diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json new file mode 100644 index 000000000..10c59121d --- /dev/null +++ b/.devcontainer/devcontainer.json @@ -0,0 +1,22 @@ +{ + "name": "coriolis-eda", + "dockerComposeFile": "../docker/ubuntu24.04/docker-compose.yml", + "service": "coriolis-eda", + "workspaceFolder": "/home/developer/coriolis-2.x", + "customizations":{ + "vscode": { + "settings":{ + "terminal.integrated.shell.linux": "/bin/bash" + }, + "extensions": [ + "ms-python.python", + "ms-python.debugpy", + "ms-python.vscode-pylance", + "donjayamanne.python-environment-manager", + "vscode.cpptools-extension-pack", + "ms-vscode.makefile-tools", + "mrmomo.meson-build" + ] + } + } +} diff --git a/.env.example b/.env.example new file mode 100644 index 000000000..f5d6ab2d9 --- /dev/null +++ b/.env.example @@ -0,0 +1,4 @@ +CMAKE_FRAMEWORK_PATH=/opt/homebrew/opt/qt@5/lib/cmake/ +PKG_CONFIG_PATH=/opt/homebrew/opt/qt@5/lib/pkgconfig:/opt/homebrew/opt/qwt-qt5/lib/pkgconfig +PYTHON3=python3.10 +VENV_PATH=${PWD}/.venv diff --git a/.gitignore b/.gitignore index ed9a4ff53..1dcc085a0 100644 --- a/.gitignore +++ b/.gitignore @@ -3,7 +3,7 @@ *.pyc *.log *.bak -.#* +*.log TAGS GTAGS @@ -12,6 +12,7 @@ GRTAGS .dir-locals.el .projectile .vscode +.venv lefdef/src/lef/lef/lef.tab.h lefdef/src/def/def/def.tab.h @@ -22,10 +23,19 @@ html/ latex/ build/ +install/ +debug/ +pkgs/ +release/ +dist/ venv/ -coriolis.egg-info/ +.venv/ +.env +*.egg-info/ .pdm-python .doit.db +.DS_Store +wheelhouse/ bootstrap/coriolis2.spec diff --git a/.gitmodules b/.gitmodules index a6280f3d0..0a905a2b2 100644 --- a/.gitmodules +++ b/.gitmodules @@ -7,3 +7,12 @@ [submodule "documentation/pelican-plugins"] path = documentation/pelican-plugins url = https://github.com/getpelican/pelican-plugins +[submodule "pdks/common/libs.tech/skywater-pdk-libs-sky130_fd_pr"] + path = pdks/common/libs.tech/skywater-pdk-libs-sky130_fd_pr + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git +[submodule "pdks/common/libs.tech/globalfoundries-pdk-libs-gf180mcu_fd_pr"] + path = pdks/common/libs.tech/globalfoundries-pdk-libs-gf180mcu_fd_pr + url = https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr.git +[submodule "pdks/common/libs.tech/IHP-Open-PDK"] + path = pdks/common/libs.tech/IHP-Open-PDK + url = https://github.com/IHP-GmbH/IHP-Open-PDK.git diff --git a/Makefile b/Makefile new file mode 100644 index 000000000..2ab7068c5 --- /dev/null +++ b/Makefile @@ -0,0 +1,70 @@ +## Main Coriolis EDA Makefile + +### Environment variables and venv setup +PYTHON3 := python3 +DIST_PATH := ./dist +VENV_PATH := .venv + +venv := . ${VENV_PATH}/bin/activate; +PIP_INSTALL := $(venv) pip3 install --upgrade +PACKAGES := pip setuptools build wheel cibuildwheel + +LOG_FILE := coriolis_eda-build.log + +.PHONY: init venv-setup coriolis_eda + +init: + @if [ ! -f .env ]; then \ + echo "Missing .env file. Copying .env.example to .env"; \ + cp .env.example .env; \ + fi + +venv-setup: init + ${PYTHON3} -m venv ${VENV_PATH} 2>&1 | tee -a $(LOG_FILE) + $(foreach pkg,$(PACKAGES),$(PIP_INSTALL) $(pkg);) + +### Coriolis EDA target +coriolis_eda: venv-setup + @echo "Building Coriolis EDA wheel package..." 2>&1 | tee -a $(LOG_FILE) + $(eval include .env) + @echo "CMAKE_FRAMEWORK_PATH=${CMAKE_FRAMEWORK_PATH}" + @echo "PKG_CONFIG_PATH=${PKG_CONFIG_PATH}" + $(venv) ${PYTHON3} -m build -w -o ${DIST_PATH} 2>&1 | tee -a $(LOG_FILE) + +### PDKs target +pdks: coriolis_eda + @make -C ./pdks all + @echo "Built all PDKs wheel packages" 2>&1 | tee -a $(LOG_FILE) + +### IPs target +ips: coriolis_eda + @make -C ./ips all + @echo "Built all IPs wheel packages" 2>&1 | tee -a $(LOG_FILE) + +### All target +all: pdks ips + @echo "Built all wheel packages" 2>&1 | tee -a $(LOG_FILE) + +### Install target +install: all + @echo "Installing all Coriolis wheel packages in ${VENV_PATH} ..." 2>&1 | tee -a $(LOG_FILE) + $(venv) pip3 install --upgrade --force-reinstall ${DIST_PATH}/*.whl + @echo "Installed all Coriolis wheel packages" 2>&1 | tee -a $(LOG_FILE) + +## Uninstall target +uninstall: + @make -C ./pdks uninstall + $(venv) pip3 uninstall -y coriolis_eda + @echo "Uninstalled all Coriolis wheel packages" 2>&1 | tee -a $(LOG_FILE) + +### Clean target +clean: + @echo "Cleaning up..." + @rm -rf ./{build,*.egg-info} + @rm -f $(LOG_FILE) + +### MrProper target +mrproper: clean + @rm -rf ${DIST_PATH} + @make -C ./pdks clean + @make -C ./ips clean diff --git a/Makefile.LIP6 b/Makefile.LIP6 index ced745404..51ec8876a 100644 --- a/Makefile.LIP6 +++ b/Makefile.LIP6 @@ -1,6 +1,6 @@ - venv = source .venv/bin/activate; + venv = . .venv/bin/activate; REGRESSION_DIR = ifneq ($(findstring nightly,$(shell pwd)),) @@ -16,6 +16,8 @@ endif ifeq ($(findstring abuild/rpmbuild,$(shell pwd)),) $(info Using LIP6 build directory tree scheme) +# PYTHON_BIN = /usr/bin/python3.11 + PYTHON_BIN = python3 SRC_DIR = ${HOME}$(REGRESSION_DIR)/coriolis-2.x/src CORIOLIS_SRC = ${SRC_DIR}/coriolis ALLIANCE_SRC = ${SRC_DIR}/alliance/alliance/src @@ -24,6 +26,7 @@ PREFIX = ${HOME}$(REGRESSION_DIR)/coriolis-2.x/$(BUILDTYPE)/install else $(info Using rpmbuild directory tree scheme) + PYTHON_BIN = python3 SRC_DIR = ${HOME}/rpmbuild/BUILD CORIOLIS_SRC = ${SRC_DIR}/coriolis-eda-2.5.5 ALLIANCE_SRC = ${SRC_DIR}/alliance/alliance/src @@ -33,6 +36,7 @@ PDM_BIN = $(CORIOLIS_SRC)/.venv/bin/pdm MESON_BIN = $(CORIOLIS_SRC)/.venv/bin/meson PELICAN_BIN = $(CORIOLIS_SRC)/.venv/bin/pelican + DOIT_BIN = $(CORIOLIS_SRC)/.venv/bin/doit @@ -71,7 +75,7 @@ check_dir: $(CORIOLIS_SRC)/.venv: - python3 -m venv .venv + $(PYTHON_BIN) -m venv .venv $(MESON_BIN): $(CORIOLIS_SRC)/.venv @@ -82,13 +86,17 @@ $(PELICAN_BIN): $(CORIOLIS_SRC)/.venv $(venv) if [ ! -x "$(PELICAN_BIN)" ]; then pip install pelican; fi +$(DOIT_BIN): $(CORIOLIS_SRC)/.venv + $(venv) if [ ! -x "$(DOIT_BIN)" ]; then pip install doit==0.33.1; fi + + ifeq ($(USE_SYSTEM_PDM),) $(PDM_BIN): $(CORIOLIS_SRC)/.venv $(venv) if [ ! -x "$(PDM_BIN)" ]; then pip install pdm; pdm install --no-self -d --plugins; fi -install_venv: $(PDM_BIN) $(MESON_BIN) $(PELICAN_BIN) +install_venv: $(PDM_BIN) $(MESON_BIN) $(PELICAN_BIN) #$(DOIT_BIN) else diff --git a/README.rst b/README.rst index 4c311c659..e673a875f 100644 --- a/README.rst +++ b/README.rst @@ -10,7 +10,6 @@ :align: center :width: 10% - ====================== Coriolis Open EDA Tool ====================== @@ -23,7 +22,7 @@ Main documentation is available at: https://coriolis.lip6.fr/ Development discussion can be found `on our Matrix Channel `_ and in our `GitHub Discussions `_. -Coriolis is part of a set of three repositories that are closely relateds. +Coriolis is one of a three repositories set that are closely related: * Alliance @@ -38,7 +37,6 @@ Coriolis is part of a set of three repositories that are closely relateds. https://github.com/lip6/alliance-check-toolkit - Purpose ======= @@ -47,7 +45,7 @@ main components are the Hurricane database, the Etesian placer and the Katana router, but other tools can use the Hurricane database and the parsers provided. -Coriolus can be used via both the ```cgt`` graphical tool `_ and via the `rich Python API `_. +Coriolus can be used via both the ``cgt`` graphical tool `_ and via the `rich Python API `_. Installation ============ @@ -66,10 +64,17 @@ Building Coriolis Most folk will only need to install using pip, but if you want to develop or need to build from scratch, read on! +Docker +====== + +A development container is provided for both development and Linux distributions specific packaging purposes. +Check out the *docker* folder and its documentation. +It gathers all three Coriolis, Alliance and Alliance Check Toolkit repositories in one comprehensive workspace. + Ubuntu/Windows WSL2 Build Environment ===================================== -If you haven't already got them, install `build-essential` and `git` +If you haven't already, install `build-essential` and `git`: .. code-block:: bash @@ -92,11 +97,10 @@ Install the build dependencies: qtbase5-dev libqt5svg5-dev libqwt-qt5-dev libbz2-dev \ rapidjson-dev libboost-all-dev libeigen3-dev libxml2-dev - Mac OSX Build Environment ========================= -To build on Mac, first install _Homebrew: https://brew.sh. Be sure to follow all the instructions it gives after install so HOMEBREW_PREFIX gets set! +To build on Mac, first install _Homebrew: https://brew.sh. Be sure to follow all the instructions it gives after install so HOMEBREW_PREFIX gets set! Clone the repo: @@ -110,9 +114,32 @@ To install the prereqisites: .. code-block:: bash - brew install ccache doxygen pelican qt@5 qwt-qt5 rapidjson boost eigen - brew install --cask mactex + brew install ccache doxygen pelican qt@5 qwt-qt5 rapidjson boost eigen binutils + brew install --cask mactex + +If required for debug, install binutils. Under MacOS > 12, libiberty is to be installed explicitly. +Modify the Brew formulae: + +.. code-block:: bash + + export HOMEBREW_NO_INSTALL_FROM_API=1 + brew tap --force homebrew/core + brew edit binutils + +Add "--enable-install-libiberty" to configuration args. Then reinstall binutils: + +.. code-block:: bash + + brew reinstall -s binutils +Both libbfd, libiberty are installed in $HOMEBREW_PREFIX/opt/binutils/bin. + +Also install X11 dependencies, we suggest using XQuartz as X11 is no longer included in MacOS: + +.. code-block:: bash + + brew install automake libtool libx11 openmotif + brew install --cask xquartz We need to set some environment variables for finding the cask only components. We use dotenv to set these in the PDM venv (see below) @@ -122,8 +149,6 @@ We need to set some environment variables for finding the cask only components. dotenv set CMAKE_FRAMEWORK_PATH "$HOMEBREW_PREFIX/opt/qt@5/lib/cmake/" dotenv set PKG_CONFIG_PATH "$HOMEBREW_PREFIX/opt/qt@5/lib/pkgconfig:$HOMEBREW_PREFIX/opt/qwt-qt5/lib/pkgconfig" - - Building Coriolis ================= @@ -149,6 +174,8 @@ Development environment For day-to-day development, its currently best to use meson and ninja directly. Currently there are `issues with using a Python editable install`_. +An automated deployment and setup of the workspace is provided, refer to the docker development container. +Manual configuration is described in the rest of this section. We use PDM_ to manage our development environment, which uses Python's venv_ system. @@ -186,14 +213,12 @@ You can also install locally using: pdm run meson setup builddir -Dpython.install_env=system pdm run ninja -C builddir install - For more configuration and install options, see: .. code-block:: bash pdm run meson configure - .. _issues with using a Python editable install: https://github.com/lip6/coriolis/issues/67 .. _venv: https://www.dataquest.io/blog/a-complete-guide-to-python-virtual-environments/#how-to-use-python-environments .. _shell completion: https://pdm.fming.dev/latest/#shell-completion @@ -226,11 +251,7 @@ You'll need the following prerequisites: * pelican * latex - - - Documentation ============= The full documentation for Coriolis can be found at http://coriolis.lip6.fr/pages/documentation.html - diff --git a/anabatic/src/AntennaProtect.cpp b/anabatic/src/AntennaProtect.cpp index c83db0555..87bf5457b 100644 --- a/anabatic/src/AntennaProtect.cpp +++ b/anabatic/src/AntennaProtect.cpp @@ -1158,9 +1158,9 @@ namespace Anabatic { cmess2 << Dots::asString ( " - Antenna gate maximum WL" , DbU::getValueString(etesian->getAntennaGateMaxWL()) ) << endl; cmess2 << Dots::asString ( " - Antenna diode maximum WL" , DbU::getValueString(etesian->getAntennaDiodeMaxWL()) ) << endl; cmess2 << Dots::asString ( " - Antenna segment maximum WL", DbU::getValueString(segmentMaxWL) ) << endl; - cmess2 << Dots::asInt ( " - Total needed diodes", total ) << endl; - cmess2 << Dots::asInt ( " - Failed to allocate" , failed ) << endl; - cmess2 << Dots::asPercentage( " - Success ratio" , (float)(total-failed)/(float)total ) << endl; + cmess1 << Dots::asInt ( " - Total needed diodes", total ) << endl; + cmess1 << Dots::asInt ( " - Failed to allocate" , failed ) << endl; + cmess1 << Dots::asPercentage( " - Success ratio" , (float)(total-failed)/(float)total ) << endl; stopMeasures(); printMeasures( "antennas" ); diff --git a/anabatic/src/AutoHorizontal.cpp b/anabatic/src/AutoHorizontal.cpp index 8ea0b6838..def5a9b4c 100644 --- a/anabatic/src/AutoHorizontal.cpp +++ b/anabatic/src/AutoHorizontal.cpp @@ -134,6 +134,11 @@ namespace Anabatic { void AutoHorizontal::setDuSource ( DbU::Unit du ) { _horizontal->setDxSource(du); + if (du > 0) + cerr << Warning( "AutoHorizontal::setDuSource(): Positive du=%s (should always be negative)\n" + " On %s" + , DbU::getValueString(du).c_str() + , getString(this).c_str() ) << endl; if (abs(du) > getPitch()) cerr << Warning( "AutoHorizontal::setDuSource(): Suspiciously big du=%s (should not exceed routing pitch %s)\n" " On %s" @@ -146,6 +151,11 @@ namespace Anabatic { void AutoHorizontal::setDuTarget ( DbU::Unit du ) { _horizontal->setDxTarget(du); + if (du < 0) + cerr << Warning( "AutoHorizontal::setDuTarget(): Negative du=%s (should always be positive)\n" + " On %s" + , DbU::getValueString(du).c_str() + , getString(this).c_str() ) << endl; if (abs(du) > getPitch()) cerr << Warning( "AutoHorizontal::setDuTarget(): Suspiciously big du=%s (should not exceed routing pitch %s)\n" " On %s" @@ -538,16 +548,16 @@ namespace Anabatic { } - void AutoHorizontal::updatePositions () - { - _sourcePosition = getSourceU() - getExtensionCap(Flags::Source); - _targetPosition = getTargetU() + getExtensionCap(Flags::Target); - if (isNonPref()) { - DbU::Unit halfCap = getExtensionCap( Flags::NoFlags ) -1; - _sourcePosition -= halfCap; - _targetPosition += halfCap; - } - } + // void AutoHorizontal::updatePositions () + // { + // _sourcePosition = getSourceU() - getExtensionCap(Flags::Source); + // _targetPosition = getTargetU() + getExtensionCap(Flags::Target); + // if (isNonPref()) { + // DbU::Unit halfCap = getExtensionCap( Flags::NoFlags ) -1; + // _sourcePosition -= halfCap; + // _targetPosition += halfCap; + // } + // } void AutoHorizontal::updateNativeConstraints () @@ -563,42 +573,42 @@ namespace Anabatic { } - bool AutoHorizontal::checkPositions () const - { - bool coherency = true; - DbU::Unit sourcePosition = _horizontal->getSource()->getX() - getExtensionCap(Flags::Source); - DbU::Unit targetPosition = _horizontal->getTarget()->getX() + getExtensionCap(Flags::Target); - if (isNonPref()) { - DbU::Unit halfCap = getExtensionCap( Flags::NoFlags ) -1; - sourcePosition -= halfCap; - targetPosition += halfCap; - } - - if ( _sourcePosition != sourcePosition ) { - cerr << "extensionCap: " << DbU::getValueString(getExtensionCap(Flags::Source)) << endl; - cerr << "ppitch: " << DbU::getValueString(getPPitch()) << endl; - cerr << "via width: " << DbU::getValueString(Session::getViaWidth(getLayer())) << endl; - cerr << Error ( "%s\n Source position incoherency: " - "shadow: %s, real: %s." - , _getString().c_str() - , DbU::getValueString(_sourcePosition).c_str() - , DbU::getValueString( sourcePosition).c_str() - ) << endl; - coherency = false; - } - - if ( _targetPosition != targetPosition ) { - cerr << Error ( "%s\n Target position incoherency: " - "shadow: %s, real: %s." - , _getString().c_str() - , DbU::getValueString(_targetPosition).c_str() - , DbU::getValueString( targetPosition).c_str() - ) << endl; - coherency = false; - } - - return coherency; - } + // bool AutoHorizontal::checkPositions () const + // { + // bool coherency = true; + // DbU::Unit sourcePosition = _horizontal->getSource()->getX() - getExtensionCap(Flags::Source); + // DbU::Unit targetPosition = _horizontal->getTarget()->getX() + getExtensionCap(Flags::Target); + // if (isNonPref()) { + // DbU::Unit halfCap = getExtensionCap( Flags::NoFlags ) -1; + // sourcePosition -= halfCap; + // targetPosition += halfCap; + // } + + // if ( _sourcePosition != sourcePosition ) { + // cerr << "extensionCap: " << DbU::getValueString(getExtensionCap(Flags::Source)) << endl; + // cerr << "ppitch: " << DbU::getValueString(getPPitch()) << endl; + // cerr << "via width: " << DbU::getValueString(Session::getViaWidth(getLayer())) << endl; + // cerr << Error ( "%s\n Source position incoherency: " + // "shadow: %s, real: %s." + // , _getString().c_str() + // , DbU::getValueString(_sourcePosition).c_str() + // , DbU::getValueString( sourcePosition).c_str() + // ) << endl; + // coherency = false; + // } + + // if ( _targetPosition != targetPosition ) { + // cerr << Error ( "%s\n Target position incoherency: " + // "shadow: %s, real: %s." + // , _getString().c_str() + // , DbU::getValueString(_targetPosition).c_str() + // , DbU::getValueString( targetPosition).c_str() + // ) << endl; + // coherency = false; + // } + + // return coherency; + // } bool AutoHorizontal::checkConstraints () const diff --git a/anabatic/src/AutoSegment.cpp b/anabatic/src/AutoSegment.cpp index 93194e1fe..498f268e4 100644 --- a/anabatic/src/AutoSegment.cpp +++ b/anabatic/src/AutoSegment.cpp @@ -25,7 +25,7 @@ #include "hurricane/Vertical.h" #include "crlcore/RoutingGauge.h" #include "anabatic/Session.h" -#include "anabatic/AutoContact.h" +#include "anabatic/AutoContactTurn.h" #include "anabatic/AutoSegment.h" #include "anabatic/AutoHorizontal.h" #include "anabatic/AutoVertical.h" @@ -789,10 +789,10 @@ namespace Anabatic { // << endl; // } if (not (flags & Flags::NoSegExt)) { - // cdebug_log(150,0) << "duSource=" << DbU::getValueString(getDuSource()) << endl; + //cdebug_log(150,0) << "duSource=" << DbU::getValueString(getDuSource()) << endl; if (-getDuSource() > cap) { cap = -getDuSource(); - // cdebug_log(150,0) << "-> Custom cap (-duSource):" << DbU::getValueString(cap) << endl; + //cdebug_log(150,0) << "-> Custom cap (-duSource):" << DbU::getValueString(cap) << endl; } } } else { @@ -923,12 +923,13 @@ namespace Anabatic { sourceAxis = getSourceU(); targetAxis = getTargetU(); + if (sourceAxis > targetAxis) std::swap( sourceAxis, targetAxis ); //if (not isNotAligned()) { - for( AutoSegment* aligned : const_cast(this)->getAligneds() ) { - sourceAxis = std::min( sourceAxis, aligned->getSourceU() ); - targetAxis = std::max( targetAxis, aligned->getTargetU() ); - } + for( AutoSegment* aligned : const_cast(this)->getAligneds() ) { + sourceAxis = std::min( sourceAxis, aligned->getSourceU() ); + targetAxis = std::max( targetAxis, aligned->getTargetU() ); + } //} } @@ -1543,6 +1544,87 @@ namespace Anabatic { } + void AutoSegment::updatePositions () + { + DbU::Unit sourceCap = getExtensionCap( Flags::Source ); + DbU::Unit targetCap = getExtensionCap( Flags::Target ); + DbU::Unit sourcePos1 = getSourceU() - sourceCap; + DbU::Unit sourcePos2 = getTargetU() - getExtensionCap( Flags::Target|Flags::NoSegExt ); + DbU::Unit targetPos1 = getTargetU() + targetCap; + DbU::Unit targetPos2 = getSourceU() + getExtensionCap( Flags::Source|Flags::NoSegExt ); + + DebugSession::open( getNet(), 145, 146 ); + cdebug_log(145,1) << "updatePositions() " << this << endl; + cdebug_log(145,0) << "sourceCap " << DbU::getValueString(sourceCap) << endl; + cdebug_log(145,0) << "targetCap " << DbU::getValueString(targetCap) << endl; + + if (sourcePos2 < sourcePos1) { + if (_sourcePosition != sourcePos2) { + if (sourcePos2 < _sourcePosition) + setFlags( SegBecomeBelowPitch ); + _sourcePosition = sourcePos2; + } + } else + _sourcePosition = sourcePos1; + + if (targetPos2 > targetPos1) { + if (_targetPosition != targetPos2) { + if (targetPos2 > _targetPosition) + setFlags( SegBecomeBelowPitch ); + _targetPosition = targetPos2; + } + } else + _targetPosition = targetPos1; + + if (isNonPref()) { + DbU::Unit halfCap = getExtensionCap( Flags::NoFlags ) - 1; + _sourcePosition -= halfCap; + _targetPosition += halfCap; + } + cdebug_log(145,-1) << "updated() " << this << endl; + DebugSession::close(); + } + + + bool AutoSegment::checkPositions () const + { + bool coherency = true; + DbU::Unit sourceU = getSourceU(); + DbU::Unit targetU = getTargetU(); + DbU::Unit sourcePosition = std::min( sourceU - getExtensionCap(Flags::Source) + , targetU - getExtensionCap(Flags::Target|Flags::NoSegExt) ); + DbU::Unit targetPosition = std::max( targetU + getExtensionCap(Flags::Target) + , sourceU + getExtensionCap(Flags::Source|Flags::NoSegExt) ); + if (isNonPref()) { + DbU::Unit halfCap = getExtensionCap( Flags::NoFlags ) - 1; + sourcePosition -= halfCap; + targetPosition += halfCap; + } + + if ( _sourcePosition != sourcePosition ) { + cerr << Error ( "%s\n Source position incoherency: " + "Shadow: %s, real: %s." + , _getString().c_str() + , DbU::getValueString(_sourcePosition).c_str() + , DbU::getValueString( sourcePosition).c_str() + ) << endl; + coherency = false; + } + + if ( _targetPosition != targetPosition ) { + cerr << Error ( "%s\n Target position incoherency: " + "Shadow: %s, real: %s." + , _getString().c_str() + , DbU::getValueString(_targetPosition).c_str() + , DbU::getValueString( targetPosition).c_str() + ) << endl; + coherency = false; + } + + return coherency; + } + + AutoSegment* AutoSegment::canonize ( Flags flags ) { cdebug_log(149,0) << "canonize() - " << this << endl; @@ -1720,7 +1802,10 @@ namespace Anabatic { cdebug_log(149,0) << "| Canonical axis length superior to P-Pitch " << this << endl; return false; } - cdebug_log(149,0) << " Length below P-Pitch." << endl; + cdebug_log(149,0) << " Length below P-Pitch (axis S:" + << DbU::getValueString(sourceAxis) << " T:" + << DbU::getValueString(targetAxis) << ")" + << endl; return true; } @@ -1799,27 +1884,27 @@ namespace Anabatic { DbU::Unit duTarget = getDuTarget(); DbU::Unit sourceCap = getExtensionCap( Flags::Source|Flags::NoSegExt|Flags::LayerCapOnly ); DbU::Unit targetCap = getExtensionCap( Flags::Target|Flags::NoSegExt|Flags::LayerCapOnly ); - DbU::Unit segLength = getTargetU() - getSourceU(); - DbU::Unit segMinLength = getAnchoredLength() + sourceCap + targetCap; + DbU::Unit segLength = getAnchoredLength(); + DbU::Unit segMinLength = segLength + sourceCap + targetCap; DbU::Unit techMinLength = getMinimalLength( Session::getLayerDepth( getLayer() )); cdebug_log(149,0) << "* Anchored length " << DbU::getValueString(getAnchoredLength()) << endl; - cdebug_log(149,0) << "* Source cap " << DbU::getValueString(sourceCap) << endl; - cdebug_log(149,0) << "* Target cap " << DbU::getValueString(targetCap) << endl; - cdebug_log(149,0) << "* duSource " << DbU::getValueString(duSource) << endl; - cdebug_log(149,0) << "* duTarget " << DbU::getValueString(duTarget) << endl; + cdebug_log(149,0) << "* Source cap " << DbU::getValueString(sourceCap) << endl; + cdebug_log(149,0) << "* Target cap " << DbU::getValueString(targetCap) << endl; + cdebug_log(149,0) << "* duSource " << DbU::getValueString(duSource) << endl; + cdebug_log(149,0) << "* duTarget " << DbU::getValueString(duTarget) << endl; if ((duSource == 0) and (duTarget == 0)) { cdebug_log(149,0) << "Already reset!" << endl; return; } - if (segLength <= techMinLength) { + if (segLength < techMinLength) { cdebug_log(149,0) << "Still at min area, do nothing." << endl; return; } - if (segMinLength > techMinLength) { + if (segMinLength >= techMinLength) { cdebug_log(149,0) << "Complete reset." << endl; setDuSource( 0 ); setDuTarget( 0 ); @@ -2377,15 +2462,6 @@ namespace Anabatic { } - bool AutoSegment::moveUpToPref ( Flags flags ) - { - size_t depth = Session::getRoutingGauge()->getLayerDepth(getLayer()); - if (not isNonPref() or (depth >= Session::getAllowedDepth())) return false; - changeDepth( depth + 1, flags|Flags::Propagate ); - return true; - } - - bool AutoSegment::moveDown ( Flags flags ) { //if ( not canPivotDown(0.0,flags) ) return false; @@ -2616,6 +2692,79 @@ namespace Anabatic { #endif + bool AutoSegment::promoteToPref ( Flags flags ) + { + cdebug_log(149,0) << "AutoVertical::promoteToPref() " << this << endl; + + if (not isNonPref()) return false; + size_t depth = Session::getRoutingGauge()->getLayerDepth( getLayer() ); + if (depth >= Session::getAllowedDepth()) return false; + + AutoContact* autoSource = getAutoSource(); + AutoContact* autoTarget = getAutoTarget(); + AutoContact* terminal = nullptr; + + unsetFlags( SegNonPref ); + if (autoSource->isTerminal()) terminal = autoSource; + if (autoTarget->isTerminal()) terminal = autoTarget; + if (not terminal) { + changeDepth( depth + 1, flags|Flags::Propagate ); + return true; + } + + Flags perpandDir = isHorizontal() ? Flags::Vertical : Flags::Horizontal; + DbU::Unit perpandAxis = isHorizontal() ? terminal->getX() : terminal->getY(); + + Layer* contactLayer = Session::getRoutingGauge()->getContactLayer( depth ); + Session::dogleg( this ); + + if (terminal == autoTarget) { + targetDetach(); + } else { + sourceDetach(); + } + + invalidate( Flags::Topology ); + terminal->invalidate( Flags::Topology ); + AutoContact* dlContact1 = AutoContactTurn::create( terminal->getGCell(), getNet(), contactLayer ); + cdebug_log(149,0) << dlContact1 << endl; + AutoSegment* segment1 = AutoSegment::create( terminal, dlContact1, perpandDir ); + cdebug_log(149,0) << segment1 << endl; + segment1->setLayer( depth ); + segment1->_setAxis( perpandAxis ); + segment1->setFlags( SegDogleg|SegSlackened|SegCanonical|SegNotAligned ); + cdebug_log(149,0) << "New " << dlContact1->base() << "." << endl; + Session::dogleg( segment1 ); + + if (terminal == autoTarget) { + targetAttach( dlContact1 ); + autoTarget->cacheAttach( segment1 ); + autoSource->invalidate( Flags::Topology ); + } else { + sourceAttach( dlContact1 ); + autoSource->cacheAttach( segment1 ); + autoTarget->invalidate( Flags::Topology ); + } + setLayer( depth+1 ); + Session::dogleg( nullptr ); + + if (isAnalog ()) segment1->setFlags( SegAnalog ); + if (isNoMoveUp()) segment1->setFlags( SegNoMoveUp ); + unsetFlags( AutoSegment::SegDrag ); + terminal ->unsetFlags( CntWeakTerminal|CntDrag ); + dlContact1->setFlags ( CntWeakTerminal ); + + cdebug_log(149,0) << "Session::dogleg[x+1] perpand: " << segment1 << endl; + cdebug_log(149,0) << "Session::dogleg[x+2] new paral: " << nullptr << endl; + cdebug_log(149,0) << "Session::dogleg[x+0] original: " << this << endl; + + dlContact1->updateCache(); + updateNativeConstraints(); + + return true; + } + + Flags AutoSegment::canDogleg ( Interval interval ) { cdebug_log(149,0) << "AutoSegment::canDogleg(Interval) " << interval << endl; @@ -2908,6 +3057,9 @@ namespace Anabatic { s.insert ( s.size()-1, sdistance ); s.insert ( s.size()-1, sblevel ); s.insert ( s.size()-1, _getStringFlags() ); + string shadowSpan = " [" + DbU::getValueString(_sourcePosition) + + ":" + DbU::getValueString(_targetPosition) + "]"; + s.insert ( s.size()-1, shadowSpan ); return s; } diff --git a/anabatic/src/AutoVertical.cpp b/anabatic/src/AutoVertical.cpp index 74dabcb6e..19836cf54 100644 --- a/anabatic/src/AutoVertical.cpp +++ b/anabatic/src/AutoVertical.cpp @@ -15,6 +15,7 @@ #include +#include "hurricane/DebugSession.h" #include "hurricane/Bug.h" #include "hurricane/Warning.h" #include "hurricane/ViaLayer.h" @@ -35,6 +36,8 @@ namespace Anabatic { using Hurricane::Error; using Hurricane::Warning; using Hurricane::ViaLayer; + using Hurricane::ViaLayer; + using Hurricane::DebugSession; // ------------------------------------------------------------------- @@ -121,6 +124,11 @@ namespace Anabatic { void AutoVertical::setDuSource ( DbU::Unit du ) { _vertical->setDySource(du); + if (du > 0) + cerr << Warning( "AutoVertical::setDuSource(): Positive du=%s (should always be negative)\n" + " On %s" + , DbU::getValueString(du).c_str() + , getString(this).c_str() ) << endl; if (abs(du) > getPitch()) cerr << Warning( "AutoVertical::setDuSource(): Suspiciously big du=%s (should not exceed routing pitch %s)\n" " On %s" @@ -133,6 +141,11 @@ namespace Anabatic { void AutoVertical::setDuTarget ( DbU::Unit du ) { _vertical->setDyTarget(du); + if (du < 0) + cerr << Warning( "AutoVertical::setDuTarget(): Negative du=%s (should always be positive)\n" + " On %s" + , DbU::getValueString(du).c_str() + , getString(this).c_str() ) << endl; if (abs(du) > getPitch()) cerr << Warning( "AutoVertical::setDuTarget(): Suspiciously big du=%s (should not exceed routing pitch %s)\n" " On %s" @@ -405,7 +418,7 @@ namespace Anabatic { void AutoVertical::updateOrient () { - if (_vertical->getTargetY() < _vertical->getSourceY()) { + if (_vertical->getTarget()->getY() < _vertical->getSource()->getY()) { cdebug_log(145,0) << "updateOrient() " << this << " (before S/T swap)" << endl; _vertical->invert(); @@ -429,41 +442,6 @@ namespace Anabatic { } - void AutoVertical::updatePositions () - { - DbU::Unit sourceCap = getExtensionCap( Flags::Source ); - DbU::Unit targetCap = getExtensionCap( Flags::Target ); - DbU::Unit sourcePos1 = getSourceU() - sourceCap; - DbU::Unit sourcePos2 = getTargetU() - targetCap; - DbU::Unit targetPos1 = getTargetU() + targetCap; - DbU::Unit targetPos2 = getSourceU() + sourceCap; - - if (sourcePos2 < sourcePos1) { - if (_sourcePosition != sourcePos2) { - if (sourcePos2 < _sourcePosition) - setFlags( SegBecomeBelowPitch ); - _sourcePosition = sourcePos2; - } - } else - _sourcePosition = sourcePos1; - - if (targetPos2 > targetPos1) { - if (_targetPosition != targetPos2) { - if (targetPos2 > _targetPosition) - setFlags( SegBecomeBelowPitch ); - _targetPosition = targetPos2; - } - } else - _targetPosition = targetPos1; - - if (isNonPref()) { - DbU::Unit halfCap = getExtensionCap( Flags::NoFlags ) - 1; - _sourcePosition -= halfCap; - _targetPosition += halfCap; - } - } - - void AutoVertical::updateNativeConstraints () { vector gcells; @@ -477,45 +455,6 @@ namespace Anabatic { } - bool AutoVertical::checkPositions () const - { - bool coherency = true; - DbU::Unit sourceCap = getExtensionCap(Flags::Source); - DbU::Unit targetCap = getExtensionCap(Flags::Target); - DbU::Unit sourceU = _vertical->getSource()->getY(); - DbU::Unit targetU = _vertical->getTarget()->getY(); - DbU::Unit sourcePosition = std::min( getSourceU() - sourceCap, getTargetU() - targetCap ); - DbU::Unit targetPosition = std::max( getTargetU() + targetCap, getSourceU() + sourceCap ); - if (isNonPref()) { - DbU::Unit halfCap = getExtensionCap( Flags::NoFlags ) - 1; - sourcePosition -= halfCap; - targetPosition += halfCap; - } - - if ( _sourcePosition != sourcePosition ) { - cerr << Error ( "%s\n Source position incoherency: " - "Shadow: %s, real: %s." - , _getString().c_str() - , DbU::getValueString(_sourcePosition).c_str() - , DbU::getValueString( sourcePosition).c_str() - ) << endl; - coherency = false; - } - - if ( _targetPosition != targetPosition ) { - cerr << Error ( "%s\n Target position incoherency: " - "Shadow: %s, real: %s." - , _getString().c_str() - , DbU::getValueString(_targetPosition).c_str() - , DbU::getValueString( targetPosition).c_str() - ) << endl; - coherency = false; - } - - return coherency; - } - - bool AutoVertical::checkConstraints () const { Interval sourceConstraints = Interval(getAutoSource()->getCBXMin(),getAutoSource()->getCBXMax()); diff --git a/anabatic/src/GCell.cpp b/anabatic/src/GCell.cpp index e154963a3..9d834c835 100644 --- a/anabatic/src/GCell.cpp +++ b/anabatic/src/GCell.cpp @@ -58,7 +58,7 @@ namespace { bool operator() ( const Axis* lhs, const Axis* rhs ) const; }; - class AxisMatch : public unary_function { + class AxisMatch { public: inline AxisMatch ( DbU::Unit axis ); inline bool operator() ( const Axis* ); @@ -1734,16 +1734,20 @@ namespace Anabatic { if (flags & Flags::AllAbove) { for ( size_t i=depth; i <= Session::getAllowedDepth() ; i += 2 ) { capacity += getCapacity( i ); - feedthroughs += _feedthroughs[i] + 0.99 + reserve; + feedthroughs += _feedthroughs[i]; + cdebug_log(149,0) << "(loop) feedthroughs=" << _feedthroughs << endl; } } else { capacity += getCapacity( depth ); - feedthroughs += _feedthroughs[depth] + 0.99 + reserve; + feedthroughs += _feedthroughs[depth]; + cdebug_log(149,0) << "feedthroughs=" << _feedthroughs << endl; } + feedthroughs += + 0.99 + reserve; cdebug_log(149,0) << " | hasFreeTrack [" << getId() << "] depth:" << depth << " " << Session::getRoutingGauge()->getRoutingLayer(depth)->getName() - << " " << feedthroughs << " vs. " << capacity + << " " << _feedthroughs[depth] << "+" << reserve + << "/" << feedthroughs << " vs. " << capacity << " " << this << endl; return (feedthroughs < capacity); diff --git a/anabatic/src/anabatic/AutoHorizontal.h b/anabatic/src/anabatic/AutoHorizontal.h index ccab6c6ea..16d20f9e1 100644 --- a/anabatic/src/anabatic/AutoHorizontal.h +++ b/anabatic/src/anabatic/AutoHorizontal.h @@ -53,14 +53,12 @@ namespace Anabatic { virtual void setDuTarget ( DbU::Unit ); virtual void _setAxis ( DbU::Unit ); virtual void updateOrient (); - virtual void updatePositions (); virtual void updateNativeConstraints (); - virtual bool checkPositions () const; virtual bool checkConstraints () const; - virtual Flags _makeDogleg ( GCell*, Flags flags ); + virtual Flags _makeDogleg ( GCell*, Flags ); virtual bool moveULeft (); virtual bool moveURight (); - virtual bool _slacken ( Flags flags ); + virtual bool _slacken ( Flags ); #if THIS_IS_DISABLED virtual void desalignate ( AutoContact* ); #endif diff --git a/anabatic/src/anabatic/AutoSegment.h b/anabatic/src/anabatic/AutoSegment.h index 2044e18a2..fac0cbe91 100644 --- a/anabatic/src/anabatic/AutoSegment.h +++ b/anabatic/src/anabatic/AutoSegment.h @@ -43,7 +43,6 @@ namespace Anabatic { using std::set; using std::cerr; using std::endl; - using std::binary_function; using Hurricane::StaticObservable; using Hurricane::BaseObserver; using Hurricane::tab; @@ -253,7 +252,7 @@ namespace Anabatic { bool canPivotUp ( float reserve=0.0, Flags flags=Flags::NoFlags ) const; bool canPivotDown ( float reserve=0.0, Flags flags=Flags::NoFlags ) const; bool canSlacken ( Flags flags=Flags::NoFlags ) const; - virtual bool checkPositions () const = 0; + virtual bool checkPositions () const; virtual bool checkConstraints () const = 0; bool checkDepthSpin () const; // Accessors. @@ -319,7 +318,7 @@ namespace Anabatic { virtual void setDuTarget ( DbU::Unit du ) = 0; void computeTerminal (); virtual void updateOrient () = 0; - virtual void updatePositions () = 0; + virtual void updatePositions (); virtual void updateNativeConstraints () = 0; void updateSourceSpin (); void updateTargetSpin (); @@ -338,6 +337,7 @@ namespace Anabatic { bool checkNotInvalidated () const; inline void setParent ( AutoSegment* ); void revalidate (); + bool promoteToPref ( Flags ); AutoSegment* makeDogleg ( AutoContact* ); Flags makeDogleg ( Interval, Flags flags=Flags::NoFlags ); Flags makeDogleg ( GCell* , Flags flags=Flags::NoFlags ); @@ -350,7 +350,6 @@ namespace Anabatic { void changeDepth ( unsigned int depth, Flags flags ); bool moveUp ( Flags flags=Flags::NoFlags ); bool moveDown ( Flags flags=Flags::NoFlags ); - bool moveUpToPref ( Flags flags=Flags::NoFlags ); bool reduceDoglegLayer (); bool bloatStackedStrap (); bool reduce ( Flags flags=Flags::WithPerpands ); @@ -435,26 +434,26 @@ namespace Anabatic { virtual void _setAxis ( DbU::Unit ) = 0; public: - struct CompareId : public binary_function { + struct CompareId { inline bool operator() ( const AutoSegment* lhs, const AutoSegment* rhs ) const; }; public: - struct CompareByDepthLength : public binary_function { + struct CompareByDepthLength { bool operator() ( AutoSegment* lhs, AutoSegment* rhs ) const; }; public: - struct CompareByDepthAxis : public binary_function { + struct CompareByDepthAxis { bool operator() ( AutoSegment* lhs, AutoSegment* rhs ) const; }; public: - struct CompareBySourceU : public binary_function { + struct CompareBySourceU { bool operator() ( AutoSegment* lhs, AutoSegment* rhs ) const; }; public: - struct CompareByRevalidate : public binary_function { + struct CompareByRevalidate { bool operator() ( AutoSegment* lhs, AutoSegment* rhs ) const; }; - struct CompareByReduceds : public binary_function { + struct CompareByReduceds { bool operator() ( AutoSegment* lhs, AutoSegment* rhs ) const; }; public: diff --git a/anabatic/src/anabatic/AutoVertical.h b/anabatic/src/anabatic/AutoVertical.h index 153a6b01d..486214123 100644 --- a/anabatic/src/anabatic/AutoVertical.h +++ b/anabatic/src/anabatic/AutoVertical.h @@ -53,14 +53,12 @@ namespace Anabatic { virtual void setDuTarget ( DbU::Unit ); virtual void _setAxis ( DbU::Unit ); virtual void updateOrient (); - virtual void updatePositions (); virtual void updateNativeConstraints (); - virtual bool checkPositions () const; virtual bool checkConstraints () const; - virtual Flags _makeDogleg ( GCell*, Flags flags ); + virtual Flags _makeDogleg ( GCell*, Flags ); virtual bool moveULeft (); virtual bool moveURight (); - virtual bool _slacken ( Flags flags ); + virtual bool _slacken ( Flags ); #if THIS_IS_DISABLED virtual void desalignate ( AutoContact* ); #endif diff --git a/anabatic/src/anabatic/GCell.h b/anabatic/src/anabatic/GCell.h index e500ab3f9..057774313 100644 --- a/anabatic/src/anabatic/GCell.h +++ b/anabatic/src/anabatic/GCell.h @@ -43,7 +43,6 @@ namespace Anabatic { using std::string; using std::vector; using std::set; - using std::binary_function; using Hurricane::StaticObservable; using Hurricane::BaseObserver; using Hurricane::Name; @@ -100,14 +99,14 @@ namespace Anabatic { Observable& operator= ( const StaticObservable& ); }; public: - class CompareByDensity : public binary_function { + class CompareByDensity { public: CompareByDensity ( size_t depth ); inline bool operator() ( GCell* lhs, GCell* rhs ) const; private: size_t _depth; }; - class CompareByKey : public binary_function { + class CompareByKey { public: inline bool operator() ( const GCell* lhs, const GCell* rhs ) const; }; diff --git a/crlcore/python/technos/common/kite.py b/crlcore/python/technos/common/kite.py index f86e0f7a6..9c2fcc56f 100644 --- a/crlcore/python/technos/common/kite.py +++ b/crlcore/python/technos/common/kite.py @@ -9,7 +9,7 @@ # | Author : Jean-Paul CHAPUT | # | E-mail : Jean-Paul.Chaput@asim.lip6.fr | # | =============================================================== | -# | Python : "./etc/common/kite.py" | +# | Python : "./etc/common/katana.py" | # +-----------------------------------------------------------------+ @@ -27,16 +27,16 @@ layout.addParameter( 'Router', 'katabatic.topRoutingLayer' , 'Top Routing Layer' , 0, 1 ) layout.addParameter( 'Router', 'anabatic.gcell.displayMode' , 'GCell Display Mode' , 1, 1 ) layout.addRule ( 'Router' ) -layout.addTitle ( 'Router', 'Kite - Detailed Router' ) -layout.addParameter( 'Router', 'kite.hTracksReservedMin' , 'Min Vert. Reserved Tracks', 0 ) -layout.addParameter( 'Router', 'kite.vTracksReservedMin' , 'Min Hor. Reserved Tracks' , 0 ) -layout.addParameter( 'Router', 'kite.hTracksReservedLocal', 'Max Vert. Reserved Tracks', 5 ) -layout.addParameter( 'Router', 'kite.vTracksReservedLocal', 'Max Hor. Reserved Tracks' , 5 ) -layout.addParameter( 'Router', 'kite.eventsLimit' , 'Events Limit' , 0 ) -layout.addParameter( 'Router', 'kite.ripupCost' , 'Ripup Cost' , 1, 1, Cfg.Parameter.Flags.UseSpinBox ) +layout.addTitle ( 'Router', 'Katana - Detailed Router' ) +layout.addParameter( 'Router', 'katana.hTracksReservedMin' , 'Min Vert. Reserved Tracks', 0 ) +layout.addParameter( 'Router', 'katana.vTracksReservedMin' , 'Min Hor. Reserved Tracks' , 0 ) +layout.addParameter( 'Router', 'katana.hTracksReservedLocal', 'Max Vert. Reserved Tracks', 5 ) +layout.addParameter( 'Router', 'katana.vTracksReservedLocal', 'Max Hor. Reserved Tracks' , 5 ) +layout.addParameter( 'Router', 'katana.eventsLimit' , 'Events Limit' , 0 ) +layout.addParameter( 'Router', 'katana.ripupCost' , 'Ripup Cost' , 1, 1, Cfg.Parameter.Flags.UseSpinBox ) layout.addSection ( 'Router', 'Ripup Limits', 1 ) -layout.addParameter( 'Router', 'kite.strapRipupLimit' , 'Straps' , 1, 1, Cfg.Parameter.Flags.UseSpinBox ) -layout.addParameter( 'Router', 'kite.localRipupLimit' , 'Locals' , 1, 1, Cfg.Parameter.Flags.UseSpinBox ) -layout.addParameter( 'Router', 'kite.globalRipupLimit' , 'Globals' , 1, 1, Cfg.Parameter.Flags.UseSpinBox ) -layout.addParameter( 'Router', 'kite.longGlobalRipupLimit', 'Long Globals', 1, 1, Cfg.Parameter.Flags.UseSpinBox ) +layout.addParameter( 'Router', 'katana.strapRipupLimit' , 'Straps' , 1, 1, Cfg.Parameter.Flags.UseSpinBox ) +layout.addParameter( 'Router', 'katana.localRipupLimit' , 'Locals' , 1, 1, Cfg.Parameter.Flags.UseSpinBox ) +layout.addParameter( 'Router', 'katana.globalRipupLimit' , 'Globals' , 1, 1, Cfg.Parameter.Flags.UseSpinBox ) +layout.addParameter( 'Router', 'katana.longGlobalRipupLimit', 'Long Globals', 1, 1, Cfg.Parameter.Flags.UseSpinBox ) layout.addRule ( 'Router' ) diff --git a/crlcore/python/technos/node180/gf180mcu_c4m/iolib.py b/crlcore/python/technos/node180/gf180mcu_c4m/iolib.py index bc10197ab..46fc41581 100644 --- a/crlcore/python/technos/node180/gf180mcu_c4m/iolib.py +++ b/crlcore/python/technos/node180/gf180mcu_c4m/iolib.py @@ -44,11 +44,12 @@ def _loadIoLib ( pdkDir ): """ Load the I/O cells from the LEF+GDS files. """ - af = AllianceFramework.get() - db = DataBase.getDB() - tech = db.getTechnology() - rootlib = db.getRootLibrary() - ioLib = Library.create( rootlib, 'iolib' ) + af = AllianceFramework.get() + db = DataBase.getDB() + tech = db.getTechnology() + rootlib = db.getRootLibrary() + ioLib = Library.create( rootlib, 'iolib' ) + ioLibGds = Library.create( ioLib , 'GDS' ) LefImport.setMergeLibrary( ioLib ) LefImport.load( (pdkDir / 'libraries' / 'gf180mcu_fd_sc_mcu9t5v0' @@ -62,7 +63,7 @@ def _loadIoLib ( pdkDir ): gdsFile = lefFile.with_suffix( '.gds' ) if gdsFile.is_file(): Gds.setTopCellName( gdsFile.stem[:-4] ) - Gds.load( ioLib, gdsFile.as_posix(), Gds.Layer_0_IsBoundary|Gds.NoBlockages ) + Gds.load( ioLibGds, gdsFile.as_posix(), Gds.Layer_0_IsBoundary|Gds.NoBlockages|Gds.LefForeign ) LefImport.load( lefFile.as_posix() ) # Demote the VDD/VSS nets until we understand how that works. for cell in ioLib.getCells(): diff --git a/crlcore/src/ccore/crlcore/Gds.h b/crlcore/src/ccore/crlcore/Gds.h index 5ad386aac..3a4161077 100644 --- a/crlcore/src/ccore/crlcore/Gds.h +++ b/crlcore/src/ccore/crlcore/Gds.h @@ -34,6 +34,7 @@ namespace CRL { static const uint32_t NoGdsPrefix = (1<<0); static const uint32_t Layer_0_IsBoundary = (1<<1); static const uint32_t NoBlockages = (1<<2); + static const uint32_t LefForeign = (1<<3); static std::string _topCellName; public: static bool save ( Cell* ); diff --git a/crlcore/src/ccore/crlcore/LefImport.h b/crlcore/src/ccore/crlcore/LefImport.h index 2045fc551..a6f378d3f 100644 --- a/crlcore/src/ccore/crlcore/LefImport.h +++ b/crlcore/src/ccore/crlcore/LefImport.h @@ -39,6 +39,7 @@ namespace CRL { static void reset (); static Hurricane::Library* load ( std::string fileName ); static void setMergeLibrary ( Hurricane::Library* ); + static void setGdsForeignLibrary ( Hurricane::Library* ); static void setGdsForeignDirectory ( std::string path ); static void setPinFilter ( DbU::Unit xThreshold, DbU::Unit yThreshold, uint32_t flags ); static Hurricane::Layer* getLayer ( std::string name); diff --git a/crlcore/src/ccore/gds/GdsDriver.cpp b/crlcore/src/ccore/gds/GdsDriver.cpp index 2b9693285..f13cf8a7e 100644 --- a/crlcore/src/ccore/gds/GdsDriver.cpp +++ b/crlcore/src/ccore/gds/GdsDriver.cpp @@ -43,6 +43,7 @@ using namespace std; #include "hurricane/Cell.h" #include "hurricane/Plug.h" #include "hurricane/Instance.h" +#include "hurricane/Library.h" using namespace Hurricane; #include "crlcore/Utilities.h" @@ -783,7 +784,6 @@ namespace { for ( Instance* instance : cell->getInstances() ) { if (instance->getMasterCell()->getName() == "control_r") continue; if (not hasLayout(instance->getMasterCell())) continue; - //cerr << "| " << getString(instance) << endl; if (instance->getPlacementStatus() == Instance::PlacementStatus::UNPLACED) continue; @@ -800,18 +800,29 @@ namespace { cdebug_log(101,0) << "Writing " << component << endl; Polygon* polygon = dynamic_cast(component); if (polygon) { - vector< vector > subpolygons; - polygon->getSubPolygons( subpolygons ); - - for ( const vector& subpolygon : subpolygons ) { + if (polygon->isPolygon45()) { for ( const BasicLayer* layer : component->getLayer()->getBasicLayers() ) { if (getString(layer->getName()).substr(0,8) == "CORIOBLK") continue; (*this) << BOUNDARY; (*this) << LAYER(layer->getGds2Layer()); (*this) << DATATYPE(layer->getGds2Datatype()); - (*this) << subpolygon; + (*this) << polygon->getPoints(); (*this) << ENDEL; } + } else { + vector< vector > subpolygons; + polygon->getSubPolygons( subpolygons ); + + for ( const vector& subpolygon : subpolygons ) { + for ( const BasicLayer* layer : component->getLayer()->getBasicLayers() ) { + if (getString(layer->getName()).substr(0,8) == "CORIOBLK") continue; + (*this) << BOUNDARY; + (*this) << LAYER(layer->getGds2Layer()); + (*this) << DATATYPE(layer->getGds2Datatype()); + (*this) << subpolygon; + (*this) << ENDEL; + } + } } } else { Rectilinear* rectilinear = dynamic_cast(component); diff --git a/crlcore/src/ccore/gds/GdsParser.cpp b/crlcore/src/ccore/gds/GdsParser.cpp index 899e5d6f1..45f81d388 100644 --- a/crlcore/src/ccore/gds/GdsParser.cpp +++ b/crlcore/src/ccore/gds/GdsParser.cpp @@ -36,6 +36,7 @@ using namespace std; #include "hurricane/Vertical.h" #include "hurricane/Diagonal.h" #include "hurricane/Rectilinear.h" +#include "hurricane/Polygon.h" #include "hurricane/Pad.h" #include "hurricane/Text.h" #include "hurricane/Net.h" @@ -658,6 +659,7 @@ namespace { static void _staticInit (); GdsStream ( string gdsPath, uint32_t flags ); Cell* getCell ( string cellName, bool create=false ); + inline bool isLefForeign () const; inline bool useGdsPrefix () const; inline bool useLayer0AsBoundary () const; inline bool isValidSyntax () const; @@ -766,6 +768,7 @@ namespace { inline bool GdsStream::isValidSyntax () const { return _validSyntax; } + inline bool GdsStream::isLefForeign () const { return (_flags & Gds::LefForeign); } inline bool GdsStream::useGdsPrefix () const { return not(_flags & Gds::NoGdsPrefix); } inline bool GdsStream::useLayer0AsBoundary () const { return (_flags & Gds::Layer_0_IsBoundary); } @@ -946,8 +949,10 @@ namespace { cdebug_log(101,1) << "GdsStream::readStructure()" << endl; if (_record.isSTRNAME()) { + cdebug_log(101,0) << "name " << _record.getName() << endl; if (_library) { string cellName = _record.getName(); + if (isLefForeign()) cellName += "_lef_foreign"; _cell = getCell( cellName, true ); _stream >> _record; } @@ -1022,7 +1027,6 @@ namespace { const Layer* layer = gdsToLayer( gdsLayer, gdsDatatype ); if ((gdsLayer == 0) and not useLayer0AsBoundary()) { - cdebug_log(101,0) << "Layer id+datatype:" << gdsLayer << "+" << gdsDatatype << " " << layer << endl; if (not layer) { cerr << Error( "GdsStream::readLayerAndDatatype(): No BasicLayer id:%d+%d in GDS conversion table (skipped)." , gdsLayer, gdsDatatype @@ -1031,6 +1035,7 @@ namespace { } isBoundary = (not layer and (gdsLayer == 0) and useLayer0AsBoundary()); + cdebug_log(101,0) << "Layer id+datatype:" << gdsLayer << "+" << gdsDatatype << " " << layer << endl; cdebug_tabw(101,-1); return layer; } @@ -1197,9 +1202,12 @@ namespace { else if (not layer and useLayer0AsBoundary()) { xyToAbutmentBox(); } - else + else { + cdebug_log(101,0) << "Cannot translate XY RECORD, missing Cell or Layer" << endl; _stream >> _record; + } } else { + cdebug_log(101,0) << "Unsupported RECORD type " << _record.getName() << endl; _validSyntax = false; cdebug_tabw(101,-1); return _validSyntax; @@ -1274,6 +1282,7 @@ namespace { if (_record.isSNAME()) { masterName = _record.getName(); + if (isLefForeign()) masterName += "_lef_foreign"; _stream >> _record; } else { _validSyntax = false; @@ -1308,6 +1317,17 @@ namespace { return _validSyntax; } + while (_record.getType() == GdsRecord::PROPATTR) { + _stream >> _record; + if (_record.isPROPVALUE()) { _stream >> _record; } + else { + cdebug_log(101,1) << "Missing PROPVALUE" << endl; + _validSyntax = false; + cdebug_tabw(101,-1); + return _validSyntax; + } + } + if (not masterName.empty()) { Transformation::Orientation orient = Transformation::Orientation::ID; if (_angle == 90.0) orient = Transformation::Orientation::R1; @@ -1330,10 +1350,10 @@ namespace { } } - // cerr << "Delayed Instance: " << masterName - // << " XR:" << _xReflection << " angle:" << _angle - // << " " << Transformation(xpos,ypos,orient) - // << " in " << _cell << endl; + cdebug_log(101,0) << "Delayed Instance: " << masterName + << " XR:" << _xReflection << " angle:" << _angle + << " " << Transformation(xpos,ypos,orient) + << " in " << _cell << endl; _delayedInstances.push_back( DelayedInstance( _cell , masterName , Transformation(xpos,ypos,orient)) ); @@ -1574,6 +1594,8 @@ namespace { void GdsStream::xyToAbutmentBox () { + cdebug_log(101,1) << "GdsStream::xyToAbutmetBox()" << endl; + DbU::Unit oneGrid = DbU::fromGrid( 1 ); vector points; @@ -1582,8 +1604,8 @@ namespace { for ( size_t i=0 ; i> _record; + while ( _record.getType() == GdsRecord::PROPATTR) { + _stream >> _record; + if (_record.isPROPVALUE()) { _stream >> _record; } + else { + cdebug_log(101,1) << "Missing PROPVALUE" << endl; + _validSyntax = false; + cdebug_tabw(101,-1); + return; + } + } if ( (_record.getType() == GdsRecord::ENDEL) or (_record.getType() == GdsRecord::STRING)) { //_stream >> _record; } else { + cdebug_log(101,1) << "Missing ENDEL or STRING" << endl; _validSyntax = false; + cdebug_tabw(101,-1); return; } @@ -1633,21 +1668,26 @@ namespace { _cell->setAbutmentBox( ab ); cdebug_log(101,0) << "| Abutment box =" << ab << endl; } + + cdebug_tabw(101,-1); } void GdsStream::xyToComponent ( const Layer* layer ) { + cdebug_log(101,1) << "GdsStream::xyToAbutmetBox()" << endl; + DbU::Unit oneGrid = DbU::fromGrid( 1 ); vector points; vector coordinates = _record.getInt32s(); vector offgrids; + bool isRectilinear = true; for ( size_t i=0 ; igetName()).c_str() , DbU::getValueString(oneGrid).c_str() , m.str().c_str() ) << endl; } _stream >> _record; + while ( _record.getType() == GdsRecord::PROPATTR) { + _stream >> _record; + if (_record.isPROPVALUE()) { _stream >> _record; } + else { + cdebug_log(101,1) << "Missing PROPVALUE" << endl; + _validSyntax = false; + cdebug_tabw(101,-1); + return; + } + } if ( (_record.getType() == GdsRecord::ENDEL) or (_record.getType() == GdsRecord::STRING)) { //_stream >> _record; } else { _validSyntax = false; + cdebug_tabw(101,-1); return; } @@ -1696,8 +1748,10 @@ namespace { } else _skipENDEL = true; - if (layer->isBlockage() and (_flags & Gds::NoBlockages)) + if (layer->isBlockage() and (_flags & Gds::NoBlockages)) { + cdebug_tabw(101,-1); return; + } if (not net) net = fusedNet(); @@ -1716,13 +1770,18 @@ namespace { for ( Point p : points ) boundingBox.merge( p ); _component = Pad::create( net, layer, boundingBox ); } else { - _component = Rectilinear::create( net, layer, points ); + if (isRectilinear) + _component = Rectilinear::create( net, layer, points ); + else + _component = Polygon::create( net, layer, points ); } // cdebug_log(101,0) << "| " << net->getCell() << endl; cdebug_log(101,0) << "| " << _component << endl; if (not net->isAutomatic()) NetExternalComponents::setExternal( _component ); } + + cdebug_tabw(101,-1); } @@ -1754,6 +1813,16 @@ namespace { points.push_back( Point( coordinates[i ]*_scale , coordinates[i+1]*_scale ) ); _stream >> _record; + while ( _record.getType() == GdsRecord::PROPATTR) { + _stream >> _record; + if (_record.isPROPVALUE()) { _stream >> _record; } + else { + cdebug_log(101,1) << "Missing PROPVALUE" << endl; + _validSyntax = false; + cdebug_tabw(101,-1); + return; + } + } if (_record.getType() != GdsRecord::ENDEL) { _validSyntax = false; return; @@ -1887,6 +1956,7 @@ namespace { cdebug_log(101,1) << "GdsStream::makeInstances(): " << endl; for ( const DelayedInstance& di : _delayedInstances ) { + cdebug_log(101,0) << "> " << di._masterName << " @" << di._transformation << " in " << di._owner << endl; Cell* masterCell = getCell( di._masterName ); if (masterCell) { @@ -2038,7 +2108,8 @@ namespace CRL { bool Gds::load ( Library* library, string gdsPath, uint32_t flags ) { - //DebugSession::open( 101, 110 ); + // if (library->getName() == "working") + // DebugSession::open( 101, 110 ); UpdateSession::open(); Contact::disableCheckMinSize(); @@ -2053,7 +2124,8 @@ namespace CRL { Contact::enableCheckMinSize(); UpdateSession::close(); Gds::setTopCellName( "" ); - //DebugSession::close(); + // if (library->getName() == "working") + // DebugSession::close(); return true; } diff --git a/crlcore/src/ccore/lefdef/DefDriver.cpp b/crlcore/src/ccore/lefdef/DefDriver.cpp index 9d2dc54aa..683c57a39 100644 --- a/crlcore/src/ccore/lefdef/DefDriver.cpp +++ b/crlcore/src/ccore/lefdef/DefDriver.cpp @@ -104,7 +104,7 @@ namespace CRL { typedef list NetList; -struct LessNet : public binary_function { +struct LessNet { bool operator () ( Net* net1, Net* net2 ); }; diff --git a/crlcore/src/ccore/lefdef/LefImport.cpp b/crlcore/src/ccore/lefdef/LefImport.cpp index 469980d60..e84111bb0 100644 --- a/crlcore/src/ccore/lefdef/LefImport.cpp +++ b/crlcore/src/ccore/lefdef/LefImport.cpp @@ -126,6 +126,8 @@ namespace { public: static void setMergeLibrary ( Library* ); static void setGdsForeignDirectory ( string ); + static void setGdsForeignLibrary ( Library* ); + static Library* getGdsForeignLibrary (); static void setPinFilter ( DbU::Unit xThreshold, DbU::Unit yThreshold, uint32_t flags ); static DbU::Unit fromLefUnits ( int ); static Layer* getLayer ( string ); @@ -142,6 +144,9 @@ namespace { Net* earlyGetNet ( string name ); inline string getLibraryName () const; inline Library* getLibrary ( bool create=false ); + inline const Point& getOrigin () const; + inline DbU::Unit getOriginX () const; + inline DbU::Unit getOriginY () const; inline string getForeignPath () const; inline void setForeignPath ( string ); inline const Point& getForeignPosition () const; @@ -156,6 +161,7 @@ namespace { inline void setCellGauge ( CellGauge* ); inline Net* getNet () const; inline void setNet ( Net* ); + inline void setOrigin ( DbU::Unit x, DbU::Unit y ); static void setCoreSite ( DbU::Unit x, DbU::Unit y ); static DbU::Unit getCoreSiteX (); static DbU::Unit getCoreSiteY (); @@ -191,6 +197,7 @@ namespace { private: static string _gdsForeignDirectory; static Library* _mergeLibrary; + static Library* _gdsForeignLibrary; static PinRectilinearFilter _pinFilter; string _file; string _libraryName; @@ -200,6 +207,7 @@ namespace { Net* _gdsPower; Net* _gdsGround; Cell* _cell; + Point _origin; Net* _net; string _busBits; double _unitsMicrons; @@ -224,6 +232,10 @@ namespace { inline Library* LefParser::getLibrary ( bool create ) { if (not _library and create) createLibrary(); return _library; } inline Cell* LefParser::getCell () const { return _cell; } inline void LefParser::setCell ( Cell* cell ) { _cell=cell; } + inline const Point& LefParser::getOrigin () const { return _origin; } + inline DbU::Unit LefParser::getOriginX () const { return _origin.getX(); } + inline DbU::Unit LefParser::getOriginY () const { return _origin.getY(); } + inline void LefParser::setOrigin ( DbU::Unit x, DbU::Unit y ) { _origin=Point(x,y); } inline string LefParser::getForeignPath () const { return _foreignPath; } inline void LefParser::setForeignPath ( string path ) { _foreignPath=path; } inline const Point& LefParser::getForeignPosition () const { return _foreignPosition; } @@ -269,7 +281,8 @@ namespace { string LefParser::_gdsForeignDirectory = ""; - Library* LefParser::_mergeLibrary = nullptr; + Library* LefParser::_gdsForeignLibrary = nullptr; + Library* LefParser::_mergeLibrary = nullptr; PinRectilinearFilter LefParser::_pinFilter; map LefParser::_layerLut; DbU::Unit LefParser::_coreSiteX = 0; @@ -284,6 +297,14 @@ namespace { { _gdsForeignDirectory = path; } + void LefParser::setGdsForeignLibrary ( Library* library ) + { _gdsForeignLibrary = library; } + + + Library* LefParser::getGdsForeignLibrary () + { return _gdsForeignLibrary; } + + void LefParser::setPinFilter ( DbU::Unit xThreshold, DbU::Unit yThreshold, uint32_t flags ) { _pinFilter.setXThreshold( xThreshold ); @@ -341,6 +362,7 @@ namespace { , _gdsPower (nullptr) , _gdsGround (nullptr) , _cell (nullptr) + , _origin () , _net (nullptr) , _busBits ("()") , _unitsMicrons (0.01) @@ -351,7 +373,7 @@ namespace { , _nthRouting (0) , _routingGauge (nullptr) , _cellGauge (nullptr) - , _minTerminalWidth(Cfg::getParamInt("lefImport.minTerminalWidth",0)->asInt()) + , _minTerminalWidth(DbU::fromMicrons( Cfg::getParamDouble("lefImport.minTerminalWidth",0)->asDouble() )) { _routingGauge = AllianceFramework::get()->getRoutingGauge(); _cellGauge = AllianceFramework::get()->getCellGauge(); @@ -603,10 +625,14 @@ namespace { { LefParser* parser = (LefParser*)ud; - bool created = false; - Cell* cell = parser->earlyGetCell( created, foreign->cellName() ); + bool created = false; + string cellName = string(foreign->cellName()) + "_lef_foreign"; + Cell* cell = parser->earlyGetCell( created, cellName ); - if (created) { + // parser->setForeignPosition( Point( parser->fromUnitsMicrons( - foreign->px() ) + // , parser->fromUnitsMicrons( - foreign->py() ))); + + if (not created) { if (_gdsForeignDirectory.empty()) { cerr << Warning( "LefParser::_macroForeignCbk(): GDS directory *not* set, ignoring FOREIGN statement." ) << endl; return 0; @@ -618,22 +644,36 @@ namespace { Gds::setTopCellName( foreign->cellName() ); Gds::load( parser->getLibrary(), parser->getForeignPath() , Gds::NoBlockages|Gds::Layer_0_IsBoundary); - } - - parser->setForeignPosition( Point( parser->fromUnitsMicrons( foreign->px() ) - , parser->fromUnitsMicrons( foreign->px() ))); - for ( Net* net : cell->getNets() ) { - if (net->isPower ()) parser->setGdsPower ( net ); - if (net->isGround()) parser->setGdsGround( net ); - if (parser->getForeignPosition() != Point(0,0)) { - for ( Component* component : net->getComponents() ) { - component->translate( parser->getForeignPosition().getX() - , parser->getForeignPosition().getY() ); + for ( Net* net : cell->getNets() ) { + if (net->isPower ()) parser->setGdsPower ( net ); + if (net->isGround()) parser->setGdsGround( net ); + if (parser->getForeignPosition() != Point(0,0)) { + for ( Component* component : net->getComponents() ) { + component->translate( parser->getForeignPosition().getX() + , parser->getForeignPosition().getY() ); + } } } + + return 0; + } + + if (not _gdsForeignLibrary) { + cerr << Warning( "LefParser::_macroForeignCbk(): GDS foreign library *not* set, ignoring FOREIGN statement." ) << endl; + return 0; + } + Cell* gdsCell = _gdsForeignLibrary->getCell( cellName ); + if (not gdsCell) { + cerr << Warning( "LefParser::_macroForeignCbk(): GDS foreign cell *not* found in library." ) << endl; + return 0; } + Instance::create( cell, "foreign" + , gdsCell + , Transformation( parser->getForeignPosition() ) + , Instance::PlacementStatus::FIXED ); + return 0; } @@ -652,7 +692,7 @@ namespace { blockageNet->setType( Net::Type::BLOCKAGE ); } - //cerr << " @ _obstructionCbk: " << blockageNet->getName() << endl; + cdebug_log(100,1) << "@ LefParser::_obstructionCbk: " << blockageNet->getName() << endl; lefiGeometries* geoms = obstruction->geometries(); for ( int igeom=0 ; igeom < geoms->numItems() ; ++ igeom ) { @@ -723,6 +763,13 @@ namespace { , parser->fromUnitsMicrons( r->yh ) ); } + cdebug_log(100,0) << "xl=" << DbU::getValueString(xl) + << " xh=" << DbU::getValueString(xh) + << " w=" << DbU::getValueString(w) + << " h=" << DbU::getValueString(h) + << " Ox=" << DbU::getValueString(parser->getOriginX()) + << " Oy=" << DbU::getValueString(parser->getOriginY()) + << endl; } cdebug_log(100,0) << "| " << segment << endl; } @@ -741,12 +788,15 @@ namespace { } } + cdebug_tabw(100,-1); return 0; } int LefParser::_macroCbk ( lefrCallbackType_e c, lefiMacro* macro, lefiUserData ud ) { + cdebug_log(100,1) << "@ LefParser::_macroCbk()" << endl; + AllianceFramework* af = AllianceFramework::get(); LefParser* parser = (LefParser*)ud; @@ -758,6 +808,11 @@ namespace { DbU::Unit height = 0; Cell* cell = parser->earlyGetCell( created ); + parser->setOrigin( parser->fromUnitsMicrons( - macro->originX() ) + , parser->fromUnitsMicrons( - macro->originY() )); + cdebug_log(100,0) << "Macro: " << cellName << endl; + cdebug_log(100,0) << "Origin: " << parser->getOrigin() << endl; + if (cell->getName() != Name(cellName)) { cell->setName( cellName ); } @@ -765,9 +820,16 @@ namespace { if (macro->hasSize()) { width = parser->fromUnitsMicrons( macro->sizeX() ); height = parser->fromUnitsMicrons( macro->sizeY() ); - cell->setAbutmentBox( Box( 0, 0, width, height ) ); + cell->setAbutmentBox( Box( 0, 0, width, height ).translate( parser->getOrigin() )); + cdebug_log(100,0) << "AB " << cell->getAbutmentBox() << endl; } + // for ( Net* net : cell->getNets() ) { + // for ( Component* component : net->getComponents() ) { + // component->translate( parser->getOrigin() ); + // } + // } + bool isPad = false; string gaugeName = "Unknown SITE"; if (macro->hasSiteName()) { @@ -793,9 +855,9 @@ namespace { else parser->_pinPadPostProcess(); parser->clearPinComponents(); - cerr << " o " << cellName - << " " << DbU::getValueString(width) << " " << DbU::getValueString(height) - << " " << gaugeName; + cmess2 << " o " << cellName + << " " << DbU::getValueString(width) << " " << DbU::getValueString(height) + << " " << gaugeName; if (isPad) cerr << " (PAD)"; cerr << endl; @@ -809,7 +871,9 @@ namespace { parser->setCell ( nullptr ); parser->setGdsPower ( nullptr ); parser->setGdsGround( nullptr ); + parser->setOrigin ( 0, 0 ); + cdebug_tabw(100,-1); return 0; } @@ -827,7 +891,7 @@ namespace { //if (parser->getCell()->getName() == "NAND2B_X2_GF6T_1P5") if (parser->getCell()->getName() == "AOI222_X2_GF6T_1P5") DebugSession::open( 100, 110 ); - cdebug_log(100,1) << "@ _pinCbk()" << endl; + cdebug_log(100,1) << "@ LefParser::_pinCbk()" << endl; bool created = false; parser->earlyGetCell( created ); @@ -898,6 +962,13 @@ namespace { float formFactor = (float)w / (float)h; const RoutingLayerGauge* gauge = parser->getRoutingGauge()->getLayerGauge( layer ); + cdebug_log(100,0) << "xl=" << DbU::getValueString(xl) + << " xh=" << DbU::getValueString(xh) + << " yl=" << DbU::getValueString(yl) + << " yh=" << DbU::getValueString(yh) + << " Ox=" << DbU::getValueString(parser->getOriginX()) + << " Oy=" << DbU::getValueString(parser->getOriginY()) + << endl; cdebug_log(100,0) << "formFactor=" << formFactor << " h=" << DbU::getValueString(h) << " (> " << DbU::getValueString(parser->getMinTerminalWidth()) << ")" @@ -999,7 +1070,7 @@ namespace { //if (_cell->getName() == "MXI2_X1_GF6T_1P5") if (_cell->getName() == "AOI222_X2_GF6T_1P5") DebugSession::open( 100, 110 ); - cdebug_log(100,1) << "@ _pinStdPostProcess" << endl; + cdebug_log(100,1) << "LefParser::_pinStdPostProcess" << endl; for ( auto element : _pinComponents ) { string pinName = element.first; @@ -1220,6 +1291,8 @@ namespace { void LefParser::_pinPadPostProcess () { + cdebug_log(100,1) << "@ LefParser::_pinPadPostProcess()" << endl; + Box ab = getCell()->getAbutmentBox(); bool isCornerPad = (_cellGauge) and (_cellGauge->getSliceHeight() == _cellGauge->getSliceStep()); @@ -1310,6 +1383,8 @@ namespace { , vspan.getVMin() , ab.getYMax() ); + cdebug_log(100,0) << "| Native " << segments[i] << endl; + cdebug_log(100,0) << "| cap North " << capSegment << endl; break; } } @@ -1321,6 +1396,7 @@ namespace { } } } + cdebug_tabw(100,-1); } @@ -1354,6 +1430,9 @@ namespace { string libraryName = file.substr( islash, file.size()-4-islash ); unique_ptr parser ( new LefParser(file,libraryName) ); + // if (libraryName == "sg13g2_io") + // DebugSession::open( 100, 110 ); + FILE* lefStream = fopen( file.c_str(), "r" ); if (not lefStream) throw Error( "LefImport::load(): Cannot open LEF file \"%s\".", file.c_str() ); @@ -1362,6 +1441,8 @@ namespace { lefrRead( lefStream, file.c_str(), (lefiUserData)parser.get() ); fclose( lefStream ); + // if (libraryName == "sg13g2_io") + // DebugSession::close(); if (not parser->getCellGauge()) { cerr << Warning( "LefParser::parse(): No default Alliance cell gauge, unable to check the Cell gauge." ) << endl; @@ -1382,6 +1463,7 @@ namespace { return parser->getLibrary(); } + } // Anonymous namespace. #endif // HAVE_LEFDEF @@ -1431,6 +1513,14 @@ namespace CRL { } + void LefImport::setGdsForeignLibrary ( Library* library ) + { +#if defined(HAVE_LEFDEF) + LefParser::setGdsForeignLibrary( library ); +#endif + } + + void LefImport::setGdsForeignDirectory ( string path ) { #if defined(HAVE_LEFDEF) @@ -1446,6 +1536,7 @@ namespace CRL { #endif } + Layer* LefImport::getLayer ( string name ) { #if defined(HAVE_LEFDEF) @@ -1455,6 +1546,7 @@ namespace CRL { #endif } + void LefImport::addLayer ( string name, Layer* layer ) { #if defined(HAVE_LEFDEF) @@ -1462,10 +1554,13 @@ namespace CRL { #endif } + void LefImport::clearLayer ( string name ) { #if defined(HAVE_LEFDEF) LefParser::clearLayer( name ); #endif } + + } // CRL namespace. diff --git a/crlcore/src/ccore/liberty/LibertyTechnology.h b/crlcore/src/ccore/liberty/LibertyTechnology.h index e012b6230..e0f561e2e 100644 --- a/crlcore/src/ccore/liberty/LibertyTechnology.h +++ b/crlcore/src/ccore/liberty/LibertyTechnology.h @@ -71,8 +71,8 @@ class CLibertyTechnology : public PrivateProperty { }; - public: struct TemplateComp : public binary_function { - // ********************************************************************************************************** + public: struct TemplateComp { + // ************************** public:bool operator() (const CLuTableTemplate* t1,const CLuTableTemplate* t2) const { diff --git a/crlcore/src/pyCRL/PyGds.cpp b/crlcore/src/pyCRL/PyGds.cpp index b7e4c4401..1b6df4e45 100644 --- a/crlcore/src/pyCRL/PyGds.cpp +++ b/crlcore/src/pyCRL/PyGds.cpp @@ -155,6 +155,7 @@ extern "C" { PyObject* constant; LoadObjectConstant(PyTypeGds.tp_dict,Gds::NoGdsPrefix ,"NoGdsPrefix"); LoadObjectConstant(PyTypeGds.tp_dict,Gds::NoBlockages ,"NoBlockages"); + LoadObjectConstant(PyTypeGds.tp_dict,Gds::LefForeign ,"LefForeign"); LoadObjectConstant(PyTypeGds.tp_dict,Gds::Layer_0_IsBoundary,"Layer_0_IsBoundary"); } diff --git a/crlcore/src/pyCRL/PyLefImport.cpp b/crlcore/src/pyCRL/PyLefImport.cpp index 26506dc93..e4286b9a9 100644 --- a/crlcore/src/pyCRL/PyLefImport.cpp +++ b/crlcore/src/pyCRL/PyLefImport.cpp @@ -116,6 +116,27 @@ extern "C" { } + static PyObject* PyLefImport_setGdsForeignLibrary ( PyObject*, PyObject* args ) + { + cdebug_log(30,0) << "PyLefImport_setGdsForeignLibrary()" << endl; + HTRY + PyObject* pyLibrary = NULL; + if (PyArg_ParseTuple( args, "O:LefImport.setGdsForeignLibrary", &pyLibrary )) { + if (IsPyLibrary(pyLibrary)) { + LefImport::setGdsForeignLibrary( PYLIBRARY_O(pyLibrary) ); + } else { + PyErr_SetString( ConstructorError, "LefImport.setGdsForeignLibrary(): Bad parameter type (not a Library)." ); + return NULL; + } + } else { + PyErr_SetString( ConstructorError, "LefImport.setGdsForeignLibrary(): Bad number of parameters." ); + return NULL; + } + HCATCH + Py_RETURN_NONE; + } + + static PyObject* PyLefImport_setGdsForeignDirectory ( PyObject*, PyObject* args ) { cdebug_log(30,0) << "PyLefImport_setGdsForeignDirectory()" << endl; @@ -212,6 +233,8 @@ extern "C" { , "Load a complete Cadence LEF library." } , { "reset" , (PyCFunction)PyLefImport_reset , METH_NOARGS|METH_STATIC , "Reset the Cadence LEF parser (clear technology)." } + , { "setGdsForeignLibrary" , (PyCFunction)PyLefImport_setGdsForeignLibrary , METH_VARARGS|METH_STATIC + , "Sets the library from which FOREIGN GDS cells will be searched." } , { "setMergeLibrary" , (PyCFunction)PyLefImport_setMergeLibrary , METH_VARARGS|METH_STATIC , "Merge into this library instead of creating a new one." } , { "setGdsForeignDirectory", (PyCFunction)PyLefImport_setGdsForeignDirectory, METH_VARARGS|METH_STATIC diff --git a/cumulus/src/designflow/alias.py b/cumulus/src/designflow/alias.py index b19fcacdb..402a7ab72 100644 --- a/cumulus/src/designflow/alias.py +++ b/cumulus/src/designflow/alias.py @@ -31,7 +31,7 @@ def __repr__ ( self ): def doTask ( self ): return True - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/asimut.py b/cumulus/src/designflow/asimut.py index 44c11818f..f07edf967 100644 --- a/cumulus/src/designflow/asimut.py +++ b/cumulus/src/designflow/asimut.py @@ -48,7 +48,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Asimut.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/blif2vst.py b/cumulus/src/designflow/blif2vst.py index 3690d6c4f..cec90159d 100644 --- a/cumulus/src/designflow/blif2vst.py +++ b/cumulus/src/designflow/blif2vst.py @@ -44,8 +44,6 @@ def __init__ ( self, rule, targets, depends, flags ): self.addClean( self.targets ) def __repr__ ( self ): - for d in self.file_dep: - print( d ) return '' \ .format( self.design, ','.join([f.as_posix() for f in self.file_dep]) ) @@ -61,7 +59,6 @@ def doTask ( self ): from ..helpers.io import ErrorMessage from ..plugins import rsave - print( 'Blif2Vst.doTask() on "{}"'.format( self.design )) views = CRL.Catalog.State.Logical | self.flags cell = CRL.Blif.load( self.file_depend().as_posix() ) if cell.getName() == 'top': @@ -76,13 +73,14 @@ def doTask ( self ): return self.checkTargets( 'Blif2Vst.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): if self.design: doc = 'Run {}.'.format( self ) else: doc = 'Run plain CGT (no loaded design)' - return { 'basename' : self.basename + params = { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : doc , 'targets' : self.targets , 'file_dep' : self.file_dep } + return params diff --git a/cumulus/src/designflow/boog.py b/cumulus/src/designflow/boog.py index 8e477c3d2..7ea7839a8 100644 --- a/cumulus/src/designflow/boog.py +++ b/cumulus/src/designflow/boog.py @@ -59,7 +59,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Boog.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/boom.py b/cumulus/src/designflow/boom.py index a90c27fab..0389399c6 100644 --- a/cumulus/src/designflow/boom.py +++ b/cumulus/src/designflow/boom.py @@ -51,7 +51,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Boom.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/clean.py b/cumulus/src/designflow/clean.py index 88134d3ba..4631bb65a 100644 --- a/cumulus/src/designflow/clean.py +++ b/cumulus/src/designflow/clean.py @@ -53,7 +53,7 @@ def doTask ( self, doExtrasClean ): filePath.unlink() return True - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Clean all generated (targets) files.' diff --git a/cumulus/src/designflow/command.py b/cumulus/src/designflow/command.py index 6f3aab206..d683461f8 100644 --- a/cumulus/src/designflow/command.py +++ b/cumulus/src/designflow/command.py @@ -33,7 +33,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Command.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/copy.py b/cumulus/src/designflow/copy.py index 564eb2e4c..f87448489 100644 --- a/cumulus/src/designflow/copy.py +++ b/cumulus/src/designflow/copy.py @@ -34,7 +34,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Copy.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : 'copy_' + self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/cougar.py b/cumulus/src/designflow/cougar.py index 39d220819..e8aa8301f 100644 --- a/cumulus/src/designflow/cougar.py +++ b/cumulus/src/designflow/cougar.py @@ -57,7 +57,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Cougar.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/dreal.py b/cumulus/src/designflow/dreal.py index d680ab90e..dd97ef065 100644 --- a/cumulus/src/designflow/dreal.py +++ b/cumulus/src/designflow/dreal.py @@ -49,7 +49,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Dreal.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/druc.py b/cumulus/src/designflow/druc.py index 87715c741..461beaf90 100644 --- a/cumulus/src/designflow/druc.py +++ b/cumulus/src/designflow/druc.py @@ -44,7 +44,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Druc.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/flatph.py b/cumulus/src/designflow/flatph.py index 438324886..4ee2998cf 100644 --- a/cumulus/src/designflow/flatph.py +++ b/cumulus/src/designflow/flatph.py @@ -51,7 +51,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Flatph.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/genpat.py b/cumulus/src/designflow/genpat.py index 97dba66b4..a705e6e3e 100644 --- a/cumulus/src/designflow/genpat.py +++ b/cumulus/src/designflow/genpat.py @@ -39,7 +39,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Genpat.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/graal.py b/cumulus/src/designflow/graal.py index fd10e1df3..c34156692 100644 --- a/cumulus/src/designflow/graal.py +++ b/cumulus/src/designflow/graal.py @@ -49,7 +49,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Graal.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/klayout.py b/cumulus/src/designflow/klayout.py index 829f9cea4..00c950003 100644 --- a/cumulus/src/designflow/klayout.py +++ b/cumulus/src/designflow/klayout.py @@ -8,25 +8,55 @@ class MissingTarget ( Exception ): pass class BadDrcRules ( Exception ): pass +class BadLypFile ( Exception ): pass class Klayout ( FlowTask ): Verbose = 0x0001 + _lypFile = None + @staticmethod - def mkRule ( rule, targets=[], depends=[], script=None, variables={}, flags=0 ): - return Klayout( rule, targets, depends, script, variables, flags ) + def setLypFile (lypFile ): + if isinstance(lypFile,Path): pass + elif isinstance(lypFile,str): lypFile = Path( lypFile ) + else: + raise BadLypFile( '[ERROR] Klayout.setLypFile(): Should be or ({})' \ + .format( lypFile )) + if not lypFile.is_file(): + raise BadLypFile( '[ERROR] Klayout.setLypFile(): File not found "{}"' \ + .format( lypFile )) + Klayout._lypFile = lypFile - def __init__ ( self, rule, targets, depends, script, variables, flags ): - depends.insert( 0, script ) + @staticmethod + def mkRule ( rule, targets=[], depends=[], script=None, arguments=[], variables={}, flags=0 ): + return Klayout( rule, targets, depends, script, arguments, variables, flags ) + + def __init__ ( self, rule, targets, depends, script, arguments, variables, flags ): + if script and not isinstance(script,Path): + script = Path( script ) + if script: + depends.append( script ) super().__init__( rule, targets, depends ) - self.flags = flags - self.variable = variables - self.command = [ 'klayout' ] + self.flags = flags + self.arguments = arguments + self.variable = variables + self.command = [ 'klayout' ] + arguments + if Klayout._lypFile: + self.command += [ '-l', Klayout._lypFile.as_posix() ] for name, value in variables.items(): - self.command += [ '-rd', '{}={}'.format(name,value) ] - self.command += [ '-b', '-r', self.file_depend(0).as_posix() ] + if value is None: + self.command += [ '-rd', '{}'.format(name) ] + else: + self.command += [ '-rd', '{}={}'.format(name,value) ] + if script: + self.command += [ '-r', script.as_posix() ] + if self.file_depend(0) and not (self.file_depend(0) == script): + self.command += [ self.file_depend(0).as_posix() ] +# else: +# if self.file_target(0): +# self.command += [ self.file_target(0).as_posix() ] self.addClean( self.targets ) def __repr__ ( self ): @@ -35,6 +65,8 @@ def __repr__ ( self ): def doTask ( self ): from ..helpers.io import ErrorMessage + shellEnv = ShellEnv() + shellEnv.export() state = subprocess.run( self.command ) if state.returncode: e = ErrorMessage( 1, 'Klayout.doTask(): UNIX command failed ({}).' \ @@ -42,7 +74,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Klayout.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) @@ -74,12 +106,15 @@ def mkRule ( rule, depends=[], flags=0 ): def __init__ ( self, rule, depends, flags ): from ..helpers.io import ErrorMessage - depends = FlowTask._normFileList( depends ) - targets = [ depends[0].with_suffix('.kdrc-report.txt') ] + arguments = [] + depends = FlowTask._normFileList( depends ) + targets = [ depends[0].with_suffix('.kdrc-report.txt') ] if not DRC._drcRules: raise ErrorMessage( 1, 'DRC.doTask(): No DRC rules defined.' ) - variables = { 'input' : depends[0] - , 'report' : targets[0] + variables = { 'in_gds' : depends[0] + , 'input' : depends[0] + , 'report' : targets[0] + , 'report_file' : targets[0] } - super().__init__( rule, targets, depends, DRC._drcRules, variables, flags ) + super().__init__( rule, targets, depends, DRC._drcRules, arguments, variables, flags ) diff --git a/cumulus/src/designflow/loon.py b/cumulus/src/designflow/loon.py index 38adfdd43..06b49a7d1 100644 --- a/cumulus/src/designflow/loon.py +++ b/cumulus/src/designflow/loon.py @@ -61,7 +61,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Loon.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/lvx.py b/cumulus/src/designflow/lvx.py index 91dd2c9cc..3d3cada6c 100644 --- a/cumulus/src/designflow/lvx.py +++ b/cumulus/src/designflow/lvx.py @@ -58,7 +58,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Lvx.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/pnr.py b/cumulus/src/designflow/pnr.py index ec7e5c3e6..7aefe5cb6 100644 --- a/cumulus/src/designflow/pnr.py +++ b/cumulus/src/designflow/pnr.py @@ -102,7 +102,7 @@ def doTask ( self ): return self.checkTargets( 'PnR.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): if self.design: doc = 'Run {}.'.format( self ) else: doc = 'Run plain CGT (no loaded design)' return { 'basename' : self.basename diff --git a/cumulus/src/designflow/s2r.py b/cumulus/src/designflow/s2r.py index 8c53e1b50..3955ea7b9 100644 --- a/cumulus/src/designflow/s2r.py +++ b/cumulus/src/designflow/s2r.py @@ -53,7 +53,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'S2R.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/surelog.py b/cumulus/src/designflow/surelog.py index 1622fc331..6dd1403fd 100644 --- a/cumulus/src/designflow/surelog.py +++ b/cumulus/src/designflow/surelog.py @@ -61,7 +61,7 @@ def doTask ( self ): shutil.move( 'slpp_all/surelog.uhdm', self.file_target(0) ) return True - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/sv2v.py b/cumulus/src/designflow/sv2v.py index 38450d4c0..67b2e593d 100644 --- a/cumulus/src/designflow/sv2v.py +++ b/cumulus/src/designflow/sv2v.py @@ -64,7 +64,7 @@ def doTask ( self ): status = subprocess.call( command, stdout=fdOut ) return status == 0 - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/svase.py b/cumulus/src/designflow/svase.py index cf5f27a34..9bde9d0d0 100644 --- a/cumulus/src/designflow/svase.py +++ b/cumulus/src/designflow/svase.py @@ -74,7 +74,7 @@ def doTask ( self ): status = subprocess.call( command ) return status == 0 - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/task.py b/cumulus/src/designflow/task.py index e33147d9c..92a0dbbd9 100644 --- a/cumulus/src/designflow/task.py +++ b/cumulus/src/designflow/task.py @@ -20,6 +20,10 @@ class ShellEnv ( object ): * ``GRAAL_TECHNO_NAME``. * ``DREAL_TECHNO_NAME``. * ``CHECK_TOOLKIT``, where the ``alliance-check-toolkit`` is installed. + * ``PDK_ROOT``, parent directory where all the PDKs should be storeds + * ``PDK``, name of the selected PDK. + * ``KLAYOUT_PATH``, technologies & scripts for Klayout. + * ``KLAYOUT_HOME``, user's work directory for Klayout. Mutable environment variables, could be changed in each instance. Their initial values are extracted from the Coriolis Alliance Framework. @@ -41,6 +45,10 @@ class ShellEnv ( object ): RDS_TECHNO_NAME = None GRAAL_TECHNO_NAME = None DREAL_TECHNO_NAME = None + PDK_ROOT = None + PDK = None + KLAYOUT_PATH = None + KLAYOUT_HOME = None def __init__ ( self ): self.shellEnv = {} @@ -76,7 +84,7 @@ def capture ( self ): if ShellEnv.ALLIANCE_TOP: self.shellEnv[ 'ALLIANCE_TOP' ] = ShellEnv.ALLIANCE_TOP libPath = ShellEnv.ALLIANCE_TOP + '/lib' - LD_LIBRARY_PATH = os.environ[ 'LD_LIBRARY_PATH' ] + LD_LIBRARY_PATH = os.environ.get('LD_LIBRARY_PATH', '') if LD_LIBRARY_PATH != '': libPath += ':' + LD_LIBRARY_PATH self.shellEnv[ 'LD_LIBRARY_PATH' ] = libPath @@ -97,6 +105,48 @@ def export ( self ): os.environ[ 'DREAL_TECHNO_NAME' ] = ShellEnv.DREAL_TECHNO_NAME if ShellEnv.CHECK_TOOLKIT is not None: os.environ[ 'CHECK_TOOLKIT' ] = ShellEnv.CHECK_TOOLKIT + if ShellEnv.PDK_ROOT is not None: + os.environ[ 'PDK_ROOT' ] = ShellEnv.PDK_ROOT + if ShellEnv.PDK is not None: + os.environ[ 'PDK' ] = ShellEnv.PDK + if ShellEnv.KLAYOUT_PATH is not None: + os.environ[ 'KLAYOUT_PATH' ] = ShellEnv.KLAYOUT_PATH + if ShellEnv.KLAYOUT_HOME is not None: + os.environ[ 'KLAYOUT_HOME' ] = ShellEnv.KLAYOUT_HOME + + +class Tasks ( object ): + """ + Gather all the FlowTask to execute and provides them to doit through + the ``create_doit_tasks()`` class method. + + In order for the tasks to be taken into account by doit, this class + *must* be imported into the ``dodo.py``: + + .. code:: python + + from coriolis.designflow.task import Tasks + """ + + tasks = [] + + @staticmethod + def hasRule ( name ): + for rule in Tasks.tasks: + if name == rule.basename: return True + return False + + @staticmethod + def append ( task ): + Tasks.tasks.append( task ) + + @classmethod + def create_doit_tasks ( selfClass ): + """ + Return the recorded tasks one by one. + """ + for task in selfClass.tasks: + yield task.asDoitTask() class FlowTask ( object ): @@ -119,7 +169,6 @@ class FlowTask ( object ): the special ``clean_flow`` task. """ - rules = {} cleanTargets = [] @staticmethod @@ -140,17 +189,16 @@ def __init__ ( self, basename, targets, depends ): Promote ``targets`` and ``depends`` arguments to list if needed. Check for duplicated rules, then register the rule name at class level. """ - if FlowTask.hasRule(basename): + if Tasks.hasRule(basename): raise DuplicatedRule( 'FlowTask.__init__(): Duplicated rule "{}"'.format(basename) ) self.basename = basename self.depends = FlowTask._normFileList( depends ) self.targets = FlowTask._normFileList( targets ) - FlowTask.rules[ self.basename ] = self + Tasks.append( self ) @staticmethod def hasRule ( name ): - if name in FlowTask.rules: return True - return False + return Tasks.hasRule( name ) @property def file_dep ( self ): diff --git a/cumulus/src/designflow/technos.py b/cumulus/src/designflow/technos.py index 82a0a4d6f..1f7ce7fae 100644 --- a/cumulus/src/designflow/technos.py +++ b/cumulus/src/designflow/technos.py @@ -3,7 +3,18 @@ import os import socket from pathlib import Path -from .task import ShellEnv +import warnings + +import coriolis # Import the coriolis package to get its path +from .task import ShellEnv +from .klayout import DRC +from .yosys import Yosys + +# Imports from C++ bindings +from coriolis import Cfg +from coriolis import Viewer +from coriolis import CRL +from coriolis.helpers import overlay, l, u, n, setNdaTopDir __all__ = [ 'Where', 'setupCMOS', 'setupCMOS45', 'setupLCMOS' ] @@ -11,29 +22,29 @@ class Where ( object ): - coriolisTop = None - allianceTop = None - cellsTop = None - checkToolkit = None + coriolisTop : Path | None = None + allianceTop : Path | None = None + cellsTop : Path | None = None + checkToolkit : Path | None = None def __init__ ( self, checkToolkit=None ): - if 'CORIOLIS_TOP' in os.environ: Where.coriolisTop = Path( os.environ['CORIOLIS_TOP'] ) - if 'ALLIANCE_TOP' in os.environ: Where.allianceTop = Path( os.environ['ALLIANCE_TOP'] ) - if 'CELLS_TOP' in os.environ: Where.cellsTop = Path( os.environ['CELLS_TOP'] ) - if Where.coriolisTop and not Where.allianceTop: Where.allianceTop = Where.coriolisTop - #print( Where.coriolisTop, Where.allianceTop ) - if not Where.coriolisTop: - print( 'technos.Where.__init__(): Unable to locate Coriolis top.' ) - if checkToolkit is None: + if checkToolkit is None: #TODO Keep this as a hard coded path? checkToolkit = Path.home() / 'coriolis-2.x' / 'src' / 'alliance-check-toolkit' + + Where.checkToolkit = Path( checkToolkit ) + + coriolisTop = os.environ.get('CORIOLIS_TOP', None) + if coriolisTop: + Where.coriolisTop = Path( coriolisTop ) else: - if isinstance(checkToolkit,str): - checkToolkit = Path( checkToolkit ) - if not Where.cellsTop: - Where.cellsTop = checkToolkit / 'cells' - Where.checkToolkit = checkToolkit - if not Where.cellsTop and Where.allianceTop: - Where.cellsTop = Where.allianceTop / 'cells' + Where.coriolisTop = Path( os.path.dirname(os.path.abspath(coriolis.__file__)) ) + + allianceTop = os.environ.get('ALLIANCE_TOP', None) + if allianceTop: + Where.allianceTop = Path( allianceTop ) + else: + Where.allianceTop = Where.coriolisTop + ShellEnv.ALLIANCE_TOP = Where.allianceTop.as_posix() def __repr__ ( self ): @@ -41,58 +52,31 @@ def __repr__ ( self ): return '' return ''.format( Where.coriolisTop.as_posix() ) + @property + def cellsTop( self ): + warnings.warn( + "Where.cellsTop property property is deprecated. Use appropriate PDK instead.", + DeprecationWarning, + stacklevel=2, + ) + return None def setupCMOS ( checkToolkit=None ): - Where( checkToolkit ) - ShellEnv().export() - - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import overlay, l, u, n - from .yosys import Yosys - import coriolis.technos.symbolic.cmos + warnings.warn( + "setupCMOS function has moved to PDK like pdks.cmos_sx.techno, use them instead.", + DeprecationWarning, + stacklevel=2, + ) - with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: - cfg.misc.catchCore = False - cfg.misc.info = False - cfg.misc.paranoid = False - cfg.misc.bug = False - cfg.misc.logMode = True - cfg.misc.verboseLevel1 = True - cfg.misc.verboseLevel2 = True - cfg.misc.minTraceLevel = 1900 - cfg.misc.maxTraceLevel = 3000 - cfg.katana.eventsLimit = 1000000 - cfg.katana.termSatReservedLocal = 6 - cfg.katana.termSatThreshold = 9 - Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) - af = CRL.AllianceFramework.get() - env = af.getEnvironment() - env.setCLOCK( '^ck$|m_clock|^clk' ) - env.addSYSTEM_LIBRARY( library=(Where.checkToolkit / 'cells' / 'niolib').as_posix() - , mode =CRL.Environment.Append ) - - Yosys.setLiberty( Where.allianceTop / 'cells' / 'sxlib' / 'sxlib.lib' ) - ShellEnv.RDS_TECHNO_NAME = (Where.allianceTop / 'etc' / 'cmos.rds').as_posix() - - path = None - for pathVar in [ 'PATH', 'path' ]: - if pathVar in os.environ: - path = os.environ[ pathVar ] - os.environ[ pathVar ] = path + ':' + (Where.allianceTop / 'bin').as_posix() - break + from pdks.cmos_sx import techno + + return techno.setup(checkToolkit) def setupLCMOS ( checkToolkit=None ): Where( checkToolkit ) ShellEnv().export() - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import overlay, l, u, n - from .yosys import Yosys import coriolis.technos.symbolic.lcmos with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: @@ -112,9 +96,9 @@ def setupLCMOS ( checkToolkit=None ): af = CRL.AllianceFramework.get() env = af.getEnvironment() env.setCLOCK( '^ck$|m_clock|^clk$' ) - env.addSYSTEM_LIBRARY ( library=(Where.checkToolkit / 'cells' / 'lsxlib').as_posix(), mode=CRL.Environment.Append ) + env.addSYSTEM_LIBRARY ( library=(Where.cellsTop / 'lsxlib').as_posix(), mode=CRL.Environment.Append ) - Yosys.setLiberty( Where.checkToolkit / 'cells' / 'lsxlib' / 'lsxlib.lib' ) + Yosys.setLiberty( Where.cellsTop / 'lsxlib' / 'lsxlib.lib' ) ShellEnv.RDS_TECHNO_NAME = (Where.allianceTop / 'etc' / 'cmos.rds').as_posix() path = None @@ -128,20 +112,8 @@ def setupLCMOS ( checkToolkit=None ): def setupPhenitec600 ( checkToolkit=None ): Where( checkToolkit ) ShellEnv().export() - cellsTop = Where.checkToolkit / 'cells' - if cellsTop is None: - cellsTop = Where.cellsTop - else: - if isinstance(cellsTop,str): - cellsTop = Path( cellsTop ) - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import overlay, l, u, n - from .yosys import Yosys import coriolis.technos.node600.phenitec - with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: cfg.misc.catchCore = False @@ -161,8 +133,8 @@ def setupPhenitec600 ( checkToolkit=None ): env = af.getEnvironment() env.setCLOCK( '^ck$|m_clock|^clk' ) - nsxlib = cellsTop / 'nsxlib' - phlib80 = cellsTop / 'phlib80' + nsxlib = Where.cellsTop / 'nsxlib' + phlib80 = Where.cellsTop / 'phlib80' liberty = nsxlib / 'nsxlib.lib' env.addSYSTEM_LIBRARY( library=nsxlib .as_posix(), mode=CRL.Environment.Append ) env.addSYSTEM_LIBRARY( library=phlib80.as_posix(), mode=CRL.Environment.Append ) @@ -196,6 +168,14 @@ def setupSky130_nsx2 ( checkToolkit=None ): liberty = cellsTop / 'nsxlib2' / 'nsxlib2.lib' kdrcRules = pdkDir / 'klayout' / 'drc_sky130.lydrc' + + from .. import Cfg + from .. import Viewer + from .. import CRL + from ..helpers import overlay, l, u, n + from .yosys import Yosys + from .klayout import DRC + from .. import Cfg from .. import Viewer from .. import CRL @@ -248,16 +228,10 @@ def setupSky130_lsx ( checkToolkit=None ): liberty = cellsTop / 'lsxlib' / 'lsxlib.lib' kdrcRules = pdkDir / 'klayout' / 'drc_sky130.lydrc' - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import overlay, l, u, n - from .yosys import Yosys - from .klayout import DRC from sky130_lsx import techno, lsxlib techno.setup( coriolisTechDir ) lsxlib.setup( cellsTop ) - + with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: cfg.misc.catchCore = False cfg.misc.info = False @@ -285,11 +259,6 @@ def setupSky130_lsx ( checkToolkit=None ): break def setupCMOS45 ( useNsxlib=False, checkToolkit=None, cellsTop=None ): - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import overlay, l, u, n - from .yosys import Yosys import coriolis.technos.symbolic.cmos45 Where( checkToolkit ) @@ -347,11 +316,6 @@ def setupCMOS45 ( useNsxlib=False, checkToolkit=None, cellsTop=None ): def setupMOSIS ( checkToolkit=None, cellsTop=None ): - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import overlay, l, u, n - from .yosys import Yosys import coriolis.technos.node180.scn6m_deep_09 Where( checkToolkit ) @@ -406,12 +370,6 @@ def setupMOSIS ( checkToolkit=None, cellsTop=None ): def setupSky130_c4m ( checkToolkit=None, pdkMasterTop=None ): - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import setNdaTopDir, overlay, l, u, n - from .yosys import Yosys - if isinstance(pdkMasterTop,str): pdkMasterTop = Path( pdkMasterTop ) ndaDirectory = None @@ -467,11 +425,6 @@ def setupSky130_c4m ( checkToolkit=None, pdkMasterTop=None ): def setupGf180mcu_c4m ( checkToolkit=None , pdkMasterTop=Path('/usr/share/open_pdks/C4M.gf180mcu') ): - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import overlay, l, u, n - from .yosys import Yosys if isinstance(pdkMasterTop,str): pdkMasterTop = Path( pdkMasterTop ) @@ -517,12 +470,6 @@ def setupGf180mcu_c4m ( checkToolkit=None def setupFreePDK45_c4m ( checkToolkit=None, pdkMasterTop=None ): - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import setNdaTopDir, overlay, l, u, n - from .yosys import Yosys - if isinstance(pdkMasterTop,str): pdkMasterTop = Path( pdkMasterTop ) if not pdkMasterTop.is_dir(): @@ -564,12 +511,6 @@ def setupFreePDK45_c4m ( checkToolkit=None, pdkMasterTop=None ): def setupTSMC_c180_c4m ( checkToolkit=None, ndaTop=None ): - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import setNdaTopDir, overlay, l, u, n - from .yosys import Yosys - ndaDirectory = None if ndaTop is not None: if not isinstance(ndaTop,Path): @@ -620,12 +561,6 @@ def setupTSMC_c180_c4m ( checkToolkit=None, ndaTop=None ): def setupGF180MCU_GF ( checkToolkit=None, pdkTop=None, useHV=False ): - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import setNdaTopDir, overlay, l, u, n - from .yosys import Yosys - if isinstance(pdkTop,str): pdkTop = Path( pdkTop ) if not pdkTop: @@ -669,12 +604,6 @@ def setupGF180MCU_GF ( checkToolkit=None, pdkTop=None, useHV=False ): def setupAMS350 ( checkToolkit=None, ndaTop=None, cellsTop=None ): - from .. import Cfg - from .. import Viewer - from .. import CRL - from ..helpers import setNdaTopDir, overlay, l, u, n - from .yosys import Yosys - if isinstance(ndaTop,str): ndaTop = Path( ndaTop ) setNdaTopDir( ndaTop.as_posix() ) diff --git a/cumulus/src/designflow/vasy.py b/cumulus/src/designflow/vasy.py index b70415d37..e8da1ab09 100644 --- a/cumulus/src/designflow/vasy.py +++ b/cumulus/src/designflow/vasy.py @@ -62,7 +62,7 @@ def doTask ( self ): return TaskFailed( e ) return self.checkTargets( 'Vasy.doTask' ) - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/yosys.py b/cumulus/src/designflow/yosys.py index d3add7960..e072cfa32 100644 --- a/cumulus/src/designflow/yosys.py +++ b/cumulus/src/designflow/yosys.py @@ -215,7 +215,7 @@ def doTask ( self ): self._runScript() return self.success - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/designflow/yosysnp.py b/cumulus/src/designflow/yosysnp.py index adb466250..eb917bb68 100644 --- a/cumulus/src/designflow/yosysnp.py +++ b/cumulus/src/designflow/yosysnp.py @@ -84,7 +84,7 @@ def doTask ( self ): status = subprocess.call( command ) return status == 0 - def create_doit_tasks ( self ): + def asDoitTask ( self ): return { 'basename' : self.basename , 'actions' : [ self.doTask ] , 'doc' : 'Run {}.'.format( self ) diff --git a/cumulus/src/plugins/block/block.py b/cumulus/src/plugins/block/block.py index fd509f0d3..790ccdc3b 100644 --- a/cumulus/src/plugins/block/block.py +++ b/cumulus/src/plugins/block/block.py @@ -223,7 +223,7 @@ def place ( self, ioPin ): , gauge.getLayer() , pinPos.getX() , pinPos.getY() - , gauge.getWireWidth() // 2 + , gauge.getWireWidth() # // 2 , gauge.getWireWidth() ) NetExternalComponents.setExternal( pin ) diff --git a/cumulus/src/plugins/chip/__init__.py b/cumulus/src/plugins/chip/__init__.py index b3269b9b3..4e9b873c5 100644 --- a/cumulus/src/plugins/chip/__init__.py +++ b/cumulus/src/plugins/chip/__init__.py @@ -238,13 +238,14 @@ def drawWire ( self ): , xPadMax ) trace( 550, '\thChip2: %s\n' % str(hChip2) ) + viaHeight = max( 2*wwidthM5, self.bbSegment.getHeight() ) hChip = hChip2 if self.side == West else hChip1 bvia1 = BigVia( self.chipNet , rg.getLayerDepth( self.padSegment.getLayer() ) , xJumpMin , self.bbSegment.getCenter().getY() , wwidthM5 - , 2*wwidthM5 + , viaHeight , flags=BigVia.FitToVias ) bvia1.mergeDepth( gaugeM5.getDepth() ) trace( 550, '\tbvia1: %s\n' % str(bvia1) ) @@ -254,7 +255,7 @@ def drawWire ( self ): , xJumpMax , self.bbSegment.getCenter().getY() , wwidthM5 - , 2*wwidthM5 + , viaHeight , flags=BigVia.FitToVias ) bvia2.mergeDepth( gaugeM5.getDepth() ) bvia2.doLayout() @@ -263,7 +264,7 @@ def drawWire ( self ): , bvia2.getPlate( gaugeM5.getLayer() ) , gaugeM5.getLayer() , self.bbSegment.getCenter().getY() - , wwidthM5 + , viaHeight ) else: hChip = Horizontal.create( self.chipNet @@ -378,6 +379,7 @@ def drawWire ( self ): , yPadMin , yPadMax ) + trace( 550, '\tvChip: {}\n'.format( vChip )) trace( 550, '\tself.arraySize: %s\n' % str(self.arraySize) ) if self.arraySize: contacts = self.conf.coronaContactArray( self.chipNet diff --git a/cumulus/src/plugins/chip/chip.py b/cumulus/src/plugins/chip/chip.py index 161f1f100..40fd4a499 100644 --- a/cumulus/src/plugins/chip/chip.py +++ b/cumulus/src/plugins/chip/chip.py @@ -78,10 +78,6 @@ def doChipFloorplan ( self ): minVCorona = self.conf.minVCorona self.conf.chipValidate() if not self.conf.useHarness: - print( ' - Chip has {} north pads.'.format(len(self.conf.chipConf.northPads)) ) - print( ' - Chip has {} south pads.'.format(len(self.conf.chipConf.southPads)) ) - print( ' - Chip has {} east pads.' .format(len(self.conf.chipConf.eastPads )) ) - print( ' - Chip has {} west pads.' .format(len(self.conf.chipConf.westPads )) ) self.conf.computeCoronaBorder() if not self.conf.validated: raise ErrorMessage( 1, 'chip.doChipFloorplan(): Chip is not valid, aborting.' ) @@ -98,6 +94,12 @@ def doChipFloorplan ( self ): minVCorona = self.conf.minVCorona trace( 550, '\tminHCorona={}\n'.format(DbU.getValueString( minHCorona ))) trace( 550, '\tminVCorona={}\n'.format(DbU.getValueString( minVCorona ))) + print( ' - Chip has {} north pads.'.format(len(self.conf.chipConf.northPads)) ) + print( ' - Chip has {} south pads.'.format(len(self.conf.chipConf.southPads)) ) + print( ' - Chip has {} east pads.' .format(len(self.conf.chipConf.eastPads )) ) + print( ' - Chip has {} west pads.' .format(len(self.conf.chipConf.westPads )) ) + print( ' - Chip die size {} x {}.'.format( DbU.getValueString( self.conf.chip.getAbutmentBox().getWidth () ) + , DbU.getValueString( self.conf.chip.getAbutmentBox().getHeight() ))) else: print( ' - Using harness.' ) self.padsCorona = harnessPads.Corona( self ) @@ -126,6 +128,8 @@ def doChipFloorplan ( self ): y = y - (y % self.conf.sliceHeight) self.conf.icore.setTransformation ( Transformation(x,y,Transformation.Orientation.ID) ) self.conf.icore.setPlacementStatus( Instance.PlacementStatus.FIXED ) + print( ' - Chip core size {} x {}.'.format( DbU.getValueString( self.conf.core.getAbutmentBox().getWidth () ) + , DbU.getValueString( self.conf.core.getAbutmentBox().getHeight() ))) self.conf.refresh() def doConnectCore ( self ): diff --git a/cumulus/src/plugins/chip/configuration.py b/cumulus/src/plugins/chip/configuration.py index aa051e833..b1afa08dd 100644 --- a/cumulus/src/plugins/chip/configuration.py +++ b/cumulus/src/plugins/chip/configuration.py @@ -101,6 +101,7 @@ def __init__ ( self, cell, ioPins=[], ioPads=[] ): self.cfg.chip.block.rails.hSpacing = None self.cfg.chip.block.rails.vSpacing = None self._railsCount = self.cfg.chip.block.rails.count + self.cfg.chip.mergeIoGrounds = None self.cfg.chip.iopinRingLayer = None trace( 550, 'iopinRingLayer="{}"'.format( self.cfg.chip.iopinRingLayer )) # Global Net names. @@ -149,6 +150,10 @@ def vRailSpace ( self ): def iopinRingLayer ( self ): return self.cfg.chip.iopinRingLayer + @property + def mergeIoGrounds ( self ): + return self.cfg.chip.mergeIoGrounds + def computeCoronaBorder ( self ): global af if self.useClockTree: diff --git a/cumulus/src/plugins/chip/pads.py b/cumulus/src/plugins/chip/pads.py index b8d9d7b6f..c735582f0 100644 --- a/cumulus/src/plugins/chip/pads.py +++ b/cumulus/src/plugins/chip/pads.py @@ -918,13 +918,13 @@ def _supplyToPad ( self, chipNet, coronaNet, coronaAxis, stripeWidth, side ): trace( 550, '\tchipAxis={}\n'.format(DbU.getValueString(chipAxis)) ) trace( 550, '\trailNet={} <-> {}\n'.format(net,chipNet) ) trace( 550, '\trailAxis={}\n'.format(DbU.getValueString(railAxis)) ) - Vertical.create( chipNet - , supplyLayer - , chipAxis - , stripeWidth - , coronaAb.getYMax() - , self.conf.chipAb.getYMax() - railAxis - ) + v = Vertical.create( chipNet + , supplyLayer + , chipAxis + , stripeWidth + , coronaAb.getYMax() + , self.conf.chipAb.getYMax() - railAxis + ) via = BigVia( chipNet , supplyLayerDepth , chipAxis @@ -933,6 +933,7 @@ def _supplyToPad ( self, chipNet, coronaNet, coronaAxis, stripeWidth, side ): , width , BigVia.FitToVias ) + trace( 550, '\tvertical={}\n'.format(v) ) trace( 550, '\tpower depth: {}\n'.format( self.conf.routingGauge.getPowerSupplyGauge().getDepth() )) via.mergeDepth( self.conf.routingGauge.getPowerSupplyGauge().getDepth()-1 ) via.doLayout() @@ -956,13 +957,13 @@ def _supplyToPad ( self, chipNet, coronaNet, coronaAxis, stripeWidth, side ): trace( 550, '\tchipAxis={}\n'.format(DbU.getValueString(chipAxis)) ) trace( 550, '\trailNet={} <-> {}\n'.format(net,chipNet) ) trace( 550, '\trailAxis={}\n'.format(DbU.getValueString(railAxis)) ) - Vertical.create( chipNet - , supplyLayer - , chipAxis - , stripeWidth - , self.conf.chipAb.getYMin() + railAxis - , coronaAb.getYMin() - ) + v = Vertical.create( chipNet + , supplyLayer + , chipAxis + , stripeWidth + , self.conf.chipAb.getYMin() + railAxis + , coronaAb.getYMin() + ) via = BigVia( chipNet , supplyLayerDepth , chipAxis @@ -973,6 +974,7 @@ def _supplyToPad ( self, chipNet, coronaNet, coronaAxis, stripeWidth, side ): ) via.mergeDepth( supplyLayerDepth-1 ) via.doLayout() + trace( 550, '\tvertical={}\n'.format(v) ) pin = Pin.create( coronaNet , '{}.{}'.format(coronaNet.getName(),self.powerCount) , Pin.Direction.SOUTH @@ -1004,11 +1006,14 @@ def doPowerLayout ( self ): if not self.conf.routingGauge.hasPowerSupply(): return with UpdateSession(): capViaWidth = self.conf.vDeepRG.getPitch()*3 + supplyLayer = self.conf.routingGauge.getPowerSupplyGauge().getLayer() coreAb = self.conf.coreAb powerNet = None groundNet = None chipPowerNet = None chipGroundNet = None + capViaWidth = max( capViaWidth, supplyLayer.getMinimalSize() ) + corona = self.conf.corona for net in corona.getNets(): if net.isPower (): powerNet = net @@ -1049,7 +1054,7 @@ def doPowerLayout ( self ): // self.supplyRailPitch - 1 ) offset = (coreAb.getWidth() - self.supplyRailPitch*(stripesNb-1)) // 2 stripeSpecs.append( [ xcore + capViaWidth//2 , capViaWidth ] ) - stripeSpecs.append( [ xcore + 2*capViaWidth + capViaWidth//2 , capViaWidth ] ) + stripeSpecs.append( [ xcore + 4*capViaWidth + capViaWidth//2 , capViaWidth ] ) if self.chip.spares and len(self.chip.spares.rleafX) > 1: rleafX = self.chip.spares.rleafX spacing = (rleafX[1] - rleafX[0]) // 2 @@ -1079,7 +1084,7 @@ def doPowerLayout ( self ): stripeSpecs.append( [ xcore + offset + i*self.supplyRailPitch , self.supplyRailWidth ] ) - stripeSpecs.append( [ xcore + coreAb.getWidth() - 2*capViaWidth - capViaWidth//2 , capViaWidth ] ) + stripeSpecs.append( [ xcore + coreAb.getWidth() - 4*capViaWidth - capViaWidth//2 , capViaWidth ] ) stripeSpecs.append( [ xcore + coreAb.getWidth() - capViaWidth//2 , capViaWidth ] ) trace( 550, '\ticoreAb={}\n'.format(icore.getAbutmentBox()) ) diff --git a/cumulus/src/plugins/core2chip/core2chip.py b/cumulus/src/plugins/core2chip/core2chip.py index 8dd436e39..a4d87b4a5 100644 --- a/cumulus/src/plugins/core2chip/core2chip.py +++ b/cumulus/src/plugins/core2chip/core2chip.py @@ -646,7 +646,7 @@ def getIoNet ( self, coreNet ): def _connectPadRing ( self, padInstance ): """Connect ring signals to the I/O pad.""" for masterNetName, netName in self.ringNetNames.items(): - if masterNetName == 'iovss': + if masterNetName == 'iovss' and self.conf.mergeIoGrounds: netName = 'vss' trace( 550, '\tCoreToChip._connectPadRing(): master:{} net:{}\n'.format(masterNetName,netName) ) CoreToChip._connect( padInstance, netName, masterNetName ) diff --git a/docker/ubuntu24.04/.bashrc.d/10_coriolis_env.sh b/docker/ubuntu24.04/.bashrc.d/10_coriolis_env.sh new file mode 100644 index 000000000..69a655498 --- /dev/null +++ b/docker/ubuntu24.04/.bashrc.d/10_coriolis_env.sh @@ -0,0 +1,16 @@ +#!/bin/bash + +export PATH="${HOME}/coriolis-2.x/release/install/bin:${PATH}" +export PYTHONPATH="${HOME}/coriolis-2.x/release/install/lib/python3/dist-packages:${PYTHONPATH}" +export VENV_PATH="${HOME}/coriolis-2.x/src/coriolis/.venv" + +export ARCH=$(gcc -dumpmachine) +export LD_LIBRARY_PATH="${HOME}/coriolis-2.x/release/install/lib:${HOME}/coriolis-2.x/release/install/lib/${ARCH}:${LD_LIBRARY_PATH}" + +export CORIOLIS_TOP="${HOME}/coriolis-2.x/release/install" +export ALLIANCE_TOP="${HOME}/coriolis-2.x/release/install" +export CELLS_TOP="${HOME}/coriolis-2.x/release/install/cells" + +if [[ -z "$VIRTUAL_ENV" ]]; then + source ${VENV_PATH}/bin/activate +fi diff --git a/docker/ubuntu24.04/.env.example b/docker/ubuntu24.04/.env.example new file mode 100644 index 000000000..4b63730eb --- /dev/null +++ b/docker/ubuntu24.04/.env.example @@ -0,0 +1,8 @@ +UID=1000 +GID=1000 +CORIOLIS_URL=https://github.com/lip6/coriolis.git +CORIOLIS_BRANCH=main +ALLIANCE_URL=https://github.com/lip6/alliance.git +ALLIANCE_BRANCH=main +ALLIANCE_CT_URL=https://github.com/lip6/alliance-check-toolkit.git +ALLIANCE_CT_BRANCH=main diff --git a/docker/ubuntu24.04/Makefile b/docker/ubuntu24.04/Makefile new file mode 100644 index 000000000..afa183098 --- /dev/null +++ b/docker/ubuntu24.04/Makefile @@ -0,0 +1,65 @@ +VENV_PATH := $(if $(VENV_PATH),$(VENV_PATH),${PWD}) + +BUILD_TYPE := $(if $(BUILD_TYPE),$(BUILD_TYPE),release) + +SRC_DIR := $(if $(SRC_DIR),$(SRC_DIR),${PWD}/../..) + +OUT_DIR := $(if $(OUT_DIR),$(OUT_DIR),${PWD}/${BUILD_TYPE}) + +ALLIANCE_SRC = ${SRC_DIR}/../alliance/alliance/src + +BUILD_DIR = ${OUT_DIR}/build + +PREFIX = ${OUT_DIR}/install + +venv = . ${VENV_PATH}/bin/activate; + +pkg_python3-coriolis-eda = /bin/bash ${SRC_DIR}/packaging/ubuntu24.04/pkg_python3-coriolis-eda.sh + +venv-setup: + python3 -m venv ${VENV_PATH} + +pdm-setup: venv-setup + $(venv) pip3 install build + $(venv) pip3 install pdm + $(venv) pdm plugin update + $(venv) pdm sync -d --no-self + +pdm-config: pdm-setup + $(venv) pdm run meson setup ${SRC_DIR} ${BUILD_DIR} --prefix=${PREFIX} --buildtype=${BUILD_TYPE} -Dpython.install_env=prefix -Donly-docs=false + +install: pdm-config + $(venv) pdm run ninja -j`nproc` -C ${BUILD_DIR} install + +install_alliance: + cd ${ALLIANCE_SRC}; \ + sed -i 's,dirs="\\$$newdirs documentation",dirs="$$newdirs",' ./autostuff; \ + ./autostuff clean; \ + ./autostuff; \ + mkdir -p ${BUILD_DIR}; \ + cd ${BUILD_DIR}; \ + ${ALLIANCE_SRC}/configure --prefix=${PREFIX} --enable-alc-shared; \ + make -j`nproc` install + +install_docs: + $(venv) meson configure ${BUILD_DIR} --prefix=${PREFIX} -Ddocs=true + $(venv) meson install -C ${BUILD_DIR} + @echo "Documentation generated and installed." + +uninstall: + $(venv) pdm run ninja -C ${BUILD_DIR} uninstall + +dist-pkg: install install_docs + @echo "Building distribution package for Ubuntu 24.04"; + $(pkg_python3-coriolis-eda) ${SRC_DIR} ${PREFIX} ${OUT_DIR} + +clean: + rm -rf ${OUT_DIR}/build/* + rm -rf ${OUT_DIR}/install/* + +nuke-everything: + rm -rf ${VENV_PATH} + rm -rf ${OUT_DIR} + @echo ""; + @echo "Successfully nuked all files"; + @echo "\t'Ahhhh... much better!' - Duke Nukem"; diff --git a/docker/ubuntu24.04/README.rst b/docker/ubuntu24.04/README.rst new file mode 100644 index 000000000..f19077982 --- /dev/null +++ b/docker/ubuntu24.04/README.rst @@ -0,0 +1,228 @@ +.. -*- Mode: rst -*- + +Docker development container +============================ + +For users intending to build Coriolis from sources we provide a development container environment. +It is including companions projects Alliance and Alliance Check Toolkit. + +This folder provides two Docker compose deployments: + - A standard, volume based one + - A second one using local folder binding for the Coriolis workspace + +They mainly differ in the way the persistence of the Coriolis workspace folder is achieved. +The default one (as used by VSCode's devcontainer extension) retrieves all repos from GitHub before configuring the workspace. +While the bounded version requires the user to get the source code by himself previously. See guide bellow. + +Purpose +^^^^^^^ + +This container is made for development in a local workspace, bounded inside the container, while +providing a clean, isolated and comprehensive environment. +All dependencies and configurations are met, in a declarative manner. + +Users can both develop and generate distribution packages. + +Base image +^^^^^^^^^^ + +Currently, it uses **Ubuntu 24 LTS** as its base image, tagged *ubuntu:24.04* in DockerHub. +Further development will decide if additional base images should be provided in order for instance +to generate other distribution specific packages. + +For RPM based distributions, OpenSUSE Build System (OBS) is already in use by the project. +Check out the *packaging* folder in coriolis repo. + +Developer guide +=============== + +Prerequisites +^^^^^^^^^^^^^ + +A Docker host is required, with docker and docker-compose properly installed and configured. +Current user also needs proper permissions. This is OS specific and out of this documentation scope. +Refer to suitable instructions in `installation documentation `_. + +**Classic container** + +User may adjust the Coriolis and Alliance GitHub repos URIs and branches being checked out in an .env file placed next the docker compose file. + +.. code-block:: bash + + echo "CORIOLIS_URL=https://github.com/my_fork/coriolis.git" >> docker/ubuntu24.04/.env + echo "CORIOLIS_BRANCH=my_branch" >> docker/ubuntu24.04/.env + echo "ALLIANCE_URL=https://github.com/my_fork/alliance.git" >> docker/ubuntu24.04/.env + echo "ALLIANCE_BRANCH=my_branch" >> docker/ubuntu24.04/.env + echo "ALLIANCE_CT_URL=https://github.com/my_fork/alliance-check-toolkit.git" >> docker/ubuntu24.04/.env + echo "ALLIANCE_CT_BRANCH=my_branch" >> docker/ubuntu24.04/.env + +From now on, simply "docker compose up" the deployment or use VSCode command 'Reopen in container'. +At start, the repos will be cloned if needed and PDM project configured. + + **Important note:** As the changes made to project repositories are kept inside a Docker volume, they persist even when restarting or rebuilding the container. + Which is intended through Docker container lifecycle. Nevertheless, they are not accessible from host filesystem. + **Do not** delete underlying volume without pushing your work toward your repos remotes, or it will be lost. + +**Bounded Workspace container** + +First, choose a workspace on the Docker host. That workspace will be mounted read-write inside the development container. +Declare it using WORKSPACE environment variable, for instance: + +.. code-block:: bash + + export WORKSPACE="${HOME}/coriolis-2.x" + mkdir -p ${WORKSPACE} + +Then clone the projects repositories within workspace: + +.. code-block:: bash + + git clone --recurse-submodules https://github.com/lip6/coriolis.git ${WORKSPACE}/src/coriolis + git clone https://github.com/lip6/alliance.git ${WORKSPACE}/src/alliance + git clone https://github.com/lip6/alliance-check-toolkit.git ${WORKSPACE}/src/alliance-check-toolkit + +It is also advised to set workspace environment variable in an .env file next to the docker compose file: + +.. code-block:: bash + + echo -e "WORKSPACE=${HOME}/coriolis-2.x" >> ${WORKSPACE}/src/coriolis/docker/ubuntu24.04/.env + +Note that for the time being, legacy Coriolis build system requires an *src* folder is to be created in workspace, and that repositories are cloned inside. +Build files will output along that *src* folder. +The build system may remove that requirement in the future. This documentation will be updated accordingly. + +Security +^^^^^^^^ + +Obviously, neither of the provided containers run in **privileged** mode. + +In addition, container's internal user is denied sudo permissions, as it exposes to potential root-level exploitation. Remember Docker is daemon based. +Compromising host security through volumes or local filesystem binding is a common attack pattern if the container is breached. + +All dependencies and requirements are already installed from Dockerfile. Feel free to add or modify them before rebuilding the container. +For generated distribution package testing purposes, they are either available in bounded folder or can be copied over from volume. + +**On bind version** + +For the local folder binding to work with respect to discretionary access control, the current user UID and GID have to match the internal user inside the container. + +Note: For host distributions enforcing Mandatory Access Control with for instance SELinux, the local workspace binding defines the **:Z** attribute. +This allows the binding in a private mode, e.g. only within this development container. + +It is advised to set UID and GID to current user in Docker host machine. The container defaults to **USER 1000:1000**. + +If those values do not match current user's, the local directory binding may fail, rendering its content unreadable. +Set their values in the .env file along docker compose: + +.. code-block:: bash + + echo -e "UID=$(id -u)" >> ${WORKSPACE}/src/coriolis/docker/ubuntu24.04/.env + echo -e "GID=$(id -g)" >> ${WORKSPACE}/src/coriolis/docker/ubuntu24.04/.env + +**On volume version** + +Previous remarks do not apply to the volume version, as it keeps complete isolation from host filesystem. + +Workspace view +^^^^^^^^^^^^^^ + +By default, the user is placed inside the Coriolis repo, along Alliance and Alliance Check Toolkit within workspace. +To set another folder as workspace, either change the *workspaceFolder* parameter in .devcontainer file, or add the *working_dir* in the compose file. + +Then either run docker compose restart or rebuild the development container in VSCode. + +Persistence +^^^^^^^^^^^ + +Data persistence is usually done using Docker volumes, that is what the default development containers uses. +We also provided a second one with a local folder binding. Feel free to used the one best suited and flexible regarding your preferences. + +The workspace is either a volume or a local folder from the Docker host. +In both cases it is persistent, while the container's filesystem is transient, re-initialized upon every container restart cycle. +Any changes made in the workspace like code edits and build outputs are retained inside the *$WORKSPACE/coriolis-2.x* folder. + +With Linux hosts, there is no performance penalty when using either volume or local binding. Also, the binding is secured through Mandatory Access Control like **SELinux** or **AppArmor**, if the host distribution implements it. +That may render the binding variant a little less portable than volume though. +That is why we recommend using the latter as a good standard practice. + +Starting up dev container +^^^^^^^^^^^^^^^^^^^^^^^^^ + +The container me be started using CLI: + +.. code-block:: bash + + docker compose -f "$WORKSPACE/docker/ubuntu24.04/docker-compose-bind.yml" up -d --build + +Get the CONTAINER ID, using for instance: + +.. code-block:: bash + + docker ps + +Then a shell can then be attached to the running container: + +.. code-block:: bash + + docker exec -it $CONTAINER_ID bash + +Although, the recommended workflow recommends using **VSCode** with **Docker** and **Dev Containers** extensions. +A devcontainer.json configuration exists inside coriolis repo. +Simply configure aforementioned env variable then use the 'Reopen in container' command. + +Virtual Environment +^^^^^^^^^^^^^^^^^^^ + +Coriolis build system relies upon Python modules, managed in a PDM project. It follows good practices by using a Python virtual environment. +The idea is to install recommended version for every build dependency without messing up with system wide installations. + +The virtual environment like the PDM project are configured and activated upon container start. + +Workspace configuration +^^^^^^^^^^^^^^^^^^^^^^^ + +An initial configuration is to be done at container start, using provided *setup-coriolis-workspace.sh* script. +That includes cloning the Coriolis, Alliance and Alliance Check Toolkit repositories, and setting up the PDM project. +This operation is done only once, at the first container start or if the volume was recreated. + +All environment variables required by Coriolis and Alliance are configured by the container. +They may then be used by Makefiles and other build tools. + +The internal user's bashrc is also configured to export proper variables: + +.. code-block:: bash + + cat ~/.bashrc + [...] + # Coriolis environment variables + export PATH="${HOME}/coriolis-2.x/release/install/bin:${PATH}" + export PYTHONPATH="${HOME}/coriolis-2.x/release/install/lib/python3/dist-packages:${PYTHONPATH}" + export VENV_PATH="${HOME}/coriolis-2.x/src/coriolis/.venv" + export ARCH=x86_64-linux-gnu + export LD_LIBRARY_PATH="${HOME}/coriolis-2.x/release/install/lib:${HOME}/coriolis-2.x/release/install/lib/${ARCH}:${LD_LIBRARY_PATH}" + export CORIOLIS_TOP="${HOME}/coriolis-2.x/release/install" + export ALLIANCE_TOP="${HOME}/coriolis-2.x/release/install" + export CELLS_TOP="${HOME}/coriolis-2.x/release/install/cells" + [...] + +Note: ARCH value depends on Docker host's architecture. It resolves to *$(gcc -dumpmachine)*. + +Graphic Server Socket +^^^^^^^^^^^^^^^^^^^^^ + +Some of the Coriolis tools rely on the graphic server (Xorg or Wayland), such as **CGT**. + +Running a graphic application from inside a container requires sharing the graphic server socket and configuration with the container. +In compose file, for X11 we use the environment variable: + + - DISPLAY + - XDG_SESSION_TYPE + - XDG_RUNTIME_DIR + +and X11 socket within /tmp/.X11-unix, along with Wayland counterparts: + + - WAYLAND_DISPLAY + +and Wayland socket at: \${XDG_RUNTIME_DIR}/\${WAYLAND_DISPLAY} + +Be sure that your host has a graphic server running and those environment variables are properly set. diff --git a/docker/ubuntu24.04/coriolis-eda-bind.dockerfile b/docker/ubuntu24.04/coriolis-eda-bind.dockerfile new file mode 100644 index 000000000..faeb5f9c4 --- /dev/null +++ b/docker/ubuntu24.04/coriolis-eda-bind.dockerfile @@ -0,0 +1,45 @@ +# Image for vscode container development using local workspace + +FROM ubuntu:24.04 + +RUN apt-get update -y && \ + apt-get install -y vim git locales build-essential ccache cmake \ + python3 python3-pip python3-venv \ + bison flex \ + qtbase5-dev libqt5svg5-dev libqwt-qt5-dev libbz2-dev \ + rapidjson-dev libboost-all-dev libeigen3-dev libxml2-dev libcairo2-dev \ + libmotif-dev libxpm-dev \ + doxygen pelican texlive-latex-recommended graphviz yosys + +RUN export LC_ALL=en_US.UTF-8 && \ + export LANG=en_US.UTF-8 && \ + locale-gen en_US.UTF-8 + +ARG UID=1000 +ARG GID=1000 + +# Clame back all user ids and create developer user +RUN userdel ubuntu && \ + adduser --uid $UID developer && \ + echo "developer:developer" | chpasswd developer + +USER $UID:$GID + +VOLUME /home/developer/coriolis-2.x + +RUN cat <> /home/developer/.bashrc + +# Coriolis environment variables +export PATH="\${HOME}/coriolis-2.x/release/install/bin:\${PATH}" +export PYTHONPATH="\${HOME}/coriolis-2.x/release/install/lib/python3/dist-packages:\${PYTHONPATH}" +export VIRTUAL_ENV="\${HOME}/coriolis-2.x/src/coriolis/.venv" +export ARCH=$(gcc -dumpmachine) +export LD_LIBRARY_PATH="\${HOME}/coriolis-2.x/release/install/lib:\${HOME}/coriolis-2.x/release/install/lib/\${ARCH}:\${LD_LIBRARY_PATH}" +export CORIOLIS_TOP="\${HOME}/coriolis-2.x/release/install" +export ALLIANCE_TOP="\${HOME}/coriolis-2.x/release/install" +export CELLS_TOP="\${HOME}/coriolis-2.x/release/install/cells" +EOF + +WORKDIR /home/developer/coriolis-2.x/src/coriolis + +CMD ["/bin/bash"] diff --git a/docker/ubuntu24.04/coriolis-eda-noX11.dockerfile b/docker/ubuntu24.04/coriolis-eda-noX11.dockerfile new file mode 100644 index 000000000..ed5fbeab4 --- /dev/null +++ b/docker/ubuntu24.04/coriolis-eda-noX11.dockerfile @@ -0,0 +1,50 @@ +# Image for vscode container development using local workspace + +FROM ubuntu:24.04 + +RUN apt-get update -y && \ + apt-get install -y vim git locales build-essential ccache cmake \ + python3 python3-pip python3-venv \ + bison flex \ + qtbase5-dev libqt5svg5-dev libqwt-qt5-dev libbz2-dev \ + rapidjson-dev libboost-all-dev libeigen3-dev libxml2-dev libcairo2-dev \ + libmotif-dev libxpm-dev \ + doxygen pelican texlive-latex-recommended graphviz yosys klayout \ + binutils-dev libiberty-dev && \ + export LC_ALL=en_US.UTF-8 && \ + export LANG=en_US.UTF-8 && \ + locale-gen en_US.UTF-8 + +ARG USER_ID=1000 +ARG GROUP_ID=1000 + +RUN userdel $(getent passwd ${USER_ID} | cut -d':' -f1) && \ + groupadd -g ${GROUP_ID} developer && \ + adduser --uid ${USER_ID} --gid ${GROUP_ID} --disabled-password --gecos "" --shell /bin/bash developer + +USER developer + +COPY setup-coriolis-workspace.sh /home/developer/.local/bin/setup-coriolis-workspace.sh + +COPY .bashrc.d/10_coriolis_env.sh /home/developer/.bashrc.d/10_coriolis_env.sh + +RUN cat <> /home/developer/.bashrc + +# Source all scripts in ~/.bashrc.d +if [[ -d "\${HOME}/.bashrc.d" ]]; then + for file in "\${HOME}/.bashrc.d"/*; do + [ -r "\$file" ] && [ -f "\$file" ] && source "\$file" + done +fi + +# Check if Coriolis workspace is setup +if [[ ! -d "\${HOME}/coriolis-2.x/src/coriolis/.git" ]]; then + echo "Coriolis workspace is not setup yet, you may run 'setup-coriolis-workspace.sh'" +fi +EOF + +VOLUME /home/developer/coriolis-2.x + +WORKDIR /home/developer/coriolis-2.x + +CMD ["/bin/bash"] diff --git a/docker/ubuntu24.04/coriolis-eda.dockerfile b/docker/ubuntu24.04/coriolis-eda.dockerfile new file mode 100644 index 000000000..0224b5696 --- /dev/null +++ b/docker/ubuntu24.04/coriolis-eda.dockerfile @@ -0,0 +1,50 @@ +# Image for vscode container development using local workspace + +FROM ubuntu:24.04 + +RUN apt-get update -y && \ + apt-get install -y vim git locales build-essential ccache cmake \ + python3 python3-pip python3-venv \ + bison flex \ + qtbase5-dev libqt5svg5-dev libqwt-qt5-dev libbz2-dev \ + rapidjson-dev libboost-all-dev libeigen3-dev libxml2-dev libcairo2-dev \ + libmotif-dev libxpm-dev \ + doxygen pelican texlive-latex-recommended graphviz yosys klayout \ + xwayland wayland-protocols libwayland-dev && \ + export LC_ALL=en_US.UTF-8 && \ + export LANG=en_US.UTF-8 && \ + locale-gen en_US.UTF-8 + +ARG USER_ID=1000 +ARG GROUP_ID=1000 + +RUN userdel $(getent passwd ${USER_ID} | cut -d':' -f1) && \ + groupadd -g ${GROUP_ID} developer && \ + adduser --uid ${USER_ID} --gid ${GROUP_ID} --disabled-password --gecos "" --shell /bin/bash developer + +USER developer + +COPY setup-coriolis-workspace.sh /home/developer/.local/bin/setup-coriolis-workspace.sh + +COPY .bashrc.d/10_coriolis_env.sh /home/developer/.bashrc.d/10_coriolis_env.sh + +RUN cat <> /home/developer/.bashrc + +# Source all scripts in ~/.bashrc.d +if [[ -d "\${HOME}/.bashrc.d" ]]; then + for file in "\${HOME}/.bashrc.d"/*; do + [ -r "\$file" ] && [ -f "\$file" ] && source "\$file" + done +fi + +# Check if Coriolis workspace is setup +if [[ ! -d "\${HOME}/coriolis-2.x/src/coriolis/.git" ]]; then + echo "Coriolis workspace is not setup yet, you may run 'setup-coriolis-workspace.sh'" +fi +EOF + +VOLUME /home/developer/coriolis-2.x + +WORKDIR /home/developer/coriolis-2.x + +CMD ["/bin/bash"] diff --git a/docker/ubuntu24.04/docker-compose-bind.yml b/docker/ubuntu24.04/docker-compose-bind.yml new file mode 100644 index 000000000..3adb6dc2b --- /dev/null +++ b/docker/ubuntu24.04/docker-compose-bind.yml @@ -0,0 +1,28 @@ +services: + coriolis-eda-bind: + build: + context: . + dockerfile: ./coriolis-eda-bind.dockerfile + args: + - UID=$UID + - GID=$GID + image: coriolis-eda:ubuntu24.04 + container_name: coriolis-eda + hostname: coriolis-eda + restart: unless-stopped + volumes: + - $WORKSPACE:/home/developer/coriolis-2.x:Z + environment: + - VIRTUAL_ENV=/home/developer/coriolis-2.x/src/coriolis/.venv + - BUILD_TYPE=release + - SRC_DIR=/home/developer/coriolis-2.x/src/coriolis + - OUT_DIR=/home/developer/coriolis-2.x/src/coriolis/docker/ubuntu24.04 + command: bash -c " + make -f /home/developer/coriolis-2.x/src/coriolis/docker/ubuntu24.04/Makefile pdm-config && + sleep infinity" + networks: + - host + +networks: + host: + driver: bridge diff --git a/docker/ubuntu24.04/docker-compose-noX11.yml b/docker/ubuntu24.04/docker-compose-noX11.yml new file mode 100644 index 000000000..ff0c58b69 --- /dev/null +++ b/docker/ubuntu24.04/docker-compose-noX11.yml @@ -0,0 +1,28 @@ +volumes: + coriolis-workspace: + +services: + coriolis-eda-noX11: + build: + context: . + dockerfile: ./coriolis-eda-noX11.dockerfile + image: coriolis-eda-nox11:ubuntu24.04 + container_name: coriolis-eda-noX11 + hostname: coriolis-eda-noX11 + restart: unless-stopped + volumes: + - coriolis-workspace:/home/developer/coriolis-2.x + environment: + - CORIOLIS_URL=${CORIOLIS_URL} + - CORIOLIS_BRANCH=${CORIOLIS_BRANCH} + - ALLIANCE_URL=${ALLIANCE_URL} + - ALLIANCE_BRANCH=${ALLIANCE_BRANCH} + - ALLIANCE_CT_URL=${ALLIANCE_CT_URL} + - ALLIANCE_CT_BRANCH=${ALLIANCE_CT_BRANCH} + - VENV_PATH=/home/developer/coriolis-2.x/src/coriolis/.venv + - BUILD_TYPE=release + - SRC_DIR=/home/developer/coriolis-2.x/src/coriolis + - OUT_DIR=/home/developer/coriolis-2.x/src/coriolis/docker/ubuntu24.04 + privileged: false + network_mode: "bridge" + command: ["sleep", "infinity"] diff --git a/docker/ubuntu24.04/docker-compose.yml b/docker/ubuntu24.04/docker-compose.yml new file mode 100644 index 000000000..08958271b --- /dev/null +++ b/docker/ubuntu24.04/docker-compose.yml @@ -0,0 +1,44 @@ +volumes: + coriolis-workspace: + +services: + coriolis-eda: + build: + context: . + dockerfile: ./coriolis-eda.dockerfile + args: + - USER_ID=${UID} + - GROUP_ID=${GID} + image: coriolis-eda:ubuntu24.04 + container_name: coriolis-eda + hostname: coriolis-eda + restart: unless-stopped + volumes: + - coriolis-workspace:/home/developer/coriolis-2.x + - ${XDG_RUNTIME_DIR}:${XDG_RUNTIME_DIR}:ro + - ${XDG_RUNTIME_DIR}/${WAYLAND_DISPLAY}:${XDG_RUNTIME_DIR}/${WAYLAND_DISPLAY}:ro + - /tmp/.X11-unix:/tmp/.X11-unix:ro + environment: + - CORIOLIS_URL=${CORIOLIS_URL} + - CORIOLIS_BRANCH=${CORIOLIS_BRANCH} + - ALLIANCE_URL=${ALLIANCE_URL} + - ALLIANCE_BRANCH=${ALLIANCE_BRANCH} + - ALLIANCE_CT_URL=${ALLIANCE_CT_URL} + - ALLIANCE_CT_BRANCH=${ALLIANCE_CT_BRANCH} + - VENV_PATH=/home/developer/coriolis-2.x/src/coriolis/.venv + - BUILD_TYPE=release + - SRC_DIR=/home/developer/coriolis-2.x/src/coriolis + - OUT_DIR=/home/developer/coriolis-2.x/src/coriolis/docker/ubuntu24.04 + - XDG_SESSION_TYPE=${XDG_SESSION_TYPE} + - XDG_RUNTIME_DIR=${XDG_RUNTIME_DIR} + - WAYLAND_DISPLAY=${WAYLAND_DISPLAY} + - DISPLAY=${DISPLAY} + privileged: false + cap_drop: + - ALL + security_opt: + - no-new-privileges:true + - label:type:container_runtime_t + - label:level:s0 + network_mode: "bridge" + command: ["sleep", "infinity"] diff --git a/docker/ubuntu24.04/setup-coriolis-workspace.sh b/docker/ubuntu24.04/setup-coriolis-workspace.sh new file mode 100755 index 000000000..f8ef4cf59 --- /dev/null +++ b/docker/ubuntu24.04/setup-coriolis-workspace.sh @@ -0,0 +1,35 @@ +#!/bin/bash + +if [[ ! -d ${HOME}/coriolis-2.x/src/coriolis/.git ]]; then + echo "Coriolis Git repo not found, cloning..." + git clone -b ${CORIOLIS_BRANCH} --recurse-submodules ${CORIOLIS_URL} ${HOME}/coriolis-2.x/src/coriolis +else + echo "Coriolis Git repo already exists, skip cloning." +fi + +if [[ ! -d ${HOME}/coriolis-2.x/src/alliance/.git ]]; then + echo "Alliance Git repo not found, cloning..." + git clone -b ${ALLIANCE_BRANCH} ${ALLIANCE_URL} ${HOME}/coriolis-2.x/src/alliance +else + echo "Alliance Git repo already exists, skip cloning." +fi + +if [[ ! -d ${HOME}/coriolis-2.x/src/alliance-check-toolkit/.git ]]; then + echo "Alliance-check-toolkit Git repo not found, cloning..." + git clone -b ${ALLIANCE_CT_BRANCH} ${ALLIANCE_CT_URL} ${HOME}/coriolis-2.x/src/alliance-check-toolkit +else + echo "Alliance-check-toolkit Git repo already exists, skip cloning." +fi + +if [[ -d "${VENV_PATH}" ]]; then + echo "PDM project and virtual env are already configured, skip configuration." +else + echo "PDM project and virtual env not configured, configuring..." + make -C ${HOME}/coriolis-2.x/src/coriolis -f docker/ubuntu24.04/Makefile pdm-config +fi + +cat < { + class RailMatch { public: inline RailMatch ( DbU::Unit axis, DbU::Unit width ); inline bool operator() ( const Rail* ); diff --git a/hurricane/src/analog/hurricane/analog/Device.h b/hurricane/src/analog/hurricane/analog/Device.h index 8406bf970..3325414ee 100644 --- a/hurricane/src/analog/hurricane/analog/Device.h +++ b/hurricane/src/analog/hurricane/analog/Device.h @@ -34,7 +34,7 @@ namespace Analog { class Device : public Hurricane::Cell { public: - struct ParameterCompare: public std::binary_function { + struct ParameterCompare { bool operator() ( Parameter* dp1, Parameter* dp2 ) const { if (dp1->getIndex() < dp2->getIndex()) return true; return (dp1->getIndex() == dp2->getIndex() diff --git a/hurricane/src/hurricane/Box.cpp b/hurricane/src/hurricane/Box.cpp index 8de4eb805..3f1d9b97f 100644 --- a/hurricane/src/hurricane/Box.cpp +++ b/hurricane/src/hurricane/Box.cpp @@ -329,6 +329,18 @@ Box& Box::translate(const DbU::Unit& dx, const DbU::Unit& dy) return *this; } +Box& Box::translate(const Point& p) +// ******************************** +{ + if (!isEmpty()) { + _xMin += p.getX(); + _yMin += p.getY(); + _xMax += p.getX(); + _yMax += p.getY(); + } + return *this; +} + string Box::_getString() const // *************************** { diff --git a/hurricane/src/hurricane/Cell.cpp b/hurricane/src/hurricane/Cell.cpp index 45825626d..03918fcdd 100644 --- a/hurricane/src/hurricane/Cell.cpp +++ b/hurricane/src/hurricane/Cell.cpp @@ -33,6 +33,7 @@ #include "hurricane/Vertical.h" #include "hurricane/Contact.h" #include "hurricane/Pad.h" +#include "hurricane/Rectilinear.h" #include "hurricane/Layer.h" #include "hurricane/Slice.h" #include "hurricane/Rubber.h" @@ -1067,7 +1068,6 @@ Cell* Cell::getClone() return clone; } - void Cell::uniquify(unsigned int depth) // ************************************ { diff --git a/hurricane/src/hurricane/Component.cpp b/hurricane/src/hurricane/Component.cpp index 8548f38de..67726e5cd 100644 --- a/hurricane/src/hurricane/Component.cpp +++ b/hurricane/src/hurricane/Component.cpp @@ -515,6 +515,14 @@ void Component::_preDestroy() } +bool Component::isConvex () const +{ return true; } + + +bool Component::isPolygon45 () const +{ return false; } + + bool Component::isNonRectangle () const { return false; } diff --git a/hurricane/src/hurricane/Go.cpp b/hurricane/src/hurricane/Go.cpp index f7615dea2..bdaf11c34 100644 --- a/hurricane/src/hurricane/Go.cpp +++ b/hurricane/src/hurricane/Go.cpp @@ -84,6 +84,9 @@ void Go::_preDestroy() //ltraceout(10); } +void Go::translate(const Point& p ) +{ translate( p.getX(), p.getY() ); } + string Go::_getString() const // ************************** { diff --git a/hurricane/src/hurricane/Point.cpp b/hurricane/src/hurricane/Point.cpp index 903b19dd3..4aaa478a6 100644 --- a/hurricane/src/hurricane/Point.cpp +++ b/hurricane/src/hurricane/Point.cpp @@ -104,6 +104,14 @@ Point& Point::translate(const DbU::Unit& dx, const DbU::Unit& dy) return *this; } +Point& Point::translate(const Point& p) +// ************************************ +{ + _x += p.getX(); + _y += p.getY(); + return *this; +} + Point Point::getTranslated(const DbU::Unit& dx, const DbU::Unit& dy) const { return Point(*this).translate(dx, dy); } diff --git a/hurricane/src/hurricane/Polygon.cpp b/hurricane/src/hurricane/Polygon.cpp index 806725710..2eccf023b 100644 --- a/hurricane/src/hurricane/Polygon.cpp +++ b/hurricane/src/hurricane/Polygon.cpp @@ -36,6 +36,8 @@ #include "hurricane/BasicLayer.h" #include "hurricane/Layer.h" #include "hurricane/Error.h" +#include "hurricane/UpdateSession.h" +#include "hurricane/Breakpoint.h" namespace Hurricane { @@ -195,6 +197,7 @@ namespace Hurricane { Polygon::Polygon ( Net* net, const Layer* layer, const vector& points ) : Super (net) + , _flags (Convex) , _layer (layer) , _points(points) , _edges () @@ -209,40 +212,54 @@ namespace Hurricane { if (points.size() < 3) throw Error("Can't create " + _TName("Polygon") + " : less than three points"); - float sign = 0.0; - for ( size_t i=0 ; i_points, polygon->_flags ); + polygon->_postCreate(); + polygon->manhattanize(); + return polygon; + } + + void Polygon::normalize ( vector& points, uint32_t& flags ) + { + vector rawPoints ( points ); + flags = Convex|Polygon45; + + float sign = 0.0; + for ( size_t i=0 ; i points[istart].getX()) - or ( (points[i].getX() == points[istart].getX()) - and (points[i].getY() > points[istart].getY()) ) ) + for ( size_t i=0 ; i rawPoints[istart].getX()) + or ( (rawPoints[i].getX() == rawPoints[istart].getX()) + and (rawPoints[i].getY() > rawPoints[istart].getY()) )) istart = i; } - vector normalized ( points.size(), Point() ); if ( (istart != 0) or (sign > 0.0) ) { if (sign < 0.0) { - for ( size_t i=0 ; i_postCreate(); - triangle->manhattanize(); - return triangle; + } } @@ -252,6 +269,14 @@ namespace Hurricane { } + bool Polygon::isConvex () const + { return (_flags & Convex); } + + + bool Polygon::isPolygon45 () const + { return (_flags & Polygon45); } + + bool Polygon::isNonRectangle () const { return true; } @@ -342,10 +367,12 @@ namespace Hurricane { { invalidate( true ); + vector emptyVector; _points.swap( emptyVector ); _points.reserve( points.size() ); _points = points; + normalize( _points, _flags ); if (isManhattanized()) { for ( Edge* edge : _edges ) delete edge; @@ -369,6 +396,18 @@ namespace Hurricane { } + bool Polygon::isEdge45 ( const vector& points, size_t i ) + { + size_t i1 = (i+1) % points.size(); + + DbU::Unit dx = std::abs( points[i1].getX() - points[i ].getX() ); + DbU::Unit dy = std::abs( points[i1].getY() - points[i ].getY() ); + // cerr << "| dx=" << dx << " dy=" << dy << "(" + // << DbU::getValueString(dx) << "," << DbU::getValueString(dy) << ")" << endl; + return (dx == 0) or (dy == 0) or (dx == dy); + } + + float Polygon::getSlope ( const Point& origin, const Point& extremity ) { float dx1 = (float)(extremity.getX() - origin.getX()); @@ -388,6 +427,8 @@ namespace Hurricane { for ( Edge* edge : _edges ) delete edge; _edges.clear(); + if (isPolygon45()) return; + for ( size_t i=0 ; i<_points.size() ; ++i ) { const Point& origin = _points[ i % _points.size()]; const Point& extremity = _points[ (i+1) % _points.size()]; @@ -405,6 +446,8 @@ namespace Hurricane { // cerr << "Polygon::getSubPolygons(): " << this << endl; + if (isPolygon45()) return; + vector upSide; vector downSide; Point first; diff --git a/hurricane/src/hurricane/hurricane/Box.h b/hurricane/src/hurricane/hurricane/Box.h index ae9497858..89383552d 100644 --- a/hurricane/src/hurricane/hurricane/Box.h +++ b/hurricane/src/hurricane/hurricane/Box.h @@ -17,9 +17,7 @@ // not, see . // **************************************************************************************************** -#ifndef HURRICANE_BOX -#define HURRICANE_BOX - +#pragma once #include "hurricane/Point.h" namespace Hurricane { @@ -118,6 +116,7 @@ class Box { public: Box& merge(const Box& box); public: Box& translate(const DbU::Unit& dx, const DbU::Unit& dy); + public: Box& translate(const Point& p); // Others // ****** @@ -148,9 +147,6 @@ class JsonBox : public JsonObject { INSPECTOR_PR_SUPPORT(Hurricane::Box); -#endif // HURRICANE_BOX - - // **************************************************************************************************** // Copyright (c) BULL S.A. 2000-2018, All Rights Reserved // **************************************************************************************************** diff --git a/hurricane/src/hurricane/hurricane/Component.h b/hurricane/src/hurricane/hurricane/Component.h index 077ce7741..5b5f0dfe1 100644 --- a/hurricane/src/hurricane/hurricane/Component.h +++ b/hurricane/src/hurricane/hurricane/Component.h @@ -89,6 +89,8 @@ namespace Hurricane { Component ( Net* , bool inPlugCreate = false ); public: // Accessors. + virtual bool isConvex () const; + virtual bool isPolygon45 () const; virtual bool isManhattanized () const; virtual bool isNonRectangle () const; virtual Cell* getCell () const; diff --git a/hurricane/src/hurricane/hurricane/DBo.h b/hurricane/src/hurricane/hurricane/DBo.h index 1db5455fc..94a481052 100644 --- a/hurricane/src/hurricane/hurricane/DBo.h +++ b/hurricane/src/hurricane/hurricane/DBo.h @@ -97,7 +97,7 @@ namespace Hurricane { unsigned int _id; mutable set _propertySet; public: - struct CompareById : public std::binary_function { + struct CompareById { template inline bool operator() ( const Key* lhs, const Key* rhs ) const; }; diff --git a/hurricane/src/hurricane/hurricane/DeviceDescriptor.h b/hurricane/src/hurricane/hurricane/DeviceDescriptor.h index 5babc9cea..febaebe63 100644 --- a/hurricane/src/hurricane/hurricane/DeviceDescriptor.h +++ b/hurricane/src/hurricane/hurricane/DeviceDescriptor.h @@ -26,8 +26,7 @@ namespace Hurricane { class DeviceDescriptor { public: - struct DeviceDescriptorComp: - public std::binary_function { + struct DeviceDescriptorComp { bool operator () ( const DeviceDescriptor* ldd, const DeviceDescriptor* rdd ) const { return ldd->getName() < rdd->getName(); } }; diff --git a/hurricane/src/hurricane/hurricane/Go.h b/hurricane/src/hurricane/hurricane/Go.h index b0112e048..1f4ad399b 100644 --- a/hurricane/src/hurricane/hurricane/Go.h +++ b/hurricane/src/hurricane/hurricane/Go.h @@ -76,6 +76,7 @@ class Go : public Entity { // implementation located on file UpdateSession.cpp to access local variables public: virtual void translate(const DbU::Unit& dx, const DbU::Unit& dy) = 0; + public: virtual void translate(const Point& ); // Others // ****** diff --git a/hurricane/src/hurricane/hurricane/IntervalTree.h b/hurricane/src/hurricane/hurricane/IntervalTree.h index 58f4264d0..5aef960b4 100644 --- a/hurricane/src/hurricane/hurricane/IntervalTree.h +++ b/hurricane/src/hurricane/hurricane/IntervalTree.h @@ -455,7 +455,7 @@ namespace Hurricane { leftMost = current; } if ( current->getLeft() - and (overlap.getVMin() < current->getLeft()->getValue().getChildsVMax()) ) { + and (overlap.getVMin() <= current->getLeft()->getValue().getChildsVMax()) ) { current = current->getLeft(); leftMost = nullptr; } else { diff --git a/hurricane/src/hurricane/hurricane/Layer.h b/hurricane/src/hurricane/hurricane/Layer.h index 3701fbdf4..4f6fa5a60 100644 --- a/hurricane/src/hurricane/hurricane/Layer.h +++ b/hurricane/src/hurricane/hurricane/Layer.h @@ -140,7 +140,7 @@ namespace Hurricane { virtual void _preDestroy (); public: - struct CompareByMask : public binary_function { + struct CompareByMask { inline bool operator() ( const Layer* lhs, const Layer* rhs ) const; }; }; diff --git a/hurricane/src/hurricane/hurricane/ModelDescriptor.h b/hurricane/src/hurricane/hurricane/ModelDescriptor.h index 333385c70..b9e59ef6c 100644 --- a/hurricane/src/hurricane/hurricane/ModelDescriptor.h +++ b/hurricane/src/hurricane/hurricane/ModelDescriptor.h @@ -24,8 +24,7 @@ namespace Hurricane { class ModelDescriptor { public: - struct ModelDescriptorComp: - public std::binary_function { + struct ModelDescriptorComp { bool operator () ( const ModelDescriptor* lmd, const ModelDescriptor* rmd ) const { return lmd->getName() < rmd->getName(); } }; diff --git a/hurricane/src/hurricane/hurricane/Point.h b/hurricane/src/hurricane/hurricane/Point.h index 3d5fba0fa..53d96a7a9 100644 --- a/hurricane/src/hurricane/hurricane/Point.h +++ b/hurricane/src/hurricane/hurricane/Point.h @@ -17,9 +17,7 @@ // not, see . // **************************************************************************************************** -#ifndef HURRICANE_POINT -#define HURRICANE_POINT - +#pragma once #include "hurricane/DbU.h" namespace Hurricane { @@ -74,6 +72,7 @@ class Point { public: void setX(DbU::Unit x) {_x = x;}; public: void setY(DbU::Unit y) {_y = y;}; public: Point& translate(const DbU::Unit& dx, const DbU::Unit& dy); + public: Point& translate(const Point&); public: Point getTranslated(const DbU::Unit& dx, const DbU::Unit& dy) const; // Others @@ -103,9 +102,6 @@ class JsonPoint : public JsonObject { INSPECTOR_PR_SUPPORT(Hurricane::Point); -#endif // HURRICANE_POINT - - // **************************************************************************************************** // Copyright (c) BULL S.A. 2000-2018, All Rights Reserved // **************************************************************************************************** diff --git a/hurricane/src/hurricane/hurricane/Polygon.h b/hurricane/src/hurricane/hurricane/Polygon.h index 9e81e57cc..a7715cb90 100644 --- a/hurricane/src/hurricane/hurricane/Polygon.h +++ b/hurricane/src/hurricane/hurricane/Polygon.h @@ -29,9 +29,7 @@ // +-----------------------------------------------------------------+ -#ifndef HURRICANE_POLYGON_H -#define HURRICANE_POLYGON_H - +#pragma once #include "hurricane/Component.h" #include "hurricane/Polygons.h" @@ -52,6 +50,8 @@ namespace Hurricane { static const uint32_t YIncrease = (1<<4); static const uint32_t Horizontal = (1<<5); static const uint32_t Vertical = (1<<6); + static const uint32_t Convex = (1<<7); + static const uint32_t Polygon45 = (1<<8); public: class Edge { @@ -105,9 +105,12 @@ namespace Hurricane { public: static Polygon* create ( Net*, const Layer*, const std::vector& ); static float getSlope ( const Point&, const Point& ); + static void normalize ( std::vector&, uint32_t& flags ); public: virtual bool isNonRectangle () const; virtual bool isManhattanized () const; + virtual bool isConvex () const; + virtual bool isPolygon45 () const; virtual DbU::Unit getX () const; virtual DbU::Unit getY () const; inline const vector& getPoints () const; @@ -122,6 +125,7 @@ namespace Hurricane { virtual void translate ( const DbU::Unit& dx, const DbU::Unit& dy ); void setPoints ( const vector& ); static float getSign ( const vector&, size_t ); + static bool isEdge45 ( const vector&, size_t ); float getSlope ( size_t i ) const; void manhattanize (); virtual Points getMContour () const; @@ -134,6 +138,7 @@ namespace Hurricane { Polygon ( Net*, const Layer*, const std::vector& ); ~Polygon (); private: + uint32_t _flags; const Layer* _layer; std::vector _points; std::vector _edges; @@ -187,5 +192,3 @@ namespace Hurricane { INSPECTOR_P_SUPPORT(Hurricane::Polygon::Edge); INSPECTOR_P_SUPPORT(Hurricane::Polygon); - -#endif // HURRICANE_POLYGON_H diff --git a/hurricane/src/hurricane/meson.build b/hurricane/src/hurricane/meson.build index e78211dc7..c1401fb69 100644 --- a/hurricane/src/hurricane/meson.build +++ b/hurricane/src/hurricane/meson.build @@ -92,7 +92,7 @@ hurricane = shared_library( 'TwoLayersPhysicalRule.cpp', 'Text.cpp', - dependencies: [qt_deps, boost, rapidjson, bzip2], + dependencies: [qt_deps, boost, rapidjson, bzip2, libbfd_deps], include_directories: hurricane_includes, install: true, ) diff --git a/hurricane/src/isobar/PyBox.cpp b/hurricane/src/isobar/PyBox.cpp index dcfc7d160..a6aa880e8 100644 --- a/hurricane/src/isobar/PyBox.cpp +++ b/hurricane/src/isobar/PyBox.cpp @@ -344,8 +344,9 @@ extern "C" { PyObject* arg0 = NULL; PyObject* arg1 = NULL; __cs.init ("Box.translate"); - if (PyArg_ParseTuple(args,"O&O&:Box.translate", Converter, &arg0, Converter, &arg1)) { - if (__cs.getObjectIds() == INTS2_ARG) box->translate( PyAny_AsLong(arg0), PyAny_AsLong(arg1) ); + if (PyArg_ParseTuple(args,"O&|O&:Box.translate", Converter, &arg0, Converter, &arg1)) { + if (__cs.getObjectIds() == INTS2_ARG) box->translate( PyAny_AsLong(arg0), PyAny_AsLong(arg1) ); + else if (__cs.getObjectIds() == POINT_ARG) box->translate( *PYPOINT_O(arg0) ); else { PyErr_SetString ( ConstructorError, "Box.translate(): Invalid type for parameter(s)." ); return NULL; @@ -356,7 +357,8 @@ extern "C" { } HCATCH - Py_RETURN_NONE; + Py_INCREF ( self ); + return ( (PyObject*)self ); } diff --git a/hurricane/src/isobar/PyComponent.cpp b/hurricane/src/isobar/PyComponent.cpp index 1910e6f3b..c0fb79ad6 100644 --- a/hurricane/src/isobar/PyComponent.cpp +++ b/hurricane/src/isobar/PyComponent.cpp @@ -217,6 +217,31 @@ extern "C" { } + static PyObject* PyComponent_translate ( PyComponent *self, PyObject* args ) { + cdebug_log(20,0) << "PyComponent_translate ()" << endl; + + HTRY + METHOD_HEAD ( "Component.translate()" ) + PyObject* arg0 = NULL; + PyObject* arg1 = NULL; + __cs.init ("Component.translate"); + if (PyArg_ParseTuple(args,"O&|O&:Component.translate", Converter, &arg0, Converter, &arg1)) { + if (__cs.getObjectIds() == INTS2_ARG) component->translate( PyAny_AsLong(arg0), PyAny_AsLong(arg1) ); + else if (__cs.getObjectIds() == POINT_ARG) component->translate( *PYPOINT_O(arg0) ); + else { + PyErr_SetString ( ConstructorError, "Component.translate(): Invalid type for parameter(s)." ); + return NULL; + } + } else { + PyErr_SetString ( ConstructorError, "Component.translate(): Invalid number of parameters." ); + return NULL; + } + HCATCH + + Py_RETURN_NONE; + } + + PyMethodDef PyComponent_Methods[] = { { "getBodyHook" , (PyCFunction)PyComponent_getBodyHook , METH_NOARGS , "Return the component body hook (is a master Hook)." } , { "getX" , (PyCFunction)PyComponent_getX , METH_NOARGS , "Return the Component X value." } @@ -229,6 +254,7 @@ extern "C" { , { "getContour" , (PyCFunction)PyComponent_getContour , METH_NOARGS , "Return the points of the polygonic contour." } , { "getConnexComponents" , (PyCFunction)PyComponent_getConnexComponents, METH_NOARGS , "All the components connecteds to this one through hyper hooks." } , { "getSlaveComponents" , (PyCFunction)PyComponent_getSlaveComponents , METH_NOARGS , "All the components anchored directly or indirectly on this one." } + , { "translate" , (PyCFunction)PyComponent_translate , METH_VARARGS, "Translate the component." } , { "destroy" , (PyCFunction)PyComponent_destroy , METH_NOARGS , "destroy associated hurricane object, the python object remains." } , {NULL, NULL, 0, NULL} /* sentinel */ diff --git a/hurricane/src/isobar/PyHorizontal.cpp b/hurricane/src/isobar/PyHorizontal.cpp index e046b9846..43237ca00 100644 --- a/hurricane/src/isobar/PyHorizontal.cpp +++ b/hurricane/src/isobar/PyHorizontal.cpp @@ -162,33 +162,6 @@ extern "C" { } - // --------------------------------------------------------------- - // Attribute Method : "PyHorizontal_translate ()" - - static PyObject* PyHorizontal_translate ( PyHorizontal *self, PyObject* args ) { - cdebug_log(20,0) << "PyHorizontal_translate ()" << endl; - - HTRY - METHOD_HEAD ( "Horizontal.translate()" ) - PyObject* arg0 = NULL; - PyObject* arg1 = NULL; - __cs.init ("Horizontal.translate"); - if (PyArg_ParseTuple(args,"O&O&:Horizontal.translate", Converter, &arg0, Converter, &arg1)) { - if (__cs.getObjectIds() == INTS2_ARG) horizontal->translate( PyAny_AsLong(arg0), PyAny_AsLong(arg1) ); - else { - PyErr_SetString ( ConstructorError, "Horizontal.translate(): Invalid type for parameter(s)." ); - return NULL; - } - } else { - PyErr_SetString ( ConstructorError, "Horizontal.translate(): Invalid number of parameters." ); - return NULL; - } - HCATCH - - Py_RETURN_NONE; - } - - // --------------------------------------------------------------- // PyHorizontal Attribute Method table. @@ -201,7 +174,6 @@ extern "C" { , { "setY" , (PyCFunction)PyHorizontal_setY , METH_VARARGS, "Modify the segment Y position." } , { "setDxSource", (PyCFunction)PyHorizontal_setDxSource, METH_VARARGS, "Modify the segment source X offset." } , { "setDxTarget", (PyCFunction)PyHorizontal_setDxTarget, METH_VARARGS, "Modify the segment target X offset." } - , { "translate" , (PyCFunction)PyHorizontal_translate , METH_VARARGS, "Translates the Horizontal segment of dx and dy." } , { "destroy" , (PyCFunction)PyHorizontal_destroy , METH_NOARGS , "destroy associated hurricane object, the python object remains." } , {NULL, NULL, 0, NULL} /* sentinel */ diff --git a/hurricane/src/isobar/PyPolygon.cpp b/hurricane/src/isobar/PyPolygon.cpp index d80f12f3c..c32f2a6d2 100644 --- a/hurricane/src/isobar/PyPolygon.cpp +++ b/hurricane/src/isobar/PyPolygon.cpp @@ -160,6 +160,20 @@ extern "C" { } + static PyObject *PyPolygon_getPoints ( PyPolygon *self ) + { + cdebug_log(20,0) << "Polygon.getPoints()" << endl; + + HTRY + METHOD_HEAD( "Polygon.getPoints()" ) + + return VectorToList(polygon->getPoints()); + HCATCH + + Py_RETURN_NONE; + } + + static PyObject* PyPolygon_setPoints ( PyPolygon *self, PyObject* args ) { cdebug_log(20,0) << "Polygon.setPoints()" << endl; @@ -237,6 +251,7 @@ extern "C" { , { "getX" , (PyCFunction)PyPolygon_getX , METH_NOARGS , "Return the Polygon X value." } , { "getY" , (PyCFunction)PyPolygon_getY , METH_NOARGS , "Return the Polygon Y value." } , { "getBoundingBox", (PyCFunction)PyPolygon_getBoundingBox, METH_NOARGS , "Return the Polygon Bounding Box." } + , { "getPoints" , (PyCFunction)PyPolygon_getPoints , METH_NOARGS , "Gets the Polygon points." } , { "getMContour" , (PyCFunction)PyPolygon_getMContour , METH_NOARGS , "Return the points of the manhattanized contour." } , { "getSubPolygons", (PyCFunction)PyPolygon_getSubPolygons, METH_NOARGS , "Return the list of sub-polygons (GDSII compliants)." } , { "setPoints" , (PyCFunction)PyPolygon_setPoints , METH_VARARGS, "Sets the Polygon Bounding Box." } diff --git a/hurricane/src/isobar/PyRectilinear.cpp b/hurricane/src/isobar/PyRectilinear.cpp index b4db4f6ca..0071f13eb 100644 --- a/hurricane/src/isobar/PyRectilinear.cpp +++ b/hurricane/src/isobar/PyRectilinear.cpp @@ -160,6 +160,7 @@ extern "C" { Py_RETURN_NONE; } + static PyObject *PyRectilinear_getPoints ( PyRectilinear *self ) { cdebug_log(20,0) << "Rectilinear.getPoints()" << endl; diff --git a/hurricane/src/isobar/PyVertical.cpp b/hurricane/src/isobar/PyVertical.cpp index 9ff8f1568..7f27c5f44 100644 --- a/hurricane/src/isobar/PyVertical.cpp +++ b/hurricane/src/isobar/PyVertical.cpp @@ -145,33 +145,6 @@ extern "C" { } - // --------------------------------------------------------------- - // Attribute Method : "PyVertical_translate ()" - - static PyObject* PyVertical_translate ( PyVertical *self, PyObject* args ) { - cdebug_log(20,0) << "PyVertical_translate ()" << endl; - - HTRY - METHOD_HEAD ( "Vertical.translate()" ) - PyObject* arg0 = NULL; - PyObject* arg1 = NULL; - __cs.init ("Vertical.translate"); - if (PyArg_ParseTuple(args,"O&O&:Vertical.translate", Converter, &arg0, Converter, &arg1)) { - if (__cs.getObjectIds() == INTS2_ARG) vertical->translate( PyAny_AsLong(arg0), PyAny_AsLong(arg1) ); - else { - PyErr_SetString ( ConstructorError, "Vertical.translate(): Invalid type for parameter(s)." ); - return NULL; - } - } else { - PyErr_SetString ( ConstructorError, "Vertical.translate(): Invalid number of parameters." ); - return NULL; - } - HCATCH - - Py_RETURN_NONE; - } - - // --------------------------------------------------------------- // PyVertical Attribute Method table. @@ -184,7 +157,6 @@ extern "C" { , { "setX" , (PyCFunction)PyVertical_setX , METH_VARARGS, "Modify the segment X position." } , { "setDySource", (PyCFunction)PyVertical_setDySource, METH_VARARGS, "Modify the segment source Y offset." } , { "setDyTarget", (PyCFunction)PyVertical_setDyTarget, METH_VARARGS, "Modify the segment target Y offset." } - , { "translate" , (PyCFunction)PyVertical_translate , METH_VARARGS, "Translates the Vertical segment of dx and dy." } , { "destroy" , (PyCFunction)PyVertical_destroy , METH_NOARGS , "Destroy associated hurricane object, the python object remains." } , {NULL, NULL, 0, NULL} /* sentinel */ diff --git a/hurricane/src/viewer/hurricane/viewer/CellWidget.h b/hurricane/src/viewer/hurricane/viewer/CellWidget.h index 05cb7c803..d78a01f16 100644 --- a/hurricane/src/viewer/hurricane/viewer/CellWidget.h +++ b/hurricane/src/viewer/hurricane/viewer/CellWidget.h @@ -51,7 +51,6 @@ class QAction; namespace Hurricane { using std::vector; - using std::unary_function; using std::shared_ptr; class Technology; @@ -638,7 +637,7 @@ namespace Hurricane { bool _historyEnable; }; public: - class FindStateName : public unary_function< const shared_ptr&, bool > { + class FindStateName { public: inline FindStateName ( const Name& ); inline bool operator() ( const shared_ptr& ); @@ -1130,8 +1129,7 @@ namespace Hurricane { inline CellWidget::FindStateName::FindStateName ( const Name& cellHierName ) - : unary_function< const shared_ptr&, bool >() - , _cellHierName(cellHierName) + : _cellHierName(cellHierName) { } diff --git a/ips/Makefile b/ips/Makefile new file mode 100644 index 000000000..6abab8382 --- /dev/null +++ b/ips/Makefile @@ -0,0 +1,56 @@ +## IPs wheel packages build Makefile + +### Environment variables and venv setup +PYTHON3 := python3 +DIST_PATH := ../dist +VENV_PATH := ../.venv + +venv := . ${VENV_PATH}/bin/activate; +pip_install := $(venv) pip3 install --upgrade +venv_python := $(venv) ${PYTHON3} + +PACKAGES := pip setuptools build wheel cibuildwheel + +venv_setup: + ${PYTHON3} -m venv ${VENV_PATH} + $(foreach pkg,$(PACKAGES),$(pip_install) $(pkg);) + +### IPs +IPS = lsxram + +define build_ip +$(1): venv_setup + $(venv_python) -m build -w -o ${DIST_PATH} $(1) 2>&1 | tee -a $(1)_build.log +endef + +# Generate build targets +$(foreach ip,$(IPS),$(eval $(call build_ip,$(ip)))) + +### All target +all: $(IPS) + @echo "### Finished building all cells wheel packages" + +## Uninstall target +define uninstall_ips +uninstall-$(1): + $(venv) pip3 uninstall -y ips_$(1) +endef + +$(foreach ip,$(IPS),$(eval $(call uninstall_ips,$(ip)))) + +uninstall: $(foreach ip,$(IPS),uninstall-$(ip)) + @echo "### Uninstalled all IPs wheel packages" + +### Clean target +define clean_target +clean-$(1): + @rm -rf $(1)/{build,*.egg-info} + @rm -f $(1)_build.log +endef + +# Generate clean targets +$(foreach ip,$(IPS),$(eval $(call clean_target,$(ip)))) + +clean: $(foreach ip,$(IPS),clean-$(ip)) + @find . -type f -name "*.log" -delete + @echo "### Cleaned up all IPs wheel packages" diff --git a/ips/lsxram/MANIFEST.in b/ips/lsxram/MANIFEST.in new file mode 100644 index 000000000..7fb834fba --- /dev/null +++ b/ips/lsxram/MANIFEST.in @@ -0,0 +1 @@ +recursive-include coriolis * diff --git a/ips/lsxram/coriolis/__init__.py b/ips/lsxram/coriolis/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/ips/lsxram/coriolis/ips/__init__.py b/ips/lsxram/coriolis/ips/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/ips/lsxram/coriolis/ips/lsxram/__init__.py b/ips/lsxram/coriolis/ips/lsxram/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_c/__init__.py b/ips/lsxram/coriolis/ips/lsxram/sram_c/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_c/sram_w2r2.c b/ips/lsxram/coriolis/ips/lsxram/sram_c/sram_w2r2.c new file mode 100644 index 000000000..2593f1373 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_c/sram_w2r2.c @@ -0,0 +1,813 @@ +#include +#include + +char *FNAME = "sram_w2r2"; + +unsigned NBW; // number of words +unsigned NBB; // number of bits +char *PHINS_REF = NULL; // first instance of each column + +char *M_NFF = "sram_w2r2nff"; +char *M_CFF = "sram_w2r2nffct"; +char *M_NOA = "sram_noa2a22"; +char *M_COA = "sram_noa2a22ct"; +char *M_MCT = "sram_mxct"; +char *M_DEC = "sram_w2dec4"; +char *M_INV = "sram_w2inv"; + +#define INAMEV(colname,cell,bit) str("%s_%s_%d", colname,cell,bit) +#define INAME(colname,cell) str("%s_%s", colname,cell) + +#define DOSYMY ((++symy)%2)?SYM_Y:NOSYM +#define NOSYMY ((symy)%2)?SYM_Y:NOSYM +#define XFIRST 'x' +#define YFIRST 'y' + +//-------------------------------------------------------------------------------------------------- +// General Purpose Functions +//-------------------------------------------------------------------------------------------------- + +void usage(char *cmd) +{ + fprintf(stderr, "\nUsage: genlib %s \n\n", cmd); + fprintf(stderr, " : nb of words 2,4,8\n"); + fprintf(stderr, " : number of bits 1,4,8\n\n"); + exit(1); +} + +char *inttostr(int entier) +{ + char *str = (char *) alloca(32 * sizeof(char)); + sprintf(str, "%d", entier); + return namealloc(str); +} + +char *bin(int n, int size) { + char *str = alloca(size+1); + str[size] = 0; + for (int i = size - 1; i >= 0; i--) { + str[i] = (n & 1) ? '1' : '0'; + n >>= 1; + } + return namealloc(str); +} + +char *str(char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + char *str = (char *) alloca(256 * sizeof(char)); + vsnprintf(str, 256, fmt, ap); + va_end(ap); + return namealloc(str); +} + +int in(int val, size_t size, ...) +{ + va_list ap; + va_start(ap, size); + int res=0; + for(; size; size--) { + int n = va_arg(ap, int); + if (val == n) + res=1; + } + va_end(ap); + return res; +} + +//-------------------------------------------------------------------------------------------------- +// Route DataPath Data & Addresses +//-------------------------------------------------------------------------------------------------- + +void PHSEG_WE_DT(char * cell, char * port[], size_t nbp, int nbr) +{ + long x1, y1, x2, y2; + char *iname1 = str("w%d_w%d_%s", 0, 1, cell); + char *iname2 = str("w%d_w%d_%s", NBW-2, NBW-1, cell); + long xmin = GENLIB_GET_REF_X(iname1,"vss0"); + long xmax = GENLIB_GET_REF_X(iname2,"vss1"); + for (int p = 0; p < nbp; p++ ) { // foreach input port + char *ref1 = str("w%s_0", port[p]); + char *ref2 = str("w%s_1", port[p]); + char *pname = str("w%s", port[p]); + y1 = GENLIB_GET_REF_Y(iname1,ref1); + y2 = GENLIB_GET_REF_Y(iname2,ref2); + GENLIB_PHSEG(CALU2, 2, pname, xmin, y1, xmax, y2); // PUT a CALU2 connecting all + } +} + +void PHSEG_CK_DT(char * cell, int nbr) +{ + char *iname1 = str("w%d_w%d_%s", 0, 1, cell); + char *iname2 = str("w%d_w%d_%s", NBW-2, NBW-1, cell); + long xmin = GENLIB_GET_REF_X(iname1,"vss0"); + long xmax = GENLIB_GET_REF_X(iname2,"vss1"); + long x, y; + for (int w = 0; w < NBW ; w += 2) { // foreach word + for (int r = 0; r < nbr ; r++) { // foreach ref + char *iname = str("w%d_w%d_%s", w, w+1, cell); + char *ref = str("ck%di", r); + x = GENLIB_GET_REF_X(iname,ref); + y = GENLIB_GET_REF_Y(iname,ref); + GENLIB_PHVIA(CONT_VIA, x, y); // put a VIA + } + } + GENLIB_PHSEG(CALU2, 2, "ck", xmin, y, xmax, y); // PUT a CALU2 connecting all +} + +void PHSEG_AXAY_DT(char * cell, char * port[], size_t nbp) +{ + char *iname1 = str("w%d_w%d_cff", 0, 1); + char *iname2 = str("w%d_w%d_cff", NBW-2, NBW-1); + long xmin = GENLIB_GET_REF_X(iname1,"vss0"); + long xmax = GENLIB_GET_REF_X(iname2,"vss1"); + for (int p = 0; p < nbp; p++ ) { // foreach input port + char *iname = str("w%d_w%d_%s", 0, 1, cell); + char *ref1 = str("a%s10", port[p]); + char *ref2 = str("a%s20", port[p]); + long y1 = GENLIB_GET_REF_Y(iname,ref1); + long y2 = GENLIB_GET_REF_Y(iname,ref2); + char * pname1 = str("a%s[1]", port[p]); + char * pname2 = str("a%s[2]", port[p]); + GENLIB_PHSEG(CALU2, 2, pname1, xmin, y1, xmax, y1); // PUT a CALU2 connecting all + GENLIB_PHSEG(CALU2, 2, pname2, xmin, y2, xmax, y2); // PUT a CALU2 connecting all + } +} + +void PHSEG_AX0AY0_DT(char * cell, char * port[], size_t nbp) +{ + char *iname1 = str("w%d_w%d_%s", 0, 1, cell); + char *iname2 = str("w%d_w%d_%s", NBW-2, NBW-1, cell); + long xmin = GENLIB_GET_REF_X(iname1,"vss0"); + long xmax = GENLIB_GET_REF_X(iname2,"vss1"); + long x0, y0, x1, y1; + for (int p = 0; p < nbp; p++ ) { // foreach input port + for (int w = 0; w < NBW ; w += 2) { // foreach word + char *iname = str("w%d_w%d_%s", w, w+1, cell); + char *ref1 = str("a%s1", port[p]); + char *ref0 = str("a%s0", port[p]); + x0 = GENLIB_GET_REF_X(iname,ref0); + y0 = GENLIB_GET_REF_Y(iname,ref0); + x1 = GENLIB_GET_REF_X(iname,ref1); + y1 = GENLIB_GET_REF_Y(iname,ref1); + GENLIB_PHVIA(CONT_VIA2, x0, y0); // put a VIA + GENLIB_PHVIA(CONT_VIA2, x1, y1); // put a VIA + GENLIB_PHVIA(CONT_VIA, x1, y1); // put a VIA + GENLIB_PHSEG(ALU3, 2, "", x0, y0, x1, y1); + } + char * pname = str("a%s[0]", port[p]); + GENLIB_PHSEG(CALU2, 2, pname, xmin, y0, xmax, y0); // PUT a CALU2 connecting all + } +} + +void PHSEG_AZ0AT0_DT(char * cell, char * port[], size_t nbp, int nbr) +{ + char *iname1 = str("w%d_w%d_cff", 0, 1, cell); + char *iname2 = str("w%d_w%d_cff", NBW-2, NBW-1, cell); + long xmin = GENLIB_GET_REF_X(iname1,"vss0"); + long xmax = GENLIB_GET_REF_X(iname2,"vss1"); + long x, y; + for (int p = 0; p < nbp; p++ ) { // foreach input port + for (int w = 0; w < NBW ; w += 2) { // foreach word + for (int r = 0; r < nbr ; r++) { // foreach ref + char *iname = str("w%d_w%d_%s", w, w+1, cell); + char *ref = str("a%s_%d0", port[p], r); + x = GENLIB_GET_REF_X(iname,ref); + y = GENLIB_GET_REF_Y(iname,ref); + GENLIB_PHVIA(CONT_VIA2, x, y); // put a VIA + GENLIB_PHVIA(CONT_VIA, x, y); // put a VIA + } + } + char * pname = str("a%s[0]", port[p]); + GENLIB_PHSEG(CALU2, 2, pname, xmin, y, xmax, y); // PUT a CALU2 connecting all + } +} + +void PHSEG_AZ1AT1_DT(char * cell, char * port[], size_t nbp, int nbr) +{ + char *iname1 = str("w%d_w%d_cff", 0, 1, cell); + char *iname2 = str("w%d_w%d_cff", NBW-2, NBW-1, cell); + long xmin = GENLIB_GET_REF_X(iname1,"vss0"); + long xmax = GENLIB_GET_REF_X(iname2,"vss1"); + long x, y; + for (int p = 0; p < nbp; p++ ) { // foreach input port + char *iname, *refi, *refq; + long y12i, x23i, y23i, x23q, y23q, x67i, y67i, x67q, y67q; + for (int w = 0; w < NBW ; w += 2) { // foreach word + for (int r = 0; r < nbr ; r++) { // foreach ref + char *iname = str("w%d_w%d_dec", w, w+1); + char *ref = str("a%s_%d1", port[p], r); + x = GENLIB_GET_REF_X(iname,ref); + y = GENLIB_GET_REF_Y(iname,ref); + GENLIB_PHVIA(CONT_VIA, x, y); // put a VIA + } + } + if (NBW == 2) { + iname = str("w0_w1_inv"); + refi = str("i0_%d",((strcmp(port[p],"z"))==0)?3:2); + y12i = GENLIB_GET_REF_Y(iname, refi); + } + if (NBW > 2) { + iname = str("w2_w3_inv"); + if (strcmp(port[p],"z")==0) { + refi = "i0_3"; + refq = "nq0_3"; + } else { + refi = "i1_2"; + refq = "nq1_2"; + } + x23i = GENLIB_GET_REF_X(iname, refi); + y23i = GENLIB_GET_REF_Y(iname, refi); + x23q = GENLIB_GET_REF_X(iname, refq); + y23q = GENLIB_GET_REF_Y(iname, refq); + GENLIB_PHVIA(CONT_VIA, x23i, y23i); + GENLIB_PHVIA(CONT_VIA, x23q, y23q); + } + if (NBW > 4) { + iname = str("w6_w7_inv"); + if (strcmp(port[p],"z")==0) { + refi = "i0_3"; + refq = "nq0_3"; + } else { + refi = "i1_2"; + refq = "nq1_2"; + } + x67i = GENLIB_GET_REF_X(iname, refi); + y67i = GENLIB_GET_REF_Y(iname, refi); + x67q = GENLIB_GET_REF_X(iname, refq); + y67q = GENLIB_GET_REF_Y(iname, refq); + GENLIB_PHVIA(CONT_VIA, x67i, y67i); + GENLIB_PHVIA(CONT_VIA, x67q, y67q); + } + + char * pname = str("a%s[1]", port[p]); + switch (NBW) { + case 2: + GENLIB_PHSEG(CALU2, 2, pname, xmin, y12i, xmax, y12i); + break; + case 4: + GENLIB_PHSEG(CALU2, 2, pname, xmax, y23i, x23i, y23i); + GENLIB_PHSEG(ALU2, 2, "", x23q, y23q, xmin, y23q); + break; + case 8: + GENLIB_PHSEG(ALU2, 2, "", xmin, y23i, x23q, y23i); + GENLIB_PHSEG(ALU2, 2, "", x23i, y23q, x67q, y23q); + GENLIB_PHSEG(CALU2, 2, pname, x67i, y23q, xmax, y23q); + break; + } + } +} + +void PHSEG_AZ2AT2_DT(char * cell, char * port[], size_t nbp, int nbr) +{ + char *iname1 = str("w%d_w%d_cff", 0, 1, cell); + char *iname2 = str("w%d_w%d_cff", NBW-2, NBW-1, cell); + long xmin = GENLIB_GET_REF_X(iname1,"vss0"); + long xmax = GENLIB_GET_REF_X(iname2,"vss1"); + long x, y; + for (int p = 0; p < nbp; p++ ) { // foreach input port + char *iname, *refi, *refq; + long y12i, x45i, y45i, x45q, y45q; + for (int w = 0; w < NBW ; w += 2) { // foreach word + for (int r = 0; r < nbr ; r++) { // foreach ref + char *iname = str("w%d_w%d_dec", w, w+1); + char *ref = str("a%s_%d2", port[p], r); + x = GENLIB_GET_REF_X(iname,ref); + y = GENLIB_GET_REF_Y(iname,ref); + GENLIB_PHVIA(CONT_VIA, x, y); // put a VIA + } + } + if (NBW < 8) { + iname = str("w0_w1_inv"); + refi = str("i0_%d",((strcmp(port[p],"z"))==0)?1:0); + y12i = GENLIB_GET_REF_Y(iname, refi); + } + if (NBW > 4) { + iname = str("w4_w5_inv"); + if (strcmp(port[p],"z")==0) { + refi = "i0_1"; + refq = "nq0_1"; + } else { + refi = "i1_0"; + refq = "nq1_0"; + } + x45i = GENLIB_GET_REF_X(iname, refi); + y45i = GENLIB_GET_REF_Y(iname, refi); + x45q = GENLIB_GET_REF_X(iname, refq); + y45q = GENLIB_GET_REF_Y(iname, refq); + GENLIB_PHVIA(CONT_VIA, x45i, y45i); + GENLIB_PHVIA(CONT_VIA, x45q, y45q); + } + char * pname = str("a%s[2]", port[p]); + if (NBW < 8) { + GENLIB_PHSEG(CALU2, 2, pname, xmin, y12i, xmax, y12i); + } else { + GENLIB_PHSEG(ALU2, 2, "", xmin, y45q, x45q, y45q); + GENLIB_PHSEG(CALU2, 2, pname, x45i, y45i, xmax, y45i); + } + } +} + +void PHSEG_IN_DT(char * cell, char * port[], size_t nbp, int nbr) +{ + char *iname1 = str("w%d_w%d_%s_0", 0, 1, cell); + char *iname2 = str("w%d_w%d_%s_0", NBW-2, NBW-1, cell); + long xmin = GENLIB_GET_REF_X(iname1,"vss0"); + long xmax = GENLIB_GET_REF_X(iname2,"vss1"); + long x, y; + for (int p = 0; p < nbp; p++ ) { // foreach input port + for (int b = 0; b < NBB ; b++) { // foreach bit + for (int w = 0; w < NBW ; w += 2) { // foreach word + for (int r = 0; r < nbr ; r++) { // foreach ref + char *iname = str("w%d_w%d_%s_%d", w, w+1, cell, b); + char *ref = str("i%s%d", port[p], r); + x = GENLIB_GET_REF_X(iname,ref); + y = GENLIB_GET_REF_Y(iname,ref); + GENLIB_PHVIA(CONT_VIA, x, y); // put a VIA + } + } + char * pname = str("i%s[%d]", port[p], b); + GENLIB_PHSEG(CALU2, 2, pname, xmin, y, xmax, y); // PUT a CALU2 connecting all + } + } +} + +void PHSEG_OUT_DT(char * cnff, char *cnoa, char * port[], size_t nbp) +{ + char *iname1 = str("w%d_w%d_%s_0", 0, 1, cnff); + char *iname2 = str("w%d_w%d_%s_0", NBW-2, NBW-1, cnff); + long xmin = GENLIB_GET_REF_X(iname1,"vss0"); + long xmax = GENLIB_GET_REF_X(iname2,"vss1"); + for (int p = 0; p < nbp; p++ ) { // foreach output port + for (int b = 0; b < NBB ; b++) { // foreach bit + long x01, x23, x45, x67; + long x12, x34, x56; + long x120, x121, x340, x341, x560, x561; + long y01, y23, y45, y67; + long y12, y34, y56; + long y120, y121, y340, y341, y560, y561; + char * inff; + char * inoa; + char * nffname = str("nq%s", port[p]); + char * noaname = str("i%s", port[p]); + switch (NBW) { // Put VIAs on nff cells + case 8: + inff = str("w6_w7_%s_%d", cnff, b); + x67 = GENLIB_GET_REF_X(inff,nffname); + y67 = GENLIB_GET_REF_Y(inff,nffname); + GENLIB_PHVIA(CONT_VIA, x67, y67); + inff = str("w4_w5_%s_%d", cnff, b); + x45 = GENLIB_GET_REF_X(inff,nffname); + y45 = GENLIB_GET_REF_Y(inff,nffname); + GENLIB_PHVIA(CONT_VIA, x45, y45); + case 4: + inff = str("w2_w3_%s_%d", cnff, b); + x23 = GENLIB_GET_REF_X(inff,nffname); + y23 = GENLIB_GET_REF_Y(inff,nffname); + GENLIB_PHVIA(CONT_VIA, x23, y23); + case 2: + inff = str("w0_w1_%s_%d", cnff, b); + x01 = GENLIB_GET_REF_X(inff,nffname); + y01 = GENLIB_GET_REF_Y(inff,nffname); + GENLIB_PHVIA(CONT_VIA, x01, y01); + } + switch (NBW) { // Put VIAs on noa cells + case 8: + inoa = str("mx_56_%s_%d", cnoa, b); + x560 = GENLIB_GET_REF_X(inoa,str("%s0",noaname)); + y560 = GENLIB_GET_REF_Y(inoa,str("%s0",noaname)); + GENLIB_PHVIA(CONT_VIA, x560, y560); + x561 = GENLIB_GET_REF_X(inoa,str("%s1",noaname)); + y561 = GENLIB_GET_REF_Y(inoa,str("%s1",noaname)); + GENLIB_PHVIA(CONT_VIA, x561, y561); + x56 = GENLIB_GET_REF_X(inoa,nffname); + y56 = GENLIB_GET_REF_Y(inoa,nffname); + GENLIB_PHVIA(CONT_VIA, x56, y56); + inoa = str("mx_34_%s_%d", cnoa, b); + x340 = GENLIB_GET_REF_X(inoa,str("%s0o",noaname)); + y340 = GENLIB_GET_REF_Y(inoa,str("%s0o",noaname)); + GENLIB_PHVIA(CONT_VIA, x340, y340); + x341 = GENLIB_GET_REF_X(inoa,str("%s1o",noaname)); + y341 = GENLIB_GET_REF_Y(inoa,str("%s1o",noaname)); + GENLIB_PHVIA(CONT_VIA, x341, y341); + x34 = GENLIB_GET_REF_X(inoa,str("%so",nffname)); + y34 = GENLIB_GET_REF_Y(inoa,str("%so",nffname)); + GENLIB_PHVIA(CONT_VIA, x34, y34); + if (((y34-y340) % 5) == 3) { + GENLIB_PHSEG(ALU2, 2, "", x34, y34, x34, y34+2); + y34 = y34 + 2; + } else if (((y34-y340) % 5) == -3) { + GENLIB_PHSEG(ALU2, 2, "", x34, y34, x34, y34-2); + y34 = y34 - 2; + } + case 4: + inoa = str("mx_12_%s_%d", cnoa, b); + x120 = GENLIB_GET_REF_X(inoa,str("%s0",noaname)); + y120 = GENLIB_GET_REF_Y(inoa,str("%s0",noaname)); + GENLIB_PHVIA(CONT_VIA, x120, y120); + x121 = GENLIB_GET_REF_X(inoa,str("%s1",noaname)); + y121 = GENLIB_GET_REF_Y(inoa,str("%s1",noaname)); + GENLIB_PHVIA(CONT_VIA, x121, y121); + x12 = GENLIB_GET_REF_X(inoa,nffname); + y12 = GENLIB_GET_REF_Y(inoa,nffname); + GENLIB_PHVIA(CONT_VIA, x12, y12); + } + switch (NBW) { + case 8: + GENLIB_PHSEG(ALU2, 2, "", x12, y12, x340, y340); + GENLIB_PHSEG(ALU2, 2, "", x56, y56, x341, y341); + GENLIB_PHSEG(ALU2, 2, "", x45, y45, x560, y560); + GENLIB_PHSEG(ALU2, 2, "", x67, y67, x561, y561); + case 4: + GENLIB_PHSEG(ALU2, 2, "", x01, y01, x120, y120); + GENLIB_PHSEG(ALU2, 2, "", x23, y23, x121, y121); + } + char * pname = str("nq%s[%d]", port[p], b); + long y = (NBW == 2) ? y01 : (NBW == 4) ? y12 : y34; + GENLIB_PHSEG(CALU2, 2, pname, xmin, y, xmax, y); // PUT a CALU2 connecting all + } + } +} + +void RouteDT() +{ + char * in_port[] = { "z", "t" }; + char * out_port[] = { "x", "y" }; + PHSEG_CK_DT ("cff", 2); + PHSEG_AZ0AT0_DT ("dec", in_port, sizeof(in_port)/sizeof(char*), 2); + PHSEG_AZ1AT1_DT ("dec", in_port, sizeof(in_port)/sizeof(char*), 2); + PHSEG_AZ2AT2_DT ("dec", in_port, sizeof(in_port)/sizeof(char*), 2); + PHSEG_AX0AY0_DT ("cff", out_port, sizeof(in_port)/sizeof(char*)); + PHSEG_AXAY_DT ("cff", out_port, sizeof(in_port)/sizeof(char*)); + PHSEG_WE_DT ("cff", in_port, sizeof(in_port)/sizeof(char*), 2); + PHSEG_IN_DT ("nff", in_port, sizeof(in_port)/sizeof(char*), 2); + PHSEG_OUT_DT ("nff", "noa", out_port, sizeof(out_port)/sizeof(char*)); +} + +//-------------------------------------------------------------------------------------------------- +// Route DataPath Control +//-------------------------------------------------------------------------------------------------- + +void PHSEG_CT(char *iname, char *c1, char *c2, char *ref1, char *ref2, int metal) +{ + char *ins1 = INAME(iname, c1); + long x1 = GENLIB_GET_REF_X(ins1, ref1); + long y1 = GENLIB_GET_REF_Y(ins1, ref1); + + char *ins2 = INAME(iname, c2); + long x2 = GENLIB_GET_REF_X(ins2, ref2); + long y2 = GENLIB_GET_REF_Y(ins2, ref2); + + if (metal == 1) GENLIB_PHVIA(CONT_VIA, x1, y1); + GENLIB_PHVIA(CONT_VIA, x2, y2); + GENLIB_PHVIA(CONT_VIA2, x1, y1); + GENLIB_PHSEG(ALU3, 2, "", x1, y1, x1, y2); + + if (x1 == x2) { + GENLIB_PHVIA(CONT_VIA2, x2, y2); + } else { + GENLIB_PHVIA(CONT_VIA2, x1, y2); + GENLIB_PHSEG(ALU2, 2, "", x1, y2, x2, y2); + } +} + +void PHSEG_DL(char *iname, char *c1, char *c2, char *ref1, char* ref2, int leg) +{ + char *ins1 = INAME(iname, c1); + long x1 = GENLIB_GET_REF_X(ins1, ref1); + long y1 = GENLIB_GET_REF_Y(ins1, ref1); + + char *ins2 = INAME(iname, c2); + long x2 = GENLIB_GET_REF_X(ins2, ref2); + long y2 = GENLIB_GET_REF_Y(ins2, ref2); + + long x3 = x1 + leg; + + GENLIB_PHVIA(CONT_VIA, x1, y1); + GENLIB_PHSEG(ALU2, 2, "", x1, y1, x3, y1); + GENLIB_PHVIA(CONT_VIA2, x3, y1); + GENLIB_PHSEG(ALU3, 2, "", x3, y1, x3, y2); + GENLIB_PHVIA(CONT_VIA2, x3, y2); + GENLIB_PHSEG(ALU2, 2, "", x3, y2, x2, y2); + GENLIB_PHVIA(CONT_VIA2, x2, y2); + GENLIB_PHVIA(CONT_VIA, x2, y2); +} + +void PHSEG_DP(char *iname, char *c1, char *c2, char *ref1, char* ref2, char direction) +{ + long x1, y1, x2, y2; + char *ins1 = INAMEV(iname, c1, 0); + char *ins2 ; + + x1 = GENLIB_GET_REF_X(ins1, ref1); + y1 = GENLIB_GET_REF_Y(ins1, ref1); + GENLIB_PHVIA(CONT_VIA, x1, y1); + GENLIB_PHVIA(CONT_VIA2, x1, y1); + + for (int bit = 1; bit != NBB; bit++) { + ins2 = INAMEV(iname, c1, bit); + x2 = GENLIB_GET_REF_X(ins2, ref1); + y2 = GENLIB_GET_REF_Y(ins2, ref1); + GENLIB_PHVIA(CONT_VIA, x2, y2); + GENLIB_PHVIA(CONT_VIA2, x2, y2); + } + + GENLIB_PHSEG(ALU3, 2, "", x1, y1, x2, y2); + x1 = x2; + y1 = y2; + + ins2 = INAME(iname, c2); + x2 = GENLIB_GET_REF_X(ins2, ref2); + y2 = GENLIB_GET_REF_Y(ins2, ref2); + + if (x1 == x2) { + GENLIB_PHSEG(ALU3, 2, "", x1, y1, x2, y2); + GENLIB_PHVIA(CONT_VIA2, x2, y2); + } else { + if (direction == XFIRST) { + GENLIB_PHVIA(CONT_VIA2, x1, y1); + GENLIB_PHSEG(ALU2, 2, "", x1, y1, x2, y1); + GENLIB_PHVIA(CONT_VIA2, x2, y1); + GENLIB_PHSEG(ALU3, 2, "", x2, y1, x2, y2); + GENLIB_PHVIA(CONT_VIA2, x2, y2); + } else { + GENLIB_PHSEG(ALU3, 2, "", x1, y1, x1, y2); + GENLIB_PHVIA(CONT_VIA2, x1, y2); + GENLIB_PHSEG(ALU2, 2, "", x1, y2, x2, y2); + } + } + GENLIB_PHVIA(CONT_VIA, x2, y2); +} + + +void RouteMem(char *iname) +{ + PHSEG_DP (iname, "nff", "cff", "ck0", "ck0", YFIRST); + PHSEG_DP (iname, "nff", "cff", "ck1", "ck1", YFIRST); + PHSEG_DP (iname, "nff", "cff", "nck0", "nck0", YFIRST); + PHSEG_DP (iname, "nff", "cff", "nck1", "nck1", YFIRST); + PHSEG_DP (iname, "nff", "cff", "nwt1", "nwt1", YFIRST); + PHSEG_DP (iname, "nff", "cff", "wt1", "wt1", YFIRST); + PHSEG_DP (iname, "nff", "cff", "nwt0", "nwt0", YFIRST); + PHSEG_DP (iname, "nff", "cff", "wt0", "wt0", YFIRST); + PHSEG_DP (iname, "nff", "cff", "nwd0", "nwd0", YFIRST); + PHSEG_DP (iname, "nff", "cff", "wd0", "wd0", YFIRST); + PHSEG_DP (iname, "nff", "cff", "wd1", "wd1", YFIRST); + PHSEG_DP (iname, "nff", "cff", "nwd1", "nwd1", YFIRST); + PHSEG_DP (iname, "nff", "cff", "nwz0", "nwz0", XFIRST); + PHSEG_DP (iname, "nff", "cff", "wz0", "wz0", YFIRST); + PHSEG_DP (iname, "nff", "cff", "nwz1", "nwz1", XFIRST); + PHSEG_DP (iname, "nff", "cff", "wz1", "wz1", YFIRST); + + // words are missnamed 0 is 1, and 0 is 0 + // I do not want to change the layout, thus it is simpler to change the addr routing + + PHSEG_DP (iname, "nff", "cff", "rx1", "rx0", YFIRST); + PHSEG_DP (iname, "nff", "cff", "rx0", "rx1", YFIRST); + PHSEG_DP (iname, "nff", "cff", "ry1", "ry0", YFIRST); + PHSEG_DP (iname, "nff", "cff", "ry0", "ry1", YFIRST); + + //if (NBW > 2) { + PHSEG_CT (iname, "cff", "dec", "wt_0", "wt_0", 2); + PHSEG_CT (iname, "cff", "dec", "wt_1", "wt_1", 2); + PHSEG_CT (iname, "cff", "dec", "wz_0", "wz_0", 2); + PHSEG_CT (iname, "cff", "dec", "wz_1", "wz_1", 2); + + PHSEG_DL (iname, "cff", "dec", "at0", "at0", 6); + PHSEG_CT (iname, "cff", "dec", "at1", "at1", 1); + PHSEG_CT (iname, "cff", "dec", "az0", "az0", 1); + PHSEG_CT (iname, "cff", "dec", "az1", "az1", 1); + // } +} + +void RouteMux(char *iname, int ref) +{ + PHSEG_DP (iname, "noa", "coa", "rx0", "rx0", XFIRST); + PHSEG_DP (iname, "noa", "coa", "rx1", "rx1", YFIRST); + PHSEG_DP (iname, "noa", "coa", "ry0", "ry0", YFIRST); + PHSEG_DP (iname, "noa", "coa", "ry1", "ry1", XFIRST); + PHSEG_CT (iname, "coa", "coa", str("ay%d", ref), "ay0", 2); + PHSEG_CT (iname, "coa", "coa", str("ax%d", ref), "ax0", 2); +} + +//-------------------------------------------------------------------------------------------------- +// Place +//-------------------------------------------------------------------------------------------------- + +void PlaceMem(char sym, char *iname) +{ + int symy = (sym == NOSYM) ? 1 : 0; + + if (PHINS_REF == NULL) { + GENLIB_PLACE(M_NFF, INAMEV(iname,"nff",0), DOSYMY, 0, 0); + } else { + GENLIB_DEF_PHINS(PHINS_REF); + GENLIB_PLACE_RIGHT(M_NFF, INAMEV(iname,"nff",0), DOSYMY); + } + for (int bit = 1; bit != NBB; bit ++) { + GENLIB_PLACE_TOP(M_NFF, INAMEV(iname,"nff",bit), DOSYMY); + } + GENLIB_PLACE_TOP(M_CFF, INAME(iname,"cff"), DOSYMY); + + //if (NBW > 2) { + GENLIB_PLACE_TOP(M_INV, INAME(iname,"inv"), DOSYMY); + GENLIB_PLACE_RIGHT(M_DEC, INAME(iname,"dec"), NOSYMY); + //} + PHINS_REF = INAMEV(iname,"nff",0); +} + +void PlaceMux(char sym, char *iname) +{ + int symy = (sym == NOSYM) ? 1 : 0; + + GENLIB_DEF_PHINS(PHINS_REF); + GENLIB_PLACE_RIGHT(M_NOA, INAMEV(iname,"noa",0), DOSYMY); + for (int bit = 1; bit != NBB; bit ++) { + GENLIB_PLACE_TOP(M_NOA, INAMEV(iname,"noa",bit), DOSYMY); + } + GENLIB_PLACE_TOP(M_COA, INAME(iname,"coa"), DOSYMY); + // if (NBW > 2) + GENLIB_PLACE_TOP(M_MCT, INAME(iname,"mct"), DOSYMY); + PHINS_REF = INAMEV(iname,"noa",0); +} + +//-------------------------------------------------------------------------------------------------- +// Route Supply Both Horizotal and Vertical +//-------------------------------------------------------------------------------------------------- + +void RouteSupply(void) +{ + int b, y; + char * iname = str("w%d_w%d_%s", NBW-2, NBW-1, "cff"); + long xmax = GENLIB_GET_REF_X(iname,"vss1"); + + for(b = 0, y = 0; b < NBB + 2; b+=2, y+=100) { + GENLIB_PHSEG (CALU1, 4, "vdd", 0, y, xmax, y); + GENLIB_PHSEG (CALU1, 4, "vss", 0, y+50, xmax, y+50); + } + GENLIB_PHSEG (CALU1, 4, "vdd", 0, y, xmax, y); +} + +//-------------------------------------------------------------------------------------------------- +// Create Figure +//-------------------------------------------------------------------------------------------------- + +void create_vbe(void) +{ + FILE * vbe = fopen (str("sram_w2r2_%dx%d.vbe", NBW, NBB), "w"); + + int s = (NBW==2) ? 6 : (NBW==4) ? 4 : 0 ; + int logNBW = (NBW==2) ? 1 : (NBW==4) ? 2 : 3 ; + + fprintf(vbe, + "ENTITY sram_w2r2_%dx%d IS\n" + "PORT (\n" + "\n" + " at : in bit_vector(2 DOWNTO 0) ;\n" + " az : in bit_vector(2 DOWNTO 0) ;\n" + " ax : in bit_vector(2 DOWNTO 0) ;\n" + " ay : in bit_vector(2 DOWNTO 0) ;\n" + " wt : in BIT;\n" + " wz : in BIT;\n" + "\n" + " it : in bit_vector(%d DOWNTO 0) ;\n" + " iz : in bit_vector(%d DOWNTO 0) ;\n" + "\n" + " nqx : out bit_vector(%d DOWNTO 0) ;\n" + " nqy : out bit_vector(%d DOWNTO 0) ;\n" + "\n" + " ck : in BIT;\n" + "\n" + " vdd : in BIT;\n" + " vss : in BIT\n" + ");\n" + "END sram_w2r2_%dx%d;\n" + "\n" + "ARCHITECTURE behaviour_data_flow OF sram_w2r2_%dx%d IS\n" + "\n" + ,NBW,NBB,NBB-1,NBB-1,NBB-1,NBB-1,NBW,NBB,NBW,NBB); + + for (int w = 0; w < NBW; w++) + fprintf(vbe, + " SIGNAL w%dm, w%ds : REG_VECTOR(%d DOWNTO 0) REGISTER;\n", w, w, NBB-1); + + fprintf(vbe, + "\n" + "BEGIN\n" + "\n" + " Masters : BLOCK (NOT(ck))\n" + " BEGIN\n" + ); + + for (int w = 0; w < NBW; w++) + fprintf(vbe, + " w%dm <= GUARDED NOT(it) when (wt AND at = \"%s\") else NOT(iz) when (wz AND az = \"%s\") else NOT(w%ds);\n" + , w, bin(s+w,3), bin(s+w,3), w); + + fprintf(vbe, + " END BLOCK Masters;\n" + "\n" + " Slaves : BLOCK (ck)\n" + " BEGIN\n" + ); + + for (int w = 0; w < NBW; w++) + fprintf(vbe, + " w%ds <= GUARDED NOT(w%dm);\n" + , w, w); + + fprintf(vbe, + " END BLOCK Slaves;\n" + "\n" + " nqx <= %s w0s when (ax(%d downto 0) = \"%s\")\n" + , (NBW == 4) ? "" : "NOT", logNBW-1, bin(0,logNBW)); + + for (int w = 1; w < NBW-1; w++) + fprintf(vbe, + " else %s w%ds when (ax(%d downto 0) = \"%s\")\n" + , (NBW == 4) ? "" : "NOT", w, logNBW-1, bin(w,logNBW)); + + fprintf(vbe, + " else %s w%ds;\n" + "\n" + , (NBW == 4) ? "" : "NOT", NBW-1); + + fprintf(vbe, + " nqy <= %s w0s when (ay(%d downto 0) = \"%s\")\n" + , (NBW == 4) ? "" : "NOT", logNBW-1, bin(0,logNBW)); + + for (int w = 1; w < NBW-1; w++) + fprintf(vbe, + " else %s w%ds when (ay(%d downto 0) = \"%s\")\n" + , (NBW == 4) ? "" : "NOT", w, logNBW-1, bin(w,logNBW)); + + fprintf(vbe, + " else %s w%ds;\n" + "\n" + , (NBW == 4) ? "" : "NOT", NBW-1); + + fprintf(vbe, + "END;\n"); +} + +int main(int argc, char *argv[]) +{ + +//- Check Arguments + + if (argc != 3) + usage(argv[0]); + + NBW = atoi(argv[1]); + NBB = atoi(argv[2]); + + int sym = SYM_Y; + + if (!in(NBW,3,2,4,8)) usage(argv[0]); + if (!in(NBB,5,2,4,8,16,32)) usage(argv[0]); + + create_vbe(); + +//- Create Figure + + GENLIB_DEF_PHFIG(str("%s_%dx%d", FNAME, NBW, NBB)); + +//- Place Cells + + PlaceMem (sym, "w0_w1"); + if (NBW > 2) { + PlaceMux (sym, "mx_12"); + PlaceMem (sym, "w2_w3"); + } + if (NBW > 4) { + PlaceMux (sym, "mx_34"); + PlaceMem (sym, "w4_w5"); + PlaceMux (sym, "mx_56"); + PlaceMem (sym, "w6_w7"); + } + +//- Route Cells Most of Control Signals + + RouteMem ("w0_w1"); + if (NBW > 2) { + RouteMux ("mx_12",1); + RouteMem ("w2_w3"); + } + if (NBW > 4) { + RouteMux ("mx_34",2); + RouteMem ("w4_w5"); + RouteMux ("mx_56",1); + RouteMem ("w6_w7"); + } + +//- Create Data And Addresses + + RouteDT (); + RouteSupply(); + +//- Create Abutment Box and Save figure + + GENLIB_DEF_AB(0, 0, 0, 0); + GENLIB_SAVE_PHFIG(); +} diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_c/sram_w2r2_4x2.ap b/ips/lsxram/coriolis/ips/lsxram/sram_c/sram_w2r2_4x2.ap new file mode 100644 index 000000000..e3f7a8b10 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_c/sram_w2r2_4x2.ap @@ -0,0 +1,622 @@ +V ALLIANCE : 6 +H sram_w2r2_4x2,P,23/ 8/2024,100 +A 0,0,47000,20000 +S 0,20000,47000,20000,400,vdd,RIGHT,CALU1 +S 0,15000,47000,15000,400,vss,RIGHT,CALU1 +S 0,10000,47000,10000,400,vdd,RIGHT,CALU1 +S 0,5000,47000,5000,400,vss,RIGHT,CALU1 +S 0,0,47000,0,400,vdd,RIGHT,CALU1 +S 0,5900,47000,5900,200,nqy 1,RIGHT,CALU2 +S 23300,6400,37000,6400,200,,LEFT,ALU2 +S 11000,6400,21300,6400,200,,RIGHT,ALU2 +S 0,4100,47000,4100,200,nqy 0,RIGHT,CALU2 +S 23300,3600,37000,3600,200,,LEFT,ALU2 +S 11000,3600,21300,3600,200,,RIGHT,ALU2 +S 0,8900,47000,8900,200,nqx 1,RIGHT,CALU2 +S 25700,8400,36000,8400,200,,LEFT,ALU2 +S 10000,8400,24000,8400,200,,RIGHT,ALU2 +S 0,1100,47000,1100,200,nqx 0,RIGHT,CALU2 +S 25700,1600,36000,1600,200,,LEFT,ALU2 +S 10000,1600,24000,1600,200,,RIGHT,ALU2 +S 0,6900,47000,6900,200,it 1,RIGHT,CALU2 +S 0,3100,47000,3100,200,it 0,RIGHT,CALU2 +S 0,7400,47000,7400,200,iz 1,RIGHT,CALU2 +S 0,2600,47000,2600,200,iz 0,RIGHT,CALU2 +S 0,13900,47000,13900,200,wt,RIGHT,CALU2 +S 0,14400,47000,14400,200,wz,RIGHT,CALU2 +S 0,9900,47000,9900,200,ay 2,RIGHT,CALU2 +S 0,10900,47000,10900,200,ay 1,RIGHT,CALU2 +S 0,14900,47000,14900,200,ax 2,RIGHT,CALU2 +S 0,10400,47000,10400,200,ax 1,RIGHT,CALU2 +S 0,11400,47000,11400,200,ay 0,RIGHT,CALU2 +S 37000,11400,37000,12900,200,,UP,ALU3 +S 11000,11400,11000,12900,200,,UP,ALU3 +S 0,11900,47000,11900,200,ax 0,RIGHT,CALU2 +S 36000,11900,36000,12900,200,,UP,ALU3 +S 10000,11900,10000,12900,200,,UP,ALU3 +S 0,16700,47000,16700,200,at 2,RIGHT,CALU2 +S 0,17200,47000,17200,200,az 2,RIGHT,CALU2 +S 0,17700,27500,17700,200,,LEFT,ALU2 +S 28000,17700,47000,17700,200,at 1,LEFT,CALU2 +S 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6900,7900,6900,13400,200,,UP,ALU3 +S 6900,2100,6900,7900,200,,UP,ALU3 +S 14600,7900,14600,13400,200,,UP,ALU3 +S 14600,2100,14600,7900,200,,UP,ALU3 +S 14100,7900,14100,13400,200,,UP,ALU3 +S 14100,2100,14100,7900,200,,UP,ALU3 +S 18700,7900,18700,13400,200,,UP,ALU3 +S 18700,2100,18700,7900,200,,UP,ALU3 +S 2300,7900,2300,13400,200,,UP,ALU3 +S 2300,2100,2300,7900,200,,UP,ALU3 +S 19200,7900,19200,13400,200,,UP,ALU3 +S 19200,2100,19200,7900,200,,UP,ALU3 +S 1800,7900,1800,13400,200,,UP,ALU3 +S 1800,2100,1800,7900,200,,UP,ALU3 +I 28500,15000,sram_w2dec4,w2_w3_dec,NOSYM +I 26000,15000,sram_w2inv,w2_w3_inv,NOSYM +I 26000,10000,sram_w2r2nffct,w2_w3_cff,SYM_Y +I 26000,5000,sram_w2r2nff,w2_w3_nff_1,NOSYM +I 26000,0,sram_w2r2nff,w2_w3_nff_0,SYM_Y +I 21000,15000,sram_mxct,mx_12_mct,NOSYM +I 21000,10000,sram_noa2a22ct,mx_12_coa,SYM_Y +I 21000,5000,sram_noa2a22,mx_12_noa_1,NOSYM +I 21000,0,sram_noa2a22,mx_12_noa_0,SYM_Y +I 2500,15000,sram_w2dec4,w0_w1_dec,NOSYM +I 0,15000,sram_w2inv,w0_w1_inv,NOSYM +I 0,10000,sram_w2r2nffct,w0_w1_cff,SYM_Y +I 0,5000,sram_w2r2nff,w0_w1_nff_1,NOSYM +I 0,0,sram_w2r2nff,w0_w1_nff_0,SYM_Y +V 22400,5900,CONT_VIA,* +V 23300,6400,CONT_VIA,* +V 21300,6400,CONT_VIA,* +V 11000,6400,CONT_VIA,* +V 37000,6400,CONT_VIA,* +V 22400,4100,CONT_VIA,* +V 23300,3600,CONT_VIA,* +V 21300,3600,CONT_VIA,* +V 11000,3600,CONT_VIA,* +V 37000,3600,CONT_VIA,* +V 25200,8900,CONT_VIA,* +V 25700,8400,CONT_VIA,* +V 24000,8400,CONT_VIA,* +V 10000,8400,CONT_VIA,* +V 36000,8400,CONT_VIA,* +V 25200,1100,CONT_VIA,* +V 25700,1600,CONT_VIA,* +V 24000,1600,CONT_VIA,* +V 10000,1600,CONT_VIA,* +V 36000,1600,CONT_VIA,* +V 40100,6900,CONT_VIA,* +V 32900,6900,CONT_VIA,* +V 14100,6900,CONT_VIA,* +V 6900,6900,CONT_VIA,* +V 40100,3100,CONT_VIA,* +V 32900,3100,CONT_VIA,* +V 14100,3100,CONT_VIA,* +V 6900,3100,CONT_VIA,* +V 41700,7400,CONT_VIA,* +V 31300,7400,CONT_VIA,* +V 15700,7400,CONT_VIA,* +V 5300,7400,CONT_VIA,* +V 41700,2600,CONT_VIA,* +V 31300,2600,CONT_VIA,* +V 15700,2600,CONT_VIA,* +V 5300,2600,CONT_VIA,* +V 37000,12900,CONT_VIA,* +V 37000,12900,CONT_VIA2,* +V 37000,11400,CONT_VIA2,* +V 11000,12900,CONT_VIA,* +V 11000,12900,CONT_VIA2,* +V 11000,11400,CONT_VIA2,* +V 36000,12900,CONT_VIA,* +V 36000,12900,CONT_VIA2,* +V 36000,11900,CONT_VIA2,* +V 10000,12900,CONT_VIA,* +V 10000,12900,CONT_VIA2,* +V 10000,11900,CONT_VIA2,* +V 39500,16700,CONT_VIA,* +V 34700,16700,CONT_VIA,* +V 13500,16700,CONT_VIA,* +V 8700,16700,CONT_VIA,* +V 43300,17200,CONT_VIA,* +V 30900,17200,CONT_VIA,* +V 17300,17200,CONT_VIA,* +V 4900,17200,CONT_VIA,* +V 27500,17700,CONT_VIA,* +V 28000,17700,CONT_VIA,* +V 39000,17700,CONT_VIA,* +V 35200,17700,CONT_VIA,* +V 13000,17700,CONT_VIA,* +V 9200,17700,CONT_VIA,* +V 26300,18200,CONT_VIA,* +V 26800,18200,CONT_VIA,* +V 43800,18200,CONT_VIA,* +V 30400,18200,CONT_VIA,* +V 17800,18200,CONT_VIA,* +V 4400,18200,CONT_VIA,* +V 36800,18700,CONT_VIA,* +V 36800,18700,CONT_VIA2,* +V 36200,18700,CONT_VIA,* +V 36200,18700,CONT_VIA2,* +V 10800,18700,CONT_VIA,* +V 10800,18700,CONT_VIA2,* +V 10200,18700,CONT_VIA,* +V 10200,18700,CONT_VIA2,* +V 46600,19200,CONT_VIA,* +V 46600,19200,CONT_VIA2,* +V 28900,19200,CONT_VIA,* +V 28900,19200,CONT_VIA2,* +V 20600,19200,CONT_VIA,* +V 20600,19200,CONT_VIA2,* +V 2900,19200,CONT_VIA,* +V 2900,19200,CONT_VIA2,* +V 45200,12400,CONT_VIA,* +V 27800,12400,CONT_VIA,* +V 19200,12400,CONT_VIA,* +V 1800,12400,CONT_VIA,* +V 44000,16200,CONT_VIA2,* +V 44000,13400,CONT_VIA2,* +V 41700,16200,CONT_VIA,* +V 44000,13400,CONT_VIA,* +V 29000,16200,CONT_VIA2,* +V 29000,13400,CONT_VIA2,* +V 32500,16200,CONT_VIA,* +V 29000,13400,CONT_VIA,* +V 41700,15700,CONT_VIA2,* +V 41700,13400,CONT_VIA2,* +V 41100,15700,CONT_VIA,* +V 41700,13400,CONT_VIA,* +V 33100,15700,CONT_VIA,* +V 33100,15700,CONT_VIA2,* +V 31900,15700,CONT_VIA2,* +V 31900,13400,CONT_VIA2,* +V 31300,13400,CONT_VIA,* +V 42800,15700,CONT_VIA2,* +V 42800,14400,CONT_VIA2,* +V 42800,15700,CONT_VIA,* +V 31400,15700,CONT_VIA2,* +V 31400,14400,CONT_VIA2,* +V 31400,15700,CONT_VIA,* +V 40000,15700,CONT_VIA2,* +V 40000,13900,CONT_VIA2,* +V 40000,15700,CONT_VIA,* +V 34000,16200,CONT_VIA2,* +V 34000,13900,CONT_VIA2,* +V 34000,16200,CONT_VIA,* +V 37500,12900,CONT_VIA,* +V 38000,12900,CONT_VIA2,* +V 38000,7900,CONT_VIA2,* +V 38000,7900,CONT_VIA,* +V 38000,2100,CONT_VIA2,* +V 38000,2100,CONT_VIA,* +V 38000,13400,CONT_VIA,* +V 37500,13400,CONT_VIA2,* +V 37500,7900,CONT_VIA2,* +V 37500,7900,CONT_VIA,* +V 37500,2100,CONT_VIA2,* +V 37500,2100,CONT_VIA,* +V 35000,12900,CONT_VIA,* +V 35500,12900,CONT_VIA2,* +V 35500,7900,CONT_VIA2,* +V 35500,7900,CONT_VIA,* +V 35500,2100,CONT_VIA2,* +V 35500,2100,CONT_VIA,* +V 35500,13400,CONT_VIA,* +V 35000,13400,CONT_VIA2,* +V 35000,7900,CONT_VIA2,* +V 35000,7900,CONT_VIA,* +V 35000,2100,CONT_VIA2,* +V 35000,2100,CONT_VIA,* +V 42800,12900,CONT_VIA,* +V 41200,12900,CONT_VIA2,* +V 41200,7900,CONT_VIA2,* +V 41200,7900,CONT_VIA,* +V 41200,2100,CONT_VIA2,* +V 41200,2100,CONT_VIA,* +V 43300,12900,CONT_VIA,* +V 43300,12900,CONT_VIA2,* +V 43300,7900,CONT_VIA2,* +V 41700,7900,CONT_VIA2,* +V 41700,7900,CONT_VIA2,* +V 41700,7900,CONT_VIA,* +V 41700,2100,CONT_VIA2,* +V 41700,2100,CONT_VIA,* +V 30200,12900,CONT_VIA,* +V 31800,12900,CONT_VIA2,* +V 31800,7900,CONT_VIA2,* +V 31800,7900,CONT_VIA,* +V 31800,2100,CONT_VIA2,* +V 31800,2100,CONT_VIA,* +V 29700,12900,CONT_VIA,* +V 29700,12900,CONT_VIA2,* +V 29700,7900,CONT_VIA2,* +V 31300,7900,CONT_VIA2,* +V 31300,7900,CONT_VIA2,* +V 31300,7900,CONT_VIA,* +V 31300,2100,CONT_VIA2,* +V 31300,2100,CONT_VIA,* +V 39500,13400,CONT_VIA,* +V 39500,13400,CONT_VIA2,* +V 39500,7900,CONT_VIA2,* +V 39500,7900,CONT_VIA,* +V 39500,2100,CONT_VIA2,* +V 39500,2100,CONT_VIA,* +V 39000,13400,CONT_VIA,* +V 39000,13400,CONT_VIA2,* +V 39000,7900,CONT_VIA2,* +V 39000,7900,CONT_VIA,* +V 39000,2100,CONT_VIA2,* +V 39000,2100,CONT_VIA,* +V 34000,13400,CONT_VIA,* +V 34000,13400,CONT_VIA2,* +V 34000,7900,CONT_VIA2,* +V 34000,7900,CONT_VIA,* +V 34000,2100,CONT_VIA2,* +V 34000,2100,CONT_VIA,* +V 33500,13400,CONT_VIA,* +V 33500,13400,CONT_VIA2,* +V 33500,7900,CONT_VIA2,* +V 33500,7900,CONT_VIA,* +V 33500,2100,CONT_VIA2,* +V 33500,2100,CONT_VIA,* +V 32400,13400,CONT_VIA,* +V 32400,13400,CONT_VIA2,* +V 32400,7900,CONT_VIA2,* +V 32400,7900,CONT_VIA,* +V 32400,2100,CONT_VIA2,* +V 32400,2100,CONT_VIA,* +V 32900,13400,CONT_VIA,* +V 32900,13400,CONT_VIA2,* +V 32900,7900,CONT_VIA2,* +V 32900,7900,CONT_VIA,* +V 32900,2100,CONT_VIA2,* +V 32900,2100,CONT_VIA,* +V 40600,13400,CONT_VIA,* +V 40600,13400,CONT_VIA2,* +V 40600,7900,CONT_VIA2,* +V 40600,7900,CONT_VIA,* +V 40600,2100,CONT_VIA2,* +V 40600,2100,CONT_VIA,* +V 40100,13400,CONT_VIA,* +V 40100,13400,CONT_VIA2,* +V 40100,7900,CONT_VIA2,* +V 40100,7900,CONT_VIA,* +V 40100,2100,CONT_VIA2,* +V 40100,2100,CONT_VIA,* +V 44700,13400,CONT_VIA,* +V 44700,13400,CONT_VIA2,* +V 44700,7900,CONT_VIA2,* +V 44700,7900,CONT_VIA,* +V 44700,2100,CONT_VIA2,* +V 44700,2100,CONT_VIA,* +V 28300,13400,CONT_VIA,* +V 28300,13400,CONT_VIA2,* +V 28300,7900,CONT_VIA2,* +V 28300,7900,CONT_VIA,* +V 28300,2100,CONT_VIA2,* +V 28300,2100,CONT_VIA,* +V 45200,13400,CONT_VIA,* +V 45200,13400,CONT_VIA2,* +V 45200,7900,CONT_VIA2,* +V 45200,7900,CONT_VIA,* +V 45200,2100,CONT_VIA2,* +V 45200,2100,CONT_VIA,* +V 27800,13400,CONT_VIA,* +V 27800,13400,CONT_VIA2,* +V 27800,7900,CONT_VIA2,* +V 27800,7900,CONT_VIA,* +V 27800,2100,CONT_VIA2,* +V 27800,2100,CONT_VIA,* +V 24900,13400,CONT_VIA2,* +V 24900,10400,CONT_VIA2,* +V 24900,13400,CONT_VIA,* +V 22300,13400,CONT_VIA2,* +V 22300,10900,CONT_VIA2,* +V 22300,13400,CONT_VIA,* +V 21600,12900,CONT_VIA,* +V 21600,12900,CONT_VIA2,* +V 21600,7900,CONT_VIA2,* +V 22300,7900,CONT_VIA2,* +V 22300,7900,CONT_VIA2,* +V 22300,7900,CONT_VIA,* +V 22300,2100,CONT_VIA2,* +V 22300,2100,CONT_VIA,* +V 22800,12900,CONT_VIA,* +V 22800,12900,CONT_VIA2,* +V 22800,7900,CONT_VIA2,* +V 22800,7900,CONT_VIA,* +V 22800,2100,CONT_VIA2,* +V 22800,2100,CONT_VIA,* +V 24200,12900,CONT_VIA,* +V 24200,12900,CONT_VIA2,* +V 24200,7900,CONT_VIA2,* +V 24200,7900,CONT_VIA,* +V 24200,2100,CONT_VIA2,* +V 24200,2100,CONT_VIA,* +V 25400,12900,CONT_VIA,* +V 25400,12900,CONT_VIA2,* +V 25400,7900,CONT_VIA2,* +V 24700,7900,CONT_VIA2,* +V 24700,7900,CONT_VIA2,* +V 24700,7900,CONT_VIA,* +V 24700,2100,CONT_VIA2,* +V 24700,2100,CONT_VIA,* +V 18000,16200,CONT_VIA2,* +V 18000,13400,CONT_VIA2,* +V 15700,16200,CONT_VIA,* +V 18000,13400,CONT_VIA,* +V 3000,16200,CONT_VIA2,* +V 3000,13400,CONT_VIA2,* +V 6500,16200,CONT_VIA,* +V 3000,13400,CONT_VIA,* +V 15700,15700,CONT_VIA2,* +V 15700,13400,CONT_VIA2,* +V 15100,15700,CONT_VIA,* +V 15700,13400,CONT_VIA,* +V 7100,15700,CONT_VIA,* +V 7100,15700,CONT_VIA2,* +V 5900,15700,CONT_VIA2,* +V 5900,13400,CONT_VIA2,* +V 5300,13400,CONT_VIA,* +V 16800,15700,CONT_VIA2,* +V 16800,14400,CONT_VIA2,* +V 16800,15700,CONT_VIA,* +V 5400,15700,CONT_VIA2,* +V 5400,14400,CONT_VIA2,* +V 5400,15700,CONT_VIA,* +V 14000,15700,CONT_VIA2,* +V 14000,13900,CONT_VIA2,* +V 14000,15700,CONT_VIA,* +V 8000,16200,CONT_VIA2,* +V 8000,13900,CONT_VIA2,* +V 8000,16200,CONT_VIA,* +V 11500,12900,CONT_VIA,* +V 12000,12900,CONT_VIA2,* +V 12000,7900,CONT_VIA2,* +V 12000,7900,CONT_VIA,* +V 12000,2100,CONT_VIA2,* +V 12000,2100,CONT_VIA,* +V 12000,13400,CONT_VIA,* +V 11500,13400,CONT_VIA2,* +V 11500,7900,CONT_VIA2,* +V 11500,7900,CONT_VIA,* +V 11500,2100,CONT_VIA2,* +V 11500,2100,CONT_VIA,* +V 9000,12900,CONT_VIA,* +V 9500,12900,CONT_VIA2,* +V 9500,7900,CONT_VIA2,* +V 9500,7900,CONT_VIA,* +V 9500,2100,CONT_VIA2,* +V 9500,2100,CONT_VIA,* +V 9500,13400,CONT_VIA,* +V 9000,13400,CONT_VIA2,* +V 9000,7900,CONT_VIA2,* +V 9000,7900,CONT_VIA,* +V 9000,2100,CONT_VIA2,* +V 9000,2100,CONT_VIA,* +V 16800,12900,CONT_VIA,* +V 15200,12900,CONT_VIA2,* +V 15200,7900,CONT_VIA2,* +V 15200,7900,CONT_VIA,* +V 15200,2100,CONT_VIA2,* +V 15200,2100,CONT_VIA,* +V 17300,12900,CONT_VIA,* +V 17300,12900,CONT_VIA2,* +V 17300,7900,CONT_VIA2,* +V 15700,7900,CONT_VIA2,* +V 15700,7900,CONT_VIA2,* +V 15700,7900,CONT_VIA,* +V 15700,2100,CONT_VIA2,* +V 15700,2100,CONT_VIA,* +V 4200,12900,CONT_VIA,* +V 5800,12900,CONT_VIA2,* +V 5800,7900,CONT_VIA2,* +V 5800,7900,CONT_VIA,* +V 5800,2100,CONT_VIA2,* +V 5800,2100,CONT_VIA,* +V 3700,12900,CONT_VIA,* +V 3700,12900,CONT_VIA2,* +V 3700,7900,CONT_VIA2,* +V 5300,7900,CONT_VIA2,* +V 5300,7900,CONT_VIA2,* +V 5300,7900,CONT_VIA,* +V 5300,2100,CONT_VIA2,* +V 5300,2100,CONT_VIA,* +V 13500,13400,CONT_VIA,* +V 13500,13400,CONT_VIA2,* +V 13500,7900,CONT_VIA2,* +V 13500,7900,CONT_VIA,* +V 13500,2100,CONT_VIA2,* +V 13500,2100,CONT_VIA,* +V 13000,13400,CONT_VIA,* +V 13000,13400,CONT_VIA2,* +V 13000,7900,CONT_VIA2,* +V 13000,7900,CONT_VIA,* +V 13000,2100,CONT_VIA2,* +V 13000,2100,CONT_VIA,* +V 8000,13400,CONT_VIA,* +V 8000,13400,CONT_VIA2,* +V 8000,7900,CONT_VIA2,* +V 8000,7900,CONT_VIA,* +V 8000,2100,CONT_VIA2,* +V 8000,2100,CONT_VIA,* +V 7500,13400,CONT_VIA,* +V 7500,13400,CONT_VIA2,* +V 7500,7900,CONT_VIA2,* +V 7500,7900,CONT_VIA,* +V 7500,2100,CONT_VIA2,* +V 7500,2100,CONT_VIA,* +V 6400,13400,CONT_VIA,* +V 6400,13400,CONT_VIA2,* +V 6400,7900,CONT_VIA2,* +V 6400,7900,CONT_VIA,* +V 6400,2100,CONT_VIA2,* +V 6400,2100,CONT_VIA,* +V 6900,13400,CONT_VIA,* +V 6900,13400,CONT_VIA2,* +V 6900,7900,CONT_VIA2,* +V 6900,7900,CONT_VIA,* +V 6900,2100,CONT_VIA2,* +V 6900,2100,CONT_VIA,* +V 14600,13400,CONT_VIA,* +V 14600,13400,CONT_VIA2,* +V 14600,7900,CONT_VIA2,* +V 14600,7900,CONT_VIA,* +V 14600,2100,CONT_VIA2,* +V 14600,2100,CONT_VIA,* +V 14100,13400,CONT_VIA,* +V 14100,13400,CONT_VIA2,* +V 14100,7900,CONT_VIA2,* +V 14100,7900,CONT_VIA,* +V 14100,2100,CONT_VIA2,* +V 14100,2100,CONT_VIA,* +V 18700,13400,CONT_VIA,* +V 18700,13400,CONT_VIA2,* +V 18700,7900,CONT_VIA2,* +V 18700,7900,CONT_VIA,* +V 18700,2100,CONT_VIA2,* +V 18700,2100,CONT_VIA,* +V 2300,13400,CONT_VIA,* +V 2300,13400,CONT_VIA2,* +V 2300,7900,CONT_VIA2,* +V 2300,7900,CONT_VIA,* +V 2300,2100,CONT_VIA2,* +V 2300,2100,CONT_VIA,* +V 19200,13400,CONT_VIA,* +V 19200,13400,CONT_VIA2,* +V 19200,7900,CONT_VIA2,* +V 19200,7900,CONT_VIA,* +V 19200,2100,CONT_VIA2,* +V 19200,2100,CONT_VIA,* +V 1800,13400,CONT_VIA,* +V 1800,13400,CONT_VIA2,* +V 1800,7900,CONT_VIA2,* +V 1800,7900,CONT_VIA,* +V 1800,2100,CONT_VIA2,* +V 1800,2100,CONT_VIA,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_c/sram_w2r2_4x2.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_c/sram_w2r2_4x2.vbe new file mode 100644 index 000000000..19a66e560 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_c/sram_w2r2_4x2.vbe @@ -0,0 +1,59 @@ +ENTITY sram_w2r2_4x2 IS +PORT ( + + at : in bit_vector(2 DOWNTO 0) ; + az : in bit_vector(2 DOWNTO 0) ; + ax : in bit_vector(2 DOWNTO 0) ; + ay : in bit_vector(2 DOWNTO 0) ; + wt : in BIT; + wz : in BIT; + + it : in bit_vector(1 DOWNTO 0) ; + iz : in bit_vector(1 DOWNTO 0) ; + + nqx : out bit_vector(1 DOWNTO 0) ; + nqy : out bit_vector(1 DOWNTO 0) ; + + ck : in BIT; + + vdd : in BIT; + vss : in BIT +); +END sram_w2r2_4x2; + +ARCHITECTURE behaviour_data_flow OF sram_w2r2_4x2 IS + + SIGNAL w0m, w0s : REG_VECTOR(1 DOWNTO 0) REGISTER; + SIGNAL w1m, w1s : REG_VECTOR(1 DOWNTO 0) REGISTER; + SIGNAL w2m, w2s : REG_VECTOR(1 DOWNTO 0) REGISTER; + SIGNAL w3m, w3s : REG_VECTOR(1 DOWNTO 0) REGISTER; + +BEGIN + + Masters : BLOCK (NOT(ck)) + BEGIN + w0m <= GUARDED NOT(it) when (wt AND at = "100") else NOT(iz) when (wz AND az = "100") else NOT(w0s); + w1m <= GUARDED NOT(it) when (wt AND at = "101") else NOT(iz) when (wz AND az = "101") else NOT(w1s); + w2m <= GUARDED NOT(it) when (wt AND at = "110") else NOT(iz) when (wz AND az = "110") else NOT(w2s); + w3m <= GUARDED NOT(it) when (wt AND at = "111") else NOT(iz) when (wz AND az = "111") else NOT(w3s); + END BLOCK Masters; + + Slaves : BLOCK (ck) + BEGIN + w0s <= GUARDED NOT(w0m); + w1s <= GUARDED NOT(w1m); + w2s <= GUARDED NOT(w2m); + w3s <= GUARDED NOT(w3m); + END BLOCK Slaves; + + nqx <= w0s when (ax(1 downto 0) = "00") + else w1s when (ax(1 downto 0) = "01") + else w2s when (ax(1 downto 0) = "10") + else w3s; + + nqy <= w0s when (ay(1 downto 0) = "00") + else w1s when (ay(1 downto 0) = "01") + else w2s when (ay(1 downto 0) = "10") + else w3s; + +END; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/__init__.py b/ips/lsxram/coriolis/ips/lsxram/sram_g/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_nmxr2_2x1.ap b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_nmxr2_2x1.ap new file mode 100644 index 000000000..f6bdfd0a0 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_nmxr2_2x1.ap @@ -0,0 +1,51 @@ +V ALLIANCE : 6 +H sram_nmxr2_2x1,P,17/ 8/2024,100 +A 0,0,5000,10000 +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 0,10000,5000,10000,400,vss,RIGHT,CALU1 +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +S 3900,8400,3900,10000,200,ax,UP,CALU3 +S 1800,2900,1800,7900,200,*,DOWN,ALU3 +S 3200,2900,3200,7900,200,*,UP,ALU3 +S 600,2900,1300,2900,200,*,RIGHT,ALU2 +S 3700,2900,4400,2900,200,*,LEFT,ALU2 +S 600,2900,600,7900,200,*,DOWN,ALU3 +S 4400,2900,4400,7900,200,*,DOWN,ALU3 +S 1400,900,5000,900,200,nqy,LEFT,CALU2 +S 4200,3900,5000,3900,200,nqx,LEFT,CALU2 +S 1300,8400,1300,10000,200,ay,UP,CALU3 +S 2300,1400,5000,1400,200,iy1,LEFT,CALU2 +S 0,1400,300,1400,200,iy0,LEFT,CALU2 +S 0,3400,2700,3400,200,ix0,LEFT,CALU2 +S 4700,3400,5000,3400,200,ix1,LEFT,CALU2 +I 0,5000,sram_noa2a22ct,i,SYM_Y +I 0,0,sram_noa2a22,a,NOSYM +V 3900,8400,CONT_VIA,* +V 3900,8400,CONT_VIA2,* +V 4400,2900,CONT_VIA2,* +V 600,2900,CONT_VIA2,* +V 4400,7900,CONT_VIA,* +V 4400,7900,CONT_VIA2,* +V 600,7900,CONT_VIA,* +V 600,7900,CONT_VIA2,* +V 3200,7900,CONT_VIA,* +V 1800,7900,CONT_VIA,* +V 1800,7900,CONT_VIA2,* +V 3200,7900,CONT_VIA2,* +V 1400,900,CONT_VIA,* +V 4200,3900,CONT_VIA,* +V 1300,8400,CONT_VIA2,* +V 1300,8400,CONT_VIA,* +V 2300,1400,CONT_VIA,* +V 3700,2900,CONT_VIA,* +V 3200,2900,CONT_VIA,* +V 3700,2900,CONT_VIA2,* +V 3200,2900,CONT_VIA2,* +V 1300,2900,CONT_VIA,* +V 1800,2900,CONT_VIA,* +V 1300,2900,CONT_VIA2,* +V 1800,2900,CONT_VIA2,* +V 300,1400,CONT_VIA,* +V 2700,3400,CONT_VIA,* +V 4700,3400,CONT_VIA,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_nmxr2_2x1.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_nmxr2_2x1.vbe new file mode 100644 index 000000000..c97ab6d21 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_nmxr2_2x1.vbe @@ -0,0 +1,24 @@ +ENTITY sram_nmxr2_2x1 IS +PORT ( + ax : in BIT; + ix0 : in BIT; + ix1 : in BIT; + nqx : out BIT; + + ay : in BIT; + iy0 : in BIT; + iy1 : in BIT; + nqy : out BIT; + + vdd : in BIT; + vss : in BIT +); +END sram_nmxr2_2x1; + +ARCHITECTURE behaviour_data_flow OF sram_nmxr2_2x1 IS +BEGIN + + nqx <= NOT( (ix1 AND ax) OR (ix0 AND NOT(ax)) ); + nqy <= NOT( (iy1 AND ay) OR (iy0 AND NOT(ay)) ); + +END; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1.ap b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1.ap new file mode 100644 index 000000000..0f3e522ae --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1.ap @@ -0,0 +1,236 @@ +V ALLIANCE : 6 +H sram_w2r2_2x1,P,18/ 8/2024,100 +A 0,0,21000,15000 +S 0,4400,21000,4400,200,ay 2,RIGHT,CALU2 +S 0,4900,21000,4900,200,ax 2,RIGHT,CALU2 +S 2100,10600,2100,14400,200,invnq1,DOWN,CALU1 +S 900,10600,900,14400,200,invnq0,DOWN,CALU1 +S 1600,11700,1600,13200,200,invi1,DOWN,CALU1 +S 400,11700,400,13200,200,invi0,DOWN,CALU1 +S 2100,13200,21000,13200,200,az 1,LEFT,CALU2 +S 2100,12700,21000,12700,200,at 1,LEFT,CALU2 +S 900,11700,21000,11700,200,at 2,RIGHT,CALU2 +S 900,12200,21000,12200,200,az 2,RIGHT,CALU2 +S 16800,9400,16800,10700,200,wz,UP,CALU3 +S 14000,8900,14000,10700,200,wt,UP,CALU3 +S 8200,8900,8200,10700,200,wt,UP,CALU3 +S 5400,9400,5400,10700,200,wz,UP,CALU3 +S 11000,6400,11000,15000,200,ay 0,UP,CALU3 +S 10000,6900,10000,15000,200,ax 0,UP,CALU3 +S 0,0,21000,0,400,vss,RIGHT,CALU1 +S 0,10000,21000,10000,400,vss,RIGHT,CALU1 +S 0,13700,21000,13700,200,at 0,LEFT,CALU2 +S 0,1400,21000,1400,200,nqy,RIGHT,CALU2 +S 0,14200,21000,14200,200,az 0,LEFT,CALU2 +S 0,15000,21000,15000,400,vdd,RIGHT,CALU1 +S 0,1900,21000,1900,200,it,RIGHT,CALU2 +S 0,2400,21000,2400,200,iz,RIGHT,CALU2 +S 0,3400,21000,3400,200,nqx,RIGHT,CALU2 +S 0,5000,21000,5000,400,vdd,RIGHT,CALU1 +S 0,5000,21000,5000,400,vdd,RIGHT,CALU1 +S 0,5400,21000,5400,200,ay 1,RIGHT,CALU2 +S 0,5900,21000,5900,200,ax 1,RIGHT,CALU2 +S 0,6400,21000,6400,200,ay 0,RIGHT,CALU2 +S 0,6900,21000,6900,200,ax 0,RIGHT,CALU2 +S 0,7400,21000,7400,200,ck,RIGHT,CALU2 +S 0,8900,21000,8900,200,wt,RIGHT,CALU2 +S 0,9400,21000,9400,200,wz,RIGHT,CALU2 +S 10000,7100,10000,8400,200,ax,DOWN,ALU1 +S 11000,7100,11000,8400,200,ay,DOWN,ALU1 +S 11500,0,11500,5000,200,ry1,UP,CALU3 +S 11500,5000,11500,8400,200,ry1,UP,CALU3 +S 12000,0,12000,5000,200,ry0,UP,CALU3 +S 12000,5000,12000,8400,200,ry0,UP,CALU3 +S 13000,0,13000,5000,200,wd1,UP,CALU3 +S 13000,5000,13000,8400,200,wd1,UP,CALU3 +S 13500,0,13500,5000,200,nwd1,UP,CALU3 +S 13500,5000,13500,8400,200,nwd1,UP,CALU3 +S 14100,0,14100,5000,200,nwt1,UP,CALU3 +S 14100,5000,14100,8400,200,nwt1,UP,CALU3 +S 14600,0,14600,5000,200,wt1,UP,CALU3 +S 14600,5000,14600,8400,200,wt1,UP,CALU3 +S 15100,10700,15700,10700,200,*,RIGHT,ALU2 +S 15200,0,15200,5000,200,wz1,UP,CALU3 +S 15200,5000,15200,7900,200,wz1,UP,CALU3 +S 15200,7900,16800,7900,200,*,RIGHT,ALU2 +S 15700,11200,18000,11200,200,*,RIGHT,ALU2 +S 15700,2900,17300,2900,200,*,LEFT,ALU2 +S 15700,7100,15700,8400,200,at1,UP,ALU1 +S 15700,8400,15700,15000,200,at1,UP,CALU3 +S 17300,0,17300,5000,200,nwz1,UP,CALU3 +S 17300,5000,17300,7900,200,nwz1,UP,CALU3 +S 1800,0,1800,5000,200,ck0,UP,CALU3 +S 18000,6600,18000,8400,200,az1,UP,ALU1 +S 18000,8400,18000,15000,200,az1,UP,CALU3 +S 1800,5000,1800,8400,200,ck0,UP,CALU3 +S 18700,0,18700,5000,200,nck1,UP,CALU3 +S 18700,5000,18700,8400,200,nck1,UP,CALU3 +S 19200,0,19200,5000,200,ck1,UP,CALU3 +S 19200,5000,19200,8400,200,ck1,UP,CALU3 +S 2300,0,2300,5000,200,nck0,UP,CALU3 +S 2300,5000,2300,8400,200,nck0,UP,CALU3 +S 3000,11200,6500,11200,200,*,RIGHT,ALU2 +S 3000,6600,3000,8400,200,az0,UP,ALU1 +S 3000,8400,3000,15000,200,az0,UP,CALU3 +S 3700,0,3700,5000,200,nwz0,UP,CALU3 +S 3700,2900,5300,2900,200,*,RIGHT,ALU2 +S 3700,5000,3700,7900,200,nwz0,UP,CALU3 +S 4200,7900,5800,7900,200,*,RIGHT,ALU2 +S 5300,6600,5300,8400,200,at0,UP,ALU1 +S 5300,8400,5900,8400,200,*,RIGHT,ALU2 +S 5800,0,5800,5000,200,wz0,UP,CALU3 +S 5800,5000,5800,7900,200,wz0,UP,CALU3 +S 5900,10700,7100,10700,200,*,LEFT,ALU2 +S 5900,8400,5900,15000,200,at0,UP,CALU3 +S 6400,0,6400,5000,200,wt0,UP,CALU3 +S 6400,5000,6400,8400,200,wt0,UP,CALU3 +S 6900,0,6900,5000,200,nwt0,UP,CALU3 +S 6900,5000,6900,8400,200,nwt0,UP,CALU3 +S 7500,0,7500,5000,200,nwd0,UP,CALU3 +S 7500,5000,7500,8400,200,nwd0,UP,CALU3 +S 8000,0,8000,5000,200,wd0,UP,CALU3 +S 8000,5000,8000,8400,200,wd0,UP,CALU3 +S 9000,0,9000,5000,200,rx1,DOWN,CALU3 +S 9000,5000,9000,8400,200,rx1,DOWN,CALU3 +S 9500,0,9500,5000,200,rx0,UP,CALU3 +S 9500,5000,9500,8400,200,rx0,UP,CALU3 +I 0,0,sram_w2r2nff,ff,NOSYM +I 0,10000,sram_w2inv,inv01,NOSYM +I 0,5000,sram_w2r2nffct,ctr,SYM_Y +I 2500,10000,sram_w2dec4,dec01,NOSYM +V 13500,11700,CONT_VIA,* +V 8700,11700,CONT_VIA,* +V 10000,3400,CONT_VIA,* +V 10000,6900,CONT_VIA2,* +V 10000,7900,CONT_VIA,* +V 10000,7900,CONT_VIA2,* +V 10200,13700,CONT_VIA,* +V 10800,13700,CONT_VIA,* +V 11000,1400,CONT_VIA,* +V 11000,6400,CONT_VIA2,* +V 11000,7900,CONT_VIA,* +V 11000,7900,CONT_VIA2,* +V 11500,2900,CONT_VIA,* +V 11500,2900,CONT_VIA2,* +V 11500,8400,CONT_VIA,* +V 11500,8400,CONT_VIA2,* +V 12000,2900,CONT_VIA,* +V 12000,2900,CONT_VIA2,* +V 12000,8400,CONT_VIA,* +V 12000,8400,CONT_VIA2,* +V 13000,12700,CONT_VIA,* +V 13000,2900,CONT_VIA,* +V 13000,2900,CONT_VIA2,* +V 13000,8400,CONT_VIA,* +V 13000,8400,CONT_VIA2,* +V 13500,2900,CONT_VIA,* +V 13500,2900,CONT_VIA2,* +V 13500,8400,CONT_VIA,* +V 13500,8400,CONT_VIA2,* +V 14000,10700,CONT_VIA,* +V 14000,10700,CONT_VIA2,* +V 14000,8900,CONT_VIA2,* +V 14100,1900,CONT_VIA,* +V 14100,2900,CONT_VIA,* +V 14100,2900,CONT_VIA2,* +V 14100,8400,CONT_VIA,* +V 14100,8400,CONT_VIA2,* +V 14600,2900,CONT_VIA,* +V 14600,2900,CONT_VIA2,* +V 14600,8400,CONT_VIA,* +V 14600,8400,CONT_VIA2,* +V 15100,10700,CONT_VIA,* +V 15200,2900,CONT_VIA,* +V 15200,2900,CONT_VIA2,* +V 15200,7900,CONT_VIA2,* +V 15700,10700,CONT_VIA2,* +V 15700,11200,CONT_VIA,* +V 15700,2400,CONT_VIA,* +V 15700,2900,CONT_VIA,* +V 15700,8400,CONT_VIA,* +V 15700,8400,CONT_VIA2,* +V 16800,10700,CONT_VIA,* +V 16800,10700,CONT_VIA2,* +V 16800,7900,CONT_VIA,* +V 16800,9400,CONT_VIA2,* +V 17300,12200,CONT_VIA,* +V 17300,2900,CONT_VIA2,* +V 17300,7900,CONT_VIA,* +V 17300,7900,CONT_VIA2,* +V 17800,13200,CONT_VIA,* +V 18000,11200,CONT_VIA2,* +V 18000,8400,CONT_VIA,* +V 18000,8400,CONT_VIA2,* +V 1800,2900,CONT_VIA,* +V 1800,2900,CONT_VIA2,* +V 1800,7400,CONT_VIA,* +V 1800,8400,CONT_VIA,* +V 1800,8400,CONT_VIA2,* +V 18700,2900,CONT_VIA,* +V 18700,2900,CONT_VIA2,* +V 18700,8400,CONT_VIA,* +V 18700,8400,CONT_VIA2,* +V 19200,2900,CONT_VIA,* +V 19200,2900,CONT_VIA2,* +V 19200,7400,CONT_VIA,* +V 19200,8400,CONT_VIA,* +V 19200,8400,CONT_VIA2,* +V 20600,14200,CONT_VIA,* +V 2300,2900,CONT_VIA,* +V 2300,2900,CONT_VIA2,* +V 2300,8400,CONT_VIA,* +V 2300,8400,CONT_VIA2,* +V 2900,14200,CONT_VIA,* +V 3000,11200,CONT_VIA2,* +V 3000,8400,CONT_VIA,* +V 3000,8400,CONT_VIA2,* +V 3700,2900,CONT_VIA2,* +V 3700,7900,CONT_VIA,* +V 3700,7900,CONT_VIA2,* +V 4200,7900,CONT_VIA,* +V 4400,13200,CONT_VIA,* +V 4900,12200,CONT_VIA,* +V 5300,2400,CONT_VIA,* +V 5300,2900,CONT_VIA,* +V 5300,8400,CONT_VIA,* +V 5400,10700,CONT_VIA,* +V 5400,10700,CONT_VIA2,* +V 5400,9400,CONT_VIA2,* +V 5800,2900,CONT_VIA,* +V 5800,2900,CONT_VIA2,* +V 5800,7900,CONT_VIA2,* +V 5900,10700,CONT_VIA2,* +V 5900,8400,CONT_VIA2,* +V 6400,2900,CONT_VIA,* +V 6400,2900,CONT_VIA2,* +V 6400,8400,CONT_VIA,* +V 6400,8400,CONT_VIA2,* +V 6500,11200,CONT_VIA,* +V 6900,1900,CONT_VIA,* +V 6900,2900,CONT_VIA,* +V 6900,2900,CONT_VIA2,* +V 6900,8400,CONT_VIA,* +V 6900,8400,CONT_VIA2,* +V 7100,10700,CONT_VIA,* +V 7500,2900,CONT_VIA,* +V 7500,2900,CONT_VIA2,* +V 7500,8400,CONT_VIA,* +V 7500,8400,CONT_VIA2,* +V 8000,2900,CONT_VIA,* +V 8000,2900,CONT_VIA2,* +V 8000,8400,CONT_VIA,* +V 8000,8400,CONT_VIA2,* +V 8200,10700,CONT_VIA,* +V 8200,10700,CONT_VIA,* +V 8200,10700,CONT_VIA2,* +V 8200,8900,CONT_VIA2,* +V 9000,2900,CONT_VIA,* +V 9000,2900,CONT_VIA2,* +V 9000,8400,CONT_VIA,* +V 9000,8400,CONT_VIA2,* +V 9200,12700,CONT_VIA,* +V 9500,2900,CONT_VIA,* +V 9500,2900,CONT_VIA2,* +V 9500,8400,CONT_VIA,* +V 9500,8400,CONT_VIA2,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1.vbe new file mode 100644 index 000000000..9730f2c07 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1.vbe @@ -0,0 +1,119 @@ +ENTITY sram_w2r2_2x1 IS +PORT ( + + invi0 : in BIT; + invi1 : in BIT; + invnq0 : out BIT; + invnq1 : out BIT; + + at : in bit_vector(0 TO 2) ; + az : in bit_vector(0 TO 2) ; + ax : in bit_vector(0 TO 2) ; + ay : in bit_vector(0 TO 2) ; + wt : in BIT; + wz : in BIT; + + it : in BIT; + iz : in BIT; + + nqx : out BIT; + nqy : out BIT; + + ck : in BIT; + + at0 : inout BIT; + at1 : inout BIT; + az0 : inout BIT; + az1 : inout BIT; + + wt0 : inout BIT; + wt1 : inout BIT; + nwt0 : inout BIT; + nwt1 : inout BIT; + + wz0 : inout BIT; + wz1 : inout BIT; + nwz0 : inout BIT; + nwz1 : inout BIT; + + wd0 : inout BIT; + wd1 : inout BIT; + nwd0 : inout BIT; + nwd1 : inout BIT; + + rx0 : inout BIT; + rx1 : inout BIT; + + ry0 : inout BIT; + ry1 : inout BIT; + + ck0 : inout BIT; + ck1 : inout BIT; + nck0 : inout BIT; + nck1 : inout BIT; + + vdd : in BIT; + vss : in BIT +); +END sram_w2r2_2x1; + +ARCHITECTURE behaviour_data_flow OF sram_w2r2_2x1 IS + SIGNAL ffm1 : REG_BIT REGISTER; + SIGNAL ffs1 : REG_BIT REGISTER; + SIGNAL ffm0 : REG_BIT REGISTER; + SIGNAL ffs0 : REG_BIT REGISTER; + +BEGIN + + invnq1 <= NOT(invi1); + invnq0 <= NOT(invi0); + + at0 <= (at(2) AND at(1) AND at(0) AND wt); -- at = 11 + at1 <= (at(2) AND at(1) AND NOT(at(0)) AND wt); -- at = 10 + az0 <= (az(2) AND az(1) AND az(0) AND wz); -- az = 11 + az1 <= (az(2) AND az(1) AND NOT(az(0)) AND wz); -- az = 10 + + Masters : BLOCK (NOT(ck)) + BEGIN + ffm0 <= GUARDED NOT(it) when at0 + else NOT(iz) when az0 + else NOT(ffs0); + ffm1 <= GUARDED NOT(it) when at1 + else NOT(iz) when az1 + else NOT(ffs1); + END BLOCK Masters; + + Slaves : BLOCK (ck) + BEGIN + ffs0 <= GUARDED NOT(ffm0); + ffs1 <= GUARDED NOT(ffm1); + END BLOCK Slaves; + + nqy <= NOT(ffs1) when ay(0) else NOT(ffs0); + nqx <= NOT(ffs1) when ax(0) else NOT(ffs0); + + wt0 <= at0; + wt1 <= at1; + wz0 <= (az0 AND NOT(at0)); + wz1 <= (az1 AND NOT(at1)); + wd1 <= (NOT(az1) AND NOT(at1)); + wd0 <= (NOT(az0) AND NOT(at0)); + + nwt0 <= NOT(wt0); + nwt1 <= NOT(wt1); + nwz0 <= NOT(wz0); + nwz1 <= NOT(wz1); + nwd1 <= NOT(wd1); + nwd0 <= NOT(wd0); + + rx0 <= NOT(ax(0)); + rx1 <= NOT(rx0); + ry0 <= NOT(ay(0)); + ry1 <= NOT(ry0); + + ck1 <= ck; + ck0 <= ck; + nck1 <= NOT(ck); + nck0 <= NOT(ck); + +END; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_dec.ap b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_dec.ap new file mode 100644 index 000000000..27791213c --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_dec.ap @@ -0,0 +1,178 @@ +V ALLIANCE : 6 +H sram_w2r2_2x1_dec,P,18/ 8/2024,100 +A 0,5000,21000,15000 +S 0,11700,21000,11700,200,at 2,RIGHT,CALU2 +S 0,12200,21000,12200,200,az 2,RIGHT,CALU2 +S 16800,10700,17300,10700,200,*,RIGHT,ALU2 +S 17300,9400,17300,10700,200,wz,UP,ALU3 +S 14000,8900,14000,10700,200,wt,UP,ALU3 +S 8200,8900,8200,10700,200,wt,UP,ALU3 +S 5400,9400,5400,10600,200,wz,UP,ALU3 +S 14600,5000,14600,8400,200,wt1,UP,CALU3 +S 6400,5000,6400,8400,200,wt0,UP,CALU3 +S 18700,5000,18700,8400,200,nck1,UP,CALU3 +S 0,5400,21000,5400,200,ay 1,RIGHT,CALU2 +S 19200,5000,19200,8400,200,ck1,UP,CALU3 +S 17300,5000,17300,7900,200,nwz1,UP,CALU3 +S 15200,5000,15200,7900,200,wz1,UP,CALU3 +S 14100,5000,14100,8400,200,nwt1,UP,CALU3 +S 13500,5000,13500,8400,200,nwd1,UP,CALU3 +S 13000,5000,13000,8400,200,wd1,UP,CALU3 +S 12000,5000,12000,8400,200,ry0,UP,CALU3 +S 11500,5000,11500,8400,200,ry1,UP,CALU3 +S 9500,5000,9500,8400,200,rx0,UP,CALU3 +S 9000,5000,9000,8400,200,rx1,DOWN,CALU3 +S 8000,5000,8000,8400,200,wd0,UP,CALU3 +S 7500,5000,7500,8400,200,nwd0,UP,CALU3 +S 6900,5000,6900,8400,200,nwt0,UP,CALU3 +S 5800,5000,5800,7900,200,wz0,UP,CALU3 +S 3700,5000,3700,7900,200,nwz0,UP,CALU3 +S 2300,5000,2300,8400,200,nck0,UP,CALU3 +S 1800,5000,1800,8400,200,ck0,UP,CALU3 +S 20100,5000,20100,15000,800,vdd,UP,CALU3 +S 4500,5000,4500,15000,800,vss,UP,CALU3 +S 15700,8400,15700,15000,200,at1,UP,CALU3 +S 18000,8400,18000,15000,200,az1,UP,CALU3 +S 5900,8400,5900,15000,200,at0,UP,CALU3 +S 3000,8400,3000,15000,200,az0,UP,CALU3 +S 0,15000,21000,15000,400,vdd,RIGHT,CALU1 +S 0,5000,21000,5000,400,vdd,RIGHT,CALU1 +S 0,10000,21000,10000,400,vss,RIGHT,CALU1 +S 0,5900,21000,5900,200,ax 1,RIGHT,CALU2 +S 0,6400,21000,6400,200,ay 0,RIGHT,CALU2 +S 0,6900,21000,6900,200,ax 0,RIGHT,CALU2 +S 0,7400,21000,7400,200,ck,RIGHT,CALU2 +S 0,8900,21000,8900,200,wt,RIGHT,CALU2 +S 0,9400,21000,9400,200,wz,RIGHT,CALU2 +S 0,13200,21000,13200,200,az 1,LEFT,CALU2 +S 0,12700,21000,12700,200,at 1,LEFT,CALU2 +S 0,13700,21000,13700,200,at 0,LEFT,CALU2 +S 0,14200,21000,14200,200,az 0,LEFT,CALU2 +S 11000,6400,11000,7900,200,*,UP,ALU3 +S 10000,6900,10000,7900,200,*,UP,ALU3 +S 1600,10000,1600,11700,200,*,DOWN,ALU1 +S 400,10000,400,11700,200,*,DOWN,ALU1 +S 5300,8400,5900,8400,200,*,RIGHT,ALU2 +S 3000,6600,3000,8400,200,az0,UP,ALU1 +S 5300,6600,5300,8400,200,at0,UP,ALU1 +S 18000,6600,18000,8400,200,az1,UP,ALU1 +S 15700,7100,15700,8400,200,at1,UP,ALU1 +S 10000,7100,10000,8400,200,ax,DOWN,ALU1 +S 11000,7100,11000,8400,200,ay,DOWN,ALU1 +S 4200,7900,5800,7900,200,*,RIGHT,ALU2 +S 15200,7900,16800,7900,200,*,RIGHT,ALU2 +S 5900,10700,7100,10700,200,*,LEFT,ALU2 +S 15100,10700,15700,10700,200,*,RIGHT,ALU2 +S 15700,11200,18000,11200,200,*,RIGHT,ALU2 +S 3000,11200,6500,11200,200,*,RIGHT,ALU2 +I 0,5000,sram_w2r2nffct,ctr0,SYM_Y +I 2500,10000,sram_w2dec4,dec01,NOSYM +I 0,10000,sram_w2inv,inv01,NOSYM +V 13500,11700,CONT_VIA,* +V 8700,11700,CONT_VIA,* +V 16800,10700,CONT_VIA,* +V 17300,10700,CONT_VIA2,* +V 17300,9400,CONT_VIA2,* +V 19800,14900,CONT_VIA,* +V 20400,14900,CONT_VIA,* +V 19800,14900,CONT_VIA2,* +V 20400,14900,CONT_VIA2,* +V 17800,13200,CONT_VIA,* +V 8200,10700,CONT_VIA2,* +V 8200,10700,CONT_VIA,* +V 4900,12200,CONT_VIA,* +V 17300,12200,CONT_VIA,* +V 13000,12700,CONT_VIA,* +V 9200,12700,CONT_VIA,* +V 4400,13200,CONT_VIA,* +V 20600,14200,CONT_VIA,* +V 11000,7900,CONT_VIA,* +V 10000,7900,CONT_VIA,* +V 11000,7900,CONT_VIA2,* +V 10000,7900,CONT_VIA2,* +V 11000,6400,CONT_VIA2,* +V 10000,6900,CONT_VIA2,* +V 10800,13700,CONT_VIA,* +V 10200,13700,CONT_VIA,* +V 2900,14200,CONT_VIA,* +V 18000,8400,CONT_VIA2,* +V 18000,8400,CONT_VIA,* +V 15700,8400,CONT_VIA2,* +V 15700,8400,CONT_VIA,* +V 3000,8400,CONT_VIA2,* +V 3000,8400,CONT_VIA,* +V 5300,8400,CONT_VIA,* +V 5900,8400,CONT_VIA2,* +V 18700,8400,CONT_VIA2,* +V 14600,8400,CONT_VIA2,* +V 2300,8400,CONT_VIA2,* +V 9000,8400,CONT_VIA2,* +V 9000,8400,CONT_VIA,* +V 9500,8400,CONT_VIA2,* +V 11500,8400,CONT_VIA2,* +V 12000,8400,CONT_VIA2,* +V 12000,8400,CONT_VIA,* +V 13500,8400,CONT_VIA2,* +V 13000,8400,CONT_VIA2,* +V 13000,8400,CONT_VIA,* +V 13500,8400,CONT_VIA,* +V 8000,8400,CONT_VIA2,* +V 8000,8400,CONT_VIA,* +V 19200,8400,CONT_VIA,* +V 6900,8400,CONT_VIA2,* +V 6900,8400,CONT_VIA,* +V 7500,8400,CONT_VIA2,* +V 7500,8400,CONT_VIA,* +V 2300,8400,CONT_VIA,* +V 9500,8400,CONT_VIA,* +V 1800,8400,CONT_VIA2,* +V 1800,8400,CONT_VIA,* +V 19200,8400,CONT_VIA2,* +V 18700,8400,CONT_VIA,* +V 11500,8400,CONT_VIA,* +V 14100,8400,CONT_VIA2,* +V 14100,8400,CONT_VIA,* +V 14600,8400,CONT_VIA,* +V 19200,7400,CONT_VIA,* +V 1800,7400,CONT_VIA,* +V 4200,10000,CONT_VIA2,* +V 4200,10000,CONT_VIA,* +V 4800,10000,CONT_VIA2,* +V 4200,10000,CONT_VIA,* +V 4800,10000,CONT_VIA,* +V 5800,7900,CONT_VIA2,* +V 4200,7900,CONT_VIA,* +V 15200,7900,CONT_VIA2,* +V 16800,7900,CONT_VIA,* +V 6400,8400,CONT_VIA2,* +V 3700,7900,CONT_VIA2,* +V 3700,7900,CONT_VIA,* +V 17300,7900,CONT_VIA2,* +V 17300,7900,CONT_VIA,* +V 6400,8400,CONT_VIA,* +V 5900,10700,CONT_VIA2,* +V 8200,10700,CONT_VIA,* +V 14000,8900,CONT_VIA2,* +V 14000,10700,CONT_VIA2,* +V 14000,10700,CONT_VIA,* +V 15700,10700,CONT_VIA2,* +V 15100,10700,CONT_VIA,* +V 18000,11200,CONT_VIA2,* +V 15700,11200,CONT_VIA,* +V 8200,8900,CONT_VIA2,* +V 7100,10700,CONT_VIA,* +V 5400,10700,CONT_VIA,* +V 5400,10700,CONT_VIA2,* +V 5400,9400,CONT_VIA2,* +V 4200,10000,CONT_VIA2,* +V 4200,10000,CONT_VIA,* +V 4800,10000,CONT_VIA2,* +V 4200,10000,CONT_VIA,* +V 4800,10000,CONT_VIA,* +V 3000,11200,CONT_VIA2,* +V 6500,11200,CONT_VIA,* +V 4800,10000,CONT_VIA2,* +V 4200,10000,CONT_VIA2,* +V 4800,10000,CONT_VIA,* +V 4200,10000,CONT_VIA,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_dec.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_dec.vbe new file mode 100644 index 000000000..4263c2ecb --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_dec.vbe @@ -0,0 +1,79 @@ +ENTITY sram_w2r2_2x1_dec IS +PORT ( + at : in bit_vector(0 TO 2) ; + wt : in BIT; + az : in bit_vector(0 TO 2) ; + wz : in BIT; + ax : in bit_vector(0 TO 1) ; + ay : in bit_vector(0 TO 1) ; + + at0 : inout BIT; + at1 : inout BIT; + az0 : inout BIT; + az1 : inout BIT; + + rx0 : inout BIT; + rx1 : out BIT; + ry0 : inout BIT; + ry1 : out BIT; + + nwt0 : inout BIT; + nwt1 : inout BIT; + nwz0 : inout BIT; + nwz1 : inout BIT; + nwd0 : inout BIT; + nwd1 : inout BIT; + + wt0 : out BIT; + wt1 : out BIT; + wd0 : out BIT; + wd1 : out BIT; + wz0 : out BIT; + wz1 : out BIT; + + ck : in BIT; + ck0 : out BIT; + ck1 : out BIT; + nck0 : inout BIT; + nck1 : inout BIT; + + vdd : in BIT; + vss : in BIT +); +END sram_w2r2_2x1_dec; + +ARCHITECTURE behaviour_data_flow OF sram_w2r2_2x1_dec IS + +BEGIN + + wt0 <= at0; + wt1 <= at1; + nwt0 <= NOT(at0); + nwt1 <= NOT(at1); + + nwz0 <= (NOT(az0) OR NOT(nwt0)); + nwz1 <= (NOT(az1) OR NOT(nwt1)); + wz0 <= NOT(nwz0); + wz1 <= NOT(nwz1); + + nwd0 <= (NOT(nwt0) OR NOT(nwz0)); + nwd1 <= (NOT(nwt1) OR NOT(nwz1)); + wd0 <= NOT(nwd0); + wd1 <= NOT(nwd1); + + rx0 <= NOT(ax(0)); + rx1 <= NOT(rx0); + ry0 <= NOT(ay(0)); + ry1 <= NOT(ry0); + + nck1 <= NOT(ck); + nck0 <= NOT(ck); + ck1 <= ck; + ck0 <= ck; + + az1 <= (az(2) AND az(1) AND NOT(az(0)) AND wz); + az0 <= (az(2) AND az(1) AND az(0) AND wz); + at1 <= (at(2) AND at(1) AND NOT(at(0)) AND wt); + at0 <= (at(2) AND at(1) AND at(0) AND wt); + +END; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_mx.ap b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_mx.ap new file mode 100644 index 000000000..4b9e87bab --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_mx.ap @@ -0,0 +1,64 @@ +V ALLIANCE : 6 +H sram_w2r2_2x1_mx,P,18/ 8/2024,100 +A 0,0,5000,15000 +S 0,4900,5000,4900,200,ax 2,RIGHT,CALU2 +S 3900,8200,3900,8400,200,iax,DOWN,CALU1 +S 1300,8200,1300,8400,200,iay,UP,CALU1 +S 0,4400,5000,4400,200,ay 2,RIGHT,CALU2 +S 0,11700,5000,11700,200,at 2,LEFT,CALU2 +S 0,12200,5000,12200,200,az 2,LEFT,CALU2 +S 600,0,600,7900,200,ry1,UP,CALU3 +S 1800,0,1800,7900,200,ry0,DOWN,CALU3 +S 3200,0,3200,7900,200,rx1,UP,CALU3 +S 4400,0,4400,7900,200,rx0,UP,CALU3 +S 0,5400,5000,5400,200,ay 1,RIGHT,CALU2 +S 0,3400,3000,3400,200,ix0,LEFT,CALU2 +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 0,10000,5000,10000,400,vss,RIGHT,CALU1 +S 0,15000,5000,15000,400,vdd,RIGHT,CALU1 +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +S 0,13200,5000,13200,200,az 1,LEFT,CALU2 +S 0,12700,5000,12700,200,at 1,LEFT,CALU2 +S 0,9400,5000,9400,200,wz,RIGHT,CALU2 +S 0,8900,5000,8900,200,wt,RIGHT,CALU2 +S 0,7400,5000,7400,200,ck,RIGHT,CALU2 +S 0,1400,300,1400,200,iy0,LEFT,CALU2 +S 0,5900,5000,5900,200,ax 1,RIGHT,CALU2 +S 0,6900,5000,6900,200,ax 0,RIGHT,CALU2 +S 0,6400,5000,6400,200,ay 0,RIGHT,CALU2 +S 0,2400,5000,2400,200,iz,RIGHT,CALU2 +S 0,1900,5000,1900,200,it,RIGHT,CALU2 +S 0,14200,5000,14200,200,az 0,LEFT,CALU2 +S 0,13700,5000,13700,200,at 0,LEFT,CALU2 +S 2300,1400,5000,1400,200,iy1,LEFT,CALU2 +S 4700,3400,5000,3400,200,ix1,LEFT,CALU2 +S 600,2900,1300,2900,200,*,LEFT,ALU2 +S 3700,2900,4400,2900,200,*,RIGHT,ALU2 +S 1400,900,5000,900,200,nqy,LEFT,CALU2 +S 4200,3900,5000,3900,200,nqx,LEFT,CALU2 +I 0,0,sram_noa2a22,noa,NOSYM +I 0,10000,sram_mxct,mxct,NOSYM +I 0,5000,sram_noa2a22ct,noact,SYM_Y +V 3000,3400,CONT_VIA,* +V 4700,3400,CONT_VIA,* +V 3200,7900,CONT_VIA,* +V 1800,7900,CONT_VIA,* +V 600,7900,CONT_VIA,* +V 1400,900,CONT_VIA,* +V 4200,3900,CONT_VIA,* +V 2300,1400,CONT_VIA,* +V 3200,2900,CONT_VIA,* +V 1300,2900,CONT_VIA,* +V 1800,2900,CONT_VIA,* +V 300,1400,CONT_VIA,* +V 4400,7900,CONT_VIA,* +V 3700,2900,CONT_VIA,* +V 1800,2900,CONT_VIA2,* +V 4400,2900,CONT_VIA2,* +V 4400,7900,CONT_VIA2,* +V 1800,7900,CONT_VIA2,* +V 3200,7900,CONT_VIA2,* +V 600,2900,CONT_VIA2,* +V 600,7900,CONT_VIA2,* +V 3200,2900,CONT_VIA2,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_mx.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_mx.vbe new file mode 100644 index 000000000..875895017 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x1_mx.vbe @@ -0,0 +1,38 @@ +ENTITY sram_w2r2_2x1_mx IS +PORT ( + iax : in BIT; + iay : in BIT; + at : in bit_vector(0 TO 2) ; + az : in bit_vector(0 TO 2) ; + ax : in bit_vector(0 TO 2) ; + ay : in bit_vector(0 TO 2) ; + rx0 : inout BIT; + rx1 : inout BIT; + ry0 : inout BIT; + ry1 : inout BIT; + it : in BIT; + ix0 : in BIT; + ix1 : in BIT; + iy0 : in BIT; + iy1 : in BIT; + iz : in BIT; + nqx : out BIT; + nqy : out BIT; + wt : in BIT; + wz : in BIT; + ck : in BIT; + vdd : in BIT; + vss : in BIT +); +END sram_w2r2_2x1_mx; + +ARCHITECTURE behaviour_data_flow OF sram_w2r2_2x1_mx IS +BEGIN + ry1 <= NOT(ry0); + ry0 <= NOT(iay); + rx1 <= NOT(rx0); + rx0 <= NOT(iax); + + nqy <= NOT(iy1) when iay else NOT(iy0); + nqx <= NOT(ix1) when iax else NOT(ix0); +END; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x2.ap b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x2.ap new file mode 100644 index 000000000..eae5a4d8b --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x2.ap @@ -0,0 +1,309 @@ +V ALLIANCE : 6 +H sram_w2r2_2x2,P,19/ 8/2024,100 +A 0,-5000,21000,15000 +S 0,-5000,21000,-5000,400,vdd,RIGHT,CALU1 +S 13500,-5000,13500,0,200,nwd1,UP,ALU3 +S 3700,-2900,5300,-2900,200,*,LEFT,ALU2 +S 0,-3400,21000,-3400,200,nqx 1,LEFT,CALU2 +S 0,-2400,21000,-2400,200,iz 1,LEFT,CALU2 +S 0,-1900,21000,-1900,200,it 1,LEFT,CALU2 +S 0,-1400,21000,-1400,200,nqy 1,LEFT,CALU2 +S 15700,-2900,17300,-2900,200,*,RIGHT,ALU2 +S 5800,-5000,5800,0,200,wz0,UP,ALU3 +S 3700,-5000,3700,0,200,nwz0,UP,ALU3 +S 2300,-5000,2300,0,200,nck0,UP,ALU3 +S 1800,-5000,1800,0,200,ck0,UP,ALU3 +S 12000,-5000,12000,0,200,ry0,UP,ALU3 +S 11500,-5000,11500,0,200,ry1,UP,ALU3 +S 15200,-5000,15200,0,200,wz1,UP,ALU3 +S 14600,-5000,14600,0,200,wt1,UP,ALU3 +S 14100,-5000,14100,0,200,nwt1,UP,ALU3 +S 7500,-5000,7500,0,200,nwd0,UP,ALU3 +S 6900,-5000,6900,0,200,nwt0,UP,ALU3 +S 6400,-5000,6400,0,200,wt0,UP,ALU3 +S 9500,-5000,9500,0,200,rx0,UP,ALU3 +S 9000,-5000,9000,0,200,rx1,DOWN,ALU3 +S 8000,-5000,8000,0,200,wd0,UP,ALU3 +S 13000,-5000,13000,0,200,wd1,UP,ALU3 +S 19200,-5000,19200,0,200,ck1,UP,ALU3 +S 18700,-5000,18700,0,200,nck1,UP,ALU3 +S 17300,-5000,17300,0,200,nwz1,UP,ALU3 +S 0,4400,21000,4400,200,ay 2,RIGHT,CALU2 +S 0,4900,21000,4900,200,ax 2,RIGHT,CALU2 +S 2100,10600,2100,14400,200,invnq1,DOWN,CALU1 +S 900,10600,900,14400,200,invnq0,DOWN,CALU1 +S 1600,11700,1600,13200,200,invi1,DOWN,CALU1 +S 400,11700,400,13200,200,invi0,DOWN,CALU1 +S 2100,13200,21000,13200,200,az 1,LEFT,CALU2 +S 2100,12700,21000,12700,200,at 1,LEFT,CALU2 +S 900,11700,21000,11700,200,at 2,RIGHT,CALU2 +S 900,12200,21000,12200,200,az 2,RIGHT,CALU2 +S 16800,9400,16800,10700,200,wz,UP,CALU3 +S 14000,8900,14000,10700,200,wt,UP,CALU3 +S 8200,8900,8200,10700,200,wt,UP,CALU3 +S 5400,9400,5400,10700,200,wz,UP,CALU3 +S 11000,6400,11000,15000,200,ay 0,UP,CALU3 +S 10000,6900,10000,15000,200,ax 0,UP,CALU3 +S 0,0,21000,0,400,vss,RIGHT,CALU1 +S 0,10000,21000,10000,400,vss,RIGHT,CALU1 +S 0,13700,21000,13700,200,at 0,LEFT,CALU2 +S 0,1400,21000,1400,200,nqy 0,RIGHT,CALU2 +S 0,14200,21000,14200,200,az 0,LEFT,CALU2 +S 0,15000,21000,15000,400,vdd,RIGHT,CALU1 +S 0,1900,21000,1900,200,it 0,RIGHT,CALU2 +S 0,2400,21000,2400,200,iz 0,RIGHT,CALU2 +S 0,3400,21000,3400,200,nqx 0,RIGHT,CALU2 +S 0,5000,21000,5000,400,vdd,RIGHT,CALU1 +S 0,5400,21000,5400,200,ay 1,RIGHT,CALU2 +S 0,5900,21000,5900,200,ax 1,RIGHT,CALU2 +S 0,6400,21000,6400,200,ay 0,RIGHT,CALU2 +S 0,6900,21000,6900,200,ax 0,RIGHT,CALU2 +S 0,7400,21000,7400,200,ck,RIGHT,CALU2 +S 0,8900,21000,8900,200,wt,RIGHT,CALU2 +S 0,9400,21000,9400,200,wz,RIGHT,CALU2 +S 10000,7100,10000,8400,200,ax,DOWN,ALU1 +S 11000,7100,11000,8400,200,ay,DOWN,ALU1 +S 11500,0,11500,5000,200,ry1,UP,CALU3 +S 11500,5000,11500,8400,200,ry1,UP,CALU3 +S 12000,0,12000,5000,200,ry0,UP,CALU3 +S 12000,5000,12000,8400,200,ry0,UP,CALU3 +S 13000,0,13000,5000,200,wd1,UP,CALU3 +S 13000,5000,13000,8400,200,wd1,UP,CALU3 +S 13500,0,13500,5000,200,nwd1,UP,CALU3 +S 13500,5000,13500,8400,200,nwd1,UP,CALU3 +S 14100,0,14100,5000,200,nwt1,UP,CALU3 +S 14100,5000,14100,8400,200,nwt1,UP,CALU3 +S 14600,0,14600,5000,200,wt1,UP,CALU3 +S 14600,5000,14600,8400,200,wt1,UP,CALU3 +S 15100,10700,15700,10700,200,*,RIGHT,ALU2 +S 15200,0,15200,5000,200,wz1,UP,CALU3 +S 15200,5000,15200,7900,200,wz1,UP,CALU3 +S 15200,7900,16800,7900,200,*,RIGHT,ALU2 +S 15700,11200,18000,11200,200,*,RIGHT,ALU2 +S 15700,2900,17300,2900,200,*,LEFT,ALU2 +S 15700,7100,15700,8400,200,at1,UP,ALU1 +S 15700,8400,15700,15000,200,at1,UP,CALU3 +S 17300,0,17300,5000,200,nwz1,UP,CALU3 +S 17300,5000,17300,7900,200,nwz1,UP,CALU3 +S 1800,0,1800,5000,200,ck0,UP,CALU3 +S 18000,6600,18000,8400,200,az1,UP,ALU1 +S 18000,8400,18000,15000,200,az1,UP,CALU3 +S 1800,5000,1800,8400,200,ck0,UP,CALU3 +S 18700,0,18700,5000,200,nck1,UP,CALU3 +S 18700,5000,18700,8400,200,nck1,UP,CALU3 +S 19200,0,19200,5000,200,ck1,UP,CALU3 +S 19200,5000,19200,8400,200,ck1,UP,CALU3 +S 2300,0,2300,5000,200,nck0,UP,CALU3 +S 2300,5000,2300,8400,200,nck0,UP,CALU3 +S 3000,11200,6500,11200,200,*,RIGHT,ALU2 +S 3000,6600,3000,8400,200,az0,UP,ALU1 +S 3000,8400,3000,15000,200,az0,UP,CALU3 +S 3700,0,3700,5000,200,nwz0,UP,CALU3 +S 3700,2900,5300,2900,200,*,RIGHT,ALU2 +S 3700,5000,3700,7900,200,nwz0,UP,CALU3 +S 4200,7900,5800,7900,200,*,RIGHT,ALU2 +S 5300,6600,5300,8400,200,at0,UP,ALU1 +S 5300,8400,5900,8400,200,*,RIGHT,ALU2 +S 5800,0,5800,5000,200,wz0,UP,CALU3 +S 5800,5000,5800,7900,200,wz0,UP,CALU3 +S 5900,10700,7100,10700,200,*,LEFT,ALU2 +S 5900,8400,5900,15000,200,at0,UP,CALU3 +S 6400,0,6400,5000,200,wt0,UP,CALU3 +S 6400,5000,6400,8400,200,wt0,UP,CALU3 +S 6900,0,6900,5000,200,nwt0,UP,CALU3 +S 6900,5000,6900,8400,200,nwt0,UP,CALU3 +S 7500,0,7500,5000,200,nwd0,UP,CALU3 +S 7500,5000,7500,8400,200,nwd0,UP,CALU3 +S 8000,0,8000,5000,200,wd0,UP,CALU3 +S 8000,5000,8000,8400,200,wd0,UP,CALU3 +S 9000,0,9000,5000,200,rx1,DOWN,CALU3 +S 9000,5000,9000,8400,200,rx1,DOWN,CALU3 +S 9500,0,9500,5000,200,rx0,UP,CALU3 +S 9500,5000,9500,8400,200,rx0,UP,CALU3 +I 0,-5000,sram_w2r2nff,b01ff,SYM_Y +I 0,0,sram_w2r2nff,b00ff,NOSYM +I 0,5000,sram_w2r2nffct,ctr,SYM_Y +I 0,10000,sram_w2inv,inv01,NOSYM +I 2500,10000,sram_w2dec4,dec01,NOSYM +V 11500,-2900,CONT_VIA,* +V 12000,-2900,CONT_VIA,* +V 6400,-2900,CONT_VIA,* +V 1800,-2900,CONT_VIA,* +V 2300,-2900,CONT_VIA,* +V 5300,-2400,CONT_VIA,* +V 5300,-2900,CONT_VIA,* +V 5800,-2900,CONT_VIA,* +V 13000,-2900,CONT_VIA,* +V 13500,-2900,CONT_VIA,* +V 14100,-1900,CONT_VIA,* +V 14100,-2900,CONT_VIA,* +V 14600,-2900,CONT_VIA,* +V 15200,-2900,CONT_VIA,* +V 10000,-3400,CONT_VIA,* +V 11000,-1400,CONT_VIA,* +V 7500,-2900,CONT_VIA,* +V 8000,-2900,CONT_VIA,* +V 9000,-2900,CONT_VIA,* +V 9500,-2900,CONT_VIA,* +V 6900,-1900,CONT_VIA,* +V 6900,-2900,CONT_VIA,* +V 18700,-2900,CONT_VIA,* +V 19200,-2900,CONT_VIA,* +V 15700,-2400,CONT_VIA,* +V 15700,-2900,CONT_VIA,* +V 2300,-2900,CONT_VIA2,* +V 3700,-2900,CONT_VIA2,* +V 5800,-2900,CONT_VIA2,* +V 12000,-2900,CONT_VIA2,* +V 6400,-2900,CONT_VIA2,* +V 1800,-2900,CONT_VIA2,* +V 6900,-2900,CONT_VIA2,* +V 8000,-2900,CONT_VIA2,* +V 9000,-2900,CONT_VIA2,* +V 9500,-2900,CONT_VIA2,* +V 13500,-2900,CONT_VIA2,* +V 14100,-2900,CONT_VIA2,* +V 14600,-2900,CONT_VIA2,* +V 15200,-2900,CONT_VIA2,* +V 11500,-2900,CONT_VIA2,* +V 13000,-2900,CONT_VIA2,* +V 7500,-2900,CONT_VIA2,* +V 17300,-2900,CONT_VIA2,* +V 18700,-2900,CONT_VIA2,* +V 19200,-2900,CONT_VIA2,* +V 13500,11700,CONT_VIA,* +V 8700,11700,CONT_VIA,* +V 10000,3400,CONT_VIA,* +V 10000,6900,CONT_VIA2,* +V 10000,7900,CONT_VIA,* +V 10000,7900,CONT_VIA2,* +V 10200,13700,CONT_VIA,* +V 10800,13700,CONT_VIA,* +V 11000,1400,CONT_VIA,* +V 11000,6400,CONT_VIA2,* +V 11000,7900,CONT_VIA,* +V 11000,7900,CONT_VIA2,* +V 11500,2900,CONT_VIA,* +V 11500,2900,CONT_VIA2,* +V 11500,8400,CONT_VIA,* +V 11500,8400,CONT_VIA2,* +V 12000,2900,CONT_VIA,* +V 12000,2900,CONT_VIA2,* +V 12000,8400,CONT_VIA,* +V 12000,8400,CONT_VIA2,* +V 13000,12700,CONT_VIA,* +V 13000,2900,CONT_VIA,* +V 13000,2900,CONT_VIA2,* +V 13000,8400,CONT_VIA,* +V 13000,8400,CONT_VIA2,* +V 13500,2900,CONT_VIA,* +V 13500,2900,CONT_VIA2,* +V 13500,8400,CONT_VIA,* +V 13500,8400,CONT_VIA2,* +V 14000,10700,CONT_VIA,* +V 14000,10700,CONT_VIA2,* +V 14000,8900,CONT_VIA2,* +V 14100,1900,CONT_VIA,* +V 14100,2900,CONT_VIA,* +V 14100,2900,CONT_VIA2,* +V 14100,8400,CONT_VIA,* +V 14100,8400,CONT_VIA2,* +V 14600,2900,CONT_VIA,* +V 14600,2900,CONT_VIA2,* +V 14600,8400,CONT_VIA,* +V 14600,8400,CONT_VIA2,* +V 15100,10700,CONT_VIA,* +V 15200,2900,CONT_VIA,* +V 15200,2900,CONT_VIA2,* +V 15200,7900,CONT_VIA2,* +V 15700,10700,CONT_VIA2,* +V 15700,11200,CONT_VIA,* +V 15700,2400,CONT_VIA,* +V 15700,2900,CONT_VIA,* +V 15700,8400,CONT_VIA,* +V 15700,8400,CONT_VIA2,* +V 16800,10700,CONT_VIA,* +V 16800,10700,CONT_VIA2,* +V 16800,7900,CONT_VIA,* +V 16800,9400,CONT_VIA2,* +V 17300,12200,CONT_VIA,* +V 17300,2900,CONT_VIA2,* +V 17300,7900,CONT_VIA,* +V 17300,7900,CONT_VIA2,* +V 17800,13200,CONT_VIA,* +V 18000,11200,CONT_VIA2,* +V 18000,8400,CONT_VIA,* +V 18000,8400,CONT_VIA2,* +V 1800,2900,CONT_VIA,* +V 1800,2900,CONT_VIA2,* +V 1800,7400,CONT_VIA,* +V 1800,8400,CONT_VIA,* +V 1800,8400,CONT_VIA2,* +V 18700,2900,CONT_VIA,* +V 18700,2900,CONT_VIA2,* +V 18700,8400,CONT_VIA,* +V 18700,8400,CONT_VIA2,* +V 19200,2900,CONT_VIA,* +V 19200,2900,CONT_VIA2,* +V 19200,7400,CONT_VIA,* +V 19200,8400,CONT_VIA,* +V 19200,8400,CONT_VIA2,* +V 20600,14200,CONT_VIA,* +V 2300,2900,CONT_VIA,* +V 2300,2900,CONT_VIA2,* +V 2300,8400,CONT_VIA,* +V 2300,8400,CONT_VIA2,* +V 2900,14200,CONT_VIA,* +V 3000,11200,CONT_VIA2,* +V 3000,8400,CONT_VIA,* +V 3000,8400,CONT_VIA2,* +V 3700,2900,CONT_VIA2,* +V 3700,7900,CONT_VIA,* +V 3700,7900,CONT_VIA2,* +V 4200,7900,CONT_VIA,* +V 4400,13200,CONT_VIA,* +V 4900,12200,CONT_VIA,* +V 5300,2400,CONT_VIA,* +V 5300,2900,CONT_VIA,* +V 5300,8400,CONT_VIA,* +V 5400,10700,CONT_VIA,* +V 5400,10700,CONT_VIA2,* +V 5400,9400,CONT_VIA2,* +V 5800,2900,CONT_VIA,* +V 5800,2900,CONT_VIA2,* +V 5800,7900,CONT_VIA2,* +V 5900,10700,CONT_VIA2,* +V 5900,8400,CONT_VIA2,* +V 6400,2900,CONT_VIA,* +V 6400,2900,CONT_VIA2,* +V 6400,8400,CONT_VIA,* +V 6400,8400,CONT_VIA2,* +V 6500,11200,CONT_VIA,* +V 6900,1900,CONT_VIA,* +V 6900,2900,CONT_VIA,* +V 6900,2900,CONT_VIA2,* +V 6900,8400,CONT_VIA,* +V 6900,8400,CONT_VIA2,* +V 7100,10700,CONT_VIA,* +V 7500,2900,CONT_VIA,* +V 7500,2900,CONT_VIA2,* +V 7500,8400,CONT_VIA,* +V 7500,8400,CONT_VIA2,* +V 8000,2900,CONT_VIA,* +V 8000,2900,CONT_VIA2,* +V 8000,8400,CONT_VIA,* +V 8000,8400,CONT_VIA2,* +V 8200,10700,CONT_VIA,* +V 8200,10700,CONT_VIA,* +V 8200,10700,CONT_VIA2,* +V 8200,8900,CONT_VIA2,* +V 9000,2900,CONT_VIA,* +V 9000,2900,CONT_VIA2,* +V 9000,8400,CONT_VIA,* +V 9000,8400,CONT_VIA2,* +V 9200,12700,CONT_VIA,* +V 9500,2900,CONT_VIA,* +V 9500,2900,CONT_VIA2,* +V 9500,8400,CONT_VIA,* +V 9500,8400,CONT_VIA2,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x2.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x2.vbe new file mode 100644 index 000000000..994b2bb41 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_2x2.vbe @@ -0,0 +1,128 @@ +ENTITY sram_w2r2_2x2 IS +PORT ( + + invi0 : in BIT; + invi1 : in BIT; + invnq0 : out BIT; + invnq1 : out BIT; + + at : in bit_vector(2 downto 0) ; + az : in bit_vector(2 downto 0) ; + ax : in bit_vector(2 downto 0) ; + ay : in bit_vector(2 downto 0) ; + wt : in BIT; + wz : in BIT; + + it : in bit_vector(1 downto 0); + iz : in bit_vector(1 downto 0); + + nqx : out bit_vector(1 downto 0); + nqy : out bit_vector(1 downto 0); + + ck : in BIT; + + at0 : inout BIT; + at1 : inout BIT; + az0 : inout BIT; + az1 : inout BIT; + + wt0 : inout BIT; + wt1 : inout BIT; + nwt0 : inout BIT; + nwt1 : inout BIT; + + wz0 : inout BIT; + wz1 : inout BIT; + nwz0 : inout BIT; + nwz1 : inout BIT; + + wd0 : inout BIT; + wd1 : inout BIT; + nwd0 : inout BIT; + nwd1 : inout BIT; + + rx0 : inout BIT; + rx1 : inout BIT; + + ry0 : inout BIT; + ry1 : inout BIT; + + ck0 : inout BIT; + ck1 : inout BIT; + nck0 : inout BIT; + nck1 : inout BIT; + + vdd : in BIT; + vss : in BIT +); +END sram_w2r2_2x2; + +ARCHITECTURE behaviour_data_flow OF sram_w2r2_2x2 IS + SIGNAL b00ffm1 : REG_BIT REGISTER; + SIGNAL b00ffs1 : REG_BIT REGISTER; + SIGNAL b00ffm0 : REG_BIT REGISTER; + SIGNAL b00ffs0 : REG_BIT REGISTER; + + SIGNAL b01ffm1 : REG_BIT REGISTER; + SIGNAL b01ffs1 : REG_BIT REGISTER; + SIGNAL b01ffm0 : REG_BIT REGISTER; + SIGNAL b01ffs0 : REG_BIT REGISTER; + +BEGIN + + invnq1 <= NOT(invi1); + invnq0 <= NOT(invi0); + + at0 <= (at(2) AND at(1) AND at(0) AND wt); -- at = 11 + at1 <= (at(2) AND at(1) AND NOT(at(0)) AND wt); -- at = 10 + az0 <= (az(2) AND az(1) AND az(0) AND wz); -- az = 11 + az1 <= (az(2) AND az(1) AND NOT(az(0)) AND wz); -- az = 10 + + Masters : BLOCK (NOT(ck)) + BEGIN + b00ffm0 <= GUARDED NOT(it(0)) when at0 else NOT(iz(0)) when az0 else NOT(b00ffs0); + b00ffm1 <= GUARDED NOT(it(0)) when at1 else NOT(iz(0)) when az1 else NOT(b00ffs1); + + b01ffm0 <= GUARDED NOT(it(1)) when at0 else NOT(iz(1)) when az0 else NOT(b01ffs0); + b01ffm1 <= GUARDED NOT(it(1)) when at1 else NOT(iz(1)) when az1 else NOT(b01ffs1); + END BLOCK Masters; + + Slaves : BLOCK (ck) + BEGIN + b00ffs0 <= GUARDED NOT(b00ffm0); + b00ffs1 <= GUARDED NOT(b00ffm1); + + b01ffs0 <= GUARDED NOT(b01ffm0); + b01ffs1 <= GUARDED NOT(b01ffm1); + END BLOCK Slaves; + + nqy(0) <= NOT(b00ffs1) when ay(0) else NOT(b00ffs0); + nqx(0) <= NOT(b00ffs1) when ax(0) else NOT(b00ffs0); + nqy(1) <= NOT(b01ffs1) when ay(0) else NOT(b01ffs0); + nqx(1) <= NOT(b01ffs1) when ax(0) else NOT(b01ffs0); + + wt0 <= at0; + wt1 <= at1; + wz0 <= (az0 AND NOT(at0)); + wz1 <= (az1 AND NOT(at1)); + wd1 <= (NOT(az1) AND NOT(at1)); + wd0 <= (NOT(az0) AND NOT(at0)); + + nwt0 <= NOT(wt0); + nwt1 <= NOT(wt1); + nwz0 <= NOT(wz0); + nwz1 <= NOT(wz1); + nwd1 <= NOT(wd1); + nwd0 <= NOT(wd0); + + rx0 <= NOT(ax(0)); + rx1 <= NOT(rx0); + ry0 <= NOT(ay(0)); + ry1 <= NOT(ry0); + + ck1 <= ck; + ck0 <= ck; + nck1 <= NOT(ck); + nck0 <= NOT(ck); + +END; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_4x1.ap b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_4x1.ap new file mode 100644 index 000000000..1b1a72ed6 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_4x1.ap @@ -0,0 +1,57 @@ +V ALLIANCE : 6 +H sram_w2r2_4x1,P,19/ 8/2024,100 +A 0,0,47000,15000 +S 0,11700,0,11700,200,at 2,LEFT,CALU2 +S 0,12200,0,12200,200,az 2,LEFT,CALU2 +S 47000,4900,47000,4900,200,ax 2,LEFT,CALU2 +S 47000,4400,47000,4400,200,ay 2,LEFT,CALU2 +S 24900,5900,24900,8400,200,*,UP,ALU3 +S 22300,5400,22300,8400,200,*,UP,ALU3 +S 21000,4400,26000,4400,200,*,RIGHT,ALU2 +S 21000,4900,26000,4900,200,*,RIGHT,ALU2 +S 26900,13200,28100,13200,200,*,RIGHT,ALU2 +S 26000,12700,27600,12700,200,*,RIGHT,ALU2 +S 26000,13200,26400,13200,200,*,RIGHT,ALU2 +S 26000,11700,26900,11700,200,*,RIGHT,ALU2 +S 26000,12200,26900,12200,200,*,RIGHT,ALU2 +S 0,11700,900,11700,200,*,RIGHT,ALU2 +S 0,12200,900,12200,200,*,RIGHT,ALU2 +S 0,12700,2100,12700,200,*,RIGHT,ALU2 +S 0,13200,2100,13200,200,*,RIGHT,ALU2 +S 26000,900,46900,900,200,*,RIGHT,ALU2 +S 26000,3900,47000,3900,200,*,RIGHT,ALU2 +S 47000,900,47000,900,200,nqy,LEFT,CALU2 +S 47000,3900,47000,3900,200,nqx,LEFT,CALU2 +S 0,0,0,0,200,vss,LEFT,CALU1 +S 0,5000,0,5000,200,vdd,LEFT,CALU1 +S 0,10000,0,10000,200,vss,LEFT,CALU1 +S 0,15000,0,15000,200,vdd,LEFT,CALU1 +S 0,14200,0,14200,200,az 0,LEFT,CALU2 +S 0,7400,0,7400,200,ck,LEFT,CALU2 +S 0,8900,0,8900,200,wt,LEFT,CALU2 +S 0,9400,0,9400,200,wz,LEFT,CALU2 +S 0,12700,0,12700,200,at 1,LEFT,CALU2 +S 0,13700,0,13700,200,at 0,LEFT,CALU2 +S 0,13200,0,13200,200,az 1,LEFT,CALU2 +S 0,1900,0,1900,200,it,LEFT,CALU2 +S 0,2400,0,2400,200,iz,LEFT,CALU2 +S 0,5400,0,5400,200,ay 1,LEFT,CALU2 +S 0,5900,0,5900,200,ax 1,LEFT,CALU2 +S 0,6400,0,6400,200,ay 0,LEFT,CALU2 +S 0,6900,0,6900,200,ax 0,LEFT,CALU2 +I 26000,0,sram_w2r2_2x1,ff23,NOSYM +I 21000,0,sram_w2r2_2x1_mx,mx12,NOSYM +I 0,0,sram_w2r2_2x1,ff01,NOSYM +V 22300,8400,CONT_VIA2,* +V 22300,5400,CONT_VIA2,* +V 24900,5900,CONT_VIA2,* +V 22300,5400,CONT_VIA2,* +V 24900,8400,CONT_VIA2,* +V 22300,8400,CONT_VIA2,* +V 24900,8400,CONT_VIA,* +V 22300,8400,CONT_VIA,* +V 28100,12700,CONT_VIA,* +V 27600,12700,CONT_VIA,* +V 26900,13200,CONT_VIA,* +V 26400,13200,CONT_VIA,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_4x1.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_4x1.vbe new file mode 100644 index 000000000..4890a56ab --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_g/sram_w2r2_4x1.vbe @@ -0,0 +1,73 @@ +ENTITY sram_w2r2_4x1 IS +PORT ( + + at : in bit_vector(2 DOWNTO 0) ; + az : in bit_vector(2 DOWNTO 0) ; + ax : in bit_vector(2 DOWNTO 0) ; + ay : in bit_vector(2 DOWNTO 0) ; + wt : in BIT; + wz : in BIT; + + it : in BIT; + iz : in BIT; + + nqx : out BIT; + nqy : out BIT; + + ck : in BIT; + + vdd : in BIT; + vss : in BIT +); +END sram_w2r2_4x1; + +ARCHITECTURE behaviour_data_flow OF sram_w2r2_4x1 IS + + SIGNAL ff01_ffm0 : REG_BIT REGISTER; + SIGNAL ff01_ffm1 : REG_BIT REGISTER; + SIGNAL ff23_ffm0 : REG_BIT REGISTER; + SIGNAL ff23_ffm1 : REG_BIT REGISTER; + + SIGNAL ff01_ffs0 : REG_BIT REGISTER; + SIGNAL ff01_ffs1 : REG_BIT REGISTER; + SIGNAL ff23_ffs0 : REG_BIT REGISTER; + SIGNAL ff23_ffs1 : REG_BIT REGISTER; + +BEGIN + + Masters : BLOCK (NOT(ck)) + BEGIN + + ff01_ffm0 <= GUARDED NOT(it) when (wt AND at = "111") + else NOT(iz) when (wz AND az = "111") + else NOT(ff01_ffs0); + ff01_ffm1 <= GUARDED NOT(it) when (wt AND at = "110") + else NOT(iz) when (wz AND az = "110") + else NOT(ff01_ffs1); + ff23_ffm0 <= GUARDED NOT(it) when (wt AND at = "101") + else NOT(iz) when (wz AND az = "101") + else NOT(ff23_ffs0); + ff23_ffm1 <= GUARDED NOT(it) when (wt AND at = "100") + else NOT(iz) when (wz AND az = "100") + else NOT(ff23_ffs1); + END BLOCK Masters; + + Slaves : BLOCK (ck) + BEGIN + ff01_ffs0 <= GUARDED NOT(ff01_ffm0); + ff01_ffs1 <= GUARDED NOT(ff01_ffm1); + ff23_ffs0 <= GUARDED NOT(ff23_ffm0); + ff23_ffs1 <= GUARDED NOT(ff23_ffm1); + END BLOCK Slaves; + + nqy <= ff01_ffs0 when (ay(1 downto 0) = b"00") + else ff01_ffs1 when (ay(1 downto 0) = b"01") + else ff23_ffs0 when (ay(1 downto 0) = b"10") + else ff23_ffs1; + + nqx <= ff01_ffs0 when (ax(1 downto 0) = b"00") + else ff01_ffs1 when (ax(1 downto 0) = b"01") + else ff23_ffs0 when (ax(1 downto 0) = b"10") + else ff23_ffs1; + +END; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_mxct.ap b/ips/lsxram/coriolis/ips/lsxram/sram_mxct.ap new file mode 100644 index 000000000..5c3e5b898 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_mxct.ap @@ -0,0 +1,33 @@ +V ALLIANCE : 6 +H sram_mxct,P,16/ 8/2024,100 +A 0,0,5000,5000 +S 0,1100,5000,1100,1400,*,RIGHT,PWELL +S 0,0,5000,0,300,*,RIGHT,PTIE +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22.ap b/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22.ap new file mode 100644 index 000000000..113ab085e --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22.ap @@ -0,0 +1,172 @@ +V ALLIANCE : 6 +H sram_noa2a22,P,20/ 8/2024,100 +A 0,0,5000,5000 +R 1400,600,ref_ref,nqyo +R 2000,900,ref_ref,iy1o +R 800,900,ref_ref,iy0o +R 300,1400,ref_ref,iy0 +R 1400,900,ref_ref,nqy +R 4200,4400,ref_ref,nqxo +R 4200,3900,ref_ref,nqx +R 4700,3900,ref_ref,ix1o +R 3000,3900,ref_ref,ix0o +R 4700,3400,ref_ref,ix1 +R 2300,1400,ref_ref,iy1 +R 1300,2900,ref_ref,ry1 +R 1800,2900,ref_ref,ry0 +R 3000,3400,ref_ref,ix0 +R 3700,2900,ref_ref,rx0 +R 3200,2900,ref_ref,rx1 +R 0,5000,ref_ref,vdd0 +R 5000,5000,ref_ref,vdd1 +R 0,0,ref_ref,vss0 +R 5000,0,ref_ref,vss1 +S 2500,3900,2500,5000,200,*,DOWN,ALU1 +S 1400,3400,1400,4400,200,nqy,UP,CALU1 +S 800,1600,800,3400,200,nqy,UP,CALU1 +S 800,3400,1400,3400,200,*,RIGHT,ALU1 +S 3700,2900,3900,2900,200,*,LEFT,POLY +S 4400,2100,4700,2100,200,*,RIGHT,POLY +S 3700,2100,3900,2100,200,*,RIGHT,POLY +S 1100,2100,1300,2100,200,*,RIGHT,POLY +S 300,2100,600,2100,200,*,RIGHT,POLY +S 1100,2900,1300,2900,200,*,RIGHT,POLY +S 300,1100,800,1100,200,*,LEFT,ALU1 +S 300,3900,800,3900,200,*,LEFT,ALU1 +S 800,3900,800,4400,200,iy0,DOWN,CALU1 +S 800,600,800,1100,200,iy0,UP,CALU1 +S 1400,600,1400,1600,200,nqy,UP,CALU1 +S 800,1600,1400,1600,200,*,LEFT,ALU1 +S 2800,1600,2900,1600,200,*,LEFT,POLY2 +S 1100,1100,1100,2100,100,*,DOWN,POLY +S 1700,2900,1700,3200,100,*,UP,POLY +S 1700,1100,1700,2500,100,*,UP,POLY +S 1100,2500,1100,3200,100,*,UP,POLY +S 1100,2500,1700,2500,100,*,LEFT,POLY +S 1100,2100,1300,2100,200,*,RIGHT,POLY2 +S 1700,2900,1800,2900,200,*,RIGHT,POLY2 +S 1100,2900,1300,2900,200,*,LEFT,POLY2 +S 1800,2400,1800,2900,200,*,UP,ALU1 +S 1300,2400,1800,2400,200,*,RIGHT,ALU1 +S 1300,2100,1300,2400,200,*,UP,ALU1 +S 1300,2900,1300,2900,200,ry1,LEFT,CALU1 +S 1800,2900,1800,2900,200,ry0,LEFT,CALU1 +S 2000,1100,2300,1100,200,*,LEFT,ALU1 +S 2000,600,2000,1100,200,iy1,UP,CALU1 +S 2700,3400,3000,3400,200,*,LEFT,ALU1 +S 2700,2900,2700,3400,200,ix0,UP,CALU1 +S 3000,3400,3000,4400,200,ix0,DOWN,CALU1 +S 3000,600,3000,1900,200,ix0,DOWN,CALU1 +S 2300,1100,2300,2400,200,iy1,DOWN,CALU1 +S 300,1100,300,3900,200,iy0,UP,CALU1 +S 4400,2100,4700,2100,200,*,RIGHT,POLY2 +S 3700,2100,3900,2100,200,*,RIGHT,POLY2 +S 3700,2900,3900,2900,200,*,RIGHT,POLY2 +S 3200,2900,3300,2900,200,*,RIGHT,POLY2 +S 2200,2100,2300,2100,200,*,LEFT,POLY2 +S 2700,2900,2800,2900,200,*,RIGHT,POLY2 +S 300,2100,600,2100,200,*,RIGHT,POLY2 +S 4700,1100,4700,3900,200,ix1,DOWN,CALU1 +S 3700,2900,3700,2900,200,rx0,LEFT,CALU1 +S 3200,2900,3200,2900,200,rx1,LEFT,CALU1 +S 3700,2100,3700,2400,200,*,DOWN,ALU1 +S 3200,2400,3700,2400,200,*,RIGHT,ALU1 +S 3200,2400,3200,2900,200,*,DOWN,ALU1 +S 4200,600,4200,4400,200,nqx,UP,CALU1 +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +S 0,1100,5000,1100,1400,*,LEFT,PWELL +S 0,0,5000,0,300,*,RIGHT,PTIE +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 3300,3200,3300,4700,100,*,UP,PTRANS +S 4400,300,4400,1100,100,*,DOWN,NTRANS +S 4400,3200,4400,4700,100,*,UP,PTRANS +S 2800,300,2800,1100,100,*,DOWN,NTRANS +S 2800,3200,2800,4700,100,*,UP,PTRANS +S 3300,300,3300,1100,100,*,DOWN,NTRANS +S 3900,300,3900,1100,100,*,DOWN,NTRANS +S 3900,3200,3900,4700,100,*,UP,PTRANS +S 3600,500,3600,900,300,*,UP,NDIF +S 4700,500,4700,900,300,*,UP,NDIF +S 3600,3400,3600,4500,300,*,DOWN,PDIF +S 4700,3400,4700,4500,300,*,DOWN,PDIF +S 3900,1100,3900,2100,100,*,UP,POLY +S 3300,1100,3300,2500,100,*,DOWN,POLY +S 3300,2900,3300,3200,100,*,DOWN,POLY +S 3900,2500,3900,3200,100,*,DOWN,POLY +S 3300,2500,3900,2500,100,*,LEFT,POLY +S 4400,1100,4400,3200,100,*,DOWN,POLY +S 2800,1100,2800,3200,100,*,DOWN,POLY +S 4700,0,4700,600,200,*,DOWN,ALU1 +S 3600,4400,4200,4400,200,*,RIGHT,ALU1 +S 4700,4400,4700,5000,200,*,UP,ALU1 +S 3600,3500,4200,3500,200,*,RIGHT,ALU1 +S 3600,600,4200,600,200,*,RIGHT,ALU1 +S 1700,3200,1700,4700,100,*,DOWN,PTRANS +S 600,300,600,1100,100,*,UP,NTRANS +S 600,3200,600,4700,100,*,DOWN,PTRANS +S 2200,300,2200,1100,100,*,UP,NTRANS +S 2200,3200,2200,4700,100,*,DOWN,PTRANS +S 1700,300,1700,1100,100,*,UP,NTRANS +S 1100,300,1100,1100,100,*,UP,NTRANS +S 1100,3200,1100,4700,100,*,DOWN,PTRANS +S 2500,500,2500,900,300,*,DOWN,NDIF +S 300,500,300,900,300,*,DOWN,NDIF +S 1400,500,1400,900,300,*,DOWN,NDIF +S 2500,3400,2500,4500,300,*,UP,PDIF +S 300,3400,300,4500,300,*,UP,PDIF +S 1400,3400,1400,4500,300,*,UP,PDIF +S 600,1100,600,3200,100,*,UP,POLY +S 2200,1100,2200,3200,100,*,UP,POLY +S 300,0,300,600,200,*,UP,ALU1 +S 2500,0,2500,600,200,*,UP,ALU1 +S 300,4400,300,5000,200,*,DOWN,ALU1 +V 2500,3900,CONT_DIF_P,* +V 2900,1600,CONT_POLY,* +V 1800,2900,CONT_POLY,* +V 1300,2100,CONT_POLY,* +V 1300,2900,CONT_POLY,* +V 2300,2100,CONT_POLY,* +V 2700,2900,CONT_POLY,* +V 5000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4700,600,CONT_DIF_N,* +V 3600,600,CONT_DIF_N,* +V 4700,4400,CONT_DIF_P,* +V 3600,3500,CONT_DIF_P,* +V 3600,4400,CONT_DIF_P,* +V 3200,2900,CONT_POLY,* +V 3700,2100,CONT_POLY,* +V 3700,2900,CONT_POLY,* +V 4700,2100,CONT_POLY,* +V 300,600,CONT_DIF_N,* +V 2500,600,CONT_DIF_N,* +V 1400,600,CONT_DIF_N,* +V 1400,4400,CONT_DIF_P,* +V 2500,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 1400,3500,CONT_DIF_P,* +V 300,2100,CONT_POLY,* +V 500,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22.vbe new file mode 100644 index 000000000..730139b96 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22.vbe @@ -0,0 +1,40 @@ +ENTITY sram_noa2a22 IS +PORT ( + rx0 : in BIT; + rx1 : in BIT; + ix0 : in BIT; + ix1 : in BIT; + nqx : out MUX_BIT BUS; + + ry0 : in BIT; + ry1 : in BIT; + iy0 : in BIT; + iy1 : in BIT; + nqy : out MUX_BIT BUS; + + vdd : in BIT; + vss : in BIT +); +END sram_noa2a22; + +ARCHITECTURE behaviour_data_flow OF sram_noa2a22 IS + +BEGIN + lnqx0 : BLOCK ((ix0 AND rx0) OR (ix1 AND rx1)) + BEGIN + nqx <= GUARDED '0'; + END BLOCK lnqx0; + lnqx1 : BLOCK ((NOT(ix0) AND NOT(rx1)) OR (NOT(ix1) AND NOT(rx0))) + BEGIN + nqx <= GUARDED '1'; + END BLOCK lnqx1; + + lnqy0 : BLOCK ((iy0 AND ry0) OR (ry1 AND iy1)) + BEGIN + nqy <= GUARDED '0'; + END BLOCK lnqy0; + lnqy1 : BLOCK ((NOT(iy0) AND NOT(ry1)) OR (NOT(iy1) AND NOT(ry0))) + BEGIN + nqy <= GUARDED '1'; + END BLOCK lnqy1; +END; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22ct.ap b/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22ct.ap new file mode 100644 index 000000000..ae2e1dc76 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22ct.ap @@ -0,0 +1,138 @@ +V ALLIANCE : 6 +H sram_noa2a22ct,P,20/ 8/2024,100 +A 0,0,5000,5000 +R 3900,100,ref_ref,ax2 +R 1300,5100,ref_ref,ay2 +R 3900,4600,ref_ref,ax1 +R 1300,4100,ref_ref,ay1 +R 3900,1600,ref_ref,ax0 +R 1300,1600,ref_ref,ay0 +R 4400,2100,ref_ref,rx0 +R 600,2100,ref_ref,ry1 +R 3200,2100,ref_ref,rx1 +R 1800,2100,ref_ref,ry0 +R 0,0,ref_ref,vss0 +R 5000,0,ref_ref,vss1 +R 0,5000,ref_ref,vdd0 +R 5000,5000,ref_ref,vdd1 +S 1300,1600,1300,1800,200,ay,DOWN,CALU1 +S 1200,2800,1200,5000,200,*,DOWN,ALU1 +S 3800,2800,3800,5000,200,*,DOWN,ALU1 +S 3700,2300,4400,2300,200,*,RIGHT,ALU1 +S 3900,1800,4100,1800,200,*,RIGHT,POLY2 +S 3500,2300,3700,2300,200,*,LEFT,POLY2 +S 1300,1800,1500,1800,200,*,RIGHT,POLY2 +S 900,2300,1100,2300,200,*,LEFT,POLY2 +S 3900,1600,3900,1800,200,ax,UP,CALU1 +S 1300,1600,1300,1800,200,*,UP,ALU1 +S 3800,0,3800,1000,200,*,DOWN,ALU1 +S 1200,0,1200,1000,200,*,DOWN,ALU1 +S 600,600,600,4400,200,ry1,DOWN,CALU1 +S 3500,2400,3500,4700,100,*,UP,PTRANS +S 4100,2400,4100,4700,100,*,UP,PTRANS +S 900,2400,900,4700,100,*,UP,PTRANS +S 1500,2400,1500,4700,100,*,UP,PTRANS +S 600,2600,600,4500,300,*,DOWN,PDIF +S 1200,2600,1200,4500,300,*,DOWN,PDIF +S 1800,2600,1800,4500,300,*,DOWN,PDIF +S 3800,2600,3800,4500,300,*,DOWN,PDIF +S 4400,2600,4400,4500,300,*,DOWN,PDIF +S 3200,2600,3200,4500,300,*,DOWN,PDIF +S 3900,1800,4100,1800,200,*,RIGHT,POLY +S 3500,2300,3700,2300,200,*,LEFT,POLY +S 900,2300,1100,2300,200,*,LEFT,POLY +S 1300,1800,1500,1800,200,*,RIGHT,POLY +S 1100,2300,1800,2300,200,*,RIGHT,ALU1 +S 4100,1600,4100,2600,100,*,DOWN,POLY +S 3500,1600,3500,2600,100,*,DOWN,POLY +S 900,1600,900,2600,100,*,DOWN,POLY +S 1500,1600,1500,2600,100,*,DOWN,POLY +S 1500,300,1500,1600,100,*,DOWN,NTRANS +S 900,300,900,1600,100,*,DOWN,NTRANS +S 3500,300,3500,1600,100,*,DOWN,NTRANS +S 4100,300,4100,1600,100,*,DOWN,NTRANS +S 3200,500,3200,1400,300,*,UP,NDIF +S 3800,500,3800,1400,300,*,UP,NDIF +S 4400,500,4400,1400,300,*,UP,NDIF +S 1800,500,1800,1400,300,*,UP,NDIF +S 1200,500,1200,1400,300,*,UP,NDIF +S 600,500,600,1400,300,*,UP,NDIF +S 1800,600,1800,4400,200,ry0,DOWN,CALU1 +S 4400,600,4400,4400,200,rx0,DOWN,CALU1 +S 3200,600,3200,4400,200,rx1,DOWN,CALU1 +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +S 0,0,5000,0,300,*,RIGHT,PTIE +S 0,1100,5000,1100,1400,*,LEFT,PWELL +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +V 1200,2800,CONT_DIF_P,* +V 1200,3200,CONT_DIF_P,* +V 1200,3600,CONT_DIF_P,* +V 1200,4000,CONT_DIF_P,* +V 1200,4400,CONT_DIF_P,* +V 3800,4400,CONT_DIF_P,* +V 3800,4000,CONT_DIF_P,* +V 3800,3600,CONT_DIF_P,* +V 3800,3200,CONT_DIF_P,* +V 3800,2800,CONT_DIF_P,* +V 3800,1000,CONT_DIF_N,* +V 3800,600,CONT_DIF_N,* +V 1200,1000,CONT_DIF_N,* +V 1200,600,CONT_DIF_N,* +V 4400,3200,CONT_DIF_P,* +V 4400,2800,CONT_DIF_P,* +V 3200,3200,CONT_DIF_P,* +V 3200,2800,CONT_DIF_P,* +V 600,3200,CONT_DIF_P,* +V 1800,3200,CONT_DIF_P,* +V 1800,2800,CONT_DIF_P,* +V 600,2800,CONT_DIF_P,* +V 3200,700,CONT_DIF_N,* +V 4400,700,CONT_DIF_N,* +V 1800,700,CONT_DIF_N,* +V 600,700,CONT_DIF_N,* +V 600,1200,CONT_DIF_N,* +V 1800,1200,CONT_DIF_N,* +V 4400,1200,CONT_DIF_N,* +V 3200,1200,CONT_DIF_N,* +V 600,3600,CONT_DIF_P,* +V 1800,3600,CONT_DIF_P,* +V 3200,3600,CONT_DIF_P,* +V 4400,3600,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 1800,4000,CONT_DIF_P,* +V 600,4000,CONT_DIF_P,* +V 3900,1800,CONT_POLY,* +V 3700,2300,CONT_POLY,* +V 1100,2300,CONT_POLY,* +V 1300,1800,CONT_POLY,* +V 1800,4400,CONT_DIF_P,* +V 600,4400,CONT_DIF_P,* +V 3200,4400,CONT_DIF_P,* +V 4400,4400,CONT_DIF_P,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22ct.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22ct.vbe new file mode 100644 index 000000000..3dee3c3d7 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_noa2a22ct.vbe @@ -0,0 +1,19 @@ +ENTITY sram_noa2a22ct IS +PORT( + ax : IN BIT; + ay : IN BIT; + rx0 : INOUT BIT; + rx1 : OUT BIT; + ry0 : INOUT BIT; + ry1 : OUT BIT; + vdd : IN BIT; + vss : IN BIT ); +END sram_noa2a22ct; + +ARCHITECTURE VBE OF sram_noa2a22ct IS +BEGIN + rx0 <= NOT(ax); + rx1 <= NOT(rx0); + ry0 <= NOT(ay); + ry1 <= NOT(ry0); +END VBE; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_w2dec4.ap b/ips/lsxram/coriolis/ips/lsxram/sram_w2dec4.ap new file mode 100644 index 000000000..6302b7b7c --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_w2dec4.ap @@ -0,0 +1,490 @@ +V ALLIANCE : 6 +H sram_w2dec4,P,22/ 8/2024,100 +A 0,0,18500,5000 +R 5500,1200,ref_ref,wt_0 +R 15300,3200,ref_ref,az_11 +R 1900,3200,ref_ref,az_01 +R 10500,2700,ref_ref,at_11 +R 400,4200,ref_ref,az_00 +R 11500,700,ref_ref,wt_1 +R 13200,1200,ref_ref,az1 +R 4000,1200,ref_ref,az0 +R 14300,700,ref_ref,wz_1 +R 2900,700,ref_ref,wz_0 +R 8300,3700,ref_ref,at_10 +R 7700,3700,ref_ref,at_00 +R 18100,4200,ref_ref,az_10 +R 12600,700,ref_ref,at1 +R 4600,700,ref_ref,at0 +R 6700,2700,ref_ref,at_01 +R 6200,1700,ref_ref,at_02 +R 11000,1700,ref_ref,at_12 +R 2400,2200,ref_ref,az_02 +R 14800,2200,ref_ref,az_12 +S 5500,1200,5700,1200,200,wt_0,LEFT,CALU1 +S 5200,0,5200,500,200,*,DOWN,ALU1 +S 10100,3900,10100,4400,200,*,DOWN,ALU1 +S 15700,3900,15700,4400,200,*,DOWN,ALU1 +S 7100,3900,7100,4400,200,*,DOWN,ALU1 +S 1500,3900,1500,4400,200,*,DOWN,ALU1 +S 15800,1300,15800,3900,200,*,DOWN,ALU1 +S 10000,1300,10000,3900,200,*,DOWN,ALU1 +S 7200,1300,7200,3900,200,*,UP,ALU1 +S 1400,1300,1400,3900,200,*,DOWN,ALU1 +S 1500,3900,2700,3900,200,*,RIGHT,ALU1 +S 16200,1700,16200,2700,100,*,UP,POLY +S 16000,2700,16000,3400,100,*,DOWN,POLY +S 9800,2700,9800,3400,100,*,UP,POLY +S 9600,1700,9600,2700,100,*,UP,POLY +S 7600,1700,7600,2700,100,*,UP,POLY +S 7400,2700,7400,3400,100,*,DOWN,POLY +S 1200,2700,1200,3400,100,*,UP,POLY +S 1000,1700,1000,2700,100,*,UP,POLY +S 1000,2700,1200,2700,100,*,RIGHT,POLY +S 7400,2700,7600,2700,100,*,RIGHT,POLY +S 16000,2700,16200,2700,100,*,RIGHT,POLY +S 9600,2700,9800,2700,100,*,RIGHT,POLY +S 8300,0,8300,600,200,*,DOWN,ALU1 +S 7700,1800,7700,3700,200,at_0[0],DOWN,CALU1 +S 7700,4400,7700,5000,200,*,UP,ALU1 +S 8300,1200,8300,3700,200,at_1[0],DOWN,CALU1 +S 6800,1600,6800,1700,100,*,UP,POLY +S 15400,1600,15400,1700,100,*,UP,POLY +S 15400,3300,15400,3400,100,*,DOWN,POLY +S 6800,3300,6800,3400,100,*,DOWN,POLY +S 8900,2200,9500,2200,200,*,RIGHT,ALU1 +S 13500,2200,15800,2200,200,*,LEFT,POLY +S 13500,2200,15800,2200,200,*,LEFT,POLY2 +S 10000,2200,12300,2200,200,*,RIGHT,POLY2 +S 16300,2200,16900,2200,200,*,RIGHT,ALU1 +S 400,2200,900,2200,200,*,RIGHT,ALU1 +S 15300,1700,15400,1700,200,*,RIGHT,POLY2 +S 15300,3300,15400,3300,200,*,RIGHT,POLY2 +S 11000,600,11000,3400,200,at_1[2],UP,CALU1 +S 2900,600,2900,3400,200,wz_0,UP,CALU1 +S 2400,600,2400,3400,200,az_0[2],UP,CALU1 +S 13200,600,13200,4400,200,az1,DOWN,CALU1 +S 12600,600,12600,4400,200,at1,UP,CALU1 +S 4000,600,4000,4400,200,az0,UP,CALU1 +S 4600,600,4600,4400,200,at0,DOWN,CALU1 +S 6700,600,6700,3400,200,at_0[1],DOWN,CALU1 +S 10500,600,10500,3400,200,at_1[1],UP,CALU1 +S 6200,600,6200,3400,200,at_0[2],DOWN,CALU1 +S 11500,600,11500,3400,200,wt_1,UP,CALU1 +S 5700,600,5700,3400,200,wt_0,DOWN,CALU1 +S 18100,700,18100,4200,200,az_1[0],DOWN,CALU1 +S 400,600,400,4200,200,az_0[0],DOWN,CALU1 +S 14300,600,14300,3400,200,wz_1,DOWN,CALU1 +S 0,0,18500,0,400,vss,RIGHT,CALU1 +S 0,5000,18500,5000,400,vdd,RIGHT,CALU1 +S 14800,600,14800,3400,200,az_1[2],DOWN,CALU1 +S 15300,600,15300,3400,200,az_1[1],DOWN,CALU1 +S 1900,600,1900,3400,200,az_0[1],UP,CALU1 +S 0,1100,18500,1100,1400,*,RIGHT,PWELL +S 0,3100,18500,3100,1200,*,RIGHT,NWELL +S 0,4000,18500,4000,1200,*,RIGHT,NWELL +S 0,5000,18500,5000,300,*,RIGHT,NTIE +S 0,0,18500,0,300,*,RIGHT,PTIE +S 15400,3400,15400,4700,100,*,UP,PTRANS +S 10400,300,10400,1600,100,*,UP,NTRANS +S 17200,3400,17200,4700,100,*,UP,PTRANS +S 17200,300,17200,1100,100,*,DOWN,NTRANS +S 5600,3400,5600,4700,100,*,UP,PTRANS +S 4900,2400,4900,4700,100,*,DOWN,PTRANS +S 10400,3400,10400,4700,100,*,DOWN,PTRANS +S 11000,3400,11000,4700,100,*,DOWN,PTRANS +S 14200,300,14200,1600,100,*,DOWN,NTRANS +S 14800,300,14800,1600,100,*,DOWN,NTRANS +S 13500,2400,13500,4700,100,*,DOWN,PTRANS +S 14800,3400,14800,4700,100,*,UP,PTRANS +S 3000,3400,3000,4700,100,*,DOWN,PTRANS +S 3700,2400,3700,4700,100,*,UP,PTRANS +S 15400,300,15400,1600,100,*,DOWN,NTRANS +S 13500,300,13500,1600,100,*,UP,NTRANS +S 8600,300,8600,1100,100,*,DOWN,NTRANS +S 8600,3400,8600,4700,100,*,UP,PTRANS +S 12300,2400,12300,4700,100,*,UP,PTRANS +S 9800,3400,9800,4700,100,*,DOWN,PTRANS +S 1800,300,1800,1600,100,*,UP,NTRANS +S 3700,300,3700,1600,100,*,DOWN,NTRANS +S 11600,300,11600,1600,100,*,UP,NTRANS +S 11000,300,11000,1600,100,*,UP,NTRANS +S 9800,300,9800,1600,100,*,UP,NTRANS +S 14200,3400,14200,4700,100,*,UP,PTRANS +S 6800,300,6800,1600,100,*,DOWN,NTRANS +S 4900,300,4900,1600,100,*,UP,NTRANS +S 6200,300,6200,1600,100,*,DOWN,NTRANS +S 7400,300,7400,1600,100,*,DOWN,NTRANS +S 12300,300,12300,1600,100,*,DOWN,NTRANS +S 11600,3400,11600,4700,100,*,DOWN,PTRANS +S 16000,3400,16000,4700,100,*,UP,PTRANS +S 16000,300,16000,1600,100,*,DOWN,NTRANS +S 2400,3400,2400,4700,100,*,DOWN,PTRANS +S 3000,300,3000,1600,100,*,UP,NTRANS +S 6200,3400,6200,4700,100,*,UP,PTRANS +S 5600,300,5600,1600,100,*,DOWN,NTRANS +S 2400,300,2400,1600,100,*,UP,NTRANS +S 1200,300,1200,1600,100,*,UP,NTRANS +S 7400,3400,7400,4700,100,*,UP,PTRANS +S 6800,3400,6800,4700,100,*,UP,PTRANS +S 1200,3400,1200,4700,100,*,DOWN,PTRANS +S 1800,3400,1800,4700,100,*,DOWN,PTRANS +S 8300,500,8300,900,300,*,UP,NDIF +S 8900,500,8900,900,300,*,UP,NDIF +S 17500,500,17500,900,300,*,UP,NDIF +S 16900,500,16900,900,300,*,UP,NDIF +S 16300,600,16300,1400,300,*,DOWN,NDIF +S 10100,500,10100,1400,300,*,UP,NDIF +S 12600,500,12600,1400,300,*,DOWN,NDIF +S 9500,600,9500,1400,300,*,UP,NDIF +S 900,600,900,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +S 2700,500,2700,1400,300,*,UP,NDIF +S 3400,500,3400,1400,300,*,DOWN,NDIF +S 15700,500,15700,1400,300,*,DOWN,NDIF +S 15100,500,15100,1400,300,*,DOWN,NDIF +S 14500,500,14500,1400,300,*,DOWN,NDIF +S 12000,500,12000,1400,300,*,DOWN,NDIF +S 7100,500,7100,1400,300,*,DOWN,NDIF +S 5900,500,5900,1400,300,*,DOWN,NDIF +S 4600,500,4600,1400,300,*,UP,NDIF +S 5200,500,5200,1400,300,*,UP,NDIF +S 13800,500,13800,1400,300,*,UP,NDIF +S 13200,500,13200,1400,300,*,UP,NDIF +S 10700,500,10700,1400,300,*,UP,NDIF +S 11300,500,11300,1400,300,*,UP,NDIF +S 6500,500,6500,1400,300,*,DOWN,NDIF +S 7700,600,7700,1400,300,*,DOWN,NDIF +S 2100,500,2100,1400,300,*,UP,NDIF +S 4000,500,4000,1400,300,*,DOWN,NDIF +S 12600,2600,12600,4500,300,*,UP,PDIF +S 15100,3600,15100,4500,300,*,DOWN,PDIF +S 13200,2600,13200,4500,300,*,DOWN,PDIF +S 10100,3600,10100,4500,300,*,UP,PDIF +S 14500,3600,14500,4500,300,*,DOWN,PDIF +S 9500,3600,9500,4500,300,*,UP,PDIF +S 8300,3600,8300,4400,300,*,UP,PDIF +S 17600,3600,17600,4400,300,*,UP,PDIF +S 16300,3600,16300,4500,300,*,DOWN,PDIF +S 13800,2600,13800,4500,300,*,DOWN,PDIF +S 11300,3600,11300,4500,300,*,UP,PDIF +S 15700,3600,15700,4500,300,*,DOWN,PDIF +S 12000,2600,12000,4500,300,*,UP,PDIF +S 10700,3600,10700,4500,300,*,UP,PDIF +S 8900,3600,8900,4500,300,*,DOWN,PDIF +S 16900,3600,16900,4500,300,*,DOWN,PDIF +S 2700,3600,2700,4500,300,*,UP,PDIF +S 2100,3600,2100,4500,300,*,UP,PDIF +S 900,3600,900,4500,300,*,UP,PDIF +S 4000,2600,4000,4500,300,*,UP,PDIF +S 5200,2600,5200,4500,300,*,DOWN,PDIF +S 7700,3600,7700,4500,300,*,DOWN,PDIF +S 7100,3600,7100,4500,300,*,DOWN,PDIF +S 5900,3600,5900,4500,300,*,DOWN,PDIF +S 6500,3600,6500,4500,300,*,DOWN,PDIF +S 4600,2600,4600,4500,300,*,DOWN,PDIF +S 3400,2600,3400,4500,300,*,UP,PDIF +S 1500,3600,1500,4500,300,*,UP,PDIF +S 17200,1100,17200,3400,100,*,DOWN,POLY +S 8600,1100,8600,3400,100,*,DOWN,POLY +S 10400,1600,10400,1700,100,*,UP,POLY +S 10400,3300,10400,3400,100,*,DOWN,POLY +S 17200,2200,17400,2200,200,*,RIGHT,POLY +S 9800,1600,9800,1700,100,*,DOWN,POLY +S 16000,1700,16200,1700,100,*,RIGHT,POLY +S 14800,1600,14800,1700,100,*,DOWN,POLY +S 9600,1700,9800,1700,100,*,LEFT,POLY +S 13500,1600,13500,2400,100,*,DOWN,POLY +S 11000,3300,11000,3400,100,*,DOWN,POLY +S 11600,1600,11600,1700,100,*,UP,POLY +S 10000,2200,12300,2200,200,*,RIGHT,POLY +S 16000,1600,16000,1700,100,*,UP,POLY +S 8400,2200,8600,2200,200,*,RIGHT,POLY +S 11600,3300,11600,3400,100,*,DOWN,POLY +S 11000,1600,11000,1700,100,*,UP,POLY +S 5600,3300,5600,3400,100,*,DOWN,POLY +S 6200,3300,6200,3400,100,*,UP,POLY +S 4900,2200,7200,2200,200,*,LEFT,POLY +S 1800,1600,1800,1700,100,*,UP,POLY +S 12300,1600,12300,2400,100,*,UP,POLY +S 14200,3300,14200,3400,100,*,DOWN,POLY +S 14800,3300,14800,3400,100,*,UP,POLY +S 14200,1600,14200,1700,100,*,DOWN,POLY +S 7400,1600,7400,1700,100,*,DOWN,POLY +S 5600,1600,5600,1700,100,*,DOWN,POLY +S 2400,3300,2400,3400,100,*,DOWN,POLY +S 3000,3300,3000,3400,100,*,DOWN,POLY +S 1400,2200,3700,2200,200,*,RIGHT,POLY +S 1800,3300,1800,3400,100,*,DOWN,POLY +S 7400,1700,7600,1700,100,*,RIGHT,POLY +S 1200,1600,1200,1700,100,*,DOWN,POLY +S 1000,1700,1200,1700,100,*,LEFT,POLY +S 3700,1600,3700,2400,100,*,UP,POLY +S 4900,1600,4900,2400,100,*,DOWN,POLY +S 6200,1600,6200,1700,100,*,DOWN,POLY +S 2400,1600,2400,1700,100,*,UP,POLY +S 3000,1600,3000,1700,100,*,UP,POLY +S 2900,1700,3000,1700,200,*,LEFT,POLY2 +S 11500,1700,11600,1700,200,*,LEFT,POLY2 +S 6700,3300,6800,3300,200,*,RIGHT,POLY2 +S 10400,3300,10500,3300,200,*,RIGHT,POLY2 +S 11500,3300,11600,3300,200,*,LEFT,POLY2 +S 17200,2200,17400,2200,200,*,RIGHT,POLY2 +S 8400,2200,8600,2200,200,*,RIGHT,POLY2 +S 5600,1700,5700,1700,200,*,LEFT,POLY2 +S 14200,3300,14300,3300,200,*,LEFT,POLY2 +S 1400,2200,3700,2200,200,*,RIGHT,POLY2 +S 5600,3300,5700,3300,200,*,LEFT,POLY2 +S 1800,3300,1900,3300,200,*,RIGHT,POLY2 +S 2900,3300,3000,3300,200,*,LEFT,POLY2 +S 1800,1700,1900,1700,200,*,RIGHT,POLY2 +S 4900,2200,7200,2200,200,*,RIGHT,POLY2 +S 10400,1700,10500,1700,200,*,RIGHT,POLY2 +S 14200,1700,14300,1700,200,*,LEFT,POLY2 +S 6700,1700,6800,1700,200,*,RIGHT,POLY2 +S 3400,0,3400,1300,200,*,UP,ALU1 +S 12000,0,12000,1300,200,*,UP,ALU1 +S 13800,0,13800,1300,200,*,DOWN,ALU1 +S 17500,0,17500,600,200,*,DOWN,ALU1 +S 16900,600,16900,4400,200,*,DOWN,ALU1 +S 9500,3900,9500,5000,200,*,UP,ALU1 +S 17400,2200,18100,2200,200,*,LEFT,ALU1 +S 17600,3900,17600,5000,200,*,DOWN,ALU1 +S 16300,600,16300,1300,200,*,DOWN,ALU1 +S 15800,1300,16300,1300,200,*,RIGHT,ALU1 +S 9500,600,9500,1300,200,*,DOWN,ALU1 +S 10100,3900,11300,3900,200,*,LEFT,ALU1 +S 14500,3900,15700,3900,200,*,RIGHT,ALU1 +S 11300,3900,11300,4400,200,*,UP,ALU1 +S 15100,4400,15100,5000,200,*,DOWN,ALU1 +S 9500,1300,10000,1300,200,*,LEFT,ALU1 +S 14500,3900,14500,4400,200,*,DOWN,ALU1 +S 8300,2200,8400,2200,200,*,RIGHT,ALU1 +S 12000,2700,12000,5000,200,*,DOWN,ALU1 +S 10700,4400,10700,5000,200,*,UP,ALU1 +S 8900,600,8900,4400,200,*,DOWN,ALU1 +S 13800,2700,13800,5000,200,*,UP,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 5900,3900,5900,4400,200,*,DOWN,ALU1 +S 5200,2700,5200,5000,200,*,UP,ALU1 +S 8300,4400,8300,5000,200,*,DOWN,ALU1 +S 2700,3900,2700,4400,200,*,UP,ALU1 +S 900,600,900,1300,200,*,DOWN,ALU1 +S 5900,3900,7100,3900,200,*,RIGHT,ALU1 +S 900,1300,1400,1300,200,*,LEFT,ALU1 +S 3400,2700,3400,5000,200,*,DOWN,ALU1 +S 6500,4400,6500,5000,200,*,DOWN,ALU1 +S 16300,3900,16300,5000,200,*,DOWN,ALU1 +S 900,3900,900,5000,200,*,UP,ALU1 +S 7200,1300,7700,1300,200,*,LEFT,ALU1 +S 7700,600,7700,1300,200,*,UP,ALU1 +V 9500,2200,CONT_POLY,* +V 16300,2200,CONT_POLY,* +V 7700,2200,CONT_POLY,* +V 900,2200,CONT_POLY,* +V 13800,1300,CONT_DIF_N,* +V 13200,600,CONT_DIF_N,* +V 13200,1300,CONT_DIF_N,* +V 12000,1300,CONT_DIF_N,* +V 4600,600,CONT_DIF_N,* +V 7700,600,CONT_DIF_N,* +V 4000,600,CONT_DIF_N,* +V 4000,1300,CONT_DIF_N,* +V 12600,600,CONT_DIF_N,* +V 12600,1300,CONT_DIF_N,* +V 9500,600,CONT_DIF_N,* +V 9500,1300,CONT_DIF_N,* +V 900,1300,CONT_DIF_N,* +V 3400,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 3400,1300,CONT_DIF_N,* +V 16900,600,CONT_DIF_N,* +V 17500,600,CONT_DIF_N,* +V 16300,600,CONT_DIF_N,* +V 16300,1300,CONT_DIF_N,* +V 5200,600,CONT_DIF_N,* +V 4600,1300,CONT_DIF_N,* +V 7700,1300,CONT_DIF_N,* +V 13800,600,CONT_DIF_N,* +V 12000,600,CONT_DIF_N,* +V 8900,600,CONT_DIF_N,* +V 8300,600,CONT_DIF_N,* +V 16900,4400,CONT_DIF_P,* +V 17600,4400,CONT_DIF_P,* +V 17600,3900,CONT_DIF_P,* +V 9500,3900,CONT_DIF_P,* +V 13800,2700,CONT_DIF_P,* +V 13800,3300,CONT_DIF_P,* +V 13200,4400,CONT_DIF_P,* +V 12000,2700,CONT_DIF_P,* +V 12000,3300,CONT_DIF_P,* +V 13800,4400,CONT_DIF_P,* +V 12000,3900,CONT_DIF_P,* +V 15100,4400,CONT_DIF_P,* +V 10100,3900,CONT_DIF_P,* +V 15700,4400,CONT_DIF_P,* +V 11300,3900,CONT_DIF_P,* +V 15700,3900,CONT_DIF_P,* +V 14500,3900,CONT_DIF_P,* +V 13200,3900,CONT_DIF_P,* +V 16900,3900,CONT_DIF_P,* +V 13200,2700,CONT_DIF_P,* +V 12600,3300,CONT_DIF_P,* +V 13200,3300,CONT_DIF_P,* +V 12600,4400,CONT_DIF_P,* +V 12600,2700,CONT_DIF_P,* +V 11300,4400,CONT_DIF_P,* +V 12000,4400,CONT_DIF_P,* +V 14500,4400,CONT_DIF_P,* +V 10100,4400,CONT_DIF_P,* +V 8900,4400,CONT_DIF_P,* +V 8900,3900,CONT_DIF_P,* +V 8300,4400,CONT_DIF_P,* +V 16300,4400,CONT_DIF_P,* +V 10700,4400,CONT_DIF_P,* +V 12600,3900,CONT_DIF_P,* +V 13800,3900,CONT_DIF_P,* +V 4600,3900,CONT_DIF_P,* +V 4600,2700,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 7100,3900,CONT_DIF_P,* +V 5200,3300,CONT_DIF_P,* +V 6500,4400,CONT_DIF_P,* +V 5900,3900,CONT_DIF_P,* +V 9500,4400,CONT_DIF_P,* +V 5200,4400,CONT_DIF_P,* +V 5900,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 4600,4400,CONT_DIF_P,* +V 5200,2700,CONT_DIF_P,* +V 4600,3300,CONT_DIF_P,* +V 7100,4400,CONT_DIF_P,* +V 4000,4400,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 4000,3900,CONT_DIF_P,* +V 3400,2700,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 5200,3900,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 4000,3300,CONT_DIF_P,* +V 4000,2700,CONT_DIF_P,* +V 900,3900,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 3400,3300,CONT_DIF_P,* +V 16300,3900,CONT_DIF_P,* +V 7700,4400,CONT_DIF_P,* +V 3400,4400,CONT_DIF_P,* +V 3400,3900,CONT_DIF_P,* +V 5500,5000,CONT_BODY_N,* +V 8000,5000,CONT_BODY_N,* +V 7500,5000,CONT_BODY_N,* +V 7000,5000,CONT_BODY_N,* +V 6500,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 6500,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 12000,5000,CONT_BODY_N,* +V 16500,5000,CONT_BODY_N,* +V 17000,5000,CONT_BODY_N,* +V 16000,5000,CONT_BODY_N,* +V 17500,5000,CONT_BODY_N,* +V 17000,5000,CONT_BODY_N,* +V 10000,5000,CONT_BODY_N,* +V 14500,5000,CONT_BODY_N,* +V 15500,5000,CONT_BODY_N,* +V 15000,5000,CONT_BODY_N,* +V 13000,5000,CONT_BODY_N,* +V 13500,5000,CONT_BODY_N,* +V 12500,5000,CONT_BODY_N,* +V 14000,5000,CONT_BODY_N,* +V 8000,5000,CONT_BODY_N,* +V 8500,5000,CONT_BODY_N,* +V 9500,5000,CONT_BODY_N,* +V 9000,5000,CONT_BODY_N,* +V 11000,5000,CONT_BODY_N,* +V 11500,5000,CONT_BODY_N,* +V 10500,5000,CONT_BODY_N,* +V 18500,5000,CONT_BODY_N,* +V 18000,5000,CONT_BODY_N,* +V 6500,0,CONT_BODY_P,* +V 8000,0,CONT_BODY_P,* +V 7500,0,CONT_BODY_P,* +V 7000,0,CONT_BODY_P,* +V 6500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 15000,0,CONT_BODY_P,* +V 16500,0,CONT_BODY_P,* +V 16000,0,CONT_BODY_P,* +V 17000,0,CONT_BODY_P,* +V 17500,0,CONT_BODY_P,* +V 17000,0,CONT_BODY_P,* +V 11500,0,CONT_BODY_P,* +V 11000,0,CONT_BODY_P,* +V 12500,0,CONT_BODY_P,* +V 13500,0,CONT_BODY_P,* +V 14000,0,CONT_BODY_P,* +V 13000,0,CONT_BODY_P,* +V 15500,0,CONT_BODY_P,* +V 14500,0,CONT_BODY_P,* +V 8000,0,CONT_BODY_P,* +V 8500,0,CONT_BODY_P,* +V 9500,0,CONT_BODY_P,* +V 9000,0,CONT_BODY_P,* +V 10000,0,CONT_BODY_P,* +V 12000,0,CONT_BODY_P,* +V 10500,0,CONT_BODY_P,* +V 18500,0,CONT_BODY_P,* +V 18000,0,CONT_BODY_P,* +V 10000,2200,CONT_POLY,* +V 14800,3300,CONT_POLY,* +V 15300,1700,CONT_POLY,* +V 11000,3300,CONT_POLY,* +V 15800,2200,CONT_POLY,* +V 17400,2200,CONT_POLY,* +V 15300,3300,CONT_POLY,* +V 10500,1700,CONT_POLY,* +V 14300,1700,CONT_POLY,* +V 14300,3300,CONT_POLY,* +V 11500,1700,CONT_POLY,* +V 14800,1700,CONT_POLY,* +V 11000,1700,CONT_POLY,* +V 6200,1700,CONT_POLY,* +V 6200,3300,CONT_POLY,* +V 11500,3300,CONT_POLY,* +V 8400,2200,CONT_POLY,* +V 10500,3300,CONT_POLY,* +V 6700,3300,CONT_POLY,* +V 2400,1700,CONT_POLY,* +V 6700,1700,CONT_POLY,* +V 7200,2200,CONT_POLY,* +V 5700,3300,CONT_POLY,* +V 2900,1700,CONT_POLY,* +V 1900,3300,CONT_POLY,* +V 5700,1700,CONT_POLY,* +V 2400,3300,CONT_POLY,* +V 1900,1700,CONT_POLY,* +V 2900,3300,CONT_POLY,* +V 1400,2200,CONT_POLY,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_w2dec4.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_w2dec4.vbe new file mode 100644 index 000000000..8fc6fe8c3 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_w2dec4.vbe @@ -0,0 +1,36 @@ +ENTITY sram_w2dec4 IS +PORT ( + at_0 : in bit_vector(0 TO 2) ; + wt_0 : in BIT; + at0 : out BIT; + + az_0 : in bit_vector(0 TO 2) ; + wz_0 : in BIT; + az0 : out BIT; + + at_1 : in bit_vector(0 TO 2) ; + wt_1 : in BIT; + at1 : out BIT; + + az_1 : in bit_vector(0 TO 2) ; + wz_1 : in BIT; + az1 : out BIT; + + vdd : in BIT; + vss : in BIT +); +END sram_w2dec4; + +ARCHITECTURE behaviour_data_flow OF sram_w2dec4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on sram_w2dec4" + SEVERITY WARNING; + + at0 <= (wt_0 AND at_0(2) AND at_0(1) AND at_0(0)); + az0 <= (wz_0 AND az_0(2) AND az_0(1) AND az_0(0)); + az1 <= (wz_1 AND az_1(2) AND az_1(1) AND NOT(az_1(0))); + at1 <= (wt_1 AND at_1(2) AND at_1(1) AND NOT(at_1(0))); + +END; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_w2inv.ap b/ips/lsxram/coriolis/ips/lsxram/sram_w2inv.ap new file mode 100644 index 000000000..c553e2e58 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_w2inv.ap @@ -0,0 +1,87 @@ +V ALLIANCE : 6 +H sram_w2inv,P,22/ 8/2024,100 +A 0,0,2500,5000 +R 2000,3200,ref_ref,i1_3 +R 2000,2700,ref_ref,i1_2 +R 2000,2200,ref_ref,i1_1 +R 2000,1700,ref_ref,i1_0 +R 1500,3200,ref_ref,nq1_3 +R 1500,2700,ref_ref,nq1_2 +R 1500,2200,ref_ref,nq1_1 +R 1500,1700,ref_ref,nq1_0 +R 800,3200,ref_ref,i0_3 +R 800,2700,ref_ref,i0_2 +R 800,2200,ref_ref,i0_1 +R 800,1700,ref_ref,i0_0 +R 300,3200,ref_ref,nq0_3 +R 300,2700,ref_ref,nq0_2 +R 300,2200,ref_ref,nq0_1 +R 300,1700,ref_ref,nq0_0 +S 2000,1700,2000,3200,200,i1,UP,CALU1 +S 2100,0,2100,1200,200,*,DOWN,ALU1 +S 2100,3900,2100,5000,200,*,DOWN,ALU1 +S 1800,2200,2000,2200,200,*,RIGHT,POLY +S 1800,2200,2000,2200,200,*,RIGHT,POLY2 +S 1500,600,1500,4400,200,nq1,DOWN,CALU1 +S 1500,2600,1500,4500,300,*,UP,PDIF +S 900,0,900,1200,200,*,DOWN,ALU1 +S 900,3900,900,5000,200,*,DOWN,ALU1 +S 800,1700,800,3200,200,i0,UP,CALU1 +S 300,600,300,4400,200,nq0,DOWN,CALU1 +S 600,2200,800,2200,200,*,RIGHT,POLY +S 600,2200,800,2200,200,*,RIGHT,POLY2 +S 300,2600,300,4500,300,*,UP,PDIF +S 0,5000,2500,5000,400,vdd,RIGHT,CALU1 +S 0,0,2500,0,400,vss,RIGHT,CALU1 +S 0,4000,2500,4000,1200,*,RIGHT,NWELL +S 0,3100,2500,3100,1200,*,RIGHT,NWELL +S 0,0,2500,0,300,*,RIGHT,PTIE +S 0,1100,2500,1100,1400,*,RIGHT,PWELL +S 0,5000,2500,5000,300,*,RIGHT,NTIE +S 600,300,600,1600,100,*,DOWN,NTRANS +S 600,2400,600,4700,100,*,UP,PTRANS +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 1500,500,1500,1400,300,*,UP,NDIF +S 2100,500,2100,1400,300,*,UP,NDIF +S 900,500,900,1400,300,*,UP,NDIF +S 300,500,300,1400,300,*,UP,NDIF +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 900,2600,900,4500,300,*,DOWN,PDIF +S 1800,1600,1800,2400,100,*,DOWN,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +V 2000,2200,CONT_POLY,* +V 2100,1200,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 2100,3900,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 1500,2700,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 1500,3300,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 1500,1200,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 900,1200,CONT_DIF_N,* +V 900,4400,CONT_DIF_P,* +V 900,3900,CONT_DIF_P,* +V 800,2200,CONT_POLY,* +V 300,4400,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 300,2700,CONT_DIF_P,* +V 300,3300,CONT_DIF_P,* +V 300,1200,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 500,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_w2inv.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_w2inv.vbe new file mode 100644 index 000000000..f7453300b --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_w2inv.vbe @@ -0,0 +1,20 @@ +ENTITY sram_w2inv IS +PORT ( + i0 : in BIT; + i1 : in BIT; + nq0 : out BIT; + nq1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END sram_w2inv; + +ARCHITECTURE behaviour_data_flow OF sram_w2inv IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on sram_w2inv" + SEVERITY WARNING; + nq0 <= not (i0); + nq1 <= not (i1); +END; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nff.ap b/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nff.ap new file mode 100644 index 000000000..06aecf09a --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nff.ap @@ -0,0 +1,668 @@ +V ALLIANCE : 6 +H sram_w2r2nff,P,21/ 8/2024,100 +A 0,0,21000,5000 +R 8500,5000,ref_ref,vdd2 +R 12500,1400,ref_ref,vss2 +R 21000,5000,ref_ref,vdd1 +R 0,5000,ref_ref,vdd0 +R 21000,0,ref_ref,vss1 +R 0,0,ref_ref,vss0 +R 11000,1400,ref_ref,nqy +R 10000,3400,ref_ref,nqx +R 14100,1900,ref_ref,it1 +R 6900,1900,ref_ref,it0 +R 15700,2400,ref_ref,iz1 +R 5300,2400,ref_ref,iz0 +R 1800,2900,ref_ref,ck0 +R 14600,2900,ref_ref,wt1 +R 14100,2900,ref_ref,nwt1 +R 6400,2900,ref_ref,wt0 +R 6900,2900,ref_ref,nwt0 +R 15200,2900,ref_ref,wz1 +R 15700,2900,ref_ref,nwz1 +R 5300,2900,ref_ref,nwz0 +R 5800,2900,ref_ref,wz0 +R 12000,2900,ref_ref,ry0 +R 11500,2900,ref_ref,ry1 +R 9000,2900,ref_ref,rx1 +R 18700,2900,ref_ref,nck1 +R 19200,2900,ref_ref,ck1 +R 9500,2900,ref_ref,rx0 +R 2300,2900,ref_ref,nck0 +R 1800,2900,ref_ref,ck0 +R 7500,2900,ref_ref,nwd0 +R 13500,2900,ref_ref,nwd1 +R 13000,2900,ref_ref,wd1 +R 8000,2900,ref_ref,wd0 +S 19700,3900,19700,5000,800,vdd,DOWN,CALU1 +S 17700,4400,17700,5000,200,vdd,DOWN,CALU1 +S 18100,4400,18100,5000,800,vdd,UP,CALU1 +S 12700,3900,12700,5000,400,vdd,DOWN,CALU1 +S 8900,3900,8900,5000,1400,vdd,DOWN,CALU1 +S 1300,3900,1300,5000,800,vdd,UP,CALU1 +S 19700,0,19700,1100,800,vss,UP,CALU1 +S 17400,100,17400,600,800,vss,DOWN,CALU1 +S 17100,0,17100,1100,200,vss,UP,CALU1 +S 14900,0,14900,600,1400,vss,DOWN,CALU1 +S 12600,0,12600,1900,1000,vss,DOWN,CALU1 +S 11900,1200,11900,1600,1000,vss,DOWN,CALU1 +S 8000,0,8000,1100,800,vss,UP,CALU1 +S 7800,0,7800,1600,400,vss,UP,CALU1 +S 3900,0,3900,1100,200,vss,UP,CALU1 +S 3600,0,3600,600,800,vss,DOWN,CALU1 +S 1300,0,1300,1100,800,vss,UP,CALU1 +S 16600,1600,17700,1600,200,*,LEFT,ALU1 +S 16600,600,16600,1600,200,*,UP,ALU1 +S 3300,1600,4400,1600,200,*,LEFT,ALU1 +S 4400,600,4400,1600,200,*,DOWN,ALU1 +S 9400,3400,10000,3400,200,*,RIGHT,ALU1 +S 9900,1100,10500,1100,200,*,RIGHT,ALU1 +S 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1300,3400,2100,3400,200,*,LEFT,ALU1 +S 400,600,400,4400,200,*,UP,ALU1 +S 1000,4400,1000,5000,200,*,UP,ALU1 +S 3900,2900,3900,3400,200,*,DOWN,ALU1 +S 3300,4400,3300,5000,200,*,UP,ALU1 +S 400,2700,800,2700,200,*,LEFT,ALU1 +S 1800,2100,1800,2900,200,*,UP,ALU1 +S 5000,3400,5000,3900,200,*,DOWN,ALU1 +S 4400,3400,4400,3900,200,*,DOWN,ALU1 +S 3800,3900,3800,4400,200,*,UP,ALU1 +S 2700,3400,3400,3400,200,*,LEFT,ALU1 +S 3900,3400,4400,3400,200,*,RIGHT,ALU1 +S 400,1700,800,1700,200,*,RIGHT,ALU1 +S 6100,4400,6100,5000,200,*,UP,ALU1 +S 4400,2100,4400,2900,200,*,DOWN,ALU1 +S 5000,600,5000,1100,200,*,UP,ALU1 +S 4100,2100,4400,2100,200,*,LEFT,ALU1 +S 5600,3900,5600,4400,200,*,DOWN,ALU1 +S 5600,3900,6600,3900,200,*,RIGHT,ALU1 +S 3800,4400,5600,4400,200,*,RIGHT,ALU1 +S 5000,1100,7200,1100,200,*,RIGHT,ALU1 +S 6600,4400,7800,4400,200,*,RIGHT,ALU1 +S 6600,3900,6600,4400,200,*,UP,ALU1 +S 9400,1100,9400,1100,200,*,LEFT,ALU1 +S 9400,1100,9400,1600,200,*,UP,ALU1 +S 20600,600,20600,4400,200,*,DOWN,ALU1 +S 0,0,21000,0,300,*,RIGHT,PTIE +S 0,0,21000,0,400,vss,RIGHT,CALU1 +S 0,4000,21000,4000,1200,*,RIGHT,NWELL +S 0,3100,21000,3100,1200,*,RIGHT,NWELL +S 0,5000,21000,5000,300,*,RIGHT,NTIE +S 0,5000,21000,5000,400,vdd,RIGHT,CALU1 +V 8300,3900,CONT_DIF_P,* +V 9400,3400,CONT_DIF_P,* +V 12700,1100,CONT_DIF_N,* +V 8300,1100,CONT_DIF_N,* +V 14600,2100,CONT_POLY,* +V 14100,2900,CONT_POLY,* +V 14100,2100,CONT_POLY,* +V 6400,2100,CONT_POLY,* +V 6900,2900,CONT_POLY,* +V 6900,2100,CONT_POLY,* +V 15200,2100,CONT_POLY,* +V 15700,2900,CONT_POLY,* +V 15700,2100,CONT_POLY,* +V 5800,2100,CONT_POLY,* +V 5300,2100,CONT_POLY,* +V 5300,2900,CONT_POLY,* +V 11500,2900,CONT_POLY,* +V 12000,2900,CONT_POLY,* +V 11500,2100,CONT_POLY,* +V 11600,600,CONT_DIF_N,* +V 18700,2900,CONT_POLY,* +V 17700,1600,CONT_POLY,* +V 17700,2900,CONT_POLY,* +V 3300,1600,CONT_POLY,* +V 3300,2900,CONT_POLY,* +V 2300,2900,CONT_POLY,* +V 13500,2100,CONT_POLY,* +V 7500,2100,CONT_POLY,* +V 18900,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 16000,600,CONT_DIF_N,* +V 14900,600,CONT_DIF_N,* +V 13800,600,CONT_DIF_N,* +V 20000,600,CONT_DIF_N,* +V 18900,600,CONT_DIF_N,* +V 12700,600,CONT_DIF_N,* +V 18300,600,CONT_DIF_N,* +V 17700,600,CONT_DIF_N,* +V 16600,600,CONT_DIF_N,* +V 10500,600,CONT_DIF_N,* +V 3300,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 1000,600,CONT_DIF_N,* +V 6100,600,CONT_DIF_N,* +V 5000,600,CONT_DIF_N,* +V 9400,1100,CONT_DIF_N,* +V 4400,600,CONT_DIF_N,* +V 8300,600,CONT_DIF_N,* +V 7200,600,CONT_DIF_N,* +V 20600,600,CONT_DIF_N,* +V 11600,3900,CONT_DIF_P,* +V 13800,3900,CONT_DIF_P,* +V 12700,4400,CONT_DIF_P,* +V 18300,3400,CONT_DIF_P,* +V 17700,4400,CONT_DIF_P,* +V 16600,3900,CONT_DIF_P,* +V 16000,3900,CONT_DIF_P,* +V 14900,4400,CONT_DIF_P,* +V 20000,4400,CONT_DIF_P,* +V 10500,4400,CONT_DIF_P,* +V 6100,4400,CONT_DIF_P,* +V 5000,3900,CONT_DIF_P,* +V 4400,3900,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 2700,3400,CONT_DIF_P,* +V 7200,3900,CONT_DIF_P,* +V 8300,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 20600,4400,CONT_DIF_P,* +V 10500,2100,CONT_POLY,* +V 10500,2600,CONT_POLY,* +V 17600,1100,CONT_POLY,* +V 12500,2900,CONT_POLY,* +V 17600,3400,CONT_POLY,* +V 13500,2900,CONT_POLY,* +V 16600,2900,CONT_POLY,* +V 16900,2100,CONT_POLY,* +V 20100,2200,CONT_POLY,* +V 19200,2900,CONT_POLY,* +V 18800,2100,CONT_POLY,* +V 20200,1700,CONT_POLY,* +V 20200,2700,CONT_POLY,* +V 900,2200,CONT_POLY,* +V 800,1700,CONT_POLY,* +V 800,2700,CONT_POLY,* +V 4400,2900,CONT_POLY,* +V 4100,2100,CONT_POLY,* +V 3400,1100,CONT_POLY,* +V 2200,2100,CONT_POLY,* +V 7500,2900,CONT_POLY,* +V 9500,2100,CONT_POLY,* +V 9500,2900,CONT_POLY,* +V 9000,2900,CONT_POLY,* +V 8500,2100,CONT_POLY,* +V 1800,2900,CONT_POLY,* +V 3400,3400,CONT_POLY,* +V 11500,5000,CONT_BODY_N,* +V 8000,5000,CONT_BODY_N,* +V 8500,5000,CONT_BODY_N,* +V 10000,5000,CONT_BODY_N,* +V 9500,5000,CONT_BODY_N,* +V 7000,5000,CONT_BODY_N,* +V 12500,5000,CONT_BODY_N,* +V 13000,5000,CONT_BODY_N,* +V 11000,5000,CONT_BODY_N,* +V 10500,5000,CONT_BODY_N,* +V 9000,5000,CONT_BODY_N,* +V 7500,5000,CONT_BODY_N,* +V 15000,5000,CONT_BODY_N,* +V 19000,5000,CONT_BODY_N,* +V 18500,5000,CONT_BODY_N,* +V 13500,5000,CONT_BODY_N,* +V 14000,5000,CONT_BODY_N,* +V 14500,5000,CONT_BODY_N,* +V 16000,5000,CONT_BODY_N,* +V 15500,5000,CONT_BODY_N,* +V 12000,5000,CONT_BODY_N,* +V 20000,5000,CONT_BODY_N,* +V 19500,5000,CONT_BODY_N,* +V 18000,5000,CONT_BODY_N,* +V 17500,5000,CONT_BODY_N,* +V 17000,5000,CONT_BODY_N,* +V 16500,5000,CONT_BODY_N,* +V 20500,5000,CONT_BODY_N,* +V 21000,5000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 9500,0,CONT_BODY_P,* +V 11500,0,CONT_BODY_P,* +V 7000,0,CONT_BODY_P,* +V 7500,0,CONT_BODY_P,* +V 8000,0,CONT_BODY_P,* +V 17000,0,CONT_BODY_P,* +V 13000,0,CONT_BODY_P,* +V 9000,0,CONT_BODY_P,* +V 8500,0,CONT_BODY_P,* +V 11000,0,CONT_BODY_P,* +V 10500,0,CONT_BODY_P,* +V 15000,0,CONT_BODY_P,* +V 20000,0,CONT_BODY_P,* +V 19500,0,CONT_BODY_P,* +V 19000,0,CONT_BODY_P,* +V 13500,0,CONT_BODY_P,* +V 14000,0,CONT_BODY_P,* +V 14500,0,CONT_BODY_P,* +V 12500,0,CONT_BODY_P,* +V 12000,0,CONT_BODY_P,* +V 18000,0,CONT_BODY_P,* +V 18500,0,CONT_BODY_P,* +V 16500,0,CONT_BODY_P,* +V 16000,0,CONT_BODY_P,* +V 15500,0,CONT_BODY_P,* +V 17500,0,CONT_BODY_P,* +V 20500,0,CONT_BODY_P,* +V 21000,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 6500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 6000,5000,CONT_BODY_N,* +V 6500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nff.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nff.vbe new file mode 100644 index 000000000..26acc00c8 --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nff.vbe @@ -0,0 +1,90 @@ +ENTITY sram_w2r2nff_2x1 IS + PORT ( + ck0 : in BIT; + nck0 : in BIT; + ck1 : in BIT; + nck1 : in BIT; + + it0 : in BIT; + iz0 : in BIT; + wd0 : in BIT; + nwd0 : in BIT; + wt0 : in BIT; + nwt0 : in BIT; + wz0 : in BIT; + nwz0 : in BIT; + + it1 : in BIT; + iz1 : in BIT; + wd1 : in BIT; + nwd1 : in BIT; + wt1 : in BIT; + nwt1 : in BIT; + wz1 : in BIT; + nwz1 : in BIT; + + rx0 : in BIT; + rx1 : in BIT; + ry0 : in BIT; + ry1 : in BIT; + + nqx : out MUX_BIT BUS; + nqy : out MUX_BIT BUS; + + vss : in BIT; + vdd : in BIT +); +END sram_w2r2nff_2x1; + + +ARCHITECTURE behaviour_data_flow OF sram_w2r2nff_2x1 IS + + SIGNAL m1 : REG_BIT REGISTER; + SIGNAL s1 : REG_BIT REGISTER; + SIGNAL m0 : REG_BIT REGISTER; + SIGNAL s0 : REG_BIT REGISTER; + +BEGIN + +--- Master Latches + + lmaster0 : BLOCK ((NOT(ck0) AND nck0) = '1') + BEGIN + m0 <= GUARDED ((((NOT(iz0) OR wd0 OR NOT(wz0)) AND ((((NOT(iz0) AND NOT(nwt0) AND NOT(nwz0)) OR NOT(wd0)) AND ( NOT(nwt0) OR NOT(nwz0)) AND NOT(it0) AND (NOT(iz0) OR NOT(nwt0))) OR (NOT(nwt0) AND nwz0 AND NOT(wd0) AND wt0) OR ((NOT(iz0) AND NOT(nwz0)) AND NOT(wd0) AND NOT(wt0)))) OR NOT(s0)) AND (((NOT(nwd0) OR NOT(nwz0)) AND NOT(nwd0 XOR nwt0) AND wt0) OR (NOT(it0) AND NOT(nwd0) AND NOT(nwt0)) OR NOT(iz0) OR NOT(wz0)) AND (NOT(it0) OR (NOT(iz0) AND NOT(nwd0) AND NOT(nwz0)) OR NOT( wt0)) AND ((NOT(iz0) AND NOT(nwz0)) OR (NOT(it0) AND NOT(nwt0)) OR NOT( nwd0))); + END BLOCK lmaster0; + + lmaster1 : BLOCK ((NOT(ck1) AND nck1) = '1') + BEGIN + m1 <= GUARDED ((((NOT(iz1) OR wd1 OR NOT(wz1)) AND ((((NOT(iz1) AND NOT(nwt1) AND NOT(nwz1)) OR NOT(wd1)) AND ( NOT(nwt1) OR NOT(nwz1)) AND NOT(it1) AND (NOT(iz1) OR NOT(nwt1))) OR (NOT(nwt1) AND nwz1 AND NOT(wd1) AND wt1) OR ((NOT(iz1) AND NOT(nwz1)) AND NOT(wd1) AND NOT(wt1)))) OR NOT(s1)) AND (((NOT(nwd1) OR NOT(nwz1)) AND NOT(nwd1 XOR nwt1) AND wt1) OR (NOT(it1) AND NOT(nwd1) AND NOT(nwt1)) OR NOT(iz1) OR NOT(wz1)) AND (NOT(it1) OR (NOT(iz1) AND NOT(nwd1) AND NOT(nwz1)) OR NOT( wt1)) AND ((NOT(iz1) AND NOT(nwz1)) OR (NOT(it1) AND NOT(nwt1)) OR NOT( nwd1))); + END BLOCK lmaster1; + +--- Slave Latches + + lslave0 : BLOCK (ck0 AND NOT(nck0)) + BEGIN + s0 <= GUARDED NOT(m0); + END BLOCK lslave0; + lslave1 : BLOCK (ck1 AND NOT(nck1)) + BEGIN + s1 <= GUARDED NOT(m1); + END BLOCK lslave1; + +--- Output Mux + + lnqy0 : BLOCK ((ry0 AND s0) OR (ry1 AND s1)) + BEGIN + nqy <= GUARDED '0'; + END BLOCK lnqy0; + lnqy1 : BLOCK ((NOT(ry1) AND NOT(s0)) OR (NOT(ry0) AND NOT(s1))) + BEGIN + nqy <= GUARDED '1'; + END BLOCK lnqy1; + lnqx0 : BLOCK ((rx0 AND s0) OR (rx1 AND s1)) + BEGIN + nqx <= GUARDED '0'; + END BLOCK lnqx0; + lnqx1 : BLOCK ((NOT(rx1) AND NOT(s0)) OR (NOT(rx0) AND NOT(s1))) + BEGIN + nqx <= GUARDED '1'; + END BLOCK lnqx1; +END; diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nffct.ap b/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nffct.ap new file mode 100644 index 000000000..797d75e3e --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nffct.ap @@ -0,0 +1,564 @@ +V ALLIANCE : 6 +H sram_w2r2nffct,P,23/ 8/2024,100 +A 0,0,21000,5000 +R 0,100,ref_ref,ax20 +R 0,4100,ref_ref,ay10 +R 0,4600,ref_ref,ax10 +R 0,5100,ref_ref,ay20 +R 11500,2100,ref_ref,ry1 +R 9000,2100,ref_ref,rx1 +R 8000,1100,ref_ref,wt_0 +R 11000,2100,ref_ref,ay1 +R 10000,2100,ref_ref,ax1 +R 11000,3600,ref_ref,ay0 +R 10000,3100,ref_ref,ax0 +R 17300,2100,ref_ref,nwz1 +R 19200,2600,ref_ref,ck1i +R 1800,2600,ref_ref,ck0i +R 16800,600,ref_ref,wz_1 +R 14000,1100,ref_ref,wt_1 +R 5400,600,ref_ref,wz_0 +R 3700,2100,ref_ref,nwz0 +R 4200,2100,ref_ref,wz0 +R 16800,2100,ref_ref,wz1 +R 14600,1600,ref_ref,wt1 +R 15700,1600,ref_ref,at1 +R 5300,1600,ref_ref,at0 +R 13500,1600,ref_ref,nwd1 +R 14100,1600,ref_ref,nwt1 +R 13000,1600,ref_ref,wd1 +R 8000,1600,ref_ref,wd0 +R 7500,1600,ref_ref,nwd0 +R 6900,1600,ref_ref,nwt0 +R 6400,1600,ref_ref,wt0 +R 18000,1600,ref_ref,az1 +R 3000,1600,ref_ref,az0 +R 0,0,ref_ref,vss0 +R 21000,0,ref_ref,vss1 +R 0,5000,ref_ref,vdd0 +R 21000,5000,ref_ref,vdd1 +R 1800,1600,ref_ref,ck0 +R 2300,1600,ref_ref,nck0 +R 9500,1600,ref_ref,rx0 +R 12000,1600,ref_ref,ry0 +R 18700,1600,ref_ref,nck1 +R 19200,1600,ref_ref,ck1 +S 19200,600,19200,1100,200,nck1,DOWN,CALU1 +S 19200,3400,19200,4400,200,nck1,DOWN,CALU1 +S 18700,1100,18700,3400,200,nck1,DOWN,ALU1 +S 19200,1600,20400,1600,200,ck1,LEFT,CALU1 +S 20400,600,20400,4400,200,ck1,DOWN,CALU1 +S 17300,1100,17300,3900,200,nwz1,DOWN,CALU1 +S 18000,600,18000,1100,200,nwz1,DOWN,CALU1 +S 16200,600,16200,3400,200,nwt1,DOWN,CALU1 +S 14100,1600,14100,2100,200,nwt1,UP,CALU1 +S 13700,600,13700,1100,200,nwd1,UP,CALU1 +S 13500,1100,13500,2100,200,nwd1,UP,CALU1 +S 13800,3400,13800,4400,200,nwd1,DOWN,CALU1 +S 13100,2100,13100,3400,200,nwd1,UP,CALU1 +S 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14400,600,CONT_DIF_N,* +V 12600,600,CONT_DIF_N,* +V 12000,600,CONT_DIF_N,* +V 10200,600,CONT_DIF_N,* +V 9000,600,CONT_DIF_N,* +V 8400,600,CONT_DIF_N,* +V 7800,600,CONT_DIF_N,* +V 6600,600,CONT_DIF_N,* +V 6000,600,CONT_DIF_N,* +V 5400,600,CONT_DIF_N,* +V 4800,600,CONT_DIF_N,* +V 4200,600,CONT_DIF_N,* +V 3600,600,CONT_DIF_N,* +V 2400,600,CONT_DIF_N,* +V 1800,600,CONT_DIF_N,* +V 1200,600,CONT_DIF_N,* +V 600,600,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 600,4400,CONT_DIF_P,* +V 1000,0,CONT_BODY_P,* +V 1100,2600,CONT_POLY,* +V 1200,4400,CONT_DIF_P,* +V 1500,0,CONT_BODY_P,* +V 1800,2600,CONT_POLY,* +V 2000,0,CONT_BODY_P,* +V 2400,4400,CONT_DIF_P,* +V 2500,0,CONT_BODY_P,* +V 2900,2100,CONT_POLY,* +V 3000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3600,4400,CONT_DIF_P,* +V 3700,1600,CONT_POLY,* +V 4000,0,CONT_BODY_P,* +V 4200,3400,CONT_DIF_P,* +V 4500,0,CONT_BODY_P,* +V 4800,3400,CONT_DIF_P,* +V 5000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 6500,0,CONT_BODY_P,* +V 6600,4400,CONT_DIF_P,* +V 7000,0,CONT_BODY_P,* +V 7200,4400,CONT_DIF_P,* +V 7400,2600,CONT_POLY,* +V 7500,0,CONT_BODY_P,* +V 7800,4400,CONT_DIF_P,* +V 7900,2100,CONT_POLY,* +V 8000,0,CONT_BODY_P,* +V 8400,4400,CONT_DIF_P,* +V 8500,0,CONT_BODY_P,* +V 9000,0,CONT_BODY_P,* +V 9500,0,CONT_BODY_P,* +V 9600,4400,CONT_DIF_P,* +V 10000,0,CONT_BODY_P,* +V 10200,4400,CONT_DIF_P,* +V 10500,0,CONT_BODY_P,* +V 10800,4400,CONT_DIF_P,* +V 11000,0,CONT_BODY_P,* +V 11400,4400,CONT_DIF_P,* +V 11500,0,CONT_BODY_P,* +V 12000,0,CONT_BODY_P,* +V 12500,0,CONT_BODY_P,* +V 12600,4400,CONT_DIF_P,* +V 13000,0,CONT_BODY_P,* +V 13100,2100,CONT_POLY,* +V 13200,4400,CONT_DIF_P,* +V 13500,0,CONT_BODY_P,* +V 13600,2600,CONT_POLY,* +V 13800,4400,CONT_DIF_P,* +V 14000,0,CONT_BODY_P,* +V 14400,4400,CONT_DIF_P,* +V 14500,0,CONT_BODY_P,* +V 15000,0,CONT_BODY_P,* +V 15500,0,CONT_BODY_P,* +V 16000,0,CONT_BODY_P,* +V 16200,3400,CONT_DIF_P,* +V 16500,0,CONT_BODY_P,* +V 16800,3400,CONT_DIF_P,* +V 17000,0,CONT_BODY_P,* +V 17300,1600,CONT_POLY,* +V 17400,4400,CONT_DIF_P,* +V 17500,0,CONT_BODY_P,* +V 18000,0,CONT_BODY_P,* +V 18100,2100,CONT_POLY,* +V 18500,0,CONT_BODY_P,* +V 18600,4400,CONT_DIF_P,* +V 19000,0,CONT_BODY_P,* +V 19200,2600,CONT_POLY,* +V 19500,0,CONT_BODY_P,* +V 19800,4400,CONT_DIF_P,* +V 19900,2600,CONT_POLY,* +V 20000,0,CONT_BODY_P,* +V 20400,4400,CONT_DIF_P,* +V 20500,0,CONT_BODY_P,* +V 21000,0,CONT_BODY_P,* +EOF diff --git a/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nffct.vbe b/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nffct.vbe new file mode 100644 index 000000000..a345b1b8a --- /dev/null +++ b/ips/lsxram/coriolis/ips/lsxram/sram_w2r2nffct.vbe @@ -0,0 +1,67 @@ +ENTITY sram_w2r2nffct IS +PORT ( + ck0i : in BIT; + ck1i : in BIT; + ck0 : out BIT; + ck1 : out BIT; + nck0 : inout BIT; + nck1 : inout BIT; + + at0 : in BIT; + az0 : in BIT; + wt0 : out BIT; + wz0 : out BIT; + wd0 : out BIT; + nwt0 : inout BIT; + nwz0 : inout BIT; + nwd0 : inout BIT; + + at1 : in BIT; + az1 : in BIT; + wt1 : out BIT; + wz1 : out BIT; + wd1 : out BIT; + nwt1 : inout BIT; + nwz1 : inout BIT; + nwd1 : inout BIT; + + ax : in BIT; + ay : in BIT; + rx1 : out BIT; + rx0 : inout BIT; + ry1 : out BIT; + ry0 : inout BIT; + + vdd : in BIT; + vss : in BIT + ); +END sram_w2r2nffct ; + +ARCHITECTURE behaviour_data_flow OF sram_w2r2nffct IS +BEGIN + + nck0 <= NOT(ck0i); + ck0 <= NOT(nck0); + nck1 <= NOT(ck1i); + ck1 <= NOT(nck1); + + nwt0 <= NOT(at0); + wt0 <= NOT(nwt0); + nwz0 <= NOT(az0 AND nwt0); + wz0 <= NOT(nwz0); + nwd0 <= NOT(nwt0 AND nwz0); + wd0 <= NOT(nwd0); + + nwt1 <= NOT(at1); + wt1 <= NOT(nwt1); + nwz1 <= NOT(az1 AND nwt1); + wz1 <= NOT(nwz1); + nwd1 <= NOT(nwt1 AND nwz1); + wd1 <= NOT(nwd1); + + rx0 <= NOT(ax); + rx1 <= NOT(rx0); + ry0 <= NOT(ay); + ry1 <= NOT(ry0); + +END; diff --git a/ips/lsxram/pyproject.toml b/ips/lsxram/pyproject.toml new file mode 100644 index 000000000..aa373e3c1 --- /dev/null +++ b/ips/lsxram/pyproject.toml @@ -0,0 +1,34 @@ +[project] +name = "ip_lsxram" +version = "0.1.0" +description = "LSXRAM IP for Coriolis EDA" +authors = [ { name = "Coriolis EDA Contributers" } ] +requires-python = ">= 3.9" +dependencies = [] + +[tool.setuptools.packages.find] +where = ["."] +include = [ + "coriolis.ips.lsxram", + "coriolis.ips.lsxram.*" +] + +[tool.setuptools.package-data] +lsxram = [ + "*.c", + "*.ap", + "*.vbe" +] + +[build-system] +requires = [ + "setuptools", + "cibuildwheel", + "build", + "pdm-backend" +] +build-backend = "setuptools.build_meta" + +[tool.cibuildwheel] +build = "cp310-*" +skip = ["cp36-*", "cp37-*", "cp38-*", "cp39-*", "pp*"] diff --git a/katana/src/Manipulator.cpp b/katana/src/Manipulator.cpp index 8a08f4de5..5fb097566 100644 --- a/katana/src/Manipulator.cpp +++ b/katana/src/Manipulator.cpp @@ -40,7 +40,7 @@ namespace { class LvGCandidate { public: - struct Compare : public binary_function { + struct Compare { inline bool operator() ( const LvGCandidate& lhs, const LvGCandidate& rhs ) const; }; public: diff --git a/katana/src/NegociateWindow.cpp b/katana/src/NegociateWindow.cpp index a06c9a60f..c4fa4f585 100644 --- a/katana/src/NegociateWindow.cpp +++ b/katana/src/NegociateWindow.cpp @@ -421,7 +421,7 @@ namespace Katana { Interval span; autoSegment = autoSegment->getCanonical( span ); - bool created; + bool created = false; TrackElement* trackSegment = TrackSegment::create( autoSegment, insTrack, created ); if (not (flags & Flags::LoadingStage)) @@ -699,29 +699,39 @@ namespace Katana { event->process( _eventQueue, _eventHistory, _eventLoop ); count++; - // if (RoutingEvent::getProcesseds() == 49053) { + // if (RoutingEvent::getProcesseds() == 32512) { // UpdateSession::close(); - // Breakpoint::stop( 0, "After processing RoutingEvent 49053." ); + // Breakpoint::stop( 0, "After processing RoutingEvent 32511." ); // UpdateSession::open(); // } - //if (event->getSegment()->getNet()->getId() == 239546) { - // UpdateSession::close(); - // ostringstream message; - // message << "After processing an event from Net id:239546\n" << event; - // Breakpoint::stop( 0, message.str() ); - // UpdateSession::open(); - //} - - //if (count and not (count % 500)) { - // _pack( count, false ); - //} - - //if (RoutingEvent::getProcesseds() == 65092) { - // UpdateSession::close(); - // Breakpoint::stop( 0, "Overlap has happened" ); - // UpdateSession::open(); - //} + // if ( (event->getSegment()->getId() == 88365) + // or (event->getSegment()->getId() == 88368)) { + // UpdateSession::close(); + // ostringstream message; + // message << "After processing AutoSegment " << event->getSegment()->getId() + // << " (@event:" << (count-1) << ")"; + // Breakpoint::stop( 0, message.str() ); + // UpdateSession::open(); + // } + + // if (event->getSegment()->getNet()->getId() == 239546) { + // UpdateSession::close(); + // ostringstream message; + // message << "After processing an event from Net id:239546\n" << event; + // Breakpoint::stop( 0, message.str() ); + // UpdateSession::open(); + // } + + // if (count and not (count % 500)) { + // _pack( count, false ); + // } + + // if (RoutingEvent::getProcesseds() == 65092) { + // UpdateSession::close(); + // Breakpoint::stop( 0, "Overlap has happened" ); + // UpdateSession::open(); + // } if (RoutingEvent::getProcesseds() >= limit) setInterrupt( true ); } _statistics.setProcessedEventsCount( RoutingEvent::getProcesseds() ); @@ -762,6 +772,12 @@ namespace Katana { event->process( _eventQueue, _eventHistory, _eventLoop ); count++; if (RoutingEvent::getProcesseds() >= limit) setInterrupt( true ); + + // if (RoutingEvent::getProcesseds() == 55063) { + // UpdateSession::close(); + // Breakpoint::stop( 0, "Stoping after event 55063" ); + // UpdateSession::open(); + // } } _negociateRepair(); diff --git a/katana/src/PowerRails.cpp b/katana/src/PowerRails.cpp index a34b04183..60efd1467 100644 --- a/katana/src/PowerRails.cpp +++ b/katana/src/PowerRails.cpp @@ -317,7 +317,7 @@ namespace { bool operator() ( const Rail* lhs, const Rail* rhs ); }; - class RailMatch : public unary_function { + class RailMatch { public: inline RailMatch ( DbU::Unit axis, DbU::Unit width ); inline bool operator() ( const Rail* ); diff --git a/katana/src/RoutingEvent.cpp b/katana/src/RoutingEvent.cpp index c60cf688c..4a6b95649 100644 --- a/katana/src/RoutingEvent.cpp +++ b/katana/src/RoutingEvent.cpp @@ -557,7 +557,12 @@ namespace Katana { bool RoutingEvent::_rescheduleAsPref () { - if (_segment->getDirection() xor Session::getDirection(_segment->getLayer())) + cdebug_log(159,0) << "_rescheduleAsPref() " << _segment << endl; + cdebug_log(159,0) << "_segment->getDirection() " << _segment->getDirection() << endl; + cdebug_log(159,0) << "Session::getDirection() " << Session::getDirection(_segment->getLayer()) << endl; + if (_segment->getDirection() == Session::getDirection(_segment->getLayer())) + return false; + if (_dataNegociate and (_dataNegociate->getState() < DataNegociate::MaximumSlack)) return false; TrackSegmentNonPref* nonPref = dynamic_cast( _segment ); if (nonPref) nonPref->promoteToPref(); diff --git a/katana/src/Session.cpp b/katana/src/Session.cpp index 3c3fb300a..304b4d639 100644 --- a/katana/src/Session.cpp +++ b/katana/src/Session.cpp @@ -487,13 +487,13 @@ namespace Katana { void Session::_addMoveEvent ( TrackElement* segment, Track* track, DbU::Unit axis ) { - if (not segment->getTrack()) { - if (not segment->isNonPref() and not segment->isReduced()) { - cerr << Bug( " Katana::Session::addMoveEvent() : %s is not yet in a track." - , getString(segment).c_str() ) << endl; - } - } else { + if (segment->getTrack()) { _addRemoveEvent( segment ); + } else { + // if (not segment->isNonPref() and not segment->isReduced()) { + // cerr << Bug( " Katana::Session::addMoveEvent() : %s is not yet in a track." + // , getString(segment).c_str() ) << endl; + // } } _addInsertEvent( segment, track, axis, false ); } diff --git a/katana/src/TrackElement.cpp b/katana/src/TrackElement.cpp index 781614002..35ba68aa7 100644 --- a/katana/src/TrackElement.cpp +++ b/katana/src/TrackElement.cpp @@ -200,7 +200,8 @@ namespace Katana { void TrackElement::updatePPitch () { } void TrackElement::updateTrackSpan () { } void TrackElement::setAxis ( DbU::Unit, uint32_t flags ) { } - TrackElement* TrackElement::makeDogleg () { return NULL; } + TrackElement* TrackElement::promoteToPref () { return nullptr; } + TrackElement* TrackElement::makeDogleg () { return nullptr; } Flags TrackElement::makeDogleg ( Interval, TrackElement*&, TrackElement*&, Flags ) { return Flags::NoFlags; } TrackElement* TrackElement::makeDogleg ( Anabatic::GCell*, TrackElement*&, TrackElement*& ) { return NULL; } void TrackElement::_postDoglegs ( TrackElement*&, TrackElement*& ) { } diff --git a/katana/src/TrackSegment.cpp b/katana/src/TrackSegment.cpp index 2ab2357c5..a37a84183 100644 --- a/katana/src/TrackSegment.cpp +++ b/katana/src/TrackSegment.cpp @@ -138,7 +138,9 @@ namespace Katana { bool useNonPref = (segment->getDirection() xor Session::getDirection(segment->getLayer())); DbU::Unit defaultWireWidth = Session::getWireWidth( segment->base()->getLayer() ); - TrackElement* trackElement = Session::lookup( segment->base() ); + // TO_CHECK. + //TrackElement* trackElement = Session::lookup( segment->base() ); + TrackElement* trackElement = Session::lookup( segment ); if (not trackElement) { if (useNonPref) { trackElement = new TrackSegmentNonPref( segment ); @@ -482,11 +484,12 @@ namespace Katana { _sourceU = perpandicularSpan.getVMin(); _targetU = perpandicularSpan.getVMax(); + + updateTrackSpan(); } else _base->getCanonical( _sourceU, _targetU ); - if (isNonPref()) updateTrackSpan(); if (_track) { Track* wtrack = getTrack(); @@ -988,14 +991,32 @@ namespace Katana { } + + TrackElement* TrackSegment::promoteToPref () + { + TrackElement* perpandicular = nullptr; + TrackElement* parallel = nullptr; + + base()->setObserver( AutoSegment::Observable::TrackSegment, nullptr ); + DataNegociate* data = getDataNegociate(); + if (data and data->hasRoutingEvent()) + data->getRoutingEvent()->setDisabled( true ); + + base()->promoteToPref( Flags::NoFlags ); + _postDoglegs( perpandicular, parallel ); + + return perpandicular; + } + + TrackElement* TrackSegment::makeDogleg () { Anabatic::AutoContact* source = _base->getAutoSource(); Anabatic::AutoContact* target = _base->getAutoTarget(); Anabatic::GCell* gcell = _base->getAutoSource()->getGCell(); - TrackElement* dogleg = NULL; - TrackElement* parallel = NULL; + TrackElement* dogleg = nullptr; + TrackElement* parallel = nullptr; makeDogleg( gcell, dogleg, parallel ); if (dogleg) { @@ -1071,12 +1092,16 @@ namespace Katana { segments[i+1]->setFlags( TElemSourceDogleg|TElemTargetDogleg ); cdebug_log(159,0) << "Looking up new parallel: " << doglegs[i+2] << endl; - segments.push_back( Session::getNegociateWindow()->createTrackSegment(doglegs[i+2],0) ); - segments[i+2]->setFlags( TElemSourceDogleg ); - segments[i+2]->getDataNegociate()->resetStateCount(); - segments[i+2]->getDataNegociate()->setState( segments[i+0]->getDataNegociate()->getState() ); - - segments[i+0]->getDataNegociate()->setChildSegment( segments[i+2] ); + if (doglegs[i+2]) { + segments.push_back( Session::getNegociateWindow()->createTrackSegment(doglegs[i+2],0) ); + segments[i+2]->setFlags( TElemSourceDogleg ); + segments[i+2]->getDataNegociate()->resetStateCount(); + segments[i+2]->getDataNegociate()->setState( segments[i+0]->getDataNegociate()->getState() ); + + segments[i+0]->getDataNegociate()->setChildSegment( segments[i+2] ); + } else { + segments.push_back( nullptr ); + } perpandicular = segments[i+1]; parallel = segments[i+2]; @@ -1088,7 +1113,8 @@ namespace Katana { //if ( getGCell() != originalGCell ) swapTrack ( segments[2] ); for ( size_t i=0 ; ireschedule ( ((i%3==1) ? 0 : 1) ); + if (not segments[i]) continue; + segments[i]->reschedule( ((i%3==1) ? 0 : 1) ); const char* segPart = "Unknown"; switch ( i%3 ) { case 0: segPart = "original "; break; diff --git a/katana/src/TrackSegmentNonPref.cpp b/katana/src/TrackSegmentNonPref.cpp index 46191aa13..b95b85bbf 100644 --- a/katana/src/TrackSegmentNonPref.cpp +++ b/katana/src/TrackSegmentNonPref.cpp @@ -181,20 +181,4 @@ namespace Katana { } - void TrackSegmentNonPref::promoteToPref () - { - base()->setObserver( AutoSegment::Observable::TrackSegment, nullptr ); - bool created = false; - TrackElement* segment = TrackSegment::create( base(), nullptr, created ); - if (segment->isNonPref()) - throw Error( "TrackSegmentNonPref::promoteToPref(): Layer/direction incoherency for prefered,\n" - " From non-pref %s." - , getString(this).c_str() ); - DataNegociate* data = getDataNegociate(); - if (data and data->hasRoutingEvent()) - data->getRoutingEvent()->setDisabled( true ); - segment->reschedule( 0 ); - } - - } // Katana namespace. diff --git a/katana/src/katana/RoutingEvent.h b/katana/src/katana/RoutingEvent.h index c44ada0c0..bdd5cbf50 100644 --- a/katana/src/katana/RoutingEvent.h +++ b/katana/src/katana/RoutingEvent.h @@ -35,7 +35,6 @@ namespace Katana { using std::set; using std::vector; - using std::binary_function; using std::labs; using Hurricane::DbU; using Hurricane::Interval; @@ -55,7 +54,7 @@ namespace Katana { private: class Key { public: - class Compare : public binary_function { + class Compare { public: bool operator() ( const Key& lhs, const Key& rhs ) const; }; @@ -80,12 +79,12 @@ namespace Katana { public: // Sub-Class: "Compare". - class Compare : public binary_function { + class Compare { public: bool operator() ( const RoutingEvent* lhs, const RoutingEvent* rhs ) const; }; // Sub-Class: "CompareById". - class CompareById : public binary_function { + class CompareById { public: inline bool operator() ( const RoutingEvent* lhs, const RoutingEvent* rhs ) const; }; diff --git a/katana/src/katana/TrackElement.h b/katana/src/katana/TrackElement.h index 0e8ca03c3..0bdd5aeed 100644 --- a/katana/src/katana/TrackElement.h +++ b/katana/src/katana/TrackElement.h @@ -213,6 +213,7 @@ namespace Katana { virtual void addTrackCount ( int32_t ); virtual void incOverlapCost ( TrackCost& ) const; virtual void setAxis ( DbU::Unit, uint32_t flags=Anabatic::AutoSegment::SegAxisSet ); + virtual TrackElement* promoteToPref (); virtual TrackElement* makeDogleg (); inline bool makeDogleg ( Anabatic::GCell* ); virtual TrackElement* makeDogleg ( Anabatic::GCell*, TrackElement*& perpandicular, TrackElement*& parallel ); diff --git a/katana/src/katana/TrackSegment.h b/katana/src/katana/TrackSegment.h index d47cee651..df3427498 100644 --- a/katana/src/katana/TrackSegment.h +++ b/katana/src/katana/TrackSegment.h @@ -25,7 +25,6 @@ namespace Katana { using std::string; using std::map; using std::set; - using std::binary_function; using Hurricane::Record; using Hurricane::Interval; using Hurricane::DbU; @@ -48,7 +47,7 @@ namespace Katana { class TrackSegment : public TrackElement { public: - class CompareById : public binary_function { + class CompareById { public: inline bool operator() ( const TrackSegment* lhs, const TrackSegment* rhs ) const; }; @@ -140,6 +139,7 @@ namespace Katana { virtual void revalidate (); virtual void updatePPitch (); virtual void setAxis ( DbU::Unit, uint32_t flags ); + virtual TrackElement* promoteToPref (); virtual TrackElement* makeDogleg (); virtual TrackElement* makeDogleg ( Anabatic::GCell*, TrackElement*& perpandicular, TrackElement*& parallel ); virtual Flags makeDogleg ( Interval, TrackElement*& perpandicular, TrackElement*& parallel, Flags flags ); diff --git a/katana/src/katana/TrackSegmentNonPref.h b/katana/src/katana/TrackSegmentNonPref.h index 9350e6d70..07e084f09 100644 --- a/katana/src/katana/TrackSegmentNonPref.h +++ b/katana/src/katana/TrackSegmentNonPref.h @@ -25,7 +25,6 @@ namespace Katana { using std::string; using std::map; using std::set; - using std::binary_function; using Hurricane::Record; using Hurricane::Interval; using Hurricane::DbU; @@ -45,8 +44,6 @@ namespace Katana { friend class TrackSegment; public: typedef TrackSegment Super; - public: - void promoteToPref (); protected: TrackSegmentNonPref ( AutoSegment* ) ; virtual ~TrackSegmentNonPref (); diff --git a/katana/src/katana/TrackSegmentRegular.h b/katana/src/katana/TrackSegmentRegular.h index ac0e66cc8..c064f3b91 100644 --- a/katana/src/katana/TrackSegmentRegular.h +++ b/katana/src/katana/TrackSegmentRegular.h @@ -27,7 +27,6 @@ namespace Katana { using std::string; using std::map; using std::set; - using std::binary_function; using Hurricane::Record; using Hurricane::Interval; using Hurricane::DbU; diff --git a/katana/src/katana/TrackSegmentWide.h b/katana/src/katana/TrackSegmentWide.h index 930b2a627..c069bbb78 100644 --- a/katana/src/katana/TrackSegmentWide.h +++ b/katana/src/katana/TrackSegmentWide.h @@ -27,7 +27,6 @@ namespace Katana { using std::string; using std::map; using std::set; - using std::binary_function; using Hurricane::Record; using Hurricane::Interval; using Hurricane::DbU; diff --git a/meson.build b/meson.build index 46a2b58d5..f5c022eea 100644 --- a/meson.build +++ b/meson.build @@ -27,6 +27,30 @@ add_project_arguments( language: ['c','cpp'] ) +# Using libbfd for proper backtrace in Python bindings +if build_machine.system() == 'darwin' + binutils_prefix = '/opt/homebrew/opt/binutils' +else + binutils_prefix = '/usr' +endif + +libbfd = cpp.find_library('bfd', dirs: [binutils_prefix / 'lib'], required: true) +if libbfd.found() + add_project_arguments('-DHAVE_LIBBFD', language: ['c', 'cpp']) + + libiberty = cpp.find_library('iberty', dirs: [binutils_prefix / 'lib'], required: true) + zlib = cpp.find_library('z', required: true) + libsframe = cpp.find_library('sframe', dirs: [binutils_prefix / 'lib'], required: true) + + libbfd_deps = declare_dependency( + dependencies: [libbfd, libiberty, zlib, libsframe], + include_directories: include_directories(binutils_prefix / 'include'), + link_args: ['-Wl,-rpath,' + binutils_prefix / 'lib'], + ) +else + libbfd_deps = disabler() +endif + if get_option('check-database') add_project_arguments('-DCHECK_DATABASE') endif @@ -34,7 +58,7 @@ endif py = import('python').find_installation(pure:false) py_deps = dependency('python3', required: true) -py_mod_deps = declare_dependency(dependencies: py_deps, compile_args: '-D__PYTHON_MODULE__=1') +py_mod_deps = declare_dependency(dependencies: [py_deps, libbfd_deps], compile_args: '-D__PYTHON_MODULE__=1') qt = import('qt5', disabler: true) sed = find_program('sed', disabler: true) diff --git a/packaging/ubuntu24.04/gen_coriolis-eda_copyright.py b/packaging/ubuntu24.04/gen_coriolis-eda_copyright.py new file mode 100755 index 000000000..48ee6dc6b --- /dev/null +++ b/packaging/ubuntu24.04/gen_coriolis-eda_copyright.py @@ -0,0 +1,117 @@ +#!/usr/bin/env python3 + +from datetime import datetime +import sys +import os +from pathlib import Path +import re + +from jinja2 import Environment, FileSystemLoader + +# Arguments +pkg_path = sys.argv[1] +print(f"Search for pkg files in {pkg_path}") + +def search_pattern(path, pattern, in_name=True): + base_path = Path(path) + + results = [] + for file in base_path.rglob('*'): + if not file.is_file(): + continue + + if in_name: + search_in = file.name + else: + search_in = str(file.resolve) + + if pattern.search(search_in): + results.append(str(file).replace(path, '')) + + return results + +def search_binaries(path): + base_path = Path(path) + pattern = re.compile(r"^.*.so$", re.I) + + results = [] + for file in base_path.rglob('*'): + if file.is_file() and os.access(file, os.X_OK) and not pattern.search(file.name): + results.append(str(file).replace(path, '')) + + return results + +def search_doc(path, pattern): + base_path = Path(path) + + results = [] + for file in base_path.rglob('*'): + if file.is_dir() and pattern.search(str(file.absolute)): + results.append(f"{file}/*".replace(path, '')) + + return results + +template_params = { + "current_year": datetime.now().year +} + +## LefDef: C++ + +pattern = re.compile(r"^.*liblefdef.*.so$", re.I) +template_params["lefdef_so"] = search_pattern(pkg_path, pattern) + +## Flute: C++ + +pattern = re.compile(r"^.*libflute.*.so$", re.I) +template_params["flute_so"] = search_pattern(pkg_path, pattern) + +## Hurricane: C++ + +pattern = re.compile(r"^.*libhurricane.*.so$", re.I) +template_params["hurricane_so"] = search_pattern(pkg_path, pattern) + +## Coriolis: includes + +pattern = re.compile(r"^.*/include/.*$", re.I) +template_params["coriolis_includes"] = search_pattern(pkg_path, pattern, in_name=False) + +## Coriolis: C++ + +pattern = re.compile(r"^.*lib.*.so$", re.I) +coriolis_so = search_pattern(pkg_path, pattern) + +for so in template_params["lefdef_so"]: + coriolis_so.remove(so) + +for so in template_params["flute_so"]: + coriolis_so.remove(so) + +for so in template_params["hurricane_so"]: + coriolis_so.remove(so) + +template_params["coriolis_so"] = coriolis_so + +## Coriolis: Python bindings + +pattern = re.compile(r"^.*cpython.*.so$", re.I) +template_params["coriolis_bindings"] = search_pattern(pkg_path, pattern) + +## Coriolis: Doc + +pattern = re.compile(r"^.*/doc/coriolis/.*$", re.I) +template_params["coriolis_docs"] = search_doc(pkg_path, pattern) + +## Coriolis: bin + +template_params["coriolis_binaries"] = search_binaries(pkg_path) + +## Generate copyright file using template + +current_dir = os.path.dirname(os.path.abspath(__file__)) +jinja2_env = Environment(loader = FileSystemLoader(current_dir + '/templates')) + +copyright = jinja2_env.get_template('copyright.jinja2') +copyright_contents = copyright.render(template_params) + +with open(f"{pkg_path}/DEBIAN/copyright", 'w') as copyright_file: + copyright_file.write(copyright_contents) diff --git a/packaging/ubuntu24.04/pkg_python3-coriolis-eda.sh b/packaging/ubuntu24.04/pkg_python3-coriolis-eda.sh new file mode 100644 index 000000000..bb2ab38ef --- /dev/null +++ b/packaging/ubuntu24.04/pkg_python3-coriolis-eda.sh @@ -0,0 +1,83 @@ +#!/bin/bash + +# Arguments +SRC_DIR=$1 +if [[ -z "${SRC_DIR}" ]]; then + SRC_DIR=${PWD} +fi + +PREFIX=$2 +if [[ -z "${PREFIX}" ]]; then + PREFIX=${PWD}/${BUILD_TYPE} +fi + +OUT_DIR=$3 +if [[ -z "${OUT_DIR}" ]]; then + OUT_DIR=${PWD}/${BUILD_TYPE} +fi + +PKG_NAME=python3-coriolis-eda +PKG_VERSION=2.5.5 +PKG_REVISION=1 +PKG_MAINTAINER="Gabriel Rocherolle " + +PKG_ARCH="" +case $(uname -m) in + i386 | i686) PKG_ARCH="386" ;; + x86_64) PKG_ARCH="amd64" ;; + arm | aarch64) dpkg --print-architecture | grep -q "arm64" && PKG_ARCH="arm64" || PKG_ARCH="arm" ;; + *) echo "Unable to determine system architecture."; exit 1 ;; +esac + +DEB_PKG=${PKG_NAME}_${PKG_VERSION}-${PKG_REVISION}_${PKG_ARCH} + +PKG_PATH=${OUT_DIR}/pkgs/${DEB_PKG} + +mkdir -p ${PKG_PATH}/DEBIAN + +# PKG control +cat << EOF > "${PKG_PATH}/DEBIAN/control" +Package: ${PKG_NAME} +Version: ${PKG_VERSION} +Architecture: ${PKG_ARCH} +Section: universe/python +Maintainer: ${PKG_MAINTAINER} +Build-Depends: + build-essential, + ccache, + python3, + python3-pip, + python3-venv, + bison, + flex, + rapidjson-dev, + libboost-all-dev, + libeigen3-dev, + libxml2-dev, + libcairo2-dev, + qtbase5-dev, + libqt5svg5-dev, + libqwt-qt5-dev, + libbz2-dev, +Depends: python3:any, python3-pip, python3-venv +Recommends: doxygen, pelican, texlive-latex-recommanded +Provides: cyclop +Homepage: https://coriolis.lip6.fr +Description: Coriolis 2 EDA toolchain + Coriolis provides several tools to perform the layout of VLSI circuits. + Its main components are the Hurricane database, the Etesian placer and the Katana router, but other tools can use the Hurricane database and the parsers provided. +EOF + +# PKG contents +mkdir -p ${PKG_PATH}/usr +cp -r ${PREFIX}/* ${PKG_PATH}/usr + +# PKG copyright +echo "Generate copyright file" +python3 ${SRC_DIR}/packaging/ubuntu24.04/gen_coriolis-eda_copyright.py ${PKG_PATH} + +# Build PKG +DISTRIB_NAME=$(grep -e "^ID=" /etc/os-release | cut -d '=' -f 2) + +echo "Building ${PKG_NAME} for ${DISTRIB_NAME}"; +dpkg-deb --build --root-owner-group ${PKG_PATH} diff --git a/packaging/ubuntu24.04/templates/copyright.jinja2 b/packaging/ubuntu24.04/templates/copyright.jinja2 new file mode 100644 index 000000000..c1e8eb1cf --- /dev/null +++ b/packaging/ubuntu24.04/templates/copyright.jinja2 @@ -0,0 +1,39 @@ +Files: +{%- for file in lefdef_so %} + {{ file }} +{%- endfor %} +Copyright: Cadence Design Systems 2012-{{ current_year }} +License: Apache-2.0 + +Files: +{%- for file in flute_so %} + {{ file }} +{%- endfor %} +Copyright: Dr. Chris C. N. Chu 2004, Iowa State University +License: BSD-1-Clause + +Files: +{%- for file in hurricane_so %} + {{ file }} +{%- endfor %} +Copyright: Bull S.A. 2000-{{ current_year }} (now ATOS) +License: LGPL-2.0 + +Files: +{%- for file in coriolis_includes %} + {{ file }} +{%- endfor %} +{%- for file in coriolis_binaries %} + {{ file }} +{%- endfor %} +{%- for file in coriolis_bindings %} + {{ file }} +{%- endfor %} +{%- for file in coriolis_so %} + {{ file }} +{%- endfor %} +{%- for file in coriolis_docs %} + {{ file }} +{%- endfor %} +Copyright: Sorbonne Université 2000-{{ current_year }} (formerly UPMC) +License: GPL-2.0 diff --git a/pdks/Makefile b/pdks/Makefile new file mode 100644 index 000000000..e14bd5e7e --- /dev/null +++ b/pdks/Makefile @@ -0,0 +1,105 @@ +## PDKs wheel packages build Makefile + +### Environment variables and venv setup +PYTHON3 := python3 +DIST_PATH := ../dist +VENV_PATH := ../.venv + +venv := . ${VENV_PATH}/bin/activate; +pip_install := $(venv) pip3 install --upgrade +venv_python := $(venv) ${PYTHON3} + +PACKAGES := pip setuptools build wheel cibuildwheel + +venv_setup: + ${PYTHON3} -m venv ${VENV_PATH} + $(foreach pkg,$(PACKAGES),$(pip_install) $(pkg);) + + +### PDKs +PDKS := \ + common \ + symbolic \ + sg13g2_lsx \ + sky130_lsx \ + sg13g2_nsx2 \ + sky130_nsx2 \ + gf180mcu_nsx2 \ + scmos2m1u_nsx2 \ + sky130_vsc \ + cmos_sx \ + +PDKS_PATHS := \ + common \ + symbolic \ + symbolic/lsxlib/sg13g2_lsx \ + symbolic/lsxlib/sky130_lsx \ + symbolic/nsxlib2/sg13g2_nsx2 \ + symbolic/nsxlib2/sky130_nsx2 \ + symbolic/nsxlib2/gf180mcu_nsx2 \ + symbolic/nsxlib2/scmos2m1u_nsx2 \ + symbolic/vsclib/sky130_vsc \ + symbolic/sxlib/cmos_sx \ + +### Build targets +define map_path +$(1)_path = $(2) +endef + +indices := $(shell seq 1 $(words $(PDKS))) + +# Generate pdks paths +$(foreach i,$(indices),\ + $(eval $(call map_path,$(word $(i),$(PDKS)),$(word $(i),$(PDKS_PATHS))))) + + +define build_pdk +pdk_$(1): venv_setup + @echo "\n\t### Building PDK $(1)" 2>&1 | tee -a $($(1)_path)/$(1)_build.log + $(venv_python) -m build -w -o ${DIST_PATH} $($(1)_path) 2>&1 | tee -a $($(1)_path)/$(1)_build.log +endef + +# Generate build targets +$(foreach pdk,$(PDKS),$(eval $(call build_pdk,$(pdk)))) + +### All targets +all: $(foreach pdk,$(PDKS),pdk_$(pdk)) + @echo "### Finished building all PDK wheel packages" + +### Install target +define install_pdk +install_$(1): pdk_$(1) + $(venv) pip3 install --upgrade --force-reinstall ${DIST_PATH}/pdk_$(1)*.whl +endef + +$(foreach pdk,$(PDKS),$(eval $(call install_pdk,$(pdk)))) + +install: $(foreach pdk,$(PDKS),install_$(pdk)) + @echo "### Installed all PDK wheel packages" + +## Uninstall targets +define uninstall_pdk +uninstall_$(1): + $(venv) pip3 uninstall -y pdk_$(1) +endef + +$(foreach pdk,$(PDKS),$(eval $(call uninstall_pdk,$(pdk)))) + +uninstall: $(foreach pdk,$(PDKS),uninstall_$(pdk)) + @echo "### Uninstalled all PDK wheel packages" + +### Clean targets +define clean +clean_$(1): + @find $($(1)_path) -type f -name "*.log" -delete + @find $($(1)_path) -type d -name ".mesonpy*" -exec rm -rf {} \; + @find $($(1)_path) -type d -name "build*" -exec rm -rf {} \; + @find $($(1)_path) -type d -name "*.egg-info" -exec rm -rf {} \; +endef + +# Generate clean targets +$(foreach pdk,$(PDKS),$(eval $(call clean,$(pdk)))) + +clean: $(foreach pdk,$(PDKS),clean_$(pdk)) + @find . -type f -name "*.log" -delete + @echo "### Cleaned all PDK wheel packages" diff --git a/pdks/common/coriolis/__init__.py b/pdks/common/coriolis/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/pdks/common/coriolis/pnrcheck.py b/pdks/common/coriolis/pnrcheck.py new file mode 100644 index 000000000..e5ef018ef --- /dev/null +++ b/pdks/common/coriolis/pnrcheck.py @@ -0,0 +1,107 @@ + +from coriolis.designflow.copy import Copy +from coriolis.designflow.yosys import Yosys +from coriolis.designflow.blif2vst import Blif2Vst +from coriolis.designflow.cougar import Cougar +from coriolis.designflow.lvx import Lvx +from coriolis.designflow.druc import Druc +from coriolis.designflow.pnr import PnR +from s2r import S2R +from scr import SCR +from sta import STA +from coriolis.designflow.klayout import DRC +from coriolis.designflow.graal import Graal +from coriolis.designflow.dreal import Dreal +from coriolis.designflow.alias import Alias +from coriolis.designflow.clean import Clean +PnR.textMode = True + + +UseClockTree = 0x0001 +NoSynthesis = 0x0002 +NoGDS = 0x0004 +IsChip = 0x0008 +ChannelRoute = 0x0010 + + +def mkRuleSet ( callerGlobals, vlogDesignName, flags=0, extraRtlDepends=[], extrasClean=[] ): + from doDesign import scriptMain + + vhdlDesignName = vlogDesignName.lower() + if flags & IsChip: + routedName = 'chip_r' + else: + routedName = vhdlDesignName + if flags & UseClockTree: + routedName = vhdlDesignName + '_cts' + routedName = routedName + '_r' + + if not (flags & NoSynthesis): + ruleYosys = Yosys .mkRule( 'yosys', vlogDesignName+'.v' ) + ruleB2V = Blif2Vst.mkRule( 'b2v' , [ vhdlDesignName+'.vst' ] + , [ruleYosys] + , flags=0 ) + rtlDepends = [ ruleB2V ] + pnrTargets = [ routedName+'.ap' + , routedName+'.vst' + , routedName+'.spi' ] + else: + rtlDepends = [ vhdlDesignName+'.vst' ] + pnrTargets = [ routedName+'.ap' + , routedName+'.vst' + , routedName+'.spi' ] + rtlDepends += extraRtlDepends + scrTargets = [ routedName+'.ap' + , routedName+'.vst' + , routedName+'.spi' ] + scrFlag = SCR.Route | SCR.Place + if SCR.Iterations_value != 0: + scrFlag = scrFlag | SCR.Iterations + if SCR.RandSeed_value != 0: + scrFlag = scrFlag | SCR.RandSeed + if SCR.MaxRetry_value != 0: + scrFlag = scrFlag | SCR.MaxRetry + if flags & ChannelRoute: + rulePnR = SCR.mkRule( 'scr', scrTargets, rtlDepends, scrFlag ) + else: + rulePnR = PnR .mkRule( 'pnr', pnrTargets, rtlDepends, scriptMain ) + ruleCougar = Cougar.mkRule( 'cougar', routedName+'_r_ext.vst', [rulePnR], flags=Cougar.Verbose ) + if STA.flags & STA.Transistor: + cougarFlag = Cougar.Transistor | Cougar.Verbose + else: + cougarFlag = 0 + ruleCougarSpi = Cougar.mkRule( 'cougarSpi', routedName+'_ext.spi', [rulePnR], cougarFlag ) + staTargets = [ routedName+'_ext.cpath.rep' + , routedName+'_ext.cns' + , routedName+'_ext.cnv' + , routedName+'_ext.dtx' + , routedName+'_ext.rcx' + , routedName+'_ext.rep' + , routedName+'_ext.slack.rep' + , routedName+'_ext.stat' + , routedName+'_ext.stm' + , routedName+'_ext.sto' + , routedName+'_ext.str' ] + ruleSta = STA.mkRule( 'sta', staTargets, [ruleCougarSpi] ) + ruleLvx = Lvx .mkRule( 'lvx' + , [ rulePnR.file_target(1) + , ruleCougar.file_target(0) ] + , flags=Lvx.Flatten ) + ruleDruc = Druc .mkRule( 'druc' , [rulePnR], flags=0 ) + ruleLayout = Alias .mkRule( 'layout', [rulePnR] ) + ruleCgt = PnR .mkRule( 'cgt' ) + ruleGraal = Graal .mkRule( 'graal', rulePnR.file_target(0) ) + + if not (flags & NoGDS): + ruleGds = S2R .mkRule( 'gds', rulePnR.file_target(0).with_suffix('.gds'), rulePnR.file_target(0) + , flags=S2R.Verbose|S2R.NoReplaceBlackboxes|S2R.PinLayer|S2R.DeleteSubConnectors ) + ruleDRC = DRC .mkRule( 'drc' , ruleGds.file_target(0) ) + ruleDreal = Dreal .mkRule( 'dreal', ruleGds.file_target(0) ) + + ruleClean = Clean .mkRule( extrasClean ) + + for tag in [ 'Yosys', 'B2V', 'PnR', 'Cougar', 'Lvx', 'Druc', 'Cgt', 'CougarSpi', 'Sta', 'Scr' + , 'Layout', 'Gds', 'DRC', 'Graal', 'Dreal', 'Clean' ]: + rule = 'rule' + tag + if rule in locals(): + callerGlobals[ rule ] = locals()[ rule ] diff --git a/pdks/common/coriolis/s2r.py b/pdks/common/coriolis/s2r.py new file mode 100644 index 000000000..66f2bb9cf --- /dev/null +++ b/pdks/common/coriolis/s2r.py @@ -0,0 +1,67 @@ + +import os +import subprocess +from pathlib import Path +from doit.exceptions import TaskFailed +from coriolis.designflow.task import FlowTask, ShellEnv + + +class MissingTarget ( Exception ): pass + + +class S2R ( FlowTask ): + + NoDenotch = 0x0001 + DeleteNames = 0x0002 + DoBlackboxes = 0x0004 + NoReplaceBlackboxes = 0x0008 + Verbose = 0x0010 + PinLayer = 0x0020 + DeleteSubConnectors = 0x0030 + + @staticmethod + def mkRule ( rule, targets, depends=[], flags=0 ): + return S2R( rule, targets, depends, flags ) + + def __init__ ( self, rule, targets, depends, flags ): + super().__init__( rule, targets, depends ) + self.flags = flags + self.inputFile = self.file_depend(0) + self.outputFile = self.targets[0] + self.command = [ 's2r' ] + if flags & S2R.NoDenotch: self.command.append( '-t' ) + if flags & S2R.DeleteNames: self.command.append( '-c' ) + if flags & S2R.DoBlackboxes: self.command.append( '-1' ) + if flags & S2R.NoReplaceBlackboxes: self.command.append( '-r' ) + if flags & S2R.Verbose: self.command.append( '-v' ) + if flags & S2R.PinLayer: self.command.append( '-P' ) + if flags & S2R.DeleteSubConnectors: self.command.append( '-C' ) + self.command += [ self.inputFile.stem, self.outputFile.stem ] + self.addClean( self.targets ) + + def __repr__ ( self ): + return '<{}>'.format( ' '.join(self.command) ) + + def doTask ( self ): + from coriolis.CRL import AllianceFramework + from coriolis.helpers.io import ErrorMessage + + shellEnv = ShellEnv() + shellEnv[ 'RDS_OUT' ] = self.outputFile.suffix[1:] + shellEnv[ 'MBK_IN_PH' ] = self.inputFile .suffix[1:] + shellEnv.export() + state = subprocess.run( self.command ) + if state.returncode: + e = ErrorMessage( 1, 'S2R.doTask(): UNIX command failed ({}).' \ + .format( state.returncode )) + return TaskFailed( e ) + return self.checkTargets( 'S2R.doTask' ) + + def asDoitTask ( self ): + return { 'basename' : self.basename + , 'actions' : [ self.doTask ] + , 'doc' : 'Run {}.'.format( self ) + , 'targets' : self.targets + , 'file_dep' : self.file_dep + } + diff --git a/pdks/common/coriolis/scr.py b/pdks/common/coriolis/scr.py new file mode 100644 index 000000000..fdc2bf17b --- /dev/null +++ b/pdks/common/coriolis/scr.py @@ -0,0 +1,89 @@ + +import os +import subprocess +from pathlib import Path +from doit.exceptions import TaskFailed +from coriolis.designflow.task import FlowTask, ShellEnv + + +class MissingTarget ( Exception ): pass + + +class SCR ( FlowTask ): + + Route = 0x0001 + Place = 0x0002 + Iterations = 0x0004 + Iterations_value = 0 + SliceNumber = 0x0008 + Slice_value = 0 + SupplyNumber = 0x0010 + Supply_value = 0 + ChannelName = 0x0020 + Channel_str = 'c' + RandSeed = 0x0040 + RandSeed_value = 0 + MaxRetry = 0x0080 + MaxRetry_value = 0 + MBK_CATA_LIB = '.' + + @staticmethod + def mkRule ( rule, targets, depends=[], flags=0 ): + return SCR( rule, targets, depends, flags ) + + def __init__ ( self, rule, targets, depends, flags ): + super().__init__( rule, targets, depends ) + self.flags = flags + self.inputFile = self.file_depend(0) + self.outputFile = self.targets[0] + self.command = [ 'scr' ] + if flags & SCR.Route: self.command.append( '-r' ) + if flags & SCR.Place: self.command.append( '-p' ) + if flags & SCR.Iterations: self.command.extend( ['-i' ,str(SCR.Iterations_value)]) + if flags & SCR.SliceNumber : self.command.extend( ['-l' ,str(SCR.Slice_value)]) + if flags & SCR.SupplyNumber: self.command.extend( ['-a' ,str(SCR.Supply_value)]) + if flags & SCR.ChannelName: self.command.extend( ['-c' ,SCR.Channel_str ]) + if flags & SCR.RandSeed : self.command.extend( ['-s' ,str(SCR.RandSeed_value) ]) + if flags & SCR.MaxRetry : self.command.extend( ['-M' ,str(SCR.MaxRetry_value) ]) + self.command += [ '-o', self.outputFile.stem, self.inputFile.stem ] + self.commandvst = [ 'x2y' ] + self.commandvst.extend( ['vst','vst', self.inputFile.stem, self.outputFile.stem] ) + self.commandspi = [ 'x2y' ] + self.commandspi.extend( ['vst','spi', self.inputFile.stem, self.outputFile.stem] ) + self.addClean( self.targets ) + + def __repr__ ( self ): + return '<{}>'.format( ' '.join(self.command) ) + + def doTask ( self ): + from coriolis.CRL import AllianceFramework + from coriolis.helpers.io import ErrorMessage + shellEnv = ShellEnv() + shellEnv[ 'MBK_CATA_LIB' ] = self.MBK_CATA_LIB + shellEnv.export() + + state = subprocess.run( self.command ) + if state.returncode: + e = ErrorMessage( 1, 'SCR.doTask(): UNIX command failed ({}).' \ + .format( state.returncode )) + return TaskFailed( e ) + statevst = subprocess.run( self.commandvst ) + if statevst.returncode: + e = ErrorMessage( 1, 'SCR.doTask(): UNIX command failed ({}).' \ + .format( statevst.returncode )) + return TaskFailed( e ) + statespi = subprocess.run( self.commandspi ) + if statespi.returncode: + e = ErrorMessage( 1, 'SCR.doTask(): UNIX command failed ({}).' \ + .format( statespi.returncode )) + return TaskFailed( e ) + return self.checkTargets( 'SCR.doTask' ) + + def asDoitTask ( self ): + return { 'basename' : self.basename + , 'actions' : [ self.doTask ] + , 'doc' : 'Run {}.'.format( self ) + , 'targets' : self.targets + , 'file_dep' : self.file_dep + } + diff --git a/pdks/common/coriolis/sta.py b/pdks/common/coriolis/sta.py new file mode 100644 index 000000000..0abf45381 --- /dev/null +++ b/pdks/common/coriolis/sta.py @@ -0,0 +1,70 @@ +import os +import subprocess +from pathlib import Path +from doit.exceptions import TaskFailed +from coriolis.designflow.task import FlowTask, ShellEnv + +CalcCPathBin = Path(os.path.dirname(__file__)) / '..' / '..' / '..' / 'bin' / 'calcCPath.tcl' + + + +class MissingTarget ( Exception ): pass + +class STA ( FlowTask ): + flags = 0 + Transistor = 0x0001 + VddSupply = 1.8 + ClockName = 'm_clock' + SpiceType = 'hspice' + SpiceTrModel = 'scn6_deep.hsp' + MBK_CATA_LIB = '.' + VddName = 'vdd' + VssName = 'vss' + Temperature = 25.0 + OSDIdll = '' + + @staticmethod + def mkRule ( rule, targets, depends=[], flags=0 ): + return STA( rule, targets, depends, flags ) + + def __init__ ( self, rule, targets, depends, flags ): + super().__init__( rule, targets, depends ) + + self.flags = flags + self.inputFile = self.file_depend(0) + self.outputFile = self.targets[0] + if isinstance(self.SpiceTrModel, list): + model = ' '.join(self.SpiceTrModel) + else: + model = self.SpiceTrModel + self.command = [ 'avt_shell' , str(CalcCPathBin ), '-Target', self.inputFile.stem, '-SpiceModel', model, '-SpiceType', self.SpiceType, '-VddVoltage', str(self.VddSupply), '-ClockSignal', self.ClockName, '-VddName', self.VddName, '-VssName', self.VssName, '-Temperature', str(self.Temperature), '-OsdiDll', str(self.OSDIdll)] + self.addClean( self.targets ) + + def __repr__ ( self ): + return '<{}>'.format( ' '.join(self.command) ) + + def doTask ( self ): + from coriolis.CRL import AllianceFramework + from coriolis.helpers.io import ErrorMessage + + shellEnv = ShellEnv() + shellEnv[ 'MBK_CATA_LIB' ] = self.MBK_CATA_LIB + shellEnv[ 'MBK_OUT_LO' ] = 'spi' + shellEnv[ 'MBK_IN_PH' ] = 'ap' + shellEnv.export() + state = subprocess.run( self.command ) + # state = subprocess.run('pwd') + if state.returncode: + e = ErrorMessage( 1, 'STA.doTask(): UNIX command failed ({}).' \ + .format( state.returncode )) + return TaskFailed( e ) + return self.checkTargets( 'STA.doTask' ) + + def asDoitTask ( self ): + return { 'basename' : self.basename + , 'actions' : [ self.doTask ] + , 'doc' : 'Run {}.'.format( self ) + , 'targets' : self.targets + , 'file_dep' : self.file_dep + } + diff --git a/pdks/common/libs.tech/IHP-Open-PDK b/pdks/common/libs.tech/IHP-Open-PDK new file mode 160000 index 000000000..4c6508d03 --- /dev/null +++ b/pdks/common/libs.tech/IHP-Open-PDK @@ -0,0 +1 @@ +Subproject commit 4c6508d03a3078b21c737d04fae5dccec9aa590f diff --git a/pdks/common/libs.tech/globalfoundries-pdk-libs-gf180mcu_fd_pr b/pdks/common/libs.tech/globalfoundries-pdk-libs-gf180mcu_fd_pr new file mode 160000 index 000000000..9f992d5a9 --- /dev/null +++ b/pdks/common/libs.tech/globalfoundries-pdk-libs-gf180mcu_fd_pr @@ -0,0 +1 @@ +Subproject commit 9f992d5a9186d1f7820c58f039c484ad35b2edea diff --git a/pdks/common/libs.tech/skywater-pdk-libs-sky130_fd_pr b/pdks/common/libs.tech/skywater-pdk-libs-sky130_fd_pr new file mode 160000 index 000000000..f62031a1b --- /dev/null +++ b/pdks/common/libs.tech/skywater-pdk-libs-sky130_fd_pr @@ -0,0 +1 @@ +Subproject commit f62031a1be9aefe902d6d54cddd6f59b57627436 diff --git a/pdks/common/meson.build b/pdks/common/meson.build new file mode 100644 index 000000000..98b135339 --- /dev/null +++ b/pdks/common/meson.build @@ -0,0 +1,45 @@ + +project( + 'pdk_common', + version: '0.1.0', + meson_version: '>= 1.2.0', + default_options: ['warning_level=3'] +) + +python = import('python') +py = python.find_installation('python3') +py_deps = py.dependency() + +pdks_dir = py.get_install_dir() / 'pdks' / 'common' + +common_files = [ + 'coriolis/__init__.py', + 'coriolis/pnrcheck.py', + 'coriolis/s2r.py', + 'coriolis/scr.py', + 'coriolis/sta.py', +] + +py.install_sources( files(common_files), subdir: 'pdks/common' ) + +# gf180mcu +install_subdir( 'libs.tech/globalfoundries-pdk-libs-gf180mcu_fd_pr/cells' , install_dir: pdks_dir / 'gf180mcu' ) +install_subdir( 'libs.tech/globalfoundries-pdk-libs-gf180mcu_fd_pr/models' , install_dir: pdks_dir / 'gf180mcu' ) +install_subdir( 'libs.tech/globalfoundries-pdk-libs-gf180mcu_fd_pr/rules' , install_dir: pdks_dir / 'gf180mcu' ) +install_subdir( 'libs.tech/globalfoundries-pdk-libs-gf180mcu_fd_pr/tech' , install_dir: pdks_dir / 'gf180mcu' ) + +py.install_sources( 'libs.tech/globalfoundries-pdk-libs-gf180mcu_fd_pr/LICENSE', subdir: 'pdks/common/gf180mcu' ) + +# ihp-sg13g3 +install_subdir( 'libs.tech/IHP-Open-PDK/ihp-sg13g2/libs.qa' , install_dir: pdks_dir / 'ihp-sg13g2' ) +install_subdir( 'libs.tech/IHP-Open-PDK/ihp-sg13g2/libs.ref' , install_dir: pdks_dir / 'ihp-sg13g2' ) +install_subdir( 'libs.tech/IHP-Open-PDK/ihp-sg13g2/libs.tech' , install_dir: pdks_dir / 'ihp-sg13g2' ) + +py.install_sources( 'libs.tech/IHP-Open-PDK/LICENSE', subdir: 'pdks/common/ihp-sg13g2' ) + +# sky130 +install_subdir( 'libs.tech/skywater-pdk-libs-sky130_fd_pr/cells' , install_dir: pdks_dir / 'sky130' ) +install_subdir( 'libs.tech/skywater-pdk-libs-sky130_fd_pr/models' , install_dir: pdks_dir / 'sky130' ) +install_subdir( 'libs.tech/skywater-pdk-libs-sky130_fd_pr/tech' , install_dir: pdks_dir / 'sky130' ) + +py.install_sources( 'libs.tech/skywater-pdk-libs-sky130_fd_pr/LICENSE', subdir: 'pdks/common/sky130' ) diff --git a/pdks/common/pyproject.toml b/pdks/common/pyproject.toml new file mode 100644 index 000000000..f1a367ced --- /dev/null +++ b/pdks/common/pyproject.toml @@ -0,0 +1,25 @@ +[project] +name = "pdk_common" +version = "0.1.0" +description = "Common PDK for Coriolis EDA" +authors = [ { name = "Coriolis EDA Contributers" } ] +requires-python = ">= 3.8" + +[build-system] +requires = [ + "meson", + "meson-python", + "ninja", + "setuptools", + "cibuildwheel", + "build", + "pdm-backend" +] +build-backend = "mesonpy" + +[tool.meson] +build-dir = "build" + +[tool.cibuildwheel] +build = "cp310-*" +skip = ["cp36-*", "cp37-*", "pp*"] diff --git a/pdks/symbolic/__init__.py b/pdks/symbolic/__init__.py new file mode 100644 index 000000000..638ce048d --- /dev/null +++ b/pdks/symbolic/__init__.py @@ -0,0 +1,4 @@ +import os +from pathlib import Path + +path = Path( os.path.dirname(os.path.abspath(__file__)) ) diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/CATAL b/pdks/symbolic/hibikino/cells/padlib_25um/CATAL new file mode 100644 index 000000000..2dac959f8 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/CATAL @@ -0,0 +1,18 @@ +padreal G +padreal C +padline C +padall C +pck_sp C +pi_sp C +po_sp C +pvddck2_sp C +pvssck2_sp C +ck_buf C +i_buf C +pbuf_c C +pbuf_e C +supplyck_buf C +vssck_con C +vddck_con C +corner_sp C +cornar_sp C diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/ck_buf.ap b/pdks/symbolic/hibikino/cells/padlib_25um/ck_buf.ap new file mode 100644 index 000000000..c96f93736 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/ck_buf.ap @@ -0,0 +1,365 @@ +V ALLIANCE : 6 +H ck_buf,P,10/12/2016,100 +A -200,0,6200,15600 +C 6200,4300,6000,vdd,1,EAST,ALU1 +C 6200,9700,3200,vss,1,EAST,ALU1 +C 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+V 4700,13600,CONT_DIF_N,* +V 1100,7700,CONT_VIA,* +V 500,7700,CONT_VIA,* +V 5300,4000,CONT_VIA,* +V 4700,4000,CONT_VIA,* +V 5300,2800,CONT_VIA,* +V 4700,2800,CONT_VIA,* +V 500,2800,CONT_VIA,* +V 500,4000,CONT_VIA,* +V 1100,5600,CONT_VIA,* +V 500,5600,CONT_VIA,* +V 500,6800,CONT_VIA,* +V 1100,6800,CONT_VIA,* +V 2300,6800,CONT_VIA,* +V 2300,5600,CONT_VIA,* +V 3500,5600,CONT_VIA,* +V 3500,6800,CONT_VIA,* +V 4700,6800,CONT_VIA,* +V 5300,6800,CONT_VIA,* +V 4700,5600,CONT_VIA,* +V 5300,5600,CONT_VIA,* +V 4700,4800,CONT_VIA,* +V 5300,4800,CONT_VIA,* +V 500,7200,CONT_BODY_N,* +V 500,6400,CONT_BODY_N,* +V 500,6000,CONT_BODY_N,* +V 500,5200,CONT_BODY_N,* +V 500,4400,CONT_BODY_N,* +V 500,3600,CONT_BODY_N,* +V 500,3200,CONT_BODY_N,* +V 500,2400,CONT_BODY_N,* +V 5300,2400,CONT_BODY_N,* +V 5300,3200,CONT_BODY_N,* +V 5300,3600,CONT_BODY_N,* +V 5300,4400,CONT_BODY_N,* +V 5300,5200,CONT_BODY_N,* +V 5300,6000,CONT_BODY_N,* +V 5300,6400,CONT_BODY_N,* +V 5300,7200,CONT_BODY_N,* +V 4700,2400,CONT_DIF_P,* +V 4700,3200,CONT_DIF_P,* +V 4700,3600,CONT_DIF_P,* +V 4700,4400,CONT_DIF_P,* +V 4700,5200,CONT_DIF_P,* +V 4700,6000,CONT_DIF_P,* +V 4700,6400,CONT_DIF_P,* +V 4100,6800,CONT_DIF_P,* +V 4100,6400,CONT_DIF_P,* +V 4100,6000,CONT_DIF_P,* +V 4100,5600,CONT_DIF_P,* +V 4100,5200,CONT_DIF_P,* +V 4100,4800,CONT_DIF_P,* +V 4100,4400,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,3600,CONT_DIF_P,* +V 4100,3200,CONT_DIF_P,* +V 4100,2800,CONT_DIF_P,* +V 4100,2400,CONT_DIF_P,* +V 1100,4400,CONT_DIF_P,* +V 1100,3600,CONT_DIF_P,* +V 1100,3200,CONT_DIF_P,* +V 1700,2800,CONT_DIF_P,* +V 1700,3200,CONT_DIF_P,* +V 1700,3600,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 1700,4400,CONT_DIF_P,* +V 2300,3600,CONT_DIF_P,* +V 2300,3200,CONT_DIF_P,* +V 2900,2800,CONT_DIF_P,* +V 2900,3200,CONT_DIF_P,* +V 2900,3600,CONT_DIF_P,* +V 2900,4000,CONT_DIF_P,* +V 2900,4400,CONT_DIF_P,* +V 2300,4400,CONT_DIF_P,* +V 1100,7200,CONT_DIF_P,* +V 1100,6400,CONT_DIF_P,* +V 1100,6000,CONT_DIF_P,* +V 1700,7200,CONT_DIF_P,* +V 1700,6800,CONT_DIF_P,* +V 1700,6400,CONT_DIF_P,* +V 1700,6000,CONT_DIF_P,* +V 1700,5600,CONT_DIF_P,* +V 2300,7200,CONT_DIF_P,* +V 2300,6400,CONT_DIF_P,* +V 2300,6000,CONT_DIF_P,* +V 2900,7200,CONT_DIF_P,* +V 2900,6800,CONT_DIF_P,* +V 2900,6400,CONT_DIF_P,* +V 2900,6000,CONT_DIF_P,* +V 2900,5600,CONT_DIF_P,* +V 1100,5200,CONT_DIF_P,* +V 1700,5200,CONT_DIF_P,* +V 2300,5200,CONT_DIF_P,* +V 2900,5200,CONT_DIF_P,* +V 3500,7200,CONT_DIF_P,* +V 3500,6400,CONT_DIF_P,* +V 3500,6000,CONT_DIF_P,* +V 3500,5200,CONT_DIF_P,* +V 1100,4800,CONT_VIA,* +V 1100,4000,CONT_VIA,* +V 1100,2800,CONT_VIA,* +V 2300,2800,CONT_VIA,* +V 2300,4000,CONT_VIA,* +V 3500,2800,CONT_VIA,* +V 3500,4000,CONT_VIA,* +V 2300,4800,CONT_VIA,* +V 3500,4800,CONT_VIA,* +V 3500,4400,CONT_DIF_P,* +V 3500,3600,CONT_DIF_P,* +V 3500,3200,CONT_DIF_P,* +V 1100,8100,CONT_DIF_P,* +V 1700,8100,CONT_DIF_P,* +V 2300,8100,CONT_DIF_P,* +V 2900,8100,CONT_DIF_P,* +V 1100,8900,CONT_DIF_P,* +V 1700,8900,CONT_DIF_P,* +V 2300,8900,CONT_DIF_P,* +V 2900,8900,CONT_DIF_P,* +V 5300,8500,CONT_VIA,* +V 500,8500,CONT_VIA,* +V 500,9300,CONT_VIA,* +V 5300,9300,CONT_VIA,* +V 5300,8900,CONT_BODY_N,* +V 5300,9700,CONT_BODY_N,* +V 2900,8500,CONT_DIF_P,* +V 1700,8500,CONT_DIF_P,* +V 1700,9300,CONT_DIF_P,* +V 2900,9300,CONT_DIF_P,* +V 4100,9300,CONT_DIF_P,* +V 4100,8500,CONT_DIF_P,* +V 4100,8100,CONT_DIF_P,* +V 4100,8900,CONT_DIF_P,* +V 4700,8900,CONT_DIF_P,* +V 4700,8500,CONT_VIA,* +V 4700,9300,CONT_VIA,* +V 1100,8500,CONT_VIA,* +V 1100,9300,CONT_VIA,* +V 2300,9300,CONT_VIA,* +V 2300,8500,CONT_VIA,* +V 4100,1400,CONT_BODY_N,* +V 3500,1400,CONT_BODY_N,* +V 2900,1400,CONT_BODY_N,* +V 2300,1400,CONT_BODY_N,* +V 1100,1400,CONT_BODY_N,* +V 500,1400,CONT_BODY_N,* +V 4700,1400,CONT_BODY_N,* +V 5300,10400,CONT_BODY_N,* +V 4700,10400,CONT_BODY_N,* +V 500,10400,CONT_BODY_N,* +V 1100,10400,CONT_BODY_N,* +V 2300,10400,CONT_BODY_N,* +V 3500,10400,CONT_BODY_N,* +V 3500,8500,CONT_VIA,* +V 3500,9300,CONT_VIA,* +V 3500,8100,CONT_DIF_P,* +V 3500,8900,CONT_DIF_P,* +V 1100,9700,CONT_DIF_P,* +V 1700,9700,CONT_DIF_P,* +V 2300,9700,CONT_DIF_P,* +V 2900,9700,CONT_DIF_P,* +V 3500,9700,CONT_DIF_P,* +V 1100,2400,CONT_DIF_P,* +V 1700,2400,CONT_DIF_P,* +V 2300,2400,CONT_DIF_P,* +V 2900,2400,CONT_DIF_P,* +V 3500,2400,CONT_DIF_P,* +V 4100,7200,CONT_DIF_P,* +V 4700,7200,CONT_DIF_P,* +V 4700,11400,CONT_VIA,* +V 3500,14500,CONT_POLY,* +V 3500,1900,CONT_POLY,* +V 5300,11400,CONT_BODY_P,* +V 3500,7700,CONT_POLY,* +V 4100,9700,CONT_DIF_P,* +V 4700,9700,CONT_DIF_P,* +V 5300,1400,CONT_BODY_N,* +V 500,4800,CONT_VIA,* +V 4700,14500,CONT_POLY,* +V 4700,15000,CONT_BODY_P,* +V 2900,15000,CONT_BODY_P,* +V 500,15000,CONT_BODY_P,* +V 1100,15000,CONT_BODY_P,* +V 1700,15000,CONT_BODY_P,* +V 2300,14500,CONT_POLY,* +V 2900,7700,CONT_POLY,* +V 2300,1900,CONT_POLY,* +V 4700,7700,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/frame_temp_x1.ap b/pdks/symbolic/hibikino/cells/padlib_25um/frame_temp_x1.ap new file mode 100644 index 000000000..2d7c72eef --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/frame_temp_x1.ap @@ -0,0 +1,12 @@ +V ALLIANCE : 6 +H frame_temp_x1,P,16/11/2016,100 +A 0,0,6200,15600 +C 3100,15600,4000,pad,0,NORTH,ALU1 +C 3100,15600,4000,pad,1,NORTH,ALU2 +C 6200,4300,6000,vdd,1,EAST,ALU1 +C 6200,9700,3200,vss,1,EAST,ALU1 +C 0,9700,3200,vss,0,WEST,ALU1 +C 0,4300,6000,vdd,0,WEST,ALU1 +C 0,700,600,ck,0,WEST,ALU1 +C 6200,700,600,ck,1,EAST,ALU1 +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/frame_temp_x2.ap b/pdks/symbolic/hibikino/cells/padlib_25um/frame_temp_x2.ap new file mode 100644 index 000000000..45c2564d7 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/frame_temp_x2.ap @@ -0,0 +1,12 @@ +V ALLIANCE : 6 +H frame_temp_x2,P,16/11/2016,100 +A 0,0,12400,15600 +C 9300,15600,4000,pad,2,NORTH,ALU1 +C 9300,15600,4000,pad,3,NORTH,ALU2 +C 12400,700,600,ck,2,EAST,ALU1 +C 12400,9700,3200,vss,2,EAST,ALU1 +C 12400,4300,6000,vdd,2,EAST,ALU1 +C 0,9700,3200,vss,0,WEST,ALU1 +C 0,4300,6000,vdd,0,WEST,ALU1 +C 0,700,600,ck,0,WEST,ALU1 +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/i_buf.ap b/pdks/symbolic/hibikino/cells/padlib_25um/i_buf.ap new file mode 100644 index 000000000..4cc6ab415 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/i_buf.ap @@ -0,0 +1,378 @@ +V ALLIANCE : 6 +H i_buf,P,10/12/2016,100 +A -200,0,6200,15600 +C 6200,700,600,ck,1,EAST,ALU1 +C 6200,9700,3200,vss,1,EAST,ALU1 +C 6200,4300,6000,vdd,1,EAST,ALU1 +C 1700,0,200,t,1,SOUTH,ALU2 +C 1700,0,200,t,0,SOUTH,ALU1 +C -200,700,600,ck,0,WEST,ALU1 +C -200,4300,6000,vdd,0,WEST,ALU1 +C -200,9700,3200,vss,0,WEST,ALU1 +C 3000,15600,4000,pad,1,NORTH,ALU2 +C 3000,15600,4000,pad,0,NORTH,ALU1 +S 4400,7700,4700,7700,300,*,RIGHT,POLY +S 5000,1400,5000,10400,800,*,DOWN,ALU1 +S 2300,1400,5300,1400,200,*,LEFT,ALU1 +S 2300,1900,2900,1900,200,*,LEFT,ALU1 +S 2900,1900,2900,14500,200,*,UP,ALU1 +S 1400,2000,2400,2000,100,*,RIGHT,POLY +S 2300,2400,2300,10400,200,*,UP,ALU1 +S 1400,7700,2900,7700,100,*,RIGHT,POLY +S 2300,14500,2900,14500,200,*,LEFT,ALU1 +S 1400,14400,2400,14400,100,*,RIGHT,POLY +S 2300,11400,2300,14000,200,*,UP,ALU1 +S 3200,2000,3600,2000,100,*,RIGHT,POLY +S 2300,2200,2300,4500,300,*,UP,PDIF +S 2900,2200,2900,4500,300,*,DOWN,PDIF +S 2300,5100,2300,7400,300,*,DOWN,PDIF +S 2900,5100,2900,7400,300,*,DOWN,PDIF +S 2300,8000,2300,9800,300,*,DOWN,PDIF +S 2900,8000,2900,9800,300,*,DOWN,PDIF +S 3800,14500,3800,15600,800,*,UP,ALU1 +S 2300,11900,2300,14200,300,*,UP,NDIF +S 2900,11900,2900,14200,300,*,UP,NDIF +S 3200,14400,3500,14400,100,*,LEFT,POLY +S 500,15000,2900,15000,200,*,RIGHT,ALU1 +S 800,11400,800,15000,800,*,DOWN,ALU1 +S 500,11400,500,15000,200,*,UP,ALU1 +S 4700,15000,5300,15000,200,*,LEFT,ALU1 +S 5300,11400,5300,15000,200,*,UP,ALU1 +S 4700,11400,4700,14500,200,*,UP,ALU1 +S 4400,14500,4700,14500,300,*,RIGHT,POLY +S 1100,11400,1100,14400,200,*,UP,ALU1 +S 3500,2400,3500,7200,200,*,DOWN,ALU1 +S 3500,8100,3500,10400,200,*,UP,ALU1 +S 4400,1900,4400,7600,100,*,UP,PTRANS +S 4700,2100,4700,7400,300,*,DOWN,PDIF +S 4100,2100,4100,7400,300,*,UP,PDIF +S 500,1300,500,10400,300,*,UP,NTIE +S 1100,8000,1100,9800,300,*,UP,PDIF +S 400,1400,5400,1400,300,*,LEFT,NTIE +S 1400,7800,1400,10000,100,*,UP,PTRANS +S 2000,7800,2000,10000,100,*,UP,PTRANS +S 3500,8000,3500,9800,300,*,UP,PDIF +S 3200,7800,3200,10000,100,*,UP,PTRANS +S 4700,8000,4700,9800,300,*,UP,PDIF +S 4100,8000,4100,9800,300,*,UP,PDIF +S 4400,7800,4400,10000,100,*,UP,PTRANS +S 5300,1300,5300,10400,300,*,UP,NTIE +S 5300,1400,5300,7200,200,*,DOWN,ALU1 +S 4400,7600,4400,7800,100,*,UP,POLY +S 3200,7500,3200,7900,100,*,UP,POLY +S 2000,7500,2000,7900,100,*,UP,POLY +S 1400,7500,1400,7900,100,*,UP,POLY +S 3200,4900,3200,7600,100,*,UP,PTRANS +S 3500,5100,3500,7400,300,*,UP,PDIF +S 2000,4900,2000,7600,100,*,UP,PTRANS +S 1400,4900,1400,7600,100,*,UP,PTRANS +S 1100,5100,1100,7400,300,*,UP,PDIF +S 3500,7700,4100,7700,200,*,LEFT,ALU1 +S 5000,1400,5000,7200,800,*,DOWN,ALU1 +S 4700,1400,4700,7200,200,*,UP,ALU1 +S 4700,4300,6200,4300,6000,*,LEFT,ALU1 +S 400,15000,5400,15000,300,*,LEFT,PTIE +S 400,11400,5400,11400,300,*,LEFT,PTIE +S 500,11300,500,15100,300,*,DOWN,PTIE +S 5300,11300,5300,15100,300,*,DOWN,PTIE +S 3200,2000,3200,4700,100,*,UP,PTRANS +S 2000,2000,2000,4700,100,*,UP,PTRANS +S 1400,2000,1400,4700,100,*,UP,PTRANS +S 1100,2200,1100,4500,300,*,UP,PDIF +S 3500,2200,3500,4500,300,*,UP,PDIF +S 3500,1900,4100,1900,200,*,LEFT,ALU1 +S 4100,1900,4100,14500,200,*,DOWN,ALU1 +S 4400,11700,4400,14400,100,*,UP,NTRANS +S 4100,11900,4100,14200,300,*,UP,NDIF +S 4700,11900,4700,14200,300,*,UP,NDIF +S 3200,11700,3200,14400,100,*,UP,NTRANS +S 2000,11700,2000,14400,100,*,UP,NTRANS +S 1400,11700,1400,14400,100,*,UP,NTRANS +S 1100,11900,1100,14200,300,*,UP,NDIF +S 3500,11900,3500,14200,300,*,UP,NDIF +S 3500,14500,4100,14500,200,*,LEFT,ALU1 +S 5000,11400,5000,14000,800,*,DOWN,ALU1 +S 3500,11400,3500,14000,200,*,UP,ALU1 +S 4700,11400,5300,11400,200,*,LEFT,ALU1 +S 4400,14400,4400,14600,100,*,DOWN,POLY +S 400,10400,5400,10400,300,*,LEFT,NTIE +S 1100,1400,1100,10400,200,*,UP,ALU1 +S 800,1400,800,10400,800,*,DOWN,ALU1 +S 500,10400,1100,10400,200,*,RIGHT,ALU1 +S 500,1400,500,10400,200,*,UP,ALU1 +S 4700,8200,4700,10400,200,*,UP,ALU1 +S 5300,8200,5300,10400,200,*,DOWN,ALU1 +S 4700,10400,5300,10400,200,*,LEFT,ALU1 +S 500,5900,5300,5900,9200,*,RIGHT,ALU2 +S 2900,11100,2900,15300,5200,*,DOWN,PWELL +S 2900,1100,2900,10700,5200,*,UP,NWELL +S 4700,12700,6200,12700,2800,*,LEFT,ALU1 +S 500,13200,5300,13200,3800,*,RIGHT,ALU2 +S 6200,8200,6200,14000,200,*,UP,ALU1 +S 3200,7700,3500,7700,300,*,RIGHT,POLY +S 2300,700,6200,700,600,*,RIGHT,ALU1 +S 1700,0,1700,14000,200,*,UP,ALU1 +S 400,700,5300,700,600,*,RIGHT,ALU2 +S -200,8200,-200,14000,200,*,UP,ALU1 +S -200,12700,1100,12700,2800,*,LEFT,ALU1 +S -200,4300,1100,4300,6000,*,RIGHT,ALU1 +S -200,700,1100,700,600,*,RIGHT,ALU1 +S 3000,15600,3000,17500,4000,*,UP,ALU2 +S 3000,15600,3000,17500,4000,*,UP,ALU1 +V 4700,7700,CONT_POLY,* +V 2300,1900,CONT_POLY,* +V 2900,7700,CONT_POLY,* +V 2300,14500,CONT_POLY,* +V 1700,15000,CONT_BODY_P,* +V 1100,15000,CONT_BODY_P,* +V 500,15000,CONT_BODY_P,* +V 2900,15000,CONT_BODY_P,* +V 4700,15000,CONT_BODY_P,* +V 4700,14500,CONT_POLY,* +V 500,4800,CONT_VIA,* +V 5300,1400,CONT_BODY_N,* +V 4700,9700,CONT_DIF_P,* +V 4100,9700,CONT_DIF_P,* +V 3500,7700,CONT_POLY,* +V 5300,11400,CONT_BODY_P,* +V 3500,1900,CONT_POLY,* +V 3500,14500,CONT_POLY,* +V 4700,11400,CONT_VIA,* +V 4700,7200,CONT_DIF_P,* +V 4100,7200,CONT_DIF_P,* +V 3500,2400,CONT_DIF_P,* +V 2900,2400,CONT_DIF_P,* +V 2300,2400,CONT_DIF_P,* +V 1700,2400,CONT_DIF_P,* +V 1100,2400,CONT_DIF_P,* +V 3500,9700,CONT_DIF_P,* +V 2900,9700,CONT_DIF_P,* +V 2300,9700,CONT_DIF_P,* +V 1700,9700,CONT_DIF_P,* +V 1100,9700,CONT_DIF_P,* +V 3500,8900,CONT_DIF_P,* +V 3500,8100,CONT_DIF_P,* +V 3500,9300,CONT_VIA,* +V 3500,8500,CONT_VIA,* +V 3500,10400,CONT_BODY_N,* +V 2300,10400,CONT_BODY_N,* +V 1100,10400,CONT_BODY_N,* +V 500,10400,CONT_BODY_N,* +V 4700,10400,CONT_BODY_N,* +V 5300,10400,CONT_BODY_N,* +V 4700,1400,CONT_BODY_N,* +V 500,1400,CONT_BODY_N,* +V 1100,1400,CONT_BODY_N,* +V 2300,1400,CONT_BODY_N,* +V 2900,1400,CONT_BODY_N,* +V 3500,1400,CONT_BODY_N,* +V 4100,1400,CONT_BODY_N,* +V 2300,8500,CONT_VIA,* +V 2300,9300,CONT_VIA,* +V 1100,9300,CONT_VIA,* +V 1100,8500,CONT_VIA,* +V 4700,9300,CONT_VIA,* +V 4700,8500,CONT_VIA,* +V 4700,8900,CONT_DIF_P,* +V 4100,8900,CONT_DIF_P,* +V 4100,8100,CONT_DIF_P,* +V 4100,8500,CONT_DIF_P,* +V 4100,9300,CONT_DIF_P,* +V 2900,9300,CONT_DIF_P,* +V 1700,9300,CONT_DIF_P,* +V 1700,8500,CONT_DIF_P,* +V 2900,8500,CONT_DIF_P,* +V 5300,9700,CONT_BODY_N,* +V 5300,8900,CONT_BODY_N,* +V 5300,9300,CONT_VIA,* +V 500,9300,CONT_VIA,* +V 500,8500,CONT_VIA,* +V 5300,8500,CONT_VIA,* +V 2900,8900,CONT_DIF_P,* +V 2300,8900,CONT_DIF_P,* +V 1700,8900,CONT_DIF_P,* +V 1100,8900,CONT_DIF_P,* +V 2900,8100,CONT_DIF_P,* +V 2300,8100,CONT_DIF_P,* +V 1700,8100,CONT_DIF_P,* +V 1100,8100,CONT_DIF_P,* +V 3500,3200,CONT_DIF_P,* +V 3500,3600,CONT_DIF_P,* +V 3500,4400,CONT_DIF_P,* +V 3500,4800,CONT_VIA,* +V 2300,4800,CONT_VIA,* +V 3500,4000,CONT_VIA,* +V 3500,2800,CONT_VIA,* +V 2300,4000,CONT_VIA,* +V 2300,2800,CONT_VIA,* +V 1100,2800,CONT_VIA,* +V 1100,4000,CONT_VIA,* +V 1100,4800,CONT_VIA,* +V 3500,5200,CONT_DIF_P,* +V 3500,6000,CONT_DIF_P,* +V 3500,6400,CONT_DIF_P,* +V 3500,7200,CONT_DIF_P,* +V 2900,5200,CONT_DIF_P,* +V 2300,5200,CONT_DIF_P,* +V 1700,5200,CONT_DIF_P,* +V 1100,5200,CONT_DIF_P,* +V 2900,5600,CONT_DIF_P,* +V 2900,6000,CONT_DIF_P,* +V 2900,6400,CONT_DIF_P,* +V 2900,6800,CONT_DIF_P,* +V 2900,7200,CONT_DIF_P,* +V 2300,6000,CONT_DIF_P,* +V 2300,6400,CONT_DIF_P,* +V 2300,7200,CONT_DIF_P,* +V 1700,5600,CONT_DIF_P,* +V 1700,6000,CONT_DIF_P,* +V 1700,6400,CONT_DIF_P,* +V 1700,6800,CONT_DIF_P,* +V 1700,7200,CONT_DIF_P,* +V 1100,6000,CONT_DIF_P,* +V 1100,6400,CONT_DIF_P,* +V 1100,7200,CONT_DIF_P,* +V 2300,4400,CONT_DIF_P,* +V 2900,4400,CONT_DIF_P,* +V 2900,4000,CONT_DIF_P,* +V 2900,3600,CONT_DIF_P,* +V 2900,3200,CONT_DIF_P,* +V 2900,2800,CONT_DIF_P,* +V 2300,3200,CONT_DIF_P,* +V 2300,3600,CONT_DIF_P,* +V 1700,4400,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 1700,3600,CONT_DIF_P,* +V 1700,3200,CONT_DIF_P,* +V 1700,2800,CONT_DIF_P,* +V 1100,3200,CONT_DIF_P,* +V 1100,3600,CONT_DIF_P,* +V 1100,4400,CONT_DIF_P,* +V 4100,2400,CONT_DIF_P,* +V 4100,2800,CONT_DIF_P,* +V 4100,3200,CONT_DIF_P,* +V 4100,3600,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,4400,CONT_DIF_P,* +V 4100,4800,CONT_DIF_P,* +V 4100,5200,CONT_DIF_P,* +V 4100,5600,CONT_DIF_P,* +V 4100,6000,CONT_DIF_P,* +V 4100,6400,CONT_DIF_P,* +V 4100,6800,CONT_DIF_P,* +V 4700,6400,CONT_DIF_P,* +V 4700,6000,CONT_DIF_P,* +V 4700,5200,CONT_DIF_P,* +V 4700,4400,CONT_DIF_P,* +V 4700,3600,CONT_DIF_P,* +V 4700,3200,CONT_DIF_P,* +V 4700,2400,CONT_DIF_P,* +V 5300,7200,CONT_BODY_N,* +V 5300,6400,CONT_BODY_N,* +V 5300,6000,CONT_BODY_N,* +V 5300,5200,CONT_BODY_N,* +V 5300,4400,CONT_BODY_N,* +V 5300,3600,CONT_BODY_N,* +V 5300,3200,CONT_BODY_N,* +V 5300,2400,CONT_BODY_N,* +V 500,2400,CONT_BODY_N,* +V 500,3200,CONT_BODY_N,* +V 500,3600,CONT_BODY_N,* +V 500,4400,CONT_BODY_N,* +V 500,5200,CONT_BODY_N,* +V 500,6000,CONT_BODY_N,* +V 500,6400,CONT_BODY_N,* +V 500,7200,CONT_BODY_N,* +V 5300,4800,CONT_VIA,* +V 4700,4800,CONT_VIA,* +V 5300,5600,CONT_VIA,* +V 4700,5600,CONT_VIA,* +V 5300,6800,CONT_VIA,* +V 4700,6800,CONT_VIA,* +V 3500,6800,CONT_VIA,* +V 3500,5600,CONT_VIA,* +V 2300,5600,CONT_VIA,* +V 2300,6800,CONT_VIA,* +V 1100,6800,CONT_VIA,* +V 500,6800,CONT_VIA,* +V 500,5600,CONT_VIA,* +V 1100,5600,CONT_VIA,* +V 500,4000,CONT_VIA,* +V 500,2800,CONT_VIA,* +V 4700,2800,CONT_VIA,* +V 5300,2800,CONT_VIA,* +V 4700,4000,CONT_VIA,* +V 5300,4000,CONT_VIA,* +V 500,7700,CONT_VIA,* +V 1100,7700,CONT_VIA,* +V 4700,13600,CONT_DIF_N,* +V 4700,12800,CONT_DIF_N,* +V 4700,12000,CONT_DIF_N,* +V 4100,12000,CONT_DIF_N,* +V 4100,12400,CONT_DIF_N,* +V 4100,12800,CONT_DIF_N,* +V 4100,13200,CONT_DIF_N,* +V 4100,13600,CONT_DIF_N,* +V 4100,14000,CONT_DIF_N,* +V 3500,13600,CONT_DIF_N,* +V 3500,12800,CONT_DIF_N,* +V 3500,12000,CONT_DIF_N,* +V 2900,12000,CONT_DIF_N,* +V 2900,12400,CONT_DIF_N,* +V 2900,12800,CONT_DIF_N,* +V 2900,13200,CONT_DIF_N,* +V 2900,13600,CONT_DIF_N,* +V 2900,14000,CONT_DIF_N,* +V 2300,13600,CONT_DIF_N,* +V 2300,12800,CONT_DIF_N,* +V 2300,12000,CONT_DIF_N,* +V 1700,12000,CONT_DIF_N,* +V 1700,12400,CONT_DIF_N,* +V 1700,12800,CONT_DIF_N,* +V 1700,13200,CONT_DIF_N,* +V 1700,13600,CONT_DIF_N,* +V 1700,14000,CONT_DIF_N,* +V 1100,13600,CONT_DIF_N,* +V 1100,12800,CONT_DIF_N,* +V 1100,12000,CONT_DIF_N,* +V 5300,13600,CONT_BODY_P,* +V 5300,12800,CONT_BODY_P,* +V 5300,12000,CONT_BODY_P,* +V 500,12000,CONT_BODY_P,* +V 500,12800,CONT_BODY_P,* +V 500,13600,CONT_BODY_P,* +V 500,14400,CONT_BODY_P,* +V 500,11400,CONT_BODY_P,* +V 1100,11400,CONT_BODY_P,* +V 2300,11400,CONT_BODY_P,* +V 3500,11400,CONT_BODY_P,* +V 2300,15000,CONT_BODY_P,* +V 5300,15000,CONT_BODY_P,* +V 5300,12400,CONT_VIA,* +V 4700,12400,CONT_VIA,* +V 4700,13200,CONT_VIA,* +V 5300,13200,CONT_VIA,* +V 5300,14000,CONT_VIA,* +V 4700,14000,CONT_VIA,* +V 3500,12400,CONT_VIA,* +V 3500,13200,CONT_VIA,* +V 3500,14000,CONT_VIA,* +V 2300,14000,CONT_VIA,* +V 2300,13200,CONT_VIA,* +V 2300,12400,CONT_VIA,* +V 1100,12400,CONT_VIA,* +V 500,12400,CONT_VIA,* +V 500,13200,CONT_VIA,* +V 1100,13200,CONT_VIA,* +V 1100,14000,CONT_VIA,* +V 500,14000,CONT_VIA,* +V 2400,700,CONT_VIA,* +V 2900,700,CONT_VIA,* +V 3400,700,CONT_VIA,* +V 3900,700,CONT_VIA,* +V 4400,700,CONT_VIA,* +V 4900,700,CONT_VIA,* +V 1000,700,CONT_VIA,* +V 500,700,CONT_VIA,* +V 1700,0,CONT_VIA,* +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/padall.ap b/pdks/symbolic/hibikino/cells/padlib_25um/padall.ap new file mode 100644 index 000000000..dff1f2778 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/padall.ap @@ -0,0 +1,8 @@ +V ALLIANCE : 6 +H padall,P,25/11/2016,100 +A -64000,-128000,64000,0 +I 52800,-115200,padline,east,ROT_M +I -59200,-115200,padline,west,ROT_P +I -51200,-123200,padline,south,SYMXY +I -51200,-11200,padline,north,NOSYM +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/padline.ap b/pdks/symbolic/hibikino/cells/padlib_25um/padline.ap new file mode 100644 index 000000000..e82d453ee --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/padline.ap @@ -0,0 +1,20 @@ +V ALLIANCE : 6 +H padline,P,25/11/2016,100 +A 0,0,102400,6400 +I 0,0,padreal,pad0,NOSYM +I 6400,0,padreal,pad1,NOSYM +I 12800,0,padreal,pad2,NOSYM +I 19200,0,padreal,pad3,NOSYM +I 25600,0,padreal,pad4,NOSYM +I 32000,0,padreal,pad5,NOSYM +I 38400,0,padreal,pad6,NOSYM +I 44800,0,padreal,pad7,NOSYM +I 51200,0,padreal,pad8,NOSYM +I 57600,0,padreal,pad9,NOSYM +I 64000,0,padreal,pad10,NOSYM +I 70400,0,padreal,pad11,NOSYM +I 76800,0,padreal,pad12,NOSYM +I 83200,0,padreal,pad13,NOSYM +I 89600,0,padreal,pad14,NOSYM +I 96000,0,padreal,pad15,NOSYM +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/padreal.ap b/pdks/symbolic/hibikino/cells/padlib_25um/padreal.ap new file mode 100644 index 000000000..4d5ebf39a --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/padreal.ap @@ -0,0 +1,5 @@ +V ALLIANCE : 6 +H padreal,P,10/12/2016,100 +A -800,-1300,5600,5100 +B 2400,1900,4000,4000,CONT_VIA,* +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/padreal.gds b/pdks/symbolic/hibikino/cells/padlib_25um/padreal.gds new file mode 100644 index 000000000..7892f08ed Binary files /dev/null and b/pdks/symbolic/hibikino/cells/padlib_25um/padreal.gds differ diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pbuf_c.ap b/pdks/symbolic/hibikino/cells/padlib_25um/pbuf_c.ap new file mode 100644 index 000000000..d66e5750b --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pbuf_c.ap @@ -0,0 +1,365 @@ +V ALLIANCE : 6 +H pbuf_c,P,10/12/2016,100 +A 0,0,6400,15600 +C 0,700,600,ck,0,WEST,ALU1 +C 0,4300,6000,vdd,0,WEST,ALU1 +C 0,9700,3200,vss,0,WEST,ALU1 +C 400,0,200,i,1,SOUTH,ALU2 +C 400,0,200,i,0,SOUTH,ALU1 +C 6400,700,600,ck,1,EAST,ALU1 +C 6400,9700,3200,vss,1,EAST,ALU1 +C 6400,4300,6000,vdd,1,EAST,ALU1 +C 3200,15600,4000,pad,1,NORTH,ALU2 +C 3200,15600,4000,pad,0,NORTH,ALU1 +S 1400,2000,3600,2000,100,*,RIGHT,POLY +S 0,15000,1700,15000,200,*,RIGHT,ALU1 +S 500,11400,500,14400,200,*,UP,ALU1 +S 1100,11400,1100,14400,200,*,UP,ALU1 +S 2300,11400,2300,15000,200,*,UP,ALU1 +S 800,11400,800,14400,800,*,DOWN,ALU1 +S 3500,2400,3500,7200,200,*,DOWN,ALU1 +S 3500,8100,3500,10400,200,*,UP,ALU1 +S 0,10900,4100,10900,200,*,LEFT,ALU2 +S 4400,1900,4400,7600,100,*,UP,PTRANS +S 4700,2100,4700,7400,300,*,DOWN,PDIF +S 4100,2100,4100,7400,300,*,UP,PDIF +S 500,1300,500,10400,300,*,UP,NTIE +S 1100,8000,1100,9800,300,*,UP,PDIF +S 400,1400,5400,1400,300,*,LEFT,NTIE +S 1400,7800,1400,10000,100,*,UP,PTRANS +S 2000,7800,2000,10000,100,*,UP,PTRANS +S 2600,7800,2600,10000,100,*,UP,PTRANS +S 3500,8000,3500,9800,300,*,UP,PDIF +S 3200,7800,3200,10000,100,*,UP,PTRANS +S 4700,8000,4700,9800,300,*,UP,PDIF +S 4100,8000,4100,9800,300,*,UP,PDIF +S 4400,7800,4400,10000,100,*,UP,PTRANS +S 5300,1300,5300,10400,300,*,UP,NTIE +S 5300,1400,5300,7200,200,*,DOWN,ALU1 +S 4400,7600,4400,7800,100,*,UP,POLY +S 4600,7700,5800,7700,200,*,RIGHT,ALU1 +S 4400,7700,4600,7700,300,*,RIGHT,POLY +S 3200,7500,3200,7900,100,*,UP,POLY +S 2600,7500,2600,7900,100,*,UP,POLY +S 2000,7500,2000,7900,100,*,UP,POLY +S 1400,7500,1400,7900,100,*,UP,POLY +S 3200,4900,3200,7600,100,*,UP,PTRANS +S 3500,5100,3500,7400,300,*,UP,PDIF +S 2600,4900,2600,7600,100,*,DOWN,PTRANS +S 2000,4900,2000,7600,100,*,UP,PTRANS +S 1400,4900,1400,7600,100,*,UP,PTRANS +S 1100,5100,1100,7400,300,*,UP,PDIF +S 3500,7700,4100,7700,200,*,LEFT,ALU1 +S 500,1400,5300,1400,200,*,LEFT,ALU1 +S 5000,1400,5000,7200,800,*,DOWN,ALU1 +S 4700,1400,4700,7200,200,*,UP,ALU1 +S 0,4300,1100,4300,6000,*,RIGHT,ALU1 +S 400,15000,5400,15000,300,*,LEFT,PTIE +S 400,11400,5400,11400,300,*,LEFT,PTIE +S 500,11300,500,15100,300,*,DOWN,PTIE +S 5300,11300,5300,15100,300,*,DOWN,PTIE +S 3200,2000,3200,4700,100,*,UP,PTRANS +S 2600,2000,2600,4700,100,*,UP,PTRANS +S 2000,2000,2000,4700,100,*,UP,PTRANS +S 1400,2000,1400,4700,100,*,UP,PTRANS +S 1100,2200,1100,4500,300,*,UP,PDIF +S 3500,2200,3500,4500,300,*,UP,PDIF +S 3500,1900,4100,1900,200,*,LEFT,ALU1 +S 4100,1900,4100,14500,200,*,DOWN,ALU1 +S 4400,11700,4400,14400,100,*,UP,NTRANS +S 4100,11900,4100,14200,300,*,UP,NDIF +S 4700,11900,4700,14200,300,*,UP,NDIF +S 3200,11700,3200,14400,100,*,UP,NTRANS +S 2600,11700,2600,14400,100,*,UP,NTRANS +S 2000,11700,2000,14400,100,*,UP,NTRANS +S 1400,11700,1400,14400,100,*,UP,NTRANS +S 1100,11900,1100,14200,300,*,UP,NDIF +S 3500,11900,3500,14200,300,*,UP,NDIF +S 1400,14400,3500,14400,100,*,LEFT,POLY +S 3500,14500,4100,14500,200,*,LEFT,ALU1 +S 5300,11400,5300,14000,200,*,UP,ALU1 +S 4700,11400,4700,14000,200,*,UP,ALU1 +S 5000,11400,5000,14000,800,*,DOWN,ALU1 +S 3500,11400,3500,14000,200,*,UP,ALU1 +S 4700,11400,5300,11400,200,*,LEFT,ALU1 +S 2900,2400,2900,15700,200,*,UP,ALU1 +S 4600,14500,5800,14500,200,*,LEFT,ALU1 +S 4400,14500,4600,14500,300,*,RIGHT,POLY +S 4400,14400,4400,14600,100,*,DOWN,POLY +S 400,10400,5400,10400,300,*,LEFT,NTIE +S 1100,1400,1100,10400,200,*,UP,ALU1 +S 800,1400,800,10400,800,*,DOWN,ALU1 +S 500,10400,1100,10400,200,*,RIGHT,ALU1 +S 500,1400,500,10400,200,*,UP,ALU1 +S 2300,1400,2300,10400,200,*,UP,ALU1 +S 4700,8200,4700,10400,200,*,UP,ALU1 +S 5000,8200,5000,10400,800,*,DOWN,ALU1 +S 5300,8200,5300,10400,200,*,DOWN,ALU1 +S 4700,10400,5300,10400,200,*,LEFT,ALU1 +S 500,5900,5300,5900,9200,*,RIGHT,ALU2 +S 1700,2400,1700,15700,200,*,UP,ALU1 +S 2900,11100,2900,15300,5200,*,DOWN,PWELL +S 2900,1100,2900,10700,5200,*,UP,NWELL +S 500,13200,5300,13200,3800,*,RIGHT,ALU2 +S 3500,15000,5300,15000,200,*,LEFT,ALU1 +S 0,12700,1100,12700,2800,*,LEFT,ALU1 +S 0,8200,0,14000,200,*,UP,ALU1 +S 1400,7700,3200,7700,100,*,RIGHT,POLY +S 3200,7700,3500,7700,300,*,RIGHT,POLY +S 5800,700,5800,14500,200,*,DOWN,ALU2 +S 400,700,5800,700,200,*,LEFT,ALU2 +S 400,0,400,700,200,*,DOWN,ALU2 +S 3200,15600,3200,17500,4000,*,UP,ALU2 +S 3200,15600,3200,17500,4000,*,UP,ALU1 +S 4700,12700,6400,12700,2800,*,LEFT,ALU1 +S 6400,8200,6400,14000,200,*,UP,ALU1 +S 0,700,6400,700,600,*,RIGHT,ALU1 +S 4700,4300,6400,4300,6000,*,LEFT,ALU1 +V 500,4800,CONT_VIA,* +V 4100,10900,CONT_VIA,* +V 5300,1400,CONT_BODY_N,* +V 4700,9700,CONT_DIF_P,* +V 4100,9700,CONT_DIF_P,* +V 5800,7700,CONT_VIA,* +V 4600,7700,CONT_POLY,* +V 3500,7700,CONT_POLY,* +V 5300,11400,CONT_BODY_P,* +V 3500,1900,CONT_POLY,* +V 3500,14500,CONT_POLY,* +V 4700,11400,CONT_VIA,* +V 4600,14500,CONT_POLY,* +V 5800,14500,CONT_VIA,* +V 4700,7200,CONT_DIF_P,* +V 4100,7200,CONT_DIF_P,* +V 3500,2400,CONT_DIF_P,* +V 2900,2400,CONT_DIF_P,* +V 2300,2400,CONT_DIF_P,* +V 1700,2400,CONT_DIF_P,* +V 1100,2400,CONT_DIF_P,* +V 3500,9700,CONT_DIF_P,* +V 2900,9700,CONT_DIF_P,* +V 2300,9700,CONT_DIF_P,* +V 1700,9700,CONT_DIF_P,* +V 1100,9700,CONT_DIF_P,* +V 3500,8900,CONT_DIF_P,* +V 3500,8100,CONT_DIF_P,* +V 3500,9300,CONT_VIA,* +V 3500,8500,CONT_VIA,* +V 3500,10400,CONT_BODY_N,* +V 2300,10400,CONT_BODY_N,* +V 1100,10400,CONT_BODY_N,* +V 500,10400,CONT_BODY_N,* +V 4700,10400,CONT_BODY_N,* +V 5300,10400,CONT_BODY_N,* +V 4700,1400,CONT_BODY_N,* +V 500,1400,CONT_BODY_N,* +V 1100,1400,CONT_BODY_N,* +V 1700,1400,CONT_BODY_N,* +V 2300,1400,CONT_BODY_N,* +V 2900,1400,CONT_BODY_N,* +V 3500,1400,CONT_BODY_N,* +V 4100,1400,CONT_BODY_N,* +V 2300,8500,CONT_VIA,* +V 2300,9300,CONT_VIA,* +V 1100,9300,CONT_VIA,* +V 1100,8500,CONT_VIA,* +V 4700,9300,CONT_VIA,* +V 4700,8500,CONT_VIA,* +V 4700,8900,CONT_DIF_P,* +V 4100,8900,CONT_DIF_P,* +V 4100,8100,CONT_DIF_P,* +V 4100,8500,CONT_DIF_P,* +V 4100,9300,CONT_DIF_P,* +V 2900,9300,CONT_DIF_P,* +V 1700,9300,CONT_DIF_P,* +V 1700,8500,CONT_DIF_P,* +V 2900,8500,CONT_DIF_P,* +V 5300,9700,CONT_BODY_N,* +V 5300,8900,CONT_BODY_N,* +V 5300,9300,CONT_VIA,* +V 500,9300,CONT_VIA,* +V 500,8500,CONT_VIA,* +V 5300,8500,CONT_VIA,* +V 2900,8900,CONT_DIF_P,* +V 2300,8900,CONT_DIF_P,* +V 1700,8900,CONT_DIF_P,* +V 1100,8900,CONT_DIF_P,* +V 2900,8100,CONT_DIF_P,* +V 2300,8100,CONT_DIF_P,* +V 1700,8100,CONT_DIF_P,* +V 1100,8100,CONT_DIF_P,* +V 3500,3200,CONT_DIF_P,* +V 3500,3600,CONT_DIF_P,* +V 3500,4400,CONT_DIF_P,* +V 3500,4800,CONT_VIA,* +V 2300,4800,CONT_VIA,* +V 3500,4000,CONT_VIA,* +V 3500,2800,CONT_VIA,* +V 2300,4000,CONT_VIA,* +V 2300,2800,CONT_VIA,* +V 1100,2800,CONT_VIA,* +V 1100,4000,CONT_VIA,* +V 1100,4800,CONT_VIA,* +V 3500,5200,CONT_DIF_P,* +V 3500,6000,CONT_DIF_P,* +V 3500,6400,CONT_DIF_P,* +V 3500,7200,CONT_DIF_P,* +V 2900,5200,CONT_DIF_P,* +V 2300,5200,CONT_DIF_P,* +V 1700,5200,CONT_DIF_P,* +V 1100,5200,CONT_DIF_P,* +V 2900,5600,CONT_DIF_P,* +V 2900,6000,CONT_DIF_P,* +V 2900,6400,CONT_DIF_P,* +V 2900,6800,CONT_DIF_P,* +V 2900,7200,CONT_DIF_P,* +V 2300,6000,CONT_DIF_P,* +V 2300,6400,CONT_DIF_P,* +V 2300,7200,CONT_DIF_P,* +V 1700,5600,CONT_DIF_P,* +V 1700,6000,CONT_DIF_P,* +V 1700,6400,CONT_DIF_P,* +V 1700,6800,CONT_DIF_P,* +V 1700,7200,CONT_DIF_P,* +V 1100,6000,CONT_DIF_P,* +V 1100,6400,CONT_DIF_P,* +V 1100,7200,CONT_DIF_P,* +V 2300,4400,CONT_DIF_P,* +V 2900,4400,CONT_DIF_P,* +V 2900,4000,CONT_DIF_P,* +V 2900,3600,CONT_DIF_P,* +V 2900,3200,CONT_DIF_P,* +V 2900,2800,CONT_DIF_P,* +V 2300,3200,CONT_DIF_P,* +V 2300,3600,CONT_DIF_P,* +V 1700,4400,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 1700,3600,CONT_DIF_P,* +V 1700,3200,CONT_DIF_P,* +V 1700,2800,CONT_DIF_P,* +V 1100,3200,CONT_DIF_P,* +V 1100,3600,CONT_DIF_P,* +V 1100,4400,CONT_DIF_P,* +V 4100,2400,CONT_DIF_P,* +V 4100,2800,CONT_DIF_P,* +V 4100,3200,CONT_DIF_P,* +V 4100,3600,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,4400,CONT_DIF_P,* +V 4100,4800,CONT_DIF_P,* +V 4100,5200,CONT_DIF_P,* +V 4100,5600,CONT_DIF_P,* +V 4100,6000,CONT_DIF_P,* +V 4100,6400,CONT_DIF_P,* +V 4100,6800,CONT_DIF_P,* +V 4700,6400,CONT_DIF_P,* +V 4700,6000,CONT_DIF_P,* +V 4700,5200,CONT_DIF_P,* +V 4700,4400,CONT_DIF_P,* +V 4700,3600,CONT_DIF_P,* +V 4700,3200,CONT_DIF_P,* +V 4700,2400,CONT_DIF_P,* +V 5300,7200,CONT_BODY_N,* +V 5300,6400,CONT_BODY_N,* +V 5300,6000,CONT_BODY_N,* +V 5300,5200,CONT_BODY_N,* +V 5300,4400,CONT_BODY_N,* +V 5300,3600,CONT_BODY_N,* +V 5300,3200,CONT_BODY_N,* +V 5300,2400,CONT_BODY_N,* +V 500,2400,CONT_BODY_N,* +V 500,3200,CONT_BODY_N,* +V 500,3600,CONT_BODY_N,* +V 500,4400,CONT_BODY_N,* +V 500,5200,CONT_BODY_N,* +V 500,6000,CONT_BODY_N,* +V 500,6400,CONT_BODY_N,* +V 500,7200,CONT_BODY_N,* +V 5300,4800,CONT_VIA,* +V 4700,4800,CONT_VIA,* +V 5300,5600,CONT_VIA,* +V 4700,5600,CONT_VIA,* +V 5300,6800,CONT_VIA,* +V 4700,6800,CONT_VIA,* +V 3500,6800,CONT_VIA,* +V 3500,5600,CONT_VIA,* +V 2300,5600,CONT_VIA,* +V 2300,6800,CONT_VIA,* +V 1100,6800,CONT_VIA,* +V 500,6800,CONT_VIA,* +V 500,5600,CONT_VIA,* +V 1100,5600,CONT_VIA,* +V 500,4000,CONT_VIA,* +V 500,2800,CONT_VIA,* +V 4700,2800,CONT_VIA,* +V 5300,2800,CONT_VIA,* +V 4700,4000,CONT_VIA,* +V 5300,4000,CONT_VIA,* +V 500,7700,CONT_VIA,* +V 1100,7700,CONT_VIA,* +V 4700,13600,CONT_DIF_N,* +V 4700,12800,CONT_DIF_N,* +V 4700,12000,CONT_DIF_N,* +V 4100,12000,CONT_DIF_N,* +V 4100,12400,CONT_DIF_N,* +V 4100,12800,CONT_DIF_N,* +V 4100,13200,CONT_DIF_N,* +V 4100,13600,CONT_DIF_N,* +V 4100,14000,CONT_DIF_N,* +V 3500,13600,CONT_DIF_N,* +V 3500,12800,CONT_DIF_N,* +V 3500,12000,CONT_DIF_N,* +V 2900,12000,CONT_DIF_N,* +V 2900,12400,CONT_DIF_N,* +V 2900,12800,CONT_DIF_N,* +V 2900,13200,CONT_DIF_N,* +V 2900,13600,CONT_DIF_N,* +V 2900,14000,CONT_DIF_N,* +V 2300,13600,CONT_DIF_N,* +V 2300,12800,CONT_DIF_N,* +V 2300,12000,CONT_DIF_N,* +V 1700,12000,CONT_DIF_N,* +V 1700,12400,CONT_DIF_N,* +V 1700,12800,CONT_DIF_N,* +V 1700,13200,CONT_DIF_N,* +V 1700,13600,CONT_DIF_N,* +V 1700,14000,CONT_DIF_N,* +V 1100,13600,CONT_DIF_N,* +V 1100,12800,CONT_DIF_N,* +V 1100,12000,CONT_DIF_N,* +V 5300,13600,CONT_BODY_P,* +V 5300,12800,CONT_BODY_P,* +V 5300,12000,CONT_BODY_P,* +V 500,12000,CONT_BODY_P,* +V 500,12800,CONT_BODY_P,* +V 500,13600,CONT_BODY_P,* +V 500,14400,CONT_BODY_P,* +V 500,11400,CONT_BODY_P,* +V 1100,11400,CONT_BODY_P,* +V 2300,11400,CONT_BODY_P,* +V 3500,11400,CONT_BODY_P,* +V 2300,15000,CONT_BODY_P,* +V 5300,15000,CONT_BODY_P,* +V 3500,15000,CONT_BODY_P,* +V 4700,15000,CONT_VIA,* +V 4100,15000,CONT_VIA,* +V 5300,12400,CONT_VIA,* +V 4700,12400,CONT_VIA,* +V 4700,13200,CONT_VIA,* +V 5300,13200,CONT_VIA,* +V 5300,14000,CONT_VIA,* +V 4700,14000,CONT_VIA,* +V 3500,12400,CONT_VIA,* +V 3500,13200,CONT_VIA,* +V 3500,14000,CONT_VIA,* +V 2300,14000,CONT_VIA,* +V 2300,13200,CONT_VIA,* +V 2300,12400,CONT_VIA,* +V 1100,12400,CONT_VIA,* +V 500,12400,CONT_VIA,* +V 500,13200,CONT_VIA,* +V 1100,13200,CONT_VIA,* +V 1100,14000,CONT_VIA,* +V 500,14000,CONT_VIA,* +V 400,0,CONT_VIA,* +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pbuf_e.ap b/pdks/symbolic/hibikino/cells/padlib_25um/pbuf_e.ap new file mode 100644 index 000000000..f8cc0cd95 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pbuf_e.ap @@ -0,0 +1,361 @@ +V ALLIANCE : 6 +H pbuf_e,P,10/12/2016,100 +A -200,0,6200,15600 +C 6200,4300,6000,vdd,1,EAST,ALU1 +C 6200,9700,3200,vss,1,EAST,ALU1 +C 6200,700,600,ck,1,EAST,ALU1 +C -200,9700,3200,vss,0,WEST,ALU1 +C -200,4300,6000,vdd,0,WEST,ALU1 +C -200,700,600,ck,0,WEST,ALU1 +C 3000,15600,4000,pad,1,NORTH,ALU2 +C 3000,15600,4000,pad,0,NORTH,ALU1 +S 500,13200,5300,13200,3800,*,RIGHT,ALU2 +S 6200,8200,6200,14000,200,*,UP,ALU1 +S 4700,12700,6200,12700,2800,*,LEFT,ALU1 +S 2900,1100,2900,10700,5200,*,UP,NWELL +S 2900,11100,2900,15300,5200,*,DOWN,PWELL +S 4700,10400,5300,10400,200,*,LEFT,ALU1 +S 5300,8200,5300,10400,200,*,DOWN,ALU1 +S 5000,8200,5000,10400,800,*,DOWN,ALU1 +S 4700,8200,4700,10400,200,*,UP,ALU1 +S 2300,1400,2300,10400,200,*,UP,ALU1 +S 500,1400,500,10400,200,*,UP,ALU1 +S 500,10400,1100,10400,200,*,RIGHT,ALU1 +S 800,1400,800,10400,800,*,DOWN,ALU1 +S 1100,1400,1100,10400,200,*,UP,ALU1 +S 400,10400,5400,10400,300,*,LEFT,NTIE +S 4400,14400,4400,14600,100,*,DOWN,POLY +S 4400,14500,4600,14500,300,*,RIGHT,POLY +S 4600,14500,5800,14500,200,*,LEFT,ALU1 +S 4700,11400,5300,11400,200,*,LEFT,ALU1 +S 800,11400,800,15000,800,*,DOWN,ALU1 +S 1100,11400,1100,15000,200,*,UP,ALU1 +S 5000,11400,5000,14000,800,*,DOWN,ALU1 +S 4700,11400,4700,14000,200,*,UP,ALU1 +S 5300,11400,5300,14000,200,*,UP,ALU1 +S 1100,11900,1100,14200,300,*,UP,NDIF +S 1400,11700,1400,14400,100,*,UP,NTRANS +S 2000,11700,2000,14400,100,*,UP,NTRANS +S 2600,11700,2600,14400,100,*,UP,NTRANS +S 3200,11700,3200,14400,100,*,UP,NTRANS +S 4700,11900,4700,14200,300,*,UP,NDIF +S 4100,11900,4100,14200,300,*,UP,NDIF +S 4400,11700,4400,14400,100,*,UP,NTRANS +S 1100,2200,1100,4500,300,*,UP,PDIF +S 1400,2000,1400,4700,100,*,UP,PTRANS +S 2000,2000,2000,4700,100,*,UP,PTRANS +S 2600,2000,2600,4700,100,*,UP,PTRANS +S 3200,2000,3200,4700,100,*,UP,PTRANS +S 500,11400,500,15000,200,*,UP,ALU1 +S 5300,11300,5300,15100,300,*,DOWN,PTIE +S 500,11300,500,15100,300,*,DOWN,PTIE +S 400,11400,5400,11400,300,*,LEFT,PTIE +S 400,15000,5400,15000,300,*,LEFT,PTIE +S 4700,4300,6200,4300,6000,*,LEFT,ALU1 +S 4700,1400,4700,7200,200,*,UP,ALU1 +S 5000,1400,5000,7200,800,*,DOWN,ALU1 +S 1100,5100,1100,7400,300,*,UP,PDIF +S 1400,4900,1400,7600,100,*,UP,PTRANS +S 2000,4900,2000,7600,100,*,UP,PTRANS +S 2600,4900,2600,7600,100,*,DOWN,PTRANS +S 3200,4900,3200,7600,100,*,UP,PTRANS +S 1400,7500,1400,7900,100,*,UP,POLY +S 2000,7500,2000,7900,100,*,UP,POLY +S 2600,7500,2600,7900,100,*,UP,POLY +S 3200,7500,3200,7900,100,*,UP,POLY +S 4400,7700,4600,7700,300,*,RIGHT,POLY +S 4600,7700,5800,7700,200,*,RIGHT,ALU1 +S 4400,7600,4400,7800,100,*,UP,POLY +S 5300,1400,5300,7200,200,*,DOWN,ALU1 +S 5300,1300,5300,10400,300,*,UP,NTIE +S 4400,7800,4400,10000,100,*,UP,PTRANS +S 4100,8000,4100,9800,300,*,UP,PDIF +S 4700,8000,4700,9800,300,*,UP,PDIF +S 3200,7800,3200,10000,100,*,UP,PTRANS +S 2600,7800,2600,10000,100,*,UP,PTRANS +S 2000,7800,2000,10000,100,*,UP,PTRANS +S 1400,7800,1400,10000,100,*,UP,PTRANS +S 400,1400,5400,1400,300,*,LEFT,NTIE +S 1100,8000,1100,9800,300,*,UP,PDIF +S 500,1300,500,10400,300,*,UP,NTIE +S 3500,8100,3500,10400,200,*,UP,ALU1 +S 3500,2400,3500,7200,200,*,DOWN,ALU1 +S 5800,10900,6200,10900,200,*,LEFT,ALU2 +S 5800,800,5800,14500,200,*,DOWN,ALU2 +S 3800,7800,3800,10000,100,*,DOWN,PTRANS +S 3800,4900,3800,7600,100,*,DOWN,PTRANS +S 3800,2000,3800,4700,100,*,DOWN,PTRANS +S 4400,4900,4400,7600,100,*,UP,PTRANS +S 4400,2000,4400,4700,100,*,DOWN,PTRANS +S 3800,11700,3800,14400,100,*,DOWN,NTRANS +S 1400,2000,4400,2000,100,*,RIGHT,POLY +S 4700,5100,4700,7400,300,*,DOWN,PDIF +S 4700,2200,4700,4500,300,*,UP,PDIF +S 500,6400,5300,6400,8200,*,RIGHT,ALU2 +S 3500,1400,5300,1400,200,*,LEFT,ALU1 +S 500,1400,2300,1400,200,*,RIGHT,ALU1 +S 2900,800,5800,800,200,*,LEFT,ALU2 +S 2900,800,2900,1400,200,*,UP,ALU2 +S 2900,1400,2900,1800,200,*,UP,ALU1 +S 2900,1800,2900,2000,300,*,DOWN,POLY +S 1400,7700,4400,7700,100,*,RIGHT,POLY +S 3800,7500,3800,7900,100,*,UP,POLY +S 1400,14400,4400,14400,100,*,LEFT,POLY +S 4100,2400,4100,15000,200,*,DOWN,ALU1 +S 3500,11400,3500,14000,200,*,UP,ALU1 +S 2300,11400,2300,14000,200,*,UP,ALU1 +S 4100,15000,6200,15000,200,*,RIGHT,ALU1 +S 1700,14500,4100,14500,200,*,LEFT,ALU1 +S 2900,2400,2900,14500,200,*,UP,ALU1 +S 1700,2400,1700,14500,200,*,UP,ALU1 +S 500,15000,3500,15000,200,*,RIGHT,ALU1 +S -200,8200,-200,14000,200,*,UP,ALU1 +S -200,12700,1100,12700,2800,*,LEFT,ALU1 +S -200,4300,1100,4300,6000,*,RIGHT,ALU1 +S -200,700,6200,700,600,*,RIGHT,ALU1 +S 3000,15000,3000,17500,4000,*,UP,ALU2 +S 3000,15600,3000,17500,4000,*,UP,ALU1 +V 500,14000,CONT_VIA,* +V 1100,14000,CONT_VIA,* +V 1100,13200,CONT_VIA,* +V 500,13200,CONT_VIA,* +V 500,12400,CONT_VIA,* +V 1100,12400,CONT_VIA,* +V 2300,12400,CONT_VIA,* +V 2300,13200,CONT_VIA,* +V 2300,14000,CONT_VIA,* +V 3500,14000,CONT_VIA,* +V 3500,13200,CONT_VIA,* +V 3500,12400,CONT_VIA,* +V 4700,14000,CONT_VIA,* +V 5300,14000,CONT_VIA,* +V 5300,13200,CONT_VIA,* +V 4700,13200,CONT_VIA,* +V 4700,12400,CONT_VIA,* +V 5300,12400,CONT_VIA,* +V 3500,11400,CONT_BODY_P,* +V 2300,11400,CONT_BODY_P,* +V 1100,11400,CONT_BODY_P,* +V 500,11400,CONT_BODY_P,* +V 1100,15000,CONT_BODY_P,* +V 500,15000,CONT_BODY_P,* +V 500,14400,CONT_BODY_P,* +V 500,13600,CONT_BODY_P,* +V 500,12800,CONT_BODY_P,* +V 500,12000,CONT_BODY_P,* +V 5300,12000,CONT_BODY_P,* +V 5300,12800,CONT_BODY_P,* +V 5300,13600,CONT_BODY_P,* +V 1100,12000,CONT_DIF_N,* +V 1100,12800,CONT_DIF_N,* +V 1100,13600,CONT_DIF_N,* +V 1700,14000,CONT_DIF_N,* +V 1700,13600,CONT_DIF_N,* +V 1700,13200,CONT_DIF_N,* +V 1700,12800,CONT_DIF_N,* +V 1700,12400,CONT_DIF_N,* +V 1700,12000,CONT_DIF_N,* +V 2300,12000,CONT_DIF_N,* +V 2300,12800,CONT_DIF_N,* +V 2300,13600,CONT_DIF_N,* +V 2900,14000,CONT_DIF_N,* +V 2900,13600,CONT_DIF_N,* +V 2900,13200,CONT_DIF_N,* +V 2900,12800,CONT_DIF_N,* +V 2900,12400,CONT_DIF_N,* +V 2900,12000,CONT_DIF_N,* +V 3500,12000,CONT_DIF_N,* +V 3500,12800,CONT_DIF_N,* +V 3500,13600,CONT_DIF_N,* +V 4100,14000,CONT_DIF_N,* +V 4100,13600,CONT_DIF_N,* +V 4100,13200,CONT_DIF_N,* +V 4100,12800,CONT_DIF_N,* +V 4100,12400,CONT_DIF_N,* +V 4100,12000,CONT_DIF_N,* +V 4700,12000,CONT_DIF_N,* +V 4700,12800,CONT_DIF_N,* +V 4700,13600,CONT_DIF_N,* +V 1100,7700,CONT_VIA,* +V 500,7700,CONT_VIA,* +V 5300,4000,CONT_VIA,* +V 4700,4000,CONT_VIA,* +V 5300,2800,CONT_VIA,* +V 4700,2800,CONT_VIA,* +V 500,2800,CONT_VIA,* +V 500,4000,CONT_VIA,* +V 1100,5600,CONT_VIA,* +V 500,5600,CONT_VIA,* +V 500,6800,CONT_VIA,* +V 1100,6800,CONT_VIA,* +V 2300,6800,CONT_VIA,* +V 2300,5600,CONT_VIA,* +V 3500,5600,CONT_VIA,* +V 3500,6800,CONT_VIA,* +V 4700,6800,CONT_VIA,* +V 5300,6800,CONT_VIA,* +V 4700,5600,CONT_VIA,* +V 5300,5600,CONT_VIA,* +V 4700,4800,CONT_VIA,* +V 5300,4800,CONT_VIA,* +V 500,7200,CONT_BODY_N,* +V 500,6400,CONT_BODY_N,* +V 500,6000,CONT_BODY_N,* +V 500,5200,CONT_BODY_N,* +V 500,4400,CONT_BODY_N,* +V 500,3600,CONT_BODY_N,* +V 500,3200,CONT_BODY_N,* +V 500,2400,CONT_BODY_N,* +V 5300,2400,CONT_BODY_N,* +V 5300,3200,CONT_BODY_N,* +V 5300,3600,CONT_BODY_N,* +V 5300,4400,CONT_BODY_N,* +V 5300,5200,CONT_BODY_N,* +V 5300,6000,CONT_BODY_N,* +V 5300,6400,CONT_BODY_N,* +V 5300,7200,CONT_BODY_N,* +V 4700,2400,CONT_DIF_P,* +V 4700,3200,CONT_DIF_P,* +V 4700,3600,CONT_DIF_P,* +V 4700,4400,CONT_DIF_P,* +V 4700,5200,CONT_DIF_P,* +V 4700,6000,CONT_DIF_P,* +V 4700,6400,CONT_DIF_P,* +V 4100,6800,CONT_DIF_P,* +V 4100,6400,CONT_DIF_P,* +V 4100,6000,CONT_DIF_P,* +V 4100,5600,CONT_DIF_P,* +V 4100,5200,CONT_DIF_P,* +V 4100,4400,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,3600,CONT_DIF_P,* +V 4100,3200,CONT_DIF_P,* +V 4100,2800,CONT_DIF_P,* +V 4100,2400,CONT_DIF_P,* +V 1100,4400,CONT_DIF_P,* +V 1100,3600,CONT_DIF_P,* +V 1100,3200,CONT_DIF_P,* +V 1700,2800,CONT_DIF_P,* +V 1700,3200,CONT_DIF_P,* +V 1700,3600,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 1700,4400,CONT_DIF_P,* +V 2300,3600,CONT_DIF_P,* +V 2300,3200,CONT_DIF_P,* +V 2900,2800,CONT_DIF_P,* +V 2900,3200,CONT_DIF_P,* +V 2900,3600,CONT_DIF_P,* +V 2900,4000,CONT_DIF_P,* +V 2900,4400,CONT_DIF_P,* +V 2300,4400,CONT_DIF_P,* +V 1100,7200,CONT_DIF_P,* +V 1100,6400,CONT_DIF_P,* +V 1100,6000,CONT_DIF_P,* +V 1700,7200,CONT_DIF_P,* +V 1700,6800,CONT_DIF_P,* +V 1700,6400,CONT_DIF_P,* +V 1700,6000,CONT_DIF_P,* +V 1700,5600,CONT_DIF_P,* +V 2300,7200,CONT_DIF_P,* +V 2300,6400,CONT_DIF_P,* +V 2300,6000,CONT_DIF_P,* +V 2900,7200,CONT_DIF_P,* +V 2900,6800,CONT_DIF_P,* +V 2900,6400,CONT_DIF_P,* +V 2900,6000,CONT_DIF_P,* +V 2900,5600,CONT_DIF_P,* +V 1100,5200,CONT_DIF_P,* +V 1700,5200,CONT_DIF_P,* +V 2300,5200,CONT_DIF_P,* +V 2900,5200,CONT_DIF_P,* +V 3500,7200,CONT_DIF_P,* +V 3500,6400,CONT_DIF_P,* +V 3500,6000,CONT_DIF_P,* +V 3500,5200,CONT_DIF_P,* +V 1100,4800,CONT_VIA,* +V 1100,4000,CONT_VIA,* +V 1100,2800,CONT_VIA,* +V 2300,2800,CONT_VIA,* +V 2300,4000,CONT_VIA,* +V 3500,2800,CONT_VIA,* +V 3500,4000,CONT_VIA,* +V 2300,4800,CONT_VIA,* +V 3500,4800,CONT_VIA,* +V 3500,4400,CONT_DIF_P,* +V 3500,3600,CONT_DIF_P,* +V 3500,3200,CONT_DIF_P,* +V 1100,8100,CONT_DIF_P,* +V 1700,8100,CONT_DIF_P,* +V 2300,8100,CONT_DIF_P,* +V 2900,8100,CONT_DIF_P,* +V 1100,8900,CONT_DIF_P,* +V 1700,8900,CONT_DIF_P,* +V 2300,8900,CONT_DIF_P,* +V 2900,8900,CONT_DIF_P,* +V 5300,8500,CONT_VIA,* +V 500,8500,CONT_VIA,* +V 500,9300,CONT_VIA,* +V 5300,9300,CONT_VIA,* +V 5300,8900,CONT_BODY_N,* +V 5300,9700,CONT_BODY_N,* +V 2900,8500,CONT_DIF_P,* +V 1700,8500,CONT_DIF_P,* +V 1700,9300,CONT_DIF_P,* +V 2900,9300,CONT_DIF_P,* +V 4100,9300,CONT_DIF_P,* +V 4100,8500,CONT_DIF_P,* +V 4100,8100,CONT_DIF_P,* +V 4100,8900,CONT_DIF_P,* +V 4700,8900,CONT_DIF_P,* +V 4700,8500,CONT_VIA,* +V 4700,9300,CONT_VIA,* +V 1100,8500,CONT_VIA,* +V 1100,9300,CONT_VIA,* +V 2300,9300,CONT_VIA,* +V 2300,8500,CONT_VIA,* +V 4100,1400,CONT_BODY_N,* +V 3500,1400,CONT_BODY_N,* +V 2300,1400,CONT_BODY_N,* +V 1700,1400,CONT_BODY_N,* +V 1100,1400,CONT_BODY_N,* +V 500,1400,CONT_BODY_N,* +V 4700,1400,CONT_BODY_N,* +V 5300,10400,CONT_BODY_N,* +V 4700,10400,CONT_BODY_N,* +V 500,10400,CONT_BODY_N,* +V 1100,10400,CONT_BODY_N,* +V 2300,10400,CONT_BODY_N,* +V 3500,10400,CONT_BODY_N,* +V 3500,8500,CONT_VIA,* +V 3500,9300,CONT_VIA,* +V 3500,8100,CONT_DIF_P,* +V 3500,8900,CONT_DIF_P,* +V 1100,9700,CONT_DIF_P,* +V 1700,9700,CONT_DIF_P,* +V 2300,9700,CONT_DIF_P,* +V 2900,9700,CONT_DIF_P,* +V 3500,9700,CONT_DIF_P,* +V 1100,2400,CONT_DIF_P,* +V 1700,2400,CONT_DIF_P,* +V 2300,2400,CONT_DIF_P,* +V 2900,2400,CONT_DIF_P,* +V 3500,2400,CONT_DIF_P,* +V 4100,7200,CONT_DIF_P,* +V 4700,7200,CONT_DIF_P,* +V 5800,14500,CONT_VIA,* +V 4600,14500,CONT_POLY,* +V 4700,11400,CONT_VIA,* +V 5300,11400,CONT_BODY_P,* +V 4600,7700,CONT_POLY,* +V 5800,7700,CONT_VIA,* +V 4100,9700,CONT_DIF_P,* +V 4700,9700,CONT_DIF_P,* +V 5300,1400,CONT_BODY_N,* +V 2900,1400,CONT_VIA,* +V 2900,1800,CONT_POLY,* +V 3500,15000,CONT_BODY_P,* +V 2900,15000,CONT_BODY_P,* +V 2300,15000,CONT_BODY_P,* +V 1700,15000,CONT_BODY_P,* +V 500,4800,CONT_VIA,* +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pck_i.ap b/pdks/symbolic/hibikino/cells/padlib_25um/pck_i.ap new file mode 100644 index 000000000..3882bc815 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pck_i.ap @@ -0,0 +1,12 @@ +V ALLIANCE : 6 +H pck_i,P,16/11/2016,100 +A 0,0,6200,15600 +C 6200,700,600,ck,1,EAST,ALU1 +C 0,700,600,ck,0,WEST,ALU1 +C 0,4300,6000,vdd,0,WEST,ALU1 +C 0,9700,3200,vss,0,WEST,ALU1 +C 6200,9700,3200,vss,1,EAST,ALU1 +C 6200,4300,6000,vdd,1,EAST,ALU1 +C 3100,15600,4000,pad,1,NORTH,ALU2 +C 3100,15600,4000,pad,0,NORTH,ALU1 +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pck_sp.ap b/pdks/symbolic/hibikino/cells/padlib_25um/pck_sp.ap new file mode 100644 index 000000000..7584127cf --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pck_sp.ap @@ -0,0 +1,13 @@ +V ALLIANCE : 6 +H pck_sp,P,10/12/2016,100 +A 0,0,6400,15600 +C 3200,15600,4000,pad,2,NORTH,ALU1 +C 3200,15600,4000,pad,3,NORTH,ALU2 +C 6400,4300,6000,vdd,2,EAST,ALU1 +C 6400,9700,3200,vss,2,EAST,ALU1 +C 6400,700,600,ck,2,EAST,ALU1 +C 0,9700,3200,vss,0,WEST,ALU1 +C 0,4300,6000,vdd,0,WEST,ALU1 +C 0,700,600,ck,0,WEST,ALU1 +I 0,0,ck_buf,ck,NOSYM +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pck_sp.vbe b/pdks/symbolic/hibikino/cells/padlib_25um/pck_sp.vbe new file mode 100644 index 000000000..ea3ae4ff0 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pck_sp.vbe @@ -0,0 +1,40 @@ +-- VHDL data flow description generated from `pck_sp` +-- date : Thu Feb 23 17:05:59 1995 + + +-- Entity Declaration + +ENTITY pck_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_pad : NATURAL := 1326; -- cin_pad + CONSTANT tpll_pad : NATURAL := 1443; -- tpll_pad + CONSTANT rdown_pad : NATURAL := 58; -- rdown_pad + CONSTANT tphh_pad : NATURAL := 228; -- tphh_pad + CONSTANT rup_pad : NATURAL := 68 -- rup_pad + ); + PORT ( + pad : in BIT; -- pad + ck : out BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vsi + --vdde : in BIT; -- vdde + --vddi : in BIT; -- vddi + --vsse : in BIT; -- vsse + --vssi : in BIT -- vssi + ); +END pck_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pck_sp IS + +BEGIN + ASSERT ((((vdd and vdd)and not (vss)) and not (vss)) = '1') + REPORT "power supply is missing on pck_sp" + SEVERITY WARNING; + + +ck <= pad; +END; diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pi_sp.ap b/pdks/symbolic/hibikino/cells/padlib_25um/pi_sp.ap new file mode 100644 index 000000000..2f9971d2b --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pi_sp.ap @@ -0,0 +1,15 @@ +V ALLIANCE : 6 +H pi_sp,P,10/12/2016,100 +A 0,0,6400,15600 +C 3200,15600,4000,pad,2,NORTH,ALU1 +C 3200,15600,4000,pad,3,NORTH,ALU2 +C 6400,4300,6000,vdd,2,EAST,ALU1 +C 6400,9700,3200,vss,2,EAST,ALU1 +C 6400,700,600,ck,2,EAST,ALU1 +C 0,9700,3200,vss,0,WEST,ALU1 +C 0,4300,6000,vdd,0,WEST,ALU1 +C 0,700,600,ck,0,WEST,ALU1 +C 1700,0,200,t,1,SOUTH,ALU2 +C 1700,0,200,t,0,SOUTH,ALU1 +I 0,0,i_buf,ibuf,NOSYM +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pi_sp.vbe b/pdks/symbolic/hibikino/cells/padlib_25um/pi_sp.vbe new file mode 100644 index 000000000..22d6de503 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pi_sp.vbe @@ -0,0 +1,37 @@ +-- VHDL data flow description generated from `pi_sp` +-- date : Thu Feb 23 17:06:23 1995 + + +-- Entity Declaration + +ENTITY pi_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_pad : NATURAL := 654; -- cin_pad + CONSTANT tpll_pad : NATURAL := 1487; -- tpll_pad + CONSTANT rdown_pad : NATURAL := 234; -- rdown_pad + CONSTANT tphh_pad : NATURAL := 233; -- tphh_pad + CONSTANT rup_pad : NATURAL := 273 -- rup_pad + ); + PORT ( + pad : in BIT; -- pad + t : out BIT; -- t + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + ); +END pi_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pi_sp IS + +BEGIN + ASSERT ((((vdd and vdd) and not (vss)) and not (vss)) = '1') + REPORT "power supply is missing on pi_sp" + SEVERITY WARNING; + + +t <= pad; +END; diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/po_sp.ap b/pdks/symbolic/hibikino/cells/padlib_25um/po_sp.ap new file mode 100644 index 000000000..7fa0d827f --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/po_sp.ap @@ -0,0 +1,16 @@ +V ALLIANCE : 6 +H po_sp,P,10/12/2016,100 +A 0,0,12800,15600 +C 6800,0,200,i,2,SOUTH,ALU1 +C 6800,0,200,i,3,SOUTH,ALU2 +C 12800,700,600,ck,3,EAST,ALU1 +C 12800,9700,3200,vss,3,EAST,ALU1 +C 12800,4300,6000,vdd,3,EAST,ALU1 +C 9600,15600,4000,pad,2,NORTH,ALU1 +C 9600,15600,4000,pad,3,NORTH,ALU2 +C 0,700,600,ck,0,WEST,ALU1 +C 0,4300,6000,vdd,0,WEST,ALU1 +C 0,9700,3200,vss,0,WEST,ALU1 +I 6400,0,pbuf_c,con,NOSYM +I 0,0,pbuf_e,ext,NOSYM +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/po_sp.vbe b/pdks/symbolic/hibikino/cells/padlib_25um/po_sp.vbe new file mode 100644 index 000000000..df9f47c42 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/po_sp.vbe @@ -0,0 +1,41 @@ +-- VHDL data flow description generated from `po_sp` +-- date : Thu Feb 23 17:08:20 1995 + + +-- Entity Declaration + +ENTITY po_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_i : NATURAL := 191; -- cin_i + CONSTANT tpll_i : NATURAL := 2176; -- tpll_i + CONSTANT rdown_i : NATURAL := 15; -- rdown_i + CONSTANT tphh_i : NATURAL := 2032; -- tphh_i + CONSTANT rup_i : NATURAL := 16 -- rup_i + ); + PORT ( + i : in BIT; -- i + pad : out BIT; -- pad + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + -- vdde : in BIT; -- vdde + -- vddi : in BIT; -- vddi + -- vsse : in BIT; -- vsse + -- vssi : in BIT -- vssi + ); +END po_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF po_sp IS + +BEGIN + ASSERT ((((vdd and vdd) and not (vss)) and not (vss)) = '1') + REPORT "power supply is missing on po_sp" + SEVERITY WARNING; + + +pad <= i; +END; diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pvddck2_sp.ap b/pdks/symbolic/hibikino/cells/padlib_25um/pvddck2_sp.ap new file mode 100644 index 000000000..43d96a98b --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pvddck2_sp.ap @@ -0,0 +1,18 @@ +V ALLIANCE : 6 +H pvddck2_sp,P,10/12/2016,100 +A 0,0,12800,15600 +C 3200,15600,4000,vdd,9,NORTH,ALU1 +C 3200,15600,4000,vdd,10,NORTH,ALU2 +C 5900,0,200,cko,2,SOUTH,ALU1 +C 5900,0,200,cko,3,SOUTH,ALU2 +C 3200,0,2000,vdd,2,SOUTH,ALU1 +C 3200,0,2000,vdd,3,SOUTH,ALU2 +C 12800,700,600,ck,2,EAST,ALU1 +C 12800,9700,3200,vss,2,EAST,ALU1 +C 12800,4300,6000,vdd,6,EAST,ALU1 +C 0,9700,3200,vss,0,WEST,ALU1 +C 0,4300,6000,vdd,4,WEST,ALU1 +C 0,700,600,ck,0,WEST,ALU1 +I 6400,0,supplyck_buf,buf,NOSYM +I 0,0,vddck_con,con,NOSYM +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pvddck2_sp.vbe b/pdks/symbolic/hibikino/cells/padlib_25um/pvddck2_sp.vbe new file mode 100644 index 000000000..ea0afc33d --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pvddck2_sp.vbe @@ -0,0 +1,42 @@ +-- VHDL data flow description generated from `pvddck2_sp` +-- date : Thu Feb 23 17:11:45 1995 + + +-- Entity Declaration + +ENTITY pvddck2_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_ck : NATURAL := 127; -- cin_ck + CONSTANT tpll_ck : NATURAL := 1055; -- tpll_ck + CONSTANT rdown_ck : NATURAL := 126; -- rdown_ck + CONSTANT tphh_ck : NATURAL := 963; -- tphh_ck + CONSTANT rup_ck : NATURAL := 183 -- rup_ck + ); + PORT ( + cko : out WOR_BIT BUS; -- cko + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + -- vdde : in BIT; -- vdde + -- vddi : in BIT; -- vddi + -- vsse : in BIT; -- vsse + -- vssi : in BIT -- vssi + ); +END pvddck2_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvddck2_sp IS + +BEGIN + ASSERT ((((not (vss) and not (vss)) and vdd) and vdd) = '1') + REPORT "power supply is missing on pvddck2_sp" + SEVERITY WARNING; + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; +END; diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pvddssck_sp.vbe b/pdks/symbolic/hibikino/cells/padlib_25um/pvddssck_sp.vbe new file mode 100644 index 000000000..1ad2b08e1 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pvddssck_sp.vbe @@ -0,0 +1,42 @@ +-- VHDL data flow description generated from `pvddssck_sp` +-- date : Thu Feb 23 17:11:45 1995 + + +-- Entity Declaration + +ENTITY pvddssck_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_ck : NATURAL := 127; -- cin_ck + CONSTANT tpll_ck : NATURAL := 1055; -- tpll_ck + CONSTANT rdown_ck : NATURAL := 126; -- rdown_ck + CONSTANT tphh_ck : NATURAL := 963; -- tphh_ck + CONSTANT rup_ck : NATURAL := 183 -- rup_ck + ); + PORT ( + cko : out WOR_BIT BUS; -- cko + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + -- vdde : in BIT; -- vdde + -- vddi : in BIT; -- vddi + -- vsse : in BIT; -- vsse + -- vssi : in BIT -- vssi + ); +END pvddssck_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvddssck_sp IS + +BEGIN + ASSERT ((((not (vss) and not (vss)) and vdd) and vdd) = '1') + REPORT "power supply is missing on pvddssck_sp" + SEVERITY WARNING; + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; +END; diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pvssck2_sp.ap b/pdks/symbolic/hibikino/cells/padlib_25um/pvssck2_sp.ap new file mode 100644 index 000000000..40bf8b229 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pvssck2_sp.ap @@ -0,0 +1,18 @@ +V ALLIANCE : 6 +H pvssck2_sp,P,10/12/2016,100 +A 0,0,12800,15600 +C 5900,0,200,cko,4,SOUTH,ALU2 +C 5900,0,200,cko,3,SOUTH,ALU1 +C 3200,0,2000,vss,2,SOUTH,ALU1 +C 3200,0,2000,vss,3,SOUTH,ALU2 +C 3200,15600,4000,vss,14,NORTH,ALU1 +C 3200,15600,4000,vss,13,NORTH,ALU2 +C 12800,700,600,ck,2,EAST,ALU1 +C 12800,9700,3200,vss,6,EAST,ALU1 +C 12800,4300,6000,vdd,2,EAST,ALU1 +C 0,9700,3200,vss,4,WEST,ALU1 +C 0,4300,6000,vdd,0,WEST,ALU1 +C 0,700,600,ck,0,WEST,ALU1 +I 6400,0,supplyck_buf,buf,NOSYM +I 0,0,vssck_con,con,NOSYM +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/pvssck2_sp.vbe b/pdks/symbolic/hibikino/cells/padlib_25um/pvssck2_sp.vbe new file mode 100644 index 000000000..1aadc0998 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/pvssck2_sp.vbe @@ -0,0 +1,42 @@ +-- VHDL data flow description generated from `pvssck2_sp` +-- date : Thu Feb 23 17:11:45 1995 + + +-- Entity Declaration + +ENTITY pvssck2_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_ck : NATURAL := 127; -- cin_ck + CONSTANT tpll_ck : NATURAL := 1055; -- tpll_ck + CONSTANT rdown_ck : NATURAL := 126; -- rdown_ck + CONSTANT tphh_ck : NATURAL := 963; -- tphh_ck + CONSTANT rup_ck : NATURAL := 183 -- rup_ck + ); + PORT ( + cko : out WOR_BIT BUS; -- cko + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + -- vdde : in BIT; -- vdde + -- vddi : in BIT; -- vddi + -- vsse : in BIT; -- vsse + -- vssi : in BIT -- vssi + ); +END pvssck2_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvssck2_sp IS + +BEGIN + ASSERT ((((not (vss) and not (vss)) and vdd) and vdd) = '1') + REPORT "power supply is missing on pvssck2_sp" + SEVERITY WARNING; + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; +END; diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/supplyck_buf.ap b/pdks/symbolic/hibikino/cells/padlib_25um/supplyck_buf.ap new file mode 100644 index 000000000..76049f4ca --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/supplyck_buf.ap @@ -0,0 +1,362 @@ +V ALLIANCE : 6 +H supplyck_buf,P,10/12/2016,100 +A 0,0,6400,15600 +C 0,9700,3200,vss,0,WEST,ALU1 +C 0,4300,6000,vdd,0,WEST,ALU1 +C 0,700,600,ck,0,WEST,ALU1 +C 6400,4300,6000,vdd,1,EAST,ALU1 +C 6400,9700,3200,vss,1,EAST,ALU1 +C 6400,700,600,ck,1,EAST,ALU1 +S 0,10900,2900,10900,200,*,LEFT,ALU2 +S 4400,700,6000,700,600,*,LEFT,ALU2 +S 5800,600,5800,14500,200,*,DOWN,ALU2 +S 1700,2400,1700,14100,200,*,UP,ALU1 +S 2900,2400,2900,14100,200,*,UP,ALU1 +S 3200,7700,3500,7700,300,*,RIGHT,POLY +S 1400,7700,3200,7700,100,*,RIGHT,POLY +S 0,8200,0,14000,200,*,UP,ALU1 +S 0,12700,1100,12700,2800,*,LEFT,ALU1 +S 3500,15000,5300,15000,200,*,LEFT,ALU1 +S 500,13200,5300,13200,3800,*,RIGHT,ALU2 +S 2900,1100,2900,10700,5200,*,UP,NWELL +S 2900,11100,2900,15300,5200,*,DOWN,PWELL +S 500,5900,5300,5900,9200,*,RIGHT,ALU2 +S 4700,10400,5300,10400,200,*,LEFT,ALU1 +S 5300,8200,5300,10400,200,*,DOWN,ALU1 +S 5000,8200,5000,10400,800,*,DOWN,ALU1 +S 4700,8200,4700,10400,200,*,UP,ALU1 +S 2300,1400,2300,10400,200,*,UP,ALU1 +S 500,1400,500,10400,200,*,UP,ALU1 +S 500,10400,1100,10400,200,*,RIGHT,ALU1 +S 800,1400,800,10400,800,*,DOWN,ALU1 +S 1100,1400,1100,10400,200,*,UP,ALU1 +S 400,10400,5400,10400,300,*,LEFT,NTIE +S 4400,14400,4400,14600,100,*,DOWN,POLY +S 4400,14500,4600,14500,300,*,RIGHT,POLY +S 4600,14500,5800,14500,200,*,LEFT,ALU1 +S 4700,11400,5300,11400,200,*,LEFT,ALU1 +S 3500,11400,3500,14000,200,*,UP,ALU1 +S 5000,11400,5000,14000,800,*,DOWN,ALU1 +S 4700,11400,4700,14000,200,*,UP,ALU1 +S 5300,11400,5300,14000,200,*,UP,ALU1 +S 3500,14500,4100,14500,200,*,LEFT,ALU1 +S 1400,14400,3500,14400,100,*,LEFT,POLY +S 3500,11900,3500,14200,300,*,UP,NDIF +S 1100,11900,1100,14200,300,*,UP,NDIF +S 1400,11700,1400,14400,100,*,UP,NTRANS +S 2000,11700,2000,14400,100,*,UP,NTRANS +S 2600,11700,2600,14400,100,*,UP,NTRANS +S 3200,11700,3200,14400,100,*,UP,NTRANS +S 4700,11900,4700,14200,300,*,UP,NDIF +S 4100,11900,4100,14200,300,*,UP,NDIF +S 4400,11700,4400,14400,100,*,UP,NTRANS +S 4100,1900,4100,14500,200,*,DOWN,ALU1 +S 3500,1900,4100,1900,200,*,LEFT,ALU1 +S 3500,2200,3500,4500,300,*,UP,PDIF +S 1100,2200,1100,4500,300,*,UP,PDIF +S 1400,2000,1400,4700,100,*,UP,PTRANS +S 2000,2000,2000,4700,100,*,UP,PTRANS +S 2600,2000,2600,4700,100,*,UP,PTRANS +S 3200,2000,3200,4700,100,*,UP,PTRANS +S 5300,11300,5300,15100,300,*,DOWN,PTIE +S 500,11300,500,15100,300,*,DOWN,PTIE +S 400,11400,5400,11400,300,*,LEFT,PTIE +S 400,15000,5400,15000,300,*,LEFT,PTIE +S 0,4300,1100,4300,6000,*,RIGHT,ALU1 +S 4700,1400,4700,7200,200,*,UP,ALU1 +S 5000,1400,5000,7200,800,*,DOWN,ALU1 +S 500,1400,5300,1400,200,*,LEFT,ALU1 +S 3500,7700,4100,7700,200,*,LEFT,ALU1 +S 1100,5100,1100,7400,300,*,UP,PDIF +S 1400,4900,1400,7600,100,*,UP,PTRANS +S 2000,4900,2000,7600,100,*,UP,PTRANS +S 2600,4900,2600,7600,100,*,DOWN,PTRANS +S 3500,5100,3500,7400,300,*,UP,PDIF +S 3200,4900,3200,7600,100,*,UP,PTRANS +S 1400,7500,1400,7900,100,*,UP,POLY +S 2000,7500,2000,7900,100,*,UP,POLY +S 2600,7500,2600,7900,100,*,UP,POLY +S 3200,7500,3200,7900,100,*,UP,POLY +S 4400,7700,4600,7700,300,*,RIGHT,POLY +S 4600,7700,5800,7700,200,*,RIGHT,ALU1 +S 4400,7600,4400,7800,100,*,UP,POLY +S 5300,1400,5300,7200,200,*,DOWN,ALU1 +S 5300,1300,5300,10400,300,*,UP,NTIE +S 4400,7800,4400,10000,100,*,UP,PTRANS +S 4100,8000,4100,9800,300,*,UP,PDIF +S 4700,8000,4700,9800,300,*,UP,PDIF +S 3200,7800,3200,10000,100,*,UP,PTRANS +S 3500,8000,3500,9800,300,*,UP,PDIF +S 2600,7800,2600,10000,100,*,UP,PTRANS +S 2000,7800,2000,10000,100,*,UP,PTRANS +S 1400,7800,1400,10000,100,*,UP,PTRANS +S 400,1400,5400,1400,300,*,LEFT,NTIE +S 1100,8000,1100,9800,300,*,UP,PDIF +S 500,1300,500,10400,300,*,UP,NTIE +S 4100,2100,4100,7400,300,*,UP,PDIF +S 4700,2100,4700,7400,300,*,DOWN,PDIF +S 4400,1900,4400,7600,100,*,UP,PTRANS +S 3500,8100,3500,10400,200,*,UP,ALU1 +S 3500,2400,3500,7200,200,*,DOWN,ALU1 +S 800,11400,800,14400,800,*,DOWN,ALU1 +S 2300,11400,2300,15000,200,*,UP,ALU1 +S 1100,11400,1100,14400,200,*,UP,ALU1 +S 500,11400,500,14400,200,*,UP,ALU1 +S 1400,2000,3600,2000,100,*,RIGHT,POLY +S 4700,12700,6400,12700,2800,*,LEFT,ALU1 +S 6400,8200,6400,14000,200,*,UP,ALU1 +S 4700,4300,6400,4300,6000,*,LEFT,ALU1 +S 0,700,6400,700,600,*,RIGHT,ALU1 +S 3200,15000,3200,17500,4000,*,UP,ALU2 +S 3200,15600,3200,17500,4000,*,UP,ALU1 +V 1700,10900,CONT_VIA,* +V 2900,10900,CONT_VIA,* +V 4800,700,CONT_VIA,* +V 5300,700,CONT_VIA,* +V 5800,700,CONT_VIA,* +V 500,14000,CONT_VIA,* +V 1100,14000,CONT_VIA,* +V 1100,13200,CONT_VIA,* +V 500,13200,CONT_VIA,* +V 500,12400,CONT_VIA,* +V 1100,12400,CONT_VIA,* +V 2300,12400,CONT_VIA,* +V 2300,13200,CONT_VIA,* +V 2300,14000,CONT_VIA,* +V 3500,14000,CONT_VIA,* +V 3500,13200,CONT_VIA,* +V 3500,12400,CONT_VIA,* +V 4700,14000,CONT_VIA,* +V 5300,14000,CONT_VIA,* +V 5300,13200,CONT_VIA,* +V 4700,13200,CONT_VIA,* +V 4700,12400,CONT_VIA,* +V 5300,12400,CONT_VIA,* +V 4100,15000,CONT_VIA,* +V 4700,15000,CONT_VIA,* +V 3500,15000,CONT_BODY_P,* +V 5300,15000,CONT_BODY_P,* +V 2300,15000,CONT_BODY_P,* +V 3500,11400,CONT_BODY_P,* +V 2300,11400,CONT_BODY_P,* +V 1100,11400,CONT_BODY_P,* +V 500,11400,CONT_BODY_P,* +V 500,14400,CONT_BODY_P,* +V 500,13600,CONT_BODY_P,* +V 500,12800,CONT_BODY_P,* +V 500,12000,CONT_BODY_P,* +V 5300,12000,CONT_BODY_P,* +V 5300,12800,CONT_BODY_P,* +V 5300,13600,CONT_BODY_P,* +V 1100,12000,CONT_DIF_N,* +V 1100,12800,CONT_DIF_N,* +V 1100,13600,CONT_DIF_N,* +V 1700,14000,CONT_DIF_N,* +V 1700,13600,CONT_DIF_N,* +V 1700,13200,CONT_DIF_N,* +V 1700,12800,CONT_DIF_N,* +V 1700,12400,CONT_DIF_N,* +V 1700,12000,CONT_DIF_N,* +V 2300,12000,CONT_DIF_N,* +V 2300,12800,CONT_DIF_N,* +V 2300,13600,CONT_DIF_N,* +V 2900,14000,CONT_DIF_N,* +V 2900,13600,CONT_DIF_N,* +V 2900,13200,CONT_DIF_N,* +V 2900,12800,CONT_DIF_N,* +V 2900,12400,CONT_DIF_N,* +V 2900,12000,CONT_DIF_N,* +V 3500,12000,CONT_DIF_N,* +V 3500,12800,CONT_DIF_N,* +V 3500,13600,CONT_DIF_N,* +V 4100,14000,CONT_DIF_N,* +V 4100,13600,CONT_DIF_N,* +V 4100,13200,CONT_DIF_N,* +V 4100,12800,CONT_DIF_N,* +V 4100,12400,CONT_DIF_N,* +V 4100,12000,CONT_DIF_N,* +V 4700,12000,CONT_DIF_N,* +V 4700,12800,CONT_DIF_N,* +V 4700,13600,CONT_DIF_N,* +V 1100,7700,CONT_VIA,* +V 500,7700,CONT_VIA,* +V 5300,4000,CONT_VIA,* +V 4700,4000,CONT_VIA,* +V 5300,2800,CONT_VIA,* +V 4700,2800,CONT_VIA,* +V 500,2800,CONT_VIA,* +V 500,4000,CONT_VIA,* +V 1100,5600,CONT_VIA,* +V 500,5600,CONT_VIA,* +V 500,6800,CONT_VIA,* +V 1100,6800,CONT_VIA,* +V 2300,6800,CONT_VIA,* +V 2300,5600,CONT_VIA,* +V 3500,5600,CONT_VIA,* +V 3500,6800,CONT_VIA,* +V 4700,6800,CONT_VIA,* +V 5300,6800,CONT_VIA,* +V 4700,5600,CONT_VIA,* +V 5300,5600,CONT_VIA,* +V 4700,4800,CONT_VIA,* +V 5300,4800,CONT_VIA,* +V 500,7200,CONT_BODY_N,* +V 500,6400,CONT_BODY_N,* +V 500,6000,CONT_BODY_N,* +V 500,5200,CONT_BODY_N,* +V 500,4400,CONT_BODY_N,* +V 500,3600,CONT_BODY_N,* +V 500,3200,CONT_BODY_N,* +V 500,2400,CONT_BODY_N,* +V 5300,2400,CONT_BODY_N,* +V 5300,3200,CONT_BODY_N,* +V 5300,3600,CONT_BODY_N,* +V 5300,4400,CONT_BODY_N,* +V 5300,5200,CONT_BODY_N,* +V 5300,6000,CONT_BODY_N,* +V 5300,6400,CONT_BODY_N,* +V 5300,7200,CONT_BODY_N,* +V 4700,2400,CONT_DIF_P,* +V 4700,3200,CONT_DIF_P,* +V 4700,3600,CONT_DIF_P,* +V 4700,4400,CONT_DIF_P,* +V 4700,5200,CONT_DIF_P,* +V 4700,6000,CONT_DIF_P,* +V 4700,6400,CONT_DIF_P,* +V 4100,6800,CONT_DIF_P,* +V 4100,6400,CONT_DIF_P,* +V 4100,6000,CONT_DIF_P,* +V 4100,5600,CONT_DIF_P,* +V 4100,5200,CONT_DIF_P,* +V 4100,4800,CONT_DIF_P,* +V 4100,4400,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,3600,CONT_DIF_P,* +V 4100,3200,CONT_DIF_P,* +V 4100,2800,CONT_DIF_P,* +V 4100,2400,CONT_DIF_P,* +V 1100,4400,CONT_DIF_P,* +V 1100,3600,CONT_DIF_P,* +V 1100,3200,CONT_DIF_P,* +V 1700,2800,CONT_DIF_P,* +V 1700,3200,CONT_DIF_P,* +V 1700,3600,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 1700,4400,CONT_DIF_P,* +V 2300,3600,CONT_DIF_P,* +V 2300,3200,CONT_DIF_P,* +V 2900,2800,CONT_DIF_P,* +V 2900,3200,CONT_DIF_P,* +V 2900,3600,CONT_DIF_P,* +V 2900,4000,CONT_DIF_P,* +V 2900,4400,CONT_DIF_P,* +V 2300,4400,CONT_DIF_P,* +V 1100,7200,CONT_DIF_P,* +V 1100,6400,CONT_DIF_P,* +V 1100,6000,CONT_DIF_P,* +V 1700,7200,CONT_DIF_P,* +V 1700,6800,CONT_DIF_P,* +V 1700,6400,CONT_DIF_P,* +V 1700,6000,CONT_DIF_P,* +V 1700,5600,CONT_DIF_P,* +V 2300,7200,CONT_DIF_P,* +V 2300,6400,CONT_DIF_P,* +V 2300,6000,CONT_DIF_P,* +V 2900,7200,CONT_DIF_P,* +V 2900,6800,CONT_DIF_P,* +V 2900,6400,CONT_DIF_P,* +V 2900,6000,CONT_DIF_P,* +V 2900,5600,CONT_DIF_P,* +V 1100,5200,CONT_DIF_P,* +V 1700,5200,CONT_DIF_P,* +V 2300,5200,CONT_DIF_P,* +V 2900,5200,CONT_DIF_P,* +V 3500,7200,CONT_DIF_P,* +V 3500,6400,CONT_DIF_P,* +V 3500,6000,CONT_DIF_P,* +V 3500,5200,CONT_DIF_P,* +V 1100,4800,CONT_VIA,* +V 1100,4000,CONT_VIA,* +V 1100,2800,CONT_VIA,* +V 2300,2800,CONT_VIA,* +V 2300,4000,CONT_VIA,* +V 3500,2800,CONT_VIA,* +V 3500,4000,CONT_VIA,* +V 2300,4800,CONT_VIA,* +V 3500,4800,CONT_VIA,* +V 3500,4400,CONT_DIF_P,* +V 3500,3600,CONT_DIF_P,* +V 3500,3200,CONT_DIF_P,* +V 1100,8100,CONT_DIF_P,* +V 1700,8100,CONT_DIF_P,* +V 2300,8100,CONT_DIF_P,* +V 2900,8100,CONT_DIF_P,* +V 1100,8900,CONT_DIF_P,* +V 1700,8900,CONT_DIF_P,* +V 2300,8900,CONT_DIF_P,* +V 2900,8900,CONT_DIF_P,* +V 5300,8500,CONT_VIA,* +V 500,8500,CONT_VIA,* +V 500,9300,CONT_VIA,* +V 5300,9300,CONT_VIA,* +V 5300,8900,CONT_BODY_N,* +V 5300,9700,CONT_BODY_N,* +V 2900,8500,CONT_DIF_P,* +V 1700,8500,CONT_DIF_P,* +V 1700,9300,CONT_DIF_P,* +V 2900,9300,CONT_DIF_P,* +V 4100,9300,CONT_DIF_P,* +V 4100,8500,CONT_DIF_P,* +V 4100,8100,CONT_DIF_P,* +V 4100,8900,CONT_DIF_P,* +V 4700,8900,CONT_DIF_P,* +V 4700,8500,CONT_VIA,* +V 4700,9300,CONT_VIA,* +V 1100,8500,CONT_VIA,* +V 1100,9300,CONT_VIA,* +V 2300,9300,CONT_VIA,* +V 2300,8500,CONT_VIA,* +V 4100,1400,CONT_BODY_N,* +V 3500,1400,CONT_BODY_N,* +V 2900,1400,CONT_BODY_N,* +V 2300,1400,CONT_BODY_N,* +V 1700,1400,CONT_BODY_N,* +V 1100,1400,CONT_BODY_N,* +V 500,1400,CONT_BODY_N,* +V 4700,1400,CONT_BODY_N,* +V 5300,10400,CONT_BODY_N,* +V 4700,10400,CONT_BODY_N,* +V 500,10400,CONT_BODY_N,* +V 1100,10400,CONT_BODY_N,* +V 2300,10400,CONT_BODY_N,* +V 3500,10400,CONT_BODY_N,* +V 3500,8500,CONT_VIA,* +V 3500,9300,CONT_VIA,* +V 3500,8100,CONT_DIF_P,* +V 3500,8900,CONT_DIF_P,* +V 1100,9700,CONT_DIF_P,* +V 1700,9700,CONT_DIF_P,* +V 2300,9700,CONT_DIF_P,* +V 2900,9700,CONT_DIF_P,* +V 3500,9700,CONT_DIF_P,* +V 1100,2400,CONT_DIF_P,* +V 1700,2400,CONT_DIF_P,* +V 2300,2400,CONT_DIF_P,* +V 2900,2400,CONT_DIF_P,* +V 3500,2400,CONT_DIF_P,* +V 4100,7200,CONT_DIF_P,* +V 4700,7200,CONT_DIF_P,* +V 5800,14500,CONT_VIA,* +V 4600,14500,CONT_POLY,* +V 4700,11400,CONT_VIA,* +V 3500,14500,CONT_POLY,* +V 3500,1900,CONT_POLY,* +V 5300,11400,CONT_BODY_P,* +V 3500,7700,CONT_POLY,* +V 4600,7700,CONT_POLY,* +V 5800,7700,CONT_VIA,* +V 4100,9700,CONT_DIF_P,* +V 4700,9700,CONT_DIF_P,* +V 5300,1400,CONT_BODY_N,* +V 500,4800,CONT_VIA,* +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/vddck_con.ap b/pdks/symbolic/hibikino/cells/padlib_25um/vddck_con.ap new file mode 100644 index 000000000..c0ab8d4c4 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/vddck_con.ap @@ -0,0 +1,30 @@ +V ALLIANCE : 6 +H vddck_con,P,10/12/2016,100 +A -200,0,6200,15600 +C 6200,4300,6000,vdd,3,EAST,ALU1 +C 6200,9700,3200,vss,1,EAST,ALU1 +C 6200,700,600,ck,1,EAST,ALU1 +C 5700,0,200,cko,1,NORTH,ALU2 +C 5700,0,200,cko,0,SOUTH,ALU1 +C -200,9700,3200,vss,0,WEST,ALU1 +C -200,4300,6000,vdd,2,WEST,ALU1 +C -200,700,600,ck,0,WEST,ALU1 +C 3000,15600,4000,vdd,5,NORTH,ALU2 +C 3000,15600,4000,vdd,4,NORTH,ALU1 +C 3000,0,2000,vdd,1,SOUTH,ALU2 +C 3000,0,2000,vdd,0,SOUTH,ALU1 +S 5700,0,5700,10900,200,*,DOWN,ALU2 +S 5700,10900,6200,10900,200,*,LEFT,ALU2 +S -200,9700,6200,9700,3200,*,RIGHT,ALU1 +S -200,4300,6200,4300,6000,*,RIGHT,ALU1 +S -200,700,6200,700,600,*,LEFT,ALU1 +S 3000,1400,3000,17500,4000,*,UP,ALU2 +S 3000,15600,3000,17500,4000,*,UP,ALU1 +S 3000,0,3000,7200,2000,*,UP,ALU2 +V 5700,0,CONT_VIA,* +V 3800,0,CONT_VIA,* +V 3300,0,CONT_VIA,* +V 2800,0,CONT_VIA,* +V 2300,0,CONT_VIA,* +B 3000,4300,4000,6000,CONT_VIA,* +EOF diff --git a/pdks/symbolic/hibikino/cells/padlib_25um/vssck_con.ap b/pdks/symbolic/hibikino/cells/padlib_25um/vssck_con.ap new file mode 100644 index 000000000..01662b6aa --- /dev/null +++ b/pdks/symbolic/hibikino/cells/padlib_25um/vssck_con.ap @@ -0,0 +1,30 @@ +V ALLIANCE : 6 +H vssck_con,P,10/12/2016,100 +A -200,0,6200,15600 +C 3000,0,2000,vss,0,SOUTH,ALU1 +C 3000,0,2000,vss,1,SOUTH,ALU2 +C 3000,15600,4000,vss,7,NORTH,ALU1 +C 3000,15600,4000,vss,8,NORTH,ALU2 +C -200,9700,3200,vss,4,WEST,ALU1 +C -200,4300,6000,vdd,0,WEST,ALU1 +C -200,700,600,ck,0,WEST,ALU1 +C 6200,4300,6000,vdd,2,EAST,ALU1 +C 6200,9700,3200,vss,6,EAST,ALU1 +C 6200,700,600,ck,2,EAST,ALU1 +C 5700,0,200,cko,1,NORTH,ALU2 +C 5700,0,200,cko,0,SOUTH,ALU1 +S 3000,0,3000,11200,2000,*,UP,ALU2 +S 3000,8200,3000,17500,4000,*,DOWN,ALU1 +S 3000,8200,3000,17500,4000,*,UP,ALU2 +S -200,700,6200,700,600,*,LEFT,ALU1 +S -200,4300,6200,4300,6000,*,RIGHT,ALU1 +S -200,9700,6200,9700,3200,*,RIGHT,ALU1 +S 5700,0,5700,10900,200,*,DOWN,ALU2 +S 5700,10900,6200,10900,200,*,LEFT,ALU2 +V 3800,0,CONT_VIA,* +V 3300,0,CONT_VIA,* +V 2700,0,CONT_VIA,* +V 2200,0,CONT_VIA,* +B 3000,9700,4000,3200,CONT_VIA,* +V 5700,0,CONT_VIA,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/CATAL b/pdks/symbolic/hibikino/cells/sxlib_25um/CATAL new file mode 100644 index 000000000..8b40a9293 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/CATAL @@ -0,0 +1,98 @@ +a2_x2 C +a2_x4 C +a3_x2 C +a3_x4 C +a4_x2 C +a4_x4 C +an12_x1 C +an12_x4 C +ao22_x2 C +ao22_x4 C +ao2o22_x2 C +ao2o22_x4 C +buf_x2 C +buf_x4 C +buf_x8 C +fulladder_x2 C +fulladder_x4 C +halfadder_x2 C +halfadder_x4 C +inv_x1 C +inv_x2 C +inv_x4 C +inv_x8 C +mx2_x2 C +mx2_x4 C +mx3_x2 C +mx3_x4 C +na2_x1 C +na2_x4 C +na3_x1 C +na3_x4 C +na4_x1 C +na4_x4 C +nao22_x1 C +nao22_x4 C +nao2o22_x1 C +nao2o22_x4 C +nmx2_x1 C +nmx2_x4 C +nmx3_x1 C +nmx3_x4 C +no2_x1 C +no2_x4 C +no3_x1 C +no3_x4 C +no4_x1 C +no4_x4 C +noa22_x1 C +noa22_x4 C +noa2a22_x1 C +noa2a22_x4 C +noa2a2a23_x1 C +noa2a2a23_x4 C +noa2a2a2a24_x1 C +noa2a2a2a24_x4 C +noa2ao222_x1 C +noa2ao222_x4 C +noa3ao322_x1 C +noa3ao322_x4 C +nts_x1 C +nts_x2 C +nxr2_x1 C +nxr2_x4 C +o2_x2 C +o2_x4 C +o3_x2 C +o3_x4 C +o4_x2 C +o4_x4 C +oa22_x2 C +oa22_x4 C +oa2a22_x2 C +oa2a22_x4 C +oa2a2a23_x2 C +oa2a2a23_x4 C +oa2a2a2a24_x2 C +oa2a2a2a24_x4 C +oa2ao222_x2 C +oa2ao222_x4 C +oa3ao322_x2 C +oa3ao322_x4 C +on12_x1 C +on12_x4 C +one_x0 C +powmid_x0 C +powmid_x0 F +rowend_x0 C +rowend_x0 F +sff1_x4 C +sff2_x4 C +sff3_x4 C +tie_x0 C +tie_x0 F +ts_x4 C +ts_x8 C +xr2_x1 C +xr2_x4 C +zero_x0 C diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x2.ap new file mode 100644 index 000000000..66d758a3e --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x2.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H a2_x2,P,22/ 7/2016,100 +A 0,0,2500,5000 +R 1500,3000,ref_ref,i1_25 +R 1500,2500,ref_ref,i1_30 +R 1500,4000,ref_ref,i1_40 +R 1500,3500,ref_ref,i1_35 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 1500,1000,ref_ref,i1_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 2000,2500,ref_ref,q_25 +R 2000,3000,ref_ref,q_30 +R 2000,3500,ref_ref,q_35 +R 2000,4000,ref_ref,q_40 +R 2000,1000,ref_ref,q_10 +R 2000,1500,ref_ref,q_15 +R 2000,2000,ref_ref,q_20 +S 1500,1000,1500,4000,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 2000,1000,2000,4000,200,q,DOWN,CALU1 +S 900,300,900,1700,300,*,UP,NDIF +S 300,800,300,1700,300,*,UP,NDIF +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1000,2000,1800,2000,100,*,RIGHT,POLY +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,ALU1 +S 0,300,2500,300,600,vss,RIGHT,ALU1 +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 1800,1400,1800,2600,100,*,UP,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1200,2400,1200,3100,100,*,DOWN,POLY +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 500,1500,500,3500,200,*,DOWN,ALU1 +S 0,1000,2500,1000,1800,*,RIGHT,PWELL +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 300,4000,300,4500,200,*,UP,ALU1 +S 2000,1000,2000,4000,200,*,DOWN,ALU1 +S 300,1000,900,1000,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 1500,1000,1500,4000,200,*,DOWN,ALU1 +V 1500,2500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 300,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 500,3000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x2.vbe new file mode 100644 index 000000000..8e6db7cd8 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i1_q : NATURAL := 203; + CONSTANT tphh_i0_q : NATURAL := 261; + CONSTANT tpll_i0_q : NATURAL := 388; + CONSTANT tpll_i1_q : NATURAL := 434; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x2; + +ARCHITECTURE behaviour_data_flow OF a2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x2" + SEVERITY WARNING; + q <= (i0 and i1) after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x4.ap new file mode 100644 index 000000000..61b832d6d --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x4.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H a2_x4,P,22/ 7/2016,100 +A 0,0,3000,5000 +R 1500,2500,ref_ref,i1_30 +R 1500,3000,ref_ref,i1_25 +R 1500,4000,ref_ref,i1_40 +R 1500,3500,ref_ref,i1_35 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 1500,1000,ref_ref,i1_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 2000,2500,ref_ref,q_25 +R 2000,3000,ref_ref,q_30 +R 2000,3500,ref_ref,q_35 +R 2000,4000,ref_ref,q_40 +R 2000,1000,ref_ref,q_10 +R 2000,1500,ref_ref,q_15 +R 2000,2000,ref_ref,q_20 +S 300,1000,900,1000,200,*,RIGHT,ALU1 +S 1500,1000,1500,4000,200,*,DOWN,ALU1 +S 500,1500,500,3500,200,*,DOWN,ALU1 +S 1500,1000,1500,4000,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 2000,1000,2000,4000,200,q,DOWN,CALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +S 0,1000,3000,1000,1800,*,RIGHT,PWELL +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 2700,3000,2700,4500,200,*,DOWN,ALU1 +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,UP,POLY +S 1000,2000,2400,2000,100,*,RIGHT,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 1200,2400,1200,3100,100,*,DOWN,POLY +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 2000,1000,2000,4000,200,*,DOWN,ALU1 +S 2700,500,2700,1000,200,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +V 1500,1500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1000,2000,CONT_POLY,* +V 300,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 500,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x4.vbe new file mode 100644 index 000000000..f6955d6e9 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphh_i0_q : NATURAL := 338; + CONSTANT tpll_i0_q : NATURAL := 476; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x4; + +ARCHITECTURE behaviour_data_flow OF a2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x4" + SEVERITY WARNING; + q <= (i0 and i1) after 1100 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x2.ap new file mode 100644 index 000000000..2a541b5b4 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x2.ap @@ -0,0 +1,93 @@ +V ALLIANCE : 6 +H a3_x2,P,22/ 7/2016,100 +A 0,0,3000,5000 +R 2500,2500,ref_ref,q_20 +R 2500,2000,ref_ref,q_25 +R 1500,2500,ref_ref,i2_35 +R 1500,3500,ref_ref,i2_25 +R 1000,2500,ref_ref,i1_35 +R 1000,3500,ref_ref,i1_25 +R 1500,2000,ref_ref,i2_20 +R 1500,1500,ref_ref,i2_15 +R 500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 1000,3000,ref_ref,i1_30 +R 1000,2000,ref_ref,i1_20 +R 1500,3000,ref_ref,i2_30 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +R 2500,1500,ref_ref,q_15 +R 2500,1000,ref_ref,q_10 +S 1400,3100,1800,3100,100,*,RIGHT,POLY +S 600,3000,600,3100,100,*,DOWN,POLY +S 2400,2500,2400,2600,100,*,UP,POLY +S 2400,1300,2400,1500,100,*,DOWN,POLY +S 2200,1500,2400,1500,100,*,RIGHT,POLY +S 2200,2500,2400,2500,100,*,RIGHT,POLY +S 2200,1500,2200,2500,100,*,UP,POLY +S 1900,2000,2200,2000,300,*,RIGHT,POLY +S 2500,1000,2700,1000,200,*,LEFT,ALU1 +S 2500,4000,2700,4000,200,*,LEFT,ALU1 +S 300,4000,2000,4000,200,*,RIGHT,ALU1 +S 300,1000,2000,1000,200,*,RIGHT,ALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 1500,1500,1500,3500,200,*,DOWN,ALU1 +S 1000,1500,1000,3500,200,*,DOWN,ALU1 +S 500,1500,500,3500,200,*,DOWN,ALU1 +S 300,300,1100,300,300,*,RIGHT,PTIE +S 2500,3000,2700,3000,200,*,LEFT,ALU1 +S 2500,3500,2700,3500,200,*,LEFT,ALU1 +S 300,800,300,1700,300,*,UP,NDIF +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 1000,3100,1200,3100,100,*,LEFT,POLY +S 900,3300,900,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 0,1000,3000,1000,1800,*,RIGHT,PWELL +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 1500,1500,1500,3500,200,i2,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 2000,300,2000,1200,400,*,UP,NDIF +S 1700,300,1700,1700,300,*,UP,NDIF +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +V 1500,3000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,3000,CONT_POLY,* +V 1100,300,CONT_BODY_P,* +V 700,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 2000,2000,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 900,4500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,1000,CONT_DIF_N,* +V 2100,4500,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 1700,500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x2.vbe new file mode 100644 index 000000000..7a7b521b3 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 290; + CONSTANT tphh_i1_q : NATURAL := 353; + CONSTANT tphh_i0_q : NATURAL := 395; + CONSTANT tpll_i0_q : NATURAL := 435; + CONSTANT tpll_i1_q : NATURAL := 479; + CONSTANT tpll_i2_q : NATURAL := 521; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x2; + +ARCHITECTURE behaviour_data_flow OF a3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x2" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1100 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x4.ap new file mode 100644 index 000000000..c84482bfe --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x4.ap @@ -0,0 +1,94 @@ +V ALLIANCE : 6 +H a3_x4,P, 9/12/2016,100 +A 0,0,3500,5000 +R 2500,1500,ref_ref,q_15 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1500,2500,ref_ref,i2_25 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 2500,4000,ref_ref,q_40 +R 2500,3500,ref_ref,q_35 +R 2500,3000,ref_ref,q_30 +R 2500,2500,ref_ref,q_25 +R 2500,2000,ref_ref,q_20 +R 2500,1000,ref_ref,q_10 +S 1000,2800,1200,2800,300,*,LEFT,POLY +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +S 3200,500,3200,1000,200,*,DOWN,ALU1 +S 2000,4500,2000,4700,300,*,UP,PDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 3200,300,3200,1200,300,*,UP,NDIF +S 2900,100,2900,1400,100,*,DOWN,NTRANS +S 2600,300,2600,1200,300,*,UP,NDIF +S 2300,100,2300,1400,100,*,DOWN,NTRANS +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 2900,1400,2900,2600,100,*,UP,POLY +S 2300,1400,2300,2600,100,*,UP,POLY +S 1800,2900,1800,4200,100,*,UP,PTRANS +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1600,2900,1800,2900,100,*,RIGHT,POLY +S 1900,2000,2900,2000,300,*,RIGHT,POLY +S 2100,2800,2100,4700,300,*,UP,PDIF +S 300,3100,300,4000,300,*,DOWN,PDIF +S 1200,2900,1200,4200,100,*,UP,PTRANS +S 600,2900,600,4200,100,*,UP,PTRANS +S 1500,3100,1500,4000,300,*,DOWN,PDIF +S 900,3100,900,4600,300,*,DOWN,PDIF +S 1900,300,1900,1200,300,*,UP,NDIF +S 1700,300,1700,1200,300,*,UP,NDIF +S 3200,3000,3200,4500,200,*,DOWN,ALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 0,1000,3500,1000,1800,*,RIGHT,PWELL +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i2,DOWN,CALU1 +S 300,4000,2000,4000,200,*,RIGHT,ALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 1500,1500,1500,3500,200,*,DOWN,ALU1 +S 1000,1500,1000,3500,200,*,DOWN,ALU1 +S 300,1000,2000,1000,200,*,RIGHT,ALU1 +S 500,1500,500,3500,200,*,DOWN,ALU1 +S 1200,2700,1200,2900,100,*,DOWN,POLY +V 2000,4600,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 3200,500,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2000,500,CONT_DIF_N,* +V 2600,1000,CONT_DIF_N,* +V 2600,3000,CONT_DIF_P,* +V 2600,4000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 3200,4500,CONT_DIF_P,* +V 2600,3500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 1000,2800,CONT_POLY,* +V 1500,2800,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 500,2800,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x4.vbe new file mode 100644 index 000000000..556b6b0fc --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 356; + CONSTANT tphh_i1_q : NATURAL := 428; + CONSTANT tphh_i0_q : NATURAL := 478; + CONSTANT tpll_i0_q : NATURAL := 514; + CONSTANT tpll_i1_q : NATURAL := 554; + CONSTANT tpll_i2_q : NATURAL := 592; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x4; + +ARCHITECTURE behaviour_data_flow OF a3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x4" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x2.ap new file mode 100644 index 000000000..66e4cd2e4 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x2.ap @@ -0,0 +1,110 @@ +V ALLIANCE : 6 +H a4_x2,P, 9/12/2016,100 +A 0,0,3500,5000 +R 3000,2500,ref_ref,q_20 +R 3000,2000,ref_ref,q_25 +R 1500,1000,ref_ref,i2_10 +R 1000,1000,ref_ref,i1_10 +R 500,1000,ref_ref,i0_10 +R 3000,1000,ref_ref,q_10 +R 3000,1500,ref_ref,q_15 +R 3000,3000,ref_ref,q_30 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1000,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 2000,3500,ref_ref,i3_35 +R 2000,3000,ref_ref,i3_30 +R 2000,2000,ref_ref,i3_20 +R 1000,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i2_25 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 2000,2500,ref_ref,i3_15 +R 2000,1500,ref_ref,i3_25 +S 2500,2600,2900,2600,100,*,RIGHT,POLY +S 2500,1400,2900,1400,100,*,RIGHT,POLY +S 1600,3100,1800,3100,100,*,RIGHT,POLY +S 2100,2900,2100,3100,100,*,DOWN,POLY +S 3000,4000,3200,4000,200,*,RIGHT,ALU1 +S 3000,1000,3200,1000,200,*,LEFT,ALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3000,1100,3000,4000,200,q,DOWN,CALU1 +S 900,300,1900,300,300,*,RIGHT,PTIE +S 2000,1500,2000,3500,200,i3,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 3000,3000,3200,3000,200,*,RIGHT,ALU1 +S 3000,3500,3200,3500,200,*,RIGHT,ALU1 +S 1500,1000,1500,3500,200,*,DOWN,ALU1 +S 1000,1000,1000,3500,200,*,DOWN,ALU1 +S 500,1000,500,3500,200,*,DOWN,ALU1 +S 2000,800,2000,1700,300,*,UP,NDIF +S 300,400,300,1700,300,*,UP,NDIF +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1800,600,1800,1900,100,*,DOWN,NTRANS +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 1800,1900,2100,1900,100,*,RIGHT,POLY +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 3200,300,3200,1200,300,*,UP,NDIF +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 2900,100,2900,1400,100,*,DOWN,NTRANS +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 2100,3100,2400,3100,100,*,LEFT,POLY +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 2000,1500,2000,3500,200,*,DOWN,ALU1 +S 300,3300,300,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 1500,3300,1500,4600,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 0,1000,3500,1000,1800,*,RIGHT,PWELL +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +S 2100,1000,2500,1000,200,*,RIGHT,ALU1 +S 900,4000,2500,4000,200,*,RIGHT,ALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +S 1800,2000,1900,2000,300,*,LEFT,POLY +V 2000,2800,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 1500,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 500,3000,CONT_POLY,* +V 1800,300,CONT_BODY_P,* +V 1000,300,CONT_BODY_P,* +V 2000,2000,CONT_POLY,* +V 2600,400,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 3200,3000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 2500,2500,CONT_POLY,* +V 2600,4700,CONT_DIF_P,* +V 300,500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x2.vbe new file mode 100644 index 000000000..3a6353969 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 374; + CONSTANT tphh_i1_q : NATURAL := 441; + CONSTANT tpll_i3_q : NATURAL := 455; + CONSTANT tphh_i2_q : NATURAL := 482; + CONSTANT tpll_i2_q : NATURAL := 498; + CONSTANT tphh_i3_q : NATURAL := 506; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x2; + +ARCHITECTURE behaviour_data_flow OF a4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x4.ap new file mode 100644 index 000000000..5631c7f3d --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x4.ap @@ -0,0 +1,118 @@ +V ALLIANCE : 6 +H a4_x4,P, 9/12/2016,100 +A 0,0,4000,5000 +R 1500,1000,ref_ref,i2_10 +R 1000,1000,ref_ref,i1_10 +R 500,1000,ref_ref,i0_10 +R 3000,1000,ref_ref,q_10 +R 3000,1500,ref_ref,q_15 +R 3000,2000,ref_ref,q_20 +R 3000,2500,ref_ref,q_25 +R 3000,3000,ref_ref,q_30 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1000,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 2000,3500,ref_ref,i3_35 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,2000,ref_ref,i3_20 +R 2000,1500,ref_ref,i3_15 +R 1000,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i2_25 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +S 1450,3300,1450,4800,200,*,DOWN,PDIF +S 1800,2000,1900,2000,300,*,LEFT,POLY +S 3000,1100,3000,4000,200,q,DOWN,CALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3700,500,3700,1000,200,*,DOWN,ALU1 +S 2000,1500,2000,3500,200,i3,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 2000,900,2000,1700,300,*,UP,NDIF +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +S 900,4000,2500,4000,200,*,RIGHT,ALU1 +S 2100,1000,2500,1000,200,*,RIGHT,ALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 0,1000,4000,1000,1800,*,RIGHT,PWELL +S 1500,1000,1500,3500,200,*,DOWN,ALU1 +S 1000,1000,1000,3500,200,*,DOWN,ALU1 +S 500,1000,500,3500,200,*,DOWN,ALU1 +S 300,400,300,1700,300,*,UP,NDIF +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1800,600,1800,1900,100,*,DOWN,NTRANS +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 1800,1900,2100,1900,100,*,RIGHT,POLY +S 3200,300,3200,1200,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 2000,1500,2000,3500,200,*,DOWN,ALU1 +S 300,3300,300,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 900,3300,900,4200,300,*,DOWN,PDIF +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 3400,2600,3400,4900,100,*,DOWN,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 3700,3000,3700,4500,200,*,UP,ALU1 +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 1700,3100,1700,4400,100,*,UP,PTRANS +S 2300,3100,2300,4400,100,*,UP,PTRANS +S 2100,3100,2300,3100,100,*,LEFT,POLY +S 1600,3100,1700,3100,100,*,RIGHT,POLY +S 2550,2800,2550,4700,200,*,DOWN,PDIF +S 900,300,1900,300,300,*,RIGHT,PTIE +S 2400,2000,3400,2000,300,*,RIGHT,POLY +S 2700,1400,2700,2600,100,*,UP,POLY +S 2700,2600,2800,2600,100,*,RIGHT,POLY +S 2700,1400,2800,1400,100,*,RIGHT,POLY +V 300,4000,CONT_DIF_P,* +V 1800,300,CONT_BODY_P,* +V 1000,300,CONT_BODY_P,* +V 2000,2000,CONT_POLY,* +V 2100,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 2500,400,CONT_DIF_N,* +V 3100,1000,CONT_DIF_N,* +V 3100,4000,CONT_DIF_P,* +V 3100,3000,CONT_DIF_P,* +V 3100,3500,CONT_DIF_P,* +V 2500,4700,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 3700,500,CONT_DIF_N,* +V 3700,4500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 1500,4700,CONT_DIF_P,* +V 2000,4000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 500,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1500,3000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x4.vbe new file mode 100644 index 000000000..4f96afa4c --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/a4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 540; + CONSTANT rdown_i1_q : NATURAL := 540; + CONSTANT rdown_i2_q : NATURAL := 540; + CONSTANT rdown_i3_q : NATURAL := 540; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 505; + CONSTANT tpll_i3_q : NATURAL := 538; + CONSTANT tpll_i2_q : NATURAL := 576; + CONSTANT tphh_i1_q : NATURAL := 578; + CONSTANT tpll_i1_q : NATURAL := 614; + CONSTANT tphh_i2_q : NATURAL := 627; + CONSTANT tpll_i0_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 661; + CONSTANT transistors : NATURAL := 13 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x4; + +ARCHITECTURE behaviour_data_flow OF a4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1300 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x1.ap new file mode 100644 index 000000000..6d7570275 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x1.ap @@ -0,0 +1,80 @@ +V ALLIANCE : 6 +H an12_x1,P, 1/ 8/2016,100 +A 0,0,2500,5000 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i0_20 +R 500,1500,ref_ref,q_15 +R 500,2500,ref_ref,q_25 +R 500,3000,ref_ref,q_30 +R 1500,4000,ref_ref,i1_40 +R 1500,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i1_30 +R 500,3500,ref_ref,q_35 +R 500,4000,ref_ref,q_40 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 1000,4000,ref_ref,i0_40 +R 500,1000,ref_ref,q_10 +R 1000,1500,ref_ref,i0_25 +R 1000,2500,ref_ref,i0_15 +R 1500,1000,ref_ref,i1_25 +R 1500,2500,ref_ref,i1_10 +S 500,1000,500,4000,200,q,DOWN,CALU1 +S 500,1500,500,2500,200,*,DOWN,ALU1 +S 500,1000,1000,1000,200,*,LEFT,ALU1 +S 500,2500,500,4000,200,*,DOWN,ALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 1500,1000,1500,4000,200,i1,DOWN,CALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 0,1000,2500,1000,1800,*,RIGHT,PWELL +S 1000,1500,1000,4000,200,*,UP,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 1300,1400,1300,2000,100,*,UP,POLY +S 1000,800,1000,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 400,400,400,1200,300,*,UP,NDIF +S 1600,400,1600,1200,300,*,UP,NDIF +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 900,2600,900,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,UP,PDIF +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 600,2800,600,4200,300,*,DOWN,PDIF +S 1900,2600,1900,3900,100,*,UP,PTRANS +S 400,2800,400,4200,300,*,DOWN,PDIF +S 1300,2050,1300,2600,100,*,DOWN,POLY +S 2200,800,2200,1200,300,*,DOWN,NDIF +S 2200,2800,2200,3700,300,*,UP,PDIF +S 1300,2000,2200,2000,100,*,RIGHT,POLY +S 2200,1000,2200,3500,200,*,UP,ALU1 +S 1500,2500,1700,2500,200,*,LEFT,ALU1 +S 1500,1500,1700,1500,200,*,LEFT,ALU1 +S 1900,1400,1900,1600,100,*,UP,POLY +S 1900,2400,1900,2600,100,*,UP,POLY +S 700,1400,700,2000,100,*,UP,POLY +S 700,2000,900,2000,100,*,RIGHT,POLY +S 900,2000,900,2600,100,*,UP,POLY +S 500,1000,500,1500,200,*,DOWN,ALU1 +S 1700,2500,1900,2500,300,*,RIGHT,POLY +S 1700,1500,1900,1500,300,*,RIGHT,POLY +S 2200,4300,2200,4800,300,*,DOWN,NTIE +V 1000,2100,CONT_POLY,* +V 1000,1000,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 2200,3000,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,4000,CONT_DIF_P,* +V 2200,4700,CONT_BODY_N,* +V 2200,3500,CONT_DIF_P,* +V 2200,1000,CONT_DIF_N,* +V 2200,2000,CONT_POLY,* +V 1700,1500,CONT_POLY,* +V 1700,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x1.vbe new file mode 100644 index 000000000..10267b443 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 3640; + CONSTANT rdown_i1_q : NATURAL := 3640; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i0_q : NATURAL := 168; + CONSTANT tphl_i0_q : NATURAL := 200; + CONSTANT tphh_i1_q : NATURAL := 285; + CONSTANT tpll_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x1; + +ARCHITECTURE behaviour_data_flow OF an12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x1" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x4.ap new file mode 100644 index 000000000..7ca39f0c8 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x4.ap @@ -0,0 +1,102 @@ +V ALLIANCE : 6 +H an12_x4,P,22/ 7/2016,100 +A 0,0,4000,5000 +R 2500,2500,ref_ref,i1_30 +R 2500,3000,ref_ref,i1_25 +R 1000,2500,ref_ref,i0_35 +R 1000,3500,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_40 +R 1000,1000,ref_ref,i0_10 +R 1000,2000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_30 +R 1000,1500,ref_ref,i0_15 +R 2500,1000,ref_ref,i1_10 +R 3000,1000,ref_ref,q_10 +R 3000,1500,ref_ref,q_15 +R 3000,2000,ref_ref,q_20 +R 3000,2500,ref_ref,q_25 +R 3000,3000,ref_ref,q_30 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 2500,4000,ref_ref,i1_40 +R 2500,3500,ref_ref,i1_35 +R 2500,2000,ref_ref,i1_20 +R 2500,1500,ref_ref,i1_15 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 2500,1000,2500,4000,200,i1,DOWN,CALU1 +S 1000,1100,1000,1200,100,*,UP,POLY +S 600,1100,1000,1100,100,*,RIGHT,POLY +S 1000,3000,1000,3100,100,*,DOWN,POLY +S 600,3100,1000,3100,100,*,RIGHT,POLY +S 1600,1400,1800,1400,100,*,RIGHT,POLY +S 1600,1400,1600,3100,100,*,DOWN,POLY +S 300,2500,1600,2500,100,*,RIGHT,POLY +S 300,1000,300,4000,200,*,DOWN,ALU1 +S 1100,3300,1100,4600,700,*,DOWN,PDIF +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,500,300,900,300,*,UP,NDIF +S 600,300,600,1100,100,*,UP,NTRANS +S 900,500,900,900,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1500,1000,1900,1000,200,*,RIGHT,ALU1 +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1600,3100,1600,4400,100,*,UP,PTRANS +S 0,1000,4000,1000,1800,*,RIGHT,PWELL +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1900,3300,1900,4200,300,*,DOWN,PDIF +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 3700,2800,3700,4700,300,*,DOWN,PDIF +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 3100,2800,3100,4700,300,*,DOWN,PDIF +S 2200,3100,2200,4400,100,*,UP,PTRANS +S 2200,100,2200,1400,100,*,DOWN,NTRANS +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 3100,300,3100,1200,300,*,UP,NDIF +S 2500,300,2500,1200,300,*,UP,NDIF +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 3700,300,3700,1200,300,*,UP,NDIF +S 2200,2400,2200,3100,100,*,DOWN,POLY +S 2200,1500,2500,1500,300,*,RIGHT,POLY +S 2200,2500,2500,2500,300,*,RIGHT,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2800,1400,2800,2600,100,*,UP,POLY +S 2000,2000,3400,2000,100,*,RIGHT,POLY +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 1900,1000,1900,4000,200,*,DOWN,ALU1 +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 3700,3000,3700,4500,200,*,DOWN,ALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3700,500,3700,1000,200,*,DOWN,ALU1 +V 1000,1200,CONT_POLY,* +V 300,2500,CONT_POLY,* +V 900,4500,CONT_DIF_P,* +V 1000,3000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 1300,4500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 3100,4000,CONT_DIF_P,* +V 3100,3500,CONT_DIF_P,* +V 3100,3000,CONT_DIF_P,* +V 1900,4000,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,4500,CONT_DIF_P,* +V 2500,4500,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 3700,500,CONT_DIF_N,* +V 3100,1000,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 2400,1500,CONT_POLY,* +V 2400,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 1900,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x4.vbe new file mode 100644 index 000000000..0d030a6cb --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/an12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphl_i0_q : NATURAL := 461; + CONSTANT tplh_i0_q : NATURAL := 471; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x4; + +ARCHITECTURE behaviour_data_flow OF an12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x4" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1100 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x2.ap new file mode 100644 index 000000000..1cb42b48c --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x2.ap @@ -0,0 +1,103 @@ +V ALLIANCE : 6 +H ao22_x2,P,22/ 7/2016,100 +A 0,0,3000,5000 +R 2500,2000,ref_ref,q_25 +R 2500,2500,ref_ref,q_20 +R 2000,3000,ref_ref,i2_25 +R 2000,2500,ref_ref,i2_30 +R 2000,1000,ref_ref,i2_10 +R 2500,1000,ref_ref,q_10 +R 2500,1500,ref_ref,q_15 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,4000,ref_ref,i2_40 +R 2000,3500,ref_ref,i2_35 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +S 1400,2100,2300,2100,100,*,RIGHT,POLY +S 2300,2600,2400,2600,100,*,RIGHT,POLY +S 2300,1400,2400,1400,100,*,RIGHT,POLY +S 2300,1400,2300,2600,100,*,UP,POLY +S 600,1400,600,2100,100,*,UP,POLY +S 200,300,1600,300,300,*,RIGHT,PTIE +S 800,4700,1600,4700,300,*,RIGHT,NTIE +S 2500,3000,2700,3000,200,*,RIGHT,ALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 900,1500,1500,1500,200,*,RIGHT,ALU1 +S 1500,1500,1500,4000,200,*,DOWN,ALU1 +S 300,1000,1500,1000,200,*,RIGHT,ALU1 +S 1000,2000,1000,4000,200,*,UP,ALU1 +S 500,2000,500,4000,200,*,UP,ALU1 +S 2500,1000,2700,1000,200,*,RIGHT,ALU1 +S 2500,4000,2700,4000,200,*,RIGHT,ALU1 +S 2500,3500,2700,3500,200,*,RIGHT,ALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 1200,1400,1200,1800,100,*,DOWN,POLY +S 900,1800,1200,1800,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 1800,2600,1800,3100,100,*,DOWN,POLY +S 1800,2600,2100,2600,100,*,LEFT,POLY +S 1000,1800,1000,2100,300,*,UP,POLY +S 600,600,600,1400,100,*,UP,NTRANS +S 1200,600,1200,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 300,800,300,1200,300,*,DOWN,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 900,800,900,1600,300,*,DOWN,NDIF +S 0,1000,3000,1000,1800,*,RIGHT,PWELL +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 2400,2600,2400,4900,100,*,DOWN,PTRANS +S 1500,3300,1500,4200,300,*,UP,PDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 300,3300,300,4600,300,*,UP,PDIF +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +V 500,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1500,2200,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 900,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 2100,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 900,1500,CONT_DIF_N,* +V 1500,4700,CONT_BODY_N,* +V 2100,4500,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x2.vbe new file mode 100644 index 000000000..7cfca61f3 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 420; + CONSTANT tpll_i2_q : NATURAL := 425; + CONSTANT tpll_i0_q : NATURAL := 447; + CONSTANT tphh_i1_q : NATURAL := 493; + CONSTANT tpll_i1_q : NATURAL := 526; + CONSTANT tphh_i0_q : NATURAL := 558; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x2; + +ARCHITECTURE behaviour_data_flow OF ao22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x4.ap new file mode 100644 index 000000000..f2197b418 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x4.ap @@ -0,0 +1,112 @@ +V ALLIANCE : 6 +H ao22_x4,P,22/ 7/2016,100 +A 0,0,4000,5000 +R 2000,3500,ref_ref,i2_25 +R 2000,2500,ref_ref,i2_35 +R 2000,1000,ref_ref,i2_10 +R 3000,1500,ref_ref,q_15 +R 3000,2000,ref_ref,q_20 +R 3000,2500,ref_ref,q_25 +R 3000,3000,ref_ref,q_30 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 3000,1000,ref_ref,q_10 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,4000,ref_ref,i2_40 +R 2000,3000,ref_ref,i2_30 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +S 600,1400,600,2000,100,*,UP,POLY +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 900,1500,1500,1500,200,*,RIGHT,ALU1 +S 1500,1500,1500,4000,200,*,DOWN,ALU1 +S 300,1000,1500,1000,200,*,RIGHT,ALU1 +S 1000,2000,1000,4000,200,*,UP,ALU1 +S 500,2000,500,4000,200,*,UP,ALU1 +S 3600,500,3600,1000,200,*,DOWN,ALU1 +S 3600,3000,3600,4500,200,*,UP,ALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 1200,1400,1200,1800,100,*,DOWN,POLY +S 900,1800,1200,1800,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 1800,2600,1800,3100,100,*,DOWN,POLY +S 1800,2600,2100,2600,100,*,LEFT,POLY +S 2700,1400,2700,2600,100,*,UP,POLY +S 1400,2100,3300,2100,100,*,RIGHT,POLY +S 1000,1800,1000,2100,300,*,UP,POLY +S 3300,1400,3300,2600,100,*,UP,POLY +S 600,600,600,1400,100,*,UP,NTRANS +S 1200,600,1200,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 300,800,300,1200,300,*,DOWN,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 3300,100,3300,1400,100,*,UP,NTRANS +S 900,800,900,1600,300,*,DOWN,NDIF +S 2700,100,2700,1400,100,*,UP,NTRANS +S 3000,300,3000,1200,300,*,DOWN,NDIF +S 3600,300,3600,1200,300,*,DOWN,NDIF +S 2400,300,2400,1200,400,*,DOWN,NDIF +S 2400,2800,2400,4700,400,*,UP,PDIF +S 1500,3300,1500,4200,300,*,UP,PDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 300,3300,300,4600,300,*,UP,PDIF +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 2700,2600,2700,4900,100,*,DOWN,PTRANS +S 3000,2800,3000,4700,300,*,UP,PDIF +S 3300,2600,3300,4900,100,*,DOWN,PTRANS +S 3600,2800,3600,4700,300,*,UP,PDIF +S 0,1000,4000,1000,1800,*,RIGHT,PWELL +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 800,4700,1600,4700,300,*,RIGHT,NTIE +S 200,300,1600,300,300,*,RIGHT,PTIE +V 500,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1500,2200,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 900,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 3600,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 3000,1000,CONT_DIF_N,* +V 2300,500,CONT_DIF_N,* +V 3600,500,CONT_DIF_N,* +V 900,1500,CONT_DIF_N,* +V 3600,3000,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 3000,4000,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 3600,4500,CONT_DIF_P,* +V 2300,4500,CONT_DIF_P,* +V 3600,4000,CONT_DIF_P,* +V 3600,3500,CONT_DIF_P,* +V 3000,3000,CONT_DIF_P,* +V 3000,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x4.vbe new file mode 100644 index 000000000..2995c9cca --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tpll_i2_q : NATURAL := 505; + CONSTANT tphh_i2_q : NATURAL := 526; + CONSTANT tpll_i0_q : NATURAL := 552; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 647; + CONSTANT tphh_i0_q : NATURAL := 674; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x4; + +ARCHITECTURE behaviour_data_flow OF ao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1300 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x2.ap new file mode 100644 index 000000000..283497474 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x2.ap @@ -0,0 +1,117 @@ +V ALLIANCE : 6 +H ao2o22_x2,P, 7/ 3/2017,100 +A 0,0,4500,5000 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2500,3000,ref_ref,i3_30 +R 2500,2500,ref_ref,i3_25 +R 2500,2000,ref_ref,i3_20 +R 2500,1500,ref_ref,i3_15 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 2000,3500,ref_ref,i2_35 +R 2500,3500,ref_ref,i3_35 +R 4000,4000,ref_ref,q_40 +R 4000,2000,ref_ref,q_20 +R 4000,3000,ref_ref,q_30 +R 4000,3500,ref_ref,q_35 +R 4000,2500,ref_ref,q_25 +R 4000,1500,ref_ref,q_15 +R 4000,1000,ref_ref,q_10 +S 600,1900,600,2100,300,*,UP,POLY +S 600,3100,700,3100,100,*,LEFT,POLY +S 600,1400,600,1900,100,*,UP,POLY +S 700,1900,700,3100,100,*,DOWN,POLY +S 800,4700,2200,4700,300,*,RIGHT,NTIE +S 200,300,1600,300,300,*,RIGHT,PTIE +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 2000,1500,2000,3500,200,i2,DOWN,CALU1 +S 2500,1500,2500,3500,200,i3,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 2700,800,2700,1200,300,*,UP,NDIF +S 1500,1500,1500,4000,200,*,UP,ALU1 +S 300,1000,2700,1000,200,*,RIGHT,ALU1 +S 900,800,900,1600,300,*,UP,NDIF +S 1000,2000,1000,4000,200,*,DOWN,ALU1 +S 500,2000,500,4000,200,*,UP,ALU1 +S 900,1500,1500,1500,200,*,RIGHT,ALU1 +S 2000,1500,2000,3500,200,*,DOWN,ALU1 +S 2500,1500,2500,3500,200,*,DOWN,ALU1 +S 300,800,300,1200,300,*,UP,NDIF +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 4000,300,4000,1200,300,*,UP,NDIF +S 3400,300,3400,1200,300,*,UP,NDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 1600,4000,3000,4000,200,*,LEFT,ALU1 +S 3000,2000,3000,4000,200,*,DOWN,ALU1 +S 3000,2000,3500,2000,200,*,RIGHT,ALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 0,1000,4500,1000,1800,*,RIGHT,PWELL +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 3500,2000,3700,2000,300,*,RIGHT,POLY +S 2400,1400,2400,2100,100,*,DOWN,POLY +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 1500,300,CONT_BODY_P,* +V 1500,4700,CONT_BODY_N,* +V 2700,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 2100,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 900,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 3500,2000,CONT_POLY,* +V 3400,500,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 3400,4500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +V 2500,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x2.vbe new file mode 100644 index 000000000..c503d1b97 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 432; + CONSTANT tpll_i0_q : NATURAL := 451; + CONSTANT tphh_i3_q : NATURAL := 488; + CONSTANT tphh_i1_q : NATURAL := 508; + CONSTANT tpll_i3_q : NATURAL := 526; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tphh_i0_q : NATURAL := 572; + CONSTANT tpll_i2_q : NATURAL := 627; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x2; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x4.ap new file mode 100644 index 000000000..4aa987558 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x4.ap @@ -0,0 +1,130 @@ +V ALLIANCE : 6 +H ao2o22_x4,P,12/ 3/2017,100 +A 0,0,5000,5000 +R 4000,1000,ref_ref,q_10 +R 4000,1500,ref_ref,q_15 +R 4000,2500,ref_ref,q_25 +R 4000,3500,ref_ref,q_35 +R 4000,3000,ref_ref,q_30 +R 4000,2000,ref_ref,q_20 +R 4000,4000,ref_ref,q_40 +R 2500,3500,ref_ref,i3_35 +R 2000,3500,ref_ref,i2_35 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 500,4000,ref_ref,i0_40 +R 500,3500,ref_ref,i0_35 +R 2500,1500,ref_ref,i3_15 +R 2500,2000,ref_ref,i3_20 +R 2500,2500,ref_ref,i3_25 +R 2500,3000,ref_ref,i3_30 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +S 600,1400,600,1900,100,*,UP,POLY +S 700,2000,700,3100,100,*,DOWN,POLY +S 2400,1400,2400,2000,100,*,DOWN,POLY +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 2500,1500,2500,3500,200,i3,DOWN,CALU1 +S 2000,1500,2000,3500,200,i2,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,1000,5000,1000,1800,*,RIGHT,PWELL +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 3000,2000,3500,2000,200,*,RIGHT,ALU1 +S 3000,2000,3000,4000,200,*,DOWN,ALU1 +S 1600,4000,3000,4000,200,*,LEFT,ALU1 +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 3400,300,3400,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 4600,300,4600,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 3500,2000,4300,2000,300,*,RIGHT,POLY +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 300,800,300,1200,300,*,UP,NDIF +S 2500,1500,2500,3500,200,*,DOWN,ALU1 +S 2000,1500,2000,3500,200,*,DOWN,ALU1 +S 900,1500,1500,1500,200,*,RIGHT,ALU1 +S 500,2000,500,4000,200,*,UP,ALU1 +S 1000,2000,1000,4000,200,*,DOWN,ALU1 +S 900,800,900,1600,300,*,UP,NDIF +S 300,1000,2700,1000,200,*,RIGHT,ALU1 +S 1500,1500,1500,4000,200,*,UP,ALU1 +S 2700,800,2700,1200,300,*,UP,NDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 800,4700,2200,4700,300,*,RIGHT,NTIE +S 200,300,1600,300,300,*,RIGHT,PTIE +S 600,1900,600,2100,300,*,UP,POLY +S 600,3100,700,3100,100,*,LEFT,POLY +V 2500,3000,CONT_POLY,* +V 4000,4000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 4600,500,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 3500,2000,CONT_POLY,* +V 300,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 900,4700,CONT_BODY_N,* +V 2100,4700,CONT_BODY_N,* +V 900,1500,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 1500,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x4.vbe new file mode 100644 index 000000000..61a5bff61 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 554; + CONSTANT tpll_i0_q : NATURAL := 569; + CONSTANT tphh_i3_q : NATURAL := 606; + CONSTANT tphh_i1_q : NATURAL := 637; + CONSTANT tpll_i3_q : NATURAL := 639; + CONSTANT tpll_i1_q : NATURAL := 666; + CONSTANT tphh_i0_q : NATURAL := 696; + CONSTANT tpll_i2_q : NATURAL := 744; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1300 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x2.ap new file mode 100644 index 000000000..2926f3fdc --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x2.ap @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H buf_x2,P,19/ 7/2016,100 +A 0,0,2000,5000 +R 1000,1000,ref_ref,i_10 +R 1000,1500,ref_ref,i_15 +R 1500,1000,ref_ref,q_10 +R 1500,2500,ref_ref,q_25 +R 1500,1500,ref_ref,q_15 +R 1500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,q_35 +R 1500,3000,ref_ref,q_30 +R 1500,2000,ref_ref,q_20 +R 1000,4000,ref_ref,i_40 +R 1000,3500,ref_ref,i_35 +R 1000,3000,ref_ref,i_30 +R 1000,2500,ref_ref,i_25 +R 1000,2000,ref_ref,i_20 +S 200,1100,200,3000,200,*,DOWN,ALU1 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 300,4200,300,4700,200,*,DOWN,ALU1 +S 600,2500,800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 300,4200,300,4700,300,*,DOWN,NTIE +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 0,1000,2000,1000,1800,*,RIGHT,PWELL +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 600,800,600,1400,100,*,DOWN,NTRANS +S 600,2600,600,3500,100,*,UP,PTRANS +S 300,2800,300,3300,300,*,DOWN,PDIF +S 300,1000,300,1200,300,*,UP,NDIF +S 300,2000,1200,2000,200,*,RIGHT,POLY +S 1600,2800,1600,4700,300,*,DOWN,PDIF +V 700,2500,CONT_POLY,* +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 800,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 300,4200,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 300,3000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1100,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x2.vbe new file mode 100644 index 000000000..e2e4c344e --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x2.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 6; + CONSTANT rdown_i_q : NATURAL := 1620; + CONSTANT rup_i_q : NATURAL := 1790; + CONSTANT tpll_i_q : NATURAL := 391; + CONSTANT tphh_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x2; + +ARCHITECTURE behaviour_data_flow OF buf_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x2" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x4.ap new file mode 100644 index 000000000..3340740dc --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x4.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H buf_x4,P,22/ 7/2016,100 +A 0,0,2500,5000 +R 1000,3000,ref_ref,i_25 +R 1000,2500,ref_ref,i_30 +R 1000,2000,ref_ref,i_20 +R 1000,3500,ref_ref,i_35 +R 1000,4000,ref_ref,i_40 +R 1500,2000,ref_ref,q_20 +R 1500,3000,ref_ref,q_30 +R 1500,3500,ref_ref,q_35 +R 1500,4000,ref_ref,q_40 +R 1500,1500,ref_ref,q_15 +R 1500,2500,ref_ref,q_25 +R 1500,1000,ref_ref,q_10 +R 1000,1500,ref_ref,i_15 +R 1000,1000,ref_ref,i_10 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 0,1000,2500,1000,1800,*,RIGHT,PWELL +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 300,2800,300,3700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 600,2600,600,3900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 300,4200,300,4700,300,*,DOWN,NTIE +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 600,2500,800,2500,300,*,RIGHT,POLY +S 300,4200,300,4700,200,*,DOWN,ALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 2100,3000,2100,4500,200,*,DOWN,ALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 2100,500,2100,1000,200,*,DOWN,ALU1 +S 300,2000,1800,2000,300,*,RIGHT,POLY +S 600,1500,800,1500,300,*,RIGHT,POLY +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 300,1000,300,3500,200,*,DOWN,ALU1 +V 2100,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 2100,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 300,4200,CONT_BODY_N,* +V 800,2500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 800,1500,CONT_POLY,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x4.vbe new file mode 100644 index 000000000..0b7726ef9 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x4.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i : NATURAL := 9; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphh_i_q : NATURAL := 379; + CONSTANT tpll_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x4; + +ARCHITECTURE behaviour_data_flow OF buf_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x4" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x8.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x8.ap new file mode 100644 index 000000000..7fd59b08f --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x8.ap @@ -0,0 +1,102 @@ +V ALLIANCE : 6 +H buf_x8,P,19/ 7/2016,100 +A 0,0,4000,5000 +R 1000,2000,ref_ref,i_20 +R 1000,2500,ref_ref,i_45 +R 1000,3000,ref_ref,i_30 +R 1000,3500,ref_ref,i_25 +R 1000,4000,ref_ref,i_40 +R 1000,1500,ref_ref,i_15 +R 1000,1000,ref_ref,i_10 +R 1500,1500,ref_ref,q_15 +R 1500,2500,ref_ref,q_25 +R 1500,1000,ref_ref,q_10 +R 1500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,q_35 +R 1500,3000,ref_ref,q_30 +R 1500,2000,ref_ref,q_20 +S 300,2100,300,2900,200,*,DOWN,ALU1 +S 300,3000,300,4000,200,*,UP,ALU1 +S 300,1000,300,2000,200,*,UP,ALU1 +S 3300,3400,3700,3400,200,*,RIGHT,ALU1 +S 3300,3400,3300,4500,200,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 2700,1000,2700,4000,200,*,UP,ALU1 +S 1500,2000,2700,2000,200,*,RIGHT,ALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 0,1000,4000,1000,1800,*,RIGHT,PWELL +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 2100,3000,2100,4500,200,*,DOWN,ALU1 +S 2100,500,2100,1000,200,*,DOWN,ALU1 +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 3300,4000,3300,4700,300,*,DOWN,PDIF +S 3700,2900,3700,3400,300,*,DOWN,NTIE +S 600,100,600,1400,100,*,DOWN,NTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 300,300,300,1200,300,*,UP,NDIF +S 3200,1700,3800,1700,300,*,RIGHT,PTIE +S 300,2000,3000,2000,300,*,RIGHT,POLY +S 600,2500,800,2500,300,*,RIGHT,POLY +S 600,1500,800,1500,300,*,RIGHT,POLY +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 3300,500,3300,1700,200,*,UP,ALU1 +S 3300,1700,3700,1700,200,*,RIGHT,ALU1 +S 3700,2900,3700,3400,200,*,DOWN,ALU1 +V 800,2500,CONT_POLY,* +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 2100,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 3300,500,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 3300,4000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 3700,2900,CONT_BODY_N,* +V 3700,3400,CONT_BODY_N,* +V 3300,1700,CONT_BODY_P,* +V 3700,1700,CONT_BODY_P,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 300,2000,CONT_POLY,* +V 800,1500,CONT_POLY,* +V 1500,1000,CONT_DIF_N,* +V 2700,3000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,1000,CONT_DIF_N,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x8.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x8.vbe new file mode 100644 index 000000000..3b2ecc3bb --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/buf_x8.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i : NATURAL := 15; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphh_i_q : NATURAL := 343; + CONSTANT tpll_i_q : NATURAL := 396; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x8; + +ARCHITECTURE behaviour_data_flow OF buf_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x8" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x1.ap new file mode 100644 index 000000000..052e8e9d1 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x1.ap @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H inv_x1,P,15/ 6/2016,100 +A 0,0,1500,5000 +R 500,4000,ref_ref,i_40 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +R 500,2500,ref_ref,i_25 +R 500,2000,ref_ref,i_20 +R 500,1500,ref_ref,i_15 +R 500,1000,ref_ref,i_10 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1000,4000,ref_ref,nq_40 +S 1100,2800,1100,3700,300,*,DOWN,PDIF +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 350,2800,350,4600,400,*,DOWN,PDIF +S 350,400,350,1200,400,*,UP,NDIF +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 0,1000,1500,1000,1800,*,RIGHT,PWELL +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 700,1400,700,2600,100,*,UP,POLY +S 400,2000,700,2000,300,*,RIGHT,POLY +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 0,300,1500,300,600,vss,RIGHT,CALU1 +S 700,600,700,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 700,2600,700,3900,100,*,UP,PTRANS +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 1000,4300,1000,4800,300,*,DOWN,NTIE +V 1000,4700,CONT_BODY_N,* +V 500,2000,CONT_POLY,* +V 1000,1000,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1000,3500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x1.vbe new file mode 100644 index 000000000..67e85e029 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x1.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_i_nq : NATURAL := 3640; + CONSTANT rup_i_nq : NATURAL := 3720; + CONSTANT tphl_i_nq : NATURAL := 101; + CONSTANT tplh_i_nq : NATURAL := 139; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x1; + +ARCHITECTURE behaviour_data_flow OF inv_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x1" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x2.ap new file mode 100644 index 000000000..861c47471 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x2.ap @@ -0,0 +1,45 @@ +V ALLIANCE : 6 +H inv_x2,P,12/ 7/2016,100 +A 0,0,1500,5000 +R 1000,4000,ref_ref,nq_40 +R 1000,3500,ref_ref,nq_35 +R 1000,3000,ref_ref,nq_30 +R 1000,2500,ref_ref,nq_25 +R 1000,2000,ref_ref,nq_20 +R 1000,1500,ref_ref,nq_15 +R 1000,1000,ref_ref,nq_10 +R 500,1000,ref_ref,i_10 +R 500,1500,ref_ref,i_15 +R 500,2000,ref_ref,i_20 +R 500,2500,ref_ref,i_25 +R 500,3000,ref_ref,i_30 +R 500,3500,ref_ref,i_35 +R 500,4000,ref_ref,i_40 +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 350,2800,350,4600,400,*,DOWN,PDIF +S 350,400,350,1700,400,*,UP,NDIF +S 0,1000,1500,1000,1800,*,RIGHT,PWELL +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 1000,800,1000,1700,300,*,UP,NDIF +S 700,600,700,1900,100,*,DOWN,NTRANS +S 700,1900,700,2600,100,*,UP,POLY +S 700,2600,700,4400,100,*,UP,PTRANS +S 400,2000,700,2000,300,*,RIGHT,POLY +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 0,300,1500,300,600,vss,RIGHT,CALU1 +S 1100,2800,1100,4200,300,*,DOWN,PDIF +S 900,4600,1200,4600,300,*,RIGHT,NTIE +V 1100,300,CONT_BODY_P,* +V 1000,1500,CONT_DIF_N,* +V 1000,3000,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 400,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 1000,4600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x2.vbe new file mode 100644 index 000000000..9df0116d3 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x2.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 12; + CONSTANT rdown_i_nq : NATURAL := 1620; + CONSTANT rup_i_nq : NATURAL := 2420; + CONSTANT tphl_i_nq : NATURAL := 69; + CONSTANT tplh_i_nq : NATURAL := 163; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x2; + +ARCHITECTURE behaviour_data_flow OF inv_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x2" + SEVERITY WARNING; + nq <= not (i) after 800 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x4.ap new file mode 100644 index 000000000..bfb117e1c --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x4.ap @@ -0,0 +1,53 @@ +V ALLIANCE : 6 +H inv_x4,P,10/ 6/2002,100 +A 0,0,2000,5000 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1000,4000,ref_ref,nq_40 +R 500,4000,ref_ref,i_40 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +R 500,2500,ref_ref,i_25 +R 500,2000,ref_ref,i_20 +R 500,1500,ref_ref,i_15 +R 500,1000,ref_ref,i_10 +S 1600,3500,1600,4500,200,*,DOWN,ALU1 +S 1600,500,1600,1000,200,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 0,3900,2000,3900,2400,*,LEFT,NWELL +S 0,1000,2000,1000,1800,*,LEFT,PWELL +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 1600,3400,1600,4700,300,*,DOWN,PDIF +S 1300,1400,1300,3200,100,*,UP,POLY +S 1300,3200,1300,4900,100,*,UP,PTRANS +S 400,300,400,1200,300,*,UP,NDIF +S 1000,300,1000,1200,300,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 1300,100,1300,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,300,*,UP,NDIF +S 500,1500,1300,1500,300,*,RIGHT,POLY +S 400,2800,400,4700,300,*,DOWN,PDIF +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 700,1400,700,2600,100,*,UP,POLY +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +V 400,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 1600,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 1600,4000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 1600,3500,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x4.vbe new file mode 100644 index 000000000..3091ae3f7 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x4.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 26; + CONSTANT rdown_i_nq : NATURAL := 810; + CONSTANT rup_i_nq : NATURAL := 1060; + CONSTANT tphl_i_nq : NATURAL := 71; + CONSTANT tplh_i_nq : NATURAL := 143; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x4; + +ARCHITECTURE behaviour_data_flow OF inv_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x4" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x8.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x8.ap new file mode 100644 index 000000000..428679a5d --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x8.ap @@ -0,0 +1,85 @@ +V ALLIANCE : 6 +H inv_x8,P,15/ 6/2016,100 +A 0,0,3500,5000 +R 500,4000,ref_ref,i_40 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +R 500,2500,ref_ref,i_25 +R 500,2000,ref_ref,i_20 +R 500,1500,ref_ref,i_15 +R 500,1000,ref_ref,i_10 +R 1000,4000,ref_ref,nq_40 +R 1000,3500,ref_ref,nq_35 +R 1000,3000,ref_ref,nq_30 +R 1000,2500,ref_ref,nq_25 +R 1000,2000,ref_ref,nq_20 +R 1000,1500,ref_ref,nq_15 +R 1000,1000,ref_ref,nq_10 +S 2800,3400,2800,4500,200,*,UP,ALU1 +S 2800,3400,3200,3400,200,*,LEFT,ALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 0,3900,3500,3900,2400,*,LEFT,NWELL +S 0,1000,3500,1000,1800,*,LEFT,PWELL +S 2800,300,2800,1200,300,*,UP,NDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 2500,1400,2500,2600,100,*,UP,POLY +S 1900,1400,1900,2600,100,*,UP,POLY +S 1300,1400,1300,2600,100,*,UP,POLY +S 700,1400,700,2600,100,*,UP,POLY +S 400,2800,400,4700,300,*,DOWN,PDIF +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,DOWN,PDIF +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 2500,2600,2500,4900,100,*,UP,PTRANS +S 2200,2800,2200,4700,300,*,DOWN,PDIF +S 1900,2600,1900,4900,100,*,UP,PTRANS +S 1300,100,1300,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,300,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 1000,300,1000,1200,300,*,UP,NDIF +S 400,300,400,1200,300,*,UP,NDIF +S 2200,300,2200,1200,300,*,UP,NDIF +S 2500,100,2500,1400,100,*,DOWN,NTRANS +S 1900,100,1900,1400,100,*,DOWN,NTRANS +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 1600,500,1600,1000,200,*,DOWN,ALU1 +S 1600,3000,1600,4500,200,*,UP,ALU1 +S 400,1500,2500,1500,300,*,RIGHT,POLY +S 2700,1700,3300,1700,300,*,RIGHT,PTIE +S 2800,3900,2800,4700,300,*,DOWN,PDIF +S 3200,2800,3200,3500,300,*,UP,NTIE +S 2200,1000,2200,4000,200,*,DOWN,ALU1 +S 1000,2000,2200,2000,200,*,LEFT,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 2800,1700,3200,1700,200,*,LEFT,ALU1 +S 2800,500,2800,1700,200,*,DOWN,ALU1 +S 3200,2900,3200,3400,200,*,UP,ALU1 +V 2800,500,CONT_DIF_N,* +V 1000,3500,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1600,4000,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 1600,3500,CONT_DIF_P,* +V 1600,3000,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 2200,4000,CONT_DIF_P,* +V 2200,3500,CONT_DIF_P,* +V 2200,3000,CONT_DIF_P,* +V 1000,1000,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 2200,1000,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 1600,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 2800,1700,CONT_BODY_P,* +V 3200,1700,CONT_BODY_P,* +V 3200,2900,CONT_BODY_N,* +V 2800,4500,CONT_DIF_P,* +V 2800,4000,CONT_DIF_P,* +V 3200,3400,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x8.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x8.vbe new file mode 100644 index 000000000..4e6fa0639 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/inv_x8.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i : NATURAL := 54; + CONSTANT rdown_i_nq : NATURAL := 400; + CONSTANT rup_i_nq : NATURAL := 450; + CONSTANT tphl_i_nq : NATURAL := 86; + CONSTANT tplh_i_nq : NATURAL := 133; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x8; + +ARCHITECTURE behaviour_data_flow OF inv_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x8" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x2.ap new file mode 100644 index 000000000..13cda9ea8 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x2.ap @@ -0,0 +1,117 @@ +V ALLIANCE : 6 +H mx2_x2,P, 9/12/2016,100 +A 0,0,4500,5000 +R 3000,4000,ref_ref,i1_40 +R 3000,3500,ref_ref,i1_35 +R 3000,3000,ref_ref,i1_30 +R 3000,2500,ref_ref,i1_25 +R 3000,2000,ref_ref,i1_20 +R 3000,1500,ref_ref,i1_15 +R 3000,1000,ref_ref,i1_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 4000,1000,ref_ref,q_10 +R 4000,3000,ref_ref,q_30 +R 4000,2000,ref_ref,q_20 +R 4000,1500,ref_ref,q_15 +R 4000,4000,ref_ref,q_40 +R 4000,3500,ref_ref,q_35 +R 4000,2500,ref_ref,q_25 +R 1500,4000,ref_ref,cmd_40 +R 1500,3500,ref_ref,cmd_35 +R 1500,3000,ref_ref,cmd_30 +R 1500,2500,ref_ref,cmd_25 +R 1500,2000,ref_ref,cmd_20 +R 1500,1500,ref_ref,cmd_15 +S 2000,2200,2000,2400,300,*,UP,POLY +S 4000,1000,4000,4000,200,*,DOWN,ALU1 +S 3500,500,3500,1000,200,*,DOWN,ALU1 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,4000,200,cmd,DOWN,CALU1 +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 300,1000,2500,1000,200,*,RIGHT,ALU1 +S 1000,1500,1000,4000,200,*,DOWN,ALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 300,1000,300,4000,200,*,DOWN,ALU1 +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 2000,1500,2000,4000,200,*,DOWN,ALU1 +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 3800,100,3800,1400,100,*,UP,NTRANS +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 3300,300,3300,1200,700,*,DOWN,NDIF +S 3300,3300,3300,4700,700,*,UP,PDIF +S 3500,3000,3500,4500,200,*,UP,ALU1 +S 2500,1000,2500,2700,200,*,UP,ALU1 +S 2400,2800,2400,3100,100,*,UP,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 0,1000,4500,1000,1800,*,RIGHT,PWELL +S 1200,100,1200,900,100,*,UP,NTRANS +S 1600,100,1600,900,100,*,UP,NTRANS +S 600,100,600,900,100,*,UP,NTRANS +S 900,300,900,700,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 600,900,600,3100,100,*,DOWN,POLY +S 2400,100,2400,900,100,*,UP,NTRANS +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1500,1500,1500,4000,200,*,UP,ALU1 +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3800,1400,3800,2600,100,*,DOWN,POLY +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3500,2800,3500,3300,300,*,DOWN,PDIF +S 2000,2200,3800,2200,100,*,RIGHT,POLY +V 3000,1500,CONT_POLY,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1000,3000,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 2000,1500,CONT_DIF_N,* +V 2000,3500,CONT_DIF_P,* +V 2000,4700,CONT_BODY_N,* +V 2000,4000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 3500,4000,CONT_DIF_P,* +V 4100,3500,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,3000,CONT_DIF_P,* +V 4100,1000,CONT_DIF_N,* +V 3500,500,CONT_DIF_N,* +V 3500,4500,CONT_DIF_P,* +V 3500,1000,CONT_DIF_N,* +V 3500,3000,CONT_DIF_P,* +V 2500,2700,CONT_POLY,* +V 2000,2400,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1600,1000,CONT_POLY,* +V 1500,4700,CONT_BODY_N,* +V 2500,4700,CONT_BODY_N,* +V 1500,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x2.vbe new file mode 100644 index 000000000..401686e9e --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x2.vbe @@ -0,0 +1,40 @@ +ENTITY mx2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_cmd_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 451; + CONSTANT tphh_i1_q : NATURAL := 451; + CONSTANT tpll_i0_q : NATURAL := 469; + CONSTANT tpll_i1_q : NATURAL := 469; + CONSTANT tphh_cmd_q : NATURAL := 484; + CONSTANT tphl_cmd_q : NATURAL := 485; + CONSTANT tpll_cmd_q : NATURAL := 522; + CONSTANT tplh_cmd_q : NATURAL := 534; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x2; + +ARCHITECTURE behaviour_data_flow OF mx2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x2" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1100 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x4.ap new file mode 100644 index 000000000..0bdf940f4 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x4.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 6 +H mx2_x4,P, 9/12/2016,100 +A 0,0,5000,5000 +R 3000,4000,ref_ref,i1_40 +R 3000,3500,ref_ref,i1_35 +R 3000,3000,ref_ref,i1_30 +R 3000,2500,ref_ref,i1_25 +R 3000,2000,ref_ref,i1_20 +R 3000,1500,ref_ref,i1_15 +R 3000,1000,ref_ref,i1_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 4000,1000,ref_ref,q_10 +R 4000,3000,ref_ref,q_30 +R 4000,2000,ref_ref,q_20 +R 4000,1500,ref_ref,q_15 +R 4000,4000,ref_ref,q_40 +R 4000,3500,ref_ref,q_35 +R 4000,2500,ref_ref,q_25 +R 1500,4000,ref_ref,cmd_40 +R 1500,3500,ref_ref,cmd_35 +R 1500,3000,ref_ref,cmd_30 +R 1500,2500,ref_ref,cmd_25 +R 1500,2000,ref_ref,cmd_20 +R 1500,1500,ref_ref,cmd_15 +S 2000,2200,2000,2400,300,*,UP,POLY +S 4000,1000,4000,4000,200,*,DOWN,ALU1 +S 4400,1400,4400,2600,100,*,DOWN,POLY +S 3800,1400,3800,2600,100,*,DOWN,POLY +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3500,2800,3500,3300,300,*,DOWN,PDIF +S 4700,2800,4700,3300,300,*,DOWN,PDIF +S 4700,2800,4700,4700,300,*,UP,PDIF +S 4400,2600,4400,4900,100,*,DOWN,PTRANS +S 4700,3000,4700,4500,200,*,UP,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,1000,5000,1000,1800,*,RIGHT,PWELL +S 4700,300,4700,1200,300,*,DOWN,NDIF +S 4400,100,4400,1400,100,*,UP,NTRANS +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 300,1000,2500,1000,200,*,RIGHT,ALU1 +S 1000,1500,1000,4000,200,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 300,1000,300,4000,200,*,DOWN,ALU1 +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 2000,1500,2000,4000,200,*,DOWN,ALU1 +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 3800,100,3800,1400,100,*,UP,NTRANS +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 3300,300,3300,1200,700,*,DOWN,NDIF +S 3300,3300,3300,4700,700,*,UP,PDIF +S 3500,3000,3500,4500,200,*,UP,ALU1 +S 2500,1000,2500,2700,200,*,UP,ALU1 +S 2400,2800,2400,3100,100,*,UP,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 1200,100,1200,900,100,*,UP,NTRANS +S 1600,100,1600,900,100,*,UP,NTRANS +S 600,100,600,900,100,*,UP,NTRANS +S 900,300,900,700,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 600,900,600,3100,100,*,DOWN,POLY +S 2400,100,2400,900,100,*,UP,NTRANS +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1500,1500,1500,4000,200,*,UP,ALU1 +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,4000,200,cmd,DOWN,CALU1 +S 4700,500,4700,1000,200,*,DOWN,ALU1 +S 3500,500,3500,1000,200,*,DOWN,ALU1 +S 2000,2200,4400,2200,100,*,RIGHT,POLY +V 4700,1000,CONT_DIF_N,* +V 4700,500,CONT_DIF_N,* +V 4700,4000,CONT_DIF_P,* +V 4700,4500,CONT_DIF_P,* +V 4700,3000,CONT_DIF_P,* +V 4700,3500,CONT_DIF_P,* +V 3000,1500,CONT_POLY,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1000,3000,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 2000,1500,CONT_DIF_N,* +V 2000,3500,CONT_DIF_P,* +V 2000,4700,CONT_BODY_N,* +V 2000,4000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 3500,4000,CONT_DIF_P,* +V 4100,3500,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,3000,CONT_DIF_P,* +V 4100,1000,CONT_DIF_N,* +V 3500,500,CONT_DIF_N,* +V 3500,4500,CONT_DIF_P,* +V 3500,1000,CONT_DIF_N,* +V 3500,3000,CONT_DIF_P,* +V 2500,2700,CONT_POLY,* +V 2000,2400,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1600,1000,CONT_POLY,* +V 1500,4700,CONT_BODY_N,* +V 2500,4700,CONT_BODY_N,* +V 1500,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x4.vbe new file mode 100644 index 000000000..ddb1f3ca7 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/mx2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY mx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 564; + CONSTANT tphh_i1_q : NATURAL := 564; + CONSTANT tphl_cmd_q : NATURAL := 574; + CONSTANT tpll_i0_q : NATURAL := 576; + CONSTANT tpll_i1_q : NATURAL := 576; + CONSTANT tphh_cmd_q : NATURAL := 615; + CONSTANT tplh_cmd_q : NATURAL := 631; + CONSTANT tpll_cmd_q : NATURAL := 647; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x4; + +ARCHITECTURE behaviour_data_flow OF mx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x4" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x1.ap new file mode 100644 index 000000000..c3032e4de --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x1.ap @@ -0,0 +1,60 @@ +V ALLIANCE : 6 +H na2_x1,P,12/ 7/2016,100 +A 0,0,2000,5000 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1000,4000,ref_ref,nq_40 +R 1500,4000,ref_ref,i1_40 +R 1500,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i1_25 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +S 1200,300,1700,300,300,*,RIGHT,PTIE +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 1500,1500,1500,4000,200,i1,DOWN,CALU1 +S 500,1000,500,4000,200,i0,DOWN,CALU1 +S 0,1000,2000,1000,1800,*,RIGHT,PWELL +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +S 400,3000,700,3000,300,*,RIGHT,POLY +S 1500,1500,1500,4000,200,*,DOWN,ALU1 +S 1600,3300,1600,4600,300,*,DOWN,PDIF +S 400,3300,400,4600,300,*,DOWN,PDIF +S 700,3100,700,4400,100,*,UP,PTRANS +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 1300,2000,1600,2000,300,*,RIGHT,POLY +S 1300,1900,1300,3100,100,*,DOWN,POLY +S 700,600,700,1900,100,*,DOWN,NTRANS +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 700,1900,700,3100,100,*,UP,POLY +S 1100,1900,1600,1900,100,*,RIGHT,POLY +S 1000,1000,1400,1000,200,*,RIGHT,ALU1 +S 1400,800,1400,1700,300,*,UP,NDIF +S 400,400,400,1700,300,*,UP,NDIF +S 1000,1000,1000,4000,200,*,UP,ALU1 +V 1000,4600,CONT_BODY_N,* +V 500,3000,CONT_POLY,* +V 1600,4500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1500,2000,CONT_POLY,* +V 400,500,CONT_DIF_N,* +V 1400,1000,CONT_DIF_N,* +V 1250,300,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x1.vbe new file mode 100644 index 000000000..486b6aaf0 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 59; + CONSTANT tphl_i1_nq : NATURAL := 111; + CONSTANT tplh_i1_nq : NATURAL := 234; + CONSTANT tplh_i0_nq : NATURAL := 288; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x1; + +ARCHITECTURE behaviour_data_flow OF na2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x1" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 900 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x4.ap new file mode 100644 index 000000000..39b06ef39 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x4.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H na2_x4,P, 9/12/2016,100 +A 0,0,3500,5000 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 2000,3500,ref_ref,nq_35 +R 2000,3000,ref_ref,nq_30 +R 2000,2500,ref_ref,nq_25 +R 2000,2000,ref_ref,nq_20 +R 2000,1500,ref_ref,nq_15 +R 2000,1000,ref_ref,nq_10 +S 1000,3000,1200,3000,300,*,LEFT,POLY +S 300,4000,300,4500,200,*,UP,ALU1 +S 2000,1000,2000,3500,200,*,DOWN,ALU1 +S 1400,300,1400,1700,300,*,UP,NDIF +S 600,600,600,1900,100,*,DOWN,NTRANS +S 900,800,900,1700,300,*,UP,NDIF +S 300,800,300,1700,300,*,UP,NDIF +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 2400,1900,2400,2600,100,*,DOWN,POLY +S 2300,1400,2300,1900,100,*,DOWN,POLY +S 1700,1400,1700,2100,100,*,UP,POLY +S 1700,2000,2600,2000,300,*,RIGHT,POLY +S 2500,2000,3200,2000,200,*,LEFT,ALU1 +S 2700,4300,2700,4700,300,*,UP,PDIF +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 300,3300,300,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 850,3700,850,4200,200,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 3200,1000,3200,3500,200,*,DOWN,ALU1 +S 900,4000,3000,4000,200,*,RIGHT,ALU1 +S 500,1500,500,3500,200,*,UP,ALU1 +S 1000,1500,1000,3500,200,*,UP,ALU1 +S 300,1000,1500,1000,200,*,RIGHT,ALU1 +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 3200,2800,3200,3700,300,*,UP,PDIF +S 2900,2600,2900,3900,100,*,UP,PTRANS +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 3200,800,3200,1200,300,*,DOWN,NDIF +S 2900,600,2900,1400,100,*,DOWN,NTRANS +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 2600,300,2600,1200,300,*,UP,NDIF +S 2300,100,2300,1400,100,*,DOWN,NTRANS +S 2000,300,2000,1200,300,*,UP,NDIF +S 1700,100,1700,1400,100,*,DOWN,NTRANS +S 300,300,900,300,300,*,LEFT,PTIE +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 0,1000,3500,1000,1800,*,RIGHT,PWELL +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 2000,1000,2000,3500,200,nq,DOWN,CALU1 +S 1200,2900,1200,3100,100,*,DOWN,POLY +S 1700,1900,1700,2600,100,*,DOWN,POLY +S 1700,2600,1800,2600,100,*,RIGHT,POLY +V 300,4000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 2500,2000,CONT_POLY,* +V 900,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 3200,3500,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 800,300,CONT_BODY_P,* +V 3200,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 2600,500,CONT_DIF_N,* +V 1400,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 300,300,CONT_BODY_P,* +V 500,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x4.vbe new file mode 100644 index 000000000..c73eca058 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 353; + CONSTANT tphl_i0_nq : NATURAL := 412; + CONSTANT tplh_i0_nq : NATURAL := 552; + CONSTANT tplh_i1_nq : NATURAL := 601; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x4; + +ARCHITECTURE behaviour_data_flow OF na2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x4" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x1.ap new file mode 100644 index 000000000..e70d0c57a --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x1.ap @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H na3_x1,P, 9/12/2016,100 +A 0,0,2500,5000 +R 2000,4000,ref_ref,nq_40 +R 2000,3500,ref_ref,nq_35 +R 2000,2500,ref_ref,nq_25 +R 2000,3000,ref_ref,nq_30 +R 2000,2000,ref_ref,nq_20 +R 2000,1500,ref_ref,nq_15 +R 2000,1000,ref_ref,nq_10 +R 500,4000,ref_ref,i0_40 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 1500,3500,ref_ref,i2_35 +R 1500,3000,ref_ref,i2_30 +R 1500,2500,ref_ref,i2_25 +R 1500,2000,ref_ref,i2_20 +R 1500,1500,ref_ref,i2_15 +R 1500,1000,ref_ref,i2_10 +S 1500,2900,1900,2900,100,*,LEFT,POLY +S 1000,4000,2200,4000,200,*,RIGHT,ALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 0,1000,2500,1000,1800,*,RIGHT,PWELL +S 1700,900,1700,1200,300,*,DOWN,NDIF +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 800,300,800,1200,300,*,UP,NDIF +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,UP,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,200,*,UP,NDIF +S 1900,800,1900,1200,500,*,UP,NDIF +S 2200,3300,2200,4200,300,*,DOWN,PDIF +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 400,3300,400,4600,300,*,DOWN,PDIF +S 1600,3300,1600,4600,300,*,DOWN,PDIF +S 1900,3100,1900,4400,100,*,UP,PTRANS +S 700,3100,700,4400,100,*,UP,PTRANS +S 400,3000,700,3000,300,*,RIGHT,POLY +S 2000,4000,2200,4000,200,*,RIGHT,ALU1 +S 2000,1000,2000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +S 1100,3100,1300,3100,100,*,RIGHT,POLY +S 1900,2900,1900,3100,100,*,DOWN,POLY +V 300,500,CONT_DIF_N,* +V 1500,1500,CONT_POLY,* +V 2000,1000,CONT_DIF_N,* +V 2200,4000,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 500,3000,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1500,2800,CONT_POLY,* +V 1000,1500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x1.vbe new file mode 100644 index 000000000..d51e12075 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 4120; + CONSTANT rdown_i1_nq : NATURAL := 4120; + CONSTANT rdown_i2_nq : NATURAL := 4120; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 119; + CONSTANT tphl_i1_nq : NATURAL := 171; + CONSTANT tphl_i2_nq : NATURAL := 193; + CONSTANT tplh_i2_nq : NATURAL := 265; + CONSTANT tplh_i1_nq : NATURAL := 316; + CONSTANT tplh_i0_nq : NATURAL := 363; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x1; + +ARCHITECTURE behaviour_data_flow OF na3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x4.ap new file mode 100644 index 000000000..9010ce6ae --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x4.ap @@ -0,0 +1,104 @@ +V ALLIANCE : 6 +H na3_x4,P, 9/12/2016,100 +A 0,0,4000,5000 +R 1500,3000,ref_ref,i1_30 +R 1500,3500,ref_ref,i1_35 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 1500,2500,ref_ref,i1_25 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 2500,1000,ref_ref,nq_10 +R 2500,1500,ref_ref,nq_15 +R 2500,2000,ref_ref,nq_20 +R 2500,2500,ref_ref,nq_25 +R 2500,3000,ref_ref,nq_30 +R 2500,3500,ref_ref,nq_35 +R 1000,3500,ref_ref,i2_35 +R 1000,3000,ref_ref,i2_30 +R 1000,2500,ref_ref,i2_25 +R 1000,2000,ref_ref,i2_20 +R 1000,1500,ref_ref,i2_15 +S 1000,2900,1200,2900,300,*,LEFT,POLY +S 2200,2600,2300,2600,100,*,RIGHT,POLY +S 2200,1900,2200,2600,100,*,DOWN,POLY +S 1400,3000,1800,3000,100,*,RIGHT,POLY +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1500,1500,1500,3500,200,i1,DOWN,CALU1 +S 2500,1000,2500,3500,200,nq,DOWN,CALU1 +S 1000,1500,1000,3500,200,i2,DOWN,CALU1 +S 0,1000,4000,1000,1800,*,RIGHT,PWELL +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 900,3200,900,4600,300,*,DOWN,PDIF +S 300,3200,300,4100,300,*,DOWN,PDIF +S 1800,3000,1800,4300,100,*,UP,PTRANS +S 1500,3200,1500,4100,300,*,DOWN,PDIF +S 1200,3000,1200,4300,100,*,UP,PTRANS +S 600,3000,600,4300,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 500,1500,500,3500,200,*,UP,ALU1 +S 400,2000,700,2000,300,*,RIGHT,POLY +S 300,4000,3500,4000,200,*,RIGHT,ALU1 +S 400,1000,2000,1000,200,*,RIGHT,ALU1 +S 400,800,400,1700,300,*,UP,NDIF +S 1800,300,1800,1700,300,*,UP,NDIF +S 1500,600,1500,1900,100,*,DOWN,NTRANS +S 700,600,700,1900,100,*,DOWN,NTRANS +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 3700,800,3700,1200,300,*,DOWN,NDIF +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 1900,300,1900,1700,300,*,UP,NDIF +S 2200,100,2200,1400,100,*,DOWN,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 3100,300,3100,1200,300,*,UP,NDIF +S 3400,600,3400,1400,100,*,DOWN,NTRANS +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,DOWN,PDIF +S 3400,2600,3400,3900,100,*,UP,PTRANS +S 3700,2800,3700,3700,300,*,UP,PDIF +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2200,2000,3100,2000,300,*,RIGHT,POLY +S 2200,1400,2200,2100,100,*,UP,POLY +S 2800,1400,2800,1900,100,*,DOWN,POLY +S 2900,1900,2900,2600,100,*,DOWN,POLY +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 3000,2000,3700,2000,200,*,LEFT,ALU1 +S 1500,1500,1500,3500,200,*,UP,ALU1 +S 1000,1500,1000,3500,200,*,UP,ALU1 +S 3700,1000,3700,3500,200,*,DOWN,ALU1 +S 2500,1000,2500,3500,200,*,DOWN,ALU1 +S 200,300,1200,300,300,*,RIGHT,PTIE +S 1200,2800,1200,3000,100,*,DOWN,POLY +V 1000,2000,CONT_POLY,* +V 300,300,CONT_BODY_P,* +V 900,4500,CONT_DIF_P,* +V 3200,4600,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 400,1000,CONT_DIF_N,* +V 1900,500,CONT_DIF_N,* +V 3100,500,CONT_DIF_N,* +V 2500,1000,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 3700,3000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 2600,3000,CONT_DIF_P,* +V 2600,3500,CONT_DIF_P,* +V 3500,4000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 2000,4600,CONT_DIF_P,* +V 700,300,CONT_BODY_P,* +V 1100,300,CONT_BODY_P,* +V 1000,2900,CONT_POLY,* +V 1500,2900,CONT_POLY,* +V 500,2900,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x4.vbe new file mode 100644 index 000000000..160a97f61 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 460; + CONSTANT tphl_i2_nq : NATURAL := 519; + CONSTANT tphl_i0_nq : NATURAL := 556; + CONSTANT tplh_i0_nq : NATURAL := 601; + CONSTANT tplh_i2_nq : NATURAL := 647; + CONSTANT tplh_i1_nq : NATURAL := 691; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x4; + +ARCHITECTURE behaviour_data_flow OF na3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x1.ap new file mode 100644 index 000000000..dab374a71 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x1.ap @@ -0,0 +1,88 @@ +V ALLIANCE : 6 +H na4_x1,P, 9/12/2016,100 +A 0,0,3000,5000 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,1000,ref_ref,i0_10 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1500,3500,ref_ref,i2_35 +R 1500,3000,ref_ref,i2_30 +R 1500,2500,ref_ref,i2_25 +R 1500,2000,ref_ref,i2_20 +R 1500,1500,ref_ref,i2_15 +R 1500,1000,ref_ref,i2_10 +R 2000,1000,ref_ref,i3_10 +R 2000,1500,ref_ref,i3_15 +R 2000,2000,ref_ref,i3_20 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2000,3500,ref_ref,i3_35 +R 2500,3500,ref_ref,nq_35 +R 2500,3000,ref_ref,nq_30 +R 2500,2000,ref_ref,nq_20 +R 2500,1000,ref_ref,nq_10 +R 2500,4000,ref_ref,nq_40 +R 2500,1500,ref_ref,nq_25 +R 2500,2500,ref_ref,nq_15 +S 1800,1500,2000,1500,300,*,LEFT,POLY +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +S 2000,1000,2000,3500,200,i3,DOWN,CALU1 +S 2500,1000,2500,4000,200,nq,DOWN,CALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 0,1000,3000,1000,1800,*,RIGHT,PWELL +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 900,3300,900,4200,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 600,3100,600,4400,100,*,UP,PTRANS +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 1500,3300,1500,4600,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 500,1000,500,3500,200,*,DOWN,ALU1 +S 1000,1000,1000,3500,200,*,DOWN,ALU1 +S 1500,1000,1500,3500,200,*,DOWN,ALU1 +S 2000,1000,2000,3500,200,*,DOWN,ALU1 +S 2300,800,2300,1200,700,*,UP,NDIF +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 1800,1400,1800,1900,100,*,UP,POLY +S 1800,1900,2400,1900,100,*,RIGHT,POLY +S 2400,1900,2400,3100,100,*,UP,POLY +S 2500,1000,2500,4000,200,*,UP,ALU1 +S 900,4000,2500,4000,200,*,LEFT,ALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +S 1400,3100,1800,3100,100,*,RIGHT,POLY +V 300,500,CONT_DIF_N,* +V 1500,4500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2500,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 500,3000,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1500,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x1.vbe new file mode 100644 index 000000000..07f51ce0b --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 5400; + CONSTANT rdown_i1_nq : NATURAL := 5400; + CONSTANT rdown_i2_nq : NATURAL := 5400; + CONSTANT rdown_i3_nq : NATURAL := 5400; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT rup_i3_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 179; + CONSTANT tphl_i1_nq : NATURAL := 237; + CONSTANT tphl_i2_nq : NATURAL := 269; + CONSTANT tphl_i3_nq : NATURAL := 282; + CONSTANT tplh_i3_nq : NATURAL := 302; + CONSTANT tplh_i2_nq : NATURAL := 350; + CONSTANT tplh_i1_nq : NATURAL := 395; + CONSTANT tplh_i0_nq : NATURAL := 438; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x1; + +ARCHITECTURE behaviour_data_flow OF na4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x4.ap new file mode 100644 index 000000000..6f534e959 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x4.ap @@ -0,0 +1,123 @@ +V ALLIANCE : 6 +H na4_x4,P,22/ 7/2016,100 +A 0,0,5000,5000 +R 1500,1000,ref_ref,nq_10 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 3500,1500,ref_ref,i2_15 +R 3500,1000,ref_ref,i2_10 +R 4000,1000,ref_ref,i3_10 +R 4000,1500,ref_ref,i3_15 +R 4000,2000,ref_ref,i3_20 +R 4000,2500,ref_ref,i3_25 +R 4000,3000,ref_ref,i3_30 +R 4000,3500,ref_ref,i3_35 +R 3000,2000,ref_ref,i1_20 +R 3000,2500,ref_ref,i1_25 +R 3000,3000,ref_ref,i1_30 +R 3000,3500,ref_ref,i1_35 +R 3500,3500,ref_ref,i2_35 +R 3500,3000,ref_ref,i2_30 +R 3500,2500,ref_ref,i2_25 +R 3500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i0_15 +R 2500,2000,ref_ref,i0_20 +R 2500,2500,ref_ref,i0_25 +R 2500,3000,ref_ref,i0_30 +R 2500,3500,ref_ref,i0_35 +R 2500,1000,ref_ref,i0_10 +R 3000,1000,ref_ref,i1_10 +R 3000,1500,ref_ref,i1_15 +S 3600,3100,3800,3100,100,*,RIGHT,POLY +S 300,4300,300,4800,300,*,DOWN,NTIE +S 300,3000,300,3500,200,*,DOWN,ALU1 +S 4500,1000,4500,4000,200,*,UP,ALU1 +S 4400,1900,4400,3100,100,*,UP,POLY +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 2300,3300,2300,4700,300,*,DOWN,PDIF +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 300,1000,300,3000,200,*,DOWN,ALU1 +S 600,2500,800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,2600,600,3900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,DOWN,PDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 3800,100,3800,1400,100,*,DOWN,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 4300,800,4300,1200,700,*,UP,NDIF +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2600,100,2600,1400,100,*,DOWN,NTRANS +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2600,3100,2600,4400,100,*,UP,PTRANS +S 4700,3300,4700,4600,300,*,DOWN,PDIF +S 3500,3300,3500,4600,300,*,DOWN,PDIF +S 4100,3300,4100,4200,300,*,DOWN,PDIF +S 2900,3300,2900,4200,300,*,DOWN,PDIF +S 3200,3100,3200,4400,100,*,UP,PTRANS +S 3800,3100,3800,4400,100,*,UP,PTRANS +S 4400,3100,4400,4400,100,*,UP,PTRANS +S 3000,3100,3200,3100,100,*,RIGHT,POLY +S 3800,1400,3800,1900,100,*,UP,POLY +S 3800,1900,4400,1900,100,*,RIGHT,POLY +S 2500,1000,2500,3500,200,*,DOWN,ALU1 +S 3000,1000,3000,3500,200,*,DOWN,ALU1 +S 3500,1000,3500,3500,200,*,DOWN,ALU1 +S 4000,1000,4000,3500,200,*,DOWN,ALU1 +S 0,1000,5000,1000,1800,*,RIGHT,PWELL +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 1500,1000,1500,3500,200,*,UP,ALU1 +S 1000,1500,1000,4000,200,*,DOWN,ALU1 +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 600,2000,1800,2000,300,*,RIGHT,POLY +S 1000,4000,4500,4000,200,*,LEFT,ALU1 +S 1500,1000,1500,3500,200,nq,DOWN,CALU1 +S 3500,1000,3500,3500,200,i2,DOWN,CALU1 +S 4000,1000,4000,3500,200,i3,DOWN,CALU1 +S 3000,1000,3000,3500,200,i1,DOWN,CALU1 +S 2500,1000,2500,3500,200,i0,DOWN,CALU1 +S 300,2000,500,2000,200,*,LEFT,ALU1 +V 3500,3000,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 2500,3000,CONT_POLY,* +V 300,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 2200,500,CONT_DIF_N,* +V 2200,4500,CONT_DIF_P,* +V 800,1500,CONT_POLY,* +V 800,2500,CONT_POLY,* +V 300,4700,CONT_BODY_N,* +V 300,3000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 4500,1000,CONT_DIF_N,* +V 2900,4000,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 3500,4500,CONT_DIF_P,* +V 4700,4500,CONT_DIF_P,* +V 4000,2000,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x4.vbe new file mode 100644 index 000000000..a67d18901 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/na4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 578; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i3_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 681; + CONSTANT tplh_i2_nq : NATURAL := 689; + CONSTANT tphl_i3_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 731; + CONSTANT tplh_i0_nq : NATURAL := 771; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x4; + +ARCHITECTURE behaviour_data_flow OF na4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x1.ap new file mode 100644 index 000000000..8536602dc --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x1.ap @@ -0,0 +1,85 @@ +V ALLIANCE : 6 +H nao22_x1,P, 9/12/2016,100 +A 0,0,3000,5000 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,4000,ref_ref,i0_40 +R 500,3500,ref_ref,i0_35 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 1500,4000,ref_ref,nq_40 +R 2000,4000,ref_ref,i2_40 +R 2000,1000,ref_ref,i2_10 +R 500,2500,ref_ref,i0_20 +R 500,2000,ref_ref,i0_25 +S 300,2500,600,2500,300,*,RIGHT,POLY +S 1500,1600,1500,4000,200,nq,DOWN,CALU1 +S 1500,1500,1500,4000,200,*,UP,ALU1 +S 900,1500,1500,1500,200,*,RIGHT,ALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 900,300,900,1600,300,*,UP,NDIF +S 1000,2000,1000,4000,200,*,DOWN,ALU1 +S 500,2000,500,4000,200,*,UP,ALU1 +S 300,1000,1500,1000,200,*,RIGHT,ALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 0,1000,3000,1000,1800,*,RIGHT,PWELL +S 2700,2900,2700,4500,200,*,DOWN,ALU1 +S 2700,500,2700,1700,200,*,DOWN,ALU1 +S 2000,1000,2000,4000,200,*,DOWN,ALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 2700,4300,2700,4800,300,*,DOWN,NTIE +S 2700,2800,2700,3300,300,*,UP,NTIE +S 2700,1300,2700,1800,300,*,DOWN,PTIE +S 2700,200,2700,700,300,*,UP,PTIE +S 300,1500,300,2600,100,*,DOWN,POLY +S 300,1500,600,1500,100,*,RIGHT,POLY +S 600,1400,600,1500,100,*,DOWN,POLY +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 2700,1700,CONT_BODY_P,* +V 2700,2900,CONT_BODY_N,* +V 2700,4700,CONT_BODY_N,* +V 2700,300,CONT_BODY_P,* +V 500,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x1.vbe new file mode 100644 index 000000000..13c4e6dec --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 1790; + CONSTANT tphl_i2_nq : NATURAL := 165; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tplh_i2_nq : NATURAL := 238; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x1; + +ARCHITECTURE behaviour_data_flow OF nao22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 900 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x4.ap new file mode 100644 index 000000000..42b26df0f --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x4.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 6 +H nao22_x4,P, 2/ 8/2016,100 +A 0,0,5000,5000 +R 4000,4000,ref_ref,nq_40 +R 500,4000,ref_ref,i2_40 +R 500,3500,ref_ref,i2_35 +R 1500,3500,ref_ref,i1_35 +R 2000,3500,ref_ref,i0_35 +R 500,2000,ref_ref,i2_20 +R 1500,2000,ref_ref,i1_20 +R 1500,2500,ref_ref,i1_25 +R 1500,3000,ref_ref,i1_30 +R 2000,3000,ref_ref,i0_30 +R 2000,2500,ref_ref,i0_25 +R 2000,2000,ref_ref,i0_20 +R 4000,2500,ref_ref,nq_25 +R 4000,1500,ref_ref,nq_15 +R 4000,1000,ref_ref,nq_10 +R 4000,2000,ref_ref,nq_20 +R 4000,3000,ref_ref,nq_30 +R 4000,3500,ref_ref,nq_35 +R 500,3000,ref_ref,i2_30 +R 500,2500,ref_ref,i2_25 +R 500,1500,ref_ref,i2_15 +R 500,1000,ref_ref,i2_10 +S 2000,2000,2000,3500,200,*,DOWN,ALU1 +S 2000,2000,2000,3500,200,i0,DOWN,CALU1 +S 2000,2000,2200,2000,200,*,RIGHT,ALU1 +S 2200,1500,2200,1900,200,*,DOWN,ALU1 +S 1900,1400,2100,1400,100,*,RIGHT,POLY +S 900,300,2900,300,300,*,RIGHT,PTIE +S 900,4700,1700,4700,300,*,RIGHT,NTIE +S 1500,2000,1500,3500,200,i1,DOWN,CALU1 +S 4000,1000,4000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i2,DOWN,CALU1 +S 2800,2000,2800,3000,200,*,UP,ALU1 +S 2800,1000,3500,1000,200,*,LEFT,ALU1 +S 3500,1000,3500,2000,200,*,DOWN,ALU1 +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 1900,3100,1900,4400,100,*,UP,PTRANS +S 700,3100,700,4400,100,*,UP,PTRANS +S 2200,3300,2200,4600,300,*,DOWN,PDIF +S 1600,3300,1600,4200,300,*,DOWN,PDIF +S 400,3300,400,4600,300,*,DOWN,PDIF +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,1000,5000,1000,1800,*,RIGHT,PWELL +S 2800,2800,2800,3700,300,*,DOWN,PDIF +S 3100,2600,3100,3900,100,*,UP,PTRANS +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 2200,800,2200,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 2800,800,2800,1200,300,*,UP,NDIF +S 3100,600,3100,1400,100,*,DOWN,NTRANS +S 4600,300,4600,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 3400,300,3400,1200,300,*,UP,NDIF +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 1300,1400,1300,3100,100,*,DOWN,POLY +S 700,1400,700,3100,100,*,DOWN,POLY +S 3100,1400,3100,2600,100,*,DOWN,POLY +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 3100,2500,3300,2500,300,*,RIGHT,POLY +S 3500,2000,4300,2000,300,*,RIGHT,POLY +S 1300,2000,1500,2000,300,*,RIGHT,POLY +S 500,2000,700,2000,300,*,RIGHT,POLY +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 1000,1000,2200,1000,200,*,RIGHT,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 1000,1500,1000,4000,200,*,UP,ALU1 +S 2800,3500,3300,3500,200,*,LEFT,ALU1 +S 2800,3500,2800,4000,200,*,UP,ALU1 +S 1100,4000,2800,4000,200,*,LEFT,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3300,2500,3300,3500,200,*,DOWN,ALU1 +S 2800,2000,3500,2000,200,*,RIGHT,ALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 400,400,400,1200,300,*,UP,NDIF +S 1600,800,1600,1600,300,*,UP,NDIF +S 1500,2000,1500,3500,200,*,DOWN,ALU1 +S 1000,1500,1600,1500,200,*,RIGHT,ALU1 +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 2800,4300,2800,4800,300,*,DOWN,NTIE +V 2200,1500,CONT_POLY,* +V 4000,4000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 2200,4500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1600,4700,CONT_BODY_N,* +V 400,4500,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 2800,3000,CONT_DIF_P,* +V 2800,4700,CONT_BODY_N,* +V 1000,4700,CONT_BODY_N,* +V 3400,4000,CONT_DIF_P,* +V 4600,1000,CONT_DIF_N,* +V 2200,1000,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 4600,500,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 2800,300,CONT_BODY_P,* +V 1000,300,CONT_BODY_P,* +V 2200,300,CONT_BODY_P,* +V 3300,2500,CONT_POLY,* +V 3500,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 1600,300,CONT_BODY_P,* +V 400,500,CONT_DIF_N,* +V 1600,1500,CONT_DIF_N,* +V 2000,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x4.vbe new file mode 100644 index 000000000..ebdcfc515 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 596; + CONSTANT tplh_i2_nq : NATURAL := 636; + CONSTANT tplh_i0_nq : NATURAL := 650; + CONSTANT tphl_i1_nq : NATURAL := 664; + CONSTANT tplh_i1_nq : NATURAL := 723; + CONSTANT tphl_i0_nq : NATURAL := 732; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x4; + +ARCHITECTURE behaviour_data_flow OF nao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x1.ap new file mode 100644 index 000000000..8f5a0d8fe --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x1.ap @@ -0,0 +1,95 @@ +V ALLIANCE : 6 +H nao2o22_x1,P, 9/12/2016,100 +A 0,0,3500,5000 +R 2500,2000,ref_ref,i2_25 +R 2500,2500,ref_ref,i2_20 +R 500,2500,ref_ref,i0_20 +R 500,2000,ref_ref,i0_25 +R 2500,4000,ref_ref,i2_40 +R 2000,4000,ref_ref,i3_40 +R 1500,4000,ref_ref,nq_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,1500,ref_ref,i3_15 +R 2000,2000,ref_ref,i3_20 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2000,3500,ref_ref,i3_35 +R 2500,3500,ref_ref,i2_35 +R 2500,3000,ref_ref,i2_30 +R 2500,1500,ref_ref,i2_15 +R 1500,1500,ref_ref,nq_15 +R 1500,2000,ref_ref,nq_20 +R 1500,2500,ref_ref,nq_25 +R 1500,3000,ref_ref,nq_30 +R 1500,3500,ref_ref,nq_35 +S 200,2500,600,2500,300,*,LEFT,POLY +S 600,2400,600,2600,100,*,DOWN,POLY +S 200,1400,600,1400,100,*,RIGHT,POLY +S 200,1400,200,2600,100,*,DOWN,POLY +S 2400,2600,2700,2600,100,*,RIGHT,POLY +S 2700,1400,2700,2600,100,*,DOWN,POLY +S 1500,1500,1500,4000,200,*,UP,ALU1 +S 900,1500,1500,1500,200,*,RIGHT,ALU1 +S 2500,1500,2500,4000,200,*,DOWN,ALU1 +S 2000,1500,2000,4000,200,*,DOWN,ALU1 +S 300,1000,2700,1000,200,*,RIGHT,ALU1 +S 500,2000,500,4000,200,*,UP,ALU1 +S 1000,2000,1000,4000,200,*,DOWN,ALU1 +S 900,300,900,1600,300,*,UP,NDIF +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 3200,2900,3200,4500,200,*,DOWN,ALU1 +S 0,1000,3500,1000,1800,*,RIGHT,PWELL +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 2500,1500,2500,4000,200,i2,DOWN,CALU1 +S 2000,1500,2000,4000,200,i3,DOWN,CALU1 +S 1500,1500,1500,4000,200,nq,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 2700,3700,2700,4700,300,*,DOWN,PDIF +S 2600,2800,2600,3700,300,*,UP,PDIF +S 3200,2800,3200,3300,300,*,DOWN,NTIE +S 2400,1500,2700,1500,300,*,LEFT,POLY +V 400,2500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 1500,3000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 3200,2900,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x1.vbe new file mode 100644 index 000000000..327e99763 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i3_nq : NATURAL := 174; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tphl_i2_nq : NATURAL := 237; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT tplh_i2_nq : NATURAL := 307; + CONSTANT tplh_i3_nq : NATURAL := 382; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x1; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x4.ap new file mode 100644 index 000000000..b1a5d31ae --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x4.ap @@ -0,0 +1,150 @@ +V ALLIANCE : 6 +H nao2o22_x4,P, 9/12/2016,100 +A 0,0,5500,5000 +R 4500,2500,ref_ref,nq_25 +R 4500,1500,ref_ref,nq_15 +R 4500,1000,ref_ref,nq_10 +R 4500,2000,ref_ref,nq_20 +R 4500,3000,ref_ref,nq_30 +R 4500,3500,ref_ref,nq_35 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,1500,ref_ref,i3_15 +R 2000,2000,ref_ref,i3_20 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 4500,4000,ref_ref,nq_40 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 2000,3500,ref_ref,i3_35 +R 2500,3500,ref_ref,i2_35 +S 1000,3000,1200,3000,300,*,LEFT,POLY +S 3300,4300,3300,4800,300,*,DOWN,NTIE +S 4500,1000,4500,4000,200,nq,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 2000,1500,2000,3500,200,i3,DOWN,CALU1 +S 2500,1500,2500,3500,200,i2,DOWN,CALU1 +S 4500,1000,4500,4000,200,*,UP,ALU1 +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 0,1000,5500,1000,1800,*,RIGHT,PWELL +S 3300,1000,3300,3000,200,*,DOWN,ALU1 +S 3300,800,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,3700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 5100,300,5100,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 3900,300,3900,1200,300,*,UP,NDIF +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 3800,2500,3800,3500,200,*,DOWN,ALU1 +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 3300,2000,4000,2000,200,*,RIGHT,ALU1 +S 3600,2500,3800,2500,300,*,RIGHT,POLY +S 3900,4000,3900,4500,200,*,DOWN,ALU1 +S 5100,3000,5100,4500,200,*,DOWN,ALU1 +S 5100,500,5100,1000,200,*,DOWN,ALU1 +S 3900,500,3900,1000,200,*,DOWN,ALU1 +S 4000,2000,4800,2000,300,*,RIGHT,POLY +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 2700,800,2700,1200,300,*,UP,NDIF +S 1500,1500,1500,4000,200,*,UP,ALU1 +S 300,1000,2700,1000,200,*,RIGHT,ALU1 +S 900,800,900,1600,300,*,UP,NDIF +S 1000,2000,1000,4000,200,*,DOWN,ALU1 +S 500,2000,500,4000,200,*,UP,ALU1 +S 900,1500,1500,1500,200,*,RIGHT,ALU1 +S 2000,1500,2000,3500,200,*,DOWN,ALU1 +S 2500,1500,2500,3500,200,*,DOWN,ALU1 +S 3300,3500,3800,3500,200,*,LEFT,ALU1 +S 3300,3500,3300,4000,200,*,UP,ALU1 +S 1600,4000,3300,4000,200,*,LEFT,ALU1 +S 300,800,300,1200,300,*,UP,NDIF +S 900,4700,2100,4700,300,*,RIGHT,NTIE +S 300,300,1500,300,300,*,RIGHT,PTIE +S 2700,300,3300,300,300,*,RIGHT,PTIE +S 600,1400,600,2000,100,*,DOWN,POLY +S 1200,1400,1200,2100,100,*,DOWN,POLY +S 2400,1400,2400,2100,100,*,DOWN,POLY +S 1200,2900,1200,3100,100,*,DOWN,POLY +V 4500,1000,CONT_DIF_N,* +V 3300,300,CONT_BODY_P,* +V 5100,500,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3800,2500,CONT_POLY,* +V 3900,4000,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 3300,3000,CONT_DIF_P,* +V 3300,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 4000,2000,CONT_POLY,* +V 3300,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 1500,4700,CONT_BODY_N,* +V 2700,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 2100,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 2700,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 4500,3000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 500,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 2500,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x4.vbe new file mode 100644 index 000000000..b5c506fee --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i3_nq : NATURAL := 607; + CONSTANT tplh_i0_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 664; + CONSTANT tphl_i1_nq : NATURAL := 666; + CONSTANT tplh_i1_nq : NATURAL := 717; + CONSTANT tplh_i2_nq : NATURAL := 721; + CONSTANT tphl_i0_nq : NATURAL := 734; + CONSTANT tplh_i3_nq : NATURAL := 807; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1400 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x1.ap new file mode 100644 index 000000000..64c8a3de7 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x1.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 6 +H nmx2_x1,P, 9/12/2016,100 +A 0,0,3500,5000 +R 2000,1000,ref_ref,nq_10 +R 2000,2000,ref_ref,nq_20 +R 2000,2500,ref_ref,nq_25 +R 2000,3000,ref_ref,nq_30 +R 2000,3500,ref_ref,nq_35 +R 3000,4000,ref_ref,i1_40 +R 3000,3500,ref_ref,i1_35 +R 3000,3000,ref_ref,i1_30 +R 3000,1500,ref_ref,i1_15 +R 3000,1000,ref_ref,i1_10 +R 1000,3500,ref_ref,i0_35 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1500,3500,ref_ref,cmd_35 +R 1500,3000,ref_ref,cmd_30 +R 1500,2500,ref_ref,cmd_25 +R 1500,2000,ref_ref,cmd_20 +R 1000,3000,ref_ref,i0_25 +R 1000,2500,ref_ref,i0_30 +R 3000,2000,ref_ref,i1_25 +R 3000,2500,ref_ref,i1_20 +S 1500,2000,1700,2000,300,*,LEFT,POLY +S 1500,1500,1700,1500,300,*,LEFT,POLY +S 2000,1000,2000,3500,200,nq,DOWN,CALU1 +S 1700,1400,1700,1500,100,1,DOWN,POLY +S 2000,1000,2000,2000,200,*,UP,ALU1 +S 2000,1000,2000,1000,200,nq,LEFT,CALU1 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 1000,1500,1000,3500,200,i0,DOWN,CALU1 +S 1500,2000,1500,3500,200,cmd,DOWN,CALU1 +S 2600,300,2600,1200,200,*,DOWN,NDIF +S 2600,2800,2600,4700,200,*,UP,PDIF +S 2300,2600,2500,2600,100,*,RIGHT,POLY +S 2300,2600,2300,4900,100,*,DOWN,PTRANS +S 600,2000,2300,2000,100,*,RIGHT,POLY +S 2300,1400,2300,2000,100,*,DOWN,POLY +S 2300,100,2300,1400,100,*,UP,NTRANS +S 1700,100,1700,1400,100,*,UP,NTRANS +S 1700,2000,1700,2600,100,*,UP,POLY +S 1700,2600,1700,4900,100,*,DOWN,PTRANS +S 300,1000,1500,1000,200,*,RIGHT,ALU1 +S 1500,1000,1500,1500,200,*,UP,ALU1 +S 2000,300,2000,1200,500,*,DOWN,NDIF +S 2500,2500,2500,4000,200,*,DOWN,ALU1 +S 300,4000,2500,4000,200,*,RIGHT,ALU1 +S 3200,300,3200,1200,300,*,UP,NDIF +S 2900,100,2900,1400,100,*,UP,NTRANS +S 2900,2600,2900,4900,100,*,DOWN,PTRANS +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 1000,1500,1000,3500,200,*,DOWN,ALU1 +S 1500,2000,1500,3500,200,*,UP,ALU1 +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 2000,2800,2000,4700,500,*,DOWN,PDIF +S 900,2600,1200,2600,100,*,RIGHT,POLY +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 0,1000,3500,1000,1800,*,RIGHT,PWELL +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 300,800,300,1200,300,*,UP,NDIF +S 600,1400,600,3100,100,*,DOWN,POLY +S 600,600,600,1400,100,*,UP,NTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 300,1000,300,4000,200,*,DOWN,ALU1 +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 2000,2000,2000,3500,200,*,DOWN,ALU1 +V 1500,1500,CONT_POLY,* +V 2000,1000,CONT_DIF_N,* +V 3200,500,CONT_DIF_N,* +V 2500,2500,CONT_POLY,* +V 3200,4500,CONT_DIF_P,* +V 2000,3000,CONT_DIF_P,* +V 3000,2500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 900,500,CONT_DIF_N,* +V 3000,1500,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 2000,3500,CONT_DIF_P,* +V 1500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x1.vbe new file mode 100644 index 000000000..3f0ab6425 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x1.vbe @@ -0,0 +1,40 @@ +ENTITY nmx2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_cmd : NATURAL := 21; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 217; + CONSTANT tphl_i1_nq : NATURAL := 217; + CONSTANT tphl_cmd_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 256; + CONSTANT tplh_i1_nq : NATURAL := 256; + CONSTANT tplh_cmd_nq : NATURAL := 287; + CONSTANT tphh_cmd_nq : NATURAL := 379; + CONSTANT tpll_cmd_nq : NATURAL := 410; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x1; + +ARCHITECTURE behaviour_data_flow OF nmx2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x1" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x4.ap new file mode 100644 index 000000000..91f0f8555 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x4.ap @@ -0,0 +1,145 @@ +V ALLIANCE : 6 +H nmx2_x4,P, 9/12/2016,100 +A 0,0,6000,5000 +R 3000,4000,ref_ref,i1_40 +R 3000,3500,ref_ref,i1_35 +R 3000,3000,ref_ref,i1_30 +R 3000,2500,ref_ref,i1_25 +R 3000,2000,ref_ref,i1_20 +R 3000,1500,ref_ref,i1_15 +R 3000,1000,ref_ref,i1_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1500,4000,ref_ref,cmd_40 +R 1500,3500,ref_ref,cmd_35 +R 1500,3000,ref_ref,cmd_30 +R 1500,2500,ref_ref,cmd_25 +R 1500,2000,ref_ref,cmd_20 +R 1500,1500,ref_ref,cmd_15 +R 5000,4000,ref_ref,nq_40 +R 5000,3500,ref_ref,nq_35 +R 5000,2500,ref_ref,nq_25 +R 5000,1000,ref_ref,nq_10 +R 5000,3000,ref_ref,nq_30 +R 5000,2000,ref_ref,nq_20 +R 5000,1500,ref_ref,nq_15 +S 2000,2200,2000,2400,300,*,UP,POLY +S 4400,500,4400,1000,200,*,DOWN,ALU1 +S 5600,500,5600,1000,200,*,DOWN,ALU1 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 1500,1500,1500,4000,200,cmd,DOWN,CALU1 +S 5000,1000,5000,4000,200,nq,DOWN,CALU1 +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 300,1000,2500,1000,200,*,RIGHT,ALU1 +S 1000,1500,1000,4000,200,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 300,1000,300,4000,200,*,DOWN,ALU1 +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 2000,1500,2000,4000,200,*,DOWN,ALU1 +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 2500,1000,2500,2700,200,*,UP,ALU1 +S 2400,2800,2400,3100,100,*,UP,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 1200,100,1200,900,100,*,UP,NTRANS +S 1600,100,1600,900,100,*,UP,NTRANS +S 600,100,600,900,100,*,UP,NTRANS +S 900,300,900,700,300,*,UP,NDIF +S 600,900,600,3100,100,*,DOWN,POLY +S 2400,100,2400,900,100,*,UP,NTRANS +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1500,1500,1500,4000,200,*,UP,ALU1 +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,1000,6000,1000,1800,*,RIGHT,PWELL +S 3400,100,3400,900,100,*,UP,NTRANS +S 3100,300,3100,700,300,*,DOWN,NDIF +S 3700,300,3700,1100,300,*,DOWN,NDIF +S 300,300,300,1100,300,*,UP,NDIF +S 3400,3100,3400,4400,100,*,DOWN,PTRANS +S 3700,3300,3700,4200,300,*,DOWN,PDIF +S 3100,3300,3100,4600,300,*,DOWN,PDIF +S 3700,1000,3700,4000,200,*,DOWN,ALU1 +S 3400,900,3400,3100,100,*,DOWN,POLY +S 5600,3000,5600,4500,200,*,UP,ALU1 +S 4400,3000,4400,4500,200,*,UP,ALU1 +S 5600,2900,5600,3300,300,*,DOWN,PDIF +S 4700,100,4700,1400,100,*,UP,NTRANS +S 5000,300,5000,1200,300,*,DOWN,NDIF +S 5300,100,5300,1400,100,*,UP,NTRANS +S 5600,300,5600,1200,300,*,DOWN,NDIF +S 4400,300,4400,1200,300,*,DOWN,NDIF +S 4700,1400,4700,2600,100,*,DOWN,POLY +S 4700,2600,4700,4900,100,*,DOWN,PTRANS +S 5300,1400,5300,2600,100,*,DOWN,POLY +S 5300,2600,5300,4900,100,*,DOWN,PTRANS +S 4400,2800,4400,4700,300,*,UP,PDIF +S 5600,2800,5600,4700,300,*,UP,PDIF +S 5000,2800,5000,4700,300,*,UP,PDIF +S 3800,2200,5300,2200,100,*,LEFT,POLY +S 2000,2200,3400,2200,100,*,RIGHT,POLY +V 3000,1500,CONT_POLY,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1000,3000,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 2000,1500,CONT_DIF_N,* +V 2000,3500,CONT_DIF_P,* +V 2000,4700,CONT_BODY_N,* +V 2000,4000,CONT_DIF_P,* +V 2500,2700,CONT_POLY,* +V 2000,2400,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1600,1000,CONT_POLY,* +V 1500,4700,CONT_BODY_N,* +V 2500,4700,CONT_BODY_N,* +V 3100,500,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 3100,4500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,3400,CONT_DIF_P,* +V 4400,3000,CONT_DIF_P,* +V 4400,4500,CONT_DIF_P,* +V 5600,3000,CONT_DIF_P,* +V 5600,4500,CONT_DIF_P,* +V 5600,4000,CONT_DIF_P,* +V 5000,3000,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 5000,3500,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 4400,3500,CONT_DIF_P,* +V 5600,3500,CONT_DIF_P,* +V 4400,1000,CONT_DIF_N,* +V 4400,500,CONT_DIF_N,* +V 5600,500,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +V 5000,1000,CONT_DIF_N,* +V 1500,3000,CONT_POLY,* +V 3800,2200,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x4.vbe new file mode 100644 index 000000000..436a6b355 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nmx2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY nmx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_cmd_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 610; + CONSTANT tphl_cmd_nq : NATURAL := 632; + CONSTANT tplh_i0_nq : NATURAL := 653; + CONSTANT tplh_i1_nq : NATURAL := 653; + CONSTANT tphh_cmd_nq : NATURAL := 688; + CONSTANT tpll_cmd_nq : NATURAL := 703; + CONSTANT tplh_cmd_nq : NATURAL := 708; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x4; + +ARCHITECTURE behaviour_data_flow OF nmx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x4" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1300 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x1.ap new file mode 100644 index 000000000..f95a0c34c --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x1.ap @@ -0,0 +1,60 @@ +V ALLIANCE : 6 +H no2_x1,P, 9/12/2016,100 +A 0,0,2000,5000 +R 1500,1000,ref_ref,i0_10 +R 500,1000,ref_ref,nq_10 +R 500,4000,ref_ref,nq_40 +R 500,3500,ref_ref,nq_35 +R 500,3000,ref_ref,nq_30 +R 500,2500,ref_ref,nq_25 +R 500,2000,ref_ref,nq_20 +R 500,1500,ref_ref,nq_15 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 1500,4000,ref_ref,i0_40 +R 1000,2000,ref_ref,i1_25 +R 1000,2500,ref_ref,i1_20 +R 1500,2000,ref_ref,i0_25 +R 1500,2500,ref_ref,i0_20 +S 1300,1500,1500,1500,300,*,LEFT,POLY +S 400,2800,400,4200,300,*,DOWN,PDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1600,400,1600,1200,300,*,UP,NDIF +S 400,400,400,1200,300,*,UP,NDIF +S 700,1400,700,2400,100,*,DOWN,POLY +S 700,2400,1000,2400,100,*,LEFT,POLY +S 1700,2800,1700,4700,300,*,UP,PDIF +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +S 0,1000,2000,1000,1800,*,RIGHT,PWELL +S 1500,1000,1500,4000,200,i0,DOWN,CALU1 +S 500,1000,500,4000,200,nq,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 500,1000,1000,1000,200,*,LEFT,ALU1 +S 1300,1400,1300,1600,100,*,UP,POLY +V 1000,2500,CONT_POLY,* +V 1600,500,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 1700,4500,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 1500,1500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x1.vbe new file mode 100644 index 000000000..37a91f3f6 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tplh_i0_nq : NATURAL := 121; + CONSTANT tplh_i1_nq : NATURAL := 161; + CONSTANT tphl_i1_nq : NATURAL := 193; + CONSTANT tphl_i0_nq : NATURAL := 298; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x1; + +ARCHITECTURE behaviour_data_flow OF no2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x1" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 900 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x4.ap new file mode 100644 index 000000000..be7b0fa24 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x4.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H no2_x4,P, 9/12/2016,100 +A 0,0,3500,5000 +R 2000,1500,ref_ref,nq_15 +R 2000,2000,ref_ref,nq_20 +R 2000,2500,ref_ref,nq_25 +R 2000,3000,ref_ref,nq_30 +R 2000,3500,ref_ref,nq_35 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,1500,ref_ref,i0_15 +R 500,1500,ref_ref,i1_15 +R 500,3000,ref_ref,i1_30 +R 500,3500,ref_ref,i1_35 +R 2000,1000,ref_ref,nq_10 +R 500,2000,ref_ref,i1_25 +R 1000,2000,ref_ref,i0_25 +S 1000,1500,1200,1500,300,*,LEFT,POLY +S 3200,4300,3200,4800,300,*,DOWN,NTIE +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 0,1000,3500,1000,1800,*,RIGHT,PWELL +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,100,2400,1400,100,*,UP,NTRANS +S 3200,1000,3200,3000,200,*,UP,ALU1 +S 1400,2800,1400,4700,300,*,UP,PDIF +S 2900,2600,2900,3900,100,*,DOWN,PTRANS +S 2600,2800,2600,4700,300,*,UP,PDIF +S 2000,2800,2000,4700,300,*,UP,PDIF +S 1700,2600,1700,4900,100,*,DOWN,PTRANS +S 2300,2600,2300,4900,100,*,DOWN,PTRANS +S 3200,2800,3200,3700,300,*,UP,PDIF +S 3200,800,3200,1200,300,*,DOWN,NDIF +S 2900,600,2900,1400,100,*,UP,NTRANS +S 2600,300,2600,1200,300,*,DOWN,NDIF +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 1000,1500,1000,3500,200,*,UP,ALU1 +S 500,1500,500,3500,200,*,UP,ALU1 +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 2700,2500,2700,4000,200,*,DOWN,ALU1 +S 2400,1400,2400,2100,100,*,UP,POLY +S 2300,1900,2300,2600,100,*,DOWN,POLY +S 1700,1900,1700,2600,100,*,UP,POLY +S 1800,1400,1800,2100,100,*,DOWN,POLY +S 1700,2000,2600,2000,300,*,RIGHT,POLY +S 2600,2500,2900,2500,300,*,RIGHT,POLY +S 2500,2000,3200,2000,200,*,RIGHT,ALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 300,2800,300,4700,300,*,DOWN,PDIF +S 300,4000,2700,4000,200,*,RIGHT,ALU1 +S 600,2600,600,4900,100,*,UP,PTRANS +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 1300,2800,1300,4700,300,*,DOWN,PDIF +S 300,400,300,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,1000,1500,1000,200,*,LEFT,ALU1 +S 1500,300,1500,1200,300,*,UP,NDIF +S 3200,3000,3200,3500,200,*,DOWN,ALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 1000,1500,1000,3500,200,i0,DOWN,CALU1 +S 500,1500,500,3500,200,i1,DOWN,CALU1 +S 2000,1000,2000,3500,200,*,DOWN,ALU1 +S 2000,1100,2000,3500,200,nq,DOWN,CALU1 +S 1200,1400,1200,1600,100,*,UP,POLY +V 2000,3500,CONT_DIF_P,* +V 2000,3000,CONT_DIF_P,* +V 2700,300,CONT_DIF_N,* +V 2700,2500,CONT_POLY,* +V 3200,4700,CONT_BODY_N,* +V 3200,3000,CONT_DIF_P,* +V 2600,4500,CONT_DIF_P,* +V 1400,4500,CONT_DIF_P,* +V 3200,1000,CONT_DIF_N,* +V 1000,2500,CONT_POLY,* +V 2100,1000,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 1500,400,CONT_DIF_N,* +V 3200,3500,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x4.vbe new file mode 100644 index 000000000..5060db0e8 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tplh_i0_nq : NATURAL := 447; + CONSTANT tplh_i1_nq : NATURAL := 504; + CONSTANT tphl_i1_nq : NATURAL := 522; + CONSTANT tphl_i0_nq : NATURAL := 618; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x4; + +ARCHITECTURE behaviour_data_flow OF no2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x4" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x1.ap new file mode 100644 index 000000000..0e471c6d0 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x1.ap @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H no3_x1,P,22/ 7/2016,100 +A 0,0,2500,5000 +R 2000,2000,ref_ref,i2_25 +R 1500,2000,ref_ref,i0_25 +R 1000,2000,ref_ref,i1_25 +R 500,1000,ref_ref,nq_10 +R 2000,4000,ref_ref,i2_40 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,1500,ref_ref,i2_15 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 500,1500,ref_ref,nq_15 +R 500,2000,ref_ref,nq_20 +R 500,2500,ref_ref,nq_25 +R 500,3000,ref_ref,nq_30 +R 500,3500,ref_ref,nq_35 +R 500,4000,ref_ref,nq_40 +R 2000,1000,ref_ref,i2_10 +S 600,1400,600,2300,100,*,DOWN,POLY +S 600,2300,1100,2300,100,*,LEFT,POLY +S 1000,2500,1000,2600,100,*,DOWN,POLY +S 1400,2500,1400,2600,100,*,DOWN,POLY +S 1200,1400,1200,1600,100,*,DOWN,POLY +S 1200,1600,1600,1600,100,*,LEFT,POLY +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 300,1000,1500,1000,200,*,LEFT,ALU1 +S 0,1000,2500,1000,1800,*,RIGHT,PWELL +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,400,900,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 300,1000,500,1000,200,*,RIGHT,ALU1 +S 500,1000,500,4000,200,nq,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 400,2800,400,4200,300,*,DOWN,PDIF +V 1000,2400,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 500,4000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x1.vbe new file mode 100644 index 000000000..6711f8b1f --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT tplh_i2_nq : NATURAL := 192; + CONSTANT tphl_i1_nq : NATURAL := 215; + CONSTANT tplh_i1_nq : NATURAL := 243; + CONSTANT tplh_i0_nq : NATURAL := 246; + CONSTANT tphl_i0_nq : NATURAL := 318; + CONSTANT tphl_i2_nq : NATURAL := 407; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x1; + +ARCHITECTURE behaviour_data_flow OF no3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x4.ap new file mode 100644 index 000000000..7de751e4d --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x4.ap @@ -0,0 +1,97 @@ +V ALLIANCE : 6 +H no3_x4,P,22/ 7/2016,100 +A 0,0,4000,5000 +R 1500,2000,ref_ref,i0_25 +R 1000,2000,ref_ref,i1_25 +R 500,2000,ref_ref,i2_25 +R 2500,1000,ref_ref,nq_10 +R 500,3500,ref_ref,i2_35 +R 500,1500,ref_ref,i2_15 +R 500,3000,ref_ref,i2_30 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 2500,3500,ref_ref,nq_35 +R 2500,3000,ref_ref,nq_30 +R 2500,2500,ref_ref,nq_25 +R 2500,2000,ref_ref,nq_20 +R 2500,1500,ref_ref,nq_15 +S 1400,1400,1800,1400,100,*,LEFT,POLY +S 3700,4300,3700,4800,300,*,DOWN,NTIE +S 3000,2000,3700,2000,200,*,RIGHT,ALU1 +S 3100,2500,3400,2500,300,*,RIGHT,POLY +S 2200,2000,3100,2000,300,*,RIGHT,POLY +S 2300,1400,2300,2100,100,*,DOWN,POLY +S 2200,1900,2200,2600,100,*,UP,POLY +S 2800,1900,2800,2600,100,*,DOWN,POLY +S 2900,1400,2900,2100,100,*,UP,POLY +S 3200,2500,3200,4000,200,*,DOWN,ALU1 +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2600,300,2600,1200,300,*,DOWN,NDIF +S 300,1000,2000,1000,200,*,LEFT,ALU1 +S 300,4000,3200,4000,200,*,RIGHT,ALU1 +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 500,1500,500,3500,200,*,UP,ALU1 +S 1000,1500,1000,3500,200,*,UP,ALU1 +S 1500,1500,1500,3500,200,*,UP,ALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 1700,2800,1700,4700,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 900,400,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 3100,300,3100,1200,300,*,DOWN,NDIF +S 3400,600,3400,1400,100,*,UP,NTRANS +S 3700,800,3700,1200,300,*,DOWN,NDIF +S 3700,2800,3700,3700,300,*,UP,PDIF +S 2800,2600,2800,4900,100,*,DOWN,PTRANS +S 2200,2600,2200,4900,100,*,DOWN,PTRANS +S 2500,2800,2500,4700,300,*,UP,PDIF +S 3100,2800,3100,4700,300,*,UP,PDIF +S 3400,2600,3400,3900,100,*,DOWN,PTRANS +S 1900,2800,1900,4700,300,*,UP,PDIF +S 3700,1000,3700,3000,200,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 2900,100,2900,1400,100,*,UP,NTRANS +S 2300,100,2300,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 0,1000,4000,1000,1800,*,RIGHT,PWELL +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 500,1500,500,3500,200,i2,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 2500,1100,2500,3500,200,nq,DOWN,CALU1 +S 2500,1000,2500,3500,200,*,DOWN,ALU1 +V 1500,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 2600,1000,CONT_DIF_N,* +V 1500,2500,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 1900,4500,CONT_DIF_P,* +V 3100,4500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 3700,4700,CONT_BODY_N,* +V 3200,2500,CONT_POLY,* +V 3200,300,CONT_DIF_N,* +V 2000,300,CONT_DIF_N,* +V 2500,3000,CONT_DIF_P,* +V 2500,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x4.vbe new file mode 100644 index 000000000..52e3d602b --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 545; + CONSTANT tplh_i0_nq : NATURAL := 561; + CONSTANT tplh_i1_nq : NATURAL := 623; + CONSTANT tphl_i1_nq : NATURAL := 638; + CONSTANT tplh_i2_nq : NATURAL := 640; + CONSTANT tphl_i0_nq : NATURAL := 722; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x4; + +ARCHITECTURE behaviour_data_flow OF no3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x1.ap new file mode 100644 index 000000000..736655e4f --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x1.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H no4_x1,P,22/ 7/2016,100 +A 0,0,3000,5000 +R 1000,2000,ref_ref,i1_25 +R 2500,2000,ref_ref,i3_25 +R 2000,2000,ref_ref,i2_25 +R 1500,2000,ref_ref,i0_25 +R 2000,4000,ref_ref,i2_40 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,1500,ref_ref,i2_15 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 2500,4000,ref_ref,i3_40 +R 2500,3500,ref_ref,i3_35 +R 2500,3000,ref_ref,i3_30 +R 2500,1500,ref_ref,i3_15 +R 500,4000,ref_ref,nq_40 +R 500,1500,ref_ref,nq_15 +R 500,2000,ref_ref,nq_20 +R 500,2500,ref_ref,nq_25 +R 500,3000,ref_ref,nq_30 +R 500,3500,ref_ref,nq_35 +R 500,1000,ref_ref,nq_10 +S 600,1400,600,1600,100,*,DOWN,POLY +S 600,1600,1100,1600,100,*,LEFT,POLY +S 2000,2400,2000,2600,100,*,DOWN,POLY +S 1900,2600,2000,2600,100,*,RIGHT,POLY +S 1200,1400,1600,1400,100,*,LEFT,POLY +S 500,1000,800,1000,200,*,LEFT,ALU1 +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 500,1100,500,4000,200,nq,DOWN,CALU1 +S 2000,1500,2000,4000,200,i2,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 2500,1500,2500,4000,200,i3,DOWN,CALU1 +S 800,1000,2100,1000,200,*,LEFT,ALU1 +S 0,1000,3000,1000,1800,*,RIGHT,PWELL +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2000,1500,2000,4000,200,*,UP,ALU1 +S 1500,1500,1500,4000,200,*,UP,ALU1 +S 1000,1500,1000,4000,200,*,UP,ALU1 +S 300,400,300,1200,300,*,UP,NDIF +S 1500,400,1500,1200,300,*,UP,NDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2500,1500,2500,4000,200,*,UP,ALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 400,2800,400,4200,300,*,DOWN,PDIF +S 2600,2800,2600,4700,300,*,DOWN,PDIF +V 1000,1700,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 2000,2300,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 500,4000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 2500,4500,CONT_DIF_P,* +V 2700,500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x1.vbe new file mode 100644 index 000000000..5d15a3cd4 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rdown_i3_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT tphl_i1_nq : NATURAL := 230; + CONSTANT tplh_i3_nq : NATURAL := 271; + CONSTANT tplh_i1_nq : NATURAL := 320; + CONSTANT tphl_i0_nq : NATURAL := 330; + CONSTANT tplh_i2_nq : NATURAL := 333; + CONSTANT tplh_i0_nq : NATURAL := 340; + CONSTANT tphl_i2_nq : NATURAL := 419; + CONSTANT tphl_i3_nq : NATURAL := 499; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x1; + +ARCHITECTURE behaviour_data_flow OF no4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x1" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1100 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x4.ap new file mode 100644 index 000000000..aa5e8da77 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x4.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H no4_x4,P,22/ 7/2016,100 +A 0,0,5000,5000 +R 2500,3000,ref_ref,i3_25 +R 2000,3000,ref_ref,i2_25 +R 1500,1500,ref_ref,i0_25 +R 1000,1500,ref_ref,i1_25 +R 2000,4000,ref_ref,i2_40 +R 2000,3500,ref_ref,i2_35 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2000,ref_ref,i0_20 +R 1000,2000,ref_ref,i1_20 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 2500,4000,ref_ref,i3_40 +R 2500,3500,ref_ref,i3_35 +R 2500,2000,ref_ref,i3_20 +R 2500,1500,ref_ref,i3_15 +R 3500,3500,ref_ref,nq_35 +R 3500,4000,ref_ref,nq_40 +R 3500,1500,ref_ref,nq_15 +R 3500,2000,ref_ref,nq_20 +R 3500,2500,ref_ref,nq_25 +R 3500,3000,ref_ref,nq_30 +S 2000,1500,2000,4000,200,i2,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 2500,1500,2500,4000,200,i3,DOWN,CALU1 +S 3500,1500,3500,4000,200,nq,DOWN,CALU1 +S 3500,1500,3500,4000,200,*,DOWN,ALU1 +S 0,1000,5000,1000,1800,*,RIGHT,PWELL +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 600,2400,1100,2400,100,*,LEFT,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2000,1500,2000,4000,200,*,UP,ALU1 +S 1500,1500,1500,4000,200,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1000,1500,1000,4000,200,*,UP,ALU1 +S 300,400,300,1200,300,*,UP,NDIF +S 1500,400,1500,1200,300,*,UP,NDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2500,1500,2500,4000,200,*,UP,ALU1 +S 4000,2500,4200,2500,200,*,RIGHT,ALU1 +S 2900,300,2900,1200,300,*,DOWN,NDIF +S 3200,100,3200,1400,100,*,UP,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 3800,100,3800,1400,100,*,UP,NTRANS +S 4400,600,4400,1400,100,*,UP,NTRANS +S 4700,800,4700,1200,300,*,DOWN,NDIF +S 4700,2800,4700,3700,300,*,UP,PDIF +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 3200,2600,3200,4900,100,*,DOWN,PTRANS +S 3500,2800,3500,4700,300,*,UP,PDIF +S 4100,2800,4100,4700,300,*,UP,PDIF +S 4400,2600,4400,3900,100,*,DOWN,PTRANS +S 2900,2800,2900,4700,300,*,UP,PDIF +S 3200,1400,3200,2600,100,*,UP,POLY +S 3800,1400,3800,2600,100,*,UP,POLY +S 4200,2500,4400,2500,300,*,RIGHT,POLY +S 4700,1000,4700,3000,200,*,UP,ALU1 +S 3200,2000,4700,2000,300,*,RIGHT,POLY +S 4200,1500,4400,1500,300,*,RIGHT,POLY +S 4000,1500,4200,1500,200,*,RIGHT,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 2800,2800,2800,4700,400,*,UP,PDIF +S 2700,300,2700,1200,300,*,UP,NDIF +S 4000,1000,4000,2500,200,*,UP,ALU1 +S 3500,300,3500,1600,300,*,DOWN,NDIF +S 4100,3000,4100,4500,200,*,DOWN,ALU1 +S 500,1000,500,3000,200,*,DOWN,ALU1 +S 500,3000,500,4000,200,*,UP,ALU1 +S 500,1000,4000,1000,200,*,LEFT,ALU1 +S 500,1000,900,1000,200,*,LEFT,ALU1 +S 4700,3000,4700,3500,200,*,DOWN,ALU1 +S 4700,4300,4700,4800,300,*,DOWN,NTIE +V 1500,2000,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 4700,1000,CONT_DIF_N,* +V 4100,500,CONT_DIF_N,* +V 4100,4500,CONT_DIF_P,* +V 4700,3000,CONT_DIF_P,* +V 4700,4700,CONT_BODY_N,* +V 4200,2500,CONT_POLY,* +V 4700,2000,CONT_POLY,* +V 4200,1500,CONT_POLY,* +V 2800,500,CONT_DIF_N,* +V 3500,4000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 3500,3000,CONT_DIF_P,* +V 3500,1500,CONT_DIF_N,* +V 500,3000,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,3500,CONT_DIF_P,* +V 4100,3000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 2500,4500,CONT_DIF_P,* +V 2900,4500,CONT_DIF_P,* +V 4700,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x4.vbe new file mode 100644 index 000000000..cffb179c4 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/no4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 564; + CONSTANT tphl_i0_nq : NATURAL := 656; + CONSTANT tplh_i3_nq : NATURAL := 693; + CONSTANT tphl_i2_nq : NATURAL := 739; + CONSTANT tplh_i2_nq : NATURAL := 761; + CONSTANT tplh_i1_nq : NATURAL := 768; + CONSTANT tplh_i0_nq : NATURAL := 777; + CONSTANT tphl_i3_nq : NATURAL := 816; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x4; + +ARCHITECTURE behaviour_data_flow OF no4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x4" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x1.ap new file mode 100644 index 000000000..a259afcaf --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x1.ap @@ -0,0 +1,82 @@ +V ALLIANCE : 6 +H noa22_x1,P,22/ 7/2016,100 +A 0,0,3000,5000 +R 500,2000,ref_ref,i0_25 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 1500,1000,ref_ref,nq_10 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 2000,1000,ref_ref,i2_10 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +R 2000,4000,ref_ref,i2_40 +S 1500,1000,1500,3500,200,*,UP,ALU1 +S 300,3500,300,4000,200,*,UP,ALU1 +S 900,3500,1500,3500,200,*,RIGHT,ALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1000,1000,1000,3000,200,*,DOWN,ALU1 +S 500,1000,500,3000,200,*,UP,ALU1 +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 300,4000,1500,4000,200,*,RIGHT,ALU1 +S 2000,1000,2000,4000,200,*,DOWN,ALU1 +S 2700,2900,2700,4500,200,*,DOWN,ALU1 +S 2700,500,2700,1700,200,*,DOWN,ALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,1000,3000,1000,1800,*,LEFT,PWELL +S 0,3900,3000,3900,2400,*,LEFT,NWELL +S 1500,1000,1500,3500,200,nq,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 2700,4300,2700,4800,300,*,DOWN,NTIE +S 2700,2800,2700,3300,300,*,UP,NTIE +S 2700,1300,2700,1800,300,*,DOWN,PTIE +S 2700,200,2700,700,300,*,UP,PTIE +V 500,2500,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 300,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 2700,1700,CONT_BODY_P,* +V 2700,2900,CONT_BODY_N,* +V 2700,4700,CONT_BODY_N,* +V 2700,300,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x1.vbe new file mode 100644 index 000000000..5c13864f3 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 1620; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tphl_i2_nq : NATURAL := 218; + CONSTANT tplh_i2_nq : NATURAL := 241; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x1; + +ARCHITECTURE behaviour_data_flow OF noa22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 900 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x4.ap new file mode 100644 index 000000000..853f0059b --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x4.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H noa22_x4,P,22/ 7/2016,100 +A 0,0,5000,5000 +R 500,4000,ref_ref,i2_40 +R 500,3500,ref_ref,i2_35 +R 4000,3500,ref_ref,nq_35 +R 4000,3000,ref_ref,nq_30 +R 4000,2000,ref_ref,nq_20 +R 4000,1000,ref_ref,nq_10 +R 4000,1500,ref_ref,nq_15 +R 4000,2500,ref_ref,nq_25 +R 500,1000,ref_ref,i2_10 +R 500,1500,ref_ref,i2_15 +R 500,2000,ref_ref,i2_20 +R 500,2500,ref_ref,i2_25 +R 500,3000,ref_ref,i2_30 +R 2000,2000,ref_ref,i0_20 +R 2000,2500,ref_ref,i0_25 +R 2000,3000,ref_ref,i0_30 +R 1500,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i1_25 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 1500,1000,ref_ref,i1_10 +R 4000,4000,ref_ref,nq_40 +R 2000,1000,ref_ref,i0_10 +R 2000,1500,ref_ref,i0_15 +S 500,1000,500,4000,200,i2,DOWN,CALU1 +S 1500,1000,1500,3000,200,i1,DOWN,CALU1 +S 4000,1000,4000,4000,200,nq,DOWN,CALU1 +S 2000,1000,2000,3000,200,i0,DOWN,CALU1 +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 400,3300,400,4600,300,*,DOWN,PDIF +S 1600,3300,1600,4200,300,*,DOWN,PDIF +S 1000,3500,3300,3500,200,*,RIGHT,ALU1 +S 1500,1000,1500,3000,200,*,DOWN,ALU1 +S 2800,1000,2800,3000,200,*,DOWN,ALU1 +S 1000,1000,1000,3500,200,*,UP,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 2800,2000,3500,2000,200,*,RIGHT,ALU1 +S 3300,2500,3300,3500,200,*,DOWN,ALU1 +S 2000,1000,2000,3000,200,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 1000,4000,2200,4000,200,*,RIGHT,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 500,2000,700,2000,300,*,RIGHT,POLY +S 1300,2000,1500,2000,300,*,RIGHT,POLY +S 3500,2000,4300,2000,300,*,RIGHT,POLY +S 3100,2500,3300,2500,300,*,RIGHT,POLY +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 3100,1400,3100,2600,100,*,DOWN,POLY +S 700,1400,700,3100,100,*,DOWN,POLY +S 1300,1400,1300,3100,100,*,DOWN,POLY +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 3400,300,3400,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 4600,300,4600,1200,300,*,UP,NDIF +S 3100,600,3100,1400,100,*,DOWN,NTRANS +S 2800,800,2800,1200,300,*,UP,NDIF +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 1600,800,1600,1200,300,*,UP,NDIF +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 2200,400,2200,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 400,400,400,1200,300,*,UP,NDIF +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 3100,2600,3100,3900,100,*,UP,PTRANS +S 2800,2800,2800,3700,300,*,DOWN,PDIF +S 700,3100,700,4400,100,*,UP,PTRANS +S 1900,3100,1900,4400,100,*,UP,PTRANS +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 2200,3300,2200,4200,300,*,DOWN,PDIF +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 0,1000,5000,1000,1800,*,RIGHT,PWELL +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 900,4700,2900,4700,300,*,RIGHT,NTIE +S 900,300,1700,300,300,*,RIGHT,PTIE +V 2000,1500,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 1600,4700,CONT_BODY_N,* +V 400,4500,CONT_DIF_P,* +V 1600,3500,CONT_DIF_P,* +V 3500,2000,CONT_POLY,* +V 3300,2500,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1600,300,CONT_BODY_P,* +V 1000,300,CONT_BODY_P,* +V 1000,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 2200,500,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 4600,500,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 3400,4500,CONT_DIF_P,* +V 3400,4000,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 2200,4000,CONT_DIF_P,* +V 1000,4700,CONT_BODY_N,* +V 2800,4700,CONT_BODY_N,* +V 2800,3000,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 2200,4700,CONT_BODY_N,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x4.vbe new file mode 100644 index 000000000..6288a32e6 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 550; + CONSTANT tphl_i2_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i2_nq : NATURAL := 646; + CONSTANT tplh_i1_nq : NATURAL := 709; + CONSTANT tplh_i0_nq : NATURAL := 740; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x4; + +ARCHITECTURE behaviour_data_flow OF noa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x1.ap new file mode 100644 index 000000000..6119832fe --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x1.ap @@ -0,0 +1,87 @@ +V ALLIANCE : 6 +H noa2a22_x1,P,22/ 7/2016,100 +A 0,0,3500,5000 +R 500,2000,ref_ref,i0_25 +R 2500,2000,ref_ref,i2_25 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 2000,1000,ref_ref,i3_10 +R 2000,1500,ref_ref,i3_15 +R 2000,2000,ref_ref,i3_20 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2000,3500,ref_ref,i3_35 +R 2500,3500,ref_ref,i2_35 +R 2500,3000,ref_ref,i2_30 +R 2500,1500,ref_ref,i2_15 +R 2500,1000,ref_ref,i2_10 +R 1500,1000,ref_ref,nq_10 +R 1500,1500,ref_ref,nq_15 +R 1500,2000,ref_ref,nq_20 +R 1500,2500,ref_ref,nq_25 +R 1500,3000,ref_ref,nq_30 +R 1500,3500,ref_ref,nq_35 +S 900,3500,1500,3500,200,*,RIGHT,ALU1 +S 1500,1000,1500,3500,200,*,UP,ALU1 +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 500,1000,500,3000,200,*,UP,ALU1 +S 1000,1000,1000,3000,200,*,DOWN,ALU1 +S 2500,1000,2500,3500,200,*,DOWN,ALU1 +S 2000,1000,2000,3500,200,*,DOWN,ALU1 +S 300,4000,2700,4000,200,*,RIGHT,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 3200,2900,3200,4500,200,*,DOWN,ALU1 +S 0,1000,3500,1000,1800,*,LEFT,PWELL +S 0,3900,3500,3900,2400,*,LEFT,NWELL +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 2000,1000,2000,3500,200,i3,DOWN,CALU1 +S 2500,1000,2500,3500,200,i2,DOWN,CALU1 +S 1500,1000,1500,3500,200,nq,DOWN,CALU1 +S 2700,3700,2700,4700,300,*,DOWN,PDIF +S 2600,2800,2600,3700,300,*,UP,PDIF +S 3200,2900,3200,3300,300,*,DOWN,NTIE +V 500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 1500,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2700,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3200,2900,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x1.vbe new file mode 100644 index 000000000..d63481981 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i3_nq : NATURAL := 256; + CONSTANT tphl_i2_nq : NATURAL := 284; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i2_nq : NATURAL := 289; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT tphl_i3_nq : NATURAL := 372; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x4.ap new file mode 100644 index 000000000..40876762f --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x4.ap @@ -0,0 +1,147 @@ +V ALLIANCE : 6 +H noa2a22_x4,P, 9/12/2016,100 +A 0,0,5500,5000 +R 4500,4000,ref_ref,nq_40 +R 2500,1000,ref_ref,i2_10 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,2000,ref_ref,i3_20 +R 2000,1500,ref_ref,i3_15 +R 2000,1000,ref_ref,i3_10 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +R 4500,3500,ref_ref,nq_35 +R 4500,3000,ref_ref,nq_30 +R 4500,2000,ref_ref,nq_20 +R 4500,1000,ref_ref,nq_10 +R 4500,1500,ref_ref,nq_15 +R 4500,2500,ref_ref,nq_25 +S 1800,3000,2000,3000,300,*,RIGHT,POLY +S 1000,3000,1200,3000,300,*,LEFT,POLY +S 2400,1400,2400,1900,100,*,DOWN,POLY +S 1800,2900,1800,3100,100,*,DOWN,POLY +S 1800,1400,1800,2000,100,*,DOWN,POLY +S 1200,1400,1200,2100,100,*,DOWN,POLY +S 600,1400,600,2100,100,*,DOWN,POLY +S 2500,1000,2500,3000,200,i2,DOWN,CALU1 +S 2000,1000,2000,3000,200,i3,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 4500,1000,4500,4000,200,nq,DOWN,CALU1 +S 4500,1000,4500,4000,200,*,UP,ALU1 +S 0,1000,5500,1000,1800,*,RIGHT,PWELL +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 2700,400,2700,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2700,3300,2700,4200,300,*,DOWN,PDIF +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 4000,2000,4800,2000,300,*,RIGHT,POLY +S 3900,500,3900,1000,200,*,DOWN,ALU1 +S 5100,500,5100,1000,200,*,DOWN,ALU1 +S 5100,3000,5100,4500,200,*,DOWN,ALU1 +S 3900,4000,3900,4500,200,*,DOWN,ALU1 +S 3600,2500,3800,2500,300,*,RIGHT,POLY +S 3300,2000,4000,2000,200,*,RIGHT,ALU1 +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3800,2500,3800,3500,200,*,DOWN,ALU1 +S 900,3500,3800,3500,200,*,RIGHT,ALU1 +S 2500,1000,2500,3000,200,*,DOWN,ALU1 +S 2000,1000,2000,3000,200,*,DOWN,ALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 300,4000,2700,4000,200,*,RIGHT,ALU1 +S 1000,1000,1000,3000,200,*,DOWN,ALU1 +S 500,1000,500,3000,200,*,UP,ALU1 +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 3900,300,3900,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 5100,300,5100,1200,300,*,UP,NDIF +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 3300,2800,3300,3700,300,*,DOWN,PDIF +S 3300,800,3300,1200,300,*,UP,NDIF +S 3300,1000,3300,3000,200,*,DOWN,ALU1 +S 1500,1000,1500,3500,200,*,UP,ALU1 +S 300,4700,1500,4700,300,*,RIGHT,NTIE +S 900,300,2100,300,300,*,LEFT,PTIE +S 2600,4700,3400,4700,300,*,RIGHT,NTIE +S 1200,2900,1200,3100,100,*,DOWN,POLY +V 2500,3000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 500,3000,CONT_POLY,* +V 1500,4700,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 3300,4700,CONT_BODY_N,* +V 4000,2000,CONT_POLY,* +V 5100,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 3300,3000,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 3900,4000,CONT_DIF_P,* +V 3800,2500,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 3900,500,CONT_DIF_N,* +V 5100,500,CONT_DIF_N,* +V 4500,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 900,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +V 4500,3000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 2700,4700,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x4.vbe new file mode 100644 index 000000000..93e31d341 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 562; + CONSTANT tphl_i1_nq : NATURAL := 646; + CONSTANT tplh_i3_nq : NATURAL := 677; + CONSTANT tphl_i2_nq : NATURAL := 701; + CONSTANT tplh_i2_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 714; + CONSTANT tplh_i0_nq : NATURAL := 745; + CONSTANT tphl_i3_nq : NATURAL := 805; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1400 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x1.ap new file mode 100644 index 000000000..fe5002d4b --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x1.ap @@ -0,0 +1,118 @@ +V ALLIANCE : 6 +H noa2a2a23_x1,P,22/ 7/2016,100 +A 0,0,5000,5000 +R 2000,3000,ref_ref,i3_25 +R 1500,3000,ref_ref,i4_25 +R 1000,3000,ref_ref,i5_25 +R 500,2000,ref_ref,nq_25 +R 2500,2000,ref_ref,i2_25 +R 4000,2000,ref_ref,i1_25 +R 4500,2000,ref_ref,i0_25 +R 1000,2000,ref_ref,i5_20 +R 1000,1500,ref_ref,i5_15 +R 2000,1500,ref_ref,i3_15 +R 2500,1500,ref_ref,i2_15 +R 2500,3000,ref_ref,i2_30 +R 2000,2000,ref_ref,i3_20 +R 1500,1500,ref_ref,i4_15 +R 1500,2000,ref_ref,i4_20 +R 500,1500,ref_ref,nq_15 +R 500,3500,ref_ref,nq_35 +R 500,3000,ref_ref,nq_30 +R 4500,1500,ref_ref,i0_15 +R 4500,3000,ref_ref,i0_30 +R 4000,3000,ref_ref,i1_30 +R 4000,1500,ref_ref,i1_15 +R 500,1000,ref_ref,nq_10 +R 1500,3500,ref_ref,i4_35 +S 3100,300,3100,800,300,*,UP,PTIE +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 4500,1500,4500,3000,200,i0,DOWN,CALU1 +S 4000,1500,4000,3000,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 300,4000,2700,4000,200,*,RIGHT,ALU1 +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 4700,300,4700,1000,200,*,DOWN,ALU1 +S 4400,100,4400,1400,100,*,UP,NTRANS +S 4400,2600,4400,4900,100,*,UP,PTRANS +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3800,2600,3800,4900,100,*,UP,PTRANS +S 1000,1500,1000,3000,200,*,UP,ALU1 +S 2000,1500,2000,3000,200,*,UP,ALU1 +S 2500,1500,2500,3000,200,*,UP,ALU1 +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 900,1400,900,2600,100,*,DOWN,POLY +S 3500,4000,3500,4700,200,*,UP,ALU1 +S 2100,3500,4100,3500,200,*,RIGHT,ALU1 +S 4100,3500,4100,4000,200,*,UP,ALU1 +S 4700,2800,4700,4700,300,*,UP,PDIF +S 4700,3500,4700,4600,200,*,DOWN,ALU1 +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 4700,300,4700,1200,300,*,DOWN,NDIF +S 3800,2500,4000,2500,100,*,LEFT,POLY +S 3800,2500,3800,2700,100,*,UP,POLY +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 800,100,800,1400,100,*,UP,NTRANS +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,1400,900,1400,100,*,LEFT,POLY +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,1000,5000,1000,1800,*,RIGHT,PWELL +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 4500,1500,4500,3000,200,*,UP,ALU1 +S 4000,1500,4000,3000,200,*,UP,ALU1 +S 1500,1500,1500,3500,200,*,UP,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3500,2800,3500,4700,300,*,UP,PDIF +S 500,1000,3800,1000,200,*,LEFT,ALU1 +S 500,1000,500,3500,200,*,DOWN,ALU1 +S 500,1100,500,3500,200,nq,DOWN,CALU1 +S 500,3500,900,3500,200,*,RIGHT,ALU1 +V 2500,1500,CONT_POLY,* +V 4000,1500,CONT_POLY,* +V 4500,1500,CONT_POLY,* +V 1500,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 3900,2500,CONT_POLY,* +V 4700,1000,CONT_DIF_N,* +V 4100,4000,CONT_DIF_P,* +V 4700,4000,CONT_DIF_P,* +V 2500,2500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 3500,4000,CONT_DIF_P,* +V 4700,4500,CONT_DIF_P,* +V 4700,3500,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 4700,500,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 3100,400,CONT_BODY_P,* +V 4500,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x1.vbe new file mode 100644 index 000000000..2d90886a0 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x1.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT rup_i3_nq : NATURAL := 4690; + CONSTANT rup_i4_nq : NATURAL := 4690; + CONSTANT rup_i5_nq : NATURAL := 4690; + CONSTANT tphl_i5_nq : NATURAL := 178; + CONSTANT tphl_i4_nq : NATURAL := 250; + CONSTANT tphl_i2_nq : NATURAL := 307; + CONSTANT tplh_i1_nq : NATURAL := 388; + CONSTANT tphl_i3_nq : NATURAL := 398; + CONSTANT tplh_i4_nq : NATURAL := 416; + CONSTANT tplh_i0_nq : NATURAL := 425; + CONSTANT tplh_i3_nq : NATURAL := 438; + CONSTANT tplh_i5_nq : NATURAL := 464; + CONSTANT tplh_i2_nq : NATURAL := 479; + CONSTANT tphl_i0_nq : NATURAL := 525; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x4.ap new file mode 100644 index 000000000..e885dc5ee --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x4.ap @@ -0,0 +1,151 @@ +V ALLIANCE : 6 +H noa2a2a23_x4,P,22/ 7/2016,100 +A 0,0,6500,5000 +R 1000,3000,ref_ref,i5_25 +R 1500,3000,ref_ref,i4_25 +R 2000,3000,ref_ref,i3_25 +R 2500,2000,ref_ref,i2_25 +R 3500,2000,ref_ref,i1_25 +R 4000,2000,ref_ref,i0_25 +R 5000,4000,ref_ref,nq_40 +R 5000,1500,ref_ref,nq_15 +R 5000,3500,ref_ref,nq_35 +R 5000,3000,ref_ref,nq_30 +R 5000,2500,ref_ref,nq_25 +R 5000,2000,ref_ref,nq_20 +R 4000,1500,ref_ref,i0_15 +R 4000,3000,ref_ref,i0_30 +R 3500,3000,ref_ref,i1_30 +R 3500,1500,ref_ref,i1_15 +R 1500,3500,ref_ref,i4_35 +R 1500,2000,ref_ref,i4_20 +R 1500,1500,ref_ref,i4_15 +R 2000,2000,ref_ref,i3_20 +R 2500,3000,ref_ref,i2_30 +R 2500,1500,ref_ref,i2_15 +R 2000,1500,ref_ref,i3_15 +R 1000,1500,ref_ref,i5_15 +R 1000,2000,ref_ref,i5_20 +S 6200,4200,6200,4700,300,*,DOWN,NTIE +S 3500,1500,3500,3000,200,i1,DOWN,CALU1 +S 4000,1500,4000,3000,200,i0,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +S 2100,3500,3800,3500,200,*,RIGHT,ALU1 +S 6200,1000,6200,3500,200,*,DOWN,ALU1 +S 5500,2000,6200,2000,200,*,RIGHT,ALU1 +S 5700,1000,5700,1500,200,*,UP,ALU1 +S 500,1000,5700,1000,200,*,RIGHT,ALU1 +S 4700,2000,5300,2000,100,*,RIGHT,POLY +S 5900,1400,5900,2600,100,*,UP,POLY +S 3250,2800,3250,4600,200,*,DOWN,PDIF +S 2700,2800,2700,4000,300,*,UP,PDIF +S 6200,2800,6200,3700,300,*,UP,PDIF +S 6200,800,6200,1200,300,*,DOWN,NDIF +S 5900,2600,5900,3900,100,*,UP,PTRANS +S 5900,600,5900,1400,100,*,DOWN,NTRANS +S 3500,2600,3500,4900,100,*,UP,PTRANS +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 5000,2800,5000,4700,300,*,UP,PDIF +S 5600,2800,5600,4700,300,*,UP,PDIF +S 4400,2800,4400,4700,300,*,UP,PDIF +S 3800,2800,3800,4700,300,*,UP,PDIF +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 4100,100,4100,1400,100,*,UP,NTRANS +S 3700,100,3700,1400,100,*,UP,NTRANS +S 3400,300,3400,1200,300,*,DOWN,NDIF +S 4400,300,4400,1200,300,*,DOWN,NDIF +S 5600,300,5600,1200,300,*,DOWN,NDIF +S 4700,100,4700,1400,100,*,UP,NTRANS +S 5300,100,5300,1400,100,*,DOWN,NTRANS +S 5300,1400,5300,2600,100,*,DOWN,POLY +S 4700,1400,4700,2600,100,*,DOWN,POLY +S 3500,1400,3700,1400,100,*,LEFT,POLY +S 5600,3500,5600,4600,200,*,DOWN,ALU1 +S 3800,3500,3800,4000,200,*,UP,ALU1 +S 4400,3500,4400,4600,200,*,DOWN,ALU1 +S 4000,1500,4000,3000,200,*,UP,ALU1 +S 3500,1500,3500,3000,200,*,UP,ALU1 +S 500,1000,500,3400,200,*,DOWN,ALU1 +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 0,1000,6500,1000,1800,*,RIGHT,PWELL +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 1500,1500,1500,3500,200,*,UP,ALU1 +S 800,1400,900,1400,100,*,LEFT,POLY +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,100,800,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 900,1400,900,2600,100,*,DOWN,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 2500,1500,2500,3000,200,*,UP,ALU1 +S 2000,1500,2000,3000,200,*,UP,ALU1 +S 1000,1500,1000,3000,200,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 300,4000,2700,4000,200,*,RIGHT,ALU1 +S 5000,300,5000,1500,300,*,DOWN,NDIF +S 5300,2000,5500,2000,300,*,LEFT,POLY +S 5700,1500,5900,1500,300,*,RIGHT,POLY +S 5000,1500,5000,4000,200,*,DOWN,ALU1 +S 5000,1600,5000,4000,200,nq,DOWN,CALU1 +S 500,3500,900,3500,200,*,LEFT,ALU1 +V 2500,1500,CONT_POLY,* +V 4000,1500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 5700,1500,CONT_POLY,* +V 5500,2000,CONT_POLY,* +V 3200,4600,CONT_DIF_P,* +V 6200,4600,CONT_BODY_N,* +V 6200,3500,CONT_DIF_P,* +V 6200,3000,CONT_DIF_P,* +V 6200,1000,CONT_DIF_N,* +V 5000,3500,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 4400,4500,CONT_DIF_P,* +V 4400,3500,CONT_DIF_P,* +V 3800,4000,CONT_DIF_P,* +V 5600,3500,CONT_DIF_P,* +V 5600,4500,CONT_DIF_P,* +V 5600,4000,CONT_DIF_P,* +V 5000,3000,CONT_DIF_P,* +V 4400,500,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 5600,500,CONT_DIF_N,* +V 3500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 500,500,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 5000,1500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x4.vbe new file mode 100644 index 000000000..328209403 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT tphl_i5_nq : NATURAL := 496; + CONSTANT tphl_i4_nq : NATURAL := 574; + CONSTANT tphl_i2_nq : NATURAL := 620; + CONSTANT tphl_i3_nq : NATURAL := 716; + CONSTANT tplh_i1_nq : NATURAL := 778; + CONSTANT tplh_i0_nq : NATURAL := 814; + CONSTANT tplh_i4_nq : NATURAL := 819; + CONSTANT tplh_i3_nq : NATURAL := 833; + CONSTANT tphl_i0_nq : NATURAL := 834; + CONSTANT tplh_i5_nq : NATURAL := 865; + CONSTANT tplh_i2_nq : NATURAL := 873; + CONSTANT tphl_i1_nq : NATURAL := 955; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1600 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x1.ap new file mode 100644 index 000000000..c328fef11 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x1.ap @@ -0,0 +1,151 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x1,P, 9/12/2016,100 +A 0,0,7000,5000 +R 500,1000,ref_ref,i7_10 +R 500,1500,ref_ref,i7_15 +R 500,3000,ref_ref,i7_30 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1500,1500,ref_ref,i6_15 +R 1500,3000,ref_ref,i6_30 +R 2500,1500,ref_ref,i5_15 +R 2500,3000,ref_ref,i5_30 +R 3000,1500,ref_ref,i4_15 +R 3000,3000,ref_ref,i4_30 +R 3500,1500,ref_ref,i3_15 +R 3500,3000,ref_ref,i3_30 +R 4000,1500,ref_ref,i2_15 +R 4000,3000,ref_ref,i2_30 +R 5500,1500,ref_ref,i1_15 +R 5500,3000,ref_ref,i1_30 +R 5500,3500,ref_ref,i1_35 +R 6000,1500,ref_ref,i0_15 +R 6000,3000,ref_ref,i0_30 +R 6000,3500,ref_ref,i0_35 +R 500,2000,ref_ref,i7_25 +R 1500,2000,ref_ref,i6_25 +R 2500,2000,ref_ref,i5_25 +R 3000,2000,ref_ref,i4_25 +R 3500,2000,ref_ref,i3_25 +R 4000,2000,ref_ref,i2_25 +R 5500,2000,ref_ref,i1_25 +R 6000,2000,ref_ref,i0_25 +S 4000,1500,4200,1500,300,*,LEFT,POLY +S 1000,1000,1000,3500,200,*,DOWN,ALU1 +S 1000,1100,1000,3500,200,nq,DOWN,CALU1 +S 1000,1000,5100,1000,200,*,LEFT,ALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +S 5500,1500,5500,3500,200,i1,DOWN,CALU1 +S 6000,1500,6000,3500,200,i0,DOWN,CALU1 +S 300,3500,300,4000,200,*,UP,ALU1 +S 3300,3500,3300,4000,200,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 500,1000,500,3000,200,*,UP,ALU1 +S 3900,3500,5000,3500,200,*,LEFT,ALU1 +S 5000,3500,5000,4000,200,*,DOWN,ALU1 +S 5000,4000,5700,4000,200,*,LEFT,ALU1 +S 5500,1500,5500,3500,200,*,UP,ALU1 +S 6000,1500,6000,3500,200,*,UP,ALU1 +S 4000,1500,4000,3000,200,*,UP,ALU1 +S 3500,1500,3500,3000,200,*,UP,ALU1 +S 3000,1500,3000,3000,200,*,UP,ALU1 +S 2500,1500,2500,3000,200,*,UP,ALU1 +S 1500,1500,1500,3000,200,*,UP,ALU1 +S 6300,4000,6300,4600,200,*,DOWN,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 5700,2800,5700,4700,300,*,UP,PDIF +S 6000,2600,6000,4900,100,*,UP,PTRANS +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 4500,2800,4500,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3300,2800,3300,4700,300,*,UP,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,3500,2700,3500,200,*,RIGHT,ALU1 +S 2100,4000,4500,4000,200,*,RIGHT,ALU1 +S 300,4000,1500,4000,200,*,RIGHT,ALU1 +S 1500,3500,1500,4000,200,*,DOWN,ALU1 +S 0,4700,7000,4700,600,vdd,RIGHT,CALU1 +S 0,300,7000,300,600,vss,RIGHT,CALU1 +S 0,3900,7000,3900,2400,*,RIGHT,NWELL +S 0,1000,7000,1000,1800,*,RIGHT,PWELL +S 6300,300,6300,1000,200,*,DOWN,ALU1 +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 5100,300,5100,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 4500,300,4500,1200,300,*,DOWN,NDIF +S 3600,100,3600,1400,100,*,UP,NTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 5700,300,5700,1200,300,*,DOWN,NDIF +S 4200,100,4200,1400,100,*,UP,NTRANS +S 6000,100,6000,1400,100,*,UP,NTRANS +S 2400,100,2400,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 5400,100,5400,1400,100,*,UP,NTRANS +S 600,100,600,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +S 4000,2500,4200,2500,300,*,RIGHT,POLY +S 6300,2800,6300,4700,300,*,UP,PDIF +S 6300,300,6300,1200,300,*,DOWN,NDIF +S 1200,1500,1500,1500,300,*,LEFT,POLY +S 4200,1400,4200,1600,100,*,DOWN,POLY +V 1500,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3300,3500,CONT_DIF_P,* +V 6000,2500,CONT_POLY,* +V 5500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 6300,1000,CONT_DIF_N,* +V 6300,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 300,500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 4000,1500,CONT_POLY,* +V 5500,1500,CONT_POLY,* +V 6000,1500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x1.vbe new file mode 100644 index 000000000..ed253ca47 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x1.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rdown_i6_nq : NATURAL := 2850; + CONSTANT rdown_i7_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT rup_i4_nq : NATURAL := 6190; + CONSTANT rup_i5_nq : NATURAL := 6190; + CONSTANT rup_i6_nq : NATURAL := 6190; + CONSTANT rup_i7_nq : NATURAL := 6190; + CONSTANT tphl_i7_nq : NATURAL := 200; + CONSTANT tphl_i6_nq : NATURAL := 270; + CONSTANT tphl_i5_nq : NATURAL := 329; + CONSTANT tphl_i4_nq : NATURAL := 419; + CONSTANT tplh_i6_nq : NATURAL := 535; + CONSTANT tphl_i2_nq : NATURAL := 550; + CONSTANT tplh_i1_nq : NATURAL := 562; + CONSTANT tplh_i7_nq : NATURAL := 591; + CONSTANT tplh_i0_nq : NATURAL := 606; + CONSTANT tplh_i4_nq : NATURAL := 613; + CONSTANT tplh_i3_nq : NATURAL := 616; + CONSTANT tphl_i0_nq : NATURAL := 649; + CONSTANT tplh_i2_nq : NATURAL := 662; + CONSTANT tplh_i5_nq : NATURAL := 662; + CONSTANT tphl_i3_nq : NATURAL := 667; + CONSTANT tphl_i1_nq : NATURAL := 775; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x1" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1400 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x4.ap new file mode 100644 index 000000000..af673c96b --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x4.ap @@ -0,0 +1,191 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x4,P,22/ 7/2016,100 +A 0,0,8500,5000 +R 5500,2000,ref_ref,i1_25 +R 4000,2000,ref_ref,i2_25 +R 3500,2000,ref_ref,i3_25 +R 3000,2000,ref_ref,i4_25 +R 2500,2000,ref_ref,i5_25 +R 1500,2000,ref_ref,i6_25 +R 500,2000,ref_ref,i7_25 +R 4000,3000,ref_ref,i2_30 +R 4000,1500,ref_ref,i2_15 +R 3500,3000,ref_ref,i3_30 +R 3500,1500,ref_ref,i3_15 +R 3000,3000,ref_ref,i4_30 +R 3000,1500,ref_ref,i4_15 +R 2500,3000,ref_ref,i5_30 +R 2500,1500,ref_ref,i5_15 +R 1500,3000,ref_ref,i6_30 +R 1500,2000,ref_ref,i6_20 +R 1500,1500,ref_ref,i6_15 +R 500,3000,ref_ref,i7_30 +R 500,2000,ref_ref,i7_20 +R 500,1500,ref_ref,i7_15 +R 500,1000,ref_ref,i7_10 +R 7000,2500,ref_ref,nq_25 +R 7000,3000,ref_ref,nq_30 +R 7000,3500,ref_ref,nq_35 +R 7000,1500,ref_ref,nq_15 +R 7000,2000,ref_ref,nq_20 +R 7000,4000,ref_ref,nq_40 +R 6500,3000,ref_ref,i0_30 +R 6500,2500,ref_ref,i0_25 +R 6500,2000,ref_ref,i0_20 +R 6500,1500,ref_ref,i0_15 +R 5500,1500,ref_ref,i1_15 +R 5500,3000,ref_ref,i1_30 +R 6500,3500,ref_ref,i0_35 +S 1200,1500,1500,1500,300,*,LEFT,POLY +S 8200,4200,8200,4700,300,*,DOWN,NTIE +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +S 5500,1500,5500,3000,200,i1,DOWN,CALU1 +S 6500,1500,6500,3500,200,i0,DOWN,CALU1 +S 6100,1400,6100,2600,100,*,DOWN,POLY +S 5500,1400,5700,1400,100,*,LEFT,POLY +S 6700,2000,7500,2000,100,*,LEFT,POLY +S 6200,2000,6400,2000,200,*,RIGHT,ALU1 +S 7500,2000,8200,2000,200,*,RIGHT,ALU1 +S 3900,3500,5800,3500,200,*,RIGHT,ALU1 +S 7700,1000,7700,1500,200,*,UP,ALU1 +S 5400,1000,7700,1000,200,*,RIGHT,ALU1 +S 7900,1400,7900,2600,100,*,UP,POLY +S 8200,1000,8200,3500,200,*,UP,ALU1 +S 8200,2800,8200,3700,300,*,UP,PDIF +S 8200,800,8200,1200,300,*,UP,NDIF +S 7900,2600,7900,3900,100,*,UP,PTRANS +S 7900,600,7900,1400,100,*,DOWN,NTRANS +S 1000,1000,5400,1000,200,*,RIGHT,ALU1 +S 5500,1500,5500,3000,200,*,UP,ALU1 +S 6500,1500,6500,3500,200,*,UP,ALU1 +S 5200,2800,5200,4700,300,*,UP,PDIF +S 5500,2600,5500,4900,100,*,UP,PTRANS +S 7300,2600,7300,4900,100,*,UP,PTRANS +S 6400,2800,6400,4700,300,*,UP,PDIF +S 6700,2600,6700,4900,100,*,UP,PTRANS +S 7600,2800,7600,4700,300,*,UP,PDIF +S 7000,2800,7000,4700,300,*,UP,PDIF +S 5800,2800,5800,4700,300,*,UP,PDIF +S 6100,2600,6100,4900,100,*,UP,PTRANS +S 6100,100,6100,1400,100,*,UP,NTRANS +S 7600,300,7600,1200,300,*,DOWN,NDIF +S 6400,300,6400,1200,300,*,DOWN,NDIF +S 7300,100,7300,1400,100,*,DOWN,NTRANS +S 5400,300,5400,1200,300,*,DOWN,NDIF +S 5700,100,5700,1400,100,*,UP,NTRANS +S 6700,100,6700,1400,100,*,UP,NTRANS +S 6700,1400,6700,2600,100,*,DOWN,POLY +S 7300,1400,7300,2600,100,*,DOWN,POLY +S 5800,3500,5800,4000,200,*,UP,ALU1 +S 6400,4000,6400,4600,200,*,DOWN,ALU1 +S 5200,4000,5200,4600,200,*,DOWN,ALU1 +S 7600,3500,7600,4600,200,*,DOWN,ALU1 +S 4500,2800,4500,4700,300,*,UP,PDIF +S 0,4700,8500,4700,600,vdd,RIGHT,CALU1 +S 0,1000,8500,1000,1800,*,RIGHT,PWELL +S 0,3900,8500,3900,2400,*,RIGHT,NWELL +S 0,300,8500,300,600,vss,RIGHT,CALU1 +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 1500,3500,1500,4000,200,*,DOWN,ALU1 +S 300,4000,1500,4000,200,*,RIGHT,ALU1 +S 2100,4000,4500,4000,200,*,RIGHT,ALU1 +S 1500,3500,2700,3500,200,*,RIGHT,ALU1 +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1500,1500,1500,3000,200,*,UP,ALU1 +S 2500,1500,2500,3000,200,*,UP,ALU1 +S 3000,1500,3000,3000,200,*,UP,ALU1 +S 3500,1500,3500,3000,200,*,UP,ALU1 +S 4000,1500,4000,3000,200,*,UP,ALU1 +S 500,1000,500,3000,200,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 3300,3500,3300,4000,200,*,UP,ALU1 +S 300,3500,300,4000,200,*,UP,ALU1 +S 900,3500,1000,3500,200,*,RIGHT,ALU1 +S 1000,1000,1000,3500,200,*,DOWN,ALU1 +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2600,100,2600,1400,100,*,UP,NTRANS +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 7000,300,7000,1500,300,*,DOWN,NDIF +S 7300,2000,7500,2000,300,*,LEFT,POLY +S 7700,1500,7900,1500,300,*,RIGHT,POLY +S 7000,1500,7000,4000,200,*,DOWN,ALU1 +S 7000,1600,7000,4000,200,nq,DOWN,CALU1 +V 5500,2500,CONT_POLY,* +V 5500,1500,CONT_POLY,* +V 4000,1500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 6200,2000,CONT_POLY,* +V 7500,2000,CONT_POLY,* +V 7700,1500,CONT_POLY,* +V 8200,1000,CONT_DIF_N,* +V 8200,3500,CONT_DIF_P,* +V 8200,2900,CONT_DIF_P,* +V 5200,4500,CONT_DIF_P,* +V 7000,3000,CONT_DIF_P,* +V 7600,4000,CONT_DIF_P,* +V 5800,4000,CONT_DIF_P,* +V 5200,4000,CONT_DIF_P,* +V 7600,4500,CONT_DIF_P,* +V 7600,3500,CONT_DIF_P,* +V 6400,4000,CONT_DIF_P,* +V 7000,4000,CONT_DIF_P,* +V 6400,4500,CONT_DIF_P,* +V 7000,3500,CONT_DIF_P,* +V 7600,500,CONT_DIF_N,* +V 6400,500,CONT_DIF_N,* +V 5400,1000,CONT_DIF_N,* +V 8200,4600,CONT_BODY_N,* +V 3300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 3300,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 4300,500,CONT_DIF_N,* +V 2300,500,CONT_DIF_N,* +V 7000,1500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x4.vbe new file mode 100644 index 000000000..2499cd710 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/noa2a2a2a24_x4.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4250; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rdown_i7_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT rup_i7_nq : NATURAL := 890; + CONSTANT tphl_i7_nq : NATURAL := 525; + CONSTANT tphl_i6_nq : NATURAL := 606; + CONSTANT tphl_i5_nq : NATURAL := 649; + CONSTANT tphl_i4_nq : NATURAL := 748; + CONSTANT tphl_i2_nq : NATURAL := 867; + CONSTANT tphl_i0_nq : NATURAL := 966; + CONSTANT tphl_i3_nq : NATURAL := 990; + CONSTANT tplh_i6_nq : NATURAL := 999; + CONSTANT tplh_i1_nq : NATURAL := 1005; + CONSTANT tplh_i0_nq : NATURAL := 1049; + CONSTANT tplh_i7_nq : NATURAL := 1052; + CONSTANT tplh_i3_nq : NATURAL := 1061; + CONSTANT tplh_i4_nq : NATURAL := 1061; + CONSTANT tphl_i1_nq : NATURAL := 1097; + CONSTANT tplh_i2_nq : NATURAL := 1106; + CONSTANT tplh_i5_nq : NATURAL := 1109; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x4" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1700 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x1.ap new file mode 100644 index 000000000..ff6d4bd01 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x1.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H nts_x1,P, 9/12/2016,100 +A 0,0,3000,5000 +R 1000,4000,ref_ref,cmd_40 +R 1000,3500,ref_ref,cmd_35 +R 1000,3000,ref_ref,cmd_30 +R 1000,2500,ref_ref,cmd_25 +R 500,4000,ref_ref,i_40 +R 1500,2500,ref_ref,nq_25 +R 500,1500,ref_ref,i_15 +R 500,1000,ref_ref,i_10 +R 1000,2000,ref_ref,cmd_20 +R 1000,1500,ref_ref,cmd_15 +R 1000,1000,ref_ref,cmd_10 +R 1500,1000,ref_ref,nq_10 +R 1500,4000,ref_ref,nq_40 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +R 500,2000,ref_ref,i_25 +S 1000,2000,1200,2000,300,*,LEFT,POLY +S 2000,2300,2000,2500,300,*,DOWN,POLY +S 2000,300,2800,300,300,*,RIGHT,PTIE +S 2000,4700,2800,4700,300,*,RIGHT,NTIE +S 2700,3000,2700,4700,200,*,UP,ALU1 +S 2700,300,2700,1000,200,*,DOWN,ALU1 +S 1000,2000,2400,2000,100,*,RIGHT,POLY +S 1200,1400,1200,2000,100,*,UP,POLY +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 1500,1000,1500,4000,200,*,DOWN,ALU1 +S 500,1000,500,4000,200,*,UP,ALU1 +S 2400,2600,2400,3900,100,*,DOWN,PTRANS +S 2100,2800,2100,3700,300,*,DOWN,PDIF +S 2700,2800,2700,3700,300,*,DOWN,PDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 600,2600,600,4900,100,*,DOWN,PTRANS +S 2400,600,2400,1400,100,*,UP,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 2700,800,2700,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2000,2500,2000,2600,100,*,DOWN,POLY +S 2100,1000,2100,3500,200,*,DOWN,ALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 0,1000,3000,1000,1800,*,RIGHT,PWELL +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 1000,1000,1000,4000,200,cmd,DOWN,CALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,nq,DOWN,CALU1 +S 1200,2300,1200,2600,100,*,DOWN,POLY +S 1200,2300,2100,2300,100,*,RIGHT,POLY +V 2100,4700,CONT_BODY_N,* +V 2100,300,CONT_BODY_P,* +V 2700,4700,CONT_BODY_N,* +V 2700,300,CONT_BODY_P,* +V 1000,2000,CONT_POLY,* +V 300,4500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 2000,2500,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 500,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x1.vbe new file mode 100644 index 000000000..f6cada4ad --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x1.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_cmd : NATURAL := 14; + CONSTANT cin_i : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i_nq : NATURAL := 3210; + CONSTANT tphl_cmd_nq : NATURAL := 41; + CONSTANT tphl_i_nq : NATURAL := 169; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 249; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x1; + +ARCHITECTURE behaviour_data_flow OF nts_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x1" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 800 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x2.ap new file mode 100644 index 000000000..3369f54f0 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x2.ap @@ -0,0 +1,96 @@ +V ALLIANCE : 6 +H nts_x2,P, 9/12/2016,100 +A 0,0,4000,5000 +R 1000,4000,ref_ref,i_40 +R 1000,3500,ref_ref,i_35 +R 1000,3000,ref_ref,i_30 +R 1000,2500,ref_ref,i_25 +R 1000,2000,ref_ref,i_20 +R 1000,1500,ref_ref,i_15 +R 1000,1000,ref_ref,i_10 +R 1500,4000,ref_ref,nq_40 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 1500,1000,ref_ref,nq_10 +R 3000,2000,ref_ref,cmd_20 +R 3000,1500,ref_ref,cmd_15 +R 3000,1000,ref_ref,cmd_10 +R 3000,2500,ref_ref,cmd_25 +R 3000,3000,ref_ref,cmd_30 +R 3000,3500,ref_ref,cmd_35 +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 2000,2300,2000,2500,300,*,UP,POLY +S 1200,2300,2100,2300,100,*,RIGHT,POLY +S 3700,4300,3700,4800,300,*,DOWN,NTIE +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,nq,DOWN,CALU1 +S 3000,1000,3000,3500,200,cmd,DOWN,CALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 1200,1400,2000,1400,100,*,RIGHT,POLY +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,100,2400,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,2600,600,4900,100,*,DOWN,PTRANS +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 1800,2600,1800,4900,100,*,DOWN,PTRANS +S 2400,2600,2400,4900,100,*,DOWN,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 600,1400,600,2600,100,*,UP,POLY +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 0,1000,4000,1000,1800,*,RIGHT,PWELL +S 3400,2600,3400,3900,100,*,DOWN,PTRANS +S 3700,2800,3700,3700,300,*,DOWN,PDIF +S 300,3000,300,4500,200,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 3400,600,3400,1400,100,*,UP,NTRANS +S 3700,800,3700,1200,300,*,UP,NDIF +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2000,1500,3000,1500,200,*,RIGHT,ALU1 +S 3000,2000,3400,2000,300,*,RIGHT,POLY +S 2000,4000,3700,4000,200,*,RIGHT,ALU1 +S 3700,1000,3700,4000,200,*,DOWN,ALU1 +S 2000,2500,2000,4000,200,*,DOWN,ALU1 +S 3000,1000,3000,3500,200,*,UP,ALU1 +S 2900,300,2900,1200,700,*,DOWN,NDIF +S 2900,2800,2900,4700,700,*,UP,PDIF +S 1500,1000,1500,4000,200,*,DOWN,ALU1 +S 1200,2300,1200,2600,100,*,DOWN,POLY +V 3700,3500,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2000,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 3700,4700,CONT_BODY_N,* +V 300,4500,CONT_DIF_P,* +V 2000,1500,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 2700,4500,CONT_DIF_P,* +V 2700,500,CONT_DIF_N,* +V 3100,4500,CONT_DIF_P,* +V 3100,500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x2.vbe new file mode 100644 index 000000000..4bb47086f --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nts_x2.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_cmd : NATURAL := 18; + CONSTANT cin_i : NATURAL := 28; + CONSTANT rdown_cmd_nq : NATURAL := 1430; + CONSTANT rdown_i_nq : NATURAL := 1430; + CONSTANT rup_cmd_nq : NATURAL := 1600; + CONSTANT rup_i_nq : NATURAL := 1600; + CONSTANT tphl_cmd_nq : NATURAL := 33; + CONSTANT tphl_i_nq : NATURAL := 167; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 330; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x2; + +ARCHITECTURE behaviour_data_flow OF nts_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x2" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 900 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x1.ap new file mode 100644 index 000000000..cfd41387d --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x1.ap @@ -0,0 +1,112 @@ +V ALLIANCE : 6 +H nxr2_x1,P, 9/12/2016,100 +A 0,0,4500,5000 +R 3500,4000,ref_ref,i1_40 +R 3500,3500,ref_ref,i1_35 +R 3500,3000,ref_ref,i1_30 +R 3500,1500,ref_ref,i1_15 +R 3500,1000,ref_ref,i1_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1000,1000,ref_ref,i0_10 +R 1500,3000,ref_ref,nq_30 +R 1500,3500,ref_ref,nq_35 +R 1500,1000,ref_ref,nq_10 +R 1500,1500,ref_ref,nq_15 +R 1500,2000,ref_ref,nq_20 +R 1500,2500,ref_ref,nq_25 +R 3500,2000,ref_ref,i1_25 +R 1000,3000,ref_ref,i0_25 +S 4000,1800,4000,2000,300,*,UP,POLY +S 3000,1800,3000,2000,300,*,UP,POLY +S 1500,3500,2100,3500,200,*,RIGHT,ALU1 +S 1500,1100,1500,3500,200,nq,DOWN,CALU1 +S 1500,1000,1500,3500,200,*,UP,ALU1 +S 2700,3000,2700,4000,200,*,UP,ALU1 +S 4000,3500,4000,4000,200,*,UP,ALU1 +S 300,3500,300,4000,200,*,DOWN,ALU1 +S 2500,2000,3000,2000,200,*,RIGHT,ALU1 +S 2500,1500,2500,2000,200,*,DOWN,ALU1 +S 2000,1500,2500,1500,200,*,RIGHT,ALU1 +S 3000,1400,3600,1400,100,*,RIGHT,POLY +S 2000,2500,3500,2500,200,*,RIGHT,ALU1 +S 3000,2000,3000,2600,100,*,DOWN,POLY +S 4000,800,4000,1200,300,*,UP,NDIF +S 4000,3300,4000,4200,300,*,DOWN,PDIF +S 4000,1000,4000,3500,200,*,DOWN,ALU1 +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 3500,1000,3500,4000,200,*,DOWN,ALU1 +S 3600,2600,3600,3100,100,*,DOWN,POLY +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 3600,3100,3600,4400,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 600,2600,600,3100,100,*,DOWN,POLY +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 300,1000,300,3500,200,*,DOWN,ALU1 +S 1500,4000,2700,4000,200,*,RIGHT,ALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 0,1000,4500,1000,1800,*,RIGHT,PWELL +S 3500,1000,3500,4000,200,i1,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 3800,4700,4300,4700,300,*,RIGHT,NTIE +S 3800,300,4300,300,300,*,RIGHT,PTIE +S 1500,1000,2100,1000,200,*,RIGHT,ALU1 +S 3000,1800,4000,1800,100,*,RIGHT,POLY +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 3000,2000,CONT_POLY,* +V 4000,1000,CONT_DIF_N,* +V 4000,3500,CONT_DIF_P,* +V 4000,2000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2100,3500,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 3900,4700,CONT_BODY_N,* +V 3900,300,CONT_BODY_P,* +V 1000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x1.vbe new file mode 100644 index 000000000..1c89dd228 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY nxr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i1_nq : NATURAL := 156; + CONSTANT tphl_i0_nq : NATURAL := 288; + CONSTANT tplh_i0_nq : NATURAL := 293; + CONSTANT tplh_i1_nq : NATURAL := 327; + CONSTANT tphh_i0_nq : NATURAL := 366; + CONSTANT tpll_i0_nq : NATURAL := 389; + CONSTANT tphh_i1_nq : NATURAL := 395; + CONSTANT tpll_i1_nq : NATURAL := 503; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x1; + +ARCHITECTURE behaviour_data_flow OF nxr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x1" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1100 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x4.ap new file mode 100644 index 000000000..de458c96a --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x4.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H nxr2_x4,P, 9/12/2016,100 +A 0,0,6000,5000 +R 3500,2000,ref_ref,i1_25 +R 1000,3000,ref_ref,i0_25 +R 5000,4000,ref_ref,nq_40 +R 5000,1000,ref_ref,nq_10 +R 5000,3000,ref_ref,nq_30 +R 5000,3500,ref_ref,nq_35 +R 5000,2500,ref_ref,nq_25 +R 5000,2000,ref_ref,nq_20 +R 5000,1500,ref_ref,nq_15 +R 3500,4000,ref_ref,i1_40 +R 3500,3500,ref_ref,i1_35 +R 3500,3000,ref_ref,i1_30 +R 3500,1500,ref_ref,i1_15 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1000,1000,ref_ref,i0_10 +S 3000,1800,3000,2000,300,*,UP,POLY +S 3000,1800,4000,1800,100,*,RIGHT,POLY +S 4500,2000,5400,2000,300,*,RIGHT,POLY +S 5000,1000,5000,4000,200,nq,DOWN,CALU1 +S 3500,1500,3500,4000,200,i1,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 300,1000,300,3000,200,*,DOWN,ALU1 +S 3000,2600,3600,2600,100,*,RIGHT,POLY +S 3000,1400,3000,2000,100,*,DOWN,POLY +S 2000,1500,3500,1500,200,*,RIGHT,ALU1 +S 2500,2000,2500,2500,200,*,DOWN,ALU1 +S 2000,2500,2500,2500,200,*,RIGHT,ALU1 +S 4500,300,4500,1000,300,*,UP,NDIF +S 3900,800,3900,1600,300,*,UP,NDIF +S 1500,1000,4500,1000,200,*,RIGHT,ALU1 +S 4500,1000,4500,2000,200,*,DOWN,ALU1 +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 5400,1400,5400,2600,100,*,DOWN,POLY +S 5700,500,5700,1000,200,*,DOWN,ALU1 +S 5700,3000,5700,4500,200,*,DOWN,ALU1 +S 4500,3500,4500,4500,200,*,DOWN,ALU1 +S 3500,1500,3500,4000,200,*,DOWN,ALU1 +S 4000,1500,4000,2900,200,*,DOWN,ALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 5700,300,5700,1200,300,*,UP,NDIF +S 5100,300,5100,1200,300,*,UP,NDIF +S 5400,100,5400,1400,100,*,DOWN,NTRANS +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 3900,2800,3900,3700,300,*,DOWN,PDIF +S 4500,3400,4500,4700,300,*,DOWN,PDIF +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 600,2600,600,3900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,UP,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 5700,2800,5700,4700,300,*,DOWN,PDIF +S 2500,2000,3000,2000,200,*,RIGHT,ALU1 +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 1500,3500,2100,3500,200,*,RIGHT,ALU1 +S 1500,1000,1500,3500,200,*,UP,ALU1 +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 1500,4000,2700,4000,200,*,RIGHT,ALU1 +S 0,1000,6000,1000,1800,*,LEFT,PWELL +S 0,3900,6000,3900,2400,*,LEFT,NWELL +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +S 3900,4300,3900,4800,300,*,DOWN,NTIE +S 300,4300,300,4800,300,*,DOWN,NTIE +S 4000,1800,4000,2000,300,*,UP,POLY +V 4500,2000,CONT_POLY,* +V 4000,2900,CONT_DIF_P,* +V 4000,1500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 5100,3000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 5700,3000,CONT_DIF_P,* +V 5700,3500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 5700,4500,CONT_DIF_P,* +V 5700,1000,CONT_DIF_N,* +V 5700,500,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 300,3000,CONT_DIF_P,* +V 3000,2000,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2100,3500,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 3900,4700,CONT_BODY_N,* +V 1000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x4.vbe new file mode 100644 index 000000000..aa5ea7108 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/nxr2_x4.vbe @@ -0,0 +1,36 @@ +ENTITY nxr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tpll_i1_nq : NATURAL := 453; + CONSTANT tphh_i0_nq : NATURAL := 469; + CONSTANT tpll_i0_nq : NATURAL := 481; + CONSTANT tphl_i0_nq : NATURAL := 522; + CONSTANT tplh_i1_nq : NATURAL := 542; + CONSTANT tphl_i1_nq : NATURAL := 553; + CONSTANT tplh_i0_nq : NATURAL := 553; + CONSTANT tphh_i1_nq : NATURAL := 568; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x4; + +ARCHITECTURE behaviour_data_flow OF nxr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x4" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x2.ap new file mode 100644 index 000000000..932d47215 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x2.ap @@ -0,0 +1,70 @@ +V ALLIANCE : 6 +H o2_x2,P,22/ 7/2016,100 +A 0,0,2500,5000 +R 1500,3000,ref_ref,i0_25 +R 500,3000,ref_ref,i1_25 +R 2000,1000,ref_ref,q_10 +R 2000,4000,ref_ref,q_40 +R 2000,3500,ref_ref,q_35 +R 2000,3000,ref_ref,q_30 +R 2000,2500,ref_ref,q_25 +R 2000,2000,ref_ref,q_20 +R 2000,1500,ref_ref,q_15 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,1000,ref_ref,i0_10 +R 500,2000,ref_ref,i1_20 +R 500,1500,ref_ref,i1_15 +R 500,3500,ref_ref,i1_35 +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 2000,1100,2000,4000,200,q,DOWN,CALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 1500,1000,1500,4000,200,i0,DOWN,CALU1 +S 500,1500,500,3500,200,i1,DOWN,CALU1 +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 1000,2000,1800,2000,100,*,RIGHT,POLY +S 500,1500,500,3500,200,*,UP,ALU1 +S 600,2600,800,2600,100,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 1500,2800,1500,4700,300,*,UP,PDIF +S 500,2800,500,4200,300,*,DOWN,PDIF +S 300,2800,300,4200,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 800,2600,800,4400,100,*,UP,PTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 300,400,300,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 0,1000,2500,1000,1800,*,LEFT,PWELL +S 0,3900,2500,3900,2400,*,LEFT,NWELL +S 300,4000,900,4000,200,*,LEFT,ALU1 +S 200,4700,1000,4700,300,*,RIGHT,NTIE +V 1500,1500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2100,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 300,4700,CONT_BODY_N,* +V 1500,4500,CONT_DIF_P,* +V 1500,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 300,4000,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x2.vbe new file mode 100644 index 000000000..9e115a06f --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tpll_i0_q : NATURAL := 310; + CONSTANT tphh_i1_q : NATURAL := 335; + CONSTANT tpll_i1_q : NATURAL := 364; + CONSTANT tphh_i0_q : NATURAL := 406; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x2; + +ARCHITECTURE behaviour_data_flow OF o2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x2" + SEVERITY WARNING; + q <= (i0 or i1) after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x4.ap new file mode 100644 index 000000000..331d32fc0 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x4.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H o2_x4,P,22/ 7/2016,100 +A 0,0,3000,5000 +R 1500,3000,ref_ref,i0_25 +R 500,3000,ref_ref,i1_25 +R 2000,1000,ref_ref,q_10 +R 2000,4000,ref_ref,q_40 +R 2000,3500,ref_ref,q_35 +R 2000,3000,ref_ref,q_30 +R 2000,2500,ref_ref,q_25 +R 2000,2000,ref_ref,q_20 +R 2000,1500,ref_ref,q_15 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,1000,ref_ref,i0_10 +R 500,2000,ref_ref,i1_20 +R 500,1500,ref_ref,i1_15 +R 500,3500,ref_ref,i1_35 +S 2000,1100,2000,4000,200,q,DOWN,CALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 1500,1000,1500,4000,200,i0,DOWN,CALU1 +S 500,1500,500,3500,200,i1,DOWN,CALU1 +S 2700,3000,2700,4500,200,*,UP,ALU1 +S 2700,500,2700,1000,200,*,DOWN,ALU1 +S 1000,2000,2400,2000,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 500,1500,500,3500,200,*,UP,ALU1 +S 600,2600,800,2600,100,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 1500,2800,1500,4700,300,*,UP,PDIF +S 500,2800,500,4200,300,*,DOWN,PDIF +S 300,2800,300,4200,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 800,2600,800,4400,100,*,UP,PTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 300,400,300,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 0,1000,3000,1000,1800,*,RIGHT,PWELL +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 300,4000,900,4000,200,*,LEFT,ALU1 +S 200,4700,1000,4700,300,*,RIGHT,NTIE +S 1000,1000,1000,4000,200,*,UP,ALU1 +V 2700,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 300,4700,CONT_BODY_N,* +V 1500,4500,CONT_DIF_P,* +V 1500,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 300,4000,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 1500,2500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x4.vbe new file mode 100644 index 000000000..e22a93618 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 394; + CONSTANT tphh_i1_q : NATURAL := 427; + CONSTANT tpll_i1_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 491; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x4; + +ARCHITECTURE behaviour_data_flow OF o2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x4" + SEVERITY WARNING; + q <= (i0 or i1) after 1100 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x2.ap new file mode 100644 index 000000000..8c0f167c7 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x2.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 6 +H o3_x2,P, 9/12/2016,100 +A 0,0,3000,5000 +R 2500,1000,ref_ref,q_10 +R 2500,1500,ref_ref,q_15 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,1500,ref_ref,i2_15 +R 500,3500,ref_ref,i2_35 +R 500,3000,ref_ref,i2_30 +R 2500,2000,ref_ref,q_25 +R 1500,2000,ref_ref,i0_25 +R 1000,2000,ref_ref,i1_25 +R 500,2000,ref_ref,i2_25 +S 2000,1600,2000,1800,300,*,UP,POLY +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +S 2500,1100,2500,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i2,DOWN,CALU1 +S 0,3900,3000,3900,2400,*,LEFT,NWELL +S 0,1000,3000,1000,1800,*,LEFT,PWELL +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,400,900,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,1500,1500,3500,200,*,UP,ALU1 +S 1000,1500,1000,3500,200,*,UP,ALU1 +S 500,1500,500,3500,200,*,UP,ALU1 +S 300,1000,2000,1000,200,*,RIGHT,ALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 300,2800,300,4200,300,*,DOWN,PDIF +S 300,4000,2000,4000,200,*,LEFT,ALU1 +S 600,2600,600,4400,100,*,UP,PTRANS +S 1000,2600,1000,4400,100,*,UP,PTRANS +S 1400,2600,1400,4400,100,*,UP,PTRANS +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1600,1400,1800,1400,100,*,LEFT,POLY +S 1800,2800,1800,4700,500,*,DOWN,PDIF +S 2500,4000,2700,4000,200,*,RIGHT,ALU1 +S 2500,3500,2700,3500,200,*,LEFT,ALU1 +S 2500,3000,2700,3000,200,*,LEFT,ALU1 +S 2500,1000,2700,1000,200,*,LEFT,ALU1 +S 200,4700,1200,4700,300,*,RIGHT,NTIE +S 2400,1400,2400,1600,100,*,DOWN,POLY +S 2000,1600,2400,1600,100,*,LEFT,POLY +S 2000,2600,2400,2600,100,*,RIGHT,POLY +V 2700,1000,CONT_DIF_N,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 2100,4500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,2500,CONT_POLY,* +V 1700,4500,CONT_DIF_P,* +V 1100,4700,CONT_BODY_N,* +V 500,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1800,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x2.vbe new file mode 100644 index 000000000..5aad7aba9 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 360; + CONSTANT tpll_i0_q : NATURAL := 407; + CONSTANT tphh_i1_q : NATURAL := 430; + CONSTANT tpll_i1_q : NATURAL := 482; + CONSTANT tphh_i0_q : NATURAL := 494; + CONSTANT tpll_i2_q : NATURAL := 506; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x2; + +ARCHITECTURE behaviour_data_flow OF o3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x2" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1100 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x4.ap new file mode 100644 index 000000000..7764597d2 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x4.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H o3_x4,P,22/ 7/2016,100 +A 0,0,3500,5000 +R 1500,2000,ref_ref,i0_25 +R 1000,2000,ref_ref,i1_25 +R 500,2000,ref_ref,i2_25 +R 500,3000,ref_ref,i2_30 +R 500,3500,ref_ref,i2_35 +R 500,1500,ref_ref,i2_15 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 2500,4000,ref_ref,q_40 +R 2500,3500,ref_ref,q_35 +R 2500,3000,ref_ref,q_30 +R 2500,2500,ref_ref,q_25 +R 2500,2000,ref_ref,q_20 +R 2500,1500,ref_ref,q_15 +R 2500,1000,ref_ref,q_10 +S 200,4700,1200,4700,300,*,RIGHT,NTIE +S 500,1500,500,3500,200,i2,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 3200,3000,3200,4500,200,*,UP,ALU1 +S 3200,2800,3200,4700,300,*,UP,PDIF +S 1900,2000,2900,2000,300,*,RIGHT,POLY +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 2900,2600,2900,4900,100,*,DOWN,PTRANS +S 3200,300,3200,1200,300,*,DOWN,NDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 2900,100,2900,1400,100,*,DOWN,NTRANS +S 2600,2800,2600,4700,300,*,UP,PDIF +S 2600,300,2600,1200,300,*,DOWN,NDIF +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 2300,1400,2300,2600,100,*,DOWN,POLY +S 2300,100,2300,1400,100,*,DOWN,NTRANS +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 1800,2800,1800,4700,500,*,DOWN,PDIF +S 1600,1400,1800,1400,100,*,LEFT,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1400,2600,1400,4400,100,*,UP,PTRANS +S 1000,2600,1000,4400,100,*,UP,PTRANS +S 600,2600,600,4400,100,*,UP,PTRANS +S 300,4000,2000,4000,200,*,LEFT,ALU1 +S 300,2800,300,4200,300,*,DOWN,PDIF +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 300,1000,2000,1000,200,*,RIGHT,ALU1 +S 500,1500,500,3500,200,*,UP,ALU1 +S 1000,1500,1000,3500,200,*,UP,ALU1 +S 1500,1500,1500,3500,200,*,UP,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 900,400,900,1200,300,*,UP,NDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 0,1000,3500,1000,1800,*,RIGHT,PWELL +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +S 3200,500,3200,1000,200,*,UP,ALU1 +V 1500,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 1100,4700,CONT_BODY_N,* +V 3200,1000,CONT_DIF_N,* +V 3200,3000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 3200,4500,CONT_DIF_P,* +V 3200,500,CONT_DIF_N,* +V 2600,4000,CONT_DIF_P,* +V 2600,3500,CONT_DIF_P,* +V 2600,3000,CONT_DIF_P,* +V 2600,1000,CONT_DIF_N,* +V 2000,4500,CONT_DIF_P,* +V 2000,300,CONT_DIF_N,* +V 1500,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,4700,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x4.vbe new file mode 100644 index 000000000..1e7ea94f8 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 447; + CONSTANT tpll_i0_q : NATURAL := 501; + CONSTANT tphh_i1_q : NATURAL := 510; + CONSTANT tphh_i0_q : NATURAL := 569; + CONSTANT tpll_i1_q : NATURAL := 585; + CONSTANT tpll_i2_q : NATURAL := 622; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x4; + +ARCHITECTURE behaviour_data_flow OF o3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x4" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x2.ap new file mode 100644 index 000000000..14e083e4f --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x2.ap @@ -0,0 +1,102 @@ +V ALLIANCE : 6 +H o4_x2,P, 2/ 8/2016,100 +A 0,0,3500,5000 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 2000,1500,ref_ref,i2_15 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 3000,3000,ref_ref,q_30 +R 3000,1000,ref_ref,q_10 +R 3000,1500,ref_ref,q_15 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 500,3000,ref_ref,i3_30 +R 500,3500,ref_ref,i3_35 +R 500,1500,ref_ref,i3_15 +R 500,2000,ref_ref,i3_25 +R 1000,2000,ref_ref,i1_25 +R 1500,2000,ref_ref,i0_25 +R 2000,2000,ref_ref,i2_25 +R 3000,2000,ref_ref,q_25 +S 2100,1400,2100,1600,100,*,UP,POLY +S 200,4700,1600,4700,300,*,RIGHT,NTIE +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 2000,1500,2000,3500,200,i2,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 500,1500,500,3500,200,i3,DOWN,CALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 0,1000,3500,1000,1800,*,RIGHT,PWELL +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1500,400,1500,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 1000,1500,1000,3500,200,*,UP,ALU1 +S 1500,1500,1500,3500,200,*,UP,ALU1 +S 2000,1500,2000,3500,200,*,UP,ALU1 +S 500,1500,500,3500,200,*,UP,ALU1 +S 300,2800,300,4200,300,*,DOWN,PDIF +S 600,2600,600,4400,100,*,UP,PTRANS +S 1000,2600,1000,4400,100,*,UP,PTRANS +S 1400,2600,1400,4400,100,*,UP,PTRANS +S 2100,1400,2400,1400,100,*,RIGHT,POLY +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 2200,2800,2200,4700,500,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,DOWN,PTRANS +S 3200,2800,3200,4700,300,*,UP,PDIF +S 3200,300,3200,1200,300,*,DOWN,NDIF +S 2900,100,2900,1400,100,*,UP,NTRANS +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1600,1400,1800,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +S 300,4000,2500,4000,200,*,RIGHT,ALU1 +S 900,1000,2500,1000,200,*,LEFT,ALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3000,4000,3200,4000,200,*,LEFT,ALU1 +S 3000,3500,3200,3500,200,*,LEFT,ALU1 +S 3000,3000,3200,3000,200,*,LEFT,ALU1 +S 3000,1000,3200,1000,200,*,LEFT,ALU1 +S 2400,2500,2900,2500,300,*,RIGHT,POLY +S 2400,1700,2900,1700,300,*,RIGHT,POLY +S 2900,1400,2900,1800,100,*,DOWN,POLY +V 2000,1700,CONT_POLY,* +V 900,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 1500,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 300,4700,CONT_BODY_N,* +V 1500,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 300,4000,CONT_DIF_P,* +V 3200,1000,CONT_DIF_N,* +V 3200,4000,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 2600,300,CONT_DIF_N,* +V 2600,4500,CONT_DIF_P,* +V 2200,4500,CONT_DIF_P,* +V 500,1500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2500,1700,CONT_POLY,* +V 2500,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x2.vbe new file mode 100644 index 000000000..09652e62b --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i3_q : NATURAL := 378; + CONSTANT tphh_i1_q : NATURAL := 446; + CONSTANT tphh_i0_q : NATURAL := 508; + CONSTANT tpll_i2_q : NATURAL := 531; + CONSTANT tphh_i2_q : NATURAL := 567; + CONSTANT tpll_i0_q : NATURAL := 601; + CONSTANT tpll_i3_q : NATURAL := 626; + CONSTANT tpll_i1_q : NATURAL := 631; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x2; + +ARCHITECTURE behaviour_data_flow OF o4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x2" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x4.ap new file mode 100644 index 000000000..c960e0f1f --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x4.ap @@ -0,0 +1,115 @@ +V ALLIANCE : 6 +H o4_x4,P, 1/ 8/2016,100 +A 0,0,4000,5000 +R 2500,2000,ref_ref,i3_20 +R 2500,3500,ref_ref,i3_35 +R 2500,4000,ref_ref,i3_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2000,ref_ref,i1_20 +R 1500,2000,ref_ref,i0_20 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 1500,4000,ref_ref,i0_40 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,3500,ref_ref,i2_35 +R 2000,4000,ref_ref,i2_40 +R 3500,1500,ref_ref,q_15 +R 3500,1000,ref_ref,q_10 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 3000,3000,ref_ref,q_30 +R 1000,1500,ref_ref,i1_25 +R 1500,1500,ref_ref,i0_25 +R 2000,3000,ref_ref,i2_25 +R 2500,3000,ref_ref,i3_25 +R 3500,2000,ref_ref,q_25 +S 700,2800,700,4700,300,*,DOWN,PDIF +S 2550,300,2550,1200,200,*,UP,NDIF +S 2300,1400,2400,1400,100,*,RIGHT,POLY +S 1700,1400,1900,1400,100,*,RIGHT,POLY +S 2300,600,2300,1400,100,*,DOWN,NTRANS +S 2000,1000,2500,1000,200,*,RIGHT,ALU1 +S 1700,600,1700,1400,100,*,DOWN,NTRANS +S 1450,250,1450,1200,200,*,UP,NDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 0,1000,4000,1000,1800,*,RIGHT,PWELL +S 500,1000,500,3000,200,*,DOWN,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 300,400,300,1200,300,*,UP,NDIF +S 1000,1500,1000,4000,200,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,1500,1500,4000,200,*,UP,ALU1 +S 2000,1500,2000,4000,200,*,UP,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,2400,1100,2400,100,*,LEFT,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 2800,2600,2800,4900,100,*,DOWN,PTRANS +S 3400,2600,3400,4900,100,*,DOWN,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3100,2800,3100,4700,300,*,UP,PDIF +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 2800,100,2800,1400,100,*,UP,NTRANS +S 3400,100,3400,1400,100,*,UP,NTRANS +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 3100,300,3100,1200,300,*,DOWN,NDIF +S 2500,1500,3000,1500,200,*,LEFT,ALU1 +S 2500,1000,2500,1500,200,*,DOWN,ALU1 +S 500,1000,2500,1000,200,*,LEFT,ALU1 +S 2500,2000,2500,4000,200,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 2800,2600,3400,2600,100,*,RIGHT,POLY +S 2800,1400,3400,1400,100,*,RIGHT,POLY +S 3000,1500,3000,2500,200,*,DOWN,ALU1 +S 3100,1000,3500,1000,200,*,RIGHT,ALU1 +S 500,3000,500,4000,200,*,UP,ALU1 +S 3500,1000,3500,3000,200,*,DOWN,ALU1 +S 3100,3000,3500,3000,200,*,LEFT,ALU1 +S 3700,3500,3700,4500,200,*,UP,ALU1 +S 500,1000,900,1000,200,*,LEFT,ALU1 +S 2500,2000,2500,4000,200,i3,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 2000,1500,2000,4000,200,i2,DOWN,CALU1 +S 3000,3000,3000,4000,200,*,UP,ALU1 +S 3500,1000,3500,3000,200,q,DOWN,CALU1 +V 2000,2000,CONT_POLY,* +V 2000,1000,CONT_DIF_N,* +V 1500,300,CONT_DIF_N,* +V 500,3000,CONT_DIF_P,* +V 2500,2000,CONT_POLY,* +V 900,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3700,4500,CONT_DIF_P,* +V 3700,500,CONT_DIF_N,* +V 3000,1500,CONT_POLY,* +V 2500,4500,CONT_DIF_P,* +V 2500,300,CONT_DIF_N,* +V 3000,2500,CONT_POLY,* +V 3100,1000,CONT_DIF_N,* +V 3100,3000,CONT_DIF_P,* +V 3100,3500,CONT_DIF_P,* +V 3100,4000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x4.vbe new file mode 100644 index 000000000..bc869a8fb --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/o4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 492; + CONSTANT tpll_i3_q : NATURAL := 536; + CONSTANT tphh_i0_q : NATURAL := 574; + CONSTANT tpll_i2_q : NATURAL := 611; + CONSTANT tpll_i0_q : NATURAL := 638; + CONSTANT tphh_i2_q : NATURAL := 649; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 721; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x4; + +ARCHITECTURE behaviour_data_flow OF o4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x4" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1300 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x2.ap new file mode 100644 index 000000000..1cf956286 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x2.ap @@ -0,0 +1,99 @@ +V ALLIANCE : 6 +H oa22_x2,P,22/ 7/2016,100 +A 0,0,3000,5000 +R 2500,2000,ref_ref,q_25 +R 2000,3500,ref_ref,i2_25 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 2000,4000,ref_ref,i2_40 +R 2000,3000,ref_ref,i2_30 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 2000,1000,ref_ref,i2_10 +R 2500,1000,ref_ref,q_10 +R 2500,1500,ref_ref,q_15 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +S 2300,1400,2400,1400,100,*,RIGHT,POLY +S 2300,2600,2400,2600,100,*,RIGHT,POLY +S 1500,2000,2300,2000,100,*,RIGHT,POLY +S 2300,1400,2300,2600,100,*,UP,POLY +S 800,300,1600,300,300,*,RIGHT,PTIE +S 200,4700,1600,4700,300,*,RIGHT,NTIE +S 300,3500,300,4000,200,*,UP,ALU1 +S 1000,3000,1200,3000,300,*,RIGHT,POLY +S 1000,1500,1200,1500,300,*,RIGHT,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1800,1500,2000,1500,300,*,RIGHT,POLY +S 1800,2500,2000,2500,300,*,RIGHT,POLY +S 2500,1000,2700,1000,200,*,RIGHT,ALU1 +S 2500,3000,2700,3000,200,*,LEFT,ALU1 +S 2500,3500,2700,3500,200,*,RIGHT,ALU1 +S 2500,4000,2700,4000,200,*,RIGHT,ALU1 +S 0,1000,3000,1000,1800,*,RIGHT,PWELL +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 2100,2800,2100,4700,300,*,UP,PDIF +S 2400,2600,2400,4900,100,*,DOWN,PTRANS +S 2700,2800,2700,4700,300,*,UP,PDIF +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 1500,3300,1500,4200,300,*,UP,PDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 300,400,300,1200,300,*,DOWN,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 600,600,600,1400,100,*,UP,NTRANS +S 900,800,900,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 900,3500,1500,3500,200,*,RIGHT,ALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 300,4000,1500,4000,200,*,RIGHT,ALU1 +S 1500,1000,1500,3500,200,*,DOWN,ALU1 +S 500,1000,500,3000,200,*,UP,ALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 1000,1000,1000,3000,200,*,UP,ALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 2500,1100,2500,4000,200,q,DOWN,CALU1 +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +V 500,3000,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 300,3500,CONT_DIF_P,* +V 1500,2000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 2100,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 2100,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 900,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x2.vbe new file mode 100644 index 000000000..d2d267604 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 390; + CONSTANT tphh_i2_q : NATURAL := 438; + CONSTANT tpll_i2_q : NATURAL := 454; + CONSTANT tphh_i1_q : NATURAL := 488; + CONSTANT tpll_i1_q : NATURAL := 525; + CONSTANT tpll_i0_q : NATURAL := 555; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x2; + +ARCHITECTURE behaviour_data_flow OF oa22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x4.ap new file mode 100644 index 000000000..c0a678755 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x4.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 6 +H oa22_x4,P,22/ 7/2016,100 +A 0,0,4000,5000 +R 2000,3500,ref_ref,i2_25 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 2000,4000,ref_ref,i2_40 +R 2000,3000,ref_ref,i2_30 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 2000,1000,ref_ref,i2_10 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 3000,3000,ref_ref,q_30 +R 3000,2500,ref_ref,q_25 +R 3000,2000,ref_ref,q_20 +R 3000,1500,ref_ref,q_15 +R 3000,1000,ref_ref,q_10 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 0,1000,4000,1000,1800,*,RIGHT,PWELL +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 1000,3000,1200,3000,300,*,RIGHT,POLY +S 1000,1500,1200,1500,300,*,RIGHT,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1800,1500,2000,1500,300,*,RIGHT,POLY +S 1800,2500,2000,2500,300,*,RIGHT,POLY +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 1500,3300,1500,4200,300,*,UP,PDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 300,400,300,1200,300,*,DOWN,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 600,600,600,1400,100,*,UP,NTRANS +S 900,800,900,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 900,3500,1500,3500,200,*,RIGHT,ALU1 +S 300,4000,1500,4000,200,*,RIGHT,ALU1 +S 1500,1000,1500,3500,200,*,DOWN,ALU1 +S 500,1000,500,3000,200,*,UP,ALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 1000,1000,1000,3000,200,*,UP,ALU1 +S 3600,3000,3600,4500,200,*,UP,ALU1 +S 3600,500,3600,1000,200,*,DOWN,ALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3300,1400,3300,2600,100,*,DOWN,POLY +S 2700,1400,2700,2600,100,*,UP,POLY +S 3600,300,3600,1200,300,*,DOWN,NDIF +S 3300,100,3300,1400,100,*,UP,NTRANS +S 3000,300,3000,1200,300,*,DOWN,NDIF +S 2700,100,2700,1400,100,*,UP,NTRANS +S 2700,2600,2700,4900,100,*,DOWN,PTRANS +S 3000,2800,3000,4700,300,*,UP,PDIF +S 3600,2800,3600,4700,300,*,UP,PDIF +S 3300,2600,3300,4900,100,*,DOWN,PTRANS +S 2300,2800,2300,4700,300,*,UP,PDIF +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 1500,2000,3300,2000,200,*,RIGHT,POLY +S 200,4700,1600,4700,300,*,RIGHT,NTIE +S 800,300,1600,300,300,*,RIGHT,PTIE +V 500,3000,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 2300,500,CONT_DIF_N,* +V 2300,4500,CONT_DIF_P,* +V 1500,2000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 300,4700,CONT_BODY_N,* +V 900,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 900,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 3600,500,CONT_DIF_N,* +V 3600,1000,CONT_DIF_N,* +V 3000,1000,CONT_DIF_N,* +V 3600,4000,CONT_DIF_P,* +V 3600,4500,CONT_DIF_P,* +V 3000,3000,CONT_DIF_P,* +V 3000,3500,CONT_DIF_P,* +V 3000,4000,CONT_DIF_P,* +V 3600,3000,CONT_DIF_P,* +V 3600,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x4.vbe new file mode 100644 index 000000000..fa425e333 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 511; + CONSTANT tphh_i2_q : NATURAL := 523; + CONSTANT tpll_i2_q : NATURAL := 571; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tpll_i0_q : NATURAL := 677; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x4; + +ARCHITECTURE behaviour_data_flow OF oa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1300 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x2.ap new file mode 100644 index 000000000..015a18984 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x2.ap @@ -0,0 +1,118 @@ +V ALLIANCE : 6 +H oa2a22_x2,P, 9/12/2016,100 +A 0,0,4500,5000 +R 2500,1000,ref_ref,i3_10 +R 2500,1500,ref_ref,i3_15 +R 2500,2000,ref_ref,i3_20 +R 2500,2500,ref_ref,i3_25 +R 2500,3000,ref_ref,i3_30 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 2000,1000,ref_ref,i2_10 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +R 4000,4000,ref_ref,q_40 +R 4000,3500,ref_ref,q_35 +R 4000,3000,ref_ref,q_30 +R 4000,2000,ref_ref,q_20 +R 4000,1000,ref_ref,q_10 +R 4000,1500,ref_ref,q_15 +R 4000,2500,ref_ref,q_25 +S 1000,3000,1200,3000,300,*,RIGHT,POLY +S 1000,1500,1200,1500,300,*,RIGHT,POLY +S 1800,1500,2000,1500,300,*,LEFT,POLY +S 1800,3000,2000,3000,300,*,LEFT,POLY +S 1800,2900,1800,3100,100,*,DOWN,POLY +S 1800,1400,1800,1600,100,*,UP,POLY +S 800,300,2200,300,300,*,RIGHT,PTIE +S 200,4700,1600,4700,300,*,RIGHT,NTIE +S 2500,1000,2500,3000,200,i3,DOWN,CALU1 +S 2000,1000,2000,3000,200,i2,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 2700,400,2700,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2700,3300,2700,4200,300,*,DOWN,PDIF +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 2500,1000,2500,3000,200,*,DOWN,ALU1 +S 2000,1000,2000,3000,200,*,DOWN,ALU1 +S 300,4000,2700,4000,200,*,RIGHT,ALU1 +S 1000,1000,1000,3000,200,*,DOWN,ALU1 +S 500,1000,500,3000,200,*,UP,ALU1 +S 1500,1000,1500,3500,200,*,UP,ALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 3400,300,3400,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 900,3500,3500,3500,200,*,RIGHT,ALU1 +S 3500,2000,3500,3500,200,*,DOWN,ALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 0,1000,4500,1000,1800,*,RIGHT,PWELL +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 3500,2000,3700,2000,300,*,RIGHT,POLY +S 4100,2800,4100,4700,300,*,DOWN,PDIF +S 1200,2900,1200,3100,100,*,DOWN,POLY +S 1200,1400,1200,1600,100,*,UP,POLY +V 2500,1500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 2500,3000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 500,3000,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 4000,4000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 3500,2000,CONT_POLY,* +V 4000,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 3400,4500,CONT_DIF_P,* +V 3400,4000,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 900,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x2.vbe new file mode 100644 index 000000000..1c5c40883 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 403; + CONSTANT tpll_i2_q : NATURAL := 487; + CONSTANT tphh_i1_q : NATURAL := 495; + CONSTANT tpll_i3_q : NATURAL := 512; + CONSTANT tpll_i1_q : NATURAL := 534; + CONSTANT tphh_i3_q : NATURAL := 537; + CONSTANT tpll_i0_q : NATURAL := 564; + CONSTANT tphh_i2_q : NATURAL := 646; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1200 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x4.ap new file mode 100644 index 000000000..b14aa9089 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x4.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H oa2a22_x4,P, 9/12/2016,100 +A 0,0,5000,5000 +R 2500,1000,ref_ref,i3_10 +R 2500,1500,ref_ref,i3_15 +R 2500,2000,ref_ref,i3_20 +R 2500,2500,ref_ref,i3_25 +R 2500,3000,ref_ref,i3_30 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 2000,1000,ref_ref,i2_10 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +R 4000,4000,ref_ref,q_40 +R 4000,3500,ref_ref,q_35 +R 4000,3000,ref_ref,q_30 +R 4000,2000,ref_ref,q_20 +R 4000,1000,ref_ref,q_10 +R 4000,1500,ref_ref,q_15 +R 4000,2500,ref_ref,q_25 +S 3500,2000,3700,2000,300,*,LEFT,POLY +S 1000,1500,1200,1500,300,*,LEFT,POLY +S 1800,1500,2000,1500,300,*,LEFT,POLY +S 1000,3000,1200,3000,300,*,LEFT,POLY +S 1800,3000,2000,3000,300,*,RIGHT,POLY +S 800,300,2200,300,300,*,RIGHT,PTIE +S 200,4700,1600,4700,300,*,RIGHT,NTIE +S 2700,400,2700,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2700,3300,2700,4200,300,*,DOWN,PDIF +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 2500,1000,2500,3000,200,*,DOWN,ALU1 +S 2000,1000,2000,3000,200,*,DOWN,ALU1 +S 300,4000,2700,4000,200,*,RIGHT,ALU1 +S 1000,1000,1000,3000,200,*,DOWN,ALU1 +S 500,1000,500,3000,200,*,UP,ALU1 +S 1500,1000,1500,3500,200,*,UP,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,1000,5000,1000,1800,*,RIGHT,PWELL +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 3400,300,3400,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 4600,300,4600,1200,300,*,UP,NDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 900,3500,3500,3500,200,*,RIGHT,ALU1 +S 3500,2000,3500,3500,200,*,DOWN,ALU1 +S 3500,2000,4300,2000,100,*,RIGHT,POLY +S 2500,1000,2500,3000,200,i3,DOWN,CALU1 +S 2000,1000,2000,3000,200,i2,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 1200,2900,1200,3100,100,*,DOWN,POLY +S 1800,2900,1800,3100,100,*,DOWN,POLY +S 1800,1400,1800,1600,100,*,UP,POLY +S 1200,1400,1200,1600,100,*,UP,POLY +V 4000,4000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 3500,2000,CONT_POLY,* +V 4000,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 4600,500,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 3400,4500,CONT_DIF_P,* +V 3400,4000,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 900,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +V 500,1500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 500,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 2500,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x4.vbe new file mode 100644 index 000000000..a233499c0 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 519; + CONSTANT tpll_i2_q : NATURAL := 596; + CONSTANT tpll_i3_q : NATURAL := 619; + CONSTANT tphh_i1_q : NATURAL := 624; + CONSTANT tphh_i3_q : NATURAL := 644; + CONSTANT tpll_i1_q : NATURAL := 669; + CONSTANT tpll_i0_q : NATURAL := 696; + CONSTANT tphh_i2_q : NATURAL := 763; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x2.ap new file mode 100644 index 000000000..539913520 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x2.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 6 +H oa2a2a23_x2,P,22/ 7/2016,100 +A 0,0,6000,5000 +R 4500,2000,ref_ref,i0_25 +R 4000,2000,ref_ref,i1_25 +R 2500,2000,ref_ref,i2_25 +R 2000,3000,ref_ref,i3_25 +R 1500,2000,ref_ref,i4_25 +R 1000,2000,ref_ref,i5_25 +R 4500,1500,ref_ref,i0_15 +R 4500,3000,ref_ref,i0_30 +R 4000,3000,ref_ref,i1_30 +R 4000,1500,ref_ref,i1_15 +R 5500,1000,ref_ref,q_10 +R 5500,1500,ref_ref,q_15 +R 5500,3500,ref_ref,q_35 +R 5500,3000,ref_ref,q_30 +R 5500,2500,ref_ref,q_25 +R 5500,2000,ref_ref,q_20 +R 1500,3500,ref_ref,i4_35 +R 1500,3000,ref_ref,i4_30 +R 1500,1500,ref_ref,i4_15 +R 2000,2000,ref_ref,i3_20 +R 2500,3000,ref_ref,i2_30 +R 2500,1500,ref_ref,i2_15 +R 2000,1500,ref_ref,i3_15 +R 1000,1500,ref_ref,i5_15 +R 1000,3000,ref_ref,i5_30 +R 5500,4000,ref_ref,q_40 +S 300,1000,300,3500,200,*,DOWN,ALU1 +S 3700,4000,3700,4600,200,*,DOWN,ALU1 +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3200,300,3200,800,300,*,UP,PTIE +S 5000,2000,5200,2000,300,*,RIGHT,POLY +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 0,1000,6000,1000,1800,*,RIGHT,PWELL +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 5200,1400,5200,2600,100,*,DOWN,POLY +S 5000,1000,5000,2000,200,*,UP,ALU1 +S 500,1000,5000,1000,200,*,RIGHT,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2100,3500,4300,3500,200,*,RIGHT,ALU1 +S 4000,1400,4200,1400,100,*,LEFT,POLY +S 4500,1500,4500,3000,200,*,UP,ALU1 +S 4000,1500,4000,3000,200,*,UP,ALU1 +S 5200,2600,5200,4900,100,*,UP,PTRANS +S 5500,2800,5500,4700,300,*,UP,PDIF +S 4900,2800,4900,4700,300,*,UP,PDIF +S 4300,2800,4300,4700,300,*,UP,PDIF +S 4600,2600,4600,4900,100,*,UP,PTRANS +S 4000,2600,4000,4900,100,*,UP,PTRANS +S 4900,300,4900,1200,300,*,DOWN,NDIF +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5200,100,5200,1400,100,*,UP,NTRANS +S 4600,100,4600,1400,100,*,UP,NTRANS +S 4200,100,4200,1400,100,*,UP,NTRANS +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 4300,3500,4300,4000,200,*,UP,ALU1 +S 4900,3500,4900,4600,200,*,DOWN,ALU1 +S 1500,1500,1500,3500,200,*,UP,ALU1 +S 800,1400,900,1400,100,*,LEFT,POLY +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,100,800,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 600,2600,900,2600,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 2500,1500,2500,3000,200,*,UP,ALU1 +S 2000,1500,2000,3000,200,*,UP,ALU1 +S 1000,1500,1000,3000,200,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 300,4000,2700,4000,200,*,RIGHT,ALU1 +S 4500,1500,4500,3000,200,i0,DOWN,CALU1 +S 4000,1500,4000,3000,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +S 5500,1100,5500,4000,200,q,DOWN,CALU1 +S 5500,1000,5500,4000,200,*,DOWN,ALU1 +S 500,3500,900,3500,200,*,LEFT,ALU1 +V 4500,1500,CONT_POLY,* +V 4000,1500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 800,2500,CONT_POLY,* +V 800,1500,CONT_POLY,* +V 3700,4000,CONT_DIF_P,* +V 3700,4500,CONT_DIF_P,* +V 5000,2000,CONT_POLY,* +V 3200,400,CONT_BODY_P,* +V 4000,2500,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 5500,3000,CONT_DIF_P,* +V 5500,3500,CONT_DIF_P,* +V 5500,4000,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 4900,4500,CONT_DIF_P,* +V 4900,3500,CONT_DIF_P,* +V 4300,4000,CONT_DIF_P,* +V 5500,1000,CONT_DIF_N,* +V 4900,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 2000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x2.vbe new file mode 100644 index 000000000..189ed7159 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x2.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT tphh_i5_q : NATURAL := 321; + CONSTANT tphh_i4_q : NATURAL := 402; + CONSTANT tphh_i2_q : NATURAL := 441; + CONSTANT tphh_i3_q : NATURAL := 540; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT tpll_i4_q : NATURAL := 591; + CONSTANT tpll_i3_q : NATURAL := 600; + CONSTANT tpll_i5_q : NATURAL := 636; + CONSTANT tpll_i2_q : NATURAL := 639; + CONSTANT tphh_i0_q : NATURAL := 653; + CONSTANT tphh_i1_q : NATURAL := 775; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x2" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x4.ap new file mode 100644 index 000000000..c08f5f180 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x4.ap @@ -0,0 +1,143 @@ +V ALLIANCE : 6 +H oa2a2a23_x4,P, 9/12/2016,100 +A 0,0,6500,5000 +R 5500,4000,ref_ref,q_40 +R 1000,3000,ref_ref,i5_30 +R 1000,1500,ref_ref,i5_15 +R 2000,1500,ref_ref,i3_15 +R 2500,1500,ref_ref,i2_15 +R 2500,3000,ref_ref,i2_30 +R 2000,2000,ref_ref,i3_20 +R 1500,1500,ref_ref,i4_15 +R 1500,3000,ref_ref,i4_30 +R 1500,3500,ref_ref,i4_35 +R 5500,2000,ref_ref,q_20 +R 5500,2500,ref_ref,q_25 +R 5500,3000,ref_ref,q_30 +R 5500,3500,ref_ref,q_35 +R 5500,1500,ref_ref,q_15 +R 5500,1000,ref_ref,q_10 +R 4000,1500,ref_ref,i1_15 +R 4000,3000,ref_ref,i1_30 +R 4500,3000,ref_ref,i0_30 +R 4500,1500,ref_ref,i0_15 +R 4500,2000,ref_ref,i0_25 +R 4000,2000,ref_ref,i1_25 +R 2500,2000,ref_ref,i2_25 +R 2000,3000,ref_ref,i3_25 +R 1500,2000,ref_ref,i4_25 +R 1000,2000,ref_ref,i5_25 +S 5000,2000,5200,2000,300,*,LEFT,POLY +S 500,3500,900,3500,200,*,LEFT,ALU1 +S 5500,1100,5500,4000,200,q,DOWN,CALU1 +S 5500,1000,5500,4000,200,*,DOWN,ALU1 +S 300,4000,2700,4000,200,*,RIGHT,ALU1 +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1000,1500,1000,3000,200,*,UP,ALU1 +S 2000,1500,2000,3000,200,*,UP,ALU1 +S 2500,1500,2500,3000,200,*,UP,ALU1 +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 800,100,800,1400,100,*,UP,NTRANS +S 500,300,500,1200,300,*,DOWN,NDIF +S 1500,1500,1500,3500,200,*,UP,ALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 0,1000,6500,1000,1800,*,RIGHT,PWELL +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 4900,3500,4900,4600,200,*,DOWN,ALU1 +S 4300,3500,4300,4000,200,*,UP,ALU1 +S 6100,3500,6100,4600,200,*,DOWN,ALU1 +S 6100,300,6100,1000,200,*,DOWN,ALU1 +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 4200,100,4200,1400,100,*,UP,NTRANS +S 4600,100,4600,1400,100,*,UP,NTRANS +S 5800,100,5800,1400,100,*,DOWN,NTRANS +S 5200,100,5200,1400,100,*,UP,NTRANS +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 6100,300,6100,1200,300,*,DOWN,NDIF +S 4900,300,4900,1200,300,*,DOWN,NDIF +S 4000,2600,4000,4900,100,*,UP,PTRANS +S 4600,2600,4600,4900,100,*,UP,PTRANS +S 4300,2800,4300,4700,300,*,UP,PDIF +S 4900,2800,4900,4700,300,*,UP,PDIF +S 6100,2800,6100,4700,300,*,UP,PDIF +S 5500,2800,5500,4700,300,*,UP,PDIF +S 5800,2600,5800,4900,100,*,UP,PTRANS +S 5200,2600,5200,4900,100,*,UP,PTRANS +S 4000,1500,4000,3000,200,*,UP,ALU1 +S 4500,1500,4500,3000,200,*,UP,ALU1 +S 4000,1400,4200,1400,100,*,LEFT,POLY +S 2100,3500,4300,3500,200,*,RIGHT,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 500,1000,5000,1000,200,*,RIGHT,ALU1 +S 5000,1000,5000,2000,200,*,UP,ALU1 +S 5200,1400,5200,2600,100,*,DOWN,POLY +S 5800,1400,5800,2600,100,*,DOWN,POLY +S 5000,2000,5800,2000,100,*,RIGHT,POLY +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 4500,1500,4500,3000,200,i0,DOWN,CALU1 +S 4000,1500,4000,3000,200,i1,DOWN,CALU1 +S 3700,4000,3700,4600,200,*,UP,ALU1 +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3200,300,3200,800,300,*,UP,PTIE +S 300,1000,300,3500,200,*,DOWN,ALU1 +S 600,2600,800,2600,100,*,RIGHT,POLY +V 1500,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2500,2500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2500,500,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 4900,500,CONT_DIF_N,* +V 5500,1000,CONT_DIF_N,* +V 6100,1000,CONT_DIF_N,* +V 6100,500,CONT_DIF_N,* +V 3700,4000,CONT_DIF_P,* +V 4300,4000,CONT_DIF_P,* +V 4900,3500,CONT_DIF_P,* +V 4900,4500,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 5500,4000,CONT_DIF_P,* +V 5500,3500,CONT_DIF_P,* +V 5500,3000,CONT_DIF_P,* +V 6100,4000,CONT_DIF_P,* +V 6100,4500,CONT_DIF_P,* +V 6100,3500,CONT_DIF_P,* +V 4500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 3200,400,CONT_BODY_P,* +V 5000,2000,CONT_POLY,* +V 3700,4500,CONT_DIF_P,* +V 800,1500,CONT_POLY,* +V 800,2500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 4000,1500,CONT_POLY,* +V 4500,1500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x4.vbe new file mode 100644 index 000000000..c39f56f93 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT tphh_i5_q : NATURAL := 379; + CONSTANT tphh_i4_q : NATURAL := 464; + CONSTANT tphh_i2_q : NATURAL := 493; + CONSTANT tphh_i3_q : NATURAL := 594; + CONSTANT tpll_i1_q : NATURAL := 613; + CONSTANT tpll_i0_q : NATURAL := 648; + CONSTANT tpll_i4_q : NATURAL := 673; + CONSTANT tpll_i3_q : NATURAL := 677; + CONSTANT tphh_i0_q : NATURAL := 699; + CONSTANT tpll_i5_q : NATURAL := 714; + CONSTANT tpll_i2_q : NATURAL := 715; + CONSTANT tphh_i1_q : NATURAL := 822; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x4" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x2.ap new file mode 100644 index 000000000..8e8f1830a --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x2.ap @@ -0,0 +1,167 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x2,P, 9/12/2016,100 +A 0,0,7500,5000 +R 4000,3000,ref_ref,i2_30 +R 4000,1500,ref_ref,i2_15 +R 3500,3000,ref_ref,i3_30 +R 3500,1500,ref_ref,i3_15 +R 3000,3000,ref_ref,i4_30 +R 3000,1500,ref_ref,i4_15 +R 2500,3000,ref_ref,i5_30 +R 2500,1500,ref_ref,i5_15 +R 1500,3000,ref_ref,i6_30 +R 1500,1500,ref_ref,i6_15 +R 500,3000,ref_ref,i7_30 +R 500,1500,ref_ref,i7_15 +R 500,1000,ref_ref,i7_10 +R 7000,2500,ref_ref,q_25 +R 7000,3000,ref_ref,q_30 +R 7000,3500,ref_ref,q_35 +R 7000,1500,ref_ref,q_15 +R 7000,2000,ref_ref,q_20 +R 7000,4000,ref_ref,q_40 +R 7000,1000,ref_ref,q_10 +R 6500,3000,ref_ref,i0_30 +R 6500,1500,ref_ref,i0_15 +R 5500,1500,ref_ref,i1_15 +R 5500,3000,ref_ref,i1_30 +R 6500,3500,ref_ref,i0_35 +R 5500,2000,ref_ref,i1_25 +R 6500,2000,ref_ref,i0_25 +R 4000,2000,ref_ref,i2_25 +R 3500,2000,ref_ref,i3_25 +R 3000,2000,ref_ref,i4_25 +R 2500,2000,ref_ref,i5_25 +R 1500,2000,ref_ref,i6_25 +R 500,2000,ref_ref,i7_25 +S 4800,1800,4800,2000,300,*,UP,POLY +S 7000,1100,7000,4000,200,q,DOWN,CALU1 +S 7000,1000,7000,4000,200,*,DOWN,ALU1 +S 0,4700,7500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,7500,3900,2400,*,RIGHT,NWELL +S 0,1000,7500,1000,1800,*,RIGHT,PWELL +S 0,300,7500,300,600,vss,RIGHT,CALU1 +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 1500,3500,1500,4000,200,*,DOWN,ALU1 +S 300,4000,1500,4000,200,*,RIGHT,ALU1 +S 2100,4000,4500,4000,200,*,RIGHT,ALU1 +S 1500,3500,2700,3500,200,*,RIGHT,ALU1 +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1500,1500,1500,3000,200,*,UP,ALU1 +S 2500,1500,2500,3000,200,*,UP,ALU1 +S 3000,1500,3000,3000,200,*,UP,ALU1 +S 3500,1500,3500,3000,200,*,UP,ALU1 +S 4000,1500,4000,3000,200,*,UP,ALU1 +S 500,1000,500,3000,200,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 3300,3500,3300,4000,200,*,UP,ALU1 +S 300,3500,300,4000,200,*,UP,ALU1 +S 900,3500,1000,3500,200,*,RIGHT,ALU1 +S 1000,1000,1000,3500,200,*,DOWN,ALU1 +S 6800,1400,6800,2600,100,*,DOWN,POLY +S 6800,100,6800,1400,100,*,UP,NTRANS +S 7100,300,7100,1200,300,*,DOWN,NDIF +S 6200,100,6200,1400,100,*,UP,NTRANS +S 6500,300,6500,1200,300,*,DOWN,NDIF +S 5900,2800,5900,4700,300,*,UP,PDIF +S 6200,2600,6200,4900,100,*,UP,PTRANS +S 5600,2600,5600,4900,100,*,UP,PTRANS +S 6500,2800,6500,4700,300,*,UP,PDIF +S 6800,2600,6800,4900,100,*,UP,PTRANS +S 7100,2800,7100,4700,300,*,UP,PDIF +S 3900,3500,5900,3500,200,*,RIGHT,ALU1 +S 5900,3500,5900,4000,200,*,UP,ALU1 +S 6500,4000,6500,4600,200,*,DOWN,ALU1 +S 5300,4000,5300,4600,200,*,DOWN,ALU1 +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5800,100,5800,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2600,100,2600,1400,100,*,UP,NTRANS +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 1000,1000,5500,1000,200,*,RIGHT,ALU1 +S 6300,2500,6500,2500,200,*,RIGHT,ALU1 +S 6300,1500,6500,1500,200,*,RIGHT,ALU1 +S 4800,1000,4800,2000,200,*,UP,ALU1 +S 5500,1500,5500,3000,200,*,UP,ALU1 +S 5500,1500,5700,1500,200,*,RIGHT,ALU1 +S 6500,1500,6500,3500,200,*,UP,ALU1 +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +S 6500,1500,6500,3500,200,i0,DOWN,CALU1 +S 5500,1500,5500,3000,200,i1,DOWN,CALU1 +S 4900,300,4900,800,300,*,UP,PTIE +S 4500,2800,4500,4700,300,*,UP,PDIF +S 5300,2800,5300,4700,300,*,UP,PDIF +S 1200,1500,1500,1500,300,*,LEFT,POLY +S 4700,1800,6800,1800,100,*,RIGHT,POLY +V 3300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 3300,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 7100,1000,CONT_DIF_N,* +V 6500,500,CONT_DIF_N,* +V 6500,4000,CONT_DIF_P,* +V 7100,4000,CONT_DIF_P,* +V 6500,4500,CONT_DIF_P,* +V 7100,3500,CONT_DIF_P,* +V 7100,3000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 5900,4000,CONT_DIF_P,* +V 5300,4000,CONT_DIF_P,* +V 5500,1000,CONT_DIF_N,* +V 4300,500,CONT_DIF_N,* +V 2300,500,CONT_DIF_N,* +V 4900,400,CONT_BODY_P,* +V 6300,1500,CONT_POLY,* +V 6300,2500,CONT_POLY,* +V 4800,2000,CONT_POLY,* +V 5500,2500,CONT_POLY,* +V 5700,1500,CONT_POLY,* +V 5300,4500,CONT_DIF_P,* +V 500,1500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 4000,1500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x2.vbe new file mode 100644 index 000000000..39a24492c --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x2.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rdown_i7_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT rup_i7_q : NATURAL := 1790; + CONSTANT tphh_i7_q : NATURAL := 346; + CONSTANT tphh_i6_q : NATURAL := 426; + CONSTANT tphh_i5_q : NATURAL := 467; + CONSTANT tphh_i4_q : NATURAL := 565; + CONSTANT tphh_i2_q : NATURAL := 682; + CONSTANT tpll_i6_q : NATURAL := 748; + CONSTANT tpll_i1_q : NATURAL := 753; + CONSTANT tphh_i0_q : NATURAL := 780; + CONSTANT tpll_i0_q : NATURAL := 797; + CONSTANT tpll_i7_q : NATURAL := 800; + CONSTANT tphh_i3_q : NATURAL := 803; + CONSTANT tpll_i3_q : NATURAL := 810; + CONSTANT tpll_i4_q : NATURAL := 813; + CONSTANT tpll_i2_q : NATURAL := 856; + CONSTANT tpll_i5_q : NATURAL := 861; + CONSTANT tphh_i1_q : NATURAL := 909; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x2" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1500 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x4.ap new file mode 100644 index 000000000..a912c6fd8 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x4.ap @@ -0,0 +1,179 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x4,P, 9/12/2016,100 +A 0,0,8000,5000 +R 4000,3000,ref_ref,i2_30 +R 4000,1500,ref_ref,i2_15 +R 3500,3000,ref_ref,i3_30 +R 3500,1500,ref_ref,i3_15 +R 3000,3000,ref_ref,i4_30 +R 3000,1500,ref_ref,i4_15 +R 2500,3000,ref_ref,i5_30 +R 2500,1500,ref_ref,i5_15 +R 1500,3000,ref_ref,i6_30 +R 1500,1500,ref_ref,i6_15 +R 500,3000,ref_ref,i7_30 +R 500,1500,ref_ref,i7_15 +R 500,1000,ref_ref,i7_10 +R 7000,2500,ref_ref,q_25 +R 7000,3000,ref_ref,q_30 +R 7000,3500,ref_ref,q_35 +R 7000,1500,ref_ref,q_15 +R 7000,2000,ref_ref,q_20 +R 7000,4000,ref_ref,q_40 +R 7000,1000,ref_ref,q_10 +R 6500,2000,ref_ref,i0_20 +R 6500,1500,ref_ref,i0_15 +R 5500,1500,ref_ref,i1_15 +R 5500,3000,ref_ref,i1_30 +R 6500,3500,ref_ref,i0_35 +R 6500,3000,ref_ref,i0_25 +R 5500,2000,ref_ref,i1_25 +R 4000,2000,ref_ref,i2_25 +R 3500,2000,ref_ref,i3_25 +R 3000,2000,ref_ref,i4_25 +R 2500,2000,ref_ref,i5_25 +R 1500,2000,ref_ref,i6_25 +R 500,2000,ref_ref,i7_25 +S 4800,1800,4800,2000,300,*,UP,POLY +S 7000,1000,7000,4000,200,*,DOWN,ALU1 +S 7000,1100,7000,4000,200,q,DOWN,CALU1 +S 4900,300,4900,800,300,*,UP,PTIE +S 4500,2800,4500,4700,300,*,UP,PDIF +S 5300,2800,5300,4700,300,*,UP,PDIF +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +S 5500,1500,5500,3000,200,i1,DOWN,CALU1 +S 6500,1500,6500,3500,200,i0,DOWN,CALU1 +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 1500,3500,1500,4000,200,*,DOWN,ALU1 +S 300,4000,1500,4000,200,*,RIGHT,ALU1 +S 2100,4000,4500,4000,200,*,RIGHT,ALU1 +S 1500,3500,2700,3500,200,*,RIGHT,ALU1 +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1500,1500,1500,3000,200,*,UP,ALU1 +S 2500,1500,2500,3000,200,*,UP,ALU1 +S 3000,1500,3000,3000,200,*,UP,ALU1 +S 3500,1500,3500,3000,200,*,UP,ALU1 +S 4000,1500,4000,3000,200,*,UP,ALU1 +S 500,1000,500,3000,200,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 3300,3500,3300,4000,200,*,UP,ALU1 +S 300,3500,300,4000,200,*,UP,ALU1 +S 0,300,8000,300,600,vss,RIGHT,CALU1 +S 0,3900,8000,3900,2400,*,RIGHT,NWELL +S 0,1000,8000,1000,1800,*,RIGHT,PWELL +S 0,4700,8000,4700,600,vdd,RIGHT,CALU1 +S 900,3500,1000,3500,200,*,RIGHT,ALU1 +S 1000,1000,1000,3500,200,*,DOWN,ALU1 +S 7700,3500,7700,4600,200,*,DOWN,ALU1 +S 7700,300,7700,1000,200,*,DOWN,ALU1 +S 7400,1400,7400,2600,100,*,DOWN,POLY +S 6800,1400,6800,2600,100,*,DOWN,POLY +S 6800,100,6800,1400,100,*,UP,NTRANS +S 7100,300,7100,1200,300,*,DOWN,NDIF +S 6200,100,6200,1400,100,*,UP,NTRANS +S 7700,300,7700,1200,300,*,DOWN,NDIF +S 6500,300,6500,1200,300,*,DOWN,NDIF +S 7400,100,7400,1400,100,*,DOWN,NTRANS +S 5900,2800,5900,4700,300,*,UP,PDIF +S 6200,2600,6200,4900,100,*,UP,PTRANS +S 5600,2600,5600,4900,100,*,UP,PTRANS +S 7400,2600,7400,4900,100,*,UP,PTRANS +S 6500,2800,6500,4700,300,*,UP,PDIF +S 6800,2600,6800,4900,100,*,UP,PTRANS +S 7700,2800,7700,4700,300,*,UP,PDIF +S 7100,2800,7100,4700,300,*,UP,PDIF +S 3900,3500,5900,3500,200,*,RIGHT,ALU1 +S 5900,3500,5900,4000,200,*,UP,ALU1 +S 6500,4000,6500,4600,200,*,DOWN,ALU1 +S 5300,4000,5300,4600,200,*,DOWN,ALU1 +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5800,100,5800,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2600,100,2600,1400,100,*,UP,NTRANS +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 1000,1000,5500,1000,200,*,RIGHT,ALU1 +S 6300,2500,6500,2500,200,*,RIGHT,ALU1 +S 6300,1500,6500,1500,200,*,RIGHT,ALU1 +S 4800,1000,4800,2000,200,*,UP,ALU1 +S 5500,1500,5500,3000,200,*,UP,ALU1 +S 5500,1500,5700,1500,200,*,RIGHT,ALU1 +S 6500,1500,6500,3500,200,*,UP,ALU1 +S 1200,1500,1500,1500,300,*,LEFT,POLY +S 4700,1800,7400,1800,100,*,RIGHT,POLY +V 5300,4500,CONT_DIF_P,* +V 3300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 3300,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 7700,500,CONT_DIF_N,* +V 7100,1000,CONT_DIF_N,* +V 6500,500,CONT_DIF_N,* +V 7700,1000,CONT_DIF_N,* +V 7700,4500,CONT_DIF_P,* +V 7700,3500,CONT_DIF_P,* +V 6500,4000,CONT_DIF_P,* +V 7100,4000,CONT_DIF_P,* +V 6500,4500,CONT_DIF_P,* +V 7100,3500,CONT_DIF_P,* +V 7100,3000,CONT_DIF_P,* +V 7700,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 5900,4000,CONT_DIF_P,* +V 5300,4000,CONT_DIF_P,* +V 5500,1000,CONT_DIF_N,* +V 4300,500,CONT_DIF_N,* +V 2300,500,CONT_DIF_N,* +V 4900,400,CONT_BODY_P,* +V 6300,1500,CONT_POLY,* +V 6300,2500,CONT_POLY,* +V 4800,2000,CONT_POLY,* +V 5500,2500,CONT_POLY,* +V 5700,1500,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 4000,1500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x4.vbe new file mode 100644 index 000000000..33d168440 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa2a2a2a24_x4.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rdown_i7_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT rup_i7_q : NATURAL := 890; + CONSTANT tphh_i7_q : NATURAL := 399; + CONSTANT tphh_i6_q : NATURAL := 487; + CONSTANT tphh_i5_q : NATURAL := 515; + CONSTANT tphh_i4_q : NATURAL := 619; + CONSTANT tphh_i2_q : NATURAL := 726; + CONSTANT tphh_i0_q : NATURAL := 823; + CONSTANT tpll_i1_q : NATURAL := 835; + CONSTANT tpll_i6_q : NATURAL := 845; + CONSTANT tphh_i3_q : NATURAL := 851; + CONSTANT tpll_i0_q : NATURAL := 879; + CONSTANT tpll_i3_q : NATURAL := 895; + CONSTANT tpll_i7_q : NATURAL := 895; + CONSTANT tpll_i4_q : NATURAL := 902; + CONSTANT tpll_i2_q : NATURAL := 940; + CONSTANT tpll_i5_q : NATURAL := 949; + CONSTANT tphh_i1_q : NATURAL := 955; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x4" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1600 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x2.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x2.ap new file mode 100644 index 000000000..0246a3f94 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x2.ap @@ -0,0 +1,160 @@ +V ALLIANCE : 6 +H oa3ao322_x2,P, 9/12/2016,100 +A 0,0,5500,5000 +R 500,3500,ref_ref,q_35 +R 500,3000,ref_ref,q_30 +R 500,2500,ref_ref,q_25 +R 500,2000,ref_ref,q_20 +R 500,1500,ref_ref,q_15 +R 500,1000,ref_ref,q_10 +R 500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,i0_35 +R 4000,3500,ref_ref,i3_35 +R 5000,3000,ref_ref,i5_30 +R 5000,3500,ref_ref,i5_35 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 4000,3000,ref_ref,i3_30 +R 4500,1500,ref_ref,i4_15 +R 4500,3000,ref_ref,i4_30 +R 4500,3500,ref_ref,i4_35 +R 5000,1500,ref_ref,i5_15 +R 4000,1500,ref_ref,i3_15 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2500,3500,ref_ref,i2_35 +R 3000,2000,ref_ref,i6_20 +R 3000,2500,ref_ref,i6_25 +R 3000,3000,ref_ref,i6_30 +R 3000,3500,ref_ref,i6_35 +R 2000,1500,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_20 +R 2000,2500,ref_ref,i1_25 +R 2000,3000,ref_ref,i1_30 +R 2000,3500,ref_ref,i1_35 +R 2500,2000,ref_ref,i2_20 +R 4000,2000,ref_ref,i3_25 +R 4500,2000,ref_ref,i4_25 +R 5000,2000,ref_ref,i5_25 +S 3000,2800,3200,2800,300,*,LEFT,POLY +S 4300,1500,4500,1500,300,*,LEFT,POLY +S 1100,2800,1100,4700,200,*,DOWN,PDIF +S 3000,2000,3200,2000,300,*,RIGHT,POLY +S 800,2000,1000,2000,300,*,LEFT,POLY +S 500,1000,500,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 4500,1500,4500,3500,200,i4,DOWN,CALU1 +S 5000,1500,5000,3500,200,i5,DOWN,CALU1 +S 4000,1500,4000,3500,200,i3,DOWN,CALU1 +S 3000,2000,3000,3500,200,i6,DOWN,CALU1 +S 2000,1500,2000,3500,200,i1,DOWN,CALU1 +S 2500,2000,2500,3500,200,i2,DOWN,CALU1 +S 3100,1900,3200,1900,100,*,LEFT,POLY +S 1400,1900,1500,1900,100,*,RIGHT,POLY +S 800,2600,800,4900,100,*,UP,PTRANS +S 500,2800,500,4700,300,*,DOWN,PDIF +S 500,800,500,1700,300,*,UP,NDIF +S 800,600,800,1900,100,*,DOWN,NTRANS +S 1200,500,1200,1700,300,*,UP,NDIF +S 4700,400,5100,400,300,*,RIGHT,PTIE +S 800,1900,800,2600,100,*,DOWN,POLY +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 500,1000,500,4000,200,*,UP,ALU1 +S 1100,4000,1100,4700,200,*,UP,ALU1 +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 1000,1000,1000,2000,200,*,UP,ALU1 +S 3400,1000,4600,1000,200,*,RIGHT,ALU1 +S 4000,1500,4000,3500,200,*,UP,ALU1 +S 3500,1500,3500,3500,200,*,DOWN,ALU1 +S 1500,1500,1500,3500,200,*,DOWN,ALU1 +S 2000,1500,2000,3500,200,*,DOWN,ALU1 +S 4500,1500,4500,3500,200,*,UP,ALU1 +S 3000,2000,3000,3500,200,*,UP,ALU1 +S 5200,300,5200,1000,200,*,DOWN,ALU1 +S 5000,1500,5000,3500,200,*,DOWN,ALU1 +S 2500,2000,2500,3500,200,*,UP,ALU1 +S 2800,1000,2800,1500,200,*,UP,ALU1 +S 2800,1500,3500,1500,200,*,RIGHT,ALU1 +S 1000,1000,2800,1000,200,*,LEFT,ALU1 +S 1700,4000,5200,4000,200,*,RIGHT,ALU1 +S 3900,2600,3900,4400,100,*,UP,PTRANS +S 4400,2600,4400,4400,100,*,UP,PTRANS +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 3100,700,3100,1600,100,*,UP,NTRANS +S 3700,700,3700,1400,100,*,UP,NTRANS +S 4300,700,4300,1400,100,*,UP,NTRANS +S 4900,700,4900,1400,100,*,UP,NTRANS +S 5200,900,5200,1200,300,*,UP,NDIF +S 4600,900,4600,1200,300,*,UP,NDIF +S 4000,400,4000,1200,300,*,DOWN,NDIF +S 3400,900,3400,1400,200,*,UP,NDIF +S 2800,900,2800,1400,200,*,UP,NDIF +S 3100,1600,3100,1900,100,*,UP,POLY +S 1400,3000,1400,4400,100,*,UP,PTRANS +S 2000,3000,2000,4400,100,*,UP,PTRANS +S 2600,3000,2600,4400,100,*,UP,PTRANS +S 3200,2900,3200,4400,100,*,UP,PTRANS +S 5200,2800,5200,4200,300,*,UP,PDIF +S 1700,3200,1700,4200,300,*,UP,PDIF +S 2300,3200,2300,4500,300,*,DOWN,PDIF +S 2900,3100,2900,4200,200,*,UP,PDIF +S 3500,3100,3500,4200,400,*,DOWN,PDIF +S 2500,700,2500,1800,100,*,UP,NTRANS +S 2000,700,2000,1800,100,*,UP,NTRANS +S 1500,700,1500,1800,100,*,UP,NTRANS +S 1800,400,3300,400,300,*,RIGHT,PTIE +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 0,1000,5500,1000,1800,*,RIGHT,PWELL +S 1500,1800,1500,2000,100,*,DOWN,POLY +S 2000,1800,2000,2000,100,*,UP,POLY +S 2500,1800,2500,2000,100,*,UP,POLY +S 2800,4700,4800,4700,300,*,RIGHT,NTIE +S 3700,1400,3900,1400,100,*,RIGHT,POLY +S 4300,1400,4300,1600,100,*,UP,POLY +S 4900,1400,4900,1600,100,*,UP,POLY +S 3200,2700,3200,2900,100,i6,UP,POLY +V 500,3500,CONT_DIF_P,* +V 1100,4000,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 3500,3000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 2300,4500,CONT_DIF_P,* +V 5200,4000,CONT_DIF_P,* +V 500,1500,CONT_DIF_N,* +V 4000,500,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 1200,500,CONT_DIF_N,* +V 5200,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 5100,400,CONT_BODY_P,* +V 4700,400,CONT_BODY_P,* +V 1000,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 2900,4000,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 2900,4700,CONT_BODY_N,* +V 3500,4700,CONT_BODY_N,* +V 4100,4700,CONT_BODY_N,* +V 4700,4700,CONT_BODY_N,* +V 2800,400,CONT_BODY_P,* +V 2300,400,CONT_BODY_P,* +V 1800,400,CONT_BODY_P,* +V 3350,400,CONT_BODY_P,* +V 5000,1500,CONT_POLY,* +V 5000,2500,CONT_POLY,* +V 4500,1500,CONT_POLY,* +V 4000,1500,CONT_POLY,* +V 2500,2900,CONT_POLY,* +V 3000,2800,CONT_POLY,* +V 1500,2900,CONT_POLY,* +V 2000,2900,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x2.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x2.vbe new file mode 100644 index 000000000..dc2a71887 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x2.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT tpll_i6_q : NATURAL := 540; + CONSTANT tphh_i3_q : NATURAL := 560; + CONSTANT tphh_i6_q : NATURAL := 563; + CONSTANT tphh_i0_q : NATURAL := 638; + CONSTANT tphh_i4_q : NATURAL := 649; + CONSTANT tpll_i2_q : NATURAL := 707; + CONSTANT tphh_i5_q : NATURAL := 734; + CONSTANT tpll_i5_q : NATURAL := 734; + CONSTANT tphh_i1_q : NATURAL := 735; + CONSTANT tpll_i4_q : NATURAL := 760; + CONSTANT tpll_i1_q : NATURAL := 764; + CONSTANT tpll_i3_q : NATURAL := 765; + CONSTANT tphh_i2_q : NATURAL := 806; + CONSTANT tpll_i0_q : NATURAL := 820; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x2; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1400 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x4.ap new file mode 100644 index 000000000..2c3fd0100 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x4.ap @@ -0,0 +1,172 @@ +V ALLIANCE : 6 +H oa3ao322_x4,P, 9/12/2016,100 +A 0,0,6000,5000 +R 3500,3500,ref_ref,i6_35 +R 2500,1500,ref_ref,i1_15 +R 2500,2000,ref_ref,i1_20 +R 2500,2500,ref_ref,i1_25 +R 2500,3000,ref_ref,i1_30 +R 2500,3500,ref_ref,i1_35 +R 1000,3500,ref_ref,q_35 +R 3000,2000,ref_ref,i2_20 +R 3000,2500,ref_ref,i2_25 +R 3000,3000,ref_ref,i2_30 +R 3000,3500,ref_ref,i2_35 +R 3500,2000,ref_ref,i6_20 +R 3500,2500,ref_ref,i6_25 +R 3500,3000,ref_ref,i6_30 +R 5000,1500,ref_ref,i4_15 +R 5000,3000,ref_ref,i4_30 +R 5000,3500,ref_ref,i4_35 +R 5500,1500,ref_ref,i5_15 +R 4500,1500,ref_ref,i3_15 +R 5500,3000,ref_ref,i5_30 +R 5500,3500,ref_ref,i5_35 +R 2000,1500,ref_ref,i0_15 +R 2000,2000,ref_ref,i0_20 +R 2000,2500,ref_ref,i0_25 +R 2000,3000,ref_ref,i0_30 +R 4500,3000,ref_ref,i3_30 +R 1000,3000,ref_ref,q_30 +R 1000,2500,ref_ref,q_25 +R 1000,2000,ref_ref,q_20 +R 1000,1500,ref_ref,q_15 +R 1000,1000,ref_ref,q_10 +R 1000,4000,ref_ref,q_40 +R 2000,3500,ref_ref,i0_35 +R 4500,3500,ref_ref,i3_35 +R 5500,2000,ref_ref,i5_25 +R 5000,2000,ref_ref,i4_25 +R 4500,2000,ref_ref,i3_25 +S 3500,2900,3700,2900,300,*,LEFT,POLY +S 4800,1500,5000,1500,300,*,RIGHT,POLY +S 1600,2800,1600,4700,200,*,DOWN,PDIF +S 4000,2800,4000,4200,300,*,DOWN,PDIF +S 700,2000,1500,2000,300,*,LEFT,POLY +S 3500,2000,3700,2000,300,*,RIGHT,POLY +S 2500,1500,2500,3500,200,i1,DOWN,CALU1 +S 3000,2000,3000,3500,200,i2,DOWN,CALU1 +S 3500,2000,3500,3500,200,i6,DOWN,CALU1 +S 5000,1500,5000,3500,200,i4,DOWN,CALU1 +S 5500,1500,5500,3500,200,i5,DOWN,CALU1 +S 1000,1000,1000,4000,200,q,DOWN,CALU1 +S 2000,1500,2000,3500,200,i0,DOWN,CALU1 +S 4500,1500,4500,3500,200,i3,DOWN,CALU1 +S 2000,1500,2000,3500,200,*,DOWN,ALU1 +S 2500,1500,2500,3500,200,*,DOWN,ALU1 +S 5000,1500,5000,3500,200,*,UP,ALU1 +S 3500,2000,3500,3500,200,*,UP,ALU1 +S 5700,300,5700,1000,200,*,DOWN,ALU1 +S 5500,1500,5500,3500,200,*,DOWN,ALU1 +S 2200,4000,5700,4000,200,*,RIGHT,ALU1 +S 1500,1000,1500,2000,200,*,UP,ALU1 +S 3900,1000,5100,1000,200,*,RIGHT,ALU1 +S 4500,1500,4500,3500,200,*,UP,ALU1 +S 4000,1500,4000,3500,200,*,DOWN,ALU1 +S 1500,1000,3300,1000,200,*,LEFT,ALU1 +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 1600,4000,1600,4700,200,*,UP,ALU1 +S 3300,1500,4000,1500,200,*,RIGHT,ALU1 +S 3300,1000,3300,1500,200,*,UP,ALU1 +S 3000,2000,3000,3500,200,*,UP,ALU1 +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 400,400,400,1500,200,*,DOWN,ALU1 +S 400,3000,400,4500,200,*,UP,ALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 1300,1900,1300,2600,100,*,DOWN,POLY +S 2500,1800,2500,2000,100,*,UP,POLY +S 3000,1800,3000,2000,100,*,UP,POLY +S 3600,1900,3700,1900,100,*,LEFT,POLY +S 1900,1900,2000,1900,100,*,RIGHT,POLY +S 2000,1800,2000,2000,100,*,DOWN,POLY +S 3600,1600,3600,1900,100,*,UP,POLY +S 700,1900,700,2600,100,*,DOWN,POLY +S 2300,400,3800,400,300,*,RIGHT,PTIE +S 5200,400,5600,400,300,*,RIGHT,PTIE +S 2500,700,2500,1800,100,*,UP,NTRANS +S 5100,900,5100,1200,300,*,UP,NDIF +S 4500,400,4500,1200,300,*,DOWN,NDIF +S 3600,700,3600,1600,100,*,UP,NTRANS +S 1700,500,1700,1700,300,*,UP,NDIF +S 3900,900,3900,1400,200,*,UP,NDIF +S 4200,700,4200,1400,100,*,UP,NTRANS +S 2000,700,2000,1800,100,*,UP,NTRANS +S 3000,700,3000,1800,100,*,UP,NTRANS +S 1000,800,1000,1700,300,*,UP,NDIF +S 1300,600,1300,1900,100,*,DOWN,NTRANS +S 4800,700,4800,1400,100,*,UP,NTRANS +S 3300,900,3300,1400,200,*,UP,NDIF +S 5400,700,5400,1400,100,*,UP,NTRANS +S 5700,900,5700,1200,300,*,UP,NDIF +S 400,800,400,1700,300,*,DOWN,NDIF +S 700,600,700,1900,100,*,DOWN,NTRANS +S 5700,2800,5700,4200,300,*,UP,PDIF +S 3100,3000,3100,4400,100,*,UP,PTRANS +S 3700,2900,3700,4400,100,*,UP,PTRANS +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 2200,3200,2200,4200,300,*,UP,PDIF +S 4400,2600,4400,4400,100,*,UP,PTRANS +S 2500,3000,2500,4400,100,*,UP,PTRANS +S 2800,3200,2800,4500,300,*,DOWN,PDIF +S 3400,3100,3400,4200,200,*,UP,PDIF +S 5400,2600,5400,4400,100,*,UP,PTRANS +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 1900,3000,1900,4400,100,*,UP,PTRANS +S 400,2800,400,4700,300,*,UP,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,1000,6000,1000,1800,*,RIGHT,PWELL +S 3300,4700,5300,4700,300,*,RIGHT,NTIE +S 3700,2800,3700,3000,100,i6,UP,POLY +S 4800,1400,4800,1600,100,*,UP,POLY +S 4200,1400,4400,1400,100,*,RIGHT,POLY +V 1500,2000,CONT_POLY,* +V 3500,2000,CONT_POLY,* +V 5000,2500,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 2300,400,CONT_BODY_P,* +V 3850,400,CONT_BODY_P,* +V 2800,400,CONT_BODY_P,* +V 3300,400,CONT_BODY_P,* +V 5600,400,CONT_BODY_P,* +V 5200,400,CONT_BODY_P,* +V 5700,1000,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 1700,500,CONT_DIF_N,* +V 1000,1500,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 400,1500,CONT_DIF_N,* +V 400,1000,CONT_DIF_N,* +V 3400,4000,CONT_DIF_P,* +V 4600,4700,CONT_BODY_N,* +V 1000,3500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 4000,4700,CONT_BODY_N,* +V 3400,4700,CONT_BODY_N,* +V 1600,4000,CONT_DIF_P,* +V 5200,4700,CONT_BODY_N,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 2800,4500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 2200,4000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 400,4000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +V 2000,2900,CONT_POLY,* +V 2500,2900,CONT_POLY,* +V 3000,2900,CONT_POLY,* +V 3500,2900,CONT_POLY,* +V 4500,1500,CONT_POLY,* +V 5000,1500,CONT_POLY,* +V 5500,1500,CONT_POLY,* +V 5500,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x4.vbe new file mode 100644 index 000000000..6f1ad9762 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/oa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT tpll_i6_q : NATURAL := 651; + CONSTANT tphh_i3_q : NATURAL := 673; + CONSTANT tphh_i6_q : NATURAL := 684; + CONSTANT tphh_i0_q : NATURAL := 717; + CONSTANT tphh_i4_q : NATURAL := 758; + CONSTANT tphh_i1_q : NATURAL := 818; + CONSTANT tpll_i2_q : NATURAL := 834; + CONSTANT tphh_i5_q : NATURAL := 839; + CONSTANT tpll_i5_q : NATURAL := 865; + CONSTANT tpll_i1_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 894; + CONSTANT tpll_i4_q : NATURAL := 896; + CONSTANT tpll_i3_q : NATURAL := 898; + CONSTANT tpll_i0_q : NATURAL := 946; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1500 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x1.ap new file mode 100644 index 000000000..3833eaa22 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x1.ap @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H on12_x1,P,22/ 7/2016,100 +A 0,0,2500,5000 +R 1000,3500,ref_ref,i1_25 +R 2000,4000,ref_ref,i0_40 +R 1500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,q_35 +R 1500,3000,ref_ref,q_30 +R 1500,2500,ref_ref,q_25 +R 1500,2000,ref_ref,q_20 +R 1500,1500,ref_ref,q_15 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 2000,1500,ref_ref,i0_15 +R 2000,2000,ref_ref,i0_20 +R 2000,2500,ref_ref,i0_25 +R 2000,3000,ref_ref,i0_30 +R 2000,3500,ref_ref,i0_35 +R 1000,4000,ref_ref,i1_40 +R 1000,3000,ref_ref,i1_30 +R 1000,1000,ref_ref,i1_10 +R 1500,1000,ref_ref,q_10 +S 300,200,300,700,300,*,UP,PTIE +S 1400,300,2300,300,300,*,RIGHT,PTIE +S 2000,1500,2000,4000,200,i0,DOWN,CALU1 +S 1000,1000,1000,4000,200,i1,DOWN,CALU1 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +S 2000,1500,2000,4000,200,*,DOWN,ALU1 +S 800,2000,1000,2000,200,*,RIGHT,ALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 800,3000,1000,3000,200,*,RIGHT,ALU1 +S 300,1500,300,4000,200,*,UP,ALU1 +S 1500,1000,1900,1000,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 1800,1900,1800,3100,100,*,DOWN,POLY +S 1800,2000,2100,2000,300,*,RIGHT,POLY +S 1600,1900,2100,1900,100,*,RIGHT,POLY +S 1200,1900,1200,3100,100,*,UP,POLY +S 600,3000,800,3000,300,*,LEFT,POLY +S 600,2000,800,2000,300,*,LEFT,POLY +S 300,2500,1200,2500,100,*,RIGHT,POLY +S 600,1100,600,1900,100,*,DOWN,NTRANS +S 300,1300,300,1700,300,*,DOWN,NDIF +S 1900,800,1900,1700,300,*,UP,NDIF +S 1600,600,1600,1900,100,*,DOWN,NTRANS +S 1200,600,1200,1900,100,*,DOWN,NTRANS +S 900,400,900,1700,300,*,UP,NDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 900,3300,900,4600,300,*,DOWN,PDIF +S 0,1000,2500,1000,1800,*,RIGHT,PWELL +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 1500,1000,1500,4000,200,*,UP,ALU1 +V 2200,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 2000,2000,CONT_POLY,* +V 800,3000,CONT_POLY,* +V 800,2000,CONT_POLY,* +V 300,2500,CONT_POLY,* +V 300,300,CONT_BODY_P,* +V 300,1500,CONT_DIF_N,* +V 1900,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 2100,4500,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x1.vbe new file mode 100644 index 000000000..32688f423 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3720; + CONSTANT rup_i1_q : NATURAL := 3720; + CONSTANT tphl_i0_q : NATURAL := 111; + CONSTANT tplh_i0_q : NATURAL := 234; + CONSTANT tpll_i1_q : NATURAL := 291; + CONSTANT tphh_i1_q : NATURAL := 314; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x1; + +ARCHITECTURE behaviour_data_flow OF on12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x1" + SEVERITY WARNING; + q <= (not (i0) or i1) after 900 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x4.ap new file mode 100644 index 000000000..2e78a8491 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x4.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 6 +H on12_x4,P, 9/12/2016,100 +A 0,0,4000,5000 +R 2500,2000,ref_ref,i1_20 +R 3000,1500,ref_ref,q_15 +R 3000,2000,ref_ref,q_20 +R 3000,2500,ref_ref,q_25 +R 3000,3000,ref_ref,q_30 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 2500,3500,ref_ref,i1_35 +R 2500,4000,ref_ref,i1_40 +R 2500,1500,ref_ref,i1_15 +R 2500,1000,ref_ref,i1_10 +R 3000,1000,ref_ref,q_10 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,4000,ref_ref,i0_40 +R 1000,1000,ref_ref,i0_10 +R 2500,3000,ref_ref,i1_25 +S 600,3500,800,3500,300,*,RIGHT,POLY +S 600,1500,800,1500,300,*,RIGHT,POLY +S 3000,1100,3000,4000,200,q,DOWN,CALU1 +S 3000,1000,3000,4000,200,*,UP,ALU1 +S 1500,2900,1500,4000,200,*,DOWN,ALU1 +S 1900,1000,1900,2900,200,*,DOWN,ALU1 +S 1500,2900,1900,2900,200,*,RIGHT,ALU1 +S 3700,3000,3700,4500,200,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 2500,1000,2500,4000,200,*,UP,ALU1 +S 3700,500,3700,1000,200,*,DOWN,ALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 2200,2500,2500,2500,300,*,RIGHT,POLY +S 1600,1400,1600,2600,100,*,DOWN,POLY +S 1600,2600,1800,2600,100,*,RIGHT,POLY +S 2800,1400,2800,2600,100,*,DOWN,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2000,2000,3400,2000,100,*,RIGHT,POLY +S 2200,1500,2500,1500,300,*,RIGHT,POLY +S 2200,600,2200,1400,100,*,DOWN,NTRANS +S 1900,800,1900,1200,300,*,UP,NDIF +S 1600,600,1600,1400,100,*,DOWN,NTRANS +S 3400,100,3400,1400,100,*,UP,NTRANS +S 3700,300,3700,1200,300,*,UP,NDIF +S 3100,300,3100,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 2200,2600,2200,4400,100,*,UP,PTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,UP,PDIF +S 2500,2800,2500,4700,300,*,UP,PDIF +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 0,1000,4000,1000,1800,*,RIGHT,PWELL +S 1500,2800,1500,4200,300,*,DOWN,PDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1100,400,1100,1200,700,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,1400,600,1600,100,*,UP,POLY +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 300,2000,1600,2000,100,*,RIGHT,POLY +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 800,3500,1000,3500,200,*,RIGHT,ALU1 +S 600,3400,600,3600,100,*,DOWN,POLY +S 900,3800,900,4700,300,*,UP,PDIF +S 600,3600,600,4900,100,*,UP,PTRANS +S 300,3800,300,4700,300,*,UP,PDIF +S 300,1000,300,4000,200,*,DOWN,ALU1 +S 2500,1000,2500,4000,200,i1,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 1400,4700,2000,4700,300,*,RIGHT,NTIE +V 2400,1500,CONT_POLY,* +V 2400,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2500,500,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 3700,500,CONT_DIF_N,* +V 3100,1000,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 1900,1000,CONT_DIF_N,* +V 1300,500,CONT_DIF_N,* +V 3100,3500,CONT_DIF_P,* +V 3100,4000,CONT_DIF_P,* +V 3700,4500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 2500,4500,CONT_DIF_P,* +V 3100,3000,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 1500,4000,CONT_DIF_P,* +V 800,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 800,3500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 1900,4700,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x4.vbe new file mode 100644 index 000000000..c5f990c6c --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/on12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 394; + CONSTANT tphl_i0_q : NATURAL := 474; + CONSTANT tphh_i1_q : NATURAL := 491; + CONSTANT tplh_i0_q : NATURAL := 499; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x4; + +ARCHITECTURE behaviour_data_flow OF on12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x4" + SEVERITY WARNING; + q <= (not (i0) or i1) after 1100 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/one_x0.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/one_x0.ap new file mode 100644 index 000000000..4acfe7ec5 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/one_x0.ap @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H one_x0,P,18/ 5/2002,100 +A 0,0,1500,5000 +R 1000,4000,ref_ref,q_40 +R 1000,3500,ref_ref,q_35 +R 1000,3000,ref_ref,q_30 +R 1000,2500,ref_ref,q_25 +R 1000,2000,ref_ref,q_20 +R 1000,1500,ref_ref,q_15 +R 1000,1000,ref_ref,q_10 +S 1000,1000,1000,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 1000,2800,1000,3700,300,*,DOWN,PDIF +S 700,2600,700,3900,100,*,UP,PTRANS +S 0,300,1500,300,600,vss,RIGHT,CALU1 +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 0,1000,1500,1000,1800,*,RIGHT,PWELL +S 350,2800,350,3700,400,*,DOWN,PDIF +S 400,3000,400,4700,200,*,UP,ALU1 +S 700,2400,700,2600,100,*,DOWN,POLY +S 500,300,500,2500,200,*,DOWN,ALU1 +S 400,4500,1000,4500,300,*,RIGHT,NTIE +S 500,500,500,1500,300,*,DOWN,PTIE +S 500,500,1000,500,300,*,RIGHT,PTIE +S 500,2500,700,2500,300,*,RIGHT,POLY +V 1000,3000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +V 500,2500,CONT_POLY,* +V 500,500,CONT_BODY_P,* +V 500,1000,CONT_BODY_P,* +V 500,1500,CONT_BODY_P,* +V 1000,500,CONT_BODY_P,* +V 1000,4500,CONT_BODY_N,* +V 400,4500,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/one_x0.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/one_x0.vbe new file mode 100644 index 000000000..e7439c597 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/one_x0.vbe @@ -0,0 +1,20 @@ +ENTITY one_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END one_x0; + +ARCHITECTURE behaviour_data_flow OF one_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on one_x0" + SEVERITY WARNING; + q <= '1'; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/powmid_x0.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/powmid_x0.ap new file mode 100644 index 000000000..171530bb0 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/powmid_x0.ap @@ -0,0 +1,10 @@ +V ALLIANCE : 6 +H powmid_x0,P, 6/ 6/2003,100 +A 0,0,3500,5000 +S 2000,0,3000,0,200,*,RIGHT,TALU2 +S 500,5000,1500,5000,200,*,RIGHT,TALU2 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 1000,0,1000,5000,1200,vdd,DOWN,CALU3 +S 2500,0,2500,5000,1200,vss,DOWN,CALU3 +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/powmid_x0.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/powmid_x0.vbe new file mode 100644 index 000000000..52f4c8149 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/powmid_x0.vbe @@ -0,0 +1,18 @@ +ENTITY powmid_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END powmid_x0; + +ARCHITECTURE behaviour_data_flow OF powmid_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on powmid_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/rowend_x0.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/rowend_x0.ap new file mode 100644 index 000000000..99460c972 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/rowend_x0.ap @@ -0,0 +1,10 @@ +V ALLIANCE : 6 +H rowend_x0,P,24/ 7/2002,100 +A 0,0,500,5000 +S 0,3900,500,3900,2400,*,RIGHT,NWELL +S 0,1000,500,1000,1800,*,RIGHT,PWELL +S 0,300,500,300,600,vss,RIGHT,CALU1 +S 0,300,500,300,600,vss,RIGHT,ALU1 +S 0,4700,500,4700,600,vdd,RIGHT,CALU1 +S 0,4700,500,4700,600,vdd,RIGHT,ALU1 +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/rowend_x0.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/rowend_x0.vbe new file mode 100644 index 000000000..dfe3de719 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/rowend_x0.vbe @@ -0,0 +1,18 @@ +ENTITY rowend_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 250; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END rowend_x0; + +ARCHITECTURE behaviour_data_flow OF rowend_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rowend_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/sff1_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/sff1_x4.ap new file mode 100644 index 000000000..4294ce99e --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/sff1_x4.ap @@ -0,0 +1,219 @@ +V ALLIANCE : 6 +H sff1_x4,P, 9/12/2016,100 +A 0,0,9000,5000 +R 8000,2000,ref_ref,q_20 +R 1000,4000,ref_ref,ck_40 +R 1000,3500,ref_ref,ck_35 +R 1000,3000,ref_ref,ck_30 +R 1000,2500,ref_ref,ck_25 +R 1000,2000,ref_ref,ck_20 +R 1000,1500,ref_ref,ck_15 +R 1000,1000,ref_ref,ck_10 +R 3000,4000,ref_ref,i_40 +R 2500,3000,ref_ref,i_30 +R 2500,2500,ref_ref,i_25 +R 2500,2000,ref_ref,i_20 +R 3000,1000,ref_ref,i_10 +R 8000,4000,ref_ref,q_40 +R 8000,3500,ref_ref,q_35 +R 8000,3000,ref_ref,q_30 +R 8000,2500,ref_ref,q_25 +R 8000,1500,ref_ref,q_15 +R 8000,1000,ref_ref,q_10 +S 300,2500,300,2700,300,*,DOWN,POLY +S 3500,2500,3500,2700,300,*,DOWN,POLY +S 200,2700,6600,2700,100,nckr,RIGHT,POLY +S 6600,1400,6600,2700,100,*,DOWN,POLY +S 4200,2700,4200,3100,100,*,DOWN,POLY +S 6000,2700,6000,3600,100,*,DOWN,POLY +S 7400,2500,8000,2500,200,*,RIGHT,ALU1 +S 7400,1500,8000,1500,200,*,RIGHT,ALU1 +S 2000,800,2000,1200,300,*,DOWN,NDIF +S 2000,3800,2000,4700,300,*,UP,PDIF +S 7300,2000,8400,2000,300,sff_s,RIGHT,POLY +S 6900,2000,7400,2000,200,*,RIGHT,ALU1 +S 7200,2400,7200,3600,100,*,UP,POLY +S 2000,1000,2000,4000,200,*,DOWN,ALU1 +S 2500,4000,3000,4000,200,*,RIGHT,ALU1 +S 2500,1000,3000,1000,200,*,RIGHT,ALU1 +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +S 6300,300,6900,300,300,*,RIGHT,PTIE +S 3300,300,3900,300,300,*,RIGHT,PTIE +S 1500,300,2100,300,300,*,RIGHT,PTIE +S 300,3500,300,4000,200,*,DOWN,ALU1 +S 1500,1000,1500,3500,200,*,DOWN,ALU1 +S 5000,3500,5700,3500,200,*,LEFT,ALU1 +S 5700,1000,5700,4000,200,y,DOWN,ALU1 +S 7500,500,7500,1000,200,*,DOWN,ALU1 +S 8700,500,8700,1000,200,*,DOWN,ALU1 +S 7500,3000,7500,4500,200,*,DOWN,ALU1 +S 8700,3000,8700,4500,200,*,DOWN,ALU1 +S 4500,1500,5200,1500,200,*,LEFT,ALU1 +S 3900,1000,4500,1000,200,*,RIGHT,ALU1 +S 5000,1000,5700,1000,200,*,RIGHT,ALU1 +S 6300,2000,6300,3500,200,*,DOWN,ALU1 +S 4500,3000,5200,3000,200,*,RIGHT,ALU1 +S 0,4700,9000,4700,600,vdd,RIGHT,CALU1 +S 0,300,9000,300,600,vss,RIGHT,CALU1 +S 7800,1400,7800,2600,100,*,DOWN,POLY +S 7200,1500,7500,1500,300,*,RIGHT,POLY +S 7200,2500,7500,2500,300,*,RIGHT,POLY +S 8400,1400,8400,2600,100,*,DOWN,POLY +S 6000,1400,6000,2000,100,*,DOWN,POLY +S 5400,900,5400,1500,100,*,UP,POLY +S 5400,3000,5400,3600,100,*,DOWN,POLY +S 4200,1400,4200,2000,100,*,DOWN,POLY +S 5600,3800,5600,4700,300,*,DOWN,PDIF +S 5000,3800,5000,4700,300,*,DOWN,PDIF +S 5400,3600,5400,4900,100,*,UP,PTRANS +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 8400,2600,8400,4900,100,*,DOWN,PTRANS +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 7800,2600,7800,4900,100,*,DOWN,PTRANS +S 7500,2800,7500,4700,300,*,DOWN,PDIF +S 3000,3600,3000,4900,100,*,DOWN,PTRANS +S 6900,3800,6900,4700,300,*,UP,PDIF +S 2400,3600,2400,4900,100,*,DOWN,PTRANS +S 2700,3800,2700,4700,300,*,UP,PDIF +S 5400,100,5400,900,100,*,UP,NTRANS +S 5700,300,5700,700,300,*,DOWN,NDIF +S 5100,300,5100,700,300,*,DOWN,NDIF +S 5700,300,5700,1200,300,*,DOWN,NDIF +S 7500,300,7500,1200,300,*,DOWN,NDIF +S 8100,300,8100,1200,300,*,DOWN,NDIF +S 8400,100,8400,1400,100,*,UP,NTRANS +S 8700,300,8700,1200,300,*,DOWN,NDIF +S 6900,800,6900,1200,300,*,DOWN,NDIF +S 7800,100,7800,1400,100,*,UP,NTRANS +S 3900,800,3900,1200,300,*,DOWN,NDIF +S 4500,300,4500,1200,300,*,DOWN,NDIF +S 2400,600,2400,1400,100,*,UP,NTRANS +S 3000,600,3000,1400,100,*,UP,NTRANS +S 2700,400,2700,1200,300,*,DOWN,NDIF +S 0,1000,9000,1000,1800,*,RIGHT,PWELL +S 0,3900,9000,3900,2400,*,RIGHT,NWELL +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 900,3300,900,4600,300,*,UP,PDIF +S 3500,1500,3500,2500,200,*,DOWN,ALU1 +S 600,3000,900,3000,300,*,RIGHT,POLY +S 6000,2000,6300,2000,300,*,RIGHT,POLY +S 3900,2000,4200,2000,300,*,RIGHT,POLY +S 5100,3000,5400,3000,300,*,RIGHT,POLY +S 6300,3500,6600,3500,300,*,RIGHT,POLY +S 4800,3500,5100,3500,300,*,RIGHT,POLY +S 5100,1500,5400,1500,300,*,RIGHT,POLY +S 4800,1000,5100,1000,300,*,RIGHT,POLY +S 2000,3000,3000,3000,100,*,RIGHT,POLY +S 300,800,300,1200,300,*,DOWN,NDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,UP,NTRANS +S 300,1000,300,3500,200,*,DOWN,ALU1 +S 900,400,900,1200,300,*,DOWN,NDIF +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 600,1500,900,1500,300,*,RIGHT,POLY +S 1500,3300,1500,4200,300,*,UP,PDIF +S 1600,2000,6000,2000,100,ckr,RIGHT,POLY +S 3500,3000,4000,3000,200,*,RIGHT,ALU1 +S 3900,3300,3900,4200,300,*,UP,PDIF +S 4000,2000,4000,3000,200,*,UP,ALU1 +S 4500,3300,4500,4700,300,*,UP,PDIF +S 3000,3100,3000,3600,100,*,UP,POLY +S 3000,1500,3000,3000,200,u,DOWN,ALU1 +S 3900,3500,4500,3500,200,*,RIGHT,ALU1 +S 6900,1000,6900,4000,200,*,DOWN,ALU1 +S 4500,1000,4500,3500,200,sff_m,DOWN,ALU1 +S 3300,3300,3300,4700,300,*,UP,PDIF +S 3300,800,3300,1200,300,*,DOWN,NDIF +S 3600,600,3600,1400,100,*,UP,NTRANS +S 3600,3100,3600,4400,100,*,DOWN,PTRANS +S 4800,3600,4800,4900,100,*,DOWN,PTRANS +S 4200,3100,4200,4400,100,*,DOWN,PTRANS +S 4200,600,4200,1400,100,*,UP,NTRANS +S 4800,100,4800,900,100,*,UP,NTRANS +S 6000,600,6000,1400,100,*,UP,NTRANS +S 6000,3600,6000,4900,100,*,DOWN,PTRANS +S 6600,3600,6600,4900,100,*,DOWN,PTRANS +S 7200,3600,7200,4900,100,*,DOWN,PTRANS +S 7200,600,7200,1400,100,*,UP,NTRANS +S 6600,600,6600,1400,100,*,UP,NTRANS +S 6300,3800,6300,4700,300,*,DOWN,PDIF +S 6300,800,6300,1200,300,*,DOWN,NDIF +S 6300,1000,6900,1000,200,*,RIGHT,ALU1 +S 6300,4000,6900,4000,200,*,RIGHT,ALU1 +S 8000,1000,8000,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,ck,DOWN,CALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 800,3000,1000,3000,200,*,RIGHT,ALU1 +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 8000,1000,8000,4000,200,*,DOWN,ALU1 +S 2500,1000,2500,4000,200,i,DOWN,CALU1 +V 3900,4600,CONT_BODY_N,* +V 2000,1000,CONT_DIF_N,* +V 2000,4000,CONT_DIF_P,* +V 7400,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 5000,3500,CONT_POLY,* +V 7400,2500,CONT_POLY,* +V 7400,1500,CONT_POLY,* +V 5200,1500,CONT_POLY,* +V 6200,2000,CONT_POLY,* +V 5200,3000,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 5000,1000,CONT_POLY,* +V 6400,3500,CONT_POLY,* +V 6300,4000,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 8700,3000,CONT_DIF_P,* +V 8100,3000,CONT_DIF_P,* +V 7500,3000,CONT_DIF_P,* +V 7500,3500,CONT_DIF_P,* +V 7500,4000,CONT_DIF_P,* +V 8700,4500,CONT_DIF_P,* +V 7500,4500,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 8700,3500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 6300,1000,CONT_DIF_N,* +V 5100,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 5700,1000,CONT_DIF_N,* +V 8700,500,CONT_DIF_N,* +V 7500,500,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 7500,1000,CONT_DIF_N,* +V 8100,1000,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,3500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 800,3000,CONT_POLY,* +V 300,2500,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 1500,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +V 3300,300,CONT_BODY_P,* +V 3900,300,CONT_BODY_P,* +V 2500,3500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 800,1500,CONT_POLY,* +V 8100,4000,CONT_DIF_P,* +V 8100,3500,CONT_DIF_P,* +V 6300,300,CONT_BODY_P,* +V 6900,300,CONT_BODY_P,* +V 3500,3000,CONT_POLY,* +V 3900,3500,CONT_DIF_P,* +V 1500,2000,CONT_POLY,* +V 1500,4600,CONT_BODY_N,* +V 300,4600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/sff1_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/sff1_x4.vbe new file mode 100644 index 000000000..4756bfddd --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/sff1_x4.vbe @@ -0,0 +1,39 @@ +ENTITY sff1_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tsr_i_ck : NATURAL := 476; + CONSTANT transistors : NATURAL := 26 +); +PORT ( + ck : in BIT; + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff1_x4; + +ARCHITECTURE VBE OF sff1_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff1_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED i; + END BLOCK label0; + + q <= sff_m after 1700 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/sff2_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/sff2_x4.ap new file mode 100644 index 000000000..3ed304faf --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/sff2_x4.ap @@ -0,0 +1,258 @@ +V ALLIANCE : 6 +H sff2_x4,P,22/ 7/2016,100 +A 0,0,12000,5000 +R 4500,3500,ref_ref,ck_25 +R 1000,2000,ref_ref,i0_25 +R 4500,1000,ref_ref,ck_10 +R 4500,3000,ref_ref,ck_30 +R 4500,2000,ref_ref,ck_20 +R 4500,1500,ref_ref,ck_15 +R 1000,1500,ref_ref,i0_15 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,4000,ref_ref,i0_40 +R 3000,1000,ref_ref,i1_10 +R 3000,1500,ref_ref,i1_15 +R 3000,2000,ref_ref,i1_20 +R 3000,2500,ref_ref,i1_25 +R 3000,3000,ref_ref,i1_30 +R 3000,3500,ref_ref,i1_35 +R 1500,2500,ref_ref,cmd_25 +R 1500,3000,ref_ref,cmd_30 +R 1500,3500,ref_ref,cmd_35 +R 1500,4000,ref_ref,cmd_40 +R 11000,1000,ref_ref,q_10 +R 11000,1500,ref_ref,q_15 +R 11000,2500,ref_ref,q_25 +R 11000,3000,ref_ref,q_30 +R 11000,3500,ref_ref,q_35 +R 11000,4000,ref_ref,q_40 +R 11000,2000,ref_ref,q_20 +S 11100,1000,11100,4000,200,q,DOWN,CALU1 +S 11100,1000,11100,4000,200,*,DOWN,ALU1 +S 2500,1400,2500,2700,100,*,DOWN,POLY +S 1600,2700,1600,3100,100,*,DOWN,POLY +S 600,2700,2500,2700,100,*,RIGHT,POLY +S 10200,600,10200,1400,100,*,UP,NTRANS +S 9600,600,9600,1400,100,*,UP,NTRANS +S 10200,3600,10200,4900,100,*,DOWN,PTRANS +S 9600,3600,9600,4900,100,*,DOWN,PTRANS +S 9000,3600,9000,4900,100,*,DOWN,PTRANS +S 9000,600,9000,1400,100,*,UP,NTRANS +S 7800,100,7800,900,100,*,UP,NTRANS +S 7200,600,7200,1400,100,*,UP,NTRANS +S 7800,3600,7800,4900,100,*,DOWN,PTRANS +S 7200,3100,7200,4400,100,*,DOWN,PTRANS +S 6600,3100,6600,4400,100,*,DOWN,PTRANS +S 6600,600,6600,1400,100,*,UP,NTRANS +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 9300,300,9900,300,300,*,RIGHT,PTIE +S 6300,300,6900,300,300,*,RIGHT,PTIE +S 1500,300,2500,300,300,*,RIGHT,PTIE +S 0,1000,12000,1000,1800,*,RIGHT,PWELL +S 0,3900,12000,3900,2400,*,RIGHT,NWELL +S 900,400,900,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1200,600,1200,1400,100,*,UP,NTRANS +S 2500,600,2500,1400,100,*,UP,NTRANS +S 1900,800,1900,1200,300,*,UP,NDIF +S 1600,600,1600,1400,100,*,UP,NTRANS +S 3200,400,3200,1200,300,*,UP,NDIF +S 2900,600,2900,1400,100,*,UP,NTRANS +S 2100,800,2100,1600,500,*,DOWN,NDIF +S 4800,600,4800,1400,100,*,UP,NTRANS +S 4500,400,4500,1200,300,*,DOWN,NDIF +S 3900,800,3900,1200,300,*,DOWN,NDIF +S 4200,600,4200,1400,100,*,UP,NTRANS +S 5100,800,5100,1200,300,*,DOWN,NDIF +S 8100,300,8100,700,300,*,DOWN,NDIF +S 8700,300,8700,700,300,*,DOWN,NDIF +S 8400,100,8400,900,100,*,UP,NTRANS +S 11700,300,11700,1200,300,*,DOWN,NDIF +S 11400,100,11400,1400,100,*,UP,NTRANS +S 11100,300,11100,1200,300,*,DOWN,NDIF +S 10500,300,10500,1200,300,*,DOWN,NDIF +S 8700,300,8700,1200,300,*,DOWN,NDIF +S 9300,800,9300,1200,300,*,DOWN,NDIF +S 10800,100,10800,1400,100,*,UP,NTRANS +S 9900,800,9900,1200,300,*,DOWN,NDIF +S 5700,400,5700,1200,300,*,DOWN,NDIF +S 6000,600,6000,1400,100,*,UP,NTRANS +S 6300,800,6300,1200,300,*,DOWN,NDIF +S 7500,300,7500,1200,300,*,DOWN,NDIF +S 6900,800,6900,1200,300,*,DOWN,NDIF +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 2900,3100,2900,4400,100,*,DOWN,PTRANS +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 3200,3300,3200,4600,300,*,DOWN,PDIF +S 2500,3100,2500,4400,100,*,DOWN,PTRANS +S 5100,3300,5100,4200,300,*,UP,PDIF +S 4800,3100,4800,4400,100,*,DOWN,PTRANS +S 4200,3100,4200,4400,100,*,DOWN,PTRANS +S 3900,3300,3900,4200,300,*,UP,PDIF +S 8000,3800,8000,4700,300,*,DOWN,PDIF +S 9300,3800,9300,4700,300,*,DOWN,PDIF +S 8600,3800,8600,4700,300,*,DOWN,PDIF +S 4500,3300,4500,4600,300,*,UP,PDIF +S 11700,2800,11700,4700,300,*,DOWN,PDIF +S 11400,2600,11400,4900,100,*,DOWN,PTRANS +S 11100,2800,11100,4700,300,*,DOWN,PDIF +S 8400,3600,8400,4900,100,*,UP,PTRANS +S 9900,3800,9900,4700,300,*,UP,PDIF +S 6000,3600,6000,4900,100,*,DOWN,PTRANS +S 10500,2800,10500,4700,300,*,DOWN,PDIF +S 10800,2600,10800,4900,100,*,DOWN,PTRANS +S 7500,3300,7500,4700,300,*,UP,PDIF +S 6900,3300,6900,4200,300,*,UP,PDIF +S 6300,3300,6300,4700,300,*,UP,PDIF +S 5700,3800,5700,4700,300,*,UP,PDIF +S 7800,1000,8100,1000,300,*,RIGHT,POLY +S 8400,900,8400,1500,100,*,UP,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 900,1500,1200,1500,300,*,RIGHT,POLY +S 900,3000,1200,3000,300,*,RIGHT,POLY +S 1600,1400,1600,2000,100,*,DOWN,POLY +S 4200,3000,4500,3000,300,*,RIGHT,POLY +S 5100,2000,9000,2000,100,ckr,RIGHT,POLY +S 3900,2500,9600,2500,100,nckr,RIGHT,POLY +S 10200,2500,10500,2500,300,*,RIGHT,POLY +S 10200,1500,10500,1500,300,*,RIGHT,POLY +S 10800,1400,10800,2600,100,*,DOWN,POLY +S 9600,1400,9600,2500,100,*,DOWN,POLY +S 4800,1400,4800,3100,100,*,DOWN,POLY +S 4200,1500,4500,1500,300,*,RIGHT,POLY +S 6900,2000,7200,2000,300,*,RIGHT,POLY +S 9000,2000,9300,2000,300,*,RIGHT,POLY +S 7200,1400,7200,2000,100,*,DOWN,POLY +S 9000,2500,9000,3600,100,*,DOWN,POLY +S 8400,3000,8400,3600,100,*,DOWN,POLY +S 9000,1400,9000,2000,100,*,DOWN,POLY +S 11400,1400,11400,2600,100,*,DOWN,POLY +S 7200,2500,7200,3100,100,*,DOWN,POLY +S 8100,1500,8400,1500,300,*,RIGHT,POLY +S 7800,3500,8100,3500,300,*,RIGHT,POLY +S 9300,3500,9600,3500,300,*,RIGHT,POLY +S 8100,3000,8400,3000,300,*,RIGHT,POLY +S 0,300,12000,300,600,vss,RIGHT,CALU1 +S 300,1000,2500,1000,200,*,RIGHT,ALU1 +S 300,1000,300,3500,200,*,DOWN,ALU1 +S 4500,1000,4500,3500,200,*,DOWN,ALU1 +S 5100,1000,5100,3500,200,*,DOWN,ALU1 +S 2500,1000,2500,3000,200,*,DOWN,ALU1 +S 1500,1000,1500,2000,200,*,UP,ALU1 +S 8700,1000,8700,4000,200,y,DOWN,ALU1 +S 3000,1000,3000,3500,200,*,DOWN,ALU1 +S 3900,1000,3900,3500,200,*,DOWN,ALU1 +S 8000,1000,8700,1000,200,*,RIGHT,ALU1 +S 6900,1000,7500,1000,200,*,RIGHT,ALU1 +S 9300,1000,9900,1000,200,*,RIGHT,ALU1 +S 11700,500,11700,1000,200,*,DOWN,ALU1 +S 10500,500,10500,1000,200,*,DOWN,ALU1 +S 0,4700,12000,4700,600,vdd,RIGHT,CALU1 +S 1000,1500,1000,4000,200,*,DOWN,ALU1 +S 2000,4000,6000,4000,200,*,RIGHT,ALU1 +S 1500,2500,1500,4000,200,*,DOWN,ALU1 +S 2000,1500,2000,4000,200,*,DOWN,ALU1 +S 8000,3500,8700,3500,200,*,LEFT,ALU1 +S 11700,3000,11700,4500,200,*,DOWN,ALU1 +S 10500,3000,10500,4500,200,*,DOWN,ALU1 +S 10400,2500,11100,2500,200,*,RIGHT,ALU1 +S 10400,1500,11100,1500,200,*,RIGHT,ALU1 +S 7500,3000,8200,3000,200,*,RIGHT,ALU1 +S 9300,2000,9300,3500,200,*,DOWN,ALU1 +S 7500,1500,8200,1500,200,*,LEFT,ALU1 +S 9300,4000,9900,4000,200,*,RIGHT,ALU1 +S 6900,3500,7500,3500,200,*,RIGHT,ALU1 +S 6000,1500,6000,4000,200,u,DOWN,ALU1 +S 7000,2000,7000,3000,200,*,UP,ALU1 +S 6500,3000,7000,3000,200,*,RIGHT,ALU1 +S 6500,1500,6500,2500,200,*,DOWN,ALU1 +S 7500,1000,7500,3500,200,sff_m,DOWN,ALU1 +S 9900,1000,9900,4000,200,sff_s,DOWN,ALU1 +S 10200,2400,10200,3600,100,*,DOWN,POLY +S 9900,2000,10400,2000,200,*,RIGHT,ALU1 +S 10400,2000,11400,2000,300,*,RIGHT,POLY +S 4500,1000,4500,3500,200,ck,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 3000,1000,3000,3500,200,i1,DOWN,CALU1 +S 1500,2500,1500,4000,200,cmd,DOWN,CALU1 +V 1500,3000,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 3200,500,CONT_DIF_N,* +V 9300,1000,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 11100,1000,CONT_DIF_N,* +V 10500,1000,CONT_DIF_N,* +V 11700,1000,CONT_DIF_N,* +V 10500,500,CONT_DIF_N,* +V 11700,500,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 6900,1000,CONT_DIF_N,* +V 8100,500,CONT_DIF_N,* +V 5700,500,CONT_DIF_N,* +V 2000,1500,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 3200,4500,CONT_DIF_P,* +V 10500,3000,CONT_DIF_P,* +V 11100,3000,CONT_DIF_P,* +V 11700,3000,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 8100,4500,CONT_DIF_P,* +V 9300,4000,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 2000,3500,CONT_DIF_P,* +V 11100,4000,CONT_DIF_P,* +V 5700,4500,CONT_DIF_P,* +V 11700,3500,CONT_DIF_P,* +V 11700,4000,CONT_DIF_P,* +V 10500,4500,CONT_DIF_P,* +V 11700,4500,CONT_DIF_P,* +V 10500,4000,CONT_DIF_P,* +V 10500,3500,CONT_DIF_P,* +V 6900,3500,CONT_DIF_P,* +V 11100,3500,CONT_DIF_P,* +V 2500,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 9900,300,CONT_BODY_P,* +V 9300,300,CONT_BODY_P,* +V 6900,300,CONT_BODY_P,* +V 6300,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 2500,300,CONT_BODY_P,* +V 8000,1000,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 2500,3000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 8000,3500,CONT_POLY,* +V 4400,1500,CONT_POLY,* +V 4400,3000,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 5200,2000,CONT_POLY,* +V 5900,3500,CONT_POLY,* +V 9400,3500,CONT_POLY,* +V 7000,2000,CONT_POLY,* +V 8200,3000,CONT_POLY,* +V 9200,2000,CONT_POLY,* +V 8200,1500,CONT_POLY,* +V 10400,1500,CONT_POLY,* +V 10400,2500,CONT_POLY,* +V 6500,3000,CONT_POLY,* +V 6500,1500,CONT_POLY,* +V 6500,2500,CONT_POLY,* +V 6000,1500,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 10400,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/sff2_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/sff2_x4.vbe new file mode 100644 index 000000000..59eaa6446 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/sff2_x4.vbe @@ -0,0 +1,51 @@ +ENTITY sff2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd : NATURAL := 16; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 7; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_cmd_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thr_cmd_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT tsf_cmd_ck : NATURAL := 833; + CONSTANT tsf_i0_ck : NATURAL := 764; + CONSTANT tsf_i1_ck : NATURAL := 764; + CONSTANT tsr_cmd_ck : NATURAL := 770; + CONSTANT tsr_i0_ck : NATURAL := 666; + CONSTANT tsr_i1_ck : NATURAL := 666; + CONSTANT transistors : NATURAL := 34 +); +PORT ( + ck : in BIT; + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff2_x4; + +ARCHITECTURE VBE OF sff2_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff2_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd))); + END BLOCK label0; + + q <= sff_m after 2000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/tie_x0.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/tie_x0.ap new file mode 100644 index 000000000..6c769d12c --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/tie_x0.ap @@ -0,0 +1,19 @@ +V ALLIANCE : 6 +H tie_x0,P,24/ 7/2002,100 +A 0,0,1000,5000 +S 500,500,500,1500,200,*,UP,ALU1 +S 500,3000,500,4500,200,*,DOWN,ALU1 +S 500,3000,500,4500,300,*,UP,NTIE +S 500,500,500,1500,300,*,DOWN,PTIE +S 0,4700,1000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,1000,3900,2400,*,RIGHT,NWELL +S 0,1000,1000,1000,1800,*,RIGHT,PWELL +S 0,300,1000,300,600,vss,RIGHT,CALU1 +V 500,1500,CONT_BODY_P,* +V 500,1000,CONT_BODY_P,* +V 500,500,CONT_BODY_P,* +V 500,3000,CONT_BODY_N,* +V 500,3500,CONT_BODY_N,* +V 500,4000,CONT_BODY_N,* +V 500,4500,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/tie_x0.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/tie_x0.vbe new file mode 100644 index 000000000..938a45c77 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/tie_x0.vbe @@ -0,0 +1,18 @@ +ENTITY tie_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 500; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END tie_x0; + +ARCHITECTURE behaviour_data_flow OF tie_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on tie_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x4.ap new file mode 100644 index 000000000..ff6e663ba --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x4.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H ts_x4,P,15/ 6/2016,100 +A 0,0,5000,5000 +R 1000,1000,ref_ref,q_10 +R 1000,1500,ref_ref,q_15 +R 1000,2000,ref_ref,q_20 +R 1000,2500,ref_ref,q_25 +R 1000,3000,ref_ref,q_30 +R 1000,3500,ref_ref,q_35 +R 1000,4000,ref_ref,q_40 +R 4000,2000,ref_ref,i_20 +R 4000,2500,ref_ref,i_25 +R 4000,3000,ref_ref,i_30 +R 4000,3500,ref_ref,i_35 +R 4000,1500,ref_ref,i_15 +R 1500,1000,ref_ref,cmd_10 +R 1500,3000,ref_ref,cmd_30 +R 1500,3500,ref_ref,cmd_35 +R 1500,4000,ref_ref,cmd_40 +R 1500,1500,ref_ref,cmd_15 +R 1500,2000,ref_ref,cmd_20 +R 1500,2500,ref_ref,cmd_25 +S 1000,1100,1000,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 600,2300,4700,2300,100,*,RIGHT,POLY +S 2300,3100,3200,3100,100,*,RIGHT,POLY +S 3500,3500,3500,4000,200,*,UP,ALU1 +S 2100,4000,2400,4000,200,*,RIGHT,ALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 300,3000,300,4500,200,*,DOWN,ALU1 +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2300,1200,2600,100,*,DOWN,POLY +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1900,2800,1900,3000,300,*,UP,POLY +S 1500,3000,1900,3000,200,*,RIGHT,ALU1 +S 600,2300,600,2600,100,*,UP,POLY +S 1800,2800,3800,2800,100,*,RIGHT,POLY +S 3800,2800,3800,3100,100,*,DOWN,POLY +S 1800,2800,1800,3600,100,*,DOWN,POLY +S 3400,1800,3400,2700,200,*,DOWN,ALU1 +S 4200,3000,4400,3000,300,*,RIGHT,POLY +S 4000,3000,4200,3000,200,*,LEFT,ALU1 +S 2700,4700,3500,4700,300,*,RIGHT,NTIE +S 0,3900,5000,3900,2400,*,LEFT,NWELL +S 0,1000,5000,1000,1800,*,LEFT,PWELL +S 3500,3300,3500,4200,300,*,UP,PDIF +S 3800,3100,3800,4400,100,*,UP,PTRANS +S 2900,3300,2900,4200,300,*,UP,PDIF +S 3200,3100,3200,4400,100,*,UP,PTRANS +S 4400,1400,4400,1900,100,*,DOWN,POLY +S 3400,1900,4400,1900,100,*,RIGHT,POLY +S 600,1900,2900,1900,100,*,RIGHT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 600,1400,600,1900,100,*,DOWN,POLY +S 4100,3300,4100,4700,300,*,UP,PDIF +S 4700,3300,4700,4200,300,*,UP,PDIF +S 4400,3100,4400,4400,100,*,UP,PTRANS +S 4100,300,4700,300,300,*,RIGHT,PTIE +S 2100,300,2900,300,300,*,RIGHT,PTIE +S 4000,1500,4000,3500,200,*,DOWN,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 3500,400,3500,1200,300,*,UP,NDIF +S 2900,1000,2900,4000,200,*,DOWN,ALU1 +S 2900,1000,4100,1000,200,*,RIGHT,ALU1 +S 3800,600,3800,1400,100,*,UP,NTRANS +S 3200,600,3200,1400,100,*,UP,NTRANS +S 4700,800,4700,1200,300,*,UP,NDIF +S 4400,600,4400,1400,100,*,UP,NTRANS +S 2900,800,2900,1200,300,*,UP,NDIF +S 4100,800,4100,1200,300,*,UP,NDIF +S 4700,1000,4700,4000,200,*,DOWN,ALU1 +S 3800,1500,4000,1500,300,*,RIGHT,POLY +S 3500,4000,4700,4000,200,*,RIGHT,ALU1 +S 2100,3800,2100,4700,300,*,UP,PDIF +S 1800,3600,1800,4900,100,*,UP,PTRANS +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 600,100,600,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 1600,1500,1800,1500,300,*,RIGHT,POLY +S 1500,1500,1600,1500,200,*,RIGHT,ALU1 +S 2400,1000,2400,4000,200,*,DOWN,ALU1 +S 2300,1400,3200,1400,100,*,RIGHT,POLY +S 2100,1000,2400,1000,200,*,RIGHT,ALU1 +S 4000,1500,4000,3500,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,cmd,DOWN,CALU1 +V 2400,3200,CONT_POLY,* +V 2900,3500,CONT_DIF_P,* +V 4700,3500,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 1900,3000,CONT_POLY,* +V 4200,3000,CONT_POLY,* +V 3500,4700,CONT_BODY_N,* +V 2700,4700,CONT_BODY_N,* +V 4700,2300,CONT_POLY,* +V 3400,2700,CONT_POLY,* +V 900,3000,CONT_DIF_P,* +V 3400,1800,CONT_POLY,* +V 2100,300,CONT_BODY_P,* +V 4100,300,CONT_BODY_P,* +V 4700,300,CONT_BODY_P,* +V 2900,300,CONT_BODY_P,* +V 300,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 3500,4000,CONT_DIF_P,* +V 4100,1000,CONT_DIF_N,* +V 3500,500,CONT_DIF_N,* +V 4700,1000,CONT_DIF_N,* +V 2900,1000,CONT_DIF_N,* +V 4000,1500,CONT_POLY,* +V 4100,4500,CONT_DIF_P,* +V 2900,4000,CONT_DIF_P,* +V 4700,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1600,1500,CONT_POLY,* +V 2900,1800,CONT_POLY,* +V 2400,1500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x4.vbe new file mode 100644 index 000000000..25d28a499 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x4.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphl_cmd_q : NATURAL := 409; + CONSTANT tpll_i_q : NATURAL := 444; + CONSTANT tphh_i_q : NATURAL := 475; + CONSTANT tphh_cmd_q : NATURAL := 492; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x4; + +ARCHITECTURE behaviour_data_flow OF ts_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x4" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1100 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x8.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x8.ap new file mode 100644 index 000000000..8624a421c --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x8.ap @@ -0,0 +1,162 @@ +V ALLIANCE : 6 +H ts_x8,P,15/ 6/2016,100 +A 0,0,6500,5000 +R 5500,1500,ref_ref,i_15 +R 3000,1000,ref_ref,cmd_10 +R 3000,3000,ref_ref,cmd_30 +R 3000,3500,ref_ref,cmd_35 +R 3000,4000,ref_ref,cmd_40 +R 3000,1500,ref_ref,cmd_15 +R 3000,2000,ref_ref,cmd_20 +R 3000,2500,ref_ref,cmd_25 +R 2500,2500,ref_ref,q_25 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +R 5500,2000,ref_ref,i_20 +R 5500,2500,ref_ref,i_25 +R 5500,3000,ref_ref,i_30 +R 5500,3500,ref_ref,i_35 +R 2500,1000,ref_ref,q_10 +R 2500,1500,ref_ref,q_15 +R 2500,2000,ref_ref,q_20 +S 2500,1100,2500,4000,200,q,DOWN,CALU1 +S 2500,1000,2500,4000,200,*,UP,ALU1 +S 900,2300,6200,2300,100,*,RIGHT,POLY +S 1200,2100,2500,2100,200,*,RIGHT,ALU1 +S 1200,1000,1200,4000,200,*,DOWN,ALU1 +S 4400,1000,5600,1000,200,*,RIGHT,ALU1 +S 6200,1000,6200,4000,200,*,DOWN,ALU1 +S 5000,4000,6200,4000,200,*,RIGHT,ALU1 +S 3000,1000,3000,4000,200,*,UP,ALU1 +S 3000,1500,3100,1500,200,*,RIGHT,ALU1 +S 3000,3000,3400,3000,200,*,RIGHT,ALU1 +S 3900,1000,3900,4000,200,*,DOWN,ALU1 +S 4900,1800,4900,2700,200,*,DOWN,ALU1 +S 5500,3000,5700,3000,200,*,LEFT,ALU1 +S 5500,1500,5500,3500,200,*,DOWN,ALU1 +S 4400,1000,4400,4000,200,*,DOWN,ALU1 +S 3600,4000,3900,4000,200,*,RIGHT,ALU1 +S 1800,500,1800,1000,200,*,DOWN,ALU1 +S 1800,3000,1800,4500,200,*,DOWN,ALU1 +S 3600,1000,3900,1000,200,*,RIGHT,ALU1 +S 600,3000,600,4500,200,*,DOWN,ALU1 +S 600,500,600,1000,200,*,DOWN,ALU1 +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 5900,1400,5900,1900,100,*,DOWN,POLY +S 4900,1900,5900,1900,100,*,RIGHT,POLY +S 2700,1400,2700,1900,100,*,DOWN,POLY +S 2100,1400,2100,1900,100,*,DOWN,POLY +S 5300,1500,5500,1500,300,*,RIGHT,POLY +S 3100,1500,3300,1500,300,*,RIGHT,POLY +S 3400,2800,3400,3000,300,*,UP,POLY +S 2100,2300,2100,2600,100,*,UP,POLY +S 3300,2800,5300,2800,100,*,RIGHT,POLY +S 5300,2800,5300,3100,100,*,DOWN,POLY +S 3300,2800,3300,3600,100,*,DOWN,POLY +S 5700,3000,5900,3000,300,*,RIGHT,POLY +S 2700,2300,2700,2600,100,*,DOWN,POLY +S 3800,1400,4700,1400,100,*,RIGHT,POLY +S 900,1900,4400,1900,100,*,RIGHT,POLY +S 900,2300,900,2600,100,*,DOWN,POLY +S 1500,2300,1500,2600,100,*,UP,POLY +S 900,1400,900,1900,100,*,DOWN,POLY +S 1500,1400,1500,1900,100,*,DOWN,POLY +S 5600,300,6200,300,300,*,RIGHT,PTIE +S 3600,300,4400,300,300,*,RIGHT,PTIE +S 4200,4700,5000,4700,300,*,RIGHT,NTIE +S 5900,3100,5900,4400,100,*,UP,PTRANS +S 1800,2800,1800,4700,300,*,UP,PDIF +S 2100,2600,2100,4900,100,*,UP,PTRANS +S 3600,3800,3600,4700,300,*,UP,PDIF +S 3300,3600,3300,4900,100,*,UP,PTRANS +S 5000,3300,5000,4200,300,*,UP,PDIF +S 5300,3100,5300,4400,100,*,UP,PTRANS +S 4400,3300,4400,4200,300,*,UP,PDIF +S 4700,3100,4700,4400,100,*,UP,PTRANS +S 6200,3300,6200,4200,300,*,UP,PDIF +S 2400,2800,2400,4700,300,*,UP,PDIF +S 3000,2800,3000,4700,300,*,UP,PDIF +S 2700,2600,2700,4900,100,*,UP,PTRANS +S 1200,2800,1200,4700,300,*,UP,PDIF +S 900,2600,900,4900,100,*,UP,PTRANS +S 1500,2600,1500,4900,100,*,UP,PTRANS +S 600,2800,600,4700,300,*,UP,PDIF +S 1800,300,1800,1200,300,*,UP,NDIF +S 2700,100,2700,1400,100,*,UP,NTRANS +S 2100,100,2100,1400,100,*,UP,NTRANS +S 3000,300,3000,1200,300,*,UP,NDIF +S 2400,300,2400,1200,300,*,UP,NDIF +S 6200,800,6200,1200,300,*,UP,NDIF +S 5900,600,5900,1400,100,*,UP,NTRANS +S 4400,800,4400,1200,300,*,UP,NDIF +S 5600,800,5600,1200,300,*,UP,NDIF +S 3600,800,3600,1200,300,*,UP,NDIF +S 3300,600,3300,1400,100,*,UP,NTRANS +S 5000,400,5000,1200,300,*,UP,NDIF +S 5300,600,5300,1400,100,*,UP,NTRANS +S 4700,600,4700,1400,100,*,UP,NTRANS +S 600,300,600,1200,300,*,UP,NDIF +S 1200,300,1200,1200,300,*,UP,NDIF +S 900,100,900,1400,100,*,UP,NTRANS +S 1500,100,1500,1400,100,*,UP,NTRANS +S 0,3900,6500,3900,2400,*,LEFT,NWELL +S 0,1000,6500,1000,1800,*,LEFT,PWELL +S 5000,3500,5000,4000,200,*,UP,ALU1 +S 3850,3100,4700,3100,100,*,RIGHT,POLY +S 5600,3300,5600,4550,300,*,UP,PDIF +S 5500,1500,5500,3500,200,i,DOWN,CALU1 +S 3000,1000,3000,4000,200,cmd,DOWN,CALU1 +V 3400,3000,CONT_POLY,* +V 6200,2300,CONT_POLY,* +V 4900,2700,CONT_POLY,* +V 4900,1800,CONT_POLY,* +V 5700,3000,CONT_POLY,* +V 5500,1500,CONT_POLY,* +V 3100,1500,CONT_POLY,* +V 3900,1500,CONT_POLY,* +V 4400,1800,CONT_POLY,* +V 3600,300,CONT_BODY_P,* +V 5600,300,CONT_BODY_P,* +V 6200,300,CONT_BODY_P,* +V 4400,300,CONT_BODY_P,* +V 5000,4700,CONT_BODY_N,* +V 4200,4700,CONT_BODY_N,* +V 3600,4000,CONT_DIF_P,* +V 1800,4500,CONT_DIF_P,* +V 1800,3500,CONT_DIF_P,* +V 1800,4000,CONT_DIF_P,* +V 2400,3500,CONT_DIF_P,* +V 2400,4000,CONT_DIF_P,* +V 1800,3000,CONT_DIF_P,* +V 3000,4500,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 5600,4500,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 6200,4000,CONT_DIF_P,* +V 2400,3000,CONT_DIF_P,* +V 600,4000,CONT_DIF_P,* +V 600,3500,CONT_DIF_P,* +V 600,3000,CONT_DIF_P,* +V 600,4500,CONT_DIF_P,* +V 1200,3000,CONT_DIF_P,* +V 1200,3500,CONT_DIF_P,* +V 1200,4000,CONT_DIF_P,* +V 4400,1000,CONT_DIF_N,* +V 3600,1000,CONT_DIF_N,* +V 1800,500,CONT_DIF_N,* +V 3000,500,CONT_DIF_N,* +V 1800,1000,CONT_DIF_N,* +V 2400,1000,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +V 5000,500,CONT_DIF_N,* +V 6200,1000,CONT_DIF_N,* +V 1200,1000,CONT_DIF_N,* +V 600,1000,CONT_DIF_N,* +V 600,500,CONT_DIF_N,* +V 5000,3500,CONT_DIF_P,* +V 6200,3500,CONT_DIF_P,* +V 3900,3200,CONT_POLY,* +V 4400,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x8.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x8.vbe new file mode 100644 index 000000000..c92f94f59 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/ts_x8.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 400; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_cmd_q : NATURAL := 450; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphl_cmd_q : NATURAL := 466; + CONSTANT tpll_i_q : NATURAL := 569; + CONSTANT tphh_i_q : NATURAL := 613; + CONSTANT tphh_cmd_q : NATURAL := 626; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x8; + +ARCHITECTURE behaviour_data_flow OF ts_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x8" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1200 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x1.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x1.ap new file mode 100644 index 000000000..2d30b350c --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x1.ap @@ -0,0 +1,121 @@ +V ALLIANCE : 6 +H xr2_x1,P, 9/12/2016,100 +A 0,0,4500,5000 +R 3500,2000,ref_ref,i1_25 +R 2000,3000,ref_ref,q_30 +R 2000,3500,ref_ref,q_35 +R 3500,4000,ref_ref,i1_40 +R 3500,3500,ref_ref,i1_35 +R 3500,3000,ref_ref,i1_30 +R 3500,1000,ref_ref,i1_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_25 +R 1000,3000,ref_ref,i0_30 +R 1000,2000,ref_ref,i0_20 +R 1000,1000,ref_ref,i0_10 +R 1500,1000,ref_ref,q_10 +R 1500,1500,ref_ref,q_15 +R 1500,2000,ref_ref,q_20 +R 1500,2500,ref_ref,q_25 +R 1000,2500,ref_ref,i0_35 +S 3600,2400,3600,3000,100,*,UP,POLY +S 3000,1800,3000,2000,300,*,UP,POLY +S 4000,1800,4000,2000,300,*,UP,POLY +S 3000,2600,3500,2600,100,*,RIGHT,POLY +S 3000,1800,4000,1800,100,*,RIGHT,POLY +S 300,3100,300,3500,200,*,DOWN,ALU1 +S 300,1000,300,1500,200,*,UP,ALU1 +S 1500,1000,1500,3000,200,q,DOWN,CALU1 +S 3800,300,4300,300,300,*,RIGHT,PTIE +S 3800,4700,4300,4700,300,*,RIGHT,NTIE +S 1500,3500,1500,4000,200,*,UP,ALU1 +S 4000,3500,4000,4000,200,*,DOWN,ALU1 +S 1500,3000,2000,3000,200,*,LEFT,ALU1 +S 2000,3000,2000,3500,200,*,DOWN,ALU1 +S 2700,3000,2700,4000,200,*,UP,ALU1 +S 300,3500,300,4000,200,*,DOWN,ALU1 +S 4000,800,4000,1200,300,*,UP,NDIF +S 4000,3300,4000,4200,300,*,DOWN,PDIF +S 2000,2500,2500,2500,200,*,RIGHT,ALU1 +S 2500,2000,3000,2000,200,*,RIGHT,ALU1 +S 2500,2000,2500,2500,200,*,DOWN,ALU1 +S 3000,1400,3000,2000,100,*,DOWN,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 2000,1500,3500,1500,200,*,RIGHT,ALU1 +S 3500,1000,3500,4000,200,*,DOWN,ALU1 +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 3600,3100,3600,4400,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 600,2600,600,3100,100,*,DOWN,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 1500,4000,2700,4000,200,*,RIGHT,ALU1 +S 0,1000,4500,1000,1800,*,RIGHT,PWELL +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 1500,1000,2100,1000,200,*,RIGHT,ALU1 +S 3500,1000,3500,4000,200,i1,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 1500,1000,1500,3000,200,*,UP,ALU1 +S 4000,1000,4000,2400,200,*,DOWN,ALU1 +S 4300,2400,4300,3500,200,*,UP,ALU1 +S 4000,2400,4300,2400,200,*,RIGHT,ALU1 +S 4000,3500,4300,3500,200,*,RIGHT,ALU1 +S 3600,2900,3600,3100,100,*,DOWN,POLY +S 300,1700,300,3000,200,*,DOWN,ALU1 +S 600,2600,1200,2600,100,*,RIGHT,POLY +V 3500,2500,CONT_POLY,* +V 1500,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 4000,1000,CONT_DIF_N,* +V 4000,3500,CONT_DIF_P,* +V 4000,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2100,3500,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 3900,4700,CONT_BODY_N,* +V 3900,300,CONT_BODY_P,* +V 1000,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 300,4600,CONT_BODY_N,* +V 800,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x1.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x1.vbe new file mode 100644 index 000000000..925f29ad5 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY xr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i1_q : NATURAL := 261; + CONSTANT tphl_i0_q : NATURAL := 292; + CONSTANT tplh_i0_q : NATURAL := 293; + CONSTANT tphh_i0_q : NATURAL := 366; + CONSTANT tphl_i1_q : NATURAL := 377; + CONSTANT tpll_i1_q : NATURAL := 388; + CONSTANT tpll_i0_q : NATURAL := 389; + CONSTANT tphh_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x1; + +ARCHITECTURE behaviour_data_flow OF xr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x1" + SEVERITY WARNING; + q <= (i0 xor i1) after 1000 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x4.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x4.ap new file mode 100644 index 000000000..c1c5a221e --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x4.ap @@ -0,0 +1,144 @@ +V ALLIANCE : 6 +H xr2_x4,P, 9/12/2016,100 +A 0,0,6000,5000 +R 5000,4000,ref_ref,q_40 +R 5000,1000,ref_ref,q_10 +R 5000,3000,ref_ref,q_30 +R 5000,3500,ref_ref,q_35 +R 5000,2500,ref_ref,q_25 +R 5000,2000,ref_ref,q_20 +R 5000,1500,ref_ref,q_15 +R 3500,4000,ref_ref,i1_40 +R 3500,3500,ref_ref,i1_35 +R 3500,3000,ref_ref,i1_30 +R 3500,1500,ref_ref,i1_15 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1000,1000,ref_ref,i0_10 +R 1000,3000,ref_ref,i0_25 +R 3500,2000,ref_ref,i1_25 +S 3000,1800,3000,2000,300,*,UP,POLY +S 4000,1800,4000,2000,300,*,UP,POLY +S 300,4300,300,4800,300,*,DOWN,NTIE +S 3900,4300,3900,4800,300,*,DOWN,NTIE +S 4500,2000,5400,2000,300,*,RIGHT,POLY +S 5000,1000,5000,4000,200,q,DOWN,CALU1 +S 3500,1500,3500,4000,200,i1,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 0,3900,6000,3900,2400,*,LEFT,NWELL +S 0,1000,6000,1000,1800,*,LEFT,PWELL +S 4500,300,4500,1000,300,*,UP,NDIF +S 3900,800,3900,1600,300,*,UP,NDIF +S 1500,1000,4500,1000,200,*,RIGHT,ALU1 +S 4500,1000,4500,2000,200,*,DOWN,ALU1 +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 5400,1400,5400,2600,100,*,DOWN,POLY +S 5700,500,5700,1000,200,*,DOWN,ALU1 +S 5700,3000,5700,4500,200,*,DOWN,ALU1 +S 4500,3500,4500,4500,200,*,DOWN,ALU1 +S 3500,1500,3500,4000,200,*,DOWN,ALU1 +S 4000,1500,4000,2900,200,*,DOWN,ALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 5700,300,5700,1200,300,*,UP,NDIF +S 5100,300,5100,1200,300,*,UP,NDIF +S 5400,100,5400,1400,100,*,DOWN,NTRANS +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 3900,2800,3900,3700,300,*,DOWN,PDIF +S 4500,3400,4500,4700,300,*,DOWN,PDIF +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 600,2600,600,3900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,UP,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 5700,2800,5700,4700,300,*,DOWN,PDIF +S 2500,2000,3000,2000,200,*,RIGHT,ALU1 +S 2500,1500,2500,2000,200,*,DOWN,ALU1 +S 2000,1500,2500,1500,200,*,RIGHT,ALU1 +S 3000,1400,3600,1400,100,*,RIGHT,POLY +S 2000,2500,3500,2500,200,*,RIGHT,ALU1 +S 3000,2000,3000,2600,100,*,DOWN,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 1500,4000,2700,4000,200,*,RIGHT,ALU1 +S 300,1000,300,3000,200,*,DOWN,ALU1 +S 2100,3000,2100,3500,200,*,DOWN,ALU1 +S 1500,3000,2100,3000,200,*,LEFT,ALU1 +S 1500,1000,1500,3000,200,*,UP,ALU1 +S 1500,3500,1500,4000,200,*,UP,ALU1 +S 2700,3000,2700,4000,200,*,DOWN,ALU1 +S 300,3000,300,3500,200,*,UP,ALU1 +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +S 3000,1800,4000,1800,100,*,RIGHT,POLY +V 4500,2000,CONT_POLY,* +V 4000,2900,CONT_DIF_P,* +V 4000,1500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 5100,3000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 5700,3000,CONT_DIF_P,* +V 5700,3500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 5700,4500,CONT_DIF_P,* +V 5700,1000,CONT_DIF_N,* +V 5700,500,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 300,3000,CONT_DIF_P,* +V 3000,2000,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2100,3500,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 3900,4700,CONT_BODY_N,* +V 1000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 1500,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x4.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x4.vbe new file mode 100644 index 000000000..7e2da9edb --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/xr2_x4.vbe @@ -0,0 +1,36 @@ +ENTITY xr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 357; + CONSTANT tphh_i0_q : NATURAL := 476; + CONSTANT tpll_i0_q : NATURAL := 480; + CONSTANT tphl_i0_q : NATURAL := 521; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphl_i1_q : NATURAL := 541; + CONSTANT tplh_i0_q : NATURAL := 560; + CONSTANT tplh_i1_q : NATURAL := 657; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x4; + +ARCHITECTURE behaviour_data_flow OF xr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x4" + SEVERITY WARNING; + q <= (i0 xor i1) after 1300 ps; +END; diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/zero_x0.ap b/pdks/symbolic/hibikino/cells/sxlib_25um/zero_x0.ap new file mode 100644 index 000000000..a9b7c852f --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/zero_x0.ap @@ -0,0 +1,36 @@ +V ALLIANCE : 6 +H zero_x0,P,18/ 5/2002,100 +A 0,0,1500,5000 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1000,4000,ref_ref,nq_40 +S 400,500,1000,500,300,*,RIGHT,PTIE +S 400,300,400,1500,200,*,DOWN,ALU1 +S 500,2000,500,4700,200,*,DOWN,ALU1 +S 700,1100,700,1900,100,*,DOWN,NTRANS +S 1000,1300,1000,1700,300,*,UP,NDIF +S 350,1300,350,1700,400,*,UP,NDIF +S 400,2000,700,2000,300,*,RIGHT,POLY +S 500,4500,1000,4500,300,*,LEFT,NTIE +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 0,1000,1500,1000,1800,*,RIGHT,PWELL +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 0,300,1500,300,600,vss,RIGHT,CALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 500,3000,500,4600,300,*,UP,NTIE +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +V 400,500,CONT_BODY_P,* +V 1000,500,CONT_BODY_P,* +V 1000,1500,CONT_DIF_N,* +V 400,1500,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 500,4500,CONT_BODY_N,* +V 1000,4500,CONT_BODY_N,* +V 500,3000,CONT_BODY_N,* +V 500,3500,CONT_BODY_N,* +V 500,4000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/hibikino/cells/sxlib_25um/zero_x0.vbe b/pdks/symbolic/hibikino/cells/sxlib_25um/zero_x0.vbe new file mode 100644 index 000000000..535efebc9 --- /dev/null +++ b/pdks/symbolic/hibikino/cells/sxlib_25um/zero_x0.vbe @@ -0,0 +1,20 @@ +ENTITY zero_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END zero_x0; + +ARCHITECTURE behaviour_data_flow OF zero_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on zero_x0" + SEVERITY WARNING; + nq <= '0'; +END; diff --git a/pdks/symbolic/lsxlib/LSXLIB.pdf b/pdks/symbolic/lsxlib/LSXLIB.pdf new file mode 100644 index 000000000..8cdd7e549 Binary files /dev/null and b/pdks/symbolic/lsxlib/LSXLIB.pdf differ diff --git a/pdks/symbolic/lsxlib/cells/CATAL b/pdks/symbolic/lsxlib/cells/CATAL new file mode 100644 index 000000000..5657ebeb3 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/CATAL @@ -0,0 +1,93 @@ +a2_x2 C +a2_x4 C +a3_x2 C +a3_x4 C +a4_x2 C +a4_x4 C +an12_x1 C +an12_x4 C +ao22_x2 C +ao22_x4 C +ao2o22_x2 C +ao2o22_x4 C +buf_x2 C +buf_x4 C +buf_x8 C +inv_x1 C +inv_x2 C +inv_x4 C +inv_x8 C +mx2_x2 C +mx2_x4 C +mx3_x2 C +mx3_x4 C +na2_x1 C +na2_x4 C +na3_x1 C +na3_x4 C +na4_x1 C +na4_x4 C +nao22_x1 C +nao22_x4 C +nao2o22_x1 C +nao2o22_x4 C +nmx2_x1 C +nmx2_x4 C +nmx3_x1 C +no2_x1 C +no2_x4 C +no3_x1 C +no3_x4 C +no4_x1 C +no4_x4 C +noa22_x1 C +noa22_x4 C +noa2a22_x1 C +noa2a22_x4 C +noa2a2a23_x1 C +noa2a2a23_x4 C +noa2a2a2a24_x1 C +noa2a2a2a24_x4 C +noa2ao222_x1 C +noa2ao222_x4 C +noa3ao322_x1 C +noa3ao322_x4 C +nts_x1 C +nts_x2 C +nxr2_x1 C +nxr2_x4 C +o2_x2 C +o2_x4 C +o3_x2 C +o3_x4 C +o4_x2 C +o4_x4 C +oa22_x2 C +oa22_x4 C +oa2a22_x2 C +oa2a22_x4 C +oa2a2a23_x2 C +oa2a2a23_x4 C +oa2a2a2a24_x2 C +oa2a2a2a24_x4 C +oa2ao222_x2 C +oa2ao222_x4 C +oa3ao322_x2 C +oa3ao322_x4 C +on12_x1 C +on12_x4 C +one_x0 C +powmid_x0 C +powmid_x0 F +rowend_x0 C +rowend_x0 F +sff1_x4 C +sff1r_x4 C +sff2_x4 C +tie_x0 C +tie_x0 F +ts_x4 C +ts_x8 C +xr2_x1 C +xr2_x4 C +zero_x0 C diff --git a/pdks/symbolic/lsxlib/cells/a2_x2.ap b/pdks/symbolic/lsxlib/cells/a2_x2.ap new file mode 100644 index 000000000..9c8937468 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a2_x2.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H a2_x2,P,31/ 7/2024,100 +A 0,0,2500,5000 +S 0,1100,2500,1100,1400,*,RIGHT,PWELL +S 1800,2300,2000,2300,100,*,RIGHT,POLY +S 1000,2300,1200,2300,100,*,RIGHT,POLY +S 600,1800,800,1800,100,*,LEFT,POLY +S 0,5000,2500,5000,300,*,RIGHT,NTIE +S 0,4000,2500,4000,1200,*,RIGHT,NWELL +S 0,3100,2500,3100,1200,*,RIGHT,NWELL +S 1500,500,1500,1400,300,*,DOWN,NDIF +S 1800,1600,1800,3400,100,*,DOWN,POLY +S 1200,1600,1200,3400,100,*,UP,POLY +S 300,2600,300,4500,300,*,DOWN,PDIF +S 600,2400,600,4700,100,*,DOWN,PTRANS +S 1200,3400,1200,4700,100,*,UP,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 2100,3600,2100,4500,300,*,DOWN,PDIF +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 600,300,600,1600,100,*,UP,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 300,500,300,1400,300,*,UP,NDIF +S 900,500,900,1400,300,*,UP,NDIF +S 2100,500,2100,1400,300,*,UP,NDIF +S 0,0,2500,0,300,*,RIGHT,PTIE +S 600,1600,600,2400,100,*,DOWN,POLY +S 300,600,300,4400,200,q,UP,CALU1 +S 0,0,2500,0,400,vss,RIGHT,CALU1 +S 900,0,900,1300,200,*,DOWN,ALU1 +S 1500,600,1500,4400,200,*,DOWN,ALU1 +S 1500,600,2100,600,200,*,RIGHT,ALU1 +S 0,5000,2500,5000,400,vdd,RIGHT,CALU1 +S 800,1800,1500,1800,200,*,RIGHT,ALU1 +S 1000,2300,1000,3900,200,i0,DOWN,CALU1 +S 2000,1100,2000,3900,200,i1,DOWN,CALU1 +S 900,4400,900,5000,200,*,UP,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +B 750,1800,300,200,CONT_TURN8,* +B 1950,2300,300,200,CONT_TURN8,* +B 1050,2300,300,200,CONT_TURN8,* +B 1500,600,200,200,CONT_TURN1,* +V 300,2700,CONT_DIF_P,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 300,3300,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,4400,CONT_DIF_P,* +V 1500,3700,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 300,1300,CONT_DIF_N,* +V 900,1300,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 800,1800,CONT_POLY,* +V 2000,2300,CONT_POLY,* +V 1000,2300,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/a2_x2.vbe b/pdks/symbolic/lsxlib/cells/a2_x2.vbe new file mode 100644 index 000000000..8e6db7cd8 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i1_q : NATURAL := 203; + CONSTANT tphh_i0_q : NATURAL := 261; + CONSTANT tpll_i0_q : NATURAL := 388; + CONSTANT tpll_i1_q : NATURAL := 434; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x2; + +ARCHITECTURE behaviour_data_flow OF a2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x2" + SEVERITY WARNING; + q <= (i0 and i1) after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/a2_x4.ap b/pdks/symbolic/lsxlib/cells/a2_x4.ap new file mode 100644 index 000000000..724dc36ec --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a2_x4.ap @@ -0,0 +1,87 @@ +V ALLIANCE : 6 +H a2_x4,P,31/ 7/2024,100 +A 0,0,3000,5000 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 2400,2300,2600,2300,100,*,RIGHT,POLY +S 1600,2300,1800,2300,100,*,RIGHT,POLY +S 600,1800,1400,1800,100,*,RIGHT,POLY +S 300,2700,300,5000,200,*,UP,ALU1 +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 2400,1600,2400,3400,100,*,DOWN,POLY +S 1800,1600,1800,3400,100,*,UP,POLY +S 2100,500,2100,1400,300,*,DOWN,NDIF +S 300,2600,300,4500,300,*,DOWN,PDIF +S 2700,4400,2700,5000,200,*,UP,ALU1 +S 1500,4400,1500,5000,200,*,UP,ALU1 +S 1500,0,1500,1300,200,*,DOWN,ALU1 +S 300,0,300,1300,200,*,DOWN,ALU1 +S 600,2400,600,4700,100,*,DOWN,PTRANS +S 1200,2400,1200,4700,100,*,DOWN,PTRANS +S 2700,3600,2700,4500,300,*,DOWN,PDIF +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 2400,3400,2400,4700,100,*,UP,PTRANS +S 2100,3600,2100,4500,300,*,DOWN,PDIF +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 1200,300,1200,1600,100,*,UP,NTRANS +S 2400,300,2400,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 600,300,600,1600,100,*,UP,NTRANS +S 300,500,300,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +S 2700,500,2700,1400,300,*,UP,NDIF +S 900,500,900,1400,300,*,UP,NDIF +S 600,1600,600,2400,100,*,DOWN,POLY +S 1200,1600,1200,2400,100,*,DOWN,POLY +S 2100,600,2100,4400,200,*,DOWN,ALU1 +S 2100,600,2700,600,200,*,RIGHT,ALU1 +S 900,600,900,4400,200,q,UP,CALU1 +S 1400,1800,2100,1800,200,*,RIGHT,ALU1 +S 1600,2300,1600,3900,200,i0,DOWN,CALU1 +S 2600,1100,2600,3900,200,i1,DOWN,CALU1 +S 0,0,3000,0,300,*,RIGHT,PTIE +S 0,0,3000,0,400,vss,RIGHT,CALU1 +S 0,5000,3000,5000,300,*,RIGHT,NTIE +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +B 2550,2300,300,200,CONT_TURN8,* +B 1650,2300,300,200,CONT_TURN8,* +B 1050,1800,900,200,CONT_TURN8,* +B 2100,600,200,200,CONT_TURN1,* +V 300,4400,CONT_DIF_P,* +V 300,3300,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 300,2700,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 900,3900,CONT_DIF_P,* +V 900,3300,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 2100,3700,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 900,2700,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 300,1300,CONT_DIF_N,* +V 1500,1300,CONT_DIF_N,* +V 900,1300,CONT_DIF_N,* +V 1400,1800,CONT_POLY,* +V 1600,2300,CONT_POLY,* +V 2600,2300,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/a2_x4.vbe b/pdks/symbolic/lsxlib/cells/a2_x4.vbe new file mode 100644 index 000000000..f6955d6e9 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphh_i0_q : NATURAL := 338; + CONSTANT tpll_i0_q : NATURAL := 476; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x4; + +ARCHITECTURE behaviour_data_flow OF a2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x4" + SEVERITY WARNING; + q <= (i0 and i1) after 1100 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/a3_x2.ap b/pdks/symbolic/lsxlib/cells/a3_x2.ap new file mode 100644 index 000000000..3867fa87b --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a3_x2.ap @@ -0,0 +1,87 @@ +V ALLIANCE : 6 +H a3_x2,P, 1/ 8/2024,100 +A 0,0,3000,5000 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 1500,500,1500,1400,300,*,DOWN,NDIF +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 1800,1600,1800,3400,100,*,DOWN,POLY +S 1200,1600,1200,3400,100,*,UP,POLY +S 2400,1600,2400,3400,100,*,DOWN,POLY +S 2000,1100,2000,3400,200,i1,DOWN,CALU1 +S 2600,1100,2600,3400,200,i2,DOWN,CALU1 +S 2700,3900,2700,4400,200,*,UP,ALU1 +S 1500,3900,2700,3900,200,*,RIGHT,ALU1 +S 2700,3600,2700,4500,300,*,DOWN,PDIF +S 2700,500,2700,1400,300,*,UP,NDIF +S 1500,600,2700,600,200,*,RIGHT,ALU1 +S 2400,300,2400,1600,100,*,DOWN,NTRANS +S 2400,3400,2400,4700,100,*,UP,PTRANS +S 2400,2300,2600,2300,200,*,RIGHT,POLY +S 0,0,3000,0,300,*,RIGHT,PTIE +S 0,0,3000,0,400,vss,RIGHT,CALU1 +S 0,5000,3000,5000,300,*,RIGHT,NTIE +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +S 300,2600,300,4500,300,*,DOWN,PDIF +S 600,2400,600,4700,100,*,DOWN,PTRANS +S 1200,3400,1200,4700,100,*,UP,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 2100,3600,2100,4500,300,*,DOWN,PDIF +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 600,300,600,1600,100,*,UP,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 300,500,300,1400,300,*,UP,NDIF +S 900,500,900,1400,300,*,UP,NDIF +S 2100,500,2100,1400,300,*,UP,NDIF +S 600,1800,800,1800,200,*,LEFT,POLY +S 1800,2300,2000,2300,200,*,RIGHT,POLY +S 1000,2300,1200,2300,200,*,RIGHT,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +S 300,600,300,4400,200,q,UP,CALU1 +S 900,0,900,1300,200,*,DOWN,ALU1 +S 1500,600,1500,4400,200,*,DOWN,ALU1 +S 800,1800,1500,1800,200,*,RIGHT,ALU1 +S 1000,2300,1000,3900,200,i0,DOWN,CALU1 +S 900,4400,900,5000,200,*,UP,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +B 2550,2300,300,200,CONT_TURN8,* +B 1950,2300,300,200,CONT_TURN8,* +B 1050,2300,300,200,CONT_TURN8,* +B 750,1800,300,200,CONT_TURN8,* +B 2700,3900,200,200,CONT_TURN1,* +B 1500,600,200,200,CONT_TURN1,* +V 2600,2300,CONT_POLY,* +V 2700,600,CONT_DIF_N,* +V 2700,4400,CONT_DIF_P,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 300,2700,CONT_DIF_P,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 300,3300,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,4400,CONT_DIF_P,* +V 1500,3700,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 300,1300,CONT_DIF_N,* +V 900,1300,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 800,1800,CONT_POLY,* +V 2000,2300,CONT_POLY,* +V 1000,2300,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/a3_x2.vbe b/pdks/symbolic/lsxlib/cells/a3_x2.vbe new file mode 100644 index 000000000..7a7b521b3 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 290; + CONSTANT tphh_i1_q : NATURAL := 353; + CONSTANT tphh_i0_q : NATURAL := 395; + CONSTANT tpll_i0_q : NATURAL := 435; + CONSTANT tpll_i1_q : NATURAL := 479; + CONSTANT tpll_i2_q : NATURAL := 521; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x2; + +ARCHITECTURE behaviour_data_flow OF a3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x2" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1100 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/a3_x4.ap b/pdks/symbolic/lsxlib/cells/a3_x4.ap new file mode 100644 index 000000000..9db1a6135 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a3_x4.ap @@ -0,0 +1,113 @@ +V ALLIANCE : 6 +H a3_x4,P, 1/ 8/2024,100 +A 0,0,3500,5000 +S 0,1100,3500,1100,1400,*,RIGHT,PWELL +S 2300,2000,2600,2000,100,*,RIGHT,POLY +S 600,2300,1200,2300,100,*,RIGHT,POLY +S 0,4000,3500,4000,1200,*,RIGHT,NWELL +S 0,3100,3500,3100,1200,*,RIGHT,NWELL +S 900,600,900,1800,200,q,UP,CALU1 +S 300,1800,300,3500,200,q,DOWN,CALU1 +S 300,1800,900,1800,200,*,LEFT,ALU1 +S 900,2300,900,2600,200,*,DOWN,ALU1 +S 1500,1100,1500,2100,200,i0,DOWN,CALU1 +S 1600,2000,1800,2000,200,*,RIGHT,POLY +S 900,2600,2100,2600,200,*,LEFT,ALU1 +S 1500,0,1500,600,200,*,DOWN,ALU1 +S 900,3300,900,4400,200,q,UP,CALU1 +S 300,3500,900,3500,200,*,RIGHT,ALU1 +S 300,4000,300,5000,200,*,UP,ALU1 +S 1500,3100,1500,5000,200,*,UP,ALU1 +S 1500,2600,1500,3100,300,*,DOWN,PDIF +S 3200,1100,3200,3400,200,i2,DOWN,CALU1 +S 2600,1100,2600,3400,200,i1,DOWN,CALU1 +S 2100,600,2100,3900,200,*,DOWN,ALU1 +S 1800,1600,1800,3400,100,*,UP,POLY +S 1700,3400,1800,3400,100,*,RIGHT,POLY +S 2900,2400,2900,3400,100,*,DOWN,POLY +S 2300,1600,2300,3400,100,*,UP,POLY +S 2600,4400,2600,5000,200,*,UP,ALU1 +S 2300,3400,2300,4700,100,*,UP,PTRANS +S 2600,3600,2600,4500,300,*,DOWN,PDIF +S 2900,3400,2900,4700,100,*,UP,PTRANS +S 3200,3600,3200,4500,300,*,DOWN,PDIF +S 2000,3600,2000,4500,300,*,DOWN,PDIF +S 1700,3400,1700,4700,100,*,UP,PTRANS +S 2000,3900,3200,3900,200,*,RIGHT,ALU1 +S 3200,3900,3200,4400,200,*,UP,ALU1 +S 2000,3900,2000,4400,200,*,DOWN,ALU1 +S 2100,600,3200,600,200,*,RIGHT,ALU1 +S 3000,2000,3200,2000,200,*,LEFT,POLY +S 2900,2400,3000,2400,100,*,RIGHT,POLY +S 3000,1600,3000,2400,100,*,UP,POLY +S 2900,1600,3000,1600,100,*,RIGHT,POLY +S 1400,2600,1400,4500,300,*,UP,PDIF +S 300,0,300,1300,200,*,DOWN,ALU1 +S 600,2400,600,4700,100,*,DOWN,PTRANS +S 300,2600,300,4500,300,*,DOWN,PDIF +S 1200,2400,1200,4700,100,*,DOWN,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 600,300,600,1600,100,*,UP,NTRANS +S 2900,300,2900,1600,100,*,DOWN,NTRANS +S 2300,300,2300,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 1200,300,1200,1600,100,*,UP,NTRANS +S 3200,500,3200,1400,300,*,UP,NDIF +S 300,500,300,1400,300,*,UP,NDIF +S 2600,500,2600,1400,300,*,UP,NDIF +S 900,500,900,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +S 600,1600,600,2400,100,*,DOWN,POLY +S 1200,1600,1200,2400,100,*,DOWN,POLY +S 0,0,3500,0,300,*,RIGHT,PTIE +S 0,0,3500,0,400,vss,RIGHT,CALU1 +S 0,5000,3500,5000,300,*,RIGHT,NTIE +S 0,5000,3500,5000,400,vdd,RIGHT,CALU1 +B 3150,2000,300,200,CONT_TURN8,* +B 1650,2000,300,200,CONT_TURN8,* +B 2500,2000,400,200,CONT_TURN8,* +B 900,2300,600,200,CONT_TURN8,* +B 900,2600,200,200,CONT_TURN1,* +B 900,1800,200,200,CONT_TURN1,* +B 300,1800,200,200,CONT_TURN1,* +B 2100,600,200,200,CONT_TURN1,* +B 300,3500,200,200,CONT_TURN1,* +V 3200,3900,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,3100,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 900,1300,CONT_DIF_N,* +V 300,1300,CONT_DIF_N,* +V 900,2300,CONT_POLY,* +V 1600,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,3100,CONT_DIF_P,* +V 2000,4400,CONT_DIF_P,* +V 2600,4400,CONT_DIF_P,* +V 3200,4400,CONT_DIF_P,* +V 2000,3900,CONT_DIF_P,* +V 3200,2000,CONT_POLY,* +V 2600,2000,CONT_POLY,* +V 300,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 3200,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/a3_x4.vbe b/pdks/symbolic/lsxlib/cells/a3_x4.vbe new file mode 100644 index 000000000..556b6b0fc --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 356; + CONSTANT tphh_i1_q : NATURAL := 428; + CONSTANT tphh_i0_q : NATURAL := 478; + CONSTANT tpll_i0_q : NATURAL := 514; + CONSTANT tpll_i1_q : NATURAL := 554; + CONSTANT tpll_i2_q : NATURAL := 592; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x4; + +ARCHITECTURE behaviour_data_flow OF a3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x4" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/a4_x2.ap b/pdks/symbolic/lsxlib/cells/a4_x2.ap new file mode 100644 index 000000000..a120abccd --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a4_x2.ap @@ -0,0 +1,112 @@ +V ALLIANCE : 6 +H a4_x2,P, 5/ 8/2024,100 +A 0,0,4000,5000 +S 3000,1700,3200,1700,200,*,RIGHT,POLY2 +S 2500,1700,2600,1700,200,*,RIGHT,POLY2 +S 1400,1700,1500,1700,200,*,LEFT,POLY2 +S 3000,3300,3200,3300,200,*,RIGHT,POLY2 +S 2500,3300,2600,3300,200,*,RIGHT,POLY2 +S 1400,3300,1500,3300,200,*,LEFT,POLY2 +S 0,1100,4000,1100,1400,*,RIGHT,PWELL +S 1700,3900,3500,3900,200,*,LEFT,ALU1 +S 2300,3600,2300,4500,300,*,DOWN,PDIF +S 2900,500,2900,1400,300,*,DOWN,NDIF +S 2300,500,2300,1400,300,*,DOWN,NDIF +S 1700,500,1700,1400,300,*,DOWN,NDIF +S 0,4000,4000,4000,1200,*,RIGHT,NWELL +S 0,3100,4000,3100,1200,*,RIGHT,NWELL +S 400,2600,400,4500,300,*,DOWN,PDIF +S 1400,3400,1400,4700,100,*,UP,PTRANS +S 700,2400,700,4700,100,*,DOWN,PTRANS +S 1700,3600,1700,4500,300,*,DOWN,PDIF +S 3500,3600,3500,4500,300,*,DOWN,PDIF +S 3200,3400,3200,4700,100,*,UP,PTRANS +S 2900,3600,2900,4500,300,*,DOWN,PDIF +S 2600,3400,2600,4700,100,*,UP,PTRANS +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 2000,3400,2000,4700,100,*,UP,PTRANS +S 1400,300,1400,1600,100,*,DOWN,NTRANS +S 2000,300,2000,1600,100,*,DOWN,NTRANS +S 3200,300,3200,1600,100,*,DOWN,NTRANS +S 2600,300,2600,1600,100,*,DOWN,NTRANS +S 700,300,700,1600,100,*,UP,NTRANS +S 1000,500,1000,1400,300,*,UP,NDIF +S 400,500,400,1400,300,*,UP,NDIF +S 3500,600,3500,1400,300,*,DOWN,NDIF +S 2000,1600,2000,1700,100,*,DOWN,POLY +S 700,1600,700,2400,100,*,DOWN,POLY +S 2000,3300,2000,3400,100,*,UP,POLY +S 1000,0,1000,1300,200,*,DOWN,ALU1 +S 1000,2700,1000,5000,200,*,UP,ALU1 +S 400,600,400,4400,200,q,DOWN,CALU1 +S 2300,4400,2300,5000,200,*,DOWN,ALU1 +S 3500,600,3500,3900,200,*,UP,ALU1 +S 2500,600,2500,3400,200,i2,DOWN,CALU1 +S 1700,3900,1700,4400,200,*,DOWN,ALU1 +S 3500,4400,3500,5000,200,*,DOWN,ALU1 +S 3000,600,3000,3400,200,i3,DOWN,CALU1 +S 2900,3900,2900,4400,200,*,DOWN,ALU1 +S 2000,600,2000,3400,200,i1,DOWN,CALU1 +S 1500,600,1500,3400,200,i0,DOWN,CALU1 +S 0,5000,4000,5000,300,*,RIGHT,NTIE +S 0,5000,4000,5000,400,vdd,RIGHT,CALU1 +S 0,0,4000,0,300,*,RIGHT,PTIE +S 0,0,4000,0,400,vss,RIGHT,CALU1 +B 3050,3300,300,200,CONT_TURN8,* +B 3050,1700,300,200,CONT_TURN8,* +B 2500,3300,200,200,CONT_TURN8,* +B 2000,3300,200,200,CONT_TURN8,* +B 1500,3300,200,200,CONT_TURN8,* +B 2500,1700,200,200,CONT_TURN8,* +B 2000,1700,200,200,CONT_TURN8,* +B 1500,1700,200,200,CONT_TURN8,* +B 2150,2200,2900,200,CONT_TURN8,* +B 3500,3900,200,200,CONT_TURN1,* +V 400,2700,CONT_DIF_P,* +V 1000,2700,CONT_DIF_P,* +V 1000,3300,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 2900,4400,CONT_DIF_P,* +V 2900,3900,CONT_DIF_P,* +V 1700,3900,CONT_DIF_P,* +V 3500,4400,CONT_DIF_P,* +V 1700,4400,CONT_DIF_P,* +V 2300,4400,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 1000,3900,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 400,3300,CONT_DIF_P,* +V 1000,600,CONT_DIF_N,* +V 1000,1300,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 400,1300,CONT_DIF_N,* +V 3500,600,CONT_DIF_N,* +V 3500,1300,CONT_DIF_N,* +V 2000,3300,CONT_POLY,* +V 2500,1700,CONT_POLY,* +V 3000,1700,CONT_POLY,* +V 2000,1700,CONT_POLY,* +V 1500,3300,CONT_POLY,* +V 3500,2200,CONT_POLY,* +V 1500,1700,CONT_POLY,* +V 3000,3300,CONT_POLY,* +V 2500,3300,CONT_POLY,* +V 4000,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/a4_x2.vbe b/pdks/symbolic/lsxlib/cells/a4_x2.vbe new file mode 100644 index 000000000..3a6353969 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 374; + CONSTANT tphh_i1_q : NATURAL := 441; + CONSTANT tpll_i3_q : NATURAL := 455; + CONSTANT tphh_i2_q : NATURAL := 482; + CONSTANT tpll_i2_q : NATURAL := 498; + CONSTANT tphh_i3_q : NATURAL := 506; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x2; + +ARCHITECTURE behaviour_data_flow OF a4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/a4_x4.ap b/pdks/symbolic/lsxlib/cells/a4_x4.ap new file mode 100644 index 000000000..ebbfa662e --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a4_x4.ap @@ -0,0 +1,121 @@ +V ALLIANCE : 6 +H a4_x4,P, 5/ 8/2024,100 +A 0,0,4500,5000 +S 2000,1700,2100,1700,200,*,LEFT,POLY2 +S 3100,1700,3200,1700,200,*,RIGHT,POLY2 +S 3600,1700,3800,1700,200,*,RIGHT,POLY2 +S 3600,3300,3800,3300,200,*,RIGHT,POLY2 +S 3100,3300,3200,3300,200,*,RIGHT,POLY2 +S 2000,3300,2100,3300,200,*,LEFT,POLY2 +S 0,1100,4500,1100,1400,*,RIGHT,PWELL +S 2300,3900,4100,3900,200,*,LEFT,ALU1 +S 3500,500,3500,1400,300,*,UP,NDIF +S 2900,500,2900,1400,300,*,UP,NDIF +S 2300,500,2300,1400,300,*,UP,NDIF +S 2900,3600,2900,4500,300,*,UP,PDIF +S 1300,2400,1300,4700,100,*,DOWN,PTRANS +S 1300,300,1300,1600,100,*,UP,NTRANS +S 700,300,700,1600,100,*,UP,NTRANS +S 700,2400,700,4700,100,*,DOWN,PTRANS +S 2600,3400,2600,4700,100,*,UP,PTRANS +S 3800,3400,3800,4700,100,*,UP,PTRANS +S 3200,3400,3200,4700,100,*,UP,PTRANS +S 2000,300,2000,1600,100,*,DOWN,NTRANS +S 3800,300,3800,1600,100,*,DOWN,NTRANS +S 3200,300,3200,1600,100,*,DOWN,NTRANS +S 2600,300,2600,1600,100,*,DOWN,NTRANS +S 2000,3400,2000,4700,100,*,UP,PTRANS +S 4100,600,4100,1400,300,*,DOWN,NDIF +S 1600,500,1600,1400,300,*,UP,NDIF +S 400,500,400,1400,300,*,UP,NDIF +S 1000,500,1000,1400,300,*,UP,NDIF +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 400,2600,400,4500,300,*,DOWN,PDIF +S 2300,3600,2300,4500,300,*,DOWN,PDIF +S 4100,3600,4100,4500,300,*,DOWN,PDIF +S 3500,3600,3500,4500,300,*,DOWN,PDIF +S 700,1600,700,2400,100,*,DOWN,POLY +S 1300,1600,1300,2400,100,*,DOWN,POLY +S 2600,1600,2600,1700,100,*,DOWN,POLY +S 2600,3300,2600,3400,100,*,UP,POLY +S 1600,0,1600,1300,200,*,DOWN,ALU1 +S 400,0,400,1300,200,*,DOWN,ALU1 +S 1000,600,1000,4400,200,q,DOWN,CALU1 +S 4100,4400,4100,5000,200,*,DOWN,ALU1 +S 2900,4400,2900,5000,200,*,DOWN,ALU1 +S 4100,600,4100,3900,200,*,UP,ALU1 +S 2300,3900,2300,4400,200,*,DOWN,ALU1 +S 3500,3900,3500,4400,200,*,DOWN,ALU1 +S 1600,2700,1600,5000,200,*,UP,ALU1 +S 400,2700,400,5000,200,*,UP,ALU1 +S 3600,600,3600,3400,200,i3,DOWN,CALU1 +S 2100,600,2100,3400,200,i0,DOWN,CALU1 +S 2600,600,2600,3400,200,i1,DOWN,CALU1 +S 3100,600,3100,3400,200,i2,DOWN,CALU1 +S 0,4000,4500,4000,1200,*,RIGHT,NWELL +S 0,3100,4500,3100,1200,*,RIGHT,NWELL +S 0,0,4500,0,300,*,RIGHT,PTIE +S 0,0,4500,0,400,vss,RIGHT,CALU1 +S 0,5000,4500,5000,300,*,RIGHT,NTIE +S 0,5000,4500,5000,400,vdd,RIGHT,CALU1 +B 2600,3300,200,200,CONT_TURN8,* +B 2600,1700,200,200,CONT_TURN8,* +B 2450,2200,3500,200,CONT_TURN8,* +B 4100,3900,200,200,CONT_TURN1,* +V 4100,600,CONT_DIF_N,* +V 4100,1300,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 1600,1300,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 400,1300,CONT_DIF_N,* +V 1000,1300,CONT_DIF_N,* +V 1000,600,CONT_DIF_N,* +V 1000,3900,CONT_DIF_P,* +V 1000,2700,CONT_DIF_P,* +V 1000,3300,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 3500,4400,CONT_DIF_P,* +V 3500,3900,CONT_DIF_P,* +V 4100,4400,CONT_DIF_P,* +V 2900,4400,CONT_DIF_P,* +V 1600,3300,CONT_DIF_P,* +V 1600,2700,CONT_DIF_P,* +V 1600,3900,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 400,3300,CONT_DIF_P,* +V 400,2700,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 2300,3900,CONT_DIF_P,* +V 2300,4400,CONT_DIF_P,* +V 4100,2200,CONT_POLY,* +V 3100,3300,CONT_POLY,* +V 3600,3300,CONT_POLY,* +V 2100,1700,CONT_POLY,* +V 3100,1700,CONT_POLY,* +V 2600,3300,CONT_POLY,* +V 3600,1700,CONT_POLY,* +V 2600,1700,CONT_POLY,* +V 2100,3300,CONT_POLY,* +V 4500,5000,CONT_BODY_N,* +V 4500,0,CONT_BODY_P,* +V 4000,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/a4_x4.vbe b/pdks/symbolic/lsxlib/cells/a4_x4.vbe new file mode 100644 index 000000000..4f96afa4c --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/a4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 540; + CONSTANT rdown_i1_q : NATURAL := 540; + CONSTANT rdown_i2_q : NATURAL := 540; + CONSTANT rdown_i3_q : NATURAL := 540; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 505; + CONSTANT tpll_i3_q : NATURAL := 538; + CONSTANT tpll_i2_q : NATURAL := 576; + CONSTANT tphh_i1_q : NATURAL := 578; + CONSTANT tpll_i1_q : NATURAL := 614; + CONSTANT tphh_i2_q : NATURAL := 627; + CONSTANT tpll_i0_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 661; + CONSTANT transistors : NATURAL := 13 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x4; + +ARCHITECTURE behaviour_data_flow OF a4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/an12_x1.ap b/pdks/symbolic/lsxlib/cells/an12_x1.ap new file mode 100644 index 000000000..28b94ba9a --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/an12_x1.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H an12_x1,P, 5/ 8/2024,100 +A 0,0,2500,5000 +S 1700,1200,1900,1200,200,*,RIGHT,POLY2 +S 1700,2300,1900,2300,200,*,RIGHT,POLY2 +S 0,1100,2500,1100,1400,*,RIGHT,PWELL +S 2200,600,2200,4400,200,*,UP,ALU1 +S 700,1800,900,1800,200,*,RIGHT,POLY +S 1300,1800,2200,1800,100,*,RIGHT,POLY +S 400,1100,1000,1100,200,*,RIGHT,ALU1 +S 0,4000,2500,4000,1200,*,RIGHT,NWELL +S 0,3100,2500,3100,1200,*,RIGHT,NWELL +S 1300,1100,1300,2400,100,*,UP,POLY +S 1000,600,1000,1100,200,q,DOWN,CALU1 +S 1000,1600,1000,4400,200,i0,DOWN,CALU1 +S 1900,2400,1900,3400,100,*,DOWN,POLY +S 2200,3600,2200,4500,300,*,UP,PDIF +S 1900,3400,1900,4700,100,*,UP,PTRANS +S 1000,500,1000,900,300,*,UP,NDIF +S 400,500,400,900,300,*,UP,NDIF +S 1600,500,1600,900,300,*,UP,NDIF +S 700,1100,700,2400,100,*,DOWN,POLY +S 2200,500,2200,900,300,*,DOWN,NDIF +S 1900,300,1900,1100,100,*,DOWN,NTRANS +S 1300,300,1300,1100,100,*,DOWN,NTRANS +S 700,300,700,1100,100,*,DOWN,NTRANS +S 400,1100,400,4400,200,q,DOWN,CALU1 +S 1700,1100,1700,3500,200,i1,DOWN,CALU1 +S 1600,4000,1600,5000,200,*,UP,ALU1 +S 400,2600,400,4500,300,*,DOWN,PDIF +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 700,2400,700,4700,100,*,UP,PTRANS +S 1300,2400,1300,4700,100,*,UP,PTRANS +S 1600,2600,1600,4500,300,*,UP,PDIF +S 0,0,2500,0,400,vss,RIGHT,CALU1 +S 0,5000,2500,5000,400,vdd,RIGHT,CALU1 +S 0,5000,2500,5000,300,*,RIGHT,NTIE +S 0,0,2500,0,300,*,RIGHT,PTIE +S 1600,0,1600,600,200,*,UP,ALU1 +S 400,0,400,600,200,*,UP,ALU1 +B 1800,1800,1000,200,CONT_TURN8,* +B 850,1800,300,200,CONT_TURN8,* +V 900,1800,CONT_POLY,* +V 2200,1800,CONT_POLY,* +V 2200,4400,CONT_DIF_P,* +V 2200,3800,CONT_DIF_P,* +V 1000,600,CONT_DIF_N,* +V 1700,1200,CONT_POLY,* +V 2200,600,CONT_DIF_N,* +V 400,3900,CONT_DIF_P,* +V 1600,4000,CONT_DIF_P,* +V 400,3300,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,2700,CONT_DIF_P,* +V 1700,2300,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 1600,600,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/an12_x1.vbe b/pdks/symbolic/lsxlib/cells/an12_x1.vbe new file mode 100644 index 000000000..10267b443 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/an12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 3640; + CONSTANT rdown_i1_q : NATURAL := 3640; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i0_q : NATURAL := 168; + CONSTANT tphl_i0_q : NATURAL := 200; + CONSTANT tphh_i1_q : NATURAL := 285; + CONSTANT tpll_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x1; + +ARCHITECTURE behaviour_data_flow OF an12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x1" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/an12_x4.ap b/pdks/symbolic/lsxlib/cells/an12_x4.ap new file mode 100644 index 000000000..df51b38ec --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/an12_x4.ap @@ -0,0 +1,111 @@ +V ALLIANCE : 6 +H an12_x4,P, 5/ 8/2024,100 +A 0,0,4000,5000 +S 600,1100,900,1100,200,*,LEFT,POLY2 +S 2100,1700,2200,1700,200,*,RIGHT,POLY2 +S 2000,3300,2200,3300,200,*,RIGHT,POLY2 +S 0,1100,4000,1100,1400,*,RIGHT,PWELL +S 300,4400,700,4400,200,*,RIGHT,ALU1 +S 1900,3600,1900,4500,300,*,UP,PDIF +S 3100,2600,3100,4500,300,*,UP,PDIF +S 3100,500,3100,1400,300,*,UP,NDIF +S 0,4000,4000,4000,1200,*,RIGHT,NWELL +S 0,3100,4000,3100,1200,*,RIGHT,NWELL +S 1500,3900,1900,3900,200,*,LEFT,ALU1 +S 1400,3600,1400,4500,300,*,DOWN,PDIF +S 700,3800,700,4500,300,*,DOWN,PDIF +S 1000,3600,1000,4700,100,*,UP,PTRANS +S 1000,3500,1000,3600,100,*,UP,POLY +S 1500,1300,1500,3900,200,*,DOWN,ALU1 +S 2500,2700,2500,5000,200,*,UP,ALU1 +S 3700,0,3700,1200,200,*,UP,ALU1 +S 2500,0,2500,1200,200,*,UP,ALU1 +S 2000,600,2000,3400,200,i1,DOWN,CALU1 +S 300,1600,1700,1600,100,*,LEFT,POLY +S 300,600,300,4400,200,*,UP,ALU1 +S 900,1100,900,3900,200,i0,DOWN,CALU1 +S 900,0,900,600,200,*,DOWN,ALU1 +S 300,2900,1600,2900,100,*,LEFT,POLY +S 600,300,600,1000,100,*,UP,NTRANS +S 300,500,300,800,300,*,UP,NDIF +S 900,500,900,800,300,*,UP,NDIF +S 1900,3900,1900,4400,200,*,UP,ALU1 +S 3100,600,3100,4400,200,q,UP,CALU1 +S 1300,4400,1300,5000,200,*,UP,ALU1 +S 3700,2700,3700,5000,200,*,UP,ALU1 +S 3700,500,3700,1400,300,*,DOWN,NDIF +S 3700,2600,3700,4500,300,*,UP,PDIF +S 2800,2400,2800,4700,100,*,UP,PTRANS +S 3400,2400,3400,4700,100,*,UP,PTRANS +S 2500,2600,2500,4500,300,*,DOWN,PDIF +S 2200,3400,2200,4700,100,*,UP,PTRANS +S 1600,3400,1600,4700,100,*,UP,PTRANS +S 2200,300,2200,1600,100,*,UP,NTRANS +S 1700,300,1700,1600,100,*,UP,NTRANS +S 2800,300,2800,1600,100,*,UP,NTRANS +S 3400,300,3400,1600,100,*,UP,NTRANS +S 2400,500,2400,1400,300,*,DOWN,NDIF +S 1500,500,1500,1400,300,*,DOWN,NDIF +S 2800,1600,2800,2400,100,*,UP,POLY +S 3400,1600,3400,2400,100,*,UP,POLY +S 1600,2900,1600,3400,100,*,UP,POLY +S 0,5000,4000,5000,400,vdd,RIGHT,CALU1 +S 0,0,4000,0,400,vss,RIGHT,CALU1 +S 0,5000,4000,5000,300,*,RIGHT,NTIE +S 0,0,4000,0,300,*,RIGHT,PTIE +B 1000,3500,200,200,CONT_TURN8,* +B 2400,2200,2000,200,CONT_TURN8,* +B 1500,1300,200,200,CONT_TURN1,* +B 1500,3900,200,200,CONT_TURN1,* +B 300,4400,200,200,CONT_TURN1,* +V 700,4400,CONT_DIF_P,* +V 1000,3500,CONT_POLY,* +V 1400,1300,CONT_DIF_N,* +V 1500,2200,CONT_POLY,* +V 2500,3300,CONT_DIF_P,* +V 2500,2700,CONT_DIF_P,* +V 2000,3300,CONT_POLY,* +V 3700,1200,CONT_DIF_N,* +V 3100,1200,CONT_DIF_N,* +V 2500,1200,CONT_DIF_N,* +V 300,1600,CONT_POLY,* +V 900,1100,CONT_POLY,* +V 300,2900,CONT_POLY,* +V 300,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 2500,3900,CONT_DIF_P,* +V 3100,3900,CONT_DIF_P,* +V 1900,3900,CONT_DIF_P,* +V 3700,3900,CONT_DIF_P,* +V 3100,3300,CONT_DIF_P,* +V 3100,2700,CONT_DIF_P,* +V 3100,4400,CONT_DIF_P,* +V 3100,600,CONT_DIF_N,* +V 3700,3300,CONT_DIF_P,* +V 3700,2700,CONT_DIF_P,* +V 3700,4400,CONT_DIF_P,* +V 3700,600,CONT_DIF_N,* +V 2500,4400,CONT_DIF_P,* +V 1300,4400,CONT_DIF_P,* +V 1900,4400,CONT_DIF_P,* +V 2500,600,CONT_DIF_N,* +V 2100,1700,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/an12_x4.vbe b/pdks/symbolic/lsxlib/cells/an12_x4.vbe new file mode 100644 index 000000000..0d030a6cb --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/an12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphl_i0_q : NATURAL := 461; + CONSTANT tplh_i0_q : NATURAL := 471; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x4; + +ARCHITECTURE behaviour_data_flow OF an12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x4" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1100 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/ao22_x2.ap b/pdks/symbolic/lsxlib/cells/ao22_x2.ap new file mode 100644 index 000000000..fe0be5c0f --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ao22_x2.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H ao22_x2,P, 5/ 8/2024,100 +A 0,0,3000,5000 +S 1700,1200,1800,1200,200,*,RIGHT,POLY2 +S 1800,2300,2000,2300,200,*,LEFT,POLY2 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 1500,1800,2400,1800,100,*,RIGHT,POLY +S 900,500,900,1200,300,*,DOWN,NDIF +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 2400,1600,2400,2400,100,*,UP,POLY +S 2100,500,2100,1400,300,*,DOWN,NDIF +S 400,3400,600,3400,100,*,RIGHT,POLY +S 400,1100,600,1100,100,*,RIGHT,POLY +S 400,1100,400,3400,100,*,UP,POLY +S 1400,1700,1400,4300,200,*,UP,ALU1 +S 900,1100,900,1700,200,*,DOWN,ALU1 +S 900,1700,1400,1700,200,*,LEFT,ALU1 +S 1700,1200,2000,1200,200,*,RIGHT,ALU1 +S 900,2300,900,4400,200,i1,DOWN,CALU1 +S 2000,1100,2000,3900,200,i2,DOWN,CALU1 +S 1200,2900,1200,3400,100,*,DOWN,POLY +S 1800,2300,1800,3400,100,*,DOWN,POLY +S 2700,600,2700,4400,200,q,DOWN,CALU1 +S 400,1100,400,3900,200,i0,DOWN,CALU1 +S 300,3600,300,4400,300,*,UP,PDIF +S 1200,3400,1200,4700,100,*,DOWN,PTRANS +S 600,3400,600,4700,100,*,DOWN,PTRANS +S 1800,3400,1800,4700,100,*,DOWN,PTRANS +S 900,3600,900,4500,300,*,UP,PDIF +S 1500,3600,1500,4500,300,*,UP,PDIF +S 1000,1400,1000,2900,100,*,DOWN,POLY +S 2700,2600,2700,4500,300,*,UP,PDIF +S 2100,2600,2100,4500,300,*,UP,PDIF +S 2400,2400,2400,4700,100,*,DOWN,PTRANS +S 1000,2900,1200,2900,100,*,RIGHT,POLY +S 1200,1100,1200,1400,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 300,600,1500,600,200,*,RIGHT,ALU1 +S 1800,300,1800,1100,100,*,UP,NTRANS +S 1200,300,1200,1100,100,*,UP,NTRANS +S 600,300,600,1100,100,*,UP,NTRANS +S 300,500,300,900,300,*,DOWN,NDIF +S 1500,500,1500,900,300,*,DOWN,NDIF +S 0,0,3000,0,400,vss,LEFT,CALU1 +S 2400,300,2400,1600,100,*,UP,NTRANS +S 2700,500,2700,1400,300,*,DOWN,NDIF +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +S 0,5000,3000,5000,300,*,RIGHT,NTIE +S 0,0,3000,0,300,*,RIGHT,PTIE +S 2100,0,2100,600,200,*,UP,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +B 1850,1800,1100,200,CONT_TURN8,* +V 1400,1800,CONT_POLY,* +B 1700,1200,200,200,CONT_TURN8,* +B 1400,1700,200,200,CONT_TURN1,* +B 900,1700,200,200,CONT_TURN1,* +B 1400,4300,200,200,CONT_TURN1,* +V 2000,2300,CONT_POLY,* +V 400,2300,CONT_POLY,* +V 900,2300,CONT_POLY,* +V 1700,1200,CONT_POLY,* +V 2700,600,CONT_DIF_N,* +V 2700,1300,CONT_DIF_N,* +V 2700,3800,CONT_DIF_P,* +V 2700,3200,CONT_DIF_P,* +V 2700,2700,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 1500,4300,CONT_DIF_P,* +V 1500,3800,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 900,1100,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/ao22_x2.vbe b/pdks/symbolic/lsxlib/cells/ao22_x2.vbe new file mode 100644 index 000000000..7cfca61f3 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ao22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 420; + CONSTANT tpll_i2_q : NATURAL := 425; + CONSTANT tpll_i0_q : NATURAL := 447; + CONSTANT tphh_i1_q : NATURAL := 493; + CONSTANT tpll_i1_q : NATURAL := 526; + CONSTANT tphh_i0_q : NATURAL := 558; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x2; + +ARCHITECTURE behaviour_data_flow OF ao22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/ao22_x4.ap b/pdks/symbolic/lsxlib/cells/ao22_x4.ap new file mode 100644 index 000000000..e553233c9 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ao22_x4.ap @@ -0,0 +1,127 @@ +V ALLIANCE : 6 +H ao22_x4,P, 5/ 8/2024,100 +A 0,0,4000,5000 +S 1800,1200,2000,1200,200,*,LEFT,POLY2 +S 1800,2300,2000,2300,200,*,LEFT,POLY2 +S 0,1100,4000,1100,1400,*,RIGHT,PWELL +S 2300,3600,2300,4500,300,*,DOWN,PDIF +S 2300,500,2300,900,300,*,UP,NDIF +S 2200,500,2200,900,300,*,DOWN,NDIF +S 1500,1800,3400,1800,100,*,RIGHT,POLY +S 0,4000,4000,4000,1200,*,RIGHT,NWELL +S 0,3100,4000,3100,1200,*,RIGHT,NWELL +S 2800,1600,2800,2400,100,*,UP,POLY +S 2000,600,2000,4400,200,i2,DOWN,CALU1 +S 2200,3600,2200,4500,300,*,DOWN,PDIF +S 2500,2600,2500,4500,300,*,UP,PDIF +S 2500,2700,2500,5000,200,*,UP,ALU1 +S 2500,2700,2500,5000,200,*,UP,ALU1 +S 3700,2600,3700,4500,300,*,UP,PDIF +S 3400,2400,3400,4700,100,*,DOWN,PTRANS +S 3700,2700,3700,5000,200,*,UP,ALU1 +S 2500,500,2500,1400,300,*,DOWN,NDIF +S 2500,0,2500,1300,200,*,DOWN,ALU1 +S 3400,2400,3400,4700,100,*,DOWN,PTRANS +S 3700,2600,3700,4500,300,*,UP,PDIF +S 2800,2400,2800,4700,100,*,DOWN,PTRANS +S 3100,2600,3100,4500,300,*,UP,PDIF +S 2800,300,2800,1600,100,*,UP,NTRANS +S 3400,300,3400,1600,100,*,UP,NTRANS +S 3700,500,3700,1400,300,*,DOWN,NDIF +S 3100,500,3100,1400,300,*,DOWN,NDIF +S 3400,1600,3400,2400,100,*,DOWN,POLY +S 3700,0,3700,1300,200,*,DOWN,ALU1 +S 3700,2700,3700,5000,200,*,UP,ALU1 +S 3100,600,3100,4400,200,q,DOWN,CALU1 +S 0,5000,4000,5000,300,*,RIGHT,NTIE +S 0,5000,4000,5000,400,vdd,RIGHT,CALU1 +S 0,0,4000,0,300,*,RIGHT,PTIE +S 0,0,4000,0,400,vss,LEFT,CALU1 +S 400,3400,600,3400,100,*,RIGHT,POLY +S 400,1100,600,1100,100,*,RIGHT,POLY +S 400,1100,400,3400,100,*,UP,POLY +S 1400,1700,1400,4300,200,*,UP,ALU1 +S 900,1100,900,1700,200,*,DOWN,ALU1 +S 900,1700,1400,1700,200,*,LEFT,ALU1 +S 900,2300,900,4400,200,i1,DOWN,CALU1 +S 1200,2900,1200,3400,100,*,DOWN,POLY +S 1800,2300,1800,3400,100,*,DOWN,POLY +S 400,1100,400,3900,200,i0,DOWN,CALU1 +S 300,3600,300,4400,300,*,UP,PDIF +S 1200,3400,1200,4700,100,*,DOWN,PTRANS +S 600,3400,600,4700,100,*,DOWN,PTRANS +S 1800,3400,1800,4700,100,*,DOWN,PTRANS +S 900,3600,900,4500,300,*,UP,PDIF +S 1500,3600,1500,4500,300,*,UP,PDIF +S 1000,1400,1000,2900,100,*,DOWN,POLY +S 1000,2900,1200,2900,100,*,RIGHT,POLY +S 1200,1100,1200,1400,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 900,500,900,1200,300,*,DOWN,NDIF +S 300,600,1500,600,200,*,RIGHT,ALU1 +S 1800,300,1800,1100,100,*,UP,NTRANS +S 1200,300,1200,1100,100,*,UP,NTRANS +S 600,300,600,1100,100,*,UP,NTRANS +S 300,500,300,900,300,*,DOWN,NDIF +S 1500,500,1500,900,300,*,DOWN,NDIF +S 300,4400,300,5000,200,*,UP,ALU1 +B 2350,1800,2100,200,CONT_TURN8,* +V 1400,1800,CONT_POLY,* +B 1400,1700,200,200,CONT_TURN1,* +B 900,1700,200,200,CONT_TURN1,* +B 1400,4300,200,200,CONT_TURN1,* +V 2000,1200,CONT_POLY,* +V 2500,2700,CONT_DIF_P,* +V 2500,3200,CONT_DIF_P,* +V 2500,3800,CONT_DIF_P,* +V 2500,3800,CONT_DIF_P,* +V 2500,3200,CONT_DIF_P,* +V 2500,2700,CONT_DIF_P,* +V 2500,4400,CONT_DIF_P,* +V 2500,4400,CONT_DIF_P,* +V 3700,3800,CONT_DIF_P,* +V 3700,3200,CONT_DIF_P,* +V 3700,2700,CONT_DIF_P,* +V 3700,4400,CONT_DIF_P,* +V 2500,600,CONT_DIF_N,* +V 2500,1300,CONT_DIF_N,* +V 3700,4400,CONT_DIF_P,* +V 3700,2700,CONT_DIF_P,* +V 3700,3200,CONT_DIF_P,* +V 3700,3800,CONT_DIF_P,* +V 3100,3800,CONT_DIF_P,* +V 3100,3200,CONT_DIF_P,* +V 3100,2700,CONT_DIF_P,* +V 3100,4400,CONT_DIF_P,* +V 3700,1300,CONT_DIF_N,* +V 3700,600,CONT_DIF_N,* +V 3100,600,CONT_DIF_N,* +V 3100,1300,CONT_DIF_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 2000,2300,CONT_POLY,* +V 400,2300,CONT_POLY,* +V 900,2300,CONT_POLY,* +V 1500,4300,CONT_DIF_P,* +V 1500,3800,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 900,1100,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/ao22_x4.vbe b/pdks/symbolic/lsxlib/cells/ao22_x4.vbe new file mode 100644 index 000000000..2995c9cca --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tpll_i2_q : NATURAL := 505; + CONSTANT tphh_i2_q : NATURAL := 526; + CONSTANT tpll_i0_q : NATURAL := 552; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 647; + CONSTANT tphh_i0_q : NATURAL := 674; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x4; + +ARCHITECTURE behaviour_data_flow OF ao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/ao2o22_x2.ap b/pdks/symbolic/lsxlib/cells/ao2o22_x2.ap new file mode 100644 index 000000000..f84233e9d --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ao2o22_x2.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H ao2o22_x2,P, 1/ 8/2024,100 +A 0,0,4500,5000 +S 0,1100,4500,1100,1400,*,RIGHT,PWELL +S 900,500,900,1200,300,*,UP,NDIF +S 0,4000,4500,4000,1200,*,RIGHT,NWELL +S 0,3100,4500,3100,1200,*,RIGHT,NWELL +S 600,1100,600,3400,100,*,DOWN,POLY +S 2400,1100,2400,3400,100,*,DOWN,POLY +S 1800,1100,1800,3400,100,*,DOWN,POLY +S 1200,1100,1200,3400,100,*,DOWN,POLY +S 3000,2200,3000,3900,200,*,DOWN,ALU1 +S 1500,3900,3000,3900,200,*,RIGHT,ALU1 +S 2000,1600,2000,3400,200,i2,DOWN,CALU1 +S 2500,1600,2500,3400,200,i3,DOWN,CALU1 +S 400,1100,400,3900,200,i0,DOWN,CALU1 +S 3500,0,3500,1300,200,*,DOWN,ALU1 +S 3500,2700,3500,5000,200,*,UP,ALU1 +S 3800,2400,3800,4700,100,*,UP,PTRANS +S 3500,2600,3500,4500,300,*,DOWN,PDIF +S 4100,2600,4100,4500,300,*,DOWN,PDIF +S 3800,300,3800,1600,100,*,DOWN,NTRANS +S 4100,500,4100,1400,300,*,UP,NDIF +S 3500,500,3500,1400,300,*,UP,NDIF +S 3600,2200,3800,2200,200,*,RIGHT,POLY +S 3800,1600,3800,2400,100,*,DOWN,POLY +S 4100,600,4100,4400,200,q,DOWN,CALU1 +S 1000,2100,1000,4400,200,i1,DOWN,CALU1 +S 1800,2200,2000,2200,200,*,RIGHT,POLY +S 1000,2200,1200,2200,200,*,RIGHT,POLY +S 3000,2200,3500,2200,200,*,RIGHT,ALU1 +S 900,1100,900,1600,200,*,DOWN,ALU1 +S 1500,1600,1500,4400,200,*,UP,ALU1 +S 900,1600,1500,1600,200,*,RIGHT,ALU1 +S 2700,600,2700,1100,200,*,UP,ALU1 +S 1500,600,1500,1100,200,*,DOWN,ALU1 +S 300,600,1500,600,200,*,RIGHT,ALU1 +S 2100,500,2100,900,300,*,UP,NDIF +S 1500,1100,2700,1100,200,*,LEFT,ALU1 +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 2400,300,2400,1100,100,*,DOWN,NTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 2700,500,2700,900,300,*,UP,NDIF +S 300,500,300,900,300,*,UP,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 300,3600,300,4500,300,*,DOWN,PDIF +S 2700,3600,2700,4500,300,*,DOWN,PDIF +S 2100,3600,2100,4500,300,*,DOWN,PDIF +S 900,3600,900,4500,300,*,DOWN,PDIF +S 600,3400,600,4700,100,*,UP,PTRANS +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 2400,3400,2400,4700,100,*,UP,PTRANS +S 1200,3400,1200,4700,100,*,UP,PTRANS +S 0,5000,4500,5000,400,vdd,RIGHT,CALU1 +S 0,0,4500,0,400,vss,RIGHT,CALU1 +S 0,5000,4500,5000,300,*,RIGHT,NTIE +S 0,0,4500,0,300,*,RIGHT,PTIE +S 2700,4400,2700,5000,200,*,UP,ALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +S 2100,0,2100,600,200,*,UP,ALU1 +B 2500,2200,200,200,CONT_TURN8,* +B 500,2200,200,200,CONT_TURN8,* +B 3650,2200,300,200,CONT_TURN8,* +B 1950,2200,300,200,CONT_TURN8,* +B 1050,2200,300,200,CONT_TURN8,* +B 2700,1100,200,200,CONT_TURN1,* +B 1500,1100,200,200,CONT_TURN1,* +B 1500,1600,200,200,CONT_TURN1,* +B 900,1600,200,200,CONT_TURN1,* +B 3000,2200,200,200,CONT_TURN1,* +B 3000,3900,200,200,CONT_TURN1,* +V 3500,1300,CONT_DIF_N,* +V 4100,1300,CONT_DIF_N,* +V 3500,3300,CONT_DIF_P,* +V 3500,2700,CONT_DIF_P,* +V 3500,3900,CONT_DIF_P,* +V 4100,2700,CONT_DIF_P,* +V 4100,3300,CONT_DIF_P,* +V 4100,4400,CONT_DIF_P,* +V 4100,3900,CONT_DIF_P,* +V 3500,4400,CONT_DIF_P,* +V 4100,600,CONT_DIF_N,* +V 3500,600,CONT_DIF_N,* +V 3600,2200,CONT_POLY,* +V 2000,2200,CONT_POLY,* +V 1000,2200,CONT_POLY,* +V 2500,2200,CONT_POLY,* +V 500,2200,CONT_POLY,* +V 2700,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 900,1100,CONT_DIF_N,* +V 1500,4400,CONT_DIF_P,* +V 1500,3700,CONT_DIF_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 2700,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2100,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/ao2o22_x2.vbe b/pdks/symbolic/lsxlib/cells/ao2o22_x2.vbe new file mode 100644 index 000000000..c503d1b97 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ao2o22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 432; + CONSTANT tpll_i0_q : NATURAL := 451; + CONSTANT tphh_i3_q : NATURAL := 488; + CONSTANT tphh_i1_q : NATURAL := 508; + CONSTANT tpll_i3_q : NATURAL := 526; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tphh_i0_q : NATURAL := 572; + CONSTANT tpll_i2_q : NATURAL := 627; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x2; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/ao2o22_x4.ap b/pdks/symbolic/lsxlib/cells/ao2o22_x4.ap new file mode 100644 index 000000000..5b4e34d65 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ao2o22_x4.ap @@ -0,0 +1,134 @@ +V ALLIANCE : 6 +H ao2o22_x4,P, 1/ 8/2024,100 +A 0,0,5000,5000 +S 0,1100,5000,1100,1400,*,RIGHT,PWELL +S 900,500,900,1200,300,*,UP,NDIF +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +S 0,0,5000,0,300,*,RIGHT,PTIE +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +S 3600,2200,4400,2200,200,*,RIGHT,POLY +S 4700,2600,4700,4500,300,*,DOWN,PDIF +S 3500,2700,3500,5000,200,*,UP,ALU1 +S 4700,2700,4700,5000,200,*,UP,ALU1 +S 4700,500,4700,1400,300,*,UP,NDIF +S 4700,0,4700,1300,200,*,DOWN,ALU1 +S 4400,2400,4400,4700,100,*,UP,PTRANS +S 4400,1600,4400,2400,100,*,DOWN,POLY +S 4400,300,4400,1600,100,*,DOWN,NTRANS +S 600,1100,600,3400,100,*,DOWN,POLY +S 2400,1100,2400,3400,100,*,DOWN,POLY +S 1800,1100,1800,3400,100,*,DOWN,POLY +S 1200,1100,1200,3400,100,*,DOWN,POLY +S 3000,2200,3000,3900,200,*,DOWN,ALU1 +S 1500,3900,3000,3900,200,*,RIGHT,ALU1 +S 2000,1600,2000,3400,200,i2,DOWN,CALU1 +S 2500,1600,2500,3400,200,i3,DOWN,CALU1 +S 400,1100,400,3900,200,i0,DOWN,CALU1 +S 3500,0,3500,1300,200,*,DOWN,ALU1 +S 3800,2400,3800,4700,100,*,UP,PTRANS +S 3500,2600,3500,4500,300,*,DOWN,PDIF +S 4100,2600,4100,4500,300,*,DOWN,PDIF +S 3800,300,3800,1600,100,*,DOWN,NTRANS +S 4100,500,4100,1400,300,*,UP,NDIF +S 3500,500,3500,1400,300,*,UP,NDIF +S 3800,1600,3800,2400,100,*,DOWN,POLY +S 4100,600,4100,4400,200,q,DOWN,CALU1 +S 1000,2100,1000,4400,200,i1,DOWN,CALU1 +S 1800,2200,2000,2200,200,*,RIGHT,POLY +S 1000,2200,1200,2200,200,*,RIGHT,POLY +S 3000,2200,3500,2200,200,*,RIGHT,ALU1 +S 900,1100,900,1600,200,*,DOWN,ALU1 +S 1500,1600,1500,4400,200,*,UP,ALU1 +S 900,1600,1500,1600,200,*,RIGHT,ALU1 +S 2700,600,2700,1100,200,*,UP,ALU1 +S 1500,600,1500,1100,200,*,DOWN,ALU1 +S 300,600,1500,600,200,*,RIGHT,ALU1 +S 2100,500,2100,900,300,*,UP,NDIF +S 1500,1100,2700,1100,200,*,LEFT,ALU1 +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 2400,300,2400,1100,100,*,DOWN,NTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 2700,500,2700,900,300,*,UP,NDIF +S 300,500,300,900,300,*,UP,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 300,3600,300,4500,300,*,DOWN,PDIF +S 2700,3600,2700,4500,300,*,DOWN,PDIF +S 2100,3600,2100,4500,300,*,DOWN,PDIF +S 900,3600,900,4500,300,*,DOWN,PDIF +S 600,3400,600,4700,100,*,UP,PTRANS +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 2400,3400,2400,4700,100,*,UP,PTRANS +S 1200,3400,1200,4700,100,*,UP,PTRANS +S 2700,4400,2700,5000,200,*,UP,ALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +S 2100,0,2100,600,200,*,UP,ALU1 +B 2500,2200,200,200,CONT_TURN8,* +B 500,2200,200,200,CONT_TURN8,* +B 3950,2200,900,200,CONT_TURN8,* +B 1950,2200,300,200,CONT_TURN8,* +B 1050,2200,300,200,CONT_TURN8,* +B 900,1600,200,200,CONT_TURN1,* +B 2700,1100,200,200,CONT_TURN1,* +B 1500,1100,200,200,CONT_TURN1,* +B 3000,3900,200,200,CONT_TURN1,* +B 3000,2200,200,200,CONT_TURN1,* +V 5000,5000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 3500,3900,CONT_DIF_P,* +V 3500,2700,CONT_DIF_P,* +V 3500,3300,CONT_DIF_P,* +V 3500,4400,CONT_DIF_P,* +V 4700,4400,CONT_DIF_P,* +V 4700,3300,CONT_DIF_P,* +V 4700,2700,CONT_DIF_P,* +V 4700,3900,CONT_DIF_P,* +V 4700,1300,CONT_DIF_N,* +V 4700,600,CONT_DIF_N,* +V 3500,1300,CONT_DIF_N,* +V 4100,1300,CONT_DIF_N,* +V 4100,2700,CONT_DIF_P,* +V 4100,3300,CONT_DIF_P,* +V 4100,4400,CONT_DIF_P,* +V 4100,3900,CONT_DIF_P,* +V 4100,600,CONT_DIF_N,* +V 3500,600,CONT_DIF_N,* +V 3600,2200,CONT_POLY,* +V 2000,2200,CONT_POLY,* +V 1000,2200,CONT_POLY,* +V 2500,2200,CONT_POLY,* +V 500,2200,CONT_POLY,* +V 2700,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 900,1100,CONT_DIF_N,* +V 1500,4400,CONT_DIF_P,* +V 1500,3700,CONT_DIF_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 2700,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2100,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/ao2o22_x4.vbe b/pdks/symbolic/lsxlib/cells/ao2o22_x4.vbe new file mode 100644 index 000000000..61a5bff61 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 554; + CONSTANT tpll_i0_q : NATURAL := 569; + CONSTANT tphh_i3_q : NATURAL := 606; + CONSTANT tphh_i1_q : NATURAL := 637; + CONSTANT tpll_i3_q : NATURAL := 639; + CONSTANT tpll_i1_q : NATURAL := 666; + CONSTANT tphh_i0_q : NATURAL := 696; + CONSTANT tpll_i2_q : NATURAL := 744; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/buf_x2.ap b/pdks/symbolic/lsxlib/cells/buf_x2.ap new file mode 100644 index 000000000..cc61d4c83 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/buf_x2.ap @@ -0,0 +1,63 @@ +V ALLIANCE : 6 +H buf_x2,P, 1/ 8/2024,100 +A 0,0,2000,5000 +S 0,1100,2000,1100,1400,*,RIGHT,PWELL +S 400,2200,700,2200,100,*,RIGHT,POLY +S 700,1000,700,3600,100,*,DOWN,POLY +S 400,3800,400,4500,300,*,DOWN,PDIF +S 700,3600,700,4700,100,*,UP,PTRANS +S 400,500,400,800,300,*,DOWN,NDIF +S 700,300,700,1000,100,*,DOWN,NTRANS +S 0,4000,2000,4000,1200,*,RIGHT,NWELL +S 0,3100,2000,3100,1200,*,RIGHT,NWELL +S 1300,1600,1300,2400,100,*,DOWN,POLY +S 1300,2400,1300,4700,100,*,UP,PTRANS +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 1300,300,1300,1600,100,*,DOWN,NTRANS +S 400,500,400,700,300,*,UP,NDIF +S 1600,500,1600,1400,300,*,UP,NDIF +S 1000,500,1000,1400,300,*,UP,NDIF +S 1100,2200,1300,2200,200,*,RIGHT,POLY +S 1000,0,1000,600,200,*,UP,ALU1 +S 1600,600,1600,4400,200,q,DOWN,CALU1 +S 400,3900,400,4400,200,*,UP,ALU1 +S 400,1600,400,3400,200,i,DOWN,CALU1 +S 1100,1100,1100,3900,200,*,UP,ALU1 +S 400,1100,1100,1100,200,*,RIGHT,ALU1 +S 400,3900,1100,3900,200,*,LEFT,ALU1 +S 400,600,400,1100,200,*,UP,ALU1 +S 1000,4400,1000,5000,200,*,UP,ALU1 +S 0,5000,2000,5000,400,vdd,RIGHT,CALU1 +S 0,0,2000,0,400,vss,RIGHT,CALU1 +S 0,5000,2000,5000,300,*,RIGHT,NTIE +S 0,0,2000,0,300,*,RIGHT,PTIE +B 1150,2200,300,200,CONT_TURN8,* +B 500,2200,400,200,CONT_TURN8,* +B 400,1100,200,200,CONT_TURN1,* +B 1100,1100,200,200,CONT_TURN1,* +B 1100,3900,200,200,CONT_TURN1,* +B 400,3900,200,200,CONT_TURN1,* +V 1600,4400,CONT_DIF_P,* +V 1600,2700,CONT_DIF_P,* +V 1600,3300,CONT_DIF_P,* +V 1600,3800,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 1600,1300,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 1000,600,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 400,2200,CONT_POLY,* +V 1100,2200,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/buf_x2.vbe b/pdks/symbolic/lsxlib/cells/buf_x2.vbe new file mode 100644 index 000000000..e2e4c344e --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/buf_x2.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 6; + CONSTANT rdown_i_q : NATURAL := 1620; + CONSTANT rup_i_q : NATURAL := 1790; + CONSTANT tpll_i_q : NATURAL := 391; + CONSTANT tphh_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x2; + +ARCHITECTURE behaviour_data_flow OF buf_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x2" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/buf_x4.ap b/pdks/symbolic/lsxlib/cells/buf_x4.ap new file mode 100644 index 000000000..ea43c97a4 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/buf_x4.ap @@ -0,0 +1,77 @@ +V ALLIANCE : 6 +H buf_x4,P,31/ 7/2024,100 +A 0,0,2500,5000 +S 0,1100,2500,1100,1400,*,RIGHT,PWELL +S 1100,2200,1900,2200,100,*,RIGHT,POLY +S 400,2200,700,2200,100,*,RIGHT,POLY +S 0,4000,2500,4000,1200,*,RIGHT,NWELL +S 0,3100,2500,3100,1200,*,RIGHT,NWELL +S 1900,1600,1900,2400,100,*,DOWN,POLY +S 1300,1600,1300,2400,100,*,DOWN,POLY +S 2200,2700,2200,5000,200,*,UP,ALU1 +S 2200,0,2200,1300,200,*,DOWN,ALU1 +S 0,0,2500,0,300,*,RIGHT,PTIE +S 0,0,2500,0,400,vss,RIGHT,CALU1 +S 0,5000,2500,5000,300,*,RIGHT,NTIE +S 0,5000,2500,5000,400,vdd,RIGHT,CALU1 +S 2200,2600,2200,4500,300,*,DOWN,PDIF +S 1900,300,1900,1600,100,*,DOWN,NTRANS +S 2200,500,2200,1400,300,*,UP,NDIF +S 1900,2400,1900,4700,100,*,UP,PTRANS +S 400,3600,400,4500,300,*,DOWN,PDIF +S 700,1100,700,3400,100,*,DOWN,POLY +S 700,3400,700,4700,100,*,UP,PTRANS +S 400,500,400,900,300,*,UP,NDIF +S 700,300,700,1100,100,*,DOWN,NTRANS +S 1300,2400,1300,4700,100,*,UP,PTRANS +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 1300,300,1300,1600,100,*,DOWN,NTRANS +S 1600,500,1600,1400,300,*,UP,NDIF +S 1000,500,1000,1400,300,*,UP,NDIF +S 1000,0,1000,600,200,*,UP,ALU1 +S 1600,600,1600,4400,200,q,DOWN,CALU1 +S 400,3900,400,4400,200,*,UP,ALU1 +S 400,1600,400,3400,200,i,DOWN,CALU1 +S 1100,1100,1100,3900,200,*,UP,ALU1 +S 400,1100,1100,1100,200,*,RIGHT,ALU1 +S 400,3900,1100,3900,200,*,LEFT,ALU1 +S 400,600,400,1100,200,*,UP,ALU1 +S 1000,4400,1000,5000,200,*,UP,ALU1 +B 1450,2200,900,200,CONT_TURN8,* +B 500,2200,400,200,CONT_TURN8,* +B 1100,1100,200,200,CONT_TURN1,* +B 400,1100,200,200,CONT_TURN1,* +B 1100,3900,200,200,CONT_TURN1,* +V 2500,5000,CONT_BODY_N,* +V 2500,0,CONT_BODY_P,* +V 2200,2700,CONT_DIF_P,* +V 2200,3300,CONT_DIF_P,* +V 2200,3800,CONT_DIF_P,* +V 2200,4400,CONT_DIF_P,* +V 2200,600,CONT_DIF_N,* +V 2200,1300,CONT_DIF_N,* +V 400,3900,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 1600,2700,CONT_DIF_P,* +V 1600,3300,CONT_DIF_P,* +V 1600,3800,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 1600,1300,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 1000,600,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 400,2200,CONT_POLY,* +V 1100,2200,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/buf_x4.vbe b/pdks/symbolic/lsxlib/cells/buf_x4.vbe new file mode 100644 index 000000000..0b7726ef9 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/buf_x4.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i : NATURAL := 9; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphh_i_q : NATURAL := 379; + CONSTANT tpll_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x4; + +ARCHITECTURE behaviour_data_flow OF buf_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x4" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/buf_x8.ap b/pdks/symbolic/lsxlib/cells/buf_x8.ap new file mode 100644 index 000000000..93dceb5f4 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/buf_x8.ap @@ -0,0 +1,111 @@ +V ALLIANCE : 6 +H buf_x8,P,31/ 7/2024,100 +A 0,0,4000,5000 +S 0,1100,4000,1100,1400,*,RIGHT,PWELL +S 1200,2200,3200,2200,100,*,RIGHT,POLY +S 500,2200,800,2200,100,*,RIGHT,POLY +S 0,4000,4000,4000,1200,*,RIGHT,NWELL +S 0,3100,4000,3100,1200,*,RIGHT,NWELL +S 3200,1600,3200,2400,100,*,DOWN,POLY +S 2600,1600,2600,2400,100,*,DOWN,POLY +S 2000,1600,2000,2400,100,*,DOWN,POLY +S 1400,1600,1400,2400,100,*,DOWN,POLY +S 500,1600,500,2900,200,i,DOWN,CALU1 +S 500,2600,500,4500,300,*,DOWN,PDIF +S 800,2400,800,4700,100,*,UP,PTRANS +S 3200,2400,3200,4700,100,*,UP,PTRANS +S 2600,2400,2600,4700,100,*,UP,PTRANS +S 3500,2600,3500,4500,300,*,DOWN,PDIF +S 2300,2600,2300,4500,300,*,DOWN,PDIF +S 2000,2400,2000,4700,100,*,UP,PTRANS +S 2900,2600,2900,4500,300,*,DOWN,PDIF +S 1100,2600,1100,4500,300,*,DOWN,PDIF +S 1700,2600,1700,4500,300,*,DOWN,PDIF +S 1400,2400,1400,4700,100,*,UP,PTRANS +S 800,300,800,1600,100,*,DOWN,NTRANS +S 3200,300,3200,1600,100,*,DOWN,NTRANS +S 2600,300,2600,1600,100,*,DOWN,NTRANS +S 2000,300,2000,1600,100,*,DOWN,NTRANS +S 1400,300,1400,1600,100,*,DOWN,NTRANS +S 2900,500,2900,1400,300,*,UP,NDIF +S 3500,500,3500,1400,300,*,UP,NDIF +S 500,500,500,1400,300,*,UP,NDIF +S 1100,500,1100,1400,300,*,UP,NDIF +S 1700,500,1700,1400,300,*,UP,NDIF +S 2300,500,2300,1400,300,*,UP,NDIF +S 800,1600,800,2400,100,*,DOWN,POLY +S 1100,0,1100,600,200,*,UP,ALU1 +S 2300,0,2300,1300,200,*,DOWN,ALU1 +S 3500,0,3500,1300,200,*,DOWN,ALU1 +S 500,3400,1200,3400,200,*,LEFT,ALU1 +S 500,3400,500,4400,200,*,UP,ALU1 +S 1200,1100,1200,3400,200,*,UP,ALU1 +S 1100,3900,1100,5000,200,*,UP,ALU1 +S 2300,2700,2300,5000,200,*,UP,ALU1 +S 2900,600,2900,4400,200,q,DOWN,CALU1 +S 1700,2200,2900,2200,200,*,RIGHT,ALU1 +S 1700,600,1700,4400,200,*,DOWN,ALU1 +S 3500,2700,3500,5000,200,*,UP,ALU1 +S 500,600,500,1100,200,*,UP,ALU1 +S 500,1100,1200,1100,200,*,RIGHT,ALU1 +S 0,0,4000,0,300,*,RIGHT,PTIE +S 0,0,4000,0,400,vss,RIGHT,CALU1 +S 0,5000,4000,5000,300,*,RIGHT,NTIE +S 0,5000,4000,5000,400,vdd,RIGHT,CALU1 +B 2150,2200,2100,200,CONT_TURN8,* +B 600,2200,400,200,CONT_TURN8,* +B 1200,1100,200,200,CONT_TURN1,* +B 1200,3400,200,200,CONT_TURN1,* +V 500,2200,CONT_POLY,* +V 500,3400,CONT_DIF_P,* +V 1100,3900,CONT_DIF_P,* +V 3500,3300,CONT_DIF_P,* +V 3500,3800,CONT_DIF_P,* +V 2900,3800,CONT_DIF_P,* +V 2900,3300,CONT_DIF_P,* +V 2900,2700,CONT_DIF_P,* +V 3500,4400,CONT_DIF_P,* +V 2900,4400,CONT_DIF_P,* +V 1700,3300,CONT_DIF_P,* +V 1700,2700,CONT_DIF_P,* +V 2300,4400,CONT_DIF_P,* +V 500,3900,CONT_DIF_P,* +V 3500,2700,CONT_DIF_P,* +V 2300,3300,CONT_DIF_P,* +V 2300,3800,CONT_DIF_P,* +V 500,4400,CONT_DIF_P,* +V 1100,4400,CONT_DIF_P,* +V 1700,3800,CONT_DIF_P,* +V 1700,4400,CONT_DIF_P,* +V 2300,2700,CONT_DIF_P,* +V 2900,1300,CONT_DIF_N,* +V 500,1100,CONT_DIF_N,* +V 1100,600,CONT_DIF_N,* +V 1700,600,CONT_DIF_N,* +V 3500,600,CONT_DIF_N,* +V 3500,1300,CONT_DIF_N,* +V 2900,600,CONT_DIF_N,* +V 1700,1300,CONT_DIF_N,* +V 2300,600,CONT_DIF_N,* +V 2300,1300,CONT_DIF_N,* +V 500,600,CONT_DIF_N,* +V 1200,2200,CONT_POLY,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 2500,5000,CONT_BODY_N,* +V 2500,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/buf_x8.vbe b/pdks/symbolic/lsxlib/cells/buf_x8.vbe new file mode 100644 index 000000000..3b2ecc3bb --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/buf_x8.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i : NATURAL := 15; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphh_i_q : NATURAL := 343; + CONSTANT tpll_i_q : NATURAL := 396; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x8; + +ARCHITECTURE behaviour_data_flow OF buf_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x8" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/inv_x1.ap b/pdks/symbolic/lsxlib/cells/inv_x1.ap new file mode 100644 index 000000000..17b1f0315 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/inv_x1.ap @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H inv_x1,P, 1/ 8/2024,100 +A 0,0,1500,5000 +S 0,1100,1500,1100,1400,*,RIGHT,PWELL +S 0,4000,1500,4000,1200,*,RIGHT,NWELL +S 0,3100,1500,3100,1200,*,RIGHT,NWELL +S 500,2000,700,2000,200,*,RIGHT,POLY +S 500,1100,500,3900,200,i,DOWN,CALU1 +S 400,500,400,900,300,*,DOWN,NDIF +S 400,3600,400,4400,300,*,DOWN,PDIF +S 700,1100,700,3400,100,*,UP,POLY +S 1000,600,1000,4400,200,nq,DOWN,CALU1 +S 1000,3600,1000,4500,300,*,DOWN,PDIF +S 700,3400,700,4700,100,*,UP,PTRANS +S 700,300,700,1100,100,*,DOWN,NTRANS +S 1000,500,1000,900,300,*,UP,NDIF +S 0,0,1500,0,400,vss,RIGHT,CALU1 +S 0,5000,1500,5000,400,vdd,RIGHT,CALU1 +S 0,5000,1500,5000,300,*,RIGHT,NTIE +S 0,0,1500,0,300,*,RIGHT,PTIE +S 400,4400,400,5000,200,*,UP,ALU1 +S 400,0,400,600,200,*,UP,ALU1 +B 550,2000,300,200,CONT_TURN8,* +V 1000,3700,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 1000,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 400,4400,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/inv_x1.gds b/pdks/symbolic/lsxlib/cells/inv_x1.gds new file mode 100644 index 000000000..267be79a7 Binary files /dev/null and b/pdks/symbolic/lsxlib/cells/inv_x1.gds differ diff --git a/pdks/symbolic/lsxlib/cells/inv_x1.vbe b/pdks/symbolic/lsxlib/cells/inv_x1.vbe new file mode 100644 index 000000000..67e85e029 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/inv_x1.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_i_nq : NATURAL := 3640; + CONSTANT rup_i_nq : NATURAL := 3720; + CONSTANT tphl_i_nq : NATURAL := 101; + CONSTANT tplh_i_nq : NATURAL := 139; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x1; + +ARCHITECTURE behaviour_data_flow OF inv_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x1" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/inv_x2.ap b/pdks/symbolic/lsxlib/cells/inv_x2.ap new file mode 100644 index 000000000..2100e7d47 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/inv_x2.ap @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H inv_x2,P, 1/ 8/2024,100 +A 0,0,1500,5000 +S 0,1100,1500,1100,1400,*,RIGHT,PWELL +S 400,3900,400,5000,200,*,UP,ALU1 +S 500,1100,500,3400,200,i,DOWN,CALU1 +S 400,2600,400,4400,300,*,DOWN,PDIF +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 700,2400,700,4700,100,*,UP,PTRANS +S 700,1600,700,2400,100,*,UP,POLY +S 1000,500,1000,1400,300,*,UP,NDIF +S 400,500,400,1400,300,*,DOWN,NDIF +S 700,300,700,1600,100,*,DOWN,NTRANS +S 500,2000,700,2000,200,*,RIGHT,POLY +S 1000,600,1000,4400,200,nq,DOWN,CALU1 +S 0,0,1500,0,400,vss,RIGHT,CALU1 +S 0,5000,1500,5000,400,vdd,RIGHT,CALU1 +S 0,4000,1500,4000,1200,*,RIGHT,NWELL +S 0,3100,1500,3100,1200,*,RIGHT,NWELL +S 0,5000,1500,5000,300,*,RIGHT,NTIE +S 0,0,1500,0,300,*,RIGHT,PTIE +S 400,0,400,600,200,*,UP,ALU1 +B 550,2000,300,200,CONT_TURN8,* +V 1000,3300,CONT_DIF_P,* +V 1000,3900,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 1000,2700,CONT_DIF_P,* +V 1000,1300,CONT_DIF_N,* +V 1000,4400,CONT_DIF_P,* +V 1000,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 400,4400,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/inv_x2.vbe b/pdks/symbolic/lsxlib/cells/inv_x2.vbe new file mode 100644 index 000000000..9df0116d3 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/inv_x2.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 12; + CONSTANT rdown_i_nq : NATURAL := 1620; + CONSTANT rup_i_nq : NATURAL := 2420; + CONSTANT tphl_i_nq : NATURAL := 69; + CONSTANT tplh_i_nq : NATURAL := 163; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x2; + +ARCHITECTURE behaviour_data_flow OF inv_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x2" + SEVERITY WARNING; + nq <= not (i) after 800 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/inv_x4.ap b/pdks/symbolic/lsxlib/cells/inv_x4.ap new file mode 100644 index 000000000..f5526f25a --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/inv_x4.ap @@ -0,0 +1,57 @@ +V ALLIANCE : 6 +H inv_x4,P, 1/ 8/2024,100 +A 0,0,2000,5000 +S 0,1100,2000,1100,1400,*,RIGHT,PWELL +S 1600,2700,1600,5000,200,*,UP,ALU1 +S 1600,0,1600,1300,200,*,DOWN,ALU1 +S 500,2000,1300,2000,200,*,RIGHT,POLY +S 0,0,2000,0,300,*,RIGHT,PTIE +S 0,0,2000,0,400,vss,RIGHT,CALU1 +S 0,4000,2000,4000,1200,*,RIGHT,NWELL +S 0,3100,2000,3100,1200,*,RIGHT,NWELL +S 0,5000,2000,5000,300,*,RIGHT,NTIE +S 0,5000,2000,5000,400,vdd,RIGHT,CALU1 +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 1300,2400,1300,4700,100,*,UP,PTRANS +S 1300,300,1300,1600,100,*,DOWN,NTRANS +S 1600,500,1600,1400,300,*,UP,NDIF +S 1300,1600,1300,2400,100,*,UP,POLY +S 400,3900,400,5000,200,*,UP,ALU1 +S 500,1100,500,3400,200,i,DOWN,CALU1 +S 400,2600,400,4400,300,*,DOWN,PDIF +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 700,2400,700,4700,100,*,UP,PTRANS +S 700,1600,700,2400,100,*,UP,POLY +S 1000,500,1000,1400,300,*,UP,NDIF +S 400,500,400,1400,300,*,DOWN,NDIF +S 700,300,700,1600,100,*,DOWN,NTRANS +S 1000,600,1000,4400,200,nq,DOWN,CALU1 +S 400,0,400,600,200,*,UP,ALU1 +B 850,2000,900,200,CONT_TURN8,* +V 2000,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1600,3900,CONT_DIF_P,* +V 1600,3300,CONT_DIF_P,* +V 1600,2700,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 1600,600,CONT_DIF_N,* +V 1600,1300,CONT_DIF_N,* +V 1000,3300,CONT_DIF_P,* +V 1000,3900,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 1000,2700,CONT_DIF_P,* +V 1000,1300,CONT_DIF_N,* +V 1000,4400,CONT_DIF_P,* +V 1000,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 400,4400,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/inv_x4.vbe b/pdks/symbolic/lsxlib/cells/inv_x4.vbe new file mode 100644 index 000000000..3091ae3f7 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/inv_x4.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 26; + CONSTANT rdown_i_nq : NATURAL := 810; + CONSTANT rup_i_nq : NATURAL := 1060; + CONSTANT tphl_i_nq : NATURAL := 71; + CONSTANT tplh_i_nq : NATURAL := 143; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x4; + +ARCHITECTURE behaviour_data_flow OF inv_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x4" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/inv_x8.ap b/pdks/symbolic/lsxlib/cells/inv_x8.ap new file mode 100644 index 000000000..4f64c73da --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/inv_x8.ap @@ -0,0 +1,87 @@ +V ALLIANCE : 6 +H inv_x8,P, 1/ 8/2024,100 +A 0,0,3000,5000 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 0,5000,3000,5000,300,*,RIGHT,NTIE +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +S 0,0,3000,0,300,*,RIGHT,PTIE +S 0,0,3000,0,400,vss,RIGHT,CALU1 +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 2400,2400,2400,4700,100,*,UP,PTRANS +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 300,2600,300,4400,300,*,DOWN,PDIF +S 900,2600,900,4500,300,*,DOWN,PDIF +S 600,2400,600,4700,100,*,UP,PTRANS +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 600,300,600,1600,100,*,DOWN,NTRANS +S 2400,300,2400,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 2700,500,2700,1400,300,*,UP,NDIF +S 2100,500,2100,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +S 900,500,900,1400,300,*,UP,NDIF +S 300,500,300,1400,300,*,DOWN,NDIF +S 2400,1600,2400,2400,100,*,UP,POLY +S 1800,1600,1800,2400,100,*,UP,POLY +S 400,2000,2400,2000,200,*,RIGHT,POLY +S 1200,1600,1200,2400,100,*,UP,POLY +S 600,1600,600,2400,100,*,UP,POLY +S 2700,0,2700,1300,200,*,DOWN,ALU1 +S 1500,0,1500,1300,200,*,DOWN,ALU1 +S 300,0,300,600,200,*,UP,ALU1 +S 900,2000,2100,2000,200,*,RIGHT,ALU1 +S 900,600,900,4400,200,*,DOWN,ALU1 +S 2700,2700,2700,5000,200,*,UP,ALU1 +S 2100,600,2100,4400,200,nq,DOWN,CALU1 +S 1500,2700,1500,5000,200,*,UP,ALU1 +S 300,3900,300,5000,200,*,UP,ALU1 +S 400,1100,400,3400,200,i,DOWN,CALU1 +B 1350,2000,2100,200,CONT_TURN8,* +V 2500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2700,2700,CONT_DIF_P,* +V 2100,3300,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 2100,2700,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 2700,3300,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 1500,3300,CONT_DIF_P,* +V 1500,2700,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 900,3300,CONT_DIF_P,* +V 900,3900,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 900,2700,CONT_DIF_P,* +V 2700,600,CONT_DIF_N,* +V 2700,1300,CONT_DIF_N,* +V 2100,1300,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 1500,1300,CONT_DIF_N,* +V 900,1300,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 400,2000,CONT_POLY,* +V 2000,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/inv_x8.vbe b/pdks/symbolic/lsxlib/cells/inv_x8.vbe new file mode 100644 index 000000000..4e6fa0639 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/inv_x8.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i : NATURAL := 54; + CONSTANT rdown_i_nq : NATURAL := 400; + CONSTANT rup_i_nq : NATURAL := 450; + CONSTANT tphl_i_nq : NATURAL := 86; + CONSTANT tplh_i_nq : NATURAL := 133; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x8; + +ARCHITECTURE behaviour_data_flow OF inv_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x8" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/invbuf_x3.ap b/pdks/symbolic/lsxlib/cells/invbuf_x3.ap new file mode 100644 index 000000000..683e5dc03 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/invbuf_x3.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H invbuf_x3,P,31/ 7/2024,100 +A 0,0,3000,5000 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 1800,2500,2600,2500,100,*,RIGHT,POLY +S 600,2500,1400,2500,100,*,RIGHT,POLY +S 2700,0,2700,1000,200,*,DOWN,ALU1 +S 2700,3400,2700,5000,200,*,UP,ALU1 +S 2600,1500,2600,2900,200,i,UP,CALU1 +S 1500,0,1500,1000,200,*,DOWN,ALU1 +S 300,0,300,1000,200,*,DOWN,ALU1 +S 2400,300,2400,1300,100,*,DOWN,NTRANS +S 600,300,600,1300,100,*,DOWN,NTRANS +S 1200,300,1200,1300,100,*,DOWN,NTRANS +S 1800,300,1800,1300,100,*,DOWN,NTRANS +S 1500,500,1500,1100,300,*,UP,NDIF +S 900,500,900,1100,300,*,UP,NDIF +S 2100,500,2100,1100,300,*,UP,NDIF +S 2700,500,2700,1100,300,*,UP,NDIF +S 300,500,300,1100,300,*,UP,NDIF +S 1200,1300,1200,3000,100,*,DOWN,POLY +S 1800,1300,1800,3000,100,*,DOWN,POLY +S 600,1300,600,3000,100,*,DOWN,POLY +S 2400,1300,2400,3000,100,*,DOWN,POLY +S 1800,3000,1800,4700,100,*,UP,PTRANS +S 1200,3000,1200,4700,100,*,UP,PTRANS +S 600,3000,600,4700,100,*,UP,PTRANS +S 2400,3000,2400,4700,100,*,UP,PTRANS +S 2100,3200,2100,4500,300,*,DOWN,PDIF +S 900,3200,900,4500,300,*,DOWN,PDIF +S 1500,3200,1500,4500,300,*,DOWN,PDIF +S 300,3200,300,4500,300,*,DOWN,PDIF +S 2700,3200,2700,4500,300,*,DOWN,PDIF +S 1500,3400,1500,5000,200,*,DOWN,ALU1 +S 300,3400,300,5000,200,*,DOWN,ALU1 +S 1600,1600,2100,1600,200,*,RIGHT,ALU1 +S 1600,1600,1600,1600,200,c0,LEFT,CALU1 +S 1100,1600,1100,1600,200,c1,LEFT,CALU1 +S 900,1600,1100,1600,200,*,RIGHT,ALU1 +S 1400,2500,2100,2500,200,*,RIGHT,ALU1 +S 2100,600,2100,4400,200,*,DOWN,ALU1 +S 900,600,900,4400,200,*,DOWN,ALU1 +S 0,5000,3000,5000,300,*,RIGHT,NTIE +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +S 0,0,3000,0,300,*,RIGHT,PTIE +S 0,0,3000,0,400,vss,RIGHT,CALU1 +B 2250,2500,900,200,CONT_TURN8,* +B 1050,2500,900,200,CONT_TURN8,* +V 2700,1000,CONT_DIF_N,* +V 2700,3400,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 900,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2100,3400,CONT_DIF_P,* +V 1500,3400,CONT_DIF_P,* +V 900,3400,CONT_DIF_P,* +V 300,3400,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 900,3900,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 1400,2500,CONT_POLY,* +V 2600,2500,CONT_POLY,* +V 2100,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 2700,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1500,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 500,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/invbuf_x3.vbe b/pdks/symbolic/lsxlib/cells/invbuf_x3.vbe new file mode 100644 index 000000000..64ebb495c --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/invbuf_x3.vbe @@ -0,0 +1,18 @@ +ENTITY invbuf_x3 IS +PORT( + i : IN BIT; + c0 : INOUT BIT; + c1 : OUT BIT; + vdd : IN BIT; + vss : IN BIT +); +END invbuf_x3; + +ARCHITECTURE VBE OF invbuf_x3 IS + +BEGIN + + c0 <= NOT(i); + c1 <= NOT(c0); + +END VBE; diff --git a/pdks/symbolic/lsxlib/cells/mx2_x2.ap b/pdks/symbolic/lsxlib/cells/mx2_x2.ap new file mode 100644 index 000000000..1ff653ddf --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/mx2_x2.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H mx2_x2,P, 5/ 8/2024,100 +A 0,0,4000,5000 +S 900,3300,1200,3300,100,*,LEFT,POLY +S 1200,3300,1200,3400,100,*,DOWN,POLY +S 900,3100,900,3300,200,*,UP,POLY2 +S 1500,1600,1700,1600,200,*,LEFT,POLY2 +S 2600,1600,2800,1600,200,*,RIGHT,POLY2 +S 2300,3300,2400,3300,200,*,LEFT,POLY2 +S 2600,2800,2800,2800,200,*,RIGHT,POLY2 +S 900,1600,1000,1600,200,*,LEFT,POLY2 +S 0,1100,4000,1100,1400,*,RIGHT,PWELL +S 2000,2400,2600,2400,100,*,RIGHT,POLY +S 1700,2800,1700,3400,100,*,UP,POLY +S 1400,2100,1400,2800,100,*,DOWN,POLY +S 1400,2800,1700,2800,100,*,RIGHT,POLY +S 300,1100,1500,1100,200,*,RIGHT,ALU1 +S 1500,1100,1500,1600,200,*,DOWN,ALU1 +S 1900,2400,2100,2400,200,*,LEFT,ALU1 +S 2000,600,2100,600,200,*,LEFT,ALU1 +S 2100,600,2100,2400,200,*,UP,ALU1 +S 1900,2400,1900,3900,200,*,DOWN,ALU1 +S 2600,2100,3400,2100,100,*,LEFT,POLY +S 2600,2100,2600,2400,100,*,UP,POLY +S 2600,600,2600,2800,200,i1,DOWN,CALU1 +S 1900,3900,2000,3900,200,*,RIGHT,ALU1 +S 1400,2100,1400,3400,200,cmd,DOWN,CALU1 +S 500,2000,2100,2000,100,*,LEFT,POLY +S 500,1000,600,1000,100,*,RIGHT,POLY +S 500,1000,500,3600,100,*,DOWN,POLY +S 500,3600,600,3600,100,*,LEFT,POLY +S 900,1600,900,3400,200,i0,DOWN,CALU1 +S 1400,4400,2500,4400,200,*,LEFT,ALU1 +S 2500,3300,2500,4400,200,*,UP,ALU1 +S 2400,3300,2500,3300,200,*,RIGHT,ALU1 +S 300,3900,1400,3900,200,*,LEFT,ALU1 +S 1400,3900,1400,4400,200,*,UP,ALU1 +S 3100,2700,3100,5000,200,*,UP,ALU1 +S 1000,1100,1000,1600,100,*,UP,POLY +S 1700,1100,1700,1500,100,*,UP,POLY +S 2800,1100,2800,1500,100,*,UP,POLY +S 2800,2900,2800,3400,100,*,DOWN,POLY +S 0,0,4000,0,300,*,RIGHT,PTIE +S 0,0,4000,0,400,vss,RIGHT,CALU1 +S 3700,600,3700,4400,200,q,DOWN,CALU1 +S 3100,0,3100,1300,200,*,DOWN,ALU1 +S 3400,2400,3400,4700,100,*,UP,PTRANS +S 3100,2600,3100,4500,300,*,DOWN,PDIF +S 3700,2600,3700,4500,300,*,UP,PDIF +S 2800,3400,2800,4700,100,*,DOWN,PTRANS +S 2800,300,2800,1100,100,*,UP,NTRANS +S 3400,300,3400,1600,100,*,UP,NTRANS +S 3100,500,3100,1400,300,*,UP,NDIF +S 3700,500,3700,1400,300,*,DOWN,NDIF +S 3400,1600,3400,2400,100,*,DOWN,POLY +S 0,5000,4000,5000,300,*,RIGHT,NTIE +S 0,4000,4000,4000,1200,*,RIGHT,NWELL +S 0,3100,4000,3100,1200,*,RIGHT,NWELL +S 0,5000,4000,5000,400,vdd,RIGHT,CALU1 +S 2100,1100,2100,2000,100,*,UP,POLY +S 2100,1100,2300,1100,100,*,LEFT,POLY +S 1000,1100,1200,1100,100,*,LEFT,POLY +S 300,600,300,4400,200,*,DOWN,ALU1 +S 300,3900,300,4500,300,*,DOWN,PDIF +S 600,3600,600,4700,100,*,DOWN,PTRANS +S 900,3600,900,4500,300,*,DOWN,PDIF +S 1200,3400,1200,4700,100,*,DOWN,PTRANS +S 2000,3600,2000,4500,500,*,DOWN,PDIF +S 2300,3400,2300,4700,100,*,DOWN,PTRANS +S 1700,3400,1700,4700,100,*,DOWN,PTRANS +S 2300,4500,2300,4600,100,*,DOWN,POLY +S 600,300,600,1000,100,*,UP,NTRANS +S 300,500,300,800,300,*,DOWN,NDIF +S 2300,300,2300,1100,100,*,UP,NTRANS +S 1200,300,1200,1100,100,*,UP,NTRANS +S 1700,300,1700,1100,100,*,UP,NTRANS +S 900,500,900,900,300,*,UP,NDIF +S 2000,500,2000,900,500,*,DOWN,NDIF +S 900,4400,900,5000,200,*,UP,ALU1 +S 900,0,900,600,200,*,DOWN,ALU1 +B 900,1600,200,200,CONT_TURN8,* +B 2100,2400,200,200,CONT_TURN1,* +B 2100,600,200,200,CONT_TURN1,* +B 1500,1100,200,200,CONT_TURN1,* +B 1900,2400,200,200,CONT_TURN1,* +B 1900,3900,200,200,CONT_TURN1,* +B 2500,3300,200,200,CONT_TURN1,* +B 2500,4400,200,200,CONT_TURN1,* +B 1400,3900,200,200,CONT_TURN1,* +B 1400,4400,200,200,CONT_TURN1,* +V 1500,1600,CONT_POLY,* +V 2600,2800,CONT_POLY,* +V 2600,1600,CONT_POLY,* +V 900,3100,CONT_POLY,* +V 1400,2100,CONT_POLY,* +V 900,1600,CONT_POLY,* +V 2400,3300,CONT_POLY,* +V 3100,2700,CONT_DIF_P,* +V 3100,3200,CONT_DIF_P,* +V 3100,3800,CONT_DIF_P,* +V 4000,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 3700,3800,CONT_DIF_P,* +V 3700,3200,CONT_DIF_P,* +V 3700,2700,CONT_DIF_P,* +V 3700,4400,CONT_DIF_P,* +V 3700,600,CONT_DIF_N,* +V 3700,1300,CONT_DIF_N,* +V 3100,1300,CONT_DIF_N,* +V 3100,4400,CONT_DIF_P,* +V 3100,600,CONT_DIF_N,* +V 2000,2400,CONT_POLY,* +V 300,600,CONT_DIF_N,* +V 300,3900,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2000,3900,CONT_DIF_P,* +V 2000,600,CONT_DIF_N,* +V 900,4400,CONT_DIF_P,* +V 900,600,CONT_DIF_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/mx2_x2.vbe b/pdks/symbolic/lsxlib/cells/mx2_x2.vbe new file mode 100644 index 000000000..401686e9e --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/mx2_x2.vbe @@ -0,0 +1,40 @@ +ENTITY mx2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_cmd_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 451; + CONSTANT tphh_i1_q : NATURAL := 451; + CONSTANT tpll_i0_q : NATURAL := 469; + CONSTANT tpll_i1_q : NATURAL := 469; + CONSTANT tphh_cmd_q : NATURAL := 484; + CONSTANT tphl_cmd_q : NATURAL := 485; + CONSTANT tpll_cmd_q : NATURAL := 522; + CONSTANT tplh_cmd_q : NATURAL := 534; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x2; + +ARCHITECTURE behaviour_data_flow OF mx2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x2" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1100 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/mx2_x4.ap b/pdks/symbolic/lsxlib/cells/mx2_x4.ap new file mode 100644 index 000000000..aee16829f --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/mx2_x4.ap @@ -0,0 +1,153 @@ +V ALLIANCE : 6 +H mx2_x4,P, 5/ 8/2024,100 +A 0,0,5000,5000 +S 1100,1600,1200,1600,200,*,RIGHT,POLY2 +S 1400,3300,1400,3400,100,*,UP,POLY +S 1100,3300,1400,3300,100,*,RIGHT,POLY +S 1100,3100,1100,3300,200,*,UP,POLY2 +S 1700,1600,1900,1600,200,*,LEFT,POLY2 +S 2800,1600,3000,1600,200,*,RIGHT,POLY2 +S 2800,2800,3000,2800,200,*,RIGHT,POLY2 +S 2500,3300,2600,3300,200,*,LEFT,POLY2 +S 0,1100,5000,1100,1400,*,RIGHT,PWELL +S 2200,2400,2800,2400,100,*,RIGHT,POLY +S 4200,2400,4200,4700,100,*,UP,PTRANS +S 4500,2600,4500,4500,300,*,UP,PDIF +S 1400,3400,1400,4700,100,*,DOWN,PTRANS +S 1100,3600,1100,4500,300,*,DOWN,PDIF +S 3300,2600,3300,4500,300,*,DOWN,PDIF +S 3600,2400,3600,4700,100,*,UP,PTRANS +S 1900,3400,1900,4700,100,*,DOWN,PTRANS +S 2500,3400,2500,4700,100,*,DOWN,PTRANS +S 2200,3600,2200,4500,500,*,DOWN,PDIF +S 800,3600,800,4700,100,*,DOWN,PTRANS +S 500,3900,500,4500,300,*,DOWN,PDIF +S 3000,3400,3000,4700,100,*,DOWN,PTRANS +S 3900,2600,3900,4500,300,*,UP,PDIF +S 1900,300,1900,1100,100,*,UP,NTRANS +S 1400,300,1400,1100,100,*,UP,NTRANS +S 2500,300,2500,1100,100,*,UP,NTRANS +S 800,300,800,1000,100,*,UP,NTRANS +S 3600,300,3600,1600,100,*,UP,NTRANS +S 3000,300,3000,1100,100,*,UP,NTRANS +S 4200,300,4200,1600,100,*,UP,NTRANS +S 2200,500,2200,900,500,*,DOWN,NDIF +S 4500,500,4500,1400,300,*,UP,NDIF +S 500,500,500,800,300,*,DOWN,NDIF +S 3900,500,3900,1400,300,*,DOWN,NDIF +S 3300,500,3300,1400,300,*,UP,NDIF +S 1100,500,1100,900,300,*,UP,NDIF +S 3600,2100,4200,2100,100,*,RIGHT,POLY +S 4200,1600,4200,2400,100,*,DOWN,POLY +S 3600,1600,3600,2400,100,*,DOWN,POLY +S 3000,2900,3000,3400,100,*,DOWN,POLY +S 2500,4500,2500,4600,100,*,DOWN,POLY +S 1200,1100,1400,1100,100,*,LEFT,POLY +S 2300,1100,2500,1100,100,*,LEFT,POLY +S 1900,1100,1900,1500,100,*,UP,POLY +S 1200,1100,1200,1600,100,*,UP,POLY +S 700,3600,800,3600,100,*,LEFT,POLY +S 700,1000,700,3600,100,*,DOWN,POLY +S 2300,1100,2300,2000,100,*,UP,POLY +S 700,2000,2300,2000,100,*,LEFT,POLY +S 2800,2100,2800,2400,100,*,UP,POLY +S 2800,2100,3600,2100,100,*,LEFT,POLY +S 3000,1100,3000,1500,100,*,UP,POLY +S 1600,2800,1900,2800,100,*,RIGHT,POLY +S 1600,2100,1600,2800,100,*,DOWN,POLY +S 1900,2800,1900,3400,100,*,UP,POLY +S 700,1000,800,1000,100,*,RIGHT,POLY +S 1100,0,1100,600,200,*,DOWN,ALU1 +S 3300,0,3300,1300,200,*,DOWN,ALU1 +S 4500,0,4500,1300,200,*,DOWN,ALU1 +S 1100,1600,1100,3400,200,i0,DOWN,CALU1 +S 1600,2100,1600,3400,200,cmd,DOWN,CALU1 +S 1100,4400,1100,5000,200,*,UP,ALU1 +S 500,600,500,4400,200,*,DOWN,ALU1 +S 3900,600,3900,4400,200,q,DOWN,CALU1 +S 4500,2700,4500,5000,200,*,UP,ALU1 +S 1700,1100,1700,1600,200,*,DOWN,ALU1 +S 500,1100,1700,1100,200,*,RIGHT,ALU1 +S 3300,2700,3300,5000,200,*,UP,ALU1 +S 1600,3900,1600,4400,200,*,UP,ALU1 +S 500,3900,1600,3900,200,*,LEFT,ALU1 +S 2600,3300,2700,3300,200,*,RIGHT,ALU1 +S 2700,3300,2700,4400,200,*,UP,ALU1 +S 1600,4400,2700,4400,200,*,LEFT,ALU1 +S 2100,3900,2200,3900,200,*,RIGHT,ALU1 +S 2800,600,2800,2800,200,i1,DOWN,CALU1 +S 2100,2400,2100,3900,200,*,DOWN,ALU1 +S 2300,600,2300,2400,200,*,UP,ALU1 +S 2200,600,2300,600,200,*,LEFT,ALU1 +S 2100,2400,2300,2400,200,*,LEFT,ALU1 +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +S 0,0,5000,0,300,*,RIGHT,PTIE +S 0,0,5000,0,400,vss,RIGHT,CALU1 +B 2300,2400,200,200,CONT_TURN1,* +B 2100,2400,200,200,CONT_TURN1,* +B 2300,600,200,200,CONT_TURN1,* +B 1700,1100,200,200,CONT_TURN1,* +B 2100,3900,200,200,CONT_TURN1,* +B 2700,3300,200,200,CONT_TURN1,* +B 2700,4400,200,200,CONT_TURN1,* +B 1600,3900,200,200,CONT_TURN1,* +B 1600,4400,200,200,CONT_TURN1,* +V 3900,3800,CONT_DIF_P,* +V 1100,4400,CONT_DIF_P,* +V 2200,3900,CONT_DIF_P,* +V 4500,4400,CONT_DIF_P,* +V 4500,3200,CONT_DIF_P,* +V 4500,3800,CONT_DIF_P,* +V 4500,2700,CONT_DIF_P,* +V 500,4400,CONT_DIF_P,* +V 500,3900,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 3900,2700,CONT_DIF_P,* +V 3900,3200,CONT_DIF_P,* +V 3300,3800,CONT_DIF_P,* +V 3300,3200,CONT_DIF_P,* +V 3300,2700,CONT_DIF_P,* +V 4500,1300,CONT_DIF_N,* +V 4500,600,CONT_DIF_N,* +V 1100,600,CONT_DIF_N,* +V 2200,600,CONT_DIF_N,* +V 500,600,CONT_DIF_N,* +V 3300,600,CONT_DIF_N,* +V 3300,1300,CONT_DIF_N,* +V 3900,1300,CONT_DIF_N,* +V 3900,600,CONT_DIF_N,* +V 2800,1600,CONT_POLY,* +V 2800,2800,CONT_POLY,* +V 1700,1600,CONT_POLY,* +V 2200,2400,CONT_POLY,* +V 2600,3300,CONT_POLY,* +V 1100,1600,CONT_POLY,* +V 1600,2100,CONT_POLY,* +V 1100,3100,CONT_POLY,* +V 4500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4000,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/mx2_x4.vbe b/pdks/symbolic/lsxlib/cells/mx2_x4.vbe new file mode 100644 index 000000000..ddb1f3ca7 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/mx2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY mx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 564; + CONSTANT tphh_i1_q : NATURAL := 564; + CONSTANT tphl_cmd_q : NATURAL := 574; + CONSTANT tpll_i0_q : NATURAL := 576; + CONSTANT tpll_i1_q : NATURAL := 576; + CONSTANT tphh_cmd_q : NATURAL := 615; + CONSTANT tplh_cmd_q : NATURAL := 631; + CONSTANT tpll_cmd_q : NATURAL := 647; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x4; + +ARCHITECTURE behaviour_data_flow OF mx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x4" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/mx3_x2.ap b/pdks/symbolic/lsxlib/cells/mx3_x2.ap new file mode 100644 index 000000000..a88add363 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/mx3_x2.ap @@ -0,0 +1,199 @@ +V ALLIANCE : 6 +H mx3_x2,P, 5/ 8/2024,100 +A 0,0,6500,5000 +S 2300,3400,2400,3400,200,*,RIGHT,POLY2 +S 1600,1100,1700,1100,200,*,RIGHT,POLY2 +S 0,1100,6500,1100,1400,*,RIGHT,PWELL +S 5000,1200,5000,1700,300,*,DOWN,NDIF +S 900,4400,3200,4400,200,*,RIGHT,ALU1 +S 300,600,300,1400,300,*,DOWN,NDIF +S 2300,2100,2900,2100,100,*,RIGHT,POLY +S 1200,2100,1500,2100,100,*,RIGHT,POLY +S 4600,3400,4600,3500,100,*,UP,POLY +S 5600,2100,5700,2100,200,*,LEFT,ALU1 +S 4500,3400,4600,3400,200,*,LEFT,ALU1 +S 4500,2100,4600,2100,200,*,LEFT,ALU1 +S 600,1600,600,2400,100,*,DOWN,POLY +S 2900,1000,2900,3500,100,*,DOWN,POLY +S 1200,1000,1200,3500,100,*,DOWN,POLY +S 5000,1100,5600,1100,200,*,RIGHT,ALU1 +S 5000,600,5000,1100,200,*,UP,ALU1 +S 4900,600,5000,600,200,*,RIGHT,ALU1 +S 0,5000,6500,5000,300,*,RIGHT,NTIE +S 2300,2900,2300,3400,200,*,UP,ALU1 +S 2400,3400,2400,3600,100,*,UP,POLY +S 5600,1100,5600,3900,200,*,DOWN,ALU1 +S 5700,2100,5900,2100,200,*,RIGHT,POLY +S 2100,3900,5600,3900,200,*,RIGHT,ALU1 +S 6200,2600,6200,4500,300,*,UP,PDIF +S 5600,4400,5600,5000,200,*,UP,ALU1 +S 4500,2100,4500,3400,200,i0,DOWN,CALU1 +S 5600,0,5600,600,200,*,UP,ALU1 +S 5900,2400,5900,4700,100,*,UP,PTRANS +S 5900,1600,5900,2400,100,*,UP,POLY +S 5900,300,5900,1600,100,*,UP,NTRANS +S 5100,1600,5100,2900,200,*,DOWN,ALU1 +S 2800,1100,2800,3900,200,*,UP,ALU1 +S 5600,2600,5600,4500,300,*,UP,PDIF +S 5300,1600,5300,2500,100,*,DOWN,POLY +S 3900,2500,5300,2500,100,*,RIGHT,POLY +S 5300,2500,5300,3400,100,*,UP,PTRANS +S 5000,2700,5000,3200,300,*,UP,PDIF +S 6200,500,6200,1400,300,*,UP,NDIF +S 6200,600,6200,4400,200,q,DOWN,CALU1 +S 3800,0,3800,600,200,*,UP,ALU1 +S 3900,1600,3900,3400,200,cmd0,UP,CALU1 +S 3700,1600,3900,1600,100,*,RIGHT,POLY +S 3900,1600,3900,3500,100,*,DOWN,POLY +S 3700,1000,3700,1600,100,*,DOWN,POLY +S 4600,1000,4600,2100,100,*,DOWN,POLY +S 4100,1000,4100,1100,100,*,DOWN,POLY +S 900,600,3200,600,200,*,RIGHT,ALU1 +S 4600,300,4600,1000,100,*,UP,NTRANS +S 3500,300,3500,1000,100,*,UP,NTRANS +S 4100,300,4100,1000,100,*,UP,NTRANS +S 3800,500,3800,800,300,*,DOWN,NDIF +S 4900,500,4900,800,300,*,UP,NDIF +S 3500,1000,3700,1000,100,*,RIGHT,POLY +S 3300,1100,4500,1100,200,*,RIGHT,ALU1 +S 3300,1100,3300,1600,200,*,DOWN,ALU1 +S 5300,1000,5300,1600,100,*,DOWN,NTRANS +S 5600,500,5600,1400,300,*,DOWN,NDIF +S 4500,1600,5000,1600,200,*,LEFT,ALU1 +S 4500,1100,4500,1600,200,*,DOWN,ALU1 +S 3300,1600,3300,3500,100,*,UP,POLY +S 300,2600,300,4500,300,*,UP,PDIF +S 900,2600,900,3100,300,*,UP,PDIF +S 600,2400,600,3300,100,*,UP,PTRANS +S 0,4000,6500,4000,1200,*,RIGHT,NWELL +S 0,3100,6500,3100,1200,*,RIGHT,NWELL +S 4900,3700,4900,4500,300,*,UP,PDIF +S 3800,4400,3800,5000,200,*,UP,ALU1 +S 3900,3500,4100,3500,100,*,LEFT,POLY +S 3300,3500,3500,3500,100,*,RIGHT,POLY +S 2100,3700,2100,4500,300,*,UP,PDIF +S 2400,1000,2400,1700,100,*,UP,POLY +S 4600,3500,4600,4700,100,*,UP,PTRANS +S 2300,1600,2300,2400,200,i1,UP,CALU1 +S 1500,1600,1500,2400,200,i2,UP,CALU1 +S 400,3400,1600,3400,200,*,LEFT,ALU1 +S 400,1100,400,3900,200,cmd1,DOWN,CALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +S 400,2100,600,2100,200,*,RIGHT,POLY +S 300,0,300,600,200,*,DOWN,ALU1 +S 900,1100,900,2900,200,*,UP,ALU1 +S 600,1000,600,1600,100,*,DOWN,NTRANS +S 900,1200,900,1400,300,*,DOWN,NDIF +S 900,1100,1600,1100,200,*,RIGHT,ALU1 +S 1200,300,1200,1000,100,*,UP,NTRANS +S 2400,300,2400,1000,100,*,UP,NTRANS +S 1700,300,1700,1000,100,*,UP,NTRANS +S 2900,300,2900,1000,100,*,UP,NTRANS +S 1500,500,1500,800,300,*,DOWN,NDIF +S 900,500,900,800,300,*,DOWN,NDIF +S 3300,500,3300,800,300,*,DOWN,NDIF +S 1900,1700,1900,2500,100,*,DOWN,POLY +S 1700,2500,1900,2500,100,*,RIGHT,POLY +S 1700,2500,1700,3500,100,*,DOWN,POLY +S 900,2900,2300,2900,200,*,LEFT,ALU1 +S 1900,1700,2400,1700,100,*,RIGHT,POLY +S 1200,3500,1200,4700,100,*,UP,PTRANS +S 1500,3700,1500,4500,300,*,DOWN,PDIF +S 1700,3500,1700,4700,100,*,UP,PTRANS +S 2400,3500,2400,4700,100,*,UP,PTRANS +S 4100,3500,4100,4700,100,*,UP,PTRANS +S 3500,3500,3500,4700,100,*,UP,PTRANS +S 3800,3700,3800,4500,300,*,UP,PDIF +S 3200,3700,3200,4500,300,*,UP,PDIF +S 2900,3500,2900,4700,100,*,UP,PTRANS +S 900,3700,900,4500,300,*,UP,PDIF +S 2100,500,2100,1200,300,*,UP,NDIF +S 2100,1100,2800,1100,200,*,RIGHT,ALU1 +S 0,0,6500,0,300,*,RIGHT,PTIE +S 0,5000,6500,5000,400,vdd,RIGHT,CALU1 +S 0,0,6500,0,400,vss,RIGHT,CALU1 +B 2550,2100,700,200,CONT_TURN8,* +B 4100,1100,200,200,CONT_TURN8,* +B 4600,3400,200,200,CONT_TURN8,* +B 1600,3400,200,200,CONT_TURN8,* +B 5750,2100,300,200,CONT_TURN8,* +B 450,2100,300,200,CONT_TURN8,* +B 1400,2100,400,200,CONT_TURN8,* +B 5100,2900,200,200,CONT_TURN1,* +B 5100,1600,200,200,CONT_TURN1,* +B 5600,3900,200,200,CONT_TURN1,* +B 5600,1100,200,200,CONT_TURN1,* +B 5000,600,200,200,CONT_TURN1,* +B 5000,1100,200,200,CONT_TURN1,* +B 4500,1600,200,200,CONT_TURN1,* +B 4500,1100,200,200,CONT_TURN1,* +B 3300,1100,200,200,CONT_TURN1,* +B 2800,1100,200,200,CONT_TURN1,* +B 2300,2900,200,200,CONT_TURN1,* +B 900,2900,200,200,CONT_TURN1,* +B 900,1100,200,200,CONT_TURN1,* +V 6500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2300,3400,CONT_POLY,* +V 6200,3300,CONT_DIF_P,* +V 6200,3900,CONT_DIF_P,* +V 6200,4400,CONT_DIF_P,* +V 6200,600,CONT_DIF_N,* +V 6200,1300,CONT_DIF_N,* +V 5700,2100,CONT_POLY,* +V 5600,4400,CONT_DIF_P,* +V 5600,600,CONT_DIF_N,* +V 6200,2700,CONT_DIF_P,* +V 5000,2900,CONT_DIF_P,* +V 4100,1100,CONT_POLY,* +V 4900,600,CONT_DIF_N,* +V 3800,600,CONT_DIF_N,* +V 3300,1600,CONT_POLY,* +V 5000,1600,CONT_DIF_N,* +V 3200,600,CONT_DIF_N,* +V 900,2700,CONT_DIF_P,* +V 4900,3900,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 4600,2100,CONT_POLY,* +V 4600,3400,CONT_POLY,* +V 3800,4400,CONT_DIF_P,* +V 3200,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 400,2100,CONT_POLY,* +V 300,600,CONT_DIF_N,* +V 900,1300,CONT_DIF_N,* +V 1600,1100,CONT_POLY,* +V 3900,2500,CONT_POLY,* +V 1500,2100,CONT_POLY,* +V 2100,1100,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 1600,3400,CONT_POLY,* +V 2300,2100,CONT_POLY,* +V 6500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/mx3_x2.vbe b/pdks/symbolic/lsxlib/cells/mx3_x2.vbe new file mode 100644 index 000000000..ddc531ad5 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/mx3_x2.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 1620; + CONSTANT rdown_cmd1_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_cmd0_q : NATURAL := 1790; + CONSTANT rup_cmd1_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 538; + CONSTANT tphh_cmd0_q : NATURAL := 573; + CONSTANT tphh_i1_q : NATURAL := 654; + CONSTANT tphh_i2_q : NATURAL := 654; + CONSTANT tpll_i0_q : NATURAL := 658; + CONSTANT tphh_cmd1_q : NATURAL := 664; + CONSTANT tpll_cmd0_q : NATURAL := 680; + CONSTANT tplh_cmd1_q : NATURAL := 738; + CONSTANT tphl_cmd1_q : NATURAL := 739; + CONSTANT tplh_cmd0_q : NATURAL := 768; + CONSTANT tphl_cmd0_q : NATURAL := 792; + CONSTANT tpll_i1_q : NATURAL := 808; + CONSTANT tpll_i2_q : NATURAL := 808; + CONSTANT tpll_cmd1_q : NATURAL := 817; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x2; + +ARCHITECTURE behaviour_data_flow OF mx3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx3_x2" + SEVERITY WARNING; + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) + and i2)))) after 1400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/mx3_x4.ap b/pdks/symbolic/lsxlib/cells/mx3_x4.ap new file mode 100644 index 000000000..aad9b7d60 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/mx3_x4.ap @@ -0,0 +1,224 @@ +V ALLIANCE : 6 +H mx3_x4,P, 5/ 8/2024,100 +A 0,0,7000,5000 +S 1600,1100,1700,1100,200,*,RIGHT,POLY2 +S 4400,2000,4400,2100,200,*,DOWN,POLY2 +S 4400,2100,4600,2100,200,*,RIGHT,POLY2 +S 4400,3000,4600,3000,200,*,RIGHT,POLY2 +S 4400,3000,4400,3100,200,*,UP,POLY2 +S 2300,3400,2400,3400,200,*,RIGHT,POLY2 +S 0,1100,7000,1100,1400,*,RIGHT,PWELL +S 4900,1200,4900,1700,300,*,DOWN,NDIF +S 900,4400,3200,4400,200,*,RIGHT,ALU1 +S 300,600,300,1400,300,*,DOWN,NDIF +S 2900,1000,2900,3500,100,*,DOWN,POLY +S 2400,3400,2400,3500,100,*,UP,POLY +S 2300,2100,2900,2100,100,*,RIGHT,POLY +S 1200,2100,1500,2100,100,*,RIGHT,POLY +S 5500,2100,5600,2100,200,*,LEFT,ALU1 +S 4500,1600,4900,1600,200,*,LEFT,ALU1 +S 600,1600,600,2400,100,*,DOWN,POLY +S 1200,1000,1200,3500,100,*,DOWN,POLY +S 0,4000,7000,4000,1200,*,RIGHT,NWELL +S 0,3100,7000,3100,1200,*,RIGHT,NWELL +S 0,5000,7000,5000,300,*,RIGHT,NTIE +S 0,5000,7000,5000,400,vdd,RIGHT,CALU1 +S 0,0,7000,0,300,*,RIGHT,PTIE +S 0,0,7000,0,400,vss,RIGHT,CALU1 +S 5600,2100,6400,2100,200,*,RIGHT,POLY +S 4600,3100,4600,3500,100,*,DOWN,POLY +S 4400,3100,4600,3100,100,*,LEFT,POLY +S 4400,3000,4400,3100,200,*,DOWN,POLY +S 5000,1100,5500,1100,200,*,RIGHT,ALU1 +S 2100,3900,5500,3900,200,*,RIGHT,ALU1 +S 3900,2500,5200,2500,100,*,RIGHT,POLY +S 4900,2700,4900,3200,300,*,UP,PDIF +S 4900,1600,4900,2900,200,*,DOWN,ALU1 +S 6400,2400,6400,4700,100,*,UP,PTRANS +S 6700,2600,6700,4500,300,*,UP,PDIF +S 6100,2600,6100,4500,300,*,UP,PDIF +S 5800,2400,5800,4700,100,*,UP,PTRANS +S 5500,2600,5500,4500,300,*,UP,PDIF +S 6400,300,6400,1600,100,*,UP,NTRANS +S 5800,300,5800,1600,100,*,UP,NTRANS +S 5200,1000,5200,1600,100,*,DOWN,NTRANS +S 6700,500,6700,1400,300,*,UP,NDIF +S 5500,500,5500,1400,300,*,DOWN,NDIF +S 6100,500,6100,1400,300,*,UP,NDIF +S 5200,2500,5200,3400,100,*,UP,PTRANS +S 6400,1600,6400,2400,100,*,UP,POLY +S 5800,1600,5800,2400,100,*,UP,POLY +S 5200,1600,5200,2500,100,*,DOWN,POLY +S 6700,0,6700,1300,200,*,DOWN,ALU1 +S 5500,0,5500,600,200,*,UP,ALU1 +S 6700,2700,6700,5000,200,*,UP,ALU1 +S 6100,600,6100,4400,200,q,DOWN,CALU1 +S 5500,1100,5500,3900,200,*,DOWN,ALU1 +S 5500,4400,5500,5000,200,*,UP,ALU1 +S 4400,2000,4400,2100,200,*,DOWN,POLY +S 4400,2000,4600,2000,100,*,LEFT,POLY +S 4600,1000,4600,2000,100,*,UP,POLY +S 4400,2100,4400,3400,200,i0,DOWN,CALU1 +S 3800,1600,3800,3400,200,cmd0,UP,CALU1 +S 5000,600,5000,1100,200,*,UP,ALU1 +S 4900,600,5000,600,200,*,RIGHT,ALU1 +S 2300,2900,2300,3400,200,*,UP,ALU1 +S 2300,3400,2400,3400,200,*,RIGHT,POLY +S 2800,1100,2800,3900,200,*,UP,ALU1 +S 3800,0,3800,600,200,*,UP,ALU1 +S 3700,1600,3900,1600,100,*,RIGHT,POLY +S 3900,1600,3900,3500,100,*,DOWN,POLY +S 3700,1000,3700,1600,100,*,DOWN,POLY +S 4100,1000,4100,1100,100,*,DOWN,POLY +S 900,600,3200,600,200,*,RIGHT,ALU1 +S 4600,300,4600,1000,100,*,UP,NTRANS +S 3500,300,3500,1000,100,*,UP,NTRANS +S 4100,300,4100,1000,100,*,UP,NTRANS +S 3800,500,3800,800,300,*,DOWN,NDIF +S 4900,500,4900,800,300,*,UP,NDIF +S 3500,1000,3700,1000,100,*,RIGHT,POLY +S 3300,1100,4500,1100,200,*,RIGHT,ALU1 +S 3300,1100,3300,1600,200,*,DOWN,ALU1 +S 4500,1100,4500,1600,200,*,DOWN,ALU1 +S 3300,1600,3300,3500,100,*,UP,POLY +S 300,2600,300,4500,300,*,UP,PDIF +S 900,2600,900,3100,300,*,UP,PDIF +S 600,2400,600,3300,100,*,UP,PTRANS +S 4900,3700,4900,4500,300,*,UP,PDIF +S 3800,4400,3800,5000,200,*,UP,ALU1 +S 3900,3500,4100,3500,100,*,LEFT,POLY +S 3300,3500,3500,3500,100,*,RIGHT,POLY +S 2100,3700,2100,4500,300,*,UP,PDIF +S 2400,1000,2400,1700,100,*,UP,POLY +S 4600,3500,4600,4700,100,*,UP,PTRANS +S 2300,1600,2300,2400,200,i1,UP,CALU1 +S 1500,1600,1500,2400,200,i2,UP,CALU1 +S 400,3400,1600,3400,200,*,LEFT,ALU1 +S 400,1100,400,3900,200,cmd1,DOWN,CALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +S 400,2100,600,2100,200,*,RIGHT,POLY +S 300,0,300,600,200,*,DOWN,ALU1 +S 900,1100,900,2900,200,*,UP,ALU1 +S 600,1000,600,1600,100,*,DOWN,NTRANS +S 900,1200,900,1400,300,*,DOWN,NDIF +S 1700,1000,1700,1100,100,*,DOWN,POLY +S 1600,1100,1700,1100,200,*,LEFT,POLY +S 900,1100,1600,1100,200,*,RIGHT,ALU1 +S 1200,300,1200,1000,100,*,UP,NTRANS +S 2400,300,2400,1000,100,*,UP,NTRANS +S 1700,300,1700,1000,100,*,UP,NTRANS +S 2900,300,2900,1000,100,*,UP,NTRANS +S 1500,500,1500,800,300,*,DOWN,NDIF +S 900,500,900,800,300,*,DOWN,NDIF +S 3300,500,3300,800,300,*,DOWN,NDIF +S 1900,1700,1900,2500,100,*,DOWN,POLY +S 1700,2500,1900,2500,100,*,RIGHT,POLY +S 1700,2500,1700,3500,100,*,DOWN,POLY +S 900,2900,2300,2900,200,*,LEFT,ALU1 +S 1900,1700,2400,1700,100,*,RIGHT,POLY +S 1200,3500,1200,4700,100,*,UP,PTRANS +S 1500,3700,1500,4500,300,*,DOWN,PDIF +S 1700,3500,1700,4700,100,*,UP,PTRANS +S 2400,3500,2400,4700,100,*,UP,PTRANS +S 4100,3500,4100,4700,100,*,UP,PTRANS +S 3500,3500,3500,4700,100,*,UP,PTRANS +S 3800,3700,3800,4500,300,*,UP,PDIF +S 3200,3700,3200,4500,300,*,UP,PDIF +S 2900,3500,2900,4700,100,*,UP,PTRANS +S 900,3700,900,4500,300,*,UP,PDIF +S 2100,500,2100,1200,300,*,UP,NDIF +S 2100,1100,2800,1100,200,*,RIGHT,ALU1 +B 2550,2100,700,200,CONT_TURN8,* +B 4450,3000,300,200,CONT_TURN8,* +B 5950,2100,900,200,CONT_TURN8,* +B 1600,1100,200,200,CONT_TURN8,* +B 4100,1100,200,200,CONT_TURN8,* +B 4450,2100,300,200,CONT_TURN8,* +B 2300,3400,200,200,CONT_TURN8,* +B 1600,3400,200,200,CONT_TURN8,* +B 450,2100,300,200,CONT_TURN8,* +B 1400,2100,400,200,CONT_TURN8,* +B 5000,600,200,200,CONT_TURN1,* +B 3300,1100,200,200,CONT_TURN1,* +B 4500,1100,200,200,CONT_TURN1,* +B 4500,1600,200,200,CONT_TURN1,* +B 5000,1100,200,200,CONT_TURN1,* +B 5500,1100,200,200,CONT_TURN1,* +B 5500,3900,200,200,CONT_TURN1,* +B 2800,1100,200,200,CONT_TURN1,* +B 900,1100,200,200,CONT_TURN1,* +B 2300,2900,200,200,CONT_TURN1,* +B 900,2900,200,200,CONT_TURN1,* +V 7000,0,CONT_BODY_P,* +V 7000,5000,CONT_BODY_N,* +V 4400,3000,CONT_POLY,* +V 4900,2900,CONT_DIF_P,* +V 4900,1600,CONT_DIF_N,* +V 6700,3300,CONT_DIF_P,* +V 6700,2700,CONT_DIF_P,* +V 6700,4400,CONT_DIF_P,* +V 6700,3900,CONT_DIF_P,* +V 5500,4400,CONT_DIF_P,* +V 6100,2700,CONT_DIF_P,* +V 6100,3300,CONT_DIF_P,* +V 6100,3900,CONT_DIF_P,* +V 6100,4400,CONT_DIF_P,* +V 6700,600,CONT_DIF_N,* +V 6700,1300,CONT_DIF_N,* +V 6100,1300,CONT_DIF_N,* +V 5500,600,CONT_DIF_N,* +V 6100,600,CONT_DIF_N,* +V 5600,2100,CONT_POLY,* +V 4400,2100,CONT_POLY,* +V 3800,2500,CONT_POLY,* +V 6500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2300,3400,CONT_POLY,* +V 4100,1100,CONT_POLY,* +V 4900,600,CONT_DIF_N,* +V 3800,600,CONT_DIF_N,* +V 3300,1600,CONT_POLY,* +V 3200,600,CONT_DIF_N,* +V 900,2700,CONT_DIF_P,* +V 4900,3900,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 3800,4400,CONT_DIF_P,* +V 3200,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 400,2100,CONT_POLY,* +V 300,600,CONT_DIF_N,* +V 900,1300,CONT_DIF_N,* +V 1600,1100,CONT_POLY,* +V 1500,2100,CONT_POLY,* +V 2100,1100,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 1600,3400,CONT_POLY,* +V 2300,2100,CONT_POLY,* +V 6500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/mx3_x4.vbe b/pdks/symbolic/lsxlib/cells/mx3_x4.vbe new file mode 100644 index 000000000..77baa4489 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/mx3_x4.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 810; + CONSTANT rdown_cmd1_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_cmd0_q : NATURAL := 890; + CONSTANT rup_cmd1_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 640; + CONSTANT tphh_cmd0_q : NATURAL := 683; + CONSTANT tphh_i1_q : NATURAL := 770; + CONSTANT tphh_i2_q : NATURAL := 770; + CONSTANT tpll_i0_q : NATURAL := 774; + CONSTANT tpll_cmd0_q : NATURAL := 779; + CONSTANT tphh_cmd1_q : NATURAL := 792; + CONSTANT tplh_cmd0_q : NATURAL := 844; + CONSTANT tplh_cmd1_q : NATURAL := 846; + CONSTANT tphl_cmd1_q : NATURAL := 872; + CONSTANT tphl_cmd0_q : NATURAL := 922; + CONSTANT tpll_i1_q : NATURAL := 948; + CONSTANT tpll_i2_q : NATURAL := 948; + CONSTANT tpll_cmd1_q : NATURAL := 967; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x4; + +ARCHITECTURE behaviour_data_flow OF mx3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx3_x4" + SEVERITY WARNING; + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) + and i2)))) after 1600 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/na2_x1.ap b/pdks/symbolic/lsxlib/cells/na2_x1.ap new file mode 100644 index 000000000..477aa9d3f --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na2_x1.ap @@ -0,0 +1,52 @@ +V ALLIANCE : 6 +H na2_x1,P, 1/ 8/2024,100 +A 0,0,2000,5000 +S 0,1100,2000,1100,1400,*,RIGHT,PWELL +S 1000,500,1000,1400,300,*,DOWN,NDIF +S 700,1600,700,3400,100,*,UP,POLY +S 1300,1600,1300,3400,100,*,DOWN,POLY +S 0,4000,2000,4000,1200,*,RIGHT,NWELL +S 0,3100,2000,3100,1200,*,RIGHT,NWELL +S 0,0,2000,0,400,vss,RIGHT,CALU1 +S 0,5000,2000,5000,400,vdd,RIGHT,CALU1 +S 1500,1100,1500,3900,200,i1,DOWN,CALU1 +S 500,1100,500,3900,200,i0,DOWN,CALU1 +S 400,4400,400,5000,200,*,UP,ALU1 +S 1600,4400,1600,5000,200,*,UP,ALU1 +S 1600,3600,1600,4500,300,*,DOWN,PDIF +S 400,3600,400,4500,300,*,DOWN,PDIF +S 1300,3400,1300,4700,100,*,UP,PTRANS +S 1000,3600,1000,4500,300,*,DOWN,PDIF +S 700,3400,700,4700,100,*,UP,PTRANS +S 1000,600,1000,4400,200,nq,DOWN,CALU1 +S 400,0,400,600,200,*,DOWN,ALU1 +S 1000,600,1600,600,200,*,RIGHT,ALU1 +S 1300,300,1300,1600,100,*,DOWN,NTRANS +S 700,300,700,1600,100,*,DOWN,NTRANS +S 400,500,400,1400,300,*,UP,NDIF +S 1600,500,1600,1400,300,*,UP,NDIF +S 0,5000,2000,5000,300,*,RIGHT,NTIE +S 0,0,2000,0,300,*,RIGHT,PTIE +S 1300,2500,1500,2500,200,*,RIGHT,POLY +S 500,2500,700,2500,200,*,RIGHT,POLY +B 1450,2500,300,200,CONT_TURN8,* +B 550,2500,300,200,CONT_TURN8,* +V 1000,4400,CONT_DIF_P,* +V 1000,3700,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 1500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/na2_x1.vbe b/pdks/symbolic/lsxlib/cells/na2_x1.vbe new file mode 100644 index 000000000..486b6aaf0 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 59; + CONSTANT tphl_i1_nq : NATURAL := 111; + CONSTANT tplh_i1_nq : NATURAL := 234; + CONSTANT tplh_i0_nq : NATURAL := 288; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x1; + +ARCHITECTURE behaviour_data_flow OF na2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x1" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 900 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/na2_x4.ap b/pdks/symbolic/lsxlib/cells/na2_x4.ap new file mode 100644 index 000000000..849c12e1e --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na2_x4.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H na2_x4,P, 1/ 8/2024,100 +A 0,0,4000,5000 +S 0,1100,4000,1100,1400,*,RIGHT,PWELL +S 1000,500,1000,1200,300,*,DOWN,NDIF +S 3300,700,3300,4400,200,*,UP,ALU1 +S 3700,1100,3700,3400,100,*,DOWN,POLY +S 3100,3400,3700,3400,100,*,RIGHT,POLY +S 3400,3600,3400,4500,300,*,DOWN,PDIF +S 3100,3400,3100,4700,100,*,DOWN,PTRANS +S 3300,4400,3400,4400,200,*,RIGHT,ALU1 +S 3300,3700,3400,3700,200,*,RIGHT,ALU1 +S 3100,1100,3700,1100,100,*,LEFT,POLY +S 3400,500,3400,900,300,*,DOWN,NDIF +S 3100,300,3100,1100,100,*,UP,NTRANS +S 1000,3400,1600,3400,200,*,RIGHT,ALU1 +S 1000,1500,1600,1500,200,*,RIGHT,ALU1 +S 1300,300,1300,1400,100,*,DOWN,NTRANS +S 700,300,700,1400,100,*,DOWN,NTRANS +S 400,500,400,1200,300,*,UP,NDIF +S 1100,1500,1100,2400,100,*,UP,POLY +S 1100,1500,1300,1500,100,*,LEFT,POLY +S 1300,1400,1300,1500,100,*,DOWN,POLY +S 700,1400,700,3600,100,*,UP,POLY +S 1300,3600,1300,4700,100,*,UP,PTRANS +S 700,3600,700,4700,100,*,UP,PTRANS +S 400,3800,400,4500,300,*,DOWN,PDIF +S 1000,3800,1000,4500,300,*,DOWN,PDIF +S 2500,2400,2500,4700,100,*,DOWN,PTRANS +S 1900,2400,1900,4700,100,*,DOWN,PTRANS +S 2200,2600,2200,4500,300,*,DOWN,PDIF +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 2800,2600,2800,4500,300,*,UP,PDIF +S 1900,300,1900,1600,100,*,UP,NTRANS +S 2500,300,2500,1600,100,*,UP,NTRANS +S 1600,500,1600,1400,300,*,UP,NDIF +S 2800,500,2800,1400,300,*,DOWN,NDIF +S 2200,500,2200,1400,300,*,DOWN,NDIF +S 1600,2000,3700,2000,100,*,RIGHT,POLY +S 1900,2400,3300,2400,100,*,RIGHT,POLY +S 1300,2400,1300,3600,100,*,DOWN,POLY +S 600,2000,700,2000,200,*,RIGHT,POLY +S 1900,1600,3300,1600,100,*,RIGHT,POLY +S 1100,2400,1300,2400,100,*,LEFT,POLY +S 1600,0,1600,1000,200,*,DOWN,ALU1 +S 2800,0,2800,1300,200,*,DOWN,ALU1 +S 1100,2000,1100,2900,200,i1,DOWN,CALU1 +S 1600,1500,1600,3400,200,*,UP,ALU1 +S 1000,600,1000,1500,200,*,UP,ALU1 +S 1600,3900,1600,5000,200,*,UP,ALU1 +S 1000,3400,1000,4400,200,*,DOWN,ALU1 +S 2800,2700,2800,5000,200,*,UP,ALU1 +S 400,1100,400,3900,200,i0,DOWN,CALU1 +S 400,2000,600,2000,200,*,LEFT,ALU1 +S 3300,700,3400,700,200,*,LEFT,ALU1 +S 400,600,1000,600,200,*,RIGHT,ALU1 +S 400,4400,400,5000,200,*,UP,ALU1 +S 2200,600,2200,4400,200,nq,UP,CALU1 +S 0,5000,4000,5000,300,*,RIGHT,NTIE +S 0,5000,4000,5000,400,vdd,RIGHT,CALU1 +S 0,4000,4000,4000,1200,*,RIGHT,NWELL +S 0,3100,4000,3100,1200,*,RIGHT,NWELL +S 0,0,4000,0,300,*,RIGHT,PTIE +S 0,0,4000,0,400,vss,RIGHT,CALU1 +B 1100,2000,200,200,CONT_TURN8,* +B 600,2000,200,200,CONT_TURN8,* +B 3300,4400,200,200,CONT_TURN1,* +B 3300,700,200,200,CONT_TURN1,* +B 1600,3400,200,200,CONT_TURN1,* +B 1600,1500,200,200,CONT_TURN1,* +B 1000,600,200,200,CONT_TURN1,* +B 1000,1500,200,200,CONT_TURN1,* +B 1000,3400,200,200,CONT_TURN1,* +V 3400,3700,CONT_DIF_P,* +V 3400,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 2800,2700,CONT_DIF_P,* +V 2800,3200,CONT_DIF_P,* +V 1600,3900,CONT_DIF_P,* +V 1000,3900,CONT_DIF_P,* +V 2200,2700,CONT_DIF_P,* +V 2200,4400,CONT_DIF_P,* +V 2800,4400,CONT_DIF_P,* +V 2200,3800,CONT_DIF_P,* +V 2200,3200,CONT_DIF_P,* +V 2800,3800,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 1600,1000,CONT_DIF_N,* +V 3400,700,CONT_DIF_N,* +V 2800,1300,CONT_DIF_N,* +V 2800,600,CONT_DIF_N,* +V 2200,600,CONT_DIF_N,* +V 2200,1300,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 1100,2000,CONT_POLY,* +V 1600,2000,CONT_POLY,* +V 3300,2400,CONT_POLY,* +V 3300,1600,CONT_POLY,* +V 600,2000,CONT_POLY,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/na2_x4.vbe b/pdks/symbolic/lsxlib/cells/na2_x4.vbe new file mode 100644 index 000000000..c73eca058 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 353; + CONSTANT tphl_i0_nq : NATURAL := 412; + CONSTANT tplh_i0_nq : NATURAL := 552; + CONSTANT tplh_i1_nq : NATURAL := 601; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x4; + +ARCHITECTURE behaviour_data_flow OF na2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x4" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/na3_x1.ap b/pdks/symbolic/lsxlib/cells/na3_x1.ap new file mode 100644 index 000000000..bfa137533 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na3_x1.ap @@ -0,0 +1,67 @@ +V ALLIANCE : 6 +H na3_x1,P, 1/ 8/2024,100 +A 0,0,2500,5000 +S 0,1100,2500,1100,1400,*,RIGHT,PWELL +S 1000,500,1000,1700,300,*,DOWN,NDIF +S 1900,1900,1900,3400,100,*,DOWN,POLY +S 1300,1900,1300,3400,100,*,DOWN,POLY +S 700,1900,700,3400,100,*,UP,POLY +S 1900,300,1900,1900,100,*,DOWN,NTRANS +S 700,300,700,1900,100,*,DOWN,NTRANS +S 1300,300,1300,1900,100,*,DOWN,NTRANS +S 1600,500,1600,1700,300,*,UP,NDIF +S 2200,500,2200,1700,300,*,UP,NDIF +S 400,500,400,1700,300,*,UP,NDIF +S 0,4000,2500,4000,1200,*,RIGHT,NWELL +S 0,3100,2500,3100,1200,*,RIGHT,NWELL +S 2200,3900,2200,4400,200,*,DOWN,ALU1 +S 1000,3900,2200,3900,200,*,RIGHT,ALU1 +S 0,0,2500,0,400,vss,RIGHT,CALU1 +S 0,5000,2500,5000,400,vdd,RIGHT,CALU1 +S 0,5000,2500,5000,300,*,RIGHT,NTIE +S 0,0,2500,0,300,*,RIGHT,PTIE +S 1900,3400,1900,4700,100,*,UP,PTRANS +S 2200,3600,2200,4500,300,*,DOWN,PDIF +S 1600,3600,1600,4500,300,*,DOWN,PDIF +S 1300,3400,1300,4700,100,*,UP,PTRANS +S 1000,3600,1000,4500,300,*,DOWN,PDIF +S 700,3400,700,4700,100,*,UP,PTRANS +S 1900,2500,2100,2500,200,*,RIGHT,POLY +S 1300,2500,1500,2500,200,*,RIGHT,POLY +S 500,2500,700,2500,200,*,RIGHT,POLY +S 1000,600,2200,600,200,*,RIGHT,ALU1 +S 1500,1100,1500,3400,200,i1,DOWN,CALU1 +S 2100,1100,2100,3400,200,i2,DOWN,CALU1 +S 500,1100,500,3900,200,i0,DOWN,CALU1 +S 400,4400,400,5000,200,*,UP,ALU1 +S 1600,4400,1600,5000,200,*,UP,ALU1 +S 1000,600,1000,4400,200,nq,DOWN,CALU1 +S 400,3600,400,4500,300,*,DOWN,PDIF +S 400,0,400,600,200,*,DOWN,ALU1 +B 2050,2500,300,200,CONT_TURN8,* +B 1450,2500,300,200,CONT_TURN8,* +B 550,2500,300,200,CONT_TURN8,* +B 2200,3900,200,200,CONT_TURN1,* +V 2500,0,CONT_BODY_P,* +V 2500,5000,CONT_BODY_N,* +V 2200,4400,CONT_DIF_P,* +V 1000,3700,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 2200,600,CONT_DIF_N,* +V 1500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 2100,2500,CONT_POLY,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 400,4400,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/na3_x1.vbe b/pdks/symbolic/lsxlib/cells/na3_x1.vbe new file mode 100644 index 000000000..d51e12075 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 4120; + CONSTANT rdown_i1_nq : NATURAL := 4120; + CONSTANT rdown_i2_nq : NATURAL := 4120; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 119; + CONSTANT tphl_i1_nq : NATURAL := 171; + CONSTANT tphl_i2_nq : NATURAL := 193; + CONSTANT tplh_i2_nq : NATURAL := 265; + CONSTANT tplh_i1_nq : NATURAL := 316; + CONSTANT tplh_i0_nq : NATURAL := 363; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x1; + +ARCHITECTURE behaviour_data_flow OF na3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/na3_x4.ap b/pdks/symbolic/lsxlib/cells/na3_x4.ap new file mode 100644 index 000000000..bb43b9d70 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na3_x4.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H na3_x4,P, 1/ 8/2024,100 +A 0,0,4500,5000 +S 0,1100,4500,1100,1400,*,RIGHT,PWELL +S 4200,1100,4200,3400,100,*,DOWN,POLY +S 300,2000,600,2000,100,*,RIGHT,POLY +S 3800,600,3800,4400,200,*,UP,ALU1 +S 300,3900,300,4400,200,*,DOWN,ALU1 +S 3600,3400,4200,3400,100,*,RIGHT,POLY +S 3900,3600,3900,4500,300,*,DOWN,PDIF +S 3600,3400,3600,4700,100,*,DOWN,PTRANS +S 3800,3700,3900,3700,200,*,RIGHT,ALU1 +S 3800,4400,3900,4400,200,*,RIGHT,ALU1 +S 3900,500,3900,900,300,*,DOWN,NDIF +S 3600,1100,4200,1100,100,*,LEFT,POLY +S 3800,600,3900,600,200,*,LEFT,ALU1 +S 3600,300,3600,1100,100,*,UP,NTRANS +S 1500,3400,2100,3400,200,*,RIGHT,ALU1 +S 1500,1500,2100,1500,200,*,RIGHT,ALU1 +S 1500,600,1500,1500,200,*,UP,ALU1 +S 600,300,600,1800,100,*,UP,NTRANS +S 1100,300,1100,1800,100,*,DOWN,NTRANS +S 1600,300,1600,1800,100,*,DOWN,NTRANS +S 2000,500,2000,1600,300,*,UP,NDIF +S 300,500,300,1600,300,*,UP,NDIF +S 1600,1800,1600,2400,100,*,UP,POLY +S 1100,1800,1100,2000,100,*,UP,POLY +S 600,1800,600,3600,100,*,DOWN,POLY +S 2000,0,2000,1000,200,*,DOWN,ALU1 +S 1200,2000,1200,3600,100,*,UP,POLY +S 1800,2400,1800,3600,100,*,DOWN,POLY +S 300,3800,300,4500,300,*,DOWN,PDIF +S 1200,3600,1200,4700,100,*,UP,PTRANS +S 900,3800,900,4500,300,*,DOWN,PDIF +S 1500,3800,1500,4500,300,*,DOWN,PDIF +S 600,3600,600,4700,100,*,DOWN,PTRANS +S 1800,3600,1800,4700,100,*,UP,PTRANS +S 300,600,1500,600,200,*,RIGHT,ALU1 +S 1600,2000,1600,2900,200,i2,DOWN,CALU1 +S 1100,2000,1200,2000,200,*,RIGHT,POLY +S 900,2000,1100,2000,200,*,LEFT,ALU1 +S 900,1100,900,3400,200,i1,DOWN,CALU1 +S 300,1100,300,3400,200,i0,DOWN,CALU1 +S 0,4000,4500,4000,1200,*,RIGHT,NWELL +S 0,3100,4500,3100,1200,*,RIGHT,NWELL +S 0,5000,4500,5000,300,*,RIGHT,NTIE +S 0,5000,4500,5000,400,vdd,RIGHT,CALU1 +S 0,0,4500,0,300,*,RIGHT,PTIE +S 0,0,4500,0,400,vss,RIGHT,CALU1 +S 3300,2600,3300,4500,300,*,UP,PDIF +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 2400,2400,2400,4700,100,*,DOWN,PTRANS +S 3000,2400,3000,4700,100,*,DOWN,PTRANS +S 3000,300,3000,1600,100,*,UP,NTRANS +S 2400,300,2400,1600,100,*,UP,NTRANS +S 3300,500,3300,1400,300,*,DOWN,NDIF +S 2700,500,2700,1400,300,*,DOWN,NDIF +S 1600,2400,1800,2400,100,*,LEFT,POLY +S 2400,1600,3800,1600,100,*,RIGHT,POLY +S 2400,2400,3800,2400,100,*,RIGHT,POLY +S 2100,2000,4200,2000,100,*,RIGHT,POLY +S 3300,0,3300,1300,200,*,DOWN,ALU1 +S 300,3900,1500,3900,200,*,RIGHT,ALU1 +S 900,4400,900,5000,200,*,UP,ALU1 +S 3300,2700,3300,5000,200,*,UP,ALU1 +S 1500,3400,1500,4400,200,*,DOWN,ALU1 +S 2100,3900,2100,5000,200,*,UP,ALU1 +S 2100,1500,2100,3400,200,*,UP,ALU1 +S 2700,600,2700,4400,200,nq,UP,CALU1 +B 1100,2000,200,200,CONT_TURN8,* +B 1600,2000,200,200,CONT_TURN8,* +B 400,2000,400,200,CONT_TURN8,* +B 3800,600,200,200,CONT_TURN1,* +B 3800,4400,200,200,CONT_TURN1,* +B 2100,3400,200,200,CONT_TURN1,* +B 2100,1500,200,200,CONT_TURN1,* +B 1500,600,200,200,CONT_TURN1,* +B 1500,1500,200,200,CONT_TURN1,* +B 1500,3400,200,200,CONT_TURN1,* +V 3900,3700,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 3900,600,CONT_DIF_N,* +V 1500,3900,CONT_DIF_P,* +V 2000,1000,CONT_DIF_N,* +V 2000,600,CONT_DIF_N,* +V 1100,2000,CONT_POLY,* +V 300,3900,CONT_DIF_P,* +V 300,2000,CONT_POLY,* +V 4500,5000,CONT_BODY_N,* +V 4500,0,CONT_BODY_P,* +V 300,4400,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 2700,2700,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 3300,3200,CONT_DIF_P,* +V 3300,2700,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 3300,3800,CONT_DIF_P,* +V 2700,3200,CONT_DIF_P,* +V 2700,3800,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 2700,1300,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 3300,600,CONT_DIF_N,* +V 3300,1300,CONT_DIF_N,* +V 3800,1600,CONT_POLY,* +V 3800,2400,CONT_POLY,* +V 2100,2000,CONT_POLY,* +V 1600,2000,CONT_POLY,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/na3_x4.vbe b/pdks/symbolic/lsxlib/cells/na3_x4.vbe new file mode 100644 index 000000000..160a97f61 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 460; + CONSTANT tphl_i2_nq : NATURAL := 519; + CONSTANT tphl_i0_nq : NATURAL := 556; + CONSTANT tplh_i0_nq : NATURAL := 601; + CONSTANT tplh_i2_nq : NATURAL := 647; + CONSTANT tplh_i1_nq : NATURAL := 691; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x4; + +ARCHITECTURE behaviour_data_flow OF na3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/na4_x1.ap b/pdks/symbolic/lsxlib/cells/na4_x1.ap new file mode 100644 index 000000000..af6981de3 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na4_x1.ap @@ -0,0 +1,85 @@ +V ALLIANCE : 6 +H na4_x1,P, 1/ 8/2024,100 +A 0,0,3000,5000 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 1500,500,1500,1700,300,*,DOWN,NDIF +S 2700,4000,2700,4400,200,*,DOWN,ALU1 +S 300,4000,300,4400,200,*,UP,ALU1 +S 2600,1100,2600,3400,200,i3,DOWN,CALU1 +S 2000,1100,2000,3400,200,i2,DOWN,CALU1 +S 1000,600,1000,3400,200,i1,DOWN,CALU1 +S 400,2100,400,3400,200,i0,DOWN,CALU1 +S 300,3900,2700,3900,200,*,RIGHT,ALU1 +S 600,1900,600,3700,100,*,UP,POLY +S 2400,1900,2400,3700,100,*,DOWN,POLY +S 1800,1900,1800,3700,100,*,DOWN,POLY +S 1200,1900,1200,3700,100,*,UP,POLY +S 300,3900,300,4500,300,*,DOWN,PDIF +S 1200,3700,1200,4700,100,*,UP,PTRANS +S 1500,3900,1500,4500,300,*,DOWN,PDIF +S 1800,3700,1800,4700,100,*,UP,PTRANS +S 2100,3900,2100,4500,300,*,DOWN,PDIF +S 2700,3900,2700,4500,300,*,DOWN,PDIF +S 2400,3700,2400,4700,100,*,UP,PTRANS +S 900,3900,900,4500,300,*,DOWN,PDIF +S 600,3700,600,4700,100,*,DOWN,PTRANS +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 0,5000,3000,5000,300,*,RIGHT,NTIE +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +S 0,0,3000,0,300,*,RIGHT,PTIE +S 0,0,3000,0,400,vss,RIGHT,CALU1 +S 400,2500,600,2500,200,*,RIGHT,POLY +S 300,0,300,1600,200,*,DOWN,ALU1 +S 300,500,300,1700,300,*,DOWN,NDIF +S 600,300,600,1900,100,*,DOWN,NTRANS +S 2400,300,2400,1900,100,*,DOWN,NTRANS +S 1200,300,1200,1900,100,*,DOWN,NTRANS +S 1800,300,1800,1900,100,*,DOWN,NTRANS +S 2700,500,2700,1700,300,*,UP,NDIF +S 900,500,900,1700,300,*,UP,NDIF +S 2100,500,2100,1700,300,*,UP,NDIF +S 2400,2500,2600,2500,200,*,RIGHT,POLY +S 1800,2500,2000,2500,200,*,RIGHT,POLY +S 1000,2500,1200,2500,200,*,RIGHT,POLY +S 900,4400,900,5000,200,*,UP,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 1500,600,1500,4400,200,nq,DOWN,CALU1 +S 1500,600,2700,600,200,*,RIGHT,ALU1 +B 2550,2500,300,200,CONT_TURN8,* +B 1950,2500,300,200,CONT_TURN8,* +B 1050,2500,300,200,CONT_TURN8,* +B 450,2500,300,200,CONT_TURN8,* +B 2700,3900,200,200,CONT_TURN1,* +B 300,3900,200,200,CONT_TURN1,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 3000,0,CONT_BODY_P,* +V 3000,5000,CONT_BODY_N,* +V 400,2500,CONT_POLY,* +V 300,4400,CONT_DIF_P,* +V 300,1100,CONT_DIF_N,* +V 300,1600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 900,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 2700,600,CONT_DIF_N,* +V 2000,2500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 2600,2500,CONT_POLY,* +V 2500,0,CONT_BODY_P,* +V 2500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/na4_x1.vbe b/pdks/symbolic/lsxlib/cells/na4_x1.vbe new file mode 100644 index 000000000..07f51ce0b --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 5400; + CONSTANT rdown_i1_nq : NATURAL := 5400; + CONSTANT rdown_i2_nq : NATURAL := 5400; + CONSTANT rdown_i3_nq : NATURAL := 5400; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT rup_i3_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 179; + CONSTANT tphl_i1_nq : NATURAL := 237; + CONSTANT tphl_i2_nq : NATURAL := 269; + CONSTANT tphl_i3_nq : NATURAL := 282; + CONSTANT tplh_i3_nq : NATURAL := 302; + CONSTANT tplh_i2_nq : NATURAL := 350; + CONSTANT tplh_i1_nq : NATURAL := 395; + CONSTANT tplh_i0_nq : NATURAL := 438; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x1; + +ARCHITECTURE behaviour_data_flow OF na4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/na4_x4.ap b/pdks/symbolic/lsxlib/cells/na4_x4.ap new file mode 100644 index 000000000..1bb2fda98 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na4_x4.ap @@ -0,0 +1,153 @@ +V ALLIANCE : 6 +H na4_x4,P, 5/ 8/2024,100 +A 0,0,5000,5000 +S 1700,2000,1800,2000,200,*,LEFT,POLY2 +S 2200,2000,2400,2000,200,*,RIGHT,POLY2 +S 0,1100,5000,1100,1400,*,RIGHT,PWELL +S 4400,600,4400,4400,200,*,UP,ALU1 +S 4800,1100,4800,3400,100,*,DOWN,POLY +S 4500,3600,4500,4500,300,*,DOWN,PDIF +S 4200,3400,4200,4700,100,*,DOWN,PTRANS +S 4200,3400,4800,3400,100,*,RIGHT,POLY +S 4400,3700,4500,3700,200,*,RIGHT,ALU1 +S 4400,4400,4500,4400,200,*,RIGHT,ALU1 +S 4200,300,4200,1100,100,*,UP,NTRANS +S 4500,500,4500,900,300,*,DOWN,NDIF +S 4200,1100,4800,1100,100,*,LEFT,POLY +S 4400,600,4500,600,200,*,LEFT,ALU1 +S 600,2000,600,3400,200,i0,DOWN,CALU1 +S 1100,1100,1100,3400,200,i1,DOWN,CALU1 +S 1600,1100,1600,3400,200,i2,DOWN,CALU1 +S 2200,3400,2200,3900,200,*,DOWN,ALU1 +S 2100,3900,2100,4400,200,*,DOWN,ALU1 +S 900,3900,900,4400,200,*,DOWN,ALU1 +S 900,3900,2200,3900,200,*,RIGHT,ALU1 +S 300,600,300,1500,200,*,DOWN,ALU1 +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +S 0,0,5000,0,300,*,RIGHT,PTIE +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 300,3900,300,4500,300,*,DOWN,PDIF +S 300,500,300,1700,300,*,UP,NDIF +S 2400,3700,2400,4700,100,*,UP,PTRANS +S 1200,3700,1200,4700,100,*,DOWN,PTRANS +S 2100,3900,2100,4500,300,*,DOWN,PDIF +S 1500,3900,1500,4500,300,*,DOWN,PDIF +S 1800,3700,1800,4700,100,*,UP,PTRANS +S 900,3900,900,4500,300,*,DOWN,PDIF +S 600,3700,600,4700,100,*,DOWN,PTRANS +S 3900,2600,3900,4500,300,*,UP,PDIF +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 3300,2600,3300,4500,300,*,DOWN,PDIF +S 3000,2400,3000,4700,100,*,DOWN,PTRANS +S 3600,2400,3600,4700,100,*,DOWN,PTRANS +S 1700,300,1700,1900,100,*,DOWN,NTRANS +S 1200,300,1200,1900,100,*,UP,NTRANS +S 600,300,600,1900,100,*,UP,NTRANS +S 3600,300,3600,1600,100,*,UP,NTRANS +S 3000,300,3000,1600,100,*,UP,NTRANS +S 2200,300,2200,1900,100,*,DOWN,NTRANS +S 2600,500,2600,1700,300,*,UP,NDIF +S 900,500,900,1700,300,*,UP,NDIF +S 3900,500,3900,1400,300,*,DOWN,NDIF +S 3300,500,3300,1400,300,*,DOWN,NDIF +S 2200,1900,2200,2000,100,*,UP,POLY +S 600,1900,600,3700,100,*,DOWN,POLY +S 1200,1900,1200,3700,100,*,DOWN,POLY +S 1700,1900,1700,2000,100,*,UP,POLY +S 1700,2000,1800,2000,200,*,LEFT,POLY +S 2800,2000,4800,2000,100,*,RIGHT,POLY +S 2400,2000,2400,3700,100,*,DOWN,POLY +S 2200,2000,2400,2000,200,*,RIGHT,POLY +S 1800,2000,1800,3700,100,*,UP,POLY +S 3000,1600,4400,1600,100,*,RIGHT,POLY +S 3000,2400,4400,2400,100,*,RIGHT,POLY +S 2600,0,2600,1000,200,*,DOWN,ALU1 +S 3900,0,3900,1300,200,*,DOWN,ALU1 +S 2300,2000,2300,2900,200,i3,DOWN,CALU1 +S 2100,600,2100,1500,200,*,UP,ALU1 +S 300,4000,300,5000,200,*,UP,ALU1 +S 2200,3400,2800,3400,200,*,RIGHT,ALU1 +S 1600,2000,1800,2000,200,*,LEFT,ALU1 +S 2800,1500,2800,3400,200,*,UP,ALU1 +S 2100,1500,2800,1500,200,*,RIGHT,ALU1 +S 2700,3900,2700,5000,200,*,UP,ALU1 +S 3300,600,3300,4400,200,nq,UP,CALU1 +S 1500,4400,1500,5000,200,*,UP,ALU1 +S 300,600,2100,600,200,*,RIGHT,ALU1 +S 3900,2700,3900,5000,200,*,UP,ALU1 +B 600,2000,200,200,CONT_TURN8,* +B 1100,2000,200,200,CONT_TURN8,* +B 2300,2000,200,200,CONT_TURN8,* +B 1800,2000,200,200,CONT_TURN8,* +B 1800,2000,200,200,CONT_TURN3,* +B 4400,600,200,200,CONT_TURN1,* +B 4400,4400,200,200,CONT_TURN1,* +B 2100,600,200,200,CONT_TURN1,* +B 2100,1500,200,200,CONT_TURN1,* +B 2800,1500,200,200,CONT_TURN1,* +B 2800,3400,200,200,CONT_TURN1,* +B 2200,3400,200,200,CONT_TURN1,* +B 2200,3900,200,200,CONT_TURN1,* +B 900,3900,200,200,CONT_TURN1,* +V 4500,4400,CONT_DIF_P,* +V 4500,3700,CONT_DIF_P,* +V 4500,600,CONT_DIF_N,* +V 5000,0,CONT_BODY_P,* +V 5000,5000,CONT_BODY_N,* +V 2100,4000,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 3300,3200,CONT_DIF_P,* +V 3300,3800,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 3300,2700,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 3900,3200,CONT_DIF_P,* +V 3900,2700,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 3900,3800,CONT_DIF_P,* +V 2600,1000,CONT_DIF_N,* +V 2600,600,CONT_DIF_N,* +V 3300,1300,CONT_DIF_N,* +V 3300,600,CONT_DIF_N,* +V 3900,600,CONT_DIF_N,* +V 3900,1300,CONT_DIF_N,* +V 1800,2000,CONT_POLY,* +V 1100,2000,CONT_POLY,* +V 600,2000,CONT_POLY,* +V 2800,2000,CONT_POLY,* +V 2300,2000,CONT_POLY,* +V 4400,1600,CONT_POLY,* +V 4400,2400,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 300,1100,CONT_DIF_N,* +V 300,1500,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 4500,5000,CONT_BODY_N,* +V 4500,0,CONT_BODY_P,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/na4_x4.vbe b/pdks/symbolic/lsxlib/cells/na4_x4.vbe new file mode 100644 index 000000000..a67d18901 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/na4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 578; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i3_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 681; + CONSTANT tplh_i2_nq : NATURAL := 689; + CONSTANT tphl_i3_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 731; + CONSTANT tplh_i0_nq : NATURAL := 771; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x4; + +ARCHITECTURE behaviour_data_flow OF na4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/nao22_x1.ap b/pdks/symbolic/lsxlib/cells/nao22_x1.ap new file mode 100644 index 000000000..ce5077f8d --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nao22_x1.ap @@ -0,0 +1,68 @@ +V ALLIANCE : 6 +H nao22_x1,P, 1/ 8/2024,100 +A 0,0,2500,5000 +S 0,1100,2500,1100,1400,*,RIGHT,PWELL +S 2000,1100,2000,3900,200,i2,DOWN,CALU1 +S 400,1100,400,3900,200,i0,DOWN,CALU1 +S 1800,1600,1800,2400,100,*,DOWN,POLY +S 1200,1600,1200,2400,100,*,DOWN,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +S 0,0,2500,0,300,*,RIGHT,PTIE +S 0,0,2500,0,400,vss,LEFT,CALU1 +S 0,5000,2500,5000,300,*,RIGHT,NTIE +S 0,5000,2500,5000,400,vdd,RIGHT,CALU1 +S 0,4000,2500,4000,1200,*,RIGHT,NWELL +S 0,3100,2500,3100,1200,*,RIGHT,NWELL +S 1500,1100,1500,4400,200,nq,DOWN,CALU1 +S 900,1100,1500,1100,200,*,RIGHT,ALU1 +S 400,2000,600,2000,200,*,RIGHT,POLY +S 1000,1600,1000,4400,200,i1,DOWN,CALU1 +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 300,2600,300,4500,300,*,DOWN,PDIF +S 600,2400,600,4700,100,*,UP,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 900,500,900,1400,300,*,UP,NDIF +S 2100,0,2100,600,200,*,UP,ALU1 +S 300,600,1500,600,200,*,RIGHT,ALU1 +S 600,300,600,1600,100,*,DOWN,NTRANS +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 2100,500,2100,1400,300,*,UP,NDIF +S 300,500,300,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +S 1800,2000,2000,2000,200,*,RIGHT,POLY +S 1000,2000,1200,2000,200,*,RIGHT,POLY +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +B 1950,2000,300,200,CONT_TURN8,* +B 1050,2000,300,200,CONT_TURN8,* +B 450,2000,300,200,CONT_TURN8,* +V 1500,2700,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 400,2000,CONT_POLY,* +V 900,1100,CONT_DIF_N,* +V 1500,3800,CONT_DIF_P,* +V 1500,3300,CONT_DIF_P,* +V 1500,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nao22_x1.vbe b/pdks/symbolic/lsxlib/cells/nao22_x1.vbe new file mode 100644 index 000000000..13c4e6dec --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nao22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 1790; + CONSTANT tphl_i2_nq : NATURAL := 165; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tplh_i2_nq : NATURAL := 238; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x1; + +ARCHITECTURE behaviour_data_flow OF nao22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 900 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/nao22_x4.ap b/pdks/symbolic/lsxlib/cells/nao22_x4.ap new file mode 100644 index 000000000..80345d8e3 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nao22_x4.ap @@ -0,0 +1,126 @@ +V ALLIANCE : 6 +H nao22_x4,P, 1/ 8/2024,100 +A 0,0,4500,5000 +S 0,1100,4500,1100,1400,*,RIGHT,PWELL +S 3800,600,3800,4400,200,*,UP,ALU1 +S 4200,1100,4200,3400,100,*,DOWN,POLY +S 3900,3600,3900,4500,300,*,DOWN,PDIF +S 3600,3400,3600,4700,100,*,DOWN,PTRANS +S 3600,3400,4200,3400,100,*,RIGHT,POLY +S 3800,3700,3900,3700,200,*,RIGHT,ALU1 +S 3800,4400,3900,4400,200,*,RIGHT,ALU1 +S 3600,300,3600,1100,100,*,UP,NTRANS +S 3900,500,3900,900,300,*,DOWN,NDIF +S 3600,1100,4200,1100,100,*,LEFT,POLY +S 3800,600,3900,600,200,*,LEFT,ALU1 +S 2100,0,2100,600,200,*,DOWN,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 900,3600,900,4500,300,*,DOWN,PDIF +S 1000,1600,1000,4400,200,i1,DOWN,CALU1 +S 1800,1100,1800,3400,100,*,DOWN,POLY +S 1200,1100,1200,3400,100,*,UP,POLY +S 600,1100,600,3400,100,*,DOWN,POLY +S 2200,1100,2200,3900,200,*,UP,ALU1 +S 1600,1600,1600,3400,200,i2,DOWN,CALU1 +S 1500,3900,1500,4400,200,*,UP,ALU1 +S 1500,3900,2200,3900,200,*,LEFT,ALU1 +S 900,1100,2200,1100,200,*,RIGHT,ALU1 +S 2200,2000,4200,2000,100,*,RIGHT,POLY +S 900,500,900,1200,300,*,UP,NDIF +S 400,1100,400,3900,200,i0,DOWN,CALU1 +S 2100,500,2100,1400,300,*,UP,NDIF +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 300,3600,300,4500,300,*,DOWN,PDIF +S 600,3400,600,4700,100,*,UP,PTRANS +S 1200,3400,1200,4700,100,*,UP,PTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 1600,2000,1800,2000,200,*,RIGHT,POLY +S 400,2000,600,2000,200,*,RIGHT,POLY +S 1000,2000,1200,2000,200,*,RIGHT,POLY +S 300,4400,300,5000,200,*,UP,ALU1 +S 300,600,1500,600,200,*,RIGHT,ALU1 +S 300,600,1500,600,200,*,RIGHT,ALU1 +S 1100,2000,1200,2000,200,*,RIGHT,POLY +S 0,4000,4500,4000,1200,*,RIGHT,NWELL +S 0,3100,4500,3100,1200,*,RIGHT,NWELL +S 0,5000,4500,5000,300,*,RIGHT,NTIE +S 0,5000,4500,5000,400,vdd,RIGHT,CALU1 +S 0,0,4500,0,300,*,RIGHT,PTIE +S 0,0,4500,0,400,vss,RIGHT,CALU1 +S 3300,2600,3300,4500,300,*,UP,PDIF +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 2400,2400,2400,4700,100,*,DOWN,PTRANS +S 3000,2400,3000,4700,100,*,DOWN,PTRANS +S 3000,300,3000,1600,100,*,UP,NTRANS +S 2400,300,2400,1600,100,*,UP,NTRANS +S 3300,500,3300,1400,300,*,DOWN,NDIF +S 2700,500,2700,1400,300,*,DOWN,NDIF +S 2400,1600,3800,1600,100,*,RIGHT,POLY +S 2400,2400,3800,2400,100,*,RIGHT,POLY +S 3300,0,3300,1300,200,*,DOWN,ALU1 +S 3300,2700,3300,5000,200,*,UP,ALU1 +S 2700,600,2700,4400,200,nq,UP,CALU1 +B 1650,2000,300,200,CONT_TURN8,* +B 1050,2000,300,200,CONT_TURN8,* +B 450,2000,300,200,CONT_TURN8,* +B 3800,4400,200,200,CONT_TURN1,* +B 3800,600,200,200,CONT_TURN1,* +B 2200,1100,200,200,CONT_TURN1,* +B 2200,3900,200,200,CONT_TURN1,* +V 3900,4400,CONT_DIF_P,* +V 3900,3700,CONT_DIF_P,* +V 3900,600,CONT_DIF_N,* +V 1500,3900,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 2000,5000,CONT_BODY_N,* +V 2100,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2200,2000,CONT_POLY,* +V 2100,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 900,1100,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 400,2000,CONT_POLY,* +V 4500,5000,CONT_BODY_N,* +V 4500,0,CONT_BODY_P,* +V 3300,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 2700,2700,CONT_DIF_P,* +V 3300,3200,CONT_DIF_P,* +V 3300,2700,CONT_DIF_P,* +V 3300,3800,CONT_DIF_P,* +V 2700,3200,CONT_DIF_P,* +V 2700,3800,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 2700,1300,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 3300,600,CONT_DIF_N,* +V 3300,1300,CONT_DIF_N,* +V 3800,1600,CONT_POLY,* +V 3800,2400,CONT_POLY,* +V 1600,2000,CONT_POLY,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nao22_x4.vbe b/pdks/symbolic/lsxlib/cells/nao22_x4.vbe new file mode 100644 index 000000000..ebdcfc515 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 596; + CONSTANT tplh_i2_nq : NATURAL := 636; + CONSTANT tplh_i0_nq : NATURAL := 650; + CONSTANT tphl_i1_nq : NATURAL := 664; + CONSTANT tplh_i1_nq : NATURAL := 723; + CONSTANT tphl_i0_nq : NATURAL := 732; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x4; + +ARCHITECTURE behaviour_data_flow OF nao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/nao2o22_x1.ap b/pdks/symbolic/lsxlib/cells/nao2o22_x1.ap new file mode 100644 index 000000000..4ed23f9c1 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nao2o22_x1.ap @@ -0,0 +1,85 @@ +V ALLIANCE : 6 +H nao2o22_x1,P, 1/ 8/2024,100 +A 0,0,3000,5000 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 300,2100,600,2100,100,*,RIGHT,POLY +S 1000,2100,1000,4400,200,i1,DOWN,CALU1 +S 1000,2100,1200,2100,200,*,RIGHT,POLY +S 1800,2100,2000,2100,200,*,RIGHT,POLY +S 2500,1600,2500,3900,200,i2,DOWN,CALU1 +S 300,1100,300,3900,200,i0,DOWN,CALU1 +S 2000,1600,2000,4400,200,i3,DOWN,CALU1 +S 0,5000,3000,5000,300,*,RIGHT,NTIE +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +S 0,0,3000,0,300,*,RIGHT,PTIE +S 0,0,3000,0,400,vss,RIGHT,CALU1 +S 1500,1600,1500,4400,200,nq,DOWN,CALU1 +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 2400,2400,2400,4700,100,*,UP,PTRANS +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 600,2400,600,4700,100,*,UP,PTRANS +S 300,2600,300,4500,300,*,DOWN,PDIF +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 2400,1600,2400,2400,100,*,DOWN,POLY +S 1800,1600,1800,2400,100,*,DOWN,POLY +S 1200,1600,1200,2400,100,*,DOWN,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +S 900,1100,900,1600,200,nq,DOWN,CALU1 +S 900,1600,1500,1600,200,*,LEFT,ALU1 +S 900,500,900,1400,300,*,UP,NDIF +S 2700,600,2700,1100,200,*,DOWN,ALU1 +S 1500,1100,2700,1100,200,*,RIGHT,ALU1 +S 1500,600,1500,1100,200,*,UP,ALU1 +S 300,600,1500,600,200,*,RIGHT,ALU1 +S 2400,300,2400,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 600,300,600,1600,100,*,DOWN,NTRANS +S 300,500,300,1400,300,*,UP,NDIF +S 2700,500,2700,1400,300,*,UP,NDIF +S 2100,500,2100,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +S 2100,0,2100,600,200,*,UP,ALU1 +S 2700,4400,2700,5000,200,*,UP,ALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +B 2500,2100,200,200,CONT_TURN8,* +B 1950,2100,300,200,CONT_TURN8,* +B 1050,2100,300,200,CONT_TURN8,* +B 400,2100,400,200,CONT_TURN8,* +V 1000,2100,CONT_POLY,* +V 2000,2100,CONT_POLY,* +V 300,2100,CONT_POLY,* +V 2500,2100,CONT_POLY,* +V 1500,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 1500,2800,CONT_DIF_P,* +V 1500,3300,CONT_DIF_P,* +V 1500,3800,CONT_DIF_P,* +V 2700,1100,CONT_DIF_N,* +V 1500,1100,CONT_DIF_N,* +V 900,1100,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nao2o22_x1.vbe b/pdks/symbolic/lsxlib/cells/nao2o22_x1.vbe new file mode 100644 index 000000000..327e99763 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nao2o22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i3_nq : NATURAL := 174; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tphl_i2_nq : NATURAL := 237; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT tplh_i2_nq : NATURAL := 307; + CONSTANT tplh_i3_nq : NATURAL := 382; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x1; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/nao2o22_x4.ap b/pdks/symbolic/lsxlib/cells/nao2o22_x4.ap new file mode 100644 index 000000000..b741d011a --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nao2o22_x4.ap @@ -0,0 +1,145 @@ +V ALLIANCE : 6 +H nao2o22_x4,P, 1/ 8/2024,100 +A 0,0,5500,5000 +S 0,1100,5500,1100,1400,*,RIGHT,PWELL +S 900,500,900,1200,300,*,UP,NDIF +S 300,2100,600,2100,100,*,RIGHT,POLY +S 2500,2100,2500,3900,200,i2,DOWN,CALU1 +S 4500,600,4500,4400,200,nq,UP,CALU1 +S 0,5000,5500,5000,300,*,RIGHT,NTIE +S 0,5000,5500,5000,400,vdd,RIGHT,CALU1 +S 0,0,5500,0,300,*,RIGHT,PTIE +S 0,0,5500,0,400,vss,RIGHT,CALU1 +S 3300,600,3300,4400,200,*,UP,ALU1 +S 2800,1600,3600,1600,100,*,RIGHT,POLY +S 0,4000,5500,4000,1200,*,RIGHT,NWELL +S 0,3100,5500,3100,1200,*,RIGHT,NWELL +S 3600,1100,3600,3400,100,*,UP,POLY +S 3300,3600,3300,4500,300,*,DOWN,PDIF +S 3600,3400,3600,4700,100,*,DOWN,PTRANS +S 3600,300,3600,1100,100,*,UP,NTRANS +S 3300,500,3300,900,300,*,DOWN,NDIF +S 900,1600,2800,1600,200,*,RIGHT,ALU1 +S 3900,2600,3900,4500,300,*,UP,PDIF +S 4800,2400,4800,4700,100,*,DOWN,PTRANS +S 4200,2400,4200,4700,100,*,DOWN,PTRANS +S 4500,2600,4500,4500,300,*,DOWN,PDIF +S 5100,2600,5100,4500,300,*,UP,PDIF +S 4200,300,4200,1600,100,*,UP,NTRANS +S 4800,300,4800,1600,100,*,UP,NTRANS +S 3900,500,3900,1400,300,*,DOWN,NDIF +S 4500,500,4500,1400,300,*,DOWN,NDIF +S 5100,500,5100,1400,300,*,DOWN,NDIF +S 4200,1600,4200,2400,100,*,UP,POLY +S 4800,1600,4800,2400,100,*,DOWN,POLY +S 4000,2100,4800,2100,200,*,RIGHT,POLY +S 3900,0,3900,1300,200,*,DOWN,ALU1 +S 5100,0,5100,1300,200,*,DOWN,ALU1 +S 3300,2100,4000,2100,200,*,RIGHT,ALU1 +S 3900,2700,3900,5000,200,*,UP,ALU1 +S 5100,2700,5100,5000,200,*,UP,ALU1 +S 1500,1600,1500,4400,200,*,DOWN,ALU1 +S 900,1100,900,1600,200,*,UP,ALU1 +S 600,3400,600,4700,100,*,UP,PTRANS +S 300,3600,300,4500,300,*,DOWN,PDIF +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 2700,3600,2700,4500,300,*,DOWN,PDIF +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 2100,3600,2100,4500,300,*,DOWN,PDIF +S 2400,3400,2400,4700,100,*,UP,PTRANS +S 1200,3400,1200,4700,100,*,UP,PTRANS +S 900,3600,900,4500,300,*,DOWN,PDIF +S 2400,1100,2400,3400,100,*,DOWN,POLY +S 600,1100,600,3400,100,*,DOWN,POLY +S 1200,1100,1200,3400,100,*,DOWN,POLY +S 1800,1100,1800,3400,100,*,DOWN,POLY +S 1500,1100,2700,1100,200,*,RIGHT,ALU1 +S 2400,300,2400,1100,100,*,DOWN,NTRANS +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 2700,500,2700,900,300,*,UP,NDIF +S 2100,500,2100,900,300,*,UP,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 2000,2100,2000,4400,200,i3,DOWN,CALU1 +S 1000,2100,1000,4400,200,i1,DOWN,CALU1 +S 1000,2100,1200,2100,200,*,RIGHT,POLY +S 1800,2100,2000,2100,200,*,RIGHT,POLY +S 300,1100,300,3900,200,i0,DOWN,CALU1 +S 2700,600,2700,1100,200,*,DOWN,ALU1 +S 1500,600,1500,1100,200,*,UP,ALU1 +S 300,600,1500,600,200,*,RIGHT,ALU1 +S 2100,0,2100,600,200,*,UP,ALU1 +S 2700,4400,2700,5000,200,*,UP,ALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +B 3150,1600,900,200,CONT_TURN8,* +B 4350,2100,900,200,CONT_TURN8,* +B 2500,2100,200,200,CONT_TURN8,* +B 1950,2100,300,200,CONT_TURN8,* +B 1050,2100,300,200,CONT_TURN8,* +B 400,2100,400,200,CONT_TURN8,* +B 2700,1100,200,200,CONT_TURN1,* +B 1500,1100,200,200,CONT_TURN1,* +B 900,1600,200,200,CONT_TURN1,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5500,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 2800,1600,CONT_POLY,* +V 3300,4400,CONT_DIF_P,* +V 3300,3700,CONT_DIF_P,* +V 3300,600,CONT_DIF_N,* +V 3900,3200,CONT_DIF_P,* +V 3900,2700,CONT_DIF_P,* +V 3900,3800,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 5100,4400,CONT_DIF_P,* +V 4500,3200,CONT_DIF_P,* +V 5100,3800,CONT_DIF_P,* +V 5100,2700,CONT_DIF_P,* +V 5100,3200,CONT_DIF_P,* +V 4500,2700,CONT_DIF_P,* +V 4500,4400,CONT_DIF_P,* +V 4500,3800,CONT_DIF_P,* +V 3900,1300,CONT_DIF_N,* +V 3900,600,CONT_DIF_N,* +V 5100,1300,CONT_DIF_N,* +V 5100,600,CONT_DIF_N,* +V 4500,600,CONT_DIF_N,* +V 4500,1300,CONT_DIF_N,* +V 4000,2100,CONT_POLY,* +V 1000,2100,CONT_POLY,* +V 2000,2100,CONT_POLY,* +V 300,2100,CONT_POLY,* +V 2500,2100,CONT_POLY,* +V 1500,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 1500,3800,CONT_DIF_P,* +V 900,1100,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nao2o22_x4.vbe b/pdks/symbolic/lsxlib/cells/nao2o22_x4.vbe new file mode 100644 index 000000000..b5c506fee --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i3_nq : NATURAL := 607; + CONSTANT tplh_i0_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 664; + CONSTANT tphl_i1_nq : NATURAL := 666; + CONSTANT tplh_i1_nq : NATURAL := 717; + CONSTANT tplh_i2_nq : NATURAL := 721; + CONSTANT tphl_i0_nq : NATURAL := 734; + CONSTANT tplh_i3_nq : NATURAL := 807; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/nmx2_x1.ap b/pdks/symbolic/lsxlib/cells/nmx2_x1.ap new file mode 100644 index 000000000..d3b25b440 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nmx2_x1.ap @@ -0,0 +1,115 @@ +V ALLIANCE : 6 +H nmx2_x1,P, 5/ 8/2024,100 +A 0,0,3500,5000 +S 1600,1600,1700,1600,200,*,LEFT,POLY2 +S 1000,1600,1200,1600,200,*,LEFT,POLY2 +S 2500,2100,2700,2100,200,*,LEFT,POLY2 +S 1500,2100,1700,2100,200,*,RIGHT,POLY2 +S 1000,2500,1000,2600,200,*,DOWN,POLY2 +S 0,1100,3500,1100,1400,*,RIGHT,PWELL +S 2000,600,2100,600,200,*,RIGHT,ALU1 +S 2000,1100,2100,1100,200,*,RIGHT,ALU1 +S 2000,2900,2100,2900,200,*,RIGHT,ALU1 +S 2000,3400,2100,3400,200,*,RIGHT,ALU1 +S 2000,3900,2100,3900,200,*,RIGHT,ALU1 +S 1500,1100,1500,1600,200,*,UP,ALU1 +S 2700,2100,2700,4400,200,*,DOWN,ALU1 +S 2500,2100,2500,2600,100,*,DOWN,POLY +S 2500,2100,2700,2100,200,*,LEFT,POLY +S 300,600,300,4400,200,*,DOWN,ALU1 +S 600,1000,600,3500,100,*,DOWN,POLY +S 300,3700,300,4500,300,*,DOWN,PDIF +S 600,3500,600,4700,100,*,DOWN,PTRANS +S 600,300,600,1000,100,*,UP,NTRANS +S 300,500,300,800,300,*,DOWN,NDIF +S 1500,1600,1600,1600,200,*,LEFT,ALU1 +S 2100,600,2100,3900,200,nq,UP,CALU1 +S 1500,4400,2700,4400,200,*,LEFT,ALU1 +S 600,2100,2100,2100,100,*,LEFT,POLY +S 2100,1500,2100,2100,100,*,UP,POLY +S 2100,1500,2300,1500,100,*,LEFT,POLY +S 2900,2600,3200,2600,100,*,LEFT,POLY +S 3200,1500,3200,2600,100,*,UP,POLY +S 2900,1500,3200,1500,100,*,RIGHT,POLY +S 2300,4300,2300,4600,100,*,DOWN,POLY +S 3200,1100,3200,3900,200,i1,DOWN,CALU1 +S 300,3900,1500,3900,200,*,LEFT,ALU1 +S 1500,3900,1500,4400,200,*,DOWN,ALU1 +S 900,500,900,1300,300,*,UP,NDIF +S 2300,300,2300,1500,100,*,UP,NTRANS +S 1700,300,1700,1500,100,*,UP,NTRANS +S 2900,300,2900,1500,100,*,UP,NTRANS +S 1200,300,1200,1500,100,*,UP,NTRANS +S 2600,500,2600,1300,300,*,DOWN,NDIF +S 2000,500,2000,1300,500,*,DOWN,NDIF +S 3200,500,3200,1300,300,*,UP,NDIF +S 1500,2100,1500,3400,200,cmd,DOWN,CALU1 +S 1000,2500,1000,2600,200,*,DOWN,POLY +S 2300,2600,2500,2600,100,*,RIGHT,POLY +S 1000,2600,1200,2600,100,*,LEFT,POLY +S 1500,2100,1700,2100,200,*,RIGHT,POLY +S 0,4000,3500,4000,1200,*,RIGHT,NWELL +S 0,3100,3500,3100,1200,*,RIGHT,NWELL +S 300,1100,1500,1100,200,*,RIGHT,ALU1 +S 1000,1600,1000,3400,200,i0,DOWN,CALU1 +S 1700,2100,1700,2600,100,*,UP,POLY +S 900,4400,900,5000,200,*,UP,ALU1 +S 3200,4400,3200,5000,200,*,UP,ALU1 +S 900,0,900,600,200,*,DOWN,ALU1 +S 3200,0,3200,600,200,*,DOWN,ALU1 +S 2300,2600,2300,4700,100,*,DOWN,PTRANS +S 2600,2800,2600,4500,300,*,UP,PDIF +S 1700,2600,1700,4700,100,*,DOWN,PTRANS +S 2900,2600,2900,4700,100,*,DOWN,PTRANS +S 3200,2800,3200,4500,300,*,DOWN,PDIF +S 900,2800,900,4500,300,*,DOWN,PDIF +S 1200,2600,1200,4700,100,*,DOWN,PTRANS +S 2000,2800,2000,4500,500,*,DOWN,PDIF +S 0,5000,3500,5000,300,*,RIGHT,NTIE +S 0,5000,3500,5000,400,vdd,RIGHT,CALU1 +S 0,0,3500,0,300,*,RIGHT,PTIE +S 0,0,3500,0,400,vss,RIGHT,CALU1 +B 3200,2100,200,200,CONT_TURN8,* +B 1000,2500,200,200,CONT_TURN8,* +B 2650,2100,300,200,CONT_TURN8,* +B 1550,2100,300,200,CONT_TURN8,* +B 1500,1600,200,200,CONT_TURN1,* +B 1500,1100,200,200,CONT_TURN1,* +B 2700,4400,200,200,CONT_TURN1,* +B 1500,4400,200,200,CONT_TURN1,* +B 1500,3900,200,200,CONT_TURN1,* +V 2700,2100,CONT_POLY,* +V 3200,2100,CONT_POLY,* +V 300,4400,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 300,3800,CONT_DIF_P,* +V 2000,3900,CONT_DIF_P,* +V 2000,600,CONT_DIF_N,* +V 2000,2900,CONT_DIF_P,* +V 2000,1100,CONT_DIF_N,* +V 1600,1600,CONT_POLY,* +V 1500,2100,CONT_POLY,* +V 1000,1600,CONT_POLY,* +V 2000,3400,CONT_DIF_P,* +V 3200,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 3200,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 1000,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nmx2_x1.vbe b/pdks/symbolic/lsxlib/cells/nmx2_x1.vbe new file mode 100644 index 000000000..3f0ab6425 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nmx2_x1.vbe @@ -0,0 +1,40 @@ +ENTITY nmx2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_cmd : NATURAL := 21; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 217; + CONSTANT tphl_i1_nq : NATURAL := 217; + CONSTANT tphl_cmd_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 256; + CONSTANT tplh_i1_nq : NATURAL := 256; + CONSTANT tplh_cmd_nq : NATURAL := 287; + CONSTANT tphh_cmd_nq : NATURAL := 379; + CONSTANT tpll_cmd_nq : NATURAL := 410; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x1; + +ARCHITECTURE behaviour_data_flow OF nmx2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x1" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/nmx2_x4.ap b/pdks/symbolic/lsxlib/cells/nmx2_x4.ap new file mode 100644 index 000000000..7e7140f5a --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nmx2_x4.ap @@ -0,0 +1,166 @@ +V ALLIANCE : 6 +H nmx2_x4,P, 5/ 8/2024,100 +A 0,0,5500,5000 +S 1400,2100,1700,2100,200,*,LEFT,POLY2 +S 2300,3300,2400,3300,200,*,LEFT,POLY2 +S 1400,1600,1700,1600,200,*,RIGHT,POLY2 +S 900,1600,1000,1600,200,*,RIGHT,POLY2 +S 900,3100,900,3200,200,*,UP,POLY2 +S 900,3200,1200,3200,100,*,LEFT,POLY +S 0,1100,5500,1100,1400,*,RIGHT,PWELL +S 1700,2100,1700,3400,100,*,UP,POLY +S 2500,2800,2800,2800,100,*,RIGHT,POLY +S 4800,600,4800,4400,200,*,UP,ALU1 +S 5200,1100,5200,3400,100,*,DOWN,POLY +S 4900,3600,4900,4500,300,*,DOWN,PDIF +S 4600,3400,4600,4700,100,*,DOWN,PTRANS +S 4600,3400,5200,3400,100,*,RIGHT,POLY +S 4800,4400,4900,4400,200,*,RIGHT,ALU1 +S 4800,3700,4900,3700,200,*,RIGHT,ALU1 +S 4600,300,4600,1100,100,*,UP,NTRANS +S 4900,500,4900,900,300,*,DOWN,NDIF +S 4600,1100,5200,1100,100,*,LEFT,POLY +S 4800,600,4900,600,200,*,LEFT,ALU1 +S 0,0,5500,0,300,*,RIGHT,PTIE +S 0,0,5500,0,400,vss,RIGHT,CALU1 +S 0,5000,5500,5000,300,*,RIGHT,NTIE +S 0,4000,5500,4000,1200,*,RIGHT,NWELL +S 0,3100,5500,3100,1200,*,RIGHT,NWELL +S 0,5000,5500,5000,400,vdd,RIGHT,CALU1 +S 3700,600,3700,4400,200,nq,UP,CALU1 +S 2500,1600,2500,2800,200,i1,DOWN,CALU1 +S 3200,1100,3200,2000,200,*,UP,ALU1 +S 2000,600,2000,1100,200,*,UP,ALU1 +S 1900,1100,3200,1100,200,*,RIGHT,ALU1 +S 1900,1100,1900,3900,200,*,UP,ALU1 +S 3100,0,3100,600,200,*,DOWN,ALU1 +S 2300,3300,2400,3300,200,*,RIGHT,POLY +S 2300,3300,2300,3400,100,*,DOWN,POLY +S 1900,3900,2000,3900,200,*,LEFT,ALU1 +S 1400,4400,2500,4400,200,*,LEFT,ALU1 +S 300,3900,1400,3900,200,*,LEFT,ALU1 +S 1400,2100,1400,3400,200,cmd,DOWN,CALU1 +S 1400,3900,1400,4400,200,*,DOWN,ALU1 +S 1200,3200,1200,3400,100,*,DOWN,POLY +S 300,1100,1400,1100,200,*,RIGHT,ALU1 +S 1400,1100,1400,1600,200,*,DOWN,ALU1 +S 1000,1100,1000,1500,100,*,UP,POLY +S 900,1600,900,3400,200,i0,DOWN,CALU1 +S 500,3600,600,3600,100,*,RIGHT,POLY +S 500,1000,500,3600,100,*,UP,POLY +S 500,1000,600,1000,100,*,LEFT,POLY +S 3100,2600,3100,4500,300,*,DOWN,PDIF +S 4300,2600,4300,4500,300,*,UP,PDIF +S 4000,2400,4000,4700,100,*,DOWN,PTRANS +S 3400,2400,3400,4700,100,*,DOWN,PTRANS +S 3700,2600,3700,4500,300,*,DOWN,PDIF +S 4000,300,4000,1600,100,*,UP,NTRANS +S 3400,300,3400,1600,100,*,UP,NTRANS +S 3100,500,3100,1400,300,*,UP,NDIF +S 3700,500,3700,1400,300,*,DOWN,NDIF +S 4300,500,4300,1400,300,*,DOWN,NDIF +S 3200,2000,5200,2000,100,*,RIGHT,POLY +S 3400,2400,4800,2400,100,*,RIGHT,POLY +S 3400,1600,4800,1600,100,*,RIGHT,POLY +S 4300,0,4300,1300,200,*,DOWN,ALU1 +S 3100,3900,3100,5000,200,*,UP,ALU1 +S 4300,2700,4300,5000,200,*,UP,ALU1 +S 2800,3400,2800,4700,100,*,DOWN,PTRANS +S 2800,1100,2800,3400,100,*,DOWN,POLY +S 2800,300,2800,1100,100,*,UP,NTRANS +S 2500,3300,2500,4400,200,*,DOWN,ALU1 +S 2100,1100,2100,2100,100,*,UP,POLY +S 2100,1100,2300,1100,100,*,LEFT,POLY +S 1700,1100,1700,1500,100,*,UP,POLY +S 1000,1100,1200,1100,100,*,RIGHT,POLY +S 300,700,300,4400,200,*,DOWN,ALU1 +S 300,3800,300,4500,300,*,DOWN,PDIF +S 600,3600,600,4700,100,*,DOWN,PTRANS +S 600,300,600,1000,100,*,UP,NTRANS +S 300,500,300,800,300,*,DOWN,NDIF +S 1200,3400,1200,4700,100,*,DOWN,PTRANS +S 900,3600,900,4500,300,*,DOWN,PDIF +S 1700,3400,1700,4700,100,*,DOWN,PTRANS +S 2300,3400,2300,4700,100,*,DOWN,PTRANS +S 2000,3600,2000,4500,500,*,DOWN,PDIF +S 2300,4200,2300,4600,100,*,DOWN,POLY +S 2300,300,2300,1100,100,*,UP,NTRANS +S 1700,300,1700,1100,100,*,UP,NTRANS +S 1200,300,1200,1100,100,*,UP,NTRANS +S 2000,500,2000,900,500,*,DOWN,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 600,2100,2100,2100,100,*,LEFT,POLY +S 900,4400,900,5000,200,*,UP,ALU1 +S 900,0,900,600,200,*,DOWN,ALU1 +B 2400,3300,200,200,CONT_TURN8,* +B 1500,2100,400,200,CONT_TURN8,* +B 2600,2800,400,200,CONT_TURN8,* +B 2500,3300,200,200,CONT_TURN1,* +B 4800,4400,200,200,CONT_TURN1,* +B 4800,600,200,200,CONT_TURN1,* +B 3200,1100,200,200,CONT_TURN1,* +B 1400,1100,200,200,CONT_TURN1,* +B 1900,1100,200,200,CONT_TURN1,* +B 1900,3900,200,200,CONT_TURN1,* +B 2500,4400,200,200,CONT_TURN1,* +B 1400,3900,200,200,CONT_TURN1,* +B 1400,4400,200,200,CONT_TURN1,* +V 4900,3700,CONT_DIF_P,* +V 4900,4400,CONT_DIF_P,* +V 4900,600,CONT_DIF_N,* +V 5500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 5500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 2500,2800,CONT_POLY,* +V 2400,3300,CONT_POLY,* +V 1400,2100,CONT_POLY,* +V 900,3100,CONT_POLY,* +V 1400,1600,CONT_POLY,* +V 900,1600,CONT_POLY,* +V 3700,2700,CONT_DIF_P,* +V 3700,4400,CONT_DIF_P,* +V 4300,4400,CONT_DIF_P,* +V 3700,3800,CONT_DIF_P,* +V 3700,3200,CONT_DIF_P,* +V 4300,3800,CONT_DIF_P,* +V 3100,4400,CONT_DIF_P,* +V 4300,2700,CONT_DIF_P,* +V 4300,3200,CONT_DIF_P,* +V 3100,3900,CONT_DIF_P,* +V 3100,600,CONT_DIF_N,* +V 4300,1300,CONT_DIF_N,* +V 4300,600,CONT_DIF_N,* +V 3700,600,CONT_DIF_N,* +V 3700,1300,CONT_DIF_N,* +V 4800,1600,CONT_POLY,* +V 3200,2000,CONT_POLY,* +V 4800,2400,CONT_POLY,* +V 300,4400,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 2000,3900,CONT_DIF_P,* +V 2000,600,CONT_DIF_N,* +V 300,3900,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 900,600,CONT_DIF_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nmx2_x4.vbe b/pdks/symbolic/lsxlib/cells/nmx2_x4.vbe new file mode 100644 index 000000000..436a6b355 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nmx2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY nmx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_cmd_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 610; + CONSTANT tphl_cmd_nq : NATURAL := 632; + CONSTANT tplh_i0_nq : NATURAL := 653; + CONSTANT tplh_i1_nq : NATURAL := 653; + CONSTANT tphh_cmd_nq : NATURAL := 688; + CONSTANT tpll_cmd_nq : NATURAL := 703; + CONSTANT tplh_cmd_nq : NATURAL := 708; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x4; + +ARCHITECTURE behaviour_data_flow OF nmx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x4" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/nmx3_x1.ap b/pdks/symbolic/lsxlib/cells/nmx3_x1.ap new file mode 100644 index 000000000..20532d31e --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nmx3_x1.ap @@ -0,0 +1,177 @@ +V ALLIANCE : 6 +H nmx3_x1,P, 5/ 8/2024,100 +A 0,0,6000,5000 +S 1600,1100,1700,1100,200,*,LEFT,POLY2 +S 2300,3400,2400,3400,200,*,RIGHT,POLY2 +S 0,1100,6000,1100,1400,*,RIGHT,PWELL +S 900,4400,3200,4400,200,*,RIGHT,ALU1 +S 5600,2700,5600,4500,300,*,UP,PDIF +S 5000,1200,5000,1700,300,*,DOWN,NDIF +S 300,500,300,1400,300,*,DOWN,NDIF +S 2900,1000,2900,3500,100,*,DOWN,POLY +S 2300,2100,2900,2100,100,*,RIGHT,POLY +S 1200,2100,1500,2100,100,*,RIGHT,POLY +S 5600,1100,5600,3900,200,nq,DOWN,CALU1 +S 0,0,6000,0,300,*,RIGHT,PTIE +S 0,0,6000,0,400,vss,RIGHT,CALU1 +S 0,5000,6000,5000,300,*,RIGHT,NTIE +S 0,5000,6000,5000,400,vdd,RIGHT,CALU1 +S 0,4000,6000,4000,1200,*,RIGHT,NWELL +S 0,3100,6000,3100,1200,*,RIGHT,NWELL +S 4500,1600,5100,1600,200,*,LEFT,ALU1 +S 4600,3400,4600,3500,100,*,UP,POLY +S 1200,1000,1200,3500,100,*,DOWN,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +S 4900,600,5000,600,200,*,LEFT,ALU1 +S 5000,600,5000,1100,200,*,UP,ALU1 +S 5000,1100,5600,1100,200,*,RIGHT,ALU1 +S 2300,2900,2300,3400,200,*,UP,ALU1 +S 2100,3900,5600,3900,200,*,RIGHT,ALU1 +S 5600,4400,5600,5000,200,*,UP,ALU1 +S 4500,2100,4500,3400,200,i0,DOWN,CALU1 +S 5600,0,5600,600,200,*,UP,ALU1 +S 5100,1600,5100,2900,200,*,DOWN,ALU1 +S 2800,1100,2800,3900,200,*,UP,ALU1 +S 5300,1600,5300,2500,100,*,DOWN,POLY +S 3900,2500,5300,2500,100,*,RIGHT,POLY +S 5300,2500,5300,3400,100,*,UP,PTRANS +S 5000,2700,5000,3200,300,*,UP,PDIF +S 3800,0,3800,600,200,*,UP,ALU1 +S 3900,1600,3900,3400,200,cmd0,UP,CALU1 +S 3700,1600,3900,1600,100,*,RIGHT,POLY +S 3900,1600,3900,3500,100,*,DOWN,POLY +S 3700,1000,3700,1600,100,*,DOWN,POLY +S 4600,1000,4600,2100,100,*,DOWN,POLY +S 4100,1000,4100,1100,100,*,DOWN,POLY +S 900,600,3200,600,200,*,RIGHT,ALU1 +S 4600,300,4600,1000,100,*,UP,NTRANS +S 3500,300,3500,1000,100,*,UP,NTRANS +S 4100,300,4100,1000,100,*,UP,NTRANS +S 3800,500,3800,800,300,*,DOWN,NDIF +S 4900,500,4900,800,300,*,UP,NDIF +S 3500,1000,3700,1000,100,*,RIGHT,POLY +S 3300,1100,4500,1100,200,*,RIGHT,ALU1 +S 3300,1100,3300,1600,200,*,DOWN,ALU1 +S 5300,1000,5300,1600,100,*,DOWN,NTRANS +S 5600,500,5600,1400,300,*,DOWN,NDIF +S 4500,1100,4500,1600,200,*,DOWN,ALU1 +S 3300,1600,3300,3500,100,*,UP,POLY +S 300,2600,300,4500,300,*,UP,PDIF +S 900,2600,900,3100,300,*,UP,PDIF +S 600,2400,600,3300,100,*,UP,PTRANS +S 4900,3700,4900,4500,300,*,UP,PDIF +S 3800,4400,3800,5000,200,*,UP,ALU1 +S 3900,3500,4100,3500,100,*,LEFT,POLY +S 3300,3500,3500,3500,100,*,RIGHT,POLY +S 2100,3700,2100,4500,300,*,UP,PDIF +S 2400,1000,2400,1700,100,*,UP,POLY +S 4600,3500,4600,4700,100,*,UP,PTRANS +S 2300,1600,2300,2400,200,i1,UP,CALU1 +S 1500,1600,1500,2400,200,i2,UP,CALU1 +S 400,3400,1600,3400,200,*,LEFT,ALU1 +S 400,1100,400,3900,200,cmd1,DOWN,CALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +S 400,2100,600,2100,200,*,RIGHT,POLY +S 300,0,300,600,200,*,DOWN,ALU1 +S 900,1100,900,2900,200,*,UP,ALU1 +S 600,1000,600,1600,100,*,DOWN,NTRANS +S 900,1200,900,1400,300,*,DOWN,NDIF +S 1700,1000,1700,1100,100,*,DOWN,POLY +S 1600,1100,1700,1100,200,*,LEFT,POLY +S 900,1100,1600,1100,200,*,RIGHT,ALU1 +S 1200,300,1200,1000,100,*,UP,NTRANS +S 2400,300,2400,1000,100,*,UP,NTRANS +S 1700,300,1700,1000,100,*,UP,NTRANS +S 2900,300,2900,1000,100,*,UP,NTRANS +S 1500,500,1500,800,300,*,DOWN,NDIF +S 900,500,900,800,300,*,DOWN,NDIF +S 3300,500,3300,800,300,*,DOWN,NDIF +S 1900,1700,1900,2500,100,*,DOWN,POLY +S 1700,2500,1900,2500,100,*,RIGHT,POLY +S 1700,2500,1700,3500,100,*,DOWN,POLY +S 900,2900,2300,2900,200,*,LEFT,ALU1 +S 1900,1700,2400,1700,100,*,RIGHT,POLY +S 1200,3500,1200,4700,100,*,UP,PTRANS +S 1500,3700,1500,4500,300,*,DOWN,PDIF +S 1700,3500,1700,4700,100,*,UP,PTRANS +S 2400,3500,2400,4700,100,*,UP,PTRANS +S 4100,3500,4100,4700,100,*,UP,PTRANS +S 3500,3500,3500,4700,100,*,UP,PTRANS +S 3800,3700,3800,4500,300,*,UP,PDIF +S 3200,3700,3200,4500,300,*,UP,PDIF +S 2900,3500,2900,4700,100,*,UP,PTRANS +S 900,3700,900,4500,300,*,UP,PDIF +S 2100,500,2100,1200,300,*,UP,NDIF +S 2100,1100,2800,1100,200,*,RIGHT,ALU1 +B 2550,2100,700,200,CONT_TURN8,* +B 4600,3400,200,200,CONT_TURN8,* +B 4100,1100,200,200,CONT_TURN8,* +B 1600,1100,200,200,CONT_TURN8,* +B 1600,3400,200,200,CONT_TURN8,* +B 450,2100,300,200,CONT_TURN8,* +B 1400,2100,400,200,CONT_TURN8,* +B 5100,2900,200,200,CONT_TURN1,* +B 5100,1600,200,200,CONT_TURN1,* +B 5000,600,200,200,CONT_TURN1,* +B 5000,1100,200,200,CONT_TURN1,* +B 4500,1600,200,200,CONT_TURN1,* +B 4500,1100,200,200,CONT_TURN1,* +B 3300,1100,200,200,CONT_TURN1,* +B 2800,1100,200,200,CONT_TURN1,* +B 2300,2900,200,200,CONT_TURN1,* +B 900,2900,200,200,CONT_TURN1,* +B 900,1100,200,200,CONT_TURN1,* +V 5500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2300,3400,CONT_POLY,* +V 5600,4400,CONT_DIF_P,* +V 5600,600,CONT_DIF_N,* +V 5000,2900,CONT_DIF_P,* +V 4100,1100,CONT_POLY,* +V 4900,600,CONT_DIF_N,* +V 3800,600,CONT_DIF_N,* +V 3300,1600,CONT_POLY,* +V 5000,1600,CONT_DIF_N,* +V 3200,600,CONT_DIF_N,* +V 900,2700,CONT_DIF_P,* +V 4900,3900,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 4600,2100,CONT_POLY,* +V 4600,3400,CONT_POLY,* +V 3800,4400,CONT_DIF_P,* +V 3200,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 400,2100,CONT_POLY,* +V 300,600,CONT_DIF_N,* +V 900,1300,CONT_DIF_N,* +V 1600,1100,CONT_POLY,* +V 3900,2500,CONT_POLY,* +V 1500,2100,CONT_POLY,* +V 2100,1100,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 1600,3400,CONT_POLY,* +V 2300,2100,CONT_POLY,* +V 5500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nmx3_x1.vbe b/pdks/symbolic/lsxlib/cells/nmx3_x1.vbe new file mode 100644 index 000000000..1853919ce --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nmx3_x1.vbe @@ -0,0 +1,55 @@ +ENTITY nmx3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 7420; + CONSTANT rdown_cmd1_nq : NATURAL := 7420; + CONSTANT rdown_i0_nq : NATURAL := 5140; + CONSTANT rdown_i1_nq : NATURAL := 7420; + CONSTANT rdown_i2_nq : NATURAL := 7420; + CONSTANT rup_cmd0_nq : NATURAL := 9760; + CONSTANT rup_cmd1_nq : NATURAL := 9760; + CONSTANT rup_i0_nq : NATURAL := 6680; + CONSTANT rup_i1_nq : NATURAL := 9760; + CONSTANT rup_i2_nq : NATURAL := 9760; + CONSTANT tphl_i0_nq : NATURAL := 315; + CONSTANT tphl_cmd0_nq : NATURAL := 356; + CONSTANT tphl_cmd1_nq : NATURAL := 414; + CONSTANT tphl_i1_nq : NATURAL := 429; + CONSTANT tphl_i2_nq : NATURAL := 429; + CONSTANT tplh_i0_nq : NATURAL := 441; + CONSTANT tplh_cmd0_nq : NATURAL := 495; + CONSTANT tphh_cmd1_nq : NATURAL := 519; + CONSTANT tpll_cmd1_nq : NATURAL := 520; + CONSTANT tplh_cmd1_nq : NATURAL := 566; + CONSTANT tphh_cmd0_nq : NATURAL := 582; + CONSTANT tplh_i1_nq : NATURAL := 582; + CONSTANT tplh_i2_nq : NATURAL := 582; + CONSTANT tpll_cmd0_nq : NATURAL := 586; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x1; + +ARCHITECTURE behaviour_data_flow OF nmx3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx3_x1" + SEVERITY WARNING; + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not + (cmd1) and i2))))) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/nmx3_x4.ap b/pdks/symbolic/lsxlib/cells/nmx3_x4.ap new file mode 100644 index 000000000..8282e961a --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nmx3_x4.ap @@ -0,0 +1,242 @@ +V ALLIANCE : 6 +H nmx3_x4,P, 5/ 8/2024,100 +A 0,0,8000,5000 +S 4500,3400,4600,3400,200,*,LEFT,POLY2 +S 4500,2100,4600,2100,200,*,RIGHT,POLY2 +S 4500,3400,4500,3500,200,*,UP,POLY2 +S 2300,3400,2400,3400,200,*,LEFT,POLY2 +S 0,1100,8000,1100,1400,*,RIGHT,PWELL +S 900,4400,3200,4400,200,*,RIGHT,ALU1 +S 5000,1200,5000,1700,300,*,DOWN,NDIF +S 300,500,300,1400,300,*,DOWN,NDIF +S 2900,1000,2900,3500,100,*,DOWN,POLY +S 2300,2100,2900,2100,100,*,RIGHT,POLY +S 1200,2100,1500,2100,100,*,RIGHT,POLY +S 7300,600,7300,4400,200,*,UP,ALU1 +S 5000,2900,5100,2900,200,*,LEFT,ALU1 +S 6200,600,6200,4400,200,nq,UP,CALU1 +S 4500,1600,5100,1600,200,*,LEFT,ALU1 +S 1200,1000,1200,3500,100,*,DOWN,POLY +S 7700,1100,7700,3400,100,*,DOWN,POLY +S 7400,3600,7400,4500,300,*,DOWN,PDIF +S 7100,3400,7100,4700,100,*,DOWN,PTRANS +S 7100,3400,7700,3400,100,*,RIGHT,POLY +S 7300,4400,7400,4400,200,*,RIGHT,ALU1 +S 7300,3700,7400,3700,200,*,RIGHT,ALU1 +S 7100,300,7100,1100,100,*,UP,NTRANS +S 7400,500,7400,900,300,*,DOWN,NDIF +S 7100,1100,7700,1100,100,*,LEFT,POLY +S 7300,600,7400,600,200,*,LEFT,ALU1 +S 600,1600,600,2400,100,*,DOWN,POLY +S 5600,2600,5600,4500,300,*,UP,PDIF +S 4500,2100,4600,2100,200,*,LEFT,POLY +S 4500,3400,4500,3500,200,*,DOWN,POLY +S 4500,3500,4600,3500,100,*,RIGHT,POLY +S 3800,1600,3800,3400,200,cmd0,UP,CALU1 +S 0,5000,8000,5000,300,*,RIGHT,NTIE +S 0,4000,8000,4000,1200,*,RIGHT,NWELL +S 0,3100,8000,3100,1200,*,RIGHT,NWELL +S 0,5000,8000,5000,400,vdd,RIGHT,CALU1 +S 0,0,8000,0,300,*,RIGHT,PTIE +S 0,0,8000,0,400,vss,RIGHT,CALU1 +S 5700,2000,7700,2000,100,*,RIGHT,POLY +S 2100,3900,5700,3900,200,*,RIGHT,ALU1 +S 5000,1100,5700,1100,200,*,RIGHT,ALU1 +S 5700,1100,5700,3900,200,*,DOWN,ALU1 +S 6200,2600,6200,4500,300,*,DOWN,PDIF +S 5900,2400,5900,4700,100,*,DOWN,PTRANS +S 6500,2400,6500,4700,100,*,DOWN,PTRANS +S 6800,2600,6800,4500,300,*,UP,PDIF +S 6500,300,6500,1600,100,*,UP,NTRANS +S 5900,300,5900,1600,100,*,UP,NTRANS +S 6200,500,6200,1400,300,*,DOWN,NDIF +S 6800,500,6800,1400,300,*,DOWN,NDIF +S 5900,2400,7300,2400,100,*,RIGHT,POLY +S 5900,1600,7300,1600,100,*,RIGHT,POLY +S 6800,0,6800,1300,200,*,DOWN,ALU1 +S 6800,2700,6800,5000,200,*,UP,ALU1 +S 4900,600,5000,600,200,*,LEFT,ALU1 +S 5000,600,5000,1100,200,*,UP,ALU1 +S 2300,2900,2300,3400,200,*,UP,ALU1 +S 2300,3400,2400,3400,200,*,RIGHT,POLY +S 2400,3400,2400,3600,100,*,UP,POLY +S 5600,4400,5600,5000,200,*,UP,ALU1 +S 4500,2100,4500,3400,200,i0,DOWN,CALU1 +S 5600,0,5600,600,200,*,UP,ALU1 +S 5100,1600,5100,2900,200,*,DOWN,ALU1 +S 2800,1100,2800,3900,200,*,UP,ALU1 +S 5300,1600,5300,2500,100,*,DOWN,POLY +S 3900,2500,5300,2500,100,*,RIGHT,POLY +S 5300,2500,5300,3400,100,*,UP,PTRANS +S 5000,2700,5000,3200,300,*,UP,PDIF +S 3800,0,3800,600,200,*,UP,ALU1 +S 3700,1600,3900,1600,100,*,RIGHT,POLY +S 3900,1600,3900,3500,100,*,DOWN,POLY +S 3700,1000,3700,1600,100,*,DOWN,POLY +S 4600,1000,4600,2100,100,*,DOWN,POLY +S 4100,1000,4100,1100,100,*,DOWN,POLY +S 900,600,3200,600,200,*,RIGHT,ALU1 +S 4600,300,4600,1000,100,*,UP,NTRANS +S 3500,300,3500,1000,100,*,UP,NTRANS +S 4100,300,4100,1000,100,*,UP,NTRANS +S 3800,500,3800,800,300,*,DOWN,NDIF +S 4900,500,4900,800,300,*,UP,NDIF +S 3500,1000,3700,1000,100,*,RIGHT,POLY +S 3300,1100,4500,1100,200,*,RIGHT,ALU1 +S 3300,1100,3300,1600,200,*,DOWN,ALU1 +S 5300,1000,5300,1600,100,*,DOWN,NTRANS +S 5600,500,5600,1400,300,*,DOWN,NDIF +S 4500,1100,4500,1600,200,*,DOWN,ALU1 +S 3300,1600,3300,3500,100,*,UP,POLY +S 300,2600,300,4500,300,*,UP,PDIF +S 900,2600,900,3100,300,*,UP,PDIF +S 600,2400,600,3300,100,*,UP,PTRANS +S 4900,3700,4900,4500,300,*,UP,PDIF +S 3800,4400,3800,5000,200,*,UP,ALU1 +S 3900,3500,4100,3500,100,*,LEFT,POLY +S 3300,3500,3500,3500,100,*,RIGHT,POLY +S 2100,3700,2100,4500,300,*,UP,PDIF +S 2400,1000,2400,1700,100,*,UP,POLY +S 4600,3500,4600,4700,100,*,UP,PTRANS +S 2300,1600,2300,2400,200,i1,UP,CALU1 +S 1500,1600,1500,2400,200,i2,UP,CALU1 +S 400,3400,1600,3400,200,*,LEFT,ALU1 +S 400,1100,400,3900,200,cmd1,DOWN,CALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +S 400,2100,600,2100,200,*,RIGHT,POLY +S 300,0,300,600,200,*,DOWN,ALU1 +S 900,1100,900,2900,200,*,UP,ALU1 +S 600,1000,600,1600,100,*,DOWN,NTRANS +S 900,1200,900,1400,300,*,DOWN,NDIF +S 1700,1000,1700,1100,100,*,DOWN,POLY +S 1600,1100,1700,1100,200,*,LEFT,POLY +S 900,1100,1600,1100,200,*,RIGHT,ALU1 +S 1200,300,1200,1000,100,*,UP,NTRANS +S 2400,300,2400,1000,100,*,UP,NTRANS +S 1700,300,1700,1000,100,*,UP,NTRANS +S 2900,300,2900,1000,100,*,UP,NTRANS +S 1500,500,1500,800,300,*,DOWN,NDIF +S 900,500,900,800,300,*,DOWN,NDIF +S 3300,500,3300,800,300,*,DOWN,NDIF +S 1900,1700,1900,2500,100,*,DOWN,POLY +S 1700,2500,1900,2500,100,*,RIGHT,POLY +S 1700,2500,1700,3500,100,*,DOWN,POLY +S 900,2900,2300,2900,200,*,LEFT,ALU1 +S 1900,1700,2400,1700,100,*,RIGHT,POLY +S 1200,3500,1200,4700,100,*,UP,PTRANS +S 1500,3700,1500,4500,300,*,DOWN,PDIF +S 1700,3500,1700,4700,100,*,UP,PTRANS +S 2400,3500,2400,4700,100,*,UP,PTRANS +S 4100,3500,4100,4700,100,*,UP,PTRANS +S 3500,3500,3500,4700,100,*,UP,PTRANS +S 3800,3700,3800,4500,300,*,UP,PDIF +S 3200,3700,3200,4500,300,*,UP,PDIF +S 2900,3500,2900,4700,100,*,UP,PTRANS +S 900,3700,900,4500,300,*,UP,PDIF +S 2100,500,2100,1200,300,*,UP,NDIF +S 2100,1100,2800,1100,200,*,RIGHT,ALU1 +B 2550,2100,700,200,CONT_TURN8,* +B 4500,3400,200,200,CONT_TURN8,* +B 4100,1100,200,200,CONT_TURN8,* +B 1600,1100,200,200,CONT_TURN8,* +B 2300,3400,200,200,CONT_TURN8,* +B 1600,3400,200,200,CONT_TURN8,* +B 450,2100,300,200,CONT_TURN8,* +B 1400,2100,400,200,CONT_TURN8,* +B 5000,600,200,200,CONT_TURN1,* +B 5100,2900,200,200,CONT_TURN1,* +B 5100,1600,200,200,CONT_TURN1,* +B 4500,1600,200,200,CONT_TURN1,* +B 4500,1100,200,200,CONT_TURN1,* +B 7300,4400,200,200,CONT_TURN1,* +B 7300,600,200,200,CONT_TURN1,* +B 5700,1100,200,200,CONT_TURN1,* +B 5000,1100,200,200,CONT_TURN1,* +B 5700,3900,200,200,CONT_TURN1,* +B 3300,1100,200,200,CONT_TURN1,* +B 2800,1100,200,200,CONT_TURN1,* +B 2300,2900,200,200,CONT_TURN1,* +B 900,2900,200,200,CONT_TURN1,* +B 900,1100,200,200,CONT_TURN1,* +V 7400,4400,CONT_DIF_P,* +V 7400,3700,CONT_DIF_P,* +V 7400,600,CONT_DIF_N,* +V 8000,5000,CONT_BODY_N,* +V 7500,5000,CONT_BODY_N,* +V 7000,5000,CONT_BODY_N,* +V 6500,5000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 7500,0,CONT_BODY_P,* +V 7000,0,CONT_BODY_P,* +V 6500,0,CONT_BODY_P,* +V 4500,3400,CONT_POLY,* +V 4500,2100,CONT_POLY,* +V 3800,2500,CONT_POLY,* +V 5700,2000,CONT_POLY,* +V 6800,3800,CONT_DIF_P,* +V 6200,3200,CONT_DIF_P,* +V 6200,3800,CONT_DIF_P,* +V 6200,2700,CONT_DIF_P,* +V 6200,4400,CONT_DIF_P,* +V 6800,4400,CONT_DIF_P,* +V 6800,2700,CONT_DIF_P,* +V 6800,3200,CONT_DIF_P,* +V 6800,600,CONT_DIF_N,* +V 6800,1300,CONT_DIF_N,* +V 6200,600,CONT_DIF_N,* +V 6200,1300,CONT_DIF_N,* +V 7300,2400,CONT_POLY,* +V 7300,1600,CONT_POLY,* +V 6000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2300,3400,CONT_POLY,* +V 5600,4400,CONT_DIF_P,* +V 5600,600,CONT_DIF_N,* +V 5000,2900,CONT_DIF_P,* +V 4100,1100,CONT_POLY,* +V 4900,600,CONT_DIF_N,* +V 3800,600,CONT_DIF_N,* +V 3300,1600,CONT_POLY,* +V 5000,1600,CONT_DIF_N,* +V 3200,600,CONT_DIF_N,* +V 900,2700,CONT_DIF_P,* +V 4900,3900,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 3800,4400,CONT_DIF_P,* +V 3200,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 400,2100,CONT_POLY,* +V 300,600,CONT_DIF_N,* +V 900,1300,CONT_DIF_N,* +V 1600,1100,CONT_POLY,* +V 1500,2100,CONT_POLY,* +V 2100,1100,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 1600,3400,CONT_POLY,* +V 2300,2100,CONT_POLY,* +V 6000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nmx3_x4.vbe b/pdks/symbolic/lsxlib/cells/nmx3_x4.vbe new file mode 100644 index 000000000..b6b54b2a0 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nmx3_x4.vbe @@ -0,0 +1,55 @@ +ENTITY nmx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 810; + CONSTANT rdown_cmd1_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_cmd0_nq : NATURAL := 890; + CONSTANT rup_cmd1_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 748; + CONSTANT tphl_cmd0_nq : NATURAL := 790; + CONSTANT tphl_cmd1_nq : NATURAL := 866; + CONSTANT tphl_i1_nq : NATURAL := 869; + CONSTANT tphl_i2_nq : NATURAL := 869; + CONSTANT tplh_i0_nq : NATURAL := 900; + CONSTANT tplh_cmd0_nq : NATURAL := 936; + CONSTANT tpll_cmd1_nq : NATURAL := 952; + CONSTANT tphh_cmd1_nq : NATURAL := 981; + CONSTANT tpll_cmd0_nq : NATURAL := 993; + CONSTANT tphh_cmd0_nq : NATURAL := 1041; + CONSTANT tplh_cmd1_nq : NATURAL := 1048; + CONSTANT tplh_i1_nq : NATURAL := 1053; + CONSTANT tplh_i2_nq : NATURAL := 1053; + CONSTANT transistors : NATURAL := 24 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x4; + +ARCHITECTURE behaviour_data_flow OF nmx3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx3_x4" + SEVERITY WARNING; + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not + (cmd1) and i2))))) after 1700 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/no2_x1.ap b/pdks/symbolic/lsxlib/cells/no2_x1.ap new file mode 100644 index 000000000..505dfa2b9 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no2_x1.ap @@ -0,0 +1,54 @@ +V ALLIANCE : 6 +H no2_x1,P, 1/ 8/2024,100 +A 0,0,2000,5000 +S 0,1100,2000,1100,1400,*,RIGHT,PWELL +S 1000,500,1000,900,300,*,DOWN,NDIF +S 1600,3900,1600,5000,200,*,UP,ALU1 +S 400,3900,1000,3900,200,*,LEFT,ALU1 +S 1500,1100,1500,3400,200,i1,DOWN,CALU1 +S 500,1100,500,3400,200,i0,DOWN,CALU1 +S 400,4400,1000,4400,200,*,LEFT,ALU1 +S 1600,0,1600,600,200,*,DOWN,ALU1 +S 1300,2300,1500,2300,200,*,RIGHT,POLY +S 500,2300,700,2300,200,*,RIGHT,POLY +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 400,2600,400,4500,300,*,DOWN,PDIF +S 1300,2400,1300,4700,100,*,UP,PTRANS +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 700,2400,700,4700,100,*,UP,PTRANS +S 1300,1100,1300,2400,100,*,DOWN,POLY +S 700,1100,700,2400,100,*,UP,POLY +S 1600,500,1600,900,300,*,UP,NDIF +S 1300,300,1300,1100,100,*,DOWN,NTRANS +S 700,300,700,1100,100,*,DOWN,NTRANS +S 400,500,400,900,300,*,UP,NDIF +S 0,4000,2000,4000,1200,*,RIGHT,NWELL +S 0,3100,2000,3100,1200,*,RIGHT,NWELL +S 0,0,2000,0,400,vss,RIGHT,CALU1 +S 0,5000,2000,5000,400,vdd,RIGHT,CALU1 +S 1000,600,1000,4400,200,nq,DOWN,CALU1 +S 400,0,400,600,200,*,DOWN,ALU1 +S 0,5000,2000,5000,300,*,RIGHT,NTIE +S 0,0,2000,0,300,*,RIGHT,PTIE +B 1450,2300,300,200,CONT_TURN8,* +B 550,2300,300,200,CONT_TURN8,* +V 400,3900,CONT_DIF_P,* +V 1600,3900,CONT_DIF_P,* +V 1600,600,CONT_DIF_N,* +V 1000,600,CONT_DIF_N,* +V 1500,2300,CONT_POLY,* +V 500,2300,CONT_POLY,* +V 400,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/no2_x1.vbe b/pdks/symbolic/lsxlib/cells/no2_x1.vbe new file mode 100644 index 000000000..37a91f3f6 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tplh_i0_nq : NATURAL := 121; + CONSTANT tplh_i1_nq : NATURAL := 161; + CONSTANT tphl_i1_nq : NATURAL := 193; + CONSTANT tphl_i0_nq : NATURAL := 298; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x1; + +ARCHITECTURE behaviour_data_flow OF no2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x1" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 900 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/no2_x4.ap b/pdks/symbolic/lsxlib/cells/no2_x4.ap new file mode 100644 index 000000000..f24ed593d --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no2_x4.ap @@ -0,0 +1,111 @@ +V ALLIANCE : 6 +H no2_x4,P, 1/ 8/2024,100 +A 0,0,4000,5000 +S 0,1100,4000,1100,1400,*,RIGHT,PWELL +S 3300,600,3300,4400,200,*,UP,ALU1 +S 1000,500,1000,900,300,*,DOWN,NDIF +S 2200,600,2200,4400,200,nq,UP,CALU1 +S 3700,1100,3700,3400,100,*,DOWN,POLY +S 3400,3600,3400,4500,300,*,DOWN,PDIF +S 3100,3400,3100,4700,100,*,DOWN,PTRANS +S 3100,3400,3700,3400,100,*,RIGHT,POLY +S 3300,4400,3400,4400,200,*,RIGHT,ALU1 +S 3300,3700,3400,3700,200,*,RIGHT,ALU1 +S 3100,300,3100,1100,100,*,UP,NTRANS +S 3400,500,3400,900,300,*,DOWN,NDIF +S 3100,1100,3700,1100,100,*,LEFT,POLY +S 3300,600,3400,600,200,*,LEFT,ALU1 +S 0,4000,4000,4000,1200,*,RIGHT,NWELL +S 0,3100,4000,3100,1200,*,RIGHT,NWELL +S 0,5000,4000,5000,300,*,RIGHT,NTIE +S 0,5000,4000,5000,400,vdd,RIGHT,CALU1 +S 0,0,4000,0,300,*,RIGHT,PTIE +S 0,0,4000,0,400,vss,RIGHT,CALU1 +S 1700,1100,1700,3900,200,*,UP,ALU1 +S 1100,2300,1300,2300,200,i1,RIGHT,POLY +S 1100,1600,1100,3400,200,i1,UP,CALU1 +S 1600,4400,1600,5000,200,*,UP,ALU1 +S 400,3900,400,4400,200,*,UP,ALU1 +S 400,3900,1700,3900,200,*,LEFT,ALU1 +S 1000,1100,1700,1100,200,*,RIGHT,ALU1 +S 1000,600,1000,1100,200,*,UP,ALU1 +S 1700,2000,3700,2000,100,*,RIGHT,POLY +S 1600,500,1600,1400,300,*,UP,NDIF +S 2500,2400,2500,4700,100,*,DOWN,PTRANS +S 2800,2600,2800,4500,300,*,UP,PDIF +S 2200,2600,2200,4500,300,*,DOWN,PDIF +S 1900,2400,1900,4700,100,*,DOWN,PTRANS +S 2500,300,2500,1600,100,*,UP,NTRANS +S 1900,300,1900,1600,100,*,UP,NTRANS +S 2200,500,2200,1400,300,*,DOWN,NDIF +S 2800,500,2800,1400,300,*,DOWN,NDIF +S 1900,2400,3300,2400,100,*,RIGHT,POLY +S 1900,1600,3300,1600,100,*,RIGHT,POLY +S 2800,0,2800,1300,200,*,DOWN,ALU1 +S 2800,2700,2800,5000,200,*,UP,ALU1 +S 500,1100,500,3400,200,i0,DOWN,CALU1 +S 1600,0,1600,600,200,*,DOWN,ALU1 +S 500,2300,700,2300,200,*,RIGHT,POLY +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 400,2600,400,4500,300,*,DOWN,PDIF +S 1300,2400,1300,4700,100,*,UP,PTRANS +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 700,2400,700,4700,100,*,UP,PTRANS +S 1300,1100,1300,2400,100,*,DOWN,POLY +S 700,1100,700,2400,100,*,UP,POLY +S 1300,300,1300,1100,100,*,DOWN,NTRANS +S 700,300,700,1100,100,*,DOWN,NTRANS +S 400,500,400,900,300,*,UP,NDIF +S 400,0,400,600,200,*,DOWN,ALU1 +B 1150,2300,300,200,CONT_TURN8,* +B 550,2300,300,200,CONT_TURN8,* +B 3300,4400,200,200,CONT_TURN1,* +B 3300,600,200,200,CONT_TURN1,* +B 1000,1100,200,200,CONT_TURN1,* +B 1700,1100,200,200,CONT_TURN1,* +B 1700,3900,200,200,CONT_TURN1,* +V 3400,4400,CONT_DIF_P,* +V 3400,3700,CONT_DIF_P,* +V 3400,600,CONT_DIF_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 1100,2300,CONT_POLY,* +V 1700,2000,CONT_POLY,* +V 2800,3200,CONT_DIF_P,* +V 2800,2700,CONT_DIF_P,* +V 2800,3800,CONT_DIF_P,* +V 2200,3200,CONT_DIF_P,* +V 2200,3800,CONT_DIF_P,* +V 2800,4400,CONT_DIF_P,* +V 2200,4400,CONT_DIF_P,* +V 2200,2700,CONT_DIF_P,* +V 2200,1300,CONT_DIF_N,* +V 2200,600,CONT_DIF_N,* +V 2800,600,CONT_DIF_N,* +V 2800,1300,CONT_DIF_N,* +V 3300,1600,CONT_POLY,* +V 3300,2400,CONT_POLY,* +V 400,3900,CONT_DIF_P,* +V 1600,600,CONT_DIF_N,* +V 1000,600,CONT_DIF_N,* +V 500,2300,CONT_POLY,* +V 400,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/no2_x4.vbe b/pdks/symbolic/lsxlib/cells/no2_x4.vbe new file mode 100644 index 000000000..5060db0e8 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tplh_i0_nq : NATURAL := 447; + CONSTANT tplh_i1_nq : NATURAL := 504; + CONSTANT tphl_i1_nq : NATURAL := 522; + CONSTANT tphl_i0_nq : NATURAL := 618; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x4; + +ARCHITECTURE behaviour_data_flow OF no2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x4" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/no3_x1.ap b/pdks/symbolic/lsxlib/cells/no3_x1.ap new file mode 100644 index 000000000..152427308 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no3_x1.ap @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H no3_x1,P, 1/ 8/2024,100 +A 0,0,2500,5000 +S 0,1100,2500,1100,1400,*,RIGHT,PWELL +S 1500,500,1500,900,300,*,DOWN,NDIF +S 0,4000,2500,4000,1200,*,RIGHT,NWELL +S 0,3100,2500,3100,1200,*,RIGHT,NWELL +S 0,5000,2500,5000,300,*,RIGHT,NTIE +S 0,5000,2500,5000,400,vdd,RIGHT,CALU1 +S 0,0,2500,0,300,*,RIGHT,PTIE +S 0,0,2500,0,400,vss,RIGHT,CALU1 +S 1000,1600,1000,3900,200,i1,DOWN,CALU1 +S 400,4400,1500,4400,200,*,RIGHT,ALU1 +S 300,3900,300,4400,200,*,UP,ALU1 +S 2000,1100,2000,3400,200,i2,DOWN,CALU1 +S 600,1100,600,2400,100,*,DOWN,POLY +S 400,2300,600,2300,200,*,RIGHT,POLY +S 400,1600,400,3400,200,i0,DOWN,CALU1 +S 300,2600,300,4500,300,*,DOWN,PDIF +S 600,2400,600,4700,100,*,UP,PTRANS +S 300,1100,1500,1100,200,*,RIGHT,ALU1 +S 300,600,300,1100,200,*,UP,ALU1 +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 2100,500,2100,900,300,*,UP,NDIF +S 1200,1100,1200,2400,100,*,UP,POLY +S 1800,1100,1800,2400,100,*,DOWN,POLY +S 1000,2300,1200,2300,200,*,RIGHT,POLY +S 1800,2300,2000,2300,200,*,RIGHT,POLY +S 900,0,900,600,200,*,DOWN,ALU1 +S 2100,0,2100,600,200,*,DOWN,ALU1 +S 2100,3900,2100,5000,200,*,UP,ALU1 +S 1500,600,1500,4400,200,nq,DOWN,CALU1 +B 1950,2300,300,200,CONT_TURN8,* +B 1050,2300,300,200,CONT_TURN8,* +B 450,2300,300,200,CONT_TURN8,* +B 300,1100,200,200,CONT_TURN1,* +V 2500,5000,CONT_BODY_N,* +V 2500,0,CONT_BODY_P,* +V 400,2300,CONT_POLY,* +V 300,3900,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 1000,2300,CONT_POLY,* +V 2000,2300,CONT_POLY,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/no3_x1.vbe b/pdks/symbolic/lsxlib/cells/no3_x1.vbe new file mode 100644 index 000000000..6711f8b1f --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT tplh_i2_nq : NATURAL := 192; + CONSTANT tphl_i1_nq : NATURAL := 215; + CONSTANT tplh_i1_nq : NATURAL := 243; + CONSTANT tplh_i0_nq : NATURAL := 246; + CONSTANT tphl_i0_nq : NATURAL := 318; + CONSTANT tphl_i2_nq : NATURAL := 407; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x1; + +ARCHITECTURE behaviour_data_flow OF no3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/no3_x4.ap b/pdks/symbolic/lsxlib/cells/no3_x4.ap new file mode 100644 index 000000000..a72215eaa --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no3_x4.ap @@ -0,0 +1,128 @@ +V ALLIANCE : 6 +H no3_x4,P, 1/ 8/2024,100 +A 0,0,4500,5000 +S 0,1100,4500,1100,1400,*,RIGHT,PWELL +S 1500,500,1500,900,300,*,DOWN,NDIF +S 3800,600,3800,4400,200,*,UP,ALU1 +S 4200,1100,4200,3400,100,*,DOWN,POLY +S 3900,3600,3900,4500,300,*,DOWN,PDIF +S 3600,3400,3600,4700,100,*,DOWN,PTRANS +S 3600,3400,4200,3400,100,*,RIGHT,POLY +S 3800,4400,3900,4400,200,*,RIGHT,ALU1 +S 3800,3700,3900,3700,200,*,RIGHT,ALU1 +S 3600,300,3600,1100,100,*,UP,NTRANS +S 3900,500,3900,900,300,*,DOWN,NDIF +S 3600,1100,4200,1100,100,*,LEFT,POLY +S 3800,600,3900,600,200,*,LEFT,ALU1 +S 1000,1600,1000,3900,200,i1,DOWN,CALU1 +S 1600,3900,2200,3900,200,*,RIGHT,ALU1 +S 1600,3900,1600,4400,200,*,DOWN,ALU1 +S 300,4400,1600,4400,200,*,RIGHT,ALU1 +S 300,600,300,1100,200,*,DOWN,ALU1 +S 300,1100,2200,1100,200,*,RIGHT,ALU1 +S 400,1600,400,3400,200,i0,DOWN,CALU1 +S 1600,1600,1600,3400,200,i2,UP,CALU1 +S 300,2600,300,4500,300,*,DOWN,PDIF +S 600,300,600,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 600,2400,600,4700,100,*,UP,PTRANS +S 600,1100,600,2400,100,*,UP,POLY +S 400,2300,600,2300,200,*,RIGHT,POLY +S 300,3900,300,4400,200,*,UP,ALU1 +S 0,5000,4500,5000,300,*,RIGHT,NTIE +S 0,4000,4500,4000,1200,*,RIGHT,NWELL +S 0,3100,4500,3100,1200,*,RIGHT,NWELL +S 0,5000,4500,5000,400,vdd,RIGHT,CALU1 +S 0,0,4500,0,300,*,RIGHT,PTIE +S 0,0,4500,0,400,vss,RIGHT,CALU1 +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 900,2600,900,4500,300,*,DOWN,PDIF +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 3000,2400,3000,4700,100,*,DOWN,PTRANS +S 3300,2600,3300,4500,300,*,UP,PDIF +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 2400,2400,2400,4700,100,*,DOWN,PTRANS +S 3000,300,3000,1600,100,*,UP,NTRANS +S 2400,300,2400,1600,100,*,UP,NTRANS +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 3300,500,3300,1400,300,*,DOWN,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 2100,500,2100,1400,300,*,UP,NDIF +S 2700,500,2700,1400,300,*,DOWN,NDIF +S 1800,1100,1800,2400,100,*,DOWN,POLY +S 1200,1100,1200,2400,100,*,UP,POLY +S 2400,2400,3800,2400,100,*,RIGHT,POLY +S 2400,1600,3800,1600,100,*,RIGHT,POLY +S 1000,2300,1200,2300,200,*,RIGHT,POLY +S 1600,2300,1800,2300,200,i1,RIGHT,POLY +S 2200,2000,4200,2000,100,*,RIGHT,POLY +S 3300,0,3300,1300,200,*,DOWN,ALU1 +S 2100,0,2100,600,200,*,DOWN,ALU1 +S 900,0,900,600,200,*,DOWN,ALU1 +S 1500,600,1500,1100,200,*,UP,ALU1 +S 2700,600,2700,4400,200,nq,UP,CALU1 +S 3300,2700,3300,5000,200,*,UP,ALU1 +S 2200,1100,2200,3900,200,*,UP,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +B 1650,2300,300,200,CONT_TURN8,* +B 1050,2300,300,200,CONT_TURN8,* +B 450,2300,300,200,CONT_TURN8,* +B 3800,4400,200,200,CONT_TURN1,* +B 3800,600,200,200,CONT_TURN1,* +B 300,1100,200,200,CONT_TURN1,* +B 2200,1100,200,200,CONT_TURN1,* +B 2200,3900,200,200,CONT_TURN1,* +B 1600,3900,200,200,CONT_TURN1,* +B 1600,4400,200,200,CONT_TURN1,* +V 3900,3700,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 3900,600,CONT_DIF_N,* +V 300,4400,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 400,2300,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 2700,4400,CONT_DIF_P,* +V 2700,2700,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3300,3200,CONT_DIF_P,* +V 3300,2700,CONT_DIF_P,* +V 3300,3800,CONT_DIF_P,* +V 2700,3200,CONT_DIF_P,* +V 2700,3800,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 2700,600,CONT_DIF_N,* +V 3300,600,CONT_DIF_N,* +V 3300,1300,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 2700,1300,CONT_DIF_N,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,2300,CONT_POLY,* +V 1600,2300,CONT_POLY,* +V 2200,2000,CONT_POLY,* +V 3800,1600,CONT_POLY,* +V 3800,2400,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/no3_x4.vbe b/pdks/symbolic/lsxlib/cells/no3_x4.vbe new file mode 100644 index 000000000..52e3d602b --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 545; + CONSTANT tplh_i0_nq : NATURAL := 561; + CONSTANT tplh_i1_nq : NATURAL := 623; + CONSTANT tphl_i1_nq : NATURAL := 638; + CONSTANT tplh_i2_nq : NATURAL := 640; + CONSTANT tphl_i0_nq : NATURAL := 722; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x4; + +ARCHITECTURE behaviour_data_flow OF no3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/no4_x1.ap b/pdks/symbolic/lsxlib/cells/no4_x1.ap new file mode 100644 index 000000000..9758853e0 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no4_x1.ap @@ -0,0 +1,82 @@ +V ALLIANCE : 6 +H no4_x1,P, 1/ 8/2024,100 +A 0,0,3000,5000 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 2100,500,2100,900,300,*,DOWN,NDIF +S 0,5000,3000,5000,300,*,RIGHT,NTIE +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +S 0,0,3000,0,300,*,RIGHT,PTIE +S 0,0,3000,0,400,vss,RIGHT,CALU1 +S 300,2600,300,4500,300,*,DOWN,PDIF +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 600,2400,600,4700,100,*,UP,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 2400,2400,2400,4700,100,*,UP,PTRANS +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 2400,300,2400,1100,100,*,DOWN,NTRANS +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 2700,500,2700,900,300,*,UP,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 600,1100,600,2400,100,*,DOWN,POLY +S 400,2300,600,2300,200,*,RIGHT,POLY +S 1200,1100,1200,2400,100,*,DOWN,POLY +S 2400,2300,2600,2300,200,*,RIGHT,POLY +S 1600,2300,1800,2300,200,*,RIGHT,POLY +S 2400,1100,2400,2400,100,*,DOWN,POLY +S 1800,1100,1800,2400,100,*,UP,POLY +S 1000,2300,1200,2300,200,*,RIGHT,POLY +S 300,0,300,600,200,*,DOWN,ALU1 +S 2700,0,2700,600,200,*,DOWN,ALU1 +S 1500,0,1500,600,200,*,DOWN,ALU1 +S 300,4400,2100,4400,200,*,RIGHT,ALU1 +S 1000,1600,1000,3900,200,i1,DOWN,CALU1 +S 1600,1600,1600,3900,200,i2,DOWN,CALU1 +S 2600,1100,2600,3400,200,i3,DOWN,CALU1 +S 300,3900,300,4400,200,*,UP,ALU1 +S 400,1600,400,3400,200,i0,DOWN,CALU1 +S 2100,600,2100,4400,200,nq,DOWN,CALU1 +S 2700,3900,2700,5000,200,*,UP,ALU1 +S 900,600,900,1100,200,*,UP,ALU1 +S 900,1100,2100,1100,200,*,RIGHT,ALU1 +B 2550,2300,300,200,CONT_TURN8,* +B 1650,2300,300,200,CONT_TURN8,* +B 1050,2300,300,200,CONT_TURN8,* +B 450,2300,300,200,CONT_TURN8,* +B 900,1100,200,200,CONT_TURN1,* +V 0,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 300,3900,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 400,2300,CONT_POLY,* +V 2600,2300,CONT_POLY,* +V 1600,2300,CONT_POLY,* +V 1000,2300,CONT_POLY,* +V 500,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/no4_x1.vbe b/pdks/symbolic/lsxlib/cells/no4_x1.vbe new file mode 100644 index 000000000..5d15a3cd4 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rdown_i3_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT tphl_i1_nq : NATURAL := 230; + CONSTANT tplh_i3_nq : NATURAL := 271; + CONSTANT tplh_i1_nq : NATURAL := 320; + CONSTANT tphl_i0_nq : NATURAL := 330; + CONSTANT tplh_i2_nq : NATURAL := 333; + CONSTANT tplh_i0_nq : NATURAL := 340; + CONSTANT tphl_i2_nq : NATURAL := 419; + CONSTANT tphl_i3_nq : NATURAL := 499; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x1; + +ARCHITECTURE behaviour_data_flow OF no4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x1" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1100 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/no4_x4.ap b/pdks/symbolic/lsxlib/cells/no4_x4.ap new file mode 100644 index 000000000..70f591aa6 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no4_x4.ap @@ -0,0 +1,141 @@ +V ALLIANCE : 6 +H no4_x4,P, 1/ 8/2024,100 +A 0,0,5000,5000 +S 0,1100,5000,1100,1400,*,RIGHT,PWELL +S 300,0,300,600,200,*,DOWN,ALU1 +S 2100,500,2100,900,300,*,DOWN,NDIF +S 4400,600,4400,4400,200,*,UP,ALU1 +S 400,1100,400,3400,200,i0,DOWN,CALU1 +S 4800,1100,4800,3400,100,*,DOWN,POLY +S 4500,3600,4500,4500,300,*,DOWN,PDIF +S 4200,3400,4200,4700,100,*,DOWN,PTRANS +S 4200,3400,4800,3400,100,*,RIGHT,POLY +S 4400,4400,4500,4400,200,*,RIGHT,ALU1 +S 4400,3700,4500,3700,200,*,RIGHT,ALU1 +S 4200,300,4200,1100,100,*,UP,NTRANS +S 4500,500,4500,900,300,*,DOWN,NDIF +S 4200,1100,4800,1100,100,*,LEFT,POLY +S 4400,600,4500,600,200,*,LEFT,ALU1 +S 2200,1600,2200,3400,200,i3,UP,CALU1 +S 1600,1600,1600,3900,200,i2,DOWN,CALU1 +S 1000,1600,1000,3900,200,i1,DOWN,CALU1 +S 300,4400,2200,4400,200,*,RIGHT,ALU1 +S 300,2600,300,4500,300,*,DOWN,PDIF +S 600,300,600,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 600,2400,600,4700,100,*,UP,PTRANS +S 400,2300,600,2300,200,*,RIGHT,POLY +S 600,1100,600,2400,100,*,UP,POLY +S 300,3900,300,4400,200,*,UP,ALU1 +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 3600,2400,3600,4700,100,*,DOWN,PTRANS +S 3900,2600,3900,4500,300,*,UP,PDIF +S 3300,2600,3300,4500,300,*,DOWN,PDIF +S 3000,2400,3000,4700,100,*,DOWN,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 2400,2400,2400,4700,100,*,UP,PTRANS +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 3600,300,3600,1600,100,*,UP,NTRANS +S 3000,300,3000,1600,100,*,UP,NTRANS +S 2400,300,2400,1100,100,*,DOWN,NTRANS +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 2700,500,2700,1400,300,*,UP,NDIF +S 3300,500,3300,1400,300,*,DOWN,NDIF +S 3900,500,3900,1400,300,*,DOWN,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 3000,2400,4400,2400,100,*,RIGHT,POLY +S 3000,1600,4400,1600,100,*,RIGHT,POLY +S 1600,2300,1800,2300,200,*,RIGHT,POLY +S 2200,2300,2400,2300,200,i1,RIGHT,POLY +S 2800,2000,4800,2000,100,*,RIGHT,POLY +S 2400,1100,2400,2400,100,*,DOWN,POLY +S 1800,1100,1800,2400,100,*,UP,POLY +S 1200,1100,1200,2400,100,*,UP,POLY +S 1000,2300,1200,2300,200,*,RIGHT,POLY +S 3900,0,3900,1300,200,*,DOWN,ALU1 +S 2700,0,2700,600,200,*,DOWN,ALU1 +S 1500,0,1500,600,200,*,DOWN,ALU1 +S 3900,2700,3900,5000,200,*,UP,ALU1 +S 2800,1100,2800,3900,200,*,UP,ALU1 +S 2700,4400,2700,5000,200,*,UP,ALU1 +S 2100,600,2100,1100,200,*,UP,ALU1 +S 3300,600,3300,4400,200,nq,UP,CALU1 +S 2200,3900,2800,3900,200,*,RIGHT,ALU1 +S 2200,3900,2200,4400,200,*,DOWN,ALU1 +S 900,600,900,1100,200,*,DOWN,ALU1 +S 900,1100,2800,1100,200,*,RIGHT,ALU1 +S 0,0,5000,0,300,*,RIGHT,PTIE +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +B 2250,2300,300,200,CONT_TURN8,* +B 1650,2300,300,200,CONT_TURN8,* +B 1050,2300,300,200,CONT_TURN8,* +B 450,2300,300,200,CONT_TURN8,* +B 4400,4400,200,200,CONT_TURN1,* +B 4400,600,200,200,CONT_TURN1,* +B 900,1100,200,200,CONT_TURN1,* +B 2800,1100,200,200,CONT_TURN1,* +B 2800,3900,200,200,CONT_TURN1,* +B 2200,3900,200,200,CONT_TURN1,* +B 2200,4400,200,200,CONT_TURN1,* +V 4500,3700,CONT_DIF_P,* +V 4500,4400,CONT_DIF_P,* +V 4500,600,CONT_DIF_N,* +V 5000,0,CONT_BODY_P,* +V 5000,5000,CONT_BODY_N,* +V 300,3900,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 400,2300,CONT_POLY,* +V 3300,3200,CONT_DIF_P,* +V 3300,3800,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 3900,3200,CONT_DIF_P,* +V 3900,2700,CONT_DIF_P,* +V 3900,3800,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 3300,2700,CONT_DIF_P,* +V 2100,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 3300,1300,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 3300,600,CONT_DIF_N,* +V 3900,600,CONT_DIF_N,* +V 3900,1300,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 1000,2300,CONT_POLY,* +V 1600,2300,CONT_POLY,* +V 2200,2300,CONT_POLY,* +V 2800,2000,CONT_POLY,* +V 4400,1600,CONT_POLY,* +V 4400,2400,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/no4_x4.vbe b/pdks/symbolic/lsxlib/cells/no4_x4.vbe new file mode 100644 index 000000000..cffb179c4 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/no4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 564; + CONSTANT tphl_i0_nq : NATURAL := 656; + CONSTANT tplh_i3_nq : NATURAL := 693; + CONSTANT tphl_i2_nq : NATURAL := 739; + CONSTANT tplh_i2_nq : NATURAL := 761; + CONSTANT tplh_i1_nq : NATURAL := 768; + CONSTANT tplh_i0_nq : NATURAL := 777; + CONSTANT tphl_i3_nq : NATURAL := 816; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x4; + +ARCHITECTURE behaviour_data_flow OF no4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x4" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa22_x1.ap b/pdks/symbolic/lsxlib/cells/noa22_x1.ap new file mode 100644 index 000000000..5bd586cfc --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa22_x1.ap @@ -0,0 +1,67 @@ +V ALLIANCE : 6 +H noa22_x1,P, 1/ 8/2024,100 +A 0,0,2500,5000 +S 0,1100,2500,1100,1400,*,RIGHT,PWELL +S 2000,1100,2000,3900,200,i2,DOWN,CALU1 +S 1800,1600,1800,2400,100,*,DOWN,POLY +S 1200,1600,1200,2400,100,*,DOWN,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +S 400,1100,400,3400,200,i0,DOWN,CALU1 +S 300,4400,1500,4400,200,*,RIGHT,ALU1 +S 300,3900,300,4400,200,*,UP,ALU1 +S 900,3900,1500,3900,200,*,RIGHT,ALU1 +S 1500,600,1500,3900,200,nq,DOWN,CALU1 +S 1000,600,1000,3400,200,i1,DOWN,CALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +S 0,0,2500,0,300,*,RIGHT,PTIE +S 0,0,2500,0,400,vss,LEFT,CALU1 +S 0,5000,2500,5000,300,*,RIGHT,NTIE +S 0,5000,2500,5000,400,vdd,RIGHT,CALU1 +S 0,4000,2500,4000,1200,*,RIGHT,NWELL +S 0,3100,2500,3100,1200,*,RIGHT,NWELL +S 400,2000,600,2000,200,*,RIGHT,POLY +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 300,2600,300,4500,300,*,DOWN,PDIF +S 600,2400,600,4700,100,*,UP,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 900,500,900,1400,300,*,UP,NDIF +S 2100,0,2100,600,200,*,UP,ALU1 +S 600,300,600,1600,100,*,DOWN,NTRANS +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 2100,500,2100,1400,300,*,UP,NDIF +S 300,500,300,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +S 1800,2000,2000,2000,200,*,RIGHT,POLY +S 1000,2000,1200,2000,200,*,RIGHT,POLY +S 2100,4400,2100,5000,200,*,UP,ALU1 +B 1950,2000,300,200,CONT_TURN8,* +B 1050,2000,300,200,CONT_TURN8,* +B 450,2000,300,200,CONT_TURN8,* +V 300,3900,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 900,3900,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 400,2000,CONT_POLY,* +V 1500,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa22_x1.vbe b/pdks/symbolic/lsxlib/cells/noa22_x1.vbe new file mode 100644 index 000000000..5c13864f3 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 1620; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tphl_i2_nq : NATURAL := 218; + CONSTANT tplh_i2_nq : NATURAL := 241; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x1; + +ARCHITECTURE behaviour_data_flow OF noa22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 900 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa22_x4.ap b/pdks/symbolic/lsxlib/cells/noa22_x4.ap new file mode 100644 index 000000000..1941c6872 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa22_x4.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H noa22_x4,P, 1/ 8/2024,100 +A 0,0,4500,5000 +S 0,1100,4500,1100,1400,*,RIGHT,PWELL +S 3800,600,3800,4400,200,*,UP,ALU1 +S 4200,1100,4200,3400,100,*,DOWN,POLY +S 3600,300,3600,1100,100,*,UP,NTRANS +S 3900,500,3900,900,300,*,DOWN,NDIF +S 3600,1100,4200,1100,100,*,LEFT,POLY +S 3800,600,3900,600,200,*,LEFT,ALU1 +S 3900,3600,3900,4500,300,*,DOWN,PDIF +S 3600,3400,3600,4700,100,*,DOWN,PTRANS +S 3600,3400,4200,3400,100,*,RIGHT,POLY +S 3800,4400,3900,4400,200,*,RIGHT,ALU1 +S 3800,3700,3900,3700,200,*,RIGHT,ALU1 +S 400,1100,400,3900,200,i0,DOWN,CALU1 +S 300,4400,1500,4400,200,*,RIGHT,ALU1 +S 900,3900,2200,3900,200,*,LEFT,ALU1 +S 1000,600,1000,3400,200,i1,DOWN,CALU1 +S 1500,600,1500,1100,200,*,UP,ALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +S 1500,1100,2200,1100,200,*,RIGHT,ALU1 +S 900,500,900,900,300,*,UP,NDIF +S 2100,0,2100,600,200,*,DOWN,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 900,3600,900,4500,300,*,DOWN,PDIF +S 1800,1100,1800,3400,100,*,DOWN,POLY +S 1200,1100,1200,3400,100,*,UP,POLY +S 600,1100,600,3400,100,*,DOWN,POLY +S 2200,1100,2200,3900,200,*,UP,ALU1 +S 1600,1600,1600,3400,200,i2,DOWN,CALU1 +S 2200,2000,4200,2000,100,*,RIGHT,POLY +S 2100,500,2100,1400,300,*,UP,NDIF +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 300,3600,300,4500,300,*,DOWN,PDIF +S 600,3400,600,4700,100,*,UP,PTRANS +S 1200,3400,1200,4700,100,*,UP,PTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 1600,2000,1800,2000,200,*,RIGHT,POLY +S 400,2000,600,2000,200,*,RIGHT,POLY +S 1000,2000,1200,2000,200,*,RIGHT,POLY +S 1100,2000,1200,2000,200,*,RIGHT,POLY +S 0,4000,4500,4000,1200,*,RIGHT,NWELL +S 0,3100,4500,3100,1200,*,RIGHT,NWELL +S 0,5000,4500,5000,300,*,RIGHT,NTIE +S 0,5000,4500,5000,400,vdd,RIGHT,CALU1 +S 0,0,4500,0,300,*,RIGHT,PTIE +S 0,0,4500,0,400,vss,RIGHT,CALU1 +S 3300,2600,3300,4500,300,*,UP,PDIF +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 2400,2400,2400,4700,100,*,DOWN,PTRANS +S 3000,2400,3000,4700,100,*,DOWN,PTRANS +S 3000,300,3000,1600,100,*,UP,NTRANS +S 2400,300,2400,1600,100,*,UP,NTRANS +S 3300,500,3300,1400,300,*,DOWN,NDIF +S 2700,500,2700,1400,300,*,DOWN,NDIF +S 2400,1600,3800,1600,100,*,RIGHT,POLY +S 2400,2400,3800,2400,100,*,RIGHT,POLY +S 3300,0,3300,1300,200,*,DOWN,ALU1 +S 3300,2700,3300,5000,200,*,UP,ALU1 +S 2700,600,2700,4400,200,nq,UP,CALU1 +B 1650,2000,300,200,CONT_TURN8,* +B 1050,2000,300,200,CONT_TURN8,* +B 450,2000,300,200,CONT_TURN8,* +B 3800,600,200,200,CONT_TURN1,* +B 3800,4400,200,200,CONT_TURN1,* +B 2200,3900,200,200,CONT_TURN1,* +B 2200,1100,200,200,CONT_TURN1,* +B 1500,1100,200,200,CONT_TURN1,* +V 3900,600,CONT_DIF_N,* +V 3900,4400,CONT_DIF_P,* +V 3900,3700,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 900,3900,CONT_DIF_P,* +V 1500,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 2000,5000,CONT_BODY_N,* +V 2100,4400,CONT_DIF_P,* +V 2200,2000,CONT_POLY,* +V 2100,600,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 400,2000,CONT_POLY,* +V 4500,5000,CONT_BODY_N,* +V 4500,0,CONT_BODY_P,* +V 3300,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 2700,2700,CONT_DIF_P,* +V 3300,3200,CONT_DIF_P,* +V 3300,2700,CONT_DIF_P,* +V 3300,3800,CONT_DIF_P,* +V 2700,3200,CONT_DIF_P,* +V 2700,3800,CONT_DIF_P,* +V 2700,1300,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 3300,600,CONT_DIF_N,* +V 3300,1300,CONT_DIF_N,* +V 3800,1600,CONT_POLY,* +V 3800,2400,CONT_POLY,* +V 1600,2000,CONT_POLY,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa22_x4.vbe b/pdks/symbolic/lsxlib/cells/noa22_x4.vbe new file mode 100644 index 000000000..6288a32e6 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 550; + CONSTANT tphl_i2_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i2_nq : NATURAL := 646; + CONSTANT tplh_i1_nq : NATURAL := 709; + CONSTANT tplh_i0_nq : NATURAL := 740; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x4; + +ARCHITECTURE behaviour_data_flow OF noa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa2a22_x1.ap b/pdks/symbolic/lsxlib/cells/noa2a22_x1.ap new file mode 100644 index 000000000..8540a2563 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a22_x1.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 6 +H noa2a22_x1,P, 1/ 8/2024,100 +A 0,0,3000,5000 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 300,2100,600,2100,100,*,RIGHT,POLY +S 2700,0,2700,600,200,*,DOWN,ALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 900,3400,900,3900,200,*,DOWN,ALU1 +S 1500,3900,2700,3900,200,*,RIGHT,ALU1 +S 300,4400,1500,4400,200,*,RIGHT,ALU1 +S 900,3400,1500,3400,200,*,RIGHT,ALU1 +S 2700,3900,2700,4400,200,*,DOWN,ALU1 +S 1500,3900,1500,4400,200,*,DOWN,ALU1 +S 300,3900,300,4400,200,*,DOWN,ALU1 +S 300,1100,300,3400,200,i0,DOWN,CALU1 +S 2500,1100,2500,3400,200,i2,DOWN,CALU1 +S 2000,600,2000,3400,200,i3,DOWN,CALU1 +S 1500,600,1500,3400,200,nq,DOWN,CALU1 +S 1000,600,1000,2900,200,i1,DOWN,CALU1 +S 1000,2100,1200,2100,200,*,RIGHT,POLY +S 1800,2100,2000,2100,200,*,RIGHT,POLY +S 0,5000,3000,5000,300,*,RIGHT,NTIE +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +S 0,0,3000,0,300,*,RIGHT,PTIE +S 0,0,3000,0,400,vss,RIGHT,CALU1 +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 2400,2400,2400,4700,100,*,UP,PTRANS +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 600,2400,600,4700,100,*,UP,PTRANS +S 300,2600,300,4500,300,*,DOWN,PDIF +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 2400,1600,2400,2400,100,*,DOWN,POLY +S 1800,1600,1800,2400,100,*,DOWN,POLY +S 1200,1600,1200,2400,100,*,DOWN,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +S 900,500,900,1400,300,*,UP,NDIF +S 2400,300,2400,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 600,300,600,1600,100,*,DOWN,NTRANS +S 300,500,300,1400,300,*,UP,NDIF +S 2700,500,2700,1400,300,*,UP,NDIF +S 2100,500,2100,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +B 2500,2100,200,200,CONT_TURN8,* +B 1950,2100,300,200,CONT_TURN8,* +B 1050,2100,300,200,CONT_TURN8,* +B 400,2100,400,200,CONT_TURN8,* +V 900,3900,CONT_DIF_P,* +V 900,3400,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 1500,600,CONT_DIF_N,* +V 1500,1300,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1000,2100,CONT_POLY,* +V 2000,2100,CONT_POLY,* +V 300,2100,CONT_POLY,* +V 2500,2100,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa2a22_x1.vbe b/pdks/symbolic/lsxlib/cells/noa2a22_x1.vbe new file mode 100644 index 000000000..d63481981 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i3_nq : NATURAL := 256; + CONSTANT tphl_i2_nq : NATURAL := 284; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i2_nq : NATURAL := 289; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT tphl_i3_nq : NATURAL := 372; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa2a22_x4.ap b/pdks/symbolic/lsxlib/cells/noa2a22_x4.ap new file mode 100644 index 000000000..28b9802fd --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a22_x4.ap @@ -0,0 +1,155 @@ +V ALLIANCE : 6 +H noa2a22_x4,P, 1/ 8/2024,100 +A 0,0,5500,5000 +S 0,1100,5500,1100,1400,*,RIGHT,PWELL +S 300,2100,600,2100,100,*,RIGHT,POLY +S 2400,1100,2400,3400,100,*,DOWN,POLY +S 1800,1100,1800,3400,100,*,DOWN,POLY +S 1200,1100,1200,3400,100,*,DOWN,POLY +S 600,1100,600,3400,100,*,DOWN,POLY +S 300,3600,300,4500,300,*,DOWN,PDIF +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 2700,3600,2700,4500,300,*,DOWN,PDIF +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 2100,3600,2100,4500,300,*,DOWN,PDIF +S 2400,3400,2400,4700,100,*,UP,PTRANS +S 1200,3400,1200,4700,100,*,UP,PTRANS +S 900,3600,900,4500,300,*,DOWN,PDIF +S 600,3400,600,4700,100,*,UP,PTRANS +S 2400,300,2400,1100,100,*,DOWN,NTRANS +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 2700,500,2700,900,300,*,UP,NDIF +S 2100,500,2100,900,300,*,UP,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 3400,4400,3500,4400,200,*,LEFT,ALU1 +S 3400,3700,3500,3700,200,*,LEFT,ALU1 +S 3400,600,3500,600,200,*,LEFT,ALU1 +S 1500,600,1500,3400,200,*,DOWN,ALU1 +S 4600,600,4600,4400,200,nq,UP,CALU1 +S 0,0,5500,0,300,*,RIGHT,PTIE +S 0,0,5500,0,400,vss,RIGHT,CALU1 +S 0,5000,5500,5000,300,*,RIGHT,NTIE +S 0,4000,5500,4000,1200,*,RIGHT,NWELL +S 0,3100,5500,3100,1200,*,RIGHT,NWELL +S 0,5000,5500,5000,400,vdd,RIGHT,CALU1 +S 1500,1100,3000,1100,200,*,RIGHT,ALU1 +S 3000,1100,3000,2100,200,*,UP,ALU1 +S 2000,1600,2000,3400,200,i3,DOWN,CALU1 +S 2500,1600,2500,3400,200,i2,DOWN,CALU1 +S 3000,2100,3700,2100,100,*,LEFT,POLY +S 3700,3400,3700,4700,100,*,DOWN,PTRANS +S 4000,2600,4000,4500,300,*,UP,PDIF +S 4900,2400,4900,4700,100,*,DOWN,PTRANS +S 4300,2400,4300,4700,100,*,DOWN,PTRANS +S 4600,2600,4600,4500,300,*,DOWN,PDIF +S 5200,2600,5200,4500,300,*,UP,PDIF +S 3400,3600,3400,4500,300,*,DOWN,PDIF +S 3700,300,3700,1100,100,*,UP,NTRANS +S 4300,300,4300,1600,100,*,UP,NTRANS +S 4900,300,4900,1600,100,*,UP,NTRANS +S 4600,500,4600,1400,300,*,DOWN,NDIF +S 5200,500,5200,1400,300,*,DOWN,NDIF +S 3400,500,3400,900,300,*,DOWN,NDIF +S 4000,500,4000,1400,300,*,DOWN,NDIF +S 4300,1600,4300,2400,100,*,UP,POLY +S 4900,1600,4900,2400,100,*,DOWN,POLY +S 4100,2100,4900,2100,200,*,RIGHT,POLY +S 3700,1100,3700,3400,100,*,UP,POLY +S 4000,0,4000,1300,200,*,DOWN,ALU1 +S 5200,0,5200,1300,200,*,DOWN,ALU1 +S 3500,600,3500,4400,200,*,UP,ALU1 +S 3500,2100,4100,2100,200,*,RIGHT,ALU1 +S 5200,2700,5200,5000,200,*,UP,ALU1 +S 4000,2700,4000,5000,200,*,UP,ALU1 +S 2700,0,2700,600,200,*,DOWN,ALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 900,3400,900,3900,200,*,DOWN,ALU1 +S 1500,3900,2700,3900,200,*,RIGHT,ALU1 +S 300,4400,1500,4400,200,*,RIGHT,ALU1 +S 900,3400,1500,3400,200,*,RIGHT,ALU1 +S 2700,3900,2700,4400,200,*,DOWN,ALU1 +S 1500,3900,1500,4400,200,*,DOWN,ALU1 +S 300,3900,300,4400,200,*,DOWN,ALU1 +S 300,1100,300,3400,200,i0,DOWN,CALU1 +S 1000,600,1000,2900,200,i1,DOWN,CALU1 +S 1000,2100,1200,2100,200,*,RIGHT,POLY +S 1800,2100,2000,2100,200,*,RIGHT,POLY +B 2500,2100,200,200,CONT_TURN8,* +B 3300,2100,800,200,CONT_TURN8,* +B 4450,2100,900,200,CONT_TURN8,* +B 1950,2100,300,200,CONT_TURN8,* +B 1050,2100,300,200,CONT_TURN8,* +B 400,2100,400,200,CONT_TURN8,* +B 3500,4400,200,200,CONT_TURN1,* +B 3500,600,200,200,CONT_TURN1,* +B 3000,1100,200,200,CONT_TURN1,* +B 1500,3400,200,200,CONT_TURN1,* +B 900,3400,200,200,CONT_TURN1,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,2100,CONT_POLY,* +V 4600,4400,CONT_DIF_P,* +V 4600,3800,CONT_DIF_P,* +V 3400,4400,CONT_DIF_P,* +V 3400,3700,CONT_DIF_P,* +V 4000,3200,CONT_DIF_P,* +V 4000,2700,CONT_DIF_P,* +V 4000,3800,CONT_DIF_P,* +V 4000,4400,CONT_DIF_P,* +V 5200,4400,CONT_DIF_P,* +V 4600,3200,CONT_DIF_P,* +V 5200,3800,CONT_DIF_P,* +V 5200,2700,CONT_DIF_P,* +V 5200,3200,CONT_DIF_P,* +V 4600,2700,CONT_DIF_P,* +V 5200,600,CONT_DIF_N,* +V 4600,600,CONT_DIF_N,* +V 4600,1300,CONT_DIF_N,* +V 3400,600,CONT_DIF_N,* +V 4000,1300,CONT_DIF_N,* +V 4000,600,CONT_DIF_N,* +V 5200,1300,CONT_DIF_N,* +V 4100,2100,CONT_POLY,* +V 900,3900,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 1500,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1000,2100,CONT_POLY,* +V 2000,2100,CONT_POLY,* +V 300,2100,CONT_POLY,* +V 2500,2100,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa2a22_x4.vbe b/pdks/symbolic/lsxlib/cells/noa2a22_x4.vbe new file mode 100644 index 000000000..93e31d341 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 562; + CONSTANT tphl_i1_nq : NATURAL := 646; + CONSTANT tplh_i3_nq : NATURAL := 677; + CONSTANT tphl_i2_nq : NATURAL := 701; + CONSTANT tplh_i2_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 714; + CONSTANT tplh_i0_nq : NATURAL := 745; + CONSTANT tphl_i3_nq : NATURAL := 805; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa2a2a23_x1.ap b/pdks/symbolic/lsxlib/cells/noa2a2a23_x1.ap new file mode 100644 index 000000000..bc5fc3c9c --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a2a23_x1.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 6 +H noa2a2a23_x1,P, 1/ 8/2024,100 +A 0,0,5000,5000 +S 0,1100,5000,1100,1400,*,RIGHT,PWELL +S 400,2100,700,2100,100,*,RIGHT,POLY +S 4000,500,4000,1400,300,*,DOWN,NDIF +S 2700,1600,2700,3400,200,i2,DOWN,CALU1 +S 2100,1600,2100,2900,200,i3,DOWN,CALU1 +S 1600,600,1600,3400,200,nq,DOWN,CALU1 +S 3400,2600,3400,4500,300,*,DOWN,PDIF +S 4000,2600,4000,4500,300,*,DOWN,PDIF +S 4300,2400,4300,4700,100,*,UP,PTRANS +S 4600,2600,4600,4500,300,*,DOWN,PDIF +S 3700,2400,3700,4700,100,*,UP,PTRANS +S 700,2400,700,4700,100,*,UP,PTRANS +S 400,2600,400,4500,300,*,DOWN,PDIF +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 2800,2600,2800,4500,300,*,DOWN,PDIF +S 1900,2400,1900,4700,100,*,UP,PTRANS +S 2200,2600,2200,4500,300,*,DOWN,PDIF +S 2500,2400,2500,4700,100,*,UP,PTRANS +S 1300,2400,1300,4700,100,*,UP,PTRANS +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 2500,300,2500,1600,100,*,DOWN,NTRANS +S 1900,300,1900,1600,100,*,DOWN,NTRANS +S 1300,300,1300,1600,100,*,DOWN,NTRANS +S 700,300,700,1600,100,*,DOWN,NTRANS +S 3700,300,3700,1600,100,*,DOWN,NTRANS +S 4300,300,4300,1600,100,*,DOWN,NTRANS +S 3400,500,3400,1400,300,*,UP,NDIF +S 400,500,400,1400,300,*,UP,NDIF +S 2800,500,2800,1400,300,*,UP,NDIF +S 2200,500,2200,1400,300,*,UP,NDIF +S 1600,500,1600,1400,300,*,UP,NDIF +S 4600,500,4600,1400,300,*,UP,NDIF +S 1000,500,1000,1400,300,*,UP,NDIF +S 4300,1600,4300,2400,100,*,DOWN,POLY +S 3700,1600,3700,2400,100,*,UP,POLY +S 3700,2100,3900,2100,200,*,LEFT,POLY +S 4300,2100,4500,2100,200,*,RIGHT,POLY +S 2500,2100,2700,2100,200,*,LEFT,POLY +S 1900,1600,1900,2400,100,*,DOWN,POLY +S 1300,1600,1300,2400,100,*,DOWN,POLY +S 700,1600,700,2400,100,*,DOWN,POLY +S 1100,2100,1300,2100,200,*,RIGHT,POLY +S 1900,2100,2100,2100,200,*,RIGHT,POLY +S 2500,1600,2500,2400,100,*,DOWN,POLY +S 4600,0,4600,600,200,*,DOWN,ALU1 +S 2800,0,2800,600,200,*,DOWN,ALU1 +S 400,0,400,600,200,*,DOWN,ALU1 +S 3400,4400,3400,5000,200,*,UP,ALU1 +S 4000,3900,4000,4400,200,*,DOWN,ALU1 +S 3400,600,3400,1100,200,*,UP,ALU1 +S 400,4400,2800,4400,200,*,RIGHT,ALU1 +S 1600,1100,3400,1100,200,*,LEFT,ALU1 +S 4600,3400,4600,5000,200,*,UP,ALU1 +S 4500,1100,4500,2900,200,i4,DOWN,CALU1 +S 2200,3900,4000,3900,200,*,LEFT,ALU1 +S 1600,3900,1600,4400,200,*,DOWN,ALU1 +S 400,3900,400,4400,200,*,DOWN,ALU1 +S 400,1100,400,3400,200,i0,DOWN,CALU1 +S 3400,3400,4600,3400,200,*,RIGHT,ALU1 +S 3900,600,3900,2900,200,i5,DOWN,CALU1 +S 1100,600,1100,2900,200,i1,DOWN,CALU1 +S 2200,3400,2200,3900,200,*,DOWN,ALU1 +S 1000,3400,1000,3900,200,*,DOWN,ALU1 +S 1000,3400,1600,3400,200,*,RIGHT,ALU1 +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +S 0,0,5000,0,300,*,RIGHT,PTIE +S 0,0,5000,0,400,vss,RIGHT,CALU1 +B 4450,2100,300,200,CONT_TURN8,* +B 3850,2100,300,200,CONT_TURN8,* +B 2650,2100,300,200,CONT_TURN8,* +B 2050,2100,300,200,CONT_TURN8,* +B 1150,2100,300,200,CONT_TURN8,* +B 500,2100,400,200,CONT_TURN8,* +V 4600,3400,CONT_DIF_P,* +V 3400,4400,CONT_DIF_P,* +V 3400,3400,CONT_DIF_P,* +V 4600,3900,CONT_DIF_P,* +V 2200,3400,CONT_DIF_P,* +V 2800,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 4000,3900,CONT_DIF_P,* +V 1000,3900,CONT_DIF_P,* +V 1000,3400,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 1600,3900,CONT_DIF_P,* +V 2200,3900,CONT_DIF_P,* +V 4600,4400,CONT_DIF_P,* +V 4000,4400,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 1600,1100,CONT_DIF_N,* +V 3400,1100,CONT_DIF_N,* +V 3400,600,CONT_DIF_N,* +V 4600,600,CONT_DIF_N,* +V 2800,600,CONT_DIF_N,* +V 4500,2100,CONT_POLY,* +V 2100,2100,CONT_POLY,* +V 400,2100,CONT_POLY,* +V 2700,2100,CONT_POLY,* +V 3900,2100,CONT_POLY,* +V 1100,2100,CONT_POLY,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa2a2a23_x1.vbe b/pdks/symbolic/lsxlib/cells/noa2a2a23_x1.vbe new file mode 100644 index 000000000..2d90886a0 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a2a23_x1.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT rup_i3_nq : NATURAL := 4690; + CONSTANT rup_i4_nq : NATURAL := 4690; + CONSTANT rup_i5_nq : NATURAL := 4690; + CONSTANT tphl_i5_nq : NATURAL := 178; + CONSTANT tphl_i4_nq : NATURAL := 250; + CONSTANT tphl_i2_nq : NATURAL := 307; + CONSTANT tplh_i1_nq : NATURAL := 388; + CONSTANT tphl_i3_nq : NATURAL := 398; + CONSTANT tplh_i4_nq : NATURAL := 416; + CONSTANT tplh_i0_nq : NATURAL := 425; + CONSTANT tplh_i3_nq : NATURAL := 438; + CONSTANT tplh_i5_nq : NATURAL := 464; + CONSTANT tplh_i2_nq : NATURAL := 479; + CONSTANT tphl_i0_nq : NATURAL := 525; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa2a2a23_x4.ap b/pdks/symbolic/lsxlib/cells/noa2a2a23_x4.ap new file mode 100644 index 000000000..f06b3ec99 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a2a23_x4.ap @@ -0,0 +1,188 @@ +V ALLIANCE : 6 +H noa2a2a23_x4,P, 1/ 8/2024,100 +A 0,0,7500,5000 +S 0,1100,7500,1100,1400,*,RIGHT,PWELL +S 400,2100,700,2100,100,*,RIGHT,POLY +S 0,0,7500,0,400,vss,RIGHT,CALU1 +S 0,5000,7500,5000,400,vdd,RIGHT,CALU1 +S 0,0,7500,0,300,*,RIGHT,PTIE +S 4000,500,4000,900,300,*,DOWN,NDIF +S 1600,1100,4700,1100,200,*,RIGHT,ALU1 +S 0,5000,7500,5000,300,*,RIGHT,NTIE +S 3700,1100,3700,3400,100,*,UP,POLY +S 4300,1100,4300,3400,100,*,DOWN,POLY +S 2500,1100,2500,3400,100,*,DOWN,POLY +S 1900,1100,1900,3400,100,*,DOWN,POLY +S 1300,1100,1300,3400,100,*,DOWN,POLY +S 700,1100,700,3400,100,*,DOWN,POLY +S 1600,3600,1600,4500,300,*,DOWN,PDIF +S 2800,3600,2800,4500,300,*,DOWN,PDIF +S 1900,3400,1900,4700,100,*,UP,PTRANS +S 2200,3600,2200,4500,300,*,DOWN,PDIF +S 2500,3400,2500,4700,100,*,UP,PTRANS +S 1300,3400,1300,4700,100,*,UP,PTRANS +S 1000,3600,1000,4500,300,*,DOWN,PDIF +S 3400,3600,3400,4500,300,*,DOWN,PDIF +S 4000,3600,4000,4500,300,*,DOWN,PDIF +S 4300,3400,4300,4700,100,*,UP,PTRANS +S 4600,3600,4600,4500,300,*,DOWN,PDIF +S 3700,3400,3700,4700,100,*,UP,PTRANS +S 700,3400,700,4700,100,*,UP,PTRANS +S 400,3600,400,4500,300,*,DOWN,PDIF +S 4300,300,4300,1100,100,*,DOWN,NTRANS +S 2500,300,2500,1100,100,*,DOWN,NTRANS +S 1900,300,1900,1100,100,*,DOWN,NTRANS +S 1300,300,1300,1100,100,*,DOWN,NTRANS +S 700,300,700,1100,100,*,DOWN,NTRANS +S 3700,300,3700,1100,100,*,DOWN,NTRANS +S 2800,500,2800,900,300,*,UP,NDIF +S 2200,500,2200,900,300,*,UP,NDIF +S 1600,500,1600,900,300,*,UP,NDIF +S 4600,500,4600,900,300,*,UP,NDIF +S 1000,500,1000,900,300,*,UP,NDIF +S 3400,500,3400,900,300,*,UP,NDIF +S 400,500,400,900,300,*,UP,NDIF +S 4100,1600,4100,3400,200,i4,DOWN,CALU1 +S 3600,1600,3600,3400,200,i5,DOWN,CALU1 +S 2700,1600,2700,3400,200,i2,DOWN,CALU1 +S 2100,1600,2100,2900,200,i3,DOWN,CALU1 +S 1600,600,1600,3400,200,*,DOWN,ALU1 +S 6400,600,6400,4400,200,nq,DOWN,CALU1 +S 0,4000,7500,4000,1200,*,RIGHT,NWELL +S 0,3100,7500,3100,1200,*,RIGHT,NWELL +S 4600,3900,4600,5000,200,*,UP,ALU1 +S 4700,2100,5500,2100,200,*,RIGHT,POLY +S 5900,2100,6700,2100,200,*,RIGHT,POLY +S 5200,2100,5800,2100,200,*,RIGHT,ALU1 +S 4700,1100,4700,2100,200,*,UP,ALU1 +S 4100,2100,4300,2100,200,*,RIGHT,POLY +S 3600,2100,3700,2100,200,*,RIGHT,POLY +S 5200,3600,5200,4500,300,*,DOWN,PDIF +S 5500,3400,5500,4700,100,*,DOWN,PTRANS +S 6400,2600,6400,4500,300,*,DOWN,PDIF +S 5800,2600,5800,4500,300,*,DOWN,PDIF +S 6100,2400,6100,4700,100,*,UP,PTRANS +S 6700,2400,6700,4700,100,*,UP,PTRANS +S 7000,2600,7000,4500,300,*,DOWN,PDIF +S 6100,300,6100,1600,100,*,DOWN,NTRANS +S 6700,300,6700,1600,100,*,DOWN,NTRANS +S 5500,300,5500,1100,100,*,UP,NTRANS +S 5200,500,5200,900,300,*,UP,NDIF +S 7000,500,7000,1400,300,*,UP,NDIF +S 5800,500,5800,1400,300,*,UP,NDIF +S 6400,500,6400,1400,300,*,UP,NDIF +S 5500,1100,5500,3400,100,*,DOWN,POLY +S 6700,1600,6700,2400,100,*,DOWN,POLY +S 6100,1600,6100,2400,100,*,DOWN,POLY +S 5800,0,5800,1300,200,*,DOWN,ALU1 +S 7000,0,7000,1300,200,*,DOWN,ALU1 +S 5200,600,5200,4400,200,*,DOWN,ALU1 +S 7000,2700,7000,5000,200,*,UP,ALU1 +S 5800,2700,5800,5000,200,*,UP,ALU1 +S 2500,2100,2700,2100,200,*,LEFT,POLY +S 1100,2100,1300,2100,200,*,RIGHT,POLY +S 1900,2100,2100,2100,200,*,RIGHT,POLY +S 4600,0,4600,600,200,*,DOWN,ALU1 +S 2800,0,2800,600,200,*,DOWN,ALU1 +S 400,0,400,600,200,*,DOWN,ALU1 +S 3400,4400,3400,5000,200,*,UP,ALU1 +S 4000,3900,4000,4400,200,*,DOWN,ALU1 +S 3400,600,3400,1100,200,*,UP,ALU1 +S 400,4400,2800,4400,200,*,RIGHT,ALU1 +S 2200,3900,4000,3900,200,*,LEFT,ALU1 +S 1600,3900,1600,4400,200,*,DOWN,ALU1 +S 400,3900,400,4400,200,*,DOWN,ALU1 +S 400,1100,400,3400,200,i0,DOWN,CALU1 +S 1100,600,1100,2900,200,i1,DOWN,CALU1 +S 1000,3400,1000,3900,200,*,DOWN,ALU1 +S 1000,3400,1600,3400,200,*,RIGHT,ALU1 +B 6250,2100,900,200,CONT_TURN8,* +B 5050,2100,900,200,CONT_TURN8,* +B 4150,2100,300,200,CONT_TURN8,* +B 3600,2100,200,200,CONT_TURN8,* +B 2650,2100,300,200,CONT_TURN8,* +B 2050,2100,300,200,CONT_TURN8,* +B 1150,2100,300,200,CONT_TURN8,* +B 500,2100,400,200,CONT_TURN8,* +B 1600,3400,200,200,CONT_TURN1,* +B 1000,3400,200,200,CONT_TURN1,* +B 4700,1100,200,200,CONT_TURN1,* +V 5500,5000,CONT_BODY_N,* +V 7000,5000,CONT_BODY_N,* +V 7500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 6500,5000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6500,0,CONT_BODY_P,* +V 7000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 7500,0,CONT_BODY_P,* +V 5900,2100,CONT_POLY,* +V 4700,2100,CONT_POLY,* +V 3600,2100,CONT_POLY,* +V 4100,2100,CONT_POLY,* +V 5200,3900,CONT_DIF_P,* +V 5800,4400,CONT_DIF_P,* +V 5800,3300,CONT_DIF_P,* +V 5800,2700,CONT_DIF_P,* +V 5800,3900,CONT_DIF_P,* +V 5200,4400,CONT_DIF_P,* +V 6400,3900,CONT_DIF_P,* +V 6400,4400,CONT_DIF_P,* +V 6400,3300,CONT_DIF_P,* +V 6400,2700,CONT_DIF_P,* +V 7000,3900,CONT_DIF_P,* +V 7000,2700,CONT_DIF_P,* +V 7000,3300,CONT_DIF_P,* +V 7000,4400,CONT_DIF_P,* +V 7000,1300,CONT_DIF_N,* +V 5200,600,CONT_DIF_N,* +V 5800,600,CONT_DIF_N,* +V 6400,600,CONT_DIF_N,* +V 6400,1300,CONT_DIF_N,* +V 5800,1300,CONT_DIF_N,* +V 7000,600,CONT_DIF_N,* +V 3400,4400,CONT_DIF_P,* +V 4600,3900,CONT_DIF_P,* +V 2800,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 4000,3900,CONT_DIF_P,* +V 1000,3900,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 1600,3900,CONT_DIF_P,* +V 2200,3900,CONT_DIF_P,* +V 4600,4400,CONT_DIF_P,* +V 4000,4400,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 3400,600,CONT_DIF_N,* +V 4600,600,CONT_DIF_N,* +V 2800,600,CONT_DIF_N,* +V 2100,2100,CONT_POLY,* +V 400,2100,CONT_POLY,* +V 2700,2100,CONT_POLY,* +V 1100,2100,CONT_POLY,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa2a2a23_x4.vbe b/pdks/symbolic/lsxlib/cells/noa2a2a23_x4.vbe new file mode 100644 index 000000000..328209403 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT tphl_i5_nq : NATURAL := 496; + CONSTANT tphl_i4_nq : NATURAL := 574; + CONSTANT tphl_i2_nq : NATURAL := 620; + CONSTANT tphl_i3_nq : NATURAL := 716; + CONSTANT tplh_i1_nq : NATURAL := 778; + CONSTANT tplh_i0_nq : NATURAL := 814; + CONSTANT tplh_i4_nq : NATURAL := 819; + CONSTANT tplh_i3_nq : NATURAL := 833; + CONSTANT tphl_i0_nq : NATURAL := 834; + CONSTANT tplh_i5_nq : NATURAL := 865; + CONSTANT tplh_i2_nq : NATURAL := 873; + CONSTANT tphl_i1_nq : NATURAL := 955; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1600 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x1.ap b/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x1.ap new file mode 100644 index 000000000..e96c51d07 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x1.ap @@ -0,0 +1,150 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x1,P, 1/ 8/2024,100 +A 0,0,6000,5000 +S 0,1100,6000,1100,1400,*,RIGHT,PWELL +S 5400,2100,5700,2100,100,*,RIGHT,POLY +S 3300,2100,3600,2100,100,*,RIGHT,POLY +S 300,2100,600,2100,100,*,RIGHT,POLY +S 0,5000,6000,5000,300,*,RIGHT,NTIE +S 0,4000,6000,4000,1200,*,RIGHT,NWELL +S 0,3100,6000,3100,1200,*,RIGHT,NWELL +S 0,5000,6000,5000,400,vdd,RIGHT,CALU1 +S 0,0,6000,0,300,*,RIGHT,PTIE +S 0,0,6000,0,400,vss,RIGHT,CALU1 +S 5700,1100,5700,3900,200,i7,DOWN,CALU1 +S 4000,1600,4000,3400,200,i5,DOWN,CALU1 +S 4600,1600,4600,3400,200,i6,DOWN,CALU1 +S 3300,1600,3300,3400,200,i4,DOWN,CALU1 +S 4500,600,4500,1100,200,*,DOWN,ALU1 +S 1500,1100,5100,1100,200,*,LEFT,ALU1 +S 5100,1100,5100,3900,200,*,DOWN,ALU1 +S 4600,2100,4800,2100,200,*,RIGHT,POLY +S 2000,1600,2000,3400,200,i3,DOWN,CALU1 +S 1000,600,1000,3400,200,i1,DOWN,CALU1 +S 2500,1600,2500,3400,200,i2,DOWN,CALU1 +S 1500,3900,1500,4400,200,*,DOWN,ALU1 +S 4500,4400,5700,4400,200,*,RIGHT,ALU1 +S 4500,3900,4500,4400,200,*,UP,ALU1 +S 3300,3900,4500,3900,200,*,RIGHT,ALU1 +S 2100,4400,3900,4400,200,*,RIGHT,ALU1 +S 300,3900,2700,3900,200,*,RIGHT,ALU1 +S 300,3900,300,4400,200,*,DOWN,ALU1 +S 900,4400,900,5000,200,*,UP,ALU1 +S 3600,2400,3600,4700,100,*,UP,PTRANS +S 3300,2600,3300,4500,300,*,DOWN,PDIF +S 4500,2600,4500,4500,300,*,DOWN,PDIF +S 5700,2600,5700,4500,300,*,DOWN,PDIF +S 4800,2400,4800,4700,100,*,UP,PTRANS +S 5100,2600,5100,4500,300,*,DOWN,PDIF +S 5400,2400,5400,4700,100,*,UP,PTRANS +S 4200,2400,4200,4700,100,*,UP,PTRANS +S 3900,2600,3900,4500,300,*,DOWN,PDIF +S 5400,300,5400,1600,100,*,DOWN,NTRANS +S 4800,300,4800,1600,100,*,DOWN,NTRANS +S 4200,300,4200,1600,100,*,DOWN,NTRANS +S 3600,300,3600,1600,100,*,DOWN,NTRANS +S 3300,500,3300,1400,300,*,UP,NDIF +S 5700,500,5700,1400,300,*,UP,NDIF +S 5100,500,5100,1400,300,*,UP,NDIF +S 4500,500,4500,1400,300,*,UP,NDIF +S 3900,500,3900,1400,300,*,UP,NDIF +S 4800,1600,4800,2400,100,*,DOWN,POLY +S 4200,1600,4200,2400,100,*,DOWN,POLY +S 3600,1600,3600,2400,100,*,DOWN,POLY +S 4000,2100,4200,2100,200,*,RIGHT,POLY +S 5400,1600,5400,2400,100,*,DOWN,POLY +S 5700,0,5700,600,200,*,DOWN,ALU1 +S 3300,0,3300,600,200,*,DOWN,ALU1 +S 2700,0,2700,600,200,*,DOWN,ALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +S 300,1100,300,3400,200,i0,DOWN,CALU1 +S 1500,600,1500,3400,200,nq,DOWN,CALU1 +S 1000,2100,1200,2100,200,*,RIGHT,POLY +S 1800,2100,2000,2100,200,*,RIGHT,POLY +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 2400,2400,2400,4700,100,*,UP,PTRANS +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 600,2400,600,4700,100,*,UP,PTRANS +S 300,2600,300,4500,300,*,DOWN,PDIF +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 2400,1600,2400,2400,100,*,DOWN,POLY +S 1800,1600,1800,2400,100,*,DOWN,POLY +S 1200,1600,1200,2400,100,*,DOWN,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +S 900,500,900,1400,300,*,UP,NDIF +S 2400,300,2400,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 600,300,600,1600,100,*,DOWN,NTRANS +S 300,500,300,1400,300,*,UP,NDIF +S 2700,500,2700,1400,300,*,UP,NDIF +S 2100,500,2100,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +B 4650,2100,300,200,CONT_TURN8,* +B 4050,2100,300,200,CONT_TURN8,* +B 2500,2100,200,200,CONT_TURN8,* +B 1950,2100,300,200,CONT_TURN8,* +B 1050,2100,300,200,CONT_TURN8,* +B 5600,2100,400,200,CONT_TURN8,* +B 3400,2100,400,200,CONT_TURN8,* +B 400,2100,400,200,CONT_TURN8,* +B 5100,1100,200,200,CONT_TURN1,* +V 5000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 4500,600,CONT_DIF_N,* +V 4500,1100,CONT_DIF_N,* +V 5700,2100,CONT_POLY,* +V 4600,2100,CONT_POLY,* +V 1500,4400,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 4500,4400,CONT_DIF_P,* +V 5100,3900,CONT_DIF_P,* +V 4500,3900,CONT_DIF_P,* +V 3300,3900,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 5700,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 3300,600,CONT_DIF_N,* +V 5700,600,CONT_DIF_N,* +V 3300,2100,CONT_POLY,* +V 4000,2100,CONT_POLY,* +V 1500,600,CONT_DIF_N,* +V 1500,1300,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1000,2100,CONT_POLY,* +V 2000,2100,CONT_POLY,* +V 300,2100,CONT_POLY,* +V 2500,2100,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x1.vbe b/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x1.vbe new file mode 100644 index 000000000..ed253ca47 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x1.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rdown_i6_nq : NATURAL := 2850; + CONSTANT rdown_i7_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT rup_i4_nq : NATURAL := 6190; + CONSTANT rup_i5_nq : NATURAL := 6190; + CONSTANT rup_i6_nq : NATURAL := 6190; + CONSTANT rup_i7_nq : NATURAL := 6190; + CONSTANT tphl_i7_nq : NATURAL := 200; + CONSTANT tphl_i6_nq : NATURAL := 270; + CONSTANT tphl_i5_nq : NATURAL := 329; + CONSTANT tphl_i4_nq : NATURAL := 419; + CONSTANT tplh_i6_nq : NATURAL := 535; + CONSTANT tphl_i2_nq : NATURAL := 550; + CONSTANT tplh_i1_nq : NATURAL := 562; + CONSTANT tplh_i7_nq : NATURAL := 591; + CONSTANT tplh_i0_nq : NATURAL := 606; + CONSTANT tplh_i4_nq : NATURAL := 613; + CONSTANT tplh_i3_nq : NATURAL := 616; + CONSTANT tphl_i0_nq : NATURAL := 649; + CONSTANT tplh_i2_nq : NATURAL := 662; + CONSTANT tplh_i5_nq : NATURAL := 662; + CONSTANT tphl_i3_nq : NATURAL := 667; + CONSTANT tphl_i1_nq : NATURAL := 775; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x1" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x4.ap b/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x4.ap new file mode 100644 index 000000000..4b3dcf139 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x4.ap @@ -0,0 +1,212 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x4,P, 1/ 8/2024,100 +A 0,0,8500,5000 +S 0,1100,8500,1100,1400,*,RIGHT,PWELL +S 3300,2100,3600,2100,100,*,RIGHT,POLY +S 300,2100,600,2100,100,*,RIGHT,POLY +S 1500,600,1500,1100,200,*,DOWN,ALU1 +S 600,1100,600,3400,100,*,DOWN,POLY +S 1200,1100,1200,3400,100,*,DOWN,POLY +S 1800,1100,1800,3400,100,*,DOWN,POLY +S 2400,1100,2400,3400,100,*,DOWN,POLY +S 3600,1100,3600,3400,100,*,DOWN,POLY +S 4200,1100,4200,3400,100,*,DOWN,POLY +S 4800,1100,4800,3400,100,*,DOWN,POLY +S 5400,1100,5400,3400,100,*,DOWN,POLY +S 600,3400,600,4700,100,*,UP,PTRANS +S 300,3600,300,4500,300,*,DOWN,PDIF +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 4200,3400,4200,4700,100,*,UP,PTRANS +S 3900,3600,3900,4500,300,*,DOWN,PDIF +S 2700,3600,2700,4500,300,*,DOWN,PDIF +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 2100,3600,2100,4500,300,*,DOWN,PDIF +S 2400,3400,2400,4700,100,*,UP,PTRANS +S 1200,3400,1200,4700,100,*,UP,PTRANS +S 900,3600,900,4500,300,*,DOWN,PDIF +S 3600,3400,3600,4700,100,*,UP,PTRANS +S 3300,3600,3300,4500,300,*,DOWN,PDIF +S 4500,3600,4500,4500,300,*,DOWN,PDIF +S 5700,3600,5700,4500,300,*,DOWN,PDIF +S 4800,3400,4800,4700,100,*,UP,PTRANS +S 5100,3600,5100,4500,300,*,DOWN,PDIF +S 5400,3400,5400,4700,100,*,UP,PTRANS +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 5400,300,5400,1100,100,*,DOWN,NTRANS +S 4800,300,4800,1100,100,*,DOWN,NTRANS +S 4200,300,4200,1100,100,*,DOWN,NTRANS +S 3600,300,3600,1100,100,*,DOWN,NTRANS +S 2400,300,2400,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 2700,500,2700,900,300,*,UP,NDIF +S 2100,500,2100,900,300,*,UP,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 3300,500,3300,900,300,*,UP,NDIF +S 5700,500,5700,900,300,*,UP,NDIF +S 5100,500,5100,900,300,*,UP,NDIF +S 4500,500,4500,900,300,*,UP,NDIF +S 3900,500,3900,900,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 0,5000,8500,5000,300,*,RIGHT,NTIE +S 0,4000,8500,4000,1200,*,RIGHT,NWELL +S 0,3100,8500,3100,1200,*,RIGHT,NWELL +S 0,5000,8500,5000,400,vdd,RIGHT,CALU1 +S 0,0,8500,0,300,*,RIGHT,PTIE +S 0,0,8500,0,400,vss,RIGHT,CALU1 +S 7500,600,7500,4400,200,nq,DOWN,CALU1 +S 5100,3900,5800,3900,200,*,RIGHT,ALU1 +S 1500,1100,5800,1100,200,*,LEFT,ALU1 +S 5800,2100,6600,2100,200,*,RIGHT,POLY +S 5800,1100,5800,3900,200,*,DOWN,ALU1 +S 5200,2100,5400,2100,200,*,LEFT,POLY +S 5200,1600,5200,3400,200,i7,DOWN,CALU1 +S 6900,2600,6900,4500,300,*,DOWN,PDIF +S 7200,2400,7200,4700,100,*,UP,PTRANS +S 7800,2400,7800,4700,100,*,UP,PTRANS +S 8100,2600,8100,4500,300,*,DOWN,PDIF +S 6300,3600,6300,4500,300,*,DOWN,PDIF +S 6600,3400,6600,4700,100,*,DOWN,PTRANS +S 7500,2600,7500,4500,300,*,DOWN,PDIF +S 7800,300,7800,1600,100,*,DOWN,NTRANS +S 6600,300,6600,1100,100,*,UP,NTRANS +S 7200,300,7200,1600,100,*,DOWN,NTRANS +S 6300,500,6300,900,300,*,UP,NDIF +S 8100,500,8100,1400,300,*,UP,NDIF +S 6900,500,6900,1400,300,*,UP,NDIF +S 7500,500,7500,1400,300,*,UP,NDIF +S 6600,1100,6600,3400,100,*,DOWN,POLY +S 7800,1600,7800,2400,100,*,DOWN,POLY +S 7200,1600,7200,2400,100,*,DOWN,POLY +S 7000,2100,7800,2100,200,*,RIGHT,POLY +S 6900,0,6900,1300,200,*,DOWN,ALU1 +S 8100,0,8100,1300,200,*,DOWN,ALU1 +S 6900,2700,6900,5000,200,*,UP,ALU1 +S 6300,2100,6900,2100,200,*,RIGHT,ALU1 +S 6300,600,6300,4400,200,*,DOWN,ALU1 +S 8100,2700,8100,5000,200,*,UP,ALU1 +S 4000,1600,4000,3400,200,i5,DOWN,CALU1 +S 4600,1600,4600,3400,200,i6,DOWN,CALU1 +S 3300,1600,3300,3400,200,i4,DOWN,CALU1 +S 4500,600,4500,1100,200,*,DOWN,ALU1 +S 4600,2100,4800,2100,200,*,RIGHT,POLY +S 2000,1600,2000,3400,200,i3,DOWN,CALU1 +S 1000,600,1000,3400,200,i1,DOWN,CALU1 +S 2500,1600,2500,3400,200,i2,DOWN,CALU1 +S 1500,3900,1500,4400,200,*,DOWN,ALU1 +S 4500,4400,5700,4400,200,*,RIGHT,ALU1 +S 4500,3900,4500,4400,200,*,UP,ALU1 +S 3300,3900,4500,3900,200,*,RIGHT,ALU1 +S 2100,4400,3900,4400,200,*,RIGHT,ALU1 +S 300,3900,2700,3900,200,*,RIGHT,ALU1 +S 300,3900,300,4400,200,*,DOWN,ALU1 +S 900,4400,900,5000,200,*,UP,ALU1 +S 4000,2100,4200,2100,200,*,RIGHT,POLY +S 5700,0,5700,600,200,*,DOWN,ALU1 +S 3300,0,3300,600,200,*,DOWN,ALU1 +S 2700,0,2700,600,200,*,DOWN,ALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +S 300,1100,300,3400,200,i0,DOWN,CALU1 +S 1000,2100,1200,2100,200,*,RIGHT,POLY +S 1800,2100,2000,2100,200,*,RIGHT,POLY +B 7350,2100,900,200,CONT_TURN8,* +B 6150,2100,900,200,CONT_TURN8,* +B 5250,2100,300,200,CONT_TURN8,* +B 4650,2100,300,200,CONT_TURN8,* +B 4050,2100,300,200,CONT_TURN8,* +B 2500,2100,200,200,CONT_TURN8,* +B 1950,2100,300,200,CONT_TURN8,* +B 1050,2100,300,200,CONT_TURN8,* +B 3400,2100,400,200,CONT_TURN8,* +B 400,2100,400,200,CONT_TURN8,* +B 5800,3900,200,200,CONT_TURN1,* +B 5800,1100,200,200,CONT_TURN1,* +B 1500,1100,200,200,CONT_TURN1,* +V 6500,5000,CONT_BODY_N,* +V 7000,5000,CONT_BODY_N,* +V 7500,5000,CONT_BODY_N,* +V 8000,5000,CONT_BODY_N,* +V 8500,5000,CONT_BODY_N,* +V 6500,0,CONT_BODY_P,* +V 7000,0,CONT_BODY_P,* +V 7500,0,CONT_BODY_P,* +V 8000,0,CONT_BODY_P,* +V 8500,0,CONT_BODY_P,* +V 5800,2100,CONT_POLY,* +V 5200,2100,CONT_POLY,* +V 8100,3900,CONT_DIF_P,* +V 8100,2700,CONT_DIF_P,* +V 6300,3900,CONT_DIF_P,* +V 6900,4400,CONT_DIF_P,* +V 6900,3300,CONT_DIF_P,* +V 6900,2700,CONT_DIF_P,* +V 8100,3300,CONT_DIF_P,* +V 8100,4400,CONT_DIF_P,* +V 6900,3900,CONT_DIF_P,* +V 6300,4400,CONT_DIF_P,* +V 7500,3900,CONT_DIF_P,* +V 7500,4400,CONT_DIF_P,* +V 7500,3300,CONT_DIF_P,* +V 7500,2700,CONT_DIF_P,* +V 6900,1300,CONT_DIF_N,* +V 8100,600,CONT_DIF_N,* +V 8100,1300,CONT_DIF_N,* +V 6300,600,CONT_DIF_N,* +V 6900,600,CONT_DIF_N,* +V 7500,600,CONT_DIF_N,* +V 7500,1300,CONT_DIF_N,* +V 7000,2100,CONT_POLY,* +V 5000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 4500,600,CONT_DIF_N,* +V 4600,2100,CONT_POLY,* +V 1500,4400,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 4500,4400,CONT_DIF_P,* +V 5100,3900,CONT_DIF_P,* +V 4500,3900,CONT_DIF_P,* +V 3300,3900,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 5700,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 3300,600,CONT_DIF_N,* +V 5700,600,CONT_DIF_N,* +V 3300,2100,CONT_POLY,* +V 4000,2100,CONT_POLY,* +V 1500,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1000,2100,CONT_POLY,* +V 2000,2100,CONT_POLY,* +V 300,2100,CONT_POLY,* +V 2500,2100,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x4.vbe b/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x4.vbe new file mode 100644 index 000000000..2499cd710 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2a2a2a24_x4.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4250; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rdown_i7_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT rup_i7_nq : NATURAL := 890; + CONSTANT tphl_i7_nq : NATURAL := 525; + CONSTANT tphl_i6_nq : NATURAL := 606; + CONSTANT tphl_i5_nq : NATURAL := 649; + CONSTANT tphl_i4_nq : NATURAL := 748; + CONSTANT tphl_i2_nq : NATURAL := 867; + CONSTANT tphl_i0_nq : NATURAL := 966; + CONSTANT tphl_i3_nq : NATURAL := 990; + CONSTANT tplh_i6_nq : NATURAL := 999; + CONSTANT tplh_i1_nq : NATURAL := 1005; + CONSTANT tplh_i0_nq : NATURAL := 1049; + CONSTANT tplh_i7_nq : NATURAL := 1052; + CONSTANT tplh_i3_nq : NATURAL := 1061; + CONSTANT tplh_i4_nq : NATURAL := 1061; + CONSTANT tphl_i1_nq : NATURAL := 1097; + CONSTANT tplh_i2_nq : NATURAL := 1106; + CONSTANT tplh_i5_nq : NATURAL := 1109; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x4" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1700 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa2ao222_x1.ap b/pdks/symbolic/lsxlib/cells/noa2ao222_x1.ap new file mode 100644 index 000000000..36513d1db --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2ao222_x1.ap @@ -0,0 +1,110 @@ +V ALLIANCE : 6 +H noa2ao222_x1,P, 1/ 8/2024,100 +A 0,0,3500,5000 +S 0,1100,3500,1100,1400,*,RIGHT,PWELL +S 1500,3400,1500,4500,300,*,DOWN,PDIF +S 900,3400,900,4500,300,*,DOWN,PDIF +S 1500,3900,1500,4400,200,*,UP,ALU1 +S 300,3900,300,4400,200,*,DOWN,ALU1 +S 300,3900,1500,3900,200,*,RIGHT,ALU1 +S 1500,2100,1500,3400,200,i4,DOWN,CALU1 +S 1000,1100,1000,3400,200,i1,DOWN,CALU1 +S 500,1100,500,3400,200,i0,DOWN,CALU1 +S 2400,2100,2500,2100,200,*,RIGHT,POLY +S 1000,2100,1100,2100,200,*,RIGHT,POLY +S 500,2100,600,2100,200,*,RIGHT,POLY +S 2900,2100,3100,2100,200,*,LEFT,POLY +S 2500,2100,2600,2100,200,*,LEFT,ALU1 +S 2000,3900,2100,3900,200,*,LEFT,ALU1 +S 2000,2700,2100,2700,200,*,LEFT,ALU1 +S 1400,600,1500,600,200,*,LEFT,ALU1 +S 1700,3200,1800,3200,100,*,RIGHT,POLY +S 1100,3200,1200,3200,100,*,RIGHT,POLY +S 600,1200,600,3200,100,*,UP,POLY +S 1100,1200,1100,3200,100,*,UP,POLY +S 1700,1200,1700,3200,100,*,UP,POLY +S 2000,3300,2100,3300,200,*,LEFT,ALU1 +S 2100,2600,2100,4500,300,*,UP,PDIF +S 2000,1600,2000,3900,200,nq,DOWN,CALU1 +S 2600,1600,2600,3900,200,i2,DOWN,CALU1 +S 3100,1600,3100,3900,200,i3,DOWN,CALU1 +S 1500,2100,1700,2100,200,*,RIGHT,POLY +S 1500,4400,3200,4400,200,*,RIGHT,ALU1 +S 300,3400,300,4500,300,*,UP,PDIF +S 600,3200,600,4700,100,*,UP,PTRANS +S 1200,3200,1200,4700,100,*,DOWN,PTRANS +S 1800,3200,1800,4700,100,*,UP,PTRANS +S 2900,1200,2900,2400,100,*,UP,POLY +S 2400,1200,2400,2400,100,*,UP,POLY +S 2300,1200,2400,1200,100,*,RIGHT,POLY +S 2300,300,2300,1200,100,*,UP,NTRANS +S 1700,300,1700,1200,100,*,UP,NTRANS +S 1100,300,1100,1200,100,*,UP,NTRANS +S 2900,300,2900,1200,100,*,UP,NTRANS +S 600,300,600,1200,100,*,UP,NTRANS +S 1400,500,1400,1000,200,*,UP,NDIF +S 3200,500,3200,1000,300,*,UP,NDIF +S 300,500,300,1000,300,*,UP,NDIF +S 2600,500,2600,1000,300,*,UP,NDIF +S 2000,500,2000,1000,200,*,UP,NDIF +S 2900,2400,2900,4700,100,*,UP,PTRANS +S 3200,2600,3200,4500,300,*,UP,PDIF +S 2400,2400,2400,4700,100,*,UP,PTRANS +S 2700,2600,2700,4500,200,*,UP,PDIF +S 3200,600,3200,1100,200,*,DOWN,ALU1 +S 2000,1100,3200,1100,200,*,RIGHT,ALU1 +S 2000,600,2000,1100,200,*,UP,ALU1 +S 1500,600,1500,1600,200,nq,DOWN,CALU1 +S 1500,1600,2000,1600,200,*,LEFT,ALU1 +S 0,5000,3500,5000,400,vdd,RIGHT,CALU1 +S 0,0,3500,0,400,vss,RIGHT,CALU1 +S 0,4000,3500,4000,1200,*,RIGHT,NWELL +S 0,3100,3500,3100,1200,*,RIGHT,NWELL +S 0,5000,3500,5000,300,*,RIGHT,NTIE +S 0,0,3500,0,300,*,RIGHT,PTIE +S 2600,0,2600,600,200,*,UP,ALU1 +S 900,4400,900,5000,200,*,UP,ALU1 +S 300,0,300,600,200,*,UP,ALU1 +B 3050,2100,300,200,CONT_TURN8,* +B 2500,2100,200,200,CONT_TURN8,* +B 1550,2100,300,200,CONT_TURN8,* +B 1000,2100,200,200,CONT_TURN8,* +B 500,2100,200,200,CONT_TURN8,* +B 3200,1100,200,200,CONT_TURN1,* +B 2000,1100,200,200,CONT_TURN1,* +V 300,3900,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 2500,2100,CONT_POLY,* +V 3100,2100,CONT_POLY,* +V 2100,3300,CONT_DIF_P,* +V 2100,2700,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 500,2100,CONT_POLY,* +V 1000,2100,CONT_POLY,* +V 1500,2100,CONT_POLY,* +V 3200,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 3200,600,CONT_DIF_N,* +V 2000,600,CONT_DIF_N,* +V 1400,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 2600,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa2ao222_x1.vbe b/pdks/symbolic/lsxlib/cells/noa2ao222_x1.vbe new file mode 100644 index 000000000..034393fea --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2ao222_x1.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3210; + CONSTANT rdown_i1_nq : NATURAL := 3210; + CONSTANT rdown_i2_nq : NATURAL := 3210; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 5260; + CONSTANT rup_i1_nq : NATURAL := 5260; + CONSTANT rup_i2_nq : NATURAL := 5260; + CONSTANT rup_i3_nq : NATURAL := 5260; + CONSTANT rup_i4_nq : NATURAL := 3750; + CONSTANT tphl_i2_nq : NATURAL := 186; + CONSTANT tphl_i4_nq : NATURAL := 240; + CONSTANT tphl_i3_nq : NATURAL := 256; + CONSTANT tplh_i4_nq : NATURAL := 309; + CONSTANT tphl_i0_nq : NATURAL := 348; + CONSTANT tplh_i1_nq : NATURAL := 378; + CONSTANT tplh_i0_nq : NATURAL := 422; + CONSTANT tphl_i1_nq : NATURAL := 440; + CONSTANT tplh_i3_nq : NATURAL := 459; + CONSTANT tplh_i2_nq : NATURAL := 473; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x1; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1100 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa2ao222_x4.ap b/pdks/symbolic/lsxlib/cells/noa2ao222_x4.ap new file mode 100644 index 000000000..a04d45a5d --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2ao222_x4.ap @@ -0,0 +1,178 @@ +V ALLIANCE : 6 +H noa2ao222_x4,P, 1/ 8/2024,100 +A 0,0,6000,5000 +S 0,1100,6000,1100,1400,*,RIGHT,PWELL +S 3100,2100,3100,3900,200,i3,DOWN,CALU1 +S 2600,2100,2600,3900,200,i2,DOWN,CALU1 +S 1500,2100,1500,3400,200,i4,DOWN,CALU1 +S 1000,1100,1000,3400,200,i1,DOWN,CALU1 +S 500,1100,500,3400,200,i0,DOWN,CALU1 +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 900,3600,900,4500,300,*,DOWN,PDIF +S 1500,3900,1500,4400,200,*,UP,ALU1 +S 300,3900,300,4400,200,*,DOWN,ALU1 +S 300,3900,1500,3900,200,*,RIGHT,ALU1 +S 0,0,6000,0,400,vss,RIGHT,CALU1 +S 0,5000,6000,5000,400,vdd,RIGHT,CALU1 +S 4400,2700,4400,5000,200,*,UP,ALU1 +S 3800,2100,3800,4400,200,*,UP,ALU1 +S 3800,2100,4500,2100,200,*,LEFT,ALU1 +S 4500,1100,4500,2100,200,*,UP,ALU1 +S 4500,2100,5300,2100,200,*,RIGHT,POLY +S 2400,2100,2500,2100,200,*,LEFT,POLY +S 1000,2100,1100,2100,200,*,RIGHT,POLY +S 500,2100,600,2100,200,*,RIGHT,POLY +S 1700,3400,1800,3400,100,*,RIGHT,POLY +S 1100,3400,1200,3400,100,*,RIGHT,POLY +S 1700,1100,1700,3400,100,*,UP,POLY +S 1100,1100,1100,3400,100,*,UP,POLY +S 600,1100,600,3400,100,*,UP,POLY +S 300,3600,300,4500,300,*,UP,PDIF +S 600,3400,600,4700,100,*,UP,PTRANS +S 1200,3400,1200,4700,100,*,DOWN,PTRANS +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 2300,1100,2400,1100,100,*,RIGHT,POLY +S 2900,1100,2900,2400,100,*,UP,POLY +S 2400,1100,2400,2400,100,*,UP,POLY +S 3200,600,3200,1100,200,*,DOWN,ALU1 +S 2000,600,2000,1100,200,*,UP,ALU1 +S 2900,300,2900,1100,100,*,UP,NTRANS +S 600,300,600,1100,100,*,UP,NTRANS +S 2300,300,2300,1100,100,*,UP,NTRANS +S 1700,300,1700,1100,100,*,UP,NTRANS +S 1100,300,1100,1100,100,*,UP,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 2600,500,2600,900,300,*,UP,NDIF +S 2000,500,2000,900,200,*,UP,NDIF +S 1400,500,1400,900,200,*,UP,NDIF +S 3200,500,3200,900,300,*,UP,NDIF +S 2900,2100,3100,2100,200,*,LEFT,POLY +S 2500,2100,2600,2100,200,*,LEFT,ALU1 +S 1500,1600,4000,1600,200,*,LEFT,ALU1 +S 3800,1100,4500,1100,200,*,RIGHT,ALU1 +S 3800,600,3800,1100,200,*,UP,ALU1 +S 4400,0,4400,600,200,*,DOWN,ALU1 +S 5000,600,5000,4400,200,nq,DOWN,CALU1 +S 5600,2700,5600,5000,200,*,UP,ALU1 +S 4100,1100,4100,3400,100,*,DOWN,POLY +S 3800,3600,3800,4500,300,*,UP,PDIF +S 4100,3400,4100,4700,100,*,UP,PTRANS +S 3800,500,3800,900,300,*,UP,NDIF +S 4100,300,4100,1100,100,*,DOWN,NTRANS +S 5600,0,5600,1300,200,*,DOWN,ALU1 +S 5300,1600,5300,2400,100,*,UP,POLY +S 4700,1600,4700,2400,100,*,UP,POLY +S 5300,2400,5300,4700,100,*,UP,PTRANS +S 5000,2600,5000,4500,300,*,DOWN,PDIF +S 4700,2400,4700,4700,100,*,UP,PTRANS +S 4400,2600,4400,4500,300,*,DOWN,PDIF +S 5600,2600,5600,4500,300,*,DOWN,PDIF +S 4700,300,4700,1600,100,*,DOWN,NTRANS +S 5300,300,5300,1600,100,*,DOWN,NTRANS +S 5000,500,5000,1400,300,*,UP,NDIF +S 4400,500,4400,1400,300,*,UP,NDIF +S 5600,500,5600,1400,300,*,UP,NDIF +S 1500,600,1500,1600,200,*,DOWN,ALU1 +S 2000,1600,2000,3900,200,*,DOWN,ALU1 +S 2100,2600,2100,4500,300,*,UP,PDIF +S 2700,2600,2700,4500,200,*,UP,PDIF +S 2400,2400,2400,4700,100,*,UP,PTRANS +S 3200,2600,3200,4500,300,*,UP,PDIF +S 2900,2400,2900,4700,100,*,UP,PTRANS +S 1500,2100,1700,2100,200,*,RIGHT,POLY +S 300,0,300,600,200,*,UP,ALU1 +S 2600,0,2600,600,200,*,UP,ALU1 +S 1500,4400,3200,4400,200,*,RIGHT,ALU1 +S 2000,3300,2100,3300,200,*,LEFT,ALU1 +S 1400,600,1500,600,200,*,LEFT,ALU1 +S 2000,2700,2100,2700,200,*,LEFT,ALU1 +S 2000,3900,2100,3900,200,*,LEFT,ALU1 +S 900,4400,900,5000,200,*,UP,ALU1 +S 2000,1100,3200,1100,200,*,RIGHT,ALU1 +S 0,4000,6000,4000,1200,*,RIGHT,NWELL +S 0,3100,6000,3100,1200,*,RIGHT,NWELL +S 0,5000,6000,5000,300,*,RIGHT,NTIE +S 0,0,6000,0,300,*,RIGHT,PTIE +B 4850,2100,900,200,CONT_TURN8,* +B 3050,2100,300,200,CONT_TURN8,* +B 2500,2100,200,200,CONT_TURN8,* +B 1550,2100,300,200,CONT_TURN8,* +B 1000,2100,200,200,CONT_TURN8,* +B 500,2100,200,200,CONT_TURN8,* +B 2600,2100,200,200,CONT_TURN1,* +B 3800,2100,200,200,CONT_TURN1,* +B 1500,600,200,200,CONT_TURN1,* +B 4500,1100,200,200,CONT_TURN1,* +B 3800,1100,200,200,CONT_TURN1,* +B 3200,1100,200,200,CONT_TURN1,* +B 2000,1100,200,200,CONT_TURN1,* +B 1500,1600,200,200,CONT_TURN1,* +B 2000,3900,200,200,CONT_TURN1,* +V 300,3900,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 4400,3200,CONT_DIF_P,* +V 4400,2700,CONT_DIF_P,* +V 4500,2100,CONT_POLY,* +V 2500,2100,CONT_POLY,* +V 3100,2100,CONT_POLY,* +V 4000,1600,CONT_POLY,* +V 5600,3800,CONT_DIF_P,* +V 4400,3800,CONT_DIF_P,* +V 5000,3800,CONT_DIF_P,* +V 3800,3800,CONT_DIF_P,* +V 5600,4400,CONT_DIF_P,* +V 5600,2700,CONT_DIF_P,* +V 5600,3200,CONT_DIF_P,* +V 5000,3200,CONT_DIF_P,* +V 5000,2700,CONT_DIF_P,* +V 5000,4400,CONT_DIF_P,* +V 4400,4400,CONT_DIF_P,* +V 3800,4400,CONT_DIF_P,* +V 3800,600,CONT_DIF_N,* +V 5600,1300,CONT_DIF_N,* +V 5000,1300,CONT_DIF_N,* +V 5000,600,CONT_DIF_N,* +V 5600,600,CONT_DIF_N,* +V 4400,600,CONT_DIF_N,* +V 2100,3900,CONT_DIF_P,* +V 2100,2700,CONT_DIF_P,* +V 2100,3300,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 3200,4400,CONT_DIF_P,* +V 3200,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 2600,600,CONT_DIF_N,* +V 1400,600,CONT_DIF_N,* +V 2000,600,CONT_DIF_N,* +V 1500,2100,CONT_POLY,* +V 1000,2100,CONT_POLY,* +V 500,2100,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa2ao222_x4.vbe b/pdks/symbolic/lsxlib/cells/noa2ao222_x4.vbe new file mode 100644 index 000000000..89b9f12c5 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 638; + CONSTANT tplh_i4_nq : NATURAL := 664; + CONSTANT tphl_i0_nq : NATURAL := 684; + CONSTANT tphl_i4_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 732; + CONSTANT tplh_i1_nq : NATURAL := 758; + CONSTANT tphl_i1_nq : NATURAL := 780; + CONSTANT tplh_i3_nq : NATURAL := 795; + CONSTANT tplh_i0_nq : NATURAL := 801; + CONSTANT tplh_i2_nq : NATURAL := 809; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa3ao322_x1.ap b/pdks/symbolic/lsxlib/cells/noa3ao322_x1.ap new file mode 100644 index 000000000..17a3e2774 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa3ao322_x1.ap @@ -0,0 +1,133 @@ +V ALLIANCE : 6 +H noa3ao322_x1,P, 1/ 8/2024,100 +A 0,0,5000,5000 +S 0,1100,5000,1100,1400,*,RIGHT,PWELL +S 400,2100,700,2100,100,*,RIGHT,POLY +S 2300,2100,2300,3400,200,i6,DOWN,CALU1 +S 1700,600,1700,3400,200,i2,DOWN,CALU1 +S 1100,600,1100,3400,200,i1,DOWN,CALU1 +S 4600,0,4600,600,200,*,DOWN,ALU1 +S 4300,2100,4500,2100,200,*,RIGHT,POLY +S 3700,2100,3900,2100,200,*,RIGHT,POLY +S 3100,2100,3300,2100,200,*,RIGHT,POLY +S 3900,1600,3900,3900,200,i4,DOWN,CALU1 +S 4500,1100,4500,3900,200,i5,UP,CALU1 +S 3300,1600,3300,3900,200,i3,DOWN,CALU1 +S 2300,2100,2500,2100,200,*,RIGHT,POLY +S 1700,2100,1900,2100,200,*,RIGHT,POLY +S 1100,2100,1300,2100,200,*,RIGHT,POLY +S 4300,1000,4300,2400,100,*,DOWN,POLY +S 3700,1000,3700,2400,100,*,DOWN,POLY +S 3100,1000,3100,2400,100,*,DOWN,POLY +S 2500,1000,2500,3200,100,*,DOWN,POLY +S 1900,1500,1900,3200,100,*,DOWN,POLY +S 1300,1500,1300,3200,100,*,DOWN,POLY +S 700,1500,700,3200,100,*,DOWN,POLY +S 400,1100,400,3900,200,i0,DOWN,CALU1 +S 2200,600,2200,1600,200,nq,DOWN,CALU1 +S 2800,1600,2800,3900,200,nq,DOWN,CALU1 +S 2200,1600,2800,1600,200,*,RIGHT,ALU1 +S 1000,3900,1000,4400,200,*,UP,ALU1 +S 1000,3900,2200,3900,200,*,LEFT,ALU1 +S 2200,3900,2200,4400,200,*,DOWN,ALU1 +S 2200,4400,4600,4400,200,*,LEFT,ALU1 +S 2800,600,2800,1100,200,*,DOWN,ALU1 +S 2800,1100,4000,1100,200,*,LEFT,ALU1 +S 4000,600,4000,1100,200,*,UP,ALU1 +S 3400,0,3400,600,200,*,DOWN,ALU1 +S 400,0,400,600,200,*,DOWN,ALU1 +S 1600,4400,1600,5000,200,*,UP,ALU1 +S 400,4400,400,5000,200,*,UP,ALU1 +S 4600,500,4600,800,300,*,UP,NDIF +S 4000,500,4000,800,300,*,UP,NDIF +S 3400,500,3400,800,300,*,UP,NDIF +S 2800,500,2800,800,300,*,UP,NDIF +S 2200,500,2200,1300,300,*,UP,NDIF +S 1600,500,1600,1300,300,*,UP,NDIF +S 1000,500,1000,1300,300,*,UP,NDIF +S 400,500,400,1300,300,*,UP,NDIF +S 4600,2600,4600,4500,300,*,DOWN,PDIF +S 4000,2600,4000,4500,300,*,DOWN,PDIF +S 3400,2600,3400,4500,300,*,DOWN,PDIF +S 2800,2600,2800,4500,300,*,DOWN,PDIF +S 2200,3400,2200,4500,300,*,DOWN,PDIF +S 1600,3400,1600,4500,300,*,DOWN,PDIF +S 1000,3400,1000,4500,300,*,DOWN,PDIF +S 400,3400,400,4500,300,*,DOWN,PDIF +S 700,3200,700,4700,100,*,DOWN,PTRANS +S 1300,3200,1300,4700,100,*,DOWN,PTRANS +S 1900,3200,1900,4700,100,*,DOWN,PTRANS +S 2500,3200,2500,4700,100,*,DOWN,PTRANS +S 3100,2400,3100,4700,100,*,UP,PTRANS +S 3700,2400,3700,4700,100,*,UP,PTRANS +S 4300,2400,4300,4700,100,*,DOWN,PTRANS +S 3700,300,3700,1000,100,*,UP,NTRANS +S 3100,300,3100,1000,100,*,UP,NTRANS +S 2500,300,2500,1000,100,*,UP,NTRANS +S 1900,300,1900,1500,100,*,UP,NTRANS +S 1300,300,1300,1500,100,*,UP,NTRANS +S 700,300,700,1500,100,*,UP,NTRANS +S 4300,300,4300,1000,100,*,UP,NTRANS +S 0,0,5000,0,300,*,RIGHT,PTIE +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +B 4450,2100,300,200,CONT_TURN8,* +B 3850,2100,300,200,CONT_TURN8,* +B 3250,2100,300,200,CONT_TURN8,* +B 2350,2100,300,200,CONT_TURN8,* +B 1750,2100,300,200,CONT_TURN8,* +B 1150,2100,300,200,CONT_TURN8,* +B 500,2100,400,200,CONT_TURN8,* +B 2800,1100,200,200,CONT_TURN1,* +B 4000,1100,200,200,CONT_TURN1,* +B 2200,3900,200,200,CONT_TURN1,* +B 1000,3900,200,200,CONT_TURN1,* +V 5000,0,CONT_BODY_P,* +V 5000,5000,CONT_BODY_N,* +V 4500,2100,CONT_POLY,* +V 3900,2100,CONT_POLY,* +V 3300,2100,CONT_POLY,* +V 1100,2100,CONT_POLY,* +V 400,2100,CONT_POLY,* +V 1700,2100,CONT_POLY,* +V 2300,2100,CONT_POLY,* +V 2800,3300,CONT_DIF_P,* +V 2800,3900,CONT_DIF_P,* +V 2800,2700,CONT_DIF_P,* +V 2200,1200,CONT_DIF_N,* +V 4000,600,CONT_DIF_N,* +V 3400,600,CONT_DIF_N,* +V 1600,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 2200,4400,CONT_DIF_P,* +V 4600,4400,CONT_DIF_P,* +V 4600,600,CONT_DIF_N,* +V 4000,600,CONT_DIF_N,* +V 2800,600,CONT_DIF_N,* +V 2200,600,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa3ao322_x1.vbe b/pdks/symbolic/lsxlib/cells/noa3ao322_x1.vbe new file mode 100644 index 000000000..ff0227769 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa3ao322_x1.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3370; + CONSTANT rdown_i1_nq : NATURAL := 3370; + CONSTANT rdown_i2_nq : NATURAL := 3370; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rdown_i5_nq : NATURAL := 3210; + CONSTANT rdown_i6_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 6700; + CONSTANT rup_i1_nq : NATURAL := 6700; + CONSTANT rup_i2_nq : NATURAL := 6700; + CONSTANT rup_i3_nq : NATURAL := 6700; + CONSTANT rup_i4_nq : NATURAL := 6700; + CONSTANT rup_i5_nq : NATURAL := 6700; + CONSTANT rup_i6_nq : NATURAL := 3690; + CONSTANT tphl_i3_nq : NATURAL := 196; + CONSTANT tphl_i6_nq : NATURAL := 246; + CONSTANT tphl_i4_nq : NATURAL := 264; + CONSTANT tplh_i6_nq : NATURAL := 311; + CONSTANT tphl_i5_nq : NATURAL := 328; + CONSTANT tphl_i0_nq : NATURAL := 396; + CONSTANT tphl_i1_nq : NATURAL := 486; + CONSTANT tplh_i2_nq : NATURAL := 488; + CONSTANT tphl_i2_nq : NATURAL := 546; + CONSTANT tplh_i1_nq : NATURAL := 552; + CONSTANT tplh_i5_nq : NATURAL := 581; + CONSTANT tplh_i3_nq : NATURAL := 599; + CONSTANT tplh_i4_nq : NATURAL := 608; + CONSTANT tplh_i0_nq : NATURAL := 616; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x1; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/noa3ao322_x4.ap b/pdks/symbolic/lsxlib/cells/noa3ao322_x4.ap new file mode 100644 index 000000000..f45cdb7b6 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa3ao322_x4.ap @@ -0,0 +1,189 @@ +V ALLIANCE : 6 +H noa3ao322_x4,P, 1/ 8/2024,100 +A 0,0,6500,5000 +S 0,1100,6500,1100,1400,*,RIGHT,PWELL +S 2100,2600,2100,4500,300,*,DOWN,PDIF +S 5300,1000,5400,1000,100,*,RIGHT,POLY +S 4700,1000,4800,1000,100,*,RIGHT,POLY +S 4100,1000,4200,1000,100,*,RIGHT,POLY +S 900,4400,900,5000,200,*,UP,ALU1 +S 1500,600,1500,3400,200,nq,UP,CALU1 +S 600,2300,800,2300,200,*,LEFT,POLY +S 800,2300,900,2300,200,*,LEFT,ALU1 +S 900,2300,900,3900,200,*,DOWN,ALU1 +S 900,3900,2100,3900,200,*,LEFT,ALU1 +S 2100,3400,2100,3900,200,*,UP,ALU1 +S 2100,3400,4500,3400,200,*,LEFT,ALU1 +S 900,0,900,1200,200,*,DOWN,ALU1 +S 300,1700,1000,1700,200,*,RIGHT,ALU1 +S 300,600,300,4400,200,*,DOWN,ALU1 +S 1000,1700,1800,1700,200,*,RIGHT,POLY +S 2200,1100,2200,2900,200,i0,DOWN,CALU1 +S 3300,600,3300,2900,200,i2,DOWN,CALU1 +S 2800,600,2800,2900,200,i1,DOWN,CALU1 +S 4000,2100,4000,2900,200,i6,DOWN,CALU1 +S 3800,600,3800,1600,200,*,DOWN,ALU1 +S 3800,1600,4500,1600,200,*,LEFT,ALU1 +S 4500,1600,4500,3900,200,*,DOWN,ALU1 +S 600,1100,600,3400,100,*,DOWN,POLY +S 1200,1600,1200,2400,100,*,DOWN,POLY +S 1800,1600,1800,2400,100,*,DOWN,POLY +S 2200,2100,2400,2100,200,*,RIGHT,POLY +S 0,0,6500,0,400,vss,RIGHT,CALU1 +S 0,0,6500,0,300,*,RIGHT,PTIE +S 0,5000,6500,5000,300,*,RIGHT,NTIE +S 3900,4400,6200,4400,200,*,LEFT,ALU1 +S 5400,2100,5500,2100,200,*,LEFT,POLY +S 5500,1600,5500,3900,200,i4,DOWN,CALU1 +S 6200,2600,6200,4500,300,*,DOWN,PDIF +S 5900,2400,5900,4700,100,*,DOWN,PTRANS +S 5900,1000,5900,2400,100,*,DOWN,POLY +S 5900,2100,6100,2100,200,*,RIGHT,POLY +S 6100,1100,6100,3900,200,i5,UP,CALU1 +S 3500,1500,3500,2100,100,*,UP,POLY +S 3600,2100,3600,3200,100,*,DOWN,POLY +S 3300,2100,3400,2100,200,*,LEFT,ALU1 +S 5900,300,5900,1000,100,*,UP,NTRANS +S 3500,300,3500,1500,100,*,UP,NTRANS +S 4100,300,4100,1000,100,*,UP,NTRANS +S 4700,300,4700,1000,100,*,UP,NTRANS +S 5300,300,5300,1000,100,*,UP,NTRANS +S 3800,500,3800,1300,300,*,UP,NDIF +S 4400,500,4400,800,300,*,UP,NDIF +S 5000,500,5000,800,300,*,UP,NDIF +S 5600,500,5600,800,300,*,UP,NDIF +S 6200,500,6200,800,300,*,UP,NDIF +S 5000,0,5000,600,200,*,DOWN,ALU1 +S 6200,0,6200,600,200,*,DOWN,ALU1 +S 5600,600,5600,1100,200,*,UP,ALU1 +S 4400,1100,5600,1100,200,*,LEFT,ALU1 +S 4400,600,4400,1100,200,*,DOWN,ALU1 +S 0,4000,6500,4000,1200,*,RIGHT,NWELL +S 0,3100,6500,3100,1200,*,RIGHT,NWELL +S 0,5000,6500,5000,400,vdd,RIGHT,CALU1 +S 3300,4400,3300,5000,200,*,UP,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 1800,2400,1800,4700,100,*,DOWN,PTRANS +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 2400,3200,2400,4700,100,*,DOWN,PTRANS +S 3000,3200,3000,4700,100,*,DOWN,PTRANS +S 3600,3200,3600,4700,100,*,DOWN,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 300,3600,300,4500,300,*,DOWN,PDIF +S 600,3400,600,4700,100,*,DOWN,PTRANS +S 5100,2600,5100,4500,300,*,DOWN,PDIF +S 4500,2600,4500,4500,300,*,DOWN,PDIF +S 3900,3400,3900,4500,300,*,DOWN,PDIF +S 3300,3400,3300,4500,300,*,DOWN,PDIF +S 2700,3400,2700,4500,300,*,DOWN,PDIF +S 2100,3400,2100,4500,300,*,DOWN,PDIF +S 4200,3200,4200,4700,100,*,DOWN,PTRANS +S 4800,2400,4800,4700,100,*,UP,PTRANS +S 5400,2400,5400,4700,100,*,UP,PTRANS +S 3000,300,3000,1500,100,*,UP,NTRANS +S 2400,300,2400,1500,100,*,UP,NTRANS +S 600,300,600,1100,100,*,UP,NTRANS +S 1200,300,1200,1600,100,*,UP,NTRANS +S 1800,300,1800,1600,100,*,UP,NTRANS +S 1500,500,1500,1400,300,*,DOWN,NDIF +S 900,500,900,1400,300,*,DOWN,NDIF +S 300,500,300,900,300,*,DOWN,NDIF +S 2700,500,2700,1300,300,*,UP,NDIF +S 2100,500,2100,1300,300,*,UP,NDIF +S 5400,1000,5400,2400,100,*,DOWN,POLY +S 4800,2100,5000,2100,200,*,RIGHT,POLY +S 4800,1000,4800,2400,100,*,DOWN,POLY +S 4200,1000,4200,3200,100,*,DOWN,POLY +S 3000,1500,3000,3200,100,*,DOWN,POLY +S 2400,1500,2400,3200,100,*,DOWN,POLY +S 4000,2100,4200,2100,200,*,RIGHT,POLY +S 3400,2100,3600,2100,200,*,RIGHT,POLY +S 2800,2100,3000,2100,200,*,RIGHT,POLY +S 2100,0,2100,600,200,*,DOWN,ALU1 +S 2700,3900,2700,4400,200,*,UP,ALU1 +S 5000,1600,5000,3900,200,i3,DOWN,CALU1 +S 2700,3900,3900,3900,200,*,LEFT,ALU1 +S 3900,3900,3900,4400,200,*,DOWN,ALU1 +B 6050,2100,300,200,CONT_TURN8,* +B 5500,2100,200,200,CONT_TURN8,* +B 4950,2100,300,200,CONT_TURN8,* +B 4050,2100,300,200,CONT_TURN8,* +B 3450,2100,300,200,CONT_TURN8,* +B 2850,2100,300,200,CONT_TURN8,* +B 2250,2100,300,200,CONT_TURN8,* +B 1350,1700,900,200,CONT_TURN8,* +B 750,2300,300,200,CONT_TURN8,* +B 5600,1100,200,200,CONT_TURN1,* +B 4400,1100,200,200,CONT_TURN1,* +B 4500,1600,200,200,CONT_TURN1,* +B 3800,1600,200,200,CONT_TURN1,* +B 900,2300,200,200,CONT_TURN1,* +B 3900,3900,200,200,CONT_TURN1,* +B 2700,3900,200,200,CONT_TURN1,* +B 2100,3900,200,200,CONT_TURN1,* +B 900,3900,200,200,CONT_TURN1,* +V 1500,1200,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 1500,3400,CONT_DIF_P,* +V 1500,2700,CONT_DIF_P,* +V 800,2300,CONT_POLY,* +V 900,4400,CONT_DIF_P,* +V 900,1200,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 300,4400,CONT_DIF_P,* +V 300,3700,CONT_DIF_P,* +V 1000,1700,CONT_POLY,* +V 2200,2100,CONT_POLY,* +V 5500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 6500,5000,CONT_BODY_N,* +V 5500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 6500,0,CONT_BODY_P,* +V 5500,2100,CONT_POLY,* +V 6200,4400,CONT_DIF_P,* +V 6100,2100,CONT_POLY,* +V 3800,600,CONT_DIF_N,* +V 4400,600,CONT_DIF_N,* +V 5600,600,CONT_DIF_N,* +V 6200,600,CONT_DIF_N,* +V 5600,600,CONT_DIF_N,* +V 3800,1200,CONT_DIF_N,* +V 5000,600,CONT_DIF_N,* +V 3900,4400,CONT_DIF_P,* +V 4500,3300,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 4500,3900,CONT_DIF_P,* +V 4500,2700,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 2100,600,CONT_DIF_N,* +V 3400,2100,CONT_POLY,* +V 4000,2100,CONT_POLY,* +V 5000,2100,CONT_POLY,* +V 2800,2100,CONT_POLY,* +V 5000,0,CONT_BODY_P,* +V 5000,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/noa3ao322_x4.vbe b/pdks/symbolic/lsxlib/cells/noa3ao322_x4.vbe new file mode 100644 index 000000000..1fc4b8a6f --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/noa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT tplh_i6_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 729; + CONSTANT tphl_i6_nq : NATURAL := 738; + CONSTANT tphl_i0_nq : NATURAL := 819; + CONSTANT tphl_i4_nq : NATURAL := 821; + CONSTANT tplh_i2_nq : NATURAL := 874; + CONSTANT tplh_i5_nq : NATURAL := 900; + CONSTANT tphl_i5_nq : NATURAL := 907; + CONSTANT tphl_i1_nq : NATURAL := 914; + CONSTANT tplh_i4_nq : NATURAL := 924; + CONSTANT tplh_i3_nq : NATURAL := 926; + CONSTANT tplh_i1_nq : NATURAL := 931; + CONSTANT tplh_i0_nq : NATURAL := 987; + CONSTANT tphl_i2_nq : NATURAL := 990; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1600 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/nts_x1.ap b/pdks/symbolic/lsxlib/cells/nts_x1.ap new file mode 100644 index 000000000..2bb142ec8 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nts_x1.ap @@ -0,0 +1,68 @@ +V ALLIANCE : 6 +H nts_x1,P, 5/ 8/2024,100 +A 0,0,2500,5000 +S 600,3300,800,3300,200,*,LEFT,POLY2 +S 600,1600,800,1600,200,*,LEFT,POLY2 +S 600,1100,600,1600,100,*,UP,POLY +S 0,1100,2500,1100,1400,*,RIGHT,PWELL +S 1000,500,1000,900,300,*,UP,NDIF +S 0,0,2500,0,400,vss,RIGHT,CALU1 +S 0,0,2500,0,300,*,RIGHT,PTIE +S 1000,0,1000,600,200,*,DOWN,ALU1 +S 1700,2000,1900,2000,200,*,RIGHT,POLY +S 300,2400,1400,2400,100,*,RIGHT,POLY +S 0,4000,2500,4000,1200,*,RIGHT,NWELL +S 0,3100,2500,3100,1200,*,RIGHT,NWELL +S 0,5000,2500,5000,300,*,RIGHT,NTIE +S 0,5000,2500,5000,400,vdd,RIGHT,CALU1 +S 800,1100,800,3500,200,cmd,UP,CALU1 +S 1000,4000,1000,5000,200,*,UP,ALU1 +S 1700,600,1700,4400,200,i,DOWN,CALU1 +S 2200,600,2200,4400,200,nq,DOWN,CALU1 +S 1000,3600,1000,4500,300,*,DOWN,PDIF +S 1200,2600,1200,4500,300,*,DOWN,PDIF +S 1200,500,1200,1400,300,*,DOWN,NDIF +S 800,1600,1400,1600,100,*,RIGHT,POLY +S 1900,2400,1900,4700,100,*,UP,PTRANS +S 2200,2600,2200,4500,300,*,DOWN,PDIF +S 1900,300,1900,1600,100,*,UP,NTRANS +S 1400,300,1400,1600,100,*,UP,NTRANS +S 2200,500,2200,1400,300,*,UP,NDIF +S 1400,2400,1400,4700,100,*,UP,PTRANS +S 1900,1600,1900,2400,100,*,DOWN,POLY +S 900,500,900,900,300,*,UP,NDIF +S 600,300,600,1100,100,*,UP,NTRANS +S 300,600,300,4400,200,*,DOWN,ALU1 +S 300,3600,300,4500,300,*,DOWN,PDIF +S 600,3400,600,4700,100,*,DOWN,PTRANS +S 300,500,300,900,300,*,UP,NDIF +B 1750,2000,300,200,CONT_TURN8,* +V 1700,2000,CONT_POLY,* +V 300,2400,CONT_POLY,* +V 800,3300,CONT_POLY,* +V 1000,4000,CONT_DIF_P,* +V 2200,3300,CONT_DIF_P,* +V 2200,2700,CONT_DIF_P,* +V 2200,3900,CONT_DIF_P,* +V 2200,4400,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 2200,1300,CONT_DIF_N,* +V 2200,600,CONT_DIF_N,* +V 1000,600,CONT_DIF_N,* +V 800,1600,CONT_POLY,* +V 300,600,CONT_DIF_N,* +V 300,3700,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nts_x1.vbe b/pdks/symbolic/lsxlib/cells/nts_x1.vbe new file mode 100644 index 000000000..f6cada4ad --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nts_x1.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_cmd : NATURAL := 14; + CONSTANT cin_i : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i_nq : NATURAL := 3210; + CONSTANT tphl_cmd_nq : NATURAL := 41; + CONSTANT tphl_i_nq : NATURAL := 169; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 249; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x1; + +ARCHITECTURE behaviour_data_flow OF nts_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x1" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 800 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/lsxlib/cells/nts_x2.ap b/pdks/symbolic/lsxlib/cells/nts_x2.ap new file mode 100644 index 000000000..5ed99c4e3 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nts_x2.ap @@ -0,0 +1,104 @@ +V ALLIANCE : 6 +H nts_x2,P, 5/ 8/2024,100 +A 0,0,3500,5000 +S 1600,1500,1600,1600,200,*,DOWN,POLY2 +S 1600,2400,1600,2500,200,*,UP,POLY2 +S 0,1100,3500,1100,1400,*,RIGHT,PWELL +S 1500,2400,1500,3900,200,*,UP,ALU1 +S 3100,2900,3100,5000,200,*,UP,ALU1 +S 2000,2900,2100,2900,200,*,RIGHT,ALU1 +S 800,1600,1600,1600,200,*,LEFT,ALU1 +S 900,2700,900,4500,300,*,UP,PDIF +S 900,4400,900,5000,200,*,UP,ALU1 +S 900,0,900,600,200,*,DOWN,ALU1 +S 3100,2700,3100,4500,300,*,UP,PDIF +S 3100,0,3100,1100,200,*,UP,ALU1 +S 0,0,3500,0,300,*,RIGHT,PTIE +S 0,0,3500,0,400,vss,RIGHT,CALU1 +S 0,4000,3500,4000,1200,*,RIGHT,NWELL +S 0,3100,3500,3100,1200,*,RIGHT,NWELL +S 0,5000,3500,5000,300,*,RIGHT,NTIE +S 0,5000,3500,5000,400,vdd,RIGHT,CALU1 +S 300,3600,300,4500,300,*,DOWN,PDIF +S 600,3400,600,4700,100,*,DOWN,PTRANS +S 1200,2500,1200,4700,100,*,UP,PTRANS +S 2000,2700,2000,4500,300,*,DOWN,PDIF +S 1700,2500,1700,4700,100,*,UP,PTRANS +S 2300,2500,2300,4700,100,*,UP,PTRANS +S 2800,2500,2800,4700,100,*,UP,PTRANS +S 1200,300,1200,1500,100,*,UP,NTRANS +S 1700,300,1700,1500,100,*,UP,NTRANS +S 600,300,600,1100,100,*,UP,NTRANS +S 2800,300,2800,1500,100,*,DOWN,NTRANS +S 2300,300,2300,1500,100,*,DOWN,NTRANS +S 3100,500,3100,1300,300,*,DOWN,NDIF +S 900,500,900,1300,300,*,DOWN,NDIF +S 300,500,300,900,300,*,UP,NDIF +S 2000,500,2000,1300,300,*,UP,NDIF +S 600,1100,600,3400,100,*,DOWN,POLY +S 600,1600,800,1600,200,*,LEFT,POLY +S 1200,1500,1200,2500,100,*,DOWN,POLY +S 1200,2000,2600,2000,100,*,LEFT,POLY +S 2600,2000,2800,2000,200,*,RIGHT,POLY +S 1600,1500,2300,1500,100,*,RIGHT,POLY +S 1600,1500,1600,1600,200,*,DOWN,POLY +S 1600,2400,1600,2500,200,*,DOWN,POLY +S 2800,1500,2800,2500,100,*,UP,POLY +S 1600,2500,2300,2500,100,*,RIGHT,POLY +S 300,3900,1500,3900,200,*,LEFT,ALU1 +S 800,1100,800,3400,200,cmd,UP,CALU1 +S 2000,1100,2100,1100,200,*,RIGHT,ALU1 +S 2000,600,2100,600,200,*,RIGHT,ALU1 +S 1500,2400,1600,2400,200,*,LEFT,ALU1 +S 2000,4400,2100,4400,200,*,RIGHT,ALU1 +S 2000,3900,2100,3900,200,*,RIGHT,ALU1 +S 2000,3400,2100,3400,200,*,RIGHT,ALU1 +S 300,600,300,4400,200,*,DOWN,ALU1 +S 2100,600,2100,4400,200,nq,DOWN,CALU1 +S 2600,600,2600,4400,200,i,DOWN,CALU1 +B 1600,2400,200,200,CONT_TURN8,* +B 1600,1600,200,200,CONT_TURN8,* +B 750,1600,300,200,CONT_TURN8,* +B 2650,2000,300,200,CONT_TURN8,* +B 1500,2400,200,200,CONT_TURN1,* +B 1500,3900,200,200,CONT_TURN1,* +V 3100,2900,CONT_DIF_P,* +V 2000,2900,CONT_DIF_P,* +V 3100,4400,CONT_DIF_P,* +V 3100,3900,CONT_DIF_P,* +V 3100,3400,CONT_DIF_P,* +V 3000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 900,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 2000,3400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 300,3700,CONT_DIF_P,* +V 2000,3900,CONT_DIF_P,* +V 2000,4400,CONT_DIF_P,* +V 3100,600,CONT_DIF_N,* +V 3100,1100,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 2000,1100,CONT_DIF_N,* +V 2000,600,CONT_DIF_N,* +V 800,1600,CONT_POLY,* +V 2600,2000,CONT_POLY,* +V 1600,1600,CONT_POLY,* +V 1600,2400,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nts_x2.vbe b/pdks/symbolic/lsxlib/cells/nts_x2.vbe new file mode 100644 index 000000000..4bb47086f --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nts_x2.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_cmd : NATURAL := 18; + CONSTANT cin_i : NATURAL := 28; + CONSTANT rdown_cmd_nq : NATURAL := 1430; + CONSTANT rdown_i_nq : NATURAL := 1430; + CONSTANT rup_cmd_nq : NATURAL := 1600; + CONSTANT rup_i_nq : NATURAL := 1600; + CONSTANT tphl_cmd_nq : NATURAL := 33; + CONSTANT tphl_i_nq : NATURAL := 167; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 330; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x2; + +ARCHITECTURE behaviour_data_flow OF nts_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x2" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 900 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/lsxlib/cells/nxr2_x1.ap b/pdks/symbolic/lsxlib/cells/nxr2_x1.ap new file mode 100644 index 000000000..70b1f4686 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nxr2_x1.ap @@ -0,0 +1,127 @@ +V ALLIANCE : 6 +H nxr2_x1,P, 5/ 8/2024,100 +A 0,0,4500,5000 +S 3000,1900,3000,2000,200,*,UP,POLY2 +S 3500,2400,3500,2500,200,*,UP,POLY2 +S 3500,2500,3700,2500,100,*,LEFT,POLY +S 1900,1600,2100,1600,200,*,LEFT,POLY2 +S 1900,2400,2100,2400,200,*,LEFT,POLY2 +S 0,1100,4500,1100,1400,*,RIGHT,PWELL +S 2500,1500,2500,2500,100,*,DOWN,POLY +S 3100,2000,3100,2500,100,*,DOWN,POLY +S 3700,2500,3700,3400,100,*,DOWN,POLY +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 400,2000,2500,2000,100,*,RIGHT,POLY +S 4000,600,4000,4400,200,*,DOWN,ALU1 +S 400,600,400,4400,200,*,DOWN,ALU1 +S 2100,2400,3500,2400,200,*,RIGHT,ALU1 +S 2100,1600,2100,1900,200,*,DOWN,ALU1 +S 2100,1900,3000,1900,200,*,LEFT,ALU1 +S 3000,1900,3000,2000,200,*,UP,POLY +S 3700,1100,3700,1500,100,*,UP,POLY +S 3500,1100,3500,3900,200,i1,DOWN,CALU1 +S 900,1100,900,3900,200,i0,DOWN,CALU1 +S 2800,2900,2800,4400,200,*,UP,ALU1 +S 2200,2900,2200,3900,200,nq,DOWN,CALU1 +S 1600,2900,2200,2900,200,*,LEFT,ALU1 +S 1600,4000,1600,4400,200,*,UP,ALU1 +S 4000,3600,4000,4500,300,*,DOWN,PDIF +S 4000,500,4000,900,300,*,UP,NDIF +S 1600,4400,2800,4400,200,*,RIGHT,ALU1 +S 1600,600,1600,3500,200,nq,DOWN,CALU1 +S 3400,2700,3400,4500,300,*,DOWN,PDIF +S 2800,2700,2800,4500,300,*,DOWN,PDIF +S 3100,2500,3100,4700,100,*,UP,PTRANS +S 1600,2700,1600,4500,300,*,DOWN,PDIF +S 2200,2700,2200,4500,300,*,DOWN,PDIF +S 2500,2500,2500,4700,100,*,UP,PTRANS +S 1900,2500,1900,4700,100,*,UP,PTRANS +S 3100,1500,3700,1500,100,*,RIGHT,POLY +S 1600,1100,2200,1100,200,*,LEFT,ALU1 +S 2200,600,2200,1100,200,*,DOWN,ALU1 +S 3400,500,3400,1300,300,*,UP,NDIF +S 3100,300,3100,1500,100,*,DOWN,NTRANS +S 2800,500,2800,1300,300,*,UP,NDIF +S 2500,300,2500,1500,100,*,DOWN,NTRANS +S 2200,500,2200,1300,300,*,UP,NDIF +S 1000,2700,1000,4500,300,*,UP,PDIF +S 1000,500,1000,1300,300,*,DOWN,NDIF +S 700,2500,700,3400,100,*,UP,POLY +S 700,2500,1300,2500,100,*,LEFT,POLY +S 700,1100,700,1500,100,*,DOWN,POLY +S 700,1500,1300,1500,100,*,LEFT,POLY +S 1300,2500,1300,4700,100,*,UP,PTRANS +S 1600,500,1600,1300,300,*,UP,NDIF +S 1900,300,1900,1500,100,*,DOWN,NTRANS +S 1300,300,1300,1500,100,*,DOWN,NTRANS +S 3700,3400,3700,4700,100,*,UP,PTRANS +S 700,3400,700,4700,100,*,UP,PTRANS +S 400,3600,400,4500,300,*,UP,PDIF +S 700,300,700,1100,100,*,DOWN,NTRANS +S 3700,300,3700,1100,100,*,DOWN,NTRANS +S 400,500,400,900,300,*,UP,NDIF +S 3400,0,3400,600,200,*,UP,ALU1 +S 1000,0,1000,600,200,*,UP,ALU1 +S 3400,4400,3400,5000,200,*,UP,ALU1 +S 1000,4400,1000,5000,200,*,UP,ALU1 +S 0,4000,4500,4000,1200,*,RIGHT,NWELL +S 0,3100,4500,3100,1200,*,RIGHT,NWELL +S 0,5000,4500,5000,400,vdd,RIGHT,CALU1 +S 0,0,4500,0,400,vss,RIGHT,CALU1 +S 0,5000,4500,5000,300,*,RIGHT,NTIE +S 0,0,4500,0,300,*,RIGHT,PTIE +B 900,1600,200,200,CONT_TURN8,* +B 900,2400,200,200,CONT_TURN8,* +B 3000,1900,200,200,CONT_TURN8,* +B 2100,1900,200,200,CONT_TURN1,* +V 4000,2000,CONT_POLY,* +V 400,2000,CONT_POLY,* +V 3000,1900,CONT_POLY,* +V 3500,2400,CONT_POLY,* +V 3500,1600,CONT_POLY,* +V 900,2400,CONT_POLY,* +V 900,1600,CONT_POLY,* +V 2200,3400,CONT_DIF_P,* +V 2200,2900,CONT_DIF_P,* +V 2800,3400,CONT_DIF_P,* +V 2800,2900,CONT_DIF_P,* +V 2200,3900,CONT_DIF_P,* +V 2800,3900,CONT_DIF_P,* +V 1600,4000,CONT_DIF_P,* +V 4000,3800,CONT_DIF_P,* +V 4000,4400,CONT_DIF_P,* +V 4000,600,CONT_DIF_N,* +V 1600,4400,CONT_DIF_P,* +V 2800,4400,CONT_DIF_P,* +V 2100,2400,CONT_POLY,* +V 2200,1100,CONT_DIF_N,* +V 2200,600,CONT_DIF_N,* +V 2100,1600,CONT_POLY,* +V 400,4400,CONT_DIF_P,* +V 3400,4400,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 400,3800,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 1000,600,CONT_DIF_N,* +V 3400,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nxr2_x1.vbe b/pdks/symbolic/lsxlib/cells/nxr2_x1.vbe new file mode 100644 index 000000000..1c89dd228 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nxr2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY nxr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i1_nq : NATURAL := 156; + CONSTANT tphl_i0_nq : NATURAL := 288; + CONSTANT tplh_i0_nq : NATURAL := 293; + CONSTANT tplh_i1_nq : NATURAL := 327; + CONSTANT tphh_i0_nq : NATURAL := 366; + CONSTANT tpll_i0_nq : NATURAL := 389; + CONSTANT tphh_i1_nq : NATURAL := 395; + CONSTANT tpll_i1_nq : NATURAL := 503; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x1; + +ARCHITECTURE behaviour_data_flow OF nxr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x1" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1100 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/nxr2_x4.ap b/pdks/symbolic/lsxlib/cells/nxr2_x4.ap new file mode 100644 index 000000000..d2cc1ac0f --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nxr2_x4.ap @@ -0,0 +1,172 @@ +V ALLIANCE : 6 +H nxr2_x4,P, 5/ 8/2024,100 +A 0,0,6000,5000 +S 2900,2100,3000,2100,200,*,RIGHT,POLY2 +S 3400,1500,3400,1600,200,*,DOWN,POLY2 +S 1800,1600,2000,1600,200,*,LEFT,POLY2 +S 1800,2400,2000,2400,200,*,LEFT,POLY2 +S 0,1100,6000,1100,1400,*,RIGHT,PWELL +S 2400,1500,2400,2500,100,*,DOWN,POLY +S 3400,1500,3600,1500,100,*,LEFT,POLY +S 5100,600,5100,4400,200,nq,UP,CALU1 +S 1500,3400,1500,4400,200,*,UP,ALU1 +S 1500,1100,1500,2900,200,*,DOWN,ALU1 +S 2100,2900,2100,3900,200,*,DOWN,ALU1 +S 5700,0,5700,1100,200,*,DOWN,ALU1 +S 4500,0,4500,600,200,*,DOWN,ALU1 +S 5700,2700,5700,5000,200,*,UP,ALU1 +S 4500,2700,4500,5000,200,*,UP,ALU1 +S 4400,1100,4400,2000,200,*,UP,ALU1 +S 1500,1100,4400,1100,200,*,RIGHT,ALU1 +S 5400,1600,5400,2400,100,*,DOWN,POLY +S 4800,1600,4800,2400,100,*,DOWN,POLY +S 4500,2600,4500,4500,300,*,DOWN,PDIF +S 4500,500,4500,1400,300,*,DOWN,NDIF +S 3900,900,3900,1700,300,*,UP,NDIF +S 0,0,6000,0,300,*,RIGHT,PTIE +S 0,0,6000,0,400,vss,RIGHT,CALU1 +S 0,4000,6000,4000,1200,*,RIGHT,NWELL +S 0,3100,6000,3100,1200,*,RIGHT,NWELL +S 0,5000,6000,5000,300,*,RIGHT,NTIE +S 0,5000,6000,5000,400,vdd,RIGHT,CALU1 +S 4800,2400,4800,4700,100,*,UP,PTRANS +S 5100,2600,5100,4500,300,*,DOWN,PDIF +S 5700,2600,5700,4500,300,*,DOWN,PDIF +S 5400,2400,5400,4700,100,*,UP,PTRANS +S 5400,300,5400,1600,100,*,DOWN,NTRANS +S 4800,300,4800,1600,100,*,DOWN,NTRANS +S 5100,500,5100,1400,300,*,UP,NDIF +S 5700,500,5700,1400,300,*,UP,NDIF +S 900,2700,900,4500,300,*,UP,PDIF +S 1200,2500,1200,4700,100,*,UP,PTRANS +S 3600,3400,3600,4700,100,*,UP,PTRANS +S 600,3400,600,4700,100,*,UP,PTRANS +S 300,3600,300,4500,300,*,UP,PDIF +S 3900,3600,3900,4500,300,*,DOWN,PDIF +S 3300,2700,3300,4500,300,*,DOWN,PDIF +S 2700,2700,2700,4500,300,*,DOWN,PDIF +S 3000,2500,3000,4700,100,*,UP,PTRANS +S 1500,2700,1500,4500,300,*,DOWN,PDIF +S 2100,2700,2100,4500,300,*,DOWN,PDIF +S 2400,2500,2400,4700,100,*,UP,PTRANS +S 1800,2500,1800,4700,100,*,UP,PTRANS +S 3000,300,3000,1500,100,*,DOWN,NTRANS +S 2400,300,2400,1500,100,*,DOWN,NTRANS +S 1800,300,1800,1500,100,*,DOWN,NTRANS +S 1200,300,1200,1500,100,*,DOWN,NTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 3600,700,3600,1500,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 900,500,900,1300,300,*,DOWN,NDIF +S 1500,500,1500,1300,300,*,UP,NDIF +S 3300,500,3300,1300,300,*,UP,NDIF +S 2700,500,2700,1300,300,*,UP,NDIF +S 2100,500,2100,1300,300,*,UP,NDIF +S 3000,1500,3000,2100,100,*,UP,POLY +S 3000,2500,3600,2500,100,*,LEFT,POLY +S 3600,2500,3600,3400,100,*,DOWN,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 3000,2000,3900,2000,100,*,RIGHT,POLY +S 600,2500,600,3400,100,*,UP,POLY +S 600,2500,1200,2500,100,*,LEFT,POLY +S 600,1100,600,1500,100,*,DOWN,POLY +S 600,1500,1200,1500,100,*,LEFT,POLY +S 3300,0,3300,600,200,*,UP,ALU1 +S 900,0,900,600,200,*,UP,ALU1 +S 3400,1600,3400,3900,200,i1,DOWN,CALU1 +S 2000,1600,3400,1600,200,*,RIGHT,ALU1 +S 2000,2100,2000,2400,200,*,UP,ALU1 +S 2000,2100,2900,2100,200,*,LEFT,ALU1 +S 300,600,300,4400,200,*,DOWN,ALU1 +S 3900,1600,3900,4400,200,*,DOWN,ALU1 +S 900,4400,900,5000,200,*,UP,ALU1 +S 1500,4400,2700,4400,200,*,RIGHT,ALU1 +S 2100,600,2100,1100,200,*,DOWN,ALU1 +S 3300,4400,3300,5000,200,*,UP,ALU1 +S 800,1100,800,3900,200,i0,DOWN,CALU1 +S 2700,2900,2700,4400,200,*,UP,ALU1 +S 1500,2900,2100,2900,200,*,LEFT,ALU1 +B 800,1600,200,200,CONT_TURN8,* +B 800,2400,200,200,CONT_TURN8,* +B 2900,2100,200,200,CONT_TURN8,* +B 4850,2000,1100,200,CONT_TURN8,* +B 2000,2100,200,200,CONT_TURN1,* +B 4400,1100,200,200,CONT_TURN1,* +B 1500,1100,200,200,CONT_TURN1,* +B 1500,2900,200,200,CONT_TURN1,* +V 1500,3400,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 4500,0,CONT_BODY_P,* +V 4500,5000,CONT_BODY_N,* +V 5100,2700,CONT_DIF_P,* +V 5100,3300,CONT_DIF_P,* +V 5100,3900,CONT_DIF_P,* +V 5100,4400,CONT_DIF_P,* +V 5700,4400,CONT_DIF_P,* +V 5700,3900,CONT_DIF_P,* +V 5700,3300,CONT_DIF_P,* +V 5700,2700,CONT_DIF_P,* +V 4500,2700,CONT_DIF_P,* +V 4500,3300,CONT_DIF_P,* +V 4500,3900,CONT_DIF_P,* +V 4500,4400,CONT_DIF_P,* +V 5100,1100,CONT_DIF_N,* +V 5100,600,CONT_DIF_N,* +V 5700,1100,CONT_DIF_N,* +V 5700,600,CONT_DIF_N,* +V 4500,600,CONT_DIF_N,* +V 4400,2000,CONT_POLY,* +V 5000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 1500,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,3800,CONT_DIF_P,* +V 2100,2900,CONT_DIF_P,* +V 2700,3400,CONT_DIF_P,* +V 2700,2900,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 3900,3800,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 2100,3400,CONT_DIF_P,* +V 3300,600,CONT_DIF_N,* +V 3900,1600,CONT_DIF_N,* +V 2100,1100,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 2000,1600,CONT_POLY,* +V 3400,1600,CONT_POLY,* +V 3400,2400,CONT_POLY,* +V 3900,2000,CONT_POLY,* +V 2900,2100,CONT_POLY,* +V 2000,2400,CONT_POLY,* +V 800,2400,CONT_POLY,* +V 800,1600,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/nxr2_x4.vbe b/pdks/symbolic/lsxlib/cells/nxr2_x4.vbe new file mode 100644 index 000000000..aa5ea7108 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/nxr2_x4.vbe @@ -0,0 +1,36 @@ +ENTITY nxr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tpll_i1_nq : NATURAL := 453; + CONSTANT tphh_i0_nq : NATURAL := 469; + CONSTANT tpll_i0_nq : NATURAL := 481; + CONSTANT tphl_i0_nq : NATURAL := 522; + CONSTANT tplh_i1_nq : NATURAL := 542; + CONSTANT tphl_i1_nq : NATURAL := 553; + CONSTANT tplh_i0_nq : NATURAL := 553; + CONSTANT tphh_i1_nq : NATURAL := 568; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x4; + +ARCHITECTURE behaviour_data_flow OF nxr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x4" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/o2_x2.ap b/pdks/symbolic/lsxlib/cells/o2_x2.ap new file mode 100644 index 000000000..59d1fdc62 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o2_x2.ap @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H o2_x2,P, 1/ 8/2024,100 +A 0,0,2500,5000 +S 0,1100,2500,1100,1400,*,RIGHT,PWELL +S 0,0,2500,0,300,*,RIGHT,PTIE +S 0,5000,2500,5000,300,*,RIGHT,NTIE +S 900,2600,900,4500,300,*,DOWN,PDIF +S 600,1100,600,2400,100,*,DOWN,POLY +S 1200,1100,1200,2400,100,*,DOWN,POLY +S 1800,1600,1800,2400,100,*,DOWN,POLY +S 0,0,2500,0,400,vss,RIGHT,CALU1 +S 0,4000,2500,4000,1200,*,RIGHT,NWELL +S 0,3100,2500,3100,1200,*,RIGHT,NWELL +S 0,5000,2500,5000,400,vdd,RIGHT,CALU1 +S 300,2600,300,4500,300,*,DOWN,PDIF +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 600,2400,600,4700,100,*,UP,PTRANS +S 2100,2600,2100,4500,300,*,UP,PDIF +S 1500,2600,1500,4500,300,*,UP,PDIF +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,UP,NTRANS +S 2100,500,2100,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +S 300,500,300,900,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 600,2200,700,2200,200,*,LEFT,POLY +S 1600,1700,1800,1700,200,*,RIGHT,POLY +S 1500,0,1500,600,200,*,DOWN,ALU1 +S 300,0,300,600,200,*,UP,ALU1 +S 800,1600,800,4400,200,i1,DOWN,CALU1 +S 1300,2200,1300,3900,200,i0,DOWN,CALU1 +S 300,1100,1600,1100,200,*,LEFT,ALU1 +S 300,1100,300,4400,200,*,DOWN,ALU1 +S 1500,4400,1500,5000,200,*,UP,ALU1 +S 2100,600,2100,4400,200,q,DOWN,CALU1 +S 1600,1100,1600,1700,200,*,DOWN,ALU1 +S 900,600,900,1100,200,*,DOWN,ALU1 +B 750,2200,300,200,CONT_TURN8,* +B 1300,2200,200,200,CONT_TURN8,* +B 1650,1700,300,200,CONT_TURN8,* +B 1600,1100,200,200,CONT_TURN1,* +B 300,1100,200,200,CONT_TURN1,* +V 300,4400,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 300,2700,CONT_DIF_P,* +V 300,3300,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 2100,3300,CONT_DIF_P,* +V 2100,2700,CONT_DIF_P,* +V 1500,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 2100,1200,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 1600,1700,CONT_POLY,* +V 800,2200,CONT_POLY,* +V 1300,2200,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/o2_x2.vbe b/pdks/symbolic/lsxlib/cells/o2_x2.vbe new file mode 100644 index 000000000..9e115a06f --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tpll_i0_q : NATURAL := 310; + CONSTANT tphh_i1_q : NATURAL := 335; + CONSTANT tpll_i1_q : NATURAL := 364; + CONSTANT tphh_i0_q : NATURAL := 406; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x2; + +ARCHITECTURE behaviour_data_flow OF o2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x2" + SEVERITY WARNING; + q <= (i0 or i1) after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/o2_x4.ap b/pdks/symbolic/lsxlib/cells/o2_x4.ap new file mode 100644 index 000000000..f607cf012 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o2_x4.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 6 +H o2_x4,P, 5/ 8/2024,100 +A 0,0,3000,5000 +S 1400,1600,1400,1700,200,*,DOWN,POLY2 +S 1200,1600,1400,1600,100,*,RIGHT,POLY +S 900,2000,900,2100,200,*,UP,POLY2 +S 1200,2500,1400,2500,200,*,LEFT,POLY2 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 900,3000,900,4500,300,*,DOWN,PDIF +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 0,5000,3000,5000,300,*,RIGHT,NTIE +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +S 0,0,3000,0,300,*,RIGHT,PTIE +S 0,0,3000,0,400,vss,RIGHT,CALU1 +S 2400,1600,2400,2400,100,*,DOWN,POLY +S 900,2100,2400,2100,100,*,RIGHT,POLY +S 2700,2700,2700,5000,200,*,UP,ALU1 +S 2700,0,2700,1200,200,*,DOWN,ALU1 +S 2700,500,2700,1400,300,*,DOWN,NDIF +S 2700,2600,2700,4500,300,*,DOWN,PDIF +S 2100,2600,2100,4500,300,*,UP,PDIF +S 1800,1600,1800,2600,100,*,DOWN,POLY +S 2400,300,2400,1600,100,*,UP,NTRANS +S 2400,2400,2400,4700,100,*,DOWN,PTRANS +S 1800,2600,1800,4700,100,*,UP,PTRANS +S 1500,2800,1500,4500,300,*,UP,PDIF +S 2100,2800,2100,4500,300,*,UP,PDIF +S 600,300,600,1100,100,*,DOWN,NTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 1200,1100,1200,1600,100,*,DOWN,POLY +S 400,1100,400,2800,100,*,DOWN,POLY +S 400,1100,600,1100,100,*,RIGHT,POLY +S 400,1100,400,3900,200,i1,DOWN,CALU1 +S 2100,600,2100,4400,200,q,DOWN,CALU1 +S 1400,1100,1400,3900,200,i0,DOWN,CALU1 +S 1200,2500,1200,2800,100,*,UP,POLY +S 400,2800,600,2800,100,*,LEFT,POLY +S 900,2100,1800,2100,100,*,RIGHT,POLY +S 300,3000,300,4500,300,*,DOWN,PDIF +S 300,4400,900,4400,200,*,LEFT,ALU1 +S 900,600,900,4400,200,*,UP,ALU1 +S 1200,2800,1200,4700,100,*,UP,PTRANS +S 600,2800,600,4700,100,*,UP,PTRANS +S 1800,300,1800,1600,100,*,UP,NTRANS +S 2100,500,2100,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +S 300,0,300,600,200,*,UP,ALU1 +S 1500,0,1500,600,200,*,UP,ALU1 +S 1500,0,1500,600,200,*,UP,ALU1 +S 1500,4400,1500,5000,200,*,UP,ALU1 +B 900,4400,200,200,CONT_TURN1,* +V 3000,0,CONT_BODY_P,* +V 3000,5000,CONT_BODY_N,* +V 2100,2700,CONT_DIF_P,* +V 2100,3300,CONT_DIF_P,* +V 2700,600,CONT_DIF_N,* +V 2700,1200,CONT_DIF_N,* +V 2700,3900,CONT_DIF_P,* +V 2700,3300,CONT_DIF_P,* +V 2700,2700,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 2100,600,CONT_DIF_N,* +V 900,2000,CONT_POLY,* +V 400,2000,CONT_POLY,* +V 300,4400,CONT_DIF_P,* +V 1500,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 2100,1200,CONT_DIF_N,* +V 1400,1700,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 1400,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/o2_x4.vbe b/pdks/symbolic/lsxlib/cells/o2_x4.vbe new file mode 100644 index 000000000..e22a93618 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 394; + CONSTANT tphh_i1_q : NATURAL := 427; + CONSTANT tpll_i1_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 491; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x4; + +ARCHITECTURE behaviour_data_flow OF o2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x4" + SEVERITY WARNING; + q <= (i0 or i1) after 1100 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/o3_x2.ap b/pdks/symbolic/lsxlib/cells/o3_x2.ap new file mode 100644 index 000000000..d1f7f42f3 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o3_x2.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 6 +H o3_x2,P, 1/ 8/2024,100 +A 0,0,3000,5000 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 2400,1600,2400,2400,100,*,DOWN,POLY +S 1800,1100,1800,2400,100,*,DOWN,POLY +S 1200,1100,1200,2400,100,*,DOWN,POLY +S 600,1100,600,2400,100,*,DOWN,POLY +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 900,2600,900,4500,300,*,DOWN,PDIF +S 1200,2200,1300,2200,200,*,LEFT,POLY +S 600,2200,800,2200,200,*,LEFT,POLY +S 1800,2400,1800,4700,100,*,UP,PTRANS +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 600,2400,600,4700,100,*,DOWN,PTRANS +S 300,2600,300,4500,300,*,DOWN,PDIF +S 2700,2600,2700,4500,300,*,UP,PDIF +S 2100,2600,2100,4500,300,*,UP,PDIF +S 2400,2400,2400,4700,100,*,UP,PTRANS +S 1800,2200,1800,3900,200,i0,DOWN,CALU1 +S 1300,1600,1300,4400,200,i1,DOWN,CALU1 +S 800,1600,800,4400,200,i2,UP,CALU1 +S 2200,1700,2400,1700,200,*,RIGHT,POLY +S 2200,1100,2200,1700,200,*,DOWN,ALU1 +S 300,1100,2200,1100,200,*,LEFT,ALU1 +S 300,600,300,4400,200,*,DOWN,ALU1 +S 1500,600,1500,1100,200,*,DOWN,ALU1 +S 2100,0,2100,600,200,*,DOWN,ALU1 +S 300,500,300,900,300,*,UP,NDIF +S 600,300,600,1100,100,*,UP,NTRANS +S 900,0,900,600,200,*,UP,ALU1 +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 2400,300,2400,1600,100,*,UP,NTRANS +S 2700,500,2700,1400,300,*,UP,NDIF +S 2100,500,2100,1400,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 2700,600,2700,4400,200,q,DOWN,CALU1 +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +S 0,0,3000,0,300,*,RIGHT,PTIE +S 0,0,3000,0,400,vss,RIGHT,CALU1 +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 0,5000,3000,5000,300,*,RIGHT,NTIE +B 750,2200,300,200,CONT_TURN8,* +B 1800,2200,200,200,CONT_TURN8,* +B 1300,2200,200,200,CONT_TURN8,* +B 2250,1700,300,200,CONT_TURN8,* +B 2200,1100,200,200,CONT_TURN1,* +V 3000,0,CONT_BODY_P,* +V 3000,5000,CONT_BODY_N,* +V 1800,2200,CONT_POLY,* +V 1300,2200,CONT_POLY,* +V 800,2200,CONT_POLY,* +V 300,3300,CONT_DIF_P,* +V 2700,3300,CONT_DIF_P,* +V 300,2700,CONT_DIF_P,* +V 2700,2700,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 2200,1700,CONT_POLY,* +V 300,4400,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 2700,3900,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 2700,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 2700,1200,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/o3_x2.vbe b/pdks/symbolic/lsxlib/cells/o3_x2.vbe new file mode 100644 index 000000000..5aad7aba9 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 360; + CONSTANT tpll_i0_q : NATURAL := 407; + CONSTANT tphh_i1_q : NATURAL := 430; + CONSTANT tpll_i1_q : NATURAL := 482; + CONSTANT tphh_i0_q : NATURAL := 494; + CONSTANT tpll_i2_q : NATURAL := 506; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x2; + +ARCHITECTURE behaviour_data_flow OF o3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x2" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1100 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/o3_x4.ap b/pdks/symbolic/lsxlib/cells/o3_x4.ap new file mode 100644 index 000000000..e980a22a9 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o3_x4.ap @@ -0,0 +1,109 @@ +V ALLIANCE : 6 +H o3_x4,P, 1/ 8/2024,100 +A 0,0,4000,5000 +S 0,1100,4000,1100,1400,*,RIGHT,PWELL +S 3600,0,3600,1200,200,*,DOWN,ALU1 +S 2500,1700,3300,1700,200,*,RIGHT,POLY +S 2700,1600,2700,2400,100,*,DOWN,POLY +S 1400,1600,1400,4400,200,i1,DOWN,CALU1 +S 1600,2400,1600,4700,100,*,UP,PTRANS +S 1100,2400,1100,4700,100,*,DOWN,PTRANS +S 800,2600,800,4500,300,*,DOWN,PDIF +S 2100,2400,2100,4700,100,*,UP,PTRANS +S 3600,2600,3600,4500,300,*,UP,PDIF +S 3300,2400,3300,4700,100,*,UP,PTRANS +S 2700,2400,2700,4700,100,*,UP,PTRANS +S 2400,2600,2400,4500,300,*,UP,PDIF +S 3000,2600,3000,4500,300,*,UP,PDIF +S 1500,300,1500,1100,100,*,DOWN,NTRANS +S 900,300,900,1100,100,*,UP,NTRANS +S 3300,300,3300,1600,100,*,UP,NTRANS +S 2700,300,2700,1600,100,*,UP,NTRANS +S 2100,300,2100,1100,100,*,DOWN,NTRANS +S 3000,500,3000,1400,300,*,UP,NDIF +S 3600,500,3600,1400,300,*,UP,NDIF +S 600,500,600,900,300,*,UP,NDIF +S 1800,500,1800,900,300,*,UP,NDIF +S 1200,500,1200,900,300,*,UP,NDIF +S 2400,500,2400,1400,300,*,UP,NDIF +S 900,2400,1100,2400,100,*,RIGHT,POLY +S 1500,2400,1600,2400,100,*,LEFT,POLY +S 300,1700,900,1700,100,*,RIGHT,POLY +S 2100,1100,2100,2400,100,*,DOWN,POLY +S 3300,1600,3300,2400,100,*,DOWN,POLY +S 1900,1700,2100,1700,200,*,RIGHT,POLY +S 1400,1700,1500,1700,200,*,RIGHT,POLY +S 900,1100,900,2400,100,*,DOWN,POLY +S 1500,1100,1500,2400,100,*,DOWN,POLY +S 1200,0,1200,600,200,*,UP,ALU1 +S 2400,0,2400,600,200,*,DOWN,ALU1 +S 600,1100,2500,1100,200,*,LEFT,ALU1 +S 800,1100,800,4400,200,*,DOWN,ALU1 +S 600,600,600,1100,200,*,DOWN,ALU1 +S 300,1600,300,4400,200,i2,UP,CALU1 +S 3600,2700,3600,5000,200,*,UP,ALU1 +S 2400,2700,2400,5000,200,*,UP,ALU1 +S 1900,1600,1900,4400,200,i0,DOWN,CALU1 +S 3000,600,3000,4400,200,q,DOWN,CALU1 +S 1800,600,1800,1100,200,*,DOWN,ALU1 +S 2500,1100,2500,1700,200,*,DOWN,ALU1 +S 0,0,4000,0,300,*,RIGHT,PTIE +S 0,0,4000,0,400,vss,RIGHT,CALU1 +S 0,4000,4000,4000,1200,*,RIGHT,NWELL +S 0,3100,4000,3100,1200,*,RIGHT,NWELL +S 0,5000,4000,5000,300,*,RIGHT,NTIE +S 0,5000,4000,5000,400,vdd,RIGHT,CALU1 +B 550,1700,700,200,CONT_TURN8,* +B 1400,1700,200,200,CONT_TURN8,* +B 1950,1700,300,200,CONT_TURN8,* +B 2850,1700,900,200,CONT_TURN8,* +B 2500,1100,200,200,CONT_TURN1,* +B 600,1100,200,200,CONT_TURN1,* +V 800,3300,CONT_DIF_P,* +V 2400,3900,CONT_DIF_P,* +V 2400,3300,CONT_DIF_P,* +V 800,2700,CONT_DIF_P,* +V 800,4400,CONT_DIF_P,* +V 800,3900,CONT_DIF_P,* +V 2400,2700,CONT_DIF_P,* +V 3600,4400,CONT_DIF_P,* +V 3600,3300,CONT_DIF_P,* +V 3600,2700,CONT_DIF_P,* +V 3000,3300,CONT_DIF_P,* +V 3000,4400,CONT_DIF_P,* +V 2400,4400,CONT_DIF_P,* +V 3000,3900,CONT_DIF_P,* +V 3600,3900,CONT_DIF_P,* +V 3000,2700,CONT_DIF_P,* +V 3600,600,CONT_DIF_N,* +V 3000,1200,CONT_DIF_N,* +V 1200,600,CONT_DIF_N,* +V 1800,600,CONT_DIF_N,* +V 2400,600,CONT_DIF_N,* +V 3600,1200,CONT_DIF_N,* +V 2400,600,CONT_DIF_N,* +V 3000,600,CONT_DIF_N,* +V 600,600,CONT_DIF_N,* +V 300,1700,CONT_POLY,* +V 1900,1700,CONT_POLY,* +V 1400,1700,CONT_POLY,* +V 2500,1700,CONT_POLY,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/o3_x4.vbe b/pdks/symbolic/lsxlib/cells/o3_x4.vbe new file mode 100644 index 000000000..1e7ea94f8 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 447; + CONSTANT tpll_i0_q : NATURAL := 501; + CONSTANT tphh_i1_q : NATURAL := 510; + CONSTANT tphh_i0_q : NATURAL := 569; + CONSTANT tpll_i1_q : NATURAL := 585; + CONSTANT tpll_i2_q : NATURAL := 622; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x4; + +ARCHITECTURE behaviour_data_flow OF o3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x4" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/o4_x2.ap b/pdks/symbolic/lsxlib/cells/o4_x2.ap new file mode 100644 index 000000000..2a0e03de4 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o4_x2.ap @@ -0,0 +1,109 @@ +V ALLIANCE : 6 +H o4_x2,P, 1/ 8/2024,100 +A 0,0,4000,5000 +S 0,1100,4000,1100,1400,*,RIGHT,PWELL +S 900,1600,900,4400,200,i3,UP,CALU1 +S 2200,2600,2200,4500,300,*,DOWN,PDIF +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 1900,1100,1900,2400,100,*,DOWN,POLY +S 700,1100,700,2400,100,*,DOWN,POLY +S 1300,1100,1300,2400,100,*,DOWN,POLY +S 2500,1100,2500,2400,100,*,DOWN,POLY +S 3300,1600,3300,2400,100,*,DOWN,POLY +S 2500,2200,2500,4400,200,i0,DOWN,CALU1 +S 3000,0,3000,1200,200,*,DOWN,ALU1 +S 3000,2700,3000,5000,200,*,UP,ALU1 +S 400,1100,2500,1100,200,*,RIGHT,ALU1 +S 2500,1100,2500,1700,200,*,DOWN,ALU1 +S 2500,1700,3100,1700,200,*,LEFT,ALU1 +S 2900,500,2900,1400,300,*,UP,NDIF +S 2900,2600,2900,4500,300,*,UP,PDIF +S 400,2600,400,4500,300,*,DOWN,PDIF +S 1300,2400,1300,4700,100,*,DOWN,PTRANS +S 700,2400,700,4700,100,*,DOWN,PTRANS +S 1900,2400,1900,4700,100,*,UP,PTRANS +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 1300,300,1300,1100,100,*,UP,NTRANS +S 700,300,700,1100,100,*,UP,NTRANS +S 2500,300,2500,1100,100,*,DOWN,NTRANS +S 1900,300,1900,1100,100,*,DOWN,NTRANS +S 1000,500,1000,900,300,*,DOWN,NDIF +S 2200,500,2200,900,300,*,UP,NDIF +S 1600,500,1600,900,300,*,UP,NDIF +S 400,500,400,900,300,*,UP,NDIF +S 2500,2400,2500,4700,100,*,UP,PTRANS +S 1300,2200,1500,2200,200,*,LEFT,POLY +S 700,2200,900,2200,200,*,LEFT,POLY +S 1900,2200,2000,2200,200,*,LEFT,POLY +S 1600,0,1600,600,200,*,UP,ALU1 +S 400,0,400,600,200,*,DOWN,ALU1 +S 2000,1600,2000,4400,200,i1,DOWN,CALU1 +S 1000,600,1000,1100,200,*,UP,ALU1 +S 400,1100,400,4400,200,*,DOWN,ALU1 +S 2200,600,2200,1100,200,*,DOWN,ALU1 +S 1500,1600,1500,4400,200,i2,UP,CALU1 +S 0,4000,4000,4000,1200,*,RIGHT,NWELL +S 0,3100,4000,3100,1200,*,RIGHT,NWELL +S 3300,2400,3300,4700,100,*,UP,PTRANS +S 3600,2600,3600,4500,300,*,UP,PDIF +S 3300,300,3300,1600,100,*,UP,NTRANS +S 3600,500,3600,1400,300,*,UP,NDIF +S 3100,1700,3300,1700,200,*,RIGHT,POLY +S 3600,600,3600,4400,200,q,DOWN,CALU1 +S 0,0,4000,0,300,*,RIGHT,PTIE +S 0,0,4000,0,400,vss,RIGHT,CALU1 +S 0,5000,4000,5000,300,*,RIGHT,NTIE +S 0,5000,4000,5000,400,vdd,RIGHT,CALU1 +B 3150,1700,300,200,CONT_TURN8,* +B 2500,2200,200,200,CONT_TURN8,* +B 2000,2200,200,200,CONT_TURN8,* +B 1450,2200,300,200,CONT_TURN8,* +B 850,2200,300,200,CONT_TURN8,* +B 400,1100,200,200,CONT_TURN1,* +B 2500,1100,200,200,CONT_TURN1,* +B 2500,1700,200,200,CONT_TURN1,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3000,1200,CONT_DIF_N,* +V 3000,3900,CONT_DIF_P,* +V 3000,3300,CONT_DIF_P,* +V 3000,2700,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 400,3300,CONT_DIF_P,* +V 400,2700,CONT_DIF_P,* +V 1000,600,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 2200,600,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 1500,2200,CONT_POLY,* +V 2000,2200,CONT_POLY,* +V 900,2200,CONT_POLY,* +V 2500,2200,CONT_POLY,* +V 3600,4400,CONT_DIF_P,* +V 3000,4400,CONT_DIF_P,* +V 3600,3900,CONT_DIF_P,* +V 3600,2700,CONT_DIF_P,* +V 3600,3300,CONT_DIF_P,* +V 3600,1200,CONT_DIF_N,* +V 3000,600,CONT_DIF_N,* +V 3000,600,CONT_DIF_N,* +V 3600,600,CONT_DIF_N,* +V 3100,1700,CONT_POLY,* +V 3000,0,CONT_BODY_P,* +V 3000,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/o4_x2.vbe b/pdks/symbolic/lsxlib/cells/o4_x2.vbe new file mode 100644 index 000000000..09652e62b --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i3_q : NATURAL := 378; + CONSTANT tphh_i1_q : NATURAL := 446; + CONSTANT tphh_i0_q : NATURAL := 508; + CONSTANT tpll_i2_q : NATURAL := 531; + CONSTANT tphh_i2_q : NATURAL := 567; + CONSTANT tpll_i0_q : NATURAL := 601; + CONSTANT tpll_i3_q : NATURAL := 626; + CONSTANT tpll_i1_q : NATURAL := 631; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x2; + +ARCHITECTURE behaviour_data_flow OF o4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x2" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/o4_x4.ap b/pdks/symbolic/lsxlib/cells/o4_x4.ap new file mode 100644 index 000000000..7ac20e286 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o4_x4.ap @@ -0,0 +1,125 @@ +V ALLIANCE : 6 +H o4_x4,P, 1/ 8/2024,100 +A 0,0,4500,5000 +S 0,1100,4500,1100,1400,*,RIGHT,PWELL +S 900,1600,900,4400,200,i3,UP,CALU1 +S 2200,2600,2200,4500,300,*,UP,PDIF +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 0,0,4500,0,300,*,RIGHT,PTIE +S 0,0,4500,0,400,vss,RIGHT,CALU1 +S 0,4000,4500,4000,1200,*,RIGHT,NWELL +S 0,3100,4500,3100,1200,*,RIGHT,NWELL +S 0,5000,4500,5000,300,*,RIGHT,NTIE +S 0,5000,4500,5000,400,vdd,RIGHT,CALU1 +S 3100,1700,3900,1700,200,*,RIGHT,POLY +S 3900,1600,3900,2400,100,*,DOWN,POLY +S 4200,2700,4200,5000,200,*,UP,ALU1 +S 4200,500,4200,1400,300,*,DOWN,NDIF +S 4200,2600,4200,4500,300,*,UP,PDIF +S 4200,0,4200,1200,200,*,DOWN,ALU1 +S 3900,300,3900,1600,100,*,UP,NTRANS +S 2500,1100,2500,2400,100,*,DOWN,POLY +S 1900,1100,1900,2400,100,*,DOWN,POLY +S 700,1100,700,2400,100,*,DOWN,POLY +S 1300,1100,1300,2400,100,*,DOWN,POLY +S 3300,1600,3300,2400,100,*,DOWN,POLY +S 3900,2400,3900,4700,100,*,DOWN,PTRANS +S 2500,2200,2500,4400,200,i0,DOWN,CALU1 +S 3000,0,3000,1200,200,*,DOWN,ALU1 +S 3000,2700,3000,5000,200,*,UP,ALU1 +S 400,1100,2500,1100,200,*,RIGHT,ALU1 +S 2500,1100,2500,1700,200,*,DOWN,ALU1 +S 2500,1700,3100,1700,200,*,LEFT,ALU1 +S 2900,500,2900,1400,300,*,UP,NDIF +S 2900,2600,2900,4500,300,*,UP,PDIF +S 400,2600,400,4500,300,*,DOWN,PDIF +S 1300,2400,1300,4700,100,*,DOWN,PTRANS +S 700,2400,700,4700,100,*,DOWN,PTRANS +S 1900,2400,1900,4700,100,*,UP,PTRANS +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 1300,300,1300,1100,100,*,UP,NTRANS +S 700,300,700,1100,100,*,UP,NTRANS +S 2500,300,2500,1100,100,*,DOWN,NTRANS +S 1900,300,1900,1100,100,*,DOWN,NTRANS +S 1000,500,1000,900,300,*,DOWN,NDIF +S 2200,500,2200,900,300,*,UP,NDIF +S 1600,500,1600,900,300,*,UP,NDIF +S 400,500,400,900,300,*,UP,NDIF +S 2500,2400,2500,4700,100,*,UP,PTRANS +S 1300,2200,1500,2200,200,*,LEFT,POLY +S 700,2200,900,2200,200,*,LEFT,POLY +S 1900,2200,2000,2200,200,*,LEFT,POLY +S 1600,0,1600,600,200,*,UP,ALU1 +S 400,0,400,600,200,*,DOWN,ALU1 +S 2000,1600,2000,4400,200,i1,DOWN,CALU1 +S 1000,600,1000,1100,200,*,UP,ALU1 +S 400,1100,400,4400,200,*,DOWN,ALU1 +S 2200,600,2200,1100,200,*,DOWN,ALU1 +S 1500,1600,1500,4400,200,i2,UP,CALU1 +S 3300,2400,3300,4700,100,*,UP,PTRANS +S 3600,2600,3600,4500,300,*,UP,PDIF +S 3300,300,3300,1600,100,*,UP,NTRANS +S 3600,500,3600,1400,300,*,UP,NDIF +S 3600,600,3600,4400,200,q,DOWN,CALU1 +B 3450,1700,900,200,CONT_TURN8,* +B 2500,2200,200,200,CONT_TURN8,* +B 2000,2200,200,200,CONT_TURN8,* +B 1450,2200,300,200,CONT_TURN8,* +B 850,2200,300,200,CONT_TURN8,* +B 2500,1700,200,200,CONT_TURN1,* +B 2500,1100,200,200,CONT_TURN1,* +B 400,1100,200,200,CONT_TURN1,* +V 4500,0,CONT_BODY_P,* +V 4500,5000,CONT_BODY_N,* +V 4200,4400,CONT_DIF_P,* +V 4200,3900,CONT_DIF_P,* +V 4200,3300,CONT_DIF_P,* +V 4200,2700,CONT_DIF_P,* +V 4200,600,CONT_DIF_N,* +V 4200,600,CONT_DIF_N,* +V 4200,1200,CONT_DIF_N,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3000,1200,CONT_DIF_N,* +V 3000,3900,CONT_DIF_P,* +V 3000,3300,CONT_DIF_P,* +V 3000,2700,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 400,3300,CONT_DIF_P,* +V 400,2700,CONT_DIF_P,* +V 1000,600,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 2200,600,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 1500,2200,CONT_POLY,* +V 2000,2200,CONT_POLY,* +V 900,2200,CONT_POLY,* +V 2500,2200,CONT_POLY,* +V 3600,4400,CONT_DIF_P,* +V 3000,4400,CONT_DIF_P,* +V 3600,3900,CONT_DIF_P,* +V 3600,2700,CONT_DIF_P,* +V 3600,3300,CONT_DIF_P,* +V 3600,1200,CONT_DIF_N,* +V 3000,600,CONT_DIF_N,* +V 3000,600,CONT_DIF_N,* +V 3600,600,CONT_DIF_N,* +V 3100,1700,CONT_POLY,* +V 3000,0,CONT_BODY_P,* +V 3000,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/o4_x4.vbe b/pdks/symbolic/lsxlib/cells/o4_x4.vbe new file mode 100644 index 000000000..bc869a8fb --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/o4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 492; + CONSTANT tpll_i3_q : NATURAL := 536; + CONSTANT tphh_i0_q : NATURAL := 574; + CONSTANT tpll_i2_q : NATURAL := 611; + CONSTANT tpll_i0_q : NATURAL := 638; + CONSTANT tphh_i2_q : NATURAL := 649; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 721; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x4; + +ARCHITECTURE behaviour_data_flow OF o4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x4" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa22_x2.ap b/pdks/symbolic/lsxlib/cells/oa22_x2.ap new file mode 100644 index 000000000..884c3e419 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa22_x2.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 6 +H oa22_x2,P, 5/ 8/2024,100 +A 0,0,3000,5000 +S 2000,1600,2000,1700,200,*,DOWN,POLY2 +S 2000,2500,2000,2600,200,*,UP,POLY2 +S 0,1100,3000,1100,1400,*,RIGHT,PWELL +S 1800,2600,1800,3400,100,*,UP,POLY +S 1800,1100,1800,1600,100,*,DOWN,POLY +S 1800,1600,2000,1600,100,*,LEFT,POLY +S 1800,2600,2000,2600,100,*,LEFT,POLY +S 1500,600,1500,3900,200,*,DOWN,ALU1 +S 2700,600,2700,4400,200,q,UP,CALU1 +S 1100,3400,1200,3400,100,*,LEFT,POLY +S 1100,1100,1200,1100,100,*,LEFT,POLY +S 1000,2000,1100,2000,200,*,RIGHT,POLY +S 1100,1100,1100,3400,100,*,DOWN,POLY +S 1500,2100,2400,2100,100,*,RIGHT,POLY +S 2700,2800,2700,4500,300,*,DOWN,PDIF +S 2100,2800,2100,4500,300,*,DOWN,PDIF +S 2400,1600,2400,2600,100,*,DOWN,POLY +S 2400,2600,2400,4700,100,*,DOWN,PTRANS +S 2100,500,2100,1400,300,*,DOWN,NDIF +S 2700,500,2700,1400,300,*,DOWN,NDIF +S 0,0,3000,0,300,*,RIGHT,PTIE +S 0,0,3000,0,400,vss,LEFT,CALU1 +S 0,4000,3000,4000,1200,*,RIGHT,NWELL +S 0,3100,3000,3100,1200,*,RIGHT,NWELL +S 0,5000,3000,5000,300,*,RIGHT,NTIE +S 0,5000,3000,5000,400,vdd,RIGHT,CALU1 +S 2400,300,2400,1600,100,*,UP,NTRANS +S 600,1100,600,3400,100,*,DOWN,POLY +S 1200,3400,1200,4700,100,*,UP,PTRANS +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 300,3600,300,4500,300,*,DOWN,PDIF +S 600,3400,600,4700,100,*,UP,PTRANS +S 900,3600,900,4500,300,*,DOWN,PDIF +S 600,300,600,1100,100,*,DOWN,NTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 2100,500,2100,900,300,*,UP,NDIF +S 400,1100,400,3400,200,i0,DOWN,CALU1 +S 300,4400,1500,4400,200,*,RIGHT,ALU1 +S 300,3900,300,4400,200,*,UP,ALU1 +S 900,3900,1500,3900,200,*,RIGHT,ALU1 +S 1000,600,1000,3400,200,i1,DOWN,CALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +S 2000,1100,2000,3800,200,i2,DOWN,CALU1 +S 400,2000,600,2000,200,*,RIGHT,POLY +S 2100,0,2100,600,200,*,UP,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +B 1000,2000,200,200,CONT_TURN8,* +B 450,2000,300,200,CONT_TURN8,* +B 1500,3900,200,200,CONT_TURN1,* +V 2700,1300,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 2700,3900,CONT_DIF_P,* +V 2700,3400,CONT_DIF_P,* +V 2700,2900,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 1500,2100,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1700,CONT_POLY,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 300,3900,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 900,3900,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 400,2000,CONT_POLY,* +V 1500,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 1000,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa22_x2.vbe b/pdks/symbolic/lsxlib/cells/oa22_x2.vbe new file mode 100644 index 000000000..d2d267604 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 390; + CONSTANT tphh_i2_q : NATURAL := 438; + CONSTANT tpll_i2_q : NATURAL := 454; + CONSTANT tphh_i1_q : NATURAL := 488; + CONSTANT tpll_i1_q : NATURAL := 525; + CONSTANT tpll_i0_q : NATURAL := 555; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x2; + +ARCHITECTURE behaviour_data_flow OF oa22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa22_x4.ap b/pdks/symbolic/lsxlib/cells/oa22_x4.ap new file mode 100644 index 000000000..2cf31c2c9 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa22_x4.ap @@ -0,0 +1,114 @@ +V ALLIANCE : 6 +H oa22_x4,P, 1/ 8/2024,100 +A 0,0,4000,5000 +S 0,1100,4000,1100,1400,*,RIGHT,PWELL +S 1300,600,1500,600,200,*,LEFT,ALU1 +S 900,3900,1300,3900,200,*,RIGHT,ALU1 +S 1300,2100,3300,2100,200,*,RIGHT,POLY +S 1800,3300,1800,3400,100,*,UP,POLY +S 1800,1100,1800,1200,100,*,DOWN,POLY +S 2300,0,2300,1300,200,*,DOWN,ALU1 +S 3600,0,3600,1300,200,*,DOWN,ALU1 +S 3600,2700,3600,5000,200,*,UP,ALU1 +S 2300,2700,2300,5000,200,*,UP,ALU1 +S 2300,500,2300,1400,300,*,DOWN,NDIF +S 3600,500,3600,1400,300,*,DOWN,NDIF +S 3300,300,3300,1600,100,*,DOWN,NTRANS +S 3300,1600,3300,2400,100,*,DOWN,POLY +S 2700,1600,2700,2400,100,*,DOWN,POLY +S 2300,2600,2300,4500,300,*,DOWN,PDIF +S 2700,2400,2700,4700,100,*,DOWN,PTRANS +S 2100,3600,2100,4500,300,*,DOWN,PDIF +S 1200,2600,1200,3400,100,*,UP,POLY +S 800,2600,1200,2600,100,*,RIGHT,POLY +S 800,1600,800,2600,100,*,UP,POLY +S 800,1600,1200,1600,100,*,LEFT,POLY +S 1200,1100,1200,1600,100,*,UP,POLY +S 1300,600,1300,3900,200,*,DOWN,ALU1 +S 1800,1100,1800,3800,200,i2,DOWN,CALU1 +S 3000,2800,3000,4500,300,*,DOWN,PDIF +S 3600,2600,3600,4500,300,*,DOWN,PDIF +S 3300,2400,3300,4700,100,*,DOWN,PTRANS +S 2700,300,2700,1600,100,*,UP,NTRANS +S 3000,500,3000,1400,300,*,DOWN,NDIF +S 3000,600,3000,4400,200,q,UP,CALU1 +S 800,600,800,3400,200,i1,DOWN,CALU1 +S 300,3400,600,3400,100,*,LEFT,POLY +S 300,1100,600,1100,100,*,LEFT,POLY +S 300,1100,300,3400,100,*,DOWN,POLY +S 300,1100,300,3400,200,i0,DOWN,CALU1 +S 0,0,4000,0,300,*,RIGHT,PTIE +S 0,0,4000,0,400,vss,LEFT,CALU1 +S 0,4000,4000,4000,1200,*,RIGHT,NWELL +S 0,3100,4000,3100,1200,*,RIGHT,NWELL +S 0,5000,4000,5000,300,*,RIGHT,NTIE +S 0,5000,4000,5000,400,vdd,RIGHT,CALU1 +S 1200,3400,1200,4700,100,*,UP,PTRANS +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 300,3600,300,4500,300,*,DOWN,PDIF +S 600,3400,600,4700,100,*,UP,PTRANS +S 900,3600,900,4500,300,*,DOWN,PDIF +S 600,300,600,1100,100,*,DOWN,NTRANS +S 1200,300,1200,1100,100,*,DOWN,NTRANS +S 1800,300,1800,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 1500,500,1500,900,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 2100,500,2100,900,300,*,UP,NDIF +S 300,4400,1500,4400,200,*,RIGHT,ALU1 +S 300,3900,300,4400,200,*,UP,ALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +B 2250,2100,2100,200,CONT_TURN8,* +B 1800,1200,200,200,CONT_TURN8,* +B 1800,3300,200,200,CONT_TURN8,* +B 1300,600,200,200,CONT_TURN1,* +B 1300,3900,200,200,CONT_TURN1,* +V 1800,1200,CONT_POLY,* +V 1800,3300,CONT_POLY,* +V 2300,3900,CONT_DIF_P,* +V 2300,3300,CONT_DIF_P,* +V 2300,2700,CONT_DIF_P,* +V 3600,2700,CONT_DIF_P,* +V 3600,3300,CONT_DIF_P,* +V 3600,3900,CONT_DIF_P,* +V 3600,4400,CONT_DIF_P,* +V 3000,3300,CONT_DIF_P,* +V 3000,2700,CONT_DIF_P,* +V 3600,600,CONT_DIF_N,* +V 3600,1300,CONT_DIF_N,* +V 2300,1300,CONT_DIF_N,* +V 2300,600,CONT_DIF_N,* +V 300,2100,CONT_POLY,* +V 800,2100,CONT_POLY,* +V 1300,2100,CONT_POLY,* +V 2300,4400,CONT_DIF_P,* +V 3000,4400,CONT_DIF_P,* +V 3000,3900,CONT_DIF_P,* +V 3000,600,CONT_DIF_N,* +V 3000,1300,CONT_DIF_N,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 300,3900,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 900,3900,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 1500,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa22_x4.vbe b/pdks/symbolic/lsxlib/cells/oa22_x4.vbe new file mode 100644 index 000000000..fa425e333 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 511; + CONSTANT tphh_i2_q : NATURAL := 523; + CONSTANT tpll_i2_q : NATURAL := 571; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tpll_i0_q : NATURAL := 677; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x4; + +ARCHITECTURE behaviour_data_flow OF oa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa2a22_x2.ap b/pdks/symbolic/lsxlib/cells/oa2a22_x2.ap new file mode 100644 index 000000000..91f1de4f0 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a22_x2.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H oa2a22_x2,P, 1/ 8/2024,100 +A 0,0,4500,5000 +S 0,1100,4500,1100,1400,*,RIGHT,PWELL +S 3000,2100,3800,2100,100,*,LEFT,POLY +S 3800,1600,3800,2400,100,*,UP,POLY +S 300,2100,600,2100,100,*,RIGHT,POLY +S 3500,600,3500,4400,200,q,UP,CALU1 +S 2400,300,2400,1200,100,*,DOWN,NTRANS +S 1800,300,1800,1200,100,*,DOWN,NTRANS +S 1200,300,1200,1200,100,*,DOWN,NTRANS +S 600,300,600,1200,100,*,DOWN,NTRANS +S 300,500,300,1000,300,*,UP,NDIF +S 2700,500,2700,1000,300,*,UP,NDIF +S 2100,500,2100,1000,300,*,UP,NDIF +S 1500,500,1500,1000,300,*,UP,NDIF +S 900,500,900,1000,300,*,UP,NDIF +S 2700,3900,2700,4400,200,*,DOWN,ALU1 +S 1500,3900,1500,4400,200,*,DOWN,ALU1 +S 300,3900,300,4400,200,*,DOWN,ALU1 +S 600,3200,600,4700,100,*,UP,PTRANS +S 300,3400,300,4500,300,*,DOWN,PDIF +S 1500,3400,1500,4500,300,*,DOWN,PDIF +S 2700,3400,2700,4500,300,*,DOWN,PDIF +S 1800,3200,1800,4700,100,*,UP,PTRANS +S 2100,3400,2100,4500,300,*,DOWN,PDIF +S 2400,3200,2400,4700,100,*,UP,PTRANS +S 1200,3200,1200,4700,100,*,UP,PTRANS +S 900,3400,900,4500,300,*,DOWN,PDIF +S 600,1200,600,3200,100,*,DOWN,POLY +S 1200,1200,1200,3200,100,*,DOWN,POLY +S 1800,1200,1800,3200,100,*,DOWN,POLY +S 2400,1200,2400,3200,100,*,DOWN,POLY +S 2000,1600,2000,3400,200,i3,DOWN,CALU1 +S 3500,2600,3500,4500,300,*,DOWN,PDIF +S 3800,2400,3800,4700,100,*,DOWN,PTRANS +S 4100,0,4100,1300,200,*,DOWN,ALU1 +S 4100,2700,4100,5000,200,*,UP,ALU1 +S 4100,2600,4100,4500,300,*,UP,PDIF +S 3800,300,3800,1600,100,*,UP,NTRANS +S 3500,500,3500,1400,300,*,DOWN,NDIF +S 4100,500,4100,1400,300,*,DOWN,NDIF +S 0,5000,4500,5000,400,vdd,RIGHT,CALU1 +S 0,5000,4500,5000,300,*,RIGHT,NTIE +S 0,4000,4500,4000,1200,*,RIGHT,NWELL +S 0,3100,4500,3100,1200,*,RIGHT,NWELL +S 0,0,4500,0,300,*,RIGHT,PTIE +S 0,0,4500,0,400,vss,RIGHT,CALU1 +S 1500,600,1500,3400,200,*,DOWN,ALU1 +S 1500,1100,3000,1100,200,*,RIGHT,ALU1 +S 3000,1100,3000,2100,200,*,UP,ALU1 +S 2500,1600,2500,3400,200,i2,DOWN,CALU1 +S 2700,0,2700,600,200,*,DOWN,ALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 900,3400,900,3900,200,*,DOWN,ALU1 +S 1500,3900,2700,3900,200,*,RIGHT,ALU1 +S 300,4400,1500,4400,200,*,RIGHT,ALU1 +S 900,3400,1500,3400,200,*,RIGHT,ALU1 +S 300,1100,300,3400,200,i0,DOWN,CALU1 +S 1000,600,1000,2900,200,i1,DOWN,CALU1 +S 1000,2100,1200,2100,200,*,RIGHT,POLY +S 1800,2100,2000,2100,200,*,RIGHT,POLY +B 2500,2100,200,200,CONT_TURN8,* +B 3350,2100,900,200,CONT_TURN8,* +B 1950,2100,300,200,CONT_TURN8,* +B 1050,2100,300,200,CONT_TURN8,* +B 400,2100,400,200,CONT_TURN8,* +B 3000,1100,200,200,CONT_TURN1,* +B 1500,3400,200,200,CONT_TURN1,* +B 900,3400,200,200,CONT_TURN1,* +V 3500,1300,CONT_DIF_N,* +V 3500,2700,CONT_DIF_P,* +V 3500,3200,CONT_DIF_P,* +V 4100,2700,CONT_DIF_P,* +V 4100,3200,CONT_DIF_P,* +V 3500,3800,CONT_DIF_P,* +V 4500,5000,CONT_BODY_N,* +V 4500,0,CONT_BODY_P,* +V 3500,4400,CONT_DIF_P,* +V 4100,3800,CONT_DIF_P,* +V 4100,4400,CONT_DIF_P,* +V 3500,600,CONT_DIF_N,* +V 4100,1300,CONT_DIF_N,* +V 4100,600,CONT_DIF_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,2100,CONT_POLY,* +V 900,3900,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 1500,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1000,2100,CONT_POLY,* +V 2000,2100,CONT_POLY,* +V 300,2100,CONT_POLY,* +V 2500,2100,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa2a22_x2.vbe b/pdks/symbolic/lsxlib/cells/oa2a22_x2.vbe new file mode 100644 index 000000000..1c5c40883 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 403; + CONSTANT tpll_i2_q : NATURAL := 487; + CONSTANT tphh_i1_q : NATURAL := 495; + CONSTANT tpll_i3_q : NATURAL := 512; + CONSTANT tpll_i1_q : NATURAL := 534; + CONSTANT tphh_i3_q : NATURAL := 537; + CONSTANT tpll_i0_q : NATURAL := 564; + CONSTANT tphh_i2_q : NATURAL := 646; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa2a22_x4.ap b/pdks/symbolic/lsxlib/cells/oa2a22_x4.ap new file mode 100644 index 000000000..c0608a3bd --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a22_x4.ap @@ -0,0 +1,135 @@ +V ALLIANCE : 6 +H oa2a22_x4,P, 1/ 8/2024,100 +A 0,0,5000,5000 +S 0,1100,5000,1100,1400,*,RIGHT,PWELL +S 4400,1600,4400,2400,100,*,UP,POLY +S 3800,1600,3800,2400,100,*,UP,POLY +S 300,2100,600,2100,100,*,RIGHT,POLY +S 2400,300,2400,1300,100,*,DOWN,NTRANS +S 1800,300,1800,1300,100,*,DOWN,NTRANS +S 1200,300,1200,1300,100,*,DOWN,NTRANS +S 600,300,600,1300,100,*,DOWN,NTRANS +S 300,500,300,1100,300,*,UP,NDIF +S 2700,500,2700,1100,300,*,UP,NDIF +S 2100,500,2100,1100,300,*,UP,NDIF +S 1500,500,1500,1100,300,*,UP,NDIF +S 900,500,900,1100,300,*,UP,NDIF +S 900,3400,900,3900,200,*,DOWN,ALU1 +S 2700,3900,2700,4400,200,*,DOWN,ALU1 +S 1500,3900,1500,4400,200,*,DOWN,ALU1 +S 300,3900,300,4400,200,*,DOWN,ALU1 +S 900,3200,900,4500,300,*,DOWN,PDIF +S 600,3000,600,4700,100,*,UP,PTRANS +S 300,3200,300,4500,300,*,DOWN,PDIF +S 1500,3200,1500,4500,300,*,DOWN,PDIF +S 2700,3200,2700,4500,300,*,DOWN,PDIF +S 1800,3000,1800,4700,100,*,UP,PTRANS +S 2100,3200,2100,4500,300,*,DOWN,PDIF +S 2400,3000,2400,4700,100,*,UP,PTRANS +S 1200,3000,1200,4700,100,*,UP,PTRANS +S 2400,1300,2400,3000,100,*,DOWN,POLY +S 1800,1300,1800,3000,100,*,DOWN,POLY +S 600,1300,600,3000,100,*,DOWN,POLY +S 1200,1300,1200,3000,100,*,DOWN,POLY +S 3000,2100,4400,2100,200,*,RIGHT,POLY +S 4700,2700,4700,5000,200,*,UP,ALU1 +S 3500,2700,3500,5000,200,*,UP,ALU1 +S 4700,0,4700,1300,200,*,DOWN,ALU1 +S 3500,0,3500,1300,200,*,DOWN,ALU1 +S 4100,600,4100,4400,200,q,UP,CALU1 +S 4700,2600,4700,4500,300,*,UP,PDIF +S 4400,300,4400,1600,100,*,UP,NTRANS +S 4700,500,4700,1400,300,*,DOWN,NDIF +S 4400,2400,4400,4700,100,*,DOWN,PTRANS +S 0,0,5000,0,300,*,RIGHT,PTIE +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 0,5000,5100,5000,400,vdd,RIGHT,CALU1 +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +S 2000,1600,2000,3400,200,i3,DOWN,CALU1 +S 3500,2600,3500,4500,300,*,DOWN,PDIF +S 3800,2400,3800,4700,100,*,DOWN,PTRANS +S 4100,2600,4100,4500,300,*,UP,PDIF +S 3800,300,3800,1600,100,*,UP,NTRANS +S 3500,500,3500,1400,300,*,DOWN,NDIF +S 4100,500,4100,1400,300,*,DOWN,NDIF +S 1500,600,1500,3400,200,*,DOWN,ALU1 +S 1500,1100,3000,1100,200,*,RIGHT,ALU1 +S 3000,1100,3000,2100,200,*,UP,ALU1 +S 2500,1600,2500,3400,200,i2,DOWN,CALU1 +S 2700,0,2700,600,200,*,DOWN,ALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +S 2100,4400,2100,5000,200,*,UP,ALU1 +S 1500,3900,2700,3900,200,*,RIGHT,ALU1 +S 300,4400,1500,4400,200,*,RIGHT,ALU1 +S 900,3400,1500,3400,200,*,RIGHT,ALU1 +S 300,1100,300,3400,200,i0,DOWN,CALU1 +S 1000,600,1000,2900,200,i1,DOWN,CALU1 +S 1000,2100,1200,2100,200,*,RIGHT,POLY +S 1800,2100,2000,2100,200,*,RIGHT,POLY +B 3650,2100,1500,200,CONT_TURN8,* +B 2500,2100,200,200,CONT_TURN8,* +B 1950,2100,300,200,CONT_TURN8,* +B 1050,2100,300,200,CONT_TURN8,* +B 400,2100,400,200,CONT_TURN8,* +B 3000,1100,200,200,CONT_TURN1,* +B 1500,3400,200,200,CONT_TURN1,* +B 900,3400,200,200,CONT_TURN1,* +V 5000,0,CONT_BODY_P,* +V 5000,5000,CONT_BODY_N,* +V 4700,2700,CONT_DIF_P,* +V 4700,3200,CONT_DIF_P,* +V 4700,3800,CONT_DIF_P,* +V 4700,4400,CONT_DIF_P,* +V 4700,1300,CONT_DIF_N,* +V 4700,600,CONT_DIF_N,* +V 3500,1300,CONT_DIF_N,* +V 3500,2700,CONT_DIF_P,* +V 3500,3200,CONT_DIF_P,* +V 4100,2700,CONT_DIF_P,* +V 4100,3200,CONT_DIF_P,* +V 3500,3800,CONT_DIF_P,* +V 4500,5000,CONT_BODY_N,* +V 4500,0,CONT_BODY_P,* +V 3500,4400,CONT_DIF_P,* +V 4100,3800,CONT_DIF_P,* +V 4100,4400,CONT_DIF_P,* +V 3500,600,CONT_DIF_N,* +V 4100,1300,CONT_DIF_N,* +V 4100,600,CONT_DIF_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,2100,CONT_POLY,* +V 900,3900,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 1500,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1000,2100,CONT_POLY,* +V 2000,2100,CONT_POLY,* +V 300,2100,CONT_POLY,* +V 2500,2100,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa2a22_x4.vbe b/pdks/symbolic/lsxlib/cells/oa2a22_x4.vbe new file mode 100644 index 000000000..a233499c0 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 519; + CONSTANT tpll_i2_q : NATURAL := 596; + CONSTANT tpll_i3_q : NATURAL := 619; + CONSTANT tphh_i1_q : NATURAL := 624; + CONSTANT tphh_i3_q : NATURAL := 644; + CONSTANT tpll_i1_q : NATURAL := 669; + CONSTANT tpll_i0_q : NATURAL := 696; + CONSTANT tphh_i2_q : NATURAL := 763; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa2a2a23_x2.ap b/pdks/symbolic/lsxlib/cells/oa2a2a23_x2.ap new file mode 100644 index 000000000..c2236eb75 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a2a23_x2.ap @@ -0,0 +1,146 @@ +V ALLIANCE : 6 +H oa2a2a23_x2,P, 1/ 8/2024,100 +A 0,0,5500,5000 +S 0,1100,5500,1100,1400,*,RIGHT,PWELL +S 400,2100,700,2100,100,*,RIGHT,POLY +S 1600,1100,4700,1100,200,*,RIGHT,ALU1 +S 4000,500,4000,900,300,*,DOWN,NDIF +S 2100,1600,2100,3400,200,i3,DOWN,CALU1 +S 4600,500,4600,1400,300,*,DOWN,NDIF +S 0,5000,5500,5000,400,vdd,RIGHT,CALU1 +S 0,5000,5500,5000,300,*,RIGHT,NTIE +S 0,4000,5500,4000,1200,*,RIGHT,NWELL +S 0,3100,5500,3100,1200,*,RIGHT,NWELL +S 0,0,5500,0,300,*,RIGHT,PTIE +S 0,0,5500,0,400,vss,RIGHT,CALU1 +S 4600,2700,4600,5000,200,*,UP,ALU1 +S 4100,2100,4300,2100,200,*,RIGHT,POLY +S 4100,1600,4100,3400,200,i4,DOWN,CALU1 +S 3600,1600,3600,3400,200,i5,DOWN,CALU1 +S 4600,2600,4600,4500,300,*,DOWN,PDIF +S 4900,1600,4900,2400,100,*,DOWN,POLY +S 4900,2400,4900,4700,100,*,DOWN,PTRANS +S 4900,300,4900,1600,100,*,UP,NTRANS +S 3700,1100,3700,3400,100,*,DOWN,POLY +S 4300,1100,4300,3400,100,*,DOWN,POLY +S 4700,2100,4900,2100,200,*,RIGHT,POLY +S 4700,1100,4700,2100,200,*,UP,ALU1 +S 5200,600,5200,4400,200,q,DOWN,CALU1 +S 5200,2600,5200,4500,300,*,DOWN,PDIF +S 5200,500,5200,1400,300,*,UP,NDIF +S 2500,1100,2500,3400,100,*,DOWN,POLY +S 1900,1100,1900,3400,100,*,DOWN,POLY +S 1300,1100,1300,3400,100,*,DOWN,POLY +S 700,1100,700,3400,100,*,DOWN,POLY +S 1600,3600,1600,4500,300,*,DOWN,PDIF +S 2800,3600,2800,4500,300,*,DOWN,PDIF +S 1900,3400,1900,4700,100,*,UP,PTRANS +S 2200,3600,2200,4500,300,*,DOWN,PDIF +S 2500,3400,2500,4700,100,*,UP,PTRANS +S 1300,3400,1300,4700,100,*,UP,PTRANS +S 1000,3600,1000,4500,300,*,DOWN,PDIF +S 3400,3600,3400,4500,300,*,DOWN,PDIF +S 4000,3600,4000,4500,300,*,DOWN,PDIF +S 4300,3400,4300,4700,100,*,UP,PTRANS +S 3700,3400,3700,4700,100,*,UP,PTRANS +S 700,3400,700,4700,100,*,UP,PTRANS +S 400,3600,400,4500,300,*,DOWN,PDIF +S 4300,300,4300,1100,100,*,DOWN,NTRANS +S 2500,300,2500,1100,100,*,DOWN,NTRANS +S 1900,300,1900,1100,100,*,DOWN,NTRANS +S 1300,300,1300,1100,100,*,DOWN,NTRANS +S 700,300,700,1100,100,*,DOWN,NTRANS +S 3700,300,3700,1100,100,*,DOWN,NTRANS +S 2800,500,2800,900,300,*,UP,NDIF +S 2200,500,2200,900,300,*,UP,NDIF +S 1600,500,1600,900,300,*,UP,NDIF +S 4600,500,4600,900,300,*,UP,NDIF +S 1000,500,1000,900,300,*,UP,NDIF +S 3400,500,3400,900,300,*,UP,NDIF +S 400,500,400,900,300,*,UP,NDIF +S 2700,1600,2700,3400,200,i2,DOWN,CALU1 +S 1600,600,1600,3400,200,*,DOWN,ALU1 +S 2500,2100,2700,2100,200,*,LEFT,POLY +S 1100,2100,1300,2100,200,*,RIGHT,POLY +S 1900,2100,2100,2100,200,*,RIGHT,POLY +S 4600,0,4600,600,200,*,DOWN,ALU1 +S 2800,0,2800,600,200,*,DOWN,ALU1 +S 400,0,400,600,200,*,DOWN,ALU1 +S 3400,4400,3400,5000,200,*,UP,ALU1 +S 4000,3900,4000,4400,200,*,DOWN,ALU1 +S 3400,600,3400,1100,200,*,UP,ALU1 +S 400,4400,2800,4400,200,*,RIGHT,ALU1 +S 2200,3900,4000,3900,200,*,LEFT,ALU1 +S 1600,3900,1600,4400,200,*,DOWN,ALU1 +S 400,3900,400,4400,200,*,DOWN,ALU1 +S 400,1100,400,3400,200,i0,DOWN,CALU1 +S 1100,600,1100,2900,200,i1,DOWN,CALU1 +S 1000,3400,1000,3900,200,*,DOWN,ALU1 +S 1000,3400,1600,3400,200,*,RIGHT,ALU1 +B 4750,2100,300,200,CONT_TURN8,* +B 4150,2100,300,200,CONT_TURN8,* +B 3600,2100,200,200,CONT_TURN8,* +B 2650,2100,300,200,CONT_TURN8,* +B 2050,2100,300,200,CONT_TURN8,* +B 1150,2100,300,200,CONT_TURN8,* +B 500,2100,400,200,CONT_TURN8,* +B 4700,1100,200,200,CONT_TURN1,* +B 1600,3400,200,200,CONT_TURN1,* +B 1000,3400,200,200,CONT_TURN1,* +V 4600,3300,CONT_DIF_P,* +V 4600,2700,CONT_DIF_P,* +V 3600,2100,CONT_POLY,* +V 4100,2100,CONT_POLY,* +V 5200,3900,CONT_DIF_P,* +V 5200,4400,CONT_DIF_P,* +V 5200,3300,CONT_DIF_P,* +V 5200,2700,CONT_DIF_P,* +V 5200,1300,CONT_DIF_N,* +V 5200,600,CONT_DIF_N,* +V 5500,5000,CONT_BODY_N,* +V 5500,0,CONT_BODY_P,* +V 4700,2100,CONT_POLY,* +V 3400,4400,CONT_DIF_P,* +V 4600,3900,CONT_DIF_P,* +V 2800,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 4000,3900,CONT_DIF_P,* +V 1000,3900,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 1600,3900,CONT_DIF_P,* +V 2200,3900,CONT_DIF_P,* +V 4600,4400,CONT_DIF_P,* +V 4000,4400,CONT_DIF_P,* +V 400,600,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 3400,600,CONT_DIF_N,* +V 4600,600,CONT_DIF_N,* +V 2800,600,CONT_DIF_N,* +V 2100,2100,CONT_POLY,* +V 400,2100,CONT_POLY,* +V 2700,2100,CONT_POLY,* +V 1100,2100,CONT_POLY,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa2a2a23_x2.vbe b/pdks/symbolic/lsxlib/cells/oa2a2a23_x2.vbe new file mode 100644 index 000000000..189ed7159 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a2a23_x2.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT tphh_i5_q : NATURAL := 321; + CONSTANT tphh_i4_q : NATURAL := 402; + CONSTANT tphh_i2_q : NATURAL := 441; + CONSTANT tphh_i3_q : NATURAL := 540; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT tpll_i4_q : NATURAL := 591; + CONSTANT tpll_i3_q : NATURAL := 600; + CONSTANT tpll_i5_q : NATURAL := 636; + CONSTANT tpll_i2_q : NATURAL := 639; + CONSTANT tphh_i0_q : NATURAL := 653; + CONSTANT tphh_i1_q : NATURAL := 775; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x2" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa2a2a23_x4.ap b/pdks/symbolic/lsxlib/cells/oa2a2a23_x4.ap new file mode 100644 index 000000000..f06600822 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a2a23_x4.ap @@ -0,0 +1,161 @@ +V ALLIANCE : 6 +H oa2a2a23_x4,P, 1/ 8/2024,100 +A 0,0,6000,5000 +S 0,1100,6000,1100,1400,*,RIGHT,PWELL +S 2400,1200,2400,3200,100,*,DOWN,POLY +S 1800,1200,1800,3200,100,*,DOWN,POLY +S 1200,1200,1200,3200,100,*,DOWN,POLY +S 600,1200,600,3200,100,*,DOWN,POLY +S 4200,1200,4200,3200,100,*,DOWN,POLY +S 3600,1200,3600,3200,100,*,DOWN,POLY +S 300,2100,600,2100,100,*,RIGHT,POLY +S 1500,1100,4600,1100,200,*,RIGHT,ALU1 +S 3900,500,3900,1000,300,*,DOWN,NDIF +S 0,5000,6000,5000,400,vdd,RIGHT,CALU1 +S 0,5000,6000,5000,300,*,RIGHT,NTIE +S 0,4000,6000,4000,1200,*,RIGHT,NWELL +S 0,3100,6000,3100,1200,*,RIGHT,NWELL +S 0,0,6000,0,300,*,RIGHT,PTIE +S 0,0,6000,0,400,vss,RIGHT,CALU1 +S 3300,3400,3300,4500,300,*,DOWN,PDIF +S 900,3400,900,4500,300,*,DOWN,PDIF +S 1200,3200,1200,4700,100,*,UP,PTRANS +S 2400,3200,2400,4700,100,*,UP,PTRANS +S 2100,3400,2100,4500,300,*,DOWN,PDIF +S 300,3400,300,4500,300,*,DOWN,PDIF +S 600,3200,600,4700,100,*,UP,PTRANS +S 4200,3200,4200,4700,100,*,UP,PTRANS +S 1800,3200,1800,4700,100,*,UP,PTRANS +S 2700,3400,2700,4500,300,*,DOWN,PDIF +S 1500,3400,1500,4500,300,*,DOWN,PDIF +S 3600,3200,3600,4700,100,*,UP,PTRANS +S 3900,3400,3900,4500,300,*,DOWN,PDIF +S 5400,2400,5400,4700,100,*,DOWN,PTRANS +S 5700,2600,5700,4500,300,*,DOWN,PDIF +S 4500,2600,4500,4500,300,*,DOWN,PDIF +S 4800,2400,4800,4700,100,*,DOWN,PTRANS +S 5100,2600,5100,4500,300,*,DOWN,PDIF +S 3600,300,3600,1200,100,*,DOWN,NTRANS +S 600,300,600,1200,100,*,DOWN,NTRANS +S 1200,300,1200,1200,100,*,DOWN,NTRANS +S 1800,300,1800,1200,100,*,DOWN,NTRANS +S 2400,300,2400,1200,100,*,DOWN,NTRANS +S 4200,300,4200,1200,100,*,DOWN,NTRANS +S 4800,300,4800,1600,100,*,UP,NTRANS +S 5400,300,5400,1600,100,*,UP,NTRANS +S 2700,500,2700,1000,300,*,UP,NDIF +S 300,500,300,1000,300,*,UP,NDIF +S 3300,500,3300,1000,300,*,UP,NDIF +S 900,500,900,1000,300,*,UP,NDIF +S 1500,500,1500,1000,300,*,UP,NDIF +S 2100,500,2100,1000,300,*,UP,NDIF +S 5700,500,5700,1400,300,*,UP,NDIF +S 4500,500,4500,900,300,*,UP,NDIF +S 4500,500,4500,1400,300,*,DOWN,NDIF +S 5100,500,5100,1400,300,*,UP,NDIF +S 5400,1600,5400,2400,100,*,DOWN,POLY +S 4600,2100,5400,2100,200,*,RIGHT,POLY +S 1000,2100,1200,2100,200,*,RIGHT,POLY +S 1800,2100,2000,2100,200,*,RIGHT,POLY +S 2400,2100,2600,2100,200,*,LEFT,POLY +S 4000,2100,4200,2100,200,*,RIGHT,POLY +S 4800,1600,4800,2400,100,*,DOWN,POLY +S 5700,0,5700,1300,200,*,DOWN,ALU1 +S 4500,0,4500,600,200,*,DOWN,ALU1 +S 2700,0,2700,600,200,*,DOWN,ALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +S 300,3900,300,4400,200,*,DOWN,ALU1 +S 3900,3900,3900,4400,200,*,DOWN,ALU1 +S 1500,3900,1500,4400,200,*,DOWN,ALU1 +S 5700,2700,5700,5000,200,*,UP,ALU1 +S 900,3400,1500,3400,200,*,RIGHT,ALU1 +S 3300,600,3300,1100,200,*,UP,ALU1 +S 300,4400,2700,4400,200,*,RIGHT,ALU1 +S 2100,3900,3900,3900,200,*,LEFT,ALU1 +S 300,1100,300,3400,200,i0,DOWN,CALU1 +S 1000,600,1000,2900,200,i1,DOWN,CALU1 +S 900,3400,900,3900,200,*,DOWN,ALU1 +S 5100,600,5100,4400,200,q,DOWN,CALU1 +S 2600,1600,2600,3400,200,i2,DOWN,CALU1 +S 1500,600,1500,3400,200,*,DOWN,ALU1 +S 3300,4400,3300,5000,200,*,UP,ALU1 +S 2000,1600,2000,3400,200,i3,DOWN,CALU1 +S 4500,2700,4500,5000,200,*,UP,ALU1 +S 4000,1600,4000,3400,200,i4,DOWN,CALU1 +S 3500,1600,3500,3400,200,i5,DOWN,CALU1 +S 4600,1100,4600,2100,200,*,UP,ALU1 +B 4950,2100,900,200,CONT_TURN8,* +B 4050,2100,300,200,CONT_TURN8,* +B 3500,2100,200,200,CONT_TURN8,* +B 2550,2100,300,200,CONT_TURN8,* +B 1950,2100,300,200,CONT_TURN8,* +B 1050,2100,300,200,CONT_TURN8,* +B 400,2100,400,200,CONT_TURN8,* +B 4600,1100,200,200,CONT_TURN1,* +B 1500,3400,200,200,CONT_TURN1,* +B 900,3400,200,200,CONT_TURN1,* +V 5100,600,CONT_DIF_N,* +V 5700,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 4500,600,CONT_DIF_N,* +V 3300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 5700,2700,CONT_DIF_P,* +V 5700,3300,CONT_DIF_P,* +V 5700,4400,CONT_DIF_P,* +V 5700,3900,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 4500,4400,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 4500,3900,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 3900,3900,CONT_DIF_P,* +V 900,3900,CONT_DIF_P,* +V 4500,3300,CONT_DIF_P,* +V 4500,2700,CONT_DIF_P,* +V 5100,3900,CONT_DIF_P,* +V 5100,4400,CONT_DIF_P,* +V 5100,3300,CONT_DIF_P,* +V 5100,2700,CONT_DIF_P,* +V 300,600,CONT_DIF_N,* +V 5700,1300,CONT_DIF_N,* +V 5100,1300,CONT_DIF_N,* +V 2600,2100,CONT_POLY,* +V 1000,2100,CONT_POLY,* +V 3500,2100,CONT_POLY,* +V 4000,2100,CONT_POLY,* +V 4600,2100,CONT_POLY,* +V 2000,2100,CONT_POLY,* +V 300,2100,CONT_POLY,* +V 6000,0,CONT_BODY_P,* +V 6000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5500,0,CONT_BODY_P,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa2a2a23_x4.vbe b/pdks/symbolic/lsxlib/cells/oa2a2a23_x4.vbe new file mode 100644 index 000000000..c39f56f93 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT tphh_i5_q : NATURAL := 379; + CONSTANT tphh_i4_q : NATURAL := 464; + CONSTANT tphh_i2_q : NATURAL := 493; + CONSTANT tphh_i3_q : NATURAL := 594; + CONSTANT tpll_i1_q : NATURAL := 613; + CONSTANT tpll_i0_q : NATURAL := 648; + CONSTANT tpll_i4_q : NATURAL := 673; + CONSTANT tpll_i3_q : NATURAL := 677; + CONSTANT tphh_i0_q : NATURAL := 699; + CONSTANT tpll_i5_q : NATURAL := 714; + CONSTANT tpll_i2_q : NATURAL := 715; + CONSTANT tphh_i1_q : NATURAL := 822; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x4" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x2.ap b/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x2.ap new file mode 100644 index 000000000..2d195ec0d --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x2.ap @@ -0,0 +1,182 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x2,P, 1/ 8/2024,100 +A 0,0,7500,5000 +S 0,1100,7500,1100,1400,*,RIGHT,PWELL +S 3400,2100,3700,2100,100,*,RIGHT,POLY +S 400,2100,700,2100,100,*,RIGHT,POLY +S 7000,600,7000,4400,200,q,DOWN,CALU1 +S 4300,300,4300,1200,100,*,DOWN,NTRANS +S 1900,300,1900,1200,100,*,DOWN,NTRANS +S 3700,300,3700,1200,100,*,DOWN,NTRANS +S 2500,300,2500,1200,100,*,DOWN,NTRANS +S 4900,300,4900,1200,100,*,DOWN,NTRANS +S 5500,300,5500,1200,100,*,DOWN,NTRANS +S 700,300,700,1200,100,*,DOWN,NTRANS +S 1300,300,1300,1200,100,*,DOWN,NTRANS +S 400,500,400,1000,300,*,UP,NDIF +S 1000,500,1000,1000,300,*,UP,NDIF +S 4000,500,4000,1000,300,*,UP,NDIF +S 4600,500,4600,1000,300,*,UP,NDIF +S 1600,500,1600,1000,300,*,UP,NDIF +S 3400,500,3400,1000,300,*,UP,NDIF +S 2800,500,2800,1000,300,*,UP,NDIF +S 2200,500,2200,1000,300,*,UP,NDIF +S 5200,500,5200,1000,300,*,UP,NDIF +S 5800,500,5800,1000,300,*,UP,NDIF +S 2500,1200,2500,2400,100,*,DOWN,POLY +S 3700,1200,3700,2400,100,*,DOWN,POLY +S 1300,1200,1300,2400,100,*,DOWN,POLY +S 1900,1200,1900,2400,100,*,DOWN,POLY +S 4300,1200,4300,2400,100,*,DOWN,POLY +S 4900,1200,4900,2400,100,*,DOWN,POLY +S 5500,1200,5500,2400,100,*,DOWN,POLY +S 700,1200,700,2400,100,*,DOWN,POLY +S 0,5000,7500,5000,300,*,RIGHT,NTIE +S 0,5000,7500,5000,400,vdd,RIGHT,CALU1 +S 0,0,7500,0,300,*,RIGHT,PTIE +S 0,0,7500,0,400,vss,RIGHT,CALU1 +S 0,4000,7500,4000,1200,*,RIGHT,NWELL +S 0,3100,7500,3100,1200,*,RIGHT,NWELL +S 5900,2100,6700,2100,200,*,RIGHT,POLY +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 1300,2400,1300,4700,100,*,UP,PTRANS +S 2500,2400,2500,4700,100,*,UP,PTRANS +S 5500,2400,5500,4700,100,*,UP,PTRANS +S 5200,2600,5200,4500,300,*,DOWN,PDIF +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 400,2600,400,4500,300,*,DOWN,PDIF +S 700,2400,700,4700,100,*,UP,PTRANS +S 4900,2400,4900,4700,100,*,UP,PTRANS +S 5800,2600,5800,4500,300,*,DOWN,PDIF +S 4600,2600,4600,4500,300,*,DOWN,PDIF +S 3400,2600,3400,4500,300,*,DOWN,PDIF +S 3700,2400,3700,4700,100,*,UP,PTRANS +S 2200,2600,2200,4500,300,*,DOWN,PDIF +S 1900,2400,1900,4700,100,*,UP,PTRANS +S 2800,2600,2800,4500,300,*,DOWN,PDIF +S 4000,2600,4000,4500,300,*,DOWN,PDIF +S 4300,2400,4300,4700,100,*,UP,PTRANS +S 6700,2400,6700,4700,100,*,UP,PTRANS +S 6400,2600,6400,4500,300,*,DOWN,PDIF +S 7000,2600,7000,4500,300,*,DOWN,PDIF +S 6700,300,6700,1600,100,*,DOWN,NTRANS +S 7000,500,7000,1400,300,*,UP,NDIF +S 6400,500,6400,1400,300,*,UP,NDIF +S 6700,1600,6700,2400,100,*,DOWN,POLY +S 1100,2100,1300,2100,200,*,RIGHT,POLY +S 1900,2100,2100,2100,200,*,RIGHT,POLY +S 4700,2100,4900,2100,200,*,RIGHT,POLY +S 4100,2100,4300,2100,200,*,RIGHT,POLY +S 5300,2100,5500,2100,200,*,LEFT,POLY +S 6400,0,6400,1300,200,*,DOWN,ALU1 +S 5800,0,5800,600,200,*,DOWN,ALU1 +S 3400,0,3400,600,200,*,DOWN,ALU1 +S 2800,0,2800,600,200,*,DOWN,ALU1 +S 400,0,400,600,200,*,DOWN,ALU1 +S 6400,2700,6400,5000,200,*,UP,ALU1 +S 400,1100,400,3400,200,i0,DOWN,CALU1 +S 3400,3900,4600,3900,200,*,RIGHT,ALU1 +S 2200,4400,4000,4400,200,*,RIGHT,ALU1 +S 400,3900,2800,3900,200,*,RIGHT,ALU1 +S 400,3900,400,4400,200,*,DOWN,ALU1 +S 1000,4400,1000,5000,200,*,UP,ALU1 +S 3400,1600,3400,3400,200,i4,DOWN,CALU1 +S 4600,600,4600,1100,200,*,DOWN,ALU1 +S 2100,1600,2100,3400,200,i3,DOWN,CALU1 +S 1100,600,1100,3400,200,i1,DOWN,CALU1 +S 2600,1600,2600,3400,200,i2,DOWN,CALU1 +S 1600,3900,1600,4400,200,*,DOWN,ALU1 +S 4600,4400,5800,4400,200,*,RIGHT,ALU1 +S 4600,3900,4600,4400,200,*,UP,ALU1 +S 4100,1600,4100,3400,200,i5,DOWN,CALU1 +S 4700,1600,4700,3400,200,i6,DOWN,CALU1 +S 1600,600,1600,1100,200,*,DOWN,ALU1 +S 5200,3900,5900,3900,200,*,RIGHT,ALU1 +S 1600,1100,5900,1100,200,*,LEFT,ALU1 +S 5900,1100,5900,3900,200,*,DOWN,ALU1 +S 5300,1600,5300,3400,200,i7,DOWN,CALU1 +B 6250,2100,900,200,CONT_TURN8,* +B 5350,2100,300,200,CONT_TURN8,* +B 4750,2100,300,200,CONT_TURN8,* +B 4150,2100,300,200,CONT_TURN8,* +B 2600,2100,200,200,CONT_TURN8,* +B 2050,2100,300,200,CONT_TURN8,* +B 1150,2100,300,200,CONT_TURN8,* +B 3500,2100,400,200,CONT_TURN8,* +B 500,2100,400,200,CONT_TURN8,* +B 1600,1100,200,200,CONT_TURN1,* +B 5900,1100,200,200,CONT_TURN1,* +B 5900,3900,200,200,CONT_TURN1,* +V 6400,3900,CONT_DIF_P,* +V 6400,3300,CONT_DIF_P,* +V 6400,4400,CONT_DIF_P,* +V 7000,2700,CONT_DIF_P,* +V 7000,3300,CONT_DIF_P,* +V 7000,4400,CONT_DIF_P,* +V 7000,3900,CONT_DIF_P,* +V 6400,2700,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 4600,3900,CONT_DIF_P,* +V 3400,3900,CONT_DIF_P,* +V 4000,4400,CONT_DIF_P,* +V 2200,4400,CONT_DIF_P,* +V 2800,3900,CONT_DIF_P,* +V 1600,3900,CONT_DIF_P,* +V 5800,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 4600,4400,CONT_DIF_P,* +V 5200,3900,CONT_DIF_P,* +V 7000,600,CONT_DIF_N,* +V 6400,600,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 6400,1300,CONT_DIF_N,* +V 7000,1300,CONT_DIF_N,* +V 4600,600,CONT_DIF_N,* +V 3400,600,CONT_DIF_N,* +V 5800,600,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 2800,600,CONT_DIF_N,* +V 5900,2100,CONT_POLY,* +V 1100,2100,CONT_POLY,* +V 2100,2100,CONT_POLY,* +V 400,2100,CONT_POLY,* +V 2600,2100,CONT_POLY,* +V 5300,2100,CONT_POLY,* +V 4700,2100,CONT_POLY,* +V 3400,2100,CONT_POLY,* +V 4100,2100,CONT_POLY,* +V 6500,5000,CONT_BODY_N,* +V 7000,5000,CONT_BODY_N,* +V 7500,5000,CONT_BODY_N,* +V 6500,0,CONT_BODY_P,* +V 7000,0,CONT_BODY_P,* +V 7500,0,CONT_BODY_P,* +V 5000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x2.vbe b/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x2.vbe new file mode 100644 index 000000000..39a24492c --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x2.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rdown_i7_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT rup_i7_q : NATURAL := 1790; + CONSTANT tphh_i7_q : NATURAL := 346; + CONSTANT tphh_i6_q : NATURAL := 426; + CONSTANT tphh_i5_q : NATURAL := 467; + CONSTANT tphh_i4_q : NATURAL := 565; + CONSTANT tphh_i2_q : NATURAL := 682; + CONSTANT tpll_i6_q : NATURAL := 748; + CONSTANT tpll_i1_q : NATURAL := 753; + CONSTANT tphh_i0_q : NATURAL := 780; + CONSTANT tpll_i0_q : NATURAL := 797; + CONSTANT tpll_i7_q : NATURAL := 800; + CONSTANT tphh_i3_q : NATURAL := 803; + CONSTANT tpll_i3_q : NATURAL := 810; + CONSTANT tpll_i4_q : NATURAL := 813; + CONSTANT tpll_i2_q : NATURAL := 856; + CONSTANT tpll_i5_q : NATURAL := 861; + CONSTANT tphh_i1_q : NATURAL := 909; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x2" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1500 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x4.ap b/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x4.ap new file mode 100644 index 000000000..6fdbe5b13 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x4.ap @@ -0,0 +1,197 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x4,P, 1/ 8/2024,100 +A 0,0,8000,5000 +S 0,1100,8000,1100,1400,*,RIGHT,PWELL +S 3400,2100,3700,2100,100,*,RIGHT,POLY +S 400,2100,700,2100,100,*,RIGHT,POLY +S 7000,600,7000,4400,200,q,DOWN,CALU1 +S 4900,300,4900,1300,100,*,DOWN,NTRANS +S 5500,300,5500,1300,100,*,DOWN,NTRANS +S 700,300,700,1300,100,*,DOWN,NTRANS +S 1300,300,1300,1300,100,*,DOWN,NTRANS +S 1900,300,1900,1300,100,*,DOWN,NTRANS +S 2500,300,2500,1300,100,*,DOWN,NTRANS +S 3700,300,3700,1300,100,*,DOWN,NTRANS +S 4300,300,4300,1300,100,*,DOWN,NTRANS +S 5800,500,5800,1100,300,*,UP,NDIF +S 3400,500,3400,1100,300,*,UP,NDIF +S 1600,500,1600,1100,300,*,UP,NDIF +S 2200,500,2200,1100,300,*,UP,NDIF +S 2800,500,2800,1100,300,*,UP,NDIF +S 400,500,400,1100,300,*,UP,NDIF +S 1000,500,1000,1100,300,*,UP,NDIF +S 4000,500,4000,1100,300,*,UP,NDIF +S 4600,500,4600,1100,300,*,UP,NDIF +S 5200,500,5200,1100,300,*,UP,NDIF +S 1300,1300,1300,2400,100,*,DOWN,POLY +S 1900,1300,1900,2400,100,*,DOWN,POLY +S 2500,1300,2500,2400,100,*,DOWN,POLY +S 3700,1300,3700,2400,100,*,DOWN,POLY +S 4300,1300,4300,2400,100,*,DOWN,POLY +S 4900,1300,4900,2400,100,*,DOWN,POLY +S 5500,1300,5500,2400,100,*,DOWN,POLY +S 700,1300,700,2400,100,*,DOWN,POLY +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 1300,2400,1300,4700,100,*,UP,PTRANS +S 2500,2400,2500,4700,100,*,UP,PTRANS +S 5500,2400,5500,4700,100,*,UP,PTRANS +S 5200,2600,5200,4500,300,*,DOWN,PDIF +S 1600,2600,1600,4500,300,*,DOWN,PDIF +S 400,2600,400,4500,300,*,DOWN,PDIF +S 700,2400,700,4700,100,*,UP,PTRANS +S 4900,2400,4900,4700,100,*,UP,PTRANS +S 5800,2600,5800,4500,300,*,DOWN,PDIF +S 4600,2600,4600,4500,300,*,DOWN,PDIF +S 3400,2600,3400,4500,300,*,DOWN,PDIF +S 3700,2400,3700,4700,100,*,UP,PTRANS +S 2200,2600,2200,4500,300,*,DOWN,PDIF +S 1900,2400,1900,4700,100,*,UP,PTRANS +S 2800,2600,2800,4500,300,*,DOWN,PDIF +S 4000,2600,4000,4500,300,*,DOWN,PDIF +S 4300,2400,4300,4700,100,*,UP,PTRANS +S 7600,2600,7600,4500,300,*,DOWN,PDIF +S 7300,2400,7300,4700,100,*,UP,PTRANS +S 6700,2400,6700,4700,100,*,UP,PTRANS +S 6400,2600,6400,4500,300,*,DOWN,PDIF +S 7000,2600,7000,4500,300,*,DOWN,PDIF +S 6700,300,6700,1600,100,*,DOWN,NTRANS +S 7300,300,7300,1600,100,*,DOWN,NTRANS +S 7000,500,7000,1400,300,*,UP,NDIF +S 6400,500,6400,1400,300,*,UP,NDIF +S 7600,500,7600,1400,300,*,UP,NDIF +S 5900,2100,7300,2100,200,*,RIGHT,POLY +S 6700,1600,6700,2400,100,*,DOWN,POLY +S 7300,1600,7300,2400,100,*,DOWN,POLY +S 1100,2100,1300,2100,200,*,RIGHT,POLY +S 1900,2100,2100,2100,200,*,RIGHT,POLY +S 4700,2100,4900,2100,200,*,RIGHT,POLY +S 4100,2100,4300,2100,200,*,RIGHT,POLY +S 5300,2100,5500,2100,200,*,LEFT,POLY +S 7600,0,7600,1300,200,*,DOWN,ALU1 +S 6400,0,6400,1300,200,*,DOWN,ALU1 +S 5800,0,5800,600,200,*,DOWN,ALU1 +S 3400,0,3400,600,200,*,DOWN,ALU1 +S 2800,0,2800,600,200,*,DOWN,ALU1 +S 400,0,400,600,200,*,DOWN,ALU1 +S 7600,2700,7600,5000,200,*,UP,ALU1 +S 6400,2700,6400,5000,200,*,UP,ALU1 +S 400,1100,400,3400,200,i0,DOWN,CALU1 +S 3400,3900,4600,3900,200,*,RIGHT,ALU1 +S 2200,4400,4000,4400,200,*,RIGHT,ALU1 +S 400,3900,2800,3900,200,*,RIGHT,ALU1 +S 400,3900,400,4400,200,*,DOWN,ALU1 +S 1000,4400,1000,5000,200,*,UP,ALU1 +S 3400,1600,3400,3400,200,i4,DOWN,CALU1 +S 4600,600,4600,1100,200,*,DOWN,ALU1 +S 2100,1600,2100,3400,200,i3,DOWN,CALU1 +S 1100,600,1100,3400,200,i1,DOWN,CALU1 +S 2600,1600,2600,3400,200,i2,DOWN,CALU1 +S 1600,3900,1600,4400,200,*,DOWN,ALU1 +S 4600,4400,5800,4400,200,*,RIGHT,ALU1 +S 4600,3900,4600,4400,200,*,UP,ALU1 +S 4100,1600,4100,3400,200,i5,DOWN,CALU1 +S 4700,1600,4700,3400,200,i6,DOWN,CALU1 +S 1600,600,1600,1100,200,*,DOWN,ALU1 +S 5200,3900,5900,3900,200,*,RIGHT,ALU1 +S 1600,1100,5900,1100,200,*,LEFT,ALU1 +S 5900,1100,5900,3900,200,*,DOWN,ALU1 +S 5300,1600,5300,3400,200,i7,DOWN,CALU1 +S 0,5000,8000,5000,300,*,RIGHT,NTIE +S 0,0,8000,0,300,*,RIGHT,PTIE +S 0,5000,8000,5000,400,vdd,RIGHT,CALU1 +S 0,4000,8000,4000,1200,*,RIGHT,NWELL +S 0,3100,8000,3100,1200,*,RIGHT,NWELL +S 0,0,8000,0,400,vss,RIGHT,CALU1 +B 6550,2100,1500,200,CONT_TURN8,* +B 5350,2100,300,200,CONT_TURN8,* +B 4750,2100,300,200,CONT_TURN8,* +B 4150,2100,300,200,CONT_TURN8,* +B 2600,2100,200,200,CONT_TURN8,* +B 2050,2100,300,200,CONT_TURN8,* +B 1150,2100,300,200,CONT_TURN8,* +B 3500,2100,400,200,CONT_TURN8,* +B 500,2100,400,200,CONT_TURN8,* +B 5900,1100,200,200,CONT_TURN1,* +B 5900,3900,200,200,CONT_TURN1,* +B 1600,1100,200,200,CONT_TURN1,* +V 6400,3900,CONT_DIF_P,* +V 6400,3300,CONT_DIF_P,* +V 6400,4400,CONT_DIF_P,* +V 7600,2700,CONT_DIF_P,* +V 7600,3900,CONT_DIF_P,* +V 7000,2700,CONT_DIF_P,* +V 7000,3300,CONT_DIF_P,* +V 7000,4400,CONT_DIF_P,* +V 7000,3900,CONT_DIF_P,* +V 7600,4400,CONT_DIF_P,* +V 7600,3300,CONT_DIF_P,* +V 6400,2700,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 4600,3900,CONT_DIF_P,* +V 3400,3900,CONT_DIF_P,* +V 4000,4400,CONT_DIF_P,* +V 2200,4400,CONT_DIF_P,* +V 2800,3900,CONT_DIF_P,* +V 1600,3900,CONT_DIF_P,* +V 5800,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 4600,4400,CONT_DIF_P,* +V 5200,3900,CONT_DIF_P,* +V 7000,600,CONT_DIF_N,* +V 6400,600,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 7600,1300,CONT_DIF_N,* +V 7600,600,CONT_DIF_N,* +V 6400,1300,CONT_DIF_N,* +V 7000,1300,CONT_DIF_N,* +V 4600,600,CONT_DIF_N,* +V 3400,600,CONT_DIF_N,* +V 5800,600,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 2800,600,CONT_DIF_N,* +V 5900,2100,CONT_POLY,* +V 1100,2100,CONT_POLY,* +V 2100,2100,CONT_POLY,* +V 400,2100,CONT_POLY,* +V 2600,2100,CONT_POLY,* +V 5300,2100,CONT_POLY,* +V 4700,2100,CONT_POLY,* +V 3400,2100,CONT_POLY,* +V 4100,2100,CONT_POLY,* +V 6500,5000,CONT_BODY_N,* +V 7000,5000,CONT_BODY_N,* +V 7500,5000,CONT_BODY_N,* +V 8000,5000,CONT_BODY_N,* +V 6500,0,CONT_BODY_P,* +V 7000,0,CONT_BODY_P,* +V 7500,0,CONT_BODY_P,* +V 8000,0,CONT_BODY_P,* +V 5000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x4.vbe b/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x4.vbe new file mode 100644 index 000000000..33d168440 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2a2a2a24_x4.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rdown_i7_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT rup_i7_q : NATURAL := 890; + CONSTANT tphh_i7_q : NATURAL := 399; + CONSTANT tphh_i6_q : NATURAL := 487; + CONSTANT tphh_i5_q : NATURAL := 515; + CONSTANT tphh_i4_q : NATURAL := 619; + CONSTANT tphh_i2_q : NATURAL := 726; + CONSTANT tphh_i0_q : NATURAL := 823; + CONSTANT tpll_i1_q : NATURAL := 835; + CONSTANT tpll_i6_q : NATURAL := 845; + CONSTANT tphh_i3_q : NATURAL := 851; + CONSTANT tpll_i0_q : NATURAL := 879; + CONSTANT tpll_i3_q : NATURAL := 895; + CONSTANT tpll_i7_q : NATURAL := 895; + CONSTANT tpll_i4_q : NATURAL := 902; + CONSTANT tpll_i2_q : NATURAL := 940; + CONSTANT tpll_i5_q : NATURAL := 949; + CONSTANT tphh_i1_q : NATURAL := 955; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x4" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1600 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa2ao222_x2.ap b/pdks/symbolic/lsxlib/cells/oa2ao222_x2.ap new file mode 100644 index 000000000..026d33df6 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2ao222_x2.ap @@ -0,0 +1,144 @@ +V ALLIANCE : 6 +H oa2ao222_x2,P, 5/ 8/2024,100 +A 0,0,5000,5000 +S 3400,1600,3400,1700,200,*,UP,POLY2 +S 3400,1700,4200,1700,100,*,LEFT,POLY +S 0,1100,5000,1100,1400,*,RIGHT,PWELL +S 600,1100,600,3400,200,i0,DOWN,CALU1 +S 1600,2100,1600,3400,200,i4,DOWN,CALU1 +S 1100,1100,1100,3400,200,i1,DOWN,CALU1 +S 1600,3600,1600,4500,300,*,DOWN,PDIF +S 1000,3600,1000,4500,300,*,DOWN,PDIF +S 3200,2100,3200,3900,200,i3,DOWN,CALU1 +S 2700,2100,2700,3900,200,i2,DOWN,CALU1 +S 4500,600,4500,4400,200,q,DOWN,CALU1 +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,0,5000,0,300,*,RIGHT,PTIE +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 3000,2200,3200,2200,200,*,LEFT,POLY +S 2500,2200,2600,2200,200,*,LEFT,POLY +S 1100,2200,1200,2200,200,*,RIGHT,POLY +S 600,2200,700,2200,200,*,RIGHT,POLY +S 1600,2200,1800,2200,200,*,RIGHT,POLY +S 2600,2200,2700,2200,200,*,LEFT,ALU1 +S 3900,2600,3900,4500,300,*,DOWN,PDIF +S 4200,2400,4200,4700,100,*,UP,PTRANS +S 4500,2600,4500,4500,300,*,DOWN,PDIF +S 2200,2600,2200,4500,300,*,UP,PDIF +S 2800,2600,2800,4500,200,*,UP,PDIF +S 2500,2400,2500,4700,100,*,UP,PTRANS +S 3300,2600,3300,4500,300,*,UP,PDIF +S 3000,2400,3000,4700,100,*,UP,PTRANS +S 400,3600,400,4500,300,*,UP,PDIF +S 700,3400,700,4700,100,*,UP,PTRANS +S 1300,3400,1300,4700,100,*,DOWN,PTRANS +S 1900,3400,1900,4700,100,*,UP,PTRANS +S 4200,300,4200,1600,100,*,DOWN,NTRANS +S 3000,300,3000,1100,100,*,UP,NTRANS +S 700,300,700,1100,100,*,UP,NTRANS +S 2400,300,2400,1100,100,*,UP,NTRANS +S 1800,300,1800,1100,100,*,UP,NTRANS +S 1200,300,1200,1100,100,*,UP,NTRANS +S 3900,500,3900,1400,300,*,UP,NDIF +S 4500,500,4500,1400,300,*,UP,NDIF +S 400,500,400,900,300,*,UP,NDIF +S 2700,500,2700,900,300,*,UP,NDIF +S 2100,500,2100,900,200,*,UP,NDIF +S 1500,500,1500,900,200,*,UP,NDIF +S 3300,500,3300,900,300,*,UP,NDIF +S 4200,1600,4200,2400,100,*,UP,POLY +S 700,1100,700,3400,100,*,UP,POLY +S 2400,1100,2500,1100,100,*,RIGHT,POLY +S 3000,1100,3000,2400,100,*,UP,POLY +S 2500,1100,2500,2400,100,*,UP,POLY +S 1800,3400,1900,3400,100,*,RIGHT,POLY +S 1200,3400,1300,3400,100,*,RIGHT,POLY +S 1800,1100,1800,3400,100,*,UP,POLY +S 1200,1100,1200,3400,100,*,UP,POLY +S 3900,0,3900,1300,200,*,DOWN,ALU1 +S 400,0,400,600,200,*,UP,ALU1 +S 2700,0,2700,600,200,*,UP,ALU1 +S 1600,1600,3400,1600,200,*,LEFT,ALU1 +S 3900,2700,3900,5000,200,*,UP,ALU1 +S 2100,3900,2200,3900,200,*,LEFT,ALU1 +S 1000,4400,1000,5000,200,*,UP,ALU1 +S 2100,1100,3300,1100,200,*,RIGHT,ALU1 +S 1600,600,1600,1600,200,*,DOWN,ALU1 +S 2100,1600,2100,3900,200,*,DOWN,ALU1 +S 1600,4400,3300,4400,200,*,RIGHT,ALU1 +S 2100,3300,2200,3300,200,*,LEFT,ALU1 +S 1500,600,1600,600,200,*,LEFT,ALU1 +S 2100,2700,2200,2700,200,*,LEFT,ALU1 +S 3300,600,3300,1100,200,*,DOWN,ALU1 +S 2100,600,2100,1100,200,*,UP,ALU1 +S 1600,3900,1600,4400,200,*,UP,ALU1 +S 400,3900,400,4400,200,*,DOWN,ALU1 +S 400,3900,1600,3900,200,*,RIGHT,ALU1 +B 3150,2200,300,200,CONT_TURN8,* +B 2600,2200,200,200,CONT_TURN8,* +B 1650,2200,300,200,CONT_TURN8,* +B 1100,2200,200,200,CONT_TURN8,* +B 600,2200,200,200,CONT_TURN8,* +B 1600,600,200,200,CONT_TURN1,* +B 3300,1100,200,200,CONT_TURN1,* +B 2100,1100,200,200,CONT_TURN1,* +B 1600,1600,200,200,CONT_TURN1,* +B 2100,3900,200,200,CONT_TURN1,* +V 2600,2200,CONT_POLY,* +V 3200,2200,CONT_POLY,* +V 1600,2200,CONT_POLY,* +V 1100,2200,CONT_POLY,* +V 600,2200,CONT_POLY,* +V 4500,2700,CONT_DIF_P,* +V 4500,3200,CONT_DIF_P,* +V 4500,3800,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 3900,3800,CONT_DIF_P,* +V 3900,2700,CONT_DIF_P,* +V 3900,3200,CONT_DIF_P,* +V 4500,4400,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 2200,3900,CONT_DIF_P,* +V 2200,2700,CONT_DIF_P,* +V 2200,3300,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 1600,3900,CONT_DIF_P,* +V 3900,1300,CONT_DIF_N,* +V 4500,600,CONT_DIF_N,* +V 4500,1300,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 3900,600,CONT_DIF_N,* +V 3300,600,CONT_DIF_N,* +V 3400,1600,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa2ao222_x2.vbe b/pdks/symbolic/lsxlib/cells/oa2ao222_x2.vbe new file mode 100644 index 000000000..2a96b29e2 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2ao222_x2.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT tpll_i4_q : NATURAL := 453; + CONSTANT tphh_i2_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 495; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphh_i3_q : NATURAL := 556; + CONSTANT tphh_i4_q : NATURAL := 558; + CONSTANT tpll_i3_q : NATURAL := 578; + CONSTANT tpll_i0_q : NATURAL := 581; + CONSTANT tphh_i1_q : NATURAL := 598; + CONSTANT tpll_i2_q : NATURAL := 604; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x2; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1200 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa2ao222_x4.ap b/pdks/symbolic/lsxlib/cells/oa2ao222_x4.ap new file mode 100644 index 000000000..50f87afb0 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2ao222_x4.ap @@ -0,0 +1,159 @@ +V ALLIANCE : 6 +H oa2ao222_x4,P, 5/ 8/2024,100 +A 0,0,5500,5000 +S 3400,1600,3400,1700,200,*,UP,POLY2 +S 3400,1700,4800,1700,100,*,LEFT,POLY +S 0,1100,5500,1100,1400,*,RIGHT,PWELL +S 600,1100,600,3400,200,i0,DOWN,CALU1 +S 3200,2100,3200,3900,200,i3,DOWN,CALU1 +S 2700,2100,2700,3900,200,i2,DOWN,CALU1 +S 1600,2100,1600,3400,200,i4,DOWN,CALU1 +S 1100,1100,1100,3400,200,i1,DOWN,CALU1 +S 1600,3600,1600,4500,300,*,DOWN,PDIF +S 1000,3600,1000,4500,300,*,DOWN,PDIF +S 4500,600,4500,4400,200,q,DOWN,CALU1 +S 3000,2200,3200,2200,200,*,LEFT,POLY +S 2500,2200,2600,2200,200,*,LEFT,POLY +S 1100,2200,1200,2200,200,*,RIGHT,POLY +S 600,2200,700,2200,200,*,RIGHT,POLY +S 1600,2200,1800,2200,200,*,RIGHT,POLY +S 2600,2200,2700,2200,200,*,LEFT,ALU1 +S 5100,2600,5100,4500,300,*,DOWN,PDIF +S 3900,2600,3900,4500,300,*,DOWN,PDIF +S 4200,2400,4200,4700,100,*,UP,PTRANS +S 4500,2600,4500,4500,300,*,DOWN,PDIF +S 4800,2400,4800,4700,100,*,UP,PTRANS +S 2200,2600,2200,4500,300,*,UP,PDIF +S 2800,2600,2800,4500,200,*,UP,PDIF +S 2500,2400,2500,4700,100,*,UP,PTRANS +S 3300,2600,3300,4500,300,*,UP,PDIF +S 3000,2400,3000,4700,100,*,UP,PTRANS +S 400,3600,400,4500,300,*,UP,PDIF +S 700,3400,700,4700,100,*,UP,PTRANS +S 1300,3400,1300,4700,100,*,DOWN,PTRANS +S 1900,3400,1900,4700,100,*,UP,PTRANS +S 4800,300,4800,1600,100,*,DOWN,NTRANS +S 4200,300,4200,1600,100,*,DOWN,NTRANS +S 3000,300,3000,1100,100,*,UP,NTRANS +S 700,300,700,1100,100,*,UP,NTRANS +S 2400,300,2400,1100,100,*,UP,NTRANS +S 1800,300,1800,1100,100,*,UP,NTRANS +S 1200,300,1200,1100,100,*,UP,NTRANS +S 5100,500,5100,1400,300,*,UP,NDIF +S 3900,500,3900,1400,300,*,UP,NDIF +S 4500,500,4500,1400,300,*,UP,NDIF +S 400,500,400,900,300,*,UP,NDIF +S 2700,500,2700,900,300,*,UP,NDIF +S 2100,500,2100,900,200,*,UP,NDIF +S 1500,500,1500,900,200,*,UP,NDIF +S 3300,500,3300,900,300,*,UP,NDIF +S 4200,1600,4200,2400,100,*,UP,POLY +S 4800,1600,4800,2400,100,*,UP,POLY +S 700,1100,700,3400,100,*,UP,POLY +S 2400,1100,2500,1100,100,*,RIGHT,POLY +S 3000,1100,3000,2400,100,*,UP,POLY +S 2500,1100,2500,2400,100,*,UP,POLY +S 1800,3400,1900,3400,100,*,RIGHT,POLY +S 1200,3400,1300,3400,100,*,RIGHT,POLY +S 1800,1100,1800,3400,100,*,UP,POLY +S 1200,1100,1200,3400,100,*,UP,POLY +S 5100,0,5100,1300,200,*,DOWN,ALU1 +S 3900,0,3900,1300,200,*,DOWN,ALU1 +S 400,0,400,600,200,*,UP,ALU1 +S 2700,0,2700,600,200,*,UP,ALU1 +S 1600,1600,3400,1600,200,*,LEFT,ALU1 +S 5100,2700,5100,5000,200,*,UP,ALU1 +S 3900,2700,3900,5000,200,*,UP,ALU1 +S 2100,3900,2200,3900,200,*,LEFT,ALU1 +S 1000,4400,1000,5000,200,*,UP,ALU1 +S 2100,1100,3300,1100,200,*,RIGHT,ALU1 +S 1600,600,1600,1600,200,*,DOWN,ALU1 +S 2100,1600,2100,3900,200,*,DOWN,ALU1 +S 1600,4400,3300,4400,200,*,RIGHT,ALU1 +S 2100,3300,2200,3300,200,*,LEFT,ALU1 +S 1500,600,1600,600,200,*,LEFT,ALU1 +S 2100,2700,2200,2700,200,*,LEFT,ALU1 +S 3300,600,3300,1100,200,*,DOWN,ALU1 +S 2100,600,2100,1100,200,*,UP,ALU1 +S 1600,3900,1600,4400,200,*,UP,ALU1 +S 400,3900,400,4400,200,*,DOWN,ALU1 +S 400,3900,1600,3900,200,*,RIGHT,ALU1 +S 0,0,5500,0,300,*,RIGHT,PTIE +S 0,0,5500,0,400,vss,RIGHT,CALU1 +S 0,4000,5500,4000,1200,*,RIGHT,NWELL +S 0,3100,5500,3100,1200,*,RIGHT,NWELL +S 0,5000,5500,5000,300,*,RIGHT,NTIE +S 0,5000,5500,5000,400,vdd,RIGHT,CALU1 +B 3150,2200,300,200,CONT_TURN8,* +B 2600,2200,200,200,CONT_TURN8,* +B 1650,2200,300,200,CONT_TURN8,* +B 1100,2200,200,200,CONT_TURN8,* +B 600,2200,200,200,CONT_TURN8,* +B 1600,600,200,200,CONT_TURN1,* +B 3300,1100,200,200,CONT_TURN1,* +B 2100,1100,200,200,CONT_TURN1,* +B 1600,1600,200,200,CONT_TURN1,* +B 2100,3900,200,200,CONT_TURN1,* +V 2600,2200,CONT_POLY,* +V 3200,2200,CONT_POLY,* +V 1600,2200,CONT_POLY,* +V 1100,2200,CONT_POLY,* +V 600,2200,CONT_POLY,* +V 4500,2700,CONT_DIF_P,* +V 4500,3200,CONT_DIF_P,* +V 5100,3200,CONT_DIF_P,* +V 5100,2700,CONT_DIF_P,* +V 5100,4400,CONT_DIF_P,* +V 4500,3800,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 3900,3800,CONT_DIF_P,* +V 5100,3800,CONT_DIF_P,* +V 3900,2700,CONT_DIF_P,* +V 3900,3200,CONT_DIF_P,* +V 4500,4400,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 2200,3900,CONT_DIF_P,* +V 2200,2700,CONT_DIF_P,* +V 2200,3300,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 400,3900,CONT_DIF_P,* +V 1600,3900,CONT_DIF_P,* +V 3900,1300,CONT_DIF_N,* +V 4500,600,CONT_DIF_N,* +V 4500,1300,CONT_DIF_N,* +V 5100,1300,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 3900,600,CONT_DIF_N,* +V 5100,600,CONT_DIF_N,* +V 3300,600,CONT_DIF_N,* +V 3400,1600,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa2ao222_x4.vbe b/pdks/symbolic/lsxlib/cells/oa2ao222_x4.vbe new file mode 100644 index 000000000..d8e7b2abf --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT tpll_i4_q : NATURAL := 529; + CONSTANT tphh_i2_q : NATURAL := 552; + CONSTANT tphh_i0_q : NATURAL := 553; + CONSTANT tpll_i1_q : NATURAL := 616; + CONSTANT tphh_i3_q : NATURAL := 640; + CONSTANT tphh_i4_q : NATURAL := 656; + CONSTANT tpll_i0_q : NATURAL := 657; + CONSTANT tpll_i3_q : NATURAL := 660; + CONSTANT tphh_i1_q : NATURAL := 662; + CONSTANT tpll_i2_q : NATURAL := 693; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa3ao322_x2.ap b/pdks/symbolic/lsxlib/cells/oa3ao322_x2.ap new file mode 100644 index 000000000..c86715801 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa3ao322_x2.ap @@ -0,0 +1,159 @@ +V ALLIANCE : 6 +H oa3ao322_x2,P, 1/ 8/2024,100 +A 0,0,5500,5000 +S 0,1100,5500,1100,1400,*,RIGHT,PWELL +S 0,5000,5500,5000,300,*,RIGHT,NTIE +S 0,0,5500,0,300,*,RIGHT,PTIE +S 0,0,5500,0,400,vss,RIGHT,CALU1 +S 0,4000,5500,4000,1200,*,RIGHT,NWELL +S 0,3100,5500,3100,1200,*,RIGHT,NWELL +S 0,5000,5500,5000,400,vdd,RIGHT,CALU1 +S 300,2600,300,4500,300,*,DOWN,PDIF +S 1000,2600,1000,4500,300,*,DOWN,PDIF +S 600,2400,600,4700,100,*,DOWN,PTRANS +S 5200,2600,5200,4500,300,*,DOWN,PDIF +S 4900,2400,4900,4700,100,*,DOWN,PTRANS +S 4400,2400,4400,4700,100,*,UP,PTRANS +S 1400,3200,1400,4700,100,*,DOWN,PTRANS +S 2000,3200,2000,4700,100,*,DOWN,PTRANS +S 2600,3200,2600,4700,100,*,DOWN,PTRANS +S 4100,2600,4100,4500,300,*,DOWN,PDIF +S 3500,2600,3500,4500,300,*,DOWN,PDIF +S 2900,3400,2900,4500,300,*,DOWN,PDIF +S 2300,3400,2300,4500,300,*,DOWN,PDIF +S 1700,3400,1700,4500,300,*,DOWN,PDIF +S 3200,3200,3200,4700,100,*,DOWN,PTRANS +S 3800,2400,3800,4700,100,*,UP,PTRANS +S 600,300,600,1600,100,*,UP,NTRANS +S 2500,300,2500,1500,100,*,UP,NTRANS +S 4300,300,4300,1000,100,*,UP,NTRANS +S 2000,300,2000,1500,100,*,UP,NTRANS +S 1400,300,1400,1500,100,*,UP,NTRANS +S 3700,300,3700,1000,100,*,UP,NTRANS +S 3100,300,3100,1000,100,*,UP,NTRANS +S 4900,300,4900,1000,100,*,UP,NTRANS +S 1000,500,1000,1400,300,*,UP,NDIF +S 300,500,300,1400,300,*,DOWN,NDIF +S 3400,500,3400,800,300,*,UP,NDIF +S 2800,500,2800,1300,300,*,UP,NDIF +S 4000,500,4000,800,300,*,UP,NDIF +S 1700,500,1700,1300,300,*,UP,NDIF +S 5200,500,5200,800,300,*,UP,NDIF +S 4600,500,4600,800,300,*,UP,NDIF +S 1300,2100,1400,2100,200,*,RIGHT,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +S 600,2100,800,2100,200,*,RIGHT,POLY +S 3000,2100,3200,2100,200,*,RIGHT,POLY +S 2400,2100,2600,2100,200,*,RIGHT,POLY +S 1800,2100,2000,2100,200,*,RIGHT,POLY +S 4900,2100,5100,2100,200,*,RIGHT,POLY +S 2500,1500,2500,2100,100,*,UP,POLY +S 4400,1000,4400,2400,100,*,DOWN,POLY +S 1400,1500,1400,3200,100,*,DOWN,POLY +S 4900,1000,4900,2400,100,*,DOWN,POLY +S 4400,2100,4500,2100,200,*,LEFT,POLY +S 3800,2100,4000,2100,200,*,RIGHT,POLY +S 4300,1000,4400,1000,100,*,RIGHT,POLY +S 3700,1000,3800,1000,100,*,RIGHT,POLY +S 3100,1000,3200,1000,100,*,RIGHT,POLY +S 3200,1000,3200,3200,100,*,DOWN,POLY +S 3800,1000,3800,2400,100,*,DOWN,POLY +S 2000,1500,2000,3200,100,*,DOWN,POLY +S 2600,2100,2600,3200,100,*,DOWN,POLY +S 1000,0,1000,600,200,*,DOWN,ALU1 +S 5200,0,5200,600,200,*,DOWN,ALU1 +S 4000,0,4000,600,200,*,DOWN,ALU1 +S 1000,3900,1000,5000,200,*,UP,ALU1 +S 300,600,300,4400,200,q,UP,CALU1 +S 800,2100,800,3400,200,*,UP,ALU1 +S 800,3400,3500,3400,200,*,RIGHT,ALU1 +S 1700,3900,2900,3900,200,*,LEFT,ALU1 +S 1700,3900,1700,4400,200,*,UP,ALU1 +S 2900,3900,2900,4400,200,*,DOWN,ALU1 +S 1300,1100,1300,2900,200,i0,DOWN,CALU1 +S 4500,1600,4500,3900,200,i4,DOWN,CALU1 +S 5100,1100,5100,3900,200,i5,UP,CALU1 +S 2300,2100,2400,2100,200,*,LEFT,ALU1 +S 3000,2100,3000,2900,200,i6,DOWN,CALU1 +S 2300,600,2300,2900,200,i2,DOWN,CALU1 +S 1800,600,1800,2900,200,i1,DOWN,CALU1 +S 2800,600,2800,1600,200,*,DOWN,ALU1 +S 2800,1600,3500,1600,200,*,LEFT,ALU1 +S 4000,1600,4000,3900,200,i3,DOWN,CALU1 +S 3500,1600,3500,3900,200,*,DOWN,ALU1 +S 2900,4400,5200,4400,200,*,LEFT,ALU1 +S 2300,4400,2300,5000,200,*,UP,ALU1 +S 3400,1100,4600,1100,200,*,LEFT,ALU1 +S 3400,600,3400,1100,200,*,DOWN,ALU1 +S 4600,600,4600,1100,200,*,UP,ALU1 +B 5050,2100,300,200,CONT_TURN8,* +B 4500,2100,200,200,CONT_TURN8,* +B 3950,2100,300,200,CONT_TURN8,* +B 3050,2100,300,200,CONT_TURN8,* +B 2450,2100,300,200,CONT_TURN8,* +B 1850,2100,300,200,CONT_TURN8,* +B 1300,2100,200,200,CONT_TURN8,* +B 750,2100,300,200,CONT_TURN8,* +B 4600,1100,200,200,CONT_TURN1,* +B 3400,1100,200,200,CONT_TURN1,* +B 3500,1600,200,200,CONT_TURN1,* +B 2800,1600,200,200,CONT_TURN1,* +B 2900,3900,200,200,CONT_TURN1,* +B 1700,3900,200,200,CONT_TURN1,* +B 800,3400,200,200,CONT_TURN1,* +V 1000,3900,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 300,3300,CONT_DIF_P,* +V 1700,4400,CONT_DIF_P,* +V 2900,4400,CONT_DIF_P,* +V 2300,4400,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 300,2700,CONT_DIF_P,* +V 5200,4400,CONT_DIF_P,* +V 3500,3300,CONT_DIF_P,* +V 3500,3900,CONT_DIF_P,* +V 3500,2700,CONT_DIF_P,* +V 300,1200,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1000,600,CONT_DIF_N,* +V 2800,600,CONT_DIF_N,* +V 3400,600,CONT_DIF_N,* +V 4600,600,CONT_DIF_N,* +V 2800,1200,CONT_DIF_N,* +V 5200,600,CONT_DIF_N,* +V 4000,600,CONT_DIF_N,* +V 4600,600,CONT_DIF_N,* +V 800,2100,CONT_POLY,* +V 1300,2100,CONT_POLY,* +V 4500,2100,CONT_POLY,* +V 5100,2100,CONT_POLY,* +V 2400,2100,CONT_POLY,* +V 3000,2100,CONT_POLY,* +V 4000,2100,CONT_POLY,* +V 1800,2100,CONT_POLY,* +V 1500,0,CONT_BODY_P,* +V 5500,5000,CONT_BODY_N,* +V 5500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 5000,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa3ao322_x2.vbe b/pdks/symbolic/lsxlib/cells/oa3ao322_x2.vbe new file mode 100644 index 000000000..dc2a71887 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa3ao322_x2.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT tpll_i6_q : NATURAL := 540; + CONSTANT tphh_i3_q : NATURAL := 560; + CONSTANT tphh_i6_q : NATURAL := 563; + CONSTANT tphh_i0_q : NATURAL := 638; + CONSTANT tphh_i4_q : NATURAL := 649; + CONSTANT tpll_i2_q : NATURAL := 707; + CONSTANT tphh_i5_q : NATURAL := 734; + CONSTANT tpll_i5_q : NATURAL := 734; + CONSTANT tphh_i1_q : NATURAL := 735; + CONSTANT tpll_i4_q : NATURAL := 760; + CONSTANT tpll_i1_q : NATURAL := 764; + CONSTANT tpll_i3_q : NATURAL := 765; + CONSTANT tphh_i2_q : NATURAL := 806; + CONSTANT tpll_i0_q : NATURAL := 820; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x2; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/oa3ao322_x4.ap b/pdks/symbolic/lsxlib/cells/oa3ao322_x4.ap new file mode 100644 index 000000000..12cf31c44 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa3ao322_x4.ap @@ -0,0 +1,173 @@ +V ALLIANCE : 6 +H oa3ao322_x4,P, 1/ 8/2024,100 +A 0,0,6000,5000 +S 0,1100,6000,1100,1400,*,RIGHT,PWELL +S 300,2100,1200,2100,100,*,RIGHT,POLY +S 0,0,6000,0,300,*,RIGHT,PTIE +S 0,0,6000,0,400,vss,RIGHT,CALU1 +S 0,5000,6000,5000,300,*,RIGHT,NTIE +S 0,4000,6000,4000,1200,*,RIGHT,NWELL +S 0,3100,6000,3100,1200,*,RIGHT,NWELL +S 0,5000,6000,5000,400,vdd,RIGHT,CALU1 +S 3300,3400,3300,4500,300,*,DOWN,PDIF +S 2700,3400,2700,4500,300,*,DOWN,PDIF +S 2100,3400,2100,4500,300,*,DOWN,PDIF +S 1500,3400,1500,4500,300,*,DOWN,PDIF +S 3600,3200,3600,4700,100,*,DOWN,PTRANS +S 4200,2400,4200,4700,100,*,UP,PTRANS +S 4800,2400,4800,4700,100,*,UP,PTRANS +S 1800,3200,1800,4700,100,*,DOWN,PTRANS +S 2400,3200,2400,4700,100,*,DOWN,PTRANS +S 3000,3200,3000,4700,100,*,DOWN,PTRANS +S 300,2600,300,4500,300,*,DOWN,PDIF +S 4500,2600,4500,4500,300,*,DOWN,PDIF +S 3900,2600,3900,4500,300,*,DOWN,PDIF +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 5600,2600,5600,4500,300,*,DOWN,PDIF +S 5300,2400,5300,4700,100,*,DOWN,PTRANS +S 600,2400,600,4700,100,*,UP,PTRANS +S 1200,2400,1200,4700,100,*,DOWN,PTRANS +S 900,2600,900,4500,300,*,DOWN,PDIF +S 600,300,600,1600,100,*,UP,NTRANS +S 1200,300,1200,1600,100,*,UP,NTRANS +S 5300,300,5300,1000,100,*,UP,NTRANS +S 2900,300,2900,1500,100,*,UP,NTRANS +S 3500,300,3500,1000,100,*,UP,NTRANS +S 4100,300,4100,1000,100,*,UP,NTRANS +S 4700,300,4700,1000,100,*,UP,NTRANS +S 2400,300,2400,1500,100,*,UP,NTRANS +S 1800,300,1800,1500,100,*,UP,NTRANS +S 900,500,900,1400,300,*,DOWN,NDIF +S 300,500,300,1400,300,*,DOWN,NDIF +S 2100,500,2100,1300,300,*,UP,NDIF +S 1500,500,1500,1300,300,*,UP,NDIF +S 3200,500,3200,1300,300,*,UP,NDIF +S 3800,500,3800,800,300,*,UP,NDIF +S 4400,500,4400,800,300,*,UP,NDIF +S 5000,500,5000,800,300,*,UP,NDIF +S 5600,500,5600,800,300,*,UP,NDIF +S 3400,2100,3600,2100,200,*,RIGHT,POLY +S 2800,2100,3000,2100,200,*,RIGHT,POLY +S 2200,2100,2400,2100,200,*,RIGHT,POLY +S 4800,1000,4800,2400,100,*,DOWN,POLY +S 4200,2100,4400,2100,200,*,RIGHT,POLY +S 4200,1000,4200,2400,100,*,DOWN,POLY +S 3600,1000,3600,3200,100,*,DOWN,POLY +S 2400,1500,2400,3200,100,*,DOWN,POLY +S 1800,1500,1800,3200,100,*,DOWN,POLY +S 1600,2100,1800,2100,200,*,RIGHT,POLY +S 4800,2100,4900,2100,200,*,LEFT,POLY +S 5300,1000,5300,2400,100,*,DOWN,POLY +S 5300,2100,5500,2100,200,*,RIGHT,POLY +S 2900,1500,2900,2100,100,*,UP,POLY +S 3000,2100,3000,3200,100,*,DOWN,POLY +S 4700,1000,4800,1000,100,*,RIGHT,POLY +S 4100,1000,4200,1000,100,*,RIGHT,POLY +S 3500,1000,3600,1000,100,*,RIGHT,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +S 1200,1600,1200,2400,100,*,DOWN,POLY +S 300,0,300,1200,200,*,DOWN,ALU1 +S 4400,0,4400,600,200,*,DOWN,ALU1 +S 5600,0,5600,600,200,*,DOWN,ALU1 +S 1500,0,1500,600,200,*,DOWN,ALU1 +S 900,600,900,3400,200,q,UP,CALU1 +S 300,2100,300,3900,200,*,DOWN,ALU1 +S 4400,1600,4400,3900,200,i3,DOWN,CALU1 +S 2100,3900,3300,3900,200,*,LEFT,ALU1 +S 3300,3900,3300,4400,200,*,DOWN,ALU1 +S 5000,600,5000,1100,200,*,UP,ALU1 +S 3800,1100,5000,1100,200,*,LEFT,ALU1 +S 3800,600,3800,1100,200,*,DOWN,ALU1 +S 2700,4400,2700,5000,200,*,UP,ALU1 +S 1500,4400,1500,5000,200,*,UP,ALU1 +S 2100,3900,2100,4400,200,*,UP,ALU1 +S 3900,1600,3900,3900,200,*,DOWN,ALU1 +S 3300,4400,5600,4400,200,*,LEFT,ALU1 +S 4900,1600,4900,3900,200,i4,DOWN,CALU1 +S 5500,1100,5500,3900,200,i5,UP,CALU1 +S 2700,2100,2800,2100,200,*,LEFT,ALU1 +S 1600,1100,1600,2900,200,i0,DOWN,CALU1 +S 2700,600,2700,2900,200,i2,DOWN,CALU1 +S 2200,600,2200,2900,200,i1,DOWN,CALU1 +S 3400,2100,3400,2900,200,i6,DOWN,CALU1 +S 3200,600,3200,1600,200,*,DOWN,ALU1 +S 3200,1600,3900,1600,200,*,LEFT,ALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +S 300,3900,1500,3900,200,*,LEFT,ALU1 +S 1500,3400,1500,3900,200,*,UP,ALU1 +S 1500,3400,3900,3400,200,*,LEFT,ALU1 +B 5450,2100,300,200,CONT_TURN8,* +B 4900,2100,200,200,CONT_TURN8,* +B 4350,2100,300,200,CONT_TURN8,* +B 3450,2100,300,200,CONT_TURN8,* +B 2850,2100,300,200,CONT_TURN8,* +B 2250,2100,300,200,CONT_TURN8,* +B 1650,2100,300,200,CONT_TURN8,* +B 700,2100,1000,200,CONT_TURN8,* +B 3800,1100,200,200,CONT_TURN1,* +B 5000,1100,200,200,CONT_TURN1,* +B 3900,1600,200,200,CONT_TURN1,* +B 3200,1600,200,200,CONT_TURN1,* +B 3300,3900,200,200,CONT_TURN1,* +B 2100,3900,200,200,CONT_TURN1,* +B 1500,3400,200,200,CONT_TURN1,* +B 1500,3900,200,200,CONT_TURN1,* +B 300,3900,200,200,CONT_TURN1,* +V 3300,4400,CONT_DIF_P,* +V 3900,3300,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 3900,3900,CONT_DIF_P,* +V 3900,2700,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 900,2700,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 5600,4400,CONT_DIF_P,* +V 900,3400,CONT_DIF_P,* +V 3200,1200,CONT_DIF_N,* +V 4400,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 300,1200,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 3200,600,CONT_DIF_N,* +V 3800,600,CONT_DIF_N,* +V 5000,600,CONT_DIF_N,* +V 5600,600,CONT_DIF_N,* +V 5000,600,CONT_DIF_N,* +V 900,1200,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 2800,2100,CONT_POLY,* +V 3400,2100,CONT_POLY,* +V 4400,2100,CONT_POLY,* +V 2200,2100,CONT_POLY,* +V 300,2100,CONT_POLY,* +V 1600,2100,CONT_POLY,* +V 4900,2100,CONT_POLY,* +V 5500,2100,CONT_POLY,* +V 5500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 5500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 5000,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/oa3ao322_x4.vbe b/pdks/symbolic/lsxlib/cells/oa3ao322_x4.vbe new file mode 100644 index 000000000..6f1ad9762 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/oa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT tpll_i6_q : NATURAL := 651; + CONSTANT tphh_i3_q : NATURAL := 673; + CONSTANT tphh_i6_q : NATURAL := 684; + CONSTANT tphh_i0_q : NATURAL := 717; + CONSTANT tphh_i4_q : NATURAL := 758; + CONSTANT tphh_i1_q : NATURAL := 818; + CONSTANT tpll_i2_q : NATURAL := 834; + CONSTANT tphh_i5_q : NATURAL := 839; + CONSTANT tpll_i5_q : NATURAL := 865; + CONSTANT tpll_i1_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 894; + CONSTANT tpll_i4_q : NATURAL := 896; + CONSTANT tpll_i3_q : NATURAL := 898; + CONSTANT tpll_i0_q : NATURAL := 946; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1500 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/on12_x1.ap b/pdks/symbolic/lsxlib/cells/on12_x1.ap new file mode 100644 index 000000000..745287093 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/on12_x1.ap @@ -0,0 +1,70 @@ +V ALLIANCE : 6 +H on12_x1,P, 1/ 8/2024,100 +A 0,0,2500,5000 +S 0,1100,2500,1100,1400,*,RIGHT,PWELL +S 300,2200,600,2200,100,*,RIGHT,POLY +S 1500,0,1500,600,200,*,DOWN,ALU1 +S 1500,4400,1500,5000,200,*,UP,ALU1 +S 1800,2800,1800,3600,100,*,DOWN,POLY +S 1600,2800,1800,2800,200,*,LEFT,POLY +S 1600,1700,1800,1700,200,*,LEFT,POLY +S 1800,1000,1800,1700,100,*,UP,POLY +S 1200,2200,2100,2200,200,*,RIGHT,POLY +S 1600,1100,1600,3900,200,i1,DOWN,CALU1 +S 300,1100,300,3900,200,i0,DOWN,CALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +S 300,600,900,600,200,*,RIGHT,ALU1 +S 900,600,900,4400,200,q,DOWN,CALU1 +S 2100,600,2100,4400,200,*,DOWN,ALU1 +S 2100,500,2100,800,300,*,DOWN,NDIF +S 1500,500,1500,1400,300,*,DOWN,NDIF +S 900,500,900,1400,300,*,DOWN,NDIF +S 300,500,300,1400,300,*,DOWN,NDIF +S 2100,3800,2100,4500,300,*,DOWN,PDIF +S 1500,3600,1500,4500,300,*,DOWN,PDIF +S 900,3600,900,4500,300,*,DOWN,PDIF +S 300,3600,300,4500,300,*,DOWN,PDIF +S 1200,1600,1200,3400,100,*,DOWN,POLY +S 600,1600,600,3400,100,*,DOWN,POLY +S 1800,3600,1800,4700,100,*,DOWN,PTRANS +S 1200,3400,1200,4700,100,*,DOWN,PTRANS +S 600,3400,600,4700,100,*,DOWN,PTRANS +S 1800,300,1800,1000,100,*,UP,NTRANS +S 1200,300,1200,1600,100,*,UP,NTRANS +S 600,300,600,1600,100,*,UP,NTRANS +S 0,5000,2500,5000,400,vdd,RIGHT,CALU1 +S 0,0,2500,0,400,vss,RIGHT,CALU1 +S 0,4000,2500,4000,1200,*,RIGHT,NWELL +S 0,3100,2500,3100,1200,*,RIGHT,NWELL +S 0,5000,2500,5000,300,*,RIGHT,NTIE +S 0,0,2500,0,300,*,RIGHT,PTIE +B 1700,2200,1000,200,CONT_TURN8,* +B 1650,2800,300,200,CONT_TURN8,* +B 1650,1700,300,200,CONT_TURN8,* +B 400,2200,400,200,CONT_TURN8,* +V 1600,2800,CONT_POLY,* +V 300,2200,CONT_POLY,* +V 2100,2200,CONT_POLY,* +V 1600,1700,CONT_POLY,* +V 900,3700,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 2100,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 300,4400,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/on12_x1.vbe b/pdks/symbolic/lsxlib/cells/on12_x1.vbe new file mode 100644 index 000000000..32688f423 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/on12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3720; + CONSTANT rup_i1_q : NATURAL := 3720; + CONSTANT tphl_i0_q : NATURAL := 111; + CONSTANT tplh_i0_q : NATURAL := 234; + CONSTANT tpll_i1_q : NATURAL := 291; + CONSTANT tphh_i1_q : NATURAL := 314; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x1; + +ARCHITECTURE behaviour_data_flow OF on12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x1" + SEVERITY WARNING; + q <= (not (i0) or i1) after 900 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/on12_x4.ap b/pdks/symbolic/lsxlib/cells/on12_x4.ap new file mode 100644 index 000000000..ae3a1736d --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/on12_x4.ap @@ -0,0 +1,129 @@ +V ALLIANCE : 6 +H on12_x4,P, 5/ 8/2024,100 +A 0,0,4500,5000 +S 2500,2200,2800,2200,200,*,LEFT,POLY2 +S 2500,1200,2700,1200,200,*,LEFT,POLY2 +S 3700,1200,3900,1200,200,*,LEFT,POLY2 +S 3700,2200,3900,2200,200,*,LEFT,POLY2 +S 0,1100,4500,1100,1400,*,RIGHT,PWELL +S 3000,600,3000,2700,200,*,UP,ALU1 +S 2500,2700,3000,2700,200,*,RIGHT,ALU1 +S 2500,2700,2500,4400,200,*,UP,ALU1 +S 3900,2200,3900,3600,100,*,DOWN,POLY +S 2800,2200,2800,2400,100,*,DOWN,POLY +S 2500,2200,2800,2200,200,*,RIGHT,POLY +S 3700,2200,3900,2200,200,*,LEFT,POLY +S 2000,2200,2500,2200,200,*,LEFT,ALU1 +S 3300,1100,3300,2400,100,*,DOWN,POLY +S 3600,2600,3600,4500,300,*,DOWN,PDIF +S 3300,2400,3300,4700,100,*,DOWN,PTRANS +S 2500,2600,2500,4500,300,*,DOWN,PDIF +S 2800,2400,2800,4700,100,*,DOWN,PTRANS +S 2700,300,2700,1100,100,*,UP,NTRANS +S 3300,300,3300,1100,100,*,UP,NTRANS +S 3000,500,3000,900,300,*,DOWN,NDIF +S 2400,500,2400,900,300,*,DOWN,NDIF +S 3600,500,3600,900,300,*,DOWN,NDIF +S 2700,1100,2700,1200,100,*,UP,POLY +S 2500,1200,2700,1200,200,*,RIGHT,POLY +S 2000,1200,2500,1200,200,*,LEFT,ALU1 +S 600,1700,2900,1700,200,*,LEFT,POLY +S 2000,1100,2000,4400,200,i1,DOWN,CALU1 +S 900,600,900,4400,200,q,DOWN,CALU1 +S 1500,2700,1500,4900,200,*,UP,ALU1 +S 300,2700,300,5000,200,*,UP,ALU1 +S 1500,0,1500,1300,200,*,DOWN,ALU1 +S 300,0,300,1300,200,*,DOWN,ALU1 +S 0,0,4500,0,300,*,RIGHT,PTIE +S 0,0,4500,0,400,vss,RIGHT,CALU1 +S 0,5000,4500,5000,300,*,RIGHT,NTIE +S 0,4000,4500,4000,1200,*,RIGHT,NWELL +S 0,3100,4500,3100,1200,*,RIGHT,NWELL +S 0,5000,4500,5000,400,vdd,RIGHT,CALU1 +S 3900,3600,3900,4700,100,*,DOWN,PTRANS +S 4200,3800,4200,4500,300,*,DOWN,PDIF +S 3900,300,3900,1000,100,*,UP,NTRANS +S 4200,500,4200,800,300,*,DOWN,NDIF +S 3900,1000,3900,1200,100,*,UP,POLY +S 3300,1700,4200,1700,200,*,RIGHT,POLY +S 3700,1200,3900,1200,200,*,LEFT,POLY +S 2400,0,2400,600,200,*,DOWN,ALU1 +S 3600,0,3600,600,200,*,DOWN,ALU1 +S 4200,600,4200,4400,200,*,DOWN,ALU1 +S 3600,4400,3600,5000,200,*,UP,ALU1 +S 3700,1100,3700,3900,200,i0,DOWN,CALU1 +S 600,2400,600,4700,100,*,DOWN,PTRANS +S 300,2600,300,4500,300,*,DOWN,PDIF +S 1200,2400,1200,4700,100,*,DOWN,PTRANS +S 1500,2600,1500,4500,300,*,DOWN,PDIF +S 900,2600,900,4500,300,*,DOWN,PDIF +S 1200,300,1200,1600,100,*,UP,NTRANS +S 600,300,600,1600,100,*,UP,NTRANS +S 300,500,300,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +S 900,500,900,1400,300,*,UP,NDIF +S 1200,1600,1200,2400,100,*,DOWN,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +B 1800,1700,2400,200,CONT_TURN8,* +B 3800,1700,1000,200,CONT_TURN8,* +B 3750,2200,300,200,CONT_TURN8,* +B 3750,1200,300,200,CONT_TURN8,* +B 2550,1200,300,200,CONT_TURN8,* +B 2600,2200,400,200,CONT_TURN8,* +B 3000,2700,200,200,CONT_TURN1,* +V 3500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 2500,2200,CONT_POLY,* +V 3700,2200,CONT_POLY,* +V 2500,2700,CONT_DIF_P,* +V 2500,3300,CONT_DIF_P,* +V 2500,3800,CONT_DIF_P,* +V 2500,1200,CONT_POLY,* +V 2900,1700,CONT_POLY,* +V 2500,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 1500,3800,CONT_DIF_P,* +V 900,3800,CONT_DIF_P,* +V 900,2700,CONT_DIF_P,* +V 1500,2700,CONT_DIF_P,* +V 1500,3300,CONT_DIF_P,* +V 900,3300,CONT_DIF_P,* +V 300,3300,CONT_DIF_P,* +V 300,3800,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 300,2700,CONT_DIF_P,* +V 1500,1300,CONT_DIF_N,* +V 3600,4400,CONT_DIF_P,* +V 4200,3900,CONT_DIF_P,* +V 4200,4400,CONT_DIF_P,* +V 3600,600,CONT_DIF_N,* +V 2400,600,CONT_DIF_N,* +V 3000,600,CONT_DIF_N,* +V 4200,600,CONT_DIF_N,* +V 3700,1200,CONT_POLY,* +V 4200,1700,CONT_POLY,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 300,1300,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 900,1300,CONT_DIF_N,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/on12_x4.vbe b/pdks/symbolic/lsxlib/cells/on12_x4.vbe new file mode 100644 index 000000000..c5f990c6c --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/on12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 394; + CONSTANT tphl_i0_q : NATURAL := 474; + CONSTANT tphh_i1_q : NATURAL := 491; + CONSTANT tplh_i0_q : NATURAL := 499; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x4; + +ARCHITECTURE behaviour_data_flow OF on12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x4" + SEVERITY WARNING; + q <= (not (i0) or i1) after 1100 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/one_x0.ap b/pdks/symbolic/lsxlib/cells/one_x0.ap new file mode 100644 index 000000000..99819a1ad --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/one_x0.ap @@ -0,0 +1,32 @@ +V ALLIANCE : 6 +H one_x0,P, 5/ 8/2024,100 +A 0,0,1500,5000 +S 400,3800,700,3800,200,*,LEFT,POLY2 +S 0,1100,1500,1100,1400,*,RIGHT,PWELL +S 400,3800,700,3800,200,*,RIGHT,POLY +S 700,3800,700,3900,100,*,DOWN,POLY +S 1000,600,1000,4400,200,q,DOWN,CALU1 +S 400,0,400,3800,200,*,UP,ALU1 +S 400,4400,400,5000,200,*,UP,ALU1 +S 1000,4100,1000,4500,300,*,DOWN,PDIF +S 400,4100,400,4500,300,*,DOWN,PDIF +S 700,3900,700,4700,100,*,DOWN,PTRANS +S 0,0,1500,0,400,vss,RIGHT,CALU1 +S 0,5000,1500,5000,400,vdd,RIGHT,CALU1 +S 0,4000,1500,4000,1200,*,RIGHT,NWELL +S 0,3100,1500,3100,1200,*,RIGHT,NWELL +S 0,5000,1500,5000,300,*,RIGHT,NTIE +S 0,0,1500,0,300,*,RIGHT,PTIE +B 500,3800,400,200,CONT_TURN8,* +V 400,3800,CONT_POLY,* +V 1000,4400,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/one_x0.vbe b/pdks/symbolic/lsxlib/cells/one_x0.vbe new file mode 100644 index 000000000..e7439c597 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/one_x0.vbe @@ -0,0 +1,20 @@ +ENTITY one_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END one_x0; + +ARCHITECTURE behaviour_data_flow OF one_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on one_x0" + SEVERITY WARNING; + q <= '1'; +END; diff --git a/pdks/symbolic/lsxlib/cells/powmid_x0.vbe b/pdks/symbolic/lsxlib/cells/powmid_x0.vbe new file mode 100644 index 000000000..52f4c8149 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/powmid_x0.vbe @@ -0,0 +1,18 @@ +ENTITY powmid_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END powmid_x0; + +ARCHITECTURE behaviour_data_flow OF powmid_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on powmid_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/lsxlib/cells/rowend_x0.ap b/pdks/symbolic/lsxlib/cells/rowend_x0.ap new file mode 100644 index 000000000..d03c5f841 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/rowend_x0.ap @@ -0,0 +1,15 @@ +V ALLIANCE : 6 +H rowend_x0,P,17/ 4/2023,100 +A 0,0,500,5000 +S 0,1100,500,1100,1400,*,RIGHT,PWELL +S 0,0,500,0,300,*,RIGHT,PTIE +S 0,5000,500,5000,300,*,RIGHT,NTIE +S 0,4000,500,4000,1200,*,RIGHT,NWELL +S 0,3100,500,3100,1200,*,RIGHT,NWELL +S 0,0,500,0,400,vss,RIGHT,CALU1 +S 0,5000,500,5000,400,vdd,RIGHT,CALU1 +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/rowend_x0.vbe b/pdks/symbolic/lsxlib/cells/rowend_x0.vbe new file mode 100644 index 000000000..dfe3de719 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/rowend_x0.vbe @@ -0,0 +1,18 @@ +ENTITY rowend_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 250; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END rowend_x0; + +ARCHITECTURE behaviour_data_flow OF rowend_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rowend_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/lsxlib/cells/sff1_x4.ap b/pdks/symbolic/lsxlib/cells/sff1_x4.ap new file mode 100644 index 000000000..b54a9e97e --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/sff1_x4.ap @@ -0,0 +1,275 @@ +V ALLIANCE : 6 +H sff1_x4,P, 5/ 8/2024,100 +A 0,0,9000,5000 +S 6000,3000,6000,3200,200,*,UP,POLY2 +S 2400,1100,2500,1100,200,*,LEFT,POLY2 +S 2400,3500,2500,3500,200,*,LEFT,POLY2 +S 600,1200,800,1200,200,*,LEFT,POLY2 +S 600,3300,800,3300,200,*,LEFT,POLY2 +S 0,1100,9000,1100,1400,*,RIGHT,PWELL +S 900,4400,900,5000,200,*,UP,ALU1 +S 2000,1500,4100,1500,100,*,LEFT,POLY +S 2000,1500,2000,2000,100,*,UP,POLY +S 800,1600,800,2500,100,*,UP,POLY +S 8400,1600,8400,2400,100,*,DOWN,POLY +S 7800,1600,7800,2400,100,*,DOWN,POLY +S 4600,1600,4600,3000,200,sff_m,DOWN,ALU1 +S 6500,600,6500,4000,200,sff_s,UP,ALU1 +S 4600,1000,4600,1100,100,*,DOWN,POLY +S 5500,500,5500,800,300,*,UP,NDIF +S 6700,500,6700,900,300,*,UP,NDIF +S 6700,3600,6700,4500,300,*,DOWN,PDIF +S 900,3600,900,4500,300,*,UP,PDIF +S 6500,2000,7600,2000,200,*,LEFT,ALU1 +S 7700,2000,8400,2000,200,*,RIGHT,POLY +S 7000,1500,8100,1500,200,*,RIGHT,ALU1 +S 7000,2500,8100,2500,200,*,RIGHT,ALU1 +S 7500,2600,7500,4500,300,*,DOWN,PDIF +S 7500,500,7500,1400,300,*,DOWN,NDIF +S 6100,600,6500,600,200,*,RIGHT,ALU1 +S 6100,4000,6500,4000,200,*,LEFT,ALU1 +S 6400,3200,6400,3400,100,*,DOWN,POLY +S 6000,3200,6400,3200,100,*,RIGHT,POLY +S 5600,2500,5600,3600,100,*,DOWN,POLY +S 5600,3600,5800,3600,100,*,LEFT,POLY +S 5800,1600,6000,1600,200,*,LEFT,ALU1 +S 6000,1600,6000,3300,200,*,DOWN,ALU1 +S 4900,4000,4900,5000,200,*,UP,ALU1 +S 2700,4000,2700,5000,200,*,UP,ALU1 +S 7500,3000,7500,5000,200,*,DOWN,ALU1 +S 7500,0,7500,1000,200,*,DOWN,ALU1 +S 3000,1200,3000,3000,200,u,DOWN,ALU1 +S 3000,3000,3000,3600,100,*,UP,POLY +S 2000,3000,3000,3000,100,*,RIGHT,POLY +S 5500,2400,5500,4400,200,y,DOWN,ALU1 +S 6100,4000,6100,4400,200,*,DOWN,ALU1 +S 2100,4000,2100,4400,200,*,DOWN,ALU1 +S 3800,4000,3800,4400,200,*,DOWN,ALU1 +S 3800,4000,4000,4000,200,*,RIGHT,ALU1 +S 2000,4000,2100,4000,200,*,RIGHT,ALU1 +S 2000,600,2000,4000,200,*,UP,ALU1 +S 2000,600,2100,600,200,*,RIGHT,ALU1 +S 4600,1600,5200,1600,100,*,RIGHT,POLY +S 4100,1000,4100,2100,100,*,DOWN,POLY +S 4100,2000,5800,2000,100,ckr,RIGHT,POLY +S 3500,2400,4100,2400,200,*,RIGHT,ALU1 +S 4100,2100,4100,2400,200,*,UP,ALU1 +S 1200,2500,1200,3400,100,*,DOWN,POLY +S 1500,700,1500,4300,200,*,DOWN,ALU1 +S 300,700,300,4300,200,*,DOWN,ALU1 +S 1500,3600,1500,4500,300,*,UP,PDIF +S 300,3600,300,4500,300,*,UP,PDIF +S 600,3400,600,4700,100,*,DOWN,PTRANS +S 1200,3400,1200,4700,100,*,DOWN,PTRANS +S 7000,1100,7000,1500,100,*,DOWN,POLY +S 7000,300,7000,1100,100,*,UP,NTRANS +S 7000,2500,7000,3400,100,*,UP,POLY +S 7000,3400,7000,4700,100,*,DOWN,PTRANS +S 6100,3600,6100,4500,300,*,UP,PDIF +S 7300,500,7300,900,300,*,DOWN,NDIF +S 7300,3600,7300,4500,300,*,DOWN,PDIF +S 8100,600,8100,4300,200,q,DOWN,CALU1 +S 8700,0,8700,1200,200,*,DOWN,ALU1 +S 8700,2800,8700,5000,200,*,DOWN,ALU1 +S 300,2500,6200,2500,100,nckr,RIGHT,POLY +S 6200,1100,6200,2500,100,*,UP,POLY +S 6200,1100,6400,1100,100,*,LEFT,POLY +S 5100,2400,5500,2400,200,*,RIGHT,ALU1 +S 4700,3500,5500,3500,200,*,RIGHT,ALU1 +S 4000,3000,4600,3000,200,*,RIGHT,ALU1 +S 4600,3000,5200,3000,100,*,RIGHT,POLY +S 5200,3000,5200,3600,100,*,DOWN,POLY +S 5800,3600,5800,4700,100,*,DOWN,PTRANS +S 5500,3800,5500,4500,300,*,DOWN,PDIF +S 6400,3400,6400,4700,100,*,DOWN,PTRANS +S 5200,3600,5200,4700,100,*,UP,PTRANS +S 4000,3000,4000,4000,200,*,DOWN,ALU1 +S 8700,500,8700,1400,300,*,DOWN,NDIF +S 4100,2500,4100,3600,100,*,DOWN,POLY +S 4000,1600,4600,1600,200,*,RIGHT,ALU1 +S 4600,3500,4600,3600,100,*,DOWN,POLY +S 2500,1100,2500,3500,200,i,DOWN,CALU1 +S 3500,3500,3500,3600,100,*,UP,POLY +S 2700,3800,2700,4500,300,*,UP,PDIF +S 2400,3600,2400,4700,100,*,DOWN,PTRANS +S 3000,3600,3000,4700,100,*,DOWN,PTRANS +S 4100,3600,4100,4700,100,*,DOWN,PTRANS +S 2100,3800,2100,4500,300,*,UP,PDIF +S 4900,3800,4900,4500,300,*,DOWN,PDIF +S 4600,3600,4600,4700,100,*,DOWN,PTRANS +S 3900,3800,3900,4500,300,*,UP,PDIF +S 3500,3600,3500,4700,100,*,DOWN,PTRANS +S 3500,2400,3500,3400,200,*,UP,ALU1 +S 3500,1900,3500,2500,200,*,UP,POLY +S 3500,1200,3500,1900,200,*,DOWN,ALU1 +S 1500,2000,2000,2000,100,*,RIGHT,POLY +S 2100,500,2100,800,300,*,DOWN,NDIF +S 2400,300,2400,1000,100,*,UP,NTRANS +S 5800,1000,5800,2000,100,*,UP,POLY +S 5200,1000,5200,1600,100,*,DOWN,POLY +S 3000,1000,3000,1100,100,*,DOWN,POLY +S 3500,1000,3500,1100,100,*,DOWN,POLY +S 5800,300,5800,1000,100,*,UP,NTRANS +S 4900,500,4900,800,300,*,DOWN,NDIF +S 5200,300,5200,1000,100,*,UP,NTRANS +S 4600,300,4600,1000,100,*,UP,NTRANS +S 4100,300,4100,1000,100,*,UP,NTRANS +S 3800,500,3800,800,300,*,DOWN,NDIF +S 2700,500,2700,800,300,*,DOWN,NDIF +S 3500,300,3500,1000,100,*,UP,NTRANS +S 3000,300,3000,1000,100,*,UP,NTRANS +S 6400,300,6400,1100,100,*,UP,NTRANS +S 6100,500,6100,900,300,*,DOWN,NDIF +S 4600,1100,5500,1100,200,*,RIGHT,ALU1 +S 5500,600,5500,1100,200,*,UP,ALU1 +S 5100,1100,5100,2400,200,*,UP,ALU1 +S 7800,300,7800,1600,100,*,UP,NTRANS +S 8400,300,8400,1600,100,*,UP,NTRANS +S 8100,500,8100,1400,300,*,DOWN,NDIF +S 8400,2400,8400,4700,100,*,DOWN,PTRANS +S 8100,2600,8100,4500,300,*,DOWN,PDIF +S 7800,2400,7800,4700,100,*,DOWN,PTRANS +S 8700,2600,8700,4500,300,*,DOWN,PDIF +S 4900,0,4900,600,200,*,DOWN,ALU1 +S 4000,600,4000,1600,200,*,UP,ALU1 +S 3800,600,4000,600,200,*,RIGHT,ALU1 +S 2700,0,2700,600,200,*,DOWN,ALU1 +S 800,1100,800,3900,200,ck,DOWN,CALU1 +S 0,5000,9000,5000,300,*,RIGHT,NTIE +S 900,0,900,600,200,*,DOWN,ALU1 +S 1200,1100,1200,1600,100,*,UP,POLY +S 800,1600,1200,1600,100,*,LEFT,POLY +S 900,600,900,900,300,*,DOWN,NDIF +S 1200,300,1200,1100,100,*,UP,NTRANS +S 600,300,600,1100,100,*,UP,NTRANS +S 1500,500,1500,900,300,*,DOWN,NDIF +S 300,500,300,900,300,*,DOWN,NDIF +S 0,4000,9000,4000,1200,*,RIGHT,NWELL +S 0,3100,9000,3100,1200,*,RIGHT,NWELL +S 0,0,9000,0,300,*,RIGHT,PTIE +S 0,0,9000,0,400,vss,RIGHT,CALU1 +S 0,5000,9000,5000,400,vdd,RIGHT,CALU1 +B 7950,2000,900,200,CONT_TURN8,* +B 4600,3500,200,200,CONT_TURN8,* +B 3500,3500,200,200,CONT_TURN8,* +B 4600,1100,200,200,CONT_TURN8,* +B 3500,2150,200,700,CONT_TURN8,* +B 3500,1100,200,200,CONT_TURN8,* +B 3000,1100,200,200,CONT_TURN8,* +B 5500,2400,200,200,CONT_TURN1,* +B 5100,2400,200,200,CONT_TURN1,* +B 2000,4000,200,200,CONT_TURN1,* +B 4000,600,200,200,CONT_TURN1,* +B 4000,1600,200,200,CONT_TURN1,* +B 6500,600,200,200,CONT_TURN1,* +B 6500,4000,200,200,CONT_TURN1,* +B 6000,1600,200,200,CONT_TURN1,* +B 5500,1100,200,200,CONT_TURN1,* +B 2000,600,200,200,CONT_TURN1,* +B 4100,2400,200,200,CONT_TURN1,* +B 4000,3000,200,200,CONT_TURN1,* +B 4000,4000,200,200,CONT_TURN1,* +V 7600,2000,CONT_POLY,* +V 7000,1500,CONT_POLY,* +V 7000,2500,CONT_POLY,* +V 6000,3000,CONT_POLY,* +V 4900,4000,CONT_DIF_P,* +V 4900,4400,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 7500,3700,CONT_DIF_P,* +V 7500,3000,CONT_DIF_P,* +V 7500,600,CONT_DIF_N,* +V 7500,1000,CONT_DIF_N,* +V 9000,5000,CONT_BODY_N,* +V 8500,5000,CONT_BODY_N,* +V 8000,5000,CONT_BODY_N,* +V 7500,5000,CONT_BODY_N,* +V 7000,5000,CONT_BODY_N,* +V 6500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 3000,3000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 6100,4000,CONT_DIF_P,* +V 5500,4000,CONT_DIF_P,* +V 3800,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 6100,4400,CONT_DIF_P,* +V 5500,4400,CONT_DIF_P,* +V 3800,4400,CONT_DIF_P,* +V 2100,600,CONT_DIF_N,* +V 4600,1600,CONT_POLY,* +V 4100,2100,CONT_POLY,* +V 1500,4300,CONT_DIF_P,* +V 300,4300,CONT_DIF_P,* +V 300,3800,CONT_DIF_P,* +V 1500,3800,CONT_DIF_P,* +V 800,3300,CONT_POLY,* +V 8100,600,CONT_DIF_N,* +V 8700,600,CONT_DIF_N,* +V 8100,4300,CONT_DIF_P,* +V 4600,3500,CONT_POLY,* +V 4600,3000,CONT_POLY,* +V 3500,3500,CONT_POLY,* +V 2500,3500,CONT_POLY,* +V 300,2500,CONT_POLY,* +V 3500,1900,CONT_POLY,* +V 2500,1100,CONT_POLY,* +V 5800,1600,CONT_POLY,* +V 4600,1100,CONT_POLY,* +V 3500,1100,CONT_POLY,* +V 3000,1100,CONT_POLY,* +V 6100,600,CONT_DIF_N,* +V 8100,1200,CONT_DIF_N,* +V 8700,1200,CONT_DIF_N,* +V 8100,2800,CONT_DIF_P,* +V 8700,2800,CONT_DIF_P,* +V 8100,3800,CONT_DIF_P,* +V 8700,3300,CONT_DIF_P,* +V 8700,3800,CONT_DIF_P,* +V 7500,4300,CONT_DIF_P,* +V 8700,4300,CONT_DIF_P,* +V 8100,3300,CONT_DIF_P,* +V 5500,600,CONT_DIF_N,* +V 4900,600,CONT_DIF_N,* +V 3800,600,CONT_DIF_N,* +V 2700,600,CONT_DIF_N,* +V 900,4400,CONT_DIF_P,* +V 1500,2000,CONT_POLY,* +V 800,1200,CONT_POLY,* +V 900,600,CONT_DIF_N,* +V 1500,700,CONT_DIF_N,* +V 300,700,CONT_DIF_N,* +V 9000,0,CONT_BODY_P,* +V 8000,0,CONT_BODY_P,* +V 8500,0,CONT_BODY_P,* +V 7500,0,CONT_BODY_P,* +V 7000,0,CONT_BODY_P,* +V 6500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/sff1_x4.vbe b/pdks/symbolic/lsxlib/cells/sff1_x4.vbe new file mode 100644 index 000000000..4756bfddd --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/sff1_x4.vbe @@ -0,0 +1,39 @@ +ENTITY sff1_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tsr_i_ck : NATURAL := 476; + CONSTANT transistors : NATURAL := 26 +); +PORT ( + ck : in BIT; + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff1_x4; + +ARCHITECTURE VBE OF sff1_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff1_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED i; + END BLOCK label0; + + q <= sff_m after 1700 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/sff1r_x4.vbe b/pdks/symbolic/lsxlib/cells/sff1r_x4.vbe new file mode 100644 index 000000000..5d04e53d9 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/sff1r_x4.vbe @@ -0,0 +1,50 @@ +ENTITY sff1r_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_i : NATURAL := 8; + CONSTANT cin_nrst : NATURAL := 16; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT taf_nrst_q : NATURAL := 500; + CONSTANT tar_nrst_q : NATURAL := 500; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tsr_i_ck : NATURAL := 476; + CONSTANT transistors : NATURAL := 30 +); +PORT ( + ck : in BIT; + i : in BIT; + nrst : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff1r_x4; + +ARCHITECTURE VBE OF sff1r_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff1r_x4" + SEVERITY WARNING; + + label0 : BLOCK (nrst = '0') + BEGIN + sff_m <= GUARDED '0'; + END BLOCK label0; + label1 : BLOCK ( (ck AND NOT(ck'STABLE)) = '1' ) + BEGIN + label2 : BLOCK (nrst = '1') + BEGIN + sff_m <= GUARDED i; + END BLOCK label2; + END BLOCK label1; + + q <= sff_m after 1700 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/sff2_x4.ap b/pdks/symbolic/lsxlib/cells/sff2_x4.ap new file mode 100644 index 000000000..42b0b76bd --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/sff2_x4.ap @@ -0,0 +1,345 @@ +V ALLIANCE : 6 +H sff2_x4,P, 5/ 8/2024,100 +A 0,0,12000,5000 +S 3900,2500,9400,2500,100,*,RIGHT,POLY +S 2700,2000,6000,2000,100,*,RIGHT,POLY +S 7100,2000,7100,2100,200,*,DOWN,POLY2 +S 9000,3000,9400,3000,200,*,LEFT,POLY2 +S 4200,1100,4400,1100,100,*,LEFT,POLY +S 4400,1100,4400,1200,200,*,DOWN,POLY2 +S 3900,1500,3900,1600,200,*,UP,POLY2 +S 4200,3300,4400,3300,200,*,LEFT,POLY2 +S 1200,3400,1200,3600,100,*,DOWN,POLY +S 2900,1500,3200,1500,200,*,LEFT,POLY2 +S 2900,3500,3200,3500,200,*,LEFT,POLY2 +S 2300,3500,2500,3500,200,*,LEFT,POLY2 +S 1000,1600,1200,1600,200,*,RIGHT,POLY2 +S 1000,3400,1200,3400,200,*,RIGHT,POLY2 +S 0,1100,12000,1100,1400,*,RIGHT,PWELL +S 4500,4400,4500,5000,200,*,UP,ALU1 +S 5200,1500,7100,1500,100,*,LEFT,POLY +S 9400,1100,9400,2500,100,*,UP,POLY +S 11400,1600,11400,2400,100,*,DOWN,POLY +S 10800,1600,10800,2400,100,*,DOWN,POLY +S 6500,2500,6500,3400,200,*,UP,ALU1 +S 7600,1600,7600,3000,200,sff_m,DOWN,ALU1 +S 9500,600,9500,4000,200,sff_s,UP,ALU1 +S 2000,2000,2700,2000,200,*,RIGHT,ALU1 +S 2300,1000,2300,2500,100,*,UP,POLY +S 1700,2500,1700,3600,100,*,UP,POLY +S 600,2500,2300,2500,200,*,RIGHT,POLY +S 300,1100,1700,1100,200,*,RIGHT,ALU1 +S 1700,1000,1700,1100,100,*,DOWN,POLY +S 2000,600,2700,600,200,*,RIGHT,ALU1 +S 2700,600,2700,2000,200,*,UP,ALU1 +S 2300,300,2300,1000,100,*,UP,NTRANS +S 3200,1100,3200,3900,200,i1,DOWN,CALU1 +S 10500,0,10500,1000,200,*,UP,ALU1 +S 10500,3000,10500,5000,200,*,DOWN,ALU1 +S 6500,2000,6500,2500,200,*,UP,POLY +S 6500,1200,6500,2000,200,*,DOWN,ALU1 +S 7100,2100,7100,2500,200,*,UP,ALU1 +S 6500,2500,7100,2500,200,*,RIGHT,ALU1 +S 6000,3500,6000,3600,100,*,UP,POLY +S 6000,1200,6000,3500,200,u,DOWN,ALU1 +S 0,4000,12000,4000,1200,*,RIGHT,NWELL +S 0,3100,12000,3100,1200,*,RIGHT,NWELL +S 5100,600,5100,4300,200,*,DOWN,ALU1 +S 3900,600,3900,4300,200,*,DOWN,ALU1 +S 4500,3600,4500,4500,300,*,UP,PDIF +S 9700,3600,9700,4500,200,*,DOWN,PDIF +S 7600,1000,7600,1100,100,*,DOWN,POLY +S 9700,500,9700,900,200,*,UP,NDIF +S 8500,500,8500,800,200,*,UP,NDIF +S 600,1000,600,3600,100,*,DOWN,POLY +S 2500,3500,2500,4400,200,*,UP,ALU1 +S 3200,3800,3200,4500,300,*,DOWN,PDIF +S 900,3800,900,4500,300,*,DOWN,PDIF +S 2300,3600,2300,4700,100,*,DOWN,PTRANS +S 2000,3800,2000,4500,500,*,DOWN,PDIF +S 2900,3600,2900,4700,100,*,DOWN,PTRANS +S 1200,3600,1200,4700,100,*,DOWN,PTRANS +S 300,3800,300,4500,300,*,DOWN,PDIF +S 600,3600,600,4700,100,*,DOWN,PTRANS +S 1700,3600,1700,4700,100,*,DOWN,PTRANS +S 2600,3800,2600,4500,300,*,UP,PDIF +S 10500,2600,10500,4500,300,*,DOWN,PDIF +S 10500,500,10500,1400,300,*,DOWN,NDIF +S 9500,2000,10600,2000,200,*,LEFT,ALU1 +S 9100,600,9500,600,200,*,RIGHT,ALU1 +S 9100,4000,9500,4000,200,*,LEFT,ALU1 +S 9000,3000,9400,3000,200,*,LEFT,POLY +S 9400,3000,9400,3400,100,*,DOWN,POLY +S 9000,1600,9000,3000,200,*,UP,ALU1 +S 8800,1600,9000,1600,200,*,RIGHT,ALU1 +S 8600,3600,8800,3600,100,*,RIGHT,POLY +S 8600,2500,8600,3600,100,*,DOWN,POLY +S 7900,4000,7900,5000,200,*,UP,ALU1 +S 5700,4000,5700,5000,200,*,UP,ALU1 +S 10600,2000,11400,2000,200,*,RIGHT,POLY +S 10000,1500,11100,1500,200,*,RIGHT,ALU1 +S 10000,2500,11100,2500,200,*,RIGHT,ALU1 +S 1000,1600,1000,3400,200,i0,DOWN,CALU1 +S 0,5000,12000,5000,300,*,RIGHT,NTIE +S 10800,2400,10800,4700,100,*,DOWN,PTRANS +S 11700,2600,11700,4500,300,*,DOWN,PDIF +S 6000,3600,6000,4700,100,*,DOWN,PTRANS +S 7100,3600,7100,4700,100,*,DOWN,PTRANS +S 7900,3800,7900,4500,300,*,DOWN,PDIF +S 7600,3600,7600,4700,100,*,DOWN,PTRANS +S 6900,3800,6900,4500,300,*,UP,PDIF +S 6500,3600,6500,4700,100,*,DOWN,PTRANS +S 11400,2400,11400,4700,100,*,DOWN,PTRANS +S 11100,2600,11100,4500,300,*,DOWN,PDIF +S 9100,3600,9100,4500,300,*,UP,PDIF +S 10300,3600,10300,4500,300,*,DOWN,PDIF +S 8800,3600,8800,4700,100,*,DOWN,PTRANS +S 8500,3800,8500,4500,300,*,DOWN,PDIF +S 9400,3400,9400,4700,100,*,DOWN,PTRANS +S 8200,3600,8200,4700,100,*,UP,PTRANS +S 5700,3800,5700,4500,300,*,UP,PDIF +S 4200,3400,4200,4700,100,*,DOWN,PTRANS +S 3900,3600,3900,4500,300,*,UP,PDIF +S 5100,3600,5100,4500,300,*,UP,PDIF +S 4800,3400,4800,4700,100,*,DOWN,PTRANS +S 10000,3400,10000,4700,100,*,DOWN,PTRANS +S 2900,300,2900,1000,100,*,UP,NTRANS +S 1700,300,1700,1000,100,*,UP,NTRANS +S 1200,300,1200,1000,100,*,UP,NTRANS +S 600,300,600,1000,100,*,UP,NTRANS +S 6000,300,6000,1000,100,*,UP,NTRANS +S 9400,300,9400,1100,100,*,UP,NTRANS +S 10800,300,10800,1600,100,*,UP,NTRANS +S 11400,300,11400,1600,100,*,UP,NTRANS +S 4200,300,4200,1100,100,*,UP,NTRANS +S 4800,300,4800,1100,100,*,UP,NTRANS +S 10000,300,10000,1100,100,*,UP,NTRANS +S 8800,300,8800,1000,100,*,UP,NTRANS +S 8200,300,8200,1000,100,*,UP,NTRANS +S 7600,300,7600,1000,100,*,UP,NTRANS +S 7100,300,7100,1000,100,*,UP,NTRANS +S 6500,300,6500,1000,100,*,UP,NTRANS +S 2000,500,2000,800,500,*,DOWN,NDIF +S 2600,500,2600,800,300,*,DOWN,NDIF +S 300,500,300,800,300,*,UP,NDIF +S 900,500,900,800,300,*,UP,NDIF +S 11100,500,11100,1400,300,*,DOWN,NDIF +S 5700,500,5700,800,300,*,DOWN,NDIF +S 9100,500,9100,900,300,*,DOWN,NDIF +S 7900,500,7900,800,300,*,DOWN,NDIF +S 6800,500,6800,800,300,*,DOWN,NDIF +S 4500,600,4500,900,300,*,DOWN,NDIF +S 10300,500,10300,900,300,*,DOWN,NDIF +S 11700,500,11700,1400,300,*,DOWN,NDIF +S 3200,500,3200,800,300,*,UP,NDIF +S 3900,500,3900,900,300,*,DOWN,NDIF +S 5100,500,5100,900,300,*,DOWN,NDIF +S 0,0,12000,0,300,*,RIGHT,PTIE +S 1200,1000,1200,1500,100,*,DOWN,POLY +S 2900,1000,2900,1500,100,*,DOWN,POLY +S 6000,1000,6000,1100,100,*,DOWN,POLY +S 6500,1000,6500,1100,100,*,DOWN,POLY +S 6500,3500,6500,3600,100,*,UP,POLY +S 8800,1000,8800,2000,100,*,UP,POLY +S 8200,1000,8200,1600,100,*,DOWN,POLY +S 7600,3000,8200,3000,100,*,RIGHT,POLY +S 8200,3000,8200,3600,100,*,DOWN,POLY +S 7100,2500,7100,3600,100,*,DOWN,POLY +S 7600,3500,7600,3600,100,*,DOWN,POLY +S 10000,2500,10000,3400,100,*,UP,POLY +S 4800,1100,4800,1600,100,*,UP,POLY +S 7600,1600,8200,1600,100,*,RIGHT,POLY +S 7100,1000,7100,2100,100,*,DOWN,POLY +S 7100,2000,8800,2000,100,ckr,RIGHT,POLY +S 10000,1100,10000,1500,100,*,DOWN,POLY +S 4800,2500,4800,3400,100,*,DOWN,POLY +S 3900,1600,4800,1600,100,*,LEFT,POLY +S 0,0,12000,0,400,vss,RIGHT,CALU1 +S 900,0,900,600,200,*,DOWN,ALU1 +S 3200,0,3200,600,200,*,DOWN,ALU1 +S 4500,0,4500,600,200,*,DOWN,ALU1 +S 11700,0,11700,1200,200,*,DOWN,ALU1 +S 7900,0,7900,600,200,*,DOWN,ALU1 +S 5700,0,5700,600,200,*,DOWN,ALU1 +S 2000,2000,2000,3900,200,*,DOWN,ALU1 +S 1500,1600,1500,3400,200,cmd,DOWN,CALU1 +S 1500,4400,2500,4400,200,*,LEFT,ALU1 +S 1500,3900,1500,4400,200,*,DOWN,ALU1 +S 400,3900,1500,3900,200,*,LEFT,ALU1 +S 0,5000,12000,5000,400,vdd,RIGHT,CALU1 +S 300,600,300,3900,200,*,DOWN,ALU1 +S 900,4400,900,5000,200,*,UP,ALU1 +S 7000,600,7000,1600,200,*,UP,ALU1 +S 6800,600,7000,600,200,*,RIGHT,ALU1 +S 7600,1100,8500,1100,200,*,RIGHT,ALU1 +S 8500,600,8500,1100,200,*,UP,ALU1 +S 8100,1100,8100,2400,200,*,UP,ALU1 +S 8100,2400,8500,2400,200,*,RIGHT,ALU1 +S 7700,3500,8500,3500,200,*,RIGHT,ALU1 +S 7000,3000,7600,3000,200,*,RIGHT,ALU1 +S 7000,3000,7000,4000,200,*,DOWN,ALU1 +S 7000,1600,7600,1600,200,*,RIGHT,ALU1 +S 11100,600,11100,4300,200,q,DOWN,CALU1 +S 11700,2800,11700,5000,200,*,DOWN,ALU1 +S 8500,2400,8500,4400,200,y,DOWN,ALU1 +S 9100,4000,9100,4400,200,*,DOWN,ALU1 +S 6800,4000,6800,4400,200,*,DOWN,ALU1 +S 6800,4000,7000,4000,200,*,RIGHT,ALU1 +S 3200,4400,3200,5000,200,*,UP,ALU1 +S 4400,1100,4400,3900,200,ck,DOWN,CALU1 +B 7600,3500,200,200,CONT_TURN8,* +B 6500,3500,200,200,CONT_TURN8,* +B 6000,3500,200,200,CONT_TURN8,* +B 7600,1100,200,200,CONT_TURN8,* +B 6500,1100,200,200,CONT_TURN8,* +B 6000,1100,200,200,CONT_TURN8,* +B 1700,1100,200,200,CONT_TURN8,* +B 1450,2500,1700,200,CONT_TURN8,* +B 6500,2200,200,600,CONT_TURN8,* +B 10950,2000,900,200,CONT_TURN8,* +B 9150,3000,500,200,CONT_TURN8,* +V 1500,2500,CONT_POLY,* +V 3200,3500,CONT_POLY,* +V 3200,1500,CONT_POLY,* +V 1700,1100,CONT_POLY,* +B 2700,600,200,200,CONT_TURN1,* +V 2700,2000,CONT_POLY,* +V 10500,1000,CONT_DIF_N,* +V 10500,3700,CONT_DIF_P,* +V 10500,3000,CONT_DIF_P,* +V 6500,2000,CONT_POLY,* +B 7100,2500,200,200,CONT_TURN1,* +V 6000,3500,CONT_POLY,* +B 7000,600,200,200,CONT_TURN1,* +B 9500,600,200,200,CONT_TURN1,* +B 8500,2400,200,200,CONT_TURN1,* +B 1500,3900,200,200,CONT_TURN1,* +B 7000,3000,200,200,CONT_TURN1,* +B 9000,1600,200,200,CONT_TURN1,* +B 8100,2400,200,200,CONT_TURN1,* +B 7000,4000,200,200,CONT_TURN1,* +B 2000,2000,200,200,CONT_TURN1,* +B 7000,1600,200,200,CONT_TURN1,* +B 8500,1100,200,200,CONT_TURN1,* +B 9500,4000,200,200,CONT_TURN1,* +B 2500,4400,200,200,CONT_TURN1,* +B 1500,4400,200,200,CONT_TURN1,* +V 5100,600,CONT_DIF_N,* +V 3900,600,CONT_DIF_N,* +V 10500,600,CONT_DIF_N,* +V 1000,3400,CONT_POLY,* +V 2500,3500,CONT_POLY,* +V 9000,3000,CONT_POLY,* +V 9000,3000,CONT_POLY,* +V 7900,4400,CONT_DIF_P,* +V 7900,4000,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 5700,4400,CONT_DIF_P,* +V 10600,2000,CONT_POLY,* +V 10000,1500,CONT_POLY,* +V 10000,2500,CONT_POLY,* +V 1000,1600,CONT_POLY,* +V 2000,3900,CONT_DIF_P,* +V 300,3900,CONT_DIF_P,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 900,4400,CONT_DIF_P,* +V 3200,4400,CONT_DIF_P,* +V 11700,2800,CONT_DIF_P,* +V 11100,3800,CONT_DIF_P,* +V 11700,3300,CONT_DIF_P,* +V 11700,3800,CONT_DIF_P,* +V 10500,4300,CONT_DIF_P,* +V 11700,4300,CONT_DIF_P,* +V 11100,3300,CONT_DIF_P,* +V 9100,4400,CONT_DIF_P,* +V 8500,4400,CONT_DIF_P,* +V 6800,4400,CONT_DIF_P,* +V 11100,4300,CONT_DIF_P,* +V 11100,2800,CONT_DIF_P,* +V 6000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 9100,4000,CONT_DIF_P,* +V 8500,4000,CONT_DIF_P,* +V 6800,4000,CONT_DIF_P,* +V 10000,5000,CONT_BODY_N,* +V 9500,5000,CONT_BODY_N,* +V 9000,5000,CONT_BODY_N,* +V 8500,5000,CONT_BODY_N,* +V 8000,5000,CONT_BODY_N,* +V 7500,5000,CONT_BODY_N,* +V 7000,5000,CONT_BODY_N,* +V 6500,5000,CONT_BODY_N,* +V 3900,4300,CONT_DIF_P,* +V 5100,4300,CONT_DIF_P,* +V 5100,3800,CONT_DIF_P,* +V 4500,4400,CONT_DIF_P,* +V 12000,5000,CONT_BODY_N,* +V 11500,5000,CONT_BODY_N,* +V 11000,5000,CONT_BODY_N,* +V 10500,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3900,3800,CONT_DIF_P,* +V 900,600,CONT_DIF_N,* +V 2000,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 7900,600,CONT_DIF_N,* +V 6800,600,CONT_DIF_N,* +V 5700,600,CONT_DIF_N,* +V 11100,600,CONT_DIF_N,* +V 11700,600,CONT_DIF_N,* +V 9100,600,CONT_DIF_N,* +V 11100,1200,CONT_DIF_N,* +V 11700,1200,CONT_DIF_N,* +V 8500,600,CONT_DIF_N,* +V 3200,600,CONT_DIF_N,* +V 4500,600,CONT_DIF_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 9500,0,CONT_BODY_P,* +V 9000,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 6500,0,CONT_BODY_P,* +V 7000,0,CONT_BODY_P,* +V 8000,0,CONT_BODY_P,* +V 7500,0,CONT_BODY_P,* +V 8500,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 12000,0,CONT_BODY_P,* +V 11000,0,CONT_BODY_P,* +V 11500,0,CONT_BODY_P,* +V 10500,0,CONT_BODY_P,* +V 10000,0,CONT_BODY_P,* +V 6500,3500,CONT_POLY,* +V 8800,1600,CONT_POLY,* +V 7600,1100,CONT_POLY,* +V 6500,1100,CONT_POLY,* +V 6000,1100,CONT_POLY,* +V 7600,1600,CONT_POLY,* +V 7100,2100,CONT_POLY,* +V 7600,3500,CONT_POLY,* +V 7600,3000,CONT_POLY,* +V 6000,2000,CONT_POLY,* +V 3900,1500,CONT_POLY,* +V 5200,1500,CONT_POLY,* +V 4400,3300,CONT_POLY,* +V 3900,2500,CONT_POLY,* +V 4400,1200,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/sff2_x4.vbe b/pdks/symbolic/lsxlib/cells/sff2_x4.vbe new file mode 100644 index 000000000..59eaa6446 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/sff2_x4.vbe @@ -0,0 +1,51 @@ +ENTITY sff2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd : NATURAL := 16; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 7; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_cmd_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thr_cmd_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT tsf_cmd_ck : NATURAL := 833; + CONSTANT tsf_i0_ck : NATURAL := 764; + CONSTANT tsf_i1_ck : NATURAL := 764; + CONSTANT tsr_cmd_ck : NATURAL := 770; + CONSTANT tsr_i0_ck : NATURAL := 666; + CONSTANT tsr_i1_ck : NATURAL := 666; + CONSTANT transistors : NATURAL := 34 +); +PORT ( + ck : in BIT; + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff2_x4; + +ARCHITECTURE VBE OF sff2_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff2_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd))); + END BLOCK label0; + + q <= sff_m after 2000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/sff3_x4.ap b/pdks/symbolic/lsxlib/cells/sff3_x4.ap new file mode 100644 index 000000000..914389be7 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/sff3_x4.ap @@ -0,0 +1,424 @@ +V ALLIANCE : 6 +H sff3_x4,P, 5/ 8/2024,100 +A 0,0,13500,5000 +S 8800,2000,8800,2100,200,*,DOWN,POLY2 +S 8200,1900,8200,2500,200,*,UP,POLY2 +S 6700,2500,11100,2500,100,*,RIGHT,POLY +S 4500,2100,4600,2100,200,*,LEFT,POLY2 +S 4500,3400,4600,3400,200,*,LEFT,POLY2 +S 1600,1100,1700,1100,200,*,LEFT,POLY2 +S 2300,3400,2400,3400,200,*,LEFT,POLY2 +S 1700,3400,1900,3400,200,*,LEFT,POLY2 +S 10700,3000,11100,3000,200,*,LEFT,POLY2 +S 11600,2500,11700,2500,200,*,LEFT,POLY2 +S 11600,1500,11700,1500,200,*,LEFT,POLY2 +S 0,1100,13500,1100,1400,*,RIGHT,PWELL +S 5000,1200,5000,1700,300,*,DOWN,NDIF +S 300,600,300,1400,300,*,DOWN,NDIF +S 900,4400,3200,4400,200,*,RIGHT,ALU1 +S 2900,1000,2900,3500,100,*,DOWN,POLY +S 7200,1500,8800,1500,100,*,LEFT,POLY +S 3500,1100,4500,1100,200,*,RIGHT,ALU1 +S 3500,1100,3500,3400,200,*,DOWN,ALU1 +S 4000,1600,4000,3400,200,cmd0,UP,CALU1 +S 11100,1100,11100,2500,100,*,UP,POLY +S 7700,3500,7700,3600,100,*,UP,POLY +S 4600,3400,4600,3500,100,*,DOWN,POLY +S 4500,3400,4600,3400,200,*,RIGHT,POLY +S 1700,3400,1900,3400,200,*,LEFT,POLY +S 1900,1700,1900,3400,100,*,UP,POLY +S 1700,3400,1700,3500,100,*,DOWN,POLY +S 4100,2500,4100,3500,100,*,DOWN,POLY +S 4500,2100,4600,2100,200,*,RIGHT,POLY +S 4600,1000,4600,2100,100,*,UP,POLY +S 4500,2100,4500,3400,200,i0,DOWN,CALU1 +S 3500,2500,5300,2500,100,*,RIGHT,POLY +S 3500,1000,3500,2500,100,*,UP,POLY +S 11200,600,11200,4000,200,sff_s,UP,ALU1 +S 9300,1600,9300,3000,200,sff_m,DOWN,ALU1 +S 400,1100,400,3900,200,cmd1,DOWN,CALU1 +S 9300,1000,9300,1100,100,*,DOWN,POLY +S 0,0,13500,0,300,*,RIGHT,PTIE +S 0,0,13500,0,400,vss,RIGHT,CALU1 +S 2300,1600,2300,2400,200,i1,UP,CALU1 +S 1500,1600,1500,2400,200,i2,UP,CALU1 +S 10200,500,10200,800,300,*,DOWN,NDIF +S 11100,300,11100,1100,100,*,UP,NTRANS +S 7700,300,7700,1000,100,*,UP,NTRANS +S 8200,300,8200,1000,100,*,UP,NTRANS +S 9300,300,9300,1000,100,*,UP,NTRANS +S 2900,300,2900,1000,100,*,UP,NTRANS +S 1200,300,1200,1000,100,*,UP,NTRANS +S 7100,300,7100,1000,100,*,UP,NTRANS +S 4100,300,4100,1000,100,*,UP,NTRANS +S 600,1000,600,1600,100,*,DOWN,NTRANS +S 9900,300,9900,1000,100,*,UP,NTRANS +S 10500,300,10500,1000,100,*,UP,NTRANS +S 2400,300,2400,1000,100,*,UP,NTRANS +S 9900,3600,9900,4700,100,*,UP,PTRANS +S 11100,3400,11100,4700,100,*,DOWN,PTRANS +S 8800,300,8800,1000,100,*,UP,NTRANS +S 5300,1000,5300,1600,100,*,DOWN,NTRANS +S 4600,300,4600,1000,100,*,UP,NTRANS +S 3500,300,3500,1000,100,*,UP,NTRANS +S 5900,300,5900,1000,100,*,DOWN,NTRANS +S 1700,300,1700,1000,100,*,UP,NTRANS +S 2400,3500,2400,4700,100,*,UP,PTRANS +S 4600,3500,4600,4700,100,*,UP,PTRANS +S 1200,3500,1200,4700,100,*,UP,PTRANS +S 2900,3500,2900,4700,100,*,UP,PTRANS +S 5300,2500,5300,3400,100,*,UP,PTRANS +S 10500,3600,10500,4700,100,*,DOWN,PTRANS +S 9300,3600,9300,4700,100,*,DOWN,PTRANS +S 8800,3600,8800,4700,100,*,DOWN,PTRANS +S 12300,2400,12300,4700,100,*,DOWN,PTRANS +S 12900,2400,12900,4700,100,*,DOWN,PTRANS +S 1700,3500,1700,4700,100,*,UP,PTRANS +S 7700,3600,7700,4700,100,*,DOWN,PTRANS +S 8200,3600,8200,4700,100,*,DOWN,PTRANS +S 3500,3500,3500,4700,100,*,UP,PTRANS +S 4100,3500,4100,4700,100,*,UP,PTRANS +S 5900,3600,5900,4700,100,*,DOWN,PTRANS +S 7100,3600,7100,4700,100,*,DOWN,PTRANS +S 600,2400,600,3300,100,*,UP,PTRANS +S 11600,3400,11600,4700,100,*,DOWN,PTRANS +S 11600,300,11600,1100,100,*,UP,NTRANS +S 12900,300,12900,1600,100,*,UP,NTRANS +S 12300,300,12300,1600,100,*,UP,NTRANS +S 6800,500,6800,800,300,*,UP,NDIF +S 2100,500,2100,1200,300,*,UP,NDIF +S 5600,500,5600,1400,300,*,DOWN,NDIF +S 8500,500,8500,800,300,*,DOWN,NDIF +S 9600,500,9600,800,300,*,DOWN,NDIF +S 10800,500,10800,900,300,*,DOWN,NDIF +S 7400,500,7400,800,300,*,DOWN,NDIF +S 6200,500,6200,800,300,*,UP,NDIF +S 1500,500,1500,800,300,*,DOWN,NDIF +S 900,500,900,800,300,*,DOWN,NDIF +S 3800,500,3800,800,300,*,DOWN,NDIF +S 4900,500,4900,800,300,*,UP,NDIF +S 13200,500,13200,1400,300,*,DOWN,NDIF +S 12600,500,12600,1400,300,*,DOWN,NDIF +S 12000,500,12000,1200,300,*,UP,NDIF +S 3300,500,3300,800,300,*,DOWN,NDIF +S 900,1200,900,1400,300,*,DOWN,NDIF +S 4900,3700,4900,4500,300,*,UP,PDIF +S 5000,2700,5000,3200,300,*,UP,PDIF +S 1500,3700,1500,4500,300,*,DOWN,PDIF +S 10800,3600,10800,4500,300,*,UP,PDIF +S 9600,3800,9600,4500,300,*,DOWN,PDIF +S 7400,3800,7400,4500,300,*,UP,PDIF +S 900,2600,900,3100,300,*,UP,PDIF +S 300,2600,300,4500,300,*,UP,PDIF +S 8600,3800,8600,4500,300,*,UP,PDIF +S 6800,3300,6800,4500,300,*,DOWN,PDIF +S 5600,2700,5600,4500,300,*,UP,PDIF +S 900,3700,900,4500,300,*,UP,PDIF +S 3800,3700,3800,4500,300,*,UP,PDIF +S 3200,3700,3200,4500,300,*,UP,PDIF +S 13200,2600,13200,4500,300,*,DOWN,PDIF +S 2100,3700,2100,4500,300,*,UP,PDIF +S 10200,3800,10200,4500,300,*,DOWN,PDIF +S 12600,2600,12600,4500,300,*,DOWN,PDIF +S 12000,2800,12000,4500,300,*,DOWN,PDIF +S 6200,3300,6200,4500,300,*,DOWN,PDIF +S 0,5000,13500,5000,300,*,RIGHT,NTIE +S 2300,3400,2400,3400,200,*,RIGHT,POLY +S 4100,1000,4100,1100,100,*,DOWN,POLY +S 600,1600,600,2400,100,*,DOWN,POLY +S 400,2100,600,2100,200,*,RIGHT,POLY +S 8800,2000,10500,2000,100,ckr,RIGHT,POLY +S 9300,3000,9900,3000,100,*,RIGHT,POLY +S 9900,1000,9900,1600,100,*,DOWN,POLY +S 8800,2500,8800,3600,100,*,DOWN,POLY +S 1200,1000,1200,3500,100,*,DOWN,POLY +S 1600,1100,1700,1100,200,*,LEFT,POLY +S 1700,1000,1700,1100,100,*,DOWN,POLY +S 2300,2100,2800,2100,100,*,RIGHT,POLY +S 8200,3500,8200,3600,100,*,UP,POLY +S 8200,1900,8200,2500,200,*,UP,POLY +S 2400,3400,2400,3500,100,*,UP,POLY +S 10300,3600,10500,3600,100,*,RIGHT,POLY +S 11100,3000,11100,3400,100,*,DOWN,POLY +S 10700,3000,11100,3000,200,*,LEFT,POLY +S 10300,2500,10300,3600,100,*,DOWN,POLY +S 5300,1600,5300,2500,100,*,DOWN,POLY +S 6800,1000,7100,1000,100,*,LEFT,POLY +S 1900,1700,2400,1700,100,*,RIGHT,POLY +S 2400,1000,2400,1700,100,*,UP,POLY +S 6800,1000,6800,2500,100,*,UP,POLY +S 8200,1000,8200,1100,100,*,DOWN,POLY +S 7700,1000,7700,1100,100,*,DOWN,POLY +S 8800,1000,8800,2100,100,*,DOWN,POLY +S 9300,1600,9900,1600,100,*,RIGHT,POLY +S 7100,2500,7100,3600,100,*,DOWN,POLY +S 3500,3400,3500,3500,100,*,DOWN,POLY +S 10500,1000,10500,2000,100,*,UP,POLY +S 9300,3500,9300,3600,100,*,DOWN,POLY +S 9900,3000,9900,3600,100,*,DOWN,POLY +S 5900,1000,5900,3600,100,*,DOWN,POLY +S 12100,2000,12900,2000,200,*,RIGHT,POLY +S 11600,2500,11600,3400,100,*,UP,POLY +S 11600,1100,11600,1500,100,*,DOWN,POLY +S 12900,1600,12900,2400,100,*,DOWN,POLY +S 12300,1600,12300,2400,100,*,DOWN,POLY +S 9600,0,9600,600,200,*,DOWN,ALU1 +S 13200,0,13200,1200,200,*,DOWN,ALU1 +S 12000,0,12000,800,200,*,UP,ALU1 +S 7400,0,7400,600,200,*,DOWN,ALU1 +S 300,0,300,600,200,*,DOWN,ALU1 +S 3800,0,3800,600,200,*,UP,ALU1 +S 5600,0,5600,600,200,*,UP,ALU1 +S 0,5000,13500,5000,400,vdd,RIGHT,CALU1 +S 2300,2900,2300,3400,200,*,UP,ALU1 +S 300,4400,300,5000,200,*,UP,ALU1 +S 400,3400,1600,3400,200,*,LEFT,ALU1 +S 10700,1600,10700,3000,200,*,UP,ALU1 +S 8200,1200,8200,1900,200,*,DOWN,ALU1 +S 900,600,3200,600,200,*,RIGHT,ALU1 +S 900,2900,2300,2900,200,*,LEFT,ALU1 +S 4900,600,5000,600,200,*,LEFT,ALU1 +S 4500,1100,4500,1600,200,*,DOWN,ALU1 +S 5600,4400,5600,5000,200,*,UP,ALU1 +S 2100,1100,2800,1100,200,*,RIGHT,ALU1 +S 2800,1100,2800,3900,200,*,UP,ALU1 +S 5000,600,5000,1100,200,*,UP,ALU1 +S 2100,3900,7700,3900,200,*,RIGHT,ALU1 +S 10800,4000,11200,4000,200,*,LEFT,ALU1 +S 7700,1200,7700,3900,200,u,DOWN,ALU1 +S 10500,1600,10700,1600,200,*,RIGHT,ALU1 +S 8800,2100,8800,2400,200,*,UP,ALU1 +S 8700,600,8700,1600,200,*,UP,ALU1 +S 8500,600,8700,600,200,*,RIGHT,ALU1 +S 8200,2400,8200,3400,200,*,UP,ALU1 +S 8500,4000,8500,4400,200,*,DOWN,ALU1 +S 9300,1100,10200,1100,200,*,RIGHT,ALU1 +S 10200,600,10200,1100,200,*,UP,ALU1 +S 9600,4000,9600,5000,200,*,UP,ALU1 +S 8500,4000,8700,4000,200,*,RIGHT,ALU1 +S 8200,2400,8800,2400,200,*,RIGHT,ALU1 +S 9800,1100,9800,2400,200,*,UP,ALU1 +S 9800,2400,10200,2400,200,*,RIGHT,ALU1 +S 9400,3500,10200,3500,200,*,RIGHT,ALU1 +S 8700,3000,9300,3000,200,*,RIGHT,ALU1 +S 8700,3000,8700,4000,200,*,DOWN,ALU1 +S 10800,600,11200,600,200,*,RIGHT,ALU1 +S 8700,1600,9300,1600,200,*,RIGHT,ALU1 +S 900,1100,1600,1100,200,*,RIGHT,ALU1 +S 900,1100,900,2900,200,*,UP,ALU1 +S 7400,4400,7400,5000,200,*,UP,ALU1 +S 3800,4400,3800,5000,200,*,UP,ALU1 +S 10800,4000,10800,4400,200,*,DOWN,ALU1 +S 10200,2400,10200,4400,200,y,DOWN,ALU1 +S 12600,600,12600,4300,200,q,DOWN,CALU1 +S 13200,2800,13200,5000,200,*,DOWN,ALU1 +S 5000,1100,5500,1100,200,*,RIGHT,ALU1 +S 5500,1100,5500,3900,200,*,DOWN,ALU1 +S 5000,1600,5000,2900,200,*,DOWN,ALU1 +S 11700,1500,12600,1500,200,*,RIGHT,ALU1 +S 11200,2000,12100,2000,200,*,LEFT,ALU1 +S 4500,1600,5000,1600,200,*,LEFT,ALU1 +S 6200,1600,6700,1600,200,*,LEFT,ALU1 +S 6200,600,6200,1600,200,*,UP,ALU1 +S 6800,1100,7200,1100,200,*,LEFT,ALU1 +S 6800,600,6800,1100,200,*,DOWN,ALU1 +S 12000,3300,12000,5000,200,*,DOWN,ALU1 +S 6800,3400,7200,3400,200,*,LEFT,ALU1 +S 7200,1100,7200,3400,200,*,DOWN,ALU1 +S 6200,2100,6200,2400,200,ck,DOWN,CALU1 +S 6200,2900,6700,2900,200,*,RIGHT,ALU1 +S 6200,2900,6200,3400,200,*,UP,ALU1 +S 6700,1600,6700,2900,200,*,DOWN,ALU1 +S 11700,2500,12600,2500,200,*,RIGHT,ALU1 +S 0,4000,13500,4000,1200,*,RIGHT,NWELL +S 0,3100,13500,3100,1200,*,RIGHT,NWELL +B 4100,1100,200,200,CONT_TURN8,* +B 1600,1100,200,200,CONT_TURN8,* +B 4500,2100,200,200,CONT_TURN8,* +B 7700,1100,200,200,CONT_TURN8,* +B 8200,1100,200,200,CONT_TURN8,* +B 9300,1100,200,200,CONT_TURN8,* +B 11700,2500,200,200,CONT_TURN8,* +B 11700,1500,200,200,CONT_TURN8,* +B 12450,2000,900,200,CONT_TURN8,* +B 9300,3500,200,200,CONT_TURN8,* +B 8200,3500,200,200,CONT_TURN8,* +B 7700,3500,200,200,CONT_TURN8,* +B 4500,3400,200,200,CONT_TURN8,* +B 3500,3400,200,200,CONT_TURN8,* +B 2550,2100,700,200,CONT_TURN8,* +B 2300,3400,200,200,CONT_TURN8,* +B 1750,3400,300,200,CONT_TURN8,* +B 450,2100,300,200,CONT_TURN8,* +B 10850,3000,500,200,CONT_TURN8,* +B 6100,2300,400,200,CONT_TURN8,* +B 1400,2100,400,200,CONT_TURN8,* +V 3500,3400,CONT_POLY,* +B 3500,1100,200,200,CONT_TURN1,* +V 4000,2500,CONT_POLY,* +V 7700,3500,CONT_POLY,* +V 4500,3400,CONT_POLY,* +V 1700,3400,CONT_POLY,* +V 4500,2100,CONT_POLY,* +B 10200,2400,200,200,CONT_TURN1,* +B 9800,2400,200,200,CONT_TURN1,* +B 8800,2400,200,200,CONT_TURN1,* +B 8200,2400,200,200,CONT_TURN1,* +B 11200,600,200,200,CONT_TURN1,* +B 11200,4000,200,200,CONT_TURN1,* +B 10700,1600,200,200,CONT_TURN1,* +B 10200,1100,200,200,CONT_TURN1,* +B 8700,600,200,200,CONT_TURN1,* +B 8700,1600,200,200,CONT_TURN1,* +B 8700,3000,200,200,CONT_TURN1,* +B 8700,4000,200,200,CONT_TURN1,* +B 7700,3900,200,200,CONT_TURN1,* +B 7200,3400,200,200,CONT_TURN1,* +B 7200,1100,200,200,CONT_TURN1,* +B 6800,1100,200,200,CONT_TURN1,* +B 6200,1600,200,200,CONT_TURN1,* +B 6700,1600,200,200,CONT_TURN1,* +B 6700,2900,200,200,CONT_TURN1,* +B 6200,2900,200,200,CONT_TURN1,* +B 4500,1600,200,200,CONT_TURN1,* +B 4500,1100,200,200,CONT_TURN1,* +B 5000,600,200,200,CONT_TURN1,* +B 5000,1100,200,200,CONT_TURN1,* +B 5500,1100,200,200,CONT_TURN1,* +B 2800,1100,200,200,CONT_TURN1,* +B 900,1100,200,200,CONT_TURN1,* +B 2300,2900,200,200,CONT_TURN1,* +B 900,2900,200,200,CONT_TURN1,* +V 5000,1600,CONT_DIF_N,* +V 900,1300,CONT_DIF_N,* +V 6200,600,CONT_DIF_N,* +V 3800,600,CONT_DIF_N,* +V 2100,1100,CONT_DIF_N,* +V 3200,600,CONT_DIF_N,* +V 7400,600,CONT_DIF_N,* +V 8500,600,CONT_DIF_N,* +V 6800,600,CONT_DIF_N,* +V 9600,600,CONT_DIF_N,* +V 4900,600,CONT_DIF_N,* +V 5600,600,CONT_DIF_N,* +V 10800,600,CONT_DIF_N,* +V 10200,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 12600,600,CONT_DIF_N,* +V 12600,1200,CONT_DIF_N,* +V 13200,1200,CONT_DIF_N,* +V 13200,600,CONT_DIF_N,* +V 12000,800,CONT_DIF_N,* +V 900,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 8500,4000,CONT_DIF_P,* +V 5600,4400,CONT_DIF_P,* +V 3800,4400,CONT_DIF_P,* +V 5000,2900,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 7400,4400,CONT_DIF_P,* +V 12600,3800,CONT_DIF_P,* +V 12000,4300,CONT_DIF_P,* +V 12600,4300,CONT_DIF_P,* +V 9600,4000,CONT_DIF_P,* +V 9600,4400,CONT_DIF_P,* +V 4900,3900,CONT_DIF_P,* +V 10200,4000,CONT_DIF_P,* +V 10800,4000,CONT_DIF_P,* +V 12600,3300,CONT_DIF_P,* +V 12000,3300,CONT_DIF_P,* +V 12000,3800,CONT_DIF_P,* +V 8500,4400,CONT_DIF_P,* +V 900,2700,CONT_DIF_P,* +V 3200,4400,CONT_DIF_P,* +V 10200,4400,CONT_DIF_P,* +V 10800,4400,CONT_DIF_P,* +V 6800,3400,CONT_DIF_P,* +V 12600,2800,CONT_DIF_P,* +V 13200,3800,CONT_DIF_P,* +V 13200,2800,CONT_DIF_P,* +V 13200,3300,CONT_DIF_P,* +V 13200,4300,CONT_DIF_P,* +V 6200,3400,CONT_DIF_P,* +V 0,5000,CONT_BODY_N,* +V 8000,5000,CONT_BODY_N,* +V 9000,5000,CONT_BODY_N,* +V 9500,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 13000,5000,CONT_BODY_N,* +V 13500,5000,CONT_BODY_N,* +V 8500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 6500,5000,CONT_BODY_N,* +V 7000,5000,CONT_BODY_N,* +V 7500,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 10000,5000,CONT_BODY_N,* +V 10500,5000,CONT_BODY_N,* +V 11000,5000,CONT_BODY_N,* +V 11500,5000,CONT_BODY_N,* +V 12000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 12500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 7500,0,CONT_BODY_P,* +V 7000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 9500,0,CONT_BODY_P,* +V 10000,0,CONT_BODY_P,* +V 9000,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 8500,0,CONT_BODY_P,* +V 8000,0,CONT_BODY_P,* +V 11000,0,CONT_BODY_P,* +V 11500,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 6500,0,CONT_BODY_P,* +V 13500,0,CONT_BODY_P,* +V 13000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 10500,0,CONT_BODY_P,* +V 12000,0,CONT_BODY_P,* +V 12500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 9300,1100,CONT_POLY,* +V 2300,3400,CONT_POLY,* +V 10700,3000,CONT_POLY,* +V 400,2100,CONT_POLY,* +V 8200,1900,CONT_POLY,* +V 2300,2100,CONT_POLY,* +V 7200,1500,CONT_POLY,* +V 8200,1100,CONT_POLY,* +V 1500,2100,CONT_POLY,* +V 4100,1100,CONT_POLY,* +V 1600,1100,CONT_POLY,* +V 8800,2100,CONT_POLY,* +V 9300,1600,CONT_POLY,* +V 10700,3000,CONT_POLY,* +V 7700,1100,CONT_POLY,* +V 10500,1600,CONT_POLY,* +V 11700,1500,CONT_POLY,* +V 12100,2000,CONT_POLY,* +V 6700,2500,CONT_POLY,* +V 6200,2300,CONT_POLY,* +V 8200,3500,CONT_POLY,* +V 9300,3000,CONT_POLY,* +V 9300,3500,CONT_POLY,* +V 11700,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/sff3_x4.vbe b/pdks/symbolic/lsxlib/cells/sff3_x4.vbe new file mode 100644 index 000000000..a1953ab9f --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/sff3_x4.vbe @@ -0,0 +1,65 @@ +ENTITY sff3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 890; + CONSTANT rup_ck_q : NATURAL := 810; + CONSTANT taf_ck_q : NATURAL := 600; + CONSTANT tar_ck_q : NATURAL := 600; + CONSTANT thf_ck_q : NATURAL := 0; + CONSTANT thf_cmd0_ck : NATURAL := 0; + CONSTANT thf_cmd1_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thf_i2_ck : NATURAL := 0; + CONSTANT thr_ck_q : NATURAL := 0; + CONSTANT thr_cmd0_ck : NATURAL := 0; + CONSTANT thr_cmd1_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT thr_i2_ck : NATURAL := 0; + CONSTANT tsf_cmd0_ck : NATURAL := 1200; + CONSTANT tsf_cmd1_ck : NATURAL := 1200; + CONSTANT tsf_i0_ck : NATURAL := 1200; + CONSTANT tsf_i1_ck : NATURAL := 1200; + CONSTANT tsf_i2_ck : NATURAL := 1200; + CONSTANT tsr_cmd0_ck : NATURAL := 1100; + CONSTANT tsr_cmd1_ck : NATURAL := 1100; + CONSTANT tsr_i0_ck : NATURAL := 850; + CONSTANT tsr_i1_ck : NATURAL := 950; + CONSTANT tsr_i2_ck : NATURAL := 950; + CONSTANT transistors : NATURAL := 42 +); +PORT ( + ck : in BIT; + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff3_x4; + +ARCHITECTURE behaviour_data_flow OF sff3_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff3_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2)))); + END BLOCK label0; + + q <= sff_m after 2400 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/tie_x0.ap b/pdks/symbolic/lsxlib/cells/tie_x0.ap new file mode 100644 index 000000000..df2a5d588 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/tie_x0.ap @@ -0,0 +1,15 @@ +V ALLIANCE : 6 +H tie_x0,P,18/ 6/2024,100 +A 0,0,500,5000 +S 0,1100,500,1100,1400,*,RIGHT,PWELL +S 0,4000,500,4000,1200,*,RIGHT,NWELL +S 0,3100,500,3100,1200,*,RIGHT,NWELL +S 0,0,500,0,300,*,RIGHT,PTIE +S 0,0,500,0,400,vss,RIGHT,CALU1 +S 0,5000,500,5000,300,*,RIGHT,NTIE +S 0,5000,500,5000,400,vdd,RIGHT,CALU1 +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/tie_x0.vbe b/pdks/symbolic/lsxlib/cells/tie_x0.vbe new file mode 100644 index 000000000..938a45c77 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/tie_x0.vbe @@ -0,0 +1,18 @@ +ENTITY tie_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 500; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END tie_x0; + +ARCHITECTURE behaviour_data_flow OF tie_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on tie_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/lsxlib/cells/ts_x4.ap b/pdks/symbolic/lsxlib/cells/ts_x4.ap new file mode 100644 index 000000000..148116490 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ts_x4.ap @@ -0,0 +1,158 @@ +V ALLIANCE : 6 +H ts_x4,P, 5/ 8/2024,100 +A 0,0,5000,5000 +S 4200,2900,4400,2900,200,*,LEFT,POLY2 +S 1800,1300,1900,1300,200,*,LEFT,POLY2 +S 3400,1900,3400,2000,200,*,UP,POLY2 +S 3800,1600,4000,1600,200,*,LEFT,POLY2 +S 3400,2900,3800,2900,200,*,RIGHT,POLY2 +S 1800,2900,1900,2900,200,*,LEFT,POLY2 +S 0,1100,5000,1100,1400,*,RIGHT,PWELL +S 0,4000,5000,4000,1200,*,RIGHT,NWELL +S 0,3100,5000,3100,1200,*,RIGHT,NWELL +S 3500,3700,3500,4400,200,*,UP,ALU1 +S 4400,1100,4400,2000,100,*,DOWN,POLY +S 0,0,5000,0,400,vss,RIGHT,CALU1 +S 900,500,900,1400,300,*,UP,NDIF +S 1500,500,1500,1400,300,*,UP,NDIF +S 300,500,300,1400,300,*,UP,NDIF +S 2100,500,2100,900,300,*,UP,NDIF +S 3200,300,3200,1100,100,*,UP,NTRANS +S 4400,300,4400,1100,100,*,UP,NTRANS +S 4700,500,4700,900,300,*,UP,NDIF +S 2900,500,2900,900,300,*,UP,NDIF +S 4100,500,4100,900,300,*,UP,NDIF +S 3500,500,3500,900,300,*,UP,NDIF +S 600,300,600,1600,100,*,UP,NTRANS +S 1200,300,1200,1600,100,*,UP,NTRANS +S 1800,300,1800,1100,100,*,UP,NTRANS +S 3800,300,3800,1100,100,*,UP,NTRANS +S 300,2600,300,4500,300,*,UP,PDIF +S 2100,3600,2100,4500,300,*,UP,PDIF +S 1800,3400,1800,4700,100,*,UP,PTRANS +S 3200,3400,3200,4700,100,*,UP,PTRANS +S 1200,2400,1200,4700,100,*,UP,PTRANS +S 1500,2600,1500,4500,300,*,UP,PDIF +S 900,2600,900,4500,300,*,UP,PDIF +S 600,2400,600,4700,100,*,UP,PTRANS +S 4100,3600,4100,4400,300,*,UP,PDIF +S 2900,3600,2900,4500,300,*,UP,PDIF +S 3800,3400,3800,4700,100,*,UP,PTRANS +S 3500,3600,3500,4500,300,*,UP,PDIF +S 4400,3400,4400,4700,100,*,UP,PTRANS +S 4700,3600,4700,4500,300,*,UP,PDIF +S 0,5000,5000,5000,300,*,RIGHT,NTIE +S 0,0,5000,0,300,*,RIGHT,PTIE +S 3800,1100,3800,1600,100,*,DOWN,POLY +S 3800,1600,4000,1600,200,*,RIGHT,POLY +S 3400,2000,4400,2000,100,*,RIGHT,POLY +S 2400,3300,3200,3300,100,*,LEFT,POLY +S 3200,3300,3200,3400,100,*,DOWN,POLY +S 600,1600,600,1800,100,*,DOWN,POLY +S 2800,2400,4700,2400,200,*,LEFT,POLY +S 1200,2300,1200,2400,100,*,DOWN,POLY +S 600,2300,600,2400,100,*,DOWN,POLY +S 3800,2900,3800,3400,100,*,DOWN,POLY +S 1800,2900,1800,3600,100,*,DOWN,POLY +S 1800,2900,3800,2900,100,*,RIGHT,POLY +S 3400,1900,3400,2000,200,*,UP,POLY +S 1200,1600,1200,1800,100,*,DOWN,POLY +S 600,1800,2900,1800,200,*,RIGHT,POLY +S 600,2300,2900,2300,200,*,RIGHT,POLY +S 4400,2900,4400,3400,100,*,DOWN,POLY +S 4200,2900,4400,2900,200,*,RIGHT,POLY +S 1800,1100,1800,1300,100,*,UP,POLY +S 3200,1100,3200,1300,100,*,DOWN,POLY +S 1800,1300,1900,1300,200,*,LEFT,POLY +S 2400,1300,3200,1300,100,*,RIGHT,POLY +S 1500,0,1500,600,200,*,DOWN,ALU1 +S 300,0,300,1200,200,*,DOWN,ALU1 +S 3500,0,3500,600,200,*,UP,ALU1 +S 1500,1100,1500,3900,200,cmd,DOWN,CALU1 +S 3400,2000,3400,2800,200,*,DOWN,ALU1 +S 4100,600,4100,1100,200,*,DOWN,ALU1 +S 2900,1100,4100,1100,200,*,RIGHT,ALU1 +S 900,600,900,4400,200,q,DOWN,CALU1 +S 300,2800,300,5000,200,*,DOWN,ALU1 +S 2100,600,2400,600,200,*,RIGHT,ALU1 +S 4000,1600,4000,3400,200,i,DOWN,CALU1 +S 3500,3900,4700,3900,200,*,RIGHT,ALU1 +S 0,5000,5000,5000,400,vdd,RIGHT,CALU1 +S 1500,4400,1500,5000,200,*,UP,ALU1 +S 4700,600,4700,4400,200,*,DOWN,ALU1 +S 2900,600,2900,4400,200,*,DOWN,ALU1 +S 4100,4400,4100,5000,200,*,UP,ALU1 +S 4000,2900,4200,2900,200,*,LEFT,ALU1 +S 1500,1300,1900,1300,200,*,LEFT,ALU1 +S 2400,600,2400,3700,200,*,DOWN,ALU1 +S 2100,3700,2400,3700,200,*,RIGHT,ALU1 +S 2100,3700,2100,4400,200,*,DOWN,ALU1 +S 1500,2900,1900,2900,200,*,LEFT,ALU1 +B 1900,1300,200,200,CONT_TURN8,* +B 3950,1600,300,200,CONT_TURN8,* +B 3550,2900,500,200,CONT_TURN8,* +B 4250,2900,300,200,CONT_TURN8,* +B 2400,3700,200,200,CONT_TURN1,* +B 4100,1100,200,200,CONT_TURN1,* +B 2400,600,200,200,CONT_TURN1,* +V 2900,600,CONT_DIF_N,* +V 3500,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 1500,600,CONT_DIF_N,* +V 900,1200,CONT_DIF_N,* +V 300,1200,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 4100,600,CONT_DIF_N,* +V 4700,600,CONT_DIF_N,* +V 3500,3700,CONT_DIF_P,* +V 300,2800,CONT_DIF_P,* +V 900,3800,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 4100,4400,CONT_DIF_P,* +V 900,3300,CONT_DIF_P,* +V 900,2800,CONT_DIF_P,* +V 300,3300,CONT_DIF_P,* +V 300,3800,CONT_DIF_P,* +V 2100,4400,CONT_DIF_P,* +V 4700,3700,CONT_DIF_P,* +V 2900,3700,CONT_DIF_P,* +V 2100,3700,CONT_DIF_P,* +V 3500,4400,CONT_DIF_P,* +V 2900,4400,CONT_DIF_P,* +V 4700,4400,CONT_DIF_P,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3400,1900,CONT_POLY,* +V 2900,1800,CONT_POLY,* +V 4700,2400,CONT_POLY,* +V 2400,3300,CONT_POLY,* +V 4000,1600,CONT_POLY,* +V 4200,2900,CONT_POLY,* +V 1900,1300,CONT_POLY,* +V 2400,1300,CONT_POLY,* +V 1900,2900,CONT_POLY,* +V 3400,2900,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/ts_x4.vbe b/pdks/symbolic/lsxlib/cells/ts_x4.vbe new file mode 100644 index 000000000..25d28a499 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ts_x4.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphl_cmd_q : NATURAL := 409; + CONSTANT tpll_i_q : NATURAL := 444; + CONSTANT tphh_i_q : NATURAL := 475; + CONSTANT tphh_cmd_q : NATURAL := 492; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x4; + +ARCHITECTURE behaviour_data_flow OF ts_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x4" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1100 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/lsxlib/cells/ts_x8.ap b/pdks/symbolic/lsxlib/cells/ts_x8.ap new file mode 100644 index 000000000..9cf624782 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ts_x8.ap @@ -0,0 +1,191 @@ +V ALLIANCE : 6 +H ts_x8,P, 5/ 8/2024,100 +A 0,0,6500,5000 +S 3100,1300,3200,1300,200,*,LEFT,POLY2 +S 4700,1900,4700,2000,200,*,UP,POLY2 +S 5100,1600,5300,1600,200,*,LEFT,POLY2 +S 4700,2900,5100,2900,200,*,RIGHT,POLY2 +S 3100,2900,3200,2900,200,*,LEFT,POLY2 +S 0,1100,6500,1100,1400,*,RIGHT,PWELL +S 3100,2900,3100,3400,100,*,DOWN,POLY +S 5700,2900,5700,3300,100,*,DOWN,POLY +S 5100,2900,5100,3300,100,*,DOWN,POLY +S 5700,1200,5700,2000,100,*,DOWN,POLY +S 0,4000,6500,4000,1200,*,RIGHT,NWELL +S 0,3100,6500,3100,1200,*,RIGHT,NWELL +S 400,500,400,1400,300,*,UP,NDIF +S 1000,500,1000,1400,300,*,UP,NDIF +S 6000,500,6000,1000,300,*,UP,NDIF +S 4200,500,4200,1000,300,*,UP,NDIF +S 5400,500,5400,1000,300,*,UP,NDIF +S 4800,500,4800,1000,300,*,UP,NDIF +S 2800,500,2800,1400,300,*,UP,NDIF +S 2200,500,2200,1400,300,*,UP,NDIF +S 3400,500,3400,900,300,*,UP,NDIF +S 1600,500,1600,1400,300,*,UP,NDIF +S 700,300,700,1600,100,*,UP,NTRANS +S 1900,300,1900,1600,100,*,UP,NTRANS +S 2500,300,2500,1600,100,*,UP,NTRANS +S 3100,300,3100,1100,100,*,UP,NTRANS +S 4500,300,4500,1200,100,*,UP,NTRANS +S 5700,300,5700,1200,100,*,UP,NTRANS +S 5100,300,5100,1200,100,*,UP,NTRANS +S 1300,300,1300,1600,100,*,UP,NTRANS +S 1300,2400,1300,4700,100,*,UP,PTRANS +S 3400,3600,3400,4500,300,*,UP,PDIF +S 1600,2600,1600,4500,300,*,UP,PDIF +S 1900,2400,1900,4700,100,*,UP,PTRANS +S 1000,2600,1000,4500,300,*,UP,PDIF +S 400,2600,400,4500,300,*,UP,PDIF +S 700,2400,700,4700,100,*,UP,PTRANS +S 4500,3300,4500,4700,100,*,UP,PTRANS +S 2200,2600,2200,4500,300,*,UP,PDIF +S 2800,2600,2800,4500,300,*,UP,PDIF +S 2500,2400,2500,4700,100,*,UP,PTRANS +S 3100,3400,3100,4700,100,*,UP,PTRANS +S 4200,3500,4200,4500,300,*,UP,PDIF +S 5400,3500,5400,4400,300,*,UP,PDIF +S 5100,3300,5100,4700,100,*,UP,PTRANS +S 4800,3500,4800,4500,300,*,UP,PDIF +S 5700,3300,5700,4700,100,*,UP,PTRANS +S 6000,3500,6000,4500,300,*,UP,PDIF +S 0,5000,6500,5000,300,*,RIGHT,NTIE +S 0,0,6500,0,300,*,RIGHT,PTIE +S 700,2300,4200,2300,200,*,RIGHT,POLY +S 2500,2300,2500,2400,100,*,DOWN,POLY +S 1900,2300,1900,2400,100,*,DOWN,POLY +S 1300,1600,1300,1800,100,*,DOWN,POLY +S 700,1600,700,1800,100,*,DOWN,POLY +S 1300,2300,1300,2400,100,*,DOWN,POLY +S 700,2300,700,2400,100,*,DOWN,POLY +S 5500,2900,5700,2900,200,*,RIGHT,POLY +S 4100,2400,6000,2400,200,*,LEFT,POLY +S 3100,1300,3200,1300,200,*,LEFT,POLY +S 3100,2900,5100,2900,100,*,RIGHT,POLY +S 4700,1900,4700,2000,200,*,UP,POLY +S 700,1800,4200,1800,200,*,RIGHT,POLY +S 2500,1600,2500,1800,100,*,DOWN,POLY +S 1900,1600,1900,1800,100,*,DOWN,POLY +S 4500,1200,4500,1300,100,*,DOWN,POLY +S 5100,1200,5100,1600,100,*,DOWN,POLY +S 3700,1300,4500,1300,100,*,RIGHT,POLY +S 4700,2000,5700,2000,100,*,RIGHT,POLY +S 5100,1600,5300,1600,200,*,RIGHT,POLY +S 3100,1100,3100,1300,100,*,UP,POLY +S 3700,3300,4500,3300,100,*,LEFT,POLY +S 400,0,400,1200,200,*,DOWN,ALU1 +S 1600,0,1600,1200,200,*,DOWN,ALU1 +S 4800,0,4800,600,200,*,UP,ALU1 +S 2800,0,2800,600,200,*,DOWN,ALU1 +S 0,0,6500,0,400,vss,RIGHT,CALU1 +S 4200,600,4200,4400,200,*,DOWN,ALU1 +S 2800,2900,3200,2900,200,*,LEFT,ALU1 +S 5400,4400,5400,5000,200,*,UP,ALU1 +S 0,5000,6500,5000,400,vdd,RIGHT,CALU1 +S 4700,2000,4700,2800,200,*,DOWN,ALU1 +S 6000,600,6000,4400,200,*,DOWN,ALU1 +S 5400,600,5400,1100,200,*,DOWN,ALU1 +S 2800,1300,3200,1300,200,*,LEFT,ALU1 +S 1000,600,1000,4400,200,q,DOWN,CALU1 +S 3700,600,3700,3700,200,*,DOWN,ALU1 +S 3400,3700,3700,3700,200,*,RIGHT,ALU1 +S 3400,3700,3400,4400,200,*,DOWN,ALU1 +S 5300,2900,5500,2900,200,*,LEFT,ALU1 +S 2800,4400,2800,5000,200,*,UP,ALU1 +S 4800,3900,6000,3900,200,*,RIGHT,ALU1 +S 5300,1600,5300,3400,200,i,DOWN,CALU1 +S 3400,600,3700,600,200,*,RIGHT,ALU1 +S 1600,2800,1600,5000,200,*,DOWN,ALU1 +S 4200,1100,5400,1100,200,*,RIGHT,ALU1 +S 2800,1100,2800,3900,200,cmd,DOWN,CALU1 +S 2200,600,2200,4400,200,*,DOWN,ALU1 +S 1000,2100,2200,2100,200,*,RIGHT,ALU1 +S 400,2800,400,5000,200,*,UP,ALU1 +S 4800,3700,4800,4400,200,*,UP,ALU1 +B 3200,2900,200,200,CONT_TURN8,* +B 4850,2900,500,200,CONT_TURN8,* +B 5250,1600,300,200,CONT_TURN8,* +B 3200,1300,200,200,CONT_TURN8,* +B 5550,2900,300,200,CONT_TURN8,* +B 3700,600,200,200,CONT_TURN1,* +B 5400,1100,200,200,CONT_TURN1,* +B 3700,3700,200,200,CONT_TURN1,* +V 1000,600,CONT_DIF_N,* +V 4800,600,CONT_DIF_N,* +V 4200,600,CONT_DIF_N,* +V 3400,600,CONT_DIF_N,* +V 1600,1200,CONT_DIF_N,* +V 6000,600,CONT_DIF_N,* +V 5400,600,CONT_DIF_N,* +V 400,1200,CONT_DIF_N,* +V 2200,1200,CONT_DIF_N,* +V 2800,600,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 2200,600,CONT_DIF_N,* +V 1000,1200,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 1000,3300,CONT_DIF_P,* +V 400,3800,CONT_DIF_P,* +V 400,3300,CONT_DIF_P,* +V 1000,2800,CONT_DIF_P,* +V 6000,4400,CONT_DIF_P,* +V 5400,4400,CONT_DIF_P,* +V 2200,3300,CONT_DIF_P,* +V 400,4400,CONT_DIF_P,* +V 1000,4400,CONT_DIF_P,* +V 1000,3800,CONT_DIF_P,* +V 400,2800,CONT_DIF_P,* +V 2800,4400,CONT_DIF_P,* +V 1600,3300,CONT_DIF_P,* +V 1600,3800,CONT_DIF_P,* +V 3400,4400,CONT_DIF_P,* +V 6000,3700,CONT_DIF_P,* +V 4200,3700,CONT_DIF_P,* +V 4800,3700,CONT_DIF_P,* +V 4800,4400,CONT_DIF_P,* +V 4200,4400,CONT_DIF_P,* +V 3400,3700,CONT_DIF_P,* +V 1600,2800,CONT_DIF_P,* +V 2200,3800,CONT_DIF_P,* +V 2200,4400,CONT_DIF_P,* +V 1600,4400,CONT_DIF_P,* +V 2200,2800,CONT_DIF_P,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 6500,5000,CONT_BODY_N,* +V 6000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 6500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 5300,1600,CONT_POLY,* +V 4700,1900,CONT_POLY,* +V 3200,2900,CONT_POLY,* +V 4700,2900,CONT_POLY,* +V 3700,3300,CONT_POLY,* +V 3200,1300,CONT_POLY,* +V 5500,2900,CONT_POLY,* +V 3700,1300,CONT_POLY,* +V 4200,1800,CONT_POLY,* +V 6000,2400,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/ts_x8.vbe b/pdks/symbolic/lsxlib/cells/ts_x8.vbe new file mode 100644 index 000000000..c92f94f59 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/ts_x8.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 400; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_cmd_q : NATURAL := 450; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphl_cmd_q : NATURAL := 466; + CONSTANT tpll_i_q : NATURAL := 569; + CONSTANT tphh_i_q : NATURAL := 613; + CONSTANT tphh_cmd_q : NATURAL := 626; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x8; + +ARCHITECTURE behaviour_data_flow OF ts_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x8" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1200 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/lsxlib/cells/xr2_x1.ap b/pdks/symbolic/lsxlib/cells/xr2_x1.ap new file mode 100644 index 000000000..35f795262 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/xr2_x1.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H xr2_x1,P, 5/ 8/2024,100 +A 0,0,4500,5000 +S 3000,2000,3000,2100,200,*,UP,POLY2 +S 3500,1600,3600,1600,200,*,LEFT,POLY2 +S 3500,2400,3600,2400,200,*,LEFT,POLY2 +S 1800,1600,2000,1600,200,*,LEFT,POLY2 +S 1800,2400,2000,2400,200,*,LEFT,POLY2 +S 0,1100,4500,1100,1400,*,RIGHT,PWELL +S 2700,2800,2700,4400,200,*,DOWN,ALU1 +S 1500,3400,1500,4400,200,*,UP,ALU1 +S 1500,2900,2100,2900,200,*,LEFT,ALU1 +S 2100,2900,2100,3800,200,q,DOWN,CALU1 +S 3000,1500,3000,2000,100,*,DOWN,POLY +S 2400,1500,2400,2500,100,*,DOWN,POLY +S 0,5000,4500,5000,300,*,RIGHT,NTIE +S 4000,600,4000,4400,200,*,UP,ALU1 +S 300,600,300,4400,200,*,UP,ALU1 +S 3300,4400,3300,5000,200,*,UP,ALU1 +S 900,4400,900,5000,200,*,UP,ALU1 +S 3600,2400,3600,3400,100,*,DOWN,POLY +S 3600,1100,3600,1600,100,*,DOWN,POLY +S 600,2500,600,3400,100,*,UP,POLY +S 600,1100,600,1500,100,*,DOWN,POLY +S 1500,4400,2700,4400,200,*,RIGHT,ALU1 +S 3600,300,3600,1100,100,*,DOWN,NTRANS +S 4000,500,4000,900,300,*,UP,NDIF +S 600,300,600,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 300,3600,300,4500,300,*,UP,PDIF +S 600,3400,600,4700,100,*,UP,PTRANS +S 4000,3600,4000,4500,300,*,DOWN,PDIF +S 3600,3400,3600,4700,100,*,UP,PTRANS +S 1500,600,2100,600,200,*,LEFT,ALU1 +S 1500,1100,2100,1100,200,*,RIGHT,ALU1 +S 2000,1600,3500,1600,200,*,RIGHT,ALU1 +S 3500,1100,3500,3800,200,i1,DOWN,CALU1 +S 1500,600,1500,2900,200,q,DOWN,CALU1 +S 1800,1600,2000,1600,200,*,LEFT,POLY +S 1800,1500,1800,1600,100,*,UP,POLY +S 1800,2400,1800,2500,100,*,UP,POLY +S 1800,2400,2000,2400,200,*,LEFT,POLY +S 1000,1100,1000,3800,200,i0,DOWN,CALU1 +S 2000,2100,3000,2100,200,*,RIGHT,ALU1 +S 2000,2100,2000,2400,200,*,DOWN,ALU1 +S 3000,2500,3600,2500,100,*,RIGHT,POLY +S 600,2500,1200,2500,100,*,RIGHT,POLY +S 3000,2500,3000,4700,100,*,UP,PTRANS +S 2700,2700,2700,4500,300,*,DOWN,PDIF +S 2400,2500,2400,4700,100,*,UP,PTRANS +S 2100,2700,2100,4500,300,*,DOWN,PDIF +S 900,2700,900,4500,300,*,DOWN,PDIF +S 1200,2500,1200,4700,100,*,UP,PTRANS +S 1800,2500,1800,4700,100,*,UP,PTRANS +S 3300,2700,3300,4500,300,*,DOWN,PDIF +S 1500,2700,1500,4500,300,*,DOWN,PDIF +S 3300,0,3300,600,200,*,DOWN,ALU1 +S 900,0,900,600,200,*,DOWN,ALU1 +S 3500,1600,3600,1600,200,*,RIGHT,POLY +S 600,1500,1200,1500,100,*,RIGHT,POLY +S 900,600,900,1300,300,*,UP,NDIF +S 3300,600,3300,1300,300,*,UP,NDIF +S 3000,300,3000,1500,100,*,DOWN,NTRANS +S 2400,300,2400,1500,100,*,DOWN,NTRANS +S 1800,300,1800,1500,100,*,DOWN,NTRANS +S 1200,300,1200,1500,100,*,DOWN,NTRANS +S 2700,500,2700,1300,300,*,UP,NDIF +S 2100,500,2100,1300,300,*,UP,NDIF +S 1500,500,1500,1300,300,*,UP,NDIF +S 0,0,4500,0,300,*,RIGHT,PTIE +S 0,4000,4500,4000,1200,*,RIGHT,NWELL +S 0,3100,4500,3100,1200,*,RIGHT,NWELL +S 0,5000,4500,5000,400,vdd,RIGHT,CALU1 +S 0,0,4500,0,400,vss,RIGHT,CALU1 +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +B 3500,1600,200,200,CONT_TURN8,* +B 1950,1600,300,200,CONT_TURN8,* +B 1950,2400,300,200,CONT_TURN8,* +B 2000,2100,200,200,CONT_TURN1,* +V 4000,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 300,3700,CONT_DIF_P,* +V 4000,3700,CONT_DIF_P,* +V 4000,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 2700,4400,CONT_DIF_P,* +V 2100,600,CONT_DIF_N,* +V 2100,1100,CONT_DIF_N,* +V 3000,2100,CONT_POLY,* +V 1500,3400,CONT_DIF_P,* +V 2100,2900,CONT_DIF_P,* +V 4500,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_BODY_N,* +V 1500,3800,CONT_DIF_P,* +V 2100,3800,CONT_DIF_P,* +V 1000,2400,CONT_POLY,* +V 2000,2400,CONT_POLY,* +V 3500,2400,CONT_POLY,* +V 1000,1600,CONT_POLY,* +V 2000,1600,CONT_POLY,* +V 3500,1600,CONT_POLY,* +V 3300,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 2700,3800,CONT_DIF_P,* +V 2700,2800,CONT_DIF_P,* +V 2700,3300,CONT_DIF_P,* +V 2100,3300,CONT_DIF_P,* +V 4500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 4000,2000,CONT_POLY,* +V 300,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/xr2_x1.vbe b/pdks/symbolic/lsxlib/cells/xr2_x1.vbe new file mode 100644 index 000000000..925f29ad5 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/xr2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY xr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i1_q : NATURAL := 261; + CONSTANT tphl_i0_q : NATURAL := 292; + CONSTANT tplh_i0_q : NATURAL := 293; + CONSTANT tphh_i0_q : NATURAL := 366; + CONSTANT tphl_i1_q : NATURAL := 377; + CONSTANT tpll_i1_q : NATURAL := 388; + CONSTANT tpll_i0_q : NATURAL := 389; + CONSTANT tphh_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x1; + +ARCHITECTURE behaviour_data_flow OF xr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x1" + SEVERITY WARNING; + q <= (i0 xor i1) after 1000 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/xr2_x4.ap b/pdks/symbolic/lsxlib/cells/xr2_x4.ap new file mode 100644 index 000000000..b2e195d8b --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/xr2_x4.ap @@ -0,0 +1,186 @@ +V ALLIANCE : 6 +H xr2_x4,P, 5/ 8/2024,100 +A 0,0,6000,5000 +S 2000,1500,2000,1600,200,*,DOWN,POLY2 +S 1800,2400,2000,2400,200,*,LEFT,POLY2 +S 1800,1600,2000,1600,200,*,LEFT,POLY2 +S 2000,2400,2000,2500,200,*,UP,POLY2 +S 2900,1900,2900,2000,200,*,DOWN,POLY2 +S 3400,2400,3400,2500,200,*,UP,POLY2 +S 0,1100,6000,1100,1400,*,RIGHT,PWELL +S 3000,2000,3000,2500,100,*,DOWN,POLY +S 2400,1500,2400,2500,100,*,DOWN,POLY +S 5100,600,5100,4400,200,q,UP,CALU1 +S 2100,2900,2100,3900,200,*,DOWN,ALU1 +S 1500,1100,1500,2900,200,*,DOWN,ALU1 +S 1500,3400,1500,4400,200,*,DOWN,ALU1 +S 3900,900,3900,1700,300,*,DOWN,NDIF +S 3600,700,3600,1500,100,*,DOWN,NTRANS +S 1500,1100,4400,1100,200,*,LEFT,ALU1 +S 3400,1600,3400,3900,200,i1,DOWN,CALU1 +S 3900,1600,3900,4400,200,*,DOWN,ALU1 +S 0,0,6000,0,300,*,RIGHT,PTIE +S 0,0,6000,0,400,vss,RIGHT,CALU1 +S 0,4000,6000,4000,1200,*,RIGHT,NWELL +S 0,3100,6000,3100,1200,*,RIGHT,NWELL +S 0,5000,6000,5000,300,*,RIGHT,NTIE +S 0,5000,6000,5000,400,vdd,RIGHT,CALU1 +S 4800,2400,4800,4700,100,*,UP,PTRANS +S 4500,2600,4500,4500,300,*,DOWN,PDIF +S 5400,2400,5400,4700,100,*,UP,PTRANS +S 5700,2600,5700,4500,300,*,DOWN,PDIF +S 5100,2600,5100,4500,300,*,DOWN,PDIF +S 4800,300,4800,1600,100,*,DOWN,NTRANS +S 5400,300,5400,1600,100,*,DOWN,NTRANS +S 4500,500,4500,1400,300,*,DOWN,NDIF +S 5700,500,5700,1400,300,*,UP,NDIF +S 5100,500,5100,1400,300,*,UP,NDIF +S 4800,1600,4800,2400,100,*,DOWN,POLY +S 5400,1600,5400,2400,100,*,DOWN,POLY +S 4400,2000,5400,2000,200,*,RIGHT,POLY +S 4500,0,4500,600,200,*,DOWN,ALU1 +S 5700,0,5700,1100,200,*,DOWN,ALU1 +S 4400,1100,4400,2000,200,*,UP,ALU1 +S 4500,2700,4500,5000,200,*,UP,ALU1 +S 5700,2700,5700,5000,200,*,UP,ALU1 +S 900,2700,900,4500,300,*,UP,PDIF +S 1200,2500,1200,4700,100,*,UP,PTRANS +S 3600,3400,3600,4700,100,*,UP,PTRANS +S 600,3400,600,4700,100,*,UP,PTRANS +S 300,3600,300,4500,300,*,UP,PDIF +S 3900,3600,3900,4500,300,*,DOWN,PDIF +S 3300,2700,3300,4500,300,*,DOWN,PDIF +S 2700,2700,2700,4500,300,*,DOWN,PDIF +S 3000,2500,3000,4700,100,*,UP,PTRANS +S 1500,2700,1500,4500,300,*,DOWN,PDIF +S 2100,2700,2100,4500,300,*,DOWN,PDIF +S 2400,2500,2400,4700,100,*,UP,PTRANS +S 1800,2500,1800,4700,100,*,UP,PTRANS +S 3000,300,3000,1500,100,*,DOWN,NTRANS +S 2400,300,2400,1500,100,*,DOWN,NTRANS +S 1800,300,1800,1500,100,*,DOWN,NTRANS +S 1200,300,1200,1500,100,*,DOWN,NTRANS +S 600,300,600,1100,100,*,DOWN,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 900,500,900,1300,300,*,DOWN,NDIF +S 1500,500,1500,1300,300,*,UP,NDIF +S 3300,500,3300,1300,300,*,UP,NDIF +S 2700,500,2700,1300,300,*,UP,NDIF +S 2100,500,2100,1300,300,*,UP,NDIF +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 600,2500,600,3400,100,*,UP,POLY +S 600,2500,1200,2500,100,*,LEFT,POLY +S 600,1100,600,1500,100,*,DOWN,POLY +S 600,1500,1200,1500,100,*,LEFT,POLY +S 2000,2400,2000,2500,200,*,DOWN,POLY +S 1800,2500,2000,2500,100,*,RIGHT,POLY +S 3000,1500,3600,1500,100,*,RIGHT,POLY +S 2000,1500,2000,1600,200,*,UP,POLY +S 3400,2400,3400,2500,200,*,DOWN,POLY +S 3400,2500,3600,2500,100,*,LEFT,POLY +S 3600,2500,3600,3400,100,*,DOWN,POLY +S 2900,2000,3900,2000,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 2900,1900,2900,2000,200,*,UP,POLY +S 3400,1500,3400,1600,200,*,UP,POLY +S 3300,0,3300,600,200,*,UP,ALU1 +S 900,0,900,600,200,*,UP,ALU1 +S 3300,4400,3300,5000,200,*,UP,ALU1 +S 900,4400,900,5000,200,*,UP,ALU1 +S 1500,2900,2100,2900,200,*,LEFT,ALU1 +S 1500,4400,2700,4400,200,*,RIGHT,ALU1 +S 2100,600,2100,1100,200,*,DOWN,ALU1 +S 300,600,300,4400,200,*,DOWN,ALU1 +S 2000,2400,3400,2400,200,*,RIGHT,ALU1 +S 2000,1600,2000,1900,200,*,DOWN,ALU1 +S 2000,1900,2900,1900,200,*,LEFT,ALU1 +S 800,1100,800,3900,200,i0,DOWN,CALU1 +S 2700,2900,2700,4400,200,*,UP,ALU1 +B 4850,2000,1100,200,CONT_TURN8,* +B 800,2400,200,200,CONT_TURN8,* +B 800,1600,200,200,CONT_TURN8,* +B 3400,1600,200,200,CONT_TURN8,* +B 2900,1900,200,200,CONT_TURN8,* +B 3400,2400,200,200,CONT_TURN8,* +B 1950,2400,300,200,CONT_TURN8,* +B 1950,1600,300,200,CONT_TURN8,* +V 1500,3400,CONT_DIF_P,* +V 1500,3900,CONT_DIF_P,* +V 1500,4400,CONT_DIF_P,* +B 1500,1100,200,200,CONT_TURN1,* +B 1500,2900,200,200,CONT_TURN1,* +B 2000,1900,200,200,CONT_TURN1,* +B 4400,1100,200,200,CONT_TURN1,* +V 3900,1600,CONT_DIF_N,* +V 5100,3300,CONT_DIF_P,* +V 5100,2700,CONT_DIF_P,* +V 4500,5000,CONT_BODY_N,* +V 4500,3300,CONT_DIF_P,* +V 4500,2700,CONT_DIF_P,* +V 5700,2700,CONT_DIF_P,* +V 5700,3300,CONT_DIF_P,* +V 5700,3900,CONT_DIF_P,* +V 5700,4400,CONT_DIF_P,* +V 5100,4400,CONT_DIF_P,* +V 5100,3900,CONT_DIF_P,* +V 6000,5000,CONT_BODY_N,* +V 5500,5000,CONT_BODY_N,* +V 5000,5000,CONT_BODY_N,* +V 4500,4400,CONT_DIF_P,* +V 4500,3900,CONT_DIF_P,* +V 4500,600,CONT_DIF_N,* +V 5700,600,CONT_DIF_N,* +V 5700,1100,CONT_DIF_N,* +V 5100,600,CONT_DIF_N,* +V 5100,1100,CONT_DIF_N,* +V 4500,0,CONT_BODY_P,* +V 5500,0,CONT_BODY_P,* +V 6000,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 4400,2000,CONT_POLY,* +V 2700,4400,CONT_DIF_P,* +V 300,4400,CONT_DIF_P,* +V 3300,4400,CONT_DIF_P,* +V 900,4400,CONT_DIF_P,* +V 300,3800,CONT_DIF_P,* +V 2100,2900,CONT_DIF_P,* +V 2700,3400,CONT_DIF_P,* +V 2700,2900,CONT_DIF_P,* +V 2100,3900,CONT_DIF_P,* +V 2700,3900,CONT_DIF_P,* +V 3900,3800,CONT_DIF_P,* +V 3900,4400,CONT_DIF_P,* +V 2100,3400,CONT_DIF_P,* +V 3300,600,CONT_DIF_N,* +V 2100,1100,CONT_DIF_N,* +V 2100,600,CONT_DIF_N,* +V 300,600,CONT_DIF_N,* +V 900,600,CONT_DIF_N,* +V 300,2000,CONT_POLY,* +V 2900,1900,CONT_POLY,* +V 3400,2400,CONT_POLY,* +V 3400,1600,CONT_POLY,* +V 800,2400,CONT_POLY,* +V 800,1600,CONT_POLY,* +V 2000,2400,CONT_POLY,* +V 2000,1600,CONT_POLY,* +V 3900,2000,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 2000,5000,CONT_BODY_N,* +V 2500,5000,CONT_BODY_N,* +V 3000,5000,CONT_BODY_N,* +V 4000,5000,CONT_BODY_N,* +V 3500,5000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 2500,0,CONT_BODY_P,* +V 4000,0,CONT_BODY_P,* +V 3500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/xr2_x4.vbe b/pdks/symbolic/lsxlib/cells/xr2_x4.vbe new file mode 100644 index 000000000..7e2da9edb --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/xr2_x4.vbe @@ -0,0 +1,36 @@ +ENTITY xr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 357; + CONSTANT tphh_i0_q : NATURAL := 476; + CONSTANT tpll_i0_q : NATURAL := 480; + CONSTANT tphl_i0_q : NATURAL := 521; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphl_i1_q : NATURAL := 541; + CONSTANT tplh_i0_q : NATURAL := 560; + CONSTANT tplh_i1_q : NATURAL := 657; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x4; + +ARCHITECTURE behaviour_data_flow OF xr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x4" + SEVERITY WARNING; + q <= (i0 xor i1) after 1300 ps; +END; diff --git a/pdks/symbolic/lsxlib/cells/zero_x0.ap b/pdks/symbolic/lsxlib/cells/zero_x0.ap new file mode 100644 index 000000000..968eb693e --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/zero_x0.ap @@ -0,0 +1,30 @@ +V ALLIANCE : 6 +H zero_x0,P, 5/ 8/2024,100 +A 0,0,1500,5000 +S 400,900,400,1100,200,*,DOWN,POLY2 +S 0,1100,1500,1100,1400,*,RIGHT,PWELL +S 400,0,400,600,200,*,UP,ALU1 +S 1000,600,1000,4400,200,nq,DOWN,CALU1 +S 400,900,400,1100,200,*,DOWN,POLY +S 400,900,700,900,100,*,LEFT,POLY +S 400,1100,400,5000,200,*,UP,ALU1 +S 700,300,700,900,100,*,UP,NTRANS +S 0,0,1500,0,400,vss,RIGHT,CALU1 +S 0,5000,1500,5000,400,vdd,RIGHT,CALU1 +S 0,4000,1500,4000,1200,*,RIGHT,NWELL +S 0,3100,1500,3100,1200,*,RIGHT,NWELL +S 0,5000,1500,5000,300,*,RIGHT,NTIE +S 0,0,1500,0,300,*,RIGHT,PTIE +B 400,1050,200,300,CONT_TURN8,* +V 1000,600,CONT_DIF_N,* +V 400,600,CONT_DIF_N,* +V 400,1100,CONT_POLY,* +V 0,5000,CONT_BODY_N,* +V 500,5000,CONT_BODY_N,* +V 1000,5000,CONT_BODY_N,* +V 1500,5000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 500,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 1500,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/lsxlib/cells/zero_x0.vbe b/pdks/symbolic/lsxlib/cells/zero_x0.vbe new file mode 100644 index 000000000..535efebc9 --- /dev/null +++ b/pdks/symbolic/lsxlib/cells/zero_x0.vbe @@ -0,0 +1,20 @@ +ENTITY zero_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END zero_x0; + +ARCHITECTURE behaviour_data_flow OF zero_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on zero_x0" + SEVERITY WARNING; + nq <= '0'; +END; diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/__init__.py b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/Sg13g2lsxSetup.py b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/Sg13g2lsxSetup.py new file mode 100644 index 000000000..658880c57 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/Sg13g2lsxSetup.py @@ -0,0 +1,96 @@ + +import sys +import os +import socket +from pathlib import Path +from coriolis.designflow.task import ShellEnv + + +__all__ = [ 'Where', 'setupSg13g2_lsx ' ] + + +class Where ( object ): + + coriolisTop = None + allianceTop = None + cellsTop = None + checkToolkit = None + + def __init__ ( self, checkToolkit=None ): + if 'CORIOLIS_TOP' in os.environ: Where.coriolisTop = Path( os.environ['CORIOLIS_TOP'] ) + if 'ALLIANCE_TOP' in os.environ: Where.allianceTop = Path( os.environ['ALLIANCE_TOP'] ) + if 'CELLS_TOP' in os.environ: Where.cellsTop = Path( os.environ['CELLS_TOP'] ) + if Where.coriolisTop and not Where.allianceTop: Where.allianceTop = Where.coriolisTop + #print( Where.coriolisTop, Where.allianceTop ) + if not Where.coriolisTop: + print( 'technos.Where.__init__(): Unable to locate Coriolis top.' ) + if checkToolkit is None: + checkToolkit = Path.home() / 'coriolis-2.x' / 'src' / 'alliance-check-toolkit' + else: + if isinstance(checkToolkit,str): + checkToolkit = Path( checkToolkit ) + if not Where.cellsTop: + Where.cellsTop = checkToolkit / 'cells' + Where.checkToolkit = checkToolkit + if not Where.cellsTop and Where.allianceTop: + Where.cellsTop = Where.allianceTop / 'cells' + ShellEnv.ALLIANCE_TOP = Where.allianceTop.as_posix() + + def __repr__ ( self ): + if not Where.coriolisTop: + return '' + return ''.format( Where.coriolisTop.as_posix() ) + + +def setupSg13g2_lsx ( checkToolkit=None ): + Where( checkToolkit ) + ShellEnv().export() + + pdkDir = Where.checkToolkit / 'dks' / 'sg13g2_lsx' / 'libs.tech' + coriolisTechDir = pdkDir / 'coriolis' + if not pdkDir.is_dir(): + print( '[ERROR] technos.setupSg13g2_lsx(): PDK directory do *not* exists:' ) + print( ' "{}"'.format(techDir.as_posix()) ) + sys.path.append( coriolisTechDir.as_posix() ) + + cellsTop = Where.checkToolkit / 'cells' + liberty = cellsTop / 'lsxlib' / 'lsxlib.lib' +# kdrcRules = pdkDir / 'klayout' / 'drc_sky130.lydrc' + + from coriolis import Cfg + from coriolis import Viewer + from coriolis import CRL + from coriolis.helpers import overlay, l, u, n + from coriolis.designflow.yosys import Yosys + from coriolis.designflow.klayout import DRC + from sg13g2_lsx import techno, lsxlib + techno.setup( coriolisTechDir ) + lsxlib.setup( cellsTop ) + + with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.misc.minTraceLevel = 1900 + cfg.misc.maxTraceLevel = 3000 + cfg.katana.eventsLimit = 1000000 + cfg.katana.termSatReservedLocal = 6 + cfg.katana.termSatThreshold = 9 + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + Yosys.setLiberty( liberty ) +# DRC.setDrcRules( kdrcRules ) + ShellEnv.CHECK_TOOLKIT = Where.checkToolkit.as_posix() + + path = None + for pathVar in [ 'PATH', 'path' ]: + if pathVar in os.environ: + path = os.environ[ pathVar ] + os.environ[ pathVar ] = path + ':' + (Where.allianceTop / 'bin').as_posix() + break + + diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/__init__.py b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/__init__.py new file mode 100644 index 000000000..b87e091fc --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/__init__.py @@ -0,0 +1,5 @@ + +import os +from pathlib import Path + +path = Path( os.path.dirname(os.path.abspath(__file__)) ) diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/Makefile b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/Makefile new file mode 100644 index 000000000..ca98d7254 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/Makefile @@ -0,0 +1,14 @@ +## PDK sg13g2_lsx +# Building .rds from .exp files + +# Hard coded path... Oh brother ... +#TODO: fix this ASAP e.g. using env variable to some meaningful place +exp_bin = $$HOME/coriolis-2.x/release/install/bin/exp + +../sg13g2_lsx.rds: \ + sg13g2_lsx.main.exp \ + sg13g2_lsx.rules.exp \ + sg13g2_lsx.values.exp \ + symbolic_lsx.rules.exp \ + lambda_lsx.exp + $(exp_bin) -v2 -o $@ $< diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/lambda_lsx.exp b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/lambda_lsx.exp new file mode 100644 index 000000000..877e51d07 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/lambda_lsx.exp @@ -0,0 +1,174 @@ +[ +# date 20230223:1357 +# --------------------------------------------------------------------------- +# Lambda Definition +# --------------------------------------------------------------------------- + +# all lambda constraints +# ---------------------- + +BW_CTIE = BW_VIA0+2*BE_ATIE_VIA0; +BW_CDIF = BW_VIA0+2*BE_ACTI_VIA0; +SW_CDIF = SW_VIAX+2*SE_DIFX_VIA0; + +"Lambda: Pitch run NWELL - run NWELL ||" = + (RD_NWEL+BW_NWEL) + /(SD_WELL+SW_WELL); + +"Lambda: Pitch run NWELL - run NWELL |-" = + (RD_NWEL+BW_NWEL) + /(SD_WELL+2*SE_WELL); + +"Lambda: Pitch run DIF - run DIF" = + (RD_ACTI+BW_ACTI) + /(SD_DIFX+SW_DIFX); + +"Lambda: Pitch run DIF - contact DIF on VIA0" = + (BW_CDIF/2+RD_ACTI+BW_ACTI/2) + /(SW_CDIF/2+SD_DIFX+SW_DIFX/2) ; + +"Lambda: Pitch contact DIF on VIA0 - contact DIF on VIA0" = + (BW_CDIF+RD_ACTI) + /(SW_CDIF+SD_DIFX) ; + +"Lambda: Pitch run TRANSISTOR - run TRANSISTOR (1 active area)" = + (RD_GATE+BW_POLY) + /(SD_GATE+SW_POLY) ; + +"Lambda: Pitch run TRANSISTOR - run TRANSISTOR (2 actives area)" = + (BW_POLY+2*BE_ACTI_POLT+RD_ACTI) + /(SW_POLY+2*SE_DIFT_POLT+SD_DIFX) ; + +"Lambda: Pitch run TRANSISTOR - cont - run TRANSISTOR" = + (2*RD_POLR_VIA0+BW_VIA0+BW_POLY) + /(2*SD_POLY_VIA0+SW_VIAX+SW_POLY) ; + +"Lambda: Pitch contact PDIF on VIA0 - contact NDIF on VIA0" = + (BW_CDIF+BE_PIMP_ACTI+BE_NWEL_PIMP+RD_NWEL_ACTI) + /(SW_CDIF+SE_WELL_DIFX+SD_WELL_DIFX) ; + +"Lambda: Pitch contact NTIE on VIA0 - transistor gate (sidewise)" = + (BW_CTIE/2+BE_NTIE_ATIE+BE_PIMP_GATE) + /(SW_CDIF/2+SD_GATE_TIEX); + +"Lambda: Pitch contact PTIE on VIA0 - transistor gate (sidewise)" = + (BW_CTIE/2+BE_PTIE_ATIE+BE_NIMP_GATE) + /(SW_CDIF/2+SD_GATE_TIEX); + +if (def(BE_POLT), + "Lambda: Pitch contact NTIE on VIA0 - transistor gate (lengthwise)" = + (BW_CTIE/2+BE_NTIE_ATIE+BE_PIMP_GATE+BE_GATE_POLT+BE_POLT) + /(SW_CDIF/2+SD_GATE_TIEX+SE_GATE_POLT+SE_POLT), + + "Lambda: Pitch contact PTIE on VIA0 - transistor gate (lengthwise)" = + (BW_CTIE/2+BE_PTIE_ATIE+BE_NIMP_GATE+BE_GATE_POLT+BE_POLT) + /(SW_CDIF/2+SD_GATE_TIEX+SE_GATE_POLT+SE_POLT) +); + +"Lambda: minimal transistor" = + (BW_ACTI+BE_POLT_ACTI*2) + /(SW_DIFX+SE_POLT_DIFT*2); + +"Lambda: Pitch run POLY - run POLY" = + (RD_POLY+BW_POLY) + /(SD_POLY+SW_POLY) ; + +"Lambda: Pitch contact NTIE on VIA0 - contact NDIF on VIA0" = + (BW_CTIE+BE_NTIE_ATIE+BE_NWEL_NTIE+RD_NWEL_ACTI) + /(SW_CDIF+SE_WELL_DIFX+SD_WELL_DIFX) ; + +"Lambda: Pitch run POLY - contact POLY on VIA0" = + (BW_VIA0/2+BE_POLY_VIA0+RD_POLY+BW_POLY/2) + /(SW_VIAX/2+SE_POLY_VIA0+SD_POLY+SW_POLY/2); + +# as SD_POLY < SD_ALU1, it is impossible to have 2 contact closest +"Lambda: Pitch contact POLY on VIA0 - contact POLY on VIA0" = + (BW_VIA0+2*BE_POLY_VIA0+RD_POLY) + /(SW_VIAX+2*SE_POLY_VIA0+SD_ALU1) ; + +# --------------------------------------------------------------------------- + +"Lambda: Pitch run TRANS - run POLY" = + (BE_ACTI_POLT+RD_POLR_ACTI+BW_POLY) + /(SE_DIFT_POLT+SD_POLR_DIFT+SW_POLY) ; + +"Lambda: Pitch run DIF - run POLY" = + (BW_ACTI/2+RD_POLR_ACTI+BW_POLY/2) + /(SW_DIFX/2+SD_POLY_DIFX+SW_POLY/2) ; + +"Lambda: Pitch contact DIF on VIA0 - run POLY" = + (BW_VIA0/2+BE_ACTI_VIA0+RD_POLR_ACTI+BW_POLY/2) + /(SW_VIAX/2+SE_DIFX_VIA0+SD_POLY_DIFX+SW_POLY/2) ; + +"Lambda: Pitch contact DIF on VIA0 - contact POLY on VIA0" = + (BW_VIA0+BE_ACTI_VIA0+RD_POLR_ACTI+BE_POLY_VIA0) + /(SW_VIAX+SE_DIFX_VIA0+SD_POLY_DIFX+SE_POLY_VIA0) ; + +# --------------------------------------------------------------------------- + +"Lambda: Pitch run ALU1 - run ALU1" = + (RD_ALU1+BW_ALU1) + /(SD_ALU1+SW_ALU1) ; + +"Lambda: Pitch run ALU1 - contact ALU1 on VIA0" = + (BW_VIA0/2+BE_ALU1_VIA0+RD_ALU1+BW_ALU1/2) + /(SW_VIAX/2+SE_ALU1_VIA0+SD_ALU1+SW_ALU1/2) ; + +"Lambda: Pitch contact ALU1 on VIA0 - contact ALU1 on VIA0" = + (BW_VIA0+2*BE_ALU1_VIA0+RD_ALU1) + /(SW_VIAX+2*SE_ALU1_VIA0+SD_ALU1) ; + +"Lambda: Pitch VIA0 - VIA0" = + (BW_VIA0+RD_VIA0) + /(SW_VIAX+SD_VIA0) ; + +# --------------------------------------------------------------------------- + +"Lambda: Pitch run ALU2 - run ALU2" = + (RD_ALU2+BW_ALU2) + /(SD_ALU2+SW_ALU2) ; + +"Lambda: Pitch run ALU2 - contact ALU2 on VIA1" = + (BW_VIA1/2+BE_ALU2_VIA1+RD_ALU2+BW_ALU2/2) + /(SW_VIAX/2+SE_ALU2_VIA1+SD_ALU2+SW_ALU2/2) ; + +"Lambda: Pitch contact ALU2 on VIA1 - contact ALU2 on VIA1" = + (BW_VIA1+2*BE_ALU2_VIA1+RD_ALU2) + /(SW_VIAX+2*SE_ALU2_VIA1+SD_ALU2) ; + +"Lambda: Pitch contact ALU2 on VIA2 - contact ALU2 on VIA2" = + (BW_VIA1+2*BE_ALU2_VIA2+RD_ALU2) + /(SW_VIAX+2*SE_ALU2_VIA2+SD_ALU2) ; + +"Lambda: Pitch VIA1 - VIA1" = + (BW_VIA1+RD_VIA1) + /(SW_VIAX+SD_VIA1) ; + +# --------------------------------------------------------------------------- + +"Lambda: Pitch run ALU3 - run ALU3" = + (RD_ALU3+BW_ALU3) + /(SD_ALU3+SW_ALU3) ; + +"Lambda: Pitch run ALU3 - contact ALU3 on VIA2" = + (BW_VIA2/2+BE_ALU3_VIA2+RD_ALU3+BW_ALU3/2) + /(SW_VIAX/2+SE_ALU3_VIA2+SD_ALU3+SW_ALU3/2) ; + +"Lambda: Pitch contact ALU3 on VIA2 - contact ALU3 on VIA2" = + (BW_VIA2+2*BE_ALU3_VIA2+RD_ALU3) + /(SW_VIAX+2*SE_ALU3_VIA2+SD_ALU3) ; + +"Lambda: Pitch VIA1 - VIA1" = + (BW_VIA2+RD_VIA2) + /(SW_VIAX+SD_VIA2) ; + +# --------------------------------------------------------------------------- + +LAMBDA = sup(GRID, max('Lambda.*')); # finally LAMBDA is the greatest constraint +LAMBDA = inf(GRID, (LAMBDA+GRID)/2)*2; # but LAMBDA must be pair +LAMBDA = 0.11; +]// + +[# print results +# --------------------------------------------------------------------------- +sort('Lambda.*')][message (LAMBDA)]// diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.main.exp b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.main.exp new file mode 100644 index 000000000..00e45002d --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.main.exp @@ -0,0 +1,468 @@ +# 20240801 +# --------------------------------------------------------------------------- +# For sg13g2 +# --------------------------------------------------------------------------- + +include "symbolic_lsx.rules.exp" // +include "sg13g2_lsx.rules.exp" // +include "lambda_lsx.exp"// + +[# symbolic to real parametrisation +BE_POLT = (BW_ACTI + 2*BE_POLT_ACTI - (SW_DIFX + 2*SE_POLT_DIFT)*LAMBDA)/2; + +DW_NWEL = sup(GRID, BW_NWEL-SW_WELL*LAMBDA); +DW_PWEL = sup(GRID, BW_PWEL-SW_WELL*LAMBDA); +DW_POLY = sup(GRID, BW_POLY-SW_POLY*LAMBDA); +DW_POLY_CONT = sup(GRID, BW_VIA0+2*BE_POLY_VIA0-2*LAMBDA); +DW_TRAN_POLY = sup(GRID, DW_POLY); +DW_TRAN_ACTI = sup(GRID, 2*BE_ACTI_POLT+DW_POLY); +DW_ACTI = sup(GRID, BW_ACTI-SW_DIFX*LAMBDA); +DW_ATIE = sup(GRID, BW_ATIE-SW_DIFX*LAMBDA); +DW_ALU1 = sup(GRID, BW_ALU1-SW_ALU1*LAMBDA); +DW_ALU2 = sup(GRID, BW_ALU2-SW_ALU2*LAMBDA); +DW_ALU3 = sup(GRID, BW_ALU3-SW_ALU3*LAMBDA); + +DL_NWEL = sup(GRID, 2*LAMBDA); #DW_NWEL/2); +DL_PWEL = sup(GRID, 2*LAMBDA); #DW_PWEL/2); +DL_POLY = sup(GRID, BW_POLY/2); +DL_TRAN_POLY = sup(GRID, BE_POLT); +DL_TRAN_ACTI = sup(GRID, DL_TRAN_POLY-BE_POLT_ACTI); +DL_ACTI = sup(GRID, 2*LAMBDA+DL_TRAN_ACTI); +DL_ATIE = sup(GRID, BW_ATIE/2); +DL_ALU1 = sup(GRID, BW_ALU1/2); +DL_ALU2 = sup(GRID, BW_ALU2/2); +DL_ALU3 = sup(GRID, BW_ALU3/2); + +T_OFFSET = (BW_POLY - SW_POLY*LAMBDA)/2; # Drain & Source for extractor +]// + +# ------------------------------------------------------------------- +# globals define +# ------------------------------------------------------------------- + +define physical_grid [GRID] +define lambda [LAMBDA] + +include "sg13g2_lsx.values.exp" // +// +table mbk_to_rds_segment +# ---------------------------------------------------------------------------------- +# mbk_name rds_name1 dlr dwr offset mode rds_name2 dlr dwr offset mode +# ---------------------------------------------------------------------------------- +// calculation of the transisor offset + + nwell rds_nwell vw [ DL_NWEL+BE_NTIE_ATIE+BE_NWEL_NTIE ] [ DW_NWEL ] .0 all\ + rds_pimp vw [ DL_NWEL-BE_NWEL_PIMP ] [ DW_NWEL-2*(BE_NWEL_PIMP) ] .0 all + + pwell rds_pwell vw [ DL_PWEL+BE_PTIE_ATIE+BE_PWEL_PTIE ] [ DW_PWEL ] .0 all\ + rds_nimp vw [ DL_NWEL-BE_PWEL_NIMP ] [ DW_NWEL-2*(BE_PWEL_NIMP) ] .0 all + + ndif rds_activ vw [ DL_ACTI ] [ DW_ACTI ] .0 all\ + rds_ndif vw [ DL_ACTI ] [ DW_ACTI ] .0 ext + + pdif rds_activ vw [ DL_ACTI ] [ DW_ACTI ] .0 all\ + rds_pdif vw [ DL_ACTI ] [ DW_ACTI ] .0 ext + + ntie rds_activ vw [ DL_ATIE ] [ DW_ATIE ] .0 all\ + rds_ntie vw [ DL_ATIE+BE_NTIE_ATIE ] [ DW_ATIE+2*(BE_NTIE_ATIE) ] .0 all\ + rds_nwell vw [ DL_NWEL+BE_NTIE_ATIE+BE_NWEL_NTIE ] [ DW_ATIE+2*(BE_NTIE_ATIE+BE_NWEL_NTIE+LAMBDA)] .0 all + + ptie rds_activ vw [ DL_ATIE ] [ DW_ATIE ] .0 all\ + rds_ptie vw [ DL_ATIE+BE_PTIE_ATIE ] [ DW_ATIE+2*(BE_PTIE_ATIE) ] .0 all\ + rds_pwell vw [ DL_PWEL+BE_PTIE_ATIE+BE_PWEL_PTIE ] [ DW_ATIE+2*(BE_PTIE_ATIE+BE_PWEL_PTIE+LAMBDA)] .0 all + + ntrans rds_poly vw [ DL_TRAN_POLY ] [ DW_TRAN_POLY ] .0 all\ + rds_activ vw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI ] .0 drc\ + rds_ndif lcw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI/2 ] [T_OFFSET] ext\ + rds_ndif rcw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI/2 ] [T_OFFSET] ext + + ptrans rds_poly vw [ DL_TRAN_POLY ] [ DW_TRAN_POLY ] .0 all\ + rds_activ vw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI ] .0 drc\ + rds_pdif lcw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI/2 ] [T_OFFSET] ext\ + rds_pdif rcw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI/2 ] [T_OFFSET] ext + + poly rds_poly vw [ DL_POLY ] [ DW_POLY ] .0 all + + alu1 rds_alu1 vw [ DL_ALU1 ] [ DW_ALU1 ] .0 all + calu1 rds_alu1 vw [ DL_ALU1 ] [ DW_ALU1 ] .0 all + talu1 rds_talu1 vw [ DL_ALU1 ] [ DW_ALU1 ] .0 all + + alu2 rds_alu2 vw [ DL_ALU2 ] [ DW_ALU2 ] .0 all + calu2 rds_alu2 vw [ DL_ALU2 ] [ DW_ALU2 ] .0 all + talu2 rds_talu2 vw [ DL_ALU2 ] [ DW_ALU2 ] .0 all + + alu3 rds_alu3 vw [ DL_ALU3 ] [ DW_ALU3 ] .0 all + calu3 rds_alu3 vw [ DL_ALU3 ] [ DW_ALU3 ] .0 all + talu3 rds_talu3 vw [ DL_ALU3 ] [ DW_ALU3 ] .0 all +end + +table mbk_to_rds_connector +# ------------------------------------------------------------------- +# mbk_name rds_name der dwr +# ------------------------------------------------------------------- +end + +table mbk_to_rds_reference +# ------------------------------------------------------------------- +# mbk_name rds_name width +# ------------------------------------------------------------------- + ref_ref rds_ref [ BW_ALU1 ] + ref_con rds_ref [ BW_ALU1 ] +end + +table mbk_to_rds_via +# ------------------------------------------------------------------- +# mbk_name rds_name1 width mode rds_name2 width mode ... +## ------------------------------------------------------------------ + cont_body_n \ + rds_cont [ BW_VIA0 ] all\ + rds_alu1 [ BW_VIA0+2*(BE_ALU1_VIA0) ] all\ + rds_activ [ BW_VIA0+2*(BE_ATIE_VIA0) ] drc\ + rds_ntie [ BW_VIA0+2*(BE_ATIE_VIA0) ] ext + + cont_body_p \ + rds_cont [ BW_VIA0 ] all\ + rds_alu1 [ BW_VIA0+2*(BE_ALU1_VIA0) ] all\ + rds_activ [ BW_VIA0+2*(BE_ATIE_VIA0) ] drc\ + rds_ptie [ BW_VIA0+2*(BE_ATIE_VIA0) ] ext + + cont_dif_n \ + rds_cont [ BW_VIA0 ] all\ + rds_alu1 [ BW_VIA0+2*(BE_ALU1_VIA0) ] all\ + rds_activ [ BW_VIA0+2*(BE_ACTI_VIA0) ] drc\ + rds_ndif [ BW_VIA0+2*(BE_ACTI_VIA0) ] ext + + cont_dif_p \ + rds_cont [ BW_VIA0 ] all\ + rds_alu1 [ BW_VIA0+2*(BE_ALU1_VIA0) ] all\ + rds_activ [ BW_VIA0+2*(BE_ACTI_VIA0) ] drc\ + rds_pdif [ BW_VIA0+2*(BE_ACTI_VIA0) ] ext + + cont_poly \ + rds_cont [ BW_VIA0 ] all\ + rds_poly [ BW_VIA0+2*(BE_POLY_VIA0) ] all\ + rds_alu1 [ BW_VIA0+2*(BE_ALU1_VIA0) ] all + + cont_via \ + rds_via1 [ BW_VIA1 ] all\ + rds_alu1 [ BW_VIA1+2*(BE_ALU1_VIA1) ] all\ + rds_alu2 [ BW_VIA1+2*(BE_ALU2_VIA1) ] all + + cont_via2 \ + rds_via2 [ BW_VIA2 ] all\ + rds_alu2 [ BW_VIA2+2*(BE_ALU2_VIA2) ] all\ + rds_alu3 [ BW_VIA2+2*(BE_ALU3_VIA2) ] all +end + +table mbk_to_rds_bigvia_hole +# ------------------------------------------------------------------- +# mbk_via_name rds_hole_name side step mode +# ------------------------------------------------------------------- +end + +table mbk_to_rds_bigvia_metal +# ------------------------------------------------------------------- +# mbk_via_name rds_name dwr overlap mode +# ------------------------------------------------------------------- +end + +table mbk_to_rds_turnvia +# ------------------------------------------------------------------- +# mbk_name rds_name dwr mode +# ------------------------------------------------------------------- + cont_turn1 rds_alu1 [ DW_ALU1 ] all + cont_turn2 rds_alu2 [ DW_ALU2 ] all + cont_turn3 rds_alu3 [ DW_ALU3 ] all + cont_turn8 rds_poly [ DW_POLY_CONT ] all +end + +table lynx_bulk_implicit +# ------------------------------------------------------------------- +# rds_name type[explicit|implicit] +# ------------------------------------------------------------------- +end + +table lynx_transistor +# ------------------------------------------------------------------- +# mbk_name trans_name compostion +# ------------------------------------------------------------------- + NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL + PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL +end + +table lynx_diffusion +# ------------------------------------------------------------------- +# rds_name compostion +# ------------------------------------------------------------------- + rds_ndif rds_activ 1 rds_nimp 1 rds_nwell 0 + rds_pdif rds_activ 1 rds_pimp 1 rds_nwell 1 + rds_ntie rds_activ 1 rds_nimp 1 rds_nwell 1 + rds_ptie rds_activ 1 rds_pimp 1 rds_nwell 0 +end + +table lynx_graph +# ------------------------------------------------------------------- +# rds_name in_contact_with rds_name1 rds_name2 ... +# ------------------------------------------------------------------- + rds_ndif rds_cont rds_ndif + rds_pdif rds_cont rds_pdif + rds_poly rds_cont rds_poly + rds_cont rds_pdif rds_ndif rds_poly rds_alu1 rds_cont + rds_alu1 rds_cont rds_via1 rds_ref rds_alu1 + rds_ref rds_cont rds_via1 rds_alu1 rds_ref + rds_alu2 rds_via1 rds_via2 rds_alu2 + rds_alu3 rds_via2 rds_alu3 +end + +table s2r_oversize_denotch +# ------------------------------------------------------------------- +# rds_name oversized_value_for_denotching +# ------------------------------------------------------------------- + rds_nwell [ sup(GRID,RD_NWEL/2) ] + rds_pwell [ sup(GRID,RD_PWEL/2) ] + rds_poly [ inf(GRID,RD_POLY/2-GRID) ] + rds_alu1 [ inf(GRID,RD_ALU1/2-GRID) ] + rds_alu2 [ inf(GRID,RD_ALU2/2-GRID) ] + rds_alu3 [ inf(GRID,RD_ALU3/2-GRID) ] + rds_activ [ inf(GRID,RD_ACTI/2-GRID) ] + rds_ntie [ sup(GRID,RD_NIMP/2) ] + rds_ptie [ sup(GRID,RD_PIMP/2) ] + rds_nimp [ sup(GRID,RD_NIMP/2) ] + rds_pimp [ sup(GRID,RD_NIMP/2) ] +end + +table s2r_bloc_ring_width +# ------------------------------------------------------------------- +# rds_name ring_width_to_copy_up +# ------------------------------------------------------------------- + rds_nwell 0. # [ RD_NWEL ] + rds_pwell 0. # [ RD_PWEL ] + rds_poly 0. # [ RD_POLY ] + rds_alu1 0. # [ RD_ALU1 ] + rds_alu2 0. # [ RD_ALU2 ] + rds_alu3 0. # [ RD_ALU3 ] + rds_activ 0. # [ RD_ACTI ] + rds_ntie 0. # [ RD_NIMP ] + rds_ptie 0. # [ RD_PIMP ] + rds_nimp 0. # [ RD_NIMP ] + rds_pimp 0. # [ RD_PIMP ] +end + +table s2r_minimum_layer_width +# ------------------------------------------------------------------- +# rds_name min_layer_width_to_keep +# ------------------------------------------------------------------- + rds_nwell [ BW_NWEL ] + rds_pwell [ BW_PWEL ] + rds_poly [ BW_POLY ] + rds_alu1 [ BW_ALU1 ] + rds_alu2 [ BW_ALU2 ] + rds_alu3 [ BW_ALU3 ] + rds_activ [ BW_ACTI ] + rds_ntie [ BW_NIMP ] + rds_ptie [ BW_PIMP ] + rds_nimp [ BW_NIMP ] + rds_pimp [ BW_PIMP ] +end + +table s2r_post_treat +# ------------------------------------------------------------------- +# rds_name s2r_must_treat_or_not second_layer_whenever_scotch +# ------------------------------------------------------------------- + rds_nwell treat null + rds_pwell treat null + rds_poly treat null + rds_activ treat null + rds_ntie treat rds_pimp + rds_ptie treat rds_nimp + rds_nimp treat rds_ptie + rds_pimp treat rds_ntie + rds_alu1 treat null + rds_alu2 treat null + rds_alu3 treat null + rds_cont notreat null +end + +DRC_RULES + +layer RDS_NWELL [ RW_NWEL ] ; +layer RDS_NTIE [ RW_NTIE ] ; +layer RDS_PTIE [ RW_PTIE ] ; +layer RDS_NIMP [ RW_NIMP ] ; +layer RDS_PIMP [ RW_PIMP ] ; +layer RDS_ACTIV [ RW_ACTI ] ; +layer RDS_CONT [ RW_VIA0 ] ; +layer RDS_POLY [ RW_POLY ] ; +layer RDS_ALU1 [ RW_ALU1 ] ; +layer RDS_ALU2 [ RW_ALU2 ] ; +layer RDS_ALU3 [ RW_ALU3 ] ; +layer RDS_USER0 [ GRID ] ; +layer RDS_USER1 [ GRID ] ; +layer RDS_USER2 [ GRID ] ; + +regles + +# note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# there is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# ---------------------------------------------------------- + +# check the nwell shapes +# ---------------------- +caracterise RDS_NWELL ( + regle {N=1;N++} : largeur >= [ RW_NWEL ] ; + regle {N++} : longueur_inter min [ RW_NWEL ] ; + regle {N++} : notch >= [ RD_NWEL ] ; +); +relation RDS_NWELL , RDS_NWELL ( + regle {N++} : distance axiale min [ RD_NWEL ] ; +); +relation RDS_NWELL , RDS_ACTI ( + regle {N++} : distance axiale min [ RD_NWEL_ACTI ] ; +); + +# check the RDS_PIMP shapes +# ------------------------- +caracterise RDS_PIMP ( + regle {N++} : surface min [ RA_PIMP ] ; + regle {N++} : largeur >= [ RW_PIMP ] ; + regle {N++} : longueur_inter min [ RW_PIMP ] ; + regle {N++} : notch >= [ RD_PIMP ] ; +); +relation RDS_PIMP , RDS_PIMP ( + regle {N++} : distance axiale min [ RD_PIMP ] ; +); + +# check the RDS_NIMP shapes +# ------------------------- +caracterise RDS_NIMP ( + regle {N++} : surface min [ RA_NIMP ] ; + regle {N++} : largeur >= [ RW_NIMP ] ; + regle {N++} : longueur_inter min [ RW_NIMP ] ; + regle {N++} : notch >= [ RD_NIMP ] ; +); +relation RDS_NIMP , RDS_NIMP ( + regle {N++} : distance axiale min [ RD_NIMP ] ; +); + +# check the RDS_PTIE shapes +# ------------------------- +caracterise RDS_PTIE ( + regle {N++} : surface min [ RA_PIMP ] ; + regle {N++} : largeur >= [ RW_PIMP ] ; + regle {N++} : longueur_inter min [ RW_PIMP ] ; + regle {N++} : notch >= [ RD_PIMP ] ; +); +relation RDS_PTIE , RDS_PTIE ( + regle {N++} : distance axiale min [ RD_PIMP ] ; +); + +# check the RDS_NTIE shapes +# ------------------------- +caracterise RDS_NTIE ( + regle {N++} : surface min [ RA_NIMP ] ; + regle {N++} : largeur >= [ RW_NIMP ] ; + regle {N++} : longueur_inter min [ RW_NIMP ] ; + regle {N++} : notch >= [ RD_NIMP ] ; +); +relation RDS_NTIE , RDS_NTIE ( + regle {N++} : distance axiale min [ RD_NIMP ] ; +); + +# check the RDS_ACTI shapes +# ------------------------- +caracterise RDS_ACTI ( + regle {N++} : surface min [ RA_ACTI ] ; + regle {N++} : largeur >= [ RW_ACTI ] ; + regle {N++} : longueur_inter min [ RW_ACTI ] ; + regle {N++} : notch >= [ RD_ACTI ] ; +); +relation RDS_ACTI, RDS_ACTI ( + regle {N++} : distance axiale min [ RD_ACTI ] ; +); + +# check the RDS_NIMP RDS_PTIE exclusion +# ------------------------------------- +define RDS_NIMP , RDS_PTIE intersection -> NPIMP; +caracterise NPIMP ( + regle {N++} : largeur = 0. ; +); +undefine NPIMP; + +# check the RDS_NTIE RDS_PIMP exclusion +# ------------------------------------- +define RDS_NTIE , RDS_PIMP intersection -> NPIMP; +caracterise NPIMP ( + regle {N++} : largeur = 0. ; +); +undefine NPIMP; + +# check the RDS_POLY shapes +# ------------------------- +caracterise RDS_POLY ( + regle {N++} : largeur >= [ RW_POLY ] ; + regle {N++} : longueur_inter min [ RW_POLY ] ; + regle {N++} : notch >= [ RD_POLY ] ; +); +relation RDS_POLY , RDS_POLY ( + regle {N++} : distance axiale min [ RD_POLY ] ; +); + +define RDS_ACTI , RDS_POLY intersection -> channel; + + # check the channel shapes + # ------------------------- + caracterise channel ( + regle {N++} : notch >= [ RD_GATE ] ; + ); + relation channel , channel ( + regle {N++} : distance axiale min [ RD_GATE ] ; + ); + +undefine channel; + +define RDS_ACTI , RDS_CONT intersection -> cont_diff; + + relation RDS_POLY , cont_diff ( + regle {N++} : distance axiale >= [ RD_POLR_VIA0 ] ; + ); + +undefine cont_diff; + +# check RDS_ALU1 shapes +# --------------------- +caracterise RDS_ALU1 ( + regle {N++} : surface min [ RA_ALU1 ] ; + regle {N++} : largeur >= [ RW_ALU1 ] ; + regle {N++} : longueur_inter min [ RW_ALU1 ] ; + regle {N++} : notch >= [ RD_ALU1 ] ; +); +relation RDS_ALU1 , RDS_ALU1 ( + regle {N++} : distance axiale min [ RD_ALU1 ] ; +); + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_CONT , RDS_CONT ( + regle {N++} : distance axiale >= [ RD_VIA0 ] ; +); + +caracterise RDS_CONT ( + regle {N++} : largeur = [ RW_VIA0 ] ; + regle {N++} : longueur = [ RW_VIA0 ] ; +); + +# check RDS_POLY is distant from activ zone of transistor +# ------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + regle {N++} : distance axiale >= [ RD_POLR_ACTI ] ; +); + +fin regles +DRC_COMMENT +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.rules.exp b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.rules.exp new file mode 100644 index 000000000..e94755c48 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.rules.exp @@ -0,0 +1,158 @@ +[ +# ----------------------------------------------------------------------------- +# 16 january 2023, revision MML +# 23 january 2023, MML +# 2 february 2023, MML +# 1 march 2023, MML +# 18 april 2023, FW +# creation of two types of real rules: +# R) the true "Real" rules found in the PDK, they are prefixed by R +# B) the "Beautiful" rules computed to improve the quality of the layout without increasing the lambda, they are prefixed by B +# The lambda now is computed from low level mask (ALU1 and below) +# 19 June 2024, FW, IHP +# +# Layer Name +# +# NWEL : N WELL (NW) +# PWEL : P WELL (PW) +# NIMP : N+ implanted zone ("N+") +# PIMP : P+ implanted zone ("P+") +# NTIE : N+ implanted zone for NWELL body tie "NW STRAP" (NP) +# PTIE : P+ implanted zone for PWELL body tie "PW STRAP" (PP) +# ACTI : active zone (OD) (N+ ACTIVE or P+ACTIVE) +# ATIE : active zone +# POLY : POLY wire or Transistors ("PO" or "GATE") +# POLT : POLY transistor (T stands for Transistor) +# POLR : POLY wire (R stands for Run) +# VIA0 : CONTACT (cut to join ALU1 to POLX or DIFX) ("CO") # licon +# ALU1 : ALU first level (ALU1) # li local Interconnect to diff/tap and poly +# +# Real Rule type +# +# RA_LAYER : Real Area +# RW_LAYER : Real Width +# RD_LAYER : Real Distance between two edges of the same layer +# RD_LAYER1_LAYER2 : Real Distance between layer1 and layer2 +# RE_LAYER1_LAYER2 : Real Extension of Layer1 on Layer2 (all directions) +# REL_LAYER1_LAYER2 : Real Extension of Layer1 on Layer2 (linearly) +# +# In order to make layout "beautiful" (less edges) +# +# BW_LAYER : Beautiful Width +# BE_LAYER1_LAYER2 : Beautiful Extension of Layer1 on Layer2 +# +# GRID is the physical grid, every physical rule is a multiple of it. +# --------------------------------------------------------------------------- + +GRID = 0.001 ; # sky130: 0.005 ; # derived from distance values + +RA_ACTI = 1.222 ; # sky130: 0.0 ; # Act.2 +RA_ATIE = 1.222 ; # sky130: 0.0 ; # Act.2 +RA_NIMP = 0.250 ; # sky130: 0.265 ; # pSD.k +RA_PIMP = 0.250 ; # sky130: 0.255 ; # pSD.k +RA_ALU1 = 0.090 ; # sky130: 0.06 ; # M1.d +RA_ALU2 = 0.144 ; # sky130: 0.00 ; # Mn.d +RA_ALU3 = 0.144 ; # sky130: 0.00 ; # Mn.d + +RW_NWEL = 0.62 ; # sky130: 0.84 ; # NW.a +RW_PWEL = 0.62 ; # sky130: RW_NWEL; # PWB.a +RW_ACTI = 0.15 ; # sky130: 0.42 ; # Act.a +RW_ATIE = 0.15 ; # sky130: 0.15 ; # Act.a +RW_NTIE = 0.15 ; # sky130: 0.38 ; # Act.a +RW_PTIE = 0.15 ; # sky130: 0.38 ; # Act.a +RW_NIMP = 0.31 ; # sky130: 0.38 ; # nSD.1 = NOT (pSD OR nSD:block) +RW_PIMP = 0.31 ; # sky130: 0.38 ; # pSD.a +RW_POLY = 0.13 ; # sky130: 0.15 ; # Gat.a +RW_VIA0 = 0.16 ; # sky130: 0.17 ; # Cnt.a +RW_VIA1 = 0.19 ; # sky130: 0.17 ; # V1.a +RW_VIA2 = 0.19 ; # sky130: 0.17 ; # Vn.a +RW_ALU1 = 0.16 ; # sky130: 0.17 ; # M1.a +RW_ALU2 = 0.20 ; # sky130: 0.17 ; # Mn.a +RW_ALU3 = 0.20 ; # sky130: 0.17 ; # Mn.a + +RD_NWEL = 1.80 ; # sky130: 1.27 ; # max(NW.b[0.62],NW.b1[1.80]) +RD_PWEL = 1.80 ; # sky130: RD_NWEL; # not sure there is PWELL +RD_ACTI = 0.21 ; # sky130: 0.27 ; # Act.b +RD_ATIE = 0.21 ; # sky130: 0.27 ; # Act.b +RD_PIMP = 0.31 ; # sky130: 0.38 ; # pSD.b +RD_NIMP = 0.31 ; # sky130: 0.38 ; # nsd.2 +RD_POLY = 0.18 ; # sky130: 0.21 ; # Gat.b +RD_GATE = 0.18 ; # sky130: 0.21 ; # Gat.b +RD_VIA0 = 0.18 ; # sky130: 0.17 ; # Cnt.b +RD_VIA1 = 0.22 ; # sky130: 0.17 ; # V1.b +RD_VIA2 = 0.22 ; # sky130: 0.17 ; # Vn.b +RD_ALU1 = 0.18 ; # sky130: 0.17 ; # M1.b +RD_ALU2 = 0.21 ; # sky130: 0.17 ; # Mn.b +RD_ALU3 = 0.21 ; # sky130: 0.17 ; # Mn.b + +RD_POLR_ACTI = 0.07 ; # sky130: 0.075 ; # Gat.d +RD_POLR_ATIE = 0.07 ; # sky130: 0.075 ; # Gat.d +RD_POLR_VIA0 = 0.11 ; # sky130: 0.25 ; # Cnt.f +RD_NWEL_ACTI = 0.62 ; # sky130: 0.34 ; # max(NW.d[0.31],NW.d1[0.62]) + +RE_NWEL_PIMP = 0.13 ; # sky130: 0.055 ; # max(NW.c[0.31],NW.c1[0.62]) - pSD.c[0.18] +RE_NWEL_NTIE = 0.21 ; # sky130: 0.055 ; # max(NW.e[0.24],NW.e1[0.62]) - pSD.c1[0.03] +RE_PWEL_NIMP = 0.13 ; # sky130: RE_NWEL_PIMP; # like RE_NWEL_PIMP ? +RE_PWEL_PTIE = 0.21 ; # sky130: RE_NWEL_NTIE; # like RE_NWEL_NTIE ? +RE_NIMP_GATE = 0.00 ; # sky130: 0.00 ; # NA ? +RE_PIMP_GATE = 0.00 ; # sky130: 0.00 ; # NA ? +RE_GATE_POLT = -0.18 ; # sky130: -0.130 ; # -Gat.c (RE_POLT_ACTI) to be checked see above RE_NIMP_GATE not found +RE_NIMP_ACTI = 0.18 ; # sky130: 0.125 ; # no rule since NIMP is by default +RE_PIMP_ACTI = 0.18 ; # sky130: 0.125 ; # pSD.c +RE_NTIE_ATIE = 0.03 ; # sky130: 0.125 ; # no rule since NIMP is by default +RE_PTIE_ATIE = 0.03 ; # sky130: 0.125 ; # pSD.c1 +RE_ACTI_POLT = 0.23 ; # sky130: 0.250 ; # Act.c +RE_POLT_ACTI = 0.18 ; # sky130: 0.130 ; # Gat.c +RE_ACTI_VIA0 = 0.07 ; # sky130: 0.06 ; # Cnt.c +RE_ATIE_VIA0 = 0.07 ; # sky130: 0.06 ; # Cnt.c +RE_POLY_VIA0 = 0.07 ; # sky130: 0.05 ; # Cnt.d +RE_ALU1_VIA0 = 0.05 ; # sky130: 0.08 ; # max(M1.c[0.00],M1.c1[0.05]) +RE_ALU1_VIA1 = 0.05 ; # sky130: 0.08 ; # max(Mn.c[0.005],Mn.c1[0.05]) +RE_ALU2_VIA1 = 0.05 ; # sky130: 0.08 ; # max(Mn.c[0.005],Mn.c1[0.05]) +RE_ALU2_VIA2 = 0.05 ; # sky130: 0.08 ; # max(Mn.c[0.005],Mn.c1[0.05]) +RE_ALU3_VIA2 = 0.05 ; # sky130: 0.08 ; # max(Mn.c[0.005],Mn.c1[0.05]) + +# --------------------------------------------------------------------------- +# Modifications in order to get a more beautiful layout +# Symbolic technology for all metals : SW_VIAX+2*SE_ALUX_VIAX == SW_ALUX +# then it is possible to blot layers in order to have contacts included in wire +# --------------------------------------------------------------------------- + +BW_NWEL = RW_NWEL; +BW_PWEL = RW_PWEL; +BW_ACTI = RW_ACTI + 0.15; +BW_ATIE = RW_ATIE + 0.15; +BW_NTIE = RW_NTIE; +BW_PTIE = RW_PTIE; +BW_NIMP = RW_NIMP; +BW_PIMP = RW_PIMP; +BW_POLY = RW_POLY; +BW_VIA0 = RW_VIA0; +BW_VIA1 = RW_VIA1; +BW_VIA2 = RW_VIA2; +BW_ALU1 = RW_VIA0+2*RE_ALU1_VIA0; # RW_ALU1 + 0.02; to have cont_alu1 width = 2 lambda alu1 wire width +BW_ALU2 = RW_VIA1+2*RE_ALU2_VIA1; # FIXME +BW_ALU3 = RW_VIA2+2*RE_ALU3_VIA2; # FIXME + +BE_NWEL_PIMP = RE_NWEL_PIMP; +BE_NWEL_NTIE = RE_NWEL_NTIE; +BE_PWEL_NIMP = RE_PWEL_NIMP; +BE_PWEL_PTIE = RE_PWEL_PTIE; +BE_NIMP_GATE = RE_NIMP_GATE; +BE_PIMP_GATE = RE_PIMP_GATE; +BE_GATE_POLT = RE_GATE_POLT; +BE_NIMP_ACTI = RE_NIMP_ACTI; +BE_PIMP_ACTI = RE_PIMP_ACTI; +BE_NTIE_ATIE = RE_NTIE_ATIE; +BE_PTIE_ATIE = RE_PTIE_ATIE; +BE_ACTI_POLT = RE_ACTI_POLT; # + 0.025; +BE_POLT_ACTI = RE_POLT_ACTI; # + 0.005; +BE_ACTI_VIA0 = RE_ACTI_VIA0; # + 0.065; +BE_ATIE_VIA0 = RE_ATIE_VIA0; +BE_POLY_VIA0 = RE_POLY_VIA0; # + 0.01; # to have cont_poly width = 2 lambda poly wire width +BE_ALU1_VIA0 = RE_ALU1_VIA0; +BE_ALU1_VIA1 = RE_ALU1_VIA1; +BE_ALU2_VIA1 = RE_ALU2_VIA1; +BE_ALU2_VIA2 = RE_ALU2_VIA2; +BE_ALU3_VIA2 = RE_ALU3_VIA2; +]// diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.values.exp b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.values.exp new file mode 100644 index 000000000..d6a9c8bfd --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.values.exp @@ -0,0 +1,127 @@ +table cif_layer +# ------------------------------------------------------------------- +# rds_name cif_name +# ------------------------------------------------------------------- + rds_nwell nwel +# rds_pwell pwel + rds_activ active + rds_ntie nplus + rds_ptie pplus + rds_nimp nplus + rds_pimp pplus + rds_poly poly + rds_alu1 metal1 + rds_alu2 metal2 + rds_alu3 metal3 + rds_alu4 metal4 + rds_alu5 metal5 + rds_alu6 metal6 + rds_cont contact + rds_via1 via1 + rds_via2 via2 + rds_via3 via3 + rds_via4 via4 + rds_via5 via5 + rds_cpas pad +end + +table gds_layer +# ------------------------------------------------------------------- +# rds_name gds_number +# ------------------------------------------------------------------- + rds_nwell 31 +# rds_pwell + rds_activ 1 + rds_ptie 14 + rds_ntie 7 + rds_pimp 14 + rds_nimp 7 + rds_poly 5 5 + rds_alu1 8 8 + rds_alu2 10 10 + rds_alu3 30 30 + rds_alu4 50 50 + rds_alu5 67 67 + rds_alu6 0 0 + rds_cont 6 + rds_via1 19 + rds_via2 29 + rds_via3 49 + rds_via4 66 + rds_via5 0 + rds_cpas 0 +end + +table lynx_resistor +# ------------------------------------------------------------------- +# rds_name square_resistor(ohm/square) # typical values +# ------------------------------------------------------------------- + rds_poly 48 + rds_alu1 13 + rds_alu2 0.125 + rds_alu3 0.125 + rds_alu4 0.047 + rds_alu5 0.047 + rds_alu6 0.029 + rds_cont 15 + rds_via1 152 + rds_via2 4.5 + rds_via3 3.4 + rds_via4 3.4 + rds_via5 0.38 +end + +table lynx_capa +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- + rds_poly 25.2e-6 51.8e-6 # Ca max POLY_NWELL 2Cf0 max POLY_NWELL + rds_alu1 2.6e-5 8.5e-5 # Ca max M1_NWELL 2Cf0 max M1_NWELL + rds_alu2 1.6e-5 7.9e-5 # Ca max M2_NWELL 2Cf0 max M2_NWELL + rds_alu3 8.0e-6 6.8e-5 # Ca max M3_NWELL 2Cf0 max M3_NWELL + rds_alu4 6.0e-6 6.0e-5 # Ca max M4_NWELL 2Cf0 max M4_NWELL + rds_alu5 6.0e-6 6.0e-5 # hyp + rds_alu6 6.0e-6 6.0e-5 +end + +table lynx_capa_poly +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_poly2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu1 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu3 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu4 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu5 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/symbolic_lsx.rules.exp b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/symbolic_lsx.rules.exp new file mode 100644 index 000000000..3e1413b14 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/exp/symbolic_lsx.rules.exp @@ -0,0 +1,70 @@ +[ +# 20230418 +# --------------------------------------------------------------------------- +# Symbolic layer names, which appear below, are not exactly the MBK names, +# because this file must contain as less values as possible. +# Theses names are chosen to avoid giving twice the same value. +# +# WELL : NWELL PWELL +# DIFR : NDIF, PDIF in wires +# DIFT : NDIF or PDIF in transistors +# TIEX : NTIE or PTIE +# DIFX : all DIFFUSIONs +# POLR : POLY wire +# POLT : POLY in Transistors +# POLY : POLR or POLT +# GATE : GATE is over POLT but not with the same lengthwise extension +# VIA0 : VIA0ACT (cut to join ALU1 to POLY or DIFX) +# ALU1 : METAL LEVEL 1 +# +# Symbolic rules type, minimum values (Theses Data should not be changed) +# +# SW_LAYER : Symbolic Width +# SE_LAYER : Symbolic Extension (if not defined, it is SW_LAYER/2) +# SD_LAYER : Symbolic Distance between two edges of the same layer +# SD_LAYER1_LAYER2 : Symbolic Distance between layer1 and layer2 +# SE_LAYER1_LAYER2 : Symbolic Extension of Layer1 on Layer2 +# -------------------------------------------------------------------------- + +SW_WELL = 4.0 ; +SW_DIFX = 3.0 ; # 2.0 +SW_POLY = 1.0 ; +SW_VIAX = 1.0 ; +SW_ALU1 = 2.0 ; + +SE_WELL = 2.0 ; +SE_POLT = 0.0 ; +SE_DIFX = 0.5 ; + +SD_WELL = 20.0 ; # 12.0 NWELL are never too close +SD_DIFX = 3.0 ; +SD_POLY = 2.5 ; # 2.0 +SD_GATE = 3.0 ; +SD_VIA0 = 3.0 ; +SD_ALU1 = 3.0 ; + +SD_WELL_DIFX = 7.5 ; +SD_GATE_TIEX = 3.0 ; +SD_POLY_DIFX = 1.0 ; +SD_POLR_DIFT = 1.5 ; +SD_POLY_VIA0 = 2.0 ; + +SE_WELL_DIFX = 0.5 ; +SE_GATE_POLT = -1.5 ; # lengthwise extension +SE_POLT_DIFT = 1.5 ; +SE_DIFT_POLT = 2.5 ; +SE_DIFX_VIA0 = 1.5 ; # 1.0 +SE_POLY_VIA0 = 0.5 ; # 1.0 +SE_ALU1_VIA0 = 0.5 ; +SE_ALU1_VIA1 = 0.5 ; + +SD_VIA1 = 3.0 ; +SW_ALU2 = 2.0 ; +SD_ALU2 = 3.0 ; +SE_ALU2_VIA1 = 0.5 ; +SE_ALU2_VIA2 = 0.5 ; +SD_VIA2 = 3.0 ; +SW_ALU3 = 2.0 ; +SD_ALU3 = 3.0 ; +SE_ALU3_VIA2 = 0.5 ; +] // diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/lsxlib.py b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/lsxlib.py new file mode 100644 index 000000000..c17cabed5 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/lsxlib.py @@ -0,0 +1,219 @@ + +import sys +import os.path +from coriolis import Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, \ + BasicLayer, Cell, Net, Horizontal, Vertical, \ + Rectilinear, Box, Point, Instance, Transformation, \ + NetExternalComponents, Pad +import coriolis.Viewer +from coriolis.CRL import AllianceFramework, Environment, Gds, LefImport, \ + CellGauge, RoutingGauge, RoutingLayerGauge +from coriolis.helpers import l, u, n, overlay, io, ndaTopDir +from coriolis.helpers.overlay import CfgCache, UpdateSession +from coriolis.Anabatic import StyleFlags + + +__all__ = [ "setup" ] + + +def _routing (): + """ + Define the routing gauge along with the various P&R tool parameters. + """ + af = AllianceFramework.get() + db = DataBase.getDB() + tech = db.getTechnology() + rg = RoutingGauge.create('lsxlib') + rg.setSymbolic( True ) + dirM1 = RoutingLayerGauge.Vertical + dirM2 = RoutingLayerGauge.Horizontal + netBuilderStyle = 'HV,3RL+' + routingStyle = StyleFlags.HV + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL1' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.PinOnly # layer usage + , 0 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(5.0) # track pitch + , l( 2.0) # wire width + , l( 2.0) # perpandicular wire width + , l( 1.0) # VIA side + , l( 3.5) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL2' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 1 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(5.0) # track pitch + , l( 2.0) # wire width + , l( 2.0) # perpandicular wire width + , l( 1.0) # VIA side + , l( 4.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL3' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 2 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(5.0) # track pitch + , l( 2.0) # wire width + , l( 2.0) # perpandicular wire width + , l( 1.0) # VIA side + , l( 4.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL4' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 3 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(5.0) # track pitch + , l( 2.0) # wire width + , l( 2.0) # perpandicular wire width + , l( 1.0) # VIA side + , l( 4.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL5' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 4 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(5.0) # track pitch + , l( 2.0) # wire width + , l( 2.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 4.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL6' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.PowerSupply # layer usage + , 5 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(7.5) # track pitch + , l(6.0) # wire width + , l(6.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 4.0 ) )) # obstacle dW + af.addRoutingGauge( rg ) + af.setRoutingGauge( 'lsxlib' ) + + cg = CellGauge.create( 'lsxlib' + , 'METAL1' # pin layer name. + , l( 5.0) # pitch. + , l(50.0) # cell slice height. + , l( 5.0) # cell slice step. + ) + af.addCellGauge( cg ) + af.setCellGauge( 'lsxlib' ) + + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + # Place & Route setup + cfg.viewer.minimumSize = 500 + cfg.viewer.pixelThreshold = 2 + cfg.lefImport.minTerminalWidth = 0.0 + cfg.crlcore.groundName = 'vss' + cfg.crlcore.powerName = 'vdd' + cfg.etesian.bloat = 'disabled' + cfg.etesian.aspectRatio = 1.00 + cfg.etesian.aspectRatio = [10, 1000] + cfg.etesian.spaceMargin = 0.10 + cfg.etesian.densityVariation = 0.05 + cfg.etesian.routingDriven = False + cfg.etesian.latchUpDistance = l(1000.0) + #cfg.etesian.diodeName = 'diode' + #cfg.etesian.antennaInsertThreshold = 0.50 + #cfg.etesian.antennaMaxWL = u(250.0) + cfg.etesian.feedNames = 'tie_x0,rowend_x0' + cfg.etesian.defaultFeed = 'tie_x0' + cfg.etesian.cell.zero = 'zero_x0' + cfg.etesian.cell.one = 'one_x0' + cfg.etesian.effort = 2 + cfg.etesian.effort = ( ('Fast' , 1) + , ('Standard', 2) + , ('High' , 3) + , ('Extreme' , 4) + ) + cfg.etesian.graphics = 2 + cfg.etesian.graphics = ( ('Show every step' , 1) + , ('Show lower bound', 2) + , ('Show result only', 3) + ) + cfg.anabatic.routingGauge = 'lsxlib' + cfg.anabatic.cellGauge = 'lsxlib' + cfg.anabatic.globalLengthThreshold = 30*l(50.0) + cfg.anabatic.saturateRatio = 0.90 + cfg.anabatic.saturateRp = 10 + cfg.anabatic.topRoutingLayer = 'METAL5' + cfg.anabatic.edgeLength = 24 + cfg.anabatic.edgeWidth = 4 + cfg.anabatic.edgeCostH = 9.0 + cfg.anabatic.edgeCostK = -10.0 + cfg.anabatic.edgeHInc = 1.0 + cfg.anabatic.edgeHScaling = 1.0 + cfg.anabatic.globalIterations = 10 + cfg.anabatic.globalIterations = [ 1, 100 ] + cfg.anabatic.gcell.displayMode = 1 + cfg.anabatic.gcell.displayMode = (("Boundary", 1), ("Density", 2)) + cfg.anabatic.netBuilderStyle = netBuilderStyle + cfg.anabatic.routingStyle = routingStyle + cfg.katana.disableStackedVias = False + cfg.katana.hTracksReservedMin = 4 + cfg.katana.hTracksReservedLocal = 11 + cfg.katana.hTracksReservedLocal = [0, 20] + cfg.katana.vTracksReservedMin = 4 + cfg.katana.vTracksReservedLocal = 11 + cfg.katana.vTracksReservedLocal = [0, 20] + cfg.katana.termSatReservedLocal = 8 + cfg.katana.termSatThreshold = 9 + cfg.katana.eventsLimit = 4000002 + cfg.katana.ripupCost = 3 + cfg.katana.ripupCost = [0, None] + cfg.katana.strapRipupLimit = 16 + cfg.katana.strapRipupLimit = [1, None] + cfg.katana.localRipupLimit = 9 + cfg.katana.localRipupLimit = [1, None] + cfg.katana.globalRipupLimit = 5 + cfg.katana.globalRipupLimit = [1, None] + cfg.katana.longGlobalRipupLimit = 5 + cfg.chip.padCoreSide = 'North' + # Plugins setup + cfg.clockTree.minimumSide = l(50.0) * 6 + cfg.clockTree.buffer = 'buf_x8' + cfg.clockTree.placerEngine = 'Etesian' + cfg.block.spareSide = 10*l(50.0) + cfg.spares.buffer = 'buf_x8' + cfg.spares.maxSinks = 31 + + +def _loadLsxlib ( cellsTop ): + """ + Setup for NSXLIB2 Alliance library. It is an symbolic library + from which cells are loaded on demand, so we only setup pathes. + + :param cellsTop: The top directory containing the cells views. + """ + af = AllianceFramework.get() + env = af.getEnvironment() + env.setSCALE_X ( 50 ) + env.setCATALOG ( 'CATAL' ) + env.setPOWER ( 'vdd' ) + env.setGROUND ( 'vss' ) + env.setCLOCK ( '^ck$|m_clock|^clk$' ) + env.setBLOCKAGE( 'blockage[Nn]et.*' ) + env.setPad ( '.*_mpx$' ) + env.setRegister( 'sff.*' ) + env.setWORKING_LIBRARY( '.' ) + env.addSYSTEM_LIBRARY ( library=(cellsTop / 'lsxlib').as_posix(), mode=Environment.Append ) + +def setup ( cellsTop ): + + _routing() + _loadLsxlib( cellsTop ) diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/sg13g2_lsx.rds b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/sg13g2_lsx.rds new file mode 100644 index 000000000..2e19f72ce --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/sg13g2_lsx.rds @@ -0,0 +1,562 @@ +# 20240801 +# --------------------------------------------------------------------------- +# For sg13g2 +# --------------------------------------------------------------------------- + + + + +# ------------------------------------------------------------------- +# globals define +# ------------------------------------------------------------------- + +define physical_grid 0.001 +define lambda 0.110 + +table cif_layer +# ------------------------------------------------------------------- +# rds_name cif_name +# ------------------------------------------------------------------- + rds_nwell nwel +# rds_pwell pwel + rds_activ active + rds_ntie nplus + rds_ptie pplus + rds_nimp nplus + rds_pimp pplus + rds_poly poly + rds_alu1 metal1 + rds_alu2 metal2 + rds_alu3 metal3 + rds_alu4 metal4 + rds_alu5 metal5 + rds_alu6 metal6 + rds_cont contact + rds_via1 via1 + rds_via2 via2 + rds_via3 via3 + rds_via4 via4 + rds_via5 via5 + rds_cpas pad +end + +table gds_layer +# ------------------------------------------------------------------- +# rds_name gds_number +# ------------------------------------------------------------------- + rds_nwell 31 +# rds_pwell + rds_activ 1 + rds_ptie 14 + rds_ntie 7 + rds_pimp 14 + rds_nimp 7 + rds_poly 5 5 + rds_alu1 8 8 + rds_alu2 10 10 + rds_alu3 30 30 + rds_alu4 50 50 + rds_alu5 67 67 + rds_alu6 0 0 + rds_cont 6 + rds_via1 19 + rds_via2 29 + rds_via3 49 + rds_via4 66 + rds_via5 0 + rds_cpas 0 +end + +table lynx_resistor +# ------------------------------------------------------------------- +# rds_name square_resistor(ohm/square) # typical values +# ------------------------------------------------------------------- + rds_poly 48 + rds_alu1 13 + rds_alu2 0.125 + rds_alu3 0.125 + rds_alu4 0.047 + rds_alu5 0.047 + rds_alu6 0.029 + rds_cont 15 + rds_via1 152 + rds_via2 4.5 + rds_via3 3.4 + rds_via4 3.4 + rds_via5 0.38 +end + +table lynx_capa +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- + rds_poly 25.2e-6 51.8e-6 # Ca max POLY_NWELL 2Cf0 max POLY_NWELL + rds_alu1 2.6e-5 8.5e-5 # Ca max M1_NWELL 2Cf0 max M1_NWELL + rds_alu2 1.6e-5 7.9e-5 # Ca max M2_NWELL 2Cf0 max M2_NWELL + rds_alu3 8.0e-6 6.8e-5 # Ca max M3_NWELL 2Cf0 max M3_NWELL + rds_alu4 6.0e-6 6.0e-5 # Ca max M4_NWELL 2Cf0 max M4_NWELL + rds_alu5 6.0e-6 6.0e-5 # hyp + rds_alu6 6.0e-6 6.0e-5 +end + +table lynx_capa_poly +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_poly2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu1 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu3 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu4 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu5 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end +table mbk_to_rds_segment +# ---------------------------------------------------------------------------------- +# mbk_name rds_name1 dlr dwr offset mode rds_name2 dlr dwr offset mode +# ---------------------------------------------------------------------------------- + + nwell rds_nwell vw 0.460 0.180 .0 all\ + rds_pimp vw 0.090 -0.080 .0 all + + pwell rds_pwell vw 0.460 0.180 .0 all\ + rds_nimp vw 0.090 -0.080 .0 all + + ndif rds_activ vw 0.040 -0.030 .0 all\ + rds_ndif vw 0.040 -0.030 .0 ext + + pdif rds_activ vw 0.040 -0.030 .0 all\ + rds_pdif vw 0.040 -0.030 .0 ext + + ntie rds_activ vw 0.150 -0.030 .0 all\ + rds_ntie vw 0.180 0.030 .0 all\ + rds_nwell vw 0.460 0.670 .0 all + + ptie rds_activ vw 0.150 -0.030 .0 all\ + rds_ptie vw 0.180 0.030 .0 all\ + rds_pwell vw 0.460 0.670 .0 all + + ntrans rds_poly vw 0.000 0.020 .0 all\ + rds_activ vw -0.180 0.480 .0 drc\ + rds_ndif lcw -0.180 0.240 0.010 ext\ + rds_ndif rcw -0.180 0.240 0.010 ext + + ptrans rds_poly vw 0.000 0.020 .0 all\ + rds_activ vw -0.180 0.480 .0 drc\ + rds_pdif lcw -0.180 0.240 0.010 ext\ + rds_pdif rcw -0.180 0.240 0.010 ext + + poly rds_poly vw 0.065 0.020 .0 all + + alu1 rds_alu1 vw 0.130 0.040 .0 all + calu1 rds_alu1 vw 0.130 0.040 .0 all + talu1 rds_talu1 vw 0.130 0.040 .0 all + + alu2 rds_alu2 vw 0.145 0.070 .0 all + calu2 rds_alu2 vw 0.145 0.070 .0 all + talu2 rds_talu2 vw 0.145 0.070 .0 all + + alu3 rds_alu3 vw 0.145 0.070 .0 all + calu3 rds_alu3 vw 0.145 0.070 .0 all + talu3 rds_talu3 vw 0.145 0.070 .0 all +end + +table mbk_to_rds_connector +# ------------------------------------------------------------------- +# mbk_name rds_name der dwr +# ------------------------------------------------------------------- +end + +table mbk_to_rds_reference +# ------------------------------------------------------------------- +# mbk_name rds_name width +# ------------------------------------------------------------------- + ref_ref rds_ref 0.260 + ref_con rds_ref 0.260 +end + +table mbk_to_rds_via +# ------------------------------------------------------------------- +# mbk_name rds_name1 width mode rds_name2 width mode ... +## ------------------------------------------------------------------ + cont_body_n \ + rds_cont 0.160 all\ + rds_alu1 0.260 all\ + rds_activ 0.300 drc\ + rds_ntie 0.300 ext + + cont_body_p \ + rds_cont 0.160 all\ + rds_alu1 0.260 all\ + rds_activ 0.300 drc\ + rds_ptie 0.300 ext + + cont_dif_n \ + rds_cont 0.160 all\ + rds_alu1 0.260 all\ + rds_activ 0.300 drc\ + rds_ndif 0.300 ext + + cont_dif_p \ + rds_cont 0.160 all\ + rds_alu1 0.260 all\ + rds_activ 0.300 drc\ + rds_pdif 0.300 ext + + cont_poly \ + rds_cont 0.160 all\ + rds_poly 0.300 all\ + rds_alu1 0.260 all + + cont_via \ + rds_via1 0.190 all\ + rds_alu1 0.290 all\ + rds_alu2 0.290 all + + cont_via2 \ + rds_via2 0.190 all\ + rds_alu2 0.290 all\ + rds_alu3 0.290 all +end + +table mbk_to_rds_bigvia_hole +# ------------------------------------------------------------------- +# mbk_via_name rds_hole_name side step mode +# ------------------------------------------------------------------- +end + +table mbk_to_rds_bigvia_metal +# ------------------------------------------------------------------- +# mbk_via_name rds_name dwr overlap mode +# ------------------------------------------------------------------- +end + +table mbk_to_rds_turnvia +# ------------------------------------------------------------------- +# mbk_name rds_name dwr mode +# ------------------------------------------------------------------- + cont_turn1 rds_alu1 0.040 all + cont_turn2 rds_alu2 0.070 all + cont_turn3 rds_alu3 0.070 all + cont_turn8 rds_poly 0.080 all +end + +table lynx_bulk_implicit +# ------------------------------------------------------------------- +# rds_name type[explicit|implicit] +# ------------------------------------------------------------------- +end + +table lynx_transistor +# ------------------------------------------------------------------- +# mbk_name trans_name compostion +# ------------------------------------------------------------------- + NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL + PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL +end + +table lynx_diffusion +# ------------------------------------------------------------------- +# rds_name compostion +# ------------------------------------------------------------------- + rds_ndif rds_activ 1 rds_nimp 1 rds_nwell 0 + rds_pdif rds_activ 1 rds_pimp 1 rds_nwell 1 + rds_ntie rds_activ 1 rds_nimp 1 rds_nwell 1 + rds_ptie rds_activ 1 rds_pimp 1 rds_nwell 0 +end + +table lynx_graph +# ------------------------------------------------------------------- +# rds_name in_contact_with rds_name1 rds_name2 ... +# ------------------------------------------------------------------- + rds_ndif rds_cont rds_ndif + rds_pdif rds_cont rds_pdif + rds_poly rds_cont rds_poly + rds_cont rds_pdif rds_ndif rds_poly rds_alu1 rds_cont + rds_alu1 rds_cont rds_via1 rds_ref rds_alu1 + rds_ref rds_cont rds_via1 rds_alu1 rds_ref + rds_alu2 rds_via1 rds_via2 rds_alu2 + rds_alu3 rds_via2 rds_alu3 +end + +table s2r_oversize_denotch +# ------------------------------------------------------------------- +# rds_name oversized_value_for_denotching +# ------------------------------------------------------------------- + rds_nwell 0.900 + rds_pwell 0.900 + rds_poly 0.089 + rds_alu1 0.089 + rds_alu2 0.104 + rds_alu3 0.104 + rds_activ 0.104 + rds_ntie 0.155 + rds_ptie 0.155 + rds_nimp 0.155 + rds_pimp 0.155 +end + +table s2r_bloc_ring_width +# ------------------------------------------------------------------- +# rds_name ring_width_to_copy_up +# ------------------------------------------------------------------- + rds_nwell 0. # [ RD_NWEL ] + rds_pwell 0. # [ RD_PWEL ] + rds_poly 0. # [ RD_POLY ] + rds_alu1 0. # [ RD_ALU1 ] + rds_alu2 0. # [ RD_ALU2 ] + rds_alu3 0. # [ RD_ALU3 ] + rds_activ 0. # [ RD_ACTI ] + rds_ntie 0. # [ RD_NIMP ] + rds_ptie 0. # [ RD_PIMP ] + rds_nimp 0. # [ RD_NIMP ] + rds_pimp 0. # [ RD_PIMP ] +end + +table s2r_minimum_layer_width +# ------------------------------------------------------------------- +# rds_name min_layer_width_to_keep +# ------------------------------------------------------------------- + rds_nwell 0.620 + rds_pwell 0.620 + rds_poly 0.130 + rds_alu1 0.260 + rds_alu2 0.290 + rds_alu3 0.290 + rds_activ 0.300 + rds_ntie 0.310 + rds_ptie 0.310 + rds_nimp 0.310 + rds_pimp 0.310 +end + +table s2r_post_treat +# ------------------------------------------------------------------- +# rds_name s2r_must_treat_or_not second_layer_whenever_scotch +# ------------------------------------------------------------------- + rds_nwell treat null + rds_pwell treat null + rds_poly treat null + rds_activ treat null + rds_ntie treat rds_pimp + rds_ptie treat rds_nimp + rds_nimp treat rds_ptie + rds_pimp treat rds_ntie + rds_alu1 treat null + rds_alu2 treat null + rds_alu3 treat null + rds_cont notreat null +end + +DRC_RULES + +layer RDS_NWELL 0.620 ; +layer RDS_NTIE 0.150 ; +layer RDS_PTIE 0.150 ; +layer RDS_NIMP 0.310 ; +layer RDS_PIMP 0.310 ; +layer RDS_ACTIV 0.150 ; +layer RDS_CONT 0.160 ; +layer RDS_POLY 0.130 ; +layer RDS_ALU1 0.160 ; +layer RDS_ALU2 0.200 ; +layer RDS_ALU3 0.200 ; +layer RDS_USER0 0.001 ; +layer RDS_USER1 0.001 ; +layer RDS_USER2 0.001 ; + +regles + +# note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# there is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# ---------------------------------------------------------- + +# check the nwell shapes +# ---------------------- +caracterise RDS_NWELL ( + regle 1 : largeur >= 0.620 ; + regle 2 : longueur_inter min 0.620 ; + regle 3 : notch >= 1.800 ; +); +relation RDS_NWELL , RDS_NWELL ( + regle 4 : distance axiale min 1.800 ; +); +relation RDS_NWELL , RDS_ACTI ( + regle 5 : distance axiale min 0.620 ; +); + +# check the RDS_PIMP shapes +# ------------------------- +caracterise RDS_PIMP ( + regle 6 : surface min 0.250 ; + regle 7 : largeur >= 0.310 ; + regle 8 : longueur_inter min 0.310 ; + regle 9 : notch >= 0.310 ; +); +relation RDS_PIMP , RDS_PIMP ( + regle 10 : distance axiale min 0.310 ; +); + +# check the RDS_NIMP shapes +# ------------------------- +caracterise RDS_NIMP ( + regle 11 : surface min 0.250 ; + regle 12 : largeur >= 0.310 ; + regle 13 : longueur_inter min 0.310 ; + regle 14 : notch >= 0.310 ; +); +relation RDS_NIMP , RDS_NIMP ( + regle 15 : distance axiale min 0.310 ; +); + +# check the RDS_PTIE shapes +# ------------------------- +caracterise RDS_PTIE ( + regle 16 : surface min 0.250 ; + regle 17 : largeur >= 0.310 ; + regle 18 : longueur_inter min 0.310 ; + regle 19 : notch >= 0.310 ; +); +relation RDS_PTIE , RDS_PTIE ( + regle 20 : distance axiale min 0.310 ; +); + +# check the RDS_NTIE shapes +# ------------------------- +caracterise RDS_NTIE ( + regle 21 : surface min 0.250 ; + regle 22 : largeur >= 0.310 ; + regle 23 : longueur_inter min 0.310 ; + regle 24 : notch >= 0.310 ; +); +relation RDS_NTIE , RDS_NTIE ( + regle 25 : distance axiale min 0.310 ; +); + +# check the RDS_ACTI shapes +# ------------------------- +caracterise RDS_ACTI ( + regle 26 : surface min 1.222 ; + regle 27 : largeur >= 0.150 ; + regle 28 : longueur_inter min 0.150 ; + regle 29 : notch >= 0.210 ; +); +relation RDS_ACTI, RDS_ACTI ( + regle 30 : distance axiale min 0.210 ; +); + +# check the RDS_NIMP RDS_PTIE exclusion +# ------------------------------------- +define RDS_NIMP , RDS_PTIE intersection -> NPIMP; +caracterise NPIMP ( + regle 31 : largeur = 0. ; +); +undefine NPIMP; + +# check the RDS_NTIE RDS_PIMP exclusion +# ------------------------------------- +define RDS_NTIE , RDS_PIMP intersection -> NPIMP; +caracterise NPIMP ( + regle 32 : largeur = 0. ; +); +undefine NPIMP; + +# check the RDS_POLY shapes +# ------------------------- +caracterise RDS_POLY ( + regle 33 : largeur >= 0.130 ; + regle 34 : longueur_inter min 0.130 ; + regle 35 : notch >= 0.180 ; +); +relation RDS_POLY , RDS_POLY ( + regle 36 : distance axiale min 0.180 ; +); + +define RDS_ACTI , RDS_POLY intersection -> channel; + + # check the channel shapes + # ------------------------- + caracterise channel ( + regle 37 : notch >= 0.180 ; + ); + relation channel , channel ( + regle 38 : distance axiale min 0.180 ; + ); + +undefine channel; + +define RDS_ACTI , RDS_CONT intersection -> cont_diff; + + relation RDS_POLY , cont_diff ( + regle 39 : distance axiale >= 0.110 ; + ); + +undefine cont_diff; + +# check RDS_ALU1 shapes +# --------------------- +caracterise RDS_ALU1 ( + regle 40 : surface min 0.090 ; + regle 41 : largeur >= 0.160 ; + regle 42 : longueur_inter min 0.160 ; + regle 43 : notch >= 0.180 ; +); +relation RDS_ALU1 , RDS_ALU1 ( + regle 44 : distance axiale min 0.180 ; +); + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_CONT , RDS_CONT ( + regle 45 : distance axiale >= 0.180 ; +); + +caracterise RDS_CONT ( + regle 46 : largeur = 0.160 ; + regle 47 : longueur = 0.160 ; +); + +# check RDS_POLY is distant from activ zone of transistor +# ------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + regle 48 : distance axiale >= 0.070 ; +); + +fin regles +DRC_COMMENT +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/spimodel.cfg b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/spimodel.cfg new file mode 100644 index 000000000..636595d08 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/spimodel.cfg @@ -0,0 +1,5 @@ +# MBK_SPI_MODEL +# configure the transistor models of spi parser/driver +# +sg13_lv_nmos N +sg13_lv_pmos P diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/symbolic.dreal b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/symbolic.dreal new file mode 100644 index 000000000..3c39bd85c --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/symbolic.dreal @@ -0,0 +1,127 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Dreal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 02/08/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +dEFINE DREAL_LOWER_FIGURE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_INSTANCE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_CONNECTOR_STEP 0.5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_SEGMENT_STEP 0.7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_REFERENCE_STEP 1.0 + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TAbLE DREAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/symbolic.graal b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/symbolic.graal new file mode 100644 index 000000000..5b380757b --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/symbolic.graal @@ -0,0 +1,387 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Graal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 27/06/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Graal Peek Bound in lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_PEEK_BOUND 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_FIGURE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_INSTANCE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_CONNECTOR_STEP 5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_SEGMENT_STEP 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_REFERENCE_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | Segment Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_NAME + + NWELL Nwell tan Black + PWELL Pwell light_yellow Black + NDIF Ndif lawn_green Black + PDIF Pdif yellow Black + NTIE Ntie spring_green Black + PTIE Ptie light_goldenrod Black + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 GReen Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + TPOLY Tpoly hot_pink Black + TALU1 Talu1 royal_blue Black + TALU2 Talu2 turquoise Black + TALU3 Talu3 light_pink Black + TALU4 Talu4 green Black + TALU5 Talu5 yellow Black + TALU6 Talu6 violet Black + TALU7 Talu7 red Black + TALU8 Talu8 blue Black + CALU1 CAlu1 royal_blue Black + CALU2 CAlu2 Cyan Black + CALU3 CAlu3 light_pink Black + CALU4 CAlu4 green Black + CALU5 CAlu5 yellow Black + CALU6 CAlu6 violet Black + CALU7 CAlu7 red Black + CALU8 CAlu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Transistor Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_TRANSISTOR_NAME + + NTRANS Ntrans lawn_green Black + PTRANS Ptrans yellow Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Connector Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_CONNECTOR_NAME + + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 green Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Length and Width for a symbolic Segment | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_VALUE + + NWELL 4 4 + PWELL 4 4 + NDIF 3 2 # LSX 2 -> 3 + PDIF 3 2 # LSX 2 -> 3 + NTIE 3 1 # LSX 2 -> 3 + PTIE 3 1 # LSX 2 -> 3 + NTRANS 1 5 # LSX 4 -> 5 + PTRANS 1 5 # LSX 4 -> 5 + POLY 1 1 + POLY2 1 1 + ALU1 2 1 # LSX 1 -> 2 + ALU2 2 1 + ALU3 2 1 + ALU4 2 1 + ALU5 2 1 + ALU6 2 1 + ALU7 2 1 + ALU8 2 1 + TPOLY 1 1 + TALU1 2 1 # LSX 1 -> 2 + TALU2 2 1 # LSX 2 -> 1 + TALU3 2 1 # LSX 2 -> 1 + TALU4 2 1 # LSX 2 -> 1 + TALU5 2 1 # LSX 2 -> 1 + TALU6 2 1 # LSX 2 -> 1 + TALU7 2 1 # LSX 2 -> 1 + TALU8 2 1 # LSX 2 -> 1 + CALU1 2 0 + CALU2 2 0 + CALU3 2 0 + CALU4 2 0 + CALU5 2 0 + CALU6 2 0 + CALU7 2 0 + CALU8 2 0 + +END + +# /*------------------------------------------------------------\ +# | | +# | Reference Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_REFERENCE_NAME + + REF_REF Ref_Ref red Black + REF_CON Ref_Con Cyan Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_VIA_NAME + + CONT_DIF_N Cont_NDif lawn_green Black + CONT_DIF_P Cont_PDif yellow Black + CONT_BODY_N Cont_NTie spring_green Black + CONT_BODY_P Cont_PTie light_goldenrod Black + CONT_POLY Cont_Poly red Black + CONT_POLY2 Cont_Poly2 orange Black + CONT_VIA Via_1-2 cyan Black + CONT_VIA2 Via_2-3 light_pink Black + CONT_VIA3 Via_3-4 green Black + CONT_VIA4 Via_4-5 yellow Black + CONT_VIA5 Via_5-6 violet Black + CONT_VIA6 Via_6-7 red Black + CONT_VIA7 Via_7-8 blue Black + C_X_N Cont_CxN orange Black + C_X_P Cont_CxP orange Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Big Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_NAME + + CONT_VIA Big_Via_1-2 cyan Black + CONT_VIA2 Big_Via_2-3 light_pink Black + CONT_VIA3 Big_Via_3-4 green Black + CONT_VIA4 Big_Via_4-5 yellow Black + CONT_VIA5 Big_Via_5-6 violet Black + CONT_VIA6 Big_Via_6-7 red Black + CONT_VIA7 Big_Via_7-8 blue Black + + CONT_TURN1 Turn_Via_0 red Black + CONT_TURN1 Turn_Via_1 royal_blue Black + CONT_TURN2 Turn_Via_2 Cyan Black + CONT_TURN3 Turn_Via_3 light_pink Black + CONT_TURN4 Turn_Via_4 green Black + CONT_TURN5 Turn_Via_5 yellow Black + CONT_TURN6 Turn_Via_6 violet Black + CONT_TURN7 Turn_Via_7 blue Black + CONT_TURN8 Turn_Via_8 red Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Size for a symbolic Big Via | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_VALUE + + CONT_VIA 2 + CONT_VIA2 2 + CONT_VIA3 2 + CONT_VIA4 2 + CONT_VIA5 2 + CONT_VIA6 2 + CONT_VIA7 2 + + CONT_TURN1 2 + CONT_TURN2 2 + CONT_TURN3 2 + CONT_TURN4 2 + CONT_TURN5 2 + CONT_TURN6 2 + CONT_TURN7 2 + CONT_TURN8 2 + +END + +# /*------------------------------------------------------------\ +# | | +# | Orient Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_ORIENT_NAME + + NORTH North lawn_green Black + SOUTH South yellow Black + EAST East tan Black + WEST West red Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Symmetry Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SYMMETRY_NAME + + NOSYM No_Sym LightBlue Black + SYM_X Sym_X turquoise Black + SYM_Y Sym_Y cyan Black + SYMXY Sym_XY lightCyan Black + ROT_P Rot_P MediumAquamarine Black + ROT_M Rot_M aquamarine Black + SY_RP Sym_RP green Black + SY_RM Sym_RM MediumSpringGreen Black + +END + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/symbolic.rds b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/symbolic.rds new file mode 100644 index 000000000..3f90d923e --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/symbolic.rds @@ -0,0 +1,950 @@ +#===================================================================== +# +# ALLIANCE VLSI CAD +# (R)eal (D)ata (S)tructure parameter file +# (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI +# all rights reserved +# e-mail : cao-vlsi@masi.ibp.fr +# +# file : cmos.rds +# version : 12 +# last modif : Apr 4, 2002, Feb 24, 2023 +# +##------------------------------------------------------------------- +# Symbolic to micron on a 'one lambda equals one micron' basis +##------------------------------------------------------------------- +# Refer to the documentation for more precise information. +#===================================================================== +# 1/05/23 +# . no more CXN and CXP +# +# 01/11/09 ALU5/6 pitch 10 +# +# 99/11/3 ALU5/6 rules +# . theses rules are preliminary rules, we hope that they wil change +# in future. For now, ALU5/6 are dedicated to supplies an clock. +# +# 99/3/22 new symbolics rules +# . ALU1 width remains 1, ALU2/3/4 is 2 +# . ALU1/2/3/4 distance (edge to edge) is now 3 for all +# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2 +# . All via stacking are allowed +# +# 98/12/1 drc rules were updated +# distance VIA to POLY or gate is one rather 2 +# VIA2 and ALU3 appeared +# . ALU3 width is 3 +# . ALU2/VIA2/ALU3 is resp. 3/1/3 +# . ALU3 edge distance is 2 +# . stacked VIA/VIA2 is allowed +# . if they are not stacked they must distant of 2 +# . CONT/VIA2 is free +# note +# . stacked CONT/VIA is always not allowed +# NWELL is automatically drawn with the DIFN and NTIE layers +#===================================================================== + +##------------------------------------------------------------------- +# PHYSICAL_GRID : +##------------------------------------------------------------------- + +DEFINE PHYSICAL_GRID .5 + +##------------------------------------------------------------------- +# LAMBDA : +##------------------------------------------------------------------- + +DEFINE LAMBDA 1 + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_SEGMENT : +# +# MBK RDS layer 1 RDS layer 2 +# name name TRANS DLR DWR OFFSET name TRANS DLR DWR OFFSET ... +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_SEGMENT + + PWELL RDS_PWELL VW 2.0 0.0 0.0 EXT + NWELL RDS_NWELL VW 2.0 0.0 0.0 ALL + NDIF RDS_NDIF VW 0.5 0.0 0.0 ALL + PDIF RDS_PDIF VW 0.5 0.0 0.0 ALL + NTIE RDS_NTIE VW 1.5 0.0 0.0 ALL\ + RDS_NWELL VW 2.0 5.0 0.0 ALL + PTIE RDS_PTIE VW 1.5 0.0 0.0 ALL\ + RDS_PWELL VW 2.0 5.0 0.0 ALL # LSX DLR 0.5 -> 1.5 + NTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \ + RDS_NDIF LCW -1.5 2.5 0.0 EXT \ + RDS_NDIF RCW -1.5 2.5 0.0 EXT \ + RDS_NDIF VW -1.5 6.0 0.0 DRC \ + RDS_ACTIV VW -1.5 6.0 0.0 ALL + PTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \ + RDS_PDIF LCW -1.5 2.5 0.0 EXT \ + RDS_PDIF RCW -1.5 2.5 0.0 EXT \ + RDS_PDIF VW -1.5 6.0 0.0 DRC \ + RDS_ACTIV VW -1.5 6.0 0.0 ALL + POLY RDS_POLY VW 0.5 0.0 0.0 ALL + POLY2 RDS_POLY2 VW 0.5 0.0 0.0 ALL + ALU1 RDS_ALU1 VW 1.0 0.0 0.0 ALL # LSX DLR 0.5 -> 1.0 + ALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL + ALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL + ALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL + ALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL + ALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL + CALU1 RDS_ALU1 VW 1.0 0.0 0.0 ALL + CALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL + CALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL + CALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL + CALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL + CALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL + TPOLY RDS_TPOLY VW 0.5 0.0 0.0 ALL + TALU1 RDS_TALU1 VW 1.0 0.0 0.0 ALL # SX DLR 0.5 -> 1.0 + TALU2 RDS_TALU2 VW 1.0 0.0 0.0 ALL + TALU3 RDS_TALU3 VW 1.0 0.0 0.0 ALL + TALU4 RDS_TALU4 VW 1.0 0.0 0.0 ALL + TALU5 RDS_TALU5 VW 1.0 0.0 0.0 ALL + TALU6 RDS_TALU6 VW 1.0 0.0 0.0 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_CONNECTOR : +# +# MBK RDS layer +# name name DER DWR +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_CONNECTOR + + POLY RDS_POLY .5 0 + POLY2 RDS_POLY2 .5 0 + ALU1 RDS_ALU1 1.0 0 # LSX DER 0.5 -> 1.0 + ALU2 RDS_ALU2 1.0 0 + ALU3 RDS_ALU3 1.0 0 + ALU4 RDS_ALU4 1.0 0 + ALU5 RDS_ALU5 1.0 0 + ALU6 RDS_ALU6 1.0 0 + CALU1 RDS_ALU1 1.0 0 # LSX DER 0.5 -> 1.0 + CALU2 RDS_ALU2 1.0 0 + CALU3 RDS_ALU3 1.0 0 + CALU4 RDS_ALU4 1.0 0 + CALU5 RDS_ALU5 1.0 0 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_REFERENCE : +# +# MBK ref RDS layer +# name name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_REFERENCE + + REF_REF RDS_REF 1 + REF_CON RDS_VALU1 2 RDS_TVIA1 1 RDS_TALU2 2 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_VIA1 : +# +# MBK via RDS layer 1 RDS layer 2 RDS layer 3 RDS layer 4 +# name name width name width name width name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_VIA + + CONT_BODY_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PTIE 3 ALL + CONT_BODY_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NTIE 3 ALL + CONT_DIF_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NDIF 3 ALL + CONT_DIF_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PDIF 3 ALL + CONT_POLY RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY 2 ALL # LSX POLY=3 -> POLY=2 + CONT_POLY2 RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY2 2 ALL # LSX POLY2=3 -> POLY2=2 + CONT_VIA RDS_ALU1 2 ALL RDS_VIA1 1 ALL RDS_ALU2 2 ALL + CONT_VIA2 RDS_ALU2 2 ALL RDS_VIA2 1 ALL RDS_ALU3 2 ALL + CONT_VIA3 RDS_ALU3 2 ALL RDS_VIA3 1 ALL RDS_ALU4 2 ALL + CONT_VIA4 RDS_ALU4 2 ALL RDS_VIA4 1 ALL RDS_ALU5 2 ALL + CONT_VIA5 RDS_ALU5 2 ALL RDS_VIA5 1 ALL RDS_ALU6 2 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_HOLE : +# +# MBK via RDS Hole +# name name side step mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_HOLE + +CONT_VIA RDS_VIA1 1 4 ALL +CONT_VIA2 RDS_VIA2 1 4 ALL +CONT_VIA3 RDS_VIA3 1 4 ALL +CONT_VIA4 RDS_VIA4 1 4 ALL # should be more than 4 +CONT_VIA5 RDS_VIA5 1 4 ALL # should be more than 4 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_METAL : +# +# MBK via RDS layer 1 ... +# name name delta-width overlap mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_METAL + +CONT_VIA RDS_ALU1 0.0 0.5 ALL RDS_ALU2 0.0 0.5 ALL +CONT_VIA2 RDS_ALU2 0.0 0.5 ALL RDS_ALU3 0.0 0.5 ALL +CONT_VIA3 RDS_ALU3 0.0 0.5 ALL RDS_ALU4 0.0 0.5 ALL +CONT_VIA4 RDS_ALU4 0.0 0.5 ALL RDS_ALU5 0.0 0.5 ALL +CONT_VIA5 RDS_ALU5 0.0 0.5 ALL RDS_ALU6 0.0 0.5 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_TURNVIA : +# +# MBK via RDS layer 1 ... +# name name DWR MODE +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_TURNVIA + +CONT_TURN1 RDS_ALU1 0 ALL +CONT_TURN2 RDS_ALU2 0 ALL +CONT_TURN3 RDS_ALU3 0 ALL +CONT_TURN4 RDS_ALU4 0 ALL +CONT_TURN5 RDS_ALU5 0 ALL +CONT_TURN6 RDS_ALU6 0 ALL +CONT_TURN7 RDS_ALU7 0 ALL +CONT_TURN8 RDS_POLY 0 ALL + +END + + +##------------------------------------------------------------------- +# TABLE LYNX_GRAPH : +# +# RDS layer Rds layer 1 Rds layer 2 ... +# name name name ... +##------------------------------------------------------------------- + +TABLE LYNX_GRAPH + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# RDS_NWELL RDS_NTIE RDS_NWELL +# RDS_PWELL RDS_PTIE RDS_PWELL +# RDS_NDIF RDS_CONT RDS_NDIF +# RDS_PDIF RDS_CONT RDS_PDIF +# RDS_NTIE RDS_CONT RDS_NTIE RDS_NWELL +# RDS_PTIE RDS_CONT RDS_PTIE RDS_PWELL + + RDS_NDIF RDS_CONT RDS_NDIF + RDS_PDIF RDS_CONT RDS_PDIF + RDS_NTIE RDS_CONT RDS_NTIE + RDS_PTIE RDS_CONT RDS_PTIE + + RDS_POLY RDS_CONT RDS_POLY + RDS_POLY2 RDS_CONT RDS_POLY2 + RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT + RDS_ALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1 + RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 + RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 + RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 + RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 + RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 + RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 + RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2 + RDS_ALU3 RDS_VIA2 RDS_VIA3 RDS_ALU3 + RDS_ALU4 RDS_VIA3 RDS_VIA4 RDS_ALU4 + RDS_ALU5 RDS_VIA4 RDS_VIA5 RDS_ALU5 + RDS_ALU6 RDS_VIA5 RDS_ALU6 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_CAPA : +# +# RDS layer Surface capacitance Perimetric capacitance +# name piF / Micron^2 piF / Micron +##------------------------------------------------------------------- + +TABLE LYNX_CAPA + + RDS_POLY 1.00e-04 1.00e-04 + RDS_POLY2 1.00e-04 1.00e-04 + RDS_ALU1 0.50e-04 0.90e-04 + RDS_ALU2 0.25e-04 0.95e-04 + RDS_ALU3 0.25e-04 0.95e-04 + RDS_ALU4 0.25e-04 0.95e-04 + RDS_ALU5 0.25e-04 0.95e-04 + RDS_ALU6 0.25e-04 0.95e-04 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_RESISTOR : +# +# RDS layer Surface resistor +# name Ohm / Micron^2 +##------------------------------------------------------------------- + +TABLE LYNX_RESISTOR + + RDS_POLY 50.0 + RDS_POLY2 50.0 + RDS_ALU1 12.0 # LSX .1 -> 12 + RDS_ALU2 0.05 + RDS_ALU3 0.05 + RDS_ALU4 0.05 + RDS_ALU5 0.05 + RDS_ALU6 0.05 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_TRANSISTOR : +# +# MBK layer Transistor Type MBK via +# name name name +##------------------------------------------------------------------- + +TABLE LYNX_TRANSISTOR + + NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL + PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL + +END + +##------------------------------------------------------------------- +# TABLE LYNX_DIFFUSION : +# +# RDS layer RDS layer +# name name +##------------------------------------------------------------------- + +TABLE LYNX_DIFFUSION +END + +##------------------------------------------------------------------- +# TABLE LYNX_BULK_IMPLICIT : +# +# RDS layer Bulk type +# name EXPLICIT/IMPLICIT +##------------------------------------------------------------------- + +TABLE LYNX_BULK_IMPLICIT + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# NWELL EXPLICIT +# PWELL IMPLICIT + +END + + + +##------------------------------------------------------------------- +# TABLE S2R_OVERSIZE_DENOTCH : +##------------------------------------------------------------------- + +TABLE S2R_OVERSIZE_DENOTCH +END + +##------------------------------------------------------------------- +# TABLE S2R_BLOC_RING_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_BLOC_RING_WIDTH +END + +##------------------------------------------------------------------- +# TABLE S2R_MINIMUM_LAYER_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_MINIMUM_LAYER_WIDTH + + RDS_NWELL 4 + RDS_NDIF 3 # LSX 2 -> 3 + RDS_PDIF 3 # LSX 2 -> 3 + RDS_NTIE 3 # LSX 2 -> 3 + RDS_PTIE 3 # LSX 2 -> 3 + RDS_POLY 1 + RDS_POLY2 1 + RDS_TPOLY 1 + RDS_CONT 1 + RDS_ALU1 2 # LSX 1 -> 2 + RDS_TALU1 2 # LSX 1 -> 2 + RDS_VIA1 1 + RDS_ALU2 2 + RDS_TALU2 2 + RDS_VIA2 1 + RDS_ALU3 2 + RDS_TALU3 2 + RDS_VIA3 1 + RDS_ALU4 2 + RDS_TALU4 2 + RDS_VIA4 1 + RDS_ALU5 2 + RDS_TALU5 2 + RDS_VIA5 1 + RDS_ALU6 2 + RDS_TALU6 2 + +END + +##------------------------------------------------------------------- +# TABLE MBK_WIRESETTING : +##------------------------------------------------------------------- +# +# This table is used by ocp, nero & ring. It supplies *symbolic* +# information about the routing grid, the cell gauge and the power +# wires. + + +TABLE MBK_WIRESETTING + + X_GRID 5 + Y_GRID 5 + Y_SLICE 50 + WIDTH_VDD 4 # LSX 6 -> 4 + WIDTH_VSS 4 # LSX 6 -> 4 + TRACK_WIDTH_ALU8 0 + TRACK_WIDTH_ALU7 2 + TRACK_WIDTH_ALU6 2 + TRACK_WIDTH_ALU5 2 + TRACK_WIDTH_ALU4 2 + TRACK_WIDTH_ALU3 2 + TRACK_WIDTH_ALU2 2 + TRACK_WIDTH_ALU1 2 + TRACK_SPACING_ALU8 0 + TRACK_SPACING_ALU7 8 + TRACK_SPACING_ALU6 8 + TRACK_SPACING_ALU5 3 + TRACK_SPACING_ALU4 3 + TRACK_SPACING_ALU3 3 + TRACK_SPACING_ALU2 3 + TRACK_SPACING_ALU1 3 + +END + + +##------------------------------------------------------------------- +# TABLE CIF_LAYER : +##------------------------------------------------------------------- + +TABLE CIF_LAYER + + RDS_NWELL LNWELL + RDS_NDIF LNDIF + RDS_PDIF LPDIF + RDS_NTIE LNTIE + RDS_PTIE LPTIE + RDS_POLY LPOLY + RDS_POLY2 LPOLY2 + RDS_TPOLY LTPOLY + RDS_CONT LCONT + RDS_ALU1 LALU1 + RDS_VALU1 LVALU1 + RDS_TALU1 LTALU1 + RDS_VIA1 LVIA + RDS_TVIA1 LTVIA1 + RDS_ALU2 LALU2 + RDS_TALU2 LTALU2 + RDS_VIA2 LVIA2 + RDS_ALU3 LALU3 + RDS_TALU3 LTALU3 + RDS_VIA3 LVIA3 + RDS_ALU4 LALU4 + RDS_TALU4 LTALU4 + RDS_VIA4 LVIA4 + RDS_ALU5 LALU5 + RDS_TALU5 LTALU5 + RDS_VIA5 LVIA5 + RDS_ALU6 LALU6 + RDS_TALU6 LTALU6 + RDS_REF LREF + +END + +##------------------------------------------------------------------- +# TABLE GDS_LAYER : +##------------------------------------------------------------------- + +TABLE GDS_LAYER + + RDS_NWELL 1 + RDS_NDIF 3 + RDS_PDIF 4 + RDS_NTIE 5 + RDS_PTIE 6 + RDS_POLY 7 + RDS_POLY2 8 + RDS_TPOLY 9 + RDS_CONT 10 + RDS_ALU1 11 11 + RDS_VALU1 12 + RDS_TALU1 13 + RDS_VIA1 14 + RDS_TVIA1 15 + RDS_ALU2 16 16 + RDS_TALU2 17 + RDS_VIA2 18 + RDS_ALU3 19 19 + RDS_TALU3 20 + RDS_VIA3 21 + RDS_ALU4 22 22 + RDS_TALU4 23 + RDS_VIA4 25 + RDS_ALU5 26 26 + RDS_TALU5 27 + RDS_VIA5 28 + RDS_ALU6 29 29 + RDS_TALU6 30 + RDS_REF 24 + +END + +##------------------------------------------------------------------- +# TABLE S2R_POST_TREAT : +##------------------------------------------------------------------- + +TABLE S2R_POST_TREAT + +END +DRC_RULES + +layer RDS_NWELL 4.; +layer RDS_NTIE 3.; # LSX 2 -> 3 +layer RDS_PTIE 3.; # LSX 2 -> 3 +layer RDS_NDIF 3.; # LSX 2 -> 3 +layer RDS_PDIF 3.; # LSX 2 -> 3 +layer RDS_ACTIV 2.; +layer RDS_CONT 1.; +layer RDS_VIA1 1.; +layer RDS_VIA2 1.; +layer RDS_VIA3 1.; +layer RDS_VIA4 1.; +layer RDS_VIA5 1.; +layer RDS_POLY 1.; +layer RDS_POLY2 1.; +layer RDS_ALU1 2.; # LSX 1 -> 2 +layer RDS_ALU2 2.; +layer RDS_ALU3 2.; +layer RDS_ALU4 2.; +layer RDS_ALU5 2.; +layer RDS_ALU6 2.; +layer RDS_USER0 1.; +layer RDS_USER1 1.; +layer RDS_USER2 1.; + +regles + +# Note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# There is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# There is no rule to check NTIE and PDIF are included in NWELL +# since this is necessarily true +#----------------------------------------------------------- + +# Check the NWELL shapes +#----------------------- +caracterise RDS_NWELL ( + regle 1 : largeur >= 4. ; + regle 2 : longueur_inter min 4. ; + regle 3 : notch >= 12. ; +); +relation RDS_NWELL , RDS_NWELL ( + regle 4 : distance axiale min 12. ; +); + +# Check RDS_PTIE is really excluded outside NWELL +#------------------------------------------------ +relation RDS_PTIE , RDS_NWELL ( + regle 5 : distance axiale >= 7.5; + regle 6 : enveloppe longueur_inter < 0. ; + regle 7 : marge longueur_inter < 0. ; + regle 8 : croix longueur_inter < 0. ; + regle 9 : intersection longueur_inter < 0. ; + regle 10 : extension longueur_inter < 0. ; + regle 11 : inclusion longueur_inter < 0. ; +); + +# Check RDS_NDIF is really excluded outside NWELL +#------------------------------------------------ +relation RDS_NDIF , RDS_NWELL ( + regle 12 : distance axiale >= 7.5; + regle 13 : enveloppe longueur_inter < 0. ; + regle 14 : marge longueur_inter < 0. ; + regle 15 : croix longueur_inter < 0. ; + regle 16 : intersection longueur_inter < 0. ; + regle 17 : extension longueur_inter < 0. ; + regle 18 : inclusion longueur_inter < 0. ; +); + +# Check the RDS_PDIF shapes +#-------------------------- +caracterise RDS_PDIF ( + regle 19 : largeur >= 3. ; # LSX 2 -> 3 + regle 20 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 21 : notch >= 3. ; +); +relation RDS_PDIF , RDS_PDIF ( + regle 22 : distance axiale min 3. ; +); + +# Check the RDS_NDIF shapes +#-------------------------- +caracterise RDS_NDIF ( + regle 23 : largeur >= 3. ; # LSX 2 -> 3 + regle 24 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 25 : notch >= 3. ; +); +relation RDS_NDIF , RDS_NDIF ( + regle 26 : distance axiale min 3. ; +); + +# Check the RDS_PTIE shapes +#-------------------------- +caracterise RDS_PTIE ( + regle 27 : largeur >= 3. ; # LSX 2 -> 3 + regle 28 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 29 : notch >= 3. ; +); +relation RDS_PTIE , RDS_PTIE ( + regle 30 : distance axiale min 3. ; +); + +# Check the RDS_NTIE shapes +#-------------------------- +caracterise RDS_NTIE ( + regle 31 : largeur >= 3. ; # LSX 2 -> 3 + regle 32 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 33 : notch >= 3. ; +); +relation RDS_NTIE , RDS_NTIE ( + regle 34 : distance axiale min 3. ; +); + +define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF; +define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF; + +# Check the ANY_N_DIF ANY_P_DIFF exclusion +#-------------------------------------- +relation ANY_N_DIF , ANY_P_DIF ( + regle 35 : distance axiale >= 3. ; + regle 36 : enveloppe longueur_inter < 0. ; + regle 37 : marge longueur_inter < 0. ; + regle 38 : croix longueur_inter < 0. ; + regle 39 : intersection longueur_inter < 0. ; + regle 40 : extension longueur_inter < 0. ; + regle 41 : inclusion longueur_inter < 0. ; +); + +undefine ANY_P_DIF; +undefine ANY_N_DIF; + +define RDS_NDIF , RDS_PDIF union -> NP_DIF; + +# Check RDS_POLY related to NP_DIF +#--------------------------------- +relation RDS_POLY , NP_DIF ( + regle 42 : distance axiale >= 1. ; + regle 43 : intersection longueur_inter < 0. ; +); + +define NP_DIF , RDS_POLY intersection -> CHANNEL; + +# Check the RDS_POLY shapes +#-------------------------- +caracterise RDS_POLY ( + regle 44 : largeur >= 1. ; + regle 45 : longueur_inter min 1. ; + regle 46 : notch >= 2.5 ; # LSX 2 -> 2.5 +); +relation RDS_POLY , RDS_POLY ( + regle 47 : distance axiale min 2.5; # LSX 2 -> 2.5 +); + +define NP_DIF , RDS_CONT intersection -> CONT_DIFF; +# Check the CHANNEL shapes +#-------------------------- +caracterise CHANNEL ( + regle 48 : notch >= 3. ; +); +relation CHANNEL , CHANNEL ( + regle 49 : distance axiale min 3.; +); + +undefine CHANNEL; + +# Check RDS_POLY is distant from ACTIV ZONE of TRANSISTOR +#-------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + regle 79 : distance axiale >= 1. ; +); + +relation RDS_POLY , CONT_DIFF ( + regle 50 : distance axiale >= 2. ; +); + +undefine CONT_DIFF; +undefine NP_DIF; + + +# Check RDS_ALU1 shapes +#---------------------- +caracterise RDS_ALU1 ( + regle 51 : largeur >= 2. ; # LSX 1 -> 2 + regle 52 : longueur_inter min 2. ; # LSX 1 -> 2 + regle 53 : notch >= 3. ; +); +relation RDS_ALU1 , RDS_ALU1 ( + regle 54 : distance axiale min 3. ; +); + +# Check RDS_ALU2 shapes +#---------------------- +caracterise RDS_ALU2 ( + regle 55 : largeur >= 2. ; + regle 56 : longueur_inter min 2. ; + regle 57 : notch >= 3. ; +); +relation RDS_ALU2 , RDS_ALU2 ( + regle 58 : distance axiale min 3. ; +); + +# Check RDS_ALU3 shapes +#---------------------- +caracterise RDS_ALU3 ( + regle 59 : largeur >= 2. ; + regle 60 : longueur_inter min 2. ; + regle 61 : notch >= 3. ; +); +relation RDS_ALU3 , RDS_ALU3 ( + regle 62 : distance axiale min 3. ; +); + +# Check RDS_ALU4 shapes +#---------------------- +caracterise RDS_ALU4 ( + regle 63 : largeur >= 2. ; + regle 64 : longueur_inter min 2. ; + regle 65 : notch >= 3. ; +); +relation RDS_ALU4 , RDS_ALU4 ( + regle 66 : distance axiale min 3. ; +); + +# Check RDS_ALU5 shapes +#---------------------- +caracterise RDS_ALU5 ( + regle 80 : largeur >= 2. ; + regle 81 : longueur_inter min 2. ; + regle 82 : notch >= 3. ; +); +relation RDS_ALU5 , RDS_ALU5 ( + regle 83 : distance axiale min 3. ; +); + +# Check RDS_ALU6 shapes +#---------------------- +caracterise RDS_ALU6 ( + regle 84 : largeur >= 2. ; + regle 85 : longueur_inter min 2. ; + regle 86 : notch >= 3. ; +); +relation RDS_ALU6 , RDS_ALU6 ( + regle 87 : distance axiale min 3. ; +); + +# Check ANY_VIA layers, stacking are free +#---------------------------------------- +relation RDS_CONT , RDS_CONT ( + regle 67 : distance axiale >= 3. ; +); +relation RDS_VIA , RDS_VIA ( + regle 68 : distance axiale >= 4. ; +); +relation RDS_VIA2 , RDS_VIA2 ( + regle 69 : distance axiale >= 4. ; +); +relation RDS_VIA3 , RDS_VIA3 ( + regle 70 : distance axiale >= 4. ; +); +relation RDS_VIA4 , RDS_VIA4 ( + regle 88 : distance axiale >= 4. ; +); +relation RDS_VIA5 , RDS_VIA5 ( + regle 89 : distance axiale >= 4. ; +); +caracterise RDS_CONT ( + regle 71 : largeur >= 1. ; + regle 72 : longueur <= 1. ; +); +caracterise RDS_VIA ( + regle 73 : largeur >= 1. ; + regle 74 : longueur <= 1. ; +); +caracterise RDS_VIA2 ( + regle 75 : largeur >= 1. ; + regle 76 : longueur <= 1. ; +); +caracterise RDS_VIA3 ( + regle 77 : largeur >= 1. ; + regle 78 : longueur <= 1. ; +); +caracterise RDS_VIA4 ( + regle 90 : largeur >= 1. ; + regle 91 : longueur <= 1. ; +); +caracterise RDS_VIA5 ( + regle 92 : largeur >= 1. ; + regle 93 : longueur <= 1. ; +); + +# Check the POLY2 shapes +#----------------------- +caracterise RDS_POLY2 ( + regle 94 : largeur >= 1. ; + regle 95 : longueur_inter min 1. ; + regle 96 : notch >= 5. ; +); +relation RDS_POLY2 , RDS_POLY2 ( + regle 97 : distance axiale min 5. ; +); + +# Check RDS_POLY2 is really included inside RDS_POLY1 +#---------------------------------------------------- +relation RDS_POLY , RDS_POLY2 ( + regle 98 : distance axiale < 0.; + regle 99 : enveloppe inferieure min 5. ; + regle 100 : marge longueur_inter < 0. ; + regle 101 : croix longueur_inter < 0. ; + regle 102 : intersection longueur_inter < 0. ; + regle 103 : extension longueur_inter < 0. ; + regle 104 : inclusion longueur_inter < 0. ; +); + + +fin regles +DRC_COMMENT +1 (RDS_NWELL) minimum width 4. +2 (RDS_NWELL) minimum width 4. +3 (RDS_NWELL) Manhatan distance min 12. +4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12. +5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5 +6 (RDS_PTIE,RDS_NWELL) must never been in contact +7 (RDS_PTIE,RDS_NWELL) must never been in contact +8 (RDS_PTIE,RDS_NWELL) must never been in contact +9 (RDS_PTIE,RDS_NWELL) must never been in contact +10 (RDS_PTIE,RDS_NWELL) must never been in contact +11 (RDS_PTIE,RDS_NWELL) must never been in contact +12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5 +13 (RDS_NDIF,RDS_NWELL) must never been in contact +14 (RDS_NDIF,RDS_NWELL) must never been in contact +15 (RDS_NDIF,RDS_NWELL) must never been in contact +16 (RDS_NDIF,RDS_NWELL) must never been in contact +17 (RDS_NDIF,RDS_NWELL) must never been in contact +18 (RDS_NDIF,RDS_NWELL) must never been in contact +19 (RDS_PDIF) minimum width 3. # LSX 2 -> 3 +20 (RDS_PDIF) minimum width 3. # LSX 2 -> 3 +21 (RDS_PDIF) Manhatan distance min 3. +22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3. +23 (RDS_NDIF) minimum width 3. # LSX 2 -> 3 +24 (RDS_NDIF) minimum width 3. # LSX 2 -> 3 +25 (RDS_NDIF) Manhatan distance min 3. +26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3. +27 (RDS_PTIE) minimum width 3. # LSX 2 -> 3 +28 (RDS_PTIE) minimum width 3. # LSX 2 -> 3 +29 (RDS_PTIE) Manhatan distance min 3. +30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3. +31 (RDS_NTIE) minimum width 3. # LSX 2 -> 3 +32 (RDS_NTIE) minimum width 3. # LSX 2 -> 3 +33 (RDS_NTIE) Manhatan distance min 3. +34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3. +35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3. +36 (ANY_N_DIF,ANY_P_DIF) must never been in contact +37 (ANY_N_DIF,ANY_P_DIF) must never been in contact +38 (ANY_N_DIF,ANY_P_DIF) must never been in contact +39 (ANY_N_DIF,ANY_P_DIF) must never been in contact +40 (ANY_N_DIF,ANY_P_DIF) must never been in contact +41 (ANY_N_DIF,ANY_P_DIF) must never been in contact +42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1. +43 (RDS_POLY,NP_DIF) bad intersection +44 (RDS_POLY) minimum width 1. +45 (RDS_POLY) minimum width 1. +46 (RDS_POLY) Manhatan distance min 2. +47 (RDS_POLY,RDS_POLY) Manhatan distance min 2. +48 (CHANNEL) Manhatan distance min 3. +49 (CHANNEL,CHANNEL) Manhatan distance min 3. +50 (RDS_POLY,CONT_DIFF) Manhatan distance min 2. +51 (RDS_ALU1) minimum width 2. # LSX 1 -> 2 +52 (RDS_ALU1) minimum width 2. # LSX 1 -> 2 +53 (RDS_ALU1) Manhatan distance min 3. +54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 3. +55 (RDS_ALU2) minimum width 2. +56 (RDS_ALU2) minimum width 2. +57 (RDS_ALU2) Manhatan distance min 3. +58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 3. +59 (RDS_ALU3) minimum width 2. +60 (RDS_ALU3) minimum width 2. +61 (RDS_ALU3) Manhatan distance min 3. +62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3. +63 (RDS_ALU4) minimum width 2. +64 (RDS_ALU4) minimum width 2. +65 (RDS_ALU4) Manhatan distance min 3. +66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3. +67 (RDS_CONT,RDS_CONT) Manhatan distance min 3. +68 (RDS_VIA,RDS_VIA) Manhatan distance min 4. +69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 4. +70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 4. +71 (RDS_CONT) minimum width 1. +72 (RDS_CONT) maximum length 1. +73 (RDS_VIA) minimum width 1. +74 (RDS_VIA) maximum length 1. +75 (RDS_VIA2) minimum width 1. +76 (RDS_VIA2) maximum length 1. +77 (RDS_VIA3) minimum width 1. +78 (RDS_VIA3) maximum length 1. +79 (RDS_POLY,RDS_ACTIV) Manhatan distance min 1. +80 (RDS_ALU5) minimum width 2. +81 (RDS_ALU5) minimum width 2. +82 (RDS_ALU5) Manhatan distance min 4. +83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 4. +84 (RDS_ALU6) minimum width 2. +85 (RDS_ALU6) minimum width 2. +86 (RDS_ALU6) Manhatan distance min 4. +87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 4. +88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 4. +89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 4. +90 (RDS_VIA4) minimum width 1. +91 (RDS_VIA4) maximum length 1. +92 (RDS_VIA5) minimum width 1. +93 (RDS_VIA5) maximum length 1. +94 (RDS_POLY2) minimum width 1. +95 (RDS_POLY2) minimum width 1. +96 (RDS_POLY2) Manhatan distance min 5. +97 (RDS_POLY2,POLY2) Manhatan distance min 5. +98 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +99 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +100 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +101 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +102 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +103 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +104 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/techno.py b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/techno.py new file mode 100644 index 000000000..534feec0f --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/techno.py @@ -0,0 +1,647 @@ + +from coriolis import CRL, Hurricane, Viewer, Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, BasicLayer, \ + RegularLayer, Cell, Net, Horizontal, Vertical, Rectilinear, \ + Box, Point, NetExternalComponents +from coriolis.technos.common.colors import toRGB +from coriolis.technos.common.patterns import toHexa +from coriolis.helpers import u +from coriolis.helpers.technology import createBL, createVia +from coriolis.helpers.overlay import CfgCache +from coriolis.helpers.analogtechno import Length, Area, Unit, Asymmetric, loadAnalogTechno, addDevice +from coriolis.designflow.task import ShellEnv + + +__all__ = [ "setup" ] + + +""" +Coriolis Design Technological Rules (DTR) for IHP 130nm BiCMOS General Purpose +================================================================================= + +:Version: rev.LIP6-1 +:Date: May 22, 2024 +:Authors: Naohiko Shimizu + +Reference documents: + SG13G2 Process Specification Rev.1.2 + SG13G2 Open Source Layout Rules Rev.0.2 (2024-03-08) + +===================== ======= ============ ==================================== + +""" + + +analogTechnologyTable = \ + ( ('Header', 'Sg13g2', DbU.UnitPowerMicro, 'rev.LIP6-1') + # ------------------------------------------------------------------------------------ + # ( Rule name , [Layer1] , [Layer2] , Value , Rule flags , Reference ) + , ('physicalGrid' , 0.001 , Length , 'Grid Rules') + , ('transistorMinL' , 0.13 , Length , 'Gat.a') + #, ('transistorMinL' , 0.38 , Length , 'lvtn.1a') + #, ('transistorMaxL' , 38 , Length , 'rule0002') + #, ('transistorMinW' , 0.42 , Length , 'activ.2') + #, ('transistorMinW' , 0.36 , Length , 'activ.2b') + #, ('transistorMaxW' , 4000 , Length , 'rule0004') + + # N-WELL (nwm) + , ('minWidth' , 'nwm' , 0.62 , Length , 'NW.a') + , ('minSpacing' , 'nwm' , 0.62 , Length , 'NW.b') + , ('minArea' , 'nwm' , 0 , Area , 'N/A') + + # LVTN (lvtn) + #, ('minWidth' , 'lvtn' , 0.38 , Length , 'lvtn.1a') + #, ('minSpacing' , 'lvtn' , 0.38 , Length , 'lvtn.2') + #, ('minArea' , 'lvtn' , 0.265 , Area , 'lvtn.13') + #, ('minEnclosure' , 'nwm' , 'lvtn' , 0.38 , Length|Asymmetric, 'lvtn.10') + + # ACTIV (activ) + , ('minWidth' , 'activ' , 0.15 , Length , 'Act.a') + , ('minSpacing' , 'activ' , 0.21 , Length , 'Act.b') + , ('minArea' , 'activ' , 0.122 , Area , 'Act.d') + , ('minEnclosure' , 'nwm' , 'activ' , 0.31 , Length|Asymmetric, 'NW.c') + + # Poly1 (poly) + , ('minWidth' , 'poly' , 0.13 , Length , 'Gat.a') + , ('minSpacing' , 'poly' , 0.18 , Length , 'Gat.b') + , ('minGateSpacing' , 'poly' , 0.18 , Length , 'Gat.b') + , ('minArea' , 'poly' , 0.09 , Area , 'Gat.e') + , ('minSpacing' , 'poly' , 'activ' , 0.07 , Length , 'Gat.d') + , ('minExtension' , 'poly' , 'activ' , 0.180 , Length|Asymmetric, 'Gat.c') + , ('minGateExtension' , 'activ' , 'poly' , 0.23 , Length|Asymmetric, 'Act.c') + , ('minExtension' , 'activ' , 'poly' , 0.23 , Length|Asymmetric, 'Act.c') + + # 4.1.6 PPLUS (psdm) + , ('minWidth' , 'psdm' , 0.31 , Length , 'pSD.a') + , ('minSpacing' , 'psdm' , 0.31 , Length , 'pSD.b') + , ('minArea' , 'psdm' , 0.25 , Area , 'pSD.k') + , ('minSpacing' , 'psdm' , 'activ' , 0.180 , Length , 'pSD.d') + , ('minGateExtension' , 'psdm' , 'poly' , 0.00 , Length|Asymmetric, 'N/A') + , ('minOverlap' , 'psdm' , 'activ' , 0.30 , Length , 'pSD.e') + , ('minEnclosure' , 'psdm' , 'activ' , 0.180 , Length|Asymmetric, 'pSD.c') + , ('minStrapEnclosure' , 'psdm' , 'activ' , 0.180 , Length , 'pSD.c') + , ('minSpacing' , 'nsdm' , 'psdm' , 0.00 , Length , 'N/A') + , ('minEnclosure' , 'psdm' , 'poly' , 0.30 , Length|Asymmetric, 'pSD.i') + , ('minLengthEnclosure', 'psdm' , 'activ' , 0 , Length|Asymmetric, 'N/A') + , ('minWidthEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'psdm' , 'activ' , 0.180 , Length|Asymmetric, 'dup. pSD.c') + , ('minStrapEnclosure' , 'psdm' , 0.180 , Length , 'dup. pSD.c') + + # NPLUS (nsdm) no nSD rules + #, ('minWidth' , 'nsdm' , 0.38 , Length , 'nsd.1') + #, ('minSpacing' , 'nsdm' , 0.38 , Length , 'nsd.2') + #, ('minArea' , 'nsdm' , 0.265 , Area , 'nsd.10a') + #, ('minSpacing' , 'nsdm' , 'activ' , 0.130 , Length , 'nsd.7') + #, ('minGateExtension' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minOverlap' , 'nsdm' , 'activ' , 0 , Length , 'N/A') + #, ('minEnclosure' , 'nsdm' , 'activ' , 0.125 , Length|Asymmetric, 'nsd.5a') + #, ('minStrapEnclosure' , 'nsdm' , 'activ' , 0.125 , Length , 'nsd.5b') + #, ('minEnclosure' , 'nsdm' , 'nwm' , 0 , Length|Asymmetric, 'N/A') + #, ('minEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minLengthEnclosure', 'nsdm' , 'activ' , 0 , Length|Asymmetric, 'N/A') + #, ('minWidthEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minGateEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + #, ('minExtension' , 'nsdm' , 'activ' , 0.125 , Length|Asymmetric, 'dup. nsd.5a') + #, ('minStrapEnclosure' , 'nsdm' , 0.215 , Length , 'dup. nsd.5b') + + # LICM1 (CONT) + , ('minWidth' , 'cont' , 0.16 , Length , 'Cnt.a') + , ('minSpacing' , 'cont' , 0.18 , Length , 'Cnt.b') + , ('minGateSpacing' , 'cont' , 'poly' , 0.11 , Length|Asymmetric, 'Cnt.f') + , ('minSpacing' , 'cont' , 'poly' , 0.11 , Length|Asymmetric, 'Cnt.f') + , ('minSpacing' , 'cont' , 'activ' , 0.14 , Length , 'Cnt.e') + #, ('minSpacing' , 'cont' , 'activ' , 0.06 , Length , 'cont.5b') + , ('minEnclosure' , 'activ' , 'cont' , 0.07 , Length|Asymmetric, 'Cnt.c') + , ('minEnclosure' , 'poly' , 'cont' , 0.07 , Length|Asymmetric, 'Cnt.d') + #, ('minEnclosure' , 'psdm' , 'cont' , 0 , Length|Asymmetric, 'N/A') + #, ('minEnclosure' , 'nsdm' , 'cont' , 0 , Length|Asymmetric, 'N/A') + #, ('minGateEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'poly' , 'cont' , 0.07 , Length|Asymmetric, 'dup. Cnt.d') + , ('minExtension' , 'psdm' , 'cont' , 0.09 , Length|Asymmetric, 'Cnt.g2') + #, ('minExtension' , 'nsdm' , 'cont' , 0.25 , Length|Asymmetric, 'dup.') + + # LI1M (M1) + , ('minWidth' , 'M1' , 0.16 , Length , 'M1.a') + , ('minSpacing' , 'M1' , 0.18 , Length , 'M1.b') + , ('minArea' , 'M1' , 0.09 , Area , 'M1.d') + , ('minEnclosure' , 'M1' , 'cont' , 0.05 , Length|Asymmetric, 'M1.c1') + , ('minEnclosure' , 'M1' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # CTM1 (via12) + , ('minWidth' , 'via12' , 0.19 , Length , 'V1.a') + , ('minSpacing' , 'via12' , 0.22 , Length , 'V1.b') + + + # MM1 (M2) + , ('minWidth' , 'M2' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M2' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M2' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M2' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M2' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via23) + , ('minWidth' , 'via23' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via23' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M2' , 'via23' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M2' , 'via23' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + + # MM1 (M3) + , ('minWidth' , 'M3' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M3' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M3' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M3' , 'via23' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M3' , 'via23' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via34) + , ('minWidth' , 'via34' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via34' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M3' , 'via34' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M3' , 'via34' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + # MM1 (M4) + , ('minWidth' , 'M4' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M4' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M4' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M4' , 'via34' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M4' , 'via34' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via45) + , ('minWidth' , 'via45' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via45' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M4' , 'via45' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M4' , 'via45' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + # MM5 (M5) + , ('minWidth' , 'M5' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M5' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M5' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M5' , 'via45' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M5' , 'via45' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via56 TopVia1) + , ('minWidth' , 'via56' , 0.42 , Length , 'TV1.a') + , ('minSpacing' , 'via56' , 0.42 , Length , 'TV1.b') + , ('minEnclosure' , 'M5' , 'via56' , 0.1 , Length|Asymmetric, 'TV1.c') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M5' , 'via56' , 0.1 , Length|Asymmetric, 'dup. TV1.c') + + # MM6 (M6) TopMetal1 + , ('minWidth' , 'M6' , 1.64 , Length , 'TM1.a') + , ('minSpacing' , 'M6' , 1.64 , Length , 'TM1.b') + #, ('minArea' , 'M6' , 0.24 , Area , 'M5.4a') + , ('minEnclosure' , 'M6' , 'via56' , 0.10 , Length|Asymmetric, 'TV1.c') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M6' , 'via56' , 0.10 , Length|Asymmetric, 'dup. TV1.c ') + + # VIM (via56 TopVia2) + , ('minWidth' , 'via56' , 0.90 , Length , 'TV2.a') + , ('minSpacing' , 'via56' , 1.06 , Length , 'TV2.b') + , ('minEnclosure' , 'M6' , 'via56' , 0.5 , Length|Asymmetric, 'TV2.c') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M6' , 'via56' , 0.5 , Length|Asymmetric, 'dup. TV2.c') + + # MM5 (M7) TopMetal2 + , ('minWidth' , 'M7' , 2.00 , Length , 'TM2.a') + , ('minSpacing' , 'M7' , 2.00 , Length , 'TM2.b') + #, ('minArea' , 'M7' , 0.24 , Area , 'M5.4a') + , ('minEnclosure' , 'M7' , 'via56' , 0.50 , Length|Asymmetric, 'TV1.d') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M7' , 'via56' , 0.50 , Length|Asymmetric, 'dup. TV1.d ') + + + + #capm + #, ('minWidth' , 'metcap' , 1.0 , Length , 'capm.1') + #, ('minWidth' , 'metcapdum' , 0.5 , Length , '') + #, ('maxWidth' , 'metcap' , 300.0 , Length , '') + #, ('maxWidth' , 'metbot' , 350.0 , Length , '') + #, ('minSpacing' , 'metcap' , 0.84 , Length , 'capm.2a') + #, ('minSpacing' , 'metbot' , 0.8 , Length , 'metcap.2b') + #, ('minSpacing' , 'cut1' , 'metcap' , 0.50 , Length , '') + #, ('minSpacing' , 'cut2' , 'metcap' , 0.50 , Length , 'capm.5') + #, ('minSpacingOnMetbot', 'cut2' , 0.2 , Length , 'via34.2') + #, ('minSpacingOnMetbot', 'via34' , 0.2 , Length , 'via34.2') + #, ('minSpacingOnMetcap', 'cut2' , 0.2 , Length , 'via34.2') + #, ('minEnclosure' , 'M3' , 'metcap' , 0.14 , Length|Asymmetric, 'capm.3') + #, ('minEnclosure' , 'metbot' , 'cut1' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'metbot' , 'cut2' , 0.04 , Length|Asymmetric, 'via34.14') + #, ('minEnclosure' , 'metcap' , 'cut2' , 0.14 , Length|Asymmetric, 'capm.4') + #, ('minArea' , 'metcap' , 0 , Area , 'na') + #, ('minAreaInMetcap' , 'cut2' , 0 , Area , 'na') + #, ('MIMCap' , 1.25 , Unit , 'na') + #, ('MIMPerimeterCap' , 0.17 , Unit , 'na') + + + #capm + , ('minWidth' , 'capm' , 1.14 , Length , 'MIM.a') + #, ('minWidth' , 'capmdum' , 0.5 , Length , '') + #, ('maxWidth' , 'capm' , 30.0 , Length , '') + #, ('maxWidth' , 'metbot' , 35.0 , Length , '') + , ('minSpacing' , 'capm' , 0.60 , Length , 'MIM.b') + #, ('minSpacing' , 'M4' , 0.8 , Length , 'capm.2b') + , ('minSpacingWide1' , 'M3' , 0.8 , Length , 'capm.2b') + , ('minSpacing' , 'M6' , 'capm' , 0.60 , Length , 'MIM.e') + , ('minSpacing' , 'via34' , 'capm' , 0.50 , Length , 'capm.5') + , ('minSpacingOnMetBot', 'via34' , 0.2 , Length , 'via34.2') + , ('minSpacingOnMetCap', 'via34' , 0.2 , Length , 'via34.2') + , ('minSpacingOnMetBot', 'via23' , 0.2 , Length , 'via34.2 fake') + , ('minSpacingOnMetCap', 'via23' , 0.2 , Length , 'via34.2 fake') + , ('minEnclosure' , 'M5' , 'capm' , 0.60 , Length|Asymmetric, 'MIM.c') + #, ('minEnclosure' , 'M4' , 'via23' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'M4' , 'via34' , 0.04 , Length|Asymmetric, 'via34.14') + #, ('minEnclosure' , 'capm' , 'via23' , 0.14 , Length|Asymmetric, 'capm.4 fake') + , ('minEnclosure' , 'capm' , 'via56' , 0.36 , Length|Asymmetric, 'MIM.d') + , ('minArea' , 'capm' , 1.30 , Area , 'MIM.f') + , ('minAreaInMetcap' , 'via34' , 0 , Area , 'na') + , ('MIMCap' , 1.25 , Unit , 'na') + , ('MIMPerimeterCap' , 0.17 , Unit , 'na') + , ('PIPCap' , 1.25 , Unit , 'na') + , ('PIPPerimeterCap' , 0.17 , Unit , 'na') + + ) + + +def _loadDtr (): + """ + Load design kit physical rules for IHP 130nm. + """ + loadAnalogTechno( analogTechnologyTable, __file__ ) + + +def _loadDevices (): + addDevice( name = 'DifferentialPairBulkConnected' + #, spice = spiceDir+'DiffPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'DifferentialPairBulkUnconnected' + #, spice = spiceDir+'DiffPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'LevelShifterBulkUnconnected' + #, spice = spiceDir+'LevelShifterBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S1', 'S2', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.LS_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.LS_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.LS_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.LS_interdigitated.py' ) + ) + ) + addDevice( name = 'TransistorBulkConnected' + #, spice = spiceDir+'TransistorBulkConnected.spi' + , connectors = ( 'D', 'G', 'S' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'TransistorBulkUnconnected' + #, spice = spiceDir+'TransistorBulkUnconnected.spi' + , connectors = ( 'D', 'G', 'S', 'B' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkConnected' + #, spice = spiceDir+'CCPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkUnconnected' + #, spice = spiceDir+'CCPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkConnected' + #, spice = spiceDir+'CommonSourcePairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkUnconnected' + #, spice = spiceDir+'CommonSourcePairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkConnected' + #, spice = spiceDir+'CurrMirBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkUnconnected' + #, spice = spiceDir+'CurrMirBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'MultiCapacitor' + #, spice = spiceDir+'MIM_OneCapacitor.spi' + , connectors = ( 'T1', 'B1' ) + , layouts = ( ('Matrix', 'coriolis.oroshi.multicapacitor.py' ), + ) + ) + #addDevice( name = 'Resistor' + # #, spice = spiceDir+'MIM_OneCapacitor.spi' + # , connectors = ( 'PIN1', 'PIN2' ) + # , layouts = ( ('Snake', 'coriolis.oroshi.resistorsnake.py' ), + # ) + # ) + + +def _setup_techno ( coriolisTechDir ): + ShellEnv.RDS_TECHNO_NAME = (coriolisTechDir / 'sg13g2_lsx' / 'sg13g2.rds').as_posix() + ShellEnv.GRAAL_TECHNO_NAME = (coriolisTechDir / 'sg13g2_lsx' / 'symbolic.graal' ).as_posix() + ShellEnv.DREAL_TECHNO_NAME = (coriolisTechDir / 'sg13g2_lsx' / 'symbolic.dreal' ).as_posix() + + db = DataBase.getDB() + CRL.System.get() + + tech = Technology.create(db, 'sg13g2_lsx') + + DbU.setPrecision( 2 ) + DbU.setPhysicalsPerGrid( 0.001, DbU.UnitPowerMicro ) + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + cfg.gdsDriver.metricDbu = 1e-09 + cfg.gdsDriver.dbuPerUu = 0.001 + DbU.setGridsPerLambda ( 30 ) + DbU.setSymbolicSnapGridStep( DbU.fromGrid( 1.0 )) + DbU.setPolygonStep ( DbU.fromGrid( 1.0 )) + DbU.setStringMode ( DbU.StringModePhysical, DbU.UnitPowerMicro ) + + createBL( tech, 'nwm' , BasicLayer.Material.nWell , size=u(0.62), spacing=u(0.62), gds2Layer= 31, gds2DataType= 0 ) + createBL( tech, 'nsdm' , BasicLayer.Material.nImplant, size=u(0.31), spacing=u(0.31), area=0.25, gds2Layer= 7, gds2DataType= 0 ) + createBL( tech, 'psdm' , BasicLayer.Material.pImplant, size=u(0.31), spacing=u(0.31), area=0.25, gds2Layer= 14, gds2DataType= 0 ) + #createBL( tech, 'hvi' , BasicLayer.Material.other , gds2Layer= 75, gds2DataType= 20 ) + createBL( tech, 'activ.pin' , BasicLayer.Material.other , gds2Layer= 1, gds2DataType= 2 ) + #createBL( tech, 'activ.block', BasicLayer.Material.blockage, gds2Layer=1, gds2DataType= 23 ) + createBL( tech, 'poly.pin' , BasicLayer.Material.other , gds2Layer= 5, gds2DataType= 2 ) + #createBL( tech, 'poly.block' , BasicLayer.Material.blockage, gds2Layer=5, gds2DataType= 23 ) + createBL( tech, 'M1.pin' , BasicLayer.Material.other , gds2Layer= 8, gds2DataType= 2 ) + #createBL( tech, 'M1.block' , BasicLayer.Material.blockage, gds2Layer=8, gds2DataType= 23 ) + createBL( tech, 'M2.pin' , BasicLayer.Material.other , gds2Layer= 10, gds2DataType= 2 ) + #createBL( tech, 'M2.block' , BasicLayer.Material.blockage, gds2Layer=10, gds2DataType= 23 ) + createBL( tech, 'M3.pin' , BasicLayer.Material.other , gds2Layer= 30, gds2DataType= 2 ) + #createBL( tech, 'M3.block' , BasicLayer.Material.blockage, gds2Layer=30, gds2DataType= 23 ) + createBL( tech, 'M4.pin' , BasicLayer.Material.other , gds2Layer= 50, gds2DataType= 2 ) + #createBL( tech, 'M4.block' , BasicLayer.Material.blockage, gds2Layer=50, gds2DataType=23 ) + createBL( tech, 'M5.pin' , BasicLayer.Material.other , gds2Layer= 67, gds2DataType= 2 ) + #createBL( tech, 'M5.block' , BasicLayer.Material.blockage, gds2Layer=67, gds2DataType=23 ) + createBL( tech, 'M6.pin' , BasicLayer.Material.other , gds2Layer= 126, gds2DataType= 2 ) + #createBL( tech, 'M6.block' , BasicLayer.Material.blockage, gds2Layer=126, gds2DataType=23 ) + #createBL( tech, 'cont.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 30 ) + #createBL( tech, 'via12.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 50 ) + #createBL( tech, 'via23.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 70 ) + #createBL( tech, 'via34.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 90 ) + #createBL( tech, 'via45.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=110 ) + #createBL( tech, 'via56.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=130 ) + createBL( tech, 'activ' , BasicLayer.Material.active , size=u(0.15), spacing=u(0.21), gds2Layer= 1, gds2DataType= 0 ) + createBL( tech, 'poly' , BasicLayer.Material.poly , size=u(0.13), spacing=u(0.18), gds2Layer= 5, gds2DataType= 0 ) + createBL( tech, 'cont' , BasicLayer.Material.cut , size=u(0.16), spacing=u(0.18), gds2Layer= 6, gds2DataType= 0 ) + createBL( tech, 'M1' , BasicLayer.Material.metal , size=u(0.16), spacing=u(0.18), area=0.009, gds2Layer= 8, gds2DataType= 0 ) + createBL( tech, 'via12' , BasicLayer.Material.cut , size=u(0.19), spacing=u(0.22), gds2Layer= 19, gds2DataType= 0 ) + createBL( tech, 'M2' , BasicLayer.Material.metal , size=u(0.20), spacing=u(0.21), area=0.144, gds2Layer= 10, gds2DataType= 0 ) + createBL( tech, 'via23' , BasicLayer.Material.cut , size=u(0.19), spacing=u(0.22), gds2Layer= 29, gds2DataType= 0 ) + createBL( tech, 'M3' , BasicLayer.Material.metal , size=u(0.19), spacing=u(0.21), area=0.144, gds2Layer= 30, gds2DataType= 0 ) + createBL( tech, 'capm' , BasicLayer.Material.metal ) + createBL( tech, 'via34' , BasicLayer.Material.cut , size=u(0.19 ), spacing=u(0.22), gds2Layer= 49, gds2DataType= 0 ) + createBL( tech, 'M4' , BasicLayer.Material.metal , size=u(0.19 ), spacing=u(0.21 ), area=0.144, gds2Layer= 50, gds2DataType= 0 ) + createBL( tech, 'via45' , BasicLayer.Material.cut , size=u(0.19 ), spacing=u(0.22), gds2Layer= 49, gds2DataType= 0 ) + createBL( tech, 'M5' , BasicLayer.Material.metal , size=u(0.19 ), spacing=u(0.21 ), area=0.144, gds2Layer=67, gds2DataType= 0 ) + createBL( tech, 'via56' , BasicLayer.Material.cut , size=u(0.42 ), spacing=u(0.42 ), gds2Layer= 125, gds2DataType= 0 ) + createBL( tech, 'M6' , BasicLayer.Material.metal , size=u(1.64), spacing=u(1.64), gds2Layer= 126, gds2DataType= 0 ) + createBL( tech, 'hvtp' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 78, gds2DataType= 44 ) + createBL( tech, 'lvtn' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer=125, gds2DataType= 44 ) + createBL( tech, 'areaid_sc' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 4 ) + createBL( tech, 'pad' , BasicLayer.Material.cut , size=u(40.0), spacing=u(1.27), gds2Layer= 76, gds2DataType= 20 ) + createBL( tech, 'areaid_diode' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 23 ) + createBL( tech, 'pnp' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 44 ) + createBL( tech, 'diffres' , BasicLayer.Material.other , gds2Layer= 65, gds2DataType= 13 ) + createBL( tech, 'npn' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 20 ) + createBL( tech, 'polyres' , BasicLayer.Material.other , gds2Layer= 66, gds2DataType= 13 ) + createBL( tech, 'prBoundary' , BasicLayer.Material.other , gds2Layer=235, gds2DataType= 4 ) + + tech.addLayerAlias( 'M2', 'met1' ) + tech.addLayerAlias( 'M3', 'met2' ) + tech.addLayerAlias( 'M4', 'met3' ) + tech.addLayerAlias( 'M5', 'met4' ) + tech.addLayerAlias( 'M6', 'met5' ) + + # ViaLayers + createVia( tech, 'li_via12_M2' , 'M1' , 'via12', 'M2', u(0.17) ) + createVia( tech, 'M2_via_M3' , 'M2' , 'via23' , 'M3', u(0.15) ) + createVia( tech, 'M3_via34_M4' , 'M3' , 'via34', 'M4', u(0.2 ) ) + createVia( tech, 'M4_via45_M5' , 'M4' , 'via45', 'M5', u(0.2 ) ) + createVia( tech, 'M5_via56_M6' , 'M5' , 'via56', 'M6', u(0.8 ) ) + createVia( tech, 'capm_via56', 'capm', 'via56', 'M6', u(0.2 ) ) + + # Blockages + #ech.getLayer('activ' ).setBlockageLayer( tech.getLayer('activ.block') ) + #ech.getLayer('poly') .setBlockageLayer( tech.getLayer('poly.block') ) + #ech.getLayer('M1') .setBlockageLayer( tech.getLayer('M1.block') ) + #ech.getLayer('M2') .setBlockageLayer( tech.getLayer('M2.block') ) + #ech.getLayer('M3') .setBlockageLayer( tech.getLayer('M3.block') ) + #ech.getLayer('M4') .setBlockageLayer( tech.getLayer('M4.block') ) + #ech.getLayer('M5') .setBlockageLayer( tech.getLayer('M5.block') ) + #ech.getLayer('M6') .setBlockageLayer( tech.getLayer('M6.block') ) + #ech.getLayer('cont' ) .setBlockageLayer( tech.getLayer('cont.block') ) + #ech.getLayer('via12') .setBlockageLayer( tech.getLayer('via12.block') ) + #ech.getLayer('via23') .setBlockageLayer( tech.getLayer('via23.block') ) + #ech.getLayer('via34') .setBlockageLayer( tech.getLayer('via34.block') ) + #ech.getLayer('via45') .setBlockageLayer( tech.getLayer('via45.block') ) + #ech.getLayer('via56') .setBlockageLayer( tech.getLayer('via56.block') ) + + # Coriolis internal layers + createBL( tech, 'text.cell' , BasicLayer.Material.other, ) + createBL( tech, 'text.instance', BasicLayer.Material.other, ) + createBL( tech, 'SPL1' , BasicLayer.Material.other, ) + createBL( tech, 'AutoLayer' , BasicLayer.Material.other, ) + createBL( tech, 'gmetalh' , BasicLayer.Material.metal, ) + createBL( tech, 'gcontact' , BasicLayer.Material.cut, ) + createBL( tech, 'gmetalv' , BasicLayer.Material.metal, ) + + # Resistors + # ResistorLayer.create(tech, 'poly_res', 'poly', 'polyres') + # ResistorLayer.create(tech, 'active_res', 'activ' , 'diffres') + + # Transistors + # GateLayer.create(tech, 'hvmosgate' , 'activ' , 'poly', 'hvi') + # GateLayer.create(tech, 'mosgate' , 'activ' , 'poly') + # GateLayer.create(tech, 'mosgate_sc', 'activ' , 'poly') + # TransistorLayer.create(tech, 'nfet_01v8' , 'mosgate' , 'nsdm') + # TransistorLayer.create(tech, 'nfet_01v8_lvt' , 'mosgate' , ('nsdm', 'lvtn')) + # TransistorLayer.create(tech, 'nfet_01v8_sc' , 'mosgate_sc', 'nsdm') + # TransistorLayer.create(tech, 'nfet_g5v0d10v5', 'hvmosgate' , 'nsdm') + # TransistorLayer.create(tech, 'pfet_01v8' , 'mosgate' , 'psdm', 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_hvt' , 'mosgate' , ('psdm', 'hvtp'), 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_lvt' , 'mosgate' , ('psdm', 'lvtn'), 'nwm') + # TransistorLayer.create(tech, 'pfet_g5v0d10v5', 'hvmosgate' , 'psdm', 'nwm') + + # Bipolars + # Not implemented: Bipolar 'pnp_05v5_w0u68l0u68' + # Not implemented: Bipolar 'npn_05v5_w1u00l2u00' + # Not implemented: Bipolar 'pnp_05v5_w3u40l3u40' + # Not implemented: Bipolar 'npn_05v5_w1u00l1u00' + + +def _setup_display (): + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [black] + + threshold = 0.2 if Viewer.Graphics.isHighDpi() else 0.1 + + style = Viewer.DisplayStyle( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - black background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + # Viewer. + style.addDrawingStyle( group='Viewer', name='fallback' , color=toRGB('Gray238' ), border=1, pattern='55AA55AA55AA55AA' ) + style.addDrawingStyle( group='Viewer', name='background' , color=toRGB('Gray50' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='rubber' , color=toRGB('192,0,192' ), border=4, threshold=0.02 ) + style.addDrawingStyle( group='Viewer', name='phantom' , color=toRGB('Seashell4' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries' , color=toRGB('wheat1' ), border=2, pattern='0000000000000000', threshold=0 ) + style.addDrawingStyle( group='Viewer', name='marker' , color=toRGB('80,250,80' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionDraw' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionFill' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='grid' , color=toRGB('White' ), border=1, threshold=2.0 ) + style.addDrawingStyle( group='Viewer', name='spot' , color=toRGB('White' ), border=2, threshold=6.0 ) + style.addDrawingStyle( group='Viewer', name='ghost' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='text.ruler' , color=toRGB('White' ), border=1, threshold= 0.0 ) + style.addDrawingStyle( group='Viewer', name='text.instance' , color=toRGB('White' ), border=1, threshold=400.0 ) + style.addDrawingStyle( group='Viewer', name='text.reference', color=toRGB('White' ), border=1, threshold=200.0 ) + style.addDrawingStyle( group='Viewer', name='undef' , color=toRGB('Violet' ), border=0, pattern='2244118822441188' ) + + # Active Layers. + style.addDrawingStyle(group='Active Layers', name='nwm' , color=toRGB('Tan' ), pattern=toHexa('urgo.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='nsdm' , color=toRGB('LawnGreen'), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='psdm' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='hvtp' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='lvtn' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='activ' , color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='activ.pin', color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly.pin' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + + # Routing Layers. + style.addDrawingStyle(group='Routing Layers', name='M1' , color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M1.pin', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M2' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M2.pin', color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M3' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M3.pin', color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M4' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M4.pin', color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M5' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M5.pin', color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M6' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M6.pin', color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + + # Cuts (VIA holes). + style.addDrawingStyle(group='Cuts (VIA holes', name='cont' , color=toRGB('0,150,150'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via12' , color=toRGB('Aqua' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via23' , color=toRGB('LightPink'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via34' , color=toRGB('Green' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via45' , color=toRGB('Yellow' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via56' , color=toRGB('Violet' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='pad' , color=toRGB('Red' ), threshold=threshold) + + # Blockages. + #style.addDrawingStyle(group='Blockages', name='activ.block', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='poly.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M1.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M2.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M3.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M4.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M5.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M6.block' , color=toRGB('Blue' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='cont.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via12.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via23.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via34.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via45.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via56.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) +# + # Knick & Kite. + style.addDrawingStyle( group='Knik & Kite', name='SPL1' , color=toRGB('Red' ) ) + style.addDrawingStyle( group='Knik & Kite', name='AutoLayer' , color=toRGB('Magenta' ) ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalh' , color=toRGB('128,255,200'), pattern=toHexa('antislash2.32' ), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalv' , color=toRGB('200,200,255'), pattern=toHexa('light_antihash1.8'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gcontact' , color=toRGB('255,255,190'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::Edge' , color=toRGB('255,255,190'), pattern='0000000000000000' , border=4, threshold=0.02 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::GCell', color=toRGB('255,255,190'), pattern='0000000000000000' , border=2, threshold=threshold ) + + Viewer.Graphics.addStyle( style ) + + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [white]. + + style = Viewer.DisplayStyle( 'Alliance.Classic [white]' ) + style.inheritFrom( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - white background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + style.addDrawingStyle( group='Viewer', name='background', color=toRGB('White'), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground', color=toRGB('Black'), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries', color=toRGB('Black'), border=1, pattern='0000000000000000' ) + Viewer.Graphics.addStyle( style ) + + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + +def setup ( coriolisTechDir ): + _setup_techno( coriolisTechDir ) + _setup_display() + try: + from .techno_symb import setup as setupSymbolic + except: + pass + else: + setupSymbolic() + _loadDtr() + _loadDevices() + diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/techno_symb.py b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/techno_symb.py new file mode 100644 index 000000000..1b2601d47 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/coriolis/sg13g2_lsx/techno_symb.py @@ -0,0 +1,284 @@ + +from coriolis.helpers import l, u, n +from coriolis.Hurricane import DataBase, Technology, Layer, BasicLayer, DiffusionLayer, \ + TransistorLayer, RegularLayer, ContactLayer, ViaLayer + +__all__ = [ 'setup' ] + + +def setup (): + tech = DataBase.getDB().getTechnology() + tech.addLayerAlias( 'nwm' , 'nWell' ) + tech.addLayerAlias( 'difftap' , 'active' ) + #tech.addLayerAlias( 'poly' , 'poly' ) + tech.addLayerAlias( 'psdm' , 'pImplant' ) + tech.addLayerAlias( 'nsdm' , 'nImplant' ) + tech.addLayerAlias( 'licon' , 'cut0' ) + tech.addLayerAlias( 'li' , 'metal1' ) + tech.addLayerAlias( 'mcon' , 'cut1' ) + tech.addLayerAlias( 'm1' , 'metal2' ) + tech.addLayerAlias( 'via' , 'cut2' ) + tech.addLayerAlias( 'm2' , 'metal3' ) + tech.addLayerAlias( 'via2' , 'cut3' ) + tech.addLayerAlias( 'm3' , 'metal4' ) + tech.addLayerAlias( 'via3' , 'cut4' ) + tech.addLayerAlias( 'm4' , 'metla5' ) + tech.addLayerAlias( 'via4' , 'cut5' ) + tech.addLayerAlias( 'm5' , 'metal6' ) + tech.addLayerAlias( 'li.block', 'blockage1' ) + tech.addLayerAlias( 'm1.block', 'blockage2' ) + tech.addLayerAlias( 'm2.block', 'blockage3' ) + tech.addLayerAlias( 'm3.block', 'blockage4' ) + tech.addLayerAlias( 'm4.block', 'blockage5' ) + tech.addLayerAlias( 'm5.block', 'blockage6' ) + tech.addLayerAlias( 'capm' , 'metcap' ) + tech.addLayerAlias( 'capm' , 'metcapdum' ) + tech.addLayerAlias( 'm3' , 'metbot' ) + + nWell = tech.getBasicLayer( 'nwm' ) + active = tech.getBasicLayer( 'difftap' ) + poly = tech.getBasicLayer( 'poly' ) + pImplant = tech.getBasicLayer( 'psdm' ) + nImplant = tech.getBasicLayer( 'nsdm' ) + cut0 = tech.getBasicLayer( 'licon' ) + metal1 = tech.getBasicLayer( 'li' ) + cut1 = tech.getBasicLayer( 'mcon' ) + metal2 = tech.getBasicLayer( 'm1' ) + cut2 = tech.getBasicLayer( 'via' ) + metal3 = tech.getBasicLayer( 'm2' ) + cut3 = tech.getBasicLayer( 'via2' ) + metal4 = tech.getBasicLayer( 'm3' ) + cut4 = tech.getBasicLayer( 'via3' ) + metal5 = tech.getBasicLayer( 'm4' ) + cut5 = tech.getBasicLayer( 'via4' ) + metal6 = tech.getBasicLayer( 'm5' ) + blockage1 = tech.getBasicLayer( 'blockage1' ) + blockage2 = tech.getBasicLayer( 'blockage1' ) + blockage3 = tech.getBasicLayer( 'blockage2' ) + blockage4 = tech.getBasicLayer( 'blockage3' ) + blockage5 = tech.getBasicLayer( 'blockage4' ) + blockage6 = tech.getBasicLayer( 'blockage5' ) + + # Composite/Symbolic layers. + NWELL = RegularLayer .create( tech, 'NWELL' , nWell ) + #PWELL = RegularLayer .create( tech, 'PWELL' , pWell ) + NTIE = DiffusionLayer .create( tech, 'NTIE' , nImplant , active, nWell) + PTIE = DiffusionLayer .create( tech, 'PTIE' , pImplant , active, None) + NDIF = DiffusionLayer .create( tech, 'NDIF' , nImplant , active, None ) + PDIF = DiffusionLayer .create( tech, 'PDIF' , pImplant , active, None ) + GATE = DiffusionLayer .create( tech, 'GATE' , poly , active, None ) + NTRANS = TransistorLayer.create( tech, 'NTRANS' , nImplant , active, poly, None ) + PTRANS = TransistorLayer.create( tech, 'PTRANS' , pImplant , active, poly, nWell ) + POLY = RegularLayer .create( tech, 'POLY' , poly ) + METAL1 = RegularLayer .create( tech, 'METAL1' , metal1 ) + METAL2 = RegularLayer .create( tech, 'METAL2' , metal2 ) + METAL3 = RegularLayer .create( tech, 'METAL3' , metal3 ) + METAL4 = RegularLayer .create( tech, 'METAL4' , metal4 ) + METAL5 = RegularLayer .create( tech, 'METAL5' , metal5 ) + METAL6 = RegularLayer .create( tech, 'METAL6' , metal6 ) + CONT_BODY_N = ContactLayer .create( tech, 'CONT_BODY_N', nImplant , active, cut0, metal1, None ) + CONT_BODY_P = ContactLayer .create( tech, 'CONT_BODY_P', pImplant , active, cut0, metal1, None ) + CONT_DIF_N = ContactLayer .create( tech, 'CONT_DIF_N' , nImplant , active, cut0, metal1, None ) + CONT_DIF_P = ContactLayer .create( tech, 'CONT_DIF_P' , pImplant , active, cut0, metal1, None ) + CONT_POLY = ViaLayer .create( tech, 'CONT_POLY' , poly, cut0, metal1 ) + + # VIAs for symbolic technologies. + VIA12 = ViaLayer .create( tech, 'VIA12' , metal1, cut1, metal2 ) + VIA23 = ViaLayer .create( tech, 'VIA23' , metal2, cut2, metal3 ) + #VIA23cap = ViaLayer .create( tech, 'VIA23cap' , metcap, cut2, metal3 ) + VIA34 = ViaLayer .create( tech, 'VIA34' , metal3, cut3, metal4 ) + VIA45 = ViaLayer .create( tech, 'VIA45' , metal4, cut4, metal5 ) + VIA56 = ViaLayer .create( tech, 'VIA56' , metal5, cut5, metal6 ) + BLOCKAGE1 = RegularLayer.create( tech, 'BLOCKAGE1' , blockage1 ) + BLOCKAGE2 = RegularLayer.create( tech, 'BLOCKAGE2' , blockage2 ) + BLOCKAGE3 = RegularLayer.create( tech, 'BLOCKAGE3' , blockage3 ) + BLOCKAGE4 = RegularLayer.create( tech, 'BLOCKAGE4' , blockage4 ) + BLOCKAGE5 = RegularLayer.create( tech, 'BLOCKAGE5' , blockage5 ) + BLOCKAGE6 = RegularLayer.create( tech, 'BLOCKAGE6' , blockage6 ) + + tech.setSymbolicLayer( CONT_BODY_N.getName() ) + tech.setSymbolicLayer( CONT_BODY_P.getName() ) + tech.setSymbolicLayer( CONT_DIF_N .getName() ) + tech.setSymbolicLayer( CONT_DIF_P .getName() ) + tech.setSymbolicLayer( CONT_POLY .getName() ) + tech.setSymbolicLayer( POLY .getName() ) + tech.setSymbolicLayer( METAL1 .getName() ) + tech.setSymbolicLayer( METAL2 .getName() ) + tech.setSymbolicLayer( METAL3 .getName() ) + tech.setSymbolicLayer( METAL4 .getName() ) + tech.setSymbolicLayer( METAL5 .getName() ) + tech.setSymbolicLayer( METAL6 .getName() ) + tech.setSymbolicLayer( BLOCKAGE1 .getName() ) + tech.setSymbolicLayer( BLOCKAGE2 .getName() ) + tech.setSymbolicLayer( BLOCKAGE3 .getName() ) + tech.setSymbolicLayer( BLOCKAGE4 .getName() ) + tech.setSymbolicLayer( BLOCKAGE5 .getName() ) + tech.setSymbolicLayer( BLOCKAGE6 .getName() ) + tech.setSymbolicLayer( VIA12 .getName() ) + tech.setSymbolicLayer( VIA23 .getName() ) + tech.setSymbolicLayer( VIA34 .getName() ) + tech.setSymbolicLayer( VIA45 .getName() ) + tech.setSymbolicLayer( VIA56 .getName() ) + + NWELL.setExtentionCap( nWell, l(0.0) ) + #PWELL.setExtentionCap( pWell, l(0.0) ) + + NTIE.setMinimalSize ( l(1.5) ) + NTIE.setExtentionCap ( nWell , l(0.75) ) + NTIE.setExtentionWidth( nWell , l(0.25) ) + NTIE.setExtentionCap ( nImplant, l(0.5) ) + NTIE.setExtentionWidth( nImplant, l(0.25) ) + NTIE.setExtentionCap ( active , l(0.25) ) + NTIE.setExtentionWidth( active , l(0.0) ) + + PTIE.setMinimalSize ( l(1.5) ) + PTIE.setExtentionCap ( nWell , l(0.75) ) + PTIE.setExtentionWidth( nWell , l(0.25) ) + PTIE.setExtentionCap ( nImplant, l(0.5) ) + PTIE.setExtentionWidth( nImplant, l(0.25) ) + PTIE.setExtentionCap ( active , l(0.25) ) + PTIE.setExtentionWidth( active , l(0.0) ) + + NDIF.setMinimalSize ( l(1.5) ) + NDIF.setExtentionCap ( nImplant, l(0.5) ) + NDIF.setExtentionWidth( nImplant, l(0.25) ) + NDIF.setExtentionCap ( active , l(0.25) ) + NDIF.setExtentionWidth( active , l(0.0) ) + + PDIF.setMinimalSize ( l(1.5) ) + PDIF.setExtentionCap ( pImplant, l(0.5) ) + PDIF.setExtentionWidth( pImplant, l(0.25) ) + PDIF.setExtentionCap ( active , l(0.25) ) + PDIF.setExtentionWidth( active , l(0.0) ) + + GATE.setMinimalSize ( l(0.5) ) + GATE.setExtentionCap ( poly , l(0.75) ) + + NTRANS.setMinimalSize ( l( 1.0) ) + NTRANS.setExtentionCap ( nImplant, l(-1.0) ) + NTRANS.setExtentionWidth( nImplant, l( 2.5) ) + NTRANS.setExtentionCap ( active , l(-1.5) ) + NTRANS.setExtentionWidth( active , l( 2.0) ) + + PTRANS.setMinimalSize ( l( 0.5) ) + PTRANS.setExtentionCap ( nWell , l(-0.5) ) + PTRANS.setExtentionWidth( nWell , l( 2.25) ) + PTRANS.setExtentionCap ( pImplant, l(-0.5) ) + PTRANS.setExtentionWidth( pImplant, l( 2.0) ) + PTRANS.setExtentionCap ( active , l(-0.75) ) + PTRANS.setExtentionWidth( active , l( 1.5) ) + + POLY .setMinimalSize ( l(0.5) ) + POLY .setExtentionCap ( poly , l(0.25) ) + #POLY2.setMinimalSize ( l(1.0) ) + #POLY2.setExtentionCap ( poly , l(0.5) ) + + METAL1 .setMinimalSize ( l(0.5) ) + METAL1 .setExtentionCap ( metal1 , l(0.25) ) + METAL2 .setMinimalSize ( l(0.5) ) + METAL2 .setExtentionCap ( metal2 , l(0.5) ) + METAL3 .setMinimalSize ( l(0.5) ) + METAL3 .setExtentionCap ( metal3 , l(0.5) ) + METAL4 .setMinimalSize ( l(0.5) ) + METAL4 .setExtentionCap ( metal4 , l(0.5) ) + METAL4 .setMinimalSpacing( l(1.5) ) + METAL5 .setMinimalSize ( l(1.0) ) + METAL5 .setExtentionCap ( metal5 , l(0.5) ) + #METAL6 .setMinimalSize ( l(2.0) ) + #METAL6 .setExtentionCap ( metal6 , l(1.0) ) + #METAL7 .setMinimalSize ( l(2.0) ) + #METAL7 .setExtentionCap ( metal7 , l(1.0) ) + #METAL8 .setMinimalSize ( l(2.0) ) + #METAL8 .setExtentionCap ( metal8 , l(1.0) ) + #METAL9 .setMinimalSize ( l(2.0) ) + #METAL9 .setExtentionCap ( metal9 , l(1.0) ) + #METAL10.setMinimalSize ( l(2.0) ) + #METAL10.setExtentionCap ( metal10 , l(1.0) ) + + # Contacts (i.e. Active <--> Metal) (symbolic). + CONT_BODY_N.setMinimalSize( l( 0.5) ) + CONT_BODY_N.setEnclosure ( nWell , l( 0.75), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( nImplant, l( 0.75), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_BODY_P.setMinimalSize( l( 0.5) ) + #CONT_BODY_P.setEnclosure ( pWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( pImplant, l( 0.75), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_N.setMinimalSize( l( 0.5) ) + CONT_DIF_N.setEnclosure ( nImplant, l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( active , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_P.setMinimalSize( l( 0.5) ) + CONT_DIF_P.setEnclosure ( pImplant, l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( active , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_POLY.setMinimalSize( l( 0.5) ) + CONT_POLY.setEnclosure ( poly , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + CONT_POLY.setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + + # VIAs (i.e. Metal <--> Metal) (symbolic). + VIA12 .setMinimalSize ( l( 0.5) ) + VIA12 .setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setEnclosure ( metal2 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setMinimalSpacing( l( 2.0) ) + VIA23 .setMinimalSize ( l( 0.5) ) + VIA23 .setEnclosure ( metal2 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setEnclosure ( metal3 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setMinimalSpacing( l( 2.0) ) + VIA34 .setMinimalSize ( l( 0.5) ) + VIA34 .setEnclosure ( metal3 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setEnclosure ( metal4 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setMinimalSpacing( l( 2.0) ) + VIA45 .setMinimalSize ( l( 0.5) ) + VIA45 .setEnclosure ( metal4 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setEnclosure ( metal5 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setMinimalSpacing( l( 2.0) ) + #VIA56 .setMinimalSize ( l( 1.0) ) + #VIA56 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setMinimalSpacing( l( 4.0) ) + #VIA67 .setMinimalSize ( l( 1.0) ) + #VIA67 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSize ( l( 1.0) ) + #VIA78 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA89 .setMinimalSize ( l( 1.0) ) + #VIA89 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setMinimalSpacing( l( 4.0) ) + #VIA910.setMinimalSize ( l( 1.0) ) + #VIA910.setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setEnclosure ( metal10 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setMinimalSpacing( l( 4.0) ) + + # Blockages (symbolic). + BLOCKAGE1 .setMinimalSize ( l( 0.5) ) + BLOCKAGE1 .setExtentionCap( blockage1 , l( 0.25) ) + BLOCKAGE2 .setMinimalSize ( l( 1.0) ) + BLOCKAGE2 .setExtentionCap( blockage2 , l( 0.25) ) + BLOCKAGE3 .setMinimalSize ( l( 1.0) ) + BLOCKAGE3 .setExtentionCap( blockage3 , l( 0.25) ) + BLOCKAGE4 .setMinimalSize ( l( 1.0) ) + BLOCKAGE4 .setExtentionCap( blockage4 , l( 0.25) ) + BLOCKAGE5 .setMinimalSize ( l( 1.0) ) + BLOCKAGE5 .setExtentionCap( blockage5 , l( 0.5) ) + #BLOCKAGE6 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE6 .setExtentionCap( blockage6 , l( 1.0) ) + #BLOCKAGE7 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE7 .setExtentionCap( blockage7 , l( 1.0) ) + #BLOCKAGE8 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE8 .setExtentionCap( blockage8 , l( 1.0) ) + #BLOCKAGE9 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE9 .setExtentionCap( blockage9 , l( 1.0) ) + #BLOCKAGE10.setMinimalSize ( l( 2.0) ) + #BLOCKAGE10.setExtentionCap( blockage10, l( 1.0) ) diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/klayout/sg13g2.lydrc b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/klayout/sg13g2.lydrc new file mode 100644 index 000000000..da9e16eb6 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/klayout/sg13g2.lydrc @@ -0,0 +1,768 @@ + + + + + + drc + + + + false + false + + true + drc_scripts + tools_menu.drc.end + dsl + drc-dsl-xml + +application = RBA::Application.instance +#main_window = application.main_window +#if main_window +# curr_layout_view = main_window.current_view() +# unless curr_layout_view +# layout_path = RBA::FileDialog::ask_open_file_name("Chose your layout file.", ".", "GDSII files (*.GDS *.gds *.GDS.gz *.gds.gz *.GDS2 *.gds2 *.GDS2.gz *.gds2.gz);; All files (*)") +# main_window.load_layout(layout_path, 1) +# curr_layout_view = main_window.current_view() +# end +#end +#active_layout = RBA::CellView::active.layout +#active_cellname = RBA::CellView::active.cell_name +#source(active_layout, active_cellname) +if $input + source($input, $top_cell) +end + +if $report == "" + report("SG13G2 DRC runset") +elsif $report + report("SG13G2 DRC runset", $report) +else + report("SG13G2 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "sg13g2_drc.txt")) +end +#if $input.dbu != 0.001 +# puts "WARNING: Layout dbu value (" + $input.dbu.to_s + " ) deviates from rule file dbu value (0.001). This will scale the layout and may not be intended." +#end +#report("design rules: sg13g2 | layout cell: " + active_cellname, "sg13g2.lyrdb") + +deep + +# Initial definitions of control flow variables +conditional_enabled = {} +conditional_enabled[:density] = false +conditional_enabled[:sanityRules] = true + +class DRC::DRCLayer + def ext_and(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self & other + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_area(constraint) + output_layer = self.dup + constraint.each do |expression| + output_layer.data.min_coherence = true + relation = expression[0] + value = expression[1].to_i + if relation == ">" + output_layer = output_layer.with_area((value + 1), nil) + elsif relation == "<" + output_layer = output_layer.with_area(nil, value) + elsif relation == "==" + output_layer = output_layer.with_area(value) + elsif relation == "!=" + output_layer = output_layer.without_area(value) + elsif relation == ">=" + output_layer = output_layer.with_area(value, nil) + elsif relation == "<=" + output_layer = output_layer.with_area(nil, (value + 1)) + else + raise "invalid expression" + end + end + return output_layer + end + + def ext_constraint_satisfied(value, constraint) + output_bool = true + constraint.each do |expression| + if expression[0] == ">" + output_bool = output_bool && (value > expression[1]) + elsif expression[0] == "<" + output_bool = output_bool && (value < expression[1]) + elsif expression[0] == "==" + output_bool = output_bool && (value == expression[1]) + elsif expression[0] == "!=" + output_bool = output_bool && (value != expression[1]) + elsif expression[0] == ">=" + output_bool = output_bool && (value >= expression[1]) + elsif expression[0] == "<=" + output_bool = output_bool && (value <= expression[1]) + else + raise "invalid expression" + end + end + return output_bool + end + + def ext_covering(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self.covering(other.inside(self)) + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_not(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self - other + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_or(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self | other + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_rectangles(axis_aligned = false, use_bbox = false, constraint1 = nil, constraint2 = nil, aspect_ratio_constraint = nil, inverted: false) + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + if ( ( constraint1 && ( !constraint2 || constraint1.length() > 1 || constraint1[0][0] != "==") ) || + ( constraint2 && ( constraint2.length() > 1 || constraint2[0][0] != "==" ) ) || + ( constraint1 && constraint2 && constraint1[0][1] != constraint2[0][1] ) ) + raise "ext_rectangle: unsupported options" + end + square = constraint1 ? true : false + shape_filter = + if use_bbox + @engine.extents + elsif axis_aligned + @engine.rectangles + else + @engine.if_all((@engine.corners == 270).count == 4, @engine.corners.count == 4) + end + if square + if use_bbox + shape_filter = @engine.if_all((@engine.extents.length == constraint1[0][1]).count == 4) + else + square_filter = (@engine.length == constraint1[0][1]).count == 4 + shape_filter = @engine.if_all(shape_filter, square_filter) + end + end + if inverted + output_layer = self.drc(! shape_filter) + else + output_layer = self.drc(shape_filter) + end + self.data.min_coherence = self_min_coherence_state + return output_layer + end + + def ext_ring + holes = self.holes + hulls = self.hulls + covering = hulls.covering(holes) + result = covering.and(self) + return result + end + + def ext_interacting_with_text(text_layer_number, text) + text_layer = @engine.labels(text_layer_number) + initial_merged_semantics = self.data.merged_semantics? + self.data.merged_semantics = false + result = self.interacting(text_layer.texts(text)) + self.data.merged_semantics = initial_merged_semantics + return result + end + + def ext_with_density(range, *args) + if self.is_empty? + return DRC::DRCLayer::new(@engine, RBA::Region::new()) + end + origin = 'cc' + tile_size = nil + tile_step = nil + arguments = [range] + args.each do |a| + if a.is_a?(DRC::DRCTileSize) + tile_size = a + arguments.push(tile_size) + elsif a.is_a?(DRC::DRCTileStep) + tile_step = a + arguments.push(tile_step) + elsif a.is_a?(String) + origin = a + else + raise "argument error" + end + end + bbox = @engine.extent.bbox + if origin == 'll' + origin_x = bbox.left + origin_y = bbox.bottom + tile_origin = DRC::DRCTileOrigin::new(origin_x, origin_y) + arguments.push(tile_origin) + elsif origin != 'cc' + raise "Unkown origin: 'cc' or 'll' expected" + end + if tile_size + return self.with_density(*arguments) + else + tile_size = DRC::DRCTileSize::new(bbox.width, bbox.height) + tile_count = DRC::DRCTileCount::new(1,2) + enlarged_bbox = bbox.enlarged(1.1).to_itype(@engine.dbu) + boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(enlarged_bbox)) + tile_boundary = DRC::DRCTileBoundary::new(boundary_layer) + result = self.with_density(*arguments, tile_size, tile_count, tile_boundary) + return result.raw.overlapping(DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu)))) + end + end +end +NWell_org = source.polygons("31/0") +NWell_pin_org = source.polygons("31/2") +Activ_org = source.polygons("1/0") +Activ_pin_org = source.polygons("1/2") +Activ_filler_org = source.polygons("1/22") +ThickGateOx_org = source.polygons("44/0") +GatPoly_org = source.polygons("5/0") +GatPoly_pin_org = source.polygons("5/2") +GatPoly_filler_org = source.polygons("5/22") +Cont_org = source.polygons("6/0") +Metal1_org = source.polygons("8/0") +Metal1_pin_org = source.polygons("8/2") +Metal1_filler_org = source.polygons("8/22") +Metal1_slit_org = source.polygons("8/24") +Via1_org = source.polygons("19/0") +Metal2_org = source.polygons("10/0") +Metal2_pin_org = source.polygons("10/2") +Metal2_filler_org = source.polygons("10/22") +Metal2_slit_org = source.polygons("10/24") +Via2_org = source.polygons("29/0") +Metal3_org = source.polygons("30/0") +Metal3_pin_org = source.polygons("30/2") +Metal3_filler_org = source.polygons("30/22") +Metal3_slit_org = source.polygons("30/24") +Via3_org = source.polygons("49/0") +Metal4_org = source.polygons("50/0") +Metal4_pin_org = source.polygons("50/2") +Metal4_filler_org = source.polygons("50/22") +Metal4_slit_org = source.polygons("50/24") +Via4_org = source.polygons("66/0") +Metal5_org = source.polygons("67/0") +Metal5_pin_org = source.polygons("67/2") +Metal5_filler_org = source.polygons("67/22") +Metal5_slit_org = source.polygons("67/24") +TopVia1_org = source.polygons("125/0") +TopMetal1_org = source.polygons("126/0") +TopMetal1_pin_org = source.polygons("126/2") +TopMetal1_filler_org = source.polygons("126/22") +TopMetal1_slit_org = source.polygons("126/24") +Vmim_org = source.polygons("129/0") +TopVia2_org = source.polygons("133/0") +TopMetal2_org = source.polygons("134/0") +TopMetal2_pin_org = source.polygons("134/2") +TopMetal2_filler_org = source.polygons("134/22") +TopMetal2_slit_org = source.polygons("134/24") +Passiv_org = source.polygons("9/0") +EdgeSeal_org = source.polygons("39/0") +BiWind_org = source.polygons("3/0") +PEmWind_org = source.polygons("11/0") +BasPoly_org = source.polygons("13/0") +DeepCo_org = source.polygons("35/0") +PEmPoly_org = source.polygons("53/0", "70/0") +EmPoly_org = source.polygons("55/0") +LDMOS_org = source.polygons("57/0") +PBiWind_org = source.polygons("58/0") +Flash_org = source.polygons("71/0") +ColWind_org = source.polygons("139/0") +SRAM_org = source.polygons("25/0") +TRANS_org = source.polygons("26/0") +NoDRC = source.polygons("62/0") +LBE_org = source.polygons("157/0") +NWell = NWell_org.ext_not(NoDRC) +Activ = Activ_org.ext_not(NoDRC) +ThickGateOx = ThickGateOx_org.ext_not(NoDRC) +GatPoly = GatPoly_org.ext_not(NoDRC) +Cont = Cont_org.ext_not(NoDRC) +ActFiller = Activ_filler_org.ext_not(NoDRC) +GatFiller = GatPoly_filler_org.ext_not(NoDRC) +Activ_pin = Activ_pin_org.ext_not(NoDRC) +GatPoly_pin = GatPoly_pin_org.ext_not(NoDRC) +NWell_pin = NWell_pin_org.ext_not(NoDRC) +Metal1 = Metal1_org.ext_not(NoDRC) +Via1 = Via1_org.ext_not(NoDRC) +Metal2 = Metal2_org.ext_not(NoDRC) +Via2 = Via2_org.ext_not(NoDRC) +Metal3 = Metal3_org.ext_not(NoDRC) +Via3 = Via3_org.ext_not(NoDRC) +Metal4 = Metal4_org.ext_not(NoDRC) +Via4 = Via4_org.ext_not(NoDRC) +Metal5 = Metal5_org.ext_not(NoDRC) +Vmim = Vmim_org.ext_not(NoDRC) +TopMetal1 = TopMetal1_org.ext_not(NoDRC) +TopVia2 = TopVia2_org.ext_not(NoDRC) +TopMetal2 = TopMetal2_org.ext_not(NoDRC) +Passiv = Passiv_org.ext_not(NoDRC) +EdgeSeal = EdgeSeal_org.ext_not(NoDRC) +M1Filler = Metal1_filler_org.ext_not(NoDRC) +M2Filler = Metal2_filler_org.ext_not(NoDRC) +M3Filler = Metal3_filler_org.ext_not(NoDRC) +M4Filler = Metal4_filler_org.ext_not(NoDRC) +M5Filler = Metal5_filler_org.ext_not(NoDRC) +TopMet1Filler = TopMetal1_filler_org.ext_not(NoDRC) +TopMet2Filler = TopMetal2_filler_org.ext_not(NoDRC) +M1Slit = Metal1_slit_org.ext_not(NoDRC) +M2Slit = Metal2_slit_org.ext_not(NoDRC) +M3Slit = Metal3_slit_org.ext_not(NoDRC) +M4Slit = Metal4_slit_org.ext_not(NoDRC) +M5Slit = Metal5_slit_org.ext_not(NoDRC) +TopMet1Slit = TopMetal1_slit_org.ext_not(NoDRC) +TopMet2Slit = TopMetal2_slit_org.ext_not(NoDRC) +Metal1_pin = Metal1_pin_org.ext_not(NoDRC) +Metal2_pin = Metal2_pin_org.ext_not(NoDRC) +Metal3_pin = Metal3_pin_org.ext_not(NoDRC) +Metal4_pin = Metal4_pin_org.ext_not(NoDRC) +Metal5_pin = Metal5_pin_org.ext_not(NoDRC) +TopMetal1_pin = TopMetal1_pin_org.ext_not(NoDRC) +TopMetal2_pin = TopMetal2_pin_org.ext_not(NoDRC) +TRANS = TRANS_org.ext_not(NoDRC) +SRAM = SRAM_org.ext_not(NoDRC) +LBE = LBE_org.ext_not(NoDRC) +TopVia1 = NoDRC.ext_or(Vmim_org).ext_or(TopVia1_org.ext_not(NoDRC)) +Activ_Act_a = Activ.width(150) +ThickGateOx_TGO_f = ThickGateOx.width(860) +Cont_SQ = Cont.ext_rectangles(true, false, [["==", 160]], [["==", 160]], nil) +ContBar = Cont.ext_area([[">", (0.16*0.16)*1000.0*1000.0]]) +Act_density = ActFiller.ext_or(Activ) +Gat_density = GatFiller.ext_or(GatPoly) +Act_Nsram = Activ.ext_not(SRAM) +GP_Nsram = GatPoly.ext_not(SRAM) +M1_Nsram = Metal1.ext_not(SRAM) +M2_Nsram = Metal2.ext_not(SRAM) +M3_Nsram = Metal3.ext_not(SRAM) +M4_Nsram = Metal4.ext_not(SRAM) +M5_Nsram = Metal5.ext_not(SRAM) +M1_density = M1Filler.ext_or(Metal1).ext_not(M1Slit) +M2_density = M2Filler.ext_or(Metal2).ext_not(M2Slit) +M3_density = M3Filler.ext_or(Metal3).ext_not(M3Slit) +M4_density = M4Filler.ext_or(Metal4).ext_not(M4Slit) +M5_density = M5Filler.ext_or(Metal5).ext_not(M5Slit) +TM1_density = TopMet1Filler.ext_or(TopMetal1).ext_not(TopMet1Slit) +TM2_density = TopMet2Filler.ext_or(TopMetal2).ext_not(TopMet2Slit) +emi2Pin = Metal2_pin.ext_and(TRANS).ext_interacting_with_text(63, "E") +GP_Nsram_Gat_a = GP_Nsram.width(130) +GP_Nsram_Gat_b = GP_Nsram.space(180) +transG2L = TRANS.ext_interacting_with_text(63, "npn13G2L").ext_covering(emi2Pin) + +-> do + Activ_Act_a.dup +end.().output("Act.a", "Min. Activ width = 0.15") + +-> do + Act_Nsram.space(210) +end.().output("Act.b", "Act.b: Min. Activ space or notch = 0.21") + +-> do + ThickGateOx_TGO_f.dup +end.().output("TGO.f", "Min. ThickGateOx width = 0.86") + +-> do + GP_Nsram_Gat_a.dup +end.().output("Gat.a", "Min GatPoly width = 0.13") + +-> do + GP_Nsram_Gat_b.dup +end.().output("Gat.b", "Min. GatPoly space or notch = 0.18") + +-> do + GP_Nsram.separation(Act_Nsram, 70) +end.().output("Gat.d", "Min. GatPoly to Activ space = 0.07") + +-> do + Cont.merged(true, 0).outside(EdgeSeal).ext_not(ContBar.ext_or(Cont_SQ)) +end.().output("Cnt.a", "Min.and max. size of Cont = 0.16") + +-> do + Cont.merged(true, 0).outside(EdgeSeal).space(180) +end.().output("Cnt.b", "Min. Cont space = 0.18") + +-> do + Passiv.width(2100) +end.().output("Pas.a", "Min. Passiv width = 2.10") + +-> do + Passiv.space(3500) +end.().output("Pas.b", "Min. Passiv space or notch = 3.50") + +-> do + Metal1.width(160) +end.().output("M1.a", "Min. width of Metal1 = 0.16") + +-> do + M1_Nsram.space(180) +end.().output("M1.b", "Min. Metal1 space or notch = 0.18") + +-> do + Metal2.width(200) +end.().output("M2.a", "Min. width of Metal2 = 0.2") + +-> do + M2_Nsram.space(210) +end.().output("M2.b", "Min. Metal2 space or notch = 0.21") + +-> do + Metal3.width(200) +end.().output("M3.a", "Min. width of Metal3 = 0.2") + +-> do + M3_Nsram.space(210) +end.().output("M3.b", "Min. Metal3 space or notch = 0.21") + +-> do + Metal4.width(200) +end.().output("M4.a", "Min. width of Metal4 = 0.2") + +-> do + M4_Nsram.space(210) +end.().output("M4.b", "Min. Metal4 space or notch = 0.21") + +-> do + Metal5.width(200) +end.().output("M5.a", "Min. width of Metal5 = 0.2") + +-> do + M5_Nsram.space(210) +end.().output("M5.b", "Min. Metal5 space or notch = 0.21") + +-> do + Via1.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) +end.().output("Via1.a", "Via1.a: Min. and Maxi. size of Via1 = 0.19") + +-> do + Via1.ext_not(EdgeSeal).space(220) +end.().output("Via1.b", "Via1.b: Min. Via1 space = 0.22") + +-> do + Via2.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) +end.().output("Via2.a", "Via2.a: Min. and Maxi. size of Via2 = 0.19") + +-> do + Via2.ext_not(EdgeSeal).space(220) +end.().output("Via2.b", "Via2.b: Min. Via2 space = 0.22") + +-> do + Via3.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) +end.().output("Via3.a", "Via3.a: Min. and Maxi. size of Via3 = 0.19") + +-> do + Via3.ext_not(EdgeSeal).space(220) +end.().output("Via3.b", "Via3.b: Min. Via3 space = 0.22") + +-> do + Via4.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) +end.().output("Via4.a", "Via4.a: Min. and Maxi. size of Via4 = 0.19") + +-> do + Via4.ext_not(EdgeSeal).space(220) +end.().output("Via4.b", "Via4.b: Min. Via4 space = 0.22") + +-> do + Vmim.ext_or(TopVia1.ext_not(EdgeSeal)).ext_rectangles(false, false, [["==", 420]], [["==", 420]], nil, inverted: true) +end.().output("TV1.a", "Min.and Max. TopVia1 (µm²) = 0.42") + +-> do + TopVia1.ext_or(Vmim).space(420) +end.().output("TV1.b", "Min. TopVia1 space = 0.42") + +-> do + TopMetal1.width(1640) +end.().output("TM1.a", "Min. width of TopMetal1 = 1.64") + +-> do + TopMetal1.space(1640) +end.().output("TM1.b", "Min. TopMetal1 space or notch = 1.64") + +-> do + TopMetal2.width(2000) +end.().output("TM2.a", "Min. width of TopMetal2 = 2.0") + +-> do + TopMetal2.space(2000) +end.().output("TM2.b", "Min. TopMetal2 space or notch = 2.0") + +-> do + TopVia2.ext_not(EdgeSeal).ext_rectangles(false, false, [["==", 900]], [["==", 900]], nil, inverted: true) +end.().output("TV2.a", "Min.and Max. TopVia2 = 0.90") + +-> do + TopVia2.space(1060) +end.().output("TV2.b", "Min. TopVia2 space = 1.06") + +if conditional_enabled[:density] + + -> do + Act_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("aFil.g", "Min. global Activ coverage = 35.0 %") + + -> do + Act_density.ext_with_density(0.55 .. 1.0, 'll') + end.().output("aFil.g1", "Max. global Activ coverage = 55.0 %") + + -> do + Act_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("aFil.g2", "Min. Active coverage ratio for any 800 x 800 µm² chip area = 25.0 %") + + -> do + Act_density.ext_with_density(0.65 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("aFil.g3", "Max. Active coverage ratio for any 800 x 800 µm² chip area = 65.0 %") + + -> do + Gat_density.ext_with_density(0.0 .. 0.15, 'll') + end.().output("GFil.g", "Min. global GatPoly density [%] = 15.0") + + -> do + M1_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M1.j", "Min. global Metal1 density [%] = 35.0") + + -> do + M1_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M1.k", "Max. global Metal1 density [%] = 60.0") + + -> do + M2_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M2.j", "Min. global Metal2 density [%] = 35.0") + + -> do + M2_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M2.k", "Max. global Metal2 density [%] = 60.0") + + -> do + M3_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M3.j", "Min. global Metal3 density [%] = 35.0") + + -> do + M3_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M3.k", "Max. global Metal3 density [%] = 60.0") + + -> do + M4_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M4.j", "Min. global Metal4 density [%] = 35.0") + + -> do + M4_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M4.k", "Max. global Metal4 density [%] = 60.0") + + -> do + M5_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M5.j", "Min. global Metal5 density [%] = 35.0") + + -> do + M5_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M5.k", "Max. global Metal5 density [%] = 60.0") + + -> do + M1_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M1Fil.h", "Min. Metal coverage MM1Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") + + -> do + M1_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M1Fil.k", "Max. Metal coverage MM1Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") + + -> do + M2_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M2Fil.h", "Min. Metal coverage MM2Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") + + -> do + M2_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M2Fil.k", "Max. Metal coverage MM2Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") + + -> do + M3_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M3Fil.h", "Min. Metal coverage MM3Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") + + -> do + M3_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M3Fil.k", "Max. Metal coverage MM3Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") + + -> do + M4_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M4Fil.h", "Min. Metal coverage MM4Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") + + -> do + M4_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M4Fil.k", "Max. Metal coverage MM4Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") + + -> do + M5_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M5Fil.h", "Min. Metal coverage MM5Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") + + -> do + M5_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M5Fil.k", "Max. Metal coverage MM5Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") + + -> do + TM1_density.ext_with_density(0.0 .. 0.25, 'll') + end.().output("TM1.c", "Min. global TopMetal1 density [%] = 25.00") + + -> do + TM1_density.ext_with_density(0.7 .. 1.0, 'll') + end.().output("TM1.d", "Max. global TopMetal1 density [%] = 70.00") + + -> do + TM2_density.ext_with_density(0.0 .. 0.25, 'll') + end.().output("TM2.c", "Min. global TopMetal1 density [%] = 25.0") + + -> do + TM2_density.ext_with_density(0.7 .. 1.0, 'll') + end.().output("TM2.c1", "Max. global TopMetal1 density [%] = 70.0") + + -> do + LBE.ext_with_density(0.2 .. 1.0, 'll') + end.().output("LBE.i", "Max. global LBE density [%] = 20.0 %") + +end + +if conditional_enabled[:sanityRules] + + -> do + Activ_pin.ext_not(Activ) + end.().output("forbidden.a", "Activ enclosure of Activ_pin = 0.0") + + -> do + GatPoly_pin.ext_not(GatPoly) + end.().output("forbidden.b", "GatPoly enclosure of GatPoly_pin = 0.0") + + -> do + NWell_pin.ext_not(NWell) + end.().output("forbidden.c", "NWell enclosure of NWell_pin = 0.0") + + -> do + Metal1_pin.ext_not(Metal1) + end.().output("forbidden.d", "Metal1 enclosure of Metal1_pin = 0.0") + + -> do + Metal2_pin.ext_not(Metal2) + end.().output("forbidden.f.M1", "Metal2 enclosure of Metal2_pin = 0.0") + + -> do + Metal3_pin.ext_not(Metal3) + end.().output("forbidden.f.M2", "Metal3 enclosure of Metal3_pin = 0.0") + + -> do + Metal4_pin.ext_not(Metal4) + end.().output("forbidden.f.M3", "Metal4 enclosure of Metal4_pin = 0.0") + + -> do + Metal5_pin.ext_not(Metal5) + end.().output("forbidden.f.M4", "Metal5 enclosure of Metal5_pin = 0.0") + + -> do + TopMetal1_pin.ext_not(TopMetal1) + end.().output("forbidden.f.M5", "TopMetal1 enclosure of TopMetal1_pin = 0.0") + + -> do + TopMetal2_pin.ext_not(TopMetal2) + end.().output("forbidden.f.MT1", "TopMetal2 enclosure of TopMetal2_pin = 0.0") + + -> do + BiWind_org.dup + end.().output("forbidden.Biwind", "Biwind forbidden layer in 0.13um designs") + + -> do + PEmWind_org.dup + end.().output("forbidden.PEmWind", "PEmWind forbidden layer in 0.13um designs") + + -> do + BasPoly_org.dup + end.().output("forbidden.BasPoly", "BasPoly forbidden layer in 0.13um designs") + + -> do + DeepCo_org.dup + end.().output("forbidden.DeepCo", "DeepCo forbidden layer in 0.13um designs") + + -> do + PEmPoly_org.dup + end.().output("forbidden.PEmPoly", "PEmPoly forbidden layer in 0.13um designs") + + -> do + EmPoly_org.dup + end.().output("forbidden.EmPoly", "EmPoly forbidden layer in 0.13um designs") + + -> do + LDMOS_org.dup + end.().output("forbidden.LDMOS", "LDMOS forbidden layer in 0.13um designs") + + -> do + PBiWind_org.dup + end.().output("forbidden.PBiWind", "PBiWind forbidden layer in 0.13um designs") + + -> do + Flash_org.dup + end.().output("forbidden.Flash", "Flash forbidden layer in 0.13um designs") + + -> do + ColWind_org.dup + end.().output("forbidden.ColWind", "ColWind forbidden layer in 0.13um designs") + +end + +-> do + LBE.width(100000) +end.().output("LBE.a", "LBE.a: Min. width of LBE = 100.0") + +-> do + LBE.drc(width > 1500000) +end.().output("LBE.b", "LBE.b: Max. width of LBE = 1500.0") + +-> do + LBE.ext_area([[">", 250000.0*1000.0*1000.0]]) +end.().output("LBE.b1", "LBE.b1: Max allowed LBE area = 250000.0") + +-> do + LBE.space(100000) +end.().output("LBE.c", "LBE.c: Min. LBE space or notch = 100.0") + +-> (;lbe_in_seal) do + lbe_in_seal = LBE.merged(true, 0).inside(EdgeSeal.holes.merge) + lbe_in_seal.separation(EdgeSeal, 150000) +end.().output("LBE.d", "LBE.d: Min. space of LBE to inner edge of Edge Seal = 150.0") + +-> do + LBE.ext_ring.dup +end.().output("LBE.h", "LBE.h: No LBE ring allowed") + + diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/klayout/sg13g2.lyp b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/klayout/sg13g2.lyp new file mode 100644 index 000000000..6c8cf9703 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/klayout/sg13g2.lyp @@ -0,0 +1,7016 @@ + + + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + 0 + Activ.drw + 1/0 + + + #00ff00 + #00ff00 + 0 + 0 + C1 + C1 + true + true + false + 1 + false + 0 + Activ.lbl + 1/1 + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + 0 + Activ.pin + 1/2 + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + 0 + Activ.net + 1/3 + + + #00ff00 + #00ff00 + 0 + 0 + C1 + C1 + false + true + false + 1 + false + 0 + Activ.bnd + 1/4 + + + #ffff00 + #ffff00 + 0 + 0 + I1 + C2 + true + true + false + 1 + false + 0 + Activ.lvs + 1/19 + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + 0 + Activ.msk + 1/20 + + + #00ff00 + #00ff00 + 0 + 0 + C3 + C0 + true + true + false + 1 + false + 0 + Activ.flr + 1/22 + + + #00ff00 + #00ff00 + 0 + 0 + I1 + C3 + true + true + false + 3 + false + 0 + Activ.nfl + 1/23 + + + #00cc66 + #00cc66 + 0 + 0 + C4 + C2 + false + true + false + 1 + false + 0 + Activ.opc + 1/26 + + + #00ff00 + #00ff00 + 0 + 0 + C5 + C2 + false + true + false + 1 + false + 0 + Activ.iop + 1/27 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + Activ.noq + 1/28 + + + #268c6b + #268c6b + 0 + 0 + C6 + C2 + false + true + false + 1 + false + 0 + BiWind.drw + 3/0 + + + #0000ff + #0000ff + 0 + 0 + I1 + C4 + false + true + false + 1 + false + 0 + BiWind.opc + 3/26 + + + #bf4026 + #bf4026 + 0 + 0 + C6 + C1 + true + true + false + 1 + false + 0 + GatPoly.drw + 5/0 + + + #bf4026 + #bf4026 + 0 + 0 + C1 + C1 + true + true + false + 1 + false + 0 + GatPoly.lbl + 5/1 + + + #bf4026 + #bf4026 + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + GatPoly.pin + 5/2 + + + #bf4026 + #bf4026 + 0 + 0 + C6 + C1 + false + true + false + 1 + false + 0 + GatPoly.net + 5/3 + + + #bf4026 + #bf4026 + 0 + 0 + C6 + C1 + false + true + false + 1 + false + 0 + GatPoly.bnd + 5/4 + + + #bf4026 + #bf4026 + 0 + 0 + C6 + C2 + true + true + false + 1 + false + 0 + GatPoly.flr + 5/22 + + + #bf4026 + #bf4026 + 0 + 0 + I1 + C3 + true + true + false + 3 + false + 0 + GatPoly.nfl + 5/23 + + + #ffff00 + #9900e6 + 0 + 0 + I1 + C5 + false + true + false + 1 + false + 0 + GatPoly.opc + 5/26 + + + #ffff00 + #ffff00 + 0 + 0 + C7 + C2 + false + true + false + 1 + false + 0 + GatPoly.iop + 5/27 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + GatPoly.noq + 5/28 + + + #00ffff + #00ffff + 0 + 0 + C8 + C1 + true + true + false + 1 + false + 0 + Cont.drw + 6/0 + + + #00ffff + #00ffff + 0 + 0 + C8 + C1 + false + true + false + 1 + false + 0 + Cont.net + 6/3 + + + #00ffff + #00ffff + 0 + 0 + C8 + C1 + false + true + false + 1 + false + 0 + Cont.bnd + 6/4 + + + #39bfff + #ffff00 + 0 + 0 + I1 + C5 + false + true + false + 1 + false + 0 + Cont.opc + 6/26 + + + #00cc66 + #00cc66 + 0 + 0 + C9 + C2 + false + true + false + 1 + false + 0 + nSD.drw + 7/0 + + + #00cc66 + #00cc66 + 0 + 0 + C10 + C2 + true + true + false + 1 + false + 0 + nSD.blk + 7/21 + + + #39bfff + #39bfff + 0 + 0 + C11 + C1 + true + true + false + 1 + false + 0 + Metal1.drw + 8/0 + + + #39bfff + #39bfff + 0 + 0 + C11 + C2 + false + true + false + 1 + false + 0 + Metal1.lbl + 8/1 + + + #39bfff + #39bfff + 0 + 0 + C11 + C2 + true + true + false + 1 + false + 0 + Metal1.pin + 8/2 + + + #39bfff + #39bfff + 0 + 0 + C11 + C2 + false + true + false + 1 + false + 0 + Metal1.net + 8/3 + + + #39bfff + #39bfff + 0 + 0 + I1 + C2 + false + true + false + 1 + false + 0 + Metal1.bnd + 8/4 + + + #39bfff + #39bfff + 0 + 0 + C11 + C1 + true + true + false + 1 + false + 0 + Metal1.msk + 8/20 + + + #39bfff + #39bfff + 0 + 0 + C11 + C0 + true + true + false + 1 + false + 0 + Metal1.flr + 8/22 + + + #39bfff + #39bfff + 0 + 0 + I1 + C3 + true + true + false + 3 + false + 0 + Metal1.nfl + 8/23 + + + #39bfff + #39bfff + 0 + 0 + I1 + C0 + true + true + false + 1 + false + 0 + Metal1.slt + 8/24 + + + #39bfff + #39bfff + 0 + 0 + C11 + C1 + true + true + false + 1 + false + 0 + Metal1.txt + 8/25 + + + #00ffff + #ffff00 + 0 + 0 + I1 + C6 + false + true + false + 1 + false + 0 + Metal1.opc + 8/26 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + Metal1.noq + 8/28 + + + #bf4026 + #bf4026 + 0 + 0 + C13 + C3 + true + true + false + 3 + false + 0 + Metal1.res + 8/29 + + + #39bfff + #39bfff + 0 + 0 + I1 + C4 + true + true + false + 1 + false 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false + 0 + Metal2.drw + 10/0 + + + #ccccd9 + #ccccd9 + 0 + 0 + C14 + C2 + false + true + false + 1 + false + 0 + Metal2.lbl + 10/1 + + + #ccccd9 + #ccccd9 + 0 + 0 + C14 + C2 + true + true + false + 1 + false + 0 + Metal2.pin + 10/2 + + + #ccccd9 + #ccccd9 + 0 + 0 + C14 + C1 + false + true + false + 1 + false + 0 + Metal2.net + 10/3 + + + #ccccd9 + #ccccd9 + 0 + 0 + C14 + C1 + false + true + false + 1 + false + 0 + Metal2.bnd + 10/4 + + + #ccccd9 + #ccccd9 + 0 + 0 + C14 + C2 + true + true + false + 1 + false + 0 + Metal2.msk + 10/20 + + + #ccccd9 + #ccccd9 + 0 + 0 + C14 + C0 + true + true + false + 1 + false + 0 + Metal2.flr + 10/22 + + + #ccccd9 + #ccccd9 + 0 + 0 + I1 + C3 + true + true + false + 3 + false + 0 + Metal2.nfl + 10/23 + + + #ccccd9 + #ccccd9 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + 0 + Metal2.slt + 10/24 + + + #ccccd9 + #ccccd9 + 0 + 0 + C14 + C8 + true + true + false + 3 + false + 0 + Metal2.txt + 10/25 + + + #ccccd9 + #ffff00 + 0 + 0 + I1 + C0 + false + true + false + 1 + false + 0 + Metal2.opc + 10/26 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + Metal2.noq + 10/28 + + + #bf4026 + #bf4026 + 0 + 0 + C13 + C3 + true + true + false + 3 + false + 0 + Metal2.res + 10/29 + + + #ccccd9 + #ccccd9 + 0 + 0 + I1 + C4 + true + true + false + 1 + false + 0 + Metal2.iprb + 10/33 + + + #ccccd9 + #ccccd9 + 0 + 0 + I1 + C4 + true + true + false + 1 + false + 0 + Metal2.difp + 10/34 + + + #bf4026 + #bf4026 + 0 + 0 + C15 + C1 + false + true + false + 1 + false + 0 + BasPoly.drw + 13/0 + + + #bf4026 + #bf4026 + 0 + 0 + C1 + C1 + false + true + false + 1 + false + 0 + BasPoly.lbl + 13/1 + + + #bf4026 + #bf4026 + 0 + 0 + C1 + C1 + false + true + false + 1 + false + 0 + BasPoly.pin + 13/2 + + + #bf4026 + #bf4026 + 0 + 0 + C16 + C1 + false + true + false + 1 + false + 0 + BasPoly.net + 13/3 + + + #bf4026 + #bf4026 + 0 + 0 + C1 + C1 + false + true + false + 1 + false + 0 + BasPoly.bnd + 13/4 + + + #ccb899 + #ccb899 + 0 + 0 + C17 + C1 + true + true + false + 1 + false + 0 + pSD.drw + 14/0 + + + #ffff00 + #ffff00 + 0 + 0 + C2 + C2 + false + true + false + 1 + false + 0 + NLDB.drw + 15/0 + + + #ff0000 + #ff0000 + 0 + 0 + C18 + C3 + true + true + false + 3 + false + 0 + DigiBnd.drw + 16/0 + + + #ff0000 + #ff0000 + 0 + 0 + C18 + C3 + true + true + false + 3 + false + 0 + DigiBnd.dw0 + 16/10 + + + #ccccff + #ccccff + 0 + 0 + C19 + C9 + true + true + false + 2 + false + 0 + Via1.drw + 19/0 + + + #ccccff + #ccccff + 0 + 0 + C19 + C1 + false + true + false + 1 + false + 0 + Via1.net + 19/3 + + + #ccccff + #ccccff + 0 + 0 + C19 + C1 + false + true + false + 1 + false + 0 + Via1.bnd + 19/4 + + + #ffe6bf + #ffe6bf + 0 + 0 + C20 + C2 + true + true + false + 1 + false + 0 + BackMetal1.drw + 20/0 + + + #ffe6bf + #ffe6bf + 0 + 0 + C20 + C2 + false + true + false + 1 + false + 0 + BackMetal1.lbl + 20/1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C20 + C2 + true + true + false + 1 + false + 0 + BackMetal1.pin + 20/2 + + + #ffe6bf + #ffe6bf + 0 + 0 + C20 + C2 + false + true + false + 1 + false + 0 + BackMetal1.net + 20/3 + + + #ffe6bf + #ffe6bf + 0 + 0 + I1 + C2 + false + true + false + 1 + false + 0 + BackMetal1.bnd + 20/4 + + + #ffe6bf + #ffe6bf + 0 + 0 + C20 + C2 + false + true + false + 1 + false + 0 + BackMetal1.msk + 20/20 + + + #ffe6bf + #ffe6bf + 0 + 0 + I1 + C2 + true + true + false + 1 + false + 0 + BackMetal1.flr + 20/22 + + + #ffe6bf + #ffe6bf + 0 + 0 + C20 + C2 + true + true + false + 1 + false + 0 + BackMetal1.nfl + 20/23 + + + #ffe6bf + #ffe6bf + 0 + 0 + C20 + C2 + true + true + false + 1 + false + 0 + BackMetal1.slt + 20/24 + + + #39bfff + #39bfff + 0 + 0 + C11 + C1 + true + true + false + 1 + false + 0 + BackMetal1.txt + 20/25 + + + #ffe6bf + #ffe6bf + 0 + 0 + C20 + C2 + false + true + false + 1 + false + 0 + BackMetal1.opc + 20/26 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + BackMetal1.noq + 20/28 + + + #bf4026 + #bf4026 + 0 + 0 + C13 + C3 + true + true + false + 3 + false + 0 + BackMetal1.res + 20/29 + + + #ffe6bf + #ffe6bf + 0 + 0 + I1 + C4 + true + true + false + 1 + false + 0 + BackMetal1.iprb + 20/33 + + + #ffe6bf + #ffe6bf + 0 + 0 + I1 + C4 + true + true + false + 1 + false + 0 + BackMetal1.difp + 20/34 + + + #ffe6bf + #ffe6bf + 0 + 0 + C20 + C2 + true + true + false + 1 + false + 0 + BackPassiv.drw + 23/0 + + + #bf4026 + #bf4026 + 0 + 0 + C13 + C3 + true + true + false + 3 + false + 0 + RES.drw + 24/0 + + + #bf4026 + #bf4026 + 0 + 0 + C2 + C3 + false + true + false + 3 + false + 0 + RES.lbl + 24/1 + + + #ffff00 + #ffff00 + 0 + 0 + C0 + C2 + false + true + false + 1 + false + 0 + SRAM.drw + 25/0 + + + #ffff00 + #ffff00 + 0 + 0 + C1 + C2 + false + true + false + 1 + false + 0 + SRAM.lbl + 25/1 + + + #ffff00 + #ffff00 + 0 + 0 + I1 + C2 + false + true + false + 1 + false + 0 + SRAM.bnd + 25/4 + + + #00ffff + #00ffff + 0 + 0 + C2 + C2 + false + true + false + 1 + false + 0 + TRANS.drw + 26/0 + + + #ffff00 + #ffff00 + 0 + 0 + I1 + C2 + true + true + false + 1 + false + 0 + IND.drw + 27/0 + + + #ffff00 + #ffff00 + 0 + 0 + C2 + C2 + true + true + false + 1 + false + 0 + IND.pin + 27/2 + + + #ffff00 + #ffff00 + 0 + 0 + I1 + C2 + true + true + false + 1 + false + 0 + IND.bnd + 27/4 + + + #ffff00 + #ffff00 + 0 + 0 + C2 + C2 + true + true + false + 1 + false + 0 + IND.txt + 27/25 + + + #9900e6 + #9900e6 + 0 + 0 + C21 + C0 + true + true + false + 1 + false + 0 + SalBlock.drw + 28/0 + + + #ff3736 + #ff3736 + 0 + 0 + C22 + C9 + true + true + false + 2 + false + 0 + Via2.drw + 29/0 + + + #ff3736 + #ff3736 + 0 + 0 + C22 + C9 + false + true + false + 2 + false + 0 + Via2.net + 29/3 + + + #ff3736 + #ff3736 + 0 + 0 + C22 + C2 + false + true + false + 1 + false + 0 + Via2.bnd + 29/4 + + + #d80000 + #d80000 + 0 + 0 + C23 + C2 + true + true + false + 1 + false + 0 + Metal3.drw + 30/0 + + + #d80000 + #d80000 + 0 + 0 + C23 + C1 + false + true + false + 1 + false + 0 + Metal3.lbl + 30/1 + + + #d80000 + #d80000 + 0 + 0 + C23 + C2 + true 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..*..*....*..*.. + .*....*..*....*. + *......**......* + *......**......* + .*....*..*....*. + ..*..*....*..*.. + ...**......**... + ...**......**... + ..*..*....*..*.. + .*....*..*....*. + *......**......* + *......**......* + .*....*..*....*. + ..*..*....*..*.. + ...**......**... + + 54 + stipple57 + + + ****.. + 0 + dashed + + + * + 1 + lineStyle0 + + + *** + 2 + solid + + + *.. + 3 + tdots + + + *.. + 4 + dots + + + **.. + 5 + shortDash + + + ****..**.. + 6 + doubleDash + + + ****........ + 7 + tdots2 + + + *** + 8 + thickLine + + + *** + 9 + mLine + + + **..**..**..**. + 10 + lineStyle1 + + + ***..*.. + 11 + dashDot + + diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/klayout/sg13g2.lyt b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/klayout/sg13g2.lyt new file mode 100644 index 000000000..d73e740b9 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/libs.tech/klayout/sg13g2.lyt @@ -0,0 +1,197 @@ + + + + sg13g2 + IHP SiGe 130nm technology + + 0.001 + $(appdata_path)/tech + $(appdata_path)/tech + sg13g2.lyp + true + + + 1 + true + true + + + true + layer_map() + true + true + + + true + layer_map() + 0.001 + true + #1 + true + #1 + false + #1 + true + OUTLINE + true + PLACEMENT_BLK + true + REGIONS + true + + 0 + true + .PIN + 2 + true + .PIN + 2 + true + .FILL + 5 + true + .OBS + 3 + true + .BLK + 4 + true + .LABEL + 1 + true + .LABEL + 1 + true + + 0 + true + + 0 + VIA_ + true + default + false + + merged.lef + + + false + true + true + 64 + 0 + 1 + 0 + DATA + 0 + 0 + BORDER + layer_map() + true + + + 0.001 + 1 + 100 + 100 + 0 + 0 + 0 + false + false + false + true + layer_map() + + + 0 + 0.001 + layer_map() + true + false + + + 1 + 0.001 + layer_map() + true + false + true + + + + + + GDS2 + + true + false + false + false + false + false + 8000 + 32000 + LIB + + + 2 + true + true + 1 + * + false + + + 0 + + + false + false + + + 0 + + true + + + + GatPoly,Cont,Metal1 + Diff,Cont,Metal1 + Metal1,Via1,Metal2 + Metal2,Via2,Metal3 + Metal3,Via3,Metal4 + Metal4,Via4,Metal5 + Metal5,TopVia1,TopMetal1 + TopMetal1,TopVia2,TopMetal2 + SalBlock='28/0' + Activ='1/0-Salblock' + GatPoly='5/0-SalBlock' + Diff='Activ-GatPoly' + Cont='6/0' + Metal1='8/0-8/29' + Via1='19/0' + Metal2='10/0-10/29' + Via2='29/0' + Metal3='30/0-30/29' + Via3='49/0' + Metal4='50/0-50/29' + Via4='66/0' + Metal5='67/0-67/29' + TopVia1='125/0' + TopMetal1='126/0-126/29' + TopVia2='133/0' + TopMetal2='134/0-134/29' + + diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/meson.build b/pdks/symbolic/lsxlib/sg13g2_lsx/meson.build new file mode 100644 index 000000000..1787a58b0 --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/meson.build @@ -0,0 +1,50 @@ + +project( + 'pdk_sg13g2_lsx', + version: '0.1.0', + meson_version: '>= 1.2.0', + default_options: ['warning_level=3'] +) + +python = import('python') +py = python.find_installation('python3') +py_deps = py.dependency() + +pdks_dir = py.get_install_dir() / 'pdks' / 'sg13g2_lsx' + +py_files = [ + 'libs.tech/coriolis/sg13g2_lsx/__init__.py', + 'libs.tech/coriolis/sg13g2_lsx/lsxlib.py', + 'libs.tech/coriolis/sg13g2_lsx/Sg13g2lsxSetup.py', + 'libs.tech/coriolis/sg13g2_lsx/techno_symb.py', + 'libs.tech/coriolis/sg13g2_lsx/techno.py', +] + +data_files = [ + 'libs.tech/coriolis/sg13g2_lsx/sg13g2_lsx.rds', + 'libs.tech/coriolis/sg13g2_lsx/symbolic.rds', + 'libs.tech/coriolis/sg13g2_lsx/symbolic.dreal', + 'libs.tech/coriolis/sg13g2_lsx/symbolic.graal', + 'libs.tech/coriolis/sg13g2_lsx/spimodel.cfg', +] + +exp_files = [ + 'libs.tech/coriolis/sg13g2_lsx/exp/lambda_lsx.exp', + 'libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.main.exp', + 'libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.rules.exp', + 'libs.tech/coriolis/sg13g2_lsx/exp/sg13g2_lsx.values.exp', + 'libs.tech/coriolis/sg13g2_lsx/exp/symbolic_lsx.rules.exp', +] + +klayout_files = [ + 'libs.tech/klayout/sg13g2.lydrc', + 'libs.tech/klayout/sg13g2.lyp', + 'libs.tech/klayout/sg13g2.lyt', +] + +py.install_sources( files(py_files) , subdir: 'pdks/sg13g2_lsx' ) +py.install_sources( files(data_files) , subdir: 'pdks/sg13g2_lsx' ) +py.install_sources( files(exp_files) , subdir: 'pdks/sg13g2_lsx' ) +py.install_sources( files(klayout_files) , subdir: 'pdks/sg13g2_lsx' ) + +install_subdir( 'libs.tech/globalfoundries-pdk-libs-gf180mcu_fd_pr/cells' , install_dir: pdks_dir / 'sg13g2_lsx' ) diff --git a/pdks/symbolic/lsxlib/sg13g2_lsx/pyproject.toml b/pdks/symbolic/lsxlib/sg13g2_lsx/pyproject.toml new file mode 100644 index 000000000..336f0c89b --- /dev/null +++ b/pdks/symbolic/lsxlib/sg13g2_lsx/pyproject.toml @@ -0,0 +1,25 @@ +[project] +name = "pdk_sg13g2_lsx" +version = "0.1.0" +description = "IHP sg13g2 lsxlib PDK for Coriolis EDA" +authors = [ { name = "Coriolis EDA Contributers" } ] +requires-python = ">= 3.8" + +[build-system] +requires = [ + "meson", + "meson-python", + "ninja", + "setuptools", + "cibuildwheel", + "build", + "pdm-backend" +] +build-backend = "mesonpy" + +[tool.meson] +build-dir = "build" + +[tool.cibuildwheel] +build = "cp310-*" +skip = ["cp36-*", "cp37-*", "pp*"] diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/__init__.py b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/Sky130lsxSetup.py b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/Sky130lsxSetup.py new file mode 100644 index 000000000..2eaeeaec8 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/Sky130lsxSetup.py @@ -0,0 +1,95 @@ + +import sys +import os +import socket +from pathlib import Path +from coriolis.designflow.task import ShellEnv + + +__all__ = [ 'Where', 'setupSky130_lsx' ] + + +class Where ( object ): + + coriolisTop = None + allianceTop = None + cellsTop = None + checkToolkit = None + + def __init__ ( self, checkToolkit=None ): + if 'CORIOLIS_TOP' in os.environ: Where.coriolisTop = Path( os.environ['CORIOLIS_TOP'] ) + if 'ALLIANCE_TOP' in os.environ: Where.allianceTop = Path( os.environ['ALLIANCE_TOP'] ) + if 'CELLS_TOP' in os.environ: Where.cellsTop = Path( os.environ['CELLS_TOP'] ) + if Where.coriolisTop and not Where.allianceTop: Where.allianceTop = Where.coriolisTop + #print( Where.coriolisTop, Where.allianceTop ) + if not Where.coriolisTop: + print( 'technos.Where.__init__(): Unable to locate Coriolis top.' ) + if checkToolkit is None: + checkToolkit = Path.home() / 'coriolis-2.x' / 'src' / 'alliance-check-toolkit' + else: + if isinstance(checkToolkit,str): + checkToolkit = Path( checkToolkit ) + if not Where.cellsTop: + Where.cellsTop = checkToolkit / 'cells' + Where.checkToolkit = checkToolkit + if not Where.cellsTop and Where.allianceTop: + Where.cellsTop = Where.allianceTop / 'cells' + ShellEnv.ALLIANCE_TOP = Where.allianceTop.as_posix() + + def __repr__ ( self ): + if not Where.coriolisTop: + return '' + return ''.format( Where.coriolisTop.as_posix() ) + +def setupSky130_lsx ( checkToolkit=None ): + Where( checkToolkit ) + ShellEnv().export() + + pdkDir = Where.checkToolkit / 'dks' / 'sky130_lsx' / 'libs.tech' + coriolisTechDir = pdkDir / 'coriolis' + if not pdkDir.is_dir(): + print( '[ERROR] technos.setupSky130_lsx(): PDK directory do *not* exists:' ) + print( ' "{}"'.format(techDir.as_posix()) ) + sys.path.append( coriolisTechDir.as_posix() ) + + cellsTop = Where.checkToolkit / 'cells' + liberty = cellsTop / 'lsxlib' / 'lsxlib.lib' + kdrcRules = pdkDir / 'klayout' / 'drc_sky130.lydrc' + + from coriolis import Cfg + from coriolis import Viewer + from coriolis import CRL + from coriolis.helpers import overlay, l, u, n + from coriolis.desigflow.yosys import Yosys + from coriolis.desigflow.klayout import DRC + from sky130_lsx import techno, lsxlib + techno.setup( coriolisTechDir ) + lsxlib.setup( cellsTop ) + + with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.misc.minTraceLevel = 1900 + cfg.misc.maxTraceLevel = 3000 + cfg.katana.eventsLimit = 1000000 + cfg.katana.termSatReservedLocal = 6 + cfg.katana.termSatThreshold = 9 + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + Yosys.setLiberty( liberty ) + DRC.setDrcRules( kdrcRules ) + ShellEnv.CHECK_TOOLKIT = Where.checkToolkit.as_posix() + + path = None + for pathVar in [ 'PATH', 'path' ]: + if pathVar in os.environ: + path = os.environ[ pathVar ] + os.environ[ pathVar ] = path + ':' + (Where.allianceTop / 'bin').as_posix() + break + + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/__init__.py b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/__init__.py new file mode 100644 index 000000000..b87e091fc --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/__init__.py @@ -0,0 +1,5 @@ + +import os +from pathlib import Path + +path = Path( os.path.dirname(os.path.abspath(__file__)) ) diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/Makefile b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/Makefile new file mode 100644 index 000000000..124bde9fb --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/Makefile @@ -0,0 +1,7 @@ +../sky130_lsx.rds: \ + sky130_lsx.main.exp \ + sky130_lsx.rules.exp \ + sky130_lsx.values.exp \ + symbolic_lsx.rules.exp \ + lambda_lsx.exp + $$HOME/coriolis-2.x/release/install/bin/exp -v2 -o $@ $< diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/README.rst b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/README.rst new file mode 100644 index 000000000..2029fefec --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/README.rst @@ -0,0 +1,82 @@ +------------------------------------------- +Process to make an realTechno.rds file +------------------------------------------ +/users/cao/mariem/coriolis/2023symbolic/StudySky130/README.rst + +version January 16, 2023, MML + February 2, 2023, MML + February 26, 2023, MML + March 1, 2023, MML + +techno target : sky130 (SkyWater130) + +library target : sxlib +/users/cao/mariem/coriolis-2.x/src/alliance-check-toolkit/cells/sxlib + +symbolic rules : 1 lambda is used (as poly gate minimal width (i.e. gate length of transistor (L))) + +------------------------------ +techno target : SkyWater130 nm +https://skywater-pdk.readthedocs.io/en/main + +process: +https://skywater-pdk.readthedocs.io/en/main/rules/assumptions.html#process-stack-diagram + +layers: +https://skywater-pdk.readthedocs.io/en/main/rules/layers.html#gds-layers-information + +rules: +https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html#x + +in LIP6: +/users/soft/freepdks/src/skywater-pdk/docs/rules/device-details/cap_mim +/users/soft/freepdks/src/skywater-pdk/libraries/sky130_fd_pr/latest +/users/cao/mariem/coriolis-2.x/src/alliance-check-toolkit/pdkmaster/C4M.Sky130/libs.tech/coriolis/techno/etc/coriolis2/node130/sky130 + +stream in/out map file +https://skywater-pdk.readthedocs.io/en/main/rules/layers.html#gds-layers-information + +GDS index: +https://skywater-pdk.readthedocs.io/en/main/rules/layers.html#gds-layers-information + +library target : sxlib +/users/cao/mariem/coriolis-2.x/src/alliance-check-toolkit/cells/sxlib + + +------------------------------ + +Programm used is : exp + It is part of alliance + The alliance environment has to be launched. This can be done using: + source sourceme + +Files requested : +sky130d1_1.main.exp + computing the data (scaling and extensions) for each layer, based on lambda value, and creation of the rds file + including : symbolic_1.rules.exp + sky130d1_1.rules.exp (real DRM rules, see below), + sky130d1_1.values.exp (GDS mask index see below) + +sky130d1_1.nice.exp + blot few layers and make the layout more beautifull ! + +sky130d1_1.rules.exp + real rules extracted manually from the PDK DRM, unit is micron + +sky130d1_1.values.exp + electrical values for the extractor, layer cif names and layer gds numbers + +lambda_1.exp + lambda computation, based on the investigation of all rules, and keeping the worse value (larger value) + +sourceme + to set alliance environment + source sourceme + +Makefile + make to generate sky130d1_1.rds file + uses files described above + +-------------------- +2024 Jul 31 +This file is now obsolete and will be rewritten soon. diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/lambda_lsx.exp b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/lambda_lsx.exp new file mode 100644 index 000000000..14de665e6 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/lambda_lsx.exp @@ -0,0 +1,173 @@ +[ +# date 20230223:1357 +# --------------------------------------------------------------------------- +# Lambda Definition +# --------------------------------------------------------------------------- + +# all lambda constraints +# ---------------------- + +BW_CTIE = BW_VIA0+2*BE_ATIE_VIA0; +BW_CDIF = BW_VIA0+2*BE_ACTI_VIA0; +SW_CDIF = SW_VIAX+2*SE_DIFX_VIA0; + +"Lambda: Pitch run NWELL - run NWELL ||" = + (RD_NWEL+BW_NWEL) + /(SD_WELL+SW_WELL); + +"Lambda: Pitch run NWELL - run NWELL |-" = + (RD_NWEL+BW_NWEL) + /(SD_WELL+2*SE_WELL); + +"Lambda: Pitch run DIF - run DIF" = + (RD_ACTI+BW_ACTI) + /(SD_DIFX+SW_DIFX); + +"Lambda: Pitch run DIF - contact DIF on VIA0" = + (BW_CDIF/2+RD_ACTI+BW_ACTI/2) + /(SW_CDIF/2+SD_DIFX+SW_DIFX/2) ; + +"Lambda: Pitch contact DIF on VIA0 - contact DIF on VIA0" = + (BW_CDIF+RD_ACTI) + /(SW_CDIF+SD_DIFX) ; + +"Lambda: Pitch run TRANSISTOR - run TRANSISTOR (1 active area)" = + (RD_GATE+BW_POLY) + /(SD_GATE+SW_POLY) ; + +"Lambda: Pitch run TRANSISTOR - run TRANSISTOR (2 actives area)" = + (BW_POLY+2*BE_ACTI_POLT+RD_ACTI) + /(SW_POLY+2*SE_DIFT_POLT+SD_DIFX) ; + +"Lambda: Pitch run TRANSISTOR - cont - run TRANSISTOR" = + (2*RD_POLR_VIA0+BW_VIA0+BW_POLY) + /(2*SD_POLY_VIA0+SW_VIAX+SW_POLY) ; + +"Lambda: Pitch contact PDIF on VIA0 - contact NDIF on VIA0" = + (BW_CDIF+BE_PIMP_ACTI+BE_NWEL_PIMP+RD_NWEL_ACTI) + /(SW_CDIF+SE_WELL_DIFX+SD_WELL_DIFX) ; + +"Lambda: Pitch contact NTIE on VIA0 - transistor gate (sidewise)" = + (BW_CTIE/2+BE_NTIE_ATIE+BE_PIMP_GATE) + /(SW_CDIF/2+SD_GATE_TIEX); + +"Lambda: Pitch contact PTIE on VIA0 - transistor gate (sidewise)" = + (BW_CTIE/2+BE_PTIE_ATIE+BE_NIMP_GATE) + /(SW_CDIF/2+SD_GATE_TIEX); + +if (def(BE_POLT), + "Lambda: Pitch contact NTIE on VIA0 - transistor gate (lengthwise)" = + (BW_CTIE/2+BE_NTIE_ATIE+BE_PIMP_GATE+BE_GATE_POLT+BE_POLT) + /(SW_CDIF/2+SD_GATE_TIEX+SE_GATE_POLT+SE_POLT), + + "Lambda: Pitch contact PTIE on VIA0 - transistor gate (lengthwise)" = + (BW_CTIE/2+BE_PTIE_ATIE+BE_NIMP_GATE+BE_GATE_POLT+BE_POLT) + /(SW_CDIF/2+SD_GATE_TIEX+SE_GATE_POLT+SE_POLT) +); + +"Lambda: minimal transistor" = + (BW_ACTI+BE_POLT_ACTI*2) + /(SW_DIFX+SE_POLT_DIFT*2); + +"Lambda: Pitch run POLY - run POLY" = + (RD_POLY+BW_POLY) + /(SD_POLY+SW_POLY) ; + +"Lambda: Pitch contact NTIE on VIA0 - contact NDIF on VIA0" = + (BW_CTIE+BE_NTIE_ATIE+BE_NWEL_NTIE+RD_NWEL_ACTI) + /(SW_CDIF+SE_WELL_DIFX+SD_WELL_DIFX) ; + +"Lambda: Pitch run POLY - contact POLY on VIA0" = + (BW_VIA0/2+BE_POLY_VIA0+RD_POLY+BW_POLY/2) + /(SW_VIAX/2+SE_POLY_VIA0+SD_POLY+SW_POLY/2); + +# as SD_POLY < SD_ALU1, it is impossible to have 2 contact closest +"Lambda: Pitch contact POLY on VIA0 - contact POLY on VIA0" = + (BW_VIA0+2*BE_POLY_VIA0+RD_POLY) + /(SW_VIAX+2*SE_POLY_VIA0+SD_ALU1) ; + +# --------------------------------------------------------------------------- + +"Lambda: Pitch run TRANS - run POLY" = + (BE_ACTI_POLT+RD_POLR_ACTI+BW_POLY) + /(SE_DIFT_POLT+SD_POLR_DIFT+SW_POLY) ; + +"Lambda: Pitch run DIF - run POLY" = + (BW_ACTI/2+RD_POLR_ACTI+BW_POLY/2) + /(SW_DIFX/2+SD_POLY_DIFX+SW_POLY/2) ; + +"Lambda: Pitch contact DIF on VIA0 - run POLY" = + (BW_VIA0/2+BE_ACTI_VIA0+RD_POLR_ACTI+BW_POLY/2) + /(SW_VIAX/2+SE_DIFX_VIA0+SD_POLY_DIFX+SW_POLY/2) ; + +"Lambda: Pitch contact DIF on VIA0 - contact POLY on VIA0" = + (BW_VIA0+BE_ACTI_VIA0+RD_POLR_ACTI+BE_POLY_VIA0) + /(SW_VIAX+SE_DIFX_VIA0+SD_POLY_DIFX+SE_POLY_VIA0) ; + +# --------------------------------------------------------------------------- + +"Lambda: Pitch run ALU1 - run ALU1" = + (RD_ALU1+BW_ALU1) + /(SD_ALU1+SW_ALU1) ; + +"Lambda: Pitch run ALU1 - contact ALU1 on VIA0" = + (BW_VIA0/2+BE_ALU1_VIA0+RD_ALU1+BW_ALU1/2) + /(SW_VIAX/2+SE_ALU1_VIA0+SD_ALU1+SW_ALU1/2) ; + +"Lambda: Pitch contact ALU1 on VIA0 - contact ALU1 on VIA0" = + (BW_VIA0+2*BE_ALU1_VIA0+RD_ALU1) + /(SW_VIAX+2*SE_ALU1_VIA0+SD_ALU1) ; + +"Lambda: Pitch VIA0 - VIA0" = + (BW_VIA0+RD_VIA0) + /(SW_VIAX+SD_VIA0) ; + +# --------------------------------------------------------------------------- + +"Lambda: Pitch run ALU2 - run ALU2" = + (RD_ALU2+BW_ALU2) + /(SD_ALU2+SW_ALU2) ; + +"Lambda: Pitch run ALU2 - contact ALU2 on VIA1" = + (BW_VIA1/2+BE_ALU2_VIA1+RD_ALU2+BW_ALU2/2) + /(SW_VIAX/2+SE_ALU2_VIA1+SD_ALU2+SW_ALU2/2) ; + +"Lambda: Pitch contact ALU2 on VIA1 - contact ALU2 on VIA1" = + (BW_VIA1+2*BE_ALU2_VIA1+RD_ALU2) + /(SW_VIAX+2*SE_ALU2_VIA1+SD_ALU2) ; + +"Lambda: Pitch contact ALU2 on VIA2 - contact ALU2 on VIA2" = + (BW_VIA1+2*BE_ALU2_VIA2+RD_ALU2) + /(SW_VIAX+2*SE_ALU2_VIA2+SD_ALU2) ; + +"Lambda: Pitch VIA1 - VIA1" = + (BW_VIA1+RD_VIA1) + /(SW_VIAX+SD_VIA1) ; + +# --------------------------------------------------------------------------- + +"Lambda: Pitch run ALU3 - run ALU3" = + (RD_ALU3+BW_ALU3) + /(SD_ALU3+SW_ALU3) ; + +"Lambda: Pitch run ALU3 - contact ALU3 on VIA2" = + (BW_VIA2/2+BE_ALU3_VIA2+RD_ALU3+BW_ALU3/2) + /(SW_VIAX/2+SE_ALU3_VIA2+SD_ALU3+SW_ALU3/2) ; + +"Lambda: Pitch contact ALU3 on VIA2 - contact ALU3 on VIA2" = + (BW_VIA2+2*BE_ALU3_VIA2+RD_ALU3) + /(SW_VIAX+2*SE_ALU3_VIA2+SD_ALU3) ; + +"Lambda: Pitch VIA1 - VIA1" = + (BW_VIA2+RD_VIA2) + /(SW_VIAX+SD_VIA2) ; + +# --------------------------------------------------------------------------- + +LAMBDA = sup(GRID, max('Lambda.*')); # finally LAMBDA is the greatest constraint +LAMBDA = inf(GRID, (LAMBDA+GRID)/2)*2; # but LAMBDA must be pair +]// + +[# print results +# --------------------------------------------------------------------------- +sort('Lambda.*')][message (LAMBDA)]// diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/removepwell.py b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/removepwell.py new file mode 100644 index 000000000..6de83e85a --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/removepwell.py @@ -0,0 +1,16 @@ +import os + +def remove_lines_with_pwell(directory): + # Parcourt tous les fichiers dans le répertoire courant + for filename in os.listdir(directory): + # Vérifie si le fichier a l'extension .ap + if filename.endswith('.ap'): + # Lis le fichier et stocke toutes les lignes sauf celles contenant 'PWELL' + with open(filename, 'r') as file: + lines = file.readlines() + + with open(filename, 'w') as file: + for line in lines: + if 'PWELL' not in line: + file.write(line) +remove_lines_with_pwell('./') diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/sky130_lsx.main.exp b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/sky130_lsx.main.exp new file mode 100644 index 000000000..0e6c55b9f --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/sky130_lsx.main.exp @@ -0,0 +1,472 @@ +# 20230301 +# --------------------------------------------------------------------------- +# For SkyWater130 +# --------------------------------------------------------------------------- + +include "symbolic_lsx.rules.exp" // +include "sky130_lsx.rules.exp" // +include "lambda_lsx.exp"// + +[# symbolic to real parametrisation +BE_POLT = (BW_ACTI + 2*BE_POLT_ACTI - (SW_DIFX + 2*SE_POLT_DIFT)*LAMBDA)/2; + +DW_NWEL = sup(GRID, BW_NWEL-SW_WELL*LAMBDA); +DW_PWEL = sup(GRID, BW_PWEL-SW_WELL*LAMBDA); +DW_POLY = sup(GRID, BW_POLY-SW_POLY*LAMBDA); +DW_POLY_CONT = sup(GRID, BW_VIA0+2*BE_POLY_VIA0-2*LAMBDA); +DW_TRAN_POLY = sup(GRID, DW_POLY); +DW_TRAN_ACTI = sup(GRID, 2*BE_ACTI_POLT+DW_POLY); +DW_ACTI = sup(GRID, BW_ACTI-SW_DIFX*LAMBDA); +DW_ATIE = sup(GRID, BW_ATIE-SW_DIFX*LAMBDA); +DW_ALU1 = sup(GRID, BW_ALU1-SW_ALU1*LAMBDA); +DW_ALU2 = sup(GRID, BW_ALU2-SW_ALU2*LAMBDA); +DW_ALU3 = sup(GRID, BW_ALU3-SW_ALU3*LAMBDA); + +DL_NWEL = sup(GRID, 2*LAMBDA); #DW_NWEL/2); +DL_PWEL = sup(GRID, 2*LAMBDA); #DW_PWEL/2); +DL_POLY = sup(GRID, BW_POLY/2); +DL_TRAN_POLY = sup(GRID, BE_POLT); +DL_TRAN_ACTI = sup(GRID, DL_TRAN_POLY-BE_POLT_ACTI); +DL_ACTI = sup(GRID, 2*LAMBDA+DL_TRAN_ACTI); +DL_ATIE = sup(GRID, BW_ATIE/2); +DL_ALU1 = sup(GRID, BW_ALU1/2); +DL_ALU2 = sup(GRID, BW_ALU2/2); +DL_ALU3 = sup(GRID, BW_ALU3/2); + +T_OFFSET = (BW_POLY - SW_POLY*LAMBDA)/2; # Drain & Source for extractor +]// + +# ------------------------------------------------------------------- +# globals define +# ------------------------------------------------------------------- + +define physical_grid [GRID] +define lambda [LAMBDA] + +include "sky130_lsx.values.exp" // +// +table mbk_to_rds_segment +# ---------------------------------------------------------------------------------- +# mbk_name rds_name1 dlr dwr offset mode rds_name2 dlr dwr offset mode +# ---------------------------------------------------------------------------------- +// calculation of the transisor offset + + nwell rds_nwell vw [ DL_NWEL+BE_NTIE_ATIE+BE_NWEL_NTIE ] [ DW_NWEL ] .0 all\ + rds_pimp vw [ DL_NWEL-BE_NWEL_PIMP ] [ DW_NWEL-2*(BE_NWEL_PIMP) ] .0 all + + pwell rds_pwell vw [ DL_PWEL+BE_PTIE_ATIE+BE_PWEL_PTIE ] [ DW_PWEL ] .0 all\ + rds_nimp vw [ DL_NWEL-BE_PWEL_NIMP ] [ DW_NWEL-2*(BE_PWEL_NIMP) ] .0 all + + ndif rds_activ vw [ DL_ACTI ] [ DW_ACTI ] .0 all\ + rds_ndif vw [ DL_ACTI ] [ DW_ACTI ] .0 ext + + pdif rds_activ vw [ DL_ACTI ] [ DW_ACTI ] .0 all\ + rds_pdif vw [ DL_ACTI ] [ DW_ACTI ] .0 ext + + ntie rds_activ vw [ DL_ATIE ] [ DW_ATIE ] .0 all\ + rds_ntie vw [ DL_ATIE+BE_NTIE_ATIE ] [ DW_ATIE+2*(BE_NTIE_ATIE) ] .0 all\ + rds_nwell vw [ DL_NWEL+BE_NTIE_ATIE+BE_NWEL_NTIE ] [ DW_ATIE+2*(BE_NTIE_ATIE+BE_NWEL_NTIE+LAMBDA)] .0 all + + ptie rds_activ vw [ DL_ATIE ] [ DW_ATIE ] .0 all\ + rds_ptie vw [ DL_ATIE+BE_PTIE_ATIE ] [ DW_ATIE+2*(BE_PTIE_ATIE) ] .0 all\ + rds_pwell vw [ DL_PWEL+BE_PTIE_ATIE+BE_PWEL_PTIE ] [ DW_ATIE+2*(BE_PTIE_ATIE+BE_PWEL_PTIE+LAMBDA)] .0 all + + ntrans rds_poly vw [ DL_TRAN_POLY ] [ DW_TRAN_POLY ] .0 all\ + rds_activ vw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI ] .0 drc\ + rds_ndif lcw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI/2 ] [T_OFFSET] ext\ + rds_ndif rcw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI/2 ] [T_OFFSET] ext + + ptrans rds_poly vw [ DL_TRAN_POLY ] [ DW_TRAN_POLY ] .0 all\ + rds_activ vw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI ] .0 drc\ + rds_pdif lcw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI/2 ] [T_OFFSET] ext\ + rds_pdif rcw [ DL_TRAN_ACTI ] [ DW_TRAN_ACTI/2 ] [T_OFFSET] ext + + poly rds_poly vw [ DL_POLY ] [ DW_POLY ] .0 all + poly2 rds_poly vw [ DL_POLY ] [ DW_POLY_CONT ] .0 all + + alu1 rds_alu1 vw [ DL_ALU1 ] [ DW_ALU1 ] .0 all + calu1 rds_alu1 vw [ DL_ALU1 ] [ DW_ALU1 ] .0 all + talu1 rds_talu1 vw [ DL_ALU1 ] [ DW_ALU1 ] .0 all + + alu2 rds_alu2 vw [ DL_ALU2 ] [ DW_ALU2 ] .0 all + calu2 rds_alu2 vw [ DL_ALU2 ] [ DW_ALU2 ] .0 all + talu2 rds_talu2 vw [ DL_ALU2 ] [ DW_ALU2 ] .0 all + + alu3 rds_alu3 vw [ DL_ALU3 ] [ DW_ALU3 ] .0 all + calu3 rds_alu3 vw [ DL_ALU3 ] [ DW_ALU3 ] .0 all + talu3 rds_talu3 vw [ DL_ALU3 ] [ DW_ALU3 ] .0 all +end + +table mbk_to_rds_connector +# ------------------------------------------------------------------- +# mbk_name rds_name der dwr +# ------------------------------------------------------------------- +end + +table mbk_to_rds_reference +# ------------------------------------------------------------------- +# mbk_name rds_name width +# ------------------------------------------------------------------- + ref_ref rds_ref [ BW_ALU1 ] + ref_con rds_ref [ BW_ALU1 ] +end + +table mbk_to_rds_via +# ------------------------------------------------------------------- +# mbk_name rds_name1 width mode rds_name2 width mode ... +## ------------------------------------------------------------------ + cont_body_n \ + rds_cont [ BW_VIA0 ] all\ + rds_alu1 [ BW_VIA0+2*(BE_ALU1_VIA0) ] all\ + rds_activ [ BW_VIA0+2*(BE_ATIE_VIA0) ] drc\ + rds_ntie [ BW_VIA0+2*(BE_ATIE_VIA0) ] ext + + cont_body_p \ + rds_cont [ BW_VIA0 ] all\ + rds_alu1 [ BW_VIA0+2*(BE_ALU1_VIA0) ] all\ + rds_activ [ BW_VIA0+2*(BE_ATIE_VIA0) ] drc\ + rds_ptie [ BW_VIA0+2*(BE_ATIE_VIA0) ] ext + + cont_dif_n \ + rds_cont [ BW_VIA0 ] all\ + rds_alu1 [ BW_VIA0+2*(BE_ALU1_VIA0) ] all\ + rds_activ [ BW_VIA0+2*(BE_ACTI_VIA0) ] drc\ + rds_ndif [ BW_VIA0+2*(BE_ACTI_VIA0) ] ext + + cont_dif_p \ + rds_cont [ BW_VIA0 ] all\ + rds_alu1 [ BW_VIA0+2*(BE_ALU1_VIA0) ] all\ + rds_activ [ BW_VIA0+2*(BE_ACTI_VIA0) ] drc\ + rds_pdif [ BW_VIA0+2*(BE_ACTI_VIA0) ] ext + + cont_poly \ + rds_cont [ BW_VIA0 ] all\ + rds_poly [ BW_VIA0+2*(BE_POLY_VIA0) ] all\ + rds_alu1 [ BW_VIA0+2*(BE_ALU1_VIA0) ] all + + cont_via \ + rds_via1 [ BW_VIA1 ] all\ + rds_alu1 [ BW_VIA1+2*(BE_ALU1_VIA1) ] all\ + rds_alu2 [ BW_VIA1+2*(BE_ALU2_VIA1) ] all + + cont_via2 \ + rds_via2 [ BW_VIA2 ] all\ + rds_alu2 [ BW_VIA2+2*(BE_ALU2_VIA2) ] all\ + rds_alu3 [ BW_VIA2+2*(BE_ALU3_VIA2) ] all +end + +table mbk_to_rds_bigvia_hole +# ------------------------------------------------------------------- +# mbk_via_name rds_hole_name side step mode +# ------------------------------------------------------------------- +end + +table mbk_to_rds_bigvia_metal +# ------------------------------------------------------------------- +# mbk_via_name rds_name dwr overlap mode +# ------------------------------------------------------------------- +end + +table mbk_to_rds_turnvia +# ------------------------------------------------------------------- +# mbk_name rds_name dwr mode +# ------------------------------------------------------------------- + cont_turn1 rds_alu1 [ DW_ALU1 ] all + cont_turn2 rds_alu2 [ DW_ALU2 ] all + cont_turn3 rds_alu3 [ DW_ALU3 ] all + cont_turn8 rds_poly [ DW_POLY_CONT ] all +end + +table lynx_bulk_implicit +# ------------------------------------------------------------------- +# rds_name type[explicit|implicit] +# ------------------------------------------------------------------- +end + +table lynx_transistor +# ------------------------------------------------------------------- +# mbk_name trans_name compostion +# ------------------------------------------------------------------- + NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL + PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL +end + +table lynx_diffusion +# ------------------------------------------------------------------- +# rds_name compostion +# ------------------------------------------------------------------- + rds_ndif rds_activ 1 rds_nimp 1 rds_nwell 0 + rds_pdif rds_activ 1 rds_pimp 1 rds_nwell 1 + rds_ntie rds_activ 1 rds_nimp 1 rds_nwell 1 + rds_ptie rds_activ 1 rds_pimp 1 rds_nwell 0 +end + +table lynx_graph +# ------------------------------------------------------------------- +# rds_name in_contact_with rds_name1 rds_name2 ... +# ------------------------------------------------------------------- + rds_ndif rds_cont rds_ndif + rds_pdif rds_cont rds_pdif + rds_poly rds_cont rds_poly2 rds_poly + rds_poly2 rds_cont rds_poly rds_poly2 + rds_cont rds_pdif rds_ndif rds_poly rds_poly2 rds_alu1 rds_cont + rds_via1 rds_alu1 rds_alu2 rds_via1 + rds_via2 rds_alu2 rds_alu3 rds_via2 + rds_alu1 rds_cont rds_via1 rds_ref rds_alu1 + rds_ref rds_cont rds_via1 rds_alu1 rds_ref + rds_alu2 rds_via1 rds_via2 rds_alu2 + rds_alu3 rds_via2 rds_alu3 +end + +table s2r_oversize_denotch +# ------------------------------------------------------------------- +# rds_name oversized_value_for_denotching +# ------------------------------------------------------------------- + rds_nwell [ sup(GRID,RD_NWEL/2) ] + rds_pwell [ sup(GRID,RD_PWEL/2) ] + rds_poly [ inf(GRID,RD_POLY/2-GRID) ] + rds_alu1 [ inf(GRID,RD_ALU1/2-GRID) ] + rds_alu2 [ inf(GRID,RD_ALU2/2-GRID) ] + rds_alu3 [ inf(GRID,RD_ALU3/2-GRID) ] + rds_activ [ inf(GRID,RD_ACTI/2-GRID) ] + rds_ntie [ sup(GRID,RD_NIMP/2) ] + rds_ptie [ sup(GRID,RD_PIMP/2) ] + rds_nimp [ sup(GRID,RD_NIMP/2) ] + rds_pimp [ sup(GRID,RD_NIMP/2) ] +end + +table s2r_bloc_ring_width +# ------------------------------------------------------------------- +# rds_name ring_width_to_copy_up +# ------------------------------------------------------------------- + rds_nwell 0. # [ RD_NWEL ] + rds_pwell 0. # [ RD_PWEL ] + rds_poly 0. # [ RD_POLY ] + rds_alu1 0. # [ RD_ALU1 ] + rds_alu2 0. # [ RD_ALU2 ] + rds_alu3 0. # [ RD_ALU3 ] + rds_activ 0. # [ RD_ACTI ] + rds_ntie 0. # [ RD_NIMP ] + rds_ptie 0. # [ RD_PIMP ] + rds_nimp 0. # [ RD_NIMP ] + rds_pimp 0. # [ RD_PIMP ] +end + +table s2r_minimum_layer_width +# ------------------------------------------------------------------- +# rds_name min_layer_width_to_keep +# ------------------------------------------------------------------- + rds_nwell [ BW_NWEL ] + rds_pwell [ BW_PWEL ] + rds_poly [ BW_POLY ] + rds_alu1 [ BW_ALU1 ] + rds_alu2 [ BW_ALU2 ] + rds_alu3 [ BW_ALU3 ] + rds_activ [ BW_ACTI ] + rds_ntie [ BW_NIMP ] + rds_ptie [ BW_PIMP ] + rds_nimp [ BW_NIMP ] + rds_pimp [ BW_PIMP ] +end + +table s2r_post_treat +# ------------------------------------------------------------------- +# rds_name s2r_must_treat_or_not second_layer_whenever_scotch +# ------------------------------------------------------------------- + rds_nwell treat null + rds_pwell treat null + rds_poly treat null + rds_activ treat null + rds_ntie treat rds_pimp + rds_ptie treat rds_nimp + rds_nimp treat rds_ptie + rds_pimp treat rds_ntie + rds_alu1 treat null + rds_alu2 treat null + rds_alu3 treat null + rds_cont notreat null +end + +DRC_RULES + +layer RDS_NWELL [ RW_NWEL ] ; +layer RDS_NTIE [ RW_NTIE ] ; +layer RDS_PTIE [ RW_PTIE ] ; +layer RDS_NIMP [ RW_NIMP ] ; +layer RDS_PIMP [ RW_PIMP ] ; +layer RDS_ACTIV [ RW_ACTI ] ; +layer RDS_CONT [ RW_VIA0 ] ; +layer RDS_POLY [ RW_POLY ] ; +layer RDS_ALU1 [ RW_ALU1 ] ; +layer RDS_ALU2 [ RW_ALU2 ] ; +layer RDS_ALU3 [ RW_ALU3 ] ; +layer RDS_USER0 [ GRID ] ; +layer RDS_USER1 [ GRID ] ; +layer RDS_USER2 [ GRID ] ; + +regles + +# note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# there is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# ---------------------------------------------------------- + +# check the nwell shapes +# ---------------------- +caracterise RDS_NWELL ( + regle {N=1;N++} : largeur >= [ RW_NWEL ] ; + regle {N++} : longueur_inter min [ RW_NWEL ] ; + regle {N++} : notch >= [ RD_NWEL ] ; +); +relation RDS_NWELL , RDS_NWELL ( + regle {N++} : distance axiale min [ RD_NWEL ] ; +); +relation RDS_NWELL , RDS_ACTI ( + regle {N++} : distance axiale min [ RD_NWEL_ACTI ] ; +); + +# check the RDS_PIMP shapes +# ------------------------- +caracterise RDS_PIMP ( + regle {N++} : surface min [ RA_PIMP ] ; + regle {N++} : largeur >= [ RW_PIMP ] ; + regle {N++} : longueur_inter min [ RW_PIMP ] ; + regle {N++} : notch >= [ RD_PIMP ] ; +); +relation RDS_PIMP , RDS_PIMP ( + regle {N++} : distance axiale min [ RD_PIMP ] ; +); + +# check the RDS_NIMP shapes +# ------------------------- +caracterise RDS_NIMP ( + regle {N++} : surface min [ RA_NIMP ] ; + regle {N++} : largeur >= [ RW_NIMP ] ; + regle {N++} : longueur_inter min [ RW_NIMP ] ; + regle {N++} : notch >= [ RD_NIMP ] ; +); +relation RDS_NIMP , RDS_NIMP ( + regle {N++} : distance axiale min [ RD_NIMP ] ; +); + +# check the RDS_PTIE shapes +# ------------------------- +caracterise RDS_PTIE ( + regle {N++} : surface min [ RA_PIMP ] ; + regle {N++} : largeur >= [ RW_PIMP ] ; + regle {N++} : longueur_inter min [ RW_PIMP ] ; + regle {N++} : notch >= [ RD_PIMP ] ; +); +relation RDS_PTIE , RDS_PTIE ( + regle {N++} : distance axiale min [ RD_PIMP ] ; +); + +# check the RDS_NTIE shapes +# ------------------------- +caracterise RDS_NTIE ( + regle {N++} : surface min [ RA_NIMP ] ; + regle {N++} : largeur >= [ RW_NIMP ] ; + regle {N++} : longueur_inter min [ RW_NIMP ] ; + regle {N++} : notch >= [ RD_NIMP ] ; +); +relation RDS_NTIE , RDS_NTIE ( + regle {N++} : distance axiale min [ RD_NIMP ] ; +); + +# check the RDS_ACTI shapes +# ------------------------- +caracterise RDS_ACTI ( + regle {N++} : surface min [ RA_ACTI ] ; + regle {N++} : largeur >= [ RW_ACTI ] ; + regle {N++} : longueur_inter min [ RW_ACTI ] ; + regle {N++} : notch >= [ RD_ACTI ] ; +); +relation RDS_ACTI, RDS_ACTI ( + regle {N++} : distance axiale min [ RD_ACTI ] ; +); + +# check the RDS_NIMP RDS_PTIE exclusion +# ------------------------------------- +define RDS_NIMP , RDS_PTIE intersection -> NPIMP; +caracterise NPIMP ( + regle {N++} : largeur = 0. ; +); +undefine NPIMP; + +# check the RDS_NTIE RDS_PIMP exclusion +# ------------------------------------- +define RDS_NTIE , RDS_PIMP intersection -> NPIMP; +caracterise NPIMP ( + regle {N++} : largeur = 0. ; +); +undefine NPIMP; + +# check the RDS_POLY shapes +# ------------------------- +caracterise RDS_POLY ( + regle {N++} : largeur >= [ RW_POLY ] ; + regle {N++} : longueur_inter min [ RW_POLY ] ; + regle {N++} : notch >= [ RD_POLY ] ; +); +relation RDS_POLY , RDS_POLY ( + regle {N++} : distance axiale min [ RD_POLY ] ; +); + +define RDS_ACTI , RDS_POLY intersection -> channel; + + # check the channel shapes + # ------------------------- + caracterise channel ( + regle {N++} : notch >= [ RD_GATE ] ; + ); + relation channel , channel ( + regle {N++} : distance axiale min [ RD_GATE ] ; + ); + +undefine channel; + +define RDS_ACTI , RDS_CONT intersection -> cont_diff; + + relation RDS_POLY , cont_diff ( + regle {N++} : distance axiale >= [ RD_POLR_VIA0 ] ; + ); + +undefine cont_diff; + +# check RDS_ALU1 shapes +# --------------------- +caracterise RDS_ALU1 ( + regle {N++} : surface min [ RA_ALU1 ] ; + regle {N++} : largeur >= [ RW_ALU1 ] ; + regle {N++} : longueur_inter min [ RW_ALU1 ] ; + regle {N++} : notch >= [ RD_ALU1 ] ; +); +relation RDS_ALU1 , RDS_ALU1 ( + regle {N++} : distance axiale min [ RD_ALU1 ] ; +); + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_CONT , RDS_CONT ( + regle {N++} : distance axiale >= [ RD_VIA0 ] ; +); + +caracterise RDS_CONT ( + regle {N++} : largeur = [ RW_VIA0 ] ; + regle {N++} : longueur = [ RW_VIA0 ] ; +); + +# check RDS_POLY is distant from activ zone of transistor +# ------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + regle {N++} : distance axiale >= [ RD_POLR_ACTI ] ; +); + +fin regles +DRC_COMMENT +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/sky130_lsx.rules.exp b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/sky130_lsx.rules.exp new file mode 100644 index 000000000..ed0ca53a4 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/sky130_lsx.rules.exp @@ -0,0 +1,160 @@ +[ +# ----------------------------------------------------------------------------- +# 16 january 2023, revision MML +# 23 january 2023, MML +# 2 february 2023, MML +# 1 march 2023, MML +# 18 april 2023, FW +# creation of two types of real rules: +# R) the true "Real" rules found in the PDK, they are prefixed by R +# B) the "Beautiful" rules computed to improve the quality of the layout without increasing the lambda, they are prefixed by B +# The lambda now is computed from low level mask (ALU1 and below) +# +# https://skywater-pdk.readthedocs.io/en/main/rules/summary.html +# https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html#x +# +# Layer Name +# +# NWEL : N WELL (NW) +# PWEL : P WELL (PW) +# NIMP : N+ implanted zone ("N+") +# PIMP : P+ implanted zone ("P+") +# NTIE : N+ implanted zone for NWELL body tie "NW STRAP" (NP) +# PTIE : P+ implanted zone for PWELL body tie "PW STRAP" (PP) +# ACTI : active zone (OD) (N+ ACTIVE or P+ACTIVE) +# ATIE : active zone +# POLY : POLY wire or Transistors ("PO" or "GATE") +# POLT : POLY transistor (T stands for Transistor) +# POLR : POLY wire (R stands for Run) +# VIA0 : CONTACT (cut to join ALU1 to POLX or DIFX) ("CO") # licon +# ALU1 : ALU first level (ALU1) # li local Interconnect to diff/tap and poly +# +# Real Rule type +# +# RA_LAYER : Real Area +# RW_LAYER : Real Width +# RD_LAYER : Real Distance between two edges of the same layer +# RD_LAYER1_LAYER2 : Real Distance between layer1 and layer2 +# RE_LAYER1_LAYER2 : Real Extension of Layer1 on Layer2 (all directions) +# REL_LAYER1_LAYER2 : Real Extension of Layer1 on Layer2 (linearly) +# +# In order to make layout "beautiful" (less edges) +# +# BW_LAYER : Beautiful Width +# BE_LAYER1_LAYER2 : Beautiful Extension of Layer1 on Layer2 +# +# GRID is the physical grid, every physical rule is a multiple of it. +# --------------------------------------------------------------------------- + +GRID = 0.005 ; # derived from distance values + +RA_ACTI = 0.0 ; # +RA_ATIE = 0.0 ; # +RA_NIMP = 0.265 ; # nsd.10a +RA_PIMP = 0.255 ; # psd.10b +RA_ALU1 = 0.06 ; # should be 0.0561 li.6, but DRUC want a GRID multiple value (it's a bug) +RA_ALU2 = 0.00 ; # FIXME +RA_ALU3 = 0.00 ; # FIXME + +RW_NWEL = 0.84 ; # nwell.1 +RW_PWEL = RW_NWEL; # is a choice, PWELL is for PIMP placement +RW_ACTI = 0.42 ; # difftap.2 for diff and poly transistor case +RW_ATIE = 0.15 ; # difftap.1 for diff in body tie +RW_NTIE = 0.38 ; # nsd.1 +RW_PTIE = 0.38 ; # psd.1 +RW_NIMP = 0.38 ; # nsd.1 +RW_PIMP = 0.38 ; # psd.1 +RW_POLY = 0.15 ; # poly.1a +RW_VIA0 = 0.17 ; # licon.1 +RW_VIA1 = 0.17 ; # FIXME +RW_VIA2 = 0.17 ; # FIXME +RW_ALU1 = 0.17 ; # li.1 +RW_ALU2 = 0.17 ; # FIXME +RW_ALU3 = 0.17 ; # FIXME + +RD_NWEL = 1.27 ; # nwell.2a +RD_PWEL = RD_NWEL; # like nwell space +RD_ACTI = 0.27 ; # difftap.3 +RD_ATIE = 0.27 ; # difftap.3 +RD_PIMP = 0.38 ; # psd.2 +RD_NIMP = 0.38 ; # nsd.2 +RD_POLY = 0.21 ; # poly.2a +RD_GATE = 0.21 ; # poly.2a to be checked +RD_VIA0 = 0.17 ; # licon.2 +RD_VIA1 = 0.17 ; # FIXME +RD_VIA2 = 0.17 ; # FIXME +RD_ALU1 = 0.17 ; # li.3 +RD_ALU2 = 0.17 ; # FIXME +RD_ALU3 = 0.17 ; # FIXME + +RD_POLR_ACTI = 0.075 ; # (poly.5 : 0.055) but Table 23 says 0.075 diff to poly on field +RD_POLR_ATIE = 0.075 ; # (poly.5 : 0.055) but Table 23 says 0.075 diff to poly on field +RD_POLR_VIA0 = 0.055 ; # licon.11 check meaning more POLYT-LICON +RD_NWEL_ACTI = 0.34 ; # difftap.9 + +RE_NWEL_PIMP = 0.055 ; # difftap.8 nwell over pdiff (not psd) - psd over difftap (psd.5a): 0.180 - 0.125 +RE_NWEL_NTIE = 0.055 ; # difftap.10 nwell over tap (not nsd) - nsd over difftap (nsd.5b) : 0.180 - 0.125 +RE_PWEL_NIMP = RE_NWEL_PIMP; # like RE_NWEL_PIMP ? +RE_PWEL_PTIE = RE_NWEL_NTIE; # like RE_NWEL_NTIE ? +RE_NIMP_GATE = 0.00 ; # NA ? +RE_PIMP_GATE = 0.00 ; # NA ? +RE_GATE_POLT = -0.130 ; # - poly.8 (RE_POLT_ACTI) to be checked see above RE_NIMP_GATE not found +RE_NIMP_ACTI = 0.125 ; # nsd.5a, butting edge nsd.6 : 0.00 +RE_PIMP_ACTI = 0.125 ; # psd.5a, butting edge psd.6 : 0.00 +RE_NTIE_ATIE = 0.125 ; # nsd.5b, butting edge nsd.6 : 0.00 +RE_PTIE_ATIE = 0.125 ; # psd.5b, butting edge psd.6 : 0.00 +RE_ACTI_POLT = 0.250 ; # poly.7 +RE_POLT_ACTI = 0.130 ; # poly.8 +RE_ACTI_VIA0 = 0.06 ; # licon.5a : 0.04, licon.5c : 0.06 sides and end +RE_ATIE_VIA0 = 0.06 ; # licon.5b, licon.7 : 0.12 isolated +RE_POLY_VIA0 = 0.08 ; # licon.8 : 0.05, ENCLOSURE POLY_LICON by POLY and one side licon.8a : 0.08 +RE_ALU1_VIA0 = 0.08 ; # li.5 : li over licon, 2 adjacent li sides +RE_ALU1_VIA1 = 0.08 ; # FIXME +RE_ALU2_VIA1 = 0.08 ; # FIXME +RE_ALU2_VIA2 = 0.08 ; # FIXME +RE_ALU3_VIA2 = 0.08 ; # FIXME + +# --------------------------------------------------------------------------- +# Modifications in order to get a more beautiful layout +# Symbolic technology for all metals : SW_VIAX+2*SE_ALUX_VIAX == SW_ALUX +# then it is possible to blot layers in order to have contacts included in wire +# --------------------------------------------------------------------------- + +BW_NWEL = RW_NWEL; +BW_PWEL = RW_PWEL; +BW_ACTI = RW_ACTI; +BW_ATIE = RW_ATIE + 0.14; +BW_NTIE = RW_NTIE; +BW_PTIE = RW_PTIE; +BW_NIMP = RW_NIMP; +BW_PIMP = RW_PIMP; +BW_POLY = RW_POLY; +BW_VIA0 = RW_VIA0; +BW_VIA1 = RW_VIA1; +BW_VIA2 = RW_VIA2; +BW_ALU1 = RW_VIA0+2*RE_ALU1_VIA0; # RW_ALU1 + 0.02; to have cont_alu1 width = 2 lambda alu1 wire width +BW_ALU2 = RW_VIA1+2*RE_ALU2_VIA1; # FIXME +BW_ALU3 = RW_VIA2+2*RE_ALU3_VIA2; # FIXME + +BE_NWEL_PIMP = RE_NWEL_PIMP; +BE_NWEL_NTIE = RE_NWEL_NTIE; +BE_PWEL_NIMP = RE_PWEL_NIMP; +BE_PWEL_PTIE = RE_PWEL_PTIE; +BE_NIMP_GATE = RE_NIMP_GATE; +BE_PIMP_GATE = RE_PIMP_GATE; +BE_GATE_POLT = RE_GATE_POLT; +BE_NIMP_ACTI = RE_NIMP_ACTI; +BE_PIMP_ACTI = RE_PIMP_ACTI; +BE_NTIE_ATIE = RE_NTIE_ATIE; +BE_PTIE_ATIE = RE_PTIE_ATIE; +BE_ACTI_POLT = RE_ACTI_POLT + 0.025; +BE_POLT_ACTI = RE_POLT_ACTI + 0.005; +BE_ACTI_VIA0 = RE_ACTI_VIA0 + 0.065; +BE_ATIE_VIA0 = RE_ATIE_VIA0; +BE_POLY_VIA0 = RE_POLY_VIA0; +BE_ALU1_VIA0 = RE_ALU1_VIA0; +BE_ALU1_VIA1 = RE_ALU1_VIA1; +BE_ALU2_VIA1 = RE_ALU2_VIA1; +BE_ALU2_VIA2 = RE_ALU2_VIA2; +BE_ALU3_VIA2 = RE_ALU3_VIA2; +]// diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/sky130_lsx.values.exp b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/sky130_lsx.values.exp new file mode 100644 index 000000000..791ec8385 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/sky130_lsx.values.exp @@ -0,0 +1,127 @@ +table cif_layer +# ------------------------------------------------------------------- +# rds_name cif_name +# ------------------------------------------------------------------- + rds_nwell nwel +# rds_pwell pwel + rds_activ active + rds_ntie nplus + rds_ptie pplus + rds_nimp nplus + rds_pimp pplus + rds_poly poly + rds_alu1 metal1 + rds_alu2 metal2 + rds_alu3 metal3 + rds_alu4 metal4 + rds_alu5 metal5 + rds_alu6 metal6 + rds_cont contact + rds_via1 via1 + rds_via2 via2 + rds_via3 via3 + rds_via4 via4 + rds_via5 via5 + rds_cpas pad +end + +table gds_layer +# ------------------------------------------------------------------- +# rds_name gds_number +# ------------------------------------------------------------------- + rds_nwell 3 +# rds_pwell 8 + rds_activ 6 + rds_ptie 25 + rds_ntie 26 + rds_pimp 25 + rds_nimp 26 + rds_poly 17 149 + rds_alu1 31 131 + rds_alu2 32 132 + rds_alu3 33 133 + rds_alu4 34 134 + rds_alu5 35 135 + rds_alu6 36 136 + rds_cont 30 + rds_via1 51 + rds_via2 52 + rds_via3 53 + rds_via4 54 + rds_via5 55 + rds_cpas 43 +end + +table lynx_resistor +# ------------------------------------------------------------------- +# rds_name square_resistor(ohm/square) # typical values +# ------------------------------------------------------------------- + rds_poly 48 + rds_alu1 13 + rds_alu2 0.125 + rds_alu3 0.125 + rds_alu4 0.047 + rds_alu5 0.047 + rds_alu6 0.029 + rds_cont 15 + rds_via1 152 + rds_via2 4.5 + rds_via3 3.4 + rds_via4 3.4 + rds_via5 0.38 +end + +table lynx_capa +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- + rds_poly 25.2e-6 51.8e-6 # Ca max POLY_NWELL 2Cf0 max POLY_NWELL + rds_alu1 2.6e-5 8.5e-5 # Ca max M1_NWELL 2Cf0 max M1_NWELL + rds_alu2 1.6e-5 7.9e-5 # Ca max M2_NWELL 2Cf0 max M2_NWELL + rds_alu3 8.0e-6 6.8e-5 # Ca max M3_NWELL 2Cf0 max M3_NWELL + rds_alu4 6.0e-6 6.0e-5 # Ca max M4_NWELL 2Cf0 max M4_NWELL + rds_alu5 6.0e-6 6.0e-5 # hyp + rds_alu6 6.0e-6 6.0e-5 +end + +table lynx_capa_poly +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_poly2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu1 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu3 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu4 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu5 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/symbolic_lsx.rules.exp b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/symbolic_lsx.rules.exp new file mode 100644 index 000000000..3e1413b14 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/exp/symbolic_lsx.rules.exp @@ -0,0 +1,70 @@ +[ +# 20230418 +# --------------------------------------------------------------------------- +# Symbolic layer names, which appear below, are not exactly the MBK names, +# because this file must contain as less values as possible. +# Theses names are chosen to avoid giving twice the same value. +# +# WELL : NWELL PWELL +# DIFR : NDIF, PDIF in wires +# DIFT : NDIF or PDIF in transistors +# TIEX : NTIE or PTIE +# DIFX : all DIFFUSIONs +# POLR : POLY wire +# POLT : POLY in Transistors +# POLY : POLR or POLT +# GATE : GATE is over POLT but not with the same lengthwise extension +# VIA0 : VIA0ACT (cut to join ALU1 to POLY or DIFX) +# ALU1 : METAL LEVEL 1 +# +# Symbolic rules type, minimum values (Theses Data should not be changed) +# +# SW_LAYER : Symbolic Width +# SE_LAYER : Symbolic Extension (if not defined, it is SW_LAYER/2) +# SD_LAYER : Symbolic Distance between two edges of the same layer +# SD_LAYER1_LAYER2 : Symbolic Distance between layer1 and layer2 +# SE_LAYER1_LAYER2 : Symbolic Extension of Layer1 on Layer2 +# -------------------------------------------------------------------------- + +SW_WELL = 4.0 ; +SW_DIFX = 3.0 ; # 2.0 +SW_POLY = 1.0 ; +SW_VIAX = 1.0 ; +SW_ALU1 = 2.0 ; + +SE_WELL = 2.0 ; +SE_POLT = 0.0 ; +SE_DIFX = 0.5 ; + +SD_WELL = 20.0 ; # 12.0 NWELL are never too close +SD_DIFX = 3.0 ; +SD_POLY = 2.5 ; # 2.0 +SD_GATE = 3.0 ; +SD_VIA0 = 3.0 ; +SD_ALU1 = 3.0 ; + +SD_WELL_DIFX = 7.5 ; +SD_GATE_TIEX = 3.0 ; +SD_POLY_DIFX = 1.0 ; +SD_POLR_DIFT = 1.5 ; +SD_POLY_VIA0 = 2.0 ; + +SE_WELL_DIFX = 0.5 ; +SE_GATE_POLT = -1.5 ; # lengthwise extension +SE_POLT_DIFT = 1.5 ; +SE_DIFT_POLT = 2.5 ; +SE_DIFX_VIA0 = 1.5 ; # 1.0 +SE_POLY_VIA0 = 0.5 ; # 1.0 +SE_ALU1_VIA0 = 0.5 ; +SE_ALU1_VIA1 = 0.5 ; + +SD_VIA1 = 3.0 ; +SW_ALU2 = 2.0 ; +SD_ALU2 = 3.0 ; +SE_ALU2_VIA1 = 0.5 ; +SE_ALU2_VIA2 = 0.5 ; +SD_VIA2 = 3.0 ; +SW_ALU3 = 2.0 ; +SD_ALU3 = 3.0 ; +SE_ALU3_VIA2 = 0.5 ; +] // diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/lsxlib.lib b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/lsxlib.lib new file mode 100644 index 000000000..575c17e08 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/lsxlib.lib @@ -0,0 +1,19782 @@ +/************************************************************************/ +/* */ +/* Avertec Release v3.4p5 (64 bits on Linux 5.14.0-427.22.1.el9_4.x86_64)*/ +/* argv: /dsk/l1/franck/coriolis-2.x/src/alliance-check-toolkit/bin/buildLib.tcl /dsk/l1/franck/coriolis-2.x/src/alliance-check-toolkit/pdkmaster/C4M.Sky130/libs.tech/ngspice/C4M.Sky130_logic_tt_model.spice hspice lsxlib */ +/* */ +/* User: franck */ +/* Generation date Thu Aug 1 18:25:21 2024 */ +/* */ +/* liberty data flow `lsxlib.lib` */ +/* */ +/************************************************************************/ + + + +library (lsxlib.lib) { + + technology (cmos) ; + date : "Thu Aug 1 18:25:21 2024" ; + delay_model : table_lookup ; + nom_voltage : 5.00 ; + nom_temperature : 70.0 ; + nom_process : 1.0 ; + slew_derate_from_library : 1.0 ; + default_fanout_load : 1000.0 ; + default_inout_pin_cap : 1000.0 ; + default_input_pin_cap : 1000.0 ; + default_output_pin_cap : 0.0 ; + voltage_unit : "1V" ; + time_unit : "1ps" ; + capacitive_load_unit (1,ff) ; + pulling_resistance_unit : "1ohm" ; + current_unit : "1mA" ; + leakage_power_unit : "1uW" ; + default_cell_leakage_power : 0.0 ; + input_threshold_pct_rise : 50.0 ; + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_rise : 50.0 ; + output_threshold_pct_fall : 50.0 ; + slew_lower_threshold_pct_fall : 20.0 ; + slew_upper_threshold_pct_fall : 80.0 ; + slew_lower_threshold_pct_rise : 20.0 ; + slew_upper_threshold_pct_rise : 80.0 ; + + lu_table_template (inslew_load_5x5__28) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.24, 2.48, 4.96, 9.93, 19.86"); + } + lu_table_template (inslew_5__0) { + variable_1 : input_net_transition; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + lu_table_template (inslew_load_5x5__27) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.73, 1.45, 2.90, 5.81, 11.62"); + } + lu_table_template (inslew_load_5x5__26) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.17, 2.34, 4.68, 9.35, 18.70"); + } + lu_table_template (inslew_load_5x5__25) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.27, 2.55, 5.09, 10.19, 20.37"); + } + lu_table_template (inslew_load_5x5__24) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.11, 2.22, 4.44, 8.87, 17.74"); + } + lu_table_template (inslew_load_5x5__23) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.99, 1.98, 3.97, 7.94, 15.88"); + } + lu_table_template (inslew_load_5x5__22) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.03, 2.07, 4.14, 8.28, 16.55"); + } + lu_table_template (inslew_load_5x5__21) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.94, 3.89, 7.78, 15.56, 31.11"); + } + lu_table_template (inslew_load_5x5__20) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.58, 3.15, 6.30, 12.60, 25.21"); + } + lu_table_template (inslew_load_5x5__19) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.15, 2.31, 4.61, 9.22, 18.45"); + } + lu_table_template (inslew_load_5x5__18) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.23, 2.47, 4.93, 9.86, 19.72"); + } + lu_table_template (inslew_load_5x5__17) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.09, 2.18, 4.36, 8.72, 17.44"); + } + lu_table_template (inslew_load_5x5__16) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.81, 1.63, 3.25, 6.51, 13.01"); + } + lu_table_template (inslew_load_5x5__15) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.42, 2.83, 5.66, 11.32, 22.64"); + } + lu_table_template (inslew_load_5x5__14) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.17, 2.34, 4.67, 9.35, 18.69"); + } + lu_table_template (inslew_load_5x5__13) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.21, 2.42, 4.85, 9.70, 19.39"); + } + lu_table_template (inslew_load_5x5__12) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.20, 2.39, 4.79, 9.58, 19.16"); + } + lu_table_template (inslew_load_5x5__11) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.28, 2.56, 5.13, 10.25, 20.51"); + } + lu_table_template (inslew_load_5x5__10) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.14, 2.27, 4.54, 9.08, 18.16"); + } + lu_table_template (inslew_load_5x5__9) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.54, 3.07, 6.14, 12.28"); + } + lu_table_template (inslew_load_5x5__8) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.50, 1.00, 2.00, 3.99, 7.98"); + } + lu_table_template (inslew_load_5x5__7) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.95, 5.90, 11.79, 23.59, 47.18"); + } + lu_table_template (inslew_load_5x5__6) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.97, 1.94, 3.88, 7.76, 15.52"); + } + lu_table_template (inslew_load_5x5__5) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.46, 4.93, 9.85, 19.70, 39.41"); + } + lu_table_template (inslew_load_5x5__4) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.44, 2.88, 5.75, 11.51, 23.02"); + } + lu_table_template (inslew_load_5x5__3) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.81, 1.62, 3.24, 6.49, 12.97"); + } + lu_table_template (inslew_load_5x5__2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.37, 2.74, 5.48, 10.96, 21.92"); + } + lu_table_template (inslew_load_5x5__1) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.19, 2.38, 4.77, 9.54, 19.07"); + } + lu_table_template (inslew_load_5x5__0) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.75, 1.50, 3.00, 5.99, 11.99"); + } + power_lut_template (energy_inslew_load_5x5__28) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.24, 2.48, 4.96, 9.93, 19.86"); + } + power_lut_template (energy_inslew_5__0) { + variable_1 : input_transition_time; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + power_lut_template (energy_inslew_load_5x5__27) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.73, 1.45, 2.90, 5.81, 11.62"); + } + power_lut_template (energy_inslew_load_5x5__26) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.17, 2.34, 4.68, 9.35, 18.70"); + } + power_lut_template (energy_inslew_load_5x5__25) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.27, 2.55, 5.09, 10.19, 20.37"); + } + power_lut_template (energy_inslew_load_5x5__24) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.11, 2.22, 4.44, 8.87, 17.74"); + } + power_lut_template (energy_inslew_load_5x5__23) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.99, 1.98, 3.97, 7.94, 15.88"); + } + power_lut_template (energy_inslew_load_5x5__22) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.03, 2.07, 4.14, 8.28, 16.55"); + } + power_lut_template (energy_inslew_load_5x5__21) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.94, 3.89, 7.78, 15.56, 31.11"); + } + power_lut_template (energy_inslew_load_5x5__20) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.58, 3.15, 6.30, 12.60, 25.21"); + } + power_lut_template (energy_inslew_load_5x5__19) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.15, 2.31, 4.61, 9.22, 18.45"); + } + power_lut_template (energy_inslew_load_5x5__18) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.23, 2.47, 4.93, 9.86, 19.72"); + } + power_lut_template (energy_inslew_load_5x5__17) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.09, 2.18, 4.36, 8.72, 17.44"); + } + power_lut_template (energy_inslew_load_5x5__16) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.81, 1.63, 3.25, 6.51, 13.01"); + } + power_lut_template (energy_inslew_load_5x5__15) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.42, 2.83, 5.66, 11.32, 22.64"); + } + power_lut_template (energy_inslew_load_5x5__14) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.17, 2.34, 4.67, 9.35, 18.69"); + } + power_lut_template (energy_inslew_load_5x5__13) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.21, 2.42, 4.85, 9.70, 19.39"); + } + power_lut_template (energy_inslew_load_5x5__12) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.20, 2.39, 4.79, 9.58, 19.16"); + } + power_lut_template (energy_inslew_load_5x5__11) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.28, 2.56, 5.13, 10.25, 20.51"); + } + power_lut_template (energy_inslew_load_5x5__10) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.14, 2.27, 4.54, 9.08, 18.16"); + } + power_lut_template (energy_inslew_load_5x5__9) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.54, 3.07, 6.14, 12.28"); + } + power_lut_template (energy_inslew_load_5x5__8) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.50, 1.00, 2.00, 3.99, 7.98"); + } + power_lut_template (energy_inslew_load_5x5__7) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.95, 5.90, 11.79, 23.59, 47.18"); + } + power_lut_template (energy_inslew_load_5x5__6) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.97, 1.94, 3.88, 7.76, 15.52"); + } + power_lut_template (energy_inslew_load_5x5__5) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.46, 4.93, 9.85, 19.70, 39.41"); + } + power_lut_template (energy_inslew_load_5x5__4) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.44, 2.88, 5.75, 11.51, 23.02"); + } + power_lut_template (energy_inslew_load_5x5__3) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.81, 1.62, 3.24, 6.49, 12.97"); + } + power_lut_template (energy_inslew_load_5x5__2) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.37, 2.74, 5.48, 10.96, 21.92"); + } + power_lut_template (energy_inslew_load_5x5__1) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.19, 2.38, 4.77, 9.54, 19.07"); + } + power_lut_template (energy_inslew_load_5x5__0) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.75, 1.50, 3.00, 5.99, 11.99"); + } + + + + + cell (a2_x2) { + area : 0.0 ; + cell_leakage_power : 1.6 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.52 ; + } + leakage_power () { + when : "(!(i0) | !(i1))" ; + value : 2.6 ; + } + pin (i1) { + direction : input ; + capacitance : 4.39 ; + } + pin (i0) { + direction : input ; + capacitance : 4.13 ; + } + pin (q) { + function : "(i0 & i1)" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("34.1, 34.1, 34.1, 40.9, 52.8", \ + "28.5, 28.5, 28.5, 35.5, 47.8", \ + "12.1, 12.1, 12.1, 19.3, 32.3", \ + "-27.3, -27.3, -27.3, -19.9, -6.2", \ + "-112.0, -112.0, -112.0, -104.3, -89.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("29.5, 29.5, 29.5, 39.0, 57.5", \ + "36.2, 36.2, 36.2, 45.8, 64.4", \ + "48.2, 48.2, 48.2, 57.8, 76.5", \ + "70.0, 70.0, 70.0, 79.7, 98.6", \ + "111.6, 111.6, 111.6, 121.4, 140.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("64.2, 64.2, 64.2, 70.8, 82.7", \ + "84.6, 84.6, 84.6, 91.7, 104.1", \ + "119.6, 119.6, 119.6, 127.0, 140.6", \ + "185.6, 185.6, 185.6, 192.9, 207.5", \ + "316.0, 316.0, 316.0, 323.1, 337.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("34.8, 34.8, 34.8, 39.4, 47.9", \ + "50.0, 50.0, 50.0, 54.6, 63.5", \ + "78.1, 78.1, 78.1, 82.8, 91.9", \ + "133.3, 133.3, 133.3, 138.0, 147.2", \ + "242.3, 242.3, 242.3, 247.2, 257.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("31.6, 31.6, 31.6, 38.4, 50.0", \ + "28.7, 28.7, 28.7, 35.7, 47.9", \ + "17.4, 17.4, 17.4, 24.6, 37.5", \ + "-11.0, -11.0, -11.0, -3.6, 10.2", \ + "-72.5, -72.5, -72.5, -64.8, -50.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("25.7, 25.7, 25.7, 35.2, 53.7", \ + "33.8, 33.8, 33.8, 43.3, 61.9", \ + "47.5, 47.5, 47.5, 57.1, 75.9", \ + "72.9, 72.9, 72.9, 82.6, 101.6", \ + "121.6, 121.6, 121.6, 131.3, 150.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("53.8, 53.8, 53.8, 60.5, 71.7", \ + "69.5, 69.5, 69.5, 76.3, 88.6", \ + "95.2, 95.2, 95.2, 102.6, 115.7", \ + "143.0, 143.0, 143.0, 150.6, 165.0", \ + "237.4, 237.4, 237.4, 244.6, 258.9"); + } + fall_transition (inslew_load_5x5__0) { + values ("29.0, 29.0, 29.0, 33.5, 41.9", \ + "42.0, 42.0, 42.0, 46.6, 55.3", \ + "66.0, 66.0, 66.0, 70.7, 79.7", \ + "113.2, 113.2, 113.2, 117.8, 127.1", \ + "206.2, 206.2, 206.2, 211.1, 220.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("265.7, 265.7, 265.7, 303.2, 378.1", \ + "304.0, 304.0, 304.0, 341.4, 416.4", \ + "378.2, 378.2, 378.2, 415.6, 490.6", \ + "523.3, 523.3, 523.3, 560.8, 635.7", \ + "810.6, 810.6, 810.6, 848.0, 923.0"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("361.3, 361.3, 361.3, 398.8, 473.7", \ + "490.4, 490.4, 490.4, 527.9, 602.8", \ + "741.4, 741.4, 741.4, 778.9, 853.8", \ + "1239.5, 1239.5, 1239.5, 1277.0, 1351.9", \ + "2233.4, 2233.4, 2233.4, 2270.9, 2345.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("218.2, 218.2, 218.2, 255.6, 330.6", \ + "261.1, 261.1, 261.1, 298.5, 373.5", \ + "343.7, 343.7, 343.7, 381.2, 456.1", \ + "506.7, 506.7, 506.7, 544.1, 619.1", \ + "829.9, 829.9, 829.9, 867.4, 942.3"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("296.9, 296.9, 296.9, 334.4, 409.3", \ + "404.7, 404.7, 404.7, 442.2, 517.1", \ + "614.3, 614.3, 614.3, 651.8, 726.7", \ + "1030.3, 1030.3, 1030.3, 1067.8, 1142.7", \ + "1860.2, 1860.2, 1860.2, 1897.7, 1972.6"); + } + } + } + } + + cell (a2_x4) { + area : 0.0 ; + cell_leakage_power : 1.8 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.52 ; + } + leakage_power () { + when : "(!(i0) | !(i1))" ; + value : 3.2 ; + } + pin (i1) { + direction : input ; + capacitance : 4.39 ; + } + pin (i0) { + direction : input ; + capacitance : 4.13 ; + } + pin (q) { + function : "(i1 & i0)" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("43.9, 43.9, 43.9, 49.6, 59.9", \ + "39.9, 39.9, 39.9, 45.7, 56.2", \ + "25.6, 25.6, 25.6, 31.6, 42.5", \ + "-11.1, -11.1, -11.1, -5.1, 6.3", \ + "-93.3, -93.3, -93.3, -87.1, -75.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("35.2, 35.2, 35.2, 42.9, 57.8", \ + "42.0, 42.0, 42.0, 49.7, 64.6", \ + "54.3, 54.3, 54.3, 62.0, 77.1", \ + "76.7, 76.7, 76.7, 84.4, 99.6", \ + "119.2, 119.2, 119.2, 126.9, 142.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("79.4, 79.4, 79.4, 85.1, 95.1", \ + "101.4, 101.4, 101.4, 107.3, 117.9", \ + "138.4, 138.4, 138.4, 144.4, 155.9", \ + "207.3, 207.3, 207.3, 212.8, 224.6", \ + "341.5, 341.5, 341.5, 347.1, 357.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("44.8, 44.8, 44.8, 48.4, 55.6", \ + "60.3, 60.3, 60.3, 64.0, 71.0", \ + "89.7, 89.7, 89.7, 93.3, 100.5", \ + "146.7, 146.7, 146.7, 150.5, 157.7", \ + "259.6, 259.6, 259.6, 263.4, 271.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("43.1, 43.1, 43.1, 48.8, 58.9", \ + "42.4, 42.4, 42.4, 48.2, 58.6", \ + "33.5, 33.5, 33.5, 39.5, 50.4", \ + "8.1, 8.1, 8.1, 14.1, 25.5", \ + "-51.0, -51.0, -51.0, -44.8, -32.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("31.9, 31.9, 31.9, 39.6, 54.5", \ + "40.1, 40.1, 40.1, 47.8, 62.7", \ + "54.3, 54.3, 54.3, 62.0, 77.1", \ + "80.3, 80.3, 80.3, 88.1, 103.3", \ + "130.0, 130.0, 130.0, 137.7, 153.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("69.8, 69.8, 69.8, 75.3, 85.3", \ + "87.0, 87.0, 87.0, 92.9, 103.1", \ + "114.9, 114.9, 114.9, 120.9, 132.1", \ + "165.4, 165.4, 165.4, 171.2, 183.0", \ + "263.5, 263.5, 263.5, 269.0, 279.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("38.8, 38.8, 38.8, 42.4, 49.3", \ + "52.2, 52.2, 52.2, 55.8, 62.9", \ + "77.2, 77.2, 77.2, 80.9, 88.0", \ + "126.1, 126.1, 126.1, 129.7, 136.9", \ + "222.4, 222.4, 222.4, 226.2, 233.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("446.7, 446.7, 446.7, 506.3, 625.5", \ + "502.5, 502.5, 502.5, 562.1, 681.3", \ + "609.8, 609.8, 609.8, 669.4, 788.6", \ + "815.8, 815.8, 815.8, 875.4, 994.6", \ + "1218.7, 1218.7, 1218.7, 1278.3, 1397.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("628.9, 628.9, 628.9, 688.5, 807.7", \ + "811.1, 811.1, 811.1, 870.7, 989.9", \ + "1164.1, 1164.1, 1164.1, 1223.7, 1342.9", \ + "1860.6, 1860.6, 1860.6, 1920.2, 2039.4", \ + "3248.5, 3248.5, 3248.5, 3308.1, 3427.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("391.5, 391.5, 391.5, 451.1, 570.3", \ + "455.9, 455.9, 455.9, 515.5, 634.7", \ + "577.1, 577.1, 577.1, 636.7, 755.9", \ + "810.8, 810.8, 810.8, 870.4, 989.6", \ + "1269.1, 1269.1, 1269.1, 1328.7, 1447.9"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("543.1, 543.1, 543.1, 602.7, 721.9", \ + "697.7, 697.7, 697.7, 757.3, 876.5", \ + "994.3, 994.3, 994.3, 1053.9, 1173.1", \ + "1579.7, 1579.7, 1579.7, 1639.3, 1758.5", \ + "2745.8, 2745.8, 2745.8, 2805.4, 2924.6"); + } + } + } + } + + cell (a3_x2) { + area : 0.0 ; + cell_leakage_power : 1.7 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 0.78 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2))" ; + value : 2.6 ; + } + pin (i2) { + direction : input ; + capacitance : 4.28 ; + } + pin (i1) { + direction : input ; + capacitance : 4.28 ; + } + pin (i0) { + direction : input ; + capacitance : 4.13 ; + } + pin (q) { + function : "(i2 & i0 & i1)" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("50.2, 50.2, 50.2, 57.3, 70.2", \ + "44.8, 44.8, 44.8, 52.1, 65.1", \ + "29.4, 29.4, 29.4, 36.8, 50.3", \ + "-7.9, -7.9, -7.9, -0.3, 13.8", \ + "-90.0, -90.0, -90.0, -82.2, -67.5"); + } + rise_transition (inslew_load_5x5__0) { + values ("45.3, 45.3, 45.3, 54.9, 73.6", \ + "51.5, 51.5, 51.5, 61.1, 79.9", \ + "63.5, 63.5, 63.5, 73.2, 92.1", \ + "86.3, 86.3, 86.3, 96.0, 115.2", \ + "130.3, 130.3, 130.3, 140.0, 159.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("73.8, 73.8, 73.8, 80.6, 92.8", \ + "94.9, 94.9, 94.9, 102.1, 114.8", \ + "130.3, 130.3, 130.3, 137.7, 151.5", \ + "196.4, 196.4, 196.4, 203.8, 218.4", \ + "325.6, 325.6, 325.6, 332.8, 347.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("40.2, 40.2, 40.2, 44.8, 53.5", \ + "55.0, 55.0, 55.0, 59.7, 68.8", \ + "82.8, 82.8, 82.8, 87.5, 96.7", \ + "137.0, 137.0, 137.0, 141.9, 151.2", \ + "244.3, 244.3, 244.3, 249.2, 259.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("48.0, 48.0, 48.0, 55.1, 67.7", \ + "46.2, 46.2, 46.2, 53.4, 66.3", \ + "36.5, 36.5, 36.5, 43.9, 57.4", \ + "10.7, 10.7, 10.7, 18.2, 32.4", \ + "-48.2, -48.2, -48.2, -40.4, -25.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("40.4, 40.4, 40.4, 50.0, 68.7", \ + "48.0, 48.0, 48.0, 57.6, 76.4", \ + "62.0, 62.0, 62.0, 71.7, 90.6", \ + "88.3, 88.3, 88.3, 98.0, 117.1", \ + "139.1, 139.1, 139.1, 148.8, 168.2"); + } + cell_fall (inslew_load_5x5__0) { + values ("65.3, 65.3, 65.3, 71.9, 83.9", \ + "81.7, 81.7, 81.7, 88.7, 101.2", \ + "108.2, 108.2, 108.2, 115.6, 129.0", \ + "156.3, 156.3, 156.3, 163.8, 178.3", \ + "250.0, 250.0, 250.0, 257.3, 271.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("35.2, 35.2, 35.2, 39.8, 48.4", \ + "47.9, 47.9, 47.9, 52.5, 61.5", \ + "71.6, 71.6, 71.6, 76.3, 85.4", \ + "118.0, 118.0, 118.0, 122.8, 132.1", \ + "209.5, 209.5, 209.5, 214.4, 224.1"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("44.0, 44.0, 44.0, 51.0, 63.3", \ + "45.4, 45.4, 45.4, 52.5, 65.3", \ + "41.8, 41.8, 41.8, 49.2, 62.6", \ + "28.7, 28.7, 28.7, 36.3, 50.5", \ + "-2.9, -2.9, -2.9, 5.0, 19.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("35.4, 35.4, 35.4, 44.9, 63.5", \ + "44.3, 44.3, 44.3, 53.9, 72.7", \ + "60.7, 60.7, 60.7, 70.3, 89.2", \ + "91.3, 91.3, 91.3, 101.1, 120.2", \ + "151.0, 151.0, 151.0, 160.7, 180.1"); + } + cell_fall (inslew_load_5x5__0) { + values ("55.3, 55.3, 55.3, 61.9, 73.3", \ + "66.9, 66.9, 66.9, 73.7, 85.9", \ + "84.2, 84.2, 84.2, 91.5, 104.4", \ + "114.2, 114.2, 114.2, 121.7, 135.9", \ + "171.6, 171.6, 171.6, 178.8, 193.4"); + } + fall_transition (inslew_load_5x5__0) { + values ("29.5, 29.5, 29.5, 34.1, 42.5", \ + "40.3, 40.3, 40.3, 44.9, 53.6", \ + "60.2, 60.2, 60.2, 64.9, 73.9", \ + "98.9, 98.9, 98.9, 103.6, 112.9", \ + "175.5, 175.5, 175.5, 180.4, 189.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("357.1, 357.1, 357.1, 394.6, 469.5", \ + "395.2, 395.2, 395.2, 432.7, 507.6", \ + "470.8, 470.8, 470.8, 508.3, 583.2", \ + "619.9, 619.9, 619.9, 657.4, 732.3", \ + "914.8, 914.8, 914.8, 952.3, 1027.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("423.3, 423.3, 423.3, 460.7, 535.7", \ + "552.3, 552.3, 552.3, 589.8, 664.7", \ + "803.7, 803.7, 803.7, 841.1, 916.1", \ + "1302.0, 1302.0, 1302.0, 1339.5, 1414.4", \ + "2296.0, 2296.0, 2296.0, 2333.5, 2408.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("309.0, 309.0, 309.0, 346.4, 421.4", \ + "352.6, 352.6, 352.6, 390.0, 465.0", \ + "437.5, 437.5, 437.5, 475.0, 549.9", \ + "604.2, 604.2, 604.2, 641.7, 716.6", \ + "934.6, 934.6, 934.6, 972.1, 1047.0"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("365.6, 365.6, 365.6, 403.1, 478.0", \ + "473.6, 473.6, 473.6, 511.1, 586.0", \ + "683.6, 683.6, 683.6, 721.1, 796.0", \ + "1099.9, 1099.9, 1099.9, 1137.4, 1212.3", \ + "1929.9, 1929.9, 1929.9, 1967.4, 2042.3"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("261.9, 261.9, 261.9, 299.3, 374.3", \ + "312.2, 312.2, 312.2, 349.7, 424.6", \ + "410.0, 410.0, 410.0, 447.5, 522.4", \ + "602.7, 602.7, 602.7, 640.2, 715.1", \ + "985.5, 985.5, 985.5, 1022.9, 1097.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("302.3, 302.3, 302.3, 339.8, 414.7", \ + "390.5, 390.5, 390.5, 428.0, 502.9", \ + "561.6, 561.6, 561.6, 599.0, 674.0", \ + "900.4, 900.4, 900.4, 937.8, 1012.8", \ + "1576.1, 1576.1, 1576.1, 1613.6, 1688.5"); + } + } + } + } + + cell (a3_x4) { + area : 0.0 ; + cell_leakage_power : 2 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 0.78 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2))" ; + value : 3.2 ; + } + pin (i2) { + direction : input ; + capacitance : 4.36 ; + } + pin (i1) { + direction : input ; + capacitance : 4.31 ; + } + pin (i0) { + direction : input ; + capacitance : 4.03 ; + } + pin (q) { + function : "(i1 & i2 & i0)" ; + direction : output ; + capacitance : 5.48 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("63.4, 63.4, 63.4, 70.2, 82.5", \ + "58.9, 58.9, 58.9, 65.7, 78.2", \ + "45.4, 45.4, 45.4, 52.2, 65.0", \ + "10.6, 10.6, 10.6, 17.6, 30.8", \ + "-68.8, -68.8, -68.8, -61.7, -48.0"); + } + rise_transition (inslew_load_5x5__2) { + values ("55.3, 55.3, 55.3, 64.1, 81.4", \ + "61.4, 61.4, 61.4, 70.2, 87.5", \ + "73.6, 73.6, 73.6, 82.5, 99.8", \ + "96.9, 96.9, 96.9, 105.8, 123.3", \ + "141.7, 141.7, 141.7, 150.6, 168.3"); + } + cell_fall (inslew_load_5x5__2) { + values ("90.3, 90.3, 90.3, 96.9, 108.4", \ + "112.9, 112.9, 112.9, 119.6, 131.8", \ + "150.4, 150.4, 150.4, 157.3, 170.3", \ + "219.3, 219.3, 219.3, 225.8, 239.3", \ + "352.7, 352.7, 352.7, 359.2, 371.8"); + } + fall_transition (inslew_load_5x5__2) { + values ("51.1, 51.1, 51.1, 55.3, 63.5", \ + "66.4, 66.4, 66.4, 70.6, 78.8", \ + "95.3, 95.3, 95.3, 99.5, 107.8", \ + "151.5, 151.5, 151.5, 155.9, 164.3", \ + "262.6, 262.6, 262.6, 267.0, 275.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("61.9, 61.9, 61.9, 68.6, 80.7", \ + "61.6, 61.6, 61.6, 68.4, 80.8", \ + "54.6, 54.6, 54.6, 61.4, 74.3", \ + "31.4, 31.4, 31.4, 38.4, 51.6", \ + "-24.5, -24.5, -24.5, -17.3, -3.5"); + } + rise_transition (inslew_load_5x5__2) { + values ("50.6, 50.6, 50.6, 59.4, 76.7", \ + "58.2, 58.2, 58.2, 67.0, 84.2", \ + "72.5, 72.5, 72.5, 81.4, 98.7", \ + "99.4, 99.4, 99.4, 108.3, 125.9", \ + "151.2, 151.2, 151.2, 160.0, 177.7"); + } + cell_fall (inslew_load_5x5__2) { + values ("82.0, 82.0, 82.0, 88.4, 99.8", \ + "100.1, 100.1, 100.1, 106.8, 118.6", \ + "129.0, 129.0, 129.0, 135.8, 148.6", \ + "179.9, 179.9, 179.9, 186.6, 200.1", \ + "277.5, 277.5, 277.5, 283.9, 296.5"); + } + fall_transition (inslew_load_5x5__2) { + values ("46.0, 46.0, 46.0, 50.2, 58.3", \ + "59.1, 59.1, 59.1, 63.3, 71.5", \ + "83.8, 83.8, 83.8, 88.0, 96.3", \ + "131.9, 131.9, 131.9, 136.2, 144.5", \ + "226.7, 226.7, 226.7, 231.1, 240.0"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("58.8, 58.8, 58.8, 65.4, 77.3", \ + "62.4, 62.4, 62.4, 69.2, 81.5", \ + "61.8, 61.8, 61.8, 68.6, 81.4", \ + "51.7, 51.7, 51.7, 58.8, 71.9", \ + "22.9, 22.9, 22.9, 30.1, 44.0"); + } + rise_transition (inslew_load_5x5__2) { + values ("45.6, 45.6, 45.6, 54.3, 71.5", \ + "54.9, 54.9, 54.9, 63.7, 81.0", \ + "71.6, 71.6, 71.6, 80.5, 97.8", \ + "102.9, 102.9, 102.9, 111.9, 129.4", \ + "163.6, 163.6, 163.6, 172.5, 190.2"); + } + cell_fall (inslew_load_5x5__2) { + values ("72.5, 72.5, 72.5, 78.8, 90.1", \ + "86.2, 86.2, 86.2, 92.8, 104.3", \ + "106.1, 106.1, 106.1, 112.9, 125.3", \ + "138.9, 138.9, 138.9, 145.8, 159.1", \ + "200.0, 200.0, 200.0, 206.4, 219.5"); + } + fall_transition (inslew_load_5x5__2) { + values ("40.1, 40.1, 40.1, 44.3, 52.2", \ + "51.3, 51.3, 51.3, 55.5, 63.7", \ + "72.1, 72.1, 72.1, 76.3, 84.5", \ + "112.4, 112.4, 112.4, 116.6, 124.9", \ + "191.7, 191.7, 191.7, 196.1, 204.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__2) { + values ("608.5, 608.5, 608.5, 677.1, 814.1", \ + "662.6, 662.6, 662.6, 731.1, 868.1", \ + "771.3, 771.3, 771.3, 839.8, 976.8", \ + "984.2, 984.2, 984.2, 1052.7, 1189.7", \ + "1402.4, 1402.4, 1402.4, 1470.9, 1607.9"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("726.9, 726.9, 726.9, 795.4, 932.4", \ + "909.5, 909.5, 909.5, 978.0, 1115.0", \ + "1262.9, 1262.9, 1262.9, 1331.4, 1468.4", \ + "1960.3, 1960.3, 1960.3, 2028.8, 2165.8", \ + "3348.4, 3348.4, 3348.4, 3416.9, 3553.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__2) { + values ("548.4, 548.4, 548.4, 616.9, 753.9", \ + "611.8, 611.8, 611.8, 680.3, 817.3", \ + "736.1, 736.1, 736.1, 804.6, 941.6", \ + "976.7, 976.7, 976.7, 1045.2, 1182.2", \ + "1449.3, 1449.3, 1449.3, 1517.8, 1654.8"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("651.5, 651.5, 651.5, 720.0, 857.0", \ + "805.2, 805.2, 805.2, 873.7, 1010.7", \ + "1102.7, 1102.7, 1102.7, 1171.3, 1308.3", \ + "1689.1, 1689.1, 1689.1, 1757.6, 1894.6", \ + "2855.4, 2855.4, 2855.4, 2923.9, 3060.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__2) { + values ("487.8, 487.8, 487.8, 556.3, 693.3", \ + "564.0, 564.0, 564.0, 632.5, 769.5", \ + "707.4, 707.4, 707.4, 775.9, 912.9", \ + "986.3, 986.3, 986.3, 1054.8, 1191.8", \ + "1535.3, 1535.3, 1535.3, 1603.8, 1740.8"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("567.1, 567.1, 567.1, 635.6, 772.6", \ + "695.1, 695.1, 695.1, 763.6, 900.6", \ + "939.8, 939.8, 939.8, 1008.3, 1145.3", \ + "1421.1, 1421.1, 1421.1, 1489.6, 1626.6", \ + "2378.2, 2378.2, 2378.2, 2446.7, 2583.7"); + } + } + } + } + + cell (a4_x2) { + area : 0.0 ; + cell_leakage_power : 1.8 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 1 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2) | !(i3))" ; + value : 2.6 ; + } + pin (i3) { + direction : input ; + capacitance : 4.39 ; + } + pin (i2) { + direction : input ; + capacitance : 4.34 ; + } + pin (i1) { + direction : input ; + capacitance : 4.28 ; + } + pin (i0) { + direction : input ; + capacitance : 4.34 ; + } + pin (q) { + function : "(i0 & i3 & i2 & i1)" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("68.4, 68.4, 68.4, 75.8, 89.4", \ + "62.2, 62.2, 62.2, 69.6, 83.4", \ + "47.3, 47.3, 47.3, 54.8, 68.9", \ + "11.8, 11.8, 11.8, 19.5, 33.9", \ + "-67.0, -67.0, -67.0, -59.1, -44.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("64.3, 64.3, 64.3, 73.9, 92.9", \ + "70.5, 70.5, 70.5, 80.2, 99.2", \ + "83.4, 83.4, 83.4, 93.1, 112.2", \ + "108.7, 108.7, 108.7, 118.5, 137.7", \ + "158.3, 158.3, 158.3, 168.1, 187.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("80.5, 80.5, 80.5, 87.5, 99.8", \ + "102.0, 102.0, 102.0, 109.2, 122.1", \ + "138.0, 138.0, 138.0, 145.4, 159.3", \ + "204.4, 204.4, 204.4, 211.8, 226.4", \ + "333.4, 333.4, 333.4, 340.7, 354.9"); + } + fall_transition (inslew_load_5x5__0) { + values ("44.2, 44.2, 44.2, 48.8, 57.7", \ + "58.8, 58.8, 58.8, 63.6, 72.6", \ + "86.5, 86.5, 86.5, 91.2, 100.5", \ + "140.4, 140.4, 140.4, 145.3, 154.7", \ + "247.1, 247.1, 247.1, 252.0, 262.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("65.2, 65.2, 65.2, 72.6, 85.9", \ + "63.4, 63.4, 63.4, 70.8, 84.4", \ + "55.2, 55.2, 55.2, 62.6, 76.7", \ + "31.6, 31.6, 31.6, 39.3, 53.7", \ + "-23.4, -23.4, -23.4, -15.5, -0.4"); + } + rise_transition (inslew_load_5x5__0) { + values ("58.2, 58.2, 58.2, 67.9, 86.8", \ + "65.9, 65.9, 65.9, 75.6, 94.6", \ + "81.1, 81.1, 81.1, 90.8, 109.9", \ + "110.3, 110.3, 110.3, 120.1, 139.3", \ + "167.1, 167.1, 167.1, 176.9, 196.3"); + } + cell_fall (inslew_load_5x5__0) { + values ("73.0, 73.0, 73.0, 79.7, 92.0", \ + "90.1, 90.1, 90.1, 97.2, 109.8", \ + "117.3, 117.3, 117.3, 124.7, 138.3", \ + "166.0, 166.0, 166.0, 173.6, 188.0", \ + "259.7, 259.7, 259.7, 267.0, 281.3"); + } + fall_transition (inslew_load_5x5__0) { + values ("39.5, 39.5, 39.5, 44.2, 52.9", \ + "52.2, 52.2, 52.2, 56.9, 66.0", \ + "75.9, 75.9, 75.9, 80.6, 89.8", \ + "122.0, 122.0, 122.0, 126.8, 136.2", \ + "213.0, 213.0, 213.0, 218.0, 227.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("60.6, 60.6, 60.6, 67.9, 81.0", \ + "62.6, 62.6, 62.6, 70.0, 83.4", \ + "61.1, 61.1, 61.1, 68.6, 82.6", \ + "50.8, 50.8, 50.8, 58.5, 73.0", \ + "23.4, 23.4, 23.4, 31.3, 46.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("51.9, 51.9, 51.9, 61.5, 80.4", \ + "61.2, 61.2, 61.2, 70.8, 89.8", \ + "79.0, 79.0, 79.0, 88.8, 107.8", \ + "113.0, 113.0, 113.0, 122.8, 142.1", \ + "179.6, 179.6, 179.6, 189.4, 208.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("64.5, 64.5, 64.5, 71.1, 83.1", \ + "77.1, 77.1, 77.1, 84.0, 96.4", \ + "95.4, 95.4, 95.4, 102.8, 115.9", \ + "126.2, 126.2, 126.2, 133.7, 148.0", \ + "183.8, 183.8, 183.8, 191.1, 205.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("34.6, 34.6, 34.6, 39.3, 47.8", \ + "45.3, 45.3, 45.3, 50.0, 58.9", \ + "65.2, 65.2, 65.2, 69.9, 79.0", \ + "103.8, 103.8, 103.8, 108.5, 117.9", \ + "180.0, 180.0, 180.0, 184.9, 194.4"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("53.5, 53.5, 53.5, 60.6, 73.4", \ + "58.8, 58.8, 58.8, 66.1, 79.3", \ + "61.8, 61.8, 61.8, 69.2, 83.1", \ + "60.8, 60.8, 60.8, 68.6, 83.0", \ + "53.0, 53.0, 53.0, 60.9, 76.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("44.5, 44.5, 44.5, 54.1, 72.8", \ + "55.4, 55.4, 55.4, 65.1, 83.9", \ + "74.9, 74.9, 74.9, 84.6, 103.6", \ + "111.8, 111.8, 111.8, 121.6, 140.8", \ + "184.0, 184.0, 184.0, 193.7, 213.2"); + } + cell_fall (inslew_load_5x5__0) { + values ("55.4, 55.4, 55.4, 62.0, 73.4", \ + "64.5, 64.5, 64.5, 71.3, 83.5", \ + "76.5, 76.5, 76.5, 83.7, 96.5", \ + "95.2, 95.2, 95.2, 102.6, 116.6", \ + "128.8, 128.8, 128.8, 136.0, 150.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("29.5, 29.5, 29.5, 34.1, 42.5", \ + "39.0, 39.0, 39.0, 43.6, 52.3", \ + "56.4, 56.4, 56.4, 61.1, 70.2", \ + "90.4, 90.4, 90.4, 95.1, 104.3", \ + "157.3, 157.3, 157.3, 162.3, 171.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("446.7, 446.7, 446.7, 484.2, 559.1", \ + "485.5, 485.5, 485.5, 522.9, 597.9", \ + "564.0, 564.0, 564.0, 601.5, 676.4", \ + "720.7, 720.7, 720.7, 758.2, 833.1", \ + "1032.0, 1032.0, 1032.0, 1069.4, 1144.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("467.3, 467.3, 467.3, 504.8, 579.7", \ + "595.9, 595.9, 595.9, 633.4, 708.3", \ + "847.5, 847.5, 847.5, 884.9, 959.9", \ + "1346.0, 1346.0, 1346.0, 1383.4, 1458.4", \ + "2340.0, 2340.0, 2340.0, 2377.5, 2452.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("398.3, 398.3, 398.3, 435.8, 510.7", \ + "442.9, 442.9, 442.9, 480.4, 555.3", \ + "531.9, 531.9, 531.9, 569.3, 644.3", \ + "707.5, 707.5, 707.5, 744.9, 819.9", \ + "1055.3, 1055.3, 1055.3, 1092.8, 1167.7"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("414.1, 414.1, 414.1, 451.6, 526.5", \ + "522.3, 522.3, 522.3, 559.8, 634.7", \ + "732.6, 732.6, 732.6, 770.1, 845.0", \ + "1149.0, 1149.0, 1149.0, 1186.5, 1261.4", \ + "1979.2, 1979.2, 1979.2, 2016.6, 2091.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("348.4, 348.4, 348.4, 385.9, 460.8", \ + "400.5, 400.5, 400.5, 438.0, 512.9", \ + "503.7, 503.7, 503.7, 541.2, 616.1", \ + "706.4, 706.4, 706.4, 743.9, 818.8", \ + "1109.1, 1109.1, 1109.1, 1146.6, 1221.5"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("357.7, 357.7, 357.7, 395.1, 470.1", \ + "446.1, 446.1, 446.1, 483.5, 558.5", \ + "617.5, 617.5, 617.5, 654.9, 729.9", \ + "956.7, 956.7, 956.7, 994.2, 1069.1", \ + "1632.6, 1632.6, 1632.6, 1670.0, 1745.0"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("294.7, 294.7, 294.7, 332.2, 407.1", \ + "352.3, 352.3, 352.3, 389.7, 464.7", \ + "462.0, 462.0, 462.0, 499.5, 574.4", \ + "677.8, 677.8, 677.8, 715.3, 790.2", \ + "1106.4, 1106.4, 1106.4, 1143.8, 1218.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("301.0, 301.0, 301.0, 338.5, 413.4", \ + "377.2, 377.2, 377.2, 414.7, 489.6", \ + "524.7, 524.7, 524.7, 562.1, 637.1", \ + "816.5, 816.5, 816.5, 853.9, 928.9", \ + "1397.8, 1397.8, 1397.8, 1435.2, 1510.2"); + } + } + } + } + + cell (a4_x4) { + area : 0.0 ; + cell_leakage_power : 2.1 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 1 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2) | !(i3))" ; + value : 3.2 ; + } + pin (i3) { + direction : input ; + capacitance : 4.39 ; + } + pin (i2) { + direction : input ; + capacitance : 4.34 ; + } + pin (i1) { + direction : input ; + capacitance : 4.28 ; + } + pin (i0) { + direction : input ; + capacitance : 4.34 ; + } + pin (q) { + function : "(i1 & i3 & i2 & i0)" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("82.5, 82.5, 82.5, 88.5, 99.9", \ + "76.8, 76.8, 76.8, 82.9, 94.3", \ + "63.0, 63.0, 63.0, 69.2, 80.7", \ + "29.7, 29.7, 29.7, 35.9, 47.8", \ + "-46.5, -46.5, -46.5, -40.2, -27.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("75.6, 75.6, 75.6, 83.4, 98.6", \ + "81.7, 81.7, 81.7, 89.5, 104.7", \ + "94.6, 94.6, 94.6, 102.4, 117.7", \ + "120.4, 120.4, 120.4, 128.2, 143.5", \ + "170.9, 170.9, 170.9, 178.6, 194.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("95.1, 95.1, 95.1, 101.0, 111.4", \ + "117.9, 117.9, 117.9, 123.9, 134.9", \ + "156.0, 156.0, 156.0, 162.1, 173.7", \ + "225.5, 225.5, 225.5, 231.1, 242.8", \ + "359.1, 359.1, 359.1, 364.8, 375.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("54.1, 54.1, 54.1, 57.8, 64.9", \ + "69.4, 69.4, 69.4, 73.0, 80.2", \ + "98.3, 98.3, 98.3, 102.0, 109.2", \ + "154.4, 154.4, 154.4, 158.3, 165.6", \ + "265.3, 265.3, 265.3, 269.1, 276.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("79.6, 79.6, 79.6, 85.5, 96.9", \ + "78.8, 78.8, 78.8, 84.8, 96.2", \ + "72.3, 72.3, 72.3, 78.5, 90.0", \ + "51.2, 51.2, 51.2, 57.4, 69.3", \ + "-0.8, -0.8, -0.8, 5.5, 17.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("69.5, 69.5, 69.5, 77.3, 92.4", \ + "77.3, 77.3, 77.3, 85.1, 100.3", \ + "92.6, 92.6, 92.6, 100.3, 115.6", \ + "122.4, 122.4, 122.4, 130.1, 145.5", \ + "180.3, 180.3, 180.3, 188.0, 203.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("87.6, 87.6, 87.6, 93.4, 103.6", \ + "106.3, 106.3, 106.3, 112.2, 123.0", \ + "135.9, 135.9, 135.9, 141.9, 153.3", \ + "187.6, 187.6, 187.6, 193.4, 205.1", \ + "285.5, 285.5, 285.5, 291.2, 302.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("49.4, 49.4, 49.4, 53.1, 60.3", \ + "62.6, 62.6, 62.6, 66.2, 73.4", \ + "87.3, 87.3, 87.3, 91.0, 98.3", \ + "135.3, 135.3, 135.3, 139.1, 146.4", \ + "230.0, 230.0, 230.0, 233.9, 241.6"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("75.5, 75.5, 75.5, 81.4, 92.6", \ + "79.0, 79.0, 79.0, 85.0, 96.3", \ + "79.7, 79.7, 79.7, 85.9, 97.4", \ + "72.2, 72.2, 72.2, 78.5, 90.4", \ + "47.8, 47.8, 47.8, 54.2, 66.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("63.3, 63.3, 63.3, 71.0, 86.1", \ + "72.6, 72.6, 72.6, 80.3, 95.5", \ + "90.8, 90.8, 90.8, 98.6, 113.9", \ + "125.6, 125.6, 125.6, 133.4, 148.8", \ + "193.4, 193.4, 193.4, 201.1, 216.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("79.5, 79.5, 79.5, 85.2, 95.2", \ + "93.9, 93.9, 93.9, 99.8, 110.3", \ + "114.8, 114.8, 114.8, 120.7, 131.9", \ + "148.6, 148.6, 148.6, 154.5, 166.3", \ + "210.3, 210.3, 210.3, 215.9, 227.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("44.4, 44.4, 44.4, 48.1, 55.2", \ + "55.4, 55.4, 55.4, 59.1, 66.3", \ + "76.2, 76.2, 76.2, 79.9, 87.1", \ + "116.6, 116.6, 116.6, 120.2, 127.5", \ + "195.8, 195.8, 195.8, 199.7, 207.3"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("68.9, 68.9, 68.9, 74.9, 85.9", \ + "76.3, 76.3, 76.3, 82.2, 93.5", \ + "82.2, 82.2, 82.2, 88.3, 99.8", \ + "84.2, 84.2, 84.2, 90.5, 102.4", \ + "79.4, 79.4, 79.4, 85.8, 98.1"); + } + rise_transition (inslew_load_5x5__1) { + values ("56.0, 56.0, 56.0, 63.7, 78.8", \ + "67.1, 67.1, 67.1, 74.8, 89.9", \ + "87.0, 87.0, 87.0, 94.7, 110.0", \ + "124.7, 124.7, 124.7, 132.5, 147.9", \ + "198.3, 198.3, 198.3, 206.0, 221.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("70.8, 70.8, 70.8, 76.3, 86.4", \ + "82.1, 82.1, 82.1, 87.9, 98.1", \ + "96.8, 96.8, 96.8, 102.8, 113.7", \ + "118.5, 118.5, 118.5, 124.5, 136.2", \ + "156.0, 156.0, 156.0, 161.6, 173.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("39.0, 39.0, 39.0, 42.6, 49.6", \ + "48.9, 48.9, 48.9, 52.6, 59.8", \ + "67.2, 67.2, 67.2, 70.9, 78.1", \ + "102.8, 102.8, 102.8, 106.4, 113.7", \ + "172.4, 172.4, 172.4, 176.3, 183.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("749.3, 749.3, 749.3, 808.9, 928.1", \ + "804.1, 804.1, 804.1, 863.7, 982.8", \ + "917.3, 917.3, 917.3, 976.9, 1096.1", \ + "1144.8, 1144.8, 1144.8, 1204.4, 1323.6", \ + "1594.5, 1594.5, 1594.5, 1654.1, 1773.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("767.8, 767.8, 767.8, 827.3, 946.5", \ + "950.4, 950.4, 950.4, 1010.0, 1129.2", \ + "1304.0, 1304.0, 1304.0, 1363.6, 1482.8", \ + "2001.7, 2001.7, 2001.7, 2061.3, 2180.5", \ + "3390.0, 3390.0, 3390.0, 3449.6, 3568.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("684.3, 684.3, 684.3, 743.9, 863.1", \ + "750.1, 750.1, 750.1, 809.7, 928.9", \ + "880.3, 880.3, 880.3, 939.9, 1059.1", \ + "1137.9, 1137.9, 1137.9, 1197.5, 1316.7", \ + "1644.8, 1644.8, 1644.8, 1704.4, 1823.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("698.9, 698.9, 698.9, 758.5, 877.7", \ + "853.0, 853.0, 853.0, 912.6, 1031.8", \ + "1151.0, 1151.0, 1151.0, 1210.6, 1329.8", \ + "1737.5, 1737.5, 1737.5, 1797.1, 1916.3", \ + "2904.3, 2904.3, 2904.3, 2963.9, 3083.1"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("617.6, 617.6, 617.6, 677.2, 796.3", \ + "695.2, 695.2, 695.2, 754.8, 874.0", \ + "848.3, 848.3, 848.3, 907.9, 1027.1", \ + "1146.9, 1146.9, 1146.9, 1206.5, 1325.7", \ + "1735.5, 1735.5, 1735.5, 1795.1, 1914.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("624.8, 624.8, 624.8, 684.4, 803.6", \ + "751.8, 751.8, 751.8, 811.4, 930.6", \ + "997.2, 997.2, 997.2, 1056.8, 1175.9", \ + "1479.2, 1479.2, 1479.2, 1538.7, 1657.9", \ + "2436.6, 2436.6, 2436.6, 2496.2, 2615.4"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("545.0, 545.0, 545.0, 604.6, 723.8", \ + "632.5, 632.5, 632.5, 692.1, 811.3", \ + "797.2, 797.2, 797.2, 856.8, 976.0", \ + "1116.9, 1116.9, 1116.9, 1176.5, 1295.7", \ + "1747.7, 1747.7, 1747.7, 1807.3, 1926.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("548.6, 548.6, 548.6, 608.2, 727.4", \ + "660.2, 660.2, 660.2, 719.8, 838.9", \ + "873.0, 873.0, 873.0, 932.6, 1051.8", \ + "1290.5, 1290.5, 1290.5, 1350.1, 1469.3", \ + "2119.6, 2119.6, 2119.6, 2179.2, 2298.4"); + } + } + } + } + + cell (an12_x1) { + area : 0.0 ; + cell_leakage_power : 1.7 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 2.8 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 2.6 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 0.26 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.98 ; + } + pin (i1) { + direction : input ; + capacitance : 3.61 ; + } + pin (i0) { + direction : input ; + capacitance : 5.02 ; + } + pin (q) { + function : "(i1 & !(i0))" ; + direction : output ; + capacitance : 3.24 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("57.0, 57.0, 57.0, 67.7, 88.9", \ + "56.4, 56.4, 56.4, 67.4, 88.8", \ + "50.8, 50.8, 50.8, 62.0, 84.0", \ + "35.7, 35.7, 35.7, 47.4, 69.9", \ + "2.7, 2.7, 2.7, 14.8, 38.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("66.0, 66.0, 66.0, 84.6, 122.5", \ + "73.8, 73.8, 73.8, 92.4, 129.9", \ + "87.7, 87.7, 87.7, 106.1, 143.4", \ + "113.7, 113.7, 113.7, 132.6, 169.3", \ + "165.4, 165.4, 165.4, 183.9, 220.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("68.8, 68.8, 68.8, 77.9, 94.2", \ + "83.6, 83.6, 83.6, 93.2, 110.6", \ + "108.1, 108.1, 108.1, 118.3, 136.9", \ + "152.7, 152.7, 152.7, 163.3, 183.5", \ + "238.8, 238.8, 238.8, 250.0, 271.2"); + } + fall_transition (inslew_load_5x5__3) { + values ("40.3, 40.3, 40.3, 48.1, 63.2", \ + "54.5, 54.5, 54.5, 62.4, 77.6", \ + "80.9, 80.9, 80.9, 88.9, 104.5", \ + "132.4, 132.4, 132.4, 140.6, 156.4", \ + "234.2, 234.2, 234.2, 242.3, 258.5"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("20.9, 20.9, 20.9, 33.6, 57.1", \ + "25.6, 25.6, 25.6, 39.5, 64.7", \ + "32.7, 32.7, 32.7, 47.5, 75.0", \ + "45.4, 45.4, 45.4, 60.8, 90.3", \ + "70.0, 70.0, 70.0, 85.8, 116.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("47.1, 47.1, 47.1, 65.9, 104.2", \ + "78.1, 78.1, 78.1, 97.5, 135.4", \ + "137.6, 137.6, 137.6, 157.2, 195.8", \ + "254.9, 254.9, 254.9, 274.7, 314.0", \ + "488.6, 488.6, 488.6, 508.6, 548.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("14.8, 14.8, 14.8, 25.1, 42.0", \ + "15.6, 15.6, 15.6, 27.3, 47.2", \ + "15.1, 15.1, 15.1, 28.1, 51.1", \ + "12.8, 12.8, 12.8, 26.7, 52.3", \ + "7.4, 7.4, 7.4, 21.8, 49.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("20.8, 20.8, 20.8, 29.1, 44.5", \ + "36.7, 36.7, 36.7, 45.5, 61.8", \ + "67.2, 67.2, 67.2, 76.4, 93.8", \ + "127.3, 127.3, 127.3, 136.9, 155.3", \ + "247.0, 247.0, 247.0, 256.8, 275.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("241.0, 241.0, 241.0, 281.5, 362.5", \ + "280.4, 280.4, 280.4, 320.9, 402.0", \ + "357.9, 357.9, 357.9, 398.5, 479.5", \ + "511.7, 511.7, 511.7, 552.2, 633.3", \ + "818.5, 818.5, 818.5, 859.0, 940.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("282.2, 282.2, 282.2, 322.7, 403.8", \ + "360.8, 360.8, 360.8, 401.3, 482.4", \ + "515.1, 515.1, 515.1, 555.6, 636.7", \ + "821.7, 821.7, 821.7, 862.3, 943.3", \ + "1433.7, 1433.7, 1433.7, 1474.3, 1555.3"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("84.8, 84.8, 84.8, 125.4, 206.4", \ + "130.0, 130.0, 130.0, 170.5, 251.6", \ + "220.2, 220.2, 220.2, 260.7, 341.8", \ + "400.7, 400.7, 400.7, 441.2, 522.3", \ + "761.7, 761.7, 761.7, 802.3, 883.3"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("76.3, 76.3, 76.3, 116.8, 197.8", \ + "111.2, 111.2, 111.2, 151.7, 232.7", \ + "180.9, 180.9, 180.9, 221.5, 302.5", \ + "320.5, 320.5, 320.5, 361.1, 442.1", \ + "599.7, 599.7, 599.7, 640.2, 721.3"); + } + } + } + } + + cell (an12_x4) { + area : 0.0 ; + cell_leakage_power : 2.9 ; + leakage_power () { + when : "i0" ; + value : 4.9 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 0.52 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 3.2 ; + } + pin (i1) { + direction : input ; + capacitance : 4.36 ; + } + pin (i0) { + direction : input ; + capacitance : 3.09 ; + } + pin (q) { + function : "(i1 & !(i0))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("43.4, 43.4, 43.4, 49.2, 59.4", \ + "39.3, 39.3, 39.3, 45.1, 55.6", \ + "24.9, 24.9, 24.9, 30.9, 41.8", \ + "-11.8, -11.8, -11.8, -5.8, 5.6", \ + "-94.2, -94.2, -94.2, -87.9, -76.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("34.9, 34.9, 34.9, 42.6, 57.5", \ + "41.7, 41.7, 41.7, 49.4, 64.3", \ + "54.0, 54.0, 54.0, 61.6, 76.7", \ + "76.4, 76.4, 76.4, 84.1, 99.3", \ + "118.9, 118.9, 118.9, 126.6, 141.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("78.8, 78.8, 78.8, 84.5, 94.5", \ + "100.7, 100.7, 100.7, 106.6, 117.1", \ + "137.7, 137.7, 137.7, 143.7, 155.1", \ + "206.7, 206.7, 206.7, 212.2, 224.0", \ + "341.3, 341.3, 341.3, 346.8, 357.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("44.3, 44.3, 44.3, 47.9, 55.0", \ + "60.0, 60.0, 60.0, 63.7, 70.7", \ + "89.5, 89.5, 89.5, 93.1, 100.2", \ + "146.7, 146.7, 146.7, 150.5, 157.7", \ + "260.0, 260.0, 260.0, 263.8, 271.4"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("84.6, 84.6, 84.6, 90.3, 100.7", \ + "93.2, 93.2, 93.2, 99.1, 109.6", \ + "103.9, 103.9, 103.9, 109.9, 120.8", \ + "118.3, 118.3, 118.3, 124.3, 135.7", \ + "141.2, 141.2, 141.2, 147.4, 159.1"); + } + rise_transition (inslew_load_5x5__1) { + values ("37.7, 37.7, 37.7, 45.4, 60.3", \ + "43.6, 43.6, 43.6, 51.3, 66.2", \ + "54.2, 54.2, 54.2, 61.9, 76.9", \ + "74.0, 74.0, 74.0, 81.7, 96.9", \ + "111.7, 111.7, 111.7, 119.5, 134.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("87.1, 87.1, 87.1, 92.4, 102.3", \ + "94.2, 94.2, 94.2, 99.7, 109.7", \ + "100.9, 100.9, 100.9, 106.6, 116.6", \ + "106.3, 106.3, 106.3, 112.3, 122.9", \ + "110.0, 110.0, 110.0, 116.0, 127.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("33.5, 33.5, 33.5, 37.2, 43.9", \ + "38.3, 38.3, 38.3, 41.9, 48.8", \ + "46.5, 46.5, 46.5, 50.1, 57.3", \ + "61.5, 61.5, 61.5, 65.1, 72.1", \ + "90.0, 90.0, 90.0, 93.6, 100.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("441.8, 441.8, 441.8, 501.4, 620.6", \ + "497.6, 497.6, 497.6, 557.2, 676.3", \ + "604.5, 604.5, 604.5, 664.1, 783.3", \ + "810.5, 810.5, 810.5, 870.1, 989.3", \ + "1213.1, 1213.1, 1213.1, 1272.7, 1391.9"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("621.2, 621.2, 621.2, 680.8, 800.0", \ + "804.5, 804.5, 804.5, 864.1, 983.3", \ + "1157.5, 1157.5, 1157.5, 1217.1, 1336.3", \ + "1854.0, 1854.0, 1854.0, 1913.6, 2032.8", \ + "3241.9, 3241.9, 3241.9, 3301.5, 3420.7"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("541.9, 541.9, 541.9, 601.5, 720.7", \ + "626.2, 626.2, 626.2, 685.8, 805.0", \ + "788.7, 788.7, 788.7, 848.3, 967.5", \ + "1108.3, 1108.3, 1108.3, 1167.9, 1287.1", \ + "1739.7, 1739.7, 1739.7, 1799.3, 1918.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("581.9, 581.9, 581.9, 641.5, 760.7", \ + "658.2, 658.2, 658.2, 717.8, 837.0", \ + "799.5, 799.5, 799.5, 859.1, 978.3", \ + "1070.2, 1070.2, 1070.2, 1129.8, 1249.0", \ + "1600.5, 1600.5, 1600.5, 1660.1, 1779.3"); + } + } + } + } + + cell (ao22_x2) { + area : 0.0 ; + cell_leakage_power : 1.2 ; + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 0.4 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 0.52 ; + } + leakage_power () { + when : "(!((i0 | i1)) | !(i2))" ; + value : 2.6 ; + } + pin (i2) { + direction : input ; + capacitance : 3.79 ; + } + pin (i1) { + direction : input ; + capacitance : 3.50 ; + } + pin (i0) { + direction : input ; + capacitance : 3.62 ; + } + pin (q) { + function : "((i0 | i1) & i2)" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("62.5, 62.5, 62.5, 69.6, 82.4", \ + "72.3, 72.3, 72.3, 79.6, 92.8", \ + "84.4, 84.4, 84.4, 91.8, 105.8", \ + "101.4, 101.4, 101.4, 109.2, 123.7", \ + "129.6, 129.6, 129.6, 137.5, 152.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("43.2, 43.2, 43.2, 52.8, 71.5", \ + "55.9, 55.9, 55.9, 65.5, 84.3", \ + "78.8, 78.8, 78.8, 88.5, 107.5", \ + "122.4, 122.4, 122.4, 132.2, 151.5", \ + "208.0, 208.0, 208.0, 217.7, 237.1"); + } + cell_fall (inslew_load_5x5__0) { + values ("86.7, 86.7, 86.7, 93.9, 106.4", \ + "91.1, 91.1, 91.1, 98.4, 111.4", \ + "97.2, 97.2, 97.2, 104.6, 118.4", \ + "107.3, 107.3, 107.3, 114.8, 129.3", \ + "125.7, 125.7, 125.7, 132.8, 147.1"); + } + fall_transition (inslew_load_5x5__0) { + values ("53.3, 53.3, 53.3, 57.9, 66.9", \ + "63.8, 63.8, 63.8, 68.5, 77.5", \ + "84.5, 84.5, 84.5, 89.2, 98.3", \ + "125.7, 125.7, 125.7, 130.3, 139.6", \ + "207.8, 207.8, 207.8, 212.7, 222.3"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("54.4, 54.4, 54.4, 61.4, 73.8", \ + "57.4, 57.4, 57.4, 64.6, 77.5", \ + "55.0, 55.0, 55.0, 62.4, 75.9", \ + "41.2, 41.2, 41.2, 48.8, 63.0", \ + "5.3, 5.3, 5.3, 13.2, 28.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("38.0, 38.0, 38.0, 47.6, 66.2", \ + "47.5, 47.5, 47.5, 57.1, 75.9", \ + "64.0, 64.0, 64.0, 73.7, 92.6", \ + "94.3, 94.3, 94.3, 104.1, 123.2", \ + "152.6, 152.6, 152.6, 162.3, 181.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("77.3, 77.3, 77.3, 84.2, 96.5", \ + "91.2, 91.2, 91.2, 98.4, 111.0", \ + "113.0, 113.0, 113.0, 120.4, 134.0", \ + "150.9, 150.9, 150.9, 158.4, 173.0", \ + "223.4, 223.4, 223.4, 230.5, 244.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("43.2, 43.2, 43.2, 47.8, 56.5", \ + "55.8, 55.8, 55.8, 60.4, 69.4", \ + "79.5, 79.5, 79.5, 84.2, 93.3", \ + "126.0, 126.0, 126.0, 130.7, 139.9", \ + "217.4, 217.4, 217.4, 222.3, 232.0"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("59.9, 59.9, 59.9, 67.0, 79.8", \ + "63.6, 63.6, 63.6, 70.9, 84.1", \ + "66.0, 66.0, 66.0, 73.5, 87.3", \ + "64.9, 64.9, 64.9, 72.7, 87.0", \ + "57.2, 57.2, 57.2, 65.1, 80.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("45.1, 45.1, 45.1, 54.7, 73.4", \ + "55.1, 55.1, 55.1, 64.7, 83.5", \ + "74.1, 74.1, 74.1, 83.8, 102.8", \ + "110.7, 110.7, 110.7, 120.5, 139.7", \ + "182.6, 182.6, 182.6, 192.3, 211.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("57.1, 57.1, 57.1, 63.8, 75.3", \ + "66.5, 66.5, 66.5, 73.2, 85.5", \ + "79.3, 79.3, 79.3, 86.5, 99.3", \ + "99.6, 99.6, 99.6, 107.0, 121.1", \ + "136.7, 136.7, 136.7, 143.8, 158.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("31.8, 31.8, 31.8, 36.3, 44.8", \ + "41.3, 41.3, 41.3, 45.9, 54.5", \ + "59.2, 59.2, 59.2, 63.8, 72.8", \ + "94.2, 94.2, 94.2, 98.8, 108.0", \ + "163.5, 163.5, 163.5, 168.4, 177.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("281.9, 281.9, 281.9, 319.3, 394.3", \ + "344.2, 344.2, 344.2, 381.7, 456.6", \ + "464.3, 464.3, 464.3, 501.8, 576.7", \ + "700.4, 700.4, 700.4, 737.9, 812.8", \ + "1169.3, 1169.3, 1169.3, 1206.7, 1281.7"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("390.6, 390.6, 390.6, 428.1, 503.0", \ + "460.4, 460.4, 460.4, 497.8, 572.8", \ + "599.0, 599.0, 599.0, 636.4, 711.4", \ + "875.0, 875.0, 875.0, 912.4, 987.4", \ + "1428.4, 1428.4, 1428.4, 1465.8, 1540.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("240.8, 240.8, 240.8, 278.3, 353.2", \ + "280.9, 280.9, 280.9, 318.4, 393.3", \ + "356.3, 356.3, 356.3, 393.8, 468.7", \ + "501.8, 501.8, 501.8, 539.2, 614.2", \ + "787.9, 787.9, 787.9, 825.3, 900.3"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("318.4, 318.4, 318.4, 355.9, 430.8", \ + "395.1, 395.1, 395.1, 432.6, 507.5", \ + "543.9, 543.9, 543.9, 581.3, 656.3", \ + "837.5, 837.5, 837.5, 875.0, 949.9", \ + "1421.8, 1421.8, 1421.8, 1459.3, 1534.2"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("302.7, 302.7, 302.7, 340.1, 415.1", \ + "356.1, 356.1, 356.1, 393.5, 468.5", \ + "461.4, 461.4, 461.4, 498.9, 573.8", \ + "670.0, 670.0, 670.0, 707.4, 782.4", \ + "1084.8, 1084.8, 1084.8, 1122.3, 1197.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("315.3, 315.3, 315.3, 352.8, 427.7", \ + "391.6, 391.6, 391.6, 429.1, 504.0", \ + "540.9, 540.9, 540.9, 578.3, 653.3", \ + "836.8, 836.8, 836.8, 874.3, 949.2", \ + "1427.1, 1427.1, 1427.1, 1464.6, 1539.5"); + } + } + } + } + + cell (ao22_x4) { + area : 0.0 ; + cell_leakage_power : 3.7 ; + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 0.4 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 0.52 ; + } + leakage_power () { + when : "(!((i0 | i1)) | !(i2))" ; + value : 10 ; + } + pin (i2) { + direction : input ; + capacitance : 3.91 ; + } + pin (i1) { + direction : input ; + capacitance : 3.50 ; + } + pin (i0) { + direction : input ; + capacitance : 3.62 ; + } + pin (q) { + function : "((i0 | i1) & i2)" ; + direction : output ; + capacitance : 5.75 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("79.1, 79.1, 79.1, 84.8, 94.9", \ + "89.6, 89.6, 89.6, 95.2, 105.7", \ + "101.6, 101.6, 101.6, 107.2, 118.0", \ + "114.2, 114.2, 114.2, 120.0, 130.9", \ + "128.1, 128.1, 128.1, 134.2, 145.7"); + } + rise_transition (inslew_load_5x5__4) { + values ("48.0, 48.0, 48.0, 54.4, 66.9", \ + "57.3, 57.3, 57.3, 63.7, 76.2", \ + "74.9, 74.9, 74.9, 81.4, 94.1", \ + "108.6, 108.6, 108.6, 115.0, 127.8", \ + "173.7, 173.7, 173.7, 180.3, 193.2"); + } + cell_fall (inslew_load_5x5__4) { + values ("171.4, 171.4, 171.4, 177.1, 188.5", \ + "181.3, 181.3, 181.3, 187.1, 198.3", \ + "198.7, 198.7, 198.7, 204.5, 215.5", \ + "229.9, 229.9, 229.9, 235.6, 247.0", \ + "288.2, 288.2, 288.2, 294.0, 305.5"); + } + fall_transition (inslew_load_5x5__4) { + values ("108.7, 108.7, 108.7, 112.8, 120.6", \ + "122.1, 122.1, 122.1, 126.3, 134.2", \ + "148.7, 148.7, 148.7, 152.9, 161.1", \ + "203.3, 203.3, 203.3, 207.5, 215.9", \ + "311.9, 311.9, 311.9, 316.0, 324.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("73.0, 73.0, 73.0, 78.6, 88.4", \ + "78.4, 78.4, 78.4, 84.1, 94.3", \ + "79.1, 79.1, 79.1, 84.6, 95.3", \ + "66.2, 66.2, 66.2, 71.8, 82.6", \ + "24.5, 24.5, 24.5, 30.5, 41.6"); + } + rise_transition (inslew_load_5x5__4) { + values ("44.2, 44.2, 44.2, 50.5, 63.0", \ + "51.4, 51.4, 51.4, 57.8, 70.3", \ + "64.5, 64.5, 64.5, 71.0, 83.5", \ + "88.5, 88.5, 88.5, 94.9, 107.8", \ + "133.6, 133.6, 133.6, 140.1, 152.9"); + } + cell_fall (inslew_load_5x5__4) { + values ("158.9, 158.9, 158.9, 164.7, 176.0", \ + "180.6, 180.6, 180.6, 186.3, 197.6", \ + "217.1, 217.1, 217.1, 222.8, 233.9", \ + "281.2, 281.2, 281.2, 287.0, 298.4", \ + "399.7, 399.7, 399.7, 405.6, 417.1"); + } + fall_transition (inslew_load_5x5__4) { + values ("96.2, 96.2, 96.2, 100.2, 108.0", \ + "112.1, 112.1, 112.1, 116.3, 124.1", \ + "143.1, 143.1, 143.1, 147.4, 155.5", \ + "204.8, 204.8, 204.8, 209.0, 217.4", \ + "327.0, 327.0, 327.0, 331.1, 339.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("74.4, 74.4, 74.4, 80.1, 90.2", \ + "78.2, 78.2, 78.2, 83.8, 94.2", \ + "80.0, 80.0, 80.0, 85.6, 96.4", \ + "75.1, 75.1, 75.1, 80.8, 91.7", \ + "55.5, 55.5, 55.5, 61.6, 72.9"); + } + rise_transition (inslew_load_5x5__4) { + values ("49.2, 49.2, 49.2, 55.5, 68.0", \ + "56.3, 56.3, 56.3, 62.7, 75.2", \ + "70.6, 70.6, 70.6, 77.1, 89.7", \ + "98.7, 98.7, 98.7, 105.1, 118.0", \ + "153.4, 153.4, 153.4, 159.9, 172.7"); + } + cell_fall (inslew_load_5x5__4) { + values ("101.9, 101.9, 101.9, 107.7, 118.4", \ + "118.5, 118.5, 118.5, 124.4, 135.4", \ + "143.7, 143.7, 143.7, 149.5, 160.8", \ + "184.4, 184.4, 184.4, 190.2, 201.2", \ + "256.8, 256.8, 256.8, 262.6, 274.0"); + } + fall_transition (inslew_load_5x5__4) { + values ("60.6, 60.6, 60.6, 64.6, 72.5", \ + "73.4, 73.4, 73.4, 77.3, 85.2", \ + "97.7, 97.7, 97.7, 101.7, 109.5", \ + "144.5, 144.5, 144.5, 148.7, 156.8", \ + "236.8, 236.8, 236.8, 241.0, 249.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__4) { + values ("608.9, 608.9, 608.9, 680.8, 824.7", \ + "703.4, 703.4, 703.4, 775.3, 919.2", \ + "887.0, 887.0, 887.0, 958.9, 1102.7", \ + "1242.5, 1242.5, 1242.5, 1314.4, 1458.3", \ + "1941.0, 1941.0, 1941.0, 2013.0, 2156.8"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("1302.9, 1302.9, 1302.9, 1374.9, 1518.7", \ + "1455.1, 1455.1, 1455.1, 1527.0, 1670.8", \ + "1757.5, 1757.5, 1757.5, 1829.4, 1973.2", \ + "2374.1, 2374.1, 2374.1, 2446.0, 2589.9", \ + "3602.6, 3602.6, 3602.6, 3674.5, 3818.3"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__4) { + values ("554.6, 554.6, 554.6, 626.5, 770.3", \ + "620.7, 620.7, 620.7, 692.6, 836.4", \ + "744.8, 744.8, 744.8, 816.7, 960.5", \ + "977.9, 977.9, 977.9, 1049.9, 1193.7", \ + "1425.6, 1425.6, 1425.6, 1497.6, 1641.4"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("1155.3, 1155.3, 1155.3, 1227.2, 1371.0", \ + "1329.2, 1329.2, 1329.2, 1401.1, 1545.0", \ + "1670.4, 1670.4, 1670.4, 1742.4, 1886.2", \ + "2349.2, 2349.2, 2349.2, 2421.1, 2565.0", \ + "3695.6, 3695.6, 3695.6, 3767.5, 3911.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__4) { + values ("633.0, 633.0, 633.0, 704.9, 848.8", \ + "710.2, 710.2, 710.2, 782.1, 925.9", \ + "866.2, 866.2, 866.2, 938.1, 1081.9", \ + "1173.8, 1173.8, 1173.8, 1245.7, 1389.6", \ + "1781.2, 1781.2, 1781.2, 1853.1, 1997.0"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("879.3, 879.3, 879.3, 951.2, 1095.1", \ + "1033.4, 1033.4, 1033.4, 1105.3, 1249.2", \ + "1333.9, 1333.9, 1333.9, 1405.8, 1549.6", \ + "1922.6, 1922.6, 1922.6, 1994.5, 2138.4", \ + "3089.4, 3089.4, 3089.4, 3161.3, 3305.2"); + } + } + } + } + + cell (ao2o22_x2) { + area : 0.0 ; + cell_leakage_power : 0.94 ; + leakage_power () { + when : "(i3 & !(i2) & !(i1) & i0)" ; + value : 0.27 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 0.52 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & i3) | (!(i1) & i2))) | (i1 & !(i2) & i3))" ; + value : 0.4 ; + } + leakage_power () { + when : "(!((i0 | i1)) | (!(i2) & !(i3)))" ; + value : 2.6 ; + } + pin (i3) { + direction : input ; + capacitance : 3.36 ; + } + pin (i2) { + direction : input ; + capacitance : 3.42 ; + } + pin (i1) { + direction : input ; + capacitance : 3.52 ; + } + pin (i0) { + direction : input ; + capacitance : 3.57 ; + } + pin (q) { + function : "((i3 | i2) & (i0 | i1))" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("65.6, 65.6, 65.6, 72.7, 85.5", \ + "75.7, 75.7, 75.7, 83.1, 96.4", \ + "88.5, 88.5, 88.5, 96.0, 110.0", \ + "105.8, 105.8, 105.8, 113.6, 128.2", \ + "134.1, 134.1, 134.1, 142.0, 157.4"); + } + rise_transition (inslew_load_5x5__0) { + values ("45.3, 45.3, 45.3, 55.0, 73.7", \ + "57.9, 57.9, 57.9, 67.5, 86.4", \ + "80.8, 80.8, 80.8, 90.5, 109.6", \ + "124.3, 124.3, 124.3, 134.1, 153.4", \ + "209.6, 209.6, 209.6, 219.3, 238.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("91.3, 91.3, 91.3, 98.5, 111.2", \ + "95.6, 95.6, 95.6, 103.0, 116.1", \ + "101.8, 101.8, 101.8, 109.2, 123.1", \ + "111.6, 111.6, 111.6, 119.2, 133.6", \ + "129.5, 129.5, 129.5, 136.7, 151.1"); + } + fall_transition (inslew_load_5x5__0) { + values ("55.6, 55.6, 55.6, 60.3, 69.4", \ + "66.0, 66.0, 66.0, 70.7, 79.8", \ + "86.4, 86.4, 86.4, 91.1, 100.3", \ + "127.6, 127.6, 127.6, 132.4, 141.7", \ + "208.0, 208.0, 208.0, 212.9, 222.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("57.6, 57.6, 57.6, 64.7, 77.2", \ + "61.3, 61.3, 61.3, 68.5, 81.5", \ + "59.8, 59.8, 59.8, 67.2, 80.8", \ + "46.7, 46.7, 46.7, 54.3, 68.6", \ + "11.3, 11.3, 11.3, 19.1, 34.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("40.3, 40.3, 40.3, 49.8, 68.5", \ + "49.6, 49.6, 49.6, 59.3, 78.1", \ + "66.2, 66.2, 66.2, 75.9, 94.8", \ + "96.6, 96.6, 96.6, 106.3, 125.5", \ + "154.8, 154.8, 154.8, 164.5, 183.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("82.3, 82.3, 82.3, 89.2, 101.6", \ + "96.3, 96.3, 96.3, 103.6, 116.4", \ + "118.2, 118.2, 118.2, 125.6, 139.3", \ + "156.2, 156.2, 156.2, 163.8, 178.3", \ + "228.1, 228.1, 228.1, 235.3, 249.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("45.8, 45.8, 45.8, 50.4, 59.2", \ + "58.1, 58.1, 58.1, 62.8, 71.9", \ + "81.6, 81.6, 81.6, 86.2, 95.4", \ + "127.4, 127.4, 127.4, 132.2, 141.5", \ + "217.8, 217.8, 217.8, 222.7, 232.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("64.6, 64.6, 64.6, 71.8, 84.7", \ + "64.2, 64.2, 64.2, 71.6, 84.8", \ + "57.0, 57.0, 57.0, 64.4, 78.1", \ + "32.4, 32.4, 32.4, 40.0, 54.2", \ + "-27.8, -27.8, -27.8, -20.0, -5.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("48.3, 48.3, 48.3, 57.9, 76.7", \ + "55.4, 55.4, 55.4, 65.0, 83.8", \ + "68.9, 68.9, 68.9, 78.5, 97.5", \ + "93.9, 93.9, 93.9, 103.7, 122.8", \ + "141.6, 141.6, 141.6, 151.4, 170.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("102.8, 102.8, 102.8, 110.0, 122.8", \ + "122.0, 122.0, 122.0, 129.4, 142.9", \ + "154.3, 154.3, 154.3, 161.8, 176.0", \ + "212.9, 212.9, 212.9, 220.1, 234.8", \ + "325.1, 325.1, 325.1, 332.4, 346.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("57.9, 57.9, 57.9, 62.6, 71.7", \ + "72.7, 72.7, 72.7, 77.4, 86.5", \ + "100.5, 100.5, 100.5, 105.2, 114.5", \ + "155.2, 155.2, 155.2, 160.1, 169.4", \ + "263.5, 263.5, 263.5, 268.4, 278.3"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("72.0, 72.0, 72.0, 79.3, 92.4", \ + "76.6, 76.6, 76.6, 84.0, 97.5", \ + "80.5, 80.5, 80.5, 87.9, 102.0", \ + "80.9, 80.9, 80.9, 88.7, 103.2", \ + "74.3, 74.3, 74.3, 82.2, 97.5"); + } + rise_transition (inslew_load_5x5__0) { + values ("53.3, 53.3, 53.3, 62.9, 81.8", \ + "63.1, 63.1, 63.1, 72.7, 91.6", \ + "82.1, 82.1, 82.1, 91.8, 110.8", \ + "118.7, 118.7, 118.7, 128.5, 147.7", \ + "190.5, 190.5, 190.5, 200.2, 219.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("112.7, 112.7, 112.7, 120.1, 133.4", \ + "122.6, 122.6, 122.6, 130.0, 143.7", \ + "139.4, 139.4, 139.4, 146.9, 161.3", \ + "171.6, 171.6, 171.6, 178.8, 193.5", \ + "233.7, 233.7, 233.7, 241.0, 255.1"); + } + fall_transition (inslew_load_5x5__0) { + values ("68.6, 68.6, 68.6, 73.3, 82.4", \ + "81.7, 81.7, 81.7, 86.4, 95.6", \ + "107.6, 107.6, 107.6, 112.3, 121.6", \ + "159.3, 159.3, 159.3, 164.2, 173.5", \ + "263.0, 263.0, 263.0, 267.9, 277.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("298.7, 298.7, 298.7, 336.2, 411.1", \ + "361.1, 361.1, 361.1, 398.5, 473.5", \ + "481.5, 481.5, 481.5, 519.0, 593.9", \ + "718.0, 718.0, 718.0, 755.4, 830.4", \ + "1187.0, 1187.0, 1187.0, 1224.4, 1299.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("412.4, 412.4, 412.4, 449.9, 524.8", \ + "482.1, 482.1, 482.1, 519.5, 594.5", \ + "620.4, 620.4, 620.4, 657.9, 732.8", \ + "898.8, 898.8, 898.8, 936.2, 1011.2", \ + "1449.7, 1449.7, 1449.7, 1487.2, 1562.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("257.7, 257.7, 257.7, 295.1, 370.1", \ + "298.0, 298.0, 298.0, 335.4, 410.4", \ + "373.8, 373.8, 373.8, 411.3, 486.2", \ + "519.8, 519.8, 519.8, 557.3, 632.2", \ + "806.5, 806.5, 806.5, 843.9, 918.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("340.3, 340.3, 340.3, 377.8, 452.7", \ + "417.0, 417.0, 417.0, 454.5, 529.4", \ + "565.6, 565.6, 565.6, 603.0, 678.0", \ + "859.4, 859.4, 859.4, 896.9, 971.8", \ + "1444.0, 1444.0, 1444.0, 1481.5, 1556.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("324.5, 324.5, 324.5, 361.9, 436.9", \ + "357.2, 357.2, 357.2, 394.7, 469.6", \ + "421.5, 421.5, 421.5, 459.0, 533.9", \ + "545.9, 545.9, 545.9, 583.4, 658.3", \ + "789.3, 789.3, 789.3, 826.7, 901.7"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("430.9, 430.9, 430.9, 468.3, 543.3", \ + "524.1, 524.1, 524.1, 561.5, 636.5", \ + "704.7, 704.7, 704.7, 742.1, 817.1", \ + "1063.4, 1063.4, 1063.4, 1100.8, 1175.8", \ + "1777.8, 1777.8, 1777.8, 1815.3, 1890.2"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("365.4, 365.4, 365.4, 402.9, 477.8", \ + "418.6, 418.6, 418.6, 456.1, 531.0", \ + "524.5, 524.5, 524.5, 562.0, 636.9", \ + "733.8, 733.8, 733.8, 771.2, 846.2", \ + "1149.3, 1149.3, 1149.3, 1186.7, 1261.7"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("508.0, 508.0, 508.0, 545.5, 620.4", \ + "598.4, 598.4, 598.4, 635.9, 710.8", \ + "777.5, 777.5, 777.5, 815.0, 889.9", \ + "1136.8, 1136.8, 1136.8, 1174.2, 1249.2", \ + "1857.0, 1857.0, 1857.0, 1894.4, 1969.4"); + } + } + } + } + + cell (ao2o22_x4) { + area : 0.0 ; + cell_leakage_power : 1.1 ; + leakage_power () { + when : "(i3 & !(i2) & !(i1) & i0)" ; + value : 0.27 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 0.52 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & i3) | (!(i1) & i2))) | (i1 & !(i2) & i3))" ; + value : 0.4 ; + } + leakage_power () { + when : "(!((i0 | i1)) | (!(i2) & !(i3)))" ; + value : 3.2 ; + } + pin (i3) { + direction : input ; + capacitance : 3.36 ; + } + pin (i2) { + direction : input ; + capacitance : 3.42 ; + } + pin (i1) { + direction : input ; + capacitance : 3.52 ; + } + pin (i0) { + direction : input ; + capacitance : 3.57 ; + } + pin (q) { + function : "((i3 | i2) & (i0 | i1))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("83.6, 83.6, 83.6, 89.6, 100.6", \ + "96.1, 96.1, 96.1, 102.1, 113.4", \ + "112.0, 112.0, 112.0, 118.2, 129.6", \ + "132.8, 132.8, 132.8, 139.1, 151.1", \ + "164.5, 164.5, 164.5, 170.9, 183.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("56.8, 56.8, 56.8, 64.5, 79.6", \ + "69.3, 69.3, 69.3, 77.0, 92.2", \ + "92.9, 92.9, 92.9, 100.6, 115.9", \ + "137.5, 137.5, 137.5, 145.2, 160.6", \ + "224.4, 224.4, 224.4, 232.0, 247.4"); + } + cell_fall (inslew_load_5x5__1) { + values ("120.8, 120.8, 120.8, 126.8, 137.9", \ + "125.9, 125.9, 125.9, 131.9, 143.3", \ + "133.3, 133.3, 133.3, 139.4, 151.0", \ + "146.2, 146.2, 146.2, 151.7, 163.5", \ + "167.8, 167.8, 167.8, 173.4, 184.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("75.0, 75.0, 75.0, 78.7, 85.9", \ + "85.6, 85.6, 85.6, 89.2, 96.4", \ + "106.5, 106.5, 106.5, 110.1, 117.3", \ + "148.7, 148.7, 148.7, 152.5, 159.8", \ + "232.3, 232.3, 232.3, 236.1, 243.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("76.1, 76.1, 76.1, 82.1, 92.9", \ + "82.8, 82.8, 82.8, 88.8, 99.9", \ + "85.7, 85.7, 85.7, 91.8, 103.2", \ + "77.8, 77.8, 77.8, 84.0, 95.7", \ + "47.1, 47.1, 47.1, 53.5, 65.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("51.7, 51.7, 51.7, 59.4, 74.5", \ + "61.4, 61.4, 61.4, 69.0, 84.2", \ + "78.7, 78.7, 78.7, 86.5, 101.7", \ + "110.3, 110.3, 110.3, 118.1, 133.4", \ + "170.3, 170.3, 170.3, 178.0, 193.4"); + } + cell_fall (inslew_load_5x5__1) { + values ("112.3, 112.3, 112.3, 118.3, 129.1", \ + "128.0, 128.0, 128.0, 134.0, 145.2", \ + "152.8, 152.8, 152.8, 158.8, 170.4", \ + "195.1, 195.1, 195.1, 200.6, 212.4", \ + "272.0, 272.0, 272.0, 277.6, 288.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("65.1, 65.1, 65.1, 68.8, 75.9", \ + "77.7, 77.7, 77.7, 81.4, 88.5", \ + "101.9, 101.9, 101.9, 105.6, 112.8", \ + "149.4, 149.4, 149.4, 153.3, 160.6", \ + "243.4, 243.4, 243.4, 247.2, 255.0"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("81.5, 81.5, 81.5, 87.5, 98.5", \ + "82.8, 82.8, 82.8, 88.7, 100.0", \ + "78.4, 78.4, 78.4, 84.5, 95.9", \ + "57.9, 57.9, 57.9, 64.1, 75.8", \ + "2.2, 2.2, 2.2, 8.5, 20.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("59.6, 59.6, 59.6, 67.2, 82.3", \ + "66.5, 66.5, 66.5, 74.2, 89.3", \ + "80.3, 80.3, 80.3, 88.0, 103.2", \ + "106.2, 106.2, 106.2, 114.0, 129.3", \ + "155.3, 155.3, 155.3, 163.1, 178.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("132.7, 132.7, 132.7, 138.7, 149.9", \ + "153.3, 153.3, 153.3, 159.3, 170.8", \ + "188.0, 188.0, 188.0, 193.9, 205.6", \ + "250.5, 250.5, 250.5, 256.1, 267.5", \ + "368.1, 368.1, 368.1, 373.7, 384.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("77.9, 77.9, 77.9, 81.6, 88.8", \ + "92.8, 92.8, 92.8, 96.4, 103.7", \ + "122.0, 122.0, 122.0, 125.6, 132.9", \ + "178.1, 178.1, 178.1, 181.9, 189.4", \ + "290.7, 290.7, 290.7, 294.5, 302.2"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("88.6, 88.6, 88.6, 94.6, 105.8", \ + "94.6, 94.6, 94.6, 100.6, 112.0", \ + "100.6, 100.6, 100.6, 106.8, 118.2", \ + "103.9, 103.9, 103.9, 110.1, 122.1", \ + "100.4, 100.4, 100.4, 106.7, 119.1"); + } + rise_transition (inslew_load_5x5__1) { + values ("64.6, 64.6, 64.6, 72.3, 87.4", \ + "74.1, 74.1, 74.1, 81.9, 97.1", \ + "93.4, 93.4, 93.4, 101.1, 116.4", \ + "130.8, 130.8, 130.8, 138.5, 153.9", \ + "203.9, 203.9, 203.9, 211.6, 227.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("142.4, 142.4, 142.4, 148.4, 159.8", \ + "152.7, 152.7, 152.7, 158.8, 170.4", \ + "171.4, 171.4, 171.4, 177.2, 189.0", \ + "205.9, 205.9, 205.9, 211.5, 222.8", \ + "272.3, 272.3, 272.3, 277.9, 288.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("88.5, 88.5, 88.5, 92.2, 99.4", \ + "102.1, 102.1, 102.1, 105.7, 112.9", \ + "128.5, 128.5, 128.5, 132.2, 139.5", \ + "181.8, 181.8, 181.8, 185.6, 193.1", \ + "289.2, 289.2, 289.2, 293.0, 300.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("550.4, 550.4, 550.4, 610.0, 729.2", \ + "646.3, 646.3, 646.3, 705.9, 825.1", \ + "831.7, 831.7, 831.7, 891.3, 1010.5", \ + "1190.8, 1190.8, 1190.8, 1250.4, 1369.6", \ + "1897.9, 1897.9, 1897.9, 1957.5, 2076.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("816.6, 816.6, 816.6, 876.2, 995.4", \ + "922.2, 922.2, 922.2, 981.8, 1101.0", \ + "1132.3, 1132.3, 1132.3, 1191.9, 1311.1", \ + "1558.3, 1558.3, 1558.3, 1617.9, 1737.1", \ + "2404.6, 2404.6, 2404.6, 2464.2, 2583.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("495.9, 495.9, 495.9, 555.5, 674.7", \ + "562.7, 562.7, 562.7, 622.3, 741.5", \ + "687.3, 687.3, 687.3, 746.9, 866.1", \ + "921.6, 921.6, 921.6, 981.2, 1100.3", \ + "1373.8, 1373.8, 1373.8, 1433.4, 1552.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("711.2, 711.2, 711.2, 770.8, 890.0", \ + "830.8, 830.8, 830.8, 890.4, 1009.6", \ + "1063.5, 1063.5, 1063.5, 1123.1, 1242.3", \ + "1524.9, 1524.9, 1524.9, 1584.5, 1703.7", \ + "2441.4, 2441.4, 2441.4, 2501.0, 2620.2"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("583.1, 583.1, 583.1, 642.7, 761.9", \ + "633.9, 633.9, 633.9, 693.5, 812.7", \ + "736.2, 736.2, 736.2, 795.8, 915.0", \ + "932.8, 932.8, 932.8, 992.4, 1111.6", \ + "1311.7, 1311.7, 1311.7, 1371.3, 1490.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("846.9, 846.9, 846.9, 906.5, 1025.7", \ + "990.4, 990.4, 990.4, 1050.0, 1169.2", \ + "1274.6, 1274.6, 1274.6, 1334.2, 1453.4", \ + "1829.2, 1829.2, 1829.2, 1888.8, 2008.0", \ + "2941.1, 2941.1, 2941.1, 3000.7, 3119.9"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("637.8, 637.8, 637.8, 697.4, 816.6", \ + "716.0, 716.0, 716.0, 775.6, 894.8", \ + "874.1, 874.1, 874.1, 933.7, 1052.9", \ + "1185.8, 1185.8, 1185.8, 1245.4, 1364.6", \ + "1801.2, 1801.2, 1801.2, 1860.8, 1980.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("959.7, 959.7, 959.7, 1019.3, 1138.5", \ + "1096.8, 1096.8, 1096.8, 1156.4, 1275.6", \ + "1367.6, 1367.6, 1367.6, 1427.2, 1546.4", \ + "1913.5, 1913.5, 1913.5, 1973.1, 2092.3", \ + "3012.0, 3012.0, 3012.0, 3071.6, 3190.8"); + } + } + } + } + + cell (buf_x2) { + area : 0.0 ; + cell_leakage_power : 2.2 ; + leakage_power () { + when : "i" ; + value : 1.7 ; + } + leakage_power () { + when : "!(i)" ; + value : 2.6 ; + } + pin (i) { + direction : input ; + capacitance : 3.03 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("45.4, 45.4, 45.4, 52.3, 64.3", \ + "49.1, 49.1, 49.1, 56.2, 68.9", \ + "50.4, 50.4, 50.4, 57.8, 71.2", \ + "46.7, 46.7, 46.7, 54.3, 68.6", \ + "34.6, 34.6, 34.6, 42.5, 57.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("31.6, 31.6, 31.6, 41.1, 59.6", \ + "42.5, 42.5, 42.5, 52.1, 70.8", \ + "62.0, 62.0, 62.0, 71.6, 90.5", \ + "98.4, 98.4, 98.4, 108.1, 127.2", \ + "169.3, 169.3, 169.3, 179.0, 198.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("54.1, 54.1, 54.1, 60.7, 72.4", \ + "63.1, 63.1, 63.1, 70.0, 82.3", \ + "75.9, 75.9, 75.9, 83.2, 96.2", \ + "96.9, 96.9, 96.9, 104.4, 118.7", \ + "136.8, 136.8, 136.8, 143.8, 158.3"); + } + fall_transition (inslew_load_5x5__0) { + values ("33.3, 33.3, 33.3, 37.9, 46.3", \ + "44.4, 44.4, 44.4, 49.0, 57.7", \ + "65.4, 65.4, 65.4, 70.0, 78.9", \ + "106.6, 106.6, 106.6, 111.2, 120.3", \ + "188.1, 188.1, 188.1, 193.0, 202.3"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__0) { + values ("221.9, 221.9, 221.9, 259.4, 334.3", \ + "273.7, 273.7, 273.7, 311.2, 386.1", \ + "373.7, 373.7, 373.7, 411.1, 486.1", \ + "570.1, 570.1, 570.1, 607.6, 682.5", \ + "960.0, 960.0, 960.0, 997.5, 1072.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("278.0, 278.0, 278.0, 315.5, 390.4", \ + "355.0, 355.0, 355.0, 392.4, 467.4", \ + "505.3, 505.3, 505.3, 542.8, 617.7", \ + "803.6, 803.6, 803.6, 841.0, 916.0", \ + "1398.7, 1398.7, 1398.7, 1436.2, 1511.1"); + } + } + } + } + + cell (buf_x4) { + area : 0.0 ; + cell_leakage_power : 1.7 ; + leakage_power () { + when : "i" ; + value : 0.26 ; + } + leakage_power () { + when : "!(i)" ; + value : 3.2 ; + } + pin (i) { + direction : input ; + capacitance : 3.44 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("53.6, 53.6, 53.6, 59.4, 69.6", \ + "59.2, 59.2, 59.2, 65.1, 75.7", \ + "62.8, 62.8, 62.8, 68.7, 79.9", \ + "61.3, 61.3, 61.3, 67.4, 78.9", \ + "50.8, 50.8, 50.8, 57.1, 69.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("34.1, 34.1, 34.1, 41.7, 56.6", \ + "44.7, 44.7, 44.7, 52.3, 67.3", \ + "63.6, 63.6, 63.6, 71.3, 86.4", \ + "98.5, 98.5, 98.5, 106.3, 121.6", \ + "166.0, 166.0, 166.0, 173.7, 189.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("64.2, 64.2, 64.2, 69.6, 79.5", \ + "74.6, 74.6, 74.6, 80.4, 90.3", \ + "89.1, 89.1, 89.1, 95.0, 105.8", \ + "111.4, 111.4, 111.4, 117.4, 129.0", \ + "152.0, 152.0, 152.0, 157.5, 168.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("36.6, 36.6, 36.6, 40.2, 47.0", \ + "46.5, 46.5, 46.5, 50.1, 57.2", \ + "65.3, 65.3, 65.3, 68.9, 76.0", \ + "102.1, 102.1, 102.1, 105.7, 112.8", \ + "174.4, 174.4, 174.4, 178.3, 185.6"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__1) { + values ("396.6, 396.6, 396.6, 456.2, 575.4", \ + "477.2, 477.2, 477.2, 536.8, 656.0", \ + "630.1, 630.1, 630.1, 689.7, 808.9", \ + "925.9, 925.9, 925.9, 985.4, 1104.6", \ + "1507.7, 1507.7, 1507.7, 1567.3, 1686.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("499.7, 499.7, 499.7, 559.3, 678.5", \ + "610.2, 610.2, 610.2, 669.8, 789.0", \ + "824.3, 824.3, 824.3, 883.9, 1003.0", \ + "1246.7, 1246.7, 1246.7, 1306.3, 1425.5", \ + "2087.2, 2087.2, 2087.2, 2146.8, 2266.0"); + } + } + } + } + + cell (buf_x8) { + area : 0.0 ; + cell_leakage_power : 7.9 ; + leakage_power () { + when : "i" ; + value : 2.6 ; + } + leakage_power () { + when : "!(i)" ; + value : 13 ; + } + pin (i) { + direction : input ; + capacitance : 5.48 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 9.85 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__5) { + values ("53.7, 53.7, 53.7, 59.6, 70.1", \ + "59.2, 59.2, 59.2, 65.3, 76.2", \ + "62.9, 62.9, 62.9, 69.0, 80.5", \ + "62.2, 62.2, 62.2, 68.5, 80.4", \ + "53.7, 53.7, 53.7, 60.2, 72.8"); + } + rise_transition (inslew_load_5x5__5) { + values ("34.8, 34.8, 34.8, 42.7, 58.0", \ + "45.8, 45.8, 45.8, 53.7, 69.2", \ + "65.5, 65.5, 65.5, 73.4, 89.0", \ + "102.1, 102.1, 102.1, 110.2, 125.9", \ + "173.3, 173.3, 173.3, 181.1, 197.1"); + } + cell_fall (inslew_load_5x5__5) { + values ("64.1, 64.1, 64.1, 69.6, 79.8", \ + "74.3, 74.3, 74.3, 80.2, 90.4", \ + "88.5, 88.5, 88.5, 94.6, 105.7", \ + "110.7, 110.7, 110.7, 117.0, 129.0", \ + "151.9, 151.9, 151.9, 157.5, 169.0"); + } + fall_transition (inslew_load_5x5__5) { + values ("37.6, 37.6, 37.6, 41.2, 48.2", \ + "48.4, 48.4, 48.4, 52.0, 59.4", \ + "69.0, 69.0, 69.0, 72.7, 79.9", \ + "109.4, 109.4, 109.4, 113.0, 120.2", \ + "188.8, 188.8, 188.8, 192.6, 200.3"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__5) { + values ("778.9, 778.9, 778.9, 902.1, 1148.4", \ + "945.3, 945.3, 945.3, 1068.4, 1314.7", \ + "1262.0, 1262.0, 1262.0, 1385.1, 1631.4", \ + "1876.6, 1876.6, 1876.6, 1999.8, 2246.1", \ + "3088.6, 3088.6, 3088.6, 3211.7, 3458.0"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("986.8, 986.8, 986.8, 1109.9, 1356.2", \ + "1219.6, 1219.6, 1219.6, 1342.8, 1589.1", \ + "1671.9, 1671.9, 1671.9, 1795.0, 2041.3", \ + "2563.8, 2563.8, 2563.8, 2686.9, 2933.2", \ + "4339.6, 4339.6, 4339.6, 4462.7, 4709.0"); + } + } + } + } + + cell (invbuf_x3) { + area : 0.0 ; + cell_leakage_power : 4 ; + leakage_power () { + when : "1" ; + value : 4 ; + } + pin (i) { + direction : input ; + capacitance : 8.00 ; + } + pin (c1) { + function : "!(c0)" ; + direction : output ; + capacitance : 3.88 ; + } + pin (c0) { + function : "!(i)" ; + direction : output ; + capacitance : 11.79 ; + timing (maxd_c0_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__7) { + values ("29.1, 29.1, 29.1, 45.3, 74.4", \ + "38.0, 38.0, 38.0, 55.9, 88.1", \ + "53.0, 53.0, 53.0, 72.6, 108.4", \ + "81.4, 81.4, 81.4, 102.1, 141.1", \ + "137.1, 137.1, 137.1, 158.5, 199.8"); + } + rise_transition (inslew_load_5x5__7) { + values ("56.9, 56.9, 56.9, 82.9, 133.9", \ + "90.0, 90.0, 90.0, 116.5, 168.3", \ + "153.9, 153.9, 153.9, 180.9, 233.7", \ + "280.2, 280.2, 280.2, 307.5, 361.4", \ + "532.0, 532.0, 532.0, 559.6, 614.2"); + } + cell_fall (inslew_load_5x5__7) { + values ("15.4, 15.4, 15.4, 28.3, 49.6", \ + "12.8, 12.8, 12.8, 28.2, 53.7", \ + "5.1, 5.1, 5.1, 22.9, 53.4", \ + "-12.4, -12.4, -12.4, 7.3, 42.8", \ + "-48.8, -48.8, -48.8, -27.6, 11.7"); + } + fall_transition (inslew_load_5x5__7) { + values ("24.1, 24.1, 24.1, 34.9, 55.3", \ + "37.8, 37.8, 37.8, 49.5, 70.9", \ + "63.9, 63.9, 63.9, 76.6, 99.9", \ + "115.3, 115.3, 115.3, 128.8, 154.1", \ + "217.2, 217.2, 217.2, 231.4, 258.4"); + } + } + internal_power (energy_neg_c0_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__7) { + values ("278.3, 278.3, 278.3, 425.7, 720.5", \ + "408.5, 408.5, 408.5, 555.9, 850.8", \ + "668.9, 668.9, 668.9, 816.4, 1111.2", \ + "1189.8, 1189.8, 1189.8, 1337.3, 1632.1", \ + "2231.7, 2231.7, 2231.7, 2379.1, 2674.0"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("218.5, 218.5, 218.5, 365.9, 660.7", \ + "290.4, 290.4, 290.4, 437.8, 732.7", \ + "434.3, 434.3, 434.3, 581.7, 876.6", \ + "722.1, 722.1, 722.1, 869.6, 1164.4", \ + "1297.8, 1297.8, 1297.8, 1445.2, 1740.1"); + } + } + } + } + + cell (inv_x1) { + area : 0.0 ; + cell_leakage_power : 0.13 ; + leakage_power () { + when : "i" ; + value : 0.26 ; + } + leakage_power () { + when : "!(i)" ; + value : 5.9e-05 ; + } + pin (i) { + direction : input ; + capacitance : 3.63 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 2.00 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__8) { + values ("17.5, 17.5, 17.5, 26.2, 41.5", \ + "24.1, 24.1, 24.1, 33.5, 50.6", \ + "35.8, 35.8, 35.8, 45.8, 64.4", \ + "58.4, 58.4, 58.4, 68.7, 88.4", \ + "103.0, 103.0, 103.0, 113.5, 133.9"); + } + rise_transition (inslew_load_5x5__8) { + values ("38.2, 38.2, 38.2, 50.3, 73.8", \ + "67.2, 67.2, 67.2, 79.5, 103.5", \ + "123.4, 123.4, 123.4, 135.9, 160.4", \ + "234.9, 234.9, 234.9, 247.4, 272.2", \ + "457.2, 457.2, 457.2, 469.8, 494.8"); + } + cell_fall (inslew_load_5x5__8) { + values ("7.6, 7.6, 7.6, 14.9, 26.8", \ + "4.7, 4.7, 4.7, 13.0, 27.2", \ + "-2.1, -2.1, -2.1, 6.9, 23.3", \ + "-16.6, -16.6, -16.6, -6.9, 11.1", \ + "-45.8, -45.8, -45.8, -35.8, -16.6"); + } + fall_transition (inslew_load_5x5__8) { + values ("17.6, 17.6, 17.6, 23.1, 33.0", \ + "31.0, 31.0, 31.0, 36.9, 47.6", \ + "57.2, 57.2, 57.2, 63.4, 75.0", \ + "109.1, 109.1, 109.1, 115.6, 127.9", \ + "212.8, 212.8, 212.8, 219.3, 232.1"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__8) { + values ("67.0, 67.0, 67.0, 92.0, 141.9", \ + "109.6, 109.6, 109.6, 134.6, 184.4", \ + "194.8, 194.8, 194.8, 219.7, 269.6", \ + "365.1, 365.1, 365.1, 390.0, 439.9", \ + "705.7, 705.7, 705.7, 730.6, 780.5"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("52.6, 52.6, 52.6, 77.6, 127.4", \ + "79.8, 79.8, 79.8, 104.8, 154.6", \ + "134.2, 134.2, 134.2, 159.2, 209.1", \ + "243.1, 243.1, 243.1, 268.0, 317.9", \ + "460.7, 460.7, 460.7, 485.6, 535.5"); + } + } + } + } + + cell (inv_x2) { + area : 0.0 ; + cell_leakage_power : 1.3 ; + leakage_power () { + when : "i" ; + value : 2.6 ; + } + leakage_power () { + when : "!(i)" ; + value : 8.5e-05 ; + } + pin (i) { + direction : input ; + capacitance : 5.67 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__0) { + values ("16.2, 16.2, 16.2, 23.2, 35.7", \ + "22.8, 22.8, 22.8, 30.3, 44.1", \ + "34.5, 34.5, 34.5, 42.3, 57.2", \ + "57.2, 57.2, 57.2, 65.2, 80.7", \ + "102.0, 102.0, 102.0, 110.1, 126.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("38.4, 38.4, 38.4, 48.1, 66.8", \ + "69.9, 69.9, 69.9, 79.6, 98.7", \ + "130.7, 130.7, 130.7, 140.6, 160.0", \ + "251.3, 251.3, 251.3, 261.2, 280.9", \ + "492.0, 492.0, 492.0, 501.9, 521.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("6.2, 6.2, 6.2, 12.2, 22.3", \ + "3.3, 3.3, 3.3, 10.0, 21.9", \ + "-3.3, -3.3, -3.3, 3.9, 17.2", \ + "-17.1, -17.1, -17.1, -9.5, 4.8", \ + "-44.8, -44.8, -44.8, -37.1, -22.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("17.3, 17.3, 17.3, 21.8, 29.9", \ + "31.3, 31.3, 31.3, 36.1, 44.9", \ + "58.8, 58.8, 58.8, 63.7, 73.1", \ + "113.3, 113.3, 113.3, 118.4, 128.2", \ + "222.0, 222.0, 222.0, 227.2, 237.3"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__0) { + values ("123.3, 123.3, 123.3, 160.8, 235.7", \ + "210.0, 210.0, 210.0, 247.5, 322.4", \ + "383.4, 383.4, 383.4, 420.9, 495.8", \ + "730.2, 730.2, 730.2, 767.7, 842.6", \ + "1423.9, 1423.9, 1423.9, 1461.3, 1536.3"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("94.4, 94.4, 94.4, 131.9, 206.8", \ + "150.4, 150.4, 150.4, 187.9, 262.8", \ + "262.5, 262.5, 262.5, 300.0, 374.9", \ + "486.6, 486.6, 486.6, 524.1, 599.0", \ + "934.9, 934.9, 934.9, 972.4, 1047.3"); + } + } + } + } + + cell (inv_x4) { + area : 0.0 ; + cell_leakage_power : 1.6 ; + leakage_power () { + when : "i" ; + value : 3.2 ; + } + leakage_power () { + when : "!(i)" ; + value : 0.00048 ; + } + pin (i) { + direction : input ; + capacitance : 10.77 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("14.6, 14.6, 14.6, 20.4, 30.8", \ + "21.2, 21.2, 21.2, 27.3, 38.6", \ + "32.9, 32.9, 32.9, 39.2, 51.2", \ + "55.5, 55.5, 55.5, 61.9, 74.4", \ + "100.3, 100.3, 100.3, 106.8, 119.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("36.4, 36.4, 36.4, 44.2, 59.2", \ + "67.9, 67.9, 67.9, 75.7, 91.0", \ + "128.7, 128.7, 128.7, 136.5, 152.1", \ + "249.3, 249.3, 249.3, 257.2, 272.9", \ + "489.9, 489.9, 489.9, 497.8, 513.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("4.8, 4.8, 4.8, 9.9, 18.4", \ + "1.8, 1.8, 1.8, 7.4, 17.2", \ + "-4.8, -4.8, -4.8, 1.0, 11.9", \ + "-18.7, -18.7, -18.7, -12.6, -0.9", \ + "-46.4, -46.4, -46.4, -40.2, -28.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("16.3, 16.3, 16.3, 20.0, 26.7", \ + "30.3, 30.3, 30.3, 34.2, 41.3", \ + "57.8, 57.8, 57.8, 61.7, 69.3", \ + "112.2, 112.2, 112.2, 116.3, 124.2", \ + "220.9, 220.9, 220.9, 225.1, 233.2"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__1) { + values ("231.2, 231.2, 231.2, 290.8, 410.0", \ + "404.7, 404.7, 404.7, 464.3, 583.4", \ + "751.5, 751.5, 751.5, 811.1, 930.3", \ + "1445.1, 1445.1, 1445.1, 1504.7, 1623.9", \ + "2832.4, 2832.4, 2832.4, 2892.0, 3011.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("173.4, 173.4, 173.4, 233.0, 352.2", \ + "285.5, 285.5, 285.5, 345.1, 464.3", \ + "509.6, 509.6, 509.6, 569.2, 688.4", \ + "957.9, 957.9, 957.9, 1017.5, 1136.7", \ + "1854.5, 1854.5, 1854.5, 1914.0, 2033.2"); + } + } + } + } + + cell (inv_x8) { + area : 0.0 ; + cell_leakage_power : 6.6 ; + leakage_power () { + when : "i" ; + value : 13 ; + } + leakage_power () { + when : "!(i)" ; + value : 0.0028 ; + } + pin (i) { + direction : input ; + capacitance : 20.95 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 9.85 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__5) { + values ("14.8, 14.8, 14.8, 20.8, 31.4", \ + "21.4, 21.4, 21.4, 27.7, 39.3", \ + "33.1, 33.1, 33.1, 39.6, 52.0", \ + "55.7, 55.7, 55.7, 62.3, 75.3", \ + "100.5, 100.5, 100.5, 107.2, 120.4"); + } + rise_transition (inslew_load_5x5__5) { + values ("36.7, 36.7, 36.7, 44.7, 60.2", \ + "68.1, 68.1, 68.1, 76.2, 92.0", \ + "128.9, 128.9, 128.9, 137.1, 153.1", \ + "249.5, 249.5, 249.5, 257.7, 273.9", \ + "490.2, 490.2, 490.2, 498.4, 514.7"); + } + cell_fall (inslew_load_5x5__5) { + values ("5.0, 5.0, 5.0, 10.2, 18.9", \ + "2.0, 2.0, 2.0, 7.7, 17.8", \ + "-4.6, -4.6, -4.6, 1.4, 12.6", \ + "-18.5, -18.5, -18.5, -12.2, -0.1", \ + "-46.2, -46.2, -46.2, -39.8, -27.3"); + } + fall_transition (inslew_load_5x5__5) { + values ("16.5, 16.5, 16.5, 20.2, 27.1", \ + "30.5, 30.5, 30.5, 34.4, 41.8", \ + "57.9, 57.9, 57.9, 62.0, 69.8", \ + "112.4, 112.4, 112.4, 116.6, 124.7", \ + "221.1, 221.1, 221.1, 225.4, 233.7"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__5) { + values ("466.4, 466.4, 466.4, 589.6, 835.9", \ + "813.3, 813.3, 813.3, 936.4, 1182.7", \ + "1506.9, 1506.9, 1506.9, 1630.0, 1876.3", \ + "2894.2, 2894.2, 2894.2, 3017.3, 3263.6", \ + "5668.7, 5668.7, 5668.7, 5791.9, 6038.2"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("350.8, 350.8, 350.8, 474.0, 720.3", \ + "575.0, 575.0, 575.0, 698.1, 944.4", \ + "1023.2, 1023.2, 1023.2, 1146.4, 1392.7", \ + "1919.8, 1919.8, 1919.8, 2042.9, 2289.2", \ + "3712.9, 3712.9, 3712.9, 3836.0, 4082.3"); + } + } + } + } + + cell (mx2_x2) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "(cmd & i1)" ; + value : 2.1 ; + } + leakage_power () { + when : "(cmd & !(i1))" ; + value : 4.3 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 0.4 ; + } + leakage_power () { + when : "(!(cmd) & !(i0))" ; + value : 2.6 ; + } + pin (i1) { + direction : input ; + capacitance : 3.58 ; + } + pin (i0) { + direction : input ; + capacitance : 3.52 ; + } + pin (cmd) { + direction : input ; + capacitance : 5.98 ; + } + pin (q) { + function : "((i1 & (i0 | cmd)) | (i0 & !(cmd)))" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("55.0, 55.0, 55.0, 62.1, 74.5", \ + "58.0, 58.0, 58.0, 65.2, 78.1", \ + "55.7, 55.7, 55.7, 63.1, 76.7", \ + "41.9, 41.9, 41.9, 49.6, 63.8", \ + "6.1, 6.1, 6.1, 14.0, 28.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("38.4, 38.4, 38.4, 47.9, 66.6", \ + "47.7, 47.7, 47.7, 57.4, 76.1", \ + "64.3, 64.3, 64.3, 73.9, 92.9", \ + "94.6, 94.6, 94.6, 104.3, 123.5", \ + "152.8, 152.8, 152.8, 162.6, 181.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("77.8, 77.8, 77.8, 84.7, 97.0", \ + "91.8, 91.8, 91.8, 99.0, 111.7", \ + "113.6, 113.6, 113.6, 120.9, 134.6", \ + "151.5, 151.5, 151.5, 158.9, 173.5", \ + "223.9, 223.9, 223.9, 231.0, 245.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("43.5, 43.5, 43.5, 48.1, 56.8", \ + "56.0, 56.0, 56.0, 60.7, 69.7", \ + "79.7, 79.7, 79.7, 84.4, 93.5", \ + "126.1, 126.1, 126.1, 130.8, 140.0", \ + "217.4, 217.4, 217.4, 222.3, 232.0"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("61.4, 61.4, 61.4, 68.6, 81.5", \ + "65.2, 65.2, 65.2, 72.5, 85.8", \ + "68.0, 68.0, 68.0, 75.4, 89.3", \ + "67.0, 67.0, 67.0, 74.8, 89.1", \ + "59.6, 59.6, 59.6, 67.5, 82.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("46.2, 46.2, 46.2, 55.8, 74.5", \ + "56.0, 56.0, 56.0, 65.7, 84.5", \ + "75.1, 75.1, 75.1, 84.8, 103.8", \ + "111.7, 111.7, 111.7, 121.5, 140.7", \ + "183.6, 183.6, 183.6, 193.3, 212.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("98.0, 98.0, 98.0, 105.3, 118.1", \ + "107.7, 107.7, 107.7, 115.1, 128.5", \ + "124.5, 124.5, 124.5, 132.0, 146.2", \ + "156.5, 156.5, 156.5, 163.7, 178.4", \ + "219.3, 219.3, 219.3, 226.5, 240.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("60.0, 60.0, 60.0, 64.7, 73.7", \ + "73.5, 73.5, 73.5, 78.1, 87.2", \ + "99.7, 99.7, 99.7, 104.4, 113.6", \ + "152.2, 152.2, 152.2, 157.1, 166.3", \ + "257.3, 257.3, 257.3, 262.1, 272.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("61.4, 61.4, 61.4, 68.6, 81.5", \ + "65.2, 65.2, 65.2, 72.5, 85.8", \ + "68.0, 68.0, 68.0, 75.4, 89.3", \ + "67.0, 67.0, 67.0, 74.8, 89.1", \ + "59.6, 59.6, 59.6, 67.5, 82.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("46.2, 46.2, 46.2, 55.8, 74.5", \ + "56.0, 56.0, 56.0, 65.7, 84.5", \ + "75.1, 75.1, 75.1, 84.8, 103.8", \ + "111.7, 111.7, 111.7, 121.5, 140.7", \ + "183.6, 183.6, 183.6, 193.3, 212.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("98.0, 98.0, 98.0, 105.3, 118.1", \ + "107.7, 107.7, 107.7, 115.1, 128.5", \ + "124.5, 124.5, 124.5, 132.0, 146.2", \ + "156.5, 156.5, 156.5, 163.7, 178.4", \ + "219.3, 219.3, 219.3, 226.5, 240.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("60.0, 60.0, 60.0, 64.7, 73.7", \ + "73.5, 73.5, 73.5, 78.1, 87.2", \ + "99.7, 99.7, 99.7, 104.4, 113.6", \ + "152.2, 152.2, 152.2, 157.1, 166.3", \ + "257.3, 257.3, 257.3, 262.1, 272.0"); + } + } + timing (maxd_q_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__0) { + values ("102.8, 102.8, 102.8, 110.0, 122.9", \ + "113.5, 113.5, 113.5, 120.8, 133.9", \ + "127.6, 127.6, 127.6, 135.0, 148.6", \ + "148.1, 148.1, 148.1, 155.6, 169.7", \ + "180.4, 180.4, 180.4, 188.2, 202.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("46.2, 46.2, 46.2, 55.8, 74.5", \ + "52.6, 52.6, 52.6, 62.3, 81.1", \ + "64.2, 64.2, 64.2, 73.9, 92.8", \ + "85.9, 85.9, 85.9, 95.6, 114.7", \ + "127.5, 127.5, 127.5, 137.2, 156.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("100.4, 100.4, 100.4, 107.1, 119.3", \ + "106.6, 106.6, 106.6, 113.5, 125.8", \ + "111.4, 111.4, 111.4, 118.5, 131.0", \ + "113.1, 113.1, 113.1, 120.4, 133.5", \ + "109.5, 109.5, 109.5, 117.0, 131.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("39.5, 39.5, 39.5, 44.1, 52.7", \ + "43.8, 43.8, 43.8, 48.4, 57.2", \ + "51.5, 51.5, 51.5, 56.1, 65.1", \ + "65.2, 65.2, 65.2, 69.9, 78.9", \ + "91.7, 91.7, 91.7, 96.3, 105.5"); + } + } + internal_power (energy_pos_q_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__0) { + values ("242.9, 242.9, 242.9, 280.4, 355.3", \ + "282.8, 282.8, 282.8, 320.3, 395.2", \ + "358.3, 358.3, 358.3, 395.8, 470.7", \ + "503.8, 503.8, 503.8, 541.3, 616.2", \ + "789.9, 789.9, 789.9, 827.4, 902.3"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("320.8, 320.8, 320.8, 358.3, 433.2", \ + "397.5, 397.5, 397.5, 435.0, 509.9", \ + "546.2, 546.2, 546.2, 583.6, 658.6", \ + "839.8, 839.8, 839.8, 877.3, 952.2", \ + "1424.3, 1424.3, 1424.3, 1461.7, 1536.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("310.5, 310.5, 310.5, 348.0, 422.9", \ + "363.7, 363.7, 363.7, 401.2, 476.1", \ + "469.3, 469.3, 469.3, 506.7, 581.7", \ + "678.0, 678.0, 678.0, 715.5, 790.4", \ + "1092.8, 1092.8, 1092.8, 1130.3, 1205.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("441.5, 441.5, 441.5, 479.0, 553.9", \ + "532.4, 532.4, 532.4, 569.9, 644.8", \ + "711.9, 711.9, 711.9, 749.4, 824.3", \ + "1071.6, 1071.6, 1071.6, 1109.1, 1184.0", \ + "1792.3, 1792.3, 1792.3, 1829.7, 1904.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("310.5, 310.5, 310.5, 348.0, 422.9", \ + "363.7, 363.7, 363.7, 401.2, 476.1", \ + "469.3, 469.3, 469.3, 506.7, 581.7", \ + "678.0, 678.0, 678.0, 715.5, 790.4", \ + "1092.8, 1092.8, 1092.8, 1130.3, 1205.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("441.5, 441.5, 441.5, 479.0, 553.9", \ + "532.4, 532.4, 532.4, 569.9, 644.8", \ + "711.9, 711.9, 711.9, 749.4, 824.3", \ + "1071.6, 1071.6, 1071.6, 1109.1, 1184.0", \ + "1792.3, 1792.3, 1792.3, 1829.7, 1904.7"); + } + } + internal_power (energy_neg_q_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__0) { + values ("396.7, 396.7, 396.7, 434.2, 509.1", \ + "462.8, 462.8, 462.8, 500.2, 575.2", \ + "590.8, 590.8, 590.8, 628.3, 703.2", \ + "843.2, 843.2, 843.2, 880.7, 955.6", \ + "1344.2, 1344.2, 1344.2, 1381.6, 1456.6"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("405.0, 405.0, 405.0, 442.4, 517.4", \ + "455.1, 455.1, 455.1, 492.5, 567.5", \ + "550.2, 550.2, 550.2, 587.7, 662.6", \ + "733.4, 733.4, 733.4, 770.9, 845.8", \ + "1095.7, 1095.7, 1095.7, 1133.2, 1208.1"); + } + } + } + } + + cell (mx2_x4) { + area : 0.0 ; + cell_leakage_power : 2.7 ; + leakage_power () { + when : "(cmd & i1)" ; + value : 2.1 ; + } + leakage_power () { + when : "(cmd & !(i1))" ; + value : 4.9 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 0.4 ; + } + leakage_power () { + when : "(!(cmd) & !(i0))" ; + value : 3.2 ; + } + pin (i1) { + direction : input ; + capacitance : 3.58 ; + } + pin (i0) { + direction : input ; + capacitance : 3.52 ; + } + pin (cmd) { + direction : input ; + capacitance : 5.98 ; + } + pin (q) { + function : "((i0 & (i1 | !(cmd))) | (i1 & cmd))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("73.8, 73.8, 73.8, 79.8, 90.5", \ + "80.1, 80.1, 80.1, 86.1, 97.1", \ + "82.3, 82.3, 82.3, 88.3, 99.7", \ + "73.4, 73.4, 73.4, 79.6, 91.3", \ + "42.4, 42.4, 42.4, 48.7, 60.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("49.9, 49.9, 49.9, 57.6, 72.6", \ + "59.6, 59.6, 59.6, 67.3, 82.4", \ + "76.9, 76.9, 76.9, 84.6, 99.8", \ + "108.4, 108.4, 108.4, 116.2, 131.5", \ + "168.4, 168.4, 168.4, 176.0, 191.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("108.1, 108.1, 108.1, 114.0, 124.7", \ + "123.7, 123.7, 123.7, 129.7, 140.8", \ + "148.3, 148.3, 148.3, 154.3, 165.9", \ + "190.5, 190.5, 190.5, 196.0, 207.8", \ + "267.8, 267.8, 267.8, 273.3, 284.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("62.8, 62.8, 62.8, 66.4, 73.5", \ + "75.6, 75.6, 75.6, 79.2, 86.3", \ + "100.0, 100.0, 100.0, 103.6, 110.8", \ + "148.0, 148.0, 148.0, 151.8, 159.0", \ + "242.8, 242.8, 242.8, 246.6, 254.3"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("78.4, 78.4, 78.4, 84.3, 95.3", \ + "83.7, 83.7, 83.7, 89.7, 100.9", \ + "88.7, 88.7, 88.7, 94.8, 106.2", \ + "90.6, 90.6, 90.6, 96.9, 108.7", \ + "86.0, 86.0, 86.0, 92.4, 104.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("57.4, 57.4, 57.4, 65.1, 80.2", \ + "67.2, 67.2, 67.2, 74.9, 90.0", \ + "86.4, 86.4, 86.4, 94.2, 109.4", \ + "123.8, 123.8, 123.8, 131.5, 146.9", \ + "196.9, 196.9, 196.9, 204.6, 220.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("127.5, 127.5, 127.5, 133.6, 144.8", \ + "137.9, 137.9, 137.9, 143.9, 155.4", \ + "156.4, 156.4, 156.4, 162.3, 174.0", \ + "190.9, 190.9, 190.9, 196.5, 207.9", \ + "257.8, 257.8, 257.8, 263.3, 274.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("79.6, 79.6, 79.6, 83.3, 90.4", \ + "93.4, 93.4, 93.4, 97.0, 104.2", \ + "120.3, 120.3, 120.3, 123.9, 131.1", \ + "174.3, 174.3, 174.3, 178.1, 185.5", \ + "282.9, 282.9, 282.9, 286.7, 294.3"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("78.4, 78.4, 78.4, 84.3, 95.3", \ + "83.7, 83.7, 83.7, 89.7, 100.9", \ + "88.7, 88.7, 88.7, 94.8, 106.2", \ + "90.6, 90.6, 90.6, 96.9, 108.7", \ + "86.0, 86.0, 86.0, 92.4, 104.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("57.4, 57.4, 57.4, 65.1, 80.2", \ + "67.2, 67.2, 67.2, 74.9, 90.0", \ + "86.4, 86.4, 86.4, 94.2, 109.4", \ + "123.8, 123.8, 123.8, 131.5, 146.9", \ + "196.9, 196.9, 196.9, 204.6, 220.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("127.5, 127.5, 127.5, 133.6, 144.8", \ + "137.9, 137.9, 137.9, 143.9, 155.4", \ + "156.4, 156.4, 156.4, 162.3, 174.0", \ + "190.9, 190.9, 190.9, 196.5, 207.9", \ + "257.8, 257.8, 257.8, 263.3, 274.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("79.6, 79.6, 79.6, 83.3, 90.4", \ + "93.4, 93.4, 93.4, 97.0, 104.2", \ + "120.3, 120.3, 120.3, 123.9, 131.1", \ + "174.3, 174.3, 174.3, 178.1, 185.5", \ + "282.9, 282.9, 282.9, 286.7, 294.3"); + } + } + timing (maxd_q_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("124.0, 124.0, 124.0, 130.0, 140.9", \ + "136.6, 136.6, 136.6, 142.6, 153.8", \ + "153.6, 153.6, 153.6, 159.6, 171.0", \ + "177.5, 177.5, 177.5, 183.7, 195.2", \ + "214.7, 214.7, 214.7, 221.0, 233.1"); + } + rise_transition (inslew_load_5x5__1) { + values ("57.8, 57.8, 57.8, 65.5, 80.6", \ + "64.6, 64.6, 64.6, 72.2, 87.4", \ + "76.7, 76.7, 76.7, 84.4, 99.6", \ + "99.2, 99.2, 99.2, 106.9, 122.2", \ + "141.9, 141.9, 141.9, 149.6, 165.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("130.1, 130.1, 130.1, 136.0, 146.5", \ + "136.8, 136.8, 136.8, 142.8, 153.5", \ + "142.6, 142.6, 142.6, 148.6, 159.6", \ + "146.2, 146.2, 146.2, 152.2, 163.5", \ + "145.2, 145.2, 145.2, 151.3, 162.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("58.8, 58.8, 58.8, 62.5, 69.6", \ + "63.1, 63.1, 63.1, 66.8, 73.9", \ + "70.8, 70.8, 70.8, 74.4, 81.5", \ + "85.2, 85.2, 85.2, 88.8, 96.0", \ + "112.4, 112.4, 112.4, 115.9, 123.1"); + } + } + internal_power (energy_pos_q_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__1) { + values ("476.0, 476.0, 476.0, 535.6, 654.8", \ + "542.4, 542.4, 542.4, 602.0, 721.2", \ + "666.3, 666.3, 666.3, 725.9, 845.1", \ + "899.6, 899.6, 899.6, 959.2, 1078.4", \ + "1350.8, 1350.8, 1350.8, 1410.4, 1529.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("681.2, 681.2, 681.2, 740.8, 860.0", \ + "801.2, 801.2, 801.2, 860.8, 980.0", \ + "1033.9, 1033.9, 1033.9, 1093.5, 1212.7", \ + "1495.3, 1495.3, 1495.3, 1554.9, 1674.1", \ + "2411.6, 2411.6, 2411.6, 2471.2, 2590.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("562.8, 562.8, 562.8, 622.4, 741.6", \ + "641.7, 641.7, 641.7, 701.3, 820.5", \ + "799.5, 799.5, 799.5, 859.1, 978.3", \ + "1110.1, 1110.1, 1110.1, 1169.7, 1288.9", \ + "1724.2, 1724.2, 1724.2, 1783.8, 1903.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("859.1, 859.1, 859.1, 918.7, 1037.9", \ + "997.0, 997.0, 997.0, 1056.6, 1175.8", \ + "1268.8, 1268.8, 1268.8, 1328.4, 1447.6", \ + "1815.9, 1815.9, 1815.9, 1875.5, 1994.7", \ + "2915.2, 2915.2, 2915.2, 2974.8, 3094.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("562.8, 562.8, 562.8, 622.4, 741.6", \ + "641.7, 641.7, 641.7, 701.3, 820.5", \ + "799.5, 799.5, 799.5, 859.1, 978.3", \ + "1110.1, 1110.1, 1110.1, 1169.7, 1288.9", \ + "1724.2, 1724.2, 1724.2, 1783.8, 1903.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("859.1, 859.1, 859.1, 918.7, 1037.9", \ + "997.0, 997.0, 997.0, 1056.6, 1175.8", \ + "1268.8, 1268.8, 1268.8, 1328.4, 1447.6", \ + "1815.9, 1815.9, 1815.9, 1875.5, 1994.7", \ + "2915.2, 2915.2, 2915.2, 2974.8, 3094.0"); + } + } + internal_power (energy_neg_q_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__1) { + values ("651.1, 651.1, 651.1, 710.7, 829.9", \ + "735.9, 735.9, 735.9, 795.5, 914.7", \ + "898.0, 898.0, 898.0, 957.6, 1076.8", \ + "1212.8, 1212.8, 1212.8, 1272.4, 1391.6", \ + "1831.3, 1831.3, 1831.3, 1890.9, 2010.1"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("752.2, 752.2, 752.2, 811.8, 931.0", \ + "816.4, 816.4, 816.4, 876.0, 995.2", \ + "937.0, 937.0, 937.0, 996.6, 1115.8", \ + "1171.1, 1171.1, 1171.1, 1230.7, 1349.9", \ + "1626.1, 1626.1, 1626.1, 1685.7, 1804.9"); + } + } + } + } + + cell (mx3_x2) { + area : 0.0 ; + cell_leakage_power : 6.8 ; + leakage_power () { + when : "(cmd0 & cmd1 & i1)" ; + value : 13 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i1))" ; + value : 14 ; + } + leakage_power () { + when : "((cmd0 ^ cmd1) & i0 & i2)" ; + value : 7.2 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i0) & i2) | (!(cmd0) & cmd1 & i0 & !(i2)))" ; + value : 6.9 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i2)) | (!(cmd0) & cmd1 & !(i0)))" ; + value : 8.3 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & i1)" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & !(i1))" ; + value : 1.2 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & !(i0))" ; + value : 2.6 ; + } + pin (i2) { + direction : input ; + capacitance : 2.95 ; + } + pin (i1) { + direction : input ; + capacitance : 3.03 ; + } + pin (i0) { + direction : input ; + capacitance : 3.08 ; + } + pin (cmd1) { + direction : input ; + capacitance : 5.64 ; + } + pin (cmd0) { + direction : input ; + capacitance : 5.08 ; + } + pin (q) { + function : "((i0 & ((i2 & (!(cmd0) | i1 | !(cmd1))) | !(cmd0) | (i1 & cmd1))) | (i2 & cmd0 & (i1 | !(cmd1))) | (cmd0 & i1 & cmd1))" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("112.8, 112.8, 112.8, 120.4, 134.7", \ + "118.2, 118.2, 118.2, 125.9, 140.3", \ + "126.2, 126.2, 126.2, 134.0, 148.7", \ + "137.7, 137.7, 137.7, 145.6, 160.9", \ + "155.3, 155.3, 155.3, 163.3, 178.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("94.9, 94.9, 94.9, 104.6, 123.8", \ + "107.6, 107.6, 107.6, 117.4, 136.7", \ + "133.3, 133.3, 133.3, 143.1, 162.4", \ + "184.4, 184.4, 184.4, 194.2, 213.6", \ + "286.6, 286.6, 286.6, 296.3, 315.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("131.4, 131.4, 131.4, 138.8, 152.5", \ + "139.3, 139.3, 139.3, 146.8, 160.9", \ + "153.0, 153.0, 153.0, 160.6, 175.0", \ + "178.1, 178.1, 178.1, 185.3, 200.0", \ + "225.8, 225.8, 225.8, 233.2, 247.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("80.9, 80.9, 80.9, 85.6, 94.9", \ + "93.4, 93.4, 93.4, 98.1, 107.5", \ + "118.0, 118.0, 118.0, 122.8, 132.2", \ + "167.7, 167.7, 167.7, 172.7, 182.1", \ + "267.8, 267.8, 267.8, 272.7, 282.7"); + } + } + timing (maxd_q_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("90.6, 90.6, 90.6, 98.1, 111.8", \ + "96.9, 96.9, 96.9, 104.3, 118.3", \ + "100.1, 100.1, 100.1, 107.7, 122.0", \ + "92.8, 92.8, 92.8, 100.6, 115.3", \ + "62.7, 62.7, 62.7, 70.6, 85.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("69.6, 69.6, 69.6, 79.3, 98.3", \ + "78.7, 78.7, 78.7, 88.4, 107.4", \ + "95.9, 95.9, 95.9, 105.6, 124.8", \ + "127.6, 127.6, 127.6, 137.4, 156.7", \ + "188.1, 188.1, 188.1, 197.8, 217.3"); + } + cell_fall (inslew_load_5x5__0) { + values ("135.0, 135.0, 135.0, 142.3, 156.0", \ + "149.3, 149.3, 149.3, 156.7, 170.7", \ + "174.8, 174.8, 174.8, 182.4, 196.8", \ + "219.0, 219.0, 219.0, 226.3, 241.0", \ + "299.5, 299.5, 299.5, 306.9, 321.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("77.3, 77.3, 77.3, 82.0, 91.3", \ + "89.6, 89.6, 89.6, 94.3, 103.6", \ + "114.8, 114.8, 114.8, 119.5, 129.0", \ + "163.7, 163.7, 163.7, 168.7, 178.1", \ + "261.3, 261.3, 261.3, 266.2, 276.2"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("75.2, 75.2, 75.2, 82.5, 95.7", \ + "81.1, 81.1, 81.1, 88.5, 102.0", \ + "84.1, 84.1, 84.1, 91.6, 105.7", \ + "79.1, 79.1, 79.1, 86.8, 101.3", \ + "58.0, 58.0, 58.0, 65.9, 81.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("53.6, 53.6, 53.6, 63.2, 82.1", \ + "63.5, 63.5, 63.5, 73.2, 92.1", \ + "81.8, 81.8, 81.8, 91.5, 110.6", \ + "115.8, 115.8, 115.8, 125.6, 144.9", \ + "181.3, 181.3, 181.3, 191.1, 210.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("98.0, 98.0, 98.0, 105.2, 118.0", \ + "111.1, 111.1, 111.1, 118.4, 131.7", \ + "131.0, 131.0, 131.0, 138.5, 152.5", \ + "164.2, 164.2, 164.2, 171.7, 186.2", \ + "224.3, 224.3, 224.3, 231.6, 246.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("55.9, 55.9, 55.9, 60.6, 69.7", \ + "67.8, 67.8, 67.8, 72.5, 81.7", \ + "90.3, 90.3, 90.3, 95.0, 104.3", \ + "134.7, 134.7, 134.7, 139.6, 149.0", \ + "222.5, 222.5, 222.5, 227.5, 237.3"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("101.6, 101.6, 101.6, 109.1, 123.2", \ + "106.7, 106.7, 106.7, 114.2, 128.4", \ + "110.6, 110.6, 110.6, 118.3, 132.7", \ + "108.3, 108.3, 108.3, 116.2, 131.1", \ + "92.1, 92.1, 92.1, 100.1, 115.5"); + } + rise_transition (inslew_load_5x5__0) { + values ("81.6, 81.6, 81.6, 91.4, 110.4", \ + "91.5, 91.5, 91.5, 101.2, 120.4", \ + "110.6, 110.6, 110.6, 120.4, 139.6", \ + "147.8, 147.8, 147.8, 157.5, 176.9", \ + "220.3, 220.3, 220.3, 230.0, 249.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("170.1, 170.1, 170.1, 177.6, 191.8", \ + "183.0, 183.0, 183.0, 190.7, 205.0", \ + "205.3, 205.3, 205.3, 212.7, 227.4", \ + "246.6, 246.6, 246.6, 253.9, 268.4", \ + "326.1, 326.1, 326.1, 333.5, 348.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("99.9, 99.9, 99.9, 104.6, 114.0", \ + "114.6, 114.6, 114.6, 119.3, 128.8", \ + "142.1, 142.1, 142.1, 147.0, 156.4", \ + "197.0, 197.0, 197.0, 202.0, 211.7", \ + "307.8, 307.8, 307.8, 312.8, 322.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("101.6, 101.6, 101.6, 109.1, 123.2", \ + "106.7, 106.7, 106.7, 114.2, 128.4", \ + "110.6, 110.6, 110.6, 118.3, 132.7", \ + "108.3, 108.3, 108.3, 116.2, 131.1", \ + "92.1, 92.1, 92.1, 100.1, 115.5"); + } + rise_transition (inslew_load_5x5__0) { + values ("81.6, 81.6, 81.6, 91.4, 110.4", \ + "91.5, 91.5, 91.5, 101.2, 120.4", \ + "110.6, 110.6, 110.6, 120.4, 139.6", \ + "147.8, 147.8, 147.8, 157.5, 176.9", \ + "220.3, 220.3, 220.3, 230.0, 249.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("170.1, 170.1, 170.1, 177.6, 191.8", \ + "183.0, 183.0, 183.0, 190.7, 205.0", \ + "205.3, 205.3, 205.3, 212.7, 227.4", \ + "246.6, 246.6, 246.6, 253.9, 268.4", \ + "326.1, 326.1, 326.1, 333.5, 348.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("99.9, 99.9, 99.9, 104.6, 114.0", \ + "114.6, 114.6, 114.6, 119.3, 128.8", \ + "142.1, 142.1, 142.1, 147.0, 156.4", \ + "197.0, 197.0, 197.0, 202.0, 211.7", \ + "307.8, 307.8, 307.8, 312.8, 322.7"); + } + } + timing (maxd_q_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__0) { + values ("139.5, 139.5, 139.5, 147.0, 161.0", \ + "151.9, 151.9, 151.9, 159.5, 173.6", \ + "170.3, 170.3, 170.3, 177.9, 192.2", \ + "200.2, 200.2, 200.2, 207.9, 222.6", \ + "252.2, 252.2, 252.2, 260.1, 275.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("77.7, 77.7, 77.7, 87.4, 106.5", \ + "85.0, 85.0, 85.0, 94.7, 113.8", \ + "99.1, 99.1, 99.1, 108.9, 128.1", \ + "126.6, 126.6, 126.6, 136.3, 155.7", \ + "180.4, 180.4, 180.4, 190.2, 209.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("223.8, 223.8, 223.8, 231.4, 245.8", \ + "230.9, 230.9, 230.9, 238.5, 252.9", \ + "237.1, 237.1, 237.1, 244.6, 259.2", \ + "243.5, 243.5, 243.5, 250.8, 265.5", \ + "250.8, 250.8, 250.8, 258.1, 272.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("113.9, 113.9, 113.9, 118.6, 128.1", \ + "120.4, 120.4, 120.4, 125.1, 134.6", \ + "131.2, 131.2, 131.2, 136.1, 145.5", \ + "151.5, 151.5, 151.5, 156.4, 165.9", \ + "190.5, 190.5, 190.5, 195.5, 205.1"); + } + } + timing (maxd_q_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__0) { + values ("136.4, 136.4, 136.4, 143.9, 157.8", \ + "148.1, 148.1, 148.1, 155.6, 169.7", \ + "163.8, 163.8, 163.8, 171.4, 185.6", \ + "185.0, 185.0, 185.0, 192.8, 207.3", \ + "215.4, 215.4, 215.4, 223.2, 238.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("75.9, 75.9, 75.9, 85.6, 104.6", \ + "82.1, 82.1, 82.1, 91.8, 110.9", \ + "93.4, 93.4, 93.4, 103.2, 122.4", \ + "114.6, 114.6, 114.6, 124.4, 143.7", \ + "155.0, 155.0, 155.0, 164.8, 184.2"); + } + cell_fall (inslew_load_5x5__0) { + values ("156.7, 156.7, 156.7, 164.0, 177.5", \ + "164.4, 164.4, 164.4, 171.7, 185.4", \ + "171.2, 171.2, 171.2, 178.6, 192.5", \ + "179.9, 179.9, 179.9, 187.4, 201.6", \ + "190.0, 190.0, 190.0, 197.5, 212.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("72.5, 72.5, 72.5, 77.3, 86.4", \ + "77.4, 77.4, 77.4, 82.2, 91.4", \ + "84.7, 84.7, 84.7, 89.4, 98.7", \ + "99.2, 99.2, 99.2, 103.9, 113.3", \ + "127.7, 127.7, 127.7, 132.6, 142.0"); + } + } + internal_power (energy_pos_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__0) { + values ("494.6, 494.6, 494.6, 532.1, 607.0", \ + "557.8, 557.8, 557.8, 595.2, 670.2", \ + "684.7, 684.7, 684.7, 722.1, 797.1", \ + "938.0, 938.0, 938.0, 975.5, 1050.4", \ + "1445.3, 1445.3, 1445.3, 1482.8, 1557.7"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("571.4, 571.4, 571.4, 608.8, 683.8", \ + "654.6, 654.6, 654.6, 692.1, 767.0", \ + "819.6, 819.6, 819.6, 857.0, 932.0", \ + "1151.8, 1151.8, 1151.8, 1189.3, 1264.2", \ + "1819.4, 1819.4, 1819.4, 1856.9, 1931.8"); + } + } + internal_power (energy_pos_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__0) { + values ("351.9, 351.9, 351.9, 389.4, 464.3", \ + "387.9, 387.9, 387.9, 425.3, 500.3", \ + "457.5, 457.5, 457.5, 494.9, 569.9", \ + "589.8, 589.8, 589.8, 627.2, 702.2", \ + "846.6, 846.6, 846.6, 884.0, 959.0"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("468.6, 468.6, 468.6, 506.1, 581.0", \ + "535.9, 535.9, 535.9, 573.3, 648.3", \ + "672.6, 672.6, 672.6, 710.1, 785.0", \ + "941.6, 941.6, 941.6, 979.1, 1054.0", \ + "1479.1, 1479.1, 1479.1, 1516.6, 1591.5"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("313.6, 313.6, 313.6, 351.1, 426.0", \ + "356.4, 356.4, 356.4, 393.9, 468.8", \ + "438.2, 438.2, 438.2, 475.7, 550.6", \ + "596.4, 596.4, 596.4, 633.8, 708.8", \ + "906.2, 906.2, 906.2, 943.7, 1018.6"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("395.2, 395.2, 395.2, 432.7, 507.6", \ + "466.5, 466.5, 466.5, 504.0, 578.9", \ + "604.7, 604.7, 604.7, 642.2, 717.1", \ + "879.6, 879.6, 879.6, 917.1, 992.0", \ + "1426.1, 1426.1, 1426.1, 1463.5, 1538.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("419.8, 419.8, 419.8, 457.3, 532.2", \ + "462.9, 462.9, 462.9, 500.3, 575.3", \ + "547.7, 547.7, 547.7, 585.1, 660.1", \ + "714.8, 714.8, 714.8, 752.3, 827.2", \ + "1044.5, 1044.5, 1044.5, 1081.9, 1156.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("601.9, 601.9, 601.9, 639.4, 714.3", \ + "683.8, 683.8, 683.8, 721.3, 796.2", \ + "841.2, 841.2, 841.2, 878.7, 953.6", \ + "1155.6, 1155.6, 1155.6, 1193.1, 1268.0", \ + "1787.8, 1787.8, 1787.8, 1825.2, 1900.2"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("419.8, 419.8, 419.8, 457.3, 532.2", \ + "462.9, 462.9, 462.9, 500.3, 575.3", \ + "547.7, 547.7, 547.7, 585.1, 660.1", \ + "714.8, 714.8, 714.8, 752.3, 827.2", \ + "1044.5, 1044.5, 1044.5, 1081.9, 1156.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("601.9, 601.9, 601.9, 639.4, 714.3", \ + "683.8, 683.8, 683.8, 721.3, 796.2", \ + "841.2, 841.2, 841.2, 878.7, 953.6", \ + "1155.6, 1155.6, 1155.6, 1193.1, 1268.0", \ + "1787.8, 1787.8, 1787.8, 1825.2, 1900.2"); + } + } + internal_power (energy_neg_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__0) { + values ("552.6, 552.6, 552.6, 590.1, 665.0", \ + "616.7, 616.7, 616.7, 654.2, 729.1", \ + "742.4, 742.4, 742.4, 779.9, 854.8", \ + "991.1, 991.1, 991.1, 1028.6, 1103.5", \ + "1485.0, 1485.0, 1485.0, 1522.5, 1597.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("766.8, 766.8, 766.8, 804.3, 879.2", \ + "821.0, 821.0, 821.0, 858.5, 933.4", \ + "919.9, 919.9, 919.9, 957.4, 1032.3", \ + "1110.8, 1110.8, 1110.8, 1148.3, 1223.2", \ + "1486.6, 1486.6, 1486.6, 1524.1, 1599.0"); + } + } + internal_power (energy_neg_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__0) { + values ("460.6, 460.6, 460.6, 498.1, 573.0", \ + "511.0, 511.0, 511.0, 548.5, 623.4", \ + "608.3, 608.3, 608.3, 645.8, 720.7", \ + "798.7, 798.7, 798.7, 836.2, 911.1", \ + "1173.9, 1173.9, 1173.9, 1211.4, 1286.3"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("520.2, 520.2, 520.2, 557.6, 632.6", \ + "563.5, 563.5, 563.5, 601.0, 675.9", \ + "639.9, 639.9, 639.9, 677.4, 752.3", \ + "792.0, 792.0, 792.0, 829.5, 904.4", \ + "1094.0, 1094.0, 1094.0, 1131.4, 1206.4"); + } + } + } + } + + cell (mx3_x4) { + area : 0.0 ; + cell_leakage_power : 7 ; + leakage_power () { + when : "(cmd0 & cmd1 & i1)" ; + value : 13 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i1))" ; + value : 15 ; + } + leakage_power () { + when : "((cmd0 ^ cmd1) & i0 & i2)" ; + value : 7.2 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i0) & i2) | (!(cmd0) & cmd1 & i0 & !(i2)))" ; + value : 6.9 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i2)) | (!(cmd0) & cmd1 & !(i0)))" ; + value : 8.9 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & i1)" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & !(i1))" ; + value : 1.2 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & !(i0))" ; + value : 3.2 ; + } + pin (i2) { + direction : input ; + capacitance : 2.95 ; + } + pin (i1) { + direction : input ; + capacitance : 3.03 ; + } + pin (i0) { + direction : input ; + capacitance : 3.15 ; + } + pin (cmd1) { + direction : input ; + capacitance : 5.64 ; + } + pin (cmd0) { + direction : input ; + capacitance : 5.06 ; + } + pin (q) { + function : "((i0 & ((i2 & (!(cmd0) | i1 | !(cmd1))) | !(cmd0) | (i1 & cmd1))) | (i2 & cmd0 & (i1 | !(cmd1))) | (cmd0 & i1 & cmd1))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("141.0, 141.0, 141.0, 147.2, 159.0", \ + "146.9, 146.9, 146.9, 153.1, 165.1", \ + "156.1, 156.1, 156.1, 162.4, 174.5", \ + "169.8, 169.8, 169.8, 176.2, 188.6", \ + "190.6, 190.6, 190.6, 196.8, 209.4"); + } + rise_transition (inslew_load_5x5__1) { + values ("117.5, 117.5, 117.5, 125.3, 140.7", \ + "130.1, 130.1, 130.1, 137.9, 153.3", \ + "155.7, 155.7, 155.7, 163.4, 178.9", \ + "207.5, 207.5, 207.5, 215.2, 230.6", \ + "311.0, 311.0, 311.0, 318.8, 334.2"); + } + cell_fall (inslew_load_5x5__1) { + values ("164.8, 164.8, 164.8, 170.9, 182.5", \ + "173.4, 173.4, 173.4, 179.4, 191.1", \ + "188.6, 188.6, 188.6, 194.2, 206.1", \ + "216.1, 216.1, 216.1, 221.8, 233.0", \ + "268.1, 268.1, 268.1, 273.8, 285.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("103.7, 103.7, 103.7, 107.4, 114.7", \ + "116.6, 116.6, 116.6, 120.3, 127.6", \ + "141.8, 141.8, 141.8, 145.6, 153.0", \ + "193.0, 193.0, 193.0, 196.8, 204.5", \ + "296.7, 296.7, 296.7, 300.6, 308.4"); + } + } + timing (maxd_q_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("119.6, 119.6, 119.6, 125.8, 137.3", \ + "128.2, 128.2, 128.2, 134.4, 146.0", \ + "136.1, 136.1, 136.1, 142.3, 154.2", \ + "135.2, 135.2, 135.2, 141.5, 153.7", \ + "112.4, 112.4, 112.4, 118.8, 131.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("92.2, 92.2, 92.2, 100.0, 115.3", \ + "101.1, 101.1, 101.1, 108.9, 124.2", \ + "118.9, 118.9, 118.9, 126.6, 142.0", \ + "152.0, 152.0, 152.0, 159.7, 175.2", \ + "214.4, 214.4, 214.4, 222.1, 237.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("186.9, 186.9, 186.9, 192.9, 204.6", \ + "202.2, 202.2, 202.2, 208.2, 219.9", \ + "230.5, 230.5, 230.5, 236.2, 248.0", \ + "279.1, 279.1, 279.1, 284.8, 295.9", \ + "365.6, 365.6, 365.6, 371.3, 382.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("111.2, 111.2, 111.2, 114.8, 122.1", \ + "123.5, 123.5, 123.5, 127.2, 134.5", \ + "148.8, 148.8, 148.8, 152.7, 160.0", \ + "200.1, 200.1, 200.1, 203.9, 211.7", \ + "300.6, 300.6, 300.6, 304.4, 312.2"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("97.6, 97.6, 97.6, 103.6, 114.9", \ + "105.9, 105.9, 105.9, 111.9, 123.4", \ + "112.9, 112.9, 112.9, 119.1, 130.7", \ + "113.1, 113.1, 113.1, 119.3, 131.3", \ + "97.3, 97.3, 97.3, 103.6, 116.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("68.9, 68.9, 68.9, 76.6, 91.8", \ + "78.6, 78.6, 78.6, 86.4, 101.6", \ + "97.5, 97.5, 97.5, 105.3, 120.7", \ + "132.9, 132.9, 132.9, 140.6, 156.1", \ + "200.2, 200.2, 200.2, 207.9, 223.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("131.6, 131.6, 131.6, 137.6, 148.8", \ + "146.2, 146.2, 146.2, 152.2, 163.7", \ + "169.0, 169.0, 169.0, 175.0, 186.8", \ + "206.7, 206.7, 206.7, 212.3, 224.0", \ + "272.4, 272.4, 272.4, 278.1, 289.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("78.2, 78.2, 78.2, 81.9, 89.1", \ + "89.9, 89.9, 89.9, 93.6, 101.0", \ + "113.3, 113.3, 113.3, 116.9, 124.2", \ + "159.4, 159.4, 159.4, 163.3, 170.7", \ + "250.8, 250.8, 250.8, 254.7, 262.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("129.9, 129.9, 129.9, 136.1, 147.8", \ + "136.2, 136.2, 136.2, 142.5, 154.2", \ + "142.9, 142.9, 142.9, 149.2, 161.2", \ + "145.0, 145.0, 145.0, 151.4, 163.6", \ + "133.9, 133.9, 133.9, 140.3, 152.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("104.2, 104.2, 104.2, 112.0, 127.3", \ + "113.7, 113.7, 113.7, 121.4, 136.8", \ + "133.0, 133.0, 133.0, 140.8, 156.2", \ + "171.1, 171.1, 171.1, 178.9, 194.3", \ + "245.2, 245.2, 245.2, 252.9, 268.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("222.5, 222.5, 222.5, 228.3, 240.1", \ + "236.3, 236.3, 236.3, 242.0, 253.7", \ + "260.1, 260.1, 260.1, 265.7, 277.2", \ + "304.7, 304.7, 304.7, 310.3, 321.5", \ + "388.5, 388.5, 388.5, 394.2, 405.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("133.9, 133.9, 133.9, 137.7, 145.1", \ + "148.9, 148.9, 148.9, 152.9, 160.2", \ + "177.3, 177.3, 177.3, 181.1, 188.7", \ + "233.9, 233.9, 233.9, 237.7, 245.5", \ + "348.5, 348.5, 348.5, 352.4, 360.1"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("129.9, 129.9, 129.9, 136.1, 147.8", \ + "136.2, 136.2, 136.2, 142.5, 154.2", \ + "142.9, 142.9, 142.9, 149.2, 161.2", \ + "145.0, 145.0, 145.0, 151.4, 163.6", \ + "133.9, 133.9, 133.9, 140.3, 152.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("104.2, 104.2, 104.2, 112.0, 127.3", \ + "113.7, 113.7, 113.7, 121.4, 136.8", \ + "133.0, 133.0, 133.0, 140.8, 156.2", \ + "171.1, 171.1, 171.1, 178.9, 194.3", \ + "245.2, 245.2, 245.2, 252.9, 268.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("222.5, 222.5, 222.5, 228.3, 240.1", \ + "236.3, 236.3, 236.3, 242.0, 253.7", \ + "260.1, 260.1, 260.1, 265.7, 277.2", \ + "304.7, 304.7, 304.7, 310.3, 321.5", \ + "388.5, 388.5, 388.5, 394.2, 405.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("133.9, 133.9, 133.9, 137.7, 145.1", \ + "148.9, 148.9, 148.9, 152.9, 160.2", \ + "177.3, 177.3, 177.3, 181.1, 188.7", \ + "233.9, 233.9, 233.9, 237.7, 245.5", \ + "348.5, 348.5, 348.5, 352.4, 360.1"); + } + } + timing (maxd_q_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("160.4, 160.4, 160.4, 166.6, 178.1", \ + "173.4, 173.4, 173.4, 179.6, 191.2", \ + "193.0, 193.0, 193.0, 199.2, 211.0", \ + "224.9, 224.9, 224.9, 231.2, 243.3", \ + "279.6, 279.6, 279.6, 286.0, 298.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("92.5, 92.5, 92.5, 100.2, 115.6", \ + "99.8, 99.8, 99.8, 107.6, 123.0", \ + "113.9, 113.9, 113.9, 121.7, 137.0", \ + "141.8, 141.8, 141.8, 149.5, 165.0", \ + "196.7, 196.7, 196.7, 204.4, 219.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("275.6, 275.6, 275.6, 281.2, 293.0", \ + "282.7, 282.7, 282.7, 288.3, 300.0", \ + "289.4, 289.4, 289.4, 295.0, 306.6", \ + "296.2, 296.2, 296.2, 301.8, 313.1", \ + "304.9, 304.9, 304.9, 310.6, 321.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("147.6, 147.6, 147.6, 151.5, 158.9", \ + "154.4, 154.4, 154.4, 158.3, 165.7", \ + "165.6, 165.6, 165.6, 169.5, 177.0", \ + "186.5, 186.5, 186.5, 190.4, 198.1", \ + "227.0, 227.0, 227.0, 230.9, 238.7"); + } + } + timing (maxd_q_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("166.8, 166.8, 166.8, 173.0, 184.6", \ + "179.9, 179.9, 179.9, 186.1, 197.7", \ + "198.3, 198.3, 198.3, 204.5, 216.3", \ + "224.0, 224.0, 224.0, 230.3, 242.3", \ + "260.2, 260.2, 260.2, 266.5, 278.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("98.4, 98.4, 98.4, 106.2, 121.6", \ + "104.4, 104.4, 104.4, 112.2, 127.6", \ + "116.1, 116.1, 116.1, 123.9, 139.3", \ + "138.2, 138.2, 138.2, 145.9, 161.3", \ + "180.0, 180.0, 180.0, 187.7, 203.2"); + } + cell_fall (inslew_load_5x5__1) { + values ("208.1, 208.1, 208.1, 214.1, 225.8", \ + "216.0, 216.0, 216.0, 222.0, 233.7", \ + "223.5, 223.5, 223.5, 229.5, 241.2", \ + "233.9, 233.9, 233.9, 239.7, 251.5", \ + "246.8, 246.8, 246.8, 252.4, 264.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("106.3, 106.3, 106.3, 109.9, 117.2", \ + "111.2, 111.2, 111.2, 114.9, 122.2", \ + "118.5, 118.5, 118.5, 122.2, 129.5", \ + "133.1, 133.1, 133.1, 136.9, 144.2", \ + "162.0, 162.0, 162.0, 165.9, 173.4"); + } + } + internal_power (energy_pos_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__1) { + values ("942.2, 942.2, 942.2, 1001.8, 1121.0", \ + "1038.8, 1038.8, 1038.8, 1098.4, 1217.6", \ + "1234.4, 1234.4, 1234.4, 1294.0, 1413.1", \ + "1629.7, 1629.7, 1629.7, 1689.3, 1808.5", \ + "2421.4, 2421.4, 2421.4, 2481.0, 2600.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1091.2, 1091.2, 1091.2, 1150.8, 1269.9", \ + "1219.9, 1219.9, 1219.9, 1279.5, 1398.7", \ + "1473.8, 1473.8, 1473.8, 1533.4, 1652.6", \ + "1988.0, 1988.0, 1988.0, 2047.6, 2166.8", \ + "3026.3, 3026.3, 3026.3, 3085.9, 3205.1"); + } + } + internal_power (energy_pos_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__1) { + values ("730.8, 730.8, 730.8, 790.4, 909.6", \ + "790.5, 790.5, 790.5, 850.1, 969.3", \ + "909.5, 909.5, 909.5, 969.1, 1088.3", \ + "1135.1, 1135.1, 1135.1, 1194.7, 1313.9", \ + "1566.2, 1566.2, 1566.2, 1625.8, 1745.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1054.5, 1054.5, 1054.5, 1114.1, 1233.3", \ + "1164.4, 1164.4, 1164.4, 1224.0, 1343.1", \ + "1389.2, 1389.2, 1389.2, 1448.8, 1568.0", \ + "1843.6, 1843.6, 1843.6, 1903.2, 2022.4", \ + "2737.7, 2737.7, 2737.7, 2797.3, 2916.5"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("609.5, 609.5, 609.5, 669.0, 788.2", \ + "678.2, 678.2, 678.2, 737.8, 857.0", \ + "812.9, 812.9, 812.9, 872.5, 991.7", \ + "1069.9, 1069.9, 1069.9, 1129.5, 1248.7", \ + "1566.5, 1566.5, 1566.5, 1626.1, 1745.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("825.8, 825.8, 825.8, 885.4, 1004.6", \ + "936.9, 936.9, 936.9, 996.5, 1115.6", \ + "1157.6, 1157.6, 1157.6, 1217.2, 1336.4", \ + "1597.9, 1597.9, 1597.9, 1657.5, 1776.7", \ + "2472.8, 2472.8, 2472.8, 2532.4, 2651.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("830.9, 830.9, 830.9, 890.5, 1009.7", \ + "898.6, 898.6, 898.6, 958.2, 1077.4", \ + "1036.5, 1036.5, 1036.5, 1096.1, 1215.3", \ + "1309.1, 1309.1, 1309.1, 1368.7, 1487.9", \ + "1843.5, 1843.5, 1843.5, 1903.1, 2022.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1267.4, 1267.4, 1267.4, 1327.0, 1446.2", \ + "1402.4, 1402.4, 1402.4, 1462.0, 1581.2", \ + "1660.0, 1660.0, 1660.0, 1719.6, 1838.8", \ + "2175.3, 2175.3, 2175.3, 2234.9, 2354.1", \ + "3216.5, 3216.5, 3216.5, 3276.1, 3395.3"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("830.9, 830.9, 830.9, 890.5, 1009.7", \ + "898.6, 898.6, 898.6, 958.2, 1077.4", \ + "1036.5, 1036.5, 1036.5, 1096.1, 1215.3", \ + "1309.1, 1309.1, 1309.1, 1368.7, 1487.9", \ + "1843.5, 1843.5, 1843.5, 1903.1, 2022.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1267.4, 1267.4, 1267.4, 1327.0, 1446.2", \ + "1402.4, 1402.4, 1402.4, 1462.0, 1581.2", \ + "1660.0, 1660.0, 1660.0, 1719.6, 1838.8", \ + "2175.3, 2175.3, 2175.3, 2234.9, 2354.1", \ + "3216.5, 3216.5, 3216.5, 3276.1, 3395.3"); + } + } + internal_power (energy_neg_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__1) { + values ("908.1, 908.1, 908.1, 967.7, 1086.9", \ + "992.5, 992.5, 992.5, 1052.1, 1171.3", \ + "1156.0, 1156.0, 1156.0, 1215.6, 1334.8", \ + "1480.9, 1480.9, 1480.9, 1540.5, 1659.7", \ + "2126.2, 2126.2, 2126.2, 2185.8, 2305.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1476.5, 1476.5, 1476.5, 1536.1, 1655.3", \ + "1554.6, 1554.6, 1554.6, 1614.2, 1733.4", \ + "1693.5, 1693.5, 1693.5, 1753.1, 1872.3", \ + "1959.0, 1959.0, 1959.0, 2018.6, 2137.8", \ + "2479.3, 2479.3, 2479.3, 2538.9, 2658.1"); + } + } + internal_power (energy_neg_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__1) { + values ("856.1, 856.1, 856.1, 915.7, 1034.9", \ + "922.1, 922.1, 922.1, 981.7, 1100.9", \ + "1052.0, 1052.0, 1052.0, 1111.6, 1230.8", \ + "1304.2, 1304.2, 1304.2, 1363.8, 1483.0", \ + "1796.4, 1796.4, 1796.4, 1856.0, 1975.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1088.6, 1088.6, 1088.6, 1148.2, 1267.4", \ + "1149.2, 1149.2, 1149.2, 1208.8, 1328.0", \ + "1251.0, 1251.0, 1251.0, 1310.5, 1429.7", \ + "1453.5, 1453.5, 1453.5, 1513.1, 1632.3", \ + "1857.0, 1857.0, 1857.0, 1916.6, 2035.7"); + } + } + } + } + + cell (na2_x1) { + area : 0.0 ; + cell_leakage_power : 0.13 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.52 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 8.5e-05 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 6.8e-05 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 1.4e-06 ; + } + pin (i1) { + direction : input ; + capacitance : 4.39 ; + } + pin (i0) { + direction : input ; + capacitance : 4.39 ; + } + pin (nq) { + function : "(!(i0) | !(i1))" ; + direction : output ; + capacitance : 3.07 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__9) { + values ("39.3, 39.3, 39.3, 50.3, 70.7", \ + "60.2, 60.2, 60.2, 71.9, 93.8", \ + "97.7, 97.7, 97.7, 110.0, 133.5", \ + "170.1, 170.1, 170.1, 182.9, 207.6", \ + "313.6, 313.6, 313.6, 326.6, 352.2"); + } + rise_transition (inslew_load_5x5__9) { + values ("67.4, 67.4, 67.4, 85.3, 120.8", \ + "115.2, 115.2, 115.2, 133.3, 169.1", \ + "205.0, 205.0, 205.0, 223.2, 259.4", \ + "381.3, 381.3, 381.3, 399.7, 436.2", \ + "732.2, 732.2, 732.2, 750.7, 787.4"); + } + cell_fall (inslew_load_5x5__9) { + values ("9.0, 9.0, 9.0, 15.4, 27.0", \ + "-0.4, -0.4, -0.4, 7.2, 20.9", \ + "-22.5, -22.5, -22.5, -13.3, 3.1", \ + "-69.5, -69.5, -69.5, -58.9, -39.4", \ + "-165.5, -165.5, -165.5, -153.8, -131.9"); + } + fall_transition (inslew_load_5x5__9) { + values ("23.9, 23.9, 23.9, 30.6, 43.7", \ + "32.8, 32.8, 32.8, 39.9, 53.4", \ + "49.7, 49.7, 49.7, 57.2, 71.6", \ + "82.4, 82.4, 82.4, 90.4, 105.8", \ + "147.0, 147.0, 147.0, 155.4, 171.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__9) { + values ("26.8, 26.8, 26.8, 38.9, 60.3", \ + "42.3, 42.3, 42.3, 55.1, 78.4", \ + "69.9, 69.9, 69.9, 83.3, 108.4", \ + "123.3, 123.3, 123.3, 137.0, 163.5", \ + "228.9, 228.9, 228.9, 242.8, 270.2"); + } + rise_transition (inslew_load_5x5__9) { + values ("48.6, 48.6, 48.6, 66.9, 102.6", \ + "89.3, 89.3, 89.3, 107.7, 143.9", \ + "165.8, 165.8, 165.8, 184.3, 221.0", \ + "316.1, 316.1, 316.1, 334.8, 371.8", \ + "615.3, 615.3, 615.3, 634.0, 671.3"); + } + cell_fall (inslew_load_5x5__9) { + values ("5.0, 5.0, 5.0, 13.3, 26.8", \ + "-3.0, -3.0, -3.0, 6.9, 23.5", \ + "-20.7, -20.7, -20.7, -9.2, 10.6", \ + "-57.2, -57.2, -57.2, -44.6, -21.7", \ + "-131.1, -131.1, -131.1, -117.7, -92.6"); + } + fall_transition (inslew_load_5x5__9) { + values ("18.0, 18.0, 18.0, 25.3, 38.9", \ + "28.1, 28.1, 28.1, 35.9, 50.5", \ + "47.4, 47.4, 47.4, 55.8, 71.5", \ + "85.6, 85.6, 85.6, 94.4, 111.1", \ + "161.5, 161.5, 161.5, 170.6, 188.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__9) { + values ("143.0, 143.0, 143.0, 181.4, 258.2", \ + "218.1, 218.1, 218.1, 256.5, 333.2", \ + "368.2, 368.2, 368.2, 406.6, 483.4", \ + "668.5, 668.5, 668.5, 706.9, 783.6", \ + "1269.0, 1269.0, 1269.0, 1307.3, 1384.1"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("102.1, 102.1, 102.1, 140.5, 217.2", \ + "123.9, 123.9, 123.9, 162.2, 239.0", \ + "167.4, 167.4, 167.4, 205.7, 282.5", \ + "254.4, 254.4, 254.4, 292.8, 369.5", \ + "428.4, 428.4, 428.4, 466.8, 543.6"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__9) { + values ("99.2, 99.2, 99.2, 137.6, 214.3", \ + "161.0, 161.0, 161.0, 199.3, 276.1", \ + "284.6, 284.6, 284.6, 322.9, 399.7", \ + "531.8, 531.8, 531.8, 570.1, 646.9", \ + "1026.1, 1026.1, 1026.1, 1064.5, 1141.3"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("63.2, 63.2, 63.2, 101.6, 178.3", \ + "87.0, 87.0, 87.0, 125.4, 202.2", \ + "134.7, 134.7, 134.7, 173.1, 249.8", \ + "230.0, 230.0, 230.0, 268.3, 345.1", \ + "420.6, 420.6, 420.6, 458.9, 535.7"); + } + } + } + } + + cell (na2_x4) { + area : 0.0 ; + cell_leakage_power : 3.5 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 6.7 ; + } + leakage_power () { + when : "(!(i0) | !(i1))" ; + value : 0.26 ; + } + pin (i1) { + direction : input ; + capacitance : 3.48 ; + } + pin (i0) { + direction : input ; + capacitance : 3.90 ; + } + pin (nq) { + function : "(!(i1) | !(i0))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("107.9, 107.9, 107.9, 113.7, 124.3", \ + "127.9, 127.9, 127.9, 133.9, 144.7", \ + "159.5, 159.5, 159.5, 165.4, 176.8", \ + "214.2, 214.2, 214.2, 220.4, 231.9", \ + "316.2, 316.2, 316.2, 322.5, 334.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("43.7, 43.7, 43.7, 51.3, 66.3", \ + "53.4, 53.4, 53.4, 61.0, 76.1", \ + "70.3, 70.3, 70.3, 78.0, 93.1", \ + "102.2, 102.2, 102.2, 109.9, 125.2", \ + "164.0, 164.0, 164.0, 171.7, 187.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("75.1, 75.1, 75.1, 80.4, 90.2", \ + "73.9, 73.9, 73.9, 79.2, 89.1", \ + "65.4, 65.4, 65.4, 70.8, 80.8", \ + "40.8, 40.8, 40.8, 46.6, 56.5", \ + "-15.5, -15.5, -15.5, -9.6, 1.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("31.7, 31.7, 31.7, 35.3, 42.0", \ + "34.2, 34.2, 34.2, 37.8, 44.5", \ + "38.5, 38.5, 38.5, 42.1, 48.9", \ + "46.4, 46.4, 46.4, 50.0, 57.1", \ + "61.5, 61.5, 61.5, 65.1, 72.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("121.3, 121.3, 121.3, 127.3, 137.9", \ + "146.9, 146.9, 146.9, 152.9, 163.9", \ + "188.5, 188.5, 188.5, 194.6, 206.0", \ + "263.9, 263.9, 263.9, 270.1, 281.9", \ + "406.4, 406.4, 406.4, 412.7, 425.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("48.3, 48.3, 48.3, 55.9, 70.9", \ + "59.4, 59.4, 59.4, 67.1, 82.1", \ + "79.3, 79.3, 79.3, 87.0, 102.2", \ + "116.6, 116.6, 116.6, 124.4, 139.7", \ + "189.8, 189.8, 189.8, 197.4, 212.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("78.0, 78.0, 78.0, 83.3, 93.1", \ + "73.8, 73.8, 73.8, 79.1, 89.0", \ + "59.3, 59.3, 59.3, 64.7, 74.7", \ + "22.4, 22.4, 22.4, 28.1, 38.1", \ + "-59.8, -59.8, -59.8, -53.9, -43.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("32.8, 32.8, 32.8, 36.4, 43.1", \ + "34.8, 34.8, 34.8, 38.4, 45.1", \ + "38.5, 38.5, 38.5, 42.1, 48.9", \ + "45.2, 45.2, 45.2, 48.7, 55.8", \ + "57.8, 57.8, 57.8, 61.4, 68.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("600.9, 600.9, 600.9, 660.5, 779.7", \ + "728.2, 728.2, 728.2, 787.8, 907.0", \ + "968.9, 968.9, 968.9, 1028.5, 1147.7", \ + "1440.8, 1440.8, 1440.8, 1500.4, 1619.5", \ + "2375.0, 2375.0, 2375.0, 2434.6, 2553.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("549.5, 549.5, 549.5, 609.1, 728.3", \ + "596.0, 596.0, 596.0, 655.6, 774.8", \ + "684.1, 684.1, 684.1, 743.7, 862.9", \ + "853.8, 853.8, 853.8, 913.4, 1032.6", \ + "1186.8, 1186.8, 1186.8, 1246.4, 1365.6"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("673.4, 673.4, 673.4, 733.0, 852.2", \ + "825.5, 825.5, 825.5, 885.1, 1004.2", \ + "1115.2, 1115.2, 1115.2, 1174.8, 1294.0", \ + "1682.2, 1682.2, 1682.2, 1741.8, 1861.0", \ + "2808.2, 2808.2, 2808.2, 2867.8, 2987.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("592.0, 592.0, 592.0, 651.6, 770.8", \ + "630.9, 630.9, 630.9, 690.5, 809.7", \ + "706.7, 706.7, 706.7, 766.3, 885.5", \ + "851.4, 851.4, 851.4, 911.0, 1030.2", \ + "1134.0, 1134.0, 1134.0, 1193.6, 1312.8"); + } + } + } + } + + cell (na3_x1) { + area : 0.0 ; + cell_leakage_power : 0.11 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 0.78 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 0.00012 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 0.0001 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0))" ; + value : 9.7e-05 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 2.1e-06 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 2e-06 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 9.3e-07 ; + } + pin (i2) { + direction : input ; + capacitance : 4.74 ; + } + pin (i1) { + direction : input ; + capacitance : 4.74 ; + } + pin (i0) { + direction : input ; + capacitance : 4.85 ; + } + pin (nq) { + function : "((!(i0) | !(i1)) | !(i2))" ; + direction : output ; + capacitance : 4.54 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("59.0, 59.0, 59.0, 73.8, 102.3", \ + "87.3, 87.3, 87.3, 103.0, 133.1", \ + "136.8, 136.8, 136.8, 153.5, 185.5", \ + "231.5, 231.5, 231.5, 248.9, 282.7", \ + "418.2, 418.2, 418.2, 436.0, 471.1"); + } + rise_transition (inslew_load_5x5__10) { + values ("98.2, 98.2, 98.2, 124.4, 177.1", \ + "156.3, 156.3, 156.3, 182.6, 235.0", \ + "262.9, 262.9, 262.9, 289.4, 342.2", \ + "470.7, 470.7, 470.7, 497.4, 550.7", \ + "883.4, 883.4, 883.4, 910.3, 963.9"); + } + cell_fall (inslew_load_5x5__10) { + values ("15.6, 15.6, 15.6, 23.0, 37.1", \ + "5.1, 5.1, 5.1, 13.7, 29.6", \ + "-20.0, -20.0, -20.0, -9.6, 9.2", \ + "-75.7, -75.7, -75.7, -63.2, -40.5", \ + "-192.5, -192.5, -192.5, -178.0, -151.2"); + } + fall_transition (inslew_load_5x5__10) { + values ("35.7, 35.7, 35.7, 45.4, 64.7", \ + "42.9, 42.9, 42.9, 52.8, 72.1", \ + "56.5, 56.5, 56.5, 66.8, 86.8", \ + "82.4, 82.4, 82.4, 93.2, 114.3", \ + "132.5, 132.5, 132.5, 143.9, 166.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("46.6, 46.6, 46.6, 62.1, 91.1", \ + "69.1, 69.1, 69.1, 85.7, 116.8", \ + "108.0, 108.0, 108.0, 125.7, 159.2", \ + "182.2, 182.2, 182.2, 200.6, 236.3", \ + "328.4, 328.4, 328.4, 347.4, 384.5"); + } + rise_transition (inslew_load_5x5__10) { + values ("77.4, 77.4, 77.4, 103.8, 156.5", \ + "127.2, 127.2, 127.2, 153.8, 206.4", \ + "218.7, 218.7, 218.7, 245.6, 298.8", \ + "397.3, 397.3, 397.3, 424.3, 478.1", \ + "751.8, 751.8, 751.8, 779.0, 833.1"); + } + cell_fall (inslew_load_5x5__10) { + values ("13.1, 13.1, 13.1, 21.6, 36.8", \ + "4.3, 4.3, 4.3, 14.6, 32.5", \ + "-17.0, -17.0, -17.0, -4.6, 17.1", \ + "-63.9, -63.9, -63.9, -49.3, -23.2", \ + "-161.0, -161.0, -161.0, -144.7, -114.4"); + } + fall_transition (inslew_load_5x5__10) { + values ("28.9, 28.9, 28.9, 38.8, 58.3", \ + "37.4, 37.4, 37.4, 47.7, 67.7", \ + "53.3, 53.3, 53.3, 64.3, 85.2", \ + "83.9, 83.9, 83.9, 95.5, 117.7", \ + "144.1, 144.1, 144.1, 156.2, 179.7"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("32.4, 32.4, 32.4, 49.2, 79.2", \ + "49.9, 49.9, 49.9, 67.9, 100.4", \ + "80.1, 80.1, 80.1, 99.1, 134.4", \ + "137.6, 137.6, 137.6, 157.3, 195.0", \ + "251.0, 251.0, 251.0, 271.2, 310.5"); + } + rise_transition (inslew_load_5x5__10) { + values ("55.2, 55.2, 55.2, 81.9, 134.9", \ + "98.6, 98.6, 98.6, 125.5, 178.5", \ + "178.4, 178.4, 178.4, 205.6, 259.3", \ + "334.2, 334.2, 334.2, 361.7, 416.0", \ + "643.9, 643.9, 643.9, 671.5, 726.3"); + } + cell_fall (inslew_load_5x5__10) { + values ("7.7, 7.7, 7.7, 17.9, 34.8", \ + "-0.1, -0.1, -0.1, 12.4, 33.0", \ + "-18.4, -18.4, -18.4, -3.5, 21.5", \ + "-57.1, -57.1, -57.1, -40.3, -10.6", \ + "-136.0, -136.0, -136.0, -117.8, -84.2"); + } + fall_transition (inslew_load_5x5__10) { + values ("21.2, 21.2, 21.2, 31.6, 51.4", \ + "30.6, 30.6, 30.6, 41.7, 62.5", \ + "48.4, 48.4, 48.4, 60.1, 82.3", \ + "83.3, 83.3, 83.3, 95.6, 119.1", \ + "152.5, 152.5, 152.5, 165.2, 189.9"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__10) { + values ("222.9, 222.9, 222.9, 279.6, 393.2", \ + "313.9, 313.9, 313.9, 370.7, 484.2", \ + "496.1, 496.1, 496.1, 552.8, 666.3", \ + "860.3, 860.3, 860.3, 917.1, 1030.6", \ + "1588.8, 1588.8, 1588.8, 1645.5, 1759.1"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("175.1, 175.1, 175.1, 231.9, 345.4", \ + "193.8, 193.8, 193.8, 250.6, 364.1", \ + "231.2, 231.2, 231.2, 287.9, 401.5", \ + "305.9, 305.9, 305.9, 362.7, 476.2", \ + "455.4, 455.4, 455.4, 512.2, 625.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__10) { + values ("171.6, 171.6, 171.6, 228.3, 341.9", \ + "247.5, 247.5, 247.5, 304.3, 417.8", \ + "399.4, 399.4, 399.4, 456.1, 569.7", \ + "703.1, 703.1, 703.1, 759.9, 873.4", \ + "1310.5, 1310.5, 1310.5, 1367.3, 1480.8"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("129.2, 129.2, 129.2, 186.0, 299.5", \ + "151.0, 151.0, 151.0, 207.8, 321.3", \ + "194.6, 194.6, 194.6, 251.4, 364.9", \ + "281.8, 281.8, 281.8, 338.5, 452.1", \ + "456.1, 456.1, 456.1, 512.9, 626.4"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__10) { + values ("119.4, 119.4, 119.4, 176.2, 289.7", \ + "183.8, 183.8, 183.8, 240.6, 354.1", \ + "312.6, 312.6, 312.6, 369.4, 482.9", \ + "570.2, 570.2, 570.2, 627.0, 740.5", \ + "1085.5, 1085.5, 1085.5, 1142.2, 1255.7"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("82.8, 82.8, 82.8, 139.6, 253.1", \ + "107.1, 107.1, 107.1, 163.9, 277.4", \ + "155.8, 155.8, 155.8, 212.5, 326.1", \ + "253.0, 253.0, 253.0, 309.8, 423.3", \ + "447.5, 447.5, 447.5, 504.3, 617.8"); + } + } + } + } + + cell (na3_x4) { + area : 0.0 ; + cell_leakage_power : 4.3 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 8.4 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2))" ; + value : 0.26 ; + } + pin (i2) { + direction : input ; + capacitance : 4.03 ; + } + pin (i1) { + direction : input ; + capacitance : 4.42 ; + } + pin (i0) { + direction : input ; + capacitance : 4.35 ; + } + pin (nq) { + function : "(!(i1) | !(i0) | !(i2))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("115.7, 115.7, 115.7, 121.6, 132.2", \ + "140.8, 140.8, 140.8, 146.8, 157.8", \ + "179.7, 179.7, 179.7, 185.7, 197.0", \ + "247.7, 247.7, 247.7, 253.9, 265.6", \ + "375.3, 375.3, 375.3, 381.6, 393.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("45.6, 45.6, 45.6, 53.2, 68.2", \ + "56.7, 56.7, 56.7, 64.3, 79.4", \ + "75.6, 75.6, 75.6, 83.3, 98.4", \ + "110.6, 110.6, 110.6, 118.4, 133.7", \ + "178.9, 178.9, 178.9, 186.6, 202.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("75.2, 75.2, 75.2, 80.5, 90.3", \ + "72.0, 72.0, 72.0, 77.3, 87.2", \ + "59.0, 59.0, 59.0, 64.5, 74.4", \ + "25.3, 25.3, 25.3, 31.0, 40.9", \ + "-49.8, -49.8, -49.8, -43.9, -33.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("32.2, 32.2, 32.2, 35.8, 42.5", \ + "34.3, 34.3, 34.3, 37.9, 44.6", \ + "38.0, 38.0, 38.0, 41.5, 48.4", \ + "44.6, 44.6, 44.6, 48.1, 55.2", \ + "57.1, 57.1, 57.1, 60.7, 67.7"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("132.2, 132.2, 132.2, 138.2, 148.9", \ + "161.9, 161.9, 161.9, 167.9, 179.1", \ + "208.9, 208.9, 208.9, 215.0, 226.4", \ + "293.3, 293.3, 293.3, 299.6, 311.4", \ + "453.2, 453.2, 453.2, 459.5, 471.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("51.3, 51.3, 51.3, 58.9, 74.0", \ + "63.6, 63.6, 63.6, 71.2, 86.3", \ + "84.7, 84.7, 84.7, 92.4, 107.7", \ + "124.3, 124.3, 124.3, 132.0, 147.4", \ + "201.7, 201.7, 201.7, 209.3, 224.7"); + } + cell_fall (inslew_load_5x5__1) { + values ("81.4, 81.4, 81.4, 86.7, 96.6", \ + "76.4, 76.4, 76.4, 81.7, 91.7", \ + "59.8, 59.8, 59.8, 65.2, 75.2", \ + "17.8, 17.8, 17.8, 23.5, 33.4", \ + "-75.6, -75.6, -75.6, -69.7, -59.4"); + } + fall_transition (inslew_load_5x5__1) { + values ("33.8, 33.8, 33.8, 37.4, 44.1", \ + "35.6, 35.6, 35.6, 39.2, 46.0", \ + "38.9, 38.9, 38.9, 42.4, 49.3", \ + "44.7, 44.7, 44.7, 48.3, 55.4", \ + "55.5, 55.5, 55.5, 59.2, 66.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("147.1, 147.1, 147.1, 153.1, 164.1", \ + "182.2, 182.2, 182.2, 188.2, 199.5", \ + "239.5, 239.5, 239.5, 245.7, 257.1", \ + "343.8, 343.8, 343.8, 350.0, 362.1", \ + "543.4, 543.4, 543.4, 549.8, 562.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("56.7, 56.7, 56.7, 64.3, 79.4", \ + "70.4, 70.4, 70.4, 78.1, 93.2", \ + "94.5, 94.5, 94.5, 102.3, 117.5", \ + "140.1, 140.1, 140.1, 147.8, 163.2", \ + "229.3, 229.3, 229.3, 236.9, 252.2"); + } + cell_fall (inslew_load_5x5__1) { + values ("85.0, 85.0, 85.0, 90.3, 100.3", \ + "77.1, 77.1, 77.1, 82.5, 92.4", \ + "55.9, 55.9, 55.9, 61.4, 71.4", \ + "4.6, 4.6, 4.6, 10.3, 20.2", \ + "-108.4, -108.4, -108.4, -102.5, -92.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("35.3, 35.3, 35.3, 38.9, 45.7", \ + "36.8, 36.8, 36.8, 40.3, 47.1", \ + "39.5, 39.5, 39.5, 43.0, 49.9", \ + "44.4, 44.4, 44.4, 47.9, 55.0", \ + "53.4, 53.4, 53.4, 57.0, 64.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("641.8, 641.8, 641.8, 701.4, 820.5", \ + "789.1, 789.1, 789.1, 848.7, 967.9", \ + "1062.8, 1062.8, 1062.8, 1122.4, 1241.6", \ + "1595.0, 1595.0, 1595.0, 1654.6, 1773.8", \ + "2649.8, 2649.8, 2649.8, 2709.4, 2828.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("572.4, 572.4, 572.4, 632.0, 751.2", \ + "613.8, 613.8, 613.8, 673.4, 792.6", \ + "692.0, 692.0, 692.0, 751.6, 870.8", \ + "842.4, 842.4, 842.4, 902.0, 1021.2", \ + "1137.7, 1137.7, 1137.7, 1197.3, 1316.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("734.4, 734.4, 734.4, 794.0, 913.2", \ + "902.4, 902.4, 902.4, 962.0, 1081.2", \ + "1216.1, 1216.1, 1216.1, 1275.7, 1394.9", \ + "1826.9, 1826.9, 1826.9, 1886.5, 2005.7", \ + "3038.8, 3038.8, 3038.8, 3098.4, 3217.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("632.3, 632.3, 632.3, 691.9, 811.1", \ + "669.2, 669.2, 669.2, 728.8, 848.0", \ + "738.7, 738.7, 738.7, 798.3, 917.5", \ + "872.1, 872.1, 872.1, 931.7, 1050.9", \ + "1130.9, 1130.9, 1130.9, 1190.5, 1309.7"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("824.6, 824.6, 824.6, 884.2, 1003.4", \ + "1018.8, 1018.8, 1018.8, 1078.4, 1197.6", \ + "1383.7, 1383.7, 1383.7, 1443.3, 1562.5", \ + "2097.4, 2097.4, 2097.4, 2157.0, 2276.2", \ + "3512.2, 3512.2, 3512.2, 3571.8, 3691.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("691.0, 691.0, 691.0, 750.6, 869.8", \ + "721.2, 721.2, 721.2, 780.8, 900.0", \ + "779.9, 779.9, 779.9, 839.5, 958.7", \ + "892.3, 892.3, 892.3, 951.9, 1071.1", \ + "1110.3, 1110.3, 1110.3, 1169.9, 1289.1"); + } + } + } + } + + cell (na4_x1) { + area : 0.0 ; + cell_leakage_power : 2.2 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 19 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & i0)" ; + value : 0.00012 ; + } + leakage_power () { + when : "(i3 & !(i2) & i1 & i0)" ; + value : 0.0001 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & i0)" ; + value : 9.7e-05 ; + } + leakage_power () { + when : "(i3 & i2 & i1 & !(i0))" ; + value : 9.6e-05 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & i3)" ; + value : 2e-06 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3)) | (!(i0) & ((i1 & i2 & !(i3)) | (!(i1) & i2 & i3))))" ; + value : 2.1e-06 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))))" ; + value : 9.3e-07 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.8e-07 ; + } + pin (i3) { + direction : input ; + capacitance : 4.35 ; + } + pin (i2) { + direction : input ; + capacitance : 4.35 ; + } + pin (i1) { + direction : input ; + capacitance : 4.46 ; + } + pin (i0) { + direction : input ; + capacitance : 4.13 ; + } + pin (nq) { + function : "(((!(i0) | !(i3)) | !(i2)) | !(i1))" ; + direction : output ; + capacitance : 5.13 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("91.0, 91.0, 91.0, 113.4, 157.6", \ + "128.8, 128.8, 128.8, 152.1, 197.6", \ + "192.1, 192.1, 192.1, 216.7, 264.4", \ + "310.3, 310.3, 310.3, 336.0, 386.2", \ + "541.4, 541.4, 541.4, 567.9, 620.1"); + } + rise_transition (inslew_load_5x5__11) { + values ("168.8, 168.8, 168.8, 214.7, 307.9", \ + "248.7, 248.7, 248.7, 296.0, 387.0", \ + "390.0, 390.0, 390.0, 436.0, 527.8", \ + "661.3, 661.3, 661.3, 707.7, 800.0", \ + "1197.6, 1197.6, 1197.6, 1244.2, 1337.2"); + } + cell_fall (inslew_load_5x5__11) { + values ("24.2, 24.2, 24.2, 33.6, 52.1", \ + "12.9, 12.9, 12.9, 23.1, 42.7", \ + "-13.8, -13.8, -13.8, -1.8, 20.4", \ + "-74.6, -74.6, -74.6, -60.0, -33.3", \ + "-204.7, -204.7, -204.7, -187.2, -154.9"); + } + fall_transition (inslew_load_5x5__11) { + values ("53.8, 53.8, 53.8, 68.3, 97.4", \ + "59.8, 59.8, 59.8, 74.3, 102.9", \ + "71.5, 71.5, 71.5, 86.2, 115.0", \ + "93.6, 93.6, 93.6, 108.9, 138.7", \ + "135.6, 135.6, 135.6, 151.6, 182.9"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("76.7, 76.7, 76.7, 99.5, 144.0", \ + "109.6, 109.6, 109.6, 133.6, 179.7", \ + "164.4, 164.4, 164.4, 189.8, 238.5", \ + "266.4, 266.4, 266.4, 293.0, 344.6", \ + "465.7, 465.7, 465.7, 493.1, 547.0"); + } + rise_transition (inslew_load_5x5__11) { + values ("139.9, 139.9, 139.9, 186.1, 278.8", \ + "212.2, 212.2, 212.2, 258.2, 350.7", \ + "339.5, 339.5, 339.5, 385.8, 477.7", \ + "584.0, 584.0, 584.0, 630.6, 723.4", \ + "1067.3, 1067.3, 1067.3, 1114.2, 1207.7"); + } + cell_fall (inslew_load_5x5__11) { + values ("21.7, 21.7, 21.7, 31.7, 50.8", \ + "12.4, 12.4, 12.4, 23.9, 45.1", \ + "-11.4, -11.4, -11.4, 2.5, 27.5", \ + "-66.5, -66.5, -66.5, -49.4, -18.7", \ + "-184.4, -184.4, -184.4, -164.1, -127.0"); + } + fall_transition (inslew_load_5x5__11) { + values ("45.1, 45.1, 45.1, 59.7, 88.6", \ + "52.3, 52.3, 52.3, 67.0, 95.9", \ + "65.7, 65.7, 65.7, 80.9, 110.6", \ + "90.6, 90.6, 90.6, 106.6, 137.7", \ + "138.2, 138.2, 138.2, 155.2, 188.0"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("60.9, 60.9, 60.9, 84.4, 129.2", \ + "88.7, 88.7, 88.7, 113.6, 160.6", \ + "134.5, 134.5, 134.5, 161.0, 211.3", \ + "219.8, 219.8, 219.8, 247.6, 301.1", \ + "386.4, 386.4, 386.4, 415.1, 471.2"); + } + rise_transition (inslew_load_5x5__11) { + values ("109.3, 109.3, 109.3, 155.8, 247.8", \ + "173.7, 173.7, 173.7, 219.9, 312.8", \ + "287.0, 287.0, 287.0, 333.6, 426.0", \ + "504.7, 504.7, 504.7, 551.7, 645.1", \ + "935.3, 935.3, 935.3, 982.6, 1076.7"); + } + cell_fall (inslew_load_5x5__11) { + values ("17.0, 17.0, 17.0, 28.1, 48.2", \ + "8.9, 8.9, 8.9, 22.2, 45.4", \ + "-12.7, -12.7, -12.7, 3.6, 31.9", \ + "-62.0, -62.0, -62.0, -42.2, -7.5", \ + "-166.1, -166.1, -166.1, -143.2, -101.8"); + } + fall_transition (inslew_load_5x5__11) { + values ("35.6, 35.6, 35.6, 50.3, 79.6", \ + "43.8, 43.8, 43.8, 59.0, 88.6", \ + "58.7, 58.7, 58.7, 74.7, 105.5", \ + "86.9, 86.9, 86.9, 103.8, 136.3", \ + "141.7, 141.7, 141.7, 159.5, 193.8"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("43.1, 43.1, 43.1, 68.0, 113.6", \ + "66.3, 66.3, 66.3, 92.8, 141.2", \ + "104.3, 104.3, 104.3, 132.4, 184.6", \ + "175.4, 175.4, 175.4, 204.7, 260.5", \ + "314.5, 314.5, 314.5, 344.7, 403.1"); + } + rise_transition (inslew_load_5x5__11) { + values ("76.6, 76.6, 76.6, 123.0, 215.3", \ + "134.5, 134.5, 134.5, 181.1, 273.1", \ + "236.4, 236.4, 236.4, 283.5, 376.4", \ + "432.4, 432.4, 432.4, 479.9, 573.9", \ + "820.2, 820.2, 820.2, 867.9, 962.8"); + } + cell_fall (inslew_load_5x5__11) { + values ("10.3, 10.3, 10.3, 23.0, 43.9", \ + "2.3, 2.3, 2.3, 18.1, 43.9", \ + "-17.8, -17.8, -17.8, 1.6, 33.6", \ + "-61.8, -61.8, -61.8, -38.9, 0.1", \ + "-152.7, -152.7, -152.7, -127.1, -81.3"); + } + fall_transition (inslew_load_5x5__11) { + values ("25.9, 25.9, 25.9, 40.9, 69.6", \ + "34.6, 34.6, 34.6, 50.5, 80.8", \ + "50.6, 50.6, 50.6, 67.6, 99.6", \ + "81.7, 81.7, 81.7, 99.6, 133.7", \ + "143.1, 143.1, 143.1, 161.8, 197.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__11) { + values ("258.1, 258.1, 258.1, 322.2, 450.3", \ + "337.0, 337.0, 337.0, 401.1, 529.3", \ + "494.9, 494.9, 494.9, 559.0, 687.1", \ + "810.6, 810.6, 810.6, 874.7, 1002.8", \ + "1442.0, 1442.0, 1442.0, 1506.1, 1634.3"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("215.6, 215.6, 215.6, 279.6, 407.8", \ + "227.9, 227.9, 227.9, 291.9, 420.1", \ + "252.5, 252.5, 252.5, 316.5, 444.7", \ + "301.6, 301.6, 301.6, 365.7, 493.9", \ + "400.0, 400.0, 400.0, 464.1, 592.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__11) { + values ("213.1, 213.1, 213.1, 277.2, 405.4", \ + "283.1, 283.1, 283.1, 347.2, 475.3", \ + "423.0, 423.0, 423.0, 487.1, 615.3", \ + "702.9, 702.9, 702.9, 767.0, 895.1", \ + "1262.6, 1262.6, 1262.6, 1326.7, 1454.9"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("172.0, 172.0, 172.0, 236.1, 364.3", \ + "185.4, 185.4, 185.4, 249.5, 377.6", \ + "212.2, 212.2, 212.2, 276.3, 404.4", \ + "265.7, 265.7, 265.7, 329.8, 458.0", \ + "372.8, 372.8, 372.8, 436.9, 565.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__11) { + values ("165.5, 165.5, 165.5, 229.6, 357.8", \ + "226.6, 226.6, 226.6, 290.7, 418.9", \ + "348.9, 348.9, 348.9, 413.0, 541.1", \ + "593.3, 593.3, 593.3, 657.4, 785.6", \ + "1082.3, 1082.3, 1082.3, 1146.4, 1274.5"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("126.5, 126.5, 126.5, 190.6, 318.7", \ + "141.7, 141.7, 141.7, 205.8, 333.9", \ + "172.1, 172.1, 172.1, 236.2, 364.3", \ + "232.9, 232.9, 232.9, 296.9, 425.1", \ + "354.4, 354.4, 354.4, 418.5, 546.7"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__11) { + values ("116.4, 116.4, 116.4, 180.5, 308.7", \ + "170.4, 170.4, 170.4, 234.5, 362.7", \ + "278.4, 278.4, 278.4, 342.5, 470.7", \ + "494.5, 494.5, 494.5, 558.6, 686.7", \ + "926.5, 926.5, 926.5, 990.6, 1118.8"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("82.5, 82.5, 82.5, 146.5, 274.7", \ + "99.2, 99.2, 99.2, 163.2, 291.4", \ + "132.6, 132.6, 132.6, 196.7, 324.8", \ + "199.4, 199.4, 199.4, 263.5, 391.6", \ + "333.0, 333.0, 333.0, 397.1, 525.2"); + } + } + } + } + + cell (na4_x4) { + area : 0.0 ; + cell_leakage_power : 11 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 23 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2) | !(i3))" ; + value : 0.26 ; + } + pin (i3) { + direction : input ; + capacitance : 4.05 ; + } + pin (i2) { + direction : input ; + capacitance : 4.44 ; + } + pin (i1) { + direction : input ; + capacitance : 4.29 ; + } + pin (i0) { + direction : input ; + capacitance : 4.10 ; + } + pin (nq) { + function : "(!(i3) | !(i1) | !(i2) | !(i0))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("124.7, 124.7, 124.7, 130.6, 141.3", \ + "152.0, 152.0, 152.0, 157.9, 169.0", \ + "193.3, 193.3, 193.3, 199.3, 210.7", \ + "265.2, 265.2, 265.2, 271.4, 283.1", \ + "399.8, 399.8, 399.8, 406.1, 418.4"); + } + rise_transition (inslew_load_5x5__1) { + values ("48.3, 48.3, 48.3, 56.0, 71.0", \ + "60.0, 60.0, 60.0, 67.6, 82.7", \ + "79.5, 79.5, 79.5, 87.2, 102.4", \ + "115.3, 115.3, 115.3, 123.1, 138.4", \ + "185.1, 185.1, 185.1, 192.8, 208.2"); + } + cell_fall (inslew_load_5x5__1) { + values ("80.9, 80.9, 80.9, 86.2, 96.1", \ + "78.4, 78.4, 78.4, 83.7, 93.7", \ + "65.5, 65.5, 65.5, 71.0, 81.0", \ + "30.8, 30.8, 30.8, 36.5, 46.4", \ + "-47.9, -47.9, -47.9, -41.9, -31.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("33.7, 33.7, 33.7, 37.3, 44.0", \ + "35.7, 35.7, 35.7, 39.3, 46.1", \ + "39.3, 39.3, 39.3, 42.9, 49.7", \ + "45.6, 45.6, 45.6, 49.2, 56.3", \ + "57.7, 57.7, 57.7, 61.3, 68.3"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("143.0, 143.0, 143.0, 149.0, 159.9", \ + "174.1, 174.1, 174.1, 180.0, 191.3", \ + "222.4, 222.4, 222.4, 228.5, 239.9", \ + "307.7, 307.7, 307.7, 313.9, 325.8", \ + "468.5, 468.5, 468.5, 474.8, 487.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("55.0, 55.0, 55.0, 62.7, 77.7", \ + "67.4, 67.4, 67.4, 75.1, 90.2", \ + "88.7, 88.7, 88.7, 96.4, 111.6", \ + "128.4, 128.4, 128.4, 136.1, 151.4", \ + "205.6, 205.6, 205.6, 213.3, 228.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("89.1, 89.1, 89.1, 94.4, 104.4", \ + "85.1, 85.1, 85.1, 90.5, 100.4", \ + "69.5, 69.5, 69.5, 75.0, 85.0", \ + "28.8, 28.8, 28.8, 34.5, 44.5", \ + "-63.8, -63.8, -63.8, -57.9, -47.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("35.7, 35.7, 35.7, 39.3, 46.1", \ + "37.6, 37.6, 37.6, 41.1, 47.9", \ + "40.7, 40.7, 40.7, 44.3, 51.2", \ + "46.5, 46.5, 46.5, 50.0, 57.2", \ + "57.2, 57.2, 57.2, 60.9, 67.9"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("159.4, 159.4, 159.4, 165.4, 176.4", \ + "194.9, 194.9, 194.9, 200.8, 212.2", \ + "251.3, 251.3, 251.3, 257.5, 269.0", \ + "352.4, 352.4, 352.4, 358.6, 370.7", \ + "544.4, 544.4, 544.4, 550.8, 563.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("61.0, 61.0, 61.0, 68.6, 83.7", \ + "74.7, 74.7, 74.7, 82.4, 97.6", \ + "98.2, 98.2, 98.2, 106.0, 121.3", \ + "142.6, 142.6, 142.6, 150.3, 165.7", \ + "229.2, 229.2, 229.2, 236.8, 252.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("95.2, 95.2, 95.2, 100.7, 110.6", \ + "88.9, 88.9, 88.9, 94.4, 104.4", \ + "70.2, 70.2, 70.2, 75.8, 85.7", \ + "22.7, 22.7, 22.7, 28.4, 38.3", \ + "-84.8, -84.8, -84.8, -78.9, -68.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("37.7, 37.7, 37.7, 41.3, 48.1", \ + "39.2, 39.2, 39.2, 42.8, 49.7", \ + "42.1, 42.1, 42.1, 45.6, 52.6", \ + "47.1, 47.1, 47.1, 50.6, 57.8", \ + "56.5, 56.5, 56.5, 60.1, 67.1"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("174.1, 174.1, 174.1, 180.1, 191.3", \ + "213.8, 213.8, 213.8, 219.8, 231.2", \ + "278.1, 278.1, 278.1, 284.3, 295.9", \ + "394.4, 394.4, 394.4, 400.7, 412.9", \ + "616.8, 616.8, 616.8, 623.2, 635.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("66.4, 66.4, 66.4, 74.1, 89.2", \ + "81.5, 81.5, 81.5, 89.3, 104.5", \ + "107.4, 107.4, 107.4, 115.1, 130.4", \ + "156.5, 156.5, 156.5, 164.1, 179.6", \ + "252.4, 252.4, 252.4, 260.0, 275.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("99.3, 99.3, 99.3, 104.8, 114.8", \ + "90.0, 90.0, 90.0, 95.5, 105.5", \ + "67.3, 67.3, 67.3, 72.9, 82.9", \ + "12.8, 12.8, 12.8, 18.6, 28.5", \ + "-107.9, -107.9, -107.9, -102.0, -91.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("39.5, 39.5, 39.5, 43.1, 49.9", \ + "40.7, 40.7, 40.7, 44.2, 51.2", \ + "43.1, 43.1, 43.1, 46.7, 53.7", \ + "47.5, 47.5, 47.5, 51.1, 58.3", \ + "55.8, 55.8, 55.8, 59.5, 66.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("669.7, 669.7, 669.7, 729.3, 848.5", \ + "816.0, 816.0, 816.0, 875.6, 994.8", \ + "1083.0, 1083.0, 1083.0, 1142.6, 1261.8", \ + "1598.4, 1598.4, 1598.4, 1657.9, 1777.1", \ + "2617.8, 2617.8, 2617.8, 2677.4, 2796.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("598.7, 598.7, 598.7, 658.3, 777.5", \ + "637.4, 637.4, 637.4, 697.0, 816.2", \ + "709.4, 709.4, 709.4, 769.0, 888.2", \ + "846.5, 846.5, 846.5, 906.1, 1025.3", \ + "1115.0, 1115.0, 1115.0, 1174.6, 1293.8"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("771.4, 771.4, 771.4, 831.0, 950.2", \ + "932.5, 932.5, 932.5, 992.1, 1111.3", \ + "1230.0, 1230.0, 1230.0, 1289.6, 1408.8", \ + "1806.4, 1806.4, 1806.4, 1866.0, 1985.2", \ + "2946.6, 2946.6, 2946.6, 3006.2, 3125.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("664.7, 664.7, 664.7, 724.3, 843.5", \ + "699.5, 699.5, 699.5, 759.1, 878.3", \ + "764.9, 764.9, 764.9, 824.5, 943.7", \ + "889.5, 889.5, 889.5, 949.1, 1068.3", \ + "1131.6, 1131.6, 1131.6, 1191.2, 1310.4"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("866.7, 866.7, 866.7, 926.3, 1045.5", \ + "1048.6, 1048.6, 1048.6, 1108.2, 1227.4", \ + "1383.9, 1383.9, 1383.9, 1443.5, 1562.7", \ + "2035.9, 2035.9, 2035.9, 2095.5, 2214.7", \ + "3325.9, 3325.9, 3325.9, 3385.5, 3504.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("731.6, 731.6, 731.6, 791.2, 910.4", \ + "761.5, 761.5, 761.5, 821.1, 940.3", \ + "819.4, 819.4, 819.4, 879.0, 998.2", \ + "929.0, 929.0, 929.0, 988.6, 1107.8", \ + "1141.2, 1141.2, 1141.2, 1200.8, 1320.0"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("956.0, 956.0, 956.0, 1015.6, 1134.8", \ + "1158.8, 1158.8, 1158.8, 1218.4, 1337.6", \ + "1532.4, 1532.4, 1532.4, 1592.0, 1711.2", \ + "2260.2, 2260.2, 2260.2, 2319.8, 2438.9", \ + "3701.3, 3701.3, 3701.3, 3760.9, 3880.1"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("794.6, 794.6, 794.6, 854.2, 973.4", \ + "820.0, 820.0, 820.0, 879.6, 998.8", \ + "871.4, 871.4, 871.4, 931.0, 1050.2", \ + "970.1, 970.1, 970.1, 1029.7, 1148.9", \ + "1161.2, 1161.2, 1161.2, 1220.8, 1340.0"); + } + } + } + } + + cell (nao22_x1) { + area : 0.0 ; + cell_leakage_power : 1.5 ; + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 0.00014 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 3.6 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 5.2 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 6.9e-05 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 0.00017 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 2.9e-06 ; + } + pin (i2) { + direction : input ; + capacitance : 5.78 ; + } + pin (i1) { + direction : input ; + capacitance : 5.78 ; + } + pin (i0) { + direction : input ; + capacitance : 5.78 ; + } + pin (nq) { + function : "((!(i1) & !(i0)) | !(i2))" ; + direction : output ; + capacitance : 4.79 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("45.4, 45.4, 45.4, 61.5, 93.1", \ + "49.5, 49.5, 49.5, 66.0, 98.3", \ + "56.3, 56.3, 56.3, 73.3, 106.4", \ + "69.0, 69.0, 69.0, 86.5, 120.6", \ + "93.5, 93.5, 93.5, 111.3, 146.4"); + } + rise_transition (inslew_load_5x5__12) { + values ("94.3, 94.3, 94.3, 121.9, 177.6", \ + "130.5, 130.5, 130.5, 157.7, 212.7", \ + "200.9, 200.9, 200.9, 227.7, 281.7", \ + "338.5, 338.5, 338.5, 365.5, 421.1", \ + "615.2, 615.2, 615.2, 642.2, 696.0"); + } + cell_fall (inslew_load_5x5__12) { + values ("21.8, 21.8, 21.8, 31.7, 49.2", \ + "25.1, 25.1, 25.1, 36.3, 56.4", \ + "29.1, 29.1, 29.1, 41.6, 64.4", \ + "35.3, 35.3, 35.3, 48.7, 73.8", \ + "46.6, 46.6, 46.6, 60.5, 87.4"); + } + fall_transition (inslew_load_5x5__12) { + values ("32.1, 32.1, 32.1, 42.5, 62.9", \ + "50.6, 50.6, 50.6, 61.4, 82.2", \ + "86.1, 86.1, 86.1, 97.3, 118.9", \ + "156.2, 156.2, 156.2, 167.5, 189.9", \ + "295.6, 295.6, 295.6, 307.2, 330.0"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("31.7, 31.7, 31.7, 49.6, 82.7", \ + "45.2, 45.2, 45.2, 63.9, 98.7", \ + "67.7, 67.7, 67.7, 87.3, 124.2", \ + "110.4, 110.4, 110.4, 130.6, 169.6", \ + "194.1, 194.1, 194.1, 214.8, 255.3"); + } + rise_transition (inslew_load_5x5__12) { + values ("60.4, 60.4, 60.4, 88.9, 145.1", \ + "103.5, 103.5, 103.5, 131.5, 188.1", \ + "183.3, 183.3, 183.3, 211.6, 267.5", \ + "339.6, 339.6, 339.6, 368.1, 424.6", \ + "650.4, 650.4, 650.4, 679.0, 735.9"); + } + cell_fall (inslew_load_5x5__12) { + values ("12.6, 12.6, 12.6, 23.7, 42.3", \ + "8.1, 8.1, 8.1, 21.4, 43.5", \ + "-3.2, -3.2, -3.2, 12.0, 38.4", \ + "-27.9, -27.9, -27.9, -11.0, 19.4", \ + "-78.5, -78.5, -78.5, -60.5, -26.8"); + } + fall_transition (inslew_load_5x5__12) { + values ("23.3, 23.3, 23.3, 34.2, 54.7", \ + "35.8, 35.8, 35.8, 47.2, 68.7", \ + "59.4, 59.4, 59.4, 71.5, 94.3", \ + "105.7, 105.7, 105.7, 118.4, 142.6", \ + "197.7, 197.7, 197.7, 210.8, 236.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("28.5, 28.5, 28.5, 38.1, 55.8", \ + "36.1, 36.1, 36.1, 46.8, 66.5", \ + "48.5, 48.5, 48.5, 60.2, 82.0", \ + "71.6, 71.6, 71.6, 83.9, 107.5", \ + "116.7, 116.7, 116.7, 129.4, 154.2"); + } + rise_transition (inslew_load_5x5__12) { + values ("55.8, 55.8, 55.8, 70.6, 99.9", \ + "87.5, 87.5, 87.5, 102.7, 132.5", \ + "148.5, 148.5, 148.5, 164.0, 194.5", \ + "269.3, 269.3, 269.3, 285.0, 316.0", \ + "510.0, 510.0, 510.0, 525.8, 557.3"); + } + cell_fall (inslew_load_5x5__12) { + values ("21.2, 21.2, 21.2, 30.0, 46.4", \ + "20.0, 20.0, 20.0, 29.9, 48.1", \ + "15.2, 15.2, 15.2, 26.3, 46.8", \ + "3.9, 3.9, 3.9, 15.9, 38.6", \ + "-19.8, -19.8, -19.8, -7.2, 17.0"); + } + fall_transition (inslew_load_5x5__12) { + values ("35.5, 35.5, 35.5, 45.7, 65.9", \ + "51.3, 51.3, 51.3, 61.6, 81.9", \ + "81.9, 81.9, 81.9, 92.5, 113.2", \ + "142.5, 142.5, 142.5, 153.3, 174.5", \ + "263.0, 263.0, 263.0, 274.0, 295.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__12) { + values ("192.4, 192.4, 192.4, 252.3, 372.0", \ + "257.1, 257.1, 257.1, 316.9, 436.7", \ + "386.3, 386.3, 386.3, 446.2, 565.9", \ + "644.8, 644.8, 644.8, 704.6, 824.4", \ + "1161.7, 1161.7, 1161.7, 1221.6, 1341.3"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("149.8, 149.8, 149.8, 209.7, 329.4", \ + "210.2, 210.2, 210.2, 270.1, 389.8", \ + "331.2, 331.2, 331.2, 391.0, 510.8", \ + "573.0, 573.0, 573.0, 632.8, 752.6", \ + "1056.6, 1056.6, 1056.6, 1116.5, 1236.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__12) { + values ("122.9, 122.9, 122.9, 182.7, 302.5", \ + "187.6, 187.6, 187.6, 247.5, 367.2", \ + "317.1, 317.1, 317.1, 377.0, 496.7", \ + "576.2, 576.2, 576.2, 636.1, 755.8", \ + "1094.3, 1094.3, 1094.3, 1154.1, 1273.9"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("93.9, 93.9, 93.9, 153.8, 273.5", \ + "126.2, 126.2, 126.2, 186.1, 305.8", \ + "190.8, 190.8, 190.8, 250.7, 370.4", \ + "320.0, 320.0, 320.0, 379.9, 499.6", \ + "578.4, 578.4, 578.4, 638.2, 758.0"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__12) { + values ("191.4, 191.4, 191.4, 251.2, 371.0", \ + "278.1, 278.1, 278.1, 337.9, 457.7", \ + "451.5, 451.5, 451.5, 511.3, 631.1", \ + "798.3, 798.3, 798.3, 858.2, 977.9", \ + "1491.9, 1491.9, 1491.9, 1551.8, 1671.5"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("173.6, 173.6, 173.6, 233.5, 353.2", \ + "229.7, 229.7, 229.7, 289.5, 409.3", \ + "341.7, 341.7, 341.7, 401.6, 521.3", \ + "565.9, 565.9, 565.9, 625.7, 745.5", \ + "1014.1, 1014.1, 1014.1, 1074.0, 1193.7"); + } + } + } + } + + cell (nao22_x4) { + area : 0.0 ; + cell_leakage_power : 2.5 ; + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 3.6 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 3.7 ; + } + leakage_power () { + when : "(!((i0 | i1)) | !(i2))" ; + value : 0.26 ; + } + pin (i2) { + direction : input ; + capacitance : 3.42 ; + } + pin (i1) { + direction : input ; + capacitance : 3.66 ; + } + pin (i0) { + direction : input ; + capacitance : 3.63 ; + } + pin (nq) { + function : "(!(i2) | (!(i0) & !(i1)))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("135.4, 135.4, 135.4, 141.4, 152.2", \ + "142.6, 142.6, 142.6, 148.6, 159.6", \ + "153.0, 153.0, 153.0, 159.0, 170.3", \ + "169.8, 169.8, 169.8, 176.0, 187.4", \ + "197.6, 197.6, 197.6, 203.9, 216.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("53.8, 53.8, 53.8, 61.4, 76.5", \ + "60.6, 60.6, 60.6, 68.2, 83.3", \ + "73.6, 73.6, 73.6, 81.3, 96.5", \ + "98.5, 98.5, 98.5, 106.3, 121.6", \ + "147.7, 147.7, 147.7, 155.3, 170.7"); + } + cell_fall (inslew_load_5x5__1) { + values ("102.3, 102.3, 102.3, 107.6, 117.6", \ + "112.8, 112.8, 112.8, 118.3, 128.2", \ + "125.9, 125.9, 125.9, 131.6, 141.5", \ + "143.3, 143.3, 143.3, 149.2, 159.7", \ + "170.1, 170.1, 170.1, 176.2, 187.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("36.1, 36.1, 36.1, 39.7, 46.4", \ + "40.0, 40.0, 40.0, 43.6, 50.5", \ + "47.1, 47.1, 47.1, 50.6, 57.8", \ + "60.4, 60.4, 60.4, 64.0, 71.0", \ + "86.2, 86.2, 86.2, 89.8, 96.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("122.2, 122.2, 122.2, 128.2, 138.8", \ + "139.5, 139.5, 139.5, 145.5, 156.4", \ + "166.5, 166.5, 166.5, 172.5, 183.8", \ + "211.7, 211.7, 211.7, 217.9, 229.3", \ + "294.4, 294.4, 294.4, 300.6, 312.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("47.0, 47.0, 47.0, 54.7, 69.7", \ + "55.4, 55.4, 55.4, 63.0, 78.1", \ + "70.4, 70.4, 70.4, 78.1, 93.2", \ + "98.5, 98.5, 98.5, 106.3, 121.6", \ + "153.2, 153.2, 153.2, 160.9, 176.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("93.0, 93.0, 93.0, 98.3, 108.2", \ + "96.2, 96.2, 96.2, 101.6, 111.5", \ + "94.2, 94.2, 94.2, 99.8, 109.7", \ + "80.7, 80.7, 80.7, 86.5, 96.6", \ + "44.2, 44.2, 44.2, 50.2, 61.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("34.4, 34.4, 34.4, 38.0, 44.7", \ + "37.3, 37.3, 37.3, 40.9, 47.7", \ + "42.4, 42.4, 42.4, 45.9, 52.9", \ + "51.7, 51.7, 51.7, 55.3, 62.3", \ + "69.3, 69.3, 69.3, 72.9, 79.9"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("104.4, 104.4, 104.4, 110.2, 120.7", \ + "117.0, 117.0, 117.0, 122.9, 133.5", \ + "134.5, 134.5, 134.5, 140.5, 151.6", \ + "161.6, 161.6, 161.6, 167.7, 179.1", \ + "208.6, 208.6, 208.6, 214.9, 226.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("41.4, 41.4, 41.4, 49.1, 64.1", \ + "47.9, 47.9, 47.9, 55.6, 70.6", \ + "59.6, 59.6, 59.6, 67.2, 82.3", \ + "81.4, 81.4, 81.4, 89.1, 104.3", \ + "122.9, 122.9, 122.9, 130.7, 146.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("102.2, 102.2, 102.2, 107.6, 117.5", \ + "106.8, 106.8, 106.8, 112.3, 122.2", \ + "110.2, 110.2, 110.2, 115.9, 125.8", \ + "109.9, 109.9, 109.9, 115.8, 126.1", \ + "101.6, 101.6, 101.6, 107.6, 118.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("37.0, 37.0, 37.0, 40.6, 47.4", \ + "40.1, 40.1, 40.1, 43.7, 50.6", \ + "46.0, 46.0, 46.0, 49.5, 56.7", \ + "57.2, 57.2, 57.2, 60.8, 67.8", \ + "78.9, 78.9, 78.9, 82.6, 89.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("694.8, 694.8, 694.8, 754.4, 873.6", \ + "781.1, 781.1, 781.1, 840.7, 959.8", \ + "950.6, 950.6, 950.6, 1010.2, 1129.4", \ + "1284.2, 1284.2, 1284.2, 1343.8, 1463.0", \ + "1949.2, 1949.2, 1949.2, 2008.8, 2128.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("619.4, 619.4, 619.4, 679.0, 798.2", \ + "691.4, 691.4, 691.4, 751.0, 870.2", \ + "828.0, 828.0, 828.0, 887.6, 1006.8", \ + "1094.4, 1094.4, 1094.4, 1154.0, 1273.2", \ + "1619.2, 1619.2, 1619.2, 1678.8, 1798.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("606.4, 606.4, 606.4, 665.9, 785.1", \ + "703.0, 703.0, 703.0, 762.6, 881.8", \ + "887.3, 887.3, 887.3, 946.9, 1066.1", \ + "1245.6, 1245.6, 1245.6, 1305.2, 1424.4", \ + "1954.0, 1954.0, 1954.0, 2013.6, 2132.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("573.6, 573.6, 573.6, 633.2, 752.4", \ + "621.0, 621.0, 621.0, 680.6, 799.8", \ + "708.2, 708.2, 708.2, 767.7, 886.9", \ + "874.9, 874.9, 874.9, 934.5, 1053.7", \ + "1199.5, 1199.5, 1199.5, 1259.1, 1378.3"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("605.0, 605.0, 605.0, 664.6, 783.8", \ + "696.8, 696.8, 696.8, 756.4, 875.6", \ + "873.7, 873.7, 873.7, 933.3, 1052.5", \ + "1220.8, 1220.8, 1220.8, 1280.4, 1399.6", \ + "1905.6, 1905.6, 1905.6, 1965.2, 2084.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("650.0, 650.0, 650.0, 709.6, 828.8", \ + "711.3, 711.3, 711.3, 770.9, 890.1", \ + "830.8, 830.8, 830.8, 890.4, 1009.6", \ + "1064.9, 1064.9, 1064.9, 1124.5, 1243.7", \ + "1527.6, 1527.6, 1527.6, 1587.2, 1706.4"); + } + } + } + } + + cell (nao2o22_x1) { + area : 0.0 ; + cell_leakage_power : 1.9 ; + leakage_power () { + when : "(!(i3) & !(i2) & i1 & i0)" ; + value : 0.00027 ; + } + leakage_power () { + when : "(i0 & ((i1 & i2 & !(i3)) | (!(i1) & i2 & i3)))" ; + value : 3.5 ; + } + leakage_power () { + when : "(!(i3) & i2 & !(i1) & i0)" ; + value : 2 ; + } + leakage_power () { + when : "((i0 & i1 & i3) | (i1 & i2 & i3))" ; + value : 5.1 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3) | (!(i0) & i1 & i2 & !(i3)))" ; + value : 3.6 ; + } + leakage_power () { + when : "(i3 & !(i2) & i1 & !(i0))" ; + value : 5.2 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & !(i3))" ; + value : 0.00014 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 0.00034 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3))" ; + value : 0.00017 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.8e-06 ; + } + pin (i3) { + direction : input ; + capacitance : 5.78 ; + } + pin (i2) { + direction : input ; + capacitance : 5.62 ; + } + pin (i1) { + direction : input ; + capacitance : 5.67 ; + } + pin (i0) { + direction : input ; + capacitance : 5.81 ; + } + pin (nq) { + function : "((!(i1) & !(i0)) | (!(i3) & !(i2)))" ; + direction : output ; + capacitance : 4.85 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("45.6, 45.6, 45.6, 61.9, 93.8", \ + "49.7, 49.7, 49.7, 66.4, 99.1", \ + "56.6, 56.6, 56.6, 73.7, 107.2", \ + "69.2, 69.2, 69.2, 86.9, 121.4", \ + "93.7, 93.7, 93.7, 111.7, 147.3"); + } + rise_transition (inslew_load_5x5__13) { + values ("94.6, 94.6, 94.6, 122.5, 179.0", \ + "130.8, 130.8, 130.8, 158.4, 214.1", \ + "201.2, 201.2, 201.2, 228.4, 283.1", \ + "338.8, 338.8, 338.8, 366.1, 422.5", \ + "615.5, 615.5, 615.5, 642.8, 697.3"); + } + cell_fall (inslew_load_5x5__13) { + values ("21.8, 21.8, 21.8, 31.7, 49.4", \ + "25.1, 25.1, 25.1, 36.4, 56.6", \ + "29.1, 29.1, 29.1, 41.7, 64.7", \ + "35.3, 35.3, 35.3, 48.8, 74.3", \ + "46.6, 46.6, 46.6, 60.7, 87.9"); + } + fall_transition (inslew_load_5x5__13) { + values ("32.2, 32.2, 32.2, 42.7, 63.4", \ + "50.7, 50.7, 50.7, 61.6, 82.7", \ + "86.2, 86.2, 86.2, 97.5, 119.3", \ + "156.2, 156.2, 156.2, 167.8, 190.4", \ + "295.7, 295.7, 295.7, 307.4, 330.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("32.0, 32.0, 32.0, 50.0, 83.5", \ + "45.4, 45.4, 45.4, 64.3, 99.5", \ + "68.0, 68.0, 68.0, 87.8, 125.1", \ + "110.6, 110.6, 110.6, 131.1, 170.6", \ + "194.4, 194.4, 194.4, 215.3, 256.3"); + } + rise_transition (inslew_load_5x5__13) { + values ("60.7, 60.7, 60.7, 89.5, 146.5", \ + "103.8, 103.8, 103.8, 132.2, 189.5", \ + "183.6, 183.6, 183.6, 212.3, 268.9", \ + "340.0, 340.0, 340.0, 368.8, 426.0", \ + "650.7, 650.7, 650.7, 679.7, 737.3"); + } + cell_fall (inslew_load_5x5__13) { + values ("12.6, 12.6, 12.6, 23.8, 42.5", \ + "8.2, 8.2, 8.2, 21.5, 43.8", \ + "-3.1, -3.1, -3.1, 12.2, 38.8", \ + "-27.8, -27.8, -27.8, -10.7, 19.9", \ + "-78.3, -78.3, -78.3, -60.1, -26.1"); + } + fall_transition (inslew_load_5x5__13) { + values ("23.4, 23.4, 23.4, 34.3, 55.1", \ + "35.9, 35.9, 35.9, 47.4, 69.1", \ + "59.5, 59.5, 59.5, 71.7, 94.8", \ + "105.8, 105.8, 105.8, 118.6, 143.1", \ + "197.9, 197.9, 197.9, 211.1, 236.7"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("67.2, 67.2, 67.2, 83.1, 114.8", \ + "78.3, 78.3, 78.3, 94.5, 126.5", \ + "98.2, 98.2, 98.2, 114.7, 147.5", \ + "137.0, 137.0, 137.0, 153.8, 187.0", \ + "213.8, 213.8, 213.8, 230.9, 264.7"); + } + rise_transition (inslew_load_5x5__13) { + values ("131.6, 131.6, 131.6, 159.8, 216.6", \ + "178.1, 178.1, 178.1, 206.0, 262.1", \ + "267.9, 267.9, 267.9, 295.4, 350.8", \ + "447.1, 447.1, 447.1, 474.3, 528.8", \ + "805.6, 805.6, 805.6, 832.6, 886.6"); + } + cell_fall (inslew_load_5x5__13) { + values ("28.7, 28.7, 28.7, 37.0, 53.1", \ + "28.4, 28.4, 28.4, 37.7, 55.4", \ + "24.6, 24.6, 24.6, 35.1, 55.1", \ + "13.9, 13.9, 13.9, 25.6, 47.9", \ + "-9.4, -9.4, -9.4, 3.0, 27.2"); + } + fall_transition (inslew_load_5x5__13) { + values ("43.6, 43.6, 43.6, 54.0, 74.4", \ + "59.5, 59.5, 59.5, 69.9, 90.3", \ + "90.3, 90.3, 90.3, 101.0, 121.8", \ + "151.1, 151.1, 151.1, 161.9, 183.3", \ + "271.7, 271.7, 271.7, 282.8, 304.7"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("53.6, 53.6, 53.6, 70.3, 102.9", \ + "73.7, 73.7, 73.7, 91.2, 125.0", \ + "108.4, 108.4, 108.4, 126.8, 162.2", \ + "174.6, 174.6, 174.6, 193.6, 230.5", \ + "304.5, 304.5, 304.5, 324.0, 362.3"); + } + rise_transition (inslew_load_5x5__13) { + values ("95.3, 95.3, 95.3, 123.7, 181.4", \ + "146.8, 146.8, 146.8, 175.9, 232.2", \ + "243.1, 243.1, 243.1, 271.4, 328.0", \ + "431.9, 431.9, 431.9, 460.3, 516.8", \ + "806.9, 806.9, 806.9, 835.4, 892.3"); + } + cell_fall (inslew_load_5x5__13) { + values ("21.1, 21.1, 21.1, 30.0, 46.5", \ + "14.9, 14.9, 14.9, 25.3, 44.1", \ + "-1.4, -1.4, -1.4, 10.8, 32.9", \ + "-38.4, -38.4, -38.4, -24.2, 1.7", \ + "-116.0, -116.0, -116.0, -100.3, -70.7"); + } + fall_transition (inslew_load_5x5__13) { + values ("35.2, 35.2, 35.2, 45.5, 66.0", \ + "45.9, 45.9, 45.9, 56.5, 77.2", \ + "66.3, 66.3, 66.3, 77.4, 98.9", \ + "105.7, 105.7, 105.7, 117.4, 140.0", \ + "183.1, 183.1, 183.1, 195.3, 219.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__13) { + values ("193.2, 193.2, 193.2, 253.8, 375.0", \ + "257.8, 257.8, 257.8, 318.4, 439.6", \ + "387.0, 387.0, 387.0, 447.6, 568.8", \ + "645.5, 645.5, 645.5, 706.1, 827.3", \ + "1162.5, 1162.5, 1162.5, 1223.1, 1344.3"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("150.5, 150.5, 150.5, 211.1, 332.3", \ + "211.0, 211.0, 211.0, 271.6, 392.8", \ + "331.9, 331.9, 331.9, 392.5, 513.7", \ + "573.7, 573.7, 573.7, 634.3, 755.5", \ + "1057.4, 1057.4, 1057.4, 1118.0, 1239.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__13) { + values ("123.6, 123.6, 123.6, 184.2, 305.4", \ + "188.4, 188.4, 188.4, 249.0, 370.2", \ + "317.9, 317.9, 317.9, 378.5, 499.7", \ + "576.9, 576.9, 576.9, 637.5, 758.7", \ + "1095.0, 1095.0, 1095.0, 1155.6, 1276.8"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("94.7, 94.7, 94.7, 155.3, 276.5", \ + "127.0, 127.0, 127.0, 187.6, 308.8", \ + "191.6, 191.6, 191.6, 252.2, 373.4", \ + "320.7, 320.7, 320.7, 381.3, 502.5", \ + "579.1, 579.1, 579.1, 639.7, 760.9"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__13) { + values ("276.6, 276.6, 276.6, 337.2, 458.4", \ + "363.3, 363.3, 363.3, 423.9, 545.1", \ + "536.7, 536.7, 536.7, 597.3, 718.5", \ + "883.5, 883.5, 883.5, 944.1, 1065.3", \ + "1577.1, 1577.1, 1577.1, 1637.8, 1759.0"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("221.8, 221.8, 221.8, 282.4, 403.7", \ + "277.9, 277.9, 277.9, 338.5, 459.7", \ + "389.9, 389.9, 389.9, 450.5, 571.8", \ + "614.1, 614.1, 614.1, 674.7, 795.9", \ + "1062.4, 1062.4, 1062.4, 1123.0, 1244.2"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__13) { + values ("201.7, 201.7, 201.7, 262.3, 383.5", \ + "283.2, 283.2, 283.2, 343.8, 465.0", \ + "446.4, 446.4, 446.4, 507.0, 628.2", \ + "772.6, 772.6, 772.6, 833.2, 954.4", \ + "1425.0, 1425.0, 1425.0, 1485.6, 1606.8"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("166.9, 166.9, 166.9, 227.5, 348.7", \ + "195.7, 195.7, 195.7, 256.3, 377.5", \ + "253.2, 253.2, 253.2, 313.8, 435.0", \ + "368.3, 368.3, 368.3, 428.9, 550.1", \ + "598.4, 598.4, 598.4, 659.0, 780.2"); + } + } + } + } + + cell (nao2o22_x4) { + area : 0.0 ; + cell_leakage_power : 2.7 ; + leakage_power () { + when : "(!(i3) & i2 & !(i1) & i0)" ; + value : 3.5 ; + } + leakage_power () { + when : "((i0 & ((i1 & i2 & !(i3)) | (!(i1) & i3))) | (i1 & i2 & !(i3)))" ; + value : 3.6 ; + } + leakage_power () { + when : "(i1 & i3)" ; + value : 3.7 ; + } + leakage_power () { + when : "(!((i0 | i1)) | (!(i2) & !(i3)))" ; + value : 0.26 ; + } + pin (i3) { + direction : input ; + capacitance : 3.52 ; + } + pin (i2) { + direction : input ; + capacitance : 3.36 ; + } + pin (i1) { + direction : input ; + capacitance : 3.52 ; + } + pin (i0) { + direction : input ; + capacitance : 3.66 ; + } + pin (nq) { + function : "(!((i2 | i3)) | (!(i0) & !(i1)))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("132.6, 132.6, 132.6, 138.6, 149.4", \ + "139.8, 139.8, 139.8, 145.8, 156.8", \ + "150.3, 150.3, 150.3, 156.3, 167.7", \ + "167.2, 167.2, 167.2, 173.3, 184.8", \ + "195.3, 195.3, 195.3, 201.6, 213.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("52.9, 52.9, 52.9, 60.5, 75.6", \ + "59.8, 59.8, 59.8, 67.4, 82.5", \ + "72.9, 72.9, 72.9, 80.6, 95.7", \ + "97.9, 97.9, 97.9, 105.7, 120.9", \ + "147.3, 147.3, 147.3, 155.0, 170.4"); + } + cell_fall (inslew_load_5x5__1) { + values ("100.2, 100.2, 100.2, 105.5, 115.4", \ + "110.5, 110.5, 110.5, 116.0, 125.9", \ + "123.3, 123.3, 123.3, 129.0, 138.9", \ + "140.7, 140.7, 140.7, 146.7, 157.1", \ + "167.5, 167.5, 167.5, 173.6, 184.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("35.6, 35.6, 35.6, 39.2, 45.9", \ + "39.5, 39.5, 39.5, 43.1, 50.0", \ + "46.6, 46.6, 46.6, 50.1, 57.3", \ + "59.9, 59.9, 59.9, 63.6, 70.5", \ + "85.8, 85.8, 85.8, 89.4, 96.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("119.2, 119.2, 119.2, 125.1, 135.7", \ + "136.6, 136.6, 136.6, 142.6, 153.4", \ + "163.4, 163.4, 163.4, 169.3, 180.6", \ + "208.8, 208.8, 208.8, 214.9, 226.4", \ + "291.7, 291.7, 291.7, 297.9, 310.1"); + } + rise_transition (inslew_load_5x5__1) { + values ("46.0, 46.0, 46.0, 53.7, 68.7", \ + "54.5, 54.5, 54.5, 62.1, 77.2", \ + "69.6, 69.6, 69.6, 77.3, 92.4", \ + "97.9, 97.9, 97.9, 105.7, 120.9", \ + "152.9, 152.9, 152.9, 160.5, 175.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("90.4, 90.4, 90.4, 95.7, 105.6", \ + "93.6, 93.6, 93.6, 98.9, 108.9", \ + "91.4, 91.4, 91.4, 97.0, 106.9", \ + "77.8, 77.8, 77.8, 83.6, 93.7", \ + "41.0, 41.0, 41.0, 47.0, 57.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("33.8, 33.8, 33.8, 37.5, 44.2", \ + "36.8, 36.8, 36.8, 40.4, 47.2", \ + "41.9, 41.9, 41.9, 45.4, 52.4", \ + "51.2, 51.2, 51.2, 54.8, 61.9", \ + "68.9, 68.9, 68.9, 72.5, 79.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("158.2, 158.2, 158.2, 164.2, 175.3", \ + "171.0, 171.0, 171.0, 176.9, 188.2", \ + "192.7, 192.7, 192.7, 198.8, 210.2", \ + "232.7, 232.7, 232.7, 238.9, 250.7", \ + "306.8, 306.8, 306.8, 313.1, 325.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("61.3, 61.3, 61.3, 68.9, 84.0", \ + "69.7, 69.7, 69.7, 77.5, 92.6", \ + "86.0, 86.0, 86.0, 93.8, 109.0", \ + "117.7, 117.7, 117.7, 125.4, 140.7", \ + "180.5, 180.5, 180.5, 188.2, 203.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("108.8, 108.8, 108.8, 114.2, 124.2", \ + "113.7, 113.7, 113.7, 119.3, 129.2", \ + "118.0, 118.0, 118.0, 123.7, 133.6", \ + "118.3, 118.3, 118.3, 124.2, 134.6", \ + "110.4, 110.4, 110.4, 116.5, 127.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("38.2, 38.2, 38.2, 41.7, 48.6", \ + "41.3, 41.3, 41.3, 44.8, 51.7", \ + "47.2, 47.2, 47.2, 50.7, 57.9", \ + "58.4, 58.4, 58.4, 62.0, 69.0", \ + "80.2, 80.2, 80.2, 83.8, 90.8"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("144.4, 144.4, 144.4, 150.4, 161.3", \ + "167.4, 167.4, 167.4, 173.3, 184.5", \ + "204.5, 204.5, 204.5, 210.6, 222.0", \ + "271.1, 271.1, 271.1, 277.3, 289.1", \ + "395.5, 395.5, 395.5, 401.8, 414.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("54.3, 54.3, 54.3, 61.9, 77.0", \ + "64.0, 64.0, 64.0, 71.6, 86.7", \ + "81.5, 81.5, 81.5, 89.3, 104.4", \ + "114.9, 114.9, 114.9, 122.6, 138.0", \ + "180.5, 180.5, 180.5, 188.2, 203.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("100.5, 100.5, 100.5, 105.8, 115.8", \ + "99.9, 99.9, 99.9, 105.4, 115.3", \ + "92.2, 92.2, 92.2, 97.8, 107.8", \ + "67.1, 67.1, 67.1, 72.9, 82.9", \ + "5.5, 5.5, 5.5, 11.4, 22.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("36.5, 36.5, 36.5, 40.1, 46.9", \ + "38.8, 38.8, 38.8, 42.4, 49.2", \ + "43.0, 43.0, 43.0, 46.5, 53.5", \ + "50.6, 50.6, 50.6, 54.2, 61.3", \ + "65.2, 65.2, 65.2, 68.8, 75.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("681.6, 681.6, 681.6, 741.2, 860.4", \ + "768.3, 768.3, 768.3, 827.9, 947.1", \ + "938.2, 938.2, 938.2, 997.8, 1117.0", \ + "1272.1, 1272.1, 1272.1, 1331.7, 1450.9", \ + "1938.5, 1938.5, 1938.5, 1998.1, 2117.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("608.2, 608.2, 608.2, 667.8, 787.0", \ + "680.1, 680.1, 680.1, 739.7, 858.9", \ + "816.7, 816.7, 816.7, 876.3, 995.5", \ + "1082.7, 1082.7, 1082.7, 1142.3, 1261.5", \ + "1608.0, 1608.0, 1608.0, 1667.6, 1786.8"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("592.8, 592.8, 592.8, 652.4, 771.6", \ + "689.8, 689.8, 689.8, 749.4, 868.6", \ + "874.5, 874.5, 874.5, 934.1, 1053.3", \ + "1233.4, 1233.4, 1233.4, 1293.0, 1412.2", \ + "1943.2, 1943.2, 1943.2, 2002.8, 2122.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("562.1, 562.1, 562.1, 621.7, 740.9", \ + "609.4, 609.4, 609.4, 669.0, 788.2", \ + "696.5, 696.5, 696.5, 756.1, 875.3", \ + "863.1, 863.1, 863.1, 922.7, 1041.9", \ + "1188.0, 1188.0, 1188.0, 1247.6, 1366.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("797.0, 797.0, 797.0, 856.6, 975.8", \ + "907.8, 907.8, 907.8, 967.4, 1086.6", \ + "1125.5, 1125.5, 1125.5, 1185.1, 1304.3", \ + "1557.7, 1557.7, 1557.7, 1617.3, 1736.5", \ + "2421.4, 2421.4, 2421.4, 2481.0, 2600.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("681.8, 681.8, 681.8, 741.4, 860.6", \ + "742.9, 742.9, 742.9, 802.5, 921.7", \ + "862.5, 862.5, 862.5, 922.1, 1041.3", \ + "1097.0, 1097.0, 1097.0, 1156.6, 1275.8", \ + "1559.9, 1559.9, 1559.9, 1619.5, 1738.7"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("702.6, 702.6, 702.6, 762.2, 881.4", \ + "819.8, 819.8, 819.8, 879.4, 998.6", \ + "1041.6, 1041.6, 1041.6, 1101.2, 1220.4", \ + "1476.5, 1476.5, 1476.5, 1536.1, 1655.2", \ + "2340.2, 2340.2, 2340.2, 2399.8, 2519.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("636.4, 636.4, 636.4, 696.0, 815.2", \ + "675.1, 675.1, 675.1, 734.7, 853.9", \ + "749.0, 749.0, 749.0, 808.6, 927.8", \ + "890.3, 890.3, 890.3, 949.9, 1069.1", \ + "1165.2, 1165.2, 1165.2, 1224.8, 1344.0"); + } + } + } + } + + cell (nmx2_x1) { + area : 0.0 ; + cell_leakage_power : 1.6 ; + leakage_power () { + when : "(i1 & i0 & cmd)" ; + value : 3.1 ; + } + leakage_power () { + when : "(i1 & !(i0) & cmd)" ; + value : 3.2 ; + } + leakage_power () { + when : "(cmd & !(i1))" ; + value : 0.62 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 2.5 ; + } + leakage_power () { + when : "(i1 & !(i0) & !(cmd))" ; + value : 0.00024 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & !(cmd))" ; + value : 0.00015 ; + } + pin (i1) { + direction : input ; + capacitance : 5.41 ; + } + pin (i0) { + direction : input ; + capacitance : 5.22 ; + } + pin (cmd) { + direction : input ; + capacitance : 7.80 ; + } + pin (nq) { + function : "((!(i1) & (!(i0) | cmd)) | (!(i0) & !(cmd)))" ; + direction : output ; + capacitance : 4.67 ; + timing (maxd_nq_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("68.7, 68.7, 68.7, 88.7, 125.8", \ + "78.0, 78.0, 78.0, 98.3, 136.2", \ + "88.2, 88.2, 88.2, 109.0, 147.8", \ + "100.1, 100.1, 100.1, 121.5, 162.0", \ + "117.0, 117.0, 117.0, 139.1, 181.4"); + } + rise_transition (inslew_load_5x5__14) { + values ("56.9, 56.9, 56.9, 88.7, 152.7", \ + "73.6, 73.6, 73.6, 105.5, 168.7", \ + "102.3, 102.3, 102.3, 133.8, 196.9", \ + "154.4, 154.4, 154.4, 185.7, 248.4", \ + "253.9, 253.9, 253.9, 285.5, 348.1"); + } + cell_fall (inslew_load_5x5__14) { + values ("59.0, 59.0, 59.0, 72.5, 95.0", \ + "64.8, 64.8, 64.8, 79.3, 103.5", \ + "70.8, 70.8, 70.8, 86.6, 113.4", \ + "77.1, 77.1, 77.1, 94.4, 124.4", \ + "86.2, 86.2, 86.2, 104.4, 137.7"); + } + fall_transition (inslew_load_5x5__14) { + values ("34.8, 34.8, 34.8, 46.5, 68.5", \ + "42.3, 42.3, 42.3, 54.3, 76.8", \ + "56.5, 56.5, 56.5, 68.9, 92.1", \ + "84.3, 84.3, 84.3, 96.8, 121.0", \ + "138.2, 138.2, 138.2, 151.6, 176.8"); + } + } + timing (maxd_nq_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__14) { + values ("35.1, 35.1, 35.1, 55.2, 92.7", \ + "50.2, 50.2, 50.2, 71.2, 110.4", \ + "75.5, 75.5, 75.5, 97.5, 138.9", \ + "123.2, 123.2, 123.2, 146.0, 189.6", \ + "217.0, 217.0, 217.0, 240.2, 285.6"); + } + rise_transition (inslew_load_5x5__14) { + values ("63.8, 63.8, 63.8, 95.7, 159.2", \ + "108.8, 108.8, 108.8, 140.2, 203.4", \ + "191.5, 191.5, 191.5, 223.1, 285.7", \ + "353.1, 353.1, 353.1, 384.9, 448.0", \ + "674.3, 674.3, 674.3, 706.3, 769.8"); + } + cell_fall (inslew_load_5x5__14) { + values ("13.0, 13.0, 13.0, 24.7, 44.2", \ + "7.9, 7.9, 7.9, 22.0, 45.2", \ + "-4.9, -4.9, -4.9, 11.4, 39.4", \ + "-32.8, -32.8, -32.8, -14.4, 18.1", \ + "-89.9, -89.9, -89.9, -70.3, -33.8"); + } + fall_transition (inslew_load_5x5__14) { + values ("23.4, 23.4, 23.4, 34.7, 56.3", \ + "35.2, 35.2, 35.2, 47.2, 69.7", \ + "57.4, 57.4, 57.4, 70.2, 94.2", \ + "101.0, 101.0, 101.0, 114.5, 140.1", \ + "187.6, 187.6, 187.6, 201.5, 228.5"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__14) { + values ("63.8, 63.8, 63.8, 82.0, 117.8", \ + "76.7, 76.7, 76.7, 95.1, 131.3", \ + "99.7, 99.7, 99.7, 118.4, 155.6", \ + "145.0, 145.0, 145.0, 164.0, 201.5", \ + "234.9, 234.9, 234.9, 254.1, 292.1"); + } + rise_transition (inslew_load_5x5__14) { + values ("122.7, 122.7, 122.7, 154.0, 217.2", \ + "171.6, 171.6, 171.6, 202.6, 265.1", \ + "265.6, 265.6, 265.6, 296.1, 357.8", \ + "452.3, 452.3, 452.3, 482.5, 543.3", \ + "825.6, 825.6, 825.6, 855.6, 915.8"); + } + cell_fall (inslew_load_5x5__14) { + values ("22.9, 22.9, 22.9, 32.1, 49.1", \ + "21.1, 21.1, 21.1, 31.5, 50.5", \ + "14.7, 14.7, 14.7, 26.4, 48.0", \ + "-0.6, -0.6, -0.6, 12.2, 36.5", \ + "-33.2, -33.2, -33.2, -19.4, 6.9"); + } + fall_transition (inslew_load_5x5__14) { + values ("36.8, 36.8, 36.8, 47.4, 68.7", \ + "51.5, 51.5, 51.5, 62.3, 83.6", \ + "80.0, 80.0, 80.0, 91.2, 112.9", \ + "136.1, 136.1, 136.1, 147.6, 170.0", \ + "247.7, 247.7, 247.7, 259.4, 282.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__14) { + values ("63.8, 63.8, 63.8, 82.0, 117.8", \ + "76.7, 76.7, 76.7, 95.1, 131.3", \ + "99.7, 99.7, 99.7, 118.4, 155.6", \ + "145.0, 145.0, 145.0, 164.0, 201.5", \ + "234.9, 234.9, 234.9, 254.1, 292.1"); + } + rise_transition (inslew_load_5x5__14) { + values ("122.7, 122.7, 122.7, 154.0, 217.2", \ + "171.6, 171.6, 171.6, 202.6, 265.1", \ + "265.6, 265.6, 265.6, 296.1, 357.8", \ + "452.3, 452.3, 452.3, 482.5, 543.3", \ + "825.6, 825.6, 825.6, 855.6, 915.8"); + } + cell_fall (inslew_load_5x5__14) { + values ("22.9, 22.9, 22.9, 32.1, 49.1", \ + "21.1, 21.1, 21.1, 31.5, 50.5", \ + "14.7, 14.7, 14.7, 26.4, 48.0", \ + "-0.6, -0.6, -0.6, 12.2, 36.5", \ + "-33.2, -33.2, -33.2, -19.4, 6.9"); + } + fall_transition (inslew_load_5x5__14) { + values ("36.8, 36.8, 36.8, 47.4, 68.7", \ + "51.5, 51.5, 51.5, 62.3, 83.6", \ + "80.0, 80.0, 80.0, 91.2, 112.9", \ + "136.1, 136.1, 136.1, 147.6, 170.0", \ + "247.7, 247.7, 247.7, 259.4, 282.4"); + } + } + internal_power (energy_pos_nq_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__14) { + values ("246.2, 246.2, 246.2, 304.6, 421.5", \ + "293.9, 293.9, 293.9, 352.3, 469.1", \ + "386.7, 386.7, 386.7, 445.1, 561.9", \ + "569.8, 569.8, 569.8, 628.3, 745.1", \ + "933.8, 933.8, 933.8, 992.2, 1109.0"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("257.9, 257.9, 257.9, 316.4, 433.2", \ + "310.9, 310.9, 310.9, 369.3, 486.1", \ + "415.3, 415.3, 415.3, 473.7, 590.6", \ + "623.0, 623.0, 623.0, 681.4, 798.3", \ + "1037.7, 1037.7, 1037.7, 1096.1, 1212.9"); + } + } + internal_power (energy_neg_nq_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__14) { + values ("115.3, 115.3, 115.3, 173.7, 290.6", \ + "173.8, 173.8, 173.8, 232.2, 349.1", \ + "290.8, 290.8, 290.8, 349.3, 466.1", \ + "524.9, 524.9, 524.9, 583.3, 700.1", \ + "992.9, 992.9, 992.9, 1051.3, 1168.1"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("87.1, 87.1, 87.1, 145.5, 262.3", \ + "114.1, 114.1, 114.1, 172.5, 289.4", \ + "168.2, 168.2, 168.2, 226.6, 343.5", \ + "276.4, 276.4, 276.4, 334.8, 451.6", \ + "492.8, 492.8, 492.8, 551.2, 668.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__14) { + values ("224.5, 224.5, 224.5, 282.9, 399.7", \ + "303.3, 303.3, 303.3, 361.7, 478.5", \ + "460.9, 460.9, 460.9, 519.3, 636.2", \ + "776.2, 776.2, 776.2, 834.6, 951.4", \ + "1406.7, 1406.7, 1406.7, 1465.1, 1581.9"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("168.3, 168.3, 168.3, 226.7, 343.6", \ + "214.7, 214.7, 214.7, 273.1, 389.9", \ + "307.4, 307.4, 307.4, 365.8, 482.6", \ + "492.8, 492.8, 492.8, 551.2, 668.0", \ + "863.6, 863.6, 863.6, 922.0, 1038.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__14) { + values ("224.5, 224.5, 224.5, 282.9, 399.7", \ + "303.3, 303.3, 303.3, 361.7, 478.5", \ + "460.9, 460.9, 460.9, 519.3, 636.2", \ + "776.2, 776.2, 776.2, 834.6, 951.4", \ + "1406.7, 1406.7, 1406.7, 1465.1, 1581.9"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("168.3, 168.3, 168.3, 226.7, 343.6", \ + "214.7, 214.7, 214.7, 273.1, 389.9", \ + "307.4, 307.4, 307.4, 365.8, 482.6", \ + "492.8, 492.8, 492.8, 551.2, 668.0", \ + "863.6, 863.6, 863.6, 922.0, 1038.9"); + } + } + } + } + + cell (nmx2_x4) { + area : 0.0 ; + cell_leakage_power : 2.8 ; + leakage_power () { + when : "(cmd & i1)" ; + value : 5.3 ; + } + leakage_power () { + when : "(cmd & !(i1))" ; + value : 2 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 3.6 ; + } + leakage_power () { + when : "(!(cmd) & !(i0))" ; + value : 0.26 ; + } + pin (i1) { + direction : input ; + capacitance : 3.31 ; + } + pin (i0) { + direction : input ; + capacitance : 3.45 ; + } + pin (cmd) { + direction : input ; + capacitance : 5.98 ; + } + pin (nq) { + function : "((!(i0) & (!(i1) | !(cmd))) | (!(i1) & cmd))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("143.5, 143.5, 143.5, 149.3, 159.9", \ + "151.1, 151.1, 151.1, 157.1, 167.7", \ + "158.1, 158.1, 158.1, 164.1, 174.9", \ + "163.2, 163.2, 163.2, 169.2, 180.3", \ + "164.6, 164.6, 164.6, 170.6, 182.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("44.4, 44.4, 44.4, 52.1, 67.0", \ + "47.4, 47.4, 47.4, 55.1, 70.1", \ + "52.5, 52.5, 52.5, 60.1, 75.2", \ + "61.4, 61.4, 61.4, 69.0, 84.1", \ + "77.9, 77.9, 77.9, 85.6, 100.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("141.3, 141.3, 141.3, 146.7, 156.6", \ + "152.2, 152.2, 152.2, 157.6, 167.6", \ + "166.5, 166.5, 166.5, 172.1, 182.0", \ + "187.4, 187.4, 187.4, 193.2, 203.2", \ + "219.7, 219.7, 219.7, 225.6, 236.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("36.9, 36.9, 36.9, 40.5, 47.3", \ + "38.9, 38.9, 38.9, 42.5, 49.4", \ + "42.5, 42.5, 42.5, 46.1, 53.1", \ + "49.2, 49.2, 49.2, 52.7, 59.8", \ + "61.9, 61.9, 61.9, 65.5, 72.5"); + } + } + timing (maxd_nq_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("123.1, 123.1, 123.1, 129.0, 139.7", \ + "140.4, 140.4, 140.4, 146.5, 157.3", \ + "167.4, 167.4, 167.4, 173.3, 184.6", \ + "212.5, 212.5, 212.5, 218.7, 230.2", \ + "295.2, 295.2, 295.2, 301.5, 313.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("47.3, 47.3, 47.3, 55.0, 70.0", \ + "55.6, 55.6, 55.6, 63.3, 78.3", \ + "70.6, 70.6, 70.6, 78.3, 93.4", \ + "98.7, 98.7, 98.7, 106.4, 121.7", \ + "153.3, 153.3, 153.3, 160.9, 176.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("94.0, 94.0, 94.0, 99.3, 109.2", \ + "97.1, 97.1, 97.1, 102.5, 112.4", \ + "95.2, 95.2, 95.2, 100.8, 110.7", \ + "81.8, 81.8, 81.8, 87.6, 97.7", \ + "45.2, 45.2, 45.2, 51.2, 62.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("34.5, 34.5, 34.5, 38.1, 44.9", \ + "37.5, 37.5, 37.5, 41.0, 47.8", \ + "42.5, 42.5, 42.5, 46.1, 53.1", \ + "51.8, 51.8, 51.8, 55.4, 62.4", \ + "69.4, 69.4, 69.4, 73.0, 80.1"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("149.0, 149.0, 149.0, 155.0, 166.0", \ + "161.9, 161.9, 161.9, 167.9, 179.1", \ + "183.5, 183.5, 183.5, 189.6, 201.0", \ + "223.2, 223.2, 223.2, 229.4, 241.1", \ + "296.9, 296.9, 296.9, 303.2, 315.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("58.2, 58.2, 58.2, 65.9, 80.9", \ + "66.8, 66.8, 66.8, 74.4, 89.5", \ + "83.0, 83.0, 83.0, 90.8, 106.0", \ + "114.5, 114.5, 114.5, 122.3, 137.6", \ + "177.0, 177.0, 177.0, 184.7, 200.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("102.4, 102.4, 102.4, 107.8, 117.7", \ + "107.0, 107.0, 107.0, 112.5, 122.4", \ + "110.5, 110.5, 110.5, 116.2, 126.1", \ + "110.3, 110.3, 110.3, 116.2, 126.5", \ + "101.9, 101.9, 101.9, 107.9, 119.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("37.0, 37.0, 37.0, 40.6, 47.4", \ + "40.2, 40.2, 40.2, 43.7, 50.6", \ + "46.0, 46.0, 46.0, 49.6, 56.7", \ + "57.2, 57.2, 57.2, 60.9, 67.9", \ + "78.9, 78.9, 78.9, 82.6, 89.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("149.0, 149.0, 149.0, 155.0, 166.0", \ + "161.9, 161.9, 161.9, 167.9, 179.1", \ + "183.5, 183.5, 183.5, 189.6, 201.0", \ + "223.2, 223.2, 223.2, 229.4, 241.1", \ + "296.9, 296.9, 296.9, 303.2, 315.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("58.2, 58.2, 58.2, 65.9, 80.9", \ + "66.8, 66.8, 66.8, 74.4, 89.5", \ + "83.0, 83.0, 83.0, 90.8, 106.0", \ + "114.5, 114.5, 114.5, 122.3, 137.6", \ + "177.0, 177.0, 177.0, 184.7, 200.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("102.4, 102.4, 102.4, 107.8, 117.7", \ + "107.0, 107.0, 107.0, 112.5, 122.4", \ + "110.5, 110.5, 110.5, 116.2, 126.1", \ + "110.3, 110.3, 110.3, 116.2, 126.5", \ + "101.9, 101.9, 101.9, 107.9, 119.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("37.0, 37.0, 37.0, 40.6, 47.4", \ + "40.2, 40.2, 40.2, 43.7, 50.6", \ + "46.0, 46.0, 46.0, 49.6, 56.7", \ + "57.2, 57.2, 57.2, 60.9, 67.9", \ + "78.9, 78.9, 78.9, 82.6, 89.6"); + } + } + internal_power (energy_pos_nq_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__1) { + values ("684.4, 684.4, 684.4, 744.0, 863.2", \ + "742.2, 742.2, 742.2, 801.8, 921.0", \ + "849.0, 849.0, 849.0, 908.6, 1027.8", \ + "1053.5, 1053.5, 1053.5, 1113.1, 1232.3", \ + "1454.7, 1454.7, 1454.7, 1514.3, 1633.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("734.2, 734.2, 734.2, 793.8, 913.0", \ + "805.1, 805.1, 805.1, 864.7, 983.9", \ + "941.7, 941.7, 941.7, 1001.3, 1120.5", \ + "1209.3, 1209.3, 1209.3, 1268.9, 1388.1", \ + "1738.7, 1738.7, 1738.7, 1798.3, 1917.5"); + } + } + internal_power (energy_neg_nq_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__1) { + values ("610.0, 610.0, 610.0, 669.6, 788.8", \ + "706.7, 706.7, 706.7, 766.3, 885.5", \ + "890.6, 890.6, 890.6, 950.2, 1069.4", \ + "1248.5, 1248.5, 1248.5, 1308.1, 1427.3", \ + "1956.7, 1956.7, 1956.7, 2016.3, 2135.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("576.6, 576.6, 576.6, 636.2, 755.3", \ + "623.9, 623.9, 623.9, 683.5, 802.7", \ + "711.2, 711.2, 711.2, 770.8, 890.0", \ + "877.6, 877.6, 877.6, 937.2, 1056.4", \ + "1202.5, 1202.5, 1202.5, 1262.1, 1381.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("756.8, 756.8, 756.8, 816.4, 935.6", \ + "868.1, 868.1, 868.1, 927.7, 1046.9", \ + "1085.9, 1085.9, 1085.9, 1145.5, 1264.7", \ + "1517.6, 1517.6, 1517.6, 1577.2, 1696.4", \ + "2379.6, 2379.6, 2379.6, 2439.2, 2558.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("651.2, 651.2, 651.2, 710.8, 830.0", \ + "712.5, 712.5, 712.5, 772.1, 891.3", \ + "831.9, 831.9, 831.9, 891.5, 1010.7", \ + "1066.1, 1066.1, 1066.1, 1125.7, 1244.9", \ + "1528.5, 1528.5, 1528.5, 1588.1, 1707.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("756.8, 756.8, 756.8, 816.4, 935.6", \ + "868.1, 868.1, 868.1, 927.7, 1046.9", \ + "1085.9, 1085.9, 1085.9, 1145.5, 1264.7", \ + "1517.6, 1517.6, 1517.6, 1577.2, 1696.4", \ + "2379.6, 2379.6, 2379.6, 2439.2, 2558.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("651.2, 651.2, 651.2, 710.8, 830.0", \ + "712.5, 712.5, 712.5, 772.1, 891.3", \ + "831.9, 831.9, 831.9, 891.5, 1010.7", \ + "1066.1, 1066.1, 1066.1, 1125.7, 1244.9", \ + "1528.5, 1528.5, 1528.5, 1588.1, 1707.3"); + } + } + } + } + + cell (nmx3_x1) { + area : 0.0 ; + cell_leakage_power : 5.2 ; + leakage_power () { + when : "(cmd0 & cmd1 & i1)" ; + value : 13 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i1))" ; + value : 11 ; + } + leakage_power () { + when : "((cmd0 ^ cmd1) & i0 & i2)" ; + value : 7.2 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i0) & i2) | (!(cmd0) & cmd1 & i0 & !(i2)))" ; + value : 6.9 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i2)) | (!(cmd0) & cmd1 & !(i0)))" ; + value : 5.7 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & i1)" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & !(i1))" ; + value : 1.2 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & !(i0) & i2)" ; + value : 0.00017 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & !(i0) & !(i2))" ; + value : 0.00012 ; + } + pin (i2) { + direction : input ; + capacitance : 2.95 ; + } + pin (i1) { + direction : input ; + capacitance : 3.03 ; + } + pin (i0) { + direction : input ; + capacitance : 2.92 ; + } + pin (cmd1) { + direction : input ; + capacitance : 5.64 ; + } + pin (cmd0) { + direction : input ; + capacitance : 5.08 ; + } + pin (nq) { + function : "((!(i0) & ((!(i2) & (!(cmd0) | !(i1) | !(cmd1))) | !(cmd0) | (!(i1) & cmd1))) | (!(i2) & cmd0 & (!(i1) | !(cmd1))) | (cmd0 & !(i1) & cmd1))" ; + direction : output ; + capacitance : 5.66 ; + timing (maxd_nq_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__15) { + values ("174.0, 174.0, 174.0, 234.1, 354.5", \ + "182.0, 182.0, 182.0, 242.1, 362.4", \ + "190.0, 190.0, 190.0, 250.2, 370.5", \ + "198.8, 198.8, 198.8, 259.7, 380.0", \ + "211.9, 211.9, 211.9, 273.0, 394.1"); + } + rise_transition (inslew_load_5x5__15) { + values ("260.2, 260.2, 260.2, 367.7, 583.0", \ + "281.9, 281.9, 281.9, 389.2, 604.4", \ + "318.5, 318.5, 318.5, 425.3, 640.1", \ + "385.8, 385.8, 385.8, 492.6, 706.7", \ + "515.2, 515.2, 515.2, 622.3, 836.1"); + } + cell_fall (inslew_load_5x5__15) { + values ("93.1, 93.1, 93.1, 115.7, 159.0", \ + "103.0, 103.0, 103.0, 126.6, 170.9", \ + "117.1, 117.1, 117.1, 142.1, 188.7", \ + "139.1, 139.1, 139.1, 166.2, 216.4", \ + "177.9, 177.9, 177.9, 207.0, 261.7"); + } + fall_transition (inslew_load_5x5__15) { + values ("82.5, 82.5, 82.5, 111.5, 170.0", \ + "94.3, 94.3, 94.3, 123.1, 181.2", \ + "116.5, 116.5, 116.5, 145.5, 203.4", \ + "160.0, 160.0, 160.0, 189.2, 246.9", \ + "245.7, 245.7, 245.7, 275.4, 334.0"); + } + } + timing (maxd_nq_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__15) { + values ("98.6, 98.6, 98.6, 159.9, 281.8", \ + "106.6, 106.6, 106.6, 168.3, 290.2", \ + "113.5, 113.5, 113.5, 176.4, 298.8", \ + "123.0, 123.0, 123.0, 187.5, 311.4", \ + "135.3, 135.3, 135.3, 202.3, 329.4"); + } + rise_transition (inslew_load_5x5__15) { + values ("120.3, 120.3, 120.3, 231.1, 454.4", \ + "137.1, 137.1, 137.1, 247.2, 470.0", \ + "161.9, 161.9, 161.9, 271.3, 492.7", \ + "211.5, 211.5, 211.5, 319.1, 538.1", \ + "305.3, 305.3, 305.3, 413.4, 628.0"); + } + cell_fall (inslew_load_5x5__15) { + values ("81.2, 81.2, 81.2, 113.5, 171.4", \ + "89.2, 89.2, 89.2, 124.0, 184.6", \ + "98.7, 98.7, 98.7, 137.4, 203.1", \ + "110.5, 110.5, 110.5, 154.6, 228.9", \ + "126.5, 126.5, 126.5, 176.9, 263.0"); + } + fall_transition (inslew_load_5x5__15) { + values ("67.4, 67.4, 67.4, 109.6, 194.6", \ + "76.7, 76.7, 76.7, 119.4, 204.2", \ + "93.9, 93.9, 93.9, 137.5, 222.1", \ + "126.4, 126.4, 126.4, 171.3, 257.8", \ + "189.7, 189.7, 189.7, 236.0, 325.4"); + } + } + timing (maxd_nq_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("95.9, 95.9, 95.9, 135.2, 213.6", \ + "105.4, 105.4, 105.4, 145.1, 223.9", \ + "122.3, 122.3, 122.3, 162.9, 242.3", \ + "154.4, 154.4, 154.4, 195.7, 277.4", \ + "216.8, 216.8, 216.8, 259.1, 342.3"); + } + rise_transition (inslew_load_5x5__15) { + values ("185.0, 185.0, 185.0, 257.1, 401.9", \ + "227.1, 227.1, 227.1, 298.4, 442.5", \ + "309.6, 309.6, 309.6, 379.8, 521.9", \ + "475.6, 475.6, 475.6, 544.6, 684.1", \ + "809.0, 809.0, 809.0, 877.2, 1014.4"); + } + cell_fall (inslew_load_5x5__15) { + values ("58.3, 58.3, 58.3, 85.6, 139.6", \ + "60.1, 60.1, 60.1, 88.2, 143.0", \ + "61.2, 61.2, 61.2, 90.9, 147.7", \ + "60.1, 60.1, 60.1, 91.9, 152.3", \ + "54.4, 54.4, 54.4, 88.3, 153.0"); + } + fall_transition (inslew_load_5x5__15) { + values ("97.5, 97.5, 97.5, 139.8, 225.1", \ + "118.3, 118.3, 118.3, 160.0, 244.2", \ + "159.4, 159.4, 159.4, 200.9, 283.6", \ + "241.4, 241.4, 241.4, 282.7, 365.7", \ + "405.0, 405.0, 405.0, 446.5, 529.0"); + } + } + timing (maxd_nq_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("77.3, 77.3, 77.3, 139.1, 261.4", \ + "91.7, 91.7, 91.7, 155.4, 278.5", \ + "119.0, 119.0, 119.0, 185.2, 311.2", \ + "168.0, 168.0, 168.0, 237.1, 368.2", \ + "261.0, 261.0, 261.0, 332.9, 470.8"); + } + rise_transition (inslew_load_5x5__15) { + values ("136.6, 136.6, 136.6, 246.8, 469.9", \ + "178.7, 178.7, 178.7, 287.4, 508.5", \ + "262.8, 262.8, 262.8, 370.5, 586.7", \ + "426.7, 426.7, 426.7, 532.9, 747.4", \ + "750.8, 750.8, 750.8, 857.0, 1069.2"); + } + cell_fall (inslew_load_5x5__15) { + values ("39.0, 39.0, 39.0, 69.0, 124.6", \ + "39.6, 39.6, 39.6, 73.5, 133.2", \ + "33.1, 33.1, 33.1, 73.5, 141.5", \ + "12.2, 12.2, 12.2, 60.0, 140.8", \ + "-36.7, -36.7, -36.7, 17.7, 113.2"); + } + fall_transition (inslew_load_5x5__15) { + values ("57.1, 57.1, 57.1, 99.8, 185.9", \ + "71.5, 71.5, 71.5, 114.1, 199.0", \ + "97.2, 97.2, 97.2, 141.5, 226.7", \ + "145.9, 145.9, 145.9, 192.2, 280.7", \ + "240.8, 240.8, 240.8, 289.1, 381.8"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("56.8, 56.8, 56.8, 97.9, 177.6", \ + "69.7, 69.7, 69.7, 112.9, 194.6", \ + "90.5, 90.5, 90.5, 136.6, 222.4", \ + "127.8, 127.8, 127.8, 177.1, 268.9", \ + "199.2, 199.2, 199.2, 250.9, 349.2"); + } + rise_transition (inslew_load_5x5__15) { + values ("102.1, 102.1, 102.1, 174.7, 323.5", \ + "141.6, 141.6, 141.6, 213.7, 358.9", \ + "216.4, 216.4, 216.4, 288.1, 432.2", \ + "362.9, 362.9, 362.9, 435.3, 578.5", \ + "653.7, 653.7, 653.7, 726.9, 871.7"); + } + cell_fall (inslew_load_5x5__15) { + values ("32.6, 32.6, 32.6, 56.8, 100.6", \ + "32.5, 32.5, 32.5, 60.7, 109.0", \ + "26.8, 26.8, 26.8, 60.0, 116.2", \ + "9.6, 9.6, 9.6, 48.1, 114.5", \ + "-29.3, -29.3, -29.3, 13.5, 90.5"); + } + fall_transition (inslew_load_5x5__15) { + values ("44.5, 44.5, 44.5, 73.8, 133.0", \ + "59.3, 59.3, 59.3, 89.2, 147.6", \ + "86.6, 86.6, 86.6, 118.0, 177.8", \ + "139.2, 139.2, 139.2, 172.3, 235.0", \ + "242.6, 242.6, 242.6, 277.2, 343.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("117.1, 117.1, 117.1, 177.8, 299.1", \ + "132.0, 132.0, 132.0, 193.3, 314.8", \ + "157.9, 157.9, 157.9, 219.9, 342.3", \ + "206.5, 206.5, 206.5, 269.8, 394.3", \ + "302.2, 302.2, 302.2, 366.7, 493.4"); + } + rise_transition (inslew_load_5x5__15) { + values ("212.5, 212.5, 212.5, 321.3, 540.2", \ + "261.8, 261.8, 261.8, 369.9, 587.8", \ + "354.5, 354.5, 354.5, 461.3, 677.3", \ + "538.8, 538.8, 538.8, 643.7, 856.4", \ + "908.0, 908.0, 908.0, 1011.6, 1220.6"); + } + cell_fall (inslew_load_5x5__15) { + values ("49.2, 49.2, 49.2, 77.2, 131.7", \ + "49.9, 49.9, 49.9, 80.3, 136.9", \ + "46.1, 46.1, 46.1, 80.3, 142.0", \ + "31.7, 31.7, 31.7, 70.6, 140.5", \ + "-3.7, -3.7, -3.7, 39.6, 119.1"); + } + fall_transition (inslew_load_5x5__15) { + values ("76.6, 76.6, 76.6, 118.7, 204.4", \ + "92.3, 92.3, 92.3, 134.3, 218.1", \ + "122.5, 122.5, 122.5, 164.8, 248.1", \ + "181.0, 181.0, 181.0, 224.2, 308.9", \ + "295.9, 295.9, 295.9, 340.4, 427.3"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("117.1, 117.1, 117.1, 177.8, 299.1", \ + "132.0, 132.0, 132.0, 193.3, 314.8", \ + "157.9, 157.9, 157.9, 219.9, 342.3", \ + "206.5, 206.5, 206.5, 269.8, 394.3", \ + "302.2, 302.2, 302.2, 366.7, 493.4"); + } + rise_transition (inslew_load_5x5__15) { + values ("212.5, 212.5, 212.5, 321.3, 540.2", \ + "261.8, 261.8, 261.8, 369.9, 587.8", \ + "354.5, 354.5, 354.5, 461.3, 677.3", \ + "538.8, 538.8, 538.8, 643.7, 856.4", \ + "908.0, 908.0, 908.0, 1011.6, 1220.6"); + } + cell_fall (inslew_load_5x5__15) { + values ("49.2, 49.2, 49.2, 77.2, 131.7", \ + "49.9, 49.9, 49.9, 80.3, 136.9", \ + "46.1, 46.1, 46.1, 80.3, 142.0", \ + "31.7, 31.7, 31.7, 70.6, 140.5", \ + "-3.7, -3.7, -3.7, 39.6, 119.1"); + } + fall_transition (inslew_load_5x5__15) { + values ("76.6, 76.6, 76.6, 118.7, 204.4", \ + "92.3, 92.3, 92.3, 134.3, 218.1", \ + "122.5, 122.5, 122.5, 164.8, 248.1", \ + "181.0, 181.0, 181.0, 224.2, 308.9", \ + "295.9, 295.9, 295.9, 340.4, 427.3"); + } + } + internal_power (energy_pos_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__15) { + values ("254.2, 254.2, 254.2, 325.0, 466.5", \ + "284.2, 284.2, 284.2, 355.0, 496.5", \ + "342.6, 342.6, 342.6, 413.4, 554.9", \ + "458.3, 458.3, 458.3, 529.1, 670.6", \ + "688.6, 688.6, 688.6, 759.3, 900.8"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("262.2, 262.2, 262.2, 333.0, 474.5", \ + "306.5, 306.5, 306.5, 377.2, 518.8", \ + "393.3, 393.3, 393.3, 464.1, 605.6", \ + "566.0, 566.0, 566.0, 636.7, 778.2", \ + "910.6, 910.6, 910.6, 981.4, 1122.9"); + } + } + internal_power (energy_pos_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__15) { + values ("160.1, 160.1, 160.1, 230.9, 372.4", \ + "185.3, 185.3, 185.3, 256.0, 397.6", \ + "234.8, 234.8, 234.8, 305.6, 447.1", \ + "333.1, 333.1, 333.1, 403.9, 545.4", \ + "529.3, 529.3, 529.3, 600.0, 741.6"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("174.7, 174.7, 174.7, 245.5, 387.0", \ + "208.1, 208.1, 208.1, 278.8, 420.4", \ + "274.2, 274.2, 274.2, 345.0, 486.5", \ + "406.0, 406.0, 406.0, 476.7, 618.3", \ + "669.3, 669.3, 669.3, 740.1, 881.6"); + } + } + internal_power (energy_neg_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__15) { + values ("180.6, 180.6, 180.6, 251.3, 392.9", \ + "217.4, 217.4, 217.4, 288.2, 429.7", \ + "291.2, 291.2, 291.2, 361.9, 503.5", \ + "438.6, 438.6, 438.6, 509.4, 650.9", \ + "733.5, 733.5, 733.5, 804.3, 945.8"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("156.7, 156.7, 156.7, 227.5, 369.0", \ + "184.6, 184.6, 184.6, 255.4, 396.9", \ + "240.4, 240.4, 240.4, 311.2, 452.7", \ + "352.1, 352.1, 352.1, 422.9, 564.4", \ + "575.4, 575.4, 575.4, 646.2, 787.7"); + } + } + internal_power (energy_neg_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__15) { + values ("91.1, 91.1, 91.1, 161.8, 303.3", \ + "112.8, 112.8, 112.8, 183.6, 325.1", \ + "156.3, 156.3, 156.3, 227.1, 368.6", \ + "243.3, 243.3, 243.3, 314.1, 455.6", \ + "417.4, 417.4, 417.4, 488.1, 629.6"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("83.4, 83.4, 83.4, 154.1, 295.6", \ + "94.5, 94.5, 94.5, 165.3, 306.8", \ + "116.8, 116.8, 116.8, 187.5, 329.1", \ + "161.3, 161.3, 161.3, 232.1, 373.6", \ + "250.4, 250.4, 250.4, 321.2, 462.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__15) { + values ("96.8, 96.8, 96.8, 167.5, 309.1", \ + "124.2, 124.2, 124.2, 195.0, 336.5", \ + "179.2, 179.2, 179.2, 249.9, 391.5", \ + "289.0, 289.0, 289.0, 359.8, 501.3", \ + "508.8, 508.8, 508.8, 579.5, 721.1"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("88.3, 88.3, 88.3, 159.0, 300.5", \ + "104.3, 104.3, 104.3, 175.1, 316.6", \ + "136.4, 136.4, 136.4, 207.1, 348.7", \ + "200.5, 200.5, 200.5, 271.3, 412.8", \ + "328.8, 328.8, 328.8, 399.6, 541.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__15) { + values ("140.7, 140.7, 140.7, 211.5, 353.0", \ + "168.2, 168.2, 168.2, 239.0, 380.5", \ + "223.1, 223.1, 223.1, 293.9, 435.4", \ + "333.0, 333.0, 333.0, 403.8, 545.3", \ + "552.8, 552.8, 552.8, 623.5, 765.0"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("118.3, 118.3, 118.3, 189.0, 330.6", \ + "134.3, 134.3, 134.3, 205.1, 346.6", \ + "166.4, 166.4, 166.4, 237.2, 378.7", \ + "230.5, 230.5, 230.5, 301.3, 442.8", \ + "358.8, 358.8, 358.8, 429.6, 571.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__15) { + values ("140.7, 140.7, 140.7, 211.5, 353.0", \ + "168.2, 168.2, 168.2, 239.0, 380.5", \ + "223.1, 223.1, 223.1, 293.9, 435.4", \ + "333.0, 333.0, 333.0, 403.8, 545.3", \ + "552.8, 552.8, 552.8, 623.5, 765.0"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("118.3, 118.3, 118.3, 189.0, 330.6", \ + "134.3, 134.3, 134.3, 205.1, 346.6", \ + "166.4, 166.4, 166.4, 237.2, 378.7", \ + "230.5, 230.5, 230.5, 301.3, 442.8", \ + "358.8, 358.8, 358.8, 429.6, 571.1"); + } + } + } + } + + cell (nmx3_x4) { + area : 0.0 ; + cell_leakage_power : 7.1 ; + leakage_power () { + when : "(cmd0 & cmd1 & i1)" ; + value : 16 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i1))" ; + value : 12 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & i2) | (!(cmd0) & cmd1 & i0))" ; + value : 10 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i2)) | (!(cmd0) & cmd1 & !(i0)))" ; + value : 6 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & i1)" ; + value : 4.7 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0 & !(cmd1) & !(cmd0))" ; + value : 4.4 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0 & !(cmd1) & !(cmd0))" ; + value : 4.3 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & !(i0))" ; + value : 0.26 ; + } + pin (i2) { + direction : input ; + capacitance : 2.95 ; + } + pin (i1) { + direction : input ; + capacitance : 3.03 ; + } + pin (i0) { + direction : input ; + capacitance : 2.98 ; + } + pin (cmd1) { + direction : input ; + capacitance : 5.64 ; + } + pin (cmd0) { + direction : input ; + capacitance : 5.08 ; + } + pin (nq) { + function : "((!(i0) & ((!(i2) & (!(cmd0) | !(i1) | !(cmd1))) | !(cmd0) | (!(i1) & cmd1))) | (!(i2) & cmd0 & (!(i1) | !(cmd1))) | (cmd0 & !(i1) & cmd1))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("278.1, 278.1, 278.1, 284.2, 295.7", \ + "286.1, 286.1, 286.1, 292.3, 303.7", \ + "294.4, 294.4, 294.4, 300.5, 312.0", \ + "303.3, 303.3, 303.3, 309.5, 321.2", \ + "315.5, 315.5, 315.5, 321.8, 333.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("89.2, 89.2, 89.2, 96.9, 112.2", \ + "93.1, 93.1, 93.1, 100.9, 116.1", \ + "99.8, 99.8, 99.8, 107.5, 122.8", \ + "112.0, 112.0, 112.0, 119.8, 135.1", \ + "135.6, 135.6, 135.6, 143.3, 158.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("182.0, 182.0, 182.0, 187.7, 197.7", \ + "194.7, 194.7, 194.7, 200.5, 210.5", \ + "213.4, 213.4, 213.4, 219.2, 229.4", \ + "243.1, 243.1, 243.1, 249.0, 259.6", \ + "294.3, 294.3, 294.3, 300.4, 311.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("46.5, 46.5, 46.5, 50.0, 57.1", \ + "48.7, 48.7, 48.7, 52.3, 59.4", \ + "53.1, 53.1, 53.1, 56.7, 63.7", \ + "61.5, 61.5, 61.5, 65.1, 72.1", \ + "77.8, 77.8, 77.8, 81.4, 88.4"); + } + } + timing (maxd_nq_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("201.2, 201.2, 201.2, 207.2, 218.3", \ + "210.0, 210.0, 210.0, 216.0, 227.2", \ + "218.3, 218.3, 218.3, 224.3, 235.6", \ + "229.4, 229.4, 229.4, 235.5, 246.9", \ + "243.9, 243.9, 243.9, 250.0, 261.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("63.2, 63.2, 63.2, 70.8, 85.9", \ + "66.3, 66.3, 66.3, 74.0, 89.1", \ + "70.9, 70.9, 70.9, 78.6, 93.7", \ + "80.1, 80.1, 80.1, 87.8, 103.0", \ + "97.6, 97.6, 97.6, 105.3, 120.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("174.5, 174.5, 174.5, 180.1, 190.1", \ + "186.0, 186.0, 186.0, 191.7, 201.7", \ + "201.0, 201.0, 201.0, 206.8, 216.9", \ + "221.2, 221.2, 221.2, 227.1, 237.4", \ + "250.2, 250.2, 250.2, 256.1, 267.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("45.0, 45.0, 45.0, 48.5, 55.6", \ + "46.9, 46.9, 46.9, 50.5, 57.6", \ + "50.4, 50.4, 50.4, 54.0, 61.1", \ + "56.8, 56.8, 56.8, 60.4, 67.4", \ + "69.0, 69.0, 69.0, 72.6, 79.7"); + } + } + timing (maxd_nq_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("185.5, 185.5, 185.5, 191.5, 202.8", \ + "195.8, 195.8, 195.8, 201.9, 213.2", \ + "213.8, 213.8, 213.8, 219.9, 231.4", \ + "245.5, 245.5, 245.5, 251.7, 263.5", \ + "303.9, 303.9, 303.9, 310.3, 322.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("70.9, 70.9, 70.9, 78.6, 93.7", \ + "78.7, 78.7, 78.7, 86.5, 101.6", \ + "93.8, 93.8, 93.8, 101.6, 116.9", \ + "123.9, 123.9, 123.9, 131.6, 147.0", \ + "183.9, 183.9, 183.9, 191.5, 206.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("153.2, 153.2, 153.2, 159.1, 169.1", \ + "158.9, 158.9, 158.9, 164.8, 175.0", \ + "167.1, 167.1, 167.1, 173.0, 183.6", \ + "177.8, 177.8, 177.8, 183.8, 195.0", \ + "192.6, 192.6, 192.6, 198.7, 210.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("50.9, 50.9, 50.9, 54.5, 61.6", \ + "54.8, 54.8, 54.8, 58.5, 65.5", \ + "62.7, 62.7, 62.7, 66.4, 73.4", \ + "78.2, 78.2, 78.2, 81.8, 88.9", \ + "109.1, 109.1, 109.1, 112.6, 119.6"); + } + } + timing (maxd_nq_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("180.7, 180.7, 180.7, 186.6, 197.9", \ + "197.3, 197.3, 197.3, 203.3, 214.6", \ + "226.8, 226.8, 226.8, 232.9, 244.4", \ + "277.0, 277.0, 277.0, 283.2, 295.0", \ + "367.7, 367.7, 367.7, 374.0, 386.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("66.2, 66.2, 66.2, 73.9, 89.0", \ + "74.1, 74.1, 74.1, 81.8, 96.9", \ + "89.6, 89.6, 89.6, 97.4, 112.6", \ + "119.3, 119.3, 119.3, 127.0, 142.3", \ + "177.8, 177.8, 177.8, 185.4, 200.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("128.8, 128.8, 128.8, 134.4, 144.4", \ + "134.8, 134.8, 134.8, 140.5, 150.4", \ + "137.0, 137.0, 137.0, 142.9, 152.9", \ + "128.3, 128.3, 128.3, 134.2, 144.7", \ + "95.8, 95.8, 95.8, 101.8, 113.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("43.1, 43.1, 43.1, 46.6, 53.6", \ + "45.9, 45.9, 45.9, 49.4, 56.5", \ + "51.1, 51.1, 51.1, 54.7, 61.8", \ + "60.7, 60.7, 60.7, 64.4, 71.3", \ + "78.9, 78.9, 78.9, 82.6, 89.6"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("145.3, 145.3, 145.3, 151.3, 162.1", \ + "161.2, 161.2, 161.2, 167.2, 178.3", \ + "185.1, 185.1, 185.1, 191.2, 202.5", \ + "224.9, 224.9, 224.9, 231.1, 242.7", \ + "294.7, 294.7, 294.7, 301.0, 313.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("54.9, 54.9, 54.9, 62.5, 77.6", \ + "62.7, 62.7, 62.7, 70.3, 85.4", \ + "76.8, 76.8, 76.8, 84.5, 99.7", \ + "103.8, 103.8, 103.8, 111.6, 126.9", \ + "156.6, 156.6, 156.6, 164.3, 179.7"); + } + cell_fall (inslew_load_5x5__1) { + values ("114.4, 114.4, 114.4, 119.8, 129.8", \ + "120.2, 120.2, 120.2, 125.8, 135.8", \ + "123.0, 123.0, 123.0, 128.8, 138.7", \ + "117.6, 117.6, 117.6, 123.5, 133.9", \ + "95.0, 95.0, 95.0, 101.1, 112.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("38.9, 38.9, 38.9, 42.4, 49.3", \ + "41.9, 41.9, 41.9, 45.5, 52.5", \ + "47.5, 47.5, 47.5, 51.1, 58.2", \ + "57.9, 57.9, 57.9, 61.5, 68.5", \ + "77.7, 77.7, 77.7, 81.3, 88.3"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("220.7, 220.7, 220.7, 226.8, 238.2", \ + "236.3, 236.3, 236.3, 242.5, 253.9", \ + "262.8, 262.8, 262.8, 269.0, 280.6", \ + "310.5, 310.5, 310.5, 316.8, 328.8", \ + "401.4, 401.4, 401.4, 407.7, 420.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("80.4, 80.4, 80.4, 88.2, 103.3", \ + "89.4, 89.4, 89.4, 97.2, 112.4", \ + "106.2, 106.2, 106.2, 114.0, 129.3", \ + "139.5, 139.5, 139.5, 147.2, 162.6", \ + "205.6, 205.6, 205.6, 213.2, 228.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("141.2, 141.2, 141.2, 146.9, 156.9", \ + "146.1, 146.1, 146.1, 151.9, 162.0", \ + "149.6, 149.6, 149.6, 155.5, 165.8", \ + "146.5, 146.5, 146.5, 152.4, 163.2", \ + "128.0, 128.0, 128.0, 134.0, 145.4"); + } + fall_transition (inslew_load_5x5__1) { + values ("46.8, 46.8, 46.8, 50.3, 57.5", \ + "49.8, 49.8, 49.8, 53.4, 60.5", \ + "55.8, 55.8, 55.8, 59.4, 66.4", \ + "67.0, 67.0, 67.0, 70.6, 77.7", \ + "88.9, 88.9, 88.9, 92.5, 99.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("220.7, 220.7, 220.7, 226.8, 238.2", \ + "236.3, 236.3, 236.3, 242.5, 253.9", \ + "262.8, 262.8, 262.8, 269.0, 280.6", \ + "310.5, 310.5, 310.5, 316.8, 328.8", \ + "401.4, 401.4, 401.4, 407.7, 420.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("80.4, 80.4, 80.4, 88.2, 103.3", \ + "89.4, 89.4, 89.4, 97.2, 112.4", \ + "106.2, 106.2, 106.2, 114.0, 129.3", \ + "139.5, 139.5, 139.5, 147.2, 162.6", \ + "205.6, 205.6, 205.6, 213.2, 228.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("141.2, 141.2, 141.2, 146.9, 156.9", \ + "146.1, 146.1, 146.1, 151.9, 162.0", \ + "149.6, 149.6, 149.6, 155.5, 165.8", \ + "146.5, 146.5, 146.5, 152.4, 163.2", \ + "128.0, 128.0, 128.0, 134.0, 145.4"); + } + fall_transition (inslew_load_5x5__1) { + values ("46.8, 46.8, 46.8, 50.3, 57.5", \ + "49.8, 49.8, 49.8, 53.4, 60.5", \ + "55.8, 55.8, 55.8, 59.4, 66.4", \ + "67.0, 67.0, 67.0, 70.6, 77.7", \ + "88.9, 88.9, 88.9, 92.5, 99.5"); + } + } + internal_power (energy_pos_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1131.7, 1131.7, 1131.7, 1191.3, 1310.5", \ + "1194.3, 1194.3, 1194.3, 1253.9, 1373.1", \ + "1308.3, 1308.3, 1308.3, 1367.9, 1487.1", \ + "1526.6, 1526.6, 1526.6, 1586.2, 1705.4", \ + "1954.0, 1954.0, 1954.0, 2013.6, 2132.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("910.9, 910.9, 910.9, 970.5, 1089.7", \ + "980.4, 980.4, 980.4, 1040.0, 1159.2", \ + "1116.2, 1116.2, 1116.2, 1175.8, 1295.0", \ + "1382.9, 1382.9, 1382.9, 1442.5, 1561.7", \ + "1912.2, 1912.2, 1912.2, 1971.8, 2091.0"); + } + } + internal_power (energy_pos_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__1) { + values ("822.3, 822.3, 822.3, 881.9, 1001.1", \ + "873.0, 873.0, 873.0, 932.6, 1051.8", \ + "959.9, 959.9, 959.9, 1019.5, 1138.7", \ + "1134.1, 1134.1, 1134.1, 1193.7, 1312.9", \ + "1475.5, 1475.5, 1475.5, 1535.1, 1654.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("805.6, 805.6, 805.6, 865.2, 984.4", \ + "860.5, 860.5, 860.5, 920.1, 1039.3", \ + "965.5, 965.5, 965.5, 1025.1, 1144.3", \ + "1169.4, 1169.4, 1169.4, 1229.0, 1348.2", \ + "1570.7, 1570.7, 1570.7, 1630.3, 1749.5"); + } + } + internal_power (energy_neg_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__1) { + values ("905.5, 905.5, 905.5, 965.1, 1084.3", \ + "1006.9, 1006.9, 1006.9, 1066.5, 1185.7", \ + "1206.0, 1206.0, 1206.0, 1265.6, 1384.8", \ + "1605.0, 1605.0, 1605.0, 1664.6, 1783.8", \ + "2404.2, 2404.2, 2404.2, 2463.8, 2583.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("853.4, 853.4, 853.4, 913.0, 1032.2", \ + "925.6, 925.6, 925.6, 985.2, 1104.4", \ + "1070.3, 1070.3, 1070.3, 1129.9, 1249.1", \ + "1357.3, 1357.3, 1357.3, 1416.9, 1536.1", \ + "1929.8, 1929.8, 1929.8, 1989.4, 2108.6"); + } + } + internal_power (energy_neg_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__1) { + values ("778.0, 778.0, 778.0, 837.6, 956.8", \ + "863.8, 863.8, 863.8, 923.4, 1042.6", \ + "1036.2, 1036.2, 1036.2, 1095.8, 1215.0", \ + "1370.8, 1370.8, 1370.8, 1430.4, 1549.6", \ + "2036.7, 2036.7, 2036.7, 2096.2, 2215.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("692.5, 692.5, 692.5, 752.1, 871.3", \ + "735.1, 735.1, 735.1, 794.7, 913.9", \ + "815.8, 815.8, 815.8, 875.4, 994.6", \ + "968.6, 968.6, 968.6, 1028.2, 1147.4", \ + "1263.9, 1263.9, 1263.9, 1323.4, 1442.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("692.4, 692.4, 692.4, 752.0, 871.2", \ + "782.4, 782.4, 782.4, 842.0, 961.2", \ + "952.6, 952.6, 952.6, 1012.2, 1131.4", \ + "1287.5, 1287.5, 1287.5, 1347.1, 1466.3", \ + "1949.8, 1949.8, 1949.8, 2009.4, 2128.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("651.0, 651.0, 651.0, 710.6, 829.8", \ + "701.0, 701.0, 701.0, 760.6, 879.8", \ + "795.3, 795.3, 795.3, 854.9, 974.1", \ + "975.9, 975.9, 975.9, 1035.5, 1154.7", \ + "1328.1, 1328.1, 1328.1, 1387.7, 1506.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("944.2, 944.2, 944.2, 1003.8, 1123.0", \ + "1046.4, 1046.4, 1046.4, 1106.0, 1225.2", \ + "1241.5, 1241.5, 1241.5, 1301.1, 1420.3", \ + "1630.0, 1630.0, 1630.0, 1689.6, 1808.8", \ + "2406.7, 2406.7, 2406.7, 2466.3, 2585.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("769.0, 769.0, 769.0, 828.6, 947.8", \ + "819.2, 819.2, 819.2, 878.8, 998.0", \ + "917.7, 917.7, 917.7, 977.3, 1096.5", \ + "1109.0, 1109.0, 1109.0, 1168.6, 1287.8", \ + "1484.6, 1484.6, 1484.6, 1544.2, 1663.4"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("944.2, 944.2, 944.2, 1003.8, 1123.0", \ + "1046.4, 1046.4, 1046.4, 1106.0, 1225.2", \ + "1241.5, 1241.5, 1241.5, 1301.1, 1420.3", \ + "1630.0, 1630.0, 1630.0, 1689.6, 1808.8", \ + "2406.7, 2406.7, 2406.7, 2466.3, 2585.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("769.0, 769.0, 769.0, 828.6, 947.8", \ + "819.2, 819.2, 819.2, 878.8, 998.0", \ + "917.7, 917.7, 917.7, 977.3, 1096.5", \ + "1109.0, 1109.0, 1109.0, 1168.6, 1287.8", \ + "1484.6, 1484.6, 1484.6, 1544.2, 1663.4"); + } + } + } + } + + cell (no2_x1) { + area : 0.0 ; + cell_leakage_power : 1.2 ; + leakage_power () { + when : "i0" ; + value : 2.6 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 0.98 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.00012 ; + } + pin (i1) { + direction : input ; + capacitance : 4.91 ; + } + pin (i0) { + direction : input ; + capacitance : 4.91 ; + } + pin (nq) { + function : "(!(i0) & !(i1))" ; + direction : output ; + capacitance : 3.25 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("21.0, 21.0, 21.0, 33.7, 57.2", \ + "25.7, 25.7, 25.7, 39.6, 64.9", \ + "32.7, 32.7, 32.7, 47.6, 75.2", \ + "45.5, 45.5, 45.5, 60.9, 90.5", \ + "70.1, 70.1, 70.1, 86.0, 116.8"); + } + rise_transition (inslew_load_5x5__16) { + values ("47.1, 47.1, 47.1, 66.1, 104.4", \ + "78.2, 78.2, 78.2, 97.6, 135.7", \ + "137.6, 137.6, 137.6, 157.4, 196.1", \ + "254.9, 254.9, 254.9, 274.9, 314.2", \ + "488.7, 488.7, 488.7, 508.7, 548.6"); + } + cell_fall (inslew_load_5x5__16) { + values ("14.9, 14.9, 14.9, 25.1, 42.1", \ + "15.6, 15.6, 15.6, 27.4, 47.3", \ + "15.1, 15.1, 15.1, 28.2, 51.2", \ + "12.8, 12.8, 12.8, 26.7, 52.5", \ + "7.5, 7.5, 7.5, 21.9, 49.5"); + } + fall_transition (inslew_load_5x5__16) { + values ("20.8, 20.8, 20.8, 29.2, 44.6", \ + "36.7, 36.7, 36.7, 45.6, 61.9", \ + "67.2, 67.2, 67.2, 76.5, 93.9", \ + "127.4, 127.4, 127.4, 137.0, 155.4", \ + "247.0, 247.0, 247.0, 256.9, 276.0"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("33.6, 33.6, 33.6, 44.8, 66.5", \ + "30.9, 30.9, 30.9, 42.4, 64.8", \ + "24.0, 24.0, 24.0, 36.2, 59.8", \ + "8.9, 8.9, 8.9, 21.7, 46.6", \ + "-22.7, -22.7, -22.7, -9.3, 16.7"); + } + rise_transition (inslew_load_5x5__16) { + values ("77.2, 77.2, 77.2, 95.8, 133.4", \ + "102.6, 102.6, 102.6, 120.9, 157.9", \ + "151.8, 151.8, 151.8, 170.2, 207.8", \ + "250.7, 250.7, 250.7, 269.2, 305.9", \ + "448.1, 448.1, 448.1, 466.6, 503.7"); + } + cell_fall (inslew_load_5x5__16) { + values ("27.0, 27.0, 27.0, 35.6, 51.1", \ + "36.8, 36.8, 36.8, 46.4, 63.9", \ + "53.3, 53.3, 53.3, 63.8, 83.3", \ + "84.6, 84.6, 84.6, 95.7, 116.8", \ + "146.4, 146.4, 146.4, 157.8, 180.0"); + } + fall_transition (inslew_load_5x5__16) { + values ("30.5, 30.5, 30.5, 38.3, 53.5", \ + "52.9, 52.9, 52.9, 60.9, 76.4", \ + "95.6, 95.6, 95.6, 103.8, 119.9", \ + "179.7, 179.7, 179.7, 188.1, 204.7", \ + "347.3, 347.3, 347.3, 355.8, 372.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__16) { + values ("85.0, 85.0, 85.0, 125.6, 207.0", \ + "130.1, 130.1, 130.1, 170.8, 252.1", \ + "220.3, 220.3, 220.3, 261.0, 342.3", \ + "400.8, 400.8, 400.8, 441.5, 522.8", \ + "761.9, 761.9, 761.9, 802.5, 883.8"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("76.4, 76.4, 76.4, 117.1, 198.4", \ + "111.3, 111.3, 111.3, 152.0, 233.3", \ + "181.1, 181.1, 181.1, 221.7, 303.1", \ + "320.7, 320.7, 320.7, 361.3, 442.7", \ + "599.8, 599.8, 599.8, 640.5, 721.8"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__16) { + values ("152.4, 152.4, 152.4, 193.0, 274.4", \ + "195.2, 195.2, 195.2, 235.9, 317.2", \ + "280.8, 280.8, 280.8, 321.5, 402.8", \ + "452.1, 452.1, 452.1, 492.7, 574.1", \ + "794.6, 794.6, 794.6, 835.2, 916.6"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("135.7, 135.7, 135.7, 176.4, 257.7", \ + "196.7, 196.7, 196.7, 237.4, 318.7", \ + "318.7, 318.7, 318.7, 359.3, 440.7", \ + "562.6, 562.6, 562.6, 603.3, 684.6", \ + "1050.4, 1050.4, 1050.4, 1091.1, 1172.4"); + } + } + } + } + + cell (no2_x4) { + area : 0.0 ; + cell_leakage_power : 4 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 5.7 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 5.8 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 4.2 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.26 ; + } + pin (i1) { + direction : input ; + capacitance : 4.81 ; + } + pin (i0) { + direction : input ; + capacitance : 4.91 ; + } + pin (nq) { + function : "(!(i1) & !(i0))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("92.7, 92.7, 92.7, 98.5, 108.9", \ + "102.1, 102.1, 102.1, 108.0, 118.6", \ + "113.9, 113.9, 113.9, 119.9, 130.9", \ + "130.3, 130.3, 130.3, 136.4, 147.8", \ + "156.3, 156.3, 156.3, 162.5, 174.4"); + } + rise_transition (inslew_load_5x5__1) { + values ("38.8, 38.8, 38.8, 46.5, 61.4", \ + "45.7, 45.7, 45.7, 53.4, 68.4", \ + "58.0, 58.0, 58.0, 65.7, 80.7", \ + "80.9, 80.9, 80.9, 88.6, 103.8", \ + "124.5, 124.5, 124.5, 132.2, 147.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("84.1, 84.1, 84.1, 89.4, 99.2", \ + "91.9, 91.9, 91.9, 97.2, 107.2", \ + "100.4, 100.4, 100.4, 106.0, 115.9", \ + "110.1, 110.1, 110.1, 115.9, 126.1", \ + "122.1, 122.1, 122.1, 128.1, 139.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("32.0, 32.0, 32.0, 35.6, 42.3", \ + "35.6, 35.6, 35.6, 39.2, 46.0", \ + "42.1, 42.1, 42.1, 45.6, 52.6", \ + "54.0, 54.0, 54.0, 57.6, 64.6", \ + "77.0, 77.0, 77.0, 80.6, 87.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("106.7, 106.7, 106.7, 112.6, 123.2", \ + "106.2, 106.2, 106.2, 112.2, 122.9", \ + "102.7, 102.7, 102.7, 108.7, 119.7", \ + "90.6, 90.6, 90.6, 96.6, 108.0", \ + "60.8, 60.8, 60.8, 67.0, 78.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("45.3, 45.3, 45.3, 52.9, 67.9", \ + "50.6, 50.6, 50.6, 58.3, 73.3", \ + "60.6, 60.6, 60.6, 68.2, 83.3", \ + "79.8, 79.8, 79.8, 87.5, 102.7", \ + "116.6, 116.6, 116.6, 124.4, 139.7"); + } + cell_fall (inslew_load_5x5__1) { + values ("97.5, 97.5, 97.5, 102.8, 112.7", \ + "114.6, 114.6, 114.6, 120.0, 130.0", \ + "141.0, 141.0, 141.0, 146.8, 156.7", \ + "186.3, 186.3, 186.3, 192.2, 202.9", \ + "269.8, 269.8, 269.8, 275.8, 287.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("34.0, 34.0, 34.0, 37.6, 44.3", \ + "38.9, 38.9, 38.9, 42.4, 49.3", \ + "47.5, 47.5, 47.5, 51.0, 58.2", \ + "63.9, 63.9, 63.9, 67.5, 74.5", \ + "95.7, 95.7, 95.7, 99.3, 106.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("559.5, 559.5, 559.5, 619.1, 738.3", \ + "656.8, 656.8, 656.8, 716.4, 835.6", \ + "843.4, 843.4, 843.4, 903.0, 1022.2", \ + "1209.2, 1209.2, 1209.2, 1268.8, 1388.0", \ + "1931.6, 1931.6, 1931.6, 1991.2, 2110.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("569.5, 569.5, 569.5, 629.1, 748.3", \ + "642.9, 642.9, 642.9, 702.5, 821.7", \ + "782.8, 782.8, 782.8, 842.4, 961.6", \ + "1055.2, 1055.2, 1055.2, 1114.8, 1234.0", \ + "1593.5, 1593.5, 1593.5, 1653.1, 1772.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("676.0, 676.0, 676.0, 735.6, 854.8", \ + "759.8, 759.8, 759.8, 819.4, 938.6", \ + "924.3, 924.3, 924.3, 983.9, 1103.1", \ + "1251.4, 1251.4, 1251.4, 1310.9, 1430.1", \ + "1899.0, 1899.0, 1899.0, 1958.6, 2077.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("650.1, 650.1, 650.1, 709.7, 828.9", \ + "763.3, 763.3, 763.3, 822.9, 942.1", \ + "980.5, 980.5, 980.5, 1040.1, 1159.3", \ + "1407.9, 1407.9, 1407.9, 1467.5, 1586.7", \ + "2256.0, 2256.0, 2256.0, 2315.6, 2434.8"); + } + } + } + } + + cell (no3_x1) { + area : 0.0 ; + cell_leakage_power : 1.1 ; + leakage_power () { + when : "(i0 & (i1 | !(i2)))" ; + value : 2.6 ; + } + leakage_power () { + when : "((i0 & !(i1) & i2) | (!(i0) & i1))" ; + value : 0.98 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 0.87 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.00018 ; + } + pin (i2) { + direction : input ; + capacitance : 4.91 ; + } + pin (i1) { + direction : input ; + capacitance : 4.91 ; + } + pin (i0) { + direction : input ; + capacitance : 4.81 ; + } + pin (nq) { + function : "((!(i0) & !(i1)) & !(i2))" ; + direction : output ; + capacitance : 4.36 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("35.6, 35.6, 35.6, 59.3, 104.0", \ + "47.8, 47.8, 47.8, 72.2, 118.6", \ + "69.3, 69.3, 69.3, 94.2, 142.8", \ + "108.0, 108.0, 108.0, 134.6, 185.2", \ + "183.7, 183.7, 183.7, 211.0, 264.0"); + } + rise_transition (inslew_load_5x5__17) { + values ("69.8, 69.8, 69.8, 108.1, 185.8", \ + "111.3, 111.3, 111.3, 149.5, 225.8", \ + "190.7, 190.7, 190.7, 227.6, 304.5", \ + "344.2, 344.2, 344.2, 382.2, 457.2", \ + "649.3, 649.3, 649.3, 687.5, 763.5"); + } + cell_fall (inslew_load_5x5__17) { + values ("16.7, 16.7, 16.7, 29.7, 51.1", \ + "13.7, 13.7, 13.7, 29.4, 55.1", \ + "4.7, 4.7, 4.7, 23.1, 54.2", \ + "-15.8, -15.8, -15.8, 4.8, 41.4", \ + "-58.7, -58.7, -58.7, -36.3, 4.8"); + } + fall_transition (inslew_load_5x5__17) { + values ("22.2, 22.2, 22.2, 33.1, 53.5", \ + "35.2, 35.2, 35.2, 47.1, 68.6", \ + "59.7, 59.7, 59.7, 72.7, 96.2", \ + "107.5, 107.5, 107.5, 121.4, 147.1", \ + "202.3, 202.3, 202.3, 216.8, 244.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("63.7, 63.7, 63.7, 85.7, 129.3", \ + "70.5, 70.5, 70.5, 93.2, 137.3", \ + "81.8, 81.8, 81.8, 105.0, 150.6", \ + "102.7, 102.7, 102.7, 126.6, 173.3", \ + "143.0, 143.0, 143.0, 167.6, 215.8"); + } + rise_transition (inslew_load_5x5__17) { + values ("121.1, 121.1, 121.1, 159.2, 236.1", \ + "159.3, 159.3, 159.3, 197.0, 273.0", \ + "232.8, 232.8, 232.8, 269.8, 344.6", \ + "377.1, 377.1, 377.1, 415.9, 489.4", \ + "666.5, 666.5, 666.5, 703.4, 777.3"); + } + cell_fall (inslew_load_5x5__17) { + values ("26.7, 26.7, 26.7, 38.1, 58.3", \ + "29.2, 29.2, 29.2, 42.6, 66.2", \ + "30.2, 30.2, 30.2, 45.7, 73.5", \ + "28.9, 28.9, 28.9, 46.2, 78.1", \ + "24.1, 24.1, 24.1, 42.7, 77.9"); + } + fall_transition (inslew_load_5x5__17) { + values ("30.2, 30.2, 30.2, 40.6, 60.9", \ + "46.7, 46.7, 46.7, 57.7, 78.5", \ + "77.7, 77.7, 77.7, 89.5, 111.6", \ + "138.2, 138.2, 138.2, 150.6, 174.3", \ + "258.2, 258.2, 258.2, 271.0, 296.1"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("82.1, 82.1, 82.1, 103.7, 146.8", \ + "80.3, 80.3, 80.3, 102.3, 145.9", \ + "76.6, 76.6, 76.6, 98.7, 142.7", \ + "70.2, 70.2, 70.2, 92.5, 136.6", \ + "56.5, 56.5, 56.5, 79.1, 123.9"); + } + rise_transition (inslew_load_5x5__17) { + values ("162.5, 162.5, 162.5, 200.2, 276.0", \ + "195.6, 195.6, 195.6, 233.3, 308.9", \ + "258.6, 258.6, 258.6, 296.1, 371.6", \ + "385.3, 385.3, 385.3, 422.3, 496.7", \ + "640.7, 640.7, 640.7, 677.2, 750.4"); + } + cell_fall (inslew_load_5x5__17) { + values ("33.7, 33.7, 33.7, 44.3, 63.8", \ + "44.1, 44.1, 44.1, 56.2, 78.2", \ + "61.3, 61.3, 61.3, 74.7, 99.5", \ + "93.1, 93.1, 93.1, 107.4, 134.7", \ + "155.0, 155.0, 155.0, 170.0, 199.1"); + } + fall_transition (inslew_load_5x5__17) { + values ("36.3, 36.3, 36.3, 46.6, 66.8", \ + "58.8, 58.8, 58.8, 69.3, 89.7", \ + "101.6, 101.6, 101.6, 112.5, 133.6", \ + "185.9, 185.9, 185.9, 197.1, 219.0", \ + "353.6, 353.6, 353.6, 365.0, 387.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__17) { + values ("98.4, 98.4, 98.4, 152.9, 261.9", \ + "142.4, 142.4, 142.4, 196.9, 305.9", \ + "230.4, 230.4, 230.4, 285.0, 394.0", \ + "406.6, 406.6, 406.6, 461.1, 570.1", \ + "758.8, 758.8, 758.8, 813.3, 922.3"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("77.8, 77.8, 77.8, 132.3, 241.3", \ + "100.8, 100.8, 100.8, 155.4, 264.4", \ + "147.0, 147.0, 147.0, 201.5, 310.5", \ + "239.3, 239.3, 239.3, 293.9, 402.9", \ + "424.0, 424.0, 424.0, 478.5, 587.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__17) { + values ("168.1, 168.1, 168.1, 222.6, 331.6", \ + "213.2, 213.2, 213.2, 267.7, 376.7", \ + "303.5, 303.5, 303.5, 358.0, 467.0", \ + "484.0, 484.0, 484.0, 538.5, 647.5", \ + "845.0, 845.0, 845.0, 899.5, 1008.5"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("122.8, 122.8, 122.8, 177.3, 286.3", \ + "157.7, 157.7, 157.7, 212.2, 321.2", \ + "227.5, 227.5, 227.5, 282.0, 391.0", \ + "367.1, 367.1, 367.1, 421.6, 530.6", \ + "646.3, 646.3, 646.3, 700.8, 809.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__17) { + values ("225.6, 225.6, 225.6, 280.1, 389.2", \ + "268.5, 268.5, 268.5, 323.0, 432.0", \ + "354.1, 354.1, 354.1, 408.6, 517.6", \ + "525.3, 525.3, 525.3, 579.8, 688.8", \ + "867.8, 867.8, 867.8, 922.3, 1031.3"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("166.0, 166.0, 166.0, 220.5, 329.5", \ + "226.9, 226.9, 226.9, 281.4, 390.4", \ + "348.9, 348.9, 348.9, 403.4, 512.4", \ + "592.8, 592.8, 592.8, 647.3, 756.3", \ + "1080.7, 1080.7, 1080.7, 1135.2, 1244.2"); + } + } + } + } + + cell (no3_x4) { + area : 0.0 ; + cell_leakage_power : 3.6 ; + leakage_power () { + when : "(i0 & (i1 | !(i2)))" ; + value : 5.8 ; + } + leakage_power () { + when : "((i0 & !(i1) & i2) | (!(i0) & i1))" ; + value : 4.2 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 4.1 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.26 ; + } + pin (i2) { + direction : input ; + capacitance : 4.81 ; + } + pin (i1) { + direction : input ; + capacitance : 4.91 ; + } + pin (i0) { + direction : input ; + capacitance : 4.81 ; + } + pin (nq) { + function : "(!(i2) & !(i1) & !(i0))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("118.2, 118.2, 118.2, 124.1, 134.7", \ + "133.5, 133.5, 133.5, 139.5, 150.4", \ + "157.9, 157.9, 157.9, 163.8, 175.1", \ + "199.4, 199.4, 199.4, 205.6, 217.0", \ + "273.4, 273.4, 273.4, 279.7, 291.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("46.5, 46.5, 46.5, 54.2, 69.2", \ + "55.0, 55.0, 55.0, 62.7, 77.7", \ + "70.2, 70.2, 70.2, 77.9, 93.0", \ + "99.0, 99.0, 99.0, 106.8, 122.0", \ + "154.6, 154.6, 154.6, 162.3, 177.7"); + } + cell_fall (inslew_load_5x5__1) { + values ("87.0, 87.0, 87.0, 92.3, 102.1", \ + "90.8, 90.8, 90.8, 96.1, 106.1", \ + "90.6, 90.6, 90.6, 96.1, 106.1", \ + "81.4, 81.4, 81.4, 87.2, 97.3", \ + "54.0, 54.0, 54.0, 60.0, 70.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("32.4, 32.4, 32.4, 36.1, 42.8", \ + "35.5, 35.5, 35.5, 39.1, 45.8", \ + "40.7, 40.7, 40.7, 44.3, 51.2", \ + "50.4, 50.4, 50.4, 54.0, 61.1", \ + "68.7, 68.7, 68.7, 72.3, 79.3"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("147.6, 147.6, 147.6, 153.6, 164.5", \ + "156.3, 156.3, 156.3, 162.3, 173.5", \ + "169.3, 169.3, 169.3, 175.3, 186.7", \ + "191.5, 191.5, 191.5, 197.7, 209.3", \ + "229.8, 229.8, 229.8, 236.1, 248.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("57.0, 57.0, 57.0, 64.6, 79.7", \ + "64.3, 64.3, 64.3, 72.0, 87.1", \ + "78.2, 78.2, 78.2, 86.0, 101.1", \ + "105.2, 105.2, 105.2, 112.9, 128.2", \ + "157.5, 157.5, 157.5, 165.2, 180.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("98.0, 98.0, 98.0, 103.3, 113.2", \ + "107.0, 107.0, 107.0, 112.5, 122.4", \ + "116.9, 116.9, 116.9, 122.6, 132.5", \ + "127.6, 127.6, 127.6, 133.5, 143.8", \ + "140.2, 140.2, 140.2, 146.2, 157.4"); + } + fall_transition (inslew_load_5x5__1) { + values ("34.1, 34.1, 34.1, 37.7, 44.4", \ + "37.7, 37.7, 37.7, 41.3, 48.1", \ + "44.2, 44.2, 44.2, 47.7, 54.8", \ + "56.1, 56.1, 56.1, 59.7, 66.7", \ + "79.0, 79.0, 79.0, 82.6, 89.6"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("167.0, 167.0, 167.0, 172.9, 184.1", \ + "166.3, 166.3, 166.3, 172.3, 183.6", \ + "163.4, 163.4, 163.4, 169.4, 180.9", \ + "157.5, 157.5, 157.5, 163.7, 175.3", \ + "141.9, 141.9, 141.9, 148.1, 160.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("64.9, 64.9, 64.9, 72.6, 87.7", \ + "71.3, 71.3, 71.3, 79.0, 94.1", \ + "83.2, 83.2, 83.2, 90.9, 106.1", \ + "106.4, 106.4, 106.4, 114.1, 129.4", \ + "152.7, 152.7, 152.7, 160.4, 175.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("106.0, 106.0, 106.0, 111.3, 121.3", \ + "123.5, 123.5, 123.5, 129.0, 138.9", \ + "150.2, 150.2, 150.2, 156.0, 166.0", \ + "195.9, 195.9, 195.9, 201.8, 212.5", \ + "279.3, 279.3, 279.3, 285.3, 296.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("35.4, 35.4, 35.4, 39.0, 45.7", \ + "40.1, 40.1, 40.1, 43.7, 50.6", \ + "48.7, 48.7, 48.7, 52.3, 59.4", \ + "65.0, 65.0, 65.0, 68.6, 75.6", \ + "96.7, 96.7, 96.7, 100.3, 107.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("635.2, 635.2, 635.2, 694.8, 814.0", \ + "745.8, 745.8, 745.8, 805.4, 924.6", \ + "956.2, 956.2, 956.2, 1015.8, 1135.0", \ + "1370.8, 1370.8, 1370.8, 1430.4, 1549.6", \ + "2188.5, 2188.5, 2188.5, 2248.1, 2367.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("578.8, 578.8, 578.8, 638.4, 757.5", \ + "634.2, 634.2, 634.2, 693.8, 812.9", \ + "737.8, 737.8, 737.8, 797.4, 916.6", \ + "937.5, 937.5, 937.5, 997.1, 1116.3", \ + "1327.9, 1327.9, 1327.9, 1387.5, 1506.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("786.9, 786.9, 786.9, 846.5, 965.7", \ + "891.4, 891.4, 891.4, 951.0, 1070.2", \ + "1095.2, 1095.2, 1095.2, 1154.8, 1274.0", \ + "1499.8, 1499.8, 1499.8, 1559.4, 1678.6", \ + "2298.9, 2298.9, 2298.9, 2358.5, 2477.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("641.3, 641.3, 641.3, 700.9, 820.0", \ + "715.3, 715.3, 715.3, 774.9, 894.1", \ + "856.0, 856.0, 856.0, 915.6, 1034.8", \ + "1128.8, 1128.8, 1128.8, 1188.4, 1307.6", \ + "1666.9, 1666.9, 1666.9, 1726.5, 1845.7"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("908.7, 908.7, 908.7, 968.3, 1087.5", \ + "1003.2, 1003.2, 1003.2, 1062.8, 1182.0", \ + "1186.5, 1186.5, 1186.5, 1246.0, 1365.2", \ + "1550.9, 1550.9, 1550.9, 1610.5, 1729.7", \ + "2281.8, 2281.8, 2281.8, 2341.4, 2460.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("698.2, 698.2, 698.2, 757.8, 877.0", \ + "810.8, 810.8, 810.8, 870.4, 989.6", \ + "1028.0, 1028.0, 1028.0, 1087.6, 1206.8", \ + "1455.1, 1455.1, 1455.1, 1514.7, 1633.9", \ + "2302.4, 2302.4, 2302.4, 2362.0, 2481.2"); + } + } + } + } + + cell (no4_x1) { + area : 0.0 ; + cell_leakage_power : 1 ; + leakage_power () { + when : "(i0 & ((i1 & (i2 | !(i3))) | (!(i2) & !(i3))))" ; + value : 2.6 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & i3) | (!(i1) & i2))) | (!(i0) & i1 & (i2 | !(i3))))" ; + value : 0.98 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3) | (!(i0) & (i1 ^ i2) & i3))" ; + value : 0.87 ; + } + leakage_power () { + when : "(!(i3) & i2 & !(i1) & !(i0))" ; + value : 0.88 ; + } + leakage_power () { + when : "(i3 & !(i2) & !(i1) & !(i0))" ; + value : 0.84 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.00024 ; + } + pin (i3) { + direction : input ; + capacitance : 4.91 ; + } + pin (i2) { + direction : input ; + capacitance : 4.91 ; + } + pin (i1) { + direction : input ; + capacitance : 4.91 ; + } + pin (i0) { + direction : input ; + capacitance : 4.81 ; + } + pin (nq) { + function : "(((!(i0) & !(i1)) & !(i2)) & !(i3))" ; + direction : output ; + capacitance : 4.93 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("50.6, 50.6, 50.6, 85.4, 152.5", \ + "65.9, 65.9, 65.9, 101.8, 170.3", \ + "98.4, 98.4, 98.4, 135.1, 205.6", \ + "160.4, 160.4, 160.4, 197.8, 270.6", \ + "281.5, 281.5, 281.5, 319.4, 394.4"); + } + rise_transition (inslew_load_5x5__18) { + values ("93.8, 93.8, 93.8, 151.9, 269.8", \ + "141.4, 141.4, 141.4, 199.2, 316.1", \ + "237.0, 237.0, 237.0, 294.9, 409.8", \ + "424.7, 424.7, 424.7, 481.3, 596.9", \ + "796.8, 796.8, 796.8, 853.0, 966.4"); + } + cell_fall (inslew_load_5x5__18) { + values ("17.4, 17.4, 17.4, 31.8, 55.4", \ + "12.2, 12.2, 12.2, 30.1, 58.7", \ + "-2.2, -2.2, -2.2, 19.5, 54.9", \ + "-35.0, -35.0, -35.0, -9.5, 33.6", \ + "-103.5, -103.5, -103.5, -75.1, -24.5"); + } + fall_transition (inslew_load_5x5__18) { + values ("22.7, 22.7, 22.7, 35.0, 57.9", \ + "34.0, 34.0, 34.0, 47.6, 71.7", \ + "54.8, 54.8, 54.8, 69.9, 96.7", \ + "94.7, 94.7, 94.7, 111.4, 141.4", \ + "173.2, 173.2, 173.2, 191.2, 224.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("89.6, 89.6, 89.6, 123.0, 189.4", \ + "103.7, 103.7, 103.7, 137.6, 204.6", \ + "129.2, 129.2, 129.2, 164.0, 231.7", \ + "177.7, 177.7, 177.7, 212.9, 282.0", \ + "272.5, 272.5, 272.5, 308.3, 378.9"); + } + rise_transition (inslew_load_5x5__18) { + values ("160.9, 160.9, 160.9, 218.8, 335.7", \ + "209.8, 209.8, 209.8, 267.3, 383.4", \ + "302.9, 302.9, 302.9, 359.7, 474.4", \ + "486.6, 486.6, 486.6, 542.5, 655.2", \ + "852.7, 852.7, 852.7, 908.0, 1019.3"); + } + cell_fall (inslew_load_5x5__18) { + values ("26.6, 26.6, 26.6, 39.5, 61.9", \ + "25.7, 25.7, 25.7, 41.3, 67.9", \ + "18.7, 18.7, 18.7, 37.4, 69.7", \ + "-0.2, -0.2, -0.2, 21.4, 60.0", \ + "-42.0, -42.0, -42.0, -17.9, 26.4"); + } + fall_transition (inslew_load_5x5__18) { + values ("30.2, 30.2, 30.2, 41.9, 64.8", \ + "43.9, 43.9, 43.9, 56.5, 80.1", \ + "69.1, 69.1, 69.1, 83.0, 108.5", \ + "117.6, 117.6, 117.6, 132.6, 160.7", \ + "212.8, 212.8, 212.8, 228.8, 259.3"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("123.3, 123.3, 123.3, 156.3, 222.3", \ + "133.5, 133.5, 133.5, 166.9, 233.2", \ + "149.7, 149.7, 149.7, 183.4, 250.2", \ + "181.6, 181.6, 181.6, 215.3, 282.5", \ + "244.3, 244.3, 244.3, 279.4, 347.0"); + } + rise_transition (inslew_load_5x5__18) { + values ("222.3, 222.3, 222.3, 279.9, 395.6", \ + "271.4, 271.4, 271.4, 328.7, 443.7", \ + "361.2, 361.2, 361.2, 418.4, 533.1", \ + "538.2, 538.2, 538.2, 594.8, 708.4", \ + "892.7, 892.7, 892.7, 948.6, 1061.0"); + } + cell_fall (inslew_load_5x5__18) { + values ("31.9, 31.9, 31.9, 44.1, 66.1", \ + "35.4, 35.4, 35.4, 49.7, 75.2", \ + "37.2, 37.2, 37.2, 54.0, 84.1", \ + "36.7, 36.7, 36.7, 55.6, 90.5", \ + "32.4, 32.4, 32.4, 53.0, 91.9"); + } + fall_transition (inslew_load_5x5__18) { + values ("34.7, 34.7, 34.7, 46.4, 69.2", \ + "51.5, 51.5, 51.5, 63.7, 86.9", \ + "82.8, 82.8, 82.8, 95.8, 120.4", \ + "143.5, 143.5, 143.5, 157.4, 183.8", \ + "263.6, 263.6, 263.6, 278.1, 306.1"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("148.3, 148.3, 148.3, 181.1, 246.7", \ + "150.5, 150.5, 150.5, 183.5, 249.4", \ + "152.6, 152.6, 152.6, 186.0, 252.5", \ + "157.8, 157.8, 157.8, 191.3, 257.9", \ + "170.6, 170.6, 170.6, 203.9, 270.4"); + } + rise_transition (inslew_load_5x5__18) { + values ("272.9, 272.9, 272.9, 330.0, 444.6", \ + "316.8, 316.8, 316.8, 373.5, 487.3", \ + "399.6, 399.6, 399.6, 456.6, 570.4", \ + "560.8, 560.8, 560.8, 618.0, 732.3", \ + "883.1, 883.1, 883.1, 939.8, 1053.7"); + } + cell_fall (inslew_load_5x5__18) { + values ("37.4, 37.4, 37.4, 49.1, 70.6", \ + "48.4, 48.4, 48.4, 61.6, 85.7", \ + "66.0, 66.0, 66.0, 80.7, 108.1", \ + "98.1, 98.1, 98.1, 114.0, 144.3", \ + "160.2, 160.2, 160.2, 177.0, 209.5"); + } + fall_transition (inslew_load_5x5__18) { + values ("39.7, 39.7, 39.7, 51.3, 74.1", \ + "62.3, 62.3, 62.3, 74.1, 97.0", \ + "105.2, 105.2, 105.2, 117.5, 141.1", \ + "189.6, 189.6, 189.6, 202.2, 226.8", \ + "357.3, 357.3, 357.3, 370.2, 395.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__18) { + values ("104.6, 104.6, 104.6, 166.2, 289.5", \ + "147.1, 147.1, 147.1, 208.7, 332.0", \ + "232.1, 232.1, 232.1, 293.7, 417.0", \ + "402.0, 402.0, 402.0, 463.7, 586.9", \ + "742.0, 742.0, 742.0, 803.6, 926.9"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("77.4, 77.4, 77.4, 139.1, 262.3", \ + "93.7, 93.7, 93.7, 155.3, 278.6", \ + "126.2, 126.2, 126.2, 187.8, 311.1", \ + "191.2, 191.2, 191.2, 252.8, 376.1", \ + "321.1, 321.1, 321.1, 382.8, 506.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__18) { + values ("173.3, 173.3, 173.3, 235.0, 358.2", \ + "217.3, 217.3, 217.3, 279.0, 402.3", \ + "305.4, 305.4, 305.4, 367.1, 490.3", \ + "481.5, 481.5, 481.5, 543.2, 666.5", \ + "833.8, 833.8, 833.8, 895.4, 1018.7"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("117.5, 117.5, 117.5, 179.1, 302.4", \ + "140.6, 140.6, 140.6, 202.2, 325.5", \ + "186.7, 186.7, 186.7, 248.4, 371.7", \ + "279.1, 279.1, 279.1, 340.7, 464.0", \ + "463.7, 463.7, 463.7, 525.4, 648.7"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__18) { + values ("237.7, 237.7, 237.7, 299.3, 422.6", \ + "282.8, 282.8, 282.8, 344.5, 467.7", \ + "373.1, 373.1, 373.1, 434.7, 558.0", \ + "553.6, 553.6, 553.6, 615.2, 738.5", \ + "914.6, 914.6, 914.6, 976.2, 1099.5"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("146.4, 146.4, 146.4, 208.0, 331.3", \ + "181.3, 181.3, 181.3, 242.9, 366.2", \ + "251.1, 251.1, 251.1, 312.7, 436.0", \ + "390.6, 390.6, 390.6, 452.3, 575.6", \ + "669.8, 669.8, 669.8, 731.5, 854.7"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__18) { + values ("289.1, 289.1, 289.1, 350.7, 474.0", \ + "331.9, 331.9, 331.9, 393.5, 516.8", \ + "417.5, 417.5, 417.5, 479.2, 602.4", \ + "588.8, 588.8, 588.8, 650.4, 773.7", \ + "931.3, 931.3, 931.3, 992.9, 1116.2"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("184.2, 184.2, 184.2, 245.8, 369.1", \ + "245.2, 245.2, 245.2, 306.8, 430.1", \ + "367.1, 367.1, 367.1, 428.8, 552.0", \ + "611.1, 611.1, 611.1, 672.7, 796.0", \ + "1098.9, 1098.9, 1098.9, 1160.6, 1283.8"); + } + } + } + } + + cell (no4_x4) { + area : 0.0 ; + cell_leakage_power : 3.7 ; + leakage_power () { + when : "(i0 & ((i1 & (i2 | !(i3))) | (!(i2) & !(i3))))" ; + value : 5.8 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & i3) | (!(i1) & i2))) | (!(i0) & i1 & (i2 | !(i3))))" ; + value : 4.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3) | (!(i0) & ((i1 & !(i2) & i3) | (!(i1) & i2))))" ; + value : 4.1 ; + } + leakage_power () { + when : "(i3 & !(i2) & !(i1) & !(i0))" ; + value : 4 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.26 ; + } + pin (i3) { + direction : input ; + capacitance : 4.81 ; + } + pin (i2) { + direction : input ; + capacitance : 4.91 ; + } + pin (i1) { + direction : input ; + capacitance : 4.91 ; + } + pin (i0) { + direction : input ; + capacitance : 4.91 ; + } + pin (nq) { + function : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("141.8, 141.8, 141.8, 147.8, 158.6", \ + "159.9, 159.9, 159.9, 165.9, 177.0", \ + "194.5, 194.5, 194.5, 200.6, 212.0", \ + "257.1, 257.1, 257.1, 263.3, 275.0", \ + "373.8, 373.8, 373.8, 380.1, 392.4"); + } + rise_transition (inslew_load_5x5__1) { + values ("53.8, 53.8, 53.8, 61.5, 76.5", \ + "63.1, 63.1, 63.1, 70.8, 85.8", \ + "81.3, 81.3, 81.3, 89.0, 104.2", \ + "115.4, 115.4, 115.4, 123.1, 138.4", \ + "182.4, 182.4, 182.4, 190.0, 205.4"); + } + cell_fall (inslew_load_5x5__1) { + values ("87.6, 87.6, 87.6, 92.9, 102.7", \ + "89.2, 89.2, 89.2, 94.6, 104.5", \ + "83.5, 83.5, 83.5, 89.0, 98.9", \ + "61.8, 61.8, 61.8, 67.5, 77.5", \ + "7.8, 7.8, 7.8, 13.8, 24.4"); + } + fall_transition (inslew_load_5x5__1) { + values ("32.5, 32.5, 32.5, 36.2, 42.9", \ + "35.2, 35.2, 35.2, 38.8, 45.6", \ + "39.8, 39.8, 39.8, 43.4, 50.3", \ + "48.0, 48.0, 48.0, 51.6, 58.7", \ + "63.3, 63.3, 63.3, 66.9, 73.9"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("182.0, 182.0, 182.0, 187.9, 199.2", \ + "197.3, 197.3, 197.3, 203.3, 214.7", \ + "224.0, 224.0, 224.0, 230.2, 241.6", \ + "271.9, 271.9, 271.9, 278.2, 290.1", \ + "362.0, 362.0, 362.0, 368.4, 380.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("66.9, 66.9, 66.9, 74.6, 89.7", \ + "76.1, 76.1, 76.1, 83.8, 98.9", \ + "93.2, 93.2, 93.2, 100.9, 116.2", \ + "126.5, 126.5, 126.5, 134.2, 149.5", \ + "192.3, 192.3, 192.3, 199.9, 215.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("97.8, 97.8, 97.8, 103.1, 113.0", \ + "103.2, 103.2, 103.2, 108.6, 118.5", \ + "104.7, 104.7, 104.7, 110.3, 120.2", \ + "96.9, 96.9, 96.9, 102.8, 112.9", \ + "70.8, 70.8, 70.8, 76.8, 87.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("34.0, 34.0, 34.0, 37.7, 44.4", \ + "37.2, 37.2, 37.2, 40.7, 47.5", \ + "42.5, 42.5, 42.5, 46.1, 53.1", \ + "52.2, 52.2, 52.2, 55.8, 62.9", \ + "70.6, 70.6, 70.6, 74.2, 81.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("216.2, 216.2, 216.2, 222.2, 233.6", \ + "227.0, 227.0, 227.0, 233.1, 244.5", \ + "243.5, 243.5, 243.5, 249.7, 261.3", \ + "274.1, 274.1, 274.1, 280.4, 292.4", \ + "332.8, 332.8, 332.8, 339.1, 351.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("78.5, 78.5, 78.5, 86.2, 101.4", \ + "87.5, 87.5, 87.5, 95.2, 110.5", \ + "103.9, 103.9, 103.9, 111.7, 126.9", \ + "135.9, 135.9, 135.9, 143.6, 159.0", \ + "199.5, 199.5, 199.5, 207.2, 222.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("103.8, 103.8, 103.8, 109.1, 119.1", \ + "113.7, 113.7, 113.7, 119.1, 129.1", \ + "124.1, 124.1, 124.1, 129.8, 139.8", \ + "135.6, 135.6, 135.6, 141.5, 151.8", \ + "148.6, 148.6, 148.6, 154.7, 165.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("35.0, 35.0, 35.0, 38.6, 45.3", \ + "38.6, 38.6, 38.6, 42.2, 49.1", \ + "45.1, 45.1, 45.1, 48.6, 55.7", \ + "57.0, 57.0, 57.0, 60.6, 67.6", \ + "79.9, 79.9, 79.9, 83.5, 90.6"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("241.3, 241.3, 241.3, 247.5, 258.9", \ + "243.8, 243.8, 243.8, 250.0, 261.4", \ + "246.1, 246.1, 246.1, 252.3, 263.9", \ + "249.8, 249.8, 249.8, 256.0, 268.1", \ + "257.5, 257.5, 257.5, 263.9, 276.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("87.7, 87.7, 87.7, 95.5, 110.7", \ + "95.8, 95.8, 95.8, 103.5, 118.8", \ + "110.9, 110.9, 110.9, 118.6, 133.9", \ + "140.2, 140.2, 140.2, 147.9, 163.3", \ + "197.9, 197.9, 197.9, 205.6, 220.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("110.3, 110.3, 110.3, 115.6, 125.6", \ + "128.0, 128.0, 128.0, 133.5, 143.5", \ + "155.1, 155.1, 155.1, 160.9, 170.9", \ + "200.9, 200.9, 200.9, 206.9, 217.6", \ + "284.5, 284.5, 284.5, 290.5, 302.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("36.1, 36.1, 36.1, 39.7, 46.4", \ + "40.8, 40.8, 40.8, 44.3, 51.3", \ + "49.3, 49.3, 49.3, 52.9, 60.0", \ + "65.6, 65.6, 65.6, 69.2, 76.2", \ + "97.3, 97.3, 97.3, 100.9, 108.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("698.7, 698.7, 698.7, 758.3, 877.5", \ + "815.4, 815.4, 815.4, 875.0, 994.2", \ + "1049.4, 1049.4, 1049.4, 1109.0, 1228.2", \ + "1503.9, 1503.9, 1503.9, 1563.5, 1682.7", \ + "2407.1, 2407.1, 2407.1, 2466.7, 2585.9"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("579.2, 579.2, 579.2, 638.8, 758.0", \ + "624.0, 624.0, 624.0, 683.6, 802.8", \ + "706.6, 706.6, 706.6, 766.2, 885.4", \ + "862.7, 862.7, 862.7, 922.3, 1041.5", \ + "1164.5, 1164.5, 1164.5, 1224.1, 1343.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("872.5, 872.5, 872.5, 932.1, 1051.3", \ + "991.8, 991.8, 991.8, 1051.4, 1170.6", \ + "1221.8, 1221.8, 1221.8, 1281.4, 1400.6", \ + "1676.4, 1676.4, 1676.4, 1736.0, 1855.2", \ + "2582.5, 2582.5, 2582.5, 2642.0, 2761.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("635.4, 635.4, 635.4, 695.0, 814.2", \ + "691.8, 691.8, 691.8, 751.4, 870.6", \ + "796.9, 796.9, 796.9, 856.5, 975.7", \ + "997.4, 997.4, 997.4, 1057.0, 1176.2", \ + "1389.1, 1389.1, 1389.1, 1448.7, 1567.9"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1031.9, 1031.9, 1031.9, 1091.5, 1210.7", \ + "1151.8, 1151.8, 1151.8, 1211.3, 1330.5", \ + "1378.9, 1378.9, 1378.9, 1438.5, 1557.7", \ + "1827.8, 1827.8, 1827.8, 1887.4, 2006.6", \ + "2724.4, 2724.4, 2724.4, 2784.0, 2903.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("674.5, 674.5, 674.5, 734.1, 853.3", \ + "748.7, 748.7, 748.7, 808.3, 927.5", \ + "889.7, 889.7, 889.7, 949.2, 1068.4", \ + "1162.9, 1162.9, 1162.9, 1222.5, 1341.7", \ + "1701.2, 1701.2, 1701.2, 1760.8, 1880.0"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1160.2, 1160.2, 1160.2, 1219.8, 1339.0", \ + "1269.7, 1269.7, 1269.7, 1329.3, 1448.5", \ + "1481.7, 1481.7, 1481.7, 1541.3, 1660.5", \ + "1898.5, 1898.5, 1898.5, 1958.1, 2077.3", \ + "2727.6, 2727.6, 2727.6, 2787.2, 2906.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("723.6, 723.6, 723.6, 783.2, 902.4", \ + "836.1, 836.1, 836.1, 895.7, 1014.9", \ + "1053.4, 1053.4, 1053.4, 1113.0, 1232.2", \ + "1480.4, 1480.4, 1480.4, 1540.0, 1659.2", \ + "2327.6, 2327.6, 2327.6, 2387.2, 2506.3"); + } + } + } + } + + cell (noa22_x1) { + area : 0.0 ; + cell_leakage_power : 2.3 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 5.1 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 5.2 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 0.00017 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 3.5 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0))" ; + value : 0.00015 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 2 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 8.6e-05 ; + } + pin (i2) { + direction : input ; + capacitance : 5.78 ; + } + pin (i1) { + direction : input ; + capacitance : 5.78 ; + } + pin (i0) { + direction : input ; + capacitance : 5.67 ; + } + pin (nq) { + function : "((!(i1) & !(i2)) | (!(i0) & !(i2)))" ; + direction : output ; + capacitance : 4.61 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("42.2, 42.2, 42.2, 58.6, 90.0", \ + "61.7, 61.7, 61.7, 78.8, 111.4", \ + "96.3, 96.3, 96.3, 113.9, 148.1", \ + "162.0, 162.0, 162.0, 180.3, 215.8", \ + "291.8, 291.8, 291.8, 310.5, 347.1"); + } + rise_transition (inslew_load_5x5__19) { + values ("77.8, 77.8, 77.8, 105.1, 159.8", \ + "129.2, 129.2, 129.2, 156.2, 210.6", \ + "225.7, 225.7, 225.7, 252.5, 306.3", \ + "414.3, 414.3, 414.3, 441.4, 495.1", \ + "789.3, 789.3, 789.3, 816.4, 870.6"); + } + cell_fall (inslew_load_5x5__19) { + values ("14.9, 14.9, 14.9, 23.9, 40.2", \ + "7.6, 7.6, 7.6, 18.2, 37.0", \ + "-9.8, -9.8, -9.8, 2.5, 24.6", \ + "-47.9, -47.9, -47.9, -33.8, -8.0", \ + "-126.3, -126.3, -126.3, -110.8, -81.9"); + } + fall_transition (inslew_load_5x5__19) { + values ("28.7, 28.7, 28.7, 38.6, 58.2", \ + "39.2, 39.2, 39.2, 49.5, 69.3", \ + "59.3, 59.3, 59.3, 70.1, 90.8", \ + "98.3, 98.3, 98.3, 109.6, 131.5", \ + "175.4, 175.4, 175.4, 187.2, 210.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("30.2, 30.2, 30.2, 47.4, 79.4", \ + "43.7, 43.7, 43.7, 61.4, 95.1", \ + "66.2, 66.2, 66.2, 85.1, 120.6", \ + "108.8, 108.8, 108.8, 128.4, 165.9", \ + "192.6, 192.6, 192.6, 212.6, 251.5"); + } + rise_transition (inslew_load_5x5__19) { + values ("59.3, 59.3, 59.3, 86.6, 140.9", \ + "102.2, 102.2, 102.2, 128.8, 183.4", \ + "181.9, 181.9, 181.9, 209.1, 262.8", \ + "338.2, 338.2, 338.2, 365.6, 420.0", \ + "649.0, 649.0, 649.0, 676.5, 731.3"); + } + cell_fall (inslew_load_5x5__19) { + values ("12.3, 12.3, 12.3, 23.1, 41.2", \ + "7.7, 7.7, 7.7, 20.6, 42.2", \ + "-3.7, -3.7, -3.7, 11.0, 36.7", \ + "-28.5, -28.5, -28.5, -12.1, 17.3", \ + "-79.1, -79.1, -79.1, -61.7, -29.1"); + } + fall_transition (inslew_load_5x5__19) { + values ("22.9, 22.9, 22.9, 33.4, 53.3", \ + "35.3, 35.3, 35.3, 46.4, 67.2", \ + "58.9, 58.9, 58.9, 70.6, 92.7", \ + "105.2, 105.2, 105.2, 117.5, 140.9", \ + "197.3, 197.3, 197.3, 209.9, 234.4"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("54.1, 54.1, 54.1, 69.4, 99.7", \ + "64.8, 64.8, 64.8, 80.6, 111.2", \ + "84.6, 84.6, 84.6, 100.5, 131.7", \ + "123.2, 123.2, 123.2, 139.3, 171.2", \ + "199.9, 199.9, 199.9, 216.2, 248.6"); + } + rise_transition (inslew_load_5x5__19) { + values ("108.9, 108.9, 108.9, 135.6, 189.4", \ + "155.6, 155.6, 155.6, 182.0, 235.3", \ + "245.8, 245.8, 245.8, 271.8, 324.3", \ + "425.2, 425.2, 425.2, 451.0, 502.7", \ + "783.8, 783.8, 783.8, 809.4, 860.8"); + } + cell_fall (inslew_load_5x5__19) { + values ("17.2, 17.2, 17.2, 24.4, 37.3", \ + "15.8, 15.8, 15.8, 24.4, 39.6", \ + "10.3, 10.3, 10.3, 20.1, 38.1", \ + "-2.7, -2.7, -2.7, 8.0, 28.3", \ + "-30.2, -30.2, -30.2, -18.7, 3.2"); + } + fall_transition (inslew_load_5x5__19) { + values ("25.4, 25.4, 25.4, 31.6, 43.3", \ + "40.0, 40.0, 40.0, 46.6, 59.1", \ + "67.9, 67.9, 67.9, 75.0, 88.5", \ + "122.7, 122.7, 122.7, 130.2, 144.7", \ + "231.7, 231.7, 231.7, 239.4, 254.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__19) { + values ("165.1, 165.1, 165.1, 222.8, 338.1", \ + "246.7, 246.7, 246.7, 304.4, 419.7", \ + "409.8, 409.8, 409.8, 467.5, 582.8", \ + "736.0, 736.0, 736.0, 793.7, 909.0", \ + "1388.5, 1388.5, 1388.5, 1446.2, 1561.5"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("129.2, 129.2, 129.2, 186.8, 302.1", \ + "157.9, 157.9, 157.9, 215.6, 330.9", \ + "215.5, 215.5, 215.5, 273.1, 388.4", \ + "330.6, 330.6, 330.6, 388.2, 503.5", \ + "560.7, 560.7, 560.7, 618.4, 733.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__19) { + values ("120.7, 120.7, 120.7, 178.3, 293.6", \ + "185.4, 185.4, 185.4, 243.1, 358.4", \ + "314.9, 314.9, 314.9, 372.6, 487.9", \ + "574.0, 574.0, 574.0, 631.6, 746.9", \ + "1092.1, 1092.1, 1092.1, 1149.7, 1265.0"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("91.7, 91.7, 91.7, 149.4, 264.7", \ + "124.0, 124.0, 124.0, 181.7, 297.0", \ + "188.6, 188.6, 188.6, 246.3, 361.6", \ + "317.8, 317.8, 317.8, 375.4, 490.8", \ + "576.2, 576.2, 576.2, 633.8, 749.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__19) { + values ("227.5, 227.5, 227.5, 285.2, 400.5", \ + "314.2, 314.2, 314.2, 371.9, 487.2", \ + "487.6, 487.6, 487.6, 545.3, 660.6", \ + "834.4, 834.4, 834.4, 892.1, 1007.4", \ + "1528.1, 1528.1, 1528.1, 1585.7, 1701.1"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("165.3, 165.3, 165.3, 223.0, 338.3", \ + "221.3, 221.3, 221.3, 279.0, 394.3", \ + "333.4, 333.4, 333.4, 391.1, 506.4", \ + "557.5, 557.5, 557.5, 615.2, 730.5", \ + "1005.8, 1005.8, 1005.8, 1063.5, 1178.8"); + } + } + } + } + + cell (noa22_x4) { + area : 0.0 ; + cell_leakage_power : 2.7 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 3.7 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 3.6 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 3.5 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !(i2))" ; + value : 0.26 ; + } + pin (i2) { + direction : input ; + capacitance : 3.42 ; + } + pin (i1) { + direction : input ; + capacitance : 3.66 ; + } + pin (i0) { + direction : input ; + capacitance : 3.63 ; + } + pin (nq) { + function : "((!(i0) & !(i2)) | (!(i2) & !(i1)))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("133.0, 133.0, 133.0, 138.9, 149.7", \ + "155.6, 155.6, 155.6, 161.5, 172.6", \ + "192.5, 192.5, 192.5, 198.5, 209.9", \ + "258.8, 258.8, 258.8, 265.0, 276.7", \ + "382.6, 382.6, 382.6, 388.9, 401.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("50.8, 50.8, 50.8, 58.5, 73.5", \ + "60.5, 60.5, 60.5, 68.1, 83.2", \ + "78.1, 78.1, 78.1, 85.8, 101.0", \ + "111.5, 111.5, 111.5, 119.2, 134.5", \ + "176.7, 176.7, 176.7, 184.4, 199.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("93.2, 93.2, 93.2, 98.5, 108.5", \ + "92.1, 92.1, 92.1, 97.5, 107.4", \ + "83.1, 83.1, 83.1, 88.7, 98.7", \ + "56.8, 56.8, 56.8, 62.6, 72.6", \ + "-5.7, -5.7, -5.7, 0.2, 10.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("35.3, 35.3, 35.3, 38.9, 45.6", \ + "37.6, 37.6, 37.6, 41.1, 47.9", \ + "41.7, 41.7, 41.7, 45.3, 52.2", \ + "49.3, 49.3, 49.3, 52.9, 60.0", \ + "63.7, 63.7, 63.7, 67.3, 74.3"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("121.2, 121.2, 121.2, 127.1, 137.8", \ + "138.2, 138.2, 138.2, 144.3, 155.1", \ + "165.4, 165.4, 165.4, 171.3, 182.7", \ + "210.8, 210.8, 210.8, 216.9, 228.4", \ + "293.5, 293.5, 293.5, 299.8, 312.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("47.0, 47.0, 47.0, 54.6, 69.7", \ + "55.2, 55.2, 55.2, 62.9, 77.9", \ + "70.3, 70.3, 70.3, 78.0, 93.1", \ + "98.4, 98.4, 98.4, 106.2, 121.5", \ + "153.1, 153.1, 153.1, 160.7, 176.2"); + } + cell_fall (inslew_load_5x5__1) { + values ("93.3, 93.3, 93.3, 98.6, 108.5", \ + "96.4, 96.4, 96.4, 101.8, 111.7", \ + "94.4, 94.4, 94.4, 100.0, 109.9", \ + "80.9, 80.9, 80.9, 86.7, 96.8", \ + "44.5, 44.5, 44.5, 50.4, 61.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("34.4, 34.4, 34.4, 38.0, 44.7", \ + "37.3, 37.3, 37.3, 40.9, 47.7", \ + "42.4, 42.4, 42.4, 46.0, 53.0", \ + "51.7, 51.7, 51.7, 55.3, 62.3", \ + "69.3, 69.3, 69.3, 72.9, 80.0"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("144.8, 144.8, 144.8, 150.8, 161.7", \ + "157.8, 157.8, 157.8, 163.8, 175.0", \ + "179.5, 179.5, 179.5, 185.6, 197.0", \ + "219.3, 219.3, 219.3, 225.5, 237.2", \ + "293.1, 293.1, 293.1, 299.4, 311.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("56.9, 56.9, 56.9, 64.5, 79.6", \ + "65.5, 65.5, 65.5, 73.2, 88.3", \ + "81.8, 81.8, 81.8, 89.6, 104.8", \ + "113.5, 113.5, 113.5, 121.3, 136.6", \ + "176.1, 176.1, 176.1, 183.7, 199.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("88.8, 88.8, 88.8, 94.1, 104.0", \ + "94.3, 94.3, 94.3, 99.7, 109.6", \ + "97.6, 97.6, 97.6, 103.2, 113.1", \ + "95.7, 95.7, 95.7, 101.5, 111.7", \ + "83.3, 83.3, 83.3, 89.3, 100.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("33.2, 33.2, 33.2, 36.8, 43.5", \ + "36.3, 36.3, 36.3, 39.9, 46.7", \ + "42.0, 42.0, 42.0, 45.6, 52.6", \ + "52.5, 52.5, 52.5, 56.1, 63.2", \ + "72.6, 72.6, 72.6, 76.2, 83.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("658.4, 658.4, 658.4, 718.0, 837.2", \ + "774.3, 774.3, 774.3, 833.9, 953.1", \ + "996.7, 996.7, 996.7, 1056.3, 1175.5", \ + "1431.6, 1431.6, 1431.6, 1491.2, 1610.4", \ + "2293.6, 2293.6, 2293.6, 2353.2, 2472.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("603.1, 603.1, 603.1, 662.7, 781.9", \ + "641.7, 641.7, 641.7, 701.3, 820.5", \ + "715.1, 715.1, 715.1, 774.7, 893.9", \ + "855.6, 855.6, 855.6, 915.2, 1034.4", \ + "1129.7, 1129.7, 1129.7, 1189.3, 1308.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("606.0, 606.0, 606.0, 665.5, 784.7", \ + "702.0, 702.0, 702.0, 761.6, 880.8", \ + "886.3, 886.3, 886.3, 945.9, 1065.1", \ + "1244.6, 1244.6, 1244.6, 1304.2, 1423.4", \ + "1953.1, 1953.1, 1953.1, 2012.7, 2131.9"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("573.9, 573.9, 573.9, 633.5, 752.7", \ + "621.0, 621.0, 621.0, 680.6, 799.8", \ + "708.5, 708.5, 708.5, 768.1, 887.3", \ + "874.9, 874.9, 874.9, 934.5, 1053.7", \ + "1199.8, 1199.8, 1199.8, 1259.4, 1378.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("738.5, 738.5, 738.5, 798.1, 917.3", \ + "850.2, 850.2, 850.2, 909.8, 1029.0", \ + "1068.4, 1068.4, 1068.4, 1128.0, 1247.2", \ + "1500.9, 1500.9, 1500.9, 1560.5, 1679.7", \ + "2363.2, 2363.2, 2363.2, 2422.8, 2542.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("598.5, 598.5, 598.5, 658.1, 777.3", \ + "659.3, 659.3, 659.3, 718.9, 838.1", \ + "775.9, 775.9, 775.9, 835.5, 954.7", \ + "1001.7, 1001.7, 1001.7, 1061.3, 1180.5", \ + "1445.0, 1445.0, 1445.0, 1504.6, 1623.8"); + } + } + } + } + + cell (noa2a22_x1) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 10 ; + } + leakage_power () { + when : "(!(i3) & i2 & !(i1) & i0)" ; + value : 0.00017 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3)" ; + value : 7.1 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3) | (!(i0) & i1 & i2 & !(i3)))" ; + value : 0.00015 ; + } + leakage_power () { + when : "(i3 & !(i2) & i1 & !(i0))" ; + value : 0.00014 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 3.9 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & !(i1) & i2 & !(i3)))" ; + value : 8.6e-05 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & !(i2) & i3)))" ; + value : 6.9e-05 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 2.9e-06 ; + } + pin (i3) { + direction : input ; + capacitance : 5.78 ; + } + pin (i2) { + direction : input ; + capacitance : 5.62 ; + } + pin (i1) { + direction : input ; + capacitance : 5.67 ; + } + pin (i0) { + direction : input ; + capacitance : 5.70 ; + } + pin (nq) { + function : "((((!(i0) & !(i2)) | (!(i0) & !(i3))) | (!(i1) & !(i2))) | (!(i1) & !(i3)))" ; + direction : output ; + capacitance : 4.79 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("41.8, 41.8, 41.8, 58.7, 91.3", \ + "61.1, 61.1, 61.1, 78.7, 112.5", \ + "96.0, 96.0, 96.0, 114.1, 149.5", \ + "161.8, 161.8, 161.8, 180.7, 217.4", \ + "291.6, 291.6, 291.6, 310.9, 348.9"); + } + rise_transition (inslew_load_5x5__12) { + values ("78.7, 78.7, 78.7, 106.7, 163.8", \ + "129.5, 129.5, 129.5, 157.3, 214.0", \ + "226.3, 226.3, 226.3, 254.0, 309.9", \ + "414.9, 414.9, 414.9, 442.9, 498.6", \ + "789.8, 789.8, 789.8, 818.0, 874.2"); + } + cell_fall (inslew_load_5x5__12) { + values ("15.3, 15.3, 15.3, 24.6, 41.4", \ + "8.1, 8.1, 8.1, 19.0, 38.3", \ + "-9.3, -9.3, -9.3, 3.4, 26.2", \ + "-47.3, -47.3, -47.3, -32.7, -6.1", \ + "-125.7, -125.7, -125.7, -109.7, -79.7"); + } + fall_transition (inslew_load_5x5__12) { + values ("29.1, 29.1, 29.1, 39.4, 59.7", \ + "39.6, 39.6, 39.6, 50.3, 70.8", \ + "59.7, 59.7, 59.7, 70.9, 92.3", \ + "98.7, 98.7, 98.7, 110.5, 133.1", \ + "175.9, 175.9, 175.9, 188.1, 211.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("30.1, 30.1, 30.1, 47.5, 80.6", \ + "43.5, 43.5, 43.5, 61.5, 96.2", \ + "66.1, 66.1, 66.1, 85.5, 122.1", \ + "108.7, 108.7, 108.7, 128.9, 167.8", \ + "192.6, 192.6, 192.6, 213.2, 253.6"); + } + rise_transition (inslew_load_5x5__12) { + values ("60.2, 60.2, 60.2, 88.0, 144.6", \ + "103.0, 103.0, 103.0, 130.1, 186.6", \ + "182.6, 182.6, 182.6, 210.8, 266.4", \ + "338.9, 338.9, 338.9, 367.3, 423.7", \ + "649.6, 649.6, 649.6, 678.2, 735.1"); + } + cell_fall (inslew_load_5x5__12) { + values ("12.7, 12.7, 12.7, 23.9, 42.5", \ + "8.2, 8.2, 8.2, 21.5, 43.7", \ + "-3.1, -3.1, -3.1, 12.1, 38.5", \ + "-27.8, -27.8, -27.8, -10.9, 19.5", \ + "-78.4, -78.4, -78.4, -60.4, -26.7"); + } + fall_transition (inslew_load_5x5__12) { + values ("23.4, 23.4, 23.4, 34.2, 54.8", \ + "35.8, 35.8, 35.8, 47.3, 68.8", \ + "59.4, 59.4, 59.4, 71.5, 94.4", \ + "105.7, 105.7, 105.7, 118.4, 142.6", \ + "197.8, 197.8, 197.8, 210.8, 236.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("66.6, 66.6, 66.6, 82.3, 113.5", \ + "77.7, 77.7, 77.7, 93.6, 125.3", \ + "97.5, 97.5, 97.5, 113.8, 146.3", \ + "136.3, 136.3, 136.3, 152.9, 185.7", \ + "213.1, 213.1, 213.1, 230.0, 263.4"); + } + rise_transition (inslew_load_5x5__12) { + values ("130.5, 130.5, 130.5, 158.3, 214.4", \ + "176.9, 176.9, 176.9, 204.5, 260.0", \ + "266.8, 266.8, 266.8, 294.0, 348.6", \ + "446.0, 446.0, 446.0, 472.9, 526.7", \ + "804.5, 804.5, 804.5, 831.2, 884.5"); + } + cell_fall (inslew_load_5x5__12) { + values ("27.6, 27.6, 27.6, 35.9, 51.8", \ + "27.2, 27.2, 27.2, 36.5, 54.1", \ + "23.2, 23.2, 23.2, 33.7, 53.5", \ + "12.5, 12.5, 12.5, 24.1, 46.2", \ + "-10.9, -10.9, -10.9, 1.4, 25.3"); + } + fall_transition (inslew_load_5x5__12) { + values ("42.4, 42.4, 42.4, 52.5, 72.8", \ + "58.3, 58.3, 58.3, 68.5, 88.7", \ + "89.1, 89.1, 89.1, 99.6, 120.2", \ + "149.8, 149.8, 149.8, 160.5, 181.7", \ + "270.4, 270.4, 270.4, 281.4, 303.0"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("54.1, 54.1, 54.1, 70.0, 101.4", \ + "58.4, 58.4, 58.4, 74.9, 106.8", \ + "65.5, 65.5, 65.5, 82.3, 115.1", \ + "78.4, 78.4, 78.4, 95.7, 129.6", \ + "103.0, 103.0, 103.0, 120.8, 155.7"); + } + rise_transition (inslew_load_5x5__12) { + values ("109.0, 109.0, 109.0, 136.7, 192.6", \ + "144.9, 144.9, 144.9, 172.3, 227.5", \ + "215.1, 215.1, 215.1, 242.0, 296.2", \ + "352.9, 352.9, 352.9, 379.8, 435.4", \ + "629.6, 629.6, 629.6, 656.5, 710.3"); + } + cell_fall (inslew_load_5x5__12) { + values ("26.9, 26.9, 26.9, 36.3, 53.4", \ + "30.9, 30.9, 30.9, 41.5, 61.0", \ + "35.4, 35.4, 35.4, 47.4, 69.6", \ + "41.9, 41.9, 41.9, 55.0, 79.7", \ + "53.3, 53.3, 53.3, 67.1, 93.7"); + } + fall_transition (inslew_load_5x5__12) { + values ("37.0, 37.0, 37.0, 47.4, 67.8", \ + "55.7, 55.7, 55.7, 66.4, 87.1", \ + "91.4, 91.4, 91.4, 102.4, 123.9", \ + "161.5, 161.5, 161.5, 172.9, 195.1", \ + "301.1, 301.1, 301.1, 312.6, 335.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__12) { + values ("167.4, 167.4, 167.4, 227.2, 347.0", \ + "248.9, 248.9, 248.9, 308.8, 428.5", \ + "412.0, 412.0, 412.0, 471.9, 591.6", \ + "738.3, 738.3, 738.3, 798.1, 917.9", \ + "1390.7, 1390.7, 1390.7, 1450.6, 1570.3"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("131.4, 131.4, 131.4, 191.2, 311.0", \ + "160.1, 160.1, 160.1, 220.0, 339.7", \ + "217.7, 217.7, 217.7, 277.6, 397.3", \ + "332.8, 332.8, 332.8, 392.6, 512.4", \ + "562.9, 562.9, 562.9, 622.8, 742.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__12) { + values ("122.9, 122.9, 122.9, 182.7, 302.5", \ + "187.6, 187.6, 187.6, 247.5, 367.2", \ + "317.1, 317.1, 317.1, 377.0, 496.7", \ + "576.2, 576.2, 576.2, 636.1, 755.8", \ + "1094.3, 1094.3, 1094.3, 1154.1, 1273.9"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("93.9, 93.9, 93.9, 153.8, 273.5", \ + "126.2, 126.2, 126.2, 186.1, 305.8", \ + "190.8, 190.8, 190.8, 250.7, 370.4", \ + "320.0, 320.0, 320.0, 379.9, 499.6", \ + "578.4, 578.4, 578.4, 638.2, 758.0"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__12) { + values ("274.1, 274.1, 274.1, 334.0, 453.7", \ + "360.8, 360.8, 360.8, 420.7, 540.4", \ + "534.2, 534.2, 534.2, 594.1, 713.8", \ + "881.1, 881.1, 881.1, 940.9, 1060.7", \ + "1574.7, 1574.7, 1574.7, 1634.6, 1754.3"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("214.5, 214.5, 214.5, 274.4, 394.1", \ + "270.6, 270.6, 270.6, 330.4, 450.2", \ + "382.6, 382.6, 382.6, 442.5, 562.2", \ + "606.8, 606.8, 606.8, 666.6, 786.4", \ + "1055.1, 1055.1, 1055.1, 1114.9, 1234.7"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__12) { + values ("224.3, 224.3, 224.3, 284.2, 403.9", \ + "289.0, 289.0, 289.0, 348.8, 468.6", \ + "418.2, 418.2, 418.2, 478.1, 597.8", \ + "676.7, 676.7, 676.7, 736.5, 856.3", \ + "1193.6, 1193.6, 1193.6, 1253.5, 1373.2"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("178.0, 178.0, 178.0, 237.9, 357.6", \ + "238.4, 238.4, 238.4, 298.3, 418.0", \ + "359.4, 359.4, 359.4, 419.2, 539.0", \ + "601.2, 601.2, 601.2, 661.1, 780.8", \ + "1084.8, 1084.8, 1084.8, 1144.7, 1264.4"); + } + } + } + } + + cell (noa2a22_x4) { + area : 0.0 ; + cell_leakage_power : 3 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 4.2 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3)" ; + value : 4 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 3.7 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!(i2) | !(i3)))" ; + value : 0.26 ; + } + pin (i3) { + direction : input ; + capacitance : 3.42 ; + } + pin (i2) { + direction : input ; + capacitance : 3.36 ; + } + pin (i1) { + direction : input ; + capacitance : 3.52 ; + } + pin (i0) { + direction : input ; + capacitance : 3.55 ; + } + pin (nq) { + function : "((!(i1) & (!(i3) | !(i2))) | (!((i3 & i2)) & !(i0)))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("133.2, 133.2, 133.2, 139.2, 149.9", \ + "154.4, 154.4, 154.4, 160.4, 171.4", \ + "191.6, 191.6, 191.6, 197.6, 209.0", \ + "258.2, 258.2, 258.2, 264.4, 276.0", \ + "382.0, 382.0, 382.0, 388.3, 400.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("51.4, 51.4, 51.4, 59.0, 74.1", \ + "60.7, 60.7, 60.7, 68.3, 83.4", \ + "78.2, 78.2, 78.2, 86.0, 101.1", \ + "111.6, 111.6, 111.6, 119.4, 134.7", \ + "176.8, 176.8, 176.8, 184.4, 199.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("94.0, 94.0, 94.0, 99.4, 109.3", \ + "92.9, 92.9, 92.9, 98.3, 108.3", \ + "84.0, 84.0, 84.0, 89.6, 99.6", \ + "57.8, 57.8, 57.8, 63.5, 73.6", \ + "-4.7, -4.7, -4.7, 1.3, 11.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("35.6, 35.6, 35.6, 39.2, 46.0", \ + "37.9, 37.9, 37.9, 41.4, 48.3", \ + "42.0, 42.0, 42.0, 45.5, 52.5", \ + "49.6, 49.6, 49.6, 53.2, 60.3", \ + "64.0, 64.0, 64.0, 67.6, 74.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("121.2, 121.2, 121.2, 127.2, 137.8", \ + "137.1, 137.1, 137.1, 143.2, 154.1", \ + "164.8, 164.8, 164.8, 170.8, 182.1", \ + "210.4, 210.4, 210.4, 216.6, 228.1", \ + "293.2, 293.2, 293.2, 299.5, 311.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("47.5, 47.5, 47.5, 55.2, 70.2", \ + "55.4, 55.4, 55.4, 63.0, 78.1", \ + "70.5, 70.5, 70.5, 78.3, 93.4", \ + "98.7, 98.7, 98.7, 106.4, 121.7", \ + "153.2, 153.2, 153.2, 160.9, 176.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("94.1, 94.1, 94.1, 99.4, 109.3", \ + "97.3, 97.3, 97.3, 102.7, 112.7", \ + "95.4, 95.4, 95.4, 101.0, 110.9", \ + "81.9, 81.9, 81.9, 87.8, 97.9", \ + "45.5, 45.5, 45.5, 51.4, 62.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("34.8, 34.8, 34.8, 38.4, 45.1", \ + "37.7, 37.7, 37.7, 41.2, 48.1", \ + "42.7, 42.7, 42.7, 46.3, 53.3", \ + "52.0, 52.0, 52.0, 55.6, 62.7", \ + "69.6, 69.6, 69.6, 73.2, 80.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("161.5, 161.5, 161.5, 167.5, 178.6", \ + "174.4, 174.4, 174.4, 180.3, 191.7", \ + "195.9, 195.9, 195.9, 202.0, 213.5", \ + "235.8, 235.8, 235.8, 242.0, 253.8", \ + "309.5, 309.5, 309.5, 315.8, 328.1"); + } + rise_transition (inslew_load_5x5__1) { + values ("62.4, 62.4, 62.4, 70.1, 85.2", \ + "70.8, 70.8, 70.8, 78.5, 93.6", \ + "87.0, 87.0, 87.0, 94.7, 110.0", \ + "118.4, 118.4, 118.4, 126.1, 141.4", \ + "180.8, 180.8, 180.8, 188.4, 203.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("108.4, 108.4, 108.4, 113.9, 123.8", \ + "113.4, 113.4, 113.4, 118.9, 128.9", \ + "117.4, 117.4, 117.4, 123.1, 133.1", \ + "117.6, 117.6, 117.6, 123.6, 134.0", \ + "109.7, 109.7, 109.7, 115.8, 127.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("38.4, 38.4, 38.4, 42.0, 48.8", \ + "41.4, 41.4, 41.4, 45.0, 52.0", \ + "47.3, 47.3, 47.3, 50.9, 58.0", \ + "58.5, 58.5, 58.5, 62.1, 69.1", \ + "80.2, 80.2, 80.2, 83.8, 90.8"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("149.0, 149.0, 149.0, 155.0, 166.0", \ + "156.1, 156.1, 156.1, 162.1, 173.3", \ + "166.5, 166.5, 166.5, 172.6, 184.0", \ + "183.5, 183.5, 183.5, 189.7, 201.3", \ + "211.5, 211.5, 211.5, 217.8, 229.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("58.3, 58.3, 58.3, 65.9, 81.0", \ + "64.9, 64.9, 64.9, 72.6, 87.7", \ + "77.8, 77.8, 77.8, 85.5, 100.7", \ + "102.9, 102.9, 102.9, 110.7, 126.0", \ + "151.5, 151.5, 151.5, 159.2, 174.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("109.8, 109.8, 109.8, 115.2, 125.2", \ + "120.9, 120.9, 120.9, 126.4, 136.4", \ + "134.5, 134.5, 134.5, 140.2, 150.2", \ + "152.5, 152.5, 152.5, 158.5, 169.0", \ + "179.8, 179.8, 179.8, 185.8, 197.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("37.6, 37.6, 37.6, 41.1, 48.0", \ + "41.5, 41.5, 41.5, 45.0, 52.0", \ + "48.5, 48.5, 48.5, 52.1, 59.2", \ + "61.8, 61.8, 61.8, 65.5, 72.5", \ + "87.6, 87.6, 87.6, 91.2, 98.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("665.4, 665.4, 665.4, 725.0, 844.2", \ + "778.8, 778.8, 778.8, 838.4, 957.6", \ + "1000.5, 1000.5, 1000.5, 1060.1, 1179.3", \ + "1436.0, 1436.0, 1436.0, 1495.6, 1614.8", \ + "2297.7, 2297.7, 2297.7, 2357.3, 2476.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("609.4, 609.4, 609.4, 669.0, 788.2", \ + "647.7, 647.7, 647.7, 707.3, 826.5", \ + "721.2, 721.2, 721.2, 780.8, 900.0", \ + "861.9, 861.9, 861.9, 921.5, 1040.7", \ + "1135.9, 1135.9, 1135.9, 1195.5, 1314.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("612.8, 612.8, 612.8, 672.4, 791.6", \ + "705.8, 705.8, 705.8, 765.4, 884.6", \ + "891.2, 891.2, 891.2, 950.8, 1070.0", \ + "1249.5, 1249.5, 1249.5, 1309.1, 1428.3", \ + "1957.9, 1957.9, 1957.9, 2017.5, 2136.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("580.2, 580.2, 580.2, 639.8, 759.0", \ + "627.2, 627.2, 627.2, 686.8, 806.0", \ + "714.7, 714.7, 714.7, 774.3, 893.5", \ + "881.2, 881.2, 881.2, 940.8, 1060.0", \ + "1206.1, 1206.1, 1206.1, 1265.7, 1384.9"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("814.7, 814.7, 814.7, 874.3, 993.4", \ + "925.1, 925.1, 925.1, 984.7, 1103.9", \ + "1142.4, 1142.4, 1142.4, 1202.0, 1321.2", \ + "1573.6, 1573.6, 1573.6, 1633.2, 1752.4", \ + "2435.4, 2435.4, 2435.4, 2495.0, 2614.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("683.8, 683.8, 683.8, 743.4, 862.6", \ + "744.7, 744.7, 744.7, 804.3, 923.5", \ + "864.5, 864.5, 864.5, 924.1, 1043.3", \ + "1098.8, 1098.8, 1098.8, 1158.4, 1277.6", \ + "1561.6, 1561.6, 1561.6, 1621.2, 1740.4"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("756.2, 756.2, 756.2, 815.8, 935.0", \ + "841.6, 841.6, 841.6, 901.2, 1020.4", \ + "1010.3, 1010.3, 1010.3, 1069.9, 1189.1", \ + "1346.4, 1346.4, 1346.4, 1406.0, 1525.2", \ + "2007.8, 2007.8, 2007.8, 2067.4, 2186.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("655.1, 655.1, 655.1, 714.7, 833.9", \ + "727.2, 727.2, 727.2, 786.8, 906.0", \ + "864.1, 864.1, 864.1, 923.7, 1042.9", \ + "1130.6, 1130.6, 1130.6, 1190.2, 1309.4", \ + "1656.1, 1656.1, 1656.1, 1715.7, 1834.9"); + } + } + } + } + + cell (noa2a2a23_x1) { + area : 0.0 ; + cell_leakage_power : 5 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5))" ; + value : 18 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & i3) | (!(i4) & !(i5))))" ; + value : 21 ; + } + leakage_power () { + when : "(!(i5) & i4 & !(i3) & i2 & !(i1) & i0)" ; + value : 0.00025 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & !(i3) & i4 & i5) | (!(i2) & ((i3 & i4 & i5) | (!(i3) & (i4 ^ i5)))))) | (!(i1) & i2 & i3))) | (!(i0) & i1 & i2 & i3))" ; + value : 14 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & i5) | (!(i2) & i3 & i4 & !(i5)))) | (!(i0) & i1 & i2 & !(i3) & i4 & !(i5)))" ; + value : 0.00024 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5)" ; + value : 11 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & !(i4) & i5) | (!(i0) & i1 & ((i2 & !(i3) & !(i4) & i5) | (!(i2) & i3 & i4 & !(i5)))))" ; + value : 0.00022 ; + } + leakage_power () { + when : "(i5 & !(i4) & i3 & !(i2) & i1 & !(i0))" ; + value : 0.0002 ; + } + leakage_power () { + when : "((i0 & i1 & !(i2) & !(i3) & i4 & i5) | (!(i0) & !(i1) & i2 & i3))" ; + value : 7.8 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & i4 & !(i5)))) | (!(i0) & !(i1) & i2 & !(i3) & i4 & !(i5)))" ; + value : 0.00017 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & i4 & i5) | (!(i0) & ((i1 & !(i2) & !(i3) & i4 & i5) | (!(i1) & (i2 ^ i3) & i4 & i5))))" ; + value : 7.4 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5)) | (!(i3) & !(i4) & i5))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & i4 & !(i5)))) | (!(i1) & ((i2 & !(i3) & !(i4) & i5) | (!(i2) & i3 & i4 & !(i5)))))))" ; + value : 0.00015 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & ((i3 & !(i4) & !(i5)) | (!(i3) & !(i4) & i5))) | (!(i1) & !(i2) & i3 & !(i4) & i5)))" ; + value : 0.00014 ; + } + leakage_power () { + when : "(i5 & i4 & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 7 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & i4 & !(i5)))))" ; + value : 8.8e-05 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i1) & !(i2) & ((i3 & !(i4) & !(i5)) | (!(i3) & !(i4) & i5)))))" ; + value : 7.1e-05 ; + } + leakage_power () { + when : "(!(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 4.3e-06 ; + } + pin (i5) { + direction : input ; + capacitance : 5.67 ; + } + pin (i4) { + direction : input ; + capacitance : 5.57 ; + } + pin (i3) { + direction : input ; + capacitance : 5.46 ; + } + pin (i2) { + direction : input ; + capacitance : 5.57 ; + } + pin (i1) { + direction : input ; + capacitance : 5.67 ; + } + pin (i0) { + direction : input ; + capacitance : 5.70 ; + } + pin (nq) { + function : "(((((((((!(i1) & !(i2)) & !(i5)) | ((!(i1) & !(i2)) & !(i4))) | ((!(i1) & !(i3)) & !(i5))) | ((!(i1) & !(i3)) & !(i4))) | ((!(i0) & !(i2)) & !(i5))) | ((!(i0) & !(i2)) & !(i4))) | ((!(i0) & !(i3)) & !(i5))) | ((!(i0) & !(i3)) & !(i4)))" ; + direction : output ; + capacitance : 6.30 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("62.6, 62.6, 62.6, 95.0, 158.4", \ + "91.2, 91.2, 91.2, 124.2, 188.3", \ + "138.3, 138.3, 138.3, 172.2, 238.0", \ + "237.7, 237.7, 237.7, 272.1, 339.5", \ + "431.0, 431.0, 431.0, 465.9, 534.6"); + } + rise_transition (inslew_load_5x5__20) { + values ("114.5, 114.5, 114.5, 170.6, 284.3", \ + "183.3, 183.3, 183.3, 238.9, 351.4", \ + "300.5, 300.5, 300.5, 355.6, 466.8", \ + "541.7, 541.7, 541.7, 598.8, 707.8", \ + "1017.8, 1017.8, 1017.8, 1072.5, 1181.6"); + } + cell_fall (inslew_load_5x5__20) { + values ("16.7, 16.7, 16.7, 28.6, 50.1", \ + "7.5, 7.5, 7.5, 21.8, 46.4", \ + "-15.1, -15.1, -15.1, 2.1, 31.8", \ + "-65.7, -65.7, -65.7, -44.9, -8.8", \ + "-171.7, -171.7, -171.7, -147.7, -104.8"); + } + fall_transition (inslew_load_5x5__20) { + values ("30.6, 30.6, 30.6, 44.0, 70.7", \ + "39.1, 39.1, 39.1, 53.1, 79.9", \ + "54.7, 54.7, 54.7, 69.7, 97.8", \ + "84.3, 84.3, 84.3, 100.4, 130.6", \ + "141.6, 141.6, 141.6, 158.9, 191.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("47.5, 47.5, 47.5, 80.1, 143.8", \ + "69.0, 69.0, 69.0, 102.7, 167.4", \ + "103.7, 103.7, 103.7, 137.9, 205.0", \ + "177.9, 177.9, 177.9, 213.1, 282.2", \ + "321.6, 321.6, 321.6, 357.1, 428.2"); + } + rise_transition (inslew_load_5x5__20) { + values ("89.4, 89.4, 89.4, 144.6, 257.9", \ + "147.2, 147.2, 147.2, 202.5, 314.4", \ + "245.0, 245.0, 245.0, 300.0, 410.5", \ + "449.2, 449.2, 449.2, 503.1, 614.9", \ + "850.9, 850.9, 850.9, 904.3, 1013.4"); + } + cell_fall (inslew_load_5x5__20) { + values ("14.6, 14.6, 14.6, 28.6, 51.9", \ + "7.5, 7.5, 7.5, 24.7, 52.5", \ + "-10.6, -10.6, -10.6, 10.2, 44.4", \ + "-50.7, -50.7, -50.7, -26.3, 15.3", \ + "-133.6, -133.6, -133.6, -106.4, -57.7"); + } + fall_transition (inslew_load_5x5__20) { + values ("25.1, 25.1, 25.1, 39.1, 66.0", \ + "35.1, 35.1, 35.1, 50.1, 78.0", \ + "53.5, 53.5, 53.5, 69.8, 99.8", \ + "88.9, 88.9, 88.9, 106.5, 139.1", \ + "158.7, 158.7, 158.7, 177.3, 212.4"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("110.1, 110.1, 110.1, 141.5, 204.0", \ + "134.9, 134.9, 134.9, 166.5, 229.4", \ + "178.8, 178.8, 178.8, 210.7, 274.0", \ + "263.4, 263.4, 263.4, 295.6, 360.1", \ + "431.2, 431.2, 431.2, 463.8, 528.4"); + } + rise_transition (inslew_load_5x5__20) { + values ("199.0, 199.0, 199.0, 254.7, 366.7", \ + "266.3, 266.3, 266.3, 321.7, 433.0", \ + "390.7, 390.7, 390.7, 445.5, 555.9", \ + "635.2, 635.2, 635.2, 689.5, 798.6", \ + "1123.1, 1123.1, 1123.1, 1176.8, 1284.6"); + } + cell_fall (inslew_load_5x5__20) { + values ("26.8, 26.8, 26.8, 37.7, 58.5", \ + "21.5, 21.5, 21.5, 34.2, 57.3", \ + "6.3, 6.3, 6.3, 21.3, 48.3", \ + "-29.4, -29.4, -29.4, -11.9, 20.0", \ + "-106.1, -106.1, -106.1, -86.3, -49.5"); + } + fall_transition (inslew_load_5x5__20) { + values ("41.5, 41.5, 41.5, 54.9, 81.5", \ + "52.4, 52.4, 52.4, 66.0, 92.6", \ + "73.1, 73.1, 73.1, 87.3, 114.7", \ + "112.8, 112.8, 112.8, 127.8, 156.6", \ + "190.6, 190.6, 190.6, 206.2, 236.7"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("94.2, 94.2, 94.2, 125.7, 188.3", \ + "111.1, 111.1, 111.1, 143.0, 206.1", \ + "140.3, 140.3, 140.3, 172.9, 236.7", \ + "196.5, 196.5, 196.5, 229.4, 294.2", \ + "307.4, 307.4, 307.4, 340.7, 406.6"); + } + rise_transition (inslew_load_5x5__20) { + values ("171.2, 171.2, 171.2, 226.7, 338.5", \ + "225.5, 225.5, 225.5, 280.6, 391.7", \ + "326.3, 326.3, 326.3, 380.8, 490.7", \ + "525.4, 525.4, 525.4, 579.1, 687.2", \ + "922.9, 922.9, 922.9, 976.1, 1082.8"); + } + cell_fall (inslew_load_5x5__20) { + values ("26.3, 26.3, 26.3, 38.5, 60.6", \ + "24.4, 24.4, 24.4, 39.0, 64.6", \ + "15.4, 15.4, 15.4, 32.8, 63.5", \ + "-7.2, -7.2, -7.2, 12.8, 49.1", \ + "-56.4, -56.4, -56.4, -34.2, 7.1"); + } + fall_transition (inslew_load_5x5__20) { + values ("36.4, 36.4, 36.4, 50.0, 77.0", \ + "49.5, 49.5, 49.5, 63.7, 91.1", \ + "73.9, 73.9, 73.9, 89.0, 117.8", \ + "120.9, 120.9, 120.9, 137.0, 167.6", \ + "213.5, 213.5, 213.5, 230.2, 262.6"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("142.1, 142.1, 142.1, 173.0, 235.1", \ + "160.3, 160.3, 160.3, 191.5, 253.8", \ + "192.7, 192.7, 192.7, 224.2, 286.8", \ + "257.1, 257.1, 257.1, 288.5, 351.3", \ + "386.6, 386.6, 386.6, 418.0, 480.6"); + } + rise_transition (inslew_load_5x5__20) { + values ("262.3, 262.3, 262.3, 317.2, 427.5", \ + "329.2, 329.2, 329.2, 383.9, 493.6", \ + "454.7, 454.7, 454.7, 509.5, 619.2", \ + "701.2, 701.2, 701.2, 755.9, 865.6", \ + "1192.8, 1192.8, 1192.8, 1247.3, 1356.6"); + } + cell_fall (inslew_load_5x5__20) { + values ("36.1, 36.1, 36.1, 46.6, 66.9", \ + "36.7, 36.7, 36.7, 48.3, 70.2", \ + "34.0, 34.0, 34.0, 47.0, 71.7", \ + "24.3, 24.3, 24.3, 38.9, 66.6", \ + "1.5, 1.5, 1.5, 17.3, 47.8"); + } + fall_transition (inslew_load_5x5__20) { + values ("52.4, 52.4, 52.4, 65.8, 92.6", \ + "68.4, 68.4, 68.4, 81.7, 108.2", \ + "99.4, 99.4, 99.4, 113.0, 139.8", \ + "160.3, 160.3, 160.3, 174.3, 201.8", \ + "281.2, 281.2, 281.2, 295.5, 323.7"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("123.7, 123.7, 123.7, 154.8, 216.9", \ + "132.3, 132.3, 132.3, 163.7, 226.1", \ + "146.5, 146.5, 146.5, 178.2, 241.1", \ + "175.4, 175.4, 175.4, 207.1, 270.1", \ + "234.3, 234.3, 234.3, 265.9, 329.0"); + } + rise_transition (inslew_load_5x5__20) { + values ("230.1, 230.1, 230.1, 284.9, 395.1", \ + "280.8, 280.8, 280.8, 335.4, 444.9", \ + "375.0, 375.0, 375.0, 429.7, 539.2", \ + "560.2, 560.2, 560.2, 614.7, 724.0", \ + "931.9, 931.9, 931.9, 985.8, 1094.0"); + } + cell_fall (inslew_load_5x5__20) { + values ("36.5, 36.5, 36.5, 47.8, 69.0", \ + "41.7, 41.7, 41.7, 54.7, 78.5", \ + "47.6, 47.6, 47.6, 62.3, 89.7", \ + "55.1, 55.1, 55.1, 71.5, 102.4", \ + "67.2, 67.2, 67.2, 84.8, 118.7"); + } + fall_transition (inslew_load_5x5__20) { + values ("47.2, 47.2, 47.2, 60.7, 87.7", \ + "66.2, 66.2, 66.2, 80.0, 106.9", \ + "102.2, 102.2, 102.2, 116.5, 144.2", \ + "172.7, 172.7, 172.7, 187.4, 216.2", \ + "312.4, 312.4, 312.4, 327.5, 357.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__20) { + values ("180.4, 180.4, 180.4, 259.1, 416.7", \ + "254.8, 254.8, 254.8, 333.6, 491.1", \ + "403.6, 403.6, 403.6, 482.4, 639.9", \ + "701.3, 701.3, 701.3, 780.0, 937.6", \ + "1296.6, 1296.6, 1296.6, 1375.4, 1532.9"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("138.0, 138.0, 138.0, 216.7, 374.3", \ + "155.6, 155.6, 155.6, 234.4, 392.0", \ + "190.9, 190.9, 190.9, 269.7, 427.3", \ + "261.6, 261.6, 261.6, 340.4, 497.9", \ + "402.9, 402.9, 402.9, 481.7, 639.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__20) { + values ("139.2, 139.2, 139.2, 217.9, 375.5", \ + "200.1, 200.1, 200.1, 278.8, 436.4", \ + "321.9, 321.9, 321.9, 400.7, 558.2", \ + "565.5, 565.5, 565.5, 644.3, 801.9", \ + "1052.9, 1052.9, 1052.9, 1131.6, 1289.2"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("99.9, 99.9, 99.9, 178.7, 336.2", \ + "120.4, 120.4, 120.4, 199.2, 356.8", \ + "161.5, 161.5, 161.5, 240.3, 397.9", \ + "243.8, 243.8, 243.8, 322.5, 480.1", \ + "408.2, 408.2, 408.2, 487.0, 644.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__20) { + values ("292.0, 292.0, 292.0, 370.8, 528.3", \ + "373.5, 373.5, 373.5, 452.3, 609.9", \ + "536.7, 536.7, 536.7, 615.4, 773.0", \ + "862.9, 862.9, 862.9, 941.7, 1099.2", \ + "1515.3, 1515.3, 1515.3, 1594.1, 1751.7"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("204.0, 204.0, 204.0, 282.8, 440.4", \ + "232.8, 232.8, 232.8, 311.6, 469.1", \ + "290.3, 290.3, 290.3, 369.1, 526.7", \ + "405.4, 405.4, 405.4, 484.2, 641.8", \ + "635.6, 635.6, 635.6, 714.4, 871.9"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__20) { + values ("247.5, 247.5, 247.5, 326.3, 483.8", \ + "312.3, 312.3, 312.3, 391.0, 548.6", \ + "441.8, 441.8, 441.8, 520.6, 678.1", \ + "700.8, 700.8, 700.8, 779.6, 937.2", \ + "1218.9, 1218.9, 1218.9, 1297.7, 1455.3"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("166.6, 166.6, 166.6, 245.4, 402.9", \ + "198.9, 198.9, 198.9, 277.6, 435.2", \ + "263.5, 263.5, 263.5, 342.2, 499.8", \ + "392.6, 392.6, 392.6, 471.4, 629.0", \ + "651.0, 651.0, 651.0, 729.8, 887.4"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__20) { + values ("376.7, 376.7, 376.7, 455.5, 613.0", \ + "463.4, 463.4, 463.4, 542.2, 699.7", \ + "636.8, 636.8, 636.8, 715.6, 873.1", \ + "983.6, 983.6, 983.6, 1062.4, 1220.0", \ + "1677.3, 1677.3, 1677.3, 1756.1, 1913.6"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("274.0, 274.0, 274.0, 352.7, 510.3", \ + "330.0, 330.0, 330.0, 408.8, 566.3", \ + "442.1, 442.1, 442.1, 520.9, 678.4", \ + "666.2, 666.2, 666.2, 745.0, 902.5", \ + "1114.5, 1114.5, 1114.5, 1193.3, 1350.8"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__20) { + values ("326.9, 326.9, 326.9, 405.7, 563.2", \ + "391.5, 391.5, 391.5, 470.3, 627.9", \ + "520.8, 520.8, 520.8, 599.5, 757.1", \ + "779.2, 779.2, 779.2, 858.0, 1015.6", \ + "1296.2, 1296.2, 1296.2, 1375.0, 1532.5"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("237.4, 237.4, 237.4, 316.2, 473.8", \ + "297.9, 297.9, 297.9, 376.7, 534.2", \ + "418.8, 418.8, 418.8, 497.6, 655.1", \ + "660.6, 660.6, 660.6, 739.4, 897.0", \ + "1144.3, 1144.3, 1144.3, 1223.0, 1380.6"); + } + } + } + } + + cell (noa2a2a23_x4) { + area : 0.0 ; + cell_leakage_power : 4 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5))" ; + value : 5 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & i3) | (!(i4) & !(i5))))" ; + value : 5.3 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & !(i3) & i4 & i5) | (!(i2) & ((i3 & i4 & i5) | (!(i3) & (i4 ^ i5)))))) | (!(i1) & i2 & i3))) | (!(i0) & i1 & i2 & i3))" ; + value : 4.8 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5)" ; + value : 4.5 ; + } + leakage_power () { + when : "((i0 & i1 & !(i2) & !(i3) & i4 & i5) | (!(i0) & !(i1) & i2 & i3))" ; + value : 4.3 ; + } + leakage_power () { + when : "((!(i0) & ((!(i1) & !((i2 & i3)) & i4 & i5) | (!(i2) & !(i3) & i4 & i5))) | (!(i1) & !(i2) & !(i3) & i4 & i5))" ; + value : 4.2 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !((i2 & i3)) & (!(i4) | !(i5)))" ; + value : 0.26 ; + } + pin (i5) { + direction : input ; + capacitance : 3.39 ; + } + pin (i4) { + direction : input ; + capacitance : 3.42 ; + } + pin (i3) { + direction : input ; + capacitance : 3.31 ; + } + pin (i2) { + direction : input ; + capacitance : 3.42 ; + } + pin (i1) { + direction : input ; + capacitance : 3.52 ; + } + pin (i0) { + direction : input ; + capacitance : 3.55 ; + } + pin (nq) { + function : "((!(i1) & ((!(i3) & (!(i4) | !(i5))) | (!((i4 & i5)) & !(i2)))) | (!(i3) & !((i4 & i5)) & !(i0)) | (!((i4 & i5)) & !(i2) & !(i0)))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("167.7, 167.7, 167.7, 173.7, 184.8", \ + "198.1, 198.1, 198.1, 204.1, 215.5", \ + "243.6, 243.6, 243.6, 249.8, 261.2", \ + "337.2, 337.2, 337.2, 343.5, 355.5", \ + "517.5, 517.5, 517.5, 523.9, 536.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("62.6, 62.6, 62.6, 70.2, 85.3", \ + "75.3, 75.3, 75.3, 83.0, 98.1", \ + "95.1, 95.1, 95.1, 102.9, 118.2", \ + "136.6, 136.6, 136.6, 144.3, 159.7", \ + "217.4, 217.4, 217.4, 225.0, 240.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("95.8, 95.8, 95.8, 101.1, 111.0", \ + "92.6, 92.6, 92.6, 98.0, 108.0", \ + "79.2, 79.2, 79.2, 84.7, 94.7", \ + "41.3, 41.3, 41.3, 47.0, 56.9", \ + "-47.7, -47.7, -47.7, -41.8, -31.4"); + } + fall_transition (inslew_load_5x5__1) { + values ("35.6, 35.6, 35.6, 39.2, 45.9", \ + "37.5, 37.5, 37.5, 41.1, 47.9", \ + "40.9, 40.9, 40.9, 44.4, 51.3", \ + "46.9, 46.9, 46.9, 50.5, 57.6", \ + "58.1, 58.1, 58.1, 61.7, 68.7"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("152.5, 152.5, 152.5, 158.5, 169.4", \ + "177.5, 177.5, 177.5, 183.5, 194.8", \ + "212.0, 212.0, 212.0, 218.1, 229.5", \ + "284.7, 284.7, 284.7, 290.9, 302.7", \ + "422.5, 422.5, 422.5, 428.8, 441.1"); + } + rise_transition (inslew_load_5x5__1) { + values ("57.5, 57.5, 57.5, 65.2, 80.3", \ + "68.7, 68.7, 68.7, 76.3, 91.4", \ + "85.7, 85.7, 85.7, 93.4, 108.6", \ + "120.8, 120.8, 120.8, 128.5, 143.8", \ + "190.3, 190.3, 190.3, 197.9, 213.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("96.2, 96.2, 96.2, 101.5, 111.4", \ + "97.0, 97.0, 97.0, 102.4, 112.4", \ + "88.8, 88.8, 88.8, 94.4, 104.3", \ + "60.6, 60.6, 60.6, 66.4, 76.4", \ + "-8.7, -8.7, -8.7, -2.7, 7.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("34.8, 34.8, 34.8, 38.4, 45.1", \ + "37.3, 37.3, 37.3, 40.8, 47.6", \ + "41.4, 41.4, 41.4, 45.0, 51.9", \ + "48.8, 48.8, 48.8, 52.4, 59.5", \ + "62.5, 62.5, 62.5, 66.2, 73.1"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("221.5, 221.5, 221.5, 227.5, 238.9", \ + "245.8, 245.8, 245.8, 251.9, 263.3", \ + "288.1, 288.1, 288.1, 294.3, 306.0", \ + "367.5, 367.5, 367.5, 373.8, 385.9", \ + "521.5, 521.5, 521.5, 527.9, 540.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("80.4, 80.4, 80.4, 88.2, 103.3", \ + "91.9, 91.9, 91.9, 99.7, 114.9", \ + "113.1, 113.1, 113.1, 120.8, 136.1", \ + "154.8, 154.8, 154.8, 162.5, 177.9", \ + "237.4, 237.4, 237.4, 245.0, 260.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("107.6, 107.6, 107.6, 113.0, 123.0", \ + "107.7, 107.7, 107.7, 113.2, 123.2", \ + "100.8, 100.8, 100.8, 106.4, 116.4", \ + "76.8, 76.8, 76.8, 82.7, 92.8", \ + "16.3, 16.3, 16.3, 22.3, 33.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("37.9, 37.9, 37.9, 41.5, 48.3", \ + "40.1, 40.1, 40.1, 43.7, 50.6", \ + "44.3, 44.3, 44.3, 47.8, 54.9", \ + "52.0, 52.0, 52.0, 55.5, 62.6", \ + "66.5, 66.5, 66.5, 70.1, 77.1"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("205.9, 205.9, 205.9, 211.9, 223.3", \ + "223.4, 223.4, 223.4, 229.5, 240.9", \ + "253.2, 253.2, 253.2, 259.4, 270.9", \ + "307.7, 307.7, 307.7, 313.9, 325.9", \ + "411.3, 411.3, 411.3, 417.6, 430.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("75.3, 75.3, 75.3, 83.0, 98.1", \ + "84.7, 84.7, 84.7, 92.5, 107.7", \ + "102.0, 102.0, 102.0, 109.7, 125.0", \ + "136.3, 136.3, 136.3, 144.0, 159.4", \ + "204.3, 204.3, 204.3, 211.9, 227.2"); + } + cell_fall (inslew_load_5x5__1) { + values ("109.2, 109.2, 109.2, 114.5, 124.5", \ + "114.5, 114.5, 114.5, 120.0, 130.0", \ + "115.2, 115.2, 115.2, 120.9, 130.8", \ + "104.3, 104.3, 104.3, 110.2, 120.4", \ + "70.0, 70.0, 70.0, 76.0, 86.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("37.1, 37.1, 37.1, 40.7, 47.5", \ + "40.1, 40.1, 40.1, 43.6, 50.5", \ + "45.3, 45.3, 45.3, 48.8, 55.9", \ + "54.6, 54.6, 54.6, 58.2, 65.3", \ + "72.4, 72.4, 72.4, 76.0, 83.0"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("254.2, 254.2, 254.2, 260.4, 271.8", \ + "272.1, 272.1, 272.1, 278.3, 289.9", \ + "303.1, 303.1, 303.1, 309.4, 321.2", \ + "362.5, 362.5, 362.5, 368.8, 381.0", \ + "479.8, 479.8, 479.8, 486.2, 498.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("92.1, 92.1, 92.1, 99.9, 115.2", \ + "103.7, 103.7, 103.7, 111.4, 126.7", \ + "125.3, 125.3, 125.3, 133.0, 148.4", \ + "167.3, 167.3, 167.3, 175.0, 190.4", \ + "250.7, 250.7, 250.7, 258.3, 273.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("118.8, 118.8, 118.8, 124.3, 134.3", \ + "124.3, 124.3, 124.3, 129.9, 139.9", \ + "129.1, 129.1, 129.1, 134.9, 144.9", \ + "130.4, 130.4, 130.4, 136.3, 146.8", \ + "123.3, 123.3, 123.3, 129.3, 140.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("40.1, 40.1, 40.1, 43.7, 50.6", \ + "43.2, 43.2, 43.2, 46.7, 53.7", \ + "49.0, 49.0, 49.0, 52.6, 59.7", \ + "60.2, 60.2, 60.2, 63.9, 70.8", \ + "82.0, 82.0, 82.0, 85.6, 92.6"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("236.8, 236.8, 236.8, 242.9, 254.3", \ + "246.2, 246.2, 246.2, 252.3, 263.8", \ + "261.3, 261.3, 261.3, 267.5, 279.2", \ + "289.7, 289.7, 289.7, 296.0, 308.0", \ + "345.3, 345.3, 345.3, 351.6, 364.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("86.5, 86.5, 86.5, 94.2, 109.4", \ + "95.3, 95.3, 95.3, 103.0, 118.3", \ + "111.7, 111.7, 111.7, 119.5, 134.8", \ + "143.9, 143.9, 143.9, 151.6, 167.0", \ + "207.9, 207.9, 207.9, 215.5, 230.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("121.1, 121.1, 121.1, 126.6, 136.5", \ + "133.2, 133.2, 133.2, 138.8, 148.8", \ + "148.1, 148.1, 148.1, 153.9, 163.9", \ + "167.4, 167.4, 167.4, 173.4, 184.0", \ + "195.4, 195.4, 195.4, 201.4, 212.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("39.3, 39.3, 39.3, 42.9, 49.7", \ + "43.3, 43.3, 43.3, 46.8, 53.8", \ + "50.3, 50.3, 50.3, 53.9, 61.0", \ + "63.7, 63.7, 63.7, 67.3, 74.3", \ + "89.5, 89.5, 89.5, 93.1, 100.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("761.1, 761.1, 761.1, 820.7, 939.9", \ + "900.8, 900.8, 900.8, 960.4, 1079.6", \ + "1137.1, 1137.1, 1137.1, 1196.7, 1315.9", \ + "1627.6, 1627.6, 1627.6, 1687.2, 1806.3", \ + "2594.1, 2594.1, 2594.1, 2653.7, 2772.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("612.3, 612.3, 612.3, 671.9, 791.1", \ + "641.6, 641.6, 641.6, 701.2, 820.4", \ + "695.8, 695.8, 695.8, 755.4, 874.6", \ + "797.5, 797.5, 797.5, 857.1, 976.3", \ + "991.2, 991.2, 991.2, 1050.8, 1169.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("699.9, 699.9, 699.9, 759.5, 878.7", \ + "819.4, 819.4, 819.4, 879.0, 998.2", \ + "1018.9, 1018.9, 1018.9, 1078.5, 1197.7", \ + "1430.3, 1430.3, 1430.3, 1489.9, 1609.1", \ + "2251.9, 2251.9, 2251.9, 2311.5, 2430.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("583.0, 583.0, 583.0, 642.6, 761.8", \ + "619.7, 619.7, 619.7, 679.3, 798.5", \ + "685.6, 685.6, 685.6, 745.2, 864.4", \ + "807.8, 807.8, 807.8, 867.4, 986.6", \ + "1041.4, 1041.4, 1041.4, 1101.0, 1220.2"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("970.5, 970.5, 970.5, 1030.1, 1149.3", \ + "1105.3, 1105.3, 1105.3, 1164.9, 1284.1", \ + "1361.2, 1361.2, 1361.2, 1420.8, 1540.0", \ + "1868.7, 1868.7, 1868.7, 1928.3, 2047.5", \ + "2880.8, 2880.8, 2880.8, 2940.4, 3059.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("673.1, 673.1, 673.1, 732.7, 851.9", \ + "711.3, 711.3, 711.3, 770.9, 890.1", \ + "785.5, 785.5, 785.5, 845.1, 964.3", \ + "927.1, 927.1, 927.1, 986.7, 1105.9", \ + "1202.4, 1202.4, 1202.4, 1262.0, 1381.2"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("905.6, 905.6, 905.6, 965.2, 1084.4", \ + "1014.8, 1014.8, 1014.8, 1074.4, 1193.6", \ + "1221.9, 1221.9, 1221.9, 1281.5, 1400.7", \ + "1634.9, 1634.9, 1634.9, 1694.5, 1813.7", \ + "2459.1, 2459.1, 2459.1, 2518.7, 2637.9"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("644.5, 644.5, 644.5, 704.1, 823.3", \ + "692.4, 692.4, 692.4, 752.0, 871.2", \ + "781.4, 781.4, 781.4, 841.0, 960.2", \ + "949.5, 949.5, 949.5, 1009.1, 1128.3", \ + "1275.4, 1275.4, 1275.4, 1335.0, 1454.2"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1113.3, 1113.3, 1113.3, 1172.9, 1292.1", \ + "1251.6, 1251.6, 1251.6, 1311.2, 1430.4", \ + "1516.9, 1516.9, 1516.9, 1576.5, 1695.7", \ + "2039.4, 2039.4, 2039.4, 2099.0, 2218.2", \ + "3080.6, 3080.6, 3080.6, 3140.2, 3259.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("734.8, 734.8, 734.8, 794.4, 913.5", \ + "795.4, 795.4, 795.4, 855.0, 974.1", \ + "914.9, 914.9, 914.9, 974.5, 1093.7", \ + "1149.2, 1149.2, 1149.2, 1208.8, 1328.0", \ + "1612.1, 1612.1, 1612.1, 1671.7, 1790.9"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1040.7, 1040.7, 1040.7, 1100.3, 1219.5", \ + "1145.9, 1145.9, 1145.9, 1205.5, 1324.7", \ + "1347.2, 1347.2, 1347.2, 1406.8, 1526.0", \ + "1744.2, 1744.2, 1744.2, 1803.8, 1923.0", \ + "2537.7, 2537.7, 2537.7, 2597.3, 2716.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("706.3, 706.3, 706.3, 765.9, 885.1", \ + "778.6, 778.6, 778.6, 838.2, 957.4", \ + "916.0, 916.0, 916.0, 975.6, 1094.8", \ + "1182.9, 1182.9, 1182.9, 1242.5, 1361.7", \ + "1708.0, 1708.0, 1708.0, 1767.6, 1886.8"); + } + } + } + } + + cell (noa2a2a2a24_x1) { + area : 0.0 ; + cell_leakage_power : 11 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5) & (i6 ^ i7))" ; + value : 18 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 13 ; + } + leakage_power () { + when : "(i7 & !(i6) & !(i5) & i4 & !(i3) & i2 & !(i1) & i0)" ; + value : 0.00034 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & i5 & !(i6) & i7))) | (!(i2) & i3 & i4 & !(i5) & !(i6) & i7))) | (!(i0) & i1 & i2 & !(i3) & i4 & !(i5) & !(i6) & i7))" ; + value : 0.00032 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5 & (i6 ^ i7))" ; + value : 25 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & i5 & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & i5 & !(i6) & i7))))) | (!(i0) & i1 & ((i2 & !(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & i5 & !(i6) & i7))) | (!(i2) & i3 & i4 & !(i5) & !(i6) & i7))))" ; + value : 0.00031 ; + } + leakage_power () { + when : "(!(i7) & i6 & i5 & !(i4) & i3 & !(i2) & i1 & !(i0))" ; + value : 0.00027 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & !(i4) & i5 & i6 & !(i7)) | (!(i0) & i1 & ((i2 & !(i3) & !(i4) & i5 & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & i5 & !(i6) & i7))))))" ; + value : 0.00029 ; + } + leakage_power () { + when : "(i2 & i3 & i4 & i5 & i6 & i7)" ; + value : 41 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & !((i4 & i5)) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & !((i4 & i5)) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (i2 & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))" ; + value : 28 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i2) & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i1) & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))) | (i2 & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 22 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))) | (!(i1) & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!((i2 & i3)) & i4 & i5 & !(i6) & !(i7)))))) | (!(i0) & ((i1 & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!((i2 & i3)) & i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))" ; + value : 15 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & ((!(i3) & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!(i4) & !(i5) & !(i6) & !(i7)))) | (!(i2) & ((i3 & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!(i3) & ((i4 & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i4) & ((i5 & (!(i6) | !(i7))) | (!(i5) & (i6 | i7)))))))))) | (i2 & i3 & !(i4) & !(i5) & !(i6) & !(i7)))" ; + value : 14 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & !(i6) & i7))) | (!(i2) & !(i3) & i4 & !(i5) & !(i6) & i7))) | (!(i0) & !(i1) & i2 & !(i3) & i4 & !(i5) & !(i6) & i7))" ; + value : 0.00026 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & (i5 ^ i6) & !(i7)) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & i5 & !(i6) & i7))))))) | (!(i0) & ((i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & !(i6) & i7))) | (!(i2) & !(i3) & i4 & !(i5) & !(i6) & i7))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & i5 & !(i6) & i7))) | (!(i2) & i3 & i4 & !(i5) & !(i6) & i7))))))" ; + value : 0.00024 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i1) & (i2 ^ i3) & (i4 ^ i5) & i6 & i7))))" ; + value : 35 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & ((i3 & !(i4) & (i5 ^ i6) & !(i7)) | (!(i3) & !(i4) & i5 & i6 & !(i7)))) | (!(i1) & !(i2) & i3 & !(i4) & i5 & i6 & !(i7))))" ; + value : 0.00021 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & (i5 ^ i6) & !(i7)) | (!(i3) & !(i4) & i5 & i6 & !(i7)))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & (i5 ^ i6) & !(i7)) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & i5 & !(i6) & i7))))))) | (!(i1) & ((i2 & !(i3) & !(i4) & i5 & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & i5 & !(i6) & i7))))))))" ; + value : 0.00022 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & !(i2) & !(i3) & i4 & i5 & i6 & i7) | (!(i1) & ((i2 & !(i3) & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))))" ; + value : 29 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & !(i3) & i4 & i5 & i6 & i7))) | (i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i0) & ((!(i1) & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))))" ; + value : 16 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & !(i6) & i7))))) | (!(i0) & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & !(i6) & i7))) | (!(i2) & !(i3) & i4 & !(i5) & !(i6) & i7))))" ; + value : 0.00017 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & !(i4) & (i5 ^ i6) & !(i7)))) | (!(i1) & !(i2) & ((i3 & !(i4) & (i5 ^ i6) & !(i7)) | (!(i3) & !(i4) & i5 & i6 & !(i7))))))" ; + value : 0.00014 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & !(i4) & (i5 ^ i6) & !(i7)))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & !(i6) & i7))))) | (!(i1) & ((i2 & !(i3) & !(i4) & (i5 ^ i6) & !(i7)) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & i5 & !(i6) & i7))))))))))" ; + value : 0.00016 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((!(i2) & ((!(i3) & i6 & i7) | (i4 & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7)))" ; + value : 42 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & !(i4) & (i5 ^ i6) & !(i7))))))" ; + value : 7.2e-05 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & !(i6) & i7))))))" ; + value : 8.9e-05 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.8e-06 ; + } + pin (i7) { + direction : input ; + capacitance : 5.81 ; + } + pin (i6) { + direction : input ; + capacitance : 5.57 ; + } + pin (i5) { + direction : input ; + capacitance : 5.57 ; + } + pin (i4) { + direction : input ; + capacitance : 5.59 ; + } + pin (i3) { + direction : input ; + capacitance : 5.57 ; + } + pin (i2) { + direction : input ; + capacitance : 5.51 ; + } + pin (i1) { + direction : input ; + capacitance : 5.78 ; + } + pin (i0) { + direction : input ; + capacitance : 5.70 ; + } + pin (nq) { + function : "((((((((((((((((((!(i7) & !(i5)) & !(i2)) & !(i0)) | (((!(i7) & !(i5)) & !(i2)) & !(i1))) | (((!(i7) & !(i5)) & !(i3)) & !(i0))) | (((!(i7) & !(i5)) & !(i3)) & !(i1))) | (((!(i7) & !(i4)) & !(i2)) & !(i0))) | (((!(i7) & !(i4)) & !(i2)) & !(i1))) | (((!(i7) & !(i4)) & !(i3)) & !(i0))) | (((!(i7) & !(i4)) & !(i3)) & !(i1))) | (((!(i6) & !(i5)) & !(i2)) & !(i0))) | (((!(i6) & !(i5)) & !(i2)) & !(i1))) | (((!(i6) & !(i5)) & !(i3)) & !(i0))) | (((!(i6) & !(i5)) & !(i3)) & !(i1))) | (((!(i6) & !(i4)) & !(i2)) & !(i0))) | (((!(i6) & !(i4)) & !(i2)) & !(i1))) | (((!(i6) & !(i4)) & !(i3)) & !(i0))) | (((!(i6) & !(i4)) & !(i3)) & !(i1)))" ; + direction : output ; + capacitance : 7.78 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("245.2, 245.2, 245.2, 296.9, 400.3", \ + "274.5, 274.5, 274.5, 326.1, 429.6", \ + "325.7, 325.7, 325.7, 377.7, 481.4", \ + "426.0, 426.0, 426.0, 478.0, 582.1", \ + "626.7, 626.7, 626.7, 678.7, 782.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("434.7, 434.7, 434.7, 525.2, 706.3", \ + "523.6, 523.6, 523.6, 613.7, 794.4", \ + "690.2, 690.2, 690.2, 780.1, 960.1", \ + "1016.7, 1016.7, 1016.7, 1106.8, 1287.0", \ + "1664.8, 1664.8, 1664.8, 1755.0, 1935.6"); + } + cell_fall (inslew_load_5x5__21) { + values ("38.1, 38.1, 38.1, 50.9, 75.7", \ + "38.9, 38.9, 38.9, 53.0, 79.7", \ + "36.5, 36.5, 36.5, 52.4, 82.2", \ + "27.1, 27.1, 27.1, 44.9, 78.5", \ + "4.6, 4.6, 4.6, 24.0, 61.0"); + } + fall_transition (inslew_load_5x5__21) { + values ("55.0, 55.0, 55.0, 71.5, 104.7", \ + "70.9, 70.9, 70.9, 87.3, 120.2", \ + "102.0, 102.0, 102.0, 118.7, 151.6", \ + "163.0, 163.0, 163.0, 180.2, 213.9", \ + "283.9, 283.9, 283.9, 301.5, 336.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("220.8, 220.8, 220.8, 272.4, 375.9", \ + "237.1, 237.1, 237.1, 288.9, 392.4", \ + "264.0, 264.0, 264.0, 316.1, 420.1", \ + "316.3, 316.3, 316.3, 368.6, 473.1", \ + "422.3, 422.3, 422.3, 474.5, 578.9"); + } + rise_transition (inslew_load_5x5__21) { + values ("392.1, 392.1, 392.1, 482.5, 663.6", \ + "459.0, 459.0, 459.0, 549.0, 729.4", \ + "584.3, 584.3, 584.3, 674.0, 853.8", \ + "828.2, 828.2, 828.2, 918.3, 1098.4", \ + "1311.8, 1311.8, 1311.8, 1401.9, 1582.4"); + } + cell_fall (inslew_load_5x5__21) { + values ("38.6, 38.6, 38.6, 52.4, 78.2", \ + "44.3, 44.3, 44.3, 59.9, 88.5", \ + "50.5, 50.5, 50.5, 68.4, 101.2", \ + "58.3, 58.3, 58.3, 78.3, 115.6", \ + "70.7, 70.7, 70.7, 92.2, 133.2"); + } + fall_transition (inslew_load_5x5__21) { + values ("49.8, 49.8, 49.8, 66.4, 99.7", \ + "68.8, 68.8, 68.8, 85.7, 118.8", \ + "105.0, 105.0, 105.0, 122.4, 156.4", \ + "175.5, 175.5, 175.5, 193.6, 228.8", \ + "315.2, 315.2, 315.2, 333.8, 370.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("203.1, 203.1, 203.1, 255.0, 358.9", \ + "238.6, 238.6, 238.6, 290.6, 394.6", \ + "297.3, 297.3, 297.3, 349.6, 453.9", \ + "409.6, 409.6, 409.6, 462.0, 566.6", \ + "632.5, 632.5, 632.5, 684.9, 789.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("356.0, 356.0, 356.0, 447.4, 630.5", \ + "447.1, 447.1, 447.1, 538.0, 720.6", \ + "608.8, 608.8, 608.8, 699.5, 881.5", \ + "921.7, 921.7, 921.7, 1012.5, 1194.3", \ + "1542.3, 1542.3, 1542.3, 1632.8, 1814.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("35.1, 35.1, 35.1, 48.0, 73.0", \ + "31.2, 31.2, 31.2, 45.8, 72.9", \ + "17.7, 17.7, 17.7, 34.9, 66.3", \ + "-16.1, -16.1, -16.1, 4.1, 41.2", \ + "-91.2, -91.2, -91.2, -67.9, -24.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("51.2, 51.2, 51.2, 67.8, 101.0", \ + "62.4, 62.4, 62.4, 78.9, 111.8", \ + "83.5, 83.5, 83.5, 100.6, 133.9", \ + "123.7, 123.7, 123.7, 141.8, 176.7", \ + "202.0, 202.0, 202.0, 221.1, 257.9"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("182.4, 182.4, 182.4, 234.4, 338.3", \ + "207.3, 207.3, 207.3, 259.4, 363.5", \ + "247.0, 247.0, 247.0, 299.5, 404.0", \ + "322.4, 322.4, 322.4, 375.1, 480.1", \ + "472.5, 472.5, 472.5, 525.2, 630.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("319.8, 319.8, 319.8, 411.1, 594.2", \ + "392.9, 392.9, 392.9, 483.6, 666.0", \ + "522.2, 522.2, 522.2, 612.8, 794.4", \ + "772.0, 772.0, 772.0, 862.5, 1043.9", \ + "1269.1, 1269.1, 1269.1, 1358.9, 1538.7"); + } + cell_fall (inslew_load_5x5__21) { + values ("35.6, 35.6, 35.6, 49.6, 75.6", \ + "35.5, 35.5, 35.5, 51.9, 81.4", \ + "28.7, 28.7, 28.7, 48.4, 83.4", \ + "7.9, 7.9, 7.9, 31.1, 72.9", \ + "-39.7, -39.7, -39.7, -13.5, 34.9"); + } + fall_transition (inslew_load_5x5__21) { + values ("46.4, 46.4, 46.4, 63.0, 96.3", \ + "60.0, 60.0, 60.0, 77.1, 110.3", \ + "85.0, 85.0, 85.0, 103.1, 137.7", \ + "132.7, 132.7, 132.7, 151.9, 188.7", \ + "225.7, 225.7, 225.7, 246.0, 285.2"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("150.6, 150.6, 150.6, 202.8, 307.3", \ + "187.0, 187.0, 187.0, 239.5, 344.2", \ + "247.2, 247.2, 247.2, 300.1, 405.3", \ + "366.4, 366.4, 366.4, 419.5, 525.1", \ + "600.6, 600.6, 600.6, 655.2, 761.2"); + } + rise_transition (inslew_load_5x5__21) { + values ("263.8, 263.8, 263.8, 356.1, 541.3", \ + "352.0, 352.0, 352.0, 443.8, 628.3", \ + "501.8, 501.8, 501.8, 593.3, 777.1", \ + "797.3, 797.3, 797.3, 887.9, 1070.1", \ + "1383.6, 1383.6, 1383.6, 1473.4, 1653.9"); + } + cell_fall (inslew_load_5x5__21) { + values ("27.8, 27.8, 27.8, 41.2, 66.6", \ + "20.8, 20.8, 20.8, 36.4, 64.4", \ + "1.0, 1.0, 1.0, 19.8, 53.0", \ + "-46.4, -46.4, -46.4, -23.4, 17.0", \ + "-149.5, -149.5, -149.5, -122.4, -73.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("42.8, 42.8, 42.8, 59.3, 92.3", \ + "51.7, 51.7, 51.7, 68.5, 101.2", \ + "68.2, 68.2, 68.2, 85.9, 119.6", \ + "98.8, 98.8, 98.8, 117.9, 153.8", \ + "157.2, 157.2, 157.2, 177.7, 216.6"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("131.3, 131.3, 131.3, 183.6, 288.1", \ + "159.0, 159.0, 159.0, 211.8, 316.6", \ + "203.6, 203.6, 203.6, 256.8, 362.3", \ + "292.5, 292.5, 292.5, 346.0, 452.2", \ + "465.9, 465.9, 465.9, 520.1, 628.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("230.2, 230.2, 230.2, 322.3, 507.4", \ + "303.7, 303.7, 303.7, 395.3, 579.5", \ + "427.5, 427.5, 427.5, 518.4, 701.8", \ + "672.9, 672.9, 672.9, 762.9, 944.3", \ + "1160.9, 1160.9, 1160.9, 1249.8, 1428.8"); + } + cell_fall (inslew_load_5x5__21) { + values ("27.6, 27.6, 27.6, 42.4, 69.0", \ + "23.5, 23.5, 23.5, 41.4, 72.2", \ + "8.7, 8.7, 8.7, 30.8, 68.3", \ + "-28.1, -28.1, -28.1, -1.4, 44.7", \ + "-108.5, -108.5, -108.5, -77.6, -22.3"); + } + fall_transition (inslew_load_5x5__21) { + values ("37.8, 37.8, 37.8, 54.5, 87.8", \ + "48.7, 48.7, 48.7, 66.2, 99.7", \ + "68.3, 68.3, 68.3, 87.2, 122.6", \ + "104.8, 104.8, 104.8, 125.4, 163.7", \ + "175.5, 175.5, 175.5, 197.5, 239.2"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("61.0, 61.0, 61.0, 112.6, 217.6", \ + "93.3, 93.3, 93.3, 147.4, 253.7", \ + "145.1, 145.1, 145.1, 200.5, 307.6", \ + "235.0, 235.0, 235.0, 291.4, 401.7", \ + "428.2, 428.2, 428.2, 485.5, 597.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("109.7, 109.7, 109.7, 197.4, 383.6", \ + "190.0, 190.0, 190.0, 281.3, 467.5", \ + "319.2, 319.2, 319.2, 410.3, 594.4", \ + "549.0, 549.0, 549.0, 639.2, 821.6", \ + "1027.0, 1027.0, 1027.0, 1120.8, 1300.0"); + } + cell_fall (inslew_load_5x5__21) { + values ("17.1, 17.1, 17.1, 33.5, 61.1", \ + "8.9, 8.9, 8.9, 29.4, 62.2", \ + "-12.6, -12.6, -12.6, 12.9, 53.8", \ + "-61.6, -61.6, -61.6, -30.3, 20.8", \ + "-164.6, -164.6, -164.6, -128.2, -65.7"); + } + fall_transition (inslew_load_5x5__21) { + values ("27.4, 27.4, 27.4, 44.5, 77.7", \ + "36.2, 36.2, 36.2, 54.5, 88.5", \ + "51.9, 51.9, 51.9, 72.1, 108.6", \ + "81.2, 81.2, 81.2, 103.4, 143.6", \ + "137.8, 137.8, 137.8, 162.0, 206.4"); + } + } + timing (maxd_nq_i7_negative_unate) { + related_pin : "i7" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("78.6, 78.6, 78.6, 130.6, 235.7", \ + "119.3, 119.3, 119.3, 173.1, 278.9", \ + "185.0, 185.0, 185.0, 239.0, 345.5", \ + "301.2, 301.2, 301.2, 356.5, 465.7", \ + "546.6, 546.6, 546.6, 602.4, 712.4"); + } + rise_transition (inslew_load_5x5__21) { + values ("139.0, 139.0, 139.0, 229.1, 416.0", \ + "233.3, 233.3, 233.3, 325.8, 512.3", \ + "384.2, 384.2, 384.2, 475.9, 660.9", \ + "655.0, 655.0, 655.0, 746.1, 929.3", \ + "1217.8, 1217.8, 1217.8, 1307.5, 1487.8"); + } + cell_fall (inslew_load_5x5__21) { + values ("18.7, 18.7, 18.7, 33.0, 58.9", \ + "8.8, 8.8, 8.8, 26.0, 55.3", \ + "-16.2, -16.2, -16.2, 4.9, 40.4", \ + "-73.5, -73.5, -73.5, -47.2, -3.0", \ + "-195.6, -195.6, -195.6, -164.0, -109.4"); + } + fall_transition (inslew_load_5x5__21) { + values ("32.8, 32.8, 32.8, 49.3, 82.2", \ + "40.3, 40.3, 40.3, 57.4, 90.3", \ + "53.7, 53.7, 53.7, 72.2, 106.5", \ + "78.3, 78.3, 78.3, 98.5, 135.8", \ + "124.7, 124.7, 124.7, 146.9, 187.9"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("472.2, 472.2, 472.2, 569.4, 763.9", \ + "558.9, 558.9, 558.9, 656.2, 850.6", \ + "732.3, 732.3, 732.3, 829.6, 1024.0", \ + "1079.2, 1079.2, 1079.2, 1176.4, 1370.8", \ + "1772.8, 1772.8, 1772.8, 1870.0, 2064.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("288.8, 288.8, 288.8, 386.1, 580.5", \ + "344.9, 344.9, 344.9, 442.1, 636.6", \ + "457.0, 457.0, 457.0, 554.2, 748.6", \ + "681.1, 681.1, 681.1, 778.3, 972.8", \ + "1129.4, 1129.4, 1129.4, 1226.6, 1421.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("422.4, 422.4, 422.4, 519.7, 714.1", \ + "487.1, 487.1, 487.1, 584.3, 778.7", \ + "616.3, 616.3, 616.3, 713.5, 908.0", \ + "874.8, 874.8, 874.8, 972.0, 1166.5", \ + "1391.7, 1391.7, 1391.7, 1489.0, 1683.4"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("252.3, 252.3, 252.3, 349.5, 544.0", \ + "312.8, 312.8, 312.8, 410.0, 604.4", \ + "433.7, 433.7, 433.7, 530.9, 725.3", \ + "675.5, 675.5, 675.5, 772.7, 967.2", \ + "1159.1, 1159.1, 1159.1, 1256.4, 1450.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("397.3, 397.3, 397.3, 494.5, 689.0", \ + "478.9, 478.9, 478.9, 576.1, 770.6", \ + "642.0, 642.0, 642.0, 739.2, 933.7", \ + "968.2, 968.2, 968.2, 1065.4, 1259.9", \ + "1620.7, 1620.7, 1620.7, 1717.9, 1912.4"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("261.9, 261.9, 261.9, 359.2, 553.6", \ + "290.7, 290.7, 290.7, 387.9, 582.4", \ + "348.3, 348.3, 348.3, 445.5, 639.9", \ + "463.3, 463.3, 463.3, 560.6, 755.0", \ + "693.5, 693.5, 693.5, 790.7, 985.2"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__21) { + values ("352.8, 352.8, 352.8, 450.1, 644.5", \ + "417.6, 417.6, 417.6, 514.8, 709.3", \ + "547.1, 547.1, 547.1, 644.3, 838.8", \ + "806.2, 806.2, 806.2, 903.4, 1097.8", \ + "1324.2, 1324.2, 1324.2, 1421.5, 1615.9"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("224.5, 224.5, 224.5, 321.7, 516.2", \ + "256.8, 256.8, 256.8, 354.0, 548.5", \ + "321.4, 321.4, 321.4, 418.6, 613.1", \ + "450.6, 450.6, 450.6, 547.8, 742.2", \ + "708.9, 708.9, 708.9, 806.2, 1000.6"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__21) { + values ("303.4, 303.4, 303.4, 400.6, 595.0", \ + "377.8, 377.8, 377.8, 475.0, 669.5", \ + "526.6, 526.6, 526.6, 623.8, 818.3", \ + "824.3, 824.3, 824.3, 921.5, 1116.0", \ + "1419.6, 1419.6, 1419.6, 1516.8, 1711.3"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("209.6, 209.6, 209.6, 306.8, 501.3", \ + "227.2, 227.2, 227.2, 324.5, 518.9", \ + "262.6, 262.6, 262.6, 359.8, 554.2", \ + "333.2, 333.2, 333.2, 430.4, 624.9", \ + "474.5, 474.5, 474.5, 571.7, 766.2"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__21) { + values ("262.2, 262.2, 262.2, 359.4, 553.8", \ + "323.1, 323.1, 323.1, 420.3, 614.8", \ + "444.9, 444.9, 444.9, 542.1, 736.6", \ + "688.6, 688.6, 688.6, 785.8, 980.2", \ + "1175.9, 1175.9, 1175.9, 1273.1, 1467.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("171.5, 171.5, 171.5, 268.7, 463.2", \ + "192.1, 192.1, 192.1, 289.3, 483.7", \ + "233.2, 233.2, 233.2, 330.4, 524.8", \ + "315.4, 315.4, 315.4, 412.6, 607.1", \ + "479.8, 479.8, 479.8, 577.1, 771.5"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__21) { + values ("154.8, 154.8, 154.8, 252.0, 446.5", \ + "211.6, 211.6, 211.6, 308.9, 503.3", \ + "325.4, 325.4, 325.4, 422.6, 617.1", \ + "552.9, 552.9, 552.9, 650.1, 844.5", \ + "1007.8, 1007.8, 1007.8, 1105.0, 1299.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("110.8, 110.8, 110.8, 208.0, 402.5", \ + "125.0, 125.0, 125.0, 222.2, 416.7", \ + "153.5, 153.5, 153.5, 250.7, 445.2", \ + "210.4, 210.4, 210.4, 307.6, 502.1", \ + "324.3, 324.3, 324.3, 421.5, 616.0"); + } + } + internal_power (energy_neg_nq_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__21) { + values ("193.5, 193.5, 193.5, 290.7, 485.2", \ + "261.4, 261.4, 261.4, 358.6, 553.0", \ + "397.1, 397.1, 397.1, 494.3, 688.8", \ + "668.6, 668.6, 668.6, 765.8, 960.2", \ + "1211.5, 1211.5, 1211.5, 1308.8, 1503.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("149.5, 149.5, 149.5, 246.7, 441.2", \ + "161.4, 161.4, 161.4, 258.7, 453.1", \ + "185.4, 185.4, 185.4, 282.6, 477.1", \ + "233.3, 233.3, 233.3, 330.5, 524.9", \ + "329.0, 329.0, 329.0, 426.2, 620.7"); + } + } + } + } + + cell (noa2a2a2a24_x4) { + area : 0.0 ; + cell_leakage_power : 5.5 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5) & (i6 ^ i7))" ; + value : 5.5 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5 & (i6 ^ i7))" ; + value : 6.1 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & !((i4 & i5)) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & !((i4 & i5)) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (i2 & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))" ; + value : 6.3 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i2) & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i1) & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))) | (i2 & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 5.8 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))) | (!(i1) & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!((i2 & i3)) & i4 & i5 & !(i6) & !(i7)))))) | (!(i0) & ((i1 & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!((i2 & i3)) & i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))" ; + value : 5.3 ; + } + leakage_power () { + when : "((i0 & i1 & ((!(i2) & ((!(i3) & ((!(i4) & (!(i5) | !(i6) | !(i7))) | (!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!(i3) & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!(i4) & !(i5) & !(i6) & !(i7)))) | (i2 & i3 & !(i4) & !(i5) & !(i6) & !(i7)))" ; + value : 5.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i1) & (i2 ^ i3) & (i4 ^ i5) & i6 & i7))))" ; + value : 6.8 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & !(i2) & !(i3) & i4 & i5 & i6 & i7) | (!(i1) & ((i2 & !(i3) & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))))" ; + value : 6.4 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & !(i3) & i4 & i5 & i6 & i7))) | (i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i0) & ((!(i1) & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))))" ; + value : 5.4 ; + } + leakage_power () { + when : "((!((i0 | i1)) & ((!((i2 | i3)) & i6 & i7) | (i4 & i5 & i6 & i7))) | (i2 & i3 & i4 & i5 & i6 & i7))" ; + value : 7.3 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !((i2 & i3)) & !((i4 & i5)) & (!(i6) | !(i7)))" ; + value : 0.26 ; + } + pin (i7) { + direction : input ; + capacitance : 3.42 ; + } + pin (i6) { + direction : input ; + capacitance : 3.42 ; + } + pin (i5) { + direction : input ; + capacitance : 3.42 ; + } + pin (i4) { + direction : input ; + capacitance : 3.44 ; + } + pin (i3) { + direction : input ; + capacitance : 3.42 ; + } + pin (i2) { + direction : input ; + capacitance : 3.36 ; + } + pin (i1) { + direction : input ; + capacitance : 3.63 ; + } + pin (i0) { + direction : input ; + capacitance : 3.55 ; + } + pin (nq) { + function : "((!(i6) & ((!(i5) & ((!(i3) & (!(i0) | !(i1))) | (!((i0 & i1)) & !(i2)))) | (!(i3) & !((i0 & i1)) & !(i4)) | (!((i0 & i1)) & !(i2) & !(i4)))) | (!(i5) & ((!(i3) & !((i0 & i1)) & !(i7)) | (!((i0 & i1)) & !(i2) & !(i7)))) | (!(i3) & !((i0 & i1)) & !(i4) & !(i7)) | (!((i0 & i1)) & !(i2) & !(i4) & !(i7)))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("369.8, 369.8, 369.8, 376.0, 387.9", \ + "397.0, 397.0, 397.0, 403.2, 415.3", \ + "443.6, 443.6, 443.6, 449.9, 462.1", \ + "533.4, 533.4, 533.4, 539.8, 552.2", \ + "711.9, 711.9, 711.9, 718.1, 730.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("127.6, 127.6, 127.6, 135.3, 150.7", \ + "142.8, 142.8, 142.8, 150.5, 165.9", \ + "171.0, 171.0, 171.0, 178.6, 194.0", \ + "226.1, 226.1, 226.1, 233.7, 249.0", \ + "335.0, 335.0, 335.0, 342.8, 358.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("119.5, 119.5, 119.5, 125.0, 135.0", \ + "125.1, 125.1, 125.1, 130.7, 140.7", \ + "130.0, 130.0, 130.0, 135.8, 145.8", \ + "131.4, 131.4, 131.4, 137.3, 147.8", \ + "124.3, 124.3, 124.3, 130.3, 141.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("40.3, 40.3, 40.3, 43.8, 50.7", \ + "43.3, 43.3, 43.3, 46.8, 53.8", \ + "49.1, 49.1, 49.1, 52.7, 59.8", \ + "60.4, 60.4, 60.4, 64.0, 70.9", \ + "82.1, 82.1, 82.1, 85.7, 92.7"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("346.9, 346.9, 346.9, 353.1, 364.9", \ + "362.7, 362.7, 362.7, 369.0, 380.9", \ + "388.3, 388.3, 388.3, 394.6, 406.7", \ + "436.3, 436.3, 436.3, 442.6, 454.9", \ + "532.3, 532.3, 532.3, 538.6, 551.1"); + } + rise_transition (inslew_load_5x5__1) { + values ("120.3, 120.3, 120.3, 128.0, 143.3", \ + "131.8, 131.8, 131.8, 139.5, 154.9", \ + "153.3, 153.3, 153.3, 161.0, 176.4", \ + "195.0, 195.0, 195.0, 202.6, 218.0", \ + "277.5, 277.5, 277.5, 285.1, 300.4"); + } + cell_fall (inslew_load_5x5__1) { + values ("121.9, 121.9, 121.9, 127.4, 137.3", \ + "134.1, 134.1, 134.1, 139.7, 149.6", \ + "149.2, 149.2, 149.2, 155.0, 165.0", \ + "168.6, 168.6, 168.6, 174.5, 185.2", \ + "196.6, 196.6, 196.6, 202.6, 214.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("39.5, 39.5, 39.5, 43.1, 50.0", \ + "43.4, 43.4, 43.4, 46.9, 53.9", \ + "50.5, 50.5, 50.5, 54.1, 61.1", \ + "63.9, 63.9, 63.9, 67.5, 74.4", \ + "89.6, 89.6, 89.6, 93.2, 100.3"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("326.4, 326.4, 326.4, 332.6, 344.3", \ + "358.8, 358.8, 358.8, 365.1, 377.0", \ + "412.5, 412.5, 412.5, 418.8, 431.0", \ + "514.1, 514.1, 514.1, 520.4, 532.8", \ + "714.2, 714.2, 714.2, 720.4, 733.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("113.0, 113.0, 113.0, 120.7, 136.0", \ + "128.3, 128.3, 128.3, 136.0, 151.3", \ + "155.4, 155.4, 155.4, 163.0, 178.5", \ + "207.9, 207.9, 207.9, 215.5, 230.8", \ + "311.6, 311.6, 311.6, 319.4, 334.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("116.5, 116.5, 116.5, 122.0, 131.9", \ + "117.2, 117.2, 117.2, 122.8, 132.7", \ + "111.7, 111.7, 111.7, 117.4, 127.3", \ + "89.1, 89.1, 89.1, 95.0, 105.1", \ + "30.2, 30.2, 30.2, 36.1, 47.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("39.6, 39.6, 39.6, 43.2, 50.1", \ + "41.8, 41.8, 41.8, 45.4, 52.3", \ + "46.0, 46.0, 46.0, 49.6, 56.7", \ + "53.8, 53.8, 53.8, 57.3, 64.4", \ + "68.3, 68.3, 68.3, 71.9, 78.9"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("306.5, 306.5, 306.5, 312.7, 324.3", \ + "329.8, 329.8, 329.8, 336.1, 347.8", \ + "367.1, 367.1, 367.1, 373.4, 385.4", \ + "436.4, 436.4, 436.4, 442.8, 455.0", \ + "572.5, 572.5, 572.5, 578.9, 591.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("106.5, 106.5, 106.5, 114.3, 129.5", \ + "118.8, 118.8, 118.8, 126.6, 141.9", \ + "140.8, 140.8, 140.8, 148.5, 163.9", \ + "183.0, 183.0, 183.0, 190.6, 206.0", \ + "266.8, 266.8, 266.8, 274.5, 289.7"); + } + cell_fall (inslew_load_5x5__1) { + values ("118.8, 118.8, 118.8, 124.3, 134.2", \ + "125.4, 125.4, 125.4, 131.0, 140.9", \ + "127.7, 127.7, 127.7, 133.4, 143.3", \ + "118.8, 118.8, 118.8, 124.7, 135.0", \ + "86.0, 86.0, 86.0, 92.0, 103.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("38.9, 38.9, 38.9, 42.5, 49.3", \ + "41.9, 41.9, 41.9, 45.4, 52.4", \ + "47.1, 47.1, 47.1, 50.6, 57.8", \ + "56.6, 56.6, 56.6, 60.2, 67.2", \ + "74.4, 74.4, 74.4, 78.0, 85.0"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("271.8, 271.8, 271.8, 278.0, 289.4", \ + "307.0, 307.0, 307.0, 313.2, 324.8", \ + "363.5, 363.5, 363.5, 369.8, 381.8", \ + "471.1, 471.1, 471.1, 477.4, 489.7", \ + "683.2, 683.2, 683.2, 689.5, 702.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("95.4, 95.4, 95.4, 103.2, 118.4", \ + "110.7, 110.7, 110.7, 118.4, 133.7", \ + "136.2, 136.2, 136.2, 143.9, 159.3", \ + "185.1, 185.1, 185.1, 192.7, 208.1", \ + "283.2, 283.2, 283.2, 290.9, 306.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("107.6, 107.6, 107.6, 113.0, 123.0", \ + "105.7, 105.7, 105.7, 111.1, 121.1", \ + "94.1, 94.1, 94.1, 99.7, 109.7", \ + "58.9, 58.9, 58.9, 64.6, 74.7", \ + "-27.3, -27.3, -27.3, -21.4, -10.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("37.9, 37.9, 37.9, 41.4, 48.3", \ + "39.8, 39.8, 39.8, 43.3, 50.2", \ + "43.2, 43.2, 43.2, 46.7, 53.7", \ + "49.3, 49.3, 49.3, 52.9, 60.0", \ + "60.6, 60.6, 60.6, 64.3, 71.2"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("253.0, 253.0, 253.0, 259.1, 270.5", \ + "281.0, 281.0, 281.0, 287.2, 298.7", \ + "324.5, 324.5, 324.5, 330.7, 342.5", \ + "406.5, 406.5, 406.5, 412.8, 425.0", \ + "566.6, 566.6, 566.6, 573.0, 585.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("89.3, 89.3, 89.3, 97.1, 112.3", \ + "102.2, 102.2, 102.2, 110.0, 125.3", \ + "123.6, 123.6, 123.6, 131.3, 146.7", \ + "164.8, 164.8, 164.8, 172.4, 187.8", \ + "247.4, 247.4, 247.4, 255.0, 270.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("109.2, 109.2, 109.2, 114.5, 124.5", \ + "112.0, 112.0, 112.0, 117.5, 127.4", \ + "106.5, 106.5, 106.5, 112.2, 122.1", \ + "81.4, 81.4, 81.4, 87.2, 97.3", \ + "15.2, 15.2, 15.2, 21.1, 31.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("37.1, 37.1, 37.1, 40.7, 47.5", \ + "39.6, 39.6, 39.6, 43.2, 50.1", \ + "43.9, 43.9, 43.9, 47.5, 54.5", \ + "51.5, 51.5, 51.5, 55.1, 62.2", \ + "65.4, 65.4, 65.4, 69.0, 76.0"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("175.3, 175.3, 175.3, 181.3, 192.4", \ + "207.1, 207.1, 207.1, 213.1, 224.5", \ + "260.9, 260.9, 260.9, 267.1, 278.6", \ + "344.4, 344.4, 344.4, 350.6, 362.6", \ + "524.0, 524.0, 524.0, 530.4, 542.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("64.2, 64.2, 64.2, 71.9, 86.9", \ + "78.5, 78.5, 78.5, 86.3, 101.4", \ + "101.9, 101.9, 101.9, 109.7, 125.0", \ + "140.6, 140.6, 140.6, 148.3, 163.6", \ + "222.5, 222.5, 222.5, 230.1, 245.4"); + } + cell_fall (inslew_load_5x5__1) { + values ("97.2, 97.2, 97.2, 102.5, 112.4", \ + "96.7, 96.7, 96.7, 102.0, 112.0", \ + "84.9, 84.9, 84.9, 90.4, 100.4", \ + "48.3, 48.3, 48.3, 54.0, 63.9", \ + "-41.1, -41.1, -41.1, -35.2, -24.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("34.9, 34.9, 34.9, 38.5, 45.2", \ + "37.2, 37.2, 37.2, 40.7, 47.5", \ + "40.9, 40.9, 40.9, 44.4, 51.3", \ + "47.2, 47.2, 47.2, 50.8, 57.9", \ + "58.6, 58.6, 58.6, 62.2, 69.2"); + } + } + timing (maxd_nq_i7_negative_unate) { + related_pin : "i7" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("193.6, 193.6, 193.6, 199.5, 210.8", \ + "231.6, 231.6, 231.6, 237.7, 249.1", \ + "296.2, 296.2, 296.2, 302.4, 314.1", \ + "401.7, 401.7, 401.7, 408.0, 420.2", \ + "625.3, 625.3, 625.3, 631.7, 644.1"); + } + rise_transition (inslew_load_5x5__1) { + values ("70.1, 70.1, 70.1, 77.8, 92.9", \ + "86.3, 86.3, 86.3, 94.1, 109.3", \ + "113.0, 113.0, 113.0, 120.7, 136.0", \ + "157.8, 157.8, 157.8, 165.5, 180.9", \ + "252.1, 252.1, 252.1, 259.7, 275.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("96.6, 96.6, 96.6, 102.0, 111.9", \ + "92.5, 92.5, 92.5, 97.9, 107.9", \ + "76.5, 76.5, 76.5, 82.0, 92.0", \ + "32.3, 32.3, 32.3, 38.0, 47.9", \ + "-71.9, -71.9, -71.9, -66.0, -55.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("35.8, 35.8, 35.8, 39.3, 46.1", \ + "37.5, 37.5, 37.5, 41.0, 47.9", \ + "40.5, 40.5, 40.5, 44.0, 50.9", \ + "45.7, 45.7, 45.7, 49.3, 56.4", \ + "55.0, 55.0, 55.0, 58.6, 65.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1457.9, 1457.9, 1457.9, 1517.5, 1636.7", \ + "1627.8, 1627.8, 1627.8, 1687.4, 1806.6", \ + "1949.3, 1949.3, 1949.3, 2008.9, 2128.1", \ + "2583.2, 2583.2, 2583.2, 2642.8, 2762.0", \ + "3843.4, 3843.4, 3843.4, 3903.0, 4022.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("739.1, 739.1, 739.1, 798.7, 917.9", \ + "799.5, 799.5, 799.5, 859.1, 978.3", \ + "919.0, 919.0, 919.0, 978.6, 1097.8", \ + "1153.4, 1153.4, 1153.4, 1213.0, 1332.2", \ + "1616.1, 1616.1, 1616.1, 1675.7, 1794.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1371.1, 1371.1, 1371.1, 1430.7, 1549.9", \ + "1499.8, 1499.8, 1499.8, 1559.4, 1678.5", \ + "1744.2, 1744.2, 1744.2, 1803.8, 1923.0", \ + "2223.1, 2223.1, 2223.1, 2282.7, 2401.9", \ + "3174.4, 3174.4, 3174.4, 3234.0, 3353.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("711.0, 711.0, 711.0, 770.6, 889.8", \ + "782.9, 782.9, 782.9, 842.5, 961.7", \ + "920.4, 920.4, 920.4, 980.0, 1099.2", \ + "1187.1, 1187.1, 1187.1, 1246.7, 1365.9", \ + "1712.3, 1712.3, 1712.3, 1771.9, 1891.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1293.7, 1293.7, 1293.7, 1353.3, 1472.5", \ + "1461.2, 1461.2, 1461.2, 1520.8, 1640.0", \ + "1768.2, 1768.2, 1768.2, 1827.8, 1947.0", \ + "2368.4, 2368.4, 2368.4, 2428.0, 2547.2", \ + "3561.7, 3561.7, 3561.7, 3621.3, 3740.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("719.4, 719.4, 719.4, 779.0, 898.2", \ + "757.7, 757.7, 757.7, 817.3, 936.5", \ + "832.1, 832.1, 832.1, 891.7, 1010.9", \ + "974.7, 974.7, 974.7, 1034.3, 1153.5", \ + "1250.5, 1250.5, 1250.5, 1310.1, 1429.3"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1217.1, 1217.1, 1217.1, 1276.7, 1395.9", \ + "1351.8, 1351.8, 1351.8, 1411.4, 1530.6", \ + "1599.1, 1599.1, 1599.1, 1658.7, 1777.9", \ + "2080.2, 2080.2, 2080.2, 2139.8, 2259.0", \ + "3040.1, 3040.1, 3040.1, 3099.7, 3218.9"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("691.7, 691.7, 691.7, 751.3, 870.5", \ + "739.8, 739.8, 739.8, 799.4, 918.6", \ + "829.5, 829.5, 829.5, 889.1, 1008.3", \ + "998.8, 998.8, 998.8, 1058.4, 1177.6", \ + "1326.0, 1326.0, 1326.0, 1385.6, 1504.8"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1096.4, 1096.4, 1096.4, 1156.0, 1275.2", \ + "1259.7, 1259.7, 1259.7, 1319.3, 1438.5", \ + "1545.2, 1545.2, 1545.2, 1604.8, 1724.0", \ + "2100.7, 2100.7, 2100.7, 2160.3, 2279.5", \ + "3216.0, 3216.0, 3216.0, 3275.6, 3394.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("671.7, 671.7, 671.7, 731.3, 850.5", \ + "700.8, 700.8, 700.8, 760.4, 879.5", \ + "755.9, 755.9, 755.9, 815.5, 934.7", \ + "859.0, 859.0, 859.0, 918.6, 1037.8", \ + "1054.4, 1054.4, 1054.4, 1114.0, 1233.2"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1024.8, 1024.8, 1024.8, 1084.4, 1203.6", \ + "1162.4, 1162.4, 1162.4, 1222.0, 1341.2", \ + "1400.4, 1400.4, 1400.4, 1460.0, 1579.2", \ + "1865.0, 1865.0, 1865.0, 1924.5, 2043.7", \ + "2799.0, 2799.0, 2799.0, 2858.6, 2977.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("642.9, 642.9, 642.9, 702.5, 821.7", \ + "680.3, 680.3, 680.3, 739.9, 859.1", \ + "747.9, 747.9, 747.9, 807.5, 926.7", \ + "872.3, 872.3, 872.3, 931.9, 1051.1", \ + "1108.0, 1108.0, 1108.0, 1167.6, 1286.8"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__1) { + values ("757.6, 757.6, 757.6, 817.2, 936.4", \ + "902.7, 902.7, 902.7, 962.3, 1081.5", \ + "1152.3, 1152.3, 1152.3, 1211.9, 1331.1", \ + "1586.4, 1586.4, 1586.4, 1646.0, 1765.2", \ + "2497.2, 2497.2, 2497.2, 2556.8, 2676.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("586.4, 586.4, 586.4, 646.0, 765.2", \ + "617.6, 617.6, 617.6, 677.2, 796.4", \ + "671.9, 671.9, 671.9, 731.5, 850.7", \ + "770.1, 770.1, 770.1, 829.7, 948.9", \ + "953.5, 953.5, 953.5, 1013.1, 1132.3"); + } + } + internal_power (energy_neg_nq_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__1) { + values ("825.4, 825.4, 825.4, 885.0, 1004.2", \ + "991.8, 991.8, 991.8, 1051.4, 1170.6", \ + "1279.3, 1279.3, 1279.3, 1338.9, 1458.0", \ + "1786.1, 1786.1, 1786.1, 1845.7, 1964.9", \ + "2841.4, 2841.4, 2841.4, 2901.0, 3020.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("616.1, 616.1, 616.1, 675.7, 794.9", \ + "640.5, 640.5, 640.5, 700.1, 819.3", \ + "685.2, 685.2, 685.2, 744.8, 864.0", \ + "766.7, 766.7, 766.7, 826.3, 945.5", \ + "917.5, 917.5, 917.5, 977.1, 1096.3"); + } + } + } + } + + cell (noa2ao222_x1) { + area : 0.0 ; + cell_leakage_power : 2.1 ; + leakage_power () { + when : "(i0 & i1 & ((i2 & (i3 ^ i4)) | (!(i2) & i3 & i4)))" ; + value : 2.9 ; + } + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & !(i4))" ; + value : 1.8 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & i0)" ; + value : 2.8 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 1.7 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & !(i1) & i0)" ; + value : 0.00015 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & i0)" ; + value : 0.00013 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3 & i4)" ; + value : 5.6 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & i1 & !(i0))" ; + value : 0.00014 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & i4)" ; + value : 5.1 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & i3 & i4)" ; + value : 3.5 ; + } + leakage_power () { + when : "(!(i0) & i1 & (i2 ^ i3) & !(i4))" ; + value : 8.9e-05 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & !(i0))" ; + value : 0.00012 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & !(i0))" ; + value : 4.1e-05 ; + } + leakage_power () { + when : "(i4 & i3 & i2 & !(i1) & !(i0))" ; + value : 7.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & !(i4)) | (!(i0) & !(i1) & i2 & i3 & !(i4)))" ; + value : 9.8e-05 ; + } + leakage_power () { + when : "(i4 & !(i3) & i2 & !(i1) & !(i0))" ; + value : 7.3 ; + } + leakage_power () { + when : "((i0 & i1 & i2 & i3 & i4) | (!(i0) & !(i1) & !(i2) & i3 & i4))" ; + value : 4 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4)) | (!(i0) & !(i1) & (i2 ^ i3) & !(i4)))" ; + value : 5e-05 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 7.9e-05 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 2.5e-06 ; + } + pin (i4) { + direction : input ; + capacitance : 3.77 ; + } + pin (i3) { + direction : input ; + capacitance : 5.07 ; + } + pin (i2) { + direction : input ; + capacitance : 5.15 ; + } + pin (i1) { + direction : input ; + capacitance : 3.96 ; + } + pin (i0) { + direction : input ; + capacitance : 3.93 ; + } + pin (nq) { + function : "(((((!(i2) & !(i3)) & !(i1)) | ((!(i2) & !(i3)) & !(i0))) | (!(i4) & !(i1))) | (!(i4) & !(i0)))" ; + direction : output ; + capacitance : 4.14 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("119.9, 119.9, 119.9, 144.5, 193.9", \ + "131.4, 131.4, 131.4, 156.3, 205.9", \ + "152.3, 152.3, 152.3, 177.3, 227.3", \ + "193.5, 193.5, 193.5, 218.7, 269.0", \ + "274.1, 274.1, 274.1, 299.7, 351.8"); + } + rise_transition (inslew_load_5x5__22) { + values ("219.3, 219.3, 219.3, 262.6, 349.3", \ + "266.7, 266.7, 266.7, 309.8, 396.1", \ + "357.5, 357.5, 357.5, 400.1, 486.0", \ + "538.4, 538.4, 538.4, 580.6, 665.5", \ + "901.7, 901.7, 901.7, 943.4, 1027.1"); + } + cell_fall (inslew_load_5x5__22) { + values ("39.3, 39.3, 39.3, 50.5, 72.3", \ + "40.8, 40.8, 40.8, 53.1, 76.6", \ + "39.9, 39.9, 39.9, 53.8, 79.9", \ + "33.9, 33.9, 33.9, 49.3, 78.6", \ + "18.5, 18.5, 18.5, 35.2, 67.2"); + } + fall_transition (inslew_load_5x5__22) { + values ("56.8, 56.8, 56.8, 71.4, 100.8", \ + "73.5, 73.5, 73.5, 88.1, 117.2", \ + "106.3, 106.3, 106.3, 121.1, 150.2", \ + "170.7, 170.7, 170.7, 185.8, 215.6", \ + "298.5, 298.5, 298.5, 313.9, 344.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("107.0, 107.0, 107.0, 131.7, 181.0", \ + "111.3, 111.3, 111.3, 136.3, 186.1", \ + "118.4, 118.4, 118.4, 143.7, 193.9", \ + "131.4, 131.4, 131.4, 157.1, 208.6", \ + "156.3, 156.3, 156.3, 182.6, 234.8"); + } + rise_transition (inslew_load_5x5__22) { + values ("197.0, 197.0, 197.0, 240.1, 326.8", \ + "232.4, 232.4, 232.4, 275.4, 361.6", \ + "300.6, 300.6, 300.6, 343.2, 428.6", \ + "437.9, 437.9, 437.9, 479.7, 563.8", \ + "714.7, 714.7, 714.7, 755.9, 838.6"); + } + cell_fall (inslew_load_5x5__22) { + values ("39.7, 39.7, 39.7, 51.8, 74.5", \ + "46.2, 46.2, 46.2, 59.9, 85.2", \ + "54.2, 54.2, 54.2, 69.7, 98.6", \ + "65.7, 65.7, 65.7, 83.0, 115.6", \ + "85.7, 85.7, 85.7, 104.3, 139.9"); + } + fall_transition (inslew_load_5x5__22) { + values ("51.3, 51.3, 51.3, 66.0, 95.5", \ + "71.2, 71.2, 71.2, 86.1, 115.5", \ + "109.0, 109.0, 109.0, 124.4, 154.5", \ + "183.0, 183.0, 183.0, 198.9, 230.0", \ + "329.7, 329.7, 329.7, 345.9, 377.9"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("55.1, 55.1, 55.1, 81.0, 131.4", \ + "72.4, 72.4, 72.4, 99.2, 150.7", \ + "108.2, 108.2, 108.2, 135.6, 188.7", \ + "176.9, 176.9, 176.9, 204.9, 259.6", \ + "311.3, 311.3, 311.3, 339.7, 395.8"); + } + rise_transition (inslew_load_5x5__22) { + values ("101.0, 101.0, 101.0, 144.5, 232.5", \ + "150.9, 150.9, 150.9, 194.1, 281.4", \ + "250.5, 250.5, 250.5, 294.2, 379.9", \ + "446.4, 446.4, 446.4, 488.9, 576.1", \ + "834.8, 834.8, 834.8, 877.2, 962.2"); + } + cell_fall (inslew_load_5x5__22) { + values ("26.0, 26.0, 26.0, 38.2, 60.9", \ + "20.5, 20.5, 20.5, 34.6, 59.8", \ + "5.3, 5.3, 5.3, 21.8, 51.2", \ + "-29.9, -29.9, -29.9, -10.8, 23.7", \ + "-104.6, -104.6, -104.6, -83.2, -43.6"); + } + fall_transition (inslew_load_5x5__22) { + values ("39.1, 39.1, 39.1, 53.8, 83.0", \ + "50.4, 50.4, 50.4, 65.3, 94.4", \ + "71.5, 71.5, 71.5, 87.0, 117.0", \ + "112.1, 112.1, 112.1, 128.4, 159.8", \ + "191.8, 191.8, 191.8, 208.9, 241.9"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("89.2, 89.2, 89.2, 114.2, 163.9", \ + "104.8, 104.8, 104.8, 130.1, 180.3", \ + "132.1, 132.1, 132.1, 158.0, 208.8", \ + "185.9, 185.9, 185.9, 212.0, 263.7", \ + "291.4, 291.4, 291.4, 317.9, 370.5"); + } + rise_transition (inslew_load_5x5__22) { + values ("162.2, 162.2, 162.2, 205.5, 292.6", \ + "213.8, 213.8, 213.8, 256.9, 343.5", \ + "310.0, 310.0, 310.0, 352.5, 438.2", \ + "502.1, 502.1, 502.1, 544.0, 628.3", \ + "885.3, 885.3, 885.3, 926.8, 1010.0"); + } + cell_fall (inslew_load_5x5__22) { + values ("35.5, 35.5, 35.5, 47.0, 69.1", \ + "33.8, 33.8, 33.8, 46.7, 70.8", \ + "26.1, 26.1, 26.1, 40.9, 68.2", \ + "5.8, 5.8, 5.8, 22.6, 53.9", \ + "-38.7, -38.7, -38.7, -20.3, 14.7"); + } + fall_transition (inslew_load_5x5__22) { + values ("49.8, 49.8, 49.8, 64.5, 93.8", \ + "64.0, 64.0, 64.0, 78.7, 107.9", \ + "90.8, 90.8, 90.8, 105.9, 135.3", \ + "143.1, 143.1, 143.1, 158.6, 189.0", \ + "246.1, 246.1, 246.1, 262.1, 293.6"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("34.4, 34.4, 34.4, 57.1, 99.9", \ + "46.1, 46.1, 46.1, 69.5, 114.4", \ + "66.4, 66.4, 66.4, 92.1, 139.5", \ + "104.4, 104.4, 104.4, 131.5, 182.8", \ + "178.5, 178.5, 178.5, 206.5, 260.7"); + } + rise_transition (inslew_load_5x5__22) { + values ("68.4, 68.4, 68.4, 106.7, 184.0", \ + "107.8, 107.8, 107.8, 144.6, 221.1", \ + "183.1, 183.1, 183.1, 221.3, 296.2", \ + "330.9, 330.9, 330.9, 369.7, 446.2", \ + "625.1, 625.1, 625.1, 664.1, 741.6"); + } + cell_fall (inslew_load_5x5__22) { + values ("18.1, 18.1, 18.1, 32.4, 56.9", \ + "15.3, 15.3, 15.3, 32.3, 60.9", \ + "6.3, 6.3, 6.3, 26.2, 60.2", \ + "-14.5, -14.5, -14.5, 7.8, 47.5", \ + "-58.1, -58.1, -58.1, -33.9, 10.6"); + } + fall_transition (inslew_load_5x5__22) { + values ("28.7, 28.7, 28.7, 43.8, 73.1", \ + "42.1, 42.1, 42.1, 57.9, 87.8", \ + "67.1, 67.1, 67.1, 83.9, 115.4", \ + "116.1, 116.1, 116.1, 133.7, 167.1", \ + "213.2, 213.2, 213.2, 231.4, 266.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__22) { + values ("262.2, 262.2, 262.2, 313.9, 417.4", \ + "313.7, 313.7, 313.7, 365.4, 468.9", \ + "416.6, 416.6, 416.6, 468.3, 571.8", \ + "622.5, 622.5, 622.5, 674.2, 777.7", \ + "1034.2, 1034.2, 1034.2, 1086.0, 1189.4"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("180.7, 180.7, 180.7, 232.4, 335.9", \ + "217.4, 217.4, 217.4, 269.1, 372.6", \ + "290.8, 290.8, 290.8, 342.5, 446.0", \ + "437.5, 437.5, 437.5, 489.3, 592.7", \ + "731.1, 731.1, 731.1, 782.8, 886.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__22) { + values ("233.1, 233.1, 233.1, 284.8, 388.3", \ + "270.9, 270.9, 270.9, 322.6, 426.1", \ + "346.4, 346.4, 346.4, 398.2, 501.6", \ + "497.5, 497.5, 497.5, 549.2, 652.7", \ + "799.7, 799.7, 799.7, 851.4, 954.9"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("157.8, 157.8, 157.8, 209.5, 313.0", \ + "197.0, 197.0, 197.0, 248.7, 352.2", \ + "275.3, 275.3, 275.3, 327.0, 430.5", \ + "432.0, 432.0, 432.0, 483.7, 587.2", \ + "745.3, 745.3, 745.3, 797.1, 900.5"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__22) { + values ("126.0, 126.0, 126.0, 177.8, 281.2", \ + "176.2, 176.2, 176.2, 227.9, 331.4", \ + "276.4, 276.4, 276.4, 328.1, 431.6", \ + "476.9, 476.9, 476.9, 528.6, 632.1", \ + "877.9, 877.9, 877.9, 929.6, 1033.1"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("114.0, 114.0, 114.0, 165.8, 269.2", \ + "132.3, 132.3, 132.3, 184.0, 287.4", \ + "168.7, 168.7, 168.7, 220.4, 323.9", \ + "241.6, 241.6, 241.6, 293.4, 396.8", \ + "387.5, 387.5, 387.5, 439.2, 542.7"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__22) { + values ("195.6, 195.6, 195.6, 247.4, 350.8", \ + "248.0, 248.0, 248.0, 299.7, 403.1", \ + "352.6, 352.6, 352.6, 404.3, 507.8", \ + "561.9, 561.9, 561.9, 613.6, 717.1", \ + "980.4, 980.4, 980.4, 1032.1, 1135.6"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("154.9, 154.9, 154.9, 206.7, 310.1", \ + "181.8, 181.8, 181.8, 233.5, 337.0", \ + "235.4, 235.4, 235.4, 287.2, 390.6", \ + "342.8, 342.8, 342.8, 394.5, 498.0", \ + "557.5, 557.5, 557.5, 609.3, 712.7"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__22) { + values ("88.2, 88.2, 88.2, 140.0, 243.4", \ + "126.6, 126.6, 126.6, 178.4, 281.8", \ + "203.4, 203.4, 203.4, 255.2, 358.6", \ + "357.0, 357.0, 357.0, 408.7, 512.2", \ + "664.2, 664.2, 664.2, 715.9, 819.4"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("74.8, 74.8, 74.8, 126.6, 230.0", \ + "96.0, 96.0, 96.0, 147.8, 251.2", \ + "138.5, 138.5, 138.5, 190.2, 293.6", \ + "223.3, 223.3, 223.3, 275.0, 378.5", \ + "393.0, 393.0, 393.0, 444.7, 548.1"); + } + } + } + } + + cell (noa2ao222_x4) { + area : 0.0 ; + cell_leakage_power : 5.4 ; + leakage_power () { + when : "(i4 & i3 & i2 & i1 & i0)" ; + value : 4.2 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & i3) ^ i4))" ; + value : 4 ; + } + leakage_power () { + when : "(i0 & i1 & !((i2 & i3)) & !(i4))" ; + value : 3.7 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3 & i4)" ; + value : 6.6 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & i4)" ; + value : 6.5 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & i3 & i4)" ; + value : 4.8 ; + } + leakage_power () { + when : "(i4 & i3 & i2 & !(i1) & !(i0))" ; + value : 8.9 ; + } + leakage_power () { + when : "(i4 & !(i3) & i2 & !(i1) & !(i0))" ; + value : 9 ; + } + leakage_power () { + when : "(i4 & i3 & !(i2) & !(i1) & !(i0))" ; + value : 5.7 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!((i2 | i3)) | !(i4)))" ; + value : 0.26 ; + } + pin (i4) { + direction : input ; + capacitance : 3.34 ; + } + pin (i3) { + direction : input ; + capacitance : 4.81 ; + } + pin (i2) { + direction : input ; + capacitance : 4.95 ; + } + pin (i1) { + direction : input ; + capacitance : 3.53 ; + } + pin (i0) { + direction : input ; + capacitance : 3.50 ; + } + pin (nq) { + function : "((!(i4) & (!(i0) | !(i1))) | (!((i0 & i1)) & !(i3) & !(i2)))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("217.3, 217.3, 217.3, 223.4, 234.7", \ + "230.1, 230.1, 230.1, 236.3, 247.7", \ + "252.4, 252.4, 252.4, 258.6, 270.2", \ + "293.9, 293.9, 293.9, 300.1, 312.1", \ + "372.0, 372.0, 372.0, 378.3, 390.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("79.0, 79.0, 79.0, 86.7, 101.9", \ + "87.2, 87.2, 87.2, 95.0, 110.2", \ + "102.7, 102.7, 102.7, 110.5, 125.8", \ + "133.7, 133.7, 133.7, 141.4, 156.8", \ + "195.5, 195.5, 195.5, 203.2, 218.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("121.9, 121.9, 121.9, 127.5, 137.5", \ + "127.6, 127.6, 127.6, 133.2, 143.2", \ + "132.6, 132.6, 132.6, 138.4, 148.5", \ + "134.2, 134.2, 134.2, 140.1, 150.7", \ + "127.2, 127.2, 127.2, 133.3, 144.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("41.1, 41.1, 41.1, 44.7, 51.7", \ + "44.1, 44.1, 44.1, 47.7, 54.8", \ + "50.0, 50.0, 50.0, 53.6, 60.7", \ + "61.2, 61.2, 61.2, 64.8, 71.8", \ + "82.8, 82.8, 82.8, 86.4, 93.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("205.8, 205.8, 205.8, 211.8, 223.2", \ + "212.4, 212.4, 212.4, 218.5, 229.9", \ + "223.3, 223.3, 223.3, 229.4, 240.9", \ + "241.6, 241.6, 241.6, 247.8, 259.6", \ + "272.5, 272.5, 272.5, 278.8, 291.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("75.3, 75.3, 75.3, 83.0, 98.2", \ + "81.6, 81.6, 81.6, 89.4, 104.6", \ + "93.7, 93.7, 93.7, 101.5, 116.8", \ + "118.0, 118.0, 118.0, 125.8, 141.1", \ + "166.9, 166.9, 166.9, 174.6, 190.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("124.3, 124.3, 124.3, 129.8, 139.8", \ + "136.6, 136.6, 136.6, 142.3, 152.3", \ + "151.8, 151.8, 151.8, 157.6, 167.8", \ + "171.4, 171.4, 171.4, 177.4, 188.1", \ + "199.7, 199.7, 199.7, 205.7, 217.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("40.4, 40.4, 40.4, 44.0, 50.9", \ + "44.2, 44.2, 44.2, 47.8, 54.9", \ + "51.3, 51.3, 51.3, 54.9, 62.0", \ + "64.6, 64.6, 64.6, 68.3, 75.3", \ + "90.3, 90.3, 90.3, 93.9, 101.0"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("141.1, 141.1, 141.1, 147.1, 157.9", \ + "161.3, 161.3, 161.3, 167.2, 178.4", \ + "192.5, 192.5, 192.5, 198.6, 210.0", \ + "253.9, 253.9, 253.9, 260.1, 271.8", \ + "368.1, 368.1, 368.1, 374.5, 386.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("53.9, 53.9, 53.9, 61.6, 76.7", \ + "64.0, 64.0, 64.0, 71.6, 86.7", \ + "81.2, 81.2, 81.2, 88.9, 104.1", \ + "115.1, 115.1, 115.1, 122.8, 138.1", \ + "181.7, 181.7, 181.7, 189.3, 204.7"); + } + cell_fall (inslew_load_5x5__1) { + values ("105.7, 105.7, 105.7, 111.1, 121.1", \ + "106.4, 106.4, 106.4, 111.9, 121.9", \ + "101.2, 101.2, 101.2, 106.9, 116.9", \ + "81.8, 81.8, 81.8, 87.6, 97.8", \ + "33.0, 33.0, 33.0, 39.0, 49.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("37.5, 37.5, 37.5, 41.1, 47.9", \ + "39.9, 39.9, 39.9, 43.5, 50.4", \ + "44.4, 44.4, 44.4, 48.0, 55.1", \ + "52.8, 52.8, 52.8, 56.5, 63.5", \ + "68.8, 68.8, 68.8, 72.5, 79.5"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("180.9, 180.9, 180.9, 186.9, 198.1", \ + "195.5, 195.5, 195.5, 201.6, 212.9", \ + "219.6, 219.6, 219.6, 225.7, 237.2", \ + "265.7, 265.7, 265.7, 271.9, 283.8", \ + "351.0, 351.0, 351.0, 357.3, 369.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("67.1, 67.1, 67.1, 74.7, 89.8", \ + "76.2, 76.2, 76.2, 83.9, 99.1", \ + "92.6, 92.6, 92.6, 100.3, 115.6", \ + "125.5, 125.5, 125.5, 133.2, 148.6", \ + "190.2, 190.2, 190.2, 197.9, 213.2"); + } + cell_fall (inslew_load_5x5__1) { + values ("118.3, 118.3, 118.3, 123.8, 133.8", \ + "122.9, 122.9, 122.9, 128.5, 138.5", \ + "125.2, 125.2, 125.2, 131.0, 141.0", \ + "121.2, 121.2, 121.2, 127.1, 137.6", \ + "103.3, 103.3, 103.3, 109.3, 120.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("39.9, 39.9, 39.9, 43.4, 50.4", \ + "42.8, 42.8, 42.8, 46.4, 53.4", \ + "48.3, 48.3, 48.3, 51.9, 59.1", \ + "58.8, 58.8, 58.8, 62.4, 69.4", \ + "78.9, 78.9, 78.9, 82.5, 89.6"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("124.1, 124.1, 124.1, 130.0, 140.7", \ + "139.8, 139.8, 139.8, 145.8, 156.7", \ + "167.7, 167.7, 167.7, 173.6, 185.0", \ + "213.2, 213.2, 213.2, 219.3, 230.8", \ + "295.8, 295.8, 295.8, 302.1, 314.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("48.5, 48.5, 48.5, 56.2, 71.2", \ + "56.3, 56.3, 56.3, 63.9, 79.0", \ + "71.3, 71.3, 71.3, 79.1, 94.2", \ + "99.3, 99.3, 99.3, 107.1, 122.4", \ + "153.6, 153.6, 153.6, 161.3, 176.7"); + } + cell_fall (inslew_load_5x5__1) { + values ("96.7, 96.7, 96.7, 102.0, 112.0", \ + "100.4, 100.4, 100.4, 105.8, 115.8", \ + "98.8, 98.8, 98.8, 104.5, 114.4", \ + "85.8, 85.8, 85.8, 91.6, 101.8", \ + "49.7, 49.7, 49.7, 55.7, 66.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("35.4, 35.4, 35.4, 39.0, 45.8", \ + "38.3, 38.3, 38.3, 41.9, 48.7", \ + "43.4, 43.4, 43.4, 46.9, 54.0", \ + "52.6, 52.6, 52.6, 56.2, 63.3", \ + "70.2, 70.2, 70.2, 73.8, 80.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1039.7, 1039.7, 1039.7, 1099.3, 1218.5", \ + "1149.8, 1149.8, 1149.8, 1209.4, 1328.6", \ + "1363.7, 1363.7, 1363.7, 1423.3, 1542.5", \ + "1792.5, 1792.5, 1792.5, 1852.1, 1971.3", \ + "2651.4, 2651.4, 2651.4, 2711.0, 2830.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("756.2, 756.2, 756.2, 815.8, 935.0", \ + "816.8, 816.8, 816.8, 876.4, 995.6", \ + "936.6, 936.6, 936.6, 996.2, 1115.4", \ + "1171.2, 1171.2, 1171.2, 1230.8, 1350.0", \ + "1634.4, 1634.4, 1634.4, 1694.0, 1813.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("986.1, 986.1, 986.1, 1045.7, 1164.8", \ + "1070.2, 1070.2, 1070.2, 1129.8, 1249.0", \ + "1234.4, 1234.4, 1234.4, 1294.0, 1413.2", \ + "1565.1, 1565.1, 1565.1, 1624.7, 1743.9", \ + "2230.7, 2230.7, 2230.7, 2290.3, 2409.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("728.1, 728.1, 728.1, 787.7, 906.9", \ + "800.2, 800.2, 800.2, 859.8, 979.0", \ + "938.0, 938.0, 938.0, 997.6, 1116.8", \ + "1205.0, 1205.0, 1205.0, 1264.6, 1383.8", \ + "1731.0, 1731.0, 1731.0, 1790.6, 1909.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("702.2, 702.2, 702.2, 761.8, 881.0", \ + "824.9, 824.9, 824.9, 884.5, 1003.7", \ + "1050.5, 1050.5, 1050.5, 1110.1, 1229.3", \ + "1501.8, 1501.8, 1501.8, 1561.4, 1680.6", \ + "2399.2, 2399.2, 2399.2, 2458.8, 2578.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("656.6, 656.6, 656.6, 716.2, 835.4", \ + "700.4, 700.4, 700.4, 760.0, 879.2", \ + "784.1, 784.1, 784.1, 843.7, 962.9", \ + "945.7, 945.7, 945.7, 1005.3, 1124.5", \ + "1261.4, 1261.4, 1261.4, 1321.0, 1440.2"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("875.1, 875.1, 875.1, 934.7, 1053.9", \ + "993.5, 993.5, 993.5, 1053.0, 1172.2", \ + "1215.9, 1215.9, 1215.9, 1275.5, 1394.7", \ + "1664.4, 1664.4, 1664.4, 1724.0, 1843.2", \ + "2555.9, 2555.9, 2555.9, 2615.5, 2734.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("723.5, 723.5, 723.5, 783.1, 902.3", \ + "780.5, 780.5, 780.5, 840.1, 959.3", \ + "890.8, 890.8, 890.8, 950.4, 1069.6", \ + "1105.7, 1105.7, 1105.7, 1165.3, 1284.5", \ + "1528.9, 1528.9, 1528.9, 1588.5, 1707.7"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__1) { + values ("626.6, 626.6, 626.6, 686.2, 805.4", \ + "719.1, 719.1, 719.1, 778.7, 897.9", \ + "904.2, 904.2, 904.2, 963.8, 1083.0", \ + "1261.8, 1261.8, 1261.8, 1321.4, 1440.6", \ + "1969.3, 1969.3, 1969.3, 2028.9, 2148.1"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("595.0, 595.0, 595.0, 654.6, 773.8", \ + "642.4, 642.4, 642.4, 702.0, 821.2", \ + "730.0, 730.0, 730.0, 789.6, 908.8", \ + "896.8, 896.8, 896.8, 956.4, 1075.6", \ + "1221.9, 1221.9, 1221.9, 1281.5, 1400.7"); + } + } + } + } + + cell (noa3ao322_x1) { + area : 0.0 ; + cell_leakage_power : 2.8 ; + leakage_power () { + when : "(i6 & i5 & i4 & i3 & i2 & i1 & i0)" ; + value : 6.1 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & ((i4 & (i5 ^ i6)) | (!(i4) & i5 & i6))) | (!(i3) & i4 & i5 & i6)))" ; + value : 4.4 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 2.7 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((!(i3) & !((i4 & i5)) & i6) | (!(i4) & !(i5) & i6)))" ; + value : 4.2 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((!(i3) & !((i4 & i5)) & !(i6)) | (!(i4) & !(i5) & !(i6))))" ; + value : 2.5 ; + } + leakage_power () { + when : "(!(i6) & i5 & i4 & i3 & !(i2) & i1 & i0)" ; + value : 0.0003 ; + } + leakage_power () { + when : "(i0 & i1 & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 0.00023 ; + } + leakage_power () { + when : "(i6 & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 0.00027 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 9.7e-05 ; + } + leakage_power () { + when : "(!(i6) & i5 & i4 & i3 & i2 & !(i1) & i0)" ; + value : 0.00029 ; + } + leakage_power () { + when : "(i0 & !(i1) & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 0.00022 ; + } + leakage_power () { + when : "(i0 & !(i1) & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 0.00015 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 7.9e-05 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & i4 & i5 & i6) | (!(i0) & i1 & i2 & i3 & i4 & i5 & i6))" ; + value : 7.7 ; + } + leakage_power () { + when : "(!(i6) & i5 & i4 & i3 & i2 & i1 & !(i0))" ; + value : 0.00028 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & !(i5) & i6))" ; + value : 6.5 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & (i3 ^ i4) & i5 & i6) | (!(i0) & i1 & i2 & (i3 ^ i4) & i5 & i6))" ; + value : 4.9 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3) & i4 & !(i5) & i6) | (!(i0) & i1 & i2 & !(i3) & i4 & !(i5) & i6))" ; + value : 4.8 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3) & !(i4) & i5 & i6) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5 & i6))" ; + value : 4.7 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & !(i4) & !(i5) & i6)" ; + value : 0.00025 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & i2 & i1 & !(i0))" ; + value : 7.6e-05 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & i5 & i6) | (!(i0) & (i1 ^ i2) & i3 & i4 & i5 & i6))" ; + value : 9.3 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & !(i5) & i6) | (!(i0) & (i1 ^ i2) & i3 & !(i5) & i6))" ; + value : 8.7 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))) | (!(i0) & (i1 ^ i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))))" ; + value : 5.4 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & i5 & i6) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & i5 & i6))" ; + value : 5.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!(i0) & (i1 ^ i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))" ; + value : 7.5e-05 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & !(i6)))" ; + value : 5.7e-06 ; + } + leakage_power () { + when : "((!(i0) & ((i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!((i1 & i2)) & i3 & i4 & i5 & !(i6)))) | (!(i1) & !(i2) & i3 & i4 & i5 & !(i6)))" ; + value : 0.00021 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & i3 & (i4 | !(i5)) & i6)" ; + value : 11 ; + } + leakage_power () { + when : "((!(i0) & ((i1 & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!((i1 & i2)) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))) | (!(i1) & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))" ; + value : 0.00014 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6)))" ; + value : 6 ; + } + leakage_power () { + when : "(i6 & i5 & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.7 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 7.4e-05 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!(i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6))) | (!(i0) & !((i1 & i2)) & !(i3) & !(i4) & !(i5) & i6))" ; + value : 0.00017 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 4.8e-06 ; + } + pin (i6) { + direction : input ; + capacitance : 3.44 ; + } + pin (i5) { + direction : input ; + capacitance : 4.87 ; + } + pin (i4) { + direction : input ; + capacitance : 4.76 ; + } + pin (i3) { + direction : input ; + capacitance : 4.76 ; + } + pin (i2) { + direction : input ; + capacitance : 4.52 ; + } + pin (i1) { + direction : input ; + capacitance : 4.52 ; + } + pin (i0) { + direction : input ; + capacitance : 4.55 ; + } + pin (nq) { + function : "((((((((!(i3) & !(i4)) & !(i5)) & !(i2)) | (((!(i3) & !(i4)) & !(i5)) & !(i1))) | (((!(i3) & !(i4)) & !(i5)) & !(i0))) | (!(i6) & !(i2))) | (!(i6) & !(i1))) | (!(i6) & !(i0)))" ; + direction : output ; + capacitance : 3.97 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("219.6, 219.6, 219.6, 249.8, 310.7", \ + "252.6, 252.6, 252.6, 282.9, 343.8", \ + "310.6, 310.6, 310.6, 341.0, 402.2", \ + "423.6, 423.6, 423.6, 454.2, 515.4", \ + "649.2, 649.2, 649.2, 679.8, 741.1"); + } + rise_transition (inslew_load_5x5__23) { + values ("384.8, 384.8, 384.8, 437.9, 544.1", \ + "473.4, 473.4, 473.4, 526.3, 632.1", \ + "637.1, 637.1, 637.1, 689.8, 795.4", \ + "956.9, 956.9, 956.9, 1009.8, 1115.5", \ + "1592.7, 1592.7, 1592.7, 1645.5, 1751.2"); + } + cell_fall (inslew_load_5x5__23) { + values ("34.9, 34.9, 34.9, 43.6, 61.0", \ + "30.8, 30.8, 30.8, 40.2, 58.6", \ + "19.2, 19.2, 19.2, 29.8, 50.2", \ + "-8.5, -8.5, -8.5, 3.5, 26.5", \ + "-68.3, -68.3, -68.3, -55.0, -29.3"); + } + fall_transition (inslew_load_5x5__23) { + values ("60.5, 60.5, 60.5, 73.3, 99.0", \ + "73.0, 73.0, 73.0, 85.7, 111.2", \ + "97.8, 97.8, 97.8, 110.7, 136.1", \ + "146.7, 146.7, 146.7, 159.8, 185.7", \ + "243.5, 243.5, 243.5, 256.9, 283.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("200.6, 200.6, 200.6, 230.9, 291.8", \ + "222.8, 222.8, 222.8, 253.1, 314.1", \ + "260.4, 260.4, 260.4, 291.0, 352.3", \ + "333.6, 333.6, 333.6, 364.3, 425.8", \ + "480.4, 480.4, 480.4, 511.1, 572.6"); + } + rise_transition (inslew_load_5x5__23) { + values ("352.0, 352.0, 352.0, 405.1, 511.3", \ + "422.1, 422.1, 422.1, 474.8, 580.6", \ + "551.3, 551.3, 551.3, 604.0, 709.5", \ + "803.1, 803.1, 803.1, 855.8, 961.4", \ + "1304.0, 1304.0, 1304.0, 1356.6, 1461.9"); + } + cell_fall (inslew_load_5x5__23) { + values ("34.0, 34.0, 34.0, 43.3, 61.2", \ + "33.8, 33.8, 33.8, 44.3, 64.0", \ + "29.1, 29.1, 29.1, 41.1, 63.6", \ + "15.2, 15.2, 15.2, 28.7, 54.3", \ + "-16.3, -16.3, -16.3, -1.6, 26.7"); + } + fall_transition (inslew_load_5x5__23) { + values ("53.4, 53.4, 53.4, 66.3, 91.9", \ + "68.4, 68.4, 68.4, 81.3, 106.9", \ + "97.2, 97.2, 97.2, 110.5, 136.5", \ + "153.6, 153.6, 153.6, 167.2, 194.0", \ + "265.4, 265.4, 265.4, 279.3, 306.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("180.1, 180.1, 180.1, 210.4, 271.3", \ + "194.4, 194.4, 194.4, 224.8, 285.9", \ + "217.3, 217.3, 217.3, 248.0, 309.5", \ + "261.9, 261.9, 261.9, 292.8, 354.5", \ + "352.2, 352.2, 352.2, 383.1, 444.8"); + } + rise_transition (inslew_load_5x5__23) { + values ("316.6, 316.6, 316.6, 369.6, 475.7", \ + "373.6, 373.6, 373.6, 426.2, 531.8", \ + "478.1, 478.1, 478.1, 530.7, 636.1", \ + "681.4, 681.4, 681.4, 734.0, 839.4", \ + "1086.8, 1086.8, 1086.8, 1139.1, 1243.9"); + } + cell_fall (inslew_load_5x5__23) { + values ("31.1, 31.1, 31.1, 41.1, 60.0", \ + "34.0, 34.0, 34.0, 45.6, 66.9", \ + "35.1, 35.1, 35.1, 48.5, 73.2", \ + "33.3, 33.3, 33.3, 48.3, 76.5", \ + "26.8, 26.8, 26.8, 43.0, 74.0"); + } + fall_transition (inslew_load_5x5__23) { + values ("45.7, 45.7, 45.7, 58.6, 84.7", \ + "62.6, 62.6, 62.6, 75.9, 101.9", \ + "94.7, 94.7, 94.7, 108.5, 135.3", \ + "157.5, 157.5, 157.5, 171.7, 199.5", \ + "282.0, 282.0, 282.0, 296.5, 325.0"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("53.3, 53.3, 53.3, 85.0, 147.4", \ + "73.2, 73.2, 73.2, 105.9, 169.2", \ + "100.2, 100.2, 100.2, 133.6, 199.1", \ + "160.5, 160.5, 160.5, 194.6, 261.8", \ + "278.2, 278.2, 278.2, 312.8, 381.8"); + } + rise_transition (inslew_load_5x5__23) { + values ("99.3, 99.3, 99.3, 152.0, 260.0", \ + "156.4, 156.4, 156.4, 209.7, 317.0", \ + "244.6, 244.6, 244.6, 296.7, 403.1", \ + "428.8, 428.8, 428.8, 480.6, 586.9", \ + "795.9, 795.9, 795.9, 847.2, 951.4"); + } + cell_fall (inslew_load_5x5__23) { + values ("35.9, 35.9, 35.9, 52.0, 82.4", \ + "32.4, 32.4, 32.4, 50.4, 83.3", \ + "20.8, 20.8, 20.8, 41.5, 78.7", \ + "-7.6, -7.6, -7.6, 16.0, 59.0", \ + "-69.5, -69.5, -69.5, -43.1, 5.8"); + } + fall_transition (inslew_load_5x5__23) { + values ("49.7, 49.7, 49.7, 70.2, 111.4", \ + "63.2, 63.2, 63.2, 83.7, 124.5", \ + "87.9, 87.9, 87.9, 109.0, 150.0", \ + "135.5, 135.5, 135.5, 157.4, 199.8", \ + "228.9, 228.9, 228.9, 251.6, 295.8"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("101.4, 101.4, 101.4, 132.3, 193.8", \ + "116.2, 116.2, 116.2, 147.6, 209.6", \ + "139.7, 139.7, 139.7, 171.5, 234.3", \ + "187.7, 187.7, 187.7, 220.1, 284.1", \ + "281.6, 281.6, 281.6, 314.7, 380.0"); + } + rise_transition (inslew_load_5x5__23) { + values ("181.4, 181.4, 181.4, 234.7, 342.2", \ + "232.4, 232.4, 232.4, 285.5, 392.2", \ + "320.3, 320.3, 320.3, 372.9, 478.6", \ + "500.7, 500.7, 500.7, 552.4, 656.4", \ + "861.3, 861.3, 861.3, 912.3, 1014.7"); + } + cell_fall (inslew_load_5x5__23) { + values ("49.1, 49.1, 49.1, 64.4, 94.3", \ + "49.4, 49.4, 49.4, 66.1, 97.7", \ + "44.7, 44.7, 44.7, 63.5, 98.5", \ + "29.3, 29.3, 29.3, 50.5, 90.2", \ + "-7.2, -7.2, -7.2, 16.2, 60.8"); + } + fall_transition (inslew_load_5x5__23) { + values ("65.8, 65.8, 65.8, 86.3, 127.7", \ + "81.8, 81.8, 81.8, 102.2, 142.9", \ + "111.7, 111.7, 111.7, 132.4, 173.0", \ + "169.6, 169.6, 169.6, 190.8, 232.4", \ + "283.6, 283.6, 283.6, 305.3, 348.1"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("141.4, 141.4, 141.4, 172.0, 233.1", \ + "152.1, 152.1, 152.1, 182.9, 244.4", \ + "169.2, 169.2, 169.2, 200.3, 262.3", \ + "201.1, 201.1, 201.1, 232.4, 294.8", \ + "262.6, 262.6, 262.6, 294.3, 358.3"); + } + rise_transition (inslew_load_5x5__23) { + values ("251.8, 251.8, 251.8, 304.9, 411.5", \ + "299.7, 299.7, 299.7, 352.5, 458.5", \ + "386.9, 386.9, 386.9, 439.5, 545.2", \ + "557.5, 557.5, 557.5, 609.6, 714.3", \ + "899.8, 899.8, 899.8, 951.2, 1054.4"); + } + cell_fall (inslew_load_5x5__23) { + values ("57.4, 57.4, 57.4, 72.4, 101.9", \ + "62.0, 62.0, 62.0, 78.0, 109.0", \ + "66.0, 66.0, 66.0, 83.5, 117.2", \ + "68.3, 68.3, 68.3, 87.7, 124.9", \ + "68.1, 68.1, 68.1, 89.2, 129.9"); + } + fall_transition (inslew_load_5x5__23) { + values ("76.2, 76.2, 76.2, 96.8, 138.5", \ + "96.5, 96.5, 96.5, 117.1, 157.8", \ + "134.5, 134.5, 134.5, 155.0, 195.5", \ + "208.6, 208.6, 208.6, 229.4, 270.3", \ + "355.3, 355.3, 355.3, 376.3, 417.9"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("28.8, 28.8, 28.8, 50.7, 91.9", \ + "33.9, 33.9, 33.9, 57.5, 100.6", \ + "41.2, 41.2, 41.2, 67.4, 114.9", \ + "53.0, 53.0, 53.0, 81.3, 133.8", \ + "74.6, 74.6, 74.6, 104.3, 160.9"); + } + rise_transition (inslew_load_5x5__23) { + values ("61.6, 61.6, 61.6, 98.1, 172.0", \ + "91.7, 91.7, 91.7, 127.6, 199.8", \ + "149.2, 149.2, 149.2, 186.4, 259.0", \ + "262.6, 262.6, 262.6, 300.5, 375.0", \ + "488.1, 488.1, 488.1, 526.6, 602.5"); + } + cell_fall (inslew_load_5x5__23) { + values ("26.8, 26.8, 26.8, 44.7, 76.7", \ + "29.8, 29.8, 29.8, 50.4, 86.0", \ + "31.8, 31.8, 31.8, 55.2, 96.1", \ + "32.6, 32.6, 32.6, 58.4, 105.0", \ + "32.2, 32.2, 32.2, 59.7, 111.0"); + } + fall_transition (inslew_load_5x5__23) { + values ("37.4, 37.4, 37.4, 58.0, 99.3", \ + "55.9, 55.9, 55.9, 77.1, 118.2", \ + "90.6, 90.6, 90.6, 112.6, 154.9", \ + "158.4, 158.4, 158.4, 181.1, 225.0", \ + "292.7, 292.7, 292.7, 315.9, 361.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__23) { + values ("370.9, 370.9, 370.9, 420.5, 519.8", \ + "444.8, 444.8, 444.8, 494.4, 593.6", \ + "592.5, 592.5, 592.5, 642.1, 741.3", \ + "887.8, 887.8, 887.8, 937.5, 1036.7", \ + "1478.6, 1478.6, 1478.6, 1528.2, 1627.5"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("213.8, 213.8, 213.8, 263.4, 362.7", \ + "246.0, 246.0, 246.0, 295.6, 394.9", \ + "310.3, 310.3, 310.3, 360.0, 459.2", \ + "439.0, 439.0, 439.0, 488.7, 587.9", \ + "696.4, 696.4, 696.4, 746.1, 845.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__23) { + values ("336.1, 336.1, 336.1, 385.7, 485.0", \ + "394.1, 394.1, 394.1, 443.7, 543.0", \ + "510.0, 510.0, 510.0, 559.6, 658.9", \ + "741.8, 741.8, 741.8, 791.5, 890.7", \ + "1205.5, 1205.5, 1205.5, 1255.1, 1354.4"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("182.8, 182.8, 182.8, 232.4, 331.6", \ + "218.1, 218.1, 218.1, 267.7, 367.0", \ + "288.8, 288.8, 288.8, 338.4, 437.6", \ + "430.1, 430.1, 430.1, 479.7, 579.0", \ + "712.8, 712.8, 712.8, 762.4, 861.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__23) { + values ("300.0, 300.0, 300.0, 349.6, 448.9", \ + "346.6, 346.6, 346.6, 396.2, 495.5", \ + "439.8, 439.8, 439.8, 489.4, 588.7", \ + "626.2, 626.2, 626.2, 675.8, 775.1", \ + "999.0, 999.0, 999.0, 1048.6, 1147.9"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("150.8, 150.8, 150.8, 200.4, 299.6", \ + "188.4, 188.4, 188.4, 238.0, 337.3", \ + "263.6, 263.6, 263.6, 313.3, 412.5", \ + "414.2, 414.2, 414.2, 463.8, 563.0", \ + "715.2, 715.2, 715.2, 764.8, 864.1"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__23) { + values ("105.2, 105.2, 105.2, 154.9, 254.1", \ + "142.2, 142.2, 142.2, 191.8, 291.0", \ + "216.0, 216.0, 216.0, 265.6, 364.9", \ + "363.6, 363.6, 363.6, 413.3, 512.5", \ + "659.0, 659.0, 659.0, 708.6, 807.8"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("104.8, 104.8, 104.8, 154.5, 253.7", \ + "120.9, 120.9, 120.9, 170.5, 269.8", \ + "153.0, 153.0, 153.0, 202.6, 301.9", \ + "217.2, 217.2, 217.2, 266.8, 366.1", \ + "345.6, 345.6, 345.6, 395.2, 494.4"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__23) { + values ("172.8, 172.8, 172.8, 222.4, 321.7", \ + "210.7, 210.7, 210.7, 260.3, 359.6", \ + "286.5, 286.5, 286.5, 336.1, 435.4", \ + "438.0, 438.0, 438.0, 487.7, 586.9", \ + "741.2, 741.2, 741.2, 790.8, 890.0"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("146.4, 146.4, 146.4, 196.0, 295.2", \ + "167.8, 167.8, 167.8, 217.4, 316.6", \ + "210.6, 210.6, 210.6, 260.3, 359.5", \ + "296.3, 296.3, 296.3, 346.0, 445.2", \ + "467.8, 467.8, 467.8, 517.4, 616.6"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__23) { + values ("236.7, 236.7, 236.7, 286.3, 385.6", \ + "274.5, 274.5, 274.5, 324.1, 423.4", \ + "350.1, 350.1, 350.1, 399.8, 499.0", \ + "501.4, 501.4, 501.4, 551.0, 650.3", \ + "803.9, 803.9, 803.9, 853.6, 952.8"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("176.1, 176.1, 176.1, 225.7, 325.0", \ + "206.7, 206.7, 206.7, 256.3, 355.6", \ + "267.9, 267.9, 267.9, 317.5, 416.7", \ + "390.2, 390.2, 390.2, 439.9, 539.1", \ + "635.0, 635.0, 635.0, 684.6, 783.8"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__23) { + values ("75.2, 75.2, 75.2, 124.8, 224.0", \ + "102.5, 102.5, 102.5, 152.1, 251.4", \ + "157.2, 157.2, 157.2, 206.8, 306.1", \ + "266.6, 266.6, 266.6, 316.2, 415.4", \ + "485.3, 485.3, 485.3, 534.9, 634.2"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("75.2, 75.2, 75.2, 124.9, 224.1", \ + "99.1, 99.1, 99.1, 148.7, 247.9", \ + "146.7, 146.7, 146.7, 196.4, 295.6", \ + "242.0, 242.0, 242.0, 291.7, 390.9", \ + "432.7, 432.7, 432.7, 482.3, 581.6"); + } + } + } + } + + cell (noa3ao322_x4) { + area : 0.0 ; + cell_leakage_power : 8.3 ; + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & ((i4 & (i5 ^ i6)) | (!(i4) & i5 & i6))) | (!(i3) & i4 & i5 & i6)))" ; + value : 7.5 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 5.8 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((!(i3) & !((i4 & i5)) & i6) | (!(i4) & !(i5) & i6)))" ; + value : 7.4 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((!(i3) & !((i4 & i5)) & !(i6)) | (!(i4) & !(i5) & !(i6))))" ; + value : 5.7 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & i4 & i5 & i6) | (!(i0) & i1 & i2 & i3 & i4 & i5 & i6))" ; + value : 11 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & !(i5) & i6))" ; + value : 9.7 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & (i3 ^ i4) & i5 & i6) | (!(i0) & i1 & i2 & (i3 ^ i4) & i5 & i6))" ; + value : 8.1 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3) & i4 & !(i5) & i6) | (!(i0) & i1 & i2 & !(i3) & i4 & !(i5) & i6))" ; + value : 8 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3) & !(i4) & i5 & i6) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5 & i6))" ; + value : 7.9 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & (i4 | !(i5)) & i6) | (!(i0) & (i1 ^ i2) & i3 & (i4 | !(i5)) & i6))" ; + value : 12 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))) | (!(i0) & (i1 ^ i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))))" ; + value : 8.6 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & i5 & i6) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & i5 & i6))" ; + value : 8.4 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & i3 & (i4 | !(i5)) & i6)" ; + value : 14 ; + } + leakage_power () { + when : "((i0 & i1 & i2 & i3 & i4 & i5 & i6) | (!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))))" ; + value : 9.2 ; + } + leakage_power () { + when : "(i6 & i5 & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 8.9 ; + } + leakage_power () { + when : "(!((i0 & i1 & i2)) & (!((i3 | i4 | i5)) | !(i6)))" ; + value : 0.26 ; + } + pin (i6) { + direction : input ; + capacitance : 3.36 ; + } + pin (i5) { + direction : input ; + capacitance : 4.87 ; + } + pin (i4) { + direction : input ; + capacitance : 4.77 ; + } + pin (i3) { + direction : input ; + capacitance : 4.79 ; + } + pin (i2) { + direction : input ; + capacitance : 4.51 ; + } + pin (i1) { + direction : input ; + capacitance : 4.41 ; + } + pin (i0) { + direction : input ; + capacitance : 4.31 ; + } + pin (nq) { + function : "((!(i6) & (!(i0) | !(i1) | !(i2))) | (!((i0 & i1 & i2)) & !(i5) & !(i4) & !(i3)))" ; + direction : output ; + capacitance : 4.44 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("321.6, 321.6, 321.6, 327.4, 338.3", \ + "354.0, 354.0, 354.0, 359.8, 371.0", \ + "410.2, 410.2, 410.2, 416.1, 427.4", \ + "518.4, 518.4, 518.4, 524.3, 535.9", \ + "732.7, 732.7, 732.7, 738.5, 750.1"); + } + rise_transition (inslew_load_5x5__24) { + values ("110.9, 110.9, 110.9, 118.1, 132.4", \ + "127.0, 127.0, 127.0, 134.2, 148.5", \ + "156.6, 156.6, 156.6, 163.8, 178.1", \ + "214.2, 214.2, 214.2, 221.3, 235.5", \ + "328.2, 328.2, 328.2, 335.4, 349.6"); + } + cell_fall (inslew_load_5x5__24) { + values ("114.2, 114.2, 114.2, 119.4, 128.8", \ + "113.6, 113.6, 113.6, 118.9, 128.2", \ + "107.9, 107.9, 107.9, 113.3, 122.7", \ + "89.5, 89.5, 89.5, 95.1, 104.9", \ + "44.2, 44.2, 44.2, 49.9, 60.3"); + } + fall_transition (inslew_load_5x5__24) { + values ("41.1, 41.1, 41.1, 44.4, 51.0", \ + "43.7, 43.7, 43.7, 47.0, 53.6", \ + "48.5, 48.5, 48.5, 51.9, 58.5", \ + "58.1, 58.1, 58.1, 61.5, 67.9", \ + "76.6, 76.6, 76.6, 79.9, 86.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("302.8, 302.8, 302.8, 308.6, 319.4", \ + "324.7, 324.7, 324.7, 330.5, 341.5", \ + "361.3, 361.3, 361.3, 367.1, 378.4", \ + "431.0, 431.0, 431.0, 436.9, 448.4", \ + "569.4, 569.4, 569.4, 575.3, 586.9"); + } + rise_transition (inslew_load_5x5__24) { + values ("104.9, 104.9, 104.9, 112.1, 126.3", \ + "117.7, 117.7, 117.7, 124.8, 139.1", \ + "141.1, 141.1, 141.1, 148.3, 162.6", \ + "186.5, 186.5, 186.5, 193.6, 207.9", \ + "276.4, 276.4, 276.4, 283.6, 297.8"); + } + cell_fall (inslew_load_5x5__24) { + values ("112.5, 112.5, 112.5, 117.7, 127.0", \ + "116.8, 116.8, 116.8, 122.1, 131.4", \ + "119.4, 119.4, 119.4, 124.8, 134.2", \ + "116.1, 116.1, 116.1, 121.7, 131.6", \ + "100.6, 100.6, 100.6, 106.3, 116.8"); + } + fall_transition (inslew_load_5x5__24) { + values ("39.7, 39.7, 39.7, 43.0, 49.5", \ + "42.7, 42.7, 42.7, 46.0, 52.6", \ + "48.5, 48.5, 48.5, 51.8, 58.4", \ + "59.5, 59.5, 59.5, 62.9, 69.4", \ + "80.8, 80.8, 80.8, 84.2, 90.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("282.4, 282.4, 282.4, 288.1, 298.9", \ + "296.6, 296.6, 296.6, 302.4, 313.3", \ + "319.2, 319.2, 319.2, 325.0, 336.2", \ + "361.4, 361.4, 361.4, 367.3, 378.7", \ + "445.2, 445.2, 445.2, 451.2, 462.8"); + } + rise_transition (inslew_load_5x5__24) { + values ("98.4, 98.4, 98.4, 105.6, 119.8", \ + "108.8, 108.8, 108.8, 115.9, 130.2", \ + "127.8, 127.8, 127.8, 134.9, 149.2", \ + "164.5, 164.5, 164.5, 171.7, 186.0", \ + "237.4, 237.4, 237.4, 244.5, 258.7"); + } + cell_fall (inslew_load_5x5__24) { + values ("108.7, 108.7, 108.7, 113.9, 123.2", \ + "117.3, 117.3, 117.3, 122.5, 131.8", \ + "126.6, 126.6, 126.6, 132.0, 141.4", \ + "136.7, 136.7, 136.7, 142.2, 152.1", \ + "147.6, 147.6, 147.6, 153.3, 163.9"); + } + fall_transition (inslew_load_5x5__24) { + values ("38.1, 38.1, 38.1, 41.5, 47.9", \ + "41.7, 41.7, 41.7, 45.0, 51.6", \ + "48.1, 48.1, 48.1, 51.5, 58.1", \ + "60.4, 60.4, 60.4, 63.8, 70.3", \ + "84.1, 84.1, 84.1, 87.5, 94.0"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("154.6, 154.6, 154.6, 160.1, 170.5", \ + "177.2, 177.2, 177.2, 182.8, 193.4", \ + "206.0, 206.0, 206.0, 211.7, 222.4", \ + "267.0, 267.0, 267.0, 272.8, 283.8", \ + "380.7, 380.7, 380.7, 386.6, 398.1"); + } + rise_transition (inslew_load_5x5__24) { + values ("57.5, 57.5, 57.5, 64.6, 78.7", \ + "68.7, 68.7, 68.7, 75.8, 89.9", \ + "85.0, 85.0, 85.0, 92.2, 106.4", \ + "119.0, 119.0, 119.0, 126.2, 140.5", \ + "184.9, 184.9, 184.9, 192.0, 206.3"); + } + cell_fall (inslew_load_5x5__24) { + values ("123.6, 123.6, 123.6, 128.9, 138.2", \ + "125.1, 125.1, 125.1, 130.4, 139.7", \ + "121.4, 121.4, 121.4, 126.8, 136.2", \ + "104.1, 104.1, 104.1, 109.6, 119.4", \ + "58.1, 58.1, 58.1, 63.7, 74.2"); + } + fall_transition (inslew_load_5x5__24) { + values ("40.8, 40.8, 40.8, 44.1, 50.6", \ + "43.5, 43.5, 43.5, 46.8, 53.5", \ + "48.5, 48.5, 48.5, 51.9, 58.5", \ + "57.9, 57.9, 57.9, 61.3, 67.8", \ + "75.9, 75.9, 75.9, 79.3, 85.8"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("203.7, 203.7, 203.7, 209.3, 219.9", \ + "219.4, 219.4, 219.4, 225.1, 235.8", \ + "243.7, 243.7, 243.7, 249.5, 260.3", \ + "291.5, 291.5, 291.5, 297.3, 308.5", \ + "381.1, 381.1, 381.1, 387.0, 398.5"); + } + rise_transition (inslew_load_5x5__24) { + values ("73.4, 73.4, 73.4, 80.6, 94.7", \ + "82.9, 82.9, 82.9, 90.1, 104.3", \ + "99.0, 99.0, 99.0, 106.2, 120.4", \ + "131.7, 131.7, 131.7, 138.9, 153.2", \ + "196.7, 196.7, 196.7, 203.7, 218.0"); + } + cell_fall (inslew_load_5x5__24) { + values ("139.3, 139.3, 139.3, 144.6, 153.9", \ + "144.1, 144.1, 144.1, 149.5, 158.9", \ + "146.9, 146.9, 146.9, 152.4, 162.0", \ + "142.9, 142.9, 142.9, 148.5, 158.5", \ + "123.4, 123.4, 123.4, 129.1, 139.8"); + } + fall_transition (inslew_load_5x5__24) { + values ("44.0, 44.0, 44.0, 47.3, 54.0", \ + "47.2, 47.2, 47.2, 50.5, 57.1", \ + "53.1, 53.1, 53.1, 56.4, 63.0", \ + "64.3, 64.3, 64.3, 67.7, 74.2", \ + "86.1, 86.1, 86.1, 89.4, 96.0"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("243.9, 243.9, 243.9, 249.6, 260.3", \ + "255.1, 255.1, 255.1, 260.8, 271.5", \ + "272.3, 272.3, 272.3, 278.0, 289.0", \ + "302.9, 302.9, 302.9, 308.7, 320.0", \ + "359.8, 359.8, 359.8, 365.7, 377.2"); + } + rise_transition (inslew_load_5x5__24) { + values ("86.6, 86.6, 86.6, 93.8, 108.0", \ + "95.3, 95.3, 95.3, 102.5, 116.8", \ + "111.2, 111.2, 111.2, 118.4, 132.6", \ + "142.1, 142.1, 142.1, 149.3, 163.6", \ + "203.7, 203.7, 203.7, 210.7, 225.0"); + } + cell_fall (inslew_load_5x5__24) { + values ("149.1, 149.1, 149.1, 154.5, 163.8", \ + "158.5, 158.5, 158.5, 163.9, 173.4", \ + "170.1, 170.1, 170.1, 175.6, 185.4", \ + "184.9, 184.9, 184.9, 190.5, 200.8", \ + "204.5, 204.5, 204.5, 210.1, 221.0"); + } + fall_transition (inslew_load_5x5__24) { + values ("46.1, 46.1, 46.1, 49.5, 56.1", \ + "50.1, 50.1, 50.1, 53.4, 60.0", \ + "57.4, 57.4, 57.4, 60.8, 67.3", \ + "71.6, 71.6, 71.6, 75.0, 81.5", \ + "99.4, 99.4, 99.4, 102.7, 109.3"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("114.8, 114.8, 114.8, 120.3, 130.3", \ + "123.3, 123.3, 123.3, 128.9, 139.1", \ + "136.4, 136.4, 136.4, 142.0, 152.5", \ + "152.4, 152.4, 152.4, 158.2, 168.8", \ + "175.2, 175.2, 175.2, 181.0, 192.1"); + } + rise_transition (inslew_load_5x5__24) { + values ("45.8, 45.8, 45.8, 52.9, 66.9", \ + "51.8, 51.8, 51.8, 58.9, 72.9", \ + "63.5, 63.5, 63.5, 70.6, 84.6", \ + "85.1, 85.1, 85.1, 92.3, 106.5", \ + "126.4, 126.4, 126.4, 133.6, 147.9"); + } + cell_fall (inslew_load_5x5__24) { + values ("113.9, 113.9, 113.9, 119.1, 128.4", \ + "124.1, 124.1, 124.1, 129.4, 138.7", \ + "136.1, 136.1, 136.1, 141.6, 151.0", \ + "150.2, 150.2, 150.2, 155.7, 165.7", \ + "168.9, 168.9, 168.9, 174.6, 185.3"); + } + fall_transition (inslew_load_5x5__24) { + values ("38.3, 38.3, 38.3, 41.6, 48.1", \ + "42.2, 42.2, 42.2, 45.5, 52.1", \ + "49.3, 49.3, 49.3, 52.6, 59.2", \ + "62.5, 62.5, 62.5, 65.9, 72.4", \ + "88.1, 88.1, 88.1, 91.5, 98.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__24) { + values ("1443.0, 1443.0, 1443.0, 1498.4, 1609.3", \ + "1651.2, 1651.2, 1651.2, 1706.6, 1817.5", \ + "2047.4, 2047.4, 2047.4, 2102.8, 2213.7", \ + "2827.3, 2827.3, 2827.3, 2882.8, 2993.6", \ + "4380.6, 4380.6, 4380.6, 4436.1, 4547.0"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("815.4, 815.4, 815.4, 870.8, 981.7", \ + "875.5, 875.5, 875.5, 931.0, 1041.9", \ + "994.2, 994.2, 994.2, 1049.6, 1160.5", \ + "1229.6, 1229.6, 1229.6, 1285.0, 1395.9", \ + "1695.6, 1695.6, 1695.6, 1751.0, 1861.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__24) { + values ("1357.7, 1357.7, 1357.7, 1413.1, 1524.0", \ + "1522.3, 1522.3, 1522.3, 1577.7, 1688.6", \ + "1834.7, 1834.7, 1834.7, 1890.1, 2001.0", \ + "2448.0, 2448.0, 2448.0, 2503.5, 2614.4", \ + "3670.1, 3670.1, 3670.1, 3725.5, 3836.4"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("768.7, 768.7, 768.7, 824.2, 935.1", \ + "837.5, 837.5, 837.5, 892.9, 1003.8", \ + "972.2, 972.2, 972.2, 1027.7, 1138.6", \ + "1236.9, 1236.9, 1236.9, 1292.3, 1403.2", \ + "1760.2, 1760.2, 1760.2, 1815.7, 1926.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__24) { + values ("1267.6, 1267.6, 1267.6, 1323.0, 1433.9", \ + "1400.4, 1400.4, 1400.4, 1455.9, 1566.8", \ + "1652.8, 1652.8, 1652.8, 1708.2, 1819.1", \ + "2147.8, 2147.8, 2147.8, 2203.3, 2314.2", \ + "3134.0, 3134.0, 3134.0, 3189.4, 3300.3"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("719.4, 719.4, 719.4, 774.9, 885.8", \ + "796.1, 796.1, 796.1, 851.5, 962.4", \ + "943.0, 943.0, 943.0, 998.5, 1109.4", \ + "1230.6, 1230.6, 1230.6, 1286.0, 1396.9", \ + "1799.6, 1799.6, 1799.6, 1855.0, 1965.9"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__24) { + values ("736.9, 736.9, 736.9, 792.3, 903.2", \ + "864.1, 864.1, 864.1, 919.6, 1030.5", \ + "1072.3, 1072.3, 1072.3, 1127.8, 1238.6", \ + "1503.4, 1503.4, 1503.4, 1558.9, 1669.8", \ + "2352.3, 2352.3, 2352.3, 2407.7, 2518.6"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("702.8, 702.8, 702.8, 758.3, 869.2", \ + "749.0, 749.0, 749.0, 804.4, 915.3", \ + "836.8, 836.8, 836.8, 892.2, 1003.1", \ + "1006.2, 1006.2, 1006.2, 1061.6, 1172.5", \ + "1337.3, 1337.3, 1337.3, 1392.8, 1503.7"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__24) { + values ("933.7, 933.7, 933.7, 989.2, 1100.1", \ + "1049.8, 1049.8, 1049.8, 1105.3, 1216.2", \ + "1259.1, 1259.1, 1259.1, 1314.6, 1425.5", \ + "1684.1, 1684.1, 1684.1, 1739.5, 1850.4", \ + "2532.9, 2532.9, 2532.9, 2588.4, 2699.3"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("780.0, 780.0, 780.0, 835.5, 946.4", \ + "836.5, 836.5, 836.5, 892.0, 1002.8", \ + "945.0, 945.0, 945.0, 1000.4, 1111.3", \ + "1156.9, 1156.9, 1156.9, 1212.4, 1323.3", \ + "1574.2, 1574.2, 1574.2, 1629.6, 1740.5"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__24) { + values ("1105.9, 1105.9, 1105.9, 1161.3, 1272.2", \ + "1216.3, 1216.3, 1216.3, 1271.8, 1382.7", \ + "1424.6, 1424.6, 1424.6, 1480.1, 1591.0", \ + "1834.8, 1834.8, 1834.8, 1890.3, 2001.2", \ + "2654.7, 2654.7, 2654.7, 2710.2, 2821.1"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("833.1, 833.1, 833.1, 888.6, 999.5", \ + "907.8, 907.8, 907.8, 963.3, 1074.2", \ + "1051.3, 1051.3, 1051.3, 1106.7, 1217.6", \ + "1333.6, 1333.6, 1333.6, 1389.0, 1499.9", \ + "1892.4, 1892.4, 1892.4, 1947.9, 2058.8"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__24) { + values ("614.7, 614.7, 614.7, 670.1, 781.0", \ + "688.6, 688.6, 688.6, 744.0, 854.9", \ + "836.6, 836.6, 836.6, 892.1, 1003.0", \ + "1123.4, 1123.4, 1123.4, 1178.8, 1289.7", \ + "1687.1, 1687.1, 1687.1, 1742.6, 1853.5"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("646.1, 646.1, 646.1, 701.6, 812.5", \ + "712.7, 712.7, 712.7, 768.1, 879.0", \ + "838.6, 838.6, 838.6, 894.0, 1004.9", \ + "1082.5, 1082.5, 1082.5, 1138.0, 1248.9", \ + "1562.2, 1562.2, 1562.2, 1617.6, 1728.5"); + } + } + } + } + + cell (nxr2_x1) { + area : 0.0 ; + cell_leakage_power : 3.3 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.52 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 3.7 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 9 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.00027 ; + } + pin (i1) { + direction : input ; + capacitance : 8.89 ; + } + pin (i0) { + direction : input ; + capacitance : 8.28 ; + } + pin (nq) { + function : "!((i0 ^ i1))" ; + direction : output ; + capacitance : 5.09 ; + timing (maxd_nq_i0_positive_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__25) { + values ("51.3, 51.3, 51.3, 70.6, 106.9", \ + "56.2, 56.2, 56.2, 75.9, 112.9", \ + "59.6, 59.6, 59.6, 79.6, 117.7", \ + "61.0, 61.0, 61.0, 81.8, 121.5", \ + "58.0, 58.0, 58.0, 80.1, 121.7"); + } + rise_transition (inslew_load_5x5__25) { + values ("46.7, 46.7, 46.7, 78.8, 144.3", \ + "60.6, 60.6, 60.6, 92.7, 157.7", \ + "84.1, 84.1, 84.1, 115.4, 179.8", \ + "127.7, 127.7, 127.7, 159.0, 223.4", \ + "210.7, 210.7, 210.7, 242.7, 305.9"); + } + cell_fall (inslew_load_5x5__25) { + values ("54.1, 54.1, 54.1, 67.5, 89.8", \ + "61.5, 61.5, 61.5, 75.9, 100.2", \ + "71.5, 71.5, 71.5, 87.3, 114.5", \ + "86.9, 86.9, 86.9, 104.7, 135.1", \ + "115.5, 115.5, 115.5, 133.4, 168.6"); + } + fall_transition (inslew_load_5x5__25) { + values ("32.1, 32.1, 32.1, 44.3, 67.8", \ + "40.5, 40.5, 40.5, 53.0, 76.9", \ + "56.2, 56.2, 56.2, 69.3, 93.9", \ + "86.9, 86.9, 86.9, 100.2, 125.9", \ + "147.7, 147.7, 147.7, 161.3, 187.7"); + } + } + timing (maxd_nq_i1_positive_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__25) { + values ("80.0, 80.0, 80.0, 97.9, 133.3", \ + "82.4, 82.4, 82.4, 100.4, 136.2", \ + "81.3, 81.3, 81.3, 99.7, 135.5", \ + "73.7, 73.7, 73.7, 92.3, 129.1", \ + "54.5, 54.5, 54.5, 73.6, 111.0"); + } + rise_transition (inslew_load_5x5__25) { + values ("98.4, 98.4, 98.4, 130.4, 194.3", \ + "110.4, 110.4, 110.4, 141.8, 205.7", \ + "130.2, 130.2, 130.2, 161.8, 224.8", \ + "167.4, 167.4, 167.4, 198.4, 261.1", \ + "240.1, 240.1, 240.1, 270.8, 332.5"); + } + cell_fall (inslew_load_5x5__25) { + values ("73.5, 73.5, 73.5, 84.8, 105.4", \ + "85.6, 85.6, 85.6, 97.7, 119.7", \ + "104.3, 104.3, 104.3, 117.2, 141.2", \ + "136.4, 136.4, 136.4, 150.7, 176.8", \ + "197.1, 197.1, 197.1, 211.9, 240.2"); + } + fall_transition (inslew_load_5x5__25) { + values ("48.8, 48.8, 48.8, 60.7, 83.9", \ + "60.7, 60.7, 60.7, 72.6, 96.0", \ + "82.7, 82.7, 82.7, 95.0, 118.7", \ + "125.6, 125.6, 125.6, 138.0, 162.4", \ + "210.1, 210.1, 210.1, 223.0, 247.9"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("68.4, 68.4, 68.4, 86.4, 122.0", \ + "78.9, 78.9, 78.9, 97.2, 133.2", \ + "97.6, 97.6, 97.6, 116.2, 153.2", \ + "134.1, 134.1, 134.1, 153.1, 190.5", \ + "206.2, 206.2, 206.2, 225.5, 263.6"); + } + rise_transition (inslew_load_5x5__25) { + values ("133.8, 133.8, 133.8, 165.5, 229.4", \ + "179.5, 179.5, 179.5, 210.9, 274.1", \ + "268.0, 268.0, 268.0, 298.9, 361.2", \ + "444.6, 444.6, 444.6, 475.2, 536.5", \ + "798.1, 798.1, 798.1, 828.4, 889.1"); + } + cell_fall (inslew_load_5x5__25) { + values ("29.3, 29.3, 29.3, 38.8, 56.9", \ + "29.4, 29.4, 29.4, 40.0, 60.0", \ + "26.4, 26.4, 26.4, 38.4, 60.8", \ + "17.3, 17.3, 17.3, 30.6, 55.6", \ + "-2.9, -2.9, -2.9, 11.1, 38.4"); + } + fall_transition (inslew_load_5x5__25) { + values ("43.7, 43.7, 43.7, 55.4, 78.5", \ + "59.8, 59.8, 59.8, 71.4, 94.4", \ + "90.9, 90.9, 90.9, 102.8, 126.2", \ + "152.1, 152.1, 152.1, 164.3, 188.3", \ + "273.7, 273.7, 273.7, 286.2, 310.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("43.9, 43.9, 43.9, 63.2, 100.1", \ + "62.7, 62.7, 62.7, 82.7, 121.0", \ + "96.5, 96.5, 96.5, 117.2, 157.3", \ + "160.1, 160.1, 160.1, 181.6, 223.3", \ + "285.2, 285.2, 285.2, 307.2, 350.5"); + } + rise_transition (inslew_load_5x5__25) { + values ("82.2, 82.2, 82.2, 114.2, 179.3", \ + "132.1, 132.1, 132.1, 163.9, 228.3", \ + "227.7, 227.7, 227.7, 259.2, 322.8", \ + "413.6, 413.6, 413.6, 445.5, 508.7", \ + "783.2, 783.2, 783.2, 815.3, 879.1"); + } + cell_fall (inslew_load_5x5__25) { + values ("17.0, 17.0, 17.0, 27.5, 46.5", \ + "10.4, 10.4, 10.4, 22.7, 44.4", \ + "-6.0, -6.0, -6.0, 8.4, 33.9", \ + "-42.4, -42.4, -42.4, -25.8, 3.9", \ + "-117.7, -117.7, -117.7, -99.5, -65.7"); + } + fall_transition (inslew_load_5x5__25) { + values ("30.5, 30.5, 30.5, 42.1, 65.2", \ + "41.2, 41.2, 41.2, 53.3, 76.5", \ + "61.6, 61.6, 61.6, 74.3, 98.5", \ + "101.2, 101.2, 101.2, 114.5, 140.1", \ + "179.4, 179.4, 179.4, 193.3, 220.2"); + } + } + internal_power (energy_pos_nq_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__25) { + values ("211.9, 211.9, 211.9, 275.5, 402.9", \ + "256.2, 256.2, 256.2, 319.9, 447.2", \ + "342.8, 342.8, 342.8, 406.5, 533.8", \ + "514.3, 514.3, 514.3, 578.0, 705.3", \ + "855.7, 855.7, 855.7, 919.4, 1046.7"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("238.8, 238.8, 238.8, 302.4, 429.7", \ + "299.4, 299.4, 299.4, 363.0, 490.3", \ + "419.2, 419.2, 419.2, 482.9, 610.2", \ + "657.9, 657.9, 657.9, 721.5, 848.8", \ + "1134.4, 1134.4, 1134.4, 1198.1, 1325.4"); + } + } + internal_power (energy_pos_nq_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__25) { + values ("316.5, 316.5, 316.5, 380.2, 507.5", \ + "361.1, 361.1, 361.1, 424.8, 552.1", \ + "448.2, 448.2, 448.2, 511.8, 639.2", \ + "620.3, 620.3, 620.3, 684.0, 811.3", \ + "963.0, 963.0, 963.0, 1026.7, 1154.0"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("338.4, 338.4, 338.4, 402.0, 529.3", \ + "414.4, 414.4, 414.4, 478.1, 605.4", \ + "563.5, 563.5, 563.5, 627.2, 754.5", \ + "859.8, 859.8, 859.8, 923.4, 1050.8", \ + "1451.1, 1451.1, 1451.1, 1514.8, 1642.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__25) { + values ("261.6, 261.6, 261.6, 325.3, 452.6", \ + "341.4, 341.4, 341.4, 405.1, 532.4", \ + "501.0, 501.0, 501.0, 564.6, 691.9", \ + "820.0, 820.0, 820.0, 883.7, 1011.0", \ + "1458.2, 1458.2, 1458.2, 1521.9, 1649.2"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("207.8, 207.8, 207.8, 271.5, 398.8", \ + "260.3, 260.3, 260.3, 324.0, 451.3", \ + "365.3, 365.3, 365.3, 428.9, 556.2", \ + "575.2, 575.2, 575.2, 638.8, 766.1", \ + "995.0, 995.0, 995.0, 1058.6, 1185.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__25) { + values ("161.9, 161.9, 161.9, 225.5, 352.9", \ + "236.8, 236.8, 236.8, 300.5, 427.8", \ + "386.6, 386.6, 386.6, 450.3, 577.6", \ + "686.3, 686.3, 686.3, 750.0, 877.3", \ + "1285.7, 1285.7, 1285.7, 1349.4, 1476.7"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("129.9, 129.9, 129.9, 193.6, 320.9", \ + "157.0, 157.0, 157.0, 220.6, 348.0", \ + "211.2, 211.2, 211.2, 274.8, 402.1", \ + "319.5, 319.5, 319.5, 383.2, 510.5", \ + "536.3, 536.3, 536.3, 599.9, 727.3"); + } + } + } + } + + cell (nxr2_x4) { + area : 0.0 ; + cell_leakage_power : 5.4 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 3.9 ; + } + leakage_power () { + when : "(i0 ^ i1)" ; + value : 3.4 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 8.7 ; + } + pin (i1) { + direction : input ; + capacitance : 8.69 ; + } + pin (i0) { + direction : input ; + capacitance : 8.28 ; + } + pin (nq) { + function : "!((i0 ^ i1))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_nq_i0_positive_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("67.3, 67.3, 67.3, 73.3, 84.0", \ + "72.1, 72.1, 72.1, 78.1, 89.2", \ + "76.7, 76.7, 76.7, 82.7, 94.2", \ + "79.1, 79.1, 79.1, 85.3, 97.2", \ + "77.7, 77.7, 77.7, 84.1, 96.4"); + } + rise_transition (inslew_load_5x5__1) { + values ("49.8, 49.8, 49.8, 57.5, 72.6", \ + "60.4, 60.4, 60.4, 68.1, 83.2", \ + "80.7, 80.7, 80.7, 88.5, 103.7", \ + "120.2, 120.2, 120.2, 127.9, 143.3", \ + "197.6, 197.6, 197.6, 205.3, 220.7"); + } + cell_fall (inslew_load_5x5__1) { + values ("108.0, 108.0, 108.0, 114.0, 125.0", \ + "117.3, 117.3, 117.3, 123.3, 134.6", \ + "133.5, 133.5, 133.5, 139.5, 151.2", \ + "164.1, 164.1, 164.1, 169.7, 181.3", \ + "223.9, 223.9, 223.9, 229.6, 240.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("67.1, 67.1, 67.1, 70.8, 78.0", \ + "81.3, 81.3, 81.3, 85.0, 92.2", \ + "108.9, 108.9, 108.9, 112.6, 119.9", \ + "164.0, 164.0, 164.0, 167.9, 175.4", \ + "274.6, 274.6, 274.6, 278.4, 286.2"); + } + } + timing (maxd_nq_i1_positive_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("67.8, 67.8, 67.8, 73.7, 84.4", \ + "78.3, 78.3, 78.3, 84.3, 95.3", \ + "92.4, 92.4, 92.4, 98.5, 109.9", \ + "113.0, 113.0, 113.0, 119.2, 131.2", \ + "148.1, 148.1, 148.1, 154.5, 166.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("46.5, 46.5, 46.5, 54.2, 69.2", \ + "59.3, 59.3, 59.3, 67.0, 82.1", \ + "82.9, 82.9, 82.9, 90.7, 105.9", \ + "128.3, 128.3, 128.3, 136.1, 151.5", \ + "217.3, 217.3, 217.3, 225.0, 240.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("97.0, 97.0, 97.0, 102.9, 113.6", \ + "100.7, 100.7, 100.7, 106.6, 117.7", \ + "105.3, 105.3, 105.3, 111.3, 122.8", \ + "112.9, 112.9, 112.9, 118.6, 130.4", \ + "126.0, 126.0, 126.0, 131.6, 142.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("60.4, 60.4, 60.4, 64.1, 71.3", \ + "71.4, 71.4, 71.4, 75.0, 82.3", \ + "93.0, 93.0, 93.0, 96.7, 104.0", \ + "136.5, 136.5, 136.5, 140.4, 147.6", \ + "222.1, 222.1, 222.1, 226.0, 233.8"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("96.8, 96.8, 96.8, 102.6, 113.1", \ + "107.9, 107.9, 107.9, 113.9, 124.6", \ + "123.5, 123.5, 123.5, 129.5, 140.6", \ + "147.3, 147.3, 147.3, 153.3, 164.8", \ + "187.4, 187.4, 187.4, 193.7, 205.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("42.6, 42.6, 42.6, 50.3, 65.3", \ + "48.6, 48.6, 48.6, 56.3, 71.4", \ + "59.5, 59.5, 59.5, 67.2, 82.4", \ + "79.9, 79.9, 79.9, 87.6, 102.9", \ + "119.0, 119.0, 119.0, 126.8, 142.2"); + } + cell_fall (inslew_load_5x5__1) { + values ("95.6, 95.6, 95.6, 101.2, 111.2", \ + "100.9, 100.9, 100.9, 106.6, 116.7", \ + "104.4, 104.4, 104.4, 110.2, 120.5", \ + "105.7, 105.7, 105.7, 111.7, 122.6", \ + "101.8, 101.8, 101.8, 107.8, 119.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("39.7, 39.7, 39.7, 43.4, 50.4", \ + "44.0, 44.0, 44.0, 47.6, 54.8", \ + "51.1, 51.1, 51.1, 54.8, 62.0", \ + "64.7, 64.7, 64.7, 68.4, 75.6", \ + "91.1, 91.1, 91.1, 94.8, 102.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("96.3, 96.3, 96.3, 102.2, 112.8", \ + "105.1, 105.1, 105.1, 111.0, 121.7", \ + "116.5, 116.5, 116.5, 122.5, 133.5", \ + "132.6, 132.6, 132.6, 138.7, 150.1", \ + "157.1, 157.1, 157.1, 163.3, 174.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("44.8, 44.8, 44.8, 52.5, 67.5", \ + "49.6, 49.6, 49.6, 57.2, 72.3", \ + "58.2, 58.2, 58.2, 65.9, 81.0", \ + "74.5, 74.5, 74.5, 82.3, 97.5", \ + "105.6, 105.6, 105.6, 113.4, 128.7"); + } + cell_fall (inslew_load_5x5__1) { + values ("104.8, 104.8, 104.8, 110.5, 120.6", \ + "111.9, 111.9, 111.9, 117.7, 128.0", \ + "118.4, 118.4, 118.4, 124.4, 135.0", \ + "125.3, 125.3, 125.3, 131.3, 142.4", \ + "132.0, 132.0, 132.0, 138.1, 149.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("44.8, 44.8, 44.8, 48.4, 55.6", \ + "49.9, 49.9, 49.9, 53.6, 60.8", \ + "58.5, 58.5, 58.5, 62.2, 69.4", \ + "75.0, 75.0, 75.0, 78.7, 85.9", \ + "106.3, 106.3, 106.3, 109.9, 117.2"); + } + } + internal_power (energy_pos_nq_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("633.5, 633.5, 633.5, 693.1, 812.2", \ + "741.8, 741.8, 741.8, 801.4, 920.6", \ + "956.3, 956.3, 956.3, 1015.9, 1135.1", \ + "1380.9, 1380.9, 1380.9, 1440.5, 1559.7", \ + "2224.2, 2224.2, 2224.2, 2283.8, 2403.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("918.5, 918.5, 918.5, 978.1, 1097.3", \ + "1098.9, 1098.9, 1098.9, 1158.5, 1277.7", \ + "1454.5, 1454.5, 1454.5, 1514.1, 1633.3", \ + "2167.4, 2167.4, 2167.4, 2227.0, 2346.2", \ + "3596.4, 3596.4, 3596.4, 3656.0, 3775.2"); + } + } + internal_power (energy_pos_nq_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("582.6, 582.6, 582.6, 642.2, 761.4", \ + "706.2, 706.2, 706.2, 765.8, 885.0", \ + "946.1, 946.1, 946.1, 1005.7, 1124.9", \ + "1418.7, 1418.7, 1418.7, 1478.3, 1597.5", \ + "2356.6, 2356.6, 2356.6, 2416.2, 2535.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("825.8, 825.8, 825.8, 885.4, 1004.6", \ + "963.8, 963.8, 963.8, 1023.4, 1142.6", \ + "1237.1, 1237.1, 1237.1, 1296.7, 1415.9", \ + "1787.5, 1787.5, 1787.5, 1847.1, 1966.3", \ + "2879.7, 2879.7, 2879.7, 2939.3, 3058.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__1) { + values ("626.3, 626.3, 626.3, 685.9, 805.1", \ + "718.1, 718.1, 718.1, 777.7, 896.9", \ + "895.6, 895.6, 895.6, 955.2, 1074.4", \ + "1243.8, 1243.8, 1243.8, 1303.4, 1422.6", \ + "1933.3, 1933.3, 1933.3, 1992.9, 2112.1"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("672.9, 672.9, 672.9, 732.5, 851.7", \ + "747.0, 747.0, 747.0, 806.6, 925.8", \ + "884.3, 884.3, 884.3, 943.9, 1063.1", \ + "1152.2, 1152.2, 1152.2, 1211.8, 1331.0", \ + "1680.9, 1680.9, 1680.9, 1740.5, 1859.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__1) { + values ("676.5, 676.5, 676.5, 736.1, 855.3", \ + "759.7, 759.7, 759.7, 819.3, 938.5", \ + "921.5, 921.5, 921.5, 981.1, 1100.3", \ + "1239.8, 1239.8, 1239.8, 1299.3, 1418.5", \ + "1869.9, 1869.9, 1869.9, 1929.5, 2048.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("749.5, 749.5, 749.5, 809.1, 928.3", \ + "834.8, 834.8, 834.8, 894.4, 1013.6", \ + "990.7, 990.7, 990.7, 1050.3, 1169.5", \ + "1295.9, 1295.9, 1295.9, 1355.5, 1474.6", \ + "1891.2, 1891.2, 1891.2, 1950.8, 2070.0"); + } + } + } + } + + cell (o2_x2) { + area : 0.0 ; + cell_leakage_power : 1.8 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.98 ; + } + leakage_power () { + when : "(!(i0) | i1)" ; + value : 2.6 ; + } + pin (i1) { + direction : input ; + capacitance : 5.01 ; + } + pin (i0) { + direction : input ; + capacitance : 4.73 ; + } + pin (q) { + function : "(i0 | i1)" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("57.0, 57.0, 57.0, 64.0, 76.3", \ + "72.3, 72.3, 72.3, 79.5, 92.6", \ + "96.8, 96.8, 96.8, 104.2, 118.2", \ + "141.1, 141.1, 141.1, 148.9, 163.6", \ + "226.2, 226.2, 226.2, 234.1, 249.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("35.3, 35.3, 35.3, 44.8, 63.4", \ + "50.5, 50.5, 50.5, 60.2, 79.0", \ + "78.4, 78.4, 78.4, 88.1, 107.2", \ + "132.0, 132.0, 132.0, 141.8, 161.1", \ + "237.7, 237.7, 237.7, 247.4, 266.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("58.1, 58.1, 58.1, 64.8, 76.9", \ + "55.1, 55.1, 55.1, 62.0, 74.4", \ + "47.3, 47.3, 47.3, 54.6, 67.5", \ + "29.1, 29.1, 29.1, 36.5, 50.5", \ + "-10.0, -10.0, -10.0, -2.8, 11.9"); + } + fall_transition (inslew_load_5x5__0) { + values ("37.9, 37.9, 37.9, 42.5, 51.1", \ + "45.7, 45.7, 45.7, 50.3, 59.1", \ + "61.0, 61.0, 61.0, 65.7, 74.7", \ + "91.8, 91.8, 91.8, 96.4, 105.6", \ + "153.0, 153.0, 153.0, 157.9, 167.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("45.3, 45.3, 45.3, 52.1, 64.0", \ + "51.8, 51.8, 51.8, 58.9, 71.5", \ + "58.6, 58.6, 58.6, 66.0, 79.4", \ + "66.8, 66.8, 66.8, 74.5, 88.7", \ + "79.0, 79.0, 79.0, 86.9, 102.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("28.8, 28.8, 28.8, 38.3, 56.8", \ + "40.5, 40.5, 40.5, 50.1, 68.8", \ + "61.2, 61.2, 61.2, 70.8, 89.7", \ + "100.0, 100.0, 100.0, 109.8, 129.0", \ + "175.9, 175.9, 175.9, 185.6, 205.1"); + } + cell_fall (inslew_load_5x5__0) { + values ("48.8, 48.8, 48.8, 55.5, 66.7", \ + "54.4, 54.4, 54.4, 61.1, 73.3", \ + "60.8, 60.8, 60.8, 68.0, 80.8", \ + "69.8, 69.8, 69.8, 77.2, 91.3", \ + "85.5, 85.5, 85.5, 92.6, 107.3"); + } + fall_transition (inslew_load_5x5__0) { + values ("28.7, 28.7, 28.7, 33.2, 41.6", \ + "38.6, 38.6, 38.6, 43.2, 51.8", \ + "57.3, 57.3, 57.3, 61.9, 71.0", \ + "93.9, 93.9, 93.9, 98.6, 107.7", \ + "166.3, 166.3, 166.3, 171.2, 180.5"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("315.8, 315.8, 315.8, 353.3, 428.2", \ + "416.1, 416.1, 416.1, 453.6, 528.5", \ + "612.8, 612.8, 612.8, 650.3, 725.2", \ + "1003.3, 1003.3, 1003.3, 1040.8, 1115.7", \ + "1782.0, 1782.0, 1782.0, 1819.4, 1894.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("384.5, 384.5, 384.5, 422.0, 496.9", \ + "455.2, 455.2, 455.2, 492.7, 567.6", \ + "596.1, 596.1, 596.1, 633.6, 708.5", \ + "878.2, 878.2, 878.2, 915.7, 990.6", \ + "1442.2, 1442.2, 1442.2, 1479.6, 1554.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("240.9, 240.9, 240.9, 278.3, 353.3", \ + "304.7, 304.7, 304.7, 342.2, 417.1", \ + "428.8, 428.8, 428.8, 466.3, 541.2", \ + "673.8, 673.8, 673.8, 711.3, 786.2", \ + "1161.3, 1161.3, 1161.3, 1198.7, 1273.7"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("284.2, 284.2, 284.2, 321.6, 396.6", \ + "364.6, 364.6, 364.6, 402.1, 477.0", \ + "522.1, 522.1, 522.1, 559.6, 634.5", \ + "834.6, 834.6, 834.6, 872.1, 947.0", \ + "1457.9, 1457.9, 1457.9, 1495.3, 1570.3"); + } + } + } + } + + cell (o2_x4) { + area : 0.0 ; + cell_leakage_power : 1.7 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.54 ; + } + leakage_power () { + when : "i1" ; + value : 1.2 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 3.2 ; + } + pin (i1) { + direction : input ; + capacitance : 4.46 ; + } + pin (i0) { + direction : input ; + capacitance : 4.58 ; + } + pin (q) { + function : "(i0 | i1)" ; + direction : output ; + capacitance : 4.68 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__26) { + values ("64.5, 64.5, 64.5, 70.5, 81.3", \ + "76.3, 76.3, 76.3, 82.4, 93.5", \ + "92.2, 92.2, 92.2, 98.3, 110.0", \ + "116.4, 116.4, 116.4, 122.8, 134.8", \ + "158.5, 158.5, 158.5, 165.0, 177.6"); + } + rise_transition (inslew_load_5x5__26) { + values ("40.2, 40.2, 40.2, 48.1, 63.4", \ + "53.8, 53.8, 53.8, 61.7, 77.1", \ + "78.8, 78.8, 78.8, 86.7, 102.2", \ + "125.9, 125.9, 125.9, 133.9, 149.6", \ + "218.1, 218.1, 218.1, 226.0, 241.9"); + } + cell_fall (inslew_load_5x5__26) { + values ("88.3, 88.3, 88.3, 94.3, 105.3", \ + "90.6, 90.6, 90.6, 96.7, 108.1", \ + "93.4, 93.4, 93.4, 99.1, 110.8", \ + "96.5, 96.5, 96.5, 102.4, 113.4", \ + "99.7, 99.7, 99.7, 105.9, 117.5"); + } + fall_transition (inslew_load_5x5__26) { + values ("54.6, 54.6, 54.6, 58.1, 65.2", \ + "64.4, 64.4, 64.4, 67.9, 75.1", \ + "83.7, 83.7, 83.7, 87.4, 94.5", \ + "122.6, 122.6, 122.6, 126.5, 133.9", \ + "199.0, 199.0, 199.0, 203.0, 210.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__26) { + values ("55.8, 55.8, 55.8, 61.8, 72.3", \ + "61.1, 61.1, 61.1, 67.0, 78.0", \ + "62.8, 62.8, 62.8, 69.0, 80.4", \ + "56.9, 56.9, 56.9, 63.1, 75.0", \ + "36.3, 36.3, 36.3, 42.7, 55.0"); + } + rise_transition (inslew_load_5x5__26) { + values ("35.0, 35.0, 35.0, 42.9, 58.2", \ + "45.9, 45.9, 45.9, 53.7, 69.1", \ + "64.9, 64.9, 64.9, 72.8, 88.3", \ + "99.6, 99.6, 99.6, 107.5, 123.2", \ + "165.9, 165.9, 165.9, 173.9, 189.7"); + } + cell_fall (inslew_load_5x5__26) { + values ("77.9, 77.9, 77.9, 83.8, 94.1", \ + "89.4, 89.4, 89.4, 95.4, 106.4", \ + "107.1, 107.1, 107.1, 113.0, 124.6", \ + "137.6, 137.6, 137.6, 143.5, 154.4", \ + "193.1, 193.1, 193.1, 199.3, 211.1"); + } + fall_transition (inslew_load_5x5__26) { + values ("43.8, 43.8, 43.8, 47.5, 54.5", \ + "55.8, 55.8, 55.8, 59.3, 66.4", \ + "77.9, 77.9, 77.9, 81.5, 88.6", \ + "121.4, 121.4, 121.4, 125.2, 132.7", \ + "207.4, 207.4, 207.4, 211.4, 219.2"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__26) { + values ("462.0, 462.0, 462.0, 520.5, 637.4", \ + "570.8, 570.8, 570.8, 629.3, 746.1", \ + "781.2, 781.2, 781.2, 839.7, 956.6", \ + "1193.2, 1193.2, 1193.2, 1251.6, 1368.5", \ + "2009.6, 2009.6, 2009.6, 2068.0, 2184.9"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("653.9, 653.9, 653.9, 712.4, 829.3", \ + "760.3, 760.3, 760.3, 818.7, 935.6", \ + "972.0, 972.0, 972.0, 1030.4, 1147.3", \ + "1399.3, 1399.3, 1399.3, 1457.7, 1574.6", \ + "2245.4, 2245.4, 2245.4, 2303.8, 2420.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__26) { + values ("393.8, 393.8, 393.8, 452.3, 569.2", \ + "469.1, 469.1, 469.1, 527.6, 644.4", \ + "610.4, 610.4, 610.4, 668.8, 785.7", \ + "881.2, 881.2, 881.2, 939.7, 1056.5", \ + "1411.1, 1411.1, 1411.1, 1469.5, 1586.4"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("528.9, 528.9, 528.9, 587.4, 704.3", \ + "648.1, 648.1, 648.1, 706.5, 823.4", \ + "876.5, 876.5, 876.5, 934.9, 1051.8", \ + "1331.7, 1331.7, 1331.7, 1390.1, 1507.0", \ + "2237.1, 2237.1, 2237.1, 2295.5, 2412.4"); + } + } + } + } + + cell (o3_x2) { + area : 0.0 ; + cell_leakage_power : 1.5 ; + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 0.87 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2)) | (i1 & !(i2)))" ; + value : 0.98 ; + } + leakage_power () { + when : "((!(i0) & (!(i1) | i2)) | (i1 & i2))" ; + value : 2.6 ; + } + pin (i2) { + direction : input ; + capacitance : 5.02 ; + } + pin (i1) { + direction : input ; + capacitance : 5.00 ; + } + pin (i0) { + direction : input ; + capacitance : 4.73 ; + } + pin (q) { + function : "(i0 | i1 | i2)" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("62.5, 62.5, 62.5, 69.5, 82.0", \ + "78.3, 78.3, 78.3, 85.6, 98.8", \ + "103.4, 103.4, 103.4, 110.9, 124.9", \ + "148.0, 148.0, 148.0, 155.8, 170.5", \ + "233.2, 233.2, 233.2, 241.2, 256.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("38.3, 38.3, 38.3, 47.8, 66.5", \ + "53.4, 53.4, 53.4, 63.1, 81.9", \ + "81.3, 81.3, 81.3, 91.0, 110.1", \ + "134.8, 134.8, 134.8, 144.5, 163.8", \ + "240.3, 240.3, 240.3, 250.0, 269.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("108.7, 108.7, 108.7, 116.1, 129.4", \ + "105.9, 105.9, 105.9, 113.3, 126.9", \ + "99.5, 99.5, 99.5, 107.0, 121.1", \ + "87.6, 87.6, 87.6, 95.1, 109.7", \ + "63.3, 63.3, 63.3, 70.5, 84.8"); + } + fall_transition (inslew_load_5x5__0) { + values ("67.8, 67.8, 67.8, 72.5, 81.6", \ + "78.0, 78.0, 78.0, 82.7, 91.9", \ + "97.3, 97.3, 97.3, 102.0, 111.3", \ + "136.0, 136.0, 136.0, 140.8, 150.1", \ + "213.9, 213.9, 213.9, 218.8, 228.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("55.3, 55.3, 55.3, 62.3, 74.5", \ + "63.1, 63.1, 63.1, 70.2, 83.1", \ + "71.4, 71.4, 71.4, 78.8, 92.4", \ + "80.8, 80.8, 80.8, 88.4, 102.8", \ + "93.9, 93.9, 93.9, 101.8, 117.0"); + } + rise_transition (inslew_load_5x5__0) { + values ("34.2, 34.2, 34.2, 43.8, 62.3", \ + "45.9, 45.9, 45.9, 55.5, 74.2", \ + "66.6, 66.6, 66.6, 76.3, 95.2", \ + "105.5, 105.5, 105.5, 115.3, 134.5", \ + "181.4, 181.4, 181.4, 191.1, 210.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("92.6, 92.6, 92.6, 99.8, 112.5", \ + "98.4, 98.4, 98.4, 105.8, 119.0", \ + "107.1, 107.1, 107.1, 114.6, 128.5", \ + "122.3, 122.3, 122.3, 129.8, 144.3", \ + "151.1, 151.1, 151.1, 158.3, 172.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("55.2, 55.2, 55.2, 59.9, 68.9", \ + "66.8, 66.8, 66.8, 71.5, 80.6", \ + "89.2, 89.2, 89.2, 93.9, 103.1", \ + "134.0, 134.0, 134.0, 138.8, 148.2", \ + "221.9, 221.9, 221.9, 226.9, 236.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("45.5, 45.5, 45.5, 52.3, 64.2", \ + "48.3, 48.3, 48.3, 55.4, 67.8", \ + "46.6, 46.6, 46.6, 53.9, 67.1", \ + "35.8, 35.8, 35.8, 43.3, 57.5", \ + "8.0, 8.0, 8.0, 15.8, 30.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("28.8, 28.8, 28.8, 38.4, 56.9", \ + "38.8, 38.8, 38.8, 48.3, 67.0", \ + "55.9, 55.9, 55.9, 65.5, 84.4", \ + "87.1, 87.1, 87.1, 96.9, 116.0", \ + "147.5, 147.5, 147.5, 157.2, 176.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("68.6, 68.6, 68.6, 75.3, 87.5", \ + "79.9, 79.9, 79.9, 87.0, 99.6", \ + "98.7, 98.7, 98.7, 106.0, 119.6", \ + "132.2, 132.2, 132.2, 139.7, 154.2", \ + "195.6, 195.6, 195.6, 202.9, 217.1"); + } + fall_transition (inslew_load_5x5__0) { + values ("39.4, 39.4, 39.4, 44.1, 52.8", \ + "52.2, 52.2, 52.2, 56.9, 65.9", \ + "76.2, 76.2, 76.2, 80.9, 90.1", \ + "123.8, 123.8, 123.8, 128.5, 137.8", \ + "217.1, 217.1, 217.1, 222.1, 231.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("348.2, 348.2, 348.2, 385.7, 460.6", \ + "448.7, 448.7, 448.7, 486.2, 561.1", \ + "645.8, 645.8, 645.8, 683.3, 758.2", \ + "1036.4, 1036.4, 1036.4, 1073.9, 1148.8", \ + "1815.4, 1815.4, 1815.4, 1852.9, 1927.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("561.9, 561.9, 561.9, 599.4, 674.3", \ + "641.9, 641.9, 641.9, 679.4, 754.3", \ + "797.8, 797.8, 797.8, 835.3, 910.2", \ + "1110.4, 1110.4, 1110.4, 1147.8, 1222.8", \ + "1738.4, 1738.4, 1738.4, 1775.9, 1850.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("294.8, 294.8, 294.8, 332.3, 407.2", \ + "359.6, 359.6, 359.6, 397.0, 472.0", \ + "484.5, 484.5, 484.5, 522.0, 596.9", \ + "730.4, 730.4, 730.4, 767.9, 842.8", \ + "1218.5, 1218.5, 1218.5, 1256.0, 1330.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("458.5, 458.5, 458.5, 496.0, 570.9", \ + "545.9, 545.9, 545.9, 583.3, 658.3", \ + "717.7, 717.7, 717.7, 755.2, 830.1", \ + "1061.8, 1061.8, 1061.8, 1099.3, 1174.2", \ + "1745.0, 1745.0, 1745.0, 1782.5, 1857.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("236.8, 236.8, 236.8, 274.3, 349.2", \ + "284.3, 284.3, 284.3, 321.8, 396.7", \ + "375.2, 375.2, 375.2, 412.7, 487.6", \ + "552.2, 552.2, 552.2, 589.7, 664.6", \ + "902.6, 902.6, 902.6, 940.1, 1015.0"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("331.6, 331.6, 331.6, 369.1, 444.0", \ + "421.9, 421.9, 421.9, 459.4, 534.3", \ + "597.4, 597.4, 597.4, 634.9, 709.8", \ + "946.8, 946.8, 946.8, 984.3, 1059.2", \ + "1641.3, 1641.3, 1641.3, 1678.8, 1753.7"); + } + } + } + } + + cell (o3_x4) { + area : 0.0 ; + cell_leakage_power : 1.9 ; + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 0.88 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2)) | (i1 & !(i2)))" ; + value : 0.98 ; + } + leakage_power () { + when : "(!((i0 & !(i1))) & i2)" ; + value : 2.6 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 3.2 ; + } + pin (i2) { + direction : input ; + capacitance : 5.17 ; + } + pin (i1) { + direction : input ; + capacitance : 5.02 ; + } + pin (i0) { + direction : input ; + capacitance : 5.02 ; + } + pin (q) { + function : "(i0 | i1 | i2)" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("74.8, 74.8, 74.8, 80.6, 91.2", \ + "92.1, 92.1, 92.1, 98.0, 109.1", \ + "119.0, 119.0, 119.0, 125.1, 136.6", \ + "165.5, 165.5, 165.5, 171.8, 183.8", \ + "252.8, 252.8, 252.8, 259.2, 271.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("44.7, 44.7, 44.7, 52.3, 67.4", \ + "59.9, 59.9, 59.9, 67.6, 82.7", \ + "88.1, 88.1, 88.1, 95.9, 111.2", \ + "142.4, 142.4, 142.4, 150.2, 165.6", \ + "249.4, 249.4, 249.4, 257.1, 272.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("133.3, 133.3, 133.3, 139.3, 150.6", \ + "131.0, 131.0, 131.0, 137.0, 148.6", \ + "125.3, 125.3, 125.3, 131.3, 143.1", \ + "115.0, 115.0, 115.0, 120.6, 132.3", \ + "93.6, 93.6, 93.6, 99.2, 110.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("83.9, 83.9, 83.9, 87.5, 94.7", \ + "94.4, 94.4, 94.4, 98.1, 105.4", \ + "114.4, 114.4, 114.4, 118.1, 125.3", \ + "154.2, 154.2, 154.2, 158.1, 165.3", \ + "234.7, 234.7, 234.7, 238.5, 246.2"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("68.1, 68.1, 68.1, 73.9, 84.3", \ + "77.9, 77.9, 77.9, 83.8, 94.7", \ + "88.7, 88.7, 88.7, 94.8, 106.1", \ + "101.0, 101.0, 101.0, 107.3, 119.0", \ + "116.8, 116.8, 116.8, 123.2, 135.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("40.7, 40.7, 40.7, 48.4, 63.3", \ + "52.5, 52.5, 52.5, 60.2, 75.2", \ + "73.8, 73.8, 73.8, 81.5, 96.7", \ + "113.6, 113.6, 113.6, 121.3, 136.7", \ + "190.9, 190.9, 190.9, 198.6, 214.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("117.2, 117.2, 117.2, 123.1, 134.2", \ + "123.7, 123.7, 123.7, 129.7, 141.0", \ + "133.5, 133.5, 133.5, 139.6, 151.2", \ + "151.3, 151.3, 151.3, 156.8, 168.6", \ + "183.6, 183.6, 183.6, 189.2, 200.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("71.0, 71.0, 71.0, 74.7, 81.9", \ + "82.8, 82.8, 82.8, 86.5, 93.7", \ + "105.9, 105.9, 105.9, 109.5, 116.7", \ + "151.9, 151.9, 151.9, 155.8, 163.1", \ + "243.1, 243.1, 243.1, 246.9, 254.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("59.3, 59.3, 59.3, 65.0, 75.3", \ + "64.5, 64.5, 64.5, 70.4, 81.0", \ + "66.1, 66.1, 66.1, 72.1, 83.3", \ + "58.9, 58.9, 58.9, 65.1, 76.6", \ + "34.5, 34.5, 34.5, 40.8, 53.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("35.7, 35.7, 35.7, 43.3, 58.3", \ + "45.7, 45.7, 45.7, 53.4, 68.4", \ + "63.5, 63.5, 63.5, 71.2, 86.3", \ + "95.8, 95.8, 95.8, 103.6, 118.9", \ + "157.5, 157.5, 157.5, 165.2, 180.7"); + } + cell_fall (inslew_load_5x5__1) { + values ("93.5, 93.5, 93.5, 99.4, 109.8", \ + "106.2, 106.2, 106.2, 112.2, 123.1", \ + "126.9, 126.9, 126.9, 132.9, 144.5", \ + "163.2, 163.2, 163.2, 168.8, 180.6", \ + "230.9, 230.9, 230.9, 236.6, 247.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("54.9, 54.9, 54.9, 58.6, 65.7", \ + "67.8, 67.8, 67.8, 71.4, 78.6", \ + "92.6, 92.6, 92.6, 96.3, 103.6", \ + "141.6, 141.6, 141.6, 145.4, 152.7", \ + "238.6, 238.6, 238.6, 242.4, 250.1"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("557.2, 557.2, 557.2, 616.8, 736.0", \ + "698.0, 698.0, 698.0, 757.6, 876.8", \ + "971.5, 971.5, 971.5, 1031.1, 1150.3", \ + "1510.3, 1510.3, 1510.3, 1569.9, 1689.0", \ + "2581.5, 2581.5, 2581.5, 2641.1, 2760.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("987.5, 987.5, 987.5, 1047.1, 1166.3", \ + "1104.3, 1104.3, 1104.3, 1163.9, 1283.1", \ + "1330.5, 1330.5, 1330.5, 1390.1, 1509.3", \ + "1782.8, 1782.8, 1782.8, 1842.4, 1961.6", \ + "2694.8, 2694.8, 2694.8, 2754.4, 2873.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("493.6, 493.6, 493.6, 553.2, 672.4", \ + "589.6, 589.6, 589.6, 649.2, 768.4", \ + "772.8, 772.8, 772.8, 832.4, 951.6", \ + "1127.8, 1127.8, 1127.8, 1187.4, 1306.5", \ + "1827.6, 1827.6, 1827.6, 1887.2, 2006.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("839.9, 839.9, 839.9, 899.5, 1018.7", \ + "967.9, 967.9, 967.9, 1027.5, 1146.7", \ + "1219.5, 1219.5, 1219.5, 1279.1, 1398.3", \ + "1725.7, 1725.7, 1725.7, 1785.3, 1904.5", \ + "2731.8, 2731.8, 2731.8, 2791.4, 2910.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("423.3, 423.3, 423.3, 482.9, 602.1", \ + "497.7, 497.7, 497.7, 557.3, 676.5", \ + "637.2, 637.2, 637.2, 696.7, 815.9", \ + "903.6, 903.6, 903.6, 963.2, 1082.4", \ + "1423.6, 1423.6, 1423.6, 1483.2, 1602.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("656.7, 656.7, 656.7, 716.3, 835.5", \ + "791.3, 791.3, 791.3, 850.9, 970.1", \ + "1053.7, 1053.7, 1053.7, 1113.3, 1232.5", \ + "1575.3, 1575.3, 1575.3, 1634.9, 1754.1", \ + "2613.4, 2613.4, 2613.4, 2673.0, 2792.2"); + } + } + } + } + + cell (o4_x2) { + area : 0.0 ; + cell_leakage_power : 1.2 ; + leakage_power () { + when : "(i0 & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3))))" ; + value : 0.87 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & i0)" ; + value : 0.84 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & i1 & !(i0))" ; + value : 0.88 ; + } + leakage_power () { + when : "((i0 & ((i1 & (i2 ^ i3)) | (!(i1) & i2 & i3))) | (!(i0) & ((i1 & (i2 ^ i3)) | (i2 & !(i3)))))" ; + value : 0.98 ; + } + leakage_power () { + when : "((!(i0) & ((!(i1) & (!(i2) | i3)) | (i2 & i3))) | (i1 & i2 & i3))" ; + value : 2.6 ; + } + pin (i3) { + direction : input ; + capacitance : 5.02 ; + } + pin (i2) { + direction : input ; + capacitance : 5.02 ; + } + pin (i1) { + direction : input ; + capacitance : 5.00 ; + } + pin (i0) { + direction : input ; + capacitance : 4.84 ; + } + pin (q) { + function : "(i0 | i1 | i2 | i3)" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("67.1, 67.1, 67.1, 74.2, 86.8", \ + "83.3, 83.3, 83.3, 90.7, 103.9", \ + "108.9, 108.9, 108.9, 116.4, 130.5", \ + "153.8, 153.8, 153.8, 161.6, 176.4", \ + "239.0, 239.0, 239.0, 247.0, 262.5"); + } + rise_transition (inslew_load_5x5__0) { + values ("40.9, 40.9, 40.9, 50.5, 69.2", \ + "56.0, 56.0, 56.0, 65.6, 84.5", \ + "83.7, 83.7, 83.7, 93.5, 112.5", \ + "137.1, 137.1, 137.1, 146.8, 166.2", \ + "242.3, 242.3, 242.3, 252.0, 271.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("178.8, 178.8, 178.8, 186.4, 200.7", \ + "179.3, 179.3, 179.3, 186.9, 201.3", \ + "178.0, 178.0, 178.0, 185.4, 200.0", \ + "175.9, 175.9, 175.9, 183.2, 197.7", \ + "173.8, 173.8, 173.8, 181.1, 195.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("106.3, 106.3, 106.3, 111.0, 120.5", \ + "119.6, 119.6, 119.6, 124.4, 133.7", \ + "144.7, 144.7, 144.7, 149.6, 159.0", \ + "193.5, 193.5, 193.5, 198.5, 208.1", \ + "290.9, 290.9, 290.9, 295.8, 305.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("61.4, 61.4, 61.4, 68.4, 80.8", \ + "69.9, 69.9, 69.9, 77.1, 90.1", \ + "79.2, 79.2, 79.2, 86.6, 100.4", \ + "89.5, 89.5, 89.5, 97.2, 111.6", \ + "103.1, 103.1, 103.1, 111.0, 126.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("37.6, 37.6, 37.6, 47.1, 65.8", \ + "49.1, 49.1, 49.1, 58.7, 77.5", \ + "70.0, 70.0, 70.0, 79.6, 98.6", \ + "109.0, 109.0, 109.0, 118.8, 138.0", \ + "184.8, 184.8, 184.8, 194.5, 214.0"); + } + cell_fall (inslew_load_5x5__0) { + values ("156.6, 156.6, 156.6, 164.0, 178.1", \ + "164.8, 164.8, 164.8, 172.3, 186.7", \ + "177.1, 177.1, 177.1, 184.6, 199.2", \ + "201.1, 201.1, 201.1, 208.4, 222.9", \ + "249.0, 249.0, 249.0, 256.3, 270.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("91.1, 91.1, 91.1, 95.8, 105.1", \ + "105.9, 105.9, 105.9, 110.7, 120.1", \ + "133.1, 133.1, 133.1, 138.0, 147.4", \ + "186.5, 186.5, 186.5, 191.5, 201.0", \ + "293.6, 293.6, 293.6, 298.5, 308.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("55.8, 55.8, 55.8, 62.8, 75.1", \ + "60.4, 60.4, 60.4, 67.5, 80.3", \ + "60.7, 60.7, 60.7, 68.1, 81.6", \ + "52.0, 52.0, 52.0, 59.6, 73.8", \ + "25.9, 25.9, 25.9, 33.8, 48.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("34.5, 34.5, 34.5, 44.1, 62.7", \ + "44.5, 44.5, 44.5, 54.1, 72.8", \ + "61.8, 61.8, 61.8, 71.4, 90.4", \ + "93.4, 93.4, 93.4, 103.2, 122.3", \ + "153.9, 153.9, 153.9, 163.7, 183.1"); + } + cell_fall (inslew_load_5x5__0) { + values ("126.3, 126.3, 126.3, 133.6, 147.1", \ + "138.6, 138.6, 138.6, 146.0, 160.0", \ + "160.4, 160.4, 160.4, 167.9, 182.4", \ + "201.1, 201.1, 201.1, 208.3, 223.0", \ + "279.9, 279.9, 279.9, 287.2, 301.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("72.5, 72.5, 72.5, 77.2, 86.4", \ + "87.3, 87.3, 87.3, 92.0, 101.3", \ + "115.4, 115.4, 115.4, 120.1, 129.5", \ + "170.6, 170.6, 170.6, 175.6, 185.1", \ + "281.3, 281.3, 281.3, 286.2, 296.1"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("47.0, 47.0, 47.0, 53.8, 65.7", \ + "47.8, 47.8, 47.8, 54.8, 67.3", \ + "41.0, 41.0, 41.0, 48.3, 61.5", \ + "18.4, 18.4, 18.4, 25.8, 39.9", \ + "-36.1, -36.1, -36.1, -28.3, -13.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("29.7, 29.7, 29.7, 39.2, 57.7", \ + "38.5, 38.5, 38.5, 48.1, 66.7", \ + "53.4, 53.4, 53.4, 63.0, 81.9", \ + "80.0, 80.0, 80.0, 89.7, 108.8", \ + "130.3, 130.3, 130.3, 140.1, 159.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("91.7, 91.7, 91.7, 98.9, 111.5", \ + "106.1, 106.1, 106.1, 113.5, 126.7", \ + "135.0, 135.0, 135.0, 142.4, 156.6", \ + "189.1, 189.1, 189.1, 196.3, 211.1", \ + "293.8, 293.8, 293.8, 301.1, 315.4"); + } + fall_transition (inslew_load_5x5__0) { + values ("52.1, 52.1, 52.1, 56.8, 65.9", \ + "66.5, 66.5, 66.5, 71.3, 80.4", \ + "95.7, 95.7, 95.7, 100.4, 109.7", \ + "152.2, 152.2, 152.2, 157.1, 166.5", \ + "264.6, 264.6, 264.6, 269.6, 279.5"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("376.6, 376.6, 376.6, 414.1, 489.0", \ + "477.3, 477.3, 477.3, 514.8, 589.7", \ + "674.5, 674.5, 674.5, 712.0, 786.9", \ + "1065.3, 1065.3, 1065.3, 1102.8, 1177.7", \ + "1844.5, 1844.5, 1844.5, 1882.0, 1956.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("772.8, 772.8, 772.8, 810.2, 885.2", \ + "864.3, 864.3, 864.3, 901.8, 976.7", \ + "1043.0, 1043.0, 1043.0, 1080.4, 1155.4", \ + "1395.2, 1395.2, 1395.2, 1432.7, 1507.6", \ + "2098.4, 2098.4, 2098.4, 2135.8, 2210.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("330.3, 330.3, 330.3, 367.7, 442.7", \ + "395.2, 395.2, 395.2, 432.6, 507.6", \ + "520.8, 520.8, 520.8, 558.3, 633.2", \ + "767.4, 767.4, 767.4, 804.9, 879.8", \ + "1256.1, 1256.1, 1256.1, 1293.5, 1368.5"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("665.3, 665.3, 665.3, 702.8, 777.7", \ + "765.0, 765.0, 765.0, 802.5, 877.4", \ + "955.8, 955.8, 955.8, 993.3, 1068.2", \ + "1334.0, 1334.0, 1334.0, 1371.5, 1446.4", \ + "2091.4, 2091.4, 2091.4, 2128.9, 2203.8"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("293.8, 293.8, 293.8, 331.2, 406.2", \ + "342.2, 342.2, 342.2, 379.6, 454.6", \ + "434.5, 434.5, 434.5, 471.9, 546.9", \ + "613.0, 613.0, 613.0, 650.5, 725.4", \ + "964.7, 964.7, 964.7, 1002.1, 1077.1"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("532.5, 532.5, 532.5, 570.0, 644.9", \ + "630.9, 630.9, 630.9, 668.3, 743.3", \ + "822.4, 822.4, 822.4, 859.9, 934.8", \ + "1203.3, 1203.3, 1203.3, 1240.7, 1315.7", \ + "1965.1, 1965.1, 1965.1, 2002.6, 2077.5"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("241.7, 241.7, 241.7, 279.2, 354.1", \ + "279.8, 279.8, 279.8, 317.3, 392.2", \ + "351.4, 351.4, 351.4, 388.8, 463.8", \ + "488.3, 488.3, 488.3, 525.8, 600.7", \ + "756.8, 756.8, 756.8, 794.3, 869.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("388.9, 388.9, 388.9, 426.4, 501.3", \ + "484.3, 484.3, 484.3, 521.8, 596.7", \ + "676.4, 676.4, 676.4, 713.9, 788.8", \ + "1055.3, 1055.3, 1055.3, 1092.7, 1167.7", \ + "1811.6, 1811.6, 1811.6, 1849.1, 1924.0"); + } + } + } + } + + cell (o4_x4) { + area : 0.0 ; + cell_leakage_power : 1.6 ; + leakage_power () { + when : "(!(i3) & !(i2) & i1 & i0)" ; + value : 0.87 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & i0)" ; + value : 0.84 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3)) | (!(i0) & i1 & !(i2) & !(i3)))" ; + value : 0.88 ; + } + leakage_power () { + when : "((i0 & ((i1 & (i2 ^ i3)) | (!(i1) & i2 & i3))) | (!(i0) & ((i1 & (i2 ^ i3)) | (i2 & !(i3)))))" ; + value : 0.98 ; + } + leakage_power () { + when : "((!(i0) & !((i1 & !(i2))) & i3) | (i1 & i2 & i3))" ; + value : 2.6 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 3.2 ; + } + pin (i3) { + direction : input ; + capacitance : 5.02 ; + } + pin (i2) { + direction : input ; + capacitance : 5.02 ; + } + pin (i1) { + direction : input ; + capacitance : 5.00 ; + } + pin (i0) { + direction : input ; + capacitance : 4.84 ; + } + pin (q) { + function : "(i0 | i1 | i2 | i3)" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("78.8, 78.8, 78.8, 84.7, 95.4", \ + "96.4, 96.4, 96.4, 102.4, 113.6", \ + "123.9, 123.9, 123.9, 130.0, 141.5", \ + "170.8, 170.8, 170.8, 177.1, 189.2", \ + "258.3, 258.3, 258.3, 264.7, 277.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("47.0, 47.0, 47.0, 54.7, 69.8", \ + "62.2, 62.2, 62.2, 69.9, 85.0", \ + "90.4, 90.4, 90.4, 98.1, 113.4", \ + "144.7, 144.7, 144.7, 152.4, 167.8", \ + "251.5, 251.5, 251.5, 259.2, 274.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("212.4, 212.4, 212.4, 218.3, 230.0", \ + "213.5, 213.5, 213.5, 219.1, 231.0", \ + "213.4, 213.4, 213.4, 219.1, 230.6", \ + "212.9, 212.9, 212.9, 218.6, 229.6", \ + "213.8, 213.8, 213.8, 219.5, 230.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("128.3, 128.3, 128.3, 132.1, 139.4", \ + "141.9, 141.9, 141.9, 145.8, 153.1", \ + "168.0, 168.0, 168.0, 171.9, 179.4", \ + "218.8, 218.8, 218.8, 222.7, 230.5", \ + "319.9, 319.9, 319.9, 323.8, 331.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("73.4, 73.4, 73.4, 79.3, 89.8", \ + "83.8, 83.8, 83.8, 89.8, 100.7", \ + "95.7, 95.7, 95.7, 101.7, 113.1", \ + "108.9, 108.9, 108.9, 115.1, 126.9", \ + "125.3, 125.3, 125.3, 131.7, 144.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("43.8, 43.8, 43.8, 51.4, 66.5", \ + "55.5, 55.5, 55.5, 63.1, 78.2", \ + "76.8, 76.8, 76.8, 84.6, 99.8", \ + "116.8, 116.8, 116.8, 124.5, 139.9", \ + "194.1, 194.1, 194.1, 201.8, 217.2"); + } + cell_fall (inslew_load_5x5__1) { + values ("189.6, 189.6, 189.6, 195.6, 207.3", \ + "198.7, 198.7, 198.7, 204.5, 216.3", \ + "212.4, 212.4, 212.4, 218.0, 229.7", \ + "238.2, 238.2, 238.2, 243.8, 254.8", \ + "289.7, 289.7, 289.7, 295.5, 306.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("112.8, 112.8, 112.8, 116.5, 123.8", \ + "128.0, 128.0, 128.0, 131.8, 139.0", \ + "156.2, 156.2, 156.2, 160.1, 167.4", \ + "211.5, 211.5, 211.5, 215.3, 223.1", \ + "322.4, 322.4, 322.4, 326.2, 333.9"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("68.3, 68.3, 68.3, 74.2, 84.6", \ + "75.0, 75.0, 75.0, 81.0, 91.8", \ + "78.5, 78.5, 78.5, 84.5, 95.8", \ + "73.5, 73.5, 73.5, 79.7, 91.3", \ + "50.9, 50.9, 50.9, 57.2, 69.4"); + } + rise_transition (inslew_load_5x5__1) { + values ("40.8, 40.8, 40.8, 48.5, 63.5", \ + "50.9, 50.9, 50.9, 58.6, 73.7", \ + "68.9, 68.9, 68.9, 76.6, 91.8", \ + "101.7, 101.7, 101.7, 109.5, 124.8", \ + "163.7, 163.7, 163.7, 171.4, 186.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("158.9, 158.9, 158.9, 164.9, 176.5", \ + "172.0, 172.0, 172.0, 178.1, 189.8", \ + "195.6, 195.6, 195.6, 201.3, 213.1", \ + "238.9, 238.9, 238.9, 244.5, 255.7", \ + "321.9, 321.9, 321.9, 327.6, 338.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("93.7, 93.7, 93.7, 97.4, 104.7", \ + "108.9, 108.9, 108.9, 112.5, 119.8", \ + "137.7, 137.7, 137.7, 141.5, 148.8", \ + "194.8, 194.8, 194.8, 198.7, 206.3", \ + "309.4, 309.4, 309.4, 313.3, 321.0"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("60.1, 60.1, 60.1, 65.9, 76.2", \ + "63.7, 63.7, 63.7, 69.5, 80.2", \ + "60.8, 60.8, 60.8, 66.7, 77.8", \ + "42.3, 42.3, 42.3, 48.4, 59.9", \ + "-7.8, -7.8, -7.8, -1.5, 10.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("36.1, 36.1, 36.1, 43.8, 58.8", \ + "45.2, 45.2, 45.2, 52.9, 68.0", \ + "61.0, 61.0, 61.0, 68.7, 83.8", \ + "88.8, 88.8, 88.8, 96.6, 111.9", \ + "140.8, 140.8, 140.8, 148.5, 163.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("124.6, 124.6, 124.6, 130.5, 141.6", \ + "140.0, 140.0, 140.0, 146.0, 157.4", \ + "170.9, 170.9, 170.9, 176.8, 188.6", \ + "228.2, 228.2, 228.2, 233.8, 245.2", \ + "337.7, 337.7, 337.7, 343.4, 354.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("72.6, 72.6, 72.6, 76.3, 83.5", \ + "87.5, 87.5, 87.5, 91.1, 98.4", \ + "117.3, 117.3, 117.3, 121.0, 128.3", \ + "176.5, 176.5, 176.5, 180.4, 187.9", \ + "292.6, 292.6, 292.6, 296.4, 304.1"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("590.0, 590.0, 590.0, 649.6, 768.8", \ + "730.8, 730.8, 730.8, 790.4, 909.6", \ + "1004.7, 1004.7, 1004.7, 1064.3, 1183.5", \ + "1544.1, 1544.1, 1544.1, 1603.7, 1722.9", \ + "2615.7, 2615.7, 2615.7, 2675.3, 2794.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1372.8, 1372.8, 1372.8, 1432.4, 1551.6", \ + "1512.2, 1512.2, 1512.2, 1571.8, 1691.0", \ + "1784.1, 1784.1, 1784.1, 1843.7, 1962.9", \ + "2317.7, 2317.7, 2317.7, 2377.3, 2496.5", \ + "3381.1, 3381.1, 3381.1, 3440.7, 3559.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("535.2, 535.2, 535.2, 594.8, 714.0", \ + "631.2, 631.2, 631.2, 690.8, 810.0", \ + "815.4, 815.4, 815.4, 875.0, 994.2", \ + "1171.8, 1171.8, 1171.8, 1231.4, 1350.6", \ + "1872.7, 1872.7, 1872.7, 1932.3, 2051.5"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1210.6, 1210.6, 1210.6, 1270.2, 1389.4", \ + "1364.0, 1364.0, 1364.0, 1423.6, 1542.8", \ + "1655.1, 1655.1, 1655.1, 1714.7, 1833.9", \ + "2229.9, 2229.9, 2229.9, 2289.5, 2408.7", \ + "3381.8, 3381.8, 3381.8, 3441.4, 3560.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("491.1, 491.1, 491.1, 550.7, 669.9", \ + "566.6, 566.6, 566.6, 626.2, 745.4", \ + "708.4, 708.4, 708.4, 768.0, 887.2", \ + "978.0, 978.0, 978.0, 1037.6, 1156.8", \ + "1500.5, 1500.5, 1500.5, 1560.1, 1679.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1010.7, 1010.7, 1010.7, 1070.3, 1189.5", \ + "1162.3, 1162.3, 1162.3, 1221.9, 1341.1", \ + "1455.7, 1455.7, 1455.7, 1515.3, 1634.5", \ + "2039.0, 2039.0, 2039.0, 2098.6, 2217.8", \ + "3208.7, 3208.7, 3208.7, 3268.3, 3387.5"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("427.5, 427.5, 427.5, 487.0, 606.2", \ + "490.2, 490.2, 490.2, 549.8, 669.0", \ + "605.6, 605.6, 605.6, 665.2, 784.3", \ + "820.4, 820.4, 820.4, 880.0, 999.2", \ + "1233.0, 1233.0, 1233.0, 1292.6, 1411.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("793.1, 793.1, 793.1, 852.7, 971.9", \ + "940.5, 940.5, 940.5, 1000.1, 1119.3", \ + "1237.3, 1237.3, 1237.3, 1296.9, 1416.1", \ + "1828.9, 1828.9, 1828.9, 1888.5, 2007.7", \ + "2996.5, 2996.5, 2996.5, 3056.1, 3175.3"); + } + } + } + } + + cell (oa22_x2) { + area : 0.0 ; + cell_leakage_power : 0.75 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 0.52 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 0.4 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 0.27 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !(i2))" ; + value : 1.8 ; + } + pin (i2) { + direction : input ; + capacitance : 3.58 ; + } + pin (i1) { + direction : input ; + capacitance : 3.66 ; + } + pin (i0) { + direction : input ; + capacitance : 3.52 ; + } + pin (q) { + function : "((i1 & (i2 | i0)) | i2)" ; + direction : output ; + capacitance : 2.90 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__27) { + values ("54.6, 54.6, 54.6, 62.3, 76.0", \ + "53.7, 53.7, 53.7, 61.5, 75.6", \ + "45.5, 45.5, 45.5, 53.5, 68.1", \ + "20.9, 20.9, 20.9, 29.1, 44.4", \ + "-37.0, -37.0, -37.0, -28.7, -12.8"); + } + rise_transition (inslew_load_5x5__27) { + values ("42.6, 42.6, 42.6, 53.1, 73.7", \ + "50.9, 50.9, 50.9, 61.5, 82.1", \ + "66.0, 66.0, 66.0, 76.6, 97.3", \ + "93.9, 93.9, 93.9, 104.5, 125.5", \ + "147.0, 147.0, 147.0, 157.7, 178.9"); + } + cell_fall (inslew_load_5x5__27) { + values ("75.8, 75.8, 75.8, 83.1, 95.7", \ + "91.5, 91.5, 91.5, 99.2, 112.8", \ + "119.0, 119.0, 119.0, 126.4, 140.8", \ + "168.7, 168.7, 168.7, 176.5, 190.9", \ + "264.0, 264.0, 264.0, 271.9, 287.5"); + } + fall_transition (inslew_load_5x5__27) { + values ("42.7, 42.7, 42.7, 47.3, 56.1", \ + "56.4, 56.4, 56.4, 60.9, 69.8", \ + "81.6, 81.6, 81.6, 86.4, 95.5", \ + "131.1, 131.1, 131.1, 136.3, 146.0", \ + "229.3, 229.3, 229.3, 234.7, 245.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__27) { + values ("55.4, 55.4, 55.4, 63.0, 76.6", \ + "58.9, 58.9, 58.9, 66.7, 80.7", \ + "57.7, 57.7, 57.7, 65.7, 80.4", \ + "46.4, 46.4, 46.4, 54.6, 70.1", \ + "16.1, 16.1, 16.1, 24.5, 40.5"); + } + rise_transition (inslew_load_5x5__27) { + values ("39.7, 39.7, 39.7, 50.2, 70.7", \ + "50.3, 50.3, 50.3, 60.8, 81.5", \ + "68.9, 68.9, 68.9, 79.5, 100.3", \ + "102.9, 102.9, 102.9, 113.6, 134.6", \ + "168.0, 168.0, 168.0, 178.7, 200.0"); + } + cell_fall (inslew_load_5x5__27) { + values ("66.8, 66.8, 66.8, 73.9, 86.2", \ + "78.2, 78.2, 78.2, 85.7, 98.8", \ + "96.4, 96.4, 96.4, 103.8, 118.1", \ + "127.5, 127.5, 127.5, 135.3, 149.5", \ + "185.5, 185.5, 185.5, 193.4, 208.8"); + } + fall_transition (inslew_load_5x5__27) { + values ("37.5, 37.5, 37.5, 42.1, 50.8", \ + "48.8, 48.8, 48.8, 53.4, 62.3", \ + "70.4, 70.4, 70.4, 75.0, 84.1", \ + "111.7, 111.7, 111.7, 116.9, 126.3", \ + "193.7, 193.7, 193.7, 199.0, 209.2"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__27) { + values ("49.8, 49.8, 49.8, 57.3, 70.6", \ + "55.2, 55.2, 55.2, 63.0, 76.8", \ + "59.0, 59.0, 59.0, 67.0, 81.6", \ + "59.2, 59.2, 59.2, 67.4, 82.9", \ + "53.7, 53.7, 53.7, 62.1, 78.2"); + } + rise_transition (inslew_load_5x5__27) { + values ("33.6, 33.6, 33.6, 44.2, 64.6", \ + "45.5, 45.5, 45.5, 56.0, 76.6", \ + "66.3, 66.3, 66.3, 76.9, 97.7", \ + "104.7, 104.7, 104.7, 115.4, 136.4", \ + "178.8, 178.8, 178.8, 189.5, 210.8"); + } + cell_fall (inslew_load_5x5__27) { + values ("84.0, 84.0, 84.0, 91.5, 104.9", \ + "91.6, 91.6, 91.6, 99.2, 113.2", \ + "104.6, 104.6, 104.6, 112.0, 126.4", \ + "128.6, 128.6, 128.6, 136.5, 151.0", \ + "174.9, 174.9, 174.9, 182.8, 198.4"); + } + fall_transition (inslew_load_5x5__27) { + values ("51.6, 51.6, 51.6, 56.2, 65.1", \ + "63.9, 63.9, 63.9, 68.5, 77.5", \ + "87.4, 87.4, 87.4, 92.4, 101.5", \ + "134.5, 134.5, 134.5, 139.7, 149.4", \ + "228.7, 228.7, 228.7, 234.1, 244.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__27) { + values ("254.9, 254.9, 254.9, 291.2, 363.8", \ + "287.6, 287.6, 287.6, 323.9, 396.5", \ + "350.7, 350.7, 350.7, 387.0, 459.7", \ + "473.6, 473.6, 473.6, 509.9, 582.5", \ + "714.9, 714.9, 714.9, 751.2, 823.9"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("312.5, 312.5, 312.5, 348.8, 421.5", \ + "395.1, 395.1, 395.1, 431.4, 504.0", \ + "554.9, 554.9, 554.9, 591.2, 663.9", \ + "873.0, 873.0, 873.0, 909.3, 981.9", \ + "1506.7, 1506.7, 1506.7, 1543.0, 1615.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__27) { + values ("228.3, 228.3, 228.3, 264.6, 337.2", \ + "267.9, 267.9, 267.9, 304.3, 376.9", \ + "343.0, 343.0, 343.0, 379.3, 451.9", \ + "487.9, 487.9, 487.9, 524.2, 596.8", \ + "773.1, 773.1, 773.1, 809.5, 882.1"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("273.5, 273.5, 273.5, 309.8, 382.4", \ + "340.6, 340.6, 340.6, 376.9, 449.5", \ + "472.1, 472.1, 472.1, 508.4, 581.0", \ + "731.8, 731.8, 731.8, 768.1, 840.7", \ + "1249.1, 1249.1, 1249.1, 1285.4, 1358.1"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__27) { + values ("253.8, 253.8, 253.8, 290.2, 362.8", \ + "306.8, 306.8, 306.8, 343.1, 415.7", \ + "409.5, 409.5, 409.5, 445.8, 518.4", \ + "610.3, 610.3, 610.3, 646.6, 719.2", \ + "1008.7, 1008.7, 1008.7, 1045.0, 1117.7"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("375.0, 375.0, 375.0, 411.3, 483.9", \ + "456.2, 456.2, 456.2, 492.5, 565.2", \ + "616.8, 616.8, 616.8, 653.1, 725.7", \ + "938.1, 938.1, 938.1, 974.4, 1047.0", \ + "1581.6, 1581.6, 1581.6, 1617.9, 1690.6"); + } + } + } + } + + cell (oa22_x4) { + area : 0.0 ; + cell_leakage_power : 1.1 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 0.52 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 0.4 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 0.27 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !(i2))" ; + value : 3.2 ; + } + pin (i2) { + direction : input ; + capacitance : 3.43 ; + } + pin (i1) { + direction : input ; + capacitance : 3.70 ; + } + pin (i0) { + direction : input ; + capacitance : 3.54 ; + } + pin (q) { + function : "((i1 & (i2 | i0)) | i2)" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("71.1, 71.1, 71.1, 77.1, 87.9", \ + "71.7, 71.7, 71.7, 77.6, 88.7", \ + "65.8, 65.8, 65.8, 71.8, 83.1", \ + "43.2, 43.2, 43.2, 49.3, 60.8", \ + "-14.7, -14.7, -14.7, -8.4, 3.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("52.3, 52.3, 52.3, 60.0, 75.0", \ + "59.5, 59.5, 59.5, 67.1, 82.2", \ + "73.2, 73.2, 73.2, 80.9, 96.1", \ + "98.9, 98.9, 98.9, 106.7, 122.0", \ + "147.7, 147.7, 147.7, 155.4, 170.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("116.4, 116.4, 116.4, 122.4, 133.3", \ + "136.5, 136.5, 136.5, 142.4, 153.7", \ + "170.5, 170.5, 170.5, 176.6, 188.3", \ + "232.4, 232.4, 232.4, 237.9, 249.4", \ + "350.2, 350.2, 350.2, 355.7, 366.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("68.9, 68.9, 68.9, 72.5, 79.6", \ + "83.8, 83.8, 83.8, 87.5, 94.6", \ + "113.0, 113.0, 113.0, 116.5, 123.7", \ + "170.0, 170.0, 170.0, 173.9, 181.2", \ + "283.7, 283.7, 283.7, 287.4, 295.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("73.9, 73.9, 73.9, 79.9, 90.6", \ + "80.1, 80.1, 80.1, 86.1, 97.1", \ + "82.4, 82.4, 82.4, 88.4, 99.8", \ + "73.5, 73.5, 73.5, 79.7, 91.4", \ + "42.5, 42.5, 42.5, 48.8, 61.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("50.0, 50.0, 50.0, 57.6, 72.7", \ + "59.7, 59.7, 59.7, 67.3, 82.4", \ + "76.9, 76.9, 76.9, 84.7, 99.9", \ + "108.5, 108.5, 108.5, 116.2, 131.5", \ + "168.4, 168.4, 168.4, 176.1, 191.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("106.9, 106.9, 106.9, 112.9, 123.6", \ + "122.3, 122.3, 122.3, 128.3, 139.4", \ + "147.0, 147.0, 147.0, 153.0, 164.6", \ + "189.4, 189.4, 189.4, 194.9, 206.7", \ + "266.9, 266.9, 266.9, 272.4, 283.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("62.9, 62.9, 62.9, 66.5, 73.6", \ + "75.4, 75.4, 75.4, 79.1, 86.2", \ + "99.8, 99.8, 99.8, 103.5, 110.6", \ + "147.9, 147.9, 147.9, 151.7, 158.9", \ + "242.7, 242.7, 242.7, 246.5, 254.2"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("61.8, 61.8, 61.8, 67.6, 78.0", \ + "68.7, 68.7, 68.7, 74.6, 85.3", \ + "73.8, 73.8, 73.8, 79.8, 91.1", \ + "74.0, 74.0, 74.0, 80.2, 91.8", \ + "64.8, 64.8, 64.8, 71.1, 83.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("38.7, 38.7, 38.7, 46.4, 61.3", \ + "49.2, 49.2, 49.2, 56.9, 72.0", \ + "68.3, 68.3, 68.3, 76.0, 91.2", \ + "103.5, 103.5, 103.5, 111.3, 126.6", \ + "171.1, 171.1, 171.1, 178.8, 194.2"); + } + cell_fall (inslew_load_5x5__1) { + values ("125.7, 125.7, 125.7, 131.8, 143.0", \ + "136.1, 136.1, 136.1, 142.1, 153.6", \ + "154.5, 154.5, 154.5, 160.5, 172.2", \ + "188.9, 188.9, 188.9, 194.4, 205.9", \ + "255.7, 255.7, 255.7, 261.3, 272.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("78.5, 78.5, 78.5, 82.2, 89.3", \ + "92.3, 92.3, 92.3, 95.9, 103.1", \ + "119.3, 119.3, 119.3, 122.8, 130.0", \ + "173.2, 173.2, 173.2, 177.0, 184.4", \ + "281.8, 281.8, 281.8, 285.6, 293.2"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("508.8, 508.8, 508.8, 568.4, 687.6", \ + "560.3, 560.3, 560.3, 619.9, 739.1", \ + "661.5, 661.5, 661.5, 721.1, 840.3", \ + "856.0, 856.0, 856.0, 915.6, 1034.8", \ + "1232.5, 1232.5, 1232.5, 1292.1, 1411.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("746.4, 746.4, 746.4, 806.0, 925.2", \ + "889.7, 889.7, 889.7, 949.3, 1068.5", \ + "1170.7, 1170.7, 1170.7, 1230.3, 1349.5", \ + "1728.4, 1728.4, 1728.4, 1788.0, 1907.2", \ + "2840.3, 2840.3, 2840.3, 2899.9, 3019.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("476.6, 476.6, 476.6, 536.2, 655.4", \ + "543.0, 543.0, 543.0, 602.6, 721.8", \ + "666.9, 666.9, 666.9, 726.5, 845.7", \ + "900.2, 900.2, 900.2, 959.8, 1079.0", \ + "1351.4, 1351.4, 1351.4, 1411.0, 1530.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("682.1, 682.1, 682.1, 741.7, 860.9", \ + "800.8, 800.8, 800.8, 860.4, 979.6", \ + "1033.1, 1033.1, 1033.1, 1092.7, 1211.9", \ + "1494.7, 1494.7, 1494.7, 1554.3, 1673.5", \ + "2411.2, 2411.2, 2411.2, 2470.8, 2590.0"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("457.0, 457.0, 457.0, 516.6, 635.8", \ + "538.3, 538.3, 538.3, 597.9, 717.1", \ + "693.3, 693.3, 693.3, 752.9, 872.1", \ + "991.5, 991.5, 991.5, 1051.1, 1170.3", \ + "1575.4, 1575.4, 1575.4, 1635.0, 1754.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("847.7, 847.7, 847.7, 907.3, 1026.5", \ + "985.5, 985.5, 985.5, 1045.1, 1164.3", \ + "1257.6, 1257.6, 1257.6, 1317.2, 1436.4", \ + "1804.7, 1804.7, 1804.7, 1864.3, 1983.5", \ + "2904.2, 2904.2, 2904.2, 2963.8, 3083.0"); + } + } + } + } + + cell (oa2a22_x2) { + area : 0.0 ; + cell_leakage_power : 2.8 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 4.1 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3)" ; + value : 2.9 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 1.8 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!(i2) | !(i3)))" ; + value : 2.6 ; + } + pin (i3) { + direction : input ; + capacitance : 3.85 ; + } + pin (i2) { + direction : input ; + capacitance : 3.79 ; + } + pin (i1) { + direction : input ; + capacitance : 3.96 ; + } + pin (i0) { + direction : input ; + capacitance : 3.98 ; + } + pin (q) { + function : "((i0 & ((i3 & i2) | i1)) | (i3 & i2))" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("52.8, 52.8, 52.8, 59.9, 72.6", \ + "51.2, 51.2, 51.2, 58.4, 71.4", \ + "42.0, 42.0, 42.0, 49.4, 62.9", \ + "16.3, 16.3, 16.3, 23.8, 38.0", \ + "-42.8, -42.8, -42.8, -35.0, -20.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("41.3, 41.3, 41.3, 50.9, 69.6", \ + "49.0, 49.0, 49.0, 58.7, 77.4", \ + "63.4, 63.4, 63.4, 73.0, 92.0", \ + "90.3, 90.3, 90.3, 100.0, 119.1", \ + "142.0, 142.0, 142.0, 151.8, 171.1"); + } + cell_fall (inslew_load_5x5__0) { + values ("78.8, 78.8, 78.8, 85.8, 98.2", \ + "95.2, 95.2, 95.2, 102.5, 115.5", \ + "125.1, 125.1, 125.1, 132.5, 146.4", \ + "180.4, 180.4, 180.4, 187.7, 202.3", \ + "286.8, 286.8, 286.8, 294.1, 308.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("46.3, 46.3, 46.3, 50.9, 59.8", \ + "60.8, 60.8, 60.8, 65.5, 74.5", \ + "89.0, 89.0, 89.0, 93.7, 102.9", \ + "144.9, 144.9, 144.9, 149.7, 159.0", \ + "255.0, 255.0, 255.0, 259.9, 269.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("52.5, 52.5, 52.5, 59.5, 71.9", \ + "55.3, 55.3, 55.3, 62.5, 75.4", \ + "53.8, 53.8, 53.8, 61.2, 74.7", \ + "43.2, 43.2, 43.2, 50.8, 65.1", \ + "15.3, 15.3, 15.3, 23.1, 38.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("37.9, 37.9, 37.9, 47.5, 66.1", \ + "47.5, 47.5, 47.5, 57.1, 75.8", \ + "64.5, 64.5, 64.5, 74.2, 93.1", \ + "96.4, 96.4, 96.4, 106.1, 125.3", \ + "158.1, 158.1, 158.1, 167.8, 187.2"); + } + cell_fall (inslew_load_5x5__0) { + values ("69.1, 69.1, 69.1, 75.8, 88.1", \ + "80.2, 80.2, 80.2, 87.4, 99.9", \ + "100.1, 100.1, 100.1, 107.4, 121.0", \ + "133.2, 133.2, 133.2, 140.7, 155.2", \ + "196.0, 196.0, 196.0, 203.2, 217.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("40.6, 40.6, 40.6, 45.2, 53.9", \ + "52.2, 52.2, 52.2, 56.9, 66.0", \ + "75.9, 75.9, 75.9, 80.6, 89.7", \ + "121.7, 121.7, 121.7, 126.4, 135.7", \ + "211.9, 211.9, 211.9, 216.8, 226.5"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("66.8, 66.8, 66.8, 74.1, 87.1", \ + "71.7, 71.7, 71.7, 79.1, 92.6", \ + "76.8, 76.8, 76.8, 84.3, 98.3", \ + "80.8, 80.8, 80.8, 88.6, 103.2", \ + "83.5, 83.5, 83.5, 91.5, 106.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("51.0, 51.0, 51.0, 60.6, 79.5", \ + "61.9, 61.9, 61.9, 71.5, 90.4", \ + "83.0, 83.0, 83.0, 92.7, 111.8", \ + "123.8, 123.8, 123.8, 133.6, 152.9", \ + "204.3, 204.3, 204.3, 214.0, 233.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("98.7, 98.7, 98.7, 106.0, 119.0", \ + "107.1, 107.1, 107.1, 114.4, 127.9", \ + "121.2, 121.2, 121.2, 128.7, 142.9", \ + "148.0, 148.0, 148.0, 155.2, 170.0", \ + "199.9, 199.9, 199.9, 207.2, 221.3"); + } + fall_transition (inslew_load_5x5__0) { + values ("61.9, 61.9, 61.9, 66.6, 75.6", \ + "75.0, 75.0, 75.0, 79.7, 88.8", \ + "100.8, 100.8, 100.8, 105.4, 114.7", \ + "152.4, 152.4, 152.4, 157.3, 166.6", \ + "255.8, 255.8, 255.8, 260.7, 270.6"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("67.1, 67.1, 67.1, 74.3, 87.2", \ + "77.8, 77.8, 77.8, 85.2, 98.7", \ + "92.7, 92.7, 92.7, 100.2, 114.3", \ + "115.8, 115.8, 115.8, 123.5, 138.3", \ + "156.3, 156.3, 156.3, 164.3, 179.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("47.5, 47.5, 47.5, 57.1, 75.8", \ + "60.6, 60.6, 60.6, 70.2, 89.2", \ + "85.0, 85.0, 85.0, 94.7, 113.8", \ + "131.9, 131.9, 131.9, 141.7, 161.0", \ + "224.2, 224.2, 224.2, 233.9, 253.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("88.2, 88.2, 88.2, 95.4, 108.1", \ + "90.9, 90.9, 90.9, 98.2, 111.4", \ + "93.9, 93.9, 93.9, 101.3, 115.2", \ + "97.6, 97.6, 97.6, 105.2, 119.7", \ + "102.8, 102.8, 102.8, 110.1, 124.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("55.4, 55.4, 55.4, 60.1, 69.1", \ + "65.4, 65.4, 65.4, 70.1, 79.2", \ + "85.3, 85.3, 85.3, 90.0, 99.2", \ + "124.7, 124.7, 124.7, 129.5, 138.8", \ + "203.7, 203.7, 203.7, 208.6, 218.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("289.7, 289.7, 289.7, 327.2, 402.1", \ + "328.7, 328.7, 328.7, 366.2, 441.1", \ + "404.6, 404.6, 404.6, 442.0, 517.0", \ + "553.2, 553.2, 553.2, 590.6, 665.6", \ + "846.2, 846.2, 846.2, 883.7, 958.6"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("377.4, 377.4, 377.4, 414.9, 489.8", \ + "479.2, 479.2, 479.2, 516.7, 591.6", \ + "680.2, 680.2, 680.2, 717.6, 792.6", \ + "1081.0, 1081.0, 1081.0, 1118.5, 1193.4", \ + "1878.1, 1878.1, 1878.1, 1915.6, 1990.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("258.0, 258.0, 258.0, 295.5, 370.4", \ + "303.8, 303.8, 303.8, 341.3, 416.2", \ + "391.7, 391.7, 391.7, 429.1, 504.1", \ + "563.2, 563.2, 563.2, 600.7, 675.6", \ + "902.7, 902.7, 902.7, 940.1, 1015.1"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("328.8, 328.8, 328.8, 366.2, 441.2", \ + "409.5, 409.5, 409.5, 447.0, 521.9", \ + "572.3, 572.3, 572.3, 609.7, 684.7", \ + "892.4, 892.4, 892.4, 929.9, 1004.8", \ + "1529.8, 1529.8, 1529.8, 1567.2, 1642.2"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("370.1, 370.1, 370.1, 407.5, 482.5", \ + "435.7, 435.7, 435.7, 473.2, 548.1", \ + "566.3, 566.3, 566.3, 603.8, 678.7", \ + "825.1, 825.1, 825.1, 862.6, 937.5", \ + "1340.6, 1340.6, 1340.6, 1378.1, 1453.0"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("503.8, 503.8, 503.8, 541.2, 616.2", \ + "603.0, 603.0, 603.0, 640.4, 715.4", \ + "799.6, 799.6, 799.6, 837.1, 912.0", \ + "1194.1, 1194.1, 1194.1, 1231.6, 1306.5", \ + "1984.4, 1984.4, 1984.4, 2021.9, 2096.8"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("337.8, 337.8, 337.8, 375.3, 450.2", \ + "411.8, 411.8, 411.8, 449.3, 524.2", \ + "556.4, 556.4, 556.4, 593.9, 668.8", \ + "841.9, 841.9, 841.9, 879.4, 954.3", \ + "1409.9, 1409.9, 1409.9, 1447.3, 1522.3"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("449.6, 449.6, 449.6, 487.0, 562.0", \ + "523.6, 523.6, 523.6, 561.1, 636.0", \ + "671.5, 671.5, 671.5, 708.9, 783.9", \ + "966.3, 966.3, 966.3, 1003.8, 1078.7", \ + "1557.4, 1557.4, 1557.4, 1594.9, 1669.8"); + } + } + } + } + + cell (oa2a22_x4) { + area : 0.0 ; + cell_leakage_power : 4 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 6.1 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3)" ; + value : 4.3 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 2.5 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!(i2) | !(i3)))" ; + value : 3.2 ; + } + pin (i3) { + direction : input ; + capacitance : 4.28 ; + } + pin (i2) { + direction : input ; + capacitance : 4.23 ; + } + pin (i1) { + direction : input ; + capacitance : 4.39 ; + } + pin (i0) { + direction : input ; + capacitance : 4.41 ; + } + pin (q) { + function : "((i0 & ((i3 & i2) | i1)) | (i3 & i2))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("61.2, 61.2, 61.2, 67.1, 77.7", \ + "60.1, 60.1, 60.1, 66.1, 77.0", \ + "51.6, 51.6, 51.6, 57.5, 68.8", \ + "25.1, 25.1, 25.1, 31.2, 42.7", \ + "-38.5, -38.5, -38.5, -32.2, -20.1"); + } + rise_transition (inslew_load_5x5__1) { + values ("46.0, 46.0, 46.0, 53.7, 68.7", \ + "53.3, 53.3, 53.3, 61.0, 76.0", \ + "67.1, 67.1, 67.1, 74.8, 90.0", \ + "92.8, 92.8, 92.8, 100.6, 115.9", \ + "141.7, 141.7, 141.7, 149.4, 164.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("100.0, 100.0, 100.0, 105.9, 116.6", \ + "119.2, 119.2, 119.2, 125.2, 136.3", \ + "153.1, 153.1, 153.1, 159.2, 170.9", \ + "216.4, 216.4, 216.4, 222.0, 233.5", \ + "337.6, 337.6, 337.6, 343.3, 354.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("59.9, 59.9, 59.9, 63.6, 70.7", \ + "75.6, 75.6, 75.6, 79.3, 86.4", \ + "106.4, 106.4, 106.4, 110.0, 117.2", \ + "166.9, 166.9, 166.9, 170.8, 178.2", \ + "287.0, 287.0, 287.0, 290.8, 298.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("61.7, 61.7, 61.7, 67.6, 78.1", \ + "65.5, 65.5, 65.5, 71.5, 82.3", \ + "64.8, 64.8, 64.8, 70.8, 82.1", \ + "53.3, 53.3, 53.3, 59.5, 71.0", \ + "20.4, 20.4, 20.4, 26.8, 38.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("42.9, 42.9, 42.9, 50.6, 65.6", \ + "52.1, 52.1, 52.1, 59.8, 74.8", \ + "68.7, 68.7, 68.7, 76.5, 91.6", \ + "99.5, 99.5, 99.5, 107.3, 122.6", \ + "158.5, 158.5, 158.5, 166.2, 181.6"); + } + cell_fall (inslew_load_5x5__1) { + values ("89.9, 89.9, 89.9, 95.8, 106.2", \ + "103.6, 103.6, 103.6, 109.6, 120.5", \ + "127.0, 127.0, 127.0, 133.0, 144.6", \ + "168.1, 168.1, 168.1, 173.7, 185.5", \ + "244.1, 244.1, 244.1, 249.7, 260.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("53.6, 53.6, 53.6, 57.3, 64.4", \ + "66.5, 66.5, 66.5, 70.2, 77.3", \ + "91.9, 91.9, 91.9, 95.5, 102.8", \ + "142.0, 142.0, 142.0, 145.9, 153.2", \ + "240.7, 240.7, 240.7, 244.5, 252.2"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("73.2, 73.2, 73.2, 79.2, 90.1", \ + "77.2, 77.2, 77.2, 83.2, 94.4", \ + "79.7, 79.7, 79.7, 85.8, 97.2", \ + "76.8, 76.8, 76.8, 83.1, 94.9", \ + "63.2, 63.2, 63.2, 69.5, 81.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("54.5, 54.5, 54.5, 62.1, 77.2", \ + "64.1, 64.1, 64.1, 71.8, 87.0", \ + "83.1, 83.1, 83.1, 90.8, 106.1", \ + "119.7, 119.7, 119.7, 127.4, 142.8", \ + "191.2, 191.2, 191.2, 198.9, 214.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("122.2, 122.2, 122.2, 128.2, 139.4", \ + "133.9, 133.9, 133.9, 139.9, 151.5", \ + "155.0, 155.0, 155.0, 160.8, 172.6", \ + "195.0, 195.0, 195.0, 200.5, 211.9", \ + "273.4, 273.4, 273.4, 279.1, 290.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("77.3, 77.3, 77.3, 81.0, 88.2", \ + "92.7, 92.7, 92.7, 96.4, 103.7", \ + "122.6, 122.6, 122.6, 126.3, 133.6", \ + "182.4, 182.4, 182.4, 186.3, 193.8", \ + "302.6, 302.6, 302.6, 306.4, 314.1"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("74.7, 74.7, 74.7, 80.7, 91.5", \ + "85.5, 85.5, 85.5, 91.5, 102.7", \ + "99.6, 99.6, 99.6, 105.7, 117.2", \ + "119.4, 119.4, 119.4, 125.7, 137.7", \ + "151.6, 151.6, 151.6, 157.9, 170.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("51.6, 51.6, 51.6, 59.2, 74.3", \ + "64.1, 64.1, 64.1, 71.8, 86.9", \ + "87.4, 87.4, 87.4, 95.2, 110.4", \ + "132.2, 132.2, 132.2, 139.9, 155.3", \ + "219.9, 219.9, 219.9, 227.5, 242.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("109.9, 109.9, 109.9, 115.9, 126.8", \ + "114.3, 114.3, 114.3, 120.3, 131.5", \ + "120.6, 120.6, 120.6, 126.7, 138.3", \ + "131.5, 131.5, 131.5, 137.0, 148.8", \ + "150.0, 150.0, 150.0, 155.7, 166.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("69.5, 69.5, 69.5, 73.2, 80.4", \ + "80.6, 80.6, 80.6, 84.3, 91.5", \ + "102.6, 102.6, 102.6, 106.3, 113.5", \ + "147.0, 147.0, 147.0, 150.8, 158.1", \ + "234.4, 234.4, 234.4, 238.3, 246.0"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("506.0, 506.0, 506.0, 565.6, 684.8", \ + "563.6, 563.6, 563.6, 623.2, 742.4", \ + "676.6, 676.6, 676.6, 736.2, 855.4", \ + "894.1, 894.1, 894.1, 953.7, 1072.9", \ + "1318.2, 1318.2, 1318.2, 1377.8, 1497.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("727.7, 727.7, 727.7, 787.3, 906.5", \ + "895.5, 895.5, 895.5, 955.1, 1074.3", \ + "1227.4, 1227.4, 1227.4, 1287.0, 1406.2", \ + "1887.0, 1887.0, 1887.0, 1946.6, 2065.8", \ + "3200.1, 3200.1, 3200.1, 3259.7, 3378.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("463.3, 463.3, 463.3, 522.9, 642.1", \ + "533.9, 533.9, 533.9, 593.5, 712.7", \ + "667.9, 667.9, 667.9, 727.5, 846.7", \ + "925.0, 925.0, 925.0, 984.6, 1103.8", \ + "1427.9, 1427.9, 1427.9, 1487.5, 1606.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("650.9, 650.9, 650.9, 710.5, 829.7", \ + "787.0, 787.0, 787.0, 846.6, 965.8", \ + "1055.9, 1055.9, 1055.9, 1115.5, 1234.7", \ + "1591.4, 1591.4, 1591.4, 1651.0, 1770.2", \ + "2652.8, 2652.8, 2652.8, 2712.4, 2831.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("607.2, 607.2, 607.2, 666.8, 786.0", \ + "694.5, 694.5, 694.5, 754.1, 873.3", \ + "868.4, 868.4, 868.4, 928.0, 1047.2", \ + "1210.7, 1210.7, 1210.7, 1270.3, 1389.5", \ + "1888.4, 1888.4, 1888.4, 1948.0, 2067.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("933.5, 933.5, 933.5, 993.1, 1112.3", \ + "1106.9, 1106.9, 1106.9, 1166.5, 1285.7", \ + "1448.1, 1448.1, 1448.1, 1507.7, 1626.8", \ + "2131.9, 2131.9, 2131.9, 2191.5, 2310.7", \ + "3503.9, 3503.9, 3503.9, 3563.5, 3682.6"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("569.0, 569.0, 569.0, 628.6, 747.8", \ + "677.6, 677.6, 677.6, 737.2, 856.4", \ + "888.0, 888.0, 888.0, 947.6, 1066.8", \ + "1300.8, 1300.8, 1300.8, 1360.4, 1479.6", \ + "2118.5, 2118.5, 2118.5, 2178.1, 2297.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("839.3, 839.3, 839.3, 898.9, 1018.1", \ + "963.2, 963.2, 963.2, 1022.7, 1141.9", \ + "1208.8, 1208.8, 1208.8, 1268.4, 1387.6", \ + "1704.7, 1704.7, 1704.7, 1764.3, 1883.5", \ + "2688.9, 2688.9, 2688.9, 2748.5, 2867.7"); + } + } + } + } + + cell (oa2a2a23_x2) { + area : 0.0 ; + cell_leakage_power : 1.6 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5))" ; + value : 1.8 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & i3) | (!(i4) & !(i5))))" ; + value : 2.1 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & !(i3) & i4 & i5) | (!(i2) & ((i3 & i4 & i5) | (!(i3) & (i4 ^ i5)))))) | (!(i1) & i2 & i3))) | (!(i0) & i1 & i2 & i3))" ; + value : 1.6 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5)" ; + value : 1.3 ; + } + leakage_power () { + when : "(((i0 | i1) & !(i2) & !(i3) & i4 & i5) | (!((i0 | i1)) & ((i2 & (i3 | (i4 & i5))) | (i3 & i4 & i5))))" ; + value : 1.1 ; + } + leakage_power () { + when : "(i5 & i4 & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 1 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !((i2 & i3)) & (!(i4) | !(i5)))" ; + value : 2.6 ; + } + pin (i5) { + direction : input ; + capacitance : 3.36 ; + } + pin (i4) { + direction : input ; + capacitance : 3.42 ; + } + pin (i3) { + direction : input ; + capacitance : 3.42 ; + } + pin (i2) { + direction : input ; + capacitance : 3.42 ; + } + pin (i1) { + direction : input ; + capacitance : 3.52 ; + } + pin (i0) { + direction : input ; + capacitance : 3.55 ; + } + pin (q) { + function : "((i1 & ((i3 & ((i4 & i5) | i2 | i0)) | (i4 & i5) | i0)) | (i3 & ((i4 & i5) | i2)) | (i4 & i5))" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("57.3, 57.3, 57.3, 64.4, 77.2", \ + "54.3, 54.3, 54.3, 61.5, 74.5", \ + "41.0, 41.0, 41.0, 48.4, 61.8", \ + "3.7, 3.7, 3.7, 11.2, 25.2", \ + "-84.4, -84.4, -84.4, -76.6, -62.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("43.3, 43.3, 43.3, 52.9, 71.6", \ + "49.2, 49.2, 49.2, 58.8, 77.6", \ + "60.2, 60.2, 60.2, 69.9, 88.8", \ + "80.1, 80.1, 80.1, 89.8, 108.8", \ + "116.6, 116.6, 116.6, 126.4, 145.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("123.5, 123.5, 123.5, 130.8, 144.2", \ + "149.6, 149.6, 149.6, 157.1, 171.1", \ + "189.9, 189.9, 189.9, 197.5, 212.0", \ + "275.1, 275.1, 275.1, 282.4, 296.9", \ + "442.0, 442.0, 442.0, 449.4, 463.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("71.7, 71.7, 71.7, 76.4, 85.5", \ + "91.7, 91.7, 91.7, 96.4, 105.7", \ + "124.2, 124.2, 124.2, 128.9, 138.3", \ + "192.7, 192.7, 192.7, 197.6, 207.2", \ + "328.1, 328.1, 328.1, 333.0, 342.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("59.0, 59.0, 59.0, 66.1, 78.7", \ + "60.2, 60.2, 60.2, 67.4, 80.3", \ + "52.5, 52.5, 52.5, 59.9, 73.4", \ + "25.2, 25.2, 25.2, 32.8, 46.9", \ + "-43.1, -43.1, -43.1, -35.3, -20.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("40.8, 40.8, 40.8, 50.4, 69.1", \ + "48.8, 48.8, 48.8, 58.4, 77.2", \ + "62.5, 62.5, 62.5, 72.2, 91.1", \ + "86.8, 86.8, 86.8, 96.5, 115.6", \ + "131.9, 131.9, 131.9, 141.7, 161.0"); + } + cell_fall (inslew_load_5x5__0) { + values ("110.3, 110.3, 110.3, 117.7, 130.8", \ + "131.4, 131.4, 131.4, 138.8, 152.5", \ + "161.4, 161.4, 161.4, 168.9, 183.3", \ + "226.1, 226.1, 226.1, 233.3, 248.0", \ + "351.7, 351.7, 351.7, 359.0, 373.3"); + } + fall_transition (inslew_load_5x5__0) { + values ("63.8, 63.8, 63.8, 68.6, 77.7", \ + "81.1, 81.1, 81.1, 85.8, 95.0", \ + "108.5, 108.5, 108.5, 113.2, 122.6", \ + "166.3, 166.3, 166.3, 171.3, 180.7", \ + "282.4, 282.4, 282.4, 287.3, 297.3"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("67.7, 67.7, 67.7, 75.0, 88.0", \ + "67.8, 67.8, 67.8, 75.1, 88.4", \ + "61.0, 61.0, 61.0, 68.4, 82.2", \ + "37.1, 37.1, 37.1, 44.7, 58.9", \ + "-22.6, -22.6, -22.6, -14.7, 0.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("50.4, 50.4, 50.4, 60.0, 78.9", \ + "57.5, 57.5, 57.5, 67.1, 86.0", \ + "70.9, 70.9, 70.9, 80.6, 99.6", \ + "96.1, 96.1, 96.1, 105.8, 125.0", \ + "143.8, 143.8, 143.8, 153.5, 172.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("170.8, 170.8, 170.8, 178.3, 192.5", \ + "191.8, 191.8, 191.8, 199.3, 213.8", \ + "229.3, 229.3, 229.3, 236.5, 251.3", \ + "301.4, 301.4, 301.4, 308.6, 323.0", \ + "441.2, 441.2, 441.2, 448.5, 462.9"); + } + fall_transition (inslew_load_5x5__0) { + values ("100.1, 100.1, 100.1, 104.8, 114.1", \ + "118.9, 118.9, 118.9, 123.6, 133.0", \ + "153.8, 153.8, 153.8, 158.7, 168.1", \ + "223.0, 223.0, 223.0, 227.9, 237.7", \ + "361.6, 361.6, 361.6, 366.5, 376.4"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("70.3, 70.3, 70.3, 77.5, 90.4", \ + "75.7, 75.7, 75.7, 83.1, 96.4", \ + "76.6, 76.6, 76.6, 84.0, 97.9", \ + "66.2, 66.2, 66.2, 73.9, 88.3", \ + "33.2, 33.2, 33.2, 41.1, 56.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("48.1, 48.1, 48.1, 57.7, 76.5", \ + "57.5, 57.5, 57.5, 67.2, 86.1", \ + "74.4, 74.4, 74.4, 84.0, 103.1", \ + "105.2, 105.2, 105.2, 114.9, 134.2", \ + "163.7, 163.7, 163.7, 173.4, 192.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("156.9, 156.9, 156.9, 164.4, 178.4", \ + "171.6, 171.6, 171.6, 179.2, 193.5", \ + "197.1, 197.1, 197.1, 204.5, 219.1", \ + "244.6, 244.6, 244.6, 251.9, 266.4", \ + "336.9, 336.9, 336.9, 344.2, 358.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("91.7, 91.7, 91.7, 96.4, 105.7", \ + "106.9, 106.9, 106.9, 111.6, 121.1", \ + "135.4, 135.4, 135.4, 140.2, 149.6", \ + "191.9, 191.9, 191.9, 196.9, 206.5", \ + "305.7, 305.7, 305.7, 310.6, 320.6"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("77.9, 77.9, 77.9, 85.2, 98.5", \ + "83.0, 83.0, 83.0, 90.4, 104.1", \ + "87.5, 87.5, 87.5, 95.1, 109.2", \ + "88.7, 88.7, 88.7, 96.5, 111.1", \ + "82.8, 82.8, 82.8, 90.7, 106.0"); + } + rise_transition (inslew_load_5x5__0) { + values ("57.5, 57.5, 57.5, 67.1, 86.0", \ + "67.1, 67.1, 67.1, 76.7, 95.7", \ + "86.0, 86.0, 86.0, 95.7, 114.9", \ + "122.7, 122.7, 122.7, 132.4, 151.7", \ + "194.4, 194.4, 194.4, 204.2, 223.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("200.0, 200.0, 200.0, 207.6, 222.1", \ + "215.2, 215.2, 215.2, 222.6, 237.2", \ + "241.6, 241.6, 241.6, 248.8, 263.4", \ + "293.1, 293.1, 293.1, 300.4, 314.5", \ + "396.5, 396.5, 396.5, 403.9, 418.3"); + } + fall_transition (inslew_load_5x5__0) { + values ("119.2, 119.2, 119.2, 124.0, 133.3", \ + "138.1, 138.1, 138.1, 143.0, 152.3", \ + "173.9, 173.9, 173.9, 178.8, 188.3", \ + "244.1, 244.1, 244.1, 249.0, 258.9", \ + "384.1, 384.1, 384.1, 389.1, 398.9"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("80.9, 80.9, 80.9, 88.2, 101.5", \ + "92.7, 92.7, 92.7, 100.1, 113.8", \ + "107.5, 107.5, 107.5, 115.0, 129.2", \ + "127.0, 127.0, 127.0, 134.8, 149.6", \ + "156.9, 156.9, 156.9, 164.8, 180.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("55.0, 55.0, 55.0, 64.7, 83.5", \ + "67.5, 67.5, 67.5, 77.2, 96.2", \ + "90.6, 90.6, 90.6, 100.3, 119.5", \ + "134.4, 134.4, 134.4, 144.2, 163.5", \ + "219.8, 219.8, 219.8, 229.5, 249.0"); + } + cell_fall (inslew_load_5x5__0) { + values ("184.1, 184.1, 184.1, 191.6, 206.0", \ + "191.3, 191.3, 191.3, 198.9, 213.3", \ + "202.5, 202.5, 202.5, 209.8, 224.5", \ + "224.6, 224.6, 224.6, 231.9, 246.3", \ + "269.2, 269.2, 269.2, 276.5, 290.8"); + } + fall_transition (inslew_load_5x5__0) { + values ("109.8, 109.8, 109.8, 114.5, 123.9", \ + "124.2, 124.2, 124.2, 129.0, 138.4", \ + "151.4, 151.4, 151.4, 156.4, 165.7", \ + "204.8, 204.8, 204.8, 209.7, 219.4", \ + "311.9, 311.9, 311.9, 316.8, 326.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("286.6, 286.6, 286.6, 324.1, 399.0", \ + "310.9, 310.9, 310.9, 348.4, 423.3", \ + "357.5, 357.5, 357.5, 395.0, 469.9", \ + "445.9, 445.9, 445.9, 483.3, 558.3", \ + "615.5, 615.5, 615.5, 652.9, 727.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("462.9, 462.9, 462.9, 500.4, 575.3", \ + "572.6, 572.6, 572.6, 610.1, 685.0", \ + "763.8, 763.8, 763.8, 801.2, 876.2", \ + "1160.8, 1160.8, 1160.8, 1198.3, 1273.2", \ + "1949.1, 1949.1, 1949.1, 1986.5, 2061.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("259.7, 259.7, 259.7, 297.2, 372.1", \ + "290.6, 290.6, 290.6, 328.0, 403.0", \ + "347.2, 347.2, 347.2, 384.7, 459.6", \ + "453.4, 453.4, 453.4, 490.9, 565.8", \ + "657.8, 657.8, 657.8, 695.3, 770.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("413.3, 413.3, 413.3, 450.7, 525.7", \ + "506.4, 506.4, 506.4, 543.9, 618.8", \ + "666.3, 666.3, 666.3, 703.8, 778.7", \ + "998.8, 998.8, 998.8, 1036.3, 1111.2", \ + "1665.8, 1665.8, 1665.8, 1703.3, 1778.2"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("341.2, 341.2, 341.2, 378.7, 453.6", \ + "373.9, 373.9, 373.9, 411.4, 486.3", \ + "438.2, 438.2, 438.2, 475.7, 550.6", \ + "563.2, 563.2, 563.2, 600.7, 675.6", \ + "806.8, 806.8, 806.8, 844.3, 919.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("630.6, 630.6, 630.6, 668.0, 743.0", \ + "739.3, 739.3, 739.3, 776.7, 851.7", \ + "947.5, 947.5, 947.5, 985.0, 1059.9", \ + "1361.5, 1361.5, 1361.5, 1399.0, 1473.9", \ + "2190.7, 2190.7, 2190.7, 2228.1, 2303.1"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("314.9, 314.9, 314.9, 352.4, 427.3", \ + "355.9, 355.9, 355.9, 393.3, 468.3", \ + "432.9, 432.9, 432.9, 470.4, 545.3", \ + "580.7, 580.7, 580.7, 618.1, 693.1", \ + "868.7, 868.7, 868.7, 906.2, 981.1"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("577.3, 577.3, 577.3, 614.8, 689.7", \ + "664.7, 664.7, 664.7, 702.2, 777.1", \ + "832.8, 832.8, 832.8, 870.2, 945.2", \ + "1168.3, 1168.3, 1168.3, 1205.8, 1280.7", \ + "1841.9, 1841.9, 1841.9, 1879.3, 1954.3"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__0) { + values ("397.3, 397.3, 397.3, 434.8, 509.7", \ + "450.4, 450.4, 450.4, 487.9, 562.8", \ + "556.5, 556.5, 556.5, 593.9, 668.9", \ + "766.0, 766.0, 766.0, 803.5, 878.4", \ + "1181.9, 1181.9, 1181.9, 1219.4, 1294.3"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("746.4, 746.4, 746.4, 783.8, 858.8", \ + "858.7, 858.7, 858.7, 896.1, 971.0", \ + "1075.7, 1075.7, 1075.7, 1113.2, 1188.1", \ + "1504.8, 1504.8, 1504.8, 1542.3, 1617.2", \ + "2361.8, 2361.8, 2361.8, 2399.3, 2474.2"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__0) { + values ("371.1, 371.1, 371.1, 408.6, 483.5", \ + "433.8, 433.8, 433.8, 471.3, 546.2", \ + "555.3, 555.3, 555.3, 592.8, 667.7", \ + "793.0, 793.0, 793.0, 830.5, 905.4", \ + "1263.0, 1263.0, 1263.0, 1300.5, 1375.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("686.6, 686.6, 686.6, 724.0, 799.0", \ + "771.8, 771.8, 771.8, 809.3, 884.2", \ + "936.3, 936.3, 936.3, 973.7, 1048.7", \ + "1261.2, 1261.2, 1261.2, 1298.7, 1373.6", \ + "1912.9, 1912.9, 1912.9, 1950.4, 2025.3"); + } + } + } + } + + cell (oa2a2a23_x4) { + area : 0.0 ; + cell_leakage_power : 5.1 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5))" ; + value : 7 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & i3) | (!(i4) & !(i5))))" ; + value : 8.1 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & !(i3) & i4 & i5) | (!(i2) & ((i3 & i4 & i5) | (!(i3) & (i4 ^ i5)))))) | (!(i1) & i2 & i3))) | (!(i0) & i1 & i2 & i3))" ; + value : 5.8 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5)" ; + value : 4.6 ; + } + leakage_power () { + when : "((i0 & i1 & !(i2) & !(i3) & i4 & i5) | (!(i0) & !(i1) & i2 & i3))" ; + value : 3.6 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & i4 & i5) | (!(i0) & ((i1 & !(i2) & !(i3) & i4 & i5) | (!(i1) & (i2 ^ i3) & i4 & i5))))" ; + value : 3.4 ; + } + leakage_power () { + when : "((!(i0) & ((!(i1) & ((!(i2) & (!(i3) | !(i4) | !(i5))) | (!(i3) & (!(i4) | !(i5))))) | (!((i2 & i3)) & (!(i4) | !(i5))))) | (!(i1) & !((i2 & i3)) & (!(i4) | !(i5))))" ; + value : 3.2 ; + } + pin (i5) { + direction : input ; + capacitance : 3.79 ; + } + pin (i4) { + direction : input ; + capacitance : 3.85 ; + } + pin (i3) { + direction : input ; + capacitance : 3.85 ; + } + pin (i2) { + direction : input ; + capacitance : 3.85 ; + } + pin (i1) { + direction : input ; + capacitance : 3.96 ; + } + pin (i0) { + direction : input ; + capacitance : 3.98 ; + } + pin (q) { + function : "((i1 & ((i2 & ((i4 & i5) | i3 | i0)) | (i4 & i5) | i0)) | (i2 & ((i4 & i5) | i3)) | (i4 & i5))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("72.9, 72.9, 72.9, 78.9, 89.8", \ + "76.0, 76.0, 76.0, 81.9, 93.1", \ + "76.4, 76.4, 76.4, 82.5, 93.9", \ + "69.1, 69.1, 69.1, 75.3, 87.1", \ + "46.3, 46.3, 46.3, 52.6, 64.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("54.7, 54.7, 54.7, 62.4, 77.5", \ + "64.0, 64.0, 64.0, 71.7, 86.8", \ + "82.1, 82.1, 82.1, 89.8, 105.1", \ + "116.9, 116.9, 116.9, 124.7, 140.1", \ + "184.9, 184.9, 184.9, 192.6, 208.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("140.4, 140.4, 140.4, 146.4, 157.8", \ + "154.9, 154.9, 154.9, 160.9, 172.5", \ + "174.9, 174.9, 174.9, 180.9, 192.6", \ + "216.4, 216.4, 216.4, 222.0, 233.6", \ + "292.1, 292.1, 292.1, 297.8, 308.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("85.9, 85.9, 85.9, 89.6, 96.9", \ + "99.5, 99.5, 99.5, 103.2, 110.4", \ + "121.7, 121.7, 121.7, 125.4, 132.7", \ + "170.0, 170.0, 170.0, 173.9, 181.3", \ + "267.8, 267.8, 267.8, 271.6, 279.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("70.4, 70.4, 70.4, 76.3, 87.0", \ + "73.2, 73.2, 73.2, 79.2, 90.2", \ + "69.1, 69.1, 69.1, 75.1, 86.5", \ + "47.5, 47.5, 47.5, 53.6, 65.2", \ + "-10.9, -10.9, -10.9, -4.6, 7.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("49.0, 49.0, 49.0, 56.7, 71.8", \ + "57.1, 57.1, 57.1, 64.8, 79.9", \ + "71.5, 71.5, 71.5, 79.3, 94.4", \ + "97.5, 97.5, 97.5, 105.3, 120.7", \ + "145.9, 145.9, 145.9, 153.7, 169.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("134.0, 134.0, 134.0, 140.0, 151.3", \ + "153.9, 153.9, 153.9, 160.0, 171.6", \ + "185.1, 185.1, 185.1, 191.0, 202.7", \ + "249.8, 249.8, 249.8, 255.4, 266.7", \ + "373.7, 373.7, 373.7, 379.4, 390.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("81.8, 81.8, 81.8, 85.5, 92.8", \ + "99.0, 99.0, 99.0, 102.6, 109.9", \ + "127.5, 127.5, 127.5, 131.3, 138.5", \ + "188.0, 188.0, 188.0, 191.9, 199.5", \ + "309.7, 309.7, 309.7, 313.6, 321.3"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("80.4, 80.4, 80.4, 86.4, 97.5", \ + "81.3, 81.3, 81.3, 87.2, 98.5", \ + "76.6, 76.6, 76.6, 82.7, 94.1", \ + "56.4, 56.4, 56.4, 62.6, 74.3", \ + "3.0, 3.0, 3.0, 9.4, 21.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("60.0, 60.0, 60.0, 67.7, 82.8", \ + "67.4, 67.4, 67.4, 75.1, 90.3", \ + "82.1, 82.1, 82.1, 89.9, 105.1", \ + "110.1, 110.1, 110.1, 117.8, 133.2", \ + "163.3, 163.3, 163.3, 171.0, 186.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("189.6, 189.6, 189.6, 195.6, 207.4", \ + "210.6, 210.6, 210.6, 216.4, 228.2", \ + "247.9, 247.9, 247.9, 253.5, 265.0", \ + "319.6, 319.6, 319.6, 325.2, 336.3", \ + "458.3, 458.3, 458.3, 464.1, 475.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("116.8, 116.8, 116.8, 120.5, 127.8", \ + "136.2, 136.2, 136.2, 140.1, 147.4", \ + "172.8, 172.8, 172.8, 176.7, 184.2", \ + "245.5, 245.5, 245.5, 249.3, 257.1", \ + "391.4, 391.4, 391.4, 395.2, 402.8"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("81.7, 81.7, 81.7, 87.7, 98.7", \ + "88.5, 88.5, 88.5, 94.5, 105.8", \ + "92.8, 92.8, 92.8, 98.9, 110.3", \ + "88.5, 88.5, 88.5, 94.7, 106.6", \ + "66.5, 66.5, 66.5, 72.8, 85.1"); + } + rise_transition (inslew_load_5x5__1) { + values ("56.9, 56.9, 56.9, 64.6, 79.7", \ + "66.4, 66.4, 66.4, 74.2, 89.3", \ + "84.3, 84.3, 84.3, 92.0, 107.3", \ + "117.4, 117.4, 117.4, 125.2, 140.6", \ + "180.8, 180.8, 180.8, 188.5, 203.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("175.7, 175.7, 175.7, 181.8, 193.5", \ + "189.8, 189.8, 189.8, 195.7, 207.4", \ + "214.1, 214.1, 214.1, 219.7, 231.5", \ + "259.0, 259.0, 259.0, 264.6, 275.6", \ + "345.3, 345.3, 345.3, 351.0, 362.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("108.1, 108.1, 108.1, 111.8, 119.1", \ + "123.5, 123.5, 123.5, 127.2, 134.5", \ + "152.5, 152.5, 152.5, 156.4, 163.8", \ + "210.7, 210.7, 210.7, 214.5, 222.3", \ + "328.1, 328.1, 328.1, 331.9, 339.6"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("91.7, 91.7, 91.7, 97.7, 109.0", \ + "98.2, 98.2, 98.2, 104.3, 115.7", \ + "105.9, 105.9, 105.9, 112.1, 123.6", \ + "113.4, 113.4, 113.4, 119.7, 131.8", \ + "119.4, 119.4, 119.4, 125.8, 138.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("68.2, 68.2, 68.2, 75.9, 91.1", \ + "78.9, 78.9, 78.9, 86.6, 101.8", \ + "99.9, 99.9, 99.9, 107.7, 123.0", \ + "141.5, 141.5, 141.5, 149.2, 164.6", \ + "223.2, 223.2, 223.2, 230.9, 246.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("216.3, 216.3, 216.3, 222.0, 233.8", \ + "230.2, 230.2, 230.2, 235.8, 247.6", \ + "254.6, 254.6, 254.6, 260.2, 271.4", \ + "302.0, 302.0, 302.0, 307.7, 318.8", \ + "397.4, 397.4, 397.4, 403.1, 414.4"); + } + fall_transition (inslew_load_5x5__1) { + values ("134.9, 134.9, 134.9, 138.8, 146.0", \ + "154.1, 154.1, 154.1, 158.1, 165.4", \ + "190.8, 190.8, 190.8, 194.7, 202.3", \ + "262.8, 262.8, 262.8, 266.6, 274.3", \ + "406.6, 406.6, 406.6, 410.4, 418.0"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("93.0, 93.0, 93.0, 99.0, 110.2", \ + "106.3, 106.3, 106.3, 112.4, 123.8", \ + "124.9, 124.9, 124.9, 131.1, 142.7", \ + "151.8, 151.8, 151.8, 158.1, 170.3", \ + "196.1, 196.1, 196.1, 202.5, 215.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("64.8, 64.8, 64.8, 72.5, 87.6", \ + "77.7, 77.7, 77.7, 85.5, 100.7", \ + "102.6, 102.6, 102.6, 110.4, 125.7", \ + "150.5, 150.5, 150.5, 158.2, 173.7", \ + "244.2, 244.2, 244.2, 251.9, 267.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("200.3, 200.3, 200.3, 206.2, 217.9", \ + "205.9, 205.9, 205.9, 211.6, 223.4", \ + "214.3, 214.3, 214.3, 219.9, 231.5", \ + "230.3, 230.3, 230.3, 236.0, 247.0", \ + "263.0, 263.0, 263.0, 268.7, 279.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("125.2, 125.2, 125.2, 128.9, 136.2", \ + "139.4, 139.4, 139.4, 143.3, 150.6", \ + "166.6, 166.6, 166.6, 170.5, 177.9", \ + "219.8, 219.8, 219.8, 223.7, 231.4", \ + "327.1, 327.1, 327.1, 330.9, 338.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("562.3, 562.3, 562.3, 621.9, 741.1", \ + "639.7, 639.7, 639.7, 699.3, 818.5", \ + "793.3, 793.3, 793.3, 852.9, 972.1", \ + "1095.0, 1095.0, 1095.0, 1154.6, 1273.8", \ + "1690.9, 1690.9, 1690.9, 1750.5, 1869.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("889.4, 889.4, 889.4, 949.0, 1068.2", \ + "1013.2, 1013.2, 1013.2, 1072.8, 1192.0", \ + "1226.7, 1226.7, 1226.7, 1286.3, 1405.5", \ + "1682.4, 1682.4, 1682.4, 1742.0, 1861.2", \ + "2602.8, 2602.8, 2602.8, 2662.4, 2781.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("492.4, 492.4, 492.4, 552.0, 671.2", \ + "548.1, 548.1, 548.1, 607.7, 726.9", \ + "652.2, 652.2, 652.2, 711.8, 831.0", \ + "846.6, 846.6, 846.6, 906.2, 1025.4", \ + "1217.3, 1217.3, 1217.3, 1276.9, 1396.1"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("852.5, 852.5, 852.5, 912.1, 1031.3", \ + "1010.3, 1010.3, 1010.3, 1069.9, 1189.1", \ + "1286.6, 1286.6, 1286.6, 1346.2, 1465.4", \ + "1865.0, 1865.0, 1865.0, 1924.6, 2043.8", \ + "3026.8, 3026.8, 3026.8, 3086.4, 3205.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("617.4, 617.4, 617.4, 677.0, 796.2", \ + "675.8, 675.8, 675.8, 735.4, 854.6", \ + "792.9, 792.9, 792.9, 852.5, 971.7", \ + "1019.9, 1019.9, 1019.9, 1079.5, 1198.7", \ + "1461.0, 1461.0, 1461.0, 1520.6, 1639.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1198.8, 1198.8, 1198.8, 1258.4, 1377.6", \ + "1386.8, 1386.8, 1386.8, 1446.4, 1565.6", \ + "1745.7, 1745.7, 1745.7, 1805.3, 1924.5", \ + "2461.0, 2461.0, 2461.0, 2520.6, 2639.8", \ + "3895.0, 3895.0, 3895.0, 3954.6, 4073.8"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("577.7, 577.7, 577.7, 637.3, 756.5", \ + "649.9, 649.9, 649.9, 709.5, 828.7", \ + "788.4, 788.4, 788.4, 848.0, 967.2", \ + "1053.6, 1053.6, 1053.6, 1113.2, 1232.3", \ + "1569.0, 1569.0, 1569.0, 1628.6, 1747.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1109.3, 1109.3, 1109.3, 1168.9, 1288.1", \ + "1257.1, 1257.1, 1257.1, 1316.7, 1435.9", \ + "1541.0, 1541.0, 1541.0, 1600.6, 1719.8", \ + "2109.2, 2109.2, 2109.2, 2168.8, 2288.0", \ + "3253.3, 3253.3, 3253.3, 3312.9, 3432.1"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__1) { + values ("708.6, 708.6, 708.6, 768.2, 887.4", \ + "802.9, 802.9, 802.9, 862.5, 981.7", \ + "990.4, 990.4, 990.4, 1050.0, 1169.2", \ + "1363.6, 1363.6, 1363.6, 1423.2, 1542.4", \ + "2103.5, 2103.5, 2103.5, 2163.1, 2282.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1380.7, 1380.7, 1380.7, 1440.3, 1559.5", \ + "1569.1, 1569.1, 1569.1, 1628.7, 1747.9", \ + "1933.2, 1933.2, 1933.2, 1992.8, 2112.0", \ + "2652.3, 2652.3, 2652.3, 2711.9, 2831.1", \ + "4089.1, 4089.1, 4089.1, 4148.7, 4267.9"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__1) { + values ("667.3, 667.3, 667.3, 726.9, 846.1", \ + "776.2, 776.2, 776.2, 835.8, 955.0", \ + "989.5, 989.5, 989.5, 1049.1, 1168.3", \ + "1407.3, 1407.3, 1407.3, 1466.9, 1586.1", \ + "2232.9, 2232.9, 2232.9, 2292.5, 2411.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1280.2, 1280.2, 1280.2, 1339.8, 1459.0", \ + "1419.5, 1419.5, 1419.5, 1479.1, 1598.3", \ + "1688.7, 1688.7, 1688.7, 1748.3, 1867.5", \ + "2219.5, 2219.5, 2219.5, 2279.1, 2398.3", \ + "3286.4, 3286.4, 3286.4, 3346.0, 3465.2"); + } + } + } + } + + cell (oa2a2a2a24_x2) { + area : 0.0 ; + cell_leakage_power : 23 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5) & (i6 ^ i7))" ; + value : 18 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 13 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5 & (i6 ^ i7))" ; + value : 25 ; + } + leakage_power () { + when : "(i2 & i3 & i4 & i5 & i6 & i7)" ; + value : 41 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & !((i4 & i5)) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & !((i4 & i5)) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (i2 & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))" ; + value : 28 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i2) & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i1) & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))) | (i2 & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 22 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))) | (!(i1) & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!((i2 & i3)) & i4 & i5 & !(i6) & !(i7)))))) | (!(i0) & ((i1 & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!((i2 & i3)) & i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))" ; + value : 15 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & ((!(i3) & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!(i4) & !(i5) & !(i6) & !(i7)))) | (!(i2) & ((i3 & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!(i3) & ((i4 & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i4) & ((i5 & (!(i6) | !(i7))) | (!(i5) & (i6 | i7)))))))))) | (i2 & i3 & !(i4) & !(i5) & !(i6) & !(i7)))" ; + value : 14 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i1) & (i2 ^ i3) & (i4 ^ i5) & i6 & i7))))" ; + value : 35 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & !(i2) & !(i3) & i4 & i5 & i6 & i7) | (!(i1) & ((i2 & !(i3) & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))))" ; + value : 29 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & !(i3) & i4 & i5 & i6 & i7))) | (i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i0) & ((!(i1) & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))))" ; + value : 16 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((!(i2) & ((!(i3) & i6 & i7) | (i4 & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7)))" ; + value : 42 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !((i2 & i3)) & !((i4 & i5)) & (!(i6) | !(i7)))" ; + value : 2.6 ; + } + pin (i7) { + direction : input ; + capacitance : 4.96 ; + } + pin (i6) { + direction : input ; + capacitance : 4.96 ; + } + pin (i5) { + direction : input ; + capacitance : 4.96 ; + } + pin (i4) { + direction : input ; + capacitance : 4.98 ; + } + pin (i3) { + direction : input ; + capacitance : 4.96 ; + } + pin (i2) { + direction : input ; + capacitance : 4.90 ; + } + pin (i1) { + direction : input ; + capacitance : 5.17 ; + } + pin (i0) { + direction : input ; + capacitance : 5.09 ; + } + pin (q) { + function : "((i7 & ((i4 & ((i2 & ((i1 & i0) | i3 | i5 | i6)) | (i1 & i0) | i5 | i6)) | (i2 & ((i1 & i0) | i3 | i6)) | (i1 & i0) | i6)) | (i4 & ((i2 & ((i1 & i0) | i3 | i5)) | (i1 & i0) | i5)) | (i2 & ((i1 & i0) | i3)) | (i1 & i0))" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("102.4, 102.4, 102.4, 109.8, 123.7", \ + "116.5, 116.5, 116.5, 124.0, 138.2", \ + "139.4, 139.4, 139.4, 147.2, 161.8", \ + "179.5, 179.5, 179.5, 187.4, 202.6", \ + "254.2, 254.2, 254.2, 262.2, 277.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("74.7, 74.7, 74.7, 84.4, 103.4", \ + "90.2, 90.2, 90.2, 99.9, 119.1", \ + "120.0, 120.0, 120.0, 129.8, 149.1", \ + "179.1, 179.1, 179.1, 188.9, 208.4", \ + "296.3, 296.3, 296.3, 306.1, 325.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("234.8, 234.8, 234.8, 242.3, 256.8", \ + "240.0, 240.0, 240.0, 247.3, 262.1", \ + "247.4, 247.4, 247.4, 254.7, 269.3", \ + "261.5, 261.5, 261.5, 268.9, 283.3", \ + "291.4, 291.4, 291.4, 298.8, 313.4"); + } + fall_transition (inslew_load_5x5__0) { + values ("137.1, 137.1, 137.1, 142.0, 151.4", \ + "152.4, 152.4, 152.4, 157.4, 166.8", \ + "182.0, 182.0, 182.0, 187.0, 196.6", \ + "239.7, 239.7, 239.7, 244.7, 254.6", \ + "354.4, 354.4, 354.4, 359.4, 369.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("101.9, 101.9, 101.9, 109.3, 123.1", \ + "123.7, 123.7, 123.7, 131.2, 145.4", \ + "158.9, 158.9, 158.9, 166.6, 181.2", \ + "220.8, 220.8, 220.8, 228.7, 244.0", \ + "337.8, 337.8, 337.8, 345.7, 361.4"); + } + rise_transition (inslew_load_5x5__0) { + values ("69.8, 69.8, 69.8, 79.5, 98.5", \ + "87.8, 87.8, 87.8, 97.6, 116.7", \ + "121.7, 121.7, 121.7, 131.5, 150.8", \ + "187.3, 187.3, 187.3, 197.1, 216.6", \ + "316.7, 316.7, 316.7, 326.5, 346.0"); + } + cell_fall (inslew_load_5x5__0) { + values ("220.6, 220.6, 220.6, 228.1, 242.6", \ + "217.8, 217.8, 217.8, 225.2, 239.8", \ + "209.5, 209.5, 209.5, 216.8, 231.6", \ + "192.7, 192.7, 192.7, 200.1, 214.7", \ + "161.4, 161.4, 161.4, 168.8, 183.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("129.0, 129.0, 129.0, 133.8, 143.3", \ + "139.8, 139.8, 139.8, 144.8, 154.2", \ + "160.8, 160.8, 160.8, 165.8, 175.3", \ + "201.2, 201.2, 201.2, 206.2, 216.0", \ + "281.7, 281.7, 281.7, 286.7, 296.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("97.1, 97.1, 97.1, 104.6, 118.4", \ + "103.3, 103.3, 103.3, 110.8, 124.9", \ + "109.9, 109.9, 109.9, 117.5, 131.9", \ + "114.4, 114.4, 114.4, 122.2, 137.1", \ + "113.9, 113.9, 113.9, 121.9, 137.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("70.9, 70.9, 70.9, 80.6, 99.6", \ + "81.2, 81.2, 81.2, 91.0, 110.0", \ + "101.4, 101.4, 101.4, 111.2, 130.4", \ + "140.9, 140.9, 140.9, 150.7, 170.1", \ + "218.3, 218.3, 218.3, 228.1, 247.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("203.5, 203.5, 203.5, 211.1, 225.5", \ + "216.6, 216.6, 216.6, 224.1, 238.7", \ + "237.6, 237.6, 237.6, 244.9, 259.6", \ + "277.5, 277.5, 277.5, 284.9, 299.3", \ + "356.7, 356.7, 356.7, 364.2, 378.8"); + } + fall_transition (inslew_load_5x5__0) { + values ("117.5, 117.5, 117.5, 122.3, 131.8", \ + "134.4, 134.4, 134.4, 139.3, 148.8", \ + "165.8, 165.8, 165.8, 170.8, 180.3", \ + "227.1, 227.1, 227.1, 232.1, 241.9", \ + "349.7, 349.7, 349.7, 354.7, 364.7"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("97.8, 97.8, 97.8, 105.3, 118.9", \ + "111.3, 111.3, 111.3, 118.8, 132.8", \ + "129.0, 129.0, 129.0, 136.7, 151.0", \ + "153.4, 153.4, 153.4, 161.2, 176.2", \ + "191.2, 191.2, 191.2, 199.2, 214.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("66.9, 66.9, 66.9, 76.6, 95.6", \ + "79.7, 79.7, 79.7, 89.4, 108.5", \ + "103.8, 103.8, 103.8, 113.6, 132.9", \ + "149.8, 149.8, 149.8, 159.6, 179.0", \ + "239.4, 239.4, 239.4, 249.1, 268.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("190.8, 190.8, 190.8, 198.4, 212.7", \ + "196.4, 196.4, 196.4, 204.0, 218.4", \ + "203.3, 203.3, 203.3, 210.6, 225.3", \ + "215.2, 215.2, 215.2, 222.6, 237.1", \ + "238.7, 238.7, 238.7, 246.2, 260.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("110.2, 110.2, 110.2, 115.0, 124.5", \ + "123.0, 123.0, 123.0, 127.8, 137.3", \ + "146.5, 146.5, 146.5, 151.4, 160.9", \ + "192.7, 192.7, 192.7, 197.7, 207.3", \ + "285.7, 285.7, 285.7, 290.7, 300.6"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("79.8, 79.8, 79.8, 87.1, 100.5", \ + "81.4, 81.4, 81.4, 88.9, 102.5", \ + "78.4, 78.4, 78.4, 85.9, 100.0", \ + "63.0, 63.0, 63.0, 70.7, 85.2", \ + "21.4, 21.4, 21.4, 29.3, 44.5"); + } + rise_transition (inslew_load_5x5__0) { + values ("58.6, 58.6, 58.6, 68.2, 87.2", \ + "66.8, 66.8, 66.8, 76.5, 95.5", \ + "82.7, 82.7, 82.7, 92.4, 111.5", \ + "112.9, 112.9, 112.9, 122.6, 141.9", \ + "171.2, 171.2, 171.2, 180.9, 200.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("158.5, 158.5, 158.5, 166.0, 180.0", \ + "175.5, 175.5, 175.5, 183.1, 197.5", \ + "203.7, 203.7, 203.7, 211.1, 225.8", \ + "260.2, 260.2, 260.2, 267.5, 282.1", \ + "370.2, 370.2, 370.2, 377.6, 392.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("91.5, 91.5, 91.5, 96.3, 105.6", \ + "109.3, 109.3, 109.3, 114.0, 123.5", \ + "140.0, 140.0, 140.0, 145.0, 154.4", \ + "202.2, 202.2, 202.2, 207.2, 216.9", \ + "326.8, 326.8, 326.8, 331.8, 341.8"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("80.4, 80.4, 80.4, 87.7, 101.0", \ + "88.2, 88.2, 88.2, 95.6, 109.2", \ + "94.6, 94.6, 94.6, 102.2, 116.3", \ + "96.1, 96.1, 96.1, 103.8, 118.4", \ + "87.8, 87.8, 87.8, 95.7, 111.0"); + } + rise_transition (inslew_load_5x5__0) { + values ("54.8, 54.8, 54.8, 64.5, 83.4", \ + "65.4, 65.4, 65.4, 75.0, 94.0", \ + "84.6, 84.6, 84.6, 94.3, 113.4", \ + "120.3, 120.3, 120.3, 130.1, 149.4", \ + "189.2, 189.2, 189.2, 198.9, 218.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("146.8, 146.8, 146.8, 154.2, 168.1", \ + "157.4, 157.4, 157.4, 164.9, 179.1", \ + "173.1, 173.1, 173.1, 180.7, 195.1", \ + "204.6, 204.6, 204.6, 211.9, 226.6", \ + "264.2, 264.2, 264.2, 271.6, 286.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("84.7, 84.7, 84.7, 89.4, 98.8", \ + "98.9, 98.9, 98.9, 103.6, 113.0", \ + "123.1, 123.1, 123.1, 127.9, 137.4", \ + "172.6, 172.6, 172.6, 177.6, 187.2", \ + "272.4, 272.4, 272.4, 277.4, 287.3"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("61.8, 61.8, 61.8, 68.9, 81.6", \ + "64.8, 64.8, 64.8, 72.0, 85.1", \ + "62.1, 62.1, 62.1, 69.5, 83.2", \ + "46.6, 46.6, 46.6, 54.3, 68.5", \ + "6.0, 6.0, 6.0, 13.8, 28.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("42.5, 42.5, 42.5, 52.1, 70.8", \ + "51.5, 51.5, 51.5, 61.2, 80.0", \ + "67.4, 67.4, 67.4, 77.1, 96.1", \ + "96.6, 96.6, 96.6, 106.3, 125.5", \ + "152.3, 152.3, 152.3, 162.1, 181.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("83.9, 83.9, 83.9, 91.0, 103.5", \ + "101.6, 101.6, 101.6, 108.8, 122.1", \ + "126.8, 126.8, 126.8, 134.3, 148.4", \ + "165.8, 165.8, 165.8, 173.1, 187.8", \ + "255.5, 255.5, 255.5, 262.9, 277.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("48.6, 48.6, 48.6, 53.3, 62.3", \ + "66.5, 66.5, 66.5, 71.3, 80.4", \ + "94.5, 94.5, 94.5, 99.2, 108.6", \ + "142.9, 142.9, 142.9, 147.8, 157.3", \ + "247.4, 247.4, 247.4, 252.4, 262.2"); + } + } + timing (maxd_q_i7_positive_unate) { + related_pin : "i7" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("61.8, 61.8, 61.8, 69.0, 81.9", \ + "59.9, 59.9, 59.9, 67.2, 80.3", \ + "49.5, 49.5, 49.5, 56.9, 70.5", \ + "19.7, 19.7, 19.7, 27.3, 41.5", \ + "-50.3, -50.3, -50.3, -42.5, -27.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("46.2, 46.2, 46.2, 55.9, 74.6", \ + "53.3, 53.3, 53.3, 62.9, 81.8", \ + "66.5, 66.5, 66.5, 76.1, 95.1", \ + "90.9, 90.9, 90.9, 100.6, 119.8", \ + "137.3, 137.3, 137.3, 147.1, 166.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("94.8, 94.8, 94.8, 102.0, 114.8", \ + "118.6, 118.6, 118.6, 125.9, 139.5", \ + "155.3, 155.3, 155.3, 162.8, 177.2", \ + "216.7, 216.7, 216.7, 224.0, 238.7", \ + "351.3, 351.3, 351.3, 358.8, 373.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("54.7, 54.7, 54.7, 59.4, 68.6", \ + "76.0, 76.0, 76.0, 80.7, 90.0", \ + "109.7, 109.7, 109.7, 114.5, 124.0", \ + "169.2, 169.2, 169.2, 174.2, 183.7", \ + "294.2, 294.2, 294.2, 299.2, 309.1"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("577.0, 577.0, 577.0, 614.5, 689.4", \ + "681.9, 681.9, 681.9, 719.3, 794.3", \ + "888.9, 888.9, 888.9, 926.4, 1001.3", \ + "1301.8, 1301.8, 1301.8, 1339.3, 1414.2", \ + "2125.7, 2125.7, 2125.7, 2163.2, 2238.1"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("1008.8, 1008.8, 1008.8, 1046.3, 1121.2", \ + "1117.4, 1117.4, 1117.4, 1154.9, 1229.8", \ + "1330.9, 1330.9, 1330.9, 1368.4, 1443.3", \ + "1752.5, 1752.5, 1752.5, 1789.9, 1864.9", \ + "2592.4, 2592.4, 2592.4, 2629.9, 2704.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("539.7, 539.7, 539.7, 577.2, 652.1", \ + "652.9, 652.9, 652.9, 690.4, 765.3", \ + "873.8, 873.8, 873.8, 911.2, 986.2", \ + "1310.6, 1310.6, 1310.6, 1348.0, 1423.0", \ + "2180.1, 2180.1, 2180.1, 2217.5, 2292.5"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("947.5, 947.5, 947.5, 985.0, 1059.9", \ + "1024.0, 1024.0, 1024.0, 1061.4, 1136.4", \ + "1174.1, 1174.1, 1174.1, 1211.5, 1286.5", \ + "1468.7, 1468.7, 1468.7, 1506.2, 1581.1", \ + "2056.4, 2056.4, 2056.4, 2093.9, 2168.8"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("537.1, 537.1, 537.1, 574.6, 649.5", \ + "600.2, 600.2, 600.2, 637.7, 712.6", \ + "725.5, 725.5, 725.5, 762.9, 837.9", \ + "974.3, 974.3, 974.3, 1011.7, 1086.7", \ + "1468.0, 1468.0, 1468.0, 1505.5, 1580.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("867.6, 867.6, 867.6, 905.1, 980.0", \ + "984.0, 984.0, 984.0, 1021.5, 1096.4", \ + "1207.7, 1207.7, 1207.7, 1245.2, 1320.1", \ + "1649.9, 1649.9, 1649.9, 1687.3, 1762.3", \ + "2534.6, 2534.6, 2534.6, 2572.1, 2647.0"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("503.5, 503.5, 503.5, 541.0, 615.9", \ + "576.1, 576.1, 576.1, 613.5, 688.5", \ + "717.7, 717.7, 717.7, 755.2, 830.1", \ + "995.4, 995.4, 995.4, 1032.9, 1107.8", \ + "1544.8, 1544.8, 1544.8, 1582.3, 1657.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("811.1, 811.1, 811.1, 848.6, 923.5", \ + "898.2, 898.2, 898.2, 935.7, 1010.6", \ + "1065.1, 1065.1, 1065.1, 1102.5, 1177.5", \ + "1395.7, 1395.7, 1395.7, 1433.1, 1508.1", \ + "2059.1, 2059.1, 2059.1, 2096.6, 2171.5"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__0) { + values ("432.0, 432.0, 432.0, 469.5, 544.4", \ + "477.0, 477.0, 477.0, 514.5, 589.4", \ + "565.7, 565.7, 565.7, 603.1, 678.1", \ + "739.6, 739.6, 739.6, 777.1, 852.0", \ + "1082.7, 1082.7, 1082.7, 1120.2, 1195.1"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("681.8, 681.8, 681.8, 719.3, 794.2", \ + "799.3, 799.3, 799.3, 836.8, 911.7", \ + "1017.2, 1017.2, 1017.2, 1054.6, 1129.6", \ + "1455.5, 1455.5, 1455.5, 1492.9, 1567.9", \ + "2333.0, 2333.0, 2333.0, 2370.5, 2445.4"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__0) { + values ("399.1, 399.1, 399.1, 436.5, 511.5", \ + "452.7, 452.7, 452.7, 490.1, 565.1", \ + "555.5, 555.5, 555.5, 593.0, 667.9", \ + "755.0, 755.0, 755.0, 792.5, 867.4", \ + "1147.8, 1147.8, 1147.8, 1185.3, 1260.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("629.3, 629.3, 629.3, 666.8, 741.7", \ + "721.8, 721.8, 721.8, 759.3, 834.2", \ + "891.4, 891.4, 891.4, 928.9, 1003.8", \ + "1235.6, 1235.6, 1235.6, 1273.1, 1348.0", \ + "1926.5, 1926.5, 1926.5, 1964.0, 2038.9"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__0) { + values ("296.0, 296.0, 296.0, 333.5, 408.4", \ + "338.0, 338.0, 338.0, 375.5, 450.4", \ + "416.9, 416.9, 416.9, 454.4, 529.3", \ + "569.3, 569.3, 569.3, 606.7, 681.7", \ + "868.4, 868.4, 868.4, 905.8, 980.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("390.7, 390.7, 390.7, 428.2, 503.1", \ + "496.2, 496.2, 496.2, 533.7, 608.6", \ + "678.1, 678.1, 678.1, 715.6, 790.5", \ + "1014.8, 1014.8, 1014.8, 1052.2, 1127.2", \ + "1717.2, 1717.2, 1717.2, 1754.6, 1829.6"); + } + } + internal_power (energy_pos_q_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__0) { + values ("329.1, 329.1, 329.1, 366.5, 441.5", \ + "363.6, 363.6, 363.6, 401.1, 476.0", \ + "430.8, 430.8, 430.8, 468.3, 543.2", \ + "561.0, 561.0, 561.0, 598.5, 673.4", \ + "816.2, 816.2, 816.2, 853.6, 928.6"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("439.1, 439.1, 439.1, 476.6, 551.5", \ + "567.2, 567.2, 567.2, 604.6, 679.6", \ + "790.9, 790.9, 790.9, 828.4, 903.3", \ + "1209.7, 1209.7, 1209.7, 1247.1, 1322.1", \ + "2070.2, 2070.2, 2070.2, 2107.6, 2182.6"); + } + } + } + } + + cell (oa2a2a2a24_x4) { + area : 0.0 ; + cell_leakage_power : 23 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5) & (i6 ^ i7))" ; + value : 18 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 13 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5 & (i6 ^ i7))" ; + value : 25 ; + } + leakage_power () { + when : "(i2 & i3 & i4 & i5 & i6 & i7)" ; + value : 41 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & !((i4 & i5)) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & !((i4 & i5)) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (i2 & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))" ; + value : 28 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i2) & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i1) & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))) | (i2 & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 22 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))) | (!(i1) & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!((i2 & i3)) & i4 & i5 & !(i6) & !(i7)))))) | (!(i0) & ((i1 & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!((i2 & i3)) & i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))" ; + value : 15 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & ((!(i3) & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!(i4) & !(i5) & !(i6) & !(i7)))) | (!(i2) & ((i3 & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!(i3) & ((i4 & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i4) & ((i5 & (!(i6) | !(i7))) | (!(i5) & (i6 | i7)))))))))) | (i2 & i3 & !(i4) & !(i5) & !(i6) & !(i7)))" ; + value : 14 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i1) & (i2 ^ i3) & (i4 ^ i5) & i6 & i7))))" ; + value : 35 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & !(i2) & !(i3) & i4 & i5 & i6 & i7) | (!(i1) & ((i2 & !(i3) & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))))" ; + value : 29 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & !(i3) & i4 & i5 & i6 & i7))) | (i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i0) & ((!(i1) & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))))" ; + value : 16 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((!(i2) & ((!(i3) & i6 & i7) | (i4 & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7)))" ; + value : 42 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !((i2 & i3)) & !((i4 & i5)) & (!(i6) | !(i7)))" ; + value : 3.2 ; + } + pin (i7) { + direction : input ; + capacitance : 5.11 ; + } + pin (i6) { + direction : input ; + capacitance : 5.11 ; + } + pin (i5) { + direction : input ; + capacitance : 5.11 ; + } + pin (i4) { + direction : input ; + capacitance : 5.14 ; + } + pin (i3) { + direction : input ; + capacitance : 5.11 ; + } + pin (i2) { + direction : input ; + capacitance : 5.05 ; + } + pin (i1) { + direction : input ; + capacitance : 5.33 ; + } + pin (i0) { + direction : input ; + capacitance : 5.24 ; + } + pin (q) { + function : "((i7 & ((i4 & ((i2 & ((i1 & i0) | i3 | i5 | i6)) | (i1 & i0) | i5 | i6)) | (i2 & ((i1 & i0) | i3 | i6)) | (i1 & i0) | i6)) | (i4 & ((i2 & ((i1 & i0) | i3 | i5)) | (i1 & i0) | i5)) | (i2 & ((i1 & i0) | i3)) | (i1 & i0))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("99.4, 99.4, 99.4, 105.4, 116.8", \ + "110.4, 110.4, 110.4, 116.5, 128.0", \ + "127.4, 127.4, 127.4, 133.6, 145.3", \ + "154.4, 154.4, 154.4, 160.8, 173.0", \ + "201.7, 201.7, 201.7, 208.1, 220.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("72.0, 72.0, 72.0, 79.8, 95.0", \ + "85.3, 85.3, 85.3, 93.0, 108.3", \ + "111.2, 111.2, 111.2, 119.0, 134.3", \ + "162.4, 162.4, 162.4, 170.2, 185.6", \ + "263.8, 263.8, 263.8, 271.6, 287.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("277.8, 277.8, 277.8, 283.5, 295.1", \ + "289.1, 289.1, 289.1, 294.9, 306.2", \ + "308.5, 308.5, 308.5, 314.3, 325.4", \ + "345.7, 345.7, 345.7, 351.5, 362.8", \ + "421.0, 421.0, 421.0, 426.8, 438.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("164.3, 164.3, 164.3, 168.2, 175.8", \ + "183.5, 183.5, 183.5, 187.4, 195.0", \ + "220.3, 220.3, 220.3, 224.2, 231.9", \ + "292.5, 292.5, 292.5, 296.3, 304.1", \ + "435.6, 435.6, 435.6, 439.5, 447.2"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("100.0, 100.0, 100.0, 106.0, 117.3", \ + "118.4, 118.4, 118.4, 124.5, 136.0", \ + "147.0, 147.0, 147.0, 153.3, 165.0", \ + "195.3, 195.3, 195.3, 201.7, 213.9", \ + "283.9, 283.9, 283.9, 290.2, 302.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("68.1, 68.1, 68.1, 75.8, 91.0", \ + "83.7, 83.7, 83.7, 91.5, 106.8", \ + "113.7, 113.7, 113.7, 121.5, 136.9", \ + "171.7, 171.7, 171.7, 179.4, 194.9", \ + "285.9, 285.9, 285.9, 293.7, 309.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("260.9, 260.9, 260.9, 266.6, 278.4", \ + "263.0, 263.0, 263.0, 268.7, 280.2", \ + "264.3, 264.3, 264.3, 270.0, 281.2", \ + "265.7, 265.7, 265.7, 271.5, 282.7", \ + "270.2, 270.2, 270.2, 276.0, 287.4"); + } + fall_transition (inslew_load_5x5__1) { + values ("154.6, 154.6, 154.6, 158.5, 166.0", \ + "168.3, 168.3, 168.3, 172.2, 179.8", \ + "194.9, 194.9, 194.9, 198.8, 206.6", \ + "246.7, 246.7, 246.7, 250.6, 258.4", \ + "349.2, 349.2, 349.2, 353.0, 360.8"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("93.3, 93.3, 93.3, 99.3, 110.6", \ + "95.1, 95.1, 95.1, 101.1, 112.5", \ + "92.1, 92.1, 92.1, 98.2, 109.7", \ + "74.2, 74.2, 74.2, 80.4, 92.3", \ + "23.4, 23.4, 23.4, 29.7, 41.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("67.7, 67.7, 67.7, 75.4, 90.6", \ + "74.9, 74.9, 74.9, 82.6, 97.8", \ + "89.4, 89.4, 89.4, 97.2, 112.5", \ + "117.2, 117.2, 117.2, 124.9, 140.3", \ + "169.9, 169.9, 169.9, 177.7, 193.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("250.3, 250.3, 250.3, 256.0, 267.8", \ + "278.5, 278.5, 278.5, 284.2, 295.7", \ + "327.0, 327.0, 327.0, 332.8, 343.9", \ + "420.1, 420.1, 420.1, 425.8, 437.2", \ + "605.0, 605.0, 605.0, 610.8, 622.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("146.9, 146.9, 146.9, 150.8, 158.2", \ + "172.7, 172.7, 172.7, 176.6, 184.2", \ + "220.2, 220.2, 220.2, 224.1, 231.9", \ + "313.0, 313.0, 313.0, 316.9, 324.7", \ + "497.6, 497.6, 497.6, 501.4, 509.1"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("96.3, 96.3, 96.3, 102.3, 113.5", \ + "107.7, 107.7, 107.7, 113.8, 125.2", \ + "121.3, 121.3, 121.3, 127.5, 139.0", \ + "136.1, 136.1, 136.1, 142.3, 154.4", \ + "153.0, 153.0, 153.0, 159.4, 171.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("65.5, 65.5, 65.5, 73.2, 88.4", \ + "76.8, 76.8, 76.8, 84.6, 99.8", \ + "98.5, 98.5, 98.5, 106.3, 121.6", \ + "139.5, 139.5, 139.5, 147.2, 162.7", \ + "218.9, 218.9, 218.9, 226.6, 242.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("229.3, 229.3, 229.3, 235.1, 246.9", \ + "239.6, 239.6, 239.6, 245.3, 257.1", \ + "254.9, 254.9, 254.9, 260.6, 272.0", \ + "282.7, 282.7, 282.7, 288.5, 299.6", \ + "337.9, 337.9, 337.9, 343.7, 355.1"); + } + fall_transition (inslew_load_5x5__1) { + values ("134.6, 134.6, 134.6, 138.4, 145.8", \ + "150.0, 150.0, 150.0, 154.0, 161.4", \ + "178.6, 178.6, 178.6, 182.5, 190.2", \ + "234.3, 234.3, 234.3, 238.2, 246.0", \ + "346.1, 346.1, 346.1, 349.9, 357.7"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("81.8, 81.8, 81.8, 87.8, 98.9", \ + "82.6, 82.6, 82.6, 88.6, 99.9", \ + "77.6, 77.6, 77.6, 83.7, 95.1", \ + "56.2, 56.2, 56.2, 62.4, 74.1", \ + "0.1, 0.1, 0.1, 6.4, 18.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("59.5, 59.5, 59.5, 67.2, 82.3", \ + "66.7, 66.7, 66.7, 74.5, 89.6", \ + "80.9, 80.9, 80.9, 88.7, 103.9", \ + "107.8, 107.8, 107.8, 115.5, 130.9", \ + "158.8, 158.8, 158.8, 166.5, 182.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("197.6, 197.6, 197.6, 203.7, 215.3", \ + "219.9, 219.9, 219.9, 225.6, 237.5", \ + "256.7, 256.7, 256.7, 262.4, 273.9", \ + "330.4, 330.4, 330.4, 336.2, 347.4", \ + "473.7, 473.7, 473.7, 479.5, 490.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("116.2, 116.2, 116.2, 119.9, 127.3", \ + "136.9, 136.9, 136.9, 140.7, 148.1", \ + "172.8, 172.8, 172.8, 176.7, 184.3", \ + "244.9, 244.9, 244.9, 248.8, 256.6", \ + "389.4, 389.4, 389.4, 393.2, 400.9"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("83.1, 83.1, 83.1, 89.1, 100.0", \ + "89.8, 89.8, 89.8, 95.7, 107.0", \ + "93.4, 93.4, 93.4, 99.5, 111.0", \ + "87.6, 87.6, 87.6, 93.8, 105.6", \ + "61.6, 61.6, 61.6, 67.9, 80.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("56.3, 56.3, 56.3, 64.0, 79.1", \ + "65.6, 65.6, 65.6, 73.3, 88.5", \ + "82.9, 82.9, 82.9, 90.7, 105.9", \ + "114.9, 114.9, 114.9, 122.6, 138.0", \ + "175.6, 175.6, 175.6, 183.4, 198.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("184.1, 184.1, 184.1, 190.1, 201.8", \ + "199.4, 199.4, 199.4, 205.3, 217.1", \ + "223.3, 223.3, 223.3, 229.0, 240.7", \ + "271.4, 271.4, 271.4, 277.1, 288.3", \ + "362.1, 362.1, 362.1, 367.9, 379.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("108.2, 108.2, 108.2, 111.9, 119.3", \ + "124.9, 124.9, 124.9, 128.7, 136.1", \ + "153.6, 153.6, 153.6, 157.5, 165.0", \ + "211.9, 211.9, 211.9, 215.8, 223.6", \ + "329.1, 329.1, 329.1, 333.0, 340.7"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("68.3, 68.3, 68.3, 74.2, 84.9", \ + "71.2, 71.2, 71.2, 77.2, 88.1", \ + "67.4, 67.4, 67.4, 73.4, 84.7", \ + "46.9, 46.9, 46.9, 53.1, 64.6", \ + "-7.8, -7.8, -7.8, -1.5, 10.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("46.2, 46.2, 46.2, 53.9, 69.0", \ + "54.6, 54.6, 54.6, 62.2, 77.3", \ + "69.2, 69.2, 69.2, 76.9, 92.1", \ + "95.5, 95.5, 95.5, 103.3, 118.6", \ + "144.9, 144.9, 144.9, 152.6, 168.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("119.7, 119.7, 119.7, 125.6, 136.7", \ + "142.4, 142.4, 142.4, 148.4, 159.9", \ + "176.2, 176.2, 176.2, 182.1, 193.8", \ + "229.7, 229.7, 229.7, 235.4, 246.8", \ + "347.5, 347.5, 347.5, 353.3, 364.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("69.9, 69.9, 69.9, 73.6, 80.9", \ + "90.9, 90.9, 90.9, 94.7, 102.1", \ + "123.0, 123.0, 123.0, 126.8, 134.2", \ + "179.2, 179.2, 179.2, 183.2, 190.8", \ + "298.4, 298.4, 298.4, 302.2, 310.0"); + } + } + timing (maxd_q_i7_positive_unate) { + related_pin : "i7" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("67.6, 67.6, 67.6, 73.5, 84.3", \ + "65.6, 65.6, 65.6, 71.6, 82.5", \ + "54.6, 54.6, 54.6, 60.6, 71.9", \ + "21.3, 21.3, 21.3, 27.5, 39.0", \ + "-59.6, -59.6, -59.6, -53.3, -41.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("49.5, 49.5, 49.5, 57.2, 72.3", \ + "56.0, 56.0, 56.0, 63.7, 78.8", \ + "68.0, 68.0, 68.0, 75.7, 90.9", \ + "90.0, 90.0, 90.0, 97.8, 113.1", \ + "131.1, 131.1, 131.1, 138.9, 154.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("132.3, 132.3, 132.3, 138.2, 149.5", \ + "161.1, 161.1, 161.1, 167.2, 178.8", \ + "206.3, 206.3, 206.3, 212.0, 223.9", \ + "283.5, 283.5, 283.5, 289.2, 300.4", \ + "448.4, 448.4, 448.4, 454.1, 465.5"); + } + fall_transition (inslew_load_5x5__1) { + values ("77.4, 77.4, 77.4, 81.1, 88.5", \ + "101.9, 101.9, 101.9, 105.7, 113.0", \ + "140.0, 140.0, 140.0, 143.9, 151.2", \ + "207.9, 207.9, 207.9, 211.8, 219.6", \ + "351.7, 351.7, 351.7, 355.6, 363.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("827.4, 827.4, 827.4, 887.0, 1006.2", \ + "959.0, 959.0, 959.0, 1018.6, 1137.8", \ + "1220.3, 1220.3, 1220.3, 1279.9, 1399.1", \ + "1740.7, 1740.7, 1740.7, 1800.3, 1919.5", \ + "2777.4, 2777.4, 2777.4, 2837.0, 2956.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1780.3, 1780.3, 1780.3, 1839.9, 1959.1", \ + "1980.4, 1980.4, 1980.4, 2040.0, 2159.2", \ + "2370.2, 2370.2, 2370.2, 2429.8, 2549.0", \ + "3139.7, 3139.7, 3139.7, 3199.3, 3318.5", \ + "4669.6, 4669.6, 4669.6, 4729.2, 4848.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("779.3, 779.3, 779.3, 838.9, 958.1", \ + "926.9, 926.9, 926.9, 986.5, 1105.7", \ + "1216.0, 1216.0, 1216.0, 1275.6, 1394.8", \ + "1784.8, 1784.8, 1784.8, 1844.4, 1963.6", \ + "2914.8, 2914.8, 2914.8, 2974.4, 3093.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1673.5, 1673.5, 1673.5, 1733.1, 1852.3", \ + "1817.1, 1817.1, 1817.1, 1876.7, 1995.9", \ + "2097.6, 2097.6, 2097.6, 2157.2, 2276.4", \ + "2648.5, 2648.5, 2648.5, 2708.1, 2827.3", \ + "3742.6, 3742.6, 3742.6, 3802.2, 3921.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("764.7, 764.7, 764.7, 824.3, 943.5", \ + "825.5, 825.5, 825.5, 885.0, 1004.2", \ + "948.3, 948.3, 948.3, 1007.9, 1127.1", \ + "1187.4, 1187.4, 1187.4, 1246.9, 1366.1", \ + "1652.0, 1652.0, 1652.0, 1711.6, 1830.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1601.2, 1601.2, 1601.2, 1660.8, 1780.0", \ + "1865.9, 1865.9, 1865.9, 1925.5, 2044.7", \ + "2366.4, 2366.4, 2366.4, 2426.0, 2545.2", \ + "3351.1, 3351.1, 3351.1, 3410.7, 3529.9", \ + "5312.5, 5312.5, 5312.5, 5372.1, 5491.2"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("738.0, 738.0, 738.0, 797.6, 916.8", \ + "835.8, 835.8, 835.8, 895.4, 1014.6", \ + "1026.5, 1026.5, 1026.5, 1086.1, 1205.3", \ + "1396.4, 1396.4, 1396.4, 1456.0, 1575.2", \ + "2123.8, 2123.8, 2123.8, 2183.4, 2302.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1461.4, 1461.4, 1461.4, 1521.0, 1640.2", \ + "1619.5, 1619.5, 1619.5, 1679.1, 1798.3", \ + "1918.7, 1918.7, 1918.7, 1978.3, 2097.5", \ + "2506.6, 2506.6, 2506.6, 2566.2, 2685.4", \ + "3685.6, 3685.6, 3685.6, 3745.2, 3864.4"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__1) { + values ("667.2, 667.2, 667.2, 726.8, 846.0", \ + "726.9, 726.9, 726.9, 786.5, 905.7", \ + "845.7, 845.7, 845.7, 905.3, 1024.5", \ + "1075.7, 1075.7, 1075.7, 1135.3, 1254.5", \ + "1522.5, 1522.5, 1522.5, 1582.1, 1701.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1271.9, 1271.9, 1271.9, 1331.5, 1450.7", \ + "1479.5, 1479.5, 1479.5, 1539.1, 1658.3", \ + "1855.9, 1855.9, 1855.9, 1915.5, 2034.7", \ + "2610.5, 2610.5, 2610.5, 2670.1, 2789.3", \ + "4120.5, 4120.5, 4120.5, 4180.1, 4299.3"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__1) { + values ("623.5, 623.5, 623.5, 683.1, 802.3", \ + "697.1, 697.1, 697.1, 756.7, 875.9", \ + "838.1, 838.1, 838.1, 897.7, 1016.8", \ + "1107.1, 1107.1, 1107.1, 1166.7, 1285.9", \ + "1629.6, 1629.6, 1629.6, 1689.2, 1808.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1183.3, 1183.3, 1183.3, 1242.9, 1362.1", \ + "1350.3, 1350.3, 1350.3, 1409.9, 1529.1", \ + "1649.8, 1649.8, 1649.8, 1709.4, 1828.5", \ + "2255.4, 2255.4, 2255.4, 2315.0, 2434.2", \ + "3470.9, 3470.9, 3470.9, 3530.5, 3649.7"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__1) { + values ("503.7, 503.7, 503.7, 563.3, 682.5", \ + "564.1, 564.1, 564.1, 623.7, 742.9", \ + "675.9, 675.9, 675.9, 735.5, 854.7", \ + "886.1, 886.1, 886.1, 945.7, 1064.9", \ + "1290.0, 1290.0, 1290.0, 1349.6, 1468.8"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("803.5, 803.5, 803.5, 863.1, 982.3", \ + "998.7, 998.7, 998.7, 1058.3, 1177.5", \ + "1318.6, 1318.6, 1318.6, 1378.2, 1497.4", \ + "1902.5, 1902.5, 1902.5, 1962.1, 2081.3", \ + "3118.9, 3118.9, 3118.9, 3178.5, 3297.7"); + } + } + internal_power (energy_pos_q_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__1) { + values ("548.2, 548.2, 548.2, 607.8, 727.0", \ + "596.6, 596.6, 596.6, 656.2, 775.4", \ + "690.0, 690.0, 690.0, 749.6, 868.8", \ + "867.5, 867.5, 867.5, 927.1, 1046.3", \ + "1207.9, 1207.9, 1207.9, 1267.5, 1386.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("886.1, 886.1, 886.1, 945.7, 1064.9", \ + "1116.7, 1116.7, 1116.7, 1176.3, 1295.5", \ + "1500.9, 1500.9, 1500.9, 1560.5, 1679.7", \ + "2210.8, 2210.8, 2210.8, 2270.4, 2389.6", \ + "3687.8, 3687.8, 3687.8, 3747.4, 3866.6"); + } + } + } + } + + cell (oa2ao222_x2) { + area : 0.0 ; + cell_leakage_power : 2.3 ; + leakage_power () { + when : "(i4 & i3 & i2 & i1 & i0)" ; + value : 1 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & i1 & i0)" ; + value : 0.79 ; + } + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & i4)" ; + value : 0.8 ; + } + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & !(i4))" ; + value : 0.56 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & i0)" ; + value : 0.78 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 0.54 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3 & i4)" ; + value : 3.4 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & i4)" ; + value : 3.3 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & i3 & i4)" ; + value : 1.6 ; + } + leakage_power () { + when : "(i4 & i3 & i2 & !(i1) & !(i0))" ; + value : 5.7 ; + } + leakage_power () { + when : "(i4 & !(i3) & i2 & !(i1) & !(i0))" ; + value : 5.8 ; + } + leakage_power () { + when : "(i4 & i3 & !(i2) & !(i1) & !(i0))" ; + value : 2.5 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!((i2 | i3)) | !(i4)))" ; + value : 2.6 ; + } + pin (i4) { + direction : input ; + capacitance : 3.34 ; + } + pin (i3) { + direction : input ; + capacitance : 4.81 ; + } + pin (i2) { + direction : input ; + capacitance : 4.89 ; + } + pin (i1) { + direction : input ; + capacitance : 3.53 ; + } + pin (i0) { + direction : input ; + capacitance : 3.50 ; + } + pin (q) { + function : "(((i3 | i2) & ((i0 & i1) | i4)) | (i0 & i1))" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("79.9, 79.9, 79.9, 87.3, 100.7", \ + "85.2, 85.2, 85.2, 92.6, 106.3", \ + "89.9, 89.9, 89.9, 97.5, 111.6", \ + "91.4, 91.4, 91.4, 99.2, 113.8", \ + "85.7, 85.7, 85.7, 93.6, 108.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("58.9, 58.9, 58.9, 68.5, 87.4", \ + "68.5, 68.5, 68.5, 78.2, 97.1", \ + "87.5, 87.5, 87.5, 97.2, 116.3", \ + "124.2, 124.2, 124.2, 134.0, 153.3", \ + "196.1, 196.1, 196.1, 205.8, 225.3"); + } + cell_fall (inslew_load_5x5__0) { + values ("161.1, 161.1, 161.1, 168.6, 182.6", \ + "171.5, 171.5, 171.5, 179.0, 193.4", \ + "189.8, 189.8, 189.8, 197.3, 211.8", \ + "225.2, 225.2, 225.2, 232.4, 246.9", \ + "292.1, 292.1, 292.1, 299.4, 313.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("93.9, 93.9, 93.9, 98.6, 107.8", \ + "107.2, 107.2, 107.2, 111.9, 121.2", \ + "132.8, 132.8, 132.8, 137.5, 146.9", \ + "184.0, 184.0, 184.0, 188.9, 198.4", \ + "287.6, 287.6, 287.6, 292.5, 302.3"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("83.0, 83.0, 83.0, 90.3, 103.6", \ + "95.1, 95.1, 95.1, 102.5, 116.2", \ + "110.1, 110.1, 110.1, 117.7, 131.9", \ + "130.1, 130.1, 130.1, 137.9, 152.7", \ + "160.2, 160.2, 160.2, 168.2, 183.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("56.5, 56.5, 56.5, 66.2, 85.0", \ + "69.0, 69.0, 69.0, 78.7, 97.6", \ + "92.1, 92.1, 92.1, 101.8, 120.9", \ + "136.0, 136.0, 136.0, 145.8, 165.1", \ + "221.6, 221.6, 221.6, 231.3, 250.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("150.8, 150.8, 150.8, 158.2, 172.2", \ + "155.6, 155.6, 155.6, 163.1, 177.2", \ + "163.1, 163.1, 163.1, 170.6, 185.1", \ + "175.8, 175.8, 175.8, 183.0, 197.7", \ + "198.0, 198.0, 198.0, 205.3, 219.4"); + } + fall_transition (inslew_load_5x5__0) { + values ("87.9, 87.9, 87.9, 92.6, 101.8", \ + "98.1, 98.1, 98.1, 102.7, 112.0", \ + "117.9, 117.9, 117.9, 122.6, 131.9", \ + "157.9, 157.9, 157.9, 162.9, 172.2", \ + "239.4, 239.4, 239.4, 244.3, 254.2"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("65.7, 65.7, 65.7, 72.9, 85.8", \ + "66.2, 66.2, 66.2, 73.6, 86.8", \ + "60.8, 60.8, 60.8, 68.3, 82.0", \ + "41.4, 41.4, 41.4, 49.0, 63.3", \ + "-7.0, -7.0, -7.0, 0.9, 15.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("47.2, 47.2, 47.2, 56.8, 75.5", \ + "55.0, 55.0, 55.0, 64.7, 83.5", \ + "69.7, 69.7, 69.7, 79.4, 98.4", \ + "97.3, 97.3, 97.3, 107.0, 126.2", \ + "150.2, 150.2, 150.2, 159.9, 179.3"); + } + cell_fall (inslew_load_5x5__0) { + values ("95.2, 95.2, 95.2, 102.3, 115.0", \ + "111.1, 111.1, 111.1, 118.5, 131.8", \ + "137.0, 137.0, 137.0, 144.5, 158.6", \ + "189.9, 189.9, 189.9, 197.1, 211.8", \ + "292.0, 292.0, 292.0, 299.3, 313.4"); + } + fall_transition (inslew_load_5x5__0) { + values ("54.3, 54.3, 54.3, 59.0, 68.1", \ + "69.8, 69.8, 69.8, 74.5, 83.6", \ + "97.3, 97.3, 97.3, 102.0, 111.2", \ + "153.1, 153.1, 153.1, 158.1, 167.4", \ + "264.3, 264.3, 264.3, 269.2, 279.1"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("77.0, 77.0, 77.0, 84.3, 97.5", \ + "81.1, 81.1, 81.1, 88.5, 102.0", \ + "83.1, 83.1, 83.1, 90.6, 104.7", \ + "79.1, 79.1, 79.1, 86.8, 101.3", \ + "62.2, 62.2, 62.2, 70.1, 85.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("54.8, 54.8, 54.8, 64.5, 83.3", \ + "64.2, 64.2, 64.2, 73.9, 92.8", \ + "82.1, 82.1, 82.1, 91.8, 110.9", \ + "116.4, 116.4, 116.4, 126.2, 145.5", \ + "183.2, 183.2, 183.2, 192.9, 212.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("129.1, 129.1, 129.1, 136.4, 149.9", \ + "140.6, 140.6, 140.6, 148.0, 162.0", \ + "159.8, 159.8, 159.8, 167.4, 181.9", \ + "198.6, 198.6, 198.6, 205.8, 220.4", \ + "272.4, 272.4, 272.4, 279.7, 293.8"); + } + fall_transition (inslew_load_5x5__0) { + values ("74.7, 74.7, 74.7, 79.4, 88.5", \ + "89.3, 89.3, 89.3, 94.0, 103.2", \ + "116.0, 116.0, 116.0, 120.8, 130.1", \ + "170.3, 170.3, 170.3, 175.3, 184.7", \ + "278.6, 278.6, 278.6, 283.5, 293.4"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("58.7, 58.7, 58.7, 65.8, 78.4", \ + "62.5, 62.5, 62.5, 69.8, 82.8", \ + "61.1, 61.1, 61.1, 68.5, 82.1", \ + "48.2, 48.2, 48.2, 55.8, 70.1", \ + "12.8, 12.8, 12.8, 20.7, 35.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("40.8, 40.8, 40.8, 50.4, 69.1", \ + "50.2, 50.2, 50.2, 59.8, 78.6", \ + "66.8, 66.8, 66.8, 76.5, 95.4", \ + "97.2, 97.2, 97.2, 106.9, 126.1", \ + "155.3, 155.3, 155.3, 165.1, 184.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("80.2, 80.2, 80.2, 87.2, 99.6", \ + "92.7, 92.7, 92.7, 100.0, 112.8", \ + "115.3, 115.3, 115.3, 122.7, 136.4", \ + "153.7, 153.7, 153.7, 161.3, 175.7", \ + "225.7, 225.7, 225.7, 232.9, 247.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("46.1, 46.1, 46.1, 50.7, 59.6", \ + "57.8, 57.8, 57.8, 62.5, 71.5", \ + "81.2, 81.2, 81.2, 85.9, 95.0", \ + "127.1, 127.1, 127.1, 131.8, 141.1", \ + "217.4, 217.4, 217.4, 222.3, 232.1"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("407.8, 407.8, 407.8, 445.2, 520.2", \ + "460.8, 460.8, 460.8, 498.3, 573.2", \ + "566.9, 566.9, 566.9, 604.4, 679.3", \ + "776.6, 776.6, 776.6, 814.1, 889.0", \ + "1192.7, 1192.7, 1192.7, 1230.1, 1305.1"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("684.1, 684.1, 684.1, 721.6, 796.5", \ + "775.0, 775.0, 775.0, 812.5, 887.4", \ + "953.5, 953.5, 953.5, 991.0, 1065.9", \ + "1311.5, 1311.5, 1311.5, 1349.0, 1423.9", \ + "2031.3, 2031.3, 2031.3, 2068.7, 2143.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("381.7, 381.7, 381.7, 419.2, 494.1", \ + "444.4, 444.4, 444.4, 481.9, 556.8", \ + "565.9, 565.9, 565.9, 603.3, 678.3", \ + "803.8, 803.8, 803.8, 841.2, 916.2", \ + "1274.1, 1274.1, 1274.1, 1311.6, 1386.5"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("638.9, 638.9, 638.9, 676.4, 751.3", \ + "708.0, 708.0, 708.0, 745.5, 820.4", \ + "844.3, 844.3, 844.3, 881.7, 956.7", \ + "1119.4, 1119.4, 1119.4, 1156.9, 1231.8", \ + "1674.3, 1674.3, 1674.3, 1711.8, 1786.7"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("317.3, 317.3, 317.3, 354.8, 429.7", \ + "355.0, 355.0, 355.0, 392.5, 467.4", \ + "428.1, 428.1, 428.1, 465.6, 540.5", \ + "570.8, 570.8, 570.8, 608.3, 683.2", \ + "851.4, 851.4, 851.4, 888.8, 963.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("405.5, 405.5, 405.5, 443.0, 517.9", \ + "504.3, 504.3, 504.3, 541.7, 616.7", \ + "689.1, 689.1, 689.1, 726.6, 801.5", \ + "1063.2, 1063.2, 1063.2, 1100.7, 1175.6", \ + "1810.4, 1810.4, 1810.4, 1847.9, 1922.8"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("378.3, 378.3, 378.3, 415.8, 490.7", \ + "427.9, 427.9, 427.9, 465.3, 540.3", \ + "525.1, 525.1, 525.1, 562.6, 637.5", \ + "716.8, 716.8, 716.8, 754.2, 829.2", \ + "1095.9, 1095.9, 1095.9, 1133.3, 1208.3"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("547.3, 547.3, 547.3, 584.8, 659.7", \ + "643.9, 643.9, 643.9, 681.4, 756.3", \ + "828.6, 828.6, 828.6, 866.1, 941.0", \ + "1202.0, 1202.0, 1202.0, 1239.5, 1314.4", \ + "1947.7, 1947.7, 1947.7, 1985.2, 2060.1"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__0) { + values ("261.9, 261.9, 261.9, 299.3, 374.3", \ + "302.1, 302.1, 302.1, 339.6, 414.5", \ + "378.2, 378.2, 378.2, 415.6, 490.6", \ + "524.3, 524.3, 524.3, 561.8, 636.7", \ + "811.0, 811.0, 811.0, 848.4, 923.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("342.2, 342.2, 342.2, 379.6, 454.6", \ + "416.5, 416.5, 416.5, 454.0, 528.9", \ + "565.0, 565.0, 565.0, 602.4, 677.4", \ + "859.1, 859.1, 859.1, 896.6, 971.5", \ + "1443.8, 1443.8, 1443.8, 1481.3, 1556.2"); + } + } + } + } + + cell (oa2ao222_x4) { + area : 0.0 ; + cell_leakage_power : 2.3 ; + leakage_power () { + when : "(i4 & i3 & i2 & i1 & i0)" ; + value : 1 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & i1 & i0)" ; + value : 0.79 ; + } + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & i4)" ; + value : 0.8 ; + } + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & !(i4))" ; + value : 0.56 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & i0)" ; + value : 0.78 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 0.54 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3 & i4)" ; + value : 3.4 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & i4)" ; + value : 3.3 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & i3 & i4)" ; + value : 1.6 ; + } + leakage_power () { + when : "(i4 & i3 & i2 & !(i1) & !(i0))" ; + value : 5.7 ; + } + leakage_power () { + when : "(i4 & !(i3) & i2 & !(i1) & !(i0))" ; + value : 5.8 ; + } + leakage_power () { + when : "(i4 & i3 & !(i2) & !(i1) & !(i0))" ; + value : 2.5 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!((i2 | i3)) | !(i4)))" ; + value : 3.2 ; + } + pin (i4) { + direction : input ; + capacitance : 3.34 ; + } + pin (i3) { + direction : input ; + capacitance : 4.81 ; + } + pin (i2) { + direction : input ; + capacitance : 4.89 ; + } + pin (i1) { + direction : input ; + capacitance : 3.53 ; + } + pin (i0) { + direction : input ; + capacitance : 3.50 ; + } + pin (q) { + function : "(((i3 | i2) & ((i0 & i1) | i4)) | (i0 & i1))" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("97.1, 97.1, 97.1, 103.1, 114.4", \ + "103.4, 103.4, 103.4, 109.5, 120.9", \ + "110.2, 110.2, 110.2, 116.4, 128.0", \ + "114.6, 114.6, 114.6, 120.9, 132.9", \ + "112.1, 112.1, 112.1, 118.5, 130.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("70.6, 70.6, 70.6, 78.4, 93.5", \ + "80.1, 80.1, 80.1, 87.9, 103.1", \ + "99.1, 99.1, 99.1, 106.9, 122.2", \ + "136.6, 136.6, 136.6, 144.3, 159.8", \ + "209.8, 209.8, 209.8, 217.5, 232.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("194.5, 194.5, 194.5, 200.5, 212.2", \ + "205.5, 205.5, 205.5, 211.3, 223.1", \ + "225.0, 225.0, 225.0, 230.6, 242.3", \ + "262.5, 262.5, 262.5, 268.1, 279.0", \ + "333.3, 333.3, 333.3, 339.0, 350.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("115.8, 115.8, 115.8, 119.4, 126.7", \ + "129.4, 129.4, 129.4, 133.1, 140.4", \ + "155.6, 155.6, 155.6, 159.4, 166.7", \ + "208.4, 208.4, 208.4, 212.3, 220.0", \ + "315.4, 315.4, 315.4, 319.2, 326.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("100.9, 100.9, 100.9, 106.8, 118.1", \ + "114.8, 114.8, 114.8, 120.9, 132.3", \ + "133.1, 133.1, 133.1, 139.3, 151.0", \ + "156.7, 156.7, 156.7, 163.0, 175.1", \ + "190.7, 190.7, 190.7, 197.1, 209.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("68.4, 68.4, 68.4, 76.1, 91.2", \ + "80.7, 80.7, 80.7, 88.4, 103.7", \ + "104.4, 104.4, 104.4, 112.2, 127.5", \ + "149.5, 149.5, 149.5, 157.2, 172.6", \ + "236.7, 236.7, 236.7, 244.4, 259.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("183.8, 183.8, 183.8, 189.9, 201.6", \ + "189.3, 189.3, 189.3, 195.2, 206.9", \ + "198.0, 198.0, 198.0, 203.6, 215.4", \ + "212.8, 212.8, 212.8, 218.4, 229.8", \ + "238.7, 238.7, 238.7, 244.4, 255.4"); + } + fall_transition (inslew_load_5x5__1) { + values ("109.6, 109.6, 109.6, 113.2, 120.4", \ + "119.9, 119.9, 119.9, 123.6, 130.8", \ + "140.1, 140.1, 140.1, 143.9, 151.2", \ + "181.2, 181.2, 181.2, 185.1, 192.6", \ + "265.3, 265.3, 265.3, 269.1, 276.8"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("83.3, 83.3, 83.3, 89.3, 100.3", \ + "85.4, 85.4, 85.4, 91.4, 102.7", \ + "82.9, 82.9, 82.9, 89.0, 100.5", \ + "67.3, 67.3, 67.3, 73.5, 85.2", \ + "23.1, 23.1, 23.1, 29.5, 41.7"); + } + rise_transition (inslew_load_5x5__1) { + values ("58.8, 58.8, 58.8, 66.5, 81.6", \ + "66.6, 66.6, 66.6, 74.3, 89.4", \ + "81.6, 81.6, 81.6, 89.3, 104.6", \ + "109.9, 109.9, 109.9, 117.7, 133.1", \ + "164.2, 164.2, 164.2, 171.9, 187.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("128.0, 128.0, 128.0, 134.1, 145.2", \ + "145.0, 145.0, 145.0, 151.0, 162.5", \ + "173.0, 173.0, 173.0, 178.9, 190.6", \ + "229.1, 229.1, 229.1, 234.6, 246.1", \ + "335.6, 335.6, 335.6, 341.3, 352.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("74.9, 74.9, 74.9, 78.6, 85.7", \ + "90.7, 90.7, 90.7, 94.4, 101.7", \ + "118.9, 118.9, 118.9, 122.6, 129.8", \ + "177.1, 177.1, 177.1, 181.0, 188.5", \ + "291.6, 291.6, 291.6, 295.4, 303.2"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("94.2, 94.2, 94.2, 100.2, 111.5", \ + "99.6, 99.6, 99.6, 105.6, 117.0", \ + "103.9, 103.9, 103.9, 110.1, 121.6", \ + "102.9, 102.9, 102.9, 109.2, 121.1", \ + "89.5, 89.5, 89.5, 95.8, 108.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("66.6, 66.6, 66.6, 74.3, 89.4", \ + "75.9, 75.9, 75.9, 83.6, 98.8", \ + "93.8, 93.8, 93.8, 101.6, 116.9", \ + "128.9, 128.9, 128.9, 136.6, 152.0", \ + "197.0, 197.0, 197.0, 204.7, 220.1"); + } + cell_fall (inslew_load_5x5__1) { + values ("162.0, 162.0, 162.0, 168.0, 179.6", \ + "174.2, 174.2, 174.2, 180.3, 192.0", \ + "195.2, 195.2, 195.2, 200.8, 212.6", \ + "236.3, 236.3, 236.3, 241.9, 253.0", \ + "314.2, 314.2, 314.2, 319.9, 330.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("95.9, 95.9, 95.9, 99.5, 106.8", \ + "110.9, 110.9, 110.9, 114.5, 121.7", \ + "138.2, 138.2, 138.2, 142.0, 149.3", \ + "194.2, 194.2, 194.2, 198.0, 205.6", \ + "306.1, 306.1, 306.1, 309.9, 317.6"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("77.8, 77.8, 77.8, 83.8, 94.6", \ + "84.6, 84.6, 84.6, 90.6, 101.7", \ + "87.7, 87.7, 87.7, 93.8, 105.2", \ + "80.0, 80.0, 80.0, 86.2, 97.9", \ + "49.7, 49.7, 49.7, 56.0, 68.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("52.7, 52.7, 52.7, 60.4, 75.5", \ + "62.3, 62.3, 62.3, 70.0, 85.1", \ + "79.7, 79.7, 79.7, 87.4, 102.6", \ + "111.4, 111.4, 111.4, 119.1, 134.5", \ + "171.2, 171.2, 171.2, 178.9, 194.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("111.0, 111.0, 111.0, 117.0, 127.8", \ + "125.4, 125.4, 125.4, 131.3, 142.6", \ + "150.2, 150.2, 150.2, 156.3, 167.9", \ + "193.2, 193.2, 193.2, 198.7, 210.5", \ + "270.3, 270.3, 270.3, 275.9, 286.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("66.0, 66.0, 66.0, 69.6, 76.8", \ + "77.7, 77.7, 77.7, 81.4, 88.5", \ + "101.7, 101.7, 101.7, 105.3, 112.6", \ + "149.3, 149.3, 149.3, 153.2, 160.5", \ + "243.1, 243.1, 243.1, 247.0, 254.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("699.8, 699.8, 699.8, 759.4, 878.6", \ + "778.0, 778.0, 778.0, 837.6, 956.8", \ + "935.4, 935.4, 935.4, 995.0, 1114.2", \ + "1247.8, 1247.8, 1247.8, 1307.4, 1426.6", \ + "1864.3, 1864.3, 1864.3, 1923.9, 2043.1"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1238.0, 1238.0, 1238.0, 1297.6, 1416.8", \ + "1376.5, 1376.5, 1376.5, 1436.1, 1555.3", \ + "1646.8, 1646.8, 1646.8, 1706.4, 1825.6", \ + "2190.7, 2190.7, 2190.7, 2250.3, 2369.5", \ + "3287.3, 3287.3, 3287.3, 3346.9, 3466.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("667.9, 667.9, 667.9, 727.5, 846.7", \ + "763.4, 763.4, 763.4, 823.0, 942.2", \ + "950.2, 950.2, 950.2, 1009.8, 1129.0", \ + "1312.4, 1312.4, 1312.4, 1372.0, 1491.2", \ + "2022.3, 2022.3, 2022.3, 2081.8, 2201.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1170.8, 1170.8, 1170.8, 1230.4, 1349.6", \ + "1276.2, 1276.2, 1276.2, 1335.8, 1455.0", \ + "1482.9, 1482.9, 1482.9, 1542.5, 1661.7", \ + "1902.0, 1902.0, 1902.0, 1961.6, 2080.8", \ + "2752.8, 2752.8, 2752.8, 2812.4, 2931.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__1) { + values ("577.3, 577.3, 577.3, 636.9, 756.1", \ + "635.4, 635.4, 635.4, 695.0, 814.2", \ + "750.0, 750.0, 750.0, 809.6, 928.8", \ + "971.1, 971.1, 971.1, 1030.7, 1149.9", \ + "1401.1, 1401.1, 1401.1, 1460.7, 1579.9"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("816.6, 816.6, 816.6, 876.2, 995.4", \ + "970.0, 970.0, 970.0, 1029.6, 1148.8", \ + "1253.0, 1253.0, 1253.0, 1312.6, 1431.7", \ + "1834.3, 1834.3, 1834.3, 1893.9, 2013.1", \ + "2983.7, 2983.7, 2983.7, 3043.3, 3162.5"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__1) { + values ("659.3, 659.3, 659.3, 718.9, 838.1", \ + "733.6, 733.6, 733.6, 793.2, 912.4", \ + "879.5, 879.5, 879.5, 939.1, 1058.3", \ + "1167.3, 1167.3, 1167.3, 1226.9, 1346.1", \ + "1733.4, 1733.4, 1733.4, 1793.0, 1912.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1031.2, 1031.2, 1031.2, 1090.8, 1210.0", \ + "1180.0, 1180.0, 1180.0, 1239.6, 1358.8", \ + "1460.7, 1460.7, 1460.7, 1520.3, 1639.5", \ + "2030.4, 2030.4, 2030.4, 2090.0, 2209.2", \ + "3170.6, 3170.6, 3170.6, 3230.2, 3349.4"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__1) { + values ("506.1, 506.1, 506.1, 565.7, 684.8", \ + "572.5, 572.5, 572.5, 632.1, 751.3", \ + "697.5, 697.5, 697.5, 757.0, 876.2", \ + "932.4, 932.4, 932.4, 992.0, 1111.2", \ + "1384.7, 1384.7, 1384.7, 1444.3, 1563.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("720.8, 720.8, 720.8, 780.4, 899.6", \ + "834.5, 834.5, 834.5, 894.1, 1013.3", \ + "1066.1, 1066.1, 1066.1, 1125.7, 1244.9", \ + "1529.3, 1529.3, 1529.3, 1588.9, 1708.1", \ + "2446.3, 2446.3, 2446.3, 2505.9, 2625.1"); + } + } + } + } + + cell (oa3ao322_x2) { + area : 0.0 ; + cell_leakage_power : 5.7 ; + leakage_power () { + when : "(i6 & i5 & i4 & i3 & i2 & i1 & i0)" ; + value : 6.1 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & ((i4 & (i5 ^ i6)) | (!(i4) & i5 & i6))) | (!(i3) & i4 & i5 & i6)))" ; + value : 4.4 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 2.7 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((!(i3) & !((i4 & i5)) & i6) | (!(i4) & !(i5) & i6)))" ; + value : 4.2 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((!(i3) & !((i4 & i5)) & !(i6)) | (!(i4) & !(i5) & !(i6))))" ; + value : 2.5 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & i4 & i5 & i6) | (!(i0) & i1 & i2 & i3 & i4 & i5 & i6))" ; + value : 7.7 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & !(i5) & i6))" ; + value : 6.5 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & (i3 ^ i4) & i5 & i6) | (!(i0) & i1 & i2 & (i3 ^ i4) & i5 & i6))" ; + value : 4.9 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3) & i4 & !(i5) & i6) | (!(i0) & i1 & i2 & !(i3) & i4 & !(i5) & i6))" ; + value : 4.8 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3) & !(i4) & i5 & i6) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5 & i6))" ; + value : 4.7 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & i5 & i6) | (!(i0) & (i1 ^ i2) & i3 & i4 & i5 & i6))" ; + value : 9.3 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & !(i5) & i6) | (!(i0) & (i1 ^ i2) & i3 & !(i5) & i6))" ; + value : 8.7 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))) | (!(i0) & (i1 ^ i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))))" ; + value : 5.4 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & i5 & i6) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & i5 & i6))" ; + value : 5.2 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & i3 & (i4 | !(i5)) & i6)" ; + value : 11 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6)))" ; + value : 6 ; + } + leakage_power () { + when : "(i6 & i5 & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.7 ; + } + leakage_power () { + when : "(!((i0 & i1 & i2)) & (!((i3 | i4 | i5)) | !(i6)))" ; + value : 2.6 ; + } + pin (i6) { + direction : input ; + capacitance : 3.36 ; + } + pin (i5) { + direction : input ; + capacitance : 4.87 ; + } + pin (i4) { + direction : input ; + capacitance : 4.77 ; + } + pin (i3) { + direction : input ; + capacitance : 4.79 ; + } + pin (i2) { + direction : input ; + capacitance : 4.51 ; + } + pin (i1) { + direction : input ; + capacitance : 4.41 ; + } + pin (i0) { + direction : input ; + capacitance : 4.28 ; + } + pin (q) { + function : "((i6 & ((i0 & i1 & i2) | i5 | i4 | i3)) | (i0 & i1 & i2))" ; + direction : output ; + capacitance : 3.00 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("70.2, 70.2, 70.2, 77.6, 91.0", \ + "69.0, 69.0, 69.0, 76.4, 90.0", \ + "62.7, 62.7, 62.7, 70.2, 84.3", \ + "43.8, 43.8, 43.8, 51.6, 66.1", \ + "-0.9, -0.9, -0.9, 7.0, 22.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("59.5, 59.5, 59.5, 69.2, 88.1", \ + "67.6, 67.6, 67.6, 77.2, 96.2", \ + "83.4, 83.4, 83.4, 93.1, 112.2", \ + "114.5, 114.5, 114.5, 124.2, 143.5", \ + "175.4, 175.4, 175.4, 185.2, 204.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("256.5, 256.5, 256.5, 263.8, 278.5", \ + "285.6, 285.6, 285.6, 292.9, 307.5", \ + "336.5, 336.5, 336.5, 343.7, 358.1", \ + "435.2, 435.2, 435.2, 442.5, 456.9", \ + "632.0, 632.0, 632.0, 639.4, 654.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("147.2, 147.2, 147.2, 152.2, 161.5", \ + "174.0, 174.0, 174.0, 179.0, 188.5", \ + "223.6, 223.6, 223.6, 228.6, 238.4", \ + "320.7, 320.7, 320.7, 325.6, 335.5", \ + "513.5, 513.5, 513.5, 518.4, 528.2"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("69.0, 69.0, 69.0, 76.3, 89.5", \ + "72.7, 72.7, 72.7, 80.1, 93.7", \ + "74.6, 74.6, 74.6, 82.1, 96.2", \ + "70.9, 70.9, 70.9, 78.6, 93.2", \ + "56.1, 56.1, 56.1, 64.0, 79.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("55.0, 55.0, 55.0, 64.6, 83.5", \ + "64.7, 64.7, 64.7, 74.3, 93.3", \ + "83.3, 83.3, 83.3, 93.0, 112.1", \ + "119.2, 119.2, 119.2, 129.0, 148.3", \ + "189.6, 189.6, 189.6, 199.3, 218.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("239.1, 239.1, 239.1, 246.5, 261.1", \ + "258.2, 258.2, 258.2, 265.5, 280.2", \ + "290.3, 290.3, 290.3, 297.6, 312.1", \ + "352.3, 352.3, 352.3, 359.7, 373.9", \ + "476.5, 476.5, 476.5, 483.9, 498.4"); + } + fall_transition (inslew_load_5x5__0) { + values ("137.3, 137.3, 137.3, 142.2, 151.5", \ + "158.4, 158.4, 158.4, 163.4, 172.8", \ + "197.6, 197.6, 197.6, 202.5, 212.2", \ + "274.0, 274.0, 274.0, 278.9, 288.8", \ + "425.8, 425.8, 425.8, 430.7, 440.6"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("66.0, 66.0, 66.0, 73.2, 86.3", \ + "73.8, 73.8, 73.8, 81.2, 94.7", \ + "82.4, 82.4, 82.4, 89.9, 104.0", \ + "91.8, 91.8, 91.8, 99.6, 114.1", \ + "103.8, 103.8, 103.8, 111.7, 127.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("50.0, 50.0, 50.0, 59.6, 78.5", \ + "61.3, 61.3, 61.3, 71.0, 89.9", \ + "82.2, 82.2, 82.2, 92.0, 111.1", \ + "122.2, 122.2, 122.2, 132.0, 151.3", \ + "200.6, 200.6, 200.6, 210.3, 229.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("220.2, 220.2, 220.2, 227.7, 242.2", \ + "232.1, 232.1, 232.1, 239.5, 254.1", \ + "250.8, 250.8, 250.8, 258.1, 272.7", \ + "286.5, 286.5, 286.5, 293.8, 308.0", \ + "358.4, 358.4, 358.4, 365.8, 380.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("126.5, 126.5, 126.5, 131.3, 140.7", \ + "143.6, 143.6, 143.6, 148.5, 157.9", \ + "175.3, 175.3, 175.3, 180.3, 189.8", \ + "237.0, 237.0, 237.0, 242.0, 251.9", \ + "359.8, 359.8, 359.8, 364.7, 374.6"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("82.5, 82.5, 82.5, 89.9, 103.3", \ + "83.7, 83.7, 83.7, 91.2, 104.9", \ + "79.8, 79.8, 79.8, 87.3, 101.4", \ + "62.6, 62.6, 62.6, 70.4, 84.9", \ + "17.8, 17.8, 17.8, 25.7, 40.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("60.3, 60.3, 60.3, 69.9, 88.9", \ + "68.9, 68.9, 68.9, 78.6, 97.6", \ + "85.1, 85.1, 85.1, 94.8, 113.9", \ + "115.8, 115.8, 115.8, 125.6, 144.9", \ + "175.2, 175.2, 175.2, 185.0, 204.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("105.7, 105.7, 105.7, 113.0, 125.9", \ + "124.4, 124.4, 124.4, 131.7, 145.4", \ + "148.5, 148.5, 148.5, 156.0, 170.3", \ + "201.6, 201.6, 201.6, 208.8, 223.6", \ + "303.9, 303.9, 303.9, 311.2, 325.4"); + } + fall_transition (inslew_load_5x5__0) { + values ("60.3, 60.3, 60.3, 65.1, 74.1", \ + "77.9, 77.9, 77.9, 82.6, 91.8", \ + "104.4, 104.4, 104.4, 109.1, 118.5", \ + "160.6, 160.6, 160.6, 165.6, 175.0", \ + "271.3, 271.3, 271.3, 276.2, 286.1"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("97.1, 97.1, 97.1, 104.5, 118.3", \ + "101.5, 101.5, 101.5, 109.0, 123.0", \ + "104.2, 104.2, 104.2, 111.8, 126.1", \ + "100.5, 100.5, 100.5, 108.3, 123.1", \ + "82.7, 82.7, 82.7, 90.6, 106.0"); + } + rise_transition (inslew_load_5x5__0) { + values ("70.6, 70.6, 70.6, 80.3, 99.3", \ + "80.7, 80.7, 80.7, 90.4, 109.5", \ + "99.7, 99.7, 99.7, 109.5, 128.7", \ + "136.6, 136.6, 136.6, 146.4, 165.7", \ + "208.6, 208.6, 208.6, 218.3, 237.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("148.7, 148.7, 148.7, 156.2, 170.0", \ + "161.8, 161.8, 161.8, 169.3, 183.5", \ + "181.9, 181.9, 181.9, 189.5, 203.9", \ + "222.9, 222.9, 222.9, 230.1, 244.7", \ + "301.5, 301.5, 301.5, 308.9, 323.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("85.6, 85.6, 85.6, 90.3, 99.5", \ + "101.0, 101.0, 101.0, 105.7, 115.1", \ + "127.5, 127.5, 127.5, 132.3, 141.7", \ + "181.8, 181.8, 181.8, 186.8, 196.3", \ + "290.9, 290.9, 290.9, 295.8, 305.7"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("106.4, 106.4, 106.4, 113.8, 127.8", \ + "115.2, 115.2, 115.2, 122.8, 137.0", \ + "126.8, 126.8, 126.8, 134.5, 149.0", \ + "142.0, 142.0, 142.0, 149.9, 164.9", \ + "163.8, 163.8, 163.8, 171.8, 187.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("77.4, 77.4, 77.4, 87.1, 106.2", \ + "90.0, 90.0, 90.0, 99.8, 118.9", \ + "113.9, 113.9, 113.9, 123.7, 142.9", \ + "160.7, 160.7, 160.7, 170.4, 189.9", \ + "252.7, 252.7, 252.7, 262.5, 281.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("184.9, 184.9, 184.9, 192.5, 206.8", \ + "193.8, 193.8, 193.8, 201.4, 215.9", \ + "207.4, 207.4, 207.4, 214.7, 229.4", \ + "232.1, 232.1, 232.1, 239.4, 253.8", \ + "279.8, 279.8, 279.8, 287.1, 301.4"); + } + fall_transition (inslew_load_5x5__0) { + values ("107.0, 107.0, 107.0, 111.7, 121.1", \ + "121.3, 121.3, 121.3, 126.1, 135.5", \ + "147.7, 147.7, 147.7, 152.6, 162.0", \ + "199.2, 199.2, 199.2, 204.2, 213.8", \ + "302.7, 302.7, 302.7, 307.6, 317.6"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("74.0, 74.0, 74.0, 81.2, 94.4", \ + "83.7, 83.7, 83.7, 91.1, 104.7", \ + "95.1, 95.1, 95.1, 102.7, 116.8", \ + "109.3, 109.3, 109.3, 117.1, 131.8", \ + "129.7, 129.7, 129.7, 137.6, 153.0"); + } + rise_transition (inslew_load_5x5__0) { + values ("52.4, 52.4, 52.4, 62.0, 80.9", \ + "64.8, 64.8, 64.8, 74.5, 93.4", \ + "87.6, 87.6, 87.6, 97.4, 116.5", \ + "131.0, 131.0, 131.0, 140.7, 160.1", \ + "215.7, 215.7, 215.7, 225.4, 244.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("67.9, 67.9, 67.9, 74.7, 87.0", \ + "73.8, 73.8, 73.8, 80.9, 93.4", \ + "82.8, 82.8, 82.8, 90.2, 103.5", \ + "92.8, 92.8, 92.8, 100.3, 114.6", \ + "106.6, 106.6, 106.6, 113.8, 128.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("40.7, 40.7, 40.7, 45.3, 54.0", \ + "49.3, 49.3, 49.3, 54.0, 63.0", \ + "67.7, 67.7, 67.7, 72.4, 81.5", \ + "102.7, 102.7, 102.7, 107.4, 116.8", \ + "171.4, 171.4, 171.4, 176.4, 185.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("467.0, 467.0, 467.0, 504.4, 579.4", \ + "520.8, 520.8, 520.8, 558.3, 633.2", \ + "628.3, 628.3, 628.3, 665.8, 740.7", \ + "842.5, 842.5, 842.5, 880.0, 954.9", \ + "1268.5, 1268.5, 1268.5, 1305.9, 1380.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("1016.0, 1016.0, 1016.0, 1053.5, 1128.4", \ + "1188.8, 1188.8, 1188.8, 1226.3, 1301.2", \ + "1519.8, 1519.8, 1519.8, 1557.2, 1632.2", \ + "2173.8, 2173.8, 2173.8, 2211.2, 2286.2", \ + "3476.8, 3476.8, 3476.8, 3514.3, 3589.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("423.8, 423.8, 423.8, 461.3, 536.2", \ + "485.1, 485.1, 485.1, 522.6, 597.5", \ + "606.6, 606.6, 606.6, 644.1, 719.0", \ + "846.8, 846.8, 846.8, 884.2, 959.2", \ + "1324.0, 1324.0, 1324.0, 1361.5, 1436.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("944.5, 944.5, 944.5, 982.0, 1056.9", \ + "1080.5, 1080.5, 1080.5, 1117.9, 1192.9", \ + "1341.1, 1341.1, 1341.1, 1378.5, 1453.5", \ + "1855.2, 1855.2, 1855.2, 1892.7, 1967.6", \ + "2879.9, 2879.9, 2879.9, 2917.3, 2992.3"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("378.6, 378.6, 378.6, 416.1, 491.0", \ + "446.4, 446.4, 446.4, 483.9, 558.8", \ + "578.5, 578.5, 578.5, 616.0, 690.9", \ + "839.0, 839.0, 839.0, 876.5, 951.4", \ + "1357.0, 1357.0, 1357.0, 1394.4, 1469.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("868.6, 868.6, 868.6, 906.1, 981.0", \ + "978.4, 978.4, 978.4, 1015.9, 1090.8", \ + "1188.7, 1188.7, 1188.7, 1226.2, 1301.1", \ + "1602.9, 1602.9, 1602.9, 1640.4, 1715.3", \ + "2429.5, 2429.5, 2429.5, 2467.0, 2541.9"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("360.1, 360.1, 360.1, 397.6, 472.5", \ + "399.4, 399.4, 399.4, 436.9, 511.8", \ + "475.7, 475.7, 475.7, 513.2, 588.1", \ + "624.5, 624.5, 624.5, 662.0, 736.9", \ + "917.1, 917.1, 917.1, 954.6, 1029.5"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("430.7, 430.7, 430.7, 468.1, 543.1", \ + "532.0, 532.0, 532.0, 569.5, 644.4", \ + "703.1, 703.1, 703.1, 740.6, 815.5", \ + "1058.4, 1058.4, 1058.4, 1095.9, 1170.8", \ + "1762.4, 1762.4, 1762.4, 1799.8, 1874.8"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__0) { + values ("429.5, 429.5, 429.5, 467.0, 541.9", \ + "478.5, 478.5, 478.5, 516.0, 590.9", \ + "573.6, 573.6, 573.6, 611.1, 686.0", \ + "761.1, 761.1, 761.1, 798.6, 873.5", \ + "1131.8, 1131.8, 1131.8, 1169.2, 1244.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("590.9, 590.9, 590.9, 628.4, 703.3", \ + "685.4, 685.4, 685.4, 722.9, 797.8", \ + "858.9, 858.9, 858.9, 896.4, 971.3", \ + "1211.0, 1211.0, 1211.0, 1248.4, 1323.4", \ + "1917.0, 1917.0, 1917.0, 1954.4, 2029.4"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__0) { + values ("477.8, 477.8, 477.8, 515.3, 590.2", \ + "542.9, 542.9, 542.9, 580.4, 655.3", \ + "669.8, 669.8, 669.8, 707.3, 782.2", \ + "921.6, 921.6, 921.6, 959.0, 1034.0", \ + "1421.4, 1421.4, 1421.4, 1458.8, 1533.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("733.3, 733.3, 733.3, 770.7, 845.7", \ + "824.1, 824.1, 824.1, 861.5, 936.5", \ + "997.2, 997.2, 997.2, 1034.7, 1109.6", \ + "1338.6, 1338.6, 1338.6, 1376.1, 1451.0", \ + "2023.5, 2023.5, 2023.5, 2061.0, 2135.9"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__0) { + values ("309.3, 309.3, 309.3, 346.8, 421.7", \ + "366.5, 366.5, 366.5, 403.9, 478.9", \ + "476.4, 476.4, 476.4, 513.9, 588.8", \ + "691.2, 691.2, 691.2, 728.7, 803.6", \ + "1116.4, 1116.4, 1116.4, 1153.9, 1228.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("328.5, 328.5, 328.5, 366.0, 440.9", \ + "387.7, 387.7, 387.7, 425.2, 500.1", \ + "509.5, 509.5, 509.5, 547.0, 621.9", \ + "747.4, 747.4, 747.4, 784.9, 859.8", \ + "1219.9, 1219.9, 1219.9, 1257.3, 1332.3"); + } + } + } + } + + cell (oa3ao322_x4) { + area : 0.0 ; + cell_leakage_power : 5.7 ; + leakage_power () { + when : "(i6 & i5 & i4 & i3 & i2 & i1 & i0)" ; + value : 6.1 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & ((i4 & (i5 ^ i6)) | (!(i4) & i5 & i6))) | (!(i3) & i4 & i5 & i6)))" ; + value : 4.4 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 2.7 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((!(i3) & !((i4 & i5)) & i6) | (!(i4) & !(i5) & i6)))" ; + value : 4.2 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((!(i3) & !((i4 & i5)) & !(i6)) | (!(i4) & !(i5) & !(i6))))" ; + value : 2.5 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & i4 & i5 & i6) | (!(i0) & i1 & i2 & i3 & i4 & i5 & i6))" ; + value : 7.7 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & !(i5) & i6))" ; + value : 6.5 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & (i3 ^ i4) & i5 & i6) | (!(i0) & i1 & i2 & (i3 ^ i4) & i5 & i6))" ; + value : 4.9 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3) & i4 & !(i5) & i6) | (!(i0) & i1 & i2 & !(i3) & i4 & !(i5) & i6))" ; + value : 4.8 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3) & !(i4) & i5 & i6) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5 & i6))" ; + value : 4.7 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & i5 & i6) | (!(i0) & (i1 ^ i2) & i3 & i4 & i5 & i6))" ; + value : 9.3 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & !(i5) & i6) | (!(i0) & (i1 ^ i2) & i3 & !(i5) & i6))" ; + value : 8.7 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))) | (!(i0) & (i1 ^ i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))))" ; + value : 5.4 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & i5 & i6) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & i5 & i6))" ; + value : 5.2 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & i3 & (i4 | !(i5)) & i6)" ; + value : 11 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6)))" ; + value : 6 ; + } + leakage_power () { + when : "(i6 & i5 & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.7 ; + } + leakage_power () { + when : "(!((i0 & i1 & i2)) & (!((i3 | i4 | i5)) | !(i6)))" ; + value : 3.2 ; + } + pin (i6) { + direction : input ; + capacitance : 3.36 ; + } + pin (i5) { + direction : input ; + capacitance : 4.87 ; + } + pin (i4) { + direction : input ; + capacitance : 4.77 ; + } + pin (i3) { + direction : input ; + capacitance : 4.79 ; + } + pin (i2) { + direction : input ; + capacitance : 4.51 ; + } + pin (i1) { + direction : input ; + capacitance : 4.41 ; + } + pin (i0) { + direction : input ; + capacitance : 4.31 ; + } + pin (q) { + function : "((i6 & ((i0 & i1 & i2) | i5 | i4 | i3)) | (i0 & i1 & i2))" ; + direction : output ; + capacitance : 4.44 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__24) { + values ("83.6, 83.6, 83.6, 89.2, 99.9", \ + "83.1, 83.1, 83.1, 88.8, 99.5", \ + "78.3, 78.3, 78.3, 84.1, 94.9", \ + "61.6, 61.6, 61.6, 67.5, 78.6", \ + "19.2, 19.2, 19.2, 25.2, 36.7"); + } + rise_transition (inslew_load_5x5__24) { + values ("69.4, 69.4, 69.4, 76.6, 90.7", \ + "77.2, 77.2, 77.2, 84.4, 98.6", \ + "93.1, 93.1, 93.1, 100.4, 114.6", \ + "124.7, 124.7, 124.7, 131.9, 146.2", \ + "186.5, 186.5, 186.5, 193.7, 208.1"); + } + cell_fall (inslew_load_5x5__24) { + values ("300.1, 300.1, 300.1, 305.3, 315.9", \ + "329.9, 329.9, 329.9, 335.2, 345.5", \ + "382.2, 382.2, 382.2, 387.5, 397.9", \ + "483.6, 483.6, 483.6, 489.0, 499.4", \ + "685.5, 685.5, 685.5, 690.9, 701.5"); + } + fall_transition (inslew_load_5x5__24) { + values ("175.1, 175.1, 175.1, 178.7, 185.8", \ + "202.7, 202.7, 202.7, 206.3, 213.5", \ + "253.8, 253.8, 253.8, 257.4, 264.6", \ + "354.0, 354.0, 354.0, 357.6, 364.7", \ + "553.0, 553.0, 553.0, 556.5, 563.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__24) { + values ("82.9, 82.9, 82.9, 88.4, 99.0", \ + "87.8, 87.8, 87.8, 93.5, 104.1", \ + "91.7, 91.7, 91.7, 97.4, 108.2", \ + "90.5, 90.5, 90.5, 96.3, 107.5", \ + "78.5, 78.5, 78.5, 84.4, 95.9"); + } + rise_transition (inslew_load_5x5__24) { + values ("64.8, 64.8, 64.8, 72.0, 86.1", \ + "74.4, 74.4, 74.4, 81.7, 95.8", \ + "93.4, 93.4, 93.4, 100.6, 114.9", \ + "129.9, 129.9, 129.9, 137.1, 151.5", \ + "201.4, 201.4, 201.4, 208.5, 222.9"); + } + cell_fall (inslew_load_5x5__24) { + values ("282.4, 282.4, 282.4, 287.6, 298.3", \ + "302.1, 302.1, 302.1, 307.4, 317.8", \ + "335.5, 335.5, 335.5, 340.8, 351.2", \ + "399.6, 399.6, 399.6, 405.0, 415.4", \ + "527.8, 527.8, 527.8, 533.2, 543.7"); + } + fall_transition (inslew_load_5x5__24) { + values ("164.9, 164.9, 164.9, 168.5, 175.5", \ + "186.6, 186.6, 186.6, 190.2, 197.3", \ + "226.9, 226.9, 226.9, 230.5, 237.7", \ + "305.7, 305.7, 305.7, 309.3, 316.5", \ + "462.4, 462.4, 462.4, 466.0, 473.1"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__24) { + values ("80.6, 80.6, 80.6, 86.1, 96.6", \ + "90.1, 90.1, 90.1, 95.7, 106.3", \ + "101.1, 101.1, 101.1, 106.9, 117.6", \ + "113.3, 113.3, 113.3, 119.2, 130.4", \ + "128.2, 128.2, 128.2, 134.1, 145.7"); + } + rise_transition (inslew_load_5x5__24) { + values ("60.1, 60.1, 60.1, 67.2, 81.4", \ + "71.2, 71.2, 71.2, 78.4, 92.6", \ + "92.6, 92.6, 92.6, 99.8, 114.1", \ + "133.4, 133.4, 133.4, 140.6, 154.9", \ + "212.9, 212.9, 212.9, 220.1, 234.4"); + } + cell_fall (inslew_load_5x5__24) { + values ("263.2, 263.2, 263.2, 268.4, 279.3", \ + "275.7, 275.7, 275.7, 281.0, 291.6", \ + "295.4, 295.4, 295.4, 300.7, 311.0", \ + "332.9, 332.9, 332.9, 338.2, 348.6", \ + "408.1, 408.1, 408.1, 413.5, 424.0"); + } + fall_transition (inslew_load_5x5__24) { + values ("153.7, 153.7, 153.7, 157.4, 164.3", \ + "171.3, 171.3, 171.3, 174.9, 181.9", \ + "203.9, 203.9, 203.9, 207.5, 214.8", \ + "267.6, 267.6, 267.6, 271.1, 278.4", \ + "394.2, 394.2, 394.2, 397.7, 404.8"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__24) { + values ("106.8, 106.8, 106.8, 112.5, 123.2", \ + "109.5, 109.5, 109.5, 115.3, 126.0", \ + "108.6, 108.6, 108.6, 114.4, 125.3", \ + "95.8, 95.8, 95.8, 101.6, 112.9", \ + "55.7, 55.7, 55.7, 61.7, 73.2"); + } + rise_transition (inslew_load_5x5__24) { + values ("77.2, 77.2, 77.2, 84.4, 98.6", \ + "85.6, 85.6, 85.6, 92.8, 107.1", \ + "101.8, 101.8, 101.8, 109.1, 123.4", \ + "133.5, 133.5, 133.5, 140.7, 155.1", \ + "194.3, 194.3, 194.3, 201.4, 215.8"); + } + cell_fall (inslew_load_5x5__24) { + values ("147.6, 147.6, 147.6, 153.2, 164.0", \ + "167.0, 167.0, 167.0, 172.7, 183.6", \ + "193.8, 193.8, 193.8, 199.2, 210.2", \ + "249.9, 249.9, 249.9, 255.1, 265.5", \ + "356.4, 356.4, 356.4, 361.8, 372.2"); + } + fall_transition (inslew_load_5x5__24) { + values ("86.1, 86.1, 86.1, 89.5, 96.4", \ + "104.1, 104.1, 104.1, 107.5, 114.3", \ + "131.0, 131.0, 131.0, 134.6, 141.4", \ + "188.6, 188.6, 188.6, 192.2, 199.3", \ + "302.6, 302.6, 302.6, 306.2, 313.4"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__24) { + values ("121.0, 121.0, 121.0, 126.7, 137.5", \ + "126.6, 126.6, 126.6, 132.4, 143.2", \ + "131.6, 131.6, 131.6, 137.4, 148.5", \ + "131.6, 131.6, 131.6, 137.5, 148.8", \ + "117.9, 117.9, 117.9, 123.9, 135.5"); + } + rise_transition (inslew_load_5x5__24) { + values ("87.6, 87.6, 87.6, 94.9, 109.1", \ + "97.3, 97.3, 97.3, 104.6, 118.9", \ + "116.5, 116.5, 116.5, 123.7, 138.0", \ + "154.1, 154.1, 154.1, 161.3, 175.7", \ + "227.4, 227.4, 227.4, 234.6, 248.9"); + } + cell_fall (inslew_load_5x5__24) { + values ("190.7, 190.7, 190.7, 196.4, 207.2", \ + "204.7, 204.7, 204.7, 210.2, 221.2", \ + "226.3, 226.3, 226.3, 231.5, 242.4", \ + "269.5, 269.5, 269.5, 274.8, 285.1", \ + "352.1, 352.1, 352.1, 357.4, 367.9"); + } + fall_transition (inslew_load_5x5__24) { + values ("112.0, 112.0, 112.0, 115.4, 122.2", \ + "127.6, 127.6, 127.6, 131.2, 138.0", \ + "154.7, 154.7, 154.7, 158.3, 165.2", \ + "210.3, 210.3, 210.3, 213.9, 221.1", \ + "322.5, 322.5, 322.5, 326.0, 333.2"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__24) { + values ("130.2, 130.2, 130.2, 136.0, 146.8", \ + "140.0, 140.0, 140.0, 145.8, 156.7", \ + "153.5, 153.5, 153.5, 159.3, 170.5", \ + "171.4, 171.4, 171.4, 177.3, 188.8", \ + "196.8, 196.8, 196.8, 202.7, 214.4"); + } + rise_transition (inslew_load_5x5__24) { + values ("94.5, 94.5, 94.5, 101.8, 116.0", \ + "106.8, 106.8, 106.8, 114.0, 128.3", \ + "130.8, 130.8, 130.8, 138.0, 152.3", \ + "178.2, 178.2, 178.2, 185.4, 199.7", \ + "271.5, 271.5, 271.5, 278.7, 293.0"); + } + cell_fall (inslew_load_5x5__24) { + values ("227.4, 227.4, 227.4, 232.8, 243.8", \ + "237.0, 237.0, 237.0, 242.3, 253.2", \ + "251.7, 251.7, 251.7, 257.0, 267.5", \ + "278.0, 278.0, 278.0, 283.3, 293.7", \ + "328.9, 328.9, 328.9, 334.2, 344.7"); + } + fall_transition (inslew_load_5x5__24) { + values ("133.7, 133.7, 133.7, 137.3, 144.1", \ + "148.3, 148.3, 148.3, 152.0, 158.9", \ + "175.5, 175.5, 175.5, 179.1, 186.2", \ + "228.4, 228.4, 228.4, 232.0, 239.2", \ + "334.9, 334.9, 334.9, 338.4, 345.6"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__24) { + values ("99.2, 99.2, 99.2, 104.8, 115.5", \ + "111.2, 111.2, 111.2, 116.9, 127.6", \ + "126.7, 126.7, 126.7, 132.5, 143.4", \ + "145.3, 145.3, 145.3, 151.1, 162.5", \ + "169.9, 169.9, 169.9, 175.9, 187.5"); + } + rise_transition (inslew_load_5x5__24) { + values ("69.4, 69.4, 69.4, 76.6, 90.8", \ + "81.6, 81.6, 81.6, 88.8, 103.0", \ + "104.9, 104.9, 104.9, 112.1, 126.4", \ + "149.4, 149.4, 149.4, 156.6, 171.0", \ + "235.8, 235.8, 235.8, 242.9, 257.3"); + } + cell_fall (inslew_load_5x5__24) { + values ("94.8, 94.8, 94.8, 100.3, 110.4", \ + "102.4, 102.4, 102.4, 108.0, 118.3", \ + "114.5, 114.5, 114.5, 120.1, 130.8", \ + "129.1, 129.1, 129.1, 134.6, 145.6", \ + "148.0, 148.0, 148.0, 153.3, 163.6"); + } + fall_transition (inslew_load_5x5__24) { + values ("57.9, 57.9, 57.9, 61.3, 68.0", \ + "66.6, 66.6, 66.6, 70.1, 76.8", \ + "85.2, 85.2, 85.2, 88.7, 95.5", \ + "121.8, 121.8, 121.8, 125.3, 132.1", \ + "193.0, 193.0, 193.0, 196.6, 203.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__24) { + values ("757.4, 757.4, 757.4, 812.9, 923.8", \ + "831.9, 831.9, 831.9, 887.4, 998.2", \ + "982.6, 982.6, 982.6, 1038.1, 1149.0", \ + "1283.3, 1283.3, 1283.3, 1338.8, 1449.7", \ + "1879.2, 1879.2, 1879.2, 1934.7, 2045.6"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("1810.8, 1810.8, 1810.8, 1866.3, 1977.2", \ + "2082.1, 2082.1, 2082.1, 2137.6, 2248.5", \ + "2595.6, 2595.6, 2595.6, 2651.1, 2762.0", \ + "3608.5, 3608.5, 3608.5, 3663.9, 3774.8", \ + "5624.1, 5624.1, 5624.1, 5679.5, 5790.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__24) { + values ("701.8, 701.8, 701.8, 757.2, 868.1", \ + "789.1, 789.1, 789.1, 844.6, 955.4", \ + "962.4, 962.4, 962.4, 1017.9, 1128.8", \ + "1303.2, 1303.2, 1303.2, 1358.6, 1469.5", \ + "1976.7, 1976.7, 1976.7, 2032.2, 2143.1"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("1702.5, 1702.5, 1702.5, 1758.0, 1868.9", \ + "1915.8, 1915.8, 1915.8, 1971.3, 2082.2", \ + "2320.6, 2320.6, 2320.6, 2376.1, 2487.0", \ + "3117.1, 3117.1, 3117.1, 3172.5, 3283.4", \ + "4702.6, 4702.6, 4702.6, 4758.0, 4868.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__24) { + values ("644.4, 644.4, 644.4, 699.9, 810.8", \ + "742.1, 742.1, 742.1, 797.5, 908.4", \ + "933.1, 933.1, 933.1, 988.6, 1099.5", \ + "1306.0, 1306.0, 1306.0, 1361.4, 1472.3", \ + "2042.6, 2042.6, 2042.6, 2098.1, 2209.0"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("1586.8, 1586.8, 1586.8, 1642.3, 1753.2", \ + "1759.0, 1759.0, 1759.0, 1814.4, 1925.3", \ + "2085.9, 2085.9, 2085.9, 2141.4, 2252.3", \ + "2728.0, 2728.0, 2728.0, 2783.4, 2894.3", \ + "4007.2, 4007.2, 4007.2, 4062.6, 4173.5"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__24) { + values ("690.8, 690.8, 690.8, 746.2, 857.1", \ + "752.3, 752.3, 752.3, 807.7, 918.6", \ + "872.8, 872.8, 872.8, 928.3, 1039.2", \ + "1109.7, 1109.7, 1109.7, 1165.2, 1276.1", \ + "1570.7, 1570.7, 1570.7, 1626.2, 1737.1"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("909.0, 909.0, 909.0, 964.4, 1075.3", \ + "1073.9, 1073.9, 1073.9, 1129.3, 1240.2", \ + "1340.5, 1340.5, 1340.5, 1395.9, 1506.8", \ + "1899.9, 1899.9, 1899.9, 1955.3, 2066.2", \ + "3012.2, 3012.2, 3012.2, 3067.6, 3178.5"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__24) { + values ("788.8, 788.8, 788.8, 844.3, 955.2", \ + "863.0, 863.0, 863.0, 918.4, 1029.3", \ + "1010.2, 1010.2, 1010.2, 1065.7, 1176.6", \ + "1301.6, 1301.6, 1301.6, 1357.0, 1467.9", \ + "1874.6, 1874.6, 1874.6, 1930.1, 2041.0"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("1160.8, 1160.8, 1160.8, 1216.2, 1327.1", \ + "1310.8, 1310.8, 1310.8, 1366.2, 1477.1", \ + "1580.2, 1580.2, 1580.2, 1635.6, 1746.5", \ + "2130.0, 2130.0, 2130.0, 2185.5, 2296.4", \ + "3236.2, 3236.2, 3236.2, 3291.7, 3402.6"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__24) { + values ("856.0, 856.0, 856.0, 911.5, 1022.4", \ + "953.6, 953.6, 953.6, 1009.0, 1119.9", \ + "1145.5, 1145.5, 1145.5, 1200.9, 1311.8", \ + "1527.3, 1527.3, 1527.3, 1582.7, 1693.6", \ + "2283.9, 2283.9, 2283.9, 2339.4, 2450.3"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("1380.0, 1380.0, 1380.0, 1435.4, 1546.3", \ + "1522.9, 1522.9, 1522.9, 1578.4, 1689.3", \ + "1793.1, 1793.1, 1793.1, 1848.6, 1959.5", \ + "2323.2, 2323.2, 2323.2, 2378.6, 2489.5", \ + "3388.0, 3388.0, 3388.0, 3443.4, 3554.3"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__24) { + values ("619.2, 619.2, 619.2, 674.7, 785.6", \ + "708.6, 708.6, 708.6, 764.0, 874.9", \ + "883.2, 883.2, 883.2, 938.6, 1049.5", \ + "1221.6, 1221.6, 1221.6, 1277.1, 1388.0", \ + "1885.3, 1885.3, 1885.3, 1940.8, 2051.7"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("678.5, 678.5, 678.5, 734.0, 844.9", \ + "768.2, 768.2, 768.2, 823.6, 934.5", \ + "954.9, 954.9, 954.9, 1010.3, 1121.2", \ + "1324.7, 1324.7, 1324.7, 1380.1, 1491.0", \ + "2053.6, 2053.6, 2053.6, 2109.0, 2219.9"); + } + } + } + } + + cell (on12_x1) { + area : 0.0 ; + cell_leakage_power : 0.75 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.52 ; + } + leakage_power () { + when : "i1" ; + value : 1.7 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.00016 ; + } + pin (i1) { + direction : input ; + capacitance : 3.28 ; + } + pin (i0) { + direction : input ; + capacitance : 4.41 ; + } + pin (q) { + function : "(i1 | !(i0))" ; + direction : output ; + capacitance : 3.07 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("55.4, 55.4, 55.4, 66.0, 85.8", \ + "63.4, 63.4, 63.4, 74.4, 94.8", \ + "71.9, 71.9, 71.9, 83.4, 104.8", \ + "82.1, 82.1, 82.1, 94.1, 116.7", \ + "97.3, 97.3, 97.3, 109.8, 133.7"); + } + rise_transition (inslew_load_5x5__9) { + values ("49.2, 49.2, 49.2, 67.0, 102.7", \ + "66.5, 66.5, 66.5, 84.4, 119.8", \ + "95.5, 95.5, 95.5, 113.5, 149.1", \ + "148.5, 148.5, 148.5, 166.6, 202.5", \ + "250.2, 250.2, 250.2, 268.4, 304.6"); + } + cell_fall (inslew_load_5x5__9) { + values ("45.6, 45.6, 45.6, 52.6, 65.2", \ + "49.0, 49.0, 49.0, 56.8, 70.5", \ + "51.6, 51.6, 51.6, 60.1, 75.6", \ + "52.6, 52.6, 52.6, 62.1, 79.6", \ + "50.7, 50.7, 50.7, 61.9, 81.4"); + } + fall_transition (inslew_load_5x5__9) { + values ("29.9, 29.9, 29.9, 36.8, 50.0", \ + "36.4, 36.4, 36.4, 43.5, 57.0", \ + "48.5, 48.5, 48.5, 55.9, 70.0", \ + "71.9, 71.9, 71.9, 79.6, 94.4", \ + "118.7, 118.7, 118.7, 126.4, 141.7"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__9) { + values ("26.8, 26.8, 26.8, 38.9, 60.3", \ + "42.3, 42.3, 42.3, 55.1, 78.4", \ + "69.9, 69.9, 69.9, 83.3, 108.4", \ + "123.3, 123.3, 123.3, 137.0, 163.5", \ + "228.9, 228.9, 228.9, 242.8, 270.2"); + } + rise_transition (inslew_load_5x5__9) { + values ("48.6, 48.6, 48.6, 66.9, 102.6", \ + "89.3, 89.3, 89.3, 107.7, 143.9", \ + "165.8, 165.8, 165.8, 184.3, 221.0", \ + "316.1, 316.1, 316.1, 334.8, 371.8", \ + "615.3, 615.3, 615.3, 634.0, 671.3"); + } + cell_fall (inslew_load_5x5__9) { + values ("5.0, 5.0, 5.0, 13.3, 26.8", \ + "-3.0, -3.0, -3.0, 6.9, 23.5", \ + "-20.7, -20.7, -20.7, -9.2, 10.6", \ + "-57.2, -57.2, -57.2, -44.6, -21.7", \ + "-131.1, -131.1, -131.1, -117.7, -92.6"); + } + fall_transition (inslew_load_5x5__9) { + values ("18.0, 18.0, 18.0, 25.3, 38.9", \ + "28.1, 28.1, 28.1, 35.9, 50.5", \ + "47.4, 47.4, 47.4, 55.8, 71.5", \ + "85.6, 85.6, 85.6, 94.4, 111.1", \ + "161.5, 161.5, 161.5, 170.6, 188.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__9) { + values ("214.2, 214.2, 214.2, 252.5, 329.3", \ + "261.7, 261.7, 261.7, 300.1, 376.8", \ + "354.2, 354.2, 354.2, 392.6, 469.4", \ + "536.9, 536.9, 536.9, 575.3, 652.0", \ + "900.3, 900.3, 900.3, 938.6, 1015.4"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("223.2, 223.2, 223.2, 261.6, 338.4", \ + "276.4, 276.4, 276.4, 314.7, 391.5", \ + "381.3, 381.3, 381.3, 419.7, 496.4", \ + "590.4, 590.4, 590.4, 628.8, 705.6", \ + "1008.3, 1008.3, 1008.3, 1046.6, 1123.4"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__9) { + values ("99.2, 99.2, 99.2, 137.6, 214.3", \ + "161.0, 161.0, 161.0, 199.3, 276.1", \ + "284.6, 284.6, 284.6, 322.9, 399.7", \ + "531.8, 531.8, 531.8, 570.1, 646.9", \ + "1026.1, 1026.1, 1026.1, 1064.5, 1141.3"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("63.2, 63.2, 63.2, 101.6, 178.3", \ + "87.0, 87.0, 87.0, 125.4, 202.2", \ + "134.7, 134.7, 134.7, 173.1, 249.8", \ + "230.0, 230.0, 230.0, 268.3, 345.1", \ + "420.6, 420.6, 420.6, 458.9, 535.7"); + } + } + } + } + + cell (on12_x4) { + area : 0.0 ; + cell_leakage_power : 3.2 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 4.3 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 4.9 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 2.6 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.98 ; + } + pin (i1) { + direction : input ; + capacitance : 5.56 ; + } + pin (i0) { + direction : input ; + capacitance : 3.30 ; + } + pin (q) { + function : "(!(i0) | i1)" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("58.7, 58.7, 58.7, 64.5, 74.8", \ + "67.2, 67.2, 67.2, 73.2, 83.8", \ + "76.6, 76.6, 76.6, 82.5, 93.8", \ + "87.4, 87.4, 87.4, 93.6, 105.2", \ + "102.0, 102.0, 102.0, 108.3, 120.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("35.4, 35.4, 35.4, 43.1, 58.0", \ + "47.2, 47.2, 47.2, 54.9, 69.9", \ + "68.4, 68.4, 68.4, 76.1, 91.2", \ + "108.0, 108.0, 108.0, 115.8, 131.1", \ + "185.2, 185.2, 185.2, 192.9, 208.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("65.5, 65.5, 65.5, 71.0, 81.0", \ + "72.4, 72.4, 72.4, 78.2, 88.3", \ + "81.0, 81.0, 81.0, 87.0, 97.9", \ + "92.5, 92.5, 92.5, 98.5, 110.2", \ + "111.8, 111.8, 111.8, 117.3, 128.6"); + } + fall_transition (inslew_load_5x5__1) { + values ("38.5, 38.5, 38.5, 42.1, 49.0", \ + "48.6, 48.6, 48.6, 52.2, 59.4", \ + "68.1, 68.1, 68.1, 71.8, 78.9", \ + "106.3, 106.3, 106.3, 109.9, 117.1", \ + "181.3, 181.3, 181.3, 185.2, 192.7"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("126.4, 126.4, 126.4, 132.4, 143.2", \ + "147.1, 147.1, 147.1, 153.1, 164.3", \ + "181.0, 181.0, 181.0, 187.1, 198.5", \ + "241.4, 241.4, 241.4, 247.6, 259.5", \ + "356.6, 356.6, 356.6, 363.0, 375.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("53.9, 53.9, 53.9, 61.6, 76.7", \ + "64.8, 64.8, 64.8, 72.4, 87.6", \ + "84.9, 84.9, 84.9, 92.6, 107.9", \ + "123.5, 123.5, 123.5, 131.2, 146.6", \ + "199.2, 199.2, 199.2, 206.9, 222.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("100.5, 100.5, 100.5, 106.2, 116.2", \ + "100.3, 100.3, 100.3, 106.1, 116.1", \ + "95.3, 95.3, 95.3, 101.2, 111.4", \ + "80.5, 80.5, 80.5, 86.4, 97.0", \ + "46.5, 46.5, 46.5, 52.5, 63.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("45.4, 45.4, 45.4, 49.0, 56.1", \ + "47.8, 47.8, 47.8, 51.4, 58.6", \ + "52.4, 52.4, 52.4, 56.0, 63.2", \ + "61.4, 61.4, 61.4, 65.0, 72.1", \ + "79.0, 79.0, 79.0, 82.7, 89.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("424.1, 424.1, 424.1, 483.7, 602.9", \ + "519.0, 519.0, 519.0, 578.6, 697.8", \ + "700.5, 700.5, 700.5, 760.1, 879.3", \ + "1053.3, 1053.3, 1053.3, 1112.9, 1232.1", \ + "1751.5, 1751.5, 1751.5, 1811.1, 1930.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("530.3, 530.3, 530.3, 589.9, 709.1", \ + "645.3, 645.3, 645.3, 704.9, 824.1", \ + "871.2, 871.2, 871.2, 930.8, 1050.0", \ + "1316.8, 1316.8, 1316.8, 1376.4, 1495.6", \ + "2203.2, 2203.2, 2203.2, 2262.8, 2382.0"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("740.2, 740.2, 740.2, 799.8, 919.0", \ + "877.6, 877.6, 877.6, 937.2, 1056.4", \ + "1142.2, 1142.2, 1142.2, 1201.8, 1321.0", \ + "1662.0, 1662.0, 1662.0, 1721.6, 1840.8", \ + "2693.4, 2693.4, 2693.4, 2753.0, 2872.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("733.4, 733.4, 733.4, 793.0, 912.2", \ + "788.2, 788.2, 788.2, 847.7, 966.9", \ + "894.0, 894.0, 894.0, 953.6, 1072.7", \ + "1102.8, 1102.8, 1102.8, 1162.4, 1281.6", \ + "1517.4, 1517.4, 1517.4, 1577.0, 1696.2"); + } + } + } + } + + cell (one_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + pin (q) { + function : "1" ; + direction : output ; + capacitance : 1.23 ; + } + } + + cell (sff1_x4) { + area : 0.0 ; + cell_leakage_power : 6.3 ; + pin (i) { + direction : input ; + capacitance : 2.98 ; + internal_power (energy_i) { + rise_power (energy_inslew_5__0) { + values ("231.8, 267.9, 339.1, 480.1, 761.5"); + } + fall_power (energy_inslew_5__0) { + values ("246.7, 301.6, 410.2, 626.7, 1059.0"); + } + } + } + pin (ck) { + direction : input ; + capacitance : 3.57 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("481.8, 521.9, 600.2, 754.6, 1061.4"); + } + fall_power (energy_inslew_5__0) { + values ("531.6, 590.6, 706.9, 938.3, 1400.2"); + } + } + } + pin (q) { + direction : output ; + capacitance : 8.20 ; + } + } + + cell (sff2_x4) { + area : 0.0 ; + cell_leakage_power : 8 ; + pin (i1) { + direction : input ; + capacitance : 3.22 ; + internal_power (energy_i1) { + rise_power (energy_inslew_5__0) { + values ("302.3, 339.4, 413.1, 559.6, 851.6"); + } + fall_power (energy_inslew_5__0) { + values ("363.2, 426.0, 550.3, 798.6, 1295.8"); + } + } + } + pin (i0) { + direction : input ; + capacitance : 2.97 ; + internal_power (energy_i0) { + rise_power (energy_inslew_5__0) { + values ("302.3, 339.4, 413.1, 559.6, 851.6"); + } + fall_power (energy_inslew_5__0) { + values ("363.2, 426.0, 550.3, 798.6, 1295.8"); + } + } + } + pin (cmd) { + direction : input ; + capacitance : 5.78 ; + internal_power (energy_cmd) { + rise_power (energy_inslew_5__0) { + values ("608.5, 649.6, 728.7, 882.7, 1188.4"); + } + fall_power (energy_inslew_5__0) { + values ("655.8, 710.8, 818.9, 1033.3, 1460.3"); + } + } + } + pin (ck) { + direction : input ; + capacitance : 3.55 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("481.4, 521.5, 599.8, 754.2, 1061.1"); + } + fall_power (energy_inslew_5__0) { + values ("531.3, 590.3, 706.6, 938.0, 1399.8"); + } + } + } + pin (q) { + direction : output ; + capacitance : 8.20 ; + } + } + + cell (sff3_x4) { + area : 0.0 ; + cell_leakage_power : 13 ; + pin (i2) { + direction : input ; + capacitance : 2.89 ; + internal_power (energy_i2) { + rise_power (energy_inslew_5__0) { + values ("358.5, 386.6, 441.9, 551.2, 767.8"); + } + fall_power (energy_inslew_5__0) { + values ("430.2, 481.7, 581.7, 781.6, 1182.4"); + } + } + } + pin (i1) { + direction : input ; + capacitance : 3.01 ; + internal_power (energy_i1) { + rise_power (energy_inslew_5__0) { + values ("358.5, 386.6, 441.9, 551.2, 767.8"); + } + fall_power (energy_inslew_5__0) { + values ("430.2, 481.7, 581.7, 781.6, 1182.4"); + } + } + } + pin (i0) { + direction : input ; + capacitance : 3.01 ; + internal_power (energy_i0) { + rise_power (energy_inslew_5__0) { + values ("298.1, 325.8, 379.5, 484.6, 692.5"); + } + fall_power (energy_inslew_5__0) { + values ("320.7, 367.7, 459.1, 641.2, 1004.1"); + } + } + } + pin (cmd1) { + direction : input ; + capacitance : 5.65 ; + internal_power (energy_cmd1) { + rise_power (energy_inslew_5__0) { + values ("714.1, 747.1, 808.6, 930.9, 1173.7"); + } + fall_power (energy_inslew_5__0) { + values ("751.6, 792.5, 872.2, 1029.4, 1341.7"); + } + } + } + pin (cmd0) { + direction : input ; + capacitance : 5.00 ; + internal_power (energy_cmd0) { + rise_power (energy_inslew_5__0) { + values ("979.3, 1019.7, 1096.0, 1244.7, 1538.8"); + } + fall_power (energy_inslew_5__0) { + values ("945.5, 998.5, 1102.4, 1308.4, 1718.7"); + } + } + } + pin (ck) { + direction : input ; + capacitance : 2.66 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("467.9, 504.9, 577.0, 719.1, 1001.3"); + } + fall_power (energy_inslew_5__0) { + values ("518.3, 573.7, 682.8, 899.5, 1332.1"); + } + } + } + pin (q) { + direction : output ; + capacitance : 8.19 ; + } + } + + cell (xr2_x1) { + area : 0.0 ; + cell_leakage_power : 4.3 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 3.9 ; + } + leakage_power () { + when : "(i0 ^ i1)" ; + value : 0.26 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 8.7 ; + } + pin (i1) { + direction : input ; + capacitance : 8.78 ; + } + pin (i0) { + direction : input ; + capacitance : 8.18 ; + } + pin (q) { + function : "(i0 ^ i1)" ; + direction : output ; + capacitance : 4.96 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__28) { + values ("50.8, 50.8, 50.8, 69.6, 105.0", \ + "55.6, 55.6, 55.6, 74.9, 111.0", \ + "59.0, 59.0, 59.0, 78.4, 115.7", \ + "60.3, 60.3, 60.3, 80.6, 119.4", \ + "57.4, 57.4, 57.4, 78.9, 119.5"); + } + rise_transition (inslew_load_5x5__28) { + values ("45.9, 45.9, 45.9, 77.2, 141.0", \ + "59.8, 59.8, 59.8, 91.1, 154.4", \ + "83.3, 83.3, 83.3, 113.7, 176.4", \ + "126.9, 126.9, 126.9, 157.4, 220.1", \ + "209.8, 209.8, 209.8, 241.0, 302.6"); + } + cell_fall (inslew_load_5x5__28) { + values ("53.8, 53.8, 53.8, 66.9, 88.7", \ + "61.1, 61.1, 61.1, 75.2, 99.1", \ + "71.1, 71.1, 71.1, 86.6, 113.2", \ + "86.4, 86.4, 86.4, 103.9, 133.6", \ + "115.1, 115.1, 115.1, 132.5, 166.9"); + } + fall_transition (inslew_load_5x5__28) { + values ("31.7, 31.7, 31.7, 43.7, 66.6", \ + "40.2, 40.2, 40.2, 52.4, 75.7", \ + "55.9, 55.9, 55.9, 68.7, 92.7", \ + "86.6, 86.6, 86.6, 99.6, 124.7", \ + "147.3, 147.3, 147.3, 160.6, 186.3"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__28) { + values ("61.9, 61.9, 61.9, 80.2, 115.5", \ + "69.1, 69.1, 69.1, 87.7, 123.5", \ + "75.7, 75.7, 75.7, 94.9, 131.5", \ + "83.4, 83.4, 83.4, 103.0, 140.8", \ + "92.6, 92.6, 92.6, 112.8, 152.1"); + } + rise_transition (inslew_load_5x5__28) { + values ("62.2, 62.2, 62.2, 93.6, 157.7", \ + "79.1, 79.1, 79.1, 110.2, 173.8", \ + "106.4, 106.4, 106.4, 137.8, 200.4", \ + "158.7, 158.7, 158.7, 189.5, 252.3", \ + "258.8, 258.8, 258.8, 289.4, 351.3"); + } + cell_fall (inslew_load_5x5__28) { + values ("56.9, 56.9, 56.9, 67.9, 87.5", \ + "62.8, 62.8, 62.8, 74.7, 95.7", \ + "69.7, 69.7, 69.7, 82.8, 105.9", \ + "78.8, 78.8, 78.8, 93.1, 119.2", \ + "93.1, 93.1, 93.1, 109.1, 137.6"); + } + fall_transition (inslew_load_5x5__28) { + values ("36.0, 36.0, 36.0, 47.5, 70.0", \ + "42.7, 42.7, 42.7, 54.4, 77.1", \ + "55.2, 55.2, 55.2, 67.3, 90.5", \ + "79.5, 79.5, 79.5, 92.1, 116.0", \ + "126.9, 126.9, 126.9, 140.0, 165.4"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__28) { + values ("68.5, 68.5, 68.5, 86.0, 120.8", \ + "79.0, 79.0, 79.0, 96.8, 131.9", \ + "97.7, 97.7, 97.7, 115.8, 151.9", \ + "134.2, 134.2, 134.2, 152.7, 189.2", \ + "206.3, 206.3, 206.3, 225.1, 262.3"); + } + rise_transition (inslew_load_5x5__28) { + values ("133.9, 133.9, 133.9, 164.9, 227.2", \ + "179.6, 179.6, 179.6, 210.3, 271.9", \ + "268.2, 268.2, 268.2, 298.3, 359.0", \ + "444.8, 444.8, 444.8, 474.5, 534.3", \ + "798.2, 798.2, 798.2, 827.8, 886.9"); + } + cell_fall (inslew_load_5x5__28) { + values ("29.1, 29.1, 29.1, 38.4, 56.1", \ + "29.3, 29.3, 29.3, 39.6, 59.1", \ + "26.2, 26.2, 26.2, 37.9, 59.8", \ + "17.1, 17.1, 17.1, 30.1, 54.6", \ + "-3.1, -3.1, -3.1, 10.6, 37.2"); + } + fall_transition (inslew_load_5x5__28) { + values ("43.6, 43.6, 43.6, 54.9, 77.4", \ + "59.6, 59.6, 59.6, 71.0, 93.4", \ + "90.7, 90.7, 90.7, 102.3, 125.1", \ + "151.9, 151.9, 151.9, 163.8, 187.2", \ + "273.5, 273.5, 273.5, 285.7, 309.7"); + } + } + timing (maxd_q_i1_negative_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__28) { + values ("56.4, 56.4, 56.4, 74.1, 108.9", \ + "60.4, 60.4, 60.4, 78.6, 114.1", \ + "66.8, 66.8, 66.8, 85.4, 121.8", \ + "78.3, 78.3, 78.3, 97.6, 135.1", \ + "100.3, 100.3, 100.3, 120.0, 158.7"); + } + rise_transition (inslew_load_5x5__28) { + values ("113.0, 113.0, 113.0, 143.8, 205.9", \ + "148.7, 148.7, 148.7, 179.1, 240.3", \ + "218.3, 218.3, 218.3, 248.2, 308.4", \ + "355.2, 355.2, 355.2, 385.1, 446.4", \ + "630.2, 630.2, 630.2, 660.1, 719.8"); + } + cell_fall (inslew_load_5x5__28) { + values ("28.6, 28.6, 28.6, 38.9, 57.8", \ + "33.0, 33.0, 33.0, 44.8, 66.2", \ + "38.2, 38.2, 38.2, 51.5, 76.0", \ + "46.0, 46.0, 46.0, 60.5, 87.9", \ + "59.7, 59.7, 59.7, 75.0, 104.6"); + } + fall_transition (inslew_load_5x5__28) { + values ("38.3, 38.3, 38.3, 49.7, 72.4", \ + "57.1, 57.1, 57.1, 68.9, 91.9", \ + "92.9, 92.9, 92.9, 105.1, 128.9", \ + "163.3, 163.3, 163.3, 175.9, 200.5", \ + "303.3, 303.3, 303.3, 316.1, 341.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__28) { + values ("210.3, 210.3, 210.3, 272.3, 396.4", \ + "254.6, 254.6, 254.6, 316.7, 440.8", \ + "341.2, 341.2, 341.2, 403.3, 527.4", \ + "512.7, 512.7, 512.7, 574.8, 698.9", \ + "854.1, 854.1, 854.1, 916.2, 1040.3"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("237.2, 237.2, 237.2, 299.2, 423.3", \ + "297.8, 297.8, 297.8, 359.8, 483.9", \ + "417.6, 417.6, 417.6, 479.7, 603.8", \ + "656.2, 656.2, 656.2, 718.3, 842.4", \ + "1132.8, 1132.8, 1132.8, 1194.9, 1319.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__28) { + values ("253.9, 253.9, 253.9, 316.0, 440.1", \ + "302.9, 302.9, 302.9, 364.9, 489.0", \ + "398.0, 398.0, 398.0, 460.1, 584.2", \ + "586.0, 586.0, 586.0, 648.0, 772.1", \ + "959.8, 959.8, 959.8, 1021.8, 1145.9"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("278.6, 278.6, 278.6, 340.6, 464.7", \ + "337.2, 337.2, 337.2, 399.2, 523.3", \ + "453.1, 453.1, 453.1, 515.2, 639.3", \ + "684.1, 684.1, 684.1, 746.1, 870.2", \ + "1145.2, 1145.2, 1145.2, 1207.3, 1331.4"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__28) { + values ("262.0, 262.0, 262.0, 324.0, 448.1", \ + "341.7, 341.7, 341.7, 403.8, 527.9", \ + "501.3, 501.3, 501.3, 563.3, 687.4", \ + "820.4, 820.4, 820.4, 882.4, 1006.5", \ + "1458.5, 1458.5, 1458.5, 1520.6, 1644.7"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("206.9, 206.9, 206.9, 269.0, 393.1", \ + "259.4, 259.4, 259.4, 321.4, 445.5", \ + "364.3, 364.3, 364.3, 426.4, 550.5", \ + "574.2, 574.2, 574.2, 636.3, 760.4", \ + "994.1, 994.1, 994.1, 1056.1, 1180.2"); + } + } + internal_power (energy_neg_q_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__28) { + values ("217.1, 217.1, 217.1, 279.1, 403.2", \ + "277.1, 277.1, 277.1, 339.1, 463.2", \ + "397.0, 397.0, 397.0, 459.1, 583.2", \ + "637.0, 637.0, 637.0, 699.0, 823.1", \ + "1116.9, 1116.9, 1116.9, 1178.9, 1303.0"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("173.4, 173.4, 173.4, 235.5, 359.6", \ + "229.7, 229.7, 229.7, 291.8, 415.9", \ + "342.4, 342.4, 342.4, 404.4, 528.5", \ + "567.7, 567.7, 567.7, 629.7, 753.8", \ + "1018.2, 1018.2, 1018.2, 1080.3, 1204.4"); + } + } + } + } + + cell (xr2_x4) { + area : 0.0 ; + cell_leakage_power : 5.3 ; + leakage_power () { + when : "i0" ; + value : 3.7 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 9 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 3.2 ; + } + pin (i1) { + direction : input ; + capacitance : 8.69 ; + } + pin (i0) { + direction : input ; + capacitance : 8.28 ; + } + pin (q) { + function : "(i0 ^ i1)" ; + direction : output ; + capacitance : 4.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("67.7, 67.7, 67.7, 73.6, 84.4", \ + "72.5, 72.5, 72.5, 78.5, 89.6", \ + "77.0, 77.0, 77.0, 83.1, 94.5", \ + "79.4, 79.4, 79.4, 85.6, 97.5", \ + "78.1, 78.1, 78.1, 84.5, 96.8"); + } + rise_transition (inslew_load_5x5__1) { + values ("50.1, 50.1, 50.1, 57.8, 72.8", \ + "60.6, 60.6, 60.6, 68.3, 83.5", \ + "80.9, 80.9, 80.9, 88.7, 104.0", \ + "120.3, 120.3, 120.3, 128.1, 143.5", \ + "197.8, 197.8, 197.8, 205.5, 220.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("108.4, 108.4, 108.4, 114.4, 125.4", \ + "117.8, 117.8, 117.8, 123.8, 135.1", \ + "133.9, 133.9, 133.9, 140.0, 151.7", \ + "164.4, 164.4, 164.4, 170.0, 181.6", \ + "224.1, 224.1, 224.1, 229.8, 241.0"); + } + fall_transition (inslew_load_5x5__1) { + values ("67.3, 67.3, 67.3, 71.0, 78.2", \ + "81.5, 81.5, 81.5, 85.2, 92.4", \ + "109.1, 109.1, 109.1, 112.7, 120.0", \ + "164.0, 164.0, 164.0, 168.0, 175.4", \ + "274.5, 274.5, 274.5, 278.3, 286.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("54.7, 54.7, 54.7, 60.5, 71.0", \ + "53.4, 53.4, 53.4, 59.3, 70.0", \ + "44.6, 44.6, 44.6, 50.6, 61.8", \ + "18.9, 18.9, 18.9, 25.0, 36.5", \ + "-41.5, -41.5, -41.5, -35.3, -23.2"); + } + rise_transition (inslew_load_5x5__1) { + values ("41.2, 41.2, 41.2, 48.8, 63.8", \ + "48.7, 48.7, 48.7, 56.4, 71.5", \ + "62.9, 62.9, 62.9, 70.6, 85.7", \ + "89.2, 89.2, 89.2, 97.0, 112.3", \ + "139.7, 139.7, 139.7, 147.5, 162.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("87.6, 87.6, 87.6, 93.5, 103.8", \ + "106.0, 106.0, 106.0, 112.0, 122.9", \ + "137.8, 137.8, 137.8, 143.8, 155.4", \ + "196.1, 196.1, 196.1, 201.8, 213.5", \ + "308.8, 308.8, 308.8, 314.5, 325.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("51.0, 51.0, 51.0, 54.7, 61.9", \ + "66.7, 66.7, 66.7, 70.4, 77.6", \ + "96.5, 96.5, 96.5, 100.2, 107.5", \ + "154.9, 154.9, 154.9, 158.8, 166.2", \ + "270.7, 270.7, 270.7, 274.6, 282.3"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("97.1, 97.1, 97.1, 103.0, 113.5", \ + "108.3, 108.3, 108.3, 114.2, 124.9", \ + "124.0, 124.0, 124.0, 130.0, 141.0", \ + "147.7, 147.7, 147.7, 153.8, 165.2", \ + "187.9, 187.9, 187.9, 194.2, 206.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("42.9, 42.9, 42.9, 50.6, 65.6", \ + "48.9, 48.9, 48.9, 56.6, 71.6", \ + "59.7, 59.7, 59.7, 67.4, 82.5", \ + "80.1, 80.1, 80.1, 87.9, 103.1", \ + "119.2, 119.2, 119.2, 126.9, 142.3"); + } + cell_fall (inslew_load_5x5__1) { + values ("96.1, 96.1, 96.1, 101.7, 111.8", \ + "101.3, 101.3, 101.3, 107.1, 117.1", \ + "104.9, 104.9, 104.9, 110.7, 121.0", \ + "106.2, 106.2, 106.2, 112.1, 123.0", \ + "102.3, 102.3, 102.3, 108.3, 119.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("40.0, 40.0, 40.0, 43.7, 50.7", \ + "44.2, 44.2, 44.2, 47.8, 55.0", \ + "51.3, 51.3, 51.3, 55.0, 62.2", \ + "64.9, 64.9, 64.9, 68.6, 75.8", \ + "91.3, 91.3, 91.3, 95.0, 102.3"); + } + } + timing (maxd_q_i1_negative_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("115.0, 115.0, 115.0, 121.0, 131.9", \ + "130.5, 130.5, 130.5, 136.5, 147.6", \ + "154.7, 154.7, 154.7, 160.8, 172.2", \ + "195.5, 195.5, 195.5, 201.7, 213.3", \ + "269.8, 269.8, 269.8, 276.1, 288.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("53.4, 53.4, 53.4, 61.0, 76.1", \ + "61.3, 61.3, 61.3, 69.0, 84.1", \ + "75.8, 75.8, 75.8, 83.6, 98.8", \ + "103.5, 103.5, 103.5, 111.3, 126.6", \ + "157.8, 157.8, 157.8, 165.5, 181.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("120.6, 120.6, 120.6, 126.5, 137.0", \ + "122.9, 122.9, 122.9, 128.8, 139.5", \ + "121.3, 121.3, 121.3, 127.3, 138.2", \ + "113.0, 113.0, 113.0, 119.0, 130.2", \ + "91.7, 91.7, 91.7, 97.8, 109.4"); + } + fall_transition (inslew_load_5x5__1) { + values ("56.1, 56.1, 56.1, 59.8, 67.0", \ + "59.8, 59.8, 59.8, 63.5, 70.6", \ + "65.8, 65.8, 65.8, 69.5, 76.8", \ + "77.3, 77.3, 77.3, 81.0, 88.3", \ + "99.9, 99.9, 99.9, 103.6, 110.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__1) { + values ("636.7, 636.7, 636.7, 696.3, 815.5", \ + "745.0, 745.0, 745.0, 804.6, 923.8", \ + "959.6, 959.6, 959.6, 1019.2, 1138.4", \ + "1383.8, 1383.8, 1383.8, 1443.4, 1562.6", \ + "2227.4, 2227.4, 2227.4, 2287.0, 2406.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("922.4, 922.4, 922.4, 982.0, 1101.1", \ + "1102.8, 1102.8, 1102.8, 1162.4, 1281.6", \ + "1458.4, 1458.4, 1458.4, 1518.0, 1637.2", \ + "2171.3, 2171.3, 2171.3, 2230.9, 2350.1", \ + "3600.3, 3600.3, 3600.3, 3659.9, 3779.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__1) { + values ("512.0, 512.0, 512.0, 571.6, 690.8", \ + "578.3, 578.3, 578.3, 637.9, 757.1", \ + "707.4, 707.4, 707.4, 767.0, 886.2", \ + "958.0, 958.0, 958.0, 1017.6, 1136.8", \ + "1450.4, 1450.4, 1450.4, 1510.0, 1629.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("705.2, 705.2, 705.2, 764.8, 884.0", \ + "891.3, 891.3, 891.3, 950.9, 1070.1", \ + "1253.2, 1253.2, 1253.2, 1312.8, 1432.0", \ + "1970.4, 1970.4, 1970.4, 2030.0, 2149.2", \ + "3399.1, 3399.1, 3399.1, 3458.7, 3577.9"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("629.6, 629.6, 629.6, 689.2, 808.4", \ + "721.4, 721.4, 721.4, 781.0, 900.2", \ + "898.5, 898.5, 898.5, 958.1, 1077.3", \ + "1247.0, 1247.0, 1247.0, 1306.6, 1425.8", \ + "1936.2, 1936.2, 1936.2, 1995.8, 2115.0"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("677.0, 677.0, 677.0, 736.6, 855.8", \ + "750.9, 750.9, 750.9, 810.5, 929.7", \ + "888.2, 888.2, 888.2, 947.8, 1067.0", \ + "1156.0, 1156.0, 1156.0, 1215.6, 1334.8", \ + "1685.0, 1685.0, 1685.0, 1744.6, 1863.8"); + } + } + internal_power (energy_neg_q_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("780.6, 780.6, 780.6, 840.2, 959.4", \ + "898.4, 898.4, 898.4, 958.0, 1077.2", \ + "1126.0, 1126.0, 1126.0, 1185.6, 1304.8", \ + "1572.7, 1572.7, 1572.7, 1632.3, 1751.5", \ + "2460.6, 2460.6, 2460.6, 2520.2, 2639.4"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("894.2, 894.2, 894.2, 953.8, 1073.0", \ + "964.9, 964.9, 964.9, 1024.5, 1143.7", \ + "1095.2, 1095.2, 1095.2, 1154.8, 1274.0", \ + "1348.9, 1348.9, 1348.9, 1408.5, 1527.7", \ + "1852.0, 1852.0, 1852.0, 1911.6, 2030.8"); + } + } + } + } + + cell (zero_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + pin (nq) { + function : "0" ; + direction : output ; + capacitance : 1.21 ; + } + } + + cell (rowend_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + } + + cell (tie_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + } + +} diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/lsxlib.py b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/lsxlib.py new file mode 100644 index 000000000..c17cabed5 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/lsxlib.py @@ -0,0 +1,219 @@ + +import sys +import os.path +from coriolis import Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, \ + BasicLayer, Cell, Net, Horizontal, Vertical, \ + Rectilinear, Box, Point, Instance, Transformation, \ + NetExternalComponents, Pad +import coriolis.Viewer +from coriolis.CRL import AllianceFramework, Environment, Gds, LefImport, \ + CellGauge, RoutingGauge, RoutingLayerGauge +from coriolis.helpers import l, u, n, overlay, io, ndaTopDir +from coriolis.helpers.overlay import CfgCache, UpdateSession +from coriolis.Anabatic import StyleFlags + + +__all__ = [ "setup" ] + + +def _routing (): + """ + Define the routing gauge along with the various P&R tool parameters. + """ + af = AllianceFramework.get() + db = DataBase.getDB() + tech = db.getTechnology() + rg = RoutingGauge.create('lsxlib') + rg.setSymbolic( True ) + dirM1 = RoutingLayerGauge.Vertical + dirM2 = RoutingLayerGauge.Horizontal + netBuilderStyle = 'HV,3RL+' + routingStyle = StyleFlags.HV + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL1' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.PinOnly # layer usage + , 0 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(5.0) # track pitch + , l( 2.0) # wire width + , l( 2.0) # perpandicular wire width + , l( 1.0) # VIA side + , l( 3.5) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL2' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 1 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(5.0) # track pitch + , l( 2.0) # wire width + , l( 2.0) # perpandicular wire width + , l( 1.0) # VIA side + , l( 4.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL3' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 2 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(5.0) # track pitch + , l( 2.0) # wire width + , l( 2.0) # perpandicular wire width + , l( 1.0) # VIA side + , l( 4.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL4' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 3 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(5.0) # track pitch + , l( 2.0) # wire width + , l( 2.0) # perpandicular wire width + , l( 1.0) # VIA side + , l( 4.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL5' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 4 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(5.0) # track pitch + , l( 2.0) # wire width + , l( 2.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 4.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL6' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.PowerSupply # layer usage + , 5 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(7.5) # track pitch + , l(6.0) # wire width + , l(6.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 4.0 ) )) # obstacle dW + af.addRoutingGauge( rg ) + af.setRoutingGauge( 'lsxlib' ) + + cg = CellGauge.create( 'lsxlib' + , 'METAL1' # pin layer name. + , l( 5.0) # pitch. + , l(50.0) # cell slice height. + , l( 5.0) # cell slice step. + ) + af.addCellGauge( cg ) + af.setCellGauge( 'lsxlib' ) + + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + # Place & Route setup + cfg.viewer.minimumSize = 500 + cfg.viewer.pixelThreshold = 2 + cfg.lefImport.minTerminalWidth = 0.0 + cfg.crlcore.groundName = 'vss' + cfg.crlcore.powerName = 'vdd' + cfg.etesian.bloat = 'disabled' + cfg.etesian.aspectRatio = 1.00 + cfg.etesian.aspectRatio = [10, 1000] + cfg.etesian.spaceMargin = 0.10 + cfg.etesian.densityVariation = 0.05 + cfg.etesian.routingDriven = False + cfg.etesian.latchUpDistance = l(1000.0) + #cfg.etesian.diodeName = 'diode' + #cfg.etesian.antennaInsertThreshold = 0.50 + #cfg.etesian.antennaMaxWL = u(250.0) + cfg.etesian.feedNames = 'tie_x0,rowend_x0' + cfg.etesian.defaultFeed = 'tie_x0' + cfg.etesian.cell.zero = 'zero_x0' + cfg.etesian.cell.one = 'one_x0' + cfg.etesian.effort = 2 + cfg.etesian.effort = ( ('Fast' , 1) + , ('Standard', 2) + , ('High' , 3) + , ('Extreme' , 4) + ) + cfg.etesian.graphics = 2 + cfg.etesian.graphics = ( ('Show every step' , 1) + , ('Show lower bound', 2) + , ('Show result only', 3) + ) + cfg.anabatic.routingGauge = 'lsxlib' + cfg.anabatic.cellGauge = 'lsxlib' + cfg.anabatic.globalLengthThreshold = 30*l(50.0) + cfg.anabatic.saturateRatio = 0.90 + cfg.anabatic.saturateRp = 10 + cfg.anabatic.topRoutingLayer = 'METAL5' + cfg.anabatic.edgeLength = 24 + cfg.anabatic.edgeWidth = 4 + cfg.anabatic.edgeCostH = 9.0 + cfg.anabatic.edgeCostK = -10.0 + cfg.anabatic.edgeHInc = 1.0 + cfg.anabatic.edgeHScaling = 1.0 + cfg.anabatic.globalIterations = 10 + cfg.anabatic.globalIterations = [ 1, 100 ] + cfg.anabatic.gcell.displayMode = 1 + cfg.anabatic.gcell.displayMode = (("Boundary", 1), ("Density", 2)) + cfg.anabatic.netBuilderStyle = netBuilderStyle + cfg.anabatic.routingStyle = routingStyle + cfg.katana.disableStackedVias = False + cfg.katana.hTracksReservedMin = 4 + cfg.katana.hTracksReservedLocal = 11 + cfg.katana.hTracksReservedLocal = [0, 20] + cfg.katana.vTracksReservedMin = 4 + cfg.katana.vTracksReservedLocal = 11 + cfg.katana.vTracksReservedLocal = [0, 20] + cfg.katana.termSatReservedLocal = 8 + cfg.katana.termSatThreshold = 9 + cfg.katana.eventsLimit = 4000002 + cfg.katana.ripupCost = 3 + cfg.katana.ripupCost = [0, None] + cfg.katana.strapRipupLimit = 16 + cfg.katana.strapRipupLimit = [1, None] + cfg.katana.localRipupLimit = 9 + cfg.katana.localRipupLimit = [1, None] + cfg.katana.globalRipupLimit = 5 + cfg.katana.globalRipupLimit = [1, None] + cfg.katana.longGlobalRipupLimit = 5 + cfg.chip.padCoreSide = 'North' + # Plugins setup + cfg.clockTree.minimumSide = l(50.0) * 6 + cfg.clockTree.buffer = 'buf_x8' + cfg.clockTree.placerEngine = 'Etesian' + cfg.block.spareSide = 10*l(50.0) + cfg.spares.buffer = 'buf_x8' + cfg.spares.maxSinks = 31 + + +def _loadLsxlib ( cellsTop ): + """ + Setup for NSXLIB2 Alliance library. It is an symbolic library + from which cells are loaded on demand, so we only setup pathes. + + :param cellsTop: The top directory containing the cells views. + """ + af = AllianceFramework.get() + env = af.getEnvironment() + env.setSCALE_X ( 50 ) + env.setCATALOG ( 'CATAL' ) + env.setPOWER ( 'vdd' ) + env.setGROUND ( 'vss' ) + env.setCLOCK ( '^ck$|m_clock|^clk$' ) + env.setBLOCKAGE( 'blockage[Nn]et.*' ) + env.setPad ( '.*_mpx$' ) + env.setRegister( 'sff.*' ) + env.setWORKING_LIBRARY( '.' ) + env.addSYSTEM_LIBRARY ( library=(cellsTop / 'lsxlib').as_posix(), mode=Environment.Append ) + +def setup ( cellsTop ): + + _routing() + _loadLsxlib( cellsTop ) diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/Makefile b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/Makefile new file mode 100644 index 000000000..c549dc1f5 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/Makefile @@ -0,0 +1,64 @@ +# see README.md in the same directory + +.SILENT: + + ACT_TOP = ~/coriolis-2.x/src/alliance-check-toolkit# + TECHNO_SPI = $(ACT_TOP)/pdkmaster/C4M.Sky130/libs.tech/ngspice/C4M.Sky130_logic_lib.spice + +C ?= inv_x4 inv_x4_chain a2_x2 sff1_x4 sram2bw2r2 + +help : + echo "" + echo "Usage:" + echo " make all [C=]: Simulate typic, fast, slow for Target" + echo " make [tt|ss|ff] [C=]: Simulate only one mode for Target" + echo " make clean: Delete all files except the sources" + echo "" + echo " Examples" + echo " make all" + echo " make tt C=sff1_x4" + echo " make tt C=\"sff1_x4 a2_x2\"" + echo "" + echo " Default Targets:" + echo " $(C)" + echo "" + +tt: + for c in $(C); do\ + make CELL=$$c $$c/$$c.tt ;\ + done + +ss: + for c in $(C); do\ + make CELL=$$c $$c/$$c.ss ;\ + done + +ff: + for c in $(C); do\ + make CELL=$$c $$c/$$c.ff ;\ + done + +all: tt ss ff + +define NGSPICE + cd $(CELL) + cpp -D_TECHNO=$(TECHNO_SPI) -D_TEMP=$1 -D_MODEL=$2 -D_VDD=$3 -D_VMAX=$4 $*.cir |\ + grep -v "^#" > $@.cir + -ngspice -o $@.log -b $@.cir + echo "set title '$@ T=$1 M=$2 V=$3'" >> $@.plt + echo "set term png" >> $@.plt + echo "set term png" >> $@.plt + echo "set output \""$@".png\"" >> $@.plt + echo "replot" >> $@.plt + echo Generated files : $@.log, $@.png, $@.plt, $@.data + cd .. + echo "" +endef + +%.ff:%.cir ; $(call NGSPICE,0,ff,1.85,1.884) +%.tt:%.cir ; $(call NGSPICE,25,tt,1.8,1.799) +%.ss:%.cir ; $(call NGSPICE,70,ss,1.75,1.774) + +c clean: + -killall gnuplot_x11 + -rm -f */*.*.* diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/README.md b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/README.md new file mode 100644 index 000000000..cd08bd2b6 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/README.md @@ -0,0 +1,35 @@ +# LSXLIB Spice Simulation + +- Date : 2024-08-03 +- Author : Franck Wajsburt with help of Marie-Minerve Louerat + +## spi Directory + +- All the `.spi` files originate from `coriolis-2.x/src/alliance-check-toolkit/cells/lsxlib/check`. +- This directory is created by running: + ```sh + make characterize + ``` + in `coriolis-2.x/src/alliance-check-toolkit/cells/lsxlib`. +- The `characterize` command generates `lsxlib.lib`, and thus the `.spi` files are produced. + +## cells Directories + +- There is one directory per cell. +- In each directory, there is a `cell.cir` file which: + - Instantiates the `../spi/cell.spi` model. + - Defines the simulation conditions (technology, temperature, voltage, model: slow, typical, or fast). + - Defines the stimuli. + - Defines the measurement parameters. + - Requests gnuplot to draw the stimuli. + +## Makefile + +- There is a single Makefile located in the root directory. +- For each cell: + - It navigates to the directory dedicated to the cell. + - It performs three simulations: slow, typical, and fast. +- Usage: + - `make` : Simulates all cells. + - `make C=inv_x4` : Simulates only one cell (here `inv_x4`) + - `make clean` : Cleans all files, except the source files. diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/a2_x2/a2_x2.cir b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/a2_x2/a2_x2.cir new file mode 100644 index 000000000..568bd8e21 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/a2_x2/a2_x2.cir @@ -0,0 +1,54 @@ +******************************************************************************** +* a2_x2.cir +* ngspice simulation +* lsxlib +******************************************************************************** + +.option nopage nomod ++ newtol numdgt=7 ingold=2 gmindc=1e-18 +.option DOTNODE +.option MSGNODE = 0 + +******************************************************************************** +* BSIM4 transistor model parameters for ngspice and simulation conditions +******************************************************************************** + +.lib _TECHNO _MODEL +.TEMP _TEMP +Vground vss 0 0 +Vsupply vdd 0 DC _VDD +gfoncd vdd 0 vdd 0 1.0e-15 + +******************************************************************************** +* Circuit Instantiation with loading output +******************************************************************************** +.INCLUDE ../spi/a2_x2.spi +*.subckt a2_x2 i0 i1 q vdd vss + +Xa i0 i1 q vdd vss a2_x2 +*Cload q vss 0.0020pF + +******************************************************************************** +* input stimluli and transient analysis +******************************************************************************** + +vi0 i0 vss dc 0.8 pulse (0 _VDD 170ps 30ps 30ps 170ps 400ps) +vi1 i1 vss dc 1.8 + +.control +TRAN 1ps 800ps 0 + +set width=110 + +meas tran inputRslope TRIG v(q) val=0.001 RISE=1 TARG v(q) VAL=_VMAX RISE=1 +meas tran inputFslope TRIG v(q) val=_VMAX FALL=1 TARG v(q) VAL=0.001 FALL=1 +meas tran proptimeRF TRIG v(i0) val=0.9 RISE=1 TARG v(q) VAL=0.9 FALL=1 +meas tran proptimeFR TRIG v(i0) val=0.9 FALL=1 TARG v(q) VAL=0.9 RISE=1 + +gnuplot a2_x2/a2_x2._MODEL v(i0) v(q) ++ title 'input and output of the a2_x2' ++ xlabel 'time / s' ylabel 'Voltage / V' + +.endc + +.end diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/inv_x4/.plt b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/inv_x4/.plt new file mode 100644 index 000000000..21441eb78 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/inv_x4/.plt @@ -0,0 +1,9 @@ +set term png +set output ".png" +replot +set term png +set output ".png" +replot +set term png +set output ".png" +replot diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/inv_x4/inv_x4.cir b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/inv_x4/inv_x4.cir new file mode 100644 index 000000000..41c757a4e --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/inv_x4/inv_x4.cir @@ -0,0 +1,53 @@ +******************************************************************************** +* inv_x4.cir +* ngspice simulation +* lsxlib +******************************************************************************** + +.option nopage nomod ++ newtol numdgt=7 ingold=2 gmindc=1e-18 +.option DOTNODE +.option MSGNODE = 0 + +******************************************************************************** +* BSIM4 transistor model parameters for ngspice and simulation conditions +******************************************************************************** + +.lib _TECHNO _MODEL +.TEMP _TEMP +Vground vss 0 0 +Vsupply vdd 0 DC _VDD +gfoncd vdd 0 vdd 0 1.0e-15 + +******************************************************************************** +* Circuit Instantiation with loading output +******************************************************************************** +.INCLUDE ../spi/inv_x4.spi +*.subckt inv_x4 i nq vdd vss + +Xa i nq vdd vss inv_x4 +*Cload nq vss 0.0020pF + +******************************************************************************** +* input stimluli and transient analysis +******************************************************************************** + +vi i vss dc 0.8 pulse (0 _VDD 170ps 30ps 30ps 170ps 400ps) + +.control +TRAN 1ps 800ps 0 + +set width=110 + +meas tran inputRslope TRIG v(nq) val=0.001 RISE=1 TARG v(nq) VAL=_VMAX RISE=1 +meas tran inputFslope TRIG v(nq) val=_VMAX FALL=1 TARG v(nq) VAL=0.001 FALL=1 +meas tran proptimeRF TRIG v(i) val=0.9 RISE=1 TARG v(nq) VAL=0.9 FALL=1 +meas tran proptimeFR TRIG v(i) val=0.9 FALL=1 TARG v(nq) VAL=0.9 RISE=1 + +gnuplot inv_x4/inv_x4._MODEL v(i) v(nq) ++ title 'input and output of the inv_x4' ++ xlabel 'time / s' ylabel 'Voltage / V' + +.endc + +.end diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/inv_x4_chain/inv_x4_chain.cir b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/inv_x4_chain/inv_x4_chain.cir new file mode 100644 index 000000000..6638dd726 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/inv_x4_chain/inv_x4_chain.cir @@ -0,0 +1,61 @@ +******************************************************************************** +* inv_x4_chain.cir +* ngspice simulation +* lsxlib +******************************************************************************** + +.option nopage nomod ++ newtol numdgt=7 ingold=2 gmindc=1e-18 +.option DOTNODE +.option MSGNODE = 0 + +******************************************************************************** +* BSIM4 transistor model parameters for ngspice and simulation conditions +******************************************************************************** + +.lib _TECHNO _MODEL +.TEMP _TEMP +Vground vss 0 0 +Vsupply vdd 0 DC _VDD +gfoncd vdd 0 vdd 0 1.0e-15 + +******************************************************************************** +* Circuit Instantiation with loading output +******************************************************************************** +.INCLUDE ../spi/inv_x4.spi +*.subckt inv_x4 i nq vdd vss +Xa i 1 vdd vss inv_x4 +Xb 1 2 vdd vss inv_x4 +Xc 2 3 vdd vss inv_x4 +Xd 3 4 vdd vss inv_x4 +Xe 4 5 vdd vss inv_x4 +Xf 5 6 vdd vss inv_x4 +Xg 6 7 vdd vss inv_x4 +Xh 7 q vdd vss inv_x4 +*Cload q vss 0.0020pF + +******************************************************************************** +* input stimluli and transient analysis +******************************************************************************** + +vi0 i vss dc 0.8 pulse (0 _VDD 170ps 30ps 30ps 170ps 400ps) + +.control +TRAN 1ps 1500ps 0 + +set width=110 + +meas tran inputRslope TRIG v(4) val=0.1 RISE=1 TARG v(4) VAL=_VMAX RISE=1 +meas tran inputFslope TRIG v(4) val=_VMAX FALL=1 TARG v(4) VAL=0.001 FALL=1 +meas tran inputRslope TRIG v(6) val=0.1 RISE=1 TARG v(6) VAL=_VMAX RISE=1 +meas tran inputFslope TRIG v(6) val=_VMAX FALL=1 TARG v(6) VAL=0.001 FALL=1 +meas tran proptimeRF TRIG v(i) val=0.9 RISE=1 TARG v(q) VAL=0.9 FALL=1 +meas tran proptimeFR TRIG v(i) val=0.9 FALL=1 TARG v(q) VAL=0.9 RISE=1 + +gnuplot inv_x4_chain/inv_x4_chain._MODEL v(i) v(2) v(4) v(6) v(q) ++ title 'input and output of the inverter chain' ++ xlabel 'time / s' ylabel 'Voltage / V' + +.endc + +.end diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/sff1_x4/sff1_x4.cir b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/sff1_x4/sff1_x4.cir new file mode 100644 index 000000000..8e813327c --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/sff1_x4/sff1_x4.cir @@ -0,0 +1,54 @@ +******************************************************************************** +* sff1_x4.cir +* ngspice simulation +* lsxlib +******************************************************************************** + +.option nopage nomod ++ newtol numdgt=7 ingold=2 gmindc=1e-18 +.option DOTNODE +.option MSGNODE = 0 + +******************************************************************************** +* BSIM4 transistor model parameters for ngspice and simulation conditions +******************************************************************************** + +.lib _TECHNO _MODEL +.TEMP _TEMP +Vground vss 0 0 +Vsupply vdd 0 DC _VDD +gfoncd vdd 0 vdd 0 1.0e-15 + +******************************************************************************** +* Circuit Instantiation with loading output +******************************************************************************** +.INCLUDE ../spi/sff1_x4.spi +*.subckt sff1_x4 ck i q vdd vss + +Xa ck i q vdd vss sff1_x4 +*Cload q vss 0.0020pF + +******************************************************************************** +* input stimluli and transient analysis +******************************************************************************** + +vck ck vss dc 0.8 pulse (0 _VDD 1000ps 30ps 30ps 470ps 1000ps) +vi i vss dc 0.8 pulse (0 _VDD 800ps 30ps 30ps 970ps 2025ps) + +.control +TRAN 1ps 12ns 0 + +set width=110 + +*meas tran inputRslope TRIG v(q) val=0.001 RISE=1 TARG v(q) VAL=_VMAX RISE=1 +*meas tran inputFslope TRIG v(q) val=_VMAX FALL=1 TARG v(q) VAL=0.001 FALL=1 +meas tran proptimeRF TRIG v(ck) val=0.9 RISE=1 TARG v(q) VAL=0.9 FALL=1 +meas tran proptimeFR TRIG v(ck) val=0.9 FALL=1 TARG v(q) VAL=0.9 RISE=1 + +gnuplot sff1_x4/sff1_x4._MODEL v(ck) v(i) v(q) ++ title 'input and output of the sff1_x4' ++ xlabel 'time / s' ylabel 'Voltage / V' + +.endc + +.end diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a2_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a2_x2.spi new file mode 100644 index 000000000..1be4e4188 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a2_x2.spi @@ -0,0 +1,27 @@ +* Spice description of a2_x2 +* Spice driver version 753875880 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:30 + +* INTERF i0 i1 q vdd vss + + +.subckt a2_x2 1 2 4 3 7 +* NET 1 = i0 +* NET 2 = i1 +* NET 3 = vdd +* NET 4 = q +* NET 7 = vss +Mtr_00006 4 5 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 5 1 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 3 2 5 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 7 5 4 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 6 2 5 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 7 1 6 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C7 1 7 8.37957e-16 +C6 2 7 1.09511e-15 +C5 3 7 1.46192e-15 +C4 4 7 1.22684e-15 +C3 5 7 1.81273e-15 +C1 7 7 1.42442e-15 +.ends a2_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a2_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a2_x4.spi new file mode 100644 index 000000000..68fd9b2de --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a2_x4.spi @@ -0,0 +1,29 @@ +* Spice description of a2_x4 +* Spice driver version -1293481048 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:31 + +* INTERF i0 i1 q vdd vss + + +.subckt a2_x4 2 1 5 3 6 +* NET 1 = i1 +* NET 2 = i0 +* NET 3 = vdd +* NET 5 = q +* NET 6 = vss +Mtr_00008 3 7 5 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 5 7 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 3 1 7 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 7 2 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 6 7 5 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 4 1 7 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 6 2 4 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 5 7 6 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C7 1 6 1.09511e-15 +C6 2 6 8.37957e-16 +C5 3 6 2.41928e-15 +C3 5 6 1.22684e-15 +C2 6 6 2.04962e-15 +C1 7 6 2.08981e-15 +.ends a2_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a3_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a3_x2.spi new file mode 100644 index 000000000..fcdca8c63 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a3_x2.spi @@ -0,0 +1,31 @@ +* Spice description of a3_x2 +* Spice driver version 302410664 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:32 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt a3_x2 2 1 3 5 4 7 +* NET 1 = i1 +* NET 2 = i0 +* NET 3 = i2 +* NET 4 = vdd +* NET 5 = q +* NET 7 = vss +Mtr_00008 9 3 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 5 9 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 9 2 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 4 1 9 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 6 3 9 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 7 9 5 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 8 1 6 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 7 2 8 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C9 1 7 9.89144e-16 +C8 2 7 8.39136e-16 +C7 3 7 9.89143e-16 +C6 4 7 1.63174e-15 +C5 5 7 1.22684e-15 +C3 7 7 1.59424e-15 +C1 9 7 2.54251e-15 +.ends a3_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a3_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a3_x4.spi new file mode 100644 index 000000000..2c5b03eff --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a3_x4.spi @@ -0,0 +1,33 @@ +* Spice description of a3_x4 +* Spice driver version 2105387944 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:33 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt a3_x4 4 2 1 9 5 8 +* NET 1 = i2 +* NET 2 = i1 +* NET 4 = i0 +* NET 5 = vdd +* NET 8 = vss +* NET 9 = q +Mtr_00010 5 2 3 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 3 1 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 3 4 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 5 3 9 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 9 3 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 9 3 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 6 1 3 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 7 2 6 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 8 4 7 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 8 3 9 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C9 1 8 1.06324e-15 +C8 2 8 1.01428e-15 +C7 3 8 3.07916e-15 +C6 4 8 7.39551e-16 +C5 5 8 2.47124e-15 +C2 8 8 2.01051e-15 +C1 9 8 1.93938e-15 +.ends a3_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a4_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a4_x2.spi new file mode 100644 index 000000000..7564e7835 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a4_x2.spi @@ -0,0 +1,35 @@ +* Spice description of a4_x2 +* Spice driver version 22121384 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:34 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt a4_x2 5 2 3 1 7 6 8 +* NET 1 = i3 +* NET 2 = i1 +* NET 3 = i2 +* NET 5 = i0 +* NET 6 = vdd +* NET 7 = q +* NET 8 = vss +Mtr_00010 4 5 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 7 4 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 6 1 4 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 4 3 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 6 2 4 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 8 5 9 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 9 2 10 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 11 1 4 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 10 3 11 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 8 4 7 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C11 1 8 1.09479e-15 +C10 2 8 9.82537e-16 +C9 3 8 1.04216e-15 +C8 4 8 2.57005e-15 +C7 5 8 1.04216e-15 +C6 6 8 2.75893e-15 +C5 7 8 1.22684e-15 +C4 8 8 1.93389e-15 +.ends a4_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a4_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a4_x4.spi new file mode 100644 index 000000000..f80c7449b --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/a4_x4.spi @@ -0,0 +1,37 @@ +* Spice description of a4_x4 +* Spice driver version 1435143080 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:34 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt a4_x4 4 5 1 2 11 7 8 +* NET 1 = i2 +* NET 2 = i3 +* NET 4 = i0 +* NET 5 = i1 +* NET 7 = vdd +* NET 8 = vss +* NET 11 = q +Mtr_00012 11 6 7 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 7 6 11 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 7 5 6 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 7 2 6 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 6 1 7 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 6 4 7 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 8 6 11 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 11 6 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 8 4 10 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 3 2 6 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 9 1 3 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 10 5 9 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C11 1 8 1.04216e-15 +C10 2 8 1.09479e-15 +C8 4 8 1.04216e-15 +C7 5 8 9.82537e-16 +C6 6 8 2.76982e-15 +C5 7 8 3.71629e-15 +C4 8 8 2.55909e-15 +C1 11 8 1.22684e-15 +.ends a4_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/an12_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/an12_x1.spi new file mode 100644 index 000000000..8622b3b5d --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/an12_x1.spi @@ -0,0 +1,27 @@ +* Spice description of an12_x1 +* Spice driver version -118711384 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:35 + +* INTERF i0 i1 q vdd vss + + +.subckt an12_x1 1 2 5 4 7 +* NET 1 = i0 +* NET 2 = i1 +* NET 4 = vdd +* NET 5 = q +* NET 7 = vss +Mtr_00006 6 2 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 3 1 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 4 6 3 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00003 7 2 6 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 5 6 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 7 1 5 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C7 1 7 1.03186e-15 +C6 2 7 1.1406e-15 +C4 4 7 1.36013e-15 +C3 5 7 1.41435e-15 +C2 6 7 1.60598e-15 +C1 7 7 1.52085e-15 +.ends an12_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/an12_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/an12_x4.spi new file mode 100644 index 000000000..07bafec93 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/an12_x4.spi @@ -0,0 +1,32 @@ +* Spice description of an12_x4 +* Spice driver version -1550738520 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:36 + +* INTERF i0 i1 q vdd vss + + +.subckt an12_x4 3 2 1 4 6 +* NET 1 = q +* NET 2 = i1 +* NET 3 = i0 +* NET 4 = vdd +* NET 6 = vss +Mtr_00010 4 3 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00009 1 7 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 4 7 1 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 4 2 7 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 7 5 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 6 3 5 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00004 6 2 8 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 8 5 7 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 1 7 6 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 6 7 1 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C8 1 6 1.22684e-15 +C7 2 6 1.06847e-15 +C6 3 6 1.06498e-15 +C5 4 6 3.30003e-15 +C4 5 6 1.84709e-15 +C3 6 6 2.59285e-15 +C2 7 6 1.83441e-15 +.ends an12_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao22_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao22_x2.spi new file mode 100644 index 000000000..cd5731bb0 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao22_x2.spi @@ -0,0 +1,32 @@ +* Spice description of ao22_x2 +* Spice driver version -1352500312 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:36 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt ao22_x2 3 2 4 6 5 8 +* NET 2 = i1 +* NET 3 = i0 +* NET 4 = i2 +* NET 5 = vdd +* NET 6 = q +* NET 8 = vss +Mtr_00008 1 2 7 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 5 3 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 7 4 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 5 7 6 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 8 4 9 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 9 2 7 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 7 3 9 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 6 7 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C8 2 8 1.03326e-15 +C7 3 8 1.15106e-15 +C6 4 8 1.32091e-15 +C5 5 8 1.63174e-15 +C4 6 8 1.22684e-15 +C3 7 8 1.82821e-15 +C2 8 8 1.3853e-15 +C1 9 8 4.33949e-16 +.ends ao22_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao22_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao22_x4.spi new file mode 100644 index 000000000..b238bbbdf --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao22_x4.spi @@ -0,0 +1,35 @@ +* Spice description of ao22_x4 +* Spice driver version -77472856 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:37 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt ao22_x4 5 3 4 2 6 9 +* NET 2 = q +* NET 3 = i1 +* NET 4 = i2 +* NET 5 = i0 +* NET 6 = vdd +* NET 9 = vss +Mtr_00011 2 7 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 2 7 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 6 7 2 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 1 3 7 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 6 5 1 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 7 4 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 2 7 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 9 7 2 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 9 4 8 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 8 3 7 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 7 5 8 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C8 2 9 1.22684e-15 +C7 3 9 1.03326e-15 +C6 4 9 1.43866e-15 +C5 5 9 1.15106e-15 +C4 6 9 4.8751e-15 +C3 7 9 2.21056e-15 +C2 8 9 4.33949e-16 +C1 9 9 2.38927e-15 +.ends ao22_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao2o22_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao2o22_x2.spi new file mode 100644 index 000000000..fb44be797 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao2o22_x2.spi @@ -0,0 +1,36 @@ +* Spice description of ao2o22_x2 +* Spice driver version -1787671640 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:38 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt ao2o22_x2 7 6 5 8 4 3 11 +* NET 3 = vdd +* NET 4 = q +* NET 5 = i2 +* NET 6 = i1 +* NET 7 = i0 +* NET 8 = i3 +* NET 11 = vss +Mtr_00010 4 10 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 1 7 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 2 5 10 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 3 8 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 10 6 1 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 11 10 4 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 9 5 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 11 8 9 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 9 7 10 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 10 6 9 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C9 3 11 2.92875e-15 +C8 4 11 1.22684e-15 +C7 5 11 9.46424e-16 +C6 6 11 1.05357e-15 +C5 7 11 1.10423e-15 +C4 8 11 8.89936e-16 +C3 9 11 1.25899e-15 +C2 10 11 2.70323e-15 +C1 11 11 2.35015e-15 +.ends ao2o22_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao2o22_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao2o22_x4.spi new file mode 100644 index 000000000..1e15149e8 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ao2o22_x4.spi @@ -0,0 +1,38 @@ +* Spice description of ao2o22_x4 +* Spice driver version 637803432 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:39 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt ao2o22_x4 7 6 5 8 4 3 11 +* NET 3 = vdd +* NET 4 = q +* NET 5 = i2 +* NET 6 = i1 +* NET 7 = i0 +* NET 8 = i3 +* NET 11 = vss +Mtr_00012 3 10 4 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 4 10 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 1 7 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 2 5 10 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 3 8 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 10 6 1 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 4 10 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 11 10 4 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 9 5 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 11 8 9 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 9 7 10 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 10 6 9 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C9 3 11 3.88611e-15 +C8 4 11 1.22684e-15 +C7 5 11 9.46424e-16 +C6 6 11 1.05357e-15 +C5 7 11 1.10423e-15 +C4 8 11 8.89936e-16 +C3 9 11 1.25899e-15 +C2 10 11 2.92356e-15 +C1 11 11 2.97536e-15 +.ends ao2o22_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/buf_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/buf_x2.spi new file mode 100644 index 000000000..8253872a6 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/buf_x2.spi @@ -0,0 +1,23 @@ +* Spice description of buf_x2 +* Spice driver version 1893776296 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:39 + +* INTERF i q vdd vss + + +.subckt buf_x2 1 5 2 3 +* NET 1 = i +* NET 2 = vdd +* NET 3 = vss +* NET 5 = q +Mtr_00004 2 1 4 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00003 5 4 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00002 4 1 3 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00001 3 4 5 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C5 1 3 1.01022e-15 +C4 2 3 1.04566e-15 +C3 3 3 1.04566e-15 +C2 4 3 2.07106e-15 +C1 5 3 1.22684e-15 +.ends buf_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/buf_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/buf_x4.spi new file mode 100644 index 000000000..3fc3cc392 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/buf_x4.spi @@ -0,0 +1,25 @@ +* Spice description of buf_x4 +* Spice driver version -213722200 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:40 + +* INTERF i q vdd vss + + +.subckt buf_x4 1 4 2 5 +* NET 1 = i +* NET 2 = vdd +* NET 4 = q +* NET 5 = vss +Mtr_00006 2 3 4 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 2 1 3 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 4 3 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00003 4 3 5 5 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 3 1 5 5 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 5 3 4 5 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C5 1 5 9.7156e-16 +C4 2 5 2.00302e-15 +C3 3 5 2.34697e-15 +C2 4 5 1.22684e-15 +C1 5 5 1.67086e-15 +.ends buf_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/buf_x8.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/buf_x8.spi new file mode 100644 index 000000000..1f4d2f74e --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/buf_x8.spi @@ -0,0 +1,29 @@ +* Spice description of buf_x8 +* Spice driver version -1395520600 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:41 + +* INTERF i q vdd vss + + +.subckt buf_x8 1 5 2 4 +* NET 1 = i +* NET 2 = vdd +* NET 4 = vss +* NET 5 = q +Mtr_00010 2 1 3 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 2 3 5 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 5 3 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 2 3 5 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 5 3 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 3 1 4 4 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 5 3 4 4 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 4 3 5 4 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 5 3 4 4 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 4 3 5 4 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C5 1 4 6.71128e-16 +C4 2 4 3.46611e-15 +C3 3 4 2.96007e-15 +C2 4 4 2.63571e-15 +C1 5 4 2.76978e-15 +.ends buf_x8 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x1.spi new file mode 100644 index 000000000..90cbe6661 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x1.spi @@ -0,0 +1,20 @@ +* Spice description of inv_x1 +* Spice driver version -276112472 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:42 + +* INTERF i nq vdd vss + + +.subckt inv_x1 2 3 1 4 +* NET 1 = vdd +* NET 2 = i +* NET 3 = nq +* NET 4 = vss +Mtr_00002 3 2 1 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 4 2 3 4 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C4 1 4 8.75833e-16 +C3 2 4 1.16072e-15 +C2 3 4 1.05005e-15 +C1 4 4 8.75833e-16 +.ends inv_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x2.spi new file mode 100644 index 000000000..f515066a8 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x2.spi @@ -0,0 +1,20 @@ +* Spice description of inv_x2 +* Spice driver version 1363757992 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:43 + +* INTERF i nq vdd vss + + +.subckt inv_x2 1 3 2 4 +* NET 1 = i +* NET 2 = vdd +* NET 3 = nq +* NET 4 = vss +Mtr_00002 3 1 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00001 4 1 3 4 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C4 1 4 8.60287e-16 +C3 2 4 1.04191e-15 +C2 3 4 1.22684e-15 +C1 4 4 8.75833e-16 +.ends inv_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x4.spi new file mode 100644 index 000000000..0467d2b3c --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x4.spi @@ -0,0 +1,22 @@ +* Spice description of inv_x4 +* Spice driver version 1333574568 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:43 + +* INTERF i nq vdd vss + + +.subckt inv_x4 1 4 2 3 +* NET 1 = i +* NET 2 = vdd +* NET 3 = vss +* NET 4 = nq +Mtr_00004 2 1 4 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00003 4 1 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00002 4 1 3 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 3 1 4 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C4 1 3 1.13955e-15 +C3 2 3 1.99927e-15 +C2 3 3 1.50103e-15 +C1 4 3 1.22684e-15 +.ends inv_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x8.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x8.spi new file mode 100644 index 000000000..3b1229d2f --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/inv_x8.spi @@ -0,0 +1,26 @@ +* Spice description of inv_x8 +* Spice driver version -779908184 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:44 + +* INTERF i nq vdd vss + + +.subckt inv_x8 1 4 2 3 +* NET 1 = i +* NET 2 = vdd +* NET 3 = vss +* NET 4 = nq +Mtr_00008 2 1 4 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 4 1 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 2 1 4 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 4 1 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 4 1 3 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 3 1 4 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 4 1 3 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 3 1 4 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C4 1 3 1.69807e-15 +C3 2 3 3.12646e-15 +C2 3 3 2.29606e-15 +C1 4 3 2.76978e-15 +.ends inv_x8 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/invbuf_x3.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/invbuf_x3.spi new file mode 100644 index 000000000..a17790c9f --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/invbuf_x3.spi @@ -0,0 +1,28 @@ +* Spice description of invbuf_x3 +* Spice driver version 258747304 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:41 + +* INTERF c0 c1 i vdd vss + + +.subckt invbuf_x3 5 4 2 1 3 +* NET 1 = vdd +* NET 2 = i +* NET 3 = vss +* NET 4 = c1 +* NET 5 = c0 +Mtr_00008 5 2 1 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mtr_00007 1 5 4 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mtr_00006 4 5 1 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mtr_00005 1 2 5 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mtr_00004 5 2 3 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00003 3 5 4 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00002 4 5 3 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00001 3 2 5 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +C5 1 3 2.87466e-15 +C4 2 3 1.17527e-15 +C3 3 3 2.31213e-15 +C2 4 3 1.32864e-15 +C1 5 3 2.41818e-15 +.ends invbuf_x3 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx2_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx2_x2.spi new file mode 100644 index 000000000..3b02d8d71 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx2_x2.spi @@ -0,0 +1,36 @@ +* Spice description of mx2_x2 +* Spice driver version -792630360 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:45 + +* INTERF cmd i0 i1 q vdd vss + + +.subckt mx2_x2 7 5 6 4 3 12 +* NET 3 = vdd +* NET 4 = q +* NET 5 = i0 +* NET 6 = i1 +* NET 7 = cmd +* NET 12 = vss +Mtr_00012 4 10 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 1 6 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 9 7 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00009 3 5 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 10 9 1 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 2 7 10 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 12 6 11 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 4 10 12 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 12 7 9 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00003 11 7 10 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 8 5 12 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 10 9 8 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C10 3 12 2.51249e-15 +C9 4 12 1.22684e-15 +C8 5 12 1.05272e-15 +C7 6 12 1.11439e-15 +C6 7 12 1.49322e-15 +C4 9 12 3.46344e-15 +C3 10 12 1.92357e-15 +C1 12 12 2.18033e-15 +.ends mx2_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx2_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx2_x4.spi new file mode 100644 index 000000000..5150a9fd0 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx2_x4.spi @@ -0,0 +1,38 @@ +* Spice description of mx2_x4 +* Spice driver version -2127492184 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:46 + +* INTERF cmd i0 i1 q vdd vss + + +.subckt mx2_x4 6 7 5 4 3 8 +* NET 3 = vdd +* NET 4 = q +* NET 5 = i1 +* NET 6 = cmd +* NET 7 = i0 +* NET 8 = vss +Mtr_00014 3 10 4 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00013 3 7 1 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00012 4 10 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 1 6 10 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 10 12 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 12 6 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00008 2 5 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 10 12 9 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00006 9 7 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 11 6 10 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 8 6 12 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00003 4 10 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 8 5 11 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 8 10 4 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C10 3 8 3.63967e-15 +C9 4 8 1.22684e-15 +C8 5 8 1.11439e-15 +C7 6 8 1.49322e-15 +C6 7 8 1.05272e-15 +C5 8 8 2.97536e-15 +C3 10 8 2.13619e-15 +C1 12 8 3.46344e-15 +.ends mx2_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx3_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx3_x2.spi new file mode 100644 index 000000000..123541fb5 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx3_x2.spi @@ -0,0 +1,51 @@ +* Spice description of mx3_x2 +* Spice driver version -129328216 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:46 + +* INTERF cmd0 cmd1 i0 i1 i2 q vdd vss + + +.subckt mx3_x2 5 11 6 12 10 8 13 18 +* NET 5 = cmd0 +* NET 6 = i0 +* NET 8 = q +* NET 10 = i2 +* NET 11 = cmd1 +* NET 12 = i1 +* NET 13 = vdd +* NET 18 = vss +Mtr_00020 8 17 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00019 13 5 7 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00018 19 11 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00017 17 6 1 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00016 4 10 3 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00015 17 11 4 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00014 2 19 17 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00013 1 5 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00012 13 7 3 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00011 3 12 2 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00010 8 17 18 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 17 6 9 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00008 18 5 14 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00007 9 7 18 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00006 7 5 18 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Mtr_00005 18 11 19 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Mtr_00004 16 10 14 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00003 15 11 17 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00002 17 19 16 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00001 14 12 15 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +C17 3 18 6.69675e-16 +C15 5 18 1.3491e-15 +C14 6 18 9.13739e-16 +C13 7 18 2.12483e-15 +C12 8 18 1.22684e-15 +C10 10 18 7.83035e-16 +C9 11 18 1.90919e-15 +C8 12 18 8.61981e-16 +C7 13 18 3.06695e-15 +C6 14 18 6.69675e-16 +C3 17 18 3.689e-15 +C2 18 18 3.06695e-15 +C1 19 18 1.86937e-15 +.ends mx3_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx3_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx3_x4.spi new file mode 100644 index 000000000..c6944e970 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/mx3_x4.spi @@ -0,0 +1,53 @@ +* Spice description of mx3_x4 +* Spice driver version -884991064 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:47 + +* INTERF cmd0 cmd1 i0 i1 i2 q vdd vss + + +.subckt mx3_x4 6 11 5 12 10 7 13 18 +* NET 5 = i0 +* NET 6 = cmd0 +* NET 7 = q +* NET 10 = i2 +* NET 11 = cmd1 +* NET 12 = i1 +* NET 13 = vdd +* NET 18 = vss +Mtr_00022 13 17 7 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00021 7 17 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00020 13 6 9 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00019 19 11 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00018 17 5 1 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00017 4 10 3 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00016 17 11 4 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00015 2 19 17 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00014 1 6 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00013 13 9 3 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00012 3 12 2 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00011 18 17 7 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 7 17 18 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 9 6 18 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Mtr_00008 17 5 8 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00007 18 6 14 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00006 8 9 18 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00005 18 11 19 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Mtr_00004 16 10 14 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00003 15 11 17 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00002 17 19 16 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00001 14 12 15 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +C17 3 18 6.69675e-16 +C15 5 18 9.85955e-16 +C14 6 18 1.33621e-15 +C13 7 18 1.22684e-15 +C11 9 18 1.98553e-15 +C10 10 18 7.83035e-16 +C9 11 18 1.90919e-15 +C8 12 18 8.61981e-16 +C7 13 18 4.02431e-15 +C6 14 18 6.69675e-16 +C3 17 18 3.9254e-15 +C2 18 18 3.69215e-15 +C1 19 18 1.85648e-15 +.ends mx3_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na2_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na2_x1.spi new file mode 100644 index 000000000..e5a060415 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na2_x1.spi @@ -0,0 +1,24 @@ +* Spice description of na2_x1 +* Spice driver version -903439448 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:48 + +* INTERF i0 i1 nq vdd vss + + +.subckt na2_x1 2 3 5 1 4 +* NET 1 = vdd +* NET 2 = i0 +* NET 3 = i1 +* NET 4 = vss +* NET 5 = nq +Mtr_00004 1 3 5 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 5 2 1 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 6 3 5 4 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 4 2 6 4 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C6 1 4 1.2921e-15 +C5 2 4 1.09629e-15 +C4 3 4 1.09629e-15 +C3 4 4 1.04566e-15 +C2 5 4 1.23756e-15 +.ends na2_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na2_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na2_x4.spi new file mode 100644 index 000000000..b9c003431 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na2_x4.spi @@ -0,0 +1,32 @@ +* Spice description of na2_x4 +* Spice driver version 1468505000 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:48 + +* INTERF i0 i1 nq vdd vss + + +.subckt na2_x4 2 3 6 4 7 +* NET 2 = i0 +* NET 3 = i1 +* NET 4 = vdd +* NET 6 = nq +* NET 7 = vss +Mtr_00010 4 5 1 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 4 3 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00008 5 2 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00007 6 1 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 4 1 6 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 1 5 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 8 3 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00003 5 2 8 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00002 6 1 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 7 1 6 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C8 1 7 1.9723e-15 +C7 2 7 1.22295e-15 +C6 3 7 8.00154e-16 +C5 4 7 2.92501e-15 +C4 5 7 2.90698e-15 +C3 6 7 1.22684e-15 +C2 7 7 2.32498e-15 +.ends na2_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na3_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na3_x1.spi new file mode 100644 index 000000000..3aca6f7e9 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na3_x1.spi @@ -0,0 +1,28 @@ +* Spice description of na3_x1 +* Spice driver version -1981023320 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:49 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt na3_x1 2 3 4 6 1 5 +* NET 1 = vdd +* NET 2 = i0 +* NET 3 = i1 +* NET 4 = i2 +* NET 5 = vss +* NET 6 = nq +Mtr_00006 6 4 1 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 1 3 6 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 6 2 1 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 7 4 6 5 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.62U AS=0.4698P AD=0.4698P PS=3.82U PD=3.82U +Mtr_00002 5 2 8 5 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.62U AS=0.4698P AD=0.4698P PS=3.82U PD=3.82U +Mtr_00001 8 3 7 5 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.62U AS=0.4698P AD=0.4698P PS=3.82U PD=3.82U +C8 1 5 1.46192e-15 +C7 2 5 1.05763e-15 +C6 3 5 9.50487e-16 +C5 4 5 9.50487e-16 +C4 5 5 1.21548e-15 +C3 6 5 1.96617e-15 +.ends na3_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na3_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na3_x4.spi new file mode 100644 index 000000000..dbc8cf0a0 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na3_x4.spi @@ -0,0 +1,36 @@ +* Spice description of na3_x4 +* Spice driver version 308284328 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:50 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt na3_x4 4 3 2 9 5 8 +* NET 2 = i2 +* NET 3 = i1 +* NET 4 = i0 +* NET 5 = vdd +* NET 8 = vss +* NET 9 = nq +Mtr_00012 5 10 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 10 3 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00010 10 4 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00009 5 2 10 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00008 5 1 9 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 9 1 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 1 10 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 6 4 10 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00004 6 3 7 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00003 7 2 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00002 8 1 9 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 9 1 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C10 1 8 1.99373e-15 +C9 2 8 6.90627e-16 +C8 3 8 1.08036e-15 +C7 4 8 1.01428e-15 +C6 5 8 3.09483e-15 +C3 8 8 2.4948e-15 +C2 9 8 1.22684e-15 +C1 10 8 3.63559e-15 +.ends na3_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na4_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na4_x1.spi new file mode 100644 index 000000000..4622726a1 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na4_x1.spi @@ -0,0 +1,32 @@ +* Spice description of na4_x1 +* Spice driver version 1124522920 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:51 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt na4_x1 2 5 4 3 7 1 6 +* NET 1 = vdd +* NET 2 = i0 +* NET 3 = i3 +* NET 4 = i2 +* NET 5 = i1 +* NET 6 = vss +* NET 7 = nq +Mtr_00008 7 5 1 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00007 1 4 7 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00006 7 3 1 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00005 7 2 1 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00004 6 2 8 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.62U AS=0.4698P AD=0.4698P PS=3.82U PD=3.82U +Mtr_00003 9 3 7 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.62U AS=0.4698P AD=0.4698P PS=3.82U PD=3.82U +Mtr_00002 8 5 10 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.62U AS=0.4698P AD=0.4698P PS=3.82U PD=3.82U +Mtr_00001 10 4 9 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.62U AS=0.4698P AD=0.4698P PS=3.82U PD=3.82U +C10 1 6 1.63174e-15 +C9 2 6 7.74847e-16 +C8 3 6 9.89144e-16 +C7 4 6 9.89144e-16 +C6 5 6 1.09629e-15 +C5 6 6 1.71746e-15 +C4 7 6 2.58227e-15 +.ends na4_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na4_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na4_x4.spi new file mode 100644 index 000000000..a1756fb18 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/na4_x4.spi @@ -0,0 +1,41 @@ +* Spice description of na4_x4 +* Spice driver version -1253262424 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:51 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt na4_x4 7 5 4 6 2 8 12 +* NET 2 = nq +* NET 4 = i2 +* NET 5 = i1 +* NET 6 = i3 +* NET 7 = i0 +* NET 8 = vdd +* NET 12 = vss +Mtr_00014 8 13 1 8 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00013 8 6 13 8 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00012 13 5 8 8 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00011 13 4 8 8 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00010 8 7 13 8 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00009 8 1 2 8 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 2 1 8 8 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 1 13 12 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00006 10 4 9 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.62U AS=0.4698P AD=0.4698P PS=3.82U PD=3.82U +Mtr_00005 10 5 11 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.62U AS=0.4698P AD=0.4698P PS=3.82U PD=3.82U +Mtr_00004 11 7 13 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.62U AS=0.4698P AD=0.4698P PS=3.82U PD=3.82U +Mtr_00003 12 1 2 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 2 1 12 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 9 6 12 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.62U AS=0.4698P AD=0.4698P PS=3.82U PD=3.82U +C13 1 12 1.99373e-15 +C12 2 12 1.22684e-15 +C11 3 12 4.57512e-17 +C10 4 12 1.08036e-15 +C9 5 12 9.32656e-16 +C8 6 12 6.91806e-16 +C7 7 12 7.3979e-16 +C6 8 12 3.65575e-15 +C2 12 12 2.66463e-15 +C1 13 12 4.3406e-15 +.ends na4_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao22_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao22_x1.spi new file mode 100644 index 000000000..5cdbbd4d5 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao22_x1.spi @@ -0,0 +1,29 @@ +* Spice description of nao22_x1 +* Spice driver version -520266840 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:52 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt nao22_x1 1 3 2 7 5 8 +* NET 1 = i0 +* NET 2 = i2 +* NET 3 = i1 +* NET 5 = vdd +* NET 7 = nq +* NET 8 = vss +Mtr_00006 5 2 7 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 4 1 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 7 3 4 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00003 6 1 7 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 7 3 6 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 6 2 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C8 1 8 9.67435e-16 +C7 2 8 9.67435e-16 +C6 3 8 9.67435e-16 +C4 5 8 1.46192e-15 +C3 6 8 4.33949e-16 +C2 7 8 1.24827e-15 +C1 8 8 1.21548e-15 +.ends nao22_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao22_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao22_x4.spi new file mode 100644 index 000000000..615959f80 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao22_x4.spi @@ -0,0 +1,37 @@ +* Spice description of nao22_x4 +* Spice driver version 1184426920 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:53 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt nao22_x4 3 5 4 7 6 9 +* NET 3 = i0 +* NET 4 = i2 +* NET 5 = i1 +* NET 6 = vdd +* NET 7 = nq +* NET 9 = vss +Mtr_00012 6 8 2 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 6 4 8 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 1 3 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 8 5 1 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 6 2 7 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 7 2 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 2 8 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 10 4 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 8 5 10 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 10 3 8 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 9 2 7 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 7 2 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C9 2 9 1.99373e-15 +C8 3 9 1.16072e-15 +C7 4 9 9.46424e-16 +C6 5 9 1.19053e-15 +C5 6 9 2.92875e-15 +C4 7 9 1.22684e-15 +C3 8 9 2.53515e-15 +C2 9 9 2.35015e-15 +C1 10 9 8.08967e-16 +.ends nao22_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao2o22_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao2o22_x1.spi new file mode 100644 index 000000000..e15f78a50 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao2o22_x1.spi @@ -0,0 +1,33 @@ +* Spice description of nao2o22_x1 +* Spice driver version 990751656 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:53 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt nao2o22_x1 4 3 2 1 8 7 10 +* NET 1 = i3 +* NET 2 = i2 +* NET 3 = i1 +* NET 4 = i0 +* NET 7 = vdd +* NET 8 = nq +* NET 10 = vss +Mtr_00008 6 1 8 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 7 2 6 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 8 3 5 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 5 4 7 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 10 2 9 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 9 1 10 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 8 3 9 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 9 4 8 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C10 1 10 9.67435e-16 +C9 2 10 8.038e-16 +C8 3 10 8.60287e-16 +C7 4 10 9.92572e-16 +C4 7 10 1.63174e-15 +C3 8 10 1.30721e-15 +C2 9 10 1.25899e-15 +C1 10 10 1.3853e-15 +.ends nao2o22_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao2o22_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao2o22_x4.spi new file mode 100644 index 000000000..93f3cfa2b --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nao2o22_x4.spi @@ -0,0 +1,41 @@ +* Spice description of nao2o22_x4 +* Spice driver version -75920472 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:54 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt nao2o22_x4 7 8 6 9 4 3 10 +* NET 3 = vdd +* NET 4 = nq +* NET 6 = i2 +* NET 7 = i0 +* NET 8 = i1 +* NET 9 = i3 +* NET 10 = vss +Mtr_00014 5 11 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00013 4 5 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00012 3 5 4 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 1 7 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 2 9 11 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 3 6 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 11 8 1 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 10 11 5 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00006 4 5 10 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 10 5 4 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 10 6 12 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 12 9 10 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 11 8 12 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 12 7 11 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C10 3 10 4.05594e-15 +C9 4 10 1.22684e-15 +C8 5 10 1.84673e-15 +C7 6 10 8.89936e-16 +C6 7 10 1.18586e-15 +C5 8 10 1.05357e-15 +C4 9 10 1.05357e-15 +C3 10 10 3.14518e-15 +C2 11 10 2.18533e-15 +C1 12 10 1.25899e-15 +.ends nao2o22_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx2_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx2_x1.spi new file mode 100644 index 000000000..deea1d03e --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx2_x1.spi @@ -0,0 +1,33 @@ +* Spice description of nmx2_x1 +* Spice driver version -988378200 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:55 + +* INTERF cmd i0 i1 nq vdd vss + + +.subckt nmx2_x1 3 2 1 9 5 7 +* NET 1 = i1 +* NET 2 = i0 +* NET 3 = cmd +* NET 5 = vdd +* NET 7 = vss +* NET 9 = nq +Mtr_00010 11 3 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00009 9 11 6 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.22U AS=0.6438P AD=0.6438P PS=5.02U PD=5.02U +Mtr_00008 4 3 9 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.22U AS=0.6438P AD=0.6438P PS=5.02U PD=5.02U +Mtr_00007 6 1 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.22U AS=0.6438P AD=0.6438P PS=5.02U PD=5.02U +Mtr_00006 5 2 4 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.22U AS=0.6438P AD=0.6438P PS=5.02U PD=5.02U +Mtr_00005 7 3 11 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00004 10 3 9 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00003 9 11 8 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00002 7 1 10 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00001 8 2 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +C11 1 7 1.05913e-15 +C10 2 7 8.67061e-16 +C9 3 7 1.29027e-15 +C7 5 7 1.80157e-15 +C5 7 7 1.80157e-15 +C3 9 7 1.46257e-15 +C1 11 7 3.81536e-15 +.ends nmx2_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx2_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx2_x4.spi new file mode 100644 index 000000000..f1fba1f3c --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx2_x4.spi @@ -0,0 +1,41 @@ +* Spice description of nmx2_x4 +* Spice driver version 548686760 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:56 + +* INTERF cmd i0 i1 nq vdd vss + + +.subckt nmx2_x4 7 6 8 5 3 9 +* NET 3 = vdd +* NET 5 = nq +* NET 6 = i0 +* NET 7 = cmd +* NET 8 = i1 +* NET 9 = vss +Mtr_00016 3 11 4 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00015 5 4 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00014 3 4 5 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00013 1 8 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00012 10 7 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00011 3 6 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 2 7 11 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 11 10 1 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 4 11 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00007 9 4 5 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 5 4 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 9 8 12 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 9 7 10 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00003 12 7 11 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 11 10 13 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 13 6 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C11 3 9 3.43448e-15 +C10 4 9 1.99373e-15 +C9 5 9 1.22684e-15 +C8 6 9 9.82078e-16 +C7 7 9 1.48614e-15 +C6 8 9 8.42982e-16 +C5 9 9 2.93624e-15 +C4 10 9 3.32851e-15 +C3 11 9 2.65837e-15 +.ends nmx2_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx3_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx3_x1.spi new file mode 100644 index 000000000..9f26d2c26 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx3_x1.spi @@ -0,0 +1,48 @@ +* Spice description of nmx3_x1 +* Spice driver version 338504616 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:56 + +* INTERF cmd0 cmd1 i0 i1 i2 nq vdd vss + + +.subckt nmx3_x1 6 10 5 11 9 16 12 17 +* NET 5 = i0 +* NET 6 = cmd0 +* NET 9 = i2 +* NET 10 = cmd1 +* NET 11 = i1 +* NET 12 = vdd +* NET 16 = nq +* NET 17 = vss +Mtr_00018 12 6 7 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00017 18 10 12 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00016 16 5 1 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00015 4 9 3 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00014 16 10 4 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00013 2 18 16 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00012 1 6 12 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00011 12 7 3 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00010 3 11 2 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00009 16 5 8 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00008 17 6 13 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00007 8 7 17 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00006 7 6 17 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Mtr_00005 17 10 18 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Mtr_00004 15 9 13 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00003 14 10 16 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00002 16 18 15 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00001 13 11 14 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +C16 3 17 6.69675e-16 +C14 5 17 7.53017e-16 +C13 6 17 1.3491e-15 +C12 7 17 2.14625e-15 +C10 9 17 7.83035e-16 +C9 10 17 1.90919e-15 +C8 11 17 8.61981e-16 +C7 12 17 2.83819e-15 +C6 13 17 6.69675e-16 +C3 16 17 3.1823e-15 +C2 17 17 2.83819e-15 +C1 18 17 1.85648e-15 +.ends nmx3_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx3_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx3_x4.spi new file mode 100644 index 000000000..15e53e4a4 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nmx3_x4.spi @@ -0,0 +1,56 @@ +* Spice description of nmx3_x4 +* Spice driver version -641147992 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:57 + +* INTERF cmd0 cmd1 i0 i1 i2 nq vdd vss + + +.subckt nmx3_x4 5 12 6 13 11 9 14 19 +* NET 5 = cmd0 +* NET 6 = i0 +* NET 9 = nq +* NET 11 = i2 +* NET 12 = cmd1 +* NET 13 = i1 +* NET 14 = vdd +* NET 19 = vss +Mtr_00024 14 18 7 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00023 14 7 9 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00022 9 7 14 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00021 14 5 8 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00020 20 12 14 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00019 18 6 1 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00018 4 11 3 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00017 18 12 4 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00016 2 20 18 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00015 1 5 14 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00014 14 8 3 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00013 3 13 2 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00012 7 18 19 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00011 19 7 9 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 9 7 19 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 18 6 10 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00008 19 5 15 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00007 10 8 19 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00006 8 5 19 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Mtr_00005 19 12 20 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Mtr_00004 17 11 15 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00003 16 12 18 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00002 18 20 17 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00001 15 13 16 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +C18 3 19 6.69675e-16 +C16 5 19 1.3491e-15 +C15 6 19 8.12635e-16 +C14 7 19 1.99373e-15 +C13 8 19 2.22662e-15 +C12 9 19 1.22684e-15 +C10 11 19 7.83035e-16 +C9 12 19 1.90919e-15 +C8 13 19 8.61981e-16 +C7 14 19 4.36396e-15 +C6 15 19 6.69675e-16 +C3 18 19 4.21202e-15 +C2 19 19 4.0318e-15 +C1 20 19 1.86937e-15 +.ends nmx3_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no2_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no2_x1.spi new file mode 100644 index 000000000..47176212b --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no2_x1.spi @@ -0,0 +1,24 @@ +* Spice description of no2_x1 +* Spice driver version -1834198104 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:58 + +* INTERF i0 i1 nq vdd vss + + +.subckt no2_x1 2 1 5 3 6 +* NET 1 = i1 +* NET 2 = i0 +* NET 3 = vdd +* NET 5 = nq +* NET 6 = vss +Mtr_00004 3 1 4 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00003 4 2 5 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00002 5 1 6 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 6 2 5 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C6 1 6 9.24715e-16 +C5 2 6 9.24715e-16 +C4 3 6 1.21174e-15 +C2 5 6 1.42507e-15 +C1 6 6 1.2921e-15 +.ends no2_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no2_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no2_x4.spi new file mode 100644 index 000000000..300aaff75 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no2_x4.spi @@ -0,0 +1,32 @@ +* Spice description of no2_x4 +* Spice driver version 1024228264 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:58 + +* INTERF i0 i1 nq vdd vss + + +.subckt no2_x4 1 2 7 5 8 +* NET 1 = i0 +* NET 2 = i1 +* NET 5 = vdd +* NET 7 = nq +* NET 8 = vss +Mtr_00010 5 6 3 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 7 3 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 5 3 7 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 5 2 4 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 4 1 6 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 3 6 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 8 3 7 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 7 3 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 6 2 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 8 1 6 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C8 1 8 9.24715e-16 +C7 2 8 8.17567e-16 +C6 3 8 1.99373e-15 +C4 5 8 2.51249e-15 +C3 6 8 2.76016e-15 +C2 7 8 1.22684e-15 +C1 8 8 2.42677e-15 +.ends no2_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no3_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no3_x1.spi new file mode 100644 index 000000000..36f20a1c3 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no3_x1.spi @@ -0,0 +1,28 @@ +* Spice description of no3_x1 +* Spice driver version -321918040 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:57:59 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt no3_x1 3 1 2 7 6 8 +* NET 1 = i1 +* NET 2 = i2 +* NET 3 = i0 +* NET 6 = vdd +* NET 7 = nq +* NET 8 = vss +Mtr_00006 5 3 7 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 4 1 5 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 6 2 4 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00003 8 1 7 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 7 2 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 7 3 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C8 1 8 9.24715e-16 +C7 2 8 9.24715e-16 +C6 3 8 8.17567e-16 +C3 6 8 1.38156e-15 +C2 7 8 2.11082e-15 +C1 8 8 1.46192e-15 +.ends no3_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no3_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no3_x4.spi new file mode 100644 index 000000000..348d91e8d --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no3_x4.spi @@ -0,0 +1,36 @@ +* Spice description of no3_x4 +* Spice driver version 57265064 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:00 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt no3_x4 1 3 2 8 7 9 +* NET 1 = i0 +* NET 2 = i2 +* NET 3 = i1 +* NET 7 = vdd +* NET 8 = nq +* NET 9 = vss +Mtr_00012 7 10 4 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 5 1 10 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 7 2 6 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 6 3 5 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 8 4 7 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 7 4 8 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 4 10 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 10 1 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 9 4 8 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 8 4 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 10 2 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 9 3 10 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C10 1 9 8.17567e-16 +C9 2 9 8.17567e-16 +C8 3 9 9.24715e-16 +C7 4 9 1.99373e-15 +C4 7 9 2.68231e-15 +C3 8 9 1.22684e-15 +C2 9 9 2.59659e-15 +C1 10 9 3.71378e-15 +.ends no3_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no4_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no4_x1.spi new file mode 100644 index 000000000..eb9d14f6a --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no4_x1.spi @@ -0,0 +1,32 @@ +* Spice description of no4_x1 +* Spice driver version -7042136 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:01 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt no4_x1 4 1 3 2 9 7 10 +* NET 1 = i1 +* NET 2 = i3 +* NET 3 = i2 +* NET 4 = i0 +* NET 7 = vdd +* NET 9 = nq +* NET 10 = vss +Mtr_00008 8 4 9 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 7 2 5 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 5 3 6 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 6 1 8 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 9 1 10 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 9 2 10 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 10 3 9 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 10 4 9 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C10 1 10 9.24715e-16 +C9 2 10 9.24715e-16 +C8 3 10 9.24715e-16 +C7 4 10 8.17567e-16 +C4 7 10 1.55138e-15 +C2 9 10 2.26082e-15 +C1 10 10 1.87818e-15 +.ends no4_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no4_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no4_x4.spi new file mode 100644 index 000000000..26184a4c3 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/no4_x4.spi @@ -0,0 +1,40 @@ +* Spice description of no4_x4 +* Spice driver version -248919128 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:01 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt no4_x4 6 3 5 4 2 10 12 +* NET 2 = nq +* NET 3 = i1 +* NET 4 = i3 +* NET 5 = i2 +* NET 6 = i0 +* NET 10 = vdd +* NET 12 = vss +Mtr_00014 10 11 1 10 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00013 7 6 11 10 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00012 9 5 8 10 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 2 1 10 10 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 10 1 2 10 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 8 3 7 10 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 10 4 9 10 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 1 11 12 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00006 12 6 11 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 11 3 12 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 12 1 2 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 2 1 12 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 11 4 12 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 12 5 11 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C12 1 12 1.99373e-15 +C11 2 12 1.22684e-15 +C10 3 12 9.24715e-16 +C9 4 12 8.17567e-16 +C8 5 12 9.24715e-16 +C7 6 12 9.24715e-16 +C3 10 12 2.85214e-15 +C2 11 12 3.84236e-15 +C1 12 12 3.01286e-15 +.ends no4_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa22_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa22_x1.spi new file mode 100644 index 000000000..89f08e431 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa22_x1.spi @@ -0,0 +1,29 @@ +* Spice description of noa22_x1 +* Spice driver version 1328053160 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:02 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt noa22_x1 1 3 2 7 4 6 +* NET 1 = i0 +* NET 2 = i2 +* NET 3 = i1 +* NET 4 = vdd +* NET 6 = vss +* NET 7 = nq +Mtr_00006 4 2 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 7 1 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 5 3 7 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00003 6 1 8 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 8 3 7 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 7 2 6 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C8 1 6 8.60287e-16 +C7 2 6 9.67435e-16 +C6 3 6 9.67435e-16 +C5 4 6 1.21548e-15 +C4 5 6 6.5896e-16 +C3 6 6 1.46192e-15 +C2 7 6 1.07148e-15 +.ends noa22_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa22_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa22_x4.spi new file mode 100644 index 000000000..4215d2cdf --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa22_x4.spi @@ -0,0 +1,37 @@ +* Spice description of noa22_x4 +* Spice driver version -935949400 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:03 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt noa22_x4 3 5 4 8 6 10 +* NET 3 = i0 +* NET 4 = i2 +* NET 5 = i1 +* NET 6 = vdd +* NET 8 = nq +* NET 10 = vss +Mtr_00012 6 7 2 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 6 4 1 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 7 3 1 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 1 5 7 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 6 2 8 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 8 2 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 2 7 10 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 7 4 10 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 9 5 7 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 10 3 9 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 10 2 8 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 8 2 10 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C10 1 10 4.33949e-16 +C9 2 10 1.99373e-15 +C8 3 10 1.16072e-15 +C7 4 10 9.46424e-16 +C6 5 10 1.19053e-15 +C5 6 10 2.68231e-15 +C4 7 10 2.53515e-15 +C3 8 10 1.22684e-15 +C1 10 10 2.59659e-15 +.ends noa22_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a22_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a22_x1.spi new file mode 100644 index 000000000..74a32b0ca --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a22_x1.spi @@ -0,0 +1,33 @@ +* Spice description of noa2a22_x1 +* Spice driver version 687975336 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:03 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt noa2a22_x1 4 3 2 1 8 6 9 +* NET 1 = i3 +* NET 2 = i2 +* NET 3 = i1 +* NET 4 = i0 +* NET 6 = vdd +* NET 8 = nq +* NET 9 = vss +Mtr_00008 6 1 5 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 5 2 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 5 3 8 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 8 4 5 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 7 2 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 8 1 7 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 10 3 8 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 9 4 10 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C10 1 9 9.67435e-16 +C9 2 9 8.038e-16 +C8 3 9 8.60287e-16 +C7 4 9 8.85424e-16 +C6 5 9 1.484e-15 +C5 6 9 1.3853e-15 +C3 8 9 1.24827e-15 +C2 9 9 1.63174e-15 +.ends noa2a22_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a22_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a22_x4.spi new file mode 100644 index 000000000..59efce6a7 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a22_x4.spi @@ -0,0 +1,41 @@ +* Spice description of noa2a22_x4 +* Spice driver version -973821016 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:04 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt noa2a22_x4 6 5 7 8 3 2 12 +* NET 2 = vdd +* NET 3 = nq +* NET 5 = i1 +* NET 6 = i0 +* NET 7 = i2 +* NET 8 = i3 +* NET 12 = vss +Mtr_00014 2 8 1 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00013 1 7 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00012 1 5 10 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 10 6 1 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 4 10 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 3 4 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 2 4 3 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 9 7 12 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00006 10 8 9 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 11 5 10 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 12 6 11 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 12 10 4 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 3 4 12 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 12 4 3 12 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C12 1 12 1.484e-15 +C11 2 12 3.8095e-15 +C10 3 12 1.22684e-15 +C9 4 12 2.18424e-15 +C8 5 12 1.05357e-15 +C7 6 12 1.07871e-15 +C6 7 12 8.89936e-16 +C5 8 12 9.46424e-16 +C3 10 12 2.59297e-15 +C1 12 12 3.39162e-15 +.ends noa2a22_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a23_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a23_x1.spi new file mode 100644 index 000000000..105f328e0 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a23_x1.spi @@ -0,0 +1,42 @@ +* Spice description of noa2a2a23_x1 +* Spice driver version -223765592 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:05 + +* INTERF i0 i1 i2 i3 i4 i5 nq vdd vss + + +.subckt noa2a2a23_x1 5 8 6 7 1 2 12 3 14 +* NET 1 = i4 +* NET 2 = i5 +* NET 3 = vdd +* NET 5 = i0 +* NET 6 = i2 +* NET 7 = i3 +* NET 8 = i1 +* NET 12 = nq +* NET 14 = vss +Mtr_00012 3 1 9 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 9 2 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 12 5 10 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 9 7 10 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 10 6 9 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 10 8 12 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 11 6 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 12 7 11 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 13 8 12 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 14 5 13 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 12 2 4 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 4 1 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C14 1 14 7.53139e-16 +C13 2 14 8.60287e-16 +C12 3 14 3.01822e-15 +C10 5 14 8.85424e-16 +C9 6 14 7.53139e-16 +C8 7 14 6.45991e-16 +C7 8 14 8.60287e-16 +C6 9 14 1.01255e-15 +C5 10 14 1.20006e-15 +C3 12 14 1.97688e-15 +C1 14 14 2.55748e-15 +.ends noa2a2a23_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a23_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a23_x4.spi new file mode 100644 index 000000000..bd1ba3558 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a23_x4.spi @@ -0,0 +1,50 @@ +* Spice description of noa2a2a23_x4 +* Spice driver version 261217192 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:06 + +* INTERF i0 i1 i2 i3 i4 i5 nq vdd vss + + +.subckt noa2a2a23_x4 9 12 10 11 4 5 3 6 16 +* NET 3 = nq +* NET 4 = i4 +* NET 5 = i5 +* NET 6 = vdd +* NET 9 = i0 +* NET 10 = i2 +* NET 11 = i3 +* NET 12 = i1 +* NET 16 = vss +Mtr_00018 2 11 1 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00017 1 10 2 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00016 1 12 14 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00015 6 4 2 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00014 2 5 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00013 14 9 1 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00012 7 14 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 3 7 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 6 7 3 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 8 4 16 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00008 13 10 16 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00007 14 11 13 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00006 15 12 14 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 16 9 15 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 14 5 8 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 16 7 3 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 3 7 16 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 16 14 7 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C16 1 16 1.20006e-15 +C15 2 16 7.87538e-16 +C14 3 16 1.22684e-15 +C13 4 16 9.46424e-16 +C12 5 16 9.19745e-16 +C11 6 16 4.90131e-15 +C10 7 16 1.8253e-15 +C8 9 16 1.07871e-15 +C7 10 16 9.46424e-16 +C6 11 16 8.39275e-16 +C5 12 16 1.05357e-15 +C3 14 16 3.19052e-15 +C1 16 16 4.31735e-15 +.ends noa2a2a23_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a2a24_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a2a24_x1.spi new file mode 100644 index 000000000..7ae228a20 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a2a24_x1.spi @@ -0,0 +1,51 @@ +* Spice description of noa2a2a2a24_x1 +* Spice driver version 860670888 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:06 + +* INTERF i0 i1 i2 i3 i4 i5 i6 i7 nq vdd vss + + +.subckt noa2a2a2a24_x1 11 10 9 8 1 3 2 4 16 12 17 +* NET 1 = i4 +* NET 2 = i6 +* NET 3 = i5 +* NET 4 = i7 +* NET 8 = i3 +* NET 9 = i2 +* NET 10 = i1 +* NET 11 = i0 +* NET 12 = vdd +* NET 16 = nq +* NET 17 = vss +Mtr_00016 14 1 5 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00015 16 2 5 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00014 5 4 16 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00013 5 3 14 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00012 14 8 13 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 13 9 14 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 13 10 12 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 12 11 13 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 7 4 17 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 16 2 7 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 6 3 16 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 17 1 6 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 15 9 17 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 16 8 15 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 18 10 16 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 17 11 18 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C18 1 17 7.78276e-16 +C17 2 17 7.53139e-16 +C16 3 17 7.53139e-16 +C15 4 17 9.92572e-16 +C14 5 17 1.03398e-15 +C11 8 17 7.53139e-16 +C10 9 17 6.96652e-16 +C9 10 17 9.67435e-16 +C8 11 17 8.85424e-16 +C7 12 17 2.40424e-15 +C6 13 17 1.20006e-15 +C5 14 17 5.62527e-16 +C3 16 17 2.66799e-15 +C2 17 17 3.14357e-15 +.ends noa2a2a2a24_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a2a24_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a2a24_x4.spi new file mode 100644 index 000000000..2e940e5b9 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2a2a2a24_x4.spi @@ -0,0 +1,59 @@ +* Spice description of noa2a2a2a24_x4 +* Spice driver version 280738728 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:07 + +* INTERF i0 i1 i2 i3 i4 i5 i6 i7 nq vdd vss + + +.subckt noa2a2a2a24_x4 15 16 13 14 7 8 10 9 5 4 19 +* NET 4 = vdd +* NET 5 = nq +* NET 7 = i4 +* NET 8 = i5 +* NET 9 = i7 +* NET 10 = i6 +* NET 13 = i2 +* NET 14 = i3 +* NET 15 = i0 +* NET 16 = i1 +* NET 19 = vss +Mtr_00022 4 15 3 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00021 1 8 2 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00020 2 14 3 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00019 3 13 2 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00018 3 16 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00017 2 7 1 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00016 17 10 1 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00015 1 9 17 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00014 5 6 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00013 4 6 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00012 6 17 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 17 14 20 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00010 18 16 17 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00009 19 15 18 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00008 12 9 19 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00007 17 10 12 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00006 11 8 17 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 19 7 11 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 20 13 19 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 5 6 19 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 19 17 6 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 19 6 5 19 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C20 1 19 1.03398e-15 +C19 2 19 5.62527e-16 +C18 3 19 1.20006e-15 +C17 4 19 4.82844e-15 +C16 5 19 1.22684e-15 +C15 6 19 1.8253e-15 +C14 7 19 9.7156e-16 +C13 8 19 9.46424e-16 +C12 9 19 9.46424e-16 +C11 10 19 9.46424e-16 +C8 13 19 8.89936e-16 +C7 14 19 9.46424e-16 +C6 15 19 1.07871e-15 +C5 16 19 1.16072e-15 +C4 17 19 3.19588e-15 +C2 19 19 4.90344e-15 +.ends noa2a2a2a24_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2ao222_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2ao222_x1.spi new file mode 100644 index 000000000..c820cca95 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2ao222_x1.spi @@ -0,0 +1,38 @@ +* Spice description of noa2ao222_x1 +* Spice driver version 141777832 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:08 + +* INTERF i0 i1 i2 i3 i4 nq vdd vss + + +.subckt noa2ao222_x1 5 6 4 2 7 9 1 10 +* NET 1 = vdd +* NET 2 = i3 +* NET 4 = i2 +* NET 5 = i0 +* NET 6 = i1 +* NET 7 = i4 +* NET 9 = nq +* NET 10 = vss +Mtr_00010 1 5 3 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00009 1 6 3 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00008 9 7 3 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00007 3 2 8 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 8 4 9 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 10 4 12 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00004 12 7 9 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00003 9 6 11 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00002 12 2 10 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00001 11 5 10 10 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +C12 1 10 1.55513e-15 +C11 2 10 9.1183e-16 +C10 3 10 1.36614e-15 +C9 4 10 9.94505e-16 +C8 5 10 9.88236e-16 +C7 6 10 1.01723e-15 +C6 7 10 8.29611e-16 +C4 9 10 1.54829e-15 +C3 10 10 1.80157e-15 +C1 12 10 8.83971e-16 +.ends noa2ao222_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2ao222_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2ao222_x4.spi new file mode 100644 index 000000000..c4d9446ec --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa2ao222_x4.spi @@ -0,0 +1,46 @@ +* Spice description of noa2ao222_x4 +* Spice driver version 408943528 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:08 + +* INTERF i0 i1 i2 i3 i4 nq vdd vss + + +.subckt noa2ao222_x4 9 8 6 1 7 4 3 14 +* NET 1 = i3 +* NET 3 = vdd +* NET 4 = nq +* NET 6 = i2 +* NET 7 = i4 +* NET 8 = i1 +* NET 9 = i0 +* NET 14 = vss +Mtr_00016 3 9 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00015 3 8 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00014 13 7 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00013 3 13 5 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00012 3 5 4 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 4 5 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 10 6 13 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 2 1 10 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 11 1 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00007 12 9 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00006 14 6 11 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 11 7 13 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 13 8 12 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 5 13 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 14 5 4 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 4 5 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C14 1 14 8.17567e-16 +C13 2 14 1.36614e-15 +C12 3 14 3.97932e-15 +C11 4 14 1.22684e-15 +C10 5 14 2.35032e-15 +C9 6 14 9.59174e-16 +C8 7 14 8.68268e-16 +C7 8 14 1.05589e-15 +C6 9 14 1.02689e-15 +C4 11 14 8.83971e-16 +C2 13 14 2.56202e-15 +C1 14 14 3.3525e-15 +.ends noa2ao222_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa3ao322_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa3ao322_x1.spi new file mode 100644 index 000000000..9093dcdaf --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa3ao322_x1.spi @@ -0,0 +1,46 @@ +* Spice description of noa3ao322_x1 +* Spice driver version 252046248 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:09 + +* INTERF i0 i1 i2 i3 i4 i5 i6 nq vdd vss + + +.subckt noa3ao322_x1 8 11 10 2 4 3 9 16 1 13 +* NET 1 = vdd +* NET 2 = i3 +* NET 3 = i5 +* NET 4 = i4 +* NET 8 = i0 +* NET 9 = i6 +* NET 10 = i2 +* NET 11 = i1 +* NET 13 = vss +* NET 16 = nq +Mtr_00014 1 8 5 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00013 5 11 1 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00012 1 10 5 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00011 5 9 16 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00010 7 2 16 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 6 4 7 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 6 3 5 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 15 4 13 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00006 13 2 15 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00005 15 9 16 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00004 16 10 14 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00003 14 11 12 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00002 12 8 13 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00001 13 3 15 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +C16 1 13 2.31104e-15 +C15 2 13 9.37601e-16 +C14 3 13 1.04475e-15 +C13 4 13 9.37601e-16 +C12 5 13 1.51614e-15 +C9 8 13 1.10854e-15 +C8 9 13 8.2639e-16 +C7 10 13 1.08341e-15 +C6 11 13 1.08341e-15 +C4 13 13 2.55748e-15 +C2 15 13 9.42902e-16 +C1 16 13 1.30721e-15 +.ends noa3ao322_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa3ao322_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa3ao322_x4.spi new file mode 100644 index 000000000..df270ca4c --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/noa3ao322_x4.spi @@ -0,0 +1,54 @@ +* Spice description of noa3ao322_x4 +* Spice driver version 658402216 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:10 + +* INTERF i0 i1 i2 i3 i4 i5 i6 nq vdd vss + + +.subckt noa3ao322_x4 13 11 1 2 4 5 3 15 14 16 +* NET 1 = i2 +* NET 2 = i3 +* NET 3 = i6 +* NET 4 = i4 +* NET 5 = i5 +* NET 11 = i1 +* NET 13 = i0 +* NET 14 = vdd +* NET 15 = nq +* NET 16 = vss +Mtr_00020 7 5 8 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00019 15 18 14 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00018 15 18 14 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00017 14 13 8 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00016 8 11 14 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00015 14 1 8 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00014 18 12 14 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00013 8 3 12 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00012 6 2 12 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 7 4 6 14 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 16 5 10 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00009 12 1 9 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00008 10 3 12 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00007 16 2 10 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00006 10 4 16 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00005 9 11 17 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00004 17 13 16 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00003 16 12 18 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 15 18 16 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 16 18 15 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C18 1 16 1.07273e-15 +C17 2 16 9.66594e-16 +C16 3 16 7.48235e-16 +C15 4 16 9.39915e-16 +C14 5 16 1.04475e-15 +C11 8 16 1.49471e-15 +C9 10 16 9.42902e-16 +C8 11 16 9.76258e-16 +C7 12 16 3.66263e-15 +C6 13 16 8.6911e-16 +C5 14 16 3.06695e-15 +C4 15 16 8.94686e-16 +C3 16 16 3.5009e-15 +C1 18 16 1.84673e-15 +.ends noa3ao322_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nts_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nts_x1.spi new file mode 100644 index 000000000..f5427242b --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nts_x1.spi @@ -0,0 +1,27 @@ +* Spice description of nts_x1 +* Spice driver version -563840088 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:11 + +* INTERF cmd i nq vdd vss + + +.subckt nts_x1 1 2 8 3 6 +* NET 1 = cmd +* NET 2 = i +* NET 3 = vdd +* NET 6 = vss +* NET 8 = nq +Mtr_00006 8 2 4 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 4 5 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 5 1 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 8 2 7 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 7 1 6 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 6 1 5 6 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C8 1 6 1.10285e-15 +C7 2 6 1.18173e-15 +C6 3 6 1.36013e-15 +C4 5 6 1.30376e-15 +C3 6 6 1.21548e-15 +C1 8 6 1.22684e-15 +.ends nts_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nts_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nts_x2.spi new file mode 100644 index 000000000..eb9a05d7a --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nts_x2.spi @@ -0,0 +1,31 @@ +* Spice description of nts_x2 +* Spice driver version 974969768 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:11 + +* INTERF cmd i nq vdd vss + + +.subckt nts_x2 1 2 7 5 9 +* NET 1 = cmd +* NET 2 = i +* NET 5 = vdd +* NET 7 = nq +* NET 9 = vss +Mtr_00010 8 1 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 3 2 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00008 7 8 3 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00007 4 8 7 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00006 5 2 4 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00005 6 2 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00004 7 1 6 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00003 9 1 8 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 10 2 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00001 7 1 10 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +C10 1 9 1.55285e-15 +C9 2 9 1.54897e-15 +C6 5 9 2.41767e-15 +C4 7 9 1.70901e-15 +C3 8 9 2.21365e-15 +C2 9 9 1.96765e-15 +.ends nts_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nxr2_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nxr2_x1.spi new file mode 100644 index 000000000..a9dde3182 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nxr2_x1.spi @@ -0,0 +1,35 @@ +* Spice description of nxr2_x1 +* Spice driver version 1740159912 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:12 + +* INTERF i0 i1 nq vdd vss + + +.subckt nxr2_x1 3 1 8 4 7 +* NET 1 = i1 +* NET 3 = i0 +* NET 4 = vdd +* NET 7 = vss +* NET 8 = nq +Mtr_00012 4 2 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00011 5 6 8 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00010 8 1 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00009 5 3 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00008 2 1 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 4 3 6 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 10 1 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00005 8 6 10 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00004 9 2 8 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00003 7 3 9 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00002 6 3 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 7 1 2 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C10 1 7 1.92291e-15 +C9 2 7 2.18588e-15 +C8 3 7 1.31112e-15 +C7 4 7 2.14121e-15 +C6 5 7 1.1947e-15 +C5 6 7 1.57758e-15 +C4 7 7 2.14121e-15 +C3 8 7 1.78937e-15 +.ends nxr2_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nxr2_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nxr2_x4.spi new file mode 100644 index 000000000..91f512806 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/nxr2_x4.spi @@ -0,0 +1,40 @@ +* Spice description of nxr2_x4 +* Spice driver version -394990680 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:13 + +* INTERF i0 i1 nq vdd vss + + +.subckt nxr2_x4 3 2 1 5 9 +* NET 1 = nq +* NET 2 = i1 +* NET 3 = i0 +* NET 5 = vdd +* NET 9 = vss +Mtr_00016 1 7 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00015 5 7 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00014 6 3 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00013 4 2 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00012 5 3 10 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 5 2 6 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00010 6 10 7 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00009 7 4 6 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00008 1 7 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 9 7 1 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 11 4 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00005 7 10 11 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00004 8 2 7 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00003 9 3 8 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00002 10 3 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 9 2 4 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C11 1 9 1.22684e-15 +C10 2 9 1.72126e-15 +C9 3 9 1.31112e-15 +C8 4 9 1.97158e-15 +C7 5 9 4.22576e-15 +C6 6 9 1.38221e-15 +C5 7 9 2.96717e-15 +C3 9 9 3.30965e-15 +C2 10 9 1.57758e-15 +.ends nxr2_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o2_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o2_x2.spi new file mode 100644 index 000000000..7c1189462 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o2_x2.spi @@ -0,0 +1,27 @@ +* Spice description of o2_x2 +* Spice driver version 597941160 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:13 + +* INTERF i0 i1 q vdd vss + + +.subckt o2_x2 1 2 6 4 7 +* NET 1 = i0 +* NET 2 = i1 +* NET 4 = vdd +* NET 6 = q +* NET 7 = vss +Mtr_00006 4 1 3 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 3 2 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 6 5 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00003 7 2 5 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 5 1 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 6 5 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C7 1 7 7.3965e-16 +C6 2 7 1.01861e-15 +C4 4 7 1.21548e-15 +C3 5 7 2.17821e-15 +C2 6 7 1.22684e-15 +C1 7 7 1.52085e-15 +.ends o2_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o2_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o2_x4.spi new file mode 100644 index 000000000..376aa3c9d --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o2_x4.spi @@ -0,0 +1,29 @@ +* Spice description of o2_x4 +* Spice driver version -759727192 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:14 + +* INTERF i0 i1 q vdd vss + + +.subckt o2_x4 2 3 5 4 7 +* NET 2 = i0 +* NET 3 = i1 +* NET 4 = vdd +* NET 5 = q +* NET 7 = vss +Mtr_00008 5 6 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 5 6 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.22U AS=0.6438P AD=0.6438P PS=5.02U PD=5.02U +Mtr_00006 4 2 1 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.98U AS=0.5742P AD=0.5742P PS=4.54U PD=4.54U +Mtr_00005 1 3 6 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.98U AS=0.5742P AD=0.5742P PS=4.54U PD=4.54U +Mtr_00004 7 6 5 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 7 3 6 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 6 2 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 5 6 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C6 2 7 1.18803e-15 +C5 3 7 1.07374e-15 +C4 4 7 2.17284e-15 +C3 5 7 1.22684e-15 +C2 6 7 2.00579e-15 +C1 7 7 2.31213e-15 +.ends o2_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o3_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o3_x2.spi new file mode 100644 index 000000000..48c1d3aa5 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o3_x2.spi @@ -0,0 +1,31 @@ +* Spice description of o3_x2 +* Spice driver version 1171954600 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:15 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt o3_x2 3 1 2 7 4 8 +* NET 1 = i1 +* NET 2 = i2 +* NET 3 = i0 +* NET 4 = vdd +* NET 7 = q +* NET 8 = vss +Mtr_00008 4 3 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 5 1 6 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 9 2 6 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 7 9 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00004 8 2 9 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 8 1 9 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 9 3 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 7 9 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C9 1 8 1.00519e-15 +C8 2 8 1.03186e-15 +C7 3 8 7.3965e-16 +C6 4 8 1.3853e-15 +C3 7 8 1.22684e-15 +C2 8 8 1.69067e-15 +C1 9 8 2.41393e-15 +.ends o3_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o3_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o3_x4.spi new file mode 100644 index 000000000..a11fee271 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o3_x4.spi @@ -0,0 +1,33 @@ +* Spice description of o3_x4 +* Spice driver version 1656470440 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:15 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt o3_x4 3 1 2 7 4 8 +* NET 1 = i1 +* NET 2 = i2 +* NET 3 = i0 +* NET 4 = vdd +* NET 7 = q +* NET 8 = vss +Mtr_00010 5 1 6 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 9 2 6 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 4 3 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 4 9 7 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 7 9 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 8 1 9 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 8 2 9 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 8 9 7 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 7 9 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 9 3 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C9 1 8 1.03418e-15 +C8 2 8 1.17782e-15 +C7 3 8 1.03186e-15 +C6 4 8 3.05359e-15 +C3 7 8 1.22684e-15 +C2 8 8 2.46427e-15 +C1 9 8 2.81106e-15 +.ends o3_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o4_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o4_x2.spi new file mode 100644 index 000000000..b89adc50a --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o4_x2.spi @@ -0,0 +1,35 @@ +* Spice description of o4_x2 +* Spice driver version -1758610520 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:16 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt o4_x2 2 5 3 4 1 7 11 +* NET 1 = q +* NET 2 = i0 +* NET 3 = i2 +* NET 4 = i3 +* NET 5 = i1 +* NET 7 = vdd +* NET 11 = vss +Mtr_00010 9 3 8 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 10 4 9 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 6 5 8 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 7 2 6 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 1 10 7 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 11 3 10 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 10 4 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 10 2 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 11 5 10 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 1 10 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C11 1 11 1.22684e-15 +C10 2 11 8.46798e-16 +C9 3 11 1.03186e-15 +C8 4 11 1.03186e-15 +C7 5 11 1.00519e-15 +C5 7 11 2.26605e-15 +C2 10 11 2.8211e-15 +C1 11 11 2.46427e-15 +.ends o4_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o4_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o4_x4.spi new file mode 100644 index 000000000..c76237c80 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/o4_x4.spi @@ -0,0 +1,37 @@ +* Spice description of o4_x4 +* Spice driver version -1129636952 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:17 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt o4_x4 2 5 3 4 1 7 11 +* NET 1 = q +* NET 2 = i0 +* NET 3 = i2 +* NET 4 = i3 +* NET 5 = i1 +* NET 7 = vdd +* NET 11 = vss +Mtr_00012 1 10 7 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 9 3 8 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 10 4 9 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 6 5 8 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 7 2 6 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 1 10 7 7 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 11 10 1 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 11 3 10 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 10 4 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 10 2 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 11 5 10 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 1 10 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C11 1 11 1.22684e-15 +C10 2 11 8.46798e-16 +C9 3 11 1.03186e-15 +C8 4 11 1.03186e-15 +C7 5 11 1.00519e-15 +C5 7 11 3.22341e-15 +C2 10 11 3.10036e-15 +C1 11 11 3.12698e-15 +.ends o4_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa22_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa22_x2.spi new file mode 100644 index 000000000..5716fc16d --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa22_x2.spi @@ -0,0 +1,32 @@ +* Spice description of oa22_x2 +* Spice driver version -1310008408 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:18 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt oa22_x2 2 4 3 8 5 9 +* NET 2 = i0 +* NET 3 = i2 +* NET 4 = i1 +* NET 5 = vdd +* NET 8 = q +* NET 9 = vss +Mtr_00008 5 7 8 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.22U AS=0.6438P AD=0.6438P PS=5.02U PD=5.02U +Mtr_00007 1 4 7 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 5 3 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 7 2 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 8 7 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 9 2 6 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 6 4 7 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 7 3 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C9 1 9 6.5896e-16 +C8 2 9 1.05357e-15 +C7 3 9 1.11274e-15 +C6 4 9 1.19203e-15 +C5 5 9 1.3853e-15 +C3 7 9 1.50332e-15 +C2 8 9 1.22684e-15 +C1 9 9 1.63174e-15 +.ends oa22_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa22_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa22_x4.spi new file mode 100644 index 000000000..58b7b998a --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa22_x4.spi @@ -0,0 +1,34 @@ +* Spice description of oa22_x4 +* Spice driver version 709237672 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:18 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt oa22_x4 2 4 3 6 5 9 +* NET 2 = i0 +* NET 3 = i2 +* NET 4 = i1 +* NET 5 = vdd +* NET 6 = q +* NET 9 = vss +Mtr_00010 5 8 6 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 6 8 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 1 4 8 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 5 3 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 8 2 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 6 8 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 6 8 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 9 2 7 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 7 4 8 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 8 3 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C9 1 9 6.5896e-16 +C8 2 9 1.06968e-15 +C7 3 9 9.61108e-16 +C6 4 9 1.23481e-15 +C5 5 9 3.05359e-15 +C4 6 9 1.22684e-15 +C2 8 9 2.15615e-15 +C1 9 9 2.63571e-15 +.ends oa22_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a22_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a22_x2.spi new file mode 100644 index 000000000..1623e8876 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a22_x2.spi @@ -0,0 +1,36 @@ +* Spice description of oa2a22_x2 +* Spice driver version -723342424 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:19 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt oa2a22_x2 5 4 6 7 3 2 11 +* NET 2 = vdd +* NET 3 = q +* NET 4 = i1 +* NET 5 = i0 +* NET 6 = i2 +* NET 7 = i3 +* NET 11 = vss +Mtr_00010 9 5 1 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00009 2 7 1 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00008 1 6 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00007 1 4 9 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00006 3 9 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 8 6 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00004 9 7 8 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00003 10 4 9 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00002 11 5 10 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00001 11 9 3 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C11 1 11 1.484e-15 +C10 2 11 2.68231e-15 +C9 3 11 1.22684e-15 +C8 4 11 1.01491e-15 +C7 5 11 1.04005e-15 +C6 6 11 8.51279e-16 +C5 7 11 9.07767e-16 +C3 9 11 2.426e-15 +C1 11 11 2.59659e-15 +.ends oa2a22_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a22_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a22_x4.spi new file mode 100644 index 000000000..430499a81 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a22_x4.spi @@ -0,0 +1,38 @@ +* Spice description of oa2a22_x4 +* Spice driver version 720481192 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:20 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt oa2a22_x4 5 4 6 7 3 2 11 +* NET 2 = vdd +* NET 3 = q +* NET 4 = i1 +* NET 5 = i0 +* NET 6 = i2 +* NET 7 = i3 +* NET 11 = vss +Mtr_00012 9 5 1 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mtr_00011 2 7 1 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mtr_00010 1 6 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mtr_00009 1 4 9 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mtr_00008 3 9 2 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00007 2 9 3 2 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 8 6 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00005 9 7 8 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00004 10 4 9 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00003 11 5 10 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00002 11 9 3 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 3 9 11 11 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C11 1 11 1.484e-15 +C10 2 11 3.66185e-15 +C9 3 11 1.22684e-15 +C8 4 11 9.76258e-16 +C7 5 11 1.00139e-15 +C6 6 11 8.12622e-16 +C5 7 11 8.6911e-16 +C3 9 11 2.70862e-15 +C1 11 11 3.2218e-15 +.ends oa2a22_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a23_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a23_x2.spi new file mode 100644 index 000000000..76369c98c --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a23_x2.spi @@ -0,0 +1,45 @@ +* Spice description of oa2a2a23_x2 +* Spice driver version 1518148520 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:20 + +* INTERF i0 i1 i2 i3 i4 i5 q vdd vss + + +.subckt oa2a2a23_x2 8 11 9 10 4 3 6 5 15 +* NET 3 = i5 +* NET 4 = i4 +* NET 5 = vdd +* NET 6 = q +* NET 8 = i0 +* NET 9 = i2 +* NET 10 = i3 +* NET 11 = i1 +* NET 15 = vss +Mtr_00014 5 13 6 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00013 2 10 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00012 1 9 2 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 1 11 13 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 5 4 2 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 2 3 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 13 8 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 6 13 15 15 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 7 4 15 15 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 12 9 15 15 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 13 10 12 15 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 14 11 13 15 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 15 8 14 15 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 13 3 7 15 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C15 1 15 1.20006e-15 +C14 2 15 7.87538e-16 +C13 3 15 8.89936e-16 +C12 4 15 9.46424e-16 +C11 5 15 3.02196e-15 +C10 6 15 1.22684e-15 +C8 8 15 1.07871e-15 +C7 9 15 9.46424e-16 +C6 10 15 9.46424e-16 +C5 11 15 1.05357e-15 +C3 13 15 2.83717e-15 +C1 15 15 2.7273e-15 +.ends oa2a2a23_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a23_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a23_x4.spi new file mode 100644 index 000000000..7811b1a5c --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a23_x4.spi @@ -0,0 +1,47 @@ +* Spice description of oa2a2a23_x4 +* Spice driver version -1528611928 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:21 + +* INTERF i0 i1 i2 i3 i4 i5 q vdd vss + + +.subckt oa2a2a23_x4 11 10 8 9 3 4 6 5 14 +* NET 3 = i4 +* NET 4 = i5 +* NET 5 = vdd +* NET 6 = q +* NET 8 = i2 +* NET 9 = i3 +* NET 10 = i1 +* NET 11 = i0 +* NET 14 = vss +Mtr_00016 1 10 13 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00015 1 8 2 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00014 13 11 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00013 5 3 2 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00012 2 9 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00011 2 4 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00010 6 13 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 5 13 6 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 13 4 7 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00007 14 11 12 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00006 12 10 13 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00005 13 9 15 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00004 15 8 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00003 7 3 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00002 6 13 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 14 13 6 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C15 1 14 1.20006e-15 +C14 2 14 7.87538e-16 +C13 3 14 9.07767e-16 +C12 4 14 8.51279e-16 +C11 5 14 3.97932e-15 +C10 6 14 1.22684e-15 +C8 8 14 9.07767e-16 +C7 9 14 9.07767e-16 +C6 10 14 1.01491e-15 +C5 11 14 1.04005e-15 +C3 13 14 3.11643e-15 +C2 14 14 3.3525e-15 +.ends oa2a2a23_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a2a24_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a2a24_x2.spi new file mode 100644 index 000000000..62039a662 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a2a24_x2.spi @@ -0,0 +1,54 @@ +* Spice description of oa2a2a2a24_x2 +* Spice driver version -1569252440 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:22 + +* INTERF i0 i1 i2 i3 i4 i5 i6 i7 q vdd vss + + +.subckt oa2a2a2a24_x2 10 12 11 9 5 4 2 3 1 13 17 +* NET 1 = q +* NET 2 = i6 +* NET 3 = i7 +* NET 4 = i5 +* NET 5 = i4 +* NET 9 = i3 +* NET 10 = i0 +* NET 11 = i2 +* NET 12 = i1 +* NET 13 = vdd +* NET 17 = vss +Mtr_00018 15 12 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00017 15 11 14 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00016 6 3 18 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00015 13 10 15 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00014 18 2 6 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00013 14 5 6 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00012 14 9 15 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 6 4 14 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 1 18 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 8 4 18 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00008 18 9 16 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00007 17 5 8 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00006 16 11 17 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00005 18 2 7 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00004 7 3 17 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00003 17 10 19 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00002 19 12 18 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00001 17 18 1 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C19 1 17 1.22684e-15 +C18 2 17 8.04682e-16 +C17 3 17 8.04682e-16 +C16 4 17 8.04682e-16 +C15 5 17 8.29818e-16 +C14 6 17 1.03398e-15 +C11 9 17 8.04682e-16 +C10 10 17 9.36966e-16 +C9 11 17 7.48194e-16 +C8 12 17 1.01898e-15 +C7 13 17 3.70125e-15 +C6 14 17 5.62527e-16 +C5 15 17 1.20006e-15 +C3 17 17 4.10842e-15 +C2 18 17 3.0026e-15 +.ends oa2a2a2a24_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a2a24_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a2a24_x4.spi new file mode 100644 index 000000000..245301632 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2a2a2a24_x4.spi @@ -0,0 +1,56 @@ +* Spice description of oa2a2a2a24_x4 +* Spice driver version -1278698584 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:23 + +* INTERF i0 i1 i2 i3 i4 i5 i6 i7 q vdd vss + + +.subckt oa2a2a2a24_x4 9 11 10 12 3 2 4 5 1 13 18 +* NET 1 = q +* NET 2 = i5 +* NET 3 = i4 +* NET 4 = i6 +* NET 5 = i7 +* NET 9 = i0 +* NET 10 = i2 +* NET 11 = i1 +* NET 12 = i3 +* NET 13 = vdd +* NET 18 = vss +Mtr_00020 15 11 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00019 15 10 14 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00018 6 5 17 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00017 13 9 15 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00016 17 4 6 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00015 14 3 6 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00014 14 12 15 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00013 6 2 14 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00012 13 17 1 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 1 17 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 17 4 8 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00009 8 5 18 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00008 18 9 16 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00007 16 11 17 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00006 17 12 19 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00005 19 10 18 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00004 18 3 7 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00003 7 2 17 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.9U AS=0.261P AD=0.261P PS=2.38U PD=2.38U +Mtr_00002 18 17 1 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 1 17 18 18 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C19 1 18 1.22684e-15 +C18 2 18 7.91796e-16 +C17 3 18 8.16932e-16 +C16 4 18 7.91796e-16 +C15 5 18 7.91796e-16 +C14 6 18 1.03398e-15 +C11 9 18 9.2408e-16 +C10 10 18 7.35309e-16 +C9 11 18 1.00609e-15 +C8 12 18 7.91796e-16 +C7 13 18 4.65861e-15 +C6 14 18 5.62527e-16 +C5 15 18 1.20006e-15 +C3 17 18 3.28186e-15 +C2 18 18 4.73362e-15 +.ends oa2a2a2a24_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2ao222_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2ao222_x2.spi new file mode 100644 index 000000000..b679b9d75 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2ao222_x2.spi @@ -0,0 +1,41 @@ +* Spice description of oa2ao222_x2 +* Spice driver version 928517032 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:23 + +* INTERF i0 i1 i2 i3 i4 q vdd vss + + +.subckt oa2ao222_x2 8 5 7 1 6 4 3 13 +* NET 1 = i3 +* NET 3 = vdd +* NET 4 = q +* NET 5 = i1 +* NET 6 = i4 +* NET 7 = i2 +* NET 8 = i0 +* NET 13 = vss +Mtr_00012 4 12 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 9 7 12 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 2 1 9 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 3 8 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 3 5 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 12 6 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 13 12 4 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 10 1 13 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 11 8 13 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 13 7 10 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 10 6 12 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 12 5 11 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C13 1 13 8.17567e-16 +C12 2 13 1.36614e-15 +C11 3 13 2.85214e-15 +C10 4 13 1.22684e-15 +C9 5 13 1.05589e-15 +C8 6 13 8.68268e-16 +C7 7 13 9.00243e-16 +C6 8 13 1.02689e-15 +C4 10 13 8.83971e-16 +C2 12 13 2.37108e-15 +C1 13 13 2.76642e-15 +.ends oa2ao222_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2ao222_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2ao222_x4.spi new file mode 100644 index 000000000..0055edc65 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa2ao222_x4.spi @@ -0,0 +1,43 @@ +* Spice description of oa2ao222_x4 +* Spice driver version 1182886824 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:24 + +* INTERF i0 i1 i2 i3 i4 q vdd vss + + +.subckt oa2ao222_x4 8 5 7 1 6 4 3 13 +* NET 1 = i3 +* NET 3 = vdd +* NET 4 = q +* NET 5 = i1 +* NET 6 = i4 +* NET 7 = i2 +* NET 8 = i0 +* NET 13 = vss +Mtr_00014 4 12 3 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00013 3 12 4 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00012 9 7 12 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 2 1 9 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 3 8 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 3 5 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 12 6 2 3 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 4 12 13 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 13 12 4 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 10 1 13 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 11 8 13 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 13 7 10 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 10 6 12 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 12 5 11 13 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C13 1 13 8.17567e-16 +C12 2 13 1.36614e-15 +C11 3 13 3.8095e-15 +C10 4 13 1.22684e-15 +C9 5 13 1.05589e-15 +C8 6 13 8.68268e-16 +C7 7 13 9.00243e-16 +C6 8 13 1.02689e-15 +C4 10 13 8.83971e-16 +C2 12 13 2.75148e-15 +C1 13 13 3.39162e-15 +.ends oa2ao222_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa3ao322_x2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa3ao322_x2.spi new file mode 100644 index 000000000..179de7625 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa3ao322_x2.spi @@ -0,0 +1,49 @@ +* Spice description of oa3ao322_x2 +* Spice driver version 264706984 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:25 + +* INTERF i0 i1 i2 i3 i4 i5 i6 q vdd vss + + +.subckt oa3ao322_x2 11 10 9 1 4 3 2 16 12 17 +* NET 1 = i3 +* NET 2 = i6 +* NET 3 = i5 +* NET 4 = i4 +* NET 9 = i2 +* NET 10 = i1 +* NET 11 = i0 +* NET 12 = vdd +* NET 16 = q +* NET 17 = vss +Mtr_00016 16 15 12 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00015 5 3 7 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00014 5 4 6 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00013 12 11 7 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00012 7 10 12 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00011 12 9 7 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00010 7 2 15 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00009 6 1 15 12 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 17 15 16 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 15 9 13 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00006 8 4 17 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00005 13 10 14 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00004 14 11 17 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00003 17 1 8 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00002 8 2 15 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00001 17 3 8 17 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +C17 1 17 9.66594e-16 +C16 2 17 7.48234e-16 +C15 3 17 1.04475e-15 +C14 4 17 9.39915e-16 +C11 7 17 1.49471e-15 +C10 8 17 9.42902e-16 +C9 9 17 1.07273e-15 +C8 10 17 9.76258e-16 +C7 11 17 8.42431e-16 +C6 12 17 2.64694e-15 +C3 15 17 2.78895e-15 +C2 16 17 1.22684e-15 +C1 17 17 2.7273e-15 +.ends oa3ao322_x2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa3ao322_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa3ao322_x4.spi new file mode 100644 index 000000000..9e40591d0 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/oa3ao322_x4.spi @@ -0,0 +1,51 @@ +* Spice description of oa3ao322_x4 +* Spice driver version 1160420264 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:26 + +* INTERF i0 i1 i2 i3 i4 i5 i6 q vdd vss + + +.subckt oa3ao322_x4 10 12 9 3 4 1 2 17 13 16 +* NET 1 = i5 +* NET 2 = i6 +* NET 3 = i3 +* NET 4 = i4 +* NET 9 = i2 +* NET 10 = i0 +* NET 12 = i1 +* NET 13 = vdd +* NET 16 = vss +* NET 17 = q +Mtr_00018 5 2 11 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00017 7 3 11 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00016 6 4 7 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00015 13 10 5 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00014 5 12 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00013 13 9 5 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.5U AS=0.435P AD=0.435P PS=3.58U PD=3.58U +Mtr_00012 6 1 5 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 17 11 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00010 17 11 13 13 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 17 11 16 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 16 11 17 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 16 1 8 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00006 11 9 14 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00005 8 2 11 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00004 16 3 8 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00003 8 4 16 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00002 14 12 15 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00001 15 10 16 16 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +C17 1 16 1.04475e-15 +C16 2 16 7.48235e-16 +C15 3 16 9.66594e-16 +C14 4 16 9.39915e-16 +C13 5 16 1.49471e-15 +C10 8 16 9.42902e-16 +C9 9 16 1.07273e-15 +C8 10 16 8.6911e-16 +C7 11 16 3.73406e-15 +C6 12 16 9.76258e-16 +C5 13 16 2.89713e-15 +C2 16 16 3.33108e-15 +C1 17 16 8.94686e-16 +.ends oa3ao322_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/on12_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/on12_x1.spi new file mode 100644 index 000000000..8dd1872e7 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/on12_x1.spi @@ -0,0 +1,27 @@ +* Spice description of on12_x1 +* Spice driver version 670546856 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:26 + +* INTERF i0 i1 q vdd vss + + +.subckt on12_x1 2 3 6 1 7 +* NET 1 = vdd +* NET 2 = i0 +* NET 3 = i1 +* NET 6 = q +* NET 7 = vss +Mtr_00006 1 3 4 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00005 6 4 1 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00004 1 2 6 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 4 3 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00002 7 4 5 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 5 2 6 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C7 1 7 1.46192e-15 +C6 2 7 1.12143e-15 +C5 3 7 1.26303e-15 +C4 4 7 1.67413e-15 +C2 6 7 1.23756e-15 +C1 7 7 1.21548e-15 +.ends on12_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/on12_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/on12_x4.spi new file mode 100644 index 000000000..dfc5c8929 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/on12_x4.spi @@ -0,0 +1,32 @@ +* Spice description of on12_x4 +* Spice driver version -1533351000 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:27 + +* INTERF i0 i1 q vdd vss + + +.subckt on12_x4 1 4 7 5 8 +* NET 1 = i0 +* NET 4 = i1 +* NET 5 = vdd +* NET 7 = q +* NET 8 = vss +Mtr_00010 2 3 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 6 4 2 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 5 1 3 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00007 5 6 7 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00006 7 6 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00005 6 4 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 8 3 6 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00003 3 1 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00002 8 6 7 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 7 6 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C8 1 8 1.27591e-15 +C6 3 8 1.6097e-15 +C5 4 8 1.57438e-15 +C4 5 8 3.44842e-15 +C3 6 8 2.43977e-15 +C2 7 8 1.22684e-15 +C1 8 8 3.05197e-15 +.ends on12_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/one_x0.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/one_x0.spi new file mode 100644 index 000000000..5a0fc3ca0 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/one_x0.spi @@ -0,0 +1,17 @@ +* Spice description of one_x0 +* Spice driver version -1670992984 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:28 + +* INTERF q vdd vss + + +.subckt one_x0 2 1 3 +* NET 1 = vdd +* NET 2 = q +* NET 3 = vss +Mtr_00001 1 3 2 1 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C3 1 3 8.75833e-16 +C2 2 3 9.32188e-16 +C1 3 3 1.7476e-15 +.ends one_x0 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/rowend_x0.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/rowend_x0.spi new file mode 100644 index 000000000..f0542786c --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/rowend_x0.spi @@ -0,0 +1,14 @@ +* Spice description of rowend_x0 +* Spice driver version 518753192 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:34 + +* INTERF vdd vss + + +.subckt rowend_x0 1 2 +* NET 1 = vdd +* NET 2 = vss +C2 1 2 2.89745e-16 +C1 2 2 2.89745e-16 +.ends rowend_x0 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sff1_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sff1_x4.spi new file mode 100644 index 000000000..7c070324f --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sff1_x4.spi @@ -0,0 +1,58 @@ +* Spice description of sff1_x4 +* Spice driver version 1394092968 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:28 + +* INTERF ck i q vdd vss + + +.subckt sff1_x4 13 12 5 4 14 +* NET 4 = vdd +* NET 5 = q +* NET 9 = sff_m +* NET 10 = sff_s +* NET 11 = y +* NET 12 = i +* NET 13 = ck +* NET 14 = vss +* NET 15 = ckr +* NET 16 = nckr +* NET 17 = u +Mtr_00026 16 13 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00025 4 16 15 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00024 1 5 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00023 11 16 10 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00022 10 15 1 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00021 11 9 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00020 17 12 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00019 4 17 2 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00018 9 16 3 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00017 3 11 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00016 2 15 9 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00015 5 10 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00014 4 10 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00013 14 5 6 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00012 14 12 17 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00011 10 15 11 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00010 11 9 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00009 14 11 7 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00008 7 15 9 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00007 9 16 8 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00006 8 17 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00005 6 16 10 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 5 10 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 14 10 5 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 15 16 14 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 14 13 16 14 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C14 4 14 5.63579e-15 +C13 5 14 2.18618e-15 +C9 9 14 2.60658e-15 +C8 10 14 2.38529e-15 +C7 11 14 2.2951e-15 +C6 12 14 9.56437e-16 +C5 13 14 1.09551e-15 +C4 14 14 4.7411e-15 +C3 15 14 3.96798e-15 +C2 16 14 3.55443e-15 +C1 17 14 2.42413e-15 +.ends sff1_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sff2_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sff2_x4.spi new file mode 100644 index 000000000..587996935 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sff2_x4.spi @@ -0,0 +1,71 @@ +* Spice description of sff2_x4 +* Spice driver version 1964698536 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:29 + +* INTERF ck cmd i0 i1 q vdd vss + + +.subckt sff2_x4 14 19 18 15 7 6 22 +* NET 6 = vdd +* NET 7 = q +* NET 9 = sff_m +* NET 12 = sff_s +* NET 13 = y +* NET 14 = ck +* NET 15 = i1 +* NET 16 = nckr +* NET 17 = ckr +* NET 18 = i0 +* NET 19 = cmd +* NET 21 = u +* NET 22 = vss +Mtr_00034 21 24 4 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00033 4 15 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00032 6 18 5 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00031 24 19 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00030 5 19 21 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00029 6 12 7 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00028 6 21 2 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00027 9 16 3 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00026 3 13 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00025 2 17 9 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00024 7 12 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00023 13 16 12 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00022 12 17 1 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00021 13 9 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00020 16 14 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00019 6 16 17 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00018 1 7 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00017 20 19 21 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00016 22 15 20 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00015 21 24 23 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00014 23 18 22 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00013 22 19 24 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00012 11 21 22 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00011 8 16 12 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00010 7 12 22 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00009 22 12 7 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00008 22 14 16 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00007 17 16 22 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00006 22 7 8 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 12 17 13 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00004 13 9 22 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00003 22 13 10 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00002 10 17 9 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00001 9 16 11 22 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +C19 6 22 7.14761e-15 +C18 7 22 2.18618e-15 +C16 9 22 2.60658e-15 +C13 12 22 2.39854e-15 +C12 13 22 2.2951e-15 +C11 14 22 1.08172e-15 +C10 15 22 1.20041e-15 +C9 16 22 3.59755e-15 +C8 17 22 3.84562e-15 +C7 18 22 9.45644e-16 +C6 19 22 1.73907e-15 +C4 21 22 2.99952e-15 +C3 22 22 6.25292e-15 +C1 24 22 2.78554e-15 +.ends sff2_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sff3_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sff3_x4.spi new file mode 100644 index 000000000..9a0751897 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sff3_x4.spi @@ -0,0 +1,86 @@ +* Spice description of sff3_x4 +* Spice driver version 2127473576 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:30 + +* INTERF ck cmd0 cmd1 i0 i1 i2 q vdd vss + + +.subckt sff3_x4 16 18 24 17 22 23 8 25 30 +* NET 8 = q +* NET 9 = y +* NET 10 = sff_s +* NET 12 = ckr +* NET 13 = sff_m +* NET 16 = ck +* NET 17 = i0 +* NET 18 = cmd0 +* NET 19 = nckr +* NET 22 = i1 +* NET 23 = i2 +* NET 24 = cmd1 +* NET 25 = vdd +* NET 29 = u +* NET 30 = vss +Mtr_00042 9 13 25 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00041 10 12 1 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00040 7 27 29 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00039 29 17 4 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00038 6 23 5 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00037 5 22 7 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00036 25 18 20 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00035 9 19 10 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00034 3 9 25 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00033 13 19 3 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00032 25 10 8 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00031 8 10 25 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00030 29 24 6 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00029 25 29 2 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00028 2 12 13 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00027 25 20 5 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00026 4 18 25 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00025 25 16 19 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00024 12 19 25 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mtr_00023 27 24 25 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00022 1 8 25 25 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00021 11 19 10 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00020 15 29 30 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00019 13 19 15 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00018 30 9 14 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00017 26 22 31 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00016 28 23 26 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00015 30 19 12 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00014 21 20 30 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00013 30 24 27 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Mtr_00012 9 13 30 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00011 10 12 9 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00010 31 24 29 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00009 14 12 13 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00008 20 18 30 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Mtr_00007 29 17 21 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00006 30 18 26 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00005 30 16 19 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00004 29 27 28 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.54U AS=0.1566P AD=0.1566P PS=1.66U PD=1.66U +Mtr_00003 30 8 11 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00002 30 10 8 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00001 8 10 30 30 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C27 5 30 6.69675e-16 +C24 8 30 2.17433e-15 +C23 9 30 2.2951e-15 +C22 10 30 2.35568e-15 +C20 12 30 4.13912e-15 +C19 13 30 2.60658e-15 +C16 16 30 6.34009e-16 +C15 17 30 8.49567e-16 +C14 18 30 1.27501e-15 +C13 19 30 3.72606e-15 +C12 20 30 2.11295e-15 +C10 22 30 8.49096e-16 +C9 23 30 7.28271e-16 +C8 24 30 1.9238e-15 +C7 25 30 7.44814e-15 +C6 26 30 6.69675e-16 +C5 27 30 1.85648e-15 +C3 29 30 4.68986e-15 +C2 30 30 6.6606e-15 +.ends sff3_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sram2bw2r2.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sram2bw2r2.spi new file mode 100644 index 000000000..332fda483 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/sram2bw2r2.spi @@ -0,0 +1,234 @@ +* Spice description of sram2bw2r2 +* Spice driver version -186262616 +* Date ( dd/mm/yyyy hh:mm:ss ): 8/08/2024 at 10:57:57 + +* INTERF at0 at1 ax ay az0 az1 ck it iz nqx nqy vdd vss + + +.subckt sram2bw2r2 21 7 14 13 25 6 26 70 68 52 69 28 73 +* NET 1 = ctr_bn3 +* NET 2 = ctr_bn8 +* NET 3 = ctr_an8 +* NET 4 = ctr_an2 +* NET 5 = sff_bp2 +* NET 6 = az1 +* NET 7 = at1 +* NET 8 = sff_bp6 +* NET 9 = sff_bp9 +* NET 10 = sff_bp10 +* NET 11 = sff_bp12 +* NET 13 = ay +* NET 14 = ax +* NET 15 = sff_bp15 +* NET 16 = sff_ap16 +* NET 17 = sff_bp17 +* NET 18 = sff_ap14 +* NET 19 = sff_ap12 +* NET 20 = sff_ap11 +* NET 21 = at0 +* NET 22 = sff_ap5 +* NET 23 = sff_ap8 +* NET 24 = sff_ap7 +* NET 25 = az0 +* NET 26 = ck +* NET 27 = sff_ap1 +* NET 28 = vdd +* NET 29 = sff_bn2 +* NET 30 = sff_bn0 +* NET 31 = sff_nwz1 +* NET 32 = sff_bn3 +* NET 33 = sff_bp3 +* NET 34 = sff_bn5 +* NET 35 = sff_bn4 +* NET 37 = sff_nwd1 +* NET 38 = sff_nwt1 +* NET 39 = sff_bn9 +* NET 40 = sff_bn10 +* NET 41 = sff_bn12 +* NET 42 = sff_bn11 +* NET 43 = sff_bn13 +* NET 48 = sff_bn16 +* NET 49 = sff_an16 +* NET 51 = sff_bn17 +* NET 52 = nqx +* NET 53 = sff_nwd0 +* NET 54 = sff_nwt0 +* NET 56 = sff_wt0 +* NET 57 = sff_wd0 +* NET 59 = sff_an14 +* NET 62 = sff_nwz0 +* NET 63 = sff_wz0 +* NET 64 = sff_an5 +* NET 65 = sff_an7 +* NET 66 = sff_an8 +* NET 68 = iz +* NET 69 = nqy +* NET 70 = it +* NET 73 = vss +Msff_bp0 28 46 30 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_bp1 5 30 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_bp2 46 32 5 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_bp3 35 33 46 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_bp4 35 36 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_bp5 8 35 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_bp6 36 33 8 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_bp7 36 32 12 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_bp8 12 31 9 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_bp9 9 68 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_bp10 28 70 10 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_bp11 10 38 12 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_bp12 12 37 11 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_bp13 11 46 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_ap13 19 75 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_ap12 24 53 19 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_ap11 20 54 24 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_ap10 28 70 20 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_ap8 23 68 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_ap8_1 24 62 23 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_ap7 65 72 24 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_ap6 65 71 22 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_ap5 22 74 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_ap4 74 65 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_ap3 74 71 75 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_ap2 75 72 27 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_ap1 27 77 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Msff_ap0 28 75 77 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Msff_bp16 69 47 17 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Msff_bp17 17 75 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Msff_ap17 16 46 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Msff_ap16 52 58 16 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Msff_ap15 18 55 52 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Msff_ap14 28 75 18 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Msff_bp14 28 46 15 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Msff_bp15 15 48 69 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_bp11 28 48 47 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_bp10 48 13 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_ap11 58 14 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_ap10 28 58 55 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_ap9 57 53 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_ap7 53 54 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_ap8 28 62 53 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_ap5 28 21 54 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_ap6 56 54 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_ap3 28 54 62 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_ap2 62 25 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_ap4 63 62 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_bp5 28 7 38 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_bp6 40 38 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_bp2 31 6 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_bp3 28 38 31 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_bp4 39 31 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_bp8 28 31 37 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_bp9 41 37 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_bp7 37 38 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.74U AS=0.5046P AD=0.5046P PS=4.06U PD=4.06U +Mctr_bp0 28 33 32 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.1U AS=0.609P AD=0.609P PS=4.78U PD=4.78U +Mctr_bp1 33 26 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.1U AS=0.609P AD=0.609P PS=4.78U PD=4.78U +Mctr_ap1 71 26 28 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.1U AS=0.609P AD=0.609P PS=4.78U PD=4.78U +Mctr_ap0 28 71 72 28 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.1U AS=0.609P AD=0.609P PS=4.78U PD=4.78U +Msff_bn0 30 46 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_bn1 73 30 29 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_bn2 29 33 46 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_bn3 46 32 35 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_bn4 35 36 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_bn5 73 35 34 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_bn6 34 32 36 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_bn7 36 33 44 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_bn8 44 68 45 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_bn9 45 39 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_bn10 73 40 42 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_bn11 42 70 44 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_bn12 44 41 43 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_bn13 43 46 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_an13 61 75 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_an12 66 57 61 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_an11 60 70 66 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_an10 73 56 60 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_an9 67 63 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_an8 66 68 67 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_an7 65 71 66 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_an6 64 72 65 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_an5 73 74 64 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_an4 74 65 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_an3 75 72 74 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_an2 76 71 75 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_an1 73 77 76 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +Msff_an0 77 75 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Msff_an15 52 58 59 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Msff_an14 59 75 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Msff_bn14 50 46 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Msff_bn15 69 47 50 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Msff_bn16 51 48 69 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Msff_bn17 73 75 51 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Msff_an17 73 46 49 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Msff_an16 49 55 52 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.02U AS=0.2958P AD=0.2958P PS=2.62U PD=2.62U +Mctr_bn10 48 13 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_bn11 73 48 47 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_an11 58 14 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_an10 73 58 55 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_an7 3 54 53 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_an9 57 53 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_an8 73 62 3 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_an4 63 62 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_an3 73 54 4 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_an2 4 25 62 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_bn4 39 31 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_bn5 73 7 38 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_bn6 40 38 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_bn2 1 6 31 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_bn3 73 38 1 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_an6 56 54 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_an5 73 21 54 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_bn7 2 38 37 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_bn8 73 31 2 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_bn9 41 37 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mctr_bn0 73 33 32 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mctr_bn1 33 26 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mctr_an1 71 26 73 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mctr_an0 73 71 72 73 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +C72 6 73 1.43638e-15 +C71 7 73 1.35941e-15 +C66 12 73 9.80404e-16 +C65 13 73 1.62912e-15 +C64 14 73 1.23562e-15 +C57 21 73 1.46656e-15 +C54 24 73 9.80404e-16 +C53 25 73 1.43638e-15 +C52 26 73 5.59343e-15 +C50 28 73 3.16245e-14 +C48 30 73 2.08267e-15 +C47 31 73 5.76819e-15 +C46 32 73 5.0999e-15 +C45 33 73 5.19769e-15 +C43 35 73 1.7283e-15 +C42 36 73 2.40339e-15 +C41 37 73 4.01699e-15 +C40 38 73 4.23877e-15 +C39 39 73 3.07607e-15 +C38 40 73 2.8962e-15 +C37 41 73 3.39444e-15 +C34 44 73 9.80404e-16 +C32 46 73 7.49709e-15 +C31 47 73 3.66263e-15 +C30 48 73 4.33664e-15 +C26 52 73 5.6582e-15 +C25 53 73 3.94278e-15 +C24 54 73 4.23877e-15 +C23 55 73 3.42481e-15 +C22 56 73 2.8962e-15 +C21 57 73 3.39444e-15 +C20 58 73 4.0496e-15 +C16 62 73 5.70925e-15 +C15 63 73 3.07607e-15 +C13 65 73 2.42482e-15 +C12 66 73 9.80404e-16 +C10 68 73 5.86487e-15 +C9 69 73 5.6582e-15 +C8 70 73 5.86487e-15 +C7 71 73 5.2275e-15 +C6 72 73 5.0999e-15 +C5 73 73 3.87201e-14 +C4 74 73 1.7283e-15 +C3 75 73 7.95873e-15 +C1 77 73 2.08267e-15 +.ends sram2bw2r2 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/tie_x0.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/tie_x0.spi new file mode 100644 index 000000000..09f643f89 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/tie_x0.spi @@ -0,0 +1,14 @@ +* Spice description of tie_x0 +* Spice driver version 911571880 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:34 + +* INTERF vdd vss + + +.subckt tie_x0 1 2 +* NET 1 = vdd +* NET 2 = vss +C2 1 2 2.89745e-16 +C1 2 2 2.89745e-16 +.ends tie_x0 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ts_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ts_x4.spi new file mode 100644 index 000000000..0ede53d96 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ts_x4.spi @@ -0,0 +1,35 @@ +* Spice description of ts_x4 +* Spice driver version 1523010472 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:31 + +* INTERF cmd i q vdd vss + + +.subckt ts_x4 2 1 7 4 8 +* NET 1 = i +* NET 2 = cmd +* NET 4 = vdd +* NET 7 = q +* NET 8 = vss +Mtr_00012 5 2 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 3 5 6 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 4 3 7 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00009 7 3 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00008 4 2 3 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 3 1 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 8 5 6 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 3 2 6 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 7 6 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00003 8 6 7 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00002 5 2 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00001 6 1 8 8 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C8 1 8 1.08609e-15 +C7 2 8 2.51543e-15 +C6 3 8 2.43635e-15 +C5 4 8 3.07715e-15 +C4 5 8 1.97427e-15 +C3 6 8 2.15098e-15 +C2 7 8 1.22684e-15 +C1 8 8 2.74499e-15 +.ends ts_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ts_x8.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ts_x8.spi new file mode 100644 index 000000000..b05fb4ad2 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/ts_x8.spi @@ -0,0 +1,39 @@ +* Spice description of ts_x8 +* Spice driver version 2037853096 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:31 + +* INTERF cmd i q vdd vss + + +.subckt ts_x8 3 1 8 6 7 +* NET 1 = i +* NET 3 = cmd +* NET 6 = vdd +* NET 7 = vss +* NET 8 = q +Mtr_00016 6 4 8 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00015 8 4 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00014 8 4 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00013 4 2 5 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.38U AS=0.4002P AD=0.4002P PS=3.34U PD=3.34U +Mtr_00012 6 4 8 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00011 2 3 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 6 3 4 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.38U AS=0.4002P AD=0.4002P PS=3.34U PD=3.34U +Mtr_00009 4 1 6 6 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.38U AS=0.4002P AD=0.4002P PS=3.34U PD=3.34U +Mtr_00008 8 5 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00007 8 5 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 7 5 8 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 2 3 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 7 2 5 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00003 4 3 5 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00002 5 1 7 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.78U AS=0.2262P AD=0.2262P PS=2.14U PD=2.14U +Mtr_00001 7 5 8 7 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +C8 1 7 1.06032e-15 +C7 2 7 1.93239e-15 +C6 3 7 2.50082e-15 +C5 4 7 2.65331e-15 +C4 5 7 2.39371e-15 +C3 6 7 4.35272e-15 +C2 7 7 3.68841e-15 +C1 8 7 2.76978e-15 +.ends ts_x8 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/xr2_x1.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/xr2_x1.spi new file mode 100644 index 000000000..3c93d6513 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/xr2_x1.spi @@ -0,0 +1,35 @@ +* Spice description of xr2_x1 +* Spice driver version -1999471704 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:32 + +* INTERF i0 i1 q vdd vss + + +.subckt xr2_x1 1 2 7 4 9 +* NET 1 = i0 +* NET 2 = i1 +* NET 4 = vdd +* NET 7 = q +* NET 9 = vss +Mtr_00012 4 1 10 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 3 2 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00010 4 2 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00009 5 10 7 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00008 5 1 4 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00007 7 3 5 4 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00006 9 2 3 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00005 10 1 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00004 6 3 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00003 7 10 6 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00002 8 2 7 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00001 9 1 8 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +C10 1 9 1.21583e-15 +C9 2 9 1.81357e-15 +C8 3 9 2.14093e-15 +C7 4 9 2.14121e-15 +C6 5 9 1.40364e-15 +C4 7 9 1.66079e-15 +C2 9 9 2.14121e-15 +C1 10 9 1.57758e-15 +.ends xr2_x1 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/xr2_x4.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/xr2_x4.spi new file mode 100644 index 000000000..5b06bcc5d --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/xr2_x4.spi @@ -0,0 +1,40 @@ +* Spice description of xr2_x4 +* Spice driver version -816538712 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:33 + +* INTERF i0 i1 q vdd vss + + +.subckt xr2_x4 3 4 1 5 9 +* NET 1 = q +* NET 3 = i0 +* NET 4 = i1 +* NET 5 = vdd +* NET 9 = vss +Mtr_00016 1 7 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00015 5 7 1 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.46U AS=0.7134P AD=0.7134P PS=5.5U PD=5.5U +Mtr_00014 6 3 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00013 2 4 5 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00012 5 3 10 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00011 5 2 6 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00010 6 10 7 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00009 7 4 6 5 sky130_fd_pr__pfet_01v8__model L=0.15U W=2.34U AS=0.6786P AD=0.6786P PS=5.26U PD=5.26U +Mtr_00008 9 4 2 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +Mtr_00007 9 7 1 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00006 1 7 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.26U AS=0.3654P AD=0.3654P PS=3.1U PD=3.1U +Mtr_00005 11 4 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00004 7 10 11 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00003 8 2 7 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00002 9 3 8 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=1.14U AS=0.3306P AD=0.3306P PS=2.86U PD=2.86U +Mtr_00001 10 3 9 9 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.66U AS=0.1914P AD=0.1914P PS=1.9U PD=1.9U +C11 1 9 1.22684e-15 +C10 2 9 1.97158e-15 +C9 3 9 1.31112e-15 +C8 4 9 1.72126e-15 +C7 5 9 4.22576e-15 +C6 6 9 1.38221e-15 +C5 7 9 3.11621e-15 +C3 9 9 3.30965e-15 +C2 10 9 1.57758e-15 +.ends xr2_x4 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/zero_x0.spi b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/zero_x0.spi new file mode 100644 index 000000000..eb98b4d4c --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/spi/zero_x0.spi @@ -0,0 +1,17 @@ +* Spice description of zero_x0 +* Spice driver version -381326424 +* Date ( dd/mm/yyyy hh:mm:ss ): 1/08/2024 at 18:58:33 + +* INTERF nq vdd vss + + +.subckt zero_x0 2 1 3 +* NET 1 = vdd +* NET 2 = nq +* NET 3 = vss +Mtr_00001 2 1 3 3 sky130_fd_pr__nfet_01v8__model L=0.15U W=0.42U AS=0.1218P AD=0.1218P PS=1.42U PD=1.42U +C3 1 3 1.76813e-15 +C2 2 3 9.32188e-16 +C1 3 3 8.75833e-16 +.ends zero_x0 + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/sram2bw2r2/sram2bw2r2.cir b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/sram2bw2r2/sram2bw2r2.cir new file mode 100644 index 000000000..9c5218151 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/simul_spice/sram2bw2r2/sram2bw2r2.cir @@ -0,0 +1,62 @@ +******************************************************************************** +* sram2bw2r2.cir +* ngspice simulation +* lsxram +******************************************************************************** + +.option nopage nomod ++ newtol numdgt=7 ingold=2 gmindc=1e-18 +.option DOTNODE +.option MSGNODE = 0 + +******************************************************************************** +* BSIM4 transistor model parameters for ngspice and simulation conditions +******************************************************************************** + +.lib _TECHNO _MODEL +.TEMP _TEMP +Vground vss 0 0 +Vsupply vdd 0 DC _VDD +gfoncd vdd 0 vdd 0 1.0e-15 + +******************************************************************************** +* Circuit Instantiation with loading output +******************************************************************************** +.INCLUDE ../spi/sram2bw2r2.spi +*.subckt sram2bw2r2 at0 at1 ax ay az0 az1 ck it iz nqx nqy vdd vss + +Xa at0 at1 ax ay az0 az1 ck it iz nqx nqy vdd vss sram2bw2r2 +*Cload q vss 0.0020pF + +******************************************************************************** +* input stimluli and transient analysis +******************************************************************************** + +vck ck vss dc 0 pulse (0 _VDD 1000ps 30ps 30ps 970ps 2000ps) +vit it vss dc 0 pulse (0 _VDD 700ps 30ps 30ps 1970ps 4000ps) +viz iz vss dc 0 pulse (_VDD 0 700ps 30ps 30ps 1970ps 4000ps) + +vat0 at0 vss dc 0 +vaz0 az0 vss dc _VDD + +vat1 at1 vss dc 0 +vaz1 az1 vss dc 0 + +vax ax vss dc 0 +vay ay vss dc 0 + +.control +TRAN 1ps 8ns 0 + +set width=110 + +meas tran proptimeRF TRIG v(ck) val=0.9 RISE=1 TARG v(q) VAL=0.9 FALL=1 +meas tran proptimeFR TRIG v(ck) val=0.9 FALL=1 TARG v(q) VAL=0.9 RISE=1 + +gnuplot sram2bw2r2/sram2bw2r2._MODEL v(ck) v(it) v(iz) v(nqx) ++ title 'input and output of the sff1_x4' ++ xlabel 'time / s' ylabel 'Voltage / V' + +.endc + +.end diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/sky130_lsx.rds b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/sky130_lsx.rds new file mode 100644 index 000000000..fa7b5479e --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/sky130_lsx.rds @@ -0,0 +1,566 @@ +# 20230301 +# --------------------------------------------------------------------------- +# For SkyWater130 +# --------------------------------------------------------------------------- + + + + +# ------------------------------------------------------------------- +# globals define +# ------------------------------------------------------------------- + +define physical_grid 0.005 +define lambda 0.120 + +table cif_layer +# ------------------------------------------------------------------- +# rds_name cif_name +# ------------------------------------------------------------------- + rds_nwell nwel +# rds_pwell pwel + rds_activ active + rds_ntie nplus + rds_ptie pplus + rds_nimp nplus + rds_pimp pplus + rds_poly poly + rds_alu1 metal1 + rds_alu2 metal2 + rds_alu3 metal3 + rds_alu4 metal4 + rds_alu5 metal5 + rds_alu6 metal6 + rds_cont contact + rds_via1 via1 + rds_via2 via2 + rds_via3 via3 + rds_via4 via4 + rds_via5 via5 + rds_cpas pad +end + +table gds_layer +# ------------------------------------------------------------------- +# rds_name gds_number +# ------------------------------------------------------------------- + rds_nwell 3 +# rds_pwell 8 + rds_activ 6 + rds_ptie 25 + rds_ntie 26 + rds_pimp 25 + rds_nimp 26 + rds_poly 17 149 + rds_alu1 31 131 + rds_alu2 32 132 + rds_alu3 33 133 + rds_alu4 34 134 + rds_alu5 35 135 + rds_alu6 36 136 + rds_cont 30 + rds_via1 51 + rds_via2 52 + rds_via3 53 + rds_via4 54 + rds_via5 55 + rds_cpas 43 +end + +table lynx_resistor +# ------------------------------------------------------------------- +# rds_name square_resistor(ohm/square) # typical values +# ------------------------------------------------------------------- + rds_poly 48 + rds_alu1 13 + rds_alu2 0.125 + rds_alu3 0.125 + rds_alu4 0.047 + rds_alu5 0.047 + rds_alu6 0.029 + rds_cont 15 + rds_via1 152 + rds_via2 4.5 + rds_via3 3.4 + rds_via4 3.4 + rds_via5 0.38 +end + +table lynx_capa +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- + rds_poly 25.2e-6 51.8e-6 # Ca max POLY_NWELL 2Cf0 max POLY_NWELL + rds_alu1 2.6e-5 8.5e-5 # Ca max M1_NWELL 2Cf0 max M1_NWELL + rds_alu2 1.6e-5 7.9e-5 # Ca max M2_NWELL 2Cf0 max M2_NWELL + rds_alu3 8.0e-6 6.8e-5 # Ca max M3_NWELL 2Cf0 max M3_NWELL + rds_alu4 6.0e-6 6.0e-5 # Ca max M4_NWELL 2Cf0 max M4_NWELL + rds_alu5 6.0e-6 6.0e-5 # hyp + rds_alu6 6.0e-6 6.0e-5 +end + +table lynx_capa_poly +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_poly2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu1 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu3 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu4 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu5 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end +table mbk_to_rds_segment +# ---------------------------------------------------------------------------------- +# mbk_name rds_name1 dlr dwr offset mode rds_name2 dlr dwr offset mode +# ---------------------------------------------------------------------------------- + + nwell rds_nwell vw 0.420 0.360 .0 all\ + rds_pimp vw 0.185 0.250 .0 all + + pwell rds_pwell vw 0.420 0.360 .0 all\ + rds_nimp vw 0.185 0.250 .0 all + + ndif rds_activ vw 0.090 0.060 .0 all\ + rds_ndif vw 0.090 0.060 .0 ext + + pdif rds_activ vw 0.090 0.060 .0 all\ + rds_pdif vw 0.090 0.060 .0 ext + + ntie rds_activ vw 0.145 -0.070 .0 all\ + rds_ntie vw 0.270 0.180 .0 all\ + rds_nwell vw 0.420 0.530 .0 all + + ptie rds_activ vw 0.145 -0.070 .0 all\ + rds_ptie vw 0.270 0.180 .0 all\ + rds_pwell vw 0.420 0.530 .0 all + + ntrans rds_poly vw -0.015 0.030 .0 all\ + rds_activ vw -0.150 0.580 .0 drc\ + rds_ndif lcw -0.150 0.290 0.015 ext\ + rds_ndif rcw -0.150 0.290 0.015 ext + + ptrans rds_poly vw -0.015 0.030 .0 all\ + rds_activ vw -0.150 0.580 .0 drc\ + rds_pdif lcw -0.150 0.290 0.015 ext\ + rds_pdif rcw -0.150 0.290 0.015 ext + + poly rds_poly vw 0.075 0.030 .0 all + poly2 rds_poly vw 0.075 0.090 .0 all + + alu1 rds_alu1 vw 0.165 0.090 .0 all + calu1 rds_alu1 vw 0.165 0.090 .0 all + talu1 rds_talu1 vw 0.165 0.090 .0 all + + alu2 rds_alu2 vw 0.165 0.090 .0 all + calu2 rds_alu2 vw 0.165 0.090 .0 all + talu2 rds_talu2 vw 0.165 0.090 .0 all + + alu3 rds_alu3 vw 0.165 0.090 .0 all + calu3 rds_alu3 vw 0.165 0.090 .0 all + talu3 rds_talu3 vw 0.165 0.090 .0 all +end + +table mbk_to_rds_connector +# ------------------------------------------------------------------- +# mbk_name rds_name der dwr +# ------------------------------------------------------------------- +end + +table mbk_to_rds_reference +# ------------------------------------------------------------------- +# mbk_name rds_name width +# ------------------------------------------------------------------- + ref_ref rds_ref 0.330 + ref_con rds_ref 0.330 +end + +table mbk_to_rds_via +# ------------------------------------------------------------------- +# mbk_name rds_name1 width mode rds_name2 width mode ... +## ------------------------------------------------------------------ + cont_body_n \ + rds_cont 0.170 all\ + rds_alu1 0.330 all\ + rds_activ 0.290 drc\ + rds_ntie 0.290 ext + + cont_body_p \ + rds_cont 0.170 all\ + rds_alu1 0.330 all\ + rds_activ 0.290 drc\ + rds_ptie 0.290 ext + + cont_dif_n \ + rds_cont 0.170 all\ + rds_alu1 0.330 all\ + rds_activ 0.420 drc\ + rds_ndif 0.420 ext + + cont_dif_p \ + rds_cont 0.170 all\ + rds_alu1 0.330 all\ + rds_activ 0.420 drc\ + rds_pdif 0.420 ext + + cont_poly \ + rds_cont 0.170 all\ + rds_poly 0.330 all\ + rds_alu1 0.330 all + + cont_via \ + rds_via1 0.170 all\ + rds_alu1 0.330 all\ + rds_alu2 0.330 all + + cont_via2 \ + rds_via2 0.170 all\ + rds_alu2 0.330 all\ + rds_alu3 0.330 all +end + +table mbk_to_rds_bigvia_hole +# ------------------------------------------------------------------- +# mbk_via_name rds_hole_name side step mode +# ------------------------------------------------------------------- +end + +table mbk_to_rds_bigvia_metal +# ------------------------------------------------------------------- +# mbk_via_name rds_name dwr overlap mode +# ------------------------------------------------------------------- +end + +table mbk_to_rds_turnvia +# ------------------------------------------------------------------- +# mbk_name rds_name dwr mode +# ------------------------------------------------------------------- + cont_turn1 rds_alu1 0.090 all + cont_turn2 rds_alu2 0.090 all + cont_turn3 rds_alu3 0.090 all + cont_turn8 rds_poly 0.090 all +end + +table lynx_bulk_implicit +# ------------------------------------------------------------------- +# rds_name type[explicit|implicit] +# ------------------------------------------------------------------- +end + +table lynx_transistor +# ------------------------------------------------------------------- +# mbk_name trans_name compostion +# ------------------------------------------------------------------- + NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL + PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL +end + +table lynx_diffusion +# ------------------------------------------------------------------- +# rds_name compostion +# ------------------------------------------------------------------- + rds_ndif rds_activ 1 rds_nimp 1 rds_nwell 0 + rds_pdif rds_activ 1 rds_pimp 1 rds_nwell 1 + rds_ntie rds_activ 1 rds_nimp 1 rds_nwell 1 + rds_ptie rds_activ 1 rds_pimp 1 rds_nwell 0 +end + +table lynx_graph +# ------------------------------------------------------------------- +# rds_name in_contact_with rds_name1 rds_name2 ... +# ------------------------------------------------------------------- + rds_ndif rds_cont rds_ndif + rds_pdif rds_cont rds_pdif + rds_poly rds_cont rds_poly2 rds_poly + rds_poly2 rds_cont rds_poly rds_poly2 + rds_cont rds_pdif rds_ndif rds_poly rds_poly2 rds_alu1 rds_cont + rds_via1 rds_alu1 rds_alu2 rds_via1 + rds_via2 rds_alu2 rds_alu3 rds_via2 + rds_alu1 rds_cont rds_via1 rds_ref rds_alu1 + rds_ref rds_cont rds_via1 rds_alu1 rds_ref + rds_alu2 rds_via1 rds_via2 rds_alu2 + rds_alu3 rds_via2 rds_alu3 +end + +table s2r_oversize_denotch +# ------------------------------------------------------------------- +# rds_name oversized_value_for_denotching +# ------------------------------------------------------------------- + rds_nwell 0.635 + rds_pwell 0.635 + rds_poly 0.100 + rds_alu1 0.080 + rds_alu2 0.080 + rds_alu3 0.080 + rds_activ 0.130 + rds_ntie 0.190 + rds_ptie 0.190 + rds_nimp 0.190 + rds_pimp 0.190 +end + +table s2r_bloc_ring_width +# ------------------------------------------------------------------- +# rds_name ring_width_to_copy_up +# ------------------------------------------------------------------- + rds_nwell 0. # [ RD_NWEL ] + rds_pwell 0. # [ RD_PWEL ] + rds_poly 0. # [ RD_POLY ] + rds_alu1 0. # [ RD_ALU1 ] + rds_alu2 0. # [ RD_ALU2 ] + rds_alu3 0. # [ RD_ALU3 ] + rds_activ 0. # [ RD_ACTI ] + rds_ntie 0. # [ RD_NIMP ] + rds_ptie 0. # [ RD_PIMP ] + rds_nimp 0. # [ RD_NIMP ] + rds_pimp 0. # [ RD_PIMP ] +end + +table s2r_minimum_layer_width +# ------------------------------------------------------------------- +# rds_name min_layer_width_to_keep +# ------------------------------------------------------------------- + rds_nwell 0.840 + rds_pwell 0.840 + rds_poly 0.150 + rds_alu1 0.330 + rds_alu2 0.330 + rds_alu3 0.330 + rds_activ 0.420 + rds_ntie 0.380 + rds_ptie 0.380 + rds_nimp 0.380 + rds_pimp 0.380 +end + +table s2r_post_treat +# ------------------------------------------------------------------- +# rds_name s2r_must_treat_or_not second_layer_whenever_scotch +# ------------------------------------------------------------------- + rds_nwell treat null + rds_pwell treat null + rds_poly treat null + rds_activ treat null + rds_ntie treat rds_pimp + rds_ptie treat rds_nimp + rds_nimp treat rds_ptie + rds_pimp treat rds_ntie + rds_alu1 treat null + rds_alu2 treat null + rds_alu3 treat null + rds_cont notreat null +end + +DRC_RULES + +layer RDS_NWELL 0.840 ; +layer RDS_NTIE 0.380 ; +layer RDS_PTIE 0.380 ; +layer RDS_NIMP 0.380 ; +layer RDS_PIMP 0.380 ; +layer RDS_ACTIV 0.420 ; +layer RDS_CONT 0.170 ; +layer RDS_POLY 0.150 ; +layer RDS_ALU1 0.170 ; +layer RDS_ALU2 0.170 ; +layer RDS_ALU3 0.170 ; +layer RDS_USER0 0.005 ; +layer RDS_USER1 0.005 ; +layer RDS_USER2 0.005 ; + +regles + +# note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# there is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# ---------------------------------------------------------- + +# check the nwell shapes +# ---------------------- +caracterise RDS_NWELL ( + regle 1 : largeur >= 0.840 ; + regle 2 : longueur_inter min 0.840 ; + regle 3 : notch >= 1.270 ; +); +relation RDS_NWELL , RDS_NWELL ( + regle 4 : distance axiale min 1.270 ; +); +relation RDS_NWELL , RDS_ACTI ( + regle 5 : distance axiale min 0.340 ; +); + +# check the RDS_PIMP shapes +# ------------------------- +caracterise RDS_PIMP ( + regle 6 : surface min 0.255 ; + regle 7 : largeur >= 0.380 ; + regle 8 : longueur_inter min 0.380 ; + regle 9 : notch >= 0.380 ; +); +relation RDS_PIMP , RDS_PIMP ( + regle 10 : distance axiale min 0.380 ; +); + +# check the RDS_NIMP shapes +# ------------------------- +caracterise RDS_NIMP ( + regle 11 : surface min 0.265 ; + regle 12 : largeur >= 0.380 ; + regle 13 : longueur_inter min 0.380 ; + regle 14 : notch >= 0.380 ; +); +relation RDS_NIMP , RDS_NIMP ( + regle 15 : distance axiale min 0.380 ; +); + +# check the RDS_PTIE shapes +# ------------------------- +caracterise RDS_PTIE ( + regle 16 : surface min 0.255 ; + regle 17 : largeur >= 0.380 ; + regle 18 : longueur_inter min 0.380 ; + regle 19 : notch >= 0.380 ; +); +relation RDS_PTIE , RDS_PTIE ( + regle 20 : distance axiale min 0.380 ; +); + +# check the RDS_NTIE shapes +# ------------------------- +caracterise RDS_NTIE ( + regle 21 : surface min 0.265 ; + regle 22 : largeur >= 0.380 ; + regle 23 : longueur_inter min 0.380 ; + regle 24 : notch >= 0.380 ; +); +relation RDS_NTIE , RDS_NTIE ( + regle 25 : distance axiale min 0.380 ; +); + +# check the RDS_ACTI shapes +# ------------------------- +caracterise RDS_ACTI ( + regle 26 : surface min 0.000 ; + regle 27 : largeur >= 0.420 ; + regle 28 : longueur_inter min 0.420 ; + regle 29 : notch >= 0.270 ; +); +relation RDS_ACTI, RDS_ACTI ( + regle 30 : distance axiale min 0.270 ; +); + +# check the RDS_NIMP RDS_PTIE exclusion +# ------------------------------------- +define RDS_NIMP , RDS_PTIE intersection -> NPIMP; +caracterise NPIMP ( + regle 31 : largeur = 0. ; +); +undefine NPIMP; + +# check the RDS_NTIE RDS_PIMP exclusion +# ------------------------------------- +define RDS_NTIE , RDS_PIMP intersection -> NPIMP; +caracterise NPIMP ( + regle 32 : largeur = 0. ; +); +undefine NPIMP; + +# check the RDS_POLY shapes +# ------------------------- +caracterise RDS_POLY ( + regle 33 : largeur >= 0.150 ; + regle 34 : longueur_inter min 0.150 ; + regle 35 : notch >= 0.210 ; +); +relation RDS_POLY , RDS_POLY ( + regle 36 : distance axiale min 0.210 ; +); + +define RDS_ACTI , RDS_POLY intersection -> channel; + + # check the channel shapes + # ------------------------- + caracterise channel ( + regle 37 : notch >= 0.210 ; + ); + relation channel , channel ( + regle 38 : distance axiale min 0.210 ; + ); + +undefine channel; + +define RDS_ACTI , RDS_CONT intersection -> cont_diff; + + relation RDS_POLY , cont_diff ( + regle 39 : distance axiale >= 0.055 ; + ); + +undefine cont_diff; + +# check RDS_ALU1 shapes +# --------------------- +caracterise RDS_ALU1 ( + regle 40 : surface min 0.060 ; + regle 41 : largeur >= 0.170 ; + regle 42 : longueur_inter min 0.170 ; + regle 43 : notch >= 0.170 ; +); +relation RDS_ALU1 , RDS_ALU1 ( + regle 44 : distance axiale min 0.170 ; +); + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_CONT , RDS_CONT ( + regle 45 : distance axiale >= 0.170 ; +); + +caracterise RDS_CONT ( + regle 46 : largeur = 0.170 ; + regle 47 : longueur = 0.170 ; +); + +# check RDS_POLY is distant from activ zone of transistor +# ------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + regle 48 : distance axiale >= 0.075 ; +); + +fin regles +DRC_COMMENT +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/spimodel.cfg b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/spimodel.cfg new file mode 100644 index 000000000..c58ef6c96 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/spimodel.cfg @@ -0,0 +1,5 @@ +# MBK_SPI_MODEL +# configure the transistor models of spi parser/driver +# +sky130_fd_pr__nfet_01v8__model N +sky130_fd_pr__pfet_01v8__model P diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/symbolic.graal b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/symbolic.graal new file mode 100644 index 000000000..101446888 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/symbolic.graal @@ -0,0 +1,387 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Graal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 27/06/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Graal Peek Bound in lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_PEEK_BOUND 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_FIGURE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_INSTANCE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_CONNECTOR_STEP 5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_SEGMENT_STEP 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_REFERENCE_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | Segment Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_NAME + + NWELL Nwell tan Black + PWELL Pwell light_yellow Black + NDIF Ndif lawn_green Black + PDIF Pdif yellow Black + NTIE Ntie spring_green Black + PTIE Ptie light_goldenrod Black + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 GReen Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + TPOLY Tpoly hot_pink Black + TALU1 Talu1 royal_blue Black + TALU2 Talu2 turquoise Black + TALU3 Talu3 light_pink Black + TALU4 Talu4 green Black + TALU5 Talu5 yellow Black + TALU6 Talu6 violet Black + TALU7 Talu7 red Black + TALU8 Talu8 blue Black + CALU1 CAlu1 royal_blue Black + CALU2 CAlu2 Cyan Black + CALU3 CAlu3 light_pink Black + CALU4 CAlu4 green Black + CALU5 CAlu5 yellow Black + CALU6 CAlu6 violet Black + CALU7 CAlu7 red Black + CALU8 CAlu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Transistor Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_TRANSISTOR_NAME + + NTRANS Ntrans lawn_green Black + PTRANS Ptrans yellow Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Connector Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_CONNECTOR_NAME + + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 green Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Length and Width for a symbolic Segment | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_VALUE + + NWELL 4 4 + PWELL 4 4 + NDIF 3 2 # LSX 2 -> 3 + PDIF 3 2 # LSX 2 -> 3 + NTIE 3 1 # LSX 2 -> 3 + PTIE 3 1 # LSX 2 -> 3 + NTRANS 1 5 # LSX 4 -> 5 + PTRANS 1 5 # LSX 4 -> 5 + POLY 1 1 + POLY2 2 1 # LSX 1 -> 2 + ALU1 2 1 # LSX 1 -> 2 + ALU2 2 1 + ALU3 2 1 + ALU4 2 1 + ALU5 2 1 + ALU6 2 1 + ALU7 2 1 + ALU8 2 1 + TPOLY 1 1 + TALU1 2 1 # LSX 1 -> 2 + TALU2 2 1 # LSX 2 -> 1 + TALU3 2 1 # LSX 2 -> 1 + TALU4 2 1 # LSX 2 -> 1 + TALU5 2 1 # LSX 2 -> 1 + TALU6 2 1 # LSX 2 -> 1 + TALU7 2 1 # LSX 2 -> 1 + TALU8 2 1 # LSX 2 -> 1 + CALU1 2 0 + CALU2 2 0 + CALU3 2 0 + CALU4 2 0 + CALU5 2 0 + CALU6 2 0 + CALU7 2 0 + CALU8 2 0 + +END + +# /*------------------------------------------------------------\ +# | | +# | Reference Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_REFERENCE_NAME + + REF_REF Ref_Ref red Black + REF_CON Ref_Con Cyan Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_VIA_NAME + + CONT_DIF_N Cont_NDif lawn_green Black + CONT_DIF_P Cont_PDif yellow Black + CONT_BODY_N Cont_NTie spring_green Black + CONT_BODY_P Cont_PTie light_goldenrod Black + CONT_POLY Cont_Poly red Black + CONT_POLY2 Cont_Poly2 orange Black + CONT_VIA Via_1-2 cyan Black + CONT_VIA2 Via_2-3 light_pink Black + CONT_VIA3 Via_3-4 green Black + CONT_VIA4 Via_4-5 yellow Black + CONT_VIA5 Via_5-6 violet Black + CONT_VIA6 Via_6-7 red Black + CONT_VIA7 Via_7-8 blue Black + C_X_N Cont_CxN orange Black + C_X_P Cont_CxP orange Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Big Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_NAME + + CONT_VIA Big_Via_1-2 cyan Black + CONT_VIA2 Big_Via_2-3 light_pink Black + CONT_VIA3 Big_Via_3-4 green Black + CONT_VIA4 Big_Via_4-5 yellow Black + CONT_VIA5 Big_Via_5-6 violet Black + CONT_VIA6 Big_Via_6-7 red Black + CONT_VIA7 Big_Via_7-8 blue Black + + CONT_TURN1 Turn_Via_0 red Black + CONT_TURN1 Turn_Via_1 royal_blue Black + CONT_TURN2 Turn_Via_2 Cyan Black + CONT_TURN3 Turn_Via_3 light_pink Black + CONT_TURN4 Turn_Via_4 green Black + CONT_TURN5 Turn_Via_5 yellow Black + CONT_TURN6 Turn_Via_6 violet Black + CONT_TURN7 Turn_Via_7 blue Black + CONT_TURN8 Turn_Via_8 red Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Size for a symbolic Big Via | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_VALUE + + CONT_VIA 2 + CONT_VIA2 2 + CONT_VIA3 2 + CONT_VIA4 2 + CONT_VIA5 2 + CONT_VIA6 2 + CONT_VIA7 2 + + CONT_TURN1 2 + CONT_TURN2 2 + CONT_TURN3 2 + CONT_TURN4 2 + CONT_TURN5 2 + CONT_TURN6 2 + CONT_TURN7 2 + CONT_TURN8 2 + +END + +# /*------------------------------------------------------------\ +# | | +# | Orient Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_ORIENT_NAME + + NORTH North lawn_green Black + SOUTH South yellow Black + EAST East tan Black + WEST West red Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Symmetry Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SYMMETRY_NAME + + NOSYM No_Sym LightBlue Black + SYM_X Sym_X turquoise Black + SYM_Y Sym_Y cyan Black + SYMXY Sym_XY lightCyan Black + ROT_P Rot_P MediumAquamarine Black + ROT_M Rot_M aquamarine Black + SY_RP Sym_RP green Black + SY_RM Sym_RM MediumSpringGreen Black + +END + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/symbolic.rds b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/symbolic.rds new file mode 100644 index 000000000..f840a7e4d --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/symbolic.rds @@ -0,0 +1,953 @@ +#===================================================================== +# +# ALLIANCE VLSI CAD +# (R)eal (D)ata (S)tructure parameter file +# (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI +# all rights reserved +# e-mail : cao-vlsi@masi.ibp.fr +# +# file : cmos.rds +# version : 12 +# last modif : Apr 4, 2002, Feb 24, 2023 +# +##------------------------------------------------------------------- +# Symbolic to micron on a 'one lambda equals one micron' basis +##------------------------------------------------------------------- +# Refer to the documentation for more precise information. +#===================================================================== +# 1/05/23 +# . no more CXN and CXP +# +# 01/11/09 ALU5/6 pitch 10 +# +# 99/11/3 ALU5/6 rules +# . theses rules are preliminary rules, we hope that they wil change +# in future. For now, ALU5/6 are dedicated to supplies an clock. +# +# 99/3/22 new symbolics rules +# . ALU1 width remains 1, ALU2/3/4 is 2 +# . ALU1/2/3/4 distance (edge to edge) is now 3 for all +# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2 +# . All via stacking are allowed +# +# 98/12/1 drc rules were updated +# distance VIA to POLY or gate is one rather 2 +# VIA2 and ALU3 appeared +# . ALU3 width is 3 +# . ALU2/VIA2/ALU3 is resp. 3/1/3 +# . ALU3 edge distance is 2 +# . stacked VIA/VIA2 is allowed +# . if they are not stacked they must distant of 2 +# . CONT/VIA2 is free +# note +# . stacked CONT/VIA is always not allowed +# NWELL is automatically drawn with the DIFN and NTIE layers +#===================================================================== + +##------------------------------------------------------------------- +# PHYSICAL_GRID : +##------------------------------------------------------------------- + +DEFINE PHYSICAL_GRID .5 + +##------------------------------------------------------------------- +# LAMBDA : +##------------------------------------------------------------------- + +DEFINE LAMBDA 1 + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_SEGMENT : +# +# MBK RDS layer 1 RDS layer 2 +# name name TRANS DLR DWR OFFSET name TRANS DLR DWR OFFSET ... +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_SEGMENT + + PWELL RDS_PWELL VW 2.0 0.0 0.0 EXT + NWELL RDS_NWELL VW 2.0 0.0 0.0 ALL + NDIF RDS_NDIF VW 0.5 0.0 0.0 ALL + PDIF RDS_PDIF VW 0.5 0.0 0.0 ALL + NTIE RDS_NTIE VW 1.5 0.0 0.0 ALL\ + RDS_NWELL VW 2.0 5.0 0.0 ALL + PTIE RDS_PTIE VW 1.5 0.0 0.0 ALL\ + RDS_PWELL VW 2.0 5.0 0.0 ALL # LSX DLR 0.5 -> 1.5 + NTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \ + RDS_NDIF LCW -1.5 2.5 0.0 EXT \ + RDS_NDIF RCW -1.5 2.5 0.0 EXT \ + RDS_NDIF VW -1.5 6.0 0.0 DRC \ + RDS_ACTIV VW -1.5 6.0 0.0 ALL + PTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \ + RDS_PDIF LCW -1.5 2.5 0.0 EXT \ + RDS_PDIF RCW -1.5 2.5 0.0 EXT \ + RDS_PDIF VW -1.5 6.0 0.0 DRC \ + RDS_ACTIV VW -1.5 6.0 0.0 ALL + POLY RDS_POLY VW 0.5 0.0 0.0 ALL + POLY2 RDS_POLY2 VW 0.5 0.0 0.0 ALL + ALU1 RDS_ALU1 VW 1.0 0.0 0.0 ALL # LSX DLR 0.5 -> 1.0 + ALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL + ALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL + ALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL + ALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL + ALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL + CALU1 RDS_ALU1 VW 1.0 0.0 0.0 ALL + CALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL + CALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL + CALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL + CALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL + CALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL + TPOLY RDS_TPOLY VW 0.5 0.0 0.0 ALL + TALU1 RDS_TALU1 VW 1.0 0.0 0.0 ALL # SX DLR 0.5 -> 1.0 + TALU2 RDS_TALU2 VW 1.0 0.0 0.0 ALL + TALU3 RDS_TALU3 VW 1.0 0.0 0.0 ALL + TALU4 RDS_TALU4 VW 1.0 0.0 0.0 ALL + TALU5 RDS_TALU5 VW 1.0 0.0 0.0 ALL + TALU6 RDS_TALU6 VW 1.0 0.0 0.0 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_CONNECTOR : +# +# MBK RDS layer +# name name DER DWR +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_CONNECTOR + + POLY RDS_POLY .5 0 + POLY2 RDS_POLY2 .5 0 + ALU1 RDS_ALU1 1.0 0 # LSX DER 0.5 -> 1.0 + ALU2 RDS_ALU2 1.0 0 + ALU3 RDS_ALU3 1.0 0 + ALU4 RDS_ALU4 1.0 0 + ALU5 RDS_ALU5 1.0 0 + ALU6 RDS_ALU6 1.0 0 + CALU1 RDS_ALU1 1.0 0 # LSX DER 0.5 -> 1.0 + CALU2 RDS_ALU2 1.0 0 + CALU3 RDS_ALU3 1.0 0 + CALU4 RDS_ALU4 1.0 0 + CALU5 RDS_ALU5 1.0 0 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_REFERENCE : +# +# MBK ref RDS layer +# name name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_REFERENCE + + REF_REF RDS_REF 1 + REF_CON RDS_VALU1 2 RDS_TVIA1 1 RDS_TALU2 2 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_VIA1 : +# +# MBK via RDS layer 1 RDS layer 2 RDS layer 3 RDS layer 4 +# name name width name width name width name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_VIA + + CONT_BODY_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PTIE 3 ALL + CONT_BODY_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NTIE 3 ALL + CONT_DIF_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NDIF 3 ALL + CONT_DIF_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PDIF 3 ALL + CONT_POLY RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY 2 ALL # LSX POLY=3 -> POLY=2 + CONT_POLY2 RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY2 2 ALL # LSX POLY2=3 -> POLY2=2 + CONT_VIA RDS_ALU1 2 ALL RDS_VIA1 1 ALL RDS_ALU2 2 ALL + CONT_VIA2 RDS_ALU2 2 ALL RDS_VIA2 1 ALL RDS_ALU3 2 ALL + CONT_VIA3 RDS_ALU3 2 ALL RDS_VIA3 1 ALL RDS_ALU4 2 ALL + CONT_VIA4 RDS_ALU4 2 ALL RDS_VIA4 1 ALL RDS_ALU5 2 ALL + CONT_VIA5 RDS_ALU5 2 ALL RDS_VIA5 1 ALL RDS_ALU6 2 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_HOLE : +# +# MBK via RDS Hole +# name name side step mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_HOLE + +CONT_VIA RDS_VIA1 1 4 ALL +CONT_VIA2 RDS_VIA2 1 4 ALL +CONT_VIA3 RDS_VIA3 1 4 ALL +CONT_VIA4 RDS_VIA4 1 4 ALL # should be more than 4 +CONT_VIA5 RDS_VIA5 1 4 ALL # should be more than 4 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_METAL : +# +# MBK via RDS layer 1 ... +# name name delta-width overlap mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_METAL + +CONT_VIA RDS_ALU1 0.0 0.5 ALL RDS_ALU2 0.0 0.5 ALL +CONT_VIA2 RDS_ALU2 0.0 0.5 ALL RDS_ALU3 0.0 0.5 ALL +CONT_VIA3 RDS_ALU3 0.0 0.5 ALL RDS_ALU4 0.0 0.5 ALL +CONT_VIA4 RDS_ALU4 0.0 0.5 ALL RDS_ALU5 0.0 0.5 ALL +CONT_VIA5 RDS_ALU5 0.0 0.5 ALL RDS_ALU6 0.0 0.5 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_TURNVIA : +# +# MBK via RDS layer 1 ... +# name name DWR MODE +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_TURNVIA + +CONT_TURN1 RDS_ALU1 0 ALL +CONT_TURN2 RDS_ALU2 0 ALL +CONT_TURN3 RDS_ALU3 0 ALL +CONT_TURN4 RDS_ALU4 0 ALL +CONT_TURN5 RDS_ALU5 0 ALL +CONT_TURN6 RDS_ALU6 0 ALL +CONT_TURN7 RDS_ALU7 0 ALL +CONT_TURN8 RDS_POLY 0 ALL + +END + + +##------------------------------------------------------------------- +# TABLE LYNX_GRAPH : +# +# RDS layer Rds layer 1 Rds layer 2 ... +# name name name ... +##------------------------------------------------------------------- + +TABLE LYNX_GRAPH + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# RDS_NWELL RDS_NTIE RDS_NWELL +# RDS_PWELL RDS_PTIE RDS_PWELL +# RDS_NDIF RDS_CONT RDS_NDIF +# RDS_PDIF RDS_CONT RDS_PDIF +# RDS_NTIE RDS_CONT RDS_NTIE RDS_NWELL +# RDS_PTIE RDS_CONT RDS_PTIE RDS_PWELL + + RDS_NDIF RDS_CONT RDS_NDIF + RDS_PDIF RDS_CONT RDS_PDIF + RDS_NTIE RDS_CONT RDS_NTIE + RDS_PTIE RDS_CONT RDS_PTIE + + RDS_POLY RDS_CONT RDS_POLY2 RDS_POLY + RDS_POLY2 RDS_CONT RDS_POLY RDS_POLY2 + RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_POLY2 RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT + RDS_ALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1 + RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 + RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 + RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 + RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 + RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 + RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 + RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2 + RDS_ALU3 RDS_VIA2 RDS_VIA3 RDS_ALU3 + RDS_ALU4 RDS_VIA3 RDS_VIA4 RDS_ALU4 + RDS_ALU5 RDS_VIA4 RDS_VIA5 RDS_ALU5 + RDS_ALU6 RDS_VIA5 RDS_ALU6 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_CAPA : +# +# RDS layer Surface capacitance Perimetric capacitance +# name piF / Micron^2 piF / Micron +##------------------------------------------------------------------- + +TABLE LYNX_CAPA + + RDS_POLY 1.00e-04 1.00e-04 + RDS_POLY2 1.00e-04 1.00e-04 + RDS_ALU1 0.50e-04 0.90e-04 + RDS_ALU2 0.25e-04 0.95e-04 + RDS_ALU3 0.25e-04 0.95e-04 + RDS_ALU4 0.25e-04 0.95e-04 + RDS_ALU5 0.25e-04 0.95e-04 + RDS_ALU6 0.25e-04 0.95e-04 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_RESISTOR : +# +# RDS layer Surface resistor +# name Ohm / Micron^2 +##------------------------------------------------------------------- + +TABLE LYNX_RESISTOR + + RDS_POLY 50.0 + RDS_POLY2 50.0 + RDS_ALU1 12.0 # LSX .1 -> 12 + RDS_ALU2 0.05 + RDS_ALU3 0.05 + RDS_ALU4 0.05 + RDS_ALU5 0.05 + RDS_ALU6 0.05 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_TRANSISTOR : +# +# MBK layer Transistor Type MBK via +# name name name +##------------------------------------------------------------------- + +TABLE LYNX_TRANSISTOR + + NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL + PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL + +END + +##------------------------------------------------------------------- +# TABLE LYNX_DIFFUSION : +# +# RDS layer RDS layer +# name name +##------------------------------------------------------------------- + +TABLE LYNX_DIFFUSION +END + +##------------------------------------------------------------------- +# TABLE LYNX_BULK_IMPLICIT : +# +# RDS layer Bulk type +# name EXPLICIT/IMPLICIT +##------------------------------------------------------------------- + +TABLE LYNX_BULK_IMPLICIT + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# NWELL EXPLICIT +# PWELL IMPLICIT + +END + + + +##------------------------------------------------------------------- +# TABLE S2R_OVERSIZE_DENOTCH : +##------------------------------------------------------------------- + +TABLE S2R_OVERSIZE_DENOTCH +END + +##------------------------------------------------------------------- +# TABLE S2R_BLOC_RING_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_BLOC_RING_WIDTH +END + +##------------------------------------------------------------------- +# TABLE S2R_MINIMUM_LAYER_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_MINIMUM_LAYER_WIDTH + + RDS_NWELL 4 + RDS_NDIF 3 # LSX 2 -> 3 + RDS_PDIF 3 # LSX 2 -> 3 + RDS_NTIE 3 # LSX 2 -> 3 + RDS_PTIE 3 # LSX 2 -> 3 + RDS_POLY 1 + RDS_POLY2 2 # LSX POLY2 used to fill potential notch (same width of CONT_POLY) + RDS_TPOLY 1 + RDS_CONT 1 + RDS_ALU1 2 # LSX 1 -> 2 + RDS_TALU1 2 # LSX 1 -> 2 + RDS_VIA1 1 + RDS_ALU2 2 + RDS_TALU2 2 + RDS_VIA2 1 + RDS_ALU3 2 + RDS_TALU3 2 + RDS_VIA3 1 + RDS_ALU4 2 + RDS_TALU4 2 + RDS_VIA4 1 + RDS_ALU5 2 + RDS_TALU5 2 + RDS_VIA5 1 + RDS_ALU6 2 + RDS_TALU6 2 + +END + +##------------------------------------------------------------------- +# TABLE MBK_WIRESETTING : +##------------------------------------------------------------------- +# +# This table is used by ocp, nero & ring. It supplies *symbolic* +# information about the routing grid, the cell gauge and the power +# wires. + + +TABLE MBK_WIRESETTING + + X_GRID 5 + Y_GRID 5 + Y_SLICE 50 + WIDTH_VDD 4 # LSX 6 -> 4 + WIDTH_VSS 4 # LSX 6 -> 4 + TRACK_WIDTH_ALU8 0 + TRACK_WIDTH_ALU7 2 + TRACK_WIDTH_ALU6 2 + TRACK_WIDTH_ALU5 2 + TRACK_WIDTH_ALU4 2 + TRACK_WIDTH_ALU3 2 + TRACK_WIDTH_ALU2 2 + TRACK_WIDTH_ALU1 2 + TRACK_SPACING_ALU8 0 + TRACK_SPACING_ALU7 8 + TRACK_SPACING_ALU6 8 + TRACK_SPACING_ALU5 3 + TRACK_SPACING_ALU4 3 + TRACK_SPACING_ALU3 3 + TRACK_SPACING_ALU2 3 + TRACK_SPACING_ALU1 3 + +END + + +##------------------------------------------------------------------- +# TABLE CIF_LAYER : +##------------------------------------------------------------------- + +TABLE CIF_LAYER + + RDS_NWELL LNWELL + RDS_NDIF LNDIF + RDS_PDIF LPDIF + RDS_NTIE LNTIE + RDS_PTIE LPTIE + RDS_POLY LPOLY + RDS_POLY2 LPOLY # LSX poly2 is here poly + RDS_TPOLY LTPOLY + RDS_CONT LCONT + RDS_ALU1 LALU1 + RDS_VALU1 LVALU1 + RDS_TALU1 LTALU1 + RDS_VIA1 LVIA + RDS_TVIA1 LTVIA1 + RDS_ALU2 LALU2 + RDS_TALU2 LTALU2 + RDS_VIA2 LVIA2 + RDS_ALU3 LALU3 + RDS_TALU3 LTALU3 + RDS_VIA3 LVIA3 + RDS_ALU4 LALU4 + RDS_TALU4 LTALU4 + RDS_VIA4 LVIA4 + RDS_ALU5 LALU5 + RDS_TALU5 LTALU5 + RDS_VIA5 LVIA5 + RDS_ALU6 LALU6 + RDS_TALU6 LTALU6 + RDS_REF LREF + +END + +##------------------------------------------------------------------- +# TABLE GDS_LAYER : +##------------------------------------------------------------------- + +TABLE GDS_LAYER + + RDS_NWELL 1 + RDS_NDIF 3 + RDS_PDIF 4 + RDS_NTIE 5 + RDS_PTIE 6 + RDS_POLY 7 + RDS_POLY2 7 # LSX poly2 is here poly + RDS_TPOLY 9 + RDS_CONT 10 + RDS_ALU1 11 11 + RDS_VALU1 12 + RDS_TALU1 13 + RDS_VIA1 14 + RDS_TVIA1 15 + RDS_ALU2 16 16 + RDS_TALU2 17 + RDS_VIA2 18 + RDS_ALU3 19 19 + RDS_TALU3 20 + RDS_VIA3 21 + RDS_ALU4 22 22 + RDS_TALU4 23 + RDS_VIA4 25 + RDS_ALU5 26 26 + RDS_TALU5 27 + RDS_VIA5 28 + RDS_ALU6 29 29 + RDS_TALU6 30 + RDS_REF 24 + +END + +##------------------------------------------------------------------- +# TABLE S2R_POST_TREAT : +##------------------------------------------------------------------- + +TABLE S2R_POST_TREAT + +END +DRC_RULES + +layer RDS_NWELL 4.; +layer RDS_NTIE 3.; # LSX 2 -> 3 +layer RDS_PTIE 3.; # LSX 2 -> 3 +layer RDS_NDIF 3.; # LSX 2 -> 3 +layer RDS_PDIF 3.; # LSX 2 -> 3 +layer RDS_ACTIV 2.; +layer RDS_CONT 1.; +layer RDS_VIA1 1.; +layer RDS_VIA2 1.; +layer RDS_VIA3 1.; +layer RDS_VIA4 1.; +layer RDS_VIA5 1.; +layer RDS_POLY 1.; +layer RDS_POLY2 2.; # LSX 1 -> 2 +layer RDS_ALU1 2.; # LSX 1 -> 2 +layer RDS_ALU2 2.; +layer RDS_ALU3 2.; +layer RDS_ALU4 2.; +layer RDS_ALU5 2.; +layer RDS_ALU6 2.; +layer RDS_USER0 1.; +layer RDS_USER1 1.; +layer RDS_USER2 1.; + +regles + +# Note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# There is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# There is no rule to check NTIE and PDIF are included in NWELL +# since this is necessarily true +#----------------------------------------------------------- + +# Check the NWELL shapes +#----------------------- +caracterise RDS_NWELL ( + regle 1 : largeur >= 4. ; + regle 2 : longueur_inter min 4. ; + regle 3 : notch >= 12. ; +); +relation RDS_NWELL , RDS_NWELL ( + regle 4 : distance axiale min 12. ; +); + +# Check RDS_PTIE is really excluded outside NWELL +#------------------------------------------------ +relation RDS_PTIE , RDS_NWELL ( + regle 5 : distance axiale >= 7.5; + regle 6 : enveloppe longueur_inter < 0. ; + regle 7 : marge longueur_inter < 0. ; + regle 8 : croix longueur_inter < 0. ; + regle 9 : intersection longueur_inter < 0. ; + regle 10 : extension longueur_inter < 0. ; + regle 11 : inclusion longueur_inter < 0. ; +); + +# Check RDS_NDIF is really excluded outside NWELL +#------------------------------------------------ +relation RDS_NDIF , RDS_NWELL ( + regle 12 : distance axiale >= 7.5; + regle 13 : enveloppe longueur_inter < 0. ; + regle 14 : marge longueur_inter < 0. ; + regle 15 : croix longueur_inter < 0. ; + regle 16 : intersection longueur_inter < 0. ; + regle 17 : extension longueur_inter < 0. ; + regle 18 : inclusion longueur_inter < 0. ; +); + +# Check the RDS_PDIF shapes +#-------------------------- +caracterise RDS_PDIF ( + regle 19 : largeur >= 3. ; # LSX 2 -> 3 + regle 20 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 21 : notch >= 3. ; +); +relation RDS_PDIF , RDS_PDIF ( + regle 22 : distance axiale min 3. ; +); + +# Check the RDS_NDIF shapes +#-------------------------- +caracterise RDS_NDIF ( + regle 23 : largeur >= 3. ; # LSX 2 -> 3 + regle 24 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 25 : notch >= 3. ; +); +relation RDS_NDIF , RDS_NDIF ( + regle 26 : distance axiale min 3. ; +); + +# Check the RDS_PTIE shapes +#-------------------------- +caracterise RDS_PTIE ( + regle 27 : largeur >= 3. ; # LSX 2 -> 3 + regle 28 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 29 : notch >= 3. ; +); +relation RDS_PTIE , RDS_PTIE ( + regle 30 : distance axiale min 3. ; +); + +# Check the RDS_NTIE shapes +#-------------------------- +caracterise RDS_NTIE ( + regle 31 : largeur >= 3. ; # LSX 2 -> 3 + regle 32 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 33 : notch >= 3. ; +); +relation RDS_NTIE , RDS_NTIE ( + regle 34 : distance axiale min 3. ; +); + +define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF; +define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF; + +# Check the ANY_N_DIF ANY_P_DIFF exclusion +#-------------------------------------- +relation ANY_N_DIF , ANY_P_DIF ( + regle 35 : distance axiale >= 3. ; + regle 36 : enveloppe longueur_inter < 0. ; + regle 37 : marge longueur_inter < 0. ; + regle 38 : croix longueur_inter < 0. ; + regle 39 : intersection longueur_inter < 0. ; + regle 40 : extension longueur_inter < 0. ; + regle 41 : inclusion longueur_inter < 0. ; +); + +undefine ANY_P_DIF; +undefine ANY_N_DIF; + +define RDS_NDIF , RDS_PDIF union -> NP_DIF; + +# Check RDS_POLY related to NP_DIF +#--------------------------------- +relation RDS_POLY , NP_DIF ( + regle 42 : distance axiale >= 1. ; + regle 43 : intersection longueur_inter < 0. ; +); + +define NP_DIF , RDS_POLY intersection -> CHANNEL; + +# Check the RDS_POLY shapes +#-------------------------- +caracterise RDS_POLY ( + regle 44 : largeur >= 1. ; + regle 45 : longueur_inter min 1. ; + regle 46 : notch >= 2.5 ; # LSX 2 -> 2.5 +); +relation RDS_POLY , RDS_POLY ( + regle 47 : distance axiale min 2.5; # LSX 2 -> 2.5 +); + +define NP_DIF , RDS_CONT intersection -> CONT_DIFF; +# Check the CHANNEL shapes +#-------------------------- +caracterise CHANNEL ( + regle 48 : notch >= 3. ; +); +relation CHANNEL , CHANNEL ( + regle 49 : distance axiale min 3.; +); + +undefine CHANNEL; + +# Check RDS_POLY is distant from ACTIV ZONE of TRANSISTOR +#-------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + regle 79 : distance axiale >= 1. ; +); + +relation RDS_POLY , CONT_DIFF ( + regle 50 : distance axiale >= 2. ; +); + +undefine CONT_DIFF; +undefine NP_DIF; + + +# Check RDS_ALU1 shapes +#---------------------- +caracterise RDS_ALU1 ( + regle 51 : largeur >= 2. ; # LSX 1 -> 2 + regle 52 : longueur_inter min 2. ; # LSX 1 -> 2 + regle 53 : notch >= 3. ; +); +relation RDS_ALU1 , RDS_ALU1 ( + regle 54 : distance axiale min 3. ; +); + +# Check RDS_ALU2 shapes +#---------------------- +caracterise RDS_ALU2 ( + regle 55 : largeur >= 2. ; + regle 56 : longueur_inter min 2. ; + regle 57 : notch >= 3. ; +); +relation RDS_ALU2 , RDS_ALU2 ( + regle 58 : distance axiale min 3. ; +); + +# Check RDS_ALU3 shapes +#---------------------- +caracterise RDS_ALU3 ( + regle 59 : largeur >= 2. ; + regle 60 : longueur_inter min 2. ; + regle 61 : notch >= 3. ; +); +relation RDS_ALU3 , RDS_ALU3 ( + regle 62 : distance axiale min 3. ; +); + +# Check RDS_ALU4 shapes +#---------------------- +caracterise RDS_ALU4 ( + regle 63 : largeur >= 2. ; + regle 64 : longueur_inter min 2. ; + regle 65 : notch >= 3. ; +); +relation RDS_ALU4 , RDS_ALU4 ( + regle 66 : distance axiale min 3. ; +); + +# Check RDS_ALU5 shapes +#---------------------- +caracterise RDS_ALU5 ( + regle 80 : largeur >= 2. ; + regle 81 : longueur_inter min 2. ; + regle 82 : notch >= 3. ; +); +relation RDS_ALU5 , RDS_ALU5 ( + regle 83 : distance axiale min 3. ; +); + +# Check RDS_ALU6 shapes +#---------------------- +caracterise RDS_ALU6 ( + regle 84 : largeur >= 2. ; + regle 85 : longueur_inter min 2. ; + regle 86 : notch >= 3. ; +); +relation RDS_ALU6 , RDS_ALU6 ( + regle 87 : distance axiale min 3. ; +); + +# Check ANY_VIA layers, stacking are free +#---------------------------------------- +relation RDS_CONT , RDS_CONT ( + regle 67 : distance axiale >= 3. ; +); +relation RDS_VIA , RDS_VIA ( + regle 68 : distance axiale >= 4. ; +); +relation RDS_VIA2 , RDS_VIA2 ( + regle 69 : distance axiale >= 4. ; +); +relation RDS_VIA3 , RDS_VIA3 ( + regle 70 : distance axiale >= 4. ; +); +relation RDS_VIA4 , RDS_VIA4 ( + regle 88 : distance axiale >= 4. ; +); +relation RDS_VIA5 , RDS_VIA5 ( + regle 89 : distance axiale >= 4. ; +); +caracterise RDS_CONT ( + regle 71 : largeur >= 1. ; + regle 72 : longueur <= 1. ; +); +caracterise RDS_VIA ( + regle 73 : largeur >= 1. ; + regle 74 : longueur <= 1. ; +); +caracterise RDS_VIA2 ( + regle 75 : largeur >= 1. ; + regle 76 : longueur <= 1. ; +); +caracterise RDS_VIA3 ( + regle 77 : largeur >= 1. ; + regle 78 : longueur <= 1. ; +); +caracterise RDS_VIA4 ( + regle 90 : largeur >= 1. ; + regle 91 : longueur <= 1. ; +); +caracterise RDS_VIA5 ( + regle 92 : largeur >= 1. ; + regle 93 : longueur <= 1. ; +); + + +# Check the POLY2 shapes +#----------------------- +caracterise RDS_POLY2 ( + regle 94 : largeur >= 2. ; # LSX 1 -> 2 + regle 95 : longueur_inter min 2. ; + regle 96 : notch >= 2.5 ; # LSX 5 -> 2.5 +); +relation RDS_POLY2 , RDS_POLY2 ( + regle 97 : distance axiale min 2.5 ; # LSX 5 -> 2.5 +); + +# LSX : These rules are meaningless since POLY2 is POLY here +# +# Check RDS_POLY2 is really included inside RDS_POLY1 +#---------------------------------------------------- +#relation RDS_POLY , RDS_POLY2 ( +# regle 98 : distance axiale < 0.; +# regle 99 : enveloppe inferieure min 5. ; +# regle 100 : marge longueur_inter < 0. ; +# regle 101 : croix longueur_inter < 0. ; +# regle 102 : intersection longueur_inter < 0. ; +# regle 103 : extension longueur_inter < 0. ; +# regle 104 : inclusion longueur_inter < 0. ; +#); + + +fin regles +DRC_COMMENT +1 (RDS_NWELL) minimum width 4. +2 (RDS_NWELL) minimum width 4. +3 (RDS_NWELL) Manhatan distance min 12. +4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12. +5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5 +6 (RDS_PTIE,RDS_NWELL) must never been in contact +7 (RDS_PTIE,RDS_NWELL) must never been in contact +8 (RDS_PTIE,RDS_NWELL) must never been in contact +9 (RDS_PTIE,RDS_NWELL) must never been in contact +10 (RDS_PTIE,RDS_NWELL) must never been in contact +11 (RDS_PTIE,RDS_NWELL) must never been in contact +12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5 +13 (RDS_NDIF,RDS_NWELL) must never been in contact +14 (RDS_NDIF,RDS_NWELL) must never been in contact +15 (RDS_NDIF,RDS_NWELL) must never been in contact +16 (RDS_NDIF,RDS_NWELL) must never been in contact +17 (RDS_NDIF,RDS_NWELL) must never been in contact +18 (RDS_NDIF,RDS_NWELL) must never been in contact +19 (RDS_PDIF) minimum width 3. # LSX 2 -> 3 +20 (RDS_PDIF) minimum width 3. # LSX 2 -> 3 +21 (RDS_PDIF) Manhatan distance min 3. +22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3. +23 (RDS_NDIF) minimum width 3. # LSX 2 -> 3 +24 (RDS_NDIF) minimum width 3. # LSX 2 -> 3 +25 (RDS_NDIF) Manhatan distance min 3. +26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3. +27 (RDS_PTIE) minimum width 3. # LSX 2 -> 3 +28 (RDS_PTIE) minimum width 3. # LSX 2 -> 3 +29 (RDS_PTIE) Manhatan distance min 3. +30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3. +31 (RDS_NTIE) minimum width 3. # LSX 2 -> 3 +32 (RDS_NTIE) minimum width 3. # LSX 2 -> 3 +33 (RDS_NTIE) Manhatan distance min 3. +34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3. +35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3. +36 (ANY_N_DIF,ANY_P_DIF) must never been in contact +37 (ANY_N_DIF,ANY_P_DIF) must never been in contact +38 (ANY_N_DIF,ANY_P_DIF) must never been in contact +39 (ANY_N_DIF,ANY_P_DIF) must never been in contact +40 (ANY_N_DIF,ANY_P_DIF) must never been in contact +41 (ANY_N_DIF,ANY_P_DIF) must never been in contact +42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1. +43 (RDS_POLY,NP_DIF) bad intersection +44 (RDS_POLY) minimum width 1. +45 (RDS_POLY) minimum width 1. +46 (RDS_POLY) Manhatan distance min 2. +47 (RDS_POLY,RDS_POLY) Manhatan distance min 2. +48 (CHANNEL) Manhatan distance min 3. +49 (CHANNEL,CHANNEL) Manhatan distance min 3. +50 (RDS_POLY,CONT_DIFF) Manhatan distance min 2. +51 (RDS_ALU1) minimum width 2. # LSX 1 -> 2 +52 (RDS_ALU1) minimum width 2. # LSX 1 -> 2 +53 (RDS_ALU1) Manhatan distance min 3. +54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 3. +55 (RDS_ALU2) minimum width 2. +56 (RDS_ALU2) minimum width 2. +57 (RDS_ALU2) Manhatan distance min 3. +58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 3. +59 (RDS_ALU3) minimum width 2. +60 (RDS_ALU3) minimum width 2. +61 (RDS_ALU3) Manhatan distance min 3. +62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3. +63 (RDS_ALU4) minimum width 2. +64 (RDS_ALU4) minimum width 2. +65 (RDS_ALU4) Manhatan distance min 3. +66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3. +67 (RDS_CONT,RDS_CONT) Manhatan distance min 3. +68 (RDS_VIA,RDS_VIA) Manhatan distance min 4. +69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 4. +70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 4. +71 (RDS_CONT) minimum width 1. +72 (RDS_CONT) maximum length 1. +73 (RDS_VIA) minimum width 1. +74 (RDS_VIA) maximum length 1. +75 (RDS_VIA2) minimum width 1. +76 (RDS_VIA2) maximum length 1. +77 (RDS_VIA3) minimum width 1. +78 (RDS_VIA3) maximum length 1. +79 (RDS_POLY,RDS_ACTIV) Manhatan distance min 1. +80 (RDS_ALU5) minimum width 2. +81 (RDS_ALU5) minimum width 2. +82 (RDS_ALU5) Manhatan distance min 4. +83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 4. +84 (RDS_ALU6) minimum width 2. +85 (RDS_ALU6) minimum width 2. +86 (RDS_ALU6) Manhatan distance min 4. +87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 4. +88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 4. +89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 4. +90 (RDS_VIA4) minimum width 1. +91 (RDS_VIA4) maximum length 1. +92 (RDS_VIA5) minimum width 1. +93 (RDS_VIA5) maximum length 1. +94 (RDS_POLY2) minimum width 2. +95 (RDS_POLY2) minimum width 1. +96 (RDS_POLY2) Manhatan distance min 2.5 +97 (RDS_POLY2,POLY2) Manhatan distance min 2.5 +98 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +99 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +100 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +101 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +102 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +103 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +104 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/techno.py b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/techno.py new file mode 100644 index 000000000..ae42bd38a --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/techno.py @@ -0,0 +1,663 @@ + +from coriolis import CRL, Hurricane, Viewer, Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, BasicLayer, \ + RegularLayer, Cell, Net, Horizontal, Vertical, Rectilinear, \ + Box, Point, NetExternalComponents +from coriolis.technos.common.colors import toRGB +from coriolis.technos.common.patterns import toHexa +from coriolis.helpers import u +from coriolis.helpers.technology import createBL, createVia +from coriolis.helpers.overlay import CfgCache +from coriolis.helpers.analogtechno import Length, Area, Unit, Asymmetric, loadAnalogTechno, addDevice +from coriolis.designflow.task import ShellEnv + + +__all__ = [ "setup" ] + + +""" +Coriolis Design Technological Rules (DTR) for SkyWater 130nm CMOS General Purpose +================================================================================= + +:Version: rev.LIP6-1 +:Date: December 21, 2022 +:Date: February 2, 2023 +:Date: April 20, 2023 +:Authors: Marie-Minerve Louerat + +Reference documents: + https://skywater-pdk.readthedocs.io/en/main/rules/masks.html + https://skywater-pdk.readthedosc.io/en/main/rules/periphery.html#x + +Beware of the existence of li1 local interconnect using licon to connect to +difftap or to poly and mcon ton connect to metal1 + +Beware that some rules are context dependent (via spacing at end of line or at +one side, wide metal3) + +Beware different description exist of MIM capacitors +here met2, capm, met3 and via2 connects met2/capm to met3 + +===================== ======= ========== ==================================== +SkyWater130 mask Acronym Layer name Coriolis original +purpose for rule layer name +===================== ======= ========== ==================================== +N-Well NWM nwm nwell +Low Vt Nch LVTNM lvtn +active diffusion difftap active +Poly 1 P1M poly poly +P+ Implant PSDM psdm pImplant +N+ Implant NSDM nsdm nImplant +Local Intr Cont. 1 LICM1 licon cut0 contact between difftap and li1, + poly and li1 +Local Intrcnct 1 LI1M li metal metal between poly and metal1 + for local interconnect +Contact CTM1 mcon cut1 contact between li1 and metal1 +Metal 1 MM1 m1 metal1 +Via VIM via cut2 +Metal 2 MM2 m2 metal2 +Via 2-PLM VIM2 via2 cut3 +Metal 3-PLM MM3 m3 metal3 +Via 2-PLM VIM3 via3 cut4 +Metal 4 MM4 m4 metal4 +Via 4 VIM4 via4 cut5 +Metal 5 MM5 m5 metal5 + +capm CAPM capm metcap +Metal 2 MM2 bottom_plate metbot +===================== ======= ============ ==================================== + +""" + + +analogTechnologyTable = \ + ( ('Header', 'Sky130', DbU.UnitPowerMicro, 'rev.LIP6-1') + # ------------------------------------------------------------------------------------ + # ( Rule name , [Layer1] , [Layer2] , Value , Rule flags , Reference ) + , ('physicalGrid' , 0.005 , Length , 'GSF') + , ('transistorMinL' , 0.15 , Length , 'poly.1 and device details') + #, ('transistorMinL' , 0.38 , Length , 'lvtn.1a') + , ('transistorMaxL' , 38 , Length , 'rule0002') + , ('transistorMinW' , 0.42 , Length , 'difftap.2') + #, ('transistorMinW' , 0.36 , Length , 'difftap.2b') + , ('transistorMaxW' , 4000 , Length , 'rule0004') + + # N-WELL (nwm) + , ('minWidth' , 'nwm' , 0.84 , Length , 'nwell.1') + , ('minSpacing' , 'nwm' , 1.27 , Length , 'nwell.2a') + , ('minArea' , 'nwm' , 0 , Area , 'N/A') + + # LVTN (lvtn) + , ('minWidth' , 'lvtn' , 0.38 , Length , 'lvtn.1a') + , ('minSpacing' , 'lvtn' , 0.38 , Length , 'lvtn.2') + , ('minArea' , 'lvtn' , 0.265 , Area , 'lvtn.13') + , ('minEnclosure' , 'nwm' , 'lvtn' , 0.38 , Length|Asymmetric, 'lvtn.10') + + # DIFF (difftap) + , ('minWidth' , 'difftap' , 0.15 , Length , 'difftap.1') + , ('minSpacing' , 'difftap' , 0.27 , Length , 'difftap.3') + , ('minArea' , 'difftap' , 0 , Area , 'N/A') + , ('minEnclosure' , 'nwm' , 'difftap' , 0.18 , Length|Asymmetric, 'difftap.10') + + # Poly1 (poly) + , ('minWidth' , 'poly' , 0.15 , Length , 'poly.1a') + , ('minSpacing' , 'poly' , 0.21 , Length , 'poly.2') + , ('minGateSpacing' , 'poly' , 0.21 , Length , 'poly.2') + , ('minArea' , 'poly' , 0 , Area , 'N/A') + , ('minSpacing' , 'poly' , 'difftap' , 0.075 , Length , 'poly.4') + , ('minExtension' , 'poly' , 'difftap' , 0.130 , Length|Asymmetric, 'poly.8') + , ('minGateExtension' , 'difftap' , 'poly' , 0.25 , Length|Asymmetric, 'poly.7') + , ('minExtension' , 'difftap' , 'poly' , 0.25 , Length|Asymmetric, 'poly.7') + + # 4.1.6 PPLUS (psdm) + , ('minWidth' , 'psdm' , 0.38 , Length , 'psd.1') + , ('minSpacing' , 'psdm' , 0.38 , Length , 'psd.2') + , ('minArea' , 'psdm' , 0.255 , Area , 'psd.10b') + , ('minSpacing' , 'psdm' , 'difftap' , 0.130 , Length , 'psd.7') + , ('minGateExtension' , 'psdm' , 'poly' , 0.00 , Length|Asymmetric, 'N/A') + , ('minOverlap' , 'psdm' , 'difftap' , 0.00 , Length , 'N/A') + , ('minEnclosure' , 'psdm' , 'difftap' , 0.125 , Length|Asymmetric, 'psd.5a') + , ('minStrapEnclosure' , 'psdm' , 'difftap' , 0.125 , Length , 'psd.5b') + , ('minSpacing' , 'nsdm' , 'psdm' , 0.00 , Length , 'N/A') + , ('minEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minLengthEnclosure', 'psdm' , 'difftap' , 0 , Length|Asymmetric, 'N/A') + , ('minWidthEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'psdm' , 'difftap' , 0.125 , Length|Asymmetric, 'dup. psd.5a') + , ('minStrapEnclosure' , 'psdm' , 0.125 , Length , 'dup. psd.5b') + + # NPLUS (nsdm) + , ('minWidth' , 'nsdm' , 0.38 , Length , 'nsd.1') + , ('minSpacing' , 'nsdm' , 0.38 , Length , 'nsd.2') + , ('minArea' , 'nsdm' , 0.265 , Area , 'nsd.10a') + , ('minSpacing' , 'nsdm' , 'difftap' , 0.130 , Length , 'nsd.7') + , ('minGateExtension' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minOverlap' , 'nsdm' , 'difftap' , 0 , Length , 'N/A') + , ('minEnclosure' , 'nsdm' , 'difftap' , 0.125 , Length|Asymmetric, 'nsd.5a') + , ('minStrapEnclosure' , 'nsdm' , 'difftap' , 0.125 , Length , 'nsd.5b') + , ('minEnclosure' , 'nsdm' , 'nwm' , 0 , Length|Asymmetric, 'N/A') + , ('minEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minLengthEnclosure', 'nsdm' , 'difftap' , 0 , Length|Asymmetric, 'N/A') + , ('minWidthEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minGateEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'nsdm' , 'difftap' , 0.125 , Length|Asymmetric, 'dup. nsd.5a') + , ('minStrapEnclosure' , 'nsdm' , 0.215 , Length , 'dup. nsd.5b') + + # LICM1 (licon) + , ('minWidth' , 'licon' , 0.17 , Length , 'licon.1') + , ('minSpacing' , 'licon' , 0.17 , Length , 'licon.2') + , ('minGateSpacing' , 'licon' , 'poly' , 0.25 , Length|Asymmetric, 'licon.10') + , ('minSpacing' , 'licon' , 'poly' , 0.25 , Length|Asymmetric, 'licon.10') + , ('minSpacing' , 'licon' , 'difftap' , 0.19 , Length , 'licon.14') + #, ('minSpacing' , 'licon' , 'difftap' , 0.06 , Length , 'licon.5b') + , ('minEnclosure' , 'difftap' , 'licon' , 0.04 , Length|Asymmetric, 'licon.5a and licon.7 : 0.12 isolated tap') + , ('minEnclosure' , 'poly' , 'licon' , 0.05 , Length|Asymmetric, 'licon.8 and licon.8a : 0.08') + , ('minEnclosure' , 'psdm' , 'licon' , 0 , Length|Asymmetric, 'N/A') + , ('minEnclosure' , 'nsdm' , 'licon' , 0 , Length|Asymmetric, 'N/A') + , ('minGateEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'poly' , 'licon' , 0.05 , Length|Asymmetric, 'dup. licon.8 and licon.8a') + , ('minExtension' , 'psdm' , 'licon' , 0.25 , Length|Asymmetric, 'dup.') + , ('minExtension' , 'nsdm' , 'licon' , 0.25 , Length|Asymmetric, 'dup.') + + # LI1M (li) + , ('minWidth' , 'li' , 0.17 , Length , 'li.1') + , ('minSpacing' , 'li' , 0.17 , Length , 'li.3') + , ('minArea' , 'li' , 0.0561, Area , 'li.6') + , ('minEnclosure' , 'li' , 'licon' , 0.08 , Length|Asymmetric, 'li.5') + , ('minEnclosure' , 'li' , 'mcon' , 0.00 , Length|Asymmetric, 'ct.4') + + # CTM1 (mcon) + , ('minWidth' , 'mcon' , 0.17 , Length , 'ct.1') + , ('minSpacing' , 'mcon' , 0.19 , Length , 'ct.2') + + + # MM1 (m1) + , ('minWidth' , 'm1' , 0.14 , Length , 'm1.1') + , ('minSpacing' , 'm1' , 0.14 , Length , 'm1.2') + , ('minArea' , 'm1' , 0.083 , Area , 'm1.6') + , ('minEnclosure' , 'm1' , 'mcon' , 0.03 , Length|Asymmetric, 'm1.4 and m1.5 : 0.06 one side') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm1' , 'mcon' , 0.03 , Length|Asymmetric, 'm1.4 and m1.5') + + # VIM (via) + , ('minWidth' , 'via' , 0.15 , Length , 'via.1a') + , ('minSpacing' , 'via' , 0.17 , Length , 'via.2') + , ('minEnclosure' , 'm1' , 'via' , 0.55 , Length|Asymmetric, 'via.4a and via.5a : 0.085 on one side') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'm1' , 'via' , 0.55 , Length|Asymmetric, 'dup. via.a4 and via.5a : 0.085 on one side') + + # MM2 (m2) + , ('minWidth' , 'm2' , 0.14 , Length , 'm2.1') + , ('minSpacing' , 'm2' , 0.14 , Length , 'm2.2') + , ('minArea' , 'm2' , 0.0676, Area , 'm2.6') + , ('minEnclosure' , 'm2' , 'via' , 0.055 , Length|Asymmetric, 'm2.4 and m2.5 : 0.085 end of line') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm2' , 'via' , 0.055 , Length|Asymmetric, 'dup. m2.4 and m2.5 : 0.085 end of line') + + # VIM2 (via2) + , ('minWidth' , 'via2' , 0.20 , Length , 'via2.1a') + , ('minSpacing' , 'via2' , 0.20 , Length , 'via2.2') + , ('minEnclosure' , 'm2' , 'via2' , 0.04 , Length|Asymmetric, 'via2.4 via2.5 : 0.085 and via2.14') + + # MM3 (m3) + , ('minWidth' , 'm3' , 0.30 , Length , 'm3.1') + , ('minSpacing' , 'm3' , 0.30 , Length , 'm3.2') + , ('minSpacing' , 'widem3' , 0.40 , Length , 'm3.3d') + , ('minArea' , 'm3' , 0.24 , Area , 'm3.6' ) + , ('minEnclosure' , 'm3' , 'via2' , 0.065 , Length|Asymmetric, 'm3.4') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm3' , 'via2' , 0.065 , Length|Asymmetric, 'dup. m3.4') + + # VIM3 (via3) + , ('minWidth' , 'via3' , 0.20 , Length , 'via3.1') + , ('minSpacing' , 'via3' , 0.20 , Length , 'via3.2') + , ('minEnclosure' , 'm3' , 'via3' , 0.060 , Length|Asymmetric, 'via3.4 and via3.5 end of line : 0.090') + + # MM4 (m4) + , ('minWidth' , 'm4' , 0.30 , Length , 'm4.1') + , ('minSpacing' , 'm4' , 0.30 , Length , 'm4.2') + , ('minArea' , 'm4' , 0.24 , Area , 'm4.4a') + , ('minEnclosure' , 'm4' , 'via3' , 0.065 , Length|Asymmetric, 'm4.3') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm4' , 'via3' , 0.065 , Length|Asymmetric, 'dup. m4.3 ') + + # VIM4 (via4) + , ('minWidth' , 'via4' , 0.80 , Length , 'via4.1') + , ('minSpacing' , 'via4' , 0.80 , Length , 'via4.2') + , ('minEnclosure' , 'm4' , 'via4' , 0.19 , Length|Asymmetric, 'via4.4') + + # MM5 (m5) + , ('minWidth' , 'm5' , 1.6 , Length , 'm5.1') + , ('minSpacing' , 'm5' , 1.6 , Length , 'm5.2') + , ('minArea' , 'm5' , 4.00 , Area , 'm5.4') + , ('minEnclosure' , 'm5' , 'via4' , 0.310 , Length|Asymmetric, 'm5.3') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm5' , 'via4' , 0.310 , Length|Asymmetric, 'dup. m5.3 ') + + + #capm + #, ('minWidth' , 'metcap' , 1.0 , Length , 'capm.1') + #, ('minWidth' , 'metcapdum' , 0.5 , Length , '') + #, ('maxWidth' , 'metcap' , 300.0 , Length , '') + #, ('maxWidth' , 'metbot' , 350.0 , Length , '') + #, ('minSpacing' , 'metcap' , 0.84 , Length , 'capm.2a') + #, ('minSpacing' , 'metbot' , 0.8 , Length , 'metcap.2b') + #, ('minSpacing' , 'cut1' , 'metcap' , 0.50 , Length , '') + #, ('minSpacing' , 'cut2' , 'metcap' , 0.50 , Length , 'capm.5') + #, ('minSpacingOnMetbot', 'cut2' , 0.2 , Length , 'via2.2') + #, ('minSpacingOnMetbot', 'via2' , 0.2 , Length , 'via2.2') + #, ('minSpacingOnMetcap', 'cut2' , 0.2 , Length , 'via2.2') + #, ('minEnclosure' , 'm2' , 'metcap' , 0.14 , Length|Asymmetric, 'capm.3') + #, ('minEnclosure' , 'metbot' , 'cut1' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'metbot' , 'cut2' , 0.04 , Length|Asymmetric, 'via2.14') + #, ('minEnclosure' , 'metcap' , 'cut2' , 0.14 , Length|Asymmetric, 'capm.4') + #, ('minArea' , 'metcap' , 0 , Area , 'na') + #, ('minAreaInMetcap' , 'cut2' , 0 , Area , 'na') + #, ('MIMCap' , 1.25 , Unit , 'na') + #, ('MIMPerimeterCap' , 0.17 , Unit , 'na') + + + #capm + , ('minWidth' , 'capm' , 1.0 , Length , 'capm.1') + , ('minWidth' , 'capmdum' , 0.5 , Length , '') + , ('maxWidth' , 'capm' , 30.0 , Length , '') + , ('maxWidth' , 'metbot' , 35.0 , Length , '') + , ('minSpacing' , 'capm' , 0.84 , Length , 'capm.2a') + #, ('minSpacing' , 'm3' , 0.8 , Length , 'capm.2b') + , ('minSpacingWide1' , 'm2' , 0.8 , Length , 'capm.2b') + , ('minSpacing' , 'via' , 'capm' , 0.50 , Length , 'fake') + , ('minSpacing' , 'via2' , 'capm' , 0.50 , Length , 'capm.5') + , ('minSpacingOnMetBot', 'via2' , 0.2 , Length , 'via2.2') + , ('minSpacingOnMetCap', 'via2' , 0.2 , Length , 'via2.2') + , ('minSpacingOnMetBot', 'via' , 0.2 , Length , 'via2.2 fake') + , ('minSpacingOnMetCap', 'via' , 0.2 , Length , 'via2.2 fake') + , ('minEnclosure' , 'm2' , 'capm' , 0.14 , Length|Asymmetric, 'capm.3') + , ('minEnclosure' , 'm3' , 'via' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'm3' , 'via2' , 0.04 , Length|Asymmetric, 'via2.14') + , ('minEnclosure' , 'capm' , 'via' , 0.14 , Length|Asymmetric, 'capm.4 fake') + , ('minEnclosure' , 'capm' , 'via2' , 0.14 , Length|Asymmetric, 'capm.4') + , ('minArea' , 'capm' , 0 , Area , 'na') + , ('minAreaInMetcap' , 'via2' , 0 , Area , 'na') + , ('MIMCap' , 1.25 , Unit , 'na') + , ('MIMPerimeterCap' , 0.17 , Unit , 'na') + , ('PIPCap' , 1.25 , Unit , 'na') + , ('PIPPerimeterCap' , 0.17 , Unit , 'na') + + ) + + +def _loadDtr (): + """ + Load design kit physical rules for SkyWater 130nm. + """ + loadAnalogTechno( analogTechnologyTable, __file__ ) + + +def _loadDevices (): + addDevice( name = 'DifferentialPairBulkConnected' + #, spice = spiceDir+'DiffPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'DifferentialPairBulkUnconnected' + #, spice = spiceDir+'DiffPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'LevelShifterBulkUnconnected' + #, spice = spiceDir+'LevelShifterBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S1', 'S2', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.LS_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.LS_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.LS_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.LS_interdigitated.py' ) + ) + ) + addDevice( name = 'TransistorBulkConnected' + #, spice = spiceDir+'TransistorBulkConnected.spi' + , connectors = ( 'D', 'G', 'S' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'TransistorBulkUnconnected' + #, spice = spiceDir+'TransistorBulkUnconnected.spi' + , connectors = ( 'D', 'G', 'S', 'B' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkConnected' + #, spice = spiceDir+'CCPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkUnconnected' + #, spice = spiceDir+'CCPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkConnected' + #, spice = spiceDir+'CommonSourcePairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkUnconnected' + #, spice = spiceDir+'CommonSourcePairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkConnected' + #, spice = spiceDir+'CurrMirBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkUnconnected' + #, spice = spiceDir+'CurrMirBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'MultiCapacitor' + #, spice = spiceDir+'MIM_OneCapacitor.spi' + , connectors = ( 'T1', 'B1' ) + , layouts = ( ('Matrix', 'coriolis.oroshi.multicapacitor.py' ), + ) + ) + #addDevice( name = 'Resistor' + # #, spice = spiceDir+'MIM_OneCapacitor.spi' + # , connectors = ( 'PIN1', 'PIN2' ) + # , layouts = ( ('Snake', 'coriolis.oroshi.resistorsnake.py' ), + # ) + # ) + + +def _setup_techno ( coriolisTechDir ): + ShellEnv.RDS_TECHNO_NAME = (coriolisTechDir / 'sky130_lsx' / 'sky130_lsx.rds').as_posix() + ShellEnv.GRAAL_TECHNO_NAME = (coriolisTechDir / 'sky130_lsx' / 'symbolic.graal' ).as_posix() + ShellEnv.DREAL_TECHNO_NAME = (coriolisTechDir / 'sky130_lsx' / 'symbolic.dreal' ).as_posix() + + db = DataBase.getDB() + CRL.System.get() + + tech = Technology.create(db, 'Sky130_lsx') + + DbU.setPrecision( 2 ) + DbU.setPhysicalsPerGrid( 0.0025, DbU.UnitPowerMicro ) + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + cfg.gdsDriver.metricDbu = 1e-09 + cfg.gdsDriver.dbuPerUu = 0.001 + DbU.setGridsPerLambda ( 30 ) + DbU.setSymbolicSnapGridStep( DbU.fromGrid( 1.0 )) + DbU.setPolygonStep ( DbU.fromGrid( 1.0 )) + DbU.setStringMode ( DbU.StringModePhysical, DbU.UnitPowerMicro ) + + createBL( tech, 'nwm' , BasicLayer.Material.nWell , size=u(0.84), spacing=u(1.27), gds2Layer= 64, gds2DataType= 20 ) + createBL( tech, 'nsdm' , BasicLayer.Material.nImplant, size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 93, gds2DataType= 44 ) + createBL( tech, 'psdm' , BasicLayer.Material.pImplant, size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 94, gds2DataType= 20 ) + createBL( tech, 'hvi' , BasicLayer.Material.other , gds2Layer= 75, gds2DataType= 20 ) + createBL( tech, 'difftap.pin' , BasicLayer.Material.other , gds2Layer= 65, gds2DataType= 16 ) + createBL( tech, 'difftap.block', BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 10 ) + createBL( tech, 'poly.pin' , BasicLayer.Material.other , gds2Layer= 66, gds2DataType= 16 ) + createBL( tech, 'poly.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 20 ) + createBL( tech, 'li.pin' , BasicLayer.Material.other , gds2Layer= 67, gds2DataType= 16 ) + createBL( tech, 'li.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 40 ) + createBL( tech, 'm1.pin' , BasicLayer.Material.other , gds2Layer= 68, gds2DataType= 16 ) + createBL( tech, 'm1.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 60 ) + createBL( tech, 'm2.pin' , BasicLayer.Material.other , gds2Layer= 69, gds2DataType= 16 ) + createBL( tech, 'm2.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 80 ) + createBL( tech, 'm3.pin' , BasicLayer.Material.other , gds2Layer= 70, gds2DataType= 16 ) + createBL( tech, 'm3.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=100 ) + createBL( tech, 'm4.pin' , BasicLayer.Material.other , gds2Layer= 71, gds2DataType= 16 ) + createBL( tech, 'm4.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=120 ) + createBL( tech, 'm5.pin' , BasicLayer.Material.other , gds2Layer= 72, gds2DataType= 16 ) + createBL( tech, 'm5.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=140 ) + createBL( tech, 'licon.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 30 ) + createBL( tech, 'mcon.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 50 ) + createBL( tech, 'via.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 70 ) + createBL( tech, 'via2.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 90 ) + createBL( tech, 'via3.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=110 ) + createBL( tech, 'via4.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=130 ) + createBL( tech, 'difftap' , BasicLayer.Material.active , size=u(0.15), spacing=u(0.27), gds2Layer= 65, gds2DataType= 20 ) + createBL( tech, 'poly' , BasicLayer.Material.poly , size=u(0.15), spacing=u(0.21), gds2Layer= 66, gds2DataType= 20 ) + createBL( tech, 'licon' , BasicLayer.Material.cut , size=u(0.17), spacing=u(0.17), gds2Layer= 66, gds2DataType= 44 ) + createBL( tech, 'li' , BasicLayer.Material.metal , size=u(0.17), spacing=u(0.17), gds2Layer= 67, gds2DataType= 20 ) + createBL( tech, 'mcon' , BasicLayer.Material.cut , size=u(0.17), spacing=u(0.19), gds2Layer= 67, gds2DataType= 44 ) + createBL( tech, 'm1' , BasicLayer.Material.metal , size=u(0.14), spacing=u(0.14), area=0.083, gds2Layer= 68, gds2DataType= 20 ) + createBL( tech, 'via' , BasicLayer.Material.cut , size=u(0.15), spacing=u(0.17), gds2Layer= 68, gds2DataType= 44 ) + createBL( tech, 'm2' , BasicLayer.Material.metal , size=u(0.14), spacing=u(0.14), area=0.0676, gds2Layer= 69, gds2DataType= 20 ) + createBL( tech, 'capm' , BasicLayer.Material.metal ) + createBL( tech, 'via2' , BasicLayer.Material.cut , size=u(0.2 ), spacing=u(0.2 ), gds2Layer= 69, gds2DataType= 44 ) + createBL( tech, 'm3' , BasicLayer.Material.metal , size=u(0.3 ), spacing=u(0.3 ), area=0.24, gds2Layer= 70, gds2DataType= 20 ) + createBL( tech, 'via3' , BasicLayer.Material.cut , size=u(0.2 ), spacing=u(0.2 ), gds2Layer= 70, gds2DataType= 44 ) + createBL( tech, 'm4' , BasicLayer.Material.metal , size=u(0.3 ), spacing=u(0.3 ), area=0.24, gds2Layer= 71, gds2DataType= 20 ) + createBL( tech, 'via4' , BasicLayer.Material.cut , size=u(0.8 ), spacing=u(0.8 ), gds2Layer= 71, gds2DataType= 44 ) + createBL( tech, 'm5' , BasicLayer.Material.metal , size=u(1.6 ), spacing=u(1.6 ), area=4.0, gds2Layer= 72, gds2DataType= 20 ) + createBL( tech, 'hvtp' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 78, gds2DataType= 44 ) + createBL( tech, 'lvtn' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer=125, gds2DataType= 44 ) + createBL( tech, 'areaid_sc' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 4 ) + createBL( tech, 'pad' , BasicLayer.Material.cut , size=u(40.0), spacing=u(1.27), gds2Layer= 76, gds2DataType= 20 ) + createBL( tech, 'areaid_diode' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 23 ) + createBL( tech, 'pnp' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 44 ) + createBL( tech, 'diffres' , BasicLayer.Material.other , gds2Layer= 65, gds2DataType= 13 ) + createBL( tech, 'npn' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 20 ) + createBL( tech, 'polyres' , BasicLayer.Material.other , gds2Layer= 66, gds2DataType= 13 ) + createBL( tech, 'prBoundary' , BasicLayer.Material.other , gds2Layer=235, gds2DataType= 4 ) + + tech.addLayerAlias( 'm1', 'met1' ) + tech.addLayerAlias( 'm2', 'met2' ) + tech.addLayerAlias( 'm3', 'met3' ) + tech.addLayerAlias( 'm4', 'met4' ) + tech.addLayerAlias( 'm5', 'met5' ) + + # ViaLayers + createVia( tech, 'li_mcon_m1' , 'li' , 'mcon', 'm1', u(0.17) ) + createVia( tech, 'm1_via_m2' , 'm1' , 'via' , 'm2', u(0.15) ) + createVia( tech, 'm2_via2_m3' , 'm2' , 'via2', 'm3', u(0.2 ) ) + createVia( tech, 'capm_via2_m3', 'capm', 'via2', 'm3', u(0.2 ) ) + createVia( tech, 'm3_via3_m4' , 'm3' , 'via3', 'm4', u(0.2 ) ) + createVia( tech, 'm4_via4_m5' , 'm4' , 'via4', 'm5', u(0.8 ) ) + + # Blockages + tech.getLayer('difftap').setBlockageLayer( tech.getLayer('difftap.block') ) + tech.getLayer('poly') .setBlockageLayer( tech.getLayer('poly.block') ) + tech.getLayer('li') .setBlockageLayer( tech.getLayer('li.block') ) + tech.getLayer('m1') .setBlockageLayer( tech.getLayer('m1.block') ) + tech.getLayer('m2') .setBlockageLayer( tech.getLayer('m2.block') ) + tech.getLayer('m3') .setBlockageLayer( tech.getLayer('m3.block') ) + tech.getLayer('m4') .setBlockageLayer( tech.getLayer('m4.block') ) + tech.getLayer('m5') .setBlockageLayer( tech.getLayer('m5.block') ) + tech.getLayer('licon') .setBlockageLayer( tech.getLayer('licon.block') ) + tech.getLayer('mcon') .setBlockageLayer( tech.getLayer('mcon.block') ) + tech.getLayer('via') .setBlockageLayer( tech.getLayer('via.block') ) + tech.getLayer('via2') .setBlockageLayer( tech.getLayer('via2.block') ) + tech.getLayer('via3') .setBlockageLayer( tech.getLayer('via3.block') ) + tech.getLayer('via4') .setBlockageLayer( tech.getLayer('via4.block') ) + + # Coriolis internal layers + createBL( tech, 'text.cell' , BasicLayer.Material.other, ) + createBL( tech, 'text.instance', BasicLayer.Material.other, ) + createBL( tech, 'SPL1' , BasicLayer.Material.other, ) + createBL( tech, 'AutoLayer' , BasicLayer.Material.other, ) + createBL( tech, 'gmetalh' , BasicLayer.Material.metal, ) + createBL( tech, 'gcontact' , BasicLayer.Material.cut, ) + createBL( tech, 'gmetalv' , BasicLayer.Material.metal, ) + + # Resistors + # ResistorLayer.create(tech, 'poly_res', 'poly', 'polyres') + # ResistorLayer.create(tech, 'active_res', 'difftap', 'diffres') + + # Transistors + # GateLayer.create(tech, 'hvmosgate' , 'difftap', 'poly', 'hvi') + # GateLayer.create(tech, 'mosgate' , 'difftap', 'poly') + # GateLayer.create(tech, 'mosgate_sc', 'difftap', 'poly') + # TransistorLayer.create(tech, 'nfet_01v8' , 'mosgate' , 'nsdm') + # TransistorLayer.create(tech, 'nfet_01v8_lvt' , 'mosgate' , ('nsdm', 'lvtn')) + # TransistorLayer.create(tech, 'nfet_01v8_sc' , 'mosgate_sc', 'nsdm') + # TransistorLayer.create(tech, 'nfet_g5v0d10v5', 'hvmosgate' , 'nsdm') + # TransistorLayer.create(tech, 'pfet_01v8' , 'mosgate' , 'psdm', 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_hvt' , 'mosgate' , ('psdm', 'hvtp'), 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_lvt' , 'mosgate' , ('psdm', 'lvtn'), 'nwm') + # TransistorLayer.create(tech, 'pfet_g5v0d10v5', 'hvmosgate' , 'psdm', 'nwm') + + # Bipolars + # Not implemented: Bipolar 'pnp_05v5_w0u68l0u68' + # Not implemented: Bipolar 'npn_05v5_w1u00l2u00' + # Not implemented: Bipolar 'pnp_05v5_w3u40l3u40' + # Not implemented: Bipolar 'npn_05v5_w1u00l1u00' + + +def _setup_display (): + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [black] + + threshold = 0.2 if Viewer.Graphics.isHighDpi() else 0.1 + + style = Viewer.DisplayStyle( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - black background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + # Viewer. + style.addDrawingStyle( group='Viewer', name='fallback' , color=toRGB('Gray238' ), border=1, pattern='55AA55AA55AA55AA' ) + style.addDrawingStyle( group='Viewer', name='background' , color=toRGB('Gray50' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='rubber' , color=toRGB('192,0,192' ), border=4, threshold=0.02 ) + style.addDrawingStyle( group='Viewer', name='phantom' , color=toRGB('Seashell4' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries' , color=toRGB('wheat1' ), border=2, pattern='0000000000000000', threshold=0 ) + style.addDrawingStyle( group='Viewer', name='marker' , color=toRGB('80,250,80' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionDraw' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionFill' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='grid' , color=toRGB('White' ), border=1, threshold=2.0 ) + style.addDrawingStyle( group='Viewer', name='spot' , color=toRGB('White' ), border=2, threshold=6.0 ) + style.addDrawingStyle( group='Viewer', name='ghost' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='text.ruler' , color=toRGB('White' ), border=1, threshold= 0.0 ) + style.addDrawingStyle( group='Viewer', name='text.instance' , color=toRGB('White' ), border=1, threshold=400.0 ) + style.addDrawingStyle( group='Viewer', name='text.reference', color=toRGB('White' ), border=1, threshold=200.0 ) + style.addDrawingStyle( group='Viewer', name='undef' , color=toRGB('Violet' ), border=0, pattern='2244118822441188' ) + + # Active Layers. + style.addDrawingStyle(group='Active Layers', name='nwm' , color=toRGB('Tan' ), pattern=toHexa('urgo.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='nsdm' , color=toRGB('LawnGreen'), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='psdm' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='hvtp' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='lvtn' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='difftap' , color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='difftap.pin', color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly.pin' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + + # Routing Layers. + style.addDrawingStyle(group='Routing Layers', name='li' , color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='li.pin', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m1' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m1.pin', color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m2' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m2.pin', color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m3' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m3.pin', color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m4' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m4.pin', color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m5' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m5.pin', color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + + # Cuts (VIA holes). + style.addDrawingStyle(group='Cuts (VIA holes', name='licon', color=toRGB('0,150,150'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='mcon' , color=toRGB('Aqua' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via' , color=toRGB('LightPink'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via2' , color=toRGB('Green' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via3' , color=toRGB('Yellow' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via4' , color=toRGB('Violet' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='pad' , color=toRGB('Red' ), threshold=threshold) + + # Blockages. + style.addDrawingStyle(group='Blockages', name='difftap.block', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='poly.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='li.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m1.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m2.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m3.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m4.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m5.block' , color=toRGB('Blue' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='licon.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='mcon.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via2.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via3.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via4.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + + # Knick & Kite. + style.addDrawingStyle( group='Knik & Kite', name='SPL1' , color=toRGB('Red' ) ) + style.addDrawingStyle( group='Knik & Kite', name='AutoLayer' , color=toRGB('Magenta' ) ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalh' , color=toRGB('128,255,200'), pattern=toHexa('antislash2.32' ), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalv' , color=toRGB('200,200,255'), pattern=toHexa('light_antihash1.8'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gcontact' , color=toRGB('255,255,190'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::Edge' , color=toRGB('255,255,190'), pattern='0000000000000000' , border=4, threshold=0.02 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::GCell', color=toRGB('255,255,190'), pattern='0000000000000000' , border=2, threshold=threshold ) + + Viewer.Graphics.addStyle( style ) + + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [white]. + + style = Viewer.DisplayStyle( 'Alliance.Classic [white]' ) + style.inheritFrom( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - white background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + style.addDrawingStyle( group='Viewer', name='background', color=toRGB('White'), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground', color=toRGB('Black'), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries', color=toRGB('Black'), border=1, pattern='0000000000000000' ) + Viewer.Graphics.addStyle( style ) + + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + +def setup ( coriolisTechDir ): + _setup_techno( coriolisTechDir ) + _setup_display() + try: + from .techno_symb import setup as setupSymbolic + except: + pass + else: + setupSymbolic() + _loadDtr() + _loadDevices() + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/techno_symb.py b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/techno_symb.py new file mode 100644 index 000000000..1b2601d47 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/coriolis/sky130_lsx/techno_symb.py @@ -0,0 +1,284 @@ + +from coriolis.helpers import l, u, n +from coriolis.Hurricane import DataBase, Technology, Layer, BasicLayer, DiffusionLayer, \ + TransistorLayer, RegularLayer, ContactLayer, ViaLayer + +__all__ = [ 'setup' ] + + +def setup (): + tech = DataBase.getDB().getTechnology() + tech.addLayerAlias( 'nwm' , 'nWell' ) + tech.addLayerAlias( 'difftap' , 'active' ) + #tech.addLayerAlias( 'poly' , 'poly' ) + tech.addLayerAlias( 'psdm' , 'pImplant' ) + tech.addLayerAlias( 'nsdm' , 'nImplant' ) + tech.addLayerAlias( 'licon' , 'cut0' ) + tech.addLayerAlias( 'li' , 'metal1' ) + tech.addLayerAlias( 'mcon' , 'cut1' ) + tech.addLayerAlias( 'm1' , 'metal2' ) + tech.addLayerAlias( 'via' , 'cut2' ) + tech.addLayerAlias( 'm2' , 'metal3' ) + tech.addLayerAlias( 'via2' , 'cut3' ) + tech.addLayerAlias( 'm3' , 'metal4' ) + tech.addLayerAlias( 'via3' , 'cut4' ) + tech.addLayerAlias( 'm4' , 'metla5' ) + tech.addLayerAlias( 'via4' , 'cut5' ) + tech.addLayerAlias( 'm5' , 'metal6' ) + tech.addLayerAlias( 'li.block', 'blockage1' ) + tech.addLayerAlias( 'm1.block', 'blockage2' ) + tech.addLayerAlias( 'm2.block', 'blockage3' ) + tech.addLayerAlias( 'm3.block', 'blockage4' ) + tech.addLayerAlias( 'm4.block', 'blockage5' ) + tech.addLayerAlias( 'm5.block', 'blockage6' ) + tech.addLayerAlias( 'capm' , 'metcap' ) + tech.addLayerAlias( 'capm' , 'metcapdum' ) + tech.addLayerAlias( 'm3' , 'metbot' ) + + nWell = tech.getBasicLayer( 'nwm' ) + active = tech.getBasicLayer( 'difftap' ) + poly = tech.getBasicLayer( 'poly' ) + pImplant = tech.getBasicLayer( 'psdm' ) + nImplant = tech.getBasicLayer( 'nsdm' ) + cut0 = tech.getBasicLayer( 'licon' ) + metal1 = tech.getBasicLayer( 'li' ) + cut1 = tech.getBasicLayer( 'mcon' ) + metal2 = tech.getBasicLayer( 'm1' ) + cut2 = tech.getBasicLayer( 'via' ) + metal3 = tech.getBasicLayer( 'm2' ) + cut3 = tech.getBasicLayer( 'via2' ) + metal4 = tech.getBasicLayer( 'm3' ) + cut4 = tech.getBasicLayer( 'via3' ) + metal5 = tech.getBasicLayer( 'm4' ) + cut5 = tech.getBasicLayer( 'via4' ) + metal6 = tech.getBasicLayer( 'm5' ) + blockage1 = tech.getBasicLayer( 'blockage1' ) + blockage2 = tech.getBasicLayer( 'blockage1' ) + blockage3 = tech.getBasicLayer( 'blockage2' ) + blockage4 = tech.getBasicLayer( 'blockage3' ) + blockage5 = tech.getBasicLayer( 'blockage4' ) + blockage6 = tech.getBasicLayer( 'blockage5' ) + + # Composite/Symbolic layers. + NWELL = RegularLayer .create( tech, 'NWELL' , nWell ) + #PWELL = RegularLayer .create( tech, 'PWELL' , pWell ) + NTIE = DiffusionLayer .create( tech, 'NTIE' , nImplant , active, nWell) + PTIE = DiffusionLayer .create( tech, 'PTIE' , pImplant , active, None) + NDIF = DiffusionLayer .create( tech, 'NDIF' , nImplant , active, None ) + PDIF = DiffusionLayer .create( tech, 'PDIF' , pImplant , active, None ) + GATE = DiffusionLayer .create( tech, 'GATE' , poly , active, None ) + NTRANS = TransistorLayer.create( tech, 'NTRANS' , nImplant , active, poly, None ) + PTRANS = TransistorLayer.create( tech, 'PTRANS' , pImplant , active, poly, nWell ) + POLY = RegularLayer .create( tech, 'POLY' , poly ) + METAL1 = RegularLayer .create( tech, 'METAL1' , metal1 ) + METAL2 = RegularLayer .create( tech, 'METAL2' , metal2 ) + METAL3 = RegularLayer .create( tech, 'METAL3' , metal3 ) + METAL4 = RegularLayer .create( tech, 'METAL4' , metal4 ) + METAL5 = RegularLayer .create( tech, 'METAL5' , metal5 ) + METAL6 = RegularLayer .create( tech, 'METAL6' , metal6 ) + CONT_BODY_N = ContactLayer .create( tech, 'CONT_BODY_N', nImplant , active, cut0, metal1, None ) + CONT_BODY_P = ContactLayer .create( tech, 'CONT_BODY_P', pImplant , active, cut0, metal1, None ) + CONT_DIF_N = ContactLayer .create( tech, 'CONT_DIF_N' , nImplant , active, cut0, metal1, None ) + CONT_DIF_P = ContactLayer .create( tech, 'CONT_DIF_P' , pImplant , active, cut0, metal1, None ) + CONT_POLY = ViaLayer .create( tech, 'CONT_POLY' , poly, cut0, metal1 ) + + # VIAs for symbolic technologies. + VIA12 = ViaLayer .create( tech, 'VIA12' , metal1, cut1, metal2 ) + VIA23 = ViaLayer .create( tech, 'VIA23' , metal2, cut2, metal3 ) + #VIA23cap = ViaLayer .create( tech, 'VIA23cap' , metcap, cut2, metal3 ) + VIA34 = ViaLayer .create( tech, 'VIA34' , metal3, cut3, metal4 ) + VIA45 = ViaLayer .create( tech, 'VIA45' , metal4, cut4, metal5 ) + VIA56 = ViaLayer .create( tech, 'VIA56' , metal5, cut5, metal6 ) + BLOCKAGE1 = RegularLayer.create( tech, 'BLOCKAGE1' , blockage1 ) + BLOCKAGE2 = RegularLayer.create( tech, 'BLOCKAGE2' , blockage2 ) + BLOCKAGE3 = RegularLayer.create( tech, 'BLOCKAGE3' , blockage3 ) + BLOCKAGE4 = RegularLayer.create( tech, 'BLOCKAGE4' , blockage4 ) + BLOCKAGE5 = RegularLayer.create( tech, 'BLOCKAGE5' , blockage5 ) + BLOCKAGE6 = RegularLayer.create( tech, 'BLOCKAGE6' , blockage6 ) + + tech.setSymbolicLayer( CONT_BODY_N.getName() ) + tech.setSymbolicLayer( CONT_BODY_P.getName() ) + tech.setSymbolicLayer( CONT_DIF_N .getName() ) + tech.setSymbolicLayer( CONT_DIF_P .getName() ) + tech.setSymbolicLayer( CONT_POLY .getName() ) + tech.setSymbolicLayer( POLY .getName() ) + tech.setSymbolicLayer( METAL1 .getName() ) + tech.setSymbolicLayer( METAL2 .getName() ) + tech.setSymbolicLayer( METAL3 .getName() ) + tech.setSymbolicLayer( METAL4 .getName() ) + tech.setSymbolicLayer( METAL5 .getName() ) + tech.setSymbolicLayer( METAL6 .getName() ) + tech.setSymbolicLayer( BLOCKAGE1 .getName() ) + tech.setSymbolicLayer( BLOCKAGE2 .getName() ) + tech.setSymbolicLayer( BLOCKAGE3 .getName() ) + tech.setSymbolicLayer( BLOCKAGE4 .getName() ) + tech.setSymbolicLayer( BLOCKAGE5 .getName() ) + tech.setSymbolicLayer( BLOCKAGE6 .getName() ) + tech.setSymbolicLayer( VIA12 .getName() ) + tech.setSymbolicLayer( VIA23 .getName() ) + tech.setSymbolicLayer( VIA34 .getName() ) + tech.setSymbolicLayer( VIA45 .getName() ) + tech.setSymbolicLayer( VIA56 .getName() ) + + NWELL.setExtentionCap( nWell, l(0.0) ) + #PWELL.setExtentionCap( pWell, l(0.0) ) + + NTIE.setMinimalSize ( l(1.5) ) + NTIE.setExtentionCap ( nWell , l(0.75) ) + NTIE.setExtentionWidth( nWell , l(0.25) ) + NTIE.setExtentionCap ( nImplant, l(0.5) ) + NTIE.setExtentionWidth( nImplant, l(0.25) ) + NTIE.setExtentionCap ( active , l(0.25) ) + NTIE.setExtentionWidth( active , l(0.0) ) + + PTIE.setMinimalSize ( l(1.5) ) + PTIE.setExtentionCap ( nWell , l(0.75) ) + PTIE.setExtentionWidth( nWell , l(0.25) ) + PTIE.setExtentionCap ( nImplant, l(0.5) ) + PTIE.setExtentionWidth( nImplant, l(0.25) ) + PTIE.setExtentionCap ( active , l(0.25) ) + PTIE.setExtentionWidth( active , l(0.0) ) + + NDIF.setMinimalSize ( l(1.5) ) + NDIF.setExtentionCap ( nImplant, l(0.5) ) + NDIF.setExtentionWidth( nImplant, l(0.25) ) + NDIF.setExtentionCap ( active , l(0.25) ) + NDIF.setExtentionWidth( active , l(0.0) ) + + PDIF.setMinimalSize ( l(1.5) ) + PDIF.setExtentionCap ( pImplant, l(0.5) ) + PDIF.setExtentionWidth( pImplant, l(0.25) ) + PDIF.setExtentionCap ( active , l(0.25) ) + PDIF.setExtentionWidth( active , l(0.0) ) + + GATE.setMinimalSize ( l(0.5) ) + GATE.setExtentionCap ( poly , l(0.75) ) + + NTRANS.setMinimalSize ( l( 1.0) ) + NTRANS.setExtentionCap ( nImplant, l(-1.0) ) + NTRANS.setExtentionWidth( nImplant, l( 2.5) ) + NTRANS.setExtentionCap ( active , l(-1.5) ) + NTRANS.setExtentionWidth( active , l( 2.0) ) + + PTRANS.setMinimalSize ( l( 0.5) ) + PTRANS.setExtentionCap ( nWell , l(-0.5) ) + PTRANS.setExtentionWidth( nWell , l( 2.25) ) + PTRANS.setExtentionCap ( pImplant, l(-0.5) ) + PTRANS.setExtentionWidth( pImplant, l( 2.0) ) + PTRANS.setExtentionCap ( active , l(-0.75) ) + PTRANS.setExtentionWidth( active , l( 1.5) ) + + POLY .setMinimalSize ( l(0.5) ) + POLY .setExtentionCap ( poly , l(0.25) ) + #POLY2.setMinimalSize ( l(1.0) ) + #POLY2.setExtentionCap ( poly , l(0.5) ) + + METAL1 .setMinimalSize ( l(0.5) ) + METAL1 .setExtentionCap ( metal1 , l(0.25) ) + METAL2 .setMinimalSize ( l(0.5) ) + METAL2 .setExtentionCap ( metal2 , l(0.5) ) + METAL3 .setMinimalSize ( l(0.5) ) + METAL3 .setExtentionCap ( metal3 , l(0.5) ) + METAL4 .setMinimalSize ( l(0.5) ) + METAL4 .setExtentionCap ( metal4 , l(0.5) ) + METAL4 .setMinimalSpacing( l(1.5) ) + METAL5 .setMinimalSize ( l(1.0) ) + METAL5 .setExtentionCap ( metal5 , l(0.5) ) + #METAL6 .setMinimalSize ( l(2.0) ) + #METAL6 .setExtentionCap ( metal6 , l(1.0) ) + #METAL7 .setMinimalSize ( l(2.0) ) + #METAL7 .setExtentionCap ( metal7 , l(1.0) ) + #METAL8 .setMinimalSize ( l(2.0) ) + #METAL8 .setExtentionCap ( metal8 , l(1.0) ) + #METAL9 .setMinimalSize ( l(2.0) ) + #METAL9 .setExtentionCap ( metal9 , l(1.0) ) + #METAL10.setMinimalSize ( l(2.0) ) + #METAL10.setExtentionCap ( metal10 , l(1.0) ) + + # Contacts (i.e. Active <--> Metal) (symbolic). + CONT_BODY_N.setMinimalSize( l( 0.5) ) + CONT_BODY_N.setEnclosure ( nWell , l( 0.75), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( nImplant, l( 0.75), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_BODY_P.setMinimalSize( l( 0.5) ) + #CONT_BODY_P.setEnclosure ( pWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( pImplant, l( 0.75), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_N.setMinimalSize( l( 0.5) ) + CONT_DIF_N.setEnclosure ( nImplant, l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( active , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_P.setMinimalSize( l( 0.5) ) + CONT_DIF_P.setEnclosure ( pImplant, l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( active , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_POLY.setMinimalSize( l( 0.5) ) + CONT_POLY.setEnclosure ( poly , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + CONT_POLY.setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + + # VIAs (i.e. Metal <--> Metal) (symbolic). + VIA12 .setMinimalSize ( l( 0.5) ) + VIA12 .setEnclosure ( metal1 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setEnclosure ( metal2 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setMinimalSpacing( l( 2.0) ) + VIA23 .setMinimalSize ( l( 0.5) ) + VIA23 .setEnclosure ( metal2 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setEnclosure ( metal3 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setMinimalSpacing( l( 2.0) ) + VIA34 .setMinimalSize ( l( 0.5) ) + VIA34 .setEnclosure ( metal3 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setEnclosure ( metal4 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setMinimalSpacing( l( 2.0) ) + VIA45 .setMinimalSize ( l( 0.5) ) + VIA45 .setEnclosure ( metal4 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setEnclosure ( metal5 , l( 0.25), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setMinimalSpacing( l( 2.0) ) + #VIA56 .setMinimalSize ( l( 1.0) ) + #VIA56 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setMinimalSpacing( l( 4.0) ) + #VIA67 .setMinimalSize ( l( 1.0) ) + #VIA67 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSize ( l( 1.0) ) + #VIA78 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA89 .setMinimalSize ( l( 1.0) ) + #VIA89 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setMinimalSpacing( l( 4.0) ) + #VIA910.setMinimalSize ( l( 1.0) ) + #VIA910.setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setEnclosure ( metal10 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setMinimalSpacing( l( 4.0) ) + + # Blockages (symbolic). + BLOCKAGE1 .setMinimalSize ( l( 0.5) ) + BLOCKAGE1 .setExtentionCap( blockage1 , l( 0.25) ) + BLOCKAGE2 .setMinimalSize ( l( 1.0) ) + BLOCKAGE2 .setExtentionCap( blockage2 , l( 0.25) ) + BLOCKAGE3 .setMinimalSize ( l( 1.0) ) + BLOCKAGE3 .setExtentionCap( blockage3 , l( 0.25) ) + BLOCKAGE4 .setMinimalSize ( l( 1.0) ) + BLOCKAGE4 .setExtentionCap( blockage4 , l( 0.25) ) + BLOCKAGE5 .setMinimalSize ( l( 1.0) ) + BLOCKAGE5 .setExtentionCap( blockage5 , l( 0.5) ) + #BLOCKAGE6 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE6 .setExtentionCap( blockage6 , l( 1.0) ) + #BLOCKAGE7 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE7 .setExtentionCap( blockage7 , l( 1.0) ) + #BLOCKAGE8 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE8 .setExtentionCap( blockage8 , l( 1.0) ) + #BLOCKAGE9 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE9 .setExtentionCap( blockage9 , l( 1.0) ) + #BLOCKAGE10.setMinimalSize ( l( 2.0) ) + #BLOCKAGE10.setExtentionCap( blockage10, l( 1.0) ) diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/core/sky130A_mr.drc b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/core/sky130A_mr.drc new file mode 100644 index 000000000..46c9b1fd1 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/core/sky130A_mr.drc @@ -0,0 +1,800 @@ +# DRC for SKY130 according to : +# https://skywater-pdk.readthedocs.io/en/latest/rules/periphery.html +# https://skywater-pdk.readthedocs.io/en/latest/rules/layers.html +# +# Distributed under GNU GPLv3: https://www.gnu.org/licenses/ +# +# History : +# 2022-6-22 : 2022.6.30_01.07 release +# +# 2023-6-14 : 2023.6.14_01.08 release +# +########################################################################################## +release = "2023.6.14_01.08" + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{msg} +" +end +# optionnal for a batch launch : klayout -b -rd input=my_layout.gds -rd report=sky130_drc.txt -r drc_sky130.drc +if $input + source($input, $top_cell) +end + +if $report == "" + report("SKY130 DRC runset") +elsif $report + report("SKY130 DRC runset", $report) +else + report("SKY130 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "sky130_drc.txt")) +end + +AL = true # do not change +CU = false # do not change +# choose betwen only one of AL or CU back-end flow here : +backend_flow = AL + +option_FEOL = false +option_BEOL = false +option_OFFGRID = false +option_SEAL = false +option_FLOATING_MET = false + +# enable / disable rule groups +if $feol == "1" || $feol == "true" + option_FEOL = true # front-end-of-line checks +else + option_FEOL = false +end + +if $beol == "1" || $beol == "true" + option_BEOL = true # back-end-of-line checks +else + option_BEOL = false +end + +if $offgrid == "1" || $offgrid == "true" + option_OFFGRID = true # manufacturing grid/angle checks +else + option_OFFGRID = false +end + +if $seal == "1" || $seal == "true" + option_SEAL = true # option_SEAL RING checks +else + option_SEAL = false +end + +if $floating_met == "1" || $floating_met == "true" + option_FLOATING_MET = true # back-end-of-line checks +else + option_FLOATING_MET = false +end + +# klayout setup +######################## +# use a tile size of 1mm - not used in deep mode- +# tiles(1000.um) +# use a tile border of 10 micron: +# tile_borders(1.um) +#no_borders + +# hierachical +deep + +if $thr + threads($thr) +else + threads(4) +end + +# if more inof is needed, set true +# verbose(true) +verbose(true) + +# layers definitions +######################## + +# all except purpose (datatype) 5 -- label and 44 -- via +li_wildcard = "67/20" +mcon_wildcard = "67/44" + +m1_wildcard = "68/20" +via_wildcard = "68/44" + +m2_wildcard = "69/20" +via2_wildcard = "69/44" + +m3_wildcard = "70/20" +via3_wildcard = "70/44" + +m4_wildcard = "71/20" +via4_wildcard = "71/44" + +m5_wildcard = "72/20" + +nsdm_wildcard = "93/44" + +psdm_wildcard = "94/20" +nwell_wildcard = "64/20" + +diff = input(65, 20) +tap = polygons(65, 44) +nwell = polygons(nwell_wildcard) +dnwell = polygons(64, 18) +pwbm = polygons(19, 44) +pwde = polygons(124, 20) +natfet = polygons(124, 21) +hvtr = polygons(18, 20) +hvtp = polygons(78, 44) +ldntm = polygons(11, 44) +hvi = polygons(75, 20) +tunm = polygons(80, 20) +lvtn = polygons(125, 44) +poly = polygons(66, 20) +hvntm = polygons(125, 20) +nsdm = polygons(nsdm_wildcard) +psdm = polygons(psdm_wildcard) +rpm = polygons(86, 20) +urpm = polygons(79, 20) +npc = polygons(95, 20) +licon = polygons(66, 44) + +li = polygons(li_wildcard) +mcon = polygons(mcon_wildcard) + +m1 = polygons(m1_wildcard) +via = polygons(via_wildcard) + +m2 = polygons(m2_wildcard) +via2 = polygons(via2_wildcard) + +m3 = polygons(m3_wildcard) +via3 = polygons(via3_wildcard) + +m4 = polygons(m4_wildcard) +via4 = polygons(via4_wildcard) + +m5 = polygons(m5_wildcard) + +pad = polygons(76, 20) +nsm = polygons(61, 20) +capm = polygons(89, 44) +cap2m = polygons(97, 44) +vhvi = polygons(74, 21) +uhvi = polygons(74, 22) +npn = polygons(82, 20) +inductor = polygons(82, 24) +vpp = polygons(82, 64) +pnp = polygons(82, 44) +lvs_prune = polygons(84, 44) +ncm = polygons(92, 44) +padcenter = polygons(81, 20) +mf = polygons(76, 44) +areaid_sl = polygons(81, 1) +areaid_ce = polygons(81, 2) +areaid_fe = polygons(81, 3) +areaid_sc = polygons(81, 4) +areaid_sf = polygons(81, 6) +areaid_sw = polygons(81, 7) +areaid_sr = polygons(81, 8) +areaid_mt = polygons(81, 10) +areaid_dt = polygons(81, 11) +areaid_ft = polygons(81, 12) +areaid_ww = polygons(81, 13) +areaid_ld = polygons(81, 14) +areaid_ns = polygons(81, 15) +areaid_ij = polygons(81, 17) +areaid_zr = polygons(81, 18) +areaid_ed = polygons(81, 19) +areaid_de = polygons(81, 23) +areaid_rd = polygons(81, 24) +areaid_dn = polygons(81, 50) +areaid_cr = polygons(81, 51) +areaid_cd = polygons(81, 52) +areaid_st = polygons(81, 53) +areaid_op = polygons(81, 54) +areaid_en = polygons(81, 57) +areaid_en20 = polygons(81, 58) +areaid_le = polygons(81, 60) +areaid_hl = polygons(81, 63) +areaid_sd = polygons(81, 70) +areaid_po = polygons(81, 81) +areaid_it = polygons(81, 84) +areaid_et = polygons(81, 101) +areaid_lvt = polygons(81, 108) +areaid_re = polygons(81, 125) +areaid_ag = polygons(81, 79) +poly_rs = polygons(66, 13) +diff_rs = polygons(65, 13) +pwell_rs = polygons(64, 13) +li_rs = polygons(67, 13) +cfom = polygons(22, 20) + + +# Define a new custom function that selects polygons by their number of holes: +# It will return a new layer containing those polygons with min to max holes. +# max can be nil to omit the upper limit. +class DRC::DRCLayer + def with_holes(min, max) + new_data = RBA::Region::new + self.data.each do |p| + if p.holes >= (min || 0) && (!max || p.holes <= max) + new_data.insert(p) + end + end + DRC::DRCLayer::new(@engine, new_data) + end +end + +# DRC section +######################## +log("DRC section") + +if option_FEOL +log("option_FEOL section") +# dnwell +log("START: 64/18 (dnwell)") +dnwell.width(3.0, euclidian).output("dnwell.2", "dnwell.2 : min. dnwell width : 3.0um") +log("END: 64/18 (dnwell)") + +not_sram = layout(source.cell_obj).select("-*sky130_sram_*kbyte_*") +not_sram_nsdm = not_sram.input(nsdm_wildcard) +not_sram_psdm = not_sram.input(psdm_wildcard) +not_sram_nwell = not_sram.input(nwell_wildcard) + +# This is a hack, should be reverted + +not_io = layout(source.cell_obj).select("-*sky130_fd_io__gpiov2_amux", "-*sky130_fd_io__simple_pad_and_busses") +not_io_nwell = not_io.input(nwell_wildcard) + +# nwell +log("START: 64/20 (nwell)") +nwell.width(0.84, euclidian).output("nwell.1", "nwell.1 : min. nwell width : 0.84um") +nwell.space(1.27, euclidian).output("nwell.2a", "nwell.2a : min. nwell spacing (merged if less) : 1.27um") +nwell_interact = not_sram_nwell.and(not_io_nwell).merge +dnwell.enclosing(nwell_interact.holes, 1.03, euclidian).output("nwell.6", "nwell.6 : min enclosure of nwellHole by dnwell : 1.03um") +log("END: 64/20 (nwell)") + +# hvtp +log("START: 78/44 (hvtp)") +hvtp.width(0.38, euclidian).output("hvtp.1", "hvtp.1 : min. hvtp width : 0.38um") +hvtp.space(0.38, euclidian).output("hvtp.2", "hvtp.2 : min. hvtp spacing : 0.38um") +log("END: 78/44 (hvtp)") + +# hvtr +log("START: 18/20 (htvr)") +hvtr.width(0.38, euclidian).output("hvtr.1", "hvtr.1 : min. hvtr width : 0.38um") +hvtr.separation(hvtp, 0.38, euclidian).output("hvtr.2", "hvtr.2 : min. hvtr spacing : 0.38um") +hvtr.and(hvtp).output("hvtr.2_a", "hvtr.2_a : hvtr must not overlap hvtp") +log("END: 18/20 (htvr)") + +# lvtn +log("START: 25/44 (lvtn)") +lvtn.width(0.38, euclidian).output("lvtn.1a", "lvtn.1a : min. lvtn width : 0.38um") +lvtn.space(0.38, euclidian).output("lvtn.2", "lvtn.2 : min. lvtn spacing : 0.38um") +log("END: 25/44 (lvtn)") + +# ncm +log("START: 92/44 (ncm)") +ncm.width(0.38, euclidian).output("ncm.1", "ncm.1 : min. ncm width : 0.38um") +ncm.space(0.38, euclidian).output("ncm.2a", "ncm.2a : min. ncm spacing : 0.38um") +log("END: 92/44 (ncm)") + +# diff-tap +log("START: 65/20 (diff)") +difftap = diff.or(tap) +diff_width = diff.rectangles.width(0.15, euclidian).polygons +diff_cross_areaid_ce = diff_width.edges.outside_part(areaid_ce).not(diff_width.outside(areaid_ce).edges) +diff_cross_areaid_ce.output("difftap.1", "difftap.1 : min. diff width across areaid:ce : 0.15um") +diff.outside(areaid_ce).width(0.15, euclidian).output("difftap.1_a", "difftap.1_a : min. diff width in periphery : 0.15um") +log("END: 65/20 (diff)") + +log("START: 65/44 (tap)") +tap_width = tap.rectangles.width(0.15, euclidian).polygons +tap_cross_areaid_ce = tap_width.edges.outside_part(areaid_ce).not(tap_width.outside(areaid_ce).edges) +tap_cross_areaid_ce.output("difftap.1_b", "difftap.1_b : min. tap width across areaid:ce : 0.15um") +tap.not(areaid_ce).width(0.15, euclidian).output("difftap.1_c", "difftap.1_c : min. tap width in periphery : 0.15um") +log("END: 65/44 (tap)") + +difftap.space(0.27, euclidian).output("difftap.3", "difftap.3 : min. difftap spacing : 0.27um") + +# tunm +log("START: 80/20 (tunm)") +tunm.width(0.41, euclidian).output("tunm.1", "tunm.1 : min. tunm width : 0.41um") +tunm.space(0.5, euclidian).output("tunm.2", "tunm.2 : min. tunm spacing : 0.5um") +log("END: 80/20 (tunm)") + +# poly +log("START: 66/20 (poly)") +poly.width(0.15, euclidian).output("poly.1a", "poly.1a : min. poly width : 0.15um") +poly.not(areaid_ce).space(0.21, euclidian).output("poly.2", "poly.2 : min. poly spacing : 0.21um") + + +# rpm +log("START: 86/20 (rpm)") +rpm.width(1.27, euclidian).output("rpm.1a", "rpm.1a : min. rpm width : 1.27um") +rpm.space(0.84, euclidian).output("rpm.2", "rpm.2 : min. rpm spacing : 0.84um") +log("END: 86/20 (rpm)") + +# urpm +log("START: 79/20 (urpm)") +urpm.width(1.27, euclidian).output("urpm.1a", "urpm.1a : min. rpm width : 1.27um") +urpm.space(0.84, euclidian).output("urpm.2", "urpm.2 : min. rpm spacing : 0.84um") +log("END: 79/20 (urpm)") + +# npc +log("START: 95/20 (npc)") +npc.width(0.27, euclidian).output("npc.1", "npc.1 : min. npc width : 0.27um") +npc.space(0.27, euclidian).output("npc.2", "npc.2 : min. npc spacing, should be manually merged if less than : 0.27um") +log("END: 95/20 (npc)") + +# nsdm +log("START: 93/44 (nsdm)") +not_sram_nsdm.outside(areaid_ce).width(0.38, euclidian).output("nsd.1", "nsd.1 : min. nsdm width : 0.38um") +not_sram_nsdm.not(areaid_ce).space(0.38, euclidian).output("nsd.2", "nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um") +log("END: 93/44 (nsdm)") + +# psdm +log("START: 94/20 (psdm)") +not_sram_psdm.outside(areaid_ce).width(0.38, euclidian).output("psd.1", "psd.1 : min. psdm width : 0.38um") +not_sram_psdm.not(areaid_ce).space(0.38, euclidian).output("psd.2", "psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um") +log("END: 94/20 (psdm)") + +# licon +log("START: 66/44 (licon)") +if option_SEAL + ringLICON = licon.drc(with_holes > 0) + rectLICON = licon.not(ringLICON) +else + rectLICON = licon +end +xfom = difftap.not(poly) +licon1ToXfom = licon.interacting(licon.and(xfom)) +licon1ToXfom_PERI = licon1ToXfom.not(areaid_ce) +rectLICON.non_rectangles.output("licon.1", "licon.1 : licon should be rectangle") +rectLICON.not(rpm.or(urpm)).edges.without_length(0.17).output("licon.1_a/b", "licon.1_a/b : minimum/maximum width of licon : 0.17um") +licon1ToXfom_PERI.separation(npc, 0.09, euclidian).output("licon.13", "licon.13 : min. difftap licon spacing to npc : 0.09um") +licon1ToXfom_PERI.and(npc).output("licon.13_a", "licon.13_a : licon of diffTap in periphery must not overlap npc") +licon.interacting(poly).and(licon.interacting(difftap)).output("licon.17", "licon.17 : Licons may not overlap both poly and (diff or tap)") +log("END: 66/44 (licon)") + +# CAPM +log("START: 89/44 (capm)") +capm.width(1.0, euclidian).output("capm.1", "capm.1 : min. capm width : 1.0um") +capm.space(0.84, euclidian).output("capm.2a", "capm.2a : min. capm spacing : 0.84um") +m3.interacting(capm).isolated(1.2, euclidian).output("capm.2b", "capm.2b : min. capm spacing : 1.2um") +(m3.interacting(capm)).isolated(1.2, euclidian).output("capm.2b_a", "capm.2b_a : min. spacing of m3_bot_plate : 1.2um") +capm.and(m3).enclosing(m3, 0.14, euclidian).output("capm.3", "capm.3 : min. capm and m3 enclosure of m3 : 0.14um") +m3.enclosing(capm, 0.14, euclidian).output("capm.3_a", "capm.3_a : min. m3 enclosure of capm : 0.14um") +capm.enclosing(via3, 0.14, euclidian).output("capm.4", "capm.4 : min. capm enclosure of via3 : 0.14um") +capm.separation(via3, 0.14, euclidian).output("capm.5", "capm.5 : min. capm spacing to via3 : 0.14um") +(m3.not_interacting(capm)).separation(capm, 0.5, euclidian).output("capm.11", "capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um") +log("END: 89/44 (capm)") + +# CAP2M +log("START: 97/44 (cap2m)") +cap2m.width(1.0, euclidian).output("cap2m.1", "cap2m.1 : min. cap2m width : 1.0um") +cap2m.space(0.84, euclidian).output("cap2m.2a", "cap2m.2a : min. cap2m spacing : 0.84um") +m4.interacting(cap2m).isolated(1.2, euclidian).output("cap2m.2b", "cap2m.2b : min. cap2m spacing : 1.2um") +(m4.interacting(cap2m)).isolated(1.2, euclidian).output("cap2m.2b_a", "cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um") +cap2m.and(m4).enclosing(m4, 0.14, euclidian).output("cap2m.3", "cap2m.3 : min. m4 enclosure of cap2m : 0.14um") +m4.enclosing(cap2m, 0.14, euclidian).output("cap2m.3_a", "cap2m.3_a : min. m4 enclosure of cap2m : 0.14um") +cap2m.enclosing(via4, 0.2, euclidian).output("cap2m.4", "cap2m.4 : min. cap2m enclosure of via4 : 0.14um") +cap2m.separation(via4, 0.2, euclidian).output("cap2m.5", "cap2m.5 : min. cap2m spacing to via4 : 0.14um") +(m4.not_interacting(cap2m)).separation(cap2m, 0.5, euclidian).output("cap2m.11", "cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um") +log("END: 97/44 (cap2m)") +end #option_FEOL + +if option_BEOL +log("option_BEOL section") + +# li +log("START: 67/20 (li)") +linotace = li.not(li.interacting(areaid_ce)) +linotace.width(0.17, euclidian).output("li.1", "li.1 : min. li width : 0.17um") +# This rule is taking a long time in some slots +linotace.edges.space(0.17, euclidian).output("li.3", "li.3 : min. li spacing : 0.17um") +licon_peri = licon.not(areaid_ce) +li_edges_with_less_enclosure = li.enclosing(licon_peri, 0.08, projection).second_edges +error_corners = li_edges_with_less_enclosure.width(angle_limit(100.0), 1.dbu) +li_interact = licon_peri.interacting(error_corners.polygons(1.dbu)) +li_interact.output("li.5", "li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um") +linotace.with_area(nil, 0.0561).output("li.6", "li.6 : min. li area : 0.0561um²") +log("END: 67/20 (li)") + +# ct +log("START: 67/44 (mcon)") +mconnotace = mcon.not(areaid_ce) +if option_SEAL + ringMCON = mcon.drc(with_holes > 0) + rectMCON = mcon.not(ringMCON) +else + rectMCON = mcon +end +rectMCON_peri = rectMCON.not(areaid_ce) +rectMCON.non_rectangles.output("ct.1", "ct.1: non-ring mcon should be rectangular") +# rectMCON_peri.edges.without_length(0.17).output("ct.1_a/b", "ct.1_a/b : minimum/maximum width of mcon : 0.17um") +rectMCON_peri.drc(width < 0.17).output("ct.1_a", "ct.1_a : minimum width of mcon : 0.17um") +rectMCON_peri.drc(length > 0.17).output("ct.1_b", "ct.1_b : maximum length of mcon : 0.17um") +mcon.space(0.19, euclidian).output("ct.2", "ct.2 : min. mcon spacing : 0.19um") +if option_SEAL + ringMCON.width(0.17, euclidian).output("ct.3", "ct.3 : min. width of ring-shaped mcon : 0.17um") + ringMCON.drc(width >= 0.175).output("ct.3_a", "ct.3_a : max. width of ring-shaped mcon : 0.175um") + ringMCON.not(areaid_sl).output("ct.3_b", "ct.3_b: ring-shaped mcon must be enclosed by areaid_sl") +end +mconnotace.not(li).output("ct.4", "ct.4 : mcon should covered by li") +log("END: 67/44 (mcon)") + +# m1 +log("START: 68/20 (m1)") +m1.width(0.14, euclidian).output("m1.1", "m1.1 : min. m1 width : 0.14um") +huge_m1 = m1.sized(-1.5).sized(1.5).snap(0.005) & m1 +non_huge_m1 = m1.edges - huge_m1 +huge_m1 = huge_m1.edges.outside_part(m1.merged) + +non_huge_m1.space(0.14, euclidian).output("m1.2", "m1.2 : min. m1 spacing : 0.14um") + +(huge_m1.separation(non_huge_m1, 0.28, euclidian) + huge_m1.space(0.28, euclidian)).output("m1.3ab", "m1.3ab : min. 3um.m1 spacing m1 : 0.28um") + +#not_in_cell6 = layout(source.cell_obj).select("-s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b", "-s8fpls_pl8", "-s8fs_cmux4_fm") +not_in_cell6 = layout(source.cell_obj).select("-s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b", "-s8fs_cmux4_fm") +not_in_cell6_m1 = not_in_cell6.input(m1_wildcard) + +not_in_cell6_m1.enclosing(mconnotace, 0.03, euclidian).output("791_m1.4", "791_m1.4 : min. m1 enclosure of mcon : 0.03um") +mconnotace.not(m1).output("m1.4", "m1.4 : mcon periphery must be enclosed by m1") +in_cell6 = layout(source.cell_obj).select("-*", "+s8cell_ee_plus_sseln_a", "+s8cell_ee_plus_sseln_b", "+s8cell_ee_plus_sselp_a", "+s8cell_ee_plus_sselp_b", "+s8fpls_pl8", "+s8fs_cmux4_fm") +in_cell6_m1 = in_cell6.input(m1_wildcard) +in_cell6_m1.enclosing(mcon, 0.005, euclidian).output("m1.4a", "m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um") + +in_cell6_m1.not(m1).output('m1.4a_a', 'm1.4a_a : mcon periph must be enclosed by met1 for specific cells') + +m1.with_area(0..0.083).output("m1.6", "m1.6 : min. m1 area : 0.083um²") + +m1.holes.with_area(0..0.14).output("m1.7", "m1.7 : min. m1 with holes area : 0.14um²") +if option_FLOATING_MET + m1.not_interacting(via.or(mcon)).output("m1.x", "floating met1, must interact with via1") +end + +if backend_flow = AL + #Could flag false positive, fix would be to add .rectangles for m1 + mconnotace_edges_with_less_enclosure_m1 = m1.enclosing(mconnotace, 0.06, projection).second_edges + error_corners_m1 = mconnotace_edges_with_less_enclosure_m1.width(angle_limit(100.0), 1.dbu) + mconnotace_interact_m1 = mconnotace.interacting(error_corners_m1.polygons(1.dbu)) + mconnotace_interact_m1.output("m1.5", "m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um") +end +log("END: 68/20 (m1)") + +# via +log("START: 68/44 (via)") +if backend_flow = AL + if option_SEAL + ringVIA = via.drc(with_holes > 0) + rectVIA = via.not(ringVIA) + else + rectVIA = via + end + + via_not_mt = rectVIA.not(areaid_mt) + + via_not_mt.non_rectangles.output("via.1a", "via.1a : via outside of moduleCut should be rectangular") + via_not_mt.width(0.15, euclidian).output("via.1a_a", "via.1a_a : min. width of via outside of moduleCut : 0.15um") + # via_not_mt.edges.without_length(nil, 0.15 + 1.dbu).output("via.1a_b", "via.1a_b : maximum length of via : 0.15um") + via_not_mt.drc(length > 0.15).output("via.1a_b", "via.1a_b : maximum length of via : 0.15um") + + via.space(0.17, euclidian).output("via.2", "via.2 : min. via spacing : 0.17um") + + if option_SEAL + ringVIA.width(0.2, euclidian).output("via.3", "via.3 : min. width of ring-shaped via : 0.2um") + ringVIA.drc(width >= 0.205).output("via.3_a", "via.3_a : max. width of ring-shaped via : 0.205um") + ringVIA.not(areaid_sl).output("via.3_b", "via.3_b: ring-shaped via must be enclosed by areaid_sl") + end + + m1.edges.enclosing(rectVIA.drc(width == 0.15), 0.055, euclidian).output("via.4a", "via.4a : min. m1 enclosure of 0.15um via : 0.055um") + rectVIA.squares.drc(width == 0.15).not(m1).output("via.4a_a", "via.4a_a : 0.15um via must be enclosed by met1") + + via1_edges_with_less_enclosure_m1 = m1.edges.enclosing(rectVIA.drc(width == 0.15), 0.085, projection).second_edges + error_corners_via1 = via1_edges_with_less_enclosure_m1.width(angle_limit(100.0), 1.dbu) + via2_interact = via.interacting(error_corners_via1.polygons(1.dbu)) + via2_interact.output("via.5a", "via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um") + +end +log("END: 68/44 (via)") + +# m2 +log("START: 69/20 (m2)") +m2.width(0.14, euclidian).output("m2.1", "m2.1 : min. m2 width : 0.14um") + +huge_m2 = m2.sized(-1.5).sized(1.5).snap(0.005) & m2 +non_huge_m2 = m2.edges - huge_m2 +huge_m2 = huge_m2.edges.outside_part(m2.merged) +via_outside_periphery = via.not(areaid_ce) + +non_huge_m2.space(0.14, euclidian).output("m2.2", "m2.2 : min. m2 spacing : 0.14um") + +(huge_m2.separation(non_huge_m2, 0.28, euclidian) + huge_m2.space(0.28, euclidian)).output("m2.3ab", "m2.3ab : min. 3um.m2 spacing m2 : 0.28um") + +m2.with_area(0..0.0676).output("m2.6", "m2.6 : min. m2 area : 0.0676um²") +m2.holes.with_area(0..0.14).output("m2.7", "m2.7 : min. m2 holes area : 0.14um²") +if option_FLOATING_MET + m2.not_interacting(via.or(via2)).output("m2.x", "floating met2, must interact with via1 or via2") +end +if backend_flow = AL + m2.enclosing(via_outside_periphery, 0.055, euclidian).output("m2.4", "m2.4 : min. m2 enclosure of via : 0.055um") + via_outside_periphery.not(m2).output("m2.4_a", "m2.4_a : via in periphery must be enclosed by met2") + via_edges_with_less_enclosure_m2 = m2.enclosing(via, 0.085, projection).second_edges + error_corners = via_edges_with_less_enclosure_m2.width(angle_limit(100.0), 1.dbu) + via_interact = via.interacting(error_corners.polygons(1.dbu)) + via_interact.output("m2.5", "m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um") + +end +log("END: 69/20 (m2)") + +# via2 +log("START: 69/44 (via2)") +if backend_flow = AL + if option_SEAL + ringVIA2 = via2.drc(with_holes > 0) + rectVIA2 = via2.not(ringVIA2) + else + rectVIA2 = via2 + end + + via2_not_mt = rectVIA2.not(areaid_mt) + via2_not_mt.non_rectangles.output("via2.1a", "via2.1a : via2 outside of moduleCut should be rectangular") + via2_not_mt.width(0.2, euclidian).output("via2.1a_a", "via2.1a_a : min. width of via2 outside of moduleCut : 0.2um") + via2_not_mt.edges.without_length(nil, 0.2 + 1.dbu).output("via2.1a_b", "via2.1a_b : maximum length of via2 : 0.2um") + via2.space(0.2, euclidian).output("via2.2", "via2.2 : min. via2 spacing : 0.2um") + + if option_SEAL + ringVIA2.width(0.2, euclidian).output("via2.3", "via2.3 : min. width of ring-shaped via2 : 0.2um") + ringVIA2.drc(width >= 0.205).output("via2.3_a", "via2.3_a : max. width of ring-shaped via2 : 0.205um") + ringVIA2.not(areaid_sl).output("via2.3_b", "via2.3_b: ring-shaped via2 must be enclosed by areaid_sl") + end + + m2.enclosing(via2, 0.04, euclidian).output("via2.4", "via2.4 : min. m2 enclosure of via2 : 0.04um") + via2.not(m2).output("via2.4_a", "via2.4_a : via must be enclosed by met2") + + via2_edges_with_less_enclosure = m2.enclosing(via2, 0.085, projection).second_edges + error_corners = via2_edges_with_less_enclosure.width(angle_limit(100.0), 1.dbu) + via2_interact = via2.interacting(error_corners.polygons(1.dbu)) + via2_interact.output("via2.5", "via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um") +end +log("END: 69/44 (via2)") + +# m3 +log("START: 70/20 (m3)") +m3.width(0.3, euclidian).output("m3.1", "m3.1 : min. m3 width : 0.3um") + +huge_m3 = m3.sized(-1.5).sized(1.5).snap(0.005) & m3 +non_huge_m3 = m3.edges - huge_m3 +huge_m3 = huge_m3.edges.outside_part(m3.merged) + +non_huge_m3.space(0.3, euclidian).output("m3.2", "m3.2 : min. m3 spacing : 0.3um") + +m3.with_area(0..0.240).output("m3.6", "m3.6 : min. m3 area : 0.240um²") + +(huge_m3.separation(non_huge_m3, 0.4, euclidian) + huge_m3.space(0.4, euclidian)).output("m3.3cd", "m3.3cd : min. 3um.m3 spacing m3 : 0.4um") +if option_FLOATING_MET + m3.not_interacting(via2.or(via3)).output("m3.x", "floating met3, must interact with via2 or via3") +end +if backend_flow = AL + m3.enclosing(via2, 0.065, euclidian).output("m3.4", "m3.4 : min. m3 enclosure of via2 : 0.065um") + via2.not(m3).output("m3.4_a", "m3.4_a : via2 must be enclosed by met3") +end +log("END: 70/20 (m3)") + +# via3 +log("START: 70/44 (via3)") +if backend_flow = AL + if option_SEAL + ringVIA3 = via3.drc(with_holes > 0) + rectVIA3 = via3.not(ringVIA3) + else + rectVIA3 = via3 + end + + via3_not_mt = rectVIA3.not(areaid_mt) + via3_not_mt.non_rectangles.output("via3.1", "via3.1 : via3 outside of moduleCut should be rectangular") + via3_not_mt.width(0.2, euclidian).output("via3.1_a", "via3.1_a : min. width of via3 outside of moduleCut : 0.2um") + via3_not_mt.edges.without_length(nil, 0.2 + 1.dbu).output("via3.1_b", "via3.1_b : maximum length of via3 : 0.2um") + + via3.space(0.2, euclidian).output("via3.2", "via3.2 : min. via3 spacing : 0.2um") + m3.enclosing(via3, 0.06, euclidian).output("via3.4", "via3.4 : min. m3 enclosure of via3 : 0.06um") + rectVIA3.not(m3).output("via3.4_a", "via3.4_a : non-ring via3 must be enclosed by met3") + + via_edges_with_less_enclosure = m3.enclosing(via3, 0.09, projection).second_edges + error_corners = via_edges_with_less_enclosure.width(angle_limit(100.0), 1.dbu) + via3_interact = via3.interacting(error_corners.polygons(1.dbu)) + via3_interact.output("via3.5", "via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um") +end +log("END: 70/44 (via3)") + +# m4 +log("START: 71/20 (m4)") +m4.width(0.3, euclidian).output("m4.1", "m4.1 : min. m4 width : 0.3um") + +huge_m4 = m4.sized(-1.5).sized(1.5).snap(0.005) & m4 +non_huge_m4 = m4.edges - huge_m4 +huge_m4 = huge_m4.edges.outside_part(m4.merged) + +non_huge_m4.space(0.3, euclidian).output("m4.2", "m4.2 : min. m4 spacing : 0.3um") + +m4.with_area(0..0.240).output("m4.4a", "m4.4a : min. m4 area : 0.240um²") + +(huge_m4.separation(non_huge_m4, 0.4, euclidian) + huge_m4.space(0.4, euclidian)).output("m4.5ab", "m4.5ab : min. 3um.m4 spacing m4 : 0.4um") +if option_FLOATING_MET + m4.not_interacting(via3.or(via4)).output("m4.x", "floating met3, must interact with via3 or via4") +end +if backend_flow = AL + m4.enclosing(via3, 0.065, euclidian).output("m4.3", "m4.3 : min. m4 enclosure of via3 : 0.065um") + via3.not(m4).output("m4.3_a", "m4.3_a : via3 must be enclosed by met4") +end +log("END: 71/20 (m4)") + +# via4 +log("START: 71/44 (via4)") +if option_SEAL + ringVIA4 = via4.drc(with_holes > 0) + rectVIA4 = via4.not(ringVIA4) +else + rectVIA4 = via4 +end + +via4_not_mt = rectVIA4.not(areaid_mt) +via4_not_mt.non_rectangles.output("via4.1", "via4.1 : via4 outside of moduleCut should be rectangular") +rectVIA4.width(0.8, euclidian).output("via4.1_a", "via4.1_a : min. width of via4 outside of moduleCut : 0.8um") +rectVIA4.drc(length > 0.8).output("via4.1_b", "via4.1_b : maximum length of via4 : 0.8um") + +via4.space(0.8, euclidian).polygons.output("via4.2", "via4.2 : min. via4 spacing : 0.8um") + +if option_SEAL + ringVIA4.width(0.8, euclidian).output("via4.3", "via4.3 : min. width of ring-shaped via4 : 0.8um") + ringVIA4.drc(width >= 0.805).output("via4.3_a", "via4.3_a : max. width of ring-shaped via4 : 0.805um") + ringVIA4.not(areaid_sl).output("via4.3_b", "via4.3_b: ring-shaped via4 must be enclosed by areaid_sl") +end + +m4.enclosing(via4, 0.19, euclidian).output("via4.4", "via4.4 : min. m4 enclosure of via4 : 0.19um") +rectVIA4.not(m4).output("via4.4_a", "via4.4_a : m4 must enclose all via4") +log("END: 71/44 (via4)") + +# m5 +log("START: 72/20 (m5)") +m5.width(1.6, euclidian).output("m5.1", "m5.1 : min. m5 width : 1.6um") + +m5.space(1.6, euclidian).output("m5.2", "m5.2 : min. m5 spacing : 1.6um") + +m5.enclosing(via4, 0.31, euclidian).output("m5.3", "m5.3 : min. m5 enclosure of via4 : 0.31um") +via4.not(m5).output("m5.3_a", "m5.3_a : via must be enclosed by m5") +if option_FLOATING_MET + m5.not_interacting(via4).output("m5.x", "floating met5, must interact with via4") +end +m5.with_area(0..4.0).output("m5.4", "m5.4 : min. m5 area : 4.0um²") +log("END: 72/20 (m5)") + +# pad +log("START: 76/20 (pad)") +pad.space(1.27, euclidian).output("pad.2", "pad.2 : min. pad spacing : 1.27um") +log("END: 76/20 (pad)") + +end #option_BEOL + +if option_FEOL +log("option_FEOL section") + +# hvi +log("START: 75/20 (hvi)") +hvi_peri = hvi.not(areaid_ce) +hvi_peri.width(0.6, euclidian).output("hvi.1", "hvi.1 : min. hvi width : 0.6um") +hvi_peri.space(0.7, euclidian).output("hvi.2a", "hvi.2a : min. hvi spacing : 0.7um") +log("END: 75/20 (hvi)") + +# hvntm +log("START: 125/20 (hvntm)") +hvntm_peri = hvntm.not(areaid_ce) +hvntm_peri.width(0.7, euclidian).output("hvntm.1", "hvntm.1 : min. hvntm width : 0.7um") +hvntm_peri.space(0.7, euclidian).output("hvntm.2", "hvntm.2 : min. hvntm spacing : 0.7um") +log("END: 125/20 (hvntm)") + +end #option_FEOL + + +if option_OFFGRID +log("option_OFFGRID-ANGLES section") + +dnwell.ongrid(0.005).output("dnwell_option_OFFGRID", "x.1b : option_OFFGRID vertex on dnwell") +dnwell.with_angle(0 .. 45).output("dnwell_angle", "x.3a : non 45 degree angle dnwell") +nwell.ongrid(0.005).output("nwell_option_OFFGRID", "x.1b : option_OFFGRID vertex on nwell") +nwell.with_angle(0 .. 45).output("nwell_angle", "x.3a : non 45 degree angle nwell") +pwbm.ongrid(0.005).output("pwbm_option_OFFGRID", "x.1b : option_OFFGRID vertex on pwbm") +pwbm.with_angle(0 .. 45).output("pwbm_angle", "x.3a : non 45 degree angle pwbm") +pwde.ongrid(0.005).output("pwde_option_OFFGRID", "x.1b : option_OFFGRID vertex on pwde") +pwde.with_angle(0 .. 45).output("pwde_angle", "x.3a : non 45 degree angle pwde") +hvtp.ongrid(0.005).output("hvtp_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvtp") +hvtp.with_angle(0 .. 45).output("hvtp_angle", "x.3a : non 45 degree angle hvtp") +hvtr.ongrid(0.005).output("hvtr_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvtr") +hvtr.with_angle(0 .. 45).output("hvtr_angle", "x.3a : non 45 degree angle hvtr") +lvtn.ongrid(0.005).output("lvtn_option_OFFGRID", "x.1b : option_OFFGRID vertex on lvtn") +lvtn.with_angle(0 .. 45).output("lvtn_angle", "x.3a : non 45 degree angle lvtn") +ncm.ongrid(0.005).output("ncm_option_OFFGRID", "x.1b : option_OFFGRID vertex on ncm") +ncm.with_angle(0 .. 45).output("ncm_angle", "x.3a : non 45 degree angle ncm") +diff.ongrid(0.005).output("diff_option_OFFGRID", "x.1b : option_OFFGRID vertex on diff") +tap.ongrid(0.005).output("tap_option_OFFGRID", "x.1b : option_OFFGRID vertex on tap") +diff.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("diff_angle", "x.2 : non 90 degree angle diff") +diff.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("diff_angle", "x.2c : non 45 degree angle diff") +tap.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("tap_angle", "x.2 : non 90 degree angle tap") +tap.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("tap_angle", "x.2c : non 45 degree angle tap") +tunm.ongrid(0.005).output("tunm_option_OFFGRID", "x.1b : option_OFFGRID vertex on tunm") +tunm.with_angle(0 .. 45).output("tunm_angle", "x.3a : non 45 degree angle tunm") +poly.ongrid(0.005).output("poly_option_OFFGRID", "x.1b : option_OFFGRID vertex on poly") +poly.with_angle(0 .. 90).output("poly_angle", "x.2 : non 90 degree angle poly") +rpm.ongrid(0.005).output("rpm_option_OFFGRID", "x.1b : option_OFFGRID vertex on rpm") +rpm.with_angle(0 .. 45).output("rpm_angle", "x.3a : non 45 degree angle rpm") +npc.ongrid(0.005).output("npc_option_OFFGRID", "x.1b : option_OFFGRID vertex on npc") +npc.with_angle(0 .. 45).output("npc_angle", "x.3a : non 45 degree angle npc") +nsdm.ongrid(0.005).output("nsdm_option_OFFGRID", "x.1b : option_OFFGRID vertex on nsdm") +nsdm.with_angle(0 .. 45).output("nsdm_angle", "x.3a : non 45 degree angle nsdm") +psdm.ongrid(0.005).output("psdm_option_OFFGRID", "x.1b : option_OFFGRID vertex on psdm") +psdm.with_angle(0 .. 45).output("psdm_angle", "x.3a : non 45 degree angle psdm") +licon.ongrid(0.005).output("licon_option_OFFGRID", "x.1b : option_OFFGRID vertex on licon") +licon.with_angle(0 .. 90).output("licon_angle", "x.2 : non 90 degree angle licon") +li.ongrid(0.005).output("li_option_OFFGRID", "x.1b : option_OFFGRID vertex on li") +li.with_angle(0 .. 45).output("li_angle", "x.3a : non 45 degree angle li") +mcon.ongrid(0.005).output("ct_option_OFFGRID", "x.1b : option_OFFGRID vertex on mcon") +mcon.with_angle(0 .. 90).output("ct_angle", "x.2 : non 90 degree angle mcon") +vpp.ongrid(0.005).output("vpp_option_OFFGRID", "x.1b : option_OFFGRID vertex on vpp") +vpp.with_angle(0 .. 45).output("vpp_angle", "x.3a : non 45 degree angle vpp") +m1.ongrid(0.005).output("m1_option_OFFGRID", "x.1b : option_OFFGRID vertex on m1") +m1.with_angle(0 .. 45).output("m1_angle", "x.3a : non 45 degree angle m1") +via.ongrid(0.005).output("via_option_OFFGRID", "x.1b : option_OFFGRID vertex on via") +via.with_angle(0 .. 90).output("via_angle", "x.2 : non 90 degree angle via") +m2.ongrid(0.005).output("m2_option_OFFGRID", "x.1b : option_OFFGRID vertex on m2") +m2.with_angle(0 .. 45).output("m2_angle", "x.3a : non 45 degree angle m2") +via2.ongrid(0.005).output("via2_option_OFFGRID", "x.1b : option_OFFGRID vertex on via2") +via2.with_angle(0 .. 90).output("via2_angle", "x.2 : non 90 degree angle via2") +m3.ongrid(0.005).output("m3_option_OFFGRID", "x.1b : option_OFFGRID vertex on m3") +m3.with_angle(0 .. 45).output("m3_angle", "x.3a : non 45 degree angle m3") +via3.ongrid(0.005).output("via3_option_OFFGRID", "x.1b : option_OFFGRID vertex on via3") +via3.with_angle(0 .. 90).output("via3_angle", "x.2 : non 90 degree angle via3") +nsm.ongrid(0.005).output("nsm_option_OFFGRID", "x.1b : option_OFFGRID vertex on nsm") +nsm.with_angle(0 .. 45).output("nsm_angle", "x.3a : non 45 degree angle nsm") +m4.ongrid(0.005).output("m4_option_OFFGRID", "x.1b : option_OFFGRID vertex on m4") +m4.with_angle(0 .. 45).output("m4_angle", "x.3a : non 45 degree angle m4") +via4.ongrid(0.005).output("via4_option_OFFGRID", "x.1b : option_OFFGRID vertex on via4") +via4.with_angle(0 .. 90).output("via4_angle", "x.2 : non 90 degree angle via4") +m5.ongrid(0.005).output("m5_option_OFFGRID", "x.1b : option_OFFGRID vertex on m5") +m5.with_angle(0 .. 45).output("m5_angle", "x.3a : non 45 degree angle m5") +pad.ongrid(0.005).output("pad_option_OFFGRID", "x.1b : option_OFFGRID vertex on pad") +pad.with_angle(0 .. 45).output("pad_angle", "x.3a : non 45 degree angle pad") +mf.ongrid(0.005).output("mf_option_OFFGRID", "x.1b : option_OFFGRID vertex on mf") +mf.with_angle(0 .. 90).output("mf_angle", "x.2 : non 90 degree angle mf") +hvi.ongrid(0.005).output("hvi_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvi") +hvi.with_angle(0 .. 45).output("hvi_angle", "x.3a : non 45 degree angle hvi") +hvntm.ongrid(0.005).output("hvntm_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvntm") +hvntm.with_angle(0 .. 45).output("hvntm_angle", "x.3a : non 45 degree angle hvntm") +vhvi.ongrid(0.005).output("vhvi_option_OFFGRID", "x.1b : option_OFFGRID vertex on vhvi") +vhvi.with_angle(0 .. 45).output("vhvi_angle", "x.3a : non 45 degree angle vhvi") +uhvi.ongrid(0.005).output("uhvi_option_OFFGRID", "x.1b : option_OFFGRID vertex on uhvi") +uhvi.with_angle(0 .. 45).output("uhvi_angle", "x.3a : non 45 degree angle uhvi") +pwell_rs.ongrid(0.005).output("pwell_rs_option_OFFGRID", "x.1b : option_OFFGRID vertex on pwell_rs") +pwell_rs.with_angle(0 .. 45).output("pwell_rs_angle", "x.3a : non 45 degree angle pwell_rs") +areaid_re.ongrid(0.005).output("areaid_re_option_OFFGRID", "x.1b : option_OFFGRID vertex on areaid.re") + +end #option_OFFGRID +logger.info(" ") +logger.info("Cell exclusion list:") +logger.info(" rule | cell") +logger.info(" nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram") +logger.info(" nsd.1 | sram") +logger.info(" nsd.2 | sram") +logger.info(" psd.1 | sram") +logger.info(" psd.2 | sram") +logger.info(" ") +logger.info("release #{release}") diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/drc_sky130.lydrc b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/drc_sky130.lydrc new file mode 100755 index 000000000..68a49f4bc --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/drc_sky130.lydrc @@ -0,0 +1,878 @@ + + + + + drc + + + + false + false + + true + drc_scripts + tools_menu.drc.end + dsl + drc-dsl-xml + # +# DRC for SKY130 according to : +# https://skywater-pdk.readthedocs.io/en/latest/rules/periphery.html +# https://skywater-pdk.readthedocs.io/en/latest/rules/layers.html +# +# Distributed under GNU GPLv3: https://www.gnu.org/licenses/ +# +# History : +# 2020-10-04 : v1.0 : initial release +# +########################################################################################## +tstart = Time.now + +# optionnal for a batch launch : klayout -b -rd input=my_layout.gds -rd report=sky130_drc.txt -r drc_sky130.drc +if $input + source($input) +end + +if $report +# report($report) + report("SKY130 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), $report)) +else + report("SKY130 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "sky130_drc.txt")) +end + +AL = true # do not change +CU = false # do not change +# choose betwen only one of AL or CU back-end flow here : +backend_flow = AL + +# enable / disable rule groups +FEOL = true # front-end-of-line checks +BEOL = true # back-end-of-line checks +OFFGRID = true # manufacturing grid/angle checks + +# klayout setup +######################## +# use a tile size of 1mm - not used in deep mode- +tiles(1000.um) +# use a tile border of 10 micron: +tile_borders(1.um) +#no_borders + +# hierachical +deep + +# use 4 cpu cores +threads(4) +# if more inof is needed, set true +verbose(false) + +# layers definitions +######################## +diff = input(65, 20) +tap = polygons(65, 44) +nwell = polygons(64, 20) +dnwell = polygons(64, 18) +pwbm = polygons(19, 44) +pwde = polygons(124, 20) +natfet = polygons(124, 21) +hvtr = polygons(18, 20) +hvtp = polygons(78, 44) +ldntm = polygons(11, 44) +hvi = polygons(75, 20) +tunm = polygons(80, 20) +lvtn = polygons(125, 44) +poly = polygons(66, 20) +hvntm = polygons(125, 20) +nsdm = polygons(93, 44) +psdm = polygons(94, 20) +rpm = polygons(86, 20) +urpm = polygons(79, 20) +npc = polygons(95, 20) +licon = polygons(66, 44) +li = input(67, 20) +mcon = polygons(67, 44) +m1 = polygons(68, 20) +via = polygons(68, 44) +m2 = polygons(69, 20) +via2 = polygons(69, 44) +m3 = polygons(70, 20) +via3 = polygons(70, 44) +m4 = polygons(71, 20) +via4 = polygons(71, 44) +m5 = polygons(72, 20) +pad = polygons(76, 20) +nsm = polygons(61, 20) +capm = polygons(89, 44) +cap2m = polygons(97, 44) +vhvi = polygons(74, 21) +uhvi = polygons(74, 22) +npn = polygons(82, 20) +inductor = polygons(82, 24) +vpp = polygons(82, 64) +pnp = polygons(82, 44) +lvs_prune = polygons(84, 44) +ncm = polygons(92, 44) +padcenter = polygons(81, 20) +mf = polygons(76, 44) +areaid_sl = polygons(81, 1) +areaid_ce = polygons(81, 2) +areaid_fe = polygons(81, 3) +areaid_sc = polygons(81, 4) +areaid_sf = polygons(81, 6) +areaid_sw = polygons(81, 7) +areaid_sr = polygons(81, 8) +areaid_mt = polygons(81, 10) +areaid_dt = polygons(81, 11) +areaid_ft = polygons(81, 12) +areaid_ww = polygons(81, 13) +areaid_ld = polygons(81, 14) +areaid_ns = polygons(81, 15) +areaid_ij = polygons(81, 17) +areaid_zr = polygons(81, 18) +areaid_ed = polygons(81, 19) +areaid_de = polygons(81, 23) +areaid_rd = polygons(81, 24) +areaid_dn = polygons(81, 50) +areaid_cr = polygons(81, 51) +areaid_cd = polygons(81, 52) +areaid_st = polygons(81, 53) +areaid_op = polygons(81, 54) +areaid_en = polygons(81, 57) +areaid_en20 = polygons(81, 58) +areaid_le = polygons(81, 60) +areaid_hl = polygons(81, 63) +areaid_sd = polygons(81, 70) +areaid_po = polygons(81, 81) +areaid_it = polygons(81, 84) +areaid_et = polygons(81, 101) +areaid_lvt = polygons(81, 108) +areaid_re = polygons(81, 125) +areaid_ag = polygons(81, 79) +poly_rs = polygons(66, 13) +diff_rs = polygons(65, 13) +pwell_rs = polygons(64, 13) +li_rs = polygons(67, 13) +cfom = polygons(22, 20) + + +# Define a new custom function that selects polygons by their number of holes: +# It will return a new layer containing those polygons with min to max holes. +# max can be nil to omit the upper limit. +class DRC::DRCLayer + def with_holes(min, max) + new_data = RBA::Region::new + self.data.each do |p| + if p.holes >= (min || 0) && (!max || p.holes <= max) + new_data.insert(p) + end + end + DRC::DRCLayer::new(@engine, new_data) + end +end + +# DRC section +######################## +info("DRC section") + +if FEOL +info("FEOL section") +gate = diff & poly + +# dnwell +dnwell.width(3.0, euclidian).output("dnwell.2", "dnwell.2 : min. dnwell width : 3.0um") +dnwell.not(uhvi).not(areaid_po).isolated(6.3, euclidian).output("dnwell.3", "dnwell.3 : min. dnwell spacing : 6.3um") +dnwell.and(pnp).output("dnwell.4", "dnwell.4 : dnwell must not overlap pnp") +dnwell.and(psdm).edges.not(psdm.edges).output("dnwell.5", "p+ must not straddle dnwell") +# dnwell.6 rue not coded + +# nwell +nwell.width(0.84, euclidian).output("nwell.1", "nwell.1 : min. nwell width : 0.84um") +nwell.space(1.27, euclidian).output("nwell.2a", "nwell.2a : min. nwell spacing (merged if less) : 1.27um") +# rule nwell.4 is suitable for digital cells +#nwell.not(uhvi).not(areaid_en20).not_interacting(tap.and(licon).and(li)).output("nwell.4", "nwell4 : all nwell exempt inside uhvi must contain a n+tap") +nwell.enclosing(dnwell.not(uhvi).not(areaid_po), 0.4, euclidian).output("nwell.5", "nwell.5 : min. nwell enclosing dnwell exempt unside uhvi : 0.4um") +dnwell.enclosing(nwell.not(uhvi), 1.03, euclidian).output("nwell.6", "nwell.6 : min. dnwell enclosing nwell exempt unside uhvi : 1.03um") +dnwell.separation(nwell, 4.5, euclidian).output("nwell.7", "nwell.7 : min. dnwell separation nwell : 4.5um") + +# pwbm +pwbm.not(uhvi).output("pwbm", "pwbm must be inside uhvi") +dnwell.and(uhvi).edges.not(pwbm).output("pwbm.4", "pwbm.4 : dnwell inside uhvi must be enclosed by pwbm") + +# pwde +pwde.not(pwbm).output("pwdem.3", "pwdem.3 : pwde must be inside pwbm") +pwde.not(uhvi).output("pwdem.4", "pwdem.4 : pwde must be inside uhvi") +pwde.not(dnwell).output("pwdem.5", "pwdem.5 : pwde must be inside dnwell") + +# hvtp +#hvtp.not(nwell).output("hvtp", "hvtp must inside nwell") +hvtp.width(0.38, euclidian).output("hvtp.1", "hvtp.1 : min. hvtp width : 0.38um") +hvtp.space(0.38, euclidian).output("hvtp.2", "hvtp.2 : min. hvtp spacing : 0.38um") +hvtp.enclosing(gate.and(psdm), 0.18, euclidian).output("hvtp.3", "hvtp.3 : min. hvtp enclosure of pfet gate : 0.18um") +hvtp.separation(gate.and(psdm), 0.18, euclidian).output("hvtp.4", "hvtp.4 : min. hvtp spacing pfet gate: 0.18um") +hvtp.with_area(0..0.265).output("hvtp.5", "hvtp.5 : min. hvtp area : 0.265um²") + +# hvtr +hvtr.width(0.38, euclidian).output("hvtr.1", "hvtr.1 : min. hvtr width : 0.38um") +hvtr.isolated(0.38, euclidian).output("hvtr.2", "hvtr.2 : min. hvtr spacing : 0.38um") + +# lvtn +lvtn.width(0.38, euclidian).output("lvtn.1", "lvtn.1 : min. lvtn width : 0.38um") +lvtn.space(0.38, euclidian).output("lvtn.2", "lvtn.2 : min. lvtn spacing : 0.38um") +lvtn.separation(diff.and(poly).not(uhvi), 0.18, euclidian).output("lvtn.3a", "lvtn.3a : min. lvtn spacing to gate : 0.18um") +lvtn.separation(diff.and(nwell).not(poly), 0.235, projection).output("lvtn.3b", "lvtn.3b : min. lvtn spacing to pfet s/d : 0.18um") +lvtn.enclosing(gate.not(uhvi), 0.18, euclidian).output("lvtn.4b", "lvtn.4b : min. lvtn enclosing to gate : 0.18um") +lvtn.separation(hvtp, 0.38, euclidian).output("lvtn.9", "lvtn.9 : min. lvtn spacing hvtp : 0.38um") +nwell.not_interacting(gate.and(nwell.not(hvi).not(areaid_ce))).enclosing(lvtn.not(uhvi), 0.18, euclidian).polygons.without_area(0).output("lvtn.4b", "lvtn.4b : min. lvtn enclosure of gate : 0.18um") +lvtn.separation(nwell.inside(areaid_ce), 0.38, euclidian).output("lvtn.12", "lvtn.12 : min. lvtn spacing nwell inside areaid.ce : 0.38um") +lvtn.with_area(0..0.265).output("lvtn.13", "lvtn.13 : min. lvtn area : 0.265um²") + +# ncm +ncm.and(tap.and(nwell).or(diff.not(nwell))).output("ncm.x.3", "ncm.x.3 : ncm must not overlap n+diff") +ncm.width(0.38, euclidian).output("ncm.1", "ncm.1 : min. ncm width : 0.38um") +ncm.space(0.38, euclidian).output("ncm.2", "ncm.2 : min. ncm spacing manual merge if smaller : 0.38um") +ncm.enclosing(diff.and(nwell), 0.18, euclidian).output("ncm.3", "ncm.3 : min. ncm enclosure of p+diff : 0.18um") +ncm.separation(lvtn.and(diff), 0.23, euclidian).output("ncm.5", "ncm.5 : min. ncm spacing lvtn diff : 0.23um") +ncm.separation(diff.not(nwell), 0.2, euclidian).output("ncm.6", "ncm.6 : min. ncm spacing nfet : 0.2um") +ncm.with_area(0..0.265).output("ncm.7", "ncm.13 : min. ncm area : 0.265um²") + +# diff-tap +difftap = diff + tap +difftap.width(0.15, euclidian).output("difftap.1", "difftap.1 : min. difftap width : 0.15um") +not_in_cell1 = layout(source.cell_obj).select("s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b" , "-s8fpls_pl8", "-s8fpls_rdrv4" , "-s8fpls_rdrv4f", "-s8fpls_rdrv8") +not_in_cell1_diff = not_in_cell1.input(65, 20) +not_in_cell1_diff.not(areaid_sc).not(poly).edges.and(gate.edges).with_length(0,0.42).output("difftap.2", "difftap.2: min. gate (exempt areaid.sc) width : 0.42um") +diff.and(areaid_sc).not(poly).edges.and(gate.edges).with_length(0,0.36).output("difftap.2", "difftap.2: min. gate inside areaid.sc width : 0.36um") +difftap.space(0.27, euclidian).output("difftap.3", "difftap.3 : min. difftap spacing : 0.27um") +tap.edges.and(diff.edges).with_length(0,0.29).output("difftap.4", "difftap.4 : min. tap bound by diffusion : 0.29um") +tap.edges.and(diff.edges).space(0.4, projection).output("difftap.5", "difftap.5 : min. tap bound by 2 diffusions : 0.4um") +(tap.edges.and(diff.edges)).extended(0.01, 0.01, 0, 0, false).not(tap.and(diff)).and(diff.or(tap)).output("difftap.6", "difftap.6 : diff and tap not allowed to extend beyong their abutting ege") +tap.edges.not_interacting(diff.edges).separation(diff.edges, 0.13, euclidian).output("difftap.7", "difftap.7 : min. diff/tap spacing to non-coincident diff edge : 0.13um") +diff.edges.not_interacting(tap.edges).separation(tap.edges, 0.13, euclidian).output("difftap.7", "difftap.7 : min. diff/tap spacing to non-coincident tap edge : 0.13um") +nwell.enclosing(diff.not(uhvi).and(psdm), 0.18, euclidian).output("difftap.8", "difftap.8 : min. p+diff enclosure by nwell : 0.18um") +diff.not(uhvi).and(nsdm).separation(nwell, 0.34, euclidian).output("difftap.9", "difftap.9 : min. n+diff spacing to nwell : 0.34um") +nwell.enclosing(tap.not(uhvi).and(nsdm), 0.18, euclidian).output("difftap.10", "difftap.10 : min. n+tap enclosure by nwell : 0.18um") +tap.not(uhvi).and(psdm).separation(nwell, 0.13, euclidian).output("difftap.11", "difftap.11 : min. p+tap spacing to nwell : 0.13um") + +# tunm +tunm.width(0.41, euclidian).output("tunm.1", "tunm.1 : min. tunm width : 0.41um") +tunm.isolated(0.5, euclidian).output("tunm.2", "tunm.2 : min. tunm spacing : 0.5um") +tunm.enclosing(gate, 0.095, euclidian).output("tunm.3", "tunm.3 : min. tunm beyond gate : 0.095um") +tunm.separation(gate.not_interacting(tunm), 0.095, euclidian).output("tunm.4", "tunm.4 : min. tunm spacing to gate outside tunm: 0.095um") +gate.and(tunm).edges.not(gate.edges).output("tunm.5", "tunm.5 : gate must not straddle tunm") +tunm.not(dnwell).output("tunm.6a", "tunm.6a : tunm not allowed outside dnwell") +tunm.with_area(0..0.672).output("tunm.7", "tunm.7 : min. tunm area : 0.672um²") + +# poly +poly.width(0.15, euclidian).output("poly.1a", "poly.1a : min. poly width : 0.15um") +poly.not(diff).edges.and(gate.and(lvtn).edges).space(0.35, euclidian).output("poly.1b", "poly.1b: min. lvtn gate width : 0.35um") +poly.space(0.21, euclidian).output("poly.2", "poly.2 : min. poly spacing : 0.21um") +poly.and(rpm.or(urpm).or(poly_rs)).width(0.33, euclidian).output("poly.3", "poly.3 : min. poly resistor width : 0.33um") +poly.not(gate).separation(diff, 0.075, projection).polygons.without_area(0).output("poly.4", "poly.4 : min. poly on field spacing to diff : 0.075um") +poly.not(gate).separation(tap, 0.055, euclidian).output("poly.5", "poly.5 : min. poly on field spacing to tap : 0.055um") +gate.separation(tap, 0.3, projection).polygons.and(diff).output("poly.6", "poly.6 : min. gate spacing to tap : 0.3um") +diff.enclosing(gate, 0.25, projection).polygons.without_area(0).output("poly.7", "poly.7 : min. source/drain length : 0.25um") +poly.enclosing(gate, 0.13, projection).polygons.without_area(0).output("poly.8", "poly.8 : min. poly extention gate (endcap) : 0.13um") +poly.and(rpm.or(urpm).or(poly_rs)).separation(poly.or(difftap), 0.48, euclidian).polygons.without_area(0).output("poly.9", "poly.9 : min. poly resistor space to poly or diff/tap : 0.48um") +diff.merged.edges.end_segments(0.01).and(poly).output("poly.10", "poly.10 : poly must not overlap diff corner") +gate.with_angle(0 .. 90).output("poly.11", "poly.11 : non 90 degree angle gate") +not_in_cell3 = layout(source.cell_obj).select("s8fgvr_n_fg2") +not_in_cell3_poly = not_in_cell3.input(66, 20) +not_in_cell3_poly.not(hvi).not(nwell.not(hvi)).and(tap).output("poly.12", "poly.12 : poly must not overlap tap") +poly.and(diff_rs).output("poly.15", "poly.15 : poly must not overlap diff resistor") + +# rpm +rpm.width(1.27, euclidian).output("rpm.1a", "rpm.1a : min. rpm width : 1.27um") +rpm.space(0.84, euclidian).output("rpm.2", "rpm.2 : min. rpm spacing : 0.84um") +rpm.enclosing(poly.and(poly_rs).and(psdm), 0.2, euclidian).output("rpm.3", "rpm.3 : min. rpm enclosure of poly resistor : 0.2um") +psdm.enclosing(poly.and(poly_rs).and(rpm), 0.11, euclidian).output("rpm.4", "rpm.4 : min. psdm enclosure of poly resistor : 0.11um") +npc.enclosing(poly.and(poly_rs).and(rpm), 0.095, euclidian).output("rpm.5", "rpm.5 : min. npc enclosure of poly resistor : 0.095um") +rpm.separation(nsdm, 0.2, euclidian).output("rpm.6", "rpm.6 : min. rpm spacing nsdm: 0.2um") +rpm.separation(poly, 0.2, euclidian).output("rpm.7", "rpm.7 : min. rpm spacing poly: 0.2um") +rpm.and(poly).edges.not(poly.edges).output("rpm.8", "rpm.8 : poly must not straddle rpm") +poly.and(poly_rs).and(rpm).separation(hvntm, 0.185, euclidian).output("rpm.9", "rpm.9 : min. poly resistor spacing hvntm: 0.185um") +rpm.and(pwbm).output("rpm.10", "rpm.107 : min. rpm spacing pwbm: na") + +# varac +varac = poly & tap & (nwell - hvi) - areaid_ce +tap.not(poly).edges.and(varac.edges).space(0.18, euclidian).output("varac.1", "varac.1: min. varac channel length : 0.18um") +tap.and(poly).edges.and(varac.edges).space(1.0, euclidian).output("varac.2", "varac.2: min. varac channel wdth : 1.0um") +varac.separation(hvtp, 0.18, euclidian).output("varac.3", "varac.3: min. varac channel space to hvtp : 0.18um") +varac.separation(licon.and(tap), 0.25, euclidian).output("varac.4", "varac.4: min. varac channel space to licon on tap : 0.25um") +nwell.enclosing(poly.overlapping(varac), 0.15, euclidian).output("varac.5", "varac.5: min. nwell enclosure of poly overlapping varac channel : 0.15um") +tap.overlapping(varac).separation(difftap, 0.27, euclidian).polygons.without_area(0).output("varac.6", "varac.6: min. varac channel tap space to difftap : 0.27um") +nwell.overlapping(varac).and(diff.and(nwell)).output("varac.7", "varac.7: nwell overlapping varac channel must not overlap p+diff") + +# photo +photodiode = dnwell & areaid_po +photodiode.edges.without_length(3.0).output("photo.2", "photo.2 : minimum/maximum width of photodiode : 3.0um") +photodiode.space(5.0, euclidian).output("photo.3", "photo.3 : mini. photodiode spacing : 5.0um") +photodiode.separation(dnwell, 5.3, euclidian).output("photo.4", "photo.4 : mini. photodiode spacing to dnwell : 5.3um") +areaid_po.not(dnwell).output("photo.5.6", "photo.5.6 : photodiode edges must coincide areaid.po and enclosed by dnwell") +photodiode.not(tap.not(nwell).holes).output("photo.7", "photo.7 : photodiode must be enclosed by p+tap ring") +photodiode.and(nwell).edges.without_length(0.84).output("photo.8", "photo.8 : minimum/maximum width of nwell inside photodiode : 0.84um") +areaid_po.edges.and(photodiode.and(nwell).sized(1.08)).without_length(12.0).output("photo.9", "photo.9 : minimum/maximum enclosure of nwell by photodiode : 1.08um") +photodiode.and(tap).edges.without_length(0.41).output("photo.10", "photo.10 : minimum/maximum width of tap inside photodiode : 0.41um") + +# npc +npc.width(0.27, euclidian).output("npc.1", "npc.1 : min. npc width : 0.27um") +npc.space(0.27, euclidian).output("npc.2", "npc.2 : min. npc spacing, should be mnually merge if less : 0.27um") +npc.separation(gate, 0.09, euclidian).output("npc.4", "npc.4 : min. npc spacing to gate : 0.09um") + +# nsdm/psdm +npsdm = nsdm + psdm +nsdm.width(0.38, euclidian).output("nsdm.1", "nsdm.1 : min. nsdm width : 0.38um") +psdm.width(0.38, euclidian).output("psdm.1", "psdm.1 : min. psdm width : 0.38um") +nsdm.space(0.38, euclidian).output("n/psdm.1", "n/psdm.1 : min. nsdm spacing, should be mnually merge if less : 0.38um") +psdm.space(0.38, euclidian).output("n/psdm.1", "n/psdm.1 : min. psdm spacing, should be mnually merge if less : 0.38um") +npsdm.enclosing(diff, 0.125, euclidian).polygons.not(tap.sized(0.125)).output("n/psdm.5a", "n/psdm.5a : min. n/psdm enclosure diff except butting edge : 0.125um") +npsdm.enclosing(tap, 0.125, euclidian).polygons.not(diff.sized(0.125)).output("n/psdm.5b", "n/psdm.5b : min. n/psdm enclosure tap except butting edge : 0.125um") +tap.edges.and(diff.edges).not(npsdm).output("n/psdm.6", "n/psdm.6 : min. n/psdm enclosure of butting edge : 0.0um") +nsdm.and(difftap).separation(psdm.and(difftap), 0.13, euclidian).polygons.without_area(0).output("n/psdm.7", "n/psdm.7 : min. nsdm diff spacing to psdm diff except butting edge : 0.13um") +diff.and((nsdm.and(nwell)).or(psdm.not(nwell))).output("n/psdm.8", "n/psdm.8 : diff should be the opposite type of well/substrate underneath") +tap.and((nsdm.not(nwell)).or(psdm.and(nwell))).output("n/psdm.8", "n/psdm.8 : tap should be the same type of well/substrate underneath") +tap.and(diff).without_area(0).output("tap and diff", "tap and diff must not overlap") +nsdm.with_area(0..0.265).output("n/psdm.10a", "n/psdm.10a : min. nsdm area : 0.265um²") +psdm.with_area(0..0.265).output("n/psdm.10b", "n/psdm.10b : min. psdm area : 0.265um²") + +# licon +licon.not(poly.interacting(poly_rs)).edges.without_length(0.17).output("licon.1", "licon.1 : minimum/maximum width of licon : 0.17um") +licon.and(poly.interacting(poly_rs)).not_interacting((licon.and(poly.interacting(poly_rs)).edges.with_length(0.19)).or(licon.and(poly.interacting(poly_rs)).edges.with_length(2.0))).output("licon.1b/c", "licon.1b/c : minimum/maximum width/length of licon inside poly resistor : 2.0/0.19um") +licon.space(0.17, euclidian).output("licon.2", "licon.2 : min. licon spacing : 0.17um") +licon.and(poly.interacting(poly_rs)).edges.with_length(0.19).space(0.35, euclidian).output("licon.2b", "licon.2b : min. licon 0.19um edge on resistor spacing : 0.35um") +licon.interacting(licon.and(poly.interacting(poly_rs)).edges.with_length(2.0)).separation(licon.and(poly.interacting(poly_rs)), 0.51, euclidian).output("licon.2c", "licon.2c : min. licon 2.0um edge on resistor spacing : 0.51um") +licon.and(poly.interacting(poly_rs)).separation(licon.not(poly.interacting(poly_rs)), 0.51, euclidian).output("licon.2d", "licon.2d : min. licon on resistor spacing other licon : 0.51um") +# rule licon.3 not coded +licon.not(li).not(poly.or(diff).or(tap)).output("licon.4", "licon.4 : min. licon must overlap li and (poly or tap or diff) ") +diff.enclosing(licon, 0.04, euclidian).output("licon.5", "licon.5 : min. diff enclosure of licon : 0.04um") +tap.edges.and(diff.edges).separation(licon.and(tap).edges, 0.06, euclidian).output("licon.6", "licon.6 : min. abutting edge spacing to licon tap : 0.06um") +licon_edges_with_less_enclosure_tap = tap.enclosing(licon, 0.12, projection).second_edges +opposite1 = (licon.edges - licon_edges_with_less_enclosure_tap).width(0.17 + 1.dbu, projection).polygons +licon.not_interacting(opposite1).output("licon.7", "licon.7 : min. tap enclosure of licon by one of 2 opposite edges : 0.12um") +poly.enclosing(licon, 0.05, euclidian).output("licon.8", "licon.8 : min. poly enclosure of licon : 0.05um") +licon008 = licon.interacting(poly.enclosing(licon, 0.08, euclidian).polygons) +licon_edges_with_less_enclosure_poly = poly.enclosing(licon, 0.08, projection).second_edges +opposite2 = (licon.edges - licon_edges_with_less_enclosure_poly).width(0.17 + 1.dbu, projection).polygons +licon008.not_interacting(opposite2).output("licon.8a", "licon.8a : min. poly enclosure of licon by one of 2 opposite edges : 0.08um") +# rule licon.9 not coded +licon.and(tap.and(nwell.not(hvi))).separation(varac, 0.25, euclidian).output("licon.10", "licon.10 : min. licon spacing to varac channel : 0.25um") +not_in_cell4 = layout(source.cell_obj).select("-s8fs_gwdlvx4", "-s8fs_gwdlvx8", "-s8fs_hvrsw_x4", "-s8fs_hvrsw8", "-s8fs_hvrsw264", "-s8fs_hvrsw520", "-s8fs_rdecdrv", "-s8fs_rdec8”, “s8fs_rdec32", "-s8fs_rdec264", "-s8fs_rdec520") +not_in_cell4_licon = not_in_cell4.input(66, 44) +not_in_cell4_licon.and(diff.or(tap)).separation(gate.not(areaid_sc), 0.055, euclidian).output("licon.11", "licon.11 : min. licon spacing to gate : 0.055um") +licon.and(diff.or(tap)).separation(gate.and(areaid_sc), 0.05, euclidian).output("licon.11a", "licon.11a : min. licon spacing to gate inside areaid.sc : 0.05um") +in_cell4 = layout(source.cell_obj).select("+s8fs_gwdlvx4", "+s8fs_gwdlvx8", "+s8fs_hvrsw_x4", "+s8fs_hvrsw8", "+s8fs_hvrsw264", "+s8fs_hvrsw520") +in_cell4_licon = in_cell4.input(66, 44) +in_cell4_licon.and(diff.or(tap)).separation(gate, 0.04, euclidian).output("licon.11c", "licon.11c : min. licon spacing to gate for specific cells: 0.04um") +# rules 11.b , 11.d not coded +diff.interacting(gate).not(diff.interacting(gate).width(5.7, euclidian).polygons).output("licon.12", "licon.12 : max. sd width without licon : 5.7um") +licon.and(diff.or(tap)).separation(npc, 0.09, euclidian).output("licon.13", "licon.13 : min. difftap licon spacing to npc : 0.09um") +licon.and(poly).separation(diff.or(tap), 0.19, euclidian).output("licon.14", "licon.14 : min. poly licon spacing to difftap : 0.19um") +npc.enclosing(licon.and(poly), 0.1, euclidian).output("licon.15", "licon.15 : min. npc enclosure of poly-licon : 0.1um") +# rule licon.16 not applicable for the diff for the nmos of a nand gates or the pmos of a nor gates +#diff.not(gate).not_interacting(licon).output("licon.16", "licon.16 : diff must enclose one licon") +tap.not(uhvi).not_interacting(licon).output("licon.16", "licon.16 : tap must enclose one licon") +poly.and(tap).edges.not(tap.edges).output("licon.17", "licon.17 : tap must not straddle poly") +npc.not_interacting(licon.and(poly)).output("licon.18", "licon.18 : npc mut enclosed one poly-licon") + +# li +not_in_cell5 = layout(source.cell_obj).select("-s8rf2_xcmvpp_hd5_*") +not_in_cell5_li = not_in_cell5.input(67, 20) +not_in_cell5_li.width(0.17, euclidian).output("li.1", "li.1 : min. li width : 0.17um") +in_cell5 = layout(source.cell_obj).select("+s8rf2_xcmvpp_hd5_*") +in_cell5_li = in_cell5.input(67, 20) +in_cell5_li.width(0.14, euclidian).output("li.1a", "li.1a : min. li width for the cells s8rf2_xcmvpp_hd5_* : 0.14um") +# rule li.2 not coded +not_in_cell5_li.isolated(0.17, euclidian).output("li.3", "li.3 : min. li spacing : 0.17um") +in_cell5_li.space(0.14, euclidian).output("li.3a", "li.3a : min. li spacing for the cells s8rf2_xcmvpp_hd5_* : 0.14um") +licon08 = licon.interacting(li.enclosing(licon, 0.08, euclidian).polygons) +licon_edges_with_less_enclosure_li = li.enclosing(licon, 0.08, projection).second_edges +opposite3 = (licon.edges - licon_edges_with_less_enclosure_li).width(0.17 + 1.dbu, projection).polygons +licon08.not_interacting(opposite3).output("li.5", "li.5 : min. li enclosure of licon of 2 opposite edges : 0.08um") +li.with_area(0..0.0561).output("li.6", "li.6 : min. li area : 0.0561um²") + +# vpp +vpp.width(1.43, euclidian).output("vpp.1", "vpp.1 : min. vpp width : 1.43um") +# rules 1.b, 1.c not coded +vpp.and(poly.or(difftap)).output("vpp.3", "vpp.3 : vpp must not overlapp poly or diff or tap") +vpp.and(nwell).edges.not(vpp.edges).output("vpp.4", "vpp.4 : vpp must not straddle nwell") +vpp.and(dnwell).edges.not(vpp.edges).output("vpp.4", "vpp.4 : vpp must not straddle dnwell") +vpp.and(poly.or(li).or(m1).or(m2)).separation(poly.or(li).or(m1).or(m2), 1.5, euclidian).polygons.with_area(2.25,nil).output("vpp.5", "vpp.5 : min. vpp spacing to poly or li or m1 or m2 : 1.5um") +vpp.with_area(0..area(vpp.and(m3))*0.25).output("vpp.5a", "vpp.5a : max. m3 density in vpp : 0.25") +vpp.with_area(0..area(vpp.and(m4))*0.3).output("vpp.5b", "vpp.5b : max. m4 density in vpp : 0.3") +vpp.with_area(0..area(vpp.and(m5))*0.4).output("vpp.5c", "vpp.5c : max. m5 density in vpp : 0.4") +nwell.enclosing(vpp, 1.5, euclidian).output("vpp.8", "vpp.8 : nwell enclosure of vpp : 1.5") +vpp.separation(nwell, 1.5, euclidian).polygons.without_area(0).output("vpp.9", "vpp.9 : vpp spacing to nwell : 1.5") +# rule vpp.10 not coded +# rule vpp.11 not coded because moscap is not defined properly by any gds layer +# rules vpp.12a, 12b, 12c not coded because specific to one cell +if backend_flow = CU + m1.separation(vpp.and(m1), 0.16, euclidian).polygons.without_area(0).output("vpp.13", "vpp.13 : m1 spacing to m1inside vpp : 0.16") +end + +# CAPM +capm.width(1.0, euclidian).output("capm.1", "capm.1 : min. capm width : 1.0um") +capm.space(0.84, euclidian).output("capm.2a", "capm.2a : min. capm spacing : 0.84um") +m2.interacting(capm).isolated(1.2, euclidian).output("capm.2b", "capm.2b : min. capm spacing : 1.2um") +m2.enclosing(capm, 0.14, euclidian).output("capm.3", "capm.3 : min. m2 enclosure of capm : 0.14um") +capm.enclosing(via2, 0.14, euclidian).output("capm.4", "capm.4 : min. capm enclosure of via2 : 0.14um") +capm.separation(via2, 0.14, euclidian).output("capm.5", "capm.5 : min. capm spacing to via2 : 0.14um") +capm.sized(-20.0).sized(20.0).output("capm.6", "capm.6 : max. capm lenght/width : 20um") +capm.with_angle(0 .. 90).output("capm.7", "capm.7 : capm not rectangle") +capm.separation(via, 0.14, euclidian).polygons.without_area(0).output("capm.8", "capm.8 : min. capm spacing to via : 0.14um") +capm.and(nwell).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle nwell") +capm.and(diff).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle diff") +capm.and(tap).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle tap") +capm.and(poly).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle poly") +capm.and(li).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle li") +capm.and(m1).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle m1") +capm.separation(m2.not_interacting(capm), 0.14, euclidian).output("capm.11", "capm.11 : min. capm spacing to m2 not overlapping capm : 0.5um") + +end #FEOL + +if BEOL +info("BEOL section") + +# ct +mcon.edges.without_length(0.17).output("ct.1", "ct.1 : minimum/maximum width of mcon : 0.17um") +mcon.space(0.19, euclidian).output("ct.2", "ct.2 : min. mcon spacing : 0.19um") +# rule ct.3 not coded +mcon.not(li).output("ct.4", "ct.4 : mcon should covered by li") +if backend_flow = CU + li.interacting(li.and(m1).not(mcon).with_holes(1,10)).enclosing(mcon, 0.2, euclidian).output("ct.irdrop.1", "ct.irdrop.1 : min. li enclsoure of 1..10 mcon : 0.2um") + li.interacting(li.and(m1).not(mcon).with_holes(11,100)).enclosing(mcon, 0.3, euclidian).output("ct.irdrop.2", "ct.irdrop.2 : min. li enclsoure of 11..100 mcon : 0.3um") +end + +# m1 +huge_m1 = m1.sized(-1.5).sized(1.5) +m1.width(0.14, euclidian).output("m1.1", "m1.1 : min. m1 width : 0.14um") +m1.space(0.14, euclidian).output("m1.2", "m1.2 : min. m1 spacing : 0.14um") +huge_m1.separation(m1, 0.28, euclidian).output("m1.3ab", "m1.3ab : min. 3um.m1 spacing m1 : 0.28um") +not_in_cell6 = layout(source.cell_obj).select("-s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b", "-s8fpls_pl8", "-s8fs_cmux4_fm") +not_in_cell6_m1 = not_in_cell6.input(68, 20) +not_in_cell6_m1.enclosing(mcon, 0.03, euclidian).output("m1.4", "m1.4 : min. m1 enclosure of mcon : 0.03um") +in_cell6 = layout(source.cell_obj).select("+s8cell_ee_plus_sseln_a", "+s8cell_ee_plus_sseln_b", "+s8cell_ee_plus_sselp_a", "+s8cell_ee_plus_sselp_b", "+s8fpls_pl8", "+s8fs_cmux4_fm") +in_cell6_m1 = in_cell6.input(68, 20) +in_cell6_m1.enclosing(mcon, 0.005, euclidian).output("m1.4a", "m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um") +m1.with_area(0..0.083).output("m1.6", "m1.6 : min. m1 area : 0.083um²") +m1.holes.with_area(0..0.14).output("m1.7", "m1.7 : min. m1 holes area : 0.14um²") +if backend_flow = AL + mcon06 = mcon.interacting(poly.enclosing(m1, 0.06, euclidian).polygons) + mcon_edges_with_less_enclosure_m1 = m1.enclosing(mcon, 0.06, projection).second_edges + opposite4 = (mcon.edges - mcon_edges_with_less_enclosure_m1).width(0.17 + 1.dbu, projection).polygons + mcon06.not_interacting(opposite4).output("m1.5", "m1.5 : min. m1 enclosure of mcon of 2 opposite edges : 0.06um") + # rule m1.pd.1, rule m1.pd.2a, rule m1.pd.2b not coded +end +if bakend_flow = CU + m1.sized(-2.0).sized(2.0).output("m1.11", "m1.11 : max. m1 width after slotting : 4.0um") + # rule m1.12 not coded because inconsistent with m1.11 + # rule m1.13, m1.14, m1.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 +end + +# via +#rule via.3 not coded +via.not(m1).output("via.4c.5c", "via.4c.5c : m1 must enclose all via") +if backend_flow = AL + via.not(areaid_mt).edges.without_length(0.15).output("via.1a", "via.1a : minimum/maximum width of via : 0.15um") + via.and(areaid_mt).not_interacting((via.and(areaid_mt).edges.without_length(0.15)).or(via.and(areaid_mt).edges.without_length(0.23)).or(via.and(areaid_mt).edges.without_length(0.28))).output("via.1b", "via.1b : minimum/maximum width of via in areaid.mt: 0.15um or 0.23um or 0.28um") + via.space(0.17, euclidian).output("via.2", "via.2 : min. via spacing : 0.17um") + m1.enclosing(via.not_interacting(via.edges.without_length(0.15)), 0.055, euclidian).output("via.4a", "via.4a : min. m1 enclosure of 0.15um via : 0.055um") + m1.enclosing(via.not_interacting(via.edges.without_length(0.23)), 0.03, euclidian).output("via.4b", "via.4b : min. m1 enclosure of 0.23um via : 0.03um") + via1_edges_with_less_enclosure_m1 = m1.enclosing(via.not_interacting(via.edges.without_length(0.15)), 0.085, projection).second_edges + opposite5 = (via.not_interacting(via.edges.without_length(0.15)).edges - via1_edges_with_less_enclosure_m1).width(0.15 + 1.dbu, projection).polygons + via.not_interacting(via.edges.without_length(0.15)).not_interacting(opposite5).output("via1.5a", "via1.5a : min. m1 enclosure of 0.15um via of 2 opposite edges : 0.085um") + via2_edges_with_less_enclosure_m1 = m1.enclosing(via.not_interacting(via.edges.without_length(0.23)), 0.06, projection).second_edges + opposite6 = (via.not_interacting(via.edges.without_length(0.23)).edges - via2_edges_with_less_enclosure_m1).width(0.23 + 1.dbu, projection).polygons + via.not_interacting(via.edges.without_length(0.23)).not_interacting(opposite6).output("via1.5b", "via1.5b : min. m1 enclosure of 0.23um via of 2 opposite edges : 0.06um") +end +if backend_flow = CU + via.not(areaid_mt).edges.without_length(0.18).output("via.11", "via.11 : minimum/maximum width of via : 0.18um") + via.space(0.13, euclidian).output("via.12", "via.12 : min. via spacing : 0.13um") + # rule via.13 not coded because not understandable + via1_edges_with_less_enclosure_m1 = m1.enclosing(via, 0.04, projection).second_edges + opposite5 = (via.edges - via1_edges_with_less_enclosure_m1).width(0.18 + 1.dbu, projection).polygons + via.not_interacting(opposite5).output("via1.14", "via1.14 : min. m1 enclosure of 0.04um via of 2 opposite edges : 0.04um") + # rules via.irdrop.1, via.irdrop.2, via.irdrop.3, via.irdrop.4 not coded because not understandable +end + +# m2 +huge_m2 = m2.sized(-1.5).sized(1.5) +m2.width(0.14, euclidian).output("m2.1", "m2.1 : min. m2 width : 0.14um") +m2.space(0.14, euclidian).output("m2.2", "m2.2 : min. m2 spacing : 0.14um") +huge_m2.separation(m2, 0.28, euclidian).output("m2.3ab", "m2.3ab : min. 3um.m2 spacing m2 : 0.28um") +# rule m2.3c not coded +m2.with_area(0..0.0676).output("m2.6", "m2.6 : min. m2 area : 0.0676um²") +m2.holes.with_area(0..0.14).output("m2.7", "m2.7 : min. m2 holes area : 0.14um²") +via.not(m2).output("m2.via", "m2.via : m2 must enclose via") +if backend_flow = AL + m2.enclosing(via, 0.055, euclidian).output("m2.4", "m2.4 : min. m2 enclosure of via : 0.055um") + via_edges_with_less_enclosure_m2 = m2.enclosing(via, 0.085, projection).second_edges + error_corners = via_edges_with_less_enclosure_m2.width(angle_limit(100.0), 1.dbu) + via_interact = via.interacting(error_corners.polygons(1.dbu)) + via_interact.output("m2.5", "m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um") + # opposite7 = (via.edges - via_edges_with_less_enclosure_m2).width(0.14 + 1.dbu, projection).polygons + # via.not_interacting(opposite7).output("m2.5", "m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um") + # rule m2.pd.1, rule m2.pd.2a, rule m2.pd.2b not coded +end +if bakend_flow = CU + m2.sized(-2.0).sized(2.0).output("m2.11", "m2.11 : max. m2 width after slotting : 4.0um") + # rule m2.12 not coded because inconsistent with m2.11 + # rule m2.13, m2.14, m2.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 +end + +# via2 +#rule via233 not coded +via2.not(m2).output("via2", "via2 : m2 must enclose all via2") +if backend_flow = AL + via2.not(areaid_mt).edges.without_length(0.2).output("via2.1a", "via2.1a : minimum/maximum width of via2 : 0.2um") + via2.and(areaid_mt).not_interacting((via2.and(areaid_mt).edges.without_length(0.2)).or(via2.and(areaid_mt).edges.without_length(1.2)).or(via2.and(areaid_mt).edges.without_length(1.5))).output("via2.1b", "via2.1b : minimum/maximum width of via2 in areaid.mt: 0.2um or 1.2um or 1.5um") + via2.space(0.2, euclidian).output("via2.2", "via2.2 : min. via2 spacing : 0.2um") + m2.enclosing(via2, 0.04, euclidian).output("via2.4", "via2.4 : min. m2 enclosure of via2 : 0.04um") + m2.enclosing(via2.not_interacting(via2.edges.without_length(1.5)), 0.14, euclidian).output("via2.4a", "via2.4a : min. m2 enclosure of 1.5um via2 : 0.14um") + via2_edges_with_less_enclosure_m2 = m2.enclosing(via2, 0.085, projection).second_edges + opposite8 = (via2.edges - via2_edges_with_less_enclosure_m2).width(0.2 + 1.dbu, projection).polygons + via2.not_interacting(opposite8).output("via2.5", "via2.5 : min. m2 enclosure of via2 of 2 opposite edges : 0.085um") +end +if backend_flow = CU + via2.edges.without_length(0.21).output("via2.11", "via2.11 : minimum/maximum width of via2 : 0.21um") + via2.isolated(0.18, euclidian).output("via2.12", "via2.12 : min. via2 spacing : 0.18um") + # rule via2.13 not coded because not understandable, or not clear + m2.enclosing(via2, 0.035, euclidian).output("via2.14", "via2.14 : min. m2 enclosure of via2 : 0.035um") + # rules via2.irdrop.1, via2.irdrop.2, via2.irdrop.3, via2.irdrop.4 not coded because not understandable +end + +# m3 +huge_m3 = m3.sized(-1.5).sized(1.5) +m3.width(0.3, euclidian).output("m3.1", "m3.1 : min. m3 width : 0.3um") +m3.space(0.3, euclidian).output("m3.2", "m3.2 : min. m3 spacing : 0.3um") +huge_m3.separation(m3, 0.4, euclidian).output("m3.3ab", "m3.3ab : min. 3um.m3 spacing m3 : 0.4um") +# rule m3.3c not coded +m3.with_area(0..0.24).output("m3.6", "m3.6 : min. m2 area : 0.24um²") +via2.not(m3).output("m3.via2", "m3.via2 : m3 must enclose via2") +if backend_flow = AL + m3.enclosing(via2, 0.065, euclidian).output("m3.4", "m3.4 : min. m3 enclosure of via2 : 0.065um") + via2_edges_with_less_enclosure_m3 = m3.enclosing(via2, 0.085, projection).second_edges + opposite9 = (via2.edges - via2_edges_with_less_enclosure_m3).width(0.3 + 1.dbu, projection).polygons + via2.not_interacting(opposite9).output("m3.5", "m3.5 : min. m3 enclosure of via2 of 2 opposite edges : 0.085um") + # rule m3.pd.1, rule m3.pd.2a, rule m3.pd.2b not coded +end +if bakend_flow = CU + m3.holes.with_area(0..0.2).output("m3.7", "m3.7 : min. m2 holes area : 0.2um²") + m3.sized(-2.0).sized(2.0).output("m3.11", "m3.11 : max. m3 width after slotting : 4.0um") + # rule m3.12 not coded because inconsistent with m3.11 + # rule m3.13, m3.14, m3.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 +end + +# via3 +#rule via3.3 not coded +via3.not(m3).output("via3", "via3 : m3 must enclose all via3") +if backend_flow = AL + via3.not(areaid_mt).edges.without_length(0.2).output("via3.1a", "via3.1a : minimum/maximum width of via3 : 0.2um") + via3.and(areaid_mt).not_interacting((via3.and(areaid_mt).edges.without_length(0.2)).or(via3.and(areaid_mt).edges.without_length(0.8))).output("via3.1a", "via3.1a : minimum/maximum width of via3 in areaid.mt: 0.2um or 0.8um") + via3.space(0.2, euclidian).output("via3.2", "via3.2 : min. via3 spacing : 0.2um") + m3.enclosing(via3, 0.06, euclidian).output("via3.4", "via3.4 : min. m3 enclosure of via3 : 0.06um") + via3_edges_with_less_enclosure_m3 = m3.enclosing(via3, 0.09, projection).second_edges + opposite10 = (via3.edges - via3_edges_with_less_enclosure_m3).width(0.2 + 1.dbu, projection).polygons + via3.not_interacting(opposite10).output("via3.5", "via3.5 : min. m2 enclosure of via3 of 2 opposite edges : 0.09um") +end +if backend_flow = CU + via3.edges.without_length(0.21).output("via3.11", "via3.11 : minimum/maximum width of via3 : 0.21um") + via3.space(0.18, euclidian).output("via3.12", "via3.12 : min. via3 spacing : 0.18um") + m3.enclosing(via3, 0.055, euclidian).output("via3.13", "via3.13 : min. m3 enclosure of via3 : 0.055um") + # rule via3.14 not coded because not understandable, or not clear + # rules via3.irdrop.1, via3.irdrop.2, via3.irdrop.3, via3.irdrop.4 not coded because not understandable +end + +# nsm +nsm.width(3.0, euclidian).output("nsm.1", "nsm.1 : min. nsm width : 3.0um") +nsm.space(4.0, euclidian).output("nsm.2", "nsm.2 : min. nsm spacing : 4.0um") +nsm.enclosing(diff, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of diff : 3.0um") +nsm.enclosing(tap, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of tap : 3.0um") +nsm.enclosing(poly, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of poly : 3.0um") +nsm.enclosing(li, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of li : 3.0um") +nsm.enclosing(m1, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m1 : 3.0um") +nsm.enclosing(m2, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m2 : 3.0um") +nsm.enclosing(m3, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m3 : 3.0um") +nsm.enclosing(m4, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m4 : 3.0um") +nsm.enclosing(m5, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m5 : 3.0um") +nsm.enclosing(cfom, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of cfom : 3.0um") +if backend_flow = AL + nsm.separation(diff, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to diff : 1.0um") + nsm.separation(tap, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to tap : 1.0um") + nsm.separation(poly, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to poly : 1.0um") + nsm.separation(li, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to li : 1.0um") + nsm.separation(m1, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m1 : 1.0um") + nsm.separation(m2, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m2 : 1.0um") + nsm.separation(m3, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m3 : 1.0um") + nsm.separation(m4, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m4 : 1.0um") + nsm.separation(m5, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m5 : 1.0um") + nsm.separation(cfom, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to cfom : 1.0um") +end + +# m4 +huge_m4 = m4.sized(-1.5).sized(1.5) +m4.width(0.3, euclidian).output("m4.1", "m4.1 : min. m4 width : 0.3um") +m4.space(0.3, euclidian).output("m4.2", "m4.2 : min. m4 spacing : 0.3um") +m4.with_area(0..0.24).output("m4.4", "m4.4 : min. m2 area : 0.24um²") +huge_m4.separation(m4, 0.4, euclidian).output("m4.5ab", "m4.5ab : min. 3um.m4 spacing m4 : 0.4um") +via3.not(m4).output("m4.via3", "m4.via3 : m4 must enclose via3") +if backend_flow = AL + m4.enclosing(via3, 0.065, euclidian).output("m4.3", "m4.3 : min. m4 enclosure of via3 : 0.065um") + via3_edges_with_less_enclosure_m4 = m4.enclosing(via2, 0.085, projection).second_edges + opposite9 = (via3.edges - via3_edges_with_less_enclosure_m4).width(0.3 + 1.dbu, projection).polygons + via3.not_interacting(opposite9).output("m4.5", "m4.5 : min. m4 enclosure of via3 of 2 opposite edges : 0.085um") + # rule m4.pd.1, rule m4.pd.2a, rule m4.pd.2b not coded +end +if bakend_flow = CU + m4.holes.with_area(0..0.2).output("m4.7", "m4.7 : min. m2 holes area : 0.2um²") + m4.sized(-5.0).sized(5.0).output("m4.11", "m4.11 : max. m4 width after slotting : 10.0um") + # rule m4.12 not coded because inconsistent with m4.11 + # rule m4.13, m4.14, m4.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 + m4.enclosing(via3, 0.06, euclidian).output("m4.15", "m4.15 : min. m4 enclosure of via3 : 0.06um") +end + +# via4 +via4.edges.without_length(0.8).output("via4.1a", "via4.1a : minimum/maximum width of via4 : 0.8um") +via4.space(0.8, euclidian).output("via4.2", "via4.2 : min. via4 spacing : 0.8um") +#rule via4.3 not coded +m4.enclosing(via4, 0.19, euclidian).output("via4.4", "via4.4 : min. m4 enclosure of via4 : 0.19um") +via4.not(m4).output("via4", "via4 : m4 must enclose all via4") +if backend_flow = CU + # rules via4.irdrop.1, via4.irdrop.2, via4.irdrop.3, via4.irdrop.4 not coded because not understandable +end + +# m5 +m5.width(1.6, euclidian).output("m5.1", "m5.1 : min. m5 width : 1.6um") +m5.space(1.6, euclidian).output("m5.2", "m5.2 : min. m5 spacing : 1.6um") +via4.not(m5).output("m5.via4", "m5.via4 : m5 must enclose via4") +m5.enclosing(via4, 0.31, euclidian).output("m5.3", "m4.3 : min. m5 enclosure of via4 : 0.31um") + +# pad +pad.isolated(1.27, euclidian).output("pad.2", "pad.2 : min. pad spacing : 1.27um") + +end #BEOL + +if FEOL +info("FEOL section") + +# mf +mf.not_interacting(mf.edges.without_length(0.8)).output("mf.1", "mf.1 : minimum/maximum width of fuse : 0.8um") +mf.not_interacting(mf.edges.without_length(7.2)).output("mf.2", "mf.2 : minimum/maximum length of fuse : 7.2um") +mf.space(1.96, euclidian).output("mf.3", "mf.3 : min. fuse center spacing : 2.76um") +# fuses need more clarification on fuse_shield, fuse layers ... + +# hvi +hvi.width(0.6, euclidian).output("hvi.1", "hvi.1 : min. hvi width : 0.6um") +hvi.space(0.7, euclidian).output("hvi.2", "hvi.2 : min. hvi spacing, merge if less : 0.7um") +hvi.and(tunm).output("hvi.4", "hvi.4 : hvi must not overlapp tunm") +hvi.and(nwell).separation(nwell, 2.0, euclidian).output("hvnwell.8", "hvnwelli.8 : min. hvnwel spacing to nwell : 2.0") +areaid_hl.not(hvi).output("hvnwel.9", "hvnwell.9 : hvi must overlapp hvnwell") +# rule hvnell.10 not coded +diff.not(psdm.and(diff_rs)).and(hvi).width(0.29, euclidian).output("hvdifftap.14", "hvdifftap.14 : min. diff inside hvi width : 0.29um") +diff.and(psdm.and(diff_rs)).and(hvi).width(0.15, euclidian).output("hvdifftap.14a", "hvdifftap.14a : min. p+diff resistor inside hvi width : 0.15um") +diff.and(hvi).isolated(0.3, euclidian).output("hvdifftap.15a", "hvdifftap.15a : min. diff inside hvi spacing : 0.3um") +diff.and(hvi).and(nsdm).separation(diff.and(hvi).and(psdm), 0.37, euclidian).polygons.without_area(0).output("hvdifftap.15b", "hvdifftap.15b : min. n+diff inside hvi spacing to p+diff inside hvi except abutting: 0.37um") +tap.and(hvi).edges.and(diff).without_length(0.7).output("hvdifftap.16", "hvdifftap.16 : min. tap inside hvi abuttng diff : 0.7um") +hvi.and(nwell).enclosing(diff, 0.33, euclidian).output("hvdifftap.17", "hvdifftap.17 : min. hvnwell enclosure of p+diff : 0.33um") +hvi.and(nwell).separation(diff, 0.43, euclidian).output("hvdifftap.18", "hvdifftap.18 : min. hvnwell spacing to n+diff : 0.43um") +hvi.and(nwell).enclosing(tap, 0.33, euclidian).output("hvdifftap.19", "hvdifftap.19 : min. hvnwell enclosure of n+tap : 0.33um") +hvi.and(nwell).separation(tap, 0.43, euclidian).output("hvdifftap.20", "hvdifftap.20 : min. hvnwell spacing to p+tap : 0.43um") +hvi.and(diff).edges.not(diff.edges).output("hvdifftap.21", "hvdifftap.21 : diff must not straddle hvi") +hvi.and(tap).edges.not(tap.edges).output("hvdifftap.21", "hvdifftap.21 : tap must not straddle hvi") +hvi.enclosing(difftap, 0.18, euclidian).output("hvdifftap.22", "hvdifftap.22 : min. hvi enclosure of diff or tap : 0.18um") +hvi.separation(difftap, 0.18, euclidian).output("hvdifftap.23", "hvdifftap.23 : min. hvi spacing to diff or tap : 0.18um") +hvi.and(diff).not(nwell).separation(nwell, 0.43, euclidian).output("hvdifftap.24", "hvdifftap.24 : min. hv n+diff spacing to nwell : 0.43um") +diff.and(hvi).not(nwell).isolated(1.07, euclidian).polygons.and(tap).output("hvdifftap.25", "hvdifftap.25 : min. n+diff inside hvi spacing accros p+tap : 1.07um") +diff.not(poly).edges.and(gate.and(hvi).edges).space(0.35, euclidian).output("hvpoly.13", "hvpoly.13: min. hvi gate length : 0.5um") +hvi.and(poly).edges.not(poly.edges).output("hvpoly.14", "hvpoly.14 : poly must not straddle hvi") + +# hvntm +hvntm.width(0.7, euclidian).output("hvntm.1", "hvntm.1 : min. hvntm width : 0.7um") +hvntm.space(0.7, euclidian).output("hvntm.2", "hvntm.2 : min. hvntm spacing : 0.7um") +hvntm.enclosing(diff.and(nwell).and(hvi), 0.185, euclidian).output("hvntm.3", "hvntm.3 : min. hvntm enclosure of hv n+diff : 0.185um") +hvntm.separation(diff.not(nwell).not(hvi), 0.185, euclidian).output("hvntm.4", "hvntm.4 : min. hvntm spacing to n+diff : 0.185um") +hvntm.separation(diff.and(nwell).not(hvi), 0.185, euclidian).output("hvntm.5", "hvntm.5 : min. hvntm spacing to p+diff : 0.185um") +hvntm.separation(tap.not(nwell).not(hvi), 0.185, euclidian).polygons.without_area(0).output("hvntm.6a", "hvntm.6a : min. hvntm spacing to p+tap : 0.185um") +hvntm.and(areaid_ce).output("hvntm.9", "hvntm.9 : hvntm must not overlapp areaid.ce") + +# denmos +poly.not_interacting(pwde).interacting(areaid_en).width(1.055, projection).output("denmos.1", "denmos.1 : min. de_nfet gate width : 1.055um") +diff.not_interacting(pwde).enclosing(poly.interacting(areaid_en), 0.28, projection).polygons.without_area(0).output("denmos.2", "denmos.2 : min. de_nfet source ouside poly width : 0.28um") +diff.not_interacting(pwde).and(poly.interacting(areaid_en)).width(0.925, projection).output("denmos.3", "denmos.3 : min. de_nfet source inside poly width : 0.925um") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).width(0.17, euclidian).output("denmos.4", "denmos.4 : min. de_nfet drain width : 0.17um") +nwell.not_interacting(pwde).and(poly.interacting(areaid_en)).width(0.225, projection).polygons.or(nwell.and(poly.interacting(areaid_en)).sized(-0.1125).sized(0.1125)).output("denmos.5", "denmos.5 : min. de_nfet source inside nwell width : 0.225m") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).separation(diff.interacting(poly.interacting(areaid_en)), 1.585, projection).output("denmos.6", "denmos.6 : min. de_nfet source spacing to drain : 1.585um") +nwell.not_interacting(pwde).and(poly.and(diff).interacting(areaid_en)).edges.without_length(5.0, nil).output("denmos.7", "denmos.7 : min. de_nfet channel width : 5.0um") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("denmos.8", "denmos.8 : 90deg. not allowed for de_nfet drain") +nwell.not_interacting(pwde).interacting(areaid_en).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("denmos.9a", "denmos.9a : 90deg. not allowed for de_nfet nwell") +nwell.not_interacting(pwde).interacting(areaid_en).edges.with_angle(45).without_length(0.607..0.609).output("denmos.9a", "denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners") +nwell.not_interacting(pwde).interacting(areaid_en).edges.with_angle(135).without_length(0.607..0.609).output("denmos.9a", "denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(45).without_length(0.7..0.71).output("denmos.9b", "denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(135).without_length(0.7..0.71).output("denmos.9b", "denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners") +nwell.not_interacting(pwde).enclosing(diff.interacting(areaid_en).not_interacting(poly), 0.66, euclidian).output("denmos.10", "denmos.10 : min. nwell enclosure of de_nfet drain : 0.66um") +nwell.not_interacting(pwde).interacting(areaid_en).separation(tap.not(nwell), 0.86, euclidian).output("denmos.11", "denmos.11 : min. de_nfet nwell spacing to tap : 0.86um") +nwell.not_interacting(pwde).interacting(areaid_en).isolated(2.4, euclidian).output("denmos.12", "denmos.12 : min. de_nfet nwell : 2.4um") +nsdm.not_interacting(pwde).enclosing(diff.interacting(areaid_en).interacting(poly), 0.13, euclidian).output("denmos.13", "denmos.13 : min. nsdm enclosure of de_nfet source : 0.13um") + +# depmos +poly.interacting(pwde).interacting(areaid_en).width(1.05, projection).output("depmos.1", "depmos.1 : min. de_pfet gate width : 1.05um") +diff.interacting(pwde).enclosing(poly.interacting(areaid_en), 0.28, projection).polygons.without_area(0).output("depmos.2", "depmos.2 : min. de_pfet source ouside poly width : 0.28um") +diff.interacting(pwde).and(poly.interacting(areaid_en)).width(0.92, projection).output("depmos.3", "depmos.3 : min. de_pfet source inside poly width : 0.92um") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).width(0.17, euclidian).output("depmos.4", "depmos.4 : min. de_pfet drain width : 0.17um") +pwde.not(nwell).and(poly.interacting(areaid_en)).width(0.26, projection).polygons.or(pwde.not(nwell).and(poly.interacting(areaid_en)).sized(-0.13).sized(0.13)).output("depmos.5", "depmos.5 : min. de_pfet source inside nwell width : 0.26m") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).separation(diff.interacting(poly.interacting(areaid_en)), 1.19, projection).output("depmos.6", "depmos.6 : min. de_pfet source spacing to drain : 1.19um") +nwell.interacting(pwde).and(poly.and(diff).interacting(areaid_en)).edges.without_length(5.0, nil).output("depmos.7", "depmos.7 : min. de_pfet channel width : 5.0um") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("depmos.8", "depmos.8 : 90deg. not allowed for de_pfet drain") +pwde.not(nwell).interacting(areaid_en).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("depmos.9a", "depmos.9a : 90deg. not allowed for de_pfet pwell") +pwde.not(nwell).interacting(areaid_en).edges.with_angle(45).without_length(0.607..0.609).output("depmos.9a", "depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners") +pwde.not(nwell).interacting(areaid_en).edges.with_angle(135).without_length(0.607..0.609).output("depmos.9a", "depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(45).without_length(0.7..0.71).output("depmos.9b", "depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(135).without_length(0.7..0.71).output("depmos.9b", "depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners") +nwell.interacting(pwde).separation(diff.interacting(areaid_en).not_interacting(poly), 0.86, euclidian).output("depmos.10", "depmos.10 : min. pwell enclosure of de_pfet drain : 0.86um") +pwde.not(nwell).interacting(areaid_en).separation(tap.and(nwell), 0.66, euclidian).output("depmos.11", "depmos.11 : min. de_pfet pwell spacing to tap : 0.66um") +psdm.interacting(pwde).enclosing(diff.interacting(areaid_en).interacting(poly), 0.13, euclidian).output("depmos.12", "depmos.12 : min. psdm enclosure of de_pfet source : 0.13um") + +# extd +areaid_en.and(difftap).edges.not(difftap.edges).output("extd.1", "extd.1 : difftap must not straddle areaid.en") +difftap.interacting(areaid_en).not(poly).with_area(0).output("extd.2", "extd.2 : poly must not overlapp entirely difftap in areaid.en") +# rules extd.4, extd.5, extd.6, extd.7 not coded because specific to some cells + +# vhvi +# rules vhvi.vhv.1, vhvi.vhv.2, vhvi.vhv.3, vhvi.vhv.4, vhvi.vhv.5, vhvi.vhv.6 not coded +vhvi.width(0.02, euclidian).output("vhvi.1", "vhvi.1 : min. vhvi width : 0.02um") +vhvi.and(areaid_ce).output("vhvi.2", "vhvi.2 : vhvi must not overlap areaid.ce") +vhvi.and(hvi).output("vhvi.3", "vhvi.3 : vhvi must not overlap hvi") +# rules vhvi.4, vhvi.6 not coded +vhvi.and(diff).edges.not(diff.edges).output("vhvi.5", "vhvi.5 : vhvi must not straddle diff") +vhvi.and(tap).edges.not(tap.edges).output("vhvi.5", "vhvi.5 : vhvi must not straddle tap") +vhvi.and(poly).edges.not(poly.edges).output("vhvi.7", "vhvi.7 : vhvi must not straddle poly") + +nwell.and(vhvi).separation(nwell, 2.5, euclidian).output("hv.nwell.1", "hv.nwell.1 : min. vhvi nwell spacing to nwell : 2.5um") +diff.and(vhvi).space(0.3, euclidian).output("hv.diff.1", "hv.diff.1 : min. vhvi diff spacing : 0.3um") +nwell.interacting(diff.and(vhvi)).separation(diff.not(nwell), 0.43, euclidian).output("hv.diff.2", "hv.diff.2 : min. vhvi nwell spacing n+diff : 0.43um") +diff.and(vhvi).not(nwell).separation(nwell, 0.55, euclidian).output("hv.diff.3a", "hv.diff.3a : min. vhvi n+diff spacing nwell : 0.55um") +# rule hv.diff.3b not coded +poly.and(vhvi).not(diff).separation(diff, 0.3, euclidian).polygons.without_area(0).output("hv.poly.2", "hv.poly.2 : min. vhvi poly spacing to diff : 0.3um") +poly.and(vhvi).not(diff).separation(nwell, 0.55, euclidian).polygons.without_area(0).output("hv.poly.3", "hv.poly.3 : min. vhvi poly spacing to nwell : 0.55um") +nwell.enclosing(poly.and(vhvi).not(diff), 0.3, euclidian).polygons.without_area(0).output("hv.poly.4", "hv.poly.4 : min. nwell enclosure of vhvi poly : 0.3um") +#poly.and(vhvi).enclosing(diff.interacting(areaid_en), 0.16, projection).polygons.without_area(0).output("hv.poly.6", "hv.poly.6 : min. poly enclosure of hvfet gate : 0.16um") +# rule hv.poly.7 not coded + +# uhvi +uhvi.and(diff).edges.not(diff.edges).output("uhvi.1", "uhvi.1 : diff must not straddle uhvi") +uhvi.and(tap).edges.not(tap.edges).output("uhvi.1", "uhvi.1 : tap must not straddle uhvi") +uhvi.and(poly).edges.not(poly.edges).output("uhvi.2", "uhvi.2 : poly must not straddle uhvi") +pwbm.not(uhvi).output("uhvi.3", "uhvi.3 : uhvi must not enclose pwbm") +uhvi.and(dnwell).edges.not(dnwell.edges).output("uhvi.4", "uhvi.4 : dnwell must not straddle uhvi") +areaid_en20.not(uhvi).output("uhvi.5", "uhvi.5 : uhvi must not enclose areaid.en20") +#dnwell.not(uhvi).output("uhvi.6", "uhvi.6 : uhvi must not enclose dnwell") +natfet.not(uhvi).output("uhvi.7", "uhvi.7 : uhvi must not enclose natfet") + +# pwell_res +pwell_rs.width(2.65).output("pwres.2", "pwres.2 : min. pwell resistor width : 2.65um") +pwell_rs.sized(-2.65).sized(2.65).output("pwres.2", "pwres.2 : max. pwell resistor width : 2.65um") +pwell_rs.interacting(pwell_rs.edges.with_length(2.651,26.499)).output("pwres.3", "pwres.3 : min. pwell resistor length : 26.5um") +pwell_rs.interacting(pwell_rs.edges.with_length(265.0, nil)).output("pwres.4", "pwres.4 : max. pwell resistor length : 265um") +tap.interacting(pwell_rs).separation(nwell, 0.22, euclidian).output("pwres.5", "pwres.5 : min. pwell resistor tap spacing to nwell : 0.22um") +tap.interacting(pwell_rs).and(tap.sized(0.22).and(nwell)).output("pwres.5", "pwres.5 : max. pwell resistor tap spacing to nwell : 0.22um") +tap.interacting(pwell_rs).width(0.53).output("pwres.6", "pwres.6 : min. width of tap inside pwell resistor : 0.53um") +tap.interacting(pwell_rs).sized(-0.265).sized(0.265).output("pwres.6", "pwres.6 : max. width of tap inside pwell resistor : 0.53um") +# rules pwres.7a, pwres.7b not coded +pwell_rs.and(diff).output("pwres.8", "pwres.8 : diff not allowed inside pwell resistor") +pwell_rs.and(poly).output("pwres.8", "pwres.8 : poly not allowed inside pwell resistor") +# rules pwres.9, pwres.10 not coded + +# rf_diode +areaid_re.with_angle(0 .. 90).output("rfdiode.1", "rfdiode.1 : non 90 degree angle areaid.re") +areaid_re.not(nwell).or(nwell.interacting(areaid_re).not(areaid_re)).output("rfdiode.2", "rfdiode.2 : areaid.re must coincide rf nwell diode") +# rule rfdiode.3 not coded + +end #FEOL + +if OFFGRID +info("OFFGRID-ANGLES section") + +dnwell.ongrid(0.005).output("dnwell_OFFGRID", "x.1b : OFFGRID vertex on dnwell") +dnwell.with_angle(0 .. 45).output("dnwell_angle", "x.3a : non 45 degree angle dnwell") +nwell.ongrid(0.005).output("nwell_OFFGRID", "x.1b : OFFGRID vertex on nwell") +nwell.with_angle(0 .. 45).output("nwell_angle", "x.3a : non 45 degree angle nwell") +pwbm.ongrid(0.005).output("pwbm_OFFGRID", "x.1b : OFFGRID vertex on pwbm") +pwbm.with_angle(0 .. 45).output("pwbm_angle", "x.3a : non 45 degree angle pwbm") +pwde.ongrid(0.005).output("pwde_OFFGRID", "x.1b : OFFGRID vertex on pwde") +pwde.with_angle(0 .. 45).output("pwde_angle", "x.3a : non 45 degree angle pwde") +hvtp.ongrid(0.005).output("hvtp_OFFGRID", "x.1b : OFFGRID vertex on hvtp") +hvtp.with_angle(0 .. 45).output("hvtp_angle", "x.3a : non 45 degree angle hvtp") +hvtr.ongrid(0.005).output("hvtr_OFFGRID", "x.1b : OFFGRID vertex on hvtr") +hvtr.with_angle(0 .. 45).output("hvtr_angle", "x.3a : non 45 degree angle hvtr") +lvtn.ongrid(0.005).output("lvtn_OFFGRID", "x.1b : OFFGRID vertex on lvtn") +lvtn.with_angle(0 .. 45).output("lvtn_angle", "x.3a : non 45 degree angle lvtn") +ncm.ongrid(0.005).output("ncm_OFFGRID", "x.1b : OFFGRID vertex on ncm") +ncm.with_angle(0 .. 45).output("ncm_angle", "x.3a : non 45 degree angle ncm") +diff.ongrid(0.005).output("diff_OFFGRID", "x.1b : OFFGRID vertex on diff") +tap.ongrid(0.005).output("tap_OFFGRID", "x.1b : OFFGRID vertex on tap") +diff.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("diff_angle", "x.2 : non 90 degree angle diff") +diff.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("diff_angle", "x.2c : non 45 degree angle diff") +tap.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("tap_angle", "x.2 : non 90 degree angle tap") +tap.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("tap_angle", "x.2c : non 45 degree angle tap") +tunm.ongrid(0.005).output("tunm_OFFGRID", "x.1b : OFFGRID vertex on tunm") +tunm.with_angle(0 .. 45).output("tunm_angle", "x.3a : non 45 degree angle tunm") +poly.ongrid(0.005).output("poly_OFFGRID", "x.1b : OFFGRID vertex on poly") +poly.with_angle(0 .. 90).output("poly_angle", "x.2 : non 90 degree angle poly") +rpm.ongrid(0.005).output("rpm_OFFGRID", "x.1b : OFFGRID vertex on rpm") +rpm.with_angle(0 .. 45).output("rpm_angle", "x.3a : non 45 degree angle rpm") +npc.ongrid(0.005).output("npc_OFFGRID", "x.1b : OFFGRID vertex on npc") +npc.with_angle(0 .. 45).output("npc_angle", "x.3a : non 45 degree angle npc") +nsdm.ongrid(0.005).output("nsdm_OFFGRID", "x.1b : OFFGRID vertex on nsdm") +nsdm.with_angle(0 .. 45).output("nsdm_angle", "x.3a : non 45 degree angle nsdm") +psdm.ongrid(0.005).output("psdm_OFFGRID", "x.1b : OFFGRID vertex on psdm") +psdm.with_angle(0 .. 45).output("psdm_angle", "x.3a : non 45 degree angle psdm") +licon.ongrid(0.005).output("licon_OFFGRID", "x.1b : OFFGRID vertex on licon") +licon.with_angle(0 .. 90).output("licon_angle", "x.2 : non 90 degree angle licon") +li.ongrid(0.005).output("li_OFFGRID", "x.1b : OFFGRID vertex on li") +li.with_angle(0 .. 45).output("li_angle", "x.3a : non 45 degree angle li") +mcon.ongrid(0.005).output("ct_OFFGRID", "x.1b : OFFGRID vertex on mcon") +mcon.with_angle(0 .. 90).output("ct_angle", "x.2 : non 90 degree angle mcon") +vpp.ongrid(0.005).output("vpp_OFFGRID", "x.1b : OFFGRID vertex on vpp") +vpp.with_angle(0 .. 45).output("vpp_angle", "x.3a : non 45 degree angle vpp") +m1.ongrid(0.005).output("m1_OFFGRID", "x.1b : OFFGRID vertex on m1") +m1.with_angle(0 .. 45).output("m1_angle", "x.3a : non 45 degree angle m1") +via.ongrid(0.005).output("via_OFFGRID", "x.1b : OFFGRID vertex on via") +via.with_angle(0 .. 90).output("via_angle", "x.2 : non 90 degree angle via") +m2.ongrid(0.005).output("m2_OFFGRID", "x.1b : OFFGRID vertex on m2") +m2.with_angle(0 .. 45).output("m2_angle", "x.3a : non 45 degree angle m2") +via2.ongrid(0.005).output("via2_OFFGRID", "x.1b : OFFGRID vertex on via2") +via2.with_angle(0 .. 90).output("via2_angle", "x.2 : non 90 degree angle via2") +m3.ongrid(0.005).output("m3_OFFGRID", "x.1b : OFFGRID vertex on m3") +m3.with_angle(0 .. 45).output("m3_angle", "x.3a : non 45 degree angle m3") +via3.ongrid(0.005).output("via3_OFFGRID", "x.1b : OFFGRID vertex on via3") +via3.with_angle(0 .. 90).output("via3_angle", "x.2 : non 90 degree angle via3") +nsm.ongrid(0.005).output("nsm_OFFGRID", "x.1b : OFFGRID vertex on nsm") +nsm.with_angle(0 .. 45).output("nsm_angle", "x.3a : non 45 degree angle nsm") +m4.ongrid(0.005).output("m4_OFFGRID", "x.1b : OFFGRID vertex on m4") +m4.with_angle(0 .. 45).output("m4_angle", "x.3a : non 45 degree angle m4") +via4.ongrid(0.005).output("via4_OFFGRID", "x.1b : OFFGRID vertex on via4") +via4.with_angle(0 .. 90).output("via4_angle", "x.2 : non 90 degree angle via4") +m5.ongrid(0.005).output("m5_OFFGRID", "x.1b : OFFGRID vertex on m5") +m5.with_angle(0 .. 45).output("m5_angle", "x.3a : non 45 degree angle m5") +pad.ongrid(0.005).output("pad_OFFGRID", "x.1b : OFFGRID vertex on pad") +pad.with_angle(0 .. 45).output("pad_angle", "x.3a : non 45 degree angle pad") +mf.ongrid(0.005).output("mf_OFFGRID", "x.1b : OFFGRID vertex on mf") +mf.with_angle(0 .. 90).output("mf_angle", "x.2 : non 90 degree angle mf") +hvi.ongrid(0.005).output("hvi_OFFGRID", "x.1b : OFFGRID vertex on hvi") +hvi.with_angle(0 .. 45).output("hvi_angle", "x.3a : non 45 degree angle hvi") +hvntm.ongrid(0.005).output("hvntm_OFFGRID", "x.1b : OFFGRID vertex on hvntm") +hvntm.with_angle(0 .. 45).output("hvntm_angle", "x.3a : non 45 degree angle hvntm") +vhvi.ongrid(0.005).output("vhvi_OFFGRID", "x.1b : OFFGRID vertex on vhvi") +vhvi.with_angle(0 .. 45).output("vhvi_angle", "x.3a : non 45 degree angle vhvi") +uhvi.ongrid(0.005).output("uhvi_OFFGRID", "x.1b : OFFGRID vertex on uhvi") +uhvi.with_angle(0 .. 45).output("uhvi_angle", "x.3a : non 45 degree angle uhvi") +pwell_rs.ongrid(0.005).output("pwell_rs_OFFGRID", "x.1b : OFFGRID vertex on pwell_rs") +pwell_rs.with_angle(0 .. 45).output("pwell_rs_angle", "x.3a : non 45 degree angle pwell_rs") +areaid_re.ongrid(0.005).output("areaid_re_OFFGRID", "x.1b : OFFGRID vertex on areaid.re") + +end #OFFGRID + +# time spent for the DRC +time = Time.now +hours = ((time - tstart)/3600).to_i +minutes = ((time - tstart)/60 - hours * 60).to_i +seconds = ((time - tstart) - (minutes * 60 + hours * 3600)).to_i +$stdout.write "DRC finished at : #{time.hour}:#{time.min}:#{time.sec} - DRC duration = #{hours} hrs. #{minutes} min. #{seconds} sec.\n" + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/sky130A.lydrc b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/sky130A.lydrc new file mode 100644 index 000000000..67ec2a5cf --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/sky130A.lydrc @@ -0,0 +1,39 @@ + + + DRC + + drc + + + + false + false + 0 + + true + sky130a + tools_menu.sky130a>lvs("Sky130A").end + dsl + drc-dsl-xml + +# Take input from layout window +# $input = nil + +# Interactive report +# $report = "" + +# Enable all parts +$feol = "true" +$beol = "true" +$offgrid = "true" + +# Disabled for now +$seal = "false" +$floating_met = "false" + +# Default threads +$thr = nil + +# %include ./core/sky130A_mr.drc + + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/sky130A.lyp b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/sky130A.lyp new file mode 100755 index 000000000..cf7ec0b5d --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/sky130A.lyp @@ -0,0 +1,8241 @@ + + + + #ccccd9 + #ccccd9 + 0 + 0 + C7 + C0 + true + true + false + 1 + false + false + 0 + prBoundary.boundary - 235/4 + 235/4@1 + + + #00ffff + #00ffff + 0 + 0 + C21 + C0 + true + true + false + 1 + false + false + 0 + pwell.drawing - 64/44 + 64/44@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + C39 + C0 + true + true + false + 1 + false + false + 0 + pwell.pin - 122/16 + 122/16@1 + + + #9900e6 + #9900e6 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + pwell.label - 64/59 + 64/59@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + pwell.res - 64/13 + 64/13@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + pwell.cut - 64/14 + 64/14@1 + + + #ffffff + #96c8ff + 0 + 0 + C39 + C0 + true + true + false + 1 + false + false + 0 + pwelliso.pin - 44/16 + 44/16@1 + + + #9900e6 + #9900e6 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + pwelliso.label - 44/5 + 44/5@1 + + + #00cc66 + #00cc66 + 0 + 0 + C21 + C0 + true + true + false + 1 + false + false + 0 + nwell.drawing - 64/20 + 64/20@1 + + + #ff00ff + #ff00ff + 0 + 0 + C2 + C0 + true + true + false + 1 + false + false + 0 + nwell.net - 84/23 + 84/23@1 + + + #268c6b + #268c6b + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + nwell.pin - 64/16 + 64/16@1 + + + #333399 + #333399 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + nwell.label - 64/5 + 64/5@1 + + + #c8ffc8 + #c8ffc8 + 0 + 0 + C48 + C0 + true + true + false + 1 + false + false + 0 + dnwell.drawing - 64/18 + 64/18@1 + + + #00ffff + #00ffff + 0 + 0 + C6 + C0 + true + true + false + 1 + false + false + 0 + vhvi.drawing - 74/21 + 74/21@1 + + + #00ff00 + #00ff00 + 0 + 0 + C35 + C0 + true + true + false + 1 + false + false + 0 + diff.drawing - 65/20 + 65/20@1 + + + #00ff00 + #00ff00 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + diff.res - 65/13 + 65/13@1 + + + #00ff00 + #00ff00 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + diff.cut - 65/14 + 65/14@1 + + + #268c6b + #268c6b + 0 + 0 + C37 + C0 + false + true + false + 1 + false + false + 0 + diff.pin - 65/16 + 65/16@1 + + + #c8ffc8 + #c8ffc8 + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + diff.label - 65/6 + 65/6@1 + + + #00ff00 + #00ff00 + 0 + 0 + C5 + C0 + false + true + false + 1 + false + false + 0 + diff.net - 65/23 + 65/23@1 + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + false + 0 + diff.boundary - 65/4 + 65/4@1 + + + #9900e6 + #9900e6 + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + diff.hv - 65/8 + 65/8@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C35 + C0 + true + true + false + 1 + false + false + 0 + tap.drawing - 65/44 + 65/44@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + tap.pin - 65/48 + 65/48@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C5 + C0 + false + true + false + 1 + false + false + 0 + tap.net - 65/41 + 65/41@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + false + 0 + tap.boundary - 65/60 + 65/60@1 + + + #fff464 + #fff464 + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + tap.label - 65/5 + 65/5@1 + + + #9900e6 + #9900e6 + 0 + 0 + C23 + C0 + true + true + false + 1 + false + false + 0 + psdm.drawing - 94/20 + 94/20@1 + + + #e61f0d + #e61f0d + 0 + 0 + C22 + C0 + true + true + false + 1 + false + false + 0 + nsdm.drawing - 93/44 + 93/44@1 + + + #ff0000 + #ff0000 + 0 + 0 + C42 + C0 + true + true + false + 1 + false + false + 0 + poly.drawing - 66/20 + 66/20@1 + + + #ff8000 + #ff8000 + 0 + 0 + C39 + C0 + true + true + false + 1 + false + false + 0 + poly.pin - 66/16 + 66/16@1 + + + #ff0000 + #ff0000 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + poly.res - 66/13 + 66/13@1 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.cut - 66/14 + 66/14@1 + + + #ff0000 + #ff0000 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + poly.gate - 66/9 + 66/9@1 + + + #ffafaf + #ffafaf + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.label - 66/5 + 66/5@1 + + + #ff0000 + #ff0000 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + poly.boundary - 66/4 + 66/4@1 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.probe - 66/25 + 66/25@1 + + + #ff0000 + #ff0000 + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + poly.short - 66/15 + 66/15@1 + + + #ff0000 + #ff0000 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + poly.net - 66/23 + 66/23@1 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.model - 66/83 + 66/83@1 + + + #00cc66 + #00cc66 + 0 + 0 + C51 + C0 + true + true + false + 1 + false + false + 0 + ldntm.drawing - 11/44 + 11/44@1 + + + #96c8ff + #ffffff + 0 + 0 + C15 + C0 + true + true + false + 1 + false + false + 0 + lvtn.drawing - 125/44 + 125/44@1 + + + #ff8000 + #ffffff + 0 + 0 + C14 + C0 + true + true + false + 1 + false + false + 0 + hvtp.drawing - 78/44 + 78/44@1 + + + #ff0000 + #e61f0d + 0 + 0 + C14 + C0 + false + true + false + 1 + false + false + 0 + hvtr.drawing - 18/20 + 18/20@1 + + + #9900e6 + #9900e6 + 0 + 0 + C42 + C0 + true + true + false + 1 + false + false + 0 + tunm.drawing - 80/20 + 80/20@1 + + + #ffffcc + #ffffcc + 0 + 0 + C24 + C0 + true + true + false + 1 + false + false + 0 + licon1.drawing - 66/44 + 66/44@1 + + + #ffffcc + #ffffcc + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + licon1.boundary - 66/60 + 66/60@1 + + + #ffe6bf + #c8ffff + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + licon1.pin - 66/58 + 66/58@1 + + + #ffffcc + #ffffcc + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + licon1.net - 66/41 + 66/41@1 + + + #bf4026 + #bf4026 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + npc.drawing - 95/20 + 95/20@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + li1.drawing - 67/20 + 67/20@1 + + + #bf4026 + #bf4026 + 0 + 0 + C47 + C0 + true + true + false + 1 + false + false + 0 + li1.pin - 67/16 + 67/16@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + I1 + C0 + false + true + false + 1 + false + false + 0 + li1.res - 67/13 + 67/13@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + li1.cut - 67/14 + 67/14@1 + + + #bf4026 + #bf4026 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + li1.label - 67/5 + 67/5@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C54 + C0 + true + true + false + 1 + false + false + 0 + li1.net - 67/23 + 67/23@1 + + + #d9e6ff + #d9e6ff + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + li1.boundary - 67/4 + 67/4@1 + + + #bf4026 + #bf4026 + 0 + 0 + C54 + C0 + true + true + false + 1 + false + false + 0 + li1.blockage - 67/10 + 67/10@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + li1.short - 67/15 + 67/15@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + li1.probe - 67/25 + 67/25@1 + + + #ccccd9 + #ccccd9 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + mcon.drawing - 67/44 + 67/44@1 + + + #ccccd9 + #ccccd9 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + mcon.boundary - 67/60 + 67/60@1 + + + #ffffcc + #d9e6ff + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + mcon.pin - 67/48 + 67/48@1 + + + #ccccd9 + #ccccd9 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + mcon.net - 67/41 + 67/41@1 + + + #0000ff + #0000ff + 0 + 0 + C7 + C0 + true + true + false + 1 + false + false + 0 + met1.drawing - 68/20 + 68/20@1 + + + #0000ff + #0000ff + 0 + 0 + I1 + C0 + false + true + false + 1 + false + false + 0 + met1.res - 68/13 + 68/13@1 + + + #0000ff + #0000ff + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + met1.cut - 68/14 + 68/14@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C6 + C0 + true + true + false + 1 + false + false + 0 + met1.pin - 68/16 + 68/16@1 + + + #96c8ff + #96c8ff + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + met1.label - 68/5 + 68/5@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + met1.net - 68/23 + 68/23@1 + + + #0000ff + #0000ff + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + met1.boundary - 68/4 + 68/4@1 + + + #0000ff + #0000ff + 0 + 0 + C54 + C0 + true + true + false + 1 + false + false + 0 + met1.blockage - 68/10 + 68/10@1 + + + #0000ff + #0000ff + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + met1.short - 68/15 + 68/15@1 + + + #0000ff + #0000ff + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + met1.probe - 68/25 + 68/25@1 + + + #0000ff + #0000ff + 0 + 0 + C26 + C0 + false + true + false + 1 + false + false + 0 + met1.option1 - 68/32 + 68/32@1 + + + #0000ff + #0000ff + 0 + 0 + C27 + C0 + false + true + false + 1 + false + false + 0 + met1.option2 - 68/33 + 68/33@1 + + + #0000ff + #0000ff + 0 + 0 + C28 + C0 + false + true + false + 1 + false + false + 0 + met1.option3 - 68/34 + 68/34@1 + + + #0000ff + #0000ff + 0 + 0 + C29 + C0 + false + true + false + 1 + false + false + 0 + met1.option4 - 68/35 + 68/35@1 + + + #0000ff + #0000ff + 0 + 0 + C30 + C0 + false + true + false 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................ + ................ + ...*............ + ..*.*........... + .*...*.......... + *.....*......... + .*...*.......... + ..*.*........... + ...*............ + + 54 + sparsediam + + + + .......*.......* + ......*......... + .....*.......... + ................ + ................ + ................ + .*.............. + *............... + .......*.......* + ..............*. + .............*.. + ................ + ................ + ................ + .........*...... + ........*....... + + 55 + rain + + + *** + 1 + solid + + + ****.. + 2 + dashed + + + *.. + 3 + dots + + + ***..*.. + 4 + dashDot + + + **.. + 5 + shortDash + + + ****..**.. + 6 + doubleDash + + + *... + 7 + hidden + + + *** + 8 + thickLine + + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/sky130A.lyt b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/sky130A.lyt new file mode 100755 index 000000000..9a48d2c10 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/libs.tech/klayout/sky130A.lyt @@ -0,0 +1,200 @@ + + + sky130A_el + sky130A Elements + + 0.001 + + sky130A.lyp + true + + + 1 + true + true + + + true + layer_map('66/15 : PY_SHORT';'72/15 : M5_SHORT';'81/14 : LDID';'122/16 : PWELL_PIN';'64/5 : NWELLLABEL';'64/16 : NWELLPT';'64/59 : PWELLLABEL';'64/20 : NWELL';'64/18 : DNWELL';'65/20 : DIFF';'65/44 : TAP';'125/44 : LVTN';'78/44 : HVTP';'75/20 : HVI';'80/20 : TUNM';'66/20 : POLY';'95/20 : NPC';'94/20 : PSDM';'93/44 : NSDM';'66/44 : LICON1';'67/20 : LI1';'67/16 : LI1T';'67/5 : LI1P';'67/44 : MCON';'68/20 : MET1';'68/16 : MET1T';'68/5 : MET1P';'68/44 : VIA1';'69/20 : MET2';'69/16 : MET2T';'69/5 : MET2P';'69/44 : VIA2';'70/20 : MET3';'70/16 : MET3T';'70/5 : MET3P';'70/44 : VIA3';'71/20 : MET4';'71/16 : MET4T';'71/5 : MET4P';'71/44 : VIA4';'72/20 : MET5';'72/16 : MET5T';'72/5 : MET5P';'76/20 : PAD';'76/16 : PADT';'76/5 : PADP';'81/4 : BOUND';'83/44 : TEXT';'18/20 : HVTR';'92/44 : NCM';'86/20 : RPM';'61/20 : NSM';'74/20 : RDL';'74/21 : VHVI';'11/44 : LDNTM';'125/20 : HVNTM';'85/44 : PMM';'82/44 : PNP';'82/64 : CAP';'82/24 : IND';'64/13 : PWRES';'66/13 : POLYRES';'65/13 : DIFFRES';'81/23 : DIODE') + true + true + + + true + layer_map('met1 : met1.drawing (68/20)';'met1.LABEL : met1.label (68/5)';'met1.PIN : met1.pin (68/16)';'via : via.drawing (68/44)';'met2 : met2.drawing (69/20)';'met2.LABEL : met2.label (69/5)';'met2.PIN : met2.pin (69/16)';'via2 : via2.drawing (69/44)';'met3 : met3.drawing (70/20)';'met3.LABEL : met3.label (70/5)';'met3.PIN : met3.pin (70/16)';'via3 : via3.drawing (70/44)';'met4 : met4.drawing (71/20)';'met4.LABEL : met4.label (71/5)';'met4.PIN : met4.pin (71/16)';'via4 : via4.drawing (71/44)';'met5 : met5.drawing (72/20)';'met5.LABEL : met5.label (72/5)';'met5.PIN : met5.pin (72/16)') + 0.001 + true + #1 + true + #1 + false + #1 + true + OUTLINE + true + PLACEMENT_BLK + true + REGIONS + true + + 0 + true + .PIN + 2 + true + .PIN + 2 + true + .FILL + 5 + true + .OBS + 3 + true + .BLK + 4 + true + .LABEL + 1 + true + .LABEL + 1 + true + + 0 + true + + 0 + VIA_ + true + default + false + false + + + + false + true + true + 64 + 0 + 1 + 0 + DATA + 0 + 0 + BORDER + layer_map() + true + + + 0.001 + 1 + 100 + 100 + 0 + 0 + 0 + false + false + false + true + layer_map() + + + 0 + 0.001 + layer_map() + true + false + + + 1 + 0.001 + layer_map() + true + false + true + + + + + + GDS2 + + true + false + false + false + false + false + 8000 + 32000 + LIB + + + 2 + false + false + 1 + * + false + + + 0 + + + false + false + + + 0 + + true + + + + + + + MET4,VIA4,MET5 + MET3,VIA3,MET4 + MET2,VIA2,MET3 + MET1,VIA1,MET2 + LI,MCON,MET1 + POLY,LICON,LI + POLY='66/20' + LICON='66/44' + LI='67/20' + MCON='67/44' + MET1='68/20' + VIA1='68/44' + MET2='69/20' + VIA2='69/44' + MET3='70/20' + VIA3='70/44' + MET4='71/20' + VIA4='71/44' + META5='72/20' + + MET4,VIA4,MET5 + MET3,VIA3,MET4 + MET2,VIA2,MET3 + MET1,VIA1,MET2 + LI,MCON,MET1 + POLY,LICON,LI + POLY='66/20' + LICON='66/44' + LI='67/20' + MCON='67/44' + MET1='68/20' + VIA1='68/44' + MET2='69/20' + VIA2='69/44' + MET3='70/20' + VIA3='70/44' + MET4='71/20' + VIA4='71/44' + META5='72/20' + + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/meson.build b/pdks/symbolic/lsxlib/sky130_lsx/meson.build new file mode 100644 index 000000000..b31918816 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/meson.build @@ -0,0 +1,38 @@ + +project( + 'pdk_sky130_lsx', + version: '0.1.0', + meson_version: '>= 1.2.0', + default_options: ['warning_level=3'] +) + +python = import('python') +py = python.find_installation('python3') +py_deps = py.dependency() + +pdks_dir = py.get_install_dir() / 'pdks' / 'sky130_lsx' + +find_py = 'find libs.tech/coriolis -type f -name "*.py"' +res = run_command('sh', '-c', find_py, check:true) +py_files = res.stdout().strip().split('\n') + +data_files = [ + 'libs.tech/coriolis/sky130_lsx/sky130_lsx.rds', + 'libs.tech/coriolis/sky130_lsx/symbolic.graal', + 'libs.tech/coriolis/sky130_lsx/symbolic.rds', + 'libs.tech/coriolis/sky130_lsx/lsxlib.lib', + 'libs.tech/coriolis/sky130_lsx/spimodel.cfg', +] + +find_spi = 'find libs.tech/coriolis -type f -name "*.spi"' +res = run_command('sh', '-c', find_spi, check:true) +spi_files = res.stdout().strip().split('\n') + +# *.exp and *.cir files are used for library generation and are not required in PDK packaging + +py.install_sources( files(py_files) , subdir: 'pdks/sky130_lsx' ) +py.install_sources( files(data_files) , subdir: 'pdks/sky130_lsx' ) +py.install_sources( files(spi_files) , subdir: 'pdks/sky130_lsx' ) + +install_subdir( 'libs.tech/klayout' , install_dir: pdks_dir ) + diff --git a/pdks/symbolic/lsxlib/sky130_lsx/pyproject.toml b/pdks/symbolic/lsxlib/sky130_lsx/pyproject.toml new file mode 100644 index 000000000..4721f0307 --- /dev/null +++ b/pdks/symbolic/lsxlib/sky130_lsx/pyproject.toml @@ -0,0 +1,25 @@ +[project] +name = "pdk_sky130_lsx" +version = "0.1.0" +description = "Sky130 lsxlib PDK for Coriolis EDA" +authors = [ { name = "Coriolis EDA Contributers" } ] +requires-python = ">= 3.8" + +[build-system] +requires = [ + "meson", + "meson-python", + "ninja", + "setuptools", + "cibuildwheel", + "build", + "pdm-backend" +] +build-backend = "mesonpy" + +[tool.meson] +build-dir = "build" + +[tool.cibuildwheel] +build = "cp310-*" +skip = ["cp36-*", "cp37-*", "pp*"] diff --git a/pdks/symbolic/meson.build b/pdks/symbolic/meson.build new file mode 100644 index 000000000..10001b516 --- /dev/null +++ b/pdks/symbolic/meson.build @@ -0,0 +1,31 @@ + +project( + 'pdk_symbolic_cells', + version: '0.1.0', + meson_version: '>= 1.2.0', + default_options: ['warning_level=3'] +) + +python = import('python') +py = python.find_installation('python3') +py_deps = py.dependency() + +pdks_dir = py.get_install_dir() / 'pdks' / 'symbolic' / 'cells' + +py.install_sources('__init__.py', subdir: 'pdks/symbolic' ) + +install_subdir( 'lsxlib/cells' , strip_directory:true, install_dir: pdks_dir / 'lsxlib' ) +install_subdir( 'niolib/cells' , strip_directory:true, install_dir: pdks_dir / 'niolib' ) +install_subdir( 'nsxlib2/cells' , strip_directory:true, install_dir: pdks_dir / 'nsxlib2' ) +install_subdir( 'vsclib/cells' , strip_directory:true, install_dir: pdks_dir / 'vsclib' ) +install_subdir( 'sxlib/cells' , strip_directory:true, install_dir: pdks_dir / 'sxlib' ) +install_subdir( 'hibikino/cells' , strip_directory:true, install_dir: pdks_dir / 'hibikino' ) +install_subdir( 'mpxlib/cells' , strip_directory:true, install_dir: pdks_dir / 'mpxlib' ) +install_subdir( 'msplib/cells' , strip_directory:true, install_dir: pdks_dir / 'msplib' ) +install_subdir( 'msxlib/cells' , strip_directory:true, install_dir: pdks_dir / 'msxlib' ) +install_subdir( 'nramlib/cells' , strip_directory:true, install_dir: pdks_dir / 'nramlib' ) +install_subdir( 'nrf2lib/cells' , strip_directory:true, install_dir: pdks_dir / 'nrf2lib' ) +install_subdir( 'nrflib/cells' , strip_directory:true, install_dir: pdks_dir / 'nrflib' ) +install_subdir( 'nsxlib/cells' , strip_directory:true, install_dir: pdks_dir / 'nsxlib' ) +install_subdir( 'phlib/cells' , strip_directory:true, install_dir: pdks_dir / 'phlib' ) +install_subdir( 'phlib80/cells' , strip_directory:true, install_dir: pdks_dir / 'phlib80' ) diff --git a/pdks/symbolic/mpxlib/cells/CATAL b/pdks/symbolic/mpxlib/cells/CATAL new file mode 100644 index 000000000..6b55fa38d --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/CATAL @@ -0,0 +1,13 @@ +pck_mpx C +piot_mpx C +pi_mpx C +po_mpx C +pot_mpx C +pvddeck_mpx C +pvdde_mpx C +pvddick_mpx C +pvddi_mpx C +pvsseck_mpx C +pvsse_mpx C +pvssick_mpx C +pvssi_mpx C diff --git a/pdks/symbolic/mpxlib/cells/padreal_mpx.ap b/pdks/symbolic/mpxlib/cells/padreal_mpx.ap new file mode 100644 index 000000000..375513e37 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/padreal_mpx.ap @@ -0,0 +1,5 @@ +V ALLIANCE : 6 +H padreal_mpx,P,17/9/2014,100 +A 0,0,40000,40000 +S 20000,8100,20000,31900,24400,pad,UP,CALU1 +EOF diff --git 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34800,23000,300,300,CONT_VIA2,682nymous_ +B 17800,23200,300,300,CONT_DIF_N,1167ymous_ +B 1600,29400,300,300,CONT_BODY_P,1113ymous_ +B 33200,17000,300,300,CONT_VIA2,628nymous_ +B 32000,11000,300,300,CONT_POLY,574nymous_ +B 2800,23000,300,300,CONT_DIF_N,467nymous_ +B 30400,36600,300,300,CONT_POLY,521nymous_ +B 14000,6000,300,300,CONT_BODY_P,1059ymous_ +B 26000,12000,300,300,CONT_DIF_P,413nymous_ +B 30600,22000,300,300,CONT_DIF_P,524nymous_ +B 17800,24400,300,300,CONT_VIA2,1170ymous_ +B 1600,32400,300,300,CONT_BODY_P,1116ymous_ +B 32000,17000,300,300,CONT_VIA2,577nymous_ +B 26000,17000,300,300,CONT_VIA,416nymous_ +B 14000,10000,300,300,CONT_POLY,1062ymous_ +B 11600,14800,300,300,CONT_DIF_P,1008ymous_ +B 25000,20400,300,300,CONT_VIA,362nymous_ +B 19800,26200,300,300,CONT_POLY,1222ymous_ +B 8800,37600,300,300,CONT_VIA,954nymous_ +B 7600,21800,300,300,CONT_POLY,900nymous_ +B 4400,6000,300,300,CONT_VIA2,846nymous_ +B 38200,23400,300,300,CONT_BODY_N,792nymous_ +B 36800,15000,300,300,CONT_VIA2,738nymous_ +B 17800,24400,300,300,CONT_DIF_N,1169ymous_ +B 34800,28000,300,300,CONT_VIA2,684nymous_ +B 33800,22000,300,300,CONT_VIA,630nymous_ +B 30400,36600,300,300,CONT_VIA2,523nymous_ +B 1600,31400,300,300,CONT_BODY_P,1115ymous_ +B 14000,8000,300,300,CONT_DIF_N,1061ymous_ +B 32000,17000,300,300,CONT_VIA,576nymous_ +B 26000,16000,300,300,CONT_BODY_N,415nymous_ +B 2800,25000,300,300,CONT_DIF_N,469nymous_ +B 19800,22600,300,300,CONT_POLY,1221ymous_ +B 11600,13800,300,300,CONT_DIF_P,1007ymous_ +B 8800,37600,300,300,CONT_BODY_P,953nymous_ +B 25000,20400,300,300,CONT_DIF_P,361nymous_ +B 6800,17000,300,300,CONT_VIA2,899nymous_ +B 25000,22800,300,300,CONT_DIF_P,364nymous_ +B 19800,28200,300,300,CONT_VIA,1224ymous_ +B 11600,17000,300,300,CONT_VIA,1010ymous_ +B 9200,23000,300,300,CONT_DIF_N,956nymous_ +B 7600,23000,300,300,CONT_DIF_N,902nymous_ +B 4400,17000,300,300,CONT_VIA,848nymous_ +B 38200,25400,300,300,CONT_BODY_N,794nymous_ +B 36800,16000,300,300,CONT_VIA2,740nymous_ +B 34800,33000,300,300,CONT_VIA2,686nymous_ +B 17800,25600,300,300,CONT_DIF_N,1171ymous_ +B 1600,33400,300,300,CONT_BODY_P,1117ymous_ +B 33800,23000,300,300,CONT_DIF_P,632nymous_ +B 32000,19200,300,300,CONT_BODY_N,578nymous_ +B 2800,27000,300,300,CONT_DIF_N,471nymous_ +B 30600,23000,300,300,CONT_DIF_P,525nymous_ +B 14000,12000,300,300,CONT_DIF_P,1063ymous_ +B 11600,16000,300,300,CONT_BODY_N,1009ymous_ +B 25000,21600,300,300,CONT_DIF_P,363nymous_ +B 26000,17000,300,300,CONT_VIA2,417nymous_ +B 19800,27400,300,300,CONT_POLY,1223ymous_ +B 8800,37600,300,300,CONT_VIA2,955nymous_ +B 7600,21800,300,300,CONT_VIA,901nymous_ +B 4400,16000,300,300,CONT_BODY_N,847nymous_ +B 38200,24400,300,300,CONT_BODY_N,793nymous_ +B 36800,16000,300,300,CONT_BODY_N,739nymous_ +B 34800,29000,300,300,CONT_VIA2,685nymous_ +B 33800,22000,300,300,CONT_VIA2,631nymous_ +B 2800,26000,300,300,CONT_DIF_N,470nymous_ +B 7600,24000,300,300,CONT_DIF_N,904nymous_ +B 4600,37600,300,300,CONT_BODY_P,850nymous_ +B 38200,27400,300,300,CONT_BODY_N,796nymous_ +B 36800,17000,300,300,CONT_VIA2,742nymous_ +B 17800,25600,300,300,CONT_VIA2,1173ymous_ +B 34800,35000,300,300,CONT_VIA2,688nymous_ +B 33800,23000,300,300,CONT_VIA2,634nymous_ +B 30600,25000,300,300,CONT_DIF_P,527nymous_ +B 1600,35400,300,300,CONT_BODY_P,1119ymous_ +B 14000,13800,300,300,CONT_DIF_P,1065ymous_ +B 3200,6000,300,300,CONT_VIA,580nymous_ +B 2600,37600,300,300,CONT_BODY_P,419nymous_ +B 2800,29000,300,300,CONT_DIF_N,473nymous_ +B 19800,31000,300,300,CONT_POLY,1225ymous_ +B 11600,17000,300,300,CONT_VIA2,1011ymous_ +B 9200,24000,300,300,CONT_DIF_N,957nymous_ +B 25000,22800,300,300,CONT_VIA,365nymous_ +B 7600,23000,300,300,CONT_VIA,903nymous_ +B 4400,17000,300,300,CONT_VIA2,849nymous_ +B 38200,26400,300,300,CONT_BODY_N,795nymous_ +B 36800,17000,300,300,CONT_VIA,741nymous_ +B 17800,25600,300,300,CONT_VIA,1172ymous_ +B 34800,34000,300,300,CONT_VIA2,687nymous_ +B 33800,23000,300,300,CONT_VIA,633nymous_ +B 2800,28000,300,300,CONT_DIF_N,472nymous_ +B 30600,24000,300,300,CONT_DIF_P,526nymous_ +B 1600,34400,300,300,CONT_BODY_P,1118ymous_ +B 14000,12800,300,300,CONT_DIF_P,1064ymous_ +B 3200,6000,300,300,CONT_BODY_P,579nymous_ +B 26000,19200,300,300,CONT_BODY_N,418nymous_ +B 2800,30000,300,300,CONT_DIF_N,474nymous_ +B 14000,14800,300,300,CONT_DIF_P,1066ymous_ +B 11600,19200,300,300,CONT_BODY_P,1012ymous_ +B 25000,24000,300,300,CONT_DIF_P,366nymous_ +B 19800,35200,300,300,CONT_VIA,1226ymous_ +B 9200,25000,300,300,CONT_DIF_N,958nymous_ +B 2600,19200,300,300,CONT_BODY_P,420nymous_ +B 3200,6000,300,300,CONT_VIA2,581nymous_ +B 33800,24000,300,300,CONT_DIF_P,635nymous_ +B 1600,36400,300,300,CONT_BODY_P,1120ymous_ +B 17800,26800,300,300,CONT_DIF_N,1174ymous_ +B 30600,26000,300,300,CONT_DIF_P,528nymous_ +B 35000,19200,300,300,CONT_BODY_N,689nymous_ +B 37000,22000,300,300,CONT_DIF_P,743nymous_ +B 38200,28400,300,300,CONT_BODY_N,797nymous_ +B 4600,37600,300,300,CONT_VIA,851nymous_ +B 7600,24000,300,300,CONT_VIA,905nymous_ +B 9200,26000,300,300,CONT_DIF_N,959nymous_ +B 19800,37600,300,300,CONT_BODY_P,1227ymous_ +B 27000,20400,300,300,CONT_DIF_P,421nymous_ +B 25000,25200,300,300,CONT_DIF_P,367nymous_ +B 12400,23000,300,300,CONT_DIF_N,1013ymous_ +B 14000,16000,300,300,CONT_BODY_N,1067ymous_ +B 30600,27000,300,300,CONT_DIF_P,529nymous_ +B 2800,31000,300,300,CONT_DIF_N,475nymous_ +B 3200,7000,300,300,CONT_BODY_P,582nymous_ +B 33800,24000,300,300,CONT_VIA,636nymous_ +B 1600,37600,300,300,CONT_BODY_P,1121ymous_ +B 35400,22000,300,300,CONT_DIF_P,690nymous_ +B 37000,22000,300,300,CONT_VIA,744nymous_ +B 38200,29400,300,300,CONT_BODY_N,798nymous_ +B 4600,37600,300,300,CONT_VIA2,852nymous_ +B 7600,24000,300,300,CONT_VIA2,906nymous_ +B 9200,27000,300,300,CONT_DIF_N,960nymous_ +B 12400,24000,300,300,CONT_DIF_N,1014ymous_ +B 27000,21600,300,300,CONT_DIF_P,422nymous_ +B 25000,26400,300,300,CONT_DIF_P,368nymous_ +B 3200,7000,300,300,CONT_VIA2,583nymous_ +B 14000,17000,300,300,CONT_VIA,1068ymous_ +B 1600,19200,300,300,CONT_BODY_P,1122ymous_ +B 30600,27000,300,300,CONT_VIA,530nymous_ +B 2800,32000,300,300,CONT_DIF_N,476nymous_ +B 33800,25000,300,300,CONT_DIF_P,637nymous_ +B 35400,23000,300,300,CONT_DIF_P,691nymous_ +B 17800,28000,300,300,CONT_VIA,1176ymous_ +B 37000,22000,300,300,CONT_VIA2,745nymous_ +B 38200,30400,300,300,CONT_BODY_N,799nymous_ +B 4600,19200,300,300,CONT_BODY_P,853nymous_ +B 7600,25000,300,300,CONT_DIF_N,907nymous_ +B 25000,27600,300,300,CONT_DIF_P,369nymous_ +B 9200,28000,300,300,CONT_DIF_N,961nymous_ +B 12400,25000,300,300,CONT_DIF_N,1015ymous_ +B 27000,22800,300,300,CONT_DIF_P,423nymous_ +B 14000,17000,300,300,CONT_VIA2,1069ymous_ +B 2800,33000,300,300,CONT_DIF_N,477nymous_ +B 3200,8000,300,300,CONT_BODY_P,584nymous_ +B 16400,4000,300,300,CONT_VIA2,1123ymous_ +B 30600,27000,300,300,CONT_VIA2,531nymous_ +B 33800,25000,300,300,CONT_VIA,638nymous_ +B 35400,24000,300,300,CONT_DIF_P,692nymous_ +B 17800,29200,300,300,CONT_DIF_N,1177ymous_ +B 37000,23000,300,300,CONT_DIF_P,746nymous_ +B 38200,31400,300,300,CONT_BODY_N,800nymous_ +B 5400,24000,300,300,CONT_VIA2,854nymous_ +B 7600,25000,300,300,CONT_VIA,908nymous_ +B 9200,29000,300,300,CONT_DIF_N,962nymous_ +B 25000,27600,300,300,CONT_VIA,370nymous_ +B 12400,26000,300,300,CONT_DIF_N,1016ymous_ +B 14600,19200,300,300,CONT_BODY_P,1070ymous_ +B 2800,34000,300,300,CONT_DIF_N,478nymous_ +B 27000,24000,300,300,CONT_DIF_P,424nymous_ +B 3200,8000,300,300,CONT_VIA2,585nymous_ +B 33800,26000,300,300,CONT_DIF_P,639nymous_ +B 16400,6000,300,300,CONT_BODY_P,1124ymous_ +B 17800,30400,300,300,CONT_DIF_N,1178ymous_ +B 30600,28000,300,300,CONT_DIF_P,532nymous_ +B 35400,25000,300,300,CONT_DIF_P,693nymous_ +B 37000,23000,300,300,CONT_VIA,747nymous_ +B 38200,32400,300,300,CONT_BODY_N,801nymous_ +B 5400,25000,300,300,CONT_VIA2,855nymous_ +B 7600,25000,300,300,CONT_VIA2,909nymous_ +B 9200,30000,300,300,CONT_DIF_N,963nymous_ +B 12400,27000,300,300,CONT_DIF_N,1017ymous_ +B 27000,25200,300,300,CONT_DIF_P,425nymous_ +B 25000,28800,300,300,CONT_DIF_P,371nymous_ +B 15200,4000,300,300,CONT_VIA2,1071ymous_ +B 30600,28000,300,300,CONT_VIA,533nymous_ +B 2800,35000,300,300,CONT_DIF_N,479nymous_ +B 3200,9000,300,300,CONT_BODY_P,586nymous_ +B 33800,26000,300,300,CONT_VIA,640nymous_ +B 16400,7200,300,300,CONT_DIF_N,1125ymous_ +B 17800,30400,300,300,CONT_VIA,1179ymous_ +B 35400,26000,300,300,CONT_DIF_P,694nymous_ +B 37000,23000,300,300,CONT_VIA2,748nymous_ +B 38200,33400,300,300,CONT_BODY_N,802nymous_ +B 5400,26000,300,300,CONT_VIA2,856nymous_ +B 7600,26000,300,300,CONT_DIF_N,910nymous_ +B 9200,31000,300,300,CONT_DIF_N,964nymous_ +B 12400,28000,300,300,CONT_DIF_N,1018ymous_ +B 27000,25200,300,300,CONT_VIA,426nymous_ +B 25000,30000,300,300,CONT_DIF_P,372nymous_ +B 3200,12000,300,300,CONT_BODY_N,587nymous_ +B 15200,6000,300,300,CONT_BODY_P,1072ymous_ +B 16400,8000,300,300,CONT_DIF_N,1126ymous_ +B 30600,28000,300,300,CONT_VIA2,534nymous_ +B 2800,36000,300,300,CONT_DIF_N,480nymous_ +B 33800,27000,300,300,CONT_DIF_P,641nymous_ +B 35400,27000,300,300,CONT_DIF_P,695nymous_ +B 37000,24000,300,300,CONT_DIF_P,749nymous_ +B 38200,34400,300,300,CONT_BODY_N,803nymous_ +B 5400,30000,300,300,CONT_VIA2,857nymous_ +B 7600,26000,300,300,CONT_VIA,911nymous_ +B 25000,30000,300,300,CONT_VIA,373nymous_ +B 9200,32000,300,300,CONT_DIF_N,965nymous_ +B 12400,29000,300,300,CONT_DIF_N,1019ymous_ +B 28400,6000,300,300,CONT_BODY_P,481nymous_ +B 27000,26400,300,300,CONT_DIF_P,427nymous_ +B 3200,12000,300,300,CONT_VIA2,588nymous_ +B 15200,8000,300,300,CONT_DIF_N,1073ymous_ +B 16400,10000,300,300,CONT_POLY,1127ymous_ +B 30600,29000,300,300,CONT_DIF_P,535nymous_ +B 33800,27000,300,300,CONT_VIA,642nymous_ +B 35400,28000,300,300,CONT_DIF_P,696nymous_ +B 37000,24000,300,300,CONT_VIA,750nymous_ +B 38200,35400,300,300,CONT_BODY_N,804nymous_ +B 5400,31000,300,300,CONT_VIA2,858nymous_ +B 7600,26000,300,300,CONT_VIA2,912nymous_ +B 9200,33000,300,300,CONT_DIF_N,966nymous_ +B 25000,31200,300,300,CONT_DIF_P,374nymous_ +B 12400,30000,300,300,CONT_DIF_N,1020ymous_ +B 15200,9000,300,300,CONT_DIF_N,1074ymous_ +B 27000,27600,300,300,CONT_DIF_P,428nymous_ +B 3200,13000,300,300,CONT_BODY_N,589nymous_ +B 16400,12000,300,300,CONT_DIF_P,1128ymous_ +B 30600,29000,300,300,CONT_VIA,536nymous_ +B 28400,6000,300,300,CONT_VIA,482nymous_ +B 33800,27000,300,300,CONT_VIA2,643nymous_ +B 17800,31600,300,300,CONT_VIA2,1182ymous_ +B 35400,29000,300,300,CONT_DIF_P,697nymous_ +B 37000,25000,300,300,CONT_DIF_P,751nymous_ +B 38200,36400,300,300,CONT_BODY_N,805nymous_ +B 5400,32000,300,300,CONT_VIA2,859nymous_ +B 7600,27000,300,300,CONT_DIF_N,913nymous_ +B 9200,34000,300,300,CONT_DIF_N,967nymous_ +B 27000,28800,300,300,CONT_DIF_P,429nymous_ +B 25000,32400,300,300,CONT_DIF_P,375nymous_ +B 12400,31000,300,300,CONT_DIF_N,1021ymous_ +B 15200,9000,300,300,CONT_VIA,1075ymous_ +B 30600,29000,300,300,CONT_VIA2,537nymous_ +B 28400,6000,300,300,CONT_VIA2,483nymous_ +B 3200,13000,300,300,CONT_VIA2,590nymous_ +B 33800,28000,300,300,CONT_DIF_P,644nymous_ +B 16400,12800,300,300,CONT_DIF_P,1129ymous_ +B 35400,30000,300,300,CONT_DIF_P,698nymous_ +B 37000,25000,300,300,CONT_VIA,752nymous_ +B 38200,37600,300,300,CONT_BODY_N,806nymous_ +B 5400,36000,300,300,CONT_VIA2,860nymous_ +B 7600,27000,300,300,CONT_VIA,914nymous_ +B 9200,35000,300,300,CONT_DIF_N,968nymous_ +B 12400,32000,300,300,CONT_DIF_N,1022ymous_ +B 25000,32400,300,300,CONT_VIA,376nymous_ +B 17800,32800,300,300,CONT_DIF_N,1183ymous_ +B 27000,30000,300,300,CONT_DIF_P,430nymous_ +B 3200,14000,300,300,CONT_BODY_N,591nymous_ +B 15200,10000,300,300,CONT_POLY,1076ymous_ +B 16400,13800,300,300,CONT_DIF_P,1130ymous_ +B 30600,30000,300,300,CONT_DIF_P,538nymous_ +B 28400,8000,300,300,CONT_DIF_N,484nymous_ +B 33800,28000,300,300,CONT_VIA,645nymous_ +B 35400,31000,300,300,CONT_DIF_P,699nymous_ +B 17800,34000,300,300,CONT_DIF_N,1184ymous_ +B 37000,26000,300,300,CONT_DIF_P,753nymous_ +B 38200,19200,300,300,CONT_BODY_N,807nymous_ +B 5600,37600,300,300,CONT_BODY_P,861nymous_ +B 7600,28000,300,300,CONT_DIF_N,915nymous_ +B 25000,33600,300,300,CONT_DIF_P,377nymous_ +B 9200,36000,300,300,CONT_DIF_N,969nymous_ +B 12400,33000,300,300,CONT_DIF_N,1023ymous_ +B 28400,9000,300,300,CONT_DIF_N,485nymous_ +B 27000,31200,300,300,CONT_DIF_P,431nymous_ +B 3200,14000,300,300,CONT_VIA2,592nymous_ +B 15200,11000,300,300,CONT_VIA,1077ymous_ +B 16400,14800,300,300,CONT_DIF_P,1131ymous_ +B 30600,30000,300,300,CONT_VIA,539nymous_ +B 33800,28000,300,300,CONT_VIA2,646nymous_ +B 35400,32000,300,300,CONT_DIF_P,700nymous_ +B 37000,26000,300,300,CONT_VIA,754nymous_ +B 4400,21800,300,300,CONT_POLY,808nymous_ +B 5600,37600,300,300,CONT_VIA,862nymous_ +B 7600,28000,300,300,CONT_VIA,916nymous_ +B 17800,30400,300,300,CONT_VIA2,1180ymous_ +B 17800,31600,300,300,CONT_DIF_N,1181ymous_ +B 17800,35200,300,300,CONT_DIF_N,1185ymous_ +B 9200,6000,300,300,CONT_BODY_P,970nymous_ +B 25000,35000,300,300,CONT_DIF_P,378nymous_ +B 12400,34000,300,300,CONT_DIF_N,1024ymous_ +B 15200,11800,300,300,CONT_DIF_P,1078ymous_ +B 28400,10000,300,300,CONT_POLY,486nymous_ +B 27000,32400,300,300,CONT_DIF_P,432nymous_ +B 3200,15000,300,300,CONT_BODY_N,593nymous_ +B 33800,29000,300,300,CONT_DIF_P,647nymous_ +B 16400,16000,300,300,CONT_BODY_N,1132ymous_ +B 35400,33000,300,300,CONT_DIF_P,701nymous_ +B 37000,27000,300,300,CONT_DIF_P,755nymous_ +B 4400,21800,300,300,CONT_VIA,809nymous_ +B 5600,37600,300,300,CONT_VIA2,863nymous_ +B 7600,29000,300,300,CONT_DIF_N,917nymous_ +B 9200,6000,300,300,CONT_VIA2,971nymous_ +B 27000,33600,300,300,CONT_DIF_P,433nymous_ +B 25000,36400,300,300,CONT_DIF_P,379nymous_ +B 12400,35000,300,300,CONT_DIF_N,1025ymous_ +B 15200,12800,300,300,CONT_DIF_P,1079ymous_ +B 28400,12000,300,300,CONT_DIF_P,487nymous_ +B 3200,16000,300,300,CONT_BODY_N,594nymous_ +B 33800,29000,300,300,CONT_VIA,648nymous_ +B 16400,17000,300,300,CONT_VIA,1133ymous_ +B 17800,36400,300,300,CONT_DIF_N,1186ymous_ +B 17800,37600,300,300,CONT_BODY_P,1187ymous_ +B 35400,34000,300,300,CONT_DIF_P,702nymous_ +B 37000,27000,300,300,CONT_VIA,756nymous_ +B 4400,23000,300,300,CONT_DIF_N,810nymous_ +B 5600,6000,300,300,CONT_BODY_P,864nymous_ +B 7600,29000,300,300,CONT_VIA,918nymous_ +B 9200,16000,300,300,CONT_BODY_N,972nymous_ +B 12400,36000,300,300,CONT_DIF_N,1026ymous_ +B 27000,35000,300,300,CONT_DIF_P,434nymous_ +B 25000,37600,300,300,CONT_BODY_N,380nymous_ +B 3200,17000,300,300,CONT_VIA,595nymous_ +B 15200,13800,300,300,CONT_DIF_P,1080ymous_ +B 16400,17000,300,300,CONT_VIA2,1134ymous_ +B 28400,12800,300,300,CONT_DIF_P,488nymous_ +B 33800,29000,300,300,CONT_VIA2,649nymous_ +B 35400,35000,300,300,CONT_DIF_P,703nymous_ +B 37000,27000,300,300,CONT_VIA2,757nymous_ +B 4400,23000,300,300,CONT_VIA,811nymous_ +B 5600,6000,300,300,CONT_VIA2,865nymous_ +B 7600,30000,300,300,CONT_DIF_N,919nymous_ +B 25000,19200,300,300,CONT_BODY_N,381nymous_ +B 9200,17000,300,300,CONT_VIA,973nymous_ +B 12600,19200,300,300,CONT_BODY_P,1027ymous_ +B 27000,36400,300,300,CONT_DIF_P,435nymous_ +B 15200,16000,300,300,CONT_BODY_N,1081ymous_ +B 30600,32000,300,300,CONT_DIF_P,542nymous_ +B 18600,19200,300,300,CONT_BODY_P,1188ymous_ +B 28400,16000,300,300,CONT_BODY_N,489nymous_ +B 3200,17000,300,300,CONT_VIA2,596nymous_ +B 16600,19200,300,300,CONT_BODY_P,1135ymous_ +B 30600,32000,300,300,CONT_VIA,543nymous_ +B 33800,30000,300,300,CONT_DIF_P,650nymous_ +B 35400,36000,300,300,CONT_DIF_P,704nymous_ +B 18800,22000,300,300,CONT_DIF_N,1189ymous_ +B 37000,28000,300,300,CONT_DIF_P,758nymous_ +B 4400,24000,300,300,CONT_DIF_N,812nymous_ +B 5600,16000,300,300,CONT_BODY_N,866nymous_ +B 7600,30000,300,300,CONT_VIA,920nymous_ +B 9200,17000,300,300,CONT_VIA2,974nymous_ +B 26000,20400,300,300,CONT_DIF_P,382nymous_ +B 12800,4000,300,300,CONT_VIA2,1028ymous_ +B 15200,17000,300,300,CONT_VIA,1082ymous_ +B 28400,17000,300,300,CONT_VIA,490nymous_ +B 27000,36400,300,300,CONT_VIA,436nymous_ +B 32200,22000,300,300,CONT_DIF_P,597nymous_ +B 33800,30000,300,300,CONT_VIA,651nymous_ +B 16800,20200,300,300,CONT_VIA,1136ymous_ +B 35600,6000,300,300,CONT_BODY_P,705nymous_ +B 37000,28000,300,300,CONT_VIA,759nymous_ +B 4400,24000,300,300,CONT_VIA,813nymous_ +B 5600,17000,300,300,CONT_VIA,867nymous_ +B 7600,30000,300,300,CONT_VIA2,921nymous_ +B 9600,37600,300,300,CONT_BODY_P,975nymous_ +B 12800,6000,300,300,CONT_BODY_P,1029ymous_ +B 18800,22200,300,300,CONT_VIA,1190ymous_ +B 30600,33000,300,300,CONT_DIF_P,544nymous_ +B 27000,37600,300,300,CONT_BODY_N,437nymous_ +B 26000,21600,300,300,CONT_DIF_P,383nymous_ +B 15200,17000,300,300,CONT_VIA2,1083ymous_ +B 30600,33000,300,300,CONT_VIA,545nymous_ +B 28400,17000,300,300,CONT_VIA2,491nymous_ +B 32200,23000,300,300,CONT_DIF_P,598nymous_ +B 33800,31000,300,300,CONT_DIF_P,652nymous_ +B 16800,23400,300,300,CONT_POLY,1137ymous_ +B 35600,6000,300,300,CONT_VIA,706nymous_ +B 37000,28000,300,300,CONT_VIA2,760nymous_ +B 4400,24000,300,300,CONT_VIA2,814nymous_ +B 5600,17000,300,300,CONT_VIA2,868nymous_ +B 7600,31000,300,300,CONT_DIF_N,922nymous_ +B 9600,19200,300,300,CONT_BODY_P,976nymous_ +B 12800,8000,300,300,CONT_DIF_N,1030ymous_ +B 27000,19200,300,300,CONT_BODY_N,438nymous_ +B 26000,21600,300,300,CONT_VIA,384nymous_ +B 32200,24000,300,300,CONT_DIF_P,599nymous_ +B 15600,20200,300,300,CONT_VIA,1084ymous_ +B 16800,24400,300,300,CONT_VIA,1138ymous_ +B 29000,21000,300,300,CONT_POLY,492nymous_ +B 33800,31000,300,300,CONT_VIA,653nymous_ +B 35600,6000,300,300,CONT_VIA2,707nymous_ +B 37000,29000,300,300,CONT_DIF_P,761nymous_ +B 18800,23200,300,300,CONT_DIF_N,1191ymous_ +B 30600,33000,300,300,CONT_VIA2,546nymous_ +B 18800,24400,300,300,CONT_DIF_N,1192ymous_ +B 4400,25000,300,300,CONT_DIF_N,815nymous_ +B 5600,19200,300,300,CONT_BODY_P,869nymous_ +B 7600,31000,300,300,CONT_VIA,923nymous_ +B 26000,21600,300,300,CONT_VIA2,385nymous_ +B 10400,6000,300,300,CONT_BODY_P,977nymous_ +B 12800,9000,300,300,CONT_DIF_N,1031ymous_ +B 29000,21000,300,300,CONT_VIA,493nymous_ +B 27200,6000,300,300,CONT_BODY_P,439nymous_ +B 32200,25000,300,300,CONT_DIF_P,600nymous_ +B 15600,23000,300,300,CONT_DIF_N,1085ymous_ +B 16800,25400,300,300,CONT_POLY,1139ymous_ +B 30600,34000,300,300,CONT_DIF_P,547nymous_ +B 33800,32000,300,300,CONT_DIF_P,654nymous_ +B 35600,16000,300,300,CONT_BODY_N,708nymous_ +B 37000,29000,300,300,CONT_VIA,762nymous_ +B 4400,25000,300,300,CONT_VIA,816nymous_ +B 6000,23000,300,300,CONT_DIF_N,870nymous_ +B 7600,31000,300,300,CONT_VIA2,924nymous_ +B 10400,6000,300,300,CONT_VIA2,978nymous_ +B 26000,22800,300,300,CONT_DIF_P,386nymous_ +B 12800,9000,300,300,CONT_VIA,1032ymous_ +B 15600,24000,300,300,CONT_DIF_N,1086ymous_ +B 27200,6000,300,300,CONT_VIA,440nymous_ +B 12800,11800,300,300,CONT_DIF_P,1034ymous_ +B 10400,17000,300,300,CONT_VIA,980nymous_ +B 7600,32000,300,300,CONT_VIA,926nymous_ +B 6000,25000,300,300,CONT_DIF_N,872nymous_ +B 4400,26000,300,300,CONT_DIF_N,818nymous_ +B 37000,30000,300,300,CONT_DIF_P,764nymous_ +B 35600,17000,300,300,CONT_VIA2,710nymous_ +B 16800,29200,300,300,CONT_VIA,1141ymous_ +B 33800,33000,300,300,CONT_DIF_P,656nymous_ +B 32200,27000,300,300,CONT_DIF_P,602nymous_ +B 29000,22200,300,300,CONT_POLY,495nymous_ +B 15600,25000,300,300,CONT_DIF_N,1087ymous_ +B 18800,25600,300,300,CONT_DIF_N,1193ymous_ +B 29000,21000,300,300,CONT_VIA2,494nymous_ +B 32200,26000,300,300,CONT_DIF_P,601nymous_ +B 33800,32000,300,300,CONT_VIA,655nymous_ +B 16800,28200,300,300,CONT_POLY,1140ymous_ +B 18800,26800,300,300,CONT_DIF_N,1194ymous_ +B 30600,34000,300,300,CONT_VIA,548nymous_ +B 35600,17000,300,300,CONT_VIA,709nymous_ +B 37000,29000,300,300,CONT_VIA2,763nymous_ +B 4400,25000,300,300,CONT_VIA2,817nymous_ +B 6000,24000,300,300,CONT_DIF_N,871nymous_ +B 7600,32000,300,300,CONT_DIF_N,925nymous_ +B 10400,16000,300,300,CONT_BODY_N,979nymous_ +B 27200,6000,300,300,CONT_VIA2,441nymous_ +B 26000,22800,300,300,CONT_VIA2,387nymous_ +B 12800,11000,300,300,CONT_VIA,1033ymous_ +B 4400,26000,300,300,CONT_VIA,819nymous_ +B 36000,20200,300,300,CONT_POLY,711nymous_ +B 33800,33000,300,300,CONT_VIA,657nymous_ +B 29000,22200,300,300,CONT_VIA,496nymous_ +B 30600,35000,300,300,CONT_DIF_P,550nymous_ +B 16800,32200,300,300,CONT_POLY,1142ymous_ +B 15600,26000,300,300,CONT_DIF_N,1088ymous_ +B 32200,28000,300,300,CONT_DIF_P,603nymous_ +B 26000,24000,300,300,CONT_DIF_P,388nymous_ +B 27200,8000,300,300,CONT_DIF_N,442nymous_ +B 18800,26800,300,300,CONT_VIA,1195ymous_ +B 30600,34000,300,300,CONT_VIA2,549nymous_ +B 4400,26000,300,300,CONT_VIA2,820nymous_ +B 37000,31000,300,300,CONT_DIF_P,766nymous_ +B 36000,22000,300,300,CONT_VIA2,712nymous_ +B 33800,33000,300,300,CONT_VIA2,658nymous_ +B 16800,32200,300,300,CONT_VIA,1143ymous_ +B 15600,27000,300,300,CONT_DIF_N,1089ymous_ +B 32200,29000,300,300,CONT_DIF_P,604nymous_ +B 27200,9000,300,300,CONT_DIF_N,443nymous_ +B 29000,22200,300,300,CONT_VIA2,497nymous_ +B 12800,12800,300,300,CONT_DIF_P,1035ymous_ +B 10400,17000,300,300,CONT_VIA2,981nymous_ +B 26000,24000,300,300,CONT_VIA,389nymous_ +B 7600,32000,300,300,CONT_VIA2,927nymous_ +B 6000,26000,300,300,CONT_DIF_N,873nymous_ +B 37000,30000,300,300,CONT_VIA,765nymous_ +B 18800,28000,300,300,CONT_DIF_N,1196ymous_ +B 16800,33400,300,300,CONT_VIA,1145ymous_ +B 29000,23400,300,300,CONT_VIA,499nymous_ +B 15600,29000,300,300,CONT_DIF_N,1091ymous_ +B 12800,16000,300,300,CONT_BODY_N,1037ymous_ +B 26000,26400,300,300,CONT_DIF_P,391nymous_ +B 10800,21800,300,300,CONT_POLY,983nymous_ +B 7600,33000,300,300,CONT_VIA,929nymous_ +B 6000,28000,300,300,CONT_DIF_N,875nymous_ +B 4400,27000,300,300,CONT_DIF_N,821nymous_ +B 37000,31000,300,300,CONT_VIA,767nymous_ +B 36000,23000,300,300,CONT_VIA2,713nymous_ +B 30600,35000,300,300,CONT_VIA2,552nymous_ +B 16800,33400,300,300,CONT_POLY,1144ymous_ +B 33800,34000,300,300,CONT_DIF_P,659nymous_ +B 32200,30000,300,300,CONT_DIF_P,605nymous_ +B 27200,10000,300,300,CONT_POLY,444nymous_ +B 29000,23400,300,300,CONT_POLY,498nymous_ +B 15600,28000,300,300,CONT_DIF_N,1090ymous_ +B 12800,13800,300,300,CONT_DIF_P,1036ymous_ +B 26000,25200,300,300,CONT_DIF_P,390nymous_ +B 10600,19200,300,300,CONT_BODY_P,982nymous_ +B 7600,33000,300,300,CONT_DIF_N,928nymous_ +B 6000,27000,300,300,CONT_DIF_N,874nymous_ +B 18800,29200,300,300,CONT_DIF_N,1197ymous_ +B 30600,35000,300,300,CONT_VIA,551nymous_ +B 15600,31000,300,300,CONT_DIF_N,1093ymous_ +B 12800,17000,300,300,CONT_VIA2,1039ymous_ +B 10800,21800,300,300,CONT_VIA2,985nymous_ +B 7600,34000,300,300,CONT_VIA,931nymous_ +B 6000,30000,300,300,CONT_DIF_N,877nymous_ +B 4400,28000,300,300,CONT_DIF_N,823nymous_ +B 37000,32000,300,300,CONT_VIA,769nymous_ +B 36000,28000,300,300,CONT_VIA2,715nymous_ +B 33800,34000,300,300,CONT_VIA2,661nymous_ +B 29000,24600,300,300,CONT_POLY,500nymous_ +B 16800,33400,300,300,CONT_VIA2,1146ymous_ +B 15600,30000,300,300,CONT_DIF_N,1092ymous_ +B 32200,32000,300,300,CONT_DIF_P,607nymous_ +B 26000,26400,300,300,CONT_VIA,392nymous_ +B 27200,12600,300,300,CONT_DIF_P,446nymous_ +B 12800,17000,300,300,CONT_VIA,1038ymous_ +B 10800,21800,300,300,CONT_VIA,984nymous_ +B 7600,34000,300,300,CONT_DIF_N,930nymous_ +B 6000,29000,300,300,CONT_DIF_N,876nymous_ +B 4400,27000,300,300,CONT_VIA,822nymous_ +B 37000,32000,300,300,CONT_DIF_P,768nymous_ +B 36000,27000,300,300,CONT_VIA2,714nymous_ +B 18800,31600,300,300,CONT_DIF_N,1199ymous_ +B 33800,34000,300,300,CONT_VIA,660nymous_ +B 32200,31000,300,300,CONT_DIF_P,606nymous_ +B 30800,6000,300,300,CONT_BODY_P,553nymous_ +B 27200,11600,300,300,CONT_DIF_P,445nymous_ +B 18800,30400,300,300,CONT_DIF_N,1198ymous_ +B 6000,32000,300,300,CONT_DIF_N,879nymous_ +B 4400,29000,300,300,CONT_DIF_N,825nymous_ +B 37000,33000,300,300,CONT_VIA,771nymous_ +B 36000,33000,300,300,CONT_VIA2,717nymous_ +B 16800,34600,300,300,CONT_VIA,1148ymous_ +B 33800,35000,300,300,CONT_VIA,663nymous_ +B 32200,34000,300,300,CONT_DIF_P,609nymous_ +B 27200,17000,300,300,CONT_VIA,448nymous_ +B 29000,25800,300,300,CONT_POLY,502nymous_ +B 15600,32000,300,300,CONT_DIF_N,1094ymous_ +B 13600,19200,300,300,CONT_BODY_P,1040ymous_ +B 26000,27600,300,300,CONT_VIA2,394nymous_ +B 10800,23000,300,300,CONT_DIF_N,986nymous_ +B 7600,35000,300,300,CONT_DIF_N,932nymous_ +B 6000,31000,300,300,CONT_DIF_N,878nymous_ +B 4400,28000,300,300,CONT_VIA,824nymous_ +B 37000,33000,300,300,CONT_DIF_P,770nymous_ +B 36000,29000,300,300,CONT_VIA2,716nymous_ +B 33800,35000,300,300,CONT_DIF_P,662nymous_ +B 30800,6000,300,300,CONT_VIA2,555nymous_ +B 16800,34600,300,300,CONT_POLY,1147ymous_ +B 32200,33000,300,300,CONT_DIF_P,608nymous_ +B 27200,16000,300,300,CONT_BODY_N,447nymous_ +B 29000,24600,300,300,CONT_VIA,501nymous_ +B 26000,27600,300,300,CONT_DIF_P,393nymous_ +B 18800,31600,300,300,CONT_VIA,1200ymous_ +B 30800,6000,300,300,CONT_VIA,554nymous_ +B 18800,34000,300,300,CONT_DIF_N,1202ymous_ +B 29000,31800,300,300,CONT_POLY,504nymous_ +B 16800,35800,300,300,CONT_POLY,1150ymous_ +B 15600,34000,300,300,CONT_DIF_N,1096ymous_ +B 26000,28800,300,300,CONT_VIA,396nymous_ +B 27800,36400,300,300,CONT_DIF_P,450nymous_ +B 14000,21800,300,300,CONT_VIA,1042ymous_ +B 10800,25000,300,300,CONT_DIF_N,988nymous_ +B 7600,36000,300,300,CONT_DIF_N,934nymous_ +B 6000,33000,300,300,CONT_DIF_N,880nymous_ +B 4400,29000,300,300,CONT_VIA,826nymous_ +B 37000,33000,300,300,CONT_VIA2,772nymous_ +B 36000,34000,300,300,CONT_VIA2,718nymous_ +B 16800,34600,300,300,CONT_VIA2,1149ymous_ +B 33800,35000,300,300,CONT_VIA2,664nymous_ +B 32200,35000,300,300,CONT_DIF_P,610nymous_ +B 29000,30600,300,300,CONT_POLY,503nymous_ +B 30800,16000,300,300,CONT_BODY_N,557nymous_ +B 15600,33000,300,300,CONT_DIF_N,1095ymous_ +B 14000,21800,300,300,CONT_POLY,1041ymous_ +B 26000,28800,300,300,CONT_DIF_P,395nymous_ +B 27200,17000,300,300,CONT_VIA2,449nymous_ +B 10800,24000,300,300,CONT_DIF_N,987nymous_ +B 7600,35000,300,300,CONT_VIA,933nymous_ +B 30800,9000,300,300,CONT_DIF_N,556nymous_ +B 18800,32800,300,300,CONT_DIF_N,1201ymous_ +B 18800,34000,300,300,CONT_VIA,1203ymous_ +B 15600,36000,300,300,CONT_DIF_N,1098ymous_ +B 14000,23000,300,300,CONT_DIF_N,1044ymous_ +B 18800,35200,300,300,CONT_DIF_N,1204ymous_ +B 10800,27000,300,300,CONT_DIF_N,990nymous_ +B 7600,36000,300,300,CONT_VIA2,936nymous_ +B 6000,35000,300,300,CONT_DIF_N,882nymous_ +B 4400,30000,300,300,CONT_VIA,828nymous_ +B 37000,34000,300,300,CONT_VIA,774nymous_ +B 36000,19200,300,300,CONT_BODY_N,720nymous_ +B 33800,36000,300,300,CONT_VIA,666nymous_ +B 16800,35800,300,300,CONT_VIA,1151ymous_ +B 15600,35000,300,300,CONT_DIF_N,1097ymous_ +B 32800,20200,300,300,CONT_POLY,612nymous_ +B 27800,37600,300,300,CONT_BODY_N,451nymous_ +B 29000,33000,300,300,CONT_POLY,505nymous_ +B 14000,21800,300,300,CONT_VIA2,1043ymous_ +B 10800,26000,300,300,CONT_DIF_N,989nymous_ +B 26000,28800,300,300,CONT_VIA2,397nymous_ +B 7600,36000,300,300,CONT_VIA,935nymous_ +B 6000,34000,300,300,CONT_DIF_N,881nymous_ +B 4400,30000,300,300,CONT_DIF_N,827nymous_ +B 37000,34000,300,300,CONT_DIF_P,773nymous_ +B 36000,35000,300,300,CONT_VIA2,719nymous_ +B 33800,36000,300,300,CONT_DIF_P,665nymous_ +B 30800,17000,300,300,CONT_VIA,558nymous_ +B 32200,36000,300,300,CONT_DIF_P,611nymous_ +B 7800,37600,300,300,CONT_BODY_P,938nymous_ +B 6600,24000,300,300,CONT_VIA2,884nymous_ +B 4400,31000,300,300,CONT_DIF_N,830nymous_ +B 37000,35000,300,300,CONT_DIF_P,776nymous_ +B 3600,37600,300,300,CONT_VIA,722nymous_ +B 17600,4000,300,300,CONT_VIA2,1153ymous_ +B 3400,24000,300,300,CONT_VIA2,668nymous_ +B 32800,23000,300,300,CONT_VIA2,614nymous_ +B 29400,11800,300,300,CONT_POLY,507nymous_ +B 15600,19200,300,300,CONT_BODY_P,1099ymous_ +B 14000,24000,300,300,CONT_DIF_N,1045ymous_ +B 26000,31200,300,300,CONT_DIF_P,399nymous_ +B 28000,21600,300,300,CONT_DIF_P,453nymous_ +B 18800,36400,300,300,CONT_DIF_N,1205ymous_ +B 10800,28000,300,300,CONT_DIF_N,991nymous_ +B 7600,19200,300,300,CONT_BODY_P,937nymous_ +B 6000,36000,300,300,CONT_DIF_N,883nymous_ +B 4400,30000,300,300,CONT_VIA2,829nymous_ +B 37000,34000,300,300,CONT_VIA2,775nymous_ +B 3600,37600,300,300,CONT_BODY_P,721nymous_ +B 31000,19200,300,300,CONT_BODY_N,560nymous_ +B 16800,37600,300,300,CONT_BODY_P,1152ymous_ +B 34000,19200,300,300,CONT_BODY_N,667nymous_ +B 32800,22000,300,300,CONT_VIA2,613nymous_ +B 28000,20400,300,300,CONT_DIF_P,452nymous_ +B 29000,19200,300,300,CONT_BODY_N,506nymous_ +B 26000,30000,300,300,CONT_DIF_P,398nymous_ +B 30800,17000,300,300,CONT_VIA2,559nymous_ +B 17600,8000,300,300,CONT_DIF_N,1155ymous_ +B 15800,28000,300,300,CONT_VIA2,1101ymous_ +B 32800,28000,300,300,CONT_VIA2,616nymous_ +B 28000,24000,300,300,CONT_DIF_P,455nymous_ +B 14000,26000,300,300,CONT_DIF_N,1047ymous_ +B 10800,30000,300,300,CONT_DIF_N,993nymous_ +B 26000,32400,300,300,CONT_DIF_P,401nymous_ +B 18800,37600,300,300,CONT_BODY_P,1207ymous_ +B 7800,37600,300,300,CONT_VIA,939nymous_ +B 6600,25000,300,300,CONT_VIA2,885nymous_ +B 4400,31000,300,300,CONT_VIA,831nymous_ +B 37000,35000,300,300,CONT_VIA,777nymous_ +B 3600,37600,300,300,CONT_VIA2,723nymous_ +B 3400,25000,300,300,CONT_VIA2,669nymous_ +B 29600,33000,300,300,CONT_VIA2,508nymous_ +B 17600,6000,300,300,CONT_BODY_P,1154ymous_ +B 15800,27000,300,300,CONT_VIA2,1100ymous_ +B 32800,27000,300,300,CONT_VIA2,615nymous_ +B 26000,31200,300,300,CONT_VIA,400nymous_ +B 28000,22800,300,300,CONT_DIF_P,454nymous_ +B 14000,25000,300,300,CONT_DIF_N,1046ymous_ +B 10800,29000,300,300,CONT_DIF_N,992nymous_ +B 18800,36400,300,300,CONT_VIA,1206ymous_ +B 31600,20200,300,300,CONT_POLY,561nymous_ +B 31600,22000,300,300,CONT_VIA2,562nymous_ +B 36800,9000,300,300,CONT_VIA2,731nymous_ +B 14000,28000,300,300,CONT_DIF_N,1049ymous_ +B 18800,6000,300,300,CONT_VIA,1209ymous_ +B 10800,32000,300,300,CONT_DIF_N,995nymous_ +B 8000,6000,300,300,CONT_VIA2,941nymous_ +B 6600,30000,300,300,CONT_VIA2,887nymous_ +B 4400,32000,300,300,CONT_DIF_N,833nymous_ +B 37000,36000,300,300,CONT_DIF_P,779nymous_ +B 36800,6000,300,300,CONT_BODY_P,725nymous_ +B 17600,9000,300,300,CONT_DIF_N,1156ymous_ +B 3400,30000,300,300,CONT_VIA2,671nymous_ +B 32800,29000,300,300,CONT_VIA2,617nymous_ +B 28000,25200,300,300,CONT_DIF_P,456nymous_ +B 29600,35000,300,300,CONT_VIA2,510nymous_ +B 15800,29000,300,300,CONT_VIA2,1102ymous_ +B 14000,27000,300,300,CONT_DIF_N,1048ymous_ +B 26000,33600,300,300,CONT_DIF_P,402nymous_ +B 18800,6000,300,300,CONT_BODY_P,1208ymous_ +B 10800,31000,300,300,CONT_DIF_N,994nymous_ +B 7800,37600,300,300,CONT_VIA2,940nymous_ +B 6600,26000,300,300,CONT_VIA2,886nymous_ +B 4400,31000,300,300,CONT_VIA2,832nymous_ +B 37000,35000,300,300,CONT_VIA2,778nymous_ +B 3600,19200,300,300,CONT_BODY_P,724nymous_ +B 3400,26000,300,300,CONT_VIA2,670nymous_ +B 29600,34000,300,300,CONT_VIA2,509nymous_ +B 17800,28000,300,300,CONT_DIF_N,1175ymous_ +B 31600,23000,300,300,CONT_VIA2,563nymous_ +B 4400,32000,300,300,CONT_VIA2,835nymous_ +B 37000,19200,300,300,CONT_BODY_N,781nymous_ +B 36800,6000,300,300,CONT_VIA2,727nymous_ +B 3400,32000,300,300,CONT_VIA2,673nymous_ +B 29600,6000,300,300,CONT_VIA,512nymous_ +B 17600,10000,300,300,CONT_POLY,1158ymous_ +B 1600,20400,300,300,CONT_BODY_P,1104ymous_ +B 32800,34000,300,300,CONT_VIA2,619nymous_ +B 31600,28000,300,300,CONT_VIA2,565nymous_ +B 26000,35000,300,300,CONT_DIF_P,404nymous_ +B 28000,27600,300,300,CONT_DIF_P,458nymous_ +B 14000,29000,300,300,CONT_DIF_N,1050ymous_ +B 10800,33000,300,300,CONT_DIF_N,996nymous_ +B 18800,6000,300,300,CONT_VIA2,1210ymous_ +B 8000,16000,300,300,CONT_BODY_N,942nymous_ +B 6600,31000,300,300,CONT_VIA2,888nymous_ +B 4400,32000,300,300,CONT_VIA,834nymous_ +B 37000,36000,300,300,CONT_VIA,780nymous_ +B 36800,6000,300,300,CONT_VIA,726nymous_ +B 17600,9000,300,300,CONT_VIA,1157ymous_ +B 3400,31000,300,300,CONT_VIA2,672nymous_ +B 32800,33000,300,300,CONT_VIA2,618nymous_ +B 29600,6000,300,300,CONT_BODY_P,511nymous_ +B 15800,37600,300,300,CONT_BODY_P,1103ymous_ +B 31600,27000,300,300,CONT_VIA2,564nymous_ +B 26000,33600,300,300,CONT_VIA,403nymous_ +B 28000,26400,300,300,CONT_DIF_P,457nymous_ +B 24800,6000,300,300,CONT_VIA2,354nymous_ +B 24800,8000,300,300,CONT_DIF_N,355nymous_ +B 30600,31000,300,300,CONT_VIA,541nymous_ +B 17600,11800,300,300,CONT_DIF_P,1160ymous_ +B 33000,19200,300,300,CONT_BODY_N,621nymous_ +B 28000,30000,300,300,CONT_DIF_P,460nymous_ +B 29600,8600,300,300,CONT_DIF_N,514nymous_ +B 1600,22400,300,300,CONT_BODY_P,1106ymous_ +B 28000,28800,300,300,CONT_DIF_P,459nymous_ +B 29600,6000,300,300,CONT_VIA2,513nymous_ +B 14000,30000,300,300,CONT_DIF_N,1051ymous_ +B 10800,34000,300,300,CONT_DIF_N,997nymous_ +B 26000,36400,300,300,CONT_DIF_P,405nymous_ +B 18800,8000,300,300,CONT_DIF_N,1211ymous_ +B 8000,17000,300,300,CONT_VIA,943nymous_ +B 6600,32000,300,300,CONT_VIA2,889nymous_ +B 31600,29000,300,300,CONT_VIA2,566nymous_ +B 32800,35000,300,300,CONT_VIA2,620nymous_ +B 1600,21400,300,300,CONT_BODY_P,1105ymous_ +B 17600,11000,300,300,CONT_VIA,1159ymous_ +B 3400,36000,300,300,CONT_VIA2,674nymous_ +B 36800,7000,300,300,CONT_BODY_P,728nymous_ +B 37200,37600,300,300,CONT_BODY_N,782nymous_ +B 4400,33000,300,300,CONT_DIF_N,836nymous_ +B 6600,36000,300,300,CONT_VIA2,890nymous_ +B 8000,17000,300,300,CONT_VIA2,944nymous_ +B 10800,35000,300,300,CONT_DIF_N,998nymous_ +B 18800,9000,300,300,CONT_DIF_N,1212ymous_ +B 26000,37600,300,300,CONT_BODY_N,406nymous_ +B 31600,33000,300,300,CONT_VIA2,567nymous_ +B 14000,31000,300,300,CONT_DIF_N,1052ymous_ +B 8600,25000,300,300,CONT_VIA2,946nymous_ +B 6800,37600,300,300,CONT_BODY_P,892nymous_ +B 4400,34000,300,300,CONT_DIF_N,838nymous_ +B 38000,28000,300,300,CONT_VIA2,784nymous_ +B 36800,9000,300,300,CONT_BODY_P,730nymous_ +B 17600,12800,300,300,CONT_DIF_P,1161ymous_ +B 34400,6000,300,300,CONT_VIA,676nymous_ +B 33200,6000,300,300,CONT_BODY_P,622nymous_ +B 29600,12800,300,300,CONT_DIF_P,515nymous_ +B 1600,23400,300,300,CONT_BODY_P,1107ymous_ +B 14000,32000,300,300,CONT_DIF_N,1053ymous_ +B 31600,34000,300,300,CONT_VIA2,568nymous_ +B 26000,6000,300,300,CONT_BODY_P,407nymous_ +B 28000,31200,300,300,CONT_DIF_P,461nymous_ +B 18800,11800,300,300,CONT_DIF_P,1213ymous_ +B 10800,36000,300,300,CONT_DIF_N,999nymous_ +B 8600,24000,300,300,CONT_VIA2,945nymous_ +B 6600,19200,300,300,CONT_BODY_P,891nymous_ +B 4400,33000,300,300,CONT_VIA,837nymous_ +B 38000,27000,300,300,CONT_VIA2,783nymous_ +B 36800,8000,300,300,CONT_BODY_P,729nymous_ +B 34400,6000,300,300,CONT_BODY_P,675nymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/pck_mpx.vbe b/pdks/symbolic/mpxlib/cells/pck_mpx.vbe new file mode 100644 index 000000000..59f6ddd94 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pck_mpx.vbe @@ -0,0 +1,29 @@ +ENTITY pck_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_pad : NATURAL := 1326; + CONSTANT tpll_pad : NATURAL := 1443; + CONSTANT rdown_pad : NATURAL := 58; + CONSTANT tphh_pad : NATURAL := 228; + CONSTANT rup_pad : NATURAL := 68 + ); + PORT ( + pad : in BIT; + ck : out BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pck_mpx; + + +ARCHITECTURE behaviour_data_flow OF pck_mpx IS + +BEGIN + ck <= pad; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pck_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/pi_mpx.ap b/pdks/symbolic/mpxlib/cells/pi_mpx.ap new file mode 100644 index 000000000..b21e20da9 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pi_mpx.ap @@ -0,0 +1,1551 @@ +V ALLIANCE : 6 +H pi_mpx,P,17/9/2014,100 +A 0,0,40000,80000 +I 0,40000,padreal_mpx,padreal,NOSYM +S 29000,35100,29000,39700,400,pad,UP,ALU1 +S 29000,25900,29000,34900,400,pad,UP,ALU1 +S 28600,33000,29000,33000,600,pad,RIGHT,POLY +S 28600,31800,29000,31800,600,pad,RIGHT,POLY +S 28600,30600,29000,30600,600,pad,RIGHT,POLY +S 28600,25800,29000,25800,600,pad,RIGHT,POLY +S 20000,48100,20000,71900,24400,pad,UP,CALU1 +S 8000,0,8000,0,400,t,RIGHT,CALU5 +S 8000,0,8000,0,400,t,RIGHT,CALU4 +S 7850,0,8150,0,600,t,RIGHT,CALU3 +S 7850,0,8150,0,600,t,RIGHT,CALU2 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +S 16800,33400,17200,33400,200,vdde,RIGHT,POLY +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 3600,22200,5200,22200,200,vdde,RIGHT,POLY +S 25100,28800,27900,28800,400,vdde,RIGHT,ALU1 +S 25100,26400,27900,26400,400,vdde,RIGHT,ALU1 +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 6800,22200,8400,22200,200,vdde,RIGHT,POLY +S 25100,21600,27900,21600,400,vdde,RIGHT,ALU1 +S 24000,35800,24400,35800,600,vdde,RIGHT,POLY +S 24000,34200,24400,34200,600,vdde,RIGHT,POLY +S 16800,32200,17200,32200,200,vdde,RIGHT,POLY +S 16800,35800,17200,35800,200,vdde,RIGHT,POLY +S 16800,34600,17200,34600,200,vdde,RIGHT,POLY +S 16800,30050,16800,38150,600,vdde,UP,ALU2 +S 10650,21800,14150,21800,600,vdde,RIGHT,ALU2 +S 25100,24000,27900,24000,400,vdde,RIGHT,ALU1 +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 3100,16000,36900,16000,2400,vddi,RIGHT,ALU1 +S 20000,9600,20000,11000,200,vddi,UP,POLY +S 17800,23050,17800,31750,600,vsse,UP,ALU2 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 7600,22900,7600,37500,400,vsse,UP,ALU1 +S 4400,22900,4400,37500,400,vsse,UP,ALU1 +S 30250,36600,30550,36600,600,vsse,RIGHT,ALU2 +S 30400,36400,30400,36600,200,vsse,UP,POLY +S 20800,22900,20800,37100,400,vsse,UP,ALU1 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 3100,6000,36900,6000,2400,vssi,RIGHT,ALU1 +S 28800,9000,29000,9000,200,i,RIGHT,POLY +S 27800,11800,28200,11800,200,i,RIGHT,POLY +S 17500,22600,19100,22600,200,n6d,RIGHT,NTRANS +S 28300,9000,28700,9000,400,91onymous_,RIGHT,ALU1 +S 24900,31200,28100,31200,420,53onymous_,RIGHT,PDIF +S 28300,10600,29500,10600,400,92onymous_,RIGHT,ALU1 +S 20000,11100,20000,15900,400,12onymous_,UP,ALU1 +S 28400,7500,28400,8100,620,93onymous_,UP,NDIF +S 20000,12850,20000,17150,600,13onymous_,UP,ALU2 +S 6200,10900,6200,14900,200,p18b,UP,PTRANS +S 14600,11100,14600,13100,200,p17c,UP,PTRANS +S 30800,10600,33800,10600,200,cnbb,RIGHT,POLY +S 30800,8100,30800,12900,400,cnbb,UP,ALU1 +S 6800,22500,6800,36700,200,n14c,UP,NTRANS +S 14800,22500,14800,36700,200,n15d,UP,NTRANS +S 35000,7300,35000,8300,200,n5b,UP,NTRANS +S 35000,12700,35000,14700,200,p5b,UP,PTRANS +S 27800,12500,27800,14500,200,p1,UP,PTRANS +S 17700,29200,18900,29200,620,318nymous_,RIGHT,NDIF +S 17700,30400,18900,30400,620,319nymous_,RIGHT,NDIF +S 17700,31600,18900,31600,620,320nymous_,RIGHT,NDIF +S 15600,22700,15600,36500,620,285nymous_,UP,NDIF +S 24900,30000,28100,30000,420,52onymous_,RIGHT,PDIF +S 20000,8100,20000,8500,400,11onymous_,UP,ALU1 +S 10800,21800,10800,22200,600,249nymous_,UP,POLY +S 10700,39600,35500,39600,2400,248nymous_,RIGHT,ALU1 +S 7600,21800,7600,22200,600,211nymous_,UP,POLY +S 31800,12000,31800,12200,200,127nymous_,UP,POLY +S 20000,40100,20000,59900,4400,10onymous_,UP,ALU1 +S 24900,28800,28100,28800,420,51onymous_,RIGHT,PDIF +S 31600,20200,31600,20600,600,126nymous_,UP,POLY +S 15450,18200,21150,18200,600,286nymous_,RIGHT,ALU2 +S 17700,32800,18900,32800,620,321nymous_,RIGHT,NDIF +S 7400,9600,7400,10600,200,210nymous_,UP,POLY +S 35600,12900,35600,14500,620,169nymous_,UP,PDIF +S 7450,21800,9950,21800,600,212nymous_,RIGHT,ALU2 +S 31850,6000,36950,6000,600,128nymous_,RIGHT,ALU2 +S 36000,20200,36000,20600,600,172nymous_,UP,POLY +S 15800,23850,15800,32150,600,288nymous_,UP,ALU2 +S 17700,35200,18900,35200,620,323nymous_,RIGHT,NDIF +S 35450,17000,36950,17000,600,171nymous_,RIGHT,ALU2 +S 15600,18050,15600,20350,600,287nymous_,UP,ALU2 +S 17700,34000,18900,34000,620,322nymous_,RIGHT,NDIF +S 35600,13100,35600,15900,400,170nymous_,UP,ALU1 +S 31400,35300,31400,36100,200,p11,UP,PTRANS +S 31400,20900,31400,34300,200,p14a,UP,PTRANS +S 24900,35000,28100,35000,820,56onymous_,RIGHT,PDIF +S 7600,22850,7600,38150,2400,215nymous_,UP,ALU2 +S 1700,37600,9500,37600,400,290nymous_,RIGHT,ALU1 +S 24900,33600,28100,33600,420,55onymous_,RIGHT,PDIF +S 7600,22900,7600,37500,400,214nymous_,UP,ALU1 +S 31850,7600,36950,7600,600,130nymous_,RIGHT,ALU2 +S 17700,36400,18900,36400,620,324nymous_,RIGHT,NDIF +S 32000,7500,32000,8100,620,129nymous_,UP,NDIF +S 15800,9600,15800,10800,200,289nymous_,UP,POLY +S 7600,22700,7600,36500,620,213nymous_,UP,NDIF +S 17700,8000,22300,8000,400,325nymous_,RIGHT,ALU1 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10400,7500,10400,9100,420,243nymous_,UP,NDIF +S 15300,37600,20700,37600,400,279nymous_,RIGHT,ALU1 +S 30800,13100,30800,13900,400,121nymous_,UP,ALU1 +S 6800,7500,6800,9100,620,205nymous_,UP,NDIF +S 15200,7500,15200,9100,620,280nymous_,UP,NDIF +S 50,6000,6800,6000,12000,3nonymous_,RIGHT,TALU4 +S 35400,21100,35400,36500,620,164nymous_,UP,PDIF +S 6900,10000,12700,10000,400,206nymous_,RIGHT,ALU1 +S 15200,8100,15200,8900,400,281nymous_,UP,ALU1 +S 27800,11800,27800,12400,200,85onymous_,UP,POLY +S 0,6000,40000,6000,12000,4nonymous_,RIGHT,TALU6 +S 35400,21300,35400,39700,400,165nymous_,UP,ALU1 +S 6800,11100,6800,14700,620,207nymous_,UP,PDIF +S 24600,200,24600,2000,31000,5nonymous_,UP,TALU3 +S 10250,7600,27150,7600,600,244nymous_,RIGHT,ALU2 +S 2800,20500,2800,36300,400,86onymous_,UP,ALU1 +S 10400,8100,10400,8900,400,245nymous_,UP,ALU1 +S 2800,22700,2800,36500,620,87onymous_,UP,NDIF +S 2200,13600,37800,13600,6800,88onymous_,RIGHT,NWELL +S 28200,9100,28200,11700,400,90onymous_,UP,ALU1 +S 17500,35800,19100,35800,200,n8a,RIGHT,NTRANS +S 6200,7300,6200,9300,200,n18b,UP,NTRANS +S 14600,7300,14600,9300,200,n17c,UP,NTRANS +S 34600,20900,34600,36700,200,p14c,UP,PTRANS +S 24700,31800,28300,31800,200,p8b,RIGHT,PTRANS +S 24700,33000,28300,33000,200,p8a,RIGHT,PTRANS +S 27800,7300,27800,8300,200,n2,UP,NTRANS +S 24700,34200,28300,34200,200,p9,RIGHT,PTRANS +S 24700,35800,28300,35800,200,p12,RIGHT,PTRANS +S 31000,5850,31000,11150,600,122nymous_,UP,ALU2 +S 17700,26800,18900,26800,620,316nymous_,RIGHT,NDIF +S 30850,6000,32150,6000,600,123nymous_,RIGHT,ALU2 +S 15200,11100,15200,12500,400,282nymous_,UP,ALU1 +S 17700,28000,18900,28000,620,317nymous_,RIGHT,NDIF +S 30850,10000,35950,10000,2400,124nymous_,RIGHT,ALU2 +S 35250,13000,36950,13000,2400,166nymous_,RIGHT,ALU2 +S 15200,11300,15200,12900,620,283nymous_,UP,PDIF +S 6800,12100,6800,15900,400,208nymous_,UP,ALU1 +S 3400,200,3400,2000,7000,6nonymous_,UP,TALU3 +S 35600,6100,35600,7900,400,167nymous_,UP,ALU1 +S 15600,20700,15600,36300,400,284nymous_,UP,ALU1 +S 7000,7050,7000,14150,600,209nymous_,UP,ALU2 +S 24600,200,24600,12000,31000,7nonymous_,UP,TALU5 +S 35600,7500,35600,8100,620,168nymous_,UP,NDIF +S 3400,200,3400,12000,7000,8nonymous_,UP,TALU5 +S 31400,19250,31400,28150,600,125nymous_,UP,ALU2 +S 10400,11100,10400,13700,400,246nymous_,UP,ALU1 +S 20000,40100,20000,59900,4400,9nonymous_,UP,ALU1 +S 10400,11100,10400,14700,620,247nymous_,UP,PDIF +S 28200,6450,28200,10750,600,89onymous_,UP,ALU2 +B 22400,8000,200,200,CONT_TURN1,349nymous_ +B 21200,10000,200,200,CONT_TURN1,348nymous_ +B 28200,9000,200,200,CONT_TURN1,351nymous_ +B 22400,13000,200,200,CONT_TURN1,350nymous_ +B 5000,19000,8300,2300,CONT_VIA2,352nymous_ +B 10400,11000,200,200,CONT_TURN1,353nymous_ +B 16400,9000,300,300,CONT_DIF_N,1268ymous_ +B 15200,6000,300,300,CONT_BODY_P,1214ymous_ +B 6800,37600,300,300,CONT_BODY_P,1000ymous_ +B 7600,36000,300,300,CONT_VIA,1054ymous_ +B 17800,36400,300,300,CONT_DIF_N,1322ymous_ +B 23000,28400,300,300,CONT_BODY_N,408nymous_ +B 28200,6600,300,300,CONT_VIA,569nymous_ +B 9200,12800,300,300,CONT_DIF_P,1108ymous_ +B 12400,26000,300,300,CONT_DIF_N,1162ymous_ +B 27000,27600,300,300,CONT_DIF_P,516nymous_ +B 25000,32400,300,300,CONT_DIF_P,462nymous_ +B 30600,31000,300,300,CONT_DIF_P,623nymous_ +B 3200,14000,300,300,CONT_BODY_N,677nymous_ +B 35400,25000,300,300,CONT_DIF_P,785nymous_ +B 37000,22000,300,300,CONT_VIA,839nymous_ +B 38200,29400,300,300,CONT_BODY_N,893nymous_ +B 4400,13800,300,300,CONT_DIF_P,947nymous_ +B 16400,10000,300,300,CONT_POLY,1269ymous_ +B 15200,6000,300,300,CONT_VIA,1215ymous_ +B 6800,37600,300,300,CONT_VIA,1001ymous_ +B 7600,36000,300,300,CONT_VIA2,1055ymous_ +B 17800,37600,300,300,CONT_BODY_P,1323ymous_ +B 23000,29400,300,300,CONT_BODY_N,409nymous_ +B 28200,10600,300,300,CONT_VIA,570nymous_ +B 9200,13800,300,300,CONT_DIF_P,1109ymous_ +B 12400,27000,300,300,CONT_DIF_N,1163ymous_ +B 27000,28800,300,300,CONT_DIF_P,517nymous_ +B 25000,32400,300,300,CONT_VIA,463nymous_ +B 30600,31000,300,300,CONT_VIA,624nymous_ +B 3200,14000,300,300,CONT_VIA2,678nymous_ +B 35400,26000,300,300,CONT_DIF_P,786nymous_ +B 33800,28000,300,300,CONT_DIF_P,732nymous_ +B 37000,22000,300,300,CONT_VIA2,840nymous_ +B 28000,20400,300,300,CONT_DIF_P,540nymous_ +B 38200,30400,300,300,CONT_BODY_N,894nymous_ +B 4400,14800,300,300,CONT_DIF_P,948nymous_ +B 6800,37600,300,300,CONT_VIA2,1002ymous_ +B 16400,12000,300,300,CONT_DIF_P,1270ymous_ +B 15200,6000,300,300,CONT_VIA2,1216ymous_ +B 17800,22000,200,200,CONT_TURN1,356nymous_ +B 7600,19200,300,300,CONT_BODY_P,1056ymous_ +B 9200,14800,300,300,CONT_DIF_P,1110ymous_ +B 18600,19200,300,300,CONT_BODY_P,1324ymous_ +B 25000,33600,300,300,CONT_DIF_P,464nymous_ +B 23000,30400,300,300,CONT_BODY_N,410nymous_ +B 28200,11800,300,300,CONT_POLY,571nymous_ +B 30600,32000,300,300,CONT_DIF_P,625nymous_ +B 12400,28000,300,300,CONT_DIF_N,1164ymous_ +B 27000,30000,300,300,CONT_DIF_P,518nymous_ +B 3200,15000,300,300,CONT_BODY_N,679nymous_ +B 33800,28000,300,300,CONT_VIA,733nymous_ +B 35400,27000,300,300,CONT_DIF_P,787nymous_ +B 37000,23000,300,300,CONT_DIF_P,841nymous_ +B 38200,31400,300,300,CONT_BODY_N,895nymous_ +B 15200,8000,300,300,CONT_DIF_N,1217ymous_ +B 4400,16000,300,300,CONT_BODY_N,949nymous_ +B 6800,6000,300,300,CONT_BODY_P,1003ymous_ +B 18800,22000,300,300,CONT_DIF_N,1325ymous_ +B 16400,12800,300,300,CONT_DIF_P,1271ymous_ +B 18400,12800,200,200,CONT_TURN1,357nymous_ +B 7800,37600,300,300,CONT_BODY_P,1057ymous_ +B 9200,16000,300,300,CONT_BODY_N,1111ymous_ +B 23000,31400,300,300,CONT_BODY_N,411nymous_ +B 28400,6000,300,300,CONT_BODY_P,572nymous_ +B 12400,29000,300,300,CONT_DIF_N,1165ymous_ +B 25000,35000,300,300,CONT_DIF_P,465nymous_ +B 30600,32000,300,300,CONT_VIA,626nymous_ +B 27000,31200,300,300,CONT_DIF_P,519nymous_ +B 3200,16000,300,300,CONT_BODY_N,680nymous_ +B 33800,28000,300,300,CONT_VIA2,734nymous_ +B 35400,28000,300,300,CONT_DIF_P,788nymous_ +B 37000,23000,300,300,CONT_VIA,842nymous_ +B 38200,32400,300,300,CONT_BODY_N,896nymous_ +B 4400,17000,300,300,CONT_VIA,950nymous_ +B 15200,9000,300,300,CONT_DIF_N,1218ymous_ +B 6800,6000,300,300,CONT_VIA,1004ymous_ +B 7800,37600,300,300,CONT_VIA,1058ymous_ +B 18800,22200,300,300,CONT_VIA,1326ymous_ +B 16400,16000,300,300,CONT_BODY_N,1272ymous_ +B 23000,32400,300,300,CONT_BODY_N,412nymous_ +B 19800,32800,200,200,CONT_TURN1,358nymous_ +B 28400,8000,300,300,CONT_DIF_N,573nymous_ +B 9200,17000,300,300,CONT_VIA,1112ymous_ +B 12400,30000,300,300,CONT_DIF_N,1166ymous_ +B 27000,32400,300,300,CONT_DIF_P,520nymous_ +B 25000,36400,300,300,CONT_DIF_P,466nymous_ +B 30600,33000,300,300,CONT_DIF_P,627nymous_ +B 3200,17000,300,300,CONT_VIA,681nymous_ +B 33800,29000,300,300,CONT_DIF_P,735nymous_ +B 35400,29000,300,300,CONT_DIF_P,789nymous_ +B 37000,23000,300,300,CONT_VIA2,843nymous_ +B 38200,33400,300,300,CONT_BODY_N,897nymous_ +B 4400,17000,300,300,CONT_VIA2,951nymous_ +B 16400,17000,300,300,CONT_VIA,1273ymous_ +B 15200,10000,300,300,CONT_POLY,1219ymous_ +B 6800,6000,300,300,CONT_VIA2,1005ymous_ +B 20000,6000,300,300,CONT_BODY_P,359nymous_ +B 7800,37600,300,300,CONT_VIA2,1059ymous_ +B 18800,23200,300,300,CONT_DIF_N,1327ymous_ +B 23000,33400,300,300,CONT_BODY_N,413nymous_ +B 28400,14000,300,300,CONT_DIF_P,574nymous_ +B 9200,17000,300,300,CONT_VIA2,1113ymous_ +B 12400,31000,300,300,CONT_DIF_N,1167ymous_ +B 27000,33600,300,300,CONT_DIF_P,521nymous_ +B 25000,37600,300,300,CONT_BODY_N,467nymous_ +B 30600,33000,300,300,CONT_VIA,628nymous_ +B 3200,17000,300,300,CONT_VIA2,682nymous_ +B 35400,30000,300,300,CONT_DIF_P,790nymous_ +B 33800,29000,300,300,CONT_VIA,736nymous_ +B 37000,24000,300,300,CONT_DIF_P,844nymous_ +B 38200,34400,300,300,CONT_BODY_N,898nymous_ +B 4600,37600,300,300,CONT_BODY_P,952nymous_ +B 6800,7200,300,300,CONT_DIF_N,1006ymous_ +B 16400,17000,300,300,CONT_VIA2,1274ymous_ +B 15200,11600,300,300,CONT_DIF_P,1220ymous_ +B 20000,6000,300,300,CONT_VIA,360nymous_ +B 8000,0,300,300,CONT_VIA2,1060ymous_ +B 9600,37600,300,300,CONT_BODY_P,1114ymous_ +B 18800,24400,300,300,CONT_DIF_N,1328ymous_ +B 25000,19200,300,300,CONT_BODY_N,468nymous_ +B 23000,34400,300,300,CONT_BODY_N,414nymous_ +B 28400,16000,300,300,CONT_BODY_N,575nymous_ +B 30600,33000,300,300,CONT_VIA2,629nymous_ +B 12400,32000,300,300,CONT_DIF_N,1168ymous_ +B 27000,35000,300,300,CONT_DIF_P,522nymous_ +B 32200,22000,300,300,CONT_DIF_P,683nymous_ +B 33800,29000,300,300,CONT_VIA2,737nymous_ +B 35400,31000,300,300,CONT_DIF_P,791nymous_ +B 37000,24000,300,300,CONT_VIA,845nymous_ +B 15200,12600,300,300,CONT_DIF_P,1221ymous_ +B 4600,37600,300,300,CONT_VIA,953nymous_ +B 6800,8000,300,300,CONT_DIF_N,1007ymous_ +B 18800,25600,300,300,CONT_DIF_N,1329ymous_ +B 16600,19200,300,300,CONT_BODY_P,1275ymous_ +B 20000,6000,300,300,CONT_VIA2,361nymous_ +B 8000,0,300,300,CONT_VIA3,1061ymous_ +B 9600,19200,300,300,CONT_BODY_P,1115ymous_ +B 26000,20400,300,300,CONT_DIF_P,469nymous_ +B 23000,35400,300,300,CONT_BODY_N,415nymous_ +B 28400,17000,300,300,CONT_VIA,576nymous_ +B 30600,34000,300,300,CONT_DIF_P,630nymous_ +B 33800,30000,300,300,CONT_DIF_P,738nymous_ +B 12400,33000,300,300,CONT_DIF_N,1169ymous_ +B 27000,36400,300,300,CONT_DIF_P,523nymous_ +B 32200,23000,300,300,CONT_DIF_P,684nymous_ +B 35400,32000,300,300,CONT_DIF_P,792nymous_ +B 37000,25000,300,300,CONT_DIF_P,846nymous_ +B 38200,36400,300,300,CONT_BODY_N,900nymous_ +B 4600,37600,300,300,CONT_VIA2,954nymous_ +B 15200,16000,300,300,CONT_BODY_N,1222ymous_ +B 6800,10000,300,300,CONT_POLY,1008ymous_ +B 8000,0,300,300,CONT_VIA4,1062ymous_ +B 18800,26800,300,300,CONT_DIF_N,1330ymous_ +B 16800,20200,300,300,CONT_VIA,1276ymous_ +B 23000,36400,300,300,CONT_BODY_N,416nymous_ +B 20000,8600,300,300,CONT_DIF_N,362nymous_ +B 28400,17000,300,300,CONT_VIA2,577nymous_ +B 10400,6000,300,300,CONT_BODY_P,1116ymous_ +B 12400,34000,300,300,CONT_DIF_N,1170ymous_ +B 27000,36400,300,300,CONT_VIA,524nymous_ +B 38200,35400,300,300,CONT_BODY_N,899nymous_ +B 4600,19200,300,300,CONT_BODY_P,955nymous_ +B 16800,23400,300,300,CONT_POLY,1277ymous_ +B 15200,17000,300,300,CONT_VIA,1223ymous_ +B 6800,12000,300,300,CONT_DIF_P,1009ymous_ +B 8000,8000,300,300,CONT_DIF_N,1063ymous_ +B 18800,26800,300,300,CONT_VIA,1331ymous_ +B 23000,37600,300,300,CONT_BODY_N,417nymous_ +B 20000,11000,300,300,CONT_POLY,363nymous_ +B 28800,9000,300,300,CONT_POLY,578nymous_ +B 10400,6000,300,300,CONT_VIA,1117ymous_ +B 12400,35000,300,300,CONT_DIF_N,1171ymous_ +B 27000,37600,300,300,CONT_BODY_N,525nymous_ +B 26000,21600,300,300,CONT_VIA,471nymous_ +B 30600,34000,300,300,CONT_VIA2,632nymous_ +B 32200,25000,300,300,CONT_DIF_P,686nymous_ +B 33800,31000,300,300,CONT_DIF_P,740nymous_ +B 35400,34000,300,300,CONT_DIF_P,794nymous_ +B 37000,26000,300,300,CONT_DIF_P,848nymous_ +B 38200,19200,300,300,CONT_BODY_N,902nymous_ +B 5400,24000,300,300,CONT_VIA2,956nymous_ +B 6800,12800,300,300,CONT_DIF_P,1010ymous_ +B 16800,24400,300,300,CONT_VIA,1278ymous_ +B 15200,17000,300,300,CONT_VIA2,1224ymous_ +B 20000,16000,300,300,CONT_BODY_N,364nymous_ +B 18800,28000,300,300,CONT_DIF_N,1332ymous_ +B 38200,37600,300,300,CONT_BODY_N,901nymous_ +B 37000,25000,300,300,CONT_VIA,847nymous_ +B 35400,33000,300,300,CONT_DIF_P,793nymous_ +B 33800,30000,300,300,CONT_VIA,739nymous_ +B 32200,24000,300,300,CONT_DIF_P,685nymous_ +B 30600,34000,300,300,CONT_VIA,631nymous_ +B 26000,21600,300,300,CONT_DIF_P,470nymous_ +B 4400,21800,300,300,CONT_VIA,904nymous_ +B 37000,27000,300,300,CONT_DIF_P,850nymous_ +B 35400,36000,300,300,CONT_DIF_P,796nymous_ +B 32200,27000,300,300,CONT_DIF_P,688nymous_ +B 27000,10000,300,300,CONT_VIA2,527nymous_ +B 12600,19200,300,300,CONT_BODY_P,1173ymous_ +B 33800,32000,300,300,CONT_DIF_P,742nymous_ +B 30600,35000,300,300,CONT_VIA,634nymous_ +B 29000,21000,300,300,CONT_VIA,580nymous_ +B 23400,17000,300,300,CONT_VIA,419nymous_ +B 26000,22800,300,300,CONT_DIF_P,473nymous_ +B 10400,8000,300,300,CONT_DIF_N,1119ymous_ +B 8000,9000,300,300,CONT_VIA,1065ymous_ +B 20800,20400,300,300,CONT_BODY_P,365nymous_ +B 16800,25400,300,300,CONT_POLY,1279ymous_ +B 18800,29200,300,300,CONT_DIF_N,1333ymous_ +B 6800,13800,300,300,CONT_DIF_P,1011ymous_ +B 5400,25000,300,300,CONT_VIA2,957nymous_ +B 15600,20200,300,300,CONT_VIA,1225ymous_ +B 4400,21800,300,300,CONT_POLY,903nymous_ +B 37000,26000,300,300,CONT_VIA,849nymous_ +B 35400,35000,300,300,CONT_DIF_P,795nymous_ +B 33800,31000,300,300,CONT_VIA,741nymous_ +B 32200,26000,300,300,CONT_DIF_P,687nymous_ +B 27000,9000,300,300,CONT_VIA2,526nymous_ +B 12400,36000,300,300,CONT_DIF_N,1172ymous_ +B 30600,35000,300,300,CONT_DIF_P,633nymous_ +B 29000,21000,300,300,CONT_POLY,579nymous_ +B 23000,19200,300,300,CONT_BODY_N,418nymous_ +B 26000,21600,300,300,CONT_VIA2,472nymous_ +B 10400,6000,300,300,CONT_VIA2,1118ymous_ +B 8000,9000,300,300,CONT_DIF_N,1064ymous_ +B 30800,6000,300,300,CONT_BODY_P,636nymous_ +B 26000,24000,300,300,CONT_DIF_P,475nymous_ +B 27000,19200,300,300,CONT_BODY_N,529nymous_ +B 10400,10000,300,300,CONT_POLY,1121ymous_ +B 29000,22200,300,300,CONT_VIA,582nymous_ +B 20800,22400,300,300,CONT_BODY_P,367nymous_ +B 23600,6000,300,300,CONT_BODY_P,421nymous_ +B 18800,31600,300,300,CONT_DIF_N,1335ymous_ +B 8000,11000,300,300,CONT_VIA,1067ymous_ +B 6800,16000,300,300,CONT_BODY_N,1013ymous_ +B 15600,24000,300,300,CONT_DIF_N,1227ymous_ +B 16800,29200,300,300,CONT_VIA,1281ymous_ +B 5400,30000,300,300,CONT_VIA2,959nymous_ +B 4400,23000,300,300,CONT_DIF_N,905nymous_ +B 37000,27000,300,300,CONT_VIA,851nymous_ +B 35600,6000,300,300,CONT_BODY_P,797nymous_ +B 33800,32000,300,300,CONT_VIA,743nymous_ +B 32200,28000,300,300,CONT_DIF_P,689nymous_ +B 30600,35000,300,300,CONT_VIA2,635nymous_ +B 26000,22800,300,300,CONT_VIA2,474nymous_ +B 27000,11000,300,300,CONT_VIA2,528nymous_ +B 12800,6000,300,300,CONT_BODY_P,1174ymous_ +B 10400,9000,300,300,CONT_DIF_N,1120ymous_ +B 29000,22200,300,300,CONT_POLY,581nymous_ +B 20800,21400,300,300,CONT_BODY_P,366nymous_ +B 23400,17000,300,300,CONT_VIA2,420nymous_ +B 16800,28200,300,300,CONT_POLY,1280ymous_ +B 18800,30400,300,300,CONT_DIF_N,1334ymous_ +B 8000,10000,300,300,CONT_POLY,1066ymous_ +B 6800,14800,300,300,CONT_DIF_P,1012ymous_ +B 15600,23000,300,300,CONT_DIF_N,1226ymous_ +B 5400,26000,300,300,CONT_VIA2,958nymous_ +B 23600,6000,300,300,CONT_VIA2,423nymous_ +B 8000,12800,300,300,CONT_DIF_P,1069ymous_ +B 20800,24400,300,300,CONT_BODY_P,369nymous_ +B 16800,32200,300,300,CONT_VIA,1283ymous_ +B 18800,32800,300,300,CONT_DIF_N,1337ymous_ +B 6800,17000,300,300,CONT_VIA2,1015ymous_ +B 5400,32000,300,300,CONT_VIA2,961nymous_ +B 15600,26000,300,300,CONT_DIF_N,1229ymous_ +B 4400,24000,300,300,CONT_DIF_N,907nymous_ +B 37000,28000,300,300,CONT_DIF_P,853nymous_ +B 35600,6000,300,300,CONT_VIA2,799nymous_ +B 33800,33000,300,300,CONT_VIA,745nymous_ +B 32200,30000,300,300,CONT_DIF_P,691nymous_ +B 27200,6000,300,300,CONT_BODY_P,530nymous_ +B 12800,6000,300,300,CONT_VIA2,1176ymous_ +B 30800,8000,300,300,CONT_DIF_N,637nymous_ +B 29000,23400,300,300,CONT_POLY,583nymous_ +B 23600,6000,300,300,CONT_VIA,422nymous_ +B 26000,24000,300,300,CONT_VIA,476nymous_ +B 18800,31600,300,300,CONT_VIA,1336ymous_ +B 10400,11800,300,300,CONT_DIF_P,1122ymous_ +B 8000,11800,300,300,CONT_DIF_P,1068ymous_ +B 20800,23400,300,300,CONT_BODY_P,368nymous_ +B 15600,25000,300,300,CONT_DIF_N,1228ymous_ +B 16800,32200,300,300,CONT_POLY,1282ymous_ +B 6800,17000,300,300,CONT_VIA,1014ymous_ +B 5400,31000,300,300,CONT_VIA2,960nymous_ +B 4400,23000,300,300,CONT_VIA,906nymous_ +B 37000,27000,300,300,CONT_VIA2,852nymous_ +B 35600,6000,300,300,CONT_VIA,798nymous_ +B 33800,33000,300,300,CONT_DIF_P,744nymous_ +B 32200,29000,300,300,CONT_DIF_P,690nymous_ +B 5600,37600,300,300,CONT_BODY_P,963nymous_ +B 4400,24000,300,300,CONT_VIA2,909nymous_ +B 37000,28000,300,300,CONT_VIA2,855nymous_ +B 35600,13000,300,300,CONT_DIF_P,801nymous_ +B 33800,34000,300,300,CONT_DIF_P,747nymous_ +B 32200,32000,300,300,CONT_DIF_P,693nymous_ +B 30800,13000,300,300,CONT_DIF_P,639nymous_ +B 26000,26400,300,300,CONT_DIF_P,478nymous_ +B 27200,10600,300,300,CONT_POLY,532nymous_ +B 12800,9000,300,300,CONT_DIF_N,1178ymous_ +B 10400,13800,300,300,CONT_DIF_P,1124ymous_ +B 29000,24600,300,300,CONT_POLY,585nymous_ +B 20800,25400,300,300,CONT_BODY_P,370nymous_ +B 23600,8000,300,300,CONT_DIF_N,424nymous_ +B 16800,33400,300,300,CONT_POLY,1284ymous_ +B 18800,34000,300,300,CONT_DIF_N,1338ymous_ +B 8000,13800,300,300,CONT_DIF_P,1070ymous_ +B 7000,9000,300,300,CONT_VIA2,1016ymous_ +B 15600,27000,300,300,CONT_DIF_N,1230ymous_ +B 5400,36000,300,300,CONT_VIA2,962nymous_ +B 4400,24000,300,300,CONT_VIA,908nymous_ +B 37000,28000,300,300,CONT_VIA,854nymous_ +B 35600,8000,300,300,CONT_DIF_N,800nymous_ +B 32200,31000,300,300,CONT_DIF_P,692nymous_ +B 27200,8000,300,300,CONT_DIF_N,531nymous_ +B 12800,8000,300,300,CONT_DIF_N,1177ymous_ +B 33800,33000,300,300,CONT_VIA2,746nymous_ +B 30800,10600,300,300,CONT_POLY,638nymous_ +B 29000,23400,300,300,CONT_VIA,584nymous_ +B 26000,25200,300,300,CONT_DIF_P,477nymous_ +B 10400,12800,300,300,CONT_DIF_P,1123ymous_ +B 7000,10000,300,300,CONT_VIA2,1017ymous_ +B 16800,33400,300,300,CONT_VIA,1285ymous_ +B 15600,28000,300,300,CONT_DIF_N,1231ymous_ +B 8000,16000,300,300,CONT_BODY_N,1071ymous_ +B 18800,34000,300,300,CONT_VIA,1339ymous_ +B 23600,13000,300,300,CONT_DIF_P,425nymous_ +B 20800,26400,300,300,CONT_BODY_P,371nymous_ +B 29000,24600,300,300,CONT_VIA,586nymous_ +B 10400,16000,300,300,CONT_BODY_N,1125ymous_ +B 12800,11600,300,300,CONT_DIF_P,1179ymous_ +B 27200,13000,300,300,CONT_DIF_P,533nymous_ +B 26000,26400,300,300,CONT_VIA,479nymous_ +B 30800,14000,300,300,CONT_DIF_P,640nymous_ +B 32200,33000,300,300,CONT_DIF_P,694nymous_ +B 33800,34000,300,300,CONT_VIA,748nymous_ +B 35600,14000,300,300,CONT_DIF_P,802nymous_ +B 37000,29000,300,300,CONT_DIF_P,856nymous_ +B 4400,25000,300,300,CONT_DIF_N,910nymous_ +B 5600,37600,300,300,CONT_VIA,964nymous_ +B 7000,11000,300,300,CONT_VIA2,1018ymous_ +B 16800,33400,300,300,CONT_VIA2,1286ymous_ +B 15600,29000,300,300,CONT_DIF_N,1232ymous_ +B 20800,27400,300,300,CONT_BODY_P,372nymous_ +B 8000,17000,300,300,CONT_VIA,1072ymous_ +B 10400,17000,300,300,CONT_VIA,1126ymous_ +B 18800,35200,300,300,CONT_DIF_N,1340ymous_ +B 26000,27600,300,300,CONT_DIF_P,480nymous_ +B 23600,14000,300,300,CONT_DIF_P,426nymous_ +B 29000,25800,300,300,CONT_POLY,587nymous_ +B 30800,16000,300,300,CONT_BODY_N,641nymous_ +B 27200,14000,300,300,CONT_DIF_P,534nymous_ +B 32200,34000,300,300,CONT_DIF_P,695nymous_ +B 33800,34000,300,300,CONT_VIA2,749nymous_ +B 35600,16000,300,300,CONT_BODY_N,803nymous_ +B 37000,29000,300,300,CONT_VIA,857nymous_ +B 4400,25000,300,300,CONT_VIA,911nymous_ +B 15600,30000,300,300,CONT_DIF_N,1233ymous_ +B 5600,37600,300,300,CONT_VIA2,965nymous_ +B 7600,21800,300,300,CONT_POLY,1019ymous_ +B 18800,36400,300,300,CONT_DIF_N,1341ymous_ +B 16800,34600,300,300,CONT_POLY,1287ymous_ +B 20800,28400,300,300,CONT_BODY_P,373nymous_ +B 8000,17000,300,300,CONT_VIA2,1073ymous_ +B 10400,17000,300,300,CONT_VIA2,1127ymous_ +B 26000,27600,300,300,CONT_VIA2,481nymous_ +B 23600,16000,300,300,CONT_BODY_N,427nymous_ +B 29000,30600,300,300,CONT_POLY,588nymous_ +B 30800,17000,300,300,CONT_VIA,642nymous_ +B 33800,35000,300,300,CONT_DIF_P,750nymous_ +B 27200,16000,300,300,CONT_BODY_N,535nymous_ +B 32200,35000,300,300,CONT_DIF_P,696nymous_ +B 35600,17000,300,300,CONT_VIA,804nymous_ +B 37000,29000,300,300,CONT_VIA2,858nymous_ +B 4400,25000,300,300,CONT_VIA2,912nymous_ +B 5600,6000,300,300,CONT_BODY_P,966nymous_ +B 15600,31000,300,300,CONT_DIF_N,1234ymous_ +B 7600,21800,300,300,CONT_VIA,1020ymous_ +B 8600,24000,300,300,CONT_VIA2,1074ymous_ +B 18800,36400,300,300,CONT_VIA,1342ymous_ +B 16800,34600,300,300,CONT_VIA,1288ymous_ +B 24000,27000,300,300,CONT_POLY,428nymous_ +B 20800,29400,300,300,CONT_BODY_P,374nymous_ +B 29000,31800,300,300,CONT_POLY,589nymous_ +B 10600,19200,300,300,CONT_BODY_P,1128ymous_ +B 27200,17000,300,300,CONT_VIA,536nymous_ +B 26000,28800,300,300,CONT_DIF_P,482nymous_ +B 30800,17000,300,300,CONT_VIA2,643nymous_ +B 32200,36000,300,300,CONT_DIF_P,697nymous_ +B 33800,35000,300,300,CONT_VIA,751nymous_ +B 35600,17000,300,300,CONT_VIA2,805nymous_ +B 37000,30000,300,300,CONT_DIF_P,859nymous_ +B 4400,26000,300,300,CONT_DIF_N,913nymous_ +B 5600,6000,300,300,CONT_VIA,967nymous_ +B 16800,34600,300,300,CONT_VIA2,1289ymous_ +B 15600,32000,300,300,CONT_DIF_N,1235ymous_ +B 7600,23000,300,300,CONT_DIF_N,1021ymous_ +B 8600,25000,300,300,CONT_VIA2,1075ymous_ +B 18800,37600,300,300,CONT_BODY_P,1343ymous_ +B 24000,28200,300,300,CONT_POLY,429nymous_ +B 20800,30400,300,300,CONT_BODY_P,375nymous_ +B 29000,33000,300,300,CONT_POLY,590nymous_ +B 10800,21800,300,300,CONT_POLY,1129ymous_ +B 27200,17000,300,300,CONT_VIA2,537nymous_ +B 26000,28800,300,300,CONT_VIA,483nymous_ +B 31000,19200,300,300,CONT_BODY_N,644nymous_ +B 32800,20200,300,300,CONT_POLY,698nymous_ +B 33800,35000,300,300,CONT_VIA2,752nymous_ +B 36000,20200,300,300,CONT_POLY,806nymous_ +B 37000,30000,300,300,CONT_VIA,860nymous_ +B 4400,26000,300,300,CONT_VIA,914nymous_ +B 5600,6000,300,300,CONT_VIA2,968nymous_ +B 7600,23000,300,300,CONT_VIA,1022ymous_ +B 16800,35800,300,300,CONT_POLY,1290ymous_ +B 15600,33000,300,300,CONT_DIF_N,1236ymous_ +B 20800,31400,300,300,CONT_BODY_P,376nymous_ +B 18800,6000,300,300,CONT_BODY_P,1344ymous_ +B 12800,17000,300,300,CONT_VIA,1182ymous_ +B 8600,26000,300,300,CONT_VIA2,1076ymous_ +B 10800,21800,300,300,CONT_VIA,1130ymous_ +B 26000,28800,300,300,CONT_VIA2,484nymous_ +B 24000,28200,300,300,CONT_VIA,430nymous_ +B 29000,19200,300,300,CONT_BODY_N,591nymous_ +B 31600,20200,300,300,CONT_POLY,645nymous_ +B 27800,36400,300,300,CONT_DIF_P,538nymous_ +B 32800,22000,300,300,CONT_VIA2,699nymous_ +B 33800,36000,300,300,CONT_DIF_P,753nymous_ +B 36000,22000,300,300,CONT_VIA2,807nymous_ +B 37000,31000,300,300,CONT_DIF_P,861nymous_ +B 4400,26000,300,300,CONT_VIA2,915nymous_ +B 15600,34000,300,300,CONT_DIF_N,1237ymous_ +B 5600,8000,300,300,CONT_DIF_N,969nymous_ +B 7600,24000,300,300,CONT_DIF_N,1023ymous_ +B 18800,6000,300,300,CONT_VIA,1345ymous_ +B 16800,35800,300,300,CONT_VIA,1291ymous_ +B 20800,32400,300,300,CONT_BODY_P,377nymous_ +B 8600,30000,300,300,CONT_VIA2,1077ymous_ +B 10800,21800,300,300,CONT_VIA2,1131ymous_ +B 26000,30000,300,300,CONT_DIF_P,485nymous_ +B 24000,29200,300,300,CONT_POLY,431nymous_ +B 29600,33000,300,300,CONT_VIA2,592nymous_ +B 31600,22000,300,300,CONT_VIA2,646nymous_ +B 33800,36000,300,300,CONT_VIA,754nymous_ +B 27800,37600,300,300,CONT_BODY_N,539nymous_ +B 32800,23000,300,300,CONT_VIA2,700nymous_ +B 36000,23000,300,300,CONT_VIA2,808nymous_ +B 37000,31000,300,300,CONT_VIA,862nymous_ +B 4400,27000,300,300,CONT_DIF_N,916nymous_ +B 13600,19200,300,300,CONT_BODY_P,1184ymous_ +B 12800,17000,300,300,CONT_VIA2,1183ymous_ +B 12800,12600,300,300,CONT_DIF_P,1180ymous_ +B 5600,9000,300,300,CONT_DIF_N,970nymous_ +B 15600,35000,300,300,CONT_DIF_N,1238ymous_ +B 7600,24000,300,300,CONT_VIA,1024ymous_ +B 8600,31000,300,300,CONT_VIA2,1078ymous_ +B 18800,6000,300,300,CONT_VIA2,1346ymous_ +B 16800,37600,300,300,CONT_BODY_P,1292ymous_ +B 24000,34200,300,300,CONT_POLY,432nymous_ +B 20800,33400,300,300,CONT_BODY_P,378nymous_ +B 29600,34000,300,300,CONT_VIA2,593nymous_ +B 10800,23000,300,300,CONT_DIF_N,1132ymous_ +B 26000,31200,300,300,CONT_DIF_P,486nymous_ +B 31600,23000,300,300,CONT_VIA2,647nymous_ +B 32800,27000,300,300,CONT_VIA2,701nymous_ +B 34000,19200,300,300,CONT_BODY_N,755nymous_ +B 36000,27000,300,300,CONT_VIA2,809nymous_ +B 37000,32000,300,300,CONT_DIF_P,863nymous_ +B 14000,21800,300,300,CONT_POLY,1185ymous_ +B 4400,27000,300,300,CONT_VIA,917nymous_ +B 5600,11800,300,300,CONT_DIF_P,971nymous_ +B 17400,11800,300,300,CONT_POLY,1293ymous_ +B 15600,36000,300,300,CONT_DIF_N,1239ymous_ +B 7600,24000,300,300,CONT_VIA2,1025ymous_ +B 8600,32000,300,300,CONT_VIA2,1079ymous_ +B 18800,9000,300,300,CONT_DIF_N,1347ymous_ +B 24000,34200,300,300,CONT_VIA,433nymous_ +B 20800,34400,300,300,CONT_BODY_P,379nymous_ +B 29600,35000,300,300,CONT_VIA2,594nymous_ +B 10800,24000,300,300,CONT_DIF_N,1133ymous_ +B 12800,16000,300,300,CONT_BODY_N,1181ymous_ +B 26000,31200,300,300,CONT_VIA,487nymous_ +B 31600,27000,300,300,CONT_VIA2,648nymous_ +B 32800,28000,300,300,CONT_VIA2,702nymous_ +B 3400,24000,300,300,CONT_VIA2,756nymous_ +B 36000,28000,300,300,CONT_VIA2,810nymous_ +B 37000,32000,300,300,CONT_VIA,864nymous_ +B 4400,28000,300,300,CONT_DIF_N,918nymous_ +B 14000,21800,300,300,CONT_VIA,1186ymous_ +B 5600,12800,300,300,CONT_DIF_P,972nymous_ +B 7600,25000,300,300,CONT_DIF_N,1026ymous_ +B 17600,6000,300,300,CONT_BODY_P,1294ymous_ +B 15600,19200,300,300,CONT_BODY_P,1240ymous_ +B 20800,35400,300,300,CONT_BODY_P,380nymous_ +B 8600,36000,300,300,CONT_VIA2,1080ymous_ +B 10800,25000,300,300,CONT_DIF_N,1134ymous_ +B 18800,16000,300,300,CONT_BODY_N,1348ymous_ +B 26000,32400,300,300,CONT_DIF_P,488nymous_ +B 24000,34200,300,300,CONT_VIA2,434nymous_ +B 29600,7000,300,300,CONT_DIF_N,595nymous_ +B 31600,28000,300,300,CONT_VIA2,649nymous_ +B 32800,29000,300,300,CONT_VIA2,703nymous_ +B 3400,25000,300,300,CONT_VIA2,757nymous_ +B 36000,29000,300,300,CONT_VIA2,811nymous_ +B 37000,33000,300,300,CONT_DIF_P,865nymous_ +B 4400,28000,300,300,CONT_VIA,919nymous_ +B 15800,27000,300,300,CONT_VIA2,1241ymous_ +B 14000,21800,300,300,CONT_VIA2,1187ymous_ +B 5600,13800,300,300,CONT_DIF_P,973nymous_ +B 7600,25000,300,300,CONT_VIA,1027ymous_ +B 18800,17000,300,300,CONT_VIA,1349ymous_ +B 17600,6000,300,300,CONT_VIA,1295ymous_ +B 20800,36400,300,300,CONT_BODY_P,381nymous_ +B 8600,19200,300,300,CONT_BODY_P,1081ymous_ +B 24000,35800,300,300,CONT_POLY,435nymous_ +B 10800,26000,300,300,CONT_DIF_N,1135ymous_ +B 26000,33600,300,300,CONT_DIF_P,489nymous_ +B 29600,10600,300,300,CONT_POLY,596nymous_ +B 31600,29000,300,300,CONT_VIA2,650nymous_ +B 3400,26000,300,300,CONT_VIA2,758nymous_ +B 32800,33000,300,300,CONT_VIA2,704nymous_ +B 36000,33000,300,300,CONT_VIA2,812nymous_ +B 37000,33000,300,300,CONT_VIA,866nymous_ +B 4400,29000,300,300,CONT_DIF_N,920nymous_ +B 5600,16000,300,300,CONT_BODY_N,974nymous_ +B 15800,28000,300,300,CONT_VIA2,1242ymous_ +B 14000,23000,300,300,CONT_DIF_N,1188ymous_ +B 7600,25000,300,300,CONT_VIA2,1028ymous_ +B 8800,37600,300,300,CONT_BODY_P,1082ymous_ +B 18800,17000,300,300,CONT_VIA2,1350ymous_ +B 17600,6000,300,300,CONT_VIA2,1296ymous_ +B 24000,35800,300,300,CONT_VIA,436nymous_ +B 20800,37600,300,300,CONT_BODY_P,382nymous_ +B 28000,24000,300,300,CONT_DIF_P,543nymous_ +B 29600,13000,300,300,CONT_DIF_P,597nymous_ +B 10800,27000,300,300,CONT_DIF_N,1136ymous_ +B 26000,33600,300,300,CONT_VIA,490nymous_ +B 31600,33000,300,300,CONT_VIA2,651nymous_ +B 32800,34000,300,300,CONT_VIA2,705nymous_ +B 3400,30000,300,300,CONT_VIA2,759nymous_ +B 36000,34000,300,300,CONT_VIA2,813nymous_ +B 37000,33000,300,300,CONT_VIA2,867nymous_ +B 14000,24000,300,300,CONT_DIF_N,1189ymous_ +B 4400,29000,300,300,CONT_VIA,921nymous_ +B 5600,17000,300,300,CONT_VIA,975nymous_ +B 7600,26000,300,300,CONT_DIF_N,1029ymous_ +B 28000,22800,300,300,CONT_DIF_P,542nymous_ +B 17600,8600,300,300,CONT_DIF_N,1297ymous_ +B 15800,29000,300,300,CONT_VIA2,1243ymous_ +B 8800,37600,300,300,CONT_VIA,1083ymous_ +B 19600,19200,300,300,CONT_BODY_P,1351ymous_ +B 24000,37600,300,300,CONT_BODY_N,437nymous_ +B 20800,19200,300,300,CONT_BODY_P,383nymous_ +B 28000,25200,300,300,CONT_DIF_P,544nymous_ +B 29600,14000,300,300,CONT_DIF_P,598nymous_ +B 10800,28000,300,300,CONT_DIF_N,1137ymous_ +B 26000,35000,300,300,CONT_DIF_P,491nymous_ +B 31600,34000,300,300,CONT_VIA2,652nymous_ +B 32800,35000,300,300,CONT_VIA2,706nymous_ +B 3400,31000,300,300,CONT_VIA2,760nymous_ +B 36000,35000,300,300,CONT_VIA2,814nymous_ +B 37000,34000,300,300,CONT_DIF_P,868nymous_ +B 4400,30000,300,300,CONT_DIF_N,922nymous_ +B 14000,25000,300,300,CONT_DIF_N,1190ymous_ +B 5600,17000,300,300,CONT_VIA2,976nymous_ +B 7600,26000,300,300,CONT_VIA,1030ymous_ +B 17600,12800,300,300,CONT_DIF_P,1298ymous_ +B 15800,37600,300,300,CONT_BODY_P,1244ymous_ +B 21000,13000,300,300,CONT_VIA,384nymous_ +B 28000,26400,300,300,CONT_DIF_P,545nymous_ +B 8800,37600,300,300,CONT_VIA2,1084ymous_ +B 10800,29000,300,300,CONT_DIF_N,1138ymous_ +B 19800,22600,300,300,CONT_POLY,1352ymous_ +B 26000,36400,300,300,CONT_DIF_P,492nymous_ +B 24000,19200,300,300,CONT_BODY_N,438nymous_ +B 29600,16000,300,300,CONT_BODY_N,599nymous_ +B 31600,35000,300,300,CONT_VIA2,653nymous_ +B 33000,19200,300,300,CONT_BODY_N,707nymous_ +B 3400,32000,300,300,CONT_VIA2,761nymous_ +B 36000,19200,300,300,CONT_BODY_N,815nymous_ +B 37000,34000,300,300,CONT_VIA,869nymous_ +B 4400,30000,300,300,CONT_VIA,923nymous_ +B 1600,20400,300,300,CONT_BODY_P,1245ymous_ +B 14000,26000,300,300,CONT_DIF_N,1191ymous_ +B 5600,19200,300,300,CONT_BODY_P,977nymous_ +B 7600,26000,300,300,CONT_VIA2,1031ymous_ +B 19800,26200,300,300,CONT_POLY,1353ymous_ +B 17600,16000,300,300,CONT_BODY_N,1299ymous_ +B 21000,14000,300,300,CONT_VIA,385nymous_ +B 28000,27600,300,300,CONT_DIF_P,546nymous_ +B 9200,23000,300,300,CONT_DIF_N,1085ymous_ +B 10800,30000,300,300,CONT_DIF_N,1139ymous_ +B 26000,37600,300,300,CONT_BODY_N,493nymous_ +B 24800,6000,300,300,CONT_BODY_P,439nymous_ +B 29600,17000,300,300,CONT_VIA,600nymous_ +B 31800,9000,300,300,CONT_POLY,654nymous_ +B 3400,36000,300,300,CONT_VIA2,762nymous_ +B 33200,6000,300,300,CONT_BODY_P,708nymous_ +B 3600,37600,300,300,CONT_BODY_P,816nymous_ +B 37000,34000,300,300,CONT_VIA2,870nymous_ +B 4400,30000,300,300,CONT_VIA2,924nymous_ +B 6000,23000,300,300,CONT_DIF_N,978nymous_ +B 1600,21400,300,300,CONT_BODY_P,1246ymous_ +B 14000,27000,300,300,CONT_DIF_N,1192ymous_ +B 7600,27000,300,300,CONT_DIF_N,1032ymous_ +B 9200,24000,300,300,CONT_DIF_N,1086ymous_ +B 19800,27400,300,300,CONT_POLY,1354ymous_ +B 17600,17000,300,300,CONT_VIA,1300ymous_ +B 24800,6000,300,300,CONT_VIA,440nymous_ +B 21200,6000,300,300,CONT_BODY_P,386nymous_ +B 28000,28800,300,300,CONT_DIF_P,547nymous_ +B 29600,17000,300,300,CONT_VIA2,601nymous_ +B 10800,31000,300,300,CONT_DIF_N,1140ymous_ +B 26000,6000,300,300,CONT_BODY_P,494nymous_ +B 31800,12200,300,300,CONT_POLY,655nymous_ +B 33200,6000,300,300,CONT_VIA,709nymous_ +B 34400,6000,300,300,CONT_BODY_P,763nymous_ +B 3600,37600,300,300,CONT_VIA,817nymous_ +B 37000,35000,300,300,CONT_DIF_P,871nymous_ +B 14000,28000,300,300,CONT_DIF_N,1193ymous_ +B 4400,31000,300,300,CONT_DIF_N,925nymous_ +B 6000,24000,300,300,CONT_DIF_N,979nymous_ +B 17600,17000,300,300,CONT_VIA2,1301ymous_ +B 1600,22400,300,300,CONT_BODY_P,1247ymous_ +B 7600,27000,300,300,CONT_VIA,1033ymous_ +B 9200,25000,300,300,CONT_DIF_N,1087ymous_ +B 19800,28200,300,300,CONT_VIA,1355ymous_ +B 24800,6000,300,300,CONT_VIA2,441nymous_ +B 21200,6000,300,300,CONT_VIA,387nymous_ +B 28000,30000,300,300,CONT_DIF_P,548nymous_ +B 30000,20200,300,300,CONT_VIA,602nymous_ +B 10800,32000,300,300,CONT_DIF_N,1141ymous_ +B 26000,6000,300,300,CONT_VIA,495nymous_ +B 32000,6000,300,300,CONT_BODY_P,656nymous_ +B 33200,6000,300,300,CONT_VIA2,710nymous_ +B 34400,6000,300,300,CONT_VIA,764nymous_ +B 3600,37600,300,300,CONT_VIA2,818nymous_ +B 37000,35000,300,300,CONT_VIA,872nymous_ +B 4400,31000,300,300,CONT_VIA,926nymous_ +B 14000,29000,300,300,CONT_DIF_N,1194ymous_ +B 6000,25000,300,300,CONT_DIF_N,980nymous_ +B 7600,28000,300,300,CONT_DIF_N,1034ymous_ +B 1600,23400,300,300,CONT_BODY_P,1248ymous_ +B 17600,19200,300,300,CONT_BODY_P,1302ymous_ +B 21200,6000,300,300,CONT_VIA2,388nymous_ +B 28000,31200,300,300,CONT_DIF_P,549nymous_ +B 9200,26000,300,300,CONT_DIF_N,1088ymous_ +B 10800,33000,300,300,CONT_DIF_N,1142ymous_ +B 19800,31000,300,300,CONT_POLY,1356ymous_ +B 26000,6000,300,300,CONT_VIA2,496nymous_ +B 24800,8000,300,300,CONT_DIF_N,442nymous_ +B 30000,19200,300,300,CONT_BODY_N,603nymous_ +B 32000,6000,300,300,CONT_VIA,657nymous_ +B 33200,8000,300,300,CONT_DIF_N,711nymous_ +B 34400,6000,300,300,CONT_VIA2,765nymous_ +B 3600,19200,300,300,CONT_BODY_P,819nymous_ +B 37000,35000,300,300,CONT_VIA2,873nymous_ +B 4400,31000,300,300,CONT_VIA2,927nymous_ +B 1600,24400,300,300,CONT_BODY_P,1249ymous_ +B 14000,30000,300,300,CONT_DIF_N,1195ymous_ +B 6000,26000,300,300,CONT_DIF_N,981nymous_ +B 7600,28000,300,300,CONT_VIA,1035ymous_ +B 19800,35200,300,300,CONT_VIA,1357ymous_ +B 17800,23200,300,300,CONT_DIF_N,1303ymous_ +B 21200,9000,300,300,CONT_DIF_N,389nymous_ +B 28000,31200,300,300,CONT_VIA,550nymous_ +B 9200,27000,300,300,CONT_DIF_N,1089ymous_ +B 10800,34000,300,300,CONT_DIF_N,1143ymous_ +B 26000,8000,300,300,CONT_DIF_N,497nymous_ +B 24800,13000,300,300,CONT_DIF_P,443nymous_ +B 30400,36600,300,300,CONT_POLY,604nymous_ +B 32000,6000,300,300,CONT_VIA2,658nymous_ +B 34400,8000,300,300,CONT_DIF_N,766nymous_ +B 33200,13000,300,300,CONT_DIF_P,712nymous_ +B 36800,6000,300,300,CONT_BODY_P,820nymous_ +B 37000,36000,300,300,CONT_DIF_P,874nymous_ +B 4400,32000,300,300,CONT_DIF_N,928nymous_ +B 6000,27000,300,300,CONT_DIF_N,982nymous_ +B 1600,25400,300,300,CONT_BODY_P,1250ymous_ +B 14000,31000,300,300,CONT_DIF_N,1196ymous_ +B 7600,29000,300,300,CONT_DIF_N,1036ymous_ +B 9200,28000,300,300,CONT_DIF_N,1090ymous_ +B 19800,37600,300,300,CONT_BODY_P,1358ymous_ +B 17800,23200,300,300,CONT_VIA,1304ymous_ +B 24800,13000,300,300,CONT_VIA,444nymous_ +B 21200,16000,300,300,CONT_BODY_N,390nymous_ +B 28000,32400,300,300,CONT_DIF_P,551nymous_ +B 30400,36600,300,300,CONT_VIA,605nymous_ +B 10800,35000,300,300,CONT_DIF_N,1144ymous_ +B 26000,12000,300,300,CONT_VIA2,498nymous_ +B 32000,8000,300,300,CONT_DIF_N,659nymous_ +B 33200,14000,300,300,CONT_DIF_P,713nymous_ +B 34400,13000,300,300,CONT_DIF_P,767nymous_ +B 36800,6000,300,300,CONT_VIA,821nymous_ +B 37000,36000,300,300,CONT_VIA,875nymous_ +B 14000,32000,300,300,CONT_DIF_N,1197ymous_ +B 4400,32000,300,300,CONT_VIA,929nymous_ +B 6000,28000,300,300,CONT_DIF_N,983nymous_ +B 17800,24400,300,300,CONT_DIF_N,1305ymous_ +B 1600,26400,300,300,CONT_BODY_P,1251ymous_ +B 7600,29000,300,300,CONT_VIA,1037ymous_ +B 9200,29000,300,300,CONT_DIF_N,1091ymous_ +B 22000,22200,300,300,CONT_VIA,391nymous_ +B 28000,33600,300,300,CONT_DIF_P,552nymous_ +B 10800,36000,300,300,CONT_DIF_N,1145ymous_ +B 26000,13000,300,300,CONT_DIF_P,499nymous_ +B 24800,14000,300,300,CONT_DIF_P,445nymous_ +B 30400,36600,300,300,CONT_VIA2,606nymous_ +B 32000,13000,300,300,CONT_DIF_P,660nymous_ +B 33200,16000,300,300,CONT_BODY_N,714nymous_ +B 34400,13000,300,300,CONT_VIA,768nymous_ +B 36800,6000,300,300,CONT_VIA2,822nymous_ +B 37000,19200,300,300,CONT_BODY_N,876nymous_ +B 4400,32000,300,300,CONT_VIA2,930nymous_ +B 14000,33000,300,300,CONT_DIF_N,1198ymous_ +B 6000,29000,300,300,CONT_DIF_N,984nymous_ +B 7600,30000,300,300,CONT_DIF_N,1038ymous_ +B 17800,24400,300,300,CONT_VIA2,1306ymous_ +B 1600,27400,300,300,CONT_BODY_P,1252ymous_ +B 22000,19200,300,300,CONT_VIA,392nymous_ +B 28000,35000,300,300,CONT_DIF_P,553nymous_ +B 9200,30000,300,300,CONT_DIF_N,1092ymous_ +B 11600,6000,300,300,CONT_BODY_P,1146ymous_ +B 26000,13000,300,300,CONT_VIA2,500nymous_ +B 24800,14000,300,300,CONT_VIA,446nymous_ +B 30600,22000,300,300,CONT_DIF_P,607nymous_ +B 32000,16000,300,300,CONT_BODY_N,661nymous_ +B 33200,17000,300,300,CONT_VIA,715nymous_ +B 34400,14000,300,300,CONT_DIF_P,769nymous_ +B 36800,7000,300,300,CONT_BODY_P,823nymous_ +B 37200,37600,300,300,CONT_BODY_N,877nymous_ +B 4400,33000,300,300,CONT_DIF_N,931nymous_ +B 1600,28400,300,300,CONT_BODY_P,1253ymous_ +B 14000,34000,300,300,CONT_DIF_N,1199ymous_ +B 6000,30000,300,300,CONT_DIF_N,985nymous_ +B 7600,30000,300,300,CONT_VIA,1039ymous_ +B 9200,31000,300,300,CONT_DIF_N,1093ymous_ +B 17800,25600,300,300,CONT_DIF_N,1307ymous_ +B 22400,6000,300,300,CONT_BODY_P,393nymous_ +B 28000,19200,300,300,CONT_BODY_N,554nymous_ +B 11600,6000,300,300,CONT_VIA,1147ymous_ +B 26000,14000,300,300,CONT_DIF_P,501nymous_ +B 24800,16000,300,300,CONT_BODY_N,447nymous_ +B 30600,23000,300,300,CONT_DIF_P,608nymous_ +B 32000,17000,300,300,CONT_VIA,662nymous_ +B 34400,14000,300,300,CONT_VIA,770nymous_ +B 33200,17000,300,300,CONT_VIA2,716nymous_ +B 36800,8000,300,300,CONT_BODY_P,824nymous_ +B 38000,27000,300,300,CONT_VIA2,878nymous_ +B 4400,33000,300,300,CONT_VIA,932nymous_ +B 6000,31000,300,300,CONT_DIF_N,986nymous_ +B 1600,29400,300,300,CONT_BODY_P,1254ymous_ +B 14000,35000,300,300,CONT_DIF_N,1200ymous_ +B 7600,30000,300,300,CONT_VIA2,1040ymous_ +B 9200,32000,300,300,CONT_DIF_N,1094ymous_ +B 17800,25600,300,300,CONT_VIA,1308ymous_ +B 25000,20400,300,300,CONT_DIF_P,448nymous_ +B 22400,6000,300,300,CONT_VIA,394nymous_ +B 2800,23000,300,300,CONT_DIF_N,555nymous_ +B 30600,24000,300,300,CONT_DIF_P,609nymous_ +B 11600,6000,300,300,CONT_VIA2,1148ymous_ +B 26000,14000,300,300,CONT_VIA2,502nymous_ +B 32000,17000,300,300,CONT_VIA2,663nymous_ +B 33800,22000,300,300,CONT_DIF_P,717nymous_ +B 34400,16000,300,300,CONT_BODY_N,771nymous_ +B 36800,9000,300,300,CONT_BODY_P,825nymous_ +B 38000,28000,300,300,CONT_VIA2,879nymous_ +B 14000,36000,300,300,CONT_DIF_N,1201ymous_ +B 4400,34000,300,300,CONT_DIF_N,933nymous_ +B 6000,32000,300,300,CONT_DIF_N,987nymous_ +B 17800,25600,300,300,CONT_VIA2,1309ymous_ +B 1600,30400,300,300,CONT_BODY_P,1255ymous_ +B 7600,31000,300,300,CONT_DIF_N,1041ymous_ +B 9200,33000,300,300,CONT_DIF_N,1095ymous_ +B 25000,20400,300,300,CONT_VIA,449nymous_ +B 22400,6000,300,300,CONT_VIA2,395nymous_ +B 2800,24000,300,300,CONT_DIF_N,556nymous_ +B 30600,25000,300,300,CONT_DIF_P,610nymous_ +B 11600,8000,300,300,CONT_DIF_N,1149ymous_ +B 26000,16000,300,300,CONT_BODY_N,503nymous_ +B 32000,19200,300,300,CONT_BODY_N,664nymous_ +B 33800,22000,300,300,CONT_VIA,718nymous_ +B 34800,20200,300,300,CONT_POLY,772nymous_ +B 36800,9000,300,300,CONT_VIA2,826nymous_ +B 38000,29000,300,300,CONT_VIA2,880nymous_ +B 4400,34000,300,300,CONT_VIA,934nymous_ +B 14000,6000,300,300,CONT_BODY_P,1202ymous_ +B 6000,33000,300,300,CONT_DIF_N,988nymous_ +B 7600,31000,300,300,CONT_VIA,1042ymous_ +B 17800,26800,300,300,CONT_DIF_N,1310ymous_ +B 1600,31400,300,300,CONT_BODY_P,1256ymous_ +B 22400,8600,300,300,CONT_DIF_N,396nymous_ +B 2800,25000,300,300,CONT_DIF_N,557nymous_ +B 9200,34000,300,300,CONT_DIF_N,1096ymous_ +B 11600,9000,300,300,CONT_DIF_N,1150ymous_ +B 26000,17000,300,300,CONT_VIA,504nymous_ +B 25000,21600,300,300,CONT_DIF_P,450nymous_ +B 30600,26000,300,300,CONT_DIF_P,611nymous_ +B 3200,6000,300,300,CONT_BODY_P,665nymous_ +B 33800,22000,300,300,CONT_VIA2,719nymous_ +B 34800,22000,300,300,CONT_VIA2,773nymous_ +B 36800,10000,300,300,CONT_VIA2,827nymous_ +B 38000,33000,300,300,CONT_VIA2,881nymous_ +B 4400,35000,300,300,CONT_DIF_N,935nymous_ +B 1600,32400,300,300,CONT_BODY_P,1257ymous_ +B 14000,6000,300,300,CONT_VIA,1203ymous_ +B 6000,34000,300,300,CONT_DIF_N,989nymous_ +B 7600,31000,300,300,CONT_VIA2,1043ymous_ +B 17800,28000,300,300,CONT_DIF_N,1311ymous_ +B 22400,16000,300,300,CONT_BODY_N,397nymous_ +B 2800,26000,300,300,CONT_DIF_N,558nymous_ +B 9200,35000,300,300,CONT_DIF_N,1097ymous_ +B 11600,11800,300,300,CONT_DIF_P,1151ymous_ +B 26000,17000,300,300,CONT_VIA2,505nymous_ +B 25000,22800,300,300,CONT_DIF_P,451nymous_ +B 30600,27000,300,300,CONT_DIF_P,612nymous_ +B 3200,6000,300,300,CONT_VIA,666nymous_ +B 34800,23000,300,300,CONT_VIA2,774nymous_ +B 33800,23000,300,300,CONT_DIF_P,720nymous_ +B 36800,11000,300,300,CONT_VIA2,828nymous_ +B 38000,34000,300,300,CONT_VIA2,882nymous_ +B 4400,35000,300,300,CONT_VIA,936nymous_ +B 6000,35000,300,300,CONT_DIF_N,990nymous_ +B 1600,33400,300,300,CONT_BODY_P,1258ymous_ +B 14000,6000,300,300,CONT_VIA2,1204ymous_ +B 7600,32000,300,300,CONT_DIF_N,1044ymous_ +B 9200,36000,300,300,CONT_DIF_N,1098ymous_ +B 17800,28000,300,300,CONT_VIA,1312ymous_ +B 4400,36000,300,300,CONT_VIA,938nymous_ +B 38200,20400,300,300,CONT_BODY_N,884nymous_ +B 36800,13000,300,300,CONT_BODY_N,830nymous_ +B 34800,28000,300,300,CONT_VIA2,776nymous_ +B 33800,23000,300,300,CONT_VIA2,722nymous_ +B 3200,7000,300,300,CONT_BODY_P,668nymous_ +B 2600,37600,300,300,CONT_BODY_P,507nymous_ +B 11600,13800,300,300,CONT_DIF_P,1153ymous_ +B 30600,27000,300,300,CONT_VIA2,614nymous_ +B 2800,28000,300,300,CONT_DIF_N,560nymous_ +B 22400,17000,300,300,CONT_VIA2,399nymous_ +B 25000,24000,300,300,CONT_DIF_P,453nymous_ +B 9200,6000,300,300,CONT_BODY_P,1099ymous_ +B 7600,32000,300,300,CONT_VIA,1045ymous_ +B 1600,34400,300,300,CONT_BODY_P,1259ymous_ +B 17800,29200,300,300,CONT_DIF_N,1313ymous_ +B 6000,36000,300,300,CONT_DIF_N,991nymous_ +B 4400,36000,300,300,CONT_DIF_N,937nymous_ +B 14000,7200,300,300,CONT_DIF_N,1205ymous_ +B 38000,35000,300,300,CONT_VIA2,883nymous_ +B 36800,12000,300,300,CONT_BODY_N,829nymous_ +B 34800,27000,300,300,CONT_VIA2,775nymous_ +B 33800,23000,300,300,CONT_VIA,721nymous_ +B 3200,6000,300,300,CONT_VIA2,667nymous_ +B 26000,19200,300,300,CONT_BODY_N,506nymous_ +B 11600,12800,300,300,CONT_DIF_P,1152ymous_ +B 30600,27000,300,300,CONT_VIA,613nymous_ +B 2800,27000,300,300,CONT_DIF_N,559nymous_ +B 22400,17000,300,300,CONT_VIA,398nymous_ +B 25000,22800,300,300,CONT_VIA,452nymous_ +B 30600,28000,300,300,CONT_VIA,616nymous_ +B 25000,26400,300,300,CONT_DIF_P,455nymous_ +B 11600,16000,300,300,CONT_BODY_N,1155ymous_ +B 9200,6000,300,300,CONT_VIA2,1101ymous_ +B 2800,30000,300,300,CONT_DIF_N,562nymous_ +B 23000,21400,300,300,CONT_BODY_N,401nymous_ +B 17800,30400,300,300,CONT_VIA,1315ymous_ +B 7600,33000,300,300,CONT_DIF_N,1047ymous_ +B 6600,25000,300,300,CONT_VIA2,993nymous_ +B 14000,10000,300,300,CONT_POLY,1207ymous_ +B 1600,36400,300,300,CONT_BODY_P,1261ymous_ +B 4400,36000,300,300,CONT_VIA2,939nymous_ +B 38200,21400,300,300,CONT_BODY_N,885nymous_ +B 36800,14000,300,300,CONT_BODY_N,831nymous_ +B 34800,29000,300,300,CONT_VIA2,777nymous_ +B 33800,24000,300,300,CONT_DIF_P,723nymous_ +B 3200,7000,300,300,CONT_VIA2,669nymous_ +B 30600,28000,300,300,CONT_DIF_P,615nymous_ +B 25000,25200,300,300,CONT_DIF_P,454nymous_ +B 2600,19200,300,300,CONT_BODY_P,508nymous_ +B 11600,14800,300,300,CONT_DIF_P,1154ymous_ +B 9200,6000,300,300,CONT_VIA,1100ymous_ +B 2800,29000,300,300,CONT_DIF_N,561nymous_ +B 23000,20400,300,300,CONT_BODY_N,400nymous_ +B 1600,35400,300,300,CONT_BODY_P,1260ymous_ +B 17800,30400,300,300,CONT_DIF_N,1314ymous_ +B 7600,32000,300,300,CONT_VIA2,1046ymous_ +B 6600,24000,300,300,CONT_VIA2,992nymous_ +B 14000,8000,300,300,CONT_DIF_N,1206ymous_ +B 33800,27000,300,300,CONT_VIA2,731nymous_ +B 7600,34000,300,300,CONT_DIF_N,1049ymous_ +B 1600,19200,300,300,CONT_BODY_P,1263ymous_ +B 17800,31600,300,300,CONT_DIF_N,1317ymous_ +B 6600,30000,300,300,CONT_VIA2,995nymous_ +B 4400,6000,300,300,CONT_VIA,941nymous_ +B 14000,12800,300,300,CONT_DIF_P,1209ymous_ +B 38200,23400,300,300,CONT_BODY_N,887nymous_ +B 36800,15000,300,300,CONT_VIA2,833nymous_ +B 34800,34000,300,300,CONT_VIA2,779nymous_ +B 33800,25000,300,300,CONT_DIF_P,725nymous_ +B 3200,8000,300,300,CONT_VIA2,671nymous_ +B 27000,21600,300,300,CONT_DIF_P,510nymous_ +B 11600,17000,300,300,CONT_VIA,1156ymous_ +B 30600,28000,300,300,CONT_VIA2,617nymous_ +B 2800,31000,300,300,CONT_DIF_N,563nymous_ +B 23000,22400,300,300,CONT_BODY_N,402nymous_ +B 25000,27600,300,300,CONT_DIF_P,456nymous_ +B 17800,30400,300,300,CONT_VIA2,1316ymous_ +B 9200,7000,300,300,CONT_VIA2,1102ymous_ +B 7600,33000,300,300,CONT_VIA,1048ymous_ +B 14000,12000,300,300,CONT_DIF_P,1208ymous_ +B 1600,37600,300,300,CONT_BODY_P,1262ymous_ +B 6600,26000,300,300,CONT_VIA2,994nymous_ +B 4400,6000,300,300,CONT_BODY_P,940nymous_ +B 38200,22400,300,300,CONT_BODY_N,886nymous_ +B 36800,15000,300,300,CONT_BODY_N,832nymous_ +B 33800,24000,300,300,CONT_VIA,724nymous_ +B 34800,33000,300,300,CONT_VIA2,778nymous_ +B 3200,8000,300,300,CONT_BODY_P,670nymous_ +B 27000,20400,300,300,CONT_DIF_P,509nymous_ +B 12800,6000,300,300,CONT_VIA,1175ymous_ +B 36800,16000,300,300,CONT_VIA2,835nymous_ +B 35000,19200,300,300,CONT_BODY_N,781nymous_ +B 33800,26000,300,300,CONT_DIF_P,727nymous_ +B 3200,12000,300,300,CONT_BODY_N,673nymous_ +B 30600,29000,300,300,CONT_VIA,619nymous_ +B 25000,28800,300,300,CONT_DIF_P,458nymous_ +B 27000,24000,300,300,CONT_DIF_P,512nymous_ +B 11600,19200,300,300,CONT_BODY_P,1158ymous_ +B 9200,8000,300,300,CONT_DIF_N,1104ymous_ +B 2800,33000,300,300,CONT_DIF_N,565nymous_ +B 23000,24400,300,300,CONT_BODY_N,404nymous_ +B 16400,6000,300,300,CONT_BODY_P,1264ymous_ +B 17800,31600,300,300,CONT_VIA2,1318ymous_ +B 7600,34000,300,300,CONT_VIA,1050ymous_ +B 6600,31000,300,300,CONT_VIA2,996nymous_ +B 14000,16000,300,300,CONT_BODY_N,1210ymous_ +B 4400,6000,300,300,CONT_VIA2,942nymous_ +B 38200,24400,300,300,CONT_BODY_N,888nymous_ +B 36800,16000,300,300,CONT_BODY_N,834nymous_ +B 34800,35000,300,300,CONT_VIA2,780nymous_ +B 33800,25000,300,300,CONT_VIA,726nymous_ +B 3200,9000,300,300,CONT_BODY_P,672nymous_ +B 27000,22800,300,300,CONT_DIF_P,511nymous_ +B 11600,17000,300,300,CONT_VIA2,1157ymous_ +B 30600,29000,300,300,CONT_DIF_P,618nymous_ +B 2800,32000,300,300,CONT_DIF_N,564nymous_ +B 23000,23400,300,300,CONT_BODY_N,403nymous_ +B 25000,27600,300,300,CONT_VIA,457nymous_ +B 9200,7200,300,300,CONT_DIF_N,1103ymous_ +B 28000,21600,300,300,CONT_DIF_P,541nymous_ +B 17400,11000,200,200,CONT_TURN1,354nymous_ +B 17600,8000,200,200,CONT_TURN1,355nymous_ +B 12400,23000,300,300,CONT_DIF_N,1159ymous_ +B 9200,8000,300,300,CONT_VIA2,1105ymous_ +B 2800,34000,300,300,CONT_DIF_N,566nymous_ +B 23000,25400,300,300,CONT_BODY_N,405nymous_ +B 17800,32800,300,300,CONT_DIF_N,1319ymous_ +B 7600,35000,300,300,CONT_DIF_N,1051ymous_ +B 6600,32000,300,300,CONT_VIA2,997nymous_ +B 14000,17000,300,300,CONT_VIA,1211ymous_ +B 16400,6000,300,300,CONT_VIA,1265ymous_ +B 4400,8000,300,300,CONT_DIF_N,943nymous_ +B 38200,25400,300,300,CONT_BODY_N,889nymous_ +B 27000,25200,300,300,CONT_DIF_P,513nymous_ +B 25000,30000,300,300,CONT_DIF_P,459nymous_ +B 30600,29000,300,300,CONT_VIA2,620nymous_ +B 3200,12000,300,300,CONT_VIA2,674nymous_ +B 35400,22000,300,300,CONT_DIF_P,782nymous_ +B 33800,26000,300,300,CONT_VIA,728nymous_ +B 36800,17000,300,300,CONT_VIA,836nymous_ +B 38200,26400,300,300,CONT_BODY_N,890nymous_ +B 4400,9000,300,300,CONT_DIF_N,944nymous_ +B 6600,36000,300,300,CONT_VIA2,998nymous_ +B 16400,6000,300,300,CONT_VIA2,1266ymous_ +B 14000,17000,300,300,CONT_VIA2,1212ymous_ +B 7600,35000,300,300,CONT_VIA,1052ymous_ +B 9200,10000,300,300,CONT_POLY,1106ymous_ +B 17800,34000,300,300,CONT_DIF_N,1320ymous_ +B 25000,30000,300,300,CONT_VIA,460nymous_ +B 23000,26400,300,300,CONT_BODY_N,406nymous_ +B 2800,35000,300,300,CONT_DIF_N,567nymous_ +B 30600,30000,300,300,CONT_DIF_P,621nymous_ +B 12400,24000,300,300,CONT_DIF_N,1160ymous_ +B 27000,25200,300,300,CONT_VIA,514nymous_ +B 3200,13000,300,300,CONT_BODY_N,675nymous_ +B 33800,27000,300,300,CONT_DIF_P,729nymous_ +B 35400,23000,300,300,CONT_DIF_P,783nymous_ +B 36800,17000,300,300,CONT_VIA2,837nymous_ +B 38200,27400,300,300,CONT_BODY_N,891nymous_ +B 14600,19200,300,300,CONT_BODY_P,1213ymous_ +B 4400,11800,300,300,CONT_DIF_P,945nymous_ +B 6600,19200,300,300,CONT_BODY_P,999nymous_ +B 17800,35200,300,300,CONT_DIF_N,1321ymous_ +B 16400,8000,300,300,CONT_DIF_N,1267ymous_ +B 7600,36000,300,300,CONT_DIF_N,1053ymous_ +B 9200,12000,300,300,CONT_DIF_P,1107ymous_ +B 25000,31200,300,300,CONT_DIF_P,461nymous_ +B 23000,27400,300,300,CONT_BODY_N,407nymous_ +B 2800,36000,300,300,CONT_DIF_N,568nymous_ +B 30600,30000,300,300,CONT_VIA,622nymous_ +B 12400,25000,300,300,CONT_DIF_N,1161ymous_ +B 27000,26400,300,300,CONT_DIF_P,515nymous_ +B 3200,13000,300,300,CONT_VIA2,676nymous_ +B 33800,27000,300,300,CONT_VIA,730nymous_ +B 35400,24000,300,300,CONT_DIF_P,784nymous_ +B 37000,22000,300,300,CONT_DIF_P,838nymous_ +B 38200,28400,300,300,CONT_BODY_N,892nymous_ +B 4400,12800,300,300,CONT_DIF_P,946nymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/pi_mpx.vbe b/pdks/symbolic/mpxlib/cells/pi_mpx.vbe new file mode 100644 index 000000000..4e2b19e30 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pi_mpx.vbe @@ -0,0 +1,30 @@ +ENTITY pi_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_pad : NATURAL := 654; + CONSTANT tpll_pad : NATURAL := 1487; + CONSTANT rdown_pad : NATURAL := 234; + CONSTANT tphh_pad : NATURAL := 233; + CONSTANT rup_pad : NATURAL := 273 + ); + PORT ( + pad : in BIT; + t : out BIT; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pi_mpx; + + +ARCHITECTURE behaviour_data_flow OF pi_mpx IS + +BEGIN + t <= pad; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pi_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/piot_mpx.ap b/pdks/symbolic/mpxlib/cells/piot_mpx.ap new file mode 100644 index 000000000..88be62d8d --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/piot_mpx.ap @@ -0,0 +1,1572 @@ +V ALLIANCE : 6 +H piot_mpx,P,17/9/2014,100 +A 0,0,40000,80000 +I 0,40000,padreal_mpx,padreal,NOSYM +S 28800,9000,29000,9000,200,i,RIGHT,POLY +S 28000,-150,28000,10750,600,i,UP,ALU2 +S 28000,0,28000,0,400,i,RIGHT,CALU5 +S 28000,0,28000,0,400,i,RIGHT,CALU4 +S 27850,0,28150,0,600,i,RIGHT,CALU3 +S 27850,0,28150,0,600,i,RIGHT,CALU2 +S 27800,11800,28200,11800,200,i,RIGHT,POLY +S 30000,50,30000,10750,600,b,UP,ALU2 +S 30000,0,30000,0,400,b,RIGHT,CALU5 +S 30000,0,30000,0,400,b,RIGHT,CALU4 +S 29850,0,30150,0,600,b,RIGHT,CALU3 +S 29850,0,30150,0,600,b,RIGHT,CALU2 +S 29600,9800,29600,11400,200,b,UP,POLY +S 8000,0,8000,0,400,t,RIGHT,CALU5 +S 8000,0,8000,0,400,t,RIGHT,CALU4 +S 7850,0,8150,0,600,t,RIGHT,CALU3 +S 7850,0,8150,0,600,t,RIGHT,CALU2 +S 29000,35100,29000,39700,400,pad,UP,ALU1 +S 29000,25900,29000,34900,400,pad,UP,ALU1 +S 28600,33000,29000,33000,600,pad,RIGHT,POLY +S 28600,31800,29000,31800,600,pad,RIGHT,POLY +S 28600,30600,29000,30600,600,pad,RIGHT,POLY +S 28600,25800,29000,25800,600,pad,RIGHT,POLY +S 20000,48100,20000,71900,24400,pad,UP,CALU1 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +S 16800,35800,17200,35800,200,vdde,RIGHT,POLY +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 3600,22200,5200,22200,200,vdde,RIGHT,POLY +S 25100,28800,27900,28800,400,vdde,RIGHT,ALU1 +S 25100,26400,27900,26400,400,vdde,RIGHT,ALU1 +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 6800,22200,8400,22200,200,vdde,RIGHT,POLY +S 25100,21600,27900,21600,400,vdde,RIGHT,ALU1 +S 10650,21800,14150,21800,600,vdde,RIGHT,ALU2 +S 16800,30050,16800,38150,600,vdde,UP,ALU2 +S 16800,34600,17200,34600,200,vdde,RIGHT,POLY +S 16800,33400,17200,33400,200,vdde,RIGHT,POLY +S 16800,32200,17200,32200,200,vdde,RIGHT,POLY +S 24000,34200,24400,34200,600,vdde,RIGHT,POLY +S 24000,35800,24400,35800,600,vdde,RIGHT,POLY +S 25100,24000,27900,24000,400,vdde,RIGHT,ALU1 +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 3100,16000,36900,16000,2400,vddi,RIGHT,ALU1 +S 20000,9600,20000,11000,200,vddi,UP,POLY +S 17800,23050,17800,31750,600,vsse,UP,ALU2 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 7600,22900,7600,37500,400,vsse,UP,ALU1 +S 4400,22900,4400,37500,400,vsse,UP,ALU1 +S 30250,36600,30550,36600,600,vsse,RIGHT,ALU2 +S 30400,36400,30400,36600,200,vsse,UP,POLY +S 20800,22900,20800,37100,400,vsse,UP,ALU1 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 3100,6000,36900,6000,2400,vssi,RIGHT,ALU1 +S 27800,11800,27800,12400,200,92onymous_,UP,POLY +S 17500,22600,19100,22600,200,n6d,RIGHT,NTRANS +S 6800,22500,6800,36700,200,n14c,UP,NTRANS +S 850,34000,15950,34000,2400,248nymous_,RIGHT,ALU2 +S 14600,11100,14600,13100,200,p17c,UP,PTRANS +S 34800,20200,34800,20600,600,169nymous_,UP,POLY +S 30800,10600,33800,10600,200,cnbb,RIGHT,POLY +S 30800,8100,30800,12900,400,cnbb,UP,ALU1 +S 29000,200,29000,2000,0,10onymous_,UP,TALU3 +S 17700,22000,18900,22000,620,318nymous_,RIGHT,NDIF +S 24900,20400,28100,20400,620,51onymous_,RIGHT,PDIF +S 6200,10900,6200,14900,200,p18b,UP,PTRANS +S 27800,9800,32600,9800,200,91onymous_,RIGHT,POLY +S 30800,12700,30800,14300,620,126nymous_,UP,PDIF +S 17700,23200,18900,23200,620,319nymous_,RIGHT,NDIF +S 14800,22500,14800,36700,200,n15d,UP,NTRANS +S 24900,21600,28100,21600,420,52onymous_,RIGHT,PDIF +S 35600,200,35600,2000,9000,11onymous_,UP,TALU3 +S 35000,7300,35000,8300,200,n5b,UP,NTRANS +S 6800,6100,6800,7900,400,210nymous_,UP,ALU1 +S 27800,12500,27800,14500,200,p1,UP,PTRANS +S 17700,25600,18900,25600,620,321nymous_,RIGHT,NDIF +S 15200,7500,15200,9100,620,286nymous_,UP,NDIF +S 6800,7500,6800,9100,620,211nymous_,UP,NDIF +S 18000,200,18000,12000,18000,13onymous_,UP,TALU5 +S 27850,10600,28350,10600,600,93onymous_,RIGHT,ALU2 +S 10400,7500,10400,9100,420,249nymous_,UP,NDIF +S 35000,12700,35000,14700,200,p5b,UP,PTRANS +S 30800,13100,30800,13900,400,127nymous_,UP,ALU1 +S 24900,22800,28100,22800,420,53onymous_,RIGHT,PDIF +S 15300,37600,20700,37600,400,285nymous_,RIGHT,ALU1 +S 17700,24400,18900,24400,620,320nymous_,RIGHT,NDIF +S 3400,200,3400,12000,7000,12onymous_,UP,TALU5 +S 24900,24000,28100,24000,420,54onymous_,RIGHT,PDIF +S 31000,5850,31000,11150,600,128nymous_,UP,ALU2 +S 35400,21100,35400,36500,620,170nymous_,UP,PDIF +S 29000,200,29000,12000,0,14onymous_,UP,TALU5 +S 6900,10000,12700,10000,400,212nymous_,RIGHT,ALU1 +S 17700,26800,18900,26800,620,322nymous_,RIGHT,NDIF +S 15200,8100,15200,8900,400,287nymous_,UP,ALU1 +S 24900,25200,28100,25200,420,55onymous_,RIGHT,PDIF +S 30850,6000,32150,6000,600,129nymous_,RIGHT,ALU2 +S 35400,21300,35400,39700,400,171nymous_,UP,ALU1 +S 35600,200,35600,12000,9000,15onymous_,UP,TALU5 +S 6800,11100,6800,14700,620,213nymous_,UP,PDIF +S 17700,28000,18900,28000,620,323nymous_,RIGHT,NDIF +S 15200,11100,15200,12500,400,288nymous_,UP,ALU1 +S 24900,26400,28100,26400,420,56onymous_,RIGHT,PDIF +S 30850,10000,35950,10000,2400,130nymous_,RIGHT,ALU2 +S 35250,13000,36950,13000,2400,172nymous_,RIGHT,ALU2 +S 17700,29200,18900,29200,620,324nymous_,RIGHT,NDIF +S 0,6000,40000,6000,12000,16onymous_,RIGHT,TALU6 +S 6800,12100,6800,15900,400,214nymous_,UP,ALU1 +S 15200,11300,15200,12900,620,289nymous_,UP,PDIF +S 24900,27600,28100,27600,420,57onymous_,RIGHT,PDIF +S 31400,20900,31400,34300,200,p14a,UP,PTRANS +S 35600,6100,35600,7900,400,173nymous_,UP,ALU1 +S 17700,30400,18900,30400,620,325nymous_,RIGHT,NDIF +S 15600,20700,15600,36300,400,290nymous_,UP,ALU1 +S 2800,20500,2800,36300,400,94onymous_,UP,ALU1 +S 20000,40100,20000,59900,4400,17onymous_,UP,ALU1 +S 7000,7050,7000,14150,600,215nymous_,UP,ALU2 +S 10250,7600,27150,7600,600,250nymous_,RIGHT,ALU2 +S 24900,28800,28100,28800,420,58onymous_,RIGHT,PDIF +S 31400,35300,31400,36100,200,p11,UP,PTRANS +S 24900,30000,28100,30000,420,59onymous_,RIGHT,PDIF +S 10400,8100,10400,8900,400,251nymous_,UP,ALU1 +S 15600,22700,15600,36500,620,291nymous_,UP,NDIF +S 17700,31600,18900,31600,620,326nymous_,RIGHT,NDIF +S 7400,7300,7400,9300,200,n18c,UP,NTRANS +S 20000,8100,20000,8500,400,18onymous_,UP,ALU1 +S 2800,22700,2800,36500,620,95onymous_,UP,NDIF +S 35600,7500,35600,8100,620,174nymous_,UP,NDIF +S 31400,19250,31400,28150,600,131nymous_,UP,ALU2 +S 35600,12900,35600,14500,620,175nymous_,UP,PDIF +S 7400,9600,7400,10600,200,216nymous_,UP,POLY +S 17700,32800,18900,32800,620,327nymous_,RIGHT,NDIF +S 15450,18200,21150,18200,600,292nymous_,RIGHT,ALU2 +S 24900,31200,28100,31200,420,60onymous_,RIGHT,PDIF +S 10400,11100,10400,13700,400,252nymous_,UP,ALU1 +S 2200,13600,37800,13600,6800,96onymous_,RIGHT,NWELL +S 31600,20200,31600,20600,600,132nymous_,UP,POLY +S 35600,13100,35600,15900,400,176nymous_,UP,ALU1 +S 2900,20600,15500,20600,400,pad2,RIGHT,ALU1 +S 2700,20600,15700,20600,400,pad2,RIGHT,ALU1 +S 21000,12850,21000,18350,600,pad2,UP,ALU2 +S 20000,8500,20000,9100,620,pad2,UP,NDIF +S 7400,10900,7400,14900,200,p18c,UP,PTRANS +S 17700,34000,18900,34000,620,328nymous_,RIGHT,NDIF +S 15600,18050,15600,20350,600,293nymous_,UP,ALU2 +S 24900,32400,28100,32400,420,61onymous_,RIGHT,PDIF +S 10400,11100,10400,14700,620,253nymous_,UP,PDIF +S 24900,33600,28100,33600,420,62onymous_,RIGHT,PDIF +S 15800,23850,15800,32150,600,294nymous_,UP,ALU2 +S 17700,35200,18900,35200,620,329nymous_,RIGHT,NDIF +S 7600,21800,7600,22200,600,217nymous_,UP,POLY +S 35450,17000,36950,17000,600,177nymous_,RIGHT,ALU2 +S 31800,12000,31800,12200,200,133nymous_,UP,POLY +S 20000,11100,20000,15900,400,19onymous_,UP,ALU1 +S 28200,9100,28200,11700,400,97onymous_,UP,ALU1 +S 10700,39600,35500,39600,2400,254nymous_,RIGHT,ALU1 +S 28300,9000,28700,9000,400,98onymous_,RIGHT,ALU1 +S 31850,6000,36950,6000,600,134nymous_,RIGHT,ALU2 +S 36000,20200,36000,20600,600,178nymous_,UP,POLY +S 20000,12850,20000,17150,600,20onymous_,UP,ALU2 +S 7450,21800,9950,21800,600,218nymous_,RIGHT,ALU2 +S 17700,36400,18900,36400,620,330nymous_,RIGHT,NDIF +S 15800,7300,15800,9300,200,n17d,UP,NTRANS +S 24900,35000,28100,35000,820,63onymous_,RIGHT,PDIF +S 10800,21800,10800,22200,600,255nymous_,UP,POLY +S 28400,7500,28400,8100,620,99onymous_,UP,NDIF +S 32000,7500,32000,8100,620,135nymous_,UP,NDIF +S 3600,22500,3600,36700,200,n14a,UP,NTRANS +S 15800,9600,15800,10800,200,295nymous_,UP,POLY +S 20600,8300,20600,9300,200,n16c,UP,NTRANS +S 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20800,19080,20800,37720,600,22onymous_,UP,PTIE +S 7600,22850,7600,38150,2400,221nymous_,UP,ALU2 +S 11000,7300,11000,9300,200,n18f,UP,NTRANS +S 32000,12900,32000,14500,620,138nymous_,UP,PDIF +S 36200,20900,36200,36700,200,p14d,UP,PTRANS +S 17600,12500,17600,12900,620,334nymous_,UP,PDIF +S 1700,19200,20700,19200,400,297nymous_,RIGHT,ALU1 +S 28850,24600,30150,24600,600,103nymous_,RIGHT,ALU2 +S 24800,13100,24800,14500,620,67onymous_,UP,PDIF +S 21000,13100,21000,13900,400,23onymous_,UP,ALU1 +S 8000,50,8000,11150,600,222nymous_,UP,ALU2 +S 11000,9600,11000,10600,200,258nymous_,UP,POLY +S 3200,5880,3200,8720,600,139nymous_,UP,PTIE +S 36700,37600,38100,37600,400,181nymous_,RIGHT,ALU1 +S 17700,12800,18300,12800,400,335nymous_,RIGHT,ALU1 +S 1480,19200,20920,19200,600,298nymous_,RIGHT,PTIE +S 13200,22200,14800,22200,200,cn,RIGHT,POLY +S 10000,22200,11600,22200,200,cn,RIGHT,POLY +S 4250,21800,7750,21800,600,cn,RIGHT,ALU2 +S 25100,22800,27900,22800,400,cn,RIGHT,ALU1 +S 25100,20400,27900,20400,400,cn,RIGHT,ALU1 +S 25000,20250,25000,22950,600,cn,UP,ALU2 +S 21100,13000,22300,13000,400,24onymous_,RIGHT,ALU1 +S 3200,6100,3200,9100,400,140nymous_,UP,ALU1 +S 11000,10900,11000,14900,200,p18f,UP,PTRANS +S 36800,5880,36800,8720,600,182nymous_,UP,PTIE +S 17900,22000,18700,22000,400,336nymous_,RIGHT,ALU1 +S 1600,19300,1600,37500,400,299nymous_,UP,ALU1 +S 25100,37000,27900,37000,1600,fbul,RIGHT,ALU1 +S 25100,25200,27900,25200,400,fbul,RIGHT,ALU1 +S 11600,22500,11600,36700,200,n15b,UP,NTRANS +S 21200,8500,21200,9100,420,25onymous_,UP,NDIF +S 3200,5850,3200,15950,600,141nymous_,UP,ALU2 +S 36800,6100,36800,9100,400,183nymous_,UP,ALU1 +S 17900,23200,18700,23200,400,337nymous_,RIGHT,ALU1 +S 1600,19080,1600,37720,600,300nymous_,UP,PTIE +S 8000,7500,8000,9100,420,223nymous_,UP,NDIF +S 11600,6100,11600,8900,400,259nymous_,UP,ALU1 +S 21200,9100,21200,9900,400,26onymous_,UP,ALU1 +S 3050,6000,6950,6000,600,142nymous_,RIGHT,ALU2 +S 36800,7050,36800,17150,600,184nymous_,UP,ALU2 +S 29000,7300,29000,8300,200,n1,UP,NTRANS +S 16400,30050,16400,32150,600,301nymous_,UP,ALU2 +S 17900,24400,18700,24400,400,338nymous_,RIGHT,ALU1 +S 8000,8100,8000,8900,400,224nymous_,UP,ALU1 +S 11600,7500,11600,9100,420,260nymous_,UP,NDIF +S 18650,31600,25150,31600,600,cpd,RIGHT,ALU2 +S 18800,22050,18800,36550,600,cpd,UP,ALU2 +S 25100,32400,27900,32400,400,cpd,RIGHT,ALU1 +S 25100,30000,27900,30000,400,cpd,RIGHT,ALU1 +S 25100,27600,27900,27600,400,cpd,RIGHT,ALU1 +S 25000,27450,25000,32550,600,cpd,UP,ALU2 +S 21800,8300,21800,9300,200,n16d,UP,NTRANS +S 3050,10000,6150,10000,2400,143nymous_,RIGHT,ALU2 +S 36800,11100,36800,15900,400,185nymous_,UP,ALU1 +S 16400,6100,16400,8900,400,302nymous_,UP,ALU1 +S 17900,25600,18700,25600,400,339nymous_,RIGHT,ALU1 +S 22000,22050,22000,28350,600,27onymous_,UP,ALU2 +S 8000,11100,8000,13700,400,225nymous_,UP,ALU1 +S 11600,11100,11600,14700,620,261nymous_,UP,PDIF +S 29000,8600,29000,9000,200,104nymous_,UP,POLY +S 3200,11100,3200,15900,400,144nymous_,UP,ALU1 +S 19650,36800,26150,36800,600,node_cp,RIGHT,ALU2 +S 17900,35200,19700,35200,400,node_cp,RIGHT,ALU1 +S 17900,32800,19700,32800,400,node_cp,RIGHT,ALU1 +S 34600,20600,36200,20600,200,node_cp,RIGHT,POLY +S 31400,20600,33000,20600,200,node_cp,RIGHT,POLY +S 28600,24600,29000,24600,600,node_cp,RIGHT,POLY +S 27850,24600,29150,24600,600,node_cp,RIGHT,ALU2 +S 28000,24450,28000,31350,600,node_cp,UP,ALU2 +S 25100,33600,27900,33600,400,node_cp,RIGHT,ALU1 +S 25100,31200,27900,31200,400,node_cp,RIGHT,ALU1 +S 36800,10880,36800,16120,600,186nymous_,UP,NTIE +S 16400,7500,16400,9100,620,303nymous_,UP,NDIF +S 17900,26800,18700,26800,400,340nymous_,RIGHT,ALU1 +S 8000,11100,8000,14700,620,226nymous_,UP,PDIF +S 11600,11900,11600,15900,400,262nymous_,UP,ALU1 +S 29000,11400,29000,12200,200,105nymous_,UP,POLY +S 22000,18050,22000,19350,600,28onymous_,UP,ALU2 +S 3200,10880,3200,16120,600,145nymous_,UP,NTIE +S 37000,21100,37000,36500,620,187nymous_,UP,PDIF +S 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11600,9000,300,300,CONT_DIF_N,1162ymous_ +B 27000,21600,300,300,CONT_DIF_P,516nymous_ +B 25000,27600,300,300,CONT_DIF_P,462nymous_ +B 30600,26000,300,300,CONT_DIF_P,623nymous_ +B 3200,6000,300,300,CONT_BODY_P,677nymous_ +B 34800,22000,300,300,CONT_VIA2,785nymous_ +B 36800,10000,300,300,CONT_VIA2,839nymous_ +B 38000,33000,300,300,CONT_VIA2,893nymous_ +B 4400,35000,300,300,CONT_DIF_N,947nymous_ +B 6000,34000,300,300,CONT_DIF_N,1001ymous_ +B 1600,32400,300,300,CONT_BODY_P,1269ymous_ +B 14000,6000,300,300,CONT_VIA,1215ymous_ +B 7600,31000,300,300,CONT_VIA2,1055ymous_ +B 9200,35000,300,300,CONT_DIF_N,1109ymous_ +B 17800,28000,300,300,CONT_DIF_N,1323ymous_ +B 25000,27600,300,300,CONT_VIA,463nymous_ +B 23000,23400,300,300,CONT_BODY_N,409nymous_ +B 2800,29000,300,300,CONT_DIF_N,570nymous_ +B 30600,27000,300,300,CONT_DIF_P,624nymous_ +B 11600,11800,300,300,CONT_DIF_P,1163ymous_ +B 27000,22800,300,300,CONT_DIF_P,517nymous_ +B 3200,6000,300,300,CONT_VIA,678nymous_ +B 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36800,12000,300,300,CONT_BODY_N,841nymous_ +B 38000,35000,300,300,CONT_VIA2,895nymous_ +B 4400,36000,300,300,CONT_DIF_N,949nymous_ +B 14000,7200,300,300,CONT_DIF_N,1217ymous_ +B 6000,36000,300,300,CONT_DIF_N,1003ymous_ +B 7600,32000,300,300,CONT_VIA,1057ymous_ +B 17800,29200,300,300,CONT_DIF_N,1325ymous_ +B 1600,34400,300,300,CONT_BODY_P,1271ymous_ +B 23000,25400,300,300,CONT_BODY_N,411nymous_ +B 28200,9000,200,200,CONT_TURN1,357nymous_ +B 2800,31000,300,300,CONT_DIF_N,572nymous_ +B 9200,6000,300,300,CONT_BODY_P,1111ymous_ +B 11600,13800,300,300,CONT_DIF_P,1165ymous_ +B 27000,25200,300,300,CONT_DIF_P,519nymous_ +B 25000,30000,300,300,CONT_DIF_P,465nymous_ +B 30600,27000,300,300,CONT_VIA2,626nymous_ +B 3200,7000,300,300,CONT_BODY_P,680nymous_ +B 33800,23000,300,300,CONT_VIA2,734nymous_ +B 34800,28000,300,300,CONT_VIA2,788nymous_ +B 36800,13000,300,300,CONT_BODY_N,842nymous_ +B 38200,20400,300,300,CONT_BODY_N,896nymous_ +B 4400,36000,300,300,CONT_VIA,950nymous_ +B 1600,35400,300,300,CONT_BODY_P,1272ymous_ +B 14000,8000,300,300,CONT_DIF_N,1218ymous_ +B 6600,24000,300,300,CONT_VIA2,1004ymous_ +B 7600,32000,300,300,CONT_VIA2,1058ymous_ +B 17800,30400,300,300,CONT_DIF_N,1326ymous_ +B 23000,26400,300,300,CONT_BODY_N,412nymous_ +B 5000,19000,8300,2300,CONT_VIA2,358nymous_ +B 2800,32000,300,300,CONT_DIF_N,573nymous_ +B 9200,6000,300,300,CONT_VIA,1112ymous_ +B 11600,14800,300,300,CONT_DIF_P,1166ymous_ +B 27000,25200,300,300,CONT_VIA,520nymous_ +B 25000,30000,300,300,CONT_VIA,466nymous_ +B 30600,28000,300,300,CONT_DIF_P,627nymous_ +B 3200,7000,300,300,CONT_VIA2,681nymous_ +B 33800,24000,300,300,CONT_DIF_P,735nymous_ +B 34800,29000,300,300,CONT_VIA2,789nymous_ +B 36800,14000,300,300,CONT_BODY_N,843nymous_ +B 38200,21400,300,300,CONT_BODY_N,897nymous_ +B 4400,36000,300,300,CONT_VIA2,951nymous_ +B 6600,25000,300,300,CONT_VIA2,1005ymous_ +B 1600,36400,300,300,CONT_BODY_P,1273ymous_ +B 14000,10000,300,300,CONT_POLY,1219ymous_ +B 10400,11000,200,200,CONT_TURN1,359nymous_ +B 7600,33000,300,300,CONT_DIF_N,1059ymous_ +B 9200,6000,300,300,CONT_VIA2,1113ymous_ +B 17800,30400,300,300,CONT_VIA,1327ymous_ +B 25000,31200,300,300,CONT_DIF_P,467nymous_ +B 23000,27400,300,300,CONT_BODY_N,413nymous_ +B 2800,33000,300,300,CONT_DIF_N,574nymous_ +B 30600,28000,300,300,CONT_VIA,628nymous_ +B 11600,16000,300,300,CONT_BODY_N,1167ymous_ +B 27000,26400,300,300,CONT_DIF_P,521nymous_ +B 3200,8000,300,300,CONT_BODY_P,682nymous_ +B 33800,24000,300,300,CONT_VIA,736nymous_ +B 34800,33000,300,300,CONT_VIA2,790nymous_ +B 36800,15000,300,300,CONT_BODY_N,844nymous_ +B 38200,22400,300,300,CONT_BODY_N,898nymous_ +B 14000,12000,300,300,CONT_DIF_P,1220ymous_ +B 4400,6000,300,300,CONT_BODY_P,952nymous_ +B 6600,26000,300,300,CONT_VIA2,1006ymous_ +B 17800,30400,300,300,CONT_VIA2,1328ymous_ +B 1600,37600,300,300,CONT_BODY_P,1274ymous_ +B 17400,11000,200,200,CONT_TURN1,360nymous_ +B 7600,33000,300,300,CONT_VIA,1060ymous_ +B 9200,7000,300,300,CONT_VIA2,1114ymous_ +B 25000,32400,300,300,CONT_DIF_P,468nymous_ +B 23000,28400,300,300,CONT_BODY_N,414nymous_ +B 2800,34000,300,300,CONT_DIF_N,575nymous_ +B 30600,28000,300,300,CONT_VIA2,629nymous_ +B 33800,25000,300,300,CONT_DIF_P,737nymous_ +B 11600,17000,300,300,CONT_VIA,1168ymous_ +B 27000,27600,300,300,CONT_DIF_P,522nymous_ +B 3200,8000,300,300,CONT_VIA2,683nymous_ +B 34800,34000,300,300,CONT_VIA2,791nymous_ +B 36800,15000,300,300,CONT_VIA2,845nymous_ +B 38200,23400,300,300,CONT_BODY_N,899nymous_ +B 4400,6000,300,300,CONT_VIA,953nymous_ +B 14000,12800,300,300,CONT_DIF_P,1221ymous_ +B 6600,30000,300,300,CONT_VIA2,1007ymous_ +B 7600,34000,300,300,CONT_DIF_N,1061ymous_ +B 17800,31600,300,300,CONT_DIF_N,1329ymous_ +B 1600,19200,300,300,CONT_BODY_P,1275ymous_ +B 23000,29400,300,300,CONT_BODY_N,415nymous_ +B 17600,8000,200,200,CONT_TURN1,361nymous_ +B 2800,35000,300,300,CONT_DIF_N,576nymous_ +B 9200,7200,300,300,CONT_DIF_N,1115ymous_ +B 11600,17000,300,300,CONT_VIA2,1169ymous_ +B 27000,28800,300,300,CONT_DIF_P,523nymous_ +B 25000,32400,300,300,CONT_VIA,469nymous_ +B 30600,29000,300,300,CONT_DIF_P,630nymous_ +B 3200,9000,300,300,CONT_BODY_P,684nymous_ +B 33800,25000,300,300,CONT_VIA,738nymous_ +B 34800,35000,300,300,CONT_VIA2,792nymous_ +B 36800,16000,300,300,CONT_BODY_N,846nymous_ +B 38200,24400,300,300,CONT_BODY_N,900nymous_ +B 4400,6000,300,300,CONT_VIA2,954nymous_ +B 16400,6000,300,300,CONT_BODY_P,1276ymous_ +B 14000,16000,300,300,CONT_BODY_N,1222ymous_ +B 6600,31000,300,300,CONT_VIA2,1008ymous_ +B 7600,34000,300,300,CONT_VIA,1062ymous_ +B 17800,31600,300,300,CONT_VIA2,1330ymous_ +B 23000,30400,300,300,CONT_BODY_N,416nymous_ +B 17800,22000,200,200,CONT_TURN1,362nymous_ +B 2800,36000,300,300,CONT_DIF_N,577nymous_ +B 9200,8000,300,300,CONT_DIF_N,1116ymous_ +B 11600,19200,300,300,CONT_BODY_P,1170ymous_ +B 27000,30000,300,300,CONT_DIF_P,524nymous_ +B 25000,33600,300,300,CONT_DIF_P,470nymous_ +B 30600,29000,300,300,CONT_VIA,631nymous_ +B 3200,12000,300,300,CONT_BODY_N,685nymous_ +B 33800,26000,300,300,CONT_DIF_P,739nymous_ +B 35000,19200,300,300,CONT_BODY_N,793nymous_ +B 36800,16000,300,300,CONT_VIA2,847nymous_ +B 38200,25400,300,300,CONT_BODY_N,901nymous_ +B 4400,8000,300,300,CONT_DIF_N,955nymous_ +B 6600,32000,300,300,CONT_VIA2,1009ymous_ +B 16400,6000,300,300,CONT_VIA,1277ymous_ +B 14000,17000,300,300,CONT_VIA,1223ymous_ +B 18400,12800,200,200,CONT_TURN1,363nymous_ +B 7600,35000,300,300,CONT_DIF_N,1063ymous_ +B 9200,8000,300,300,CONT_VIA2,1117ymous_ +B 17800,32800,300,300,CONT_DIF_N,1331ymous_ +B 25000,35000,300,300,CONT_DIF_P,471nymous_ +B 23000,31400,300,300,CONT_BODY_N,417nymous_ +B 28200,10600,300,300,CONT_VIA,578nymous_ +B 30600,29000,300,300,CONT_VIA2,632nymous_ +B 12400,23000,300,300,CONT_DIF_N,1171ymous_ +B 27000,31200,300,300,CONT_DIF_P,525nymous_ +B 3200,12000,300,300,CONT_VIA2,686nymous_ +B 33800,26000,300,300,CONT_VIA,740nymous_ +B 35400,22000,300,300,CONT_DIF_P,794nymous_ +B 36800,17000,300,300,CONT_VIA,848nymous_ +B 38200,26400,300,300,CONT_BODY_N,902nymous_ +B 14000,17000,300,300,CONT_VIA2,1224ymous_ +B 4400,9000,300,300,CONT_DIF_N,956nymous_ +B 6600,36000,300,300,CONT_VIA2,1010ymous_ +B 17800,34000,300,300,CONT_DIF_N,1332ymous_ +B 16400,6000,300,300,CONT_VIA2,1278ymous_ +B 19800,32800,200,200,CONT_TURN1,364nymous_ +B 7600,35000,300,300,CONT_VIA,1064ymous_ +B 9200,10000,300,300,CONT_POLY,1118ymous_ +B 25000,36400,300,300,CONT_DIF_P,472nymous_ +B 23000,32400,300,300,CONT_BODY_N,418nymous_ +B 28200,11800,300,300,CONT_POLY,579nymous_ +B 30600,30000,300,300,CONT_DIF_P,633nymous_ +B 33800,27000,300,300,CONT_DIF_P,741nymous_ +B 12400,24000,300,300,CONT_DIF_N,1172ymous_ +B 27000,32400,300,300,CONT_DIF_P,526nymous_ +B 3200,13000,300,300,CONT_BODY_N,687nymous_ +B 35400,23000,300,300,CONT_DIF_P,795nymous_ +B 36800,17000,300,300,CONT_VIA2,849nymous_ +B 38200,27400,300,300,CONT_BODY_N,903nymous_ +B 4400,11800,300,300,CONT_DIF_P,957nymous_ +B 14600,19200,300,300,CONT_BODY_P,1225ymous_ +B 6600,19200,300,300,CONT_BODY_P,1011ymous_ +B 7600,36000,300,300,CONT_DIF_N,1065ymous_ +B 17800,35200,300,300,CONT_DIF_N,1333ymous_ +B 16400,8000,300,300,CONT_DIF_N,1279ymous_ +B 23000,33400,300,300,CONT_BODY_N,419nymous_ +B 20000,6000,300,300,CONT_BODY_P,365nymous_ +B 28400,6000,300,300,CONT_BODY_P,580nymous_ +B 9200,12000,300,300,CONT_DIF_P,1119ymous_ +B 12400,25000,300,300,CONT_DIF_N,1173ymous_ +B 27000,33600,300,300,CONT_DIF_P,527nymous_ +B 25000,37600,300,300,CONT_BODY_N,473nymous_ +B 30600,30000,300,300,CONT_VIA,634nymous_ +B 3200,13000,300,300,CONT_VIA2,688nymous_ +B 33800,27000,300,300,CONT_VIA,742nymous_ +B 35400,24000,300,300,CONT_DIF_P,796nymous_ +B 37000,22000,300,300,CONT_DIF_P,850nymous_ +B 38200,28400,300,300,CONT_BODY_N,904nymous_ +B 4400,12800,300,300,CONT_DIF_P,958nymous_ +B 16400,9000,300,300,CONT_DIF_N,1280ymous_ +B 15200,6000,300,300,CONT_BODY_P,1226ymous_ +B 6800,37600,300,300,CONT_BODY_P,1012ymous_ +B 7600,36000,300,300,CONT_VIA,1066ymous_ +B 17800,36400,300,300,CONT_DIF_N,1334ymous_ +B 23000,34400,300,300,CONT_BODY_N,420nymous_ +B 20000,6000,300,300,CONT_VIA,366nymous_ +B 28400,8000,300,300,CONT_DIF_N,581nymous_ +B 9200,12800,300,300,CONT_DIF_P,1120ymous_ +B 12400,26000,300,300,CONT_DIF_N,1174ymous_ +B 27000,35000,300,300,CONT_DIF_P,528nymous_ +B 25000,19200,300,300,CONT_BODY_N,474nymous_ +B 30600,31000,300,300,CONT_DIF_P,635nymous_ +B 3200,14000,300,300,CONT_BODY_N,689nymous_ +B 33800,27000,300,300,CONT_VIA2,743nymous_ +B 35400,25000,300,300,CONT_DIF_P,797nymous_ +B 37000,22000,300,300,CONT_VIA,851nymous_ +B 38200,29400,300,300,CONT_BODY_N,905nymous_ +B 4400,13800,300,300,CONT_DIF_P,959nymous_ +B 6800,37600,300,300,CONT_VIA,1013ymous_ +B 16400,10000,300,300,CONT_POLY,1281ymous_ +B 15200,6000,300,300,CONT_VIA,1227ymous_ +B 20000,6000,300,300,CONT_VIA2,367nymous_ +B 7600,36000,300,300,CONT_VIA2,1067ymous_ +B 9200,13800,300,300,CONT_DIF_P,1121ymous_ +B 17800,37600,300,300,CONT_BODY_P,1335ymous_ +B 26000,20400,300,300,CONT_DIF_P,475nymous_ +B 23000,35400,300,300,CONT_BODY_N,421nymous_ +B 28400,14000,300,300,CONT_DIF_P,582nymous_ +B 30600,31000,300,300,CONT_VIA,636nymous_ +B 27000,36400,300,300,CONT_DIF_P,529nymous_ +B 3200,14000,300,300,CONT_VIA2,690nymous_ +B 33800,28000,300,300,CONT_DIF_P,744nymous_ +B 35400,26000,300,300,CONT_DIF_P,798nymous_ +B 37000,22000,300,300,CONT_VIA2,852nymous_ +B 38200,30400,300,300,CONT_BODY_N,906nymous_ +B 15200,6000,300,300,CONT_VIA2,1228ymous_ +B 4400,14800,300,300,CONT_DIF_P,960nymous_ +B 6800,37600,300,300,CONT_VIA2,1014ymous_ +B 18600,19200,300,300,CONT_BODY_P,1336ymous_ +B 16400,12000,300,300,CONT_DIF_P,1282ymous_ +B 20000,8600,300,300,CONT_DIF_N,368nymous_ +B 7600,19200,300,300,CONT_BODY_P,1068ymous_ +B 9200,14800,300,300,CONT_DIF_P,1122ymous_ +B 12400,28000,300,300,CONT_DIF_N,1176ymous_ +B 26000,21600,300,300,CONT_DIF_P,476nymous_ +B 23000,36400,300,300,CONT_BODY_N,422nymous_ +B 28400,16000,300,300,CONT_BODY_N,583nymous_ +B 30600,32000,300,300,CONT_DIF_P,637nymous_ +B 33800,28000,300,300,CONT_VIA,745nymous_ +B 27000,36400,300,300,CONT_VIA,530nymous_ +B 3200,15000,300,300,CONT_BODY_N,691nymous_ +B 35400,27000,300,300,CONT_DIF_P,799nymous_ +B 37000,23000,300,300,CONT_DIF_P,853nymous_ +B 38200,31400,300,300,CONT_BODY_N,907nymous_ +B 4400,16000,300,300,CONT_BODY_N,961nymous_ +B 15200,8000,300,300,CONT_DIF_N,1229ymous_ +B 6800,6000,300,300,CONT_BODY_P,1015ymous_ +B 7800,37600,300,300,CONT_BODY_P,1069ymous_ +B 18800,22000,300,300,CONT_DIF_N,1337ymous_ +B 16400,12800,300,300,CONT_DIF_P,1283ymous_ +B 23000,37600,300,300,CONT_BODY_N,423nymous_ +B 20000,11000,300,300,CONT_POLY,369nymous_ +B 28400,17000,300,300,CONT_VIA,584nymous_ +B 9200,16000,300,300,CONT_BODY_N,1123ymous_ +B 12400,29000,300,300,CONT_DIF_N,1177ymous_ +B 27000,37600,300,300,CONT_BODY_N,531nymous_ +B 26000,21600,300,300,CONT_VIA,477nymous_ +B 30600,32000,300,300,CONT_VIA,638nymous_ +B 3200,16000,300,300,CONT_BODY_N,692nymous_ +B 33800,28000,300,300,CONT_VIA2,746nymous_ +B 35400,28000,300,300,CONT_DIF_P,800nymous_ +B 37000,23000,300,300,CONT_VIA,854nymous_ +B 38200,32400,300,300,CONT_BODY_N,908nymous_ +B 4400,17000,300,300,CONT_VIA,962nymous_ +B 16400,16000,300,300,CONT_BODY_N,1284ymous_ +B 15200,9000,300,300,CONT_DIF_N,1230ymous_ +B 6800,6000,300,300,CONT_VIA,1016ymous_ +B 7800,37600,300,300,CONT_VIA,1070ymous_ +B 18800,22200,300,300,CONT_VIA,1338ymous_ +B 23000,19200,300,300,CONT_BODY_N,424nymous_ +B 20000,16000,300,300,CONT_BODY_N,370nymous_ +B 28400,17000,300,300,CONT_VIA2,585nymous_ +B 9200,17000,300,300,CONT_VIA,1124ymous_ +B 12400,30000,300,300,CONT_DIF_N,1178ymous_ +B 27000,9000,300,300,CONT_VIA2,532nymous_ +B 26000,21600,300,300,CONT_VIA2,478nymous_ +B 30600,33000,300,300,CONT_DIF_P,639nymous_ +B 3200,17000,300,300,CONT_VIA,693nymous_ +B 33800,29000,300,300,CONT_DIF_P,747nymous_ +B 35400,29000,300,300,CONT_DIF_P,801nymous_ +B 37000,23000,300,300,CONT_VIA2,855nymous_ +B 38200,33400,300,300,CONT_BODY_N,909nymous_ +B 4400,17000,300,300,CONT_VIA2,963nymous_ +B 6800,6000,300,300,CONT_VIA2,1017ymous_ +B 16400,17000,300,300,CONT_VIA,1285ymous_ +B 15200,10000,300,300,CONT_POLY,1231ymous_ +B 20800,20400,300,300,CONT_BODY_P,371nymous_ +B 7800,37600,300,300,CONT_VIA2,1071ymous_ +B 9200,17000,300,300,CONT_VIA2,1125ymous_ +B 18800,23200,300,300,CONT_DIF_N,1339ymous_ +B 26000,22800,300,300,CONT_DIF_P,479nymous_ +B 23400,17000,300,300,CONT_VIA,425nymous_ +B 28800,9000,300,300,CONT_POLY,586nymous_ +B 30600,33000,300,300,CONT_VIA,640nymous_ +B 12400,31000,300,300,CONT_DIF_N,1179ymous_ +B 27000,10000,300,300,CONT_VIA2,533nymous_ +B 3200,17000,300,300,CONT_VIA2,694nymous_ +B 33800,29000,300,300,CONT_VIA,748nymous_ +B 35400,30000,300,300,CONT_DIF_P,802nymous_ +B 37000,24000,300,300,CONT_DIF_P,856nymous_ +B 38200,34400,300,300,CONT_BODY_N,910nymous_ +B 15200,11600,300,300,CONT_DIF_P,1232ymous_ +B 4600,37600,300,300,CONT_BODY_P,964nymous_ +B 6800,7200,300,300,CONT_DIF_N,1018ymous_ +B 18800,24400,300,300,CONT_DIF_N,1340ymous_ +B 16400,17000,300,300,CONT_VIA2,1286ymous_ +B 20800,21400,300,300,CONT_BODY_P,372nymous_ +B 8000,0,300,300,CONT_VIA2,1072ymous_ +B 9600,37600,300,300,CONT_BODY_P,1126ymous_ +B 26000,22800,300,300,CONT_VIA2,480nymous_ +B 23400,17000,300,300,CONT_VIA2,426nymous_ +B 29000,21000,300,300,CONT_POLY,587nymous_ +B 30600,33000,300,300,CONT_VIA2,641nymous_ +B 33800,29000,300,300,CONT_VIA2,749nymous_ +B 27000,11000,300,300,CONT_VIA2,534nymous_ +B 32200,22000,300,300,CONT_DIF_P,695nymous_ +B 35400,31000,300,300,CONT_DIF_P,803nymous_ +B 37000,24000,300,300,CONT_VIA,857nymous_ +B 38200,35400,300,300,CONT_BODY_N,911nymous_ +B 4600,37600,300,300,CONT_VIA,965nymous_ +B 15200,12600,300,300,CONT_DIF_P,1233ymous_ +B 6800,8000,300,300,CONT_DIF_N,1019ymous_ +B 8000,0,300,300,CONT_VIA3,1073ymous_ +B 18800,25600,300,300,CONT_DIF_N,1341ymous_ +B 16600,19200,300,300,CONT_BODY_P,1287ymous_ +B 23600,6000,300,300,CONT_BODY_P,427nymous_ +B 20800,22400,300,300,CONT_BODY_P,373nymous_ +B 29000,21000,300,300,CONT_VIA,588nymous_ +B 9600,19200,300,300,CONT_BODY_P,1127ymous_ +B 27000,19200,300,300,CONT_BODY_N,535nymous_ +B 26000,24000,300,300,CONT_DIF_P,481nymous_ +B 30600,34000,300,300,CONT_DIF_P,642nymous_ +B 32200,23000,300,300,CONT_DIF_P,696nymous_ +B 33800,30000,300,300,CONT_DIF_P,750nymous_ +B 35400,32000,300,300,CONT_DIF_P,804nymous_ +B 37000,25000,300,300,CONT_DIF_P,858nymous_ +B 38200,36400,300,300,CONT_BODY_N,912nymous_ +B 4600,37600,300,300,CONT_VIA2,966nymous_ +B 16800,20200,300,300,CONT_VIA,1288ymous_ +B 15200,16000,300,300,CONT_BODY_N,1234ymous_ +B 6800,10000,300,300,CONT_POLY,1020ymous_ +B 8000,0,300,300,CONT_VIA4,1074ymous_ +B 18800,26800,300,300,CONT_DIF_N,1342ymous_ +B 23600,6000,300,300,CONT_VIA,428nymous_ +B 20800,23400,300,300,CONT_BODY_P,374nymous_ +B 29000,22200,300,300,CONT_POLY,589nymous_ +B 10400,6000,300,300,CONT_BODY_P,1128ymous_ +B 27200,6000,300,300,CONT_BODY_P,536nymous_ +B 26000,24000,300,300,CONT_VIA,482nymous_ +B 30600,34000,300,300,CONT_VIA,643nymous_ +B 32200,24000,300,300,CONT_DIF_P,697nymous_ +B 33800,30000,300,300,CONT_VIA,751nymous_ +B 35400,33000,300,300,CONT_DIF_P,805nymous_ +B 37000,25000,300,300,CONT_VIA,859nymous_ +B 38200,37600,300,300,CONT_BODY_N,913nymous_ +B 4600,19200,300,300,CONT_BODY_P,967nymous_ +B 6800,12000,300,300,CONT_DIF_P,1021ymous_ +B 16800,23400,300,300,CONT_POLY,1289ymous_ +B 15200,17000,300,300,CONT_VIA,1235ymous_ +B 20800,24400,300,300,CONT_BODY_P,375nymous_ +B 8000,8000,300,300,CONT_DIF_N,1075ymous_ +B 10400,6000,300,300,CONT_VIA,1129ymous_ +B 18800,26800,300,300,CONT_VIA,1343ymous_ +B 26000,25200,300,300,CONT_DIF_P,483nymous_ +B 23600,6000,300,300,CONT_VIA2,429nymous_ +B 29000,22200,300,300,CONT_VIA,590nymous_ +B 30600,34000,300,300,CONT_VIA2,644nymous_ +B 27200,8000,300,300,CONT_DIF_N,537nymous_ +B 32200,25000,300,300,CONT_DIF_P,698nymous_ +B 33800,31000,300,300,CONT_DIF_P,752nymous_ +B 35400,34000,300,300,CONT_DIF_P,806nymous_ +B 37000,26000,300,300,CONT_DIF_P,860nymous_ +B 38200,19200,300,300,CONT_BODY_N,914nymous_ +B 15200,17000,300,300,CONT_VIA2,1236ymous_ +B 12400,34000,300,300,CONT_DIF_N,1182ymous_ +B 5400,24000,300,300,CONT_VIA2,968nymous_ +B 6800,12800,300,300,CONT_DIF_P,1022ymous_ +B 18800,28000,300,300,CONT_DIF_N,1344ymous_ +B 16800,24400,300,300,CONT_VIA,1290ymous_ +B 20800,25400,300,300,CONT_BODY_P,376nymous_ +B 8000,9000,300,300,CONT_DIF_N,1076ymous_ +B 10400,6000,300,300,CONT_VIA2,1130ymous_ +B 26000,26400,300,300,CONT_DIF_P,484nymous_ +B 23600,8000,300,300,CONT_DIF_N,430nymous_ +B 29000,23400,300,300,CONT_POLY,591nymous_ +B 30600,35000,300,300,CONT_DIF_P,645nymous_ +B 33800,31000,300,300,CONT_VIA,753nymous_ +B 27200,10600,300,300,CONT_POLY,538nymous_ +B 32200,26000,300,300,CONT_DIF_P,699nymous_ +B 35400,35000,300,300,CONT_DIF_P,807nymous_ +B 37000,26000,300,300,CONT_VIA,861nymous_ +B 4400,21800,300,300,CONT_POLY,915nymous_ +B 5400,25000,300,300,CONT_VIA2,969nymous_ +B 15600,20200,300,300,CONT_VIA,1237ymous_ +B 12400,35000,300,300,CONT_DIF_N,1183ymous_ +B 6800,13800,300,300,CONT_DIF_P,1023ymous_ +B 8000,9000,300,300,CONT_VIA,1077ymous_ +B 18800,29200,300,300,CONT_DIF_N,1345ymous_ +B 16800,25400,300,300,CONT_POLY,1291ymous_ +B 23600,13000,300,300,CONT_DIF_P,431nymous_ +B 20800,26400,300,300,CONT_BODY_P,377nymous_ +B 29000,23400,300,300,CONT_VIA,592nymous_ +B 10400,8000,300,300,CONT_DIF_N,1131ymous_ +B 27200,13000,300,300,CONT_DIF_P,539nymous_ +B 26000,26400,300,300,CONT_VIA,485nymous_ +B 30600,35000,300,300,CONT_VIA,646nymous_ +B 32200,27000,300,300,CONT_DIF_P,700nymous_ +B 33800,32000,300,300,CONT_DIF_P,754nymous_ +B 35400,36000,300,300,CONT_DIF_P,808nymous_ +B 37000,27000,300,300,CONT_DIF_P,862nymous_ +B 12400,36000,300,300,CONT_DIF_N,1184ymous_ +B 4400,21800,300,300,CONT_VIA,916nymous_ +B 5400,26000,300,300,CONT_VIA2,970nymous_ +B 16800,28200,300,300,CONT_POLY,1292ymous_ +B 15600,23000,300,300,CONT_DIF_N,1238ymous_ +B 6800,14800,300,300,CONT_DIF_P,1024ymous_ +B 8000,10000,300,300,CONT_POLY,1078ymous_ +B 18800,30400,300,300,CONT_DIF_N,1346ymous_ +B 23600,14000,300,300,CONT_DIF_P,432nymous_ +B 20800,27400,300,300,CONT_BODY_P,378nymous_ +B 29000,24600,300,300,CONT_POLY,593nymous_ +B 10400,9000,300,300,CONT_DIF_N,1132ymous_ +B 12400,32000,300,300,CONT_DIF_N,1180ymous_ +B 26000,27600,300,300,CONT_DIF_P,486nymous_ +B 30600,35000,300,300,CONT_VIA2,647nymous_ +B 32200,28000,300,300,CONT_DIF_P,701nymous_ +B 33800,32000,300,300,CONT_VIA,755nymous_ +B 35600,6000,300,300,CONT_BODY_P,809nymous_ +B 37000,27000,300,300,CONT_VIA,863nymous_ +B 4400,23000,300,300,CONT_DIF_N,917nymous_ +B 12600,19200,300,300,CONT_BODY_P,1185ymous_ +B 5400,30000,300,300,CONT_VIA2,971nymous_ +B 6800,16000,300,300,CONT_BODY_N,1025ymous_ +B 16800,29200,300,300,CONT_VIA,1293ymous_ +B 15600,24000,300,300,CONT_DIF_N,1239ymous_ +B 20800,28400,300,300,CONT_BODY_P,379nymous_ +B 8000,11000,300,300,CONT_VIA,1079ymous_ +B 10400,10000,300,300,CONT_POLY,1133ymous_ +B 18800,31600,300,300,CONT_DIF_N,1347ymous_ +B 26000,27600,300,300,CONT_VIA2,487nymous_ +B 23600,16000,300,300,CONT_BODY_N,433nymous_ +B 29000,24600,300,300,CONT_VIA,594nymous_ +B 30800,6000,300,300,CONT_BODY_P,648nymous_ +B 12400,33000,300,300,CONT_DIF_N,1181ymous_ +B 32200,29000,300,300,CONT_DIF_P,702nymous_ +B 33800,33000,300,300,CONT_DIF_P,756nymous_ +B 35600,6000,300,300,CONT_VIA,810nymous_ +B 37000,27000,300,300,CONT_VIA2,864nymous_ +B 4400,23000,300,300,CONT_VIA,918nymous_ +B 15600,25000,300,300,CONT_DIF_N,1240ymous_ +B 12800,6000,300,300,CONT_BODY_P,1186ymous_ +B 5400,31000,300,300,CONT_VIA2,972nymous_ +B 6800,17000,300,300,CONT_VIA,1026ymous_ +B 18800,31600,300,300,CONT_VIA,1348ymous_ +B 16800,32200,300,300,CONT_POLY,1294ymous_ +B 20800,29400,300,300,CONT_BODY_P,380nymous_ +B 8000,11800,300,300,CONT_DIF_P,1080ymous_ +B 10400,11800,300,300,CONT_DIF_P,1134ymous_ +B 26000,28800,300,300,CONT_DIF_P,488nymous_ +B 24000,27000,300,300,CONT_POLY,434nymous_ +B 29000,25800,300,300,CONT_POLY,595nymous_ +B 30800,8000,300,300,CONT_DIF_N,649nymous_ +B 33800,33000,300,300,CONT_VIA,757nymous_ +B 32200,30000,300,300,CONT_DIF_P,703nymous_ +B 35600,6000,300,300,CONT_VIA2,811nymous_ +B 37000,28000,300,300,CONT_DIF_P,865nymous_ +B 4400,24000,300,300,CONT_DIF_N,919nymous_ +B 5400,32000,300,300,CONT_VIA2,973nymous_ +B 15600,26000,300,300,CONT_DIF_N,1241ymous_ +B 12800,6000,300,300,CONT_VIA,1187ymous_ +B 6800,17000,300,300,CONT_VIA2,1027ymous_ +B 8000,12800,300,300,CONT_DIF_P,1081ymous_ +B 18800,32800,300,300,CONT_DIF_N,1349ymous_ +B 16800,32200,300,300,CONT_VIA,1295ymous_ +B 24000,28200,300,300,CONT_POLY,435nymous_ +B 20800,30400,300,300,CONT_BODY_P,381nymous_ +B 27200,17000,300,300,CONT_VIA,542nymous_ +B 29000,30600,300,300,CONT_POLY,596nymous_ +B 10400,12800,300,300,CONT_DIF_P,1135ymous_ +B 26000,28800,300,300,CONT_VIA,489nymous_ +B 30800,10600,300,300,CONT_POLY,650nymous_ +B 32200,31000,300,300,CONT_DIF_P,704nymous_ +B 33800,33000,300,300,CONT_VIA2,758nymous_ +B 35600,8000,300,300,CONT_DIF_N,812nymous_ +B 37000,28000,300,300,CONT_VIA,866nymous_ +B 12800,6000,300,300,CONT_VIA2,1188ymous_ +B 4400,24000,300,300,CONT_VIA,920nymous_ +B 5400,36000,300,300,CONT_VIA2,974nymous_ +B 16800,33400,300,300,CONT_POLY,1296ymous_ +B 15600,27000,300,300,CONT_DIF_N,1242ymous_ +B 7000,9000,300,300,CONT_VIA2,1028ymous_ +B 8000,13800,300,300,CONT_DIF_P,1082ymous_ +B 18800,34000,300,300,CONT_DIF_N,1350ymous_ +B 24000,28200,300,300,CONT_VIA,436nymous_ +B 20800,31400,300,300,CONT_BODY_P,382nymous_ +B 27200,17000,300,300,CONT_VIA2,543nymous_ +B 29000,31800,300,300,CONT_POLY,597nymous_ +B 10400,13800,300,300,CONT_DIF_P,1136ymous_ +B 26000,28800,300,300,CONT_VIA2,490nymous_ +B 30800,13000,300,300,CONT_DIF_P,651nymous_ +B 32200,32000,300,300,CONT_DIF_P,705nymous_ +B 33800,34000,300,300,CONT_DIF_P,759nymous_ +B 35600,13000,300,300,CONT_DIF_P,813nymous_ +B 37000,28000,300,300,CONT_VIA2,867nymous_ +B 4400,24000,300,300,CONT_VIA2,921nymous_ +B 12800,8000,300,300,CONT_DIF_N,1189ymous_ +B 5600,37600,300,300,CONT_BODY_P,975nymous_ +B 7000,10000,300,300,CONT_VIA2,1029ymous_ +B 16800,33400,300,300,CONT_VIA,1297ymous_ +B 15600,28000,300,300,CONT_DIF_N,1243ymous_ +B 20800,32400,300,300,CONT_BODY_P,383nymous_ +B 27800,36400,300,300,CONT_DIF_P,544nymous_ +B 8000,16000,300,300,CONT_BODY_N,1083ymous_ +B 10400,16000,300,300,CONT_BODY_N,1137ymous_ +B 18800,34000,300,300,CONT_VIA,1351ymous_ +B 26000,30000,300,300,CONT_DIF_P,491nymous_ +B 24000,29200,300,300,CONT_POLY,437nymous_ +B 29000,33000,300,300,CONT_POLY,598nymous_ +B 30800,14000,300,300,CONT_DIF_P,652nymous_ +B 32200,33000,300,300,CONT_DIF_P,706nymous_ +B 33800,34000,300,300,CONT_VIA,760nymous_ +B 35600,14000,300,300,CONT_DIF_P,814nymous_ +B 37000,29000,300,300,CONT_DIF_P,868nymous_ +B 4400,25000,300,300,CONT_DIF_N,922nymous_ +B 15600,29000,300,300,CONT_DIF_N,1244ymous_ +B 12800,9000,300,300,CONT_DIF_N,1190ymous_ +B 5600,37600,300,300,CONT_VIA,976nymous_ +B 7000,11000,300,300,CONT_VIA2,1030ymous_ +B 18800,35200,300,300,CONT_DIF_N,1352ymous_ +B 16800,33400,300,300,CONT_VIA2,1298ymous_ +B 20800,33400,300,300,CONT_BODY_P,384nymous_ +B 27800,37600,300,300,CONT_BODY_N,545nymous_ +B 8000,17000,300,300,CONT_VIA,1084ymous_ +B 10400,17000,300,300,CONT_VIA,1138ymous_ +B 26000,31200,300,300,CONT_DIF_P,492nymous_ +B 24000,34200,300,300,CONT_POLY,438nymous_ +B 29000,19200,300,300,CONT_BODY_N,599nymous_ +B 30800,16000,300,300,CONT_BODY_N,653nymous_ +B 33800,34000,300,300,CONT_VIA2,761nymous_ +B 32200,34000,300,300,CONT_DIF_P,707nymous_ +B 35600,16000,300,300,CONT_BODY_N,815nymous_ +B 37000,29000,300,300,CONT_VIA,869nymous_ +B 4400,25000,300,300,CONT_VIA,923nymous_ +B 5600,37600,300,300,CONT_VIA2,977nymous_ +B 15600,30000,300,300,CONT_DIF_N,1245ymous_ +B 12800,11600,300,300,CONT_DIF_P,1191ymous_ +B 7600,21800,300,300,CONT_POLY,1031ymous_ +B 8000,17000,300,300,CONT_VIA2,1085ymous_ +B 18800,36400,300,300,CONT_DIF_N,1353ymous_ +B 16800,34600,300,300,CONT_POLY,1299ymous_ +B 24000,34200,300,300,CONT_VIA,439nymous_ +B 20800,34400,300,300,CONT_BODY_P,385nymous_ +B 28000,0,300,300,CONT_VIA2,546nymous_ +B 29600,33000,300,300,CONT_VIA2,600nymous_ +B 10400,17000,300,300,CONT_VIA2,1139ymous_ +B 26000,31200,300,300,CONT_VIA,493nymous_ +B 30800,17000,300,300,CONT_VIA,654nymous_ +B 32200,35000,300,300,CONT_DIF_P,708nymous_ +B 33800,35000,300,300,CONT_DIF_P,762nymous_ +B 35600,17000,300,300,CONT_VIA,816nymous_ +B 37000,29000,300,300,CONT_VIA2,870nymous_ +B 12800,12600,300,300,CONT_DIF_P,1192ymous_ +B 4400,25000,300,300,CONT_VIA2,924nymous_ +B 5600,6000,300,300,CONT_BODY_P,978nymous_ +B 16800,34600,300,300,CONT_VIA,1300ymous_ +B 15600,31000,300,300,CONT_DIF_N,1246ymous_ +B 7600,21800,300,300,CONT_VIA,1032ymous_ +B 8600,24000,300,300,CONT_VIA2,1086ymous_ +B 18800,36400,300,300,CONT_VIA,1354ymous_ +B 24000,34200,300,300,CONT_VIA2,440nymous_ +B 20800,35400,300,300,CONT_BODY_P,386nymous_ +B 28000,0,300,300,CONT_VIA3,547nymous_ +B 29600,34000,300,300,CONT_VIA2,601nymous_ +B 10600,19200,300,300,CONT_BODY_P,1140ymous_ +B 26000,32400,300,300,CONT_DIF_P,494nymous_ +B 30800,17000,300,300,CONT_VIA2,655nymous_ +B 32200,36000,300,300,CONT_DIF_P,709nymous_ +B 33800,35000,300,300,CONT_VIA,763nymous_ +B 35600,17000,300,300,CONT_VIA2,817nymous_ +B 37000,30000,300,300,CONT_DIF_P,871nymous_ +B 4400,26000,300,300,CONT_DIF_N,925nymous_ +B 12800,16000,300,300,CONT_BODY_N,1193ymous_ +B 5600,6000,300,300,CONT_VIA,979nymous_ +B 7600,23000,300,300,CONT_DIF_N,1033ymous_ +B 16800,34600,300,300,CONT_VIA2,1301ymous_ +B 15600,32000,300,300,CONT_DIF_N,1247ymous_ +B 20800,36400,300,300,CONT_BODY_P,387nymous_ +B 28000,0,300,300,CONT_VIA4,548nymous_ +B 8600,25000,300,300,CONT_VIA2,1087ymous_ +B 10800,21800,300,300,CONT_POLY,1141ymous_ +B 18800,37600,300,300,CONT_BODY_P,1355ymous_ +B 26000,33600,300,300,CONT_DIF_P,495nymous_ +B 24000,35800,300,300,CONT_POLY,441nymous_ +B 29600,35000,300,300,CONT_VIA2,602nymous_ +B 31000,19200,300,300,CONT_BODY_N,656nymous_ +B 32800,20200,300,300,CONT_POLY,710nymous_ +B 33800,35000,300,300,CONT_VIA2,764nymous_ +B 36000,20200,300,300,CONT_POLY,818nymous_ +B 37000,30000,300,300,CONT_VIA,872nymous_ +B 4400,26000,300,300,CONT_VIA,926nymous_ +B 15600,33000,300,300,CONT_DIF_N,1248ymous_ +B 12800,17000,300,300,CONT_VIA,1194ymous_ +B 5600,6000,300,300,CONT_VIA2,980nymous_ +B 7600,23000,300,300,CONT_VIA,1034ymous_ +B 18800,6000,300,300,CONT_BODY_P,1356ymous_ +B 16800,35800,300,300,CONT_POLY,1302ymous_ +B 20800,37600,300,300,CONT_BODY_P,388nymous_ +B 28000,20400,300,300,CONT_DIF_P,549nymous_ +B 8600,26000,300,300,CONT_VIA2,1088ymous_ +B 10800,21800,300,300,CONT_VIA,1142ymous_ +B 26000,33600,300,300,CONT_VIA,496nymous_ +B 24000,35800,300,300,CONT_VIA,442nymous_ +B 29600,7000,300,300,CONT_DIF_N,603nymous_ +B 31600,20200,300,300,CONT_POLY,657nymous_ +B 33800,36000,300,300,CONT_DIF_P,765nymous_ +B 32800,22000,300,300,CONT_VIA2,711nymous_ +B 36000,22000,300,300,CONT_VIA2,819nymous_ +B 37000,31000,300,300,CONT_DIF_P,873nymous_ +B 4400,26000,300,300,CONT_VIA2,927nymous_ +B 5600,8000,300,300,CONT_DIF_N,981nymous_ +B 15600,34000,300,300,CONT_DIF_N,1249ymous_ +B 12800,17000,300,300,CONT_VIA2,1195ymous_ +B 7600,24000,300,300,CONT_DIF_N,1035ymous_ +B 8600,30000,300,300,CONT_VIA2,1089ymous_ +B 18800,6000,300,300,CONT_VIA,1357ymous_ +B 16800,35800,300,300,CONT_VIA,1303ymous_ +B 24000,37600,300,300,CONT_BODY_N,443nymous_ +B 20800,19200,300,300,CONT_BODY_P,389nymous_ +B 28000,21600,300,300,CONT_DIF_P,550nymous_ +B 29600,10600,300,300,CONT_POLY,604nymous_ +B 10800,21800,300,300,CONT_VIA2,1143ymous_ +B 26000,35000,300,300,CONT_DIF_P,497nymous_ +B 31600,22000,300,300,CONT_VIA2,658nymous_ +B 32800,23000,300,300,CONT_VIA2,712nymous_ +B 33800,36000,300,300,CONT_VIA,766nymous_ +B 36000,23000,300,300,CONT_VIA2,820nymous_ +B 37000,31000,300,300,CONT_VIA,874nymous_ +B 13600,19200,300,300,CONT_BODY_P,1196ymous_ +B 4400,27000,300,300,CONT_DIF_N,928nymous_ +B 5600,9000,300,300,CONT_DIF_N,982nymous_ +B 16800,37600,300,300,CONT_BODY_P,1304ymous_ +B 15600,35000,300,300,CONT_DIF_N,1250ymous_ +B 7600,24000,300,300,CONT_VIA,1036ymous_ +B 8600,31000,300,300,CONT_VIA2,1090ymous_ +B 18800,6000,300,300,CONT_VIA2,1358ymous_ +B 24000,19200,300,300,CONT_BODY_N,444nymous_ +B 21000,13000,300,300,CONT_VIA,390nymous_ +B 28000,22800,300,300,CONT_DIF_P,551nymous_ +B 29600,10600,300,300,CONT_VIA,605nymous_ +B 10800,23000,300,300,CONT_DIF_N,1144ymous_ +B 26000,36400,300,300,CONT_DIF_P,498nymous_ +B 31600,23000,300,300,CONT_VIA2,659nymous_ +B 32800,27000,300,300,CONT_VIA2,713nymous_ +B 34000,19200,300,300,CONT_BODY_N,767nymous_ +B 36000,27000,300,300,CONT_VIA2,821nymous_ +B 37000,32000,300,300,CONT_DIF_P,875nymous_ +B 4400,27000,300,300,CONT_VIA,929nymous_ +B 14000,21800,300,300,CONT_POLY,1197ymous_ +B 5600,11800,300,300,CONT_DIF_P,983nymous_ +B 7600,24000,300,300,CONT_VIA2,1037ymous_ +B 17400,11800,300,300,CONT_POLY,1305ymous_ +B 15600,36000,300,300,CONT_DIF_N,1251ymous_ +B 21000,14000,300,300,CONT_VIA,391nymous_ +B 28000,24000,300,300,CONT_DIF_P,552nymous_ +B 8600,32000,300,300,CONT_VIA2,1091ymous_ +B 10800,24000,300,300,CONT_DIF_N,1145ymous_ +B 18800,9000,300,300,CONT_DIF_N,1359ymous_ +B 26000,37600,300,300,CONT_BODY_N,499nymous_ +B 24800,6000,300,300,CONT_BODY_P,445nymous_ +B 29600,13000,300,300,CONT_DIF_P,606nymous_ +B 31600,27000,300,300,CONT_VIA2,660nymous_ +B 32800,28000,300,300,CONT_VIA2,714nymous_ +B 3400,24000,300,300,CONT_VIA2,768nymous_ +B 36000,28000,300,300,CONT_VIA2,822nymous_ +B 37000,32000,300,300,CONT_VIA,876nymous_ +B 4400,28000,300,300,CONT_DIF_N,930nymous_ +B 15600,19200,300,300,CONT_BODY_P,1252ymous_ +B 14000,21800,300,300,CONT_VIA,1198ymous_ +B 5600,12800,300,300,CONT_DIF_P,984nymous_ +B 7600,25000,300,300,CONT_DIF_N,1038ymous_ +B 18800,16000,300,300,CONT_BODY_N,1360ymous_ +B 17600,6000,300,300,CONT_BODY_P,1306ymous_ +B 21200,6000,300,300,CONT_BODY_P,392nymous_ +B 28000,25200,300,300,CONT_DIF_P,553nymous_ +B 8600,36000,300,300,CONT_VIA2,1092ymous_ +B 10800,25000,300,300,CONT_DIF_N,1146ymous_ +B 26000,6000,300,300,CONT_BODY_P,500nymous_ +B 24800,6000,300,300,CONT_VIA,446nymous_ +B 29600,14000,300,300,CONT_DIF_P,607nymous_ +B 31600,28000,300,300,CONT_VIA2,661nymous_ +B 3400,25000,300,300,CONT_VIA2,769nymous_ +B 32800,29000,300,300,CONT_VIA2,715nymous_ +B 36000,29000,300,300,CONT_VIA2,823nymous_ +B 37000,33000,300,300,CONT_DIF_P,877nymous_ +B 4400,28000,300,300,CONT_VIA,931nymous_ +B 5600,13800,300,300,CONT_DIF_P,985nymous_ +B 15800,27000,300,300,CONT_VIA2,1253ymous_ +B 14000,21800,300,300,CONT_VIA2,1199ymous_ +B 7600,25000,300,300,CONT_VIA,1039ymous_ +B 8600,19200,300,300,CONT_BODY_P,1093ymous_ +B 18800,17000,300,300,CONT_VIA,1361ymous_ +B 17600,6000,300,300,CONT_VIA,1307ymous_ +B 24800,6000,300,300,CONT_VIA2,447nymous_ +B 21200,6000,300,300,CONT_VIA,393nymous_ +B 28000,26400,300,300,CONT_DIF_P,554nymous_ +B 29600,16000,300,300,CONT_BODY_N,608nymous_ +B 10800,26000,300,300,CONT_DIF_N,1147ymous_ +B 26000,6000,300,300,CONT_VIA,501nymous_ +B 31600,29000,300,300,CONT_VIA2,662nymous_ +B 32800,33000,300,300,CONT_VIA2,716nymous_ +B 3400,26000,300,300,CONT_VIA2,770nymous_ +B 36000,33000,300,300,CONT_VIA2,824nymous_ +B 37000,33000,300,300,CONT_VIA,878nymous_ +B 14000,23000,300,300,CONT_DIF_N,1200ymous_ +B 4400,29000,300,300,CONT_DIF_N,932nymous_ +B 5600,16000,300,300,CONT_BODY_N,986nymous_ +B 17600,6000,300,300,CONT_VIA2,1308ymous_ +B 15800,28000,300,300,CONT_VIA2,1254ymous_ +B 7600,25000,300,300,CONT_VIA2,1040ymous_ +B 8800,37600,300,300,CONT_BODY_P,1094ymous_ +B 18800,17000,300,300,CONT_VIA2,1362ymous_ +B 24800,8000,300,300,CONT_DIF_N,448nymous_ +B 21200,6000,300,300,CONT_VIA2,394nymous_ +B 28000,27600,300,300,CONT_DIF_P,555nymous_ +B 29600,17000,300,300,CONT_VIA,609nymous_ +B 10800,27000,300,300,CONT_DIF_N,1148ymous_ +B 26000,6000,300,300,CONT_VIA2,502nymous_ +B 31600,33000,300,300,CONT_VIA2,663nymous_ +B 32800,34000,300,300,CONT_VIA2,717nymous_ +B 3400,30000,300,300,CONT_VIA2,771nymous_ +B 36000,34000,300,300,CONT_VIA2,825nymous_ +B 37000,33000,300,300,CONT_VIA2,879nymous_ +B 4400,29000,300,300,CONT_VIA,933nymous_ +B 14000,24000,300,300,CONT_DIF_N,1201ymous_ +B 5600,17000,300,300,CONT_VIA,987nymous_ +B 7600,26000,300,300,CONT_DIF_N,1041ymous_ +B 17600,8600,300,300,CONT_DIF_N,1309ymous_ +B 15800,29000,300,300,CONT_VIA2,1255ymous_ +B 21200,9000,300,300,CONT_DIF_N,395nymous_ +B 28000,28800,300,300,CONT_DIF_P,556nymous_ +B 8800,37600,300,300,CONT_VIA,1095ymous_ +B 10800,28000,300,300,CONT_DIF_N,1149ymous_ +B 19600,19200,300,300,CONT_BODY_P,1363ymous_ +B 26000,8000,300,300,CONT_DIF_N,503nymous_ +B 24800,13000,300,300,CONT_DIF_P,449nymous_ +B 29600,17000,300,300,CONT_VIA2,610nymous_ +B 31600,34000,300,300,CONT_VIA2,664nymous_ +B 32800,35000,300,300,CONT_VIA2,718nymous_ +B 3400,31000,300,300,CONT_VIA2,772nymous_ +B 36000,35000,300,300,CONT_VIA2,826nymous_ +B 37000,34000,300,300,CONT_DIF_P,880nymous_ +B 4400,30000,300,300,CONT_DIF_N,934nymous_ +B 15800,37600,300,300,CONT_BODY_P,1256ymous_ +B 14000,25000,300,300,CONT_DIF_N,1202ymous_ +B 5600,17000,300,300,CONT_VIA2,988nymous_ +B 7600,26000,300,300,CONT_VIA,1042ymous_ +B 19800,22600,300,300,CONT_POLY,1364ymous_ +B 17600,12800,300,300,CONT_DIF_P,1310ymous_ +B 21200,16000,300,300,CONT_BODY_N,396nymous_ +B 28000,30000,300,300,CONT_DIF_P,557nymous_ +B 8800,37600,300,300,CONT_VIA2,1096ymous_ +B 10800,29000,300,300,CONT_DIF_N,1150ymous_ +B 26000,12000,300,300,CONT_VIA2,504nymous_ +B 24800,13000,300,300,CONT_VIA,450nymous_ +B 3600,37600,300,300,CONT_BODY_P,828nymous_ +B 3400,36000,300,300,CONT_VIA2,774nymous_ +B 33200,6000,300,300,CONT_BODY_P,720nymous_ +B 31800,9000,300,300,CONT_POLY,666nymous_ +B 26000,13000,300,300,CONT_DIF_P,505nymous_ +B 10800,30000,300,300,CONT_DIF_N,1151ymous_ +B 30000,0,300,300,CONT_VIA3,612nymous_ +B 28000,31200,300,300,CONT_DIF_P,558nymous_ +B 9200,24000,300,300,CONT_DIF_N,1098ymous_ +B 7600,27000,300,300,CONT_DIF_N,1044ymous_ +B 1600,21400,300,300,CONT_BODY_P,1258ymous_ +B 17600,17000,300,300,CONT_VIA,1312ymous_ +B 6000,23000,300,300,CONT_DIF_N,990nymous_ +B 4400,30000,300,300,CONT_VIA2,936nymous_ +B 14000,27000,300,300,CONT_DIF_N,1204ymous_ +B 37000,34000,300,300,CONT_VIA2,882nymous_ +B 30000,0,300,300,CONT_VIA2,611nymous_ +B 31600,35000,300,300,CONT_VIA2,665nymous_ +B 3400,32000,300,300,CONT_VIA2,773nymous_ +B 33000,19200,300,300,CONT_BODY_N,719nymous_ +B 36000,19200,300,300,CONT_BODY_N,827nymous_ +B 37000,34000,300,300,CONT_VIA,881nymous_ +B 4400,30000,300,300,CONT_VIA,935nymous_ +B 5600,19200,300,300,CONT_BODY_P,989nymous_ +B 1600,20400,300,300,CONT_BODY_P,1257ymous_ +B 14000,26000,300,300,CONT_DIF_N,1203ymous_ +B 7600,26000,300,300,CONT_VIA2,1043ymous_ +B 9200,23000,300,300,CONT_DIF_N,1097ymous_ +B 19800,26200,300,300,CONT_POLY,1365ymous_ +B 17600,16000,300,300,CONT_BODY_N,1311ymous_ +B 24800,14000,300,300,CONT_DIF_P,451nymous_ +B 22000,22200,300,300,CONT_VIA,397nymous_ +B 19800,27400,300,300,CONT_POLY,1366ymous_ +B 24800,14000,300,300,CONT_VIA,452nymous_ +B 22000,19200,300,300,CONT_VIA,398nymous_ +B 28000,31200,300,300,CONT_VIA,559nymous_ +B 30000,0,300,300,CONT_VIA4,613nymous_ +B 10800,31000,300,300,CONT_DIF_N,1152ymous_ +B 26000,13000,300,300,CONT_VIA2,506nymous_ +B 31800,12200,300,300,CONT_POLY,667nymous_ +B 33200,6000,300,300,CONT_VIA,721nymous_ +B 34400,6000,300,300,CONT_BODY_P,775nymous_ +B 3600,37600,300,300,CONT_VIA,829nymous_ +B 37000,35000,300,300,CONT_DIF_P,883nymous_ +B 4400,31000,300,300,CONT_DIF_N,937nymous_ +B 14000,28000,300,300,CONT_DIF_N,1205ymous_ +B 6000,24000,300,300,CONT_DIF_N,991nymous_ +B 7600,27000,300,300,CONT_VIA,1045ymous_ +B 17600,17000,300,300,CONT_VIA2,1313ymous_ +B 1600,22400,300,300,CONT_BODY_P,1259ymous_ +B 22400,6000,300,300,CONT_BODY_P,399nymous_ +B 28000,32400,300,300,CONT_DIF_P,560nymous_ +B 9200,25000,300,300,CONT_DIF_N,1099ymous_ +B 10800,32000,300,300,CONT_DIF_N,1153ymous_ +B 19800,28200,300,300,CONT_VIA,1367ymous_ +B 26000,14000,300,300,CONT_DIF_P,507nymous_ +B 24800,16000,300,300,CONT_BODY_N,453nymous_ +B 30000,20200,300,300,CONT_VIA,614nymous_ +B 32000,6000,300,300,CONT_BODY_P,668nymous_ +B 33200,6000,300,300,CONT_VIA2,722nymous_ +B 34400,6000,300,300,CONT_VIA,776nymous_ +B 3600,37600,300,300,CONT_VIA2,830nymous_ +B 37000,35000,300,300,CONT_VIA,884nymous_ +B 4400,31000,300,300,CONT_VIA,938nymous_ +B 1600,23400,300,300,CONT_BODY_P,1260ymous_ +B 14000,29000,300,300,CONT_DIF_N,1206ymous_ +B 6000,25000,300,300,CONT_DIF_N,992nymous_ +B 7600,28000,300,300,CONT_DIF_N,1046ymous_ +B 19800,31000,300,300,CONT_POLY,1368ymous_ +B 17600,19200,300,300,CONT_BODY_P,1314ymous_ +B 22400,6000,300,300,CONT_VIA,400nymous_ +B 28000,33600,300,300,CONT_DIF_P,561nymous_ +B 9200,26000,300,300,CONT_DIF_N,1100ymous_ +B 10800,33000,300,300,CONT_DIF_N,1154ymous_ +B 26000,14000,300,300,CONT_VIA2,508nymous_ +B 25000,20400,300,300,CONT_DIF_P,454nymous_ +B 30000,19200,300,300,CONT_BODY_N,615nymous_ +B 32000,6000,300,300,CONT_VIA,669nymous_ +B 34400,6000,300,300,CONT_VIA2,777nymous_ +B 33200,8000,300,300,CONT_DIF_N,723nymous_ +B 3600,19200,300,300,CONT_BODY_P,831nymous_ +B 37000,35000,300,300,CONT_VIA2,885nymous_ +B 4400,31000,300,300,CONT_VIA2,939nymous_ +B 6000,26000,300,300,CONT_DIF_N,993nymous_ +B 1600,24400,300,300,CONT_BODY_P,1261ymous_ +B 14000,30000,300,300,CONT_DIF_N,1207ymous_ +B 33800,22000,300,300,CONT_VIA2,731nymous_ +B 7600,28000,300,300,CONT_VIA,1047ymous_ +B 9200,27000,300,300,CONT_DIF_N,1101ymous_ +B 19800,35200,300,300,CONT_VIA,1369ymous_ +B 17800,23200,300,300,CONT_DIF_N,1315ymous_ +B 25000,20400,300,300,CONT_VIA,455nymous_ +B 22400,6000,300,300,CONT_VIA2,401nymous_ +B 28000,35000,300,300,CONT_DIF_P,562nymous_ +B 30400,36600,300,300,CONT_POLY,616nymous_ +B 10800,34000,300,300,CONT_DIF_N,1155ymous_ +B 26000,16000,300,300,CONT_BODY_N,509nymous_ +B 32000,6000,300,300,CONT_VIA2,670nymous_ +B 33200,13000,300,300,CONT_DIF_P,724nymous_ +B 34400,8000,300,300,CONT_DIF_N,778nymous_ +B 36800,6000,300,300,CONT_BODY_P,832nymous_ +B 37000,36000,300,300,CONT_DIF_P,886nymous_ +B 14000,31000,300,300,CONT_DIF_N,1208ymous_ +B 4400,32000,300,300,CONT_DIF_N,940nymous_ +B 6000,27000,300,300,CONT_DIF_N,994nymous_ +B 17800,23200,300,300,CONT_VIA,1316ymous_ +B 1600,25400,300,300,CONT_BODY_P,1262ymous_ +B 7600,29000,300,300,CONT_DIF_N,1048ymous_ +B 9200,28000,300,300,CONT_DIF_N,1102ymous_ +B 19800,37600,300,300,CONT_BODY_P,1370ymous_ +B 25000,21600,300,300,CONT_DIF_P,456nymous_ +B 22400,8600,300,300,CONT_DIF_N,402nymous_ +B 28000,19200,300,300,CONT_BODY_N,563nymous_ +B 30400,36600,300,300,CONT_VIA,617nymous_ +B 10800,35000,300,300,CONT_DIF_N,1156ymous_ +B 26000,17000,300,300,CONT_VIA,510nymous_ +B 32000,8000,300,300,CONT_DIF_N,671nymous_ +B 33200,14000,300,300,CONT_DIF_P,725nymous_ +B 34400,13000,300,300,CONT_DIF_P,779nymous_ +B 36800,6000,300,300,CONT_VIA,833nymous_ +B 37000,36000,300,300,CONT_VIA,887nymous_ +B 4400,32000,300,300,CONT_VIA,941nymous_ +B 12400,27000,300,300,CONT_DIF_N,1175ymous_ +B 14000,32000,300,300,CONT_DIF_N,1209ymous_ +B 6000,28000,300,300,CONT_DIF_N,995nymous_ +B 7600,29000,300,300,CONT_VIA,1049ymous_ +B 17800,24400,300,300,CONT_DIF_N,1317ymous_ +B 1600,26400,300,300,CONT_BODY_P,1263ymous_ +B 22400,16000,300,300,CONT_BODY_N,403nymous_ +B 2800,23000,300,300,CONT_DIF_N,564nymous_ +B 9200,29000,300,300,CONT_DIF_N,1103ymous_ +B 10800,36000,300,300,CONT_DIF_N,1157ymous_ +B 26000,17000,300,300,CONT_VIA2,511nymous_ +B 25000,22800,300,300,CONT_DIF_P,457nymous_ +B 22400,8000,200,200,CONT_TURN1,355nymous_ +B 21200,10000,200,200,CONT_TURN1,354nymous_ +B 30400,36600,300,300,CONT_VIA2,618nymous_ +B 32000,13000,300,300,CONT_DIF_P,672nymous_ +B 33200,16000,300,300,CONT_BODY_N,726nymous_ +B 34400,13000,300,300,CONT_VIA,780nymous_ +B 36800,6000,300,300,CONT_VIA2,834nymous_ +B 37000,19200,300,300,CONT_BODY_N,888nymous_ +B 4400,32000,300,300,CONT_VIA2,942nymous_ +B 1600,27400,300,300,CONT_BODY_P,1264ymous_ +B 14000,33000,300,300,CONT_DIF_N,1210ymous_ +B 6000,29000,300,300,CONT_DIF_N,996nymous_ +B 7600,30000,300,300,CONT_DIF_N,1050ymous_ +B 17800,24400,300,300,CONT_VIA2,1318ymous_ +B 22400,17000,300,300,CONT_VIA,404nymous_ +B 2800,24000,300,300,CONT_DIF_N,565nymous_ +B 9200,30000,300,300,CONT_DIF_N,1104ymous_ +B 11600,6000,300,300,CONT_BODY_P,1158ymous_ +B 26000,19200,300,300,CONT_BODY_N,512nymous_ +B 25000,22800,300,300,CONT_VIA,458nymous_ +B 27200,16000,300,300,CONT_BODY_N,541nymous_ +B 30600,22000,300,300,CONT_DIF_P,619nymous_ +B 32000,16000,300,300,CONT_BODY_N,673nymous_ +B 34400,14000,300,300,CONT_DIF_P,781nymous_ +B 33200,17000,300,300,CONT_VIA,727nymous_ +B 36800,7000,300,300,CONT_BODY_P,835nymous_ +B 37200,37600,300,300,CONT_BODY_N,889nymous_ +B 4400,33000,300,300,CONT_DIF_N,943nymous_ +B 6000,30000,300,300,CONT_DIF_N,997nymous_ +B 1600,28400,300,300,CONT_BODY_P,1265ymous_ +B 14000,34000,300,300,CONT_DIF_N,1211ymous_ +B 7600,30000,300,300,CONT_VIA,1051ymous_ +B 9200,31000,300,300,CONT_DIF_N,1105ymous_ +B 17800,25600,300,300,CONT_DIF_N,1319ymous_ +B 25000,24000,300,300,CONT_DIF_P,459nymous_ +B 22400,17000,300,300,CONT_VIA2,405nymous_ +B 2800,25000,300,300,CONT_DIF_N,566nymous_ +B 30600,23000,300,300,CONT_DIF_P,620nymous_ +B 11600,6000,300,300,CONT_VIA,1159ymous_ +B 2600,37600,300,300,CONT_BODY_P,513nymous_ +B 32000,17000,300,300,CONT_VIA,674nymous_ +B 33200,17000,300,300,CONT_VIA2,728nymous_ +B 34400,14000,300,300,CONT_VIA,782nymous_ +B 36800,8000,300,300,CONT_BODY_P,836nymous_ +B 38000,27000,300,300,CONT_VIA2,890nymous_ +B 14000,35000,300,300,CONT_DIF_N,1212ymous_ +B 4400,33000,300,300,CONT_VIA,944nymous_ +B 6000,31000,300,300,CONT_DIF_N,998nymous_ +B 17800,25600,300,300,CONT_VIA,1320ymous_ +B 1600,29400,300,300,CONT_BODY_P,1266ymous_ +B 7600,30000,300,300,CONT_VIA2,1052ymous_ +B 9200,32000,300,300,CONT_DIF_N,1106ymous_ +B 25000,25200,300,300,CONT_DIF_P,460nymous_ +B 23000,20400,300,300,CONT_BODY_N,406nymous_ +B 2800,26000,300,300,CONT_DIF_N,567nymous_ +B 30600,24000,300,300,CONT_DIF_P,621nymous_ +B 11600,6000,300,300,CONT_VIA2,1160ymous_ +B 2600,19200,300,300,CONT_BODY_P,514nymous_ +B 32000,17000,300,300,CONT_VIA2,675nymous_ +B 33800,22000,300,300,CONT_DIF_P,729nymous_ +B 34400,16000,300,300,CONT_BODY_N,783nymous_ +B 36800,9000,300,300,CONT_BODY_P,837nymous_ +B 38000,28000,300,300,CONT_VIA2,891nymous_ +B 4400,34000,300,300,CONT_DIF_N,945nymous_ +B 14000,36000,300,300,CONT_DIF_N,1213ymous_ +B 6000,32000,300,300,CONT_DIF_N,999nymous_ +B 7600,31000,300,300,CONT_DIF_N,1053ymous_ +B 17800,25600,300,300,CONT_VIA2,1321ymous_ +B 1600,30400,300,300,CONT_BODY_P,1267ymous_ +B 23000,21400,300,300,CONT_BODY_N,407nymous_ +B 2800,27000,300,300,CONT_DIF_N,568nymous_ +B 9200,33000,300,300,CONT_DIF_N,1107ymous_ +B 11600,8000,300,300,CONT_DIF_N,1161ymous_ +B 27000,20400,300,300,CONT_DIF_P,515nymous_ +B 25000,26400,300,300,CONT_DIF_P,461nymous_ +B 30600,25000,300,300,CONT_DIF_P,622nymous_ +B 32000,19200,300,300,CONT_BODY_N,676nymous_ +B 33800,22000,300,300,CONT_VIA,730nymous_ +B 34800,20200,300,300,CONT_POLY,784nymous_ +B 36800,9000,300,300,CONT_VIA2,838nymous_ +B 38000,29000,300,300,CONT_VIA2,892nymous_ +B 4400,34000,300,300,CONT_VIA,946nymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/piot_mpx.vbe b/pdks/symbolic/mpxlib/cells/piot_mpx.vbe new file mode 100644 index 000000000..27237944c --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/piot_mpx.vbe @@ -0,0 +1,44 @@ +ENTITY piot_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT rup : NATURAL := 402; + CONSTANT rdown : NATURAL := 0 + ); + PORT ( + i : in BIT; + b : in BIT; + t : out BIT; + pad : inout MUX_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END piot_mpx; + +ARCHITECTURE behaviour_data_flow OF piot_mpx IS + SIGNAL b1 : BIT; + SIGNAL b2 : BIT; + SIGNAL b3 : BIT; + SIGNAL b4 : BIT; + SIGNAL b5 : BIT; + SIGNAL b6 : BIT; + +BEGIN + b6 <= b5; + b5 <= b4; + b4 <= b3; + b3 <= b2; + b2 <= b1; + b1 <= b; + label0 : BLOCK (b6 = '1') + BEGIN + pad <= GUARDED i; + END BLOCK label0; + t <= pad; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on piot_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/po_mpx.ap b/pdks/symbolic/mpxlib/cells/po_mpx.ap new file mode 100644 index 000000000..5e4ada923 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/po_mpx.ap @@ -0,0 +1,1541 @@ +V ALLIANCE : 6 +H po_mpx,P,17/9/2014,100 +A 0,0,40000,80000 +I 0,40000,padreal_mpx,padreal,NOSYM +S 27800,11800,28200,11800,200,i,RIGHT,POLY +S 27850,0,28150,0,600,i,RIGHT,CALU2 +S 27850,0,28150,0,600,i,RIGHT,CALU3 +S 28000,0,28000,0,400,i,RIGHT,CALU4 +S 28000,0,28000,0,400,i,RIGHT,CALU5 +S 28000,-150,28000,10750,600,i,UP,ALU2 +S 28800,9000,29000,9000,200,i,RIGHT,POLY +S 20000,48100,20000,71900,24400,pad,UP,CALU1 +S 28600,25800,29000,25800,600,pad,RIGHT,POLY +S 28600,30600,29000,30600,600,pad,RIGHT,POLY +S 28600,31800,29000,31800,600,pad,RIGHT,POLY +S 28600,33000,29000,33000,600,pad,RIGHT,POLY +S 29000,25900,29000,34900,400,pad,UP,ALU1 +S 29000,35100,29000,39700,400,pad,UP,ALU1 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +S 24000,34200,24400,34200,600,vdde,RIGHT,POLY +S 24000,35800,24400,35800,600,vdde,RIGHT,POLY +S 3600,22200,5200,22200,200,vdde,RIGHT,POLY +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 10650,21800,14150,21800,600,vdde,RIGHT,ALU2 +S 16800,30050,16800,38150,600,vdde,UP,ALU2 +S 16800,32200,17200,32200,200,vdde,RIGHT,POLY +S 16800,35800,17200,35800,200,vdde,RIGHT,POLY +S 25100,24000,27900,24000,400,vdde,RIGHT,ALU1 +S 25100,28800,27900,28800,400,vdde,RIGHT,ALU1 +S 25100,26400,27900,26400,400,vdde,RIGHT,ALU1 +S 25100,21600,27900,21600,400,vdde,RIGHT,ALU1 +S 6800,22200,8400,22200,200,vdde,RIGHT,POLY +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 16800,33400,17200,33400,200,vdde,RIGHT,POLY +S 16800,34600,17200,34600,200,vdde,RIGHT,POLY +S 20000,9600,20000,11000,200,vddi,UP,POLY +S 3100,16000,36900,16000,2400,vddi,RIGHT,ALU1 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 20800,22900,20800,37100,400,vsse,UP,ALU1 +S 30400,36400,30400,36600,200,vsse,UP,POLY +S 30250,36600,30550,36600,600,vsse,RIGHT,ALU2 +S 4400,22900,4400,37500,400,vsse,UP,ALU1 +S 7600,22900,7600,37500,400,vsse,UP,ALU1 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 17800,23050,17800,31750,600,vsse,UP,ALU2 +S 3100,6000,36900,6000,2400,vssi,RIGHT,ALU1 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 29600,9800,29600,11400,200,248nymous_,UP,POLY +S 14600,11100,14600,13100,200,p17c,UP,PTRANS +S 14800,22500,14800,36700,200,n15d,UP,NTRANS +S 6200,10900,6200,14900,200,p18b,UP,PTRANS +S 30800,8100,30800,12900,400,cnbb,UP,ALU1 +S 30800,10600,33800,10600,200,cnbb,RIGHT,POLY +S 6800,22500,6800,36700,200,n14c,UP,NTRANS +S 35000,7300,35000,8300,200,n5b,UP,NTRANS +S 35000,12700,35000,14700,200,p5b,UP,PTRANS +S 27800,12500,27800,14500,200,p1,UP,PTRANS +S 18800,8500,18800,9100,420,13onymous_,UP,NDIF +S 18800,9100,18800,9900,400,12onymous_,UP,ALU1 +S 16800,23200,16800,25400,600,52onymous_,UP,POLY +S 16800,24250,16800,29350,600,51onymous_,UP,ALU2 +S 16800,21050,16800,24550,600,53onymous_,UP,ALU2 +S 18650,17000,20150,17000,600,11onymous_,RIGHT,ALU2 +S 17500,22600,19100,22600,200,n6d,RIGHT,NTRANS +S 26000,6100,26000,7900,400,285nymous_,UP,ALU1 +S 26000,31050,26000,36950,600,286nymous_,UP,ALU2 +S 12400,22700,12400,36500,620,93onymous_,UP,NDIF +S 19800,32900,19800,35100,400,10onymous_,UP,ALU1 +S 38200,19300,38200,37500,400,169nymous_,UP,ALU1 +S 32200,21100,32200,36500,620,211nymous_,UP,PDIF +S 32200,21300,32200,39700,400,210nymous_,UP,ALU1 +S 23000,19300,23000,37500,400,321nymous_,UP,ALU1 +S 12400,18650,12400,21950,2400,92onymous_,UP,ALU2 +S 23000,19080,23000,37920,600,320nymous_,UP,NTIE +S 9200,7500,9200,9100,620,127nymous_,UP,NDIF +S 12800,7500,12800,9100,620,91onymous_,UP,NDIF +S 23100,19200,38100,19200,400,319nymous_,RIGHT,ALU1 +S 9050,10000,26150,10000,2400,126nymous_,RIGHT,ALU2 +S 22880,19200,38320,19200,600,318nymous_,RIGHT,NTIE +S 29600,7100,29600,8100,620,249nymous_,UP,NDIF +S 12400,20700,12400,36300,400,94onymous_,UP,ALU1 +S 9050,6000,26150,6000,600,130nymous_,RIGHT,ALU2 +S 9200,6100,9200,7900,400,129nymous_,UP,ALU1 +S 23000,11850,23000,17150,2000,322nymous_,UP,ALU2 +S 25100,35000,29100,35000,400,290nymous_,RIGHT,ALU1 +S 9200,5850,9200,11150,600,128nymous_,UP,ALU2 +S 25400,8600,25400,12400,200,289nymous_,UP,POLY +S 29480,37600,38520,37600,600,250nymous_,RIGHT,NTIE +S 26000,21450,26000,24150,600,288nymous_,UP,ALU2 +S 26000,23850,26000,28950,600,287nymous_,UP,ALU2 +S 31400,35300,31400,36100,200,p11,UP,PTRANS +S 17900,36400,18700,36400,400,17onymous_,RIGHT,ALU1 +S 1800,17850,1800,38150,1600,16onymous_,UP,ALU2 +S 16800,20300,16800,23300,400,55onymous_,UP,ALU1 +S 3200,11100,3200,15900,400,215nymous_,UP,ALU1 +S 36800,10880,36800,16120,600,173nymous_,UP,NTIE +S 16650,21200,25150,21200,600,54onymous_,RIGHT,ALU2 +S 3200,10880,3200,16120,600,214nymous_,UP,NTIE +S 37000,21100,37000,36500,620,172nymous_,UP,PDIF +S 22400,8500,22400,9100,620,325nymous_,UP,NDIF +S 3050,15400,19150,15400,600,213nymous_,RIGHT,ALU2 +S 37000,17850,37000,38150,2400,170nymous_,UP,ALU2 +S 23100,37600,27700,37600,400,323nymous_,RIGHT,ALU1 +S 3050,17000,18950,17000,600,212nymous_,RIGHT,ALU2 +S 22250,17000,23550,17000,600,324nymous_,RIGHT,ALU2 +S 37000,21300,37000,36300,400,171nymous_,UP,ALU1 +S 16650,20200,24150,20200,600,56onymous_,RIGHT,ALU2 +S 16400,12100,16400,15900,400,57onymous_,UP,ALU1 +S 16400,11300,16400,12900,620,58onymous_,UP,PDIF +S 18400,10100,18400,12700,400,14onymous_,UP,ALU1 +S 18200,9600,21800,9600,200,15onymous_,RIGHT,POLY +S 31400,20900,31400,34300,200,p14a,UP,PTRANS +S 16400,7500,16400,9100,620,59onymous_,UP,NDIF +S 36800,5880,36800,8720,600,177nymous_,UP,PTIE +S 24900,36400,28100,36400,620,294nymous_,RIGHT,PDIF +S 36800,6100,36800,9100,400,176nymous_,UP,ALU1 +S 22000,18050,22000,19350,600,329nymous_,UP,ALU2 +S 24800,7500,24800,8100,620,293nymous_,UP,NDIF +S 3050,6000,6950,6000,600,217nymous_,RIGHT,ALU2 +S 1050,37000,8750,37000,2400,97onymous_,RIGHT,ALU2 +S 36800,7050,36800,17150,600,175nymous_,UP,ALU2 +S 21850,18200,24950,18200,600,328nymous_,RIGHT,ALU2 +S 24800,8100,24800,13900,400,292nymous_,UP,ALU1 +S 3050,10000,6150,10000,2400,216nymous_,RIGHT,ALU2 +S 36800,11100,36800,15900,400,174nymous_,UP,ALU1 +S 9200,22700,9200,36500,620,131nymous_,UP,NDIF +S 9200,20700,9200,36300,400,132nymous_,UP,ALU1 +S 12200,9600,12200,10800,200,95onymous_,UP,POLY +S 22400,8100,22400,8500,400,326nymous_,UP,ALU1 +S 8600,9600,8600,10600,200,133nymous_,UP,POLY +S 22000,19300,22000,22100,400,327nymous_,UP,ALU1 +S 1050,19000,9150,19000,2400,96onymous_,RIGHT,ALU2 +S 16400,6100,16400,8900,400,60onymous_,UP,ALU1 +S 16400,30050,16400,32150,600,61onymous_,UP,ALU2 +S 24800,13100,24800,14500,620,291nymous_,UP,PDIF +S 28850,18200,34550,18200,600,253nymous_,RIGHT,ALU2 +S 29000,18450,29000,19350,600,252nymous_,UP,ALU2 +S 29450,37000,31750,37000,2400,251nymous_,RIGHT,ALU2 +S 7400,7300,7400,9300,200,n18c,UP,NTRANS +S 7400,10900,7400,14900,200,p18c,UP,PTRANS +S 20000,8500,20000,9100,620,pad2,UP,NDIF +S 2700,20600,15700,20600,400,pad2,RIGHT,ALU1 +S 2900,20600,15500,20600,400,pad2,RIGHT,ALU1 +S 17900,31600,18700,31600,400,19onymous_,RIGHT,ALU1 +S 17900,34000,18700,34000,400,18onymous_,RIGHT,ALU1 +S 1600,19080,1600,37720,600,62onymous_,UP,PTIE +S 21200,9100,21200,9900,400,331nymous_,UP,ALU1 +S 3200,5880,3200,8720,600,220nymous_,UP,PTIE +S 8000,8100,8000,8900,400,136nymous_,UP,ALU1 +S 36700,37600,38100,37600,400,178nymous_,RIGHT,ALU1 +S 11600,7500,11600,9100,420,100nymous_,UP,NDIF +S 24900,35000,28100,35000,820,295nymous_,RIGHT,PDIF +S 3200,6100,3200,9100,400,219nymous_,UP,ALU1 +S 8000,11100,8000,13700,400,135nymous_,UP,ALU1 +S 11600,11100,11600,14700,620,99onymous_,UP,PDIF +S 22000,22050,22000,28350,600,330nymous_,UP,ALU2 +S 3200,5850,3200,15950,600,218nymous_,UP,ALU2 +S 8000,11100,8000,14700,620,134nymous_,UP,PDIF +S 11600,11900,11600,15900,400,98onymous_,UP,ALU1 +S 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5000,7300,5000,9300,200,n18a,UP,NTRANS +S 13400,11100,13400,13100,200,p17b,UP,PTRANS +S 17500,25000,19100,25000,200,n7c,RIGHT,NTRANS +S 4250,13000,20150,13000,2400,158nymous_,RIGHT,ALU2 +S 33400,11850,33400,17150,600,202nymous_,UP,ALU2 +S 17500,23800,19100,23800,200,n7d,RIGHT,NTRANS +S 4400,11900,4400,15900,400,159nymous_,UP,ALU1 +S 13400,7300,13400,9300,200,n17b,UP,NTRANS +S 5000,10000,11000,10000,600,nt,RIGHT,POLY +S 17000,12000,17400,12000,200,nt,RIGHT,POLY +S 13200,22500,13200,36700,200,n15c,UP,NTRANS +S 16900,24400,17700,24400,400,50onymous_,RIGHT,ALU1 +S 17500,28600,19100,28600,200,n7b,RIGHT,NTRANS +S 14000,22900,14000,39700,400,83onymous_,UP,ALU1 +S 5000,10900,5000,14900,200,p18a,UP,PTRANS +S 30200,8600,30200,9000,200,242nymous_,UP,POLY +S 10000,22500,10000,36700,200,n15a,UP,NTRANS +S 17500,29800,19100,29800,200,n7a,RIGHT,NTRANS +S 5200,22500,5200,36700,200,n14b,UP,NTRANS +S 14000,6100,14000,7900,400,82onymous_,UP,ALU1 +S 30200,9000,31800,9000,200,eb,RIGHT,POLY +S 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34600,200,34600,12000,11000,2nonymous_,UP,TALU5 +S 4400,7500,4400,9100,620,161nymous_,UP,NDIF +S 4400,6100,4400,8900,400,162nymous_,UP,ALU1 +S 26000,13850,26000,15950,600,280nymous_,UP,ALU2 +S 25850,17000,33350,17000,600,279nymous_,RIGHT,ALU2 +S 17500,31000,19100,31000,200,n6a,RIGHT,NTRANS +S 2700,20200,15700,20200,400,278nymous_,RIGHT,ALU1 +S 17500,32200,19100,32200,200,n8d,RIGHT,NTRANS +S 17500,33400,19100,33400,200,n8c,RIGHT,NTRANS +S 17500,34600,19100,34600,200,n8b,RIGHT,NTRANS +S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 +S 24700,28200,28300,28200,200,p6b,RIGHT,PTRANS +S 24700,29400,28300,29400,200,p6a,RIGHT,PTRANS +S 24700,30600,28300,30600,200,p8c,RIGHT,PTRANS +S 26000,13100,26000,15900,400,281nymous_,UP,ALU1 +S 30100,20200,35900,20200,400,243nymous_,RIGHT,ALU1 +S 14000,21800,14000,22200,600,85onymous_,UP,POLY +S 30000,20050,30000,24750,600,244nymous_,UP,ALU2 +S 13400,9600,13400,10800,200,86onymous_,UP,POLY +S 9650,37000,16950,37000,2400,119nymous_,RIGHT,ALU2 +S 29600,13100,29600,13900,400,245nymous_,UP,ALU1 +S 33200,12900,33200,14500,620,204nymous_,UP,PDIF +S 9650,22800,16950,22800,600,120nymous_,RIGHT,ALU2 +S 33200,7500,33200,8100,620,205nymous_,UP,NDIF +S 9800,21650,9800,22950,600,121nymous_,UP,ALU2 +S 13400,200,13400,12000,27000,3nonymous_,UP,TALU5 +S 33200,6100,33200,7900,400,206nymous_,UP,ALU1 +S 50,6000,26800,6000,12000,4nonymous_,RIGHT,TALU2 +S 12800,11300,12800,12900,620,87onymous_,UP,PDIF +S 4400,22850,4400,38150,2400,163nymous_,UP,ALU2 +S 29200,6000,39950,6000,12000,5nonymous_,RIGHT,TALU2 +S 32800,20200,32800,20600,600,207nymous_,UP,POLY +S 12900,11000,17300,11000,400,88onymous_,RIGHT,ALU1 +S 4400,22900,4400,37500,400,164nymous_,UP,ALU1 +S 4400,22700,4400,36500,620,165nymous_,UP,NDIF +S 17500,35800,19100,35800,200,n8a,RIGHT,NTRANS +S 14600,7300,14600,9300,200,n17c,UP,NTRANS +S 6200,7300,6200,9300,200,n18b,UP,NTRANS +S 27800,7300,27800,8300,200,n2,UP,NTRANS +S 34600,20900,34600,36700,200,p14c,UP,PTRANS +S 24700,31800,28300,31800,200,p8b,RIGHT,PTRANS +S 24700,33000,28300,33000,200,p8a,RIGHT,PTRANS +S 24700,34200,28300,34200,200,p9,RIGHT,PTRANS +S 24700,35800,28300,35800,200,p12,RIGHT,PTRANS +S 26000,12900,26000,14500,620,282nymous_,UP,PDIF +S 26000,8850,26000,14150,600,283nymous_,UP,ALU2 +S 26000,7500,26000,8100,620,284nymous_,UP,NDIF +S 29600,12700,29600,14300,620,246nymous_,UP,PDIF +S 29600,10450,29600,16150,600,247nymous_,UP,ALU2 +S 9450,31000,15950,31000,2400,122nymous_,RIGHT,ALU2 +S 9450,25000,15950,25000,2400,123nymous_,RIGHT,ALU2 +S 23600,6100,23600,7900,400,316nymous_,UP,ALU1 +S 9200,12100,9200,15900,400,124nymous_,UP,ALU1 +S 23080,37600,29920,37600,600,317nymous_,RIGHT,NTIE +S 50,6000,26800,6000,12000,6nonymous_,RIGHT,TALU4 +S 12900,9000,15100,9000,400,89onymous_,RIGHT,ALU1 +S 9200,11100,9200,14700,620,125nymous_,UP,PDIF +S 29200,6000,39950,6000,12000,7nonymous_,RIGHT,TALU4 +S 12800,8100,12800,12500,400,90onymous_,UP,ALU1 +S 32600,11400,32600,12400,200,208nymous_,UP,POLY +S 0,6000,40000,6000,12000,8nonymous_,RIGHT,TALU6 +S 4400,21800,4400,22200,600,166nymous_,UP,POLY +S 32600,8600,32600,9800,200,209nymous_,UP,POLY +S 4050,7600,7150,7600,600,167nymous_,RIGHT,ALU2 +S 19800,35050,19800,36950,600,9nonymous_,UP,ALU2 +S 38200,19080,38200,37920,600,168nymous_,UP,NTIE +B 19800,35200,300,300,CONT_VIA,342nymous_ +B 19800,37600,300,300,CONT_BODY_P,341nymous_ +B 19800,31000,300,300,CONT_POLY,343nymous_ +B 19800,28200,300,300,CONT_VIA,344nymous_ +B 19800,27400,300,300,CONT_POLY,345nymous_ +B 19800,26200,300,300,CONT_POLY,346nymous_ +B 19800,22600,300,300,CONT_POLY,347nymous_ +B 19600,19200,300,300,CONT_BODY_P,348nymous_ +B 18800,17000,300,300,CONT_VIA2,349nymous_ +B 18800,16000,300,300,CONT_BODY_N,351nymous_ +B 18800,17000,300,300,CONT_VIA,350nymous_ +B 18800,9000,300,300,CONT_DIF_N,352nymous_ +B 18800,6000,300,300,CONT_VIA2,353nymous_ +B 24000,29200,300,300,CONT_POLY,1268ymous_ +B 26000,30000,300,300,CONT_DIF_P,1214ymous_ +B 32200,34000,300,300,CONT_DIF_P,1000ymous_ +B 30800,16000,300,300,CONT_BODY_N,1054ymous_ +B 20800,30400,300,300,CONT_BODY_P,1322ymous_ +B 16800,35800,300,300,CONT_VIA,408nymous_ +B 10800,21800,300,300,CONT_POLY,569nymous_ +B 29000,31800,300,300,CONT_POLY,1108ymous_ +B 27200,17000,300,300,CONT_VIA2,1162ymous_ +B 12800,17000,300,300,CONT_VIA,516nymous_ +B 15600,34000,300,300,CONT_DIF_N,462nymous_ +B 8600,25000,300,300,CONT_VIA2,623nymous_ +B 7000,11000,300,300,CONT_VIA2,677nymous_ +B 4400,25000,300,300,CONT_DIF_N,785nymous_ +B 37000,29000,300,300,CONT_DIF_P,839nymous_ +B 35600,14000,300,300,CONT_DIF_P,893nymous_ +B 33800,34000,300,300,CONT_VIA,947nymous_ +B 24000,28200,300,300,CONT_VIA,1269ymous_ +B 26000,28800,300,300,CONT_VIA2,1215ymous_ +B 32200,33000,300,300,CONT_DIF_P,1001ymous_ +B 30800,14000,300,300,CONT_DIF_P,1055ymous_ +B 20800,29400,300,300,CONT_BODY_P,1323ymous_ +B 15600,33000,300,300,CONT_DIF_N,463nymous_ +B 16800,35800,300,300,CONT_POLY,409nymous_ +B 10600,19200,300,300,CONT_BODY_P,570nymous_ +B 8600,24000,300,300,CONT_VIA2,624nymous_ +B 29000,30600,300,300,CONT_POLY,1109ymous_ +B 27200,17000,300,300,CONT_VIA,1163ymous_ +B 12800,16000,300,300,CONT_BODY_N,517nymous_ +B 7000,10000,300,300,CONT_VIA2,678nymous_ +B 5600,37600,300,300,CONT_BODY_P,732nymous_ +B 4400,24000,300,300,CONT_VIA2,786nymous_ +B 37000,28000,300,300,CONT_VIA2,840nymous_ +B 11600,19200,300,300,CONT_BODY_P,540nymous_ +B 35600,13000,300,300,CONT_DIF_P,894nymous_ +B 26000,28800,300,300,CONT_VIA,1216ymous_ +B 33800,34000,300,300,CONT_DIF_P,948nymous_ +B 32200,32000,300,300,CONT_DIF_P,1002ymous_ +B 20800,28400,300,300,CONT_BODY_P,1324ymous_ +B 24000,28200,300,300,CONT_POLY,1270ymous_ +B 18800,37600,300,300,CONT_BODY_P,356nymous_ +B 30800,13000,300,300,CONT_DIF_P,1056ymous_ +B 29000,25800,300,300,CONT_POLY,1110ymous_ +B 15600,32000,300,300,CONT_DIF_N,464nymous_ +B 16800,34600,300,300,CONT_VIA2,410nymous_ +B 10400,17000,300,300,CONT_VIA2,571nymous_ +B 8000,17000,300,300,CONT_VIA2,625nymous_ +B 27200,16000,300,300,CONT_BODY_N,1164ymous_ +B 12800,12600,300,300,CONT_DIF_P,518nymous_ +B 7000,9000,300,300,CONT_VIA2,679nymous_ +B 5400,36000,300,300,CONT_VIA2,733nymous_ +B 4400,24000,300,300,CONT_VIA,787nymous_ +B 37000,28000,300,300,CONT_VIA,841nymous_ +B 35600,8000,300,300,CONT_DIF_N,895nymous_ +B 26000,28800,300,300,CONT_DIF_P,1217ymous_ +B 33800,33000,300,300,CONT_VIA2,949nymous_ +B 32200,31000,300,300,CONT_DIF_P,1003ymous_ +B 20800,27400,300,300,CONT_BODY_P,1325ymous_ +B 24000,27000,300,300,CONT_POLY,1271ymous_ +B 16800,34600,300,300,CONT_VIA,411nymous_ +B 18800,36400,300,300,CONT_VIA,357nymous_ +B 10400,17000,300,300,CONT_VIA,572nymous_ +B 30800,10600,300,300,CONT_POLY,1057ymous_ +B 29000,24600,300,300,CONT_VIA,1111ymous_ +B 27200,14000,300,300,CONT_DIF_P,1165ymous_ +B 12800,11600,300,300,CONT_DIF_P,519nymous_ +B 15600,31000,300,300,CONT_DIF_N,465nymous_ +B 8000,17000,300,300,CONT_VIA,626nymous_ +B 6800,17000,300,300,CONT_VIA2,680nymous_ +B 5400,32000,300,300,CONT_VIA2,734nymous_ +B 4400,24000,300,300,CONT_DIF_N,788nymous_ +B 37000,28000,300,300,CONT_DIF_P,842nymous_ +B 35600,6000,300,300,CONT_VIA2,896nymous_ +B 33800,33000,300,300,CONT_VIA,950nymous_ +B 23600,16000,300,300,CONT_BODY_N,1272ymous_ +B 26000,27600,300,300,CONT_VIA2,1218ymous_ +B 32200,30000,300,300,CONT_DIF_P,1004ymous_ +B 30800,8000,300,300,CONT_DIF_N,1058ymous_ +B 20800,26400,300,300,CONT_BODY_P,1326ymous_ +B 16800,34600,300,300,CONT_POLY,412nymous_ +B 18800,36400,300,300,CONT_DIF_N,358nymous_ +B 10400,16000,300,300,CONT_BODY_N,573nymous_ +B 29000,24600,300,300,CONT_POLY,1112ymous_ +B 27200,13000,300,300,CONT_DIF_P,1166ymous_ +B 12800,9000,300,300,CONT_DIF_N,520nymous_ +B 15600,30000,300,300,CONT_DIF_N,466nymous_ +B 8000,16000,300,300,CONT_BODY_N,627nymous_ +B 6800,17000,300,300,CONT_VIA,681nymous_ +B 5400,31000,300,300,CONT_VIA2,735nymous_ +B 4400,23000,300,300,CONT_VIA,789nymous_ +B 37000,27000,300,300,CONT_VIA2,843nymous_ +B 35600,6000,300,300,CONT_VIA,897nymous_ +B 33800,33000,300,300,CONT_DIF_P,951nymous_ +B 23600,14000,300,300,CONT_DIF_P,1273ymous_ +B 26000,27600,300,300,CONT_DIF_P,1219ymous_ +B 18800,35200,300,300,CONT_DIF_N,359nymous_ +B 32200,29000,300,300,CONT_DIF_P,1005ymous_ +B 30800,6000,300,300,CONT_BODY_P,1059ymous_ +B 20800,25400,300,300,CONT_BODY_P,1327ymous_ +B 15600,29000,300,300,CONT_DIF_N,467nymous_ +B 16800,33400,300,300,CONT_VIA2,413nymous_ +B 10400,13800,300,300,CONT_DIF_P,574nymous_ +B 8000,13800,300,300,CONT_DIF_P,628nymous_ +B 29000,23400,300,300,CONT_VIA,1113ymous_ +B 27200,10600,300,300,CONT_POLY,1167ymous_ +B 12800,8000,300,300,CONT_DIF_N,521nymous_ +B 6800,16000,300,300,CONT_BODY_N,682nymous_ +B 5400,30000,300,300,CONT_VIA2,736nymous_ +B 4400,23000,300,300,CONT_DIF_N,790nymous_ +B 37000,27000,300,300,CONT_VIA,844nymous_ +B 35600,6000,300,300,CONT_BODY_P,898nymous_ +B 26000,26400,300,300,CONT_VIA,1220ymous_ +B 33800,32000,300,300,CONT_VIA,952nymous_ +B 32200,28000,300,300,CONT_DIF_P,1006ymous_ +B 20800,24400,300,300,CONT_BODY_P,1328ymous_ +B 23600,13000,300,300,CONT_DIF_P,1274ymous_ +B 18800,34000,300,300,CONT_VIA,360nymous_ +B 30600,35000,300,300,CONT_VIA2,1060ymous_ +B 29000,23400,300,300,CONT_POLY,1114ymous_ +B 15600,28000,300,300,CONT_DIF_N,468nymous_ +B 16800,33400,300,300,CONT_VIA,414nymous_ +B 10400,12800,300,300,CONT_DIF_P,575nymous_ +B 8000,12800,300,300,CONT_DIF_P,629nymous_ +B 27200,8000,300,300,CONT_DIF_N,1168ymous_ +B 12800,6000,300,300,CONT_VIA2,522nymous_ +B 6800,14800,300,300,CONT_DIF_P,683nymous_ +B 5400,26000,300,300,CONT_VIA2,737nymous_ +B 4400,21800,300,300,CONT_VIA,791nymous_ +B 37000,27000,300,300,CONT_DIF_P,845nymous_ +B 5400,25000,300,300,CONT_VIA2,738nymous_ +B 35400,35000,300,300,CONT_DIF_P,900nymous_ +B 33800,31000,300,300,CONT_VIA,954nymous_ +B 23600,6000,300,300,CONT_VIA2,1276ymous_ +B 26000,25200,300,300,CONT_DIF_P,1222ymous_ +B 32200,26000,300,300,CONT_DIF_P,1008ymous_ +B 30600,35000,300,300,CONT_DIF_P,1062ymous_ +B 20800,22400,300,300,CONT_BODY_P,1330ymous_ +B 16800,32200,300,300,CONT_VIA,416nymous_ +B 18800,32800,300,300,CONT_DIF_N,362nymous_ +B 10400,10000,300,300,CONT_POLY,577nymous_ +B 29000,22200,300,300,CONT_POLY,1116ymous_ +B 27000,19200,300,300,CONT_BODY_N,1170ymous_ +B 12800,6000,300,300,CONT_BODY_P,524nymous_ +B 35400,36000,300,300,CONT_DIF_P,899nymous_ +B 26000,26400,300,300,CONT_DIF_P,1221ymous_ +B 33800,32000,300,300,CONT_DIF_P,953nymous_ +B 32200,27000,300,300,CONT_DIF_P,1007ymous_ +B 20800,23400,300,300,CONT_BODY_P,1329ymous_ +B 23600,8000,300,300,CONT_DIF_N,1275ymous_ +B 16800,33400,300,300,CONT_POLY,415nymous_ +B 18800,34000,300,300,CONT_DIF_N,361nymous_ +B 10400,11800,300,300,CONT_DIF_P,576nymous_ +B 30600,35000,300,300,CONT_VIA,1061ymous_ +B 29000,22200,300,300,CONT_VIA,1115ymous_ +B 12800,6000,300,300,CONT_VIA,523nymous_ +B 15600,27000,300,300,CONT_DIF_N,469nymous_ +B 8000,11800,300,300,CONT_DIF_P,630nymous_ +B 6800,13800,300,300,CONT_DIF_P,684nymous_ +B 27200,6000,300,300,CONT_BODY_P,1169ymous_ +B 4400,21800,300,300,CONT_POLY,792nymous_ +B 37000,26000,300,300,CONT_VIA,846nymous_ +B 35400,34000,300,300,CONT_DIF_P,901nymous_ +B 33800,31000,300,300,CONT_DIF_P,955nymous_ +B 23600,6000,300,300,CONT_VIA,1277ymous_ +B 26000,24000,300,300,CONT_VIA,1223ymous_ +B 18800,31600,300,300,CONT_VIA,363nymous_ +B 32200,25000,300,300,CONT_DIF_P,1009ymous_ +B 30600,34000,300,300,CONT_VIA2,1063ymous_ +B 20800,21400,300,300,CONT_BODY_P,1331ymous_ +B 15600,25000,300,300,CONT_DIF_N,471nymous_ +B 16800,32200,300,300,CONT_POLY,417nymous_ +B 10400,9000,300,300,CONT_DIF_N,578nymous_ +B 8000,10000,300,300,CONT_POLY,632nymous_ +B 29000,21000,300,300,CONT_VIA,1117ymous_ +B 27000,11000,300,300,CONT_VIA2,1171ymous_ +B 12600,19200,300,300,CONT_BODY_P,525nymous_ +B 6800,12000,300,300,CONT_DIF_P,686nymous_ +B 4600,19200,300,300,CONT_BODY_P,740nymous_ +B 38200,37600,300,300,CONT_BODY_N,794nymous_ +B 37000,25000,300,300,CONT_VIA,848nymous_ +B 35400,33000,300,300,CONT_DIF_P,902nymous_ +B 26000,24000,300,300,CONT_DIF_P,1224ymous_ +B 33800,30000,300,300,CONT_VIA,956nymous_ +B 32200,24000,300,300,CONT_DIF_P,1010ymous_ +B 20800,20400,300,300,CONT_BODY_P,1332ymous_ +B 23600,6000,300,300,CONT_BODY_P,1278ymous_ +B 18800,31600,300,300,CONT_DIF_N,364nymous_ +B 37000,26000,300,300,CONT_DIF_P,847nymous_ +B 38200,19200,300,300,CONT_BODY_N,793nymous_ +B 5400,24000,300,300,CONT_VIA2,739nymous_ +B 6800,12800,300,300,CONT_DIF_P,685nymous_ +B 8000,11000,300,300,CONT_VIA,631nymous_ +B 15600,26000,300,300,CONT_DIF_N,470nymous_ +B 35400,31000,300,300,CONT_DIF_P,904nymous_ +B 37000,24000,300,300,CONT_VIA,850nymous_ +B 38200,35400,300,300,CONT_BODY_N,796nymous_ +B 27000,9000,300,300,CONT_VIA2,1173ymous_ +B 4600,37600,300,300,CONT_VIA,742nymous_ +B 6800,8000,300,300,CONT_DIF_N,688nymous_ +B 8000,9000,300,300,CONT_DIF_N,634nymous_ +B 15600,23000,300,300,CONT_DIF_N,473nymous_ +B 12400,35000,300,300,CONT_DIF_N,527nymous_ +B 28800,9000,300,300,CONT_POLY,1119ymous_ +B 30600,34000,300,300,CONT_DIF_P,1065ymous_ +B 10400,6000,300,300,CONT_VIA2,580nymous_ +B 18800,30400,300,300,CONT_DIF_N,365nymous_ +B 16800,28200,300,300,CONT_POLY,419nymous_ +B 23400,17000,300,300,CONT_VIA2,1279ymous_ +B 20000,16000,300,300,CONT_BODY_N,1333ymous_ +B 32200,23000,300,300,CONT_DIF_P,1011ymous_ +B 33800,30000,300,300,CONT_DIF_P,957nymous_ +B 26000,22800,300,300,CONT_VIA2,1225ymous_ +B 35400,32000,300,300,CONT_DIF_P,903nymous_ +B 37000,25000,300,300,CONT_DIF_P,849nymous_ +B 38200,36400,300,300,CONT_BODY_N,795nymous_ +B 4600,37600,300,300,CONT_VIA2,741nymous_ +B 6800,10000,300,300,CONT_POLY,687nymous_ +B 12400,36000,300,300,CONT_DIF_N,526nymous_ +B 27000,10000,300,300,CONT_VIA2,1172ymous_ +B 8000,9000,300,300,CONT_VIA,633nymous_ +B 10400,8000,300,300,CONT_DIF_N,579nymous_ +B 16800,29200,300,300,CONT_VIA,418nymous_ +B 15600,24000,300,300,CONT_DIF_N,472nymous_ +B 29000,21000,300,300,CONT_POLY,1118ymous_ +B 30600,34000,300,300,CONT_VIA,1064ymous_ +B 12400,33000,300,300,CONT_DIF_N,529nymous_ +B 28400,17000,300,300,CONT_VIA,1121ymous_ +B 7800,37600,300,300,CONT_VIA2,636nymous_ +B 10400,6000,300,300,CONT_BODY_P,582nymous_ +B 16800,24400,300,300,CONT_VIA,421nymous_ +B 15200,17000,300,300,CONT_VIA,475nymous_ +B 20000,8600,300,300,CONT_DIF_N,1335ymous_ +B 30600,33000,300,300,CONT_VIA,1067ymous_ +B 3200,17000,300,300,CONT_VIA2,1013ymous_ +B 18800,28000,300,300,CONT_DIF_N,367nymous_ +B 26000,21600,300,300,CONT_VIA2,1227ymous_ +B 23000,19200,300,300,CONT_BODY_N,1281ymous_ +B 33800,29000,300,300,CONT_VIA,959nymous_ +B 35400,30000,300,300,CONT_DIF_P,905nymous_ +B 37000,24000,300,300,CONT_DIF_P,851nymous_ +B 38200,34400,300,300,CONT_BODY_N,797nymous_ +B 4600,37600,300,300,CONT_BODY_P,743nymous_ +B 6800,7200,300,300,CONT_DIF_N,689nymous_ +B 8000,8000,300,300,CONT_DIF_N,635nymous_ +B 15200,17000,300,300,CONT_VIA2,474nymous_ +B 12400,34000,300,300,CONT_DIF_N,528nymous_ +B 27000,37600,300,300,CONT_BODY_N,1174ymous_ +B 28400,17000,300,300,CONT_VIA2,1120ymous_ +B 10400,6000,300,300,CONT_VIA,581nymous_ +B 18800,29200,300,300,CONT_DIF_N,366nymous_ +B 16800,25400,300,300,CONT_POLY,420nymous_ +B 20000,11000,300,300,CONT_POLY,1334ymous_ +B 30600,33000,300,300,CONT_VIA2,1066ymous_ +B 32200,22000,300,300,CONT_DIF_P,1012ymous_ +B 26000,22800,300,300,CONT_DIF_P,1226ymous_ +B 23400,17000,300,300,CONT_VIA,1280ymous_ +B 33800,29000,300,300,CONT_VIA2,958nymous_ +B 30600,32000,300,300,CONT_VIA,1069ymous_ +B 18800,26800,300,300,CONT_DIF_N,369nymous_ +B 16800,20200,300,300,CONT_VIA,423nymous_ +B 23000,36400,300,300,CONT_BODY_N,1283ymous_ +B 20000,6000,300,300,CONT_VIA,1337ymous_ +B 3200,16000,300,300,CONT_BODY_N,1015ymous_ +B 33800,28000,300,300,CONT_VIA2,961nymous_ +B 26000,21600,300,300,CONT_DIF_P,1229ymous_ +B 35400,28000,300,300,CONT_DIF_P,907nymous_ +B 37000,23000,300,300,CONT_VIA,853nymous_ +B 38200,32400,300,300,CONT_BODY_N,799nymous_ +B 4400,17000,300,300,CONT_VIA,745nymous_ +B 6800,6000,300,300,CONT_VIA,691nymous_ +B 12400,32000,300,300,CONT_DIF_N,530nymous_ +B 27000,36400,300,300,CONT_DIF_P,1176ymous_ +B 7800,37600,300,300,CONT_VIA,637nymous_ +B 9600,19200,300,300,CONT_BODY_P,583nymous_ +B 16800,23400,300,300,CONT_POLY,422nymous_ +B 15200,16000,300,300,CONT_BODY_N,476nymous_ +B 28400,16000,300,300,CONT_BODY_N,1122ymous_ +B 30600,33000,300,300,CONT_DIF_P,1068ymous_ +B 18800,26800,300,300,CONT_VIA,368nymous_ +B 23000,37600,300,300,CONT_BODY_N,1282ymous_ +B 20000,6000,300,300,CONT_VIA2,1336ymous_ +B 3200,17000,300,300,CONT_VIA,1014ymous_ +B 33800,29000,300,300,CONT_DIF_P,960nymous_ +B 26000,21600,300,300,CONT_VIA,1228ymous_ +B 35400,29000,300,300,CONT_DIF_P,906nymous_ +B 37000,23000,300,300,CONT_VIA2,852nymous_ +B 38200,33400,300,300,CONT_BODY_N,798nymous_ +B 4400,17000,300,300,CONT_VIA2,744nymous_ +B 6800,6000,300,300,CONT_VIA2,690nymous_ +B 3200,14000,300,300,CONT_VIA2,1017ymous_ +B 33800,28000,300,300,CONT_DIF_P,963nymous_ +B 35400,26000,300,300,CONT_DIF_P,909nymous_ +B 37000,22000,300,300,CONT_VIA2,855nymous_ +B 38200,30400,300,300,CONT_BODY_N,801nymous_ +B 4400,14800,300,300,CONT_DIF_P,747nymous_ +B 6800,37600,300,300,CONT_VIA2,693nymous_ +B 7600,19200,300,300,CONT_BODY_P,639nymous_ +B 15200,11600,300,300,CONT_DIF_P,478nymous_ +B 12400,30000,300,300,CONT_DIF_N,532nymous_ +B 27000,33600,300,300,CONT_DIF_P,1178ymous_ +B 28400,8000,300,300,CONT_DIF_N,1124ymous_ +B 9200,17000,300,300,CONT_VIA2,585nymous_ +B 18800,25600,300,300,CONT_DIF_N,370nymous_ +B 16600,19200,300,300,CONT_BODY_P,424nymous_ +B 20000,6000,300,300,CONT_BODY_P,1338ymous_ +B 30600,32000,300,300,CONT_DIF_P,1070ymous_ +B 3200,15000,300,300,CONT_BODY_N,1016ymous_ +B 26000,20400,300,300,CONT_DIF_P,1230ymous_ +B 23000,35400,300,300,CONT_BODY_N,1284ymous_ +B 33800,28000,300,300,CONT_VIA,962nymous_ +B 35400,27000,300,300,CONT_DIF_P,908nymous_ +B 37000,23000,300,300,CONT_DIF_P,854nymous_ +B 38200,31400,300,300,CONT_BODY_N,800nymous_ +B 27000,35000,300,300,CONT_DIF_P,1177ymous_ +B 4400,16000,300,300,CONT_BODY_N,746nymous_ +B 6800,6000,300,300,CONT_BODY_P,692nymous_ +B 7800,37600,300,300,CONT_BODY_P,638nymous_ +B 15200,12600,300,300,CONT_DIF_P,477nymous_ +B 12400,31000,300,300,CONT_DIF_N,531nymous_ +B 28400,14000,300,300,CONT_DIF_P,1123ymous_ +B 9600,37600,300,300,CONT_BODY_P,584nymous_ +B 15200,9000,300,300,CONT_DIF_N,480nymous_ +B 18400,12800,200,200,CONT_TURN1,1340ymous_ +B 28200,11800,300,300,CONT_POLY,1126ymous_ +B 30600,31000,300,300,CONT_DIF_P,1072ymous_ +B 18800,23200,300,300,CONT_DIF_N,372nymous_ +B 23000,33400,300,300,CONT_BODY_N,1286ymous_ +B 3200,14000,300,300,CONT_BODY_N,1018ymous_ +B 33800,27000,300,300,CONT_VIA2,964nymous_ +B 25000,37600,300,300,CONT_BODY_N,1232ymous_ +B 35400,25000,300,300,CONT_DIF_P,910nymous_ +B 37000,22000,300,300,CONT_VIA,856nymous_ +B 38200,29400,300,300,CONT_BODY_N,802nymous_ +B 4400,13800,300,300,CONT_DIF_P,748nymous_ +B 6800,37600,300,300,CONT_VIA,694nymous_ +B 12400,29000,300,300,CONT_DIF_N,533nymous_ +B 27000,32400,300,300,CONT_DIF_P,1179ymous_ +B 28400,6000,300,300,CONT_BODY_P,1125ymous_ +B 7600,36000,300,300,CONT_VIA2,640nymous_ +B 9200,17000,300,300,CONT_VIA,586nymous_ +B 16400,17000,300,300,CONT_VIA2,425nymous_ +B 15200,10000,300,300,CONT_POLY,479nymous_ +B 19800,32800,200,200,CONT_TURN1,1339ymous_ +B 30600,31000,300,300,CONT_VIA,1071ymous_ +B 18800,24400,300,300,CONT_DIF_N,371nymous_ +B 25000,19200,300,300,CONT_BODY_N,1231ymous_ +B 23000,34400,300,300,CONT_BODY_N,1285ymous_ +B 16400,17000,300,300,CONT_VIA,426nymous_ +B 9200,16000,300,300,CONT_BODY_N,587nymous_ +B 7600,36000,300,300,CONT_VIA,641nymous_ +B 12400,28000,300,300,CONT_DIF_N,534nymous_ +B 6800,37600,300,300,CONT_BODY_P,695nymous_ +B 4400,12800,300,300,CONT_DIF_P,749nymous_ +B 38200,28400,300,300,CONT_BODY_N,803nymous_ +B 37000,22000,300,300,CONT_DIF_P,857nymous_ +B 35400,24000,300,300,CONT_DIF_P,911nymous_ +B 25000,36400,300,300,CONT_DIF_P,1233ymous_ +B 33800,27000,300,300,CONT_VIA,965nymous_ +B 3200,13000,300,300,CONT_VIA2,1019ymous_ +B 23000,32400,300,300,CONT_BODY_N,1287ymous_ +B 16400,16000,300,300,CONT_BODY_N,427nymous_ +B 18800,22200,300,300,CONT_VIA,373nymous_ +B 9200,14800,300,300,CONT_DIF_P,588nymous_ +B 30600,30000,300,300,CONT_VIA,1073ymous_ +B 28200,10600,300,300,CONT_VIA,1127ymous_ +B 17800,22000,200,200,CONT_TURN1,1341ymous_ +B 12400,27000,300,300,CONT_DIF_N,535nymous_ +B 15200,8000,300,300,CONT_DIF_N,481nymous_ +B 7600,36000,300,300,CONT_DIF_N,642nymous_ +B 6600,19200,300,300,CONT_BODY_P,696nymous_ +B 4400,11800,300,300,CONT_DIF_P,750nymous_ +B 38200,27400,300,300,CONT_BODY_N,804nymous_ +B 36800,17000,300,300,CONT_VIA2,858nymous_ +B 35400,23000,300,300,CONT_DIF_P,912nymous_ +B 33800,27000,300,300,CONT_DIF_P,966nymous_ +B 23000,31400,300,300,CONT_BODY_N,1288ymous_ +B 25000,35000,300,300,CONT_DIF_P,1234ymous_ +B 3200,13000,300,300,CONT_BODY_N,1020ymous_ +B 30600,30000,300,300,CONT_DIF_P,1074ymous_ +B 16400,12800,300,300,CONT_DIF_P,428nymous_ +B 18800,22000,300,300,CONT_DIF_N,374nymous_ +B 9200,13800,300,300,CONT_DIF_P,589nymous_ +B 2800,36000,300,300,CONT_DIF_N,1128ymous_ +B 17600,8000,200,200,CONT_TURN1,1342ymous_ +B 12400,26000,300,300,CONT_DIF_N,536nymous_ +B 15200,6000,300,300,CONT_VIA2,482nymous_ +B 7600,35000,300,300,CONT_VIA,643nymous_ +B 6600,36000,300,300,CONT_VIA2,697nymous_ +B 4400,9000,300,300,CONT_DIF_N,751nymous_ +B 38200,26400,300,300,CONT_BODY_N,805nymous_ +B 36800,17000,300,300,CONT_VIA,859nymous_ +B 35400,22000,300,300,CONT_DIF_P,913nymous_ +B 33800,26000,300,300,CONT_VIA,967nymous_ +B 23000,30400,300,300,CONT_BODY_N,1289ymous_ +B 25000,33600,300,300,CONT_DIF_P,1235ymous_ +B 18600,19200,300,300,CONT_BODY_P,375nymous_ +B 3200,12000,300,300,CONT_VIA2,1021ymous_ +B 30600,29000,300,300,CONT_VIA2,1075ymous_ +B 17400,11000,200,200,CONT_TURN1,1343ymous_ +B 15200,6000,300,300,CONT_VIA,483nymous_ +B 16400,12000,300,300,CONT_DIF_P,429nymous_ +B 9200,12800,300,300,CONT_DIF_P,590nymous_ +B 7600,35000,300,300,CONT_DIF_N,644nymous_ +B 2800,35000,300,300,CONT_DIF_N,1129ymous_ +B 12400,25000,300,300,CONT_DIF_N,537nymous_ +B 6600,32000,300,300,CONT_VIA2,698nymous_ +B 4400,8000,300,300,CONT_DIF_N,752nymous_ +B 38200,25400,300,300,CONT_BODY_N,806nymous_ +B 36800,16000,300,300,CONT_VIA2,860nymous_ +B 35000,19200,300,300,CONT_BODY_N,914nymous_ +B 25000,32400,300,300,CONT_VIA,1236ymous_ +B 33800,26000,300,300,CONT_DIF_P,968nymous_ +B 3200,12000,300,300,CONT_BODY_N,1022ymous_ +B 23000,29400,300,300,CONT_BODY_N,1290ymous_ +B 17800,37600,300,300,CONT_BODY_P,376nymous_ +B 10400,11000,200,200,CONT_TURN1,1344ymous_ +B 27000,28800,300,300,CONT_DIF_P,1182ymous_ +B 30600,29000,300,300,CONT_VIA,1076ymous_ +B 2800,34000,300,300,CONT_DIF_N,1130ymous_ +B 15200,6000,300,300,CONT_BODY_P,484nymous_ +B 16400,10000,300,300,CONT_POLY,430nymous_ +B 9200,12000,300,300,CONT_DIF_P,591nymous_ +B 7600,34000,300,300,CONT_VIA,645nymous_ +B 12400,24000,300,300,CONT_DIF_N,538nymous_ +B 6600,31000,300,300,CONT_VIA2,699nymous_ +B 4400,6000,300,300,CONT_VIA2,753nymous_ +B 38200,24400,300,300,CONT_BODY_N,807nymous_ +B 36800,16000,300,300,CONT_BODY_N,861nymous_ +B 34800,35000,300,300,CONT_VIA2,915nymous_ +B 25000,32400,300,300,CONT_DIF_P,1237ymous_ +B 33800,25000,300,300,CONT_VIA,969nymous_ +B 3200,9000,300,300,CONT_BODY_P,1023ymous_ +B 23000,28400,300,300,CONT_BODY_N,1291ymous_ +B 16400,9000,300,300,CONT_DIF_N,431nymous_ +B 17800,36400,300,300,CONT_DIF_N,377nymous_ +B 9200,10000,300,300,CONT_POLY,592nymous_ +B 30600,29000,300,300,CONT_DIF_P,1077ymous_ +B 2800,33000,300,300,CONT_DIF_N,1131ymous_ +B 5000,19000,8300,2300,CONT_VIA2,1345ymous_ +B 12400,23000,300,300,CONT_DIF_N,539nymous_ +B 14600,19200,300,300,CONT_BODY_P,485nymous_ +B 7600,34000,300,300,CONT_DIF_N,646nymous_ +B 6600,30000,300,300,CONT_VIA2,700nymous_ +B 4400,6000,300,300,CONT_VIA,754nymous_ +B 38200,23400,300,300,CONT_BODY_N,808nymous_ +B 36800,15000,300,300,CONT_VIA2,862nymous_ +B 34800,34000,300,300,CONT_VIA2,916nymous_ +B 27000,27600,300,300,CONT_DIF_P,1183ymous_ +B 27000,26400,300,300,CONT_DIF_P,1184ymous_ +B 27000,31200,300,300,CONT_DIF_P,1180ymous_ +B 27000,30000,300,300,CONT_DIF_P,1181ymous_ +B 33800,25000,300,300,CONT_DIF_P,970nymous_ +B 23000,27400,300,300,CONT_BODY_N,1292ymous_ +B 25000,31200,300,300,CONT_DIF_P,1238ymous_ +B 3200,8000,300,300,CONT_VIA2,1024ymous_ +B 30600,28000,300,300,CONT_VIA2,1078ymous_ +B 16400,8000,300,300,CONT_DIF_N,432nymous_ +B 17800,35200,300,300,CONT_DIF_N,378nymous_ +B 9200,8000,300,300,CONT_VIA2,593nymous_ +B 2800,32000,300,300,CONT_DIF_N,1132ymous_ +B 28200,9000,200,200,CONT_TURN1,1346ymous_ +B 14000,17000,300,300,CONT_VIA2,486nymous_ +B 7600,33000,300,300,CONT_VIA,647nymous_ +B 6600,26000,300,300,CONT_VIA2,701nymous_ +B 4400,6000,300,300,CONT_BODY_P,755nymous_ +B 38200,22400,300,300,CONT_BODY_N,809nymous_ +B 36800,15000,300,300,CONT_BODY_N,863nymous_ +B 27000,25200,300,300,CONT_VIA,1185ymous_ +B 34800,33000,300,300,CONT_VIA2,917nymous_ +B 33800,24000,300,300,CONT_VIA,971nymous_ +B 23000,26400,300,300,CONT_BODY_N,1293ymous_ +B 25000,30000,300,300,CONT_VIA,1239ymous_ +B 17800,34000,300,300,CONT_DIF_N,379nymous_ +B 3200,8000,300,300,CONT_BODY_P,1025ymous_ +B 30600,28000,300,300,CONT_VIA,1079ymous_ +B 22400,8000,200,200,CONT_TURN1,1347ymous_ +B 14000,17000,300,300,CONT_VIA,487nymous_ +B 16400,6000,300,300,CONT_VIA2,433nymous_ +B 9200,8000,300,300,CONT_DIF_N,594nymous_ +B 7600,33000,300,300,CONT_DIF_N,648nymous_ +B 2800,31000,300,300,CONT_DIF_N,1133ymous_ +B 6600,25000,300,300,CONT_VIA2,702nymous_ +B 4400,36000,300,300,CONT_VIA2,756nymous_ +B 38200,21400,300,300,CONT_BODY_N,810nymous_ +B 36800,14000,300,300,CONT_BODY_N,864nymous_ +B 34800,29000,300,300,CONT_VIA2,918nymous_ +B 25000,30000,300,300,CONT_DIF_P,1240ymous_ +B 27000,25200,300,300,CONT_DIF_P,1186ymous_ +B 33800,24000,300,300,CONT_DIF_P,972nymous_ +B 3200,7000,300,300,CONT_VIA2,1026ymous_ +B 23000,25400,300,300,CONT_BODY_N,1294ymous_ +B 17800,32800,300,300,CONT_DIF_N,380nymous_ +B 30600,28000,300,300,CONT_DIF_P,1080ymous_ +B 2800,30000,300,300,CONT_DIF_N,1134ymous_ +B 21200,10000,200,200,CONT_TURN1,1348ymous_ +B 14000,16000,300,300,CONT_BODY_N,488nymous_ +B 16400,6000,300,300,CONT_VIA,434nymous_ +B 9200,7200,300,300,CONT_DIF_N,595nymous_ +B 7600,32000,300,300,CONT_VIA2,649nymous_ +B 6600,24000,300,300,CONT_VIA2,703nymous_ +B 4400,36000,300,300,CONT_VIA,757nymous_ +B 38200,20400,300,300,CONT_BODY_N,811nymous_ +B 36800,13000,300,300,CONT_BODY_N,865nymous_ +B 34800,28000,300,300,CONT_VIA2,919nymous_ +B 25000,28800,300,300,CONT_DIF_P,1241ymous_ +B 27000,24000,300,300,CONT_DIF_P,1187ymous_ +B 33800,23000,300,300,CONT_VIA2,973nymous_ +B 3200,7000,300,300,CONT_BODY_P,1027ymous_ +B 23000,24400,300,300,CONT_BODY_N,1295ymous_ +B 16400,6000,300,300,CONT_BODY_P,435nymous_ +B 17800,31600,300,300,CONT_VIA2,381nymous_ +B 30600,27000,300,300,CONT_VIA2,1081ymous_ +B 11600,17000,300,300,CONT_VIA,542nymous_ +B 9200,7000,300,300,CONT_VIA2,596nymous_ +B 2800,29000,300,300,CONT_DIF_N,1135ymous_ +B 14000,12800,300,300,CONT_DIF_P,489nymous_ +B 7600,32000,300,300,CONT_VIA,650nymous_ +B 6000,36000,300,300,CONT_DIF_N,704nymous_ +B 4400,36000,300,300,CONT_DIF_N,758nymous_ +B 38000,35000,300,300,CONT_VIA2,812nymous_ +B 36800,12000,300,300,CONT_BODY_N,866nymous_ +B 27000,22800,300,300,CONT_DIF_P,1188ymous_ +B 34800,27000,300,300,CONT_VIA2,920nymous_ +B 33800,23000,300,300,CONT_VIA,974nymous_ +B 23000,23400,300,300,CONT_BODY_N,1296ymous_ +B 25000,27600,300,300,CONT_VIA,1242ymous_ +B 3200,6000,300,300,CONT_VIA2,1028ymous_ +B 30600,27000,300,300,CONT_VIA,1082ymous_ +B 1600,19200,300,300,CONT_BODY_P,436nymous_ +B 17800,31600,300,300,CONT_DIF_N,382nymous_ +B 9200,6000,300,300,CONT_VIA2,597nymous_ +B 2800,28000,300,300,CONT_DIF_N,1136ymous_ +B 14000,12000,300,300,CONT_DIF_P,490nymous_ +B 7600,32000,300,300,CONT_DIF_N,651nymous_ +B 6000,35000,300,300,CONT_DIF_N,705nymous_ +B 4400,35000,300,300,CONT_VIA,759nymous_ +B 38000,34000,300,300,CONT_VIA2,813nymous_ +B 36800,11000,300,300,CONT_VIA2,867nymous_ +B 27000,21600,300,300,CONT_DIF_P,1189ymous_ +B 34800,23000,300,300,CONT_VIA2,921nymous_ +B 33800,23000,300,300,CONT_DIF_P,975nymous_ +B 3200,6000,300,300,CONT_VIA,1029ymous_ +B 11600,16000,300,300,CONT_BODY_N,543nymous_ +B 23000,22400,300,300,CONT_BODY_N,1297ymous_ +B 25000,27600,300,300,CONT_DIF_P,1243ymous_ +B 17800,30400,300,300,CONT_VIA2,383nymous_ +B 11600,14800,300,300,CONT_DIF_P,544nymous_ +B 30600,27000,300,300,CONT_DIF_P,1083ymous_ +B 14000,10000,300,300,CONT_POLY,491nymous_ +B 1600,37600,300,300,CONT_BODY_P,437nymous_ +B 9200,6000,300,300,CONT_VIA,598nymous_ +B 7600,31000,300,300,CONT_VIA2,652nymous_ +B 2800,27000,300,300,CONT_DIF_N,1137ymous_ +B 6000,34000,300,300,CONT_DIF_N,706nymous_ +B 4400,35000,300,300,CONT_DIF_N,760nymous_ +B 38000,33000,300,300,CONT_VIA2,814nymous_ +B 36800,10000,300,300,CONT_VIA2,868nymous_ +B 34800,22000,300,300,CONT_VIA2,922nymous_ +B 25000,26400,300,300,CONT_DIF_P,1244ymous_ +B 27000,20400,300,300,CONT_DIF_P,1190ymous_ +B 33800,22000,300,300,CONT_VIA2,976nymous_ +B 3200,6000,300,300,CONT_BODY_P,1030ymous_ +B 23000,21400,300,300,CONT_BODY_N,1298ymous_ +B 17800,30400,300,300,CONT_VIA,384nymous_ +B 11600,13800,300,300,CONT_DIF_P,545nymous_ +B 30600,26000,300,300,CONT_DIF_P,1084ymous_ +B 2800,26000,300,300,CONT_DIF_N,1138ymous_ +B 14000,8000,300,300,CONT_DIF_N,492nymous_ +B 1600,36400,300,300,CONT_BODY_P,438nymous_ +B 9200,6000,300,300,CONT_BODY_P,599nymous_ +B 7600,31000,300,300,CONT_VIA,653nymous_ +B 6000,33000,300,300,CONT_DIF_N,707nymous_ +B 4400,34000,300,300,CONT_VIA,761nymous_ +B 38000,29000,300,300,CONT_VIA2,815nymous_ +B 36800,9000,300,300,CONT_VIA2,869nymous_ +B 34800,20200,300,300,CONT_POLY,923nymous_ +B 25000,25200,300,300,CONT_DIF_P,1245ymous_ +B 2600,19200,300,300,CONT_BODY_P,1191ymous_ +B 33800,22000,300,300,CONT_VIA,977nymous_ +B 32000,19200,300,300,CONT_BODY_N,1031ymous_ +B 23000,20400,300,300,CONT_BODY_N,1299ymous_ +B 1600,35400,300,300,CONT_BODY_P,439nymous_ +B 17800,30400,300,300,CONT_DIF_N,385nymous_ +B 11600,12800,300,300,CONT_DIF_P,546nymous_ +B 9200,36000,300,300,CONT_DIF_N,600nymous_ +B 30600,25000,300,300,CONT_DIF_P,1085ymous_ +B 2800,25000,300,300,CONT_DIF_N,1139ymous_ +B 14000,7200,300,300,CONT_DIF_N,493nymous_ +B 7600,31000,300,300,CONT_DIF_N,654nymous_ +B 6000,32000,300,300,CONT_DIF_N,708nymous_ +B 4400,34000,300,300,CONT_DIF_N,762nymous_ +B 38000,28000,300,300,CONT_VIA2,816nymous_ +B 36800,9000,300,300,CONT_BODY_P,870nymous_ +B 2600,37600,300,300,CONT_BODY_P,1192ymous_ +B 34400,16000,300,300,CONT_BODY_N,924nymous_ +B 33800,22000,300,300,CONT_DIF_P,978nymous_ +B 22400,17000,300,300,CONT_VIA2,1300ymous_ +B 25000,24000,300,300,CONT_DIF_P,1246ymous_ +B 32000,17000,300,300,CONT_VIA2,1032ymous_ +B 30600,24000,300,300,CONT_DIF_P,1086ymous_ +B 1600,34400,300,300,CONT_BODY_P,440nymous_ +B 17800,29200,300,300,CONT_DIF_N,386nymous_ +B 11600,11800,300,300,CONT_DIF_P,547nymous_ +B 9200,35000,300,300,CONT_DIF_N,601nymous_ +B 2800,24000,300,300,CONT_DIF_N,1140ymous_ +B 14000,6000,300,300,CONT_VIA2,494nymous_ +B 7600,30000,300,300,CONT_VIA2,655nymous_ +B 6000,31000,300,300,CONT_DIF_N,709nymous_ +B 4400,33000,300,300,CONT_VIA,763nymous_ +B 38000,27000,300,300,CONT_VIA2,817nymous_ +B 36800,8000,300,300,CONT_BODY_P,871nymous_ +B 26000,19200,300,300,CONT_BODY_N,1193ymous_ +B 34400,14000,300,300,CONT_VIA,925nymous_ +B 33200,17000,300,300,CONT_VIA2,979nymous_ +B 22400,17000,300,300,CONT_VIA,1301ymous_ +B 25000,22800,300,300,CONT_VIA,1247ymous_ +B 17800,28000,300,300,CONT_VIA,387nymous_ +B 11600,9000,300,300,CONT_DIF_N,548nymous_ +B 32000,17000,300,300,CONT_VIA,1033ymous_ +B 30600,23000,300,300,CONT_DIF_P,1087ymous_ +B 14000,6000,300,300,CONT_VIA,495nymous_ +B 1600,33400,300,300,CONT_BODY_P,441nymous_ +B 9200,34000,300,300,CONT_DIF_N,602nymous_ +B 7600,30000,300,300,CONT_VIA,656nymous_ +B 2800,23000,300,300,CONT_DIF_N,1141ymous_ +B 6000,30000,300,300,CONT_DIF_N,710nymous_ +B 4400,33000,300,300,CONT_DIF_N,764nymous_ +B 37200,37600,300,300,CONT_BODY_N,818nymous_ +B 36800,7000,300,300,CONT_BODY_P,872nymous_ +B 34400,14000,300,300,CONT_DIF_P,926nymous_ +B 25000,22800,300,300,CONT_DIF_P,1248ymous_ +B 26000,17000,300,300,CONT_VIA2,1194ymous_ +B 33200,17000,300,300,CONT_VIA,980nymous_ +B 32000,16000,300,300,CONT_BODY_N,1034ymous_ +B 22400,16000,300,300,CONT_BODY_N,1302ymous_ +B 17800,28000,300,300,CONT_DIF_N,388nymous_ +B 11600,8000,300,300,CONT_DIF_N,549nymous_ +B 30600,22000,300,300,CONT_DIF_P,1088ymous_ +B 28000,19200,300,300,CONT_BODY_N,1142ymous_ +B 14000,6000,300,300,CONT_BODY_P,496nymous_ +B 1600,32400,300,300,CONT_BODY_P,442nymous_ +B 9200,33000,300,300,CONT_DIF_N,603nymous_ +B 7600,30000,300,300,CONT_DIF_N,657nymous_ +B 6000,29000,300,300,CONT_DIF_N,711nymous_ +B 4400,32000,300,300,CONT_VIA2,765nymous_ +B 37000,19200,300,300,CONT_BODY_N,819nymous_ +B 36800,6000,300,300,CONT_VIA2,873nymous_ +B 34400,13000,300,300,CONT_VIA,927nymous_ +B 25000,21600,300,300,CONT_DIF_P,1249ymous_ +B 26000,17000,300,300,CONT_VIA,1195ymous_ +B 33200,16000,300,300,CONT_BODY_N,981nymous_ +B 32000,13000,300,300,CONT_DIF_P,1035ymous_ +B 22400,8600,300,300,CONT_DIF_N,1303ymous_ +B 1600,31400,300,300,CONT_BODY_P,443nymous_ +B 17800,26800,300,300,CONT_DIF_N,389nymous_ +B 11600,6000,300,300,CONT_VIA2,550nymous_ +B 9200,32000,300,300,CONT_DIF_N,604nymous_ +B 30400,36600,300,300,CONT_VIA2,1089ymous_ +B 28000,35000,300,300,CONT_DIF_P,1143ymous_ +B 14000,36000,300,300,CONT_DIF_N,497nymous_ +B 7600,29000,300,300,CONT_VIA,658nymous_ +B 6000,28000,300,300,CONT_DIF_N,712nymous_ +B 4400,32000,300,300,CONT_VIA,766nymous_ +B 37000,36000,300,300,CONT_VIA,820nymous_ +B 36800,6000,300,300,CONT_VIA,874nymous_ +B 26000,16000,300,300,CONT_BODY_N,1196ymous_ +B 34400,13000,300,300,CONT_DIF_P,928nymous_ +B 33200,14000,300,300,CONT_DIF_P,982nymous_ +B 22400,6000,300,300,CONT_VIA2,1304ymous_ +B 25000,20400,300,300,CONT_VIA,1250ymous_ +B 32000,8000,300,300,CONT_DIF_N,1036ymous_ +B 30400,36600,300,300,CONT_VIA,1090ymous_ +B 1600,30400,300,300,CONT_BODY_P,444nymous_ +B 17800,25600,300,300,CONT_VIA2,390nymous_ +B 11600,6000,300,300,CONT_VIA,551nymous_ +B 9200,31000,300,300,CONT_DIF_N,605nymous_ +B 28000,33600,300,300,CONT_DIF_P,1144ymous_ +B 14000,35000,300,300,CONT_DIF_N,498nymous_ +B 7600,29000,300,300,CONT_DIF_N,659nymous_ +B 6000,27000,300,300,CONT_DIF_N,713nymous_ +B 4400,32000,300,300,CONT_DIF_N,767nymous_ +B 37000,36000,300,300,CONT_DIF_P,821nymous_ +B 36800,6000,300,300,CONT_BODY_P,875nymous_ +B 26000,14000,300,300,CONT_VIA2,1197ymous_ +B 34400,8000,300,300,CONT_DIF_N,929nymous_ +B 33200,13000,300,300,CONT_DIF_P,983nymous_ +B 22400,6000,300,300,CONT_VIA,1305ymous_ +B 25000,20400,300,300,CONT_DIF_P,1251ymous_ +B 17800,25600,300,300,CONT_VIA,391nymous_ +B 11600,6000,300,300,CONT_BODY_P,552nymous_ +B 32000,6000,300,300,CONT_VIA2,1037ymous_ +B 30400,36600,300,300,CONT_POLY,1091ymous_ +B 14000,34000,300,300,CONT_DIF_N,499nymous_ +B 28000,32400,300,300,CONT_DIF_P,1145ymous_ +B 1600,29400,300,300,CONT_BODY_P,445nymous_ +B 9200,30000,300,300,CONT_DIF_N,606nymous_ +B 7600,28000,300,300,CONT_VIA,660nymous_ +B 6000,26000,300,300,CONT_DIF_N,714nymous_ +B 4400,31000,300,300,CONT_VIA2,768nymous_ +B 37000,35000,300,300,CONT_VIA2,822nymous_ +B 3600,19200,300,300,CONT_BODY_P,876nymous_ +B 34400,6000,300,300,CONT_VIA2,930nymous_ +B 24800,16000,300,300,CONT_BODY_N,1252ymous_ +B 26000,14000,300,300,CONT_DIF_P,1198ymous_ +B 33200,8000,300,300,CONT_DIF_N,984nymous_ +B 32000,6000,300,300,CONT_VIA,1038ymous_ +B 22400,6000,300,300,CONT_BODY_P,1306ymous_ +B 17800,25600,300,300,CONT_DIF_N,392nymous_ +B 10800,36000,300,300,CONT_DIF_N,553nymous_ +B 30000,19200,300,300,CONT_BODY_N,1092ymous_ +B 28000,31200,300,300,CONT_VIA,1146ymous_ +B 14000,33000,300,300,CONT_DIF_N,500nymous_ +B 1600,28400,300,300,CONT_BODY_P,446nymous_ +B 9200,29000,300,300,CONT_DIF_N,607nymous_ +B 7600,28000,300,300,CONT_DIF_N,661nymous_ +B 6000,25000,300,300,CONT_DIF_N,715nymous_ +B 4400,31000,300,300,CONT_VIA,769nymous_ +B 37000,35000,300,300,CONT_VIA,823nymous_ +B 3600,37600,300,300,CONT_VIA2,877nymous_ +B 34400,6000,300,300,CONT_VIA,931nymous_ +B 24800,14000,300,300,CONT_VIA,1253ymous_ +B 26000,13000,300,300,CONT_VIA2,1199ymous_ +B 33200,6000,300,300,CONT_VIA2,985nymous_ +B 32000,6000,300,300,CONT_BODY_P,1039ymous_ +B 30000,20200,300,300,CONT_VIA,1093ymous_ +B 22000,19200,300,300,CONT_VIA,1307ymous_ +B 1600,27400,300,300,CONT_BODY_P,447nymous_ +B 17800,24400,300,300,CONT_VIA2,393nymous_ +B 10800,35000,300,300,CONT_DIF_N,554nymous_ +B 9200,28000,300,300,CONT_DIF_N,608nymous_ +B 28000,31200,300,300,CONT_DIF_P,1147ymous_ +B 14000,32000,300,300,CONT_DIF_N,501nymous_ +B 7600,27000,300,300,CONT_VIA,662nymous_ +B 6000,24000,300,300,CONT_DIF_N,716nymous_ +B 4400,31000,300,300,CONT_DIF_N,770nymous_ +B 37000,35000,300,300,CONT_DIF_P,824nymous_ +B 3600,37600,300,300,CONT_VIA,878nymous_ +B 26000,13000,300,300,CONT_DIF_P,1200ymous_ +B 34400,6000,300,300,CONT_BODY_P,932nymous_ +B 33200,6000,300,300,CONT_VIA,986nymous_ +B 22000,22200,300,300,CONT_VIA,1308ymous_ +B 24800,14000,300,300,CONT_DIF_P,1254ymous_ +B 31800,12200,300,300,CONT_POLY,1040ymous_ +B 29600,17000,300,300,CONT_VIA2,1094ymous_ +B 1600,26400,300,300,CONT_BODY_P,448nymous_ +B 17800,24400,300,300,CONT_DIF_N,394nymous_ +B 10800,34000,300,300,CONT_DIF_N,555nymous_ +B 9200,27000,300,300,CONT_DIF_N,609nymous_ +B 28000,30000,300,300,CONT_DIF_P,1148ymous_ +B 14000,31000,300,300,CONT_DIF_N,502nymous_ +B 7600,27000,300,300,CONT_DIF_N,663nymous_ +B 6000,23000,300,300,CONT_DIF_N,717nymous_ +B 4400,30000,300,300,CONT_VIA2,771nymous_ +B 37000,34000,300,300,CONT_VIA2,825nymous_ +B 3600,37600,300,300,CONT_BODY_P,879nymous_ +B 26000,12000,300,300,CONT_VIA2,1201ymous_ +B 3400,36000,300,300,CONT_VIA2,933nymous_ +B 33200,6000,300,300,CONT_BODY_P,987nymous_ +B 21200,16000,300,300,CONT_BODY_N,1309ymous_ +B 24800,13000,300,300,CONT_VIA,1255ymous_ +B 17800,23200,300,300,CONT_VIA,395nymous_ +B 10800,33000,300,300,CONT_DIF_N,556nymous_ +B 31800,9000,300,300,CONT_POLY,1041ymous_ +B 29600,17000,300,300,CONT_VIA,1095ymous_ +B 14000,30000,300,300,CONT_DIF_N,503nymous_ +B 1600,25400,300,300,CONT_BODY_P,449nymous_ +B 9200,26000,300,300,CONT_DIF_N,610nymous_ +B 7600,26000,300,300,CONT_VIA2,664nymous_ +B 28000,28800,300,300,CONT_DIF_P,1149ymous_ +B 5600,19200,300,300,CONT_BODY_P,718nymous_ +B 4400,30000,300,300,CONT_VIA,772nymous_ +B 37000,34000,300,300,CONT_VIA,826nymous_ +B 36000,19200,300,300,CONT_BODY_N,880nymous_ +B 3400,32000,300,300,CONT_VIA2,934nymous_ +B 24800,13000,300,300,CONT_DIF_P,1256ymous_ +B 26000,8000,300,300,CONT_DIF_N,1202ymous_ +B 33000,19200,300,300,CONT_BODY_N,988nymous_ +B 31600,35000,300,300,CONT_VIA2,1042ymous_ +B 21200,9000,300,300,CONT_DIF_N,1310ymous_ +B 17800,23200,300,300,CONT_DIF_N,396nymous_ +B 10800,32000,300,300,CONT_DIF_N,557nymous_ +B 29600,16000,300,300,CONT_VIA,1096ymous_ +B 28000,27600,300,300,CONT_DIF_P,1150ymous_ +B 14000,29000,300,300,CONT_DIF_N,504nymous_ +B 1600,24400,300,300,CONT_BODY_P,450nymous_ +B 9200,25000,300,300,CONT_DIF_N,611nymous_ +B 7600,26000,300,300,CONT_VIA,665nymous_ +B 5600,17000,300,300,CONT_VIA2,719nymous_ +B 4400,30000,300,300,CONT_DIF_N,773nymous_ +B 37000,34000,300,300,CONT_DIF_P,827nymous_ +B 36000,35000,300,300,CONT_VIA2,881nymous_ +B 3400,31000,300,300,CONT_VIA2,935nymous_ +B 24800,8000,300,300,CONT_DIF_N,1257ymous_ +B 26000,6000,300,300,CONT_VIA2,1203ymous_ +B 32800,35000,300,300,CONT_VIA2,989nymous_ +B 31600,34000,300,300,CONT_VIA2,1043ymous_ +B 21200,6000,300,300,CONT_VIA2,1311ymous_ +B 1600,23400,300,300,CONT_BODY_P,451nymous_ +B 17600,19200,300,300,CONT_BODY_P,397nymous_ +B 10800,31000,300,300,CONT_DIF_N,558nymous_ +B 9200,24000,300,300,CONT_DIF_N,612nymous_ +B 29600,16000,300,300,CONT_BODY_N,1097ymous_ +B 28000,26400,300,300,CONT_DIF_P,1151ymous_ +B 14000,28000,300,300,CONT_DIF_N,505nymous_ +B 7600,26000,300,300,CONT_DIF_N,666nymous_ +B 5600,17000,300,300,CONT_VIA,720nymous_ +B 4400,29000,300,300,CONT_VIA,774nymous_ +B 37000,33000,300,300,CONT_VIA2,828nymous_ +B 36000,34000,300,300,CONT_VIA2,882nymous_ +B 26000,6000,300,300,CONT_VIA,1204ymous_ +B 3400,30000,300,300,CONT_VIA2,936nymous_ +B 32800,34000,300,300,CONT_VIA2,990nymous_ +B 21200,6000,300,300,CONT_VIA,1312ymous_ +B 24800,6000,300,300,CONT_VIA2,1258ymous_ +B 31600,33000,300,300,CONT_VIA2,1044ymous_ +B 29600,14000,300,300,CONT_DIF_P,1098ymous_ +B 3400,25000,300,300,CONT_VIA2,938nymous_ +B 36000,29000,300,300,CONT_VIA2,884nymous_ +B 37000,33000,300,300,CONT_DIF_P,830nymous_ +B 4400,28000,300,300,CONT_VIA,776nymous_ +B 5600,13800,300,300,CONT_DIF_P,722nymous_ +B 28000,24000,300,300,CONT_DIF_P,1153ymous_ +B 7600,25000,300,300,CONT_VIA,668nymous_ +B 8800,37600,300,300,CONT_VIA2,614nymous_ +B 1600,21400,300,300,CONT_BODY_P,453nymous_ +B 14000,26000,300,300,CONT_DIF_N,507nymous_ +B 29600,13000,300,300,CONT_DIF_P,1099ymous_ +B 31600,29000,300,300,CONT_VIA2,1045ymous_ +B 10800,29000,300,300,CONT_DIF_N,560nymous_ +B 17600,17000,300,300,CONT_VIA,399nymous_ +B 24800,6000,300,300,CONT_VIA,1259ymous_ +B 21200,6000,300,300,CONT_BODY_P,1313ymous_ +B 32800,33000,300,300,CONT_VIA2,991nymous_ +B 3400,26000,300,300,CONT_VIA2,937nymous_ +B 26000,6000,300,300,CONT_BODY_P,1205ymous_ +B 1600,22400,300,300,CONT_BODY_P,452nymous_ +B 17600,17000,300,300,CONT_VIA2,398nymous_ +B 10800,30000,300,300,CONT_DIF_N,559nymous_ +B 9200,23000,300,300,CONT_DIF_N,613nymous_ +B 28000,25200,300,300,CONT_DIF_P,1152ymous_ +B 14000,27000,300,300,CONT_DIF_N,506nymous_ +B 7600,25000,300,300,CONT_VIA2,667nymous_ +B 5600,16000,300,300,CONT_BODY_N,721nymous_ +B 4400,29000,300,300,CONT_DIF_N,775nymous_ +B 37000,33000,300,300,CONT_VIA,829nymous_ +B 36000,33000,300,300,CONT_VIA2,883nymous_ +B 28000,21600,300,300,CONT_DIF_P,1155ymous_ +B 29600,10600,300,300,CONT_POLY,1101ymous_ +B 8800,37600,300,300,CONT_BODY_P,616nymous_ +B 10800,27000,300,300,CONT_DIF_N,562nymous_ +B 17600,12800,300,300,CONT_DIF_P,401nymous_ +B 15800,37600,300,300,CONT_BODY_P,455nymous_ +B 20800,37600,300,300,CONT_BODY_P,1315ymous_ +B 31600,27000,300,300,CONT_VIA2,1047ymous_ +B 32800,28000,300,300,CONT_VIA2,993nymous_ +B 26000,36400,300,300,CONT_DIF_P,1207ymous_ +B 24000,19200,300,300,CONT_BODY_N,1261ymous_ +B 3400,24000,300,300,CONT_VIA2,939nymous_ +B 36000,28000,300,300,CONT_VIA2,885nymous_ +B 37000,32000,300,300,CONT_VIA,831nymous_ +B 4400,28000,300,300,CONT_DIF_N,777nymous_ +B 5600,12800,300,300,CONT_DIF_P,723nymous_ +B 7600,25000,300,300,CONT_DIF_N,669nymous_ +B 8800,37600,300,300,CONT_VIA,615nymous_ +B 1600,20400,300,300,CONT_BODY_P,454nymous_ +B 14000,25000,300,300,CONT_DIF_N,508nymous_ +B 28000,22800,300,300,CONT_DIF_P,1154ymous_ +B 29600,10600,300,300,CONT_VIA,1100ymous_ +B 10800,28000,300,300,CONT_DIF_N,561nymous_ +B 17600,16000,300,300,CONT_BODY_N,400nymous_ +B 20800,19200,300,300,CONT_BODY_P,1314ymous_ +B 31600,28000,300,300,CONT_VIA2,1046ymous_ +B 32800,29000,300,300,CONT_VIA2,992nymous_ +B 26000,37600,300,300,CONT_BODY_N,1206ymous_ +B 24800,6000,300,300,CONT_BODY_P,1260ymous_ +B 5600,37600,300,300,CONT_VIA,731nymous_ +B 31600,22000,300,300,CONT_VIA2,1049ymous_ +B 24000,35800,300,300,CONT_VIA,1263ymous_ +B 20800,35400,300,300,CONT_BODY_P,1317ymous_ +B 32800,23000,300,300,CONT_VIA2,995nymous_ +B 33800,36000,300,300,CONT_VIA,941nymous_ +B 26000,33600,300,300,CONT_VIA,1209ymous_ +B 36000,23000,300,300,CONT_VIA2,887nymous_ +B 37000,31000,300,300,CONT_VIA,833nymous_ +B 4400,27000,300,300,CONT_DIF_N,779nymous_ +B 5600,9000,300,300,CONT_DIF_N,725nymous_ +B 7600,24000,300,300,CONT_VIA,671nymous_ +B 14000,23000,300,300,CONT_DIF_N,510nymous_ +B 28000,20400,300,300,CONT_DIF_P,1156ymous_ +B 8600,19200,300,300,CONT_BODY_P,617nymous_ +B 10800,26000,300,300,CONT_DIF_N,563nymous_ +B 17600,8600,300,300,CONT_DIF_N,402nymous_ +B 15800,29000,300,300,CONT_VIA2,456nymous_ +B 29600,7000,300,300,CONT_DIF_N,1102ymous_ +B 31600,23000,300,300,CONT_VIA2,1048ymous_ +B 24000,37600,300,300,CONT_BODY_N,1262ymous_ +B 20800,36400,300,300,CONT_BODY_P,1316ymous_ +B 32800,27000,300,300,CONT_VIA2,994nymous_ +B 34000,19200,300,300,CONT_BODY_N,940nymous_ +B 26000,35000,300,300,CONT_DIF_P,1208ymous_ +B 36000,27000,300,300,CONT_VIA2,886nymous_ +B 37000,32000,300,300,CONT_DIF_P,832nymous_ +B 4400,27000,300,300,CONT_VIA,778nymous_ +B 5600,11800,300,300,CONT_DIF_P,724nymous_ +B 7600,24000,300,300,CONT_VIA2,670nymous_ +B 14000,24000,300,300,CONT_DIF_N,509nymous_ +B 27000,36400,300,300,CONT_VIA,1175ymous_ +B 37000,30000,300,300,CONT_VIA,835nymous_ +B 4400,26000,300,300,CONT_VIA,781nymous_ +B 5600,6000,300,300,CONT_VIA2,727nymous_ +B 7600,23000,300,300,CONT_VIA,673nymous_ +B 8600,32000,300,300,CONT_VIA2,619nymous_ +B 15800,27000,300,300,CONT_VIA2,458nymous_ +B 14000,21800,300,300,CONT_VIA,512nymous_ +B 28000,0,300,300,CONT_VIA3,1158ymous_ +B 29600,34000,300,300,CONT_VIA2,1104ymous_ +B 10800,24000,300,300,CONT_DIF_N,565nymous_ +B 17600,6000,300,300,CONT_VIA,404nymous_ +B 20800,34400,300,300,CONT_BODY_P,1318ymous_ +B 31600,20200,300,300,CONT_POLY,1050ymous_ +B 32800,22000,300,300,CONT_VIA2,996nymous_ +B 26000,33600,300,300,CONT_DIF_P,1210ymous_ +B 24000,35800,300,300,CONT_POLY,1264ymous_ +B 33800,36000,300,300,CONT_DIF_P,942nymous_ +B 36000,22000,300,300,CONT_VIA2,888nymous_ +B 37000,31000,300,300,CONT_DIF_P,834nymous_ +B 4400,26000,300,300,CONT_VIA2,780nymous_ +B 5600,8000,300,300,CONT_DIF_N,726nymous_ +B 28000,0,300,300,CONT_VIA4,1157ymous_ +B 7600,24000,300,300,CONT_DIF_N,672nymous_ +B 8600,36000,300,300,CONT_VIA2,618nymous_ +B 15800,28000,300,300,CONT_VIA2,457nymous_ +B 14000,21800,300,300,CONT_VIA2,511nymous_ +B 29600,35000,300,300,CONT_VIA2,1103ymous_ +B 10800,25000,300,300,CONT_DIF_N,564nymous_ +B 17600,6000,300,300,CONT_VIA2,403nymous_ +B 11600,17000,300,300,CONT_VIA2,541nymous_ +B 18800,6000,300,300,CONT_VIA,354nymous_ +B 18800,6000,300,300,CONT_BODY_P,355nymous_ +B 13600,19200,300,300,CONT_BODY_P,514nymous_ +B 27800,37600,300,300,CONT_BODY_N,1160ymous_ +B 8600,30000,300,300,CONT_VIA2,621nymous_ +B 10800,21800,300,300,CONT_VIA2,567nymous_ +B 17400,11800,300,300,CONT_POLY,406nymous_ +B 15600,36000,300,300,CONT_DIF_N,460nymous_ +B 29000,19200,300,300,CONT_BODY_N,1106ymous_ +B 30800,17000,300,300,CONT_VIA2,1052ymous_ +B 24000,34200,300,300,CONT_VIA,1266ymous_ +B 20800,32400,300,300,CONT_BODY_P,1320ymous_ +B 32200,36000,300,300,CONT_DIF_P,998nymous_ +B 33800,35000,300,300,CONT_VIA,944nymous_ +B 26000,31200,300,300,CONT_VIA,1212ymous_ +B 35600,17000,300,300,CONT_VIA2,890nymous_ +B 37000,30000,300,300,CONT_DIF_P,836nymous_ +B 4400,26000,300,300,CONT_DIF_N,782nymous_ +B 5600,6000,300,300,CONT_VIA,728nymous_ +B 7600,23000,300,300,CONT_DIF_N,674nymous_ +B 14000,21800,300,300,CONT_POLY,513nymous_ +B 28000,0,300,300,CONT_VIA2,1159ymous_ +B 29600,33000,300,300,CONT_VIA2,1105ymous_ +B 8600,31000,300,300,CONT_VIA2,620nymous_ +B 10800,23000,300,300,CONT_DIF_N,566nymous_ +B 17600,6000,300,300,CONT_BODY_P,405nymous_ +B 15600,19200,300,300,CONT_BODY_P,459nymous_ +B 20800,33400,300,300,CONT_BODY_P,1319ymous_ +B 31000,19200,300,300,CONT_BODY_N,1051ymous_ +B 32800,20200,300,300,CONT_POLY,997nymous_ +B 26000,32400,300,300,CONT_DIF_P,1211ymous_ +B 24000,34200,300,300,CONT_VIA2,1265ymous_ +B 33800,35000,300,300,CONT_VIA2,943nymous_ +B 36000,20200,300,300,CONT_POLY,889nymous_ +B 33800,35000,300,300,CONT_DIF_P,945nymous_ +B 26000,31200,300,300,CONT_DIF_P,1213ymous_ +B 35600,17000,300,300,CONT_VIA,891nymous_ +B 37000,29000,300,300,CONT_VIA2,837nymous_ +B 4400,25000,300,300,CONT_VIA2,783nymous_ +B 5600,6000,300,300,CONT_BODY_P,729nymous_ +B 7600,21800,300,300,CONT_VIA,675nymous_ +B 32200,35000,300,300,CONT_DIF_P,999nymous_ +B 20800,31400,300,300,CONT_BODY_P,1321ymous_ +B 24000,34200,300,300,CONT_POLY,1267ymous_ +B 16800,37600,300,300,CONT_BODY_P,407nymous_ +B 10800,21800,300,300,CONT_VIA,568nymous_ +B 30800,17000,300,300,CONT_VIA,1053ymous_ +B 29000,33000,300,300,CONT_POLY,1107ymous_ +B 12800,17000,300,300,CONT_VIA2,515nymous_ +B 15600,35000,300,300,CONT_DIF_N,461nymous_ +B 8600,26000,300,300,CONT_VIA2,622nymous_ +B 7600,21800,300,300,CONT_POLY,676nymous_ +B 27800,36400,300,300,CONT_DIF_P,1161ymous_ +B 5600,37600,300,300,CONT_VIA2,730nymous_ +B 4400,25000,300,300,CONT_VIA,784nymous_ +B 37000,29000,300,300,CONT_VIA,838nymous_ +B 35600,16000,300,300,CONT_BODY_N,892nymous_ +B 33800,34000,300,300,CONT_VIA2,946nymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/po_mpx.vbe b/pdks/symbolic/mpxlib/cells/po_mpx.vbe new file mode 100644 index 000000000..91d5df8ff --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/po_mpx.vbe @@ -0,0 +1,29 @@ +ENTITY po_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_i : NATURAL := 191; + CONSTANT tpll_i : NATURAL := 2176; + CONSTANT rdown_i : NATURAL := 15; + CONSTANT tphh_i : NATURAL := 2032; + CONSTANT rup_i : NATURAL := 16 + ); + PORT ( + i : in BIT; + pad : out BIT; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END po_mpx; + +ARCHITECTURE behaviour_data_flow OF po_mpx IS + +BEGIN + pad <= i; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on po_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/pot_mpx.ap b/pdks/symbolic/mpxlib/cells/pot_mpx.ap new file mode 100644 index 000000000..5c28f47c5 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pot_mpx.ap @@ -0,0 +1,1550 @@ +V ALLIANCE : 6 +H pot_mpx,P,17/9/2014,100 +A 0,0,40000,80000 +I 0,40000,padreal_mpx,padreal,NOSYM +S 28800,9000,29000,9000,200,i,RIGHT,POLY +S 28000,-150,28000,10750,600,i,UP,ALU2 +S 28000,0,28000,0,400,i,RIGHT,CALU5 +S 28000,0,28000,0,400,i,RIGHT,CALU4 +S 27850,0,28150,0,600,i,RIGHT,CALU3 +S 27850,0,28150,0,600,i,RIGHT,CALU2 +S 27800,11800,28200,11800,200,i,RIGHT,POLY +S 30000,50,30000,10750,600,b,UP,ALU2 +S 30000,0,30000,0,400,b,RIGHT,CALU5 +S 30000,0,30000,0,400,b,RIGHT,CALU4 +S 29850,0,30150,0,600,b,RIGHT,CALU3 +S 29850,0,30150,0,600,b,RIGHT,CALU2 +S 29600,9800,29600,11400,200,b,UP,POLY +S 29000,35100,29000,39700,400,pad,UP,ALU1 +S 29000,25900,29000,34900,400,pad,UP,ALU1 +S 28600,33000,29000,33000,600,pad,RIGHT,POLY +S 28600,31800,29000,31800,600,pad,RIGHT,POLY +S 28600,30600,29000,30600,600,pad,RIGHT,POLY +S 28600,25800,29000,25800,600,pad,RIGHT,POLY +S 20000,48100,20000,71900,24400,pad,UP,CALU1 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +S 16800,33400,17200,33400,200,vdde,RIGHT,POLY +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 3600,22200,5200,22200,200,vdde,RIGHT,POLY +S 16800,32200,17200,32200,200,vdde,RIGHT,POLY +S 24000,34200,24400,34200,600,vdde,RIGHT,POLY +S 16800,35800,17200,35800,200,vdde,RIGHT,POLY +S 16800,34600,17200,34600,200,vdde,RIGHT,POLY +S 16800,30050,16800,38150,600,vdde,UP,ALU2 +S 10650,21800,14150,21800,600,vdde,RIGHT,ALU2 +S 25100,24000,27900,24000,400,vdde,RIGHT,ALU1 +S 25100,26400,27900,26400,400,vdde,RIGHT,ALU1 +S 25100,28800,27900,28800,400,vdde,RIGHT,ALU1 +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 6800,22200,8400,22200,200,vdde,RIGHT,POLY +S 25100,21600,27900,21600,400,vdde,RIGHT,ALU1 +S 24000,35800,24400,35800,600,vdde,RIGHT,POLY +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 3100,16000,36900,16000,2400,vddi,RIGHT,ALU1 +S 20000,9600,20000,11000,200,vddi,UP,POLY +S 17800,23050,17800,31750,600,vsse,UP,ALU2 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 7600,22900,7600,37500,400,vsse,UP,ALU1 +S 4400,22900,4400,37500,400,vsse,UP,ALU1 +S 30250,36600,30550,36600,600,vsse,RIGHT,ALU2 +S 30400,36400,30400,36600,200,vsse,UP,POLY +S 20800,22900,20800,37100,400,vsse,UP,ALU1 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 3100,6000,36900,6000,2400,vssi,RIGHT,ALU1 +S 17500,22600,19100,22600,200,n6d,RIGHT,NTRANS +S 28500,8000,30700,8000,400,93onymous_,RIGHT,ALU1 +S 28400,7500,28400,8100,620,92onymous_,UP,NDIF +S 7450,21800,9950,21800,600,211nymous_,RIGHT,ALU2 +S 31850,6000,36950,6000,600,127nymous_,RIGHT,ALU2 +S 28300,9000,28700,9000,400,91onymous_,RIGHT,ALU1 +S 10800,22900,10800,39700,400,249nymous_,UP,ALU1 +S 35600,200,35600,12000,9000,11onymous_,UP,TALU5 +S 17700,8000,22300,8000,400,321nymous_,RIGHT,ALU1 +S 15800,9600,15800,10800,200,285nymous_,UP,POLY +S 24900,30000,28100,30000,420,52onymous_,RIGHT,PDIF +S 24900,31200,28100,31200,420,53onymous_,RIGHT,PDIF +S 0,6000,40000,6000,12000,12onymous_,RIGHT,TALU6 +S 35600,13100,35600,15900,400,169nymous_,UP,ALU1 +S 10800,22700,10800,36500,620,248nymous_,UP,NDIF +S 1700,37600,9500,37600,400,286nymous_,RIGHT,ALU1 +S 20000,40100,20000,59900,4400,13onymous_,UP,ALU1 +S 31800,12000,31800,12200,200,126nymous_,UP,POLY +S 7600,21800,7600,22200,600,210nymous_,UP,POLY +S 17700,36400,18900,36400,620,320nymous_,RIGHT,NDIF +S 24900,28800,28100,28800,420,51onymous_,RIGHT,PDIF +S 29000,200,29000,12000,0,10onymous_,UP,TALU5 +S 17700,35200,18900,35200,620,319nymous_,RIGHT,NDIF +S 17700,34000,18900,34000,620,318nymous_,RIGHT,NDIF +S 35000,12700,35000,14700,200,p5b,UP,PTRANS +S 27800,12500,27800,14500,200,p1,UP,PTRANS +S 35000,7300,35000,8300,200,n5b,UP,NTRANS +S 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38200,33400,300,300,CONT_BODY_N,896nymous_ +B 15200,16000,300,300,CONT_BODY_N,1218ymous_ +B 4400,17000,300,300,CONT_VIA2,950nymous_ +B 6800,6000,300,300,CONT_VIA2,1004ymous_ +B 18800,26800,300,300,CONT_VIA,1326ymous_ +B 16800,23400,300,300,CONT_POLY,1272ymous_ +B 20000,11000,300,300,CONT_POLY,358nymous_ +B 7800,37600,300,300,CONT_VIA2,1058ymous_ +B 10400,6000,300,300,CONT_BODY_P,1112ymous_ +B 26000,22800,300,300,CONT_DIF_P,466nymous_ +B 23400,17000,300,300,CONT_VIA,412nymous_ +B 28800,9000,300,300,CONT_POLY,573nymous_ +B 30600,33000,300,300,CONT_VIA,627nymous_ +B 12400,34000,300,300,CONT_DIF_N,1166ymous_ +B 27000,10000,300,300,CONT_VIA2,520nymous_ +B 3200,17000,300,300,CONT_VIA2,681nymous_ +B 33800,29000,300,300,CONT_VIA,735nymous_ +B 35400,30000,300,300,CONT_DIF_P,789nymous_ +B 37000,24000,300,300,CONT_DIF_P,843nymous_ +B 38200,34400,300,300,CONT_BODY_N,897nymous_ +B 15200,17000,300,300,CONT_VIA,1219ymous_ +B 4600,37600,300,300,CONT_BODY_P,951nymous_ +B 6800,7200,300,300,CONT_DIF_N,1005ymous_ +B 16800,24400,300,300,CONT_VIA,1273ymous_ +B 20000,16000,300,300,CONT_BODY_N,359nymous_ +B 26000,21600,300,300,CONT_VIA2,465nymous_ +B 30600,33000,300,300,CONT_DIF_P,626nymous_ +B 27000,9000,300,300,CONT_VIA2,519nymous_ +B 3200,17000,300,300,CONT_VIA,680nymous_ +B 33800,29000,300,300,CONT_DIF_P,734nymous_ +B 35400,29000,300,300,CONT_DIF_P,788nymous_ +B 18800,28000,300,300,CONT_DIF_N,1327ymous_ +B 23400,17000,300,300,CONT_VIA2,413nymous_ +B 29000,21000,300,300,CONT_POLY,574nymous_ +B 8000,8000,300,300,CONT_DIF_N,1059ymous_ +B 10400,6000,300,300,CONT_VIA,1113ymous_ +B 27000,11000,300,300,CONT_VIA2,521nymous_ +B 26000,22800,300,300,CONT_VIA2,467nymous_ +B 30600,33000,300,300,CONT_VIA2,628nymous_ +B 32200,22000,300,300,CONT_DIF_P,682nymous_ +B 33800,29000,300,300,CONT_VIA2,736nymous_ +B 12400,35000,300,300,CONT_DIF_N,1167ymous_ +B 35400,31000,300,300,CONT_DIF_P,790nymous_ +B 37000,24000,300,300,CONT_VIA,844nymous_ +B 38200,35400,300,300,CONT_BODY_N,898nymous_ +B 4600,37600,300,300,CONT_VIA,952nymous_ +B 16800,25400,300,300,CONT_POLY,1274ymous_ +B 15200,17000,300,300,CONT_VIA2,1220ymous_ +B 6800,8000,300,300,CONT_DIF_N,1006ymous_ +B 8000,9000,300,300,CONT_DIF_N,1060ymous_ +B 18800,29200,300,300,CONT_DIF_N,1328ymous_ +B 23600,6000,300,300,CONT_BODY_P,414nymous_ +B 20800,20400,300,300,CONT_BODY_P,360nymous_ +B 29000,21000,300,300,CONT_VIA,575nymous_ +B 10400,6000,300,300,CONT_VIA2,1114ymous_ +B 12400,36000,300,300,CONT_DIF_N,1168ymous_ +B 27000,19200,300,300,CONT_BODY_N,522nymous_ +B 26000,24000,300,300,CONT_DIF_P,468nymous_ +B 30600,34000,300,300,CONT_DIF_P,629nymous_ +B 32200,23000,300,300,CONT_DIF_P,683nymous_ +B 33800,30000,300,300,CONT_DIF_P,737nymous_ +B 35400,32000,300,300,CONT_DIF_P,791nymous_ +B 37000,25000,300,300,CONT_DIF_P,845nymous_ +B 38200,36400,300,300,CONT_BODY_N,899nymous_ +B 4600,37600,300,300,CONT_VIA2,953nymous_ +B 16800,28200,300,300,CONT_POLY,1275ymous_ +B 15600,23000,300,300,CONT_DIF_N,1221ymous_ +B 20800,21400,300,300,CONT_BODY_P,361nymous_ +B 6800,10000,300,300,CONT_POLY,1007ymous_ +B 8000,9000,300,300,CONT_VIA,1061ymous_ +B 18800,30400,300,300,CONT_DIF_N,1329ymous_ +B 26000,24000,300,300,CONT_VIA,469nymous_ +B 23600,6000,300,300,CONT_VIA,415nymous_ +B 29000,22200,300,300,CONT_POLY,576nymous_ +B 30600,34000,300,300,CONT_VIA,630nymous_ +B 10400,8000,300,300,CONT_DIF_N,1115ymous_ +B 12600,19200,300,300,CONT_BODY_P,1169ymous_ +B 27200,6000,300,300,CONT_BODY_P,523nymous_ +B 32200,24000,300,300,CONT_DIF_P,684nymous_ +B 33800,30000,300,300,CONT_VIA,738nymous_ +B 35400,33000,300,300,CONT_DIF_P,792nymous_ +B 37000,25000,300,300,CONT_VIA,846nymous_ +B 38200,37600,300,300,CONT_BODY_N,900nymous_ +B 15600,24000,300,300,CONT_DIF_N,1222ymous_ +B 4600,19200,300,300,CONT_BODY_P,954nymous_ +B 6800,12000,300,300,CONT_DIF_P,1008ymous_ +B 18800,31600,300,300,CONT_DIF_N,1330ymous_ +B 16800,29200,300,300,CONT_VIA,1276ymous_ +B 20800,22400,300,300,CONT_BODY_P,362nymous_ +B 8000,10000,300,300,CONT_POLY,1062ymous_ +B 10400,9000,300,300,CONT_DIF_N,1116ymous_ +B 23600,6000,300,300,CONT_VIA2,416nymous_ +B 29000,22200,300,300,CONT_VIA,577nymous_ +B 12800,6000,300,300,CONT_BODY_P,1170ymous_ +B 27200,8000,300,300,CONT_DIF_N,524nymous_ +B 15600,25000,300,300,CONT_DIF_N,1223ymous_ +B 5400,24000,300,300,CONT_VIA2,955nymous_ +B 6800,12800,300,300,CONT_DIF_P,1009ymous_ +B 18800,31600,300,300,CONT_VIA,1331ymous_ +B 16800,32200,300,300,CONT_POLY,1277ymous_ +B 23600,8000,300,300,CONT_DIF_N,417nymous_ +B 20800,23400,300,300,CONT_BODY_P,363nymous_ +B 29000,23400,300,300,CONT_POLY,578nymous_ +B 8000,11000,300,300,CONT_VIA,1063ymous_ +B 10400,10000,300,300,CONT_POLY,1117ymous_ +B 27200,10600,300,300,CONT_POLY,525nymous_ +B 26000,26400,300,300,CONT_DIF_P,471nymous_ +B 30600,35000,300,300,CONT_DIF_P,632nymous_ +B 32200,26000,300,300,CONT_DIF_P,686nymous_ +B 33800,31000,300,300,CONT_VIA,740nymous_ +B 12800,6000,300,300,CONT_VIA,1171ymous_ +B 35400,35000,300,300,CONT_DIF_P,794nymous_ +B 37000,26000,300,300,CONT_VIA,848nymous_ +B 4400,21800,300,300,CONT_POLY,902nymous_ +B 5400,25000,300,300,CONT_VIA2,956nymous_ +B 16800,32200,300,300,CONT_VIA,1278ymous_ +B 15600,26000,300,300,CONT_DIF_N,1224ymous_ +B 6800,13800,300,300,CONT_DIF_P,1010ymous_ +B 18800,32800,300,300,CONT_DIF_N,1332ymous_ +B 20800,24400,300,300,CONT_BODY_P,364nymous_ +B 38200,19200,300,300,CONT_BODY_N,901nymous_ +B 37000,26000,300,300,CONT_DIF_P,847nymous_ +B 35400,34000,300,300,CONT_DIF_P,793nymous_ +B 33800,31000,300,300,CONT_DIF_P,739nymous_ +B 32200,25000,300,300,CONT_DIF_P,685nymous_ +B 30600,34000,300,300,CONT_VIA2,631nymous_ +B 26000,25200,300,300,CONT_DIF_P,470nymous_ +B 4400,23000,300,300,CONT_DIF_N,904nymous_ +B 37000,27000,300,300,CONT_VIA,850nymous_ +B 35600,6000,300,300,CONT_BODY_P,796nymous_ +B 33800,32000,300,300,CONT_VIA,742nymous_ +B 32200,28000,300,300,CONT_DIF_P,688nymous_ +B 27200,14000,300,300,CONT_DIF_P,527nymous_ +B 12800,8000,300,300,CONT_DIF_N,1173ymous_ +B 10400,12800,300,300,CONT_DIF_P,1119ymous_ +B 30600,35000,300,300,CONT_VIA2,634nymous_ +B 29000,24600,300,300,CONT_POLY,580nymous_ +B 23600,14000,300,300,CONT_DIF_P,419nymous_ +B 26000,27600,300,300,CONT_DIF_P,473nymous_ +B 18800,34000,300,300,CONT_DIF_N,1333ymous_ +B 8000,12800,300,300,CONT_DIF_P,1065ymous_ +B 6800,14800,300,300,CONT_DIF_P,1011ymous_ +B 20800,25400,300,300,CONT_BODY_P,365nymous_ +B 15600,27000,300,300,CONT_DIF_N,1225ymous_ +B 16800,33400,300,300,CONT_POLY,1279ymous_ +B 5400,26000,300,300,CONT_VIA2,957nymous_ +B 4400,21800,300,300,CONT_VIA,903nymous_ +B 37000,27000,300,300,CONT_DIF_P,849nymous_ +B 35400,36000,300,300,CONT_DIF_P,795nymous_ +B 33800,32000,300,300,CONT_DIF_P,741nymous_ +B 32200,27000,300,300,CONT_DIF_P,687nymous_ +B 30600,35000,300,300,CONT_VIA,633nymous_ +B 26000,26400,300,300,CONT_VIA,472nymous_ +B 27200,13000,300,300,CONT_DIF_P,526nymous_ +B 12800,6000,300,300,CONT_VIA2,1172ymous_ +B 10400,11800,300,300,CONT_DIF_P,1118ymous_ +B 29000,23400,300,300,CONT_VIA,579nymous_ +B 23600,13000,300,300,CONT_DIF_P,418nymous_ +B 8000,11800,300,300,CONT_DIF_P,1064ymous_ +B 30800,8000,300,300,CONT_DIF_N,636nymous_ +B 26000,28800,300,300,CONT_DIF_P,475nymous_ +B 27200,17000,300,300,CONT_VIA,529nymous_ +B 10400,16000,300,300,CONT_BODY_N,1121ymous_ +B 8000,16000,300,300,CONT_BODY_N,1067ymous_ +B 29000,25800,300,300,CONT_POLY,582nymous_ +B 20800,27400,300,300,CONT_BODY_P,367nymous_ +B 24000,27000,300,300,CONT_POLY,421nymous_ +B 16800,33400,300,300,CONT_VIA2,1281ymous_ +B 18800,35200,300,300,CONT_DIF_N,1335ymous_ +B 6800,17000,300,300,CONT_VIA,1013ymous_ +B 5400,31000,300,300,CONT_VIA2,959nymous_ +B 15600,29000,300,300,CONT_DIF_N,1227ymous_ +B 4400,23000,300,300,CONT_VIA,905nymous_ +B 37000,27000,300,300,CONT_VIA2,851nymous_ +B 35600,6000,300,300,CONT_VIA,797nymous_ +B 33800,33000,300,300,CONT_DIF_P,743nymous_ +B 32200,29000,300,300,CONT_DIF_P,689nymous_ +B 27200,16000,300,300,CONT_BODY_N,528nymous_ +B 12800,9000,300,300,CONT_DIF_N,1174ymous_ +B 30800,6000,300,300,CONT_BODY_P,635nymous_ +B 29000,24600,300,300,CONT_VIA,581nymous_ +B 23600,16000,300,300,CONT_BODY_N,420nymous_ +B 26000,27600,300,300,CONT_VIA2,474nymous_ +B 10400,13800,300,300,CONT_DIF_P,1120ymous_ +B 8000,13800,300,300,CONT_DIF_P,1066ymous_ +B 20800,26400,300,300,CONT_BODY_P,366nymous_ +B 16800,33400,300,300,CONT_VIA,1280ymous_ +B 18800,34000,300,300,CONT_VIA,1334ymous_ +B 6800,16000,300,300,CONT_BODY_N,1012ymous_ +B 5400,30000,300,300,CONT_VIA2,958nymous_ +B 15600,28000,300,300,CONT_DIF_N,1226ymous_ +B 15600,30000,300,300,CONT_DIF_N,1228ymous_ +B 16800,34600,300,300,CONT_POLY,1282ymous_ +B 5400,32000,300,300,CONT_VIA2,960nymous_ +B 4400,24000,300,300,CONT_DIF_N,906nymous_ +B 37000,28000,300,300,CONT_DIF_P,852nymous_ +B 35600,6000,300,300,CONT_VIA2,798nymous_ +B 33800,33000,300,300,CONT_VIA,744nymous_ +B 32200,30000,300,300,CONT_DIF_P,690nymous_ +B 6800,17000,300,300,CONT_VIA2,1014ymous_ +B 8000,17000,300,300,CONT_VIA,1068ymous_ +B 18800,36400,300,300,CONT_DIF_N,1336ymous_ +B 24000,28200,300,300,CONT_POLY,422nymous_ +B 20800,28400,300,300,CONT_BODY_P,368nymous_ +B 29000,30600,300,300,CONT_POLY,583nymous_ +B 10400,17000,300,300,CONT_VIA,1122ymous_ +B 12800,12600,300,300,CONT_DIF_P,1176ymous_ +B 27200,17000,300,300,CONT_VIA2,530nymous_ +B 26000,28800,300,300,CONT_VIA,476nymous_ +B 30800,10600,300,300,CONT_POLY,637nymous_ +B 32200,31000,300,300,CONT_DIF_P,691nymous_ +B 33800,33000,300,300,CONT_VIA2,745nymous_ +B 35600,8000,300,300,CONT_DIF_N,799nymous_ +B 37000,28000,300,300,CONT_VIA,853nymous_ +B 4400,24000,300,300,CONT_VIA,907nymous_ +B 5400,36000,300,300,CONT_VIA2,961nymous_ +B 16800,34600,300,300,CONT_VIA,1283ymous_ +B 15600,31000,300,300,CONT_DIF_N,1229ymous_ +B 20800,29400,300,300,CONT_BODY_P,369nymous_ +B 7000,9000,300,300,CONT_VIA2,1015ymous_ +B 8000,17000,300,300,CONT_VIA2,1069ymous_ +B 18800,36400,300,300,CONT_VIA,1337ymous_ +B 24000,28200,300,300,CONT_VIA,423nymous_ +B 26000,28800,300,300,CONT_VIA2,477nymous_ +B 29000,31800,300,300,CONT_POLY,584nymous_ +B 30800,13000,300,300,CONT_DIF_P,638nymous_ +B 10400,17000,300,300,CONT_VIA2,1123ymous_ +B 12800,16000,300,300,CONT_BODY_N,1177ymous_ +B 27800,36400,300,300,CONT_DIF_P,531nymous_ +B 32200,32000,300,300,CONT_DIF_P,692nymous_ +B 33800,34000,300,300,CONT_DIF_P,746nymous_ +B 35600,13000,300,300,CONT_DIF_P,800nymous_ +B 37000,28000,300,300,CONT_VIA2,854nymous_ +B 4400,24000,300,300,CONT_VIA2,908nymous_ +B 15600,32000,300,300,CONT_DIF_N,1230ymous_ +B 5600,37600,300,300,CONT_BODY_P,962nymous_ +B 7000,10000,300,300,CONT_VIA2,1016ymous_ +B 18800,37600,300,300,CONT_BODY_P,1338ymous_ +B 16800,34600,300,300,CONT_VIA2,1284ymous_ +B 20800,30400,300,300,CONT_BODY_P,370nymous_ +B 8600,24000,300,300,CONT_VIA2,1070ymous_ +B 10600,19200,300,300,CONT_BODY_P,1124ymous_ +B 26000,30000,300,300,CONT_DIF_P,478nymous_ +B 24000,29200,300,300,CONT_POLY,424nymous_ +B 29000,33000,300,300,CONT_POLY,585nymous_ +B 30800,14000,300,300,CONT_DIF_P,639nymous_ +B 12800,17000,300,300,CONT_VIA,1178ymous_ +B 27800,37600,300,300,CONT_BODY_N,532nymous_ +B 32200,33000,300,300,CONT_DIF_P,693nymous_ +B 33800,34000,300,300,CONT_VIA,747nymous_ +B 35600,14000,300,300,CONT_DIF_P,801nymous_ +B 37000,29000,300,300,CONT_DIF_P,855nymous_ +B 4400,25000,300,300,CONT_DIF_N,909nymous_ +B 5600,37600,300,300,CONT_VIA,963nymous_ +B 7000,11000,300,300,CONT_VIA2,1017ymous_ +B 12800,17000,300,300,CONT_VIA2,1179ymous_ +B 15600,33000,300,300,CONT_DIF_N,1231ymous_ +B 18800,6000,300,300,CONT_BODY_P,1339ymous_ +B 16800,35800,300,300,CONT_POLY,1285ymous_ +B 24000,34200,300,300,CONT_POLY,425nymous_ +B 20800,31400,300,300,CONT_BODY_P,371nymous_ +B 29000,19200,300,300,CONT_BODY_N,586nymous_ +B 8600,25000,300,300,CONT_VIA2,1071ymous_ +B 10800,21800,300,300,CONT_POLY,1125ymous_ +B 28000,0,300,300,CONT_VIA2,533nymous_ +B 26000,31200,300,300,CONT_DIF_P,479nymous_ +B 30800,16000,300,300,CONT_BODY_N,640nymous_ +B 32200,34000,300,300,CONT_DIF_P,694nymous_ +B 33800,34000,300,300,CONT_VIA2,748nymous_ +B 35600,16000,300,300,CONT_BODY_N,802nymous_ +B 37000,29000,300,300,CONT_VIA,856nymous_ +B 4400,25000,300,300,CONT_VIA,910nymous_ +B 5600,37600,300,300,CONT_VIA2,964nymous_ +B 16800,35800,300,300,CONT_VIA,1286ymous_ +B 15600,34000,300,300,CONT_DIF_N,1232ymous_ +B 7600,21800,300,300,CONT_POLY,1018ymous_ +B 8600,26000,300,300,CONT_VIA2,1072ymous_ +B 18800,6000,300,300,CONT_VIA,1340ymous_ +B 24000,34200,300,300,CONT_VIA,426nymous_ +B 20800,32400,300,300,CONT_BODY_P,372nymous_ +B 29600,33000,300,300,CONT_VIA2,587nymous_ +B 10800,21800,300,300,CONT_VIA,1126ymous_ +B 28000,0,300,300,CONT_VIA3,534nymous_ +B 26000,31200,300,300,CONT_VIA,480nymous_ +B 30800,17000,300,300,CONT_VIA,641nymous_ +B 32200,35000,300,300,CONT_DIF_P,695nymous_ +B 33800,35000,300,300,CONT_DIF_P,749nymous_ +B 35600,17000,300,300,CONT_VIA,803nymous_ +B 37000,29000,300,300,CONT_VIA2,857nymous_ +B 4400,25000,300,300,CONT_VIA2,911nymous_ +B 5600,6000,300,300,CONT_BODY_P,965nymous_ +B 16800,37600,300,300,CONT_BODY_P,1287ymous_ +B 15600,35000,300,300,CONT_DIF_N,1233ymous_ +B 20800,33400,300,300,CONT_BODY_P,373nymous_ +B 7600,21800,300,300,CONT_VIA,1019ymous_ +B 8600,30000,300,300,CONT_VIA2,1073ymous_ +B 18800,6000,300,300,CONT_VIA2,1341ymous_ +B 26000,32400,300,300,CONT_DIF_P,481nymous_ +B 24000,34200,300,300,CONT_VIA2,427nymous_ +B 29600,34000,300,300,CONT_VIA2,588nymous_ +B 30800,17000,300,300,CONT_VIA2,642nymous_ +B 10800,21800,300,300,CONT_VIA2,1127ymous_ +B 28000,0,300,300,CONT_VIA4,535nymous_ +B 32200,36000,300,300,CONT_DIF_P,696nymous_ +B 33800,35000,300,300,CONT_VIA,750nymous_ +B 35600,17000,300,300,CONT_VIA2,804nymous_ +B 37000,30000,300,300,CONT_DIF_P,858nymous_ +B 4400,26000,300,300,CONT_DIF_N,912nymous_ +B 15600,36000,300,300,CONT_DIF_N,1234ymous_ +B 5600,6000,300,300,CONT_VIA,966nymous_ +B 7600,23000,300,300,CONT_DIF_N,1020ymous_ +B 18800,9000,300,300,CONT_DIF_N,1342ymous_ +B 17400,11800,300,300,CONT_POLY,1288ymous_ +B 20800,34400,300,300,CONT_BODY_P,374nymous_ +B 8600,31000,300,300,CONT_VIA2,1074ymous_ +B 10800,23000,300,300,CONT_DIF_N,1128ymous_ +B 24000,35800,300,300,CONT_POLY,428nymous_ +B 29600,35000,300,300,CONT_VIA2,589nymous_ +B 28000,20400,300,300,CONT_DIF_P,536nymous_ +B 26000,33600,300,300,CONT_DIF_P,482nymous_ +B 31000,19200,300,300,CONT_BODY_N,643nymous_ +B 32800,20200,300,300,CONT_POLY,697nymous_ +B 33800,35000,300,300,CONT_VIA2,751nymous_ +B 36000,20200,300,300,CONT_POLY,805nymous_ +B 37000,30000,300,300,CONT_VIA,859nymous_ +B 4400,26000,300,300,CONT_VIA,913nymous_ +B 15600,19200,300,300,CONT_BODY_P,1235ymous_ +B 5600,6000,300,300,CONT_VIA2,967nymous_ +B 7600,23000,300,300,CONT_VIA,1021ymous_ +B 18800,16000,300,300,CONT_BODY_N,1343ymous_ +B 17600,6000,300,300,CONT_BODY_P,1289ymous_ +B 24000,35800,300,300,CONT_VIA,429nymous_ +B 20800,35400,300,300,CONT_BODY_P,375nymous_ +B 29600,7000,300,300,CONT_DIF_N,590nymous_ +B 8600,32000,300,300,CONT_VIA2,1075ymous_ +B 10800,24000,300,300,CONT_DIF_N,1129ymous_ +B 28000,21600,300,300,CONT_DIF_P,537nymous_ +B 26000,33600,300,300,CONT_VIA,483nymous_ +B 31600,20200,300,300,CONT_POLY,644nymous_ +B 32800,22000,300,300,CONT_VIA2,698nymous_ +B 33800,36000,300,300,CONT_DIF_P,752nymous_ +B 36000,22000,300,300,CONT_VIA2,806nymous_ +B 37000,31000,300,300,CONT_DIF_P,860nymous_ +B 4400,26000,300,300,CONT_VIA2,914nymous_ +B 5600,8000,300,300,CONT_DIF_N,968nymous_ +B 17600,6000,300,300,CONT_VIA,1290ymous_ +B 15800,27000,300,300,CONT_VIA2,1236ymous_ +B 7600,24000,300,300,CONT_DIF_N,1022ymous_ +B 18800,17000,300,300,CONT_VIA,1344ymous_ +B 20800,36400,300,300,CONT_BODY_P,376nymous_ +B 14000,21800,300,300,CONT_VIA,1182ymous_ +B 8600,36000,300,300,CONT_VIA2,1076ymous_ +B 24000,37600,300,300,CONT_BODY_N,430nymous_ +B 29600,10600,300,300,CONT_POLY,591nymous_ +B 10800,25000,300,300,CONT_DIF_N,1130ymous_ +B 28000,22800,300,300,CONT_DIF_P,538nymous_ +B 26000,35000,300,300,CONT_DIF_P,484nymous_ +B 31600,22000,300,300,CONT_VIA2,645nymous_ +B 32800,23000,300,300,CONT_VIA2,699nymous_ +B 33800,36000,300,300,CONT_VIA,753nymous_ +B 36000,23000,300,300,CONT_VIA2,807nymous_ +B 37000,31000,300,300,CONT_VIA,861nymous_ +B 4400,27000,300,300,CONT_DIF_N,915nymous_ +B 5600,9000,300,300,CONT_DIF_N,969nymous_ +B 17600,6000,300,300,CONT_VIA2,1291ymous_ +B 15800,28000,300,300,CONT_VIA2,1237ymous_ +B 20800,37600,300,300,CONT_BODY_P,377nymous_ +B 7600,24000,300,300,CONT_VIA,1023ymous_ +B 8600,19200,300,300,CONT_BODY_P,1077ymous_ +B 18800,17000,300,300,CONT_VIA2,1345ymous_ +B 26000,36400,300,300,CONT_DIF_P,485nymous_ +B 24000,19200,300,300,CONT_BODY_N,431nymous_ +B 29600,10600,300,300,CONT_VIA,592nymous_ +B 31600,23000,300,300,CONT_VIA2,646nymous_ +B 10800,26000,300,300,CONT_DIF_N,1131ymous_ +B 28000,24000,300,300,CONT_DIF_P,539nymous_ +B 32800,27000,300,300,CONT_VIA2,700nymous_ +B 34000,19200,300,300,CONT_BODY_N,754nymous_ +B 36000,27000,300,300,CONT_VIA2,808nymous_ +B 37000,32000,300,300,CONT_DIF_P,862nymous_ +B 4400,27000,300,300,CONT_VIA,916nymous_ +B 14000,23000,300,300,CONT_DIF_N,1184ymous_ +B 14000,21800,300,300,CONT_VIA2,1183ymous_ +B 13600,19200,300,300,CONT_BODY_P,1180ymous_ +B 15800,29000,300,300,CONT_VIA2,1238ymous_ +B 5600,11800,300,300,CONT_DIF_P,970nymous_ +B 7600,24000,300,300,CONT_VIA2,1024ymous_ +B 19600,19200,300,300,CONT_BODY_P,1346ymous_ +B 17600,8600,300,300,CONT_DIF_N,1292ymous_ +B 20800,19200,300,300,CONT_BODY_P,378nymous_ +B 8800,37600,300,300,CONT_BODY_P,1078ymous_ +B 10800,27000,300,300,CONT_DIF_N,1132ymous_ +B 26000,37600,300,300,CONT_BODY_N,486nymous_ +B 24800,6000,300,300,CONT_BODY_P,432nymous_ +B 29600,13000,300,300,CONT_DIF_P,593nymous_ +B 31600,27000,300,300,CONT_VIA2,647nymous_ +B 32800,28000,300,300,CONT_VIA2,701nymous_ +B 3400,24000,300,300,CONT_VIA2,755nymous_ +B 36000,28000,300,300,CONT_VIA2,809nymous_ +B 37000,32000,300,300,CONT_VIA,863nymous_ +B 4400,28000,300,300,CONT_DIF_N,917nymous_ +B 15800,37600,300,300,CONT_BODY_P,1239ymous_ +B 14000,24000,300,300,CONT_DIF_N,1185ymous_ +B 5600,12800,300,300,CONT_DIF_P,971nymous_ +B 7600,25000,300,300,CONT_DIF_N,1025ymous_ +B 19800,22600,300,300,CONT_POLY,1347ymous_ +B 17600,12800,300,300,CONT_DIF_P,1293ymous_ +B 24800,6000,300,300,CONT_VIA,433nymous_ +B 21200,6000,300,300,CONT_BODY_P,379nymous_ +B 29600,14000,300,300,CONT_DIF_P,594nymous_ +B 8800,37600,300,300,CONT_VIA,1079ymous_ +B 10800,28000,300,300,CONT_DIF_N,1133ymous_ +B 14000,21800,300,300,CONT_POLY,1181ymous_ +B 26000,6000,300,300,CONT_BODY_P,487nymous_ +B 31600,28000,300,300,CONT_VIA2,648nymous_ +B 32800,29000,300,300,CONT_VIA2,702nymous_ +B 3400,25000,300,300,CONT_VIA2,756nymous_ +B 36000,29000,300,300,CONT_VIA2,810nymous_ +B 37000,33000,300,300,CONT_DIF_P,864nymous_ +B 14000,25000,300,300,CONT_DIF_N,1186ymous_ +B 4400,28000,300,300,CONT_VIA,918nymous_ +B 5600,13800,300,300,CONT_DIF_P,972nymous_ +B 17600,16000,300,300,CONT_BODY_N,1294ymous_ +B 1600,20400,300,300,CONT_BODY_P,1240ymous_ +B 7600,25000,300,300,CONT_VIA,1026ymous_ +B 8800,37600,300,300,CONT_VIA2,1080ymous_ +B 19800,26200,300,300,CONT_POLY,1348ymous_ +B 24800,6000,300,300,CONT_VIA2,434nymous_ +B 21200,6000,300,300,CONT_VIA,380nymous_ +B 29600,16000,300,300,CONT_BODY_N,595nymous_ +B 10800,29000,300,300,CONT_DIF_N,1134ymous_ +B 26000,6000,300,300,CONT_VIA,488nymous_ +B 31600,29000,300,300,CONT_VIA2,649nymous_ +B 32800,33000,300,300,CONT_VIA2,703nymous_ +B 3400,26000,300,300,CONT_VIA2,757nymous_ +B 36000,33000,300,300,CONT_VIA2,811nymous_ +B 37000,33000,300,300,CONT_VIA,865nymous_ +B 14000,26000,300,300,CONT_DIF_N,1187ymous_ +B 4400,29000,300,300,CONT_DIF_N,919nymous_ +B 5600,16000,300,300,CONT_BODY_N,973nymous_ +B 17600,17000,300,300,CONT_VIA,1295ymous_ +B 1600,21400,300,300,CONT_BODY_P,1241ymous_ +B 21200,6000,300,300,CONT_VIA2,381nymous_ +B 7600,25000,300,300,CONT_VIA2,1027ymous_ +B 9200,23000,300,300,CONT_DIF_N,1081ymous_ +B 19800,27400,300,300,CONT_POLY,1349ymous_ +B 24800,8000,300,300,CONT_DIF_N,435nymous_ +B 26000,6000,300,300,CONT_VIA2,489nymous_ +B 29600,17000,300,300,CONT_VIA,596nymous_ +B 31600,33000,300,300,CONT_VIA2,650nymous_ +B 10800,30000,300,300,CONT_DIF_N,1135ymous_ +B 32800,34000,300,300,CONT_VIA2,704nymous_ +B 3400,30000,300,300,CONT_VIA2,758nymous_ +B 36000,34000,300,300,CONT_VIA2,812nymous_ +B 37000,33000,300,300,CONT_VIA2,866nymous_ +B 4400,29000,300,300,CONT_VIA,920nymous_ +B 1600,22400,300,300,CONT_BODY_P,1242ymous_ +B 14000,27000,300,300,CONT_DIF_N,1188ymous_ +B 5600,17000,300,300,CONT_VIA,974nymous_ +B 7600,26000,300,300,CONT_DIF_N,1028ymous_ +B 19800,28200,300,300,CONT_VIA,1350ymous_ +B 17600,17000,300,300,CONT_VIA2,1296ymous_ +B 21200,9000,300,300,CONT_DIF_N,382nymous_ +B 28000,28800,300,300,CONT_DIF_P,543nymous_ +B 9200,24000,300,300,CONT_DIF_N,1082ymous_ +B 10800,31000,300,300,CONT_DIF_N,1136ymous_ +B 26000,8000,300,300,CONT_DIF_N,490nymous_ +B 24800,13000,300,300,CONT_DIF_P,436nymous_ +B 29600,17000,300,300,CONT_VIA2,597nymous_ +B 31600,34000,300,300,CONT_VIA2,651nymous_ +B 32800,35000,300,300,CONT_VIA2,705nymous_ +B 3400,31000,300,300,CONT_VIA2,759nymous_ +B 36000,35000,300,300,CONT_VIA2,813nymous_ +B 37000,34000,300,300,CONT_DIF_P,867nymous_ +B 4400,30000,300,300,CONT_DIF_N,921nymous_ +B 14000,28000,300,300,CONT_DIF_N,1189ymous_ +B 5600,17000,300,300,CONT_VIA2,975nymous_ +B 7600,26000,300,300,CONT_VIA,1029ymous_ +B 28000,27600,300,300,CONT_DIF_P,542nymous_ +B 1600,23400,300,300,CONT_BODY_P,1243ymous_ +B 19800,31000,300,300,CONT_POLY,1351ymous_ +B 17600,19200,300,300,CONT_BODY_P,1297ymous_ +B 24800,13000,300,300,CONT_VIA,437nymous_ +B 21200,16000,300,300,CONT_BODY_N,383nymous_ +B 28000,30000,300,300,CONT_DIF_P,544nymous_ +B 30000,0,300,300,CONT_VIA2,598nymous_ +B 9200,25000,300,300,CONT_DIF_N,1083ymous_ +B 10800,32000,300,300,CONT_DIF_N,1137ymous_ +B 26000,12000,300,300,CONT_VIA2,491nymous_ +B 31600,35000,300,300,CONT_VIA2,652nymous_ +B 33000,19200,300,300,CONT_BODY_N,706nymous_ +B 3400,32000,300,300,CONT_VIA2,760nymous_ +B 36000,19200,300,300,CONT_BODY_N,814nymous_ +B 37000,34000,300,300,CONT_VIA,868nymous_ +B 14000,29000,300,300,CONT_DIF_N,1190ymous_ +B 4400,30000,300,300,CONT_VIA,922nymous_ +B 5600,19200,300,300,CONT_BODY_P,976nymous_ +B 17800,23200,300,300,CONT_DIF_N,1298ymous_ +B 1600,24400,300,300,CONT_BODY_P,1244ymous_ +B 7600,26000,300,300,CONT_VIA2,1030ymous_ +B 9200,26000,300,300,CONT_DIF_N,1084ymous_ +B 19800,35200,300,300,CONT_VIA,1352ymous_ +B 24800,14000,300,300,CONT_DIF_P,438nymous_ +B 22000,22200,300,300,CONT_VIA,384nymous_ +B 28000,31200,300,300,CONT_DIF_P,545nymous_ +B 30000,0,300,300,CONT_VIA3,599nymous_ +B 10800,33000,300,300,CONT_DIF_N,1138ymous_ +B 26000,13000,300,300,CONT_DIF_P,492nymous_ +B 31800,9000,300,300,CONT_POLY,653nymous_ +B 33200,6000,300,300,CONT_BODY_P,707nymous_ +B 3400,36000,300,300,CONT_VIA2,761nymous_ +B 3600,37600,300,300,CONT_BODY_P,815nymous_ +B 37000,34000,300,300,CONT_VIA2,869nymous_ +B 14000,30000,300,300,CONT_DIF_N,1191ymous_ +B 4400,30000,300,300,CONT_VIA2,923nymous_ +B 6000,23000,300,300,CONT_DIF_N,977nymous_ +B 17800,23200,300,300,CONT_VIA,1299ymous_ +B 1600,25400,300,300,CONT_BODY_P,1245ymous_ +B 22000,19200,300,300,CONT_VIA,385nymous_ +B 28000,31200,300,300,CONT_VIA,546nymous_ +B 7600,27000,300,300,CONT_DIF_N,1031ymous_ +B 9200,27000,300,300,CONT_DIF_N,1085ymous_ +B 19800,37600,300,300,CONT_BODY_P,1353ymous_ +B 26000,13000,300,300,CONT_VIA2,493nymous_ +B 24800,14000,300,300,CONT_VIA,439nymous_ +B 30000,0,300,300,CONT_VIA4,600nymous_ +B 31800,12200,300,300,CONT_POLY,654nymous_ +B 10800,34000,300,300,CONT_DIF_N,1139ymous_ +B 33200,6000,300,300,CONT_VIA,708nymous_ +B 34400,6000,300,300,CONT_BODY_P,762nymous_ +B 3600,37600,300,300,CONT_VIA,816nymous_ +B 37000,35000,300,300,CONT_DIF_P,870nymous_ +B 4400,31000,300,300,CONT_DIF_N,924nymous_ +B 1600,26400,300,300,CONT_BODY_P,1246ymous_ +B 14000,31000,300,300,CONT_DIF_N,1192ymous_ +B 6000,24000,300,300,CONT_DIF_N,978nymous_ +B 7600,27000,300,300,CONT_VIA,1032ymous_ +B 17800,24400,300,300,CONT_DIF_N,1300ymous_ +B 22400,6000,300,300,CONT_BODY_P,386nymous_ +B 28000,32400,300,300,CONT_DIF_P,547nymous_ +B 9200,28000,300,300,CONT_DIF_N,1086ymous_ +B 24800,16000,300,300,CONT_BODY_N,440nymous_ +B 10800,35000,300,300,CONT_DIF_N,1140ymous_ +B 26000,14000,300,300,CONT_DIF_P,494nymous_ +B 30000,20200,300,300,CONT_VIA,601nymous_ +B 32000,6000,300,300,CONT_BODY_P,655nymous_ +B 33200,6000,300,300,CONT_VIA2,709nymous_ +B 34400,6000,300,300,CONT_VIA,763nymous_ +B 3600,37600,300,300,CONT_VIA2,817nymous_ +B 37000,35000,300,300,CONT_VIA,871nymous_ +B 4400,31000,300,300,CONT_VIA,925nymous_ +B 1600,27400,300,300,CONT_BODY_P,1247ymous_ +B 14000,32000,300,300,CONT_DIF_N,1193ymous_ +B 6000,25000,300,300,CONT_DIF_N,979nymous_ +B 7600,28000,300,300,CONT_DIF_N,1033ymous_ +B 17800,24400,300,300,CONT_VIA2,1301ymous_ +B 25000,20400,300,300,CONT_DIF_P,441nymous_ +B 22400,6000,300,300,CONT_VIA,387nymous_ +B 28000,33600,300,300,CONT_DIF_P,548nymous_ +B 30000,19200,300,300,CONT_BODY_N,602nymous_ +B 9200,29000,300,300,CONT_DIF_N,1087ymous_ +B 10800,36000,300,300,CONT_DIF_N,1141ymous_ +B 26000,14000,300,300,CONT_VIA2,495nymous_ +B 32000,6000,300,300,CONT_VIA,656nymous_ +B 33200,8000,300,300,CONT_DIF_N,710nymous_ +B 34400,6000,300,300,CONT_VIA2,764nymous_ +B 3600,19200,300,300,CONT_BODY_P,818nymous_ +B 37000,35000,300,300,CONT_VIA2,872nymous_ +B 14000,33000,300,300,CONT_DIF_N,1194ymous_ +B 4400,31000,300,300,CONT_VIA2,926nymous_ +B 6000,26000,300,300,CONT_DIF_N,980nymous_ +B 1600,28400,300,300,CONT_BODY_P,1248ymous_ +B 7600,28000,300,300,CONT_VIA,1034ymous_ +B 17800,25600,300,300,CONT_DIF_N,1302ymous_ +B 9200,30000,300,300,CONT_DIF_N,1088ymous_ +B 25000,20400,300,300,CONT_VIA,442nymous_ +B 22400,6000,300,300,CONT_VIA2,388nymous_ +B 28000,35000,300,300,CONT_DIF_P,549nymous_ +B 30400,36600,300,300,CONT_POLY,603nymous_ +B 11600,6000,300,300,CONT_BODY_P,1142ymous_ +B 26000,16000,300,300,CONT_BODY_N,496nymous_ +B 32000,6000,300,300,CONT_VIA2,657nymous_ +B 33200,13000,300,300,CONT_DIF_P,711nymous_ +B 34400,8000,300,300,CONT_DIF_N,765nymous_ +B 36800,6000,300,300,CONT_BODY_P,819nymous_ +B 37000,36000,300,300,CONT_DIF_P,873nymous_ +B 14000,34000,300,300,CONT_DIF_N,1195ymous_ +B 4400,32000,300,300,CONT_DIF_N,927nymous_ +B 6000,27000,300,300,CONT_DIF_N,981nymous_ +B 17800,25600,300,300,CONT_VIA,1303ymous_ +B 1600,29400,300,300,CONT_BODY_P,1249ymous_ +B 22400,8600,300,300,CONT_DIF_N,389nymous_ +B 28000,19200,300,300,CONT_BODY_N,550nymous_ +B 7600,29000,300,300,CONT_DIF_N,1035ymous_ +B 9200,31000,300,300,CONT_DIF_N,1089ymous_ +B 26000,17000,300,300,CONT_VIA,497nymous_ +B 25000,21600,300,300,CONT_DIF_P,443nymous_ +B 30400,36600,300,300,CONT_VIA,604nymous_ +B 32000,8000,300,300,CONT_DIF_N,658nymous_ +B 11600,6000,300,300,CONT_VIA,1143ymous_ +B 33200,14000,300,300,CONT_DIF_P,712nymous_ +B 34400,13000,300,300,CONT_DIF_P,766nymous_ +B 36800,6000,300,300,CONT_VIA,820nymous_ +B 37000,36000,300,300,CONT_VIA,874nymous_ +B 4400,32000,300,300,CONT_VIA,928nymous_ +B 1600,30400,300,300,CONT_BODY_P,1250ymous_ +B 14000,35000,300,300,CONT_DIF_N,1196ymous_ +B 6000,28000,300,300,CONT_DIF_N,982nymous_ +B 7600,29000,300,300,CONT_VIA,1036ymous_ +B 17800,25600,300,300,CONT_VIA2,1304ymous_ +B 22400,16000,300,300,CONT_BODY_N,390nymous_ +B 2800,23000,300,300,CONT_DIF_N,551nymous_ +B 9200,32000,300,300,CONT_DIF_N,1090ymous_ +B 11600,6000,300,300,CONT_VIA2,1144ymous_ +B 26000,17000,300,300,CONT_VIA2,498nymous_ +B 25000,22800,300,300,CONT_DIF_P,444nymous_ +B 30400,36600,300,300,CONT_VIA2,605nymous_ +B 32000,13000,300,300,CONT_DIF_P,659nymous_ +B 33200,16000,300,300,CONT_BODY_N,713nymous_ +B 34400,13000,300,300,CONT_VIA,767nymous_ +B 36800,6000,300,300,CONT_VIA2,821nymous_ +B 37000,19200,300,300,CONT_BODY_N,875nymous_ +B 4400,32000,300,300,CONT_VIA2,929nymous_ +B 1600,31400,300,300,CONT_BODY_P,1251ymous_ +B 14000,36000,300,300,CONT_DIF_N,1197ymous_ +B 6000,29000,300,300,CONT_DIF_N,983nymous_ +B 7600,30000,300,300,CONT_DIF_N,1037ymous_ +B 17800,26800,300,300,CONT_DIF_N,1305ymous_ +B 22400,17000,300,300,CONT_VIA,391nymous_ +B 2800,24000,300,300,CONT_DIF_N,552nymous_ +B 9200,33000,300,300,CONT_DIF_N,1091ymous_ +B 11600,8000,300,300,CONT_DIF_N,1145ymous_ +B 26000,19200,300,300,CONT_BODY_N,499nymous_ +B 25000,22800,300,300,CONT_VIA,445nymous_ +B 30600,22000,300,300,CONT_DIF_P,606nymous_ +B 32000,16000,300,300,CONT_BODY_N,660nymous_ +B 33200,17000,300,300,CONT_VIA,714nymous_ +B 34400,14000,300,300,CONT_DIF_P,768nymous_ +B 36800,7000,300,300,CONT_BODY_P,822nymous_ +B 37200,37600,300,300,CONT_BODY_N,876nymous_ +B 14000,6000,300,300,CONT_BODY_P,1198ymous_ +B 4400,33000,300,300,CONT_DIF_N,930nymous_ +B 6000,30000,300,300,CONT_DIF_N,984nymous_ +B 17800,28000,300,300,CONT_DIF_N,1306ymous_ +B 1600,32400,300,300,CONT_BODY_P,1252ymous_ +B 7600,30000,300,300,CONT_VIA,1038ymous_ +B 9200,34000,300,300,CONT_DIF_N,1092ymous_ +B 25000,24000,300,300,CONT_DIF_P,446nymous_ +B 22400,17000,300,300,CONT_VIA2,392nymous_ +B 2800,25000,300,300,CONT_DIF_N,553nymous_ +B 30600,23000,300,300,CONT_DIF_P,607nymous_ +B 11600,9000,300,300,CONT_DIF_N,1146ymous_ +B 2600,37600,300,300,CONT_BODY_P,500nymous_ +B 32000,17000,300,300,CONT_VIA,661nymous_ +B 33200,17000,300,300,CONT_VIA2,715nymous_ +B 34400,14000,300,300,CONT_VIA,769nymous_ +B 36800,8000,300,300,CONT_BODY_P,823nymous_ +B 38000,27000,300,300,CONT_VIA2,877nymous_ +B 14000,6000,300,300,CONT_VIA,1199ymous_ +B 4400,33000,300,300,CONT_VIA,931nymous_ +B 6000,31000,300,300,CONT_DIF_N,985nymous_ +B 1600,33400,300,300,CONT_BODY_P,1253ymous_ +B 7600,30000,300,300,CONT_VIA2,1039ymous_ +B 9200,35000,300,300,CONT_DIF_N,1093ymous_ +B 17800,28000,300,300,CONT_VIA,1307ymous_ +B 23000,20400,300,300,CONT_BODY_N,393nymous_ +B 2800,26000,300,300,CONT_DIF_N,554nymous_ +B 2600,19200,300,300,CONT_BODY_P,501nymous_ +B 25000,25200,300,300,CONT_DIF_P,447nymous_ +B 30600,24000,300,300,CONT_DIF_P,608nymous_ +B 32000,17000,300,300,CONT_VIA2,662nymous_ +B 11600,11800,300,300,CONT_DIF_P,1147ymous_ +B 33800,22000,300,300,CONT_DIF_P,716nymous_ +B 34400,16000,300,300,CONT_BODY_N,770nymous_ +B 36800,9000,300,300,CONT_BODY_P,824nymous_ +B 38000,28000,300,300,CONT_VIA2,878nymous_ +B 4400,34000,300,300,CONT_DIF_N,932nymous_ +B 1600,34400,300,300,CONT_BODY_P,1254ymous_ +B 14000,6000,300,300,CONT_VIA2,1200ymous_ +B 6000,32000,300,300,CONT_DIF_N,986nymous_ +B 7600,31000,300,300,CONT_DIF_N,1040ymous_ +B 17800,29200,300,300,CONT_DIF_N,1308ymous_ +B 23000,21400,300,300,CONT_BODY_N,394nymous_ +B 2800,27000,300,300,CONT_DIF_N,555nymous_ +B 9200,36000,300,300,CONT_DIF_N,1094ymous_ +B 11600,12800,300,300,CONT_DIF_P,1148ymous_ +B 27000,20400,300,300,CONT_DIF_P,502nymous_ +B 25000,26400,300,300,CONT_DIF_P,448nymous_ +B 30600,25000,300,300,CONT_DIF_P,609nymous_ +B 32000,19200,300,300,CONT_BODY_N,663nymous_ +B 33800,22000,300,300,CONT_VIA,717nymous_ +B 34800,20200,300,300,CONT_POLY,771nymous_ +B 36800,9000,300,300,CONT_VIA2,825nymous_ +B 38000,29000,300,300,CONT_VIA2,879nymous_ +B 4400,34000,300,300,CONT_VIA,933nymous_ +B 1600,35400,300,300,CONT_BODY_P,1255ymous_ +B 14000,7200,300,300,CONT_DIF_N,1201ymous_ +B 6000,33000,300,300,CONT_DIF_N,987nymous_ +B 7600,31000,300,300,CONT_VIA,1041ymous_ +B 17800,30400,300,300,CONT_DIF_N,1309ymous_ +B 25000,27600,300,300,CONT_DIF_P,449nymous_ +B 23000,22400,300,300,CONT_BODY_N,395nymous_ +B 2800,28000,300,300,CONT_DIF_N,556nymous_ +B 30600,26000,300,300,CONT_DIF_P,610nymous_ +B 9200,6000,300,300,CONT_BODY_P,1095ymous_ +B 11600,13800,300,300,CONT_DIF_P,1149ymous_ +B 27000,21600,300,300,CONT_DIF_P,503nymous_ +B 3200,6000,300,300,CONT_BODY_P,664nymous_ +B 33800,22000,300,300,CONT_VIA2,718nymous_ +B 34800,22000,300,300,CONT_VIA2,772nymous_ +B 36800,10000,300,300,CONT_VIA2,826nymous_ +B 38000,33000,300,300,CONT_VIA2,880nymous_ +B 14000,8000,300,300,CONT_DIF_N,1202ymous_ +B 4400,35000,300,300,CONT_DIF_N,934nymous_ +B 6000,34000,300,300,CONT_DIF_N,988nymous_ +B 17800,30400,300,300,CONT_VIA,1310ymous_ +B 1600,36400,300,300,CONT_BODY_P,1256ymous_ +B 7600,31000,300,300,CONT_VIA2,1042ymous_ +B 9200,6000,300,300,CONT_VIA,1096ymous_ +B 25000,27600,300,300,CONT_VIA,450nymous_ +B 23000,23400,300,300,CONT_BODY_N,396nymous_ +B 2800,29000,300,300,CONT_DIF_N,557nymous_ +B 11600,14800,300,300,CONT_DIF_P,1150ymous_ +B 27000,22800,300,300,CONT_DIF_P,504nymous_ +B 30600,27000,300,300,CONT_DIF_P,611nymous_ +B 3200,6000,300,300,CONT_VIA,665nymous_ +B 33800,23000,300,300,CONT_DIF_P,719nymous_ +B 34800,23000,300,300,CONT_VIA2,773nymous_ +B 36800,11000,300,300,CONT_VIA2,827nymous_ +B 38000,34000,300,300,CONT_VIA2,881nymous_ +B 14000,10000,300,300,CONT_POLY,1203ymous_ +B 4400,35000,300,300,CONT_VIA,935nymous_ +B 6000,35000,300,300,CONT_DIF_N,989nymous_ +B 17800,30400,300,300,CONT_VIA2,1311ymous_ +B 1600,37600,300,300,CONT_BODY_P,1257ymous_ +B 23000,24400,300,300,CONT_BODY_N,397nymous_ +B 2800,30000,300,300,CONT_DIF_N,558nymous_ +B 7600,32000,300,300,CONT_DIF_N,1043ymous_ +B 9200,6000,300,300,CONT_VIA2,1097ymous_ +B 27000,24000,300,300,CONT_DIF_P,505nymous_ +B 25000,28800,300,300,CONT_DIF_P,451nymous_ +B 30600,27000,300,300,CONT_VIA,612nymous_ +B 3200,6000,300,300,CONT_VIA2,666nymous_ +B 11600,16000,300,300,CONT_BODY_N,1151ymous_ +B 33800,23000,300,300,CONT_VIA,720nymous_ +B 34800,27000,300,300,CONT_VIA2,774nymous_ +B 36800,12000,300,300,CONT_BODY_N,828nymous_ +B 38000,35000,300,300,CONT_VIA2,882nymous_ +B 4400,36000,300,300,CONT_DIF_N,936nymous_ +B 1600,19200,300,300,CONT_BODY_P,1258ymous_ +B 14000,12000,300,300,CONT_DIF_P,1204ymous_ +B 6000,36000,300,300,CONT_DIF_N,990nymous_ +B 7600,32000,300,300,CONT_VIA,1044ymous_ +B 17800,31600,300,300,CONT_DIF_N,1312ymous_ +B 9200,7000,300,300,CONT_VIA2,1098ymous_ +B 4400,36000,300,300,CONT_VIA2,938nymous_ +B 38200,21400,300,300,CONT_BODY_N,884nymous_ +B 36800,14000,300,300,CONT_BODY_N,830nymous_ +B 34800,29000,300,300,CONT_VIA2,776nymous_ +B 33800,24000,300,300,CONT_DIF_P,722nymous_ +B 3200,7000,300,300,CONT_VIA2,668nymous_ +B 27000,25200,300,300,CONT_VIA,507nymous_ +B 11600,17000,300,300,CONT_VIA2,1153ymous_ +B 9200,7200,300,300,CONT_DIF_N,1099ymous_ +B 30600,28000,300,300,CONT_DIF_P,614nymous_ +B 2800,32000,300,300,CONT_DIF_N,560nymous_ +B 23000,26400,300,300,CONT_BODY_N,399nymous_ +B 25000,30000,300,300,CONT_VIA,453nymous_ +B 17800,31600,300,300,CONT_VIA2,1313ymous_ +B 7600,32000,300,300,CONT_VIA2,1045ymous_ +B 6600,24000,300,300,CONT_VIA2,991nymous_ +B 14000,12800,300,300,CONT_DIF_P,1205ymous_ +B 16400,6000,300,300,CONT_BODY_P,1259ymous_ +B 4400,36000,300,300,CONT_VIA,937nymous_ +B 38200,20400,300,300,CONT_BODY_N,883nymous_ +B 36800,13000,300,300,CONT_BODY_N,829nymous_ +B 34800,28000,300,300,CONT_VIA2,775nymous_ +B 33800,23000,300,300,CONT_VIA2,721nymous_ +B 3200,7000,300,300,CONT_BODY_P,667nymous_ +B 30600,27000,300,300,CONT_VIA2,613nymous_ +B 23000,25400,300,300,CONT_BODY_N,398nymous_ +B 2800,31000,300,300,CONT_DIF_N,559nymous_ +B 11600,17000,300,300,CONT_VIA,1152ymous_ +B 27000,25200,300,300,CONT_DIF_P,506nymous_ +B 25000,30000,300,300,CONT_DIF_P,452nymous_ +B 12400,23000,300,300,CONT_DIF_N,1155ymous_ +B 30600,28000,300,300,CONT_VIA2,616nymous_ +B 25000,32400,300,300,CONT_DIF_P,455nymous_ +B 9200,8000,300,300,CONT_VIA2,1101ymous_ +B 7600,33000,300,300,CONT_VIA,1047ymous_ +B 2800,34000,300,300,CONT_DIF_N,562nymous_ +B 23000,28400,300,300,CONT_BODY_N,401nymous_ +B 16400,6000,300,300,CONT_VIA2,1261ymous_ +B 17800,34000,300,300,CONT_DIF_N,1315ymous_ +B 6600,26000,300,300,CONT_VIA2,993nymous_ +B 4400,6000,300,300,CONT_BODY_P,939nymous_ +B 14000,17000,300,300,CONT_VIA,1207ymous_ +B 38200,22400,300,300,CONT_BODY_N,885nymous_ +B 36800,15000,300,300,CONT_BODY_N,831nymous_ +B 34800,33000,300,300,CONT_VIA2,777nymous_ +B 33800,24000,300,300,CONT_VIA,723nymous_ +B 3200,8000,300,300,CONT_BODY_P,669nymous_ +B 27000,26400,300,300,CONT_DIF_P,508nymous_ +B 11600,19200,300,300,CONT_BODY_P,1154ymous_ +B 30600,28000,300,300,CONT_VIA,615nymous_ +B 2800,33000,300,300,CONT_DIF_N,561nymous_ +B 23000,27400,300,300,CONT_BODY_N,400nymous_ +B 25000,31200,300,300,CONT_DIF_P,454nymous_ +B 9200,8000,300,300,CONT_DIF_N,1100ymous_ +B 7600,33000,300,300,CONT_DIF_N,1046ymous_ +B 16400,6000,300,300,CONT_VIA,1260ymous_ +B 17800,32800,300,300,CONT_DIF_N,1314ymous_ +B 6600,25000,300,300,CONT_VIA2,992nymous_ +B 14000,16000,300,300,CONT_BODY_N,1206ymous_ +B 33800,28000,300,300,CONT_DIF_P,731nymous_ +B 30600,29000,300,300,CONT_DIF_P,617nymous_ +B 25000,32400,300,300,CONT_VIA,456nymous_ +B 27000,28800,300,300,CONT_DIF_P,510nymous_ +B 12400,24000,300,300,CONT_DIF_N,1156ymous_ +B 9200,10000,300,300,CONT_POLY,1102ymous_ +B 2800,35000,300,300,CONT_DIF_N,563nymous_ +B 23000,29400,300,300,CONT_BODY_N,402nymous_ +B 17800,35200,300,300,CONT_DIF_N,1316ymous_ +B 7600,34000,300,300,CONT_DIF_N,1048ymous_ +B 6600,30000,300,300,CONT_VIA2,994nymous_ +B 14000,17000,300,300,CONT_VIA2,1208ymous_ +B 16400,8000,300,300,CONT_DIF_N,1262ymous_ +B 4400,6000,300,300,CONT_VIA,940nymous_ +B 38200,23400,300,300,CONT_BODY_N,886nymous_ +B 36800,15000,300,300,CONT_VIA2,832nymous_ +B 34800,34000,300,300,CONT_VIA2,778nymous_ +B 33800,25000,300,300,CONT_DIF_P,724nymous_ +B 3200,8000,300,300,CONT_VIA2,670nymous_ +B 27000,27600,300,300,CONT_DIF_P,509nymous_ +B 12800,11600,300,300,CONT_DIF_P,1175ymous_ +B 3200,9000,300,300,CONT_BODY_P,671nymous_ +B 33800,25000,300,300,CONT_VIA,725nymous_ +B 34800,35000,300,300,CONT_VIA2,779nymous_ +B 36800,16000,300,300,CONT_BODY_N,833nymous_ +B 38200,24400,300,300,CONT_BODY_N,887nymous_ +B 4400,6000,300,300,CONT_VIA2,941nymous_ +B 16400,9000,300,300,CONT_DIF_N,1263ymous_ +B 14600,19200,300,300,CONT_BODY_P,1209ymous_ +B 6600,31000,300,300,CONT_VIA2,995nymous_ +B 7600,34000,300,300,CONT_VIA,1049ymous_ +B 17800,36400,300,300,CONT_DIF_N,1317ymous_ +B 28000,26400,300,300,CONT_DIF_P,541nymous_ +B 25000,33600,300,300,CONT_DIF_P,457nymous_ +B 23000,30400,300,300,CONT_BODY_N,403nymous_ +B 2800,36000,300,300,CONT_DIF_N,564nymous_ +B 30600,29000,300,300,CONT_VIA,618nymous_ +B 9200,12000,300,300,CONT_DIF_P,1103ymous_ +B 12400,25000,300,300,CONT_DIF_N,1157ymous_ +B 27000,30000,300,300,CONT_DIF_P,511nymous_ +B 3200,12000,300,300,CONT_BODY_N,672nymous_ +B 33800,26000,300,300,CONT_DIF_P,726nymous_ +B 35000,19200,300,300,CONT_BODY_N,780nymous_ +B 36800,16000,300,300,CONT_VIA2,834nymous_ +B 38200,25400,300,300,CONT_BODY_N,888nymous_ +B 15200,6000,300,300,CONT_BODY_P,1210ymous_ +B 4400,8000,300,300,CONT_DIF_N,942nymous_ +B 6600,32000,300,300,CONT_VIA2,996nymous_ +B 17800,37600,300,300,CONT_BODY_P,1318ymous_ +B 16400,10000,300,300,CONT_POLY,1264ymous_ +B 7600,35000,300,300,CONT_DIF_N,1050ymous_ +B 9200,12800,300,300,CONT_DIF_P,1104ymous_ +B 25000,35000,300,300,CONT_DIF_P,458nymous_ +B 23000,31400,300,300,CONT_BODY_N,404nymous_ +B 28200,10600,300,300,CONT_VIA,565nymous_ +B 30600,29000,300,300,CONT_VIA2,619nymous_ +B 12400,26000,300,300,CONT_DIF_N,1158ymous_ +B 27000,31200,300,300,CONT_DIF_P,512nymous_ +B 3200,12000,300,300,CONT_VIA2,673nymous_ +B 33800,26000,300,300,CONT_VIA,727nymous_ +B 35400,22000,300,300,CONT_DIF_P,781nymous_ +B 36800,17000,300,300,CONT_VIA,835nymous_ +B 20000,6000,300,300,CONT_BODY_P,354nymous_ +B 20000,6000,300,300,CONT_VIA,355nymous_ +B 38200,26400,300,300,CONT_BODY_N,889nymous_ +B 15200,6000,300,300,CONT_VIA,1211ymous_ +B 4400,9000,300,300,CONT_DIF_N,943nymous_ +B 6600,36000,300,300,CONT_VIA2,997nymous_ +B 18600,19200,300,300,CONT_BODY_P,1319ymous_ +B 16400,12000,300,300,CONT_DIF_P,1265ymous_ +B 23000,32400,300,300,CONT_BODY_N,405nymous_ +B 28200,11800,300,300,CONT_POLY,566nymous_ +B 7600,35000,300,300,CONT_VIA,1051ymous_ +B 9200,13800,300,300,CONT_DIF_P,1105ymous_ +B 27000,32400,300,300,CONT_DIF_P,513nymous_ +B 25000,36400,300,300,CONT_DIF_P,459nymous_ +B 30600,30000,300,300,CONT_DIF_P,620nymous_ +B 3200,13000,300,300,CONT_BODY_N,674nymous_ +B 12400,27000,300,300,CONT_DIF_N,1159ymous_ +B 33800,27000,300,300,CONT_DIF_P,728nymous_ +B 35400,23000,300,300,CONT_DIF_P,782nymous_ +B 36800,17000,300,300,CONT_VIA2,836nymous_ +B 38200,27400,300,300,CONT_BODY_N,890nymous_ +B 4400,11800,300,300,CONT_DIF_P,944nymous_ +B 16400,12800,300,300,CONT_DIF_P,1266ymous_ +B 15200,6000,300,300,CONT_VIA2,1212ymous_ +B 6600,19200,300,300,CONT_BODY_P,998nymous_ +B 7600,36000,300,300,CONT_DIF_N,1052ymous_ +B 18800,22000,300,300,CONT_DIF_N,1320ymous_ +B 23000,33400,300,300,CONT_BODY_N,406nymous_ +B 28400,6000,300,300,CONT_BODY_P,567nymous_ +B 9200,14800,300,300,CONT_DIF_P,1106ymous_ +B 12400,28000,300,300,CONT_DIF_N,1160ymous_ +B 27000,33600,300,300,CONT_DIF_P,514nymous_ +B 25000,37600,300,300,CONT_BODY_N,460nymous_ +B 30600,30000,300,300,CONT_VIA,621nymous_ +B 3200,13000,300,300,CONT_VIA2,675nymous_ +B 33800,27000,300,300,CONT_VIA,729nymous_ +B 35400,24000,300,300,CONT_DIF_P,783nymous_ +B 37000,22000,300,300,CONT_DIF_P,837nymous_ +B 38200,28400,300,300,CONT_BODY_N,891nymous_ +B 4400,12800,300,300,CONT_DIF_P,945nymous_ +B 16400,16000,300,300,CONT_BODY_N,1267ymous_ +B 15200,8000,300,300,CONT_DIF_N,1213ymous_ +B 6800,37600,300,300,CONT_BODY_P,999nymous_ +B 7600,36000,300,300,CONT_VIA,1053ymous_ +B 18800,22200,300,300,CONT_VIA,1321ymous_ +B 25000,19200,300,300,CONT_BODY_N,461nymous_ +B 23000,34400,300,300,CONT_BODY_N,407nymous_ +B 28400,8000,300,300,CONT_DIF_N,568nymous_ +B 30600,31000,300,300,CONT_DIF_P,622nymous_ +B 9200,16000,300,300,CONT_BODY_N,1107ymous_ +B 12400,29000,300,300,CONT_DIF_N,1161ymous_ +B 27000,35000,300,300,CONT_DIF_P,515nymous_ +B 3200,14000,300,300,CONT_BODY_N,676nymous_ +B 33800,27000,300,300,CONT_VIA2,730nymous_ +B 35400,25000,300,300,CONT_DIF_P,784nymous_ +B 37000,22000,300,300,CONT_VIA,838nymous_ +B 38200,29400,300,300,CONT_BODY_N,892nymous_ +B 4400,13800,300,300,CONT_DIF_P,946nymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/pot_mpx.vbe b/pdks/symbolic/mpxlib/cells/pot_mpx.vbe new file mode 100644 index 000000000..fd1e07a9f --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pot_mpx.vbe @@ -0,0 +1,42 @@ +ENTITY pot_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT rup : NATURAL := 684404; + CONSTANT rdown : NATURAL := 24 + ); + PORT ( + i : in BIT; + b : in BIT; + pad : out MUX_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pot_mpx; + +ARCHITECTURE behaviour_data_flow OF pot_mpx IS + SIGNAL b1 : BIT; + SIGNAL b2 : BIT; + SIGNAL b3 : BIT; + SIGNAL b4 : BIT; + SIGNAL b5 : BIT; + SIGNAL b6 : BIT; + +BEGIN + b6 <= b5; + b5 <= b4; + b4 <= b3; + b3 <= b2; + b2 <= b1; + b1 <= b; + label0 : BLOCK (b6 = '1') + BEGIN + pad <= GUARDED i; + END BLOCK label0; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pot_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/pvdde_mpx.ap b/pdks/symbolic/mpxlib/cells/pvdde_mpx.ap new file mode 100644 index 000000000..fc09a83a0 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvdde_mpx.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H pvdde_mpx,P,17/9/2014,100 +A 0,0,40000,80000 +I 0,40000,padreal_mpx,padreal,NOSYM +S 31200,6000,32800,6000,12000,13onymous_,RIGHT,TALU2 +S 7200,6000,8800,6000,12000,11onymous_,RIGHT,TALU2 +S 50,6000,2800,6000,12000,10onymous_,RIGHT,TALU2 +S 13200,6000,26800,6000,12000,12onymous_,RIGHT,TALU2 +S 13200,6000,26800,6000,12000,17onymous_,RIGHT,TALU4 +S 37200,6000,39950,6000,12000,14onymous_,RIGHT,TALU2 +S 7200,6000,8800,6000,12000,16onymous_,RIGHT,TALU4 +S 50,6000,2800,6000,12000,15onymous_,RIGHT,TALU4 +S 31200,6000,32800,6000,12000,18onymous_,RIGHT,TALU4 +S 37200,6000,39950,6000,12000,19onymous_,RIGHT,TALU4 +S 23000,18100,23000,59900,4400,21onymous_,UP,ALU1 +S 8000,200,8000,2000,2000,1nonymous_,UP,TALU3 +S 1400,200,1400,2000,3000,0nonymous_,UP,TALU3 +S 0,6000,40000,6000,12000,20onymous_,RIGHT,TALU6 +S 20000,200,20000,2000,14000,2nonymous_,UP,TALU3 +S 32000,200,32000,2000,2000,3nonymous_,UP,TALU3 +S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 +S 38600,200,38600,2000,3000,4nonymous_,UP,TALU3 +S 1400,200,1400,12000,3000,5nonymous_,UP,TALU5 +S 17000,18100,17000,59900,4400,22onymous_,UP,ALU1 +S 20000,200,20000,12000,14000,7nonymous_,UP,TALU5 +S 8000,200,8000,12000,2000,6nonymous_,UP,TALU5 +S 38600,200,38600,12000,3000,9nonymous_,UP,TALU5 +S 32000,200,32000,12000,2000,8nonymous_,UP,TALU5 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 5000,-150,5000,17150,2400,vssi,UP,CALU2 +S 5000,-150,5000,2150,2400,vssi,UP,CALU3 +S 5000,0,5000,2000,2400,vssi,UP,CALU5 +S 5000,0,5000,2000,2400,vssi,UP,CALU4 +S 29000,-150,29000,17150,2400,vssi,UP,CALU2 +S 29000,-150,29000,2150,2400,vssi,UP,CALU3 +S 29000,0,29000,2000,2400,vssi,UP,CALU5 +S 29000,0,29000,2000,2400,vssi,UP,CALU4 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 11000,-150,11000,17150,2400,vddi,UP,CALU2 +S 11000,-150,11000,2150,2400,vddi,UP,CALU3 +S 11000,0,11000,2000,2400,vddi,UP,CALU5 +S 11000,0,11000,2000,2400,vddi,UP,CALU4 +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 35000,-150,35000,17150,2400,vddi,UP,CALU2 +S 35000,-150,35000,2150,2400,vddi,UP,CALU3 +S 35000,0,35000,2000,2400,vddi,UP,CALU5 +S 35000,0,35000,2000,2400,vddi,UP,CALU4 +S 20000,48100,20000,71900,24400,vdde,UP,CALU1 +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +B 11000,16000,2300,2300,CONT_VIA2,48onymous_ +B 17000,34000,4300,2300,CONT_VIA,53onymous_ +B 11000,1000,2300,2300,CONT_VIA3,46onymous_ +B 17000,28000,4300,2300,CONT_VIA,51onymous_ +B 35000,1000,2300,2300,CONT_VIA4,37onymous_ +B 11000,1000,2300,2300,CONT_VIA4,47onymous_ +B 17000,28000,4300,2300,CONT_VIA2,52onymous_ +B 35000,1000,2300,2300,CONT_VIA2,35onymous_ +B 35000,1000,2300,2300,CONT_VIA3,36onymous_ +B 5000,1000,2300,2300,CONT_VIA2,40onymous_ +B 17000,34000,4300,2300,CONT_VIA2,54onymous_ +B 17000,22000,4300,2300,CONT_VIA,49onymous_ +B 5000,7000,2300,2300,CONT_VIA2,39onymous_ +B 5000,1000,2300,2300,CONT_VIA3,41onymous_ +B 35000,16000,2300,2300,CONT_VIA2,38onymous_ +B 5000,1000,2300,2300,CONT_VIA4,42onymous_ +B 5000,13000,2300,2300,CONT_VIA2,43onymous_ +B 17000,22000,4300,2300,CONT_VIA2,50onymous_ +B 23000,28000,4300,2300,CONT_VIA,25onymous_ +B 23000,22000,4300,2300,CONT_VIA,23onymous_ +B 23000,22000,4300,2300,CONT_VIA2,24onymous_ +B 23000,34000,4300,2300,CONT_VIA2,28onymous_ +B 23000,34000,4300,2300,CONT_VIA,27onymous_ +B 23000,28000,4300,2300,CONT_VIA2,26onymous_ +B 29000,1000,2300,2300,CONT_VIA3,31onymous_ +B 29000,1000,2300,2300,CONT_VIA2,30onymous_ +B 29000,7000,2300,2300,CONT_VIA2,29onymous_ +B 29000,13000,2300,2300,CONT_VIA2,33onymous_ +B 11000,1000,2300,2300,CONT_VIA2,45onymous_ +B 29000,1000,2300,2300,CONT_VIA4,32onymous_ +B 11000,10000,2300,2300,CONT_VIA2,44onymous_ +B 35000,10000,2300,2300,CONT_VIA2,34onymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/pvdde_mpx.vbe b/pdks/symbolic/mpxlib/cells/pvdde_mpx.vbe new file mode 100644 index 000000000..43fa446f7 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvdde_mpx.vbe @@ -0,0 +1,20 @@ +ENTITY pvdde_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000 + ); + PORT ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvdde_mpx; + +ARCHITECTURE behaviour_data_flow OF pvdde_mpx IS + +BEGIN + ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1') + REPORT "power supply is missing on pvdde_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/pvddeck_mpx.ap b/pdks/symbolic/mpxlib/cells/pvddeck_mpx.ap new file mode 100644 index 000000000..cc0ee6eef --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvddeck_mpx.ap @@ -0,0 +1,346 @@ +V ALLIANCE : 6 +H pvddeck_mpx,P,18/ 2/2015,100 +A 0,0,40000,80000 +S 19000,-900,19000,400,2400,cko,UP,CALU4 +S 19000,-900,19000,300,2400,cko,UP,CALU5 +S 19000,0,19000,2000,2400,cko,UP,ALU4 +S 19000,0,19000,2000,2400,cko,UP,ALU5 +S 21200,6000,28800,6000,12000,9nonymous_,RIGHT,TALU4 +S 26000,7500,26000,8100,400,123nymous_,UP,ALU1 +S 26600,7500,26600,9500,200,90onymous_,UP,NTRANS +S 11200,6000,16800,6000,12000,8nonymous_,RIGHT,TALU4 +S 30800,7500,30800,9100,400,122nymous_,UP,ALU1 +S 26000,11300,26000,14900,620,89onymous_,UP,PDIF +S 50,6000,2800,6000,12000,6nonymous_,RIGHT,TALU4 +S 28400,7500,28400,8100,400,124nymous_,UP,ALU1 +S 26100,7400,30700,7400,400,125nymous_,RIGHT,ALU1 +S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 +S 25000,13800,33000,13800,6800,87onymous_,RIGHT,NWELL +S 32000,7700,32000,9300,620,120nymous_,UP,NDIF +S 26000,7700,26000,9300,620,88onymous_,UP,NDIF +S 32000,11300,32000,14900,620,121nymous_,UP,PDIF +S 21200,6000,28800,6000,12000,3nonymous_,RIGHT,TALU2 +S 32000,8500,32000,12700,400,85onymous_,UP,ALU1 +S 25880,16200,32120,16200,600,86onymous_,RIGHT,NTIE +S 31400,11100,31400,15100,200,119nymous_,UP,PTRANS +S 37200,6000,39950,6000,12000,5nonymous_,RIGHT,TALU2 +S 11200,6000,16800,6000,12000,2nonymous_,RIGHT,TALU2 +S 27200,8500,27200,9100,400,83onymous_,UP,ALU1 +S 50,6000,2800,6000,12000,0nonymous_,RIGHT,TALU2 +S 25880,6200,32120,6200,600,82onymous_,RIGHT,PTIE +S 29600,8500,29600,9100,400,84onymous_,UP,ALU1 +S 31400,10200,33000,10200,600,118nymous_,RIGHT,POLY +S 12800,850,12800,11350,600,78onymous_,UP,ALU2 +S 31400,7500,31400,9500,200,116nymous_,UP,NTRANS +S 33000,3850,33000,10350,600,81onymous_,UP,ALU2 +S 31400,9800,31400,10800,200,117nymous_,UP,POLY +S 25850,16200,28550,16200,600,79onymous_,RIGHT,ALU2 +S 12800,7700,12800,9300,420,42onymous_,UP,NDIF +S 12200,11100,12200,15100,200,50onymous_,UP,PTRANS +S 10500,9200,12700,9200,400,43onymous_,RIGHT,ALU1 +S 26000,6050,26000,7550,600,80onymous_,UP,ALU2 +S 9800,10200,13400,10200,600,40onymous_,RIGHT,POLY +S 11600,850,11600,11350,600,77onymous_,UP,ALU2 +S 13400,9800,13400,10800,200,39onymous_,UP,POLY +S 9200,12100,9200,14900,400,75onymous_,UP,ALU1 +S 13400,7500,13400,9500,200,38onymous_,UP,NTRANS +S 11600,12300,11600,14900,400,76onymous_,UP,ALU1 +S 30800,11300,30800,14900,620,115nymous_,UP,PDIF +S 13400,11100,13400,15100,200,41onymous_,UP,PTRANS +S 12200,9800,12200,10800,200,49onymous_,UP,POLY +S 14000,12300,14000,14900,400,74onymous_,UP,ALU1 +S 10500,11200,12700,11200,400,47onymous_,RIGHT,ALU1 +S 14000,7500,14000,8100,400,71onymous_,UP,ALU1 +S 12800,11300,12800,14900,620,46onymous_,UP,PDIF +S 30800,7700,30800,9300,420,114nymous_,UP,NDIF +S 14000,11300,14000,14900,620,37onymous_,UP,PDIF +S 11600,7500,11600,8100,400,72onymous_,UP,ALU1 +S 30200,7500,30200,9500,200,111nymous_,UP,NTRANS +S 12200,7500,12200,9500,200,48onymous_,UP,NTRANS +S 9300,7400,13900,7400,400,73onymous_,RIGHT,ALU1 +S 7000,13800,15000,13800,6800,35onymous_,RIGHT,NWELL +S 30200,9800,30200,10800,200,112nymous_,UP,POLY +S 14000,7700,14000,9300,620,36onymous_,UP,NDIF +S 30200,11100,30200,15100,200,113nymous_,UP,PTRANS +S 7880,16200,14120,16200,600,34onymous_,RIGHT,NTIE +S 29600,11300,29600,14900,620,110nymous_,UP,PDIF +S 8000,8500,8000,12700,400,33onymous_,UP,ALU1 +S 29600,11300,29600,13900,400,109nymous_,UP,ALU1 +S 9200,7500,9200,9100,400,70onymous_,UP,ALU1 +S 8100,10200,12700,10200,400,44onymous_,RIGHT,ALU1 +S 8000,11300,8000,14900,620,69onymous_,UP,PDIF +S 29600,7700,29600,9300,420,108nymous_,UP,NDIF +S 12800,11300,12800,13900,400,45onymous_,UP,ALU1 +S 10400,8500,10400,9100,400,32onymous_,UP,ALU1 +S 29000,11100,29000,15100,200,107nymous_,UP,PTRANS +S 12800,8500,12800,9100,400,31onymous_,UP,ALU1 +S 7000,3850,7000,10350,600,29onymous_,UP,ALU2 +S 29000,9800,29000,10800,200,106nymous_,UP,POLY +S 7880,6200,14120,6200,600,30onymous_,RIGHT,PTIE +S 8000,7700,8000,9300,620,68onymous_,UP,NDIF +S 29000,7500,29000,9500,200,105nymous_,UP,NTRANS +S 14000,6050,14000,7550,600,28onymous_,UP,ALU2 +S 28400,11300,28400,14900,620,104nymous_,UP,PDIF +S 11450,16200,14150,16200,600,27onymous_,RIGHT,ALU2 +S 11450,2000,28550,2000,600,26onymous_,RIGHT,ALU3 +S 11450,1000,28550,1000,600,25onymous_,RIGHT,ALU3 +S 1400,200,1400,12000,3000,24onymous_,UP,TALU5 +S 8600,11100,8600,15100,200,67onymous_,UP,PTRANS +S 38600,200,38600,12000,3000,23onymous_,UP,TALU5 +S 7000,10200,8600,10200,600,66onymous_,RIGHT,POLY +S 27800,11100,27800,15100,200,102nymous_,UP,PTRANS +S 28400,7700,28400,9300,620,103nymous_,UP,NDIF +S 7000,200,7000,12000,0,22onymous_,UP,TALU5 +S 27800,7500,27800,9500,200,100nymous_,UP,NTRANS +S 27300,11200,29500,11200,400,99onymous_,RIGHT,ALU1 +S 27200,11300,27200,14900,620,98onymous_,UP,PDIF +S 9200,11300,9200,14900,620,63onymous_,UP,PDIF +S 25000,200,25000,12000,8000,20onymous_,UP,TALU5 +S 27800,9800,27800,10800,200,101nymous_,UP,POLY +S 8600,7500,8600,9500,200,64onymous_,UP,NTRANS +S 14000,200,14000,12000,6000,21onymous_,UP,TALU5 +S 8600,9800,8600,10800,200,65onymous_,UP,POLY +S 27200,11300,27200,13900,400,97onymous_,UP,ALU1 +S 27300,10200,31900,10200,400,96onymous_,RIGHT,ALU1 +S 17000,18100,17000,59900,4400,132nymous_,UP,ALU1 +S 33000,200,33000,12000,0,19onymous_,UP,TALU5 +S 9200,7700,9200,9300,420,62onymous_,UP,NDIF +S 27300,9200,29500,9200,400,95onymous_,RIGHT,ALU1 +S 9800,7500,9800,9500,200,59onymous_,UP,NTRANS +S 23000,18100,23000,59900,4400,131nymous_,UP,ALU1 +S 9800,9800,9800,10800,200,60onymous_,UP,POLY +S 9800,11100,9800,15100,200,61onymous_,UP,PTRANS +S 1400,200,1400,2000,3000,18onymous_,UP,TALU3 +S 28400,12300,28400,14900,400,128nymous_,UP,ALU1 +S 10400,11300,10400,13900,400,57onymous_,UP,ALU1 +S 25000,200,25000,2000,8000,14onymous_,UP,TALU3 +S 28400,850,28400,11350,600,129nymous_,UP,ALU2 +S 10400,11300,10400,14900,620,58onymous_,UP,PDIF +S 14000,200,14000,2000,6000,15onymous_,UP,TALU3 +S 27200,7700,27200,9300,420,94onymous_,UP,NDIF +S 11000,11100,11000,15100,200,55onymous_,UP,PTRANS +S 10400,7700,10400,9300,420,56onymous_,UP,NDIF +S 27200,850,27200,11350,600,130nymous_,UP,ALU2 +S 7000,200,7000,2000,0,16onymous_,UP,TALU3 +S 38600,200,38600,2000,3000,17onymous_,UP,TALU3 +S 11000,9800,11000,10800,200,54onymous_,UP,POLY +S 0,6000,40000,6000,12000,12onymous_,RIGHT,TALU6 +S 26000,12300,26000,14900,400,126nymous_,UP,ALU1 +S 11600,11300,11600,14900,620,52onymous_,UP,PDIF +S 11600,7700,11600,9300,620,51onymous_,UP,NDIF +S 30800,12100,30800,14900,400,127nymous_,UP,ALU1 +S 33000,200,33000,2000,0,13onymous_,UP,TALU3 +S 26600,9800,26600,10800,200,91onymous_,UP,POLY +S 11000,7500,11000,9500,200,53onymous_,UP,NTRANS +S 26600,10200,30200,10200,600,92onymous_,RIGHT,POLY +S 37200,6000,39950,6000,12000,11onymous_,RIGHT,TALU4 +S 26600,11100,26600,15100,200,93onymous_,UP,PTRANS +S 5000,0,5000,2000,2400,vssi,UP,CALU4 +S 31000,0,31000,2000,2400,vssi,UP,CALU4 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 31000,-150,31000,2150,2400,vssi,UP,CALU3 +S 31000,0,31000,2000,2400,vssi,UP,CALU5 +S 26100,6800,31900,6800,1600,vssi,RIGHT,ALU1 +S 8100,6800,13900,6800,1600,vssi,RIGHT,ALU1 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 5000,-150,5000,17150,2400,vssi,UP,CALU2 +S 5000,-150,5000,2150,2400,vssi,UP,CALU3 +S 5000,0,5000,2000,2400,vssi,UP,CALU5 +S 31000,-150,31000,17150,2400,vssi,UP,CALU2 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 9000,-150,9000,17150,2400,vddi,UP,CALU2 +S 9000,-150,9000,2150,2400,vddi,UP,CALU3 +S 9000,0,9000,2000,2400,vddi,UP,CALU5 +S 9000,0,9000,2000,2400,vddi,UP,CALU4 +S 35000,-150,35000,17150,2400,vddi,UP,CALU2 +S 35000,-150,35000,2150,2400,vddi,UP,CALU3 +S 35000,0,35000,2000,2400,vddi,UP,CALU5 +S 35000,0,35000,2000,2400,vddi,UP,CALU4 +S 8100,15600,13900,15600,1600,vddi,RIGHT,ALU1 +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 26100,15600,31900,15600,1600,vddi,RIGHT,ALU1 +S 20000,48100,20000,71900,24400,vdde,UP,CALU1 +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +I 0,40000,padreal_mpx,padreal,NOSYM +B 28400,11200,300,300,CONT_VIA,247nymous_ +B 12800,9200,300,300,CONT_DIF_N,166nymous_ +B 28400,10200,300,300,CONT_POLY,246nymous_ +B 35000,10000,2300,2300,CONT_VIA2,284nymous_ +B 26000,6200,300,300,CONT_VIA2,209nymous_ +B 31000,13000,2300,2300,CONT_VIA2,283nymous_ +B 12800,10200,300,300,CONT_POLY,168nymous_ +B 26000,16200,300,300,CONT_VIA2,208nymous_ +B 12800,9200,300,300,CONT_VIA,167nymous_ +B 31000,1000,2300,2300,CONT_VIA4,282nymous_ +B 27200,16200,300,300,CONT_VIA2,207nymous_ +B 31000,1000,2300,2300,CONT_VIA3,281nymous_ +B 28400,16200,300,300,CONT_VIA2,206nymous_ +B 31000,1000,2300,2300,CONT_VIA2,280nymous_ +B 14000,15000,300,300,CONT_DIF_P,165nymous_ +B 28400,16200,300,300,CONT_VIA,205nymous_ +B 31000,7000,2300,2300,CONT_VIA2,279nymous_ +B 28400,9200,300,300,CONT_VIA,245nymous_ +B 14000,14000,300,300,CONT_DIF_P,164nymous_ +B 27200,16200,300,300,CONT_VIA,204nymous_ +B 23000,34000,4300,2300,CONT_VIA2,278nymous_ +B 28400,8200,300,300,CONT_DIF_N,244nymous_ +B 14000,13000,300,300,CONT_DIF_P,163nymous_ +B 28400,7400,300,300,CONT_DIF_N,243nymous_ +B 26000,16200,300,300,CONT_VIA,203nymous_ +B 23000,34000,4300,2300,CONT_VIA,277nymous_ +B 14000,12200,300,300,CONT_DIF_P,162nymous_ +B 23000,28000,4300,2300,CONT_VIA2,276nymous_ +B 14000,8200,300,300,CONT_DIF_N,161nymous_ +B 27200,14000,300,300,CONT_DIF_P,242nymous_ +B 14000,7400,300,300,CONT_DIF_N,160nymous_ +B 23000,28000,4300,2300,CONT_VIA,275nymous_ +B 23000,22000,4300,2300,CONT_VIA2,274nymous_ +B 27200,12000,300,300,CONT_DIF_P,240nymous_ +B 10400,11200,200,200,CONT_TURN1,159nymous_ +B 27200,11200,300,300,CONT_VIA,239nymous_ +B 14000,16200,300,300,CONT_BODY_N,158nymous_ +B 12800,16200,300,300,CONT_BODY_N,157nymous_ +B 12800,1000,300,300,CONT_VIA2,202nymous_ +B 27200,13000,300,300,CONT_DIF_P,241nymous_ +B 11600,1000,300,300,CONT_VIA2,201nymous_ +B 12800,2000,300,300,CONT_VIA2,200nymous_ +B 9200,16200,300,300,CONT_BODY_N,153nymous_ +B 11600,2000,300,300,CONT_VIA2,199nymous_ +B 23000,22000,4300,2300,CONT_VIA,273nymous_ +B 9200,7400,300,300,CONT_DIF_N,198nymous_ +B 27200,1000,300,300,CONT_VIA2,272nymous_ +B 27200,10200,300,300,CONT_POLY,238nymous_ +B 28400,1000,300,300,CONT_VIA2,271nymous_ +B 27200,9200,300,300,CONT_VIA,237nymous_ +B 11600,16200,300,300,CONT_BODY_N,156nymous_ +B 27200,9200,300,300,CONT_DIF_N,236nymous_ +B 10400,16200,300,300,CONT_BODY_N,155nymous_ +B 26000,15000,300,300,CONT_DIF_P,235nymous_ +B 8000,16200,300,300,CONT_BODY_N,154nymous_ +B 26000,14000,300,300,CONT_DIF_P,234nymous_ +B 33000,10200,300,300,CONT_VIA,267nymous_ +B 26000,13000,300,300,CONT_DIF_P,233nymous_ +B 14000,6200,300,300,CONT_BODY_P,152nymous_ +B 26000,12200,300,300,CONT_DIF_P,232nymous_ +B 26000,8200,300,300,CONT_DIF_N,231nymous_ +B 7000,10200,300,300,CONT_VIA,197nymous_ +B 7000,10200,300,300,CONT_POLY,196nymous_ +B 27200,2000,300,300,CONT_VIA2,270nymous_ +B 8000,12800,300,300,CONT_DIF_P,195nymous_ +B 28400,2000,300,300,CONT_VIA2,269nymous_ +B 30800,7400,300,300,CONT_DIF_N,268nymous_ +B 8000,9200,300,300,CONT_DIF_N,193nymous_ +B 9200,15000,300,300,CONT_DIF_P,192nymous_ +B 33000,10200,300,300,CONT_POLY,266nymous_ +B 12800,6200,300,300,CONT_BODY_P,151nymous_ +B 9200,14000,300,300,CONT_DIF_P,191nymous_ +B 11600,6200,300,300,CONT_BODY_P,150nymous_ +B 26000,7400,300,300,CONT_DIF_N,230nymous_ +B 29600,11200,200,200,CONT_TURN1,229nymous_ +B 8000,11800,300,300,CONT_DIF_P,194nymous_ +B 26000,16200,300,300,CONT_BODY_N,228nymous_ +B 9200,9200,300,300,CONT_DIF_N,188nymous_ +B 9200,6200,300,300,CONT_BODY_P,148nymous_ +B 32000,9200,300,300,CONT_DIF_N,263nymous_ +B 9200,12000,300,300,CONT_DIF_P,189nymous_ +B 10400,6200,300,300,CONT_BODY_P,149nymous_ +B 17000,34000,4300,2300,CONT_VIA2,304nymous_ +B 32000,11800,300,300,CONT_DIF_P,264nymous_ +B 9200,13000,300,300,CONT_DIF_P,190nymous_ +B 19000,1000,2300,2300,CONT_VIA3,305nymous_ +B 32000,12800,300,300,CONT_DIF_P,265nymous_ +B 19000,1000,2300,2300,CONT_VIA4,306nymous_ +B 12800,8400,300,300,CONT_DIF_N,146nymous_ +B 27200,16200,300,300,CONT_BODY_N,227nymous_ +B 8000,6200,300,300,CONT_BODY_P,147nymous_ +B 17000,28000,4300,2300,CONT_VIA2,302nymous_ +B 9200,8200,300,300,CONT_DIF_N,187nymous_ +B 30800,14000,300,300,CONT_DIF_P,261nymous_ +B 30800,15000,300,300,CONT_DIF_P,262nymous_ +B 17000,34000,4300,2300,CONT_VIA,303nymous_ +B 14000,6200,300,300,CONT_VIA,142nymous_ +B 30800,16200,300,300,CONT_BODY_N,223nymous_ +B 7000,4000,300,300,CONT_VIA2,143nymous_ +B 32000,16200,300,300,CONT_BODY_N,224nymous_ +B 10400,12000,300,300,CONT_DIF_P,184nymous_ +B 10400,8400,300,300,CONT_DIF_N,144nymous_ +B 29600,16200,300,300,CONT_BODY_N,225nymous_ +B 30800,12000,300,300,CONT_DIF_P,259nymous_ +B 10400,13000,300,300,CONT_DIF_P,185nymous_ +B 8000,8400,300,300,CONT_DIF_N,145nymous_ +B 17000,22000,4300,2300,CONT_VIA2,300nymous_ +B 28400,16200,300,300,CONT_BODY_N,226nymous_ +B 30800,13000,300,300,CONT_DIF_P,260nymous_ +B 10400,14000,300,300,CONT_DIF_P,186nymous_ +B 17000,28000,4300,2300,CONT_VIA,301nymous_ +B 27200,6200,300,300,CONT_BODY_P,221nymous_ +B 11600,15000,300,300,CONT_DIF_P,181nymous_ +B 14000,7400,300,300,CONT_VIA,141nymous_ +B 9000,1000,2300,2300,CONT_VIA3,296nymous_ +B 26000,6200,300,300,CONT_BODY_P,222nymous_ +B 10400,9200,300,300,CONT_DIF_N,182nymous_ +B 9000,1000,2300,2300,CONT_VIA4,297nymous_ +B 10400,10200,300,300,CONT_POLY,183nymous_ +B 9000,16000,2300,2300,CONT_VIA2,298nymous_ +B 30800,9200,300,300,CONT_DIF_N,258nymous_ +B 17000,22000,4300,2300,CONT_VIA,299nymous_ +B 14000,16200,300,300,CONT_VIA2,138nymous_ +B 14000,6200,300,300,CONT_VIA2,139nymous_ +B 14000,7400,300,300,CONT_VIA2,140nymous_ +B 29600,13000,300,300,CONT_DIF_P,255nymous_ +B 9000,1000,2300,2300,CONT_VIA2,295nymous_ +B 12800,16200,300,300,CONT_VIA,134nymous_ +B 11600,16200,300,300,CONT_VIA,135nymous_ +B 29600,14000,300,300,CONT_DIF_P,256nymous_ +B 11600,16200,300,300,CONT_VIA2,136nymous_ +B 30800,8200,300,300,CONT_DIF_N,257nymous_ +B 12800,16200,300,300,CONT_VIA2,137nymous_ +B 30800,6200,300,300,CONT_BODY_P,218nymous_ +B 11600,14000,300,300,CONT_DIF_P,180nymous_ +B 29600,12000,300,300,CONT_DIF_P,254nymous_ +B 28400,6200,300,300,CONT_BODY_P,220nymous_ +B 11600,13000,300,300,CONT_DIF_P,179nymous_ +B 29600,6200,300,300,CONT_BODY_P,219nymous_ +B 11600,12200,300,300,CONT_DIF_P,178nymous_ +B 9000,10000,2300,2300,CONT_VIA2,294nymous_ +B 29600,10200,300,300,CONT_POLY,253nymous_ +B 5000,13000,2300,2300,CONT_VIA2,293nymous_ +B 29600,9200,300,300,CONT_DIF_N,252nymous_ +B 5000,1000,2300,2300,CONT_VIA4,292nymous_ +B 11600,11200,300,300,CONT_VIA,177nymous_ +B 28400,15000,300,300,CONT_DIF_P,251nymous_ +B 32000,6200,300,300,CONT_BODY_P,217nymous_ +B 5000,1000,2300,2300,CONT_VIA3,291nymous_ +B 11600,10200,300,300,CONT_POLY,176nymous_ +B 27200,8400,300,300,CONT_DIF_N,216nymous_ +B 11600,9200,300,300,CONT_VIA,175nymous_ +B 14000,16200,300,300,CONT_VIA,133nymous_ +B 11600,8200,300,300,CONT_DIF_N,174nymous_ +B 5000,7000,2300,2300,CONT_VIA2,289nymous_ +B 32000,8400,300,300,CONT_DIF_N,215nymous_ +B 5000,1000,2300,2300,CONT_VIA2,290nymous_ +B 28400,14000,300,300,CONT_DIF_P,250nymous_ +B 12800,12000,300,300,CONT_DIF_P,170nymous_ +B 12800,13000,300,300,CONT_DIF_P,171nymous_ +B 26000,6200,300,300,CONT_VIA,212nymous_ +B 12800,14000,300,300,CONT_DIF_P,172nymous_ +B 35000,1000,2300,2300,CONT_VIA4,287nymous_ +B 33000,4000,300,300,CONT_VIA2,213nymous_ +B 11600,7400,300,300,CONT_DIF_N,173nymous_ +B 35000,16000,2300,2300,CONT_VIA2,288nymous_ +B 29600,8400,300,300,CONT_DIF_N,214nymous_ +B 28400,12200,300,300,CONT_DIF_P,248nymous_ +B 28400,13000,300,300,CONT_DIF_P,249nymous_ +B 12800,11200,300,300,CONT_VIA,169nymous_ +B 26000,7400,300,300,CONT_VIA2,210nymous_ +B 35000,1000,2300,2300,CONT_VIA2,285nymous_ +B 26000,7400,300,300,CONT_VIA,211nymous_ +B 35000,1000,2300,2300,CONT_VIA3,286nymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/pvddeck_mpx.vbe b/pdks/symbolic/mpxlib/cells/pvddeck_mpx.vbe new file mode 100644 index 000000000..ddffa4017 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvddeck_mpx.vbe @@ -0,0 +1,31 @@ +ENTITY pvddeck_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_ck : NATURAL := 127; + CONSTANT tpll_ck : NATURAL := 1055; + CONSTANT rdown_ck : NATURAL := 126; + CONSTANT tphh_ck : NATURAL := 963; + CONSTANT rup_ck : NATURAL := 183 + ); + PORT ( + cko : out WOR_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvddeck_mpx; + +ARCHITECTURE behaviour_data_flow OF pvddeck_mpx IS + +BEGIN + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; + + ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1') + REPORT "power supply is missing on pvddeck_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/pvddi_mpx.ap b/pdks/symbolic/mpxlib/cells/pvddi_mpx.ap new file mode 100644 index 000000000..7130e796e --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvddi_mpx.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 6 +H pvddi_mpx,P,17/9/2014,100 +A 0,0,40000,80000 +I 0,40000,padreal_mpx,padreal,NOSYM +S 31200,6000,32800,6000,12000,13onymous_,RIGHT,TALU2 +S 7200,6000,8800,6000,12000,11onymous_,RIGHT,TALU2 +S 50,6000,2800,6000,12000,10onymous_,RIGHT,TALU2 +S 13200,6000,26800,6000,12000,12onymous_,RIGHT,TALU2 +S 13200,6000,26800,6000,12000,17onymous_,RIGHT,TALU4 +S 50,6000,2800,6000,12000,15onymous_,RIGHT,TALU4 +S 37200,6000,39950,6000,12000,14onymous_,RIGHT,TALU2 +S 7200,6000,8800,6000,12000,16onymous_,RIGHT,TALU4 +S 31200,6000,32800,6000,12000,18onymous_,RIGHT,TALU4 +S 37200,6000,39950,6000,12000,19onymous_,RIGHT,TALU4 +S 17000,6100,17000,59900,4400,21onymous_,UP,ALU1 +S 8000,200,8000,2000,2000,1nonymous_,UP,TALU3 +S 1400,200,1400,2000,3000,0nonymous_,UP,TALU3 +S 0,6000,40000,6000,12000,20onymous_,RIGHT,TALU6 +S 20000,200,20000,2000,14000,2nonymous_,UP,TALU3 +S 23000,6100,23000,59900,4400,22onymous_,UP,ALU1 +S 32000,200,32000,2000,2000,3nonymous_,UP,TALU3 +S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 +S 38600,200,38600,2000,3000,4nonymous_,UP,TALU3 +S 1400,200,1400,12000,3000,5nonymous_,UP,TALU5 +S 20000,200,20000,12000,14000,7nonymous_,UP,TALU5 +S 8000,200,8000,12000,2000,6nonymous_,UP,TALU5 +S 32000,200,32000,12000,2000,8nonymous_,UP,TALU5 +S 38600,200,38600,12000,3000,9nonymous_,UP,TALU5 +S 29000,0,29000,2000,2400,vssi,UP,CALU4 +S 29000,0,29000,2000,2400,vssi,UP,CALU5 +S 29000,-150,29000,2150,2400,vssi,UP,CALU3 +S 29000,-150,29000,17150,2400,vssi,UP,CALU2 +S 5000,0,5000,2000,2400,vssi,UP,CALU4 +S 5000,0,5000,2000,2400,vssi,UP,CALU5 +S 5000,-150,5000,2150,2400,vssi,UP,CALU3 +S 5000,-150,5000,17150,2400,vssi,UP,CALU2 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 11000,0,11000,2000,2400,vddi,UP,CALU5 +S 11000,0,11000,2000,2400,vddi,UP,CALU4 +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 35000,-150,35000,17150,2400,vddi,UP,CALU2 +S 35000,-150,35000,2150,2400,vddi,UP,CALU3 +S 35000,0,35000,2000,2400,vddi,UP,CALU5 +S 35000,0,35000,2000,2400,vddi,UP,CALU4 +S 20000,48100,20000,71900,24400,vddi,UP,CALU1 +S 11000,-150,11000,17150,2400,vddi,UP,CALU2 +S 11000,-150,11000,2150,2400,vddi,UP,CALU3 +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +B 29000,7000,2300,2300,CONT_VIA2,46onymous_ +B 35000,16000,2300,2300,CONT_VIA2,37onymous_ +B 23000,16000,4300,2300,CONT_VIA2,47onymous_ +B 5000,1000,2300,2300,CONT_VIA2,35onymous_ +B 5000,7000,2300,2300,CONT_VIA2,36onymous_ +B 23000,16000,4300,2300,CONT_VIA,48onymous_ +B 35000,1000,2300,2300,CONT_VIA4,38onymous_ +B 35000,10000,2300,2300,CONT_VIA2,41onymous_ +B 35000,1000,2300,2300,CONT_VIA2,40onymous_ +B 23000,10000,4300,2300,CONT_VIA2,49onymous_ +B 35000,1000,2300,2300,CONT_VIA3,39onymous_ +B 29000,13000,2300,2300,CONT_VIA2,42onymous_ +B 29000,1000,2300,2300,CONT_VIA4,43onymous_ +B 23000,10000,4300,2300,CONT_VIA,50onymous_ +B 17000,10000,4300,2300,CONT_VIA2,25onymous_ +B 17000,16000,4300,2300,CONT_VIA2,23onymous_ +B 17000,16000,4300,2300,CONT_VIA,24onymous_ +B 11000,1000,2300,2300,CONT_VIA4,28onymous_ +B 17000,10000,4300,2300,CONT_VIA,26onymous_ +B 11000,16000,2300,2300,CONT_VIA2,27onymous_ +B 11000,10000,2300,2300,CONT_VIA2,31onymous_ +B 11000,1000,2300,2300,CONT_VIA2,30onymous_ +B 11000,1000,2300,2300,CONT_VIA3,29onymous_ +B 29000,1000,2300,2300,CONT_VIA2,45onymous_ +B 5000,1000,2300,2300,CONT_VIA4,33onymous_ +B 5000,13000,2300,2300,CONT_VIA2,32onymous_ +B 29000,1000,2300,2300,CONT_VIA3,44onymous_ +B 5000,1000,2300,2300,CONT_VIA3,34onymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/pvddi_mpx.vbe b/pdks/symbolic/mpxlib/cells/pvddi_mpx.vbe new file mode 100644 index 000000000..cb25d3395 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvddi_mpx.vbe @@ -0,0 +1,20 @@ +ENTITY pvddi_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000 + ); + PORT ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvddi_mpx; + +ARCHITECTURE behaviour_data_flow OF pvddi_mpx IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvddi_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/pvddick_mpx.ap b/pdks/symbolic/mpxlib/cells/pvddick_mpx.ap new file mode 100644 index 000000000..8dad4a015 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvddick_mpx.ap @@ -0,0 +1,342 @@ +V ALLIANCE : 6 +H pvddick_mpx,P,18/ 2/2015,100 +A 0,0,40000,80000 +S 19000,-900,19000,400,2400,cko,UP,CALU4 +S 19000,-900,19000,400,2400,cko,UP,CALU5 +S 19000,0,19000,2000,2400,cko,UP,ALU4 +S 19000,0,19000,2000,2400,cko,UP,ALU5 +S 12800,11300,12800,13900,400,89onymous_,UP,ALU1 +S 28400,12300,28400,14900,400,6nonymous_,UP,ALU1 +S 30800,12100,30800,14900,400,7nonymous_,UP,ALU1 +S 8100,10200,12700,10200,400,90onymous_,RIGHT,ALU1 +S 21200,6000,28800,6000,12000,123nymous_,RIGHT,TALU4 +S 26000,12300,26000,14900,400,8nonymous_,UP,ALU1 +S 11200,6000,16800,6000,12000,124nymous_,RIGHT,TALU4 +S 26100,7400,30700,7400,400,9nonymous_,RIGHT,ALU1 +S 37200,6000,39950,6000,12000,121nymous_,RIGHT,TALU4 +S 12800,11300,12800,14900,620,88onymous_,UP,PDIF +S 28400,850,28400,11350,600,5nonymous_,UP,ALU2 +S 0,6000,40000,6000,12000,120nymous_,RIGHT,TALU6 +S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 +S 12200,7500,12200,9500,200,86onymous_,UP,NTRANS +S 27200,850,27200,11350,600,4nonymous_,UP,ALU2 +S 33000,200,33000,2000,0,119nymous_,UP,TALU3 +S 10500,11200,12700,11200,400,87onymous_,RIGHT,ALU1 +S 23000,6100,23000,59900,4400,3nonymous_,UP,ALU1 +S 12200,9800,12200,10800,200,85onymous_,UP,POLY +S 11600,11300,11600,14900,620,82onymous_,UP,PDIF +S 17000,6100,17000,59900,4400,2nonymous_,UP,ALU1 +S 11450,2000,28550,2000,600,1nonymous_,RIGHT,ALU3 +S 11450,1000,28550,1000,600,0nonymous_,RIGHT,ALU3 +S 25000,200,25000,2000,8000,118nymous_,UP,TALU3 +S 11600,7700,11600,9300,620,83onymous_,UP,NDIF +S 12200,11100,12200,15100,200,84onymous_,UP,PTRANS +S 29600,8500,29600,9100,400,50onymous_,UP,ALU1 +S 26600,9800,26600,10800,200,43onymous_,UP,POLY +S 11000,7500,11000,9500,200,81onymous_,UP,NTRANS +S 11000,11100,11000,15100,200,79onymous_,UP,PTRANS +S 11000,9800,11000,10800,200,80onymous_,UP,POLY +S 26600,10200,30200,10200,600,42onymous_,RIGHT,POLY +S 7000,200,7000,2000,0,116nymous_,UP,TALU3 +S 10400,7700,10400,9300,420,78onymous_,UP,NDIF +S 14000,200,14000,2000,6000,117nymous_,UP,TALU3 +S 10400,11300,10400,14900,620,76onymous_,UP,PDIF +S 9800,7500,9800,9500,200,75onymous_,UP,NTRANS +S 32000,8500,32000,12700,400,49onymous_,UP,ALU1 +S 26600,11100,26600,15100,200,41onymous_,UP,PTRANS +S 9800,9800,9800,10800,200,74onymous_,UP,POLY +S 38600,200,38600,2000,3000,115nymous_,UP,TALU3 +S 27300,10200,31900,10200,400,38onymous_,RIGHT,ALU1 +S 10400,11300,10400,13900,400,77onymous_,UP,ALU1 +S 27300,9200,29500,9200,400,39onymous_,RIGHT,ALU1 +S 27200,7700,27200,9300,420,40onymous_,UP,NDIF +S 27200,11300,27200,13900,400,37onymous_,UP,ALU1 +S 1400,200,1400,2000,3000,114nymous_,UP,TALU3 +S 27200,11300,27200,14900,620,36onymous_,UP,PDIF +S 33000,200,33000,12000,0,113nymous_,UP,TALU5 +S 25000,200,25000,12000,8000,112nymous_,UP,TALU5 +S 9800,11100,9800,15100,200,73onymous_,UP,PTRANS +S 25880,16200,32120,16200,600,48onymous_,RIGHT,NTIE +S 9200,11300,9200,14900,620,71onymous_,UP,PDIF +S 26000,7700,26000,9300,620,46onymous_,UP,NDIF +S 9200,7700,9200,9300,420,72onymous_,UP,NDIF +S 27300,11200,29500,11200,400,35onymous_,RIGHT,ALU1 +S 25000,13800,33000,13800,6800,47onymous_,RIGHT,NWELL +S 14000,200,14000,12000,6000,111nymous_,UP,TALU5 +S 26600,7500,26600,9500,200,44onymous_,UP,NTRANS +S 27800,11100,27800,15100,200,32onymous_,UP,PTRANS +S 8600,9800,8600,10800,200,69onymous_,UP,POLY +S 1400,200,1400,12000,3000,108nymous_,UP,TALU5 +S 8600,7500,8600,9500,200,70onymous_,UP,NTRANS +S 27800,9800,27800,10800,200,33onymous_,UP,POLY +S 38600,200,38600,12000,3000,109nymous_,UP,TALU5 +S 26000,11300,26000,14900,620,45onymous_,UP,PDIF +S 27800,7500,27800,9500,200,34onymous_,UP,NTRANS +S 7000,200,7000,12000,0,110nymous_,UP,TALU5 +S 11450,16200,14150,16200,600,107nymous_,RIGHT,ALU2 +S 28400,11300,28400,14900,620,30onymous_,UP,PDIF +S 29000,7500,29000,9500,200,29onymous_,UP,NTRANS +S 14000,6050,14000,7550,600,106nymous_,UP,ALU2 +S 7000,10200,8600,10200,600,68onymous_,RIGHT,POLY +S 28400,7700,28400,9300,620,31onymous_,UP,NDIF +S 7000,3850,7000,10350,600,105nymous_,UP,ALU2 +S 29000,9800,29000,10800,200,28onymous_,UP,POLY +S 7880,6200,14120,6200,600,104nymous_,RIGHT,PTIE +S 29000,11100,29000,15100,200,27onymous_,UP,PTRANS +S 29600,7700,29600,9300,420,26onymous_,UP,NDIF +S 8000,7700,8000,9300,620,66onymous_,UP,NDIF +S 30200,9800,30200,10800,200,22onymous_,UP,POLY +S 12800,8500,12800,9100,400,103nymous_,UP,ALU1 +S 29600,11300,29600,14900,620,24onymous_,UP,PDIF +S 8600,11100,8600,15100,200,67onymous_,UP,PTRANS +S 30200,7500,30200,9500,200,23onymous_,UP,NTRANS +S 29600,11300,29600,13900,400,25onymous_,UP,ALU1 +S 10400,8500,10400,9100,400,102nymous_,UP,ALU1 +S 14000,7700,14000,9300,620,98onymous_,UP,NDIF +S 8000,11300,8000,14900,620,65onymous_,UP,PDIF +S 30200,11100,30200,15100,200,21onymous_,UP,PTRANS +S 9200,7500,9200,9100,400,64onymous_,UP,ALU1 +S 30800,7700,30800,9300,420,20onymous_,UP,NDIF +S 7880,16200,14120,16200,600,100nymous_,RIGHT,NTIE +S 7000,13800,15000,13800,6800,99onymous_,RIGHT,NWELL +S 8000,8500,8000,12700,400,101nymous_,UP,ALU1 +S 14000,7500,14000,8100,400,63onymous_,UP,ALU1 +S 30800,11300,30800,14900,620,19onymous_,UP,PDIF +S 13400,9800,13400,10800,200,95onymous_,UP,POLY +S 11600,7500,11600,8100,400,62onymous_,UP,ALU1 +S 31400,7500,31400,9500,200,18onymous_,UP,NTRANS +S 14000,12300,14000,14900,400,60onymous_,UP,ALU1 +S 50,6000,2800,6000,12000,132nymous_,RIGHT,TALU2 +S 9300,7400,13900,7400,400,61onymous_,RIGHT,ALU1 +S 13400,7500,13400,9500,200,96onymous_,UP,NTRANS +S 14000,11300,14000,14900,620,97onymous_,UP,PDIF +S 9200,12100,9200,14900,400,59onymous_,UP,ALU1 +S 25850,16200,28550,16200,600,55onymous_,RIGHT,ALU2 +S 31400,10200,33000,10200,600,16onymous_,RIGHT,POLY +S 26000,6050,26000,7550,600,54onymous_,UP,ALU2 +S 9800,10200,13400,10200,600,94onymous_,RIGHT,POLY +S 12800,850,12800,11350,600,56onymous_,UP,ALU2 +S 31400,9800,31400,10800,200,17onymous_,UP,POLY +S 11600,850,11600,11350,600,57onymous_,UP,ALU2 +S 21200,6000,28800,6000,12000,129nymous_,RIGHT,TALU2 +S 32000,7700,32000,9300,620,14onymous_,UP,NDIF +S 11600,12300,11600,14900,400,58onymous_,UP,ALU1 +S 11200,6000,16800,6000,12000,130nymous_,RIGHT,TALU2 +S 31400,11100,31400,15100,200,15onymous_,UP,PTRANS +S 12800,7700,12800,9300,420,92onymous_,UP,NDIF +S 33000,3850,33000,10350,600,53onymous_,UP,ALU2 +S 37200,6000,39950,6000,12000,127nymous_,RIGHT,TALU2 +S 30800,7500,30800,9100,400,12onymous_,UP,ALU1 +S 50,6000,2800,6000,12000,126nymous_,RIGHT,TALU4 +S 28400,7500,28400,8100,400,10onymous_,UP,ALU1 +S 13400,11100,13400,15100,200,93onymous_,UP,PTRANS +S 26000,7500,26000,8100,400,11onymous_,UP,ALU1 +S 32000,11300,32000,14900,620,13onymous_,UP,PDIF +S 27200,8500,27200,9100,400,51onymous_,UP,ALU1 +S 25880,6200,32120,6200,600,52onymous_,RIGHT,PTIE +S 10500,9200,12700,9200,400,91onymous_,RIGHT,ALU1 +S 31000,0,31000,2000,2400,vssi,UP,CALU5 +S 31000,-150,31000,2150,2400,vssi,UP,CALU3 +S 31000,-150,31000,17150,2400,vssi,UP,CALU2 +S 5000,0,5000,2000,2400,vssi,UP,CALU4 +S 5000,0,5000,2000,2400,vssi,UP,CALU5 +S 5000,-150,5000,2150,2400,vssi,UP,CALU3 +S 5000,-150,5000,17150,2400,vssi,UP,CALU2 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 8100,6800,13900,6800,1600,vssi,RIGHT,ALU1 +S 26100,6800,31900,6800,1600,vssi,RIGHT,ALU1 +S 31000,0,31000,2000,2400,vssi,UP,CALU4 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 35000,0,35000,2000,2400,vddi,UP,CALU4 +S 35000,0,35000,2000,2400,vddi,UP,CALU5 +S 35000,-150,35000,2150,2400,vddi,UP,CALU3 +S 35000,-150,35000,17150,2400,vddi,UP,CALU2 +S 9000,0,9000,2000,2400,vddi,UP,CALU4 +S 9000,0,9000,2000,2400,vddi,UP,CALU5 +S 9000,-150,9000,2150,2400,vddi,UP,CALU3 +S 9000,-150,9000,17150,2400,vddi,UP,CALU2 +S 26100,15600,31900,15600,1600,vddi,RIGHT,ALU1 +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 8100,15600,13900,15600,1600,vddi,RIGHT,ALU1 +S 20000,48100,20000,71900,24400,vddi,UP,CALU1 +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +I 0,40000,padreal_mpx,padreal,NOSYM +B 9200,9200,300,300,CONT_DIF_N,247nymous_ +B 28400,2000,300,300,CONT_VIA2,166nymous_ +B 9200,12000,300,300,CONT_DIF_P,246nymous_ +B 12800,6200,300,300,CONT_BODY_P,284nymous_ +B 28400,16200,300,300,CONT_BODY_N,209nymous_ +B 14000,6200,300,300,CONT_BODY_P,283nymous_ +B 33000,10200,300,300,CONT_VIA,168nymous_ +B 27200,16200,300,300,CONT_BODY_N,208nymous_ +B 30800,7400,300,300,CONT_DIF_N,167nymous_ +B 9200,16200,300,300,CONT_BODY_N,282nymous_ +B 26000,16200,300,300,CONT_BODY_N,207nymous_ +B 8000,16200,300,300,CONT_BODY_N,281nymous_ +B 29600,11200,200,200,CONT_TURN1,206nymous_ +B 10400,16200,300,300,CONT_BODY_N,280nymous_ +B 27200,2000,300,300,CONT_VIA2,165nymous_ +B 26000,7400,300,300,CONT_DIF_N,205nymous_ +B 11600,16200,300,300,CONT_BODY_N,279nymous_ +B 9200,13000,300,300,CONT_DIF_P,245nymous_ +B 28400,1000,300,300,CONT_VIA2,164nymous_ +B 26000,8200,300,300,CONT_DIF_N,204nymous_ +B 12800,16200,300,300,CONT_BODY_N,278nymous_ +B 9200,14000,300,300,CONT_DIF_P,244nymous_ +B 27200,1000,300,300,CONT_VIA2,163nymous_ +B 9200,15000,300,300,CONT_DIF_P,243nymous_ +B 26000,12200,300,300,CONT_DIF_P,203nymous_ +B 14000,16200,300,300,CONT_BODY_N,277nymous_ +B 23000,10000,4300,2300,CONT_VIA,162nymous_ +B 10400,11200,200,200,CONT_TURN1,276nymous_ +B 23000,10000,4300,2300,CONT_VIA2,161nymous_ +B 8000,9200,300,300,CONT_DIF_N,242nymous_ +B 23000,16000,4300,2300,CONT_VIA,160nymous_ +B 14000,7400,300,300,CONT_DIF_N,275nymous_ +B 14000,8200,300,300,CONT_DIF_N,274nymous_ +B 8000,12800,300,300,CONT_DIF_P,240nymous_ +B 23000,16000,4300,2300,CONT_VIA2,159nymous_ +B 7000,10200,300,300,CONT_POLY,239nymous_ +B 31000,7000,2300,2300,CONT_VIA2,158nymous_ +B 31000,1000,2300,2300,CONT_VIA2,157nymous_ +B 26000,13000,300,300,CONT_DIF_P,202nymous_ +B 8000,11800,300,300,CONT_DIF_P,241nymous_ +B 26000,14000,300,300,CONT_DIF_P,201nymous_ +B 26000,15000,300,300,CONT_DIF_P,200nymous_ +B 35000,10000,2300,2300,CONT_VIA2,153nymous_ +B 27200,9200,300,300,CONT_DIF_N,199nymous_ +B 14000,12200,300,300,CONT_DIF_P,273nymous_ +B 27200,9200,300,300,CONT_VIA,198nymous_ +B 14000,13000,300,300,CONT_DIF_P,272nymous_ +B 7000,10200,300,300,CONT_VIA,238nymous_ +B 14000,14000,300,300,CONT_DIF_P,271nymous_ +B 9200,7400,300,300,CONT_DIF_N,237nymous_ +B 31000,1000,2300,2300,CONT_VIA3,156nymous_ +B 11600,2000,300,300,CONT_VIA2,236nymous_ +B 31000,1000,2300,2300,CONT_VIA4,155nymous_ +B 12800,2000,300,300,CONT_VIA2,235nymous_ +B 31000,13000,2300,2300,CONT_VIA2,154nymous_ +B 11600,1000,300,300,CONT_VIA2,234nymous_ +B 12800,10200,300,300,CONT_POLY,267nymous_ +B 12800,1000,300,300,CONT_VIA2,233nymous_ +B 35000,1000,2300,2300,CONT_VIA2,152nymous_ +B 26000,16200,300,300,CONT_VIA,232nymous_ +B 27200,16200,300,300,CONT_VIA,231nymous_ +B 27200,10200,300,300,CONT_POLY,197nymous_ +B 27200,11200,300,300,CONT_VIA,196nymous_ +B 14000,15000,300,300,CONT_DIF_P,270nymous_ +B 27200,12000,300,300,CONT_DIF_P,195nymous_ +B 12800,9200,300,300,CONT_DIF_N,269nymous_ +B 12800,9200,300,300,CONT_VIA,268nymous_ +B 27200,14000,300,300,CONT_DIF_P,193nymous_ +B 28400,7400,300,300,CONT_DIF_N,192nymous_ +B 12800,11200,300,300,CONT_VIA,266nymous_ +B 35000,1000,2300,2300,CONT_VIA3,151nymous_ +B 28400,8200,300,300,CONT_DIF_N,191nymous_ +B 35000,1000,2300,2300,CONT_VIA4,150nymous_ +B 28400,16200,300,300,CONT_VIA,230nymous_ +B 28400,16200,300,300,CONT_VIA2,229nymous_ +B 27200,13000,300,300,CONT_DIF_P,194nymous_ +B 27200,16200,300,300,CONT_VIA2,228nymous_ +B 28400,11200,300,300,CONT_VIA,188nymous_ +B 5000,7000,2300,2300,CONT_VIA2,148nymous_ +B 12800,14000,300,300,CONT_DIF_P,263nymous_ +B 28400,10200,300,300,CONT_POLY,189nymous_ +B 35000,16000,2300,2300,CONT_VIA2,149nymous_ +B 12800,13000,300,300,CONT_DIF_P,264nymous_ +B 28400,9200,300,300,CONT_VIA,190nymous_ +B 12800,12000,300,300,CONT_DIF_P,265nymous_ +B 5000,1000,2300,2300,CONT_VIA3,146nymous_ +B 26000,16200,300,300,CONT_VIA2,227nymous_ +B 5000,1000,2300,2300,CONT_VIA2,147nymous_ +B 14000,16200,300,300,CONT_VIA,302nymous_ +B 28400,12200,300,300,CONT_DIF_P,187nymous_ +B 11600,8200,300,300,CONT_DIF_N,261nymous_ +B 11600,7400,300,300,CONT_DIF_N,262nymous_ +B 9000,1000,2300,2300,CONT_VIA2,142nymous_ +B 26000,6200,300,300,CONT_VIA,223nymous_ +B 9000,10000,2300,2300,CONT_VIA2,143nymous_ +B 26000,7400,300,300,CONT_VIA,224nymous_ +B 28400,15000,300,300,CONT_DIF_P,184nymous_ +B 5000,13000,2300,2300,CONT_VIA2,144nymous_ +B 26000,7400,300,300,CONT_VIA2,225nymous_ +B 11600,10200,300,300,CONT_POLY,259nymous_ +B 28400,14000,300,300,CONT_DIF_P,185nymous_ +B 5000,1000,2300,2300,CONT_VIA4,145nymous_ +B 11600,16200,300,300,CONT_VIA,300nymous_ +B 26000,6200,300,300,CONT_VIA2,226nymous_ +B 11600,9200,300,300,CONT_VIA,260nymous_ +B 28400,13000,300,300,CONT_DIF_P,186nymous_ +B 12800,16200,300,300,CONT_VIA,301nymous_ +B 29600,8400,300,300,CONT_DIF_N,221nymous_ +B 29600,12000,300,300,CONT_DIF_P,181nymous_ +B 9000,1000,2300,2300,CONT_VIA3,141nymous_ +B 14000,6200,300,300,CONT_VIA2,296nymous_ +B 33000,4000,300,300,CONT_VIA2,222nymous_ +B 29600,10200,300,300,CONT_POLY,182nymous_ +B 14000,16200,300,300,CONT_VIA2,297nymous_ +B 29600,9200,300,300,CONT_DIF_N,183nymous_ +B 12800,16200,300,300,CONT_VIA2,298nymous_ +B 11600,11200,300,300,CONT_VIA,258nymous_ +B 11600,16200,300,300,CONT_VIA2,299nymous_ +B 17000,10000,4300,2300,CONT_VIA,138nymous_ +B 9000,16000,2300,2300,CONT_VIA2,139nymous_ +B 9000,1000,2300,2300,CONT_VIA4,140nymous_ +B 11600,14000,300,300,CONT_DIF_P,255nymous_ +B 14000,7400,300,300,CONT_VIA2,295nymous_ +B 19000,1000,2300,2300,CONT_VIA3,134nymous_ +B 17000,16000,4300,2300,CONT_VIA2,135nymous_ +B 11600,13000,300,300,CONT_DIF_P,256nymous_ +B 17000,16000,4300,2300,CONT_VIA,136nymous_ +B 11600,12200,300,300,CONT_DIF_P,257nymous_ +B 17000,10000,4300,2300,CONT_VIA2,137nymous_ +B 32000,6200,300,300,CONT_BODY_P,218nymous_ +B 29600,13000,300,300,CONT_DIF_P,180nymous_ +B 11600,15000,300,300,CONT_DIF_P,254nymous_ +B 32000,8400,300,300,CONT_DIF_N,220nymous_ +B 29600,14000,300,300,CONT_DIF_P,179nymous_ +B 27200,8400,300,300,CONT_DIF_N,219nymous_ +B 30800,8200,300,300,CONT_DIF_N,178nymous_ +B 14000,7400,300,300,CONT_VIA,294nymous_ +B 10400,9200,300,300,CONT_DIF_N,253nymous_ +B 14000,6200,300,300,CONT_VIA,293nymous_ +B 10400,10200,300,300,CONT_POLY,252nymous_ +B 7000,4000,300,300,CONT_VIA2,292nymous_ +B 30800,9200,300,300,CONT_DIF_N,177nymous_ +B 10400,12000,300,300,CONT_DIF_P,251nymous_ +B 30800,6200,300,300,CONT_BODY_P,217nymous_ +B 10400,8400,300,300,CONT_DIF_N,291nymous_ +B 30800,12000,300,300,CONT_DIF_P,176nymous_ +B 29600,6200,300,300,CONT_BODY_P,216nymous_ +B 30800,13000,300,300,CONT_DIF_P,175nymous_ +B 19000,1000,2300,2300,CONT_VIA4,133nymous_ +B 30800,14000,300,300,CONT_DIF_P,174nymous_ +B 12800,8400,300,300,CONT_DIF_N,289nymous_ +B 28400,6200,300,300,CONT_BODY_P,215nymous_ +B 8000,8400,300,300,CONT_DIF_N,290nymous_ +B 10400,13000,300,300,CONT_DIF_P,250nymous_ +B 32000,12800,300,300,CONT_DIF_P,170nymous_ +B 32000,11800,300,300,CONT_DIF_P,171nymous_ +B 30800,16200,300,300,CONT_BODY_N,212nymous_ +B 32000,9200,300,300,CONT_DIF_N,172nymous_ +B 9200,6200,300,300,CONT_BODY_P,287nymous_ +B 26000,6200,300,300,CONT_BODY_P,213nymous_ +B 30800,15000,300,300,CONT_DIF_P,173nymous_ +B 8000,6200,300,300,CONT_BODY_P,288nymous_ +B 27200,6200,300,300,CONT_BODY_P,214nymous_ +B 9200,8200,300,300,CONT_DIF_N,248nymous_ +B 10400,14000,300,300,CONT_DIF_P,249nymous_ +B 33000,10200,300,300,CONT_POLY,169nymous_ +B 29600,16200,300,300,CONT_BODY_N,210nymous_ +B 11600,6200,300,300,CONT_BODY_P,285nymous_ +B 32000,16200,300,300,CONT_BODY_N,211nymous_ +B 10400,6200,300,300,CONT_BODY_P,286nymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/pvddick_mpx.vbe b/pdks/symbolic/mpxlib/cells/pvddick_mpx.vbe new file mode 100644 index 000000000..a195fbd68 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvddick_mpx.vbe @@ -0,0 +1,31 @@ +ENTITY pvddick_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_ck : NATURAL := 127; + CONSTANT tpll_ck : NATURAL := 1235; + CONSTANT rdown_ck : NATURAL := 253; + CONSTANT tphh_ck : NATURAL := 1109; + CONSTANT rup_ck : NATURAL := 311 + ); + PORT ( + cko : out WOR_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvddick_mpx; + +ARCHITECTURE behaviour_data_flow OF pvddick_mpx IS + +BEGIN + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvddick_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/pvsse_mpx.ap b/pdks/symbolic/mpxlib/cells/pvsse_mpx.ap new file mode 100644 index 000000000..cdee174c5 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvsse_mpx.ap @@ -0,0 +1,94 @@ +V ALLIANCE : 6 +H pvsse_mpx,P,17/9/2014,100 +A 0,0,40000,80000 +I 0,40000,padreal_mpx,padreal,NOSYM +S 31200,6000,32800,6000,12000,13onymous_,RIGHT,TALU2 +S 7200,6000,8800,6000,12000,11onymous_,RIGHT,TALU2 +S 50,6000,2800,6000,12000,10onymous_,RIGHT,TALU2 +S 13200,6000,26800,6000,12000,12onymous_,RIGHT,TALU2 +S 37200,6000,39950,6000,12000,14onymous_,RIGHT,TALU2 +S 7200,6000,8800,6000,12000,16onymous_,RIGHT,TALU4 +S 50,6000,2800,6000,12000,15onymous_,RIGHT,TALU4 +S 13200,6000,26800,6000,12000,17onymous_,RIGHT,TALU4 +S 31200,6000,32800,6000,12000,18onymous_,RIGHT,TALU4 +S 37200,6000,39950,6000,12000,19onymous_,RIGHT,TALU4 +S 17000,18100,17000,59900,4400,21onymous_,UP,ALU1 +S 8000,200,8000,2000,2000,1nonymous_,UP,TALU3 +S 1400,200,1400,2000,3000,0nonymous_,UP,TALU3 +S 0,6000,40000,6000,12000,20onymous_,RIGHT,TALU6 +S 20000,200,20000,2000,14000,2nonymous_,UP,TALU3 +S 1400,200,1400,12000,3000,5nonymous_,UP,TALU5 +S 38600,200,38600,2000,3000,4nonymous_,UP,TALU3 +S 23000,18100,23000,59900,4400,22onymous_,UP,ALU1 +S 32000,200,32000,2000,2000,3nonymous_,UP,TALU3 +S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 +S 20000,200,20000,12000,14000,7nonymous_,UP,TALU5 +S 8000,200,8000,12000,2000,6nonymous_,UP,TALU5 +S 38600,200,38600,12000,3000,9nonymous_,UP,TALU5 +S 32000,200,32000,12000,2000,8nonymous_,UP,TALU5 +S 29000,0,29000,2000,2400,vssi,UP,CALU4 +S 29000,0,29000,2000,2400,vssi,UP,CALU5 +S 29000,-150,29000,2150,2400,vssi,UP,CALU3 +S 29000,-150,29000,17150,2400,vssi,UP,CALU2 +S 5000,0,5000,2000,2400,vssi,UP,CALU4 +S 5000,0,5000,2000,2400,vssi,UP,CALU5 +S 5000,-150,5000,2150,2400,vssi,UP,CALU3 +S 5000,-150,5000,17150,2400,vssi,UP,CALU2 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 20000,48100,20000,71900,24400,vsse,UP,CALU1 +S 35000,0,35000,2000,2400,vddi,UP,CALU4 +S 35000,0,35000,2000,2400,vddi,UP,CALU5 +S 35000,-150,35000,2150,2400,vddi,UP,CALU3 +S 35000,-150,35000,17150,2400,vddi,UP,CALU2 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 11000,0,11000,2000,2400,vddi,UP,CALU4 +S 11000,0,11000,2000,2400,vddi,UP,CALU5 +S 11000,-150,11000,2150,2400,vddi,UP,CALU3 +S 11000,-150,11000,17150,2400,vddi,UP,CALU2 +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +B 29000,1000,2300,2300,CONT_VIA3,48onymous_ +B 23000,37000,4300,2300,CONT_VIA2,53onymous_ +B 29000,13000,2300,2300,CONT_VIA2,46onymous_ +B 23000,19000,4300,2300,CONT_VIA2,51onymous_ +B 5000,1000,2300,2300,CONT_VIA4,37onymous_ +B 29000,1000,2300,2300,CONT_VIA4,47onymous_ +B 23000,19000,4300,2300,CONT_VIA,52onymous_ +B 11000,10000,2300,2300,CONT_VIA2,35onymous_ +B 5000,13000,2300,2300,CONT_VIA2,36onymous_ +B 5000,7000,2300,2300,CONT_VIA2,40onymous_ +B 23000,25000,4300,2300,CONT_VIA2,57onymous_ +B 23000,37000,4300,2300,CONT_VIA,54onymous_ +B 29000,1000,2300,2300,CONT_VIA2,49onymous_ +B 5000,1000,2300,2300,CONT_VIA2,39onymous_ +B 23000,31000,4300,2300,CONT_VIA,56onymous_ +B 23000,25000,4300,2300,CONT_VIA,58onymous_ +B 35000,16000,2300,2300,CONT_VIA2,41onymous_ +B 5000,1000,2300,2300,CONT_VIA3,38onymous_ +B 23000,31000,4300,2300,CONT_VIA2,55onymous_ +B 35000,1000,2300,2300,CONT_VIA4,42onymous_ +B 35000,1000,2300,2300,CONT_VIA3,43onymous_ +B 29000,7000,2300,2300,CONT_VIA2,50onymous_ +B 17000,19000,4300,2300,CONT_VIA,24onymous_ +B 17000,19000,4300,2300,CONT_VIA2,23onymous_ +B 17000,37000,4300,2300,CONT_VIA2,25onymous_ +B 17000,31000,4300,2300,CONT_VIA,28onymous_ +B 17000,31000,4300,2300,CONT_VIA2,27onymous_ +B 17000,37000,4300,2300,CONT_VIA,26onymous_ +B 11000,16000,2300,2300,CONT_VIA2,31onymous_ +B 17000,25000,4300,2300,CONT_VIA,30onymous_ +B 17000,25000,4300,2300,CONT_VIA2,29onymous_ +B 11000,1000,2300,2300,CONT_VIA3,33onymous_ +B 35000,10000,2300,2300,CONT_VIA2,45onymous_ +B 11000,1000,2300,2300,CONT_VIA4,32onymous_ +B 35000,1000,2300,2300,CONT_VIA2,44onymous_ +B 11000,1000,2300,2300,CONT_VIA2,34onymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/pvsse_mpx.vbe b/pdks/symbolic/mpxlib/cells/pvsse_mpx.vbe new file mode 100644 index 000000000..413e4b4aa --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvsse_mpx.vbe @@ -0,0 +1,20 @@ +ENTITY pvsse_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000 + ); + PORT ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvsse_mpx; + +ARCHITECTURE behaviour_data_flow OF pvsse_mpx IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvsse_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/pvsseck_mpx.ap b/pdks/symbolic/mpxlib/cells/pvsseck_mpx.ap new file mode 100644 index 000000000..00d939205 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvsseck_mpx.ap @@ -0,0 +1,350 @@ +V ALLIANCE : 6 +H pvsseck_mpx,P,18/ 2/2015,100 +A 0,0,40000,80000 +S 19000,-900,19000,400,2400,cko,UP,CALU4 +S 19000,-900,19000,400,2400,cko,UP,CALU5 +S 19000,0,19000,2000,2400,cko,UP,ALU4 +S 19000,0,19000,2000,2400,cko,UP,ALU5 +S 30800,11300,30800,14900,620,90onymous_,UP,PDIF +S 10400,8500,10400,9100,400,7nonymous_,UP,ALU1 +S 30800,7700,30800,9300,420,89onymous_,UP,NDIF +S 12800,8500,12800,9100,400,6nonymous_,UP,ALU1 +S 8000,8500,8000,12700,400,8nonymous_,UP,ALU1 +S 7880,16200,14120,16200,600,9nonymous_,RIGHT,NTIE +S 21200,6000,28800,6000,12000,123nymous_,RIGHT,TALU4 +S 11200,6000,16800,6000,12000,124nymous_,RIGHT,TALU4 +S 37200,6000,39950,6000,12000,121nymous_,RIGHT,TALU4 +S 0,6000,40000,6000,12000,120nymous_,RIGHT,TALU6 +S 30200,9800,30200,10800,200,87onymous_,UP,POLY +S 7880,6200,14120,6200,600,5nonymous_,RIGHT,PTIE +S 30200,11100,30200,15100,200,88onymous_,UP,PTRANS +S 33000,200,33000,2000,0,119nymous_,UP,TALU3 +S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 +S 29600,11300,29600,14900,620,85onymous_,UP,PDIF +S 14000,6050,14000,7550,600,3nonymous_,UP,ALU2 +S 30200,7500,30200,9500,200,86onymous_,UP,NTRANS +S 7000,3850,7000,10350,600,4nonymous_,UP,ALU2 +S 29600,11300,29600,13900,400,84onymous_,UP,ALU1 +S 11450,16200,14150,16200,600,2nonymous_,RIGHT,ALU2 +S 29600,7700,29600,9300,420,83onymous_,UP,NDIF +S 11450,2000,28550,2000,600,1nonymous_,RIGHT,ALU3 +S 11450,1000,28550,1000,600,0nonymous_,RIGHT,ALU3 +S 25000,200,25000,2000,8000,118nymous_,UP,TALU3 +S 29000,11100,29000,15100,200,82onymous_,UP,PTRANS +S 29000,9800,29000,10800,200,81onymous_,UP,POLY +S 28400,7700,28400,9300,620,78onymous_,UP,NDIF +S 7000,200,7000,2000,0,116nymous_,UP,TALU3 +S 8600,11100,8600,15100,200,42onymous_,UP,PTRANS +S 28400,11300,28400,14900,620,79onymous_,UP,PDIF +S 14000,200,14000,2000,6000,117nymous_,UP,TALU3 +S 9200,12100,9200,14900,400,50onymous_,UP,ALU1 +S 8000,7700,8000,9300,620,43onymous_,UP,NDIF +S 29000,7500,29000,9500,200,80onymous_,UP,NTRANS +S 38600,200,38600,2000,3000,115nymous_,UP,TALU3 +S 27800,11100,27800,15100,200,77onymous_,UP,PTRANS +S 8600,9800,8600,10800,200,40onymous_,UP,POLY +S 27800,9800,27800,10800,200,76onymous_,UP,POLY +S 8600,7500,8600,9500,200,39onymous_,UP,NTRANS +S 9200,11300,9200,14900,620,38onymous_,UP,PDIF +S 27800,7500,27800,9500,200,75onymous_,UP,NTRANS +S 7000,10200,8600,10200,600,41onymous_,RIGHT,POLY +S 14000,12300,14000,14900,400,49onymous_,UP,ALU1 +S 27300,11200,29500,11200,400,74onymous_,RIGHT,ALU1 +S 11600,7500,11600,8100,400,47onymous_,UP,ALU1 +S 27300,10200,31900,10200,400,71onymous_,RIGHT,ALU1 +S 1400,200,1400,2000,3000,114nymous_,UP,TALU3 +S 14000,7500,14000,8100,400,46onymous_,UP,ALU1 +S 25000,200,25000,12000,8000,112nymous_,UP,TALU5 +S 9200,7700,9200,9300,420,37onymous_,UP,NDIF +S 33000,200,33000,12000,0,113nymous_,UP,TALU5 +S 27200,11300,27200,13900,400,72onymous_,UP,ALU1 +S 9300,7400,13900,7400,400,48onymous_,RIGHT,ALU1 +S 9800,9800,9800,10800,200,35onymous_,UP,POLY +S 27200,11300,27200,14900,620,73onymous_,UP,PDIF +S 9800,11100,9800,15100,200,36onymous_,UP,PTRANS +S 14000,200,14000,12000,6000,111nymous_,UP,TALU5 +S 9800,7500,9800,9500,200,34onymous_,UP,NTRANS +S 10400,11300,10400,14900,620,33onymous_,UP,PDIF +S 27300,9200,29500,9200,400,70onymous_,RIGHT,ALU1 +S 1400,200,1400,12000,3000,108nymous_,UP,TALU5 +S 8000,11300,8000,14900,620,44onymous_,UP,PDIF +S 27200,7700,27200,9300,420,69onymous_,UP,NDIF +S 9200,7500,9200,9100,400,45onymous_,UP,ALU1 +S 10400,11300,10400,13900,400,32onymous_,UP,ALU1 +S 38600,200,38600,12000,3000,109nymous_,UP,TALU5 +S 7000,200,7000,12000,0,110nymous_,UP,TALU5 +S 17000,18100,17000,59900,4400,107nymous_,UP,ALU1 +S 10400,7700,10400,9300,420,31onymous_,UP,NDIF +S 26600,11100,26600,15100,200,68onymous_,UP,PTRANS +S 11000,9800,11000,10800,200,29onymous_,UP,POLY +S 23000,18100,23000,59900,4400,106nymous_,UP,ALU1 +S 11000,11100,11000,15100,200,30onymous_,UP,PTRANS +S 27200,850,27200,11350,600,105nymous_,UP,ALU2 +S 11000,7500,11000,9500,200,28onymous_,UP,NTRANS +S 28400,850,28400,11350,600,104nymous_,UP,ALU2 +S 11600,7700,11600,9300,620,26onymous_,UP,NDIF +S 11600,11300,11600,14900,620,27onymous_,UP,PDIF +S 26600,10200,30200,10200,600,67onymous_,RIGHT,POLY +S 12200,7500,12200,9500,200,23onymous_,UP,NTRANS +S 26600,9800,26600,10800,200,66onymous_,UP,POLY +S 10500,11200,12700,11200,400,22onymous_,RIGHT,ALU1 +S 12200,11100,12200,15100,200,25onymous_,UP,PTRANS +S 12200,9800,12200,10800,200,24onymous_,UP,POLY +S 30800,12100,30800,14900,400,102nymous_,UP,ALU1 +S 28400,12300,28400,14900,400,103nymous_,UP,ALU1 +S 26100,7400,30700,7400,400,100nymous_,RIGHT,ALU1 +S 28400,7500,28400,8100,400,99onymous_,UP,ALU1 +S 26000,7500,26000,8100,400,98onymous_,UP,ALU1 +S 26600,7500,26600,9500,200,65onymous_,UP,NTRANS +S 12800,11300,12800,14900,620,21onymous_,UP,PDIF +S 26000,12300,26000,14900,400,101nymous_,UP,ALU1 +S 26000,7700,26000,9300,620,63onymous_,UP,NDIF +S 12800,11300,12800,13900,400,20onymous_,UP,ALU1 +S 26000,11300,26000,14900,620,64onymous_,UP,PDIF +S 30800,7500,30800,9100,400,97onymous_,UP,ALU1 +S 32000,11300,32000,14900,620,96onymous_,UP,PDIF +S 10500,9200,12700,9200,400,18onymous_,RIGHT,ALU1 +S 50,6000,2800,6000,12000,132nymous_,RIGHT,TALU2 +S 25000,13800,33000,13800,6800,62onymous_,RIGHT,NWELL +S 32000,7700,32000,9300,620,95onymous_,UP,NDIF +S 8100,10200,12700,10200,400,19onymous_,RIGHT,ALU1 +S 29600,8500,29600,9100,400,59onymous_,UP,ALU1 +S 32000,8500,32000,12700,400,60onymous_,UP,ALU1 +S 25880,16200,32120,16200,600,61onymous_,RIGHT,NTIE +S 33000,3850,33000,10350,600,56onymous_,UP,ALU2 +S 26000,6050,26000,7550,600,55onymous_,UP,ALU2 +S 31400,11100,31400,15100,200,94onymous_,UP,PTRANS +S 25880,6200,32120,6200,600,57onymous_,RIGHT,PTIE +S 27200,8500,27200,9100,400,58onymous_,UP,ALU1 +S 13400,9800,13400,10800,200,14onymous_,UP,POLY +S 9800,10200,13400,10200,600,15onymous_,RIGHT,POLY +S 21200,6000,28800,6000,12000,129nymous_,RIGHT,TALU2 +S 13400,11100,13400,15100,200,16onymous_,UP,PTRANS +S 11200,6000,16800,6000,12000,130nymous_,RIGHT,TALU2 +S 25850,16200,28550,16200,600,54onymous_,RIGHT,ALU2 +S 12800,7700,12800,9300,420,17onymous_,UP,NDIF +S 31400,10200,33000,10200,600,93onymous_,RIGHT,POLY +S 7000,13800,15000,13800,6800,10onymous_,RIGHT,NWELL +S 11600,850,11600,11350,600,52onymous_,UP,ALU2 +S 37200,6000,39950,6000,12000,127nymous_,RIGHT,TALU2 +S 11600,12300,11600,14900,400,51onymous_,UP,ALU1 +S 13400,7500,13400,9500,200,13onymous_,UP,NTRANS +S 14000,7700,14000,9300,620,11onymous_,UP,NDIF +S 14000,11300,14000,14900,620,12onymous_,UP,PDIF +S 50,6000,2800,6000,12000,126nymous_,RIGHT,TALU4 +S 31400,7500,31400,9500,200,91onymous_,UP,NTRANS +S 12800,850,12800,11350,600,53onymous_,UP,ALU2 +S 31400,9800,31400,10800,200,92onymous_,UP,POLY +S 5000,-150,5000,2150,2400,vssi,UP,CALU3 +S 5000,0,5000,2000,2400,vssi,UP,CALU5 +S 5000,0,5000,2000,2400,vssi,UP,CALU4 +S 31000,0,31000,2000,2400,vssi,UP,CALU4 +S 26100,6800,31900,6800,1600,vssi,RIGHT,ALU1 +S 5000,-150,5000,17150,2400,vssi,UP,CALU2 +S 31000,-150,31000,17150,2400,vssi,UP,CALU2 +S 31000,-150,31000,2150,2400,vssi,UP,CALU3 +S 31000,0,31000,2000,2400,vssi,UP,CALU5 +S 8100,6800,13900,6800,1600,vssi,RIGHT,ALU1 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 20000,48100,20000,71900,24400,vsse,UP,CALU1 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 9000,0,9000,2000,2400,vddi,UP,CALU5 +S 9000,0,9000,2000,2400,vddi,UP,CALU4 +S 35000,-150,35000,2150,2400,vddi,UP,CALU3 +S 35000,0,35000,2000,2400,vddi,UP,CALU5 +S 35000,0,35000,2000,2400,vddi,UP,CALU4 +S 8100,15600,13900,15600,1600,vddi,RIGHT,ALU1 +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 9000,-150,9000,17150,2400,vddi,UP,CALU2 +S 26100,15600,31900,15600,1600,vddi,RIGHT,ALU1 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 9000,-150,9000,2150,2400,vddi,UP,CALU3 +S 35000,-150,35000,17150,2400,vddi,UP,CALU2 +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +I 0,40000,padreal_mpx,padreal,NOSYM +B 28400,11200,300,300,CONT_VIA,247nymous_ +B 12800,9200,300,300,CONT_DIF_N,166nymous_ +B 28400,10200,300,300,CONT_POLY,246nymous_ +B 31000,1000,2300,2300,CONT_VIA4,284nymous_ +B 26000,6200,300,300,CONT_VIA2,209nymous_ +B 31000,1000,2300,2300,CONT_VIA3,283nymous_ +B 12800,10200,300,300,CONT_POLY,168nymous_ +B 26000,16200,300,300,CONT_VIA2,208nymous_ +B 12800,9200,300,300,CONT_VIA,167nymous_ +B 31000,1000,2300,2300,CONT_VIA2,282nymous_ +B 27200,16200,300,300,CONT_VIA2,207nymous_ +B 31000,7000,2300,2300,CONT_VIA2,281nymous_ +B 28400,16200,300,300,CONT_VIA2,206nymous_ +B 23000,19000,4300,2300,CONT_VIA2,280nymous_ +B 14000,15000,300,300,CONT_DIF_P,165nymous_ +B 28400,16200,300,300,CONT_VIA,205nymous_ +B 23000,19000,4300,2300,CONT_VIA,279nymous_ +B 28400,9200,300,300,CONT_VIA,245nymous_ +B 14000,14000,300,300,CONT_DIF_P,164nymous_ +B 27200,16200,300,300,CONT_VIA,204nymous_ +B 23000,37000,4300,2300,CONT_VIA2,278nymous_ +B 28400,8200,300,300,CONT_DIF_N,244nymous_ +B 14000,13000,300,300,CONT_DIF_P,163nymous_ +B 28400,7400,300,300,CONT_DIF_N,243nymous_ +B 26000,16200,300,300,CONT_VIA,203nymous_ +B 23000,37000,4300,2300,CONT_VIA,277nymous_ +B 14000,12200,300,300,CONT_DIF_P,162nymous_ +B 23000,31000,4300,2300,CONT_VIA2,276nymous_ +B 14000,8200,300,300,CONT_DIF_N,161nymous_ +B 27200,14000,300,300,CONT_DIF_P,242nymous_ +B 14000,7400,300,300,CONT_DIF_N,160nymous_ +B 23000,31000,4300,2300,CONT_VIA,275nymous_ +B 23000,25000,4300,2300,CONT_VIA2,274nymous_ +B 27200,12000,300,300,CONT_DIF_P,240nymous_ +B 10400,11200,200,200,CONT_TURN1,159nymous_ +B 27200,11200,300,300,CONT_VIA,239nymous_ +B 14000,16200,300,300,CONT_BODY_N,158nymous_ +B 12800,16200,300,300,CONT_BODY_N,157nymous_ +B 12800,1000,300,300,CONT_VIA2,202nymous_ +B 27200,13000,300,300,CONT_DIF_P,241nymous_ +B 11600,1000,300,300,CONT_VIA2,201nymous_ +B 12800,2000,300,300,CONT_VIA2,200nymous_ +B 9200,16200,300,300,CONT_BODY_N,153nymous_ +B 11600,2000,300,300,CONT_VIA2,199nymous_ +B 23000,25000,4300,2300,CONT_VIA,273nymous_ +B 9200,7400,300,300,CONT_DIF_N,198nymous_ +B 27200,1000,300,300,CONT_VIA2,272nymous_ +B 27200,10200,300,300,CONT_POLY,238nymous_ +B 28400,1000,300,300,CONT_VIA2,271nymous_ +B 27200,9200,300,300,CONT_VIA,237nymous_ +B 11600,16200,300,300,CONT_BODY_N,156nymous_ +B 27200,9200,300,300,CONT_DIF_N,236nymous_ +B 10400,16200,300,300,CONT_BODY_N,155nymous_ +B 26000,15000,300,300,CONT_DIF_P,235nymous_ +B 8000,16200,300,300,CONT_BODY_N,154nymous_ +B 26000,14000,300,300,CONT_DIF_P,234nymous_ +B 33000,10200,300,300,CONT_VIA,267nymous_ +B 26000,13000,300,300,CONT_DIF_P,233nymous_ +B 14000,6200,300,300,CONT_BODY_P,152nymous_ +B 26000,12200,300,300,CONT_DIF_P,232nymous_ +B 26000,8200,300,300,CONT_DIF_N,231nymous_ +B 7000,10200,300,300,CONT_VIA,197nymous_ +B 7000,10200,300,300,CONT_POLY,196nymous_ +B 27200,2000,300,300,CONT_VIA2,270nymous_ +B 8000,12800,300,300,CONT_DIF_P,195nymous_ +B 28400,2000,300,300,CONT_VIA2,269nymous_ +B 30800,7400,300,300,CONT_DIF_N,268nymous_ +B 17000,19000,4300,2300,CONT_VIA2,308nymous_ +B 8000,9200,300,300,CONT_DIF_N,193nymous_ +B 9200,15000,300,300,CONT_DIF_P,192nymous_ +B 33000,10200,300,300,CONT_POLY,266nymous_ +B 12800,6200,300,300,CONT_BODY_P,151nymous_ +B 9200,14000,300,300,CONT_DIF_P,191nymous_ +B 11600,6200,300,300,CONT_BODY_P,150nymous_ +B 26000,7400,300,300,CONT_DIF_N,230nymous_ +B 29600,11200,200,200,CONT_TURN1,229nymous_ +B 19000,1000,2300,2300,CONT_VIA4,310nymous_ +B 19000,1000,2300,2300,CONT_VIA3,309nymous_ +B 8000,11800,300,300,CONT_DIF_P,194nymous_ +B 26000,16200,300,300,CONT_BODY_N,228nymous_ +B 9200,9200,300,300,CONT_DIF_N,188nymous_ +B 9200,6200,300,300,CONT_BODY_P,148nymous_ +B 32000,9200,300,300,CONT_DIF_N,263nymous_ +B 9200,12000,300,300,CONT_DIF_P,189nymous_ +B 10400,6200,300,300,CONT_BODY_P,149nymous_ +B 17000,31000,4300,2300,CONT_VIA2,304nymous_ +B 32000,11800,300,300,CONT_DIF_P,264nymous_ +B 9200,13000,300,300,CONT_DIF_P,190nymous_ +B 17000,37000,4300,2300,CONT_VIA,305nymous_ +B 32000,12800,300,300,CONT_DIF_P,265nymous_ +B 17000,37000,4300,2300,CONT_VIA2,306nymous_ +B 17000,19000,4300,2300,CONT_VIA,307nymous_ +B 12800,8400,300,300,CONT_DIF_N,146nymous_ +B 27200,16200,300,300,CONT_BODY_N,227nymous_ +B 8000,6200,300,300,CONT_BODY_P,147nymous_ +B 17000,25000,4300,2300,CONT_VIA2,302nymous_ +B 9200,8200,300,300,CONT_DIF_N,187nymous_ +B 30800,14000,300,300,CONT_DIF_P,261nymous_ +B 30800,15000,300,300,CONT_DIF_P,262nymous_ +B 17000,31000,4300,2300,CONT_VIA,303nymous_ +B 14000,6200,300,300,CONT_VIA,142nymous_ +B 30800,16200,300,300,CONT_BODY_N,223nymous_ +B 7000,4000,300,300,CONT_VIA2,143nymous_ +B 32000,16200,300,300,CONT_BODY_N,224nymous_ +B 10400,12000,300,300,CONT_DIF_P,184nymous_ +B 10400,8400,300,300,CONT_DIF_N,144nymous_ +B 29600,16200,300,300,CONT_BODY_N,225nymous_ +B 30800,12000,300,300,CONT_DIF_P,259nymous_ +B 10400,13000,300,300,CONT_DIF_P,185nymous_ +B 8000,8400,300,300,CONT_DIF_N,145nymous_ +B 9000,16000,2300,2300,CONT_VIA2,300nymous_ +B 28400,16200,300,300,CONT_BODY_N,226nymous_ +B 30800,13000,300,300,CONT_DIF_P,260nymous_ +B 10400,14000,300,300,CONT_DIF_P,186nymous_ +B 17000,25000,4300,2300,CONT_VIA,301nymous_ +B 27200,6200,300,300,CONT_BODY_P,221nymous_ +B 11600,15000,300,300,CONT_DIF_P,181nymous_ +B 14000,7400,300,300,CONT_VIA,141nymous_ +B 9000,10000,2300,2300,CONT_VIA2,296nymous_ +B 26000,6200,300,300,CONT_BODY_P,222nymous_ +B 10400,9200,300,300,CONT_DIF_N,182nymous_ +B 9000,1000,2300,2300,CONT_VIA2,297nymous_ +B 10400,10200,300,300,CONT_POLY,183nymous_ +B 9000,1000,2300,2300,CONT_VIA3,298nymous_ +B 30800,9200,300,300,CONT_DIF_N,258nymous_ +B 9000,1000,2300,2300,CONT_VIA4,299nymous_ +B 14000,16200,300,300,CONT_VIA2,138nymous_ +B 14000,6200,300,300,CONT_VIA2,139nymous_ +B 14000,7400,300,300,CONT_VIA2,140nymous_ +B 29600,13000,300,300,CONT_DIF_P,255nymous_ +B 5000,13000,2300,2300,CONT_VIA2,295nymous_ +B 12800,16200,300,300,CONT_VIA,134nymous_ +B 11600,16200,300,300,CONT_VIA,135nymous_ +B 29600,14000,300,300,CONT_DIF_P,256nymous_ +B 11600,16200,300,300,CONT_VIA2,136nymous_ +B 30800,8200,300,300,CONT_DIF_N,257nymous_ +B 12800,16200,300,300,CONT_VIA2,137nymous_ +B 30800,6200,300,300,CONT_BODY_P,218nymous_ +B 11600,14000,300,300,CONT_DIF_P,180nymous_ +B 29600,12000,300,300,CONT_DIF_P,254nymous_ +B 28400,6200,300,300,CONT_BODY_P,220nymous_ +B 11600,13000,300,300,CONT_DIF_P,179nymous_ +B 29600,6200,300,300,CONT_BODY_P,219nymous_ +B 11600,12200,300,300,CONT_DIF_P,178nymous_ +B 5000,1000,2300,2300,CONT_VIA4,294nymous_ +B 29600,10200,300,300,CONT_POLY,253nymous_ +B 5000,1000,2300,2300,CONT_VIA3,293nymous_ +B 29600,9200,300,300,CONT_DIF_N,252nymous_ +B 5000,1000,2300,2300,CONT_VIA2,292nymous_ +B 11600,11200,300,300,CONT_VIA,177nymous_ +B 28400,15000,300,300,CONT_DIF_P,251nymous_ +B 32000,6200,300,300,CONT_BODY_P,217nymous_ +B 5000,7000,2300,2300,CONT_VIA2,291nymous_ +B 11600,10200,300,300,CONT_POLY,176nymous_ +B 27200,8400,300,300,CONT_DIF_N,216nymous_ +B 11600,9200,300,300,CONT_VIA,175nymous_ +B 14000,16200,300,300,CONT_VIA,133nymous_ +B 11600,8200,300,300,CONT_DIF_N,174nymous_ +B 35000,1000,2300,2300,CONT_VIA4,289nymous_ +B 32000,8400,300,300,CONT_DIF_N,215nymous_ +B 35000,16000,2300,2300,CONT_VIA2,290nymous_ +B 28400,14000,300,300,CONT_DIF_P,250nymous_ +B 12800,12000,300,300,CONT_DIF_P,170nymous_ +B 12800,13000,300,300,CONT_DIF_P,171nymous_ +B 26000,6200,300,300,CONT_VIA,212nymous_ +B 12800,14000,300,300,CONT_DIF_P,172nymous_ +B 35000,1000,2300,2300,CONT_VIA2,287nymous_ +B 33000,4000,300,300,CONT_VIA2,213nymous_ +B 11600,7400,300,300,CONT_DIF_N,173nymous_ +B 35000,1000,2300,2300,CONT_VIA3,288nymous_ +B 29600,8400,300,300,CONT_DIF_N,214nymous_ +B 28400,12200,300,300,CONT_DIF_P,248nymous_ +B 28400,13000,300,300,CONT_DIF_P,249nymous_ +B 12800,11200,300,300,CONT_VIA,169nymous_ +B 26000,7400,300,300,CONT_VIA2,210nymous_ +B 31000,13000,2300,2300,CONT_VIA2,285nymous_ +B 26000,7400,300,300,CONT_VIA,211nymous_ +B 35000,10000,2300,2300,CONT_VIA2,286nymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/pvsseck_mpx.vbe b/pdks/symbolic/mpxlib/cells/pvsseck_mpx.vbe new file mode 100644 index 000000000..3ef601075 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvsseck_mpx.vbe @@ -0,0 +1,31 @@ +ENTITY pvsseck_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_ck : NATURAL := 127; + CONSTANT tpll_ck : NATURAL := 1055; + CONSTANT rdown_ck : NATURAL := 126; + CONSTANT tphh_ck : NATURAL := 963; + CONSTANT rup_ck : NATURAL := 183 + ); + PORT ( + cko : out WOR_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvsseck_mpx; + +ARCHITECTURE behaviour_data_flow OF pvsseck_mpx IS + +BEGIN + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvsseck_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/pvssi_mpx.ap b/pdks/symbolic/mpxlib/cells/pvssi_mpx.ap new file mode 100644 index 000000000..d63f2237d --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvssi_mpx.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 6 +H pvssi_mpx,P,17/9/2014,100 +A 0,0,40000,80000 +I 0,40000,padreal_mpx,padreal,NOSYM +S 31200,6000,32800,6000,12000,13onymous_,RIGHT,TALU2 +S 7200,6000,8800,6000,12000,11onymous_,RIGHT,TALU2 +S 50,6000,2800,6000,12000,10onymous_,RIGHT,TALU2 +S 13200,6000,26800,6000,12000,12onymous_,RIGHT,TALU2 +S 13200,6000,26800,6000,12000,17onymous_,RIGHT,TALU4 +S 50,6000,2800,6000,12000,15onymous_,RIGHT,TALU4 +S 37200,6000,39950,6000,12000,14onymous_,RIGHT,TALU2 +S 7200,6000,8800,6000,12000,16onymous_,RIGHT,TALU4 +S 31200,6000,32800,6000,12000,18onymous_,RIGHT,TALU4 +S 37200,6000,39950,6000,12000,19onymous_,RIGHT,TALU4 +S 17000,6100,17000,59900,4400,21onymous_,UP,ALU1 +S 8000,200,8000,2000,2000,1nonymous_,UP,TALU3 +S 1400,200,1400,2000,3000,0nonymous_,UP,TALU3 +S 0,6000,40000,6000,12000,20onymous_,RIGHT,TALU6 +S 20000,200,20000,2000,14000,2nonymous_,UP,TALU3 +S 23000,6100,23000,59900,4400,22onymous_,UP,ALU1 +S 32000,200,32000,2000,2000,3nonymous_,UP,TALU3 +S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 +S 38600,200,38600,2000,3000,4nonymous_,UP,TALU3 +S 1400,200,1400,12000,3000,5nonymous_,UP,TALU5 +S 20000,200,20000,12000,14000,7nonymous_,UP,TALU5 +S 8000,200,8000,12000,2000,6nonymous_,UP,TALU5 +S 32000,200,32000,12000,2000,8nonymous_,UP,TALU5 +S 38600,200,38600,12000,3000,9nonymous_,UP,TALU5 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 20000,48100,20000,71900,24400,vssi,UP,CALU1 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 5000,-150,5000,17150,2400,vssi,UP,CALU2 +S 5000,-150,5000,2150,2400,vssi,UP,CALU3 +S 5000,0,5000,2000,2400,vssi,UP,CALU5 +S 5000,0,5000,2000,2400,vssi,UP,CALU4 +S 29000,-150,29000,17150,2400,vssi,UP,CALU2 +S 29000,-150,29000,2150,2400,vssi,UP,CALU3 +S 29000,0,29000,2000,2400,vssi,UP,CALU5 +S 29000,0,29000,2000,2400,vssi,UP,CALU4 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 35000,0,35000,2000,2400,vddi,UP,CALU4 +S 35000,0,35000,2000,2400,vddi,UP,CALU5 +S 35000,-150,35000,2150,2400,vddi,UP,CALU3 +S 35000,-150,35000,17150,2400,vddi,UP,CALU2 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 11000,0,11000,2000,2400,vddi,UP,CALU4 +S 11000,0,11000,2000,2400,vddi,UP,CALU5 +S 11000,-150,11000,2150,2400,vddi,UP,CALU3 +S 11000,-150,11000,17150,2400,vddi,UP,CALU2 +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +B 29000,7000,2300,2300,CONT_VIA2,46onymous_ +B 35000,16000,2300,2300,CONT_VIA2,37onymous_ +B 23000,13000,4300,2300,CONT_VIA2,47onymous_ +B 5000,1000,2300,2300,CONT_VIA2,35onymous_ +B 5000,7000,2300,2300,CONT_VIA2,36onymous_ +B 23000,13000,4300,2300,CONT_VIA,48onymous_ +B 35000,1000,2300,2300,CONT_VIA4,38onymous_ +B 35000,10000,2300,2300,CONT_VIA2,41onymous_ +B 35000,1000,2300,2300,CONT_VIA2,40onymous_ +B 23000,7000,4300,2300,CONT_VIA2,49onymous_ +B 35000,1000,2300,2300,CONT_VIA3,39onymous_ +B 29000,13000,2300,2300,CONT_VIA2,42onymous_ +B 29000,1000,2300,2300,CONT_VIA4,43onymous_ +B 23000,7000,4300,2300,CONT_VIA,50onymous_ +B 17000,7000,4300,2300,CONT_VIA2,25onymous_ +B 17000,13000,4300,2300,CONT_VIA2,23onymous_ +B 17000,13000,4300,2300,CONT_VIA,24onymous_ +B 11000,1000,2300,2300,CONT_VIA4,28onymous_ +B 17000,7000,4300,2300,CONT_VIA,26onymous_ +B 11000,16000,2300,2300,CONT_VIA2,27onymous_ +B 11000,10000,2300,2300,CONT_VIA2,31onymous_ +B 11000,1000,2300,2300,CONT_VIA2,30onymous_ +B 11000,1000,2300,2300,CONT_VIA3,29onymous_ +B 29000,1000,2300,2300,CONT_VIA2,45onymous_ +B 5000,1000,2300,2300,CONT_VIA4,33onymous_ +B 5000,13000,2300,2300,CONT_VIA2,32onymous_ +B 29000,1000,2300,2300,CONT_VIA3,44onymous_ +B 5000,1000,2300,2300,CONT_VIA3,34onymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/pvssi_mpx.vbe b/pdks/symbolic/mpxlib/cells/pvssi_mpx.vbe new file mode 100644 index 000000000..a2d978a04 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvssi_mpx.vbe @@ -0,0 +1,20 @@ +ENTITY pvssi_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000 + ); + PORT ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvssi_mpx; + +ARCHITECTURE behaviour_data_flow OF pvssi_mpx IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvssi_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/mpxlib/cells/pvssick_mpx.ap b/pdks/symbolic/mpxlib/cells/pvssick_mpx.ap new file mode 100644 index 000000000..ff7149329 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvssick_mpx.ap @@ -0,0 +1,339 @@ +V ALLIANCE : 6 +H pvssick_mpx,P,18/ 2/2015,100 +A 0,0,40000,80000 +S 19000,0,19000,2000,2400,cko,UP,ALU5 +S 19000,0,19000,2000,2400,cko,UP,ALU4 +S 19000,-900,19000,400,2400,cko,UP,CALU4 +S 19000,-900,19000,400,2400,cko,UP,CALU5 +S 28400,12300,28400,14900,400,8nonymous_,UP,ALU1 +S 8100,10200,12700,10200,400,90onymous_,RIGHT,ALU1 +S 28400,850,28400,11350,600,7nonymous_,UP,ALU2 +S 12800,11300,12800,13900,400,89onymous_,UP,ALU1 +S 27200,850,27200,11350,600,6nonymous_,UP,ALU2 +S 30800,12100,30800,14900,400,9nonymous_,UP,ALU1 +S 21200,6000,28800,6000,12000,123nymous_,RIGHT,TALU4 +S 11200,6000,16800,6000,12000,124nymous_,RIGHT,TALU4 +S 37200,6000,39950,6000,12000,121nymous_,RIGHT,TALU4 +S 0,6000,40000,6000,12000,120nymous_,RIGHT,TALU6 +S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 +S 8850,16200,14150,16200,600,5nonymous_,RIGHT,ALU2 +S 12800,11300,12800,14900,620,88onymous_,UP,PDIF +S 33000,200,33000,2000,0,119nymous_,UP,TALU3 +S 12200,9800,12200,10800,200,85onymous_,UP,POLY +S 26000,6050,26000,7550,600,3nonymous_,UP,ALU2 +S 12200,7500,12200,9500,200,86onymous_,UP,NTRANS +S 14000,6050,14000,7550,600,4nonymous_,UP,ALU2 +S 10500,11200,12700,11200,400,87onymous_,RIGHT,ALU1 +S 12200,11100,12200,15100,200,84onymous_,UP,PTRANS +S 25850,16200,28550,16200,600,2nonymous_,RIGHT,ALU2 +S 11600,7700,11600,9300,620,83onymous_,UP,NDIF +S 11450,2000,28550,2000,600,1nonymous_,RIGHT,ALU3 +S 11450,1000,28550,1000,600,0nonymous_,RIGHT,ALU3 +S 25000,200,25000,2000,8000,118nymous_,UP,TALU3 +S 11600,11300,11600,14900,620,82onymous_,UP,PDIF +S 25880,16200,32120,16200,600,50onymous_,RIGHT,NTIE +S 11000,7500,11000,9500,200,81onymous_,UP,NTRANS +S 10400,7700,10400,9300,420,78onymous_,UP,NDIF +S 27200,7700,27200,9300,420,42onymous_,UP,NDIF +S 7000,200,7000,2000,0,116nymous_,UP,TALU3 +S 11000,11100,11000,15100,200,79onymous_,UP,PTRANS +S 26600,11100,26600,15100,200,43onymous_,UP,PTRANS +S 14000,200,14000,2000,6000,117nymous_,UP,TALU3 +S 11000,9800,11000,10800,200,80onymous_,UP,POLY +S 27300,9200,29500,9200,400,41onymous_,RIGHT,ALU1 +S 10400,11300,10400,13900,400,77onymous_,UP,ALU1 +S 27300,10200,31900,10200,400,40onymous_,RIGHT,ALU1 +S 10400,11300,10400,14900,620,76onymous_,UP,PDIF +S 27200,11300,27200,14900,620,38onymous_,UP,PDIF +S 9800,7500,9800,9500,200,75onymous_,UP,NTRANS +S 27200,11300,27200,13900,400,39onymous_,UP,ALU1 +S 38600,200,38600,2000,3000,115nymous_,UP,TALU3 +S 25000,13800,33000,13800,6800,49onymous_,RIGHT,NWELL +S 9800,9800,9800,10800,200,74onymous_,UP,POLY +S 9200,11300,9200,14900,620,71onymous_,UP,PDIF +S 26000,11300,26000,14900,620,47onymous_,UP,PDIF +S 1400,200,1400,2000,3000,114nymous_,UP,TALU3 +S 26600,7500,26600,9500,200,46onymous_,UP,NTRANS +S 25000,200,25000,12000,8000,112nymous_,UP,TALU5 +S 33000,200,33000,12000,0,113nymous_,UP,TALU5 +S 26000,7700,26000,9300,620,48onymous_,UP,NDIF +S 27800,9800,27800,10800,200,35onymous_,UP,POLY +S 9200,7700,9200,9300,420,72onymous_,UP,NDIF +S 27800,7500,27800,9500,200,36onymous_,UP,NTRANS +S 9800,11100,9800,15100,200,73onymous_,UP,PTRANS +S 27300,11200,29500,11200,400,37onymous_,RIGHT,ALU1 +S 14000,200,14000,12000,6000,111nymous_,UP,TALU5 +S 27800,11100,27800,15100,200,34onymous_,UP,PTRANS +S 8600,7500,8600,9500,200,70onymous_,UP,NTRANS +S 28400,7700,28400,9300,620,33onymous_,UP,NDIF +S 26600,10200,30200,10200,600,44onymous_,RIGHT,POLY +S 26600,9800,26600,10800,200,45onymous_,UP,POLY +S 28400,11300,28400,14900,620,32onymous_,UP,PDIF +S 8600,9800,8600,10800,200,69onymous_,UP,POLY +S 1400,200,1400,12000,3000,108nymous_,UP,TALU5 +S 38600,200,38600,12000,3000,109nymous_,UP,TALU5 +S 7000,200,7000,12000,0,110nymous_,UP,TALU5 +S 17000,6100,17000,59900,4400,106nymous_,UP,ALU1 +S 29000,9800,29000,10800,200,30onymous_,UP,POLY +S 29000,11100,29000,15100,200,29onymous_,UP,PTRANS +S 7000,10200,8600,10200,600,68onymous_,RIGHT,POLY +S 29000,7500,29000,9500,200,31onymous_,UP,NTRANS +S 23000,6100,23000,59900,4400,107nymous_,UP,ALU1 +S 7000,3850,7000,10350,600,105nymous_,UP,ALU2 +S 7880,6200,14120,6200,600,104nymous_,RIGHT,PTIE +S 29600,11300,29600,14900,620,26onymous_,UP,PDIF +S 29600,11300,29600,13900,400,27onymous_,UP,ALU1 +S 29600,7700,29600,9300,420,28onymous_,UP,NDIF +S 30200,9800,30200,10800,200,24onymous_,UP,POLY +S 8600,11100,8600,15100,200,67onymous_,UP,PTRANS +S 30200,11100,30200,15100,200,23onymous_,UP,PTRANS +S 8000,7700,8000,9300,620,66onymous_,UP,NDIF +S 30800,7700,30800,9300,420,22onymous_,UP,NDIF +S 10400,8500,10400,9100,400,102nymous_,UP,ALU1 +S 30200,7500,30200,9500,200,25onymous_,UP,NTRANS +S 12800,8500,12800,9100,400,103nymous_,UP,ALU1 +S 7880,16200,14120,16200,600,100nymous_,RIGHT,NTIE +S 7000,13800,15000,13800,6800,99onymous_,RIGHT,NWELL +S 14000,7700,14000,9300,620,98onymous_,UP,NDIF +S 8000,11300,8000,14900,620,65onymous_,UP,PDIF +S 8000,8500,8000,12700,400,101nymous_,UP,ALU1 +S 14000,7500,14000,8100,400,63onymous_,UP,ALU1 +S 31400,7500,31400,9500,200,20onymous_,UP,NTRANS +S 9200,7500,9200,9100,400,64onymous_,UP,ALU1 +S 30800,11300,30800,14900,620,21onymous_,UP,PDIF +S 14000,11300,14000,14900,620,97onymous_,UP,PDIF +S 13400,7500,13400,9500,200,96onymous_,UP,NTRANS +S 31400,10200,33000,10200,600,18onymous_,RIGHT,POLY +S 11600,7500,11600,8100,400,62onymous_,UP,ALU1 +S 50,6000,2800,6000,12000,132nymous_,RIGHT,TALU2 +S 31400,9800,31400,10800,200,19onymous_,UP,POLY +S 13400,9800,13400,10800,200,95onymous_,UP,POLY +S 9200,12100,9200,14900,400,59onymous_,UP,ALU1 +S 14000,12300,14000,14900,400,60onymous_,UP,ALU1 +S 9300,7400,13900,7400,400,61onymous_,RIGHT,ALU1 +S 12800,850,12800,11350,600,56onymous_,UP,ALU2 +S 9800,10200,13400,10200,600,94onymous_,RIGHT,POLY +S 11600,850,11600,11350,600,57onymous_,UP,ALU2 +S 30800,7500,30800,9100,400,14onymous_,UP,ALU1 +S 11600,12300,11600,14900,400,58onymous_,UP,ALU1 +S 32000,11300,32000,14900,620,15onymous_,UP,PDIF +S 21200,6000,28800,6000,12000,129nymous_,RIGHT,TALU2 +S 32000,7700,32000,9300,620,16onymous_,UP,NDIF +S 25880,6200,32120,6200,600,54onymous_,RIGHT,PTIE +S 11200,6000,16800,6000,12000,130nymous_,RIGHT,TALU2 +S 31400,11100,31400,15100,200,17onymous_,UP,PTRANS +S 33000,3850,33000,10350,600,55onymous_,UP,ALU2 +S 26100,7400,30700,7400,400,11onymous_,RIGHT,ALU1 +S 13400,11100,13400,15100,200,93onymous_,UP,PTRANS +S 29600,8500,29600,9100,400,52onymous_,UP,ALU1 +S 37200,6000,39950,6000,12000,127nymous_,RIGHT,TALU2 +S 32000,8500,32000,12700,400,51onymous_,UP,ALU1 +S 28400,7500,28400,8100,400,12onymous_,UP,ALU1 +S 50,6000,2800,6000,12000,126nymous_,RIGHT,TALU4 +S 26000,7500,26000,8100,400,13onymous_,UP,ALU1 +S 10500,9200,12700,9200,400,91onymous_,RIGHT,ALU1 +S 27200,8500,27200,9100,400,53onymous_,UP,ALU1 +S 12800,7700,12800,9300,420,92onymous_,UP,NDIF +S 26000,12300,26000,14900,400,10onymous_,UP,ALU1 +S 31000,-150,31000,2150,2400,vssi,UP,CALU3 +S 31000,-150,31000,17150,2400,vssi,UP,CALU2 +S 31000,0,31000,2000,2400,vssi,UP,CALU4 +S 31000,0,31000,2000,2400,vssi,UP,CALU5 +S 5000,0,5000,2000,2400,vssi,UP,CALU4 +S 5000,0,5000,2000,2400,vssi,UP,CALU5 +S 5000,-150,5000,2150,2400,vssi,UP,CALU3 +S 850,13000,39150,13000,2400,vssi,RIGHT,CALU3 +S 8100,6800,13900,6800,1600,vssi,RIGHT,ALU1 +S 850,7000,39150,7000,2400,vssi,RIGHT,CALU3 +S 5000,-150,5000,17150,2400,vssi,UP,CALU2 +S 20000,48100,20000,71900,24400,vssi,UP,CALU1 +S 26100,6800,31900,6800,1600,vssi,RIGHT,ALU1 +S 850,19000,39150,19000,2400,vsse,RIGHT,CALU3 +S 850,37000,39150,37000,2400,vsse,RIGHT,CALU3 +S 850,31000,39150,31000,2400,vsse,RIGHT,CALU3 +S 850,25000,39150,25000,2400,vsse,RIGHT,CALU3 +S 9000,0,9000,2000,2400,vddi,UP,CALU5 +S 9000,0,9000,2000,2400,vddi,UP,CALU4 +S 9000,-150,9000,2150,2400,vddi,UP,CALU3 +S 26100,15600,31900,15600,1600,vddi,RIGHT,ALU1 +S 35000,0,35000,2000,2400,vddi,UP,CALU4 +S 35000,-150,35000,17150,2400,vddi,UP,CALU2 +S 850,10000,39150,10000,2400,vddi,RIGHT,CALU3 +S 850,16000,39150,16000,2400,vddi,RIGHT,CALU3 +S 9000,-150,9000,17150,2400,vddi,UP,CALU2 +S 8100,15600,13900,15600,1600,vddi,RIGHT,ALU1 +S 35000,0,35000,2000,2400,vddi,UP,CALU5 +S 35000,-150,35000,2150,2400,vddi,UP,CALU3 +S 850,34000,39150,34000,2400,vdde,RIGHT,CALU3 +S 850,28000,39150,28000,2400,vdde,RIGHT,CALU3 +S 850,22000,39150,22000,2400,vdde,RIGHT,CALU3 +S 850,4000,39150,4000,600,ck,RIGHT,CALU3 +I 0,40000,padreal_mpx,padreal,NOSYM +B 14000,15000,300,300,CONT_DIF_P,247nymous_ +B 29600,14000,300,300,CONT_DIF_P,166nymous_ +B 12800,9200,300,300,CONT_DIF_N,246nymous_ +B 5000,1000,2300,2300,CONT_VIA2,284nymous_ +B 33000,4000,300,300,CONT_VIA2,209nymous_ +B 5000,1000,2300,2300,CONT_VIA3,283nymous_ +B 29600,12000,300,300,CONT_DIF_P,168nymous_ +B 29600,8400,300,300,CONT_DIF_N,208nymous_ +B 29600,13000,300,300,CONT_DIF_P,167nymous_ +B 5000,1000,2300,2300,CONT_VIA4,282nymous_ +B 32000,8400,300,300,CONT_DIF_N,207nymous_ +B 5000,13000,2300,2300,CONT_VIA2,281nymous_ +B 27200,8400,300,300,CONT_DIF_N,206nymous_ +B 17000,7000,4300,2300,CONT_VIA,280nymous_ +B 30800,8200,300,300,CONT_DIF_N,165nymous_ +B 32000,6200,300,300,CONT_BODY_P,205nymous_ +B 17000,7000,4300,2300,CONT_VIA2,279nymous_ +B 12800,9200,300,300,CONT_VIA,245nymous_ +B 30800,9200,300,300,CONT_DIF_N,164nymous_ +B 30800,6200,300,300,CONT_BODY_P,204nymous_ +B 17000,13000,4300,2300,CONT_VIA,278nymous_ +B 12800,10200,300,300,CONT_POLY,244nymous_ +B 30800,12000,300,300,CONT_DIF_P,163nymous_ +B 12800,11200,300,300,CONT_VIA,243nymous_ +B 29600,6200,300,300,CONT_BODY_P,203nymous_ +B 17000,13000,4300,2300,CONT_VIA2,277nymous_ +B 30800,13000,300,300,CONT_DIF_P,162nymous_ +B 19000,1000,2300,2300,CONT_VIA3,276nymous_ +B 30800,14000,300,300,CONT_DIF_P,161nymous_ +B 12800,12000,300,300,CONT_DIF_P,242nymous_ +B 30800,15000,300,300,CONT_DIF_P,160nymous_ +B 19000,1000,2300,2300,CONT_VIA4,275nymous_ +B 9000,1000,2300,2300,CONT_VIA4,274nymous_ +B 12800,14000,300,300,CONT_DIF_P,240nymous_ +B 32000,9200,300,300,CONT_DIF_N,159nymous_ +B 11600,7400,300,300,CONT_DIF_N,239nymous_ +B 32000,11800,300,300,CONT_DIF_P,158nymous_ +B 32000,12800,300,300,CONT_DIF_P,157nymous_ +B 28400,6200,300,300,CONT_BODY_P,202nymous_ +B 12800,13000,300,300,CONT_DIF_P,241nymous_ +B 27200,6200,300,300,CONT_BODY_P,201nymous_ +B 26000,6200,300,300,CONT_BODY_P,200nymous_ +B 28400,2000,300,300,CONT_VIA2,153nymous_ +B 30800,16200,300,300,CONT_BODY_N,199nymous_ +B 9000,1000,2300,2300,CONT_VIA3,273nymous_ +B 32000,16200,300,300,CONT_BODY_N,198nymous_ +B 9000,10000,2300,2300,CONT_VIA2,272nymous_ +B 11600,8200,300,300,CONT_DIF_N,238nymous_ +B 9000,16000,2300,2300,CONT_VIA2,271nymous_ +B 11600,9200,300,300,CONT_VIA,237nymous_ +B 33000,10200,300,300,CONT_POLY,156nymous_ +B 11600,10200,300,300,CONT_POLY,236nymous_ +B 33000,10200,300,300,CONT_VIA,155nymous_ +B 11600,11200,300,300,CONT_VIA,235nymous_ +B 30800,7400,300,300,CONT_DIF_N,154nymous_ +B 11600,12200,300,300,CONT_DIF_P,234nymous_ +B 8000,8400,300,300,CONT_DIF_N,267nymous_ +B 11600,13000,300,300,CONT_DIF_P,233nymous_ +B 27200,2000,300,300,CONT_VIA2,152nymous_ +B 11600,14000,300,300,CONT_DIF_P,232nymous_ +B 11600,15000,300,300,CONT_DIF_P,231nymous_ +B 29600,16200,300,300,CONT_BODY_N,197nymous_ +B 28400,16200,300,300,CONT_BODY_N,196nymous_ +B 9000,1000,2300,2300,CONT_VIA2,270nymous_ +B 27200,16200,300,300,CONT_BODY_N,195nymous_ +B 7000,4000,300,300,CONT_VIA2,269nymous_ +B 10400,8400,300,300,CONT_DIF_N,268nymous_ +B 26000,7400,300,300,CONT_DIF_N,192nymous_ +B 29600,11200,200,200,CONT_TURN1,193nymous_ +B 12800,8400,300,300,CONT_DIF_N,266nymous_ +B 28400,1000,300,300,CONT_VIA2,151nymous_ +B 26000,8200,300,300,CONT_DIF_N,191nymous_ +B 27200,1000,300,300,CONT_VIA2,150nymous_ +B 10400,9200,300,300,CONT_DIF_N,230nymous_ +B 10400,10200,300,300,CONT_POLY,229nymous_ +B 26000,16200,300,300,CONT_BODY_N,194nymous_ +B 10400,12000,300,300,CONT_DIF_P,228nymous_ +B 14000,16200,300,300,CONT_VIA,147nymous_ +B 26000,14000,300,300,CONT_DIF_P,188nymous_ +B 12800,16200,300,300,CONT_VIA,148nymous_ +B 10400,6200,300,300,CONT_BODY_P,263nymous_ +B 11600,16200,300,300,CONT_VIA,149nymous_ +B 26000,13000,300,300,CONT_DIF_P,189nymous_ +B 9200,6200,300,300,CONT_BODY_P,264nymous_ +B 26000,12200,300,300,CONT_DIF_P,190nymous_ +B 8000,6200,300,300,CONT_BODY_P,265nymous_ +B 14000,7400,300,300,CONT_VIA,146nymous_ +B 10400,13000,300,300,CONT_DIF_P,227nymous_ +B 26000,15000,300,300,CONT_DIF_P,187nymous_ +B 12800,6200,300,300,CONT_BODY_P,261nymous_ +B 11600,6200,300,300,CONT_BODY_P,262nymous_ +B 26000,6200,300,300,CONT_VIA2,142nymous_ +B 9200,12000,300,300,CONT_DIF_P,223nymous_ +B 14000,7400,300,300,CONT_VIA2,143nymous_ +B 9200,9200,300,300,CONT_DIF_N,224nymous_ +B 27200,10200,300,300,CONT_POLY,184nymous_ +B 14000,6200,300,300,CONT_VIA2,144nymous_ +B 9200,8200,300,300,CONT_DIF_N,225nymous_ +B 9200,16200,300,300,CONT_BODY_N,259nymous_ +B 14000,6200,300,300,CONT_VIA,145nymous_ +B 27200,9200,300,300,CONT_VIA,185nymous_ +B 10400,14000,300,300,CONT_DIF_P,226nymous_ +B 14000,6200,300,300,CONT_BODY_P,260nymous_ +B 27200,9200,300,300,CONT_DIF_N,186nymous_ +B 26000,7400,300,300,CONT_VIA2,141nymous_ +B 9200,14000,300,300,CONT_DIF_P,221nymous_ +B 27200,13000,300,300,CONT_DIF_P,181nymous_ +B 31000,1000,2300,2300,CONT_VIA3,296nymous_ +B 9200,13000,300,300,CONT_DIF_P,222nymous_ +B 27200,12000,300,300,CONT_DIF_P,182nymous_ +B 31000,13000,2300,2300,CONT_VIA2,297nymous_ +B 27200,11200,300,300,CONT_VIA,183nymous_ +B 31000,7000,2300,2300,CONT_VIA2,298nymous_ +B 8000,16200,300,300,CONT_BODY_N,258nymous_ +B 31000,1000,2300,2300,CONT_VIA2,299nymous_ +B 26000,16200,300,300,CONT_VIA,138nymous_ +B 26000,6200,300,300,CONT_VIA,139nymous_ +B 26000,7400,300,300,CONT_VIA,140nymous_ +B 12800,16200,300,300,CONT_BODY_N,255nymous_ +B 31000,1000,2300,2300,CONT_VIA4,295nymous_ +B 27200,16200,300,300,CONT_VIA2,134nymous_ +B 28400,16200,300,300,CONT_VIA2,135nymous_ +B 11600,16200,300,300,CONT_BODY_N,256nymous_ +B 28400,16200,300,300,CONT_VIA,136nymous_ +B 10400,16200,300,300,CONT_BODY_N,257nymous_ +B 27200,16200,300,300,CONT_VIA,137nymous_ +B 8000,11800,300,300,CONT_DIF_P,218nymous_ +B 27200,14000,300,300,CONT_DIF_P,180nymous_ +B 14000,16200,300,300,CONT_BODY_N,254nymous_ +B 9200,15000,300,300,CONT_DIF_P,220nymous_ +B 28400,7400,300,300,CONT_DIF_N,179nymous_ +B 8000,9200,300,300,CONT_DIF_N,219nymous_ +B 28400,8200,300,300,CONT_DIF_N,178nymous_ +B 23000,7000,4300,2300,CONT_VIA,294nymous_ +B 10400,11200,200,200,CONT_TURN1,253nymous_ +B 23000,7000,4300,2300,CONT_VIA2,293nymous_ +B 14000,7400,300,300,CONT_DIF_N,252nymous_ +B 23000,13000,4300,2300,CONT_VIA,292nymous_ +B 28400,9200,300,300,CONT_VIA,177nymous_ +B 14000,8200,300,300,CONT_DIF_N,251nymous_ +B 8000,12800,300,300,CONT_DIF_P,217nymous_ +B 23000,13000,4300,2300,CONT_VIA2,291nymous_ +B 28400,10200,300,300,CONT_POLY,176nymous_ +B 7000,10200,300,300,CONT_POLY,216nymous_ +B 28400,11200,300,300,CONT_VIA,175nymous_ +B 26000,16200,300,300,CONT_VIA2,133nymous_ +B 28400,12200,300,300,CONT_DIF_P,174nymous_ +B 35000,1000,2300,2300,CONT_VIA2,289nymous_ +B 7000,10200,300,300,CONT_VIA,215nymous_ +B 35000,10000,2300,2300,CONT_VIA2,290nymous_ +B 14000,12200,300,300,CONT_DIF_P,250nymous_ +B 29600,9200,300,300,CONT_DIF_N,170nymous_ +B 28400,15000,300,300,CONT_DIF_P,171nymous_ +B 12800,2000,300,300,CONT_VIA2,212nymous_ +B 28400,14000,300,300,CONT_DIF_P,172nymous_ +B 35000,1000,2300,2300,CONT_VIA4,287nymous_ +B 11600,2000,300,300,CONT_VIA2,213nymous_ +B 28400,13000,300,300,CONT_DIF_P,173nymous_ +B 35000,1000,2300,2300,CONT_VIA3,288nymous_ +B 9200,7400,300,300,CONT_DIF_N,214nymous_ +B 14000,14000,300,300,CONT_DIF_P,248nymous_ +B 14000,13000,300,300,CONT_DIF_P,249nymous_ +B 29600,10200,300,300,CONT_POLY,169nymous_ +B 12800,1000,300,300,CONT_VIA2,210nymous_ +B 5000,7000,2300,2300,CONT_VIA2,285nymous_ +B 11600,1000,300,300,CONT_VIA2,211nymous_ +B 35000,16000,2300,2300,CONT_VIA2,286nymous_ +EOF diff --git a/pdks/symbolic/mpxlib/cells/pvssick_mpx.vbe b/pdks/symbolic/mpxlib/cells/pvssick_mpx.vbe new file mode 100644 index 000000000..95d24f385 --- /dev/null +++ b/pdks/symbolic/mpxlib/cells/pvssick_mpx.vbe @@ -0,0 +1,32 @@ +ENTITY pvssick_mpx IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_ck : NATURAL := 127; + CONSTANT tpll_ck : NATURAL := 1235; + CONSTANT rdown_ck : NATURAL := 253; + CONSTANT tphh_ck : NATURAL := 1109; + CONSTANT rup_ck : NATURAL := 311 + ); + PORT ( + cko : out WOR_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvssick_mpx; + +ARCHITECTURE behaviour_data_flow OF pvssick_mpx IS + +BEGIN + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvssick_mpx" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/CATAL b/pdks/symbolic/msplib/cells/CATAL new file mode 100644 index 000000000..a0604b098 --- /dev/null +++ b/pdks/symbolic/msplib/cells/CATAL @@ -0,0 +1,13 @@ +pck_msp C +pi_msp C +piot_msp C +po_msp C +pot_msp C +pvddeck_msp C +pvdde_msp C +pvddick_msp C +pvddi_msp C +pvsseck_msp C +pvsse_msp C +pvssick_msp C +pvssi_msp C diff --git a/pdks/symbolic/msplib/cells/pck_msp.ap b/pdks/symbolic/msplib/cells/pck_msp.ap new file mode 100644 index 000000000..405402439 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pck_msp.ap @@ -0,0 +1,55 @@ +V ALLIANCE : 6 +H pck_msp,P, 4/ 9/2014,100 +A 0,0,40000,80000 +C 40000,4000,750,ck,3,EAST,ALU3 +C 0,4000,750,ck,2,WEST,ALU3 +C 40000,10000,1800,vddi,1,EAST,ALU3 +C 40000,7000,1800,vssi,1,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,10000,1800,vddi,0,WEST,ALU3 +C 0,7000,1800,vssi,0,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 40000,16000,1800,vddi,3,EAST,ALU3 +C 40000,13000,1800,vssi,3,EAST,ALU3 +C 0,13000,1800,vssi,2,WEST,ALU3 +C 0,16000,1800,vddi,2,WEST,ALU3 +C 20000,80000,150,pad,0,NORTH,ALU1 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +I 0,0,pck_mpx,a,NOSYM +EOF diff --git a/pdks/symbolic/msplib/cells/pck_msp.vbe b/pdks/symbolic/msplib/cells/pck_msp.vbe new file mode 100644 index 000000000..9ecea733f --- /dev/null +++ b/pdks/symbolic/msplib/cells/pck_msp.vbe @@ -0,0 +1,29 @@ +ENTITY pck_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_pad : NATURAL := 1326; + CONSTANT tpll_pad : NATURAL := 1443; + CONSTANT rdown_pad : NATURAL := 58; + CONSTANT tphh_pad : NATURAL := 228; + CONSTANT rup_pad : NATURAL := 68 + ); + PORT ( + pad : in BIT; + ck : out BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pck_msp; + + +ARCHITECTURE behaviour_data_flow OF pck_msp IS + +BEGIN + ck <= pad; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pck_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/pi_msp.ap b/pdks/symbolic/msplib/cells/pi_msp.ap new file mode 100644 index 000000000..192500f88 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pi_msp.ap @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H pi_msp,P, 4/ 9/2014,100 +A 0,0,40000,80000 +C 20000,80000,150,pad,0,NORTH,ALU1 +C 8000,0,300,t,0,SOUTH,ALU1 +C 8000,0,300,t,1,SOUTH,ALU2 +C 0,16000,1800,vddi,6,WEST,ALU3 +C 0,13000,1800,vssi,6,WEST,ALU3 +C 40000,13000,1800,vssi,7,EAST,ALU3 +C 40000,16000,1800,vddi,7,EAST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,7000,1800,vssi,4,WEST,ALU3 +C 0,10000,1800,vddi,4,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,7000,1800,vssi,5,EAST,ALU3 +C 40000,10000,1800,vddi,5,EAST,ALU3 +C 0,4000,750,ck,0,WEST,ALU3 +C 40000,4000,750,ck,1,EAST,ALU3 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +I 0,0,pi_mpx,a,NOSYM +V 8000,0,CONT_VIA,* +EOF diff --git a/pdks/symbolic/msplib/cells/pi_msp.vbe b/pdks/symbolic/msplib/cells/pi_msp.vbe new file mode 100644 index 000000000..b9e20ccab --- /dev/null +++ b/pdks/symbolic/msplib/cells/pi_msp.vbe @@ -0,0 +1,30 @@ +ENTITY pi_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_pad : NATURAL := 654; + CONSTANT tpll_pad : NATURAL := 1487; + CONSTANT rdown_pad : NATURAL := 234; + CONSTANT tphh_pad : NATURAL := 233; + CONSTANT rup_pad : NATURAL := 273 + ); + PORT ( + pad : in BIT; + t : out BIT; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pi_msp; + + +ARCHITECTURE behaviour_data_flow OF pi_msp IS + +BEGIN + t <= pad; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pi_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/piot_msp.ap b/pdks/symbolic/msplib/cells/piot_msp.ap new file mode 100644 index 000000000..073832174 --- /dev/null +++ b/pdks/symbolic/msplib/cells/piot_msp.ap @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H piot_msp,P, 5/ 9/2014,100 +A 0,0,40000,80000 +C 20200,60200,150,pad,0,NORTH,ALU1 +C 20000,80000,150,t,2,NORTH,ALU1 +C 8000,0,300,t,0,SOUTH,ALU1 +C 8000,0,300,t,1,SOUTH,ALU2 +C 28000,0,300,i,0,SOUTH,ALU1 +C 28000,0,300,i,1,SOUTH,ALU2 +C 0,16000,1800,vddi,2,WEST,ALU3 +C 0,13000,1800,vssi,2,WEST,ALU3 +C 40000,13000,1800,vssi,3,EAST,ALU3 +C 40000,16000,1800,vddi,3,EAST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,7000,1800,vssi,0,WEST,ALU3 +C 0,10000,1800,vddi,0,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,7000,1800,vssi,1,EAST,ALU3 +C 40000,10000,1800,vddi,1,EAST,ALU3 +C 0,4000,750,ck,0,WEST,ALU3 +C 40000,4000,750,ck,1,EAST,ALU3 +C 30000,0,300,b,1,SOUTH,ALU2 +C 30000,0,300,b,0,SOUTH,ALU1 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +I 0,0,piot_mpx,a,NOSYM +V 8000,0,CONT_VIA,* +V 28000,0,CONT_VIA,* +V 30000,0,CONT_VIA,b +EOF diff --git a/pdks/symbolic/msplib/cells/piot_msp.vbe b/pdks/symbolic/msplib/cells/piot_msp.vbe new file mode 100644 index 000000000..42b25b010 --- /dev/null +++ b/pdks/symbolic/msplib/cells/piot_msp.vbe @@ -0,0 +1,44 @@ +ENTITY piot_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT rup : NATURAL := 402; + CONSTANT rdown : NATURAL := 0 + ); + PORT ( + i : in BIT; + b : in BIT; + t : out BIT; + pad : inout MUX_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END piot_msp; + +ARCHITECTURE behaviour_data_flow OF piot_msp IS + SIGNAL b1 : BIT; + SIGNAL b2 : BIT; + SIGNAL b3 : BIT; + SIGNAL b4 : BIT; + SIGNAL b5 : BIT; + SIGNAL b6 : BIT; + +BEGIN + b6 <= b5; + b5 <= b4; + b4 <= b3; + b3 <= b2; + b2 <= b1; + b1 <= b; + label0 : BLOCK (b6 = '1') + BEGIN + pad <= GUARDED i; + END BLOCK label0; + t <= pad; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on piot_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/po_msp.ap b/pdks/symbolic/msplib/cells/po_msp.ap new file mode 100644 index 000000000..474b0a0fb --- /dev/null +++ b/pdks/symbolic/msplib/cells/po_msp.ap @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H po_msp,P, 4/ 9/2014,100 +A 0,0,40000,80000 +C 20000,80000,150,pad,0,NORTH,ALU1 +C 28000,0,300,i,0,SOUTH,ALU1 +C 28000,0,300,i,1,SOUTH,ALU2 +C 0,16000,1800,vddi,6,WEST,ALU3 +C 0,13000,1800,vssi,6,WEST,ALU3 +C 40000,13000,1800,vssi,7,EAST,ALU3 +C 40000,16000,1800,vddi,7,EAST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,7000,1800,vssi,4,WEST,ALU3 +C 0,10000,1800,vddi,4,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,7000,1800,vssi,5,EAST,ALU3 +C 40000,10000,1800,vddi,5,EAST,ALU3 +C 0,4000,750,ck,0,WEST,ALU3 +C 40000,4000,750,ck,1,EAST,ALU3 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +I 0,0,po_mpx,a,NOSYM +V 28000,0,CONT_VIA,* +EOF diff --git a/pdks/symbolic/msplib/cells/po_msp.vbe b/pdks/symbolic/msplib/cells/po_msp.vbe new file mode 100644 index 000000000..4a8b47b15 --- /dev/null +++ b/pdks/symbolic/msplib/cells/po_msp.vbe @@ -0,0 +1,29 @@ +ENTITY po_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_i : NATURAL := 191; + CONSTANT tpll_i : NATURAL := 2176; + CONSTANT rdown_i : NATURAL := 15; + CONSTANT tphh_i : NATURAL := 2032; + CONSTANT rup_i : NATURAL := 16 + ); + PORT ( + i : in BIT; + pad : out BIT; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END po_msp; + +ARCHITECTURE behaviour_data_flow OF po_msp IS + +BEGIN + pad <= i; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on po_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/pot_msp.ap b/pdks/symbolic/msplib/cells/pot_msp.ap new file mode 100644 index 000000000..fd5a51209 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pot_msp.ap @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H pot_msp,P, 4/ 9/2014,100 +A 0,0,40000,80000 +C 20000,80000,150,pad,0,NORTH,ALU1 +C 28000,0,300,i,0,SOUTH,ALU1 +C 28000,0,300,i,1,SOUTH,ALU2 +C 0,16000,1800,vddi,6,WEST,ALU3 +C 0,13000,1800,vssi,6,WEST,ALU3 +C 40000,13000,1800,vssi,7,EAST,ALU3 +C 40000,16000,1800,vddi,7,EAST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,7000,1800,vssi,4,WEST,ALU3 +C 0,10000,1800,vddi,4,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,7000,1800,vssi,5,EAST,ALU3 +C 40000,10000,1800,vddi,5,EAST,ALU3 +C 0,4000,750,ck,0,WEST,ALU3 +C 40000,4000,750,ck,1,EAST,ALU3 +C 30000,0,300,b,1,SOUTH,ALU2 +C 30000,0,300,b,0,SOUTH,ALU1 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +I 0,0,pot_mpx,a,NOSYM +V 28000,0,CONT_VIA,* +V 30000,0,CONT_VIA,b +EOF diff --git a/pdks/symbolic/msplib/cells/pot_msp.vbe b/pdks/symbolic/msplib/cells/pot_msp.vbe new file mode 100644 index 000000000..61c29bbfb --- /dev/null +++ b/pdks/symbolic/msplib/cells/pot_msp.vbe @@ -0,0 +1,42 @@ +ENTITY pot_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT rup : NATURAL := 684404; + CONSTANT rdown : NATURAL := 24 + ); + PORT ( + i : in BIT; + b : in BIT; + pad : out MUX_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pot_msp; + +ARCHITECTURE behaviour_data_flow OF pot_msp IS + SIGNAL b1 : BIT; + SIGNAL b2 : BIT; + SIGNAL b3 : BIT; + SIGNAL b4 : BIT; + SIGNAL b5 : BIT; + SIGNAL b6 : BIT; + +BEGIN + b6 <= b5; + b5 <= b4; + b4 <= b3; + b3 <= b2; + b2 <= b1; + b1 <= b; + label0 : BLOCK (b6 = '1') + BEGIN + pad <= GUARDED i; + END BLOCK label0; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pot_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/pvdde_msp.ap b/pdks/symbolic/msplib/cells/pvdde_msp.ap new file mode 100644 index 000000000..e04ab0bd3 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvdde_msp.ap @@ -0,0 +1,55 @@ +V ALLIANCE : 6 +H pvdde_msp,P, 4/ 9/2014,100 +A 0,0,40000,80000 +C 20000,80000,150,vdde,6,NORTH,ALU1 +C 0,16000,1800,vddi,6,WEST,ALU3 +C 0,13000,1800,vssi,6,WEST,ALU3 +C 40000,13000,1800,vssi,7,EAST,ALU3 +C 40000,16000,1800,vddi,7,EAST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,7000,1800,vssi,4,WEST,ALU3 +C 0,10000,1800,vddi,4,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,7000,1800,vssi,5,EAST,ALU3 +C 40000,10000,1800,vddi,5,EAST,ALU3 +C 0,4000,750,ck,0,WEST,ALU3 +C 40000,4000,750,ck,1,EAST,ALU3 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +I 0,0,pvdde_mpx,a,NOSYM +EOF diff --git a/pdks/symbolic/msplib/cells/pvdde_msp.vbe b/pdks/symbolic/msplib/cells/pvdde_msp.vbe new file mode 100644 index 000000000..5c903314c --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvdde_msp.vbe @@ -0,0 +1,20 @@ +ENTITY pvdde_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000 + ); + PORT ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvdde_msp; + +ARCHITECTURE behaviour_data_flow OF pvdde_msp IS + +BEGIN + ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1') + REPORT "power supply is missing on pvdde_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/pvddeck_msp.ap b/pdks/symbolic/msplib/cells/pvddeck_msp.ap new file mode 100644 index 000000000..3e153fe0e --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvddeck_msp.ap @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H pvddeck_msp,P, 4/ 9/2014,100 +A 0,0,40000,80000 +C 40000,4000,750,ck,5,EAST,ALU3 +C 0,4000,750,ck,4,WEST,ALU3 +C 40000,10000,1800,vddi,1,EAST,ALU3 +C 40000,7000,1800,vssi,1,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,10000,1800,vddi,0,WEST,ALU3 +C 0,7000,1800,vssi,0,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 40000,16000,1800,vddi,3,EAST,ALU3 +C 40000,13000,1800,vssi,3,EAST,ALU3 +C 0,13000,1800,vssi,2,WEST,ALU3 +C 0,16000,1800,vddi,2,WEST,ALU3 +C 20000,80000,150,vdde,6,NORTH,ALU1 +C 19000,0,300,cko,1,SOUTH,ALU2 +C 19000,0,300,cko,0,SOUTH,ALU1 +S 11450,1400,28550,1400,1600,cko,RIGHT,ALU2 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +I 0,0,pvddeck_mpx,a,NOSYM +EOF diff --git a/pdks/symbolic/msplib/cells/pvddeck_msp.vbe b/pdks/symbolic/msplib/cells/pvddeck_msp.vbe new file mode 100644 index 000000000..c037edf80 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvddeck_msp.vbe @@ -0,0 +1,31 @@ +ENTITY pvddeck_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_ck : NATURAL := 127; + CONSTANT tpll_ck : NATURAL := 1055; + CONSTANT rdown_ck : NATURAL := 126; + CONSTANT tphh_ck : NATURAL := 963; + CONSTANT rup_ck : NATURAL := 183 + ); + PORT ( + cko : out WOR_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvddeck_msp; + +ARCHITECTURE behaviour_data_flow OF pvddeck_msp IS + +BEGIN + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; + + ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1') + REPORT "power supply is missing on pvddeck_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/pvddi_msp.ap b/pdks/symbolic/msplib/cells/pvddi_msp.ap new file mode 100644 index 000000000..d29c8bc7a --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvddi_msp.ap @@ -0,0 +1,59 @@ +V ALLIANCE : 6 +H pvddi_msp,P, 4/ 9/2014,100 +A 0,0,40000,80000 +C 20000,0,7800,vddi,10,SOUTH,ALU2 +C 20000,0,7800,vddi,8,SOUTH,ALU1 +S 20000,-150,20000,17150,10400,*,UP,ALU2 +C 40000,4000,750,ck,1,EAST,ALU3 +C 0,4000,750,ck,0,WEST,ALU3 +C 40000,10000,1800,vddi,14,EAST,ALU3 +C 40000,7000,1800,vssi,1,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,10000,1800,vddi,13,WEST,ALU3 +C 0,7000,1800,vssi,0,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 40000,16000,1800,vddi,16,EAST,ALU3 +C 40000,13000,1800,vssi,3,EAST,ALU3 +C 0,13000,1800,vssi,2,WEST,ALU3 +C 0,16000,1800,vddi,15,WEST,ALU3 +C 20000,80000,150,vddi,17,NORTH,ALU1 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +S 20000,-150,20000,17150,10400,*,UP,ALU2 +I 0,0,pvddi_mpx,a,NOSYM +EOF diff --git a/pdks/symbolic/msplib/cells/pvddi_msp.vbe b/pdks/symbolic/msplib/cells/pvddi_msp.vbe new file mode 100644 index 000000000..6857d1a42 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvddi_msp.vbe @@ -0,0 +1,20 @@ +ENTITY pvddi_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000 + ); + PORT ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvddi_msp; + +ARCHITECTURE behaviour_data_flow OF pvddi_msp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvddi_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/pvddick_msp.ap b/pdks/symbolic/msplib/cells/pvddick_msp.ap new file mode 100644 index 000000000..71a833d76 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvddick_msp.ap @@ -0,0 +1,68 @@ +V ALLIANCE : 6 +H pvddick_msp,P, 5/ 9/2014,100 +A 0,0,40000,80000 +C 13000,0,300,cko,4,SOUTH,ALU2 +C 11000,0,300,cko,0,SOUTH,ALU2 +C 20000,80000,150,vddi,6,NORTH,ALU1 +C 0,16000,1800,vddi,4,WEST,ALU3 +C 0,13000,1800,vssi,2,WEST,ALU3 +C 40000,13000,1800,vssi,3,EAST,ALU3 +C 40000,16000,1800,vddi,5,EAST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,7000,1800,vssi,0,WEST,ALU3 +C 0,10000,1800,vddi,2,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,7000,1800,vssi,1,EAST,ALU3 +C 40000,10000,1800,vddi,3,EAST,ALU3 +C 0,4000,750,ck,0,WEST,ALU3 +C 40000,4000,750,ck,1,EAST,ALU3 +C 20000,0,7800,vddi,0,SOUTH,ALU1 +C 20000,0,7800,vddi,1,SOUTH,ALU2 +S 13000,-150,13000,2150,600,*,DOWN,ALU2 +S 11000,850,11000,2150,600,*,UP,ALU2 +S 11000,-150,11000,1150,600,*,DOWN,ALU2 +S 10850,2000,11550,2000,600,*,LEFT,ALU3 +S 10850,1000,11550,1000,600,*,LEFT,ALU3 +S 12000,-150,12000,2150,2400,cko,DOWN,ALU3 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +S 11450,2000,28550,2000,600,*,RIGHT,ALU3 +S 11450,1000,28550,1000,600,*,RIGHT,ALU3 +S 20000,-150,20000,17150,10400,*,UP,ALU2 +I 0,0,pvddick_mpx,a,NOSYM +EOF diff --git a/pdks/symbolic/msplib/cells/pvddick_msp.vbe b/pdks/symbolic/msplib/cells/pvddick_msp.vbe new file mode 100644 index 000000000..b2e5b3d99 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvddick_msp.vbe @@ -0,0 +1,31 @@ +ENTITY pvddick_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_ck : NATURAL := 127; + CONSTANT tpll_ck : NATURAL := 1235; + CONSTANT rdown_ck : NATURAL := 253; + CONSTANT tphh_ck : NATURAL := 1109; + CONSTANT rup_ck : NATURAL := 311 + ); + PORT ( + cko : out WOR_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvddick_msp; + +ARCHITECTURE behaviour_data_flow OF pvddick_msp IS + +BEGIN + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvddick_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/pvsse_msp.ap b/pdks/symbolic/msplib/cells/pvsse_msp.ap new file mode 100644 index 000000000..e096d0b68 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvsse_msp.ap @@ -0,0 +1,55 @@ +V ALLIANCE : 6 +H pvsse_msp,P, 4/ 9/2014,100 +A 0,0,40000,80000 +C 20000,80000,150,vsse,8,NORTH,ALU1 +C 0,16000,1800,vddi,6,WEST,ALU3 +C 0,13000,1800,vssi,6,WEST,ALU3 +C 40000,13000,1800,vssi,7,EAST,ALU3 +C 40000,16000,1800,vddi,7,EAST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,7000,1800,vssi,4,WEST,ALU3 +C 0,10000,1800,vddi,4,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,7000,1800,vssi,5,EAST,ALU3 +C 40000,10000,1800,vddi,5,EAST,ALU3 +C 0,4000,750,ck,0,WEST,ALU3 +C 40000,4000,750,ck,1,EAST,ALU3 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +I 0,0,pvsse_mpx,a,NOSYM +EOF diff --git a/pdks/symbolic/msplib/cells/pvsse_msp.vbe b/pdks/symbolic/msplib/cells/pvsse_msp.vbe new file mode 100644 index 000000000..d441552ca --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvsse_msp.vbe @@ -0,0 +1,20 @@ +ENTITY pvsse_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000 + ); + PORT ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvsse_msp; + +ARCHITECTURE behaviour_data_flow OF pvsse_msp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvsse_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/pvsseck_msp.ap b/pdks/symbolic/msplib/cells/pvsseck_msp.ap new file mode 100644 index 000000000..50ddbfc54 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvsseck_msp.ap @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H pvsseck_msp,P, 4/ 9/2014,100 +A 0,0,40000,80000 +C 20000,80000,150,vsse,8,NORTH,ALU1 +C 0,16000,1800,vddi,6,WEST,ALU3 +C 0,13000,1800,vssi,6,WEST,ALU3 +C 40000,13000,1800,vssi,7,EAST,ALU3 +C 40000,16000,1800,vddi,7,EAST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,7000,1800,vssi,4,WEST,ALU3 +C 0,10000,1800,vddi,4,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,7000,1800,vssi,5,EAST,ALU3 +C 40000,10000,1800,vddi,5,EAST,ALU3 +C 0,4000,750,ck,2,WEST,ALU3 +C 40000,4000,750,ck,3,EAST,ALU3 +C 19000,0,300,cko,1,SOUTH,ALU2 +C 19000,0,300,cko,0,SOUTH,ALU1 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +S 11450,1400,28550,1400,1600,cko,RIGHT,ALU2 +I 0,0,pvsseck_mpx,a,NOSYM +EOF diff --git a/pdks/symbolic/msplib/cells/pvsseck_msp.vbe b/pdks/symbolic/msplib/cells/pvsseck_msp.vbe new file mode 100644 index 000000000..b1715be45 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvsseck_msp.vbe @@ -0,0 +1,31 @@ +ENTITY pvsseck_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_ck : NATURAL := 127; + CONSTANT tpll_ck : NATURAL := 1055; + CONSTANT rdown_ck : NATURAL := 126; + CONSTANT tphh_ck : NATURAL := 963; + CONSTANT rup_ck : NATURAL := 183 + ); + PORT ( + cko : out WOR_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvsseck_msp; + +ARCHITECTURE behaviour_data_flow OF pvsseck_msp IS + +BEGIN + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvsseck_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/pvssi_msp.ap b/pdks/symbolic/msplib/cells/pvssi_msp.ap new file mode 100644 index 000000000..d54c807ac --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvssi_msp.ap @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H pvssi_msp,P, 4/ 9/2014,100 +A 0,0,40000,80000 +C 20000,0,7800,vssi,10,SOUTH,ALU2 +C 20000,0,7800,vssi,8,SOUTH,ALU1 +C 40000,4000,750,ck,1,EAST,ALU3 +C 0,4000,750,ck,0,WEST,ALU3 +C 40000,10000,1800,vddi,1,EAST,ALU3 +C 40000,7000,1800,vssi,5,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,10000,1800,vddi,0,WEST,ALU3 +C 0,7000,1800,vssi,4,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 40000,16000,1800,vddi,3,EAST,ALU3 +C 40000,13000,1800,vssi,7,EAST,ALU3 +C 0,13000,1800,vssi,6,WEST,ALU3 +C 0,16000,1800,vddi,2,WEST,ALU3 +C 20000,80000,150,vssi,8,NORTH,ALU1 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +I 0,0,pvssi_mpx,a,NOSYM +S 20000,-150,20000,17150,10400,*,UP,ALU2 +EOF diff --git a/pdks/symbolic/msplib/cells/pvssi_msp.vbe b/pdks/symbolic/msplib/cells/pvssi_msp.vbe new file mode 100644 index 000000000..b72e6ffea --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvssi_msp.vbe @@ -0,0 +1,20 @@ +ENTITY pvssi_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000 + ); + PORT ( + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvssi_msp; + +ARCHITECTURE behaviour_data_flow OF pvssi_msp IS + +BEGIN + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvssi_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msplib/cells/pvssick_msp.ap b/pdks/symbolic/msplib/cells/pvssick_msp.ap new file mode 100644 index 000000000..df7235a7f --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvssick_msp.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H pvssick_msp,P,10/ 9/2014,100 +A 0,0,40000,80000 +C 12800,0,150,cko,3,SOUTH,ALU1 +C 12800,0,300,cko,4,SOUTH,ALU2 +C 40000,4000,750,ck,1,EAST,ALU3 +C 0,4000,750,ck,0,WEST,ALU3 +C 40000,10000,1800,vddi,1,EAST,ALU3 +C 40000,7000,1800,vssi,3,EAST,ALU3 +C 40000,34000,1800,vdde,5,EAST,ALU3 +C 40000,28000,1800,vdde,3,EAST,ALU3 +C 40000,22000,1800,vdde,1,EAST,ALU3 +C 40000,19000,1800,vsse,1,EAST,ALU3 +C 40000,25000,1800,vsse,3,EAST,ALU3 +C 40000,31000,1800,vsse,5,EAST,ALU3 +C 40000,37000,1800,vsse,7,EAST,ALU3 +C 0,34000,1800,vdde,4,WEST,ALU3 +C 0,28000,1800,vdde,2,WEST,ALU3 +C 0,22000,1800,vdde,0,WEST,ALU3 +C 0,19000,1800,vsse,0,WEST,ALU3 +C 0,10000,1800,vddi,0,WEST,ALU3 +C 0,7000,1800,vssi,2,WEST,ALU3 +C 0,25000,1800,vsse,2,WEST,ALU3 +C 0,31000,1800,vsse,4,WEST,ALU3 +C 0,37000,1800,vsse,6,WEST,ALU3 +C 40000,16000,1800,vddi,3,EAST,ALU3 +C 40000,13000,1800,vssi,5,EAST,ALU3 +C 0,13000,1800,vssi,4,WEST,ALU3 +C 0,16000,1800,vddi,2,WEST,ALU3 +C 20000,80000,150,vssi,6,NORTH,ALU1 +C 20000,0,7800,vssi,0,SOUTH,ALU1 +C 20000,0,7800,vssi,1,SOUTH,ALU2 +C 11600,0,300,cko,2,SOUTH,ALU2 +C 11600,0,300,cko,0,SOUTH,ALU1 +C 11600,0,150,cko,1,SOUTH,ALU1 +S 12800,-150,12800,2150,600,*,UP,ALU2 +S 11450,1000,28550,1000,600,*,RIGHT,ALU3 +S 11450,2000,28550,2000,600,*,RIGHT,ALU3 +S -150,13000,950,13000,2400,*,RIGHT,ALU3 +S -150,10000,950,10000,2400,*,RIGHT,ALU3 +S -150,7000,950,7000,2400,*,RIGHT,ALU3 +S -150,4000,950,4000,1000,*,RIGHT,ALU3 +S -150,37000,950,37000,2400,*,RIGHT,ALU3 +S -150,34000,950,34000,2400,*,RIGHT,ALU3 +S -150,25000,950,25000,2400,*,RIGHT,ALU3 +S -150,31000,950,31000,2400,*,RIGHT,ALU3 +S -150,28000,950,28000,2400,*,RIGHT,ALU3 +S -150,22000,950,22000,2400,*,RIGHT,ALU3 +S -150,19000,950,19000,2400,*,RIGHT,ALU3 +S -150,16000,950,16000,2400,*,RIGHT,ALU3 +S 39050,4000,40150,4000,1000,*,RIGHT,ALU3 +S 39050,7000,40150,7000,2400,*,RIGHT,ALU3 +S 39050,10000,40150,10000,2400,*,RIGHT,ALU3 +S 39050,13000,40150,13000,2400,*,RIGHT,ALU3 +S 39050,16000,40150,16000,2400,*,RIGHT,ALU3 +S 39050,19000,40150,19000,2400,*,RIGHT,ALU3 +S 39050,22000,40150,22000,2400,*,RIGHT,ALU3 +S 39050,25000,40150,25000,2400,*,RIGHT,ALU3 +S 39050,28000,40150,28000,2400,*,RIGHT,ALU3 +S 39050,31000,40150,31000,2400,*,RIGHT,ALU3 +S 39050,34000,40150,34000,2400,*,RIGHT,ALU3 +S 39050,37000,40150,37000,2400,*,RIGHT,ALU3 +S 20000,60100,20000,79900,300,*,DOWN,ALU1 +S 20000,-150,20000,17150,10400,*,UP,ALU2 +S 12000,-150,12000,2150,2400,cko,DOWN,ALU3 +S 11600,-150,11600,2150,600,*,UP,ALU2 +I 0,0,pvssick_mpx,a,NOSYM +V 12800,0,CONT_VIA,* +V 11600,1000,CONT_VIA2,* +V 11600,2000,CONT_VIA2,* +V 11600,0,CONT_VIA,* +EOF diff --git a/pdks/symbolic/msplib/cells/pvssick_msp.vbe b/pdks/symbolic/msplib/cells/pvssick_msp.vbe new file mode 100644 index 000000000..1fa7703a9 --- /dev/null +++ b/pdks/symbolic/msplib/cells/pvssick_msp.vbe @@ -0,0 +1,32 @@ +ENTITY pvssick_msp IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT cin_ck : NATURAL := 127; + CONSTANT tpll_ck : NATURAL := 1235; + CONSTANT rdown_ck : NATURAL := 253; + CONSTANT tphh_ck : NATURAL := 1109; + CONSTANT rup_ck : NATURAL := 311 + ); + PORT ( + cko : out WOR_BIT BUS; + ck : in BIT; + vdde : in BIT; + vddi : in BIT; + vsse : in BIT; + vssi : in BIT + ); +END pvssick_msp; + +ARCHITECTURE behaviour_data_flow OF pvssick_msp IS + +BEGIN + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; + + ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') + REPORT "power supply is missing on pvssick_msp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/CATAL b/pdks/symbolic/msxlib/cells/CATAL new file mode 100644 index 000000000..6fd9b7eb7 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/CATAL @@ -0,0 +1,123 @@ +an2_x05 C +an2_x1 C +an2_x2 C +an3_x1 C +an3_x2 C +an4_x1 C +an4_x2 C +an4_x3 C +aoi21_x05 C +aoi21_x1 C +aoi21_x2 C +aoi22_x05 C +aoi22_x1 C +aoi22_x2 C +aon21_x1 C +aon21_x2 C +aon22_x1 C +aon22_x2 C +bf1_w05 C +bf1_w2 C +bf1_x1 C +bf1_x2 C +bf1_x4 C +bf1_x8 C +bf1_y05 C +bf1_y1 C +bf1_y2 C +cgi2a_x05 C +cgi2a_x1 C +cgi2a_x2 C +cgi2_x05 C +cgi2_x1 C +cgi2_x2 C +cgn2_x1 C +cgn2_x2 C +cgn2_x3 C +cgn2_x4 C +ha2_x2 C +iv1_w2 C +iv1_x05 C +iv1_x1 C +iv1_x2 C +iv1_x3 C +iv1_x4 C +iv1_x8 C +iv1_y2 C +mxi2_x05 C +mxi2_x1 C +nd2ab_x1 C +nd2ab_x2 C +nd2a_x1 C +nd2a_x2 C +nd2_x05 C +nd2_x1 C +nd2_x2 C +nd2_x4 C +nd3_x05 C +nd3_x1 C +nd3_x2 C +nd3_x4 C +nd4_x05 C +nd4_x1 C +nd4_x2 C +nd4_x3 C +nr2a_x05 C +nr2a_x1 C +nr2_x05 C +nr2_x1 C +nr2_x2 C +nr3_x05 C +nr3_x1 C +nr4_x05 C +nr4_x1 C +oai21_x05 C +oai21_x1 C +oai21_x2 C +oai22_x05 C +oai22_x1 C +oai22_x2 C +oan21_x1 C +oan21_x2 C +oan22_x1 C +oan22_x2 C +or2_x1 C +or3_x1 C +or4_x1 C +powmid_x0 C +powmid_x0 F +rowend_x0 C +rowend_x0 F +sff1_x4 C +sff2_x4 C +sff3_x4 C +tie_x0 C +tie_x0 F +vddtie C +vfeed1 C +vfeed1 F +vfeed2 C +vfeed2 F +vfeed3 C +vfeed3 F +vfeed4 C +vfeed4 F +vfeed5 C +vfeed5 F +vfeed6 C +vfeed6 F +vfeed7 C +vfeed7 F +vfeed8 C +vfeed8 F +vsstie C +xaoi21_x05 C +xaoi21_x1 C +xaon21_x05 C +xaon21_x1 C +xaon22_x05 C +xaon22_x1 C +xnr2_x05 C +xnr2_x1 C +xor2_x05 C +xor2_x1 C diff --git a/pdks/symbolic/msxlib/cells/an2_x05.ap b/pdks/symbolic/msxlib/cells/an2_x05.ap new file mode 100644 index 000000000..dd93d6d42 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an2_x05.ap @@ -0,0 +1,85 @@ +V ALLIANCE : 6 +H an2_x05,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 3000,5000,ref_ref,a_50 +R 3000,4000,ref_ref,a_40 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 4000,6000,ref_ref,b_60 +R 4000,7000,ref_ref,b_70 +R 3000,7000,ref_ref,b_70 +R 4000,5000,ref_ref,b_50 +R 2000,7000,ref_ref,z_70 +R 4000,4000,ref_ref,a_40 +S 1100,700,1700,700,600,*,LEFT,PTIE +S 1100,9300,1900,9300,600,*,LEFT,NTIE +S 4000,4900,4000,7000,400,*,UP,ALU1 +S 3000,7000,3000,7000,400,b,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,5000,5000,5000,10000,an2_x05,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 2000,6100,3200,6100,600,*,LEFT,ALU1 +S 4000,5000,4000,7000,400,b,UP,CALU1 +S 4400,6000,4400,8100,600,*,DOWN,PDIF +S 2600,5200,2600,5800,200,*,DOWN,POLY +S 1000,7000,2100,7000,400,*,RIGHT,ALU1 +S 1000,7100,2100,7100,400,*,RIGHT,ALU1 +S 2900,7100,4000,7100,400,*,LEFT,ALU1 +S 2900,7000,4000,7000,400,*,LEFT,ALU1 +S 2000,6000,2000,7600,600,*,DOWN,PDIF +S 2000,7900,2000,9300,400,*,DOWN,ALU1 +S 4400,7900,4400,9300,400,*,DOWN,ALU1 +S 1000,4000,1000,7000,400,z,DOWN,CALU1 +S 1600,3800,1600,4600,200,*,UP,POLY +S 1400,4500,1400,5500,200,*,DOWN,POLY +S 1000,6000,1000,6800,400,*,UP,PDIF +S 1400,5800,1400,7000,200,1z,DOWN,PTRANS +S 1400,7000,1400,7400,200,*,DOWN,POLY +S 900,6000,900,6200,600,*,UP,ALU1 +S 2600,5800,2600,7000,200,1a,DOWN,PTRANS +S 3800,5800,3800,7000,200,1b,DOWN,PTRANS +S 3200,6000,3200,6800,400,*,UP,PDIF +S 2600,7000,2600,7400,200,*,DOWN,POLY +S 3800,7000,3800,7400,200,*,DOWN,POLY +S 1600,3200,1600,3800,200,2z,UP,NTRANS +S 1600,2800,1600,3200,200,*,UP,POLY +S 1000,3400,1000,7100,400,*,DOWN,ALU1 +S 3000,3900,4100,3900,400,*,RIGHT,ALU1 +S 3000,4000,4100,4000,400,*,RIGHT,ALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 3000,3900,3000,5200,400,*,DOWN,ALU1 +S 3000,4000,3000,5000,400,a,DOWN,CALU1 +S 2000,3000,4500,3000,400,*,LEFT,ALU1 +S 3400,2500,3400,3100,600,n1,DOWN,NDIF +S 3000,2300,3000,3300,200,2a,UP,NTRANS +S 4200,2500,4200,3100,400,*,UP,NDIF +S 3800,2300,3800,3300,200,2b,UP,NTRANS +S 3000,1900,3000,2300,200,*,UP,POLY +S 3800,1900,3800,2300,200,*,UP,POLY +S 3000,3300,3000,4900,200,*,UP,POLY +S 3800,3300,3800,5800,200,*,DOWN,POLY +S 2000,3000,2000,6200,400,*,UP,ALU1 +S 2300,700,2300,2100,400,*,DOWN,ALU1 +S 2300,1900,2300,3600,800,*,UP,NDIF +S 2600,5300,3000,5300,200,*,RIGHT,POLY +S 1400,4400,2200,4400,600,*,LEFT,POLY +V 1800,700,CONT_BODY_P,* +V 1100,700,CONT_BODY_P,* +V 2000,9300,CONT_BODY_N,* +V 1100,9300,CONT_BODY_N,* +V 3000,5100,CONT_POLY,* +V 3200,6100,CONT_DIF_P,zn +V 2000,4400,CONT_POLY,zn +V 1000,3500,CONT_DIF_N,* +V 2000,8000,CONT_DIF_P,* +V 4400,8000,CONT_DIF_P,* +V 4000,5000,CONT_POLY,* +V 800,6100,CONT_DIF_P,* +V 4400,3000,CONT_DIF_N,zn +V 2300,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/an2_x05.vbe b/pdks/symbolic/msxlib/cells/an2_x05.vbe new file mode 100644 index 000000000..2f0102420 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an2_x05.vbe @@ -0,0 +1,32 @@ +ENTITY an2_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_b_z : NATURAL := 3810; + CONSTANT rdown_a_z : NATURAL := 3830; + CONSTANT rup_b_z : NATURAL := 4940; + CONSTANT rup_a_z : NATURAL := 4940; + CONSTANT tphh_a_z : NATURAL := 71; + CONSTANT tphh_b_z : NATURAL := 70; + CONSTANT tpll_b_z : NATURAL := 87; + CONSTANT tpll_a_z : NATURAL := 97; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an2_x05; + +ARCHITECTURE behaviour_data_flow OF an2_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an2_x05" + SEVERITY WARNING; + z <= (b and a) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/an2_x1.ap b/pdks/symbolic/msxlib/cells/an2_x1.ap new file mode 100644 index 000000000..36378240f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an2_x1.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H an2_x1,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 4000,4000,ref_ref,a_40 +R 2000,7000,ref_ref,z_70 +R 4000,5000,ref_ref,b_50 +R 3000,7000,ref_ref,b_70 +R 4000,7000,ref_ref,b_70 +R 4000,6000,ref_ref,b_60 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +R 1000,7000,ref_ref,z_70 +R 3000,4000,ref_ref,a_40 +R 3000,5000,ref_ref,a_50 +S 1100,700,1700,700,600,*,LEFT,PTIE +S 1100,9300,1900,9300,600,*,LEFT,NTIE +S 2300,700,2300,2000,600,*,DOWN,ALU1 +S 2300,1900,2300,3600,800,*,UP,NDIF +S 4400,2100,4400,2700,600,*,DOWN,NDIF +S 4400,2000,4400,2800,600,*,DOWN,ALU1 +S 2000,2800,2000,6200,400,*,UP,ALU1 +S 2000,2800,4500,2800,400,*,LEFT,ALU1 +S 3000,4000,3000,5000,400,a,DOWN,CALU1 +S 3000,3900,3000,5200,400,*,DOWN,ALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 3000,4000,4100,4000,400,*,RIGHT,ALU1 +S 3000,3900,4100,3900,400,*,RIGHT,ALU1 +S 900,6000,900,7000,600,*,UP,ALU1 +S 800,7000,2100,7000,400,*,RIGHT,ALU1 +S 3000,2700,3000,4900,200,*,UP,POLY +S 3800,2700,3800,5800,200,*,DOWN,POLY +S 1400,4500,1400,5500,200,*,DOWN,POLY +S 1600,3800,1600,4600,200,*,UP,POLY +S 1000,3400,1000,7000,400,*,DOWN,ALU1 +S 1000,4000,1000,7000,400,z,DOWN,CALU1 +S 4400,7900,4400,9300,400,*,DOWN,ALU1 +S 2000,7900,2000,9300,400,*,DOWN,ALU1 +S 2000,6000,2000,7600,600,*,DOWN,PDIF +S 2900,7000,4000,7000,400,*,LEFT,ALU1 +S 2900,7100,4000,7100,400,*,LEFT,ALU1 +S 2600,5200,2600,5800,200,*,DOWN,POLY +S 4400,6000,4400,8100,600,*,DOWN,PDIF +S 4000,5000,4000,7000,400,b,UP,CALU1 +S 2000,6100,3200,6100,600,*,LEFT,ALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,5000,5000,10000,an2_x1,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 3000,1300,3000,1700,200,*,UP,POLY +S 3800,1300,3800,1700,200,*,UP,POLY +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 3000,7000,3000,7000,400,b,LEFT,CALU1 +S 4000,4900,4000,7000,400,*,UP,ALU1 +S 1400,5800,1400,7800,200,1z,DOWN,PTRANS +S 1000,6000,1000,7600,400,*,UP,PDIF +S 1400,7800,1400,8200,200,*,DOWN,POLY +S 3800,5800,3800,7400,200,1b,DOWN,PTRANS +S 2600,5800,2600,7400,200,1a,DOWN,PTRANS +S 3200,6000,3200,7200,400,*,UP,PDIF +S 2600,7400,2600,7800,200,*,DOWN,POLY +S 3800,7400,3800,7800,200,*,DOWN,POLY +S 800,6200,800,6800,600,*,UP,PDIF +S 1600,2800,1600,3800,200,2z,UP,NTRANS +S 1600,2400,1600,2800,200,*,UP,POLY +S 1200,3000,1200,3600,400,*,UP,NDIF +S 3400,1900,3400,2900,600,n1,DOWN,NDIF +S 3000,1700,3000,3100,200,2a,UP,NTRANS +S 3800,1700,3800,3100,200,2b,UP,NTRANS +S 4200,1900,4200,2900,400,*,UP,NDIF +S 2600,5300,3000,5300,200,*,RIGHT,POLY +S 1400,4400,2200,4400,600,*,LEFT,POLY +V 1800,700,CONT_BODY_P,* +V 1100,700,CONT_BODY_P,* +V 2000,9300,CONT_BODY_N,* +V 1100,9300,CONT_BODY_N,* +V 2300,2000,CONT_DIF_N,* +V 4400,2000,CONT_DIF_N,zn +V 4400,2800,CONT_DIF_N,zn +V 800,6100,CONT_DIF_P,* +V 4000,5000,CONT_POLY,* +V 4400,8000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_N,* +V 2000,4400,CONT_POLY,zn +V 3200,6100,CONT_DIF_P,zn +V 3000,5100,CONT_POLY,* +V 800,6900,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/an2_x1.vbe b/pdks/symbolic/msxlib/cells/an2_x1.vbe new file mode 100644 index 000000000..11d6ba421 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY an2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 2290; + CONSTANT rdown_a_z : NATURAL := 2290; + CONSTANT rup_b_z : NATURAL := 2960; + CONSTANT rup_a_z : NATURAL := 2960; + CONSTANT tphh_a_z : NATURAL := 68; + CONSTANT tphh_b_z : NATURAL := 68; + CONSTANT tpll_b_z : NATURAL := 87; + CONSTANT tpll_a_z : NATURAL := 97; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an2_x1; + +ARCHITECTURE behaviour_data_flow OF an2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an2_x1" + SEVERITY WARNING; + z <= (b and a) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/an2_x2.ap b/pdks/symbolic/msxlib/cells/an2_x2.ap new file mode 100644 index 000000000..c747c4c66 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an2_x2.ap @@ -0,0 +1,94 @@ +V ALLIANCE : 6 +H an2_x2,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 4000,4000,ref_ref,a_40 +R 3000,5000,ref_ref,a_50 +R 3000,4000,ref_ref,a_40 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,3000,ref_ref,z_30 +R 4000,6000,ref_ref,b_60 +R 4000,7000,ref_ref,b_70 +R 3000,7000,ref_ref,b_70 +R 4000,5000,ref_ref,b_50 +R 2000,7000,ref_ref,z_70 +S 1100,700,1700,700,600,*,RIGHT,PTIE +S 3300,9300,3900,9300,600,*,LEFT,NTIE +S 2600,5300,3000,5300,200,*,RIGHT,POLY +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 4400,1900,4400,3000,400,*,DOWN,ALU1 +S 2000,3000,4400,3000,400,*,LEFT,ALU1 +S 4400,2100,4400,2700,600,*,UP,NDIF +S 2300,700,2300,2200,400,*,DOWN,ALU1 +S 2300,1900,2300,3600,800,*,UP,NDIF +S 2000,3000,2000,6200,400,*,UP,ALU1 +S 3000,3900,3000,5200,400,*,DOWN,ALU1 +S 3000,4000,3000,5000,400,a,DOWN,CALU1 +S 3000,3900,4100,3900,400,*,RIGHT,ALU1 +S 3000,4000,4100,4000,400,*,RIGHT,ALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 800,7000,2100,7000,400,*,RIGHT,ALU1 +S 900,5700,900,7000,600,*,UP,ALU1 +S 4000,4900,4000,7100,400,*,UP,ALU1 +S 3000,7000,3000,7000,400,b,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 1400,4200,1400,5500,200,*,DOWN,POLY +S 1000,2600,1000,7000,400,*,DOWN,ALU1 +S 1000,2800,1000,3400,600,*,DOWN,NDIF +S 1600,1900,1600,3800,200,2z,UP,NTRANS +S 3000,1700,3000,3800,200,2a,UP,NTRANS +S 3800,1700,3800,3800,200,2b,UP,NTRANS +S 1400,5500,1400,9300,200,1z,DOWN,PTRANS +S 2600,5800,2600,8300,200,1a,DOWN,PTRANS +S 3800,5800,3800,8300,200,1b,DOWN,PTRANS +S 4200,1900,4200,3600,400,*,UP,NDIF +S 3800,1300,3800,1700,200,*,UP,POLY +S 3000,1300,3000,1700,200,*,UP,POLY +S 3400,1900,3400,3600,600,n1,DOWN,NDIF +S 1200,2100,1200,3600,400,*,UP,NDIF +S 1400,9300,1400,9700,200,*,DOWN,POLY +S 1000,5700,1000,9100,400,*,UP,PDIF +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,5000,5000,5000,10000,an2_x2,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 3000,3800,3000,4900,200,*,UP,POLY +S 2000,6100,3200,6100,600,*,LEFT,ALU1 +S 4000,5000,4000,7000,400,b,UP,CALU1 +S 3200,6000,3200,8100,400,*,UP,PDIF +S 4400,6000,4400,8100,600,*,DOWN,PDIF +S 2600,5200,2600,5800,200,*,DOWN,POLY +S 3800,3800,3800,5800,200,*,DOWN,POLY +S 3800,8300,3800,8700,200,*,DOWN,POLY +S 2600,8300,2600,8700,200,*,DOWN,POLY +S 2900,7100,4000,7100,400,*,LEFT,ALU1 +S 2900,7000,4000,7000,400,*,LEFT,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 1600,1500,1600,1900,200,*,UP,POLY +S 2000,7900,2000,9300,400,*,DOWN,ALU1 +S 4400,7900,4400,9300,400,*,DOWN,ALU1 +S 1600,3800,1600,4600,200,*,UP,POLY +S 2000,5700,2000,9100,600,*,DOWN,PDIF +S 800,6200,800,7000,600,*,UP,PDIF +V 1800,700,CONT_BODY_P,* +V 1100,700,CONT_BODY_P,* +V 3200,9300,CONT_BODY_N,* +V 3900,9300,CONT_BODY_N,* +V 4400,2800,CONT_DIF_N,zn +V 4400,2000,CONT_DIF_N,zn +V 2300,2100,CONT_DIF_N,* +V 3000,5100,CONT_POLY,* +V 1000,2700,CONT_DIF_N,* +V 3200,6100,CONT_DIF_P,zn +V 2000,4400,CONT_POLY,zn +V 1000,3500,CONT_DIF_N,* +V 2000,8000,CONT_DIF_P,* +V 2000,9000,CONT_DIF_P,* +V 4400,8000,CONT_DIF_P,* +V 4000,5000,CONT_POLY,* +V 800,6900,CONT_DIF_P,* +V 800,6100,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/an2_x2.vbe b/pdks/symbolic/msxlib/cells/an2_x2.vbe new file mode 100644 index 000000000..e0be85f1e --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY an2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_a : NATURAL := 6; + CONSTANT rdown_b_z : NATURAL := 1200; + CONSTANT rdown_a_z : NATURAL := 1200; + CONSTANT rup_b_z : NATURAL := 1560; + CONSTANT rup_a_z : NATURAL := 1560; + CONSTANT tphh_a_z : NATURAL := 68; + CONSTANT tphh_b_z : NATURAL := 68; + CONSTANT tpll_b_z : NATURAL := 87; + CONSTANT tpll_a_z : NATURAL := 96; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an2_x2; + +ARCHITECTURE behaviour_data_flow OF an2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an2_x2" + SEVERITY WARNING; + z <= (b and a) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/an3_x1.ap b/pdks/symbolic/msxlib/cells/an3_x1.ap new file mode 100644 index 000000000..0d5304a45 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an3_x1.ap @@ -0,0 +1,110 @@ +V ALLIANCE : 6 +H an3_x1,P, 8/ 8/2014,100 +A 0,0,6000,10000 +R 2000,3000,ref_ref,z_30 +R 5000,3000,ref_ref,c_30 +R 4000,3000,ref_ref,c_30 +R 4000,6000,ref_ref,b_60 +R 5000,6000,ref_ref,b_60 +R 3000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,a_60 +R 3000,7000,ref_ref,a_70 +R 4000,7000,ref_ref,a_70 +R 5000,7000,ref_ref,a_70 +R 5000,4000,ref_ref,c_40 +R 5000,5000,ref_ref,c_50 +R 4000,5000,ref_ref,b_50 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 1000,4000,ref_ref,z_40 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 4000,4000,ref_ref,b_40 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 2200,700,2200,2100,400,*,UP,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 2000,3000,2000,3000,400,z,LEFT,CALU1 +S 3000,5000,3000,7000,400,a,DOWN,CALU1 +S 4000,3000,4000,3000,400,c,LEFT,CALU1 +S 5000,3000,5000,5000,400,c,DOWN,CALU1 +S 5000,2900,5000,5100,400,*,DOWN,ALU1 +S 3900,3000,5000,3000,400,*,RIGHT,ALU1 +S 4000,6100,5100,6100,400,*,RIGHT,ALU1 +S 4000,6000,5100,6000,400,*,RIGHT,ALU1 +S 4000,4000,4000,6000,400,b,DOWN,CALU1 +S 4000,3900,4000,6100,400,*,DOWN,ALU1 +S 5000,6000,5000,6000,400,b,LEFT,CALU1 +S 3900,2900,5000,2900,400,*,RIGHT,ALU1 +S 5000,7000,5000,7000,400,a,LEFT,CALU1 +S 4000,7000,4000,7000,400,a,LEFT,CALU1 +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,5000,6000,5000,10000,an3_x1,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 2000,8000,5500,8000,400,*,RIGHT,ALU1 +S 3000,7000,5100,7000,400,*,RIGHT,ALU1 +S 3000,7100,5100,7100,400,*,RIGHT,ALU1 +S 3000,2000,5300,2000,400,*,LEFT,ALU1 +S 3600,6700,3600,8300,200,1b,UP,PTRANS +S 2400,6700,2400,8300,200,1a,UP,PTRANS +S 3000,6900,3000,8100,1000,*,DOWN,PDIF +S 4200,6900,4200,9100,600,*,UP,PDIF +S 4800,6700,4800,8300,200,1c,UP,PTRANS +S 5200,6900,5200,8100,400,*,DOWN,PDIF +S 2400,8300,2400,8700,200,*,DOWN,POLY +S 3600,8300,3600,8700,200,*,DOWN,POLY +S 4800,8300,4800,8700,200,*,DOWN,POLY +S 3400,1900,3400,3100,600,n1,UP,NDIF +S 3000,1700,3000,3300,200,2a,DOWN,NTRANS +S 3800,1700,3800,3300,200,2b,DOWN,NTRANS +S 4200,1900,4200,3100,600,n2,UP,NDIF +S 4600,1700,4600,3300,200,2c,DOWN,NTRANS +S 5000,1900,5000,3100,400,*,UP,NDIF +S 1200,2500,1200,3100,400,*,UP,NDIF +S 1600,2300,1600,3300,200,2z,DOWN,NTRANS +S 1600,1900,1600,2300,200,*,DOWN,POLY +S 3000,1300,3000,1700,200,*,DOWN,POLY +S 3800,1300,3800,1700,200,*,DOWN,POLY +S 4600,1300,4600,1700,200,*,DOWN,POLY +S 2300,1900,2300,3100,800,*,UP,NDIF +S 3600,6100,3600,6700,200,*,DOWN,POLY +S 4600,3300,4600,3800,200,*,UP,POLY +S 4800,3900,4800,6700,200,*,DOWN,POLY +S 3800,3300,3800,6000,200,*,UP,POLY +S 2400,5200,2400,6700,200,*,DOWN,POLY +S 2400,5200,3000,5200,200,*,RIGHT,POLY +S 3000,3300,3000,5200,200,*,DOWN,POLY +S 1000,2900,1000,7100,400,*,DOWN,ALU1 +S 1000,3000,2000,3000,600,*,RIGHT,ALU1 +S 3000,4900,3000,7000,400,*,DOWN,ALU1 +S 2000,4000,3000,4000,400,*,RIGHT,ALU1 +S 2000,4000,2000,8000,400,*,UP,ALU1 +S 3000,2000,3000,4000,400,*,DOWN,ALU1 +S 1200,4300,1800,4300,200,*,RIGHT,POLY +S 1600,3300,1600,4300,200,*,UP,POLY +S 500,7100,1000,7100,400,*,RIGHT,ALU1 +S 1200,6000,1200,8000,200,1z,UP,PTRANS +S 800,6200,800,7800,400,*,UP,PDIF +S 600,6400,600,7000,600,*,UP,PDIF +S 1800,6200,1800,9100,600,*,DOWN,PDIF +S 500,6300,1000,6300,400,*,RIGHT,ALU1 +S 1200,8000,1200,8400,200,*,DOWN,POLY +S 1200,4300,1200,6000,200,*,DOWN,POLY +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 3000,9300,CONT_BODY_N,* +V 2200,2000,CONT_DIF_N,* +V 5400,8000,CONT_DIF_P,zn +V 3000,8000,CONT_DIF_P,zn +V 5200,2000,CONT_DIF_N,zn +V 1800,9000,CONT_DIF_P,* +V 4200,9000,CONT_DIF_P,* +V 4000,6000,CONT_POLY,* +V 5000,3900,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 1000,3000,CONT_DIF_N,* +V 2000,4100,CONT_POLY,zn +V 600,7100,CONT_DIF_P,* +V 600,6300,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/an3_x1.vbe b/pdks/symbolic/msxlib/cells/an3_x1.vbe new file mode 100644 index 000000000..0f9f78c02 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY an3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 2310; + CONSTANT rdown_b_z : NATURAL := 2300; + CONSTANT rdown_c_z : NATURAL := 2290; + CONSTANT rup_a_z : NATURAL := 2970; + CONSTANT rup_b_z : NATURAL := 2970; + CONSTANT rup_c_z : NATURAL := 2970; + CONSTANT tphh_c_z : NATURAL := 88; + CONSTANT tphh_b_z : NATURAL := 91; + CONSTANT tphh_a_z : NATURAL := 93; + CONSTANT tpll_a_z : NATURAL := 121; + CONSTANT tpll_b_z : NATURAL := 111; + CONSTANT tpll_c_z : NATURAL := 100; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an3_x1; + +ARCHITECTURE behaviour_data_flow OF an3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an3_x1" + SEVERITY WARNING; + z <= ((a and b) and c) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/an3_x2.ap b/pdks/symbolic/msxlib/cells/an3_x2.ap new file mode 100644 index 000000000..291cb565a --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an3_x2.ap @@ -0,0 +1,114 @@ +V ALLIANCE : 6 +H an3_x2,P, 8/ 8/2014,100 +A 0,0,6000,10000 +R 2000,8000,ref_ref,z_80 +R 1000,8000,ref_ref,z_80 +R 4000,4000,ref_ref,a_40 +R 3000,4000,ref_ref,a_40 +R 5000,7000,ref_ref,b_70 +R 5000,3000,ref_ref,c_30 +R 4000,3000,ref_ref,c_30 +R 4000,6000,ref_ref,b_60 +R 5000,6000,ref_ref,b_60 +R 3000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,a_60 +R 5000,4000,ref_ref,c_40 +R 5000,5000,ref_ref,c_50 +R 4000,5000,ref_ref,b_50 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 1000,4000,ref_ref,z_40 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +S 4800,4200,4800,6900,200,*,DOWN,POLY +S 4800,9300,4800,9700,200,*,DOWN,POLY +S 5200,7100,5200,9100,400,*,DOWN,PDIF +S 4800,6900,4800,9300,200,1c,UP,PTRANS +S 500,6200,1000,6200,400,*,RIGHT,ALU1 +S 600,6300,600,6900,600,*,UP,PDIF +S 500,7000,1000,7000,400,*,RIGHT,ALU1 +S 2000,8000,2000,8000,400,z,LEFT,CALU1 +S 1000,8000,2000,8000,600,*,RIGHT,ALU1 +S 1000,2600,1000,8100,400,*,DOWN,ALU1 +S 1000,3000,1000,8000,400,z,DOWN,CALU1 +S 3000,8000,5500,8000,400,*,RIGHT,ALU1 +S 3000,7000,3000,8000,400,*,UP,ALU1 +S 2000,7000,3000,7000,400,*,RIGHT,ALU1 +S 2000,3000,2000,7000,400,*,UP,ALU1 +S 3000,3900,3000,6100,400,*,DOWN,ALU1 +S 3000,4000,3000,6000,400,a,DOWN,CALU1 +S 3000,3900,4100,3900,400,*,RIGHT,ALU1 +S 3000,4000,4100,4000,400,*,RIGHT,ALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 3000,2000,3000,3000,400,*,DOWN,ALU1 +S 2000,3000,3000,3000,400,*,RIGHT,ALU1 +S 4000,5000,4000,6000,400,b,DOWN,CALU1 +S 4000,4900,4000,6100,400,*,DOWN,ALU1 +S 5000,6000,5000,7000,600,*,UP,ALU1 +S 5000,6000,5000,7000,400,b,UP,CALU1 +S 1200,9300,1200,9700,200,*,DOWN,POLY +S 3600,8400,3600,8800,200,*,DOWN,POLY +S 2400,8400,2400,8800,200,*,DOWN,POLY +S 3600,5500,3600,6000,200,*,DOWN,POLY +S 2800,4600,2800,5600,200,*,DOWN,POLY +S 2400,5600,2800,5600,200,*,RIGHT,POLY +S 4200,6200,4200,9100,600,*,UP,PDIF +S 3000,6200,3000,8200,1000,*,DOWN,PDIF +S 2400,6000,2400,8400,200,1a,UP,PTRANS +S 3600,6000,3600,8400,200,1b,UP,PTRANS +S 2200,700,2200,2100,400,*,UP,ALU1 +S 3000,3800,3000,4600,200,*,UP,POLY +S 4600,3800,4600,4300,200,*,UP,POLY +S 4000,3000,4000,3000,400,c,LEFT,CALU1 +S 5000,3000,5000,5000,400,c,DOWN,CALU1 +S 5000,2900,5000,5100,400,*,DOWN,ALU1 +S 3900,3000,5000,3000,400,*,RIGHT,ALU1 +S 3800,4100,3800,5300,200,*,UP,POLY +S 4000,6100,5100,6100,400,*,RIGHT,ALU1 +S 4000,6000,5100,6000,400,*,RIGHT,ALU1 +S 3900,2900,5000,2900,400,*,RIGHT,ALU1 +S 1000,2800,1000,3400,600,*,DOWN,NDIF +S 1600,1900,1600,3800,200,2z,DOWN,NTRANS +S 3000,1400,3000,3800,200,2a,DOWN,NTRANS +S 3800,1400,3800,3800,200,2b,DOWN,NTRANS +S 4600,1400,4600,3800,200,2c,DOWN,NTRANS +S 1200,5500,1200,9300,200,1z,UP,PTRANS +S 1200,4600,1800,4600,200,*,RIGHT,POLY +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,5000,6000,5000,10000,an3_x2,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 1800,5700,1800,9100,600,*,DOWN,PDIF +S 800,5700,800,9100,400,*,UP,PDIF +S 3000,1000,3000,1400,200,*,DOWN,POLY +S 3800,1000,3800,1400,200,*,DOWN,POLY +S 4600,1000,4600,1400,200,*,DOWN,POLY +S 5000,1600,5000,3600,400,*,UP,NDIF +S 1600,1500,1600,1900,200,*,DOWN,POLY +S 1200,2100,1200,3600,400,*,UP,NDIF +S 2300,900,2300,3600,800,*,UP,NDIF +S 1200,4600,1200,5500,200,*,DOWN,POLY +S 1600,3800,1600,4600,200,*,UP,POLY +S 3000,2000,5300,2000,400,*,LEFT,ALU1 +S 3400,1600,3400,3600,600,n1,UP,NDIF +S 4200,1600,4200,3600,600,n2,UP,NDIF +V 1000,700,CONT_BODY_P,* +V 3000,9300,CONT_BODY_N,* +V 5400,8000,CONT_DIF_P,zn +V 600,6200,CONT_DIF_P,* +V 600,7000,CONT_DIF_P,* +V 3000,7900,CONT_DIF_P,zn +V 3000,7100,CONT_DIF_P,zn +V 4000,5400,CONT_POLY,* +V 3000,4700,CONT_POLY,* +V 2200,1000,CONT_DIF_N,* +V 2200,2000,CONT_DIF_N,* +V 5000,4400,CONT_POLY,* +V 1000,2700,CONT_DIF_N,* +V 2000,4400,CONT_POLY,zn +V 5200,2000,CONT_DIF_N,zn +V 1800,9000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_N,* +V 4200,9000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/an3_x2.vbe b/pdks/symbolic/msxlib/cells/an3_x2.vbe new file mode 100644 index 000000000..2fb10d66d --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY an3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_a : NATURAL := 6; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_c : NATURAL := 6; + CONSTANT rdown_a_z : NATURAL := 1210; + CONSTANT rdown_b_z : NATURAL := 1210; + CONSTANT rdown_c_z : NATURAL := 1210; + CONSTANT rup_a_z : NATURAL := 1560; + CONSTANT rup_b_z : NATURAL := 1560; + CONSTANT rup_c_z : NATURAL := 1560; + CONSTANT tphh_c_z : NATURAL := 86; + CONSTANT tphh_b_z : NATURAL := 89; + CONSTANT tphh_a_z : NATURAL := 91; + CONSTANT tpll_a_z : NATURAL := 119; + CONSTANT tpll_b_z : NATURAL := 109; + CONSTANT tpll_c_z : NATURAL := 98; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an3_x2; + +ARCHITECTURE behaviour_data_flow OF an3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an3_x2" + SEVERITY WARNING; + z <= ((a and b) and c) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/an4_x1.ap b/pdks/symbolic/msxlib/cells/an4_x1.ap new file mode 100644 index 000000000..73b6d847e --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an4_x1.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H an4_x1,P, 8/ 8/2014,100 +A 0,0,7000,10000 +R 2000,3000,ref_ref,z_30 +R 4000,5000,ref_ref,b_50 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 1000,4000,ref_ref,z_40 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 4000,4000,ref_ref,b_40 +R 4000,3000,ref_ref,b_30 +R 5000,3000,ref_ref,b_30 +R 5000,7000,ref_ref,d_70 +R 6000,7000,ref_ref,d_70 +R 6000,6000,ref_ref,d_60 +R 6000,5000,ref_ref,d_50 +R 4000,6000,ref_ref,c_60 +R 5000,6000,ref_ref,c_60 +R 5000,5000,ref_ref,c_50 +R 5000,4000,ref_ref,c_40 +R 4000,7000,ref_ref,a_70 +R 3000,7000,ref_ref,a_70 +R 3000,6000,ref_ref,a_60 +R 3000,5000,ref_ref,a_50 +R 1000,8000,ref_ref,z_80 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 4000,2900,4000,5200,400,*,DOWN,ALU1 +S 3100,2000,6000,2000,400,*,LEFT,ALU1 +S 2000,3000,2000,3000,400,z,LEFT,CALU1 +S 6000,8300,6000,8600,200,*,DOWN,POLY +S 2000,8000,5500,8000,400,*,RIGHT,ALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,5000,7000,5000,10000,an4_x1,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 4800,8300,4800,8700,200,*,DOWN,POLY +S 500,6600,1000,6600,400,*,RIGHT,ALU1 +S 3600,8300,3600,8700,200,*,DOWN,POLY +S 2400,8300,2400,8700,200,*,DOWN,POLY +S 5000,7000,5000,7000,400,d,LEFT,CALU1 +S 5000,3000,5000,3000,400,b,LEFT,CALU1 +S 4000,6000,4000,6000,400,c,LEFT,CALU1 +S 4000,7000,4000,7000,400,a,LEFT,CALU1 +S 4000,3000,4000,5000,400,b,DOWN,CALU1 +S 4000,2900,5100,2900,400,*,RIGHT,ALU1 +S 4000,3000,5100,3000,400,*,RIGHT,ALU1 +S 5000,3900,5000,6100,400,*,DOWN,ALU1 +S 3900,6000,5000,6000,400,*,RIGHT,ALU1 +S 3900,6100,5000,6100,400,*,RIGHT,ALU1 +S 3000,7000,4100,7000,400,*,RIGHT,ALU1 +S 3000,7100,4100,7100,400,*,RIGHT,ALU1 +S 6000,5000,6000,7000,400,d,UP,CALU1 +S 6000,4900,6000,7000,400,*,UP,ALU1 +S 4900,7000,6000,7000,400,*,LEFT,ALU1 +S 4900,7100,6000,7100,400,*,LEFT,ALU1 +S 5000,4000,5000,6000,400,c,DOWN,CALU1 +S 3000,4900,3000,7000,400,*,DOWN,ALU1 +S 3000,5000,3000,7000,400,a,DOWN,CALU1 +S 3600,6700,3600,8300,200,1b,UP,PTRANS +S 3000,6900,3000,8100,1000,*,DOWN,PDIF +S 2400,6700,2400,8300,200,1a,UP,PTRANS +S 5400,6900,5400,8100,600,*,DOWN,PDIF +S 6000,6700,6000,8300,200,1d,UP,PTRANS +S 4800,6700,4800,8300,200,1c,UP,PTRANS +S 4200,6900,4200,9100,600,*,UP,PDIF +S 6500,6900,6500,9300,400,*,UP,PDIF +S 6000,4800,6000,6700,200,*,DOWN,POLY +S 1800,6500,1800,9100,600,*,DOWN,PDIF +S 1200,6300,1200,8300,200,1z,UP,PTRANS +S 800,6500,800,8100,400,*,UP,PDIF +S 1200,8300,1200,8700,200,*,DOWN,POLY +S 1000,3000,2000,3000,600,*,RIGHT,ALU1 +S 2300,1900,2300,3400,800,*,UP,NDIF +S 2300,700,2300,2100,400,*,DOWN,ALU1 +S 1600,2600,1600,3600,200,2z,DOWN,NTRANS +S 1200,2800,1200,3400,400,*,UP,NDIF +S 1600,2200,1600,2600,200,*,DOWN,POLY +S 3000,1300,3000,1700,200,*,DOWN,POLY +S 3800,1300,3800,1700,200,*,DOWN,POLY +S 4600,1300,4600,1700,200,*,DOWN,POLY +S 5400,1300,5400,1700,200,*,DOWN,POLY +S 3000,1700,3000,3600,200,2a,DOWN,NTRANS +S 3400,1900,3400,3400,600,n1,UP,NDIF +S 3800,1700,3800,3600,200,2b,DOWN,NTRANS +S 5000,1900,5000,3400,600,n3,UP,NDIF +S 4600,1700,4600,3600,200,2c,DOWN,NTRANS +S 5400,1700,5400,3600,200,2d,DOWN,NTRANS +S 5800,1900,5800,3400,400,*,UP,NDIF +S 4200,1900,4200,3400,600,n2,UP,NDIF +S 3800,3600,3800,4800,200,*,UP,POLY +S 6000,2100,6000,2700,600,*,UP,NDIF +S 6000,2000,6000,2800,600,*,UP,ALU1 +S 5400,4000,5800,4000,200,*,RIGHT,POLY +S 5800,4000,5800,4800,200,*,UP,POLY +S 4800,4000,4800,6700,200,*,DOWN,POLY +S 4600,3600,4600,4100,200,*,UP,POLY +S 3600,4700,3600,6700,200,*,DOWN,POLY +S 2000,4100,3100,4100,400,*,RIGHT,ALU1 +S 2000,4100,2000,8000,400,*,UP,ALU1 +S 3100,2000,3100,4100,400,*,DOWN,ALU1 +S 1200,4400,1600,4400,200,*,RIGHT,POLY +S 1200,4400,1200,6300,200,*,DOWN,POLY +S 1600,3600,1600,4400,200,*,UP,POLY +S 2400,5800,2400,6700,200,*,DOWN,POLY +S 3000,3600,3000,5900,200,*,UP,POLY +S 2800,6000,3000,6000,600,*,RIGHT,ALU1 +S 600,6700,600,7300,600,*,DOWN,PDIF +S 500,7400,1000,7400,400,*,RIGHT,ALU1 +S 1000,3000,1000,8000,400,z,DOWN,CALU1 +S 1000,2900,1000,8100,400,*,DOWN,ALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 3000,9300,CONT_BODY_N,* +V 6400,9200,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,zn +V 4200,9000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,zn +V 1800,9000,CONT_DIF_P,* +V 600,6600,CONT_DIF_P,* +V 6000,5000,CONT_POLY,* +V 2300,2000,CONT_DIF_N,* +V 1000,3300,CONT_DIF_N,* +V 6000,2000,CONT_DIF_N,zn +V 6000,2800,CONT_DIF_N,zn +V 4000,4900,CONT_POLY,* +V 5000,6000,CONT_POLY,* +V 2000,4200,CONT_POLY,zn +V 2800,6000,CONT_POLY,* +V 600,7400,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/an4_x1.vbe b/pdks/symbolic/msxlib/cells/an4_x1.vbe new file mode 100644 index 000000000..bdfe74fbf --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY an4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT cin_d : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 2330; + CONSTANT rdown_b_z : NATURAL := 2320; + CONSTANT rdown_c_z : NATURAL := 2310; + CONSTANT rdown_d_z : NATURAL := 2300; + CONSTANT rup_a_z : NATURAL := 2980; + CONSTANT rup_b_z : NATURAL := 2980; + CONSTANT rup_c_z : NATURAL := 2980; + CONSTANT rup_d_z : NATURAL := 2980; + CONSTANT tphh_a_z : NATURAL := 115; + CONSTANT tphh_b_z : NATURAL := 112; + CONSTANT tpll_d_z : NATURAL := 107; + CONSTANT tphh_c_z : NATURAL := 106; + CONSTANT tpll_c_z : NATURAL := 121; + CONSTANT tphh_d_z : NATURAL := 98; + CONSTANT tpll_b_z : NATURAL := 133; + CONSTANT tpll_a_z : NATURAL := 142; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an4_x1; + +ARCHITECTURE behaviour_data_flow OF an4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an4_x1" + SEVERITY WARNING; + z <= (((a and b) and c) and d) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/an4_x2.ap b/pdks/symbolic/msxlib/cells/an4_x2.ap new file mode 100644 index 000000000..fda7322a4 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an4_x2.ap @@ -0,0 +1,133 @@ +V ALLIANCE : 6 +H an4_x2,P, 8/ 8/2014,100 +A 0,0,7000,10000 +R 2000,3000,ref_ref,z_30 +R 4000,5000,ref_ref,b_50 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 1000,4000,ref_ref,z_40 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 4000,4000,ref_ref,b_40 +R 4000,3000,ref_ref,b_30 +R 5000,3000,ref_ref,b_30 +R 5000,7000,ref_ref,d_70 +R 6000,7000,ref_ref,d_70 +R 6000,6000,ref_ref,d_60 +R 6000,5000,ref_ref,d_50 +R 4000,6000,ref_ref,c_60 +R 5000,6000,ref_ref,c_60 +R 5000,5000,ref_ref,c_50 +R 5000,4000,ref_ref,c_40 +R 4000,7000,ref_ref,a_70 +R 3000,7000,ref_ref,a_70 +R 3000,6000,ref_ref,a_60 +R 3000,5000,ref_ref,a_50 +R 1000,2000,ref_ref,z_20 +S 3800,3800,3800,5100,200,*,UP,POLY +S 4600,3800,4600,4300,200,*,UP,POLY +S 4000,2900,4000,5200,400,*,DOWN,ALU1 +S 3600,4900,3600,5900,200,*,DOWN,POLY +S 2300,700,2300,2200,400,*,DOWN,ALU1 +S 2300,1200,2300,3600,800,*,UP,NDIF +S 2000,4000,3100,4000,400,*,RIGHT,ALU1 +S 3100,2000,6000,2000,400,*,LEFT,ALU1 +S 3100,2000,3100,4000,400,*,DOWN,ALU1 +S 1000,3000,2100,3000,400,*,RIGHT,ALU1 +S 2000,3000,2000,3000,400,z,LEFT,CALU1 +S 6000,2300,6000,2900,600,*,UP,NDIF +S 6000,2000,6000,3100,400,*,UP,ALU1 +S 6000,8300,6000,8600,200,*,DOWN,POLY +S 6500,6100,6500,9300,400,*,UP,PDIF +S 2000,8000,5500,8000,400,*,RIGHT,ALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,5000,7000,5000,10000,an4_x2,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 6000,4800,6000,5900,200,*,DOWN,POLY +S 4800,4200,4800,5900,200,*,DOWN,POLY +S 4800,8300,4800,8700,200,*,DOWN,POLY +S 5400,6100,5400,8100,600,*,DOWN,PDIF +S 6000,5900,6000,8300,200,1d,UP,PTRANS +S 4800,5900,4800,8300,200,1c,UP,PTRANS +S 4200,6100,4200,9100,600,*,UP,PDIF +S 500,6600,1000,6600,400,*,RIGHT,ALU1 +S 500,5800,1000,5800,400,*,RIGHT,ALU1 +S 2900,4900,2900,5200,600,*,UP,ALU1 +S 2400,5200,2400,5900,200,*,DOWN,POLY +S 1800,4400,2000,4400,600,*,RIGHT,ALU1 +S 1200,4600,1600,4600,200,*,RIGHT,POLY +S 1200,4600,1200,5500,200,*,DOWN,POLY +S 3600,8300,3600,8700,200,*,DOWN,POLY +S 2400,8300,2400,8700,200,*,DOWN,POLY +S 3600,5900,3600,8300,200,1b,UP,PTRANS +S 2400,5900,2400,8300,200,1a,UP,PTRANS +S 3000,6100,3000,8100,1000,*,DOWN,PDIF +S 1800,5700,1800,9100,600,*,DOWN,PDIF +S 1200,9300,1200,9700,200,*,DOWN,POLY +S 600,5900,600,6700,600,*,UP,PDIF +S 1200,5500,1200,9300,200,1z,UP,PTRANS +S 800,5700,800,9100,400,*,UP,PDIF +S 5000,7000,5000,7000,400,d,LEFT,CALU1 +S 5000,3000,5000,3000,400,b,LEFT,CALU1 +S 4000,6000,4000,6000,400,c,LEFT,CALU1 +S 4000,7000,4000,7000,400,a,LEFT,CALU1 +S 1000,2800,1000,3400,600,*,DOWN,NDIF +S 5400,600,5400,1000,200,*,DOWN,POLY +S 4600,600,4600,1000,200,*,DOWN,POLY +S 3800,600,3800,1000,200,*,DOWN,POLY +S 3000,600,3000,1000,200,*,DOWN,POLY +S 5800,1200,5800,3600,400,*,UP,NDIF +S 5400,1000,5400,3800,200,2d,DOWN,NTRANS +S 5000,1200,5000,3600,600,n3,UP,NDIF +S 4600,1000,4600,3800,200,2c,DOWN,NTRANS +S 4200,1200,4200,3600,600,n2,UP,NDIF +S 3000,1000,3000,3800,200,2a,DOWN,NTRANS +S 3800,1000,3800,3800,200,2b,DOWN,NTRANS +S 3400,1200,3400,3600,600,n1,UP,NDIF +S 4000,3000,4000,5000,400,b,DOWN,CALU1 +S 4000,2900,5100,2900,400,*,RIGHT,ALU1 +S 4000,3000,5100,3000,400,*,RIGHT,ALU1 +S 5000,3900,5000,6100,400,*,DOWN,ALU1 +S 3900,6000,5000,6000,400,*,RIGHT,ALU1 +S 3900,6100,5000,6100,400,*,RIGHT,ALU1 +S 1600,1500,1600,1900,200,*,DOWN,POLY +S 1200,2100,1200,3600,400,*,UP,NDIF +S 3000,3800,3000,4900,200,*,UP,POLY +S 5400,4200,5800,4200,200,*,RIGHT,POLY +S 5800,4200,5800,4800,200,*,UP,POLY +S 3000,7000,4100,7000,400,*,RIGHT,ALU1 +S 3000,7100,4100,7100,400,*,RIGHT,ALU1 +S 6000,5000,6000,7000,400,d,UP,CALU1 +S 6000,4900,6000,7000,400,*,UP,ALU1 +S 4900,7000,6000,7000,400,*,LEFT,ALU1 +S 4900,7100,6000,7100,400,*,LEFT,ALU1 +S 5000,4000,5000,6000,400,c,DOWN,CALU1 +S 3000,4900,3000,7000,400,*,DOWN,ALU1 +S 3000,5000,3000,7000,400,a,DOWN,CALU1 +S 2000,4000,2000,8000,400,*,UP,ALU1 +S 1600,1900,1600,3800,200,2z,DOWN,NTRANS +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1000,1900,1000,7100,400,*,DOWN,ALU1 +V 1000,700,CONT_BODY_P,* +V 3000,9300,CONT_BODY_N,* +V 5000,5100,CONT_POLY,* +V 4000,5100,CONT_POLY,* +V 2300,1300,CONT_DIF_N,* +V 2300,2100,CONT_DIF_N,* +V 6000,2200,CONT_DIF_N,zn +V 6000,3000,CONT_DIF_N,zn +V 6400,9200,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,zn +V 4200,9000,CONT_DIF_P,* +V 2800,5100,CONT_POLY,* +V 1800,4400,CONT_POLY,zn +V 3000,8000,CONT_DIF_P,zn +V 1800,9000,CONT_DIF_P,* +V 600,6600,CONT_DIF_P,* +V 600,5800,CONT_DIF_P,* +V 1000,2700,CONT_DIF_N,* +V 1000,3500,CONT_DIF_N,* +V 6000,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/an4_x2.vbe b/pdks/symbolic/msxlib/cells/an4_x2.vbe new file mode 100644 index 000000000..ac82e4f9d --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY an4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_a : NATURAL := 7; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_c : NATURAL := 6; + CONSTANT cin_d : NATURAL := 6; + CONSTANT rdown_a_z : NATURAL := 1220; + CONSTANT rdown_b_z : NATURAL := 1220; + CONSTANT rdown_c_z : NATURAL := 1210; + CONSTANT rdown_d_z : NATURAL := 1210; + CONSTANT rup_a_z : NATURAL := 1570; + CONSTANT rup_b_z : NATURAL := 1570; + CONSTANT rup_c_z : NATURAL := 1570; + CONSTANT rup_d_z : NATURAL := 1570; + CONSTANT tphh_a_z : NATURAL := 112; + CONSTANT tphh_b_z : NATURAL := 110; + CONSTANT tpll_d_z : NATURAL := 105; + CONSTANT tphh_c_z : NATURAL := 104; + CONSTANT tpll_c_z : NATURAL := 118; + CONSTANT tphh_d_z : NATURAL := 97; + CONSTANT tpll_b_z : NATURAL := 130; + CONSTANT tpll_a_z : NATURAL := 139; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an4_x2; + +ARCHITECTURE behaviour_data_flow OF an4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an4_x2" + SEVERITY WARNING; + z <= (((a and b) and c) and d) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/an4_x3.ap b/pdks/symbolic/msxlib/cells/an4_x3.ap new file mode 100644 index 000000000..d1daacfc8 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an4_x3.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 6 +H an4_x3,P, 8/ 8/2014,100 +A 0,0,9000,10000 +R 8000,5000,ref_ref,d_50 +R 8000,7000,ref_ref,d_70 +R 8000,6000,ref_ref,d_60 +R 1000,7000,ref_ref,z_70 +R 6000,6000,ref_ref,d_60 +R 7000,5000,ref_ref,d_50 +R 6000,5000,ref_ref,c_50 +R 6000,6000,ref_ref,c_60 +R 5000,6000,ref_ref,c_60 +R 5000,7000,ref_ref,a_70 +R 4000,7000,ref_ref,a_70 +R 4000,6000,ref_ref,a_60 +R 6000,3000,ref_ref,b_30 +R 6000,4000,ref_ref,c_40 +R 5000,3000,ref_ref,b_30 +R 5000,4000,ref_ref,b_40 +R 5000,5000,ref_ref,b_50 +R 4000,5000,ref_ref,a_50 +R 2000,7000,ref_ref,z_70 +R 2000,8000,ref_ref,z_80 +R 2000,3000,ref_ref,z_30 +R 2000,4000,ref_ref,z_40 +R 2000,5000,ref_ref,z_50 +R 2000,6000,ref_ref,z_60 +S 8000,4900,8000,7100,400,*,UP,ALU1 +S 3000,8000,6600,8000,400,*,RIGHT,ALU1 +S 6600,6900,6600,8000,400,*,DOWN,ALU1 +S 6900,5000,8000,5000,600,*,LEFT,ALU1 +S 7000,5000,7000,5000,400,d,LEFT,CALU1 +S 8000,5000,8000,7000,400,d,UP,CALU1 +S 7800,7900,7800,9300,400,*,DOWN,ALU1 +S 1200,9300,1200,9700,200,*,DOWN,POLY +S 7200,2300,7200,2900,600,*,UP,NDIF +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,9000,5000,10000,an4_x3,LEFT,TALU8 +S 0,2200,9000,2200,5200,*,LEFT,PWELL +S 0,7600,9000,7600,5600,*,LEFT,NWELL +S 6000,4000,6000,6000,400,c,DOWN,CALU1 +S 6000,3900,6000,6100,400,*,DOWN,ALU1 +S 4900,6000,6000,6000,400,*,RIGHT,ALU1 +S 4900,6100,6000,6100,400,*,RIGHT,ALU1 +S 5000,6000,5000,6000,400,c,LEFT,CALU1 +S 4000,7000,5100,7000,400,*,RIGHT,ALU1 +S 4000,7100,5100,7100,400,*,RIGHT,ALU1 +S 5000,7000,5000,7000,400,a,LEFT,CALU1 +S 4000,4900,4000,7000,400,*,DOWN,ALU1 +S 4000,5000,4000,7000,400,a,DOWN,CALU1 +S 7200,2000,7200,3100,400,*,UP,ALU1 +S 5000,3000,6100,3000,400,*,RIGHT,ALU1 +S 6000,3000,6000,3000,400,b,LEFT,CALU1 +S 5000,2900,6100,2900,400,*,RIGHT,ALU1 +S 5000,3000,5000,5000,400,b,DOWN,CALU1 +S 5400,1200,5400,3700,600,n2,UP,NDIF +S 5800,3900,5800,6000,200,*,UP,POLY +S 5000,3900,5000,5100,200,*,UP,POLY +S 1200,6700,1200,9300,200,1z,UP,PTRANS +S 1800,6900,1800,9100,600,*,DOWN,PDIF +S 4800,6400,4800,9300,200,1b,UP,PTRANS +S 4200,6600,4200,9100,1000,*,DOWN,PDIF +S 3600,6400,3600,9300,200,1a,UP,PTRANS +S 3000,6600,3000,9100,600,*,DOWN,PDIF +S 5400,6600,5400,9100,600,*,UP,PDIF +S 6000,6400,6000,9300,200,1c,UP,PTRANS +S 7200,6400,7200,9300,200,1d,UP,PTRANS +S 6600,6600,6600,9100,600,*,DOWN,PDIF +S 4200,3900,4200,5800,200,*,UP,POLY +S 6600,3900,6600,4900,200,*,UP,POLY +S 5000,2900,5000,5100,400,*,DOWN,ALU1 +S 7200,4800,7200,6400,200,*,DOWN,POLY +S 4800,4900,4800,6400,200,*,DOWN,POLY +S 3600,5600,3600,6400,200,*,DOWN,POLY +S 1000,7000,1800,7000,600,*,RIGHT,ALU1 +S 1900,6900,1900,8100,600,*,DOWN,ALU1 +S 1200,6300,2400,6300,200,*,RIGHT,POLY +S 2400,6700,2400,9300,200,2z,UP,PTRANS +S 600,6900,600,9100,600,*,DOWN,PDIF +S 600,7900,600,9300,400,*,UP,ALU1 +S 7900,6600,7900,9100,600,*,DOWN,PDIF +S 4000,2000,4000,4000,400,*,UP,ALU1 +S 3000,4000,4000,4000,400,*,LEFT,ALU1 +S 3000,4000,3000,8000,400,*,DOWN,ALU1 +S 4000,2000,7200,2000,400,*,LEFT,ALU1 +S 3200,700,3200,3100,400,*,DOWN,ALU1 +S 2600,1300,2600,3900,200,3z,DOWN,NTRANS +S 2600,3900,2600,5000,200,*,UP,POLY +S 2400,4600,2400,6700,200,*,DOWN,POLY +S 2200,1500,2200,3700,400,*,UP,NDIF +S 2000,2900,2000,3500,600,*,DOWN,NDIF +S 2000,3000,2000,8000,400,z,UP,CALU1 +S 2000,2700,2000,8100,400,*,DOWN,ALU1 +S 1000,7000,1000,7000,400,z,LEFT,CALU1 +S 2400,9300,2400,9700,200,*,UP,POLY +S 3600,9300,3600,9700,200,*,UP,POLY +S 4800,9300,4800,9700,200,*,UP,POLY +S 6000,9300,6000,9700,200,*,UP,POLY +S 7200,9300,7200,9700,200,*,UP,POLY +S 6200,800,6200,3700,600,n3,UP,NDIF +S 5800,600,5800,3900,200,2c,DOWN,NTRANS +S 6600,600,6600,3900,200,2d,DOWN,NTRANS +S 4600,800,4600,3700,600,n1,UP,NDIF +S 4200,600,4200,3900,200,2a,DOWN,NTRANS +S 5000,600,5000,3900,200,2b,DOWN,NTRANS +S 7000,800,7000,3700,400,*,UP,NDIF +S 3300,800,3300,3700,800,*,UP,NDIF +S 4200,300,4200,600,200,*,DOWN,POLY +S 5000,300,5000,600,200,*,DOWN,POLY +S 5800,300,5800,600,200,*,DOWN,POLY +S 6600,300,6600,600,200,*,DOWN,POLY +S 2600,1000,2600,1300,200,*,DOWN,POLY +V 1000,700,CONT_BODY_P,* +V 6600,7800,CONT_DIF_P,zn +V 6600,7000,CONT_DIF_P,zn +V 7800,8000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,zn +V 7000,5000,CONT_POLY,* +V 7200,3000,CONT_DIF_N,zn +V 7200,2200,CONT_DIF_N,zn +V 5400,9000,CONT_DIF_P,* +V 3000,9000,CONT_DIF_P,* +V 600,9000,CONT_DIF_P,* +V 7800,9000,CONT_DIF_P,* +V 3000,4800,CONT_POLY,zn +V 1800,7000,CONT_DIF_P,* +V 1800,8000,CONT_DIF_P,* +V 4000,5800,CONT_POLY,* +V 6000,5800,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 600,8000,CONT_DIF_P,* +V 3200,2100,CONT_DIF_N,* +V 3200,3000,CONT_DIF_N,* +V 2000,3600,CONT_DIF_N,* +V 2000,2800,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/an4_x3.vbe b/pdks/symbolic/msxlib/cells/an4_x3.vbe new file mode 100644 index 000000000..f5dae13af --- /dev/null +++ b/pdks/symbolic/msxlib/cells/an4_x3.vbe @@ -0,0 +1,44 @@ +ENTITY an4_x3 IS +GENERIC ( + CONSTANT area : NATURAL := 9000; + CONSTANT cin_a : NATURAL := 8; + CONSTANT cin_b : NATURAL := 8; + CONSTANT cin_c : NATURAL := 7; + CONSTANT cin_d : NATURAL := 7; + CONSTANT rdown_a_z : NATURAL := 890; + CONSTANT rdown_b_z : NATURAL := 890; + CONSTANT rdown_c_z : NATURAL := 880; + CONSTANT rdown_d_z : NATURAL := 880; + CONSTANT rup_a_z : NATURAL := 1140; + CONSTANT rup_b_z : NATURAL := 1140; + CONSTANT rup_c_z : NATURAL := 1140; + CONSTANT rup_d_z : NATURAL := 1150; + CONSTANT tphh_a_z : NATURAL := 114; + CONSTANT tphh_b_z : NATURAL := 111; + CONSTANT tpll_d_z : NATURAL := 105; + CONSTANT tphh_c_z : NATURAL := 105; + CONSTANT tpll_c_z : NATURAL := 118; + CONSTANT tphh_d_z : NATURAL := 98; + CONSTANT tpll_b_z : NATURAL := 129; + CONSTANT tpll_a_z : NATURAL := 138; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an4_x3; + +ARCHITECTURE behaviour_data_flow OF an4_x3 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an4_x3" + SEVERITY WARNING; + z <= (((a and b) and c) and d) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/aoi21_x05.ap b/pdks/symbolic/msxlib/cells/aoi21_x05.ap new file mode 100644 index 000000000..0a9ddcc87 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi21_x05.ap @@ -0,0 +1,94 @@ +V ALLIANCE : 6 +H aoi21_x05,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 2000,7000,ref_ref,b_70 +R 3000,6000,ref_ref,a2_60 +R 3000,3000,ref_ref,a1_30 +R 2000,4000,ref_ref,z_40 +R 4000,4000,ref_ref,a1_40 +R 2000,3000,ref_ref,z_30 +R 1000,8000,ref_ref,z_80 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 2000,5000,ref_ref,b_50 +R 2000,6000,ref_ref,b_60 +R 3000,7000,ref_ref,b_70 +R 3000,5000,ref_ref,a2_50 +R 4000,6000,ref_ref,a2_60 +R 4000,5000,ref_ref,a1_50 +R 3000,4000,ref_ref,a1_40 +R 4000,7000,ref_ref,a2_70 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 3800,8300,3800,8700,200,*,DOWN,POLY +S 2600,8300,2600,8700,200,*,DOWN,POLY +S 1400,8300,1400,8700,200,*,DOWN,POLY +S 1900,4900,1900,5100,600,*,UP,ALU1 +S 2000,7100,3100,7100,400,*,RIGHT,ALU1 +S 2000,5000,2000,7000,400,b,DOWN,CALU1 +S 2000,4900,2000,7000,400,*,DOWN,ALU1 +S 4000,6000,4000,7000,400,a2,DOWN,CALU1 +S 4000,6000,4000,7100,400,*,UP,ALU1 +S 3000,6000,4000,6000,600,*,RIGHT,ALU1 +S 3000,4900,3000,6000,400,*,UP,ALU1 +S 3000,5000,3000,6000,400,a2,DOWN,CALU1 +S 1400,3300,1400,6300,200,*,DOWN,POLY +S 2600,3600,2600,6300,200,*,DOWN,POLY +S 3800,4000,3800,6300,200,*,UP,POLY +S 3400,4000,3800,4000,200,*,RIGHT,POLY +S 4000,700,4000,3100,400,*,UP,ALU1 +S 4000,2900,4000,3400,600,*,UP,NDIF +S 3000,2900,3000,4000,400,*,DOWN,ALU1 +S 3000,4000,4000,4000,600,*,RIGHT,ALU1 +S 4000,4000,4000,5100,400,*,UP,ALU1 +S 4000,4000,4000,5000,400,a1,UP,CALU1 +S 3000,3000,3000,4000,400,a1,DOWN,CALU1 +S 2200,2900,2200,3400,400,*,UP,NDIF +S 3000,2900,3000,3400,600,n1,UP,NDIF +S 3400,2700,3400,3600,200,4,UP,NTRANS +S 3400,2300,3400,2700,200,*,UP,POLY +S 2600,2700,2600,3600,200,5,UP,NTRANS +S 2600,2300,2600,2700,200,*,UP,POLY +S 1400,2700,1400,3300,200,6,UP,NTRANS +S 1400,2300,1400,2700,200,*,UP,POLY +S 800,700,800,3100,400,*,UP,ALU1 +S 2000,2900,2000,4000,400,*,DOWN,ALU1 +S 1000,4000,2000,4000,600,*,RIGHT,ALU1 +S 2000,3000,2000,4000,400,z,DOWN,CALU1 +S 1000,4000,1000,8000,400,z,DOWN,CALU1 +S 1000,4000,1000,6600,400,*,DOWN,ALU1 +S 0,5000,5000,5000,10000,aoi21_x05,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 3200,6500,3200,9100,600,*,UP,PDIF +S 1000,6500,1000,8100,400,*,UP,PDIF +S 3800,6300,3800,8300,200,1,DOWN,PTRANS +S 4200,6500,4200,8100,400,*,UP,PDIF +S 2600,6300,2600,8300,200,2,DOWN,PTRANS +S 2000,6500,2000,8100,1000,*,UP,PDIF +S 1400,6300,1400,8300,200,3,DOWN,PTRANS +S 1900,8000,4500,8000,400,*,RIGHT,ALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 2000,7000,3100,7000,400,*,RIGHT,ALU1 +S 3000,7000,3000,7000,400,b,LEFT,CALU1 +S 800,7100,800,8100,600,*,UP,PDIF +S 900,7100,900,8100,600,*,UP,ALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 4000,3000,CONT_DIF_N,* +V 2000,3000,CONT_DIF_N,* +V 800,3000,CONT_DIF_N,* +V 3000,5700,CONT_POLY,* +V 1800,5000,CONT_POLY,* +V 3200,9000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,n2 +V 4400,8000,CONT_DIF_P,n2 +V 800,8000,CONT_DIF_P,* +V 4000,5000,CONT_POLY,* +V 800,7200,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/aoi21_x05.vbe b/pdks/symbolic/msxlib/cells/aoi21_x05.vbe new file mode 100644 index 000000000..db5197213 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi21_x05.vbe @@ -0,0 +1,38 @@ +ENTITY aoi21_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_a2 : NATURAL := 4; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 4130; + CONSTANT rdown_a2_z : NATURAL := 4130; + CONSTANT rdown_b_z : NATURAL := 3810; + CONSTANT rup_a1_z : NATURAL := 5810; + CONSTANT rup_a2_z : NATURAL := 5830; + CONSTANT rup_b_z : NATURAL := 5310; + CONSTANT tphl_a1_z : NATURAL := 57; + CONSTANT tphl_a2_z : NATURAL := 58; + CONSTANT tphl_b_z : NATURAL := 45; + CONSTANT tplh_b_z : NATURAL := 48; + CONSTANT tplh_a2_z : NATURAL := 69; + CONSTANT tplh_a1_z : NATURAL := 76; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi21_x05; + +ARCHITECTURE behaviour_data_flow OF aoi21_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi21_x05" + SEVERITY WARNING; + z <= not (((a1 and a2) or b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/aoi21_x1.ap b/pdks/symbolic/msxlib/cells/aoi21_x1.ap new file mode 100644 index 000000000..d16aa4465 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi21_x1.ap @@ -0,0 +1,102 @@ +V ALLIANCE : 6 +H aoi21_x1,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 3000,3000,ref_ref,a1_30 +R 4000,4000,ref_ref,a1_40 +R 2000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 2000,5000,ref_ref,b_50 +R 2000,6000,ref_ref,b_60 +R 3000,5000,ref_ref,a2_50 +R 4000,6000,ref_ref,a2_60 +R 4000,3000,ref_ref,a1_30 +R 2000,2000,ref_ref,z_20 +R 1000,3000,ref_ref,z_30 +R 3000,2000,ref_ref,a1_20 +R 3000,4000,ref_ref,a2_40 +R 4000,5000,ref_ref,a2_50 +R 3000,6000,ref_ref,b_60 +R 2000,4000,ref_ref,b_40 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 4100,1900,4100,3200,600,*,UP,NDIF +S 3400,3800,3800,3800,200,*,RIGHT,POLY +S 1900,4800,1900,5000,600,*,UP,ALU1 +S 3400,1300,3400,1700,200,*,UP,POLY +S 3400,1700,3400,3400,200,4,UP,NTRANS +S 3000,1900,3000,3200,600,n1,UP,NDIF +S 2600,1300,2600,1700,200,*,UP,POLY +S 2600,3400,2600,5500,200,*,DOWN,POLY +S 2600,1700,2600,3400,200,5,UP,NTRANS +S 2200,1900,2200,3200,400,*,UP,NDIF +S 900,5700,900,7100,600,*,UP,ALU1 +S 800,5700,800,6500,600,*,UP,PDIF +S 2000,5700,2000,9200,600,*,UP,PDIF +S 3200,5700,3200,9200,600,*,UP,PDIF +S 4200,5700,4200,9200,400,*,UP,PDIF +S 3800,5500,3800,9400,200,1,DOWN,PTRANS +S 2600,5500,2600,9400,200,2,DOWN,PTRANS +S 1000,5700,1000,9200,400,*,UP,PDIF +S 1400,5500,1400,9400,200,3,DOWN,PTRANS +S 3800,9400,3800,9700,200,*,DOWN,POLY +S 2600,9400,2600,9700,200,*,DOWN,POLY +S 1400,9400,1400,9700,200,*,DOWN,POLY +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,5000,5000,5000,10000,aoi21_x1,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 4000,700,4000,2100,400,*,UP,ALU1 +S 3000,3000,4000,3000,600,*,RIGHT,ALU1 +S 1400,1700,1400,2700,200,6,UP,NTRANS +S 1400,1300,1400,1700,200,*,UP,POLY +S 2000,1900,2000,2500,1000,*,UP,NDIF +S 1400,2700,1400,5500,200,*,DOWN,POLY +S 800,1900,800,2500,600,*,UP,NDIF +S 700,1900,700,2500,600,*,UP,NDIF +S 800,700,800,2100,400,*,UP,ALU1 +S 1000,3000,2000,3000,400,*,RIGHT,ALU1 +S 1000,2900,2000,2900,400,*,RIGHT,ALU1 +S 2000,2000,2000,3000,600,*,DOWN,ALU1 +S 2000,2000,2000,3000,400,z,DOWN,CALU1 +S 1000,2900,1000,7000,400,*,DOWN,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 2000,4000,2000,6000,400,b,DOWN,CALU1 +S 3000,2000,3000,3000,400,a1,DOWN,CALU1 +S 3000,1900,3000,3100,400,*,DOWN,ALU1 +S 3800,3800,3800,5500,200,*,UP,POLY +S 4000,3000,4000,4100,400,*,UP,ALU1 +S 4000,3000,4000,4000,400,a1,UP,CALU1 +S 3000,5000,4000,5000,600,*,RIGHT,ALU1 +S 4000,5000,4000,6000,400,a2,DOWN,CALU1 +S 3000,3900,3000,5100,400,*,UP,ALU1 +S 3000,4000,3000,5000,400,a2,DOWN,CALU1 +S 4000,4900,4000,6100,400,*,UP,ALU1 +S 2000,6100,3100,6100,400,*,RIGHT,ALU1 +S 2000,6000,3100,6000,400,*,RIGHT,ALU1 +S 3000,6000,3000,6000,400,b,LEFT,CALU1 +S 2000,3900,2000,6100,400,*,DOWN,ALU1 +S 3200,7900,3200,9300,400,*,DOWN,ALU1 +S 4400,7000,4400,8100,400,*,DOWN,ALU1 +S 2000,7000,2000,8100,400,*,DOWN,ALU1 +S 2000,7000,4400,7000,400,*,RIGHT,ALU1 +S 4400,7300,4400,7900,600,*,UP,PDIF +V 2100,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 1800,4900,CONT_POLY,* +V 4000,2000,CONT_DIF_N,* +V 3000,4900,CONT_POLY,* +V 800,6600,CONT_DIF_P,* +V 800,5800,CONT_DIF_P,* +V 3200,9000,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 3200,8000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,n2 +V 4400,8000,CONT_DIF_P,n2 +V 2000,7200,CONT_DIF_P,n2 +V 4400,7200,CONT_DIF_P,n2 +EOF diff --git a/pdks/symbolic/msxlib/cells/aoi21_x1.vbe b/pdks/symbolic/msxlib/cells/aoi21_x1.vbe new file mode 100644 index 000000000..b53540f16 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi21_x1.vbe @@ -0,0 +1,38 @@ +ENTITY aoi21_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a1 : NATURAL := 6; + CONSTANT cin_a2 : NATURAL := 6; + CONSTANT cin_b : NATURAL := 6; + CONSTANT rdown_a1_z : NATURAL := 2190; + CONSTANT rdown_a2_z : NATURAL := 2180; + CONSTANT rdown_b_z : NATURAL := 2280; + CONSTANT rup_a1_z : NATURAL := 2980; + CONSTANT rup_a2_z : NATURAL := 2990; + CONSTANT rup_b_z : NATURAL := 2720; + CONSTANT tphl_a1_z : NATURAL := 55; + CONSTANT tphl_a2_z : NATURAL := 56; + CONSTANT tphl_b_z : NATURAL := 45; + CONSTANT tplh_b_z : NATURAL := 45; + CONSTANT tplh_a2_z : NATURAL := 64; + CONSTANT tplh_a1_z : NATURAL := 71; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi21_x1; + +ARCHITECTURE behaviour_data_flow OF aoi21_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi21_x1" + SEVERITY WARNING; + z <= not (((a1 and a2) or b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/aoi21_x2.ap b/pdks/symbolic/msxlib/cells/aoi21_x2.ap new file mode 100644 index 000000000..c4a05d00f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi21_x2.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H aoi21_x2,P, 8/ 8/2014,100 +A 0,0,9000,10000 +R 1000,3000,ref_ref,z_30 +R 4000,4000,ref_ref,b_40 +R 8000,4000,ref_ref,a1_40 +R 8000,6000,ref_ref,a1_60 +R 3000,5000,ref_ref,b_50 +R 3000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 3000,3000,ref_ref,z_30 +R 2000,3000,ref_ref,z_30 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 4000,3000,ref_ref,z_30 +R 2000,5000,ref_ref,a1_50 +R 8000,5000,ref_ref,a1_50 +R 7000,6000,ref_ref,a1_60 +R 6000,6000,ref_ref,a1_60 +R 5000,6000,ref_ref,a1_60 +R 4000,6000,ref_ref,a1_60 +R 3000,6000,ref_ref,a1_60 +R 6000,5000,ref_ref,a2_50 +R 5000,5000,ref_ref,a2_50 +R 1000,7000,ref_ref,z_70 +R 2000,6000,ref_ref,a1_60 +R 4000,5000,ref_ref,b_50 +R 6000,4000,ref_ref,a2_40 +R 6000,3000,ref_ref,a2_30 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 4900,5000,6000,5000,600,*,RIGHT,ALU1 +S 3800,3900,3800,5100,200,*,UP,POLY +S 3100,1900,3100,3700,600,*,UP,NDIF +S 3200,700,3200,2100,400,*,UP,ALU1 +S 3800,1700,3800,3900,200,09,UP,NTRANS +S 3800,1300,3800,1700,200,*,DOWN,POLY +S 4400,1900,4400,3700,1000,*,UP,NDIF +S 4600,800,4600,3700,400,*,UP,NDIF +S 5800,4300,7600,4300,200,*,LEFT,POLY +S 5000,3900,5000,4800,200,*,UP,POLY +S 5000,300,5000,600,200,*,DOWN,POLY +S 5000,600,5000,3900,200,08,UP,NTRANS +S 5800,300,5800,600,200,*,DOWN,POLY +S 5800,600,5800,3900,200,07,UP,NTRANS +S 6500,800,6500,3700,600,*,UP,NDIF +S 6400,700,6400,2000,400,*,UP,ALU1 +S 5000,5000,5000,5000,400,a2,LEFT,CALU1 +S 3000,5000,3000,5000,400,b,LEFT,CALU1 +S 7000,6000,7000,6000,400,a1,LEFT,CALU1 +S 6000,6000,6000,6000,400,a1,LEFT,CALU1 +S 5000,6000,5000,6000,400,a1,LEFT,CALU1 +S 4000,6000,4000,6000,400,a1,LEFT,CALU1 +S 3000,6000,3000,6000,400,a1,LEFT,CALU1 +S 4000,3000,4000,3000,400,z,LEFT,CALU1 +S 3000,3000,3000,3000,400,z,LEFT,CALU1 +S 2000,3000,2000,3000,400,z,LEFT,CALU1 +S 3000,7000,3000,7000,400,z,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,9000,5000,10000,aoi21_x2,LEFT,TALU8 +S 0,2200,9000,2200,5200,*,LEFT,PWELL +S 0,7600,9000,7600,5600,*,LEFT,NWELL +S 2000,6000,8000,6000,400,*,RIGHT,ALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 1600,5500,1600,9400,200,02,DOWN,PTRANS +S 900,5700,900,9200,600,*,DOWN,PDIF +S 2800,5500,2800,9400,200,06,DOWN,PTRANS +S 2200,5700,2200,9200,1000,*,UP,PDIF +S 4000,5500,4000,9400,200,05,DOWN,PTRANS +S 3400,5700,3400,9200,1000,*,UP,PDIF +S 4600,5700,4600,9200,1000,*,UP,PDIF +S 5200,5500,5200,9400,200,04,DOWN,PTRANS +S 5800,5700,5800,9200,1000,*,UP,PDIF +S 6400,5500,6400,9400,200,03,DOWN,PTRANS +S 7000,5700,7000,9200,1000,*,UP,PDIF +S 7600,5500,7600,9400,200,01,DOWN,PTRANS +S 8300,5700,8300,9200,600,*,DOWN,PDIF +S 1000,7000,3500,7000,400,*,RIGHT,ALU1 +S 1000,7100,3500,7100,400,*,RIGHT,ALU1 +S 8000,4000,8000,6000,400,a1,DOWN,CALU1 +S 8000,4000,8000,6000,600,*,UP,ALU1 +S 2000,5000,2000,6000,400,a1,DOWN,CALU1 +S 2000,4900,2000,6000,600,*,UP,ALU1 +S 1600,5000,1600,5500,200,*,DOWN,POLY +S 2800,5100,4000,5100,200,*,LEFT,POLY +S 5200,5100,6400,5100,200,*,RIGHT,POLY +S 1600,9400,1600,9700,200,*,DOWN,POLY +S 2800,9400,2800,9700,200,*,DOWN,POLY +S 4000,9400,4000,9700,200,*,DOWN,POLY +S 5200,9400,5200,9700,200,*,DOWN,POLY +S 6400,9400,6400,9700,200,*,DOWN,POLY +S 7600,9400,7600,9700,200,*,DOWN,POLY +S 7600,4300,7600,5500,200,*,DOWN,POLY +S 4000,3900,4000,5000,400,*,DOWN,ALU1 +S 4000,4000,4000,5000,400,b,DOWN,CALU1 +S 6000,2900,6000,5000,400,*,DOWN,ALU1 +S 6000,3000,6000,5000,400,a2,DOWN,CALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 1000,3000,1000,7000,400,*,DOWN,ALU1 +S 3000,5000,4000,5000,600,*,RIGHT,ALU1 +S 1000,3000,4400,3000,400,*,RIGHT,ALU1 +S 1000,2900,4400,2900,400,*,RIGHT,ALU1 +S 4400,1900,4400,3000,400,*,DOWN,ALU1 +S 2100,8000,4600,8000,400,*,RIGHT,ALU1 +S 4600,7000,7000,7000,400,*,RIGHT,ALU1 +S 4600,7000,4600,8000,400,*,UP,ALU1 +S 7000,7000,7000,8000,400,*,UP,ALU1 +S 5800,7900,5800,9300,400,*,DOWN,ALU1 +S 1000,7900,1000,9300,400,*,UP,ALU1 +S 8200,6900,8200,9300,400,*,UP,ALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 3200,2000,CONT_DIF_N,* +V 5000,4900,CONT_POLY,* +V 6400,900,CONT_DIF_N,* +V 6400,1900,CONT_DIF_N,* +V 3400,7000,CONT_DIF_P,* +V 2200,8000,CONT_DIF_P,n2 +V 1000,8000,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,9000,CONT_DIF_P,* +V 5800,9000,CONT_DIF_P,* +V 1000,9000,CONT_DIF_P,* +V 2000,4900,CONT_POLY,* +V 8000,4500,CONT_POLY,* +V 3800,4900,CONT_POLY,* +V 8200,7000,CONT_DIF_P,* +V 4400,2000,CONT_DIF_N,* +V 4400,2800,CONT_DIF_N,* +V 4600,7900,CONT_DIF_P,n2 +V 4600,7100,CONT_DIF_P,n2 +V 7000,7100,CONT_DIF_P,n2 +V 7000,7900,CONT_DIF_P,n2 +V 5800,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/aoi21_x2.vbe b/pdks/symbolic/msxlib/cells/aoi21_x2.vbe new file mode 100644 index 000000000..705fdb4ac --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi21_x2.vbe @@ -0,0 +1,38 @@ +ENTITY aoi21_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 9000; + CONSTANT cin_a1 : NATURAL := 13; + CONSTANT cin_a2 : NATURAL := 12; + CONSTANT cin_b : NATURAL := 10; + CONSTANT rdown_a1_z : NATURAL := 1120; + CONSTANT rdown_a2_z : NATURAL := 1120; + CONSTANT rdown_b_z : NATURAL := 1040; + CONSTANT rup_a1_z : NATURAL := 1490; + CONSTANT rup_a2_z : NATURAL := 1490; + CONSTANT rup_b_z : NATURAL := 1360; + CONSTANT tphl_a1_z : NATURAL := 53; + CONSTANT tphl_a2_z : NATURAL := 54; + CONSTANT tphl_b_z : NATURAL := 41; + CONSTANT tplh_b_z : NATURAL := 43; + CONSTANT tplh_a2_z : NATURAL := 60; + CONSTANT tplh_a1_z : NATURAL := 68; + CONSTANT transistors : NATURAL := 9 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi21_x2; + +ARCHITECTURE behaviour_data_flow OF aoi21_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi21_x2" + SEVERITY WARNING; + z <= not (((a1 and a2) or b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/aoi22_x05.ap b/pdks/symbolic/msxlib/cells/aoi22_x05.ap new file mode 100644 index 000000000..dab8c9b6e --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi22_x05.ap @@ -0,0 +1,126 @@ +V ALLIANCE : 6 +H aoi22_x05,P, 8/ 8/2014,100 +A 0,0,6000,10000 +R 2000,7000,ref_ref,z_70 +R 2000,2000,ref_ref,z_20 +R 1000,3000,ref_ref,z_30 +R 3000,2000,ref_ref,z_20 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 2000,5000,ref_ref,b1_50 +R 2000,4000,ref_ref,b1_40 +R 3000,3000,ref_ref,b1_30 +R 3000,6000,ref_ref,b2_60 +R 2000,6000,ref_ref,b2_60 +R 3000,5000,ref_ref,b2_50 +R 3000,4000,ref_ref,b2_40 +R 4000,6000,ref_ref,a2_60 +R 4000,5000,ref_ref,a2_50 +R 4000,4000,ref_ref,a2_40 +R 5000,4000,ref_ref,a1_40 +R 4000,3000,ref_ref,a1_30 +R 1000,7000,ref_ref,z_70 +R 5000,6000,ref_ref,a2_60 +R 5000,3000,ref_ref,a1_30 +R 2000,3000,ref_ref,b1_30 +R 1000,2000,ref_ref,z_20 +R 4000,2000,ref_ref,a1_20 +S 4100,700,4900,700,600,*,RIGHT,PTIE +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 3000,7000,5400,7000,400,*,LEFT,ALU1 +S 5400,7000,5400,8100,400,*,DOWN,ALU1 +S 5400,7300,5400,7900,600,*,UP,PDIF +S 2000,3000,2000,5100,400,*,UP,ALU1 +S 5000,6000,5000,6000,400,a2,LEFT,CALU1 +S 2000,6000,2000,6000,400,b2,LEFT,CALU1 +S 3000,3000,3000,3000,400,b1,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 3600,5600,3600,6300,200,*,DOWN,POLY +S 2400,4600,2400,6300,200,*,DOWN,POLY +S 4600,2600,4600,3400,200,*,UP,POLY +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 2600,1700,2600,2600,200,7,UP,NTRANS +S 3800,1700,3800,2600,200,8,UP,NTRANS +S 4600,1700,4600,2600,200,6,UP,NTRANS +S 2200,1900,2200,2400,600,n2,UP,NDIF +S 5300,1900,5300,2400,600,*,UP,NDIF +S 4200,1900,4200,2400,600,n1,UP,NDIF +S 3200,1900,3200,2400,1000,*,UP,NDIF +S 1200,900,1200,2400,600,*,UP,NDIF +S 1800,1700,1800,2600,200,5,UP,NTRANS +S 2000,4900,2000,5100,400,*,UP,ALU1 +S 2000,3000,3100,3000,400,*,LEFT,ALU1 +S 1800,1300,1800,1700,200,*,UP,POLY +S 2600,1300,2600,1700,200,*,UP,POLY +S 3800,1300,3800,1700,200,*,UP,POLY +S 4600,1300,4600,1700,200,*,UP,POLY +S 0,5000,6000,5000,10000,aoi22_x05,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 1800,6500,1800,8100,1000,*,UP,PDIF +S 2400,6300,2400,8300,200,3,DOWN,PTRANS +S 1200,6300,1200,8300,200,1,DOWN,PTRANS +S 3600,6300,3600,8300,200,4,DOWN,PTRANS +S 4800,6300,4800,8300,200,2,DOWN,PTRANS +S 800,6500,800,8100,400,*,UP,PDIF +S 5200,6500,5200,8100,400,*,UP,PDIF +S 3000,6500,3000,8100,1000,*,UP,PDIF +S 1200,8300,1200,8700,200,*,DOWN,POLY +S 2400,8300,2400,8700,200,*,DOWN,POLY +S 3600,8300,3600,8700,200,*,DOWN,POLY +S 4800,8300,4800,8700,200,*,DOWN,POLY +S 3000,4000,3000,6000,400,b2,DOWN,CALU1 +S 3000,3900,3000,6000,400,*,DOWN,ALU1 +S 1900,6000,3000,6000,400,*,RIGHT,ALU1 +S 1900,6100,3000,6100,400,*,RIGHT,ALU1 +S 1000,7000,2100,7000,400,*,RIGHT,ALU1 +S 1000,7100,2100,7100,400,*,RIGHT,ALU1 +S 4000,6000,5100,6000,400,*,RIGHT,ALU1 +S 4000,6100,5100,6100,400,*,RIGHT,ALU1 +S 4000,3900,4000,6000,400,*,UP,ALU1 +S 4000,4000,4000,6000,400,a2,DOWN,CALU1 +S 500,8000,3000,8000,400,*,RIGHT,ALU1 +S 3000,7000,3000,8000,600,*,UP,ALU1 +S 4200,7900,4200,9300,400,*,UP,ALU1 +S 4200,6500,4200,8100,600,*,UP,PDIF +S 2000,3000,2000,5000,400,b1,UP,CALU1 +S 2000,2900,3100,2900,400,*,LEFT,ALU1 +S 5200,700,5200,2100,400,*,UP,ALU1 +S 3800,2600,3800,5300,200,*,UP,POLY +S 4800,3600,4800,6300,200,*,DOWN,POLY +S 1800,2600,1800,3400,200,*,UP,POLY +S 1200,3700,1500,3700,200,*,RIGHT,POLY +S 1200,3700,1200,6300,200,*,DOWN,POLY +S 2600,2600,2600,4700,200,*,DOWN,POLY +S 1800,3500,2000,3500,600,*,RIGHT,ALU1 +S 4000,2000,4000,3000,400,a1,DOWN,CALU1 +S 4000,1900,4000,3100,400,*,DOWN,ALU1 +S 4000,3000,5000,3000,600,*,RIGHT,ALU1 +S 1000,1900,1000,7000,400,*,DOWN,ALU1 +S 1000,2000,3200,2000,600,*,RIGHT,ALU1 +S 5000,3000,5000,4100,400,*,UP,ALU1 +S 5000,3000,5000,4000,400,a1,UP,CALU1 +V 5000,700,CONT_BODY_P,* +V 4000,700,CONT_BODY_P,* +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 5400,7200,CONT_DIF_P,n3 +V 5400,8000,CONT_DIF_P,n3 +V 1800,7000,CONT_DIF_P,* +V 5200,2000,CONT_DIF_N,* +V 1200,1000,CONT_DIF_N,* +V 3200,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,n3 +V 600,8000,CONT_DIF_P,n3 +V 3000,7000,CONT_DIF_P,n3 +V 4200,8000,CONT_DIF_P,* +V 4000,5500,CONT_POLY,* +V 5000,3500,CONT_POLY,* +V 1800,3500,CONT_POLY,* +V 3000,4500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/aoi22_x05.vbe b/pdks/symbolic/msxlib/cells/aoi22_x05.vbe new file mode 100644 index 000000000..995b18841 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi22_x05.vbe @@ -0,0 +1,44 @@ +ENTITY aoi22_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_b1 : NATURAL := 4; + CONSTANT cin_b2 : NATURAL := 4; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_a2 : NATURAL := 4; + CONSTANT rdown_b1_z : NATURAL := 4100; + CONSTANT rdown_b2_z : NATURAL := 4090; + CONSTANT rdown_a1_z : NATURAL := 4140; + CONSTANT rdown_a2_z : NATURAL := 4140; + CONSTANT rup_b1_z : NATURAL := 5310; + CONSTANT rup_b2_z : NATURAL := 5310; + CONSTANT rup_a1_z : NATURAL := 5370; + CONSTANT rup_a2_z : NATURAL := 5390; + CONSTANT tphl_b1_z : NATURAL := 49; + CONSTANT tphl_b2_z : NATURAL := 49; + CONSTANT tplh_a2_z : NATURAL := 83; + CONSTANT tphl_a1_z : NATURAL := 70; + CONSTANT tplh_b2_z : NATURAL := 55; + CONSTANT tplh_a1_z : NATURAL := 90; + CONSTANT tplh_b1_z : NATURAL := 63; + CONSTANT tphl_a2_z : NATURAL := 71; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi22_x05; + +ARCHITECTURE behaviour_data_flow OF aoi22_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi22_x05" + SEVERITY WARNING; + z <= not (((b1 and b2) or (a1 and a2))) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/aoi22_x1.ap b/pdks/symbolic/msxlib/cells/aoi22_x1.ap new file mode 100644 index 000000000..14246d406 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi22_x1.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H aoi22_x1,P, 8/ 8/2014,100 +A 0,0,6000,10000 +R 3000,6000,ref_ref,b2_60 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +R 3000,2000,ref_ref,z_20 +R 1000,3000,ref_ref,z_30 +R 2000,2000,ref_ref,z_20 +R 2000,7000,ref_ref,z_70 +R 2000,5000,ref_ref,b1_50 +R 2000,4000,ref_ref,b1_40 +R 3000,3000,ref_ref,b1_30 +R 2000,6000,ref_ref,b2_60 +R 3000,5000,ref_ref,b2_50 +R 3000,4000,ref_ref,b2_40 +R 4000,6000,ref_ref,a2_60 +R 4000,5000,ref_ref,a2_50 +R 5000,4000,ref_ref,a1_40 +R 5000,5000,ref_ref,a1_50 +R 5000,3000,ref_ref,a1_30 +R 4000,3000,ref_ref,a1_30 +R 5000,6000,ref_ref,a2_60 +R 4000,4000,ref_ref,a2_40 +R 2000,3000,ref_ref,b1_30 +R 1000,7000,ref_ref,z_70 +R 1000,2000,ref_ref,z_20 +S 4100,700,4900,700,600,*,RIGHT,PTIE +S 3600,5000,3600,5500,200,*,DOWN,POLY +S 4600,3400,4600,3900,200,*,UP,POLY +S 3000,7000,5400,7000,400,*,RIGHT,ALU1 +S 5400,7000,5400,8100,400,*,DOWN,ALU1 +S 5400,7300,5400,7900,600,*,DOWN,PDIF +S 5000,6000,5000,6000,400,a2,LEFT,CALU1 +S 4000,3000,4000,3000,400,a1,LEFT,CALU1 +S 3000,3000,3000,3000,400,b1,LEFT,CALU1 +S 2000,6000,2000,6000,400,b2,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 2600,1700,2600,3400,200,7,UP,NTRANS +S 3800,1700,3800,3400,200,8,UP,NTRANS +S 4600,1700,4600,3400,200,6,UP,NTRANS +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,5000,6000,5000,10000,aoi22_x1,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 4600,1300,4600,1700,200,*,UP,POLY +S 3800,1300,3800,1700,200,*,UP,POLY +S 2200,1900,2200,3200,600,n2,UP,NDIF +S 1800,1700,1800,3400,200,5,UP,NTRANS +S 4200,1900,4200,3200,600,n1,UP,NDIF +S 3200,1900,3200,3200,1000,*,UP,NDIF +S 5300,1900,5300,3200,600,*,UP,NDIF +S 2600,1300,2600,1700,200,*,UP,POLY +S 1800,1300,1800,1700,200,*,UP,POLY +S 1200,900,1200,3200,600,*,UP,NDIF +S 2000,3000,3100,3000,400,*,LEFT,ALU1 +S 2000,4900,2000,5100,400,*,UP,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1000,2000,1000,7000,400,*,DOWN,ALU1 +S 1800,5700,1800,9200,1000,*,UP,PDIF +S 1200,5500,1200,9400,200,1,DOWN,PTRANS +S 2400,5500,2400,9400,200,3,DOWN,PTRANS +S 800,5700,800,9200,400,*,UP,PDIF +S 3600,5500,3600,9400,200,4,DOWN,PTRANS +S 4800,5500,4800,9400,200,2,DOWN,PTRANS +S 4200,5700,4200,9200,1000,*,UP,PDIF +S 3000,5700,3000,9200,1000,*,UP,PDIF +S 5200,5700,5200,9200,400,*,UP,PDIF +S 3900,2900,5000,2900,400,*,RIGHT,ALU1 +S 3900,3000,5000,3000,400,*,RIGHT,ALU1 +S 5000,3000,5000,5000,400,a1,UP,CALU1 +S 5000,3000,5000,5100,400,*,UP,ALU1 +S 4000,4000,4000,6000,400,a2,DOWN,CALU1 +S 4000,3900,4000,6000,400,*,UP,ALU1 +S 4000,6000,5100,6000,400,*,RIGHT,ALU1 +S 4000,6100,5100,6100,400,*,RIGHT,ALU1 +S 3000,4000,3000,6000,400,b2,DOWN,CALU1 +S 3000,3900,3000,6000,400,*,DOWN,ALU1 +S 1900,6000,3000,6000,400,*,RIGHT,ALU1 +S 1900,6100,3000,6100,400,*,RIGHT,ALU1 +S 500,8000,3000,8000,400,*,RIGHT,ALU1 +S 3000,7000,3000,8000,600,*,DOWN,ALU1 +S 4200,7900,4200,9300,400,*,DOWN,ALU1 +S 2000,3000,2000,5000,400,b1,UP,CALU1 +S 2000,3000,2000,3900,400,*,UP,ALU1 +S 2000,2900,3100,2900,400,*,LEFT,ALU1 +S 1000,2000,3300,2000,400,*,RIGHT,ALU1 +S 1000,7000,2100,7000,400,*,RIGHT,ALU1 +S 1800,4000,2000,4000,600,*,RIGHT,ALU1 +S 1200,4200,1500,4200,200,*,RIGHT,POLY +S 1200,4200,1200,5500,200,*,DOWN,POLY +S 3800,3400,3800,4700,200,*,UP,POLY +S 4800,3800,4800,5500,200,*,DOWN,POLY +S 5200,700,5200,2100,400,*,UP,ALU1 +S 1000,7100,2100,7100,400,*,RIGHT,ALU1 +S 1000,1900,3300,1900,400,*,RIGHT,ALU1 +S 2600,3400,2600,5100,200,*,DOWN,POLY +S 2400,5000,2400,5500,200,*,DOWN,POLY +S 1200,9400,1200,9700,200,*,DOWN,POLY +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 3600,9400,3600,9700,200,*,DOWN,POLY +S 4800,9400,4800,9700,200,*,DOWN,POLY +V 5000,700,CONT_BODY_P,* +V 4000,700,CONT_BODY_P,* +V 5400,7200,CONT_DIF_P,n3 +V 5400,8000,CONT_DIF_P,n3 +V 3200,2000,CONT_DIF_N,* +V 1200,1000,CONT_DIF_N,* +V 5200,2000,CONT_DIF_N,* +V 600,8000,CONT_DIF_P,n3 +V 3000,8000,CONT_DIF_P,n3 +V 1800,7000,CONT_DIF_P,* +V 4200,9000,CONT_DIF_P,* +V 4000,4900,CONT_POLY,* +V 3000,7000,CONT_DIF_P,n3 +V 4200,8000,CONT_DIF_P,* +V 1800,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/aoi22_x1.vbe b/pdks/symbolic/msxlib/cells/aoi22_x1.vbe new file mode 100644 index 000000000..c6b647e30 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY aoi22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_b1 : NATURAL := 6; + CONSTANT cin_b2 : NATURAL := 6; + CONSTANT cin_a1 : NATURAL := 6; + CONSTANT cin_a2 : NATURAL := 6; + CONSTANT rdown_b1_z : NATURAL := 2170; + CONSTANT rdown_b2_z : NATURAL := 2160; + CONSTANT rdown_a1_z : NATURAL := 2190; + CONSTANT rdown_a2_z : NATURAL := 2190; + CONSTANT rup_b1_z : NATURAL := 2720; + CONSTANT rup_b2_z : NATURAL := 2720; + CONSTANT rup_a1_z : NATURAL := 2750; + CONSTANT rup_a2_z : NATURAL := 2760; + CONSTANT tphl_b1_z : NATURAL := 46; + CONSTANT tphl_b2_z : NATURAL := 47; + CONSTANT tplh_a2_z : NATURAL := 77; + CONSTANT tphl_a1_z : NATURAL := 67; + CONSTANT tplh_b2_z : NATURAL := 51; + CONSTANT tplh_a1_z : NATURAL := 83; + CONSTANT tplh_b1_z : NATURAL := 58; + CONSTANT tphl_a2_z : NATURAL := 68; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi22_x1; + +ARCHITECTURE behaviour_data_flow OF aoi22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi22_x1" + SEVERITY WARNING; + z <= not (((b1 and b2) or (a1 and a2))) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/aoi22_x2.ap b/pdks/symbolic/msxlib/cells/aoi22_x2.ap new file mode 100644 index 000000000..46774977d --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi22_x2.ap @@ -0,0 +1,168 @@ +V ALLIANCE : 6 +H aoi22_x2,P, 8/ 8/2014,100 +A 0,0,11000,10000 +R 1000,2000,ref_ref,z_20 +R 9000,5000,ref_ref,a2_50 +R 9000,4000,ref_ref,a2_40 +R 7000,5000,ref_ref,a1_50 +R 4000,5000,ref_ref,b1_50 +R 5000,6000,ref_ref,b2_60 +R 2000,6000,ref_ref,b2_60 +R 1000,7000,ref_ref,z_70 +R 3000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 4000,6000,ref_ref,b2_60 +R 2000,2000,ref_ref,z_20 +R 1000,3000,ref_ref,z_30 +R 3000,2000,ref_ref,z_20 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 6000,5000,ref_ref,a2_50 +R 10000,5000,ref_ref,a2_50 +R 7000,6000,ref_ref,a2_60 +R 8000,6000,ref_ref,a2_60 +R 9000,6000,ref_ref,a2_60 +R 2000,5000,ref_ref,b2_50 +R 5000,5000,ref_ref,b2_50 +R 3000,6000,ref_ref,b2_60 +R 2000,4000,ref_ref,b2_40 +R 4000,7000,ref_ref,z_70 +R 4000,2000,ref_ref,z_20 +R 5000,2000,ref_ref,z_20 +R 4000,4000,ref_ref,b1_40 +R 4000,3000,ref_ref,b1_30 +R 3000,5000,ref_ref,b1_50 +R 7000,4000,ref_ref,a1_40 +R 7000,3000,ref_ref,a1_30 +R 8000,5000,ref_ref,a1_50 +R 6000,6000,ref_ref,a2_60 +S 9100,700,9900,700,600,*,RIGHT,PTIE +S 10200,5800,10200,7000,400,*,UP,ALU1 +S 10200,6000,10200,6600,600,*,DOWN,PDIF +S 5400,7000,10200,7000,400,*,RIGHT,ALU1 +S 6800,3900,6800,5200,200,*,UP,POLY +S 6000,3900,6000,4700,200,*,UP,POLY +S 4000,3900,4000,4700,200,*,UP,POLY +S 4800,3900,4800,4700,200,*,UP,POLY +S 1200,4600,1200,5600,200,*,DOWN,POLY +S 9600,9300,9600,9700,200,*,DOWN,POLY +S 8400,9300,8400,9700,200,*,DOWN,POLY +S 7200,9300,7200,9700,200,*,DOWN,POLY +S 6000,9300,6000,9700,200,*,DOWN,POLY +S 4800,9300,4800,9700,200,*,DOWN,POLY +S 3600,9300,3600,9700,200,*,DOWN,POLY +S 2400,9300,2400,9700,200,*,DOWN,POLY +S 1200,9300,1200,9700,200,*,DOWN,POLY +S 7400,700,7400,2100,400,*,DOWN,ALU1 +S 5400,1900,5400,3100,400,*,UP,ALU1 +S 1000,1900,5400,1900,400,*,RIGHT,ALU1 +S 9000,5000,10100,5000,400,*,RIGHT,ALU1 +S 6000,6000,9000,6000,400,*,RIGHT,ALU1 +S 9000,4000,9000,6000,600,*,UP,ALU1 +S 9000,4000,9000,6000,400,a2,UP,CALU1 +S 7000,3000,7000,5000,400,a1,DOWN,CALU1 +S 7000,2900,7000,5000,400,*,DOWN,ALU1 +S 7000,5100,8100,5100,400,*,RIGHT,ALU1 +S 1000,2000,5400,2000,400,*,RIGHT,ALU1 +S 2000,4000,2000,6000,600,*,DOWN,ALU1 +S 2900,5100,4000,5100,400,*,RIGHT,ALU1 +S 4000,2900,4000,5000,400,*,DOWN,ALU1 +S 4000,3000,4000,5000,400,b1,UP,CALU1 +S 2000,4000,2000,6000,400,b2,UP,CALU1 +S 6000,5000,6000,6000,600,*,UP,ALU1 +S 5000,5000,5000,6000,600,*,DOWN,ALU1 +S 5000,5000,5000,6000,400,b2,UP,CALU1 +S 6600,7900,6600,9300,400,*,UP,ALU1 +S 5400,7000,5400,8000,600,*,UP,ALU1 +S 7800,7000,7800,8100,400,*,DOWN,ALU1 +S 500,8000,5400,8000,400,*,RIGHT,ALU1 +S 6000,5000,6000,6000,400,a2,UP,CALU1 +S 1000,7000,4300,7000,400,*,RIGHT,ALU1 +S 1000,7100,4300,7100,400,*,RIGHT,ALU1 +S 9000,7900,9000,9300,400,*,UP,ALU1 +S 4800,5600,4800,9300,200,4b,DOWN,PTRANS +S 1200,5600,1200,9300,200,4a,DOWN,PTRANS +S 3600,5600,3600,9300,200,3b,DOWN,PTRANS +S 2400,5600,2400,9300,200,3a,DOWN,PTRANS +S 6000,5600,6000,9300,200,2a,DOWN,PTRANS +S 7200,5600,7200,9300,200,1a,DOWN,PTRANS +S 8400,5600,8400,9300,200,1b,DOWN,PTRANS +S 9600,5600,9600,9300,200,2b,DOWN,PTRANS +S 4000,300,4000,600,200,*,UP,POLY +S 4800,300,4800,600,200,*,UP,POLY +S 6000,300,6000,600,200,*,UP,POLY +S 6800,300,6800,600,200,*,UP,POLY +S 7500,800,7500,3700,600,*,UP,NDIF +S 5400,800,5400,3700,1000,*,UP,NDIF +S 6000,600,6000,3900,200,6,UP,NTRANS +S 6800,600,6800,3900,200,5,UP,NTRANS +S 6400,800,6400,3700,600,n1,UP,NDIF +S 3300,800,3300,3700,600,*,UP,NDIF +S 4000,600,4000,3900,200,7,UP,NTRANS +S 4800,600,4800,3900,200,8,UP,NTRANS +S 4400,800,4400,3600,600,n2,UP,NDIF +S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,11000,5000,10000,aoi22_x2,LEFT,TALU8 +S 0,2200,11000,2200,5200,*,LEFT,PWELL +S 0,7600,11000,7600,5600,*,LEFT,NWELL +S 0,600,11000,600,1200,vss,RIGHT,CALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1000,2000,1000,7000,400,*,DOWN,ALU1 +S 4200,5800,4200,9100,1000,*,UP,PDIF +S 3000,5800,3000,9100,1000,*,UP,PDIF +S 1800,5800,1800,9100,1000,*,UP,PDIF +S 7200,5200,8400,5200,200,*,RIGHT,POLY +S 2000,6000,5000,6000,400,*,RIGHT,ALU1 +S 2400,5200,3600,5200,200,*,RIGHT,POLY +S 1200,4600,1700,4600,200,*,RIGHT,POLY +S 5400,5800,5400,9100,1000,*,UP,PDIF +S 6600,5800,6600,9100,1000,*,UP,PDIF +S 7800,5800,7800,9100,1000,*,UP,PDIF +S 9000,5800,9000,9100,1000,*,UP,PDIF +S 2900,5000,4000,5000,400,*,RIGHT,ALU1 +S 7000,5000,8100,5000,400,*,RIGHT,ALU1 +S 10000,5800,10000,9100,400,*,UP,PDIF +S 800,5800,800,9100,400,*,UP,PDIF +S 7000,6000,7000,6000,400,a2,LEFT,CALU1 +S 8000,6000,8000,6000,400,a2,LEFT,CALU1 +S 10000,5000,10000,5000,400,a2,LEFT,CALU1 +S 8000,5000,8000,5000,400,a1,LEFT,CALU1 +S 3000,6000,3000,6000,400,b2,LEFT,CALU1 +S 4000,6000,4000,6000,400,b2,LEFT,CALU1 +S 3000,5000,3000,5000,400,b1,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 3000,7000,3000,7000,400,z,LEFT,CALU1 +S 4000,7000,4000,7000,400,z,LEFT,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 4000,2000,4000,2000,400,z,LEFT,CALU1 +S 5000,2000,5000,2000,400,z,LEFT,CALU1 +V 10000,700,CONT_BODY_P,* +V 9000,700,CONT_BODY_P,* +V 10200,6700,CONT_DIF_P,n3 +V 10200,5900,CONT_DIF_P,n3 +V 9400,5000,CONT_POLY,* +V 7400,2000,CONT_DIF_N,* +V 6600,8000,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,n3 +V 9000,8000,CONT_DIF_P,* +V 7800,7000,CONT_DIF_P,n3 +V 5000,5000,CONT_POLY,* +V 600,8000,CONT_DIF_P,n3 +V 3000,8000,CONT_DIF_P,n3 +V 5400,8000,CONT_DIF_P,n3 +V 7800,8000,CONT_DIF_P,n3 +V 6000,5000,CONT_POLY,* +V 2000,4400,CONT_POLY,* +V 3800,5000,CONT_POLY,* +V 6600,9000,CONT_DIF_P,* +V 9000,9000,CONT_DIF_P,* +V 1800,7000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 5400,2000,CONT_DIF_N,* +V 7400,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 5400,3000,CONT_DIF_N,* +V 7100,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/aoi22_x2.vbe b/pdks/symbolic/msxlib/cells/aoi22_x2.vbe new file mode 100644 index 000000000..329506d46 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aoi22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY aoi22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 11000; + CONSTANT cin_b1 : NATURAL := 11; + CONSTANT cin_b2 : NATURAL := 12; + CONSTANT cin_a1 : NATURAL := 11; + CONSTANT cin_a2 : NATURAL := 12; + CONSTANT rdown_b1_z : NATURAL := 1110; + CONSTANT rdown_b2_z : NATURAL := 1110; + CONSTANT rdown_a1_z : NATURAL := 1120; + CONSTANT rdown_a2_z : NATURAL := 1120; + CONSTANT rup_b1_z : NATURAL := 1430; + CONSTANT rup_b2_z : NATURAL := 1430; + CONSTANT rup_a1_z : NATURAL := 1450; + CONSTANT rup_a2_z : NATURAL := 1450; + CONSTANT tphl_b1_z : NATURAL := 44; + CONSTANT tphl_b2_z : NATURAL := 46; + CONSTANT tplh_a2_z : NATURAL := 75; + CONSTANT tphl_a1_z : NATURAL := 64; + CONSTANT tplh_b2_z : NATURAL := 51; + CONSTANT tplh_a1_z : NATURAL := 81; + CONSTANT tplh_b1_z : NATURAL := 57; + CONSTANT tphl_a2_z : NATURAL := 66; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi22_x2; + +ARCHITECTURE behaviour_data_flow OF aoi22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi22_x2" + SEVERITY WARNING; + z <= not (((b1 and b2) or (a1 and a2))) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/aon21_x1.ap b/pdks/symbolic/msxlib/cells/aon21_x1.ap new file mode 100644 index 000000000..bfdcb1432 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aon21_x1.ap @@ -0,0 +1,110 @@ +V ALLIANCE : 6 +H aon21_x1,P, 8/ 8/2014,100 +A 0,0,7000,10000 +R 6000,6000,ref_ref,a2_60 +R 5000,5000,ref_ref,a2_50 +R 5000,7000,ref_ref,b_70 +R 4000,6000,ref_ref,b_60 +R 4000,5000,ref_ref,b_50 +R 6000,4000,ref_ref,a1_40 +R 6000,7000,ref_ref,a2_70 +R 4000,7000,ref_ref,b_70 +R 5000,6000,ref_ref,a2_60 +R 5000,4000,ref_ref,a1_40 +R 6000,5000,ref_ref,a1_50 +R 5000,3000,ref_ref,a1_30 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,3000,ref_ref,z_30 +R 2000,7000,ref_ref,z_70 +R 5000,2000,ref_ref,a1_20 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 5800,8900,5800,9300,200,*,DOWN,POLY +S 4600,8900,4600,9300,200,*,DOWN,POLY +S 3400,8900,3400,9300,200,*,DOWN,POLY +S 5800,6300,5800,8900,200,1,DOWN,PTRANS +S 6200,6500,6200,8700,400,*,UP,PDIF +S 3000,6500,3000,8700,400,*,UP,PDIF +S 4600,6300,4600,8900,200,2,DOWN,PTRANS +S 3400,6300,3400,8900,200,3,DOWN,PTRANS +S 4000,6500,4000,8700,600,*,UP,PDIF +S 6100,2700,6100,3500,600,*,UP,NDIF +S 4200,2700,4200,3500,400,*,UP,NDIF +S 4600,2500,4600,3700,200,5,UP,NTRANS +S 5400,2500,5400,3700,200,4,UP,NTRANS +S 5000,2700,5000,3500,600,n1,UP,NDIF +S 5400,2100,5400,2500,200,*,UP,POLY +S 4600,2100,4600,2500,200,*,UP,POLY +S 3400,3000,3400,3700,200,6,UP,NTRANS +S 4000,3200,4000,3500,1000,*,UP,NDIF +S 3400,2600,3400,3000,200,*,UP,POLY +S 4600,3700,4600,6300,200,*,DOWN,POLY +S 1600,3700,1600,5100,200,*,UP,POLY +S 3400,3700,3400,6300,200,*,DOWN,POLY +S 4000,3300,4000,4000,400,*,DOWN,ALU1 +S 5800,4100,5800,6300,200,*,UP,POLY +S 5400,4100,5800,4100,200,*,RIGHT,POLY +S 1200,5100,1200,6300,200,*,DOWN,POLY +S 1600,2300,1600,2700,200,*,UP,POLY +S 1000,2900,1000,7100,400,*,DOWN,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 2500,2900,2500,3500,1200,*,UP,NDIF +S 1600,2700,1600,3700,200,5,UP,NTRANS +S 1200,2900,1200,3500,400,*,DOWN,NDIF +S 5200,6500,5200,8800,600,*,UP,PDIF +S 1200,8300,1200,8700,200,*,DOWN,POLY +S 800,6500,800,8100,400,*,UP,PDIF +S 1700,6500,1700,8100,400,*,UP,PDIF +S 1200,6300,1200,8300,200,3,DOWN,PTRANS +S 1800,7700,1800,8100,600,*,UP,PDIF +S 4000,7000,5100,7000,400,*,RIGHT,ALU1 +S 3900,8000,6500,8000,400,*,RIGHT,ALU1 +S 4000,7100,5100,7100,400,*,RIGHT,ALU1 +S 5000,5000,5000,6000,400,a2,DOWN,CALU1 +S 5000,4800,5000,6000,400,*,UP,ALU1 +S 5000,6000,6000,6000,600,*,RIGHT,ALU1 +S 6000,6000,6000,7100,400,*,UP,ALU1 +S 6000,6000,6000,7000,400,a2,UP,CALU1 +S 3900,4800,3900,5000,600,*,UP,ALU1 +S 4000,5000,4000,7000,400,b,DOWN,CALU1 +S 4000,5000,4000,7000,400,*,DOWN,ALU1 +S 6000,4000,6000,5000,400,a1,UP,CALU1 +S 6000,4000,6000,5000,600,*,UP,ALU1 +S 5000,4000,6000,4000,400,*,RIGHT,ALU1 +S 6000,700,6000,3100,400,*,UP,ALU1 +S 5000,7000,5000,7000,400,b,LEFT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,7000,5000,10000,aon21_x1,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 2200,700,2200,3100,400,*,UP,ALU1 +S 1200,5100,1900,5100,200,*,RIGHT,POLY +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 2800,4000,4000,4000,400,*,RIGHT,ALU1 +S 1800,4900,2800,4900,400,*,RIGHT,ALU1 +S 1800,7900,1800,9300,400,*,UP,ALU1 +S 600,7000,2000,7000,600,*,LEFT,ALU1 +S 2800,4000,2800,6700,400,*,DOWN,ALU1 +S 5000,2000,5000,4000,600,*,DOWN,ALU1 +S 5000,2000,5000,4000,400,a1,DOWN,CALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 1000,9300,CONT_BODY_N,* +V 4000,3400,CONT_DIF_N,zn +V 1000,3400,CONT_DIF_N,* +V 5000,4900,CONT_POLY,* +V 6000,4900,CONT_POLY,* +V 3800,4900,CONT_POLY,* +V 6000,3000,CONT_DIF_N,* +V 5200,9000,CONT_DIF_P,* +V 6400,8000,CONT_DIF_P,n2 +V 4000,8000,CONT_DIF_P,n2 +V 1800,8000,CONT_DIF_P,* +V 2200,3000,CONT_DIF_N,* +V 1900,4900,CONT_POLY,zn +V 2800,6600,CONT_DIF_P,zn +V 600,7000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/aon21_x1.vbe b/pdks/symbolic/msxlib/cells/aon21_x1.vbe new file mode 100644 index 000000000..b1daf1416 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aon21_x1.vbe @@ -0,0 +1,38 @@ +ENTITY aon21_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a1_z : NATURAL := 2310; + CONSTANT rdown_a2_z : NATURAL := 2300; + CONSTANT rdown_b_z : NATURAL := 2290; + CONSTANT rup_a1_z : NATURAL := 2980; + CONSTANT rup_a2_z : NATURAL := 2980; + CONSTANT rup_b_z : NATURAL := 2960; + CONSTANT tphh_a1_z : NATURAL := 94; + CONSTANT tphh_b_z : NATURAL := 80; + CONSTANT tpll_b_z : NATURAL := 91; + CONSTANT tphh_a2_z : NATURAL := 95; + CONSTANT tpll_a2_z : NATURAL := 113; + CONSTANT tpll_a1_z : NATURAL := 123; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aon21_x1; + +ARCHITECTURE behaviour_data_flow OF aon21_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aon21_x1" + SEVERITY WARNING; + z <= ((a1 and a2) or b) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/aon21_x2.ap b/pdks/symbolic/msxlib/cells/aon21_x2.ap new file mode 100644 index 000000000..cb0ae1128 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aon21_x2.ap @@ -0,0 +1,119 @@ +V ALLIANCE : 6 +H aon21_x2,P, 8/ 8/2014,100 +A 0,0,7000,10000 +R 6000,6000,ref_ref,a2_60 +R 5000,5000,ref_ref,a2_50 +R 5000,7000,ref_ref,b_70 +R 4000,6000,ref_ref,b_60 +R 4000,5000,ref_ref,b_50 +R 6000,4000,ref_ref,a1_40 +R 6000,7000,ref_ref,a2_70 +R 4000,7000,ref_ref,b_70 +R 5000,6000,ref_ref,a2_60 +R 5000,4000,ref_ref,a1_40 +R 6000,5000,ref_ref,a1_50 +R 5000,3000,ref_ref,a1_30 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,3000,ref_ref,z_30 +R 1000,2000,ref_ref,z_20 +R 2000,7000,ref_ref,z_70 +R 5000,2000,ref_ref,a1_20 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 4600,1400,4600,1800,200,*,UP,POLY +S 5400,1400,5400,1800,200,*,UP,POLY +S 6100,2000,6100,3300,600,*,UP,NDIF +S 5400,1800,5400,3500,200,4,UP,NTRANS +S 5000,2000,5000,3300,600,n1,UP,NDIF +S 4600,1800,4600,3500,200,5,UP,NTRANS +S 4200,2000,4200,3300,400,*,UP,NDIF +S 1600,1200,1600,1600,200,*,UP,POLY +S 1000,2500,1000,3100,600,*,UP,NDIF +S 1200,1800,1200,3300,400,*,DOWN,NDIF +S 1600,1600,1600,3500,200,5,UP,NTRANS +S 2500,1800,2500,3300,1200,*,UP,NDIF +S 4000,3100,4000,4000,400,*,DOWN,ALU1 +S 4600,3500,4600,5500,200,*,DOWN,POLY +S 3400,2100,3400,2500,200,*,UP,POLY +S 3400,2500,3400,3500,200,6,UP,NTRANS +S 4000,2700,4000,3300,1000,*,UP,NDIF +S 5800,3900,5800,4700,200,*,UP,POLY +S 5400,3900,5800,3900,200,*,RIGHT,POLY +S 3400,3300,3400,5500,200,*,DOWN,POLY +S 4000,7000,5100,7000,400,*,RIGHT,ALU1 +S 3900,8000,6500,8000,400,*,RIGHT,ALU1 +S 4000,7100,5100,7100,400,*,RIGHT,ALU1 +S 5000,5000,5000,6000,400,a2,DOWN,CALU1 +S 5000,4800,5000,6000,400,*,UP,ALU1 +S 5000,6000,6000,6000,600,*,RIGHT,ALU1 +S 6000,6000,6000,7100,400,*,UP,ALU1 +S 6000,6000,6000,7000,400,a2,UP,CALU1 +S 3900,4800,3900,5000,600,*,UP,ALU1 +S 4000,5000,4000,7000,400,b,DOWN,CALU1 +S 4000,5000,4000,7000,400,*,DOWN,ALU1 +S 6000,4000,6000,5000,400,a1,UP,CALU1 +S 6000,4000,6000,5000,600,*,UP,ALU1 +S 5000,4000,6000,4000,400,*,RIGHT,ALU1 +S 6000,700,6000,3100,400,*,UP,ALU1 +S 5000,7000,5000,7000,400,b,LEFT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,7000,5000,10000,aon21_x2,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 2200,700,2200,3100,400,*,UP,ALU1 +S 1600,3600,1600,5100,200,*,UP,POLY +S 1200,5100,1900,5100,200,*,RIGHT,POLY +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 2800,4000,4000,4000,400,*,RIGHT,ALU1 +S 1800,4900,2800,4900,400,*,RIGHT,ALU1 +S 1800,7900,1800,9300,400,*,UP,ALU1 +S 600,7000,2000,7000,600,*,LEFT,ALU1 +S 600,6100,600,6900,600,*,DOWN,PDIF +S 1000,1900,1000,7100,400,*,DOWN,ALU1 +S 600,6000,1000,6000,600,*,RIGHT,ALU1 +S 2800,4000,2800,6700,400,*,DOWN,ALU1 +S 2800,5900,2800,6500,600,*,UP,PDIF +S 1200,5500,1200,9300,200,3,DOWN,PTRANS +S 1700,5700,1700,9100,400,*,UP,PDIF +S 1800,7700,1800,9100,600,*,UP,PDIF +S 800,5700,800,9100,400,*,UP,PDIF +S 4000,5700,4000,9100,600,*,UP,PDIF +S 4600,5500,4600,9300,200,2,DOWN,PTRANS +S 3400,5500,3400,9300,200,3,DOWN,PTRANS +S 3000,5700,3000,9100,400,*,UP,PDIF +S 6200,5700,6200,9100,400,*,UP,PDIF +S 5800,5500,5800,9300,200,1,DOWN,PTRANS +S 5200,5700,5200,9100,600,*,UP,PDIF +S 5800,9300,5800,9700,200,*,DOWN,POLY +S 4600,9300,4600,9700,200,*,DOWN,POLY +S 3400,9300,3400,9700,200,*,DOWN,POLY +S 1200,9300,1200,9700,200,*,DOWN,POLY +S 5000,2000,5000,4000,600,*,DOWN,ALU1 +S 5000,2000,5000,4000,400,a1,DOWN,CALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 6000,2100,CONT_DIF_N,* +V 1000,2400,CONT_DIF_N,* +V 1000,3200,CONT_DIF_N,* +V 4000,3200,CONT_DIF_N,zn +V 5000,4900,CONT_POLY,* +V 6000,4900,CONT_POLY,* +V 3800,4900,CONT_POLY,* +V 6000,3000,CONT_DIF_N,* +V 5200,9000,CONT_DIF_P,* +V 6400,8000,CONT_DIF_P,n2 +V 4000,8000,CONT_DIF_P,n2 +V 1800,9000,CONT_DIF_P,* +V 1800,8000,CONT_DIF_P,* +V 2200,2000,CONT_DIF_N,* +V 2200,3000,CONT_DIF_N,* +V 2800,5800,CONT_DIF_P,zn +V 1900,4900,CONT_POLY,zn +V 2800,6600,CONT_DIF_P,zn +V 600,7000,CONT_DIF_P,* +V 600,6000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/aon21_x2.vbe b/pdks/symbolic/msxlib/cells/aon21_x2.vbe new file mode 100644 index 000000000..cec020dfe --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aon21_x2.vbe @@ -0,0 +1,38 @@ +ENTITY aon21_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_a1 : NATURAL := 7; + CONSTANT cin_a2 : NATURAL := 7; + CONSTANT cin_b : NATURAL := 6; + CONSTANT rdown_a1_z : NATURAL := 1210; + CONSTANT rdown_a2_z : NATURAL := 1210; + CONSTANT rdown_b_z : NATURAL := 1210; + CONSTANT rup_a1_z : NATURAL := 1570; + CONSTANT rup_a2_z : NATURAL := 1570; + CONSTANT rup_b_z : NATURAL := 1560; + CONSTANT tphh_a1_z : NATURAL := 97; + CONSTANT tphh_b_z : NATURAL := 83; + CONSTANT tpll_b_z : NATURAL := 94; + CONSTANT tphh_a2_z : NATURAL := 98; + CONSTANT tpll_a2_z : NATURAL := 116; + CONSTANT tpll_a1_z : NATURAL := 126; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aon21_x2; + +ARCHITECTURE behaviour_data_flow OF aon21_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aon21_x2" + SEVERITY WARNING; + z <= ((a1 and a2) or b) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/aon22_x1.ap b/pdks/symbolic/msxlib/cells/aon22_x1.ap new file mode 100644 index 000000000..a1f15c482 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aon22_x1.ap @@ -0,0 +1,140 @@ +V ALLIANCE : 6 +H aon22_x1,P, 8/ 8/2014,100 +A 0,0,8000,10000 +R 6000,7000,ref_ref,a2_70 +R 5000,7000,ref_ref,b2_70 +R 6000,6000,ref_ref,a2_60 +R 6000,5000,ref_ref,a2_50 +R 7000,5000,ref_ref,a1_50 +R 7000,3000,ref_ref,a1_30 +R 6000,3000,ref_ref,a1_30 +R 7000,6000,ref_ref,a2_60 +R 6000,4000,ref_ref,a2_40 +R 4000,3000,ref_ref,b1_30 +R 4000,5000,ref_ref,b1_50 +R 5000,6000,ref_ref,b2_60 +R 7000,4000,ref_ref,a1_40 +R 4000,4000,ref_ref,b1_40 +R 5000,3000,ref_ref,b1_30 +R 4000,6000,ref_ref,b2_60 +R 5000,5000,ref_ref,b2_50 +R 5000,4000,ref_ref,b2_40 +R 2000,6000,ref_ref,z_60 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,3000,ref_ref,z_30 +R 1000,2000,ref_ref,z_20 +S 2100,9300,2900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 6200,5900,6200,9100,600,*,UP,PDIF +S 6000,4000,6000,7000,400,a2,DOWN,CALU1 +S 5000,4000,5000,7000,400,b2,DOWN,CALU1 +S 5000,3900,5000,7100,400,*,DOWN,ALU1 +S 6000,3900,6000,7100,400,*,UP,ALU1 +S 7400,7300,7400,8100,600,*,DOWN,PDIF +S 7400,7000,7400,8000,400,*,DOWN,ALU1 +S 2500,8000,7400,8000,400,*,RIGHT,ALU1 +S 4000,3000,4000,5000,400,b1,UP,CALU1 +S 4000,3000,4000,3900,400,*,UP,ALU1 +S 4000,2900,5100,2900,400,*,LEFT,ALU1 +S 3000,2000,5300,2000,400,*,RIGHT,ALU1 +S 7200,700,7200,2100,400,*,UP,ALU1 +S 6000,6000,7100,6000,400,*,RIGHT,ALU1 +S 3900,6000,5000,6000,400,*,RIGHT,ALU1 +S 3000,2000,3000,7000,400,*,DOWN,ALU1 +S 5900,2900,7000,2900,400,*,RIGHT,ALU1 +S 5900,3000,7000,3000,400,*,RIGHT,ALU1 +S 7000,3000,7000,5000,400,a1,UP,CALU1 +S 7000,3000,7000,5100,400,*,UP,ALU1 +S 7000,6000,7000,6000,400,a2,LEFT,CALU1 +S 6000,3000,6000,3000,400,a1,LEFT,CALU1 +S 5000,3000,5000,3000,400,b1,LEFT,CALU1 +S 4000,6000,4000,6000,400,b2,LEFT,CALU1 +S 4000,3000,5100,3000,400,*,LEFT,ALU1 +S 4000,4900,4000,5100,400,*,UP,ALU1 +S 1000,6000,2000,6000,600,*,LEFT,ALU1 +S 2000,6000,2000,6000,400,z,LEFT,CALU1 +S 3000,7000,3900,7000,400,*,RIGHT,ALU1 +S 600,8400,600,9300,400,*,UP,ALU1 +S 1800,4900,3000,4900,400,*,RIGHT,ALU1 +S 1700,5900,1700,6900,400,*,DOWN,ALU1 +S 6600,1300,6600,1700,200,*,UP,POLY +S 5800,1300,5800,1700,200,*,UP,POLY +S 4600,1300,4600,1700,200,*,UP,POLY +S 3800,1300,3800,1700,200,*,UP,POLY +S 6600,2900,6600,3900,200,*,UP,POLY +S 5800,2900,5800,4700,200,*,UP,POLY +S 4600,2900,4600,5100,200,*,DOWN,POLY +S 3800,2900,3800,4000,200,*,UP,POLY +S 1100,5100,1900,5100,200,*,RIGHT,POLY +S 1100,7500,1100,7900,200,*,UP,POLY +S 6800,8300,6800,8700,200,*,DOWN,POLY +S 5600,8300,5600,8700,200,*,DOWN,POLY +S 3200,8300,3200,8700,200,*,DOWN,POLY +S 4400,8300,4400,8700,200,*,DOWN,POLY +S 4200,1900,4200,2700,600,n2,UP,NDIF +S 5200,1900,5200,2700,1000,*,UP,NDIF +S 7300,1900,7300,2700,600,*,UP,NDIF +S 6200,1900,6200,2700,600,n1,UP,NDIF +S 6600,1700,6600,2900,200,6,UP,NTRANS +S 3800,1700,3800,2900,200,5,UP,NTRANS +S 4600,1700,4600,2900,200,7,UP,NTRANS +S 5800,1700,5800,2900,200,8,UP,NTRANS +S 600,5700,600,8600,400,*,DOWN,PDIF +S 500,5700,500,8600,400,*,DOWN,PDIF +S 3800,5900,3800,8100,1000,*,UP,PDIF +S 5000,5900,5000,8100,1000,*,UP,PDIF +S 6800,5700,6800,8300,200,2,DOWN,PTRANS +S 2800,5900,2800,8100,400,*,UP,PDIF +S 1100,5500,1100,7500,200,1z,DOWN,PTRANS +S 4400,5700,4400,8300,200,3,DOWN,PTRANS +S 3200,5700,3200,8300,200,1,DOWN,PTRANS +S 1500,5700,1500,7300,400,*,UP,PDIF +S 1700,6100,1700,6700,600,*,UP,PDIF +S 5600,5700,5600,8300,200,4,DOWN,PTRANS +S 7200,5900,7200,8100,400,*,UP,PDIF +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,5000,8000,5000,10000,aon22_x1,LEFT,TALU8 +S 0,2200,8000,2200,5200,*,LEFT,PWELL +S 0,7600,8000,7600,5600,*,LEFT,NWELL +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 1600,2900,1600,3900,200,2z,UP,NTRANS +S 1200,3100,1200,3700,400,*,UP,NDIF +S 1600,2500,1600,2900,200,*,DOWN,POLY +S 2500,1900,2500,3700,1200,*,UP,NDIF +S 2200,700,2200,3100,400,*,DOWN,ALU1 +S 3200,1900,3200,2700,600,*,UP,NDIF +S 3200,4300,3500,4300,200,*,RIGHT,POLY +S 3200,4300,3200,5700,200,*,DOWN,POLY +S 4400,5000,4400,5700,200,*,DOWN,POLY +S 5600,5000,5600,5700,200,*,DOWN,POLY +S 6800,3800,6800,5700,200,*,DOWN,POLY +S 3800,4100,4000,4100,600,*,RIGHT,ALU1 +S 1600,3900,1600,5100,200,*,UP,POLY +S 1000,1900,1000,6000,400,*,DOWN,ALU1 +S 1000,2000,1000,6000,400,z,DOWN,CALU1 +V 3000,9300,CONT_BODY_N,* +V 2000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 7400,7100,CONT_DIF_P,n3 +V 7400,7900,CONT_DIF_P,n3 +V 6200,9000,CONT_DIF_P,* +V 5000,4000,CONT_POLY,* +V 6000,4900,CONT_POLY,* +V 7000,4000,CONT_POLY,* +V 1900,4900,CONT_POLY,zn +V 7200,2000,CONT_DIF_N,* +V 5200,2000,CONT_DIF_N,zn +V 2200,2000,CONT_DIF_N,* +V 1700,6000,CONT_DIF_P,* +V 600,8500,CONT_DIF_P,* +V 1700,6800,CONT_DIF_P,* +V 2600,8000,CONT_DIF_P,n3 +V 5000,8000,CONT_DIF_P,n3 +V 3800,7000,CONT_DIF_P,zn +V 1000,3600,CONT_DIF_N,* +V 2200,3000,CONT_DIF_N,* +V 3800,4100,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/aon22_x1.vbe b/pdks/symbolic/msxlib/cells/aon22_x1.vbe new file mode 100644 index 000000000..ffdc6d277 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aon22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY aon22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT cin_b1 : NATURAL := 5; + CONSTANT cin_b2 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT rdown_b1_z : NATURAL := 2310; + CONSTANT rdown_b2_z : NATURAL := 2310; + CONSTANT rdown_a2_z : NATURAL := 2320; + CONSTANT rdown_a1_z : NATURAL := 2320; + CONSTANT rup_b1_z : NATURAL := 2960; + CONSTANT rup_b2_z : NATURAL := 2960; + CONSTANT rup_a2_z : NATURAL := 2990; + CONSTANT rup_a1_z : NATURAL := 2990; + CONSTANT tphh_b1_z : NATURAL := 87; + CONSTANT tpll_a2_z : NATURAL := 133; + CONSTANT tphh_b2_z : NATURAL := 88; + CONSTANT tpll_a1_z : NATURAL := 142; + CONSTANT tpll_b2_z : NATURAL := 104; + CONSTANT tphh_a1_z : NATURAL := 114; + CONSTANT tpll_b1_z : NATURAL := 114; + CONSTANT tphh_a2_z : NATURAL := 115; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a2 : in BIT; + a1 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aon22_x1; + +ARCHITECTURE behaviour_data_flow OF aon22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aon22_x1" + SEVERITY WARNING; + z <= ((b1 and b2) or (a2 and a1)) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/aon22_x2.ap b/pdks/symbolic/msxlib/cells/aon22_x2.ap new file mode 100644 index 000000000..c7a228cf7 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aon22_x2.ap @@ -0,0 +1,142 @@ +V ALLIANCE : 6 +H aon22_x2,P, 8/ 8/2014,100 +A 0,0,9000,10000 +R 1000,6000,ref_ref,z_60 +R 2000,7000,ref_ref,z_70 +R 2000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,z_50 +R 2000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +R 2000,2000,ref_ref,z_20 +R 5000,5000,ref_ref,b1_50 +R 6000,6000,ref_ref,b2_60 +R 8000,4000,ref_ref,a1_40 +R 5000,4000,ref_ref,b1_40 +R 6000,3000,ref_ref,b1_30 +R 5000,6000,ref_ref,b2_60 +R 6000,5000,ref_ref,b2_50 +R 6000,4000,ref_ref,b2_40 +R 7000,6000,ref_ref,a2_60 +R 7000,5000,ref_ref,a2_50 +R 8000,5000,ref_ref,a1_50 +R 8000,3000,ref_ref,a1_30 +R 7000,3000,ref_ref,a1_30 +R 8000,6000,ref_ref,a2_60 +R 7000,4000,ref_ref,a2_40 +R 5000,3000,ref_ref,b1_30 +R 6000,7000,ref_ref,b2_70 +R 7000,7000,ref_ref,a2_70 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 1200,5500,1200,9300,200,1z,DOWN,PTRANS +S 5400,5000,5400,5500,200,*,DOWN,POLY +S 5600,3400,5600,5100,200,*,DOWN,POLY +S 2800,4900,4000,4900,400,*,RIGHT,ALU1 +S 1200,5100,2900,5100,200,*,RIGHT,POLY +S 1900,6000,1900,7100,600,*,UP,ALU1 +S 2000,1900,2000,6000,400,*,DOWN,ALU1 +S 900,6000,2000,6000,400,*,LEFT,ALU1 +S 1000,6000,1000,6000,400,z,LEFT,CALU1 +S 1800,6100,1800,6700,600,*,UP,PDIF +S 2000,2000,2000,7000,400,z,DOWN,CALU1 +S 600,5700,600,9100,600,*,DOWN,PDIF +S 1600,5700,1600,9100,400,*,UP,PDIF +S 1200,9300,1200,9700,200,*,UP,POLY +S 600,6900,600,9300,400,*,UP,ALU1 +S 4000,7000,4900,7000,400,*,RIGHT,ALU1 +S 3200,700,3200,3100,400,*,DOWN,ALU1 +S 4200,9300,4200,9700,200,*,DOWN,POLY +S 5400,9300,5400,9700,200,*,DOWN,POLY +S 6600,9300,6600,9700,200,*,DOWN,POLY +S 7800,9300,7800,9700,200,*,DOWN,POLY +S 8200,5700,8200,9100,400,*,UP,PDIF +S 6000,5700,6000,9100,1000,*,UP,PDIF +S 7200,5700,7200,9100,1000,*,UP,PDIF +S 7800,5500,7800,9300,200,2,DOWN,PTRANS +S 6600,5500,6600,9300,200,4,DOWN,PTRANS +S 3800,5700,3800,9100,400,*,UP,PDIF +S 4800,5700,4800,9100,1000,*,UP,PDIF +S 5400,5500,5400,9300,200,3,DOWN,PTRANS +S 4200,5500,4200,9300,200,1,DOWN,PTRANS +S 0,5000,9000,5000,10000,aon22_x2,LEFT,TALU8 +S 0,2200,9000,2200,5200,*,LEFT,PWELL +S 0,7600,9000,7600,5600,*,LEFT,NWELL +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 7600,3400,7600,3900,200,*,UP,POLY +S 6800,3400,6800,4700,200,*,UP,POLY +S 7800,3800,7800,5500,200,*,DOWN,POLY +S 7600,1300,7600,1700,200,*,UP,POLY +S 6800,1300,6800,1700,200,*,UP,POLY +S 5600,1300,5600,1700,200,*,UP,POLY +S 4800,1300,4800,1700,200,*,UP,POLY +S 6600,5000,6600,5500,200,*,DOWN,POLY +S 4200,4200,4500,4200,200,*,RIGHT,POLY +S 4200,4200,4200,5500,200,*,DOWN,POLY +S 8000,6000,8000,6000,400,a2,LEFT,CALU1 +S 7000,3000,7000,3000,400,a1,LEFT,CALU1 +S 6000,3000,6000,3000,400,b1,LEFT,CALU1 +S 5000,6000,5000,6000,400,b2,LEFT,CALU1 +S 5000,3000,6100,3000,400,*,LEFT,ALU1 +S 5000,4900,5000,5100,400,*,UP,ALU1 +S 4000,2000,4000,7000,400,*,DOWN,ALU1 +S 6900,2900,8000,2900,400,*,RIGHT,ALU1 +S 6900,3000,8000,3000,400,*,RIGHT,ALU1 +S 8000,3000,8000,5000,400,a1,UP,CALU1 +S 8000,3000,8000,5100,400,*,UP,ALU1 +S 7000,6000,8100,6000,400,*,RIGHT,ALU1 +S 4900,6000,6000,6000,400,*,RIGHT,ALU1 +S 5000,3000,5000,5000,400,b1,UP,CALU1 +S 5000,3000,5000,3900,400,*,UP,ALU1 +S 5000,2900,6100,2900,400,*,LEFT,ALU1 +S 4000,2000,6300,2000,400,*,RIGHT,ALU1 +S 4800,4000,5000,4000,600,*,RIGHT,ALU1 +S 8200,700,8200,2100,400,*,UP,ALU1 +S 8300,1900,8300,3200,600,*,UP,NDIF +S 7200,1900,7200,3200,600,n1,UP,NDIF +S 7600,1700,7600,3400,200,6,UP,NTRANS +S 6800,1700,6800,3400,200,8,UP,NTRANS +S 5200,1900,5200,3200,600,n2,UP,NDIF +S 4800,1700,4800,3400,200,5,UP,NTRANS +S 5600,1700,5600,3400,200,7,UP,NTRANS +S 6200,1900,6200,3200,1000,*,UP,NDIF +S 4200,1900,4200,3200,600,*,UP,NDIF +S 4800,3400,4800,4000,200,*,UP,POLY +S 2600,1300,2600,1700,200,*,DOWN,POLY +S 2200,1900,2200,3400,400,*,UP,NDIF +S 2600,1700,2600,3600,200,2z,UP,NTRANS +S 2000,2600,2000,3200,600,*,UP,NDIF +S 3500,1900,3500,3400,1200,*,UP,NDIF +S 2600,3600,2600,5100,200,*,UP,POLY +S 3500,8000,8400,8000,400,*,RIGHT,ALU1 +S 8400,7200,8400,7800,600,*,DOWN,PDIF +S 8400,7000,8400,8000,400,*,DOWN,ALU1 +S 6000,3900,6000,7100,400,*,DOWN,ALU1 +S 6000,4000,6000,7000,400,b2,DOWN,CALU1 +S 7000,3900,7000,7100,400,*,UP,ALU1 +S 7000,4000,7000,7000,400,a2,DOWN,CALU1 +V 2700,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2900,4900,CONT_POLY,zn +V 6200,2000,CONT_DIF_N,zn +V 4800,7000,CONT_DIF_P,zn +V 1800,6800,CONT_DIF_P,* +V 1800,6000,CONT_DIF_P,* +V 600,9000,CONT_DIF_P,* +V 600,7000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 3200,3000,CONT_DIF_N,* +V 3200,2000,CONT_DIF_N,* +V 3600,8000,CONT_DIF_P,n3 +V 6000,8000,CONT_DIF_P,n3 +V 7200,9000,CONT_DIF_P,* +V 8200,2000,CONT_DIF_N,* +V 7000,4900,CONT_POLY,* +V 4800,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +V 2000,2500,CONT_DIF_N,* +V 2000,3300,CONT_DIF_N,* +V 8400,7100,CONT_DIF_P,n3 +V 8400,7900,CONT_DIF_P,n3 +EOF diff --git a/pdks/symbolic/msxlib/cells/aon22_x2.vbe b/pdks/symbolic/msxlib/cells/aon22_x2.vbe new file mode 100644 index 000000000..2b7c10b99 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/aon22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY aon22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 9000; + CONSTANT cin_b1 : NATURAL := 7; + CONSTANT cin_b2 : NATURAL := 7; + CONSTANT cin_a2 : NATURAL := 6; + CONSTANT cin_a1 : NATURAL := 6; + CONSTANT rdown_b1_z : NATURAL := 1220; + CONSTANT rdown_b2_z : NATURAL := 1210; + CONSTANT rdown_a2_z : NATURAL := 1220; + CONSTANT rdown_a1_z : NATURAL := 1220; + CONSTANT rup_b1_z : NATURAL := 1560; + CONSTANT rup_b2_z : NATURAL := 1560; + CONSTANT rup_a2_z : NATURAL := 1570; + CONSTANT rup_a1_z : NATURAL := 1570; + CONSTANT tphh_b1_z : NATURAL := 88; + CONSTANT tpll_a2_z : NATURAL := 132; + CONSTANT tphh_b2_z : NATURAL := 89; + CONSTANT tpll_a1_z : NATURAL := 141; + CONSTANT tpll_b2_z : NATURAL := 105; + CONSTANT tphh_a1_z : NATURAL := 115; + CONSTANT tpll_b1_z : NATURAL := 114; + CONSTANT tphh_a2_z : NATURAL := 117; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a2 : in BIT; + a1 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aon22_x2; + +ARCHITECTURE behaviour_data_flow OF aon22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aon22_x2" + SEVERITY WARNING; + z <= ((b1 and b2) or (a2 and a1)) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/bf1_w05.ap b/pdks/symbolic/msxlib/cells/bf1_w05.ap new file mode 100644 index 000000000..5fba830e0 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_w05.ap @@ -0,0 +1,59 @@ +V ALLIANCE : 6 +H bf1_w05,P, 8/ 8/2014,100 +A 0,0,3000,10000 +R 2000,5000,ref_ref,z_50 +R 2000,4000,ref_ref,z_40 +R 2000,6000,ref_ref,z_60 +R 2000,8000,ref_ref,a_80 +R 2000,7000,ref_ref,a_70 +R 1000,5000,ref_ref,z_50 +S 2000,7000,2300,7000,600,*,RIGHT,ALU1 +S 0,5000,3000,5000,10000,bf1_w05,LEFT,TALU8 +S 0,2200,3000,2200,5200,*,LEFT,PWELL +S 0,7600,3000,7600,5600,*,LEFT,NWELL +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 1200,5500,1200,6400,200,1z,UP,PTRANS +S 800,5700,800,6200,400,*,UP,PDIF +S 1600,5700,1600,6200,400,*,DOWN,PDIF +S 1200,3300,1200,3900,200,2z,DOWN,NTRANS +S 400,6100,700,6100,400,*,LEFT,ALU1 +S 400,6100,400,9300,400,*,UP,ALU1 +S 400,6000,700,6000,400,*,LEFT,ALU1 +S 1200,3900,1200,5500,200,*,DOWN,POLY +S 400,700,400,3600,400,*,DOWN,ALU1 +S 400,3600,700,3600,400,*,RIGHT,ALU1 +S 400,3700,700,3700,400,*,LEFT,ALU1 +S 1600,7800,1600,8300,400,*,DOWN,PDIF +S 2000,7600,2000,8500,200,1a,UP,PTRANS +S 2000,8500,2000,8800,200,*,UP,POLY +S 2500,7800,2500,9500,400,*,DOWN,PDIF +S 2000,4000,2000,6000,400,z,DOWN,CALU1 +S 1200,6900,1200,8000,400,*,DOWN,ALU1 +S 2000,7000,2000,8000,400,a,UP,CALU1 +S 2000,6900,2000,8100,400,*,DOWN,ALU1 +S 2000,6800,2000,7600,200,*,DOWN,POLY +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 1900,3600,1900,6100,600,*,UP,ALU1 +S 900,5000,2000,5000,400,*,LEFT,ALU1 +S 1000,5000,1000,5000,400,z,LEFT,CALU1 +S 2000,1600,2000,2200,200,2a,DOWN,NTRANS +S 2000,2600,2500,2600,200,*,RIGHT,POLY +S 2500,2600,2500,7200,200,*,DOWN,POLY +S 2500,500,2500,2000,400,*,UP,NDIF +S 2000,1200,2000,1600,200,*,DOWN,POLY +S 1300,1900,1300,2800,600,*,DOWN,ALU1 +S 2000,2200,2000,2600,200,*,UP,POLY +V 1000,700,CONT_BODY_P,* +V 1000,9300,CONT_BODY_N,* +V 2200,7000,CONT_POLY,* +V 1800,5800,CONT_DIF_P,* +V 600,6100,CONT_DIF_P,* +V 600,3600,CONT_DIF_N,* +V 2400,9400,CONT_DIF_P,* +V 1200,2700,CONT_POLY,an +V 1200,7900,CONT_DIF_P,an +V 2400,600,CONT_DIF_N,* +V 1900,3600,CONT_DIF_N,* +V 1200,7000,CONT_POLY,an +V 1300,1900,CONT_DIF_N,an +EOF diff --git a/pdks/symbolic/msxlib/cells/bf1_w05.vbe b/pdks/symbolic/msxlib/cells/bf1_w05.vbe new file mode 100644 index 000000000..aee4efe5e --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_w05.vbe @@ -0,0 +1,26 @@ +ENTITY bf1_w05 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_a : NATURAL := 2; + CONSTANT rdown_a_z : NATURAL := 3810; + CONSTANT rup_a_z : NATURAL := 6580; + CONSTANT tpll_a_z : NATURAL := 80; + CONSTANT tphh_a_z : NATURAL := 61; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1_w05; + +ARCHITECTURE behaviour_data_flow OF bf1_w05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1_w05" + SEVERITY WARNING; + z <= a after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/bf1_w2.ap b/pdks/symbolic/msxlib/cells/bf1_w2.ap new file mode 100644 index 000000000..47d5bb117 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_w2.ap @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H bf1_w2,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 1000,2000,ref_ref,z_20 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 3000,4000,ref_ref,a_40 +R 3000,6000,ref_ref,a_60 +R 3000,5000,ref_ref,a_50 +S 1100,700,1900,700,600,*,LEFT,PTIE +S 2200,1900,2200,3400,600,*,UP,NDIF +S 3400,7000,3400,7900,400,*,UP,ALU1 +S 2000,6900,3400,6900,400,*,RIGHT,ALU1 +S 1600,9300,1600,9700,200,*,DOWN,POLY +S 2200,5700,2200,9100,600,*,DOWN,PDIF +S 2200,7900,2200,9300,400,*,UP,ALU1 +S 1200,5700,1200,9100,400,*,UP,PDIF +S 1200,1900,1200,3400,400,*,DOWN,NDIF +S 1600,3600,1600,5500,200,*,UP,POLY +S 1600,1300,1600,1700,200,*,UP,POLY +S 2200,700,2200,2100,400,*,UP,ALU1 +S 1000,1900,1000,7100,400,*,UP,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,4000,5000,10000,bf1_w2,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 3000,3900,3000,6100,400,*,DOWN,ALU1 +S 3000,4000,3000,6000,400,a,DOWN,CALU1 +S 2800,3600,2800,5500,200,*,UP,POLY +S 3400,7300,3400,7900,600,*,UP,PDIF +S 1000,5700,1000,6500,600,*,UP,PDIF +S 1000,2900,1000,3310,600,*,UP,NDIF +S 1600,5500,1600,9300,200,1z,UP,PTRANS +S 1600,1700,1600,3600,200,2z,DOWN,NTRANS +S 2800,9300,2800,9700,200,*,DOWN,POLY +S 2800,5500,2800,9300,200,1a,UP,PTRANS +S 3200,5700,3200,9100,400,*,UP,PDIF +S 2800,1300,2800,1700,200,*,UP,POLY +S 3200,1900,3200,3400,400,*,DOWN,NDIF +S 2800,1700,2800,3600,200,2a,DOWN,NTRANS +S 2000,3000,2000,6900,400,*,UP,ALU1 +S 3400,1900,3400,3000,400,*,UP,ALU1 +S 2000,3000,3400,3000,400,*,LEFT,ALU1 +S 3400,2100,3400,2700,600,*,UP,NDIF +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 3400,7800,CONT_DIF_P,an +V 3400,7000,CONT_DIF_P,an +V 2200,8000,CONT_DIF_P,* +V 2200,9000,CONT_DIF_P,* +V 2200,2000,CONT_DIF_N,* +V 3000,4700,CONT_POLY,* +V 2000,4700,CONT_POLY,an +V 1000,5800,CONT_DIF_P,* +V 1000,6600,CONT_DIF_P,* +V 1000,3300,CONT_DIF_N,* +V 1000,2500,CONT_DIF_N,* +V 3400,2000,CONT_DIF_N,an +V 3400,2800,CONT_DIF_N,an +EOF diff --git a/pdks/symbolic/msxlib/cells/bf1_w2.vbe b/pdks/symbolic/msxlib/cells/bf1_w2.vbe new file mode 100644 index 000000000..b4b7b0d9e --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_w2.vbe @@ -0,0 +1,26 @@ +ENTITY bf1_w2 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 7; + CONSTANT rdown_a_z : NATURAL := 1200; + CONSTANT rup_a_z : NATURAL := 1560; + CONSTANT tpll_a_z : NATURAL := 69; + CONSTANT tphh_a_z : NATURAL := 56; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1_w2; + +ARCHITECTURE behaviour_data_flow OF bf1_w2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1_w2" + SEVERITY WARNING; + z <= a after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/bf1_x1.ap b/pdks/symbolic/msxlib/cells/bf1_x1.ap new file mode 100644 index 000000000..78c6bb16a --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_x1.ap @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H bf1_x1,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 3000,4000,ref_ref,a_40 +R 3000,6000,ref_ref,a_60 +R 3000,5000,ref_ref,a_50 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,LEFT,PTIE +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 2000,3000,3500,3000,400,*,LEFT,ALU1 +S 2200,7900,2200,9300,400,*,UP,ALU1 +S 2200,700,2200,2100,400,*,UP,ALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,4000,5000,10000,bf1_x1,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 3000,3900,3000,6100,400,*,DOWN,ALU1 +S 3000,4000,3000,6000,400,a,DOWN,CALU1 +S 1600,6300,1600,8300,200,1z,UP,PTRANS +S 1600,8300,1600,8700,200,*,DOWN,POLY +S 2800,8300,2800,8700,200,*,DOWN,POLY +S 3200,6500,3200,8100,400,*,UP,PDIF +S 2800,6300,2800,8300,200,1a,UP,PTRANS +S 1200,6500,1200,8100,400,*,UP,PDIF +S 1000,6590,1000,7200,600,*,UP,PDIF +S 1000,2900,1000,7500,400,*,UP,ALU1 +S 3400,7300,3400,7900,600,*,DOWN,PDIF +S 2000,7000,3400,7000,400,*,RIGHT,ALU1 +S 3400,7000,3400,8100,400,*,DOWN,ALU1 +S 2000,3000,2000,7000,400,*,UP,ALU1 +S 2200,6500,2200,8100,600,*,DOWN,PDIF +S 3200,2500,3200,3100,400,*,DOWN,NDIF +S 2200,1900,2200,3100,600,*,UP,NDIF +S 1200,2500,1200,3100,400,*,DOWN,NDIF +S 1600,2300,1600,3300,200,2z,DOWN,NTRANS +S 1600,3300,1600,6300,200,*,UP,POLY +S 2800,3300,2800,6300,200,*,UP,POLY +S 2800,2300,2800,3300,200,2a,DOWN,NTRANS +S 2800,1900,2800,2300,200,*,UP,POLY +S 1600,1900,1600,2300,200,*,UP,POLY +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 3400,3000,CONT_DIF_N,an +V 2200,8000,CONT_DIF_P,* +V 2200,2000,CONT_DIF_N,* +V 3000,4700,CONT_POLY,* +V 2000,4700,CONT_POLY,an +V 1000,6600,CONT_DIF_P,* +V 1000,7400,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,an +V 3400,7200,CONT_DIF_P,an +V 1000,3000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/bf1_x1.vbe b/pdks/symbolic/msxlib/cells/bf1_x1.vbe new file mode 100644 index 000000000..c296d8e56 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_x1.vbe @@ -0,0 +1,26 @@ +ENTITY bf1_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 2280; + CONSTANT rup_a_z : NATURAL := 2960; + CONSTANT tpll_a_z : NATURAL := 73; + CONSTANT tphh_a_z : NATURAL := 61; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1_x1; + +ARCHITECTURE behaviour_data_flow OF bf1_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1_x1" + SEVERITY WARNING; + z <= a after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/bf1_x2.ap b/pdks/symbolic/msxlib/cells/bf1_x2.ap new file mode 100644 index 000000000..25ca522c6 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_x2.ap @@ -0,0 +1,63 @@ +V ALLIANCE : 6 +H bf1_x2,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 1000,2000,ref_ref,z_20 +R 3000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,a_60 +R 3000,4000,ref_ref,a_40 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,6000,ref_ref,z_60 +R 1000,7000,ref_ref,z_70 +R 1000,3000,ref_ref,z_30 +S 1100,700,1900,700,600,*,LEFT,PTIE +S 1600,1700,1600,3600,200,2z,DOWN,NTRANS +S 1600,5500,1600,9300,200,1z,UP,PTRANS +S 1000,2900,1000,3310,600,*,UP,NDIF +S 1000,5700,1000,6500,600,*,UP,PDIF +S 3000,4000,3000,6000,400,a,DOWN,CALU1 +S 3000,3900,3000,6100,400,*,DOWN,ALU1 +S 0,5000,4000,5000,10000,bf1_x2,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1000,1900,1000,7100,400,*,UP,ALU1 +S 2200,700,2200,2100,400,*,UP,ALU1 +S 1600,1300,1600,1700,200,*,UP,POLY +S 1600,3600,1600,5500,200,*,UP,POLY +S 1200,1900,1200,3400,400,*,DOWN,NDIF +S 1200,5700,1200,9100,400,*,UP,PDIF +S 2200,7900,2200,9300,400,*,UP,ALU1 +S 2200,5700,2200,9100,600,*,DOWN,PDIF +S 1600,9300,1600,9700,200,*,DOWN,POLY +S 2200,1900,2200,3400,600,*,UP,NDIF +S 2000,3000,3500,3000,400,*,LEFT,ALU1 +S 3200,2200,3200,3100,400,*,DOWN,NDIF +S 2800,2000,2800,3300,200,2a,DOWN,NTRANS +S 2800,1600,2800,2000,200,*,UP,POLY +S 3400,7500,3400,8100,600,*,UP,PDIF +S 2800,5700,2800,8300,200,1a,UP,PTRANS +S 3200,5900,3200,8100,400,*,UP,PDIF +S 2000,7000,3400,7000,400,*,RIGHT,ALU1 +S 2000,3000,2000,7000,400,*,UP,ALU1 +S 3400,7000,3400,8100,400,*,UP,ALU1 +S 2800,8300,2800,8700,200,*,DOWN,POLY +S 2800,3300,2800,5700,200,*,UP,POLY +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 3300,9300,CONT_BODY_N,* +V 1000,2500,CONT_DIF_N,* +V 1000,3300,CONT_DIF_N,* +V 1000,6600,CONT_DIF_P,* +V 1000,5800,CONT_DIF_P,* +V 2000,4700,CONT_POLY,an +V 3000,4700,CONT_POLY,* +V 2200,2000,CONT_DIF_N,* +V 2200,9000,CONT_DIF_P,* +V 2200,8000,CONT_DIF_P,* +V 3400,3000,CONT_DIF_N,an +V 3400,8000,CONT_DIF_P,an +V 3400,7200,CONT_DIF_P,an +EOF diff --git a/pdks/symbolic/msxlib/cells/bf1_x2.vbe b/pdks/symbolic/msxlib/cells/bf1_x2.vbe new file mode 100644 index 000000000..ef9a36852 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_x2.vbe @@ -0,0 +1,26 @@ +ENTITY bf1_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 1200; + CONSTANT rup_a_z : NATURAL := 1560; + CONSTANT tpll_a_z : NATURAL := 78; + CONSTANT tphh_a_z : NATURAL := 64; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1_x2; + +ARCHITECTURE behaviour_data_flow OF bf1_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1_x2" + SEVERITY WARNING; + z <= a after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/bf1_x4.ap b/pdks/symbolic/msxlib/cells/bf1_x4.ap new file mode 100644 index 000000000..bcdef37dc --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_x4.ap @@ -0,0 +1,88 @@ +V ALLIANCE : 6 +H bf1_x4,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 3000,6000,ref_ref,a_60 +R 2000,5000,ref_ref,a_50 +R 2000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +R 2000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 3000,5000,ref_ref,a_50 +R 2000,2000,ref_ref,z_20 +R 1000,3000,ref_ref,z_30 +R 3000,7000,ref_ref,a_70 +S 1100,700,1900,700,600,*,LEFT,PTIE +S 800,6900,800,9300,400,*,UP,ALU1 +S 1400,3600,1400,5600,200,*,UP,POLY +S 2600,3600,2600,5600,200,*,UP,POLY +S 3200,700,3200,3100,400,*,DOWN,ALU1 +S 2600,9400,2600,9700,200,*,DOWN,POLY +S 1400,9400,1400,9700,200,*,DOWN,POLY +S 2000,5800,2000,9200,1000,*,DOWN,PDIF +S 1000,6000,2000,6000,600,*,RIGHT,ALU1 +S 800,5800,800,9200,800,*,DOWN,PDIF +S 3200,5800,3200,9200,800,*,DOWN,PDIF +S 2000,6000,2000,7100,400,*,UP,ALU1 +S 2000,5000,2000,5000,400,a,LEFT,CALU1 +S 2000,6000,2000,7000,400,z,UP,CALU1 +S 3800,9400,3800,9700,200,*,DOWN,POLY +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,5000,5000,5000,10000,bf1_x4,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 3800,3600,3800,5600,200,*,DOWN,POLY +S 3000,5000,3000,7000,400,a,DOWN,CALU1 +S 800,700,800,2100,400,*,DOWN,ALU1 +S 1000,3000,2000,3000,600,*,LEFT,ALU1 +S 1000,3000,1000,6000,400,z,DOWN,CALU1 +S 1000,3000,1000,6000,400,*,UP,ALU1 +S 2000,2000,2000,3000,400,z,DOWN,CALU1 +S 2000,1900,2000,3000,400,*,UP,ALU1 +S 1400,4000,2600,4000,600,*,RIGHT,POLY +S 800,1700,800,3200,600,*,UP,NDIF +S 700,1700,700,3200,600,*,UP,NDIF +S 2000,1700,2000,3200,600,*,UP,NDIF +S 3300,1700,3300,3200,600,*,UP,NDIF +S 3200,1700,3200,3200,600,*,UP,NDIF +S 4400,2200,4400,6800,400,*,UP,ALU1 +S 4400,2400,4400,3000,600,*,UP,NDIF +S 4200,1700,4200,3200,400,*,UP,NDIF +S 2300,4000,4400,4000,400,*,RIGHT,ALU1 +S 1900,5000,3600,5000,400,*,RIGHT,ALU1 +S 3000,5000,3000,7100,400,*,UP,ALU1 +S 3200,7900,3200,9300,400,*,UP,ALU1 +S 4200,5800,4200,9200,400,*,DOWN,PDIF +S 4400,6000,4400,6600,600,*,UP,PDIF +S 3800,5600,3800,9400,200,1a,UP,PTRANS +S 3800,1500,3800,3400,200,1b,DOWN,NTRANS +S 2600,5600,2600,9400,200,1z,UP,PTRANS +S 1400,5600,1400,9400,200,2z,UP,PTRANS +S 2600,1500,2600,3400,200,3z,DOWN,NTRANS +S 1400,1500,1400,3400,200,4z,DOWN,NTRANS +S 1400,1200,1400,1500,200,*,UP,POLY +S 2600,1100,2600,1500,200,*,UP,POLY +S 3800,1100,3800,1500,200,*,UP,POLY +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 800,9000,CONT_DIF_P,* +V 3200,9000,CONT_DIF_P,* +V 3200,8000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 2000,3000,CONT_DIF_N,* +V 2000,7000,CONT_DIF_P,* +V 2000,6000,CONT_DIF_P,* +V 3200,3000,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 4400,6700,CONT_DIF_P,an +V 4400,5900,CONT_DIF_P,an +V 4400,2300,CONT_DIF_N,an +V 4400,3100,CONT_DIF_N,an +V 3200,2000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 2400,4000,CONT_POLY,an +V 3500,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/bf1_x4.vbe b/pdks/symbolic/msxlib/cells/bf1_x4.vbe new file mode 100644 index 000000000..475fb0839 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_x4.vbe @@ -0,0 +1,26 @@ +ENTITY bf1_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a : NATURAL := 7; + CONSTANT rdown_a_z : NATURAL := 600; + CONSTANT rup_a_z : NATURAL := 780; + CONSTANT tpll_a_z : NATURAL := 82; + CONSTANT tphh_a_z : NATURAL := 66; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1_x4; + +ARCHITECTURE behaviour_data_flow OF bf1_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1_x4" + SEVERITY WARNING; + z <= a after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/bf1_x8.ap b/pdks/symbolic/msxlib/cells/bf1_x8.ap new file mode 100644 index 000000000..971f02e6b --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_x8.ap @@ -0,0 +1,138 @@ +V ALLIANCE : 6 +H bf1_x8,P, 8/ 8/2014,100 +A 0,0,9000,10000 +R 4000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 2000,7000,ref_ref,z_70 +R 2000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +R 2000,6000,ref_ref,z_60 +R 3000,6000,ref_ref,z_60 +R 4000,6000,ref_ref,z_60 +R 4000,7000,ref_ref,z_70 +R 3000,4000,ref_ref,z_40 +R 4000,4000,ref_ref,z_40 +R 4000,3000,ref_ref,z_30 +R 8000,6000,ref_ref,a_60 +R 8000,5000,ref_ref,a_50 +R 8000,4000,ref_ref,a_40 +R 2000,5000,ref_ref,z_50 +R 7000,4000,ref_ref,a_40 +S 2400,700,3200,700,600,*,LEFT,PTIE +S 5400,700,5400,3100,400,*,DOWN,ALU1 +S 3000,4000,3000,4000,400,z,LEFT,CALU1 +S 4000,2000,4000,4000,400,z,DOWN,CALU1 +S 3000,6000,3000,6000,400,z,LEFT,CALU1 +S 4000,6000,4000,7000,400,z,UP,CALU1 +S 4100,6000,4100,7100,600,*,DOWN,ALU1 +S 1200,9400,1200,9700,200,*,DOWN,POLY +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 3600,9400,3600,9700,200,*,DOWN,POLY +S 600,6900,600,9300,400,*,UP,ALU1 +S 3000,6900,3000,9300,400,*,UP,ALU1 +S 5400,6900,5400,9300,400,*,UP,ALU1 +S 600,700,600,3100,400,*,DOWN,ALU1 +S 4100,1900,4100,4000,600,*,DOWN,ALU1 +S 3000,700,3000,3100,400,*,DOWN,ALU1 +S 4800,1300,4800,1700,200,*,UP,POLY +S 3600,1300,3600,1700,200,*,UP,POLY +S 2400,1300,2400,1700,200,*,UP,POLY +S 1200,1300,1200,1700,200,*,UP,POLY +S 1200,5500,1200,9400,200,1,UP,PTRANS +S 600,5700,600,9200,600,*,DOWN,PDIF +S 1800,5700,1800,9200,600,*,DOWN,PDIF +S 2400,5500,2400,9400,200,2,UP,PTRANS +S 3600,5500,3600,9400,200,3,UP,PTRANS +S 3000,5700,3000,9200,600,*,DOWN,PDIF +S 5400,5700,5400,8100,600,*,DOWN,PDIF +S 4800,5500,4800,8300,200,4,UP,PTRANS +S 4200,5700,4200,8100,600,*,UP,PDIF +S 4000,8500,4000,9200,400,*,UP,PDIF +S 4800,8400,4800,8700,200,*,DOWN,POLY +S 6600,5700,6600,8100,600,*,UP,PDIF +S 6000,8400,6000,8700,200,*,DOWN,POLY +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,9000,5000,10000,bf1_x8,LEFT,TALU8 +S 0,2200,9000,2200,5200,*,LEFT,PWELL +S 0,7600,9000,7600,5600,*,LEFT,NWELL +S 7800,6900,7800,9300,400,*,UP,ALU1 +S 8000,3900,8000,6100,400,*,DOWN,ALU1 +S 8000,4000,8000,6000,400,a,DOWN,CALU1 +S 6600,1900,6600,2800,600,*,UP,NDIF +S 7600,1900,7600,3100,400,*,UP,NDIF +S 7800,700,7800,3100,400,*,DOWN,ALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 7900,1900,7900,3100,600,*,UP,NDIF +S 7900,5700,7900,8900,600,*,DOWN,PDIF +S 6800,5700,6800,8900,400,*,UP,PDIF +S 7200,9100,7200,9500,200,*,DOWN,POLY +S 7200,5500,7200,9100,200,1a,UP,PTRANS +S 6000,5500,6000,8300,200,2a,UP,PTRANS +S 7200,1700,7200,3300,200,3a,DOWN,NTRANS +S 6000,1700,6000,3300,200,4a,DOWN,NTRANS +S 6000,1300,6000,1700,200,*,UP,POLY +S 7200,1300,7200,1700,200,*,UP,POLY +S 2400,4900,3600,4900,600,*,RIGHT,POLY +S 1200,5100,4800,5100,200,*,RIGHT,POLY +S 1800,6000,4200,6000,400,*,LEFT,ALU1 +S 1800,4000,4200,4000,400,*,RIGHT,ALU1 +S 1900,1900,1900,7100,600,*,DOWN,ALU1 +S 2000,2000,2000,7000,400,z,UP,CALU1 +S 6000,4000,7200,4000,600,*,RIGHT,POLY +S 7200,3300,7200,5500,200,*,DOWN,POLY +S 6000,3300,6000,5500,200,*,UP,POLY +S 7000,4000,8000,4000,600,*,RIGHT,ALU1 +S 7000,4000,7000,4000,400,a,LEFT,CALU1 +S 6200,3100,6200,4900,400,*,DOWN,ALU1 +S 2900,4900,6600,4900,400,*,RIGHT,ALU1 +S 6600,4900,6600,7100,400,*,DOWN,ALU1 +S 6600,1900,6600,3100,400,*,UP,ALU1 +S 700,1900,700,3300,800,*,UP,NDIF +S 1200,1700,1200,3500,200,5,DOWN,NTRANS +S 1800,1900,1800,3300,1000,*,UP,NDIF +S 3000,1900,3000,3300,1000,*,UP,NDIF +S 2400,1700,2400,3500,200,6,DOWN,NTRANS +S 1200,3500,1200,5500,200,*,UP,POLY +S 2400,3500,2400,5500,200,*,UP,POLY +S 3600,1700,3600,3500,200,7,DOWN,NTRANS +S 3600,3500,3600,5500,200,*,UP,POLY +S 4200,1900,4200,3300,1000,*,UP,NDIF +S 4800,1700,4800,3500,200,8,DOWN,NTRANS +S 4800,3500,4800,5500,200,*,UP,POLY +S 5300,1900,5300,3300,800,*,UP,NDIF +V 5400,9300,CONT_BODY_N,* +V 3300,700,CONT_BODY_P,* +V 2300,700,CONT_BODY_P,* +V 5400,3000,CONT_DIF_N,* +V 1800,7000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 600,7000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 600,9000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,9000,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 600,3000,CONT_DIF_N,* +V 600,2000,CONT_DIF_N,* +V 3000,3000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 1800,2000,CONT_DIF_N,* +V 1800,3000,CONT_DIF_N,* +V 4200,3000,CONT_DIF_N,* +V 4200,2000,CONT_DIF_N,* +V 5400,2000,CONT_DIF_N,* +V 7800,8000,CONT_DIF_P,* +V 7800,7000,CONT_DIF_P,* +V 6600,6000,CONT_DIF_P,an +V 6600,7000,CONT_DIF_P,an +V 7800,3000,CONT_DIF_N,* +V 7800,2200,CONT_DIF_N,* +V 6600,3000,CONT_DIF_N,an +V 3000,4900,CONT_POLY,* +V 1800,6200,CONT_DIF_P,* +V 4200,6200,CONT_DIF_P,* +V 7000,4000,CONT_POLY,* +V 6600,2000,CONT_DIF_N,an +EOF diff --git a/pdks/symbolic/msxlib/cells/bf1_x8.vbe b/pdks/symbolic/msxlib/cells/bf1_x8.vbe new file mode 100644 index 000000000..9d99611d1 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_x8.vbe @@ -0,0 +1,26 @@ +ENTITY bf1_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 9000; + CONSTANT cin_a : NATURAL := 11; + CONSTANT rdown_a_z : NATURAL := 320; + CONSTANT rup_a_z : NATURAL := 410; + CONSTANT tpll_a_z : NATURAL := 84; + CONSTANT tphh_a_z : NATURAL := 68; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1_x8; + +ARCHITECTURE behaviour_data_flow OF bf1_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1_x8" + SEVERITY WARNING; + z <= a after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/bf1_y05.ap b/pdks/symbolic/msxlib/cells/bf1_y05.ap new file mode 100644 index 000000000..d82bc1945 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_y05.ap @@ -0,0 +1,55 @@ +V ALLIANCE : 6 +H bf1_y05,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 3000,4000,ref_ref,a_40 +R 3000,6000,ref_ref,a_60 +R 3000,5000,ref_ref,a_50 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,LEFT,PTIE +S 1600,2300,1600,2700,200,*,UP,POLY +S 1600,2700,1600,3300,200,2z,DOWN,NTRANS +S 1200,2900,1200,3100,400,*,DOWN,NDIF +S 1000,2900,1000,7100,400,*,UP,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 2200,1900,2200,3100,600,*,UP,NDIF +S 2000,3000,3500,3000,400,*,LEFT,ALU1 +S 2000,7000,3500,7000,400,*,RIGHT,ALU1 +S 2200,7900,2200,9300,400,*,UP,ALU1 +S 2200,700,2200,2100,400,*,UP,ALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,4000,5000,10000,bf1_y05,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 3000,3900,3000,6100,400,*,DOWN,ALU1 +S 3000,4000,3000,6000,400,a,DOWN,CALU1 +S 2000,3000,2000,7000,400,*,UP,ALU1 +S 2800,2700,2800,3300,200,2a,DOWN,NTRANS +S 2800,2300,2800,2700,200,*,UP,POLY +S 3200,6900,3200,7700,400,*,UP,PDIF +S 2800,6700,2800,7900,200,1a,UP,PTRANS +S 1200,6900,1200,7700,400,*,UP,PDIF +S 1600,6700,1600,7900,200,1z,UP,PTRANS +S 2200,6900,2200,8100,600,*,DOWN,PDIF +S 1600,3300,1600,6700,200,*,UP,POLY +S 2800,3300,2800,6700,200,*,UP,POLY +S 1600,7900,1600,8300,200,*,DOWN,POLY +S 2800,7900,2800,8300,200,*,DOWN,POLY +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 1000,3000,CONT_DIF_N,* +V 3400,3000,CONT_DIF_N,an +V 3400,7000,CONT_DIF_P,an +V 2200,8000,CONT_DIF_P,* +V 2200,2000,CONT_DIF_N,* +V 3000,4700,CONT_POLY,* +V 2000,4700,CONT_POLY,an +V 1000,7000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/bf1_y05.vbe b/pdks/symbolic/msxlib/cells/bf1_y05.vbe new file mode 100644 index 000000000..9d7eeb6bb --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_y05.vbe @@ -0,0 +1,26 @@ +ENTITY bf1_y05 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3810; + CONSTANT rup_a_z : NATURAL := 4940; + CONSTANT tpll_a_z : NATURAL := 78; + CONSTANT tphh_a_z : NATURAL := 66; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1_y05; + +ARCHITECTURE behaviour_data_flow OF bf1_y05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1_y05" + SEVERITY WARNING; + z <= a after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/bf1_y1.ap b/pdks/symbolic/msxlib/cells/bf1_y1.ap new file mode 100644 index 000000000..1a88daca8 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_y1.ap @@ -0,0 +1,57 @@ +V ALLIANCE : 6 +H bf1_y1,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 3000,4000,ref_ref,a_40 +R 3000,6000,ref_ref,a_60 +R 3000,5000,ref_ref,a_50 +S 1100,700,1900,700,600,*,LEFT,PTIE +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1600,3300,1600,6300,200,*,UP,POLY +S 1000,2900,1000,7500,400,*,UP,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 1600,1900,1600,2300,200,*,UP,POLY +S 1600,2300,1600,3300,200,2z,DOWN,NTRANS +S 1200,2500,1200,3100,400,*,DOWN,NDIF +S 2200,1900,2200,3100,600,*,UP,NDIF +S 1600,8300,1600,8700,200,*,DOWN,POLY +S 2200,6500,2200,8100,600,*,DOWN,PDIF +S 1000,6500,1000,7300,600,*,UP,PDIF +S 1600,6300,1600,8300,200,1z,UP,PTRANS +S 1200,6500,1200,8100,400,*,UP,PDIF +S 2000,3000,3500,3000,400,*,LEFT,ALU1 +S 2000,7000,3500,7000,400,*,RIGHT,ALU1 +S 2200,7900,2200,9300,400,*,UP,ALU1 +S 2200,700,2200,2100,400,*,UP,ALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,4000,5000,10000,bf1_y1,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 3000,3900,3000,6100,400,*,DOWN,ALU1 +S 3000,4000,3000,6000,400,a,DOWN,CALU1 +S 2000,3000,2000,7000,400,*,UP,ALU1 +S 2800,2700,2800,3300,200,2a,DOWN,NTRANS +S 2800,2300,2800,2700,200,*,UP,POLY +S 3200,6900,3200,7700,400,*,UP,PDIF +S 2800,6700,2800,7900,200,1a,UP,PTRANS +S 2800,3300,2800,6700,200,*,UP,POLY +S 2800,7900,2800,8300,200,*,DOWN,POLY +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 1000,3000,CONT_DIF_N,* +V 1000,6600,CONT_DIF_P,* +V 1000,7400,CONT_DIF_P,* +V 3400,3000,CONT_DIF_N,an +V 3400,7000,CONT_DIF_P,an +V 2200,8000,CONT_DIF_P,* +V 2200,2000,CONT_DIF_N,* +V 3000,4700,CONT_POLY,* +V 2000,4700,CONT_POLY,an +EOF diff --git a/pdks/symbolic/msxlib/cells/bf1_y1.vbe b/pdks/symbolic/msxlib/cells/bf1_y1.vbe new file mode 100644 index 000000000..c63f06772 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_y1.vbe @@ -0,0 +1,26 @@ +ENTITY bf1_y1 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 2290; + CONSTANT rup_a_z : NATURAL := 2960; + CONSTANT tpll_a_z : NATURAL := 87; + CONSTANT tphh_a_z : NATURAL := 72; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1_y1; + +ARCHITECTURE behaviour_data_flow OF bf1_y1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1_y1" + SEVERITY WARNING; + z <= a after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/bf1_y2.ap b/pdks/symbolic/msxlib/cells/bf1_y2.ap new file mode 100644 index 000000000..0692c2bc3 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_y2.ap @@ -0,0 +1,59 @@ +V ALLIANCE : 6 +H bf1_y2,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 3000,4000,ref_ref,a_40 +R 3000,6000,ref_ref,a_60 +R 3000,5000,ref_ref,a_50 +R 1000,2000,ref_ref,z_20 +S 1100,700,1900,700,600,*,LEFT,PTIE +S 2800,3300,2800,6700,200,*,UP,POLY +S 2800,6700,2800,7900,200,1a,UP,PTRANS +S 3200,6900,3200,7700,400,*,UP,PDIF +S 2000,3000,3500,3000,400,*,LEFT,ALU1 +S 2000,7000,3500,7000,400,*,RIGHT,ALU1 +S 2200,1900,2200,3400,600,*,UP,NDIF +S 1600,9300,1600,9700,200,*,DOWN,POLY +S 2200,5700,2200,9100,600,*,DOWN,PDIF +S 2200,7900,2200,9300,400,*,UP,ALU1 +S 1200,5700,1200,9100,400,*,UP,PDIF +S 1200,1900,1200,3400,400,*,DOWN,NDIF +S 1600,3600,1600,5500,200,*,UP,POLY +S 1600,1300,1600,1700,200,*,UP,POLY +S 2200,700,2200,2100,400,*,UP,ALU1 +S 1000,1900,1000,7100,400,*,UP,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,4000,5000,10000,bf1_y2,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 3000,3900,3000,6100,400,*,DOWN,ALU1 +S 3000,4000,3000,6000,400,a,DOWN,CALU1 +S 2000,3000,2000,7000,400,*,UP,ALU1 +S 1000,5700,1000,6500,600,*,UP,PDIF +S 1000,2900,1000,3310,600,*,UP,NDIF +S 1600,5500,1600,9300,200,1z,UP,PTRANS +S 1600,1700,1600,3600,200,2z,DOWN,NTRANS +S 2800,2700,2800,3300,200,2a,DOWN,NTRANS +S 2800,2300,2800,2700,200,*,UP,POLY +S 2800,7900,2800,8300,200,*,DOWN,POLY +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 3300,9300,CONT_BODY_N,* +V 3400,3000,CONT_DIF_N,an +V 3400,7000,CONT_DIF_P,an +V 2200,8000,CONT_DIF_P,* +V 2200,9000,CONT_DIF_P,* +V 2200,2000,CONT_DIF_N,* +V 3000,4700,CONT_POLY,* +V 2000,4700,CONT_POLY,an +V 1000,5800,CONT_DIF_P,* +V 1000,6600,CONT_DIF_P,* +V 1000,3300,CONT_DIF_N,* +V 1000,2500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/bf1_y2.vbe b/pdks/symbolic/msxlib/cells/bf1_y2.vbe new file mode 100644 index 000000000..adcc7172b --- /dev/null +++ b/pdks/symbolic/msxlib/cells/bf1_y2.vbe @@ -0,0 +1,26 @@ +ENTITY bf1_y2 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 2; + CONSTANT rdown_a_z : NATURAL := 1210; + CONSTANT rup_a_z : NATURAL := 1560; + CONSTANT tpll_a_z : NATURAL := 106; + CONSTANT tphh_a_z : NATURAL := 87; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1_y2; + +ARCHITECTURE behaviour_data_flow OF bf1_y2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1_y2" + SEVERITY WARNING; + z <= a after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/cgi2_x05.ap b/pdks/symbolic/msxlib/cells/cgi2_x05.ap new file mode 100644 index 000000000..817c429f5 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2_x05.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H cgi2_x05,P, 8/ 8/2014,100 +A 0,0,7000,10000 +R 4000,6000,ref_ref,z_60 +R 6000,4000,ref_ref,b_40 +R 5000,4000,ref_ref,b_40 +R 6000,7000,ref_ref,c_70 +R 5000,7000,ref_ref,c_70 +R 5000,6000,ref_ref,c_60 +R 3000,3000,ref_ref,z_30 +R 1000,6000,ref_ref,a_60 +R 1000,5000,ref_ref,a_50 +R 6000,6000,ref_ref,b_60 +R 3000,6000,ref_ref,z_60 +R 3000,5000,ref_ref,z_50 +R 3000,4000,ref_ref,z_40 +R 4000,3000,ref_ref,z_30 +R 4000,7000,ref_ref,z_70 +R 2000,5000,ref_ref,a_50 +R 4000,4000,ref_ref,b_40 +R 6000,5000,ref_ref,b_50 +R 5000,5000,ref_ref,c_50 +R 1000,4000,ref_ref,a_40 +S 5100,700,5900,700,600,*,RIGHT,PTIE +S 4100,9300,4900,9300,600,*,RIGHT,NTIE +S 2000,6500,2000,8100,600,*,UP,PDIF +S 800,7000,800,8100,400,*,UP,ALU1 +S 3000,7000,3000,8000,400,*,UP,ALU1 +S 800,7000,3000,7000,400,*,RIGHT,ALU1 +S 2000,7900,2000,9300,400,*,DOWN,ALU1 +S 3000,8000,5300,8000,400,*,RIGHT,ALU1 +S 3000,6000,4000,6000,600,*,RIGHT,ALU1 +S 4000,5900,4000,7100,400,*,UP,ALU1 +S 3000,2900,3000,6100,400,*,UP,ALU1 +S 3000,3000,3000,6000,400,z,DOWN,CALU1 +S 4000,6000,4000,7000,400,z,DOWN,CALU1 +S 1400,1300,1400,1700,200,*,DOWN,POLY +S 700,2000,5200,2000,400,*,RIGHT,ALU1 +S 1400,2600,1400,6300,200,*,UP,POLY +S 1400,1700,1400,2600,200,07,UP,NTRANS +S 1000,1900,1000,2400,400,*,DOWN,NDIF +S 6400,7900,6400,9300,400,*,UP,ALU1 +S 6400,6500,6400,8100,600,*,DOWN,PDIF +S 1400,8300,1400,8700,200,*,DOWN,POLY +S 2600,8300,2600,8700,200,*,DOWN,POLY +S 3400,8300,3400,8700,200,*,DOWN,POLY +S 4600,8300,4600,8700,200,*,DOWN,POLY +S 5800,8300,5800,8700,200,*,DOWN,POLY +S 2600,2100,2600,2500,200,*,DOWN,POLY +S 6400,700,6400,3100,400,*,DOWN,ALU1 +S 5200,2000,5200,3100,400,*,UP,ALU1 +S 5800,2100,5800,2500,200,*,DOWN,POLY +S 4600,2100,4600,2500,200,*,DOWN,POLY +S 3400,2100,3400,2500,200,*,DOWN,POLY +S 1000,5000,2100,5000,600,*,LEFT,ALU1 +S 1400,5000,2600,5000,600,*,RIGHT,POLY +S 5800,3400,5800,6300,200,*,UP,POLY +S 4600,3400,4600,6300,200,*,UP,POLY +S 2600,3400,2600,6300,200,*,UP,POLY +S 3400,3400,3400,6300,200,*,UP,POLY +S 2600,2500,2600,3400,200,06,UP,NTRANS +S 3000,2700,3000,3200,600,n3,UP,NDIF +S 3400,2500,3400,3400,200,08,UP,NTRANS +S 4000,2700,4000,3200,1000,*,UP,NDIF +S 4600,2500,4600,3400,200,10,UP,NTRANS +S 5200,2700,5200,3200,1000,*,UP,NDIF +S 5800,2500,5800,3400,200,09,UP,NTRANS +S 6400,2700,6400,3200,600,*,UP,NDIF +S 3800,4000,6000,4000,600,*,RIGHT,ALU1 +S 6000,4000,6000,6100,400,*,DOWN,ALU1 +S 5000,4900,5000,7000,400,*,UP,ALU1 +S 5000,7100,6100,7100,400,*,LEFT,ALU1 +S 5000,7000,6100,7000,400,*,LEFT,ALU1 +S 5000,5000,5000,7000,400,c,DOWN,CALU1 +S 6000,4000,6000,6000,400,b,UP,CALU1 +S 3000,2900,4100,2900,400,*,RIGHT,ALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,5000,7000,5000,10000,cgi2_x05,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 3000,3000,4100,3000,400,*,RIGHT,ALU1 +S 5800,6300,5800,8300,200,04,DOWN,PTRANS +S 4600,6300,4600,8300,200,05,DOWN,PTRANS +S 5200,6500,5200,8100,1000,*,UP,PDIF +S 3000,6500,3000,8100,600,n1,DOWN,PDIF +S 2600,6300,2600,8300,200,01,DOWN,PTRANS +S 3400,6300,3400,8300,200,03,DOWN,PTRANS +S 1400,6300,1400,8300,200,02,DOWN,PTRANS +S 1000,6500,1000,8100,400,*,UP,PDIF +S 4000,6500,4000,8100,1000,*,UP,PDIF +S 2000,5000,2000,5000,400,a,LEFT,CALU1 +S 4000,3000,4000,3000,400,z,LEFT,CALU1 +S 4000,4000,4000,4000,400,b,LEFT,CALU1 +S 5000,4000,5000,4000,400,b,LEFT,CALU1 +S 6000,7000,6000,7000,400,c,LEFT,CALU1 +S 2000,900,2000,3200,600,*,UP,NDIF +S 1000,4000,1000,6000,400,a,DOWN,CALU1 +S 1000,3900,1000,6100,400,*,DOWN,ALU1 +S 800,7300,800,7900,600,*,UP,PDIF +V 5000,700,CONT_BODY_P,* +V 6000,700,CONT_BODY_P,* +V 5000,9300,CONT_BODY_N,* +V 4000,9300,CONT_BODY_N,* +V 2000,8000,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,n4 +V 6400,8000,CONT_DIF_P,* +V 5200,3000,CONT_DIF_N,n4 +V 4000,3000,CONT_DIF_N,* +V 2000,5000,CONT_POLY,* +V 3800,4000,CONT_POLY,* +V 6000,5000,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 4000,7000,CONT_DIF_P,* +V 2000,1000,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,n2 +V 5200,8000,CONT_DIF_P,n2 +V 6400,3000,CONT_DIF_N,* +V 800,7200,CONT_DIF_P,n2 +EOF diff --git a/pdks/symbolic/msxlib/cells/cgi2_x05.vbe b/pdks/symbolic/msxlib/cells/cgi2_x05.vbe new file mode 100644 index 000000000..889ec26dc --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2_x05.vbe @@ -0,0 +1,38 @@ +ENTITY cgi2_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_a : NATURAL := 6; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_c : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 4120; + CONSTANT rdown_b_z : NATURAL := 4130; + CONSTANT rdown_c_z : NATURAL := 4100; + CONSTANT rup_a_z : NATURAL := 5810; + CONSTANT rup_b_z : NATURAL := 5850; + CONSTANT rup_c_z : NATURAL := 5850; + CONSTANT tphl_c_z : NATURAL := 53; + CONSTANT tphl_b_z : NATURAL := 62; + CONSTANT tplh_a_z : NATURAL := 81; + CONSTANT tplh_c_z : NATURAL := 58; + CONSTANT tplh_b_z : NATURAL := 75; + CONSTANT tphl_a_z : NATURAL := 61; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END cgi2_x05; + +ARCHITECTURE behaviour_data_flow OF cgi2_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on cgi2_x05" + SEVERITY WARNING; + z <= not((b or (a and c)) and (a or c)) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/cgi2_x1.ap b/pdks/symbolic/msxlib/cells/cgi2_x1.ap new file mode 100644 index 000000000..5dd80f332 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2_x1.ap @@ -0,0 +1,128 @@ +V ALLIANCE : 6 +H cgi2_x1,P, 8/ 8/2014,100 +A 0,0,7000,10000 +R 4000,5000,ref_ref,b_50 +R 4000,6000,ref_ref,z_60 +R 1000,6000,ref_ref,a_60 +R 1000,5000,ref_ref,a_50 +R 6000,6000,ref_ref,b_60 +R 3000,6000,ref_ref,z_60 +R 3000,5000,ref_ref,z_50 +R 3000,4000,ref_ref,z_40 +R 4000,3000,ref_ref,z_30 +R 4000,7000,ref_ref,z_70 +R 1000,4000,ref_ref,a_40 +R 2000,5000,ref_ref,a_50 +R 4000,4000,ref_ref,b_40 +R 6000,5000,ref_ref,b_50 +R 5000,5000,ref_ref,c_50 +R 3000,3000,ref_ref,z_30 +R 5000,6000,ref_ref,c_60 +R 5000,7000,ref_ref,c_70 +R 6000,7000,ref_ref,c_70 +R 5000,4000,ref_ref,b_40 +R 6000,4000,ref_ref,b_40 +S 5100,700,5900,700,600,*,RIGHT,PTIE +S 1400,9400,1400,9700,200,*,DOWN,POLY +S 2600,9400,2600,9700,200,*,DOWN,POLY +S 3400,9400,3400,9700,200,*,DOWN,POLY +S 4600,9400,4600,9700,200,*,DOWN,POLY +S 5800,9400,5800,9700,200,*,DOWN,POLY +S 1400,1300,1400,1700,200,*,DOWN,POLY +S 2600,1300,2600,1700,200,*,DOWN,POLY +S 3400,1300,3400,1700,200,*,DOWN,POLY +S 4600,1300,4600,1700,200,*,DOWN,POLY +S 5800,1300,5800,1700,200,*,DOWN,POLY +S 4000,4000,4000,5000,400,b,UP,CALU1 +S 3900,3900,3900,5100,600,*,UP,ALU1 +S 4000,4000,6000,4000,400,*,RIGHT,ALU1 +S 4000,3900,6000,3900,400,*,RIGHT,ALU1 +S 6000,4000,6000,6100,400,*,DOWN,ALU1 +S 700,2000,5200,2000,400,*,RIGHT,ALU1 +S 2000,900,2000,3300,600,*,UP,NDIF +S 1400,1700,1400,3500,200,07,UP,NTRANS +S 1000,1900,1000,3300,400,*,DOWN,NDIF +S 2000,7900,2000,9300,400,*,DOWN,ALU1 +S 3000,8000,5300,8000,400,*,RIGHT,ALU1 +S 3000,7000,3000,8000,400,*,UP,ALU1 +S 1000,3900,1000,6100,400,*,DOWN,ALU1 +S 1000,4000,1000,6000,400,a,DOWN,CALU1 +S 5000,4900,5000,7000,600,*,UP,ALU1 +S 1400,3900,1400,5500,200,*,UP,POLY +S 2600,3500,2600,5500,200,*,UP,POLY +S 1400,4900,2600,4900,600,*,RIGHT,POLY +S 1000,4900,2100,4900,600,*,LEFT,ALU1 +S 4000,6000,4000,7100,400,*,UP,ALU1 +S 4000,6000,4000,7000,400,z,UP,CALU1 +S 3000,3000,3000,6000,400,*,UP,ALU1 +S 3000,3000,3000,6000,400,z,DOWN,CALU1 +S 3000,6000,4000,6000,600,*,RIGHT,ALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,7000,5000,10000,cgi2_x1,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 3000,3000,4100,3000,400,*,RIGHT,ALU1 +S 6400,5700,6400,9200,600,*,DOWN,PDIF +S 1000,5700,1000,9200,400,*,UP,PDIF +S 5200,5700,5200,9200,1000,*,UP,PDIF +S 4000,5700,4000,9200,1000,*,UP,PDIF +S 2000,5700,2000,9200,1000,*,UP,PDIF +S 2600,5500,2600,9400,200,01,DOWN,PTRANS +S 1400,5500,1400,9400,200,02,DOWN,PTRANS +S 3400,5500,3400,9400,200,03,DOWN,PTRANS +S 5800,5500,5800,9400,200,04,DOWN,PTRANS +S 4600,5500,4600,9400,200,05,DOWN,PTRANS +S 3000,5700,3000,9200,600,n1,DOWN,PDIF +S 6400,7900,6400,9300,400,*,UP,ALU1 +S 6400,1900,6400,3300,600,*,UP,NDIF +S 5800,1700,5800,3500,200,09,UP,NTRANS +S 5200,1900,5200,3300,1000,*,UP,NDIF +S 4600,1700,4600,3500,200,10,UP,NTRANS +S 4000,1900,4000,3300,1000,*,UP,NDIF +S 3400,1700,3400,3500,200,08,UP,NTRANS +S 3000,1900,3000,3300,600,n3,UP,NDIF +S 2600,1700,2600,3500,200,06,UP,NTRANS +S 5300,2000,5300,3100,400,*,UP,ALU1 +S 5200,2000,5200,3100,400,*,UP,ALU1 +S 6400,700,6400,3100,400,*,DOWN,ALU1 +S 3000,2900,4100,2900,400,*,RIGHT,ALU1 +S 5000,7000,6100,7000,400,*,LEFT,ALU1 +S 6000,4000,6000,6000,400,b,UP,CALU1 +S 3400,3500,3400,5500,200,*,UP,POLY +S 4600,3500,4600,5500,200,*,UP,POLY +S 5800,3500,5800,5500,200,*,UP,POLY +S 5000,5000,5000,7000,400,c,DOWN,CALU1 +S 800,7000,3000,7000,400,*,RIGHT,ALU1 +S 800,7000,800,8100,400,*,DOWN,ALU1 +S 800,7300,800,7900,600,*,DOWN,PDIF +S 2000,5000,2000,5000,400,a,LEFT,CALU1 +S 4000,3000,4000,3000,400,z,LEFT,CALU1 +S 5000,4000,5000,4000,400,b,LEFT,CALU1 +S 6000,7000,6000,7000,400,c,LEFT,CALU1 +S 800,2100,800,2700,600,*,UP,NDIF +S 800,2000,800,2800,600,*,DOWN,ALU1 +V 6000,700,CONT_BODY_P,* +V 5000,700,CONT_BODY_P,* +V 4000,7000,CONT_DIF_P,* +V 3800,4900,CONT_POLY,* +V 800,2000,CONT_DIF_N,n4 +V 2000,8000,CONT_DIF_P,* +V 4000,6000,CONT_DIF_P,* +V 2000,4900,CONT_POLY,* +V 6000,4900,CONT_POLY,* +V 5000,4900,CONT_POLY,* +V 4000,3000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 5200,8000,CONT_DIF_P,n2 +V 2000,9000,CONT_DIF_P,* +V 6400,9000,CONT_DIF_P,* +V 6400,8000,CONT_DIF_P,* +V 6400,2000,CONT_DIF_N,* +V 5200,2000,CONT_DIF_N,n4 +V 5200,3000,CONT_DIF_N,n4 +V 6400,3000,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,n2 +V 800,7200,CONT_DIF_P,n2 +V 800,2800,CONT_DIF_N,n4 +EOF diff --git a/pdks/symbolic/msxlib/cells/cgi2_x1.vbe b/pdks/symbolic/msxlib/cells/cgi2_x1.vbe new file mode 100644 index 000000000..161a55e56 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2_x1.vbe @@ -0,0 +1,38 @@ +ENTITY cgi2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_a : NATURAL := 12; + CONSTANT cin_b : NATURAL := 12; + CONSTANT cin_c : NATURAL := 6; + CONSTANT rdown_a_z : NATURAL := 2050; + CONSTANT rdown_b_z : NATURAL := 2060; + CONSTANT rdown_c_z : NATURAL := 2050; + CONSTANT rup_a_z : NATURAL := 2980; + CONSTANT rup_b_z : NATURAL := 3000; + CONSTANT rup_c_z : NATURAL := 3000; + CONSTANT tphl_c_z : NATURAL := 51; + CONSTANT tphl_b_z : NATURAL := 58; + CONSTANT tplh_a_z : NATURAL := 76; + CONSTANT tplh_c_z : NATURAL := 56; + CONSTANT tplh_b_z : NATURAL := 71; + CONSTANT tphl_a_z : NATURAL := 57; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END cgi2_x1; + +ARCHITECTURE behaviour_data_flow OF cgi2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on cgi2_x1" + SEVERITY WARNING; + z <= not((b or (a and c)) and (a or c)) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/cgi2_x2.ap b/pdks/symbolic/msxlib/cells/cgi2_x2.ap new file mode 100644 index 000000000..190441eb9 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2_x2.ap @@ -0,0 +1,214 @@ +V ALLIANCE : 6 +H cgi2_x2,P, 8/ 8/2014,100 +A 0,0,13000,10000 +R 1000,4000,ref_ref,a_50 +R 8000,2000,ref_ref,z_20 +R 5000,5000,ref_ref,b_50 +R 2000,3000,ref_ref,c_30 +R 6000,4000,ref_ref,b_40 +R 7000,4000,ref_ref,b_40 +R 8000,4000,ref_ref,b_40 +R 9000,4000,ref_ref,b_40 +R 5000,4000,ref_ref,b_40 +R 9000,6000,ref_ref,a_60 +R 1000,6000,ref_ref,a_60 +R 2000,7000,ref_ref,a_70 +R 3000,7000,ref_ref,a_70 +R 4000,7000,ref_ref,a_70 +R 5000,7000,ref_ref,a_70 +R 6000,7000,ref_ref,a_70 +R 7000,7000,ref_ref,a_70 +R 8000,7000,ref_ref,a_70 +R 8000,5000,ref_ref,a_50 +R 7000,5000,ref_ref,a_50 +R 9000,7000,ref_ref,a_70 +R 9000,5000,ref_ref,a_50 +R 6000,5000,ref_ref,a_50 +R 1000,5000,ref_ref,a_50 +R 7000,3000,ref_ref,z_30 +R 6000,3000,ref_ref,z_30 +R 5000,3000,ref_ref,z_30 +R 3000,3000,ref_ref,z_30 +R 4000,3000,ref_ref,z_30 +R 4000,4000,ref_ref,z_40 +R 4000,5000,ref_ref,z_50 +R 3000,6000,ref_ref,z_60 +R 4000,6000,ref_ref,z_60 +R 5000,6000,ref_ref,z_60 +R 6000,6000,ref_ref,z_60 +R 7000,6000,ref_ref,z_60 +R 10000,4000,ref_ref,b_40 +R 2000,5000,ref_ref,c_50 +R 2000,6000,ref_ref,c_60 +R 3000,5000,ref_ref,c_50 +R 2000,4000,ref_ref,c_40 +R 11000,5000,ref_ref,b_50 +R 11000,3000,ref_ref,b_30 +R 11000,4000,ref_ref,b_40 +S 11100,700,11900,700,600,*,RIGHT,PTIE +S 1000,3900,1000,7000,400,*,UP,ALU1 +S 5700,800,5700,3700,1200,*,UP,NDIF +S 5700,700,5700,2100,400,*,DOWN,ALU1 +S 5800,4600,6600,4600,200,*,LEFT,POLY +S 6600,3400,6600,4600,200,*,UP,POLY +S 6000,5000,6000,5700,200,*,DOWN,POLY +S 6600,1300,6600,1700,200,*,DOWN,POLY +S 6600,1700,6600,3400,200,7a,UP,NTRANS +S 7000,1900,7000,3200,400,n3b,UP,NDIF +S 7400,3400,7400,5300,200,*,UP,POLY +S 6800,5300,8000,5300,200,*,LEFT,POLY +S 8000,2000,8000,2000,400,z,LEFT,CALU1 +S 2900,3000,8000,3000,400,*,RIGHT,ALU1 +S 7400,1300,7400,1700,200,*,DOWN,POLY +S 7400,1700,7400,3400,200,7b,UP,NTRANS +S 8000,1900,8000,3200,600,*,DOWN,NDIF +S 8000,1900,8000,3000,400,*,DOWN,ALU1 +S 7800,3800,8600,3800,200,*,LEFT,POLY +S 8600,1300,8600,1700,200,*,DOWN,POLY +S 8600,1700,8600,3400,200,8b,UP,NTRANS +S 9000,1900,9000,3200,400,n3a,UP,NDIF +S 9400,3400,9400,5200,200,*,UP,POLY +S 8800,5000,8800,5700,200,*,DOWN,POLY +S 9400,1700,9400,3400,200,8a,UP,NTRANS +S 9400,1300,9400,1700,200,*,DOWN,POLY +S 10100,1900,10100,3200,600,*,UP,NDIF +S 10000,700,10000,3100,400,*,DOWN,ALU1 +S 5000,4000,5000,5000,400,b,UP,CALU1 +S 5000,4000,5000,5000,600,*,DOWN,ALU1 +S 2000,3000,2000,6000,400,c,DOWN,CALU1 +S 2000,2900,2000,6100,400,*,DOWN,ALU1 +S 1700,2000,4300,2000,400,*,RIGHT,ALU1 +S 6400,5900,6400,9200,400,n1b,UP,PDIF +S 8400,5900,8400,9200,400,n1a,UP,PDIF +S 4800,600,4800,3900,200,5b,UP,NTRANS +S 8000,5700,8000,9400,200,4b,DOWN,PTRANS +S 6800,5700,6800,9400,200,3b,DOWN,PTRANS +S 10000,5700,10000,9400,200,2b,DOWN,PTRANS +S 11200,5700,11200,9400,200,1b,DOWN,PTRANS +S 1200,600,1200,3900,200,5a,UP,NTRANS +S 8800,5700,8800,9400,200,4a,DOWN,PTRANS +S 6000,5700,6000,9400,200,3a,DOWN,PTRANS +S 4800,5700,4800,9400,200,2a,DOWN,PTRANS +S 1200,5700,1200,9400,200,1a,DOWN,PTRANS +S 3600,1700,3600,3400,200,4c,UP,NTRANS +S 2400,1700,2400,3400,200,3c,UP,NTRANS +S 3600,5700,3600,9400,200,2c,DOWN,PTRANS +S 2400,5700,2400,9400,200,1c,DOWN,PTRANS +S 11200,9400,11200,9700,200,*,DOWN,POLY +S 10000,9400,10000,9700,200,*,DOWN,POLY +S 8800,9400,8800,9700,200,*,DOWN,POLY +S 8000,9400,8000,9700,200,*,DOWN,POLY +S 6800,9400,6800,9700,200,*,DOWN,POLY +S 6000,9400,6000,9700,200,*,DOWN,POLY +S 4800,9400,4800,9700,200,*,DOWN,POLY +S 3600,9400,3600,9700,200,*,DOWN,POLY +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 1200,9400,1200,9700,200,*,DOWN,POLY +S 1200,300,1200,600,200,*,DOWN,POLY +S 3600,1300,3600,1700,200,*,DOWN,POLY +S 4800,300,4800,600,200,*,DOWN,POLY +S 600,700,600,3100,400,*,DOWN,ALU1 +S 11800,6900,11800,9300,400,*,UP,ALU1 +S 10600,6900,10600,8000,400,*,DOWN,ALU1 +S 1700,8000,10600,8000,400,*,RIGHT,ALU1 +S 600,7900,600,9300,400,*,UP,ALU1 +S 600,5900,600,9200,600,*,DOWN,PDIF +S 10600,5900,10600,9200,600,*,UP,PDIF +S 9400,5900,9400,9200,600,*,UP,PDIF +S 7400,5900,7400,9200,600,*,UP,PDIF +S 5400,5900,5400,9200,600,*,UP,PDIF +S 4200,5900,4200,9200,600,*,UP,PDIF +S 1800,5900,1800,9200,600,*,DOWN,PDIF +S 2400,3400,2400,5700,200,*,DOWN,POLY +S 3600,3400,3600,5700,200,*,DOWN,POLY +S 1200,3900,1200,5700,200,*,DOWN,POLY +S 4800,5300,6200,5300,200,*,RIGHT,POLY +S 10000,5200,10000,5700,200,*,DOWN,POLY +S 11200,5200,11200,5700,200,*,DOWN,POLY +S 10000,5200,11200,5200,200,*,LEFT,POLY +S 11900,5900,11900,9200,600,*,DOWN,PDIF +S 3000,5900,3000,9200,1000,*,UP,PDIF +S 4400,800,4400,3700,400,*,DOWN,NDIF +S 4200,1900,4200,3200,600,*,UP,NDIF +S 1600,800,1600,3700,400,*,UP,NDIF +S 1800,1900,1800,3200,600,*,UP,NDIF +S 600,800,600,3700,600,*,UP,NDIF +S 3000,1900,3000,3200,600,*,DOWN,NDIF +S 9000,4000,9000,4000,400,b,LEFT,CALU1 +S 8000,4000,8000,4000,400,b,LEFT,CALU1 +S 7000,4000,7000,4000,400,b,LEFT,CALU1 +S 6000,4000,6000,4000,400,b,LEFT,CALU1 +S 9000,5000,9000,7000,600,*,UP,ALU1 +S 9000,5000,9000,7000,400,a,UP,CALU1 +S 6000,5000,6000,5000,400,a,LEFT,CALU1 +S 8000,5000,8000,5000,400,a,LEFT,CALU1 +S 7000,5000,7000,5000,400,a,LEFT,CALU1 +S 5900,5000,9000,5000,400,*,RIGHT,ALU1 +S 8000,7000,8000,7000,400,a,LEFT,CALU1 +S 7000,7000,7000,7000,400,a,LEFT,CALU1 +S 6000,7000,6000,7000,400,a,LEFT,CALU1 +S 5000,7000,5000,7000,400,a,LEFT,CALU1 +S 4000,7000,4000,7000,400,a,LEFT,CALU1 +S 3000,7000,3000,7000,400,a,LEFT,CALU1 +S 2000,7000,2000,7000,400,a,LEFT,CALU1 +S 2900,6000,7500,6000,400,*,RIGHT,ALU1 +S 5000,6000,5000,6000,400,z,LEFT,CALU1 +S 6000,6000,6000,6000,400,z,LEFT,CALU1 +S 7000,6000,7000,6000,400,z,LEFT,CALU1 +S 0,5000,13000,5000,10000,cgi2_x2,LEFT,TALU8 +S 0,2200,13000,2200,5200,*,LEFT,PWELL +S 0,7600,13000,7600,5600,*,LEFT,NWELL +S 0,600,13000,600,1200,vss,RIGHT,CALU1 +S 0,9400,13000,9400,1200,vdd,RIGHT,CALU1 +S 5000,3000,5000,3000,400,z,LEFT,CALU1 +S 3000,6000,3000,6000,400,z,LEFT,CALU1 +S 3000,3000,3000,3000,400,z,LEFT,CALU1 +S 6000,3000,6000,3000,400,z,LEFT,CALU1 +S 7000,3000,7000,3000,400,z,LEFT,CALU1 +S 4000,3000,4000,6000,400,*,DOWN,ALU1 +S 4000,3000,4000,6000,400,z,DOWN,CALU1 +S 3000,5000,3000,5000,400,c,LEFT,CALU1 +S 2400,5000,3600,5000,600,*,RIGHT,POLY +S 2000,5000,3100,5000,400,*,LEFT,ALU1 +S 1000,7000,9000,7000,400,*,RIGHT,ALU1 +S 2400,1300,2400,1700,200,*,DOWN,POLY +S 11000,3000,11000,5000,400,b,DOWN,CALU1 +S 11000,2900,11000,5100,400,*,DOWN,ALU1 +S 10000,4000,10000,4000,400,b,LEFT,CALU1 +S 4900,4000,11000,4000,400,*,RIGHT,ALU1 +S 1000,4000,1000,6000,400,a,UP,CALU1 +V 12000,700,CONT_BODY_P,* +V 11000,700,CONT_BODY_P,* +V 5700,1000,CONT_DIF_N,* +V 5700,2000,CONT_DIF_N,* +V 7600,4000,CONT_POLY,* +V 8000,2800,CONT_DIF_N,* +V 8000,2000,CONT_DIF_N,* +V 10000,3000,CONT_DIF_N,* +V 10000,2000,CONT_DIF_N,* +V 1800,2000,CONT_DIF_N,n4 +V 9400,9000,CONT_DIF_P,* +V 600,3000,CONT_DIF_N,* +V 600,2000,CONT_DIF_N,* +V 11800,7000,CONT_DIF_P,* +V 10600,7800,CONT_DIF_P,n2 +V 10600,7000,CONT_DIF_P,n2 +V 600,8000,CONT_DIF_P,* +V 5000,4500,CONT_POLY,* +V 9000,5000,CONT_POLY,* +V 6000,5000,CONT_POLY,* +V 3000,6000,CONT_DIF_P,* +V 11800,9000,CONT_DIF_P,* +V 11800,8000,CONT_DIF_P,* +V 7400,6000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,n2 +V 5400,9000,CONT_DIF_P,* +V 1800,8000,CONT_DIF_P,n2 +V 4200,2000,CONT_DIF_N,n4 +V 3000,3000,CONT_DIF_N,* +V 600,1000,CONT_DIF_N,* +V 600,9000,CONT_DIF_P,* +V 3000,5000,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 11000,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/cgi2_x2.vbe b/pdks/symbolic/msxlib/cells/cgi2_x2.vbe new file mode 100644 index 000000000..f45887b82 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2_x2.vbe @@ -0,0 +1,38 @@ +ENTITY cgi2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 13000; + CONSTANT cin_a : NATURAL := 24; + CONSTANT cin_b : NATURAL := 21; + CONSTANT cin_c : NATURAL := 11; + CONSTANT rdown_a_z : NATURAL := 1090; + CONSTANT rdown_b_z : NATURAL := 1100; + CONSTANT rdown_c_z : NATURAL := 1100; + CONSTANT rup_a_z : NATURAL := 1570; + CONSTANT rup_b_z : NATURAL := 1580; + CONSTANT rup_c_z : NATURAL := 1580; + CONSTANT tphl_c_z : NATURAL := 52; + CONSTANT tphl_b_z : NATURAL := 58; + CONSTANT tplh_a_z : NATURAL := 77; + CONSTANT tplh_c_z : NATURAL := 57; + CONSTANT tplh_b_z : NATURAL := 70; + CONSTANT tphl_a_z : NATURAL := 58; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END cgi2_x2; + +ARCHITECTURE behaviour_data_flow OF cgi2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on cgi2_x2" + SEVERITY WARNING; + z <= not((b or (a and c)) and (a or c)) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/cgi2a_x05.ap b/pdks/symbolic/msxlib/cells/cgi2a_x05.ap new file mode 100644 index 000000000..d4dd19782 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2a_x05.ap @@ -0,0 +1,138 @@ +V ALLIANCE : 6 +H cgi2a_x05,P, 8/ 8/2014,100 +A 0,0,8000,10000 +R 7000,7000,ref_ref,a_70 +R 6000,7000,ref_ref,a_70 +R 6000,6000,ref_ref,a_60 +R 6000,5000,ref_ref,a_50 +R 5000,7000,ref_ref,c_70 +R 4000,5000,ref_ref,c_50 +R 5000,6000,ref_ref,c_60 +R 3000,3000,ref_ref,z_30 +R 4000,7000,ref_ref,z_70 +R 3000,4000,ref_ref,z_40 +R 3000,5000,ref_ref,z_50 +R 3000,6000,ref_ref,z_60 +R 4000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,b_40 +R 2000,5000,ref_ref,b_50 +R 1000,5000,ref_ref,b_50 +R 1000,6000,ref_ref,b_60 +R 5000,5000,ref_ref,c_50 +R 4000,3000,ref_ref,z_30 +S 4100,700,4900,700,600,*,LEFT,PTIE +S 1100,9300,1900,9300,600,*,LEFT,NTIE +S 1400,1300,1400,1700,200,*,DOWN,POLY +S 1400,2600,1400,5200,200,*,UP,POLY +S 1400,1700,1400,2600,200,3b,UP,NTRANS +S 1000,1900,1000,2400,400,*,DOWN,NDIF +S 2400,4800,2400,6300,200,*,UP,POLY +S 1800,5000,2400,5000,600,*,RIGHT,POLY +S 6800,3800,6800,5700,200,*,DOWN,POLY +S 5600,3700,5600,6300,200,*,UP,POLY +S 4400,5100,4400,6300,200,*,DOWN,POLY +S 3200,4000,3200,6300,200,*,UP,POLY +S 6400,700,6400,1500,400,*,UP,ALU1 +S 6300,1300,6300,3500,400,*,UP,NDIF +S 6800,2000,6800,2400,200,*,DOWN,POLY +S 7400,3300,7400,6100,400,*,UP,ALU1 +S 6800,2400,6800,3700,200,2a,UP,NTRANS +S 7200,2600,7200,3500,400,*,UP,NDIF +S 2600,2000,2600,2400,200,*,DOWN,POLY +S 3400,2000,3400,2400,200,*,DOWN,POLY +S 4600,2000,4600,2400,200,*,DOWN,POLY +S 5800,2000,5800,2400,200,*,DOWN,POLY +S 700,2000,5300,2000,400,*,RIGHT,ALU1 +S 5200,2000,5200,2700,600,*,UP,ALU1 +S 2600,2400,2600,3300,200,4b,UP,NTRANS +S 3000,2600,3000,3100,600,n3,UP,NDIF +S 3400,2400,3400,3300,200,5a,UP,NTRANS +S 4000,2600,4000,3100,1000,*,UP,NDIF +S 5800,2400,5800,3300,200,6a,UP,NTRANS +S 4600,2400,4600,3300,200,2c,UP,NTRANS +S 5200,2600,5200,3100,1000,*,UP,NDIF +S 6200,7900,6200,9300,400,*,UP,ALU1 +S 6200,5900,6200,8100,600,*,DOWN,PDIF +S 6000,4800,6000,7100,400,*,DOWN,ALU1 +S 6000,5000,6000,7000,400,a,DOWN,CALU1 +S 7000,7000,7000,7000,400,a,LEFT,CALU1 +S 6000,7000,7000,7000,600,*,LEFT,ALU1 +S 4000,6000,4000,7000,400,z,UP,CALU1 +S 2000,5000,2000,5000,400,b,LEFT,CALU1 +S 1000,4000,1000,6000,400,b,DOWN,CALU1 +S 3400,3300,3400,4100,200,*,UP,POLY +S 5800,3300,5800,4100,200,*,UP,POLY +S 4600,3300,4600,5100,200,*,UP,POLY +S 3000,2900,3000,6000,400,*,UP,ALU1 +S 3000,3000,4100,3000,400,*,RIGHT,ALU1 +S 3000,2900,4100,2900,400,*,RIGHT,ALU1 +S 2000,900,2000,3100,600,*,UP,NDIF +S 6000,4900,6600,4900,600,*,LEFT,ALU1 +S 5000,4900,5000,7100,400,*,DOWN,ALU1 +S 4000,5000,5000,5000,600,*,LEFT,ALU1 +S 5000,5000,5000,7000,400,c,UP,CALU1 +S 2800,8000,5100,8000,400,*,RIGHT,ALU1 +S 3800,3900,7400,3900,600,*,RIGHT,ALU1 +S 1800,7900,1800,9300,400,*,DOWN,ALU1 +S 2800,7000,2800,8000,400,*,UP,ALU1 +S 600,7000,600,8100,400,*,DOWN,ALU1 +S 600,7000,2800,7000,400,*,RIGHT,ALU1 +S 600,7300,600,7900,600,*,DOWN,PDIF +S 1000,3900,1000,6100,400,*,DOWN,ALU1 +S 1000,5000,2000,5000,600,*,LEFT,ALU1 +S 0,5000,8000,5000,10000,cgi2a_x05,LEFT,TALU8 +S 0,2200,8000,2200,5200,*,LEFT,PWELL +S 0,7600,8000,7600,5600,*,LEFT,NWELL +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 3000,3000,3000,6000,400,z,DOWN,CALU1 +S 3900,6000,3900,7100,600,*,UP,ALU1 +S 3000,6000,4000,6000,600,*,RIGHT,ALU1 +S 4000,3000,4000,3000,400,z,LEFT,CALU1 +S 7200,5900,7200,8100,400,*,DOWN,PDIF +S 6800,5700,6800,8300,200,1a,DOWN,PTRANS +S 6200,5900,6200,8100,600,*,DOWN,PDIF +S 5600,6300,5600,8300,200,4a,DOWN,PTRANS +S 5000,6500,5000,8100,1000,*,UP,PDIF +S 4400,6300,4400,8300,200,1c,DOWN,PTRANS +S 3200,6300,3200,8300,200,3a,DOWN,PTRANS +S 3800,6500,3800,8100,1000,*,UP,PDIF +S 1800,6500,1800,8100,1000,*,UP,PDIF +S 1200,6300,1200,8300,200,1b,DOWN,PTRANS +S 2400,6300,2400,8300,200,2b,DOWN,PTRANS +S 800,6500,800,8100,400,*,UP,PDIF +S 2800,6500,2800,8100,600,n1,DOWN,PDIF +S 3200,8300,3200,8700,200,*,DOWN,POLY +S 4400,8300,4400,8700,200,*,DOWN,POLY +S 5600,8300,5600,8700,200,*,DOWN,POLY +S 6800,8300,6800,8700,200,*,DOWN,POLY +S 1200,8300,1200,8700,200,*,DOWN,POLY +S 2400,8300,2400,8700,200,*,DOWN,POLY +S 4000,5000,4000,5000,400,c,LEFT,CALU1 +S 2600,3300,2600,5200,200,*,UP,POLY +S 1200,4800,1200,6300,200,*,UP,POLY +S 1200,5000,2600,5000,600,*,LEFT,POLY +S 3200,3900,4000,3900,600,*,LEFT,POLY +V 5000,700,CONT_BODY_P,* +V 4000,700,CONT_BODY_P,* +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 800,2000,CONT_DIF_N,n4 +V 1800,5000,CONT_POLY,* +V 6400,1400,CONT_DIF_N,* +V 7400,3400,CONT_DIF_N,an +V 5200,2700,CONT_DIF_N,n4 +V 6200,8000,CONT_DIF_P,* +V 5600,3900,CONT_POLY,an +V 4000,3000,CONT_DIF_N,* +V 5000,8000,CONT_DIF_P,n2 +V 3800,3900,CONT_POLY,an +V 2000,1000,CONT_DIF_N,* +V 6600,4900,CONT_POLY,* +V 1800,8000,CONT_DIF_P,* +V 3800,7000,CONT_DIF_P,* +V 600,7200,CONT_DIF_P,n2 +V 600,8000,CONT_DIF_P,n2 +V 7400,6000,CONT_DIF_P,an +V 4600,5100,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/cgi2a_x05.vbe b/pdks/symbolic/msxlib/cells/cgi2a_x05.vbe new file mode 100644 index 000000000..2695f96b5 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2a_x05.vbe @@ -0,0 +1,38 @@ +ENTITY cgi2a_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_c : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 4130; + CONSTANT rdown_b_z : NATURAL := 4120; + CONSTANT rdown_c_z : NATURAL := 4110; + CONSTANT rup_a_z : NATURAL := 5840; + CONSTANT rup_b_z : NATURAL := 5820; + CONSTANT rup_c_z : NATURAL := 5850; + CONSTANT tphl_c_z : NATURAL := 54; + CONSTANT tphl_b_z : NATURAL := 62; + CONSTANT tphh_a_z : NATURAL := 103; + CONSTANT tplh_c_z : NATURAL := 59; + CONSTANT tplh_b_z : NATURAL := 81; + CONSTANT tpll_a_z : NATURAL := 107; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END cgi2a_x05; + +ARCHITECTURE behaviour_data_flow OF cgi2a_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on cgi2a_x05" + SEVERITY WARNING; + z <= not((not(a) or (b and c)) and (b or c)) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/cgi2a_x1.ap b/pdks/symbolic/msxlib/cells/cgi2a_x1.ap new file mode 100644 index 000000000..791922e0d --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2a_x1.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H cgi2a_x1,P, 8/ 8/2014,100 +A 0,0,8000,10000 +R 4000,5000,ref_ref,z_50 +R 4000,4000,ref_ref,z_40 +R 6000,7000,ref_ref,a_70 +R 6000,6000,ref_ref,a_60 +R 6000,5000,ref_ref,a_50 +R 5000,7000,ref_ref,c_70 +R 5000,6000,ref_ref,c_60 +R 3000,6000,ref_ref,z_60 +R 4000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,b_40 +R 2000,5000,ref_ref,b_50 +R 1000,5000,ref_ref,b_50 +R 1000,6000,ref_ref,b_60 +R 5000,5000,ref_ref,c_50 +R 4000,3000,ref_ref,z_30 +R 7000,7000,ref_ref,a_70 +R 4000,7000,ref_ref,c_70 +S 4000,7000,4000,7000,400,c,LEFT,CALU1 +S 3800,3000,4000,3000,600,*,RIGHT,ALU1 +S 3000,6000,3000,6000,400,z,LEFT,CALU1 +S 4000,3000,4000,6000,400,z,DOWN,CALU1 +S 4000,2900,4000,6000,400,*,UP,ALU1 +S 5300,3900,7400,3900,400,*,RIGHT,ALU1 +S 3200,500,3200,1500,200,*,DOWN,POLY +S 5600,500,5600,1500,200,*,DOWN,POLY +S 3200,500,5600,500,200,*,RIGHT,POLY +S 2000,5000,2000,5000,400,b,LEFT,CALU1 +S 1000,4000,1000,6000,400,b,DOWN,CALU1 +S 5000,5000,5000,7000,400,c,UP,CALU1 +S 2800,8000,5100,8000,400,*,RIGHT,ALU1 +S 1800,7900,1800,9300,400,*,DOWN,ALU1 +S 2800,7000,2800,8000,400,*,UP,ALU1 +S 600,7000,600,8100,400,*,DOWN,ALU1 +S 600,7000,2800,7000,400,*,RIGHT,ALU1 +S 5600,9400,5600,9700,200,*,DOWN,POLY +S 4400,9400,4400,9700,200,*,DOWN,POLY +S 3200,9400,3200,9700,200,*,DOWN,POLY +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 1200,9400,1200,9700,200,*,DOWN,POLY +S 1800,5700,1800,9200,1000,*,UP,PDIF +S 3800,5700,3800,9200,1000,*,UP,PDIF +S 5000,5700,5000,9200,1000,*,UP,PDIF +S 800,5700,800,9200,400,*,UP,PDIF +S 600,7300,600,7900,600,*,DOWN,PDIF +S 2800,5700,2800,9200,600,n1,DOWN,PDIF +S 1000,3900,1000,6100,400,*,DOWN,ALU1 +S 1000,5000,2000,5000,600,*,LEFT,ALU1 +S 0,5000,8000,5000,10000,cgi2a_x1,LEFT,TALU8 +S 0,2200,8000,2200,5200,*,LEFT,PWELL +S 0,7600,8000,7600,5600,*,LEFT,NWELL +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 3000,6000,4000,6000,600,*,RIGHT,ALU1 +S 6200,5700,6200,9200,600,*,DOWN,PDIF +S 7200,5700,7200,9200,400,*,DOWN,PDIF +S 6800,9400,6800,9700,200,*,DOWN,POLY +S 6800,5500,6800,9400,200,1a,DOWN,PTRANS +S 1200,5500,1200,9400,200,1b,DOWN,PTRANS +S 2400,5500,2400,9400,200,2b,DOWN,PTRANS +S 4400,5500,4400,9400,200,1c,DOWN,PTRANS +S 3200,5500,3200,9400,200,3a,DOWN,PTRANS +S 5600,5500,5600,9400,200,4a,DOWN,PTRANS +S 7000,7000,7000,7000,400,a,LEFT,CALU1 +S 6000,7000,7000,7000,600,*,LEFT,ALU1 +S 6000,5000,6000,7000,400,a,DOWN,CALU1 +S 6000,4800,6000,7100,400,*,DOWN,ALU1 +S 6200,7900,6200,9300,400,*,UP,ALU1 +S 4000,7000,5000,7000,600,*,LEFT,ALU1 +S 600,2300,600,2900,600,*,UP,NDIF +S 1200,4900,2400,4900,600,*,RIGHT,POLY +S 2400,1100,2400,1500,200,*,DOWN,POLY +S 2400,1500,2400,3300,200,4b,UP,NTRANS +S 2400,3300,2400,5500,200,*,UP,POLY +S 2800,1700,2800,3100,600,n3,UP,NDIF +S 3200,1500,3200,3300,200,5a,UP,NTRANS +S 3200,3300,3200,5500,200,*,UP,POLY +S 3800,1700,3800,3100,1000,*,UP,NDIF +S 4400,1500,4400,3300,200,2c,UP,NTRANS +S 4400,1100,4400,1500,200,*,DOWN,POLY +S 4400,3300,4400,5500,200,*,DOWN,POLY +S 5000,1700,5000,3100,1000,*,UP,NDIF +S 5600,1500,5600,3300,200,6a,UP,NTRANS +S 5000,2000,5000,3100,400,*,UP,ALU1 +S 6800,1700,6800,2100,200,*,DOWN,POLY +S 6800,2100,6800,3900,200,2a,UP,NTRANS +S 7200,2300,7200,3700,400,*,UP,NDIF +S 7400,3000,7400,3610,600,*,DOWN,NDIF +S 7400,2700,7400,5900,400,*,UP,ALU1 +S 6800,3900,6800,5500,200,*,DOWN,POLY +S 5600,3300,5600,5500,200,*,UP,POLY +S 6200,1700,6200,3700,600,*,UP,NDIF +S 6200,700,6200,3100,400,*,DOWN,ALU1 +S 6000,4900,6400,4900,600,*,LEFT,ALU1 +S 3000,2000,5000,2000,400,*,RIGHT,ALU1 +S 600,3100,3000,3100,400,*,LEFT,ALU1 +S 3000,2000,3000,3100,400,*,UP,ALU1 +S 600,2100,600,3100,400,*,DOWN,ALU1 +S 1800,700,1800,2100,400,*,DOWN,ALU1 +S 800,1700,800,3100,400,*,DOWN,NDIF +S 1200,1500,1200,3300,200,3b,UP,NTRANS +S 1200,1100,1200,1500,200,*,DOWN,POLY +S 1800,1700,1800,3100,600,*,UP,NDIF +S 1200,3300,1200,5500,200,*,UP,POLY +S 4900,4800,4900,7100,600,*,DOWN,ALU1 +V 7000,700,CONT_BODY_P,* +V 5000,8000,CONT_DIF_P,n2 +V 1800,4900,CONT_POLY,* +V 3800,6000,CONT_DIF_P,* +V 1800,8000,CONT_DIF_P,* +V 600,7200,CONT_DIF_P,n2 +V 600,8000,CONT_DIF_P,n2 +V 6200,9000,CONT_DIF_P,* +V 1800,9000,CONT_DIF_P,* +V 7400,5800,CONT_DIF_P,an +V 6200,8000,CONT_DIF_P,* +V 4800,4900,CONT_POLY,* +V 600,3000,CONT_DIF_N,n4 +V 600,2200,CONT_DIF_N,n4 +V 3800,3000,CONT_DIF_N,* +V 5000,3000,CONT_DIF_N,n4 +V 5000,2200,CONT_DIF_N,n4 +V 5400,3900,CONT_POLY,an +V 7400,3600,CONT_DIF_N,an +V 7400,2800,CONT_DIF_N,an +V 6200,3000,CONT_DIF_N,* +V 6200,2000,CONT_DIF_N,* +V 6400,4900,CONT_POLY,* +V 1800,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/cgi2a_x1.vbe b/pdks/symbolic/msxlib/cells/cgi2a_x1.vbe new file mode 100644 index 000000000..4c4a0aa62 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2a_x1.vbe @@ -0,0 +1,38 @@ +ENTITY cgi2a_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT cin_a : NATURAL := 7; + CONSTANT cin_b : NATURAL := 12; + CONSTANT cin_c : NATURAL := 6; + CONSTANT rdown_a_z : NATURAL := 2060; + CONSTANT rdown_b_z : NATURAL := 2060; + CONSTANT rdown_c_z : NATURAL := 2050; + CONSTANT rup_a_z : NATURAL := 3000; + CONSTANT rup_b_z : NATURAL := 2980; + CONSTANT rup_c_z : NATURAL := 3000; + CONSTANT tphl_c_z : NATURAL := 50; + CONSTANT tphl_b_z : NATURAL := 57; + CONSTANT tphh_a_z : NATURAL := 103; + CONSTANT tplh_c_z : NATURAL := 56; + CONSTANT tplh_b_z : NATURAL := 76; + CONSTANT tpll_a_z : NATURAL := 105; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END cgi2a_x1; + +ARCHITECTURE behaviour_data_flow OF cgi2a_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on cgi2a_x1" + SEVERITY WARNING; + z <= not((not(a) or (b and c)) and (b or c)) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/cgi2a_x2.ap b/pdks/symbolic/msxlib/cells/cgi2a_x2.ap new file mode 100644 index 000000000..8992b3b01 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2a_x2.ap @@ -0,0 +1,238 @@ +V ALLIANCE : 6 +H cgi2a_x2,P, 8/ 8/2014,100 +A 0,0,15000,10000 +R 14000,6000,ref_ref,a_60 +R 14000,4000,ref_ref,a_40 +R 14000,5000,ref_ref,a_50 +R 13000,5000,ref_ref,a_50 +R 1000,5000,ref_ref,b_50 +R 1000,6000,ref_ref,b_60 +R 1000,7000,ref_ref,b_70 +R 2000,7000,ref_ref,b_70 +R 3000,7000,ref_ref,b_70 +R 4000,7000,ref_ref,b_70 +R 5000,7000,ref_ref,b_70 +R 6000,7000,ref_ref,b_70 +R 7000,7000,ref_ref,b_70 +R 8000,7000,ref_ref,b_70 +R 9000,7000,ref_ref,b_70 +R 9000,6000,ref_ref,b_60 +R 9000,5000,ref_ref,b_50 +R 8000,5000,ref_ref,b_50 +R 7000,5000,ref_ref,b_50 +R 6000,5000,ref_ref,b_50 +R 2000,4000,ref_ref,c_40 +R 3000,5000,ref_ref,c_50 +R 2000,6000,ref_ref,c_60 +R 2000,5000,ref_ref,c_50 +R 7000,6000,ref_ref,z_60 +R 6000,6000,ref_ref,z_60 +R 5000,6000,ref_ref,z_60 +R 4000,6000,ref_ref,z_60 +R 3000,6000,ref_ref,z_60 +R 4000,5000,ref_ref,z_50 +R 4000,4000,ref_ref,z_40 +R 4000,3000,ref_ref,z_30 +R 3000,3000,ref_ref,z_30 +R 5000,3000,ref_ref,z_30 +R 6000,3000,ref_ref,z_30 +R 7000,3000,ref_ref,z_30 +S 13100,9300,13900,9300,600,*,RIGHT,NTIE +S 11100,700,11900,700,600,*,RIGHT,PTIE +S 13600,1900,13600,3400,200,4i,UP,NTRANS +S 12400,1900,12400,3400,200,3i,UP,NTRANS +S 11200,5100,11200,5700,200,*,DOWN,POLY +S 10000,5100,10000,5700,200,*,DOWN,POLY +S 13000,5000,14000,5000,600,*,LEFT,ALU1 +S 10000,5100,11200,5100,200,*,LEFT,POLY +S 12400,4900,13600,4900,600,*,LEFT,POLY +S 11800,5700,11800,9200,600,*,DOWN,PDIF +S 12400,8500,12400,8900,200,*,UP,POLY +S 14300,5700,14300,8300,600,*,DOWN,PDIF +S 13600,5500,13600,8500,200,2i,DOWN,PTRANS +S 13000,5700,13000,8300,600,*,UP,PDIF +S 12400,5500,12400,8500,200,1i,DOWN,PTRANS +S 13600,1500,13600,1900,200,*,DOWN,POLY +S 12400,1500,12400,1900,200,*,DOWN,POLY +S 11800,700,11800,3100,400,*,DOWN,ALU1 +S 9400,700,9400,3100,400,*,DOWN,ALU1 +S 11600,6000,13000,6000,400,*,RIGHT,ALU1 +S 11600,4000,11600,6000,400,*,DOWN,ALU1 +S 14000,3900,14000,6100,400,*,UP,ALU1 +S 13000,5000,13000,5000,400,a,LEFT,CALU1 +S 14000,4000,14000,6000,400,a,DOWN,CALU1 +S 12400,3400,12400,5700,200,*,DOWN,POLY +S 13600,3400,13600,5700,200,*,DOWN,POLY +S 14200,700,14200,3100,400,*,DOWN,ALU1 +S 13000,2100,13000,3200,600,*,UP,NDIF +S 14300,2100,14300,3200,600,*,UP,NDIF +S 11700,2100,11700,3200,600,*,UP,NDIF +S 4900,4000,13000,4000,400,*,RIGHT,ALU1 +S 13000,6000,13000,7100,400,*,UP,ALU1 +S 6000,5000,6000,5000,400,b,LEFT,CALU1 +S 7000,5000,7000,5000,400,b,LEFT,CALU1 +S 8000,5000,8000,5000,400,b,LEFT,CALU1 +S 8000,7000,8000,7000,400,b,LEFT,CALU1 +S 9000,5000,9000,7000,400,b,UP,CALU1 +S 7000,7000,7000,7000,400,b,LEFT,CALU1 +S 6000,7000,6000,7000,400,b,LEFT,CALU1 +S 5000,7000,5000,7000,400,b,LEFT,CALU1 +S 4000,7000,4000,7000,400,b,LEFT,CALU1 +S 3000,7000,3000,7000,400,b,LEFT,CALU1 +S 2000,7000,2000,7000,400,b,LEFT,CALU1 +S 1000,5000,1000,7000,400,b,UP,CALU1 +S 14200,6900,14200,9300,400,*,UP,ALU1 +S 0,5000,15000,5000,10000,cgi2a_x2,LEFT,TALU8 +S 0,2200,15000,2200,5200,*,LEFT,PWELL +S 0,7600,15000,7600,5600,*,LEFT,NWELL +S 0,600,15000,600,1200,vss,RIGHT,CALU1 +S 0,9400,15000,9400,1200,vdd,RIGHT,CALU1 +S 2400,1300,2400,1700,200,*,DOWN,POLY +S 1000,7000,9000,7000,400,*,RIGHT,ALU1 +S 1000,4900,1000,7000,400,*,UP,ALU1 +S 2000,5000,3100,5000,400,*,LEFT,ALU1 +S 2400,5000,3600,5000,600,*,RIGHT,POLY +S 2000,3900,2000,6100,400,*,DOWN,ALU1 +S 3000,5000,3000,5000,400,c,LEFT,CALU1 +S 2000,4000,2000,6000,400,c,DOWN,CALU1 +S 4000,3000,4000,6000,400,z,DOWN,CALU1 +S 4000,3000,4000,6000,400,*,DOWN,ALU1 +S 7000,3000,7000,3000,400,z,LEFT,CALU1 +S 6000,3000,6000,3000,400,z,LEFT,CALU1 +S 3000,3000,3000,3000,400,z,LEFT,CALU1 +S 3000,6000,3000,6000,400,z,LEFT,CALU1 +S 5000,3000,5000,3000,400,z,LEFT,CALU1 +S 7000,6000,7000,6000,400,z,LEFT,CALU1 +S 6000,6000,6000,6000,400,z,LEFT,CALU1 +S 5000,6000,5000,6000,400,z,LEFT,CALU1 +S 2900,6000,7500,6000,400,*,RIGHT,ALU1 +S 5900,5000,9000,5000,400,*,RIGHT,ALU1 +S 9000,5000,9000,7000,600,*,UP,ALU1 +S 5400,800,5400,3700,600,*,UP,NDIF +S 7400,1900,7400,3200,600,*,DOWN,NDIF +S 3000,1900,3000,3200,600,*,DOWN,NDIF +S 600,800,600,3700,600,*,UP,NDIF +S 1800,1900,1800,3200,600,*,UP,NDIF +S 1600,800,1600,3700,400,*,UP,NDIF +S 4200,1900,4200,3200,600,*,UP,NDIF +S 4400,800,4400,3700,400,*,DOWN,NDIF +S 3000,5900,3000,9200,1000,*,UP,PDIF +S 4800,5300,6200,5300,200,*,RIGHT,POLY +S 8800,3400,8800,5700,200,*,DOWN,POLY +S 8000,3400,8000,5700,200,*,DOWN,POLY +S 6800,3400,6800,5700,200,*,DOWN,POLY +S 6000,3400,6000,5700,200,*,DOWN,POLY +S 1200,3900,1200,5700,200,*,DOWN,POLY +S 3600,3400,3600,5700,200,*,DOWN,POLY +S 2400,3400,2400,5700,200,*,DOWN,POLY +S 5000,4000,5000,4600,600,*,DOWN,ALU1 +S 1800,5900,1800,9200,600,*,DOWN,PDIF +S 4200,5900,4200,9200,600,*,UP,PDIF +S 5400,5900,5400,9200,600,*,UP,PDIF +S 7400,5900,7400,9200,600,*,UP,PDIF +S 9400,5900,9400,9200,600,*,UP,PDIF +S 10600,5900,10600,9200,600,*,UP,PDIF +S 600,5900,600,9200,600,*,DOWN,PDIF +S 600,7900,600,9300,400,*,UP,ALU1 +S 1700,8000,10600,8000,400,*,RIGHT,ALU1 +S 10600,6900,10600,8000,400,*,DOWN,ALU1 +S 11800,6900,11800,9300,400,*,UP,ALU1 +S 600,700,600,3100,400,*,DOWN,ALU1 +S 1800,2000,4300,2000,400,*,RIGHT,ALU1 +S 1800,2000,1800,3100,400,*,DOWN,ALU1 +S 5400,700,5400,2100,400,*,DOWN,ALU1 +S 2900,3000,7400,3000,400,*,RIGHT,ALU1 +S 7400,1900,7400,3000,400,*,DOWN,ALU1 +S 9500,1900,9500,3200,600,*,UP,NDIF +S 9400,1900,9400,3200,600,*,UP,NDIF +S 8800,1300,8800,1700,200,*,DOWN,POLY +S 8000,1300,8000,1700,200,*,DOWN,POLY +S 6800,1300,6800,1700,200,*,DOWN,POLY +S 6000,1300,6000,1700,200,*,DOWN,POLY +S 4800,300,4800,600,200,*,DOWN,POLY +S 3600,1300,3600,1700,200,*,DOWN,POLY +S 1200,300,1200,600,200,*,DOWN,POLY +S 1200,9400,1200,9700,200,*,DOWN,POLY +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 3600,9400,3600,9700,200,*,DOWN,POLY +S 4800,9400,4800,9700,200,*,DOWN,POLY +S 6000,9400,6000,9700,200,*,DOWN,POLY +S 6800,9400,6800,9700,200,*,DOWN,POLY +S 8000,9400,8000,9700,200,*,DOWN,POLY +S 8800,9400,8800,9700,200,*,DOWN,POLY +S 10000,9400,10000,9700,200,*,DOWN,POLY +S 11200,9400,11200,9700,200,*,DOWN,POLY +S 2400,5700,2400,9400,200,1c,DOWN,PTRANS +S 3600,5700,3600,9400,200,2c,DOWN,PTRANS +S 2400,1700,2400,3400,200,3c,UP,NTRANS +S 3600,1700,3600,3400,200,4c,UP,NTRANS +S 1200,5700,1200,9400,200,1a,DOWN,PTRANS +S 4800,5700,4800,9400,200,2a,DOWN,PTRANS +S 6000,5700,6000,9400,200,3a,DOWN,PTRANS +S 8800,5700,8800,9400,200,4a,DOWN,PTRANS +S 1200,600,1200,3900,200,5a,UP,NTRANS +S 6000,1700,6000,3400,200,7a,UP,NTRANS +S 8800,1700,8800,3400,200,8a,UP,NTRANS +S 11200,5700,11200,9400,200,1b,DOWN,PTRANS +S 10000,5700,10000,9400,200,2b,DOWN,PTRANS +S 6800,4000,8000,4000,600,*,RIGHT,POLY +S 6800,5700,6800,9400,200,3b,DOWN,PTRANS +S 8000,5700,8000,9400,200,4b,DOWN,PTRANS +S 4800,600,4800,3900,200,5b,UP,NTRANS +S 6800,1700,6800,3400,200,7b,UP,NTRANS +S 8000,1700,8000,3400,200,8b,UP,NTRANS +S 8400,5900,8400,9200,400,n1a,UP,PDIF +S 6400,5900,6400,9200,400,n1b,UP,PDIF +S 8400,1900,8400,3200,400,n3a,UP,NDIF +S 6400,1900,6400,3200,400,n3b,UP,NDIF +S 13600,8500,13600,8800,200,*,UP,POLY +S 13000,2200,13000,4000,400,*,UP,ALU1 +V 14000,9300,CONT_BODY_N,* +V 13000,9300,CONT_BODY_N,* +V 12000,700,CONT_BODY_P,* +V 11000,700,CONT_BODY_P,* +V 13000,6100,CONT_DIF_P,an +V 13300,4900,CONT_POLY,* +V 13000,2300,CONT_DIF_N,an +V 13000,3100,CONT_DIF_N,an +V 13000,7000,CONT_DIF_P,an +V 11600,4900,CONT_POLY,an +V 7400,4000,CONT_POLY,an +V 5000,4500,CONT_POLY,an +V 11800,3000,CONT_DIF_N,* +V 9400,3000,CONT_DIF_N,* +V 14200,3000,CONT_DIF_N,* +V 11800,2200,CONT_DIF_N,* +V 14200,2200,CONT_DIF_N,* +V 14200,8000,CONT_DIF_P,* +V 14200,7000,CONT_DIF_P,* +V 1000,5000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 600,9000,CONT_DIF_P,* +V 600,1000,CONT_DIF_N,* +V 5400,1000,CONT_DIF_N,* +V 3000,3000,CONT_DIF_N,* +V 4200,2000,CONT_DIF_N,n4 +V 1800,8000,CONT_DIF_P,n2 +V 5400,9000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,n2 +V 7400,6000,CONT_DIF_P,* +V 11800,8000,CONT_DIF_P,* +V 11800,9000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 6000,5000,CONT_POLY,* +V 9000,5000,CONT_POLY,* +V 600,8000,CONT_DIF_P,* +V 10600,7000,CONT_DIF_P,n2 +V 10600,7800,CONT_DIF_P,n2 +V 11800,7000,CONT_DIF_P,* +V 600,2000,CONT_DIF_N,* +V 600,3000,CONT_DIF_N,* +V 1800,3000,CONT_DIF_N,n4 +V 1800,2200,CONT_DIF_N,n4 +V 5400,2000,CONT_DIF_N,* +V 7400,2000,CONT_DIF_N,* +V 7400,2800,CONT_DIF_N,* +V 9400,2000,CONT_DIF_N,* +V 9400,9000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/cgi2a_x2.vbe b/pdks/symbolic/msxlib/cells/cgi2a_x2.vbe new file mode 100644 index 000000000..61ab612d1 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgi2a_x2.vbe @@ -0,0 +1,38 @@ +ENTITY cgi2a_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 15000; + CONSTANT cin_a : NATURAL := 11; + CONSTANT cin_b : NATURAL := 24; + CONSTANT cin_c : NATURAL := 11; + CONSTANT rdown_a_z : NATURAL := 1100; + CONSTANT rdown_b_z : NATURAL := 1090; + CONSTANT rdown_c_z : NATURAL := 1100; + CONSTANT rup_a_z : NATURAL := 1580; + CONSTANT rup_b_z : NATURAL := 1570; + CONSTANT rup_c_z : NATURAL := 1580; + CONSTANT tphl_c_z : NATURAL := 51; + CONSTANT tphl_b_z : NATURAL := 58; + CONSTANT tphh_a_z : NATURAL := 103; + CONSTANT tplh_c_z : NATURAL := 56; + CONSTANT tplh_b_z : NATURAL := 77; + CONSTANT tpll_a_z : NATURAL := 110; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END cgi2a_x2; + +ARCHITECTURE behaviour_data_flow OF cgi2a_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on cgi2a_x2" + SEVERITY WARNING; + z <= not((not(a) or (b and c)) and (b or c)) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/cgn2_x1.ap b/pdks/symbolic/msxlib/cells/cgn2_x1.ap new file mode 100644 index 000000000..f8ecadf00 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgn2_x1.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H cgn2_x1,P, 8/ 8/2014,100 +A 0,0,8000,10000 +R 7000,7000,ref_ref,c_70 +R 7000,8000,ref_ref,c_80 +R 4000,5000,ref_ref,b_50 +R 1000,6000,ref_ref,a_60 +R 1000,5000,ref_ref,a_50 +R 1000,4000,ref_ref,a_40 +R 2000,5000,ref_ref,a_50 +R 4000,4000,ref_ref,b_40 +R 5000,6000,ref_ref,c_60 +R 5000,7000,ref_ref,c_70 +R 6000,7000,ref_ref,c_70 +R 7000,4000,ref_ref,z_40 +R 7000,5000,ref_ref,z_50 +R 7000,6000,ref_ref,z_60 +R 7000,3000,ref_ref,z_30 +R 4000,6000,ref_ref,b_60 +R 6000,6000,ref_ref,z_60 +R 5000,5000,ref_ref,b_50 +S 2800,700,3600,700,600,*,RIGHT,PTIE +S 7100,7000,7100,8100,400,*,UP,ALU1 +S 7000,7000,7000,8100,400,*,UP,ALU1 +S 6200,7900,6200,9300,400,*,UP,ALU1 +S 5000,7000,7000,7000,400,*,LEFT,ALU1 +S 7000,7000,7000,8000,400,c,DOWN,CALU1 +S 6800,7700,6800,8100,200,*,DOWN,POLY +S 6200,5900,6200,9100,600,*,DOWN,PDIF +S 7000,3000,7000,6000,400,z,DOWN,CALU1 +S 5900,6000,7500,6000,400,*,LEFT,ALU1 +S 6800,5700,6800,7700,200,1z,DOWN,PTRANS +S 7200,5900,7200,7500,400,*,UP,PDIF +S 2400,6700,2400,9300,200,2a,DOWN,PTRANS +S 1200,6700,1200,9300,200,1a,DOWN,PTRANS +S 5600,6700,5600,9300,200,2b,DOWN,PTRANS +S 3200,6700,3200,9300,200,1b,DOWN,PTRANS +S 4400,6700,4400,9300,200,1c,DOWN,PTRANS +S 500,1900,4900,1900,400,*,RIGHT,ALU1 +S 1000,3900,1000,6100,400,*,DOWN,ALU1 +S 1000,4000,1000,6000,400,a,DOWN,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,8000,5000,10000,cgn2_x1,LEFT,TALU8 +S 0,2200,8000,2200,5200,*,LEFT,PWELL +S 0,7600,8000,7600,5600,*,LEFT,NWELL +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 1200,5000,2400,5000,600,*,RIGHT,POLY +S 1000,5000,2000,5000,600,*,LEFT,ALU1 +S 3600,5000,4000,5000,600,*,LEFT,ALU1 +S 4000,4000,4000,6000,400,b,UP,CALU1 +S 3800,6900,3800,9100,1000,*,UP,PDIF +S 5000,6900,5000,9100,1000,*,UP,PDIF +S 2800,7000,3900,7000,400,*,RIGHT,ALU1 +S 2800,3000,2800,7000,400,*,UP,ALU1 +S 5600,9300,5600,9700,200,*,DOWN,POLY +S 4400,9300,4400,9700,200,*,DOWN,POLY +S 3200,9300,3200,9700,200,*,DOWN,POLY +S 2400,9300,2400,9700,200,*,DOWN,POLY +S 2800,6900,2800,9100,600,n1,DOWN,PDIF +S 1800,6900,1800,9100,1000,*,UP,PDIF +S 800,6900,800,9100,400,*,UP,PDIF +S 1200,9300,1200,9700,200,*,DOWN,POLY +S 4400,3800,4400,6700,200,*,UP,POLY +S 3200,4800,3200,6700,200,*,UP,POLY +S 2400,4800,2400,6700,200,*,UP,POLY +S 5000,6000,5000,7000,400,c,DOWN,CALU1 +S 4900,5900,4900,7000,600,*,UP,ALU1 +S 4000,5000,5300,5000,600,*,RIGHT,ALU1 +S 5600,4800,5600,6700,200,*,UP,POLY +S 4000,3900,4000,6100,400,*,UP,ALU1 +S 600,6900,600,8000,400,*,UP,ALU1 +S 600,8000,5100,8000,400,*,RIGHT,ALU1 +S 600,7100,600,7700,600,*,UP,PDIF +S 2800,3000,5000,3000,400,*,RIGHT,ALU1 +S 5000,4000,6200,4000,600,*,RIGHT,ALU1 +S 5000,3000,5000,4100,400,*,UP,ALU1 +S 7000,3000,7200,3000,600,*,LEFT,ALU1 +S 7000,2500,7000,3100,400,*,UP,NDIF +S 6600,2300,6600,3300,200,2z,UP,NTRANS +S 6800,4100,6800,6700,200,*,DOWN,POLY +S 6600,3300,6600,4200,200,*,UP,POLY +S 7000,3000,7000,6000,400,*,DOWN,ALU1 +S 6000,700,6000,3100,400,*,DOWN,ALU1 +S 6600,1900,6600,2300,200,*,UP,POLY +S 6000,2100,6000,3100,600,*,UP,NDIF +S 5400,1500,5400,1900,200,*,DOWN,POLY +S 5400,1900,5400,3100,200,4b,UP,NTRANS +S 4200,1500,4200,1900,200,*,DOWN,POLY +S 4200,1900,4200,3100,200,2c,UP,NTRANS +S 3000,1500,3000,1900,200,*,DOWN,POLY +S 3000,1900,3000,3100,200,3b,UP,NTRANS +S 2200,1500,2200,1900,200,*,DOWN,POLY +S 2200,1900,2200,3100,200,4a,UP,NTRANS +S 3600,2100,3600,2900,600,*,UP,NDIF +S 2600,2100,2600,2900,600,n3,UP,NDIF +S 4800,2100,4800,2900,600,*,UP,NDIF +S 4800,1900,4800,2200,600,*,UP,ALU1 +S 3600,2800,3600,3000,600,*,DOWN,ALU1 +S 1200,1900,1200,3100,200,3a,UP,NTRANS +S 800,2100,800,2900,400,*,DOWN,NDIF +S 600,1900,600,2200,600,*,UP,ALU1 +S 1700,900,1700,2900,400,*,UP,NDIF +S 1200,1600,1200,1900,200,*,DOWN,POLY +S 1200,3100,1200,6700,200,*,UP,POLY +S 2200,3100,2200,4700,200,*,UP,POLY +S 3000,3100,3000,5200,200,*,UP,POLY +S 4200,3100,4200,3900,200,*,UP,POLY +S 5400,3100,5400,4700,200,*,UP,POLY +S 2000,5000,2000,5000,400,a,LEFT,CALU1 +S 5000,5000,5000,5000,400,b,LEFT,CALU1 +S 6000,6000,6000,6000,400,z,LEFT,CALU1 +S 6000,7000,6000,7000,400,c,LEFT,CALU1 +V 3800,700,CONT_BODY_P,* +V 2800,700,CONT_BODY_P,* +V 7300,9300,CONT_BODY_N,* +V 6200,8000,CONT_DIF_P,* +V 7400,6000,CONT_DIF_P,* +V 1800,9000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,n2 +V 6200,9000,CONT_DIF_P,* +V 2000,5000,CONT_POLY,* +V 3600,5000,CONT_POLY,* +V 3800,7000,CONT_DIF_P,zn +V 4800,6000,CONT_POLY,* +V 5200,5000,CONT_POLY,* +V 600,7000,CONT_DIF_P,n2 +V 600,7800,CONT_DIF_P,n2 +V 6200,4000,CONT_POLY,zn +V 6000,3000,CONT_DIF_N,* +V 7200,3000,CONT_DIF_N,* +V 6000,2200,CONT_DIF_N,* +V 4800,2200,CONT_DIF_N,n4 +V 3600,2800,CONT_DIF_N,zn +V 600,2200,CONT_DIF_N,n4 +V 1600,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/cgn2_x1.vbe b/pdks/symbolic/msxlib/cells/cgn2_x1.vbe new file mode 100644 index 000000000..b86bf48e8 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgn2_x1.vbe @@ -0,0 +1,38 @@ +ENTITY cgn2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT cin_a : NATURAL := 8; + CONSTANT cin_b : NATURAL := 9; + CONSTANT cin_c : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 2320; + CONSTANT rdown_b_z : NATURAL := 2330; + CONSTANT rdown_c_z : NATURAL := 2340; + CONSTANT rup_a_z : NATURAL := 2980; + CONSTANT rup_b_z : NATURAL := 2970; + CONSTANT rup_c_z : NATURAL := 2970; + CONSTANT tphh_c_z : NATURAL := 95; + CONSTANT tpll_c_z : NATURAL := 118; + CONSTANT tpll_a_z : NATURAL := 134; + CONSTANT tphh_b_z : NATURAL := 104; + CONSTANT tpll_b_z : NATURAL := 132; + CONSTANT tphh_a_z : NATURAL := 102; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END cgn2_x1; + +ARCHITECTURE behaviour_data_flow OF cgn2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on cgn2_x1" + SEVERITY WARNING; + z <= ((b and (a or c)) or (a and c)) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/cgn2_x2.ap b/pdks/symbolic/msxlib/cells/cgn2_x2.ap new file mode 100644 index 000000000..c708cbcef --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgn2_x2.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 6 +H cgn2_x2,P, 8/ 8/2014,100 +A 0,0,8000,10000 +R 4000,5000,ref_ref,b_50 +R 1000,6000,ref_ref,a_60 +R 1000,5000,ref_ref,a_50 +R 1000,4000,ref_ref,a_40 +R 2000,5000,ref_ref,a_50 +R 4000,4000,ref_ref,b_40 +R 5000,5000,ref_ref,c_50 +R 5000,6000,ref_ref,c_60 +R 5000,7000,ref_ref,c_70 +R 6000,7000,ref_ref,c_70 +R 5000,4000,ref_ref,b_40 +R 7000,4000,ref_ref,z_40 +R 7000,5000,ref_ref,z_50 +R 7000,6000,ref_ref,z_60 +R 7000,3000,ref_ref,z_30 +R 4000,6000,ref_ref,b_60 +R 7000,7000,ref_ref,z_70 +R 7000,2000,ref_ref,z_20 +R 6000,5000,ref_ref,z_50 +S 2800,700,3600,700,600,*,RIGHT,PTIE +S 6800,5600,6800,9400,200,1z,DOWN,PTRANS +S 4400,5600,4400,9400,200,1c,DOWN,PTRANS +S 5600,5600,5600,9400,200,2b,DOWN,PTRANS +S 3200,5600,3200,9400,200,1b,DOWN,PTRANS +S 1200,5600,1200,9400,200,2a,DOWN,PTRANS +S 2400,5600,2400,9400,200,1a,DOWN,PTRANS +S 1000,3900,1000,6100,400,*,DOWN,ALU1 +S 1000,4000,1000,6000,400,a,DOWN,CALU1 +S 5000,7000,6100,7000,400,*,LEFT,ALU1 +S 5000,5000,5000,7000,400,c,DOWN,CALU1 +S 3200,9400,3200,9700,200,*,DOWN,POLY +S 4400,9400,4400,9700,200,*,DOWN,POLY +S 5600,9400,5600,9700,200,*,DOWN,POLY +S 1200,9400,1200,9700,200,*,DOWN,POLY +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 6200,7900,6200,9300,400,*,UP,ALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,8000,5000,10000,cgn2_x2,LEFT,TALU8 +S 0,2200,8000,2200,5200,*,LEFT,PWELL +S 0,7600,8000,7600,5600,*,LEFT,NWELL +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 1000,5000,2000,5000,600,*,LEFT,ALU1 +S 3600,5000,4000,5000,600,*,LEFT,ALU1 +S 4900,4900,4900,7000,600,*,UP,ALU1 +S 4000,4000,4000,6000,400,b,UP,CALU1 +S 4000,4000,4000,6100,400,*,UP,ALU1 +S 2800,3000,6200,3000,400,*,RIGHT,ALU1 +S 6000,700,6000,2100,400,*,DOWN,ALU1 +S 600,2000,4900,2000,400,*,RIGHT,ALU1 +S 7000,7100,7500,7100,400,*,LEFT,ALU1 +S 4000,4000,5300,4000,600,*,RIGHT,ALU1 +S 800,5800,800,9200,400,*,UP,PDIF +S 1800,5800,1800,9200,1000,*,UP,PDIF +S 3800,5800,3800,9200,1000,*,UP,PDIF +S 2800,5800,2800,9200,600,n1,DOWN,PDIF +S 5000,5800,5000,9200,1000,*,UP,PDIF +S 6200,5800,6200,9200,600,*,DOWN,PDIF +S 7200,5800,7200,9200,400,*,UP,PDIF +S 6800,9400,6800,9700,200,*,DOWN,POLY +S 2800,7000,3900,7000,400,*,RIGHT,ALU1 +S 2800,3000,2800,7000,400,*,UP,ALU1 +S 600,7100,600,7700,600,*,UP,PDIF +S 600,6900,600,8000,400,*,UP,ALU1 +S 600,8000,5100,8000,400,*,RIGHT,ALU1 +S 1200,5000,2200,5000,600,*,RIGHT,POLY +S 2400,5100,2400,5600,200,*,UP,POLY +S 3200,4800,3200,5600,200,*,UP,POLY +S 4400,3800,4400,5600,200,*,UP,POLY +S 5600,4100,5600,5600,200,*,UP,POLY +S 7000,2000,7200,2000,600,*,LEFT,ALU1 +S 7000,2000,7000,7100,400,*,DOWN,ALU1 +S 7000,2000,7000,7000,400,z,DOWN,CALU1 +S 6200,3000,6200,3400,400,*,UP,ALU1 +S 6800,3400,6800,5600,200,*,DOWN,POLY +S 2200,1600,2200,3300,200,3a,UP,NTRANS +S 1200,1600,1200,3300,200,4a,UP,NTRANS +S 800,1800,800,3100,400,*,DOWN,NDIF +S 2600,1800,2600,3100,600,n3,UP,NDIF +S 3600,1800,3600,3100,1000,*,UP,NDIF +S 4200,1600,4200,3300,200,2c,UP,NTRANS +S 3000,1600,3000,3300,200,3b,UP,NTRANS +S 4600,1800,4600,3100,400,*,UP,NDIF +S 600,2000,600,3100,400,*,DOWN,ALU1 +S 600,2300,600,2900,600,*,UP,NDIF +S 1200,3300,1200,5500,200,*,UP,POLY +S 2200,3300,2200,4700,200,*,UP,POLY +S 3000,3300,3000,4900,200,*,UP,POLY +S 4200,3300,4200,3900,200,*,UP,POLY +S 1200,1200,1200,1600,200,*,DOWN,POLY +S 2200,1200,2200,1600,200,*,DOWN,POLY +S 3000,1200,3000,1600,200,*,DOWN,POLY +S 4200,1200,4200,1600,200,*,DOWN,POLY +S 1700,500,1700,3100,400,*,UP,NDIF +S 2000,5000,2000,5000,400,a,LEFT,CALU1 +S 5000,4000,5000,4000,400,b,LEFT,CALU1 +S 6000,7000,6000,7000,400,c,LEFT,CALU1 +S 6000,5000,6000,5000,400,z,LEFT,CALU1 +S 5900,5000,7000,5000,400,*,LEFT,ALU1 +S 7000,6300,7500,6300,400,*,LEFT,ALU1 +S 7400,6200,7400,7000,600,*,UP,PDIF +S 6600,300,6600,700,200,*,UP,POLY +S 6600,700,6600,2600,200,2z,UP,NTRANS +S 7000,900,7000,2400,400,*,UP,NDIF +S 6000,900,6000,2400,600,*,UP,NDIF +S 5400,500,5400,900,200,*,DOWN,POLY +S 5400,900,5400,2600,200,4b,UP,NTRANS +S 5000,1100,5000,2400,400,*,UP,NDIF +S 5400,2600,5400,3800,200,*,UP,POLY +S 6600,2600,6600,3500,200,*,UP,POLY +V 3800,700,CONT_BODY_P,* +V 2800,700,CONT_BODY_P,* +V 1800,9000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,n2 +V 6200,8000,CONT_DIF_P,* +V 6200,9000,CONT_DIF_P,* +V 2000,5000,CONT_POLY,* +V 3600,5000,CONT_POLY,* +V 4800,5000,CONT_POLY,* +V 4800,2000,CONT_DIF_N,n4 +V 5200,4000,CONT_POLY,* +V 6000,2000,CONT_DIF_N,* +V 7400,7100,CONT_DIF_P,* +V 3600,3000,CONT_DIF_N,zn +V 3800,7000,CONT_DIF_P,zn +V 600,7000,CONT_DIF_P,n2 +V 600,7800,CONT_DIF_P,n2 +V 6200,3300,CONT_POLY,zn +V 7200,2000,CONT_DIF_N,* +V 600,3000,CONT_DIF_N,n4 +V 600,2200,CONT_DIF_N,n4 +V 1600,600,CONT_DIF_N,* +V 7400,6300,CONT_DIF_P,* +V 6000,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/cgn2_x2.vbe b/pdks/symbolic/msxlib/cells/cgn2_x2.vbe new file mode 100644 index 000000000..1812601d2 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgn2_x2.vbe @@ -0,0 +1,38 @@ +ENTITY cgn2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT cin_a : NATURAL := 12; + CONSTANT cin_b : NATURAL := 12; + CONSTANT cin_c : NATURAL := 7; + CONSTANT rdown_a_z : NATURAL := 1220; + CONSTANT rdown_b_z : NATURAL := 1230; + CONSTANT rdown_c_z : NATURAL := 1230; + CONSTANT rup_a_z : NATURAL := 1560; + CONSTANT rup_b_z : NATURAL := 1560; + CONSTANT rup_c_z : NATURAL := 1560; + CONSTANT tphh_c_z : NATURAL := 98; + CONSTANT tpll_c_z : NATURAL := 120; + CONSTANT tpll_a_z : NATURAL := 135; + CONSTANT tphh_b_z : NATURAL := 106; + CONSTANT tpll_b_z : NATURAL := 133; + CONSTANT tphh_a_z : NATURAL := 105; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END cgn2_x2; + +ARCHITECTURE behaviour_data_flow OF cgn2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on cgn2_x2" + SEVERITY WARNING; + z <= ((b and (a or c)) or (a and c)) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/cgn2_x3.ap b/pdks/symbolic/msxlib/cells/cgn2_x3.ap new file mode 100644 index 000000000..684e15ac5 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgn2_x3.ap @@ -0,0 +1,226 @@ +V ALLIANCE : 6 +H cgn2_x3,P, 8/ 8/2014,100 +A 0,0,15000,10000 +R 13000,7000,ref_ref,z_70 +R 13000,6000,ref_ref,z_60 +R 14000,5000,ref_ref,z_50 +R 13000,5000,ref_ref,z_50 +R 13000,3000,ref_ref,z_30 +R 13000,4000,ref_ref,z_40 +R 10000,6000,ref_ref,b_60 +R 2000,4000,ref_ref,c_40 +R 3000,5000,ref_ref,c_50 +R 2000,6000,ref_ref,c_60 +R 2000,5000,ref_ref,c_50 +R 10000,4000,ref_ref,b_40 +R 10000,5000,ref_ref,b_50 +R 1000,5000,ref_ref,a_50 +R 6000,5000,ref_ref,a_50 +R 9000,5000,ref_ref,a_50 +R 9000,7000,ref_ref,a_70 +R 7000,5000,ref_ref,a_50 +R 8000,5000,ref_ref,a_50 +R 8000,7000,ref_ref,a_70 +R 7000,7000,ref_ref,a_70 +R 6000,7000,ref_ref,a_70 +R 5000,7000,ref_ref,a_70 +R 4000,7000,ref_ref,a_70 +R 3000,7000,ref_ref,a_70 +R 2000,7000,ref_ref,a_70 +R 1000,7000,ref_ref,a_70 +R 1000,6000,ref_ref,a_60 +R 9000,6000,ref_ref,a_60 +R 5000,4000,ref_ref,b_40 +R 9000,4000,ref_ref,b_40 +R 8000,4000,ref_ref,b_40 +R 7000,4000,ref_ref,b_40 +R 6000,4000,ref_ref,b_40 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 9400,700,9400,2200,400,*,DOWN,ALU1 +S 6000,3000,6000,5700,200,*,DOWN,POLY +S 6800,3000,6800,5700,200,*,DOWN,POLY +S 8000,3000,8000,5700,200,*,DOWN,POLY +S 8800,3000,8800,5700,200,*,DOWN,POLY +S 9500,2000,9500,2800,600,*,UP,NDIF +S 7400,2500,7400,3000,400,*,DOWN,ALU1 +S 7400,2000,7400,2800,600,*,DOWN,NDIF +S 8000,1800,8000,3000,200,8b,UP,NTRANS +S 8800,1800,8800,3000,200,8a,UP,NTRANS +S 8400,2000,8400,2800,400,n3a,UP,NDIF +S 6800,1800,6800,3000,200,7b,UP,NTRANS +S 6000,1800,6000,3000,200,7a,UP,NTRANS +S 6400,2000,6400,2800,400,n3b,UP,NDIF +S 3000,2700,3000,3000,600,*,UP,ALU1 +S 4200,2000,4200,2800,600,*,DOWN,NDIF +S 1800,2000,1800,2800,600,*,DOWN,NDIF +S 5400,700,5400,2200,400,*,DOWN,ALU1 +S 5400,2000,5400,3700,600,*,UP,NDIF +S 4800,1800,4800,3900,200,5b,UP,NTRANS +S 4400,2000,4400,3700,400,*,DOWN,NDIF +S 3600,3000,3600,5700,200,*,DOWN,POLY +S 2400,3000,2400,5700,200,*,DOWN,POLY +S 1200,3900,1200,5700,200,*,DOWN,POLY +S 600,2000,600,3700,600,*,UP,NDIF +S 1800,1900,1800,2100,600,*,DOWN,ALU1 +S 1700,1900,4300,1900,400,*,RIGHT,ALU1 +S 1200,1800,1200,3900,200,5a,UP,NTRANS +S 1600,2000,1600,3700,400,*,UP,NDIF +S 4200,1900,4200,2100,600,*,DOWN,ALU1 +S 3600,1800,3600,3000,200,4c,UP,NTRANS +S 2400,1800,2400,3000,200,3c,UP,NTRANS +S 3000,2000,3000,2800,600,*,DOWN,NDIF +S 2900,3000,11000,3000,400,*,RIGHT,ALU1 +S 11700,2400,11700,3500,600,*,UP,NDIF +S 14300,2400,14300,3500,600,*,UP,NDIF +S 14200,700,14200,3500,400,*,DOWN,ALU1 +S 11800,700,11800,3500,400,*,DOWN,ALU1 +S 13600,2200,13600,3700,200,4z,UP,NTRANS +S 12400,2200,12400,3700,200,3z,UP,NTRANS +S 13000,2400,13000,3500,600,*,UP,NDIF +S 14300,5700,14300,8100,600,*,DOWN,PDIF +S 11800,5700,11800,8100,600,*,DOWN,PDIF +S 13100,5700,13100,8100,600,*,DOWN,PDIF +S 13600,5500,13600,8300,200,2z,DOWN,PTRANS +S 12400,5500,12400,8300,200,1z,DOWN,PTRANS +S 11200,5700,11200,8300,200,1b,DOWN,PTRANS +S 10600,5900,10600,8100,600,*,UP,PDIF +S 9400,5900,9400,9100,600,*,UP,PDIF +S 5400,5900,5400,9100,600,*,UP,PDIF +S 8400,5900,8400,8100,400,n1a,UP,PDIF +S 10000,5700,10000,8300,200,2b,DOWN,PTRANS +S 8800,5700,8800,8300,200,4a,DOWN,PTRANS +S 6400,5900,6400,8100,400,n1b,UP,PDIF +S 6000,5700,6000,8300,200,3a,DOWN,PTRANS +S 6800,5700,6800,8300,200,3b,DOWN,PTRANS +S 8000,5700,8000,8300,200,4b,DOWN,PTRANS +S 7400,5900,7400,8100,600,*,UP,PDIF +S 3000,5900,3000,8100,600,*,UP,PDIF +S 3600,5700,3600,8300,200,2c,DOWN,PTRANS +S 4800,5700,4800,8300,200,2a,DOWN,PTRANS +S 4200,5900,4200,8100,600,*,UP,PDIF +S 600,5900,600,8100,600,*,DOWN,PDIF +S 2400,5700,2400,8300,200,1c,DOWN,PTRANS +S 1200,5700,1200,8300,200,1a,DOWN,PTRANS +S 1800,5900,1800,8100,600,*,DOWN,PDIF +S 14000,5000,14000,5000,400,z,LEFT,CALU1 +S 13000,5000,14100,5000,400,*,RIGHT,ALU1 +S 13000,3000,13000,7000,400,z,UP,CALU1 +S 12400,4600,13600,4600,200,*,RIGHT,POLY +S 11000,4400,12200,4400,400,*,RIGHT,ALU1 +S 11000,3000,11000,4400,400,*,UP,ALU1 +S 10000,4000,10000,6000,600,*,DOWN,ALU1 +S 10000,4000,10000,6000,400,b,DOWN,CALU1 +S 13600,3700,13600,5700,200,*,DOWN,POLY +S 12400,3700,12400,5700,200,*,DOWN,POLY +S 13000,2500,13000,7100,400,*,DOWN,ALU1 +S 14200,6900,14200,9300,400,*,UP,ALU1 +S 0,5000,15000,5000,10000,cgn2_x3,LEFT,TALU8 +S 0,2200,15000,2200,5200,*,LEFT,PWELL +S 0,7600,15000,7600,5600,*,LEFT,NWELL +S 0,9400,15000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,15000,600,1200,vss,RIGHT,CALU1 +S 1000,7000,9000,7000,400,*,RIGHT,ALU1 +S 1000,4900,1000,7000,400,*,UP,ALU1 +S 2000,5000,3100,5000,400,*,LEFT,ALU1 +S 2400,5000,3600,5000,600,*,RIGHT,POLY +S 2000,3900,2000,6100,400,*,DOWN,ALU1 +S 3000,5000,3000,5000,400,c,LEFT,CALU1 +S 2000,4000,2000,6000,400,c,DOWN,CALU1 +S 4000,3000,4000,6000,400,*,DOWN,ALU1 +S 2900,6000,7500,6000,400,*,RIGHT,ALU1 +S 1000,5000,1000,7000,400,a,UP,CALU1 +S 2000,7000,2000,7000,400,a,LEFT,CALU1 +S 3000,7000,3000,7000,400,a,LEFT,CALU1 +S 4000,7000,4000,7000,400,a,LEFT,CALU1 +S 5000,7000,5000,7000,400,a,LEFT,CALU1 +S 6000,7000,6000,7000,400,a,LEFT,CALU1 +S 7000,7000,7000,7000,400,a,LEFT,CALU1 +S 8000,7000,8000,7000,400,a,LEFT,CALU1 +S 5900,5000,9000,5000,400,*,RIGHT,ALU1 +S 7000,5000,7000,5000,400,a,LEFT,CALU1 +S 8000,5000,8000,5000,400,a,LEFT,CALU1 +S 6000,5000,6000,5000,400,a,LEFT,CALU1 +S 9000,5000,9000,7000,400,a,UP,CALU1 +S 9000,5000,9000,7000,600,*,UP,ALU1 +S 5000,4000,5000,4000,400,b,LEFT,CALU1 +S 6000,4000,6000,4000,400,b,LEFT,CALU1 +S 7000,4000,7000,4000,400,b,LEFT,CALU1 +S 8000,4000,8000,4000,400,b,LEFT,CALU1 +S 9000,4000,9000,4000,400,b,LEFT,CALU1 +S 4900,4000,10000,4000,400,*,RIGHT,ALU1 +S 10000,5200,11200,5200,200,*,LEFT,POLY +S 11200,5200,11200,5700,200,*,DOWN,POLY +S 10000,5200,10000,5700,200,*,DOWN,POLY +S 4800,5300,6200,5300,200,*,RIGHT,POLY +S 5000,4000,5000,4600,600,*,DOWN,ALU1 +S 600,7900,600,9300,400,*,UP,ALU1 +S 1700,8000,10600,8000,400,*,RIGHT,ALU1 +S 10600,6900,10600,8000,400,*,DOWN,ALU1 +S 11800,6900,11800,9300,400,*,UP,ALU1 +S 600,700,600,3100,400,*,DOWN,ALU1 +S 6800,4000,8000,4000,600,*,RIGHT,POLY +S 1200,8300,1200,8700,200,*,UP,POLY +S 2400,8300,2400,8700,200,*,UP,POLY +S 3600,8300,3600,8700,200,*,UP,POLY +S 4800,8300,4800,8700,200,*,UP,POLY +S 6000,8300,6000,8700,200,*,UP,POLY +S 6800,8300,6800,8700,200,*,UP,POLY +S 8000,8300,8000,8700,200,*,UP,POLY +S 8800,8300,8800,8700,200,*,UP,POLY +S 10000,8300,10000,8700,200,*,UP,POLY +S 11200,8300,11200,8700,200,*,UP,POLY +S 12400,8300,12400,8700,200,*,UP,POLY +S 13600,8300,13600,8700,200,*,UP,POLY +S 1200,1400,1200,1800,200,*,DOWN,POLY +S 2400,1400,2400,1800,200,*,DOWN,POLY +S 3600,1400,3600,1800,200,*,DOWN,POLY +S 4800,1400,4800,1800,200,*,DOWN,POLY +S 6000,1400,6000,1800,200,*,DOWN,POLY +S 6800,1400,6800,1800,200,*,DOWN,POLY +S 8000,1400,8000,1800,200,*,DOWN,POLY +S 8800,1400,8800,1800,200,*,DOWN,POLY +S 13600,1800,13600,2200,200,*,DOWN,POLY +S 12400,1800,12400,2200,200,*,DOWN,POLY +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 9400,2100,CONT_DIF_N,* +V 7400,2600,CONT_DIF_N,zn +V 5400,2100,CONT_DIF_N,* +V 600,2200,CONT_DIF_N,* +V 1800,2100,CONT_DIF_N,n4 +V 4200,2100,CONT_DIF_N,n4 +V 3000,2700,CONT_DIF_N,zn +V 14200,2600,CONT_DIF_N,* +V 14200,3400,CONT_DIF_N,* +V 11800,2600,CONT_DIF_N,* +V 11800,3400,CONT_DIF_N,* +V 7400,6000,CONT_DIF_P,zn +V 3000,6000,CONT_DIF_P,zn +V 12100,4400,CONT_POLY,zn +V 13000,2600,CONT_DIF_N,* +V 13000,3400,CONT_DIF_N,* +V 13000,7000,CONT_DIF_P,* +V 13000,6000,CONT_DIF_P,* +V 14200,7000,CONT_DIF_P,* +V 14200,8000,CONT_DIF_P,* +V 1000,5000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 1800,8000,CONT_DIF_P,n2 +V 5400,9000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,n2 +V 11800,8000,CONT_DIF_P,* +V 6000,5000,CONT_POLY,* +V 9000,5000,CONT_POLY,* +V 10000,5000,CONT_POLY,* +V 5000,4500,CONT_POLY,* +V 600,8000,CONT_DIF_P,* +V 10600,7000,CONT_DIF_P,n2 +V 10600,7800,CONT_DIF_P,n2 +V 11800,7000,CONT_DIF_P,* +V 600,3000,CONT_DIF_N,* +V 9400,9000,CONT_DIF_P,* +V 7400,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/cgn2_x3.vbe b/pdks/symbolic/msxlib/cells/cgn2_x3.vbe new file mode 100644 index 000000000..d2b043a21 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgn2_x3.vbe @@ -0,0 +1,38 @@ +ENTITY cgn2_x3 IS +GENERIC ( + CONSTANT area : NATURAL := 15000; + CONSTANT cin_a : NATURAL := 18; + CONSTANT cin_b : NATURAL := 17; + CONSTANT cin_c : NATURAL := 8; + CONSTANT rdown_a_z : NATURAL := 770; + CONSTANT rdown_b_z : NATURAL := 780; + CONSTANT rdown_c_z : NATURAL := 780; + CONSTANT rup_a_z : NATURAL := 1060; + CONSTANT rup_b_z : NATURAL := 1060; + CONSTANT rup_c_z : NATURAL := 1060; + CONSTANT tphh_c_z : NATURAL := 102; + CONSTANT tpll_c_z : NATURAL := 122; + CONSTANT tpll_a_z : NATURAL := 138; + CONSTANT tphh_b_z : NATURAL := 108; + CONSTANT tpll_b_z : NATURAL := 134; + CONSTANT tphh_a_z : NATURAL := 108; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END cgn2_x3; + +ARCHITECTURE behaviour_data_flow OF cgn2_x3 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on cgn2_x3" + SEVERITY WARNING; + z <= ((b and (a or c)) or (a and c)) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/cgn2_x4.ap b/pdks/symbolic/msxlib/cells/cgn2_x4.ap new file mode 100644 index 000000000..9b6749f87 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgn2_x4.ap @@ -0,0 +1,227 @@ +V ALLIANCE : 6 +H cgn2_x4,P, 8/ 8/2014,100 +A 0,0,15000,10000 +R 6000,4000,ref_ref,b_40 +R 7000,4000,ref_ref,b_40 +R 8000,4000,ref_ref,b_40 +R 9000,4000,ref_ref,b_40 +R 5000,4000,ref_ref,b_40 +R 9000,6000,ref_ref,a_60 +R 1000,6000,ref_ref,a_60 +R 1000,7000,ref_ref,a_70 +R 2000,7000,ref_ref,a_70 +R 3000,7000,ref_ref,a_70 +R 4000,7000,ref_ref,a_70 +R 5000,7000,ref_ref,a_70 +R 6000,7000,ref_ref,a_70 +R 7000,7000,ref_ref,a_70 +R 8000,7000,ref_ref,a_70 +R 8000,5000,ref_ref,a_50 +R 7000,5000,ref_ref,a_50 +R 9000,7000,ref_ref,a_70 +R 9000,5000,ref_ref,a_50 +R 6000,5000,ref_ref,a_50 +R 1000,5000,ref_ref,a_50 +R 10000,5000,ref_ref,b_50 +R 10000,4000,ref_ref,b_40 +R 2000,5000,ref_ref,c_50 +R 2000,6000,ref_ref,c_60 +R 3000,5000,ref_ref,c_50 +R 2000,4000,ref_ref,c_40 +R 10000,6000,ref_ref,b_60 +R 13000,4000,ref_ref,z_40 +R 13000,3000,ref_ref,z_30 +R 13000,5000,ref_ref,z_50 +R 14000,5000,ref_ref,z_50 +R 13000,6000,ref_ref,z_60 +R 13000,7000,ref_ref,z_70 +S 11100,700,11900,700,600,*,RIGHT,PTIE +S 13600,9300,13600,9700,200,*,DOWN,POLY +S 12400,9300,12400,9700,200,*,DOWN,POLY +S 11200,8700,11200,9100,200,*,DOWN,POLY +S 10000,8700,10000,9100,200,*,DOWN,POLY +S 8800,8700,8800,9100,200,*,DOWN,POLY +S 8000,8700,8000,9100,200,*,DOWN,POLY +S 6800,8700,6800,9100,200,*,DOWN,POLY +S 6000,8700,6000,9100,200,*,DOWN,POLY +S 4800,8700,4800,9100,200,*,DOWN,POLY +S 3600,8700,3600,9100,200,*,DOWN,POLY +S 2400,8700,2400,9100,200,*,DOWN,POLY +S 1200,8700,1200,9100,200,*,DOWN,POLY +S 10000,5600,10000,8700,200,2b,DOWN,PTRANS +S 11200,5600,11200,8700,200,1b,DOWN,PTRANS +S 10600,5800,10600,8500,600,*,UP,PDIF +S 7400,5800,7400,8500,600,*,UP,PDIF +S 8400,5800,8400,8500,400,n1a,UP,PDIF +S 8800,5600,8800,8700,200,4a,DOWN,PTRANS +S 8000,5600,8000,8700,200,4b,DOWN,PTRANS +S 6400,5800,6400,8500,400,n1b,UP,PDIF +S 6000,5600,6000,8700,200,3a,DOWN,PTRANS +S 6800,5600,6800,8700,200,3b,DOWN,PTRANS +S 4800,5600,4800,8700,200,2a,DOWN,PTRANS +S 4200,5800,4200,8500,600,*,UP,PDIF +S 600,5800,600,8500,600,*,DOWN,PDIF +S 1800,5800,1800,8500,600,*,DOWN,PDIF +S 1200,5600,1200,8700,200,1a,DOWN,PTRANS +S 3600,5600,3600,8700,200,2c,DOWN,PTRANS +S 3000,5800,3000,8500,1000,*,UP,PDIF +S 2400,5600,2400,8700,200,1c,DOWN,PTRANS +S 14300,5800,14300,9100,600,*,DOWN,PDIF +S 13600,5600,13600,9300,200,2z,DOWN,PTRANS +S 13100,5800,13100,9100,600,*,DOWN,PDIF +S 12400,5600,12400,9300,200,1z,DOWN,PTRANS +S 11900,5800,11900,9100,600,*,DOWN,PDIF +S 9400,5800,9400,9100,600,*,UP,PDIF +S 5400,5800,5400,9100,600,*,UP,PDIF +S 4800,5200,6200,5200,200,*,RIGHT,POLY +S 4800,3300,4800,4000,200,*,UP,POLY +S 8800,1500,8800,1900,200,*,DOWN,POLY +S 8000,1500,8000,1900,200,*,DOWN,POLY +S 6800,1500,6800,1900,200,*,DOWN,POLY +S 6000,1500,6000,1900,200,*,DOWN,POLY +S 8800,3300,8800,5700,200,*,DOWN,POLY +S 8000,3300,8000,5700,200,*,DOWN,POLY +S 6800,3300,6800,5700,200,*,DOWN,POLY +S 6000,3300,6000,5700,200,*,DOWN,POLY +S 9400,700,9400,2200,600,*,DOWN,ALU1 +S 6000,1900,6000,3300,200,7a,UP,NTRANS +S 6400,2100,6400,3100,400,n3b,UP,NDIF +S 9500,2100,9500,3100,600,*,UP,NDIF +S 8800,1900,8800,3300,200,8a,UP,NTRANS +S 8400,2100,8400,3100,400,n3a,UP,NDIF +S 8000,1900,8000,3300,200,8b,UP,NTRANS +S 6800,1900,6800,3300,200,7b,UP,NTRANS +S 7400,2100,7400,3100,600,*,DOWN,NDIF +S 5400,800,5400,3100,600,*,UP,NDIF +S 4800,600,4800,3300,200,5b,UP,NTRANS +S 4400,800,4400,3100,400,*,DOWN,NDIF +S 1200,3300,1200,5700,200,*,DOWN,POLY +S 600,800,600,3100,600,*,UP,NDIF +S 1200,600,1200,3300,200,5a,UP,NTRANS +S 1600,800,1600,3100,400,*,UP,NDIF +S 4200,2100,4200,3100,600,*,UP,NDIF +S 3600,3300,3600,5600,200,*,DOWN,POLY +S 2400,3300,2400,5600,200,*,DOWN,POLY +S 2400,1500,2400,1900,200,*,DOWN,POLY +S 3600,1500,3600,1900,200,*,DOWN,POLY +S 1800,2100,1800,3100,600,*,UP,NDIF +S 1800,2200,1800,3000,600,*,DOWN,ALU1 +S 1800,2200,4300,2200,400,*,RIGHT,ALU1 +S 3600,1900,3600,3300,200,4c,UP,NTRANS +S 2400,1900,2400,3300,200,3c,UP,NTRANS +S 3000,2100,3000,3100,600,*,DOWN,NDIF +S 6800,4000,8000,4000,600,*,RIGHT,POLY +S 1200,300,1200,600,200,*,DOWN,POLY +S 4800,300,4800,600,200,*,DOWN,POLY +S 5400,700,5400,2100,400,*,DOWN,ALU1 +S 600,700,600,3100,400,*,DOWN,ALU1 +S 11800,6900,11800,9300,400,*,UP,ALU1 +S 10600,6900,10600,8000,400,*,DOWN,ALU1 +S 1700,8000,10600,8000,400,*,RIGHT,ALU1 +S 600,7900,600,9300,400,*,UP,ALU1 +S 10000,5200,10000,5700,200,*,DOWN,POLY +S 11200,5200,11200,5700,200,*,DOWN,POLY +S 10000,5200,11200,5200,200,*,LEFT,POLY +S 4900,4000,10000,4000,400,*,RIGHT,ALU1 +S 9000,4000,9000,4000,400,b,LEFT,CALU1 +S 8000,4000,8000,4000,400,b,LEFT,CALU1 +S 7000,4000,7000,4000,400,b,LEFT,CALU1 +S 6000,4000,6000,4000,400,b,LEFT,CALU1 +S 5000,4000,5000,4000,400,b,LEFT,CALU1 +S 9000,5000,9000,7000,600,*,UP,ALU1 +S 9000,5000,9000,7000,400,a,UP,CALU1 +S 6000,5000,6000,5000,400,a,LEFT,CALU1 +S 8000,5000,8000,5000,400,a,LEFT,CALU1 +S 7000,5000,7000,5000,400,a,LEFT,CALU1 +S 5900,5000,9000,5000,400,*,RIGHT,ALU1 +S 8000,7000,8000,7000,400,a,LEFT,CALU1 +S 7000,7000,7000,7000,400,a,LEFT,CALU1 +S 6000,7000,6000,7000,400,a,LEFT,CALU1 +S 5000,7000,5000,7000,400,a,LEFT,CALU1 +S 4000,7000,4000,7000,400,a,LEFT,CALU1 +S 3000,7000,3000,7000,400,a,LEFT,CALU1 +S 2000,7000,2000,7000,400,a,LEFT,CALU1 +S 1000,5000,1000,7000,400,a,UP,CALU1 +S 2900,6000,7500,6000,400,*,RIGHT,ALU1 +S 4000,3000,4000,6000,400,*,DOWN,ALU1 +S 2000,4000,2000,6000,400,c,DOWN,CALU1 +S 3000,5000,3000,5000,400,c,LEFT,CALU1 +S 2000,3900,2000,6100,400,*,DOWN,ALU1 +S 2400,5000,3600,5000,600,*,RIGHT,POLY +S 2000,5000,3100,5000,400,*,LEFT,ALU1 +S 1000,4900,1000,7000,400,*,UP,ALU1 +S 1000,7000,9000,7000,400,*,RIGHT,ALU1 +S 0,600,15000,600,1200,vss,RIGHT,CALU1 +S 0,9400,15000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,15000,5000,10000,cgn2_x4,LEFT,TALU8 +S 0,2200,15000,2200,5200,*,LEFT,PWELL +S 0,7600,15000,7600,5600,*,LEFT,NWELL +S 14200,6900,14200,9300,400,*,UP,ALU1 +S 13000,2500,13000,7100,400,*,DOWN,ALU1 +S 14200,700,14200,3100,400,*,DOWN,ALU1 +S 11800,700,11800,3100,400,*,DOWN,ALU1 +S 14300,2100,14300,3500,600,*,UP,NDIF +S 11700,2100,11700,3500,600,*,UP,NDIF +S 13000,2100,13000,3500,600,*,UP,NDIF +S 12400,1900,12400,3700,200,3z,UP,NTRANS +S 13600,1900,13600,3700,200,4z,UP,NTRANS +S 12400,3700,12400,5700,200,*,DOWN,POLY +S 13600,3700,13600,5700,200,*,DOWN,POLY +S 10000,4000,10000,6000,400,b,DOWN,CALU1 +S 10000,4000,10000,6000,600,*,DOWN,ALU1 +S 7400,2100,7400,3000,400,*,DOWN,ALU1 +S 2900,3000,11000,3000,400,*,RIGHT,ALU1 +S 11000,3000,11000,4400,400,*,UP,ALU1 +S 11000,4400,12200,4400,400,*,RIGHT,ALU1 +S 12400,4600,13600,4600,200,*,RIGHT,POLY +S 13000,3000,13000,7000,400,z,UP,CALU1 +S 13000,5000,14100,5000,400,*,RIGHT,ALU1 +S 14000,5000,14000,5000,400,z,LEFT,CALU1 +S 12400,1500,12400,1900,200,*,DOWN,POLY +S 13600,1500,13600,1900,200,*,DOWN,POLY +V 12000,700,CONT_BODY_P,* +V 11000,700,CONT_BODY_P,* +V 5000,4000,CONT_POLY,* +V 9400,2200,CONT_DIF_N,* +V 4200,2200,CONT_DIF_N,n4 +V 7400,4000,CONT_POLY,* +V 9400,9000,CONT_DIF_P,* +V 5400,2000,CONT_DIF_N,* +V 1800,2200,CONT_DIF_N,n4 +V 1800,3000,CONT_DIF_N,n4 +V 600,3000,CONT_DIF_N,* +V 600,2000,CONT_DIF_N,* +V 11800,7000,CONT_DIF_P,* +V 10600,7800,CONT_DIF_P,n2 +V 10600,7000,CONT_DIF_P,n2 +V 600,8000,CONT_DIF_P,* +V 10000,5000,CONT_POLY,* +V 9000,5000,CONT_POLY,* +V 6000,5000,CONT_POLY,* +V 11800,9000,CONT_DIF_P,* +V 11800,8000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,n2 +V 5400,9000,CONT_DIF_P,* +V 1800,8000,CONT_DIF_P,n2 +V 5400,1000,CONT_DIF_N,* +V 600,1000,CONT_DIF_N,* +V 3000,5000,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 14200,9000,CONT_DIF_P,* +V 14200,8000,CONT_DIF_P,* +V 14200,7000,CONT_DIF_P,* +V 13000,6000,CONT_DIF_P,* +V 13000,7000,CONT_DIF_P,* +V 14200,2200,CONT_DIF_N,* +V 11800,2200,CONT_DIF_N,* +V 11800,3000,CONT_DIF_N,* +V 14200,3000,CONT_DIF_N,* +V 13000,3400,CONT_DIF_N,* +V 13000,2600,CONT_DIF_N,* +V 12100,4400,CONT_POLY,zn +V 7400,3000,CONT_DIF_N,zn +V 7400,2200,CONT_DIF_N,zn +V 3000,3000,CONT_DIF_N,zn +V 3000,6000,CONT_DIF_P,zn +V 7400,6000,CONT_DIF_P,zn +EOF diff --git a/pdks/symbolic/msxlib/cells/cgn2_x4.vbe b/pdks/symbolic/msxlib/cells/cgn2_x4.vbe new file mode 100644 index 000000000..4092bece4 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/cgn2_x4.vbe @@ -0,0 +1,38 @@ +ENTITY cgn2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 15000; + CONSTANT cin_a : NATURAL := 21; + CONSTANT cin_b : NATURAL := 19; + CONSTANT cin_c : NATURAL := 10; + CONSTANT rdown_a_z : NATURAL := 640; + CONSTANT rdown_b_z : NATURAL := 650; + CONSTANT rdown_c_z : NATURAL := 650; + CONSTANT rup_a_z : NATURAL := 800; + CONSTANT rup_b_z : NATURAL := 800; + CONSTANT rup_c_z : NATURAL := 800; + CONSTANT tphh_c_z : NATURAL := 100; + CONSTANT tpll_c_z : NATURAL := 123; + CONSTANT tpll_a_z : NATURAL := 139; + CONSTANT tphh_b_z : NATURAL := 107; + CONSTANT tpll_b_z : NATURAL := 135; + CONSTANT tphh_a_z : NATURAL := 107; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END cgn2_x4; + +ARCHITECTURE behaviour_data_flow OF cgn2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on cgn2_x4" + SEVERITY WARNING; + z <= ((b and (a or c)) or (a and c)) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/ha2_x2.ap b/pdks/symbolic/msxlib/cells/ha2_x2.ap new file mode 100644 index 000000000..bb459fe1e --- /dev/null +++ b/pdks/symbolic/msxlib/cells/ha2_x2.ap @@ -0,0 +1,161 @@ +V ALLIANCE : 6 +H ha2_x2,P, 8/ 8/2014,100 +A 0,0,10000,10000 +R 6000,5000,ref_ref,a_50 +R 9000,3000,ref_ref,co_30 +R 5000,4000,ref_ref,a_40 +R 5000,3000,ref_ref,a_30 +R 5000,5000,ref_ref,a_50 +R 7000,5000,ref_ref,b_50 +R 6000,6000,ref_ref,b_60 +R 5000,6000,ref_ref,b_60 +R 7000,6000,ref_ref,b_60 +R 4000,5000,ref_ref,b_50 +R 4000,4000,ref_ref,b_40 +R 4000,6000,ref_ref,b_60 +R 9000,4000,ref_ref,co_40 +R 9000,5000,ref_ref,co_50 +R 9000,6000,ref_ref,co_60 +R 9000,7000,ref_ref,co_70 +R 1000,7000,ref_ref,so_70 +R 1000,6000,ref_ref,so_60 +R 1000,5000,ref_ref,so_50 +R 1000,4000,ref_ref,so_40 +R 1000,3000,ref_ref,so_30 +S 8800,900,8800,1300,200,*,DOWN,POLY +S 7600,300,7600,600,200,*,DOWN,POLY +S 6800,300,6800,600,200,*,DOWN,POLY +S 4600,1200,4600,1600,200,*,DOWN,POLY +S 3400,900,3400,1300,200,*,DOWN,POLY +S 2200,900,2200,1300,200,*,DOWN,POLY +S 1200,1200,1200,1500,200,*,DOWN,POLY +S 8400,9400,8400,9700,200,*,UP,POLY +S 7200,9400,7200,9700,200,*,UP,POLY +S 6000,9400,6000,9700,200,*,UP,POLY +S 4600,9000,4600,9400,200,*,UP,POLY +S 3800,9000,3800,9400,200,*,UP,POLY +S 2600,7400,2600,7800,200,*,UP,POLY +S 1400,9400,1400,9700,200,*,UP,POLY +S 6000,5000,6000,5000,400,a,LEFT,CALU1 +S 6000,6000,6000,6000,400,b,LEFT,CALU1 +S 5000,6000,5000,6000,400,b,LEFT,CALU1 +S 7000,5000,7000,6000,400,b,DOWN,CALU1 +S 4000,4000,4000,6000,400,b,UP,CALU1 +S 5000,3000,5000,5000,400,a,UP,CALU1 +S 9000,3000,9000,7000,400,co,UP,CALU1 +S 1000,3000,1000,7000,400,so,UP,CALU1 +S 4200,5800,4200,8800,400,n3,UP,PDIF +S 7200,800,7200,3600,400,n1,UP,NDIF +S 7600,3800,7600,4200,200,*,UP,POLY +S 3800,4000,4000,4000,600,*,LEFT,ALU1 +S 3800,4000,3800,5600,200,*,DOWN,POLY +S 3400,2800,3400,4200,200,*,UP,POLY +S 4600,3100,4600,5600,200,*,DOWN,POLY +S 2700,1900,5300,1900,400,*,RIGHT,ALU1 +S 2200,3200,2600,3200,200,*,LEFT,POLY +S 2200,1300,2200,2800,200,2,UP,NTRANS +S 4600,1600,4600,3100,200,3a,UP,NTRANS +S 3400,1300,3400,2800,200,3b,UP,NTRANS +S 5000,1800,5000,2900,400,*,UP,NDIF +S 3800,1500,3800,2600,400,*,UP,NDIF +S 4000,1800,4000,2900,600,*,UP,NDIF +S 2800,1500,2800,2600,600,*,UP,NDIF +S 8400,5600,8400,9400,200,1c,DOWN,PTRANS +S 2600,5600,2600,7400,200,1,DOWN,PTRANS +S 6800,600,6800,3800,200,4a,UP,NTRANS +S 4600,5600,4600,9000,200,1a,DOWN,PTRANS +S 7600,600,7600,3800,200,4b,UP,NTRANS +S 7200,5600,7200,9400,200,2b,DOWN,PTRANS +S 3800,5600,3800,9000,200,1b,DOWN,PTRANS +S 8800,1300,8800,3200,200,2c,UP,NTRANS +S 1200,1500,1200,3400,200,2s,UP,NTRANS +S 1400,5600,1400,9400,200,1s,DOWN,PTRANS +S 5000,5000,6000,5000,600,*,LEFT,ALU1 +S 5000,5000,5800,5000,600,*,LEFT,POLY +S 6000,4200,6800,4200,200,*,RIGHT,POLY +S 600,2200,600,3200,400,*,UP,ALU1 +S 600,2400,600,3000,600,*,DOWN,NDIF +S 1000,2900,1000,7100,400,*,DOWN,ALU1 +S 8800,3200,8800,4800,200,*,UP,POLY +S 9400,2000,9400,3000,400,*,UP,ALU1 +S 9400,2200,9400,2700,600,*,UP,NDIF +S 9200,1500,9200,3000,400,*,UP,NDIF +S 9000,2900,9000,7100,400,*,DOWN,ALU1 +S 5200,5800,5200,9200,600,*,DOWN,PDIF +S 8200,700,8200,2100,400,*,DOWN,ALU1 +S 4000,3900,4000,6000,400,*,DOWN,ALU1 +S 4000,6000,7000,6000,400,*,RIGHT,ALU1 +S 3000,6000,3200,6000,600,*,RIGHT,ALU1 +S 3000,2800,3000,6100,400,*,DOWN,ALU1 +S 3000,2800,4100,2800,400,*,LEFT,ALU1 +S 2200,7000,8200,7000,400,*,LEFT,ALU1 +S 1800,4000,3000,4000,600,*,RIGHT,ALU1 +S 2200,4900,2200,7000,400,*,UP,ALU1 +S 2600,3200,2600,5600,200,*,DOWN,POLY +S 9000,6000,9000,6600,600,*,UP,PDIF +S 8800,5800,8800,9200,400,*,DOWN,PDIF +S 6600,7000,6600,8100,400,*,UP,ALU1 +S 7800,5800,7800,9200,600,*,UP,PDIF +S 6600,5800,6600,9200,600,*,DOWN,PDIF +S 3400,5800,3400,8800,400,*,DOWN,PDIF +S 3200,5800,3200,7200,600,*,UP,PDIF +S 6100,3500,8200,3500,400,*,RIGHT,ALU1 +S 8200,800,8200,3600,600,*,UP,NDIF +S 6400,800,6400,3600,400,*,UP,NDIF +S 8200,4800,8800,4800,200,*,LEFT,POLY +S 7400,4200,7400,5200,200,*,UP,POLY +S 1700,500,1700,3200,400,*,UP,NDIF +S 800,1700,800,3200,400,*,UP,NDIF +S 1400,3800,1400,5600,200,*,DOWN,POLY +S 1200,3400,1200,4200,200,*,DOWN,POLY +S 900,5800,900,7100,600,*,UP,ALU1 +S 800,6000,800,6600,600,*,DOWN,PDIF +S 1000,5800,1000,9200,400,*,DOWN,PDIF +S 2000,7900,2000,9300,400,*,UP,ALU1 +S 1900,5800,1900,9200,800,*,DOWN,PDIF +S 8200,3500,8200,7000,400,*,DOWN,ALU1 +S 7000,4900,7000,6000,400,*,DOWN,ALU1 +S 6000,4200,6000,5600,200,*,DOWN,POLY +S 5000,2900,5000,5100,400,*,UP,ALU1 +S 7800,7900,7800,9300,400,*,UP,ALU1 +S 5400,7900,5400,9300,400,*,UP,ALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,10000,5000,10000,ha2_x2,LEFT,TALU8 +S 0,2200,10000,2200,5200,*,LEFT,PWELL +S 0,7600,10000,7600,5600,*,LEFT,NWELL +S 6000,5600,6000,9400,200,2a,DOWN,PTRANS +S 4000,6100,7000,6100,400,*,RIGHT,ALU1 +V 5000,700,CONT_BODY_P,* +V 3800,4000,CONT_POLY,* +V 5200,1900,CONT_DIF_N,n2 +V 4000,2800,CONT_DIF_N,son +V 2800,1900,CONT_DIF_N,n2 +V 1600,600,CONT_DIF_N,* +V 5000,5000,CONT_POLY,* +V 5800,5000,CONT_POLY,* +V 600,2300,CONT_DIF_N,* +V 600,3100,CONT_DIF_N,* +V 9400,2100,CONT_DIF_N,* +V 9400,2900,CONT_DIF_N,* +V 8200,2000,CONT_DIF_N,* +V 2200,5000,CONT_POLY,con +V 2000,9000,CONT_DIF_P,* +V 8200,1000,CONT_DIF_N,* +V 6200,3500,CONT_DIF_N,con +V 800,6700,CONT_DIF_P,* +V 800,5900,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 8200,5000,CONT_POLY,con +V 7000,5000,CONT_POLY,* +V 1800,4000,CONT_POLY,son +V 3200,6000,CONT_DIF_P,son +V 6600,8000,CONT_DIF_P,con +V 6600,7000,CONT_DIF_P,con +V 7800,9000,CONT_DIF_P,* +V 7800,8000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 9000,6700,CONT_DIF_P,* +V 9000,5900,CONT_DIF_P,* +V 5400,9000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/ha2_x2.vbe b/pdks/symbolic/msxlib/cells/ha2_x2.vbe new file mode 100644 index 000000000..7315db1b8 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/ha2_x2.vbe @@ -0,0 +1,46 @@ +ENTITY ha2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 10000; + CONSTANT cin_a : NATURAL := 13; + CONSTANT cin_b : NATURAL := 13; + CONSTANT rdown_a_co : NATURAL := 1210; + CONSTANT rdown_a_so : NATURAL := 1210; + CONSTANT rdown_b_co : NATURAL := 1210; + CONSTANT rdown_b_so : NATURAL := 1210; + CONSTANT rup_a_co : NATURAL := 1560; + CONSTANT rup_a_so : NATURAL := 1560; + CONSTANT rup_b_co : NATURAL := 1560; + CONSTANT rup_b_so : NATURAL := 1560; + CONSTANT tphh_a_co : NATURAL := 70; + CONSTANT tpll_b_co : NATURAL := 99; + CONSTANT tphh_b_co : NATURAL := 70; + CONSTANT tpll_a_co : NATURAL := 89; + CONSTANT tphh_a_so : NATURAL := 100; + CONSTANT tpll_b_so : NATURAL := 108; + CONSTANT tphl_b_so : NATURAL := 154; + CONSTANT tplh_b_so : NATURAL := 160; + CONSTANT tphh_b_so : NATURAL := 87; + CONSTANT tpll_a_so : NATURAL := 117; + CONSTANT tphl_a_so : NATURAL := 155; + CONSTANT tplh_a_so : NATURAL := 144; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + a : in BIT; + b : in BIT; + co : out BIT; + so : out BIT; + vdd : in BIT; + vss : in BIT +); +END ha2_x2; + +ARCHITECTURE behaviour_data_flow OF ha2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ha2_x2" + SEVERITY WARNING; + so <= (a xor b) after 1200 ps; + co <= (a and b) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/iv1_w2.ap b/pdks/symbolic/msxlib/cells/iv1_w2.ap new file mode 100644 index 000000000..edb659234 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_w2.ap @@ -0,0 +1,46 @@ +V ALLIANCE : 6 +H iv1_w2,P, 7/ 8/2004,100 +A 0,0,3000,10000 +R 1000,3000,ref_ref,z_30 +R 2000,4000,ref_ref,a_40 +R 1000,7000,ref_ref,z_70 +R 2000,6000,ref_ref,a_60 +R 2000,5000,ref_ref,a_50 +R 1000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 2000,7000,ref_ref,z_70 +S 1000,2700,1000,7100,400,*,UP,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 1000,2900,1000,3500,600,*,UP,NDIF +S 1000,5900,1000,6500,600,*,UP,PDIF +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 0,7600,3000,7600,5600,*,LEFT,NWELL +S 0,2200,3000,2200,5200,*,LEFT,PWELL +S 0,5000,3000,5000,10000,iv1_w2,LEFT,TALU8 +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 1600,9400,1600,9700,200,*,DOWN,POLY +S 2200,5700,2200,9200,800,*,DOWN,PDIF +S 1600,5500,1600,9400,200,1,UP,PTRANS +S 1200,5700,1200,9200,400,*,UP,PDIF +S 1200,1500,1200,3700,400,*,DOWN,NDIF +S 1600,1300,1600,3900,200,2,DOWN,NTRANS +S 2300,1500,2300,3700,600,*,UP,NDIF +S 1600,900,1600,1300,200,*,UP,POLY +S 1600,3900,1600,5500,200,*,UP,POLY +S 2000,4000,2000,6000,400,a,DOWN,CALU1 +S 2000,3900,2000,6100,400,*,DOWN,ALU1 +S 2200,7900,2200,9300,400,*,UP,ALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 1000,7000,2000,7000,600,*,RIGHT,ALU1 +S 2200,700,2200,3100,400,*,UP,ALU1 +V 1000,2800,CONT_DIF_N,* +V 1000,6600,CONT_DIF_P,* +V 2200,8000,CONT_DIF_P,* +V 2200,9000,CONT_DIF_P,* +V 2200,2000,CONT_DIF_N,* +V 2000,4700,CONT_POLY,* +V 1000,5800,CONT_DIF_P,* +V 1000,3600,CONT_DIF_N,* +V 2200,3000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/iv1_w2.vbe b/pdks/symbolic/msxlib/cells/iv1_w2.vbe new file mode 100644 index 000000000..def2c41ad --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_w2.vbe @@ -0,0 +1,26 @@ +ENTITY iv1_w2 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_a : NATURAL := 7; + CONSTANT rdown_a_z : NATURAL := 880; + CONSTANT rup_a_z : NATURAL := 1520; + CONSTANT tphl_a_z : NATURAL := 32; + CONSTANT tplh_a_z : NATURAL := 39; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END iv1_w2; + +ARCHITECTURE behaviour_data_flow OF iv1_w2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on iv1_w2" + SEVERITY WARNING; + z <= not (a) after 700 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/iv1_x05.ap b/pdks/symbolic/msxlib/cells/iv1_x05.ap new file mode 100644 index 000000000..d97eef5ec --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x05.ap @@ -0,0 +1,47 @@ +V ALLIANCE : 6 +H iv1_x05,P, 8/ 8/2014,100 +A 0,0,3000,10000 +R 1000,3000,ref_ref,z_30 +R 2000,6000,ref_ref,a_60 +R 2000,5000,ref_ref,a_50 +R 1000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 2000,3000,ref_ref,z_30 +R 2000,4000,ref_ref,a_40 +R 1000,7000,ref_ref,z_70 +R 1000,2000,ref_ref,z_20 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,LEFT,PTIE +S 2300,6300,2300,7100,600,*,DOWN,PDIF +S 1600,7300,1600,7700,200,*,DOWN,POLY +S 1600,6100,1600,7300,200,1,UP,PTRANS +S 1200,6300,1200,7100,400,*,UP,PDIF +S 2200,700,2200,2100,400,*,UP,ALU1 +S 2200,6900,2200,9300,400,*,UP,ALU1 +S 1000,2900,2100,2900,400,*,RIGHT,ALU1 +S 1000,3000,2100,3000,400,*,RIGHT,ALU1 +S 2000,3900,2000,6100,400,*,DOWN,ALU1 +S 2000,4000,2000,6000,400,a,DOWN,CALU1 +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 0,5000,3000,5000,10000,iv1_x05,LEFT,TALU8 +S 0,2200,3000,2200,5200,*,LEFT,PWELL +S 0,7600,3000,7600,5600,*,LEFT,NWELL +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 2000,3000,2000,3000,400,z,LEFT,CALU1 +S 1600,1300,1600,1700,200,*,UP,POLY +S 1600,1700,1600,2300,200,2,DOWN,NTRANS +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1000,1900,1000,7100,400,*,UP,ALU1 +S 1600,2300,1600,6100,200,*,UP,POLY +S 2300,1900,2300,2100,600,*,UP,NDIF +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 1000,6400,CONT_DIF_P,* +V 2200,2000,CONT_DIF_N,* +V 2000,4700,CONT_POLY,* +V 2200,7000,CONT_DIF_P,* +V 1000,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/iv1_x05.vbe b/pdks/symbolic/msxlib/cells/iv1_x05.vbe new file mode 100644 index 000000000..55423132b --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x05.vbe @@ -0,0 +1,26 @@ +ENTITY iv1_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_a : NATURAL := 2; + CONSTANT rdown_a_z : NATURAL := 3800; + CONSTANT rup_a_z : NATURAL := 4930; + CONSTANT tphl_a_z : NATURAL := 36; + CONSTANT tplh_a_z : NATURAL := 41; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END iv1_x05; + +ARCHITECTURE behaviour_data_flow OF iv1_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on iv1_x05" + SEVERITY WARNING; + z <= not (a) after 700 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/iv1_x1.ap b/pdks/symbolic/msxlib/cells/iv1_x1.ap new file mode 100644 index 000000000..2cd20f6b6 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x1.ap @@ -0,0 +1,50 @@ +V ALLIANCE : 6 +H iv1_x1,P, 8/ 8/2014,100 +A 0,0,3000,10000 +R 2000,4000,ref_ref,a_40 +R 1000,7000,ref_ref,z_70 +R 2000,6000,ref_ref,a_60 +R 2000,5000,ref_ref,a_50 +R 1000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 2000,3000,ref_ref,z_30 +R 1000,3000,ref_ref,z_30 +S 1100,700,1900,700,600,*,LEFT,PTIE +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 2000,3000,2000,3000,400,z,LEFT,CALU1 +S 1600,7500,1600,7900,200,*,DOWN,POLY +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 0,5000,3000,5000,10000,iv1_x1,LEFT,TALU8 +S 0,2200,3000,2200,5200,*,LEFT,PWELL +S 0,7600,3000,7600,5600,*,LEFT,NWELL +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 2000,4000,2000,6000,400,a,DOWN,CALU1 +S 2000,3900,2000,6100,400,*,DOWN,ALU1 +S 2200,6900,2200,9300,400,*,UP,ALU1 +S 1600,5500,1600,7500,200,1,UP,PTRANS +S 2200,5700,2200,7300,800,*,DOWN,PDIF +S 1200,5700,1200,7300,400,*,UP,PDIF +S 1000,3000,1000,7100,400,*,UP,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 1000,3000,2100,3000,400,*,RIGHT,ALU1 +S 1000,2900,2100,2900,400,*,RIGHT,ALU1 +S 2200,700,2200,2100,400,*,UP,ALU1 +S 1200,2500,1200,3100,400,*,UP,NDIF +S 1600,2300,1600,3300,200,2,DOWN,NTRANS +S 2300,1900,2300,3100,600,*,UP,NDIF +S 2200,1900,2200,3100,600,*,UP,NDIF +S 1600,3300,1600,5500,200,*,UP,POLY +S 1600,1900,1600,2300,200,*,UP,POLY +S 1000,6100,1000,6700,600,*,UP,PDIF +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2200,7000,CONT_DIF_P,* +V 1000,6800,CONT_DIF_P,* +V 2000,4700,CONT_POLY,* +V 2200,2000,CONT_DIF_N,* +V 1000,3000,CONT_DIF_N,* +V 1000,6000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/iv1_x1.vbe b/pdks/symbolic/msxlib/cells/iv1_x1.vbe new file mode 100644 index 000000000..7b09188a4 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x1.vbe @@ -0,0 +1,26 @@ +ENTITY iv1_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 2280; + CONSTANT rup_a_z : NATURAL := 2960; + CONSTANT tphl_a_z : NATURAL := 35; + CONSTANT tplh_a_z : NATURAL := 39; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END iv1_x1; + +ARCHITECTURE behaviour_data_flow OF iv1_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on iv1_x1" + SEVERITY WARNING; + z <= not (a) after 700 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/iv1_x2.ap b/pdks/symbolic/msxlib/cells/iv1_x2.ap new file mode 100644 index 000000000..3a53b2718 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x2.ap @@ -0,0 +1,50 @@ +V ALLIANCE : 6 +H iv1_x2,P, 8/ 8/2014,100 +A 0,0,3000,10000 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,a_50 +R 2000,6000,ref_ref,a_60 +R 1000,7000,ref_ref,z_70 +R 2000,4000,ref_ref,a_40 +R 1000,3000,ref_ref,z_30 +R 1000,2000,ref_ref,z_20 +R 2000,7000,ref_ref,z_70 +S 1100,700,1900,700,600,*,LEFT,PTIE +S 1000,5900,1000,6500,600,*,UP,PDIF +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1000,1900,1000,7100,400,*,UP,ALU1 +S 1600,1300,1600,1700,200,*,UP,POLY +S 1600,1700,1600,3600,200,2,DOWN,NTRANS +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,3000,5000,10000,iv1_x2,LEFT,TALU8 +S 0,2200,3000,2200,5200,*,LEFT,PWELL +S 0,7600,3000,7600,5600,*,LEFT,NWELL +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 1600,3600,1600,5500,200,*,UP,POLY +S 1200,1900,1200,3400,400,*,DOWN,NDIF +S 1600,5500,1600,9300,200,1,UP,PTRANS +S 2200,5700,2200,9100,800,*,DOWN,PDIF +S 1200,5700,1200,9100,400,*,UP,PDIF +S 2300,1900,2300,3400,600,*,UP,NDIF +S 2000,3900,2000,6100,400,*,DOWN,ALU1 +S 2000,4000,2000,6000,400,a,DOWN,CALU1 +S 1600,9300,1600,9700,200,*,DOWN,POLY +S 2200,7900,2200,9300,400,*,UP,ALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 1000,7000,2000,7000,600,*,RIGHT,ALU1 +S 2200,700,2200,3100,400,*,UP,ALU1 +S 1000,2600,1000,3200,600,*,UP,NDIF +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 1000,6600,CONT_DIF_P,* +V 1000,5800,CONT_DIF_P,* +V 2000,4700,CONT_POLY,* +V 2200,2000,CONT_DIF_N,* +V 1000,3300,CONT_DIF_N,* +V 2200,9000,CONT_DIF_P,* +V 2200,8000,CONT_DIF_P,* +V 2200,3000,CONT_DIF_N,* +V 1000,2500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/iv1_x2.vbe b/pdks/symbolic/msxlib/cells/iv1_x2.vbe new file mode 100644 index 000000000..0e18871e1 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x2.vbe @@ -0,0 +1,26 @@ +ENTITY iv1_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_a : NATURAL := 6; + CONSTANT rdown_a_z : NATURAL := 1200; + CONSTANT rup_a_z : NATURAL := 1560; + CONSTANT tphl_a_z : NATURAL := 34; + CONSTANT tplh_a_z : NATURAL := 38; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END iv1_x2; + +ARCHITECTURE behaviour_data_flow OF iv1_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on iv1_x2" + SEVERITY WARNING; + z <= not (a) after 700 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/iv1_x3.ap b/pdks/symbolic/msxlib/cells/iv1_x3.ap new file mode 100644 index 000000000..447a9dfbf --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x3.ap @@ -0,0 +1,70 @@ +V ALLIANCE : 6 +H iv1_x3,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 3000,6000,ref_ref,a_60 +R 3000,5000,ref_ref,a_50 +R 3000,4000,ref_ref,a_40 +R 2000,5000,ref_ref,a_50 +R 2000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,z_40 +R 2000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +R 2000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,LEFT,PTIE +S 2000,3000,2000,4000,400,z,DOWN,CALU1 +S 2000,6000,2000,7000,400,z,UP,CALU1 +S 2000,5000,2000,5000,400,a,LEFT,CALU1 +S 2000,2700,2000,3700,600,*,UP,NDIF +S 3300,2700,3300,3700,600,*,UP,NDIF +S 700,2700,700,3700,600,*,UP,NDIF +S 1400,8500,1400,8800,200,*,DOWN,POLY +S 2600,8500,2600,8800,200,*,DOWN,POLY +S 2000,5800,2000,8200,1000,*,DOWN,PDIF +S 2600,5600,2600,8400,200,2,UP,PTRANS +S 1400,5600,1400,8400,200,1,UP,PTRANS +S 1400,5000,2600,5000,600,*,RIGHT,POLY +S 0,5000,4000,5000,10000,iv1_x3,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 1000,4000,2000,4000,600,*,LEFT,ALU1 +S 1000,6000,2000,6000,600,*,RIGHT,ALU1 +S 800,6900,800,9300,400,*,UP,ALU1 +S 800,5800,800,8200,800,*,DOWN,PDIF +S 3200,5800,3200,8200,800,*,DOWN,PDIF +S 2600,4100,2600,5600,200,*,UP,POLY +S 1400,4100,1400,5600,200,*,UP,POLY +S 3200,700,3200,3100,400,*,DOWN,ALU1 +S 800,700,800,3100,400,*,DOWN,ALU1 +S 1900,5000,3000,5000,400,*,RIGHT,ALU1 +S 1000,4000,1000,6000,400,*,UP,ALU1 +S 1400,2100,1400,2500,200,*,UP,POLY +S 1400,2500,1400,3900,200,3,DOWN,NTRANS +S 2600,2100,2600,2500,200,*,UP,POLY +S 2600,2500,2600,3900,200,4,DOWN,NTRANS +S 2000,6000,2000,7100,400,*,UP,ALU1 +S 3000,3900,3000,6100,400,*,DOWN,ALU1 +S 3000,4000,3000,6000,400,a,DOWN,CALU1 +S 3200,6900,3200,9300,400,*,UP,ALU1 +S 1000,4000,1000,6000,400,z,DOWN,CALU1 +S 2000,2700,2000,4000,400,*,UP,ALU1 +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,6000,CONT_DIF_P,* +V 2200,5000,CONT_POLY,* +V 800,7000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 3200,8000,CONT_DIF_P,* +V 800,3000,CONT_DIF_N,* +V 3200,3000,CONT_DIF_N,* +V 2000,2800,CONT_DIF_N,* +V 2000,3600,CONT_DIF_N,* +V 3200,7000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/iv1_x3.vbe b/pdks/symbolic/msxlib/cells/iv1_x3.vbe new file mode 100644 index 000000000..b06427343 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x3.vbe @@ -0,0 +1,26 @@ +ENTITY iv1_x3 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 9; + CONSTANT rdown_a_z : NATURAL := 810; + CONSTANT rup_a_z : NATURAL := 1060; + CONSTANT tphl_a_z : NATURAL := 33; + CONSTANT tplh_a_z : NATURAL := 37; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END iv1_x3; + +ARCHITECTURE behaviour_data_flow OF iv1_x3 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on iv1_x3" + SEVERITY WARNING; + z <= not (a) after 700 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/iv1_x4.ap b/pdks/symbolic/msxlib/cells/iv1_x4.ap new file mode 100644 index 000000000..da8d69d7e --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x4.ap @@ -0,0 +1,74 @@ +V ALLIANCE : 6 +H iv1_x4,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 2000,2000,ref_ref,z_20 +R 3000,5000,ref_ref,a_50 +R 1000,5000,ref_ref,z_50 +R 2000,6000,ref_ref,z_60 +R 2000,3000,ref_ref,z_30 +R 2000,4000,ref_ref,z_40 +R 1000,4000,ref_ref,z_40 +R 1000,6000,ref_ref,z_60 +R 2000,7000,ref_ref,z_70 +R 2000,5000,ref_ref,a_50 +R 3000,4000,ref_ref,a_40 +R 3000,6000,ref_ref,a_60 +S 1100,700,1900,700,600,*,LEFT,PTIE +S 2000,2000,2000,4000,400,z,DOWN,CALU1 +S 2000,6000,2000,7000,400,z,UP,CALU1 +S 3200,6900,3200,9300,400,*,UP,ALU1 +S 2000,5000,2000,5000,400,a,LEFT,CALU1 +S 3000,3900,3000,6100,400,*,UP,ALU1 +S 3000,4000,3000,6000,400,a,DOWN,CALU1 +S 2000,6000,2000,7100,400,*,UP,ALU1 +S 3200,5800,3200,9200,800,*,DOWN,PDIF +S 800,5800,800,9200,800,*,DOWN,PDIF +S 1000,6000,2000,6000,600,*,RIGHT,ALU1 +S 1000,4000,2000,4000,600,*,LEFT,ALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,4000,5000,10000,iv1_x4,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 1400,1300,1400,1700,200,*,UP,POLY +S 2600,1300,2600,1700,200,*,UP,POLY +S 1400,1700,1400,3600,200,3,DOWN,NTRANS +S 2600,1700,2600,3600,200,4,DOWN,NTRANS +S 1400,5000,2600,5000,600,*,RIGHT,POLY +S 2000,5800,2000,9200,1000,*,DOWN,PDIF +S 1400,5600,1400,9400,200,1,UP,PTRANS +S 2600,5600,2600,9400,200,2,UP,PTRANS +S 1400,9400,1400,9700,200,*,DOWN,POLY +S 2600,9400,2600,9700,200,*,DOWN,POLY +S 3300,1900,3300,3400,600,*,UP,NDIF +S 700,1900,700,3400,600,*,UP,NDIF +S 2000,1900,2000,3400,600,*,UP,NDIF +S 800,700,800,3100,400,*,DOWN,ALU1 +S 3200,700,3200,3100,400,*,DOWN,ALU1 +S 2600,3600,2600,5600,200,*,UP,POLY +S 1400,3600,1400,5600,200,*,UP,POLY +S 800,6900,800,9300,400,*,UP,ALU1 +S 2000,1900,2000,4000,400,*,UP,ALU1 +S 1900,5000,3000,5000,400,*,RIGHT,ALU1 +S 1000,4000,1000,6000,400,*,UP,ALU1 +S 800,1900,800,3400,600,*,UP,NDIF +S 3200,1900,3200,3400,600,*,UP,NDIF +S 1000,4000,1000,6000,400,z,DOWN,CALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 3200,7000,CONT_DIF_P,* +V 2200,5000,CONT_POLY,* +V 800,3000,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 3200,2000,CONT_DIF_N,* +V 3200,3000,CONT_DIF_N,* +V 2000,6000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,2000,CONT_DIF_N,* +V 2000,3000,CONT_DIF_N,* +V 800,7000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 3200,8000,CONT_DIF_P,* +V 3200,9000,CONT_DIF_P,* +V 800,9000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/iv1_x4.vbe b/pdks/symbolic/msxlib/cells/iv1_x4.vbe new file mode 100644 index 000000000..ddeb12e0b --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x4.vbe @@ -0,0 +1,26 @@ +ENTITY iv1_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 12; + CONSTANT rdown_a_z : NATURAL := 600; + CONSTANT rup_a_z : NATURAL := 780; + CONSTANT tphl_a_z : NATURAL := 33; + CONSTANT tplh_a_z : NATURAL := 37; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END iv1_x4; + +ARCHITECTURE behaviour_data_flow OF iv1_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on iv1_x4" + SEVERITY WARNING; + z <= not (a) after 700 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/iv1_x8.ap b/pdks/symbolic/msxlib/cells/iv1_x8.ap new file mode 100644 index 000000000..9c363c152 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x8.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H iv1_x8,P, 8/ 8/2014,100 +A 0,0,6000,10000 +R 5000,4000,ref_ref,a_40 +R 5000,6000,ref_ref,a_60 +R 5000,5000,ref_ref,a_50 +R 4000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 2000,5000,ref_ref,a_50 +R 2000,7000,ref_ref,z_70 +R 2000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +R 2000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 3000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,z_60 +R 4000,6000,ref_ref,z_60 +R 4000,7000,ref_ref,z_70 +R 4000,5000,ref_ref,a_50 +R 3000,4000,ref_ref,z_40 +R 4000,4000,ref_ref,z_40 +R 4000,3000,ref_ref,z_30 +R 1000,6000,ref_ref,z_60 +R 1000,4000,ref_ref,z_40 +S 2400,700,3200,700,600,*,LEFT,PTIE +S 5400,700,5400,3100,400,*,DOWN,ALU1 +S 5000,4000,5000,6000,400,a,DOWN,CALU1 +S 5000,3900,5000,6100,400,*,DOWN,ALU1 +S 2000,5000,2000,5000,400,a,LEFT,CALU1 +S 3000,5000,3000,5000,400,a,LEFT,CALU1 +S 4000,5000,4000,5000,400,a,LEFT,CALU1 +S 3000,4000,3000,4000,400,z,LEFT,CALU1 +S 4000,2000,4000,4000,400,z,DOWN,CALU1 +S 2000,2000,2000,4000,400,z,DOWN,CALU1 +S 3000,6000,3000,6000,400,z,LEFT,CALU1 +S 4000,6000,4000,7000,400,z,UP,CALU1 +S 2000,6000,2000,7000,400,z,UP,CALU1 +S 4100,6000,4100,7100,600,*,DOWN,ALU1 +S 1900,6000,1900,7100,600,*,DOWN,ALU1 +S 1000,4000,4200,4000,400,*,RIGHT,ALU1 +S 1000,6000,4200,6000,400,*,LEFT,ALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,6000,5000,10000,iv1_x8,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 1200,9400,1200,9700,200,*,DOWN,POLY +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 3600,9400,3600,9700,200,*,DOWN,POLY +S 600,6900,600,9300,400,*,UP,ALU1 +S 3000,6900,3000,9300,400,*,UP,ALU1 +S 1000,4000,1000,6000,400,*,DOWN,ALU1 +S 1000,6100,4200,6100,400,*,LEFT,ALU1 +S 1900,5000,5000,5000,400,*,LEFT,ALU1 +S 5400,6900,5400,9300,400,*,UP,ALU1 +S 700,1900,700,3300,800,*,UP,NDIF +S 1800,1900,1800,3300,1000,*,UP,NDIF +S 1200,1700,1200,3500,200,5,DOWN,NTRANS +S 3000,1900,3000,3300,1000,*,UP,NDIF +S 2400,1700,2400,3500,200,6,DOWN,NTRANS +S 3600,1700,3600,3500,200,7,DOWN,NTRANS +S 4200,1900,4200,3300,1000,*,UP,NDIF +S 4800,1700,4800,3500,200,8,DOWN,NTRANS +S 5300,1900,5300,3300,800,*,UP,NDIF +S 600,700,600,3100,400,*,DOWN,ALU1 +S 1900,1900,1900,4000,600,*,DOWN,ALU1 +S 4100,1900,4100,4000,600,*,DOWN,ALU1 +S 3000,700,3000,3100,400,*,DOWN,ALU1 +S 4800,1300,4800,1700,200,*,UP,POLY +S 3600,1300,3600,1700,200,*,UP,POLY +S 2400,1300,2400,1700,200,*,UP,POLY +S 1200,1300,1200,1700,200,*,UP,POLY +S 1200,3500,1200,5500,200,*,UP,POLY +S 2400,3500,2400,5500,200,*,UP,POLY +S 3600,3500,3600,5500,200,*,UP,POLY +S 4800,3500,4800,5500,200,*,UP,POLY +S 1000,3900,4200,3900,400,*,RIGHT,ALU1 +S 1200,5500,1200,9400,200,1,UP,PTRANS +S 600,5700,600,9200,600,*,DOWN,PDIF +S 1800,5700,1800,9200,600,*,DOWN,PDIF +S 2400,5500,2400,9400,200,2,UP,PTRANS +S 3600,5500,3600,9400,200,3,UP,PTRANS +S 3000,5700,3000,9200,600,*,DOWN,PDIF +S 1200,4900,2400,4900,600,*,RIGHT,POLY +S 3600,4900,4800,4900,600,*,RIGHT,POLY +S 1900,4900,5000,4900,400,*,LEFT,ALU1 +S 5400,5700,5400,8100,600,*,DOWN,PDIF +S 4800,5500,4800,8300,200,4,UP,PTRANS +S 4200,5700,4200,8100,600,*,UP,PDIF +S 4000,8500,4000,9200,400,*,UP,PDIF +S 4800,8400,4800,8700,200,*,DOWN,POLY +S 1000,4000,1000,6000,400,z,DOWN,CALU1 +V 5100,9300,CONT_BODY_N,* +V 3300,700,CONT_BODY_P,* +V 2300,700,CONT_BODY_P,* +V 5400,3000,CONT_DIF_N,* +V 1800,7000,CONT_DIF_P,* +V 1800,6000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 4200,6000,CONT_DIF_P,* +V 600,7000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 600,9000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,9000,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 600,3000,CONT_DIF_N,* +V 600,2000,CONT_DIF_N,* +V 3000,3000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 1800,2000,CONT_DIF_N,* +V 1800,3000,CONT_DIF_N,* +V 4200,3000,CONT_DIF_N,* +V 4200,2000,CONT_DIF_N,* +V 5400,2000,CONT_DIF_N,* +V 2200,4900,CONT_POLY,* +V 3800,4900,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/iv1_x8.vbe b/pdks/symbolic/msxlib/cells/iv1_x8.vbe new file mode 100644 index 000000000..02c61a080 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_x8.vbe @@ -0,0 +1,26 @@ +ENTITY iv1_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_a : NATURAL := 22; + CONSTANT rdown_a_z : NATURAL := 320; + CONSTANT rup_a_z : NATURAL := 410; + CONSTANT tphl_a_z : NATURAL := 33; + CONSTANT tplh_a_z : NATURAL := 37; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END iv1_x8; + +ARCHITECTURE behaviour_data_flow OF iv1_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on iv1_x8" + SEVERITY WARNING; + z <= not (a) after 700 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/iv1_y2.ap b/pdks/symbolic/msxlib/cells/iv1_y2.ap new file mode 100644 index 000000000..7df6e392f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_y2.ap @@ -0,0 +1,50 @@ +V ALLIANCE : 6 +H iv1_y2,P, 8/ 8/2014,100 +A 0,0,3000,10000 +R 1000,2000,ref_ref,z_20 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,a_50 +R 2000,6000,ref_ref,a_60 +R 1000,7000,ref_ref,z_70 +R 2000,4000,ref_ref,a_40 +R 1000,3000,ref_ref,z_30 +R 2000,7000,ref_ref,z_70 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 2000,3900,2000,6100,400,*,DOWN,ALU1 +S 2000,4000,2000,6000,400,a,DOWN,CALU1 +S 1000,2300,1000,2900,600,*,UP,NDIF +S 1600,1300,1600,1700,200,*,UP,POLY +S 1600,3300,1600,5500,200,*,UP,POLY +S 2300,1900,2300,3100,600,*,UP,NDIF +S 1600,1700,1600,3300,200,2,DOWN,NTRANS +S 1200,1900,1200,3100,400,*,DOWN,NDIF +S 1200,5900,1200,9100,400,*,UP,PDIF +S 1600,5700,1600,9300,200,1,UP,PTRANS +S 2200,5900,2200,9100,800,*,DOWN,PDIF +S 1600,9300,1600,9700,200,*,DOWN,POLY +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1000,1900,1000,7100,400,*,UP,ALU1 +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,3000,5000,10000,iv1_y2,LEFT,TALU8 +S 0,2200,3000,2200,5200,*,LEFT,PWELL +S 0,7600,3000,7600,5600,*,LEFT,NWELL +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 1000,6100,1000,6700,600,*,UP,PDIF +S 2200,7900,2200,9300,400,*,UP,ALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 1000,7000,2000,7000,600,*,RIGHT,ALU1 +S 2200,700,2200,3100,400,*,UP,ALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 1000,2200,CONT_DIF_N,* +V 1000,3000,CONT_DIF_N,* +V 1000,6000,CONT_DIF_P,* +V 2000,4700,CONT_POLY,* +V 2200,2000,CONT_DIF_N,* +V 2200,9000,CONT_DIF_P,* +V 2200,8000,CONT_DIF_P,* +V 1000,6800,CONT_DIF_P,* +V 2200,3000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/iv1_y2.vbe b/pdks/symbolic/msxlib/cells/iv1_y2.vbe new file mode 100644 index 000000000..db20bd0c1 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/iv1_y2.vbe @@ -0,0 +1,26 @@ +ENTITY iv1_y2 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_a : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 1420; + CONSTANT rup_a_z : NATURAL := 1640; + CONSTANT tphl_a_z : NATURAL := 36; + CONSTANT tplh_a_z : NATURAL := 38; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END iv1_y2; + +ARCHITECTURE behaviour_data_flow OF iv1_y2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on iv1_y2" + SEVERITY WARNING; + z <= not (a) after 700 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/mxi2_x05.ap b/pdks/symbolic/msxlib/cells/mxi2_x05.ap new file mode 100644 index 000000000..618a5c112 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/mxi2_x05.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H mxi2_x05,P, 8/ 8/2014,100 +A 0,0,7000,10000 +R 3000,2000,ref_ref,z_20 +R 1000,5000,ref_ref,s_50 +R 1000,6000,ref_ref,s_60 +R 1000,7000,ref_ref,s_70 +R 2000,7000,ref_ref,s_70 +R 3000,7000,ref_ref,s_70 +R 4000,7000,ref_ref,s_70 +R 5000,7000,ref_ref,s_70 +R 1000,4000,ref_ref,a1_40 +R 2000,4000,ref_ref,a1_40 +R 2000,5000,ref_ref,a1_50 +R 3000,5000,ref_ref,a1_50 +R 2000,6000,ref_ref,a1_60 +R 3000,6000,ref_ref,z_60 +R 4000,6000,ref_ref,z_60 +R 4000,2000,ref_ref,z_20 +R 3000,4000,ref_ref,a0_40 +R 3000,3000,ref_ref,a0_30 +R 2000,3000,ref_ref,a0_30 +R 1000,3000,ref_ref,a0_30 +R 1000,2000,ref_ref,a0_30 +R 5000,6000,ref_ref,s_60 +R 5000,5000,ref_ref,s_50 +R 4000,3000,ref_ref,z_30 +R 4000,4000,ref_ref,z_40 +R 4000,5000,ref_ref,z_50 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 2100,700,2900,700,600,*,RIGHT,PTIE +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,7000,5000,10000,mxi2_x05,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 900,4000,2000,4000,600,*,RIGHT,ALU1 +S 1000,3000,3000,3000,400,*,LEFT,ALU1 +S 1000,4900,1000,7000,600,*,UP,ALU1 +S 2000,3900,2000,6100,400,*,UP,ALU1 +S 1000,7900,1000,9300,400,*,UP,ALU1 +S 5000,7900,5000,9300,400,*,UP,ALU1 +S 6400,6000,6400,6600,600,*,UP,PDIF +S 1000,5000,1600,5000,600,*,RIGHT,POLY +S 2000,5000,3200,5000,600,*,RIGHT,ALU1 +S 4000,2000,4000,6000,400,*,DOWN,ALU1 +S 2500,2000,4000,2000,400,*,LEFT,ALU1 +S 3000,6000,4000,6000,600,*,RIGHT,ALU1 +S 2500,1900,4000,1900,400,*,LEFT,ALU1 +S 2400,4200,2400,5600,200,*,DOWN,POLY +S 2400,4200,3000,4200,200,*,RIGHT,POLY +S 3200,5000,3600,5000,600,*,RIGHT,POLY +S 1000,2000,1000,3000,600,*,DOWN,ALU1 +S 3000,3000,3000,4100,600,*,DOWN,ALU1 +S 5000,4900,5000,7000,600,*,DOWN,ALU1 +S 1000,7000,5100,7000,400,*,RIGHT,ALU1 +S 4900,5000,5500,5000,600,*,RIGHT,ALU1 +S 1000,2000,1000,3000,400,a0,UP,CALU1 +S 2000,3000,2000,3000,400,a0,LEFT,CALU1 +S 3000,3000,3000,4000,400,a0,UP,CALU1 +S 4000,2000,4000,6000,400,z,UP,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 3000,6000,3000,6000,400,z,LEFT,CALU1 +S 2000,4000,2000,6000,400,a1,UP,CALU1 +S 1000,4000,1000,4000,400,a1,LEFT,CALU1 +S 3000,5000,3000,5000,400,a1,LEFT,CALU1 +S 1000,5000,1000,7000,400,s,UP,CALU1 +S 5000,5000,5000,7000,400,s,DOWN,CALU1 +S 2000,7000,2000,7000,400,s,LEFT,CALU1 +S 3000,7000,3000,7000,400,s,LEFT,CALU1 +S 4000,7000,4000,7000,400,s,LEFT,CALU1 +S 3600,5600,3600,7600,200,4,DOWN,PTRANS +S 3000,5800,3000,7400,600,*,UP,PDIF +S 2400,5600,2400,7600,200,3,DOWN,PTRANS +S 2000,5800,2000,7400,400,n1,UP,PDIF +S 1600,5600,1600,7600,200,1,DOWN,PTRANS +S 4400,5600,4400,7600,200,2,DOWN,PTRANS +S 4000,5800,4000,7400,400,n2,UP,PDIF +S 900,5800,900,8100,600,*,DOWN,PDIF +S 1000,5800,1000,8100,600,*,DOWN,PDIF +S 1600,7600,1600,8000,200,*,UP,POLY +S 2400,7600,2400,8000,200,*,UP,POLY +S 3600,7600,3600,8000,200,*,UP,POLY +S 4400,7600,4400,8000,200,*,UP,POLY +S 5100,5800,5100,8100,800,*,DOWN,PDIF +S 5800,5600,5800,7400,200,1s,DOWN,PTRANS +S 6200,5800,6200,7200,400,*,DOWN,PDIF +S 5800,7400,5800,7800,200,*,UP,POLY +S 1800,3500,1800,4900,200,*,UP,POLY +S 2600,1900,2600,2400,1000,*,UP,NDIF +S 3200,1700,3200,2600,200,8,UP,NTRANS +S 2000,1700,2000,2600,200,7,UP,NTRANS +S 3600,1900,3600,2400,600,n4,UP,NDIF +S 4000,1700,4000,2600,200,6,UP,NTRANS +S 1600,1900,1600,2400,600,n3,UP,NDIF +S 1200,1700,1200,2600,200,5,UP,NTRANS +S 600,800,600,2400,600,*,UP,NDIF +S 4900,1900,4900,2400,1200,*,UP,NDIF +S 4000,1300,4000,1700,200,*,DOWN,POLY +S 3200,1300,3200,1700,200,*,DOWN,POLY +S 2000,1300,2000,1700,200,*,DOWN,POLY +S 1200,1300,1200,1700,200,*,DOWN,POLY +S 5800,1300,5800,1700,200,*,DOWN,POLY +S 5800,1700,5800,2600,200,2s,UP,NTRANS +S 6200,1900,6200,2400,400,*,UP,NDIF +S 6400,2200,6400,6800,400,*,DOWN,ALU1 +S 5800,2600,5800,5200,200,*,UP,POLY +S 5000,700,5000,2100,400,*,DOWN,ALU1 +S 4800,3400,6400,3400,400,*,RIGHT,ALU1 +S 4400,3400,5000,3400,600,*,LEFT,POLY +S 4000,3200,5000,3200,200,*,RIGHT,POLY +S 4400,3200,4400,5600,200,*,DOWN,POLY +S 4000,2600,4000,3200,200,*,UP,POLY +S 3200,2600,3200,4000,200,*,UP,POLY +S 2000,2600,2000,3600,200,*,UP,POLY +S 1200,2600,1200,4000,200,*,UP,POLY +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 3000,700,CONT_BODY_P,* +V 2000,700,CONT_BODY_P,* +V 600,900,CONT_DIF_N,* +V 3000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 2600,2000,CONT_DIF_N,* +V 1000,8000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 3200,5000,CONT_POLY,* +V 1100,5000,CONT_POLY,* +V 5400,5000,CONT_POLY,* +V 6400,5900,CONT_DIF_P,sn +V 6400,6700,CONT_DIF_P,sn +V 5000,2000,CONT_DIF_N,* +V 6400,2300,CONT_DIF_N,sn +V 4900,3400,CONT_POLY,sn +EOF diff --git a/pdks/symbolic/msxlib/cells/mxi2_x05.vbe b/pdks/symbolic/msxlib/cells/mxi2_x05.vbe new file mode 100644 index 000000000..1d94014ec --- /dev/null +++ b/pdks/symbolic/msxlib/cells/mxi2_x05.vbe @@ -0,0 +1,40 @@ +ENTITY mxi2_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_s : NATURAL := 8; + CONSTANT cin_a0 : NATURAL := 4; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT rdown_s_z : NATURAL := 4090; + CONSTANT rdown_a0_z : NATURAL := 4100; + CONSTANT rdown_a1_z : NATURAL := 4110; + CONSTANT rup_s_z : NATURAL := 5780; + CONSTANT rup_a0_z : NATURAL := 5850; + CONSTANT rup_a1_z : NATURAL := 5840; + CONSTANT tphl_a0_z : NATURAL := 54; + CONSTANT tphl_a1_z : NATURAL := 54; + CONSTANT tphl_s_z : NATURAL := 58; + CONSTANT tplh_a0_z : NATURAL := 58; + CONSTANT tplh_a1_z : NATURAL := 69; + CONSTANT tplh_s_z : NATURAL := 66; + CONSTANT tphh_s_z : NATURAL := 101; + CONSTANT tpll_s_z : NATURAL := 97; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + s : in BIT; + a0 : in BIT; + a1 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END mxi2_x05; + +ARCHITECTURE behaviour_data_flow OF mxi2_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mxi2_x05" + SEVERITY WARNING; + z <= not (((a0 and not (s)) or (a1 and s))) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/mxi2_x1.ap b/pdks/symbolic/msxlib/cells/mxi2_x1.ap new file mode 100644 index 000000000..35332b11f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/mxi2_x1.ap @@ -0,0 +1,134 @@ +V ALLIANCE : 6 +H mxi2_x1,P, 8/ 8/2014,100 +A 0,0,7000,10000 +R 3000,2000,ref_ref,z_20 +R 1000,5000,ref_ref,s_50 +R 1000,6000,ref_ref,s_60 +R 1000,7000,ref_ref,s_70 +R 2000,7000,ref_ref,s_70 +R 3000,7000,ref_ref,s_70 +R 4000,7000,ref_ref,s_70 +R 5000,7000,ref_ref,s_70 +R 1000,4000,ref_ref,a1_40 +R 2000,4000,ref_ref,a1_40 +R 2000,5000,ref_ref,a1_50 +R 3000,5000,ref_ref,a1_50 +R 2000,6000,ref_ref,a1_60 +R 3000,6000,ref_ref,z_60 +R 4000,6000,ref_ref,z_60 +R 4000,2000,ref_ref,z_20 +R 3000,4000,ref_ref,a0_40 +R 3000,3000,ref_ref,a0_30 +R 2000,3000,ref_ref,a0_30 +R 1000,3000,ref_ref,a0_30 +R 1000,2000,ref_ref,a0_30 +R 5000,6000,ref_ref,s_60 +R 5000,5000,ref_ref,s_50 +R 4000,3000,ref_ref,z_30 +R 4000,4000,ref_ref,z_40 +R 4000,5000,ref_ref,z_50 +S 4400,3800,4400,5600,200,*,DOWN,POLY +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,7000,5000,10000,mxi2_x1,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 5800,3400,5800,5200,200,*,UP,POLY +S 900,4000,2000,4000,600,*,RIGHT,ALU1 +S 1000,3000,3000,3000,400,*,LEFT,ALU1 +S 5200,5800,5200,9200,600,*,DOWN,PDIF +S 6200,5800,6200,7800,400,*,DOWN,PDIF +S 5800,8000,5800,8400,200,*,UP,POLY +S 1000,4900,1000,7000,600,*,UP,ALU1 +S 2000,3900,2000,6100,400,*,UP,ALU1 +S 1000,7900,1000,9300,400,*,UP,ALU1 +S 1600,5600,1600,9400,200,1,DOWN,PTRANS +S 900,5800,900,9200,600,*,DOWN,PDIF +S 2400,5600,2400,9400,200,3,DOWN,PTRANS +S 3600,5600,3600,9400,200,4,DOWN,PTRANS +S 3000,5800,3000,9200,600,*,UP,PDIF +S 4400,5600,4400,9400,200,2,DOWN,PTRANS +S 5000,7900,5000,9300,400,*,UP,ALU1 +S 1600,9400,1600,9700,200,*,UP,POLY +S 2400,9400,2400,9700,200,*,UP,POLY +S 3600,9400,3600,9700,200,*,UP,POLY +S 4400,9400,4400,9700,200,*,UP,POLY +S 6400,6000,6400,6600,600,*,UP,PDIF +S 1000,5000,1600,5000,600,*,RIGHT,POLY +S 2000,5000,3200,5000,600,*,RIGHT,ALU1 +S 4000,2000,4000,6000,400,*,DOWN,ALU1 +S 2500,2000,4000,2000,400,*,LEFT,ALU1 +S 3000,6000,4000,6000,600,*,RIGHT,ALU1 +S 2500,1900,4000,1900,400,*,LEFT,ALU1 +S 2400,4200,2400,5600,200,*,DOWN,POLY +S 2400,4200,3000,4200,200,*,RIGHT,POLY +S 3200,5000,3600,5000,600,*,RIGHT,POLY +S 1000,2000,1000,3000,600,*,DOWN,ALU1 +S 3000,3000,3000,4100,600,*,DOWN,ALU1 +S 5000,4900,5000,7000,600,*,DOWN,ALU1 +S 1000,7000,5100,7000,400,*,RIGHT,ALU1 +S 4900,5000,5500,5000,600,*,RIGHT,ALU1 +S 5800,5600,5800,8000,200,1s,DOWN,PTRANS +S 2000,5800,2000,9200,400,n1,UP,PDIF +S 4000,5800,4000,9200,400,n2,UP,PDIF +S 1000,2000,1000,3000,400,a0,UP,CALU1 +S 2000,3000,2000,3000,400,a0,LEFT,CALU1 +S 3000,3000,3000,4000,400,a0,UP,CALU1 +S 4000,2000,4000,6000,400,z,UP,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 3000,6000,3000,6000,400,z,LEFT,CALU1 +S 2000,4000,2000,6000,400,a1,UP,CALU1 +S 1000,4000,1000,4000,400,a1,LEFT,CALU1 +S 3000,5000,3000,5000,400,a1,LEFT,CALU1 +S 1000,5000,1000,7000,400,s,UP,CALU1 +S 5000,5000,5000,7000,400,s,DOWN,CALU1 +S 2000,7000,2000,7000,400,s,LEFT,CALU1 +S 3000,7000,3000,7000,400,s,LEFT,CALU1 +S 4000,7000,4000,7000,400,s,LEFT,CALU1 +S 1800,3500,1800,4900,200,*,UP,POLY +S 1600,1600,1600,2900,600,n3,UP,NDIF +S 2000,1400,2000,3100,200,7,UP,NTRANS +S 1200,1400,1200,3100,200,5,UP,NTRANS +S 2600,1600,2600,2900,1000,*,UP,NDIF +S 3200,1400,3200,3100,200,8,UP,NTRANS +S 3600,1600,3600,2900,600,n4,UP,NDIF +S 4000,1400,4000,3100,200,6,UP,NTRANS +S 4000,1000,4000,1400,200,*,DOWN,POLY +S 3200,1000,3200,1400,200,*,DOWN,POLY +S 2000,1000,2000,1400,200,*,DOWN,POLY +S 1200,1000,1200,1400,200,*,DOWN,POLY +S 600,890,600,2900,600,*,UP,NDIF +S 6200,2100,6200,2900,400,*,UP,NDIF +S 4900,1600,4900,2900,1200,*,UP,NDIF +S 5000,700,5000,2900,400,*,DOWN,ALU1 +S 6400,2700,6400,6800,400,*,DOWN,ALU1 +S 5800,1900,5800,3100,200,2s,UP,NTRANS +S 5800,1500,5800,1900,200,*,DOWN,POLY +S 4800,3800,6400,3800,400,*,RIGHT,ALU1 +S 4400,3800,5000,3800,600,*,LEFT,POLY +S 4000,3600,5000,3600,200,*,RIGHT,POLY +S 4000,3100,4000,3600,200,*,UP,POLY +S 3200,3100,3200,4000,200,*,UP,POLY +S 2000,3100,2000,3600,200,*,UP,POLY +S 1200,3100,1200,4000,200,*,UP,POLY +V 6300,9300,CONT_BODY_N,* +V 6300,700,CONT_BODY_P,* +V 600,900,CONT_DIF_N,* +V 3000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 2600,2000,CONT_DIF_N,* +V 1000,8000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 5000,9000,CONT_DIF_P,* +V 1000,9000,CONT_DIF_P,* +V 3200,5000,CONT_POLY,* +V 1100,5000,CONT_POLY,* +V 5400,5000,CONT_POLY,* +V 6400,5900,CONT_DIF_P,sn +V 6400,6700,CONT_DIF_P,sn +V 5000,2000,CONT_DIF_N,* +V 5000,2800,CONT_DIF_N,* +V 6400,2800,CONT_DIF_N,sn +V 4900,3800,CONT_POLY,sn +EOF diff --git a/pdks/symbolic/msxlib/cells/mxi2_x1.vbe b/pdks/symbolic/msxlib/cells/mxi2_x1.vbe new file mode 100644 index 000000000..9867123d9 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/mxi2_x1.vbe @@ -0,0 +1,40 @@ +ENTITY mxi2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_s : NATURAL := 11; + CONSTANT cin_a0 : NATURAL := 6; + CONSTANT cin_a1 : NATURAL := 6; + CONSTANT rdown_s_z : NATURAL := 2170; + CONSTANT rdown_a0_z : NATURAL := 2170; + CONSTANT rdown_a1_z : NATURAL := 2180; + CONSTANT rup_s_z : NATURAL := 3040; + CONSTANT rup_a0_z : NATURAL := 3080; + CONSTANT rup_a1_z : NATURAL := 3070; + CONSTANT tphl_a0_z : NATURAL := 51; + CONSTANT tphl_a1_z : NATURAL := 51; + CONSTANT tphl_s_z : NATURAL := 55; + CONSTANT tplh_a0_z : NATURAL := 54; + CONSTANT tplh_a1_z : NATURAL := 65; + CONSTANT tplh_s_z : NATURAL := 62; + CONSTANT tphh_s_z : NATURAL := 101; + CONSTANT tpll_s_z : NATURAL := 99; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + s : in BIT; + a0 : in BIT; + a1 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END mxi2_x1; + +ARCHITECTURE behaviour_data_flow OF mxi2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mxi2_x1" + SEVERITY WARNING; + z <= not (((a0 and not (s)) or (a1 and s))) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd2_x05.ap b/pdks/symbolic/msxlib/cells/nd2_x05.ap new file mode 100644 index 000000000..930e7fbe0 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2_x05.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H nd2_x05,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 2000,6000,ref_ref,a_60 +R 3000,5000,ref_ref,a_50 +R 2000,5000,ref_ref,b_50 +R 2000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,3000,ref_ref,z_30 +R 3000,4000,ref_ref,b_40 +R 3000,6000,ref_ref,a_60 +R 2000,4000,ref_ref,b_40 +R 1000,7000,ref_ref,z_70 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 3000,4000,3000,4000,400,b,LEFT,CALU1 +S 2000,7000,2000,7400,600,*,DOWN,ALU1 +S 700,7300,700,8100,800,*,DOWN,PDIF +S 3300,7300,3300,8100,800,*,DOWN,PDIF +S 1400,7100,1400,8300,200,1,UP,PTRANS +S 2000,7300,2000,8100,1000,*,DOWN,PDIF +S 2600,7100,2600,8300,200,2,UP,PTRANS +S 1400,4500,1400,7200,200,*,DOWN,POLY +S 2600,6000,2600,7200,200,*,DOWN,POLY +S 3000,5000,3000,6000,400,a,DOWN,CALU1 +S 3000,4900,3000,6100,400,*,DOWN,ALU1 +S 2000,6000,3000,6000,600,*,RIGHT,ALU1 +S 2800,2300,2800,2700,200,*,UP,POLY +S 2000,2300,2000,2700,200,*,UP,POLY +S 2000,3700,2000,4300,200,*,UP,POLY +S 2800,3700,2800,6000,200,*,UP,POLY +S 3400,2900,3400,3500,600,*,UP,NDIF +S 1600,2900,1600,3500,400,*,UP,NDIF +S 2000,2700,2000,3700,200,3,DOWN,NTRANS +S 2800,2700,2800,3700,200,4,DOWN,NTRANS +S 2400,2900,2400,3500,600,n1,UP,NDIF +S 3400,700,3400,3100,400,*,DOWN,ALU1 +S 1500,4500,1700,4500,200,*,RIGHT,POLY +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 2000,6000,2000,6000,400,a,LEFT,CALU1 +S 2000,4000,3000,4000,600,*,LEFT,ALU1 +S 1000,7000,2100,7000,400,*,RIGHT,ALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,4000,5000,10000,nd2_x05,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 1000,2900,1500,2900,400,*,RIGHT,ALU1 +S 1000,3000,1500,3000,400,*,RIGHT,ALU1 +S 2000,4000,2000,5100,400,*,UP,ALU1 +S 2000,4000,2000,5000,400,b,DOWN,CALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 1000,2900,1000,7000,400,*,DOWN,ALU1 +S 1000,7100,2100,7100,400,*,RIGHT,ALU1 +S 800,7900,800,9300,400,*,UP,ALU1 +S 3200,7900,3200,9300,400,*,UP,ALU1 +S 1400,8300,1400,8700,200,*,DOWN,POLY +S 2600,8300,2600,8700,200,*,DOWN,POLY +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,7400,CONT_DIF_P,* +V 3400,3000,CONT_DIF_N,* +V 2000,4300,CONT_POLY,* +V 1400,3000,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,* +V 3200,8000,CONT_DIF_P,* +V 2800,6000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd2_x05.vbe b/pdks/symbolic/msxlib/cells/nd2_x05.vbe new file mode 100644 index 000000000..fa5b61e90 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2_x05.vbe @@ -0,0 +1,32 @@ +ENTITY nd2_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3680; + CONSTANT rdown_b_z : NATURAL := 3680; + CONSTANT rup_a_z : NATURAL := 4930; + CONSTANT rup_b_z : NATURAL := 4940; + CONSTANT tphl_a_z : NATURAL := 35; + CONSTANT tphl_b_z : NATURAL := 36; + CONSTANT tplh_b_z : NATURAL := 46; + CONSTANT tplh_a_z : NATURAL := 52; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2_x05; + +ARCHITECTURE behaviour_data_flow OF nd2_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2_x05" + SEVERITY WARNING; + z <= not ((a and b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd2_x1.ap b/pdks/symbolic/msxlib/cells/nd2_x1.ap new file mode 100644 index 000000000..99a3aa2ee --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2_x1.ap @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H nd2_x1,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 2000,4000,ref_ref,b_40 +R 1000,3000,ref_ref,z_30 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +R 3000,4000,ref_ref,a_40 +R 2000,7000,ref_ref,z_70 +R 2000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,b_50 +R 3000,5000,ref_ref,b_50 +R 3000,3000,ref_ref,a_30 +R 2000,3000,ref_ref,a_30 +R 1000,2000,ref_ref,z_20 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 2000,3000,3000,3000,600,*,LEFT,ALU1 +S 0,5000,4000,5000,10000,nd2_x1,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 1400,7700,1400,8000,200,*,DOWN,POLY +S 1400,5600,1400,7600,200,1,UP,PTRANS +S 2000,5800,2000,7400,1000,*,DOWN,PDIF +S 2600,7700,2600,8000,200,*,DOWN,POLY +S 2600,5600,2600,7600,200,2,UP,PTRANS +S 1000,6000,2000,6000,600,*,LEFT,ALU1 +S 2000,6000,2000,7100,400,*,UP,ALU1 +S 2000,6000,2000,7000,400,z,UP,CALU1 +S 3200,5900,3200,9300,400,*,UP,ALU1 +S 800,6900,800,9300,400,*,UP,ALU1 +S 3300,5800,3300,7400,600,*,DOWN,PDIF +S 700,5800,700,7400,600,*,DOWN,PDIF +S 1000,2300,1000,2900,600,*,UP,NDIF +S 1200,1800,1200,3100,400,*,UP,NDIF +S 2000,1800,2000,3100,600,n1,UP,NDIF +S 1600,1600,1600,3300,200,3,DOWN,NTRANS +S 2400,1600,2400,3300,200,4,DOWN,NTRANS +S 1600,1200,1600,1600,200,*,UP,POLY +S 2400,1200,2400,1600,200,*,UP,POLY +S 3000,700,3000,2100,400,*,DOWN,ALU1 +S 3100,1800,3100,3100,600,*,UP,NDIF +S 3000,5000,3000,5000,400,b,LEFT,CALU1 +S 3000,2900,3000,4100,400,*,DOWN,ALU1 +S 3000,3000,3000,4000,400,a,DOWN,CALU1 +S 2000,4000,2000,5000,400,b,DOWN,CALU1 +S 2000,3900,2000,5100,400,*,DOWN,ALU1 +S 2000,3000,2000,3000,400,a,LEFT,CALU1 +S 1400,4800,1400,5600,200,*,DOWN,POLY +S 1600,3300,1600,5200,200,*,UP,POLY +S 1400,5000,1800,5000,600,*,LEFT,POLY +S 1800,5000,3000,5000,600,*,RIGHT,ALU1 +S 2600,3800,2600,5600,200,*,DOWN,POLY +S 2400,3300,2400,4200,200,*,UP,POLY +S 2400,4000,3000,4000,600,*,LEFT,POLY +S 1000,2000,1000,6000,400,z,DOWN,CALU1 +S 1000,1900,1000,6000,400,*,DOWN,ALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,7000,CONT_DIF_P,* +V 2000,6000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 3200,7000,CONT_DIF_P,* +V 3200,6000,CONT_DIF_P,* +V 1000,3000,CONT_DIF_N,* +V 1000,2200,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 3000,4000,CONT_POLY,* +V 1800,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd2_x1.vbe b/pdks/symbolic/msxlib/cells/nd2_x1.vbe new file mode 100644 index 000000000..e179081e7 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY nd2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 2160; + CONSTANT rdown_b_z : NATURAL := 2160; + CONSTANT rup_a_z : NATURAL := 2960; + CONSTANT rup_b_z : NATURAL := 2960; + CONSTANT tphl_a_z : NATURAL := 34; + CONSTANT tphl_b_z : NATURAL := 35; + CONSTANT tplh_b_z : NATURAL := 45; + CONSTANT tplh_a_z : NATURAL := 51; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2_x1; + +ARCHITECTURE behaviour_data_flow OF nd2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2_x1" + SEVERITY WARNING; + z <= not ((a and b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd2_x2.ap b/pdks/symbolic/msxlib/cells/nd2_x2.ap new file mode 100644 index 000000000..946cd482f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2_x2.ap @@ -0,0 +1,74 @@ +V ALLIANCE : 6 +H nd2_x2,P, 9/10/2005,100 +A 0,0,4000,10000 +R 3000,5000,ref_ref,a_50 +R 2000,5000,ref_ref,b_50 +R 2000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 2000,8000,ref_ref,z_80 +R 2000,6000,ref_ref,b_60 +R 3000,6000,ref_ref,b_60 +R 3000,4000,ref_ref,a_40 +R 2000,4000,ref_ref,a_40 +R 1000,7000,ref_ref,z_70 +R 1000,3000,ref_ref,z_30 +R 1000,2000,ref_ref,z_20 +R 3000,3000,ref_ref,a_30 +S 3000,3000,3000,5000,400,a,DOWN,CALU1 +S 1800,3900,1800,4900,200,*,UP,POLY +S 2600,4900,3200,4900,600,*,LEFT,POLY +S 1900,4000,3000,4000,400,*,LEFT,ALU1 +S 3000,6000,3000,6000,400,b,LEFT,CALU1 +S 2800,9400,2800,9700,200,*,UP,POLY +S 1600,9400,1600,9700,200,*,UP,POLY +S 1000,7000,2200,7000,600,*,LEFT,ALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,5000,4000,5000,10000,nd2_x2,LEFT,TALU8 +S 2000,6000,3000,6000,600,*,RIGHT,ALU1 +S 2000,5000,2000,6000,400,b,UP,CALU1 +S 1000,8000,1000,9300,400,*,UP,ALU1 +S 3400,8000,3400,9300,400,*,UP,ALU1 +S 2100,7000,2100,8100,600,*,DOWN,ALU1 +S 2000,7000,2000,8000,400,z,UP,CALU1 +S 3400,5700,3400,9100,600,*,DOWN,PDIF +S 2800,5500,2800,9400,200,2,UP,PTRANS +S 2200,5700,2200,9200,1000,*,DOWN,PDIF +S 1600,5500,1600,9400,200,1,UP,PTRANS +S 1000,5700,1000,9200,1000,*,DOWN,PDIF +S 2000,4800,2000,6000,400,*,UP,ALU1 +S 1600,5100,1600,5500,200,*,DOWN,POLY +S 1200,2100,1200,2900,600,*,UP,NDIF +S 1400,800,1400,3700,400,*,UP,NDIF +S 1800,600,1800,3900,200,3,DOWN,NTRANS +S 1800,300,1800,600,200,*,UP,POLY +S 2200,800,2200,3700,600,n1,UP,NDIF +S 2600,600,2600,3900,200,4,DOWN,NTRANS +S 2600,300,2600,600,200,*,UP,POLY +S 3200,700,3200,2100,400,*,DOWN,ALU1 +S 3300,800,3300,3700,600,*,UP,NDIF +S 1100,1900,1100,3100,600,*,UP,ALU1 +S 2000,4000,2000,4000,400,a,LEFT,CALU1 +S 1800,4900,2000,4900,600,*,RIGHT,ALU1 +S 2800,4700,2800,5500,200,*,UP,POLY +S 2600,3900,2600,5100,200,*,UP,POLY +S 1000,1900,1000,7000,400,*,DOWN,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 3000,2900,3000,5100,400,*,DOWN,ALU1 +V 1200,2200,CONT_DIF_N,* +V 1000,8100,CONT_DIF_P,* +V 3400,8100,CONT_DIF_P,* +V 1000,9100,CONT_DIF_P,* +V 3400,9100,CONT_DIF_P,* +V 2200,7000,CONT_DIF_P,* +V 2200,8000,CONT_DIF_P,* +V 3000,4900,CONT_POLY,* +V 1800,4900,CONT_POLY,* +V 1200,3000,CONT_DIF_N,* +V 3200,2000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd2_x2.vbe b/pdks/symbolic/msxlib/cells/nd2_x2.vbe new file mode 100644 index 000000000..3b871e5b6 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY nd2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 8; + CONSTANT cin_b : NATURAL := 8; + CONSTANT rdown_a_z : NATURAL := 1110; + CONSTANT rdown_b_z : NATURAL := 1110; + CONSTANT rup_a_z : NATURAL := 1520; + CONSTANT rup_b_z : NATURAL := 1520; + CONSTANT tphl_a_z : NATURAL := 33; + CONSTANT tphl_b_z : NATURAL := 34; + CONSTANT tplh_b_z : NATURAL := 44; + CONSTANT tplh_a_z : NATURAL := 50; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2_x2; + +ARCHITECTURE behaviour_data_flow OF nd2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2_x2" + SEVERITY WARNING; + z <= not ((a and b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd2_x4.ap b/pdks/symbolic/msxlib/cells/nd2_x4.ap new file mode 100644 index 000000000..7868c0c41 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2_x4.ap @@ -0,0 +1,114 @@ +V ALLIANCE : 6 +H nd2_x4,P,29/ 9/2005,100 +A 0,0,6000,10000 +R 3000,2000,ref_ref,z_20 +R 2000,4000,ref_ref,a_40 +R 1000,3000,ref_ref,z_30 +R 5000,6000,ref_ref,b_60 +R 4000,8000,ref_ref,z_80 +R 5000,4000,ref_ref,a_40 +R 4000,6000,ref_ref,b_60 +R 2000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +R 3000,3000,ref_ref,z_30 +R 3000,7000,ref_ref,z_70 +R 4000,7000,ref_ref,z_70 +R 2000,5000,ref_ref,a_50 +R 3000,4000,ref_ref,a_40 +R 4000,4000,ref_ref,a_40 +R 4000,5000,ref_ref,b_50 +R 5000,5000,ref_ref,a_50 +R 2000,6000,ref_ref,z_60 +S 4600,4200,5000,4200,200,*,RIGHT,POLY +S 4600,3800,4600,4300,200,*,UP,POLY +S 3800,6000,5100,6000,400,*,RIGHT,ALU1 +S 5000,6000,5000,6000,400,b,UP,CALU1 +S 5000,3900,5000,5100,400,*,UP,ALU1 +S 5000,4000,5000,5000,400,a,UP,CALU1 +S 1000,2900,1000,6100,400,*,DOWN,ALU1 +S 600,7900,600,9300,400,*,UP,ALU1 +S 2400,4800,2400,5600,200,*,DOWN,POLY +S 4600,300,4600,600,200,*,UP,POLY +S 3800,300,3800,600,200,*,UP,POLY +S 2600,300,2600,600,200,*,UP,POLY +S 1800,300,1800,600,200,*,UP,POLY +S 3000,7000,3000,7000,400,z,LEFT,CALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 3000,4000,3000,4000,400,a,LEFT,CALU1 +S 3100,1900,3100,3000,600,*,DOWN,ALU1 +S 2000,3000,2000,3000,400,z,LEFT,CALU1 +S 3000,2000,3000,3000,400,z,DOWN,CALU1 +S 1000,3000,3200,3000,600,*,RIGHT,ALU1 +S 3900,4900,3900,6000,600,*,DOWN,ALU1 +S 3700,4300,3700,4800,400,*,UP,POLY +S 1800,3800,1800,4700,200,*,UP,POLY +S 5200,800,5200,3600,600,*,UP,NDIF +S 5200,700,5200,2100,400,*,DOWN,ALU1 +S 4600,600,4600,3800,200,8,DOWN,NTRANS +S 4200,900,4200,3600,600,n2,UP,NDIF +S 2600,4200,3800,4200,200,*,RIGHT,POLY +S 3800,600,3800,3800,200,7,DOWN,NTRANS +S 3200,800,3200,3600,600,*,UP,NDIF +S 2600,600,2600,3800,200,6,DOWN,NTRANS +S 2200,900,2200,3600,600,n1,UP,NDIF +S 1800,600,1800,3800,200,5,DOWN,NTRANS +S 1100,800,1100,3600,600,*,UP,NDIF +S 1200,700,1200,2100,400,*,DOWN,ALU1 +S 2000,3900,5000,3900,400,*,RIGHT,ALU1 +S 2000,4000,5000,4000,400,*,RIGHT,ALU1 +S 4000,5000,4000,6000,400,b,DOWN,CALU1 +S 4000,7000,4000,8000,400,z,UP,CALU1 +S 4100,7000,4100,8100,600,*,DOWN,ALU1 +S 3000,5800,3000,9200,600,*,DOWN,PDIF +S 5400,7900,5400,9300,400,*,UP,ALU1 +S 3000,7900,3000,9300,400,*,UP,ALU1 +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,5000,6000,5000,10000,nd2_x4,LEFT,TALU8 +S 1200,5600,1200,9400,200,1,UP,PTRANS +S 600,5800,600,9200,600,*,DOWN,PDIF +S 1200,9400,1200,9700,200,*,DOWN,POLY +S 1800,5800,1800,9200,1000,*,DOWN,PDIF +S 2400,5600,2400,9400,200,2,UP,PTRANS +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 3600,5600,3600,9400,200,3,UP,PTRANS +S 4800,5600,4800,9400,200,4,UP,PTRANS +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 5400,5800,5400,9200,600,*,DOWN,PDIF +S 4200,5800,4200,9200,1000,*,DOWN,PDIF +S 1200,5200,2400,5200,200,*,RIGHT,POLY +S 3600,5200,4800,5200,200,*,RIGHT,POLY +S 3600,9400,3600,9700,200,*,DOWN,POLY +S 4800,9400,4800,9700,200,*,DOWN,POLY +S 2000,4000,2000,5000,400,a,DOWN,CALU1 +S 2000,4000,2000,5100,400,*,DOWN,ALU1 +S 2000,6000,2000,7000,400,z,UP,CALU1 +S 1000,3000,1000,6000,400,z,DOWN,CALU1 +S 1800,7000,4200,7000,400,*,LEFT,ALU1 +S 1800,7100,4200,7100,400,*,LEFT,ALU1 +S 1000,6000,2000,6000,600,*,RIGHT,ALU1 +S 1900,5900,1900,7100,600,*,DOWN,ALU1 +V 4200,7100,CONT_DIF_P,* +V 3800,5000,CONT_POLY,* +V 5200,1000,CONT_DIF_N,* +V 5200,2000,CONT_DIF_N,* +V 3200,3000,CONT_DIF_N,* +V 3200,2000,CONT_DIF_N,* +V 1200,1000,CONT_DIF_N,* +V 1200,2000,CONT_DIF_N,* +V 5000,4400,CONT_POLY,* +V 4200,8000,CONT_DIF_P,* +V 5400,9000,CONT_DIF_P,* +V 3000,9000,CONT_DIF_P,* +V 600,9000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 2000,5000,CONT_POLY,* +V 1800,7000,CONT_DIF_P,* +V 1800,6000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd2_x4.vbe b/pdks/symbolic/msxlib/cells/nd2_x4.vbe new file mode 100644 index 000000000..481418a22 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY nd2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_a : NATURAL := 15; + CONSTANT cin_b : NATURAL := 14; + CONSTANT rdown_a_z : NATURAL := 570; + CONSTANT rdown_b_z : NATURAL := 570; + CONSTANT rup_a_z : NATURAL := 780; + CONSTANT rup_b_z : NATURAL := 780; + CONSTANT tphl_a_z : NATURAL := 32; + CONSTANT tphl_b_z : NATURAL := 34; + CONSTANT tplh_b_z : NATURAL := 43; + CONSTANT tplh_a_z : NATURAL := 49; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2_x4; + +ARCHITECTURE behaviour_data_flow OF nd2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2_x4" + SEVERITY WARNING; + z <= not ((a and b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd2a_x1.ap b/pdks/symbolic/msxlib/cells/nd2a_x1.ap new file mode 100644 index 000000000..a56c70ab0 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2a_x1.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 6 +H nd2a_x1,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 2000,2000,ref_ref,a_20 +R 3000,2000,ref_ref,a_20 +R 2000,5000,ref_ref,b_50 +R 2000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 2000,8000,ref_ref,z_80 +R 2000,6000,ref_ref,b_60 +R 3000,6000,ref_ref,b_60 +R 3000,7000,ref_ref,b_70 +R 3000,4000,ref_ref,a_40 +R 3000,3000,ref_ref,a_30 +R 1000,7000,ref_ref,z_70 +R 1000,3000,ref_ref,z_30 +R 1000,2000,ref_ref,z_20 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 3800,8300,3800,8700,200,*,UP,POLY +S 2600,8300,2600,8700,200,*,UP,POLY +S 1400,8300,1400,8700,200,*,UP,POLY +S 1400,4700,1400,6300,200,*,DOWN,POLY +S 3800,3300,3800,6300,200,*,DOWN,POLY +S 3000,4000,3600,4000,600,*,LEFT,ALU1 +S 2000,2000,3000,2000,600,*,RIGHT,ALU1 +S 2000,2000,2000,2000,400,a,LEFT,CALU1 +S 2600,3700,2600,6300,200,*,DOWN,POLY +S 2400,3300,2400,3800,200,*,UP,POLY +S 2400,1200,2400,1600,200,*,DOWN,POLY +S 2400,1600,2400,3300,200,4,DOWN,NTRANS +S 2000,1800,2000,3100,600,n1,UP,NDIF +S 1600,3300,1600,4500,200,*,UP,POLY +S 1600,1200,1600,1600,200,*,DOWN,POLY +S 1600,1600,1600,3300,200,3,DOWN,NTRANS +S 1200,1800,1200,3100,400,*,UP,NDIF +S 1000,2100,1000,2900,600,*,UP,NDIF +S 2800,5000,4400,5000,400,*,RIGHT,ALU1 +S 4400,2900,4400,7500,400,*,DOWN,ALU1 +S 3200,900,3200,3100,600,*,UP,NDIF +S 3800,1900,3800,2300,200,*,DOWN,POLY +S 4200,2500,4200,3100,400,*,UP,NDIF +S 3800,2300,3800,3300,200,2a,DOWN,NTRANS +S 4400,6700,4400,7300,600,*,UP,PDIF +S 3200,6500,3200,8100,600,*,DOWN,PDIF +S 4200,6500,4200,8100,400,*,DOWN,PDIF +S 3800,6300,3800,8300,200,1a,UP,PTRANS +S 700,6500,700,8100,600,*,DOWN,PDIF +S 2000,6500,2000,8100,1000,*,DOWN,PDIF +S 1400,6300,1400,8300,200,1,UP,PTRANS +S 2600,6300,2600,8300,200,2,UP,PTRANS +S 3200,7900,3200,9300,400,*,UP,ALU1 +S 800,7900,800,9300,400,*,UP,ALU1 +S 3000,1900,3000,4000,400,*,DOWN,ALU1 +S 3000,2000,3000,4000,400,a,DOWN,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,5000,5000,5000,10000,nd2a_x1,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 1000,7000,2000,7000,600,*,LEFT,ALU1 +S 2000,7000,2000,8100,400,*,DOWN,ALU1 +S 3000,6000,3000,7100,400,*,UP,ALU1 +S 2000,6000,3000,6000,600,*,RIGHT,ALU1 +S 3000,6000,3000,7000,400,b,UP,CALU1 +S 2000,5000,2000,6000,400,b,UP,CALU1 +S 2000,7000,2000,8000,400,z,UP,CALU1 +S 2000,4800,2000,6000,400,*,UP,ALU1 +S 1800,4900,2000,4900,600,*,RIGHT,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1000,1900,1000,7000,400,*,DOWN,ALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2900,5000,CONT_POLY,an +V 4400,3000,CONT_DIF_N,an +V 4400,6600,CONT_DIF_P,an +V 4400,7400,CONT_DIF_P,an +V 1000,2200,CONT_DIF_N,* +V 1000,3000,CONT_DIF_N,* +V 3500,4000,CONT_POLY,* +V 800,8000,CONT_DIF_P,* +V 3200,8000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 1800,4900,CONT_POLY,* +V 3200,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd2a_x1.vbe b/pdks/symbolic/msxlib/cells/nd2a_x1.vbe new file mode 100644 index 000000000..d6c5c8314 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2a_x1.vbe @@ -0,0 +1,32 @@ +ENTITY nd2a_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 2160; + CONSTANT rdown_a_z : NATURAL := 2160; + CONSTANT rup_b_z : NATURAL := 2960; + CONSTANT rup_a_z : NATURAL := 2960; + CONSTANT tphl_b_z : NATURAL := 36; + CONSTANT tplh_b_z : NATURAL := 45; + CONSTANT tpll_a_z : NATURAL := 78; + CONSTANT tphh_a_z : NATURAL := 75; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2a_x1; + +ARCHITECTURE behaviour_data_flow OF nd2a_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2a_x1" + SEVERITY WARNING; + z <= (not (b) or a) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd2a_x2.ap b/pdks/symbolic/msxlib/cells/nd2a_x2.ap new file mode 100644 index 000000000..657916c74 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2a_x2.ap @@ -0,0 +1,95 @@ +V ALLIANCE : 6 +H nd2a_x2,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 3000,4000,ref_ref,a_40 +R 3000,7000,ref_ref,b_70 +R 3000,6000,ref_ref,b_60 +R 2000,6000,ref_ref,b_60 +R 2000,8000,ref_ref,z_80 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +R 2000,7000,ref_ref,z_70 +R 2000,5000,ref_ref,b_50 +R 2000,2000,ref_ref,a_20 +R 2000,3000,ref_ref,a_30 +R 3000,3000,ref_ref,a_30 +S 1800,4900,2000,4900,600,*,RIGHT,ALU1 +S 2600,300,2600,600,200,*,UP,POLY +S 2600,600,2600,3900,200,4,DOWN,NTRANS +S 2200,800,2200,3700,600,n1,UP,NDIF +S 1800,3900,1800,4500,200,*,UP,POLY +S 1800,300,1800,600,200,*,UP,POLY +S 1800,600,1800,3900,200,3,DOWN,NTRANS +S 1400,800,1400,3700,400,*,UP,NDIF +S 2000,4800,2000,6000,400,*,UP,ALU1 +S 2000,7000,2000,8000,400,z,UP,CALU1 +S 2000,5000,2000,6000,400,b,UP,CALU1 +S 3000,6000,3000,7000,400,b,UP,CALU1 +S 2000,6000,3000,6000,600,*,RIGHT,ALU1 +S 3000,6000,3000,7100,400,*,UP,ALU1 +S 1400,5500,1400,9400,200,1,UP,PTRANS +S 1400,9400,1400,9700,200,*,UP,POLY +S 2000,7000,2000,8100,400,*,DOWN,ALU1 +S 1000,7000,2000,7000,600,*,LEFT,ALU1 +S 1400,5000,1400,5500,200,*,DOWN,POLY +S 2000,5700,2000,9200,1000,*,DOWN,PDIF +S 2600,5500,2600,9400,200,2,UP,PTRANS +S 2600,9400,2600,9700,200,*,UP,POLY +S 2600,3900,2600,5500,200,*,UP,POLY +S 3200,8000,3200,9300,400,*,UP,ALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,5000,5000,10000,nd2a_x2,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 4400,5900,4400,6500,600,*,UP,PDIF +S 4200,5700,4200,8300,400,*,DOWN,PDIF +S 3200,5700,3200,9200,600,*,DOWN,PDIF +S 3800,8400,3800,8900,200,*,UP,POLY +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 3800,3900,3800,5500,200,*,DOWN,POLY +S 3800,5500,3800,8500,200,1a,UP,PTRANS +S 3000,800,3000,3700,400,*,DOWN,NDIF +S 2800,4900,4600,4900,400,*,RIGHT,ALU1 +S 4600,2100,4600,4900,400,*,DOWN,ALU1 +S 4400,4900,4400,6700,400,*,DOWN,ALU1 +S 3800,1800,3800,3300,200,2a,DOWN,NTRANS +S 3200,800,3200,3100,600,*,UP,NDIF +S 4500,2000,4500,3000,600,*,UP,ALU1 +S 4400,2200,4400,3100,600,*,UP,NDIF +S 3800,1400,3800,1800,200,*,DOWN,POLY +S 700,5700,700,9200,600,*,DOWN,PDIF +S 800,8000,800,9300,400,*,UP,ALU1 +S 3200,700,3200,2100,400,*,DOWN,ALU1 +S 3000,3000,3000,4000,400,a,DOWN,CALU1 +S 2000,2000,2000,3000,400,a,DOWN,CALU1 +S 2000,1900,2000,3100,400,*,DOWN,ALU1 +S 1200,2700,1200,3500,600,*,UP,NDIF +S 1000,2700,1000,7000,400,*,DOWN,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 1100,2700,1100,3700,600,*,UP,ALU1 +S 3000,3900,3800,3900,600,*,LEFT,ALU1 +S 3000,2900,3000,4000,600,*,DOWN,ALU1 +S 2000,3000,3100,3000,600,*,RIGHT,ALU1 +V 4300,9300,CONT_BODY_N,* +V 4300,700,CONT_BODY_P,* +V 3200,1000,CONT_DIF_N,* +V 1800,4900,CONT_POLY,* +V 800,8100,CONT_DIF_P,* +V 800,9100,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 3200,8100,CONT_DIF_P,* +V 3200,9100,CONT_DIF_P,* +V 4400,5800,CONT_DIF_P,* +V 4400,6600,CONT_DIF_P,* +V 2900,4900,CONT_POLY,* +V 4400,2100,CONT_DIF_N,* +V 4400,2900,CONT_DIF_N,* +V 3200,2000,CONT_DIF_N,* +V 1200,3600,CONT_DIF_N,* +V 1200,2800,CONT_DIF_N,* +V 3800,3900,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd2a_x2.vbe b/pdks/symbolic/msxlib/cells/nd2a_x2.vbe new file mode 100644 index 000000000..535da810d --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2a_x2.vbe @@ -0,0 +1,32 @@ +ENTITY nd2a_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_b : NATURAL := 8; + CONSTANT cin_a : NATURAL := 6; + CONSTANT rdown_b_z : NATURAL := 1110; + CONSTANT rdown_a_z : NATURAL := 1110; + CONSTANT rup_b_z : NATURAL := 1520; + CONSTANT rup_a_z : NATURAL := 1520; + CONSTANT tphl_b_z : NATURAL := 34; + CONSTANT tplh_b_z : NATURAL := 44; + CONSTANT tpll_a_z : NATURAL := 80; + CONSTANT tphh_a_z : NATURAL := 76; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2a_x2; + +ARCHITECTURE behaviour_data_flow OF nd2a_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2a_x2" + SEVERITY WARNING; + z <= (not (b) or a) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd2ab_x1.ap b/pdks/symbolic/msxlib/cells/nd2ab_x1.ap new file mode 100644 index 000000000..cec8334aa --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2ab_x1.ap @@ -0,0 +1,104 @@ +V ALLIANCE : 6 +H nd2ab_x1,P, 8/ 8/2014,100 +A 0,0,6000,10000 +R 3000,4000,ref_ref,z_40 +R 3000,3000,ref_ref,z_30 +R 3000,2000,ref_ref,z_20 +R 2000,6000,ref_ref,b_60 +R 3000,5000,ref_ref,z_50 +R 2000,2000,ref_ref,z_20 +R 4000,6000,ref_ref,a_60 +R 4000,7000,ref_ref,a_70 +R 1000,7000,ref_ref,b_70 +R 2000,7000,ref_ref,b_70 +R 1000,8000,ref_ref,b_80 +R 5000,7000,ref_ref,a_70 +R 4000,5000,ref_ref,a_50 +R 3000,7000,ref_ref,z_70 +R 3000,6000,ref_ref,z_60 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 600,700,600,3400,400,*,DOWN,ALU1 +S 2000,6000,2000,7000,400,b,DOWN,CALU1 +S 2000,5900,2000,7000,400,*,DOWN,ALU1 +S 4200,700,4200,3100,400,*,DOWN,ALU1 +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 5400,2900,5400,5900,400,*,UP,ALU1 +S 4000,4900,4600,4900,400,*,LEFT,ALU1 +S 4000,5000,4000,7000,400,*,DOWN,ALU1 +S 4000,5000,4000,7000,400,a,DOWN,CALU1 +S 600,4900,600,5900,400,*,UP,ALU1 +S 1000,7000,2000,7000,600,*,RIGHT,ALU1 +S 3000,2000,3000,7000,400,z,UP,CALU1 +S 2000,2000,3000,2000,600,*,RIGHT,ALU1 +S 4200,7900,4200,9300,400,*,UP,ALU1 +S 4000,7000,5100,7000,400,*,LEFT,ALU1 +S 4000,7100,5100,7100,400,*,LEFT,ALU1 +S 3900,3900,5400,3900,400,*,RIGHT,ALU1 +S 1000,7000,1000,8100,400,*,UP,ALU1 +S 1800,3500,1800,4900,400,*,DOWN,ALU1 +S 1800,7900,1800,9300,400,*,UP,ALU1 +S 3000,2000,3000,7100,400,*,DOWN,ALU1 +S 1000,7000,1000,8000,400,b,UP,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 600,4900,2100,4900,400,*,RIGHT,ALU1 +S 2400,4700,2400,5500,200,*,DOWN,POLY +S 2200,4700,2800,4700,200,*,LEFT,POLY +S 2800,2300,2800,4700,200,*,UP,POLY +S 3600,300,3600,700,200,*,DOWN,POLY +S 3600,2400,3600,5500,200,*,DOWN,POLY +S 4800,2000,4800,2400,200,*,DOWN,POLY +S 1200,3900,1200,5500,200,*,DOWN,POLY +S 2800,300,2800,700,200,*,DOWN,POLY +S 4800,7300,4800,7700,200,*,UP,POLY +S 3600,7500,3600,7900,200,*,UP,POLY +S 2400,7500,2400,7900,200,*,UP,POLY +S 1200,7300,1200,7800,200,*,UP,POLY +S 4800,3300,4800,5500,200,*,UP,POLY +S 1200,2600,1200,3000,200,*,DOWN,POLY +S 5200,2600,5200,3100,400,*,UP,NDIF +S 2400,900,2400,2200,400,*,UP,NDIF +S 1600,3200,1600,3700,400,*,UP,NDIF +S 3200,900,3200,2200,600,n1,UP,NDIF +S 600,3200,600,3700,600,*,UP,NDIF +S 4200,900,4200,3100,600,*,UP,NDIF +S 3600,700,3600,2400,200,3z,DOWN,NTRANS +S 2800,700,2800,2400,200,4z,DOWN,NTRANS +S 1200,3000,1200,3900,200,2b,DOWN,NTRANS +S 4800,2400,4800,3300,200,2a,DOWN,NTRANS +S 1800,5700,1800,7300,600,*,DOWN,PDIF +S 800,5700,800,7100,400,*,DOWN,PDIF +S 3600,5500,3600,7500,200,1z,UP,PTRANS +S 2400,5500,2400,7500,200,2z,UP,PTRANS +S 3000,5700,3000,7300,600,*,DOWN,PDIF +S 0,5000,6000,5000,10000,nd2ab_x1,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 1800,5700,1800,8100,600,*,DOWN,PDIF +S 4200,5700,4200,8100,600,*,DOWN,PDIF +S 5200,5700,5200,7100,400,*,DOWN,PDIF +S 4800,5500,4800,7300,200,1a,UP,PTRANS +S 4000,5700,4000,7300,400,*,UP,PDIF +S 1200,5500,1200,7300,200,1b,UP,PTRANS +S 5000,7000,5000,7000,400,a,LEFT,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 1000,700,CONT_BODY_P,* +V 1000,8000,CONT_POLY,* +V 4500,4900,CONT_POLY,* +V 4000,3900,CONT_POLY,an +V 2000,4900,CONT_POLY,bn +V 4200,2000,CONT_DIF_N,* +V 5400,3000,CONT_DIF_N,an +V 4200,3000,CONT_DIF_N,* +V 4200,1000,CONT_DIF_N,* +V 2200,2100,CONT_DIF_N,* +V 1800,3600,CONT_DIF_N,bn +V 600,3300,CONT_DIF_N,* +V 1800,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 600,5800,CONT_DIF_P,bn +V 5400,5800,CONT_DIF_P,an +V 3000,6000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd2ab_x1.vbe b/pdks/symbolic/msxlib/cells/nd2ab_x1.vbe new file mode 100644 index 000000000..755c20966 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2ab_x1.vbe @@ -0,0 +1,32 @@ +ENTITY nd2ab_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 2160; + CONSTANT rdown_b_z : NATURAL := 2160; + CONSTANT rup_a_z : NATURAL := 2960; + CONSTANT rup_b_z : NATURAL := 2970; + CONSTANT tpll_a_z : NATURAL := 81; + CONSTANT tphh_b_z : NATURAL := 70; + CONSTANT tpll_b_z : NATURAL := 77; + CONSTANT tphh_a_z : NATURAL := 76; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2ab_x1; + +ARCHITECTURE behaviour_data_flow OF nd2ab_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2ab_x1" + SEVERITY WARNING; + z <= (a or b) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd2ab_x2.ap b/pdks/symbolic/msxlib/cells/nd2ab_x2.ap new file mode 100644 index 000000000..e609e5596 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2ab_x2.ap @@ -0,0 +1,118 @@ +V ALLIANCE : 6 +H nd2ab_x2,P, 8/ 8/2014,100 +A 0,0,7000,10000 +R 4000,7000,ref_ref,z_70 +R 4000,6000,ref_ref,z_60 +R 4000,5000,ref_ref,z_50 +R 4000,4000,ref_ref,z_40 +R 4000,3000,ref_ref,z_30 +R 3000,2000,ref_ref,z_20 +R 2000,3000,ref_ref,b_30 +R 2000,4000,ref_ref,b_40 +R 5000,6000,ref_ref,a_60 +R 5000,7000,ref_ref,a_70 +R 5000,8000,ref_ref,a_80 +R 6000,8000,ref_ref,a_80 +R 3000,3000,ref_ref,z_30 +R 2000,5000,ref_ref,b_50 +R 3000,4000,ref_ref,b_40 +S 800,9300,1600,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 800,1900,800,6000,400,*,DOWN,ALU1 +S 1400,3100,1400,4700,200,*,UP,POLY +S 1400,1300,1400,1700,200,*,DOWN,POLY +S 2000,1900,2000,2900,600,*,UP,NDIF +S 800,2100,800,2700,600,*,UP,NDIF +S 1400,1700,1400,3100,200,2b,DOWN,NTRANS +S 1000,1900,1000,2900,400,*,UP,NDIF +S 0,5000,7000,5000,10000,nd2ab_x2,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 4200,800,4200,3700,600,n1,UP,NDIF +S 3400,800,3400,3700,400,*,UP,NDIF +S 5000,6000,5000,8000,400,*,DOWN,ALU1 +S 5000,6000,5000,8000,400,a,DOWN,CALU1 +S 5000,6000,5800,6000,600,*,LEFT,ALU1 +S 5000,8000,6100,8000,400,*,LEFT,ALU1 +S 5000,8100,6100,8100,400,*,LEFT,ALU1 +S 6300,7000,6600,7000,600,*,LEFT,ALU1 +S 6600,4900,6600,7100,400,*,DOWN,ALU1 +S 4900,4900,6600,4900,400,*,RIGHT,ALU1 +S 5200,700,5200,3100,400,*,DOWN,ALU1 +S 6400,2700,6400,4900,400,*,UP,ALU1 +S 2800,6900,2800,9200,400,*,UP,ALU1 +S 2800,5700,2800,9200,600,*,DOWN,PDIF +S 4000,5700,4000,9200,600,*,DOWN,PDIF +S 5000,5700,5000,9200,400,*,UP,PDIF +S 6400,2900,6400,3500,600,*,DOWN,NDIF +S 5200,800,5200,3700,600,*,UP,NDIF +S 4600,3900,4600,5500,200,*,DOWN,POLY +S 3400,4700,3400,5500,200,*,DOWN,POLY +S 3800,3900,3800,4700,200,*,UP,POLY +S 3200,4700,3800,4700,200,*,LEFT,POLY +S 1800,5700,1800,8100,400,*,DOWN,PDIF +S 6200,6800,6200,9200,400,*,DOWN,PDIF +S 5200,6800,5200,9200,600,*,DOWN,PDIF +S 6400,6800,6400,7100,600,*,UP,PDIF +S 5800,3900,5800,5900,200,*,UP,POLY +S 2200,8300,2200,8700,200,*,UP,POLY +S 3400,9400,3400,9700,200,*,UP,POLY +S 4600,9400,4600,9700,200,*,UP,POLY +S 5800,9400,5800,9700,200,*,UP,POLY +S 3800,300,3800,600,200,*,DOWN,POLY +S 4600,300,4600,600,200,*,DOWN,POLY +S 5800,2100,5800,2500,200,*,DOWN,POLY +S 3000,3000,4000,3000,600,*,RIGHT,ALU1 +S 3100,1900,3100,3100,600,*,DOWN,ALU1 +S 3000,2000,3000,3000,400,z,DOWN,CALU1 +S 4000,3000,4000,7000,400,z,UP,CALU1 +S 4000,3000,4000,7100,400,*,DOWN,ALU1 +S 3200,2100,3200,2900,600,*,UP,NDIF +S 2200,5500,2200,8300,200,1b,UP,PTRANS +S 5800,6600,5800,9400,200,1a,UP,PTRANS +S 5800,2500,5800,3900,200,2a,DOWN,NTRANS +S 4600,5500,4600,9400,200,1z,UP,PTRANS +S 3400,5500,3400,9400,200,2z,UP,PTRANS +S 4600,600,4600,3900,200,3z,DOWN,NTRANS +S 3800,600,3800,3900,200,4z,DOWN,NTRANS +S 6000,8000,6000,8000,400,a,LEFT,CALU1 +S 1600,6100,1600,6700,600,*,UP,PDIF +S 800,6000,3000,6000,400,*,LEFT,ALU1 +S 3000,4800,3000,6000,400,*,UP,ALU1 +S 2000,3000,2000,5000,400,b,UP,CALU1 +S 2000,4000,3100,4000,400,*,RIGHT,ALU1 +S 3000,4000,3000,4000,400,b,LEFT,CALU1 +S 2000,2900,2000,5100,400,*,UP,ALU1 +S 2000,700,2000,2100,400,*,DOWN,ALU1 +S 1400,4700,1800,4700,200,*,RIGHT,POLY +S 1600,6000,1600,6900,400,*,DOWN,ALU1 +V 1600,9300,CONT_BODY_N,* +V 700,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 800,2800,CONT_DIF_N,bn +V 800,2000,CONT_DIF_N,bn +V 5200,1000,CONT_DIF_N,* +V 3200,2000,CONT_DIF_N,* +V 3000,4900,CONT_POLY,* +V 5800,6000,CONT_POLY,* +V 5200,3000,CONT_DIF_N,* +V 5200,2000,CONT_DIF_N,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 2800,9000,CONT_DIF_P,* +V 2800,8000,CONT_DIF_P,* +V 2800,7000,CONT_DIF_P,* +V 5200,9000,CONT_DIF_P,* +V 6400,2800,CONT_DIF_N,an +V 6400,3600,CONT_DIF_N,an +V 5000,4900,CONT_POLY,an +V 6400,7000,CONT_DIF_P,an +V 3200,3000,CONT_DIF_N,* +V 1600,6800,CONT_DIF_P,bn +V 1600,6000,CONT_DIF_P,bn +V 2000,4900,CONT_POLY,* +V 2000,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd2ab_x2.vbe b/pdks/symbolic/msxlib/cells/nd2ab_x2.vbe new file mode 100644 index 000000000..0e7a960ba --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd2ab_x2.vbe @@ -0,0 +1,32 @@ +ENTITY nd2ab_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_b : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 1120; + CONSTANT rdown_b_z : NATURAL := 1110; + CONSTANT rup_a_z : NATURAL := 1520; + CONSTANT rup_b_z : NATURAL := 1520; + CONSTANT tpll_a_z : NATURAL := 84; + CONSTANT tphh_b_z : NATURAL := 73; + CONSTANT tpll_b_z : NATURAL := 80; + CONSTANT tphh_a_z : NATURAL := 78; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2ab_x2; + +ARCHITECTURE behaviour_data_flow OF nd2ab_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2ab_x2" + SEVERITY WARNING; + z <= (a or b) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd3_x05.ap b/pdks/symbolic/msxlib/cells/nd3_x05.ap new file mode 100644 index 000000000..dc0610f89 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd3_x05.ap @@ -0,0 +1,95 @@ +V ALLIANCE : 6 +H nd3_x05,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 2000,3000,ref_ref,z_30 +R 3000,4000,ref_ref,a_40 +R 3000,5000,ref_ref,c_50 +R 1000,3000,ref_ref,z_30 +R 2000,6000,ref_ref,c_60 +R 4000,6000,ref_ref,b_60 +R 3000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 2000,5000,ref_ref,c_50 +R 4000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,b_60 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 4000,7000,ref_ref,b_70 +R 4000,4000,ref_ref,a_40 +R 3000,3000,ref_ref,a_30 +R 2000,4000,ref_ref,c_40 +R 4000,8000,ref_ref,b_80 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 4400,700,4400,3100,400,*,DOWN,ALU1 +S 3800,2300,3800,2700,200,*,UP,POLY +S 3000,2300,3000,2700,200,*,UP,POLY +S 2200,2300,2200,2700,200,*,UP,POLY +S 1000,2900,2100,2900,400,*,RIGHT,ALU1 +S 1000,3000,2100,3000,400,*,RIGHT,ALU1 +S 4400,2900,4400,3700,600,*,UP,NDIF +S 3800,2700,3800,3900,200,6,UP,NTRANS +S 3400,2900,3400,3700,600,n1,DOWN,NDIF +S 3000,2700,3000,3900,200,5,UP,NTRANS +S 2600,2900,2600,3700,600,n2,UP,NDIF +S 2200,2700,2200,3900,200,4,UP,NTRANS +S 1800,2900,1800,3700,400,*,UP,NDIF +S 3800,3900,3800,7100,200,*,DOWN,POLY +S 3000,3900,3000,5900,200,*,UP,POLY +S 2200,3900,2200,4800,200,*,UP,POLY +S 4000,4000,4000,5100,400,*,DOWN,ALU1 +S 4000,4000,4000,5000,400,a,DOWN,CALU1 +S 1400,5200,1400,7100,200,*,DOWN,POLY +S 1400,5200,1800,5200,200,*,LEFT,POLY +S 2600,5800,2600,7100,200,*,DOWN,POLY +S 3200,7000,3200,7500,400,*,DOWN,ALU1 +S 3800,8300,3800,8700,200,*,DOWN,POLY +S 2600,8300,2600,8700,200,*,DOWN,POLY +S 2000,7300,2000,8100,600,*,DOWN,PDIF +S 3200,7300,3200,8100,1000,*,UP,PDIF +S 3800,7100,3800,8300,200,3,DOWN,PTRANS +S 2600,7100,2600,8300,200,2,DOWN,PTRANS +S 1000,7300,1000,8100,400,*,UP,PDIF +S 1400,7100,1400,8300,200,1,DOWN,PTRANS +S 1400,8300,1400,8700,200,*,DOWN,POLY +S 3000,6000,4000,6000,600,*,RIGHT,ALU1 +S 2000,7900,2000,9300,400,*,DOWN,ALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,5000,5000,5000,10000,nd3_x05,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 800,7000,3200,7000,400,*,LEFT,ALU1 +S 900,7000,900,7500,600,*,DOWN,ALU1 +S 3000,3000,3000,4000,400,a,UP,CALU1 +S 3000,4000,4000,4000,600,*,RIGHT,ALU1 +S 3000,2900,3000,4000,400,*,DOWN,ALU1 +S 2000,4000,2000,6000,400,c,DOWN,CALU1 +S 2000,3900,2000,6100,400,*,UP,ALU1 +S 2000,5000,3000,5000,600,*,LEFT,ALU1 +S 4000,6000,4000,8100,400,*,UP,ALU1 +S 4000,6000,4000,8000,400,b,UP,CALU1 +S 4400,7300,4400,9100,600,*,DOWN,PDIF +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 3000,7000,3000,7000,400,z,LEFT,CALU1 +S 2000,3000,2000,3000,400,z,LEFT,CALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 1000,3000,1000,7500,400,*,DOWN,ALU1 +S 3000,6000,3000,6000,400,b,LEFT,CALU1 +S 3000,5000,3000,5000,400,c,LEFT,CALU1 +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 1600,3000,CONT_DIF_N,* +V 4400,3000,CONT_DIF_N,* +V 4000,4500,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 3200,7400,CONT_DIF_P,* +V 800,7400,CONT_DIF_P,* +V 3000,6000,CONT_POLY,* +V 2000,8000,CONT_DIF_P,* +V 4400,9000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd3_x05.vbe b/pdks/symbolic/msxlib/cells/nd3_x05.vbe new file mode 100644 index 000000000..b18016de9 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd3_x05.vbe @@ -0,0 +1,38 @@ +ENTITY nd3_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_c : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 4240; + CONSTANT rdown_b_z : NATURAL := 4240; + CONSTANT rdown_c_z : NATURAL := 4240; + CONSTANT rup_a_z : NATURAL := 4940; + CONSTANT rup_b_z : NATURAL := 4940; + CONSTANT rup_c_z : NATURAL := 4950; + CONSTANT tphl_a_z : NATURAL := 47; + CONSTANT tphl_b_z : NATURAL := 46; + CONSTANT tphl_c_z : NATURAL := 43; + CONSTANT tplh_c_z : NATURAL := 54; + CONSTANT tplh_b_z : NATURAL := 62; + CONSTANT tplh_a_z : NATURAL := 69; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd3_x05; + +ARCHITECTURE behaviour_data_flow OF nd3_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd3_x05" + SEVERITY WARNING; + z <= not (((a and b) and c)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd3_x1.ap b/pdks/symbolic/msxlib/cells/nd3_x1.ap new file mode 100644 index 000000000..5e402ae98 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd3_x1.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H nd3_x1,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 3000,8000,ref_ref,z_80 +R 4000,4000,ref_ref,a_40 +R 4000,7000,ref_ref,b_70 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +R 1000,7000,ref_ref,z_70 +R 3000,4000,ref_ref,c_40 +R 3000,6000,ref_ref,b_60 +R 4000,5000,ref_ref,a_50 +R 2000,5000,ref_ref,c_50 +R 2000,7000,ref_ref,z_70 +R 3000,7000,ref_ref,z_70 +R 4000,6000,ref_ref,b_60 +R 2000,6000,ref_ref,c_60 +R 2000,4000,ref_ref,c_40 +R 3000,5000,ref_ref,b_50 +R 4000,3000,ref_ref,a_30 +R 3000,3000,ref_ref,a_30 +R 1000,3000,ref_ref,z_30 +R 1000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 2000,3000,ref_ref,a_30 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 3000,3000,3000,3000,400,a,LEFT,CALU1 +S 3000,4000,3000,4000,400,c,LEFT,CALU1 +S 2000,3000,2000,3000,400,a,LEFT,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 3000,7000,3000,8000,400,z,DOWN,CALU1 +S 3100,6900,3100,8100,600,*,DOWN,ALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,5000,5000,10000,nd3_x1,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 1000,6600,1000,8200,400,*,UP,PDIF +S 1400,6400,1400,8400,200,1,DOWN,PTRANS +S 2600,6400,2600,8400,200,2,DOWN,PTRANS +S 2000,6600,2000,8200,1000,*,DOWN,PDIF +S 3800,6400,3800,8400,200,3,DOWN,PTRANS +S 3200,6600,3200,8200,1000,*,UP,PDIF +S 4400,6600,4400,8200,600,*,UP,PDIF +S 1400,8400,1400,8800,200,*,DOWN,POLY +S 2600,8400,2600,8800,200,*,DOWN,POLY +S 3800,8400,3800,8800,200,*,DOWN,POLY +S 2000,7900,2000,9300,400,*,DOWN,ALU1 +S 4400,7900,4400,9300,400,*,DOWN,ALU1 +S 700,7000,3200,7000,600,*,LEFT,ALU1 +S 4000,6000,4000,7100,400,*,UP,ALU1 +S 4000,6000,4000,7000,400,b,UP,CALU1 +S 1400,4700,1400,6400,200,*,DOWN,POLY +S 2000,4000,2000,6000,400,c,DOWN,CALU1 +S 2000,4000,2000,6100,400,*,DOWN,ALU1 +S 2000,4000,3000,4000,600,*,RIGHT,ALU1 +S 3000,5000,3000,6000,400,b,UP,CALU1 +S 3000,4900,3000,6000,400,*,UP,ALU1 +S 3000,6000,4000,6000,600,*,RIGHT,ALU1 +S 4000,3000,4000,5000,400,a,DOWN,CALU1 +S 3800,1300,3800,1600,200,*,UP,POLY +S 3800,1700,3800,3700,200,6,UP,NTRANS +S 3000,1300,3000,1600,200,*,UP,POLY +S 3000,1700,3000,3700,200,5,UP,NTRANS +S 2200,1300,2200,1600,200,*,UP,POLY +S 2200,1700,2200,3700,200,4,UP,NTRANS +S 1800,1900,1800,3500,400,*,UP,NDIF +S 2600,1900,2600,3500,600,n2,UP,NDIF +S 3400,1900,3400,3500,600,n1,DOWN,NDIF +S 4400,1900,4400,3500,600,*,UP,NDIF +S 4400,700,4400,2100,400,*,DOWN,ALU1 +S 1000,2000,2100,2000,400,*,RIGHT,ALU1 +S 1000,2000,1000,7000,400,*,DOWN,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1900,3000,4000,3000,400,*,RIGHT,ALU1 +S 4000,3000,4000,5100,400,*,DOWN,ALU1 +S 1900,2900,4000,2900,400,*,RIGHT,ALU1 +S 2200,3700,2200,4300,200,*,UP,POLY +S 3800,3700,3800,6400,200,*,UP,POLY +S 3000,3700,3000,5600,200,*,UP,POLY +S 2600,5600,2600,6400,200,*,DOWN,POLY +S 1400,4600,1800,4600,200,*,LEFT,POLY +S 1000,1900,2100,1900,400,*,RIGHT,ALU1 +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 3200,8000,CONT_DIF_P,* +V 3200,7000,CONT_DIF_P,* +V 4400,8000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 3000,5800,CONT_POLY,* +V 4400,2000,CONT_DIF_N,* +V 1600,2000,CONT_DIF_N,* +V 4000,4400,CONT_POLY,* +V 2000,4400,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd3_x1.vbe b/pdks/symbolic/msxlib/cells/nd3_x1.vbe new file mode 100644 index 000000000..4ed728739 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY nd3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 2540; + CONSTANT rdown_b_z : NATURAL := 2540; + CONSTANT rdown_c_z : NATURAL := 2540; + CONSTANT rup_a_z : NATURAL := 2960; + CONSTANT rup_b_z : NATURAL := 2960; + CONSTANT rup_c_z : NATURAL := 2960; + CONSTANT tphl_a_z : NATURAL := 45; + CONSTANT tphl_b_z : NATURAL := 44; + CONSTANT tphl_c_z : NATURAL := 41; + CONSTANT tplh_c_z : NATURAL := 52; + CONSTANT tplh_b_z : NATURAL := 59; + CONSTANT tplh_a_z : NATURAL := 67; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd3_x1; + +ARCHITECTURE behaviour_data_flow OF nd3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd3_x1" + SEVERITY WARNING; + z <= not (((a and b) and c)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd3_x2.ap b/pdks/symbolic/msxlib/cells/nd3_x2.ap new file mode 100644 index 000000000..56de21a05 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd3_x2.ap @@ -0,0 +1,100 @@ +V ALLIANCE : 6 +H nd3_x2,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 3000,8000,ref_ref,z_80 +R 3000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 2000,5000,ref_ref,c_50 +R 4000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,b_60 +R 3000,4000,ref_ref,c_40 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 4000,3000,ref_ref,a_30 +R 4000,4000,ref_ref,a_40 +R 1000,3000,ref_ref,z_30 +R 2000,4000,ref_ref,c_40 +R 3000,3000,ref_ref,a_30 +R 4000,6000,ref_ref,b_60 +R 4000,7000,ref_ref,b_70 +R 2000,6000,ref_ref,c_60 +R 1000,2000,ref_ref,z_20 +R 2000,3000,ref_ref,a_30 +R 3000,5000,ref_ref,b_50 +S 2000,3000,2000,3000,400,a,LEFT,CALU1 +S 3000,3000,3000,3000,400,a,LEFT,CALU1 +S 3000,4000,3000,4000,400,c,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 3000,3900,3000,5600,200,*,UP,POLY +S 3800,3900,3800,6100,200,*,DOWN,POLY +S 2600,5300,2600,6100,200,*,DOWN,POLY +S 1400,4700,1400,6100,200,*,DOWN,POLY +S 3000,7000,3000,8000,400,z,UP,CALU1 +S 3100,7000,3100,8100,600,*,DOWN,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 900,6300,900,7300,600,*,UP,ALU1 +S 800,6500,800,7300,600,*,UP,PDIF +S 1800,800,1800,3700,400,*,UP,NDIF +S 4400,800,4400,3700,600,*,UP,NDIF +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,5000,5000,5000,10000,nd3_x2,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 3800,300,3800,600,200,*,UP,POLY +S 3000,300,3000,600,200,*,UP,POLY +S 2200,300,2200,600,200,*,UP,POLY +S 1400,4700,1800,4700,200,*,LEFT,POLY +S 3400,800,3400,3700,600,n1,DOWN,NDIF +S 2600,800,2600,3700,600,n2,UP,NDIF +S 4400,700,4400,2100,400,*,DOWN,ALU1 +S 2000,4000,3000,4000,600,*,RIGHT,ALU1 +S 4000,3000,4000,5100,400,*,DOWN,ALU1 +S 4000,3000,4000,5000,400,a,DOWN,CALU1 +S 4000,6000,4000,7100,400,*,UP,ALU1 +S 3000,6000,4000,6000,400,*,LEFT,ALU1 +S 3000,5900,4000,5900,400,*,LEFT,ALU1 +S 2000,4000,2000,6000,400,c,DOWN,CALU1 +S 2000,4000,2000,6100,400,*,DOWN,ALU1 +S 1000,2000,1600,2000,600,*,RIGHT,ALU1 +S 1900,2900,4000,2900,400,*,LEFT,ALU1 +S 1900,3000,4000,3000,400,*,LEFT,ALU1 +S 3000,5000,3000,6000,600,*,UP,ALU1 +S 3000,5000,3000,6000,400,b,DOWN,CALU1 +S 1000,7000,3200,7000,400,*,LEFT,ALU1 +S 1000,2000,1000,7000,400,*,DOWN,ALU1 +S 2600,9400,2600,9700,200,*,DOWN,POLY +S 1400,9400,1400,9700,200,*,DOWN,POLY +S 3800,9400,3800,9700,200,*,DOWN,POLY +S 2000,7900,2000,9300,400,*,DOWN,ALU1 +S 4400,7900,4400,9300,400,*,DOWN,ALU1 +S 1000,6900,3200,6900,400,*,LEFT,ALU1 +S 1000,6300,1000,9200,400,*,UP,PDIF +S 2000,6300,2000,9200,1000,*,DOWN,PDIF +S 3200,6300,3200,9200,400,*,UP,PDIF +S 4400,6300,4400,9200,600,*,DOWN,PDIF +S 3800,6100,3800,9400,200,1a,DOWN,PTRANS +S 2600,6100,2600,9400,200,1b,DOWN,PTRANS +S 1400,6100,1400,9400,200,1z,DOWN,PTRANS +S 3800,600,3800,3900,200,2a,UP,NTRANS +S 3000,600,3000,3900,200,2b,UP,NTRANS +S 2200,600,2200,3900,200,2c,UP,NTRANS +S 4000,6000,4000,7000,400,b,UP,CALU1 +V 700,700,CONT_BODY_P,* +V 800,7200,CONT_DIF_P,* +V 800,6400,CONT_DIF_P,* +V 4000,5000,CONT_POLY,* +V 1600,2000,CONT_DIF_N,* +V 2000,4500,CONT_POLY,* +V 4400,1000,CONT_DIF_N,* +V 4400,2000,CONT_DIF_N,* +V 3200,7000,CONT_DIF_P,* +V 3200,8000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 4400,8000,CONT_DIF_P,* +V 4400,9000,CONT_DIF_P,* +V 2000,9000,CONT_DIF_P,* +V 3000,5500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd3_x2.vbe b/pdks/symbolic/msxlib/cells/nd3_x2.vbe new file mode 100644 index 000000000..f23d898f2 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY nd3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a : NATURAL := 7; + CONSTANT cin_b : NATURAL := 7; + CONSTANT cin_c : NATURAL := 7; + CONSTANT rdown_a_z : NATURAL := 1540; + CONSTANT rdown_b_z : NATURAL := 1540; + CONSTANT rdown_c_z : NATURAL := 1540; + CONSTANT rup_a_z : NATURAL := 1800; + CONSTANT rup_b_z : NATURAL := 1790; + CONSTANT rup_c_z : NATURAL := 1800; + CONSTANT tphl_a_z : NATURAL := 43; + CONSTANT tphl_b_z : NATURAL := 42; + CONSTANT tphl_c_z : NATURAL := 39; + CONSTANT tplh_c_z : NATURAL := 50; + CONSTANT tplh_b_z : NATURAL := 58; + CONSTANT tplh_a_z : NATURAL := 64; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd3_x2; + +ARCHITECTURE behaviour_data_flow OF nd3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd3_x2" + SEVERITY WARNING; + z <= not (((a and b) and c)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd3_x4.ap b/pdks/symbolic/msxlib/cells/nd3_x4.ap new file mode 100644 index 000000000..1c3f183c4 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd3_x4.ap @@ -0,0 +1,166 @@ +V ALLIANCE : 6 +H nd3_x4,P, 8/ 8/2014,100 +A 0,0,9000,10000 +R 7000,7000,ref_ref,z_70 +R 2000,8000,ref_ref,z_80 +R 3000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 2000,5000,ref_ref,c_50 +R 4000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,b_60 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 4000,7000,ref_ref,z_70 +R 5000,7000,ref_ref,z_70 +R 6000,7000,ref_ref,z_70 +R 7000,5000,ref_ref,c_50 +R 5000,5000,ref_ref,a_50 +R 4000,6000,ref_ref,b_60 +R 5000,6000,ref_ref,b_60 +R 7000,6000,ref_ref,c_60 +R 6000,3000,ref_ref,c_30 +R 6000,5000,ref_ref,b_50 +R 3000,5000,ref_ref,b_50 +R 2000,6000,ref_ref,z_60 +R 2000,4000,ref_ref,c_40 +R 7000,4000,ref_ref,c_40 +R 6000,6000,ref_ref,b_60 +R 1000,3000,ref_ref,z_30 +R 7000,3000,ref_ref,c_30 +R 1000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 3000,2000,ref_ref,z_20 +R 4000,2000,ref_ref,z_20 +R 5000,3000,ref_ref,c_30 +R 4000,3000,ref_ref,c_30 +R 3000,3000,ref_ref,c_30 +R 2000,3000,ref_ref,c_30 +R 3000,4000,ref_ref,b_40 +R 5000,4000,ref_ref,a_40 +S 1000,6000,2000,6000,600,*,RIGHT,ALU1 +S 6000,3000,6000,3000,400,c,LEFT,CALU1 +S 5000,3000,5000,3000,400,c,LEFT,CALU1 +S 4000,3000,4000,3000,400,c,LEFT,CALU1 +S 3000,3000,3000,3000,400,c,LEFT,CALU1 +S 4000,5000,4000,5000,400,a,LEFT,CALU1 +S 5000,6000,5000,6000,400,b,LEFT,CALU1 +S 4000,6000,4000,6000,400,b,LEFT,CALU1 +S 8000,6900,8000,9300,400,*,DOWN,ALU1 +S 800,6900,800,9300,400,*,DOWN,ALU1 +S 3200,7900,3200,9300,400,*,DOWN,ALU1 +S 5600,7900,5600,9300,400,*,DOWN,ALU1 +S 2000,7000,7100,7000,400,*,LEFT,ALU1 +S 6800,7000,6800,8100,400,*,DOWN,ALU1 +S 7000,7000,7000,7000,400,z,LEFT,CALU1 +S 6000,7000,6000,7000,400,z,LEFT,CALU1 +S 5000,7000,5000,7000,400,z,LEFT,CALU1 +S 4000,7000,4000,7000,400,z,LEFT,CALU1 +S 3000,7000,3000,7000,400,z,LEFT,CALU1 +S 4000,2000,4000,2000,400,z,LEFT,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 1000,1900,4500,1900,400,*,RIGHT,ALU1 +S 2600,5500,2600,6000,200,*,DOWN,POLY +S 6600,3900,6600,4400,200,*,UP,POLY +S 1800,800,1800,3700,400,*,UP,NDIF +S 4400,800,4400,3700,600,*,UP,NDIF +S 3800,300,3800,600,200,*,UP,POLY +S 3000,300,3000,600,200,*,UP,POLY +S 2200,300,2200,600,200,*,UP,POLY +S 3800,9200,3800,9700,200,*,DOWN,POLY +S 2600,9200,2600,9700,200,*,DOWN,POLY +S 1400,9200,1400,9700,200,*,DOWN,POLY +S 1400,4700,1800,4700,200,*,LEFT,POLY +S 5000,9200,5000,9700,200,*,DOWN,POLY +S 6200,9200,6200,9700,200,*,DOWN,POLY +S 7400,9200,7400,9700,200,*,DOWN,POLY +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,9000,5000,10000,nd3_x4,LEFT,TALU8 +S 0,2200,9000,2200,5200,*,LEFT,PWELL +S 0,7600,9000,7600,5600,*,LEFT,NWELL +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 1600,800,1600,3700,800,*,UP,NDIF +S 3800,5000,5000,5000,600,*,RIGHT,POLY +S 5000,600,5000,3900,200,10,UP,NTRANS +S 5800,600,5800,3900,200,11,UP,NTRANS +S 6600,600,6600,3900,200,12,UP,NTRANS +S 3800,600,3800,3900,200,09,UP,NTRANS +S 3000,600,3000,3900,200,08,UP,NTRANS +S 2200,600,2200,3900,200,07,UP,NTRANS +S 2600,800,2600,3700,600,n1,UP,NDIF +S 3400,800,3400,3700,600,n2,DOWN,NDIF +S 5400,800,5400,3700,600,n4,DOWN,NDIF +S 6200,800,6200,3700,600,n3,DOWN,NDIF +S 4400,7000,4400,8100,400,*,DOWN,ALU1 +S 2000,6000,2000,8000,400,z,UP,CALU1 +S 2000,6000,2000,8100,400,*,DOWN,ALU1 +S 1400,6000,1400,9300,200,01,DOWN,PTRANS +S 800,6200,800,9100,800,*,UP,PDIF +S 2600,6000,2600,9300,200,02,DOWN,PTRANS +S 2000,6200,2000,9100,1000,*,DOWN,PDIF +S 3200,6200,3200,9100,400,*,UP,PDIF +S 3800,6000,3800,9300,200,03,DOWN,PTRANS +S 4400,6200,4400,9100,400,*,UP,PDIF +S 5000,6000,5000,9300,200,04,DOWN,PTRANS +S 5600,6200,5600,9100,400,*,UP,PDIF +S 6200,6000,6200,9300,200,05,DOWN,PTRANS +S 7400,6000,7400,9300,200,06,DOWN,PTRANS +S 6800,6200,6800,9100,400,*,UP,PDIF +S 8000,6200,8000,9100,800,*,UP,PDIF +S 1400,4700,1400,6000,200,*,DOWN,POLY +S 7400,4300,7400,6000,200,*,DOWN,POLY +S 5800,3900,5800,5600,200,*,UP,POLY +S 5000,3900,5000,6000,200,*,DOWN,POLY +S 3800,3900,3800,6000,200,*,DOWN,POLY +S 3000,3900,3000,5600,200,*,UP,POLY +S 6000,5000,6000,6000,600,*,UP,ALU1 +S 3000,6000,6000,6000,400,*,RIGHT,ALU1 +S 6000,5000,6000,6000,400,b,DOWN,CALU1 +S 7200,700,7200,2100,400,*,DOWN,ALU1 +S 7000,3000,7000,6100,400,*,UP,ALU1 +S 7000,3000,7000,6000,400,c,DOWN,CALU1 +S 7100,3000,7100,6100,400,*,UP,ALU1 +S 1000,2000,1000,6000,400,*,DOWN,ALU1 +S 1000,2000,1000,6000,400,z,DOWN,CALU1 +S 2000,3000,2000,5000,400,c,DOWN,CALU1 +S 2000,3000,2000,5000,600,*,DOWN,ALU1 +S 2000,3000,7000,3000,400,*,RIGHT,ALU1 +S 1000,2000,4500,2000,400,*,RIGHT,ALU1 +S 3000,4000,3000,6000,400,b,UP,CALU1 +S 4000,5000,5000,5000,600,*,RIGHT,ALU1 +S 5000,4000,5000,5000,400,a,DOWN,CALU1 +S 5000,3900,5000,5000,400,*,UP,ALU1 +S 2900,3900,2900,6000,400,*,DOWN,ALU1 +S 3000,3900,3000,6000,400,*,DOWN,ALU1 +S 5000,300,5000,600,200,*,UP,POLY +S 5800,300,5800,600,200,*,UP,POLY +S 6600,300,6600,600,200,*,UP,POLY +S 7200,800,7200,3700,600,*,UP,NDIF +V 8300,700,CONT_BODY_P,* +V 800,7000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 3200,8000,CONT_DIF_P,* +V 5600,8000,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 2000,4500,CONT_POLY,* +V 4400,5000,CONT_POLY,* +V 6800,8000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 4400,7000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 4400,8000,CONT_DIF_P,* +V 6800,7000,CONT_DIF_P,* +V 4400,2000,CONT_DIF_N,* +V 7000,4500,CONT_POLY,* +V 3000,5400,CONT_POLY,* +V 6000,5400,CONT_POLY,* +V 8000,9000,CONT_DIF_P,* +V 5600,9000,CONT_DIF_P,* +V 3200,9000,CONT_DIF_P,* +V 800,9000,CONT_DIF_P,* +V 7200,2000,CONT_DIF_N,* +V 7200,1000,CONT_DIF_N,* +V 1600,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd3_x4.vbe b/pdks/symbolic/msxlib/cells/nd3_x4.vbe new file mode 100644 index 000000000..a46b93f1d --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY nd3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 9000; + CONSTANT cin_a : NATURAL := 13; + CONSTANT cin_b : NATURAL := 15; + CONSTANT cin_c : NATURAL := 15; + CONSTANT rdown_a_z : NATURAL := 770; + CONSTANT rdown_b_z : NATURAL := 770; + CONSTANT rdown_c_z : NATURAL := 770; + CONSTANT rup_a_z : NATURAL := 900; + CONSTANT rup_b_z : NATURAL := 900; + CONSTANT rup_c_z : NATURAL := 900; + CONSTANT tphl_a_z : NATURAL := 37; + CONSTANT tphl_b_z : NATURAL := 41; + CONSTANT tphl_c_z : NATURAL := 42; + CONSTANT tplh_c_z : NATURAL := 63; + CONSTANT tplh_b_z : NATURAL := 56; + CONSTANT tplh_a_z : NATURAL := 48; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd3_x4; + +ARCHITECTURE behaviour_data_flow OF nd3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd3_x4" + SEVERITY WARNING; + z <= not (((a and b) and c)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd4_x05.ap b/pdks/symbolic/msxlib/cells/nd4_x05.ap new file mode 100644 index 000000000..ff25b3e8e --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd4_x05.ap @@ -0,0 +1,122 @@ +V ALLIANCE : 6 +H nd4_x05,P, 8/ 8/2014,100 +A 0,0,6000,10000 +R 5000,5000,ref_ref,b_50 +R 4000,2000,ref_ref,a_20 +R 4000,3000,ref_ref,a_30 +R 5000,6000,ref_ref,b_60 +R 1000,3000,ref_ref,z_30 +R 3000,5000,ref_ref,c_50 +R 2000,4000,ref_ref,d_40 +R 1000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 1000,5000,ref_ref,z_50 +R 4000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,d_50 +R 3000,6000,ref_ref,c_60 +R 2000,6000,ref_ref,c_60 +R 4000,6000,ref_ref,b_60 +R 1000,4000,ref_ref,z_40 +R 3000,7000,ref_ref,z_70 +R 5000,7000,ref_ref,b_70 +R 5000,4000,ref_ref,a_40 +R 3000,3000,ref_ref,d_30 +R 1000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 2000,3000,ref_ref,d_30 +R 3000,4000,ref_ref,c_40 +R 4000,4000,ref_ref,a_40 +S 1100,9300,1900,9300,600,*,LEFT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 5000,4900,5000,7100,400,*,UP,ALU1 +S 5000,5000,5000,7000,400,b,UP,CALU1 +S 4800,4200,4800,6900,200,*,DOWN,POLY +S 4600,3300,4600,4200,200,*,UP,POLY +S 3900,5900,5000,5900,400,*,RIGHT,ALU1 +S 5200,1800,5200,3100,800,*,UP,NDIF +S 4600,1200,4600,1600,200,*,DOWN,POLY +S 3800,1200,3800,1600,200,*,DOWN,POLY +S 3000,1200,3000,1600,200,*,DOWN,POLY +S 2200,1200,2200,1600,200,*,DOWN,POLY +S 2200,3300,2200,4600,200,*,UP,POLY +S 3000,3300,3000,6200,200,*,UP,POLY +S 3800,3300,3800,5700,200,*,UP,POLY +S 1800,1800,1800,3100,400,*,UP,NDIF +S 3400,1800,3400,3100,600,n2,UP,NDIF +S 4600,1600,4600,3300,200,8,DOWN,NTRANS +S 3800,1600,3800,3300,200,7,DOWN,NTRANS +S 4200,1800,4200,3100,600,n1,UP,NDIF +S 3000,1600,3000,3300,200,6,DOWN,NTRANS +S 2200,1600,2200,3300,200,5,DOWN,NTRANS +S 2600,1800,2600,3100,600,n3,UP,NDIF +S 5400,7900,5400,9300,400,*,UP,ALU1 +S 3000,7900,3000,9300,400,*,UP,ALU1 +S 600,7900,600,9300,400,*,UP,ALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 3600,5800,3600,6900,200,*,DOWN,POLY +S 2400,5800,2400,6900,200,*,DOWN,POLY +S 1200,5200,1200,6900,200,*,DOWN,POLY +S 1000,7000,4200,7000,400,*,LEFT,ALU1 +S 1000,7100,4200,7100,400,*,LEFT,ALU1 +S 1900,6100,3000,6100,400,*,LEFT,ALU1 +S 1900,6000,3000,6000,400,*,LEFT,ALU1 +S 600,7100,600,8100,600,*,DOWN,PDIF +S 5300,7100,5300,8100,800,*,DOWN,PDIF +S 3000,7100,3000,8100,600,*,DOWN,PDIF +S 4200,7100,4200,8100,1000,*,UP,PDIF +S 4800,6900,4800,8300,200,4,UP,PTRANS +S 3600,6900,3600,8300,200,3,UP,PTRANS +S 2400,6900,2400,8300,200,2,UP,PTRANS +S 1800,7100,1800,8100,1000,*,DOWN,PDIF +S 1200,6900,1200,8300,200,1,UP,PTRANS +S 4800,8400,4800,8700,200,*,DOWN,POLY +S 3600,8400,3600,8700,200,*,DOWN,POLY +S 2400,8400,2400,8700,200,*,DOWN,POLY +S 1200,8400,1200,8700,200,*,DOWN,POLY +S 0,5000,6000,5000,10000,nd4_x05,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 1200,5200,1800,5200,200,*,RIGHT,POLY +S 3900,6000,5000,6000,400,*,RIGHT,ALU1 +S 1000,1900,2100,1900,400,*,RIGHT,ALU1 +S 1000,2000,2100,2000,400,*,RIGHT,ALU1 +S 1000,2000,1000,7000,400,*,DOWN,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 2000,3000,3000,3000,600,*,LEFT,ALU1 +S 2000,3000,2000,5000,400,d,DOWN,CALU1 +S 2000,3000,2000,5100,400,*,DOWN,ALU1 +S 3000,3000,3000,3000,400,d,LEFT,CALU1 +S 3000,4000,3000,6000,400,c,DOWN,CALU1 +S 3000,3900,3000,6000,400,*,DOWN,ALU1 +S 4000,4000,5000,4000,600,*,RIGHT,ALU1 +S 4000,1900,4000,4000,400,*,DOWN,ALU1 +S 4000,2000,4000,4000,400,a,DOWN,CALU1 +S 5000,4000,5000,4000,400,a,LEFT,CALU1 +S 5200,700,5200,3100,400,*,UP,ALU1 +S 2000,6000,2000,6000,400,c,LEFT,CALU1 +S 4000,6000,4000,6000,400,b,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 3000,7000,3000,7000,400,z,LEFT,CALU1 +S 4000,7000,4000,7000,400,z,LEFT,CALU1 +S 1800,7000,1800,7500,400,*,DOWN,ALU1 +S 4200,7000,4200,7500,400,*,DOWN,ALU1 +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2000,5000,CONT_POLY,* +V 4000,6000,CONT_POLY,* +V 5200,2000,CONT_DIF_N,* +V 2700,6000,CONT_POLY,* +V 3000,8000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 1600,1900,CONT_DIF_N,* +V 4600,4000,CONT_POLY,* +V 5200,3000,CONT_DIF_N,* +V 1800,7400,CONT_DIF_P,* +V 4200,7400,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd4_x05.vbe b/pdks/symbolic/msxlib/cells/nd4_x05.vbe new file mode 100644 index 000000000..49ad07a68 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd4_x05.vbe @@ -0,0 +1,44 @@ +ENTITY nd4_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 4; + CONSTANT cin_d : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 3830; + CONSTANT rdown_b_z : NATURAL := 3830; + CONSTANT rdown_c_z : NATURAL := 3840; + CONSTANT rdown_d_z : NATURAL := 3830; + CONSTANT rup_a_z : NATURAL := 4270; + CONSTANT rup_b_z : NATURAL := 4250; + CONSTANT rup_c_z : NATURAL := 4240; + CONSTANT rup_d_z : NATURAL := 4250; + CONSTANT tphl_a_z : NATURAL := 59; + CONSTANT tphl_b_z : NATURAL := 56; + CONSTANT tphl_c_z : NATURAL := 51; + CONSTANT tphl_d_z : NATURAL := 44; + CONSTANT tplh_d_z : NATURAL := 58; + CONSTANT tplh_c_z : NATURAL := 68; + CONSTANT tplh_b_z : NATURAL := 76; + CONSTANT tplh_a_z : NATURAL := 84; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd4_x05; + +ARCHITECTURE behaviour_data_flow OF nd4_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd4_x05" + SEVERITY WARNING; + z <= not ((((a and b) and c) and d)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd4_x1.ap b/pdks/symbolic/msxlib/cells/nd4_x1.ap new file mode 100644 index 000000000..43c34b5b1 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd4_x1.ap @@ -0,0 +1,123 @@ +V ALLIANCE : 6 +H nd4_x1,P, 8/ 8/2014,100 +A 0,0,6000,10000 +R 2000,8000,ref_ref,z_80 +R 2000,7000,ref_ref,z_70 +R 1000,5000,ref_ref,z_50 +R 4000,7000,ref_ref,z_70 +R 4000,8000,ref_ref,z_80 +R 1000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,d_50 +R 3000,6000,ref_ref,c_60 +R 2000,6000,ref_ref,c_60 +R 4000,6000,ref_ref,b_60 +R 1000,4000,ref_ref,z_40 +R 3000,7000,ref_ref,z_70 +R 5000,7000,ref_ref,b_70 +R 5000,4000,ref_ref,a_40 +R 5000,3000,ref_ref,a_30 +R 3000,3000,ref_ref,d_30 +R 1000,7000,ref_ref,z_70 +R 1000,3000,ref_ref,z_30 +R 5000,5000,ref_ref,a_50 +R 4000,3000,ref_ref,a_30 +R 4000,5000,ref_ref,b_50 +R 2000,4000,ref_ref,d_40 +R 3000,5000,ref_ref,c_50 +R 1000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 2000,3000,ref_ref,d_30 +R 3000,4000,ref_ref,c_40 +R 5000,6000,ref_ref,b_60 +S 2200,700,2200,3900,200,2d,DOWN,NTRANS +S 3000,700,3000,3900,200,2c,DOWN,NTRANS +S 3800,700,3800,3900,200,2b,DOWN,NTRANS +S 4600,700,4600,3900,200,2a,DOWN,NTRANS +S 3600,6600,3600,9300,200,1b,UP,PTRANS +S 4800,6600,4800,9300,200,1a,UP,PTRANS +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,6000,5000,10000,nd4_x1,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 4200,900,4200,3700,600,n1,UP,NDIF +S 3400,900,3400,3700,600,n2,UP,NDIF +S 2600,900,2600,3700,600,n3,UP,NDIF +S 1800,900,1800,3700,400,*,UP,NDIF +S 3800,4100,3800,5700,200,*,UP,POLY +S 2200,3900,2200,4600,200,*,UP,POLY +S 4200,6800,4200,9100,1000,*,UP,PDIF +S 5300,6800,5300,9100,800,*,DOWN,PDIF +S 3000,7900,3000,9300,400,*,UP,ALU1 +S 5400,7900,5400,9300,400,*,UP,ALU1 +S 600,7900,600,9300,400,*,UP,ALU1 +S 2000,7000,2000,8000,400,z,UP,CALU1 +S 4000,7000,4000,8000,400,z,UP,CALU1 +S 1900,7000,1900,8100,600,*,DOWN,ALU1 +S 4100,7000,4100,8100,600,*,DOWN,ALU1 +S 1000,7000,4000,7000,400,*,LEFT,ALU1 +S 1000,7100,4000,7100,400,*,LEFT,ALU1 +S 5000,6000,5000,7000,400,b,UP,CALU1 +S 5000,6000,5000,7100,400,*,UP,ALU1 +S 4000,6000,5000,6000,600,*,RIGHT,ALU1 +S 3900,3000,5000,3000,400,*,RIGHT,ALU1 +S 5000,3000,5000,5000,400,a,DOWN,CALU1 +S 4600,3800,4600,5200,200,*,UP,POLY +S 5000,2900,5000,5100,400,*,DOWN,ALU1 +S 3900,2900,5000,2900,400,*,RIGHT,ALU1 +S 4000,5000,4000,6000,400,b,DOWN,CALU1 +S 4000,4900,4000,6000,400,*,DOWN,ALU1 +S 1900,6000,3000,6000,400,*,LEFT,ALU1 +S 1900,6100,3000,6100,400,*,LEFT,ALU1 +S 5200,900,5200,3700,800,*,UP,NDIF +S 2200,300,2200,700,200,*,DOWN,POLY +S 3000,300,3000,700,200,*,DOWN,POLY +S 3800,300,3800,700,200,*,DOWN,POLY +S 4600,300,4600,700,200,*,DOWN,POLY +S 1000,2000,2100,2000,400,*,RIGHT,ALU1 +S 1000,1900,2100,1900,400,*,RIGHT,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1000,2000,1000,7000,400,*,DOWN,ALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 2000,3000,3000,3000,600,*,LEFT,ALU1 +S 2000,3000,2000,5000,400,d,DOWN,CALU1 +S 2000,3000,2000,5100,400,*,DOWN,ALU1 +S 3000,3000,3000,3000,400,d,LEFT,CALU1 +S 4000,3000,4000,3000,400,a,LEFT,CALU1 +S 3000,4000,3000,6000,400,c,DOWN,CALU1 +S 3000,3900,3000,6000,400,*,DOWN,ALU1 +S 2000,6000,2000,6000,400,c,LEFT,CALU1 +S 3000,7000,3000,7000,400,z,LEFT,CALU1 +S 5200,700,5200,2100,400,*,UP,ALU1 +S 1200,4700,1800,4700,200,*,RIGHT,POLY +S 1800,5900,1800,8200,1000,*,DOWN,PDIF +S 1200,5700,1200,8400,200,1z,UP,PTRANS +S 2400,5700,2400,8400,200,1c,UP,PTRANS +S 700,5900,700,8200,800,*,DOWN,PDIF +S 3000,5900,3000,9100,600,*,DOWN,PDIF +S 1200,8400,1200,8800,200,*,DOWN,POLY +S 2400,8400,2400,8800,200,*,DOWN,POLY +S 3600,9300,3600,9700,200,*,DOWN,POLY +S 4800,9300,4800,9700,200,*,DOWN,POLY +S 1200,4700,1200,5700,200,*,DOWN,POLY +S 4800,5300,4800,6600,200,*,DOWN,POLY +S 2400,5300,2800,5300,200,*,LEFT,POLY +S 3600,6100,3600,6600,200,*,DOWN,POLY +S 3000,3900,3000,4900,200,*,UP,POLY +V 700,700,CONT_BODY_P,* +V 1800,8000,CONT_DIF_P,* +V 1800,7000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,* +V 4000,6000,CONT_POLY,* +V 5200,2000,CONT_DIF_N,* +V 1600,2000,CONT_DIF_N,* +V 5200,1000,CONT_DIF_N,* +V 5400,9000,CONT_DIF_P,* +V 3000,9000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 5000,5000,CONT_POLY,* +V 2000,4500,CONT_POLY,* +V 3000,5100,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd4_x1.vbe b/pdks/symbolic/msxlib/cells/nd4_x1.vbe new file mode 100644 index 000000000..64c5e0566 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY nd4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_a : NATURAL := 7; + CONSTANT cin_b : NATURAL := 7; + CONSTANT cin_c : NATURAL := 7; + CONSTANT cin_d : NATURAL := 6; + CONSTANT rdown_a_z : NATURAL := 2040; + CONSTANT rdown_b_z : NATURAL := 2040; + CONSTANT rdown_c_z : NATURAL := 2040; + CONSTANT rdown_d_z : NATURAL := 2030; + CONSTANT rup_a_z : NATURAL := 2210; + CONSTANT rup_b_z : NATURAL := 2200; + CONSTANT rup_c_z : NATURAL := 2200; + CONSTANT rup_d_z : NATURAL := 2200; + CONSTANT tphl_a_z : NATURAL := 56; + CONSTANT tphl_b_z : NATURAL := 53; + CONSTANT tphl_c_z : NATURAL := 49; + CONSTANT tphl_d_z : NATURAL := 42; + CONSTANT tplh_d_z : NATURAL := 55; + CONSTANT tplh_c_z : NATURAL := 64; + CONSTANT tplh_b_z : NATURAL := 73; + CONSTANT tplh_a_z : NATURAL := 80; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd4_x1; + +ARCHITECTURE behaviour_data_flow OF nd4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd4_x1" + SEVERITY WARNING; + z <= not ((((a and b) and c) and d)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd4_x2.ap b/pdks/symbolic/msxlib/cells/nd4_x2.ap new file mode 100644 index 000000000..e54fc17e2 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd4_x2.ap @@ -0,0 +1,167 @@ +V ALLIANCE : 6 +H nd4_x2,P, 8/ 8/2014,100 +A 0,0,9000,10000 +R 2000,6000,ref_ref,z_60 +R 2000,7000,ref_ref,z_70 +R 1000,3000,ref_ref,z_30 +R 4000,5000,ref_ref,c_50 +R 3000,5000,ref_ref,b_50 +R 7000,7000,ref_ref,b_70 +R 6000,7000,ref_ref,b_70 +R 5000,7000,ref_ref,b_70 +R 3000,8000,ref_ref,z_80 +R 4000,7000,ref_ref,b_70 +R 2000,8000,ref_ref,z_80 +R 1000,5000,ref_ref,z_50 +R 4000,8000,ref_ref,z_80 +R 1000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,b_60 +R 4000,6000,ref_ref,c_60 +R 1000,4000,ref_ref,z_40 +R 1000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 3000,2000,ref_ref,z_20 +R 4000,2000,ref_ref,z_20 +R 5000,2000,ref_ref,z_20 +R 5000,5000,ref_ref,d_50 +R 6000,5000,ref_ref,d_50 +R 4000,4000,ref_ref,c_40 +R 5000,4000,ref_ref,c_40 +R 6000,4000,ref_ref,c_40 +R 8000,4000,ref_ref,a_40 +R 8000,3000,ref_ref,a_30 +R 7000,3000,ref_ref,a_30 +R 6000,3000,ref_ref,a_30 +R 5000,3000,ref_ref,a_30 +R 4000,3000,ref_ref,a_30 +R 3000,3000,ref_ref,a_30 +R 2000,3000,ref_ref,a_30 +R 2000,4000,ref_ref,a_40 +R 3000,7000,ref_ref,b_70 +R 7000,6000,ref_ref,d_60 +R 7000,5000,ref_ref,d_50 +R 7000,4000,ref_ref,d_50 +S 900,6900,900,9300,400,*,DOWN,ALU1 +S 1000,2000,1000,6000,400,z,DOWN,CALU1 +S 1000,2000,1000,6100,400,*,DOWN,ALU1 +S 2000,6000,2000,8000,400,z,DOWN,CALU1 +S 2000,5900,2000,8000,600,*,UP,ALU1 +S 1000,6000,2000,6000,600,*,RIGHT,ALU1 +S 7800,300,7800,700,200,*,UP,POLY +S 7000,300,7000,700,200,*,UP,POLY +S 6200,300,6200,700,200,*,UP,POLY +S 5400,300,5400,700,200,*,UP,POLY +S 4200,300,4200,700,200,*,UP,POLY +S 3400,300,3400,700,200,*,UP,POLY +S 2600,300,2600,700,200,*,UP,POLY +S 1800,300,1800,700,200,*,UP,POLY +S 2000,8000,4600,8000,400,*,LEFT,ALU1 +S 5800,5700,5800,9200,600,*,DOWN,PDIF +S 5700,7900,5700,9300,400,*,DOWN,ALU1 +S 5400,3000,5400,4900,200,*,DOWN,POLY +S 3300,5700,3300,9200,1000,*,DOWN,PDIF +S 3900,4300,3900,5500,200,*,DOWN,POLY +S 5100,9400,5100,9700,200,*,DOWN,POLY +S 3900,9400,3900,9700,200,*,DOWN,POLY +S 5100,5500,5100,9400,200,04,UP,PTRANS +S 4500,5700,4500,9200,1000,*,UP,PDIF +S 3900,5500,3900,9400,200,03,UP,PTRANS +S 2700,9400,2700,9700,200,*,DOWN,POLY +S 1500,9400,1500,9700,200,*,DOWN,POLY +S 1500,4700,1500,5500,200,*,DOWN,POLY +S 1800,3000,1800,4900,200,*,UP,POLY +S 2700,3900,2700,5500,200,*,UP,POLY +S 800,5700,800,9200,600,*,DOWN,PDIF +S 1500,5500,1500,9400,200,01,UP,PTRANS +S 2700,5500,2700,9400,200,02,UP,PTRANS +S 2100,5700,2100,9200,1000,*,DOWN,PDIF +S 4000,8000,4000,8000,400,z,LEFT,CALU1 +S 3000,8000,3000,8000,400,z,LEFT,CALU1 +S 4000,7000,4000,7000,400,b,LEFT,CALU1 +S 5000,7000,5000,7000,400,b,LEFT,CALU1 +S 6000,7000,6000,7000,400,b,LEFT,CALU1 +S 6000,5000,6000,5000,400,d,LEFT,CALU1 +S 6000,4000,6000,4000,400,c,LEFT,CALU1 +S 5000,4000,5000,4000,400,c,LEFT,CALU1 +S 7000,3000,7000,3000,400,a,LEFT,CALU1 +S 6000,3000,6000,3000,400,a,LEFT,CALU1 +S 5000,3000,5000,3000,400,a,LEFT,CALU1 +S 4000,3000,4000,3000,400,a,LEFT,CALU1 +S 3000,3000,3000,3000,400,a,LEFT,CALU1 +S 5000,2000,5000,2000,400,z,LEFT,CALU1 +S 4000,2000,4000,2000,400,z,LEFT,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 0,5000,9000,5000,10000,nd4_x2,LEFT,TALU8 +S 0,2200,9000,2200,5200,*,LEFT,PWELL +S 0,7600,9000,7600,5600,*,LEFT,NWELL +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 1800,700,1800,3000,200,09,DOWN,NTRANS +S 2200,900,2200,2800,600,n3,UP,NDIF +S 2600,700,2600,3000,200,10,DOWN,NTRANS +S 3000,900,3000,2800,600,n2,UP,NDIF +S 3400,700,3400,3000,200,11,DOWN,NTRANS +S 3800,900,3800,2800,600,n1,UP,NDIF +S 4200,700,4200,3000,200,12,DOWN,NTRANS +S 4700,900,4700,2800,800,*,UP,NDIF +S 5400,700,5400,3000,200,13,DOWN,NTRANS +S 6600,900,6600,2800,600,n5,UP,NDIF +S 7000,700,7000,3000,200,15,DOWN,NTRANS +S 6200,700,6200,3000,200,14,DOWN,NTRANS +S 5800,900,5800,2800,600,n4,UP,NDIF +S 7400,900,7400,2800,600,n6,UP,NDIF +S 7800,700,7800,3000,200,16,DOWN,NTRANS +S 8400,900,8400,2800,600,*,UP,NDIF +S 4200,3400,5400,3400,200,*,RIGHT,POLY +S 3400,3000,3400,4000,200,*,UP,POLY +S 3400,4000,3800,4000,200,*,RIGHT,POLY +S 6200,3000,6200,3900,200,*,UP,POLY +S 4000,4000,4000,6000,400,c,UP,CALU1 +S 4000,4000,4000,6000,600,*,DOWN,ALU1 +S 3900,4000,6200,4000,600,*,RIGHT,ALU1 +S 7800,3000,7800,4200,200,*,UP,POLY +S 2000,3000,8000,3000,400,*,RIGHT,ALU1 +S 8000,3000,8000,4000,400,a,DOWN,CALU1 +S 8000,3000,8000,4000,600,*,DOWN,ALU1 +S 2600,3000,2600,4000,200,*,UP,POLY +S 3000,5000,3000,7000,400,b,DOWN,CALU1 +S 3000,4900,3000,7000,600,*,UP,ALU1 +S 1000,2000,5100,2000,400,*,RIGHT,ALU1 +S 1000,1900,5100,1900,400,*,RIGHT,ALU1 +S 1200,900,1200,2800,800,*,UP,NDIF +S 2000,3000,2000,5000,400,a,DOWN,CALU1 +S 2000,3000,2000,5100,400,*,DOWN,ALU1 +S 1900,3000,1900,5100,400,*,DOWN,ALU1 +S 7000,3000,7000,6800,200,*,UP,POLY +S 3000,7000,7100,7000,400,*,RIGHT,ALU1 +S 7000,4000,7000,6000,400,d,UP,CALU1 +S 7000,3900,7000,6100,400,*,UP,ALU1 +S 5000,5000,7000,5000,600,*,RIGHT,ALU1 +S 7000,7000,7000,7000,400,b,LEFT,CALU1 +S 5000,5000,5000,5000,400,d,LEFT,CALU1 +S 8400,700,8400,2100,400,*,DOWN,ALU1 +V 7900,9300,CONT_BODY_N,* +V 900,7000,CONT_DIF_P,* +V 2100,6000,CONT_DIF_P,* +V 6800,7000,CONT_POLY,* +V 900,8000,CONT_DIF_P,* +V 2100,7000,CONT_DIF_P,* +V 5700,9000,CONT_DIF_P,* +V 5700,8000,CONT_DIF_P,* +V 5200,4900,CONT_POLY,* +V 3300,9000,CONT_DIF_P,* +V 4100,4200,CONT_POLY,* +V 4500,8000,CONT_DIF_P,* +V 2100,8000,CONT_DIF_P,* +V 900,9000,CONT_DIF_P,* +V 1900,4900,CONT_POLY,* +V 1200,1000,CONT_DIF_N,* +V 4800,2000,CONT_DIF_N,* +V 8400,2000,CONT_DIF_N,* +V 8400,1000,CONT_DIF_N,* +V 3000,4900,CONT_POLY,* +V 6200,4000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd4_x2.vbe b/pdks/symbolic/msxlib/cells/nd4_x2.vbe new file mode 100644 index 000000000..0a511a249 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY nd4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 9000; + CONSTANT cin_a : NATURAL := 10; + CONSTANT cin_b : NATURAL := 10; + CONSTANT cin_c : NATURAL := 10; + CONSTANT cin_d : NATURAL := 9; + CONSTANT rdown_a_z : NATURAL := 1420; + CONSTANT rdown_b_z : NATURAL := 1420; + CONSTANT rdown_c_z : NATURAL := 1420; + CONSTANT rdown_d_z : NATURAL := 1410; + CONSTANT rup_a_z : NATURAL := 1530; + CONSTANT rup_b_z : NATURAL := 1520; + CONSTANT rup_c_z : NATURAL := 1520; + CONSTANT rup_d_z : NATURAL := 1520; + CONSTANT tphl_a_z : NATURAL := 56; + CONSTANT tphl_b_z : NATURAL := 53; + CONSTANT tphl_c_z : NATURAL := 48; + CONSTANT tphl_d_z : NATURAL := 40; + CONSTANT tplh_d_z : NATURAL := 53; + CONSTANT tplh_c_z : NATURAL := 63; + CONSTANT tplh_b_z : NATURAL := 72; + CONSTANT tplh_a_z : NATURAL := 79; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd4_x2; + +ARCHITECTURE behaviour_data_flow OF nd4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd4_x2" + SEVERITY WARNING; + z <= not ((((a and b) and c) and d)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nd4_x3.ap b/pdks/symbolic/msxlib/cells/nd4_x3.ap new file mode 100644 index 000000000..6dda1c953 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd4_x3.ap @@ -0,0 +1,215 @@ +V ALLIANCE : 6 +H nd4_x3,P, 8/ 8/2014,100 +A 0,0,11000,10000 +R 1000,3000,ref_ref,z_30 +R 9000,4000,ref_ref,a_40 +R 4000,5000,ref_ref,c_50 +R 3000,5000,ref_ref,b_50 +R 2000,7000,ref_ref,a_70 +R 2000,6000,ref_ref,a_60 +R 1000,7000,ref_ref,z_70 +R 8000,4000,ref_ref,a_40 +R 7000,4000,ref_ref,a_40 +R 6000,4000,ref_ref,a_40 +R 5000,4000,ref_ref,a_40 +R 4000,4000,ref_ref,a_40 +R 3000,4000,ref_ref,a_40 +R 7000,7000,ref_ref,b_70 +R 6000,7000,ref_ref,b_70 +R 5000,7000,ref_ref,b_70 +R 5000,3000,ref_ref,z_30 +R 4000,3000,ref_ref,z_30 +R 3000,3000,ref_ref,z_30 +R 8000,8000,ref_ref,z_80 +R 7000,8000,ref_ref,z_80 +R 6000,8000,ref_ref,z_80 +R 5000,8000,ref_ref,z_80 +R 3000,8000,ref_ref,z_80 +R 4000,7000,ref_ref,b_70 +R 7000,6000,ref_ref,c_60 +R 6000,6000,ref_ref,c_60 +R 6000,5000,ref_ref,d_50 +R 2000,8000,ref_ref,z_80 +R 1000,5000,ref_ref,z_50 +R 4000,8000,ref_ref,z_80 +R 1000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,b_60 +R 5000,5000,ref_ref,d_50 +R 4000,6000,ref_ref,c_60 +R 5000,6000,ref_ref,c_60 +R 1000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +R 8000,7000,ref_ref,b_70 +R 3000,7000,ref_ref,b_70 +R 10000,4000,ref_ref,a_40 +R 5000,2000,ref_ref,z_20 +R 1000,8000,ref_ref,z_80 +R 2000,4000,ref_ref,a_40 +R 9000,8000,ref_ref,z_80 +R 10000,5000,ref_ref,a_50 +R 9000,5000,ref_ref,b_50 +R 7000,5000,ref_ref,d_50 +R 9000,6000,ref_ref,b_60 +R 8000,6000,ref_ref,d_60 +S 9100,9300,10300,9300,600,*,RIGHT,NTIE +S 900,2900,900,8000,400,*,DOWN,ALU1 +S 1000,2900,1000,8000,400,*,DOWN,ALU1 +S 8000,8000,8000,8000,400,z,LEFT,CALU1 +S 7000,8000,7000,8000,400,z,LEFT,CALU1 +S 6000,8000,6000,8000,400,z,LEFT,CALU1 +S 5000,8000,5000,8000,400,z,LEFT,CALU1 +S 4000,8000,4000,8000,400,z,LEFT,CALU1 +S 3000,8000,3000,8000,400,z,LEFT,CALU1 +S 2000,8000,2000,8000,400,z,LEFT,CALU1 +S 7000,7000,7000,7000,400,b,LEFT,CALU1 +S 6000,7000,6000,7000,400,b,LEFT,CALU1 +S 5000,7000,5000,7000,400,b,LEFT,CALU1 +S 4000,7000,4000,7000,400,b,LEFT,CALU1 +S 5000,6000,5000,6000,400,c,LEFT,CALU1 +S 7000,6000,7000,6000,400,c,LEFT,CALU1 +S 6000,6000,6000,6000,400,c,LEFT,CALU1 +S 6000,5000,6000,5000,400,d,LEFT,CALU1 +S 5000,5000,5000,5000,400,d,LEFT,CALU1 +S 7200,5800,7200,6700,200,*,DOWN,POLY +S 6000,4800,6000,6700,200,*,DOWN,POLY +S 9000,4000,9000,4000,400,a,LEFT,CALU1 +S 8000,4000,8000,4000,400,a,LEFT,CALU1 +S 7000,4000,7000,4000,400,a,LEFT,CALU1 +S 6000,4000,6000,4000,400,a,LEFT,CALU1 +S 5000,4000,5000,4000,400,a,LEFT,CALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 3000,4000,3000,4000,400,a,LEFT,CALU1 +S 2000,3000,2000,3000,400,z,LEFT,CALU1 +S 3000,3000,3000,3000,400,z,LEFT,CALU1 +S 4000,3000,4000,3000,400,z,LEFT,CALU1 +S 5000,2000,5000,3000,400,z,DOWN,CALU1 +S 0,600,11000,600,1200,vss,RIGHT,CALU1 +S 0,5000,11000,5000,10000,nd4_x3,LEFT,TALU8 +S 0,2200,11000,2200,5200,*,LEFT,PWELL +S 0,7600,11000,7600,5600,*,LEFT,NWELL +S 4800,5000,6000,5000,600,*,RIGHT,POLY +S 1200,4600,1800,4600,200,*,RIGHT,POLY +S 4000,6000,7100,6000,400,*,RIGHT,ALU1 +S 4000,5000,4000,6000,400,c,DOWN,CALU1 +S 4000,5000,4000,6000,600,*,DOWN,ALU1 +S 3000,5000,3000,7000,400,b,DOWN,CALU1 +S 3000,5000,3000,7000,600,*,UP,ALU1 +S 2400,5200,2700,5200,200,*,RIGHT,POLY +S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 +S 600,6900,600,9100,600,*,DOWN,PDIF +S 1200,6700,1200,9300,200,01,UP,PTRANS +S 2400,6700,2400,9300,200,02,UP,PTRANS +S 1800,6900,1800,9100,1000,*,DOWN,PDIF +S 3000,6900,3000,9100,1000,*,DOWN,PDIF +S 3600,6700,3600,9300,200,03,UP,PTRANS +S 4200,6900,4200,9100,1000,*,UP,PDIF +S 4800,6700,4800,9300,200,04,UP,PTRANS +S 5400,6900,5400,9100,600,*,DOWN,PDIF +S 6000,6700,6000,9300,200,05,UP,PTRANS +S 6600,6900,6600,9100,1000,*,DOWN,PDIF +S 7200,6700,7200,9300,200,06,UP,PTRANS +S 9000,6000,9000,8200,1000,*,DOWN,PDIF +S 8400,5800,8400,8400,200,07,UP,PTRANS +S 9600,5800,9600,8400,200,08,UP,PTRANS +S 10200,6000,10200,8200,600,*,DOWN,PDIF +S 7800,6000,7800,9100,600,*,DOWN,PDIF +S 9600,8400,9600,8800,200,*,DOWN,POLY +S 8400,8400,8400,8800,200,*,DOWN,POLY +S 7200,9300,7200,9700,200,*,DOWN,POLY +S 9600,4200,9600,5800,200,*,DOWN,POLY +S 2000,4000,10100,4000,400,*,RIGHT,ALU1 +S 6000,9300,6000,9700,200,*,DOWN,POLY +S 2200,700,2200,3800,200,09,DOWN,NTRANS +S 1600,700,1600,2100,400,*,DOWN,ALU1 +S 2200,300,2200,700,200,*,UP,POLY +S 3000,300,3000,700,200,*,UP,POLY +S 3800,300,3800,700,200,*,UP,POLY +S 4600,300,4600,700,200,*,UP,POLY +S 5800,300,5800,700,200,*,UP,POLY +S 6600,300,6600,700,200,*,UP,POLY +S 7400,300,7400,700,200,*,UP,POLY +S 8200,300,8200,700,200,*,UP,POLY +S 2600,900,2600,3600,600,n3,UP,NDIF +S 3000,700,3000,3800,200,10,DOWN,NTRANS +S 3400,900,3400,3600,600,n2,UP,NDIF +S 3800,700,3800,3800,200,11,DOWN,NTRANS +S 4200,900,4200,3600,600,n1,UP,NDIF +S 4600,700,4600,3800,200,12,DOWN,NTRANS +S 5100,900,5100,3600,800,*,UP,NDIF +S 5800,700,5800,3800,200,13,DOWN,NTRANS +S 6200,900,6200,3600,600,n4,UP,NDIF +S 6600,700,6600,3800,200,14,DOWN,NTRANS +S 7000,900,7000,3600,600,n5,UP,NDIF +S 7400,700,7400,3800,200,15,DOWN,NTRANS +S 7800,900,7800,3600,600,n6,UP,NDIF +S 8200,700,8200,3800,200,16,DOWN,NTRANS +S 3000,3800,3000,5000,200,*,UP,POLY +S 1200,4600,1200,6700,200,*,DOWN,POLY +S 2400,5200,2400,6700,200,*,DOWN,POLY +S 3600,5800,3600,6700,200,*,DOWN,POLY +S 3800,3800,3800,5700,200,*,UP,POLY +S 4800,4800,4800,6700,200,*,DOWN,POLY +S 4600,3800,4600,5200,200,*,UP,POLY +S 5800,3800,5800,4800,200,*,UP,POLY +S 6600,4100,6600,5700,200,*,UP,POLY +S 8200,4200,9700,4200,200,*,RIGHT,POLY +S 5100,1900,5100,3000,600,*,DOWN,ALU1 +S 1600,900,1600,3600,800,*,UP,NDIF +S 1000,3000,5000,3000,400,*,RIGHT,ALU1 +S 1000,2900,5000,2900,400,*,RIGHT,ALU1 +S 8800,700,8800,2100,400,*,DOWN,ALU1 +S 8800,900,8800,3600,600,*,UP,NDIF +S 1000,3000,1000,8000,400,z,DOWN,CALU1 +S 2000,4000,2000,7100,400,*,DOWN,ALU1 +S 2000,4000,2000,7000,400,a,DOWN,CALU1 +S 1900,4000,1900,7100,400,*,DOWN,ALU1 +S 1200,9300,1200,9700,200,*,DOWN,POLY +S 2400,9300,2400,9700,200,*,DOWN,POLY +S 3600,9300,3600,9700,200,*,DOWN,POLY +S 4800,9300,4800,9700,200,*,DOWN,POLY +S 10200,6900,10200,9300,400,*,UP,ALU1 +S 10000,4000,10000,5000,600,*,UP,ALU1 +S 10000,4000,10000,5000,400,a,DOWN,CALU1 +S 10000,600,10000,3400,600,*,UP,PTIE +S 1000,8000,9100,8000,400,*,LEFT,ALU1 +S 7000,5000,7000,5000,400,d,LEFT,CALU1 +S 3000,7000,9000,7000,400,*,RIGHT,ALU1 +S 8000,7000,8000,7000,400,b,LEFT,CALU1 +S 8900,4900,8900,7000,600,*,DOWN,ALU1 +S 8400,4900,8400,5800,200,*,DOWN,POLY +S 8400,5100,8800,5100,600,*,LEFT,POLY +S 7400,4900,8400,4900,200,*,RIGHT,POLY +S 7400,3800,7400,4900,200,*,DOWN,POLY +S 9000,5000,9000,6000,400,b,DOWN,CALU1 +S 4900,5000,8000,5000,400,*,RIGHT,ALU1 +S 8000,6000,8000,6000,400,d,LEFT,CALU1 +S 8000,5000,8000,6100,400,*,UP,ALU1 +S 9000,8000,9000,8000,400,z,LEFT,CALU1 +V 10300,9300,CONT_BODY_N,* +V 9000,9300,CONT_BODY_N,* +V 7800,9000,CONT_DIF_P,* +V 6600,8000,CONT_DIF_P,* +V 6800,6000,CONT_POLY,* +V 5400,5000,CONT_POLY,* +V 1800,8000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,* +V 4000,6000,CONT_POLY,* +V 10200,8000,CONT_DIF_P,* +V 2000,4400,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 600,9000,CONT_DIF_P,* +V 3000,9000,CONT_DIF_P,* +V 5400,9000,CONT_DIF_P,* +V 1600,2000,CONT_DIF_N,* +V 1600,1000,CONT_DIF_N,* +V 5200,2000,CONT_DIF_N,* +V 5200,3000,CONT_DIF_N,* +V 8800,2000,CONT_DIF_N,* +V 8800,1000,CONT_DIF_N,* +V 10000,600,CONT_BODY_P,* +V 9000,8000,CONT_DIF_P,* +V 10200,7000,CONT_DIF_P,* +V 9900,4400,CONT_POLY,* +V 8800,5100,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nd4_x3.vbe b/pdks/symbolic/msxlib/cells/nd4_x3.vbe new file mode 100644 index 000000000..97aaf2843 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nd4_x3.vbe @@ -0,0 +1,44 @@ +ENTITY nd4_x3 IS +GENERIC ( + CONSTANT area : NATURAL := 11000; + CONSTANT cin_a : NATURAL := 14; + CONSTANT cin_b : NATURAL := 14; + CONSTANT cin_c : NATURAL := 13; + CONSTANT cin_d : NATURAL := 12; + CONSTANT rdown_a_z : NATURAL := 1050; + CONSTANT rdown_b_z : NATURAL := 1050; + CONSTANT rdown_c_z : NATURAL := 1050; + CONSTANT rdown_d_z : NATURAL := 1050; + CONSTANT rup_a_z : NATURAL := 1150; + CONSTANT rup_b_z : NATURAL := 1140; + CONSTANT rup_c_z : NATURAL := 1140; + CONSTANT rup_d_z : NATURAL := 1140; + CONSTANT tphl_a_z : NATURAL := 56; + CONSTANT tphl_b_z : NATURAL := 53; + CONSTANT tphl_c_z : NATURAL := 48; + CONSTANT tphl_d_z : NATURAL := 41; + CONSTANT tplh_d_z : NATURAL := 54; + CONSTANT tplh_c_z : NATURAL := 63; + CONSTANT tplh_b_z : NATURAL := 73; + CONSTANT tplh_a_z : NATURAL := 80; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd4_x3; + +ARCHITECTURE behaviour_data_flow OF nd4_x3 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd4_x3" + SEVERITY WARNING; + z <= not ((((a and b) and c) and d)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nr2_x05.ap b/pdks/symbolic/msxlib/cells/nr2_x05.ap new file mode 100644 index 000000000..2ba41463c --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr2_x05.ap @@ -0,0 +1,70 @@ +V ALLIANCE : 6 +H nr2_x05,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 2000,4000,ref_ref,b_40 +R 1000,3000,ref_ref,z_30 +R 3000,5000,ref_ref,a_50 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 3000,4000,ref_ref,b_40 +R 2000,3000,ref_ref,z_30 +R 3000,3000,ref_ref,b_30 +R 2000,2000,ref_ref,z_20 +R 2000,5000,ref_ref,a_60 +R 2000,6000,ref_ref,a_60 +S 1100,700,1900,700,600,*,LEFT,PTIE +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,4000,5000,10000,nr2_x05,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 1600,5600,1600,7800,200,1,UP,PTRANS +S 2400,5600,2400,7800,200,2,UP,PTRANS +S 2000,5800,2000,7600,600,n1,UP,PDIF +S 1200,5800,1200,7600,400,*,UP,PDIF +S 1400,1700,1400,2300,200,3,DOWN,NTRANS +S 1400,1300,1400,1700,200,*,UP,POLY +S 800,700,800,2100,400,*,DOWN,ALU1 +S 2000,1900,2000,2100,1000,*,UP,NDIF +S 2600,1300,2600,1700,200,*,UP,POLY +S 2600,1700,2600,2300,200,4,DOWN,NTRANS +S 2000,2000,2000,3000,400,z,DOWN,CALU1 +S 1000,3000,2000,3000,600,*,RIGHT,ALU1 +S 1800,4000,3000,4000,600,*,LEFT,ALU1 +S 2600,2300,2600,5200,200,*,UP,POLY +S 1600,3800,1600,5600,200,*,DOWN,POLY +S 1400,2300,1400,4200,200,*,UP,POLY +S 2000,5000,3000,5000,600,*,LEFT,ALU1 +S 2000,4000,2000,4000,400,b,LEFT,CALU1 +S 1000,3000,1000,6000,400,z,DOWN,CALU1 +S 3000,5000,3000,5000,400,a,LEFT,CALU1 +S 3000,5900,3000,9300,400,*,UP,ALU1 +S 3100,5800,3100,7600,600,*,DOWN,PDIF +S 2400,7800,2400,8200,200,*,DOWN,POLY +S 1600,7800,1600,8200,200,*,DOWN,POLY +S 2000,4900,2000,6100,400,*,UP,ALU1 +S 2000,5000,2000,6000,400,a,UP,CALU1 +S 1000,6000,1000,6600,600,*,DOWN,PDIF +S 3000,3000,3000,4000,400,b,DOWN,CALU1 +S 3000,2900,3000,4000,400,*,DOWN,ALU1 +S 3200,1900,3200,2100,600,*,UP,NDIF +S 3200,700,3200,2100,400,*,DOWN,ALU1 +S 2000,1900,2000,3100,400,*,DOWN,ALU1 +S 1000,2900,1000,6800,400,*,DOWN,ALU1 +S 1400,4000,2000,4000,600,*,LEFT,POLY +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 1000,5900,CONT_DIF_P,* +V 2000,2000,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 1800,4000,CONT_POLY,* +V 2600,5000,CONT_POLY,* +V 3000,7000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 1000,6700,CONT_DIF_P,* +V 3200,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nr2_x05.vbe b/pdks/symbolic/msxlib/cells/nr2_x05.vbe new file mode 100644 index 000000000..41e5133be --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr2_x05.vbe @@ -0,0 +1,32 @@ +ENTITY nr2_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3820; + CONSTANT rdown_b_z : NATURAL := 3810; + CONSTANT rup_a_z : NATURAL := 5280; + CONSTANT rup_b_z : NATURAL := 5280; + CONSTANT tplh_a_z : NATURAL := 55; + CONSTANT tplh_b_z : NATURAL := 45; + CONSTANT tphl_b_z : NATURAL := 44; + CONSTANT tphl_a_z : NATURAL := 53; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2_x05; + +ARCHITECTURE behaviour_data_flow OF nr2_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2_x05" + SEVERITY WARNING; + z <= not ((a or b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nr2_x1.ap b/pdks/symbolic/msxlib/cells/nr2_x1.ap new file mode 100644 index 000000000..edd6c776c --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr2_x1.ap @@ -0,0 +1,73 @@ +V ALLIANCE : 6 +H nr2_x1,P, 8/ 8/2014,100 +A 0,0,4000,10000 +R 2000,6000,ref_ref,a_60 +R 1000,3000,ref_ref,z_30 +R 2000,4000,ref_ref,b_40 +R 1000,7000,ref_ref,z_70 +R 3000,6000,ref_ref,a_60 +R 2000,3000,ref_ref,z_30 +R 3000,4000,ref_ref,b_40 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,b_50 +R 3000,5000,ref_ref,a_50 +R 2000,2000,ref_ref,z_20 +R 3000,7000,ref_ref,a_70 +S 1100,700,1900,700,600,*,LEFT,PTIE +S 2000,3900,2000,5100,400,*,UP,ALU1 +S 1000,2900,1000,7000,400,*,DOWN,ALU1 +S 1400,4000,2000,4000,600,*,LEFT,POLY +S 3000,4000,3000,4000,400,b,LEFT,CALU1 +S 2000,6000,2000,6000,400,a,LEFT,CALU1 +S 2400,5100,2600,5100,200,*,RIGHT,POLY +S 2000,4000,2000,5000,400,b,DOWN,CALU1 +S 1200,5700,1200,9200,400,*,UP,PDIF +S 3100,5700,3100,9200,600,*,DOWN,PDIF +S 3000,7900,3000,9300,400,*,UP,ALU1 +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 2000,5700,2000,9200,600,n1,UP,PDIF +S 2400,5500,2400,9400,200,2,UP,PTRANS +S 1600,9400,1600,9700,200,*,DOWN,POLY +S 1600,5500,1600,9400,200,1,UP,PTRANS +S 0,5000,4000,5000,10000,nr2_x1,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 1400,1300,1400,1700,200,*,UP,POLY +S 1400,1700,1400,2800,200,3,DOWN,NTRANS +S 2600,1300,2600,1700,200,*,UP,POLY +S 2600,1700,2600,2800,200,4,DOWN,NTRANS +S 2000,1900,2000,2600,1000,*,UP,NDIF +S 3200,700,3200,2100,400,*,DOWN,ALU1 +S 3300,1900,3300,2600,600,*,UP,NDIF +S 1600,3800,1600,5500,200,*,DOWN,POLY +S 1800,4000,3000,4000,600,*,RIGHT,ALU1 +S 1000,3000,2000,3000,600,*,RIGHT,ALU1 +S 2000,2000,2000,3000,400,z,DOWN,CALU1 +S 2000,1900,2000,3000,400,*,UP,ALU1 +S 1000,5900,1000,6500,600,*,DOWN,PDIF +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 1000,7000,1000,7100,400,*,UP,ALU1 +S 2600,2800,2600,5100,200,*,UP,POLY +S 2400,5000,2400,5500,200,*,DOWN,POLY +S 1400,2800,1400,4200,200,*,UP,POLY +S 800,700,800,2100,400,*,DOWN,ALU1 +S 700,1900,700,2600,600,*,UP,NDIF +S 3000,4900,3000,7000,600,*,UP,ALU1 +S 3000,5000,3000,7000,400,a,UP,CALU1 +S 1900,6000,3100,6000,400,*,LEFT,ALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2000,2500,CONT_DIF_N,* +V 3000,9000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,4900,CONT_POLY,* +V 3200,2000,CONT_DIF_N,* +V 1800,4000,CONT_POLY,* +V 1000,5800,CONT_DIF_P,* +V 1000,6600,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nr2_x1.vbe b/pdks/symbolic/msxlib/cells/nr2_x1.vbe new file mode 100644 index 000000000..dd781dfe9 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY nr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 6; + CONSTANT cin_b : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 2080; + CONSTANT rdown_b_z : NATURAL := 2080; + CONSTANT rup_a_z : NATURAL := 2980; + CONSTANT rup_b_z : NATURAL := 2980; + CONSTANT tplh_a_z : NATURAL := 53; + CONSTANT tplh_b_z : NATURAL := 44; + CONSTANT tphl_b_z : NATURAL := 42; + CONSTANT tphl_a_z : NATURAL := 50; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2_x1; + +ARCHITECTURE behaviour_data_flow OF nr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2_x1" + SEVERITY WARNING; + z <= not ((a or b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nr2_x2.ap b/pdks/symbolic/msxlib/cells/nr2_x2.ap new file mode 100644 index 000000000..9563816ad --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr2_x2.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H nr2_x2,P, 8/ 8/2014,100 +A 0,0,6000,10000 +R 4000,4000,ref_ref,a_40 +R 3000,4000,ref_ref,a_40 +R 2000,4000,ref_ref,a_40 +R 2000,5000,ref_ref,a_50 +R 3000,5000,ref_ref,b_50 +R 4000,5000,ref_ref,b_50 +R 4000,6000,ref_ref,b_60 +R 1000,6000,ref_ref,z_60 +R 2000,2000,ref_ref,z_20 +R 2000,3000,ref_ref,z_30 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,3000,ref_ref,z_30 +R 3000,7000,ref_ref,z_70 +R 2000,6000,ref_ref,z_60 +R 3000,6000,ref_ref,z_60 +S 2000,4000,2000,5000,400,a,DOWN,CALU1 +S 3000,4000,3000,4000,400,a,LEFT,CALU1 +S 3000,5000,3000,5000,400,b,LEFT,CALU1 +S 4400,3800,4400,5500,200,*,DOWN,POLY +S 2800,3400,2800,4700,200,*,UP,POLY +S 1600,3400,1600,5500,200,*,DOWN,POLY +S 1600,900,1600,1300,200,*,UP,POLY +S 2800,900,2800,1300,200,*,UP,POLY +S 1000,1500,1000,3200,800,*,UP,NDIF +S 3500,1500,3500,3200,600,*,DOWN,NDIF +S 2800,1300,2800,3400,200,6,DOWN,NTRANS +S 1600,1300,1600,3400,200,5,DOWN,NTRANS +S 2200,1500,2200,3200,1000,*,UP,NDIF +S 5000,5700,5000,9200,800,*,DOWN,PDIF +S 1000,5700,1000,9200,800,*,DOWN,PDIF +S 2400,5100,3600,5100,200,*,LEFT,POLY +S 4400,5500,4400,9400,200,4,UP,PTRANS +S 4000,5800,4000,9200,600,n2,DOWN,PDIF +S 3000,5700,3000,9200,1000,*,DOWN,PDIF +S 2400,5500,2400,9400,200,2,UP,PTRANS +S 2000,5700,2000,9200,600,n1,UP,PDIF +S 1600,5500,1600,9400,200,1,UP,PTRANS +S 3600,5500,3600,9400,200,3,UP,PTRANS +S 4400,9400,4400,9700,200,*,DOWN,POLY +S 3600,9400,3600,9700,200,*,DOWN,POLY +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 1600,9400,1600,9700,200,*,DOWN,POLY +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,5000,6000,5000,10000,nr2_x2,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 2000,2000,2000,3000,400,z,DOWN,CALU1 +S 1000,3000,2200,3000,600,*,RIGHT,ALU1 +S 1000,700,1000,2100,400,*,DOWN,ALU1 +S 2000,4000,2000,5100,400,*,UP,ALU1 +S 1900,4000,1900,5100,400,*,UP,ALU1 +S 2900,5000,4000,5000,600,*,LEFT,ALU1 +S 4000,4900,4000,6100,400,*,UP,ALU1 +S 4000,5000,4000,6000,400,b,UP,CALU1 +S 1900,4000,4100,4000,400,*,LEFT,ALU1 +S 3800,4000,4400,4000,600,*,RIGHT,POLY +S 3000,6000,3000,7000,400,z,UP,CALU1 +S 3000,6000,3000,7000,600,*,UP,ALU1 +S 1000,6100,3000,6100,400,*,RIGHT,ALU1 +S 1000,6000,3000,6000,400,*,RIGHT,ALU1 +S 2000,6000,2000,6000,400,z,LEFT,CALU1 +S 1000,3000,1000,6000,400,z,DOWN,CALU1 +S 1000,2900,1000,6100,400,*,DOWN,ALU1 +S 2100,1900,2100,3100,600,*,DOWN,ALU1 +S 3400,700,3400,3100,400,*,DOWN,ALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 5000,6900,5000,9300,400,*,UP,ALU1 +S 1000,6900,1000,9300,400,*,UP,ALU1 +S 5000,600,5000,3500,600,*,UP,PTIE +V 5000,700,CONT_BODY_P,* +V 2000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 3000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 5000,9000,CONT_DIF_P,* +V 1000,9000,CONT_DIF_P,* +V 2200,3000,CONT_DIF_N,* +V 3000,4900,CONT_POLY,* +V 2200,2000,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 3400,2000,CONT_DIF_N,* +V 3000,6000,CONT_DIF_P,* +V 3400,3000,CONT_DIF_N,* +V 1000,7000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nr2_x2.vbe b/pdks/symbolic/msxlib/cells/nr2_x2.vbe new file mode 100644 index 000000000..ddb1eaaf2 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY nr2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_a : NATURAL := 11; + CONSTANT cin_b : NATURAL := 10; + CONSTANT rdown_a_z : NATURAL := 1090; + CONSTANT rdown_b_z : NATURAL := 1090; + CONSTANT rup_a_z : NATURAL := 1490; + CONSTANT rup_b_z : NATURAL := 1490; + CONSTANT tplh_a_z : NATURAL := 51; + CONSTANT tplh_b_z : NATURAL := 41; + CONSTANT tphl_b_z : NATURAL := 40; + CONSTANT tphl_a_z : NATURAL := 50; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2_x2; + +ARCHITECTURE behaviour_data_flow OF nr2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2_x2" + SEVERITY WARNING; + z <= not ((a or b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nr2a_x05.ap b/pdks/symbolic/msxlib/cells/nr2a_x05.ap new file mode 100644 index 000000000..b63165ead --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr2a_x05.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 6 +H nr2a_x05,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 2000,7000,ref_ref,a_70 +R 2000,2000,ref_ref,z_20 +R 3000,5000,ref_ref,a_50 +R 2000,5000,ref_ref,b_50 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 3000,6000,ref_ref,a_60 +R 3000,3000,ref_ref,b_30 +R 1000,7000,ref_ref,z_70 +R 2000,4000,ref_ref,b_40 +R 1000,3000,ref_ref,z_30 +R 2000,6000,ref_ref,a_60 +R 1000,2000,ref_ref,z_20 +R 2000,3000,ref_ref,b_30 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 2100,700,2900,700,600,*,LEFT,PTIE +S 3200,5800,3200,7600,600,*,DOWN,PDIF +S 2600,2300,2600,5100,200,*,UP,POLY +S 1400,2300,1400,4200,200,*,UP,POLY +S 1400,1700,1400,2300,200,4z,DOWN,NTRANS +S 800,900,800,2100,600,*,UP,NDIF +S 700,900,700,2100,600,*,UP,NDIF +S 2600,1700,2600,2300,200,3z,DOWN,NTRANS +S 2000,1900,2000,2100,1000,*,UP,NDIF +S 3800,2600,3800,5500,200,*,UP,POLY +S 3300,1900,3300,2400,600,*,UP,NDIF +S 3800,1700,3800,2600,200,2a,DOWN,NTRANS +S 4200,1900,4200,2400,400,*,UP,NDIF +S 3800,7300,3800,7700,200,*,DOWN,POLY +S 1600,7800,1600,8100,200,*,DOWN,POLY +S 2400,7800,2400,8100,200,*,DOWN,POLY +S 1000,6000,1000,6600,600,*,DOWN,PDIF +S 4400,6000,4400,6600,600,*,UP,PDIF +S 1200,5800,1200,7600,400,*,UP,PDIF +S 1600,5600,1600,7800,200,2z,UP,PTRANS +S 2000,5800,2000,7600,600,n1,UP,PDIF +S 2400,5600,2400,7800,200,1z,UP,PTRANS +S 4200,5800,4200,7100,400,*,DOWN,PDIF +S 3800,5600,3800,7300,200,1a,UP,PTRANS +S 2400,5000,2400,5500,200,*,DOWN,POLY +S 1000,7000,1000,7100,400,*,UP,ALU1 +S 3200,700,3200,2100,400,*,DOWN,ALU1 +S 2600,1300,2600,1700,200,*,UP,POLY +S 1400,1300,1400,1700,200,*,UP,POLY +S 1600,3900,1600,5500,200,*,DOWN,POLY +S 1800,4100,2000,4100,600,*,RIGHT,ALU1 +S 2000,6000,2000,7000,400,a,DOWN,CALU1 +S 3000,5000,3000,6000,400,a,UP,CALU1 +S 2000,5900,2000,7100,400,*,UP,ALU1 +S 3000,6900,3000,9300,400,*,UP,ALU1 +S 1000,2000,2000,2000,600,*,RIGHT,ALU1 +S 1000,2000,1000,7000,400,*,DOWN,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 2000,3000,2000,5100,400,*,UP,ALU1 +S 2000,3000,2000,5000,400,b,DOWN,CALU1 +S 3000,3000,3000,3000,400,b,LEFT,CALU1 +S 2000,2900,3100,2900,400,*,RIGHT,ALU1 +S 2000,3000,3100,3000,400,*,RIGHT,ALU1 +S 2800,3900,4400,3900,400,*,RIGHT,ALU1 +S 3000,4900,3000,6100,400,*,UP,ALU1 +S 2000,6000,3000,6000,600,*,LEFT,ALU1 +S 3000,4900,3600,4900,400,*,LEFT,ALU1 +S 0,5000,5000,5000,10000,nr2a_x05,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 3800,1300,3800,1700,200,*,UP,POLY +S 4400,2200,4400,6800,400,*,UP,ALU1 +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 3000,700,CONT_BODY_P,* +V 2000,700,CONT_BODY_P,* +V 4400,5900,CONT_DIF_P,an +V 4400,2300,CONT_DIF_N,an +V 1000,6700,CONT_DIF_P,* +V 1000,5900,CONT_DIF_P,* +V 4400,6700,CONT_DIF_P,an +V 3200,2000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 3500,4900,CONT_POLY,* +V 3000,7000,CONT_DIF_P,* +V 800,1000,CONT_DIF_N,* +V 2900,3900,CONT_POLY,an +V 1800,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nr2a_x05.vbe b/pdks/symbolic/msxlib/cells/nr2a_x05.vbe new file mode 100644 index 000000000..8e51c8db3 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr2a_x05.vbe @@ -0,0 +1,32 @@ +ENTITY nr2a_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 3810; + CONSTANT rdown_a_z : NATURAL := 3820; + CONSTANT rup_b_z : NATURAL := 5280; + CONSTANT rup_a_z : NATURAL := 5270; + CONSTANT tplh_b_z : NATURAL := 46; + CONSTANT tphl_b_z : NATURAL := 45; + CONSTANT tphh_a_z : NATURAL := 78; + CONSTANT tpll_a_z : NATURAL := 93; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2a_x05; + +ARCHITECTURE behaviour_data_flow OF nr2a_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2a_x05" + SEVERITY WARNING; + z <= (not (b) and a) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nr2a_x1.ap b/pdks/symbolic/msxlib/cells/nr2a_x1.ap new file mode 100644 index 000000000..169e3779f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr2a_x1.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 6 +H nr2a_x1,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 2000,7000,ref_ref,a_70 +R 2000,2000,ref_ref,z_20 +R 3000,5000,ref_ref,a_50 +R 2000,5000,ref_ref,b_50 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 3000,6000,ref_ref,a_60 +R 3000,3000,ref_ref,b_30 +R 1000,7000,ref_ref,z_70 +R 2000,4000,ref_ref,b_40 +R 1000,3000,ref_ref,z_30 +R 2000,6000,ref_ref,a_60 +R 1000,2000,ref_ref,z_20 +R 2000,3000,ref_ref,b_30 +S 2100,700,2900,700,600,*,LEFT,PTIE +S 2400,5000,2400,5500,200,*,DOWN,POLY +S 2600,2800,2600,5100,200,*,UP,POLY +S 1000,7000,1000,7100,400,*,UP,ALU1 +S 1000,5900,1000,6500,600,*,DOWN,PDIF +S 3300,1900,3300,2600,600,*,UP,NDIF +S 3200,700,3200,2100,400,*,DOWN,ALU1 +S 2000,1900,2000,2600,1000,*,UP,NDIF +S 2600,1300,2600,1700,200,*,UP,POLY +S 1400,1300,1400,1700,200,*,UP,POLY +S 1600,9400,1600,9700,200,*,DOWN,POLY +S 2000,5700,2000,9200,600,n1,UP,PDIF +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 1200,5700,1200,9200,400,*,UP,PDIF +S 4400,2400,4400,6700,400,*,UP,ALU1 +S 3800,2800,3800,5500,200,*,UP,POLY +S 1600,3900,1600,5500,200,*,DOWN,POLY +S 1800,4100,2000,4100,600,*,RIGHT,ALU1 +S 2000,6000,2000,7000,400,a,DOWN,CALU1 +S 3000,5000,3000,6000,400,a,UP,CALU1 +S 2000,5900,2000,7100,400,*,UP,ALU1 +S 3000,6900,3000,9300,400,*,UP,ALU1 +S 700,900,700,2600,600,*,UP,NDIF +S 800,900,800,2600,600,*,UP,NDIF +S 1000,2000,2000,2000,600,*,RIGHT,ALU1 +S 1000,2000,1000,7000,400,*,DOWN,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 2000,3000,2000,5100,400,*,UP,ALU1 +S 2000,3000,2000,5000,400,b,DOWN,CALU1 +S 3000,3000,3000,3000,400,b,LEFT,CALU1 +S 2000,2900,3100,2900,400,*,RIGHT,ALU1 +S 2000,3000,3100,3000,400,*,RIGHT,ALU1 +S 2800,3900,4400,3900,400,*,RIGHT,ALU1 +S 4400,5900,4400,6500,600,*,UP,PDIF +S 4200,1900,4200,2600,400,*,UP,NDIF +S 4200,5700,4200,7500,400,*,DOWN,PDIF +S 3800,7700,3800,8100,200,*,DOWN,POLY +S 3000,4900,3000,6100,400,*,UP,ALU1 +S 2000,6000,3000,6000,600,*,LEFT,ALU1 +S 3000,4900,3600,4900,400,*,LEFT,ALU1 +S 0,5000,5000,5000,10000,nr2a_x1,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 3800,5500,3800,7700,200,1a,UP,PTRANS +S 3800,1700,3800,2800,200,2a,DOWN,NTRANS +S 2400,5500,2400,9400,200,1z,UP,PTRANS +S 1600,5500,1600,9400,200,2z,UP,PTRANS +S 2600,1700,2600,2800,200,3z,DOWN,NTRANS +S 1400,1700,1400,2800,200,4z,DOWN,NTRANS +S 3800,1300,3800,1700,200,*,UP,POLY +S 3200,5700,3200,9200,600,*,DOWN,PDIF +S 1400,2800,1400,4200,200,*,UP,POLY +V 3000,700,CONT_BODY_P,* +V 2000,700,CONT_BODY_P,* +V 4300,9300,CONT_BODY_N,* +V 1000,6600,CONT_DIF_P,* +V 1000,5800,CONT_DIF_P,* +V 3200,2000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 3000,9000,CONT_DIF_P,* +V 4400,5800,CONT_DIF_P,* +V 3500,4900,CONT_POLY,* +V 3000,7000,CONT_DIF_P,* +V 800,1000,CONT_DIF_N,* +V 4400,6600,CONT_DIF_P,an +V 4400,2500,CONT_DIF_N,an +V 2900,3900,CONT_POLY,an +V 1800,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nr2a_x1.vbe b/pdks/symbolic/msxlib/cells/nr2a_x1.vbe new file mode 100644 index 000000000..4a7dc1369 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr2a_x1.vbe @@ -0,0 +1,32 @@ +ENTITY nr2a_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 2080; + CONSTANT rdown_a_z : NATURAL := 2080; + CONSTANT rup_b_z : NATURAL := 2980; + CONSTANT rup_a_z : NATURAL := 2980; + CONSTANT tplh_b_z : NATURAL := 44; + CONSTANT tphl_b_z : NATURAL := 42; + CONSTANT tphh_a_z : NATURAL := 82; + CONSTANT tpll_a_z : NATURAL := 95; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2a_x1; + +ARCHITECTURE behaviour_data_flow OF nr2a_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2a_x1" + SEVERITY WARNING; + z <= (not (b) and a) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nr3_x05.ap b/pdks/symbolic/msxlib/cells/nr3_x05.ap new file mode 100644 index 000000000..e0815618b --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr3_x05.ap @@ -0,0 +1,96 @@ +V ALLIANCE : 6 +H nr3_x05,P, 8/ 8/2014,100 +A 0,0,5000,10000 +R 4000,6000,ref_ref,a_60 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 3000,4000,ref_ref,b_40 +R 4000,5000,ref_ref,a_50 +R 1000,3000,ref_ref,z_30 +R 3000,5000,ref_ref,b_50 +R 2000,4000,ref_ref,c_40 +R 2000,3000,ref_ref,c_30 +R 3000,3000,ref_ref,c_30 +R 4000,3000,ref_ref,c_30 +R 1000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 3000,2000,ref_ref,z_20 +R 1000,7000,ref_ref,z_70 +R 3000,6000,ref_ref,a_60 +R 4000,4000,ref_ref,b_40 +S 3600,700,4200,700,600,*,LEFT,PTIE +S 2800,2800,2800,4400,200,*,UP,POLY +S 2600,2400,2600,2900,200,*,UP,POLY +S 1400,2400,1400,3900,200,*,UP,POLY +S 1600,3500,1600,5500,200,*,DOWN,POLY +S 2400,4500,2800,4500,200,*,LEFT,POLY +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 4000,3000,4000,3000,400,c,LEFT,CALU1 +S 3000,3000,3000,3000,400,c,LEFT,CALU1 +S 1000,5700,1000,6700,600,*,UP,PDIF +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,5000,5000,10000,nr3_x05,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 1200,5700,1200,9200,400,*,UP,PDIF +S 1600,5500,1600,9400,200,1,UP,PTRANS +S 1600,9400,1600,9700,200,*,DOWN,POLY +S 2400,5500,2400,9400,200,2,UP,PTRANS +S 2000,5700,2000,9200,600,n2,DOWN,PDIF +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 3200,5500,3200,9400,200,3,UP,PTRANS +S 2800,5700,2800,9200,600,n1,DOWN,PDIF +S 3200,9400,3200,9700,200,*,DOWN,POLY +S 3800,5700,3800,9200,800,*,DOWN,PDIF +S 3200,5100,3800,5100,200,*,RIGHT,POLY +S 2400,4500,2400,5500,200,*,UP,POLY +S 1400,1600,1400,2400,200,4,DOWN,NTRANS +S 2600,1600,2600,2400,200,5,DOWN,NTRANS +S 3800,1600,3800,2400,200,6,DOWN,NTRANS +S 2000,900,2000,2200,600,*,UP,NDIF +S 900,1800,900,2200,800,*,DOWN,NDIF +S 3200,1800,3200,2200,1000,*,UP,NDIF +S 700,2000,3300,2000,400,*,RIGHT,ALU1 +S 4400,700,4400,2100,400,*,DOWN,ALU1 +S 4400,1800,4400,2200,600,*,UP,NDIF +S 3800,2400,3800,4600,200,*,UP,POLY +S 2000,3000,4100,3000,400,*,LEFT,ALU1 +S 2000,2900,4100,2900,400,*,LEFT,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1000,2000,1000,7100,400,*,DOWN,ALU1 +S 1400,1200,1400,1600,200,*,DOWN,POLY +S 2600,1200,2600,1600,200,*,DOWN,POLY +S 3800,1200,3800,1600,200,*,DOWN,POLY +S 2600,2800,2800,2800,200,*,RIGHT,POLY +S 2600,2900,2800,2900,200,*,RIGHT,POLY +S 2000,3000,2000,4000,400,c,UP,CALU1 +S 3000,3900,3000,5100,400,*,DOWN,ALU1 +S 3000,4000,3000,5000,400,b,UP,CALU1 +S 2900,6000,4000,6000,400,*,RIGHT,ALU1 +S 2900,6100,4000,6100,400,*,RIGHT,ALU1 +S 3000,6000,3000,6000,400,a,LEFT,CALU1 +S 4000,4800,4000,6100,400,*,UP,ALU1 +S 4000,5000,4000,6000,400,a,UP,CALU1 +S 4000,4000,4000,4000,400,b,LEFT,CALU1 +S 3000,3900,4100,3900,400,*,RIGHT,ALU1 +S 3000,4000,4100,4000,400,*,RIGHT,ALU1 +S 2000,2900,2000,4100,400,*,DOWN,ALU1 +S 3800,6900,3800,9300,400,*,UP,ALU1 +V 4200,700,CONT_BODY_P,* +V 3500,700,CONT_BODY_P,* +V 2000,3700,CONT_POLY,* +V 3000,4300,CONT_POLY,* +V 1000,6600,CONT_DIF_P,* +V 4400,2000,CONT_DIF_N,* +V 4000,4900,CONT_POLY,* +V 3200,2000,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 1000,5800,CONT_DIF_P,* +V 3800,8000,CONT_DIF_P,* +V 3800,9000,CONT_DIF_P,* +V 3800,7000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nr3_x05.vbe b/pdks/symbolic/msxlib/cells/nr3_x05.vbe new file mode 100644 index 000000000..7d04efe21 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr3_x05.vbe @@ -0,0 +1,38 @@ +ENTITY nr3_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT cin_a : NATURAL := 5; + CONSTANT rdown_b_z : NATURAL := 2890; + CONSTANT rdown_c_z : NATURAL := 2880; + CONSTANT rdown_a_z : NATURAL := 2940; + CONSTANT rup_b_z : NATURAL := 4480; + CONSTANT rup_c_z : NATURAL := 4480; + CONSTANT rup_a_z : NATURAL := 4480; + CONSTANT tplh_a_z : NATURAL := 80; + CONSTANT tphl_c_z : NATURAL := 49; + CONSTANT tplh_c_z : NATURAL := 50; + CONSTANT tplh_b_z : NATURAL := 71; + CONSTANT tphl_b_z : NATURAL := 62; + CONSTANT tphl_a_z : NATURAL := 70; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr3_x05; + +ARCHITECTURE behaviour_data_flow OF nr3_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr3_x05" + SEVERITY WARNING; + z <= not (((b or c) or a)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nr3_x1.ap b/pdks/symbolic/msxlib/cells/nr3_x1.ap new file mode 100644 index 000000000..580488068 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr3_x1.ap @@ -0,0 +1,127 @@ +V ALLIANCE : 6 +H nr3_x1,P, 9/ 8/2014,100 +A 0,0,7000,10000 +R 3000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 1000,2000,ref_ref,z_20 +R 1000,3000,ref_ref,z_30 +R 3000,7000,ref_ref,z_70 +R 2000,4000,ref_ref,a_40 +R 2000,3000,ref_ref,a_30 +R 6000,5000,ref_ref,a_50 +R 2000,5000,ref_ref,a_50 +R 2000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 3000,4000,ref_ref,b_40 +R 3000,6000,ref_ref,a_60 +R 4000,6000,ref_ref,a_60 +R 5000,6000,ref_ref,a_60 +R 6000,6000,ref_ref,a_60 +R 5000,5000,ref_ref,b_50 +R 4000,5000,ref_ref,b_50 +R 3000,5000,ref_ref,b_50 +R 3000,3000,ref_ref,b_30 +R 1000,7000,ref_ref,z_70 +R 2000,6000,ref_ref,a_60 +R 6000,3000,ref_ref,c_30 +R 6000,2000,ref_ref,c_20 +R 6000,4000,ref_ref,c_40 +R 5000,3000,ref_ref,c_30 +R 4000,3000,ref_ref,c_30 +S 3000,7000,3000,7000,400,z,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 3000,6000,3000,6000,400,a,LEFT,CALU1 +S 4000,6000,4000,6000,400,a,LEFT,CALU1 +S 5000,6000,5000,6000,400,a,LEFT,CALU1 +S 5000,5000,5000,5000,400,b,LEFT,CALU1 +S 4000,5000,4000,5000,400,b,LEFT,CALU1 +S 800,5700,800,9200,800,*,DOWN,PDIF +S 2000,2900,2000,3100,400,*,DOWN,ALU1 +S 4000,4900,4000,5000,600,*,UP,ALU1 +S 5400,5700,5400,9200,600,n3,DOWN,PDIF +S 4600,5700,4600,9200,600,n4,DOWN,PDIF +S 1800,5700,1800,9200,600,n1,DOWN,PDIF +S 2600,5700,2600,9200,600,n2,DOWN,PDIF +S 5800,5500,5800,9400,200,6,UP,PTRANS +S 5000,5500,5000,9400,200,5,UP,PTRANS +S 4200,5500,4200,9400,200,4,UP,PTRANS +S 6300,5700,6300,9200,800,*,DOWN,PDIF +S 5800,9400,5800,9700,200,*,DOWN,POLY +S 5000,9400,5000,9700,200,*,DOWN,POLY +S 4200,9400,4200,9700,200,*,DOWN,POLY +S 1400,9400,1400,9700,200,*,DOWN,POLY +S 2200,4500,2600,4500,200,*,LEFT,POLY +S 3500,5700,3500,9200,800,*,DOWN,PDIF +S 3000,5500,3000,9400,200,3,UP,PTRANS +S 1400,5500,1400,9400,200,1,UP,PTRANS +S 2200,5500,2200,9400,200,2,UP,PTRANS +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,5000,7000,5000,10000,nr3_x1,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 3000,9400,3000,9700,200,*,DOWN,POLY +S 2200,9400,2200,9700,200,*,DOWN,POLY +S 3000,3000,3000,5000,400,b,UP,CALU1 +S 3000,2900,3000,5100,400,*,UP,ALU1 +S 3000,5100,4200,5100,200,*,RIGHT,POLY +S 3000,5000,5100,5000,600,*,RIGHT,ALU1 +S 1400,3800,1400,5500,200,*,UP,POLY +S 2200,4500,2200,5500,200,*,UP,POLY +S 2000,3000,2000,6000,400,a,UP,CALU1 +S 2000,4100,2000,6000,400,*,UP,ALU1 +S 2000,6000,6000,6000,400,*,LEFT,ALU1 +S 6000,5000,6000,6000,400,a,UP,CALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 1000,2000,1000,7000,400,*,DOWN,ALU1 +S 3600,7000,3600,8100,400,*,UP,ALU1 +S 800,7900,800,9300,400,*,UP,ALU1 +S 6400,7900,6400,9300,400,*,UP,ALU1 +S 1900,2900,1900,6000,400,*,UP,ALU1 +S 1400,3800,1800,3800,200,*,RIGHT,POLY +S 1000,2000,3700,2000,400,*,RIGHT,ALU1 +S 1000,1900,3700,1900,400,*,RIGHT,ALU1 +S 6000,4900,6000,6000,600,*,UP,ALU1 +S 1400,900,1400,2000,400,*,DOWN,NDIF +S 1800,700,1800,2200,200,7,DOWN,NTRANS +S 1800,300,1800,700,200,*,UP,POLY +S 1800,2200,1800,3600,200,*,UP,POLY +S 3600,900,3600,2000,1000,*,UP,NDIF +S 4200,700,4200,2200,200,9,DOWN,NTRANS +S 3000,700,3000,2200,200,8,DOWN,NTRANS +S 2400,900,2400,2000,600,*,UP,NDIF +S 4900,900,4900,2000,600,*,UP,NDIF +S 4200,2200,4200,5100,200,*,UP,POLY +S 3000,2200,3000,4500,200,*,UP,POLY +S 1000,7100,3600,7100,400,*,RIGHT,ALU1 +S 1000,7000,3600,7000,400,*,RIGHT,ALU1 +S 6000,2000,6000,4000,400,c,UP,CALU1 +S 4000,3000,4000,3000,400,c,LEFT,CALU1 +S 5000,3000,5000,3000,400,c,LEFT,CALU1 +S 4000,3000,6000,3000,600,*,RIGHT,ALU1 +S 4200,300,4200,700,200,*,UP,POLY +S 3000,300,3000,700,200,*,UP,POLY +S 4800,700,4800,1900,400,*,UP,ALU1 +S 6000,1900,6000,4100,400,*,UP,ALU1 +V 6200,700,CONT_BODY_P,* +V 3600,7100,CONT_DIF_P,* +V 6000,4900,CONT_POLY,* +V 3600,8000,CONT_DIF_P,* +V 3000,4300,CONT_POLY,* +V 5000,4900,CONT_POLY,* +V 2000,3600,CONT_POLY,* +V 800,8000,CONT_DIF_P,* +V 6400,8000,CONT_DIF_P,* +V 800,9000,CONT_DIF_P,* +V 6400,9000,CONT_DIF_P,* +V 4800,1000,CONT_DIF_N,* +V 2400,1000,CONT_DIF_N,* +V 1200,1900,CONT_DIF_N,* +V 3600,1900,CONT_DIF_N,* +V 4000,3000,CONT_POLY,* +V 4800,1800,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nr3_x1.vbe b/pdks/symbolic/msxlib/cells/nr3_x1.vbe new file mode 100644 index 000000000..d4c2e8947 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY nr3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_b : NATURAL := 10; + CONSTANT cin_c : NATURAL := 9; + CONSTANT cin_a : NATURAL := 11; + CONSTANT rdown_b_z : NATURAL := 1540; + CONSTANT rdown_c_z : NATURAL := 1540; + CONSTANT rdown_a_z : NATURAL := 1570; + CONSTANT rup_b_z : NATURAL := 2240; + CONSTANT rup_c_z : NATURAL := 2230; + CONSTANT rup_a_z : NATURAL := 2240; + CONSTANT tplh_a_z : NATURAL := 78; + CONSTANT tphl_c_z : NATURAL := 47; + CONSTANT tplh_c_z : NATURAL := 45; + CONSTANT tplh_b_z : NATURAL := 67; + CONSTANT tphl_b_z : NATURAL := 62; + CONSTANT tphl_a_z : NATURAL := 71; + CONSTANT transistors : NATURAL := 9 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr3_x1; + +ARCHITECTURE behaviour_data_flow OF nr3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr3_x1" + SEVERITY WARNING; + z <= not (((b or c) or a)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nr4_x05.ap b/pdks/symbolic/msxlib/cells/nr4_x05.ap new file mode 100644 index 000000000..af0a64d63 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr4_x05.ap @@ -0,0 +1,118 @@ +V ALLIANCE : 6 +H nr4_x05,P, 9/ 8/2014,100 +A 0,0,6000,10000 +R 3000,5000,ref_ref,d_50 +R 1000,6000,ref_ref,z_60 +R 3000,6000,ref_ref,d_60 +R 5000,7000,ref_ref,a_70 +R 5000,6000,ref_ref,a_60 +R 5000,4000,ref_ref,b_40 +R 2000,4000,ref_ref,d_40 +R 4000,5000,ref_ref,c_50 +R 3000,3000,ref_ref,c_30 +R 2000,7000,ref_ref,z_70 +R 4000,2000,ref_ref,z_20 +R 3000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 4000,3000,ref_ref,b_30 +R 5000,5000,ref_ref,a_50 +R 1000,3000,ref_ref,z_30 +R 1000,4000,ref_ref,z_40 +R 4000,4000,ref_ref,c_40 +R 2000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 5000,3000,ref_ref,b_30 +R 3000,4000,ref_ref,c_40 +R 2000,5000,ref_ref,d_50 +R 1000,2000,ref_ref,z_20 +R 4000,7000,ref_ref,a_70 +S 4300,700,5100,700,600,*,RIGHT,PTIE +S 4800,4900,5000,4900,600,*,RIGHT,POLY +S 2200,5100,2400,5100,200,*,LEFT,POLY +S 1000,6000,2000,6000,600,*,LEFT,ALU1 +S 3900,3000,5000,3000,400,*,RIGHT,ALU1 +S 5000,5000,5000,7000,400,a,UP,CALU1 +S 4800,9400,4800,9700,200,*,DOWN,POLY +S 4000,9400,4000,9700,200,*,DOWN,POLY +S 3200,9400,3200,9700,200,*,DOWN,POLY +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 1800,1900,1800,2100,1000,*,UP,NDIF +S 3000,900,3000,2100,600,*,UP,NDIF +S 4200,1900,4200,2100,1000,*,UP,NDIF +S 600,900,600,2100,600,*,UP,NDIF +S 0,5000,6000,5000,10000,nr4_x05,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 2400,3800,2800,3800,200,*,LEFT,POLY +S 1200,1300,1200,1900,200,*,UP,POLY +S 2400,1300,2400,1900,200,*,UP,POLY +S 3600,1300,3600,1900,200,*,UP,POLY +S 4800,1300,4800,1900,200,*,UP,POLY +S 1200,1700,1200,2300,200,5,DOWN,NTRANS +S 2400,1700,2400,2300,200,6,DOWN,NTRANS +S 3600,1700,3600,2300,200,7,DOWN,NTRANS +S 4800,1700,4800,2300,200,8,DOWN,NTRANS +S 1200,4700,2000,4700,200,*,LEFT,POLY +S 2400,5500,2400,9400,200,1,UP,PTRANS +S 2800,5700,2800,9200,600,n3,UP,PDIF +S 3200,5500,3200,9400,200,2,UP,PTRANS +S 3600,5700,3600,9200,600,n2,UP,PDIF +S 4000,5500,4000,9400,200,3,UP,PTRANS +S 4800,5500,4800,9400,200,4,UP,PTRANS +S 4400,5700,4400,9200,600,n1,UP,PDIF +S 5400,5700,5400,9200,600,*,DOWN,PDIF +S 5400,7900,5400,9300,400,*,DOWN,ALU1 +S 1800,5900,1800,7100,600,*,UP,PDIF +S 2000,5700,2000,9200,400,*,DOWN,PDIF +S 5000,4900,5000,7000,600,*,DOWN,ALU1 +S 5000,3000,5000,4100,400,*,UP,ALU1 +S 5000,3000,5000,4000,400,b,UP,CALU1 +S 3900,2900,5000,2900,400,*,RIGHT,ALU1 +S 3000,3000,3000,4000,400,c,DOWN,CALU1 +S 3000,2900,3000,4000,400,*,DOWN,ALU1 +S 3000,4000,4000,4000,600,*,RIGHT,ALU1 +S 4000,4000,4000,5000,400,c,UP,CALU1 +S 4000,4000,4000,5100,400,*,UP,ALU1 +S 2000,5000,3000,5000,600,*,RIGHT,ALU1 +S 2000,3900,2000,4600,400,*,DOWN,ALU1 +S 3000,5000,3000,6100,400,*,UP,ALU1 +S 3000,5000,3000,6000,400,d,UP,CALU1 +S 3200,4000,3200,5500,200,*,DOWN,POLY +S 4000,3200,4000,5500,200,*,DOWN,POLY +S 3600,2300,3600,3200,200,*,UP,POLY +S 4800,2300,4800,5500,200,*,DOWN,POLY +S 2400,2300,2400,3800,200,*,DOWN,POLY +S 1200,2300,1200,4700,200,*,DOWN,POLY +S 1000,2000,1000,6000,400,z,DOWN,CALU1 +S 1000,2000,1000,6000,400,*,DOWN,ALU1 +S 1000,2000,4300,2000,400,*,RIGHT,ALU1 +S 5400,700,5400,2100,400,*,DOWN,ALU1 +S 1000,1900,4300,1900,400,*,RIGHT,ALU1 +S 3900,7000,5000,7000,400,*,RIGHT,ALU1 +S 1900,5900,1900,7100,600,*,DOWN,ALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 4000,2000,4000,2000,400,z,LEFT,CALU1 +S 2000,6000,2000,7000,400,z,UP,CALU1 +S 2000,4000,2000,5000,400,d,DOWN,CALU1 +S 4000,3000,4000,3000,400,b,LEFT,CALU1 +S 4000,7000,4000,7000,400,a,LEFT,CALU1 +V 700,9300,CONT_BODY_N,* +V 5200,700,CONT_BODY_P,* +V 4200,700,CONT_BODY_P,* +V 4000,3000,CONT_POLY,* +V 600,1000,CONT_DIF_N,* +V 3000,1000,CONT_DIF_N,* +V 1800,2000,CONT_DIF_N,* +V 4200,2000,CONT_DIF_N,* +V 1800,7000,CONT_DIF_P,* +V 1800,6000,CONT_DIF_P,* +V 3200,4000,CONT_POLY,* +V 5400,8000,CONT_DIF_P,* +V 5400,9000,CONT_DIF_P,* +V 5000,4900,CONT_POLY,* +V 2200,4900,CONT_POLY,* +V 5400,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nr4_x05.vbe b/pdks/symbolic/msxlib/cells/nr4_x05.vbe new file mode 100644 index 000000000..d7f5ce15f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr4_x05.vbe @@ -0,0 +1,44 @@ +ENTITY nr4_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_c : NATURAL := 5; + CONSTANT cin_d : NATURAL := 5; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a : NATURAL := 5; + CONSTANT rdown_c_z : NATURAL := 3840; + CONSTANT rdown_d_z : NATURAL := 3840; + CONSTANT rdown_b_z : NATURAL := 3910; + CONSTANT rdown_a_z : NATURAL := 4010; + CONSTANT rup_c_z : NATURAL := 5980; + CONSTANT rup_d_z : NATURAL := 5980; + CONSTANT rup_b_z : NATURAL := 5980; + CONSTANT rup_a_z : NATURAL := 5980; + CONSTANT tphl_d_z : NATURAL := 58; + CONSTANT tplh_a_z : NATURAL := 117; + CONSTANT tplh_d_z : NATURAL := 52; + CONSTANT tphl_c_z : NATURAL := 77; + CONSTANT tplh_b_z : NATURAL := 107; + CONSTANT tplh_c_z : NATURAL := 86; + CONSTANT tphl_b_z : NATURAL := 90; + CONSTANT tphl_a_z : NATURAL := 97; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + c : in BIT; + d : in BIT; + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr4_x05; + +ARCHITECTURE behaviour_data_flow OF nr4_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr4_x05" + SEVERITY WARNING; + z <= not ((((c or d) or b) or a)) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/nr4_x1.ap b/pdks/symbolic/msxlib/cells/nr4_x1.ap new file mode 100644 index 000000000..583cb7d13 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr4_x1.ap @@ -0,0 +1,170 @@ +V ALLIANCE : 6 +H nr4_x1,P, 9/ 8/2014,100 +A 0,0,9000,10000 +R 7000,5000,ref_ref,d_50 +R 7000,7000,ref_ref,d_70 +R 7000,6000,ref_ref,d_60 +R 2000,2000,ref_ref,z_20 +R 7000,4000,ref_ref,b_40 +R 7000,3000,ref_ref,b_30 +R 5000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,a_60 +R 3000,5000,ref_ref,a_50 +R 5000,7000,ref_ref,z_70 +R 4000,7000,ref_ref,z_70 +R 3000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 2000,6000,ref_ref,z_60 +R 7000,8000,ref_ref,d_80 +R 6000,8000,ref_ref,d_80 +R 5000,8000,ref_ref,d_80 +R 4000,8000,ref_ref,d_80 +R 3000,8000,ref_ref,d_80 +R 2000,8000,ref_ref,d_80 +R 1000,8000,ref_ref,d_80 +R 1000,7000,ref_ref,d_70 +R 4000,3000,ref_ref,b_30 +R 3000,3000,ref_ref,b_30 +R 4000,5000,ref_ref,a_50 +R 6000,4000,ref_ref,c_40 +R 6000,3000,ref_ref,b_30 +R 1000,5000,ref_ref,d_50 +R 4000,2000,ref_ref,z_20 +R 3000,2000,ref_ref,z_20 +R 4000,4000,ref_ref,c_40 +R 5000,3000,ref_ref,b_30 +R 5000,4000,ref_ref,c_40 +R 2000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +R 2000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,d_60 +R 8000,5000,ref_ref,d_50 +R 3000,4000,ref_ref,a_40 +R 6000,5000,ref_ref,c_50 +R 6000,6000,ref_ref,c_60 +R 7000,2000,ref_ref,b_20 +R 5000,6000,ref_ref,z_60 +S 7100,700,7900,700,600,*,RIGHT,PTIE +S 7100,4900,7100,8000,400,*,UP,ALU1 +S 7000,4900,7000,8000,400,*,UP,ALU1 +S 900,4800,900,8000,400,*,DOWN,ALU1 +S 8400,6900,8400,9300,400,*,DOWN,ALU1 +S 7000,4900,8100,4900,400,*,RIGHT,ALU1 +S 7000,5000,8100,5000,400,*,RIGHT,ALU1 +S 1000,8000,7000,8000,400,*,LEFT,ALU1 +S 5000,900,5000,1300,200,*,UP,POLY +S 3800,900,3800,1300,200,*,UP,POLY +S 2000,1900,4500,1900,400,*,RIGHT,ALU1 +S 2000,2000,4500,2000,400,*,RIGHT,ALU1 +S 2000,2000,2000,7000,400,*,DOWN,ALU1 +S 2000,2000,2000,7000,400,z,DOWN,CALU1 +S 7000,1900,7000,4100,400,*,DOWN,ALU1 +S 7000,2000,7000,4000,400,b,DOWN,CALU1 +S 5000,2400,5000,5100,200,*,UP,POLY +S 4200,5100,5400,5100,200,*,RIGHT,POLY +S 3900,4000,6000,4000,400,*,LEFT,ALU1 +S 3900,3900,6000,3900,400,*,LEFT,ALU1 +S 5000,1300,5000,2400,200,12,DOWN,NTRANS +S 4400,1500,4400,2200,1000,*,UP,NDIF +S 3800,2400,3800,3900,200,*,UP,POLY +S 3800,1300,3800,2400,200,11,DOWN,NTRANS +S 3200,900,3200,2200,600,*,UP,NDIF +S 2600,900,2600,1300,200,*,UP,POLY +S 1400,900,1400,1300,200,*,UP,POLY +S 2600,2400,2600,5500,200,*,DOWN,POLY +S 2600,1300,2600,2400,200,10,DOWN,NTRANS +S 2000,1500,2000,2200,1000,*,UP,NDIF +S 1400,1300,1400,2400,200,9,DOWN,NTRANS +S 7000,3200,7000,5500,200,*,DOWN,POLY +S 6200,4200,6200,5500,200,*,DOWN,POLY +S 6000,4000,6000,6000,400,c,UP,CALU1 +S 6000,4000,6000,6100,400,*,UP,ALU1 +S 3000,3900,3000,6100,400,*,DOWN,ALU1 +S 3000,4000,3000,6000,400,a,DOWN,CALU1 +S 3400,4100,3400,5500,200,*,DOWN,POLY +S 3400,4100,4200,4100,200,*,RIGHT,POLY +S 1000,4800,1000,8000,400,*,DOWN,ALU1 +S 1000,5000,1000,8000,400,d,UP,CALU1 +S 1200,5700,1200,9200,600,*,UP,PDIF +S 8400,5700,8400,9200,600,*,DOWN,PDIF +S 7800,5500,7800,9400,200,08,UP,PTRANS +S 7400,5700,7400,9200,600,n4,UP,PDIF +S 7000,5500,7000,9400,200,07,UP,PTRANS +S 6600,5700,6600,9200,600,n5,UP,PDIF +S 6200,5500,6200,9400,200,06,UP,PTRANS +S 5800,5700,5800,9200,600,n6,UP,PDIF +S 4800,5700,4800,9200,600,*,DOWN,PDIF +S 5400,5500,5400,9400,200,05,UP,PTRANS +S 4200,5500,4200,9400,200,04,UP,PTRANS +S 3800,5700,3800,9200,600,n3,UP,PDIF +S 3400,5500,3400,9400,200,03,UP,PTRANS +S 3000,5700,3000,9200,600,n2,UP,PDIF +S 2600,5500,2600,9400,200,02,UP,PTRANS +S 2200,5700,2200,9200,600,n1,UP,PDIF +S 1800,5500,1800,9400,200,01,UP,PTRANS +S 0,5000,9000,5000,10000,nr4_x1,LEFT,TALU8 +S 0,2200,9000,2200,5200,*,LEFT,PWELL +S 0,7600,9000,7600,5600,*,LEFT,NWELL +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 4200,9400,4200,9700,200,*,DOWN,POLY +S 3400,9400,3400,9700,200,*,DOWN,POLY +S 2600,9400,2600,9700,200,*,DOWN,POLY +S 1800,9400,1800,9700,200,*,DOWN,POLY +S 5400,9400,5400,9700,200,*,DOWN,POLY +S 6200,9400,6200,9700,200,*,DOWN,POLY +S 7000,9400,7000,9700,200,*,DOWN,POLY +S 7800,9400,7800,9700,200,*,DOWN,POLY +S 2900,3000,7000,3000,400,*,RIGHT,ALU1 +S 800,700,800,2100,400,*,DOWN,ALU1 +S 700,1500,700,2200,600,*,UP,NDIF +S 5600,700,5600,2100,400,*,DOWN,ALU1 +S 5700,1500,5700,2200,600,*,UP,NDIF +S 2000,7000,5000,7000,400,*,LEFT,ALU1 +S 2000,7100,5000,7100,400,*,LEFT,ALU1 +S 4900,5900,4900,7000,600,*,UP,ALU1 +S 2000,8000,2000,8000,400,d,LEFT,CALU1 +S 3000,8000,3000,8000,400,d,LEFT,CALU1 +S 4000,8000,4000,8000,400,d,LEFT,CALU1 +S 5000,8000,5000,8000,400,d,LEFT,CALU1 +S 6000,8000,6000,8000,400,d,LEFT,CALU1 +S 8000,5000,8000,5000,400,d,LEFT,CALU1 +S 7000,5000,7000,8000,400,d,DOWN,CALU1 +S 1400,2400,1400,5100,200,*,DOWN,POLY +S 1400,5100,1800,5100,200,*,LEFT,POLY +S 3000,7000,3000,7000,400,z,LEFT,CALU1 +S 4000,7000,4000,7000,400,z,LEFT,CALU1 +S 4000,2000,4000,2000,400,z,LEFT,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 5000,6000,5000,7000,400,z,DOWN,CALU1 +S 6000,3000,6000,3000,400,b,LEFT,CALU1 +S 5000,3000,5000,3000,400,b,LEFT,CALU1 +S 4000,3000,4000,3000,400,b,LEFT,CALU1 +S 3000,3000,3000,3000,400,b,LEFT,CALU1 +S 4000,4000,4000,4000,400,c,LEFT,CALU1 +S 5000,4000,5000,4000,400,c,LEFT,CALU1 +S 4000,5000,4000,5000,400,a,LEFT,CALU1 +S 5000,5000,5000,5000,400,a,LEFT,CALU1 +S 3000,4900,5100,4900,400,*,RIGHT,ALU1 +S 3000,5000,5100,5000,400,*,RIGHT,ALU1 +V 8000,700,CONT_BODY_P,* +V 7000,700,CONT_BODY_P,* +V 8400,7000,CONT_DIF_P,* +V 8400,8000,CONT_DIF_P,* +V 4800,6000,CONT_DIF_P,* +V 4800,4900,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 4400,2000,CONT_DIF_N,* +V 4000,3900,CONT_POLY,* +V 3200,1000,CONT_DIF_N,* +V 3000,3000,CONT_POLY,* +V 2000,2000,CONT_DIF_N,* +V 4800,7000,CONT_DIF_P,* +V 8400,9000,CONT_DIF_P,* +V 1200,9000,CONT_DIF_P,* +V 1000,4900,CONT_POLY,* +V 8000,4900,CONT_POLY,* +V 6800,3000,CONT_POLY,* +V 800,2000,CONT_DIF_N,* +V 5600,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/nr4_x1.vbe b/pdks/symbolic/msxlib/cells/nr4_x1.vbe new file mode 100644 index 000000000..126605b65 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/nr4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY nr4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 9000; + CONSTANT cin_c : NATURAL := 9; + CONSTANT cin_d : NATURAL := 11; + CONSTANT cin_b : NATURAL := 10; + CONSTANT cin_a : NATURAL := 9; + CONSTANT rdown_c_z : NATURAL := 2100; + CONSTANT rdown_d_z : NATURAL := 2180; + CONSTANT rdown_b_z : NATURAL := 2130; + CONSTANT rdown_a_z : NATURAL := 2100; + CONSTANT rup_c_z : NATURAL := 2990; + CONSTANT rup_d_z : NATURAL := 3000; + CONSTANT rup_b_z : NATURAL := 2990; + CONSTANT rup_a_z : NATURAL := 2990; + CONSTANT tphl_d_z : NATURAL := 102; + CONSTANT tplh_a_z : NATURAL := 46; + CONSTANT tplh_d_z : NATURAL := 112; + CONSTANT tphl_c_z : NATURAL := 78; + CONSTANT tplh_b_z : NATURAL := 102; + CONSTANT tplh_c_z : NATURAL := 80; + CONSTANT tphl_b_z : NATURAL := 92; + CONSTANT tphl_a_z : NATURAL := 57; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + c : in BIT; + d : in BIT; + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr4_x1; + +ARCHITECTURE behaviour_data_flow OF nr4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr4_x1" + SEVERITY WARNING; + z <= not ((((c or d) or b) or a)) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/oai21_x05.ap b/pdks/symbolic/msxlib/cells/oai21_x05.ap new file mode 100644 index 000000000..62ae640ae --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai21_x05.ap @@ -0,0 +1,96 @@ +V ALLIANCE : 6 +H oai21_x05,P, 9/ 8/2014,100 +A 0,0,5000,10000 +R 1000,2000,ref_ref,z_20 +R 3000,7000,ref_ref,a1_70 +R 3000,4000,ref_ref,a2_40 +R 2000,3000,ref_ref,b_30 +R 3000,3000,ref_ref,b_30 +R 2000,4000,ref_ref,b_40 +R 4000,5000,ref_ref,a1_50 +R 3000,5000,ref_ref,a2_50 +R 1000,3000,ref_ref,z_30 +R 2000,5000,ref_ref,b_50 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +R 4000,4000,ref_ref,a2_40 +R 3000,6000,ref_ref,a2_60 +R 4000,6000,ref_ref,a1_60 +R 4000,7000,ref_ref,a1_70 +R 2000,6000,ref_ref,z_60 +R 2000,7000,ref_ref,z_70 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 4000,7900,4000,9300,400,*,UP,ALU1 +S 800,6900,800,9300,400,*,UP,ALU1 +S 3800,1300,3800,1700,200,*,DOWN,POLY +S 2600,1300,2600,1700,200,*,DOWN,POLY +S 1400,1300,1400,1700,200,*,DOWN,POLY +S 3800,2700,3800,4800,200,*,UP,POLY +S 2900,7100,4000,7100,400,*,LEFT,ALU1 +S 2900,7000,4000,7000,400,*,LEFT,ALU1 +S 2000,3000,2000,5000,400,b,DOWN,CALU1 +S 2000,2900,2000,5100,400,*,DOWN,ALU1 +S 2000,2900,3100,2900,400,*,RIGHT,ALU1 +S 2000,3000,3100,3000,400,*,RIGHT,ALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,5000,5000,10000,oai21_x05,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 1900,2000,4500,2000,400,*,RIGHT,ALU1 +S 700,2000,1000,2000,600,*,RIGHT,ALU1 +S 1800,1900,1800,2500,400,*,DOWN,NDIF +S 1400,1700,1400,2700,200,6,UP,NTRANS +S 1000,1900,1000,2500,400,*,UP,NDIF +S 2000,1900,2000,2500,1000,*,DOWN,NDIF +S 2600,1700,2600,2700,200,5,UP,NTRANS +S 4200,1900,4200,2500,400,*,UP,NDIF +S 3800,1700,3800,2700,200,4,UP,NTRANS +S 3200,900,3200,2500,600,*,UP,NDIF +S 3000,4000,4100,4000,400,*,RIGHT,ALU1 +S 4000,5000,4000,7000,400,a1,UP,CALU1 +S 3000,3900,4100,3900,400,*,RIGHT,ALU1 +S 3000,4000,3000,6000,400,a2,DOWN,CALU1 +S 3000,4000,3000,6100,400,*,UP,ALU1 +S 1000,2000,1000,6000,400,z,DOWN,CALU1 +S 1000,2000,1000,6000,400,*,DOWN,ALU1 +S 1400,7300,1400,7700,200,*,DOWN,POLY +S 1400,6100,1400,7300,200,3,DOWN,PTRANS +S 2000,6300,2000,7100,600,*,UP,PDIF +S 800,6300,800,7100,600,*,DOWN,PDIF +S 1000,6000,2000,6000,600,*,RIGHT,ALU1 +S 2000,6000,2000,7100,400,*,UP,ALU1 +S 3400,6100,3400,8400,200,1,DOWN,PTRANS +S 3000,6300,3000,8200,400,n1,UP,PDIF +S 2600,6100,2600,8400,200,2,DOWN,PTRANS +S 2200,6300,2200,8200,400,*,DOWN,PDIF +S 4000,6300,4000,8200,600,*,DOWN,PDIF +S 3400,8400,3400,8800,200,*,DOWN,POLY +S 2600,8400,2600,8800,200,*,DOWN,POLY +S 1400,2700,1400,6100,200,*,UP,POLY +S 2600,2700,2600,6100,200,*,UP,POLY +S 2000,6000,2000,7000,400,z,UP,CALU1 +S 3400,5200,3800,5200,200,*,RIGHT,POLY +S 3400,5200,3400,6100,200,*,DOWN,POLY +S 4000,4900,4000,7000,400,*,UP,ALU1 +S 1800,5000,2000,5000,600,*,RIGHT,ALU1 +S 3000,3000,3000,3000,400,b,LEFT,CALU1 +S 4000,4000,4000,4000,400,a2,LEFT,CALU1 +S 3000,7000,3000,7000,400,a1,LEFT,CALU1 +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 4000,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 3200,1000,CONT_DIF_N,* +V 4400,2000,CONT_DIF_N,n2 +V 2000,2000,CONT_DIF_N,n2 +V 800,2000,CONT_DIF_N,* +V 2000,7000,CONT_DIF_P,* +V 4000,5000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 1800,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/oai21_x05.vbe b/pdks/symbolic/msxlib/cells/oai21_x05.vbe new file mode 100644 index 000000000..ec2c4e035 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai21_x05.vbe @@ -0,0 +1,38 @@ +ENTITY oai21_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_a2 : NATURAL := 4; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 3700; + CONSTANT rdown_a2_z : NATURAL := 3700; + CONSTANT rdown_b_z : NATURAL := 3420; + CONSTANT rup_a1_z : NATURAL := 5060; + CONSTANT rup_a2_z : NATURAL := 5060; + CONSTANT rup_b_z : NATURAL := 4960; + CONSTANT tphl_b_z : NATURAL := 42; + CONSTANT tphl_a2_z : NATURAL := 47; + CONSTANT tplh_a1_z : NATURAL := 72; + CONSTANT tplh_b_z : NATURAL := 50; + CONSTANT tplh_a2_z : NATURAL := 62; + CONSTANT tphl_a1_z : NATURAL := 57; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai21_x05; + +ARCHITECTURE behaviour_data_flow OF oai21_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai21_x05" + SEVERITY WARNING; + z <= not (((a1 or a2) and b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/oai21_x1.ap b/pdks/symbolic/msxlib/cells/oai21_x1.ap new file mode 100644 index 000000000..4cd76d46b --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai21_x1.ap @@ -0,0 +1,100 @@ +V ALLIANCE : 6 +H oai21_x1,P, 9/ 8/2014,100 +A 0,0,5000,10000 +R 1000,2000,ref_ref,z_20 +R 4000,4000,ref_ref,a2_40 +R 3000,4000,ref_ref,a2_40 +R 4000,6000,ref_ref,a1_60 +R 4000,7000,ref_ref,a1_70 +R 3000,7000,ref_ref,a1_70 +R 2000,6000,ref_ref,z_60 +R 2000,7000,ref_ref,z_70 +R 2000,3000,ref_ref,b_30 +R 3000,3000,ref_ref,b_30 +R 2000,4000,ref_ref,b_40 +R 3000,6000,ref_ref,a2_60 +R 4000,5000,ref_ref,a1_50 +R 3000,5000,ref_ref,a2_50 +R 1000,3000,ref_ref,z_30 +R 2000,5000,ref_ref,b_50 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 1800,4000,2000,4000,600,*,RIGHT,ALU1 +S 3800,3300,3800,4800,200,*,UP,POLY +S 2600,3300,2600,5500,200,*,UP,POLY +S 1400,3300,1400,5500,200,*,UP,POLY +S 1000,1800,1000,3100,400,*,UP,NDIF +S 800,2300,800,2900,600,*,UP,NDIF +S 3200,900,3200,3100,600,*,UP,NDIF +S 3800,1600,3800,3300,200,4,UP,NTRANS +S 4200,1800,4200,3100,400,*,UP,NDIF +S 1400,1600,1400,3300,200,6,UP,NTRANS +S 2600,1600,2600,3300,200,5,UP,NTRANS +S 2000,1800,2000,3100,600,*,DOWN,NDIF +S 1400,1200,1400,1600,200,*,UP,POLY +S 2600,1200,2600,1600,200,*,UP,POLY +S 3800,1200,3800,1600,200,*,UP,POLY +S 4400,2300,4400,2900,600,*,UP,NDIF +S 4400,2000,4400,3100,400,*,UP,ALU1 +S 1900,2000,4400,2000,400,*,RIGHT,ALU1 +S 3000,3000,3000,3000,400,b,LEFT,CALU1 +S 4000,4000,4000,4000,400,a2,LEFT,CALU1 +S 3000,7000,3000,7000,400,a1,LEFT,CALU1 +S 1000,2000,1000,6000,400,*,DOWN,ALU1 +S 1000,2000,1000,6000,400,z,DOWN,CALU1 +S 3400,5100,3900,5100,200,*,RIGHT,POLY +S 3400,5100,3400,5500,200,*,DOWN,POLY +S 3000,4000,3000,6100,400,*,UP,ALU1 +S 3000,3900,4100,3900,400,*,RIGHT,ALU1 +S 3000,4000,4100,4000,400,*,RIGHT,ALU1 +S 3000,4000,3000,6000,400,a2,DOWN,CALU1 +S 2900,7100,4000,7100,400,*,RIGHT,ALU1 +S 4000,4800,4000,7000,400,*,UP,ALU1 +S 4000,5000,4000,7000,400,a1,UP,CALU1 +S 2900,7000,4000,7000,400,*,RIGHT,ALU1 +S 800,5700,800,7300,600,*,DOWN,PDIF +S 800,6900,800,9300,400,*,UP,ALU1 +S 1000,6000,2000,6000,600,*,RIGHT,ALU1 +S 2000,6000,2000,7100,400,*,UP,ALU1 +S 2000,6000,2000,7000,400,z,UP,CALU1 +S 1400,7500,1400,7900,200,*,DOWN,POLY +S 4000,7900,4000,9300,400,*,UP,ALU1 +S 2000,5700,2000,7300,1000,*,UP,PDIF +S 1400,5500,1400,7500,200,3,DOWN,PTRANS +S 2000,2900,3100,2900,400,*,RIGHT,ALU1 +S 2000,3000,2000,5100,400,*,DOWN,ALU1 +S 2000,3000,3100,3000,400,*,RIGHT,ALU1 +S 2000,3000,2000,5000,400,b,DOWN,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,5000,5000,10000,oai21_x1,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 3100,5700,3100,9200,400,n1,UP,PDIF +S 3400,5500,3400,9400,200,1,DOWN,PTRANS +S 2600,5500,2600,9400,200,2,DOWN,PTRANS +S 2200,5700,2200,9200,400,*,DOWN,PDIF +S 4000,5700,4000,9200,600,*,DOWN,PDIF +S 3400,9400,3400,9700,200,*,DOWN,POLY +S 2600,9400,2600,9700,200,*,DOWN,POLY +S 900,1900,900,3100,600,*,DOWN,ALU1 +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 1800,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 800,2200,CONT_DIF_N,* +V 800,3000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,n2 +V 4400,2200,CONT_DIF_N,n2 +V 4400,3000,CONT_DIF_N,n2 +V 800,7000,CONT_DIF_P,* +V 2000,6800,CONT_DIF_P,* +V 2000,6000,CONT_DIF_P,* +V 4000,9000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 3200,1000,CONT_DIF_N,* +V 4000,4900,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/oai21_x1.vbe b/pdks/symbolic/msxlib/cells/oai21_x1.vbe new file mode 100644 index 000000000..5ab344321 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai21_x1.vbe @@ -0,0 +1,38 @@ +ENTITY oai21_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a1 : NATURAL := 6; + CONSTANT cin_a2 : NATURAL := 6; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a1_z : NATURAL := 2170; + CONSTANT rdown_a2_z : NATURAL := 2170; + CONSTANT rdown_b_z : NATURAL := 2010; + CONSTANT rup_a1_z : NATURAL := 2980; + CONSTANT rup_a2_z : NATURAL := 2980; + CONSTANT rup_b_z : NATURAL := 2970; + CONSTANT tphl_b_z : NATURAL := 41; + CONSTANT tphl_a2_z : NATURAL := 45; + CONSTANT tplh_a1_z : NATURAL := 69; + CONSTANT tplh_b_z : NATURAL := 49; + CONSTANT tplh_a2_z : NATURAL := 60; + CONSTANT tphl_a1_z : NATURAL := 55; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai21_x1; + +ARCHITECTURE behaviour_data_flow OF oai21_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai21_x1" + SEVERITY WARNING; + z <= not (((a1 or a2) and b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/oai21_x2.ap b/pdks/symbolic/msxlib/cells/oai21_x2.ap new file mode 100644 index 000000000..3fbf73010 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai21_x2.ap @@ -0,0 +1,123 @@ +V ALLIANCE : 6 +H oai21_x2,P, 9/ 8/2014,100 +A 0,0,7000,10000 +R 6000,4000,ref_ref,a1_40 +R 6000,6000,ref_ref,a1_60 +R 2000,4000,ref_ref,b_40 +R 5000,4000,ref_ref,a1_40 +R 5000,7000,ref_ref,a2_70 +R 4000,8000,ref_ref,z_80 +R 4000,7000,ref_ref,z_70 +R 3000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 5000,6000,ref_ref,a2_60 +R 6000,5000,ref_ref,a1_50 +R 4000,5000,ref_ref,a2_50 +R 4000,4000,ref_ref,a1_40 +R 1000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 2000,5000,ref_ref,b_50 +R 1000,3000,ref_ref,z_30 +R 4000,6000,ref_ref,a2_60 +R 3000,4000,ref_ref,a1_40 +R 2000,6000,ref_ref,b_60 +R 3000,6000,ref_ref,b_60 +S 5100,700,5900,700,600,*,RIGHT,PTIE +S 5600,4800,5600,5600,200,*,DOWN,POLY +S 5000,4000,5000,4000,400,a1,LEFT,CALU1 +S 6100,4000,6100,6100,400,*,UP,ALU1 +S 2900,4000,6000,4000,400,*,RIGHT,ALU1 +S 6000,4000,6000,6000,400,a1,UP,CALU1 +S 6000,4000,6000,6100,400,*,UP,ALU1 +S 4000,4000,4000,4000,400,a1,LEFT,CALU1 +S 3000,4000,3000,4000,400,a1,LEFT,CALU1 +S 3000,6000,3000,6000,400,b,LEFT,CALU1 +S 4000,7000,4000,8000,400,z,UP,CALU1 +S 3000,7000,3000,7000,400,z,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 5600,9400,5600,9700,200,*,DOWN,POLY +S 4800,9400,4800,9700,200,*,DOWN,POLY +S 3600,9400,3600,9700,200,*,DOWN,POLY +S 2800,9400,2800,9700,200,*,DOWN,POLY +S 1600,9400,1600,9700,200,*,DOWN,POLY +S 1600,300,1600,700,200,*,UP,POLY +S 1600,5600,1600,9400,200,5,DOWN,PTRANS +S 1200,5800,1200,9200,400,*,UP,PDIF +S 2200,5800,2200,9200,600,*,DOWN,PDIF +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,5000,7000,5000,10000,oai21_x2,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 2200,7900,2200,9300,400,*,DOWN,ALU1 +S 6200,7900,6200,9300,400,*,DOWN,ALU1 +S 1000,6000,1000,6800,600,*,UP,PDIF +S 1000,7000,4000,7000,600,*,RIGHT,ALU1 +S 4100,6900,4100,8100,600,*,UP,ALU1 +S 4000,6000,5000,6000,600,*,RIGHT,ALU1 +S 4000,5000,4000,6000,400,a2,DOWN,CALU1 +S 4000,4900,4000,6000,400,*,UP,ALU1 +S 5000,6000,5000,7000,400,a2,UP,CALU1 +S 5000,6000,5000,7100,400,*,UP,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 3200,5800,3200,9200,600,n2,DOWN,PDIF +S 3600,5600,3600,9400,200,4,DOWN,PTRANS +S 2800,5600,2800,9400,200,3,DOWN,PTRANS +S 4800,5600,4800,9400,200,2,DOWN,PTRANS +S 4200,5800,4200,9200,1000,*,UP,PDIF +S 6200,5800,6200,9200,800,*,DOWN,PDIF +S 5600,5600,5600,9400,200,1,DOWN,PTRANS +S 5200,5800,5200,9200,600,n1,UP,PDIF +S 3600,5200,4800,5200,200,*,RIGHT,POLY +S 2800,300,2800,700,200,*,UP,POLY +S 1200,800,1200,3600,400,*,UP,NDIF +S 1000,2600,1000,3400,600,*,UP,NDIF +S 2200,800,2200,3600,600,*,UP,NDIF +S 3400,800,3400,3600,600,*,UP,NDIF +S 5200,2200,5200,3800,200,6,UP,NTRANS +S 4600,2400,4600,3600,600,*,UP,NDIF +S 4000,1800,4000,2200,200,*,UP,POLY +S 5200,1800,5200,2200,200,*,UP,POLY +S 5800,700,5800,3100,400,*,DOWN,ALU1 +S 5900,2400,5900,3600,600,*,UP,NDIF +S 2000,6000,3100,6000,400,*,RIGHT,ALU1 +S 2000,6100,3100,6100,400,*,RIGHT,ALU1 +S 2000,4000,2000,6000,400,b,DOWN,CALU1 +S 2000,3900,2000,6000,400,*,DOWN,ALU1 +S 3000,4000,3000,4500,600,*,UP,ALU1 +S 2200,3000,4700,3000,400,*,RIGHT,ALU1 +S 2200,2000,2200,3000,600,*,DOWN,ALU1 +S 4000,4200,5200,4200,200,*,LEFT,POLY +S 3400,700,3400,2100,400,*,UP,ALU1 +S 4100,4200,4100,4800,400,*,DOWN,POLY +S 4000,2200,4000,3800,200,7,UP,NTRANS +S 2800,600,2800,3800,200,8,UP,NTRANS +S 1600,600,1600,3800,200,9,UP,NTRANS +S 1600,3800,1600,5300,200,*,UP,POLY +S 2800,4400,2800,5600,200,*,UP,POLY +S 1000,2600,1000,7000,400,*,DOWN,ALU1 +V 6000,700,CONT_BODY_P,* +V 5000,700,CONT_BODY_P,* +V 6000,5000,CONT_POLY,* +V 4200,8000,CONT_DIF_P,* +V 2200,2000,CONT_DIF_N,n3 +V 2200,9000,CONT_DIF_P,* +V 6200,9000,CONT_DIF_P,* +V 2200,8000,CONT_DIF_P,* +V 6200,8000,CONT_DIF_P,* +V 1000,5900,CONT_DIF_P,* +V 1000,6700,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 4000,5000,CONT_POLY,* +V 3400,1000,CONT_DIF_N,* +V 1000,3500,CONT_DIF_N,* +V 1000,2700,CONT_DIF_N,* +V 4600,3000,CONT_DIF_N,n3 +V 5800,3000,CONT_DIF_N,* +V 3000,4400,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 2200,3000,CONT_DIF_N,n3 +V 3400,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/oai21_x2.vbe b/pdks/symbolic/msxlib/cells/oai21_x2.vbe new file mode 100644 index 000000000..a55d6ecf2 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai21_x2.vbe @@ -0,0 +1,38 @@ +ENTITY oai21_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_a1 : NATURAL := 12; + CONSTANT cin_a2 : NATURAL := 11; + CONSTANT cin_b : NATURAL := 8; + CONSTANT rdown_a1_z : NATURAL := 1150; + CONSTANT rdown_a2_z : NATURAL := 1150; + CONSTANT rdown_b_z : NATURAL := 1060; + CONSTANT rup_a1_z : NATURAL := 1530; + CONSTANT rup_a2_z : NATURAL := 1530; + CONSTANT rup_b_z : NATURAL := 1560; + CONSTANT tphl_b_z : NATURAL := 41; + CONSTANT tphl_a2_z : NATURAL := 44; + CONSTANT tplh_a1_z : NATURAL := 66; + CONSTANT tplh_b_z : NATURAL := 48; + CONSTANT tplh_a2_z : NATURAL := 57; + CONSTANT tphl_a1_z : NATURAL := 54; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai21_x2; + +ARCHITECTURE behaviour_data_flow OF oai21_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai21_x2" + SEVERITY WARNING; + z <= not (((a1 or a2) and b)) after 900 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/oai22_x05.ap b/pdks/symbolic/msxlib/cells/oai22_x05.ap new file mode 100644 index 000000000..81b196c9c --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai22_x05.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H oai22_x05,P, 9/ 8/2014,100 +A 0,0,6000,10000 +R 5000,4000,ref_ref,a2_40 +R 2000,4000,ref_ref,z_40 +R 3000,4000,ref_ref,b2_40 +R 4000,4000,ref_ref,b2_40 +R 2000,5000,ref_ref,b1_50 +R 2000,6000,ref_ref,b1_60 +R 3000,7000,ref_ref,b1_70 +R 3000,5000,ref_ref,b2_50 +R 4000,5000,ref_ref,a2_50 +R 5000,6000,ref_ref,a1_60 +R 4000,7000,ref_ref,a1_70 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +R 1000,7000,ref_ref,z_70 +R 3000,8000,ref_ref,z_80 +R 2000,8000,ref_ref,z_80 +R 2000,3000,ref_ref,z_30 +R 5000,7000,ref_ref,a1_70 +R 4000,8000,ref_ref,a1_80 +R 4000,6000,ref_ref,a2_60 +R 5000,5000,ref_ref,a2_50 +R 1000,8000,ref_ref,z_80 +R 2000,7000,ref_ref,b1_70 +R 3000,6000,ref_ref,b2_60 +S 4100,9300,4900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 5000,4000,5000,5000,400,a2,DOWN,CALU1 +S 3000,4000,4000,4000,600,*,RIGHT,ALU1 +S 1000,4000,2000,4000,600,*,RIGHT,ALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,5000,6000,5000,10000,oai22_x05,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 5200,7900,5200,9300,400,*,UP,ALU1 +S 4600,6500,4600,8500,200,1,DOWN,PTRANS +S 3800,6500,3800,8500,200,2,DOWN,PTRANS +S 4200,6700,4200,8300,600,n1,UP,PDIF +S 3200,6700,3200,8300,1000,*,UP,PDIF +S 2600,6500,2600,8500,200,4,DOWN,PTRANS +S 1800,6500,1800,8500,200,3,DOWN,PTRANS +S 2200,6700,2200,8300,600,n2,UP,PDIF +S 4000,7000,4000,8000,400,a1,UP,CALU1 +S 4000,7000,4000,8100,400,*,UP,ALU1 +S 4000,7000,5000,7000,600,*,RIGHT,ALU1 +S 5000,6000,5000,7000,400,a1,UP,CALU1 +S 5000,5800,5000,7000,400,*,UP,ALU1 +S 5000,3900,5000,5000,400,*,DOWN,ALU1 +S 4000,5000,5000,5000,400,*,RIGHT,ALU1 +S 5100,3900,5100,5000,400,*,DOWN,ALU1 +S 4000,5000,4000,6000,400,a2,UP,CALU1 +S 4000,5000,4000,6100,400,*,UP,ALU1 +S 4000,4900,5000,4900,400,*,RIGHT,ALU1 +S 4600,6000,4600,6500,200,*,DOWN,POLY +S 5200,2900,5200,3400,400,*,DOWN,NDIF +S 4800,2700,4800,3600,200,5,UP,NTRANS +S 3000,2900,3000,3400,1000,*,UP,NDIF +S 3600,2700,3600,3600,200,6,UP,NTRANS +S 1800,2900,1800,3400,1000,*,UP,NDIF +S 2400,2700,2400,3600,200,8,UP,NTRANS +S 1200,2700,1200,3600,200,7,UP,NTRANS +S 800,2900,800,3400,400,*,DOWN,NDIF +S 1800,5300,1800,6500,200,*,DOWN,POLY +S 4800,3600,4800,5600,200,*,UP,POLY +S 3800,4000,3800,6500,200,*,DOWN,POLY +S 3600,3600,3600,4100,200,*,UP,POLY +S 2400,3600,2400,4000,200,*,UP,POLY +S 2400,4000,2800,4000,200,*,RIGHT,POLY +S 1200,3600,1200,4800,200,*,UP,POLY +S 1200,4800,1800,4800,200,*,RIGHT,POLY +S 2600,8500,2600,8900,200,*,DOWN,POLY +S 2000,3000,2000,4000,400,z,UP,CALU1 +S 1900,2900,1900,4000,600,*,UP,ALU1 +S 600,2000,600,3100,400,*,UP,ALU1 +S 4800,2300,4800,2700,200,*,UP,POLY +S 3600,2300,3600,2700,200,*,UP,POLY +S 2400,2300,2400,2700,200,*,UP,POLY +S 1200,2300,1200,2700,200,*,UP,POLY +S 1800,8500,1800,8900,200,*,DOWN,POLY +S 1000,8000,3200,8000,600,*,RIGHT,ALU1 +S 1000,4000,1000,8000,400,z,DOWN,CALU1 +S 1000,4400,1000,8000,400,*,DOWN,ALU1 +S 2000,7000,3000,7000,600,*,RIGHT,ALU1 +S 2000,4900,2000,7000,400,*,UP,ALU1 +S 2000,5000,2000,7000,400,b1,UP,CALU1 +S 2800,4000,2800,6100,200,*,DOWN,POLY +S 2600,6000,2600,6500,200,*,DOWN,POLY +S 2000,8000,2000,8000,400,z,LEFT,CALU1 +S 3000,8000,3000,8000,400,z,LEFT,CALU1 +S 3000,7000,3000,7000,400,b1,LEFT,CALU1 +S 3000,4000,3000,6100,400,*,DOWN,ALU1 +S 3000,4000,3000,6000,400,b2,DOWN,CALU1 +S 4000,4000,4000,4000,400,b2,LEFT,CALU1 +S 3800,8500,3800,8800,200,*,DOWN,POLY +S 4600,8500,4600,8800,200,*,DOWN,POLY +S 600,2000,2900,2000,400,*,RIGHT,ALU1 +S 2900,2000,2900,3000,400,*,DOWN,ALU1 +S 2900,3000,5500,3000,400,*,RIGHT,ALU1 +S 4200,1800,4200,3400,600,*,UP,NDIF +S 4200,700,4200,2100,400,*,DOWN,ALU1 +S 1200,6700,1200,9100,600,*,DOWN,PDIF +S 1100,6700,1100,9100,600,*,DOWN,PDIF +S 5300,6700,5300,8300,600,*,DOWN,PDIF +V 4000,9300,CONT_BODY_N,* +V 5000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 1800,3000,CONT_DIF_N,* +V 3200,8000,CONT_DIF_P,* +V 5200,8000,CONT_DIF_P,* +V 5000,5900,CONT_POLY,* +V 4000,5000,CONT_POLY,* +V 5400,3000,CONT_DIF_N,n3 +V 3000,3000,CONT_DIF_N,n3 +V 600,3000,CONT_DIF_N,n3 +V 3000,5000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 1200,9000,CONT_DIF_P,* +V 4200,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/oai22_x05.vbe b/pdks/symbolic/msxlib/cells/oai22_x05.vbe new file mode 100644 index 000000000..0dfc79ed7 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai22_x05.vbe @@ -0,0 +1,44 @@ +ENTITY oai22_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_b1 : NATURAL := 4; + CONSTANT cin_b2 : NATURAL := 4; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_a2 : NATURAL := 4; + CONSTANT rdown_b1_z : NATURAL := 3810; + CONSTANT rdown_b2_z : NATURAL := 3800; + CONSTANT rdown_a1_z : NATURAL := 3760; + CONSTANT rdown_a2_z : NATURAL := 3760; + CONSTANT rup_b1_z : NATURAL := 5850; + CONSTANT rup_b2_z : NATURAL := 5830; + CONSTANT rup_a1_z : NATURAL := 5840; + CONSTANT rup_a2_z : NATURAL := 5840; + CONSTANT tphl_a2_z : NATURAL := 58; + CONSTANT tphl_b2_z : NATURAL := 49; + CONSTANT tplh_b1_z : NATURAL := 68; + CONSTANT tphl_a1_z : NATURAL := 67; + CONSTANT tplh_b2_z : NATURAL := 57; + CONSTANT tphl_b1_z : NATURAL := 59; + CONSTANT tplh_a1_z : NATURAL := 87; + CONSTANT tplh_a2_z : NATURAL := 77; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai22_x05; + +ARCHITECTURE behaviour_data_flow OF oai22_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai22_x05" + SEVERITY WARNING; + z <= not (((b1 or b2) and (a1 or a2))) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/oai22_x1.ap b/pdks/symbolic/msxlib/cells/oai22_x1.ap new file mode 100644 index 000000000..e80a67875 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai22_x1.ap @@ -0,0 +1,121 @@ +V ALLIANCE : 6 +H oai22_x1,P, 9/ 8/2014,100 +A 0,0,6000,10000 +R 1000,3000,ref_ref,z_30 +R 3000,3000,ref_ref,b2_30 +R 3000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 5000,4000,ref_ref,a2_40 +R 5000,7000,ref_ref,a1_70 +R 2000,4000,ref_ref,b1_40 +R 2000,5000,ref_ref,b1_50 +R 2000,6000,ref_ref,b1_60 +R 4000,3000,ref_ref,b2_30 +R 3000,4000,ref_ref,b2_40 +R 3000,5000,ref_ref,b2_50 +R 4000,4000,ref_ref,a2_40 +R 4000,5000,ref_ref,a2_50 +R 5000,5000,ref_ref,a1_50 +R 5000,6000,ref_ref,a1_60 +R 4000,7000,ref_ref,a1_70 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +R 1000,7000,ref_ref,z_70 +R 3000,8000,ref_ref,z_80 +R 2000,3000,ref_ref,z_30 +R 4000,6000,ref_ref,a2_60 +R 3000,6000,ref_ref,b1_60 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 1000,2900,2100,2900,400,*,RIGHT,ALU1 +S 1000,7000,3200,7000,600,*,RIGHT,ALU1 +S 4000,7000,5000,7000,600,*,RIGHT,ALU1 +S 1000,3000,2100,3000,400,*,RIGHT,ALU1 +S 1200,4700,1500,4700,200,*,RIGHT,POLY +S 1800,4900,2000,4900,600,*,RIGHT,ALU1 +S 2000,3900,2000,6000,400,*,UP,ALU1 +S 3000,3000,3000,5100,400,*,DOWN,ALU1 +S 3000,3000,3000,5000,400,b2,DOWN,CALU1 +S 3000,2900,4100,2900,400,*,RIGHT,ALU1 +S 2600,3800,2600,5500,200,*,DOWN,POLY +S 3600,3400,3600,3900,200,*,UP,POLY +S 3000,3000,4100,3000,400,*,RIGHT,ALU1 +S 1200,7900,1200,9300,400,*,UP,ALU1 +S 3000,7000,3000,8000,400,z,UP,CALU1 +S 3100,7000,3100,8100,600,*,UP,ALU1 +S 1000,3000,1000,7000,400,*,DOWN,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 2000,6100,3100,6100,400,*,RIGHT,ALU1 +S 2000,4000,2000,6000,400,b1,UP,CALU1 +S 2000,6000,3100,6000,400,*,RIGHT,ALU1 +S 3800,4200,3800,5500,200,*,DOWN,POLY +S 4800,3400,4800,4700,200,*,UP,POLY +S 5000,4800,5000,7000,400,*,UP,ALU1 +S 5000,5000,5000,7000,400,a1,UP,CALU1 +S 5200,7900,5200,9300,400,*,UP,ALU1 +S 4600,9400,4600,9700,200,*,DOWN,POLY +S 3800,9400,3800,9700,200,*,DOWN,POLY +S 2600,9400,2600,9700,200,*,DOWN,POLY +S 1800,9400,1800,9700,200,*,DOWN,POLY +S 5300,5700,5300,9200,600,*,DOWN,PDIF +S 4200,5700,4200,9200,600,n1,UP,PDIF +S 4600,5500,4600,9400,200,1,DOWN,PTRANS +S 3800,5500,3800,9400,200,2,DOWN,PTRANS +S 3200,5700,3200,9200,1000,*,UP,PDIF +S 2200,5700,2200,9200,600,n2,UP,PDIF +S 2600,5500,2600,9400,200,4,DOWN,PTRANS +S 1800,5500,1800,9400,200,3,DOWN,PTRANS +S 1100,5700,1100,9200,600,*,DOWN,PDIF +S 2400,1700,2400,3400,200,8,UP,NTRANS +S 1200,1700,1200,3400,200,7,UP,NTRANS +S 3600,1700,3600,3400,200,6,UP,NTRANS +S 4800,1700,4800,3400,200,5,UP,NTRANS +S 4200,900,4200,3200,600,*,UP,NDIF +S 5200,1900,5200,3200,400,*,DOWN,NDIF +S 800,1900,800,3200,400,*,DOWN,NDIF +S 500,2000,5500,2000,400,*,RIGHT,ALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,5000,6000,5000,10000,oai22_x1,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 1200,1300,1200,1700,200,*,UP,POLY +S 2400,1300,2400,1700,200,*,UP,POLY +S 3600,1300,3600,1700,200,*,UP,POLY +S 4800,1300,4800,1700,200,*,UP,POLY +S 1800,1900,1800,3200,1000,*,UP,NDIF +S 3000,1900,3000,3200,1000,*,UP,NDIF +S 4000,4000,4000,6100,400,*,UP,ALU1 +S 3900,4000,3900,6100,400,*,UP,ALU1 +S 4000,4000,4000,6000,400,a2,DOWN,CALU1 +S 4000,4000,5100,4000,400,*,RIGHT,ALU1 +S 5000,4000,5000,4000,400,a2,LEFT,CALU1 +S 5400,2100,5400,2700,600,*,UP,NDIF +S 5400,2000,5400,2800,600,*,UP,ALU1 +S 4000,7000,4000,7000,400,a1,LEFT,CALU1 +S 4000,3000,4000,3000,400,b2,LEFT,CALU1 +S 3000,6000,3000,6000,400,b1,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 2000,3000,2000,3000,400,z,LEFT,CALU1 +S 2400,3400,2400,3900,200,*,UP,POLY +S 4600,5000,4600,5500,200,*,DOWN,POLY +S 1200,3400,1200,4700,200,*,UP,POLY +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 3200,7000,CONT_DIF_P,* +V 3000,4900,CONT_POLY,* +V 1200,8000,CONT_DIF_P,* +V 5200,8000,CONT_DIF_P,* +V 1800,4900,CONT_POLY,* +V 5000,4900,CONT_POLY,* +V 5200,9000,CONT_DIF_P,* +V 1200,9000,CONT_DIF_P,* +V 4200,1000,CONT_DIF_N,* +V 600,2000,CONT_DIF_N,n3 +V 3000,2000,CONT_DIF_N,n3 +V 5400,2000,CONT_DIF_N,n3 +V 1800,3000,CONT_DIF_N,* +V 3200,8000,CONT_DIF_P,* +V 5400,2800,CONT_DIF_N,n3 +V 4000,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/oai22_x1.vbe b/pdks/symbolic/msxlib/cells/oai22_x1.vbe new file mode 100644 index 000000000..1975abca2 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY oai22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_b1 : NATURAL := 7; + CONSTANT cin_b2 : NATURAL := 6; + CONSTANT cin_a1 : NATURAL := 6; + CONSTANT cin_a2 : NATURAL := 6; + CONSTANT rdown_b1_z : NATURAL := 2010; + CONSTANT rdown_b2_z : NATURAL := 2010; + CONSTANT rdown_a1_z : NATURAL := 1990; + CONSTANT rdown_a2_z : NATURAL := 1990; + CONSTANT rup_b1_z : NATURAL := 2990; + CONSTANT rup_b2_z : NATURAL := 2990; + CONSTANT rup_a1_z : NATURAL := 2990; + CONSTANT rup_a2_z : NATURAL := 2990; + CONSTANT tphl_a2_z : NATURAL := 55; + CONSTANT tphl_b2_z : NATURAL := 48; + CONSTANT tplh_b1_z : NATURAL := 63; + CONSTANT tphl_a1_z : NATURAL := 64; + CONSTANT tplh_b2_z : NATURAL := 53; + CONSTANT tphl_b1_z : NATURAL := 57; + CONSTANT tplh_a1_z : NATURAL := 80; + CONSTANT tplh_a2_z : NATURAL := 70; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai22_x1; + +ARCHITECTURE behaviour_data_flow OF oai22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai22_x1" + SEVERITY WARNING; + z <= not (((b1 or b2) and (a1 or a2))) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/oai22_x2.ap b/pdks/symbolic/msxlib/cells/oai22_x2.ap new file mode 100644 index 000000000..e51c32a07 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai22_x2.ap @@ -0,0 +1,167 @@ +V ALLIANCE : 6 +H oai22_x2,P, 9/ 8/2014,100 +A 0,0,10000,10000 +R 6000,4000,ref_ref,a2_40 +R 8000,4000,ref_ref,a1_40 +R 8000,7000,ref_ref,a2_70 +R 8000,6000,ref_ref,a2_60 +R 4000,4000,ref_ref,b2_40 +R 3000,5000,ref_ref,b2_50 +R 3000,6000,ref_ref,b1_60 +R 4000,5000,ref_ref,b1_50 +R 2000,5000,ref_ref,b1_50 +R 2000,4000,ref_ref,b1_40 +R 9000,4000,ref_ref,a1_40 +R 9000,5000,ref_ref,a1_50 +R 6000,5000,ref_ref,a1_50 +R 8000,5000,ref_ref,a2_50 +R 7000,4000,ref_ref,a2_40 +R 4000,3000,ref_ref,z_30 +R 3000,3000,ref_ref,z_30 +R 2000,3000,ref_ref,z_30 +R 6000,7000,ref_ref,z_70 +R 3000,8000,ref_ref,z_80 +R 3000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 4000,7000,ref_ref,z_70 +R 5000,7000,ref_ref,z_70 +R 5000,3000,ref_ref,b2_30 +R 7000,7000,ref_ref,z_70 +R 1000,7000,ref_ref,z_70 +R 1000,3000,ref_ref,z_30 +R 2000,6000,ref_ref,b1_60 +R 4000,6000,ref_ref,b1_60 +R 3000,4000,ref_ref,b2_40 +R 5000,4000,ref_ref,b2_40 +R 7000,5000,ref_ref,a2_50 +R 9000,6000,ref_ref,a1_60 +R 7000,6000,ref_ref,z_60 +S 8500,700,9300,700,600,*,RIGHT,PTIE +S 6000,7000,6000,7000,400,z,LEFT,CALU1 +S 5000,7000,5000,7000,400,z,LEFT,CALU1 +S 4000,7000,4000,7000,400,z,LEFT,CALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 4000,3000,4000,3000,400,z,LEFT,CALU1 +S 3000,3000,3000,3000,400,z,LEFT,CALU1 +S 2000,3000,2000,3000,400,z,LEFT,CALU1 +S 3000,6000,3000,6000,400,b1,LEFT,CALU1 +S 4000,4000,4000,4000,400,b2,LEFT,CALU1 +S 7400,2300,7400,2900,600,*,UP,NDIF +S 7400,2000,7400,3100,400,*,UP,ALU1 +S 2500,2000,7400,2000,400,*,RIGHT,ALU1 +S 7000,4000,7000,4000,400,a1,LEFT,CALU1 +S 8000,4000,8000,4000,400,a1,LEFT,CALU1 +S 7000,5000,7000,5000,400,a2,LEFT,CALU1 +S 8000,5000,8000,7100,400,*,DOWN,ALU1 +S 6000,4000,6000,5100,600,*,UP,ALU1 +S 6000,4000,6000,5000,400,a1,UP,CALU1 +S 8000,5000,8000,7000,400,a2,DOWN,CALU1 +S 6000,4000,9000,4000,400,*,RIGHT,ALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 0,5000,10000,5000,10000,oai22_x2,LEFT,TALU8 +S 0,2200,10000,2200,5200,*,LEFT,PWELL +S 0,7600,10000,7600,5600,*,LEFT,NWELL +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 2000,5800,2000,9100,600,n2a,UP,PDIF +S 4000,5800,4000,9100,600,n2b,UP,PDIF +S 6000,5800,6000,9100,600,n1a,UP,PDIF +S 8000,5800,8000,9100,600,n1b,UP,PDIF +S 3200,600,3200,3900,200,8,UP,NTRANS +S 4400,600,4400,3900,200,7,UP,NTRANS +S 6800,600,6800,3900,200,6,UP,NTRANS +S 5600,600,5600,3900,200,5,UP,NTRANS +S 7000,5800,7000,9100,1000,*,UP,PDIF +S 5000,5800,5000,9100,1000,*,UP,PDIF +S 3000,5800,3000,9100,1000,*,UP,PDIF +S 900,5800,900,9100,600,*,DOWN,PDIF +S 9100,5800,9100,9100,600,*,DOWN,PDIF +S 3000,4000,3000,5000,400,b2,UP,CALU1 +S 3200,300,3200,600,200,*,UP,POLY +S 4400,300,4400,600,200,*,UP,POLY +S 5600,300,5600,600,200,*,UP,POLY +S 6800,300,6800,600,200,*,UP,POLY +S 7200,800,7200,3700,400,*,UP,NDIF +S 6200,800,6200,3700,1000,*,UP,NDIF +S 5000,800,5000,3700,1000,*,UP,NDIF +S 3800,800,3800,3700,1000,*,UP,NDIF +S 2800,800,2800,3700,400,*,UP,NDIF +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 1000,3000,1000,7000,400,*,DOWN,ALU1 +S 5500,5000,6000,5000,600,*,LEFT,ALU1 +S 2000,6000,4000,6000,400,*,RIGHT,ALU1 +S 2400,5200,3600,5200,200,*,RIGHT,POLY +S 8400,5200,8600,5200,200,*,RIGHT,POLY +S 6400,5200,7600,5200,200,*,RIGHT,POLY +S 8400,5600,8400,9300,200,1b,DOWN,PTRANS +S 7600,5600,7600,9300,200,2b,DOWN,PTRANS +S 6400,5600,6400,9300,200,2a,DOWN,PTRANS +S 5600,5600,5600,9300,200,1a,DOWN,PTRANS +S 4400,5600,4400,9300,200,3b,DOWN,PTRANS +S 2400,5600,2400,9300,200,4a,DOWN,PTRANS +S 1600,5600,1600,9300,200,3a,DOWN,PTRANS +S 3600,5600,3600,9300,200,4b,DOWN,PTRANS +S 3000,7000,3000,8100,400,*,UP,ALU1 +S 3000,7000,3000,8000,400,z,UP,CALU1 +S 900,3000,900,7000,400,*,DOWN,ALU1 +S 1000,7000,7000,7000,400,*,RIGHT,ALU1 +S 1000,3000,4100,3000,400,*,RIGHT,ALU1 +S 2000,3900,2000,6000,400,*,DOWN,ALU1 +S 2000,4000,2000,6000,400,b1,UP,CALU1 +S 4000,5400,4000,6000,400,*,DOWN,ALU1 +S 4000,5000,4000,6000,400,b1,UP,CALU1 +S 2000,6100,4000,6100,400,*,RIGHT,ALU1 +S 4000,5000,4500,5000,600,*,RIGHT,ALU1 +S 3000,4000,5000,4000,400,*,RIGHT,ALU1 +S 3000,4000,3000,5000,600,*,DOWN,ALU1 +S 1600,4500,1600,5600,200,*,DOWN,POLY +S 5000,3000,5000,4000,400,b2,DOWN,CALU1 +S 5000,3000,5000,4000,600,*,DOWN,ALU1 +S 9000,4000,9000,6000,400,a1,UP,CALU1 +S 7000,5000,8000,5000,600,*,RIGHT,ALU1 +S 8400,9300,8400,9700,200,*,DOWN,POLY +S 7600,9300,7600,9700,200,*,DOWN,POLY +S 6400,9300,6400,9700,200,*,DOWN,POLY +S 5600,9300,5600,9700,200,*,DOWN,POLY +S 4400,9300,4400,9700,200,*,DOWN,POLY +S 3600,9300,3600,9700,200,*,DOWN,POLY +S 2400,9300,2400,9700,200,*,DOWN,POLY +S 1600,9300,1600,9700,200,*,DOWN,POLY +S 3200,3900,3200,4600,200,*,UP,POLY +S 4400,3900,4400,4600,200,*,UP,POLY +S 5600,3900,5600,4600,200,*,UP,POLY +S 6800,3900,6800,5200,200,*,UP,POLY +S 9000,4000,9000,6000,600,*,UP,ALU1 +S 7000,6000,7000,7000,400,z,UP,CALU1 +S 7000,6000,7000,7000,600,*,UP,ALU1 +S 1000,7900,1000,9300,400,*,UP,ALU1 +S 5000,7900,5000,9300,400,*,UP,ALU1 +S 9000,6900,9000,9300,400,*,UP,ALU1 +V 9300,700,CONT_BODY_P,* +V 8400,700,CONT_BODY_P,* +V 7400,2200,CONT_DIF_N,n3 +V 7400,3000,CONT_DIF_N,n3 +V 7000,5000,CONT_POLY,* +V 6200,1000,CONT_DIF_N,* +V 5000,2000,CONT_DIF_N,n3 +V 2600,2000,CONT_DIF_N,n3 +V 3800,3000,CONT_DIF_N,* +V 3000,5000,CONT_POLY,* +V 9000,5000,CONT_POLY,* +V 5600,5000,CONT_POLY,* +V 1000,8000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 1000,9000,CONT_DIF_P,* +V 5000,9000,CONT_DIF_P,* +V 2000,4400,CONT_POLY,* +V 9000,9000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 4400,5000,CONT_POLY,* +V 7000,6000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/oai22_x2.vbe b/pdks/symbolic/msxlib/cells/oai22_x2.vbe new file mode 100644 index 000000000..4e3796bf0 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oai22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY oai22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 10000; + CONSTANT cin_b1 : NATURAL := 12; + CONSTANT cin_b2 : NATURAL := 11; + CONSTANT cin_a1 : NATURAL := 12; + CONSTANT cin_a2 : NATURAL := 11; + CONSTANT rdown_b1_z : NATURAL := 1040; + CONSTANT rdown_b2_z : NATURAL := 1030; + CONSTANT rdown_a1_z : NATURAL := 1020; + CONSTANT rdown_a2_z : NATURAL := 1020; + CONSTANT rup_b1_z : NATURAL := 1580; + CONSTANT rup_b2_z : NATURAL := 1570; + CONSTANT rup_a1_z : NATURAL := 1570; + CONSTANT rup_a2_z : NATURAL := 1570; + CONSTANT tphl_a2_z : NATURAL := 53; + CONSTANT tphl_b2_z : NATURAL := 47; + CONSTANT tplh_b1_z : NATURAL := 62; + CONSTANT tphl_a1_z : NATURAL := 62; + CONSTANT tplh_b2_z : NATURAL := 52; + CONSTANT tphl_b1_z : NATURAL := 56; + CONSTANT tplh_a1_z : NATURAL := 78; + CONSTANT tplh_a2_z : NATURAL := 69; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai22_x2; + +ARCHITECTURE behaviour_data_flow OF oai22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai22_x2" + SEVERITY WARNING; + z <= not (((b1 or b2) and (a1 or a2))) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/oan21_x1.ap b/pdks/symbolic/msxlib/cells/oan21_x1.ap new file mode 100644 index 000000000..ae856ff3f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oan21_x1.ap @@ -0,0 +1,117 @@ +V ALLIANCE : 6 +H oan21_x1,P, 9/ 8/2014,100 +A 0,0,7000,10000 +R 5000,6000,ref_ref,a2_60 +R 6000,5000,ref_ref,a1_50 +R 5000,5000,ref_ref,a2_50 +R 4000,5000,ref_ref,b_50 +R 6000,6000,ref_ref,a1_60 +R 6000,7000,ref_ref,a1_70 +R 5000,7000,ref_ref,a1_70 +R 4000,3000,ref_ref,b_30 +R 5000,3000,ref_ref,b_30 +R 4000,4000,ref_ref,b_40 +R 6000,4000,ref_ref,a2_40 +R 5000,4000,ref_ref,a2_40 +R 1000,6000,ref_ref,z_60 +R 2000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,z_50 +R 2000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 6000,7900,6000,9300,400,*,UP,ALU1 +S 4000,2900,5100,2900,400,*,RIGHT,ALU1 +S 4000,3000,4000,5100,400,*,DOWN,ALU1 +S 4000,3000,5100,3000,400,*,RIGHT,ALU1 +S 4000,3000,4000,5000,400,b,DOWN,CALU1 +S 5000,4000,5000,6000,400,a2,DOWN,CALU1 +S 4900,7100,6000,7100,400,*,RIGHT,ALU1 +S 6000,4800,6000,7000,400,*,UP,ALU1 +S 6000,5000,6000,7000,400,a1,UP,CALU1 +S 4900,7000,6000,7000,400,*,RIGHT,ALU1 +S 2800,6900,2800,9300,400,*,UP,ALU1 +S 5000,3000,5000,3000,400,b,LEFT,CALU1 +S 6000,4000,6000,4000,400,a2,LEFT,CALU1 +S 5000,7000,5000,7000,400,a1,LEFT,CALU1 +S 5000,4000,5000,6100,400,*,UP,ALU1 +S 5000,3900,6100,3900,400,*,RIGHT,ALU1 +S 5000,4000,6100,4000,400,*,RIGHT,ALU1 +S 5400,5100,5900,5100,200,*,RIGHT,POLY +S 5400,5100,5400,5500,200,*,DOWN,POLY +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,7000,5000,10000,oan21_x1,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 4600,3800,4600,5500,200,*,UP,POLY +S 600,700,600,3100,400,*,DOWN,ALU1 +S 1600,6100,1600,6700,600,*,DOWN,PDIF +S 1000,6000,2000,6000,600,*,LEFT,ALU1 +S 1600,5900,1600,6900,400,*,DOWN,ALU1 +S 3400,4700,3400,5500,200,*,UP,POLY +S 3900,4800,3900,5100,600,*,DOWN,ALU1 +S 2800,3900,3000,3900,600,*,RIGHT,ALU1 +S 2000,3000,2000,6000,400,z,UP,CALU1 +S 1000,6000,1000,6000,400,z,LEFT,CALU1 +S 5400,8300,5400,8700,200,*,DOWN,POLY +S 4600,8300,4600,8700,200,*,DOWN,POLY +S 5100,5900,5100,8100,400,n1,UP,PDIF +S 5400,5700,5400,8300,200,1,DOWN,PTRANS +S 4600,5700,4600,8300,200,2,DOWN,PTRANS +S 6000,5900,6000,8100,600,*,DOWN,PDIF +S 4200,5900,4200,8100,400,*,DOWN,PDIF +S 4000,5900,4000,6900,1000,*,UP,PDIF +S 3400,5700,3400,7100,200,3,DOWN,PTRANS +S 4000,6000,4000,6900,400,*,UP,ALU1 +S 3000,5900,4000,5900,400,*,RIGHT,ALU1 +S 3400,7100,3400,7500,200,*,DOWN,POLY +S 4200,1900,4200,2700,600,*,DOWN,NDIF +S 4800,1700,4800,2900,200,5,UP,NTRANS +S 5800,1700,5800,2900,200,4,UP,NTRANS +S 3200,1900,3200,2700,400,*,UP,NDIF +S 3600,1700,3600,2900,200,6,UP,NTRANS +S 3000,2500,3000,5900,400,*,DOWN,ALU1 +S 4100,2000,6500,2000,400,*,RIGHT,ALU1 +S 6200,1900,6200,2700,400,*,UP,NDIF +S 5800,2900,5800,4800,200,*,UP,POLY +S 4800,2900,4800,4000,200,*,UP,POLY +S 3600,2900,3600,4800,200,*,UP,POLY +S 3600,1300,3600,1700,200,*,UP,POLY +S 4800,1300,4800,1700,200,*,UP,POLY +S 5800,1300,5800,1700,200,*,UP,POLY +S 5300,600,5300,2700,400,*,UP,NDIF +S 2200,5700,2200,7700,200,2,DOWN,PTRANS +S 2800,5900,2800,7500,600,*,DOWN,PDIF +S 1800,5900,1800,7500,400,*,UP,PDIF +S 2200,7700,2200,8100,200,*,DOWN,POLY +S 1200,2300,1200,3300,200,6,UP,NTRANS +S 1600,2500,1600,3100,400,*,UP,NDIF +S 1200,1900,1200,2300,200,*,UP,POLY +S 600,2500,600,3100,600,*,UP,NDIF +S 1200,3700,2800,3700,200,*,LEFT,POLY +S 2200,3700,2200,5500,200,*,DOWN,POLY +S 2200,3900,2800,3900,600,*,LEFT,POLY +S 2000,2900,2000,6000,400,*,UP,ALU1 +S 1900,2900,1900,3400,600,*,UP,ALU1 +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 5000,4000,CONT_POLY,* +V 6000,4900,CONT_POLY,* +V 2800,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 4200,2000,CONT_DIF_N,n2 +V 600,3000,CONT_DIF_N,* +V 1600,6000,CONT_DIF_P,* +V 1600,6800,CONT_DIF_P,* +V 3800,4900,CONT_POLY,* +V 2800,3900,CONT_POLY,zn +V 4000,6000,CONT_DIF_P,zn +V 4000,6800,CONT_DIF_P,zn +V 3000,2600,CONT_DIF_N,zn +V 6400,2000,CONT_DIF_N,n2 +V 5400,700,CONT_DIF_N,* +V 1800,3000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/oan21_x1.vbe b/pdks/symbolic/msxlib/cells/oan21_x1.vbe new file mode 100644 index 000000000..543780ba5 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oan21_x1.vbe @@ -0,0 +1,38 @@ +ENTITY oan21_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a1_z : NATURAL := 2310; + CONSTANT rdown_a2_z : NATURAL := 2310; + CONSTANT rdown_b_z : NATURAL := 2300; + CONSTANT rup_a1_z : NATURAL := 2970; + CONSTANT rup_a2_z : NATURAL := 2960; + CONSTANT rup_b_z : NATURAL := 2960; + CONSTANT tphh_b_z : NATURAL := 77; + CONSTANT tpll_b_z : NATURAL := 100; + CONSTANT tpll_a1_z : NATURAL := 125; + CONSTANT tphh_a2_z : NATURAL := 83; + CONSTANT tpll_a2_z : NATURAL := 116; + CONSTANT tphh_a1_z : NATURAL := 95; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oan21_x1; + +ARCHITECTURE behaviour_data_flow OF oan21_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oan21_x1" + SEVERITY WARNING; + z <= ((a1 or a2) and b) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/oan21_x2.ap b/pdks/symbolic/msxlib/cells/oan21_x2.ap new file mode 100644 index 000000000..90164729c --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oan21_x2.ap @@ -0,0 +1,126 @@ +V ALLIANCE : 6 +H oan21_x2,P, 9/ 8/2014,100 +A 0,0,7000,10000 +R 5000,6000,ref_ref,a2_60 +R 6000,5000,ref_ref,a1_50 +R 5000,5000,ref_ref,a2_50 +R 4000,5000,ref_ref,b_50 +R 6000,6000,ref_ref,a1_60 +R 6000,7000,ref_ref,a1_70 +R 5000,7000,ref_ref,a1_70 +R 4000,3000,ref_ref,b_30 +R 5000,3000,ref_ref,b_30 +R 4000,4000,ref_ref,b_40 +R 6000,4000,ref_ref,a2_40 +R 5000,4000,ref_ref,a2_40 +R 1000,6000,ref_ref,z_60 +R 2000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,z_50 +R 2000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 6000,7900,6000,9300,400,*,UP,ALU1 +S 4000,2900,5100,2900,400,*,RIGHT,ALU1 +S 4000,3000,4000,5100,400,*,DOWN,ALU1 +S 4000,3000,5100,3000,400,*,RIGHT,ALU1 +S 4000,3000,4000,5000,400,b,DOWN,CALU1 +S 5000,4000,5000,6000,400,a2,DOWN,CALU1 +S 4900,7100,6000,7100,400,*,RIGHT,ALU1 +S 6000,4800,6000,7000,400,*,UP,ALU1 +S 6000,5000,6000,7000,400,a1,UP,CALU1 +S 4900,7000,6000,7000,400,*,RIGHT,ALU1 +S 2800,6900,2800,9300,400,*,UP,ALU1 +S 5000,3000,5000,3000,400,b,LEFT,CALU1 +S 6000,4000,6000,4000,400,a2,LEFT,CALU1 +S 5000,7000,5000,7000,400,a1,LEFT,CALU1 +S 5000,4000,5000,6100,400,*,UP,ALU1 +S 5000,3900,6100,3900,400,*,RIGHT,ALU1 +S 5000,4000,6100,4000,400,*,RIGHT,ALU1 +S 6400,2000,6400,3100,400,*,UP,ALU1 +S 5400,5100,5900,5100,200,*,RIGHT,POLY +S 5400,5100,5400,5500,200,*,DOWN,POLY +S 3400,7500,3400,7900,200,*,DOWN,POLY +S 5800,1200,5800,1600,200,*,UP,POLY +S 5800,3300,5800,4800,200,*,UP,POLY +S 6200,1800,6200,3100,400,*,UP,NDIF +S 6400,2300,6400,2900,600,*,UP,NDIF +S 5800,1600,5800,3300,200,4,UP,NTRANS +S 4000,5700,4000,7300,1000,*,UP,PDIF +S 3400,5500,3400,7500,200,3,DOWN,PTRANS +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,7000,5000,10000,oan21_x2,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 4600,5500,4600,9300,200,2,DOWN,PTRANS +S 5400,5500,5400,9300,200,1,DOWN,PTRANS +S 5100,5700,5100,9100,400,n1,UP,PDIF +S 4200,5700,4200,9100,400,*,DOWN,PDIF +S 6000,5700,6000,9100,600,*,DOWN,PDIF +S 5400,9300,5400,9700,200,*,DOWN,POLY +S 4600,9300,4600,9700,200,*,DOWN,POLY +S 5300,500,5300,3100,400,*,UP,NDIF +S 4800,1600,4800,3300,200,5,UP,NTRANS +S 4800,1200,4800,1600,200,*,UP,POLY +S 4200,1800,4200,3100,600,*,DOWN,NDIF +S 3600,1600,3600,3300,200,6,UP,NTRANS +S 3600,1200,3600,1600,200,*,UP,POLY +S 3000,2300,3000,2900,600,*,UP,NDIF +S 3200,1800,3200,3100,400,*,UP,NDIF +S 4600,3800,4600,5500,200,*,UP,POLY +S 4800,3300,4800,4000,200,*,UP,POLY +S 1200,1700,1200,3600,200,6,UP,NTRANS +S 600,700,600,3100,400,*,DOWN,ALU1 +S 600,1900,600,3400,600,*,UP,NDIF +S 1600,1900,1600,3400,400,*,UP,NDIF +S 1200,1200,1200,1600,200,*,UP,POLY +S 2200,5500,2200,9300,200,2,DOWN,PTRANS +S 1600,6100,1600,6700,600,*,DOWN,PDIF +S 1800,5700,1800,9100,400,*,UP,PDIF +S 2800,5700,2800,9100,600,*,DOWN,PDIF +S 1000,6000,2000,6000,600,*,LEFT,ALU1 +S 1600,5900,1600,6900,400,*,DOWN,ALU1 +S 3600,3300,3600,4800,200,*,UP,POLY +S 3400,4700,3400,5500,200,*,UP,POLY +S 3900,4800,3900,5100,600,*,DOWN,ALU1 +S 2800,3900,3000,3900,600,*,RIGHT,ALU1 +S 3000,6000,4000,6000,400,*,RIGHT,ALU1 +S 4000,6000,4000,7100,400,*,UP,ALU1 +S 1200,4100,2800,4100,200,*,LEFT,POLY +S 1200,3600,1200,4100,200,*,DOWN,POLY +S 2200,4100,2200,5500,200,*,DOWN,POLY +S 3000,2100,3000,6000,400,*,DOWN,ALU1 +S 2000,3000,2000,6000,400,z,UP,CALU1 +S 1000,6000,1000,6000,400,z,LEFT,CALU1 +S 2200,9300,2200,9700,200,*,DOWN,POLY +S 4100,2000,6400,2000,400,*,RIGHT,ALU1 +S 1800,2600,1800,3200,600,*,DOWN,NDIF +S 2000,2400,2000,6000,400,*,UP,ALU1 +S 1900,2400,1900,3400,600,*,UP,ALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 700,9300,CONT_BODY_N,* +V 5000,4000,CONT_POLY,* +V 6000,4900,CONT_POLY,* +V 6400,2200,CONT_DIF_N,n2 +V 6400,3000,CONT_DIF_N,n2 +V 2800,7000,CONT_DIF_P,* +V 6000,9000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 5400,600,CONT_DIF_N,* +V 4200,2000,CONT_DIF_N,n2 +V 600,2000,CONT_DIF_N,* +V 1800,3300,CONT_DIF_N,* +V 600,3000,CONT_DIF_N,* +V 1600,6000,CONT_DIF_P,* +V 1600,6800,CONT_DIF_P,* +V 2800,8000,CONT_DIF_P,* +V 2800,9000,CONT_DIF_P,* +V 3800,4900,CONT_POLY,* +V 4000,7000,CONT_DIF_P,zn +V 4000,6200,CONT_DIF_P,zn +V 2800,3900,CONT_POLY,zn +V 3000,3000,CONT_DIF_N,zn +V 3000,2200,CONT_DIF_N,zn +V 1800,2500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/oan21_x2.vbe b/pdks/symbolic/msxlib/cells/oan21_x2.vbe new file mode 100644 index 000000000..b05bce287 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oan21_x2.vbe @@ -0,0 +1,38 @@ +ENTITY oan21_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_a1 : NATURAL := 6; + CONSTANT cin_a2 : NATURAL := 7; + CONSTANT cin_b : NATURAL := 5; + CONSTANT rdown_a1_z : NATURAL := 1220; + CONSTANT rdown_a2_z : NATURAL := 1220; + CONSTANT rdown_b_z : NATURAL := 1210; + CONSTANT rup_a1_z : NATURAL := 1560; + CONSTANT rup_a2_z : NATURAL := 1560; + CONSTANT rup_b_z : NATURAL := 1560; + CONSTANT tphh_b_z : NATURAL := 80; + CONSTANT tpll_b_z : NATURAL := 103; + CONSTANT tpll_a1_z : NATURAL := 126; + CONSTANT tphh_a2_z : NATURAL := 85; + CONSTANT tpll_a2_z : NATURAL := 117; + CONSTANT tphh_a1_z : NATURAL := 98; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oan21_x2; + +ARCHITECTURE behaviour_data_flow OF oan21_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oan21_x2" + SEVERITY WARNING; + z <= ((a1 or a2) and b) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/oan22_x1.ap b/pdks/symbolic/msxlib/cells/oan22_x1.ap new file mode 100644 index 000000000..36f662219 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oan22_x1.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 6 +H oan22_x1,P, 9/ 8/2014,100 +A 0,0,8000,10000 +R 1000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +R 2000,4000,ref_ref,z_40 +R 2000,5000,ref_ref,z_50 +R 2000,6000,ref_ref,z_60 +R 2000,7000,ref_ref,z_70 +R 5000,6000,ref_ref,b1_60 +R 6000,7000,ref_ref,a1_70 +R 6000,6000,ref_ref,a2_60 +R 4000,6000,ref_ref,b1_60 +R 6000,3000,ref_ref,b2_30 +R 5000,4000,ref_ref,b2_40 +R 5000,5000,ref_ref,b2_50 +R 6000,4000,ref_ref,a2_40 +R 6000,5000,ref_ref,a2_50 +R 7000,5000,ref_ref,a1_50 +R 7000,6000,ref_ref,a1_60 +R 5000,3000,ref_ref,b2_30 +R 7000,4000,ref_ref,a2_40 +R 7000,7000,ref_ref,a1_70 +R 4000,4000,ref_ref,b1_40 +R 4000,5000,ref_ref,b1_50 +R 2000,8000,ref_ref,z_80 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 2000,6700,2000,7300,600,*,UP,PDIF +S 6300,700,6300,2800,400,*,UP,NDIF +S 6800,1400,6800,1800,200,*,UP,POLY +S 5800,1400,5800,1800,200,*,UP,POLY +S 4600,1400,4600,1800,200,*,UP,POLY +S 3400,1400,3400,1800,200,*,UP,POLY +S 3400,3000,3400,3900,200,*,UP,POLY +S 4600,3000,4600,5500,200,*,DOWN,POLY +S 6800,3000,6800,4700,200,*,UP,POLY +S 5800,3000,5800,5500,200,*,DOWN,POLY +S 7400,1900,7400,2100,600,*,UP,ALU1 +S 2800,1900,2800,2100,600,*,UP,ALU1 +S 5200,1900,5200,2100,600,*,DOWN,ALU1 +S 4000,2700,4000,3000,600,*,UP,ALU1 +S 7200,2000,7200,2800,400,*,DOWN,NDIF +S 6800,1800,6800,3000,200,5,UP,NTRANS +S 5800,1800,5800,3000,200,6,UP,NTRANS +S 5200,2000,5200,2800,1000,*,UP,NDIF +S 3000,2000,3000,2800,400,*,DOWN,NDIF +S 4600,1800,4600,3000,200,8,UP,NTRANS +S 3400,1800,3400,3000,200,7,UP,NTRANS +S 4000,2000,4000,2800,1000,*,UP,NDIF +S 2800,1900,7400,1900,400,*,RIGHT,ALU1 +S 1300,3700,1300,4700,200,*,DOWN,POLY +S 1300,2300,1300,2700,200,*,UP,POLY +S 600,2900,600,3500,600,*,UP,NDIF +S 1300,2700,1300,3700,200,2z,UP,NTRANS +S 1700,2900,1700,3500,400,*,UP,NDIF +S 2600,4900,2600,6300,200,*,DOWN,POLY +S 6600,8300,6600,8700,200,*,DOWN,POLY +S 5800,8300,5800,8700,200,*,DOWN,POLY +S 4600,8300,4600,8700,200,*,DOWN,POLY +S 3800,8300,3800,8700,200,*,DOWN,POLY +S 2600,8300,2600,8700,200,*,DOWN,POLY +S 3200,5900,3200,8100,600,*,DOWN,PDIF +S 2200,6500,2200,8100,400,*,DOWN,PDIF +S 2600,6300,2600,8300,200,1z,DOWN,PTRANS +S 4200,5900,4200,8100,600,n2,UP,PDIF +S 3800,5700,3800,8300,200,3,DOWN,PTRANS +S 6200,5900,6200,8100,600,n1,UP,PDIF +S 6600,5700,6600,8300,200,1,DOWN,PTRANS +S 7300,5900,7300,8100,600,*,DOWN,PDIF +S 4600,5700,4600,8300,200,4,DOWN,PTRANS +S 5200,5900,5200,8100,1000,*,UP,PDIF +S 5800,5700,5800,8300,200,2,DOWN,PTRANS +S 3000,3000,3000,7000,400,*,DOWN,ALU1 +S 3000,7000,5200,7000,400,*,RIGHT,ALU1 +S 5200,7000,5200,8100,400,*,UP,ALU1 +S 2800,4900,3000,4900,600,*,RIGHT,ALU1 +S 1300,4700,2800,4700,200,*,LEFT,POLY +S 900,4000,2000,4000,400,*,LEFT,ALU1 +S 1000,4000,1000,4000,400,z,LEFT,CALU1 +S 1900,2900,1900,4000,400,*,DOWN,ALU1 +S 3800,4000,4000,4000,600,*,RIGHT,ALU1 +S 3800,4000,3800,5500,200,*,DOWN,POLY +S 700,700,700,3100,400,*,DOWN,ALU1 +S 0,5000,8000,5000,10000,oan22_x1,LEFT,TALU8 +S 0,2200,8000,2200,5200,*,LEFT,PWELL +S 0,7600,8000,7600,5600,*,LEFT,NWELL +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 6600,5000,6600,5500,200,*,DOWN,POLY +S 5000,6000,5000,6000,400,b1,LEFT,CALU1 +S 6000,4000,6000,6100,400,*,UP,ALU1 +S 5900,4000,5900,6100,400,*,UP,ALU1 +S 6000,4000,6000,6000,400,a2,DOWN,CALU1 +S 6000,4000,7100,4000,400,*,RIGHT,ALU1 +S 7000,4000,7000,4000,400,a2,LEFT,CALU1 +S 6000,7000,6000,7000,400,a1,LEFT,CALU1 +S 6000,3000,6000,3000,400,b2,LEFT,CALU1 +S 4000,4000,4000,6000,400,b1,UP,CALU1 +S 4000,6000,5100,6000,400,*,RIGHT,ALU1 +S 7000,4800,7000,7000,400,*,UP,ALU1 +S 7000,5000,7000,7000,400,a1,UP,CALU1 +S 7200,7900,7200,9300,400,*,UP,ALU1 +S 5000,2900,6100,2900,400,*,RIGHT,ALU1 +S 5000,3000,6100,3000,400,*,RIGHT,ALU1 +S 3200,7900,3200,9300,400,*,UP,ALU1 +S 4000,6100,5100,6100,400,*,RIGHT,ALU1 +S 6000,7000,7000,7000,600,*,RIGHT,ALU1 +S 3000,3000,4100,3000,400,*,RIGHT,ALU1 +S 4000,3900,4000,6000,400,*,UP,ALU1 +S 5000,3000,5000,5100,400,*,DOWN,ALU1 +S 5000,3000,5000,5000,400,b2,DOWN,CALU1 +S 2000,3000,2000,8000,400,z,DOWN,CALU1 +S 2000,2900,2000,8100,400,*,DOWN,ALU1 +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 2000,7400,CONT_DIF_P,* +V 6400,800,CONT_DIF_N,* +V 7400,2100,CONT_DIF_N,n3 +V 5200,2100,CONT_DIF_N,n3 +V 2800,2100,CONT_DIF_N,n3 +V 4000,2700,CONT_DIF_N,zn +V 1900,3400,CONT_DIF_N,* +V 5200,7200,CONT_DIF_P,zn +V 5200,8000,CONT_DIF_P,zn +V 2800,4900,CONT_POLY,zn +V 2000,6600,CONT_DIF_P,* +V 3800,4000,CONT_POLY,* +V 700,3000,CONT_DIF_N,* +V 3200,8000,CONT_DIF_P,* +V 7200,8000,CONT_DIF_P,* +V 5000,4900,CONT_POLY,* +V 7000,4900,CONT_POLY,* +V 6000,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/oan22_x1.vbe b/pdks/symbolic/msxlib/cells/oan22_x1.vbe new file mode 100644 index 000000000..6c4adb320 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oan22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY oan22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT cin_b1 : NATURAL := 5; + CONSTANT cin_b2 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT rdown_b1_z : NATURAL := 2320; + CONSTANT rdown_b2_z : NATURAL := 2320; + CONSTANT rdown_a2_z : NATURAL := 2340; + CONSTANT rdown_a1_z : NATURAL := 2340; + CONSTANT rup_b1_z : NATURAL := 2970; + CONSTANT rup_b2_z : NATURAL := 2960; + CONSTANT rup_a2_z : NATURAL := 2960; + CONSTANT rup_a1_z : NATURAL := 2970; + CONSTANT tphh_a2_z : NATURAL := 96; + CONSTANT tpll_b1_z : NATURAL := 122; + CONSTANT tphh_a1_z : NATURAL := 107; + CONSTANT tphh_b2_z : NATURAL := 87; + CONSTANT tpll_a1_z : NATURAL := 146; + CONSTANT tpll_b2_z : NATURAL := 112; + CONSTANT tphh_b1_z : NATURAL := 99; + CONSTANT tpll_a2_z : NATURAL := 136; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a2 : in BIT; + a1 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oan22_x1; + +ARCHITECTURE behaviour_data_flow OF oan22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oan22_x1" + SEVERITY WARNING; + z <= ((b1 or b2) and (a2 or a1)) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/oan22_x2.ap b/pdks/symbolic/msxlib/cells/oan22_x2.ap new file mode 100644 index 000000000..5ba3758ba --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oan22_x2.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H oan22_x2,P, 9/ 8/2014,100 +A 0,0,8000,10000 +R 1000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +R 2000,4000,ref_ref,z_40 +R 2000,5000,ref_ref,z_50 +R 2000,6000,ref_ref,z_60 +R 2000,7000,ref_ref,z_70 +R 5000,6000,ref_ref,b1_60 +R 6000,7000,ref_ref,a1_70 +R 6000,6000,ref_ref,a2_60 +R 4000,6000,ref_ref,b1_60 +R 6000,3000,ref_ref,b2_30 +R 5000,4000,ref_ref,b2_40 +R 5000,5000,ref_ref,b2_50 +R 6000,4000,ref_ref,a2_40 +R 6000,5000,ref_ref,a2_50 +R 7000,5000,ref_ref,a1_50 +R 7000,6000,ref_ref,a1_60 +R 5000,3000,ref_ref,b2_30 +R 7000,4000,ref_ref,a2_40 +R 7000,7000,ref_ref,a1_70 +R 4000,4000,ref_ref,b1_40 +R 4000,5000,ref_ref,b1_50 +R 2000,8000,ref_ref,z_80 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 2600,9400,2600,9700,200,*,DOWN,POLY +S 3000,3000,3000,7000,400,*,DOWN,ALU1 +S 3000,7000,5200,7000,400,*,RIGHT,ALU1 +S 2600,5500,2600,9400,200,1z,DOWN,PTRANS +S 5200,7000,5200,8100,400,*,UP,ALU1 +S 2800,4900,3000,4900,600,*,RIGHT,ALU1 +S 1300,3600,1300,4700,200,*,DOWN,POLY +S 1300,4700,2800,4700,200,*,LEFT,POLY +S 3400,3400,3400,3900,200,*,UP,POLY +S 900,4000,2000,4000,400,*,LEFT,ALU1 +S 1000,4000,1000,4000,400,z,LEFT,CALU1 +S 1900,2900,1900,4000,400,*,DOWN,ALU1 +S 2000,5900,2000,6500,600,*,DOWN,PDIF +S 2200,5700,2200,9200,400,*,DOWN,PDIF +S 3800,4000,4000,4000,600,*,RIGHT,ALU1 +S 3800,4000,3800,5500,200,*,DOWN,POLY +S 700,700,700,3100,400,*,DOWN,ALU1 +S 600,1900,600,3400,600,*,UP,NDIF +S 1700,1900,1700,3400,400,*,UP,NDIF +S 1300,1700,1300,3600,200,2z,UP,NTRANS +S 1300,1300,1300,1700,200,*,UP,POLY +S 2700,2000,7500,2000,400,*,RIGHT,ALU1 +S 3000,1900,3000,3200,400,*,DOWN,NDIF +S 3400,1300,3400,1700,200,*,UP,POLY +S 3400,1700,3400,3400,200,7,UP,NTRANS +S 4000,1900,4000,3200,1000,*,UP,NDIF +S 4600,3400,4600,5500,200,*,DOWN,POLY +S 4600,1300,4600,1700,200,*,UP,POLY +S 4600,1700,4600,3400,200,8,UP,NTRANS +S 5200,1900,5200,3200,1000,*,UP,NDIF +S 5800,1300,5800,1700,200,*,UP,POLY +S 5800,1700,5800,3400,200,6,UP,NTRANS +S 6300,600,6300,3200,400,*,UP,NDIF +S 0,5000,8000,5000,10000,oan22_x2,LEFT,TALU8 +S 0,2200,8000,2200,5200,*,LEFT,PWELL +S 0,7600,8000,7600,5600,*,LEFT,NWELL +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 3100,5700,3100,9200,600,*,DOWN,PDIF +S 7300,5700,7300,9200,600,*,DOWN,PDIF +S 6200,5700,6200,9200,600,n1,UP,PDIF +S 6600,5500,6600,9400,200,1,DOWN,PTRANS +S 5800,5500,5800,9400,200,2,DOWN,PTRANS +S 5200,5700,5200,9200,1000,*,UP,PDIF +S 4200,5700,4200,9200,600,n2,UP,PDIF +S 4600,5500,4600,9400,200,4,DOWN,PTRANS +S 3800,5500,3800,9400,200,3,DOWN,PTRANS +S 6800,1700,6800,3400,200,5,UP,NTRANS +S 7200,1900,7200,3200,400,*,DOWN,NDIF +S 7400,2100,7400,2700,600,*,UP,NDIF +S 6800,1300,6800,1700,200,*,UP,POLY +S 6600,5000,6600,5500,200,*,DOWN,POLY +S 3800,9400,3800,9700,200,*,DOWN,POLY +S 5800,4200,5800,5500,200,*,DOWN,POLY +S 6800,3400,6800,4700,200,*,UP,POLY +S 6600,9400,6600,9700,200,*,DOWN,POLY +S 5800,9400,5800,9700,200,*,DOWN,POLY +S 4600,9400,4600,9700,200,*,DOWN,POLY +S 5000,6000,5000,6000,400,b1,LEFT,CALU1 +S 6000,4000,6000,6100,400,*,UP,ALU1 +S 5900,4000,5900,6100,400,*,UP,ALU1 +S 6000,4000,6000,6000,400,a2,DOWN,CALU1 +S 6000,4000,7100,4000,400,*,RIGHT,ALU1 +S 7000,4000,7000,4000,400,a2,LEFT,CALU1 +S 7400,2000,7400,2800,600,*,UP,ALU1 +S 6000,7000,6000,7000,400,a1,LEFT,CALU1 +S 6000,3000,6000,3000,400,b2,LEFT,CALU1 +S 4000,4000,4000,6000,400,b1,UP,CALU1 +S 4000,6000,5100,6000,400,*,RIGHT,ALU1 +S 7000,4800,7000,7000,400,*,UP,ALU1 +S 7000,5000,7000,7000,400,a1,UP,CALU1 +S 7200,7900,7200,9300,400,*,UP,ALU1 +S 5000,2900,6100,2900,400,*,RIGHT,ALU1 +S 5000,3000,6100,3000,400,*,RIGHT,ALU1 +S 3200,7900,3200,9300,400,*,UP,ALU1 +S 4000,6100,5100,6100,400,*,RIGHT,ALU1 +S 6000,7000,7000,7000,600,*,RIGHT,ALU1 +S 3000,3000,4100,3000,400,*,RIGHT,ALU1 +S 4000,3900,4000,6000,400,*,UP,ALU1 +S 5000,3000,5000,5100,400,*,DOWN,ALU1 +S 5000,3000,5000,5000,400,b2,DOWN,CALU1 +S 2000,3000,2000,8000,400,z,DOWN,CALU1 +S 2000,2900,2000,8100,400,*,DOWN,ALU1 +V 1000,9300,CONT_BODY_N,* +V 2100,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 5200,7200,CONT_DIF_P,zn +V 5200,8000,CONT_DIF_P,zn +V 4000,3000,CONT_DIF_N,zn +V 2800,4900,CONT_POLY,zn +V 2000,6600,CONT_DIF_P,* +V 2000,5800,CONT_DIF_P,* +V 3800,4000,CONT_POLY,* +V 1900,3300,CONT_DIF_N,* +V 700,2000,CONT_DIF_N,* +V 700,3000,CONT_DIF_N,* +V 2800,2000,CONT_DIF_N,n3 +V 5200,2000,CONT_DIF_N,n3 +V 6400,700,CONT_DIF_N,* +V 3200,8000,CONT_DIF_P,* +V 7200,8000,CONT_DIF_P,* +V 7200,9000,CONT_DIF_P,* +V 3200,9000,CONT_DIF_P,* +V 7400,2000,CONT_DIF_N,n3 +V 7400,2800,CONT_DIF_N,n3 +V 5000,4900,CONT_POLY,* +V 7000,4900,CONT_POLY,* +V 6000,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/oan22_x2.vbe b/pdks/symbolic/msxlib/cells/oan22_x2.vbe new file mode 100644 index 000000000..f3d6f6e6f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/oan22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY oan22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT cin_b1 : NATURAL := 7; + CONSTANT cin_b2 : NATURAL := 7; + CONSTANT cin_a2 : NATURAL := 7; + CONSTANT cin_a1 : NATURAL := 7; + CONSTANT rdown_b1_z : NATURAL := 1220; + CONSTANT rdown_b2_z : NATURAL := 1220; + CONSTANT rdown_a2_z : NATURAL := 1230; + CONSTANT rdown_a1_z : NATURAL := 1230; + CONSTANT rup_b1_z : NATURAL := 1520; + CONSTANT rup_b2_z : NATURAL := 1520; + CONSTANT rup_a2_z : NATURAL := 1520; + CONSTANT rup_a1_z : NATURAL := 1520; + CONSTANT tphh_a2_z : NATURAL := 97; + CONSTANT tpll_b1_z : NATURAL := 122; + CONSTANT tphh_a1_z : NATURAL := 109; + CONSTANT tphh_b2_z : NATURAL := 89; + CONSTANT tpll_a1_z : NATURAL := 143; + CONSTANT tpll_b2_z : NATURAL := 112; + CONSTANT tphh_b1_z : NATURAL := 101; + CONSTANT tpll_a2_z : NATURAL := 134; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a2 : in BIT; + a1 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oan22_x2; + +ARCHITECTURE behaviour_data_flow OF oan22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oan22_x2" + SEVERITY WARNING; + z <= ((b1 or b2) and (a2 or a1)) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/or2_x1.ap b/pdks/symbolic/msxlib/cells/or2_x1.ap new file mode 100644 index 000000000..80412bf0b --- /dev/null +++ b/pdks/symbolic/msxlib/cells/or2_x1.ap @@ -0,0 +1,93 @@ +V ALLIANCE : 6 +H or2_x1,P, 9/ 8/2014,100 +A 0,0,5000,10000 +R 4000,6000,ref_ref,b_60 +R 4000,5000,ref_ref,b_50 +R 3000,5000,ref_ref,a_50 +R 3000,4000,ref_ref,a_40 +R 4000,4000,ref_ref,a_40 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,3000,ref_ref,z_30 +R 1000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 1000,7000,ref_ref,z_70 +R 3000,6000,ref_ref,b_60 +S 3500,9300,4300,9300,600,*,RIGHT,NTIE +S 3500,700,4300,700,600,*,RIGHT,PTIE +S 800,3100,1000,3100,600,*,RIGHT,ALU1 +S 1000,1900,2100,1900,400,*,RIGHT,ALU1 +S 1000,2000,2100,2000,400,*,RIGHT,ALU1 +S 1000,2600,1000,3200,400,*,DOWN,NDIF +S 1400,2000,1400,2400,200,*,DOWN,POLY +S 1400,2400,1400,3400,200,2z,DOWN,NTRANS +S 2600,3400,2600,3900,200,*,UP,POLY +S 3600,5100,3600,5600,200,*,DOWN,POLY +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 2600,2700,2600,3400,200,2a,DOWN,NTRANS +S 3800,2700,3800,3400,200,2b,DOWN,NTRANS +S 1600,5600,1600,7600,200,1z,UP,PTRANS +S 2800,5600,2800,8300,200,1a,UP,PTRANS +S 3600,5600,3600,8300,200,1b,UP,PTRANS +S 2000,900,2000,3200,600,*,UP,NDIF +S 4400,700,4400,3100,400,*,DOWN,ALU1 +S 2000,3000,3300,3000,400,*,LEFT,ALU1 +S 2800,4400,2800,5600,200,*,UP,POLY +S 2600,2300,2600,2700,200,*,DOWN,POLY +S 3800,2300,3800,2700,200,*,DOWN,POLY +S 4400,2900,4400,3200,600,*,UP,NDIF +S 3200,2900,3200,3200,1000,*,UP,NDIF +S 4000,5800,4000,8100,400,*,UP,PDIF +S 3600,8300,3600,8700,200,*,DOWN,POLY +S 2800,8300,2800,8700,200,*,DOWN,POLY +S 1600,7600,1600,8000,200,*,DOWN,POLY +S 1200,5800,1200,7400,400,*,UP,PDIF +S 3200,5800,3200,8100,600,n1,DOWN,PDIF +S 3000,3900,4100,3900,400,*,RIGHT,ALU1 +S 3000,4000,4100,4000,400,*,RIGHT,ALU1 +S 1000,5800,1000,6600,600,*,UP,PDIF +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,5000,5000,10000,or2_x1,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 3800,3400,3800,4800,200,*,UP,POLY +S 1000,1900,1000,7100,400,*,DOWN,ALU1 +S 1600,4800,1600,5600,200,*,DOWN,POLY +S 1400,3400,1400,5200,200,*,UP,POLY +S 1400,5000,2200,5000,600,*,LEFT,POLY +S 2600,3800,3000,3800,200,*,RIGHT,POLY +S 3600,5200,4000,5200,200,*,RIGHT,POLY +S 3000,4000,3000,5000,400,a,UP,CALU1 +S 3000,3900,3000,5100,400,*,DOWN,ALU1 +S 2900,6000,4000,6000,400,*,RIGHT,ALU1 +S 2900,6100,4000,6100,400,*,RIGHT,ALU1 +S 3000,6000,3000,6000,400,b,LEFT,CALU1 +S 4000,5000,4000,6000,400,b,UP,CALU1 +S 4000,4900,4000,6100,400,*,UP,ALU1 +S 4200,7300,4200,7900,600,*,DOWN,PDIF +S 2000,7000,4200,7000,400,*,LEFT,ALU1 +S 4200,7000,4200,8100,400,*,UP,ALU1 +S 2000,3000,2000,7000,400,*,UP,ALU1 +S 2200,7900,2200,9300,400,*,UP,ALU1 +S 2200,5800,2200,8100,600,n2,DOWN,PDIF +V 4300,9300,CONT_BODY_N,* +V 3400,9300,CONT_BODY_N,* +V 4300,700,CONT_BODY_P,* +V 3400,700,CONT_BODY_P,* +V 800,3100,CONT_DIF_N,* +V 3200,3000,CONT_DIF_N,zn +V 3000,4000,CONT_POLY,* +V 4400,3000,CONT_DIF_N,* +V 1000,6700,CONT_DIF_P,* +V 1000,5900,CONT_DIF_P,* +V 4000,5000,CONT_POLY,* +V 2000,1000,CONT_DIF_N,* +V 2000,5000,CONT_POLY,zn +V 4200,8000,CONT_DIF_P,zn +V 4200,7200,CONT_DIF_P,zn +V 2200,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/or2_x1.vbe b/pdks/symbolic/msxlib/cells/or2_x1.vbe new file mode 100644 index 000000000..2147c7728 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/or2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY or2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 2300; + CONSTANT rdown_b_z : NATURAL := 2300; + CONSTANT rup_a_z : NATURAL := 2970; + CONSTANT rup_b_z : NATURAL := 2960; + CONSTANT tpll_a_z : NATURAL := 102; + CONSTANT tphh_b_z : NATURAL := 80; + CONSTANT tpll_b_z : NATURAL := 93; + CONSTANT tphh_a_z : NATURAL := 93; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END or2_x1; + +ARCHITECTURE behaviour_data_flow OF or2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on or2_x1" + SEVERITY WARNING; + z <= (a or b) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/or3_x1.ap b/pdks/symbolic/msxlib/cells/or3_x1.ap new file mode 100644 index 000000000..aeca76b5b --- /dev/null +++ b/pdks/symbolic/msxlib/cells/or3_x1.ap @@ -0,0 +1,106 @@ +V ALLIANCE : 6 +H or3_x1,P, 9/ 8/2014,100 +A 0,0,6000,10000 +R 4000,3000,ref_ref,c_30 +R 5000,3000,ref_ref,c_30 +R 5000,5000,ref_ref,c_50 +R 5000,4000,ref_ref,c_40 +R 1000,7000,ref_ref,z_70 +R 2000,2000,ref_ref,z_20 +R 1000,2000,ref_ref,z_20 +R 1000,3000,ref_ref,z_30 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +R 4000,4000,ref_ref,a_40 +R 3000,4000,ref_ref,a_40 +R 3000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,a_60 +R 4000,5000,ref_ref,b_50 +R 4000,6000,ref_ref,b_60 +R 4000,7000,ref_ref,b_70 +R 3000,7000,ref_ref,b_70 +S 5400,6900,5400,8000,400,*,DOWN,ALU1 +S 2000,8000,5400,8000,400,*,LEFT,ALU1 +S 5400,7100,5400,7700,600,*,UP,PDIF +S 3000,7000,3000,7000,400,b,LEFT,CALU1 +S 4000,3000,4000,3000,400,c,LEFT,CALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 3600,2400,3600,2900,200,*,UP,POLY +S 3200,9300,3200,9700,200,*,DOWN,POLY +S 4000,9300,4000,9700,200,*,DOWN,POLY +S 4800,9300,4800,9700,200,*,DOWN,POLY +S 1800,900,1800,2500,600,*,UP,NDIF +S 3900,2900,5000,2900,400,*,RIGHT,ALU1 +S 5000,3000,5000,5100,400,*,UP,ALU1 +S 3900,3000,5000,3000,400,*,RIGHT,ALU1 +S 5000,3000,5000,5000,400,c,UP,CALU1 +S 3000,2000,5500,2000,400,*,RIGHT,ALU1 +S 3000,2000,3000,3000,400,*,DOWN,ALU1 +S 2000,3000,3000,3000,400,*,LEFT,ALU1 +S 2800,2800,2800,4500,200,*,UP,POLY +S 2400,2800,2800,2800,200,*,RIGHT,POLY +S 3800,2800,3800,4800,200,*,DOWN,POLY +S 4800,2400,4800,5600,200,*,DOWN,POLY +S 2400,1300,2400,1700,200,*,DOWN,POLY +S 3600,1300,3600,1700,200,*,DOWN,POLY +S 4800,1300,4800,1700,200,*,DOWN,POLY +S 4200,900,4200,2200,600,*,UP,NDIF +S 4800,1700,4800,2400,200,2c,DOWN,NTRANS +S 5400,1900,5400,2200,600,*,UP,NDIF +S 2400,1700,2400,2400,200,2a,DOWN,NTRANS +S 3600,1700,3600,2400,200,2b,DOWN,NTRANS +S 3000,1900,3000,2200,1000,*,UP,NDIF +S 5200,5800,5200,9100,400,*,UP,PDIF +S 3200,5600,3200,9300,200,1a,UP,PTRANS +S 3600,5800,3600,9100,600,n1,DOWN,PDIF +S 4800,5600,4800,9300,200,1c,UP,PTRANS +S 4000,5600,4000,9300,200,1b,UP,PTRANS +S 4400,5800,4400,9100,600,n2,DOWN,PDIF +S 1200,4400,1600,4400,200,*,RIGHT,POLY +S 2400,5800,2400,9100,1000,n2,DOWN,PDIF +S 3200,4400,3200,5600,200,*,UP,POLY +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,6000,5000,10000,or3_x1,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 2900,7100,4000,7100,400,*,RIGHT,ALU1 +S 2900,7000,4000,7000,400,*,RIGHT,ALU1 +S 1000,5800,1000,6600,600,*,UP,PDIF +S 3000,4000,4100,4000,400,*,RIGHT,ALU1 +S 3000,3900,4100,3900,400,*,RIGHT,ALU1 +S 3000,4000,3000,6100,400,*,DOWN,ALU1 +S 4000,4900,4000,7100,400,*,UP,ALU1 +S 1000,2000,1000,7100,400,*,DOWN,ALU1 +S 2000,3000,2000,8000,400,*,UP,ALU1 +S 1200,5800,1200,7400,400,*,UP,PDIF +S 1600,7600,1600,8000,200,*,DOWN,POLY +S 1600,4400,1600,5600,200,*,DOWN,POLY +S 4000,5000,4000,7000,400,b,UP,CALU1 +S 3000,4000,3000,6000,400,a,UP,CALU1 +S 1600,5600,1600,7600,200,1z,UP,PTRANS +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 800,1900,800,2500,400,*,DOWN,NDIF +S 1200,1700,1200,2700,200,2z,DOWN,NTRANS +S 1200,1300,1200,1700,200,*,DOWN,POLY +S 1200,2700,1200,4400,200,*,UP,POLY +S 500,2000,2100,2000,400,*,RIGHT,ALU1 +V 1000,9300,CONT_BODY_N,* +V 3000,700,CONT_BODY_P,* +V 5400,7800,CONT_DIF_P,zn +V 5400,7000,CONT_DIF_P,zn +V 5000,3000,CONT_POLY,* +V 4200,1000,CONT_DIF_N,* +V 5400,2000,CONT_DIF_N,zn +V 2400,9000,CONT_DIF_P,* +V 3000,4600,CONT_POLY,* +V 4000,5000,CONT_POLY,* +V 1000,5900,CONT_DIF_P,* +V 1000,6700,CONT_DIF_P,* +V 2000,4600,CONT_POLY,zn +V 600,2000,CONT_DIF_N,* +V 1800,1000,CONT_DIF_N,* +V 3000,2100,CONT_DIF_N,zn +EOF diff --git a/pdks/symbolic/msxlib/cells/or3_x1.vbe b/pdks/symbolic/msxlib/cells/or3_x1.vbe new file mode 100644 index 000000000..4c2892b7d --- /dev/null +++ b/pdks/symbolic/msxlib/cells/or3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY or3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 2330; + CONSTANT rdown_b_z : NATURAL := 2330; + CONSTANT rdown_c_z : NATURAL := 2330; + CONSTANT rup_a_z : NATURAL := 2990; + CONSTANT rup_b_z : NATURAL := 2970; + CONSTANT rup_c_z : NATURAL := 2960; + CONSTANT tphh_c_z : NATURAL := 93; + CONSTANT tpll_a_z : NATURAL := 143; + CONSTANT tphh_b_z : NATURAL := 112; + CONSTANT tpll_b_z : NATURAL := 134; + CONSTANT tphh_a_z : NATURAL := 125; + CONSTANT tpll_c_z : NATURAL := 111; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END or3_x1; + +ARCHITECTURE behaviour_data_flow OF or3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on or3_x1" + SEVERITY WARNING; + z <= ((a or b) or c) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/or4_x1.ap b/pdks/symbolic/msxlib/cells/or4_x1.ap new file mode 100644 index 000000000..4748a86d9 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/or4_x1.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H or4_x1,P, 9/ 8/2014,100 +A 0,0,7000,10000 +R 5000,7000,ref_ref,d_70 +R 6000,7000,ref_ref,d_70 +R 6000,6000,ref_ref,d_60 +R 6000,4000,ref_ref,c_40 +R 3000,7000,ref_ref,b_70 +R 5000,5000,ref_ref,c_50 +R 5000,4000,ref_ref,c_40 +R 1000,7000,ref_ref,z_70 +R 2000,2000,ref_ref,z_20 +R 1000,2000,ref_ref,z_20 +R 1000,3000,ref_ref,z_30 +R 1000,4000,ref_ref,z_40 +R 1000,5000,ref_ref,z_50 +R 1000,6000,ref_ref,z_60 +R 4000,4000,ref_ref,a_40 +R 3000,4000,ref_ref,a_40 +R 3000,5000,ref_ref,a_50 +R 3000,6000,ref_ref,a_60 +R 4000,5000,ref_ref,b_50 +R 4000,6000,ref_ref,b_60 +R 4000,7000,ref_ref,b_70 +R 6000,5000,ref_ref,d_50 +R 5000,6000,ref_ref,c_60 +S 5100,700,5900,700,600,*,RIGHT,PTIE +S 5600,9400,5600,9700,200,*,DOWN,POLY +S 4800,9400,4800,9700,200,*,DOWN,POLY +S 4000,9400,4000,9700,200,*,DOWN,POLY +S 3200,9400,3200,9700,200,*,DOWN,POLY +S 3600,3300,3600,3800,200,*,UP,POLY +S 4800,3900,4800,5500,200,*,DOWN,POLY +S 3200,4400,3200,5500,200,*,UP,POLY +S 3800,3700,3800,4700,200,*,DOWN,POLY +S 500,3000,1000,3000,400,*,RIGHT,ALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,7000,5000,10000,or4_x1,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 6400,700,6400,3100,400,*,DOWN,ALU1 +S 6000,4800,6000,7000,400,*,DOWN,ALU1 +S 5000,4000,5000,6100,400,*,UP,ALU1 +S 4900,7100,6000,7100,400,*,LEFT,ALU1 +S 4900,7000,6000,7000,400,*,LEFT,ALU1 +S 6000,5000,6000,7000,400,d,DOWN,CALU1 +S 4600,3300,4600,3900,200,*,UP,POLY +S 5000,3900,6100,3900,400,*,RIGHT,ALU1 +S 5600,5000,5600,5500,200,*,DOWN,POLY +S 5000,4000,6100,4000,400,*,RIGHT,ALU1 +S 2900,7000,4000,7000,400,*,RIGHT,ALU1 +S 2900,7100,4000,7100,400,*,RIGHT,ALU1 +S 2000,3000,5300,3000,400,*,LEFT,ALU1 +S 4000,700,4000,1900,400,*,DOWN,ALU1 +S 5800,3300,5800,4700,200,*,UP,POLY +S 5800,2300,5800,2700,200,*,DOWN,POLY +S 5800,2700,5800,3300,200,2d,DOWN,NTRANS +S 4600,2700,4600,3300,200,2c,DOWN,NTRANS +S 4600,2300,4600,2700,200,*,DOWN,POLY +S 4100,1700,4100,3100,400,*,UP,NDIF +S 3600,2400,3600,2700,200,*,DOWN,POLY +S 2400,3700,2800,3700,200,*,RIGHT,POLY +S 2800,3700,2800,4500,200,*,UP,POLY +S 2400,2300,2400,2700,200,*,DOWN,POLY +S 3600,2700,3600,3300,200,2b,DOWN,NTRANS +S 2400,2700,2400,3300,200,2a,DOWN,NTRANS +S 1800,900,1800,3100,600,*,UP,NDIF +S 1600,4400,1600,5500,200,*,DOWN,POLY +S 1200,4400,1600,4400,200,*,RIGHT,POLY +S 1200,3300,1200,4400,200,*,UP,POLY +S 1200,1900,1200,2300,200,*,DOWN,POLY +S 1200,2300,1200,3300,200,2z,DOWN,NTRANS +S 800,2500,800,3100,400,*,DOWN,NDIF +S 1000,1900,2100,1900,400,*,RIGHT,ALU1 +S 1000,2000,2100,2000,400,*,RIGHT,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 3000,4000,4100,4000,400,*,RIGHT,ALU1 +S 3000,3900,4100,3900,400,*,RIGHT,ALU1 +S 3000,4000,3000,6100,400,*,DOWN,ALU1 +S 1000,2000,1000,7100,400,*,DOWN,ALU1 +S 2000,3000,2000,8000,400,*,UP,ALU1 +S 4000,5000,4000,7000,400,b,UP,CALU1 +S 3000,4000,3000,6000,400,a,UP,CALU1 +S 2000,8000,6300,8000,400,*,LEFT,ALU1 +S 4000,4800,4000,7100,400,*,UP,ALU1 +S 1000,5700,1000,6500,600,*,UP,PDIF +S 1200,5700,1200,7300,400,*,UP,PDIF +S 1600,5500,1600,7500,200,1z,UP,PTRANS +S 1600,7500,1600,7900,200,*,DOWN,POLY +S 2400,5700,2400,9200,1000,n2,DOWN,PDIF +S 3200,5500,3200,9400,200,1a,UP,PTRANS +S 3600,5700,3600,9200,600,n1,DOWN,PDIF +S 4000,5500,4000,9400,200,1b,UP,PTRANS +S 4400,5700,4400,9200,600,n2,DOWN,PDIF +S 4800,5500,4800,9400,200,1c,UP,PTRANS +S 5600,5500,5600,9400,200,1d,UP,PTRANS +S 5200,5700,5200,9200,600,n2,DOWN,PDIF +S 6000,5700,6000,9200,400,n3,UP,PDIF +S 5000,4000,5000,6000,400,c,UP,CALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 5000,7000,5000,7000,400,d,LEFT,CALU1 +S 6000,4000,6000,4000,400,c,LEFT,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 3000,7000,3000,7000,400,b,LEFT,CALU1 +V 1000,9300,CONT_BODY_N,* +V 6000,700,CONT_BODY_P,* +V 5000,700,CONT_BODY_P,* +V 6400,3000,CONT_DIF_N,* +V 5000,4000,CONT_POLY,* +V 5200,3000,CONT_DIF_N,zn +V 4000,1800,CONT_DIF_N,* +V 3000,3000,CONT_DIF_N,zn +V 1800,1000,CONT_DIF_N,* +V 600,3000,CONT_DIF_N,* +V 2400,9000,CONT_DIF_P,* +V 3000,4600,CONT_POLY,* +V 1000,6700,CONT_DIF_P,* +V 2000,4600,CONT_POLY,zn +V 6200,8000,CONT_DIF_P,zn +V 4000,4900,CONT_POLY,* +V 1000,5800,CONT_DIF_P,* +V 6000,4900,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/or4_x1.vbe b/pdks/symbolic/msxlib/cells/or4_x1.vbe new file mode 100644 index 000000000..7c861e3f7 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/or4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY or4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_d : NATURAL := 5; + CONSTANT rdown_b_z : NATURAL := 2400; + CONSTANT rdown_c_z : NATURAL := 2400; + CONSTANT rdown_a_z : NATURAL := 2400; + CONSTANT rdown_d_z : NATURAL := 2400; + CONSTANT rup_b_z : NATURAL := 2990; + CONSTANT rup_c_z : NATURAL := 2970; + CONSTANT rup_a_z : NATURAL := 3020; + CONSTANT rup_d_z : NATURAL := 2970; + CONSTANT tphh_d_z : NATURAL := 103; + CONSTANT tphh_c_z : NATURAL := 127; + CONSTANT tphh_b_z : NATURAL := 145; + CONSTANT tpll_a_z : NATURAL := 191; + CONSTANT tphh_a_z : NATURAL := 157; + CONSTANT tpll_b_z : NATURAL := 181; + CONSTANT tpll_d_z : NATURAL := 125; + CONSTANT tpll_c_z : NATURAL := 159; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END or4_x1; + +ARCHITECTURE behaviour_data_flow OF or4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on or4_x1" + SEVERITY WARNING; + z <= (((b or c) or a) or d) after 1200 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/powmid_x0.ap b/pdks/symbolic/msxlib/cells/powmid_x0.ap new file mode 100644 index 000000000..ce2c8fd51 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/powmid_x0.ap @@ -0,0 +1,23 @@ +V ALLIANCE : 6 +H powmid_x0,P, 4/ 1/2008,100 +A 0,0,7000,10000 +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,5000,7000,5000,10000,powmid_x0,LEFT,TALU8 +S 1000,600,6000,600,1200,vss,RIGHT,CALU2 +S 900,500,6100,500,1400,*,RIGHT,ALU2 +S 0,500,7000,500,1400,*,RIGHT,ALU1 +S 900,9500,6100,9500,1400,*,RIGHT,ALU2 +S 1000,9400,6000,9400,1200,vdd,RIGHT,CALU2 +S 0,9500,7000,9500,1400,*,RIGHT,ALU1 +S 5000,0,5000,10000,2400,vss,DOWN,CALU3 +S 2000,0,2000,10000,2400,vdd,DOWN,CALU3 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 5000,0,5000,10000,2400,*,UP,ALU3 +S 2000,0,2000,10000,2400,*,UP,ALU3 +B 2000,500,2300,1200,CONT_VIA,* +B 5000,500,2300,1200,CONT_VIA2,* +B 5000,9500,2300,1200,CONT_VIA,* +B 2000,9500,2300,1200,CONT_VIA2,* +EOF diff --git a/pdks/symbolic/msxlib/cells/powmid_x0.vbe b/pdks/symbolic/msxlib/cells/powmid_x0.vbe new file mode 100644 index 000000000..3d677efa0 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/powmid_x0.vbe @@ -0,0 +1,18 @@ +ENTITY powmid_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END powmid_x0; + +ARCHITECTURE behaviour_data_flow OF powmid_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on powmid_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/rowend_x0.ap b/pdks/symbolic/msxlib/cells/rowend_x0.ap new file mode 100644 index 000000000..8ebdfe470 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/rowend_x0.ap @@ -0,0 +1,9 @@ +V ALLIANCE : 6 +H rowend_x0,P,17/ 6/2004,100 +A 0,0,1000,10000 +S 0,9400,1000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,1000,600,1200,vss,RIGHT,CALU1 +S 0,7600,1000,7600,5600,*,LEFT,NWELL +S 0,2200,1000,2200,5200,*,LEFT,PWELL +S 0,5000,1000,5000,10000,rowend_x0,LEFT,TALU8 +EOF diff --git a/pdks/symbolic/msxlib/cells/rowend_x0.vbe b/pdks/symbolic/msxlib/cells/rowend_x0.vbe new file mode 100644 index 000000000..bb2015f9a --- /dev/null +++ b/pdks/symbolic/msxlib/cells/rowend_x0.vbe @@ -0,0 +1,18 @@ +ENTITY rowend_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END rowend_x0; + +ARCHITECTURE behaviour_data_flow OF rowend_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rowend_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/sff1_x4.ap b/pdks/symbolic/msxlib/cells/sff1_x4.ap new file mode 100644 index 000000000..7f0357302 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/sff1_x4.ap @@ -0,0 +1,234 @@ +V ALLIANCE : 6 +H sff1_x4,P,14/ 8/2014,100 +A 0,0,18000,10000 +R 16000,4000,ref_ref,q_40 +R 2000,8000,ref_ref,ck_80 +R 2000,7000,ref_ref,ck_70 +R 2000,6000,ref_ref,ck_60 +R 2000,5000,ref_ref,ck_50 +R 2000,4000,ref_ref,ck_40 +R 2000,3000,ref_ref,ck_30 +R 2000,2000,ref_ref,ck_20 +R 5000,7000,ref_ref,i_70 +R 5000,6000,ref_ref,i_60 +R 5000,5000,ref_ref,i_50 +R 5000,4000,ref_ref,i_40 +R 5000,3000,ref_ref,i_30 +R 6000,2000,ref_ref,i_20 +R 16000,8000,ref_ref,q_80 +R 16000,7000,ref_ref,q_70 +R 16000,6000,ref_ref,q_60 +R 16000,5000,ref_ref,q_50 +R 16000,3000,ref_ref,q_30 +R 16000,2000,ref_ref,q_20 +R 6000,8000,ref_ref,i_80 +R 15000,5000,ref_ref,q_50 +R 15000,3000,ref_ref,q_30 +S 9600,7500,9600,9400,200,*,DOWN,PTRANS +S 10000,7700,10000,9200,600,*,DOWN,PDIF +S 12800,700,13600,700,600,*,RIGHT,PTIE +S 6800,700,7600,700,600,*,RIGHT,PTIE +S 3200,700,4000,700,600,*,RIGHT,PTIE +S 14600,4000,16800,4000,600,sff_s,RIGHT,POLY +S 13800,4000,14900,4000,400,*,RIGHT,ALU1 +S 14400,4800,14400,7200,200,*,UP,POLY +S 4100,2000,4100,8000,400,*,DOWN,ALU1 +S 5100,8000,6100,8000,400,*,RIGHT,ALU1 +S 5100,2000,6100,2000,400,*,RIGHT,ALU1 +S 5100,2000,5100,8000,400,*,DOWN,ALU1 +S 600,6900,600,8100,400,*,DOWN,ALU1 +S 3000,1900,3000,7100,400,*,DOWN,ALU1 +S 9900,7000,11400,7000,400,*,LEFT,ALU1 +S 11400,1900,11400,8100,400,y,DOWN,ALU1 +S 14700,3000,16200,3000,400,*,RIGHT,ALU1 +S 14700,5000,16200,5000,400,*,RIGHT,ALU1 +S 15000,900,15000,2100,400,*,DOWN,ALU1 +S 17400,900,17400,2100,400,*,DOWN,ALU1 +S 15000,5900,15000,9100,400,*,DOWN,ALU1 +S 17400,5900,17400,9100,400,*,DOWN,ALU1 +S 9000,3000,10500,3000,400,*,LEFT,ALU1 +S 7700,2000,9000,2000,400,*,RIGHT,ALU1 +S 9900,2000,11400,2000,400,*,RIGHT,ALU1 +S 12600,4000,12600,7000,400,*,DOWN,ALU1 +S 9000,6000,10500,6000,400,*,RIGHT,ALU1 +S 0,9400,18000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,18000,600,1200,vss,RIGHT,CALU1 +S 13200,2800,13200,5000,200,*,DOWN,POLY +S 15600,2800,15600,5200,200,*,DOWN,POLY +S 14400,3000,15000,3000,600,*,RIGHT,POLY +S 14400,5000,15000,5000,600,*,RIGHT,POLY +S 16800,2800,16800,5200,200,*,DOWN,POLY +S 12000,2800,12000,4000,200,*,DOWN,POLY +S 10800,1800,10800,3000,200,*,UP,POLY +S 10800,6000,10800,7200,200,*,DOWN,POLY +S 12000,5000,12000,7200,200,*,DOWN,POLY +S 8400,2800,8400,4000,200,*,DOWN,POLY +S 11200,7700,11200,9200,600,*,DOWN,PDIF +S 10800,7500,10800,9400,200,*,UP,PTRANS +S 16200,5700,16200,9200,600,*,DOWN,PDIF +S 16800,5500,16800,9400,200,*,DOWN,PTRANS +S 17400,5700,17400,9200,600,*,DOWN,PDIF +S 15600,5500,15600,9400,200,*,DOWN,PTRANS +S 15000,5700,15000,9200,600,*,DOWN,PDIF +S 6000,7500,6000,9400,200,*,DOWN,PTRANS +S 10800,600,10800,1500,200,*,UP,NTRANS +S 11400,800,11400,1300,600,*,DOWN,NDIF +S 11400,800,11400,2300,600,*,DOWN,NDIF +S 16200,800,16200,2300,600,*,DOWN,NDIF +S 16800,600,16800,2500,200,*,UP,NTRANS +S 17400,800,17400,2300,600,*,DOWN,NDIF +S 15600,600,15600,2500,200,*,UP,NTRANS +S 9000,800,9000,2300,600,*,DOWN,NDIF +S 0,5000,18000,5000,10000,sff1_x4,RIGHT,TALU8 +S 0,2200,18000,2200,5200,*,RIGHT,PWELL +S 0,7600,18000,7600,5600,*,RIGHT,NWELL +S 1200,6600,1200,8600,200,*,DOWN,PTRANS +S 600,6800,600,8400,600,*,UP,PDIF +S 1800,6800,1800,9100,600,*,UP,PDIF +S 7000,2900,7000,5100,400,*,DOWN,ALU1 +S 1200,6000,1800,6000,600,*,RIGHT,POLY +S 12000,4000,12600,4000,600,*,RIGHT,POLY +S 7800,4000,8400,4000,600,*,RIGHT,POLY +S 10200,6000,10800,6000,600,*,RIGHT,POLY +S 12600,7000,13200,7000,600,*,RIGHT,POLY +S 9600,7000,10200,7000,600,*,RIGHT,POLY +S 10200,3000,10800,3000,600,*,RIGHT,POLY +S 9600,2000,10200,2000,600,*,RIGHT,POLY +S 4000,6000,6000,6000,200,*,RIGHT,POLY +S 3000,1700,3000,2300,600,*,DOWN,NDIF +S 2400,1500,2400,2500,200,*,UP,NTRANS +S 600,1900,600,7100,400,*,DOWN,ALU1 +S 2400,2800,2400,6200,200,*,DOWN,POLY +S 1200,3000,1800,3000,600,*,RIGHT,POLY +S 600,5000,13200,5000,200,nckr,RIGHT,POLY +S 3200,4000,12000,4000,200,ckr,RIGHT,POLY +S 6900,6000,8000,6000,400,*,RIGHT,ALU1 +S 7800,6800,7800,8400,600,*,UP,PDIF +S 8400,5000,8400,6200,200,*,DOWN,POLY +S 8000,3900,8000,6000,400,*,UP,ALU1 +S 9000,6700,9000,9200,600,*,UP,PDIF +S 6000,6200,6000,7200,200,*,UP,POLY +S 6000,2900,6000,6100,400,u,DOWN,ALU1 +S 7700,7000,9000,7000,400,*,RIGHT,ALU1 +S 13800,2000,13800,8000,400,*,DOWN,ALU1 +S 9000,2000,9000,7000,400,sff_m,DOWN,ALU1 +S 6600,6800,6600,9200,600,*,UP,PDIF +S 7200,6600,7200,8600,200,*,DOWN,PTRANS +S 8400,1500,8400,2500,200,*,UP,NTRANS +S 12000,1500,12000,2500,200,*,UP,NTRANS +S 12000,7500,12000,9400,200,*,DOWN,PTRANS +S 14400,7500,14400,9400,200,*,DOWN,PTRANS +S 13200,1500,13200,2500,200,*,UP,NTRANS +S 12600,1700,12600,2300,600,*,DOWN,NDIF +S 12500,2000,13800,2000,400,*,RIGHT,ALU1 +S 12500,8000,13800,8000,400,*,RIGHT,ALU1 +S 16000,2000,16000,8000,400,q,DOWN,CALU1 +S 2000,2000,2000,8000,400,ck,DOWN,CALU1 +S 2000,1900,2000,8100,400,*,DOWN,ALU1 +S 1500,6000,2000,6000,400,*,RIGHT,ALU1 +S 1500,3000,2000,3000,400,*,RIGHT,ALU1 +S 5000,3000,5000,7000,400,i,DOWN,CALU1 +S 6000,8000,6000,8000,400,i,LEFT,CALU1 +S 6000,2000,6000,2000,400,i,LEFT,CALU1 +S 16000,1900,16000,8100,400,*,DOWN,ALU1 +S 5000,2900,5000,7100,400,*,DOWN,ALU1 +S 4100,8000,4300,8000,400,*,RIGHT,ALU1 +S 4100,2000,4300,2000,400,*,RIGHT,ALU1 +S 3900,6000,4100,6000,400,*,RIGHT,ALU1 +S 3100,4000,3300,4000,400,*,RIGHT,ALU1 +S 16100,8000,16300,8000,400,*,RIGHT,ALU1 +S 16100,7000,16300,7000,400,*,RIGHT,ALU1 +S 16100,6000,16300,6000,400,*,RIGHT,ALU1 +S 16100,2000,16300,2000,400,*,RIGHT,ALU1 +S 12700,7000,12900,7000,400,*,RIGHT,ALU1 +S 12300,4000,12500,4000,400,*,RIGHT,ALU1 +S 15000,5000,15000,5000,400,q,LEFT,CALU1 +S 15000,3000,15000,3000,400,q,LEFT,CALU1 +S 2400,6600,2400,8600,200,*,DOWN,PTRANS +S 3000,6800,3000,8400,600,*,UP,PDIF +S 8400,6600,8400,8600,200,*,DOWN,PTRANS +S 14400,1500,14400,2500,200,*,UP,NTRANS +S 15000,800,15000,2300,600,*,DOWN,NDIF +S 13800,1700,13800,2300,600,*,DOWN,NDIF +S 9600,600,9600,1500,200,*,UP,NTRANS +S 10200,800,10200,1300,600,*,DOWN,NDIF +S 1800,1000,1800,2300,600,*,DOWN,NDIF +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 600,1700,600,2300,600,*,DOWN,NDIF +S 4800,7500,4800,9400,200,*,DOWN,PTRANS +S 5400,7700,5400,9200,600,*,UP,PDIF +S 4200,7700,4200,9200,600,*,UP,PDIF +S 13200,7500,13200,9400,200,*,DOWN,PTRANS +S 12600,7700,12600,9200,600,*,DOWN,PDIF +S 13800,7700,13800,9200,600,*,UP,PDIF +S 7200,1500,7200,2500,200,*,UP,NTRANS +S 7800,1700,7800,2300,600,*,DOWN,NDIF +S 6600,1700,6600,2300,600,*,DOWN,NDIF +S 6000,1500,6000,2500,200,*,UP,NTRANS +S 5400,900,5400,2300,600,*,DOWN,NDIF +S 4800,1500,4800,2500,200,*,UP,NTRANS +S 4200,1700,4200,2300,600,*,DOWN,NDIF +V 13800,700,CONT_BODY_P,* +V 12600,700,CONT_BODY_P,* +V 7800,700,CONT_BODY_P,* +V 6600,700,CONT_BODY_P,* +V 4200,700,CONT_BODY_P,* +V 3000,700,CONT_BODY_P,* +V 14800,4000,CONT_POLY,* +V 600,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 10000,7000,CONT_POLY,* +V 14800,5000,CONT_POLY,* +V 14800,3000,CONT_POLY,* +V 10400,3000,CONT_POLY,* +V 12400,4000,CONT_POLY,* +V 10400,6000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +V 10000,2000,CONT_POLY,* +V 12800,7000,CONT_POLY,* +V 12600,8000,CONT_DIF_P,* +V 10200,9000,CONT_DIF_P,* +V 11400,8000,CONT_DIF_P,* +V 17400,6000,CONT_DIF_P,* +V 16200,6000,CONT_DIF_P,* +V 15000,6000,CONT_DIF_P,* +V 15000,7000,CONT_DIF_P,* +V 15000,8000,CONT_DIF_P,* +V 17400,9000,CONT_DIF_P,* +V 15000,9000,CONT_DIF_P,* +V 17400,8000,CONT_DIF_P,* +V 17400,7000,CONT_DIF_P,* +V 5400,9000,CONT_DIF_P,* +V 12600,2000,CONT_DIF_N,* +V 10200,1000,CONT_DIF_N,* +V 7800,2000,CONT_DIF_N,* +V 11400,2000,CONT_DIF_N,* +V 17400,1000,CONT_DIF_N,* +V 15000,1000,CONT_DIF_N,* +V 17400,2000,CONT_DIF_N,* +V 15000,2000,CONT_DIF_N,* +V 16200,2000,CONT_DIF_N,* +V 5400,1000,CONT_DIF_N,* +V 4200,2000,CONT_DIF_N,* +V 1800,1000,CONT_DIF_N,* +V 600,7000,CONT_DIF_P,* +V 1800,9000,CONT_DIF_P,* +V 1600,6000,CONT_POLY,* +V 600,5000,CONT_POLY,* +V 3200,4000,CONT_POLY,* +V 4000,6000,CONT_POLY,* +V 5000,7000,CONT_POLY,* +V 5000,3000,CONT_POLY,* +V 6000,3000,CONT_POLY,* +V 6000,6000,CONT_POLY,* +V 7000,5000,CONT_POLY,* +V 7000,3000,CONT_POLY,* +V 600,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 1600,3000,CONT_POLY,* +V 16200,8000,CONT_DIF_P,* +V 16200,7000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,* +V 7000,6000,CONT_POLY,* +V 7800,7000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/sff1_x4.vbe b/pdks/symbolic/msxlib/cells/sff1_x4.vbe new file mode 100644 index 000000000..4756bfddd --- /dev/null +++ b/pdks/symbolic/msxlib/cells/sff1_x4.vbe @@ -0,0 +1,39 @@ +ENTITY sff1_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tsr_i_ck : NATURAL := 476; + CONSTANT transistors : NATURAL := 26 +); +PORT ( + ck : in BIT; + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff1_x4; + +ARCHITECTURE VBE OF sff1_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff1_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED i; + END BLOCK label0; + + q <= sff_m after 1700 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/sff2_x4.ap b/pdks/symbolic/msxlib/cells/sff2_x4.ap new file mode 100644 index 000000000..1cc235be6 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/sff2_x4.ap @@ -0,0 +1,276 @@ +V ALLIANCE : 6 +H sff2_x4,P,14/ 8/2014,100 +A 0,0,24000,10000 +R 9000,2000,ref_ref,ck_20 +R 9000,7000,ref_ref,ck_70 +R 9000,6000,ref_ref,ck_60 +R 9000,5000,ref_ref,ck_50 +R 9000,4000,ref_ref,ck_40 +R 9000,3000,ref_ref,ck_30 +R 2000,3000,ref_ref,i0_30 +R 2000,4000,ref_ref,i0_40 +R 2000,5000,ref_ref,i0_50 +R 2000,7000,ref_ref,i0_70 +R 2000,6000,ref_ref,i0_60 +R 2000,8000,ref_ref,i0_80 +R 6000,2000,ref_ref,i1_20 +R 6000,3000,ref_ref,i1_30 +R 6000,4000,ref_ref,i1_40 +R 6000,5000,ref_ref,i1_50 +R 6000,6000,ref_ref,i1_60 +R 6000,7000,ref_ref,i1_70 +R 3000,5000,ref_ref,cmd_50 +R 3000,6000,ref_ref,cmd_60 +R 3000,7000,ref_ref,cmd_70 +R 3000,8000,ref_ref,cmd_80 +R 22000,2000,ref_ref,q_20 +R 22000,3000,ref_ref,q_30 +R 22000,5000,ref_ref,q_50 +R 22000,6000,ref_ref,q_60 +R 22000,7000,ref_ref,q_70 +R 22000,8000,ref_ref,q_80 +R 22000,4000,ref_ref,q_40 +R 21000,5000,ref_ref,q_50 +R 21000,3000,ref_ref,q_30 +S 3200,9300,4800,9300,600,*,RIGHT,NTIE +S 18800,700,19600,700,600,*,RIGHT,PTIE +S 12800,700,13600,700,600,*,RIGHT,PTIE +S 3200,700,4800,700,600,*,RIGHT,PTIE +S 22000,1900,22000,8100,400,*,DOWN,ALU1 +S 20400,1500,20400,2400,200,*,UP,NTRANS +S 19200,1500,19200,2500,200,*,UP,NTRANS +S 20400,7500,20400,9400,200,*,DOWN,PTRANS +S 19200,7600,19200,9400,200,*,DOWN,PTRANS +S 18000,7500,18000,9400,200,*,DOWN,PTRANS +S 18000,1500,18000,2500,200,*,UP,NTRANS +S 15600,600,15600,1400,200,*,UP,NTRANS +S 14400,1500,14400,2500,200,*,UP,NTRANS +S 15600,7600,15600,9400,200,*,DOWN,PTRANS +S 14400,6500,14400,8500,200,*,DOWN,PTRANS +S 13200,6600,13200,8600,200,*,DOWN,PTRANS +S 13200,1500,13200,2400,200,*,UP,NTRANS +S 0,5000,24000,5000,10000,sff2_x4,RIGHT,TALU8 +S 0,2200,24000,2200,5200,*,RIGHT,PWELL +S 0,7600,24000,7600,5600,*,RIGHT,NWELL +S 1800,900,1800,2200,600,*,UP,NDIF +S 600,1700,600,2300,600,*,UP,NDIF +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 2400,1500,2400,2400,200,*,UP,NTRANS +S 5000,1500,5000,2400,200,*,UP,NTRANS +S 3800,1700,3800,2200,600,*,UP,NDIF +S 3200,1500,3200,2400,200,*,UP,NTRANS +S 6400,900,6400,2200,600,*,UP,NDIF +S 5800,1500,5800,2400,200,*,UP,NTRANS +S 4200,1700,4200,3100,1000,*,DOWN,NDIF +S 9600,1500,9600,2500,200,*,UP,NTRANS +S 9000,900,9000,2200,600,*,DOWN,NDIF +S 7800,1600,7800,2200,600,*,DOWN,NDIF +S 8400,1400,8400,2400,200,*,UP,NTRANS +S 10200,1700,10200,2300,600,*,DOWN,NDIF +S 16200,800,16200,1200,600,*,DOWN,NDIF +S 17400,800,17400,1300,600,*,DOWN,NDIF +S 16800,600,16800,1500,200,*,UP,NTRANS +S 23400,800,23400,2300,600,*,DOWN,NDIF +S 22800,600,22800,2500,200,*,UP,NTRANS +S 22200,800,22200,2300,600,*,DOWN,NDIF +S 21000,800,21000,2200,600,*,DOWN,NDIF +S 17400,800,17400,2300,600,*,DOWN,NDIF +S 18600,1700,18600,2300,600,*,DOWN,NDIF +S 21600,600,21600,2500,200,*,UP,NTRANS +S 19800,1700,19800,2200,600,*,DOWN,NDIF +S 11400,900,11400,2200,600,*,DOWN,NDIF +S 12000,1500,12000,2400,200,*,UP,NTRANS +S 12600,1700,12600,2200,600,*,DOWN,NDIF +S 15000,800,15000,2300,600,*,DOWN,NDIF +S 13800,1700,13800,2200,600,*,DOWN,NDIF +S 2400,6600,2400,8500,200,*,DOWN,PTRANS +S 1800,6800,1800,9100,600,*,DOWN,PDIF +S 600,6700,600,8300,600,*,DOWN,PDIF +S 1200,6500,1200,8500,200,*,DOWN,PTRANS +S 5800,6600,5800,8500,200,*,DOWN,PTRANS +S 4000,6800,4000,8300,1000,*,DOWN,PDIF +S 3200,6600,3200,8500,200,*,DOWN,PTRANS +S 6400,6800,6400,9100,600,*,DOWN,PDIF +S 5000,6600,5000,8500,200,*,DOWN,PTRANS +S 10200,6700,10200,8300,600,*,UP,PDIF +S 9600,6500,9600,8500,200,*,DOWN,PTRANS +S 8400,6600,8400,8600,200,*,DOWN,PTRANS +S 7800,6800,7800,8400,600,*,UP,PDIF +S 16000,7800,16000,9200,600,*,DOWN,PDIF +S 18600,7800,18600,9200,600,*,DOWN,PDIF +S 17200,7700,17200,9200,600,*,DOWN,PDIF +S 9000,6800,9000,9100,600,*,UP,PDIF +S 23400,5700,23400,9200,600,*,DOWN,PDIF +S 22800,5500,22800,9400,200,*,DOWN,PTRANS +S 22200,5700,22200,9200,600,*,DOWN,PDIF +S 16800,7500,16800,9400,200,*,UP,PTRANS +S 19800,7800,19800,9200,600,*,UP,PDIF +S 12000,7600,12000,9400,200,*,DOWN,PTRANS +S 21000,5700,21000,9200,600,*,DOWN,PDIF +S 21600,5500,21600,9400,200,*,DOWN,PTRANS +S 15000,6700,15000,9200,600,*,UP,PDIF +S 13800,6800,13800,8400,600,*,UP,PDIF +S 12600,6800,12600,9200,600,*,UP,PDIF +S 11400,7800,11400,9200,600,*,UP,PDIF +S 15600,2000,16200,2000,600,*,RIGHT,POLY +S 16800,1800,16800,3000,200,*,UP,POLY +S 1200,5000,5000,5000,200,*,RIGHT,POLY +S 1200,2800,1200,6200,200,*,DOWN,POLY +S 1800,3000,2400,3000,600,*,RIGHT,POLY +S 1800,6000,2400,6000,600,*,RIGHT,POLY +S 5000,2800,5000,5000,200,*,DOWN,POLY +S 3200,2800,3200,4000,200,*,DOWN,POLY +S 3200,5000,3200,6200,200,*,DOWN,POLY +S 8400,6000,9000,6000,600,*,RIGHT,POLY +S 10200,4000,18000,4000,200,ckr,RIGHT,POLY +S 7800,5000,19200,5000,200,nckr,RIGHT,POLY +S 20400,5000,21000,5000,600,*,RIGHT,POLY +S 20400,3000,21000,3000,600,*,RIGHT,POLY +S 21600,2800,21600,5200,200,*,DOWN,POLY +S 19200,2800,19200,5000,200,*,DOWN,POLY +S 9600,2800,9600,6200,200,*,DOWN,POLY +S 8400,3000,9000,3000,600,*,RIGHT,POLY +S 13800,4000,14400,4000,600,*,RIGHT,POLY +S 18000,4000,18600,4000,600,*,RIGHT,POLY +S 14400,2800,14400,4000,200,*,DOWN,POLY +S 18000,5000,18000,7200,200,*,DOWN,POLY +S 16800,6000,16800,7200,200,*,DOWN,POLY +S 18000,2800,18000,4000,200,*,DOWN,POLY +S 22800,2800,22800,5200,200,*,DOWN,POLY +S 14400,5000,14400,6200,200,*,DOWN,POLY +S 16200,3000,16800,3000,600,*,RIGHT,POLY +S 15600,7000,16200,7000,600,*,RIGHT,POLY +S 18600,7000,19200,7000,600,*,RIGHT,POLY +S 16200,6000,16800,6000,600,*,RIGHT,POLY +S 0,600,24000,600,1200,vss,RIGHT,CALU1 +S 600,2000,5000,2000,400,*,RIGHT,ALU1 +S 600,1900,600,7100,400,*,DOWN,ALU1 +S 9000,1900,9000,7100,400,*,DOWN,ALU1 +S 10200,1900,10200,7100,400,*,DOWN,ALU1 +S 5000,2000,5000,6100,400,*,DOWN,ALU1 +S 3000,2000,3000,4100,400,*,UP,ALU1 +S 17400,1900,17400,8100,400,y,DOWN,ALU1 +S 6000,1900,6000,7100,400,*,DOWN,ALU1 +S 7800,1900,7800,7100,400,*,DOWN,ALU1 +S 15900,2000,17400,2000,400,*,RIGHT,ALU1 +S 13700,2000,15000,2000,400,*,RIGHT,ALU1 +S 18500,2000,19800,2000,400,*,RIGHT,ALU1 +S 23400,900,23400,2100,400,*,DOWN,ALU1 +S 21000,900,21000,2100,400,*,DOWN,ALU1 +S 0,9400,24000,9400,1200,vdd,RIGHT,CALU1 +S 2000,2900,2000,8100,400,*,DOWN,ALU1 +S 4000,8000,12000,8000,400,*,RIGHT,ALU1 +S 3000,4900,3000,8100,400,*,DOWN,ALU1 +S 4000,2900,4000,8000,400,*,DOWN,ALU1 +S 15900,7000,17400,7000,400,*,LEFT,ALU1 +S 23400,5900,23400,9100,400,*,DOWN,ALU1 +S 21000,5900,21000,9100,400,*,DOWN,ALU1 +S 20700,5000,22200,5000,400,*,RIGHT,ALU1 +S 20700,3000,22200,3000,400,*,RIGHT,ALU1 +S 15000,6000,16500,6000,400,*,RIGHT,ALU1 +S 18600,4000,18600,7000,400,*,DOWN,ALU1 +S 15000,3000,16500,3000,400,*,LEFT,ALU1 +S 18500,8000,19800,8000,400,*,RIGHT,ALU1 +S 13700,7000,15000,7000,400,*,RIGHT,ALU1 +S 12000,2900,12000,8000,400,u,DOWN,ALU1 +S 14000,3900,14000,6000,400,*,UP,ALU1 +S 12900,6000,14000,6000,400,*,RIGHT,ALU1 +S 13000,2900,13000,5100,400,*,DOWN,ALU1 +S 15000,2000,15000,7000,400,sff_m,DOWN,ALU1 +S 19800,2000,19800,8000,400,sff_s,DOWN,ALU1 +S 20400,4800,20400,7200,200,*,DOWN,POLY +S 19800,4000,20900,4000,400,*,RIGHT,ALU1 +S 20800,4000,22800,4000,600,*,RIGHT,POLY +S 9000,2000,9000,7000,400,ck,DOWN,CALU1 +S 2000,3000,2000,8000,400,i0,DOWN,CALU1 +S 6000,2000,6000,7000,400,i1,DOWN,CALU1 +S 3000,5000,3000,8000,400,cmd,DOWN,CALU1 +S 22000,2000,22000,8000,400,q,DOWN,CALU1 +S 8700,6000,8900,6000,400,*,RIGHT,ALU1 +S 8700,3000,8900,3000,400,*,RIGHT,ALU1 +S 7900,5000,8100,5000,400,*,RIGHT,ALU1 +S 22100,8000,22300,8000,400,*,RIGHT,ALU1 +S 22100,7000,22300,7000,400,*,RIGHT,ALU1 +S 22100,6000,22300,6000,400,*,RIGHT,ALU1 +S 22100,2000,22300,2000,400,*,RIGHT,ALU1 +S 18700,7000,18900,7000,400,*,RIGHT,ALU1 +S 18300,4000,18500,4000,400,*,RIGHT,ALU1 +S 11700,7000,11900,7000,400,*,RIGHT,ALU1 +S 10300,4000,10500,4000,400,*,RIGHT,ALU1 +S 21000,5000,21000,5000,400,q,LEFT,CALU1 +S 21000,3000,21000,3000,400,q,LEFT,CALU1 +V 5000,9300,CONT_BODY_N,* +V 3000,9300,CONT_BODY_N,* +V 19800,700,CONT_BODY_P,* +V 18600,700,CONT_BODY_P,* +V 13800,700,CONT_BODY_P,* +V 12600,700,CONT_BODY_P,* +V 5000,700,CONT_BODY_P,* +V 3000,700,CONT_BODY_P,* +V 8000,5000,CONT_POLY,* +V 1800,1000,CONT_DIF_N,* +V 600,2000,CONT_DIF_N,* +V 6400,1000,CONT_DIF_N,* +V 18600,2000,CONT_DIF_N,* +V 10200,2000,CONT_DIF_N,* +V 9000,1000,CONT_DIF_N,* +V 7800,2000,CONT_DIF_N,* +V 22200,2000,CONT_DIF_N,* +V 21000,2000,CONT_DIF_N,* +V 23400,2000,CONT_DIF_N,* +V 21000,1000,CONT_DIF_N,* +V 23400,1000,CONT_DIF_N,* +V 17400,2000,CONT_DIF_N,* +V 13800,2000,CONT_DIF_N,* +V 16200,1000,CONT_DIF_N,* +V 11400,1000,CONT_DIF_N,* +V 4000,3000,CONT_DIF_N,* +V 1800,9000,CONT_DIF_P,* +V 600,7000,CONT_DIF_P,* +V 7800,7000,CONT_DIF_P,* +V 10200,7000,CONT_DIF_P,* +V 6400,9000,CONT_DIF_P,* +V 21000,6000,CONT_DIF_P,* +V 22200,6000,CONT_DIF_P,* +V 23400,6000,CONT_DIF_P,* +V 17400,8000,CONT_DIF_P,* +V 16200,9000,CONT_DIF_P,* +V 18600,8000,CONT_DIF_P,* +V 9000,9000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 22200,8000,CONT_DIF_P,* +V 11400,9000,CONT_DIF_P,* +V 23400,7000,CONT_DIF_P,* +V 23400,8000,CONT_DIF_P,* +V 21000,9000,CONT_DIF_P,* +V 23400,9000,CONT_DIF_P,* +V 21000,8000,CONT_DIF_P,* +V 21000,7000,CONT_DIF_P,* +V 13800,7000,CONT_DIF_P,* +V 22200,7000,CONT_DIF_P,* +V 16000,2000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 2000,6000,CONT_POLY,* +V 5000,6000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 16000,7000,CONT_POLY,* +V 8800,3000,CONT_POLY,* +V 8800,6000,CONT_POLY,* +V 6000,3000,CONT_POLY,* +V 10400,4000,CONT_POLY,* +V 11800,7000,CONT_POLY,* +V 18800,7000,CONT_POLY,* +V 14000,4000,CONT_POLY,* +V 16400,6000,CONT_POLY,* +V 18400,4000,CONT_POLY,* +V 16400,3000,CONT_POLY,* +V 20800,3000,CONT_POLY,* +V 20800,5000,CONT_POLY,* +V 13000,6000,CONT_POLY,* +V 13000,3000,CONT_POLY,* +V 13000,5000,CONT_POLY,* +V 12000,3000,CONT_POLY,* +V 6000,6000,CONT_POLY,* +V 20800,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/sff2_x4.vbe b/pdks/symbolic/msxlib/cells/sff2_x4.vbe new file mode 100644 index 000000000..59eaa6446 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/sff2_x4.vbe @@ -0,0 +1,51 @@ +ENTITY sff2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd : NATURAL := 16; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 7; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_cmd_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thr_cmd_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT tsf_cmd_ck : NATURAL := 833; + CONSTANT tsf_i0_ck : NATURAL := 764; + CONSTANT tsf_i1_ck : NATURAL := 764; + CONSTANT tsr_cmd_ck : NATURAL := 770; + CONSTANT tsr_i0_ck : NATURAL := 666; + CONSTANT tsr_i1_ck : NATURAL := 666; + CONSTANT transistors : NATURAL := 34 +); +PORT ( + ck : in BIT; + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff2_x4; + +ARCHITECTURE VBE OF sff2_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff2_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd))); + END BLOCK label0; + + q <= sff_m after 2000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/sff3_x4.ap b/pdks/symbolic/msxlib/cells/sff3_x4.ap new file mode 100644 index 000000000..7f7d58569 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/sff3_x4.ap @@ -0,0 +1,358 @@ +V ALLIANCE : 6 +H sff3_x4,P,14/ 8/2014,100 +A 0,0,28000,10000 +R 9000,5000,ref_ref,i0_50 +R 8000,6000,ref_ref,i0_60 +R 8000,4000,ref_ref,i0_40 +R 7000,6000,ref_ref,cmd0_60 +R 7000,5000,ref_ref,cmd0_50 +R 7000,4000,ref_ref,cmd0_40 +R 5000,5000,ref_ref,i1_50 +R 3000,5000,ref_ref,i2_50 +R 1000,7000,ref_ref,cmd1_70 +R 1000,6000,ref_ref,cmd1_60 +R 1000,5000,ref_ref,cmd1_50 +R 1000,4000,ref_ref,cmd1_40 +R 1000,3000,ref_ref,cmd1_30 +R 26000,7000,ref_ref,q_70 +R 26000,8000,ref_ref,q_80 +R 26000,4000,ref_ref,q_40 +R 26000,3000,ref_ref,q_30 +R 26000,5000,ref_ref,q_50 +R 26000,6000,ref_ref,q_60 +R 26000,2000,ref_ref,q_20 +R 12000,4000,ref_ref,ck_40 +R 12000,3000,ref_ref,ck_30 +R 12000,5000,ref_ref,ck_50 +R 12000,6000,ref_ref,ck_60 +R 12000,7000,ref_ref,ck_70 +R 12000,2000,ref_ref,ck_20 +R 25000,5000,ref_ref,q_50 +R 25000,3000,ref_ref,q_30 +S 16600,9300,17800,9300,600,*,RIGHT,NTIE +S 12800,9300,14200,9300,600,*,RIGHT,NTIE +S 22800,700,23600,700,600,*,RIGHT,PTIE +S 16800,700,17600,700,600,*,RIGHT,PTIE +S 12800,700,14200,700,600,*,RIGHT,PTIE +S 8800,6000,9200,6000,600,*,RIGHT,POLY +S 8800,4000,9200,4000,600,*,RIGHT,POLY +S 3600,7000,4000,7000,600,*,RIGHT,POLY +S 3600,3000,4000,3000,600,*,RIGHT,POLY +S 26000,1900,26000,8100,400,*,DOWN,ALU1 +S 8000,4000,8000,4000,400,i0,LEFT,CALU1 +S 8000,6000,8000,6000,400,i0,LEFT,CALU1 +S 9000,5000,9000,5000,400,i0,LEFT,CALU1 +S 7000,4000,7000,6000,400,cmd0,DOWN,CALU1 +S 5000,5000,5000,5000,400,i1,LEFT,CALU1 +S 3000,5000,3000,5000,400,i2,LEFT,CALU1 +S 1000,3000,1000,7000,400,cmd1,DOWN,CALU1 +S 26000,2000,26000,8000,400,q,DOWN,CALU1 +S 12000,2000,12000,7000,400,ck,DOWN,CALU1 +S 7000,5000,7900,5000,400,*,RIGHT,ALU1 +S 9800,3000,9800,3500,400,*,DOWN,ALU1 +S 7900,6000,8800,6000,400,*,RIGHT,ALU1 +S 7900,4000,8800,4000,400,*,RIGHT,ALU1 +S 7000,3900,7000,6100,400,*,DOWN,ALU1 +S 8800,3900,8800,6100,400,*,UP,ALU1 +S 1000,7900,1000,9100,400,*,UP,ALU1 +S 2100,2000,6700,2000,400,*,RIGHT,ALU1 +S 7000,3000,7000,7200,200,*,UP,POLY +S 7000,7200,7200,7200,200,*,RIGHT,POLY +S 8800,6000,9200,6000,200,*,RIGHT,POLY +S 9200,6000,9200,7200,200,*,UP,POLY +S 8000,3800,8000,6600,200,*,DOWN,POLY +S 9000,4000,9200,4000,200,*,RIGHT,POLY +S 9200,2200,9200,4000,200,*,DOWN,POLY +S 8400,2200,8400,3000,200,*,UP,POLY +S 10400,4000,10400,5200,200,*,DOWN,POLY +S 8000,7200,8400,7200,200,*,LEFT,POLY +S 8000,6600,8000,7200,200,*,UP,POLY +S 6000,2600,6000,7200,200,*,DOWN,POLY +S 7200,2200,7600,2200,200,*,RIGHT,POLY +S 6600,3000,6800,3000,200,*,LEFT,POLY +S 8000,5000,10400,5000,200,*,RIGHT,POLY +S 7600,2200,7600,3800,200,*,DOWN,POLY +S 7600,3800,8000,3800,200,*,LEFT,POLY +S 4000,4000,4000,7200,200,*,DOWN,POLY +S 1000,5000,1600,5000,600,*,RIGHT,POLY +S 3600,3000,4000,3000,200,*,RIGHT,POLY +S 5200,6000,5200,7200,200,*,UP,POLY +S 5200,2600,5200,4000,200,*,UP,POLY +S 4000,2600,4000,3000,200,*,DOWN,POLY +S 2800,2600,2800,7200,200,*,DOWN,POLY +S 5000,5000,6000,5000,200,*,RIGHT,POLY +S 4000,4000,5200,4000,200,*,RIGHT,POLY +S 9800,3100,9800,3300,600,*,DOWN,NDIF +S 10400,2900,10400,3700,200,*,DOWN,NTRANS +S 6600,800,6600,2100,600,*,DOWN,NDIF +S 9200,700,9200,1900,200,*,UP,NTRANS +S 9800,1100,9800,1900,600,*,UP,NDIF +S 7200,600,7200,1800,200,*,UP,NTRANS +S 7800,800,7800,1600,400,*,DOWN,NDIF +S 8400,700,8400,1900,200,*,UP,NTRANS +S 4000,1100,4000,2300,200,*,UP,NTRANS +S 5200,1100,5200,2300,200,*,UP,NTRANS +S 6000,1100,6000,2300,200,*,UP,NTRANS +S 2800,1100,2800,2300,200,*,UP,NTRANS +S 2200,1300,2200,1900,600,*,DOWN,NDIF +S 3400,1300,3400,2100,400,*,DOWN,NDIF +S 4600,1300,4600,3100,600,*,UP,NDIF +S 9800,7800,9800,9200,600,*,UP,PDIF +S 7800,7800,7800,9200,400,*,UP,PDIF +S 9200,7600,9200,9400,200,*,UP,PTRANS +S 6600,7800,6600,9200,400,*,UP,PDIF +S 9800,5700,9800,6700,600,*,UP,PDIF +S 10400,5500,10400,6900,200,*,UP,PTRANS +S 8400,7600,8400,9400,200,*,UP,PTRANS +S 7200,7600,7200,9400,200,*,UP,PTRANS +S 6000,7500,6000,9400,200,*,UP,PTRANS +S 5200,7500,5200,9400,200,*,UP,PTRANS +S 2200,5800,2200,6800,600,*,UP,PDIF +S 1600,5600,1600,7000,200,*,UP,PTRANS +S 1000,5800,1000,7900,600,*,UP,PDIF +S 4000,7600,4000,9400,200,*,UP,PTRANS +S 4600,7100,4600,9200,600,*,UP,PDIF +S 3400,7800,3400,9200,400,*,DOWN,PDIF +S 2800,7500,2800,9400,200,*,UP,PTRANS +S 2200,7700,2200,9200,600,*,UP,PDIF +S 27400,5900,27400,9100,400,*,DOWN,ALU1 +S 25000,5900,25000,9100,400,*,DOWN,ALU1 +S 27400,900,27400,2100,400,*,DOWN,ALU1 +S 25000,900,25000,2100,400,*,DOWN,ALU1 +S 24400,5000,25000,5000,600,*,RIGHT,POLY +S 24400,3000,25000,3000,600,*,RIGHT,POLY +S 25600,2800,25600,5200,200,*,DOWN,POLY +S 23200,2800,23200,5000,200,*,DOWN,POLY +S 17800,4000,18400,4000,600,*,RIGHT,POLY +S 22000,4000,22600,4000,600,*,RIGHT,POLY +S 18400,2800,18400,4000,200,*,DOWN,POLY +S 22000,5000,22000,7200,200,*,DOWN,POLY +S 20800,6000,20800,7200,200,*,DOWN,POLY +S 22000,2800,22000,4000,200,*,DOWN,POLY +S 20200,3000,20800,3000,600,*,RIGHT,POLY +S 19600,7000,20200,7000,600,*,RIGHT,POLY +S 22600,7000,23200,7000,600,*,RIGHT,POLY +S 20200,6000,20800,6000,600,*,RIGHT,POLY +S 24400,4800,24400,7200,200,*,DOWN,POLY +S 24800,4000,26800,4000,600,*,RIGHT,POLY +S 26800,2800,26800,5200,200,*,DOWN,POLY +S 18400,5000,18400,6200,200,*,DOWN,POLY +S 14200,6200,14800,6200,200,*,RIGHT,POLY +S 14200,2800,14800,2800,200,*,RIGHT,POLY +S 14200,2800,14200,6200,200,*,DOWN,POLY +S 15000,4000,22000,4000,200,ckr,RIGHT,POLY +S 19600,2000,20200,2000,600,*,RIGHT,POLY +S 20800,1800,20800,3000,200,*,UP,POLY +S 17200,1500,17200,2400,200,*,UP,NTRANS +S 24400,1500,24400,2400,200,*,UP,NTRANS +S 23200,1500,23200,2500,200,*,UP,NTRANS +S 22000,1500,22000,2500,200,*,UP,NTRANS +S 19600,600,19600,1400,200,*,UP,NTRANS +S 18400,1500,18400,2500,200,*,UP,NTRANS +S 21400,800,21400,1300,600,*,DOWN,NDIF +S 20800,600,20800,1500,200,*,UP,NTRANS +S 25000,800,25000,2200,600,*,DOWN,NDIF +S 21400,800,21400,2300,600,*,DOWN,NDIF +S 22600,1700,22600,2300,600,*,DOWN,NDIF +S 25600,600,25600,2500,200,*,UP,NTRANS +S 14200,1700,14200,2200,600,*,DOWN,NDIF +S 20200,800,20200,1200,600,*,DOWN,NDIF +S 16600,1700,16600,2200,600,*,DOWN,NDIF +S 19000,800,19000,2300,600,*,DOWN,NDIF +S 17800,1700,17800,2200,600,*,DOWN,NDIF +S 27400,800,27400,2300,600,*,DOWN,NDIF +S 26800,600,26800,2500,200,*,UP,NTRANS +S 26200,800,26200,2300,600,*,DOWN,NDIF +S 23800,1700,23800,2200,600,*,DOWN,NDIF +S 15400,900,15400,2200,600,*,DOWN,NDIF +S 16000,1500,16000,2400,200,*,UP,NTRANS +S 14800,1500,14800,2400,200,*,UP,NTRANS +S 22000,7500,22000,9400,200,*,DOWN,PTRANS +S 19600,7600,19600,9400,200,*,DOWN,PTRANS +S 18400,6500,18400,8500,200,*,DOWN,PTRANS +S 24400,7500,24400,9400,200,*,DOWN,PTRANS +S 23200,7600,23200,9400,200,*,DOWN,PTRANS +S 27400,5700,27400,9200,600,*,DOWN,PDIF +S 26800,5500,26800,9400,200,*,DOWN,PTRANS +S 26200,5700,26200,9200,600,*,DOWN,PDIF +S 20800,7500,20800,9400,200,*,UP,PTRANS +S 14200,6800,14200,8300,600,*,UP,PDIF +S 17200,6600,17200,8500,200,*,DOWN,PTRANS +S 19000,6700,19000,9200,600,*,UP,PDIF +S 17800,6800,17800,8300,600,*,UP,PDIF +S 20000,7800,20000,9200,600,*,DOWN,PDIF +S 22600,7800,22600,9200,600,*,DOWN,PDIF +S 21200,7700,21200,9200,600,*,DOWN,PDIF +S 23800,7800,23800,9200,600,*,UP,PDIF +S 25000,5700,25000,9200,600,*,DOWN,PDIF +S 25600,5500,25600,9400,200,*,DOWN,PTRANS +S 16600,6800,16600,8300,600,*,UP,PDIF +S 15400,6800,15400,9100,600,*,UP,PDIF +S 16000,6600,16000,8500,200,*,DOWN,PTRANS +S 14800,6600,14800,8500,200,*,DOWN,PTRANS +S 0,5000,28000,5000,10000,sff3_x4,RIGHT,TALU8 +S 0,2200,28000,2200,5200,*,RIGHT,PWELL +S 0,7600,28000,7600,5600,*,RIGHT,NWELL +S 0,9400,28000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,28000,600,1200,vss,RIGHT,CALU1 +S 12200,2800,12200,6200,200,*,DOWN,POLY +S 12200,6500,12200,8500,200,*,DOWN,PTRANS +S 12200,1500,12200,2500,200,*,UP,NTRANS +S 12800,1700,12800,2300,600,*,DOWN,NDIF +S 12800,6700,12800,8300,600,*,UP,PDIF +S 11200,5700,11200,9100,1000,*,DOWN,PDIF +S 11200,900,11200,3500,1000,*,DOWN,NDIF +S 13000,6700,13000,8300,600,*,UP,PDIF +S 13000,1700,13000,2300,600,*,DOWN,NDIF +S 13200,5000,23200,5000,200,nckr,RIGHT,POLY +S 1000,700,1000,2100,400,*,DOWN,ALU1 +S 2200,3100,2200,3500,600,*,UP,NDIF +S 1600,2900,1600,3700,200,*,DOWN,NTRANS +S 1000,1900,1000,3500,600,*,DOWN,NDIF +S 1600,4000,1600,5200,200,*,DOWN,POLY +S 2200,3000,3700,3000,400,*,LEFT,ALU1 +S 4100,5000,5100,5000,400,*,LEFT,ALU1 +S 3000,4300,3000,5100,400,*,DOWN,ALU1 +S 2000,3200,2000,6000,400,*,UP,ALU1 +S 2100,6000,5100,6000,400,*,LEFT,ALU1 +S 4500,3000,5600,3000,400,*,RIGHT,ALU1 +S 5600,3000,5600,4000,400,*,UP,ALU1 +S 5600,4000,6000,4000,400,*,RIGHT,ALU1 +S 6000,4000,6000,6900,400,*,UP,ALU1 +S 1000,7000,3700,7000,400,*,LEFT,ALU1 +S 2100,8000,6700,8000,400,*,RIGHT,ALU1 +S 4500,7000,11000,7000,400,*,RIGHT,ALU1 +S 6700,3000,9800,3000,400,*,RIGHT,ALU1 +S 10000,3400,10000,6000,400,*,DOWN,ALU1 +S 9800,7100,9800,8100,400,*,DOWN,ALU1 +S 9800,8000,16000,8000,400,*,RIGHT,ALU1 +S 11000,2000,11000,7000,400,*,DOWN,ALU1 +S 9700,2000,11000,2000,400,*,RIGHT,ALU1 +S 13000,1900,13000,7100,400,*,DOWN,ALU1 +S 14200,6900,15000,6900,400,*,LEFT,ALU1 +S 15000,2100,15000,6900,400,*,UP,ALU1 +S 14200,2100,15000,2100,400,*,RIGHT,ALU1 +S 16000,2900,16000,8000,400,u,DOWN,ALU1 +S 17000,3000,17000,5100,400,*,DOWN,ALU1 +S 19000,2000,19000,7000,400,sff_m,DOWN,ALU1 +S 17700,7000,19000,7000,400,*,RIGHT,ALU1 +S 19100,6000,20500,6000,400,*,RIGHT,ALU1 +S 19100,3000,20500,3000,400,*,LEFT,ALU1 +S 17700,2000,19000,2000,400,*,RIGHT,ALU1 +S 19900,2000,21400,2000,400,*,RIGHT,ALU1 +S 21400,1900,21400,8100,400,y,DOWN,ALU1 +S 19900,7000,21300,7000,400,*,LEFT,ALU1 +S 22600,4000,22600,7000,400,*,DOWN,ALU1 +S 23800,2000,23800,8000,400,sff_s,DOWN,ALU1 +S 22500,8000,23800,8000,400,*,RIGHT,ALU1 +S 23900,4000,24900,4000,400,*,RIGHT,ALU1 +S 22500,2000,23800,2000,400,*,RIGHT,ALU1 +S 24700,3000,26100,3000,400,*,RIGHT,ALU1 +S 24700,5000,26100,5000,400,*,RIGHT,ALU1 +S 17100,6000,18000,6000,400,*,RIGHT,ALU1 +S 18000,3900,18000,6000,400,*,UP,ALU1 +S 8900,5000,9100,5000,400,*,LEFT,ALU1 +S 1000,2900,1000,7100,400,*,DOWN,ALU1 +S 12000,1900,12000,7100,400,*,DOWN,ALU1 +S 9700,6000,9900,6000,400,*,RIGHT,ALU1 +S 2100,3200,2300,3200,400,*,RIGHT,ALU1 +S 26100,8000,26300,8000,400,*,RIGHT,ALU1 +S 26100,7000,26300,7000,400,*,RIGHT,ALU1 +S 26100,6000,26300,6000,400,*,RIGHT,ALU1 +S 26100,2000,26300,2000,400,*,RIGHT,ALU1 +S 22700,7000,22900,7000,400,*,RIGHT,ALU1 +S 22300,4000,22500,4000,400,*,RIGHT,ALU1 +S 17100,3000,17300,3000,400,*,RIGHT,ALU1 +S 14100,7000,14300,7000,400,*,RIGHT,ALU1 +S 14100,2000,14300,2000,400,*,RIGHT,ALU1 +S 13100,5000,13300,5000,400,*,RIGHT,ALU1 +S 25000,5000,25000,5000,400,q,LEFT,CALU1 +S 25000,3000,25000,3000,400,q,LEFT,CALU1 +V 17800,9300,CONT_BODY_N,* +V 16600,9300,CONT_BODY_N,* +V 14200,9300,CONT_BODY_N,* +V 12800,9300,CONT_BODY_N,* +V 23800,700,CONT_BODY_P,* +V 22600,700,CONT_BODY_P,* +V 17800,700,CONT_BODY_P,* +V 16600,700,CONT_BODY_P,* +V 14200,700,CONT_BODY_P,* +V 12800,700,CONT_BODY_P,* +V 11000,9000,CONT_DIF_P,* +V 8800,6000,CONT_POLY,* +V 8800,4000,CONT_POLY,* +V 7800,5000,CONT_POLY,* +V 8400,3000,CONT_POLY,* +V 6800,3000,CONT_POLY,* +V 5000,6000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 3600,3000,CONT_POLY,* +V 3600,7000,CONT_POLY,* +V 9800,3400,CONT_DIF_N,* +V 4600,3000,CONT_DIF_N,* +V 6600,2000,CONT_DIF_N,* +V 7800,1000,CONT_DIF_N,* +V 9800,2000,CONT_DIF_N,* +V 11000,1000,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 2200,2000,CONT_DIF_N,* +V 6600,8000,CONT_DIF_P,* +V 7800,9000,CONT_DIF_P,* +V 9800,8000,CONT_DIF_P,* +V 9800,6000,CONT_DIF_P,* +V 4600,7000,CONT_DIF_P,* +V 2200,8000,CONT_DIF_P,* +V 2200,6000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 20000,7000,CONT_POLY,* +V 22800,7000,CONT_POLY,* +V 18000,4000,CONT_POLY,* +V 20400,6000,CONT_POLY,* +V 22400,4000,CONT_POLY,* +V 20400,3000,CONT_POLY,* +V 24800,3000,CONT_POLY,* +V 24800,5000,CONT_POLY,* +V 17000,5000,CONT_POLY,* +V 24800,4000,CONT_POLY,* +V 15000,4000,CONT_POLY,* +V 17200,6000,CONT_POLY,* +V 16000,6000,CONT_POLY,* +V 17200,3000,CONT_POLY,* +V 16000,3000,CONT_POLY,* +V 20000,2000,CONT_POLY,* +V 14200,2000,CONT_DIF_N,* +V 26200,2000,CONT_DIF_N,* +V 25000,2000,CONT_DIF_N,* +V 27400,2000,CONT_DIF_N,* +V 25000,1000,CONT_DIF_N,* +V 27400,1000,CONT_DIF_N,* +V 21400,2000,CONT_DIF_N,* +V 17800,2000,CONT_DIF_N,* +V 22600,2000,CONT_DIF_N,* +V 20200,1000,CONT_DIF_N,* +V 15400,1000,CONT_DIF_N,* +V 25000,6000,CONT_DIF_P,* +V 26200,6000,CONT_DIF_P,* +V 27400,6000,CONT_DIF_P,* +V 21400,8000,CONT_DIF_P,* +V 20200,9000,CONT_DIF_P,* +V 26200,8000,CONT_DIF_P,* +V 27400,7000,CONT_DIF_P,* +V 27400,8000,CONT_DIF_P,* +V 25000,9000,CONT_DIF_P,* +V 14200,7000,CONT_DIF_P,* +V 27400,9000,CONT_DIF_P,* +V 25000,8000,CONT_DIF_P,* +V 25000,7000,CONT_DIF_P,* +V 17800,7000,CONT_DIF_P,* +V 26200,7000,CONT_DIF_P,* +V 22600,8000,CONT_DIF_P,* +V 15400,9200,CONT_DIF_P,* +V 12000,5000,CONT_POLY,* +V 13200,5000,CONT_POLY,* +V 13000,2000,CONT_DIF_N,* +V 13000,7000,CONT_DIF_P,* +V 2200,3200,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/sff3_x4.vbe b/pdks/symbolic/msxlib/cells/sff3_x4.vbe new file mode 100644 index 000000000..a1953ab9f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/sff3_x4.vbe @@ -0,0 +1,65 @@ +ENTITY sff3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 890; + CONSTANT rup_ck_q : NATURAL := 810; + CONSTANT taf_ck_q : NATURAL := 600; + CONSTANT tar_ck_q : NATURAL := 600; + CONSTANT thf_ck_q : NATURAL := 0; + CONSTANT thf_cmd0_ck : NATURAL := 0; + CONSTANT thf_cmd1_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thf_i2_ck : NATURAL := 0; + CONSTANT thr_ck_q : NATURAL := 0; + CONSTANT thr_cmd0_ck : NATURAL := 0; + CONSTANT thr_cmd1_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT thr_i2_ck : NATURAL := 0; + CONSTANT tsf_cmd0_ck : NATURAL := 1200; + CONSTANT tsf_cmd1_ck : NATURAL := 1200; + CONSTANT tsf_i0_ck : NATURAL := 1200; + CONSTANT tsf_i1_ck : NATURAL := 1200; + CONSTANT tsf_i2_ck : NATURAL := 1200; + CONSTANT tsr_cmd0_ck : NATURAL := 1100; + CONSTANT tsr_cmd1_ck : NATURAL := 1100; + CONSTANT tsr_i0_ck : NATURAL := 850; + CONSTANT tsr_i1_ck : NATURAL := 950; + CONSTANT tsr_i2_ck : NATURAL := 950; + CONSTANT transistors : NATURAL := 42 +); +PORT ( + ck : in BIT; + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff3_x4; + +ARCHITECTURE behaviour_data_flow OF sff3_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff3_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2)))); + END BLOCK label0; + + q <= sff_m after 2400 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/tie_x0.ap b/pdks/symbolic/msxlib/cells/tie_x0.ap new file mode 100644 index 000000000..250d3cf2b --- /dev/null +++ b/pdks/symbolic/msxlib/cells/tie_x0.ap @@ -0,0 +1,15 @@ +V ALLIANCE : 6 +H tie_x0,P, 9/ 8/2014,100 +A 0,0,2000,10000 +S 1000,5700,1000,9500,1200,*,UP,NTIE +S 1000,500,1000,3700,1200,*,DOWN,PTIE +S 0,600,2000,600,1200,vss,RIGHT,CALU1 +S 0,5000,2000,5000,10000,tie_x0,LEFT,TALU8 +S 0,2200,2000,2200,5200,*,LEFT,PWELL +S 0,7600,2000,7600,5600,*,LEFT,NWELL +S 0,9400,2000,9400,1200,vdd,RIGHT,CALU1 +V 1300,700,CONT_BODY_P,* +V 700,700,CONT_BODY_P,* +V 1300,9300,CONT_BODY_N,* +V 700,9300,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/tie_x0.vbe b/pdks/symbolic/msxlib/cells/tie_x0.vbe new file mode 100644 index 000000000..fa318aafb --- /dev/null +++ b/pdks/symbolic/msxlib/cells/tie_x0.vbe @@ -0,0 +1,18 @@ +ENTITY tie_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END tie_x0; + +ARCHITECTURE behaviour_data_flow OF tie_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on tie_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/vddtie.ap b/pdks/symbolic/msxlib/cells/vddtie.ap new file mode 100644 index 000000000..18a126996 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vddtie.ap @@ -0,0 +1,53 @@ +V ALLIANCE : 6 +H vddtie,P, 9/ 8/2014,100 +A 0,0,3000,10000 +R 2000,2000,ref_ref,z_20 +R 2000,3000,ref_ref,z_30 +R 2000,4000,ref_ref,z_40 +R 2000,5000,ref_ref,z_50 +R 2000,6000,ref_ref,z_60 +R 2000,7000,ref_ref,z_70 +R 2000,8000,ref_ref,z_80 +R 1000,6000,ref_ref,z_60 +S 600,9300,2400,9300,600,*,RIGHT,NTIE +S 600,700,2400,700,600,*,RIGHT,PTIE +S 2000,1900,2000,8100,400,*,DOWN,ALU1 +S 1400,8500,1400,8800,200,*,UP,POLY +S 700,5700,700,8300,600,*,UP,PDIF +S 1400,5500,1400,8500,200,1,UP,PTRANS +S 2100,5700,2100,8300,600,*,UP,PDIF +S 1400,1600,1400,3900,200,2,DOWN,NTRANS +S 1400,1200,1400,1600,200,*,DOWN,POLY +S 2100,1800,2100,3700,600,*,DOWN,NDIF +S 700,1800,700,3700,600,*,UP,NDIF +S 800,4700,1400,4700,600,*,RIGHT,POLY +S 800,700,800,4800,400,*,DOWN,ALU1 +S 1400,3900,1400,5500,200,*,DOWN,POLY +S 2000,2000,2000,8000,400,z,DOWN,CALU1 +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 0,5000,3000,5000,10000,vddtie,LEFT,TALU8 +S 0,2200,3000,2200,5200,*,LEFT,PWELL +S 0,7600,3000,7600,5600,*,LEFT,NWELL +S 800,6000,2000,6000,400,*,LEFT,ALU1 +S 800,7300,800,9300,400,*,UP,ALU1 +S 1000,6000,1000,6000,400,z,LEFT,CALU1 +V 2300,9300,CONT_BODY_N,* +V 1500,9300,CONT_BODY_N,* +V 700,9300,CONT_BODY_N,* +V 2300,700,CONT_BODY_P,* +V 1500,700,CONT_BODY_P,* +V 700,700,CONT_BODY_P,* +V 800,2000,CONT_DIF_N,* +V 800,2800,CONT_DIF_N,* +V 800,3600,CONT_DIF_N,* +V 800,7400,CONT_DIF_P,* +V 800,8200,CONT_DIF_P,* +V 2000,2000,CONT_DIF_N,* +V 800,4700,CONT_POLY,* +V 2000,2800,CONT_DIF_N,* +V 2000,3600,CONT_DIF_N,* +V 2000,7400,CONT_DIF_P,* +V 2000,6600,CONT_DIF_P,* +V 2000,5800,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/vddtie.vbe b/pdks/symbolic/msxlib/cells/vddtie.vbe new file mode 100644 index 000000000..bf325ef83 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vddtie.vbe @@ -0,0 +1,20 @@ +ENTITY vddtie IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END vddtie; + +ARCHITECTURE behaviour_data_flow OF vddtie IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vddtie" + SEVERITY WARNING; + z <= '1'; +END; diff --git a/pdks/symbolic/msxlib/cells/vfeed1.ap b/pdks/symbolic/msxlib/cells/vfeed1.ap new file mode 100644 index 000000000..ab4bca146 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed1.ap @@ -0,0 +1,9 @@ +V ALLIANCE : 6 +H vfeed1,P,16/ 6/2004,100 +A 0,0,1000,10000 +S 0,7600,1000,7600,5600,*,LEFT,NWELL +S 0,2200,1000,2200,5200,*,LEFT,PWELL +S 0,5000,1000,5000,10000,vfeed1,LEFT,TALU8 +S 0,600,1000,600,1200,vss,RIGHT,CALU1 +S 0,9400,1000,9400,1200,vdd,RIGHT,CALU1 +EOF diff --git a/pdks/symbolic/msxlib/cells/vfeed1.vbe b/pdks/symbolic/msxlib/cells/vfeed1.vbe new file mode 100644 index 000000000..5f0117fc9 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed1.vbe @@ -0,0 +1,18 @@ +ENTITY vfeed1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END vfeed1; + +ARCHITECTURE behaviour_data_flow OF vfeed1 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vfeed1" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/vfeed2.ap b/pdks/symbolic/msxlib/cells/vfeed2.ap new file mode 100644 index 000000000..578a4f4ed --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed2.ap @@ -0,0 +1,15 @@ +V ALLIANCE : 6 +H vfeed2,P, 9/ 8/2014,100 +A 0,0,2000,10000 +S 1000,5700,1000,9500,1400,*,UP,NTIE +S 1000,500,1000,3700,1400,*,DOWN,PTIE +S 0,600,2000,600,1200,vss,RIGHT,CALU1 +S 0,5000,2000,5000,10000,vfeed2,LEFT,TALU8 +S 0,2200,2000,2200,5200,*,LEFT,PWELL +S 0,7600,2000,7600,5600,*,LEFT,NWELL +S 0,9400,2000,9400,1200,vdd,RIGHT,CALU1 +V 1300,700,CONT_BODY_P,* +V 700,700,CONT_BODY_P,* +V 1300,9300,CONT_BODY_N,* +V 700,9300,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/vfeed2.vbe b/pdks/symbolic/msxlib/cells/vfeed2.vbe new file mode 100644 index 000000000..4ad983319 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed2.vbe @@ -0,0 +1,18 @@ +ENTITY vfeed2 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END vfeed2; + +ARCHITECTURE behaviour_data_flow OF vfeed2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vfeed2" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/vfeed3.ap b/pdks/symbolic/msxlib/cells/vfeed3.ap new file mode 100644 index 000000000..d0a4d8062 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed3.ap @@ -0,0 +1,17 @@ +V ALLIANCE : 6 +H vfeed3,P, 9/ 8/2014,100 +A 0,0,3000,10000 +S 0,5000,3000,5000,10000,vfeed3,LEFT,TALU8 +S 0,2200,3000,2200,5200,*,LEFT,PWELL +S 0,7600,3000,7600,5600,*,LEFT,NWELL +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 1500,5700,1500,9500,2400,*,UP,NTIE +S 1500,500,1500,3700,2400,*,DOWN,PTIE +V 2300,700,CONT_BODY_P,* +V 1500,700,CONT_BODY_P,* +V 700,700,CONT_BODY_P,* +V 700,9300,CONT_BODY_N,* +V 2300,9300,CONT_BODY_N,* +V 1500,9300,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/vfeed3.vbe b/pdks/symbolic/msxlib/cells/vfeed3.vbe new file mode 100644 index 000000000..ca6ce9ff9 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed3.vbe @@ -0,0 +1,18 @@ +ENTITY vfeed3 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END vfeed3; + +ARCHITECTURE behaviour_data_flow OF vfeed3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vfeed3" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/vfeed4.ap b/pdks/symbolic/msxlib/cells/vfeed4.ap new file mode 100644 index 000000000..eab369ca2 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed4.ap @@ -0,0 +1,19 @@ +V ALLIANCE : 6 +H vfeed4,P, 9/ 8/2014,100 +A 0,0,4000,10000 +S 0,5000,4000,5000,10000,vfeed4,LEFT,TALU8 +S 0,2200,4000,2200,5200,*,LEFT,PWELL +S 0,7600,4000,7600,5600,*,LEFT,NWELL +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 2000,5700,2000,9500,3400,*,UP,NTIE +S 2000,500,2000,3700,3400,*,DOWN,PTIE +V 3300,700,CONT_BODY_P,* +V 3300,9300,CONT_BODY_N,* +V 2400,9300,CONT_BODY_N,* +V 1500,9300,CONT_BODY_N,* +V 700,9300,CONT_BODY_N,* +V 2500,700,CONT_BODY_P,* +V 1500,700,CONT_BODY_P,* +V 700,700,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/vfeed4.vbe b/pdks/symbolic/msxlib/cells/vfeed4.vbe new file mode 100644 index 000000000..436550bb1 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed4.vbe @@ -0,0 +1,18 @@ +ENTITY vfeed4 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END vfeed4; + +ARCHITECTURE behaviour_data_flow OF vfeed4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vfeed4" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/vfeed5.ap b/pdks/symbolic/msxlib/cells/vfeed5.ap new file mode 100644 index 000000000..fdafd35e9 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed5.ap @@ -0,0 +1,21 @@ +V ALLIANCE : 6 +H vfeed5,P, 9/ 8/2014,100 +A 0,0,5000,10000 +S 0,5000,5000,5000,10000,vfeed5,LEFT,TALU8 +S 0,2200,5000,2200,5200,*,LEFT,PWELL +S 0,7600,5000,7600,5600,*,LEFT,NWELL +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 2500,5700,2500,9500,4400,*,UP,NTIE +S 2500,500,2500,3700,4400,*,DOWN,PTIE +V 3500,9300,CONT_BODY_N,* +V 2500,9300,CONT_BODY_N,* +V 1500,9300,CONT_BODY_N,* +V 4300,9300,CONT_BODY_N,* +V 700,9300,CONT_BODY_N,* +V 2500,700,CONT_BODY_P,* +V 3500,700,CONT_BODY_P,* +V 4300,700,CONT_BODY_P,* +V 1500,700,CONT_BODY_P,* +V 700,700,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/msxlib/cells/vfeed5.vbe b/pdks/symbolic/msxlib/cells/vfeed5.vbe new file mode 100644 index 000000000..57242e79a --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed5.vbe @@ -0,0 +1,18 @@ +ENTITY vfeed5 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END vfeed5; + +ARCHITECTURE behaviour_data_flow OF vfeed5 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vfeed5" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/vfeed6.ap b/pdks/symbolic/msxlib/cells/vfeed6.ap new file mode 100644 index 000000000..5ea319b00 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed6.ap @@ -0,0 +1,23 @@ +V ALLIANCE : 6 +H vfeed6,P, 9/ 8/2014,100 +A 0,0,6000,10000 +S 0,5000,6000,5000,10000,vfeed6,LEFT,TALU8 +S 0,2200,6000,2200,5200,*,LEFT,PWELL +S 0,7600,6000,7600,5600,*,LEFT,NWELL +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 3000,500,3000,3700,5400,*,DOWN,PTIE +S 3000,5700,3000,9500,5400,*,UP,NTIE +V 1500,700,CONT_BODY_P,* +V 2500,700,CONT_BODY_P,* +V 3500,700,CONT_BODY_P,* +V 4500,700,CONT_BODY_P,* +V 5300,700,CONT_BODY_P,* +V 700,700,CONT_BODY_P,* +V 1500,9300,CONT_BODY_N,* +V 2500,9300,CONT_BODY_N,* +V 3500,9300,CONT_BODY_N,* +V 4500,9300,CONT_BODY_N,* +V 5300,9300,CONT_BODY_N,* +V 700,9300,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/vfeed6.vbe b/pdks/symbolic/msxlib/cells/vfeed6.vbe new file mode 100644 index 000000000..a603a3a97 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed6.vbe @@ -0,0 +1,18 @@ +ENTITY vfeed6 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END vfeed6; + +ARCHITECTURE behaviour_data_flow OF vfeed6 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vfeed6" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/vfeed7.ap b/pdks/symbolic/msxlib/cells/vfeed7.ap new file mode 100644 index 000000000..d01c62325 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed7.ap @@ -0,0 +1,25 @@ +V ALLIANCE : 6 +H vfeed7,P, 9/ 8/2014,100 +A 0,0,7000,10000 +S 0,5000,7000,5000,10000,vfeed7,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 3500,5700,3500,9500,6400,*,UP,NTIE +S 3500,500,3500,3700,6400,*,DOWN,PTIE +V 1500,700,CONT_BODY_P,* +V 2500,700,CONT_BODY_P,* +V 3500,700,CONT_BODY_P,* +V 4500,700,CONT_BODY_P,* +V 5500,700,CONT_BODY_P,* +V 6300,700,CONT_BODY_P,* +V 700,700,CONT_BODY_P,* +V 1500,9300,CONT_BODY_N,* +V 2500,9300,CONT_BODY_N,* +V 3500,9300,CONT_BODY_N,* +V 4500,9300,CONT_BODY_N,* +V 5500,9300,CONT_BODY_N,* +V 6300,9300,CONT_BODY_N,* +V 700,9300,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/vfeed7.vbe b/pdks/symbolic/msxlib/cells/vfeed7.vbe new file mode 100644 index 000000000..94fa2eec1 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed7.vbe @@ -0,0 +1,18 @@ +ENTITY vfeed7 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END vfeed7; + +ARCHITECTURE behaviour_data_flow OF vfeed7 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vfeed7" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/vfeed8.ap b/pdks/symbolic/msxlib/cells/vfeed8.ap new file mode 100644 index 000000000..d4f75bdf8 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed8.ap @@ -0,0 +1,27 @@ +V ALLIANCE : 6 +H vfeed8,P, 9/ 8/2014,100 +A 0,0,8000,10000 +S 0,5000,8000,5000,10000,vfeed8,LEFT,TALU8 +S 0,2200,8000,2200,5200,*,LEFT,PWELL +S 0,7600,8000,7600,5600,*,LEFT,NWELL +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 4000,500,4000,3700,7400,*,DOWN,PTIE +S 4000,5700,4000,9500,7400,*,UP,NTIE +V 1500,9300,CONT_BODY_N,* +V 2500,9300,CONT_BODY_N,* +V 3500,9300,CONT_BODY_N,* +V 4500,9300,CONT_BODY_N,* +V 5500,9300,CONT_BODY_N,* +V 6500,9300,CONT_BODY_N,* +V 6500,700,CONT_BODY_P,* +V 5500,700,CONT_BODY_P,* +V 4500,700,CONT_BODY_P,* +V 3500,700,CONT_BODY_P,* +V 2500,700,CONT_BODY_P,* +V 1500,700,CONT_BODY_P,* +V 700,700,CONT_BODY_P,* +V 7300,700,CONT_BODY_P,* +V 7300,9300,CONT_BODY_N,* +V 700,9300,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/vfeed8.vbe b/pdks/symbolic/msxlib/cells/vfeed8.vbe new file mode 100644 index 000000000..01c51c36f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vfeed8.vbe @@ -0,0 +1,18 @@ +ENTITY vfeed8 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END vfeed8; + +ARCHITECTURE behaviour_data_flow OF vfeed8 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vfeed8" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/msxlib/cells/vsstie.ap b/pdks/symbolic/msxlib/cells/vsstie.ap new file mode 100644 index 000000000..2dd552a66 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vsstie.ap @@ -0,0 +1,54 @@ +V ALLIANCE : 6 +H vsstie,P,17/ 8/2004,100 +A 0,0,3000,10000 +R 2000,8000,ref_ref,z_80 +R 2000,7000,ref_ref,z_70 +R 2000,6000,ref_ref,z_60 +R 2000,5000,ref_ref,z_50 +R 2000,4000,ref_ref,z_40 +R 2000,3000,ref_ref,z_30 +R 2000,2000,ref_ref,z_20 +R 1000,4000,ref_ref,z_40 +S 0,7600,3000,7600,5600,*,LEFT,NWELL +S 0,2200,3000,2200,5200,*,LEFT,PWELL +S 0,5000,3000,5000,10000,vsstie,LEFT,TALU8 +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 2000,2000,2000,8000,400,z,DOWN,CALU1 +S 1400,3900,1400,5500,200,*,DOWN,POLY +S 700,1800,700,3700,600,*,UP,NDIF +S 2100,1800,2100,3700,600,*,DOWN,NDIF +S 1400,1200,1400,1600,200,*,DOWN,POLY +S 1400,1600,1400,3900,200,2,DOWN,NTRANS +S 600,600,2400,600,600,*,RIGHT,PTIE +S 600,9400,2400,9400,600,*,RIGHT,NTIE +S 2100,5700,2100,8300,600,*,UP,PDIF +S 1400,5500,1400,8500,200,1,UP,PTRANS +S 700,5700,700,8300,600,*,UP,PDIF +S 1400,8500,1400,8800,200,*,UP,POLY +S 2000,1900,2000,8100,400,*,DOWN,ALU1 +S 800,700,800,2900,400,*,DOWN,ALU1 +S 800,4800,800,9300,400,*,UP,ALU1 +S 800,4900,1400,4900,600,*,RIGHT,POLY +S 1000,4000,1000,4000,400,z,LEFT,CALU1 +S 800,4000,2000,4000,400,*,LEFT,ALU1 +V 2000,5800,CONT_DIF_P,* +V 2000,6600,CONT_DIF_P,* +V 2000,7400,CONT_DIF_P,* +V 2000,3600,CONT_DIF_N,* +V 2000,2800,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 700,600,CONT_BODY_P,* +V 1500,600,CONT_BODY_P,* +V 2300,600,CONT_BODY_P,* +V 700,9400,CONT_BODY_N,* +V 1500,9400,CONT_BODY_N,* +V 2300,9400,CONT_BODY_N,* +V 800,8200,CONT_DIF_P,* +V 800,7400,CONT_DIF_P,* +V 800,6600,CONT_DIF_P,* +V 800,5800,CONT_DIF_P,* +V 800,2800,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 800,4900,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/vsstie.vbe b/pdks/symbolic/msxlib/cells/vsstie.vbe new file mode 100644 index 000000000..9f430c73a --- /dev/null +++ b/pdks/symbolic/msxlib/cells/vsstie.vbe @@ -0,0 +1,20 @@ +ENTITY vsstie IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END vsstie; + +ARCHITECTURE behaviour_data_flow OF vsstie IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vsstie" + SEVERITY WARNING; + z <= '0'; +END; diff --git a/pdks/symbolic/msxlib/cells/xaoi21_x05.ap b/pdks/symbolic/msxlib/cells/xaoi21_x05.ap new file mode 100644 index 000000000..aa036e22f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaoi21_x05.ap @@ -0,0 +1,142 @@ +V ALLIANCE : 6 +H xaoi21_x05,P, 9/ 8/2014,100 +A 0,0,8000,10000 +R 4000,8000,ref_ref,b_80 +R 5000,8000,ref_ref,b_80 +R 6000,8000,ref_ref,b_80 +R 6000,7000,ref_ref,b_70 +R 5000,2000,ref_ref,z_20 +R 5000,3000,ref_ref,z_30 +R 5000,4000,ref_ref,z_40 +R 4000,4000,ref_ref,z_40 +R 4000,5000,ref_ref,z_50 +R 4000,6000,ref_ref,z_60 +R 2000,6000,ref_ref,a2_60 +R 3000,6000,ref_ref,a2_60 +R 3000,5000,ref_ref,a2_50 +R 3000,4000,ref_ref,a2_40 +R 4000,3000,ref_ref,a1_30 +R 3000,3000,ref_ref,a1_30 +R 2000,3000,ref_ref,a1_30 +R 2000,4000,ref_ref,a1_40 +R 2000,5000,ref_ref,a1_50 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 3100,700,3900,700,600,*,RIGHT,PTIE +S 6000,1900,6000,5100,400,*,UP,ALU1 +S 5000,8000,5000,8000,400,b,LEFT,CALU1 +S 4000,8000,4000,8000,400,b,LEFT,CALU1 +S 6000,7000,6000,8000,400,b,DOWN,CALU1 +S 6000,6900,6600,6900,400,*,RIGHT,ALU1 +S 3300,8000,6000,8000,400,*,LEFT,ALU1 +S 3300,8100,6000,8100,400,*,LEFT,ALU1 +S 6600,5900,6600,6900,400,*,UP,ALU1 +S 6000,6900,6000,8100,400,*,DOWN,ALU1 +S 5000,6000,5000,7000,400,*,UP,ALU1 +S 5000,6000,5700,6000,400,*,LEFT,ALU1 +S 700,7000,5000,7000,400,*,RIGHT,ALU1 +S 3600,5100,3600,5500,200,*,DOWN,POLY +S 2200,1300,2200,1700,200,*,DOWN,POLY +S 3000,1300,3000,1700,200,*,DOWN,POLY +S 4200,1300,4200,1700,200,*,DOWN,POLY +S 5400,1300,5400,1700,200,*,DOWN,POLY +S 6600,1300,6600,1700,200,*,DOWN,POLY +S 6800,8700,6800,9100,200,*,UP,POLY +S 5600,8700,5600,9100,200,*,UP,POLY +S 4800,8700,4800,9100,200,*,UP,POLY +S 2400,7500,2400,7900,200,*,UP,POLY +S 1200,7500,1200,7900,200,*,UP,POLY +S 1800,7900,1800,9300,400,*,UP,ALU1 +S 7400,5100,7400,7900,400,*,DOWN,ALU1 +S 6000,5100,7400,5100,400,*,LEFT,ALU1 +S 5000,5000,6000,5000,600,*,RIGHT,ALU1 +S 4000,5700,4000,7300,400,*,UP,PDIF +S 4200,5900,4200,7300,600,*,UP,PDIF +S 7200,6900,7200,8500,400,*,DOWN,PDIF +S 4400,6900,4400,8500,400,*,DOWN,PDIF +S 800,5700,800,7300,400,*,DOWN,PDIF +S 6200,6900,6200,9100,600,*,DOWN,PDIF +S 7200,700,7200,2100,400,*,DOWN,ALU1 +S 7200,1900,7200,2400,600,*,UP,NDIF +S 7300,1900,7300,2400,600,*,UP,NDIF +S 6600,2600,6600,6000,200,*,UP,POLY +S 6000,1900,6000,2400,600,*,UP,NDIF +S 4000,4000,4000,6000,400,z,UP,CALU1 +S 5000,2000,5000,4000,400,z,UP,CALU1 +S 4000,4000,5000,4000,600,*,RIGHT,ALU1 +S 4900,1900,4900,4000,600,*,DOWN,ALU1 +S 3000,5700,3000,7300,600,*,DOWN,PDIF +S 1800,5700,1800,8100,600,*,DOWN,PDIF +S 600,5900,600,6500,600,*,UP,PDIF +S 2000,6000,2000,6000,400,a2,LEFT,CALU1 +S 3000,4000,3000,6000,400,a2,UP,CALU1 +S 2000,6000,3000,6000,600,*,LEFT,ALU1 +S 2000,2900,2000,5100,400,*,UP,ALU1 +S 3000,3000,3000,3000,400,a1,LEFT,CALU1 +S 4000,3000,4000,3000,400,a1,LEFT,CALU1 +S 2000,3000,2000,5000,400,a1,DOWN,CALU1 +S 2400,4500,2400,5500,200,*,DOWN,POLY +S 3000,4000,3000,4300,200,*,DOWN,POLY +S 2400,4500,3000,4500,200,*,RIGHT,POLY +S 2000,3000,4000,3000,600,*,LEFT,ALU1 +S 3000,3900,3000,6100,400,*,UP,ALU1 +S 5800,3000,5800,6000,200,*,DOWN,POLY +S 5400,3000,5800,3000,200,*,RIGHT,POLY +S 4100,4000,4100,6100,600,*,DOWN,ALU1 +S 600,2000,600,7000,400,*,DOWN,ALU1 +S 600,2000,3700,2000,400,*,RIGHT,ALU1 +S 7400,7100,7400,7700,600,*,UP,PDIF +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,8000,5000,10000,xaoi21_x05,LEFT,TALU8 +S 0,2200,8000,2200,5200,*,LEFT,PWELL +S 0,7600,8000,7600,5600,*,LEFT,NWELL +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 6800,6000,6800,6700,200,*,DOWN,POLY +S 5600,6000,5600,6700,200,*,DOWN,POLY +S 5100,6900,5100,8500,400,n1,DOWN,PDIF +S 4200,4500,4800,4500,200,*,RIGHT,POLY +S 4800,4500,4800,6700,200,*,DOWN,POLY +S 4200,2900,4200,4500,200,*,UP,POLY +S 3600,1900,3600,2700,600,*,UP,NDIF +S 3000,2900,3000,4000,200,*,UP,POLY +S 2600,1900,2600,2700,400,n2,UP,NDIF +S 1500,900,1500,2700,600,*,UP,NDIF +S 1600,900,1600,2700,600,*,UP,NDIF +S 1200,3700,2200,3700,200,*,RIGHT,POLY +S 1200,3700,1200,5500,200,*,DOWN,POLY +S 4600,1900,4600,2700,400,*,UP,NDIF +S 4800,1900,4800,2400,600,*,UP,NDIF +S 6800,6700,6800,8700,200,1b,DOWN,PTRANS +S 1200,5500,1200,7500,200,1a,DOWN,PTRANS +S 2200,1700,2200,2900,200,2a,UP,NTRANS +S 2400,5500,2400,7500,200,3a,DOWN,PTRANS +S 3000,1700,3000,2900,200,4a,UP,NTRANS +S 3600,5500,3600,7500,200,2b,DOWN,PTRANS +S 6600,1700,6600,2600,200,3b,UP,NTRANS +S 4800,6700,4800,8700,200,2z,DOWN,PTRANS +S 5600,6700,5600,8700,200,1z,DOWN,PTRANS +S 5400,1700,5400,2600,200,3z,UP,NTRANS +S 4200,1700,4200,2900,200,4z,UP,NTRANS +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 4000,700,CONT_BODY_P,* +V 3000,700,CONT_BODY_P,* +V 6000,2000,CONT_DIF_N,bn +V 4800,2000,CONT_DIF_N,* +V 5000,5000,CONT_POLY,bn +V 7200,2000,CONT_DIF_N,* +V 3000,4300,CONT_POLY,* +V 3600,2000,CONT_DIF_N,an +V 6600,6000,CONT_POLY,* +V 5600,6000,CONT_POLY,an +V 1600,1000,CONT_DIF_N,* +V 600,6600,CONT_DIF_P,an +V 600,5800,CONT_DIF_P,an +V 1800,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,an +V 4200,6000,CONT_DIF_P,* +V 3400,8100,CONT_POLY,* +V 7400,7000,CONT_DIF_P,bn +V 7400,7800,CONT_DIF_P,bn +V 6200,9000,CONT_DIF_P,* +V 2000,3500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/xaoi21_x05.vbe b/pdks/symbolic/msxlib/cells/xaoi21_x05.vbe new file mode 100644 index 000000000..a74687d78 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaoi21_x05.vbe @@ -0,0 +1,44 @@ +ENTITY xaoi21_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 3960; + CONSTANT rdown_a1_z : NATURAL := 3890; + CONSTANT rdown_a2_z : NATURAL := 3890; + CONSTANT rup_b_z : NATURAL := 3690; + CONSTANT rup_a1_z : NATURAL := 4780; + CONSTANT rup_a2_z : NATURAL := 4770; + CONSTANT tphl_a1_z : NATURAL := 83; + CONSTANT tphl_a2_z : NATURAL := 84; + CONSTANT tphl_b_z : NATURAL := 68; + CONSTANT tplh_b_z : NATURAL := 42; + CONSTANT tplh_a1_z : NATURAL := 88; + CONSTANT tplh_a2_z : NATURAL := 83; + CONSTANT tphh_b_z : NATURAL := 87; + CONSTANT tpll_b_z : NATURAL := 66; + CONSTANT tphh_a1_z : NATURAL := 120; + CONSTANT tphh_a2_z : NATURAL := 121; + CONSTANT tpll_a1_z : NATURAL := 118; + CONSTANT tpll_a2_z : NATURAL := 111; + CONSTANT transistors : NATURAL := 11 +); +PORT ( + b : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xaoi21_x05; + +ARCHITECTURE behaviour_data_flow OF xaoi21_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xaoi21_x05" + SEVERITY WARNING; + z <= not ((b xor (a1 and a2))) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/xaoi21_x1.ap b/pdks/symbolic/msxlib/cells/xaoi21_x1.ap new file mode 100644 index 000000000..8d1d5eaa2 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaoi21_x1.ap @@ -0,0 +1,146 @@ +V ALLIANCE : 6 +H xaoi21_x1,P, 9/ 8/2014,100 +A 0,0,9000,10000 +R 2000,5000,ref_ref,a1_50 +R 2000,4000,ref_ref,a1_40 +R 2000,3000,ref_ref,a1_30 +R 3000,3000,ref_ref,a1_30 +R 4000,3000,ref_ref,a1_30 +R 3000,4000,ref_ref,a2_40 +R 3000,5000,ref_ref,a2_50 +R 3000,6000,ref_ref,a2_60 +R 2000,6000,ref_ref,a2_60 +R 7000,7000,ref_ref,b_70 +R 7000,8000,ref_ref,b_80 +R 6000,8000,ref_ref,b_80 +R 5000,8000,ref_ref,b_80 +R 4000,8000,ref_ref,b_80 +R 5000,6000,ref_ref,z_60 +R 5000,5000,ref_ref,z_50 +R 5000,4000,ref_ref,z_40 +R 5000,3000,ref_ref,z_30 +R 5000,2000,ref_ref,z_20 +R 7000,6000,ref_ref,b_60 +R 4000,5000,ref_ref,z_50 +S 600,2000,3700,2000,400,*,RIGHT,ALU1 +S 600,2000,600,7000,400,*,DOWN,ALU1 +S 3000,3900,3000,6100,400,*,UP,ALU1 +S 2000,3000,4000,3000,600,*,LEFT,ALU1 +S 2400,4500,3000,4500,200,*,RIGHT,POLY +S 3000,4000,3000,4300,200,*,DOWN,POLY +S 2400,4500,2400,5500,200,*,DOWN,POLY +S 2000,3000,2000,5000,400,a1,DOWN,CALU1 +S 4000,3000,4000,3000,400,a1,LEFT,CALU1 +S 3000,3000,3000,3000,400,a1,LEFT,CALU1 +S 2000,2900,2000,5100,400,*,UP,ALU1 +S 2000,6000,3000,6000,600,*,LEFT,ALU1 +S 3000,4000,3000,6000,400,a2,UP,CALU1 +S 2000,6000,2000,6000,400,a2,LEFT,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 6000,8000,6000,8000,400,b,LEFT,CALU1 +S 5000,8000,5000,8000,400,b,LEFT,CALU1 +S 0,5000,9000,5000,10000,xaoi21_x1,LEFT,TALU8 +S 0,2200,9000,2200,5200,*,LEFT,PWELL +S 0,7600,9000,7600,5600,*,LEFT,NWELL +S 600,7900,600,9300,400,*,UP,ALU1 +S 4600,5100,4600,5500,200,*,DOWN,POLY +S 3400,8000,7000,8000,400,*,LEFT,ALU1 +S 4000,8000,4000,8000,400,b,LEFT,CALU1 +S 4600,5500,4600,9300,200,2b,DOWN,PTRANS +S 3700,8000,3700,9700,200,*,UP,POLY +S 3700,9700,4600,9700,200,*,RIGHT,POLY +S 4200,5700,4200,9100,400,*,UP,PDIF +S 2400,9300,2400,9700,200,*,UP,POLY +S 1200,9300,1200,9700,200,*,UP,POLY +S 2400,5500,2400,9300,200,3a,DOWN,PTRANS +S 2800,5700,2800,9100,400,*,DOWN,PDIF +S 1200,5500,1200,9300,200,1a,DOWN,PTRANS +S 1800,5700,1800,9100,600,*,DOWN,PDIF +S 600,5700,600,9100,600,*,DOWN,PDIF +S 1800,7000,1800,7900,400,*,UP,ALU1 +S 600,7000,6000,7000,400,*,RIGHT,ALU1 +S 5800,9300,5800,9700,200,*,UP,POLY +S 6600,9300,6600,9700,200,*,UP,POLY +S 7800,9300,7800,9700,200,*,UP,POLY +S 8200,6900,8200,9100,400,*,DOWN,PDIF +S 5000,2000,5000,6000,400,z,UP,CALU1 +S 6600,5500,6600,9300,200,1z,DOWN,PTRANS +S 5800,5500,5800,9300,200,2z,DOWN,PTRANS +S 7200,5700,7200,9100,600,*,DOWN,PDIF +S 7800,5500,7800,9300,200,1b,DOWN,PTRANS +S 8400,5900,8400,6500,600,*,UP,PDIF +S 7000,6000,7000,8000,400,b,DOWN,CALU1 +S 6000,4900,6000,7000,400,*,UP,ALU1 +S 8400,3900,8400,6700,400,*,DOWN,ALU1 +S 7000,6000,7600,6000,400,*,RIGHT,ALU1 +S 7000,6000,7000,8000,600,*,DOWN,ALU1 +S 7600,4800,7600,6000,400,*,UP,ALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 5000,1900,5000,6100,400,*,DOWN,ALU1 +S 5000,6000,5200,6000,600,*,LEFT,ALU1 +S 4800,2000,5000,2000,600,*,RIGHT,ALU1 +S 6700,3900,8400,3900,400,*,LEFT,ALU1 +S 5800,4100,5800,5500,200,*,DOWN,POLY +S 4200,4100,6400,4100,200,*,RIGHT,POLY +S 5800,3200,5800,4900,400,*,UP,ALU1 +S 5800,4900,6700,4900,400,*,LEFT,ALU1 +S 6600,700,6600,2400,200,3b,UP,NTRANS +S 5400,700,5400,2400,200,3z,UP,NTRANS +S 4600,900,4600,2900,400,*,UP,NDIF +S 4200,700,4200,3100,200,4z,UP,NTRANS +S 2600,900,2600,2900,400,n2,UP,NDIF +S 2200,700,2200,3100,200,2a,UP,NTRANS +S 3000,700,3000,3100,200,4a,UP,NTRANS +S 1600,900,1600,2900,600,*,UP,NDIF +S 1500,900,1500,2900,600,*,UP,NDIF +S 3600,900,3600,2900,600,*,UP,NDIF +S 4800,900,4800,2200,600,*,UP,NDIF +S 6000,900,6000,2200,600,*,UP,NDIF +S 7200,900,7200,2200,600,*,UP,NDIF +S 6600,2800,7600,2800,200,*,RIGHT,POLY +S 7600,2800,7600,5000,200,*,UP,POLY +S 5200,5700,5200,9100,600,*,UP,PDIF +S 4000,6300,4000,6900,600,*,DOWN,PDIF +S 4000,6100,4000,7000,400,*,UP,ALU1 +S 4000,5000,4000,5000,400,z,LEFT,CALU1 +S 3900,5000,5000,5000,400,*,RIGHT,ALU1 +S 1200,3900,2200,3900,200,*,RIGHT,POLY +S 1200,3900,1200,5500,200,*,DOWN,POLY +S 3000,3100,3000,4000,200,*,UP,POLY +S 4200,3100,4200,4100,200,*,UP,POLY +S 5400,2400,5400,3500,200,*,UP,POLY +S 2200,300,2200,700,200,*,DOWN,POLY +S 3000,300,3000,700,200,*,DOWN,POLY +S 4200,300,4200,700,200,*,DOWN,POLY +S 5400,300,5400,700,200,*,DOWN,POLY +S 6600,300,6600,700,200,*,DOWN,POLY +S 6600,2000,6600,3900,400,*,UP,ALU1 +S 5900,2000,6600,2000,400,*,RIGHT,ALU1 +S 7400,700,7400,2100,400,*,UP,ALU1 +S 7500,1800,7500,2200,600,*,DOWN,NDIF +V 8300,700,CONT_BODY_P,* +V 1600,1000,CONT_DIF_N,* +V 3600,2000,CONT_DIF_N,an +V 3000,4300,CONT_POLY,* +V 7200,9000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 1800,7000,CONT_DIF_P,an +V 5200,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,an +V 3000,9000,CONT_DIF_P,* +V 3500,8000,CONT_POLY,* +V 600,9000,CONT_DIF_P,* +V 1800,7800,CONT_DIF_P,an +V 4800,2000,CONT_DIF_N,* +V 8400,5800,CONT_DIF_P,bn +V 8400,6600,CONT_DIF_P,bn +V 6600,4900,CONT_POLY,an +V 7600,4900,CONT_POLY,* +V 5800,3300,CONT_POLY,an +V 6000,2000,CONT_DIF_N,bn +V 7200,1000,CONT_DIF_N,* +V 6800,3900,CONT_POLY,bn +V 4000,6200,CONT_DIF_P,an +V 2000,3700,CONT_POLY,* +V 7400,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/msxlib/cells/xaoi21_x1.vbe b/pdks/symbolic/msxlib/cells/xaoi21_x1.vbe new file mode 100644 index 000000000..2c54cf08d --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaoi21_x1.vbe @@ -0,0 +1,44 @@ +ENTITY xaoi21_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 9000; + CONSTANT cin_b : NATURAL := 11; + CONSTANT cin_a1 : NATURAL := 8; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT rdown_b_z : NATURAL := 2070; + CONSTANT rdown_a1_z : NATURAL := 2010; + CONSTANT rdown_a2_z : NATURAL := 2010; + CONSTANT rup_b_z : NATURAL := 1940; + CONSTANT rup_a1_z : NATURAL := 2500; + CONSTANT rup_a2_z : NATURAL := 2500; + CONSTANT tphl_a1_z : NATURAL := 74; + CONSTANT tphl_a2_z : NATURAL := 75; + CONSTANT tphl_b_z : NATURAL := 63; + CONSTANT tplh_b_z : NATURAL := 39; + CONSTANT tplh_a1_z : NATURAL := 82; + CONSTANT tplh_a2_z : NATURAL := 77; + CONSTANT tphh_b_z : NATURAL := 79; + CONSTANT tpll_b_z : NATURAL := 60; + CONSTANT tphh_a1_z : NATURAL := 110; + CONSTANT tphh_a2_z : NATURAL := 111; + CONSTANT tpll_a1_z : NATURAL := 112; + CONSTANT tpll_a2_z : NATURAL := 105; + CONSTANT transistors : NATURAL := 11 +); +PORT ( + b : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xaoi21_x1; + +ARCHITECTURE behaviour_data_flow OF xaoi21_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xaoi21_x1" + SEVERITY WARNING; + z <= not ((b xor (a1 and a2))) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/xaon21_x05.ap b/pdks/symbolic/msxlib/cells/xaon21_x05.ap new file mode 100644 index 000000000..8b813d056 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaon21_x05.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 6 +H xaon21_x05,P, 9/ 8/2014,100 +A 0,0,8000,10000 +R 1000,3000,ref_ref,a1_30 +R 1000,4000,ref_ref,a1_40 +R 3000,3000,ref_ref,z_30 +R 2000,3000,ref_ref,a1_30 +R 3000,6000,ref_ref,a2_60 +R 4000,4000,ref_ref,z_40 +R 4000,5000,ref_ref,z_50 +R 4000,6000,ref_ref,z_60 +R 4000,3000,ref_ref,z_30 +R 6000,2000,ref_ref,b_20 +R 6000,3000,ref_ref,b_30 +R 6000,4000,ref_ref,b_40 +R 2000,6000,ref_ref,a2_60 +R 3000,5000,ref_ref,a2_50 +R 3000,4000,ref_ref,a2_40 +R 7000,2000,ref_ref,b_20 +R 1000,2000,ref_ref,a1_20 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 3200,400,6800,400,200,*,RIGHT,POLY +S 1200,2900,1200,5200,200,*,UP,POLY +S 1000,3000,2000,3000,600,*,LEFT,ALU1 +S 2000,3000,2000,3000,400,a1,LEFT,CALU1 +S 2000,2900,2000,4300,200,*,UP,POLY +S 2600,1900,2600,2700,600,*,UP,NDIF +S 2500,2000,5200,2000,400,*,LEFT,ALU1 +S 1600,1900,1600,2700,400,n2,UP,NDIF +S 1200,1700,1200,2900,200,09,UP,NTRANS +S 1200,1300,1200,1700,200,*,DOWN,POLY +S 2000,1700,2000,2900,200,10,UP,NTRANS +S 2000,1300,2000,1700,200,*,DOWN,POLY +S 3000,3000,3000,3000,400,z,LEFT,CALU1 +S 3000,3000,4000,3000,600,*,RIGHT,ALU1 +S 6800,400,6800,2800,200,*,UP,POLY +S 6600,4900,7400,4900,400,*,RIGHT,ALU1 +S 3200,400,3200,1700,200,*,DOWN,POLY +S 2000,4300,2800,4300,200,*,RIGHT,POLY +S 4000,3000,4000,6000,400,z,DOWN,CALU1 +S 2800,4300,2800,5000,200,*,UP,POLY +S 2000,6000,2000,6000,400,a2,LEFT,CALU1 +S 3000,3900,3000,6100,400,*,UP,ALU1 +S 3000,4000,3000,6000,400,a2,DOWN,CALU1 +S 2000,6000,3000,6000,600,*,LEFT,ALU1 +S 6000,1900,6000,4100,400,*,DOWN,ALU1 +S 6000,2000,6000,4000,400,b,DOWN,CALU1 +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,8000,5000,10000,xaon21_x05,LEFT,TALU8 +S 0,2200,8000,2200,5200,*,LEFT,PWELL +S 0,7600,8000,7600,5600,*,LEFT,NWELL +S 7000,2000,7000,2000,400,b,LEFT,CALU1 +S 6000,2000,7000,2000,600,*,LEFT,ALU1 +S 4700,2500,4700,3000,400,n1,UP,NDIF +S 5200,2300,5200,3200,200,07,UP,NTRANS +S 4400,2300,4400,3200,200,06,UP,NTRANS +S 3600,2500,3600,3000,600,*,UP,NDIF +S 3600,2200,3600,3000,400,*,DOWN,NDIF +S 3200,2000,3200,3200,200,08,UP,NTRANS +S 2800,2200,2800,3000,400,*,DOWN,NDIF +S 3200,3200,3200,3600,200,*,UP,POLY +S 4400,1900,4400,2300,200,*,DOWN,POLY +S 5200,1900,5200,2300,200,*,DOWN,POLY +S 7200,2900,7200,3400,400,*,UP,NDIF +S 6800,2700,6800,3600,200,11,UP,NTRANS +S 6100,900,6100,3400,800,*,UP,NDIF +S 7400,3200,7400,4900,400,*,UP,ALU1 +S 6800,4000,7500,4000,200,*,RIGHT,POLY +S 5200,5400,5800,5400,400,*,RIGHT,ALU1 +S 5200,2000,5200,5400,400,*,UP,ALU1 +S 5500,6000,5500,8000,200,04,DOWN,PTRANS +S 4300,6000,4300,8000,200,03,DOWN,PTRANS +S 4900,6200,4900,7800,600,*,UP,PDIF +S 4400,3300,4400,4600,200,*,UP,POLY +S 4300,4600,4300,6000,200,*,DOWN,POLY +S 4300,4600,6900,4600,200,*,LEFT,POLY +S 4000,6300,5000,6300,400,*,LEFT,ALU1 +S 4000,2900,4000,6300,400,*,DOWN,ALU1 +S 3200,7100,5800,7100,400,*,LEFT,ALU1 +S 3200,6900,3200,7100,400,*,UP,ALU1 +S 5800,5400,5800,7100,400,*,UP,ALU1 +S 5900,6200,5900,7800,400,*,UP,PDIF +S 5500,8000,5500,8400,200,*,UP,POLY +S 4300,8000,4300,8400,200,*,UP,POLY +S 6000,7900,6600,7900,400,*,LEFT,ALU1 +S 6600,4900,6600,7900,400,*,DOWN,ALU1 +S 6200,6400,6200,8000,600,*,DOWN,PDIF +S 7500,4000,7500,5800,200,*,DOWN,POLY +S 7400,6400,7400,8000,600,*,DOWN,PDIF +S 7400,6700,7400,9300,400,*,UP,ALU1 +S 6700,8200,6700,8600,200,*,UP,POLY +S 6700,6200,6700,8200,200,05,DOWN,PTRANS +S 6700,5800,7500,5800,200,*,RIGHT,POLY +S 3800,6200,3800,7800,600,*,UP,PDIF +S 2300,7700,2300,9300,600,*,UP,ALU1 +S 2500,6200,2500,7800,600,*,UP,PDIF +S 1700,6000,1700,8000,200,01,DOWN,PTRANS +S 1300,6200,1300,7800,400,*,UP,PDIF +S 1700,8000,1700,8400,200,*,UP,POLY +S 1700,5200,1700,6100,200,*,DOWN,POLY +S 1200,5200,1700,5200,200,*,RIGHT,POLY +S 600,900,600,2700,600,*,UP,NDIF +S 1000,2000,1000,4000,400,a1,DOWN,CALU1 +S 1000,1900,1000,4100,400,*,DOWN,ALU1 +S 3100,8000,3100,8400,200,*,UP,POLY +S 3100,6000,3100,8000,200,02,DOWN,PTRANS +S 3100,4800,3100,6100,200,*,DOWN,POLY +S 1000,6900,3200,6900,400,*,LEFT,ALU1 +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,3500,CONT_POLY,* +V 2600,2000,CONT_DIF_N,an +V 6700,4900,CONT_POLY,bn +V 6100,1000,CONT_DIF_N,* +V 7000,2000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 5200,3800,CONT_POLY,an +V 3800,2900,CONT_DIF_N,* +V 7400,3300,CONT_DIF_N,bn +V 4900,6300,CONT_DIF_P,* +V 6100,7900,CONT_DIF_P,bn +V 7400,6800,CONT_DIF_P,* +V 7400,7800,CONT_DIF_P,* +V 5300,5400,CONT_POLY,an +V 2300,7700,CONT_DIF_P,* +V 1100,6900,CONT_DIF_P,an +V 600,1000,CONT_DIF_N,* +V 3700,7100,CONT_DIF_P,an +EOF diff --git a/pdks/symbolic/msxlib/cells/xaon21_x05.vbe b/pdks/symbolic/msxlib/cells/xaon21_x05.vbe new file mode 100644 index 000000000..a437136f1 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaon21_x05.vbe @@ -0,0 +1,44 @@ +ENTITY xaon21_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_a2 : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 3870; + CONSTANT rdown_a1_z : NATURAL := 3870; + CONSTANT rdown_a2_z : NATURAL := 3870; + CONSTANT rup_b_z : NATURAL := 3790; + CONSTANT rup_a1_z : NATURAL := 4790; + CONSTANT rup_a2_z : NATURAL := 4780; + CONSTANT tplh_a1_z : NATURAL := 82; + CONSTANT tplh_a2_z : NATURAL := 78; + CONSTANT tphl_b_z : NATURAL := 29; + CONSTANT tplh_b_z : NATURAL := 88; + CONSTANT tphh_b_z : NATURAL := 55; + CONSTANT tphl_a1_z : NATURAL := 76; + CONSTANT tphl_a2_z : NATURAL := 78; + CONSTANT tpll_a1_z : NATURAL := 111; + CONSTANT tpll_a2_z : NATURAL := 105; + CONSTANT tpll_b_z : NATURAL := 88; + CONSTANT tphh_a1_z : NATURAL := 113; + CONSTANT tphh_a2_z : NATURAL := 114; + CONSTANT transistors : NATURAL := 11 +); +PORT ( + b : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xaon21_x05; + +ARCHITECTURE behaviour_data_flow OF xaon21_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xaon21_x05" + SEVERITY WARNING; + z <= (b xor (a1 and a2)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/xaon21_x1.ap b/pdks/symbolic/msxlib/cells/xaon21_x1.ap new file mode 100644 index 000000000..ec6bccd4b --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaon21_x1.ap @@ -0,0 +1,130 @@ +V ALLIANCE : 6 +H xaon21_x1,P, 9/ 8/2014,100 +A 0,0,8000,10000 +R 4000,4000,ref_ref,z_40 +R 4000,5000,ref_ref,z_50 +R 3000,7000,ref_ref,a2_70 +R 2000,7000,ref_ref,a2_70 +R 2000,5000,ref_ref,a2_50 +R 1000,5000,ref_ref,a1_50 +R 1000,3000,ref_ref,a1_30 +R 1000,4000,ref_ref,a1_40 +R 3000,3000,ref_ref,z_30 +R 2000,3000,ref_ref,a1_30 +R 4000,6000,ref_ref,z_60 +R 4000,3000,ref_ref,z_30 +R 2000,6000,ref_ref,a2_60 +R 7000,5000,ref_ref,b_50 +R 3000,5000,ref_ref,b_50 +R 7000,6000,ref_ref,b_60 +R 3000,4000,ref_ref,b_40 +S 6800,3800,6800,5200,200,*,DOWN,POLY +S 6800,300,6800,2100,200,*,UP,POLY +S 6100,1400,6100,3600,800,*,UP,NDIF +S 7400,2600,7400,4000,400,*,UP,ALU1 +S 7400,2800,7400,3400,600,*,UP,NDIF +S 7200,2300,7200,3600,400,*,UP,NDIF +S 6800,2100,6800,3800,200,11,UP,NTRANS +S 3200,300,3200,1200,200,*,DOWN,POLY +S 1200,3600,1200,5200,200,*,UP,POLY +S 6000,9400,6000,9700,200,*,DOWN,POLY +S 4800,9400,4800,9700,200,*,DOWN,POLY +S 3600,9400,3600,9700,200,*,DOWN,POLY +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 1200,9400,1200,9700,200,*,DOWN,POLY +S 6000,700,6000,3100,400,*,DOWN,ALU1 +S 600,7100,600,7700,600,*,UP,PDIF +S 600,8000,4200,8000,400,*,LEFT,ALU1 +S 600,6900,600,8000,400,*,UP,ALU1 +S 6800,5800,6800,9200,800,*,DOWN,PDIF +S 6800,6900,6800,9300,400,*,UP,ALU1 +S 6000,4000,6000,8000,400,*,DOWN,ALU1 +S 6000,4000,7400,4000,400,*,LEFT,ALU1 +S 3800,1400,3800,3000,600,*,DOWN,NDIF +S 1200,800,1200,1200,200,*,DOWN,POLY +S 2000,800,2000,1200,200,*,DOWN,POLY +S 2000,3600,2000,4600,200,*,UP,POLY +S 5200,900,5200,1200,200,*,DOWN,POLY +S 4400,900,4400,1200,200,*,DOWN,POLY +S 7000,4900,7000,6100,400,*,DOWN,ALU1 +S 3000,3900,3000,5100,400,*,DOWN,ALU1 +S 2400,5100,2400,5600,200,*,DOWN,POLY +S 4000,6000,4200,6000,600,*,LEFT,ALU1 +S 3000,3000,3000,3000,400,z,LEFT,CALU1 +S 4000,3000,4000,6000,400,z,DOWN,CALU1 +S 4000,2900,4000,6100,400,*,DOWN,ALU1 +S 600,1400,600,3400,600,*,UP,NDIF +S 1200,1200,1200,3600,200,09,UP,NTRANS +S 1600,1400,1600,3400,400,n2,UP,NDIF +S 2800,2000,2800,3400,400,*,DOWN,NDIF +S 3600,1400,3600,3400,400,*,UP,NDIF +S 3200,1200,3200,3600,200,08,UP,NTRANS +S 2000,1200,2000,3600,200,10,UP,NTRANS +S 2600,1400,2600,3400,600,*,UP,NDIF +S 2500,2000,5000,2000,400,*,LEFT,ALU1 +S 5000,3400,5200,3400,600,*,RIGHT,ALU1 +S 4200,7000,5000,7000,400,*,LEFT,ALU1 +S 5000,2000,5000,7000,400,*,UP,ALU1 +S 6000,5200,6800,5200,200,*,RIGHT,POLY +S 5300,8000,6000,8000,400,*,LEFT,ALU1 +S 3600,5200,4000,5200,200,*,RIGHT,POLY +S 4800,5600,4800,9400,200,04,DOWN,PTRANS +S 5400,5800,5400,9200,600,*,DOWN,PDIF +S 6000,5600,6000,9400,200,05,DOWN,PTRANS +S 2400,5600,2400,9400,200,02,DOWN,PTRANS +S 3000,5800,3000,9200,600,*,UP,PDIF +S 3600,5600,3600,9400,200,03,DOWN,PTRANS +S 4000,4200,6000,4200,200,*,RIGHT,POLY +S 4000,4200,4000,5200,200,*,DOWN,POLY +S 4200,7000,4200,8000,400,*,UP,ALU1 +S 4000,5800,4000,9200,600,*,UP,PDIF +S 1700,5800,1700,9200,600,*,UP,PDIF +S 4400,2800,4400,4200,200,*,UP,POLY +S 3000,7000,3000,7000,400,a2,LEFT,CALU1 +S 2000,7000,3000,7000,600,*,LEFT,ALU1 +S 2000,4900,2000,7100,400,*,UP,ALU1 +S 2000,5000,2000,7000,400,a2,DOWN,CALU1 +S 1200,5600,1200,9400,200,01,DOWN,PTRANS +S 800,5800,800,9200,400,*,UP,PDIF +S 4400,1200,4400,2800,200,06,UP,NTRANS +S 5200,1200,5200,2800,200,07,UP,NTRANS +S 4700,1400,4700,2600,400,n1,UP,NDIF +S 3200,300,6800,300,200,*,RIGHT,POLY +S 1000,3000,2000,3000,600,*,LEFT,ALU1 +S 1000,3000,1000,5000,400,a1,DOWN,CALU1 +S 1000,2900,1000,5100,400,*,DOWN,ALU1 +S 2000,3000,2000,3000,400,a1,LEFT,CALU1 +S 600,700,600,2100,400,*,DOWN,ALU1 +S 3000,3000,4000,3000,600,*,RIGHT,ALU1 +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,8000,5000,10000,xaon21_x1,LEFT,TALU8 +S 0,2200,8000,2200,5200,*,LEFT,PWELL +S 0,7600,8000,7600,5600,*,LEFT,NWELL +S 7000,5000,7000,6000,400,b,DOWN,CALU1 +S 3000,4000,3000,5000,400,b,UP,CALU1 +V 7300,700,CONT_BODY_P,* +V 7400,2700,CONT_DIF_N,bn +V 7400,3500,CONT_DIF_N,bn +V 6000,3000,CONT_DIF_N,* +V 6000,2000,CONT_DIF_N,* +V 600,7800,CONT_DIF_P,an +V 600,7000,CONT_DIF_P,an +V 6800,9000,CONT_DIF_P,* +V 6800,8000,CONT_DIF_P,* +V 6800,7000,CONT_DIF_P,* +V 3800,2900,CONT_DIF_N,* +V 7000,5000,CONT_POLY,* +V 3000,4200,CONT_POLY,* +V 5000,5000,CONT_POLY,an +V 6000,4400,CONT_POLY,bn +V 5400,8000,CONT_DIF_P,bn +V 4200,6000,CONT_DIF_P,* +V 1800,9000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,an +V 2000,5000,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 5200,3400,CONT_POLY,an +V 600,2000,CONT_DIF_N,* +V 2600,2000,CONT_DIF_N,an +EOF diff --git a/pdks/symbolic/msxlib/cells/xaon21_x1.vbe b/pdks/symbolic/msxlib/cells/xaon21_x1.vbe new file mode 100644 index 000000000..79f01d2ab --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaon21_x1.vbe @@ -0,0 +1,44 @@ +ENTITY xaon21_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 8000; + CONSTANT cin_b : NATURAL := 10; + CONSTANT cin_a1 : NATURAL := 7; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT rdown_b_z : NATURAL := 2130; + CONSTANT rdown_a1_z : NATURAL := 2060; + CONSTANT rdown_a2_z : NATURAL := 2060; + CONSTANT rup_b_z : NATURAL := 1980; + CONSTANT rup_a1_z : NATURAL := 2500; + CONSTANT rup_a2_z : NATURAL := 2500; + CONSTANT tplh_a1_z : NATURAL := 78; + CONSTANT tplh_a2_z : NATURAL := 73; + CONSTANT tphl_b_z : NATURAL := 27; + CONSTANT tplh_b_z : NATURAL := 82; + CONSTANT tphh_b_z : NATURAL := 51; + CONSTANT tphl_a1_z : NATURAL := 69; + CONSTANT tphl_a2_z : NATURAL := 70; + CONSTANT tpll_a1_z : NATURAL := 105; + CONSTANT tpll_a2_z : NATURAL := 99; + CONSTANT tpll_b_z : NATURAL := 83; + CONSTANT tphh_a1_z : NATURAL := 100; + CONSTANT tphh_a2_z : NATURAL := 101; + CONSTANT transistors : NATURAL := 11 +); +PORT ( + b : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xaon21_x1; + +ARCHITECTURE behaviour_data_flow OF xaon21_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xaon21_x1" + SEVERITY WARNING; + z <= (b xor (a1 and a2)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/xaon22_x05.ap b/pdks/symbolic/msxlib/cells/xaon22_x05.ap new file mode 100644 index 000000000..f014b420f --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaon22_x05.ap @@ -0,0 +1,164 @@ +V ALLIANCE : 6 +H xaon22_x05,P, 9/ 8/2014,100 +A 0,0,10000,10000 +R 2000,4000,ref_ref,a1_40 +R 8000,7000,ref_ref,b1_70 +R 8000,6000,ref_ref,b1_60 +R 8000,4000,ref_ref,b2_40 +R 8000,3000,ref_ref,b2_30 +R 8000,2000,ref_ref,b2_20 +R 5000,3000,ref_ref,z_30 +R 3000,4000,ref_ref,a2_40 +R 3000,5000,ref_ref,a2_50 +R 2000,6000,ref_ref,a2_60 +R 4000,3000,ref_ref,z_30 +R 4000,6000,ref_ref,z_60 +R 4000,5000,ref_ref,z_50 +R 4000,4000,ref_ref,z_40 +R 3000,6000,ref_ref,a2_60 +R 1000,4000,ref_ref,a1_40 +R 1000,3000,ref_ref,a1_30 +R 1000,5000,ref_ref,a1_50 +R 7000,6000,ref_ref,b1_60 +R 8000,5000,ref_ref,b1_50 +R 9000,2000,ref_ref,b2_20 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 7000,6000,8000,6000,600,*,RIGHT,ALU1 +S 8000,4900,8000,7100,400,*,UP,ALU1 +S 6200,4800,6200,8000,400,*,UP,ALU1 +S 1600,1900,1600,3100,400,n2,UP,NDIF +S 2600,2000,6000,2000,400,*,LEFT,ALU1 +S 2600,2000,2600,3100,400,*,DOWN,ALU1 +S 2000,4000,2000,4000,400,a1,LEFT,CALU1 +S 1000,4000,2000,4000,600,*,LEFT,ALU1 +S 5200,2400,5200,3300,200,6z,UP,NTRANS +S 6000,2400,6000,3300,200,5z,UP,NTRANS +S 4000,1700,4000,3300,200,4z,UP,NTRANS +S 3200,1700,3200,3300,200,3z,UP,NTRANS +S 8600,1700,8600,3300,200,4b,UP,NTRANS +S 7800,1700,7800,3300,200,3b,UP,NTRANS +S 2000,1700,2000,3300,200,4a,UP,NTRANS +S 1200,1700,1200,3300,200,3a,UP,NTRANS +S 5600,2600,5600,3100,400,n1,UP,NDIF +S 6800,1900,6800,3100,1000,*,UP,NDIF +S 9000,1900,9000,3100,400,*,UP,NDIF +S 3200,700,8600,700,200,*,RIGHT,POLY +S 8600,3300,8600,4000,200,*,UP,POLY +S 8600,700,8600,1700,200,*,DOWN,POLY +S 2000,3300,2000,4600,200,*,UP,POLY +S 2000,4600,2800,4600,200,*,RIGHT,POLY +S 1200,3300,1200,5200,200,*,UP,POLY +S 2000,1300,2000,1700,200,*,DOWN,POLY +S 1200,1300,1200,1700,200,*,DOWN,POLY +S 3200,700,3200,1700,200,*,DOWN,POLY +S 4400,1900,4400,3100,400,*,DOWN,NDIF +S 600,1900,600,3100,600,*,UP,NDIF +S 2600,1900,2600,3100,600,*,UP,NDIF +S 3200,3300,3200,3700,200,*,UP,POLY +S 4000,3300,4000,3700,200,*,UP,POLY +S 5200,2000,5200,2400,200,*,DOWN,POLY +S 6000,2000,6000,2400,200,*,DOWN,POLY +S 4000,1300,7800,1300,200,*,RIGHT,POLY +S 7800,3300,7800,5500,200,*,UP,POLY +S 7000,700,7000,3100,400,*,DOWN,ALU1 +S 8000,2000,8000,4000,400,b2,DOWN,CALU1 +S 4000,3000,5000,3000,600,*,RIGHT,ALU1 +S 5000,3000,5000,3000,400,z,LEFT,CALU1 +S 5200,3300,5200,4700,200,*,UP,POLY +S 4400,2600,4400,3100,600,*,UP,NDIF +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,5000,10000,5000,10000,xaon22_x05,LEFT,TALU8 +S 0,2200,10000,2200,5200,*,LEFT,PWELL +S 0,7600,10000,7600,5600,*,LEFT,NWELL +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 2000,6000,3000,6000,600,*,LEFT,ALU1 +S 3000,4000,3000,6000,400,a2,DOWN,CALU1 +S 3000,3900,3000,6100,400,*,UP,ALU1 +S 2000,6000,2000,6000,400,a2,LEFT,CALU1 +S 4000,3000,4000,6000,400,z,DOWN,CALU1 +S 600,700,600,2100,400,*,DOWN,ALU1 +S 2800,2300,2800,3100,400,*,DOWN,NDIF +S 1000,2900,1000,5100,400,*,DOWN,ALU1 +S 1000,3000,1000,5000,400,a1,DOWN,CALU1 +S 6000,2000,6000,4000,400,*,UP,ALU1 +S 2200,7700,2200,9300,400,*,UP,ALU1 +S 1200,5200,1600,5200,200,*,RIGHT,POLY +S 5400,4000,6000,4000,400,*,RIGHT,ALU1 +S 6800,5800,8000,5800,200,*,LEFT,POLY +S 8000,1900,8000,4000,400,*,DOWN,ALU1 +S 6800,6200,6800,8200,200,1b,DOWN,PTRANS +S 7000,6000,7000,6000,400,b1,LEFT,CALU1 +S 8000,5000,8000,7000,400,b1,UP,CALU1 +S 6200,8000,9400,8000,400,*,RIGHT,ALU1 +S 7800,6400,7800,9100,1400,*,DOWN,PDIF +S 8800,6200,8800,8200,200,2b,DOWN,PTRANS +S 9200,6400,9200,8000,400,*,DOWN,PDIF +S 9400,6600,9400,7200,600,*,UP,PDIF +S 9000,2000,9000,2000,400,b2,LEFT,CALU1 +S 8000,4000,8600,4000,600,*,LEFT,ALU1 +S 8000,2000,9000,2000,600,*,RIGHT,ALU1 +S 9400,2900,9400,8000,400,*,UP,ALU1 +S 9100,3000,9400,3000,600,*,RIGHT,ALU1 +S 8800,4000,8800,6200,200,*,UP,POLY +S 8800,8200,8800,8600,200,*,UP,POLY +S 6800,8200,6800,8600,200,*,UP,POLY +S 4000,4700,6400,4700,200,*,LEFT,POLY +S 4000,6500,4600,6500,600,*,LEFT,ALU1 +S 5200,6200,5200,8200,200,2z,DOWN,PTRANS +S 4600,6400,4600,8000,600,*,UP,PDIF +S 4000,6200,4000,8200,200,1z,DOWN,PTRANS +S 4000,2900,4000,6600,400,*,DOWN,ALU1 +S 5400,4000,5400,7500,400,*,DOWN,ALU1 +S 6000,6400,6000,8000,600,*,UP,PDIF +S 5200,8200,5200,8600,200,*,UP,POLY +S 4000,8200,4000,8600,200,*,UP,POLY +S 5200,5500,5200,6200,200,*,DOWN,POLY +S 4900,5500,5400,5500,400,*,LEFT,ALU1 +S 2800,6200,2800,8200,200,2a,DOWN,PTRANS +S 3400,6400,3400,8000,600,*,UP,PDIF +S 2200,6400,2200,8000,600,*,UP,PDIF +S 1600,6200,1600,8200,200,1a,DOWN,PTRANS +S 1200,6400,1200,8000,400,*,UP,PDIF +S 3000,6900,3000,7500,400,*,UP,ALU1 +S 3000,7500,5400,7500,400,*,LEFT,ALU1 +S 1000,6900,3000,6900,400,*,LEFT,ALU1 +S 2800,8200,2800,8600,200,*,UP,POLY +S 1600,8200,1600,8600,200,*,UP,POLY +S 1600,5200,1600,6200,200,*,DOWN,POLY +S 2800,4800,2800,6200,200,*,DOWN,POLY +S 4000,4700,4000,6200,200,*,UP,POLY +S 1000,7200,1000,7800,600,*,UP,PDIF +S 1000,6900,1000,8000,400,*,UP,ALU1 +S 3600,1900,3600,3100,400,n3,UP,NDIF +S 8200,1900,8200,3100,400,n4,UP,NDIF +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 6200,4900,CONT_POLY,bn +V 6200,7300,CONT_DIF_P,bn +V 6200,6500,CONT_DIF_P,bn +V 8200,9000,CONT_DIF_P,* +V 7400,9000,CONT_DIF_P,* +V 2600,2200,CONT_DIF_N,an +V 2600,3000,CONT_DIF_N,an +V 9200,3000,CONT_DIF_N,bn +V 3000,4800,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 7000,2000,CONT_DIF_N,* +V 8600,4000,CONT_POLY,* +V 7000,3000,CONT_DIF_N,* +V 6000,3900,CONT_POLY,an +V 4600,3000,CONT_DIF_N,* +V 600,2000,CONT_DIF_N,* +V 2200,7800,CONT_DIF_P,* +V 8000,5600,CONT_POLY,* +V 9400,6500,CONT_DIF_P,bn +V 9400,7300,CONT_DIF_P,bn +V 4600,6500,CONT_DIF_P,* +V 5000,5500,CONT_POLY,an +V 3400,7500,CONT_DIF_P,an +V 1000,7900,CONT_DIF_P,an +V 1000,7100,CONT_DIF_P,an +EOF diff --git a/pdks/symbolic/msxlib/cells/xaon22_x05.vbe b/pdks/symbolic/msxlib/cells/xaon22_x05.vbe new file mode 100644 index 000000000..94984ef52 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaon22_x05.vbe @@ -0,0 +1,52 @@ +ENTITY xaon22_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 10000; + CONSTANT cin_b1 : NATURAL := 7; + CONSTANT cin_b2 : NATURAL := 7; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT rdown_b1_z : NATURAL := 3810; + CONSTANT rdown_b2_z : NATURAL := 3830; + CONSTANT rdown_a1_z : NATURAL := 3880; + CONSTANT rdown_a2_z : NATURAL := 3870; + CONSTANT rup_b1_z : NATURAL := 3950; + CONSTANT rup_b2_z : NATURAL := 3980; + CONSTANT rup_a1_z : NATURAL := 5000; + CONSTANT rup_a2_z : NATURAL := 4990; + CONSTANT tplh_a1_z : NATURAL := 100; + CONSTANT tplh_a2_z : NATURAL := 94; + CONSTANT tphl_b1_z : NATURAL := 34; + CONSTANT tphl_b2_z : NATURAL := 36; + CONSTANT tplh_b1_z : NATURAL := 115; + CONSTANT tplh_b2_z : NATURAL := 118; + CONSTANT tphh_b1_z : NATURAL := 61; + CONSTANT tphh_b2_z : NATURAL := 67; + CONSTANT tphl_a1_z : NATURAL := 75; + CONSTANT tphl_a2_z : NATURAL := 77; + CONSTANT tpll_a1_z : NATURAL := 121; + CONSTANT tpll_a2_z : NATURAL := 114; + CONSTANT tpll_b1_z : NATURAL := 111; + CONSTANT tpll_b2_z : NATURAL := 107; + CONSTANT tphh_a1_z : NATURAL := 107; + CONSTANT tphh_a2_z : NATURAL := 107; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xaon22_x05; + +ARCHITECTURE behaviour_data_flow OF xaon22_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xaon22_x05" + SEVERITY WARNING; + z <= ((b1 and b2) xor (a1 and a2)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/xaon22_x1.ap b/pdks/symbolic/msxlib/cells/xaon22_x1.ap new file mode 100644 index 000000000..5f59fce7a --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaon22_x1.ap @@ -0,0 +1,166 @@ +V ALLIANCE : 6 +H xaon22_x1,P,21/10/2004,100 +A 0,0,10000,10000 +R 8000,7000,ref_ref,b1_70 +R 8000,6000,ref_ref,b1_60 +R 8000,4000,ref_ref,b2_40 +R 8000,3000,ref_ref,b2_30 +R 8000,2000,ref_ref,b2_20 +R 5000,3000,ref_ref,z_30 +R 3000,4000,ref_ref,a2_40 +R 3000,5000,ref_ref,a2_50 +R 2000,6000,ref_ref,a2_60 +R 4000,3000,ref_ref,z_30 +R 4000,6000,ref_ref,z_60 +R 4000,5000,ref_ref,z_50 +R 4000,4000,ref_ref,z_40 +R 3000,6000,ref_ref,a2_60 +R 1000,4000,ref_ref,a1_40 +R 1000,3000,ref_ref,a1_30 +R 9000,2000,ref_ref,b2_20 +R 4000,7000,ref_ref,z_70 +R 2000,5000,ref_ref,a1_50 +R 1000,5000,ref_ref,a1_50 +R 8000,5000,ref_ref,b1_50 +R 7000,7000,ref_ref,b1_70 +S 4000,3000,4000,7000,400,z,DOWN,CALU1 +S 4200,1500,4200,3400,400,n3,UP,NDIF +S 8000,2000,8000,4000,400,b2,DOWN,CALU1 +S 5000,3000,5000,3000,400,z,LEFT,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,7600,10000,7600,5600,*,LEFT,NWELL +S 0,2200,10000,2200,5200,*,LEFT,PWELL +S 0,5000,10000,5000,10000,xaon22_x1,LEFT,TALU8 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 2000,6000,3000,6000,600,*,LEFT,ALU1 +S 3000,4000,3000,6000,400,a2,DOWN,CALU1 +S 3000,3900,3000,6100,400,*,UP,ALU1 +S 2000,6000,2000,6000,400,a2,LEFT,CALU1 +S 8000,5000,8000,7000,400,b1,UP,CALU1 +S 6200,8000,9400,8000,400,*,RIGHT,ALU1 +S 9000,2000,9000,2000,400,b2,LEFT,CALU1 +S 8000,2000,9000,2000,600,*,RIGHT,ALU1 +S 5200,5500,5200,6200,200,*,DOWN,POLY +S 1000,6900,3000,6900,400,*,LEFT,ALU1 +S 7200,700,7200,3100,400,*,DOWN,ALU1 +S 6600,1500,6600,1900,200,*,DOWN,POLY +S 5800,1500,5800,1900,200,*,DOWN,POLY +S 4600,900,7800,900,200,*,RIGHT,POLY +S 3800,300,3800,1300,200,*,DOWN,POLY +S 3800,300,8600,300,200,*,RIGHT,POLY +S 3000,8000,5400,8000,400,*,LEFT,ALU1 +S 3000,6900,3000,8000,400,*,UP,ALU1 +S 4000,7000,4600,7000,600,*,LEFT,ALU1 +S 4000,2900,4000,7100,400,*,DOWN,ALU1 +S 3000,800,3000,3700,400,*,DOWN,NDIF +S 2600,600,2600,3900,200,4a,UP,NTRANS +S 3200,2000,3200,3100,400,*,DOWN,ALU1 +S 3200,2000,6000,2000,400,*,LEFT,ALU1 +S 2200,800,2200,3700,400,n2,UP,NDIF +S 1800,600,1800,3900,200,3a,UP,NTRANS +S 1200,700,1200,2100,400,*,DOWN,ALU1 +S 1100,800,1100,3700,600,*,UP,NDIF +S 1800,3900,1800,5200,200,*,UP,POLY +S 2600,3900,2600,4700,200,*,UP,POLY +S 1000,5000,2000,5000,600,*,LEFT,ALU1 +S 2000,5000,2000,5000,400,a1,LEFT,CALU1 +S 1000,2900,1000,5100,400,*,DOWN,ALU1 +S 1000,3000,1000,5000,400,a1,DOWN,CALU1 +S 4000,3000,5200,3000,600,*,RIGHT,ALU1 +S 2800,5900,2800,9400,200,2a,DOWN,PTRANS +S 3400,6100,3400,9200,600,*,UP,PDIF +S 4000,5900,4000,9400,200,1z,DOWN,PTRANS +S 2200,6100,2200,9200,600,*,UP,PDIF +S 1600,5900,1600,9400,200,1a,DOWN,PTRANS +S 1200,6100,1200,9200,400,*,UP,PDIF +S 6000,6100,6000,9200,600,*,UP,PDIF +S 5200,5900,5200,9400,200,2z,DOWN,PTRANS +S 4600,6100,4600,9200,600,*,UP,PDIF +S 6800,5900,6800,9400,200,1b,DOWN,PTRANS +S 7800,6100,7800,9200,1400,*,DOWN,PDIF +S 8800,5900,8800,9400,200,2b,DOWN,PTRANS +S 4000,4500,5800,4500,200,*,LEFT,POLY +S 5900,5300,6200,5300,400,*,LEFT,ALU1 +S 6200,5300,6200,8000,400,*,UP,ALU1 +S 5400,6100,5400,8000,400,*,DOWN,ALU1 +S 2200,7900,2200,9300,400,*,UP,ALU1 +S 4000,4500,4000,5900,200,*,UP,POLY +S 1600,5200,1600,5900,200,*,DOWN,POLY +S 2800,4800,2800,5900,200,*,DOWN,POLY +S 4600,3600,4600,3900,200,*,UP,POLY +S 3800,3600,3800,3900,200,*,UP,POLY +S 4600,1300,4600,3600,200,4z,UP,NTRANS +S 3800,1300,3800,3600,200,3z,UP,NTRANS +S 3200,1500,3200,3400,600,*,UP,NDIF +S 5000,1500,5000,3400,400,*,DOWN,NDIF +S 5200,2000,5200,3400,600,*,DOWN,NDIF +S 5800,1800,5800,3600,200,6z,UP,NTRANS +S 6600,1800,6600,3600,200,5z,UP,NTRANS +S 6200,2000,6200,3400,400,n1,UP,NDIF +S 5400,2000,5400,3400,400,*,DOWN,NDIF +S 5800,3600,5800,5100,200,*,UP,POLY +S 5000,4200,5000,6100,400,*,DOWN,ALU1 +S 6000,2000,6000,4200,400,*,UP,ALU1 +S 5000,4200,6700,4200,400,*,LEFT,ALU1 +S 9200,6100,9200,9200,400,*,DOWN,PDIF +S 9100,3300,9600,3300,400,*,LEFT,ALU1 +S 7000,7000,7000,7000,400,b1,LEFT,CALU1 +S 7000,7000,8000,7000,600,*,RIGHT,ALU1 +S 8800,4200,8800,5900,200,*,UP,POLY +S 1800,300,1800,600,200,*,DOWN,POLY +S 2600,300,2600,600,200,*,DOWN,POLY +S 1600,9400,1600,9700,200,*,UP,POLY +S 2800,9400,2800,9700,200,*,UP,POLY +S 4000,9400,4000,9700,200,*,UP,POLY +S 5200,9400,5200,9700,200,*,UP,POLY +S 6800,9400,6800,9700,200,*,UP,POLY +S 8800,9400,8800,9700,200,*,UP,POLY +S 1000,7300,1000,7900,600,*,UP,PDIF +S 1000,6900,1000,8100,400,*,UP,ALU1 +S 8200,1500,8200,3400,400,n4,UP,NDIF +S 9000,1500,9000,3400,400,*,UP,NDIF +S 8600,1300,8600,3600,200,4b,UP,NTRANS +S 7400,1500,7400,3400,400,*,DOWN,NDIF +S 7800,1300,7800,3600,200,3b,UP,NTRANS +S 7200,1500,7200,3400,600,*,UP,NDIF +S 7800,900,7800,1300,200,*,DOWN,POLY +S 8600,300,8600,1300,200,*,DOWN,POLY +S 7800,3600,7800,4900,200,*,UP,POLY +S 8000,5000,8000,7100,600,*,UP,ALU1 +S 6800,5200,7600,5200,200,*,RIGHT,POLY +S 6800,5200,6800,5900,200,*,DOWN,POLY +S 7500,5000,8100,5000,400,*,RIGHT,ALU1 +S 8000,4200,8700,4200,400,*,LEFT,ALU1 +S 8000,1900,8000,4200,400,*,DOWN,ALU1 +S 9400,6300,9400,6900,600,*,UP,PDIF +S 9600,3300,9600,6100,400,*,DOWN,ALU1 +S 9400,6100,9400,8000,400,*,UP,ALU1 +V 7400,9000,CONT_DIF_P,* +V 8200,9000,CONT_DIF_P,* +V 7200,3000,CONT_DIF_N,* +V 5200,3000,CONT_DIF_N,* +V 3400,8000,CONT_DIF_P,an +V 4600,7000,CONT_DIF_P,* +V 3200,3000,CONT_DIF_N,an +V 3200,2200,CONT_DIF_N,an +V 1200,2000,CONT_DIF_N,* +V 1200,1000,CONT_DIF_N,* +V 3000,4500,CONT_POLY,* +V 1600,5000,CONT_POLY,* +V 6200,7800,CONT_DIF_P,bn +V 6200,7000,CONT_DIF_P,bn +V 6200,6200,CONT_DIF_P,bn +V 5000,5300,CONT_POLY,an +V 6000,5300,CONT_POLY,bn +V 2200,8000,CONT_DIF_P,* +V 2200,9000,CONT_DIF_P,* +V 6600,4200,CONT_POLY,an +V 9200,3300,CONT_DIF_N,bn +V 1000,8000,CONT_DIF_P,an +V 1000,7200,CONT_DIF_P,an +V 7600,5000,CONT_POLY,* +V 8600,4200,CONT_POLY,* +V 7200,2000,CONT_DIF_N,* +V 9400,6200,CONT_DIF_P,bn +V 9400,7000,CONT_DIF_P,bn +EOF diff --git a/pdks/symbolic/msxlib/cells/xaon22_x1.vbe b/pdks/symbolic/msxlib/cells/xaon22_x1.vbe new file mode 100644 index 000000000..fb62fa351 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xaon22_x1.vbe @@ -0,0 +1,52 @@ +ENTITY xaon22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 10000; + CONSTANT cin_b1 : NATURAL := 10; + CONSTANT cin_b2 : NATURAL := 10; + CONSTANT cin_a1 : NATURAL := 8; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT rdown_b1_z : NATURAL := 1960; + CONSTANT rdown_b2_z : NATURAL := 1970; + CONSTANT rdown_a1_z : NATURAL := 1970; + CONSTANT rdown_a2_z : NATURAL := 1970; + CONSTANT rup_b1_z : NATURAL := 2330; + CONSTANT rup_b2_z : NATURAL := 2350; + CONSTANT rup_a1_z : NATURAL := 2880; + CONSTANT rup_a2_z : NATURAL := 2870; + CONSTANT tplh_a1_z : NATURAL := 98; + CONSTANT tplh_a2_z : NATURAL := 89; + CONSTANT tphl_b1_z : NATURAL := 37; + CONSTANT tphl_b2_z : NATURAL := 39; + CONSTANT tplh_b1_z : NATURAL := 103; + CONSTANT tplh_b2_z : NATURAL := 106; + CONSTANT tphh_b1_z : NATURAL := 66; + CONSTANT tphh_b2_z : NATURAL := 71; + CONSTANT tphl_a1_z : NATURAL := 65; + CONSTANT tphl_a2_z : NATURAL := 66; + CONSTANT tpll_a1_z : NATURAL := 113; + CONSTANT tpll_a2_z : NATURAL := 104; + CONSTANT tpll_b1_z : NATURAL := 100; + CONSTANT tpll_b2_z : NATURAL := 96; + CONSTANT tphh_a1_z : NATURAL := 94; + CONSTANT tphh_a2_z : NATURAL := 94; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xaon22_x1; + +ARCHITECTURE behaviour_data_flow OF xaon22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xaon22_x1" + SEVERITY WARNING; + z <= ((b1 and b2) xor (a1 and a2)) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/xnr2_x05.ap b/pdks/symbolic/msxlib/cells/xnr2_x05.ap new file mode 100644 index 000000000..d4efc7267 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xnr2_x05.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H xnr2_x05,P, 9/ 8/2014,100 +A 0,0,7000,10000 +R 2000,7000,ref_ref,z_70 +R 5000,7000,ref_ref,b_70 +R 5000,8000,ref_ref,b_80 +R 4000,6000,ref_ref,b_60 +R 5000,6000,ref_ref,b_60 +R 2000,8000,ref_ref,z_80 +R 5000,3000,ref_ref,a_30 +R 3000,8000,ref_ref,z_80 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,7000,ref_ref,z_70 +R 2000,3000,ref_ref,z_30 +R 2000,4000,ref_ref,z_40 +R 5000,4000,ref_ref,a_40 +R 5000,2000,ref_ref,a_20 +R 6000,2000,ref_ref,a_20 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 2200,8500,2200,8800,200,*,UP,POLY +S 1400,8500,1400,8800,200,*,UP,POLY +S 800,7900,800,9300,400,*,UP,ALU1 +S 800,6700,800,8300,600,*,DOWN,PDIF +S 700,6700,700,8300,600,*,DOWN,PDIF +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 2000,7000,2000,8000,400,*,DOWN,ALU1 +S 1000,7000,2000,7000,600,*,RIGHT,ALU1 +S 2000,8100,3100,8100,400,*,LEFT,ALU1 +S 2000,8000,3100,8000,400,*,LEFT,ALU1 +S 1000,4000,1000,7000,400,*,UP,ALU1 +S 1000,4000,1000,7000,400,z,UP,CALU1 +S 2000,7000,2000,8000,400,z,DOWN,CALU1 +S 5000,6000,5000,8000,400,b,UP,CALU1 +S 4000,7000,4000,8100,400,*,UP,ALU1 +S 4700,900,4700,3100,1600,*,UP,NDIF +S 0,5000,7000,5000,10000,xnr2_x05,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 6200,2600,6200,3100,400,*,UP,NDIF +S 5800,2400,5800,3300,200,9,UP,NTRANS +S 3000,2600,3000,3100,600,*,UP,NDIF +S 2400,2400,2400,3300,200,7,UP,NTRANS +S 3600,2400,3600,3300,200,8,UP,NTRANS +S 3600,2000,3600,2400,200,*,DOWN,POLY +S 5800,2000,5800,2400,200,*,DOWN,POLY +S 1800,2600,1800,3100,600,*,UP,NDIF +S 1200,2400,1200,3300,200,6,UP,NTRANS +S 800,2600,800,3100,400,*,DOWN,NDIF +S 1000,4000,2000,4000,600,*,LEFT,ALU1 +S 2000,3000,2000,4000,400,z,DOWN,CALU1 +S 1900,2900,1900,4100,600,*,DOWN,ALU1 +S 600,2000,600,2800,400,*,DOWN,ALU1 +S 1200,2000,1200,2400,200,*,DOWN,POLY +S 2400,2000,2400,2400,200,*,DOWN,POLY +S 3000,2900,3000,7000,400,*,UP,ALU1 +S 3000,7000,4000,7000,400,*,LEFT,ALU1 +S 3800,5900,5500,5900,600,*,RIGHT,ALU1 +S 2200,6100,2600,6100,200,*,RIGHT,POLY +S 2600,3700,2600,6100,200,*,DOWN,POLY +S 5800,3300,5800,6500,200,*,DOWN,POLY +S 6200,6700,6200,8300,400,*,DOWN,PDIF +S 5800,6500,5800,8500,200,5,DOWN,PTRANS +S 4600,6500,4600,8500,200,4,DOWN,PTRANS +S 4000,6700,4000,8300,600,*,UP,PDIF +S 3400,6500,3400,8500,200,3,DOWN,PTRANS +S 2200,6500,2200,8500,200,2,DOWN,PTRANS +S 2800,6700,2800,8300,600,*,UP,PDIF +S 1400,6500,1400,8500,200,1,DOWN,PTRANS +S 1700,6700,1700,8300,400,n1,UP,PDIF +S 5200,6700,5200,9100,600,*,UP,PDIF +S 3400,8500,3400,8900,200,*,UP,POLY +S 4600,8500,4600,8900,200,*,UP,POLY +S 5800,8500,5800,8900,200,*,UP,POLY +S 5000,6000,5000,8100,400,*,UP,ALU1 +S 4000,6000,4000,6000,400,b,LEFT,CALU1 +S 3000,8000,3000,8000,400,z,LEFT,CALU1 +S 2400,3300,2400,3800,200,*,UP,POLY +S 3400,5700,3400,6500,200,*,DOWN,POLY +S 6000,2000,6000,2000,400,a,LEFT,CALU1 +S 5000,2000,6100,2000,400,*,RIGHT,ALU1 +S 5000,2000,5000,4000,600,*,DOWN,ALU1 +S 5000,2000,5000,4000,400,a,DOWN,CALU1 +S 600,2000,3800,2000,400,*,RIGHT,ALU1 +S 4600,3700,4600,6500,200,*,DOWN,POLY +S 3600,3700,4600,3700,200,*,LEFT,POLY +S 2800,5000,3700,5000,200,*,LEFT,POLY +S 3800,4900,6400,4900,400,*,RIGHT,ALU1 +S 3800,2000,3800,4900,400,*,UP,ALU1 +S 6400,6900,6400,7500,600,*,UP,PDIF +S 6400,2900,6400,7700,400,*,UP,ALU1 +S 1800,5000,3000,5000,600,*,LEFT,ALU1 +S 1400,4800,1400,6500,200,*,DOWN,POLY +S 1200,3300,1200,4900,200,*,UP,POLY +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 800,8000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,an +V 4200,1000,CONT_DIF_N,* +V 5200,9000,CONT_DIF_P,* +V 5200,1000,CONT_DIF_N,* +V 3000,3000,CONT_DIF_N,an +V 6400,3000,CONT_DIF_N,bn +V 2800,8000,CONT_DIF_P,* +V 1800,3000,CONT_DIF_N,* +V 600,2700,CONT_DIF_N,bn +V 3800,5900,CONT_POLY,* +V 5400,5900,CONT_POLY,* +V 6400,6800,CONT_DIF_P,bn +V 4000,7200,CONT_DIF_P,an +V 5000,3900,CONT_POLY,* +V 3800,4800,CONT_POLY,bn +V 6400,7600,CONT_DIF_P,bn +V 1800,5000,CONT_POLY,an +EOF diff --git a/pdks/symbolic/msxlib/cells/xnr2_x05.vbe b/pdks/symbolic/msxlib/cells/xnr2_x05.vbe new file mode 100644 index 000000000..283bce386 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xnr2_x05.vbe @@ -0,0 +1,36 @@ +ENTITY xnr2_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 3580; + CONSTANT rdown_a_z : NATURAL := 3690; + CONSTANT rup_b_z : NATURAL := 4620; + CONSTANT rup_a_z : NATURAL := 4840; + CONSTANT tphl_a_z : NATURAL := 67; + CONSTANT tphl_b_z : NATURAL := 72; + CONSTANT tplh_b_z : NATURAL := 42; + CONSTANT tplh_a_z : NATURAL := 72; + CONSTANT tphh_b_z : NATURAL := 86; + CONSTANT tpll_b_z : NATURAL := 70; + CONSTANT tphh_a_z : NATURAL := 101; + CONSTANT tpll_a_z : NATURAL := 97; + CONSTANT transistors : NATURAL := 9 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xnr2_x05; + +ARCHITECTURE behaviour_data_flow OF xnr2_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xnr2_x05" + SEVERITY WARNING; + z <= not ((b xor a)) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/xnr2_x1.ap b/pdks/symbolic/msxlib/cells/xnr2_x1.ap new file mode 100644 index 000000000..b9d72a367 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xnr2_x1.ap @@ -0,0 +1,114 @@ +V ALLIANCE : 6 +H xnr2_x1,P, 9/ 8/2014,100 +A 0,0,7000,10000 +R 1000,8000,ref_ref,z_80 +R 2000,8000,ref_ref,z_80 +R 4000,3000,ref_ref,a_30 +R 5000,5000,ref_ref,b_50 +R 4000,5000,ref_ref,b_50 +R 4000,4000,ref_ref,b_40 +R 5000,4000,ref_ref,a_40 +R 5000,3000,ref_ref,a_30 +R 3000,8000,ref_ref,z_80 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +S 1100,700,1900,700,600,*,RIGHT,PTIE +S 1000,8000,3100,8000,400,*,LEFT,ALU1 +S 1000,8100,3100,8100,400,*,LEFT,ALU1 +S 1400,9400,1400,9700,200,*,UP,POLY +S 2200,9400,2200,9700,200,*,UP,POLY +S 3400,9400,3400,9700,200,*,UP,POLY +S 4600,9400,4600,9700,200,*,UP,POLY +S 5800,9400,5800,9700,200,*,UP,POLY +S 5800,1300,5800,1700,200,*,DOWN,POLY +S 2400,1300,2400,1700,200,*,DOWN,POLY +S 3600,1300,3600,1700,200,*,DOWN,POLY +S 1200,1300,1200,1700,200,*,DOWN,POLY +S 6200,5900,6200,9200,400,*,DOWN,PDIF +S 700,5900,700,9200,600,*,DOWN,PDIF +S 5200,5900,5200,9200,600,*,UP,PDIF +S 4000,5900,4000,9200,600,*,UP,PDIF +S 2800,5900,2800,9200,600,*,UP,PDIF +S 1700,5900,1700,9200,400,n1,UP,PDIF +S 5200,6900,5200,9300,400,*,UP,ALU1 +S 2000,7000,4000,7000,400,*,LEFT,ALU1 +S 4000,7000,4000,8100,400,*,UP,ALU1 +S 6400,2000,6400,6900,400,*,UP,ALU1 +S 2800,4400,2800,6000,400,*,DOWN,ALU1 +S 2800,6000,6400,6000,400,*,LEFT,ALU1 +S 6400,6100,6400,6700,600,*,UP,PDIF +S 1800,4500,2000,4500,600,*,LEFT,ALU1 +S 3000,2900,3000,3600,400,*,UP,ALU1 +S 2000,3600,2000,7000,400,*,UP,ALU1 +S 4700,900,4700,3100,1600,*,UP,NDIF +S 800,1900,800,3100,400,*,DOWN,NDIF +S 6200,1900,6200,3100,400,*,UP,NDIF +S 3000,1900,3000,3100,600,*,UP,NDIF +S 1800,1900,1800,3100,600,*,UP,NDIF +S 5000,3000,5000,4000,600,*,DOWN,ALU1 +S 3900,3000,5000,3000,400,*,RIGHT,ALU1 +S 4000,4000,4000,5000,400,b,UP,CALU1 +S 5000,3000,5000,4000,400,a,DOWN,CALU1 +S 3400,5300,4000,5300,200,*,RIGHT,POLY +S 2000,3600,3000,3600,400,*,LEFT,ALU1 +S 1000,2800,1900,2800,400,*,LEFT,ALU1 +S 500,2000,6400,2000,400,*,RIGHT,ALU1 +S 1200,1700,1200,3300,200,6,UP,NTRANS +S 2400,1700,2400,3300,200,7,UP,NTRANS +S 3600,1700,3600,3300,200,8,UP,NTRANS +S 5800,5700,5800,9400,200,5,DOWN,PTRANS +S 1000,3000,1000,8000,400,*,UP,ALU1 +S 1000,3000,1000,8000,400,z,UP,CALU1 +S 0,5000,7000,5000,10000,xnr2_x1,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 1400,4500,2000,4500,600,*,LEFT,POLY +S 5800,3300,5800,5700,200,*,DOWN,POLY +S 3600,3700,4600,3700,200,*,LEFT,POLY +S 2600,3700,2600,5300,200,*,DOWN,POLY +S 4600,3700,4600,5700,200,*,DOWN,POLY +S 4600,5700,4600,9400,200,4,DOWN,PTRANS +S 3400,5700,3400,9400,200,3,DOWN,PTRANS +S 1400,5700,1400,9400,200,1,DOWN,PTRANS +S 2200,5700,2200,9400,200,2,DOWN,PTRANS +S 2200,5300,2600,5300,200,*,RIGHT,POLY +S 1400,4300,1400,5700,200,*,DOWN,POLY +S 2400,3700,2600,3700,200,*,LEFT,POLY +S 5800,1700,5800,3300,200,9,UP,NTRANS +S 4000,3000,4000,3000,400,a,LEFT,CALU1 +S 5000,5000,5000,5000,400,b,LEFT,CALU1 +S 1200,3300,1200,4400,200,*,UP,POLY +S 2000,8000,2000,8000,400,z,LEFT,CALU1 +S 3000,8000,3000,8000,400,z,LEFT,CALU1 +S 6400,2300,6400,2900,600,*,UP,NDIF +S 3900,3900,3900,5000,600,*,UP,ALU1 +S 3800,5000,5500,5000,400,*,RIGHT,ALU1 +V 2000,700,CONT_BODY_P,* +V 1000,700,CONT_BODY_P,* +V 5200,7000,CONT_DIF_P,* +V 5200,8000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,an +V 6400,6800,CONT_DIF_P,bn +V 4200,1000,CONT_DIF_N,* +V 2800,4500,CONT_POLY,bn +V 1800,2800,CONT_DIF_N,* +V 600,2000,CONT_DIF_N,bn +V 6400,6000,CONT_DIF_P,bn +V 5200,9000,CONT_DIF_P,* +V 5200,1000,CONT_DIF_N,* +V 3000,3000,CONT_DIF_N,an +V 1800,4500,CONT_POLY,an +V 6400,3000,CONT_DIF_N,bn +V 5000,3900,CONT_POLY,* +V 2800,8000,CONT_DIF_P,* +V 800,9000,CONT_DIF_P,* +V 5400,5000,CONT_POLY,* +V 4000,7200,CONT_DIF_P,an +V 6400,2200,CONT_DIF_N,bn +V 3800,4900,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/xnr2_x1.vbe b/pdks/symbolic/msxlib/cells/xnr2_x1.vbe new file mode 100644 index 000000000..55a219fd2 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xnr2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY xnr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_b : NATURAL := 10; + CONSTANT cin_a : NATURAL := 7; + CONSTANT rdown_b_z : NATURAL := 2020; + CONSTANT rdown_a_z : NATURAL := 2060; + CONSTANT rup_b_z : NATURAL := 2510; + CONSTANT rup_a_z : NATURAL := 2620; + CONSTANT tphl_a_z : NATURAL := 66; + CONSTANT tphl_b_z : NATURAL := 67; + CONSTANT tplh_b_z : NATURAL := 38; + CONSTANT tplh_a_z : NATURAL := 69; + CONSTANT tphh_b_z : NATURAL := 80; + CONSTANT tpll_b_z : NATURAL := 65; + CONSTANT tphh_a_z : NATURAL := 96; + CONSTANT tpll_a_z : NATURAL := 93; + CONSTANT transistors : NATURAL := 9 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xnr2_x1; + +ARCHITECTURE behaviour_data_flow OF xnr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xnr2_x1" + SEVERITY WARNING; + z <= not ((b xor a)) after 1100 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/xor2_x05.ap b/pdks/symbolic/msxlib/cells/xor2_x05.ap new file mode 100644 index 000000000..fb2b7d188 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xor2_x05.ap @@ -0,0 +1,122 @@ +V ALLIANCE : 6 +H xor2_x05,P, 9/ 8/2014,100 +A 0,0,7000,10000 +R 6000,7000,ref_ref,b_70 +R 5000,6000,ref_ref,b_60 +R 5000,4000,ref_ref,a_40 +R 5000,3000,ref_ref,a_30 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 5000,2000,ref_ref,a_20 +R 2000,2000,ref_ref,z_20 +R 3000,2000,ref_ref,z_20 +R 5000,7000,ref_ref,b_70 +R 6000,8000,ref_ref,b_80 +R 4000,4000,ref_ref,a_40 +R 2000,3000,ref_ref,z_30 +S 1100,9300,1900,9300,600,*,RIGHT,NTIE +S 1200,700,1900,700,600,*,RIGHT,PTIE +S 6400,1900,6400,5900,400,bn,DOWN,ALU1 +S 4700,6500,4700,9100,1600,*,UP,PDIF +S 5800,2600,5800,5500,200,*,UP,POLY +S 6000,7000,6000,8000,400,b,UP,CALU1 +S 5000,6000,5000,7000,400,b,DOWN,CALU1 +S 5000,5900,5000,7000,400,*,DOWN,ALU1 +S 6200,5700,6200,7300,400,*,UP,PDIF +S 5800,5500,5800,7500,200,4,DOWN,PTRANS +S 0,5000,7000,5000,10000,xor2_x05,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 5000,2000,5000,4000,400,a,UP,CALU1 +S 1000,7000,2100,7000,400,*,LEFT,ALU1 +S 1200,6300,1200,8300,200,1,DOWN,PTRANS +S 1800,6500,1800,8100,800,*,UP,PDIF +S 2400,6300,2400,8300,200,2,DOWN,PTRANS +S 1200,8300,1200,8700,200,*,UP,POLY +S 2400,8300,2400,8700,200,*,UP,POLY +S 3600,6300,3600,8300,200,3,DOWN,PTRANS +S 3000,6500,3000,8100,600,*,UP,PDIF +S 1000,7100,2100,7100,400,*,LEFT,ALU1 +S 800,6500,800,7800,400,*,UP,PDIF +S 3600,8300,3600,8700,200,*,UP,POLY +S 3400,400,5800,400,200,*,RIGHT,POLY +S 4000,1900,4000,3000,400,an,DOWN,ALU1 +S 5000,1900,5000,4000,400,*,DOWN,ALU1 +S 3900,4000,5000,4000,400,*,LEFT,ALU1 +S 3900,4100,5000,4100,400,*,LEFT,ALU1 +S 6200,1900,6200,2400,400,*,UP,NDIF +S 5800,1700,5800,2600,200,9,UP,NTRANS +S 4000,1900,4000,2400,1000,*,DOWN,NDIF +S 4600,1700,4600,2600,200,8,UP,NTRANS +S 3400,1700,3400,2600,200,7,UP,NTRANS +S 2800,1900,2800,2400,1000,*,DOWN,NDIF +S 2200,1700,2200,2600,200,6,UP,NTRANS +S 1800,1900,1800,2400,600,n1,UP,NDIF +S 1400,1700,1400,2600,200,5,UP,NTRANS +S 3400,2600,3400,3000,200,*,UP,POLY +S 2200,1300,2200,1700,200,*,UP,POLY +S 1400,1300,1400,1700,200,*,UP,POLY +S 3400,400,3400,1700,200,*,DOWN,POLY +S 4600,1300,4600,1700,200,*,UP,POLY +S 5800,600,5800,1700,200,*,UP,POLY +S 5200,900,5200,2400,600,*,UP,NDIF +S 2200,3000,2600,3000,200,*,LEFT,POLY +S 3000,3000,4000,3000,400,*,RIGHT,ALU1 +S 1000,3000,2000,3000,600,*,RIGHT,ALU1 +S 2000,2000,2000,3000,400,*,DOWN,ALU1 +S 2000,1900,3100,1900,400,*,RIGHT,ALU1 +S 2000,2000,3100,2000,400,*,RIGHT,ALU1 +S 1000,3000,1000,7000,400,*,DOWN,ALU1 +S 1000,3000,1000,7000,400,z,DOWN,CALU1 +S 2000,2000,2000,3000,400,z,DOWN,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 700,1900,700,2400,600,*,UP,NDIF +S 800,700,800,2100,400,*,DOWN,ALU1 +S 3600,5900,3600,6300,200,*,UP,POLY +S 3000,3000,3000,7100,400,*,UP,ALU1 +S 4900,6500,4900,8100,1200,*,DOWN,PDIF +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 5200,7900,5200,9300,400,*,UP,ALU1 +S 6100,6900,6100,8100,600,*,UP,ALU1 +S 5000,7000,6200,7000,600,*,RIGHT,ALU1 +S 5800,7500,5800,8300,200,*,UP,POLY +S 2600,3000,2600,5300,200,*,DOWN,POLY +S 2400,5300,3800,5300,200,*,LEFT,POLY +S 2400,5200,2400,6300,200,*,DOWN,POLY +S 1800,4400,3000,4400,600,*,RIGHT,ALU1 +S 1400,2600,1400,4600,200,*,UP,POLY +S 1200,4500,1200,6300,200,*,DOWN,POLY +S 4600,2600,4600,5900,200,*,UP,POLY +S 3600,5900,4600,5900,200,*,LEFT,POLY +S 3800,5000,3800,8000,400,*,DOWN,ALU1 +S 3800,5000,6400,5000,400,*,LEFT,ALU1 +S 500,8000,3800,8000,400,*,RIGHT,ALU1 +S 5300,5700,5300,7300,600,*,UP,PDIF +V 2000,9300,CONT_BODY_N,* +V 1000,9300,CONT_BODY_N,* +V 2000,700,CONT_BODY_P,* +V 1100,700,CONT_BODY_P,* +V 6400,5800,CONT_DIF_P,bn +V 4800,4000,CONT_POLY,* +V 1800,7000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,bn +V 3000,7000,CONT_DIF_P,an +V 5200,1000,CONT_DIF_N,* +V 2800,2000,CONT_DIF_N,* +V 4000,2000,CONT_DIF_N,an +V 4200,9000,CONT_DIF_P,* +V 6400,2000,CONT_DIF_N,bn +V 800,2000,CONT_DIF_N,* +V 5200,8000,CONT_DIF_P,* +V 5200,9000,CONT_DIF_P,* +V 6100,8100,CONT_POLY,* +V 1800,4400,CONT_POLY,an +V 3800,5100,CONT_POLY,bn +EOF diff --git a/pdks/symbolic/msxlib/cells/xor2_x05.vbe b/pdks/symbolic/msxlib/cells/xor2_x05.vbe new file mode 100644 index 000000000..9bb09a8d5 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xor2_x05.vbe @@ -0,0 +1,36 @@ +ENTITY xor2_x05 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 3520; + CONSTANT rdown_a_z : NATURAL := 3620; + CONSTANT rup_b_z : NATURAL := 4790; + CONSTANT rup_a_z : NATURAL := 4890; + CONSTANT tplh_a_z : NATURAL := 69; + CONSTANT tphl_b_z : NATURAL := 35; + CONSTANT tplh_b_z : NATURAL := 89; + CONSTANT tphh_b_z : NATURAL := 64; + CONSTANT tphl_a_z : NATURAL := 65; + CONSTANT tpll_a_z : NATURAL := 93; + CONSTANT tpll_b_z : NATURAL := 94; + CONSTANT tphh_a_z : NATURAL := 91; + CONSTANT transistors : NATURAL := 9 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xor2_x05; + +ARCHITECTURE behaviour_data_flow OF xor2_x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xor2_x05" + SEVERITY WARNING; + z <= (b xor a) after 1000 ps; +END; diff --git a/pdks/symbolic/msxlib/cells/xor2_x1.ap b/pdks/symbolic/msxlib/cells/xor2_x1.ap new file mode 100644 index 000000000..05b2324d4 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xor2_x1.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H xor2_x1,P, 9/ 8/2014,100 +A 0,0,7000,10000 +R 5000,2000,ref_ref,a_20 +R 5000,6000,ref_ref,b_60 +R 5000,4000,ref_ref,a_40 +R 5000,3000,ref_ref,a_30 +R 1000,6000,ref_ref,z_60 +R 1000,5000,ref_ref,z_50 +R 1000,4000,ref_ref,z_40 +R 1000,3000,ref_ref,z_30 +R 1000,7000,ref_ref,z_70 +R 2000,7000,ref_ref,z_70 +R 1000,2000,ref_ref,z_20 +R 2000,2000,ref_ref,z_20 +R 5000,7000,ref_ref,b_70 +R 4000,4000,ref_ref,a_40 +R 3000,2000,ref_ref,z_20 +R 6000,8000,ref_ref,b_80 +R 6000,7000,ref_ref,b_70 +S 6400,2000,6400,5000,400,*,UP,ALU1 +S 2000,7000,2000,7000,400,z,LEFT,CALU1 +S 3000,2000,3000,2000,400,z,LEFT,CALU1 +S 2000,2000,2000,2000,400,z,LEFT,CALU1 +S 4000,4000,4000,4000,400,a,LEFT,CALU1 +S 2000,6000,3000,6000,400,*,LEFT,ALU1 +S 0,5000,7000,5000,10000,xor2_x1,LEFT,TALU8 +S 0,2200,7000,2200,5200,*,LEFT,PWELL +S 0,7600,7000,7600,5600,*,LEFT,NWELL +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 5000,2000,5000,4000,400,a,UP,CALU1 +S 1000,7000,2100,7000,400,*,RIGHT,ALU1 +S 1000,7100,2100,7100,400,*,RIGHT,ALU1 +S 1000,2000,1000,7000,400,*,DOWN,ALU1 +S 1000,2000,1000,7000,400,z,DOWN,CALU1 +S 4000,1900,4000,3000,400,an,DOWN,ALU1 +S 2000,3000,2000,6000,400,*,UP,ALU1 +S 2000,3000,4000,3000,400,*,RIGHT,ALU1 +S 3400,400,5600,400,200,*,RIGHT,POLY +S 1200,9400,1200,9700,200,*,DOWN,POLY +S 2400,9400,2400,9700,200,*,DOWN,POLY +S 3600,9400,3600,9700,200,*,DOWN,POLY +S 3000,6000,3000,7100,400,*,DOWN,ALU1 +S 3900,4000,5000,4000,400,*,LEFT,ALU1 +S 3900,4100,5000,4100,400,*,LEFT,ALU1 +S 1000,2000,3000,2000,600,*,RIGHT,ALU1 +S 3000,5000,6400,5000,400,*,RIGHT,ALU1 +S 5200,9400,5200,9700,200,*,DOWN,POLY +S 5000,6000,5000,7000,400,b,UP,CALU1 +S 5000,5900,5000,7000,400,*,DOWN,ALU1 +S 6000,7000,6000,8000,400,b,UP,CALU1 +S 5000,7000,6500,7000,600,*,RIGHT,ALU1 +S 5000,1900,5000,4000,400,*,DOWN,ALU1 +S 4600,7900,4600,9300,400,*,UP,ALU1 +S 3800,5000,3800,8000,400,*,UP,ALU1 +S 500,8000,3800,8000,400,*,RIGHT,ALU1 +S 6000,7000,6000,8100,400,*,UP,ALU1 +S 6200,1700,6200,2900,400,*,UP,NDIF +S 1400,1200,1400,1500,200,*,UP,POLY +S 2200,1200,2200,1500,200,*,UP,POLY +S 3400,400,3400,1500,200,*,DOWN,POLY +S 4600,1100,4600,1500,200,*,UP,POLY +S 5800,400,5800,1500,200,*,UP,POLY +S 700,900,700,3000,600,*,UP,NDIF +S 800,900,800,3000,600,*,UP,NDIF +S 1800,1700,1800,3000,600,n1,UP,NDIF +S 1400,1500,1400,3200,200,5,UP,NTRANS +S 2200,1500,2200,3200,200,6,UP,NTRANS +S 2200,3600,2800,3600,200,*,LEFT,POLY +S 3400,3200,3400,3600,200,*,UP,POLY +S 1500,4400,2000,4400,600,*,LEFT,POLY +S 4000,1700,4000,3000,1000,*,DOWN,NDIF +S 4600,1500,4600,3200,200,8,UP,NTRANS +S 3400,1500,3400,3200,200,7,UP,NTRANS +S 2800,1700,2800,3000,1000,*,DOWN,NDIF +S 5200,900,5200,3000,600,*,UP,NDIF +S 5800,1500,5800,3200,200,9,UP,NTRANS +S 2400,5200,2800,5200,200,*,RIGHT,POLY +S 1400,3200,1400,4600,200,*,UP,POLY +S 1200,4500,1200,5700,200,*,UP,POLY +S 2400,5600,2400,9400,200,2,DOWN,PTRANS +S 3600,5600,3600,9400,200,3,DOWN,PTRANS +S 3000,5800,3000,9200,600,*,UP,PDIF +S 800,5800,800,9200,400,*,UP,PDIF +S 1200,5600,1200,9400,200,1,DOWN,PTRANS +S 1800,5800,1800,9200,1000,*,UP,PDIF +S 4400,5800,4400,9200,800,*,DOWN,PDIF +S 5200,5600,5200,9400,200,4,DOWN,PTRANS +S 5600,5800,5600,9200,400,*,UP,PDIF +S 5800,5000,5800,6000,400,*,DOWN,ALU1 +S 5800,3200,5800,5200,200,*,UP,POLY +S 2800,3600,2800,5200,200,*,DOWN,POLY +S 5200,5200,6600,5200,200,*,LEFT,POLY +S 6600,5200,6600,6800,200,*,DOWN,POLY +S 6400,2200,6400,2800,600,*,DOWN,NDIF +S 3000,4300,3000,5000,400,*,DOWN,ALU1 +S 4600,3200,4600,4000,200,*,DOWN,POLY +S 4200,4000,4200,5200,200,*,UP,POLY +S 3600,5200,4200,5200,200,*,LEFT,POLY +V 2000,700,CONT_BODY_P,* +V 3000,6200,CONT_DIF_P,an +V 600,8000,CONT_DIF_P,bn +V 1800,7000,CONT_DIF_P,* +V 5200,1000,CONT_DIF_N,* +V 4000,2000,CONT_DIF_N,an +V 2800,2000,CONT_DIF_N,* +V 3000,7000,CONT_DIF_P,an +V 6400,7000,CONT_POLY,* +V 4600,9000,CONT_DIF_P,* +V 4600,8000,CONT_DIF_P,* +V 800,1000,CONT_DIF_N,* +V 4000,2800,CONT_DIF_N,an +V 3000,4400,CONT_POLY,bn +V 2000,4400,CONT_POLY,an +V 6400,2900,CONT_DIF_N,bn +V 5800,5900,CONT_DIF_P,bn +V 6400,2100,CONT_DIF_N,bn +V 4400,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/msxlib/cells/xor2_x1.vbe b/pdks/symbolic/msxlib/cells/xor2_x1.vbe new file mode 100644 index 000000000..82248ab32 --- /dev/null +++ b/pdks/symbolic/msxlib/cells/xor2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY xor2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_b : NATURAL := 9; + CONSTANT cin_a : NATURAL := 7; + CONSTANT rdown_b_z : NATURAL := 1860; + CONSTANT rdown_a_z : NATURAL := 1910; + CONSTANT rup_b_z : NATURAL := 2530; + CONSTANT rup_a_z : NATURAL := 2570; + CONSTANT tplh_a_z : NATURAL := 65; + CONSTANT tphl_b_z : NATURAL := 33; + CONSTANT tplh_b_z : NATURAL := 82; + CONSTANT tphh_b_z : NATURAL := 59; + CONSTANT tphl_a_z : NATURAL := 62; + CONSTANT tpll_a_z : NATURAL := 88; + CONSTANT tpll_b_z : NATURAL := 87; + CONSTANT tphh_a_z : NATURAL := 86; + CONSTANT transistors : NATURAL := 9 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xor2_x1; + +ARCHITECTURE behaviour_data_flow OF xor2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xor2_x1" + SEVERITY WARNING; + z <= (b xor a) after 1000 ps; +END; diff --git a/pdks/symbolic/niolib/cells/CATAL b/pdks/symbolic/niolib/cells/CATAL new file mode 100644 index 000000000..eca26f07c --- /dev/null +++ b/pdks/symbolic/niolib/cells/CATAL @@ -0,0 +1,5 @@ +gpio C +iovdd C +iovss C +vdd C +vss C diff --git a/pdks/symbolic/niolib/cells/gpio.ap b/pdks/symbolic/niolib/cells/gpio.ap new file mode 100644 index 000000000..07703e6ef --- /dev/null +++ b/pdks/symbolic/niolib/cells/gpio.ap @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H gpio,P,21/10/2020,100 +A 0,0,50000,119000 +S 25000,113900,25000,119000,200,i,UP,CALU2 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU5 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU3 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU3 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU3 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU3 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU4 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU4 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU4 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU4 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU5 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU5 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU5 +S 0,87500,50000,87500,7000,iovss,RIGHT,CALU6 +S 0,78200,50000,78200,6800,iovss,RIGHT,CALU6 +S 0,69000,50000,69000,6800,iovss,RIGHT,CALU6 +S 0,59800,50000,59800,6800,iovss,RIGHT,CALU6 +S 0,96900,50000,96900,3800,iovss,RIGHT,CALU6 +S 0,4000,50000,4000,4800,iovss,RIGHT,CALU6 +S 0,11500,50000,11500,5000,iovss,RIGHT,CALU6 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU3 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU3 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU3 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU4 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU4 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU4 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU5 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU5 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU5 +S 1200,113900,1200,119000,200,o,UP,CALU2 +S 2800,113900,2800,119000,200,oe,UP,CALU2 +S 3000,35800,47000,35800,34400,pad,RIGHT,CALU6 +S 0,104300,50000,104300,7800,vdd,RIGHT,CALU4 +S 0,104800,50000,104800,8800,vdd,RIGHT,CALU5 +S 0,114400,50000,114400,8800,vdd,RIGHT,CALU3 +S 0,114900,50000,114900,7800,vss,RIGHT,CALU4 +S 0,114400,50000,114400,8800,vss,RIGHT,CALU5 +S 0,104800,50000,104800,8800,vss,RIGHT,CALU3 +EOF diff --git a/pdks/symbolic/niolib/cells/gpio.vbe b/pdks/symbolic/niolib/cells/gpio.vbe new file mode 100644 index 000000000..1e59cdf28 --- /dev/null +++ b/pdks/symbolic/niolib/cells/gpio.vbe @@ -0,0 +1,38 @@ +ENTITY gpio IS + PORT ( + i : in BIT; + oe : in BIT; + o : out BIT; + pad : inout MUX_BIT BUS; + iovdd : in BIT; + vdd : in BIT; + iovss : in BIT; + vss : in BIT + ); +END gpio; + +ARCHITECTURE behaviour_data_flow OF gpio IS + SIGNAL oe1 : BIT; + SIGNAL oe2 : BIT; + SIGNAL oe3 : BIT; + SIGNAL oe4 : BIT; + SIGNAL oe5 : BIT; + SIGNAL oe6 : BIT; + +BEGIN + oe6 <= oe5; + oe5 <= oe4; + oe4 <= oe3; + oe3 <= oe2; + oe2 <= oe1; + oe1 <= oe; + label0 : BLOCK (oe6 = '1') + BEGIN + pad <= GUARDED i; + END BLOCK label0; + o <= pad; + + ASSERT ((((vdd and iovdd) and not (iovss)) and not (vss)) = '1') + REPORT "power supply is missing on gpio" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/niolib/cells/iovdd.ap b/pdks/symbolic/niolib/cells/iovdd.ap new file mode 100644 index 000000000..43690d122 --- /dev/null +++ b/pdks/symbolic/niolib/cells/iovdd.ap @@ -0,0 +1,39 @@ +V ALLIANCE : 6 +H iovdd,P,21/10/2020,100 +A 0,0,50000,119000 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU5 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU3 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU3 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU3 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU3 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU4 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU4 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU4 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU4 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU5 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU5 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU5 +S 0,87500,50000,87500,7000,iovss,RIGHT,CALU6 +S 0,78200,50000,78200,6800,iovss,RIGHT,CALU6 +S 0,69000,50000,69000,6800,iovss,RIGHT,CALU6 +S 0,59800,50000,59800,6800,iovss,RIGHT,CALU6 +S 0,96900,50000,96900,3800,iovss,RIGHT,CALU6 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU3 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU3 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU3 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU4 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU4 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU4 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU5 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU5 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU5 +S 0,4000,50000,4000,4800,iovss,RIGHT,CALU6 +S 0,11500,50000,11500,5000,iovss,RIGHT,CALU6 +S 3000,35800,47000,35800,34400,iovdd,RIGHT,CALU6 +S 0,104300,50000,104300,7800,vdd,RIGHT,CALU4 +S 0,104800,50000,104800,8800,vdd,RIGHT,CALU5 +S 0,114400,50000,114400,8800,vdd,RIGHT,CALU3 +S 0,114900,50000,114900,7800,vss,RIGHT,CALU4 +S 0,114400,50000,114400,8800,vss,RIGHT,CALU5 +S 0,104800,50000,104800,8800,vss,RIGHT,CALU3 +EOF diff --git a/pdks/symbolic/niolib/cells/iovdd.vbe b/pdks/symbolic/niolib/cells/iovdd.vbe new file mode 100644 index 000000000..fcf46d590 --- /dev/null +++ b/pdks/symbolic/niolib/cells/iovdd.vbe @@ -0,0 +1,17 @@ +ENTITY iovdd IS + PORT ( + iovdd : in BIT; + vdd : in BIT; + iovss : in BIT; + vss : in BIT + ); +END iovdd; + +ARCHITECTURE behaviour_data_flow OF iovdd IS + +BEGIN + + ASSERT ((((vdd and iovdd) and not (iovss)) and not (vss)) = '1') + REPORT "power supply is missing on iovdd" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/niolib/cells/iovss.ap b/pdks/symbolic/niolib/cells/iovss.ap new file mode 100644 index 000000000..e5e5ad667 --- /dev/null +++ b/pdks/symbolic/niolib/cells/iovss.ap @@ -0,0 +1,39 @@ +V ALLIANCE : 6 +H iovss,P,21/10/2020,100 +A 0,0,50000,119000 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU5 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU3 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU3 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU3 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU3 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU4 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU4 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU4 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU4 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU5 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU5 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU5 +S 0,87500,50000,87500,7000,iovss,RIGHT,CALU6 +S 0,78200,50000,78200,6800,iovss,RIGHT,CALU6 +S 0,69000,50000,69000,6800,iovss,RIGHT,CALU6 +S 0,59800,50000,59800,6800,iovss,RIGHT,CALU6 +S 0,96900,50000,96900,3800,iovss,RIGHT,CALU6 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU5 +S 0,4000,50000,4000,4800,iovss,RIGHT,CALU6 +S 0,11500,50000,11500,5000,iovss,RIGHT,CALU6 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU3 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU3 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU3 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU4 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU4 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU4 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU5 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU5 +S 3000,35800,47000,35800,34400,iovss,RIGHT,CALU6 +S 0,104300,50000,104300,7800,vdd,RIGHT,CALU4 +S 0,104800,50000,104800,8800,vdd,RIGHT,CALU5 +S 0,114400,50000,114400,8800,vdd,RIGHT,CALU3 +S 0,114900,50000,114900,7800,vss,RIGHT,CALU4 +S 0,114400,50000,114400,8800,vss,RIGHT,CALU5 +S 0,104800,50000,104800,8800,vss,RIGHT,CALU3 +EOF diff --git a/pdks/symbolic/niolib/cells/iovss.vbe b/pdks/symbolic/niolib/cells/iovss.vbe new file mode 100644 index 000000000..445d362ee --- /dev/null +++ b/pdks/symbolic/niolib/cells/iovss.vbe @@ -0,0 +1,17 @@ +ENTITY iovss IS + PORT ( + iovss : in BIT; + vdd : in BIT; + iovdd : in BIT; + vss : in BIT + ); +END iovss; + +ARCHITECTURE behaviour_data_flow OF iovss IS + +BEGIN + + ASSERT ((((vdd and iovss) and not (iovss)) and not (vss)) = '1') + REPORT "power supply is missing on iovss" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/niolib/cells/vdd.ap b/pdks/symbolic/niolib/cells/vdd.ap new file mode 100644 index 000000000..c3b6e3633 --- /dev/null +++ b/pdks/symbolic/niolib/cells/vdd.ap @@ -0,0 +1,40 @@ +V ALLIANCE : 6 +H vdd,P,21/10/2020,100 +A 0,0,50000,119000 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU5 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU3 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU3 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU3 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU3 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU4 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU4 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU4 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU4 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU5 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU5 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU5 +S 0,87500,50000,87500,7000,iovss,RIGHT,CALU6 +S 0,78200,50000,78200,6800,iovss,RIGHT,CALU6 +S 0,69000,50000,69000,6800,iovss,RIGHT,CALU6 +S 0,59800,50000,59800,6800,iovss,RIGHT,CALU6 +S 0,96900,50000,96900,3800,iovss,RIGHT,CALU6 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU3 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU3 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU3 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU4 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU4 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU4 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU5 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU5 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU5 +S 0,4000,50000,4000,4800,iovss,RIGHT,CALU6 +S 0,11500,50000,11500,5000,iovss,RIGHT,CALU6 +S 3000,35800,47000,35800,34400,vdd,RIGHT,CALU6 +S 0,104300,50000,104300,7800,vdd,RIGHT,CALU4 +S 0,104800,50000,104800,8800,vdd,RIGHT,CALU5 +S 0,114400,50000,114400,8800,vdd,RIGHT,CALU3 +S 0,114900,50000,114900,7800,vss,RIGHT,CALU4 +S 0,114400,50000,114400,8800,vss,RIGHT,CALU5 +S 0,104800,50000,104800,8800,vss,RIGHT,CALU3 +S 25000,112000,25000,119000,40000,vdd,UP,CALU3 +EOF diff --git a/pdks/symbolic/niolib/cells/vdd.vbe b/pdks/symbolic/niolib/cells/vdd.vbe new file mode 100644 index 000000000..004de64af --- /dev/null +++ b/pdks/symbolic/niolib/cells/vdd.vbe @@ -0,0 +1,17 @@ +ENTITY vdd IS + PORT ( + iovss : in BIT; + vdd : in BIT; + iovdd : in BIT; + vss : in BIT + ); +END vdd; + +ARCHITECTURE behaviour_data_flow OF vdd IS + +BEGIN + + ASSERT ((((vdd and iovss) and not (iovss)) and not (vss)) = '1') + REPORT "power supply is missing on iovss" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/niolib/cells/vss.ap b/pdks/symbolic/niolib/cells/vss.ap new file mode 100644 index 000000000..564fb1337 --- /dev/null +++ b/pdks/symbolic/niolib/cells/vss.ap @@ -0,0 +1,40 @@ +V ALLIANCE : 6 +H vss,P,21/10/2020,100 +A 0,0,50000,119000 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU5 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU3 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU3 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU3 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU3 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU4 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU4 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU4 +S 0,87500,50000,87500,8200,iovdd,RIGHT,CALU4 +S 0,59800,50000,59800,8400,iovdd,RIGHT,CALU5 +S 0,69000,50000,69000,8400,iovdd,RIGHT,CALU5 +S 0,78200,50000,78200,8400,iovdd,RIGHT,CALU5 +S 0,87500,50000,87500,7000,iovss,RIGHT,CALU6 +S 0,78200,50000,78200,6800,iovss,RIGHT,CALU6 +S 0,69000,50000,69000,6800,iovss,RIGHT,CALU6 +S 0,59800,50000,59800,6800,iovss,RIGHT,CALU6 +S 0,96900,50000,96900,3800,iovss,RIGHT,CALU6 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU3 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU3 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU3 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU4 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU4 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU4 +S 0,4000,50000,4000,6400,iovss,RIGHT,CALU5 +S 0,11400,50000,11400,6400,iovss,RIGHT,CALU5 +S 0,96900,50000,96900,5400,iovss,RIGHT,CALU5 +S 0,4000,50000,4000,4800,iovss,RIGHT,CALU6 +S 0,11500,50000,11500,5000,iovss,RIGHT,CALU6 +S 3000,35800,47000,35800,34400,vss,RIGHT,CALU6 +S 0,104300,50000,104300,7800,vdd,RIGHT,CALU4 +S 0,104800,50000,104800,8800,vdd,RIGHT,CALU5 +S 0,114400,50000,114400,8800,vdd,RIGHT,CALU3 +S 0,114900,50000,114900,7800,vss,RIGHT,CALU4 +S 0,114400,50000,114400,8800,vss,RIGHT,CALU5 +S 0,104800,50000,104800,8800,vss,RIGHT,CALU3 +S 25000,112000,25000,119000,40000,vss,UP,CALU4 +EOF diff --git a/pdks/symbolic/niolib/cells/vss.vbe b/pdks/symbolic/niolib/cells/vss.vbe new file mode 100644 index 000000000..ad958c671 --- /dev/null +++ b/pdks/symbolic/niolib/cells/vss.vbe @@ -0,0 +1,17 @@ +ENTITY vss IS + PORT ( + iovss : in BIT; + vdd : in BIT; + iovdd : in BIT; + vss : in BIT + ); +END vss; + +ARCHITECTURE behaviour_data_flow OF vss IS + +BEGIN + + ASSERT ((((vdd and iovss) and not (iovss)) and not (vss)) = '1') + REPORT "power supply is missing on iovss" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/nramlib/cells/CATAL b/pdks/symbolic/nramlib/cells/CATAL new file mode 100644 index 000000000..31ad32443 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/CATAL @@ -0,0 +1,20 @@ +ram_mem_buf0 C +ram_mem_buf1 C +ram_mem_data C +ram_mem_dec2 C +ram_mem_dec3 C +ram_mem_dec4 C +ram_mem_dec5 C +ram_mem_deci C +ram_prech_buf0 C +ram_prech_buf1 C +ram_prech_data C +ram_prech_dec0 C +ram_sense_buf0 C +ram_sense_buf1 C +ram_sense_data C +ram_sense_decad12 C +ram_sense_decad2 C +ram_sense_decad3 C +ram_sense_decad4 C +ram_sense_decad5 C diff --git a/pdks/symbolic/nramlib/cells/ram_mem_buf0.ap b/pdks/symbolic/nramlib/cells/ram_mem_buf0.ap new file mode 100644 index 000000000..9cc520373 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_buf0.ap @@ -0,0 +1,77 @@ +V ALLIANCE : 6 +H ram_mem_buf0,P,23/4/2016,100 +A 0,0,5000,10000 +S 5000,5680,5000,9320,600,6nonymous_,UP,NTIE +S 5000,6100,5000,8900,300,5nonymous_,UP,ALU1 +S -1000,7800,6200,7800,6000,4nonymous_,RIGHT,NWELL +S 2400,7100,2400,8900,300,3nonymous_,UP,ALU1 +S 2200,5100,2200,5900,300,2nonymous_,UP,ALU1 +S 5000,1100,5000,2900,300,1nonymous_,UP,ALU1 +S 5000,680,5000,3320,600,0nonymous_,UP,PTIE +S 5000,-150,5000,10150,2400,vss,UP,CALU3 +S 100,600,4900,600,1200,vss,RIGHT,CALU1 +S 100,9400,4900,9400,1200,vdd,RIGHT,CALU1 +S 0,-150,0,10150,2400,vdd,UP,CALU3 +S 2000,3850,2000,4150,400,nq,UP,CALU3 +S 1800,5500,1800,9500,200,16onymous_,UP,PTRANS +S 600,5500,600,9500,200,15onymous_,UP,PTRANS +S 3000,500,3000,2500,200,14onymous_,UP,NTRANS +S 600,500,600,2500,200,13onymous_,UP,NTRANS +S 1200,700,1200,2300,600,12onymous_,UP,NDIF +S 3000,2800,3000,5200,200,11onymous_,UP,POLY +S 0,5700,0,9300,600,10onymous_,UP,PDIF +S 0,700,0,2300,600,9nonymous_,UP,NDIF +S 0,6100,0,8900,300,8nonymous_,UP,ALU1 +S 0,1100,0,1900,300,7nonymous_,UP,ALU1 +S 3000,4850,3000,5150,400,i,UP,CALU3 +S 2400,5700,2400,9300,600,17onymous_,UP,PDIF +S 2250,5000,2950,5000,300,34onymous_,RIGHT,TALU2 +S 1250,4000,3550,4000,300,33onymous_,RIGHT,TALU2 +S 2050,5000,3150,5000,600,32onymous_,RIGHT,ALU2 +S 1050,4000,3750,4000,600,31onymous_,RIGHT,ALU2 +S 1800,500,1800,2500,200,30onymous_,UP,NTRANS +S 600,5000,3000,5000,600,29onymous_,RIGHT,POLY +S 1300,4000,3500,4000,300,28onymous_,RIGHT,ALU1 +S 3600,2100,3600,7900,300,27onymous_,UP,ALU1 +S 1200,2100,1200,7900,300,26onymous_,UP,ALU1 +S 600,2800,600,5200,200,25onymous_,UP,POLY +S 1800,2800,1800,5200,200,24onymous_,UP,POLY +S 3600,5700,3600,9300,600,23onymous_,UP,PDIF +S 3600,700,3600,2300,600,22onymous_,UP,NDIF +S 2400,1100,2400,1900,300,21onymous_,UP,ALU1 +S 2400,700,2400,2300,600,20onymous_,UP,NDIF +S 1200,5700,1200,9300,600,19onymous_,UP,PDIF +S 3000,5500,3000,9500,200,18onymous_,UP,PTRANS +V 5000,1000,CONT_BODY_P,36onymous_ +V 5000,3000,CONT_BODY_P,35onymous_ +V 5000,2000,CONT_BODY_P,37onymous_ +V 5000,9000,CONT_BODY_N,38onymous_ +V 5000,8000,CONT_BODY_N,39onymous_ +V 5000,7000,CONT_BODY_N,40onymous_ +V 5000,6000,CONT_BODY_N,41onymous_ +V 0,2000,CONT_DIF_N,42onymous_ +V 0,1000,CONT_DIF_N,43onymous_ +V 0,6000,CONT_DIF_P,44onymous_ +V 0,8000,CONT_DIF_P,45onymous_ +V 0,9000,CONT_DIF_P,46onymous_ +V 0,7000,CONT_DIF_P,47onymous_ +V 2200,5000,CONT_POLY,66onymous_ +V 2200,5000,CONT_VIA,65onymous_ +V 3600,2000,CONT_DIF_N,64onymous_ +V 2400,2000,CONT_DIF_N,63onymous_ +V 1200,2000,CONT_DIF_N,62onymous_ +V 2400,8000,CONT_DIF_P,61onymous_ +V 2400,7000,CONT_DIF_P,60onymous_ +V 3600,7000,CONT_DIF_P,59onymous_ +V 3600,8000,CONT_DIF_P,58onymous_ +V 1200,8000,CONT_DIF_P,57onymous_ +V 1200,7000,CONT_DIF_P,56onymous_ +V 1200,4000,CONT_VIA,55onymous_ +V 3600,4000,CONT_VIA,54onymous_ +V 2000,4000,CONT_VIA2,53onymous_ +V 3000,5000,CONT_VIA2,52onymous_ +V 1200,6000,CONT_DIF_P,51onymous_ +V 3600,6000,CONT_DIF_P,50onymous_ +V 2400,9000,CONT_DIF_P,49onymous_ +V 2400,1000,CONT_DIF_N,48onymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_mem_buf0.vbe b/pdks/symbolic/nramlib/cells/ram_mem_buf0.vbe new file mode 100644 index 000000000..0ff6e69cc --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_buf0.vbe @@ -0,0 +1,17 @@ +ENTITY ram_mem_buf0 IS +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_buf0; + +ARCHITECTURE VBE OF ram_mem_buf0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_buf0" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_mem_buf1.ap b/pdks/symbolic/nramlib/cells/ram_mem_buf1.ap new file mode 100644 index 000000000..aaeee0587 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_buf1.ap @@ -0,0 +1,76 @@ +V ALLIANCE : 6 +H ram_mem_buf1,P,23/4/2016,100 +A 0,0,5000,10000 +S 1400,500,1400,3500,200,17onymous_,UP,NTRANS +S 2600,500,2600,3500,200,16onymous_,UP,NTRANS +S 2600,3800,2600,5200,200,15onymous_,UP,POLY +S 2100,3000,3300,3000,300,4nonymous_,RIGHT,ALU1 +S 1100,6000,2900,6000,300,3nonymous_,RIGHT,ALU1 +S 2050,7000,2950,7000,300,2nonymous_,RIGHT,TALU2 +S 1850,7000,3150,7000,600,1nonymous_,RIGHT,ALU2 +S 2000,7100,2000,7900,300,0nonymous_,UP,ALU1 +S 100,600,4900,600,1200,vss,RIGHT,CALU1 +S -150,0,5150,0,2600,vss,RIGHT,CALU2 +S 5000,-150,5000,10150,2400,vss,UP,CALU3 +S 1400,3800,1400,5200,200,14onymous_,UP,POLY +S 800,700,800,3300,600,13onymous_,UP,NDIF +S 2000,700,2000,3300,600,12onymous_,UP,NDIF +S 3200,700,3200,3300,600,11onymous_,UP,NDIF +S 800,1100,800,2900,300,10onymous_,UP,ALU1 +S 800,7100,800,8900,300,9nonymous_,UP,ALU1 +S 3200,8100,3200,8900,300,8nonymous_,UP,ALU1 +S 4400,2100,4400,7900,300,7nonymous_,UP,ALU1 +S 800,5000,1400,5000,600,6nonymous_,RIGHT,POLY +S 3200,5000,3800,5000,600,5nonymous_,RIGHT,POLY +S 100,9400,4900,9400,1200,vdd,RIGHT,CALU1 +S -150,10000,5150,10000,2600,vdd,RIGHT,CALU2 +S 0,-150,0,10150,2400,vdd,UP,CALU3 +S 2050,3000,2950,3000,300,34onymous_,RIGHT,TALU2 +S 1850,3000,3150,3000,600,33onymous_,RIGHT,ALU2 +S 2100,7000,4300,7000,300,32onymous_,RIGHT,ALU1 +S -600,7800,5600,7800,6000,31onymous_,RIGHT,NWELL +S 2400,4100,2400,4900,300,30onymous_,UP,ALU1 +S 1000,5100,1000,5900,300,29onymous_,UP,ALU1 +S 3800,5500,3800,9500,200,28onymous_,UP,PTRANS +S 1400,5500,1400,9500,200,27onymous_,UP,PTRANS +S 3200,5700,3200,9300,600,26onymous_,UP,PDIF +S 800,5700,800,9300,600,25onymous_,UP,PDIF +S 4400,5700,4400,9300,600,24onymous_,UP,PDIF +S 2000,5700,2000,9300,600,23onymous_,UP,PDIF +S 2600,5500,2600,9500,200,22onymous_,UP,PTRANS +S 4400,700,4400,3300,600,21onymous_,UP,NDIF +S 3800,500,3800,3500,200,20onymous_,UP,NTRANS +S 3400,3100,3400,4900,300,19onymous_,UP,ALU1 +S 3800,3800,3800,5200,200,18onymous_,UP,POLY +S 3000,6850,3000,7150,400,nseli,UP,CALU3 +S 1850,6000,3150,6000,600,selramx,RIGHT,CALU2 +S 1850,5000,3150,5000,600,nck,RIGHT,CALU2 +S 3000,2850,3000,3150,400,seli,UP,CALU3 +V 2000,8000,CONT_DIF_P,35onymous_ +V 3000,6000,CONT_VIA,36onymous_ +V 2000,3000,CONT_VIA,37onymous_ +V 4400,6000,CONT_DIF_P,38onymous_ +V 4400,8000,CONT_DIF_P,39onymous_ +V 3200,8000,CONT_DIF_P,40onymous_ +V 3000,7000,CONT_VIA2,61onymous_ +V 3000,3000,CONT_VIA2,60onymous_ +V 3000,3000,CONT_VIA,59onymous_ +V 3000,7000,CONT_VIA,58onymous_ +V 2000,7000,CONT_VIA,57onymous_ +V 2000,6000,CONT_VIA,56onymous_ +V 800,9000,CONT_DIF_P,55onymous_ +V 3200,9000,CONT_DIF_P,54onymous_ +V 4400,7000,CONT_DIF_P,53onymous_ +V 2000,7000,CONT_DIF_P,52onymous_ +V 1000,5000,CONT_POLY,51onymous_ +V 800,1000,CONT_DIF_N,50onymous_ +V 2400,5000,CONT_VIA,49onymous_ +V 4400,2000,CONT_DIF_N,48onymous_ +V 3400,5000,CONT_POLY,47onymous_ +V 2400,5000,CONT_POLY,46onymous_ +V 800,2000,CONT_DIF_N,45onymous_ +V 800,3000,CONT_DIF_N,44onymous_ +V 4400,3000,CONT_DIF_N,43onymous_ +V 800,7000,CONT_DIF_P,42onymous_ +V 800,8000,CONT_DIF_P,41onymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_mem_buf1.vbe b/pdks/symbolic/nramlib/cells/ram_mem_buf1.vbe new file mode 100644 index 000000000..19bd20e07 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_buf1.vbe @@ -0,0 +1,19 @@ +ENTITY ram_mem_buf1 IS +PORT ( + seli : in BIT; + nck : in BIT; + selramx : in BIT; + nseli : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_buf1; + +ARCHITECTURE VBE OF ram_mem_buf1 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_buf1" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_mem_data.ap b/pdks/symbolic/nramlib/cells/ram_mem_data.ap new file mode 100644 index 000000000..b753ad64f --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_data.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H ram_mem_data,P,23/4/2016,100 +A 0,0,5000,10000 +S 50,5000,4950,5000,300,4nonymous_,RIGHT,TALU2 +S 0,-150,0,10150,2400,vdd,UP,CALU3 +S -150,10000,5150,10000,600,vdd,RIGHT,CALU2 +S -150,0,5150,0,600,vss,RIGHT,CALU2 +S 100,400,4900,400,800,vss,RIGHT,CALU1 +S 5000,-150,5000,10150,2400,vss,UP,CALU3 +S 50,7000,4150,7000,300,0nonymous_,RIGHT,TALU2 +S 50,9000,1150,9000,300,1nonymous_,RIGHT,TALU2 +S 50,1000,3150,1000,300,2nonymous_,RIGHT,TALU2 +S 50,3000,4950,3000,300,3nonymous_,RIGHT,TALU2 +S 900,2200,1300,2200,200,14onymous_,RIGHT,PTRANS +S 1600,2200,1600,3800,200,15onymous_,UP,POLY +S 5000,7450,5000,8150,600,16onymous_,UP,ALU2 +S 5000,5850,5000,6550,600,17onymous_,UP,ALU2 +S 100,9400,900,9400,1600,5nonymous_,RIGHT,ALU1 +S 3100,9400,4900,9400,1600,6nonymous_,RIGHT,ALU1 +S 600,600,600,11000,2800,7nonymous_,UP,NWELL +S 900,8200,1300,8200,200,8nonymous_,RIGHT,PTRANS +S 1600,6600,1600,8200,200,9nonymous_,UP,POLY +S 2600,5800,2600,7200,200,10onymous_,UP,POLY +S 2100,1200,4900,1200,1200,11onymous_,RIGHT,ALU1 +S 100,1600,900,1600,300,12onymous_,RIGHT,ALU1 +S 0,1700,0,2900,300,13onymous_,UP,ALU1 +S 2000,8850,2000,9150,400,selxi,UP,CALU3 +S -150,2000,5150,2000,600,bit0,RIGHT,CALU2 +S -150,4000,5150,4000,600,nbit0,RIGHT,CALU2 +S -150,6000,5150,6000,600,bit1,RIGHT,CALU2 +S -150,8000,5150,8000,600,nbit1,RIGHT,CALU2 +S 5000,1850,5000,2950,600,18onymous_,UP,ALU2 +S 1800,10000,4400,10000,600,19onymous_,RIGHT,POLY +S 2000,9000,2000,10000,600,20onymous_,UP,POLY +S 100,5200,500,5200,300,21onymous_,RIGHT,ALU1 +S 3300,5200,4900,5200,300,22onymous_,RIGHT,ALU1 +S 4400,8200,4400,10000,200,23onymous_,UP,POLY +S 1200,8200,2600,8200,200,24onymous_,RIGHT,POLY +S 4400,7300,4400,7900,200,25onymous_,UP,NTRANS +S 2900,8200,3500,8200,200,26onymous_,RIGHT,NTRANS +S 3100,7600,3900,7600,600,27onymous_,RIGHT,NDIF +S 1200,5800,2600,5800,200,28onymous_,RIGHT,POLY +S 4400,6100,4400,6700,200,29onymous_,UP,NTRANS +S 3100,6400,3900,6400,600,30onymous_,RIGHT,NDIF +S 500,5800,900,5800,200,31onymous_,RIGHT,PTRANS +S 2900,5800,3500,5800,200,32onymous_,RIGHT,NTRANS +S 4400,4600,4400,5800,200,33onymous_,UP,POLY +S 1200,4600,2600,4600,200,34onymous_,RIGHT,POLY +S 2600,3200,2600,4600,200,35onymous_,UP,POLY +S 2900,4600,3500,4600,200,36onymous_,RIGHT,NTRANS +S 4400,3700,4400,4300,200,37onymous_,UP,NTRANS +S 3100,4000,3900,4000,600,38onymous_,RIGHT,NDIF +S 500,4600,900,4600,200,39onymous_,RIGHT,PTRANS +S 1200,2200,2800,2200,200,40onymous_,RIGHT,POLY +S 3100,2800,3900,2800,600,41onymous_,RIGHT,NDIF +S 4400,2500,4400,3100,200,42onymous_,UP,NTRANS +S 2900,2200,3500,2200,200,43onymous_,RIGHT,NTRANS +S 2000,9100,2000,9900,300,44onymous_,UP,ALU1 +S 4300,7600,4900,7600,300,45onymous_,RIGHT,ALU1 +S 4300,6400,4900,6400,300,46onymous_,RIGHT,ALU1 +S 4300,4000,4900,4000,300,47onymous_,RIGHT,ALU1 +S 4300,2800,4900,2800,300,48onymous_,RIGHT,ALU1 +S 3850,1000,5150,1000,600,49onymous_,RIGHT,ALU2 +S 3850,5000,5150,5000,600,50onymous_,RIGHT,ALU2 +S -150,5000,1150,5000,600,51onymous_,RIGHT,ALU2 +S -150,3000,1150,3000,600,52onymous_,RIGHT,ALU2 +S 3850,9000,5150,9000,600,53onymous_,RIGHT,ALU2 +S 1850,9000,3150,9000,600,54onymous_,RIGHT,ALU2 +S 1100,2800,3100,2800,300,data0,RIGHT,ALU1 +S 700,4000,3100,4000,300,ndata0,RIGHT,ALU1 +S 700,6400,3100,6400,300,data1,RIGHT,ALU1 +S -320,10000,1320,10000,600,55onymous_,RIGHT,NTIE +S 5000,8680,5000,10320,600,56onymous_,UP,PTIE +S 4079,1000,5120,1000,600,57onymous_,RIGHT,PTIE +S 1100,7600,3100,7600,300,ndata1,RIGHT,ALU1 +V 5000,0,CONT_VIA2,58onymous_ +V 4000,0,CONT_VIA2,59onymous_ +V 4000,0,CONT_VIA,60onymous_ +V 5000,0,CONT_VIA,61onymous_ +V 0,10000,CONT_VIA,62onymous_ +V 1000,10000,CONT_BODY_N,63onymous_ +V 1000,10000,CONT_VIA,64onymous_ +V 1000,10000,CONT_VIA2,65onymous_ +V 0,10000,CONT_VIA2,66onymous_ +V 1000,8800,CONT_DIF_P,69onymous_ +V 5000,1000,CONT_VIA,68onymous_ +V 5000,1000,CONT_VIA2,67onymous_ +V 1000,7600,CONT_DIF_P,70onymous_ +V 2400,7400,CONT_POLY,71onymous_ +V 1400,6600,CONT_POLY,72onymous_ +V 0,3000,CONT_VIA,73onymous_ +V 0,3000,CONT_VIA2,74onymous_ +V 1000,2800,CONT_DIF_P,75onymous_ +V 1000,1600,CONT_DIF_P,76onymous_ +V 2000,9000,CONT_VIA,77onymous_ +V 2000,9000,CONT_VIA2,78onymous_ +V 2000,9000,CONT_POLY,79onymous_ +V 5000,7600,CONT_VIA,80onymous_ +V 5000,6400,CONT_VIA,81onymous_ +V 5000,2800,CONT_VIA,82onymous_ +V 5000,7600,CONT_DIF_N,83onymous_ +V 3200,8800,CONT_DIF_N,84onymous_ +V 3200,7600,CONT_DIF_N,85onymous_ +V 3200,6400,CONT_DIF_N,86onymous_ +V 5000,6400,CONT_DIF_N,87onymous_ +V 600,6400,CONT_DIF_P,88onymous_ +V 3200,5200,CONT_DIF_N,89onymous_ +V 5000,4000,CONT_VIA,90onymous_ +V 3200,4000,CONT_DIF_N,91onymous_ +V 5000,4000,CONT_DIF_N,92onymous_ +V 1400,3800,CONT_POLY,93onymous_ +V 600,4000,CONT_DIF_P,94onymous_ +V 600,5200,CONT_DIF_P,95onymous_ +V 2400,3000,CONT_POLY,96onymous_ +V 5000,2800,CONT_DIF_N,97onymous_ +V 3200,2800,CONT_DIF_N,98onymous_ +V 3200,1600,CONT_DIF_N,99onymous_ +V 4000,1000,CONT_VIA2,100nymous_ +V 4000,1000,CONT_VIA,101nymous_ +V 0,5000,CONT_VIA2,102nymous_ +V 0,5000,CONT_VIA,103nymous_ +V 4000,9000,CONT_VIA2,104nymous_ +V 4000,9000,CONT_VIA,105nymous_ +V 4000,5000,CONT_VIA2,106nymous_ +V 4000,5000,CONT_VIA,107nymous_ +V 1000,5000,CONT_VIA2,108nymous_ +V 1000,3000,CONT_VIA2,109nymous_ +V 5000,5000,CONT_VIA2,110nymous_ +V 5000,9000,CONT_VIA2,111nymous_ +V 5000,9000,CONT_VIA,112nymous_ +V 5000,5000,CONT_VIA,113nymous_ +V 5000,10000,CONT_BODY_P,117nymous_ +V 5000,9000,CONT_BODY_P,116nymous_ +V 4400,1000,CONT_BODY_P,115nymous_ +V 0,10000,CONT_BODY_N,114nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_mem_data.vbe b/pdks/symbolic/nramlib/cells/ram_mem_data.vbe new file mode 100644 index 000000000..99fba01d0 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_data.vbe @@ -0,0 +1,49 @@ +entity RAM_MEM_DATA is + + port + ( + SELXI : in bit ; + BIT0 : inout wor_bit bus; + NBIT0 : inout wor_bit bus; + BIT1 : inout wor_bit bus; + NBIT1 : inout wor_bit bus; + VDD : in bit ; + VSS : in bit + ); + +end RAM_MEM_DATA; + +architecture vbe of RAM_MEM_DATA is + +signal LATCH0 : reg_bit register; +signal LATCH1 : reg_bit register; + +begin + + assert (VDD ='1' and VSS = '0') + report "power supply is missing on ram_mem_data" + severity WARNING; + + WRITE_0 : BLOCK ((SELXI and (BIT0 xor NBIT0)) = '1') + begin + LATCH0 <= guarded BIT0; + end block; + + WRITE_1 : BLOCK ((SELXI and (BIT1 xor NBIT1)) = '1') + begin + LATCH1 <= guarded BIT1; + end block; + + READ_0 : BLOCK ((SELXI and not SELXI'STABLE) = '1') + begin + BIT0 <= guarded LATCH0; + NBIT0 <= guarded not LATCH0; + end block; + + READ_1 : BLOCK ((SELXI and not SELXI'STABLE) = '1') + begin + BIT1 <= guarded LATCH1; + NBIT1 <= guarded not LATCH1; + end block; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_mem_dec2.ap b/pdks/symbolic/nramlib/cells/ram_mem_dec2.ap new file mode 100644 index 000000000..4fa95e58d --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_dec2.ap @@ -0,0 +1,119 @@ +V ALLIANCE : 6 +H ram_mem_dec2,P,23/4/2016,100 +A 0,0,20000,10000 +S 14000,1500,14000,2500,200,5nonymous_,UP,NTRANS +S 100,9400,19900,9400,1200,vdd,RIGHT,CALU1 +S 15000,-150,15000,10150,2400,vdd,UP,CALU3 +S 5000,-150,5000,10150,2400,vdd,UP,CALU3 +S 100,600,19900,600,1200,vss,RIGHT,CALU1 +S 20000,-150,20000,10150,2400,vss,UP,CALU3 +S 10000,-150,10000,10150,2400,vss,UP,CALU3 +S 0,-150,0,10150,2400,vss,UP,CALU3 +S 2100,4000,2900,4000,300,0nonymous_,RIGHT,ALU1 +S 12100,4000,12900,4000,300,1nonymous_,RIGHT,ALU1 +S 13400,7100,13400,8900,300,2nonymous_,UP,ALU1 +S 14600,2100,14600,7900,300,3nonymous_,UP,ALU1 +S 14600,1700,14600,2300,600,4nonymous_,UP,NDIF +S 9400,7800,20600,7800,6000,15onymous_,RIGHT,NWELL +S 11400,6100,11400,9300,300,16onymous_,UP,ALU1 +S 11400,700,11400,2900,300,17onymous_,UP,ALU1 +S 14700,4000,16900,4000,300,6nonymous_,RIGHT,ALU1 +S 12200,6200,14000,6200,200,7nonymous_,RIGHT,POLY +S 12200,2800,12200,6200,200,8nonymous_,UP,POLY +S 12200,2800,14000,2800,200,9nonymous_,RIGHT,POLY +S 13400,6700,13400,9100,600,10onymous_,UP,PDIF +S 14000,6500,14000,8500,200,11onymous_,UP,PTRANS +S 14600,6700,14600,8300,600,12onymous_,UP,PDIF +S 13400,700,13400,2300,600,13onymous_,UP,NDIF +S 13400,1100,13400,1900,300,14onymous_,UP,ALU1 +S 2200,2800,2200,6200,200,38onymous_,UP,POLY +S 2200,6200,4000,6200,200,37onymous_,RIGHT,POLY +S 4700,4000,6900,4000,300,36onymous_,RIGHT,ALU1 +S 4600,2100,4600,7900,300,35onymous_,UP,ALU1 +S 11400,280,11400,3320,600,18onymous_,UP,PTIE +S 11400,5680,11400,9720,600,19onymous_,UP,NTIE +S 18600,700,18600,2900,300,20onymous_,UP,ALU1 +S 18600,6100,18600,9300,300,21onymous_,UP,ALU1 +S 18600,280,18600,3320,600,22onymous_,UP,PTIE +S 18600,5680,18600,9720,600,23onymous_,UP,NTIE +S -600,7800,10600,7800,6000,24onymous_,RIGHT,NWELL +S 8600,6100,8600,9300,300,25onymous_,UP,ALU1 +S 8600,700,8600,2900,300,26onymous_,UP,ALU1 +S 8600,280,8600,3320,600,27onymous_,UP,PTIE +S 8600,5680,8600,9720,600,28onymous_,UP,NTIE +S 1400,700,1400,2900,300,29onymous_,UP,ALU1 +S 1400,6100,1400,9300,300,30onymous_,UP,ALU1 +S 1400,280,1400,3320,600,31onymous_,UP,PTIE +S 1400,5680,1400,9720,600,32onymous_,UP,NTIE +S 3400,1100,3400,1900,300,33onymous_,UP,ALU1 +S 3400,7100,3400,8900,300,34onymous_,UP,ALU1 +S 2200,2800,4000,2800,200,39onymous_,RIGHT,POLY +S 3400,700,3400,2300,600,40onymous_,UP,NDIF +S 4600,1700,4600,2300,600,41onymous_,UP,NDIF +S 4000,1500,4000,2500,200,42onymous_,UP,NTRANS +S 4000,6500,4000,8500,200,43onymous_,UP,PTRANS +S 4600,6700,4600,8300,600,44onymous_,UP,PDIF +S 3400,6700,3400,9100,600,45onymous_,UP,PDIF +S 1850,4000,3150,4000,600,i0,RIGHT,CALU2 +S 2000,3850,2000,4150,400,i0,UP,CALU3 +S 11850,4000,13150,4000,600,i1,RIGHT,CALU2 +S 12000,3850,12000,4150,400,i1,UP,CALU3 +S 5850,4000,7150,4000,600,ndeca,RIGHT,CALU2 +S 7000,3850,7000,4150,400,ndeca,UP,CALU3 +S 15850,4000,17150,4000,600,ndecb,RIGHT,CALU2 +S 17000,3850,17000,4150,400,ndecb,UP,CALU3 +V 13400,7000,CONT_DIF_P,46onymous_ +V 14600,8000,CONT_DIF_P,47onymous_ +V 14600,2000,CONT_DIF_N,48onymous_ +V 12000,4000,CONT_POLY,49onymous_ +V 12000,4000,CONT_VIA,50onymous_ +V 12000,4000,CONT_VIA2,51onymous_ +V 17000,4000,CONT_VIA,52onymous_ +V 17000,4000,CONT_VIA2,53onymous_ +V 13400,9000,CONT_DIF_P,54onymous_ +V 13400,8000,CONT_DIF_P,55onymous_ +V 14600,7000,CONT_DIF_P,56onymous_ +V 13400,1000,CONT_DIF_N,57onymous_ +V 13400,2000,CONT_DIF_N,58onymous_ +V 11400,600,CONT_BODY_P,59onymous_ +V 11400,2000,CONT_BODY_P,60onymous_ +V 11400,3000,CONT_BODY_P,61onymous_ +V 11400,6000,CONT_BODY_N,62onymous_ +V 11400,8000,CONT_BODY_N,63onymous_ +V 11400,9400,CONT_BODY_N,64onymous_ +V 11400,7000,CONT_BODY_N,65onymous_ +V 18600,3000,CONT_BODY_P,66onymous_ +V 8600,2000,CONT_BODY_P,74onymous_ +V 8600,600,CONT_BODY_P,73onymous_ +V 18600,9400,CONT_BODY_N,72onymous_ +V 18600,7000,CONT_BODY_N,71onymous_ +V 18600,6000,CONT_BODY_N,70onymous_ +V 18600,8000,CONT_BODY_N,69onymous_ +V 18600,600,CONT_BODY_P,68onymous_ +V 18600,2000,CONT_BODY_P,67onymous_ +V 8600,3000,CONT_BODY_P,75onymous_ +V 8600,6000,CONT_BODY_N,76onymous_ +V 8600,8000,CONT_BODY_N,77onymous_ +V 8600,9400,CONT_BODY_N,78onymous_ +V 8600,7000,CONT_BODY_N,79onymous_ +V 1400,3000,CONT_BODY_P,80onymous_ +V 1400,2000,CONT_BODY_P,81onymous_ +V 1400,600,CONT_BODY_P,82onymous_ +V 1400,8000,CONT_BODY_N,83onymous_ +V 1400,6000,CONT_BODY_N,84onymous_ +V 1400,7000,CONT_BODY_N,85onymous_ +V 1400,9400,CONT_BODY_N,86onymous_ +V 2000,4000,CONT_VIA2,87onymous_ +V 4600,8000,CONT_DIF_P,99onymous_ +V 3400,7000,CONT_DIF_P,98onymous_ +V 3400,8000,CONT_DIF_P,97onymous_ +V 3400,9000,CONT_DIF_P,96onymous_ +V 4600,7000,CONT_DIF_P,95onymous_ +V 3400,2000,CONT_DIF_N,94onymous_ +V 3400,1000,CONT_DIF_N,93onymous_ +V 4600,2000,CONT_DIF_N,92onymous_ +V 2000,4000,CONT_POLY,91onymous_ +V 2000,4000,CONT_VIA,90onymous_ +V 7000,4000,CONT_VIA,89onymous_ +V 7000,4000,CONT_VIA2,88onymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_mem_dec2.vbe b/pdks/symbolic/nramlib/cells/ram_mem_dec2.vbe new file mode 100644 index 000000000..972ceab2c --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_dec2.vbe @@ -0,0 +1,19 @@ +ENTITY ram_mem_dec2 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + ndeca : out BIT; + ndecb : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_dec2; + +ARCHITECTURE VBE OF ram_mem_dec2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_dec2" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_mem_dec3.ap b/pdks/symbolic/nramlib/cells/ram_mem_dec3.ap new file mode 100644 index 000000000..5a28348df --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_dec3.ap @@ -0,0 +1,134 @@ +V ALLIANCE : 6 +H ram_mem_dec3,P,23/4/2016,100 +A 0,0,20000,10000 +S 1400,280,1400,3320,600,4nonymous_,UP,PTIE +S 15000,-150,15000,10150,2400,vdd,UP,CALU3 +S 5000,-150,5000,10150,2400,vdd,UP,CALU3 +S 100,9400,19900,9400,1200,vdd,RIGHT,CALU1 +S 0,-150,0,10150,2400,vss,UP,CALU3 +S 10000,-150,10000,10150,2400,vss,UP,CALU3 +S 20000,-150,20000,10150,2400,vss,UP,CALU3 +S 100,600,19900,600,1200,vss,RIGHT,CALU1 +S 11100,4000,11900,4000,300,0nonymous_,RIGHT,ALU1 +S 3100,4000,3900,4000,300,1nonymous_,RIGHT,ALU1 +S 1100,4000,1900,4000,300,2nonymous_,RIGHT,ALU1 +S 1400,5680,1400,9720,600,3nonymous_,UP,NTIE +S 18600,6100,18600,9300,300,14onymous_,UP,ALU1 +S 18600,700,18600,2900,300,15onymous_,UP,ALU1 +S 11400,5680,11400,9720,600,16onymous_,UP,NTIE +S 11400,280,11400,3320,600,17onymous_,UP,PTIE +S 1400,6100,1400,9300,300,5nonymous_,UP,ALU1 +S 1400,700,1400,2900,300,6nonymous_,UP,ALU1 +S 8600,5680,8600,9720,600,7nonymous_,UP,NTIE +S 8600,280,8600,3320,600,8nonymous_,UP,PTIE +S 8600,700,8600,2900,300,9nonymous_,UP,ALU1 +S 8600,6100,8600,9300,300,10onymous_,UP,ALU1 +S -600,7800,10600,7800,6000,11onymous_,RIGHT,NWELL +S 18600,5680,18600,9720,600,12onymous_,UP,NTIE +S 18600,280,18600,3320,600,13onymous_,UP,PTIE +S 2200,2800,4000,2800,200,38onymous_,RIGHT,POLY +S 5200,3800,5200,6200,200,37onymous_,UP,POLY +S 4800,2800,4800,4200,200,36onymous_,UP,POLY +S 6100,4000,6900,4000,300,35onymous_,RIGHT,ALU1 +S 5500,2000,5900,2000,300,34onymous_,RIGHT,ALU1 +S 11400,700,11400,2900,300,18onymous_,UP,ALU1 +S 11400,6100,11400,9300,300,19onymous_,UP,ALU1 +S 9400,7800,20600,7800,6000,20onymous_,RIGHT,NWELL +S 13400,1100,13400,1900,300,21onymous_,UP,ALU1 +S 13400,700,13400,2300,600,22onymous_,UP,NDIF +S 14600,6700,14600,8300,600,23onymous_,UP,PDIF +S 14000,6500,14000,8500,200,24onymous_,UP,PTRANS +S 13400,6700,13400,9100,600,25onymous_,UP,PDIF +S 12200,2800,14000,2800,200,26onymous_,RIGHT,POLY +S 12200,2800,12200,6200,200,27onymous_,UP,POLY +S 12200,6200,14000,6200,200,28onymous_,RIGHT,POLY +S 3400,1100,3400,1900,300,29onymous_,UP,ALU1 +S 3400,8100,3400,8900,300,30onymous_,UP,ALU1 +S 5800,8100,5800,8900,300,31onymous_,UP,ALU1 +S 6000,2100,6000,6900,300,32onymous_,UP,ALU1 +S 4700,7000,5900,7000,300,33onymous_,RIGHT,ALU1 +S 2200,2800,2200,6200,200,39onymous_,UP,POLY +S 2200,6200,4000,6200,200,40onymous_,RIGHT,POLY +S 3000,4000,5200,4000,600,41onymous_,RIGHT,POLY +S 3400,700,3400,2300,600,42onymous_,UP,NDIF +S 5400,700,5400,2300,600,43onymous_,UP,NDIF +S 4000,500,4000,2500,200,44onymous_,UP,NTRANS +S 4800,500,4800,2500,200,45onymous_,UP,NTRANS +S 4600,6700,4600,8300,600,46onymous_,UP,PDIF +S 4000,6500,4000,8500,200,47onymous_,UP,PTRANS +S 5200,6500,5200,8500,200,48onymous_,UP,PTRANS +S 5800,6700,5800,9100,600,49onymous_,UP,PDIF +S 3400,6700,3400,9100,600,50onymous_,UP,PDIF +S 14700,4000,16900,4000,300,51onymous_,RIGHT,ALU1 +S 14000,1500,14000,2500,200,52onymous_,UP,NTRANS +S 14600,1700,14600,2300,600,53onymous_,UP,NDIF +S 14600,2100,14600,7900,300,54onymous_,UP,ALU1 +S 13400,7100,13400,8900,300,55onymous_,UP,ALU1 +S 850,4000,2150,4000,600,i0,RIGHT,CALU2 +S 2000,3850,2000,4150,400,i0,UP,CALU3 +S 2850,4000,4150,4000,600,i1,RIGHT,CALU2 +S 3000,3850,3000,4150,400,i1,UP,CALU3 +S 10850,4000,12150,4000,600,i2,RIGHT,CALU2 +S 12000,3850,12000,4150,400,i2,UP,CALU3 +S 5850,4000,7150,4000,600,ndeca,RIGHT,CALU2 +S 7000,3850,7000,4150,400,ndeca,UP,CALU3 +S 15850,4000,17150,4000,600,ndecb,RIGHT,CALU2 +S 17000,3850,17000,4150,400,ndecb,UP,CALU3 +V 1400,9400,CONT_BODY_N,56onymous_ +V 1400,7000,CONT_BODY_N,57onymous_ +V 1400,6000,CONT_BODY_N,58onymous_ +V 1400,8000,CONT_BODY_N,59onymous_ +V 1400,600,CONT_BODY_P,60onymous_ +V 1400,2000,CONT_BODY_P,61onymous_ +V 1400,3000,CONT_BODY_P,62onymous_ +V 8600,7000,CONT_BODY_N,63onymous_ +V 8600,9400,CONT_BODY_N,64onymous_ +V 8600,8000,CONT_BODY_N,65onymous_ +V 8600,6000,CONT_BODY_N,66onymous_ +V 18600,8000,CONT_BODY_N,73onymous_ +V 18600,6000,CONT_BODY_N,72onymous_ +V 18600,7000,CONT_BODY_N,71onymous_ +V 18600,9400,CONT_BODY_N,70onymous_ +V 8600,600,CONT_BODY_P,69onymous_ +V 8600,2000,CONT_BODY_P,68onymous_ +V 8600,3000,CONT_BODY_P,67onymous_ +V 18600,600,CONT_BODY_P,74onymous_ +V 18600,2000,CONT_BODY_P,75onymous_ +V 18600,3000,CONT_BODY_P,76onymous_ +V 11400,7000,CONT_BODY_N,77onymous_ +V 11400,9400,CONT_BODY_N,78onymous_ +V 11400,8000,CONT_BODY_N,79onymous_ +V 11400,6000,CONT_BODY_N,80onymous_ +V 11400,3000,CONT_BODY_P,81onymous_ +V 11400,2000,CONT_BODY_P,82onymous_ +V 11400,600,CONT_BODY_P,83onymous_ +V 13400,2000,CONT_DIF_N,84onymous_ +V 13400,1000,CONT_DIF_N,85onymous_ +V 14600,7000,CONT_DIF_P,86onymous_ +V 13400,8000,CONT_DIF_P,87onymous_ +V 13400,9000,CONT_DIF_P,88onymous_ +V 17000,4000,CONT_VIA2,89onymous_ +V 17000,4000,CONT_VIA,90onymous_ +V 12000,4000,CONT_VIA2,91onymous_ +V 12000,4000,CONT_VIA,92onymous_ +V 12000,4000,CONT_POLY,93onymous_ +V 7000,4000,CONT_VIA2,94onymous_ +V 2000,4000,CONT_VIA2,95onymous_ +V 3000,4000,CONT_VIA2,96onymous_ +V 7000,4000,CONT_VIA,97onymous_ +V 2000,4000,CONT_VIA,98onymous_ +V 3000,4000,CONT_VIA,99onymous_ +V 2000,4000,CONT_POLY,100nymous_ +V 13400,7000,CONT_DIF_P,112nymous_ +V 14600,8000,CONT_DIF_P,111nymous_ +V 14600,2000,CONT_DIF_N,110nymous_ +V 3400,9000,CONT_DIF_P,109nymous_ +V 3400,8000,CONT_DIF_P,108nymous_ +V 5800,8000,CONT_DIF_P,107nymous_ +V 4600,7000,CONT_DIF_P,106nymous_ +V 5800,9000,CONT_DIF_P,105nymous_ +V 3400,2000,CONT_DIF_N,104nymous_ +V 5400,2000,CONT_DIF_N,103nymous_ +V 3400,1000,CONT_DIF_N,102nymous_ +V 3000,4000,CONT_POLY,101nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_mem_dec3.vbe b/pdks/symbolic/nramlib/cells/ram_mem_dec3.vbe new file mode 100644 index 000000000..0e0acaca4 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_dec3.vbe @@ -0,0 +1,20 @@ +ENTITY ram_mem_dec3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + ndeca : out BIT; + ndecb : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_dec3; + +ARCHITECTURE VBE OF ram_mem_dec3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_dec3" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_mem_dec4.ap b/pdks/symbolic/nramlib/cells/ram_mem_dec4.ap new file mode 100644 index 000000000..949a4096d --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_dec4.ap @@ -0,0 +1,149 @@ +V ALLIANCE : 6 +H ram_mem_dec4,P,23/4/2016,100 +A 0,0,20000,10000 +S 1100,4000,1900,4000,300,3nonymous_,RIGHT,ALU1 +S 15000,-150,15000,10150,2400,vdd,UP,CALU3 +S 5000,-150,5000,10150,2400,vdd,UP,CALU3 +S 100,9400,19900,9400,1200,vdd,RIGHT,CALU1 +S 0,-150,0,10150,2400,vss,UP,CALU3 +S 10000,-150,10000,10150,2400,vss,UP,CALU3 +S 20000,-150,20000,10150,2400,vss,UP,CALU3 +S 100,600,19900,600,1200,vss,RIGHT,CALU1 +S 13100,4000,13900,4000,300,0nonymous_,RIGHT,ALU1 +S 11100,4000,11900,4000,300,1nonymous_,RIGHT,ALU1 +S 3100,4000,3900,4000,300,2nonymous_,RIGHT,ALU1 +S 18600,5680,18600,9720,600,13onymous_,UP,NTIE +S 18600,280,18600,3320,600,14onymous_,UP,PTIE +S 18600,6100,18600,9300,300,15onymous_,UP,ALU1 +S 18600,700,18600,2900,300,16onymous_,UP,ALU1 +S 11400,5680,11400,9720,600,17onymous_,UP,NTIE +S 1400,5680,1400,9720,600,4nonymous_,UP,NTIE +S 1400,280,1400,3320,600,5nonymous_,UP,PTIE +S 1400,6100,1400,9300,300,6nonymous_,UP,ALU1 +S 1400,700,1400,2900,300,7nonymous_,UP,ALU1 +S 8600,5680,8600,9720,600,8nonymous_,UP,NTIE +S 8600,280,8600,3320,600,9nonymous_,UP,PTIE +S 8600,700,8600,2900,300,10onymous_,UP,ALU1 +S 8600,6100,8600,9300,300,11onymous_,UP,ALU1 +S -600,7800,10600,7800,6000,12onymous_,RIGHT,NWELL +S 14800,2800,14800,4200,200,38onymous_,UP,POLY +S 16100,4000,16900,4000,300,37onymous_,RIGHT,ALU1 +S 15500,2000,15900,2000,300,36onymous_,RIGHT,ALU1 +S 14700,7000,15900,7000,300,35onymous_,RIGHT,ALU1 +S 16000,2100,16000,6900,300,34onymous_,UP,ALU1 +S 13400,6700,13400,9100,600,33onymous_,UP,PDIF +S 11400,280,11400,3320,600,18onymous_,UP,PTIE +S 11400,700,11400,2900,300,19onymous_,UP,ALU1 +S 11400,6100,11400,9300,300,20onymous_,UP,ALU1 +S 9400,7800,20600,7800,6000,21onymous_,RIGHT,NWELL +S 13400,1100,13400,1900,300,22onymous_,UP,ALU1 +S 13400,700,13400,2300,600,23onymous_,UP,NDIF +S 15400,700,15400,2300,600,24onymous_,UP,NDIF +S 14000,500,14000,2500,200,25onymous_,UP,NTRANS +S 14800,500,14800,2500,200,26onymous_,UP,NTRANS +S 13400,8100,13400,8900,300,27onymous_,UP,ALU1 +S 15800,8100,15800,8900,300,28onymous_,UP,ALU1 +S 14600,6700,14600,8300,600,29onymous_,UP,PDIF +S 14000,6500,14000,8500,200,30onymous_,UP,PTRANS +S 15200,6500,15200,8500,200,31onymous_,UP,PTRANS +S 15800,6700,15800,9100,600,32onymous_,UP,PDIF +S 15200,3800,15200,6200,200,39onymous_,UP,POLY +S 12200,2800,14000,2800,200,40onymous_,RIGHT,POLY +S 12200,2800,12200,6200,200,41onymous_,UP,POLY +S 12200,6200,14000,6200,200,42onymous_,RIGHT,POLY +S 13000,4000,15200,4000,600,43onymous_,RIGHT,POLY +S 3400,1100,3400,1900,300,44onymous_,UP,ALU1 +S 3400,8100,3400,8900,300,45onymous_,UP,ALU1 +S 5800,8100,5800,8900,300,46onymous_,UP,ALU1 +S 6000,2100,6000,6900,300,47onymous_,UP,ALU1 +S 4700,7000,5900,7000,300,48onymous_,RIGHT,ALU1 +S 5500,2000,5900,2000,300,49onymous_,RIGHT,ALU1 +S 6100,4000,6900,4000,300,50onymous_,RIGHT,ALU1 +S 4800,2800,4800,4200,200,51onymous_,UP,POLY +S 5200,3800,5200,6200,200,52onymous_,UP,POLY +S 2200,2800,4000,2800,200,53onymous_,RIGHT,POLY +S 2200,2800,2200,6200,200,54onymous_,UP,POLY +S 2200,6200,4000,6200,200,55onymous_,RIGHT,POLY +S 3000,4000,5200,4000,600,56onymous_,RIGHT,POLY +S 3400,700,3400,2300,600,57onymous_,UP,NDIF +S 5400,700,5400,2300,600,58onymous_,UP,NDIF +S 4000,500,4000,2500,200,59onymous_,UP,NTRANS +S 4800,500,4800,2500,200,60onymous_,UP,NTRANS +S 4600,6700,4600,8300,600,61onymous_,UP,PDIF +S 4000,6500,4000,8500,200,62onymous_,UP,PTRANS +S 5200,6500,5200,8500,200,63onymous_,UP,PTRANS +S 5800,6700,5800,9100,600,64onymous_,UP,PDIF +S 3400,6700,3400,9100,600,65onymous_,UP,PDIF +S 850,4000,2150,4000,600,i0,RIGHT,CALU2 +S 2000,3850,2000,4150,400,i0,UP,CALU3 +S 2850,4000,4150,4000,600,i1,RIGHT,CALU2 +S 3000,3850,3000,4150,400,i1,UP,CALU3 +S 10850,4000,12150,4000,600,i2,RIGHT,CALU2 +S 12000,3850,12000,4150,400,i2,UP,CALU3 +S 12850,4000,14150,4000,600,i3,RIGHT,CALU2 +S 13000,3850,13000,4150,400,i3,UP,CALU3 +S 5850,4000,7150,4000,600,ndeca,RIGHT,CALU2 +S 7000,3850,7000,4150,400,ndeca,UP,CALU3 +S 15850,4000,17150,4000,600,ndecb,RIGHT,CALU2 +S 17000,3850,17000,4150,400,ndecb,UP,CALU3 +V 1400,9400,CONT_BODY_N,66onymous_ +V 1400,3000,CONT_BODY_P,72onymous_ +V 1400,2000,CONT_BODY_P,71onymous_ +V 1400,600,CONT_BODY_P,70onymous_ +V 1400,8000,CONT_BODY_N,69onymous_ +V 1400,6000,CONT_BODY_N,68onymous_ +V 1400,7000,CONT_BODY_N,67onymous_ +V 8600,7000,CONT_BODY_N,73onymous_ +V 8600,9400,CONT_BODY_N,74onymous_ +V 8600,8000,CONT_BODY_N,75onymous_ +V 8600,6000,CONT_BODY_N,76onymous_ +V 8600,3000,CONT_BODY_P,77onymous_ +V 8600,2000,CONT_BODY_P,78onymous_ +V 8600,600,CONT_BODY_P,79onymous_ +V 18600,9400,CONT_BODY_N,80onymous_ +V 18600,7000,CONT_BODY_N,81onymous_ +V 18600,6000,CONT_BODY_N,82onymous_ +V 18600,8000,CONT_BODY_N,83onymous_ +V 18600,600,CONT_BODY_P,84onymous_ +V 18600,2000,CONT_BODY_P,85onymous_ +V 18600,3000,CONT_BODY_P,86onymous_ +V 11400,7000,CONT_BODY_N,87onymous_ +V 11400,9400,CONT_BODY_N,88onymous_ +V 11400,8000,CONT_BODY_N,89onymous_ +V 11400,6000,CONT_BODY_N,90onymous_ +V 11400,3000,CONT_BODY_P,91onymous_ +V 11400,2000,CONT_BODY_P,92onymous_ +V 11400,600,CONT_BODY_P,93onymous_ +V 13400,2000,CONT_DIF_N,94onymous_ +V 13400,1000,CONT_DIF_N,95onymous_ +V 15800,9000,CONT_DIF_P,96onymous_ +V 14600,7000,CONT_DIF_P,97onymous_ +V 15800,8000,CONT_DIF_P,98onymous_ +V 13400,8000,CONT_DIF_P,99onymous_ +V 13400,9000,CONT_DIF_P,100nymous_ +V 15400,2000,CONT_DIF_N,101nymous_ +V 17000,4000,CONT_VIA2,102nymous_ +V 17000,4000,CONT_VIA,103nymous_ +V 12000,4000,CONT_VIA2,104nymous_ +V 13000,4000,CONT_VIA2,105nymous_ +V 12000,4000,CONT_VIA,106nymous_ +V 13000,4000,CONT_VIA,107nymous_ +V 12000,4000,CONT_POLY,108nymous_ +V 13000,4000,CONT_POLY,109nymous_ +V 7000,4000,CONT_VIA2,110nymous_ +V 4600,7000,CONT_DIF_P,122nymous_ +V 5800,9000,CONT_DIF_P,121nymous_ +V 3400,2000,CONT_DIF_N,120nymous_ +V 5400,2000,CONT_DIF_N,119nymous_ +V 3400,1000,CONT_DIF_N,118nymous_ +V 3000,4000,CONT_POLY,117nymous_ +V 2000,4000,CONT_POLY,116nymous_ +V 3000,4000,CONT_VIA,115nymous_ +V 2000,4000,CONT_VIA,114nymous_ +V 7000,4000,CONT_VIA,113nymous_ +V 3000,4000,CONT_VIA2,112nymous_ +V 2000,4000,CONT_VIA2,111nymous_ +V 5800,8000,CONT_DIF_P,123nymous_ +V 3400,8000,CONT_DIF_P,124nymous_ +V 3400,9000,CONT_DIF_P,125nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_mem_dec4.vbe b/pdks/symbolic/nramlib/cells/ram_mem_dec4.vbe new file mode 100644 index 000000000..bcfdbea8b --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_dec4.vbe @@ -0,0 +1,21 @@ +ENTITY ram_mem_dec4 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + ndeca : out BIT; + ndecb : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_dec4; + +ARCHITECTURE VBE OF ram_mem_dec4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_dec4" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_mem_dec5.ap b/pdks/symbolic/nramlib/cells/ram_mem_dec5.ap new file mode 100644 index 000000000..70b35f0f5 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_dec5.ap @@ -0,0 +1,163 @@ +V ALLIANCE : 6 +H ram_mem_dec5,P,23/4/2016,100 +A 0,0,20000,10000 +S 4800,3800,4800,6200,200,2nonymous_,UP,POLY +S 15000,-150,15000,10150,2400,vdd,UP,CALU3 +S 5000,-150,5000,10150,2400,vdd,UP,CALU3 +S 100,9400,19900,9400,1200,vdd,RIGHT,CALU1 +S 0,-150,0,10150,2400,vss,UP,CALU3 +S 10000,-150,10000,10150,2400,vss,UP,CALU3 +S 20000,-150,20000,10150,2400,vss,UP,CALU3 +S 100,600,19900,600,1200,vss,RIGHT,CALU1 +S 3800,2800,4400,2800,200,0nonymous_,RIGHT,POLY +S 3800,2800,3800,6200,200,1nonymous_,UP,POLY +S 5000,6700,5000,9100,600,12onymous_,UP,PDIF +S 2600,6700,2600,9100,600,13onymous_,UP,PDIF +S 3200,6500,3200,8500,200,14onymous_,UP,PTRANS +S 4400,6500,4400,8500,200,15onymous_,UP,PTRANS +S 5600,6500,5600,8500,200,16onymous_,UP,PTRANS +S 6200,6700,6200,8300,600,17onymous_,UP,PDIF +S 5200,2800,5200,4200,200,3nonymous_,UP,POLY +S 3100,2000,3700,2000,300,4nonymous_,RIGHT,ALU1 +S 3200,6200,3800,6200,200,5nonymous_,RIGHT,POLY +S 4400,6200,4800,6200,200,6nonymous_,RIGHT,POLY +S 1400,5680,1400,9720,600,7nonymous_,UP,NTIE +S 1400,280,1400,3320,600,8nonymous_,UP,PTIE +S 1400,6100,1400,9300,300,9nonymous_,UP,ALU1 +S 1400,700,1400,2900,300,10onymous_,UP,ALU1 +S 3800,6700,3800,8300,600,11onymous_,UP,PDIF +S 18600,5680,18600,9720,600,38onymous_,UP,NTIE +S 2000,4000,3800,4000,600,37onymous_,RIGHT,POLY +S 4800,4000,7000,4000,600,36onymous_,RIGHT,POLY +S 5600,6200,7800,6200,200,35onymous_,RIGHT,POLY +S 6000,2800,7800,2800,200,34onymous_,RIGHT,POLY +S 7800,2800,7800,6200,200,33onymous_,UP,POLY +S 6600,1100,6600,1900,300,32onymous_,UP,ALU1 +S 4400,500,4400,2500,200,18onymous_,UP,NTRANS +S 5200,500,5200,2500,200,19onymous_,UP,NTRANS +S 6000,500,6000,2500,200,20onymous_,UP,NTRANS +S 3800,700,3800,2300,600,21onymous_,UP,NDIF +S 2600,8100,2600,8900,300,22onymous_,UP,ALU1 +S 5000,8100,5000,8900,300,23onymous_,UP,ALU1 +S 3000,2100,3000,6900,300,24onymous_,UP,ALU1 +S 3100,7000,6100,7000,300,25onymous_,RIGHT,ALU1 +S 8600,5680,8600,9720,600,26onymous_,UP,NTIE +S 8600,280,8600,3320,600,27onymous_,UP,PTIE +S 8600,700,8600,2900,300,28onymous_,UP,ALU1 +S 8600,6100,8600,9300,300,29onymous_,UP,ALU1 +S -600,7800,10600,7800,6000,30onymous_,RIGHT,NWELL +S 6600,700,6600,2300,600,31onymous_,UP,NDIF +S 18600,280,18600,3320,600,39onymous_,UP,PTIE +S 18600,6100,18600,9300,300,40onymous_,UP,ALU1 +S 18600,700,18600,2900,300,41onymous_,UP,ALU1 +S 11400,5680,11400,9720,600,42onymous_,UP,NTIE +S 11400,280,11400,3320,600,43onymous_,UP,PTIE +S 11400,700,11400,2900,300,44onymous_,UP,ALU1 +S 11400,6100,11400,9300,300,45onymous_,UP,ALU1 +S 9400,7800,20600,7800,6000,46onymous_,RIGHT,NWELL +S 13400,1100,13400,1900,300,47onymous_,UP,ALU1 +S 13400,700,13400,2300,600,48onymous_,UP,NDIF +S 15400,700,15400,2300,600,49onymous_,UP,NDIF +S 14000,500,14000,2500,200,50onymous_,UP,NTRANS +S 14800,500,14800,2500,200,51onymous_,UP,NTRANS +S 13400,8100,13400,8900,300,52onymous_,UP,ALU1 +S 15800,8100,15800,8900,300,53onymous_,UP,ALU1 +S 14600,6700,14600,8300,600,54onymous_,UP,PDIF +S 14000,6500,14000,8500,200,55onymous_,UP,PTRANS +S 15200,6500,15200,8500,200,56onymous_,UP,PTRANS +S 15800,6700,15800,9100,600,57onymous_,UP,PDIF +S 13400,6700,13400,9100,600,58onymous_,UP,PDIF +S 16000,2100,16000,6900,300,59onymous_,UP,ALU1 +S 14700,7000,15900,7000,300,60onymous_,RIGHT,ALU1 +S 15500,2000,15900,2000,300,61onymous_,RIGHT,ALU1 +S 16100,4000,16900,4000,300,62onymous_,RIGHT,ALU1 +S 14800,2800,14800,4200,200,63onymous_,UP,POLY +S 15200,3800,15200,6200,200,64onymous_,UP,POLY +S 12200,2800,14000,2800,200,65onymous_,RIGHT,POLY +S 12200,2800,12200,6200,200,66onymous_,UP,POLY +S 8100,4000,8900,4000,300,71onymous_,RIGHT,ALU1 +S 6100,4000,6900,4000,300,70onymous_,RIGHT,ALU1 +S 1100,4000,1900,4000,300,69onymous_,RIGHT,ALU1 +S 13000,4000,15200,4000,600,68onymous_,RIGHT,POLY +S 12200,6200,14000,6200,200,67onymous_,RIGHT,POLY +S 850,4000,2150,4000,600,i0,RIGHT,CALU2 +S 2000,3850,2000,4150,400,i0,UP,CALU3 +S 5850,4000,7150,4000,600,i1,RIGHT,CALU2 +S 7000,3850,7000,4150,400,i1,UP,CALU3 +S 7850,4000,9150,4000,600,i2,RIGHT,CALU2 +S 8000,3850,8000,4150,400,i2,UP,CALU3 +S 10850,4000,12150,4000,600,i3,RIGHT,CALU2 +S 12000,3850,12000,4150,400,i3,UP,CALU3 +S 2850,4000,4150,4000,600,ndeca,RIGHT,CALU2 +S 3000,3850,3000,4150,400,ndeca,UP,CALU3 +S 15850,4000,17150,4000,600,ndecb,RIGHT,CALU2 +S 17000,3850,17000,4150,400,ndecb,UP,CALU3 +S 11100,4000,11900,4000,300,72onymous_,RIGHT,ALU1 +S 13100,4000,13900,4000,300,73onymous_,RIGHT,ALU1 +S 12850,4000,14150,4000,600,i4,RIGHT,CALU2 +S 13000,3850,13000,4150,400,i4,UP,CALU3 +V 3000,4000,CONT_VIA,74onymous_ +V 2000,4000,CONT_VIA,75onymous_ +V 3000,4000,CONT_VIA2,76onymous_ +V 2000,4000,CONT_VIA2,77onymous_ +V 3800,2000,CONT_DIF_N,78onymous_ +V 1400,9400,CONT_BODY_N,79onymous_ +V 1400,7000,CONT_BODY_N,80onymous_ +V 1400,6000,CONT_BODY_N,81onymous_ +V 1400,8000,CONT_BODY_N,82onymous_ +V 1400,600,CONT_BODY_P,83onymous_ +V 1400,2000,CONT_BODY_P,84onymous_ +V 1400,3000,CONT_BODY_P,85onymous_ +V 5000,9000,CONT_DIF_P,86onymous_ +V 5000,8000,CONT_DIF_P,87onymous_ +V 2600,8000,CONT_DIF_P,88onymous_ +V 3800,7000,CONT_DIF_P,89onymous_ +V 6200,7000,CONT_DIF_P,90onymous_ +V 2600,9000,CONT_DIF_P,91onymous_ +V 8600,7000,CONT_BODY_N,92onymous_ +V 8600,9400,CONT_BODY_N,93onymous_ +V 8600,8000,CONT_BODY_N,94onymous_ +V 8600,6000,CONT_BODY_N,95onymous_ +V 8600,3000,CONT_BODY_P,96onymous_ +V 8600,2000,CONT_BODY_P,97onymous_ +V 8600,600,CONT_BODY_P,98onymous_ +V 6600,1000,CONT_DIF_N,99onymous_ +V 6600,2000,CONT_DIF_N,100nymous_ +V 7000,4000,CONT_VIA2,101nymous_ +V 8000,4000,CONT_VIA2,102nymous_ +V 7000,4000,CONT_VIA,103nymous_ +V 8000,4000,CONT_VIA,104nymous_ +V 8000,4000,CONT_POLY,105nymous_ +V 7000,4000,CONT_POLY,106nymous_ +V 2000,4000,CONT_POLY,107nymous_ +V 18600,9400,CONT_BODY_N,108nymous_ +V 18600,7000,CONT_BODY_N,109nymous_ +V 18600,6000,CONT_BODY_N,110nymous_ +V 13400,2000,CONT_DIF_N,122nymous_ +V 11400,600,CONT_BODY_P,121nymous_ +V 11400,2000,CONT_BODY_P,120nymous_ +V 11400,3000,CONT_BODY_P,119nymous_ +V 11400,6000,CONT_BODY_N,118nymous_ +V 11400,8000,CONT_BODY_N,117nymous_ +V 11400,9400,CONT_BODY_N,116nymous_ +V 11400,7000,CONT_BODY_N,115nymous_ +V 18600,3000,CONT_BODY_P,114nymous_ +V 18600,2000,CONT_BODY_P,113nymous_ +V 18600,600,CONT_BODY_P,112nymous_ +V 18600,8000,CONT_BODY_N,111nymous_ +V 13400,1000,CONT_DIF_N,123nymous_ +V 15800,9000,CONT_DIF_P,124nymous_ +V 14600,7000,CONT_DIF_P,125nymous_ +V 15800,8000,CONT_DIF_P,126nymous_ +V 13400,8000,CONT_DIF_P,127nymous_ +V 13400,9000,CONT_DIF_P,128nymous_ +V 15400,2000,CONT_DIF_N,129nymous_ +V 17000,4000,CONT_VIA2,130nymous_ +V 17000,4000,CONT_VIA,131nymous_ +V 12000,4000,CONT_VIA2,132nymous_ +V 13000,4000,CONT_VIA2,133nymous_ +V 12000,4000,CONT_VIA,134nymous_ +V 13000,4000,CONT_VIA,135nymous_ +V 12000,4000,CONT_POLY,136nymous_ +V 13000,4000,CONT_POLY,137nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_mem_dec5.vbe b/pdks/symbolic/nramlib/cells/ram_mem_dec5.vbe new file mode 100644 index 000000000..ef4d7906b --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_dec5.vbe @@ -0,0 +1,22 @@ +ENTITY ram_mem_dec5 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + ndeca : out BIT; + ndecb : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_dec5; + +ARCHITECTURE VBE OF ram_mem_dec5 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_dec5" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_mem_deci.ap b/pdks/symbolic/nramlib/cells/ram_mem_deci.ap new file mode 100644 index 000000000..441a71f89 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_deci.ap @@ -0,0 +1,67 @@ +V ALLIANCE : 6 +H ram_mem_deci,P,23/4/2016,100 +A 0,0,5000,10000 +S 3600,3000,4200,3000,600,17onymous_,RIGHT,POLY +S 2400,2800,2400,3800,200,16onymous_,UP,POLY +S 2800,4000,2800,5200,200,15onymous_,UP,POLY +S 2800,5500,2800,9500,200,4nonymous_,UP,PTRANS +S 4200,5700,4200,9300,600,3nonymous_,UP,PDIF +S 1000,3100,1000,7900,300,2nonymous_,UP,ALU1 +S 700,3000,2900,3000,300,1nonymous_,RIGHT,ALU1 +S 600,2100,600,2900,300,0nonymous_,UP,ALU1 +S 100,600,4900,600,1200,vss,RIGHT,CALU1 +S 5000,-150,5000,10150,2400,vss,UP,CALU3 +S 1200,2800,1200,4800,200,14onymous_,UP,POLY +S 1200,4800,2200,4800,200,13onymous_,RIGHT,POLY +S 600,1700,600,2300,600,12onymous_,UP,NDIF +S 3000,1700,3000,2300,600,11onymous_,UP,NDIF +S 2400,1500,2400,2500,200,10onymous_,UP,NTRANS +S 3600,1500,3600,2500,200,9nonymous_,UP,NTRANS +S 1200,1500,1200,2500,200,8nonymous_,UP,NTRANS +S -600,7800,5600,7800,6000,7nonymous_,RIGHT,NWELL +S 3600,5500,3600,9500,200,6nonymous_,UP,PTRANS +S 2000,5500,2000,9500,200,5nonymous_,UP,PTRANS +S 100,9400,4900,9400,1200,vdd,RIGHT,CALU1 +S 0,-150,0,10150,2400,vdd,UP,CALU3 +S 280,600,4520,600,600,33onymous_,RIGHT,PTIE +S 4200,700,4200,1900,300,32onymous_,UP,ALU1 +S 1800,700,1800,1900,300,31onymous_,UP,ALU1 +S 4200,7100,4200,8900,300,30onymous_,UP,ALU1 +S 4200,1700,4200,2300,600,29onymous_,UP,NDIF +S 1800,1700,1800,2300,600,28onymous_,UP,NDIF +S 1000,5700,1000,9300,600,27onymous_,UP,PDIF +S 1400,5700,1400,9300,600,26onymous_,UP,PDIF +S 3000,2100,3000,2900,300,25onymous_,UP,ALU1 +S 2050,2000,2950,2000,300,24onymous_,RIGHT,TALU2 +S 1850,2000,3150,2000,600,23onymous_,RIGHT,ALU2 +S 2000,5100,2000,7900,300,22onymous_,UP,ALU1 +S 3000,4100,3000,6900,300,21onymous_,UP,ALU1 +S 4200,2800,4200,5200,200,20onymous_,UP,POLY +S 3600,5200,4200,5200,200,19onymous_,RIGHT,POLY +S 2400,4000,3200,4000,600,18onymous_,RIGHT,POLY +S 3000,1850,3000,2150,400,seli,UP,CALU3 +S 4000,3100,4000,5900,300,i2,UP,CALU1 +S 1850,8000,3150,8000,600,i1,RIGHT,CALU2 +S 1850,7000,3150,7000,600,i0,RIGHT,CALU2 +V 1000,6000,CONT_DIF_P,34onymous_ +V 4200,600,CONT_BODY_P,54onymous_ +V 1800,600,CONT_BODY_P,53onymous_ +V 4200,7000,CONT_DIF_P,52onymous_ +V 4200,8000,CONT_DIF_P,51onymous_ +V 1800,2000,CONT_DIF_N,50onymous_ +V 4200,2000,CONT_DIF_N,49onymous_ +V 3000,2000,CONT_VIA2,48onymous_ +V 3000,7000,CONT_VIA,47onymous_ +V 2000,8000,CONT_VIA,46onymous_ +V 3000,2000,CONT_VIA,45onymous_ +V 4000,3000,CONT_POLY,44onymous_ +V 2000,5000,CONT_POLY,43onymous_ +V 3000,4000,CONT_POLY,42onymous_ +V 600,600,CONT_BODY_P,41onymous_ +V 3000,600,CONT_BODY_P,40onymous_ +V 3000,2000,CONT_DIF_N,39onymous_ +V 600,2000,CONT_DIF_N,38onymous_ +V 4200,9000,CONT_DIF_P,37onymous_ +V 1000,8000,CONT_DIF_P,36onymous_ +V 1000,7000,CONT_DIF_P,35onymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_mem_deci.vbe b/pdks/symbolic/nramlib/cells/ram_mem_deci.vbe new file mode 100644 index 000000000..dbedb9068 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_mem_deci.vbe @@ -0,0 +1,19 @@ +ENTITY ram_mem_deci IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + seli : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_deci; + +ARCHITECTURE VBE OF ram_mem_deci IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_deci" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_prech_buf0.ap b/pdks/symbolic/nramlib/cells/ram_prech_buf0.ap new file mode 100644 index 000000000..81dd194c6 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_prech_buf0.ap @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H ram_prech_buf0,P,23/4/2016,100 +A 0,0,6000,10000 +S 1800,5500,1800,9500,200,6nonymous_,UP,PTRANS +S 2850,4000,4150,4000,600,5nonymous_,RIGHT,ALU2 +S 2850,5000,4150,5000,600,4nonymous_,RIGHT,ALU2 +S 3600,7100,3600,8900,300,3nonymous_,UP,ALU1 +S 3600,5100,3600,5900,300,2nonymous_,UP,ALU1 +S 3050,5000,3950,5000,300,1nonymous_,RIGHT,TALU2 +S 3050,4000,3950,4000,300,0nonymous_,RIGHT,TALU2 +S 100,600,5900,600,1200,vss,RIGHT,CALU1 +S 100,9400,5900,9400,1200,vdd,RIGHT,CALU1 +S 4000,3850,4000,4150,400,nq,UP,CALU3 +S 1200,700,1200,2300,600,16onymous_,UP,NDIF +S 1800,500,1800,2500,200,15onymous_,UP,NTRANS +S 4200,500,4200,2500,200,14onymous_,UP,NTRANS +S 3000,500,3000,2500,200,13onymous_,UP,NTRANS +S 3000,5500,3000,9500,200,12onymous_,UP,PTRANS +S 3600,5700,3600,9300,600,11onymous_,UP,PDIF +S 4200,5500,4200,9500,200,10onymous_,UP,PTRANS +S 2400,5700,2400,9300,600,9nonymous_,UP,PDIF +S 4800,5700,4800,9300,600,8nonymous_,UP,PDIF +S 1200,5700,1200,9300,600,7nonymous_,UP,PDIF +S 4000,4850,4000,5150,400,i,UP,CALU3 +S 2400,700,2400,2300,600,17onymous_,UP,NDIF +S 2000,-150,2000,10150,2400,32onymous_,UP,ALU3 +S 6000,-150,6000,10150,2400,31onymous_,UP,ALU3 +S -600,7800,6600,7800,6000,30onymous_,RIGHT,NWELL +S 3600,1100,3600,1900,300,29onymous_,UP,ALU1 +S 2400,2100,2400,7900,300,28onymous_,UP,ALU1 +S 4800,2100,4800,7900,300,27onymous_,UP,ALU1 +S 2500,4000,4700,4000,300,26onymous_,RIGHT,ALU1 +S 1200,1100,1200,1900,300,25onymous_,UP,ALU1 +S 1200,6100,1200,8900,300,24onymous_,UP,ALU1 +S 3000,2800,3000,5200,200,23onymous_,UP,POLY +S 1800,2800,1800,5200,200,22onymous_,UP,POLY +S 1800,5000,4200,5000,600,21onymous_,RIGHT,POLY +S 4200,2800,4200,5200,200,20onymous_,UP,POLY +S 3600,700,3600,2300,600,19onymous_,UP,NDIF +S 4800,700,4800,2300,600,18onymous_,UP,NDIF +V 4000,4000,CONT_VIA,36onymous_ +V 4000,4000,CONT_VIA2,35onymous_ +V 3600,5000,CONT_VIA,34onymous_ +V 3600,5000,CONT_POLY,33onymous_ +V 1200,7000,CONT_DIF_P,37onymous_ +V 4000,5000,CONT_VIA2,56onymous_ +V 3600,1000,CONT_DIF_N,55onymous_ +V 2400,2000,CONT_DIF_N,54onymous_ +V 3600,2000,CONT_DIF_N,53onymous_ +V 4800,2000,CONT_DIF_N,52onymous_ +V 1200,2000,CONT_DIF_N,51onymous_ +V 1200,1000,CONT_DIF_N,50onymous_ +V 2400,6000,CONT_DIF_P,49onymous_ +V 2400,7000,CONT_DIF_P,48onymous_ +V 2400,8000,CONT_DIF_P,47onymous_ +V 4800,8000,CONT_DIF_P,46onymous_ +V 4800,7000,CONT_DIF_P,45onymous_ +V 3600,7000,CONT_DIF_P,44onymous_ +V 3600,8000,CONT_DIF_P,43onymous_ +V 3600,9000,CONT_DIF_P,42onymous_ +V 4800,6000,CONT_DIF_P,41onymous_ +V 1200,8000,CONT_DIF_P,40onymous_ +V 1200,9000,CONT_DIF_P,39onymous_ +V 1200,6000,CONT_DIF_P,38onymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_prech_buf0.vbe b/pdks/symbolic/nramlib/cells/ram_prech_buf0.vbe new file mode 100644 index 000000000..81fed27f5 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_prech_buf0.vbe @@ -0,0 +1,17 @@ +ENTITY ram_prech_buf0 IS +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_prech_buf0; + +ARCHITECTURE VBE OF ram_prech_buf0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_prech_buf0" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_prech_buf1.ap b/pdks/symbolic/nramlib/cells/ram_prech_buf1.ap new file mode 100644 index 000000000..6d8c72b11 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_prech_buf1.ap @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H ram_prech_buf1,P,23/4/2016,100 +A 0,0,6000,10000 +S 4000,6850,4000,7150,400,nckx,UP,CALU3 +S 3000,7100,3000,8900,300,17onymous_,UP,ALU1 +S 2400,5500,2400,9500,200,6nonymous_,UP,PTRANS +S 3000,5700,3000,9300,600,5nonymous_,UP,PDIF +S 3600,5500,3600,9500,200,4nonymous_,UP,PTRANS +S 1800,5700,1800,9300,600,3nonymous_,UP,PDIF +S 4200,5700,4200,9300,600,2nonymous_,UP,PDIF +S 600,680,600,2320,600,1nonymous_,UP,PTIE +S 600,5680,600,9320,600,0nonymous_,UP,NTIE +S 100,600,5900,600,1200,vss,RIGHT,CALU1 +S 100,9400,5900,9400,1200,vdd,RIGHT,CALU1 +S 3000,1100,3000,1900,300,16onymous_,UP,ALU1 +S 1800,2100,1800,7900,300,15onymous_,UP,ALU1 +S 4200,2100,4200,7900,300,14onymous_,UP,ALU1 +S 3600,2800,3600,5200,200,13onymous_,UP,POLY +S 2400,2800,2400,5200,200,12onymous_,UP,POLY +S 1800,700,1800,2300,600,11onymous_,UP,NDIF +S 3000,700,3000,2300,600,10onymous_,UP,NDIF +S 4200,700,4200,2300,600,9nonymous_,UP,NDIF +S 3600,500,3600,2500,200,8nonymous_,UP,NTRANS +S 2400,500,2400,2500,200,7nonymous_,UP,NTRANS +S 2050,7000,3950,7000,300,28onymous_,RIGHT,TALU2 +S 2400,4000,3000,4000,600,27onymous_,RIGHT,POLY +S 1850,7000,4150,7000,600,26onymous_,RIGHT,ALU2 +S 3100,4000,4100,4000,300,25onymous_,RIGHT,ALU1 +S 3000,5000,3600,5000,600,24onymous_,RIGHT,POLY +S 3000,5100,3000,5900,300,23onymous_,UP,ALU1 +S 850,10000,6150,10000,2600,22onymous_,RIGHT,ALU2 +S 850,0,6150,0,2600,21onymous_,RIGHT,ALU2 +S 2850,5000,4150,5000,600,nck,RIGHT,CALU2 +S -600,7800,6600,7800,6000,18onymous_,RIGHT,NWELL +S 2000,-150,2000,10150,2400,19onymous_,UP,ALU3 +S 6000,-150,6000,10150,2400,20onymous_,UP,ALU3 +V 4200,7000,CONT_DIF_P,36onymous_ +V 3000,7000,CONT_DIF_P,35onymous_ +V 600,2000,CONT_BODY_P,34onymous_ +V 600,8000,CONT_BODY_N,33onymous_ +V 600,7000,CONT_BODY_N,32onymous_ +V 600,6000,CONT_BODY_N,31onymous_ +V 600,9000,CONT_BODY_N,30onymous_ +V 600,1000,CONT_BODY_P,29onymous_ +V 4000,7000,CONT_VIA2,52onymous_ +V 2000,7000,CONT_VIA,51onymous_ +V 2800,4000,CONT_POLY,50onymous_ +V 3000,5000,CONT_VIA,49onymous_ +V 3200,5000,CONT_POLY,48onymous_ +V 3000,1000,CONT_DIF_N,47onymous_ +V 1800,2000,CONT_DIF_N,46onymous_ +V 3000,2000,CONT_DIF_N,45onymous_ +V 4200,2000,CONT_DIF_N,44onymous_ +V 3000,8000,CONT_DIF_P,43onymous_ +V 3000,9000,CONT_DIF_P,42onymous_ +V 4200,6000,CONT_DIF_P,41onymous_ +V 1800,6000,CONT_DIF_P,40onymous_ +V 1800,7000,CONT_DIF_P,39onymous_ +V 1800,8000,CONT_DIF_P,38onymous_ +V 4200,8000,CONT_DIF_P,37onymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_prech_buf1.vbe b/pdks/symbolic/nramlib/cells/ram_prech_buf1.vbe new file mode 100644 index 000000000..859d4aecd --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_prech_buf1.vbe @@ -0,0 +1,19 @@ +ENTITY ram_prech_buf1 IS +PORT ( + nck : in BIT; + nckx : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_prech_buf1; + +ARCHITECTURE VBE OF ram_prech_buf1 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_prech_buf1" + SEVERITY WARNING; + + nckx <= nck; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_prech_data.ap b/pdks/symbolic/nramlib/cells/ram_prech_data.ap new file mode 100644 index 000000000..0fdd95118 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_prech_data.ap @@ -0,0 +1,93 @@ +V ALLIANCE : 6 +H ram_prech_data,P,23/4/2016,100 +A 0,0,6000,10000 +S 1700,2600,3300,2600,200,4nonymous_,RIGHT,NTRANS +S 100,9400,4100,9400,1200,vdd,RIGHT,CALU1 +S 100,600,5900,600,1200,vss,RIGHT,CALU1 +S 680,600,3320,600,600,0nonymous_,RIGHT,PTIE +S 1700,6200,3300,6200,200,1nonymous_,RIGHT,NTRANS +S 1700,7400,3300,7400,200,2nonymous_,RIGHT,NTRANS +S 1700,3800,3300,3800,200,3nonymous_,RIGHT,NTRANS +S 2100,2000,2700,2000,300,14onymous_,RIGHT,ALU1 +S 2100,5600,2700,5600,300,15onymous_,RIGHT,ALU1 +S 1850,2000,2950,2000,600,16onymous_,RIGHT,ALU2 +S 1850,5600,2950,5600,600,17onymous_,RIGHT,ALU2 +S 1700,8600,3300,8600,200,5nonymous_,RIGHT,NTRANS +S 1700,5000,3300,5000,200,6nonymous_,RIGHT,NTRANS +S 1900,8000,3100,8000,600,7nonymous_,RIGHT,NDIF +S 1900,3200,3100,3200,600,8nonymous_,RIGHT,NDIF +S 1900,2000,3100,2000,600,9nonymous_,RIGHT,NDIF +S 1900,9200,3100,9200,600,10onymous_,RIGHT,NDIF +S 1900,6800,3100,6800,600,11onymous_,RIGHT,NDIF +S 1900,5600,3100,5600,600,12onymous_,RIGHT,NDIF +S 1900,4400,3100,4400,600,13onymous_,RIGHT,NDIF +S 1000,3800,1400,3800,200,34onymous_,RIGHT,POLY +S 4850,2000,6150,2000,600,bit0,RIGHT,CALU2 +S 4850,4000,6150,4000,600,nbit0,RIGHT,CALU2 +S 4850,6000,6150,6000,600,bit1,RIGHT,CALU2 +S 4850,8000,6150,8000,600,nbit1,RIGHT,CALU2 +S 6000,-150,6000,10150,2400,18onymous_,UP,ALU3 +S 2000,-150,2000,10150,2400,19onymous_,UP,ALU3 +S 2100,8000,4900,8000,300,20onymous_,RIGHT,ALU1 +S 4100,2000,4900,2000,300,21onymous_,RIGHT,ALU1 +S 850,6800,4150,6800,600,22onymous_,RIGHT,ALU2 +S 850,3200,4150,3200,600,23onymous_,RIGHT,ALU2 +S 850,4400,4150,4400,600,24onymous_,RIGHT,ALU2 +S 850,8000,4150,8000,600,25onymous_,RIGHT,ALU2 +S 2100,3200,3900,3200,300,26onymous_,RIGHT,ALU1 +S 1000,3300,1000,7900,300,27onymous_,UP,ALU1 +S 1000,2600,1400,2600,200,28onymous_,RIGHT,POLY +S 1000,8600,1400,8600,200,29onymous_,RIGHT,POLY +S 1000,7400,1400,7400,200,30onymous_,RIGHT,POLY +S 1000,6200,1400,6200,200,31onymous_,RIGHT,POLY +S 1000,5000,1400,5000,200,32onymous_,RIGHT,POLY +S 1000,2600,1000,8600,600,33onymous_,UP,POLY +S 2100,6800,4900,6800,300,35onymous_,RIGHT,ALU1 +S 2100,4400,4900,4400,300,36onymous_,RIGHT,ALU1 +S 4000,2100,4000,3100,300,37onymous_,UP,ALU1 +S 5000,6100,5000,6700,300,38onymous_,UP,ALU1 +S 5000,4100,5000,4300,300,39onymous_,UP,ALU1 +S 1050,5000,3950,5000,6300,40onymous_,RIGHT,TALU2 +S 4000,2850,4000,8150,400,prech,UP,CALU3 +V 3000,600,CONT_BODY_P,41onymous_ +V 1000,600,CONT_BODY_P,42onymous_ +V 2000,600,CONT_BODY_P,43onymous_ +V 5000,4000,CONT_VIA,44onymous_ +V 5000,8000,CONT_VIA,45onymous_ +V 5000,6000,CONT_VIA,46onymous_ +V 5000,2000,CONT_VIA,47onymous_ +V 3000,2000,CONT_VIA2,48onymous_ +V 4000,8000,CONT_VIA2,49onymous_ +V 4000,6800,CONT_VIA2,50onymous_ +V 4000,4400,CONT_VIA2,51onymous_ +V 4000,3200,CONT_VIA2,52onymous_ +V 3000,5600,CONT_VIA2,53onymous_ +V 2000,5600,CONT_VIA2,54onymous_ +V 2000,2000,CONT_VIA2,55onymous_ +V 3000,5600,CONT_VIA,56onymous_ +V 2000,5600,CONT_VIA,57onymous_ +V 2000,2000,CONT_VIA,58onymous_ +V 3000,2000,CONT_VIA,59onymous_ +V 1000,8000,CONT_VIA,60onymous_ +V 1000,6800,CONT_VIA,61onymous_ +V 1000,4400,CONT_VIA,62onymous_ +V 1000,3200,CONT_VIA,63onymous_ +V 1000,6800,CONT_POLY,64onymous_ +V 1000,8000,CONT_POLY,65onymous_ +V 1000,3200,CONT_POLY,66onymous_ +V 2000,9200,CONT_DIF_N,73onymous_ +V 3000,5600,CONT_DIF_N,72onymous_ +V 2000,6800,CONT_DIF_N,71onymous_ +V 3000,6800,CONT_DIF_N,70onymous_ +V 3000,4400,CONT_DIF_N,69onymous_ +V 3000,3200,CONT_DIF_N,68onymous_ +V 1000,4400,CONT_POLY,67onymous_ +V 2000,5600,CONT_DIF_N,81onymous_ +V 3000,2000,CONT_DIF_N,80onymous_ +V 3000,9200,CONT_DIF_N,79onymous_ +V 2000,4400,CONT_DIF_N,78onymous_ +V 2000,2000,CONT_DIF_N,77onymous_ +V 2000,3200,CONT_DIF_N,76onymous_ +V 3000,8000,CONT_DIF_N,75onymous_ +V 2000,8000,CONT_DIF_N,74onymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_prech_data.vbe b/pdks/symbolic/nramlib/cells/ram_prech_data.vbe new file mode 100644 index 000000000..731520a1e --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_prech_data.vbe @@ -0,0 +1,20 @@ +ENTITY ram_prech_data IS +PORT ( + prech : in BIT; + bit0 : in BIT; + nbit0 : in BIT; + bit1 : in BIT; + nbit1 : in BIT; + vdd : in BIT; + vss : in BIT +); +END ram_prech_data; + +ARCHITECTURE VBE OF ram_prech_data IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_prech_data" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_prech_dec0.ap b/pdks/symbolic/nramlib/cells/ram_prech_dec0.ap new file mode 100644 index 000000000..145d1cd60 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_prech_dec0.ap @@ -0,0 +1,9 @@ +V ALLIANCE : 6 +H ram_prech_dec0,P,23/4/2016,100 +A 0,0,6000,10000 +S 100,9400,5900,9400,1200,vdd,RIGHT,CALU1 +S 100,600,5900,600,1200,vss,RIGHT,CALU1 +S 6000,-150,6000,10150,2400,0nonymous_,UP,ALU3 +S 2000,-150,2000,10150,2400,1nonymous_,UP,ALU3 +S -600,7800,6600,7800,6000,2nonymous_,RIGHT,NWELL +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_prech_dec0.vbe b/pdks/symbolic/nramlib/cells/ram_prech_dec0.vbe new file mode 100644 index 000000000..ac0f71c31 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_prech_dec0.vbe @@ -0,0 +1,15 @@ +ENTITY ram_prech_dec0 IS +PORT ( + vdd : in BIT; + vss : in BIT +); +END ram_prech_dec0; + +ARCHITECTURE VBE OF ram_prech_dec0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_prech_dec0" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_sense_buf0.ap b/pdks/symbolic/nramlib/cells/ram_sense_buf0.ap new file mode 100644 index 000000000..5acefbd5d --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_buf0.ap @@ -0,0 +1,343 @@ +V ALLIANCE : 6 +H ram_sense_buf0,P,23/4/2016,100 +A 0,0,34000,10000 +S 100,600,33900,600,1200,vss,RIGHT,CALU1 +S 100,9400,33900,9400,1200,vdd,RIGHT,CALU1 +S 9000,3100,9000,3900,300,9nonymous_,UP,ALU1 +S 5850,5000,10350,5000,600,10onymous_,RIGHT,ALU2 +S 7200,4000,9600,4000,600,11onymous_,RIGHT,POLY +S 2850,4000,9150,4000,600,12onymous_,RIGHT,ALU2 +S 28000,3100,28000,3900,300,13onymous_,UP,ALU1 +S 26850,4000,28150,4000,600,14onymous_,RIGHT,ALU2 +S 21000,4100,21000,4900,300,15onymous_,UP,ALU1 +S 20850,5000,22150,5000,600,16onymous_,RIGHT,ALU2 +S 14000,5100,14000,5900,300,17onymous_,UP,ALU1 +S 7900,5000,10100,5000,300,0nonymous_,RIGHT,ALU1 +S 4050,5000,29950,5000,300,1nonymous_,RIGHT,TALU2 +S 26850,5000,29550,5000,600,2nonymous_,RIGHT,ALU2 +S 22050,4000,24750,4000,600,3nonymous_,RIGHT,ALU2 +S 17250,5000,19950,5000,600,4nonymous_,RIGHT,ALU2 +S 12450,4000,15150,4000,600,5nonymous_,RIGHT,ALU2 +S 3850,5000,5150,5000,600,6nonymous_,RIGHT,ALU2 +S 9000,6100,9000,8900,300,7nonymous_,UP,ALU1 +S 3600,5000,6000,5000,600,8nonymous_,RIGHT,POLY +S 27000,5700,27000,9300,600,38onymous_,UP,PDIF +S 23400,5700,23400,9300,600,37onymous_,UP,PDIF +S 29400,5700,29400,9300,600,36onymous_,UP,PDIF +S 28200,5700,28200,9300,600,35onymous_,UP,PDIF +S 25800,5700,25800,9300,600,34onymous_,UP,PDIF +S 9600,5500,9600,9500,200,33onymous_,UP,PTRANS +S 4200,5700,4200,9300,600,32onymous_,UP,PDIF +S 3600,5500,3600,9500,200,31onymous_,UP,PTRANS +S 6000,5500,6000,9500,200,30onymous_,UP,PTRANS +S 5400,5700,5400,9300,600,29onymous_,UP,PDIF +S 13800,7100,13800,8900,300,18onymous_,UP,ALU1 +S 12850,5000,14150,5000,600,19onymous_,RIGHT,ALU2 +S 3050,4000,27950,4000,300,20onymous_,RIGHT,TALU2 +S -600,7800,34600,7800,6000,21onymous_,RIGHT,NWELL +S 1800,5680,1800,9320,600,22onymous_,UP,NTIE +S 7200,5500,7200,9500,200,23onymous_,UP,PTRANS +S 3000,5700,3000,9300,600,24onymous_,UP,PDIF +S 11400,5680,11400,9320,600,25onymous_,UP,NTIE +S 8400,5500,8400,9500,200,26onymous_,UP,PTRANS +S 7800,5700,7800,9300,600,27onymous_,UP,PDIF +S 4800,5500,4800,9500,200,28onymous_,UP,PTRANS +S 10200,5700,10200,9300,600,39onymous_,UP,PDIF +S 9000,5700,9000,9300,600,40onymous_,UP,PDIF +S 6600,5700,6600,9300,600,41onymous_,UP,PDIF +S 26400,5500,26400,9500,200,42onymous_,UP,PTRANS +S 28800,5500,28800,9500,200,43onymous_,UP,PTRANS +S 22800,5500,22800,9500,200,44onymous_,UP,PTRANS +S 25200,5500,25200,9500,200,45onymous_,UP,PTRANS +S 24600,5700,24600,9300,600,46onymous_,UP,PDIF +S 24000,5500,24000,9500,200,47onymous_,UP,PTRANS +S 22200,5700,22200,9300,600,48onymous_,UP,PDIF +S 27600,5500,27600,9500,200,49onymous_,UP,PTRANS +S 19800,5700,19800,9300,600,50onymous_,UP,PDIF +S 18600,5700,18600,9300,600,51onymous_,UP,PDIF +S 16200,5700,16200,9300,600,52onymous_,UP,PDIF +S 18000,5500,18000,9500,200,53onymous_,UP,PTRANS +S 17400,5700,17400,9300,600,54onymous_,UP,PDIF +S 21000,5680,21000,9320,600,55onymous_,UP,NTIE +S 31400,5680,31400,9320,600,56onymous_,UP,NTIE +S 19200,5500,19200,9500,200,57onymous_,UP,PTRANS +S 16800,5500,16800,9500,200,58onymous_,UP,PTRANS +S 12600,5700,12600,9300,600,59onymous_,UP,PDIF +S 14400,5500,14400,9500,200,60onymous_,UP,PTRANS +S 15000,5700,15000,9300,600,61onymous_,UP,PDIF +S 15600,5500,15600,9500,200,62onymous_,UP,PTRANS +S 13200,5500,13200,9500,200,63onymous_,UP,PTRANS +S 13800,5700,13800,9300,600,64onymous_,UP,PDIF +S 4800,500,4800,2500,200,65onymous_,UP,NTRANS +S 6000,500,6000,2500,200,66onymous_,UP,NTRANS +S 22800,500,22800,2500,200,68onymous_,UP,NTRANS +S 27600,500,27600,2500,200,67onymous_,UP,NTRANS +S 25200,500,25200,2500,200,69onymous_,UP,NTRANS +S 24000,500,24000,2500,200,70onymous_,UP,NTRANS +S 3600,500,3600,2500,200,71onymous_,UP,NTRANS +S 8400,500,8400,2500,200,72onymous_,UP,NTRANS +S 7200,500,7200,2500,200,73onymous_,UP,NTRANS +S 9600,500,9600,2500,200,74onymous_,UP,NTRANS +S 16800,500,16800,2500,200,75onymous_,UP,NTRANS +S 19200,500,19200,2500,200,76onymous_,UP,NTRANS +S 14400,500,14400,2500,200,77onymous_,UP,NTRANS +S 15600,500,15600,2500,200,78onymous_,UP,NTRANS +S 13200,500,13200,2500,200,79onymous_,UP,NTRANS +S 18000,500,18000,2500,200,80onymous_,UP,NTRANS +S 28800,500,28800,2500,200,81onymous_,UP,NTRANS +S 26400,500,26400,2500,200,82onymous_,UP,NTRANS +S 7800,700,7800,2300,600,83onymous_,UP,NDIF +S 6600,700,6600,2300,600,84onymous_,UP,NDIF +S 4200,700,4200,2300,600,85onymous_,UP,NDIF +S 5400,700,5400,2300,600,86onymous_,UP,NDIF +S 3000,700,3000,2300,600,87onymous_,UP,NDIF +S 9000,700,9000,2300,600,88onymous_,UP,NDIF +S 10200,700,10200,2300,600,89onymous_,UP,NDIF +S 25800,700,25800,2300,600,90onymous_,UP,NDIF +S 22200,700,22200,2300,600,91onymous_,UP,NDIF +S 24600,700,24600,2300,600,92onymous_,UP,NDIF +S 29400,700,29400,2300,600,93onymous_,UP,NDIF +S 27000,700,27000,2300,600,94onymous_,UP,NDIF +S 28200,700,28200,2300,600,95onymous_,UP,NDIF +S 23400,700,23400,2300,600,96onymous_,UP,NDIF +S 15000,700,15000,2300,600,97onymous_,UP,NDIF +S 12600,700,12600,2300,600,98onymous_,UP,NDIF +S 18600,700,18600,2300,600,99onymous_,UP,NDIF +S 16200,700,16200,2300,600,100nymous_,UP,NDIF +S 13800,700,13800,2300,600,101nymous_,UP,NDIF +S 17400,700,17400,2300,600,102nymous_,UP,NDIF +S 19800,700,19800,2300,600,103nymous_,UP,NDIF +S 1800,680,1800,3320,600,104nymous_,UP,PTIE +S 21000,680,21000,3320,600,105nymous_,UP,PTIE +S 31400,680,31400,3320,600,106nymous_,UP,PTIE +S 11400,680,11400,3320,600,107nymous_,UP,PTIE +S 27600,2800,27600,5200,200,108nymous_,UP,POLY +S 8400,2800,8400,5200,200,109nymous_,UP,POLY +S 7200,2800,7200,5200,200,110nymous_,UP,POLY +S 16200,4000,19200,4000,600,122nymous_,RIGHT,POLY +S 18000,2800,18000,5200,200,121nymous_,UP,POLY +S 15600,2800,15600,5200,200,120nymous_,UP,POLY +S 26400,2800,26400,5200,200,119nymous_,UP,POLY +S 28800,2800,28800,5200,200,118nymous_,UP,POLY +S 22800,2800,22800,5200,200,117nymous_,UP,POLY +S 24000,2800,24000,5200,200,116nymous_,UP,POLY +S 25200,2800,25200,5200,200,115nymous_,UP,POLY +S 6000,2800,6000,5200,200,114nymous_,UP,POLY +S 4800,2800,4800,5200,200,113nymous_,UP,POLY +S 3600,2800,3600,5200,200,112nymous_,UP,POLY +S 9600,2800,9600,5200,200,111nymous_,UP,POLY +S 4000,2100,4000,7900,300,ad0,UP,CALU1 +S 14000,4850,14000,5150,400,nsense,UP,CALU3 +S 21000,4850,21000,5150,400,nckx,UP,CALU3 +S 28000,3850,28000,4150,400,nwrite,UP,CALU3 +S 6000,4850,6000,5150,400,ad0x,UP,CALU3 +S 3000,3850,3000,4150,400,nad0x,UP,CALU3 +S 15000,3850,15000,4150,400,sensex,UP,CALU3 +S 18000,4850,18000,5150,400,nsensex,UP,CALU3 +S 23000,3850,23000,4150,400,prech,UP,CALU3 +S 27000,4850,27000,5150,400,writex,UP,CALU3 +S 21000,5000,25200,5000,600,123nymous_,RIGHT,POLY +S 26400,4000,28800,4000,600,124nymous_,RIGHT,POLY +S 16800,2800,16800,5200,200,125nymous_,UP,POLY +S 19200,2800,19200,5200,200,126nymous_,UP,POLY +S 13200,2800,13200,5200,200,127nymous_,UP,POLY +S 14400,2800,14400,5200,200,128nymous_,UP,POLY +S 1800,1100,1800,2900,300,129nymous_,UP,ALU1 +S 1800,6100,1800,8900,300,130nymous_,UP,ALU1 +S 21000,1100,21000,2900,300,131nymous_,UP,ALU1 +S 21000,6100,21000,8900,300,132nymous_,UP,ALU1 +S 11400,6100,11400,8900,300,133nymous_,UP,ALU1 +S 11400,1100,11400,2900,300,134nymous_,UP,ALU1 +S 6600,6100,6600,8900,300,135nymous_,UP,ALU1 +S 3000,2100,3000,7900,300,136nymous_,UP,ALU1 +S 5400,2100,5400,7900,300,137nymous_,UP,ALU1 +S 31400,6100,31400,8900,300,138nymous_,UP,ALU1 +S 31400,1100,31400,2900,300,139nymous_,UP,ALU1 +S 28200,6100,28200,8900,300,140nymous_,UP,ALU1 +S 9000,1100,9000,1900,300,141nymous_,UP,ALU1 +S 10200,2100,10200,7900,300,142nymous_,UP,ALU1 +S 7800,2100,7800,7900,300,143nymous_,UP,ALU1 +S 6600,1100,6600,1900,300,144nymous_,UP,ALU1 +S 23400,1100,23400,1900,300,145nymous_,UP,ALU1 +S 25800,6100,25800,8900,300,146nymous_,UP,ALU1 +S 25800,1100,25800,1900,300,147nymous_,UP,ALU1 +S 23400,6100,23400,8900,300,148nymous_,UP,ALU1 +S 24600,2100,24600,7900,300,149nymous_,UP,ALU1 +S 27000,2100,27000,7900,300,150nymous_,UP,ALU1 +S 29400,2100,29400,7900,300,151nymous_,UP,ALU1 +S 27100,5000,29300,5000,300,152nymous_,RIGHT,ALU1 +S 13800,1100,13800,1900,300,153nymous_,UP,ALU1 +S 18600,6100,18600,8900,300,154nymous_,UP,ALU1 +S 12700,4000,16300,4000,300,155nymous_,RIGHT,ALU1 +S 17500,5000,19700,5000,300,156nymous_,RIGHT,ALU1 +S 22300,4000,24500,4000,300,157nymous_,RIGHT,ALU1 +S 28200,1100,28200,1900,300,158nymous_,UP,ALU1 +S 22200,2100,22200,7900,300,159nymous_,UP,ALU1 +S 12600,2100,12600,7900,300,160nymous_,UP,ALU1 +S 18600,1100,18600,1900,300,161nymous_,UP,ALU1 +S 19800,2100,19800,7900,300,162nymous_,UP,ALU1 +S 17400,2100,17400,7900,300,163nymous_,UP,ALU1 +S 15000,2100,15000,7900,300,164nymous_,UP,ALU1 +S 16200,1100,16200,1900,300,165nymous_,UP,ALU1 +S 16200,6100,16200,8900,300,166nymous_,UP,ALU1 +S 13200,5000,15600,5000,600,167nymous_,RIGHT,POLY +S 0,-150,0,10150,2400,168nymous_,UP,ALU3 +S 25000,-150,25000,10150,2400,169nymous_,UP,ALU3 +V 29400,5000,CONT_VIA,170nymous_ +V 24600,4000,CONT_VIA,171nymous_ +V 22200,4000,CONT_VIA,172nymous_ +V 17400,5000,CONT_VIA,173nymous_ +V 19800,5000,CONT_VIA,174nymous_ +V 12600,4000,CONT_VIA,175nymous_ +V 9000,4000,CONT_VIA,176nymous_ +V 9000,4000,CONT_POLY,177nymous_ +V 9000,6000,CONT_DIF_P,178nymous_ +V 9000,7000,CONT_DIF_P,179nymous_ +V 5400,4000,CONT_VIA,180nymous_ +V 4000,5000,CONT_POLY,181nymous_ +V 4000,5000,CONT_VIA,182nymous_ +V 1800,6000,CONT_BODY_N,183nymous_ +V 1800,7000,CONT_BODY_N,184nymous_ +V 1800,8000,CONT_BODY_N,185nymous_ +V 1800,9000,CONT_BODY_N,186nymous_ +V 22200,8000,CONT_DIF_P,187nymous_ +V 23400,8000,CONT_DIF_P,188nymous_ +V 24600,8000,CONT_DIF_P,189nymous_ +V 29400,8000,CONT_DIF_P,190nymous_ +V 28200,8000,CONT_DIF_P,191nymous_ +V 27000,8000,CONT_DIF_P,192nymous_ +V 17400,8000,CONT_DIF_P,193nymous_ +V 18600,8000,CONT_DIF_P,194nymous_ +V 19800,8000,CONT_DIF_P,195nymous_ +V 5400,7000,CONT_DIF_P,196nymous_ +V 5400,6000,CONT_DIF_P,197nymous_ +V 11400,9000,CONT_BODY_N,198nymous_ +V 11400,8000,CONT_BODY_N,199nymous_ +V 11400,7000,CONT_BODY_N,200nymous_ +V 11400,6000,CONT_BODY_N,201nymous_ +V 4200,9000,CONT_DIF_P,202nymous_ +V 6600,6000,CONT_DIF_P,203nymous_ +V 7800,8000,CONT_DIF_P,204nymous_ +V 7800,7000,CONT_DIF_P,205nymous_ +V 7800,6000,CONT_DIF_P,206nymous_ +V 6600,8000,CONT_DIF_P,207nymous_ +V 9000,8000,CONT_DIF_P,208nymous_ +V 3000,6000,CONT_DIF_P,209nymous_ +V 3000,7000,CONT_DIF_P,210nymous_ +V 10200,6000,CONT_DIF_P,211nymous_ +V 10200,7000,CONT_DIF_P,212nymous_ +V 5400,8000,CONT_DIF_P,213nymous_ +V 3000,8000,CONT_DIF_P,214nymous_ +V 28200,7000,CONT_DIF_P,215nymous_ +V 23400,9000,CONT_DIF_P,216nymous_ +V 10200,8000,CONT_DIF_P,217nymous_ +V 6600,9000,CONT_DIF_P,218nymous_ +V 6600,7000,CONT_DIF_P,219nymous_ +V 9000,9000,CONT_DIF_P,220nymous_ +V 23400,6000,CONT_DIF_P,221nymous_ +V 22200,7000,CONT_DIF_P,222nymous_ +V 22200,6000,CONT_DIF_P,223nymous_ +V 28200,6000,CONT_DIF_P,224nymous_ +V 28200,9000,CONT_DIF_P,225nymous_ +V 25800,8000,CONT_DIF_P,226nymous_ +V 29400,7000,CONT_DIF_P,227nymous_ +V 29400,6000,CONT_DIF_P,228nymous_ +V 27000,6000,CONT_DIF_P,229nymous_ +V 25800,7000,CONT_DIF_P,230nymous_ +V 25800,9000,CONT_DIF_P,231nymous_ +V 25800,6000,CONT_DIF_P,232nymous_ +V 23400,7000,CONT_DIF_P,233nymous_ +V 31400,8000,CONT_BODY_N,234nymous_ +V 31400,7000,CONT_BODY_N,235nymous_ +V 31400,6000,CONT_BODY_N,236nymous_ +V 24600,6000,CONT_DIF_P,237nymous_ +V 27000,7000,CONT_DIF_P,238nymous_ +V 24600,7000,CONT_DIF_P,239nymous_ +V 18600,7000,CONT_DIF_P,240nymous_ +V 18600,9000,CONT_DIF_P,241nymous_ +V 21000,7000,CONT_BODY_N,242nymous_ +V 21000,6000,CONT_BODY_N,243nymous_ +V 21000,9000,CONT_BODY_N,244nymous_ +V 21000,8000,CONT_BODY_N,245nymous_ +V 31400,9000,CONT_BODY_N,246nymous_ +V 12600,6000,CONT_DIF_P,247nymous_ +V 12600,7000,CONT_DIF_P,248nymous_ +V 15000,8000,CONT_DIF_P,249nymous_ +V 12600,8000,CONT_DIF_P,250nymous_ +V 13800,7000,CONT_DIF_P,251nymous_ +V 13800,9000,CONT_DIF_P,252nymous_ +V 15000,6000,CONT_DIF_P,253nymous_ +V 17400,6000,CONT_DIF_P,254nymous_ +V 19800,6000,CONT_DIF_P,255nymous_ +V 19800,7000,CONT_DIF_P,256nymous_ +V 16200,6000,CONT_DIF_P,257nymous_ +V 16200,9000,CONT_DIF_P,258nymous_ +V 16200,7000,CONT_DIF_P,259nymous_ +V 18600,6000,CONT_DIF_P,260nymous_ +V 16200,8000,CONT_DIF_P,261nymous_ +V 15000,7000,CONT_DIF_P,262nymous_ +V 17400,7000,CONT_DIF_P,263nymous_ +V 13800,8000,CONT_DIF_P,264nymous_ +V 18600,2000,CONT_DIF_N,265nymous_ +V 19800,2000,CONT_DIF_N,266nymous_ +V 22200,2000,CONT_DIF_N,267nymous_ +V 23400,2000,CONT_DIF_N,268nymous_ +V 24600,2000,CONT_DIF_N,269nymous_ +V 27000,2000,CONT_DIF_N,270nymous_ +V 28200,2000,CONT_DIF_N,271nymous_ +V 29400,2000,CONT_DIF_N,272nymous_ +V 9000,2000,CONT_DIF_N,273nymous_ +V 9000,1000,CONT_DIF_N,274nymous_ +V 5400,2000,CONT_DIF_N,275nymous_ +V 3000,2000,CONT_DIF_N,276nymous_ +V 6600,1000,CONT_DIF_N,277nymous_ +V 6600,2000,CONT_DIF_N,278nymous_ +V 17400,2000,CONT_DIF_N,279nymous_ +V 25800,2000,CONT_DIF_N,280nymous_ +V 23400,1000,CONT_DIF_N,281nymous_ +V 4200,1000,CONT_DIF_N,282nymous_ +V 10200,2000,CONT_DIF_N,283nymous_ +V 7800,2000,CONT_DIF_N,284nymous_ +V 13800,1000,CONT_DIF_N,285nymous_ +V 16200,2000,CONT_DIF_N,286nymous_ +V 25800,1000,CONT_DIF_N,287nymous_ +V 28200,1000,CONT_DIF_N,288nymous_ +V 18600,1000,CONT_DIF_N,289nymous_ +V 15000,2000,CONT_DIF_N,290nymous_ +V 16200,1000,CONT_DIF_N,291nymous_ +V 13800,2000,CONT_DIF_N,292nymous_ +V 12600,2000,CONT_DIF_N,293nymous_ +V 1800,1000,CONT_BODY_P,294nymous_ +V 1800,3000,CONT_BODY_P,295nymous_ +V 1800,2000,CONT_BODY_P,296nymous_ +V 31400,1000,CONT_BODY_P,297nymous_ +V 11400,2000,CONT_BODY_P,298nymous_ +V 11400,3000,CONT_BODY_P,299nymous_ +V 11400,1000,CONT_BODY_P,300nymous_ +V 21000,2000,CONT_BODY_P,301nymous_ +V 21000,3000,CONT_BODY_P,302nymous_ +V 21000,1000,CONT_BODY_P,303nymous_ +V 28000,4000,CONT_POLY,308nymous_ +V 21000,5000,CONT_POLY,307nymous_ +V 16400,4000,CONT_POLY,306nymous_ +V 31400,3000,CONT_BODY_P,305nymous_ +V 31400,2000,CONT_BODY_P,304nymous_ +V 27000,5000,CONT_VIA,309nymous_ +V 15000,4000,CONT_VIA,310nymous_ +V 3000,4000,CONT_VIA,311nymous_ +V 28000,4000,CONT_VIA,312nymous_ +V 21000,5000,CONT_VIA,313nymous_ +V 27000,5000,CONT_VIA2,314nymous_ +V 15000,4000,CONT_VIA2,315nymous_ +V 18000,5000,CONT_VIA2,316nymous_ +V 23000,4000,CONT_VIA2,317nymous_ +V 3000,4000,CONT_VIA2,318nymous_ +V 28000,4000,CONT_VIA2,319nymous_ +V 21000,5000,CONT_VIA2,320nymous_ +V 10200,5000,CONT_VIA,321nymous_ +V 14000,5000,CONT_POLY,326nymous_ +V 14000,5000,CONT_VIA,325nymous_ +V 14000,5000,CONT_VIA2,324nymous_ +V 6000,5000,CONT_VIA2,323nymous_ +V 7800,5000,CONT_VIA,322nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_sense_buf0.vbe b/pdks/symbolic/nramlib/cells/ram_sense_buf0.vbe new file mode 100644 index 000000000..b72d5badc --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_buf0.vbe @@ -0,0 +1,25 @@ +ENTITY ram_sense_buf0 IS +PORT ( + ad0 : in BIT; + nsense : in BIT; + nckx : in BIT; + nwrite : in BIT; + ad0x : out BIT; + nad0x : out BIT; + sensex : out BIT; + nsensex : out BIT; + prech : out BIT; + writex : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_buf0; + +ARCHITECTURE VBE OF ram_sense_buf0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_buf0" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_sense_buf1.ap b/pdks/symbolic/nramlib/cells/ram_sense_buf1.ap new file mode 100644 index 000000000..6121f3615 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_buf1.ap @@ -0,0 +1,376 @@ +V ALLIANCE : 6 +H ram_sense_buf1,P,23/4/2016,100 +A 0,0,34000,10000 +S 17080,600,20120,600,600,1nonymous_,RIGHT,PTIE +S 100,9400,33900,9400,1200,vdd,RIGHT,CALU1 +S 100,600,33900,600,1200,vss,RIGHT,CALU1 +S 17080,9400,20120,9400,600,0nonymous_,RIGHT,NTIE +S 19600,4100,19600,4900,300,11onymous_,UP,ALU1 +S 19200,3800,19200,6200,200,12onymous_,UP,POLY +S 18700,3000,19700,3000,300,13onymous_,RIGHT,ALU1 +S 18000,6500,18000,8500,200,14onymous_,UP,PTRANS +S 18600,6700,18600,8300,600,15onymous_,UP,PDIF +S 19200,6500,19200,8500,200,16onymous_,UP,PTRANS +S 17400,8100,17400,8900,300,17onymous_,UP,ALU1 +S 17400,700,17400,1900,300,2nonymous_,UP,ALU1 +S 17400,1700,17400,3300,600,3nonymous_,UP,NDIF +S 19800,6700,19800,8300,600,4nonymous_,UP,PDIF +S 17400,6700,17400,8300,600,5nonymous_,UP,PDIF +S 17850,6000,19150,6000,600,6nonymous_,RIGHT,ALU2 +S 22600,4100,22600,4900,300,7nonymous_,UP,ALU1 +S 21800,3000,22400,3000,600,8nonymous_,RIGHT,POLY +S 22300,3000,23500,3000,300,9nonymous_,RIGHT,ALU1 +S 19200,5000,19800,5000,600,10onymous_,RIGHT,POLY +S 22400,1100,22400,1900,300,36onymous_,UP,ALU1 +S 22400,6100,22400,8900,300,35onymous_,UP,ALU1 +S 23600,2100,23600,7900,300,34onymous_,UP,ALU1 +S 23000,2800,23000,5200,200,33onymous_,UP,POLY +S 21800,2800,21800,5200,200,32onymous_,UP,POLY +S 22400,700,22400,2300,600,31onymous_,UP,NDIF +S 11850,5000,31150,5000,600,nck,RIGHT,CALU2 +S 850,6000,12150,6000,600,selramx,RIGHT,CALU2 +S 19800,7100,19800,8900,300,18onymous_,UP,ALU1 +S 14050,6000,21950,6000,300,19onymous_,RIGHT,TALU2 +S 20850,6000,22150,6000,600,20onymous_,RIGHT,ALU2 +S 22400,5000,23000,5000,600,21onymous_,RIGHT,POLY +S 23000,5500,23000,9500,200,22onymous_,UP,PTRANS +S 21800,5500,21800,9500,200,23onymous_,UP,PTRANS +S 22400,5700,22400,9300,600,24onymous_,UP,PDIF +S 21200,5700,21200,9300,600,25onymous_,UP,PDIF +S 23600,5700,23600,9300,600,26onymous_,UP,PDIF +S 21800,500,21800,2500,200,27onymous_,UP,NTRANS +S 23000,500,23000,2500,200,28onymous_,UP,NTRANS +S 21200,700,21200,2300,600,29onymous_,UP,NDIF +S 23600,700,23600,2300,600,30onymous_,UP,NDIF +S 21200,2100,21200,7900,300,37onymous_,UP,ALU1 +S 19200,1500,19200,3500,200,38onymous_,UP,NTRANS +S 19800,1700,19800,3300,600,39onymous_,UP,NDIF +S 13850,6000,15150,6000,600,40onymous_,RIGHT,ALU2 +S 8600,5680,8600,9320,600,41onymous_,UP,NTIE +S 8600,680,8600,2320,600,42onymous_,UP,PTIE +S 8600,6100,8600,8900,300,43onymous_,UP,ALU1 +S 8600,6100,8600,8900,300,44onymous_,UP,ALU1 +S 8600,1100,8600,1700,300,45onymous_,UP,ALU1 +S 8600,1100,8600,1700,300,46onymous_,UP,ALU1 +S 6400,5000,10000,5000,600,47onymous_,RIGHT,POLY +S -600,7800,34600,7800,6000,48onymous_,RIGHT,NWELL +S 33400,680,33400,2320,600,49onymous_,UP,PTIE +S 33400,5680,33400,9320,600,50onymous_,UP,NTIE +S 33400,6100,33400,8900,300,51onymous_,UP,ALU1 +S 33400,1100,33400,1700,300,52onymous_,UP,ALU1 +S 33400,1100,33400,1700,300,53onymous_,UP,ALU1 +S 33400,6100,33400,8900,300,54onymous_,UP,ALU1 +S 25400,4000,32000,4000,600,55onymous_,RIGHT,POLY +S 25400,5500,25400,9500,200,56onymous_,UP,PTRANS +S 32000,5700,32000,9300,600,57onymous_,UP,PDIF +S 26600,5500,26600,9500,200,58onymous_,UP,PTRANS +S 26000,5700,26000,9300,600,59onymous_,UP,PDIF +S 24800,5700,24800,9300,600,60onymous_,UP,PDIF +S 27200,5700,27200,9300,600,61onymous_,UP,PDIF +S 28400,5700,28400,9300,600,62onymous_,UP,PDIF +S 27800,5500,27800,9500,200,63onymous_,UP,PTRANS +S 29600,5700,29600,9300,600,64onymous_,UP,PDIF +S 30800,5700,30800,9300,600,65onymous_,UP,PDIF +S 30200,5500,30200,9500,200,66onymous_,UP,PTRANS +S 30200,500,30200,2500,200,70onymous_,UP,NTRANS +S 31400,500,31400,2500,200,69onymous_,UP,NTRANS +S 31400,5500,31400,9500,200,68onymous_,UP,PTRANS +S 29000,5500,29000,9500,200,67onymous_,UP,PTRANS +S 25400,500,25400,2500,200,71onymous_,UP,NTRANS +S 26600,500,26600,2500,200,72onymous_,UP,NTRANS +S 29000,500,29000,2500,200,73onymous_,UP,NTRANS +S 27800,500,27800,2500,200,74onymous_,UP,NTRANS +S 24800,700,24800,2300,600,75onymous_,UP,NDIF +S 26000,700,26000,2300,600,76onymous_,UP,NDIF +S 32000,700,32000,2300,600,77onymous_,UP,NDIF +S 29600,700,29600,2300,600,78onymous_,UP,NDIF +S 30800,700,30800,2300,600,79onymous_,UP,NDIF +S 28400,700,28400,2300,600,80onymous_,UP,NDIF +S 27200,700,27200,2300,600,81onymous_,UP,NDIF +S 29000,2800,29000,5200,200,82onymous_,UP,POLY +S 27800,2800,27800,5200,200,83onymous_,UP,POLY +S 25400,2800,25400,5200,200,84onymous_,UP,POLY +S 26600,2800,26600,5200,200,85onymous_,UP,POLY +S 31400,2800,31400,5200,200,86onymous_,UP,POLY +S 30200,2800,30200,5200,200,87onymous_,UP,POLY +S 27200,6100,27200,8900,300,88onymous_,UP,ALU1 +S 27200,1100,27200,1900,300,89onymous_,UP,ALU1 +S 24800,6100,24800,8900,300,90onymous_,UP,ALU1 +S 24800,6100,24800,8900,300,91onymous_,UP,ALU1 +S 24800,1100,24800,1900,300,92onymous_,UP,ALU1 +S 26000,2100,26000,7900,300,93onymous_,UP,ALU1 +S 24800,1100,24800,1900,300,94onymous_,UP,ALU1 +S 29600,6100,29600,8900,300,95onymous_,UP,ALU1 +S 30800,2100,30800,7900,300,96onymous_,UP,ALU1 +S 28400,2100,28400,7900,300,97onymous_,UP,ALU1 +S 29600,6100,29600,8900,300,98onymous_,UP,ALU1 +S 29600,1100,29600,1900,300,99onymous_,UP,ALU1 +S 27200,1100,27200,1900,300,100nymous_,UP,ALU1 +S 27200,6100,27200,8900,300,101nymous_,UP,ALU1 +S 29600,1100,29600,1900,300,102nymous_,UP,ALU1 +S 1000,1100,1000,1900,300,103nymous_,UP,ALU1 +S 7000,2100,7000,7900,300,104nymous_,UP,ALU1 +S 3400,6100,3400,8900,300,105nymous_,UP,ALU1 +S 5800,1100,5800,1900,300,106nymous_,UP,ALU1 +S 3400,1100,3400,1900,300,107nymous_,UP,ALU1 +S 1000,6100,1000,8900,300,108nymous_,UP,ALU1 +S 2200,2100,2200,7900,300,109nymous_,UP,ALU1 +S 4600,2100,4600,7900,300,110nymous_,UP,ALU1 +S 5700,3000,6900,3000,300,111nymous_,RIGHT,ALU1 +S 5200,2800,5200,5200,200,112nymous_,UP,POLY +S 4600,700,4600,2300,600,122nymous_,UP,NDIF +S 7000,700,7000,2300,600,121nymous_,UP,NDIF +S 5800,700,5800,2300,600,120nymous_,UP,NDIF +S 2200,700,2200,2300,600,119nymous_,UP,NDIF +S 1000,700,1000,2300,600,118nymous_,UP,NDIF +S 1600,3000,5600,3000,600,117nymous_,RIGHT,POLY +S 6400,2800,6400,5200,200,116nymous_,UP,POLY +S 2800,2800,2800,5200,200,115nymous_,UP,POLY +S 1600,2800,1600,5200,200,114nymous_,UP,POLY +S 4000,2800,4000,5200,200,113nymous_,UP,POLY +S 11300,3000,13500,3000,300,153nymous_,RIGHT,ALU1 +S 13700,6000,13900,6000,300,152nymous_,RIGHT,ALU1 +S 11300,7000,13500,7000,300,151nymous_,RIGHT,ALU1 +S 14000,5850,14000,6150,400,nsense,UP,CALU3 +S 13600,3100,13600,7900,300,nsense,UP,ALU1 +S 19000,5850,19000,6150,400,nwrite,UP,CALU3 +S 18600,3100,18600,7900,300,nwrite,UP,ALU1 +S 21000,5850,21000,6150,400,nckx,UP,CALU3 +S 3400,700,3400,2300,600,123nymous_,UP,NDIF +S 6400,500,6400,2500,200,124nymous_,UP,NTRANS +S 1600,500,1600,2500,200,125nymous_,UP,NTRANS +S 2800,500,2800,2500,200,126nymous_,UP,NTRANS +S 5200,500,5200,2500,200,127nymous_,UP,NTRANS +S 4000,500,4000,2500,200,128nymous_,UP,NTRANS +S 2200,5700,2200,9300,600,129nymous_,UP,PDIF +S 1000,5700,1000,9300,600,130nymous_,UP,PDIF +S 4600,5700,4600,9300,600,131nymous_,UP,PDIF +S 4000,5500,4000,9500,200,132nymous_,UP,PTRANS +S 5800,5700,5800,9300,600,133nymous_,UP,PDIF +S 7000,5700,7000,9300,600,134nymous_,UP,PDIF +S 6400,5500,6400,9500,200,135nymous_,UP,PTRANS +S 5200,5500,5200,9500,200,136nymous_,UP,PTRANS +S 1600,5500,1600,9500,200,137nymous_,UP,PTRANS +S 2800,5500,2800,9500,200,138nymous_,UP,PTRANS +S 3400,5700,3400,9300,600,139nymous_,UP,PDIF +S 5800,8100,5800,8900,300,140nymous_,UP,ALU1 +S -150,10000,26150,10000,2600,141nymous_,RIGHT,ALU2 +S -150,0,26150,0,2600,142nymous_,RIGHT,ALU2 +S 0,-150,0,10150,2400,143nymous_,UP,ALU3 +S 25000,-150,25000,10150,2400,144nymous_,UP,ALU3 +S 16000,2100,16000,7900,300,145nymous_,UP,ALU1 +S 14800,1100,14800,2900,300,146nymous_,UP,ALU1 +S 15400,3800,15400,6200,200,147nymous_,UP,POLY +S 14200,3800,14200,6200,200,148nymous_,UP,POLY +S 13000,3800,13000,6200,200,149nymous_,UP,POLY +S 11800,3800,11800,6200,200,150nymous_,UP,POLY +S 11500,5000,12500,5000,300,154nymous_,RIGHT,ALU1 +S 14700,5000,15900,5000,300,155nymous_,RIGHT,ALU1 +S 14200,5000,14800,5000,600,156nymous_,RIGHT,POLY +S 12400,5000,13000,5000,600,157nymous_,RIGHT,POLY +S 18000,1500,18000,3500,200,158nymous_,UP,NTRANS +S 18600,1700,18600,3300,600,159nymous_,UP,NDIF +S 18000,3800,18000,6200,200,160nymous_,UP,POLY +S 15400,6000,18000,6000,600,161nymous_,RIGHT,POLY +S 11500,6000,12500,6000,300,162nymous_,RIGHT,ALU1 +S 16000,700,16000,3300,600,163nymous_,UP,NDIF +S 13600,700,13600,3300,600,164nymous_,UP,NDIF +S 11200,700,11200,3300,600,165nymous_,UP,NDIF +S 12400,700,12400,3300,600,166nymous_,UP,NDIF +S 14200,500,14200,3500,200,167nymous_,UP,NTRANS +S 11800,500,11800,3500,200,168nymous_,UP,NTRANS +S 13000,500,13000,3500,200,169nymous_,UP,NTRANS +S 15400,500,15400,3500,200,170nymous_,UP,NTRANS +S 14800,700,14800,3300,600,171nymous_,UP,NDIF +S 11200,2100,11200,2900,300,172nymous_,UP,ALU1 +S 14800,7100,14800,9100,300,173nymous_,UP,ALU1 +S 12400,8100,12400,9100,300,174nymous_,UP,ALU1 +S 14800,6700,14800,9300,600,175nymous_,UP,PDIF +S 12400,6700,12400,9300,600,176nymous_,UP,PDIF +S 11800,6500,11800,9500,200,177nymous_,UP,PTRANS +S 15400,6500,15400,9500,200,178nymous_,UP,PTRANS +S 16000,6700,16000,9300,600,179nymous_,UP,PDIF +S 11200,6700,11200,9300,600,180nymous_,UP,PDIF +S 13600,6700,13600,9300,600,181nymous_,UP,PDIF +S 13000,6500,13000,9500,200,182nymous_,UP,PTRANS +S 14200,6500,14200,9500,200,183nymous_,UP,PTRANS +S 11200,7100,11200,7900,300,184nymous_,UP,ALU1 +S 32000,2100,32000,7900,300,ck,UP,CALU1 +S 10000,2100,10000,7900,300,selram,UP,CALU1 +S 17000,3100,17000,6900,300,w,UP,CALU1 +V 19800,600,CONT_BODY_P,185nymous_ +V 18600,600,CONT_BODY_P,186nymous_ +V 17400,600,CONT_BODY_P,187nymous_ +V 19800,9400,CONT_BODY_N,188nymous_ +V 17400,9400,CONT_BODY_N,189nymous_ +V 19000,6000,CONT_VIA2,190nymous_ +V 22200,3000,CONT_POLY,191nymous_ +V 18600,6000,CONT_VIA,192nymous_ +V 19600,5000,CONT_POLY,193nymous_ +V 19600,5000,CONT_VIA,194nymous_ +V 19800,8000,CONT_DIF_P,195nymous_ +V 19800,7000,CONT_DIF_P,196nymous_ +V 17400,8000,CONT_DIF_P,197nymous_ +V 18600,8000,CONT_DIF_P,198nymous_ +V 18600,7000,CONT_DIF_P,199nymous_ +V 18600,9400,CONT_BODY_N,200nymous_ +V 21000,6000,CONT_VIA2,201nymous_ +V 22600,5000,CONT_VIA,202nymous_ +V 22600,5000,CONT_POLY,203nymous_ +V 22400,9000,CONT_DIF_P,204nymous_ +V 23600,8000,CONT_DIF_P,205nymous_ +V 23600,7000,CONT_DIF_P,206nymous_ +V 23600,6000,CONT_DIF_P,207nymous_ +V 21200,6000,CONT_DIF_P,208nymous_ +V 21200,7000,CONT_DIF_P,209nymous_ +V 21200,8000,CONT_DIF_P,210nymous_ +V 22400,8000,CONT_DIF_P,211nymous_ +V 22400,6000,CONT_DIF_P,212nymous_ +V 22400,7000,CONT_DIF_P,213nymous_ +V 22400,1000,CONT_DIF_N,214nymous_ +V 23600,2000,CONT_DIF_N,215nymous_ +V 21200,2000,CONT_DIF_N,216nymous_ +V 22400,2000,CONT_DIF_N,217nymous_ +V 21200,6000,CONT_VIA,218nymous_ +V 14800,3000,CONT_DIF_N,219nymous_ +V 19800,3000,CONT_DIF_N,220nymous_ +V 14000,6000,CONT_VIA2,221nymous_ +V 14000,6000,CONT_VIA,222nymous_ +V 17000,6000,CONT_POLY,223nymous_ +V 8600,7000,CONT_BODY_N,224nymous_ +V 8600,6000,CONT_BODY_N,225nymous_ +V 8600,9000,CONT_BODY_N,226nymous_ +V 8600,6000,CONT_BODY_N,227nymous_ +V 8600,7000,CONT_BODY_N,228nymous_ +V 8600,8000,CONT_BODY_N,229nymous_ +V 8600,9000,CONT_BODY_N,230nymous_ +V 8600,8000,CONT_BODY_N,231nymous_ +V 8600,1000,CONT_BODY_P,232nymous_ +V 8600,2000,CONT_BODY_P,233nymous_ +V 8600,2000,CONT_BODY_P,234nymous_ +V 8600,1000,CONT_BODY_P,235nymous_ +V 10000,5000,CONT_POLY,236nymous_ +V 33400,9000,CONT_BODY_N,237nymous_ +V 33400,8000,CONT_BODY_N,238nymous_ +V 33400,7000,CONT_BODY_N,239nymous_ +V 33400,6000,CONT_BODY_N,240nymous_ +V 33400,1000,CONT_BODY_P,241nymous_ +V 33400,2000,CONT_BODY_P,242nymous_ +V 30800,5000,CONT_VIA,243nymous_ +V 28400,5000,CONT_VIA,244nymous_ +V 26000,5000,CONT_VIA,245nymous_ +V 32000,4000,CONT_POLY,246nymous_ +V 24800,6000,CONT_DIF_P,247nymous_ +V 24800,6000,CONT_DIF_P,248nymous_ +V 24800,7000,CONT_DIF_P,249nymous_ +V 24800,9000,CONT_DIF_P,250nymous_ +V 26000,8000,CONT_DIF_P,251nymous_ +V 27200,8000,CONT_DIF_P,252nymous_ +V 27200,9000,CONT_DIF_P,253nymous_ +V 24800,8000,CONT_DIF_P,254nymous_ +V 24800,8000,CONT_DIF_P,255nymous_ +V 24800,9000,CONT_DIF_P,256nymous_ +V 24800,7000,CONT_DIF_P,257nymous_ +V 27200,9000,CONT_DIF_P,258nymous_ +V 27200,8000,CONT_DIF_P,259nymous_ +V 29600,6000,CONT_DIF_P,260nymous_ +V 29600,7000,CONT_DIF_P,261nymous_ +V 26000,6000,CONT_DIF_P,262nymous_ +V 26000,7000,CONT_DIF_P,263nymous_ +V 27200,7000,CONT_DIF_P,264nymous_ +V 27200,6000,CONT_DIF_P,265nymous_ +V 27200,6000,CONT_DIF_P,266nymous_ +V 27200,7000,CONT_DIF_P,267nymous_ +V 30800,8000,CONT_DIF_P,268nymous_ +V 30800,7000,CONT_DIF_P,269nymous_ +V 30800,6000,CONT_DIF_P,270nymous_ +V 29600,9000,CONT_DIF_P,271nymous_ +V 29600,8000,CONT_DIF_P,272nymous_ +V 28400,8000,CONT_DIF_P,273nymous_ +V 32000,9000,CONT_DIF_P,274nymous_ +V 28400,7000,CONT_DIF_P,275nymous_ +V 28400,6000,CONT_DIF_P,276nymous_ +V 29600,8000,CONT_DIF_P,277nymous_ +V 29600,9000,CONT_DIF_P,278nymous_ +V 29600,7000,CONT_DIF_P,279nymous_ +V 29600,6000,CONT_DIF_P,280nymous_ +V 26000,2000,CONT_DIF_N,281nymous_ +V 27200,1000,CONT_DIF_N,282nymous_ +V 27200,2000,CONT_DIF_N,283nymous_ +V 27200,1000,CONT_DIF_N,284nymous_ +V 29600,2000,CONT_DIF_N,285nymous_ +V 29600,1000,CONT_DIF_N,286nymous_ +V 24800,1000,CONT_DIF_N,287nymous_ +V 24800,1000,CONT_DIF_N,288nymous_ +V 24800,2000,CONT_DIF_N,289nymous_ +V 24800,2000,CONT_DIF_N,290nymous_ +V 28400,2000,CONT_DIF_N,291nymous_ +V 30800,2000,CONT_DIF_N,292nymous_ +V 29600,1000,CONT_DIF_N,293nymous_ +V 27200,2000,CONT_DIF_N,294nymous_ +V 29600,2000,CONT_DIF_N,295nymous_ +V 32000,1000,CONT_DIF_N,296nymous_ +V 33400,6000,CONT_BODY_N,297nymous_ +V 33400,7000,CONT_BODY_N,298nymous_ +V 33400,8000,CONT_BODY_N,299nymous_ +V 33400,9000,CONT_BODY_N,300nymous_ +V 33400,2000,CONT_BODY_P,301nymous_ +V 33400,1000,CONT_BODY_P,302nymous_ +V 2200,6000,CONT_VIA,303nymous_ +V 3400,1000,CONT_DIF_N,310nymous_ +V 5800,2000,CONT_DIF_N,309nymous_ +V 3400,2000,CONT_DIF_N,308nymous_ +V 2200,2000,CONT_DIF_N,307nymous_ +V 4600,2000,CONT_DIF_N,306nymous_ +V 5600,3000,CONT_POLY,305nymous_ +V 4600,6000,CONT_VIA,304nymous_ +V 5800,1000,CONT_DIF_N,311nymous_ +V 1000,1000,CONT_DIF_N,312nymous_ +V 1000,1000,CONT_DIF_N,313nymous_ +V 1000,2000,CONT_DIF_N,314nymous_ +V 7000,2000,CONT_DIF_N,315nymous_ +V 5800,1000,CONT_DIF_N,316nymous_ +V 2200,8000,CONT_DIF_P,317nymous_ +V 3400,8000,CONT_DIF_P,318nymous_ +V 1000,6000,CONT_DIF_P,319nymous_ +V 1000,7000,CONT_DIF_P,320nymous_ +V 1000,9000,CONT_DIF_P,321nymous_ +V 3400,6000,CONT_DIF_P,322nymous_ +V 3400,7000,CONT_DIF_P,323nymous_ +V 7000,8000,CONT_DIF_P,324nymous_ +V 3400,9000,CONT_DIF_P,325nymous_ +V 1000,8000,CONT_DIF_P,326nymous_ +V 5800,8000,CONT_DIF_P,327nymous_ +V 4600,8000,CONT_DIF_P,328nymous_ +V 4600,7000,CONT_DIF_P,329nymous_ +V 4600,6000,CONT_DIF_P,330nymous_ +V 2200,6000,CONT_DIF_P,331nymous_ +V 2200,7000,CONT_DIF_P,332nymous_ +V 5800,9000,CONT_DIF_P,333nymous_ +V 7000,7000,CONT_DIF_P,334nymous_ +V 7000,6000,CONT_DIF_P,335nymous_ +V 12400,8000,CONT_DIF_P,336nymous_ +V 14800,7000,CONT_DIF_P,337nymous_ +V 14800,8000,CONT_DIF_P,338nymous_ +V 12400,9000,CONT_DIF_P,339nymous_ +V 14800,9000,CONT_DIF_P,340nymous_ +V 14800,3000,CONT_DIF_N,341nymous_ +V 14800,2000,CONT_DIF_N,342nymous_ +V 14800,1000,CONT_DIF_N,343nymous_ +V 16000,3000,CONT_DIF_N,344nymous_ +V 16000,2000,CONT_DIF_N,345nymous_ +V 16000,8000,CONT_DIF_P,346nymous_ +V 16000,7000,CONT_DIF_P,347nymous_ +V 12000,6000,CONT_VIA,348nymous_ +V 12000,6000,CONT_POLY,349nymous_ +V 11200,2000,CONT_DIF_N,359nymous_ +V 17400,2000,CONT_DIF_N,358nymous_ +V 14600,5000,CONT_POLY,357nymous_ +V 12600,5000,CONT_POLY,356nymous_ +V 12000,5000,CONT_VIA,355nymous_ +V 13600,8000,CONT_DIF_P,354nymous_ +V 13600,7000,CONT_DIF_P,353nymous_ +V 11200,7000,CONT_DIF_P,352nymous_ +V 11200,8000,CONT_DIF_P,351nymous_ +V 11200,3000,CONT_DIF_N,350nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_sense_buf1.vbe b/pdks/symbolic/nramlib/cells/ram_sense_buf1.vbe new file mode 100644 index 000000000..c78fe91fb --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_buf1.vbe @@ -0,0 +1,29 @@ +ENTITY ram_sense_buf1 IS +PORT ( + ck : in BIT; + selram : in BIT; + w : in BIT; + nck : out BIT; + selramx : out BIT; + nsense : out BIT; + nwrite : out BIT; + nckx : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_buf1; + +ARCHITECTURE VBE OF ram_sense_buf1 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_buf1" + SEVERITY WARNING; + + nck <= not ck; + nckx <= not ck; + selramx <= selram; + nsense <= not(not ck and selram and not w); + nwrite <= not(not ck and w); + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_sense_data.ap b/pdks/symbolic/nramlib/cells/ram_sense_data.ap new file mode 100644 index 000000000..92a9baec6 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_data.ap @@ -0,0 +1,402 @@ +V ALLIANCE : 6 +H ram_sense_data,P,23/4/2016,100 +A 0,0,34000,10000 +S 25000,-150,25000,10150,2400,7nonymous_,UP,ALU3 +S 0,-150,0,10150,2400,8nonymous_,UP,ALU3 +S 26300,8000,27100,8000,300,9nonymous_,RIGHT,ALU1 +S 26300,2000,27100,2000,300,10onymous_,RIGHT,ALU1 +S 13200,6000,15200,6000,600,11onymous_,RIGHT,POLY +S 21850,5000,23150,5000,600,12onymous_,RIGHT,ALU2 +S 23000,3800,23000,6200,600,13onymous_,UP,POLY +S 21400,1100,21400,1900,300,14onymous_,UP,ALU1 +S 24400,7700,24400,9500,200,15onymous_,UP,NTRANS +S 25600,7700,25600,9500,200,16onymous_,UP,NTRANS +S 26200,7900,26200,9300,600,17onymous_,UP,NDIF +S 1100,9400,33900,9400,1200,vdd,RIGHT,CALU1 +S 100,600,33900,600,1200,vss,RIGHT,CALU1 +S 31680,600,33520,600,600,0nonymous_,RIGHT,PTIE +S 33200,700,33200,2900,300,1nonymous_,UP,ALU1 +S 32000,3100,32000,7900,300,2nonymous_,UP,ALU1 +S 32600,2500,32600,4500,200,3nonymous_,UP,NTRANS +S 33200,2700,33200,4300,600,4nonymous_,UP,NDIF +S 32000,2700,32000,4300,600,5nonymous_,UP,NDIF +S 32600,4800,32600,5800,200,6nonymous_,UP,POLY +S 24400,7400,27200,7400,200,30onymous_,RIGHT,POLY +S 25000,2100,25000,4300,300,29onymous_,UP,ALU1 +S 22900,2000,23700,2000,300,28onymous_,RIGHT,ALU1 +S 22900,8000,23700,8000,300,27onymous_,RIGHT,ALU1 +S 24400,2600,27000,2600,200,26onymous_,RIGHT,POLY +S 23100,5000,23900,5000,300,25onymous_,RIGHT,ALU1 +S -150,2000,5150,2000,600,bit0,RIGHT,CALU2 +S -150,4000,3150,4000,600,nbit0,RIGHT,CALU2 +S -150,6000,4150,6000,600,bit1,RIGHT,CALU2 +S -150,8000,5150,8000,600,nbit1,RIGHT,CALU2 +S 25000,7900,25000,9300,600,18onymous_,UP,NDIF +S 23800,7900,23800,9300,600,19onymous_,UP,NDIF +S 24400,500,24400,2300,200,20onymous_,UP,NTRANS +S 25600,500,25600,2300,200,21onymous_,UP,NTRANS +S 26200,700,26200,2100,600,22onymous_,UP,NDIF +S 25000,700,25000,2100,600,23onymous_,UP,NDIF +S 23800,700,23800,2100,600,24onymous_,UP,NDIF +S 1200,1100,1200,7900,300,63onymous_,UP,ALU1 +S 12200,1500,12200,2500,200,64onymous_,UP,NTRANS +S 11600,700,11600,2300,600,65onymous_,UP,NDIF +S 12800,1700,12800,2300,600,66onymous_,UP,NDIF +S 25000,5700,25000,7900,300,31onymous_,UP,ALU1 +S 21500,3200,23700,3200,300,32onymous_,RIGHT,ALU1 +S 21500,6800,23700,6800,300,33onymous_,RIGHT,ALU1 +S 21400,3300,21400,8900,300,34onymous_,UP,ALU1 +S 27000,6800,27000,7400,600,35onymous_,UP,POLY +S 26850,7000,28150,7000,600,36onymous_,RIGHT,ALU2 +S 26850,3000,28150,3000,600,37onymous_,RIGHT,ALU2 +S 27000,2600,27000,3200,600,38onymous_,UP,POLY +S 27000,3100,27000,3900,300,39onymous_,UP,ALU1 +S 27000,6100,27000,6900,300,40onymous_,UP,ALU1 +S 4100,2000,4900,2000,300,41onymous_,RIGHT,ALU1 +S 2200,6700,2200,7500,300,42onymous_,UP,ALU1 +S 2200,2100,2200,2900,300,43onymous_,UP,ALU1 +S 3100,5600,4900,5600,300,44onymous_,RIGHT,ALU1 +S 4100,3200,4900,3200,300,45onymous_,RIGHT,ALU1 +S 4100,4400,4900,4400,300,46onymous_,RIGHT,ALU1 +S 4100,7000,4900,7000,300,47onymous_,RIGHT,ALU1 +S 4100,8000,4900,8000,300,48onymous_,RIGHT,ALU1 +S 2700,6200,5500,6200,200,49onymous_,RIGHT,NTRANS +S 2700,2600,5500,2600,200,50onymous_,RIGHT,NTRANS +S 2700,3800,5500,3800,200,51onymous_,RIGHT,NTRANS +S 2700,7400,5500,7400,200,52onymous_,RIGHT,NTRANS +S 2900,6800,5300,6800,600,53onymous_,RIGHT,NDIF +S 2900,4400,5300,4400,600,54onymous_,RIGHT,NDIF +S 2900,3200,5300,3200,600,55onymous_,RIGHT,NDIF +S 2900,5600,5300,5600,600,56onymous_,RIGHT,NDIF +S 2900,2000,5300,2000,600,57onymous_,RIGHT,NDIF +S 2900,8000,5300,8000,600,58onymous_,RIGHT,NDIF +S 2200,2600,2200,3200,600,59onymous_,UP,POLY +S 2050,3000,3150,3000,600,60onymous_,RIGHT,ALU2 +S 2050,7000,3150,7000,600,61onymous_,RIGHT,ALU2 +S 2200,6200,2200,6800,600,62onymous_,UP,POLY +S 11600,1100,11600,1900,300,67onymous_,UP,ALU1 +S 4000,4250,4000,6150,600,68onymous_,UP,ALU2 +S 16850,5000,18150,5000,600,69onymous_,RIGHT,ALU2 +S 19000,6100,19000,8900,300,70onymous_,UP,ALU1 +S 9000,7300,9000,8700,300,71onymous_,UP,ALU1 +S 3000,4100,3000,5500,300,72onymous_,UP,ALU1 +S 6600,2700,6600,2900,300,73onymous_,UP,ALU1 +S 4100,3000,6500,3000,300,74onymous_,RIGHT,ALU1 +S 19000,1100,19000,1900,300,75onymous_,UP,ALU1 +S 11000,1200,11000,4200,200,76onymous_,UP,POLY +S 10200,1200,11000,1200,200,77onymous_,RIGHT,POLY +S 11000,4000,11600,4000,600,78onymous_,RIGHT,POLY +S 17800,3800,20800,3800,200,79onymous_,RIGHT,POLY +S 14000,5000,20800,5000,200,80onymous_,RIGHT,POLY +S 14800,3800,16200,3800,200,81onymous_,RIGHT,POLY +S 19600,2800,19600,3800,200,82onymous_,UP,POLY +S 20800,2800,20800,3800,200,83onymous_,UP,POLY +S 20800,5000,20800,5200,200,84onymous_,UP,POLY +S 19600,5000,19600,5200,200,85onymous_,UP,POLY +S 14800,2800,14800,3800,200,86onymous_,UP,POLY +S 5600,7400,6200,7400,200,87onymous_,RIGHT,POLY +S 9800,4200,9800,4800,200,88onymous_,UP,POLY +S 6400,4800,9800,4800,200,89onymous_,RIGHT,POLY +S 6400,2200,8200,2200,200,90onymous_,RIGHT,POLY +S 6000,7400,6000,8200,600,91onymous_,UP,POLY +S 17800,1700,17800,2300,600,92onymous_,UP,NDIF +S 15400,1700,15400,2300,600,93onymous_,UP,NDIF +S 14200,1700,14200,2300,600,94onymous_,UP,NDIF +S 7600,2700,7600,3700,600,95onymous_,UP,NDIF +S 10400,2700,10400,3700,600,96onymous_,UP,NDIF +S 9000,1700,9000,3700,1000,97onymous_,UP,NDIF +S 21400,700,21400,2300,600,98onymous_,UP,NDIF +S 8300,600,9700,600,600,99onymous_,RIGHT,NDIF +S 16600,900,16600,2300,600,100nymous_,UP,NDIF +S 19000,700,19000,2300,600,101nymous_,UP,NDIF +S 20200,700,20200,2300,600,102nymous_,UP,NDIF +S 16000,1500,16000,2500,200,103nymous_,UP,NTRANS +S 17200,1500,17200,2500,200,104nymous_,UP,NTRANS +S 14800,1500,14800,2500,200,105nymous_,UP,NTRANS +S 8100,1200,9900,1200,200,106nymous_,RIGHT,NTRANS +S 8200,2500,8200,3900,200,107nymous_,UP,NTRANS +S 9800,2500,9800,3900,200,108nymous_,UP,NTRANS +S 19600,500,19600,2500,200,109nymous_,UP,NTRANS +S 20800,500,20800,2500,200,110nymous_,UP,NTRANS +S 20800,5500,20800,9500,200,111nymous_,UP,PTRANS +S 6400,8000,22400,8000,6400,112nymous_,RIGHT,NWELL +S 14800,6500,14800,8500,200,113nymous_,UP,PTRANS +S 19000,5700,19000,9300,600,114nymous_,UP,PDIF +S 17800,6700,17800,8300,600,122nymous_,UP,PDIF +S 16000,6500,16000,8500,200,121nymous_,UP,PTRANS +S 16600,6700,16600,8300,600,120nymous_,UP,PDIF +S 10400,7100,10400,8900,600,119nymous_,UP,PDIF +S 9800,6900,9800,9100,200,118nymous_,UP,PTRANS +S 21400,5700,21400,9300,600,117nymous_,UP,PDIF +S 20200,5700,20200,9300,600,116nymous_,UP,PDIF +S 19600,5500,19600,9500,200,115nymous_,UP,PTRANS +S 8200,6600,10600,6600,200,149nymous_,RIGHT,POLY +S 6100,4200,6500,4200,300,148nymous_,RIGHT,ALU1 +S 6100,7800,6500,7800,300,147nymous_,RIGHT,ALU1 +S 4100,6800,6500,6800,300,146nymous_,RIGHT,ALU1 +S 6600,5300,6600,6700,300,145nymous_,UP,ALU1 +S 6100,8000,6500,8000,300,144nymous_,RIGHT,ALU1 +S 6100,4000,6500,4000,300,143nymous_,RIGHT,ALU1 +S 6000,3850,6000,8150,400,ad0x,UP,CALU3 +S 3000,2850,3000,7150,400,nad0x,UP,CALU3 +S 15000,3850,15000,4150,400,sensex,UP,CALU3 +S 18000,4850,18000,5150,400,nsensex,UP,CALU3 +S 27000,2850,27000,7150,400,writex,UP,CALU3 +S 17200,6500,17200,8500,200,123nymous_,UP,PTRANS +S 14200,6700,14200,8300,600,124nymous_,UP,PDIF +S 9000,7100,9000,8900,800,125nymous_,UP,PDIF +S 8200,6900,8200,9100,200,126nymous_,UP,PTRANS +S 7600,7100,7600,8900,600,127nymous_,UP,PDIF +S 23700,5600,25300,5600,600,128nymous_,RIGHT,NDIF +S 23500,6200,25500,6200,200,129nymous_,RIGHT,NTRANS +S 23700,6800,25300,6800,600,130nymous_,RIGHT,NDIF +S 23500,5000,25500,5000,200,131nymous_,RIGHT,NTRANS +S 23700,4400,25300,4400,600,132nymous_,RIGHT,NDIF +S 23500,3800,25500,3800,200,133nymous_,RIGHT,NTRANS +S 23700,3200,25300,3200,600,134nymous_,RIGHT,NDIF +S 15000,3100,15000,5900,300,135nymous_,UP,ALU1 +S 16000,4100,16000,5900,300,136nymous_,UP,ALU1 +S 17000,3100,17000,5900,300,137nymous_,UP,ALU1 +S 18000,2100,18000,7900,300,138nymous_,UP,ALU1 +S 15500,2000,17700,2000,300,139nymous_,RIGHT,ALU1 +S 15100,3000,15900,3000,300,140nymous_,RIGHT,ALU1 +S 5850,8000,7150,8000,600,141nymous_,RIGHT,ALU2 +S 5850,4000,7150,4000,600,142nymous_,RIGHT,ALU2 +S 7600,5600,12200,5600,200,150nymous_,RIGHT,POLY +S 10400,3100,10400,7900,300,151nymous_,UP,ALU1 +S 11250,4000,16150,4000,600,152nymous_,RIGHT,ALU2 +S 11400,4100,11400,4700,300,153nymous_,UP,ALU1 +S 28400,700,28400,4300,600,154nymous_,UP,NDIF +S 29000,500,29000,4500,200,155nymous_,UP,NTRANS +S 29600,700,29600,4300,600,156nymous_,UP,NDIF +S 30200,500,30200,4500,200,157nymous_,UP,NTRANS +S 30800,700,30800,4300,600,158nymous_,UP,NDIF +S 23650,2000,28550,2000,600,159nymous_,RIGHT,ALU2 +S 18050,2000,28350,2000,300,160nymous_,RIGHT,TALU2 +S 29600,1100,29600,3900,300,161nymous_,UP,ALU1 +S 23650,8000,30950,8000,600,162nymous_,RIGHT,ALU2 +S 27400,8400,34600,8400,6000,163nymous_,RIGHT,NWELL +S 28400,6300,28400,8900,600,164nymous_,UP,PDIF +S 29000,6100,29000,9100,200,165nymous_,UP,PTRANS +S 30200,6100,30200,9100,200,166nymous_,UP,PTRANS +S 29600,6300,29600,8900,600,167nymous_,UP,PDIF +S 30800,6300,30800,8900,600,168nymous_,UP,PDIF +S 29000,4800,29000,5800,200,169nymous_,UP,POLY +S 30200,4800,30200,5800,200,170nymous_,UP,POLY +S 29250,5000,32150,5000,600,171nymous_,RIGHT,ALU2 +S 30200,5000,33000,5000,600,172nymous_,RIGHT,POLY +S 33200,6300,33200,9300,600,173nymous_,UP,PDIF +S 32600,6100,32600,9500,200,174nymous_,UP,PTRANS +S 32000,6300,32000,9300,600,175nymous_,UP,PDIF +S 33200,8100,33200,8900,300,176nymous_,UP,ALU1 +S 29400,5100,29400,5900,300,177nymous_,UP,ALU1 +S 29600,7500,29600,8900,300,178nymous_,UP,ALU1 +S 12480,600,15719,600,600,179nymous_,RIGHT,PTIE +S 2480,600,7520,600,600,180nymous_,RIGHT,PTIE +S 14300,7000,16500,7000,300,181nymous_,RIGHT,ALU1 +S 14000,2100,14000,6900,300,182nymous_,UP,ALU1 +S 15400,8100,15400,9300,300,183nymous_,UP,ALU1 +S 15400,6700,15400,8300,600,184nymous_,UP,PDIF +S 12200,2800,12200,6200,200,185nymous_,UP,POLY +S 12800,6700,12800,8300,600,186nymous_,UP,PDIF +S 11600,6700,11600,8300,600,187nymous_,UP,PDIF +S 12200,6500,12200,8500,200,188nymous_,UP,PTRANS +S 11600,7100,11600,9300,300,189nymous_,UP,ALU1 +S 7280,10000,18120,10000,600,190nymous_,RIGHT,NTIE +S 28080,10000,31120,10000,600,191nymous_,RIGHT,NTIE +S 22600,280,22600,2520,600,192nymous_,UP,PTIE +S 1200,1680,1200,8320,600,193nymous_,UP,PTIE +S 6050,8000,30750,8000,300,194nymous_,RIGHT,TALU2 +S 50,3000,27950,3000,300,195nymous_,RIGHT,TALU2 +S 50,5000,3950,5000,300,196nymous_,RIGHT,TALU2 +S 2250,7000,27950,7000,300,197nymous_,RIGHT,TALU2 +S 4850,4000,15950,4000,300,198nymous_,RIGHT,TALU2 +S 17050,5000,31950,5000,300,199nymous_,RIGHT,TALU2 +S 20000,2100,20000,7900,300,dout,UP,CALU1 +S 23000,1850,23000,8150,400,prechx,UP,CALU3 +S 33000,4100,33000,6900,300,din,UP,CALU1 +S 28400,2100,28400,7900,300,dinx,UP,ALU1 +S 12800,2100,12800,6900,300,senseout,UP,ALU1 +S 7600,3100,7600,7900,300,nsenseout,UP,ALU1 +S 3850,7000,24950,7000,600,nbit,RIGHT,ALU2 +S 3850,3000,24950,3000,600,bit,RIGHT,ALU2 +S 30800,2100,30800,7900,300,ndinx,UP,ALU1 +V 33200,600,CONT_BODY_P,200nymous_ +V 32000,600,CONT_BODY_P,201nymous_ +V 32000,4000,CONT_DIF_N,202nymous_ +V 33200,3000,CONT_DIF_N,203nymous_ +V 32000,3000,CONT_DIF_N,204nymous_ +V 21400,6000,CONT_DIF_P,205nymous_ +V 21400,7000,CONT_DIF_P,206nymous_ +V 21400,8000,CONT_DIF_P,207nymous_ +V 23000,5000,CONT_VIA,208nymous_ +V 21400,2000,CONT_DIF_N,209nymous_ +V 24000,3200,CONT_DIF_N,210nymous_ +V 24000,6800,CONT_DIF_N,211nymous_ +V 25000,2000,CONT_DIF_N,212nymous_ +V 23800,2000,CONT_DIF_N,213nymous_ +V 26200,2000,CONT_DIF_N,214nymous_ +V 23800,2000,CONT_VIA,215nymous_ +V 26200,2000,CONT_VIA,216nymous_ +V 25000,4400,CONT_DIF_N,217nymous_ +V 25000,3000,CONT_VIA,218nymous_ +V 25000,5600,CONT_DIF_N,219nymous_ +V 25000,7000,CONT_VIA,220nymous_ +V 23800,8000,CONT_DIF_N,221nymous_ +V 26200,8000,CONT_DIF_N,222nymous_ +V 25000,8000,CONT_DIF_N,223nymous_ +V 23800,8000,CONT_VIA,224nymous_ +V 26200,8000,CONT_VIA,225nymous_ +V 23000,5000,CONT_POLY,226nymous_ +V 23000,5000,CONT_VIA2,227nymous_ +V 27000,7000,CONT_VIA,228nymous_ +V 27000,3000,CONT_POLY,229nymous_ +V 27000,3000,CONT_VIA,230nymous_ +V 27000,7000,CONT_POLY,231nymous_ +V 2200,3000,CONT_VIA,232nymous_ +V 2200,7000,CONT_VIA,233nymous_ +V 2200,6600,CONT_POLY,234nymous_ +V 2200,3000,CONT_POLY,235nymous_ +V 1200,2000,CONT_BODY_P,236nymous_ +V 1200,3000,CONT_BODY_P,237nymous_ +V 1200,7000,CONT_BODY_P,238nymous_ +V 1200,8000,CONT_BODY_P,239nymous_ +V 5000,5600,CONT_DIF_N,303nymous_ +V 10400,3000,CONT_DIF_N,302nymous_ +V 7600,3000,CONT_DIF_N,301nymous_ +V 1200,6000,CONT_BODY_P,240nymous_ +V 1200,5000,CONT_BODY_P,241nymous_ +V 1200,4000,CONT_BODY_P,242nymous_ +V 11600,1000,CONT_DIF_N,243nymous_ +V 11600,2000,CONT_DIF_N,244nymous_ +V 12800,2000,CONT_DIF_N,245nymous_ +V 12800,600,CONT_BODY_P,246nymous_ +V 13000,6000,CONT_POLY,247nymous_ +V 11400,4000,CONT_POLY,248nymous_ +V 18000,5000,CONT_VIA2,249nymous_ +V 15000,4000,CONT_VIA2,250nymous_ +V 6000,8000,CONT_VIA2,251nymous_ +V 6000,4000,CONT_VIA2,252nymous_ +V 3000,3000,CONT_VIA2,253nymous_ +V 3000,7000,CONT_VIA2,254nymous_ +V 27000,7000,CONT_VIA2,255nymous_ +V 27000,3000,CONT_VIA2,256nymous_ +V 16000,4000,CONT_VIA,257nymous_ +V 17000,5000,CONT_VIA,258nymous_ +V 5000,2000,CONT_VIA,259nymous_ +V 4000,8000,CONT_VIA,260nymous_ +V 5000,8000,CONT_VIA,261nymous_ +V 4000,4400,CONT_VIA,262nymous_ +V 4000,2000,CONT_VIA,263nymous_ +V 6000,8000,CONT_VIA,264nymous_ +V 6000,4000,CONT_VIA,265nymous_ +V 5000,7000,CONT_VIA,266nymous_ +V 4000,7000,CONT_VIA,267nymous_ +V 5000,3000,CONT_VIA,268nymous_ +V 4000,3000,CONT_VIA,269nymous_ +V 3000,4000,CONT_VIA,270nymous_ +V 16000,4000,CONT_POLY,271nymous_ +V 16000,3000,CONT_POLY,272nymous_ +V 17000,6000,CONT_POLY,273nymous_ +V 17000,3000,CONT_POLY,274nymous_ +V 18000,4000,CONT_POLY,275nymous_ +V 6000,4000,CONT_POLY,276nymous_ +V 6000,8000,CONT_POLY,277nymous_ +V 16000,6000,CONT_POLY,278nymous_ +V 15000,6000,CONT_POLY,279nymous_ +V 14000,5000,CONT_POLY,280nymous_ +V 6600,5200,CONT_POLY,281nymous_ +V 6600,2600,CONT_POLY,282nymous_ +V 6000,600,CONT_BODY_P,283nymous_ +V 7200,600,CONT_BODY_P,284nymous_ +V 15400,600,CONT_BODY_P,285nymous_ +V 14200,600,CONT_BODY_P,286nymous_ +V 20200,2000,CONT_DIF_N,287nymous_ +V 19000,2000,CONT_DIF_N,288nymous_ +V 4000,2000,CONT_DIF_N,289nymous_ +V 15400,2000,CONT_DIF_N,290nymous_ +V 14200,2000,CONT_DIF_N,291nymous_ +V 17800,2000,CONT_DIF_N,292nymous_ +V 5000,3200,CONT_DIF_N,293nymous_ +V 5000,2000,CONT_DIF_N,294nymous_ +V 5000,4400,CONT_DIF_N,295nymous_ +V 4000,5600,CONT_DIF_N,296nymous_ +V 4000,8000,CONT_DIF_N,297nymous_ +V 4000,6800,CONT_DIF_N,298nymous_ +V 4000,3200,CONT_DIF_N,299nymous_ +V 4000,4400,CONT_DIF_N,300nymous_ +V 5000,6800,CONT_DIF_N,304nymous_ +V 5000,8000,CONT_DIF_N,305nymous_ +V 9600,600,CONT_DIF_N,306nymous_ +V 16600,1000,CONT_DIF_N,307nymous_ +V 21400,1000,CONT_DIF_N,308nymous_ +V 19000,1000,CONT_DIF_N,309nymous_ +V 8400,600,CONT_DIF_N,310nymous_ +V 19000,9000,CONT_DIF_P,311nymous_ +V 19000,7000,CONT_DIF_P,312nymous_ +V 19000,6000,CONT_DIF_P,313nymous_ +V 19000,8000,CONT_DIF_P,314nymous_ +V 17800,8000,CONT_DIF_P,315nymous_ +V 20200,6000,CONT_DIF_P,316nymous_ +V 20200,7000,CONT_DIF_P,317nymous_ +V 20200,8000,CONT_DIF_P,318nymous_ +V 21400,9000,CONT_DIF_P,319nymous_ +V 10400,7200,CONT_DIF_P,320nymous_ +V 9000,10000,CONT_BODY_N,321nymous_ +V 7600,10000,CONT_BODY_N,322nymous_ +V 10400,10000,CONT_BODY_N,323nymous_ +V 9000,8000,CONT_DIF_P,324nymous_ +V 9000,7200,CONT_DIF_P,325nymous_ +V 9000,8800,CONT_DIF_P,326nymous_ +V 7600,7200,CONT_DIF_P,327nymous_ +V 7600,8000,CONT_DIF_P,328nymous_ +V 10400,8000,CONT_DIF_P,329nymous_ +V 10400,6400,CONT_POLY,330nymous_ +V 7600,5800,CONT_POLY,331nymous_ +V 11400,4000,CONT_VIA,332nymous_ +V 28400,2000,CONT_VIA,333nymous_ +V 28400,2000,CONT_DIF_N,334nymous_ +V 28400,3000,CONT_DIF_N,335nymous_ +V 29600,2000,CONT_DIF_N,336nymous_ +V 29600,1000,CONT_DIF_N,337nymous_ +V 29600,3000,CONT_DIF_N,338nymous_ +V 29600,4000,CONT_DIF_N,339nymous_ +V 30800,2000,CONT_DIF_N,340nymous_ +V 30800,3000,CONT_DIF_N,341nymous_ +V 29600,7400,CONT_DIF_P,342nymous_ +V 29600,8400,CONT_DIF_P,343nymous_ +V 28400,10000,CONT_BODY_N,344nymous_ +V 29600,10000,CONT_BODY_N,345nymous_ +V 30800,10000,CONT_BODY_N,346nymous_ +V 30800,8000,CONT_VIA,347nymous_ +V 30800,8000,CONT_DIF_P,348nymous_ +V 28400,8000,CONT_DIF_P,349nymous_ +V 28400,7000,CONT_DIF_P,350nymous_ +V 28400,4000,CONT_DIF_N,351nymous_ +V 30800,4000,CONT_DIF_N,352nymous_ +V 33000,5000,CONT_POLY,353nymous_ +V 33200,8000,CONT_DIF_P,359nymous_ +V 33200,9000,CONT_DIF_P,358nymous_ +V 32000,8000,CONT_DIF_P,357nymous_ +V 32000,7000,CONT_DIF_P,356nymous_ +V 32000,5000,CONT_VIA,355nymous_ +V 29400,5000,CONT_POLY,354nymous_ +V 29400,5000,CONT_VIA,360nymous_ +V 30800,7000,CONT_DIF_P,361nymous_ +V 2800,600,CONT_BODY_P,362nymous_ +V 3800,600,CONT_BODY_P,363nymous_ +V 4800,600,CONT_BODY_P,364nymous_ +V 16600,7000,CONT_DIF_P,365nymous_ +V 14200,7000,CONT_DIF_P,366nymous_ +V 15400,8000,CONT_DIF_P,367nymous_ +V 12800,7000,CONT_DIF_P,368nymous_ +V 11600,7000,CONT_DIF_P,369nymous_ +V 11600,8000,CONT_DIF_P,370nymous_ +V 15400,10000,CONT_BODY_N,371nymous_ +V 12800,10000,CONT_BODY_N,372nymous_ +V 11600,10000,CONT_BODY_N,373nymous_ +V 16600,10000,CONT_BODY_N,374nymous_ +V 14200,10000,CONT_BODY_N,375nymous_ +V 17800,10000,CONT_BODY_N,376nymous_ +V 22600,600,CONT_BODY_P,377nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_sense_data.vbe b/pdks/symbolic/nramlib/cells/ram_sense_data.vbe new file mode 100644 index 000000000..747388b08 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_data.vbe @@ -0,0 +1,70 @@ +entity RAM_SENSE_DATA is + + port + ( + bit0 : inout wor_bit bus; + Nbit0 : inout wor_bit bus; + bit1 : inout wor_bit bus; + Nbit1 : inout wor_bit bus; + AD0X : in bit ; + NAD0X : in bit ; + SENSEX : in bit ; + NSENSEX : in bit ; + PRECHX : in bit ; + WRITEX : in bit ; + DIN : in bit ; + DOUT : out mux_bit bus; + VDD : in bit ; + VSS : in bit + ); + +end RAM_SENSE_DATA; + +architecture vbe of RAM_SENSE_DATA is + +begin + + assert (VDD = '1' and VSS = '0') + report "power supply is missing on ram_sense_data" + severity WARNING; + + assert ((AD0X xor NAD0X ) = '1') + report "conflicting ad0x / nad0x in ram_sense_data" + severity WARNING; + + assert ((SENSEX xor NSENSEX) = '1') + report "conflicting sensex / nsensex in ram_sense_data" + severity WARNING; + + WRITE_0 : block (NAD0X = '1' and WRITEX = '1') + begin + BIT0 <= guarded DIN; + NBIT0 <= guarded not DIN; + end block; + + WRITE_1 : block (AD0X = '1' and WRITEX = '1') + begin + BIT1 <= guarded DIN; + NBIT1 <= guarded not DIN; + end block; + + SENSE_0 : block (PRECHX = '0' and WRITEX = '0' and (BIT0 xor NBIT0) = '1') + begin + BIT0 <= guarded BIT0 ; + NBIT0 <= guarded NBIT0; + end block; + + SENSE_1 : block (PRECHX = '0' and WRITEX = '0' and (BIT1 xor NBIT1) = '1') + begin + BIT1 <= guarded BIT1 ; + NBIT1 <= guarded NBIT1; + end block; + + DATA_OUT : block (SENSEX = '1') + begin + with AD0X select + DOUT <= guarded bit0 when '0', + bit1 when '1'; + end block; + +end; diff --git a/pdks/symbolic/nramlib/cells/ram_sense_decad12.ap b/pdks/symbolic/nramlib/cells/ram_sense_decad12.ap new file mode 100644 index 000000000..04273fd56 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_decad12.ap @@ -0,0 +1,327 @@ +V ALLIANCE : 6 +H ram_sense_decad12,P,23/4/2016,100 +A 0,0,34000,10000 +S 4079,600,5920,600,600,3nonymous_,RIGHT,PTIE +S 100,9400,33900,9400,1200,vdd,RIGHT,CALU1 +S 100,600,33900,600,1200,vss,RIGHT,CALU1 +S 30600,1100,30600,1900,300,0nonymous_,UP,ALU1 +S 16080,600,17920,600,600,1nonymous_,RIGHT,PTIE +S 10080,600,11919,600,600,2nonymous_,RIGHT,PTIE +S 10080,9400,11919,9400,600,13onymous_,RIGHT,NTIE +S 4079,9400,5920,9400,600,14onymous_,RIGHT,NTIE +S 16080,9400,17920,9400,600,15onymous_,RIGHT,NTIE +S 22080,9400,28120,9400,600,16onymous_,RIGHT,NTIE +S 24680,600,28120,600,600,17onymous_,RIGHT,PTIE +S 5600,1700,5600,2300,600,4nonymous_,UP,NDIF +S 6200,1700,6200,2300,1000,5nonymous_,UP,NDIF +S 6800,1100,6800,1900,300,6nonymous_,UP,ALU1 +S 12200,1700,12200,2300,1000,7nonymous_,UP,NDIF +S 11600,1700,11600,2300,600,8nonymous_,UP,NDIF +S 18200,1700,18200,2300,1000,9nonymous_,UP,NDIF +S 17600,1700,17600,2300,600,10onymous_,UP,NDIF +S 12800,1100,12800,1900,300,11onymous_,UP,ALU1 +S 18800,1100,18800,1900,300,12onymous_,UP,ALU1 +S 29600,5500,29600,9500,200,38onymous_,UP,PTRANS +S 29600,500,29600,2500,200,37onymous_,UP,NTRANS +S 28000,4000,29600,4000,600,36onymous_,RIGHT,POLY +S 31400,4000,33000,4000,600,35onymous_,RIGHT,POLY +S 30600,6100,30600,8900,300,34onymous_,UP,ALU1 +S 30500,700,30500,2300,1000,33onymous_,UP,NDIF +S 15450,2000,28950,2000,300,18onymous_,RIGHT,TALU2 +S 3450,3000,27950,3000,300,19onymous_,RIGHT,TALU2 +S 10650,7000,31950,7000,300,20onymous_,RIGHT,TALU2 +S 4650,8000,32950,8000,300,21onymous_,RIGHT,TALU2 +S 22600,3100,22600,6900,300,22onymous_,UP,ALU1 +S 21400,2100,21400,4900,300,23onymous_,UP,ALU1 +S 16600,3100,16600,7900,300,24onymous_,UP,ALU1 +S 15400,2100,15400,4900,300,25onymous_,UP,ALU1 +S 10600,3100,10600,6900,300,26onymous_,UP,ALU1 +S 10450,7000,32150,7000,600,27onymous_,RIGHT,ALU2 +S 9400,3100,9400,4900,300,28onymous_,UP,ALU1 +S 4450,8000,33150,8000,600,29onymous_,RIGHT,ALU2 +S 4600,3100,4600,7900,300,30onymous_,UP,ALU1 +S 3400,3100,3400,4900,300,31onymous_,UP,ALU1 +S 30500,5700,30500,9300,1000,32onymous_,UP,PDIF +S 29600,2800,29600,5200,200,39onymous_,UP,POLY +S 29000,5700,29000,9300,600,40onymous_,UP,PDIF +S 29000,700,29000,2300,600,41onymous_,UP,NDIF +S 29000,2100,29000,7900,300,42onymous_,UP,ALU1 +S 32000,5700,32000,9300,600,43onymous_,UP,PDIF +S 32000,700,32000,2300,600,44onymous_,UP,NDIF +S 31400,5500,31400,9500,200,45onymous_,UP,PTRANS +S 31400,500,31400,2500,200,46onymous_,UP,NTRANS +S 31400,2800,31400,5200,200,47onymous_,UP,POLY +S 32000,2100,32000,7900,300,48onymous_,UP,ALU1 +S 19400,5500,19400,9500,200,49onymous_,UP,PTRANS +S 18800,5700,18800,9300,600,50onymous_,UP,PDIF +S 21200,5700,21200,9300,600,51onymous_,UP,PDIF +S 20000,5700,20000,9300,600,52onymous_,UP,PDIF +S 20600,5500,20600,9500,200,53onymous_,UP,PTRANS +S 14000,5700,14000,9300,600,54onymous_,UP,PDIF +S 15200,5700,15200,9300,600,55onymous_,UP,PDIF +S 12800,5700,12800,9300,600,56onymous_,UP,PDIF +S 13400,5500,13400,9500,200,57onymous_,UP,PTRANS +S 14600,5500,14600,9500,200,58onymous_,UP,PTRANS +S 13400,500,13400,2500,200,59onymous_,UP,NTRANS +S 14600,500,14600,2500,200,60onymous_,UP,NTRANS +S 20600,500,20600,2500,200,61onymous_,UP,NTRANS +S 19400,500,19400,2500,200,62onymous_,UP,NTRANS +S 20000,700,20000,2300,600,63onymous_,UP,NDIF +S 21200,700,21200,2300,600,64onymous_,UP,NDIF +S 18800,700,18800,2300,600,65onymous_,UP,NDIF +S 14000,700,14000,2300,600,66onymous_,UP,NDIF +S 21200,5000,21800,5000,600,72onymous_,RIGHT,POLY +S 21200,3000,21800,3000,600,71onymous_,RIGHT,POLY +S 20600,2800,20600,5200,200,70onymous_,UP,POLY +S 19400,2800,19400,5200,200,69onymous_,UP,POLY +S 15200,700,15200,2300,600,68onymous_,UP,NDIF +S 12800,700,12800,2300,600,67onymous_,UP,NDIF +S 13400,2800,13400,5200,200,73onymous_,UP,POLY +S 15200,5000,15800,5000,600,74onymous_,RIGHT,POLY +S 15200,3000,15800,3000,600,75onymous_,RIGHT,POLY +S 14600,2800,14600,5200,200,76onymous_,UP,POLY +S 18800,6100,18800,8900,300,77onymous_,UP,ALU1 +S 20000,2100,20000,7900,300,78onymous_,UP,ALU1 +S 21200,6100,21200,8900,300,79onymous_,UP,ALU1 +S 14000,2100,14000,7900,300,80onymous_,UP,ALU1 +S 12800,6100,12800,8900,300,81onymous_,UP,ALU1 +S 15200,6100,15200,8900,300,82onymous_,UP,ALU1 +S 8000,5700,8000,9300,600,83onymous_,UP,PDIF +S 9200,5700,9200,9300,600,84onymous_,UP,PDIF +S 6800,5700,6800,9300,600,85onymous_,UP,PDIF +S 7400,5500,7400,9500,200,86onymous_,UP,PTRANS +S 8600,5500,8600,9500,200,87onymous_,UP,PTRANS +S 7400,500,7400,2500,200,88onymous_,UP,NTRANS +S 8600,500,8600,2500,200,89onymous_,UP,NTRANS +S 6800,700,6800,2300,600,90onymous_,UP,NDIF +S 9200,700,9200,2300,600,91onymous_,UP,NDIF +S 8000,700,8000,2300,600,92onymous_,UP,NDIF +S 7400,2800,7400,5200,200,93onymous_,UP,POLY +S 9200,5000,9800,5000,600,94onymous_,RIGHT,POLY +S 9200,3000,9800,3000,600,95onymous_,RIGHT,POLY +S 8600,2800,8600,5200,200,96onymous_,UP,POLY +S 9200,6100,9200,8900,300,97onymous_,UP,ALU1 +S 8000,2100,8000,7900,300,98onymous_,UP,ALU1 +S 6800,6100,6800,8900,300,99onymous_,UP,ALU1 +S 3200,6100,3200,8900,300,100nymous_,UP,ALU1 +S 2600,5500,2600,9500,200,101nymous_,UP,PTRANS +S 1400,5500,1400,9500,200,102nymous_,UP,PTRANS +S 800,5700,800,9300,600,103nymous_,UP,PDIF +S 3200,5700,3200,9300,600,104nymous_,UP,PDIF +S 2000,5700,2000,9300,600,105nymous_,UP,PDIF +S 2600,500,2600,2500,200,106nymous_,UP,NTRANS +S 1400,500,1400,2500,200,107nymous_,UP,NTRANS +S 2000,700,2000,2300,600,108nymous_,UP,NDIF +S 3200,700,3200,2300,600,109nymous_,UP,NDIF +S 800,700,800,2300,600,110nymous_,UP,NDIF +S 4400,5700,4400,8300,600,122nymous_,UP,PDIF +S 3800,5500,3800,8500,200,121nymous_,UP,PTRANS +S -600,7800,6600,7800,6000,120nymous_,RIGHT,NWELL +S 5400,7800,12600,7800,6000,119nymous_,RIGHT,NWELL +S -600,7800,34600,7800,6000,118nymous_,RIGHT,NWELL +S 800,6100,800,8900,300,117nymous_,UP,ALU1 +S 2000,2100,2000,7900,300,116nymous_,UP,ALU1 +S 800,1100,800,3300,300,115nymous_,UP,ALU1 +S 2600,2800,2600,5200,200,114nymous_,UP,POLY +S 1400,2800,1400,5200,200,113nymous_,UP,POLY +S 3200,5000,3800,5000,600,112nymous_,RIGHT,POLY +S 3200,3000,3800,3000,600,111nymous_,RIGHT,POLY +S 22400,3000,23000,3000,600,158nymous_,RIGHT,POLY +S 22400,5000,23000,5000,600,157nymous_,RIGHT,POLY +S 23600,2100,23600,5900,300,156nymous_,UP,ALU1 +S 22500,2000,23500,2000,300,155nymous_,RIGHT,ALU1 +S 17600,5700,17600,8300,600,154nymous_,UP,PDIF +S 17000,5500,17000,8500,200,153nymous_,UP,PTRANS +S 5000,5500,5000,8500,200,123nymous_,UP,PTRANS +S 5600,5700,5600,8300,600,124nymous_,UP,PDIF +S 3800,1500,3800,2500,200,125nymous_,UP,NTRANS +S 5000,1500,5000,2500,200,126nymous_,UP,NTRANS +S 4400,1700,4400,2300,600,127nymous_,UP,NDIF +S 5600,2100,5600,5900,300,128nymous_,UP,ALU1 +S 4500,2000,5500,2000,300,129nymous_,RIGHT,ALU1 +S 4400,3000,5000,3000,600,130nymous_,RIGHT,POLY +S 4400,5000,5000,5000,600,131nymous_,RIGHT,POLY +S 1400,4000,5600,4000,600,132nymous_,RIGHT,POLY +S 11600,2100,11600,5900,300,133nymous_,UP,ALU1 +S 10500,2000,11500,2000,300,134nymous_,RIGHT,ALU1 +S 10400,3000,11000,3000,600,135nymous_,RIGHT,POLY +S 10400,5000,11000,5000,600,136nymous_,RIGHT,POLY +S 9800,5500,9800,8500,200,137nymous_,UP,PTRANS +S 10400,1700,10400,2300,600,138nymous_,UP,NDIF +S 11000,1500,11000,2500,200,139nymous_,UP,NTRANS +S 9800,1500,9800,2500,200,140nymous_,UP,NTRANS +S 11600,5700,11600,8300,600,141nymous_,UP,PDIF +S 11000,5500,11000,8500,200,142nymous_,UP,PTRANS +S 10400,5700,10400,8300,600,143nymous_,UP,PDIF +S 17600,2100,17600,5900,300,144nymous_,UP,ALU1 +S 16500,2000,17500,2000,300,145nymous_,RIGHT,ALU1 +S 16400,5000,17000,5000,600,146nymous_,RIGHT,POLY +S 16400,3000,17000,3000,600,147nymous_,RIGHT,POLY +S 15800,5500,15800,8500,200,148nymous_,UP,PTRANS +S 16400,1700,16400,2300,600,149nymous_,UP,NDIF +S 15800,1500,15800,2500,200,150nymous_,UP,NTRANS +S 17000,1500,17000,2500,200,151nymous_,UP,NTRANS +S 16400,5700,16400,8300,600,152nymous_,UP,PDIF +S 21800,5500,21800,8500,200,159nymous_,UP,PTRANS +S 22400,1700,22400,2300,600,160nymous_,UP,NDIF +S 23600,700,23600,2300,600,161nymous_,UP,NDIF +S 21800,1500,21800,2500,200,162nymous_,UP,NTRANS +S 23000,1500,23000,2500,200,163nymous_,UP,NTRANS +S 23600,5700,23600,8300,600,164nymous_,UP,PDIF +S 23000,5500,23000,8500,200,165nymous_,UP,PTRANS +S 22400,5700,22400,8300,600,166nymous_,UP,PDIF +S 3250,3000,28150,3000,600,167nymous_,RIGHT,ALU2 +S 15250,2000,29150,2000,600,168nymous_,RIGHT,ALU2 +S 7400,4000,11600,4000,600,169nymous_,RIGHT,POLY +S 13400,4000,17600,4000,600,170nymous_,RIGHT,POLY +S 19400,4000,23600,4000,600,171nymous_,RIGHT,POLY +S 25000,-150,25000,10150,2400,172nymous_,UP,ALU3 +S 0,-150,0,10150,2400,173nymous_,UP,ALU3 +S 33000,2100,33000,7900,300,ad1,UP,CALU1 +S 28000,2100,28000,7900,300,ad2,UP,CALU1 +S 18850,6000,20150,6000,600,ndec11,RIGHT,CALU2 +S 12850,5000,14150,5000,600,ndec10,RIGHT,CALU2 +S 6850,4000,8150,4000,600,ndec01,RIGHT,CALU2 +S 850,3000,2150,3000,600,ndec00,RIGHT,CALU2 +V 17600,600,CONT_BODY_P,174nymous_ +V 11600,600,CONT_BODY_P,175nymous_ +V 5600,600,CONT_BODY_P,176nymous_ +V 26400,600,CONT_BODY_P,177nymous_ +V 25000,600,CONT_BODY_P,178nymous_ +V 26400,9400,CONT_BODY_N,179nymous_ +V 25000,9400,CONT_BODY_N,180nymous_ +V 16600,8000,CONT_VIA,181nymous_ +V 22600,7000,CONT_VIA,182nymous_ +V 21400,2000,CONT_VIA,183nymous_ +V 15400,2000,CONT_VIA,184nymous_ +V 10600,7000,CONT_VIA,185nymous_ +V 4600,8000,CONT_VIA,186nymous_ +V 27800,600,CONT_BODY_P,187nymous_ +V 27800,9400,CONT_BODY_N,188nymous_ +V 30600,9000,CONT_DIF_P,189nymous_ +V 30600,6000,CONT_DIF_P,190nymous_ +V 30600,7000,CONT_DIF_P,191nymous_ +V 30600,8000,CONT_DIF_P,192nymous_ +V 30600,2000,CONT_DIF_N,193nymous_ +V 30600,1000,CONT_DIF_N,194nymous_ +V 29000,2000,CONT_VIA,195nymous_ +V 28000,3000,CONT_VIA,196nymous_ +V 28000,4000,CONT_POLY,197nymous_ +V 33000,4000,CONT_POLY,198nymous_ +V 32000,7000,CONT_VIA,199nymous_ +V 29000,7000,CONT_DIF_P,200nymous_ +V 29000,8000,CONT_DIF_P,201nymous_ +V 29000,6000,CONT_DIF_P,202nymous_ +V 29000,2000,CONT_DIF_N,203nymous_ +V 33000,8000,CONT_VIA,204nymous_ +V 32000,6000,CONT_DIF_P,205nymous_ +V 32000,8000,CONT_DIF_P,206nymous_ +V 32000,7000,CONT_DIF_P,207nymous_ +V 32000,2000,CONT_DIF_N,208nymous_ +V 20000,6000,CONT_VIA,209nymous_ +V 14000,5000,CONT_VIA,210nymous_ +V 8000,4000,CONT_VIA,211nymous_ +V 2000,3000,CONT_VIA,212nymous_ +V 21200,7000,CONT_DIF_P,213nymous_ +V 21200,6000,CONT_DIF_P,214nymous_ +V 21200,9000,CONT_DIF_P,215nymous_ +V 18800,8000,CONT_DIF_P,216nymous_ +V 18800,9000,CONT_DIF_P,217nymous_ +V 18800,6000,CONT_DIF_P,218nymous_ +V 18800,7000,CONT_DIF_P,219nymous_ +V 20000,8000,CONT_DIF_P,220nymous_ +V 20000,6000,CONT_DIF_P,221nymous_ +V 21200,8000,CONT_DIF_P,222nymous_ +V 15200,9000,CONT_DIF_P,223nymous_ +V 15200,6000,CONT_DIF_P,224nymous_ +V 15200,7000,CONT_DIF_P,225nymous_ +V 14000,6000,CONT_DIF_P,226nymous_ +V 20000,7000,CONT_DIF_P,227nymous_ +V 14000,8000,CONT_DIF_P,228nymous_ +V 12800,7000,CONT_DIF_P,229nymous_ +V 12800,6000,CONT_DIF_P,230nymous_ +V 12800,9000,CONT_DIF_P,231nymous_ +V 12800,8000,CONT_DIF_P,232nymous_ +V 15200,8000,CONT_DIF_P,233nymous_ +V 14000,7000,CONT_DIF_P,234nymous_ +V 18800,2000,CONT_DIF_N,235nymous_ +V 18800,1000,CONT_DIF_N,236nymous_ +V 20000,2000,CONT_DIF_N,237nymous_ +V 21200,1000,CONT_DIF_N,238nymous_ +V 12800,1000,CONT_DIF_N,239nymous_ +V 12800,2000,CONT_DIF_N,240nymous_ +V 15200,1000,CONT_DIF_N,241nymous_ +V 14000,2000,CONT_DIF_N,242nymous_ +V 21400,5000,CONT_POLY,243nymous_ +V 21400,3000,CONT_POLY,244nymous_ +V 15400,3000,CONT_POLY,245nymous_ +V 15400,5000,CONT_POLY,246nymous_ +V 9200,8000,CONT_DIF_P,247nymous_ +V 9200,9000,CONT_DIF_P,248nymous_ +V 9200,6000,CONT_DIF_P,249nymous_ +V 9200,7000,CONT_DIF_P,250nymous_ +V 8000,6000,CONT_DIF_P,251nymous_ +V 8000,7000,CONT_DIF_P,252nymous_ +V 8000,8000,CONT_DIF_P,253nymous_ +V 6800,7000,CONT_DIF_P,254nymous_ +V 6800,6000,CONT_DIF_P,255nymous_ +V 6800,9000,CONT_DIF_P,256nymous_ +V 6800,8000,CONT_DIF_P,257nymous_ +V 6800,1000,CONT_DIF_N,258nymous_ +V 6800,2000,CONT_DIF_N,259nymous_ +V 9200,1000,CONT_DIF_N,260nymous_ +V 8000,2000,CONT_DIF_N,261nymous_ +V 9400,3000,CONT_POLY,262nymous_ +V 9400,5000,CONT_POLY,263nymous_ +V 3200,7000,CONT_DIF_P,264nymous_ +V 3200,6000,CONT_DIF_P,265nymous_ +V 3200,9000,CONT_DIF_P,266nymous_ +V 3200,8000,CONT_DIF_P,267nymous_ +V 800,7000,CONT_DIF_P,268nymous_ +V 2000,8000,CONT_DIF_P,269nymous_ +V 2000,7000,CONT_DIF_P,270nymous_ +V 2000,6000,CONT_DIF_P,271nymous_ +V 800,8000,CONT_DIF_P,272nymous_ +V 800,9000,CONT_DIF_P,273nymous_ +V 800,6000,CONT_DIF_P,274nymous_ +V 2000,2000,CONT_DIF_N,275nymous_ +V 3200,1000,CONT_DIF_N,276nymous_ +V 800,2000,CONT_DIF_N,277nymous_ +V 800,1000,CONT_DIF_N,278nymous_ +V 3400,3000,CONT_POLY,279nymous_ +V 3400,5000,CONT_POLY,280nymous_ +V 4400,2000,CONT_DIF_N,281nymous_ +V 5600,6000,CONT_DIF_P,282nymous_ +V 4600,3000,CONT_POLY,283nymous_ +V 4600,5000,CONT_POLY,284nymous_ +V 5600,4000,CONT_POLY,285nymous_ +V 4400,9400,CONT_BODY_N,286nymous_ +V 5600,9400,CONT_BODY_N,287nymous_ +V 4400,600,CONT_BODY_P,288nymous_ +V 10600,5000,CONT_POLY,289nymous_ +V 10600,3000,CONT_POLY,290nymous_ +V 11600,4000,CONT_POLY,291nymous_ +V 10400,600,CONT_BODY_P,292nymous_ +V 10400,2000,CONT_DIF_N,293nymous_ +V 11600,9400,CONT_BODY_N,294nymous_ +V 11600,6000,CONT_DIF_P,295nymous_ +V 10400,9400,CONT_BODY_N,296nymous_ +V 17600,4000,CONT_POLY,297nymous_ +V 16600,3000,CONT_POLY,298nymous_ +V 16600,5000,CONT_POLY,299nymous_ +V 16400,600,CONT_BODY_P,300nymous_ +V 16400,2000,CONT_DIF_N,301nymous_ +V 16400,9400,CONT_BODY_N,302nymous_ +V 17600,6000,CONT_DIF_P,303nymous_ +V 9400,3000,CONT_VIA,314nymous_ +V 3400,3000,CONT_VIA,313nymous_ +V 17600,9400,CONT_BODY_N,304nymous_ +V 22600,5000,CONT_POLY,305nymous_ +V 22600,3000,CONT_POLY,306nymous_ +V 23600,4000,CONT_POLY,307nymous_ +V 23600,1000,CONT_DIF_N,308nymous_ +V 22400,2000,CONT_DIF_N,309nymous_ +V 22400,9400,CONT_BODY_N,310nymous_ +V 23600,9400,CONT_BODY_N,311nymous_ +V 23600,6000,CONT_DIF_P,312nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_sense_decad12.vbe b/pdks/symbolic/nramlib/cells/ram_sense_decad12.vbe new file mode 100644 index 000000000..a80aee48a --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_decad12.vbe @@ -0,0 +1,21 @@ +ENTITY ram_sense_decad12 IS +PORT ( + ad1 : in BIT; + ad2 : in BIT; + ndec00 : out BIT; + ndec01 : out BIT; + ndec10 : out BIT; + ndec11 : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_decad12; + +ARCHITECTURE VBE OF ram_sense_decad12 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_decad12" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_sense_decad2.ap b/pdks/symbolic/nramlib/cells/ram_sense_decad2.ap new file mode 100644 index 000000000..d940a4d88 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_decad2.ap @@ -0,0 +1,182 @@ +V ALLIANCE : 6 +H ram_sense_decad2,P,23/4/2016,100 +A 0,0,34000,10000 +S 31600,500,31600,2500,200,17onymous_,UP,NTRANS +S 29200,500,29200,2500,200,16onymous_,UP,NTRANS +S 28600,5700,28600,9300,600,15onymous_,UP,PDIF +S 30400,5500,30400,9500,200,14onymous_,UP,PTRANS +S 29800,5700,29800,9300,600,13onymous_,UP,PDIF +S 27200,5700,27200,9300,1000,2nonymous_,UP,PDIF +S 0,-150,0,10150,2400,1nonymous_,UP,ALU3 +S 25000,-150,25000,10150,2400,0nonymous_,UP,ALU3 +S 100,600,33900,600,1200,vss,RIGHT,CALU1 +S 31600,5500,31600,9500,200,12onymous_,UP,PTRANS +S 32200,5700,32200,9300,600,11onymous_,UP,PDIF +S 31000,5700,31000,9300,600,10onymous_,UP,PDIF +S 29200,5500,29200,9500,200,9nonymous_,UP,PTRANS +S 30400,4000,33200,4000,600,8nonymous_,RIGHT,POLY +S 25200,4000,27200,4000,600,7nonymous_,RIGHT,POLY +S 22100,4000,23300,4000,300,6nonymous_,RIGHT,ALU1 +S 27200,6100,27200,8900,300,5nonymous_,UP,ALU1 +S 27200,1100,27200,1900,300,4nonymous_,UP,ALU1 +S 27200,700,27200,2300,1000,3nonymous_,UP,NDIF +S 100,9400,33900,9400,1200,vdd,RIGHT,CALU1 +S 32200,1100,32200,1900,300,32onymous_,UP,ALU1 +S 31000,2100,31000,7900,300,31onymous_,UP,ALU1 +S 29700,4000,30900,4000,300,30onymous_,RIGHT,ALU1 +S 29200,2800,29200,5200,200,29onymous_,UP,POLY +S 31600,2800,31600,5200,200,28onymous_,UP,POLY +S 30400,2800,30400,5200,200,27onymous_,UP,POLY +S 28000,2800,28000,5200,200,26onymous_,UP,POLY +S 28000,4000,29800,4000,600,25onymous_,RIGHT,POLY +S 28000,5500,28000,9500,200,24onymous_,UP,PTRANS +S 31000,700,31000,2300,600,23onymous_,UP,NDIF +S 28600,700,28600,2300,600,22onymous_,UP,NDIF +S 32200,700,32200,2300,600,21onymous_,UP,NDIF +S 29800,700,29800,2300,600,20onymous_,UP,NDIF +S 30400,500,30400,2500,200,19onymous_,UP,NTRANS +S 28000,500,28000,2500,200,18onymous_,UP,NTRANS +S 32200,6100,32200,8900,300,33onymous_,UP,ALU1 +S 28600,2100,28600,7900,300,34onymous_,UP,ALU1 +S 29800,1100,29800,1900,300,35onymous_,UP,ALU1 +S 29800,6100,29800,8900,300,36onymous_,UP,ALU1 +S 22850,4000,24550,4000,600,37onymous_,RIGHT,ALU2 +S 26400,5500,26400,9500,200,38onymous_,UP,PTRANS +S 25800,5700,25800,9300,600,39onymous_,UP,PDIF +S 25200,5500,25200,9500,200,40onymous_,UP,PTRANS +S 22800,5500,22800,9500,200,41onymous_,UP,PTRANS +S 22200,5700,22200,9300,600,42onymous_,UP,PDIF +S 23400,5700,23400,9300,600,43onymous_,UP,PDIF +S 24600,5700,24600,9300,600,44onymous_,UP,PDIF +S 24000,5500,24000,9500,200,45onymous_,UP,PTRANS +S 21000,5680,21000,9320,600,66onymous_,UP,NTIE +S 24600,1100,24600,1900,300,65onymous_,UP,ALU1 +S 22200,6100,22200,8900,300,64onymous_,UP,ALU1 +S 22200,1100,22200,1900,300,63onymous_,UP,ALU1 +S 25800,2100,25800,7900,300,62onymous_,UP,ALU1 +S 24600,6100,24600,8900,300,61onymous_,UP,ALU1 +S 23400,2100,23400,7900,300,60onymous_,UP,ALU1 +S 24700,4000,25700,4000,300,59onymous_,RIGHT,ALU1 +S 24000,2800,24000,5200,200,58onymous_,UP,POLY +S 25200,2800,25200,5200,200,57onymous_,UP,POLY +S 26400,2800,26400,5200,200,56onymous_,UP,POLY +S 22800,2800,22800,5200,200,55onymous_,UP,POLY +S 22800,4000,24600,4000,600,54onymous_,RIGHT,POLY +S 25800,700,25800,2300,600,53onymous_,UP,NDIF +S 23400,700,23400,2300,600,52onymous_,UP,NDIF +S 24600,700,24600,2300,600,51onymous_,UP,NDIF +S 22200,700,22200,2300,600,50onymous_,UP,NDIF +S 25200,500,25200,2500,200,49onymous_,UP,NTRANS +S 26400,500,26400,2500,200,48onymous_,UP,NTRANS +S 24000,500,24000,2500,200,47onymous_,UP,NTRANS +S 22800,500,22800,2500,200,46onymous_,UP,NTRANS +S -600,7800,34600,7800,6000,78onymous_,RIGHT,NWELL +S 33400,1100,33400,2900,300,77onymous_,UP,ALU1 +S 33400,6100,33400,8900,300,76onymous_,UP,ALU1 +S 33400,680,33400,3320,600,75onymous_,UP,PTIE +S 33400,5680,33400,9320,600,74onymous_,UP,NTIE +S 600,6100,600,8900,300,73onymous_,UP,ALU1 +S 21000,680,21000,3320,600,67onymous_,UP,PTIE +S 21000,1100,21000,2900,300,68onymous_,UP,ALU1 +S 21000,6100,21000,8900,300,69onymous_,UP,ALU1 +S 600,5680,600,9320,600,70onymous_,UP,NTIE +S 600,680,600,3320,600,71onymous_,UP,PTIE +S 600,1100,600,2900,300,72onymous_,UP,ALU1 +S 20850,4000,22150,4000,600,79onymous_,RIGHT,ALU2 +S 25850,4000,27150,4000,600,80onymous_,RIGHT,ALU2 +S 29850,4000,31150,4000,600,81onymous_,RIGHT,ALU2 +S 31850,4000,33150,4000,600,82onymous_,RIGHT,ALU2 +S 27850,4000,29150,4000,600,83onymous_,RIGHT,ALU2 +S 21050,4000,32950,4000,300,84onymous_,RIGHT,TALU2 +S 27000,4100,27000,4900,300,85onymous_,UP,ALU1 +S 33000,4100,33000,4900,300,86onymous_,UP,ALU1 +S 23000,3850,23000,4150,400,nad4x,UP,CALU3 +S 22000,3850,22000,4150,400,ad4x,UP,CALU3 +S 31000,3850,31000,4150,400,nad3x,UP,CALU3 +S 28000,3850,28000,4150,400,ad3x,UP,CALU3 +S 27000,3850,27000,4150,400,ad4,UP,CALU3 +S 33000,3850,33000,4150,400,ad3,UP,CALU3 +V 27000,4000,CONT_POLY,87onymous_ +V 27000,4000,CONT_VIA,88onymous_ +V 27000,4000,CONT_VIA2,89onymous_ +V 27200,6000,CONT_DIF_P,90onymous_ +V 27200,8000,CONT_DIF_P,91onymous_ +V 27200,9000,CONT_DIF_P,92onymous_ +V 27200,7000,CONT_DIF_P,93onymous_ +V 27200,2000,CONT_DIF_N,94onymous_ +V 27200,1000,CONT_DIF_N,95onymous_ +V 28600,4000,CONT_VIA,96onymous_ +V 28000,4000,CONT_VIA2,97onymous_ +V 33000,4000,CONT_POLY,98onymous_ +V 33000,4000,CONT_VIA,99onymous_ +V 33000,4000,CONT_VIA2,100nymous_ +V 31000,4000,CONT_VIA,101nymous_ +V 31000,4000,CONT_VIA2,102nymous_ +V 32200,7000,CONT_DIF_P,103nymous_ +V 28600,7000,CONT_DIF_P,104nymous_ +V 32200,9000,CONT_DIF_P,105nymous_ +V 28600,6000,CONT_DIF_P,106nymous_ +V 31000,6000,CONT_DIF_P,107nymous_ +V 31000,7000,CONT_DIF_P,108nymous_ +V 29800,9000,CONT_DIF_P,109nymous_ +V 32200,6000,CONT_DIF_P,110nymous_ +V 32200,8000,CONT_DIF_P,111nymous_ +V 29800,6000,CONT_DIF_P,112nymous_ +V 29800,7000,CONT_DIF_P,113nymous_ +V 28600,8000,CONT_DIF_P,114nymous_ +V 29800,8000,CONT_DIF_P,115nymous_ +V 31000,8000,CONT_DIF_P,116nymous_ +V 31000,2000,CONT_DIF_N,117nymous_ +V 32200,1000,CONT_DIF_N,118nymous_ +V 29800,2000,CONT_DIF_N,119nymous_ +V 28600,2000,CONT_DIF_N,120nymous_ +V 32200,2000,CONT_DIF_N,121nymous_ +V 29800,1000,CONT_DIF_N,122nymous_ +V 21000,3000,CONT_BODY_P,152nymous_ +V 21000,2000,CONT_BODY_P,151nymous_ +V 21000,6000,CONT_BODY_N,150nymous_ +V 21000,7000,CONT_BODY_N,149nymous_ +V 21000,8000,CONT_BODY_N,148nymous_ +V 21000,9000,CONT_BODY_N,147nymous_ +V 24400,4000,CONT_VIA,146nymous_ +V 24400,4000,CONT_POLY,145nymous_ +V 25800,2000,CONT_DIF_N,144nymous_ +V 22200,2000,CONT_DIF_N,143nymous_ +V 22200,1000,CONT_DIF_N,142nymous_ +V 33400,1000,CONT_BODY_P,169nymous_ +V 33400,3000,CONT_BODY_P,168nymous_ +V 33400,2000,CONT_BODY_P,167nymous_ +V 33400,6000,CONT_BODY_N,166nymous_ +V 33400,7000,CONT_BODY_N,165nymous_ +V 33400,8000,CONT_BODY_N,164nymous_ +V 33400,9000,CONT_BODY_N,163nymous_ +V 22000,4000,CONT_VIA2,162nymous_ +V 22000,4000,CONT_VIA,161nymous_ +V 600,1000,CONT_BODY_P,160nymous_ +V 600,3000,CONT_BODY_P,159nymous_ +V 600,2000,CONT_BODY_P,158nymous_ +V 600,9000,CONT_BODY_N,157nymous_ +V 600,6000,CONT_BODY_N,156nymous_ +V 600,7000,CONT_BODY_N,155nymous_ +V 600,8000,CONT_BODY_N,154nymous_ +V 21000,1000,CONT_BODY_P,153nymous_ +V 29600,4000,CONT_POLY,123nymous_ +V 23000,4000,CONT_VIA2,124nymous_ +V 22200,8000,CONT_DIF_P,125nymous_ +V 22200,9000,CONT_DIF_P,126nymous_ +V 22200,7000,CONT_DIF_P,127nymous_ +V 22200,6000,CONT_DIF_P,128nymous_ +V 24600,7000,CONT_DIF_P,129nymous_ +V 25800,6000,CONT_DIF_P,130nymous_ +V 25800,7000,CONT_DIF_P,131nymous_ +V 24600,9000,CONT_DIF_P,132nymous_ +V 24600,6000,CONT_DIF_P,133nymous_ +V 23400,7000,CONT_DIF_P,134nymous_ +V 23400,6000,CONT_DIF_P,135nymous_ +V 23400,8000,CONT_DIF_P,136nymous_ +V 24600,8000,CONT_DIF_P,137nymous_ +V 25800,8000,CONT_DIF_P,138nymous_ +V 24600,1000,CONT_DIF_N,139nymous_ +V 23400,2000,CONT_DIF_N,140nymous_ +V 24600,2000,CONT_DIF_N,141nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_sense_decad2.vbe b/pdks/symbolic/nramlib/cells/ram_sense_decad2.vbe new file mode 100644 index 000000000..1c8e50604 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_decad2.vbe @@ -0,0 +1,21 @@ +ENTITY ram_sense_decad2 IS +PORT ( + ad3 : in BIT; + ad4 : in BIT; + ad3x : out BIT; + nad3x : out BIT; + ad4x : out BIT; + nad4x : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_decad2; + +ARCHITECTURE VBE OF ram_sense_decad2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_decad2" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_sense_decad3.ap b/pdks/symbolic/nramlib/cells/ram_sense_decad3.ap new file mode 100644 index 000000000..d42f42c15 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_decad3.ap @@ -0,0 +1,267 @@ +V ALLIANCE : 6 +H ram_sense_decad3,P,23/4/2016,100 +A 0,0,34000,10000 +S 31600,500,31600,2500,200,17onymous_,UP,NTRANS +S 29200,500,29200,2500,200,16onymous_,UP,NTRANS +S 28600,5700,28600,9300,600,15onymous_,UP,PDIF +S 30400,5500,30400,9500,200,14onymous_,UP,PTRANS +S 29800,5700,29800,9300,600,13onymous_,UP,PDIF +S 31600,5500,31600,9500,200,12onymous_,UP,PTRANS +S 32200,5700,32200,9300,600,11onymous_,UP,PDIF +S 31000,5700,31000,9300,600,10onymous_,UP,PDIF +S 100,600,33900,600,1200,vss,RIGHT,CALU1 +S 29200,5500,29200,9500,200,9nonymous_,UP,PTRANS +S 30400,4000,33200,4000,600,8nonymous_,RIGHT,POLY +S 25200,4000,27200,4000,600,7nonymous_,RIGHT,POLY +S 22100,4000,23300,4000,300,6nonymous_,RIGHT,ALU1 +S 27200,6100,27200,8900,300,5nonymous_,UP,ALU1 +S 27200,1100,27200,1900,300,4nonymous_,UP,ALU1 +S 27200,700,27200,2300,1000,3nonymous_,UP,NDIF +S 27200,5700,27200,9300,1000,2nonymous_,UP,PDIF +S 0,-150,0,10150,2400,1nonymous_,UP,ALU3 +S 25000,-150,25000,10150,2400,0nonymous_,UP,ALU3 +S 100,9400,33900,9400,1200,vdd,RIGHT,CALU1 +S 29200,2800,29200,5200,200,29onymous_,UP,POLY +S 31600,2800,31600,5200,200,28onymous_,UP,POLY +S 30400,2800,30400,5200,200,27onymous_,UP,POLY +S 28000,2800,28000,5200,200,26onymous_,UP,POLY +S 28000,4000,29800,4000,600,25onymous_,RIGHT,POLY +S 28000,5500,28000,9500,200,24onymous_,UP,PTRANS +S 31000,700,31000,2300,600,23onymous_,UP,NDIF +S 28600,700,28600,2300,600,22onymous_,UP,NDIF +S 32200,700,32200,2300,600,21onymous_,UP,NDIF +S 29800,700,29800,2300,600,20onymous_,UP,NDIF +S 30400,500,30400,2500,200,19onymous_,UP,NTRANS +S 28000,500,28000,2500,200,18onymous_,UP,NTRANS +S 29700,4000,30900,4000,300,30onymous_,RIGHT,ALU1 +S 31000,2100,31000,7900,300,31onymous_,UP,ALU1 +S 32200,1100,32200,1900,300,32onymous_,UP,ALU1 +S 32200,6100,32200,8900,300,33onymous_,UP,ALU1 +S 28600,2100,28600,7900,300,34onymous_,UP,ALU1 +S 29800,1100,29800,1900,300,35onymous_,UP,ALU1 +S 29800,6100,29800,8900,300,36onymous_,UP,ALU1 +S 22850,4000,24550,4000,600,37onymous_,RIGHT,ALU2 +S 26400,5500,26400,9500,200,38onymous_,UP,PTRANS +S 25800,5700,25800,9300,600,39onymous_,UP,PDIF +S 25200,5500,25200,9500,200,40onymous_,UP,PTRANS +S 22800,5500,22800,9500,200,41onymous_,UP,PTRANS +S 22200,5700,22200,9300,600,42onymous_,UP,PDIF +S 23400,5700,23400,9300,600,43onymous_,UP,PDIF +S 24600,5700,24600,9300,600,44onymous_,UP,PDIF +S 24000,5500,24000,9500,200,45onymous_,UP,PTRANS +S 21000,5680,21000,9320,600,66onymous_,UP,NTIE +S 24600,1100,24600,1900,300,65onymous_,UP,ALU1 +S 22200,6100,22200,8900,300,64onymous_,UP,ALU1 +S 22200,1100,22200,1900,300,63onymous_,UP,ALU1 +S 25800,2100,25800,7900,300,62onymous_,UP,ALU1 +S 24600,6100,24600,8900,300,61onymous_,UP,ALU1 +S 23400,2100,23400,7900,300,60onymous_,UP,ALU1 +S 24700,4000,25700,4000,300,59onymous_,RIGHT,ALU1 +S 24000,2800,24000,5200,200,58onymous_,UP,POLY +S 25200,2800,25200,5200,200,57onymous_,UP,POLY +S 26400,2800,26400,5200,200,56onymous_,UP,POLY +S 22800,2800,22800,5200,200,55onymous_,UP,POLY +S 22800,4000,24600,4000,600,54onymous_,RIGHT,POLY +S 25800,700,25800,2300,600,53onymous_,UP,NDIF +S 23400,700,23400,2300,600,52onymous_,UP,NDIF +S 24600,700,24600,2300,600,51onymous_,UP,NDIF +S 22200,700,22200,2300,600,50onymous_,UP,NDIF +S 25200,500,25200,2500,200,49onymous_,UP,NTRANS +S 26400,500,26400,2500,200,48onymous_,UP,NTRANS +S 24000,500,24000,2500,200,47onymous_,UP,NTRANS +S 22800,500,22800,2500,200,46onymous_,UP,NTRANS +S 18600,5700,18600,9300,600,78onymous_,UP,PDIF +S 19200,5500,19200,9500,200,77onymous_,UP,PTRANS +S 19800,5700,19800,9300,600,76onymous_,UP,PDIF +S 16800,5500,16800,9500,200,75onymous_,UP,PTRANS +S 17400,5700,17400,9300,600,74onymous_,UP,PDIF +S 16200,5700,16200,9300,600,73onymous_,UP,PDIF +S 15000,5700,15000,9300,600,72onymous_,UP,PDIF +S 15600,5500,15600,9500,200,71onymous_,UP,PTRANS +S 18000,5500,18000,9500,200,70onymous_,UP,PTRANS +S 21000,680,21000,3320,600,67onymous_,UP,PTIE +S 21000,1100,21000,2900,300,68onymous_,UP,ALU1 +S 21000,6100,21000,8900,300,69onymous_,UP,ALU1 +S 16800,500,16800,2500,200,79onymous_,UP,NTRANS +S 19200,500,19200,2500,200,80onymous_,UP,NTRANS +S 18000,500,18000,2500,200,81onymous_,UP,NTRANS +S 15600,500,15600,2500,200,82onymous_,UP,NTRANS +S 17400,700,17400,2300,600,83onymous_,UP,NDIF +S 19800,700,19800,2300,600,84onymous_,UP,NDIF +S 16200,700,16200,2300,600,85onymous_,UP,NDIF +S 18600,700,18600,2300,600,86onymous_,UP,NDIF +S 15000,700,15000,2300,600,87onymous_,UP,NDIF +S 15600,4000,17200,4000,600,88onymous_,RIGHT,POLY +S 18000,4000,20200,4000,600,89onymous_,RIGHT,POLY +S 19200,2800,19200,5200,200,90onymous_,UP,POLY +S 18000,2800,18000,5200,200,91onymous_,UP,POLY +S 16800,2800,16800,5200,200,92onymous_,UP,POLY +S 15600,2800,15600,5200,200,93onymous_,UP,POLY +S 17300,4000,18500,4000,300,94onymous_,RIGHT,ALU1 +S 19800,1100,19800,1900,300,95onymous_,UP,ALU1 +S 15000,1100,15000,1900,300,96onymous_,UP,ALU1 +S 15000,6100,15000,8900,300,97onymous_,UP,ALU1 +S 16200,2100,16200,7900,300,98onymous_,UP,ALU1 +S 17400,6100,17400,8900,300,99onymous_,UP,ALU1 +S 18600,2100,18600,7900,300,100nymous_,UP,ALU1 +S 17400,1100,17400,1900,300,101nymous_,UP,ALU1 +S 19800,6100,19800,8900,300,102nymous_,UP,ALU1 +S 13800,5680,13800,9320,600,103nymous_,UP,NTIE +S 13800,680,13800,3320,600,104nymous_,UP,PTIE +S 13800,6100,13800,8900,300,105nymous_,UP,ALU1 +S 13800,1100,13800,2900,300,106nymous_,UP,ALU1 +S 600,5680,600,9320,600,107nymous_,UP,NTIE +S 600,680,600,3320,600,108nymous_,UP,PTIE +S 600,1100,600,2900,300,109nymous_,UP,ALU1 +S 600,6100,600,8900,300,110nymous_,UP,ALU1 +S 33400,5680,33400,9320,600,111nymous_,UP,NTIE +S 33400,680,33400,3320,600,112nymous_,UP,PTIE +S 33400,6100,33400,8900,300,113nymous_,UP,ALU1 +S 33400,1100,33400,2900,300,114nymous_,UP,ALU1 +S -600,7800,34600,7800,6000,115nymous_,RIGHT,NWELL +S 31850,4000,33150,4000,600,116nymous_,RIGHT,ALU2 +S 29850,4000,31150,4000,600,117nymous_,RIGHT,ALU2 +S 27850,4000,29150,4000,600,118nymous_,RIGHT,ALU2 +S 25850,4000,27150,4000,600,119nymous_,RIGHT,ALU2 +S 14850,4000,16150,4000,600,120nymous_,RIGHT,ALU2 +S 16850,4000,18150,4000,600,121nymous_,RIGHT,ALU2 +S 18850,4000,20150,4000,600,122nymous_,RIGHT,ALU2 +S 20850,4000,22150,4000,600,123nymous_,RIGHT,ALU2 +S 15050,4000,32950,4000,300,124nymous_,RIGHT,TALU2 +S 20000,4100,20000,4900,300,125nymous_,UP,ALU1 +S 27000,4100,27000,4900,300,126nymous_,UP,ALU1 +S 33000,4100,33000,4900,300,127nymous_,UP,ALU1 +S 18000,3850,18000,4150,400,nad5x,UP,CALU3 +S 16000,3850,16000,4150,400,ad5x,UP,CALU3 +S 23000,3850,23000,4150,400,nad4x,UP,CALU3 +S 22000,3850,22000,4150,400,ad4x,UP,CALU3 +S 31000,3850,31000,4150,400,nad3x,UP,CALU3 +S 28000,3850,28000,4150,400,ad3x,UP,CALU3 +S 20000,3850,20000,4150,400,ad5,UP,CALU3 +S 27000,3850,27000,4150,400,ad4,UP,CALU3 +S 33000,3850,33000,4150,400,ad3,UP,CALU3 +V 31000,7000,CONT_DIF_P,149nymous_ +V 31000,6000,CONT_DIF_P,148nymous_ +V 28600,6000,CONT_DIF_P,147nymous_ +V 32200,9000,CONT_DIF_P,146nymous_ +V 28600,7000,CONT_DIF_P,145nymous_ +V 32200,7000,CONT_DIF_P,144nymous_ +V 31000,4000,CONT_VIA2,143nymous_ +V 31000,4000,CONT_VIA,142nymous_ +V 33000,4000,CONT_VIA2,141nymous_ +V 33000,4000,CONT_VIA,140nymous_ +V 33000,4000,CONT_POLY,139nymous_ +V 28000,4000,CONT_VIA2,138nymous_ +V 28600,4000,CONT_VIA,137nymous_ +V 27200,1000,CONT_DIF_N,136nymous_ +V 27200,2000,CONT_DIF_N,135nymous_ +V 27200,7000,CONT_DIF_P,134nymous_ +V 27200,9000,CONT_DIF_P,133nymous_ +V 23400,7000,CONT_DIF_P,175nymous_ +V 24600,6000,CONT_DIF_P,174nymous_ +V 24600,9000,CONT_DIF_P,173nymous_ +V 25800,7000,CONT_DIF_P,172nymous_ +V 25800,6000,CONT_DIF_P,171nymous_ +V 24600,7000,CONT_DIF_P,170nymous_ +V 22200,6000,CONT_DIF_P,169nymous_ +V 22200,7000,CONT_DIF_P,168nymous_ +V 22200,9000,CONT_DIF_P,167nymous_ +V 22200,8000,CONT_DIF_P,166nymous_ +V 23000,4000,CONT_VIA2,165nymous_ +V 29600,4000,CONT_POLY,164nymous_ +V 29800,1000,CONT_DIF_N,163nymous_ +V 32200,2000,CONT_DIF_N,162nymous_ +V 28600,2000,CONT_DIF_N,161nymous_ +V 29800,2000,CONT_DIF_N,160nymous_ +V 32200,1000,CONT_DIF_N,159nymous_ +V 31000,2000,CONT_DIF_N,158nymous_ +V 31000,8000,CONT_DIF_P,157nymous_ +V 29800,8000,CONT_DIF_P,156nymous_ +V 28600,8000,CONT_DIF_P,155nymous_ +V 29800,7000,CONT_DIF_P,154nymous_ +V 29800,6000,CONT_DIF_P,153nymous_ +V 32200,8000,CONT_DIF_P,152nymous_ +V 32200,6000,CONT_DIF_P,151nymous_ +V 29800,9000,CONT_DIF_P,150nymous_ +V 27000,4000,CONT_POLY,128nymous_ +V 27000,4000,CONT_VIA,129nymous_ +V 27000,4000,CONT_VIA2,130nymous_ +V 27200,6000,CONT_DIF_P,131nymous_ +V 27200,8000,CONT_DIF_P,132nymous_ +V 23400,6000,CONT_DIF_P,176nymous_ +V 23400,8000,CONT_DIF_P,177nymous_ +V 24600,8000,CONT_DIF_P,178nymous_ +V 25800,8000,CONT_DIF_P,179nymous_ +V 24600,1000,CONT_DIF_N,180nymous_ +V 23400,2000,CONT_DIF_N,181nymous_ +V 24600,2000,CONT_DIF_N,182nymous_ +V 22200,1000,CONT_DIF_N,183nymous_ +V 22200,2000,CONT_DIF_N,184nymous_ +V 25800,2000,CONT_DIF_N,185nymous_ +V 24400,4000,CONT_POLY,186nymous_ +V 24400,4000,CONT_VIA,187nymous_ +V 21000,9000,CONT_BODY_N,188nymous_ +V 21000,8000,CONT_BODY_N,189nymous_ +V 21000,7000,CONT_BODY_N,190nymous_ +V 21000,6000,CONT_BODY_N,191nymous_ +V 21000,2000,CONT_BODY_P,192nymous_ +V 21000,3000,CONT_BODY_P,193nymous_ +V 21000,1000,CONT_BODY_P,194nymous_ +V 20000,4000,CONT_POLY,195nymous_ +V 20000,4000,CONT_VIA,196nymous_ +V 20000,4000,CONT_VIA2,197nymous_ +V 18000,4000,CONT_VIA,198nymous_ +V 18000,4000,CONT_VIA2,199nymous_ +V 16000,4000,CONT_VIA,200nymous_ +V 16000,4000,CONT_VIA2,201nymous_ +V 18600,6000,CONT_DIF_P,202nymous_ +V 18600,7000,CONT_DIF_P,203nymous_ +V 15000,8000,CONT_DIF_P,204nymous_ +V 15000,9000,CONT_DIF_P,205nymous_ +V 15000,7000,CONT_DIF_P,206nymous_ +V 16200,6000,CONT_DIF_P,207nymous_ +V 16200,8000,CONT_DIF_P,208nymous_ +V 17400,8000,CONT_DIF_P,209nymous_ +V 19800,8000,CONT_DIF_P,210nymous_ +V 19800,7000,CONT_DIF_P,211nymous_ +V 15000,6000,CONT_DIF_P,212nymous_ +V 19800,6000,CONT_DIF_P,213nymous_ +V 17400,7000,CONT_DIF_P,214nymous_ +V 18600,8000,CONT_DIF_P,215nymous_ +V 19800,9000,CONT_DIF_P,216nymous_ +V 17400,9000,CONT_DIF_P,217nymous_ +V 17400,6000,CONT_DIF_P,218nymous_ +V 16200,7000,CONT_DIF_P,219nymous_ +V 17400,1000,CONT_DIF_N,220nymous_ +V 17400,2000,CONT_DIF_N,221nymous_ +V 15000,1000,CONT_DIF_N,222nymous_ +V 15000,2000,CONT_DIF_N,223nymous_ +V 19800,2000,CONT_DIF_N,224nymous_ +V 18600,2000,CONT_DIF_N,225nymous_ +V 19800,1000,CONT_DIF_N,226nymous_ +V 16200,2000,CONT_DIF_N,227nymous_ +V 17200,4000,CONT_POLY,228nymous_ +V 13800,6000,CONT_BODY_N,229nymous_ +V 13800,7000,CONT_BODY_N,230nymous_ +V 13800,8000,CONT_BODY_N,231nymous_ +V 13800,9000,CONT_BODY_N,232nymous_ +V 13800,1000,CONT_BODY_P,233nymous_ +V 13800,3000,CONT_BODY_P,234nymous_ +V 13800,2000,CONT_BODY_P,235nymous_ +V 600,8000,CONT_BODY_N,236nymous_ +V 600,7000,CONT_BODY_N,237nymous_ +V 600,6000,CONT_BODY_N,238nymous_ +V 600,9000,CONT_BODY_N,239nymous_ +V 600,2000,CONT_BODY_P,240nymous_ +V 600,3000,CONT_BODY_P,241nymous_ +V 600,1000,CONT_BODY_P,242nymous_ +V 22000,4000,CONT_VIA,243nymous_ +V 22000,4000,CONT_VIA2,244nymous_ +V 33400,9000,CONT_BODY_N,245nymous_ +V 33400,8000,CONT_BODY_N,246nymous_ +V 33400,7000,CONT_BODY_N,247nymous_ +V 33400,6000,CONT_BODY_N,248nymous_ +V 33400,2000,CONT_BODY_P,249nymous_ +V 33400,3000,CONT_BODY_P,250nymous_ +V 33400,1000,CONT_BODY_P,251nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_sense_decad3.vbe b/pdks/symbolic/nramlib/cells/ram_sense_decad3.vbe new file mode 100644 index 000000000..c8430f0ba --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_decad3.vbe @@ -0,0 +1,24 @@ +ENTITY ram_sense_decad3 IS +PORT ( + ad3 : in BIT; + ad4 : in BIT; + ad5 : in BIT; + ad3x : out BIT; + nad3x : out BIT; + ad4x : out BIT; + nad4x : out BIT; + ad5x : out BIT; + nad5x : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_decad3; + +ARCHITECTURE VBE OF ram_sense_decad3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_decad3" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_sense_decad4.ap b/pdks/symbolic/nramlib/cells/ram_sense_decad4.ap new file mode 100644 index 000000000..940012fae --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_decad4.ap @@ -0,0 +1,341 @@ +V ALLIANCE : 6 +H ram_sense_decad4,P,23/4/2016,100 +A 0,0,34000,10000 +S 22100,4000,23300,4000,300,7nonymous_,RIGHT,ALU1 +S 25200,4000,27200,4000,600,8nonymous_,RIGHT,POLY +S 30400,4000,33200,4000,600,9nonymous_,RIGHT,POLY +S 29200,5500,29200,9500,200,10onymous_,UP,PTRANS +S 31000,5700,31000,9300,600,11onymous_,UP,PDIF +S 32200,5700,32200,9300,600,12onymous_,UP,PDIF +S 31600,5500,31600,9500,200,13onymous_,UP,PTRANS +S 29800,5700,29800,9300,600,14onymous_,UP,PDIF +S 30400,5500,30400,9500,200,15onymous_,UP,PTRANS +S 28600,5700,28600,9300,600,16onymous_,UP,PDIF +S 29200,500,29200,2500,200,17onymous_,UP,NTRANS +S 100,9400,33900,9400,1200,vdd,RIGHT,CALU1 +S 100,600,33900,600,1200,vss,RIGHT,CALU1 +S 25000,-150,25000,10150,2400,0nonymous_,UP,ALU3 +S 0,-150,0,10150,2400,1nonymous_,UP,ALU3 +S 9050,4000,32950,4000,300,2nonymous_,RIGHT,TALU2 +S 27200,5700,27200,9300,1000,3nonymous_,UP,PDIF +S 27200,700,27200,2300,1000,4nonymous_,UP,NDIF +S 27200,1100,27200,1900,300,5nonymous_,UP,ALU1 +S 27200,6100,27200,8900,300,6nonymous_,UP,ALU1 +S 22850,4000,24550,4000,600,38onymous_,RIGHT,ALU2 +S 29800,6100,29800,8900,300,37onymous_,UP,ALU1 +S 29800,1100,29800,1900,300,36onymous_,UP,ALU1 +S 28600,2100,28600,7900,300,35onymous_,UP,ALU1 +S 32200,6100,32200,8900,300,34onymous_,UP,ALU1 +S 32200,1100,32200,1900,300,33onymous_,UP,ALU1 +S 31000,2100,31000,7900,300,32onymous_,UP,ALU1 +S 29700,4000,30900,4000,300,31onymous_,RIGHT,ALU1 +S 29200,2800,29200,5200,200,30onymous_,UP,POLY +S 31600,2800,31600,5200,200,29onymous_,UP,POLY +S 30400,2800,30400,5200,200,28onymous_,UP,POLY +S 28000,2800,28000,5200,200,27onymous_,UP,POLY +S 31600,500,31600,2500,200,18onymous_,UP,NTRANS +S 28000,500,28000,2500,200,19onymous_,UP,NTRANS +S 30400,500,30400,2500,200,20onymous_,UP,NTRANS +S 29800,700,29800,2300,600,21onymous_,UP,NDIF +S 32200,700,32200,2300,600,22onymous_,UP,NDIF +S 28600,700,28600,2300,600,23onymous_,UP,NDIF +S 31000,700,31000,2300,600,24onymous_,UP,NDIF +S 28000,5500,28000,9500,200,25onymous_,UP,PTRANS +S 28000,4000,29800,4000,600,26onymous_,RIGHT,POLY +S 26400,5500,26400,9500,200,39onymous_,UP,PTRANS +S 25800,5700,25800,9300,600,40onymous_,UP,PDIF +S 25200,5500,25200,9500,200,41onymous_,UP,PTRANS +S 22800,5500,22800,9500,200,42onymous_,UP,PTRANS +S 22200,5700,22200,9300,600,43onymous_,UP,PDIF +S 23400,5700,23400,9300,600,44onymous_,UP,PDIF +S 24600,5700,24600,9300,600,45onymous_,UP,PDIF +S 24000,5500,24000,9500,200,46onymous_,UP,PTRANS +S 22800,500,22800,2500,200,47onymous_,UP,NTRANS +S 24000,500,24000,2500,200,48onymous_,UP,NTRANS +S 26400,500,26400,2500,200,49onymous_,UP,NTRANS +S 25200,500,25200,2500,200,50onymous_,UP,NTRANS +S 22200,700,22200,2300,600,51onymous_,UP,NDIF +S 24600,700,24600,2300,600,52onymous_,UP,NDIF +S 23400,700,23400,2300,600,53onymous_,UP,NDIF +S 25800,700,25800,2300,600,54onymous_,UP,NDIF +S 22800,4000,24600,4000,600,55onymous_,RIGHT,POLY +S 22800,2800,22800,5200,200,56onymous_,UP,POLY +S 26400,2800,26400,5200,200,57onymous_,UP,POLY +S 25200,2800,25200,5200,200,58onymous_,UP,POLY +S 24000,2800,24000,5200,200,59onymous_,UP,POLY +S 24700,4000,25700,4000,300,60onymous_,RIGHT,ALU1 +S 23400,2100,23400,7900,300,61onymous_,UP,ALU1 +S 24600,6100,24600,8900,300,62onymous_,UP,ALU1 +S 25800,2100,25800,7900,300,63onymous_,UP,ALU1 +S 22200,1100,22200,1900,300,64onymous_,UP,ALU1 +S 22200,6100,22200,8900,300,65onymous_,UP,ALU1 +S 24600,1100,24600,1900,300,66onymous_,UP,ALU1 +S 21000,5680,21000,9320,600,67onymous_,UP,NTIE +S 21000,680,21000,3320,600,68onymous_,UP,PTIE +S 21000,1100,21000,2900,300,69onymous_,UP,ALU1 +S 21000,6100,21000,8900,300,70onymous_,UP,ALU1 +S 18000,5500,18000,9500,200,71onymous_,UP,PTRANS +S 15600,5500,15600,9500,200,72onymous_,UP,PTRANS +S 15000,5700,15000,9300,600,73onymous_,UP,PDIF +S 16200,5700,16200,9300,600,74onymous_,UP,PDIF +S 17400,5700,17400,9300,600,75onymous_,UP,PDIF +S 16800,5500,16800,9500,200,76onymous_,UP,PTRANS +S 19800,5700,19800,9300,600,77onymous_,UP,PDIF +S 19200,5500,19200,9500,200,78onymous_,UP,PTRANS +S 18600,5700,18600,9300,600,79onymous_,UP,PDIF +S 16800,500,16800,2500,200,80onymous_,UP,NTRANS +S 19200,500,19200,2500,200,81onymous_,UP,NTRANS +S 18000,500,18000,2500,200,82onymous_,UP,NTRANS +S 15600,500,15600,2500,200,83onymous_,UP,NTRANS +S 17400,700,17400,2300,600,84onymous_,UP,NDIF +S 19800,700,19800,2300,600,85onymous_,UP,NDIF +S 16200,700,16200,2300,600,86onymous_,UP,NDIF +S 18600,700,18600,2300,600,87onymous_,UP,NDIF +S 15000,700,15000,2300,600,88onymous_,UP,NDIF +S 15600,4000,17200,4000,600,89onymous_,RIGHT,POLY +S 18000,4000,20200,4000,600,90onymous_,RIGHT,POLY +S 19200,2800,19200,5200,200,91onymous_,UP,POLY +S 18000,2800,18000,5200,200,92onymous_,UP,POLY +S 16800,2800,16800,5200,200,93onymous_,UP,POLY +S 15600,2800,15600,5200,200,94onymous_,UP,POLY +S 17300,4000,18500,4000,300,95onymous_,RIGHT,ALU1 +S 19800,1100,19800,1900,300,96onymous_,UP,ALU1 +S 15000,1100,15000,1900,300,97onymous_,UP,ALU1 +S 15000,6100,15000,8900,300,98onymous_,UP,ALU1 +S 16200,2100,16200,7900,300,99onymous_,UP,ALU1 +S 17400,6100,17400,8900,300,100nymous_,UP,ALU1 +S 18600,2100,18600,7900,300,101nymous_,UP,ALU1 +S 17400,1100,17400,1900,300,102nymous_,UP,ALU1 +S 19800,6100,19800,8900,300,103nymous_,UP,ALU1 +S 13800,5680,13800,9320,600,104nymous_,UP,NTIE +S 13800,680,13800,3320,600,105nymous_,UP,PTIE +S 13800,6100,13800,8900,300,106nymous_,UP,ALU1 +S 13800,1100,13800,2900,300,107nymous_,UP,ALU1 +S 7800,5700,7800,9300,600,108nymous_,UP,PDIF +S 8400,5500,8400,9500,200,109nymous_,UP,PTRANS +S 10800,5500,10800,9500,200,110nymous_,UP,PTRANS +S 9000,700,9000,2300,600,122nymous_,UP,NDIF +S 11400,700,11400,2300,600,121nymous_,UP,NDIF +S 9600,500,9600,2500,200,120nymous_,UP,NTRANS +S 12000,500,12000,2500,200,119nymous_,UP,NTRANS +S 10800,500,10800,2500,200,118nymous_,UP,NTRANS +S 8400,500,8400,2500,200,117nymous_,UP,NTRANS +S 9000,5700,9000,9300,600,116nymous_,UP,PDIF +S 10200,5700,10200,9300,600,115nymous_,UP,PDIF +S 9600,5500,9600,9500,200,114nymous_,UP,PTRANS +S 12600,5700,12600,9300,600,113nymous_,UP,PDIF +S 12000,5500,12000,9500,200,112nymous_,UP,PTRANS +S 11400,5700,11400,9300,600,111nymous_,UP,PDIF +S 29850,4000,31150,4000,600,158nymous_,RIGHT,ALU2 +S 25850,4000,27150,4000,600,157nymous_,RIGHT,ALU2 +S 20850,4000,22150,4000,600,156nymous_,RIGHT,ALU2 +S 18850,4000,20150,4000,600,155nymous_,RIGHT,ALU2 +S 16850,4000,18150,4000,600,154nymous_,RIGHT,ALU2 +S 14850,4000,16150,4000,600,153nymous_,RIGHT,ALU2 +S 12850,4000,14150,4000,600,152nymous_,RIGHT,ALU2 +S 10850,4000,12150,4000,600,151nymous_,RIGHT,ALU2 +S 8850,4000,10150,4000,600,150nymous_,RIGHT,ALU2 +S -600,7800,34600,7800,6000,149nymous_,RIGHT,NWELL +S 33400,1100,33400,2900,300,148nymous_,UP,ALU1 +S 33400,6100,33400,8900,300,147nymous_,UP,ALU1 +S 12600,700,12600,2300,600,123nymous_,UP,NDIF +S 10200,700,10200,2300,600,124nymous_,UP,NDIF +S 7800,700,7800,2300,600,125nymous_,UP,NDIF +S 10800,4000,13000,4000,600,126nymous_,RIGHT,POLY +S 8400,4000,10000,4000,600,127nymous_,RIGHT,POLY +S 8400,2800,8400,5200,200,128nymous_,UP,POLY +S 9600,2800,9600,5200,200,129nymous_,UP,POLY +S 10800,2800,10800,5200,200,130nymous_,UP,POLY +S 12000,2800,12000,5200,200,131nymous_,UP,POLY +S 10100,4000,11300,4000,300,132nymous_,RIGHT,ALU1 +S 10200,6100,10200,8900,300,133nymous_,UP,ALU1 +S 9000,2100,9000,7900,300,134nymous_,UP,ALU1 +S 7800,6100,7800,8900,300,135nymous_,UP,ALU1 +S 7800,1100,7800,1900,300,136nymous_,UP,ALU1 +S 12600,1100,12600,1900,300,137nymous_,UP,ALU1 +S 12600,6100,12600,8900,300,138nymous_,UP,ALU1 +S 10200,1100,10200,1900,300,139nymous_,UP,ALU1 +S 11400,2100,11400,7900,300,140nymous_,UP,ALU1 +S 600,5680,600,9320,600,141nymous_,UP,NTIE +S 600,680,600,3320,600,142nymous_,UP,PTIE +S 600,1100,600,2900,300,143nymous_,UP,ALU1 +S 600,6100,600,8900,300,144nymous_,UP,ALU1 +S 33400,5680,33400,9320,600,145nymous_,UP,NTIE +S 33400,680,33400,3320,600,146nymous_,UP,PTIE +S 27850,4000,29150,4000,600,159nymous_,RIGHT,ALU2 +S 31850,4000,33150,4000,600,160nymous_,RIGHT,ALU2 +S 33000,4100,33000,4900,300,161nymous_,UP,ALU1 +S 27000,4100,27000,4900,300,162nymous_,UP,ALU1 +S 20000,4100,20000,4900,300,163nymous_,UP,ALU1 +S 13000,4100,13000,4900,300,164nymous_,UP,ALU1 +S 11000,3850,11000,4150,400,nad6x,UP,CALU3 +S 33000,3850,33000,4150,400,ad3,UP,CALU3 +S 27000,3850,27000,4150,400,ad4,UP,CALU3 +S 20000,3850,20000,4150,400,ad5,UP,CALU3 +S 13000,3850,13000,4150,400,ad6,UP,CALU3 +S 28000,3850,28000,4150,400,ad3x,UP,CALU3 +S 31000,3850,31000,4150,400,nad3x,UP,CALU3 +S 22000,3850,22000,4150,400,ad4x,UP,CALU3 +S 23000,3850,23000,4150,400,nad4x,UP,CALU3 +S 16000,3850,16000,4150,400,ad5x,UP,CALU3 +S 18000,3850,18000,4150,400,nad5x,UP,CALU3 +S 9000,3850,9000,4150,400,ad6x,UP,CALU3 +V 27000,4000,CONT_POLY,165nymous_ +V 27000,4000,CONT_VIA,166nymous_ +V 27000,4000,CONT_VIA2,167nymous_ +V 27200,6000,CONT_DIF_P,168nymous_ +V 27200,8000,CONT_DIF_P,169nymous_ +V 27200,9000,CONT_DIF_P,170nymous_ +V 27200,7000,CONT_DIF_P,171nymous_ +V 27200,2000,CONT_DIF_N,172nymous_ +V 27200,1000,CONT_DIF_N,173nymous_ +V 28600,4000,CONT_VIA,174nymous_ +V 28000,4000,CONT_VIA2,175nymous_ +V 33000,4000,CONT_POLY,176nymous_ +V 33000,4000,CONT_VIA,177nymous_ +V 33000,4000,CONT_VIA2,178nymous_ +V 31000,4000,CONT_VIA,179nymous_ +V 31000,4000,CONT_VIA2,180nymous_ +V 32200,7000,CONT_DIF_P,181nymous_ +V 28600,7000,CONT_DIF_P,182nymous_ +V 32200,9000,CONT_DIF_P,183nymous_ +V 28600,6000,CONT_DIF_P,184nymous_ +V 31000,6000,CONT_DIF_P,185nymous_ +V 31000,7000,CONT_DIF_P,186nymous_ +V 29800,9000,CONT_DIF_P,187nymous_ +V 32200,6000,CONT_DIF_P,188nymous_ +V 32200,8000,CONT_DIF_P,189nymous_ +V 29800,6000,CONT_DIF_P,190nymous_ +V 29800,7000,CONT_DIF_P,191nymous_ +V 28600,8000,CONT_DIF_P,192nymous_ +V 29800,8000,CONT_DIF_P,193nymous_ +V 31000,8000,CONT_DIF_P,194nymous_ +V 31000,2000,CONT_DIF_N,195nymous_ +V 32200,1000,CONT_DIF_N,196nymous_ +V 29800,2000,CONT_DIF_N,197nymous_ +V 28600,2000,CONT_DIF_N,198nymous_ +V 32200,2000,CONT_DIF_N,199nymous_ +V 29800,1000,CONT_DIF_N,200nymous_ +V 29600,4000,CONT_POLY,201nymous_ +V 23000,4000,CONT_VIA2,202nymous_ +V 22200,8000,CONT_DIF_P,203nymous_ +V 22200,9000,CONT_DIF_P,204nymous_ +V 22200,7000,CONT_DIF_P,205nymous_ +V 22200,6000,CONT_DIF_P,206nymous_ +V 24600,7000,CONT_DIF_P,207nymous_ +V 25800,6000,CONT_DIF_P,208nymous_ +V 25800,7000,CONT_DIF_P,209nymous_ +V 24600,9000,CONT_DIF_P,210nymous_ +V 24600,6000,CONT_DIF_P,211nymous_ +V 23400,7000,CONT_DIF_P,212nymous_ +V 23400,6000,CONT_DIF_P,213nymous_ +V 23400,8000,CONT_DIF_P,214nymous_ +V 24600,8000,CONT_DIF_P,215nymous_ +V 25800,8000,CONT_DIF_P,216nymous_ +V 24600,1000,CONT_DIF_N,217nymous_ +V 23400,2000,CONT_DIF_N,218nymous_ +V 24600,2000,CONT_DIF_N,219nymous_ +V 22200,1000,CONT_DIF_N,220nymous_ +V 22200,2000,CONT_DIF_N,221nymous_ +V 25800,2000,CONT_DIF_N,222nymous_ +V 24400,4000,CONT_POLY,223nymous_ +V 24400,4000,CONT_VIA,224nymous_ +V 21000,9000,CONT_BODY_N,225nymous_ +V 21000,8000,CONT_BODY_N,226nymous_ +V 21000,7000,CONT_BODY_N,227nymous_ +V 21000,6000,CONT_BODY_N,228nymous_ +V 21000,2000,CONT_BODY_P,229nymous_ +V 21000,3000,CONT_BODY_P,230nymous_ +V 21000,1000,CONT_BODY_P,231nymous_ +V 20000,4000,CONT_POLY,232nymous_ +V 20000,4000,CONT_VIA,233nymous_ +V 20000,4000,CONT_VIA2,234nymous_ +V 18000,4000,CONT_VIA,235nymous_ +V 18000,4000,CONT_VIA2,236nymous_ +V 16000,4000,CONT_VIA,237nymous_ +V 16000,4000,CONT_VIA2,238nymous_ +V 18600,6000,CONT_DIF_P,239nymous_ +V 18600,7000,CONT_DIF_P,240nymous_ +V 15000,8000,CONT_DIF_P,241nymous_ +V 15000,9000,CONT_DIF_P,242nymous_ +V 15000,7000,CONT_DIF_P,243nymous_ +V 16200,6000,CONT_DIF_P,244nymous_ +V 16200,8000,CONT_DIF_P,245nymous_ +V 17400,8000,CONT_DIF_P,246nymous_ +V 19800,8000,CONT_DIF_P,247nymous_ +V 19800,7000,CONT_DIF_P,248nymous_ +V 15000,6000,CONT_DIF_P,249nymous_ +V 19800,6000,CONT_DIF_P,250nymous_ +V 17400,7000,CONT_DIF_P,251nymous_ +V 18600,8000,CONT_DIF_P,252nymous_ +V 19800,9000,CONT_DIF_P,253nymous_ +V 17400,9000,CONT_DIF_P,254nymous_ +V 17400,6000,CONT_DIF_P,255nymous_ +V 16200,7000,CONT_DIF_P,256nymous_ +V 17400,1000,CONT_DIF_N,257nymous_ +V 17400,2000,CONT_DIF_N,258nymous_ +V 15000,1000,CONT_DIF_N,259nymous_ +V 15000,2000,CONT_DIF_N,260nymous_ +V 19800,2000,CONT_DIF_N,261nymous_ +V 18600,2000,CONT_DIF_N,262nymous_ +V 19800,1000,CONT_DIF_N,263nymous_ +V 16200,2000,CONT_DIF_N,264nymous_ +V 17200,4000,CONT_POLY,265nymous_ +V 13800,6000,CONT_BODY_N,266nymous_ +V 13800,7000,CONT_BODY_N,267nymous_ +V 13800,8000,CONT_BODY_N,268nymous_ +V 13800,9000,CONT_BODY_N,269nymous_ +V 13800,1000,CONT_BODY_P,270nymous_ +V 13800,3000,CONT_BODY_P,271nymous_ +V 13800,2000,CONT_BODY_P,272nymous_ +V 7800,7000,CONT_DIF_P,273nymous_ +V 7800,9000,CONT_DIF_P,274nymous_ +V 7800,8000,CONT_DIF_P,275nymous_ +V 11400,7000,CONT_DIF_P,276nymous_ +V 11400,6000,CONT_DIF_P,277nymous_ +V 10200,7000,CONT_DIF_P,278nymous_ +V 12600,6000,CONT_DIF_P,279nymous_ +V 7800,6000,CONT_DIF_P,280nymous_ +V 12600,7000,CONT_DIF_P,281nymous_ +V 12600,8000,CONT_DIF_P,282nymous_ +V 10200,8000,CONT_DIF_P,283nymous_ +V 9000,8000,CONT_DIF_P,284nymous_ +V 9000,6000,CONT_DIF_P,285nymous_ +V 9000,7000,CONT_DIF_P,286nymous_ +V 10200,6000,CONT_DIF_P,287nymous_ +V 10200,9000,CONT_DIF_P,288nymous_ +V 12600,9000,CONT_DIF_P,289nymous_ +V 11400,8000,CONT_DIF_P,290nymous_ +V 10200,1000,CONT_DIF_N,291nymous_ +V 12600,2000,CONT_DIF_N,292nymous_ +V 7800,2000,CONT_DIF_N,293nymous_ +V 7800,1000,CONT_DIF_N,294nymous_ +V 10200,2000,CONT_DIF_N,295nymous_ +V 9000,2000,CONT_DIF_N,296nymous_ +V 12600,1000,CONT_DIF_N,297nymous_ +V 11400,2000,CONT_DIF_N,298nymous_ +V 13000,4000,CONT_POLY,299nymous_ +V 10000,4000,CONT_POLY,300nymous_ +V 9000,4000,CONT_VIA,301nymous_ +V 11000,4000,CONT_VIA,302nymous_ +V 13000,4000,CONT_VIA,303nymous_ +V 13000,4000,CONT_VIA2,306nymous_ +V 9000,4000,CONT_VIA2,305nymous_ +V 11000,4000,CONT_VIA2,304nymous_ +V 600,8000,CONT_BODY_N,307nymous_ +V 33400,1000,CONT_BODY_P,322nymous_ +V 33400,3000,CONT_BODY_P,321nymous_ +V 33400,2000,CONT_BODY_P,320nymous_ +V 33400,6000,CONT_BODY_N,319nymous_ +V 33400,7000,CONT_BODY_N,318nymous_ +V 33400,8000,CONT_BODY_N,317nymous_ +V 33400,9000,CONT_BODY_N,316nymous_ +V 22000,4000,CONT_VIA2,315nymous_ +V 22000,4000,CONT_VIA,314nymous_ +V 600,1000,CONT_BODY_P,313nymous_ +V 600,3000,CONT_BODY_P,312nymous_ +V 600,2000,CONT_BODY_P,311nymous_ +V 600,9000,CONT_BODY_N,310nymous_ +V 600,6000,CONT_BODY_N,309nymous_ +V 600,7000,CONT_BODY_N,308nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_sense_decad4.vbe b/pdks/symbolic/nramlib/cells/ram_sense_decad4.vbe new file mode 100644 index 000000000..992bb03c6 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_decad4.vbe @@ -0,0 +1,27 @@ +ENTITY ram_sense_decad4 IS +PORT ( + ad3 : in BIT; + ad4 : in BIT; + ad5 : in BIT; + ad6 : in BIT; + ad3x : out BIT; + nad3x : out BIT; + ad4x : out BIT; + nad4x : out BIT; + ad5x : out BIT; + nad5x : out BIT; + ad6x : out BIT; + nad6x : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_decad4; + +ARCHITECTURE VBE OF ram_sense_decad4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_decad4" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/cells/ram_sense_decad5.ap b/pdks/symbolic/nramlib/cells/ram_sense_decad5.ap new file mode 100644 index 000000000..a08981d9e --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_decad5.ap @@ -0,0 +1,425 @@ +V ALLIANCE : 6 +H ram_sense_decad5,P,23/4/2016,100 +A 0,0,34000,10000 +S 6600,6100,6600,8900,300,7nonymous_,UP,ALU1 +S 5400,2100,5400,7900,300,8nonymous_,UP,ALU1 +S 4200,6100,4200,8900,300,9nonymous_,UP,ALU1 +S 3000,2100,3000,7900,300,10onymous_,UP,ALU1 +S 600,6100,600,8900,300,11onymous_,UP,ALU1 +S 600,1100,600,2900,300,12onymous_,UP,ALU1 +S 1800,6100,1800,8900,300,13onymous_,UP,ALU1 +S 600,680,600,3320,600,14onymous_,UP,PTIE +S 3600,5500,3600,9500,200,15onymous_,UP,PTRANS +S 4200,5700,4200,9300,600,16onymous_,UP,PDIF +S 3000,5700,3000,9300,600,17onymous_,UP,PDIF +S 33400,5680,33400,9320,600,6nonymous_,UP,NTIE +S 33400,680,33400,3320,600,5nonymous_,UP,PTIE +S 33400,6100,33400,8900,300,4nonymous_,UP,ALU1 +S 100,9400,33900,9400,1200,vdd,RIGHT,CALU1 +S 100,600,33900,600,1200,vss,RIGHT,CALU1 +S 25000,-150,25000,10150,2400,0nonymous_,UP,ALU3 +S 0,-150,0,10150,2400,1nonymous_,UP,ALU3 +S -600,7800,34600,7800,6000,2nonymous_,RIGHT,NWELL +S 33400,1100,33400,2900,300,3nonymous_,UP,ALU1 +S 10800,4000,13000,4000,600,35onymous_,RIGHT,POLY +S 8400,4000,10000,4000,600,34onymous_,RIGHT,POLY +S 10100,4000,11300,4000,300,33onymous_,RIGHT,ALU1 +S 10200,6100,10200,8900,300,32onymous_,UP,ALU1 +S 9000,2100,9000,7900,300,31onymous_,UP,ALU1 +S 7800,6100,7800,8900,300,30onymous_,UP,ALU1 +S 12600,6100,12600,8900,300,29onymous_,UP,ALU1 +S 11400,2100,11400,7900,300,28onymous_,UP,ALU1 +S 4100,4000,5300,4000,300,27onymous_,RIGHT,ALU1 +S 2400,4000,4000,4000,600,26onymous_,RIGHT,POLY +S 4800,4000,7000,4000,600,25onymous_,RIGHT,POLY +S 6600,5700,6600,9300,600,24onymous_,UP,PDIF +S 600,5680,600,9320,600,18onymous_,UP,NTIE +S 1800,5700,1800,9300,600,19onymous_,UP,PDIF +S 2400,5500,2400,9500,200,20onymous_,UP,PTRANS +S 4800,5500,4800,9500,200,21onymous_,UP,PTRANS +S 5400,5700,5400,9300,600,22onymous_,UP,PDIF +S 6000,5500,6000,9500,200,23onymous_,UP,PTRANS +S 21000,6100,21000,8900,300,64onymous_,UP,ALU1 +S 21000,5680,21000,9320,600,65onymous_,UP,NTIE +S 22200,6100,22200,8900,300,66onymous_,UP,ALU1 +S 9000,5700,9000,9300,600,36onymous_,UP,PDIF +S 10200,5700,10200,9300,600,37onymous_,UP,PDIF +S 9600,5500,9600,9500,200,38onymous_,UP,PTRANS +S 12600,5700,12600,9300,600,39onymous_,UP,PDIF +S 12000,5500,12000,9500,200,40onymous_,UP,PTRANS +S 11400,5700,11400,9300,600,41onymous_,UP,PDIF +S 10800,5500,10800,9500,200,42onymous_,UP,PTRANS +S 8400,5500,8400,9500,200,43onymous_,UP,PTRANS +S 7800,5700,7800,9300,600,44onymous_,UP,PDIF +S 13800,6100,13800,8900,300,45onymous_,UP,ALU1 +S 13800,5680,13800,9320,600,46onymous_,UP,NTIE +S 19800,6100,19800,8900,300,47onymous_,UP,ALU1 +S 18600,2100,18600,7900,300,48onymous_,UP,ALU1 +S 17400,6100,17400,8900,300,49onymous_,UP,ALU1 +S 16200,2100,16200,7900,300,50onymous_,UP,ALU1 +S 15000,6100,15000,8900,300,51onymous_,UP,ALU1 +S 17300,4000,18500,4000,300,52onymous_,RIGHT,ALU1 +S 18000,4000,20200,4000,600,53onymous_,RIGHT,POLY +S 15600,4000,17200,4000,600,54onymous_,RIGHT,POLY +S 18600,5700,18600,9300,600,55onymous_,UP,PDIF +S 19200,5500,19200,9500,200,56onymous_,UP,PTRANS +S 19800,5700,19800,9300,600,57onymous_,UP,PDIF +S 16800,5500,16800,9500,200,58onymous_,UP,PTRANS +S 17400,5700,17400,9300,600,59onymous_,UP,PDIF +S 16200,5700,16200,9300,600,60onymous_,UP,PDIF +S 15000,5700,15000,9300,600,61onymous_,UP,PDIF +S 15600,5500,15600,9500,200,62onymous_,UP,PTRANS +S 18000,5500,18000,9500,200,63onymous_,UP,PTRANS +S 25800,2100,25800,7900,300,67onymous_,UP,ALU1 +S 24600,6100,24600,8900,300,68onymous_,UP,ALU1 +S 23400,2100,23400,7900,300,69onymous_,UP,ALU1 +S 24700,4000,25700,4000,300,70onymous_,RIGHT,ALU1 +S 22800,4000,24600,4000,600,71onymous_,RIGHT,POLY +S 24000,5500,24000,9500,200,72onymous_,UP,PTRANS +S 24600,5700,24600,9300,600,73onymous_,UP,PDIF +S 23400,5700,23400,9300,600,74onymous_,UP,PDIF +S 22200,5700,22200,9300,600,75onymous_,UP,PDIF +S 22800,5500,22800,9500,200,76onymous_,UP,PTRANS +S 25200,5500,25200,9500,200,77onymous_,UP,PTRANS +S 25800,5700,25800,9300,600,78onymous_,UP,PDIF +S 26400,5500,26400,9500,200,79onymous_,UP,PTRANS +S 22850,4000,24550,4000,600,80onymous_,RIGHT,ALU2 +S 29800,6100,29800,8900,300,81onymous_,UP,ALU1 +S 28600,2100,28600,7900,300,82onymous_,UP,ALU1 +S 32200,6100,32200,8900,300,83onymous_,UP,ALU1 +S 31000,2100,31000,7900,300,84onymous_,UP,ALU1 +S 29700,4000,30900,4000,300,85onymous_,RIGHT,ALU1 +S 28000,4000,29800,4000,600,86onymous_,RIGHT,POLY +S 28000,5500,28000,9500,200,87onymous_,UP,PTRANS +S 28600,5700,28600,9300,600,88onymous_,UP,PDIF +S 30400,5500,30400,9500,200,89onymous_,UP,PTRANS +S 29800,5700,29800,9300,600,90onymous_,UP,PDIF +S 31600,5500,31600,9500,200,91onymous_,UP,PTRANS +S 32200,5700,32200,9300,600,92onymous_,UP,PDIF +S 31000,5700,31000,9300,600,93onymous_,UP,PDIF +S 29200,5500,29200,9500,200,94onymous_,UP,PTRANS +S 30400,4000,33200,4000,600,95onymous_,RIGHT,POLY +S 25200,4000,27200,4000,600,96onymous_,RIGHT,POLY +S 22100,4000,23300,4000,300,97onymous_,RIGHT,ALU1 +S 27200,6100,27200,8900,300,98onymous_,UP,ALU1 +S 27200,5700,27200,9300,1000,99onymous_,UP,PDIF +S 3050,4000,32950,4000,300,100nymous_,RIGHT,TALU2 +S 2850,4000,4150,4000,600,101nymous_,RIGHT,ALU2 +S 4850,4000,6150,4000,600,102nymous_,RIGHT,ALU2 +S 8850,4000,10150,4000,600,103nymous_,RIGHT,ALU2 +S 10850,4000,12150,4000,600,104nymous_,RIGHT,ALU2 +S 12850,4000,14150,4000,600,105nymous_,RIGHT,ALU2 +S 6850,4000,8150,4000,600,106nymous_,RIGHT,ALU2 +S 14850,4000,16150,4000,600,107nymous_,RIGHT,ALU2 +S 16850,4000,18150,4000,600,108nymous_,RIGHT,ALU2 +S 18850,4000,20150,4000,600,109nymous_,RIGHT,ALU2 +S 20850,4000,22150,4000,600,110nymous_,RIGHT,ALU2 +S 31600,3800,31600,5200,200,122nymous_,UP,POLY +S 30400,3800,30400,5200,200,121nymous_,UP,POLY +S 28000,3800,28000,5200,200,120nymous_,UP,POLY +S 24000,3800,24000,5200,200,119nymous_,UP,POLY +S 25200,3800,25200,5200,200,118nymous_,UP,POLY +S 26400,3800,26400,5200,200,117nymous_,UP,POLY +S 22800,3800,22800,5200,200,116nymous_,UP,POLY +S 27850,4000,29150,4000,600,115nymous_,RIGHT,ALU2 +S 29850,4000,31150,4000,600,114nymous_,RIGHT,ALU2 +S 31850,4000,33150,4000,600,113nymous_,RIGHT,ALU2 +S 33000,4100,33000,4900,300,112nymous_,UP,ALU1 +S 25850,4000,27150,4000,600,111nymous_,RIGHT,ALU2 +S 1800,1500,1800,3300,600,158nymous_,UP,NDIF +S 5400,1500,5400,3300,600,157nymous_,UP,NDIF +S 3000,1500,3000,3300,600,156nymous_,UP,NDIF +S 6600,1500,6600,3300,600,155nymous_,UP,NDIF +S 4200,1500,4200,3300,600,154nymous_,UP,NDIF +S 18600,1500,18600,3300,600,153nymous_,UP,NDIF +S 16200,1500,16200,3300,600,152nymous_,UP,NDIF +S 19800,1500,19800,3300,600,151nymous_,UP,NDIF +S 17400,1500,17400,3300,600,150nymous_,UP,NDIF +S 9000,1500,9000,3300,600,149nymous_,UP,NDIF +S 11400,1500,11400,3300,600,148nymous_,UP,NDIF +S 7800,1500,7800,3300,600,147nymous_,UP,NDIF +S 10200,1500,10200,3300,600,146nymous_,UP,NDIF +S 28600,1500,28600,3300,600,145nymous_,UP,NDIF +S 32200,1500,32200,3300,600,144nymous_,UP,NDIF +S 29200,3800,29200,5200,200,123nymous_,UP,POLY +S 8400,3800,8400,5200,200,124nymous_,UP,POLY +S 9600,3800,9600,5200,200,125nymous_,UP,POLY +S 10800,3800,10800,5200,200,126nymous_,UP,POLY +S 12000,3800,12000,5200,200,127nymous_,UP,POLY +S 16800,3800,16800,5200,200,128nymous_,UP,POLY +S 15600,3800,15600,5200,200,129nymous_,UP,POLY +S 19200,3800,19200,5200,200,130nymous_,UP,POLY +S 18000,3800,18000,5200,200,131nymous_,UP,POLY +S 2400,3800,2400,5200,200,132nymous_,UP,POLY +S 6000,3800,6000,5200,200,133nymous_,UP,POLY +S 4800,3800,4800,5200,200,134nymous_,UP,POLY +S 3600,3800,3600,5200,200,135nymous_,UP,POLY +S 31000,1500,31000,3300,600,136nymous_,UP,NDIF +S 27200,1500,27200,3300,1000,137nymous_,UP,NDIF +S 15000,1500,15000,3300,600,138nymous_,UP,NDIF +S 25800,1500,25800,3300,600,139nymous_,UP,NDIF +S 22200,1500,22200,3300,600,140nymous_,UP,NDIF +S 24600,1500,24600,3300,600,141nymous_,UP,NDIF +S 23400,1500,23400,3300,600,142nymous_,UP,NDIF +S 29800,1500,29800,3300,600,143nymous_,UP,NDIF +S 12600,1500,12600,3300,600,159nymous_,UP,NDIF +S 22800,1300,22800,3500,200,160nymous_,UP,NTRANS +S 24000,1300,24000,3500,200,161nymous_,UP,NTRANS +S 26400,1300,26400,3500,200,162nymous_,UP,NTRANS +S 25200,1300,25200,3500,200,163nymous_,UP,NTRANS +S 8400,1300,8400,3500,200,164nymous_,UP,NTRANS +S 10800,1300,10800,3500,200,165nymous_,UP,NTRANS +S 12000,1300,12000,3500,200,166nymous_,UP,NTRANS +S 9600,1300,9600,3500,200,167nymous_,UP,NTRANS +S 29200,1300,29200,3500,200,168nymous_,UP,NTRANS +S 31600,1300,31600,3500,200,169nymous_,UP,NTRANS +S 28000,1300,28000,3500,200,170nymous_,UP,NTRANS +S 30400,1300,30400,3500,200,171nymous_,UP,NTRANS +S 3600,1300,3600,3500,200,172nymous_,UP,NTRANS +S 6000,1300,6000,3500,200,173nymous_,UP,NTRANS +S 4800,1300,4800,3500,200,174nymous_,UP,NTRANS +S 2400,1300,2400,3500,200,175nymous_,UP,NTRANS +S 16800,1300,16800,3500,200,176nymous_,UP,NTRANS +S 19200,1300,19200,3500,200,177nymous_,UP,NTRANS +S 18000,1300,18000,3500,200,178nymous_,UP,NTRANS +S 15600,1300,15600,3500,200,179nymous_,UP,NTRANS +S 21000,1100,21000,2900,300,180nymous_,UP,ALU1 +S 21000,680,21000,3320,600,181nymous_,UP,PTIE +S 13800,1100,13800,2900,300,182nymous_,UP,ALU1 +S 13800,680,13800,3320,600,183nymous_,UP,PTIE +S 27200,1100,27200,2900,300,184nymous_,UP,ALU1 +S 29800,1100,29800,2900,300,185nymous_,UP,ALU1 +S 32200,1100,32200,2900,300,186nymous_,UP,ALU1 +S 24600,1100,24600,2900,300,187nymous_,UP,ALU1 +S 22200,1100,22200,2900,300,188nymous_,UP,ALU1 +S 19800,1100,19800,2900,300,189nymous_,UP,ALU1 +S 17400,1100,17400,2900,300,190nymous_,UP,ALU1 +S 15000,1100,15000,2900,300,191nymous_,UP,ALU1 +S 12600,1100,12600,2900,300,192nymous_,UP,ALU1 +S 10200,1100,10200,2900,300,193nymous_,UP,ALU1 +S 7800,1100,7800,2900,300,194nymous_,UP,ALU1 +S 6600,1100,6600,2900,300,195nymous_,UP,ALU1 +S 4200,1100,4200,2900,300,196nymous_,UP,ALU1 +S 1800,1100,1800,2900,300,197nymous_,UP,ALU1 +S 7000,4100,7000,4900,300,198nymous_,UP,ALU1 +S 13000,4100,13000,4900,300,199nymous_,UP,ALU1 +S 20000,4100,20000,4900,300,200nymous_,UP,ALU1 +S 27000,4100,27000,4900,300,201nymous_,UP,ALU1 +S 5000,3850,5000,4150,400,nad7x,UP,CALU3 +S 3000,3850,3000,4150,400,ad7x,UP,CALU3 +S 11000,3850,11000,4150,400,nad6x,UP,CALU3 +S 9000,3850,9000,4150,400,ad6x,UP,CALU3 +S 33000,3850,33000,4150,400,ad3,UP,CALU3 +S 27000,3850,27000,4150,400,ad4,UP,CALU3 +S 20000,3850,20000,4150,400,ad5,UP,CALU3 +S 13000,3850,13000,4150,400,ad6,UP,CALU3 +S 7000,3850,7000,4150,400,ad7,UP,CALU3 +S 28000,3850,28000,4150,400,ad3x,UP,CALU3 +S 31000,3850,31000,4150,400,nad3x,UP,CALU3 +S 22000,3850,22000,4150,400,ad4x,UP,CALU3 +S 23000,3850,23000,4150,400,nad4x,UP,CALU3 +S 16000,3850,16000,4150,400,ad5x,UP,CALU3 +S 18000,3850,18000,4150,400,nad5x,UP,CALU3 +V 33400,1000,CONT_BODY_P,202nymous_ +V 33400,3000,CONT_BODY_P,203nymous_ +V 33400,2000,CONT_BODY_P,204nymous_ +V 33400,6000,CONT_BODY_N,205nymous_ +V 33400,7000,CONT_BODY_N,206nymous_ +V 33400,8000,CONT_BODY_N,207nymous_ +V 33400,9000,CONT_BODY_N,208nymous_ +V 22000,4000,CONT_VIA2,209nymous_ +V 22000,4000,CONT_VIA,210nymous_ +V 600,1000,CONT_BODY_P,211nymous_ +V 600,3000,CONT_BODY_P,212nymous_ +V 600,2000,CONT_BODY_P,213nymous_ +V 600,9000,CONT_BODY_N,214nymous_ +V 5400,8000,CONT_DIF_P,215nymous_ +V 3000,6000,CONT_DIF_P,216nymous_ +V 3000,7000,CONT_DIF_P,217nymous_ +V 4200,6000,CONT_DIF_P,218nymous_ +V 4200,9000,CONT_DIF_P,219nymous_ +V 6600,9000,CONT_DIF_P,220nymous_ +V 600,6000,CONT_BODY_N,221nymous_ +V 600,7000,CONT_BODY_N,222nymous_ +V 600,8000,CONT_BODY_N,223nymous_ +V 5400,6000,CONT_DIF_P,224nymous_ +V 4200,7000,CONT_DIF_P,225nymous_ +V 6600,6000,CONT_DIF_P,226nymous_ +V 1800,6000,CONT_DIF_P,227nymous_ +V 6600,7000,CONT_DIF_P,228nymous_ +V 6600,8000,CONT_DIF_P,229nymous_ +V 4200,8000,CONT_DIF_P,230nymous_ +V 3000,8000,CONT_DIF_P,231nymous_ +V 1800,7000,CONT_DIF_P,232nymous_ +V 1800,9000,CONT_DIF_P,233nymous_ +V 1800,8000,CONT_DIF_P,234nymous_ +V 5400,7000,CONT_DIF_P,235nymous_ +V 3000,4000,CONT_VIA,236nymous_ +V 5000,4000,CONT_VIA,237nymous_ +V 7000,4000,CONT_VIA,238nymous_ +V 7000,4000,CONT_VIA2,239nymous_ +V 5000,4000,CONT_VIA2,240nymous_ +V 3000,4000,CONT_VIA2,241nymous_ +V 7000,4000,CONT_POLY,242nymous_ +V 4000,4000,CONT_POLY,243nymous_ +V 13000,4000,CONT_VIA2,244nymous_ +V 9000,4000,CONT_VIA2,245nymous_ +V 11000,4000,CONT_VIA2,246nymous_ +V 13000,4000,CONT_VIA,247nymous_ +V 11000,4000,CONT_VIA,248nymous_ +V 9000,4000,CONT_VIA,249nymous_ +V 10000,4000,CONT_POLY,250nymous_ +V 13000,4000,CONT_POLY,251nymous_ +V 11400,8000,CONT_DIF_P,252nymous_ +V 12600,9000,CONT_DIF_P,253nymous_ +V 10200,9000,CONT_DIF_P,254nymous_ +V 10200,6000,CONT_DIF_P,255nymous_ +V 9000,7000,CONT_DIF_P,256nymous_ +V 9000,6000,CONT_DIF_P,257nymous_ +V 9000,8000,CONT_DIF_P,258nymous_ +V 10200,8000,CONT_DIF_P,259nymous_ +V 12600,8000,CONT_DIF_P,260nymous_ +V 12600,7000,CONT_DIF_P,261nymous_ +V 7800,6000,CONT_DIF_P,262nymous_ +V 12600,6000,CONT_DIF_P,263nymous_ +V 10200,7000,CONT_DIF_P,264nymous_ +V 11400,6000,CONT_DIF_P,265nymous_ +V 11400,7000,CONT_DIF_P,266nymous_ +V 7800,8000,CONT_DIF_P,267nymous_ +V 7800,9000,CONT_DIF_P,268nymous_ +V 7800,7000,CONT_DIF_P,269nymous_ +V 13800,9000,CONT_BODY_N,270nymous_ +V 13800,8000,CONT_BODY_N,271nymous_ +V 13800,7000,CONT_BODY_N,272nymous_ +V 13800,6000,CONT_BODY_N,273nymous_ +V 17200,4000,CONT_POLY,274nymous_ +V 16200,7000,CONT_DIF_P,275nymous_ +V 17400,6000,CONT_DIF_P,276nymous_ +V 17400,9000,CONT_DIF_P,277nymous_ +V 19800,9000,CONT_DIF_P,278nymous_ +V 18600,8000,CONT_DIF_P,279nymous_ +V 17400,7000,CONT_DIF_P,280nymous_ +V 19800,6000,CONT_DIF_P,281nymous_ +V 15000,6000,CONT_DIF_P,282nymous_ +V 19800,7000,CONT_DIF_P,283nymous_ +V 19800,8000,CONT_DIF_P,284nymous_ +V 17400,8000,CONT_DIF_P,285nymous_ +V 16200,8000,CONT_DIF_P,286nymous_ +V 16200,6000,CONT_DIF_P,287nymous_ +V 15000,7000,CONT_DIF_P,288nymous_ +V 15000,9000,CONT_DIF_P,289nymous_ +V 15000,8000,CONT_DIF_P,290nymous_ +V 18600,7000,CONT_DIF_P,291nymous_ +V 18600,6000,CONT_DIF_P,292nymous_ +V 16000,4000,CONT_VIA2,293nymous_ +V 16000,4000,CONT_VIA,294nymous_ +V 18000,4000,CONT_VIA2,295nymous_ +V 18000,4000,CONT_VIA,296nymous_ +V 20000,4000,CONT_VIA2,297nymous_ +V 20000,4000,CONT_VIA,298nymous_ +V 20000,4000,CONT_POLY,299nymous_ +V 21000,6000,CONT_BODY_N,300nymous_ +V 21000,7000,CONT_BODY_N,301nymous_ +V 21000,8000,CONT_BODY_N,302nymous_ +V 21000,9000,CONT_BODY_N,303nymous_ +V 24400,4000,CONT_VIA,304nymous_ +V 24400,4000,CONT_POLY,305nymous_ +V 25800,8000,CONT_DIF_P,306nymous_ +V 24600,8000,CONT_DIF_P,307nymous_ +V 23400,8000,CONT_DIF_P,308nymous_ +V 23400,6000,CONT_DIF_P,309nymous_ +V 23400,7000,CONT_DIF_P,310nymous_ +V 24600,6000,CONT_DIF_P,311nymous_ +V 24600,9000,CONT_DIF_P,312nymous_ +V 25800,7000,CONT_DIF_P,313nymous_ +V 25800,6000,CONT_DIF_P,314nymous_ +V 24600,7000,CONT_DIF_P,315nymous_ +V 22200,6000,CONT_DIF_P,316nymous_ +V 22200,7000,CONT_DIF_P,317nymous_ +V 22200,9000,CONT_DIF_P,318nymous_ +V 22200,8000,CONT_DIF_P,319nymous_ +V 23000,4000,CONT_VIA2,320nymous_ +V 29600,4000,CONT_POLY,321nymous_ +V 31000,8000,CONT_DIF_P,322nymous_ +V 29800,8000,CONT_DIF_P,323nymous_ +V 28600,8000,CONT_DIF_P,324nymous_ +V 29800,7000,CONT_DIF_P,325nymous_ +V 29800,6000,CONT_DIF_P,326nymous_ +V 32200,8000,CONT_DIF_P,327nymous_ +V 32200,6000,CONT_DIF_P,328nymous_ +V 29800,9000,CONT_DIF_P,329nymous_ +V 31000,7000,CONT_DIF_P,330nymous_ +V 31000,6000,CONT_DIF_P,331nymous_ +V 28600,6000,CONT_DIF_P,332nymous_ +V 32200,9000,CONT_DIF_P,333nymous_ +V 28600,7000,CONT_DIF_P,334nymous_ +V 32200,7000,CONT_DIF_P,335nymous_ +V 31000,4000,CONT_VIA2,336nymous_ +V 31000,4000,CONT_VIA,337nymous_ +V 33000,4000,CONT_VIA2,338nymous_ +V 33000,4000,CONT_VIA,339nymous_ +V 33000,4000,CONT_POLY,340nymous_ +V 28000,4000,CONT_VIA2,341nymous_ +V 28600,4000,CONT_VIA,342nymous_ +V 27200,7000,CONT_DIF_P,343nymous_ +V 27200,9000,CONT_DIF_P,344nymous_ +V 31000,2000,CONT_DIF_N,359nymous_ +V 28600,2000,CONT_DIF_N,358nymous_ +V 25800,2000,CONT_DIF_N,357nymous_ +V 13800,2000,CONT_BODY_P,356nymous_ +V 13800,3000,CONT_BODY_P,355nymous_ +V 13800,1000,CONT_BODY_P,354nymous_ +V 21000,2000,CONT_BODY_P,353nymous_ +V 21000,3000,CONT_BODY_P,352nymous_ +V 21000,1000,CONT_BODY_P,351nymous_ +V 23400,2000,CONT_DIF_N,350nymous_ +V 27000,4000,CONT_POLY,349nymous_ +V 27000,4000,CONT_VIA,348nymous_ +V 27000,4000,CONT_VIA2,347nymous_ +V 27200,6000,CONT_DIF_P,346nymous_ +V 27200,8000,CONT_DIF_P,345nymous_ +V 18600,2000,CONT_DIF_N,360nymous_ +V 16200,2000,CONT_DIF_N,361nymous_ +V 3000,2000,CONT_DIF_N,362nymous_ +V 5400,2000,CONT_DIF_N,363nymous_ +V 9000,2000,CONT_DIF_N,364nymous_ +V 11400,2000,CONT_DIF_N,365nymous_ +V 18600,3000,CONT_DIF_N,366nymous_ +V 16200,3000,CONT_DIF_N,367nymous_ +V 9000,3000,CONT_DIF_N,368nymous_ +V 11400,3000,CONT_DIF_N,369nymous_ +V 3000,3000,CONT_DIF_N,370nymous_ +V 5400,3000,CONT_DIF_N,371nymous_ +V 31000,3000,CONT_DIF_N,372nymous_ +V 28600,3000,CONT_DIF_N,373nymous_ +V 23400,3000,CONT_DIF_N,374nymous_ +V 25800,3000,CONT_DIF_N,375nymous_ +V 27200,3000,CONT_DIF_N,376nymous_ +V 27200,2000,CONT_DIF_N,377nymous_ +V 29800,2000,CONT_DIF_N,378nymous_ +V 29800,3000,CONT_DIF_N,379nymous_ +V 32200,2000,CONT_DIF_N,380nymous_ +V 32200,3000,CONT_DIF_N,381nymous_ +V 24600,3000,CONT_DIF_N,382nymous_ +V 24600,2000,CONT_DIF_N,383nymous_ +V 22200,3000,CONT_DIF_N,384nymous_ +V 22200,2000,CONT_DIF_N,385nymous_ +V 19800,2000,CONT_DIF_N,386nymous_ +V 19800,3000,CONT_DIF_N,387nymous_ +V 17400,2000,CONT_DIF_N,388nymous_ +V 17400,3000,CONT_DIF_N,389nymous_ +V 15000,2000,CONT_DIF_N,390nymous_ +V 15000,3000,CONT_DIF_N,391nymous_ +V 12600,3000,CONT_DIF_N,392nymous_ +V 12600,2000,CONT_DIF_N,393nymous_ +V 10200,2000,CONT_DIF_N,394nymous_ +V 10200,3000,CONT_DIF_N,395nymous_ +V 7800,3000,CONT_DIF_N,396nymous_ +V 7800,2000,CONT_DIF_N,397nymous_ +V 6600,2000,CONT_DIF_N,398nymous_ +V 6600,3000,CONT_DIF_N,399nymous_ +V 4200,3000,CONT_DIF_N,400nymous_ +V 4200,2000,CONT_DIF_N,401nymous_ +V 1800,3000,CONT_DIF_N,402nymous_ +V 1800,2000,CONT_DIF_N,403nymous_ +EOF diff --git a/pdks/symbolic/nramlib/cells/ram_sense_decad5.vbe b/pdks/symbolic/nramlib/cells/ram_sense_decad5.vbe new file mode 100644 index 000000000..f18903d07 --- /dev/null +++ b/pdks/symbolic/nramlib/cells/ram_sense_decad5.vbe @@ -0,0 +1,30 @@ +ENTITY ram_sense_decad5 IS +PORT ( + ad3 : in BIT; + ad4 : in BIT; + ad5 : in BIT; + ad6 : in BIT; + ad7 : in BIT; + ad3x : out BIT; + nad3x : out BIT; + ad4x : out BIT; + nad4x : out BIT; + ad5x : out BIT; + nad5x : out BIT; + ad6x : out BIT; + nad6x : out BIT; + ad7x : out BIT; + nad7x : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_decad5; + +ARCHITECTURE VBE OF ram_sense_decad5 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_decad5" + SEVERITY WARNING; + +END; diff --git a/pdks/symbolic/nramlib/check/__init__.py b/pdks/symbolic/nramlib/check/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/pdks/symbolic/nramlib/check/generate.py b/pdks/symbolic/nramlib/check/generate.py new file mode 100755 index 000000000..1acc57105 --- /dev/null +++ b/pdks/symbolic/nramlib/check/generate.py @@ -0,0 +1,60 @@ +#!/usr/bin/env python +# -*- coding: utf-8 -*- + +try: + import sys + import traceback + import os.path + import optparse + import Cfg + import CRL + import stratus +except ImportError, e: + serror = str(e) + if serror.startswith('No module named'): + module = serror.split()[-1] + print '[ERROR] The <%s> python module or symbol cannot be loaded.' % module + print ' Please check the integrity of the package.' + if str(e).find('cannot open shared object file'): + library = serror.split(':')[0] + print '[ERROR] The <%s> shared library cannot be loaded.' % library + print ' Under RHEL 6, you must be under devtoolset-2.' + print ' (scl enable devtoolset-2 bash)' + sys.exit(1) +except Exception, e: + print '[ERROR] A strange exception occurred while loading the basic Coriolis/Python' + print ' modules. Something may be wrong at Python/C API level.\n' + print ' %s' % e + sys.exit(2) + + +framework = CRL.AllianceFramework.get() + + +if __name__ == '__main__': + parser = optparse.OptionParser() + parser.add_option( '-b', '--bits' , type='int' , dest='bits' , help='Number of bits of each word (2 <= bits <= 64).') + parser.add_option( '-w', '--words', type='int' , dest='words' , help='Number of words in the RAM (32 <= words <= 256).') + parser.add_option( '-m', '--model', type='string', dest='model' , help='The name of the model to generate.') + parser.add_option( '-v', '--verbose' , action='store_true', dest='verbose' , help='First level of verbosity.') + parser.add_option( '-V', '--very-verbose' , action='store_true', dest='veryVerbose', help='Second level of verbosity.') + (options, args) = parser.parse_args() + + modelName = None + if options.verbose: Cfg.getParamBool('misc.verboseLevel1').setBool(True) + if options.veryVerbose: Cfg.getParamBool('misc.verboseLevel2').setBool(True) + if options.model: modelName = options.model + + print framework.getEnvironment().getPrint() + + cell = stratus.buildModel( 'dpgen_RAM' + , stratus.DoNetlist|stratus.DoLayout + , className ='DpgenRam' + , modelName = modelName + , parameters={ 'nbit' : options.bits + , 'nword' : options.words + , 'logical' : True + , 'physical' : True + } ) + + sys.exit( 0 ) diff --git a/pdks/symbolic/nramlib/check/gns/__init__.py b/pdks/symbolic/nramlib/check/gns/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/pdks/symbolic/nramlib/check/gns/bank.c b/pdks/symbolic/nramlib/check/gns/bank.c new file mode 100644 index 000000000..0ed2eb18e --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/bank.c @@ -0,0 +1,10 @@ +void bank(char *model, char *instance) +{ + begBuildCompactModel(); + + if (!gns_ModelVisited(model)) + { + gns_MarkModelVisited(model); + begSaveModel(); + } +} diff --git a/pdks/symbolic/nramlib/check/gns/bank.vhd b/pdks/symbolic/nramlib/check/gns/bank.vhd new file mode 100644 index 000000000..74525a42c --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/bank.vhd @@ -0,0 +1,37 @@ +entity bank is + generic (size, capacity, nbcolumn : integer); + port ( data_in : in bit_vector(size - 1 downto 0); + data_out : out bit_vector(size - 1 downto 0); + com : in bit_vector(capacity - 1 downto 0); + sel : in bit_vector(nbcolumn - 1 downto 0); + wen : in bit; + ck, cke, ckp : in bit; + vdd, vss : in bit); + -- pragma symmetric com + -- pragma symmetric data_in + -- pragma symmetric data_out + -- pragma symmetric sel +end; + +architecture structural of bank is + + component bit_line + generic ( capacity, nbcolumn: integer); + port ( data_in : in bit; + data_out : out bit; + com : in bit_vector(capacity - 1 downto 0); + sel : in bit_vector(nbcolumn - 1 downto 0); + wen : in bit; + ck, cke, ckp : in bit; + vdd, vss : in bit); + end component; + +begin + loop : for i in 0 to size - 1 generate + bit_line_i : bit_line + generic map ( capacity, nbcolumn) + port map ( data_in(i), data_out(i), + com(capacity-1 downto 0), sel(nbcolumn-1 downto 0), + wen, ck, cke, ckp, vdd, vss); + end generate; +end; diff --git a/pdks/symbolic/nramlib/check/gns/bit_line.c b/pdks/symbolic/nramlib/check/gns/bit_line.c new file mode 100644 index 000000000..e71ba92e5 --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/bit_line.c @@ -0,0 +1,9 @@ +/****************************************************************************/ +/* Template bit_line */ +/* behavioral actions */ +/* */ +/****************************************************************************/ +void bit_line(char *model, char *instance) +{ + begBuildCompactModel(); +} diff --git a/pdks/symbolic/nramlib/check/gns/bit_line.vhd b/pdks/symbolic/nramlib/check/gns/bit_line.vhd new file mode 100644 index 000000000..491d938ee --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/bit_line.vhd @@ -0,0 +1,54 @@ +-- +-- Template bit_line +-- Recognition rule +-- +entity bit_line is + generic ( capacity, nbcolumn : integer); + port ( data_in : in bit; + data_out : out bit; + com : in bit_vector(capacity - 1 downto 0); + sel : in bit_vector(nbcolumn - 1 downto 0); + wen : in bit; + ck, cke, ckp : in bit; + vdd, vss : in bit); + -- pragma symmetric com + -- pragma symmetric sel +end; + +architecture structural of bit_line is + component column_and_sel + generic ( capacity : integer); + port ( q, nq : inout mux_bit bus; + com : in bit_vector(capacity - 1 downto 0); + ck : in bit; + sel_column : in bit; + vdd, vss : in bit); + end component; + + component sense_amplifier + port ( data, ndata : in bit; + cke, ckp : in bit; + data_out : out bit; + vdd, vss : in bit); + end component; + + component column_input + port ( datain, wen, ckp : in bit; + q, nq : inout bit; + vdd,vss : in bit); + end component; + + signal nq, q : bit; + +begin + loop : for i in nbcolumn-1 downto 0 generate + CSEL : column_and_sel generic map(capacity) + port map (q, nq, com(capacity-1 downto 0), ck, sel(i), vdd, vss); + end generate; + + SA : sense_amplifier + port map (q, nq, cke, ckp, data_out, vdd, vss); + + CI : column_input + port map (data_in, wen, ckp, q, nq, vdd, vss); +end; diff --git a/pdks/symbolic/nramlib/check/gns/bl_precharge.c b/pdks/symbolic/nramlib/check/gns/bl_precharge.c new file mode 100644 index 000000000..f41701aa3 --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/bl_precharge.c @@ -0,0 +1,18 @@ +/****************************************************************************/ +/* Template bl_precharge */ +/* behavioral actions */ +/* */ +/****************************************************************************/ +void bl_precharge() +{ + char * q = _equiv("q"); + char * nq = _equiv("nq"); + char * ck = _equiv("ck"); + + begCreateInterface(); + + begAddMemDriver(nq, ck, "'1'", 0, NULL); + begAddMemDriver(q, ck, "'1'", 0, NULL); + + begKeepModel(); +} diff --git a/pdks/symbolic/nramlib/check/gns/bl_precharge.vhd b/pdks/symbolic/nramlib/check/gns/bl_precharge.vhd new file mode 100644 index 000000000..a21b44e63 --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/bl_precharge.vhd @@ -0,0 +1,24 @@ +-- +-- Template bl_precharge +-- Recognition rule +-- +entity bl_precharge is + port ( q, nq : inout bit; + ck : in bit; + vdd, vss : in bit); + -- pragma symmetric q nq +end; + +architecture structural of bl_precharge is + component tn + port ( gate : in bit; + source, drain : inout bit; + bulk : in bit); + end component; + +begin + tn_1 : tn port map (ck ,q ,vdd ,vss); + tn_2 : tn port map (ck ,nq ,vdd ,vss); + tn_3 : tn port map (ck ,q ,nq ,vss); + +end; diff --git a/pdks/symbolic/nramlib/check/gns/col.c b/pdks/symbolic/nramlib/check/gns/col.c new file mode 100644 index 000000000..78afbf0ad --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/col.c @@ -0,0 +1,4 @@ +void col() +{ + printf("j'execute col.c\n"); +} diff --git a/pdks/symbolic/nramlib/check/gns/column.c b/pdks/symbolic/nramlib/check/gns/column.c new file mode 100644 index 000000000..8d8a2be92 --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/column.c @@ -0,0 +1,9 @@ +/****************************************************************************/ +/* Template Column */ +/* behavioral actions */ +/* */ +/****************************************************************************/ +void column() +{ + begBuildCompactModel(); +} diff --git a/pdks/symbolic/nramlib/check/gns/column.vhd b/pdks/symbolic/nramlib/check/gns/column.vhd new file mode 100644 index 000000000..e6fdcc208 --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/column.vhd @@ -0,0 +1,29 @@ +-- +-- Template column +-- Recognition rule +-- +-- capacity is the number of mem_cell composing column +-- +entity column is + generic ( capacity : integer); + port ( q,nq : inout mux_bit bus; + com : in bit_vector(capacity-1 downto 0); + vdd,vss : in bit); + -- pragma symmetric q nq + -- pragma symmetric com +end; + + +architecture structural of column is + component mem_cell + port ( q, nq : inout mux_bit bus; + com : in bit; + vdd, vss : in bit); + end component; + +begin + loop: for i in 0 to capacity-1 generate + mem : mem_cell port map ( q ,nq ,com(i) ,vdd ,vss); + end generate; + +end; diff --git a/pdks/symbolic/nramlib/check/gns/column_and_prech.c b/pdks/symbolic/nramlib/check/gns/column_and_prech.c new file mode 100644 index 000000000..793c9897c --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/column_and_prech.c @@ -0,0 +1,21 @@ +/****************************************************************************/ +/* Template column_and_prech */ +/* behavioral actions */ +/* */ +/****************************************************************************/ +void column_and_prech() +{ + char * nq = _equiv("nq"); + char * q = _equiv("q"); + char * ck = _equiv("ck"); + + begCreateInterface(); + + // precharge + begAddMemDriver(nq ,ck ,"'1'" ,0 ,NULL); + begAddMemDriver(q ,ck ,"'1'" ,0 ,NULL); + + begAddAllInstanceModels(); + + begKeepModel(); +} diff --git a/pdks/symbolic/nramlib/check/gns/column_and_prech.vhd b/pdks/symbolic/nramlib/check/gns/column_and_prech.vhd new file mode 100644 index 000000000..430fdc85f --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/column_and_prech.vhd @@ -0,0 +1,39 @@ +-- +-- Template column_and_prech +-- Recognition rule +-- +entity column_and_prech is + generic ( capacity : integer); + port ( q, nq : inout mux_bit bus; + com : in bit_vector(capacity-1 downto 0); + ck : in bit; + vdd, vss : in bit); + -- pragma symmetric q nq + -- pragma symmetric com +end; + +architecture structural of column_and_prech is + component column + generic ( capacity : integer); + port ( q, nq : inout mux_bit bus; + com : in bit_vector(capacity-1 downto 0); + vdd, vss : in bit); + end component; + + component TN + port ( gate : in bit; + source, drain : inout bit; + bulk : in bit); + end component; + +begin + + col : column + generic map(capacity) + port map (q ,nq ,com ,vdd ,vss); + + precharge_t1 : TN port map (ck, nq, vdd, vss); + precharge_t2 : TN port map (ck, q, vdd, vss); + precharge_t3 : TN port map (ck, q, nq, vss); + +end; diff --git a/pdks/symbolic/nramlib/check/gns/column_and_sel.c b/pdks/symbolic/nramlib/check/gns/column_and_sel.c new file mode 100644 index 000000000..1ea3a2f7b --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/column_and_sel.c @@ -0,0 +1,30 @@ +/****************************************************************************/ +/* Template column_and_sel */ +/* behavioral actions */ +/* */ +/****************************************************************************/ +void column_and_sel() +{ + char * nq = _equiv("nq"); + char * q = _equiv("q"); + char * na = _equiv("na"); + char * a = _equiv("a"); + char * ck = _equiv("ck"); + char * sel = _equiv("sel"); + + begCreateInterface(); + + // pass-transistor + begAddMemDriver(nq, sel, na, 0, NULL); + begAddMemDriver(q, sel, a, 0, NULL); + begAddMemDriver(na, sel, nq, 0, NULL); + begAddMemDriver(a, sel, q, 0, NULL); + + // precharge + begAddMemDriver(nq, ck, "'1'", 0, NULL); + begAddMemDriver(q, ck, "'1'", 0, NULL); + + begAddAllInstanceModels(); + + begKeepModel(); +} diff --git a/pdks/symbolic/nramlib/check/gns/column_and_sel.vhd b/pdks/symbolic/nramlib/check/gns/column_and_sel.vhd new file mode 100644 index 000000000..e7d56d0b5 --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/column_and_sel.vhd @@ -0,0 +1,46 @@ +-- +-- Template column_and_sel +-- Recognition rule +-- +entity column_and_sel is + generic ( capacity : integer); + port ( q, nq : inout mux_bit bus; + com : in bit_vector(capacity-1 downto 0); + ck : in bit; + sel : in bit; + vdd, vss : in bit); + -- pragma symmetric q nq + -- pragma symmetric com +end; + +architecture structural of column_and_sel is + component column + generic ( capacity : integer); + port ( q, nq : inout mux_bit bus; + com : in bit_vector(capacity-1 downto 0); + vdd, vss : in bit); + end component; + + component TN + port ( gate : in bit; + source, drain : inout bit; + bulk : in bit); + end component; + + signal a, na, PCsig : bit; + +begin + + col : column + generic map(capacity) + port map (a ,na ,com ,vdd ,vss); + + -- pass transistors + t1 : TN port map (sel ,a ,q ,vss); + t2 : TN port map (sel ,na ,nq ,vss); + + precharge_t1 : TN port map (ck, na, vdd, vss); + precharge_t2 : TN port map (ck, a, vdd, vss); + precharge_t3 : TN port map (ck, a, na, vss); + +end; diff --git a/pdks/symbolic/nramlib/check/gns/column_input.c b/pdks/symbolic/nramlib/check/gns/column_input.c new file mode 100644 index 000000000..7e4cec8e0 --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/column_input.c @@ -0,0 +1,28 @@ +/****************************************************************************/ +/* Template Column_input */ +/* behavioral actions */ +/* */ +/****************************************************************************/ +void column_input() +{ + char * nq = _equiv("nq"); + char * q = _equiv("q"); + char * wen = _equiv("wen"); + char * din = _equiv("datain"); + char * ckp = _equiv("ckp"); + char data[1024]; + + + begCreateInterface(); + + begAddMemDriver(q, wen, din, 0, NULL); + + sprintf(data,"not(%s)",din); + begAddMemDriver(nq, wen, data, 0, NULL); + + // precharge + begAddMemDriver(q, ckp, "'1'", 0, NULL); + begAddMemDriver(nq, ckp, "'1'", 0, NULL); + + begKeepModel(); +} diff --git a/pdks/symbolic/nramlib/check/gns/column_input.vhd b/pdks/symbolic/nramlib/check/gns/column_input.vhd new file mode 100644 index 000000000..6c1b84fcc --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/column_input.vhd @@ -0,0 +1,44 @@ +-- +-- Template column_input +-- Recognition rule +-- +entity column_input is + port ( datain, wen, ckp : in bit; + q, nq : inout bit; + vdd,vss : in bit); +end; + +architecture precharge_included of column_input is + component tn + port ( gate : in bit; + source : inout bit; + drain : inout bit; + bulk : in bit); + end component; + + component tp + port ( gate : in bit; + source : inout bit; + drain : inout bit; + bulk : in bit); + end component; + + signal nsig, nsig2, sig, PCsig : bit; + +begin + inv_tn : tn port map ( datain ,vss ,nsig ,vss); + inv_tp : tp port map ( datain ,vdd ,nsig ,vdd); + + buf_tn1 : tn port map ( datain ,vss ,nsig2 ,vss); + buf_tp1 : tp port map ( datain ,vdd ,nsig2 ,vdd); + buf_tn2 : tn port map ( nsig2 ,vss ,sig ,vss); + buf_tp2 : tp port map ( nsig2 ,vdd ,sig ,vdd); + + precharge_tn1 : tn port map ( ckp ,nq ,vdd ,vss); + precharge_tn2 : tn port map ( ckp ,q ,vdd ,vss); + precharge_tn3 : tn port map ( ckp ,nq ,q ,vss); + + write_q : tn port map ( wen ,nq ,nsig ,vss); + write_nq : tn port map ( wen ,q ,sig ,vss); + +end; diff --git a/pdks/symbolic/nramlib/check/gns/column_xn.c b/pdks/symbolic/nramlib/check/gns/column_xn.c new file mode 100644 index 000000000..947702504 --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/column_xn.c @@ -0,0 +1,9 @@ +/****************************************************************************/ +/* Template Column_xn */ +/* behavioral actions */ +/* */ +/****************************************************************************/ +void column_xn() +{ + begBuildCompactModel(); +} diff --git a/pdks/symbolic/nramlib/check/gns/column_xn.vhd b/pdks/symbolic/nramlib/check/gns/column_xn.vhd new file mode 100644 index 000000000..0c2fd876a --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/column_xn.vhd @@ -0,0 +1,33 @@ +-- +-- Template column_xn +-- Recognition rule +-- +-- capacity is the number of mem_cell composing column +-- width is the number of column composing column_xn +-- +-- +entity column_xn is + generic ( size, width : integer); + port ( com : in bit_vector(size-1 downto 0); + q, nq : inout mux_vector(width-1 downto 0) bus; + vdd,gnd : in bit); + -- pragma symmetric com + -- pragma symmetric q(i) nq(i) +end; + +architecture structural of column_xn is + component column + generic ( capacity : integer); + port ( q, nq : inout mux_bit bus; + com : in bit_vector(capacity-1 downto 0); + vdd, gnd : in bit); + end component; + +begin + loop: for i in width-1 downto 0 generate + column_n : column + generic map (size) + port map (q(i) ,nq(i) ,com ,vdd ,gnd); + end generate; + +end; diff --git a/pdks/symbolic/nramlib/check/gns/differential_amplifier.c b/pdks/symbolic/nramlib/check/gns/differential_amplifier.c new file mode 100644 index 000000000..e69de29bb diff --git a/pdks/symbolic/nramlib/check/gns/differential_amplifier.vhd b/pdks/symbolic/nramlib/check/gns/differential_amplifier.vhd new file mode 100644 index 000000000..cb5175dad --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/differential_amplifier.vhd @@ -0,0 +1,47 @@ +-- +-- Template differential_amplifier +-- Recognition rule +-- +-- ^ ^ +-- | | +-- ]o--o---o[ +-- | | | +-- sig o----+ o-- x +-- | | +-- i_1 -[ ]- i_2 +-- | | +-- o----------+ +-- | +-- g ----+ +-- +entity differential_amplifier is + port ( i_1, i_2 : in bit; + g : in bit; + x : out bit; + vdd, vss : in bit); +end; + +architecture structural of differential_amplifier is + component TP + port ( gate : in bit; + source,drain : inout bit; + bulk : in bit); + end component; + + component TN + port ( gate : in bit; + source,drain : inout bit; + bulk : in bit); + end component; + + signal sig : bit; + +begin + tn_1 : TN port map (i_1 ,sig ,g ,vss); + tn_2 : TN port map (i_2 ,x ,g ,vss); + tp_1 : TP port map (sig ,x ,vdd ,vdd); + tp_2 : TP port map (sig ,sig ,vdd ,vdd); + +end; + + diff --git a/pdks/symbolic/nramlib/check/gns/mem_cell.c b/pdks/symbolic/nramlib/check/gns/mem_cell.c new file mode 100644 index 000000000..01504f21c --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/mem_cell.c @@ -0,0 +1,99 @@ +/****************************************************************************/ +/* Template mem_cell */ +/* behavioral actions */ +/* */ +/* This action describe the behavior of a mem_cell */ +/* */ +/* */ +/* */ +/* */ +/****************************************************************************/ +void mem_cell() +{ + char * mem = _equiv("mem"); + char * nmem = _equiv("nmem"); + char * q = _equiv("q"); + char * nq = _equiv("nq"); + char * com = _equiv("com"); + char * din_mem_delay = _equiv("din_mem_delay"); + char *com_dout_delay = _equiv("com_dout_delay"); + char command[1024]; + + begCreateInterface (); + + // IF (com AND (q AND NOT nq)) + // mem <= '1' AFTER din_mem_delay; + // IF (com AND (NOT q AND nq)) + // mem <= '0' AFTER din_mem_delay; + sprintf(command,"%s and (%s and not %s)", com, q, nq); + begAddMemDriver(mem , command, "'1'", 0, din_mem_delay); + sprintf(command,"%s and (not %s and %s)", com, q, nq); + begAddMemElse (mem , command, "'0'", 0, din_mem_delay); + + // IF (com AND com'EVENT) + // IF (mem) + // q <= '1' AFTER com_dout_delay; + // ELSIF (NOT mem) + // q <= '0' + sprintf(command,"%s and %s and %s'event", com, mem, com); + begAddMemDriver(q , command, "'1'", 0, com_dout_delay); + sprintf(command,"%s and not %s and %s'event", com, mem, com); + begAddMemElse (q , command, "'0'", 0, com_dout_delay); + + // IF (com AND com'EVENT) + // IF (mem) + // nq <= '0' AFTER com_dout_delay; + // ELSIF (NOT mem) + // nq <= '1' + sprintf(command,"%s and %s and %s'event", com, mem, com); + begAddMemDriver(nq ,command , "'0'", 0, com_dout_delay); + sprintf(command,"%s and not %s and %s'event", com, mem, com); + begAddMemElse (nq , command, "'1'", 0, com_dout_delay); + + begKeepModel (); +} + +void mem_cell_noevent() +{ + char * mem = _equiv("mem"); + char * nmem = _equiv("nmem"); + char * q = _equiv("q"); + char * nq = _equiv("nq"); + char * com = _equiv("com"); + char * din_mem_delay = _equiv("din_mem_delay"); + char *com_dout_delay = _equiv("com_dout_delay"); + char command[1024]; + + begCreateInterface (); + + // IF (com AND (q AND NOT nq)) + // mem <= '1' AFTER din_mem_delay; + // IF (com AND (NOT q AND nq)) + // mem <= '0' AFTER din_mem_delay; + sprintf(command,"%s and (%s and not %s)", com, q, nq); + begAddMemDriver(mem , command, "'1'", 0, din_mem_delay); + sprintf(command,"%s and (not %s and %s)", com, q, nq); + begAddMemElse (mem , command, "'0'", 0, din_mem_delay); + + // IF (com AND com'EVENT) + // IF (mem) + // q <= '1' AFTER com_dout_delay; + // ELSIF (NOT mem) + // q <= '0' + sprintf(command,"%s and %s", com, mem); + begAddMemDriver(q , command, "'1'", 0, com_dout_delay); + sprintf(command,"%s and not %s", com, mem); + begAddMemElse (q , command, "'0'", 0, com_dout_delay); + + // IF (com AND com'EVENT) + // IF (mem) + // nq <= '0' AFTER com_dout_delay; + // ELSIF (NOT mem) + // nq <= '1' + sprintf(command,"%s and %s", com, mem); + begAddMemDriver(nq ,command , "'0'", 0, com_dout_delay); + sprintf(command,"%s and not %s", com, mem); + begAddMemElse (nq , command, "'1'", 0, com_dout_delay); + + begKeepModel (); +} diff --git a/pdks/symbolic/nramlib/check/gns/mem_cell.vhd b/pdks/symbolic/nramlib/check/gns/mem_cell.vhd new file mode 100644 index 000000000..122fc036c --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/mem_cell.vhd @@ -0,0 +1,36 @@ +-- +-- Template mem_cell +-- Recognition rule +-- +entity mem_cell is + port ( q, nq : inout mux_bit bus; + com : in bit; + vdd, vss : in bit); + -- pragma symmetric q nq +end mem_cell; + +architecture structural of mem_cell is + component tn + port ( gate : in bit; + source, drain : inout bit; + bulk : in bit); + end component; + + component tp + port ( gate : in bit; + source, drain : inout bit; + bulk : in bit); + end component; + + signal mem : bit; + signal nmem : bit; + +begin + tn_1 : tn port map (nmem ,vss ,mem ,vss); + tn_2 : tn port map (com ,q ,mem ,vss); + tn_3 : tn port map (mem ,vss ,nmem ,vss); + tn_4 : tn port map (com ,nq ,nmem ,vss); + tp_5 : tp port map (nmem ,vdd ,mem ,vdd); + tp_6 : tp port map (mem ,vdd ,nmem ,vdd); + +end; diff --git a/pdks/symbolic/nramlib/check/gns/methodology_common.c b/pdks/symbolic/nramlib/check/gns/methodology_common.c new file mode 100644 index 000000000..c58f70de2 --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/methodology_common.c @@ -0,0 +1,83 @@ +/****************************************************************************/ +/* Template for use of progammed timing models */ +/* METHODOLOGY FUNCTIONS */ +/* */ +/****************************************************************************/ + +int METHODOLOGY_ENABLE_ROUNDING=0; +int METHODOLOGY_TRACE=0; +double METHODOLOGY_SLOPE_ROUNDING=5e-12; +double METHODOLOGY_CAPA_ROUNDING=1e-15; + +/****************************************************************************/ +/* Table based cache with interpolation to */ +/* reduce computations */ +/****************************************************************************/ + +void METHODOLOGY_CommonModel_TABLE() +{ + double threshold = 20.0; + double input_slope=GET_INPUT_SLOPE(), output_capa=GET_OUTPUT_CAPA(); + + if (METHODOLOGY_ENABLE_ROUNDING) + { + input_slope=stm_arround(input_slope, METHODOLOGY_SLOPE_ROUNDING); + output_capa=stm_arround(output_capa, METHODOLOGY_CAPA_ROUNDING); + } + + if (!stm_delayThresholdOK(input_slope, output_capa, threshold) + && !stm_slopeThresholdOK(input_slope, output_capa, threshold)) + { + CALL_SIMULATION(); + stm_sup_storeDelay(GET_DELAY()); + stm_sup_storeSlope(GET_SLOPE()); + } + else + { + SET_DELAY(stm_sup_getDelay()); + SET_SLOPE(stm_sup_getSlope()); + if (METHODOLOGY_TRACE) + printf("CACHE Request(InputSlope=%g OutputCapa=%g) => delay=%g, slope=%g\n",GET_INPUT_SLOPE(), GET_OUTPUT_CAPA(),GET_DELAY(), GET_SLOPE()); + } +} + +/****************************************************************************/ +/* Simple cache based on stored values */ +/* for previously computed values */ +/****************************************************************************/ + +void METHODOLOGY_CommonModel_SIMPLECACHE(char *ID) +{ + double input_slope=GET_INPUT_SLOPE(), output_capa=GET_OUTPUT_CAPA(); + double res_slope, res_delay; + char bufs[128]; + char bufd[128]; + + if (METHODOLOGY_ENABLE_ROUNDING) + { + input_slope=stm_arround(input_slope, METHODOLOGY_SLOPE_ROUNDING); + output_capa=stm_arround(output_capa, METHODOLOGY_CAPA_ROUNDING); + } + + dtb_Create("METHODOLOGY_SIMPLECACHE"); + + sprintf(bufs,"%s%g%g_slope", ID, input_slope, output_capa); + sprintf(bufd,"%s%g%g_slope", ID, input_slope, output_capa); + res_slope=dtb_GetDouble("METHODOLOGY_SIMPLECACHE", bufs); + res_delay=dtb_GetDouble("METHODOLOGY_SIMPLECACHE", bufd); + + if (res_slope!=0.0) + { + SET_DELAY(res_delay); + SET_SLOPE(res_slope); + if (METHODOLOGY_TRACE) + printf("CACHE Request(InputSlope=%g OutputCapa=%g) => delay=%g, slope=%g\n",GET_INPUT_SLOPE(), GET_OUTPUT_CAPA(),GET_DELAY(), GET_SLOPE()); + } + else + { + CALL_SIMULATION(); + dtb_SetDouble("METHODOLOGY_SIMPLECACHE", bufs, GET_SLOPE()); + dtb_SetDouble("METHODOLOGY_SIMPLECACHE", bufd, GET_DELAY()); + } +} + diff --git a/pdks/symbolic/nramlib/check/gns/sense_amplifier.c b/pdks/symbolic/nramlib/check/gns/sense_amplifier.c new file mode 100644 index 000000000..b702d9d90 --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/sense_amplifier.c @@ -0,0 +1,28 @@ +/****************************************************************************/ +/* Template sense_amplifier */ +/* behavioral actions */ +/* */ +/****************************************************************************/ +void sense_amplifier() +{ + char *ndata = _equiv("ndata"); + char * data = _equiv("data"); + char * cke = _equiv("cke"); + char * X = _equiv("X"); + char * ckp = _equiv("ckp"); + char command[1024]; + + + begCreateInterface(); + + sprintf(command,"%s and %s and not(%s)",cke,data,ndata); + begAddMemDriver(X, command, "'1'", 0, NULL); + + sprintf(command,"%s and not(%s) and %s",cke,data,ndata); + begAddMemDriver(X, command, "'0'", 0, NULL); + + begAddMemDriver(ndata, ckp, "'1'", 0, NULL); + begAddMemDriver(data, ckp, "'1'", 0, NULL); + + begKeepModel(); +} diff --git a/pdks/symbolic/nramlib/check/gns/sense_amplifier.vhd b/pdks/symbolic/nramlib/check/gns/sense_amplifier.vhd new file mode 100644 index 000000000..789c8b5e3 --- /dev/null +++ b/pdks/symbolic/nramlib/check/gns/sense_amplifier.vhd @@ -0,0 +1,83 @@ +-- +-- Template sense_amplifier +-- Recognition rule +-- +entity sense_amplifier is + port ( data, ndata : in bit; + cke, ckp : in bit; + X : out bit; + vdd, vss : in bit); +end; + +architecture template of sense_amplifier is + component differential_amplifier + port ( i_1, i_2 : in bit; + g : in bit; + x : out bit; + vdd, vss : in bit); + end component; + + component TN + port ( gate : in bit; + source,drain : inout bit; + bulk : in bit); + end component; + + signal g1, g2, g3, x1, x2 : bit; + +begin + tn_1 : TN port map (cke ,g1 ,vss ,vss); + DA_1 : differential_amplifier port map ( ndata ,data ,g1 ,x1 ,vdd ,vss); + + tn_2 : TN port map (cke ,g2 ,vss ,vss); + DA_2 : differential_amplifier port map ( data ,ndata ,g2 ,x2 ,vdd ,vss); + + tn_3 : TN port map (cke ,g3 ,vss ,vss); + DA_3 : differential_amplifier port map ( x1, x2, g3, X, vdd, vss); + + link : TN port map (ckp ,x2 ,x1 ,vss); + +end; + +architecture mixt of sense_amplifier is + component differential_amplifier + port ( i_1, i_2 : in bit; + g : in bit; + x : out bit; + vdd, vss : in bit); + end component; + + component TP + port ( gate : in bit; + source,drain : inout bit; + bulk : in bit); + end component; + + component TN + port ( gate : in bit; + source,drain : inout bit; + bulk : in bit); + end component; + + signal g1, g2, g3, x1, x2, sig1, sig2 : bit; + +begin + tn_1 : TN port map (cke ,g1 ,vss ,vss); + custom_amp_1_tp1 : TP port map (sig1 ,sig1 ,vdd ,vdd); + custom_amp_1_tp2 : TP port map (sig1 ,x1 ,vdd ,vdd); + custom_amp_1_tn1 : TN port map (ndata ,g1 ,sig1 ,vss); + custom_amp_1_tn2 : TN port map (data ,x1 ,g2 ,vss); + + tn_2 : TN port map (cke ,g2 ,vss ,vss); + custom_amp_2_tp1 : TP port map (sig2 ,sig2 ,vdd ,vdd); + custom_amp_2_tp2 : TP port map (sig2 ,x2 ,vdd ,vdd); + custom_amp_2_tn1 : TN port map (data ,g1 ,sig2 ,vss); + custom_amp_2_tn2 : TN port map (ndata ,x2 ,g2 ,vss); + + tn_3 : TN port map (cke ,g3 ,vss ,vss); + DA : differential_amplifier port map ( x1, x2, g3, X, vdd, vss); + + -- pass transistor + PT : TN port map (ckp ,x2 ,x1 ,vss); + +end; diff --git a/pdks/symbolic/nramlib/check/scaleCell.py b/pdks/symbolic/nramlib/check/scaleCell.py new file mode 100755 index 000000000..809aad57b --- /dev/null +++ b/pdks/symbolic/nramlib/check/scaleCell.py @@ -0,0 +1,322 @@ +#!/usr/bin/env python +# -*- coding: utf-8; explicit-buffer-name: "scaleCell.py" -*- + +try: + import sys + import traceback + import os.path + import shutil + import optparse + import math + import Cfg + import Hurricane + from Hurricane import DataBase + from Hurricane import DbU + from Hurricane import Transformation + from Hurricane import Box + from Hurricane import UpdateSession + from Hurricane import Breakpoint + from Hurricane import Net + from Hurricane import NetExternalComponents + from Hurricane import BasicLayer + from Hurricane import ContactLayer + from Hurricane import ViaLayer + from Hurricane import RegularLayer + from Hurricane import TransistorLayer + from Hurricane import DiffusionLayer + from Hurricane import Cell + from Hurricane import Instance + from Hurricane import Net + from Hurricane import Contact + from Hurricane import Horizontal + from Hurricane import Vertical + import Viewer + import CRL + from CRL import RoutingLayerGauge + import helpers + from helpers import trace + from helpers import ErrorMessage +except ImportError, e: + serror = str(e) + if serror.startswith('No module named'): + module = serror.split()[-1] + print '[ERROR] The <%s> python module or symbol cannot be loaded.' % module + print ' Please check the integrity of the package.' + if str(e).find('cannot open shared object file'): + library = serror.split(':')[0] + print '[ERROR] The <%s> shared library cannot be loaded.' % library + print ' Under RHEL 6, you must be under devtoolset-2.' + print ' (scl enable devtoolset-2 bash)' + sys.exit(1) +except Exception, e: + print '[ERROR] A strange exception occurred while loading the basic Coriolis/Python' + print ' modules. Something may be wrong at Python/C API level.\n' + print ' %s' % e + sys.exit(2) + + +framework = CRL.AllianceFramework.get() +scale = 2 + + +def getDeltas ( layer ): + # | Layer | Min W | Delta W | Delta L | + # +---------------+-------+---------+---------+ + deltas = { 'NWELL' : ( 999.0 , 12.0 , 6.0 ) + , 'PWELL' : ( 999.0 , 12.0 , 6.0 ) + , 'NDIF' : ( 999.0 , 0.0 , -1.0 ) + , 'PDIF' : ( 999.0 , 0.0 , -1.0 ) + , 'NTIE' : ( 999.0 , 0.0 , 1.2 ) + , 'PTIE' : ( 999.0 , 0.0 , 1.2 ) + , 'NTRANS' : ( 999.0 , 0.0 , -3.0 ) + , 'PTRANS' : ( 999.0 , 0.0 , -3.0 ) + , 'POLY' : ( 999.0 , 0.0 , 0.0 ) + , 'METAL1' : ( 1.5 , 1.0 , -1.0 ) + , 'METAL2' : ( 999.0 , 2.0 , 1.5 ) + #, 'METAL3' : ( 2.0 , 2.0 , 1.5 ) + , 'METAL3' : ( 999.0 , 0.0 , 1.5 ) + , 'BLOCKAGE1' : ( 999.0 , 0.0 , 0.0 ) + , 'BLOCKAGE2' : ( 999.0 , -1.0 , -0.5 ) + , 'BLOCKAGE3' : ( 999.0 , -1.0 , -0.5 ) + , 'BLOCKAGE4' : ( 999.0 , -1.0 , -0.5 ) + } + + dbuLayerDeltas = ( 0, 0, 0 ) + if deltas.has_key(layer.getName()): + deltas = deltas[ layer.getName() ] + dbuLayerDeltas = DbU.fromLambda(deltas[0]), DbU.fromLambda(deltas[1]), DbU.fromLambda(deltas[2]) + else: + print '[WARNING] Layer \"%s\" has no deltas corrections.' % layer.getName() + + return dbuLayerDeltas + + +def scaleCell ( editor, sourceCell ): + global framework + global scale + + if sourceCell == None: + raise ErrorMessage( 3, 'scaleCell.scaleCell(): Mandatory sourceCell argument is None.' ) + scaledCell = None + + print '\n o Processing', sourceCell + + UpdateSession.open() + try: + library = framework.getLibrary( 0 ) + scaledCell = Cell.create( library, sourceCell.getName() ) + + ab = sourceCell.getAbutmentBox() + scaledCell.setAbutmentBox( Box( ab.getXMin()*scale, ab.getYMin()*scale + , ab.getXMax()*scale, ab.getYMax()*scale ) ) + + for net in sourceCell.getNets(): + scaledNet = Net.create( scaledCell, net.getName() ) + if net.isExternal(): scaledNet.setExternal( True ) + if net.isGlobal (): scaledNet.setGlobal ( True ) + scaledNet.setType ( net.getType () ) + scaledNet.setDirection( net.getDirection() ) + + for component in net.getComponents(): + layer = component.getLayer() + dupComponent = None + + if isinstance(component,Contact): + # Default VIAs get their size through the parser. So they + # are already scaled (to the minimal size). + dupComponent = Contact.create( scaledNet + , layer + , component.getX ()*scale + , component.getY ()*scale + , component.getWidth () # *scale + , component.getHeight() # *scale + ) + print ' |', dupComponent + elif isinstance(component,Horizontal): + mW, dW, dL = getDeltas( layer ) + + if component.getLayer().getName() == 'METAL1' \ + and component.getWidth() == DbU.fromLambda(2.0): + print '[INFO] Shrinking METAL1 of 2l width to default contact width.' + print ' %s' % component + mW = DbU.fromLambda( 2.0) + dW = DbU.fromLambda(-1.0) + + if component.getLayer().getName() == 'METAL3' \ + and component.getSourceX() == component.getTargetX(): + print '[WARNING] Rotating badly oriented METAL3 terminal (H -> V).' + print ' %s' % component + + width = component.getWidth()*scale + #if component.getWidth() <= mW: width += dW + + dupComponent = Vertical.create( scaledNet + , layer + , component.getSourceX()*scale + , width + , component.getY()*scale - dL + , component.getY()*scale + dL + ) + print ' |', dupComponent + + else: + if component.getSourceX() > component.getTargetX(): component.invert() + bb = component.getBoundingBox() + + width = component.getWidth()*scale + if component.getWidth() <= mW: width += dW + + if width > 0 and ( (dL > 0) or (bb.getWidth()*scale > abs(2*dL)) ): + dupComponent = Horizontal.create( scaledNet + , layer + , component.getY ()*scale + , width + , component.getDxSource()*scale - dL + , component.getDxTarget()*scale + dL + ) + print ' |', dupComponent + else: + print '[WARNING] Horizontal component too small *or* skipped, not converted.' + + elif isinstance(component,Vertical): + custom_dX = 0 + if sourceCell.getName() == 'ram_sense_decad12': + if component.getLayer().getName() == 'NDIF': + if component.getSourceY() == DbU.fromLambda( 3.0) \ + and component.getTargetY() == DbU.fromLambda( 12.0) \ + and component.getX() == DbU.fromLambda(153.0) \ + and component.getWidth() == DbU.fromLambda( 5.0): + print '[INFO] Shifted left NDIF segment %s.' % component + custom_dX = DbU.fromLambda(-1.0) + if component.getLayer().getName() == 'PDIF': + if component.getSourceY() == DbU.fromLambda( 28.0) \ + and component.getTargetY() == DbU.fromLambda( 47.0) \ + and component.getX() == DbU.fromLambda(153.0) \ + and component.getWidth() == DbU.fromLambda( 5.0): + print '[INFO] Shifted left PDIF segment %s.' % component + custom_dX = DbU.fromLambda(-1.0) + + mW, dW, dL = getDeltas( component.getLayer() ) + + if component.getLayer().getName() == 'METAL1' \ + and component.getWidth() == DbU.fromLambda(2.0): + print '[INFO] Shrinking METAL1 of 2l width to default contact width.' + print ' %s' % component + mW = DbU.fromLambda( 2.0) + dW = DbU.fromLambda(-1.0) + + if component.getSourceY() > component.getTargetY(): component.invert() + bb = component.getBoundingBox() + + width = component.getWidth()*scale + if component.getWidth() <= mW: width += dW + + if width > 0 and ( (dL > 0) or (bb.getHeight()*scale > abs(2*dL)) ): + dupComponent = Vertical.create( scaledNet + , layer + , component.getX ()*scale + custom_dX + , width + , component.getDySource()*scale - dL + , component.getDyTarget()*scale + dL + ) + print ' |', dupComponent + else: + print '[WARNING] Vertical component too small *or* skipped, not converted.' + + else: + print '[WARNING] Unchanged component:', component + + if dupComponent and NetExternalComponents.isExternal( component ): + NetExternalComponents.setExternal( dupComponent ) + + except ErrorMessage, e: + print e; errorCode = e.code + except Exception, e: + print '\n\n', e; errorCode = 1 + traceback.print_tb(sys.exc_info()[2]) + + UpdateSession.close() + if scaledCell: + framework.saveCell( scaledCell, CRL.Catalog.State.Physical ) + if editor: + editor.setCell( scaledCell ) + editor.fit() + + return scaledCell + + +def scriptMain ( **kw ): + global framework + + helpers.staticInitialization( quiet=True ) + #helpers.setTraceLevel( 550 ) + + scaledDir = framework.getAllianceLibrary(0).getPath() + alibrary = framework.getAllianceLibrary(1) + if not alibrary: + print '[ERROR] No Library at index 1, please check SYSTEM_LIBRARY in settings.py.' + return 1 + + hasCatal = False + apCount = 0 + vbeCount = 0 + for file in os.listdir( scaledDir ): + if file == 'CATAL': hasCatal = True + if file[-4:] == '.vbe': vbeCount += 1 + if file[-3:] == '.ap': apCount += 1 + + if hasCatal or vbeCount or apCount: + print '[ERROR] Target directory already contains CATAL/.vbe/.ap files.' + print ' You must remove them before proceeding with this script.' + print ' (%s)' % scaledDir + return 1 + + sourceCell = None + if kw.has_key('cell') and kw['cell']: + sourceCell = kw['cell'] + + editor = None + if kw.has_key('editor') and kw['editor']: + editor = kw['editor'] + print ' o Editor detected, running in graphic mode.' + if sourceCell == None: sourceCell = editor.getCell() + + if sourceCell: + scaledCell = scaleCell( editor, sourceCell ) + else: + print ' o Processing library "%s".' % alibrary.getLibrary().getName() + print ' (path:%s)' % alibrary.getPath() + framework.loadLibraryCells( alibrary.getLibrary() ) + for sourceCell in alibrary.getLibrary().getCells(): + scaledCell = scaleCell( editor, sourceCell ) + + print '' + print ' o Direct copy of ".vbe" & CATAL files.' + for file in os.listdir( alibrary.getPath() ): + if file == 'CATAL' or file[-4:] == '.vbe': + print ' | %s' % file + shutil.copy( alibrary.getPath()+'/'+file, scaledDir ) + + return 0 + + +if __name__ == '__main__': + parser = optparse.OptionParser() + parser.add_option( '-c', '--cell', type='string', dest='cell' , help='The name of the chip to build, whithout extension.') + parser.add_option( '-v', '--verbose' , action='store_true', dest='verbose' , help='First level of verbosity.') + parser.add_option( '-V', '--very-verbose' , action='store_true', dest='veryVerbose', help='Second level of verbosity.') + (options, args) = parser.parse_args() + + kw = {} + if options.cell: + kw['cell'] = framework.getCell( options.cell, CRL.Catalog.State.Views ) + if options.verbose: Cfg.getParamBool('misc.verboseLevel1').setBool(True) + if options.veryVerbose: Cfg.getParamBool('misc.verboseLevel2').setBool(True) + + print framework.getEnvironment().getPrint() + + success = scriptMain( **kw ) + shellSuccess = 0 + if not success: shellSuccess = 1 + + sys.exit( shellSuccess ) diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad0.ap b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad0.ap new file mode 100644 index 000000000..5e69a1305 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad0.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H rf2_dec_bufad0,P,24/4/2016,100 +A 0,0,9000,10000 +S 1000,2000,1000,8000,300,i,UP,CALU1 +S 5800,5500,5800,9500,200,5nonymous_,UP,PTRANS +S 6400,5700,6400,9300,600,4nonymous_,UP,PDIF +S 7800,5680,7800,9720,600,3nonymous_,UP,NTIE +S 4000,5700,4000,9300,600,2nonymous_,UP,PDIF +S 1000,4000,3400,4000,600,1nonymous_,RIGHT,POLY +S 2800,2000,2800,8000,300,0nonymous_,UP,ALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 4850,6000,5150,6000,600,q,RIGHT,CALU2 +S 2850,5000,3150,5000,600,nq,RIGHT,CALU2 +S 4600,500,4600,2500,200,15onymous_,UP,NTRANS +S 5800,500,5800,2500,200,14onymous_,UP,NTRANS +S 2200,500,2200,2500,200,13onymous_,UP,NTRANS +S 3400,500,3400,2500,200,12onymous_,UP,NTRANS +S 1600,5700,1600,9300,600,11onymous_,UP,PDIF +S 4600,5500,4600,9500,200,10onymous_,UP,PTRANS +S 5200,5700,5200,9300,600,9nonymous_,UP,PDIF +S 3400,5500,3400,9500,200,8nonymous_,UP,PTRANS +S 2200,5500,2200,9500,200,7nonymous_,UP,PTRANS +S 2800,5700,2800,9300,600,6nonymous_,UP,PDIF +S 6400,700,6400,2300,600,16onymous_,UP,NDIF +S 2800,700,2800,2300,600,17onymous_,UP,NDIF +S 1600,700,1600,2300,600,18onymous_,UP,NDIF +S -600,7800,9600,7800,6000,35onymous_,RIGHT,NWELL +S 6400,6000,6400,9000,300,34onymous_,UP,ALU1 +S 6400,1000,6400,2000,300,33onymous_,UP,ALU1 +S 3000,3000,4200,3000,300,32onymous_,RIGHT,ALU1 +S 4000,6000,4000,9000,300,31onymous_,UP,ALU1 +S 4000,1000,4000,2000,300,30onymous_,UP,ALU1 +S 7800,6000,7800,9400,300,29onymous_,UP,ALU1 +S 7800,600,7800,3000,300,28onymous_,UP,ALU1 +S 5200,2000,5200,8000,300,27onymous_,UP,ALU1 +S 2200,2800,2200,5200,200,26onymous_,UP,POLY +S 3400,2800,3400,5200,200,25onymous_,UP,POLY +S 4600,2800,4600,5200,200,24onymous_,UP,POLY +S 5800,2800,5800,5200,200,23onymous_,UP,POLY +S 4200,3000,5800,3000,600,22onymous_,RIGHT,POLY +S 7800,280,7800,3320,600,21onymous_,UP,PTIE +S 4000,700,4000,2300,600,20onymous_,UP,NDIF +S 5200,700,5200,2300,600,19onymous_,UP,NDIF +V 1000,4000,CONT_POLY,36onymous_ +V 7800,6000,CONT_BODY_N,37onymous_ +V 1600,9000,CONT_DIF_P,38onymous_ +V 4000,9000,CONT_DIF_P,39onymous_ +V 7800,9300,CONT_BODY_N,40onymous_ +V 7800,8000,CONT_BODY_N,41onymous_ +V 7800,7000,CONT_BODY_N,42onymous_ +V 6400,6000,CONT_DIF_P,43onymous_ +V 6400,8000,CONT_DIF_P,44onymous_ +V 5200,8000,CONT_DIF_P,45onymous_ +V 5200,7000,CONT_DIF_P,46onymous_ +V 5200,6000,CONT_DIF_P,47onymous_ +V 2800,7000,CONT_DIF_P,48onymous_ +V 2800,6000,CONT_DIF_P,49onymous_ +V 2800,8000,CONT_DIF_P,50onymous_ +V 4000,8000,CONT_DIF_P,51onymous_ +V 3000,5000,CONT_VIA,68onymous_ +V 5000,6000,CONT_VIA,67onymous_ +V 4200,3000,CONT_POLY,66onymous_ +V 7800,3000,CONT_BODY_P,65onymous_ +V 7800,600,CONT_BODY_P,64onymous_ +V 7800,2000,CONT_BODY_P,63onymous_ +V 6400,2000,CONT_DIF_N,62onymous_ +V 6400,1000,CONT_DIF_N,61onymous_ +V 4000,2000,CONT_DIF_N,60onymous_ +V 4000,1000,CONT_DIF_N,59onymous_ +V 1600,1000,CONT_DIF_N,58onymous_ +V 5200,2000,CONT_DIF_N,57onymous_ +V 2800,2000,CONT_DIF_N,56onymous_ +V 6400,7000,CONT_DIF_P,55onymous_ +V 6400,9000,CONT_DIF_P,54onymous_ +V 4000,6000,CONT_DIF_P,53onymous_ +V 4000,7000,CONT_DIF_P,52onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad0.vbe b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad0.vbe new file mode 100644 index 000000000..fba7b98e0 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad0.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_bufad0 IS +PORT ( + i : in BIT; + nq : inout BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_bufad0; + +ARCHITECTURE VBE OF rf2_dec_bufad0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_bufad0" + SEVERITY WARNING; + + nq <= not i; + q <= not nq; + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_l.ap b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_l.ap new file mode 100644 index 000000000..dd8a5fd70 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_l.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H rf2_dec_bufad1_l,P,24/4/2016,100 +A 0,0,10000,10000 +S 4000,3850,4000,4150,400,i,UP,CALU3 +S 5600,5500,5600,9500,200,15onymous_,UP,PTRANS +S 7400,5700,7400,9300,600,14onymous_,UP,PDIF +S 6800,5500,6800,9500,200,13onymous_,UP,PTRANS +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 4000,4000,5600,4000,600,0nonymous_,RIGHT,POLY +S 6000,4000,7400,4000,300,1nonymous_,RIGHT,ALU1 +S 5000,3000,6400,3000,300,2nonymous_,RIGHT,ALU1 +S 5000,2000,5000,8000,300,3nonymous_,UP,ALU1 +S 4050,4000,5950,4000,300,4nonymous_,RIGHT,TALU2 +S 2000,5680,2000,9720,600,5nonymous_,UP,NTIE +S 4400,5500,4400,9500,200,16onymous_,UP,PTRANS +S 5000,5700,5000,9300,600,17onymous_,UP,PDIF +S 6800,500,6800,2500,200,18onymous_,UP,NTRANS +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 6000,3850,6000,4150,400,q,UP,CALU3 +S 5000,3850,5000,4150,400,nq,UP,CALU3 +S 2000,280,2000,3320,600,6nonymous_,UP,PTIE +S 2000,600,2000,3000,300,7nonymous_,UP,ALU1 +S 2000,6000,2000,9400,300,8nonymous_,UP,ALU1 +S 8000,5500,8000,9500,200,9nonymous_,UP,PTRANS +S 8600,5700,8600,9300,600,10onymous_,UP,PDIF +S 6200,5700,6200,9300,600,11onymous_,UP,PDIF +S 3800,5700,3800,9300,600,12onymous_,UP,PDIF +S 3800,700,3800,2300,600,24onymous_,UP,NDIF +S 5000,700,5000,2300,600,25onymous_,UP,NDIF +S 8600,700,8600,2300,600,26onymous_,UP,NDIF +S 4400,2800,4400,5200,200,27onymous_,UP,POLY +S 5600,2800,5600,5200,200,28onymous_,UP,POLY +S 6800,2800,6800,5200,200,29onymous_,UP,POLY +S 8000,2800,8000,5200,200,30onymous_,UP,POLY +S 6400,3000,8000,3000,600,31onymous_,RIGHT,POLY +S 6200,6000,6200,9000,300,32onymous_,UP,ALU1 +S 6200,1000,6200,2000,300,33onymous_,UP,ALU1 +S 3800,1000,3800,2000,300,34onymous_,UP,ALU1 +S 3800,6000,3800,9000,300,35onymous_,UP,ALU1 +S 7400,700,7400,2300,600,23onymous_,UP,NDIF +S 6200,700,6200,2300,600,22onymous_,UP,NDIF +S 5600,500,5600,2500,200,21onymous_,UP,NTRANS +S 4400,500,4400,2500,200,20onymous_,UP,NTRANS +S 8000,500,8000,2500,200,19onymous_,UP,NTRANS +S 7400,2000,7400,8000,300,36onymous_,UP,ALU1 +S 8600,6000,8600,9000,300,37onymous_,UP,ALU1 +S 8600,1000,8600,2000,300,38onymous_,UP,ALU1 +S -600,7800,10600,7800,6000,39onymous_,RIGHT,NWELL +V 8600,1000,CONT_DIF_N,75onymous_ +V 8600,2000,CONT_DIF_N,74onymous_ +V 5000,2000,CONT_DIF_N,73onymous_ +V 7400,2000,CONT_DIF_N,72onymous_ +V 6200,9000,CONT_DIF_P,71onymous_ +V 6200,2000,CONT_DIF_N,76onymous_ +V 6200,1000,CONT_DIF_N,77onymous_ +V 3800,1000,CONT_DIF_N,78onymous_ +V 3800,2000,CONT_DIF_N,79onymous_ +V 6400,3000,CONT_POLY,80onymous_ +V 4000,4000,CONT_POLY,40onymous_ +V 6000,4000,CONT_VIA,41onymous_ +V 5000,4000,CONT_VIA,42onymous_ +V 4000,4000,CONT_VIA,43onymous_ +V 6000,4000,CONT_VIA2,44onymous_ +V 5000,4000,CONT_VIA2,45onymous_ +V 4000,4000,CONT_VIA2,46onymous_ +V 2000,9300,CONT_BODY_N,47onymous_ +V 2000,8000,CONT_BODY_N,48onymous_ +V 2000,7000,CONT_BODY_N,49onymous_ +V 2000,6000,CONT_BODY_N,50onymous_ +V 2000,2000,CONT_BODY_P,51onymous_ +V 2000,600,CONT_BODY_P,52onymous_ +V 2000,3000,CONT_BODY_P,53onymous_ +V 6200,8000,CONT_DIF_P,54onymous_ +V 7400,7000,CONT_DIF_P,55onymous_ +V 7400,8000,CONT_DIF_P,56onymous_ +V 8600,8000,CONT_DIF_P,57onymous_ +V 8600,6000,CONT_DIF_P,58onymous_ +V 8600,7000,CONT_DIF_P,59onymous_ +V 8600,9000,CONT_DIF_P,60onymous_ +V 6200,6000,CONT_DIF_P,61onymous_ +V 6200,7000,CONT_DIF_P,62onymous_ +V 3800,8000,CONT_DIF_P,63onymous_ +V 3800,7000,CONT_DIF_P,64onymous_ +V 3800,6000,CONT_DIF_P,65onymous_ +V 3800,9000,CONT_DIF_P,66onymous_ +V 5000,8000,CONT_DIF_P,67onymous_ +V 5000,6000,CONT_DIF_P,68onymous_ +V 5000,7000,CONT_DIF_P,69onymous_ +V 7400,6000,CONT_DIF_P,70onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_l.vbe b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_l.vbe new file mode 100644 index 000000000..0e135104c --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_l.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_bufad1_l IS +PORT ( + i : in BIT; + nq : out BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_bufad1_l; + +ARCHITECTURE VBE OF rf2_dec_bufad1_l IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_bufad1_l" + SEVERITY WARNING; + + nq <= not i; + q <= not nq; + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_r.ap b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_r.ap new file mode 100644 index 000000000..fcfdbae42 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_r.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H rf2_dec_bufad1_r,P,24/4/2016,100 +A 0,0,20000,10000 +S 4000,3850,4000,4150,400,i,UP,CALU3 +S 8600,5700,8600,9300,600,15onymous_,UP,PDIF +S 8000,5500,8000,9500,200,14onymous_,UP,PTRANS +S 2000,6000,2000,9400,300,13onymous_,UP,ALU1 +S 0,600,20000,600,1200,vss,RIGHT,CALU1 +S 11200,5680,11200,9720,600,0nonymous_,UP,NTIE +S 11200,280,11200,3320,600,1nonymous_,UP,PTIE +S 11200,600,11200,3000,300,2nonymous_,UP,ALU1 +S 11200,6000,11200,9400,300,3nonymous_,UP,ALU1 +S -600,7800,20600,7800,6000,4nonymous_,RIGHT,NWELL +S 4000,4000,5600,4000,600,5nonymous_,RIGHT,POLY +S 6200,5700,6200,9300,600,16onymous_,UP,PDIF +S 3800,5700,3800,9300,600,17onymous_,UP,PDIF +S 6800,5500,6800,9500,200,18onymous_,UP,PTRANS +S 0,9400,20000,9400,1200,vdd,RIGHT,CALU1 +S 6000,3850,6000,4150,400,q,UP,CALU3 +S 5000,3850,5000,4150,400,nq,UP,CALU3 +S 6000,4000,7400,4000,300,6nonymous_,RIGHT,ALU1 +S 5000,3000,6400,3000,300,7nonymous_,RIGHT,ALU1 +S 5000,2000,5000,8000,300,8nonymous_,UP,ALU1 +S 4050,4000,5950,4000,300,9nonymous_,RIGHT,TALU2 +S 2000,5680,2000,9720,600,10onymous_,UP,NTIE +S 2000,280,2000,3320,600,11onymous_,UP,PTIE +S 2000,600,2000,3000,300,12onymous_,UP,ALU1 +S 5600,500,5600,2500,200,26onymous_,UP,NTRANS +S 6200,700,6200,2300,600,27onymous_,UP,NDIF +S 7400,700,7400,2300,600,28onymous_,UP,NDIF +S 3800,700,3800,2300,600,29onymous_,UP,NDIF +S 5000,700,5000,2300,600,30onymous_,UP,NDIF +S 8600,700,8600,2300,600,31onymous_,UP,NDIF +S 4400,2800,4400,5200,200,32onymous_,UP,POLY +S 5600,2800,5600,5200,200,33onymous_,UP,POLY +S 6800,2800,6800,5200,200,34onymous_,UP,POLY +S 8000,2800,8000,5200,200,35onymous_,UP,POLY +S 4400,500,4400,2500,200,25onymous_,UP,NTRANS +S 8000,500,8000,2500,200,24onymous_,UP,NTRANS +S 6800,500,6800,2500,200,23onymous_,UP,NTRANS +S 5000,5700,5000,9300,600,22onymous_,UP,PDIF +S 4400,5500,4400,9500,200,21onymous_,UP,PTRANS +S 5600,5500,5600,9500,200,20onymous_,UP,PTRANS +S 7400,5700,7400,9300,600,19onymous_,UP,PDIF +S 6400,3000,8000,3000,600,36onymous_,RIGHT,POLY +S 6200,6000,6200,9000,300,37onymous_,UP,ALU1 +S 6200,1000,6200,2000,300,38onymous_,UP,ALU1 +S 3800,1000,3800,2000,300,39onymous_,UP,ALU1 +S 3800,6000,3800,9000,300,40onymous_,UP,ALU1 +S 7400,2000,7400,8000,300,41onymous_,UP,ALU1 +S 8600,6000,8600,9000,300,42onymous_,UP,ALU1 +S 8600,1000,8600,2000,300,43onymous_,UP,ALU1 +V 3800,7000,CONT_DIF_P,75onymous_ +V 3800,8000,CONT_DIF_P,74onymous_ +V 6200,7000,CONT_DIF_P,73onymous_ +V 6200,6000,CONT_DIF_P,72onymous_ +V 8600,9000,CONT_DIF_P,71onymous_ +V 8600,7000,CONT_DIF_P,70onymous_ +V 8600,6000,CONT_DIF_P,69onymous_ +V 3800,6000,CONT_DIF_P,76onymous_ +V 3800,9000,CONT_DIF_P,77onymous_ +V 5000,8000,CONT_DIF_P,78onymous_ +V 5000,6000,CONT_DIF_P,79onymous_ +V 5000,7000,CONT_DIF_P,80onymous_ +V 7400,6000,CONT_DIF_P,81onymous_ +V 6200,9000,CONT_DIF_P,82onymous_ +V 11200,9300,CONT_BODY_N,44onymous_ +V 11200,8000,CONT_BODY_N,45onymous_ +V 11200,7000,CONT_BODY_N,46onymous_ +V 11200,6000,CONT_BODY_N,47onymous_ +V 11200,2000,CONT_BODY_P,48onymous_ +V 11200,600,CONT_BODY_P,49onymous_ +V 11200,3000,CONT_BODY_P,50onymous_ +V 4000,4000,CONT_POLY,51onymous_ +V 6000,4000,CONT_VIA,52onymous_ +V 5000,4000,CONT_VIA,53onymous_ +V 4000,4000,CONT_VIA,54onymous_ +V 6000,4000,CONT_VIA2,55onymous_ +V 5000,4000,CONT_VIA2,56onymous_ +V 4000,4000,CONT_VIA2,57onymous_ +V 2000,9300,CONT_BODY_N,58onymous_ +V 2000,8000,CONT_BODY_N,59onymous_ +V 2000,7000,CONT_BODY_N,60onymous_ +V 2000,6000,CONT_BODY_N,61onymous_ +V 2000,2000,CONT_BODY_P,62onymous_ +V 2000,600,CONT_BODY_P,63onymous_ +V 2000,3000,CONT_BODY_P,64onymous_ +V 6200,8000,CONT_DIF_P,65onymous_ +V 7400,7000,CONT_DIF_P,66onymous_ +V 7400,8000,CONT_DIF_P,67onymous_ +V 8600,8000,CONT_DIF_P,68onymous_ +V 7400,2000,CONT_DIF_N,83onymous_ +V 5000,2000,CONT_DIF_N,84onymous_ +V 8600,2000,CONT_DIF_N,85onymous_ +V 8600,1000,CONT_DIF_N,86onymous_ +V 6200,2000,CONT_DIF_N,87onymous_ +V 6200,1000,CONT_DIF_N,88onymous_ +V 3800,1000,CONT_DIF_N,89onymous_ +V 3800,2000,CONT_DIF_N,90onymous_ +V 6400,3000,CONT_POLY,91onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_r.vbe b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_r.vbe new file mode 100644 index 000000000..0a1b20a09 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad1_r.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_bufad1_r IS +PORT ( + i : in BIT; + nq : out BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_bufad1_r; + +ARCHITECTURE VBE OF rf2_dec_bufad1_r IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_bufad1_r" + SEVERITY WARNING; + + nq <= not i; + q <= not nq; + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_l.ap b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_l.ap new file mode 100644 index 000000000..3dcba0c57 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_l.ap @@ -0,0 +1,135 @@ +V ALLIANCE : 6 +H rf2_dec_bufad2_l,P,24/4/2016,100 +A 0,0,10000,10000 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 4050,4000,8950,4000,300,0nonymous_,RIGHT,TALU2 +S 1800,4000,4000,4000,300,1nonymous_,RIGHT,ALU1 +S 3600,4000,5000,4000,600,2nonymous_,RIGHT,POLY +S 6600,2000,7000,2000,300,13onymous_,RIGHT,ALU1 +S 6600,6000,7000,6000,300,14onymous_,RIGHT,ALU1 +S 6600,7000,7000,7000,300,15onymous_,RIGHT,ALU1 +S 6600,8000,7000,8000,300,16onymous_,RIGHT,ALU1 +S 7000,2000,7000,8000,300,17onymous_,UP,ALU1 +S 6000,4000,8000,4000,600,18onymous_,RIGHT,POLY +S 2800,3000,6000,3000,300,3nonymous_,RIGHT,ALU1 +S 2800,5000,6000,5000,300,4nonymous_,RIGHT,ALU1 +S 1200,3000,2800,3000,600,5nonymous_,RIGHT,POLY +S 1200,5000,2800,5000,600,6nonymous_,RIGHT,POLY +S 1800,2000,1800,8000,300,7nonymous_,UP,ALU1 +S 4200,5000,4200,8000,300,8nonymous_,UP,ALU1 +S 4200,2000,4200,3000,300,9nonymous_,UP,ALU1 +S 6000,3000,6000,5000,300,10onymous_,UP,ALU1 +S 7000,3000,8000,3000,300,11onymous_,RIGHT,ALU1 +S 7000,5000,8000,5000,300,12onymous_,RIGHT,ALU1 +S 7800,5700,7800,9300,600,23onymous_,UP,PDIF +S 9600,5500,9600,9500,200,24onymous_,UP,PTRANS +S 9000,5700,9000,9300,600,25onymous_,UP,PDIF +S 6000,5500,6000,9500,200,26onymous_,UP,PTRANS +S 5400,5700,5400,9300,600,27onymous_,UP,PDIF +S 7200,5500,7200,9500,200,28onymous_,UP,PTRANS +S 9600,500,9600,2500,200,29onymous_,UP,NTRANS +S 8400,500,8400,2500,200,30onymous_,UP,NTRANS +S 7200,500,7200,2500,200,31onymous_,UP,NTRANS +S 6000,500,6000,2500,200,32onymous_,UP,NTRANS +S 8400,5500,8400,9500,200,22onymous_,UP,PTRANS +S 10200,5700,10200,9300,600,21onymous_,UP,PDIF +S 6600,5700,6600,9300,600,20onymous_,UP,PDIF +S 8000,5000,9600,5000,600,19onymous_,RIGHT,POLY +S 6600,700,6600,2300,600,33onymous_,UP,NDIF +S 5400,700,5400,2300,600,34onymous_,UP,NDIF +S 10200,700,10200,2300,600,35onymous_,UP,NDIF +S 9000,700,9000,2300,600,36onymous_,UP,NDIF +S 7800,700,7800,2300,600,37onymous_,UP,NDIF +S 8000,3000,9600,3000,600,38onymous_,RIGHT,POLY +S 7200,2800,7200,5200,200,39onymous_,UP,POLY +S 6000,2800,6000,5200,200,40onymous_,UP,POLY +S 10200,6000,10200,9000,300,41onymous_,UP,ALU1 +S 10200,1000,10200,2000,300,42onymous_,UP,ALU1 +S 9000,2000,9000,8000,300,43onymous_,UP,ALU1 +S 5400,1000,5400,2000,300,44onymous_,UP,ALU1 +S 5400,6000,5400,9000,300,45onymous_,UP,ALU1 +S -600,7800,10600,7800,6000,46onymous_,RIGHT,NWELL +S 4800,2800,4800,5200,200,47onymous_,UP,POLY +S 3600,2800,3600,5200,200,48onymous_,UP,POLY +S 4800,5500,4800,9500,200,49onymous_,UP,PTRANS +S 1800,700,1800,2300,600,50onymous_,UP,NDIF +S 600,700,600,2300,600,51onymous_,UP,NDIF +S 4200,700,4200,2300,600,52onymous_,UP,NDIF +S 3000,700,3000,2300,600,53onymous_,UP,NDIF +S 2400,500,2400,2500,200,54onymous_,UP,NTRANS +S 1200,500,1200,2500,200,55onymous_,UP,NTRANS +S 4800,500,4800,2500,200,56onymous_,UP,NTRANS +S 3600,500,3600,2500,200,57onymous_,UP,NTRANS +S 1800,5700,1800,9300,600,58onymous_,UP,PDIF +S 1200,5500,1200,9500,200,59onymous_,UP,PTRANS +S 2400,5500,2400,9500,200,60onymous_,UP,PTRANS +S 4200,5700,4200,9300,600,61onymous_,UP,PDIF +S 3600,5500,3600,9500,200,62onymous_,UP,PTRANS +S 600,6000,600,9000,300,63onymous_,UP,ALU1 +S 600,1000,600,2000,300,64onymous_,UP,ALU1 +S 600,5700,600,9300,600,65onymous_,UP,PDIF +S 3000,5700,3000,9300,600,66onymous_,UP,PDIF +S 5000,3850,5000,4150,400,i0,UP,CALU3 +S 8000,3850,8000,4150,400,i1,UP,CALU3 +S 6000,3850,6000,4150,400,nq0,UP,CALU3 +S 4000,3850,4000,4150,400,q0,UP,CALU3 +S 7000,3850,7000,4150,400,nq1,UP,CALU3 +S 9000,3850,9000,4150,400,q1,UP,CALU3 +V 5000,4000,CONT_POLY,72onymous_ +V 5000,4000,CONT_VIA2,71onymous_ +V 6000,4000,CONT_VIA2,70onymous_ +V 4000,4000,CONT_VIA2,69onymous_ +V 8000,4000,CONT_POLY,73onymous_ +V 8000,5000,CONT_POLY,74onymous_ +V 6000,4000,CONT_VIA,75onymous_ +V 5000,4000,CONT_VIA,76onymous_ +V 4000,4000,CONT_VIA,77onymous_ +V 8000,4000,CONT_VIA,78onymous_ +V 9000,4000,CONT_VIA,79onymous_ +V 7000,4000,CONT_VIA,80onymous_ +V 8000,4000,CONT_VIA2,81onymous_ +V 9000,4000,CONT_VIA2,82onymous_ +V 2800,3000,CONT_POLY,67onymous_ +V 2800,5000,CONT_POLY,68onymous_ +V 7000,4000,CONT_VIA2,83onymous_ +V 5400,9000,CONT_DIF_P,84onymous_ +V 10200,6000,CONT_DIF_P,85onymous_ +V 10200,7000,CONT_DIF_P,86onymous_ +V 5400,7000,CONT_DIF_P,87onymous_ +V 5400,6000,CONT_DIF_P,88onymous_ +V 6600,8000,CONT_DIF_P,89onymous_ +V 6600,7000,CONT_DIF_P,90onymous_ +V 6600,6000,CONT_DIF_P,91onymous_ +V 5400,8000,CONT_DIF_P,92onymous_ +V 9000,8000,CONT_DIF_P,93onymous_ +V 9000,7000,CONT_DIF_P,94onymous_ +V 9000,6000,CONT_DIF_P,95onymous_ +V 7800,9000,CONT_DIF_P,96onymous_ +V 10200,9000,CONT_DIF_P,97onymous_ +V 10200,8000,CONT_DIF_P,98onymous_ +V 9000,2000,CONT_DIF_N,99onymous_ +V 7800,1000,CONT_DIF_N,100nymous_ +V 10200,2000,CONT_DIF_N,101nymous_ +V 10200,1000,CONT_DIF_N,102nymous_ +V 6600,2000,CONT_DIF_N,103nymous_ +V 5400,1000,CONT_DIF_N,104nymous_ +V 5400,2000,CONT_DIF_N,105nymous_ +V 8000,3000,CONT_POLY,106nymous_ +V 1800,2000,CONT_DIF_N,107nymous_ +V 4200,2000,CONT_DIF_N,108nymous_ +V 4200,8000,CONT_DIF_P,109nymous_ +V 4200,7000,CONT_DIF_P,110nymous_ +V 4200,6000,CONT_DIF_P,111nymous_ +V 1800,7000,CONT_DIF_P,112nymous_ +V 1800,6000,CONT_DIF_P,113nymous_ +V 1800,8000,CONT_DIF_P,114nymous_ +V 600,9000,CONT_DIF_P,115nymous_ +V 600,2000,CONT_DIF_N,116nymous_ +V 600,1000,CONT_DIF_N,117nymous_ +V 600,6000,CONT_DIF_P,118nymous_ +V 600,7000,CONT_DIF_P,119nymous_ +V 600,8000,CONT_DIF_P,120nymous_ +V 3000,9000,CONT_DIF_P,121nymous_ +V 3000,1000,CONT_DIF_N,122nymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_l.vbe b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_l.vbe new file mode 100644 index 000000000..5fd005730 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_l.vbe @@ -0,0 +1,26 @@ +ENTITY rf2_dec_bufad2_l IS +PORT ( + i0 : in BIT; + i1 : in BIT; + nq0 : inout BIT; + q0 : out BIT; + nq1 : inout BIT; + q1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_bufad2_l; + +ARCHITECTURE VBE OF rf2_dec_bufad2_l IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_bufad2_l" + SEVERITY WARNING; + + nq0 <= not i0; + q0 <= not nq0; + nq1 <= not i1; + q1 <= not nq1; + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_r.ap b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_r.ap new file mode 100644 index 000000000..9a62675d2 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_r.ap @@ -0,0 +1,146 @@ +V ALLIANCE : 6 +H rf2_dec_bufad2_r,P,24/4/2016,100 +A 0,0,20000,10000 +S 0,9400,20000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,20000,600,1200,vss,RIGHT,CALU1 +S 12200,680,12200,3320,600,0nonymous_,UP,PTIE +S 12200,5880,12200,9320,600,1nonymous_,UP,NTIE +S 12200,6000,12200,9000,300,2nonymous_,UP,ALU1 +S 4200,5000,4200,8000,300,13onymous_,UP,ALU1 +S 4200,2000,4200,3000,300,14onymous_,UP,ALU1 +S 6000,3000,6000,5000,300,15onymous_,UP,ALU1 +S 7000,3000,8000,3000,300,16onymous_,RIGHT,ALU1 +S 7000,5000,8000,5000,300,17onymous_,RIGHT,ALU1 +S 6600,2000,7000,2000,300,18onymous_,RIGHT,ALU1 +S 12200,1000,12200,3000,300,3nonymous_,UP,ALU1 +S -600,7800,20600,7800,6000,4nonymous_,RIGHT,NWELL +S 4050,4000,8950,4000,300,5nonymous_,RIGHT,TALU2 +S 1800,4000,4000,4000,300,6nonymous_,RIGHT,ALU1 +S 3600,4000,5000,4000,600,7nonymous_,RIGHT,POLY +S 2800,3000,6000,3000,300,8nonymous_,RIGHT,ALU1 +S 2800,5000,6000,5000,300,9nonymous_,RIGHT,ALU1 +S 1200,3000,2800,3000,600,10onymous_,RIGHT,POLY +S 1200,5000,2800,5000,600,11onymous_,RIGHT,POLY +S 1800,2000,1800,8000,300,12onymous_,UP,ALU1 +S 3000,5700,3000,9300,600,70onymous_,UP,PDIF +S 600,5700,600,9300,600,69onymous_,UP,PDIF +S 6000,4000,8000,4000,600,23onymous_,RIGHT,POLY +S 8000,5000,9600,5000,600,24onymous_,RIGHT,POLY +S 6600,5700,6600,9300,600,25onymous_,UP,PDIF +S 10200,5700,10200,9300,600,26onymous_,UP,PDIF +S 8400,5500,8400,9500,200,27onymous_,UP,PTRANS +S 7800,5700,7800,9300,600,28onymous_,UP,PDIF +S 9600,5500,9600,9500,200,29onymous_,UP,PTRANS +S 9000,5700,9000,9300,600,30onymous_,UP,PDIF +S 6000,5500,6000,9500,200,31onymous_,UP,PTRANS +S 5400,5700,5400,9300,600,32onymous_,UP,PDIF +S 7000,2000,7000,8000,300,22onymous_,UP,ALU1 +S 6600,8000,7000,8000,300,21onymous_,RIGHT,ALU1 +S 6600,7000,7000,7000,300,20onymous_,RIGHT,ALU1 +S 6600,6000,7000,6000,300,19onymous_,RIGHT,ALU1 +S 7200,5500,7200,9500,200,33onymous_,UP,PTRANS +S 9600,500,9600,2500,200,34onymous_,UP,NTRANS +S 8400,500,8400,2500,200,35onymous_,UP,NTRANS +S 7200,500,7200,2500,200,36onymous_,UP,NTRANS +S 6000,500,6000,2500,200,37onymous_,UP,NTRANS +S 6600,700,6600,2300,600,38onymous_,UP,NDIF +S 5400,700,5400,2300,600,39onymous_,UP,NDIF +S 10200,700,10200,2300,600,40onymous_,UP,NDIF +S 9000,700,9000,2300,600,41onymous_,UP,NDIF +S 7800,700,7800,2300,600,42onymous_,UP,NDIF +S 8000,3000,9600,3000,600,43onymous_,RIGHT,POLY +S 7200,2800,7200,5200,200,44onymous_,UP,POLY +S 6000,2800,6000,5200,200,45onymous_,UP,POLY +S 10200,6000,10200,9000,300,46onymous_,UP,ALU1 +S 10200,1000,10200,2000,300,47onymous_,UP,ALU1 +S 9000,2000,9000,8000,300,48onymous_,UP,ALU1 +S 5400,1000,5400,2000,300,49onymous_,UP,ALU1 +S 5400,6000,5400,9000,300,50onymous_,UP,ALU1 +S 4800,2800,4800,5200,200,51onymous_,UP,POLY +S 3600,2800,3600,5200,200,52onymous_,UP,POLY +S 4800,5500,4800,9500,200,53onymous_,UP,PTRANS +S 1800,700,1800,2300,600,54onymous_,UP,NDIF +S 600,700,600,2300,600,55onymous_,UP,NDIF +S 4200,700,4200,2300,600,56onymous_,UP,NDIF +S 3000,700,3000,2300,600,57onymous_,UP,NDIF +S 2400,500,2400,2500,200,58onymous_,UP,NTRANS +S 1200,500,1200,2500,200,59onymous_,UP,NTRANS +S 4800,500,4800,2500,200,60onymous_,UP,NTRANS +S 3600,500,3600,2500,200,61onymous_,UP,NTRANS +S 1800,5700,1800,9300,600,62onymous_,UP,PDIF +S 1200,5500,1200,9500,200,63onymous_,UP,PTRANS +S 2400,5500,2400,9500,200,64onymous_,UP,PTRANS +S 4200,5700,4200,9300,600,65onymous_,UP,PDIF +S 3600,5500,3600,9500,200,66onymous_,UP,PTRANS +S 600,6000,600,9000,300,67onymous_,UP,ALU1 +S 600,1000,600,2000,300,68onymous_,UP,ALU1 +S 5000,3850,5000,4150,400,i0,UP,CALU3 +S 8000,3850,8000,4150,400,i1,UP,CALU3 +S 6000,3850,6000,4150,400,nq0,UP,CALU3 +S 4000,3850,4000,4150,400,q0,UP,CALU3 +S 7000,3850,7000,4150,400,nq1,UP,CALU3 +S 9000,3850,9000,4150,400,q1,UP,CALU3 +V 12200,2000,CONT_BODY_P,72onymous_ +V 12200,3000,CONT_BODY_P,71onymous_ +V 12200,1000,CONT_BODY_P,73onymous_ +V 12200,6000,CONT_BODY_N,74onymous_ +V 12200,7000,CONT_BODY_N,75onymous_ +V 12200,8000,CONT_BODY_N,76onymous_ +V 12200,9000,CONT_BODY_N,77onymous_ +V 2800,3000,CONT_POLY,78onymous_ +V 2800,5000,CONT_POLY,79onymous_ +V 4000,4000,CONT_VIA2,80onymous_ +V 6000,4000,CONT_VIA2,81onymous_ +V 5000,4000,CONT_VIA2,82onymous_ +V 5000,4000,CONT_POLY,83onymous_ +V 8000,4000,CONT_POLY,84onymous_ +V 8000,5000,CONT_POLY,85onymous_ +V 6000,4000,CONT_VIA,86onymous_ +V 5000,4000,CONT_VIA,87onymous_ +V 4000,4000,CONT_VIA,88onymous_ +V 8000,4000,CONT_VIA,89onymous_ +V 9000,4000,CONT_VIA,90onymous_ +V 7000,4000,CONT_VIA,91onymous_ +V 8000,4000,CONT_VIA2,92onymous_ +V 9000,4000,CONT_VIA2,93onymous_ +V 7000,4000,CONT_VIA2,94onymous_ +V 5400,9000,CONT_DIF_P,95onymous_ +V 10200,6000,CONT_DIF_P,96onymous_ +V 10200,7000,CONT_DIF_P,97onymous_ +V 5400,7000,CONT_DIF_P,98onymous_ +V 5400,6000,CONT_DIF_P,99onymous_ +V 6600,8000,CONT_DIF_P,100nymous_ +V 6600,7000,CONT_DIF_P,101nymous_ +V 6600,6000,CONT_DIF_P,102nymous_ +V 5400,8000,CONT_DIF_P,103nymous_ +V 9000,8000,CONT_DIF_P,104nymous_ +V 9000,7000,CONT_DIF_P,105nymous_ +V 9000,6000,CONT_DIF_P,106nymous_ +V 7800,9000,CONT_DIF_P,107nymous_ +V 10200,9000,CONT_DIF_P,108nymous_ +V 10200,8000,CONT_DIF_P,109nymous_ +V 9000,2000,CONT_DIF_N,110nymous_ +V 7800,1000,CONT_DIF_N,111nymous_ +V 10200,2000,CONT_DIF_N,112nymous_ +V 10200,1000,CONT_DIF_N,113nymous_ +V 6600,2000,CONT_DIF_N,114nymous_ +V 5400,1000,CONT_DIF_N,115nymous_ +V 5400,2000,CONT_DIF_N,116nymous_ +V 8000,3000,CONT_POLY,117nymous_ +V 1800,2000,CONT_DIF_N,118nymous_ +V 4200,2000,CONT_DIF_N,119nymous_ +V 4200,8000,CONT_DIF_P,120nymous_ +V 4200,7000,CONT_DIF_P,121nymous_ +V 4200,6000,CONT_DIF_P,122nymous_ +V 1800,7000,CONT_DIF_P,123nymous_ +V 1800,6000,CONT_DIF_P,124nymous_ +V 1800,8000,CONT_DIF_P,125nymous_ +V 600,9000,CONT_DIF_P,126nymous_ +V 600,2000,CONT_DIF_N,127nymous_ +V 600,1000,CONT_DIF_N,128nymous_ +V 600,6000,CONT_DIF_P,129nymous_ +V 600,7000,CONT_DIF_P,130nymous_ +V 600,8000,CONT_DIF_P,131nymous_ +V 3000,9000,CONT_DIF_P,132nymous_ +V 3000,1000,CONT_DIF_N,133nymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_r.vbe b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_r.vbe new file mode 100644 index 000000000..4cc3ee19c --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_bufad2_r.vbe @@ -0,0 +1,26 @@ +ENTITY rf2_dec_bufad2_r IS +PORT ( + i0 : in BIT; + i1 : in BIT; + nq0 : inout BIT; + q0 : out BIT; + nq1 : inout BIT; + q1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_bufad2_r; + +ARCHITECTURE VBE OF rf2_dec_bufad2_r IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_bufad2_r" + SEVERITY WARNING; + + nq0 <= not i0; + q0 <= not nq0; + nq1 <= not i1; + q1 <= not nq1; + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nand2.ap b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand2.ap new file mode 100644 index 000000000..ad6726eed --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand2.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H rf2_dec_nand2,P,24/4/2016,100 +A 0,0,14000,10000 +S 11800,600,11800,3000,300,17onymous_,UP,ALU1 +S 2600,6700,2600,9100,600,16onymous_,UP,PDIF +S 1400,5680,1400,9720,600,5nonymous_,UP,NTIE +S 1400,280,1400,3320,600,4nonymous_,UP,PTIE +S 1400,600,1400,3000,300,3nonymous_,UP,ALU1 +S 1400,6000,1400,9400,300,2nonymous_,UP,ALU1 +S -600,7800,14600,7800,6000,1nonymous_,RIGHT,NWELL +S 5000,2000,9000,2000,300,0nonymous_,RIGHT,ALU1 +S 0,600,14000,600,1200,vss,RIGHT,CALU1 +S 0,9400,14000,9400,1200,vdd,RIGHT,CALU1 +S 5000,6700,5000,9100,600,15onymous_,UP,PDIF +S 3200,6500,3200,8500,200,14onymous_,UP,PTRANS +S 4400,6500,4400,8500,200,13onymous_,UP,PTRANS +S 3800,6700,3800,8300,600,12onymous_,UP,PDIF +S 3200,500,3200,2500,200,11onymous_,UP,NTRANS +S 2600,700,2600,2300,600,10onymous_,UP,NDIF +S 3200,2800,3200,6200,200,9nonymous_,UP,POLY +S 2600,1000,2600,2000,300,8nonymous_,UP,ALU1 +S 5000,8000,5000,9000,300,7nonymous_,UP,ALU1 +S 2600,7000,2600,9000,300,6nonymous_,UP,ALU1 +S 9000,3850,9000,4150,400,nq,UP,CALU3 +S 11800,280,11800,3320,600,18onymous_,UP,PTIE +S 3800,700,3800,2300,600,29onymous_,UP,NDIF +S 5000,700,5000,2300,600,28onymous_,UP,NDIF +S 4000,4000,4400,4000,600,27onymous_,RIGHT,POLY +S 4400,2800,4400,6200,200,26onymous_,UP,POLY +S 4400,500,4400,2500,200,25onymous_,UP,NTRANS +S 3850,4000,5150,4000,600,24onymous_,RIGHT,ALU2 +S 3050,4000,8950,4000,300,23onymous_,RIGHT,TALU2 +S 3800,7000,9000,7000,300,22onymous_,RIGHT,ALU1 +S 9000,2000,9000,7000,300,21onymous_,UP,ALU1 +S 11800,5680,11800,9720,600,20onymous_,UP,NTIE +S 11800,6000,11800,9400,300,19onymous_,UP,ALU1 +S 5000,3850,5000,4150,400,i1,UP,CALU3 +S 3000,3850,3000,4150,400,i0,UP,CALU3 +V 1400,8000,CONT_BODY_N,35onymous_ +V 1400,6000,CONT_BODY_N,34onymous_ +V 1400,3000,CONT_BODY_P,33onymous_ +V 1400,2000,CONT_BODY_P,32onymous_ +V 1400,600,CONT_BODY_P,31onymous_ +V 5000,2000,CONT_DIF_N,30onymous_ +V 1400,9300,CONT_BODY_N,36onymous_ +V 1400,7000,CONT_BODY_N,37onymous_ +V 2600,1000,CONT_DIF_N,38onymous_ +V 2600,2000,CONT_DIF_N,39onymous_ +V 2600,9000,CONT_DIF_P,40onymous_ +V 6200,9300,CONT_BODY_N,41onymous_ +V 3800,9300,CONT_BODY_N,42onymous_ +V 2600,8000,CONT_DIF_P,43onymous_ +V 4000,4000,CONT_VIA,62onymous_ +V 4000,4000,CONT_POLY,61onymous_ +V 5000,4000,CONT_VIA2,60onymous_ +V 9000,4000,CONT_VIA,59onymous_ +V 11800,8000,CONT_BODY_N,58onymous_ +V 11800,6000,CONT_BODY_N,57onymous_ +V 11800,7000,CONT_BODY_N,56onymous_ +V 11800,9300,CONT_BODY_N,55onymous_ +V 11800,600,CONT_BODY_P,54onymous_ +V 11800,2000,CONT_BODY_P,53onymous_ +V 11800,3000,CONT_BODY_P,52onymous_ +V 9000,4000,CONT_VIA2,51onymous_ +V 3000,4000,CONT_POLY,50onymous_ +V 3000,4000,CONT_VIA,49onymous_ +V 3000,4000,CONT_VIA2,48onymous_ +V 5000,9000,CONT_DIF_P,47onymous_ +V 5000,8000,CONT_DIF_P,46onymous_ +V 3800,7000,CONT_DIF_P,45onymous_ +V 2600,7000,CONT_DIF_P,44onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nand2.vbe b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand2.vbe new file mode 100644 index 000000000..eca7411b6 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand2.vbe @@ -0,0 +1,20 @@ +ENTITY rf2_dec_nand2 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nand2; + +ARCHITECTURE VBE OF rf2_dec_nand2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nand2" + SEVERITY WARNING; + + nq <= not(i0 and i1); + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nand3.ap b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand3.ap new file mode 100644 index 000000000..800a25663 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand3.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H rf2_dec_nand3,P,24/4/2016,100 +A 0,0,14000,10000 +S 2600,6700,2600,9100,600,17onymous_,UP,PDIF +S 5000,6700,5000,9100,600,16onymous_,UP,PDIF +S 3200,6500,3200,8500,200,15onymous_,UP,PTRANS +S 1400,280,1400,3320,600,4nonymous_,UP,PTIE +S 1400,600,1400,3000,300,3nonymous_,UP,ALU1 +S 1400,6000,1400,9400,300,2nonymous_,UP,ALU1 +S -600,7800,14600,7800,6000,1nonymous_,RIGHT,NWELL +S 6200,2000,9000,2000,300,0nonymous_,RIGHT,ALU1 +S 0,600,14000,600,1200,vss,RIGHT,CALU1 +S 0,9400,14000,9400,1200,vdd,RIGHT,CALU1 +S 5600,6500,5600,8500,200,14onymous_,UP,PTRANS +S 4400,6500,4400,8500,200,13onymous_,UP,PTRANS +S 3800,6700,3800,8300,600,12onymous_,UP,PDIF +S 3200,500,3200,2500,200,11onymous_,UP,NTRANS +S 2600,700,2600,2300,600,10onymous_,UP,NDIF +S 3200,2800,3200,6200,200,9nonymous_,UP,POLY +S 2600,1000,2600,2000,300,8nonymous_,UP,ALU1 +S 5000,8000,5000,9000,300,7nonymous_,UP,ALU1 +S 2600,7000,2600,9000,300,6nonymous_,UP,ALU1 +S 1400,5680,1400,9720,600,5nonymous_,UP,NTIE +S 9000,3850,9000,4150,400,nq,UP,CALU3 +S 6200,6700,6200,8300,600,18onymous_,UP,PDIF +S 5000,700,5000,2300,600,34onymous_,UP,NDIF +S 6200,700,6200,2300,600,33onymous_,UP,NDIF +S 5600,4000,6000,4000,600,32onymous_,RIGHT,POLY +S 4000,4000,4400,4000,600,31onymous_,RIGHT,POLY +S 4400,2800,4400,6200,200,30onymous_,UP,POLY +S 5600,2800,5600,6200,200,29onymous_,UP,POLY +S 4400,500,4400,2500,200,28onymous_,UP,NTRANS +S 5600,500,5600,2500,200,27onymous_,UP,NTRANS +S 3850,4000,5150,4000,600,26onymous_,RIGHT,ALU2 +S 3050,4000,8950,4000,300,25onymous_,RIGHT,TALU2 +S 3800,7000,9000,7000,300,24onymous_,RIGHT,ALU1 +S 9000,2000,9000,7000,300,23onymous_,UP,ALU1 +S 11800,5680,11800,9720,600,22onymous_,UP,NTIE +S 11800,6000,11800,9400,300,21onymous_,UP,ALU1 +S 11800,280,11800,3320,600,20onymous_,UP,PTIE +S 11800,600,11800,3000,300,19onymous_,UP,ALU1 +S 3800,700,3800,2300,600,35onymous_,UP,NDIF +S 6000,3850,6000,4150,400,i2,UP,CALU3 +S 5000,3850,5000,4150,400,i1,UP,CALU3 +S 3000,3850,3000,4150,400,i0,UP,CALU3 +V 6200,2000,CONT_DIF_N,36onymous_ +V 1400,600,CONT_BODY_P,37onymous_ +V 1400,2000,CONT_BODY_P,38onymous_ +V 1400,3000,CONT_BODY_P,39onymous_ +V 1400,6000,CONT_BODY_N,40onymous_ +V 1400,8000,CONT_BODY_N,41onymous_ +V 1400,9300,CONT_BODY_N,42onymous_ +V 1400,7000,CONT_BODY_N,43onymous_ +V 2600,1000,CONT_DIF_N,44onymous_ +V 2600,2000,CONT_DIF_N,45onymous_ +V 2600,9000,CONT_DIF_P,46onymous_ +V 6200,9300,CONT_BODY_N,47onymous_ +V 3800,9300,CONT_BODY_N,48onymous_ +V 2600,8000,CONT_DIF_P,49onymous_ +V 2600,7000,CONT_DIF_P,50onymous_ +V 3800,7000,CONT_DIF_P,51onymous_ +V 6200,7000,CONT_DIF_P,52onymous_ +V 5000,8000,CONT_DIF_P,53onymous_ +V 4000,4000,CONT_VIA,72onymous_ +V 4000,4000,CONT_POLY,71onymous_ +V 5000,4000,CONT_VIA2,70onymous_ +V 6000,4000,CONT_POLY,69onymous_ +V 6000,4000,CONT_VIA,68onymous_ +V 6000,4000,CONT_VIA2,67onymous_ +V 9000,4000,CONT_VIA,66onymous_ +V 11800,8000,CONT_BODY_N,65onymous_ +V 11800,6000,CONT_BODY_N,64onymous_ +V 11800,7000,CONT_BODY_N,63onymous_ +V 11800,9300,CONT_BODY_N,62onymous_ +V 11800,600,CONT_BODY_P,61onymous_ +V 11800,2000,CONT_BODY_P,60onymous_ +V 11800,3000,CONT_BODY_P,59onymous_ +V 9000,4000,CONT_VIA2,58onymous_ +V 3000,4000,CONT_POLY,57onymous_ +V 3000,4000,CONT_VIA,56onymous_ +V 3000,4000,CONT_VIA2,55onymous_ +V 5000,9000,CONT_DIF_P,54onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nand3.vbe b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand3.vbe new file mode 100644 index 000000000..0860b276d --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand3.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_nand3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nand3; + +ARCHITECTURE VBE OF rf2_dec_nand3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nand3" + SEVERITY WARNING; + + nq <= not(i0 and i1 and i2); + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nand4.ap b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand4.ap new file mode 100644 index 000000000..a62155c15 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand4.ap @@ -0,0 +1,95 @@ +V ALLIANCE : 6 +H rf2_dec_nand4,P,24/4/2016,100 +A 0,0,14000,10000 +S 6800,2800,6800,6200,200,13onymous_,UP,POLY +S 0,9400,14000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,14000,600,1200,vss,RIGHT,CALU1 +S 3800,700,3800,2300,600,0nonymous_,UP,NDIF +S 5000,700,5000,2300,600,1nonymous_,UP,NDIF +S 6200,700,6200,2300,600,2nonymous_,UP,NDIF +S 5600,4000,6000,4000,600,3nonymous_,RIGHT,POLY +S 3050,4000,8950,4000,300,14onymous_,RIGHT,TALU2 +S 3800,7000,9000,7000,300,15onymous_,RIGHT,ALU1 +S 9000,2000,9000,7000,300,16onymous_,UP,ALU1 +S 11800,5680,11800,9720,600,17onymous_,UP,NTIE +S 11800,6000,11800,9400,300,18onymous_,UP,ALU1 +S 9000,3850,9000,4150,400,nq,UP,CALU3 +S 4000,4000,4400,4000,600,4nonymous_,RIGHT,POLY +S 4400,2800,4400,6200,200,5nonymous_,UP,POLY +S 5600,2800,5600,6200,200,6nonymous_,UP,POLY +S 4400,500,4400,2500,200,7nonymous_,UP,NTRANS +S 5600,500,5600,2500,200,8nonymous_,UP,NTRANS +S 6800,500,6800,2500,200,9nonymous_,UP,NTRANS +S 7400,700,7400,2300,600,10onymous_,UP,NDIF +S 7400,2000,9000,2000,300,11onymous_,RIGHT,ALU1 +S 3850,4000,5150,4000,600,12onymous_,RIGHT,ALU2 +S 7400,6700,7400,9100,600,24onymous_,UP,PDIF +S 3200,6500,3200,8500,200,25onymous_,UP,PTRANS +S 6800,6500,6800,8500,200,26onymous_,UP,PTRANS +S 5600,6500,5600,8500,200,27onymous_,UP,PTRANS +S 4400,6500,4400,8500,200,28onymous_,UP,PTRANS +S 3800,6700,3800,8300,600,29onymous_,UP,PDIF +S 3200,500,3200,2500,200,30onymous_,UP,NTRANS +S 2600,700,2600,2300,600,31onymous_,UP,NDIF +S 3200,2800,3200,6200,200,32onymous_,UP,POLY +S 2600,1000,2600,2000,300,33onymous_,UP,ALU1 +S 5000,6700,5000,9100,600,23onymous_,UP,PDIF +S 2600,6700,2600,9100,600,22onymous_,UP,PDIF +S 6200,6700,6200,8300,600,21onymous_,UP,PDIF +S 11800,600,11800,3000,300,20onymous_,UP,ALU1 +S 11800,280,11800,3320,600,19onymous_,UP,PTIE +S 7400,8000,7400,9000,300,34onymous_,UP,ALU1 +S 5000,8000,5000,9000,300,35onymous_,UP,ALU1 +S 2600,7000,2600,9000,300,36onymous_,UP,ALU1 +S 1400,5680,1400,9720,600,37onymous_,UP,NTIE +S 1400,280,1400,3320,600,38onymous_,UP,PTIE +S 1400,600,1400,3000,300,39onymous_,UP,ALU1 +S 1400,6000,1400,9400,300,40onymous_,UP,ALU1 +S -600,7800,14600,7800,6000,41onymous_,RIGHT,NWELL +S 3000,3850,3000,4150,400,i0,UP,CALU3 +S 5000,3850,5000,4150,400,i1,UP,CALU3 +S 6000,3850,6000,4150,400,i2,UP,CALU3 +S 7000,3850,7000,4150,400,i3,UP,CALU3 +V 2600,9000,CONT_DIF_P,73onymous_ +V 6200,9300,CONT_BODY_N,72onymous_ +V 3800,9300,CONT_BODY_N,71onymous_ +V 2600,8000,CONT_DIF_P,70onymous_ +V 2600,7000,CONT_DIF_P,69onymous_ +V 7400,9000,CONT_DIF_P,74onymous_ +V 2600,2000,CONT_DIF_N,75onymous_ +V 2600,1000,CONT_DIF_N,76onymous_ +V 1400,7000,CONT_BODY_N,77onymous_ +V 1400,9300,CONT_BODY_N,78onymous_ +V 1400,8000,CONT_BODY_N,79onymous_ +V 1400,6000,CONT_BODY_N,80onymous_ +V 1400,3000,CONT_BODY_P,81onymous_ +V 1400,2000,CONT_BODY_P,82onymous_ +V 7400,2000,CONT_DIF_N,42onymous_ +V 4000,4000,CONT_VIA,43onymous_ +V 4000,4000,CONT_POLY,44onymous_ +V 5000,4000,CONT_VIA2,45onymous_ +V 6000,4000,CONT_POLY,46onymous_ +V 6000,4000,CONT_VIA,47onymous_ +V 6000,4000,CONT_VIA2,48onymous_ +V 7000,4000,CONT_POLY,49onymous_ +V 7000,4000,CONT_VIA,50onymous_ +V 9000,4000,CONT_VIA,51onymous_ +V 11800,8000,CONT_BODY_N,52onymous_ +V 11800,6000,CONT_BODY_N,53onymous_ +V 11800,7000,CONT_BODY_N,54onymous_ +V 11800,9300,CONT_BODY_N,55onymous_ +V 11800,600,CONT_BODY_P,56onymous_ +V 11800,2000,CONT_BODY_P,57onymous_ +V 11800,3000,CONT_BODY_P,58onymous_ +V 9000,4000,CONT_VIA2,59onymous_ +V 3000,4000,CONT_POLY,60onymous_ +V 3000,4000,CONT_VIA,61onymous_ +V 7000,4000,CONT_VIA2,62onymous_ +V 3000,4000,CONT_VIA2,63onymous_ +V 5000,9000,CONT_DIF_P,64onymous_ +V 5000,8000,CONT_DIF_P,65onymous_ +V 7400,8000,CONT_DIF_P,66onymous_ +V 6200,7000,CONT_DIF_P,67onymous_ +V 3800,7000,CONT_DIF_P,68onymous_ +V 1400,600,CONT_BODY_P,83onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nand4.vbe b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand4.vbe new file mode 100644 index 000000000..9f0204b83 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nand4.vbe @@ -0,0 +1,22 @@ +ENTITY rf2_dec_nand4 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nand4; + +ARCHITECTURE VBE OF rf2_dec_nand4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nand4" + SEVERITY WARNING; + + nq <= not(i0 and i1 and i2 and i3); + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nao3.ap b/pdks/symbolic/nrf2lib/cells/rf2_dec_nao3.ap new file mode 100644 index 000000000..52896235e --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nao3.ap @@ -0,0 +1,68 @@ +V ALLIANCE : 6 +H rf2_dec_nao3,P,24/4/2016,100 +A 0,0,7000,10000 +S 600,1700,600,3300,600,17onymous_,UP,NDIF +S 1800,1700,1800,3300,600,16onymous_,UP,NDIF +S 3600,4000,4200,4000,600,15onymous_,RIGHT,POLY +S 600,6000,600,9000,300,4nonymous_,UP,ALU1 +S 4400,900,4400,3300,600,3nonymous_,UP,NDIF +S -600,7800,7600,7800,6000,2nonymous_,RIGHT,NWELL +S 5800,6000,5800,9000,300,1nonymous_,UP,ALU1 +S 5800,5680,5800,9320,600,0nonymous_,UP,NTIE +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 3600,1500,3600,3500,200,14onymous_,UP,NTRANS +S 4200,900,4200,3300,600,13onymous_,UP,NDIF +S 3000,5700,3000,9300,400,12onymous_,UP,PDIF +S 3600,3800,3600,5200,200,11onymous_,UP,POLY +S 2400,3800,2400,5200,200,10onymous_,UP,POLY +S 1200,3800,1200,5200,200,9nonymous_,UP,POLY +S 1400,5000,2000,5000,300,8nonymous_,RIGHT,ALU1 +S 1200,5500,1200,9500,200,7nonymous_,UP,PTRANS +S 600,5700,600,9300,600,6nonymous_,UP,PDIF +S 1800,5700,1800,9300,400,5nonymous_,UP,PDIF +S 1850,3000,2150,3000,600,nq,RIGHT,CALU2 +S 3000,1700,3000,3300,600,18onymous_,UP,NDIF +S 4000,4000,4000,7000,300,31onymous_,UP,ALU1 +S 4200,8000,4200,9000,300,30onymous_,UP,ALU1 +S 2000,4000,2400,4000,600,29onymous_,RIGHT,POLY +S 2400,5500,2400,9500,200,28onymous_,UP,PTRANS +S 2000,5000,2000,8000,300,27onymous_,UP,ALU1 +S 850,4000,2150,4000,600,26onymous_,RIGHT,ALU2 +S 3600,5500,3600,9500,200,25onymous_,UP,PTRANS +S 4200,5700,4200,9300,600,24onymous_,UP,PDIF +S 600,2000,3000,2000,300,23onymous_,RIGHT,ALU1 +S 3000,3000,3000,8000,300,22onymous_,UP,ALU1 +S 1800,3000,3000,3000,300,21onymous_,RIGHT,ALU1 +S 1200,1500,1200,3500,200,20onymous_,UP,NTRANS +S 2400,1500,2400,3500,200,19onymous_,UP,NTRANS +S 3850,7000,4150,7000,600,i2,RIGHT,CALU2 +S 850,4000,1150,4000,600,i1,RIGHT,CALU2 +S 1850,8000,2150,8000,600,i0,RIGHT,CALU2 +V 5800,8000,CONT_BODY_N,34onymous_ +V 5800,7000,CONT_BODY_N,33onymous_ +V 5800,6000,CONT_BODY_N,32onymous_ +V 5800,9000,CONT_BODY_N,35onymous_ +V 600,9000,CONT_DIF_P,36onymous_ +V 1400,5000,CONT_POLY,37onymous_ +V 3000,6000,CONT_DIF_P,38onymous_ +V 4000,7000,CONT_VIA,57onymous_ +V 600,6000,CONT_DIF_P,56onymous_ +V 600,7000,CONT_DIF_P,55onymous_ +V 600,8000,CONT_DIF_P,54onymous_ +V 4200,8000,CONT_DIF_P,53onymous_ +V 2000,8000,CONT_VIA,52onymous_ +V 4200,9000,CONT_DIF_P,51onymous_ +V 3000,2000,CONT_DIF_N,50onymous_ +V 600,2000,CONT_DIF_N,49onymous_ +V 600,600,CONT_BODY_P,48onymous_ +V 3000,600,CONT_BODY_P,47onymous_ +V 4200,1000,CONT_DIF_N,46onymous_ +V 2000,4000,CONT_VIA,45onymous_ +V 2000,4000,CONT_POLY,44onymous_ +V 1800,3000,CONT_DIF_N,43onymous_ +V 4000,4000,CONT_POLY,42onymous_ +V 2000,3000,CONT_VIA,41onymous_ +V 3000,8000,CONT_DIF_P,40onymous_ +V 3000,7000,CONT_DIF_P,39onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nao3.vbe b/pdks/symbolic/nrf2lib/cells/rf2_dec_nao3.vbe new file mode 100644 index 000000000..fc2d2bbb1 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nao3.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_nao3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nao3; + +ARCHITECTURE VBE OF rf2_dec_nao3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nao3" + SEVERITY WARNING; + + nq <= not(i2 and (i1 or i0)); + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nbuf.ap b/pdks/symbolic/nrf2lib/cells/rf2_dec_nbuf.ap new file mode 100644 index 000000000..83306cb21 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nbuf.ap @@ -0,0 +1,79 @@ +V ALLIANCE : 6 +H rf2_dec_nbuf,P,24/4/2016,100 +A 0,0,21000,10000 +S 10000,2000,10000,8000,300,i,UP,CALU1 +S 5400,6000,5400,9000,300,6nonymous_,UP,ALU1 +S 5400,1000,5400,2000,300,5nonymous_,UP,ALU1 +S 5400,700,5400,2300,600,4nonymous_,UP,NDIF +S 5400,5700,5400,9300,600,3nonymous_,UP,PDIF +S 3000,6000,3000,9000,300,2nonymous_,UP,ALU1 +S 1200,4000,10000,4000,600,1nonymous_,RIGHT,POLY +S -600,7800,21600,7800,6000,0nonymous_,RIGHT,NWELL +S 0,600,21000,600,1200,vss,RIGHT,CALU1 +S 0,9400,21000,9400,1200,vdd,RIGHT,CALU1 +S 1850,2000,4150,2000,600,nq,RIGHT,CALU2 +S 3000,700,3000,2300,600,16onymous_,UP,NDIF +S 4200,700,4200,2300,600,15onymous_,UP,NDIF +S 600,700,600,2300,600,14onymous_,UP,NDIF +S 1800,700,1800,2300,600,13onymous_,UP,NDIF +S 4800,5500,4800,9500,200,12onymous_,UP,PTRANS +S 1200,2800,1200,5200,200,11onymous_,UP,POLY +S 2400,2800,2400,5200,200,10onymous_,UP,POLY +S 3600,2800,3600,5200,200,9nonymous_,UP,POLY +S 4800,2800,4800,5200,200,8nonymous_,UP,POLY +S 4200,2000,4200,8000,300,7nonymous_,UP,ALU1 +S 2400,500,2400,2500,200,17onymous_,UP,NTRANS +S 1200,500,1200,2500,200,18onymous_,UP,NTRANS +S 1800,2000,1800,8000,300,35onymous_,UP,ALU1 +S 2000,5000,4200,5000,300,34onymous_,RIGHT,ALU1 +S 6800,280,6800,3320,600,33onymous_,UP,PTIE +S 6800,5680,6800,9720,600,32onymous_,UP,NTIE +S 6800,6000,6800,9400,300,31onymous_,UP,ALU1 +S 6800,600,6800,3000,300,30onymous_,UP,ALU1 +S 3000,5700,3000,9300,600,29onymous_,UP,PDIF +S 600,5700,600,9300,600,28onymous_,UP,PDIF +S 600,1000,600,2000,300,27onymous_,UP,ALU1 +S 600,6000,600,9000,300,26onymous_,UP,ALU1 +S 3600,5500,3600,9500,200,25onymous_,UP,PTRANS +S 4200,5700,4200,9300,600,24onymous_,UP,PDIF +S 2400,5500,2400,9500,200,23onymous_,UP,PTRANS +S 1200,5500,1200,9500,200,22onymous_,UP,PTRANS +S 1800,5700,1800,9300,600,21onymous_,UP,PDIF +S 3600,500,3600,2500,200,20onymous_,UP,NTRANS +S 4800,500,4800,2500,200,19onymous_,UP,NTRANS +V 2000,2000,CONT_VIA,36onymous_ +V 4000,2000,CONT_VIA,37onymous_ +V 10000,4000,CONT_POLY,38onymous_ +V 3000,8000,CONT_DIF_P,39onymous_ +V 3000,7000,CONT_DIF_P,40onymous_ +V 3000,6000,CONT_DIF_P,41onymous_ +V 5400,9000,CONT_DIF_P,42onymous_ +V 5400,7000,CONT_DIF_P,43onymous_ +V 5400,6000,CONT_DIF_P,44onymous_ +V 5400,8000,CONT_DIF_P,45onymous_ +V 5400,1000,CONT_DIF_N,46onymous_ +V 5400,2000,CONT_DIF_N,47onymous_ +V 1800,2000,CONT_DIF_N,48onymous_ +V 4200,2000,CONT_DIF_N,49onymous_ +V 4200,8000,CONT_DIF_P,50onymous_ +V 4200,7000,CONT_DIF_P,51onymous_ +V 4200,6000,CONT_DIF_P,52onymous_ +V 6800,3000,CONT_BODY_P,70onymous_ +V 6800,600,CONT_BODY_P,69onymous_ +V 6800,2000,CONT_BODY_P,68onymous_ +V 6800,6000,CONT_BODY_N,67onymous_ +V 6800,7000,CONT_BODY_N,66onymous_ +V 6800,8000,CONT_BODY_N,65onymous_ +V 6800,9300,CONT_BODY_N,64onymous_ +V 3000,1000,CONT_DIF_N,63onymous_ +V 3000,9000,CONT_DIF_P,62onymous_ +V 600,8000,CONT_DIF_P,61onymous_ +V 600,7000,CONT_DIF_P,60onymous_ +V 600,6000,CONT_DIF_P,59onymous_ +V 600,1000,CONT_DIF_N,58onymous_ +V 600,2000,CONT_DIF_N,57onymous_ +V 600,9000,CONT_DIF_P,56onymous_ +V 1800,8000,CONT_DIF_P,55onymous_ +V 1800,6000,CONT_DIF_P,54onymous_ +V 1800,7000,CONT_DIF_P,53onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nbuf.vbe b/pdks/symbolic/nrf2lib/cells/rf2_dec_nbuf.vbe new file mode 100644 index 000000000..e4101d765 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nbuf.vbe @@ -0,0 +1,19 @@ +ENTITY rf2_dec_nbuf IS +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nbuf; + +ARCHITECTURE VBE OF rf2_dec_nbuf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nbuf" + SEVERITY WARNING; + + nq <= not i; + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nor3.ap b/pdks/symbolic/nrf2lib/cells/rf2_dec_nor3.ap new file mode 100644 index 000000000..c0e4f1c51 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nor3.ap @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H rf2_dec_nor3,P,24/4/2016,100 +A 0,0,7000,10000 +S 2000,5500,2000,9500,200,17onymous_,UP,PTRANS +S 2800,5500,2800,9500,200,16onymous_,UP,PTRANS +S 2400,1500,2400,2500,200,15onymous_,UP,NTRANS +S 2000,4000,2800,4000,600,4nonymous_,RIGHT,POLY +S 3600,2800,3600,5200,200,3nonymous_,UP,POLY +S -600,7800,7600,7800,6000,2nonymous_,RIGHT,NWELL +S 1000,5700,1000,9300,600,1nonymous_,UP,PDIF +S 1400,5700,1400,9300,600,0nonymous_,UP,PDIF +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 3600,1500,3600,2500,200,14onymous_,UP,NTRANS +S 1200,1500,1200,2500,200,13onymous_,UP,NTRANS +S 4200,5700,4200,9300,600,12onymous_,UP,PDIF +S 1800,900,1800,2300,600,11onymous_,UP,NDIF +S 600,1700,600,2300,600,10onymous_,UP,NDIF +S 4200,900,4200,2300,600,9nonymous_,UP,NDIF +S 3000,1700,3000,2300,600,8nonymous_,UP,NDIF +S 600,2000,3000,2000,300,7nonymous_,RIGHT,ALU1 +S 2400,2800,2400,4200,200,6nonymous_,UP,POLY +S 2800,3800,2800,5200,200,5nonymous_,UP,POLY +S 1850,3000,2150,3000,600,nq,RIGHT,CALU2 +S 3600,5500,3600,9500,200,18onymous_,UP,PTRANS +S 850,4000,2150,4000,600,29onymous_,RIGHT,ALU2 +S 4400,900,4400,2300,600,28onymous_,UP,NDIF +S 4000,2000,4000,3000,300,27onymous_,UP,ALU1 +S 3000,2000,3000,3000,300,26onymous_,UP,ALU1 +S 1000,3000,3000,3000,300,25onymous_,RIGHT,ALU1 +S 3600,3000,4200,3000,600,24onymous_,RIGHT,POLY +S 2000,5000,2000,8000,300,23onymous_,UP,ALU1 +S 4200,6000,4200,9000,300,22onymous_,UP,ALU1 +S 1200,4800,2200,4800,200,19onymous_,RIGHT,POLY +S 1200,2800,1200,4800,200,20onymous_,UP,POLY +S 1000,2000,1000,8000,300,21onymous_,UP,ALU1 +S 3850,2000,4150,2000,600,i2,RIGHT,CALU2 +S 850,4000,1150,4000,600,i1,RIGHT,CALU2 +S 1850,8000,2150,8000,600,i0,RIGHT,CALU2 +V 3000,600,CONT_BODY_P,34onymous_ +V 4200,1000,CONT_DIF_N,33onymous_ +V 2000,4000,CONT_VIA,32onymous_ +V 2000,4000,CONT_POLY,31onymous_ +V 5600,9300,CONT_BODY_N,30onymous_ +V 4000,2000,CONT_VIA,50onymous_ +V 2000,3000,CONT_VIA,49onymous_ +V 4000,3000,CONT_POLY,48onymous_ +V 4200,6000,CONT_DIF_P,47onymous_ +V 4200,7000,CONT_DIF_P,46onymous_ +V 4200,8000,CONT_DIF_P,45onymous_ +V 1000,6000,CONT_DIF_P,44onymous_ +V 1000,7000,CONT_DIF_P,43onymous_ +V 1000,8000,CONT_DIF_P,42onymous_ +V 2000,8000,CONT_VIA,41onymous_ +V 2000,5000,CONT_POLY,40onymous_ +V 4200,9000,CONT_DIF_P,39onymous_ +V 3000,2000,CONT_DIF_N,38onymous_ +V 600,2000,CONT_DIF_N,37onymous_ +V 1800,1000,CONT_DIF_N,36onymous_ +V 600,600,CONT_BODY_P,35onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_dec_nor3.vbe b/pdks/symbolic/nrf2lib/cells/rf2_dec_nor3.vbe new file mode 100644 index 000000000..f62600785 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_dec_nor3.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_nor3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nor3; + +ARCHITECTURE VBE OF rf2_dec_nor3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nor3" + SEVERITY WARNING; + + nq <= not(i0 or i1 or i2); + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_inmux_buf.ap b/pdks/symbolic/nrf2lib/cells/rf2_inmux_buf.ap new file mode 100644 index 000000000..8ececdeac --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_inmux_buf.ap @@ -0,0 +1,147 @@ +V ALLIANCE : 6 +H rf2_inmux_buf,P,24/4/2016,100 +A 0,0,9000,20000 +S 0,10600,9000,10600,1200,vdd,RIGHT,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 0,19400,9000,19400,1200,vss,RIGHT,CALU1 +S 5050,8000,7950,8000,300,0nonymous_,RIGHT,TALU2 +S 1050,3000,4950,3000,300,1nonymous_,RIGHT,TALU2 +S 1650,3000,5150,3000,600,2nonymous_,RIGHT,ALU2 +S 9000,1000,9000,2000,300,3nonymous_,UP,ALU1 +S 600,1000,600,3200,300,4nonymous_,UP,ALU1 +S 6600,1000,6600,3200,300,5nonymous_,UP,ALU1 +S 7800,2000,7800,8000,300,16onymous_,UP,ALU1 +S 5400,2000,5400,8000,300,17onymous_,UP,ALU1 +S 4200,2000,4200,8000,300,18onymous_,UP,ALU1 +S 3000,1000,3000,3200,300,6nonymous_,UP,ALU1 +S 1200,4800,3600,4800,600,7nonymous_,RIGHT,POLY +S 4200,4800,8400,4800,600,8nonymous_,RIGHT,POLY +S 3000,6000,3000,9000,300,9nonymous_,UP,ALU1 +S 6600,6000,6600,9000,300,10onymous_,UP,ALU1 +S 8400,2600,8400,6200,200,11onymous_,UP,POLY +S 8400,6500,8400,9500,200,12onymous_,UP,PTRANS +S 9000,6700,9000,9300,600,13onymous_,UP,PDIF +S 7200,2600,7200,5200,200,14onymous_,UP,POLY +S 6000,2600,6000,5200,200,15onymous_,UP,POLY +S 3000,5700,3000,9300,600,23onymous_,UP,PDIF +S 1200,5500,1200,9500,200,24onymous_,UP,PTRANS +S 2400,5500,2400,9500,200,25onymous_,UP,PTRANS +S 3600,5500,3600,9500,200,26onymous_,UP,PTRANS +S 600,700,600,2100,600,27onymous_,UP,NDIF +S 1800,700,1800,2100,600,28onymous_,UP,NDIF +S 3000,700,3000,2100,600,29onymous_,UP,NDIF +S 4200,700,4200,2100,600,30onymous_,UP,NDIF +S 5400,700,5400,2100,600,31onymous_,UP,NDIF +S 9000,700,9000,2100,600,32onymous_,UP,NDIF +S 7800,700,7800,2100,600,33onymous_,UP,NDIF +S 6600,700,6600,2100,600,34onymous_,UP,NDIF +S 1200,500,1200,2300,200,35onymous_,UP,NTRANS +S 1800,5700,1800,9300,600,22onymous_,UP,PDIF +S 600,5700,600,9300,600,21onymous_,UP,PDIF +S 600,6000,600,9000,300,20onymous_,UP,ALU1 +S 1800,2000,1800,8000,300,19onymous_,UP,ALU1 +S 6600,5700,6600,9300,600,36onymous_,UP,PDIF +S 6000,5500,6000,9500,200,37onymous_,UP,PTRANS +S 7200,5500,7200,9500,200,38onymous_,UP,PTRANS +S 5400,5700,5400,9300,600,39onymous_,UP,PDIF +S 7800,5700,7800,9300,600,40onymous_,UP,PDIF +S 4200,5700,4200,9300,600,41onymous_,UP,PDIF +S -600,7800,10000,7800,6000,42onymous_,RIGHT,NWELL +S -600,12200,10000,12200,6000,43onymous_,RIGHT,NWELL +S 8400,500,8400,2300,200,44onymous_,UP,NTRANS +S 7200,500,7200,2300,200,45onymous_,UP,NTRANS +S 6000,500,6000,2300,200,46onymous_,UP,NTRANS +S 3600,500,3600,2300,200,47onymous_,UP,NTRANS +S 2400,500,2400,2300,200,48onymous_,UP,NTRANS +S 1200,2600,1200,5200,200,49onymous_,UP,POLY +S 2400,2600,2400,5200,200,50onymous_,UP,POLY +S 3600,2600,3600,5200,200,51onymous_,UP,POLY +S 9000,7000,9000,9000,300,52onymous_,UP,ALU1 +S 600,11000,600,14000,300,53onymous_,UP,ALU1 +S 1200,17700,1200,19500,200,54onymous_,UP,NTRANS +S 600,16800,600,19000,300,55onymous_,UP,ALU1 +S 600,17900,600,19300,600,56onymous_,UP,NDIF +S 1800,17900,1800,19300,600,57onymous_,UP,NDIF +S 1200,9800,3600,9800,200,58onymous_,RIGHT,POLY +S 2400,9800,2400,12000,200,59onymous_,UP,POLY +S 3600,9800,3600,12000,200,60onymous_,UP,POLY +S 2400,12000,3600,12000,600,61onymous_,RIGHT,POLY +S 1800,12000,1800,18000,300,62onymous_,UP,ALU1 +S 1800,12000,3000,12000,300,63onymous_,RIGHT,ALU1 +S 1200,14800,1200,17400,200,64onymous_,UP,POLY +S 1200,16000,3000,16000,200,65onymous_,RIGHT,POLY +S 1200,10700,1200,14500,200,66onymous_,UP,PTRANS +S 1800,10900,1800,14300,600,67onymous_,UP,PDIF +S 600,10900,600,14300,600,68onymous_,UP,PDIF +S 5250,8000,7950,8000,600,69onymous_,RIGHT,ALU2 +S 3000,14000,3000,18000,300,sel,UP,CALU1 +S 7000,7850,7000,8150,400,sel0,UP,CALU3 +S 5000,2850,5000,3150,400,sel1,UP,CALU3 +V 600,2000,CONT_DIF_N,75onymous_ +V 9000,2000,CONT_DIF_N,74onymous_ +V 3000,19000,CONT_BODY_P,73onymous_ +V 1800,3000,CONT_VIA,72onymous_ +V 600,3200,CONT_BODY_P,76onymous_ +V 3000,3200,CONT_BODY_P,77onymous_ +V 4200,3000,CONT_VIA,78onymous_ +V 4400,4800,CONT_POLY,79onymous_ +V 6600,3200,CONT_BODY_P,80onymous_ +V 9000,9000,CONT_DIF_P,81onymous_ +V 1800,6000,CONT_DIF_P,82onymous_ +V 6600,10800,CONT_BODY_N,70onymous_ +V 4400,10800,CONT_BODY_N,71onymous_ +V 1800,7000,CONT_DIF_P,83onymous_ +V 1800,8000,CONT_DIF_P,84onymous_ +V 4200,6000,CONT_DIF_P,85onymous_ +V 4200,8000,CONT_DIF_P,86onymous_ +V 4200,7000,CONT_DIF_P,87onymous_ +V 7800,2000,CONT_DIF_N,88onymous_ +V 5400,2000,CONT_DIF_N,89onymous_ +V 4200,2000,CONT_DIF_N,90onymous_ +V 1800,2000,CONT_DIF_N,91onymous_ +V 5400,6000,CONT_DIF_P,92onymous_ +V 7800,6000,CONT_DIF_P,93onymous_ +V 9000,7000,CONT_DIF_P,94onymous_ +V 9000,8000,CONT_DIF_P,95onymous_ +V 3000,6000,CONT_DIF_P,96onymous_ +V 3000,8000,CONT_DIF_P,97onymous_ +V 3000,7000,CONT_DIF_P,98onymous_ +V 3000,9000,CONT_DIF_P,99onymous_ +V 600,9000,CONT_DIF_P,100nymous_ +V 600,7000,CONT_DIF_P,101nymous_ +V 600,8000,CONT_DIF_P,102nymous_ +V 600,6000,CONT_DIF_P,103nymous_ +V 9000,1000,CONT_DIF_N,104nymous_ +V 6600,1000,CONT_DIF_N,105nymous_ +V 3000,1000,CONT_DIF_N,106nymous_ +V 600,1000,CONT_DIF_N,107nymous_ +V 5400,8000,CONT_DIF_P,108nymous_ +V 7800,7000,CONT_DIF_P,109nymous_ +V 7800,8000,CONT_DIF_P,110nymous_ +V 6600,7000,CONT_DIF_P,111nymous_ +V 6600,6000,CONT_DIF_P,112nymous_ +V 6600,8000,CONT_DIF_P,113nymous_ +V 6600,9000,CONT_DIF_P,114nymous_ +V 5400,7000,CONT_DIF_P,115nymous_ +V 5400,8000,CONT_VIA,116nymous_ +V 7800,8000,CONT_VIA,117nymous_ +V 6600,2000,CONT_DIF_N,118nymous_ +V 3000,2000,CONT_DIF_N,119nymous_ +V 600,11000,CONT_DIF_P,120nymous_ +V 600,14000,CONT_DIF_P,121nymous_ +V 600,13000,CONT_DIF_P,122nymous_ +V 600,12000,CONT_DIF_P,123nymous_ +V 1800,14000,CONT_DIF_P,124nymous_ +V 1800,12000,CONT_DIF_P,125nymous_ +V 1800,13000,CONT_DIF_P,126nymous_ +V 600,16800,CONT_BODY_P,127nymous_ +V 600,19000,CONT_DIF_N,128nymous_ +V 600,18000,CONT_DIF_N,129nymous_ +V 1800,18000,CONT_DIF_N,130nymous_ +V 3000,10800,CONT_BODY_N,131nymous_ +V 3000,12000,CONT_POLY,132nymous_ +V 3000,16000,CONT_POLY,133nymous_ +V 7000,8000,CONT_VIA2,134nymous_ +V 5000,3000,CONT_VIA2,135nymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_inmux_buf.vbe b/pdks/symbolic/nrf2lib/cells/rf2_inmux_buf.vbe new file mode 100644 index 000000000..f24eee1ec --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_inmux_buf.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_inmux_buf IS +PORT ( + sel : in BIT; + sel0 : out BIT; + sel1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_inmux_buf; + +ARCHITECTURE VBE OF rf2_inmux_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_inmux_buf" + SEVERITY WARNING; + + sel1 <= sel; + sel0 <= not sel; + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_inmux_mem.ap b/pdks/symbolic/nrf2lib/cells/rf2_inmux_mem.ap new file mode 100644 index 000000000..59f8e6e0d --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_inmux_mem.ap @@ -0,0 +1,97 @@ +V ALLIANCE : 6 +H rf2_inmux_mem,P,24/4/2016,100 +A 0,0,9000,10000 +S 5050,6000,6950,6000,300,vdd,RIGHT,TALU2 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 600,1000,600,3400,300,0nonymous_,UP,ALU1 +S 600,6000,600,9000,300,1nonymous_,UP,ALU1 +S 600,700,600,2300,600,2nonymous_,UP,NDIF +S 1200,500,1200,2500,200,3nonymous_,UP,NTRANS +S 5200,500,5200,1500,200,14onymous_,UP,NTRANS +S 4400,500,4400,1500,200,15onymous_,UP,NTRANS +S 5200,1800,5200,4000,200,16onymous_,UP,POLY +S 4400,1800,4400,2800,200,17onymous_,UP,POLY +S 6000,700,6000,3100,600,18onymous_,UP,NDIF +S 6000,3000,6000,8000,300,4nonymous_,UP,ALU1 +S 1800,700,1800,2300,600,5nonymous_,UP,NDIF +S 2400,500,2400,2500,200,6nonymous_,UP,NTRANS +S 3400,700,3400,2300,1400,7nonymous_,UP,NDIF +S 3000,6000,3000,9000,300,8nonymous_,UP,ALU1 +S 3800,2800,4400,2800,200,9nonymous_,RIGHT,POLY +S 7600,500,7600,1500,200,10onymous_,UP,NTRANS +S 6800,500,6800,1500,200,11onymous_,UP,NTRANS +S 3000,1000,3000,3400,300,12onymous_,UP,ALU1 +S 8200,700,8200,1300,600,13onymous_,UP,NDIF +S 5000,2000,6800,2000,300,23onymous_,RIGHT,ALU1 +S 1200,2800,1200,5200,200,24onymous_,UP,POLY +S 2400,2800,2400,5200,200,25onymous_,UP,POLY +S 1200,5500,1200,9500,200,26onymous_,UP,PTRANS +S 2400,5500,2400,9500,200,27onymous_,UP,PTRANS +S 600,5700,600,9300,600,28onymous_,UP,PDIF +S 3000,5700,3000,6500,600,29onymous_,UP,PDIF +S 1800,5700,1800,9300,600,30onymous_,UP,PDIF +S 7600,7100,7600,9100,200,31onymous_,UP,PTRANS +S 6800,7100,6800,9100,200,32onymous_,UP,PTRANS +S 4400,7100,4400,9100,200,33onymous_,UP,PTRANS +S 5800,700,5800,3100,600,22onymous_,UP,NDIF +S 6000,700,6000,1300,1000,21onymous_,UP,NDIF +S 7600,1800,7600,2800,200,20onymous_,UP,POLY +S 7600,2800,8000,2800,200,19onymous_,RIGHT,POLY +S 5200,7100,5200,9100,200,34onymous_,UP,PTRANS +S 6000,7300,6000,8900,1000,35onymous_,UP,PDIF +S 8200,7300,8200,9100,600,36onymous_,UP,PDIF +S 3400,7300,3400,9300,1400,37onymous_,UP,PDIF +S 3800,6800,4400,6800,200,38onymous_,RIGHT,POLY +S 5200,5800,5200,6800,200,39onymous_,UP,POLY +S 5000,2000,5000,6000,300,40onymous_,UP,ALU1 +S 7600,6800,8200,6800,200,41onymous_,RIGHT,POLY +S 1200,5000,6000,5000,200,42onymous_,RIGHT,POLY +S -600,7800,7800,7800,6000,43onymous_,RIGHT,NWELL +S -600,8600,9600,8600,4400,44onymous_,RIGHT,NWELL +S 6800,4000,6800,6800,200,45onymous_,UP,POLY +S 5200,4000,6800,4000,200,46onymous_,RIGHT,POLY +S 1800,2000,1800,8000,300,47onymous_,UP,ALU1 +S 7000,5850,7000,6150,400,sel0,UP,CALU3 +S 5000,5850,5000,6150,400,sel1,UP,CALU3 +S 4000,3000,4000,8000,300,datain0,UP,CALU1 +S 8000,3000,8000,8000,300,datain1,UP,CALU1 +S 1850,2000,2150,2000,600,dinx,RIGHT,CALU2 +V 3000,6000,CONT_DIF_P,73onymous_ +V 3000,2000,CONT_DIF_N,72onymous_ +V 3000,9000,CONT_DIF_P,71onymous_ +V 3000,1000,CONT_DIF_N,70onymous_ +V 3000,3400,CONT_BODY_P,74onymous_ +V 6800,2000,CONT_POLY,75onymous_ +V 5000,6000,CONT_POLY,76onymous_ +V 4000,6600,CONT_POLY,77onymous_ +V 8000,6600,CONT_POLY,78onymous_ +V 6000,5000,CONT_POLY,79onymous_ +V 5000,6000,CONT_VIA,80onymous_ +V 7000,6000,CONT_VIA,81onymous_ +V 7000,6000,CONT_POLY,82onymous_ +V 7000,10000,CONT_BODY_N,48onymous_ +V 5000,10000,CONT_BODY_N,49onymous_ +V 2000,2000,CONT_VIA,50onymous_ +V 600,2000,CONT_DIF_N,51onymous_ +V 600,1000,CONT_DIF_N,52onymous_ +V 600,3400,CONT_BODY_P,53onymous_ +V 600,8000,CONT_DIF_P,54onymous_ +V 600,9000,CONT_DIF_P,55onymous_ +V 600,6000,CONT_DIF_P,56onymous_ +V 600,7000,CONT_DIF_P,57onymous_ +V 4000,3000,CONT_POLY,58onymous_ +V 8200,1000,CONT_DIF_N,59onymous_ +V 8200,9000,CONT_DIF_P,60onymous_ +V 8000,3000,CONT_POLY,61onymous_ +V 6000,3000,CONT_DIF_N,62onymous_ +V 6000,8000,CONT_DIF_P,63onymous_ +V 3000,7000,CONT_DIF_P,64onymous_ +V 3000,8000,CONT_DIF_P,65onymous_ +V 1800,7000,CONT_DIF_P,66onymous_ +V 1800,8000,CONT_DIF_P,67onymous_ +V 1800,6000,CONT_DIF_P,68onymous_ +V 1800,2000,CONT_DIF_N,69onymous_ +V 7000,6000,CONT_VIA2,83onymous_ +V 5000,6000,CONT_VIA2,84onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_inmux_mem.vbe b/pdks/symbolic/nrf2lib/cells/rf2_inmux_mem.vbe new file mode 100644 index 000000000..c67f278a1 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_inmux_mem.vbe @@ -0,0 +1,22 @@ +ENTITY rf2_inmux_mem IS +PORT ( + datain0 : in BIT; + datain1 : in BIT; + sel0 : in BIT; + sel1 : in BIT; + dinx : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_inmux_mem; + +ARCHITECTURE VBE OF rf2_inmux_mem IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_inmux_mem" + SEVERITY WARNING; + + dinx <= (sel0 and datain0) or (sel1 and datain1); + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_mid_buf.ap b/pdks/symbolic/nrf2lib/cells/rf2_mid_buf.ap new file mode 100644 index 000000000..93cf222e8 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_mid_buf.ap @@ -0,0 +1,234 @@ +V ALLIANCE : 6 +H rf2_mid_buf,P,24/4/2016,100 +A 0,0,7000,20000 +S 1050,3000,5950,3000,300,18onymous_,RIGHT,TALU2 +S 3050,4000,4950,4000,300,17onymous_,RIGHT,TALU2 +S 1050,8000,5950,8000,300,16onymous_,RIGHT,TALU2 +S 1050,12000,5950,12000,300,15onymous_,RIGHT,TALU2 +S 3050,13000,5950,13000,300,14onymous_,RIGHT,TALU2 +S 5000,4050,5000,12950,300,13onymous_,UP,TALU3 +S 3000,4050,3000,12950,300,12onymous_,UP,TALU3 +S 3600,8900,3600,11100,400,1nonymous_,UP,PDIF +S 5800,8900,5800,11100,400,0nonymous_,UP,PDIF +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,19400,7000,19400,1200,vss,RIGHT,CALU1 +S 5800,1700,5800,3500,600,11onymous_,UP,NDIF +S 4700,700,4700,3500,400,10onymous_,UP,NDIF +S 3000,300,3000,3700,200,9nonymous_,UP,NTRANS +S 6400,300,6400,3700,200,8nonymous_,UP,NTRANS +S 5800,500,5800,3500,400,7nonymous_,UP,NDIF +S 3600,500,3600,3500,400,6nonymous_,UP,NDIF +S 2400,500,2400,3500,600,5nonymous_,UP,NDIF +S 3000,6500,3000,12500,200,4nonymous_,UP,PTRANS +S 6400,6500,6400,12500,200,3nonymous_,UP,PTRANS +S 4700,8900,4700,11100,400,2nonymous_,UP,PDIF +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,10600,7000,10600,1200,vdd,RIGHT,CALU1 +S 600,17700,600,19500,200,78onymous_,UP,NTRANS +S 1400,17700,1400,19500,200,77onymous_,UP,NTRANS +S 0,17900,0,19300,600,76onymous_,UP,NDIF +S 1800,16400,1800,17200,200,75onymous_,UP,POLY +S 1400,16800,1400,17400,200,74onymous_,UP,POLY +S 1400,17000,2200,17000,600,73onymous_,RIGHT,POLY +S 600,4000,600,6200,200,72onymous_,UP,POLY +S 5200,13000,6400,13000,600,31onymous_,RIGHT,POLY +S 6000,13000,6000,18000,300,30onymous_,UP,ALU1 +S 4000,13000,4000,18000,300,29onymous_,UP,ALU1 +S 1000,13000,1000,18000,300,28onymous_,UP,ALU1 +S 4850,13000,6150,13000,600,27onymous_,RIGHT,ALU2 +S 2850,13000,4150,13000,600,26onymous_,RIGHT,ALU2 +S 3000,3850,3000,13150,400,25onymous_,UP,ALU3 +S 5000,3850,5000,13150,400,24onymous_,UP,ALU3 +S 3000,4200,4200,4200,600,23onymous_,RIGHT,POLY +S 5200,4200,6400,4200,600,22onymous_,RIGHT,POLY +S 3450,3000,4150,3000,600,21onymous_,RIGHT,ALU2 +S 3450,8000,4150,8000,600,20onymous_,RIGHT,ALU2 +S 600,4200,1800,4200,600,19onymous_,RIGHT,POLY +S 3000,13000,4200,13000,600,32onymous_,RIGHT,POLY +S 600,13000,1800,13000,600,33onymous_,RIGHT,POLY +S 3600,18000,4000,18000,300,34onymous_,RIGHT,ALU1 +S 2600,14500,2600,15900,1000,35onymous_,UP,PDIF +S 6400,16400,6400,17200,200,36onymous_,UP,POLY +S 5400,16800,5400,17400,200,37onymous_,UP,POLY +S 4200,16800,4200,17400,200,38onymous_,UP,POLY +S 3400,16400,3400,17200,200,39onymous_,UP,POLY +S 4000,14500,4000,15900,600,40onymous_,UP,PDIF +S 3400,14300,3400,16100,200,41onymous_,UP,PTRANS +S 3000,17000,4200,17000,600,42onymous_,RIGHT,POLY +S 5000,17000,6400,17000,600,43onymous_,RIGHT,POLY +S 4800,17900,4800,19100,600,44onymous_,UP,NDIF +S 3600,17900,3600,18300,600,45onymous_,UP,NDIF +S 6000,17900,6000,18300,600,46onymous_,UP,NDIF +S 4200,17700,4200,18500,200,47onymous_,UP,NTRANS +S 5400,17700,5400,18500,200,48onymous_,UP,NTRANS +S 5800,14500,5800,15900,600,49onymous_,UP,PDIF +S 2000,17900,2000,19300,600,50onymous_,UP,NDIF +S 7000,500,7000,3500,600,51onymous_,UP,NDIF +S 1800,4000,1800,6200,200,71onymous_,UP,POLY +S 600,16400,600,17400,200,70onymous_,UP,POLY +S -200,17000,600,17000,600,69onymous_,RIGHT,POLY +S 1000,18000,2000,18000,300,68onymous_,RIGHT,ALU1 +S 0,17000,0,18000,300,67onymous_,UP,ALU1 +S 0,5600,0,15800,300,66onymous_,UP,ALU1 +S 0,1000,0,3000,300,65onymous_,UP,ALU1 +S 3600,11300,3600,12300,600,64onymous_,UP,PDIF +S 4200,6500,4200,9100,200,63onymous_,UP,PTRANS +S 5800,6700,5800,8700,600,62onymous_,UP,PDIF +S 5200,10900,5200,12500,200,61onymous_,UP,PTRANS +S 5800,11300,5800,12300,600,60onymous_,UP,PDIF +S 3600,6700,3600,8700,600,59onymous_,UP,PDIF +S 3600,1900,3600,3500,600,58onymous_,UP,NDIF +S 4200,1500,4200,3700,200,57onymous_,UP,NTRANS +S 5200,1500,5200,3700,200,56onymous_,UP,NTRANS +S 600,300,600,3700,200,55onymous_,UP,NTRANS +S 1800,300,1800,3700,200,54onymous_,UP,NTRANS +S 1200,500,1200,3500,600,53onymous_,UP,NDIF +S 0,500,0,3500,600,52onymous_,UP,NDIF +S 600,14300,600,16100,200,79onymous_,UP,PTRANS +S 1200,6700,1200,12300,600,80onymous_,UP,PDIF +S 600,6500,600,12500,200,81onymous_,UP,PTRANS +S 0,14500,0,15900,600,82onymous_,UP,PDIF +S 1800,14300,1800,16100,200,83onymous_,UP,PTRANS +S 1200,14500,1200,15900,400,84onymous_,UP,PDIF +S 0,6700,0,12300,600,85onymous_,UP,PDIF +S 1800,6500,1800,12500,200,86onymous_,UP,PTRANS +S 2400,1000,2400,3000,300,87onymous_,UP,ALU1 +S 3000,4000,3000,6200,200,88onymous_,UP,POLY +S 4200,4000,4200,6200,200,89onymous_,UP,POLY +S 7000,1000,7000,3000,300,90onymous_,UP,ALU1 +S 7000,5600,7000,15800,300,91onymous_,UP,ALU1 +S 6400,4000,6400,6200,200,92onymous_,UP,POLY +S 5200,4000,5200,6200,200,93onymous_,UP,POLY +S 7000,14500,7000,15900,600,94onymous_,UP,PDIF +S 6400,14300,6400,16100,200,95onymous_,UP,PTRANS +S 7000,6700,7000,12300,600,96onymous_,UP,PDIF +S -1000,13000,8000,13000,7600,97onymous_,RIGHT,NWELL +S -1000,7800,8000,7800,6400,98onymous_,RIGHT,NWELL +S 2400,6700,2400,12300,600,99onymous_,UP,PDIF +S 5800,17900,5800,18300,600,100nymous_,UP,NDIF +S 2400,5600,2400,15800,300,101nymous_,UP,ALU1 +S 5200,6500,5200,9100,200,102nymous_,UP,PTRANS +S 4200,10900,4200,12500,200,103nymous_,UP,PTRANS +S 0,5600,7000,5600,300,104nymous_,RIGHT,ALU1 +S 1200,2000,1200,3000,300,105nymous_,UP,ALU1 +S 5800,2200,5800,3000,300,106nymous_,UP,ALU1 +S 3600,2200,3600,3000,300,107nymous_,UP,ALU1 +S 3600,7000,3600,8000,300,108nymous_,UP,ALU1 +S 5800,7000,5800,8000,300,109nymous_,UP,ALU1 +S 1200,7000,1200,8000,300,110nymous_,UP,ALU1 +S 1000,2850,1000,12150,400,write,UP,CALU3 +S 6000,2850,6000,12150,400,readb,UP,CALU3 +S 4000,2850,4000,12150,400,reada,UP,CALU3 +S -150,18000,150,18000,600,nck,RIGHT,CALU2 +S 1850,17000,2150,17000,600,selw,RIGHT,CALU2 +S 4850,17000,5150,17000,600,selrb,RIGHT,CALU2 +S 2850,17000,3150,17000,600,selra,RIGHT,CALU2 +V 4700,10000,CONT_DIF_P,111nymous_ +V 4700,600,CONT_DIF_N,112nymous_ +V 0,13400,CONT_BODY_N,113nymous_ +V 3000,4200,CONT_POLY,114nymous_ +V 5000,4200,CONT_POLY,115nymous_ +V 3000,4000,CONT_VIA,116nymous_ +V 5000,4000,CONT_VIA,117nymous_ +V 3000,4000,CONT_VIA2,118nymous_ +V 5000,4000,CONT_VIA2,119nymous_ +V 6000,13000,CONT_VIA,120nymous_ +V 2400,13400,CONT_BODY_N,121nymous_ +V 4000,13000,CONT_VIA,122nymous_ +V 5000,13000,CONT_VIA2,123nymous_ +V 3000,13000,CONT_VIA2,124nymous_ +V 4000,13000,CONT_POLY,125nymous_ +V 6000,13000,CONT_POLY,126nymous_ +V 1000,13000,CONT_POLY,127nymous_ +V 4000,15800,CONT_DIF_P,128nymous_ +V 4000,14800,CONT_DIF_P,129nymous_ +V 6200,19400,CONT_BODY_P,130nymous_ +V 3000,17000,CONT_POLY,131nymous_ +V 5000,17000,CONT_POLY,132nymous_ +V 4800,19000,CONT_DIF_N,133nymous_ +V 3600,18000,CONT_DIF_N,134nymous_ +V 5000,17000,CONT_VIA,135nymous_ +V 2000,17000,CONT_POLY,151nymous_ +V 0,17000,CONT_POLY,150nymous_ +V 0,18000,CONT_VIA,149nymous_ +V 2000,17000,CONT_VIA,148nymous_ +V 1000,8000,CONT_VIA,147nymous_ +V 1000,12000,CONT_VIA,146nymous_ +V 1000,3000,CONT_VIA,145nymous_ +V 1000,12000,CONT_VIA2,144nymous_ +V 1000,3000,CONT_VIA2,143nymous_ +V 1000,8000,CONT_VIA2,142nymous_ +V 3200,19400,CONT_BODY_P,141nymous_ +V 2400,12000,CONT_DIF_P,140nymous_ +V 6000,18000,CONT_DIF_N,139nymous_ +V 5800,15800,CONT_DIF_P,138nymous_ +V 5800,14800,CONT_DIF_P,137nymous_ +V 3000,17000,CONT_VIA,136nymous_ +V 0,1000,CONT_DIF_N,152nymous_ +V 2000,18000,CONT_DIF_N,153nymous_ +V 0,19000,CONT_DIF_N,154nymous_ +V 0,3000,CONT_DIF_N,155nymous_ +V 1200,3000,CONT_DIF_N,156nymous_ +V 0,2000,CONT_DIF_N,157nymous_ +V 1200,2000,CONT_DIF_N,158nymous_ +V 0,15800,CONT_DIF_P,159nymous_ +V 1200,14800,CONT_DIF_P,160nymous_ +V 0,14800,CONT_DIF_P,161nymous_ +V 1200,15800,CONT_DIF_P,162nymous_ +V 0,7000,CONT_DIF_P,163nymous_ +V 1200,7000,CONT_DIF_P,164nymous_ +V 0,8000,CONT_DIF_P,165nymous_ +V 1200,8000,CONT_DIF_P,166nymous_ +V 3600,12000,CONT_DIF_P,189nymous_ +V 3600,7000,CONT_DIF_P,188nymous_ +V 3600,8000,CONT_DIF_P,187nymous_ +V 3600,3000,CONT_DIF_N,186nymous_ +V 3600,2000,CONT_DIF_N,185nymous_ +V 3600,8000,CONT_VIA,184nymous_ +V 3600,12000,CONT_VIA,183nymous_ +V 2400,7000,CONT_DIF_P,181nymous_ +V 2400,14800,CONT_DIF_P,180nymous_ +V 2400,8000,CONT_DIF_P,179nymous_ +V 2400,11000,CONT_DIF_P,178nymous_ +V 2400,9000,CONT_DIF_P,177nymous_ +V 2400,10000,CONT_DIF_P,176nymous_ +V 2400,2000,CONT_DIF_N,175nymous_ +V 2400,1000,CONT_DIF_N,174nymous_ +V 2400,3000,CONT_DIF_N,173nymous_ +V 0,12000,CONT_DIF_P,172nymous_ +V 0,9000,CONT_DIF_P,170nymous_ +V 0,10000,CONT_DIF_P,169nymous_ +V 0,11000,CONT_DIF_P,168nymous_ +V 1200,12000,CONT_DIF_P,167nymous_ +V 6000,3000,CONT_VIA2,190nymous_ +V 6000,12000,CONT_VIA2,191nymous_ +V 6000,8000,CONT_VIA2,192nymous_ +V 6000,3000,CONT_VIA,193nymous_ +V 6000,12000,CONT_VIA,194nymous_ +V 6000,8000,CONT_VIA,195nymous_ +V 5800,3000,CONT_DIF_N,196nymous_ +V 5800,2000,CONT_DIF_N,197nymous_ +V 7000,1000,CONT_DIF_N,198nymous_ +V 7000,3000,CONT_DIF_N,199nymous_ +V 7000,2000,CONT_DIF_N,200nymous_ +V 7000,7000,CONT_DIF_P,201nymous_ +V 7000,8000,CONT_DIF_P,202nymous_ +V 7000,9000,CONT_DIF_P,203nymous_ +V 7000,10000,CONT_DIF_P,204nymous_ +V 5800,12000,CONT_DIF_P,205nymous_ +V 5800,7000,CONT_DIF_P,206nymous_ +V 5800,8000,CONT_DIF_P,207nymous_ +V 7000,11000,CONT_DIF_P,208nymous_ +V 7000,12000,CONT_DIF_P,209nymous_ +V 7000,15800,CONT_DIF_P,211nymous_ +V 7000,14800,CONT_DIF_P,212nymous_ +V 7000,13400,CONT_BODY_N,213nymous_ +V 2400,15800,CONT_DIF_P,214nymous_ +V 3600,5600,CONT_BODY_N,215nymous_ +V 5800,5600,CONT_BODY_N,216nymous_ +V 1200,5600,CONT_BODY_N,217nymous_ +V 4000,3000,CONT_VIA2,218nymous_ +V 4000,8000,CONT_VIA2,219nymous_ +V 3600,3000,CONT_VIA,220nymous_ +V 4000,12000,CONT_VIA2,221nymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_mid_buf.vbe b/pdks/symbolic/nrf2lib/cells/rf2_mid_buf.vbe new file mode 100644 index 000000000..1c30fe827 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_mid_buf.vbe @@ -0,0 +1,26 @@ +ENTITY rf2_mid_buf IS +PORT ( + selra : in BIT; + selrb : in BIT; + selw : in BIT; + nck : in BIT; + reada : out BIT; + readb : out BIT; + write : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_mid_buf; + +ARCHITECTURE VBE OF rf2_mid_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_mid_buf" + SEVERITY WARNING; + + reada <= selra; + readb <= selrb; + write <= selw and nck; + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_mid_mem.ap b/pdks/symbolic/nrf2lib/cells/rf2_mid_mem.ap new file mode 100644 index 000000000..b70540a59 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_mid_mem.ap @@ -0,0 +1,109 @@ +V ALLIANCE : 6 +H rf2_mid_mem,P,24/4/2016,100 +A 0,0,7000,10000 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 850,6000,3150,6000,600,0nonymous_,RIGHT,ALU2 +S 1400,3300,1400,3700,1000,1nonymous_,UP,NTRANS +S 400,3300,400,3500,400,2nonymous_,UP,NDIF +S 2400,7200,4000,7200,200,13onymous_,RIGHT,POLY +S 900,1400,1500,1400,200,14onymous_,RIGHT,NTRANS +S 0,3300,0,5300,600,15onymous_,UP,NDIF +S 2000,1400,2000,2200,200,16onymous_,UP,POLY +S 1800,1400,2000,1400,200,17onymous_,RIGHT,POLY +S 0,600,0,4600,300,18onymous_,UP,ALU1 +S 1200,7100,1200,9300,200,3nonymous_,UP,PTRANS +S 1800,7300,1800,9100,600,4nonymous_,UP,PDIF +S 600,7300,600,9100,600,5nonymous_,UP,PDIF +S 2400,7500,2400,8100,200,6nonymous_,UP,PTRANS +S 4100,8400,4300,8400,1400,7nonymous_,RIGHT,PDIF +S 3400,8700,3400,9100,600,8nonymous_,UP,PTRANS +S 2100,9000,2700,9000,600,9nonymous_,RIGHT,PDIF +S 3200,9400,3200,9600,200,10onymous_,UP,POLY +S 1200,9600,3200,9600,200,11onymous_,RIGHT,POLY +S 1200,2000,1200,2800,300,12onymous_,UP,ALU1 +S 600,4500,600,5300,1600,23onymous_,UP,NDIF +S 0,4600,1000,4600,300,24onymous_,RIGHT,ALU1 +S 2400,4500,2400,5300,600,25onymous_,UP,NDIF +S 2400,2000,2400,3400,300,26onymous_,UP,ALU1 +S 3850,6000,5150,6000,600,27onymous_,RIGHT,ALU2 +S 4200,7000,4200,8000,300,28onymous_,UP,ALU1 +S 600,5600,600,8000,300,29onymous_,UP,ALU1 +S 600,5600,2000,5600,300,30onymous_,RIGHT,ALU1 +S 2000,5000,2000,5600,300,31onymous_,UP,ALU1 +S 3000,7000,3000,7800,300,32onymous_,UP,ALU1 +S 1800,5800,1800,6800,200,22onymous_,UP,POLY +S 1800,4300,1800,5500,200,21onymous_,UP,NTRANS +S 1200,6600,1800,6600,600,20onymous_,RIGHT,POLY +S 1000,4000,1800,4000,200,19onymous_,RIGHT,POLY +S 1600,7000,3000,7000,300,33onymous_,RIGHT,ALU1 +S 1600,6600,1600,7000,300,34onymous_,UP,ALU1 +S 1800,8000,1800,9000,300,35onymous_,UP,ALU1 +S 3000,2600,3000,6000,200,36onymous_,UP,POLY +S 4000,3200,4000,4000,300,37onymous_,UP,ALU1 +S 5800,6000,6400,6000,600,38onymous_,RIGHT,POLY +S 2000,5000,5800,5000,300,39onymous_,RIGHT,ALU1 +S 2400,3200,4000,3200,300,40onymous_,RIGHT,ALU1 +S 4000,4000,4000,7200,600,41onymous_,UP,POLY +S -600,8600,7600,8600,4400,42onymous_,RIGHT,NWELL +S 5800,4500,5800,5300,600,43onymous_,UP,NDIF +S 7000,4500,7000,5300,600,44onymous_,UP,NDIF +S 6400,4300,6400,5500,200,45onymous_,UP,NTRANS +S 5200,3400,6400,3400,200,46onymous_,RIGHT,POLY +S 6400,1900,6400,3100,200,47onymous_,UP,NTRANS +S 5200,3400,5200,6000,200,48onymous_,UP,POLY +S 5800,2100,5800,2900,600,49onymous_,UP,NDIF +S 5800,2600,5800,5000,300,50onymous_,UP,ALU1 +S 7000,2100,7000,2900,600,51onymous_,UP,NDIF +S 7000,2600,7000,3000,300,52onymous_,UP,ALU1 +S 3500,3200,4500,3200,600,53onymous_,RIGHT,NDIF +S 3500,2000,4500,2000,600,54onymous_,RIGHT,NDIF +S 3300,2600,4700,2600,200,55onymous_,RIGHT,NTRANS +S 5800,7800,5800,9000,300,56onymous_,UP,ALU1 +S 3850,2000,4550,2000,600,dinx,RIGHT,CALU2 +S 1000,5850,1000,6150,400,write,UP,CALU3 +S 4000,5850,4000,6150,400,reada,UP,CALU3 +S 6000,5850,6000,6150,400,readb,UP,CALU3 +S 6850,3000,7150,3000,600,busa,RIGHT,CALU2 +S 6850,5000,7150,5000,600,busb,RIGHT,CALU2 +V 1000,4600,CONT_DIF_N,72onymous_ +V 1600,6600,CONT_POLY,71onymous_ +V 0,4600,CONT_DIF_N,70onymous_ +V 1200,800,CONT_DIF_N,69onymous_ +V 2400,5000,CONT_DIF_N,73onymous_ +V 4200,7000,CONT_POLY,74onymous_ +V 2400,3400,CONT_DIF_N,75onymous_ +V 5000,6000,CONT_VIA,76onymous_ +V 4000,6000,CONT_VIA2,77onymous_ +V 5000,6000,CONT_POLY,78onymous_ +V 4000,4000,CONT_POLY,79onymous_ +V 1800,8000,CONT_DIF_P,80onymous_ +V 4000,2000,CONT_VIA,81onymous_ +V 4000,2000,CONT_DIF_N,82onymous_ +V 2400,600,CONT_BODY_P,57onymous_ +V 1000,6000,CONT_VIA2,58onymous_ +V 3000,6000,CONT_VIA,59onymous_ +V 0,3400,CONT_DIF_N,60onymous_ +V 600,8000,CONT_DIF_P,61onymous_ +V 1800,9000,CONT_DIF_P,62onymous_ +V 3000,7800,CONT_DIF_P,63onymous_ +V 4200,8000,CONT_DIF_P,64onymous_ +V 1200,2800,CONT_POLY,65onymous_ +V 1200,2000,CONT_DIF_N,66onymous_ +V 3000,6000,CONT_POLY,67onymous_ +V 2200,2000,CONT_POLY,68onymous_ +V 4000,3200,CONT_DIF_N,83onymous_ +V 6000,6000,CONT_VIA2,84onymous_ +V 6000,6000,CONT_VIA,85onymous_ +V 6000,6000,CONT_POLY,86onymous_ +V 7000,5000,CONT_VIA,87onymous_ +V 7000,5000,CONT_DIF_N,88onymous_ +V 5800,5000,CONT_DIF_N,89onymous_ +V 7000,3000,CONT_VIA,90onymous_ +V 4400,600,CONT_BODY_P,91onymous_ +V 5800,2600,CONT_DIF_N,92onymous_ +V 7000,2600,CONT_DIF_N,93onymous_ +V 6200,600,CONT_BODY_P,94onymous_ +V 5800,7700,CONT_BODY_N,95onymous_ +V 5800,9000,CONT_BODY_N,96onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_mid_mem.vbe b/pdks/symbolic/nrf2lib/cells/rf2_mid_mem.vbe new file mode 100644 index 000000000..b0a4c1a31 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_mid_mem.vbe @@ -0,0 +1,37 @@ +ENTITY rf2_mid_mem IS +PORT ( + dinx : in BIT; + write : in BIT; + reada : in BIT; + readb : in BIT; + busa : out MUX_BIT BUS; + busb : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rf2_mid_mem; + +ARCHITECTURE VBE OF rf2_mid_mem IS + SIGNAL latch : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_mid_mem" + SEVERITY WARNING; + + label0 : BLOCK (write = '1') + BEGIN + latch <= GUARDED dinx; + END BLOCK label0; + + label1 : BLOCK (reada = '1') + BEGIN + busa <= GUARDED latch; + END BLOCK label1; + + label2 : BLOCK (readb = '1') + BEGIN + busb <= GUARDED latch; + END BLOCK label2; + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_mid_mem_r0.ap b/pdks/symbolic/nrf2lib/cells/rf2_mid_mem_r0.ap new file mode 100644 index 000000000..bedc62f26 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_mid_mem_r0.ap @@ -0,0 +1,43 @@ +V ALLIANCE : 6 +H rf2_mid_mem_r0,P,24/4/2016,100 +A 0,0,7000,10000 +S 3850,2000,4550,2000,600,dinx,RIGHT,CALU2 +S 1000,5850,1000,6150,400,write,UP,CALU3 +S 4000,5850,4000,6150,400,reada,UP,CALU3 +S 6000,5850,6000,6150,400,readb,UP,CALU3 +S 5800,7800,5800,9000,300,12onymous_,UP,ALU1 +S 7000,2600,7000,3000,300,11onymous_,UP,ALU1 +S 7000,2100,7000,2900,600,10onymous_,UP,NDIF +S 5800,2100,5800,2900,600,9nonymous_,UP,NDIF +S 5200,3400,5200,6000,200,8nonymous_,UP,POLY +S 6400,1900,6400,3100,200,7nonymous_,UP,NTRANS +S -600,8600,7600,8600,4400,2nonymous_,RIGHT,NWELL +S 5800,600,5800,5000,300,13onymous_,UP,ALU1 +S 5800,6000,6400,6000,600,1nonymous_,RIGHT,POLY +S 3850,6000,5150,6000,600,0nonymous_,RIGHT,ALU2 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 6850,5000,7150,5000,600,busb,RIGHT,CALU2 +S 6850,3000,7150,3000,600,busa,RIGHT,CALU2 +S 5800,4500,5800,5300,600,3nonymous_,UP,NDIF +S 7000,4500,7000,5300,600,4nonymous_,UP,NDIF +S 6400,4300,6400,5500,200,5nonymous_,UP,NTRANS +S 5200,3400,6400,3400,200,6nonymous_,RIGHT,POLY +V 2400,600,CONT_BODY_P,14onymous_ +V 5000,6000,CONT_VIA,15onymous_ +V 4000,6000,CONT_VIA2,16onymous_ +V 5000,6000,CONT_POLY,17onymous_ +V 6000,6000,CONT_VIA2,18onymous_ +V 6000,6000,CONT_VIA,19onymous_ +V 6000,6000,CONT_POLY,20onymous_ +V 7000,5000,CONT_VIA,21onymous_ +V 7000,5000,CONT_DIF_N,22onymous_ +V 5800,5000,CONT_DIF_N,23onymous_ +V 7000,3000,CONT_VIA,24onymous_ +V 4400,600,CONT_BODY_P,25onymous_ +V 5800,2600,CONT_DIF_N,26onymous_ +V 7000,2600,CONT_DIF_N,27onymous_ +V 6200,600,CONT_BODY_P,28onymous_ +V 5800,7700,CONT_BODY_N,29onymous_ +V 5800,9000,CONT_BODY_N,30onymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_mid_mem_r0.vbe b/pdks/symbolic/nrf2lib/cells/rf2_mid_mem_r0.vbe new file mode 100644 index 000000000..3927ae12c --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_mid_mem_r0.vbe @@ -0,0 +1,32 @@ +ENTITY rf2_mid_mem_r0 IS +PORT ( + dinx : in BIT; + write : in BIT; + reada : in BIT; + readb : in BIT; + busa : out MUX_BIT BUS; + busb : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rf2_mid_mem_r0; + +ARCHITECTURE VBE OF rf2_mid_mem_r0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_mid_mem_r0" + SEVERITY WARNING; + + label1 : BLOCK (reada = '1') + BEGIN + busa <= GUARDED '0'; + END BLOCK label1; + + label2 : BLOCK (readb = '1') + BEGIN + busb <= GUARDED '0'; + END BLOCK label2; + + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_out_buf.ap b/pdks/symbolic/nrf2lib/cells/rf2_out_buf.ap new file mode 100644 index 000000000..105099c6e --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_out_buf.ap @@ -0,0 +1,172 @@ +V ALLIANCE : 6 +H rf2_out_buf,P,24/4/2016,100 +A 0,0,21000,20000 +S 1800,6700,1800,12300,600,18onymous_,UP,PDIF +S 3000,6700,3000,12300,600,17onymous_,UP,PDIF +S 2400,6500,2400,12500,200,16onymous_,UP,PTRANS +S 1800,800,1800,3000,300,5nonymous_,UP,ALU1 +S 3000,2000,3000,8000,300,4nonymous_,UP,ALU1 +S 1800,5600,1800,13400,300,3nonymous_,UP,ALU1 +S 4200,5600,4200,13400,300,2nonymous_,UP,ALU1 +S 3000,13000,3000,18000,300,1nonymous_,UP,ALU1 +S 5800,600,5800,3000,300,0nonymous_,UP,ALU1 +S 0,600,21000,600,1200,vss,RIGHT,CALU1 +S 0,19400,21000,19400,1200,vss,RIGHT,CALU1 +S 2400,500,2400,3700,200,15onymous_,UP,NTRANS +S 3600,500,3600,3700,200,14onymous_,UP,NTRANS +S 1800,700,1800,3500,600,13onymous_,UP,NDIF +S 3000,700,3000,3500,600,12onymous_,UP,NDIF +S 4200,700,4200,3500,600,11onymous_,UP,NDIF +S 2400,4000,2400,6200,200,10onymous_,UP,POLY +S 3600,4000,3600,6200,200,9nonymous_,UP,POLY +S 2400,13000,3600,13000,600,8nonymous_,RIGHT,POLY +S 2400,4200,3600,4200,600,7nonymous_,RIGHT,POLY +S 4200,800,4200,3000,300,6nonymous_,UP,ALU1 +S 0,9400,21000,9400,1200,vdd,RIGHT,CALU1 +S 0,10600,21000,10600,1200,vdd,RIGHT,CALU1 +S 13600,16900,13600,19300,600,35onymous_,UP,NDIF +S 12400,16900,12400,19300,600,34onymous_,UP,NDIF +S 14800,17000,14800,19000,300,33onymous_,UP,ALU1 +S 17200,17000,17200,19200,300,32onymous_,UP,ALU1 +S 16000,12000,16000,18000,300,31onymous_,UP,ALU1 +S 17200,9000,17200,14000,300,30onymous_,UP,ALU1 +S 12400,9000,12400,14000,300,29onymous_,UP,ALU1 +S 14800,9000,14800,14000,300,28onymous_,UP,ALU1 +S 13600,12000,13600,18000,300,27onymous_,UP,ALU1 +S 12400,17000,12400,19000,300,26onymous_,UP,ALU1 +S -600,12200,21600,12200,6000,25onymous_,RIGHT,NWELL +S 3600,6500,3600,12500,200,24onymous_,UP,PTRANS +S -600,7800,21600,7800,6000,23onymous_,RIGHT,NWELL +S 2050,12000,3950,12000,300,22onymous_,RIGHT,TALU2 +S 2050,8000,3950,8000,300,21onymous_,RIGHT,TALU2 +S 2050,3000,3950,3000,300,20onymous_,RIGHT,TALU2 +S 4200,6700,4200,12300,600,19onymous_,UP,PDIF +S 14800,16900,14800,19300,600,36onymous_,UP,NDIF +S 16000,16900,16000,19300,600,37onymous_,UP,NDIF +S 17200,16900,17200,19300,600,38onymous_,UP,NDIF +S 14200,16700,14200,19500,200,39onymous_,UP,NTRANS +S 13000,16700,13000,19500,200,40onymous_,UP,NTRANS +S 16600,16700,16600,19500,200,41onymous_,UP,NTRANS +S 15400,16700,15400,19500,200,42onymous_,UP,NTRANS +S 16600,8300,16600,14300,200,43onymous_,UP,PTRANS +S 16000,8500,16000,14100,600,44onymous_,UP,PDIF +S 14800,8500,14800,14100,600,45onymous_,UP,PDIF +S 13600,8500,13600,14100,600,46onymous_,UP,PDIF +S 12400,8500,12400,14100,600,47onymous_,UP,PDIF +S 13000,8300,13000,14300,200,48onymous_,UP,PTRANS +S 14200,8300,14200,14300,200,49onymous_,UP,PTRANS +S 15400,8300,15400,14300,200,50onymous_,UP,PTRANS +S 17200,8500,17200,14100,600,51onymous_,UP,PDIF +S 13000,14600,13000,16400,200,52onymous_,UP,POLY +S 14200,14600,14200,16400,200,53onymous_,UP,POLY +S 15400,14600,15400,16400,200,54onymous_,UP,POLY +S 16600,14600,16600,16400,200,55onymous_,UP,POLY +S -600,7800,9600,7800,6400,62onymous_,RIGHT,NWELL +S -600,13000,9600,13000,7600,61onymous_,RIGHT,NWELL +S 18600,7400,18600,14000,300,60onymous_,UP,ALU1 +S 11000,7600,11000,14000,300,59onymous_,UP,ALU1 +S 18600,16600,18600,19400,300,58onymous_,UP,ALU1 +S 11000,16600,11000,19400,300,57onymous_,UP,ALU1 +S 13000,15000,20000,15000,600,56onymous_,RIGHT,POLY +S 2850,18000,3150,18000,600,nck,RIGHT,CALU2 +S 2850,18000,16150,18000,600,nck,RIGHT,CALU2 +S 3000,2850,3000,12150,400,xcks,UP,CALU3 +S 20000,12000,20000,18000,300,ck,UP,CALU1 +V 1800,8000,CONT_DIF_P,78onymous_ +V 1800,7000,CONT_DIF_P,77onymous_ +V 1800,800,CONT_DIF_N,76onymous_ +V 1800,3000,CONT_DIF_N,75onymous_ +V 3000,2000,CONT_DIF_N,74onymous_ +V 3000,3000,CONT_DIF_N,73onymous_ +V 4200,2000,CONT_DIF_N,72onymous_ +V 4200,800,CONT_DIF_N,71onymous_ +V 4200,3000,CONT_DIF_N,70onymous_ +V 1800,2000,CONT_DIF_N,69onymous_ +V 5600,19400,CONT_BODY_P,68onymous_ +V 4400,19400,CONT_BODY_P,67onymous_ +V 3000,18000,CONT_VIA,66onymous_ +V 5800,1800,CONT_BODY_P,65onymous_ +V 5800,3000,CONT_BODY_P,64onymous_ +V 5800,600,CONT_BODY_P,63onymous_ +V 1800,9000,CONT_DIF_P,79onymous_ +V 1800,10000,CONT_DIF_P,80onymous_ +V 1800,11000,CONT_DIF_P,81onymous_ +V 1800,12000,CONT_DIF_P,82onymous_ +V 1800,13400,CONT_BODY_N,83onymous_ +V 4200,13400,CONT_BODY_N,84onymous_ +V 4200,5600,CONT_BODY_N,85onymous_ +V 4200,7000,CONT_DIF_P,86onymous_ +V 4200,9000,CONT_DIF_P,87onymous_ +V 1800,5600,CONT_BODY_N,88onymous_ +V 3000,12000,CONT_DIF_P,89onymous_ +V 3000,8000,CONT_DIF_P,90onymous_ +V 3000,7000,CONT_DIF_P,91onymous_ +V 4200,11000,CONT_DIF_P,92onymous_ +V 4200,8000,CONT_DIF_P,93onymous_ +V 4200,12000,CONT_DIF_P,94onymous_ +V 3000,12000,CONT_VIA2,95onymous_ +V 3000,12000,CONT_VIA,96onymous_ +V 3000,8000,CONT_VIA2,97onymous_ +V 3000,8000,CONT_VIA,98onymous_ +V 3000,3000,CONT_VIA2,99onymous_ +V 3000,3000,CONT_VIA,100nymous_ +V 5800,9300,CONT_BODY_N,101nymous_ +V 5800,10600,CONT_BODY_N,102nymous_ +V 3000,13000,CONT_POLY,103nymous_ +V 16000,18000,CONT_VIA,104nymous_ +V 13600,18000,CONT_VIA,105nymous_ +V 12400,19000,CONT_DIF_N,106nymous_ +V 14800,19000,CONT_DIF_N,107nymous_ +V 14800,18000,CONT_DIF_N,108nymous_ +V 14800,17000,CONT_DIF_N,109nymous_ +V 13600,17000,CONT_DIF_N,110nymous_ +V 13600,18000,CONT_DIF_N,111nymous_ +V 17200,19200,CONT_DIF_N,112nymous_ +V 17200,18000,CONT_DIF_N,113nymous_ +V 17200,17000,CONT_DIF_N,114nymous_ +V 16000,17000,CONT_DIF_N,115nymous_ +V 16000,18000,CONT_DIF_N,116nymous_ +V 12400,17000,CONT_DIF_N,117nymous_ +V 12400,18000,CONT_DIF_N,118nymous_ +V 13600,13000,CONT_DIF_P,119nymous_ +V 13600,12000,CONT_DIF_P,120nymous_ +V 12400,9000,CONT_DIF_P,121nymous_ +V 12400,10000,CONT_DIF_P,122nymous_ +V 12400,11000,CONT_DIF_P,123nymous_ +V 12400,14000,CONT_DIF_P,124nymous_ +V 12400,13000,CONT_DIF_P,125nymous_ +V 12400,12000,CONT_DIF_P,126nymous_ +V 16000,14000,CONT_DIF_P,127nymous_ +V 13600,14000,CONT_DIF_P,128nymous_ +V 14800,14000,CONT_DIF_P,129nymous_ +V 14800,13000,CONT_DIF_P,130nymous_ +V 14800,12000,CONT_DIF_P,131nymous_ +V 14800,11000,CONT_DIF_P,132nymous_ +V 14800,10000,CONT_DIF_P,133nymous_ +V 14800,9000,CONT_DIF_P,134nymous_ +V 17200,9000,CONT_DIF_P,135nymous_ +V 11000,16600,CONT_BODY_P,155nymous_ +V 11000,18000,CONT_BODY_P,154nymous_ +V 20000,15000,CONT_POLY,159nymous_ +V 18600,16600,CONT_BODY_P,158nymous_ +V 18600,18000,CONT_BODY_P,157nymous_ +V 18600,19400,CONT_BODY_P,156nymous_ +V 17200,10000,CONT_DIF_P,136nymous_ +V 17200,11000,CONT_DIF_P,137nymous_ +V 17200,14000,CONT_DIF_P,138nymous_ +V 17200,13000,CONT_DIF_P,139nymous_ +V 17200,12000,CONT_DIF_P,140nymous_ +V 16000,12000,CONT_DIF_P,141nymous_ +V 16000,13000,CONT_DIF_P,142nymous_ +V 18600,14000,CONT_BODY_N,143nymous_ +V 18600,12600,CONT_BODY_N,144nymous_ +V 18600,10800,CONT_BODY_N,145nymous_ +V 18600,9200,CONT_BODY_N,146nymous_ +V 18600,7400,CONT_BODY_N,147nymous_ +V 11000,14000,CONT_BODY_N,148nymous_ +V 11000,12600,CONT_BODY_N,149nymous_ +V 11000,10800,CONT_BODY_N,150nymous_ +V 11000,9200,CONT_BODY_N,151nymous_ +V 11000,7600,CONT_BODY_N,152nymous_ +V 11000,19400,CONT_BODY_P,153nymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_out_buf.vbe b/pdks/symbolic/nrf2lib/cells/rf2_out_buf.vbe new file mode 100644 index 000000000..e7a4c7337 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_out_buf.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_out_buf IS +PORT ( + ck : in BIT; + nck : inout BIT; + xcks : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_out_buf; + +ARCHITECTURE VBE OF rf2_out_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_out_buf" + SEVERITY WARNING; + + nck <= not ck; + xcks <= not nck; + +END; diff --git a/pdks/symbolic/nrf2lib/cells/rf2_out_mem.ap b/pdks/symbolic/nrf2lib/cells/rf2_out_mem.ap new file mode 100644 index 000000000..48cd3313f --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_out_mem.ap @@ -0,0 +1,245 @@ +V ALLIANCE : 6 +H rf2_out_mem,P,24/4/2016,100 +A 0,0,21000,10000 +S 1600,7000,2000,7000,300,18onymous_,RIGHT,ALU1 +S 2000,3000,2000,7000,300,17onymous_,UP,ALU1 +S 1800,7000,1800,8000,300,16onymous_,UP,ALU1 +S 5400,3000,5600,3000,300,15onymous_,RIGHT,ALU1 +S 5600,3000,5600,7000,300,14onymous_,UP,ALU1 +S 18600,1500,18600,3500,200,3nonymous_,UP,NTRANS +S 19200,1700,19200,3300,600,2nonymous_,UP,NDIF +S 16400,5000,17000,5000,300,1nonymous_,RIGHT,ALU1 +S 19000,7000,19400,7000,300,0nonymous_,RIGHT,ALU1 +S 0,600,21000,600,1200,vss,RIGHT,CALU1 +S 5400,7000,5600,7000,300,13onymous_,RIGHT,ALU1 +S 5400,7000,5400,7200,300,12onymous_,UP,ALU1 +S -600,8600,21600,8600,4400,11onymous_,RIGHT,NWELL +S 1600,7800,21600,7800,6000,10onymous_,RIGHT,NWELL +S 19000,2000,19000,8000,300,9nonymous_,UP,ALU1 +S 18600,3800,20000,3800,200,8nonymous_,RIGHT,POLY +S 20400,6000,20400,7400,300,7nonymous_,UP,ALU1 +S 20000,3000,20000,6000,300,6nonymous_,UP,ALU1 +S 18600,6200,20000,6200,200,5nonymous_,RIGHT,POLY +S 20000,6000,20400,6000,300,4nonymous_,RIGHT,ALU1 +S 0,9400,21000,9400,1200,vdd,RIGHT,CALU1 +S 16800,7000,16800,8000,300,78onymous_,UP,ALU1 +S 16800,7000,18000,7000,300,77onymous_,RIGHT,ALU1 +S 15400,3000,15600,3000,300,76onymous_,RIGHT,ALU1 +S 3000,6300,3000,9300,600,75onymous_,UP,PDIF +S 4200,6300,4200,8300,600,74onymous_,UP,PDIF +S 3000,700,3000,3700,600,33onymous_,UP,NDIF +S 6000,1600,6600,1600,800,32onymous_,RIGHT,POLY +S 3000,8000,3000,9000,300,31onymous_,UP,ALU1 +S 3000,1000,3000,2000,300,30onymous_,UP,ALU1 +S 4200,7000,4200,8000,300,29onymous_,UP,ALU1 +S 3000,7000,4200,7000,300,28onymous_,RIGHT,ALU1 +S 3000,3000,3000,7000,300,27onymous_,UP,ALU1 +S 3000,3000,4200,3000,300,26onymous_,RIGHT,ALU1 +S 2000,5200,3600,5200,200,25onymous_,RIGHT,POLY +S 1000,4000,1000,6000,300,24onymous_,UP,ALU1 +S 1000,4200,2400,4200,200,23onymous_,RIGHT,POLY +S 2400,1900,2400,3900,200,22onymous_,UP,NTRANS +S 1800,2100,1800,3700,600,21onymous_,UP,NDIF +S 1000,6200,2400,6200,200,20onymous_,RIGHT,POLY +S 2400,6200,2400,7200,200,19onymous_,UP,POLY +S 4800,4200,4800,5000,200,34onymous_,UP,POLY +S 6600,2000,6600,8000,300,35onymous_,UP,ALU1 +S 3600,2700,3600,3900,200,36onymous_,UP,NTRANS +S 4200,3100,4200,3700,600,37onymous_,UP,NDIF +S 5400,2500,5400,3700,600,38onymous_,UP,NDIF +S 4800,2700,4800,3900,200,39onymous_,UP,NTRANS +S 5300,1600,5700,1600,800,40onymous_,RIGHT,NTRANS +S 600,6000,600,7400,300,41onymous_,UP,ALU1 +S 600,6000,1000,6000,300,42onymous_,RIGHT,ALU1 +S 5300,8000,5700,8000,600,43onymous_,RIGHT,PTRANS +S 6000,8000,6600,8000,600,44onymous_,RIGHT,POLY +S 7800,900,7800,3700,600,45onymous_,UP,NDIF +S 6600,2700,6600,3700,600,46onymous_,UP,NDIF +S 7200,2500,7200,3900,200,47onymous_,UP,NTRANS +S 7200,4200,7200,5800,200,48onymous_,UP,POLY +S 5400,4600,7200,4600,200,49onymous_,RIGHT,POLY +S 6600,6300,6600,7300,600,50onymous_,UP,PDIF +S 7200,6100,7200,7500,200,51onymous_,UP,PTRANS +S 7800,5000,9600,5000,600,52onymous_,RIGHT,POLY +S 6600,5000,8000,5000,300,53onymous_,RIGHT,ALU1 +S 3600,6100,3600,8500,200,73onymous_,UP,PTRANS +S 3600,4200,3600,5800,200,72onymous_,UP,POLY +S 7800,6000,7800,9000,300,71onymous_,UP,ALU1 +S 7800,1000,7800,3000,300,70onymous_,UP,ALU1 +S 8400,3800,8400,5200,200,69onymous_,UP,POLY +S 9600,3800,9600,5200,200,68onymous_,UP,POLY +S 10200,5700,10200,9300,600,67onymous_,UP,PDIF +S 500,8200,900,8200,600,66onymous_,RIGHT,PTRANS +S 9000,5700,9000,9300,600,65onymous_,UP,PDIF +S 8400,5500,8400,9500,200,64onymous_,UP,PTRANS +S 1800,7700,1800,9300,600,63onymous_,UP,PDIF +S 7800,5700,7800,9300,600,62onymous_,UP,PDIF +S 2400,7500,2400,9500,200,61onymous_,UP,PTRANS +S 9600,5500,9600,9500,200,60onymous_,UP,PTRANS +S 9600,1500,9600,3500,200,59onymous_,UP,NTRANS +S 10200,900,10200,3300,600,58onymous_,UP,NDIF +S 8400,1500,8400,3500,200,57onymous_,UP,NTRANS +S 9000,1700,9000,3300,600,56onymous_,UP,NDIF +S 1200,6800,1200,8400,200,55onymous_,UP,POLY +S 1200,7000,1800,7000,600,54onymous_,RIGHT,POLY +S 18000,1000,18000,2000,300,79onymous_,UP,ALU1 +S 18000,8000,18000,9000,300,80onymous_,UP,ALU1 +S 14400,2000,14400,8000,300,81onymous_,UP,ALU1 +S 15600,7000,15600,7200,300,82onymous_,UP,ALU1 +S 15400,7000,15600,7000,300,83onymous_,RIGHT,ALU1 +S 15400,3000,15400,7000,300,84onymous_,UP,ALU1 +S 13000,5000,14400,5000,300,85onymous_,RIGHT,ALU1 +S 13200,1000,13200,3000,300,86onymous_,UP,ALU1 +S 13200,6000,13200,9000,300,87onymous_,UP,ALU1 +S 16800,3000,18000,3000,300,88onymous_,RIGHT,ALU1 +S 18000,3000,18000,7000,300,89onymous_,UP,ALU1 +S 18600,6200,18600,7200,200,90onymous_,UP,POLY +S 14400,8000,15000,8000,600,91onymous_,RIGHT,POLY +S 13800,4200,13800,5800,200,92onymous_,UP,POLY +S 13800,4600,15600,4600,200,93onymous_,RIGHT,POLY +S 11400,5000,13200,5000,600,94onymous_,RIGHT,POLY +S 19200,7000,19800,7000,600,95onymous_,RIGHT,POLY +S 17400,5200,19000,5200,200,96onymous_,RIGHT,POLY +S 14400,1600,15000,1600,800,97onymous_,RIGHT,POLY +S 16200,4200,16200,5000,200,98onymous_,UP,POLY +S 12600,3800,12600,5200,200,99onymous_,UP,POLY +S 17400,4200,17400,5800,200,100nymous_,UP,POLY +S 19800,6800,19800,8400,200,101nymous_,UP,POLY +S 11400,3800,11400,5200,200,102nymous_,UP,POLY +S 11400,5500,11400,9500,200,103nymous_,UP,PTRANS +S 15600,2500,15600,3700,600,104nymous_,UP,NDIF +S 13200,900,13200,3700,600,105nymous_,UP,NDIF +S 14400,2700,14400,3700,600,106nymous_,UP,NDIF +S 12000,1700,12000,3300,600,107nymous_,UP,NDIF +S 18000,700,18000,3700,600,108nymous_,UP,NDIF +S 16800,3100,16800,3700,600,109nymous_,UP,NDIF +S 17400,2700,17400,3900,200,110nymous_,UP,NTRANS +S 16200,2700,16200,3900,200,111nymous_,UP,NTRANS +S 15300,1600,15700,1600,800,112nymous_,RIGHT,NTRANS +S 13800,2500,13800,3900,200,113nymous_,UP,NTRANS +S 12600,1500,12600,3500,200,114nymous_,UP,NTRANS +S 11400,1500,11400,3500,200,115nymous_,UP,NTRANS +S 19200,7700,19200,9300,600,116nymous_,UP,PDIF +S 15300,8000,15700,8000,600,117nymous_,RIGHT,PTRANS +S 17400,6100,17400,8500,200,118nymous_,UP,PTRANS +S 16800,6300,16800,8300,600,119nymous_,UP,PDIF +S 18000,6300,18000,9300,600,120nymous_,UP,PDIF +S 14400,6300,14400,7300,600,121nymous_,UP,PDIF +S 13800,6100,13800,7500,200,122nymous_,UP,PTRANS +S 18600,7500,18600,9500,200,123nymous_,UP,PTRANS +S 13200,5700,13200,9300,600,124nymous_,UP,PDIF +S 12600,5500,12600,9500,200,125nymous_,UP,PTRANS +S 12000,5700,12000,9300,600,126nymous_,UP,PDIF +S 20100,8200,20500,8200,600,127nymous_,RIGHT,PTRANS +S 3050,5000,16950,5000,300,128nymous_,RIGHT,TALU2 +S 2850,5000,17150,5000,600,129nymous_,RIGHT,ALU2 +S 10400,1000,10400,3000,300,130nymous_,UP,ALU1 +S 10400,6000,10400,9000,300,131nymous_,UP,ALU1 +S 10600,900,10600,3300,800,132nymous_,UP,NDIF +S 10600,5700,10600,9300,800,133nymous_,UP,PDIF +S 9000,2000,9000,8000,300,dataoutb,UP,CALU1 +S 12000,2000,12000,8000,300,dataouta,UP,CALU1 +S 3000,4850,3000,5150,400,xcks,UP,CALU3 +S 850,5000,1150,5000,600,busb,RIGHT,CALU2 +S 19850,3000,20150,3000,600,busa,RIGHT,CALU2 +V 20200,600,CONT_BODY_P,134nymous_ +V 20000,6000,CONT_POLY,135nymous_ +V 1000,6000,CONT_POLY,153nymous_ +V 5400,600,CONT_DIF_N,152nymous_ +V 5400,3000,CONT_DIF_N,151nymous_ +V 5600,4600,CONT_POLY,150nymous_ +V 4200,3000,CONT_DIF_N,149nymous_ +V 6400,2000,CONT_POLY,148nymous_ +V 3000,5000,CONT_VIA2,147nymous_ +V 4600,5000,CONT_POLY,146nymous_ +V 4600,5000,CONT_VIA,145nymous_ +V 4200,600,CONT_BODY_P,144nymous_ +V 3000,2000,CONT_DIF_N,143nymous_ +V 3000,1000,CONT_DIF_N,142nymous_ +V 1000,4000,CONT_POLY,141nymous_ +V 1800,3000,CONT_DIF_N,140nymous_ +V 1800,600,CONT_BODY_P,139nymous_ +V 2000,5200,CONT_POLY,138nymous_ +V 19200,2000,CONT_DIF_N,137nymous_ +V 20000,4000,CONT_POLY,136nymous_ +V 1000,5000,CONT_VIA,154nymous_ +V 6400,8000,CONT_POLY,155nymous_ +V 5400,7200,CONT_DIF_P,156nymous_ +V 8000,5000,CONT_POLY,157nymous_ +V 6600,9300,CONT_BODY_N,158nymous_ +V 5400,8900,CONT_DIF_P,159nymous_ +V 1600,7000,CONT_POLY,160nymous_ +V 7800,1000,CONT_DIF_N,161nymous_ +V 9000,3000,CONT_DIF_N,162nymous_ +V 9000,2000,CONT_DIF_N,163nymous_ +V 7800,2000,CONT_DIF_N,164nymous_ +V 6600,3000,CONT_DIF_N,165nymous_ +V 7800,3000,CONT_DIF_N,166nymous_ +V 13000,5000,CONT_POLY,189nymous_ +V 14600,8000,CONT_POLY,188nymous_ +V 15400,4600,CONT_POLY,187nymous_ +V 14600,2000,CONT_POLY,186nymous_ +V 16400,5000,CONT_POLY,185nymous_ +V 6600,600,CONT_BODY_P,184nymous_ +V 9000,600,CONT_BODY_P,183nymous_ +V 4200,9300,CONT_BODY_N,182nymous_ +V 7800,6000,CONT_DIF_P,181nymous_ +V 4200,8000,CONT_DIF_P,180nymous_ +V 7800,7000,CONT_DIF_P,179nymous_ +V 7800,8000,CONT_DIF_P,178nymous_ +V 600,7400,CONT_DIF_P,177nymous_ +V 3000,9000,CONT_DIF_P,176nymous_ +V 7800,9000,CONT_DIF_P,175nymous_ +V 9000,8000,CONT_DIF_P,174nymous_ +V 600,9000,CONT_DIF_P,173nymous_ +V 1800,8000,CONT_DIF_P,172nymous_ +V 4200,7000,CONT_DIF_P,171nymous_ +V 6600,7000,CONT_DIF_P,170nymous_ +V 9000,6000,CONT_DIF_P,169nymous_ +V 9000,7000,CONT_DIF_P,168nymous_ +V 3000,8000,CONT_DIF_P,167nymous_ +V 19400,7000,CONT_POLY,190nymous_ +V 19000,5200,CONT_POLY,191nymous_ +V 16800,600,CONT_BODY_P,192nymous_ +V 12000,600,CONT_BODY_P,193nymous_ +V 14400,600,CONT_BODY_P,194nymous_ +V 14400,3000,CONT_DIF_N,195nymous_ +V 18000,1000,CONT_DIF_N,196nymous_ +V 18000,2000,CONT_DIF_N,197nymous_ +V 16800,3000,CONT_DIF_N,198nymous_ +V 15600,3000,CONT_DIF_N,199nymous_ +V 13200,3000,CONT_DIF_N,200nymous_ +V 15600,600,CONT_DIF_N,201nymous_ +V 13200,1000,CONT_DIF_N,202nymous_ +V 12000,3000,CONT_DIF_N,203nymous_ +V 12000,2000,CONT_DIF_N,204nymous_ +V 13200,2000,CONT_DIF_N,205nymous_ +V 14400,7000,CONT_DIF_P,206nymous_ +V 16800,7000,CONT_DIF_P,207nymous_ +V 19200,8000,CONT_DIF_P,208nymous_ +V 15600,7200,CONT_DIF_P,209nymous_ +V 18000,9000,CONT_DIF_P,210nymous_ +V 20400,7400,CONT_DIF_P,211nymous_ +V 13200,8000,CONT_DIF_P,212nymous_ +V 14400,9300,CONT_BODY_N,213nymous_ +V 15600,8900,CONT_DIF_P,214nymous_ +V 18000,8000,CONT_DIF_P,215nymous_ +V 12000,7000,CONT_DIF_P,216nymous_ +V 12000,6000,CONT_DIF_P,217nymous_ +V 13200,7000,CONT_DIF_P,218nymous_ +V 16800,8000,CONT_DIF_P,219nymous_ +V 13200,6000,CONT_DIF_P,220nymous_ +V 16800,9300,CONT_BODY_N,221nymous_ +V 20400,9000,CONT_DIF_P,222nymous_ +V 12000,8000,CONT_DIF_P,223nymous_ +V 13200,9000,CONT_DIF_P,224nymous_ +V 17000,5000,CONT_VIA,225nymous_ +V 10400,7000,CONT_DIF_P,226nymous_ +V 10400,9000,CONT_DIF_P,227nymous_ +V 10400,6000,CONT_DIF_P,228nymous_ +V 10400,8000,CONT_DIF_P,229nymous_ +V 10400,1000,CONT_DIF_N,230nymous_ +V 10400,3000,CONT_DIF_N,231nymous_ +V 10400,2000,CONT_DIF_N,232nymous_ +V 20000,3000,CONT_VIA,233nymous_ +EOF diff --git a/pdks/symbolic/nrf2lib/cells/rf2_out_mem.vbe b/pdks/symbolic/nrf2lib/cells/rf2_out_mem.vbe new file mode 100644 index 000000000..3adf4bcc0 --- /dev/null +++ b/pdks/symbolic/nrf2lib/cells/rf2_out_mem.vbe @@ -0,0 +1,31 @@ +ENTITY rf2_out_mem IS +PORT ( + busa : in BIT; + busb : in BIT; + xcks : in BIT; + dataouta : out BIT; + dataoutb : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_out_mem; + +ARCHITECTURE VBE OF rf2_out_mem IS + SIGNAL latcha : REG_BIT REGISTER; + SIGNAL latchb : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_out_mem" + SEVERITY WARNING; + + label0 : BLOCK (xcks = '1') + BEGIN + latcha <= GUARDED busa; + latchb <= GUARDED busb; + END BLOCK label0; + + dataouta <= latcha; + dataoutb <= latchb; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_dec_bufad0.ap b/pdks/symbolic/nrflib/cells/rf_dec_bufad0.ap new file mode 100644 index 000000000..9942243f2 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_bufad0.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H rf_dec_bufad0,P,22/4/2016,100 +A 0,0,9000,10000 +S 2000,2000,2000,8000,300,i,UP,CALU1 +S 4000,2000,4000,8000,300,nq,UP,CALU1 +S 7000,2000,7000,8000,300,q,UP,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S -600,7800,9600,7800,6000,0nonymous_,RIGHT,NWELL +S 600,6000,600,9400,300,1nonymous_,UP,ALU1 +S 600,600,600,3000,300,2nonymous_,UP,ALU1 +S 600,280,600,3320,600,3nonymous_,UP,PTIE +S 600,5680,600,9720,600,4nonymous_,UP,NTIE +S 7400,5700,7400,9300,600,35onymous_,UP,PDIF +S 5000,5700,5000,9300,600,34onymous_,UP,PDIF +S 2600,5700,2600,9300,600,33onymous_,UP,PDIF +S 5600,5500,5600,9500,200,32onymous_,UP,PTRANS +S 6200,5700,6200,9300,600,31onymous_,UP,PDIF +S 4400,5500,4400,9500,200,30onymous_,UP,PTRANS +S 3200,5500,3200,9500,200,29onymous_,UP,PTRANS +S 3800,5700,3800,9300,600,28onymous_,UP,PDIF +S 6800,5500,6800,9500,200,27onymous_,UP,PTRANS +S 5600,500,5600,2500,200,26onymous_,UP,NTRANS +S 6800,500,6800,2500,200,25onymous_,UP,NTRANS +S 3200,500,3200,2500,200,24onymous_,UP,NTRANS +S 4400,500,4400,2500,200,23onymous_,UP,NTRANS +S 5000,700,5000,2300,600,22onymous_,UP,NDIF +S 6200,700,6200,2300,600,21onymous_,UP,NDIF +S 2600,700,2600,2300,600,20onymous_,UP,NDIF +S 3800,700,3800,2300,600,19onymous_,UP,NDIF +S 7400,700,7400,2300,600,18onymous_,UP,NDIF +S 2000,4000,4400,4000,600,17onymous_,RIGHT,POLY +S 3200,2800,3200,5200,200,16onymous_,UP,POLY +S 5000,1000,5000,2000,300,5nonymous_,UP,ALU1 +S 5000,6000,5000,9000,300,6nonymous_,UP,ALU1 +S 4000,3000,5200,3000,300,7nonymous_,RIGHT,ALU1 +S 6200,8000,7000,8000,300,8nonymous_,RIGHT,ALU1 +S 6200,2000,7000,2000,300,9nonymous_,RIGHT,ALU1 +S 6200,6000,7000,6000,300,10onymous_,RIGHT,ALU1 +S 6200,7000,7000,7000,300,11onymous_,RIGHT,ALU1 +S 4400,2800,4400,5200,200,15onymous_,UP,POLY +S 5600,2800,5600,5200,200,14onymous_,UP,POLY +S 6800,2800,6800,5200,200,13onymous_,UP,POLY +S 5200,3000,6800,3000,600,12onymous_,RIGHT,POLY +V 5000,7000,CONT_DIF_P,52onymous_ +V 5000,6000,CONT_DIF_P,53onymous_ +V 7400,9000,CONT_DIF_P,54onymous_ +V 6200,8000,CONT_DIF_P,55onymous_ +V 6200,7000,CONT_DIF_P,56onymous_ +V 6200,6000,CONT_DIF_P,57onymous_ +V 3800,7000,CONT_DIF_P,58onymous_ +V 3800,6000,CONT_DIF_P,59onymous_ +V 3800,8000,CONT_DIF_P,60onymous_ +V 2600,9000,CONT_DIF_P,61onymous_ +V 5000,9000,CONT_DIF_P,62onymous_ +V 5000,8000,CONT_DIF_P,51onymous_ +V 5000,1000,CONT_DIF_N,50onymous_ +V 2600,1000,CONT_DIF_N,49onymous_ +V 6200,2000,CONT_DIF_N,48onymous_ +V 3800,2000,CONT_DIF_N,47onymous_ +V 7400,1000,CONT_DIF_N,46onymous_ +V 5000,2000,CONT_DIF_N,45onymous_ +V 5200,3000,CONT_POLY,44onymous_ +V 2000,4000,CONT_POLY,43onymous_ +V 600,7000,CONT_BODY_N,42onymous_ +V 600,8000,CONT_BODY_N,41onymous_ +V 600,9300,CONT_BODY_N,40onymous_ +V 600,6000,CONT_BODY_N,39onymous_ +V 600,3000,CONT_BODY_P,38onymous_ +V 600,600,CONT_BODY_P,37onymous_ +V 600,2000,CONT_BODY_P,36onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_dec_bufad0.vbe b/pdks/symbolic/nrflib/cells/rf_dec_bufad0.vbe new file mode 100644 index 000000000..03c3741f1 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_bufad0.vbe @@ -0,0 +1,21 @@ +ENTITY rf_dec_bufad0 IS +PORT ( + i : in BIT; + nq : inout BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_bufad0; + +ARCHITECTURE VBE OF rf_dec_bufad0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_bufad0" + SEVERITY WARNING; + + nq <= not i; + q <= not nq; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_dec_bufad1.ap b/pdks/symbolic/nrflib/cells/rf_dec_bufad1.ap new file mode 100644 index 000000000..fea83eb5a --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_bufad1.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H rf_dec_bufad1,P,22/4/2016,100 +A 0,0,10000,10000 +S 2000,2000,2000,8000,300,i,UP,CALU1 +S 5000,2000,5000,8000,300,nq,UP,CALU1 +S 8000,2000,8000,8000,300,q,UP,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S -600,7800,10600,7800,6000,0nonymous_,RIGHT,NWELL +S 3600,6000,3600,9000,300,1nonymous_,UP,ALU1 +S 3600,1000,3600,2000,300,2nonymous_,UP,ALU1 +S 6000,1000,6000,2000,300,3nonymous_,UP,ALU1 +S 6000,6000,6000,9000,300,4nonymous_,UP,ALU1 +S 7200,7000,8000,7000,300,35onymous_,RIGHT,ALU1 +S 7200,8000,8000,8000,300,34onymous_,RIGHT,ALU1 +S 2000,4000,5400,4000,600,33onymous_,RIGHT,POLY +S 600,5680,600,9720,600,32onymous_,UP,NTIE +S 600,280,600,3320,600,31onymous_,UP,PTIE +S 600,6000,600,9400,300,30onymous_,UP,ALU1 +S 600,600,600,3000,300,29onymous_,UP,ALU1 +S 5000,3000,6200,3000,300,28onymous_,RIGHT,ALU1 +S 7800,5500,7800,9500,200,27onymous_,UP,PTRANS +S 8400,5700,8400,9300,600,26onymous_,UP,PDIF +S 6000,5700,6000,9300,600,25onymous_,UP,PDIF +S 3600,5700,3600,9300,600,24onymous_,UP,PDIF +S 6600,5500,6600,9500,200,23onymous_,UP,PTRANS +S 7200,5700,7200,9300,600,22onymous_,UP,PDIF +S 5400,5500,5400,9500,200,21onymous_,UP,PTRANS +S 4200,5500,4200,9500,200,20onymous_,UP,PTRANS +S 4800,5700,4800,9300,600,19onymous_,UP,PDIF +S 6600,500,6600,2500,200,18onymous_,UP,NTRANS +S 7800,500,7800,2500,200,17onymous_,UP,NTRANS +S 4200,500,4200,2500,200,16onymous_,UP,NTRANS +S 6200,3000,7800,3000,600,5nonymous_,RIGHT,POLY +S 7800,2800,7800,5200,200,6nonymous_,UP,POLY +S 6600,2800,6600,5200,200,7nonymous_,UP,POLY +S 5400,2800,5400,5200,200,8nonymous_,UP,POLY +S 4200,2800,4200,5200,200,9nonymous_,UP,POLY +S 3600,700,3600,2300,600,10onymous_,UP,NDIF +S 7200,700,7200,2300,600,11onymous_,UP,NDIF +S 6000,700,6000,2300,600,12onymous_,UP,NDIF +S 8400,700,8400,2300,600,13onymous_,UP,NDIF +S 4800,700,4800,2300,600,14onymous_,UP,NDIF +S 5400,500,5400,2500,200,15onymous_,UP,NTRANS +S 7200,6000,8000,6000,300,36onymous_,RIGHT,ALU1 +S 7200,2000,8000,2000,300,37onymous_,RIGHT,ALU1 +V 8400,9000,CONT_DIF_P,58onymous_ +V 7200,8000,CONT_DIF_P,59onymous_ +V 7200,7000,CONT_DIF_P,60onymous_ +V 600,2000,CONT_BODY_P,61onymous_ +V 600,600,CONT_BODY_P,62onymous_ +V 600,3000,CONT_BODY_P,63onymous_ +V 600,8000,CONT_BODY_N,64onymous_ +V 600,7000,CONT_BODY_N,65onymous_ +V 600,6000,CONT_BODY_N,66onymous_ +V 600,9300,CONT_BODY_N,67onymous_ +V 2000,4000,CONT_POLY,68onymous_ +V 6000,6000,CONT_DIF_P,57onymous_ +V 6000,7000,CONT_DIF_P,56onymous_ +V 3600,8000,CONT_DIF_P,55onymous_ +V 3600,7000,CONT_DIF_P,54onymous_ +V 3600,6000,CONT_DIF_P,53onymous_ +V 3600,9000,CONT_DIF_P,52onymous_ +V 6000,8000,CONT_DIF_P,51onymous_ +V 4800,8000,CONT_DIF_P,50onymous_ +V 4800,6000,CONT_DIF_P,49onymous_ +V 4800,7000,CONT_DIF_P,48onymous_ +V 7200,6000,CONT_DIF_P,47onymous_ +V 6000,9000,CONT_DIF_P,46onymous_ +V 8400,1000,CONT_DIF_N,45onymous_ +V 6000,2000,CONT_DIF_N,44onymous_ +V 6000,1000,CONT_DIF_N,43onymous_ +V 3600,1000,CONT_DIF_N,42onymous_ +V 3600,2000,CONT_DIF_N,41onymous_ +V 7200,2000,CONT_DIF_N,40onymous_ +V 4800,2000,CONT_DIF_N,39onymous_ +V 6200,3000,CONT_POLY,38onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_dec_bufad1.vbe b/pdks/symbolic/nrflib/cells/rf_dec_bufad1.vbe new file mode 100644 index 000000000..af255e8df --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_bufad1.vbe @@ -0,0 +1,21 @@ +ENTITY rf_dec_bufad1 IS +PORT ( + i : in BIT; + nq : inout BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_bufad1; + +ARCHITECTURE VBE OF rf_dec_bufad1 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_bufad1" + SEVERITY WARNING; + + nq <= not i; + q <= not nq; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_dec_bufad2.ap b/pdks/symbolic/nrflib/cells/rf_dec_bufad2.ap new file mode 100644 index 000000000..8ca629c37 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_bufad2.ap @@ -0,0 +1,103 @@ +V ALLIANCE : 6 +H rf_dec_bufad2,P,22/4/2016,100 +A 0,0,10000,10000 +S 10200,5700,10200,9300,600,4nonymous_,UP,PDIF +S 6600,5700,6600,9300,600,3nonymous_,UP,PDIF +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 1200,3000,2800,3000,600,0nonymous_,RIGHT,POLY +S 1200,5000,2800,5000,600,1nonymous_,RIGHT,POLY +S 8000,5000,9600,5000,600,2nonymous_,RIGHT,POLY +S 1800,5700,1800,9300,600,38onymous_,UP,PDIF +S 3600,500,3600,2500,200,37onymous_,UP,NTRANS +S 4800,500,4800,2500,200,36onymous_,UP,NTRANS +S 1200,500,1200,2500,200,35onymous_,UP,NTRANS +S 2400,500,2400,2500,200,34onymous_,UP,NTRANS +S 3000,700,3000,2300,600,33onymous_,UP,NDIF +S 9600,500,9600,2500,200,12onymous_,UP,NTRANS +S 7200,5500,7200,9500,200,11onymous_,UP,PTRANS +S 5400,5700,5400,9300,600,10onymous_,UP,PDIF +S 6000,5500,6000,9500,200,9nonymous_,UP,PTRANS +S 9000,5700,9000,9300,600,8nonymous_,UP,PDIF +S 9600,5500,9600,9500,200,7nonymous_,UP,PTRANS +S 7800,5700,7800,9300,600,6nonymous_,UP,PDIF +S 8400,5500,8400,9500,200,5nonymous_,UP,PTRANS +S 8400,500,8400,2500,200,13onymous_,UP,NTRANS +S 7200,500,7200,2500,200,14onymous_,UP,NTRANS +S 6000,500,6000,2500,200,15onymous_,UP,NTRANS +S 6600,700,6600,2300,600,16onymous_,UP,NDIF +S 5400,700,5400,2300,600,17onymous_,UP,NDIF +S 10200,700,10200,2300,600,18onymous_,UP,NDIF +S 4800,5500,4800,9500,200,29onymous_,UP,PTRANS +S 1800,700,1800,2300,600,30onymous_,UP,NDIF +S 600,700,600,2300,600,31onymous_,UP,NDIF +S 4200,700,4200,2300,600,32onymous_,UP,NDIF +S 3600,2800,3600,5200,200,28onymous_,UP,POLY +S 4800,2800,4800,5200,200,27onymous_,UP,POLY +S -600,7800,10600,7800,6000,26onymous_,RIGHT,NWELL +S 10200,1000,10200,2000,300,25onymous_,UP,ALU1 +S 10200,6000,10200,9000,300,24onymous_,UP,ALU1 +S 6000,2800,6000,5200,200,23onymous_,UP,POLY +S 7200,2800,7200,5200,200,22onymous_,UP,POLY +S 8000,3000,9600,3000,600,21onymous_,RIGHT,POLY +S 7800,700,7800,2300,600,20onymous_,UP,NDIF +S 9000,700,9000,2300,600,19onymous_,UP,NDIF +S 1200,5500,1200,9500,200,39onymous_,UP,PTRANS +S 2400,5500,2400,9500,200,40onymous_,UP,PTRANS +S 4200,5700,4200,9300,600,41onymous_,UP,PDIF +S 3600,5500,3600,9500,200,42onymous_,UP,PTRANS +S 600,5700,600,9300,600,43onymous_,UP,PDIF +S 3000,5700,3000,9300,600,44onymous_,UP,PDIF +S 6000,4000,9000,4000,600,45onymous_,RIGHT,POLY +S 1000,8000,1800,8000,300,46onymous_,RIGHT,ALU1 +S 1000,7000,1800,7000,300,47onymous_,RIGHT,ALU1 +S 1000,6000,1800,6000,300,48onymous_,RIGHT,ALU1 +S 1000,2000,1800,2000,300,49onymous_,RIGHT,ALU1 +S 1000,4000,4800,4000,600,50onymous_,RIGHT,POLY +S 6200,2000,6600,2000,300,51onymous_,RIGHT,ALU1 +S 6200,6000,6600,6000,300,52onymous_,RIGHT,ALU1 +S 6200,7000,6600,7000,300,53onymous_,RIGHT,ALU1 +S 6200,8000,6600,8000,300,54onymous_,RIGHT,ALU1 +S 3000,2000,3000,8000,300,i0,UP,CALU1 +S 8000,2000,8000,8000,300,i1,UP,CALU1 +S 1000,2000,1000,8000,300,nq0,UP,CALU1 +S 4000,2000,4000,8000,300,q0,UP,CALU1 +S 9000,2000,9000,8000,300,nq1,UP,CALU1 +S 6000,2000,6000,8000,300,q1,UP,CALU1 +V 2800,3000,CONT_POLY,55onymous_ +V 2800,5000,CONT_POLY,56onymous_ +V 8000,5000,CONT_POLY,57onymous_ +V 5400,9000,CONT_DIF_P,58onymous_ +V 10200,6000,CONT_DIF_P,59onymous_ +V 10200,7000,CONT_DIF_P,60onymous_ +V 9000,8000,CONT_DIF_P,61onymous_ +V 9000,7000,CONT_DIF_P,62onymous_ +V 9000,6000,CONT_DIF_P,63onymous_ +V 7800,9000,CONT_DIF_P,64onymous_ +V 10200,9000,CONT_DIF_P,65onymous_ +V 10200,8000,CONT_DIF_P,66onymous_ +V 9000,2000,CONT_DIF_N,67onymous_ +V 7800,1000,CONT_DIF_N,68onymous_ +V 1800,2000,CONT_DIF_N,72onymous_ +V 5400,1000,CONT_DIF_N,71onymous_ +V 10200,1000,CONT_DIF_N,70onymous_ +V 10200,2000,CONT_DIF_N,69onymous_ +V 4200,2000,CONT_DIF_N,73onymous_ +V 4200,8000,CONT_DIF_P,74onymous_ +V 4200,7000,CONT_DIF_P,75onymous_ +V 4200,6000,CONT_DIF_P,76onymous_ +V 1800,7000,CONT_DIF_P,77onymous_ +V 1800,6000,CONT_DIF_P,78onymous_ +V 1800,8000,CONT_DIF_P,79onymous_ +V 600,9000,CONT_DIF_P,80onymous_ +V 6600,2000,CONT_DIF_N,90onymous_ +V 6600,6000,CONT_DIF_P,89onymous_ +V 6600,8000,CONT_DIF_P,88onymous_ +V 6600,7000,CONT_DIF_P,87onymous_ +V 1000,4000,CONT_POLY,86onymous_ +V 8000,3000,CONT_POLY,85onymous_ +V 9000,4000,CONT_POLY,84onymous_ +V 3000,1000,CONT_DIF_N,83onymous_ +V 3000,9000,CONT_DIF_P,82onymous_ +V 600,1000,CONT_DIF_N,81onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_dec_bufad2.vbe b/pdks/symbolic/nrflib/cells/rf_dec_bufad2.vbe new file mode 100644 index 000000000..10b7cb272 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_bufad2.vbe @@ -0,0 +1,26 @@ +ENTITY rf_dec_bufad2 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + nq0 : inout BIT; + q0 : out BIT; + nq1 : inout BIT; + q1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_bufad2; + +ARCHITECTURE VBE OF rf_dec_bufad2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_bufad2" + SEVERITY WARNING; + + nq0 <= not i0; + q0 <= not nq0; + nq1 <= not i1; + q1 <= not nq1; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nand2.ap b/pdks/symbolic/nrflib/cells/rf_dec_nand2.ap new file mode 100644 index 000000000..ce30894df --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nand2.ap @@ -0,0 +1,63 @@ +V ALLIANCE : 6 +H rf_dec_nand2,P,23/ 4/2016,100 +A 0,0,10000,10000 +S 6000,2000,6000,7000,400,nq,UP,CALU1 +S 5000,3000,5000,6000,400,i1,UP,CALU1 +S 3200,4000,4000,4000,300,i0,LEFT,ALU1 +S 3200,2800,3200,7100,400,i0,DOWN,CALU1 +S 1400,280,1400,3320,600,11onymous_,UP,PTIE +S 1400,600,1400,3000,300,12onymous_,UP,ALU1 +S 1400,6000,1400,9400,300,13onymous_,UP,ALU1 +S -600,7800,10600,7800,6000,14onymous_,RIGHT,NWELL +S 3400,1000,3400,2000,300,15onymous_,UP,ALU1 +S 1400,5680,1400,9720,600,10onymous_,UP,NTIE +S 8600,600,8600,3000,300,9nonymous_,UP,ALU1 +S 8600,6000,8600,9400,300,8nonymous_,UP,ALU1 +S 8600,280,8600,3320,600,7nonymous_,UP,PTIE +S 8600,5680,8600,9720,600,6nonymous_,UP,NTIE +S 3400,700,3400,2300,600,16onymous_,UP,NDIF +S 5400,700,5400,2300,600,17onymous_,UP,NDIF +S 4000,500,4000,2500,200,18onymous_,UP,NTRANS +S 4800,500,4800,2500,200,19onymous_,UP,NTRANS +S 3400,8000,3400,9000,300,20onymous_,UP,ALU1 +S 5800,8000,5800,9000,300,21onymous_,UP,ALU1 +S 4600,6700,4600,8300,600,22onymous_,UP,PDIF +S 4000,6500,4000,8500,200,23onymous_,UP,PTRANS +S 5200,6500,5200,8500,200,24onymous_,UP,PTRANS +S 5800,6700,5800,9100,600,25onymous_,UP,PDIF +S 3400,6700,3400,9100,600,26onymous_,UP,PDIF +S 4000,2800,4000,6200,200,27onymous_,UP,POLY +S 4600,7000,6000,7000,300,29onymous_,RIGHT,ALU1 +S 5400,2000,6000,2000,300,30onymous_,RIGHT,ALU1 +S 4800,2800,4800,4200,200,32onymous_,UP,POLY +S 5200,3800,5200,6200,200,33onymous_,UP,POLY +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +V 8600,9300,CONT_BODY_N,36onymous_ +V 8600,7000,CONT_BODY_N,37onymous_ +V 8600,6000,CONT_BODY_N,38onymous_ +V 8600,8000,CONT_BODY_N,39onymous_ +V 8600,600,CONT_BODY_P,40onymous_ +V 8600,2000,CONT_BODY_P,41onymous_ +V 8600,3000,CONT_BODY_P,42onymous_ +V 1400,7000,CONT_BODY_N,43onymous_ +V 1400,9300,CONT_BODY_N,44onymous_ +V 1400,8000,CONT_BODY_N,45onymous_ +V 1400,6000,CONT_BODY_N,46onymous_ +V 1400,3000,CONT_BODY_P,47onymous_ +V 1400,2000,CONT_BODY_P,48onymous_ +V 1400,600,CONT_BODY_P,49onymous_ +V 3400,2000,CONT_DIF_N,50onymous_ +V 5000,4000,CONT_POLY,62onymous_ +V 4000,4000,CONT_POLY,63onymous_ +V 5000,4000,CONT_VIA2,59onymous_ +V 7000,4000,CONT_VIA2,58onymous_ +V 5400,2000,CONT_DIF_N,57onymous_ +V 3400,9000,CONT_DIF_P,56onymous_ +V 3400,8000,CONT_DIF_P,55onymous_ +V 5800,8000,CONT_DIF_P,54onymous_ +V 4600,7000,CONT_DIF_P,53onymous_ +V 5800,9000,CONT_DIF_P,52onymous_ +V 3400,1000,CONT_DIF_N,51onymous_ +V 3000,4000,CONT_VIA2,35onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nand2.vbe b/pdks/symbolic/nrflib/cells/rf_dec_nand2.vbe new file mode 100644 index 000000000..7c0132d87 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nand2.vbe @@ -0,0 +1,20 @@ +ENTITY rf_dec_nand2 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nand2; + +ARCHITECTURE VBE OF rf_dec_nand2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nand2" + SEVERITY WARNING; + + nq <= not(i0 and i1); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nand3.ap b/pdks/symbolic/nrflib/cells/rf_dec_nand3.ap new file mode 100644 index 000000000..eaa50c9cc --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nand3.ap @@ -0,0 +1,88 @@ +V ALLIANCE : 6 +H rf_dec_nand3,P,22/4/2016,100 +A 0,0,10000,10000 +S 9000,3850,9000,4150,400,nq,UP,CALU3 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 2050,4000,8950,4000,300,0nonymous_,RIGHT,TALU2 +S 1850,4000,3150,4000,600,1nonymous_,RIGHT,ALU2 +S 3850,4000,5150,4000,600,2nonymous_,RIGHT,ALU2 +S 3000,4000,4000,4000,300,3nonymous_,RIGHT,ALU1 +S 5000,4000,5000,5000,300,4nonymous_,UP,ALU1 +S 1400,5680,1400,9720,600,37onymous_,UP,NTIE +S 3800,7000,7000,7000,300,36onymous_,RIGHT,ALU1 +S 7000,2000,7000,7000,300,35onymous_,UP,ALU1 +S 6200,6200,6800,6200,200,14onymous_,RIGHT,POLY +S 6200,2000,7000,2000,300,13onymous_,RIGHT,ALU1 +S 5850,4000,7150,4000,600,12onymous_,RIGHT,ALU2 +S 7000,4000,8000,4000,300,11onymous_,RIGHT,ALU1 +S 4800,2800,4800,4200,200,10onymous_,UP,POLY +S 5200,3800,5200,6200,200,9nonymous_,UP,POLY +S 6200,2800,6200,6200,200,8nonymous_,UP,POLY +S 5600,2800,6200,2800,200,7nonymous_,RIGHT,POLY +S 7850,4000,9150,4000,600,6nonymous_,RIGHT,ALU2 +S 6000,4000,6000,5000,300,5nonymous_,UP,ALU1 +S 5200,6200,5600,6200,200,15onymous_,RIGHT,POLY +S 8600,5680,8600,9720,600,16onymous_,UP,NTIE +S 8600,280,8600,3320,600,17onymous_,UP,PTIE +S 8600,6000,8600,9400,300,18onymous_,UP,ALU1 +S 8600,600,8600,3000,300,19onymous_,UP,ALU1 +S 6200,6700,6200,8300,600,20onymous_,UP,PDIF +S 5000,6700,5000,9100,600,21onymous_,UP,PDIF +S 4000,2800,4000,6200,200,32onymous_,UP,POLY +S 7400,8000,7400,9000,300,33onymous_,UP,ALU1 +S 5000,8000,5000,9000,300,34onymous_,UP,ALU1 +S 4000,6200,4400,6200,200,31onymous_,RIGHT,POLY +S 6200,700,6200,2300,600,30onymous_,UP,NDIF +S 4000,500,4000,2500,200,29onymous_,UP,NTRANS +S 4800,500,4800,2500,200,28onymous_,UP,NTRANS +S 5600,500,5600,2500,200,27onymous_,UP,NTRANS +S 3800,6700,3800,8300,600,26onymous_,UP,PDIF +S 4400,6500,4400,8500,200,25onymous_,UP,PTRANS +S 5600,6500,5600,8500,200,24onymous_,UP,PTRANS +S 6800,6500,6800,8500,200,23onymous_,UP,PTRANS +S 7400,6700,7400,9100,600,22onymous_,UP,PDIF +S 1400,280,1400,3320,600,38onymous_,UP,PTIE +S 1400,600,1400,3000,300,39onymous_,UP,ALU1 +S 1400,6000,1400,9400,300,40onymous_,UP,ALU1 +S -600,7800,10600,7800,6000,41onymous_,RIGHT,NWELL +S 3400,700,3400,2300,600,42onymous_,UP,NDIF +S 3400,1000,3400,2000,300,43onymous_,UP,ALU1 +S 5000,3850,5000,4150,400,i2,UP,CALU3 +S 3000,3850,3000,4150,400,i1,UP,CALU3 +S 7000,3850,7000,4150,400,i0,UP,CALU3 +V 3000,4000,CONT_VIA,44onymous_ +V 3000,4000,CONT_VIA2,45onymous_ +V 9000,4000,CONT_VIA2,46onymous_ +V 4000,4000,CONT_POLY,47onymous_ +V 5000,4000,CONT_POLY,48onymous_ +V 6000,4000,CONT_POLY,49onymous_ +V 6000,4000,CONT_VIA,50onymous_ +V 5000,4000,CONT_VIA,51onymous_ +V 8000,4000,CONT_VIA,52onymous_ +V 7000,4000,CONT_VIA2,53onymous_ +V 5000,4000,CONT_VIA2,54onymous_ +V 6200,2000,CONT_DIF_N,55onymous_ +V 8600,9300,CONT_BODY_N,56onymous_ +V 8600,7000,CONT_BODY_N,57onymous_ +V 8600,6000,CONT_BODY_N,58onymous_ +V 8600,8000,CONT_BODY_N,59onymous_ +V 8600,600,CONT_BODY_P,60onymous_ +V 8600,2000,CONT_BODY_P,61onymous_ +V 8600,3000,CONT_BODY_P,62onymous_ +V 5000,9000,CONT_DIF_P,63onymous_ +V 5000,8000,CONT_DIF_P,64onymous_ +V 7400,8000,CONT_DIF_P,65onymous_ +V 6200,7000,CONT_DIF_P,66onymous_ +V 3800,7000,CONT_DIF_P,67onymous_ +V 7400,9000,CONT_DIF_P,68onymous_ +V 1400,2000,CONT_BODY_P,74onymous_ +V 1400,3000,CONT_BODY_P,73onymous_ +V 1400,6000,CONT_BODY_N,72onymous_ +V 3400,2000,CONT_DIF_N,77onymous_ +V 3400,1000,CONT_DIF_N,76onymous_ +V 1400,600,CONT_BODY_P,75onymous_ +V 1400,7000,CONT_BODY_N,69onymous_ +V 1400,9300,CONT_BODY_N,70onymous_ +V 1400,8000,CONT_BODY_N,71onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nand3.vbe b/pdks/symbolic/nrflib/cells/rf_dec_nand3.vbe new file mode 100644 index 000000000..c1eec05c4 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nand3.vbe @@ -0,0 +1,21 @@ +ENTITY rf_dec_nand3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nand3; + +ARCHITECTURE VBE OF rf_dec_nand3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nand3" + SEVERITY WARNING; + + nq <= not(i0 and i1 and i2); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nand4.ap b/pdks/symbolic/nrflib/cells/rf_dec_nand4.ap new file mode 100644 index 000000000..21c72ddb3 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nand4.ap @@ -0,0 +1,102 @@ +V ALLIANCE : 6 +H rf_dec_nand4,P,22/4/2016,100 +A 0,0,10000,10000 +S 6000,4000,6000,5000,300,4nonymous_,UP,ALU1 +S 7850,4000,9150,4000,600,nq,RIGHT,CALU2 +S 9000,3850,9000,4150,400,nq,UP,CALU3 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 1000,4000,1000,5000,300,0nonymous_,UP,ALU1 +S 1000,4000,3200,4000,600,1nonymous_,RIGHT,POLY +S 3000,4000,4000,4000,300,2nonymous_,RIGHT,ALU1 +S 5000,4000,5000,5000,300,3nonymous_,UP,ALU1 +S 8600,600,8600,3000,300,37onymous_,UP,ALU1 +S 6200,6700,6200,8300,600,36onymous_,UP,PDIF +S 2600,6700,2600,9100,600,35onymous_,UP,PDIF +S 5000,6700,5000,9100,600,34onymous_,UP,PDIF +S 2600,7000,2600,9000,300,13onymous_,UP,ALU1 +S 1400,5680,1400,9720,600,12onymous_,UP,NTIE +S 1400,280,1400,3320,600,11onymous_,UP,PTIE +S 1400,600,1400,3000,300,10onymous_,UP,ALU1 +S 1400,6000,1400,9400,300,9nonymous_,UP,ALU1 +S -600,7800,10600,7800,6000,8nonymous_,RIGHT,NWELL +S 5200,6200,5600,6200,200,7nonymous_,RIGHT,POLY +S 6200,6200,6800,6200,200,6nonymous_,RIGHT,POLY +S 6200,2000,7000,2000,300,5nonymous_,RIGHT,ALU1 +S 3800,7000,7000,7000,300,14onymous_,RIGHT,ALU1 +S 7000,2000,7000,7000,300,15onymous_,UP,ALU1 +S 5000,8000,5000,9000,300,16onymous_,UP,ALU1 +S 7400,8000,7400,9000,300,17onymous_,UP,ALU1 +S 2600,1000,2600,2000,300,18onymous_,UP,ALU1 +S 4000,2800,4000,6200,200,19onymous_,UP,POLY +S 4000,6200,4400,6200,200,20onymous_,RIGHT,POLY +S 6800,6500,6800,8500,200,31onymous_,UP,PTRANS +S 3200,6500,3200,8500,200,32onymous_,UP,PTRANS +S 7400,6700,7400,9100,600,33onymous_,UP,PDIF +S 5600,6500,5600,8500,200,30onymous_,UP,PTRANS +S 4400,6500,4400,8500,200,29onymous_,UP,PTRANS +S 3800,6700,3800,8300,600,28onymous_,UP,PDIF +S 5600,500,5600,2500,200,27onymous_,UP,NTRANS +S 4800,500,4800,2500,200,26onymous_,UP,NTRANS +S 4000,500,4000,2500,200,25onymous_,UP,NTRANS +S 3200,500,3200,2500,200,24onymous_,UP,NTRANS +S 2600,700,2600,2300,600,23onymous_,UP,NDIF +S 6200,700,6200,2300,600,22onymous_,UP,NDIF +S 3200,2800,3200,6200,200,21onymous_,UP,POLY +S 8600,6000,8600,9400,300,38onymous_,UP,ALU1 +S 8600,280,8600,3320,600,39onymous_,UP,PTIE +S 8600,5680,8600,9720,600,40onymous_,UP,NTIE +S 7000,4000,8000,4000,300,41onymous_,RIGHT,ALU1 +S 5200,3800,5200,6200,200,42onymous_,UP,POLY +S 4800,2800,4800,4200,200,43onymous_,UP,POLY +S 6200,2800,6200,6200,200,44onymous_,UP,POLY +S 5600,2800,6200,2800,200,45onymous_,RIGHT,POLY +S -150,4000,1150,4000,600,i0,RIGHT,CALU2 +S 1000,3850,1000,4150,400,i0,UP,CALU3 +S 1850,4000,3150,4000,600,i1,RIGHT,CALU2 +S 3000,3850,3000,4150,400,i1,UP,CALU3 +S 3850,4000,5150,4000,600,i2,RIGHT,CALU2 +S 5000,3850,5000,4150,400,i2,UP,CALU3 +S 5850,4000,7150,4000,600,i3,RIGHT,CALU2 +S 7000,3850,7000,4150,400,i3,UP,CALU3 +V 9000,4000,CONT_VIA2,46onymous_ +V 3000,4000,CONT_VIA,47onymous_ +V 3000,4000,CONT_VIA2,48onymous_ +V 1000,4000,CONT_POLY,49onymous_ +V 1000,4000,CONT_VIA,50onymous_ +V 1000,4000,CONT_VIA2,51onymous_ +V 6200,2000,CONT_DIF_N,52onymous_ +V 1400,600,CONT_BODY_P,53onymous_ +V 1400,2000,CONT_BODY_P,54onymous_ +V 1400,3000,CONT_BODY_P,55onymous_ +V 1400,6000,CONT_BODY_N,56onymous_ +V 1400,8000,CONT_BODY_N,57onymous_ +V 1400,9300,CONT_BODY_N,58onymous_ +V 1400,7000,CONT_BODY_N,59onymous_ +V 2600,1000,CONT_DIF_N,60onymous_ +V 2600,2000,CONT_DIF_N,61onymous_ +V 7400,9000,CONT_DIF_P,62onymous_ +V 2600,9000,CONT_DIF_P,63onymous_ +V 2600,8000,CONT_DIF_P,64onymous_ +V 2600,7000,CONT_DIF_P,65onymous_ +V 3800,7000,CONT_DIF_P,66onymous_ +V 6200,7000,CONT_DIF_P,67onymous_ +V 7400,8000,CONT_DIF_P,68onymous_ +V 8600,600,CONT_BODY_P,73onymous_ +V 8600,2000,CONT_BODY_P,72onymous_ +V 8600,3000,CONT_BODY_P,71onymous_ +V 5000,9000,CONT_DIF_P,70onymous_ +V 5000,8000,CONT_DIF_P,69onymous_ +V 8600,8000,CONT_BODY_N,74onymous_ +V 8600,6000,CONT_BODY_N,75onymous_ +V 8600,7000,CONT_BODY_N,76onymous_ +V 4000,4000,CONT_POLY,85onymous_ +V 5000,4000,CONT_POLY,84onymous_ +V 6000,4000,CONT_POLY,83onymous_ +V 8000,4000,CONT_VIA,82onymous_ +V 5000,4000,CONT_VIA,81onymous_ +V 6000,4000,CONT_VIA,80onymous_ +V 7000,4000,CONT_VIA2,79onymous_ +V 5000,4000,CONT_VIA2,78onymous_ +V 8600,9300,CONT_BODY_N,77onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nand4.vbe b/pdks/symbolic/nrflib/cells/rf_dec_nand4.vbe new file mode 100644 index 000000000..b8fb199a3 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nand4.vbe @@ -0,0 +1,22 @@ +ENTITY rf_dec_nand4 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nand4; + +ARCHITECTURE VBE OF rf_dec_nand4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nand4" + SEVERITY WARNING; + + nq <= not(i0 and i1 and i2 and i3); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nao3.ap b/pdks/symbolic/nrflib/cells/rf_dec_nao3.ap new file mode 100644 index 000000000..2b645fb13 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nao3.ap @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H rf_dec_nao3,P,22/4/2016,100 +A 0,0,5000,10000 +S 1850,3000,3150,3000,600,nq,RIGHT,CALU2 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 1000,4000,2000,4000,300,0nonymous_,RIGHT,ALU1 +S 4400,900,4400,3300,600,1nonymous_,UP,NDIF +S 600,6000,600,9000,300,2nonymous_,UP,ALU1 +S 1800,5700,1800,9300,400,3nonymous_,UP,PDIF +S 600,5700,600,9300,600,4nonymous_,UP,PDIF +S 280,700,3320,700,600,30onymous_,RIGHT,PTIE +S 4000,4000,4000,7000,300,29onymous_,UP,ALU1 +S 4200,8000,4200,9000,300,28onymous_,UP,ALU1 +S 2000,4000,2400,4000,600,27onymous_,RIGHT,POLY +S 2400,5500,2400,9500,200,26onymous_,UP,PTRANS +S 2000,5000,2000,8000,300,25onymous_,UP,ALU1 +S -600,7800,5600,7800,6000,24onymous_,RIGHT,NWELL +S 3600,5500,3600,9500,200,23onymous_,UP,PTRANS +S 4200,5700,4200,9300,600,22onymous_,UP,PDIF +S 600,2000,3000,2000,300,21onymous_,RIGHT,ALU1 +S 3000,3000,3000,8000,300,20onymous_,UP,ALU1 +S 1800,3000,3000,3000,300,19onymous_,RIGHT,ALU1 +S 1200,1500,1200,3500,200,18onymous_,UP,NTRANS +S 1800,1700,1800,3300,600,14onymous_,UP,NDIF +S 3600,4000,4200,4000,600,13onymous_,RIGHT,POLY +S 3600,1500,3600,3500,200,12onymous_,UP,NTRANS +S 4200,900,4200,3300,600,11onymous_,UP,NDIF +S 3000,5700,3000,9300,400,10onymous_,UP,PDIF +S 3600,3800,3600,5200,200,9nonymous_,UP,POLY +S 2400,3800,2400,5200,200,8nonymous_,UP,POLY +S 1200,3800,1200,5200,200,7nonymous_,UP,POLY +S 1400,5000,2000,5000,300,6nonymous_,RIGHT,ALU1 +S 1200,5500,1200,9500,200,5nonymous_,UP,PTRANS +S 600,1700,600,3300,600,15onymous_,UP,NDIF +S 3000,1700,3000,3300,600,16onymous_,UP,NDIF +S 2400,1500,2400,3500,200,17onymous_,UP,NTRANS +S 2850,7000,4150,7000,600,i2,RIGHT,CALU2 +S 850,4000,2150,4000,600,i1,RIGHT,CALU2 +S 1850,8000,3150,8000,600,i0,RIGHT,CALU2 +V 3000,6000,CONT_DIF_P,34onymous_ +V 1400,5000,CONT_POLY,33onymous_ +V 600,9000,CONT_DIF_P,32onymous_ +V 3000,3000,CONT_VIA,31onymous_ +V 4200,1000,CONT_DIF_N,42onymous_ +V 3000,600,CONT_BODY_P,43onymous_ +V 600,600,CONT_BODY_P,44onymous_ +V 600,2000,CONT_DIF_N,45onymous_ +V 3000,2000,CONT_DIF_N,46onymous_ +V 4200,9000,CONT_DIF_P,47onymous_ +V 2000,8000,CONT_VIA,48onymous_ +V 4200,8000,CONT_DIF_P,49onymous_ +V 600,8000,CONT_DIF_P,50onymous_ +V 600,7000,CONT_DIF_P,51onymous_ +V 1800,600,CONT_BODY_P,54onymous_ +V 4000,7000,CONT_VIA,53onymous_ +V 600,6000,CONT_DIF_P,52onymous_ +V 2000,4000,CONT_VIA,41onymous_ +V 2000,4000,CONT_POLY,40onymous_ +V 1800,3000,CONT_DIF_N,39onymous_ +V 4000,4000,CONT_POLY,38onymous_ +V 2000,3000,CONT_VIA,37onymous_ +V 3000,8000,CONT_DIF_P,36onymous_ +V 3000,7000,CONT_DIF_P,35onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nao3.vbe b/pdks/symbolic/nrflib/cells/rf_dec_nao3.vbe new file mode 100644 index 000000000..6f76808b0 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nao3.vbe @@ -0,0 +1,21 @@ +ENTITY rf_dec_nao3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nao3; + +ARCHITECTURE VBE OF rf_dec_nao3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nao3" + SEVERITY WARNING; + + nq <= not(i2 and (i1 or i0)); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nbuf.ap b/pdks/symbolic/nrflib/cells/rf_dec_nbuf.ap new file mode 100644 index 000000000..9743119c2 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nbuf.ap @@ -0,0 +1,80 @@ +V ALLIANCE : 6 +H rf_dec_nbuf,P,22/4/2016,100 +A 0,0,11000,10000 +S 10000,2000,10000,8000,300,i,UP,CALU1 +S 1850,2000,4150,2000,600,nq,RIGHT,CALU2 +S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,11000,600,1200,vss,RIGHT,CALU1 +S 1800,2000,4200,2000,300,0nonymous_,RIGHT,ALU1 +S 1800,5000,4200,5000,300,1nonymous_,RIGHT,ALU1 +S 1200,4000,10000,4000,600,2nonymous_,RIGHT,POLY +S 3000,6000,3000,9000,300,3nonymous_,UP,ALU1 +S 5400,5700,5400,9300,600,4nonymous_,UP,PDIF +S 1800,2000,1800,8000,300,36onymous_,UP,ALU1 +S -600,7800,11600,7800,6000,35onymous_,RIGHT,NWELL +S 6800,280,6800,3320,600,34onymous_,UP,PTIE +S 6800,5680,6800,9720,600,33onymous_,UP,NTIE +S 6800,6000,6800,9400,300,32onymous_,UP,ALU1 +S 6800,600,6800,3000,300,31onymous_,UP,ALU1 +S 3000,5700,3000,9300,600,30onymous_,UP,PDIF +S 600,5700,600,9300,600,29onymous_,UP,PDIF +S 600,1000,600,2000,300,28onymous_,UP,ALU1 +S 600,6000,600,9000,300,27onymous_,UP,ALU1 +S 3600,5500,3600,9500,200,26onymous_,UP,PTRANS +S 4200,5700,4200,9300,600,25onymous_,UP,PDIF +S 2400,5500,2400,9500,200,24onymous_,UP,PTRANS +S 1200,5500,1200,9500,200,23onymous_,UP,PTRANS +S 1800,5700,1800,9300,600,22onymous_,UP,PDIF +S 3600,500,3600,2500,200,21onymous_,UP,NTRANS +S 4800,500,4800,2500,200,20onymous_,UP,NTRANS +S 1200,500,1200,2500,200,19onymous_,UP,NTRANS +S 2400,500,2400,2500,200,18onymous_,UP,NTRANS +S 3000,700,3000,2300,600,17onymous_,UP,NDIF +S 5400,1000,5400,2000,300,6nonymous_,UP,ALU1 +S 5400,700,5400,2300,600,5nonymous_,UP,NDIF +S 5400,6000,5400,9000,300,7nonymous_,UP,ALU1 +S 4200,2000,4200,8000,300,8nonymous_,UP,ALU1 +S 4800,2800,4800,5200,200,9nonymous_,UP,POLY +S 3600,2800,3600,5200,200,10onymous_,UP,POLY +S 2400,2800,2400,5200,200,11onymous_,UP,POLY +S 1200,2800,1200,5200,200,12onymous_,UP,POLY +S 4800,5500,4800,9500,200,13onymous_,UP,PTRANS +S 1800,700,1800,2300,600,14onymous_,UP,NDIF +S 600,700,600,2300,600,15onymous_,UP,NDIF +S 4200,700,4200,2300,600,16onymous_,UP,NDIF +V 600,9000,CONT_DIF_P,57onymous_ +V 600,2000,CONT_DIF_N,58onymous_ +V 600,1000,CONT_DIF_N,59onymous_ +V 600,6000,CONT_DIF_P,60onymous_ +V 600,7000,CONT_DIF_P,61onymous_ +V 600,8000,CONT_DIF_P,62onymous_ +V 3000,9000,CONT_DIF_P,63onymous_ +V 3000,1000,CONT_DIF_N,64onymous_ +V 6800,9300,CONT_BODY_N,65onymous_ +V 6800,8000,CONT_BODY_N,66onymous_ +V 6800,6000,CONT_BODY_N,68onymous_ +V 6800,7000,CONT_BODY_N,67onymous_ +V 1800,8000,CONT_DIF_P,56onymous_ +V 1800,6000,CONT_DIF_P,55onymous_ +V 1800,7000,CONT_DIF_P,54onymous_ +V 4200,6000,CONT_DIF_P,53onymous_ +V 4200,7000,CONT_DIF_P,52onymous_ +V 4200,8000,CONT_DIF_P,51onymous_ +V 4200,2000,CONT_DIF_N,50onymous_ +V 1800,2000,CONT_DIF_N,49onymous_ +V 5400,2000,CONT_DIF_N,48onymous_ +V 5400,1000,CONT_DIF_N,47onymous_ +V 5400,8000,CONT_DIF_P,46onymous_ +V 5400,6000,CONT_DIF_P,45onymous_ +V 5400,7000,CONT_DIF_P,44onymous_ +V 5400,9000,CONT_DIF_P,43onymous_ +V 3000,6000,CONT_DIF_P,42onymous_ +V 3000,7000,CONT_DIF_P,41onymous_ +V 3000,8000,CONT_DIF_P,40onymous_ +V 10000,4000,CONT_POLY,39onymous_ +V 4000,2000,CONT_VIA,38onymous_ +V 2000,2000,CONT_VIA,37onymous_ +V 6800,2000,CONT_BODY_P,69onymous_ +V 6800,600,CONT_BODY_P,70onymous_ +V 6800,3000,CONT_BODY_P,71onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nbuf.vbe b/pdks/symbolic/nrflib/cells/rf_dec_nbuf.vbe new file mode 100644 index 000000000..336421b04 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nbuf.vbe @@ -0,0 +1,19 @@ +ENTITY rf_dec_nbuf IS +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nbuf; + +ARCHITECTURE VBE OF rf_dec_nbuf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nbuf" + SEVERITY WARNING; + + nq <= not i; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nor3.ap b/pdks/symbolic/nrflib/cells/rf_dec_nor3.ap new file mode 100644 index 000000000..2ae305fee --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nor3.ap @@ -0,0 +1,64 @@ +V ALLIANCE : 6 +H rf_dec_nor3,P,22/4/2016,100 +A 0,0,5000,10000 +S 1850,3000,3150,3000,600,nq,RIGHT,CALU2 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 2000,4000,3000,4000,300,0nonymous_,RIGHT,ALU1 +S 4400,900,4400,2300,600,1nonymous_,UP,NDIF +S 4000,2000,4000,3000,300,2nonymous_,UP,ALU1 +S 3000,2000,3000,3000,300,3nonymous_,UP,ALU1 +S 3600,3000,4200,3000,600,4nonymous_,RIGHT,POLY +S 2400,2800,2400,5200,200,31onymous_,UP,POLY +S 2000,4000,2400,4000,600,30onymous_,RIGHT,POLY +S 1800,5700,1800,9300,600,29onymous_,UP,PDIF +S 3000,5700,3000,9300,600,28onymous_,UP,PDIF +S 2400,5500,2400,9500,200,27onymous_,UP,PTRANS +S 1600,8000,2000,8000,300,26onymous_,RIGHT,ALU1 +S 1600,5000,1600,8000,300,25onymous_,UP,ALU1 +S 1200,5000,1800,5000,600,24onymous_,RIGHT,POLY +S 1200,2800,1200,5200,200,23onymous_,UP,POLY +S 1200,5500,1200,9500,200,22onymous_,UP,PTRANS +S 600,5700,600,9300,600,21onymous_,UP,PDIF +S 600,3000,3000,3000,300,20onymous_,RIGHT,ALU1 +S 600,2000,600,8000,300,19onymous_,UP,ALU1 +S 3000,1700,3000,2300,600,14onymous_,UP,NDIF +S 4200,900,4200,2300,600,13onymous_,UP,NDIF +S 600,1700,600,2300,600,12onymous_,UP,NDIF +S 4200,5700,4200,9300,600,11onymous_,UP,PDIF +S 1200,1500,1200,2500,200,10onymous_,UP,NTRANS +S 3600,1500,3600,2500,200,9nonymous_,UP,NTRANS +S 2400,1500,2400,2500,200,8nonymous_,UP,NTRANS +S 3600,5500,3600,9500,200,7nonymous_,UP,PTRANS +S -600,7800,5600,7800,6000,6nonymous_,RIGHT,NWELL +S 4200,6000,4200,9000,300,5nonymous_,UP,ALU1 +S 3600,2800,3600,5200,200,15onymous_,UP,POLY +S 1800,1700,1800,2300,600,16onymous_,UP,NDIF +S 1800,600,1800,2000,300,17onymous_,UP,ALU1 +S 280,700,3320,700,600,18onymous_,RIGHT,PTIE +S 2850,2000,4150,2000,600,i2,RIGHT,CALU2 +S 850,4000,2150,4000,600,i1,RIGHT,CALU2 +S 1850,8000,3150,8000,600,i0,RIGHT,CALU2 +V 4000,3000,CONT_POLY,34onymous_ +V 2000,3000,CONT_VIA,33onymous_ +V 4000,2000,CONT_VIA,32onymous_ +V 600,2000,CONT_DIF_N,41onymous_ +V 600,600,CONT_BODY_P,42onymous_ +V 3000,600,CONT_BODY_P,43onymous_ +V 4200,1000,CONT_DIF_N,44onymous_ +V 2000,4000,CONT_VIA,45onymous_ +V 2000,4000,CONT_POLY,46onymous_ +V 3000,3000,CONT_VIA,47onymous_ +V 1800,2000,CONT_DIF_N,48onymous_ +V 1800,600,CONT_BODY_P,49onymous_ +V 600,6000,CONT_DIF_P,50onymous_ +V 1600,5000,CONT_POLY,53onymous_ +V 600,8000,CONT_DIF_P,52onymous_ +V 600,7000,CONT_DIF_P,51onymous_ +V 3000,2000,CONT_DIF_N,40onymous_ +V 4200,9000,CONT_DIF_P,39onymous_ +V 2000,8000,CONT_VIA,38onymous_ +V 4200,8000,CONT_DIF_P,37onymous_ +V 4200,7000,CONT_DIF_P,36onymous_ +V 4200,6000,CONT_DIF_P,35onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_dec_nor3.vbe b/pdks/symbolic/nrflib/cells/rf_dec_nor3.vbe new file mode 100644 index 000000000..a13eb4b1e --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_dec_nor3.vbe @@ -0,0 +1,21 @@ +ENTITY rf_dec_nor3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_dec_nor3; + +ARCHITECTURE VBE OF rf_dec_nor3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_dec_nor3" + SEVERITY WARNING; + + nq <= not(i0 or i1 or i2); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_buf.ap b/pdks/symbolic/nrflib/cells/rf_fifo_buf.ap new file mode 100644 index 000000000..17e092d34 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_buf.ap @@ -0,0 +1,228 @@ +V ALLIANCE : 6 +H rf_fifo_buf,P,22/4/2016,100 +A 0,0,10000,20000 +S 3400,8000,4600,8000,300,4nonymous_,RIGHT,ALU1 +S 2000,17000,3000,17000,300,3nonymous_,RIGHT,ALU1 +S 7000,16000,8000,16000,300,2nonymous_,RIGHT,ALU1 +S 6000,15000,7000,15000,300,1nonymous_,RIGHT,ALU1 +S 9000,4600,9000,5000,300,0nonymous_,UP,ALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 0,19400,10000,19400,1200,vss,RIGHT,CALU1 +S 0,10600,10000,10600,1200,vdd,RIGHT,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 5000,16700,5000,18300,600,68onymous_,UP,NDIF +S 4600,4000,6000,4000,300,27onymous_,RIGHT,ALU1 +S 1600,4000,2000,4000,600,26onymous_,RIGHT,POLY +S 6000,4000,6400,4000,600,25onymous_,RIGHT,POLY +S 4000,2200,5200,2200,200,24onymous_,RIGHT,POLY +S 2800,7800,4000,7800,200,23onymous_,RIGHT,POLY +S 5600,14800,5600,16200,200,22onymous_,UP,POLY +S 9400,3800,9400,5200,200,21onymous_,UP,POLY +S 9000,5000,9400,5000,600,20onymous_,RIGHT,POLY +S 8000,2000,8800,2000,300,19onymous_,RIGHT,ALU1 +S 8000,3000,8800,3000,300,18onymous_,RIGHT,ALU1 +S 8000,6000,8800,6000,300,17onymous_,RIGHT,ALU1 +S 8000,7000,8800,7000,300,16onymous_,RIGHT,ALU1 +S 8000,8000,8600,8000,300,15onymous_,RIGHT,ALU1 +S 1000,17700,1000,19300,600,14onymous_,UP,NDIF +S 1600,17500,1600,19500,200,13onymous_,UP,NTRANS +S 1600,14800,1600,17200,200,12onymous_,UP,POLY +S 2200,18000,2200,19000,300,11onymous_,UP,ALU1 +S 2200,17700,2200,19300,600,10onymous_,UP,NDIF +S 1600,17000,2000,17000,600,9nonymous_,RIGHT,POLY +S 5600,15000,6000,15000,600,8nonymous_,RIGHT,POLY +S 3400,2000,4600,2000,300,5nonymous_,RIGHT,ALU1 +S -600,12200,11400,12200,6000,6nonymous_,RIGHT,NWELL +S -600,7800,11400,7800,6000,7nonymous_,RIGHT,NWELL +S 6400,3800,6400,5200,200,28onymous_,UP,POLY +S 5200,3800,5200,5200,200,29onymous_,UP,POLY +S 4600,3000,4600,7000,300,30onymous_,UP,ALU1 +S 5200,2500,5200,3500,200,31onymous_,UP,NTRANS +S 4600,2700,4600,3300,600,32onymous_,UP,NDIF +S 4600,5700,4600,7300,600,33onymous_,UP,PDIF +S 1000,1700,1000,3300,600,54onymous_,UP,NDIF +S 8800,1700,8800,3300,600,55onymous_,UP,NDIF +S 1600,5500,1600,9500,200,56onymous_,UP,PTRANS +S 1000,5700,1000,9300,600,57onymous_,UP,PDIF +S 2200,5700,2200,9300,600,58onymous_,UP,PDIF +S 9400,5500,9400,9500,200,59onymous_,UP,PTRANS +S 10000,5700,10000,9300,600,60onymous_,UP,PDIF +S 8800,5700,8800,9300,600,61onymous_,UP,PDIF +S 2200,6000,2200,9000,300,62onymous_,UP,ALU1 +S 10000,6000,10000,9000,300,63onymous_,UP,ALU1 +S 5600,16500,5600,18500,200,67onymous_,UP,NTRANS +S 6200,10700,6200,14300,600,66onymous_,UP,PDIF +S 5000,10700,5000,14300,600,65onymous_,UP,PDIF +S 5600,10500,5600,14500,200,64onymous_,UP,PTRANS +S 9400,1500,9400,3500,200,53onymous_,UP,NTRANS +S 1600,1500,1600,3500,200,52onymous_,UP,NTRANS +S 10000,1000,10000,3000,300,51onymous_,UP,ALU1 +S 2200,1000,2200,3000,300,50onymous_,UP,ALU1 +S 2800,5500,2800,7500,200,49onymous_,UP,PTRANS +S 3400,5700,3400,7300,600,48onymous_,UP,PDIF +S 2000,4000,3400,4000,300,47onymous_,RIGHT,ALU1 +S 1600,3800,1600,5200,200,46onymous_,UP,POLY +S 3400,2700,3400,3300,600,45onymous_,UP,NDIF +S 2800,2500,2800,3500,200,44onymous_,UP,NTRANS +S 3400,3000,3400,7000,300,43onymous_,UP,ALU1 +S 2800,3800,2800,5200,200,42onymous_,UP,POLY +S 5800,1000,5800,3000,300,41onymous_,UP,ALU1 +S 5800,6000,5800,9000,300,40onymous_,UP,ALU1 +S 7000,1700,7000,3300,600,39onymous_,UP,NDIF +S 6400,1500,6400,3500,200,38onymous_,UP,NTRANS +S 7000,5700,7000,9300,600,37onymous_,UP,PDIF +S 6400,5500,6400,9500,200,36onymous_,UP,PTRANS +S 5800,5700,5800,9300,600,35onymous_,UP,PDIF +S 5200,5500,5200,7500,200,34onymous_,UP,PTRANS +S 8000,2000,8000,8000,300,xreset,UP,CALU1 +S 5000,12000,5000,18000,300,nw,UP,CALU1 +S 1000,12000,1000,18000,300,nr,UP,CALU1 +S 7000,2000,7000,8000,300,xckm,UP,CALU1 +S 1000,2000,1000,8000,300,xcks,UP,CALU1 +S 6850,16000,8150,16000,600,reset,RIGHT,CALU2 +S 5850,15000,7150,15000,600,w,RIGHT,CALU2 +S 1850,17000,3150,17000,600,r,RIGHT,CALU2 +S 3850,2000,5150,2000,600,ckm,RIGHT,CALU2 +S 2850,8000,4150,8000,600,cks,RIGHT,CALU2 +S 9000,4850,9000,12150,400,nreset,UP,CALU3 +S 9000,12000,9000,18000,300,nreset,UP,CALU1 +S 6200,17000,6200,19000,300,69onymous_,UP,ALU1 +S 6200,11000,6200,14000,300,70onymous_,UP,ALU1 +S 1000,10700,1000,14300,600,71onymous_,UP,PDIF +S 1600,10500,1600,14500,200,72onymous_,UP,PTRANS +S 2200,10700,2200,14300,600,73onymous_,UP,PDIF +S 2200,11000,2200,14000,300,74onymous_,UP,ALU1 +S 10000,11000,10000,14000,300,75onymous_,UP,ALU1 +S 8800,10700,8800,14300,600,76onymous_,UP,PDIF +S 10000,10700,10000,14300,600,77onymous_,UP,PDIF +S 9400,10500,9400,14500,200,78onymous_,UP,PTRANS +S 9400,14800,9400,17200,200,79onymous_,UP,POLY +S 8000,16000,9400,16000,600,80onymous_,RIGHT,POLY +S 8800,16700,8800,18300,600,81onymous_,UP,NDIF +S 9400,16500,9400,18500,200,82onymous_,UP,NTRANS +S 10000,16700,10000,19100,600,83onymous_,UP,NDIF +S 10000,17000,10000,19000,300,84onymous_,UP,ALU1 +S 9050,5000,9950,5000,300,85onymous_,RIGHT,TALU2 +S 9050,12000,9950,12000,300,86onymous_,RIGHT,TALU2 +S 8850,5000,10150,5000,600,87onymous_,RIGHT,ALU2 +S 8850,12000,10150,12000,600,88onymous_,RIGHT,ALU2 +S 2200,1700,2200,3300,600,89onymous_,UP,NDIF +S 5800,1700,5800,3300,600,90onymous_,UP,NDIF +S 10000,1700,10000,3300,600,91onymous_,UP,NDIF +S 680,700,9120,700,600,92onymous_,RIGHT,PTIE +S 3600,9080,3600,14119,600,93onymous_,UP,NTIE +S 7400,10480,7400,14319,600,94onymous_,UP,NTIE +S 7400,10800,7400,14000,300,95onymous_,UP,ALU1 +S 3600,10800,3600,14000,300,96onymous_,UP,ALU1 +S 6200,16700,6200,18300,600,97onymous_,UP,NDIF +S 3079,19400,9120,19400,600,98onymous_,RIGHT,PTIE +V 4000,2000,CONT_VIA,99onymous_ +V 4000,8000,CONT_VIA,100nymous_ +V 2000,17000,CONT_VIA,101nymous_ +V 8000,16000,CONT_VIA,102nymous_ +V 6000,15000,CONT_VIA,103nymous_ +V 7400,19400,CONT_BODY_P,104nymous_ +V 6000,15000,CONT_POLY,105nymous_ +V 2000,17000,CONT_POLY,106nymous_ +V 2200,19000,CONT_DIF_N,107nymous_ +V 2200,18000,CONT_DIF_N,108nymous_ +V 1000,18000,CONT_DIF_N,109nymous_ +V 9000,12000,CONT_VIA,110nymous_ +V 9000,12000,CONT_VIA2,111nymous_ +V 9000,5000,CONT_POLY,112nymous_ +V 9000,5000,CONT_VIA,113nymous_ +V 1000,7000,CONT_DIF_P,147nymous_ +V 2200,9000,CONT_DIF_P,146nymous_ +V 2200,8000,CONT_DIF_P,145nymous_ +V 10000,3000,CONT_DIF_N,144nymous_ +V 8800,2000,CONT_DIF_N,143nymous_ +V 8800,3000,CONT_DIF_N,142nymous_ +V 1000,2000,CONT_DIF_N,141nymous_ +V 1000,3000,CONT_DIF_N,140nymous_ +V 2200,2000,CONT_DIF_N,139nymous_ +V 2200,3000,CONT_DIF_N,138nymous_ +V 3400,6000,CONT_DIF_P,137nymous_ +V 2000,4000,CONT_POLY,136nymous_ +V 3400,3000,CONT_DIF_N,135nymous_ +V 7000,2000,CONT_DIF_N,134nymous_ +V 7000,3000,CONT_DIF_N,133nymous_ +V 5800,3000,CONT_DIF_N,132nymous_ +V 5800,2000,CONT_DIF_N,131nymous_ +V 5800,6000,CONT_DIF_P,130nymous_ +V 7000,7000,CONT_DIF_P,129nymous_ +V 4600,6000,CONT_DIF_P,128nymous_ +V 7000,8000,CONT_DIF_P,127nymous_ +V 5800,7000,CONT_DIF_P,126nymous_ +V 5800,8000,CONT_DIF_P,125nymous_ +V 5800,9000,CONT_DIF_P,124nymous_ +V 4600,7000,CONT_DIF_P,123nymous_ +V 4600,3000,CONT_DIF_N,122nymous_ +V 6000,4000,CONT_POLY,121nymous_ +V 4000,8000,CONT_POLY,120nymous_ +V 4000,2000,CONT_POLY,119nymous_ +V 3400,600,CONT_BODY_P,118nymous_ +V 2200,19000,CONT_DIF_N,177nymous_ +V 2200,11000,CONT_DIF_P,176nymous_ +V 2200,12000,CONT_DIF_P,175nymous_ +V 2200,13000,CONT_DIF_P,174nymous_ +V 2200,14000,CONT_DIF_P,173nymous_ +V 1000,12000,CONT_DIF_P,172nymous_ +V 1000,13000,CONT_DIF_P,171nymous_ +V 1000,14000,CONT_DIF_P,170nymous_ +V 6200,17000,CONT_DIF_N,169nymous_ +V 6200,18000,CONT_DIF_N,168nymous_ +V 5000,17000,CONT_DIF_N,167nymous_ +V 5000,18000,CONT_DIF_N,166nymous_ +V 6200,11000,CONT_DIF_P,165nymous_ +V 5000,14000,CONT_DIF_P,164nymous_ +V 5000,13000,CONT_DIF_P,163nymous_ +V 5000,12000,CONT_DIF_P,162nymous_ +V 6200,14000,CONT_DIF_P,161nymous_ +V 6200,13000,CONT_DIF_P,160nymous_ +V 6200,12000,CONT_DIF_P,159nymous_ +V 8800,8000,CONT_DIF_P,158nymous_ +V 8800,7000,CONT_DIF_P,157nymous_ +V 8800,6000,CONT_DIF_P,156nymous_ +V 10000,6000,CONT_DIF_P,155nymous_ +V 10000,7000,CONT_DIF_P,154nymous_ +V 10000,8000,CONT_DIF_P,153nymous_ +V 10000,9000,CONT_DIF_P,152nymous_ +V 2200,7000,CONT_DIF_P,151nymous_ +V 3400,7000,CONT_DIF_P,150nymous_ +V 2200,6000,CONT_DIF_P,149nymous_ +V 1000,8000,CONT_DIF_P,148nymous_ +V 9000,5000,CONT_VIA2,114nymous_ +V 8800,600,CONT_BODY_P,115nymous_ +V 7000,600,CONT_BODY_P,116nymous_ +V 4600,600,CONT_BODY_P,117nymous_ +V 10000,11000,CONT_DIF_P,178nymous_ +V 10000,12000,CONT_DIF_P,179nymous_ +V 10000,13000,CONT_DIF_P,180nymous_ +V 10000,14000,CONT_DIF_P,181nymous_ +V 8800,12000,CONT_DIF_P,182nymous_ +V 10000,2000,CONT_DIF_N,183nymous_ +V 8000,16000,CONT_POLY,184nymous_ +V 8800,13000,CONT_DIF_P,185nymous_ +V 8800,14000,CONT_DIF_P,186nymous_ +V 10000,17000,CONT_DIF_N,187nymous_ +V 10000,18000,CONT_DIF_N,188nymous_ +V 8800,17000,CONT_DIF_N,189nymous_ +V 8800,18000,CONT_DIF_N,190nymous_ +V 10000,19000,CONT_DIF_N,191nymous_ +V 8800,19400,CONT_BODY_P,192nymous_ +V 2200,600,CONT_BODY_P,193nymous_ +V 5800,600,CONT_BODY_P,194nymous_ +V 1000,600,CONT_BODY_P,195nymous_ +V 3600,14000,CONT_BODY_N,196nymous_ +V 3600,13000,CONT_BODY_N,197nymous_ +V 3600,12000,CONT_BODY_N,198nymous_ +V 3600,10800,CONT_BODY_N,199nymous_ +V 3600,9300,CONT_BODY_N,200nymous_ +V 7400,10800,CONT_BODY_N,201nymous_ +V 7400,12000,CONT_BODY_N,202nymous_ +V 7400,13000,CONT_BODY_N,203nymous_ +V 7400,14000,CONT_BODY_N,204nymous_ +V 6200,19400,CONT_BODY_P,205nymous_ +V 3400,19400,CONT_BODY_P,206nymous_ +V 4800,19400,CONT_BODY_P,207nymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_buf.vbe b/pdks/symbolic/nrflib/cells/rf_fifo_buf.vbe new file mode 100644 index 000000000..2d64fed85 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_buf.vbe @@ -0,0 +1,33 @@ +ENTITY rf_fifo_buf IS +PORT ( + cks : in BIT; + ckm : in BIT; + r : in BIT; + w : in BIT; + reset : in BIT; + xcks : out BIT; + xckm : out BIT; + nr : out BIT; + nw : out BIT; + xreset : out BIT; + nreset : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_buf; + +ARCHITECTURE VBE OF rf_fifo_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_clock" + SEVERITY WARNING; + + xcks <= cks; + xckm <= ckm; + nr <= not r; + nw <= not w; + xreset <= reset; + nreset <= not reset; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_clock.ap b/pdks/symbolic/nrflib/cells/rf_fifo_clock.ap new file mode 100644 index 000000000..9c0d3a074 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_clock.ap @@ -0,0 +1,271 @@ +V ALLIANCE : 6 +H rf_fifo_clock,P,22/4/2016,100 +A 0,0,10000,20000 +S 10000,17700,10000,18100,600,4nonymous_,UP,NDIF +S 0,10600,10000,10600,1200,vdd,RIGHT,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 0,19400,10000,19400,1200,vss,RIGHT,CALU1 +S 4880,19400,9120,19400,600,0nonymous_,RIGHT,PTIE +S 7600,17700,7600,18100,600,1nonymous_,UP,NDIF +S 7600,17700,7600,18100,600,2nonymous_,UP,NDIF +S 6400,17700,6400,18100,600,3nonymous_,UP,NDIF +S 6400,12000,7000,12000,400,33onymous_,RIGHT,ALU1 +S 8000,12000,8000,17000,300,32onymous_,UP,ALU1 +S 4600,13800,4600,17200,200,31onymous_,UP,POLY +S 4000,14000,4600,14000,600,30onymous_,RIGHT,POLY +S 9000,16000,9400,16000,600,29onymous_,RIGHT,POLY +S 9000,7850,9000,16150,400,28onymous_,UP,ALU3 +S 5800,13800,5800,17200,200,27onymous_,UP,POLY +S 800,10700,800,13300,600,26onymous_,UP,PDIF +S 1400,10500,1400,13500,200,25onymous_,UP,PTRANS +S 8000,17000,8800,17000,300,24onymous_,RIGHT,ALU1 +S 800,11000,800,12000,300,23onymous_,UP,ALU1 +S 7000,17000,8200,17000,600,22onymous_,RIGHT,POLY +S 6050,16000,8950,16000,300,21onymous_,RIGHT,TALU2 +S 9000,8050,9000,15950,300,20onymous_,UP,TALU3 +S 7000,5050,7000,11950,300,19onymous_,UP,TALU3 +S 8000,4050,8000,11950,300,18onymous_,UP,TALU3 +S 6050,4000,7950,4000,300,17onymous_,RIGHT,TALU2 +S 1800,1700,1800,3300,600,16onymous_,UP,NDIF +S 6200,1700,6200,3300,600,15onymous_,UP,NDIF +S 10000,1700,10000,2300,600,14onymous_,UP,NDIF +S 7400,8400,7400,9600,300,5nonymous_,UP,ALU1 +S 600,8400,600,9600,300,6nonymous_,UP,ALU1 +S 7400,8080,7400,9920,600,7nonymous_,UP,NTIE +S 600,8080,600,9920,600,8nonymous_,UP,NTIE +S 7080,9600,9120,9600,600,9nonymous_,RIGHT,NTIE +S 1200,5500,1200,7500,200,10onymous_,UP,PTRANS +S 600,5700,600,7300,600,11onymous_,UP,PDIF +S 600,2000,600,7000,300,12onymous_,UP,ALU1 +S 280,700,9120,700,600,13onymous_,RIGHT,PTIE +S 6400,12000,6400,15000,300,34onymous_,UP,ALU1 +S 8800,17700,8800,18100,600,55onymous_,UP,NDIF +S 5600,3800,5600,5200,200,56onymous_,UP,POLY +S 7400,1700,7400,2300,600,57onymous_,UP,NDIF +S 5000,1700,5000,3300,600,58onymous_,UP,NDIF +S 5600,1500,5600,3500,200,59onymous_,UP,NTRANS +S 6800,1500,6800,2500,200,60onymous_,UP,NTRANS +S 6200,5700,6200,9300,600,61onymous_,UP,PDIF +S 5600,5500,5600,9500,200,62onymous_,UP,PTRANS +S 5000,5700,5000,9300,600,63onymous_,UP,PDIF +S 10000,6700,10000,9300,600,64onymous_,UP,PDIF +S 1800,1000,1800,3000,300,68onymous_,UP,ALU1 +S 10000,1000,10000,2000,300,67onymous_,UP,ALU1 +S 10000,7000,10000,9000,300,66onymous_,UP,ALU1 +S 6200,6000,6200,9000,300,65onymous_,UP,ALU1 +S 8200,17500,8200,18300,200,54onymous_,UP,NTRANS +S 9400,17500,9400,18300,200,53onymous_,UP,NTRANS +S 5200,17700,5200,18100,600,52onymous_,UP,NDIF +S 5800,17500,5800,18300,200,51onymous_,UP,NTRANS +S 4600,17500,4600,18300,200,50onymous_,UP,NTRANS +S 9400,10500,9400,13500,200,49onymous_,UP,PTRANS +S 4600,10500,4600,13500,200,48onymous_,UP,PTRANS +S 8800,10700,8800,13300,600,47onymous_,UP,PDIF +S 8200,10500,8200,13500,200,46onymous_,UP,PTRANS +S 7600,10700,7600,13300,600,45onymous_,UP,PDIF +S 5800,10500,5800,13500,200,44onymous_,UP,PTRANS +S 5200,10700,5200,13300,600,43onymous_,UP,PDIF +S 6400,10700,6400,13300,600,42onymous_,UP,PDIF +S 10000,10700,10000,13300,600,41onymous_,UP,PDIF +S 3600,11000,3600,13000,300,40onymous_,UP,ALU1 +S 3600,10700,3600,13300,1400,39onymous_,UP,PDIF +S 10000,11000,10000,13000,300,38onymous_,UP,ALU1 +S 9400,13800,9400,17200,200,37onymous_,UP,POLY +S 8200,13800,8200,17200,200,36onymous_,UP,POLY +S 7600,13000,8000,13000,300,35onymous_,RIGHT,ALU1 +S 1800,5700,1800,9300,600,76onymous_,UP,PDIF +S 3000,5700,3000,9300,600,75onymous_,UP,PDIF +S 2400,5500,2400,9500,200,74onymous_,UP,PTRANS +S 4000,7850,4000,17150,400,ckm,UP,CALU3 +S 6000,7850,6000,16150,400,cks,UP,CALU3 +S 2400,3800,2400,5200,200,69onymous_,UP,POLY +S 3000,1700,3000,3300,600,70onymous_,UP,NDIF +S 600,1700,600,2300,600,71onymous_,UP,NDIF +S 1200,1500,1200,2500,200,72onymous_,UP,NTRANS +S 2400,1500,2400,3500,200,73onymous_,UP,NTRANS +S 6400,18000,6400,19000,300,77onymous_,UP,ALU1 +S 10000,18000,10000,19000,300,78onymous_,UP,ALU1 +S 6800,5500,6800,7500,200,79onymous_,UP,PTRANS +S 7400,5700,7400,7300,600,80onymous_,UP,PDIF +S 6800,2800,6800,5200,200,81onymous_,UP,POLY +S 7400,2000,7400,7000,300,82onymous_,UP,ALU1 +S 3000,2000,3000,8000,300,83onymous_,UP,ALU1 +S 5000,2000,5000,8000,300,84onymous_,UP,ALU1 +S 8800,17000,8800,18000,300,85onymous_,UP,ALU1 +S 3800,15000,6400,15000,300,86onymous_,RIGHT,ALU1 +S 1400,13800,1400,16200,200,87onymous_,UP,POLY +S 2600,13800,2600,16200,200,88onymous_,UP,POLY +S 2600,10500,2600,13500,200,89onymous_,UP,PTRANS +S 2000,16700,2000,19300,600,90onymous_,UP,NDIF +S 800,16700,800,19300,600,91onymous_,UP,NDIF +S 1400,16500,1400,19500,200,92onymous_,UP,NTRANS +S 2600,16500,2600,19500,200,93onymous_,UP,NTRANS +S 2000,10700,2000,13300,600,94onymous_,UP,PDIF +S 800,17000,2000,17000,300,95onymous_,RIGHT,ALU1 +S 800,18000,2000,18000,300,96onymous_,RIGHT,ALU1 +S 3600,17000,3600,19000,300,97onymous_,UP,ALU1 +S 3600,17700,3600,18300,600,98onymous_,UP,NDIF +S 3600,16700,3600,19300,1400,99onymous_,UP,NDIF +S 600,4000,2000,4000,300,100nymous_,RIGHT,ALU1 +S 1200,5000,1600,5000,600,101nymous_,RIGHT,POLY +S 2000,4000,2400,4000,600,102nymous_,RIGHT,POLY +S 1600,5000,2000,5000,300,103nymous_,RIGHT,ALU1 +S 1850,5000,7150,5000,600,104nymous_,RIGHT,ALU2 +S 7000,4850,7000,12150,400,105nymous_,UP,ALU3 +S 6000,5000,7400,5000,300,106nymous_,RIGHT,ALU1 +S 5600,5000,6000,5000,600,107nymous_,RIGHT,POLY +S 6400,4000,6800,4000,600,108nymous_,RIGHT,POLY +S 5850,4000,8150,4000,600,109nymous_,RIGHT,ALU2 +S 6000,4000,6400,4000,300,110nymous_,RIGHT,ALU1 +S 8000,3850,8000,12150,400,111nymous_,UP,ALU3 +S 4850,8000,6150,8000,600,112nymous_,RIGHT,ALU2 +S 2600,15000,3800,15000,600,113nymous_,RIGHT,POLY +S 3050,8000,8950,8000,300,149nymous_,RIGHT,TALU2 +S 4050,17000,6950,17000,300,148nymous_,RIGHT,TALU2 +S 8850,5000,10150,5000,600,147nymous_,RIGHT,ALU2 +S 7850,8000,9150,8000,600,146nymous_,RIGHT,ALU2 +S 6050,12000,8950,12000,300,145nymous_,RIGHT,TALU2 +S 5850,12000,7150,12000,600,144nymous_,RIGHT,ALU2 +S 7850,12000,9150,12000,600,143nymous_,RIGHT,ALU2 +S 6400,3000,6400,4000,300,142nymous_,UP,ALU1 +S 6200,1000,6200,2000,300,141nymous_,UP,ALU1 +S 10000,4000,10000,5000,300,140nymous_,UP,ALU1 +S 1600,5000,1600,6000,300,139nymous_,UP,ALU1 +S 1200,2800,1200,6200,200,138nymous_,UP,POLY +S 1800,7000,1800,9000,300,137nymous_,UP,ALU1 +S 3000,14000,4000,14000,300,136nymous_,RIGHT,ALU1 +S 9000,15000,9000,16000,300,135nymous_,UP,ALU1 +S 6000,16000,7000,16000,300,134nymous_,RIGHT,ALU1 +S 6000,17000,7000,17000,300,133nymous_,RIGHT,ALU1 +S 4800,15000,4800,18000,300,114nymous_,UP,ALU1 +S 4800,18000,5200,18000,300,115nymous_,RIGHT,ALU1 +S 8600,2000,8600,8000,300,116nymous_,UP,ALU1 +S 9200,2800,9200,6200,200,117nymous_,UP,POLY +S 9200,6500,9200,8500,200,118nymous_,UP,PTRANS +S 8600,1700,8600,2300,600,119nymous_,UP,NDIF +S 9200,1500,9200,2500,200,120nymous_,UP,NTRANS +S 8600,6700,8600,8300,600,121nymous_,UP,PDIF +S 8600,8000,9000,8000,300,122nymous_,RIGHT,ALU1 +S 9600,5000,10000,5000,300,123nymous_,RIGHT,ALU1 +S 9200,5000,9800,5000,600,124nymous_,RIGHT,POLY +S 2050,5000,9950,5000,300,125nymous_,RIGHT,TALU2 +S -600,12200,11400,12200,6000,126nymous_,RIGHT,NWELL +S -600,7800,11400,7800,6000,127nymous_,RIGHT,NWELL +S 2850,8000,4150,8000,600,128nymous_,RIGHT,ALU2 +S 3850,17000,7150,17000,600,129nymous_,RIGHT,ALU2 +S 7600,18000,7600,19000,300,130nymous_,UP,ALU1 +S 5850,16000,7150,16000,600,131nymous_,RIGHT,ALU2 +S 7850,16000,9150,16000,600,132nymous_,RIGHT,ALU2 +S 2000,12000,2000,18000,300,ckok,UP,CALU1 +S 1000,13000,1000,16000,300,wok,UP,CALU1 +S 3850,14000,10150,14000,600,ck,RIGHT,CALU2 +S 10000,4850,10000,14150,400,ck,UP,CALU3 +V 7400,8400,CONT_BODY_N,153nymous_ +V 7400,9600,CONT_BODY_N,152nymous_ +V 6400,19400,CONT_BODY_P,151nymous_ +V 7600,19400,CONT_BODY_P,150nymous_ +V 8000,12000,CONT_VIA,177nymous_ +V 7000,12000,CONT_VIA2,176nymous_ +V 7000,12000,CONT_VIA,175nymous_ +V 4000,14000,CONT_POLY,174nymous_ +V 4000,14000,CONT_VIA,173nymous_ +V 10000,14000,CONT_VIA2,172nymous_ +V 9000,16000,CONT_VIA2,171nymous_ +V 9000,16000,CONT_VIA,170nymous_ +V 9000,16000,CONT_POLY,169nymous_ +V 3000,600,CONT_BODY_P,168nymous_ +V 5000,600,CONT_BODY_P,167nymous_ +V 800,12000,CONT_DIF_P,166nymous_ +V 800,11000,CONT_DIF_P,165nymous_ +V 2000,12000,CONT_DIF_P,164nymous_ +V 2000,13000,CONT_DIF_P,163nymous_ +V 7000,17000,CONT_VIA,162nymous_ +V 7000,17000,CONT_POLY,161nymous_ +V 6000,16000,CONT_VIA2,160nymous_ +V 6000,16000,CONT_VIA,159nymous_ +V 6000,16000,CONT_POLY,158nymous_ +V 1800,600,CONT_BODY_P,157nymous_ +V 6200,600,CONT_BODY_P,156nymous_ +V 600,6000,CONT_DIF_P,155nymous_ +V 600,8400,CONT_BODY_N,154nymous_ +V 8000,12000,CONT_VIA2,178nymous_ +V 6400,12000,CONT_DIF_P,179nymous_ +V 7600,13000,CONT_DIF_P,180nymous_ +V 6400,13000,CONT_DIF_P,181nymous_ +V 3600,12000,CONT_DIF_P,182nymous_ +V 3600,13000,CONT_DIF_P,183nymous_ +V 3600,11000,CONT_DIF_P,184nymous_ +V 8800,600,CONT_BODY_P,185nymous_ +V 10000,9000,CONT_DIF_P,186nymous_ +V 10000,2000,CONT_DIF_N,187nymous_ +V 7400,600,CONT_BODY_P,188nymous_ +V 7400,2000,CONT_DIF_N,189nymous_ +V 6200,2000,CONT_DIF_N,190nymous_ +V 5000,2000,CONT_DIF_N,191nymous_ +V 5000,3000,CONT_DIF_N,192nymous_ +V 6200,6000,CONT_DIF_P,193nymous_ +V 6200,7000,CONT_DIF_P,194nymous_ +V 6200,8000,CONT_DIF_P,195nymous_ +V 6200,9000,CONT_DIF_P,196nymous_ +V 5000,8000,CONT_DIF_P,197nymous_ +V 5000,7000,CONT_DIF_P,198nymous_ +V 5000,6000,CONT_DIF_P,199nymous_ +V 10000,7000,CONT_DIF_P,200nymous_ +V 10000,8000,CONT_DIF_P,201nymous_ +V 600,600,CONT_BODY_P,202nymous_ +V 1800,2000,CONT_DIF_N,203nymous_ +V 1800,3000,CONT_DIF_N,204nymous_ +V 3000,2000,CONT_DIF_N,205nymous_ +V 3000,3000,CONT_DIF_N,206nymous_ +V 600,2000,CONT_DIF_N,207nymous_ +V 1800,9000,CONT_DIF_P,208nymous_ +V 1800,7000,CONT_DIF_P,209nymous_ +V 3000,7000,CONT_DIF_P,210nymous_ +V 3000,6000,CONT_DIF_P,211nymous_ +V 3000,8000,CONT_DIF_P,212nymous_ +V 1800,8000,CONT_DIF_P,213nymous_ +V 10000,11000,CONT_DIF_P,214nymous_ +V 10000,12000,CONT_DIF_P,215nymous_ +V 10000,13000,CONT_DIF_P,216nymous_ +V 10000,18000,CONT_DIF_N,217nymous_ +V 8800,18000,CONT_DIF_N,218nymous_ +V 7600,18000,CONT_DIF_N,219nymous_ +V 8800,19400,CONT_BODY_P,220nymous_ +V 5200,19400,CONT_BODY_P,221nymous_ +V 5200,18000,CONT_DIF_N,222nymous_ +V 6400,18000,CONT_DIF_N,223nymous_ +V 7400,7000,CONT_DIF_P,224nymous_ +V 7400,6000,CONT_DIF_P,225nymous_ +V 8800,9600,CONT_BODY_N,226nymous_ +V 3800,15000,CONT_POLY,227nymous_ +V 800,18000,CONT_DIF_N,228nymous_ +V 800,17000,CONT_DIF_N,229nymous_ +V 600,9600,CONT_BODY_N,230nymous_ +V 1000,15000,CONT_POLY,231nymous_ +V 3600,18000,CONT_DIF_N,232nymous_ +V 3600,19000,CONT_DIF_N,233nymous_ +V 3600,17000,CONT_DIF_N,234nymous_ +V 2000,4000,CONT_POLY,235nymous_ +V 1600,5000,CONT_POLY,236nymous_ +V 2000,5000,CONT_VIA,237nymous_ +V 7000,5000,CONT_VIA2,238nymous_ +V 6000,5000,CONT_POLY,239nymous_ +V 6400,4000,CONT_POLY,240nymous_ +V 8000,4000,CONT_VIA2,241nymous_ +V 6000,4000,CONT_VIA,242nymous_ +V 5000,8000,CONT_VIA,243nymous_ +V 6000,8000,CONT_VIA2,244nymous_ +V 3000,8000,CONT_VIA,245nymous_ +V 600,7000,CONT_DIF_P,246nymous_ +V 8600,2000,CONT_DIF_N,247nymous_ +V 8600,8000,CONT_DIF_P,248nymous_ +V 8600,7000,CONT_DIF_P,249nymous_ +V 9000,8000,CONT_VIA2,250nymous_ +V 9000,8000,CONT_VIA,251nymous_ +V 10000,5000,CONT_VIA2,252nymous_ +V 10000,5000,CONT_VIA,253nymous_ +V 9600,5000,CONT_POLY,254nymous_ +V 4000,8000,CONT_VIA2,255nymous_ +V 4000,17000,CONT_VIA2,256nymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_clock.vbe b/pdks/symbolic/nrflib/cells/rf_fifo_clock.vbe new file mode 100644 index 000000000..27c0acf09 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_clock.vbe @@ -0,0 +1,39 @@ +ENTITY rf_fifo_clock IS +PORT ( + ck : in BIT; + wok : in BIT; + cks : inout BIT; + ckm : inout BIT; + ckok : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_clock; + +ARCHITECTURE VBE OF rf_fifo_clock IS + + SIGNAL nck : BIT; + SIGNAL sck : BIT; + SIGNAL mck : BIT; + SIGNAL nsck : BIT; + SIGNAL nmck : BIT; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_clock" + SEVERITY WARNING; + + nck <= not ck; + sck <= nck nor ckm; + mck <= ck nor cks; + nmck <= not mck; + nsck <= not sck; + cks <= not nsck; + ckm <= not nmck; + ckok <= mck nand wok; + +-- cks <= not(ck); +-- ckm <= ck; +-- ckok <= ckm nand wok; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_empty.ap b/pdks/symbolic/nrflib/cells/rf_fifo_empty.ap new file mode 100644 index 000000000..31167433e --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_empty.ap @@ -0,0 +1,108 @@ +V ALLIANCE : 6 +H rf_fifo_empty,P,22/4/2016,100 +A 0,0,10000,10000 +S 1800,6700,1800,8300,600,4nonymous_,UP,PDIF +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 280,9300,3320,9300,600,0nonymous_,RIGHT,NTIE +S 3000,8000,3000,9400,300,1nonymous_,UP,ALU1 +S 600,8000,600,9400,300,2nonymous_,UP,ALU1 +S 800,5000,800,7000,300,3nonymous_,UP,ALU1 +S 6600,2700,6600,3300,600,38onymous_,UP,NDIF +S 5400,2700,5400,3300,600,37onymous_,UP,NDIF +S 7200,2500,7200,3500,200,36onymous_,UP,NTRANS +S 6600,6700,6600,7300,600,35onymous_,UP,PDIF +S 7200,6500,7200,7500,200,34onymous_,UP,PTRANS +S 1000,3000,1000,4000,300,13onymous_,UP,ALU1 +S 3000,2000,4400,2000,300,12onymous_,RIGHT,ALU1 +S 1480,700,6920,700,600,11onymous_,RIGHT,PTIE +S 2000,6000,3000,6000,300,10onymous_,RIGHT,ALU1 +S 800,7000,1800,7000,300,9nonymous_,RIGHT,ALU1 +S 3000,6700,3000,8300,600,8nonymous_,UP,PDIF +S 600,6700,600,8300,600,7nonymous_,UP,PDIF +S 1200,6500,1200,8500,200,6nonymous_,UP,PTRANS +S 2400,6500,2400,8500,200,5nonymous_,UP,PTRANS +S 3000,4000,3000,5000,300,14onymous_,UP,ALU1 +S 1800,6000,2400,6000,600,15onymous_,RIGHT,POLY +S 4400,2200,6000,2200,200,16onymous_,RIGHT,POLY +S 4200,2700,4200,3300,600,17onymous_,UP,NDIF +S 3600,2500,3600,3500,200,18onymous_,UP,NTRANS +S 3000,4000,3600,4000,600,19onymous_,RIGHT,POLY +S 9000,6700,9000,9300,600,30onymous_,UP,PDIF +S 3600,5000,3600,8400,200,31onymous_,UP,POLY +S 3600,5000,6400,5000,200,32onymous_,RIGHT,POLY +S -600,7800,10600,7800,6000,33onymous_,RIGHT,NWELL +S 9000,700,9000,3300,600,29onymous_,UP,NDIF +S 8400,500,8400,3500,200,28onymous_,UP,NTRANS +S 8400,6500,8400,9500,200,27onymous_,UP,PTRANS +S 8400,3800,8400,6200,200,26onymous_,UP,POLY +S 4200,6000,7200,6000,200,25onymous_,RIGHT,POLY +S 5300,8000,5700,8000,1000,24onymous_,RIGHT,PTRANS +S 3900,8000,4300,8000,1000,23onymous_,RIGHT,PTRANS +S 7800,6700,7800,9300,600,22onymous_,UP,PDIF +S 7800,700,7800,3300,600,21onymous_,UP,NDIF +S 7200,3800,7200,6200,200,20onymous_,UP,POLY +S 6000,2500,6000,3500,200,39onymous_,UP,NTRANS +S 6200,8000,9000,8000,300,40onymous_,RIGHT,ALU1 +S 5400,2000,8000,2000,300,41onymous_,RIGHT,ALU1 +S 8000,2000,8000,4000,300,42onymous_,UP,ALU1 +S 2000,3000,3000,3000,300,43onymous_,RIGHT,ALU1 +S 2000,3000,2000,5000,300,44onymous_,UP,ALU1 +S 800,5000,2000,5000,300,45onymous_,RIGHT,ALU1 +S 1200,3800,1200,7200,200,46onymous_,UP,POLY +S 1200,1500,1200,3500,200,47onymous_,UP,NTRANS +S 600,700,600,3300,600,48onymous_,UP,NDIF +S 2400,3800,2400,7200,200,49onymous_,UP,POLY +S 2400,1500,2400,3500,200,50onymous_,UP,NTRANS +S 1800,1700,1800,3300,600,51onymous_,UP,NDIF +S 3000,1700,3000,3300,600,52onymous_,UP,NDIF +S 600,1000,600,2000,300,53onymous_,UP,ALU1 +S 2850,4000,7150,4000,600,ckm,RIGHT,CALU2 +S 850,3000,7150,3000,600,nreset,RIGHT,CALU2 +S 3850,2000,7150,2000,600,cks,RIGHT,CALU2 +S 4200,3000,4200,7000,300,y,UP,ALU1 +S 6600,3000,6600,7000,300,z,UP,ALU1 +S 5400,2000,5400,7000,300,t,UP,ALU1 +S 1850,6000,7150,6000,600,emptynext,RIGHT,CALU2 +S 9000,2000,9000,8000,300,empty,UP,CALU1 +V 1800,9300,CONT_BODY_N,54onymous_ +V 3000,9300,CONT_BODY_N,55onymous_ +V 600,9300,CONT_BODY_N,56onymous_ +V 3000,8000,CONT_DIF_P,57onymous_ +V 1800,7000,CONT_DIF_P,58onymous_ +V 600,8000,CONT_DIF_P,59onymous_ +V 5400,600,CONT_BODY_P,60onymous_ +V 3000,600,CONT_BODY_P,61onymous_ +V 1800,600,CONT_BODY_P,62onymous_ +V 9000,2000,CONT_DIF_N,63onymous_ +V 9000,8000,CONT_DIF_P,64onymous_ +V 2000,6000,CONT_VIA,65onymous_ +V 3000,4000,CONT_VIA,66onymous_ +V 1000,3000,CONT_VIA,67onymous_ +V 4000,2000,CONT_VIA,68onymous_ +V 4200,600,CONT_BODY_P,70onymous_ +V 6600,600,CONT_BODY_P,69onymous_ +V 3000,3000,CONT_DIF_N,71onymous_ +V 4400,2000,CONT_POLY,72onymous_ +V 4200,3000,CONT_DIF_N,73onymous_ +V 600,1000,CONT_DIF_N,74onymous_ +V 4200,7000,CONT_DIF_P,75onymous_ +V 4200,9000,CONT_DIF_P,76onymous_ +V 2000,6000,CONT_POLY,77onymous_ +V 3200,4000,CONT_POLY,78onymous_ +V 7800,1000,CONT_DIF_N,79onymous_ +V 6600,3000,CONT_DIF_N,80onymous_ +V 7800,9000,CONT_DIF_P,81onymous_ +V 6600,7000,CONT_DIF_P,82onymous_ +V 5400,9000,CONT_DIF_P,83onymous_ +V 600,2000,CONT_DIF_N,93onymous_ +V 1000,4000,CONT_POLY,92onymous_ +V 6200,8000,CONT_POLY,91onymous_ +V 4400,6000,CONT_POLY,90onymous_ +V 6400,5000,CONT_POLY,89onymous_ +V 5400,3000,CONT_DIF_N,88onymous_ +V 8000,4000,CONT_POLY,87onymous_ +V 9000,3000,CONT_DIF_N,86onymous_ +V 9000,7000,CONT_DIF_P,85onymous_ +V 5400,7000,CONT_DIF_P,84onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_empty.vbe b/pdks/symbolic/nrflib/cells/rf_fifo_empty.vbe new file mode 100644 index 000000000..f0cea2dde --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_empty.vbe @@ -0,0 +1,34 @@ +ENTITY rf_fifo_empty IS +PORT ( + ckm : in BIT; + nreset : in BIT; + emptynext : in BIT; + cks : in BIT; + empty : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_empty; + +ARCHITECTURE VBE OF rf_fifo_empty IS + SIGNAL latchm : REG_BIT REGISTER; + SIGNAL latchs : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_empty" + SEVERITY WARNING; + + label0 : BLOCK (ckm = '1') + BEGIN + latchm <= GUARDED (emptynext nand nreset); + END BLOCK label0; + + label1 : BLOCK (cks = '1') + BEGIN + latchs <= GUARDED (not latchm); + END BLOCK label1; + + empty <= (not latchs); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_full.ap b/pdks/symbolic/nrflib/cells/rf_fifo_full.ap new file mode 100644 index 000000000..abe8d7cc4 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_full.ap @@ -0,0 +1,114 @@ +V ALLIANCE : 6 +H rf_fifo_full,P,22/4/2016,100 +A 0,0,10000,10000 +S 6000,8000,6600,8000,1000,4nonymous_,RIGHT,POLY +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 8400,4200,8400,5200,200,0nonymous_,UP,POLY +S 9000,5700,9000,8300,600,1nonymous_,UP,PDIF +S 8400,5500,8400,8500,200,2nonymous_,UP,PTRANS +S 7800,5700,7800,8300,600,3nonymous_,UP,PDIF +S 1800,700,1800,2100,600,38onymous_,UP,NDIF +S 3000,700,3000,1300,600,37onymous_,UP,NDIF +S 3600,2500,3600,3500,200,36onymous_,UP,NTRANS +S 3000,2700,3000,3300,600,35onymous_,UP,NDIF +S 4200,2700,4200,3300,600,34onymous_,UP,NDIF +S 4400,2200,6000,2200,200,33onymous_,RIGHT,POLY +S 4200,5400,7200,5400,200,12onymous_,RIGHT,POLY +S 6600,5900,6600,6500,600,11onymous_,UP,PDIF +S 7200,5700,7200,6700,200,10onymous_,UP,PTRANS +S 7200,3800,7200,5400,200,9nonymous_,UP,POLY +S 6400,7000,9000,7000,300,8nonymous_,RIGHT,ALU1 +S 6280,9300,9320,9300,600,7nonymous_,RIGHT,NTIE +S 7800,8000,7800,9400,300,6nonymous_,UP,ALU1 +S 6400,7000,6400,8000,300,5nonymous_,UP,ALU1 +S 3600,4800,3600,8400,200,13onymous_,UP,POLY +S 3600,4800,6400,4800,200,14onymous_,RIGHT,POLY +S 3879,700,6920,700,600,15onymous_,RIGHT,PTIE +S 600,4000,600,8000,300,16onymous_,UP,ALU1 +S 3000,6000,3000,9000,300,17onymous_,UP,ALU1 +S 3000,5700,3000,9300,600,18onymous_,UP,PDIF +S 600,3000,1000,3000,300,29onymous_,RIGHT,ALU1 +S 600,2000,600,3000,300,30onymous_,UP,ALU1 +S 7800,4000,8400,4000,600,31onymous_,RIGHT,POLY +S 3200,4000,3600,4000,600,32onymous_,RIGHT,POLY +S 600,4000,2000,4000,300,28onymous_,RIGHT,ALU1 +S 2000,2000,2000,4000,300,27onymous_,UP,ALU1 +S 1200,5500,1200,9500,200,26onymous_,UP,PTRANS +S 1200,1800,1200,5200,200,25onymous_,UP,POLY +S 2400,1800,2400,5200,200,24onymous_,UP,POLY +S 600,5700,600,9300,600,23onymous_,UP,PDIF +S 2000,5000,2000,6000,300,22onymous_,UP,ALU1 +S 2000,5000,2400,5000,600,21onymous_,RIGHT,POLY +S 1800,5700,1800,9300,600,20onymous_,UP,PDIF +S 2400,5500,2400,9500,200,19onymous_,UP,PTRANS +S 2400,500,2400,1500,200,39onymous_,UP,NTRANS +S 1200,500,1200,1500,200,40onymous_,UP,NTRANS +S 600,700,600,1300,600,41onymous_,UP,NDIF +S 7800,700,7800,3300,600,42onymous_,UP,NDIF +S 3900,8000,4300,8000,1000,43onymous_,RIGHT,PTRANS +S 5300,8000,5700,8000,1000,44onymous_,RIGHT,PTRANS +S 8400,500,8400,3500,200,45onymous_,UP,NTRANS +S 9000,700,9000,3300,600,46onymous_,UP,NDIF +S -600,7800,10600,7800,6000,47onymous_,RIGHT,NWELL +S 7200,2500,7200,3500,200,48onymous_,UP,NTRANS +S 5400,2700,5400,3300,600,49onymous_,UP,NDIF +S 6600,2700,6600,3300,600,50onymous_,UP,NDIF +S 6000,2500,6000,3500,200,51onymous_,UP,NTRANS +S 5400,2000,8000,2000,300,52onymous_,RIGHT,ALU1 +S 8000,2000,8000,4000,300,53onymous_,UP,ALU1 +S 2000,3000,3000,3000,300,54onymous_,RIGHT,ALU1 +S 3000,2000,4400,2000,300,55onymous_,RIGHT,ALU1 +S 3000,4000,3000,5000,300,56onymous_,UP,ALU1 +S 2850,4000,7150,4000,600,ckm,RIGHT,CALU2 +S 850,3000,7150,3000,600,reset,RIGHT,CALU2 +S 3850,2000,7150,2000,600,cks,RIGHT,CALU2 +S 4200,3000,4200,7000,300,y,UP,ALU1 +S 5400,2000,5400,7000,300,t,UP,ALU1 +S 6600,3000,6600,6000,300,z,UP,ALU1 +S 1850,5000,7150,5000,600,fullnext,RIGHT,CALU2 +S 9000,2000,9000,8000,300,full,UP,CALU1 +V 6400,8000,CONT_POLY,57onymous_ +V 9000,9300,CONT_BODY_N,58onymous_ +V 7800,9300,CONT_BODY_N,59onymous_ +V 7800,8000,CONT_DIF_P,60onymous_ +V 6600,6000,CONT_DIF_P,61onymous_ +V 4400,5600,CONT_POLY,62onymous_ +V 6400,4600,CONT_POLY,63onymous_ +V 5400,600,CONT_BODY_P,64onymous_ +V 3000,8000,CONT_DIF_P,65onymous_ +V 3000,7000,CONT_DIF_P,66onymous_ +V 3000,6000,CONT_DIF_P,67onymous_ +V 600,6000,CONT_DIF_P,68onymous_ +V 2000,5000,CONT_POLY,70onymous_ +V 600,8000,CONT_DIF_P,69onymous_ +V 2000,5000,CONT_VIA,71onymous_ +V 4200,600,CONT_BODY_P,72onymous_ +V 1800,2000,CONT_DIF_N,73onymous_ +V 600,7000,CONT_DIF_P,74onymous_ +V 6600,600,CONT_BODY_P,75onymous_ +V 3200,4000,CONT_POLY,76onymous_ +V 4400,2000,CONT_POLY,77onymous_ +V 1000,3000,CONT_POLY,78onymous_ +V 4200,3000,CONT_DIF_N,79onymous_ +V 3000,3000,CONT_DIF_N,80onymous_ +V 3000,1000,CONT_DIF_N,81onymous_ +V 600,1000,CONT_DIF_N,82onymous_ +V 3000,9000,CONT_DIF_P,83onymous_ +V 4200,7000,CONT_DIF_P,84onymous_ +V 4200,9000,CONT_DIF_P,85onymous_ +V 7800,1000,CONT_DIF_N,86onymous_ +V 6600,3000,CONT_DIF_N,87onymous_ +V 5400,9000,CONT_DIF_P,88onymous_ +V 5400,7000,CONT_DIF_P,89onymous_ +V 9000,2000,CONT_DIF_N,99onymous_ +V 9000,8000,CONT_DIF_P,98onymous_ +V 3000,4000,CONT_VIA,97onymous_ +V 1000,3000,CONT_VIA,96onymous_ +V 4000,2000,CONT_VIA,95onymous_ +V 6600,9300,CONT_BODY_N,94onymous_ +V 5400,3000,CONT_DIF_N,93onymous_ +V 8000,4000,CONT_POLY,92onymous_ +V 9000,3000,CONT_DIF_N,91onymous_ +V 9000,7000,CONT_DIF_P,90onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_full.vbe b/pdks/symbolic/nrflib/cells/rf_fifo_full.vbe new file mode 100644 index 000000000..69a6c28cf --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_full.vbe @@ -0,0 +1,34 @@ +ENTITY rf_fifo_full IS +PORT ( + ckm : in BIT; + reset : in BIT; + fullnext : in BIT; + cks : in BIT; + full : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_full; + +ARCHITECTURE VBE OF rf_fifo_full IS + SIGNAL latchm : REG_BIT REGISTER; + SIGNAL latchs : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_full" + SEVERITY WARNING; + + label0 : BLOCK (ckm = '1') + BEGIN + latchm <= GUARDED (fullnext nor reset); + END BLOCK label0; + + label1 : BLOCK (cks = '1') + BEGIN + latchs <= GUARDED (not latchm); + END BLOCK label1; + + full <= (not latchs); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_inc.ap b/pdks/symbolic/nrflib/cells/rf_fifo_inc.ap new file mode 100644 index 000000000..45f3b517a --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_inc.ap @@ -0,0 +1,102 @@ +V ALLIANCE : 6 +H rf_fifo_inc,P,22/4/2016,100 +A 0,0,10000,10000 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 880,700,6120,700,600,0nonymous_,RIGHT,PTIE +S 3279,9300,6120,9300,600,1nonymous_,RIGHT,NTIE +S 4000,4000,4000,5000,300,2nonymous_,UP,ALU1 +S 3000,4000,3000,5000,300,3nonymous_,UP,ALU1 +S 5200,2000,5200,6000,300,4nonymous_,UP,ALU1 +S 600,3800,600,5200,200,38onymous_,UP,POLY +S 1800,3800,1800,5200,200,37onymous_,UP,POLY +S 5400,3800,5400,5200,200,36onymous_,UP,POLY +S 3000,3800,3000,5200,200,35onymous_,UP,POLY +S 600,5500,600,9500,200,14onymous_,UP,PTRANS +S -600,7800,10600,7800,6000,13onymous_,RIGHT,NWELL +S 7000,8700,7000,9300,600,12onymous_,UP,PDIF +S 7600,8500,7600,9500,200,11onymous_,UP,PTRANS +S 4800,5700,4800,7300,600,10onymous_,UP,PDIF +S 6000,5700,6000,7300,600,9nonymous_,UP,PDIF +S 0,5700,0,9300,600,8nonymous_,UP,PDIF +S 8200,700,8200,2100,600,7nonymous_,UP,NDIF +S 7000,700,7000,1300,600,6nonymous_,UP,NDIF +S 7000,8000,7600,8000,600,5nonymous_,RIGHT,POLY +S 2400,5700,2400,9300,600,15onymous_,UP,PDIF +S 1200,5700,1200,9300,600,16onymous_,UP,PDIF +S 1800,5500,1800,9500,200,17onymous_,UP,PTRANS +S 3000,5500,3000,7500,200,18onymous_,UP,PTRANS +S 3600,5700,3600,7300,600,19onymous_,UP,PDIF +S 5400,5500,5400,7500,200,20onymous_,UP,PTRANS +S 2400,1700,2400,3300,600,31onymous_,UP,NDIF +S 7600,1800,7600,8200,200,32onymous_,UP,POLY +S 3800,3800,3800,5200,200,33onymous_,UP,POLY +S 4600,3800,6800,3800,200,34onymous_,RIGHT,POLY +S 1200,1700,1200,3300,600,30onymous_,UP,NDIF +S 0,700,0,3300,600,29onymous_,UP,NDIF +S 5200,1700,5200,3300,600,28onymous_,UP,NDIF +S 4600,1500,4600,3500,200,27onymous_,UP,NTRANS +S 3800,1500,3800,3500,200,26onymous_,UP,NTRANS +S 7600,500,7600,1500,200,25onymous_,UP,NTRANS +S 3000,1500,3000,3500,200,24onymous_,UP,NTRANS +S 600,1500,600,3500,200,23onymous_,UP,NTRANS +S 1800,1500,1800,3500,200,22onymous_,UP,NTRANS +S 4200,5500,4200,7500,200,21onymous_,UP,PTRANS +S 0,6000,0,9000,300,39onymous_,UP,ALU1 +S 0,1000,0,3000,300,40onymous_,UP,ALU1 +S 2400,1000,2400,3000,300,41onymous_,UP,ALU1 +S 4800,7000,4800,9400,300,42onymous_,UP,ALU1 +S 2400,7000,2400,9000,300,43onymous_,UP,ALU1 +S 600,5000,2000,5000,600,44onymous_,RIGHT,POLY +S 8200,7900,8200,9300,600,45onymous_,UP,PDIF +S 8200,2000,8200,8000,300,46onymous_,UP,ALU1 +S 6800,3800,8200,3800,300,47onymous_,RIGHT,ALU1 +S 6000,8000,7200,8000,300,48onymous_,RIGHT,ALU1 +S 2000,5000,2000,6000,300,49onymous_,UP,ALU1 +S 2000,6000,6000,6000,300,50onymous_,RIGHT,ALU1 +S 1850,4000,3150,4000,600,ckm,RIGHT,CALU2 +S 3850,5000,5150,5000,600,nreset,RIGHT,CALU2 +S 4850,8000,6150,8000,600,nval,RIGHT,CALU2 +S 1000,2000,1000,8000,300,inc,UP,CALU1 +V 2400,600,CONT_BODY_P,51onymous_ +V 1200,600,CONT_BODY_P,52onymous_ +V 5800,600,CONT_BODY_P,53onymous_ +V 5800,9300,CONT_BODY_N,54onymous_ +V 4000,5000,CONT_VIA,55onymous_ +V 3000,4000,CONT_VIA,56onymous_ +V 7200,8000,CONT_POLY,57onymous_ +V 7000,1000,CONT_DIF_N,58onymous_ +V 8200,2000,CONT_DIF_N,59onymous_ +V 0,8000,CONT_DIF_P,60onymous_ +V 0,7000,CONT_DIF_P,61onymous_ +V 0,9000,CONT_DIF_P,62onymous_ +V 0,6000,CONT_DIF_P,63onymous_ +V 2400,8000,CONT_DIF_P,64onymous_ +V 2400,9000,CONT_DIF_P,65onymous_ +V 6000,6000,CONT_DIF_P,66onymous_ +V 3600,6000,CONT_DIF_P,67onymous_ +V 4800,7000,CONT_DIF_P,68onymous_ +V 2400,7000,CONT_DIF_P,74onymous_ +V 1200,7000,CONT_DIF_P,73onymous_ +V 1200,8000,CONT_DIF_P,72onymous_ +V 3600,9300,CONT_BODY_N,71onymous_ +V 4800,9300,CONT_BODY_N,70onymous_ +V 7000,9000,CONT_DIF_P,69onymous_ +V 2400,3000,CONT_DIF_N,75onymous_ +V 5200,3000,CONT_DIF_N,76onymous_ +V 5200,2000,CONT_DIF_N,77onymous_ +V 0,2000,CONT_DIF_N,78onymous_ +V 0,3000,CONT_DIF_N,79onymous_ +V 0,1000,CONT_DIF_N,80onymous_ +V 1200,2000,CONT_DIF_N,81onymous_ +V 6000,8000,CONT_VIA,91onymous_ +V 8200,8000,CONT_DIF_P,90onymous_ +V 3000,4000,CONT_POLY,89onymous_ +V 2000,5000,CONT_POLY,88onymous_ +V 6800,3800,CONT_POLY,87onymous_ +V 4000,5000,CONT_POLY,86onymous_ +V 3600,600,CONT_BODY_P,85onymous_ +V 4800,600,CONT_BODY_P,84onymous_ +V 2400,2000,CONT_DIF_N,83onymous_ +V 1200,3000,CONT_DIF_N,82onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_inc.vbe b/pdks/symbolic/nrflib/cells/rf_fifo_inc.vbe new file mode 100644 index 000000000..ee01d1c54 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_inc.vbe @@ -0,0 +1,21 @@ +ENTITY rf_fifo_inc IS +PORT ( + ckm : in BIT; + nreset : in BIT; + nval : in BIT; + inc : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_inc; + +ARCHITECTURE VBE OF rf_fifo_inc IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_inc" + SEVERITY WARNING; + + inc <= (not nval) and nreset and ckm; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_nop.ap b/pdks/symbolic/nrflib/cells/rf_fifo_nop.ap new file mode 100644 index 000000000..8d9141750 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_nop.ap @@ -0,0 +1,114 @@ +V ALLIANCE : 6 +H rf_fifo_nop,P,22/4/2016,100 +A 0,0,10000,10000 +S 6000,5700,6000,7300,600,4nonymous_,UP,PDIF +S 0,5700,0,9300,600,3nonymous_,UP,PDIF +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 6000,8000,8200,8000,300,0nonymous_,RIGHT,ALU1 +S 2000,6000,6000,6000,300,1nonymous_,RIGHT,ALU1 +S 2000,5000,2000,6000,300,2nonymous_,UP,ALU1 +S 5400,3800,5400,5200,200,38onymous_,UP,POLY +S 3000,3800,3000,5200,200,37onymous_,UP,POLY +S 4600,3800,6800,3800,200,36onymous_,RIGHT,POLY +S 3800,3800,3800,5200,200,35onymous_,UP,POLY +S 8800,1800,8800,8200,200,34onymous_,UP,POLY +S 7600,1800,7600,8200,200,33onymous_,UP,POLY +S 2400,5700,2400,9300,600,12onymous_,UP,PDIF +S 600,5500,600,9500,200,11onymous_,UP,PTRANS +S -600,7800,10600,7800,6000,10onymous_,RIGHT,NWELL +S 9400,8700,9400,9300,600,9nonymous_,UP,PDIF +S 7000,8700,7000,9300,600,8nonymous_,UP,PDIF +S 7600,8500,7600,9500,200,7nonymous_,UP,PTRANS +S 8800,8500,8800,9500,200,6nonymous_,UP,PTRANS +S 4800,5700,4800,7300,600,5nonymous_,UP,PDIF +S 1200,5700,1200,9300,600,13onymous_,UP,PDIF +S 1800,5500,1800,9500,200,14onymous_,UP,PTRANS +S 3000,5500,3000,7500,200,15onymous_,UP,PTRANS +S 3600,5700,3600,7300,600,16onymous_,UP,PDIF +S 5400,5500,5400,7500,200,17onymous_,UP,PTRANS +S 4200,5500,4200,7500,200,18onymous_,UP,PTRANS +S 8200,700,8200,1300,600,29onymous_,UP,NDIF +S 9400,700,9400,1300,600,30onymous_,UP,NDIF +S 1200,1700,1200,3300,600,31onymous_,UP,NDIF +S 2400,1700,2400,3300,600,32onymous_,UP,NDIF +S 0,700,0,3300,600,28onymous_,UP,NDIF +S 7000,700,7000,2100,600,27onymous_,UP,NDIF +S 5200,1700,5200,3300,600,26onymous_,UP,NDIF +S 4600,1500,4600,3500,200,25onymous_,UP,NTRANS +S 3800,1500,3800,3500,200,24onymous_,UP,NTRANS +S 7600,500,7600,1500,200,23onymous_,UP,NTRANS +S 8800,500,8800,1500,200,22onymous_,UP,NTRANS +S 3000,1500,3000,3500,200,21onymous_,UP,NTRANS +S 600,1500,600,3500,200,20onymous_,UP,NTRANS +S 1800,1500,1800,3500,200,19onymous_,UP,NTRANS +S 1800,3800,1800,5200,200,39onymous_,UP,POLY +S 600,3800,600,5200,200,40onymous_,UP,POLY +S 0,6000,0,9000,300,41onymous_,UP,ALU1 +S 0,1000,0,3000,300,42onymous_,UP,ALU1 +S 2400,1000,2400,3000,300,43onymous_,UP,ALU1 +S 4800,7000,4800,9400,300,44onymous_,UP,ALU1 +S 7600,6000,8200,6000,600,45onymous_,RIGHT,POLY +S 2400,7000,2400,9000,300,46onymous_,UP,ALU1 +S 600,5000,2000,5000,600,47onymous_,RIGHT,POLY +S 8200,7900,8200,9300,600,48onymous_,UP,PDIF +S 5200,2000,5200,6000,300,49onymous_,UP,ALU1 +S 7000,2000,7000,8000,300,50onymous_,UP,ALU1 +S 2000,4000,3000,4000,300,51onymous_,RIGHT,ALU1 +S 3000,5000,4000,5000,300,52onymous_,RIGHT,ALU1 +S 8000,6000,9000,6000,300,53onymous_,RIGHT,ALU1 +S 8000,3000,9000,3000,300,54onymous_,RIGHT,ALU1 +S 880,700,6120,700,600,55onymous_,RIGHT,PTIE +S 3279,9300,6120,9300,600,56onymous_,RIGHT,NTIE +S 1850,4000,3150,4000,600,ckm,RIGHT,CALU2 +S 3850,5000,5150,5000,600,nreset,RIGHT,CALU2 +S 4850,3000,8150,3000,600,rw,RIGHT,CALU2 +S 4850,6000,8150,6000,600,rwok,RIGHT,CALU2 +S 4850,8000,6150,8000,600,nval,RIGHT,CALU2 +S 1000,2000,1000,8000,300,nop,UP,CALU1 +V 6000,8000,CONT_VIA,57onymous_ +V 0,8000,CONT_DIF_P,58onymous_ +V 0,7000,CONT_DIF_P,59onymous_ +V 0,9000,CONT_DIF_P,60onymous_ +V 0,6000,CONT_DIF_P,61onymous_ +V 2400,8000,CONT_DIF_P,62onymous_ +V 2400,9000,CONT_DIF_P,63onymous_ +V 6000,6000,CONT_DIF_P,64onymous_ +V 3600,6000,CONT_DIF_P,65onymous_ +V 4800,7000,CONT_DIF_P,66onymous_ +V 7000,9000,CONT_DIF_P,67onymous_ +V 9400,9000,CONT_DIF_P,68onymous_ +V 1200,7000,CONT_DIF_P,72onymous_ +V 1200,8000,CONT_DIF_P,71onymous_ +V 3600,9300,CONT_BODY_N,70onymous_ +V 4800,9300,CONT_BODY_N,69onymous_ +V 2400,7000,CONT_DIF_P,73onymous_ +V 2400,3000,CONT_DIF_N,74onymous_ +V 5200,3000,CONT_DIF_N,75onymous_ +V 5200,2000,CONT_DIF_N,76onymous_ +V 7000,2000,CONT_DIF_N,77onymous_ +V 9400,1000,CONT_DIF_N,78onymous_ +V 0,2000,CONT_DIF_N,79onymous_ +V 0,3000,CONT_DIF_N,80onymous_ +V 0,1000,CONT_DIF_N,81onymous_ +V 1200,2000,CONT_DIF_N,82onymous_ +V 1200,3000,CONT_DIF_N,83onymous_ +V 2400,2000,CONT_DIF_N,84onymous_ +V 4800,600,CONT_BODY_P,85onymous_ +V 3600,600,CONT_BODY_P,86onymous_ +V 4000,5000,CONT_POLY,87onymous_ +V 6800,3800,CONT_POLY,88onymous_ +V 8000,6000,CONT_POLY,89onymous_ +V 9000,3000,CONT_POLY,90onymous_ +V 2000,5000,CONT_POLY,91onymous_ +V 5800,9300,CONT_BODY_N,101nymous_ +V 2400,600,CONT_BODY_P,100nymous_ +V 5800,600,CONT_BODY_P,99onymous_ +V 1200,600,CONT_BODY_P,98onymous_ +V 8000,3000,CONT_VIA,97onymous_ +V 8000,6000,CONT_VIA,96onymous_ +V 4000,5000,CONT_VIA,95onymous_ +V 3000,4000,CONT_VIA,94onymous_ +V 8200,8000,CONT_DIF_P,93onymous_ +V 3000,4000,CONT_POLY,92onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_nop.vbe b/pdks/symbolic/nrflib/cells/rf_fifo_nop.vbe new file mode 100644 index 000000000..b032c3a1f --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_nop.vbe @@ -0,0 +1,24 @@ +ENTITY rf_fifo_nop IS +PORT ( + ckm : in BIT; + nreset : in BIT; + rw : in BIT; + rwok : in BIT; + nval : inout BIT; + nop : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_nop; + +ARCHITECTURE VBE OF rf_fifo_nop IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_nop" + SEVERITY WARNING; + + nval <= rw nand rwok; + nop <= nval and nreset and ckm; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_ok.ap b/pdks/symbolic/nrflib/cells/rf_fifo_ok.ap new file mode 100644 index 000000000..17cb3c524 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_ok.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H rf_fifo_ok,P,22/4/2016,100 +A 0,0,10000,10000 +S 9000,5000,9000,7000,300,4nonymous_,UP,ALU1 +S 6000,4000,7000,4000,300,3nonymous_,RIGHT,ALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 5000,3000,5000,8000,300,0nonymous_,UP,ALU1 +S 6000,5000,7000,5000,300,1nonymous_,RIGHT,ALU1 +S 3000,3000,4000,3000,300,2nonymous_,RIGHT,ALU1 +S 1200,500,1200,2500,200,38onymous_,UP,NTRANS +S 3000,700,3000,2300,600,37onymous_,UP,NDIF +S 1800,700,1800,2300,600,36onymous_,UP,NDIF +S 600,700,600,2300,600,35onymous_,UP,NDIF +S 2400,2800,2400,5400,200,34onymous_,UP,POLY +S 1200,2800,1200,5400,200,33onymous_,UP,POLY +S 4200,700,4200,2300,600,12onymous_,UP,NDIF +S 4800,5700,4800,9500,200,11onymous_,UP,PTRANS +S 4800,2800,4800,5400,200,10onymous_,UP,POLY +S 4200,5900,4200,9300,600,9nonymous_,UP,PDIF +S 8400,5000,9200,5000,600,8nonymous_,RIGHT,POLY +S 600,6000,600,9000,300,7nonymous_,UP,ALU1 +S 600,1000,600,2000,300,6nonymous_,UP,ALU1 +S 3000,1000,3000,2000,300,5nonymous_,UP,ALU1 +S 4800,500,4800,2500,200,13onymous_,UP,NTRANS +S 5400,5900,5400,9300,600,14onymous_,UP,PDIF +S 6000,2800,6000,5400,200,15onymous_,UP,POLY +S 6000,5700,6000,9500,200,16onymous_,UP,PTRANS +S 5400,700,5400,2300,600,17onymous_,UP,NDIF +S 6000,500,6000,2500,200,18onymous_,UP,NTRANS +S 9000,5900,9000,9300,600,29onymous_,UP,PDIF +S 9000,700,9000,2300,600,30onymous_,UP,NDIF +S -600,7800,10600,7800,6000,31onymous_,RIGHT,NWELL +S 6600,2100,6600,2900,600,32onymous_,UP,NDIF +S 8400,500,8400,2500,200,28onymous_,UP,NTRANS +S 7800,700,7800,2300,600,27onymous_,UP,NDIF +S 8400,5700,8400,9500,200,26onymous_,UP,PTRANS +S 8400,2800,8400,5400,200,25onymous_,UP,POLY +S 7800,5900,7800,9300,600,24onymous_,UP,PDIF +S 7200,500,7200,2500,200,23onymous_,UP,NTRANS +S 6600,700,6600,2300,600,22onymous_,UP,NDIF +S 7200,5700,7200,9500,200,21onymous_,UP,PTRANS +S 7200,2800,7200,5400,200,20onymous_,UP,POLY +S 6600,5900,6600,9300,600,19onymous_,UP,PDIF +S 2400,500,2400,2500,200,39onymous_,UP,NTRANS +S 1800,5900,1800,9300,600,40onymous_,UP,PDIF +S 2400,5700,2400,9500,200,41onymous_,UP,PTRANS +S 3000,5900,3000,9300,600,42onymous_,UP,PDIF +S 600,5900,600,9300,600,43onymous_,UP,PDIF +S 1200,5700,1200,9500,200,44onymous_,UP,PTRANS +S 3800,3000,4800,3000,600,45onymous_,RIGHT,POLY +S 5000,3000,6600,3000,300,46onymous_,RIGHT,ALU1 +S 6600,8000,9000,8000,300,47onymous_,RIGHT,ALU1 +S 5400,2000,9000,2000,300,48onymous_,RIGHT,ALU1 +S 5000,8000,5400,8000,300,49onymous_,RIGHT,ALU1 +S 800,5000,2400,5000,600,50onymous_,RIGHT,POLY +S 1000,4000,1000,5000,300,51onymous_,UP,ALU1 +S 3000,6000,3000,9000,300,52onymous_,UP,ALU1 +S 5850,5000,7150,5000,600,rw,RIGHT,CALU2 +S 7850,7000,9150,7000,600,ripple,RIGHT,CALU2 +S 3850,3000,5150,3000,600,nrw,RIGHT,CALU2 +S 850,4000,6150,4000,600,prev,RIGHT,CALU2 +S 3850,6000,5150,6000,600,nextval,RIGHT,CALU2 +S 2000,2000,2000,8000,300,ok,UP,CALU1 +V 9000,7000,CONT_VIA,53onymous_ +V 6000,4000,CONT_POLY,54onymous_ +V 7000,5000,CONT_VIA,55onymous_ +V 7000,5000,CONT_POLY,56onymous_ +V 4000,3000,CONT_VIA,57onymous_ +V 3000,2000,CONT_DIF_N,58onymous_ +V 600,2000,CONT_DIF_N,59onymous_ +V 600,6000,CONT_DIF_P,60onymous_ +V 600,7000,CONT_DIF_P,61onymous_ +V 600,8000,CONT_DIF_P,62onymous_ +V 3000,7000,CONT_DIF_P,63onymous_ +V 3000,8000,CONT_DIF_P,64onymous_ +V 1800,7000,CONT_DIF_P,65onymous_ +V 1800,6000,CONT_DIF_P,66onymous_ +V 1000,4000,CONT_VIA,67onymous_ +V 9000,5000,CONT_POLY,68onymous_ +V 6600,8000,CONT_DIF_P,72onymous_ +V 5400,8000,CONT_DIF_P,71onymous_ +V 4200,1000,CONT_DIF_N,70onymous_ +V 4200,9000,CONT_DIF_P,69onymous_ +V 7800,9000,CONT_DIF_P,73onymous_ +V 9000,8000,CONT_DIF_P,74onymous_ +V 6600,3000,CONT_DIF_N,75onymous_ +V 9000,2000,CONT_DIF_N,76onymous_ +V 5400,2000,CONT_DIF_N,77onymous_ +V 1800,2000,CONT_DIF_N,78onymous_ +V 3000,6000,CONT_DIF_P,88onymous_ +V 5000,6000,CONT_VIA,87onymous_ +V 1000,5000,CONT_POLY,86onymous_ +V 4000,3000,CONT_POLY,85onymous_ +V 6000,4000,CONT_VIA,84onymous_ +V 3000,1000,CONT_DIF_N,83onymous_ +V 3000,9000,CONT_DIF_P,82onymous_ +V 1800,8000,CONT_DIF_P,81onymous_ +V 600,9000,CONT_DIF_P,80onymous_ +V 600,1000,CONT_DIF_N,79onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_ok.vbe b/pdks/symbolic/nrflib/cells/rf_fifo_ok.vbe new file mode 100644 index 000000000..5537c9045 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_ok.vbe @@ -0,0 +1,24 @@ +ENTITY rf_fifo_ok IS +PORT ( + rw : in BIT; + ripple : in BIT; + nrw : in BIT; + prev : in BIT; + nextval : out BIT; + ok : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_ok; + +ARCHITECTURE VBE OF rf_fifo_ok IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_ok" + SEVERITY WARNING; + + ok <= (not prev); + nextval <= not(((rw and ripple) or prev) and nrw); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_orand4.ap b/pdks/symbolic/nrflib/cells/rf_fifo_orand4.ap new file mode 100644 index 000000000..778dbb970 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_orand4.ap @@ -0,0 +1,80 @@ +V ALLIANCE : 6 +H rf_fifo_orand4,P,22/4/2016,100 +A 0,0,10000,10000 +S 7000,2000,7000,7000,300,a0,UP,CALU1 +S 8000,2000,8000,7000,300,b0,UP,CALU1 +S 4000,3000,4000,6000,300,a1,UP,CALU1 +S 5000,3000,5000,6000,300,b1,UP,CALU1 +S 2000,2000,2000,8000,300,rippleout,UP,CALU1 +S 8200,5900,8200,9300,600,3nonymous_,UP,PDIF +S 5800,5900,5800,9300,600,4nonymous_,UP,PDIF +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 480,9300,2320,9300,600,0nonymous_,RIGHT,NTIE +S 480,700,2320,700,600,1nonymous_,RIGHT,PTIE +S 7600,5700,7600,9500,200,2nonymous_,UP,PTRANS +S 800,1700,800,2700,600,33onymous_,UP,NDIF +S 2000,1700,2000,2700,600,32onymous_,UP,NDIF +S 1400,4000,3000,4000,600,31onymous_,RIGHT,POLY +S 1400,3200,1400,5400,200,30onymous_,UP,POLY +S 800,6000,800,9400,300,29onymous_,UP,ALU1 +S 800,600,800,2000,300,28onymous_,UP,ALU1 +S 4000,2800,4000,5400,200,27onymous_,UP,POLY +S 5200,2800,5200,5400,200,26onymous_,UP,POLY +S 7600,5000,8000,5000,600,25onymous_,RIGHT,POLY +S 7600,2800,7600,5400,200,24onymous_,UP,POLY +S 6400,2800,6400,5400,200,23onymous_,UP,POLY +S 6400,5000,6800,5000,600,22onymous_,RIGHT,POLY +S 3400,700,3400,2300,600,21onymous_,UP,NDIF +S 4600,700,4600,2300,600,20onymous_,UP,NDIF +S 5800,700,5800,2300,600,19onymous_,UP,NDIF +S 8200,700,8200,2300,600,18onymous_,UP,NDIF +S 7000,700,7000,2300,600,17onymous_,UP,NDIF +S 5800,700,5800,2300,600,16onymous_,UP,NDIF +S 7600,500,7600,2500,200,15onymous_,UP,NTRANS +S 6400,500,6400,2500,200,14onymous_,UP,NTRANS +S 6400,5700,6400,9500,200,5nonymous_,UP,PTRANS +S 7000,5900,7000,9300,600,6nonymous_,UP,PDIF +S 5800,5900,5800,9300,600,7nonymous_,UP,PDIF +S 5200,5700,5200,9500,200,8nonymous_,UP,PTRANS +S 4600,5900,4600,9300,600,9nonymous_,UP,PDIF +S 4000,5700,4000,9500,200,10onymous_,UP,PTRANS +S 3400,5900,3400,9300,600,11onymous_,UP,PDIF +S 5200,500,5200,2500,200,12onymous_,UP,NTRANS +S 4000,500,4000,2500,200,13onymous_,UP,NTRANS +S 1400,1500,1400,2900,200,34onymous_,UP,NTRANS +S -600,7800,10600,7800,6000,35onymous_,RIGHT,NWELL +S 2000,5900,2000,8300,600,36onymous_,UP,PDIF +S 800,5900,800,8300,600,37onymous_,UP,PDIF +S 1400,5700,1400,8500,200,38onymous_,UP,PTRANS +S 3000,2000,3000,7000,300,39onymous_,UP,ALU1 +S 3000,7000,4600,7000,300,42onymous_,RIGHT,ALU1 +S 3000,2000,5800,2000,300,41onymous_,RIGHT,ALU1 +S 3400,8000,8200,8000,300,40onymous_,RIGHT,ALU1 +V 800,2000,CONT_DIF_N,60onymous_ +V 800,7000,CONT_DIF_P,61onymous_ +V 800,9300,CONT_BODY_N,62onymous_ +V 2000,9300,CONT_BODY_N,63onymous_ +V 800,6000,CONT_DIF_P,64onymous_ +V 800,8000,CONT_DIF_P,65onymous_ +V 2000,6000,CONT_DIF_P,66onymous_ +V 2000,7000,CONT_DIF_P,67onymous_ +V 2000,8000,CONT_DIF_P,68onymous_ +V 2000,2000,CONT_DIF_N,59onymous_ +V 2000,600,CONT_BODY_P,58onymous_ +V 800,600,CONT_BODY_P,57onymous_ +V 5200,5000,CONT_POLY,56onymous_ +V 8000,5000,CONT_POLY,55onymous_ +V 3400,1000,CONT_DIF_N,54onymous_ +V 5800,2000,CONT_DIF_N,53onymous_ +V 8200,1000,CONT_DIF_N,52onymous_ +V 3400,8000,CONT_DIF_P,51onymous_ +V 5800,8000,CONT_DIF_P,50onymous_ +V 7000,9000,CONT_DIF_P,49onymous_ +V 4600,7000,CONT_DIF_P,48onymous_ +V 5800,8000,CONT_DIF_P,47onymous_ +V 8200,8000,CONT_DIF_P,46onymous_ +V 6800,5000,CONT_POLY,45onymous_ +V 4000,5000,CONT_POLY,44onymous_ +V 3000,4000,CONT_POLY,43onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_orand4.vbe b/pdks/symbolic/nrflib/cells/rf_fifo_orand4.vbe new file mode 100644 index 000000000..fae9974d3 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_orand4.vbe @@ -0,0 +1,22 @@ +ENTITY rf_fifo_orand4 IS +PORT ( + a0 : in BIT; + b0 : in BIT; + a1 : in BIT; + b1 : in BIT; + rippleout : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_orand4; + +ARCHITECTURE VBE OF rf_fifo_orand4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_orand4" + SEVERITY WARNING; + + rippleout <= (a0 and b0) or (a1 and b1); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_orand5.ap b/pdks/symbolic/nrflib/cells/rf_fifo_orand5.ap new file mode 100644 index 000000000..90fc93dfe --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_orand5.ap @@ -0,0 +1,87 @@ +V ALLIANCE : 6 +H rf_fifo_orand5,P,22/4/2016,100 +A 0,0,10000,10000 +S 6200,2800,6200,5400,200,4nonymous_,UP,POLY +S 800,6000,800,9400,300,3nonymous_,UP,ALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 480,700,2320,700,600,0nonymous_,RIGHT,PTIE +S 480,9300,2320,9300,600,1nonymous_,RIGHT,NTIE +S 800,600,800,2000,300,2nonymous_,UP,ALU1 +S 9200,5900,9200,9300,600,38onymous_,UP,PDIF +S 1400,5700,1400,8500,200,37onymous_,UP,PTRANS +S 800,5900,800,8300,600,36onymous_,UP,PDIF +S 2000,5900,2000,8300,600,35onymous_,UP,PDIF +S -600,7800,10600,7800,6000,34onymous_,RIGHT,NWELL +S 3200,5900,3200,9300,600,33onymous_,UP,PDIF +S 8600,5000,9000,5000,600,12onymous_,RIGHT,POLY +S 1400,4000,3000,4000,600,11onymous_,RIGHT,POLY +S 1400,3200,1400,5400,200,10onymous_,UP,POLY +S 7400,2800,7400,5400,200,9nonymous_,UP,POLY +S 8600,2800,8600,5400,200,8nonymous_,UP,POLY +S 7000,5000,7400,5000,600,7nonymous_,RIGHT,POLY +S 3800,2800,3800,5400,200,6nonymous_,UP,POLY +S 5000,2800,5000,5400,200,5nonymous_,UP,POLY +S 5600,700,5600,2300,600,13onymous_,UP,NDIF +S 4400,700,4400,2300,600,14onymous_,UP,NDIF +S 3200,700,3200,2300,600,15onymous_,UP,NDIF +S 9200,700,9200,2300,600,16onymous_,UP,NDIF +S 8000,700,8000,2300,600,17onymous_,UP,NDIF +S 6800,700,6800,2300,600,18onymous_,UP,NDIF +S 5600,5900,5600,9300,600,29onymous_,UP,PDIF +S 5000,5700,5000,9500,200,30onymous_,UP,PTRANS +S 4400,5900,4400,9300,600,31onymous_,UP,PDIF +S 3800,5700,3800,9500,200,32onymous_,UP,PTRANS +S 6200,5700,6200,9500,200,28onymous_,UP,PTRANS +S 6800,5900,6800,9300,600,27onymous_,UP,PDIF +S 3800,500,3800,2500,200,26onymous_,UP,NTRANS +S 5000,500,5000,2500,200,25onymous_,UP,NTRANS +S 6200,500,6200,2500,200,24onymous_,UP,NTRANS +S 7400,500,7400,2500,200,23onymous_,UP,NTRANS +S 8600,500,8600,2500,200,22onymous_,UP,NTRANS +S 1400,1500,1400,2900,200,21onymous_,UP,NTRANS +S 800,1700,800,2700,600,20onymous_,UP,NDIF +S 2000,1700,2000,2700,600,19onymous_,UP,NDIF +S 8600,5700,8600,9500,200,39onymous_,UP,PTRANS +S 8000,5900,8000,9300,600,40onymous_,UP,PDIF +S 7400,5700,7400,9500,200,41onymous_,UP,PTRANS +S 3000,2000,3000,7000,300,42onymous_,UP,ALU1 +S 3200,8000,5600,8000,300,43onymous_,RIGHT,ALU1 +S 6800,8000,9200,8000,300,44onymous_,RIGHT,ALU1 +S 3000,7000,8000,7000,300,45onymous_,RIGHT,ALU1 +S 3000,2000,9200,2000,300,sor,RIGHT,ALU1 +S 7000,3000,7000,6000,300,a0,UP,CALU1 +S 2000,2000,2000,8000,300,rippleout,UP,CALU1 +S 6000,3000,6000,6000,300,ripplein,UP,CALU1 +S 5000,3000,5000,6000,300,b1,UP,CALU1 +S 4000,3000,4000,6000,300,a1,UP,CALU1 +S 9000,3000,9000,6000,300,b0,UP,CALU1 +V 6000,5000,CONT_POLY,46onymous_ +V 5000,5000,CONT_POLY,47onymous_ +V 4000,5000,CONT_POLY,48onymous_ +V 3000,4000,CONT_POLY,49onymous_ +V 9000,5000,CONT_POLY,50onymous_ +V 7000,5000,CONT_POLY,51onymous_ +V 800,600,CONT_BODY_P,52onymous_ +V 2000,600,CONT_BODY_P,53onymous_ +V 9200,2000,CONT_DIF_N,54onymous_ +V 6800,1000,CONT_DIF_N,55onymous_ +V 5600,2000,CONT_DIF_N,56onymous_ +V 3200,1000,CONT_DIF_N,57onymous_ +V 2000,2000,CONT_DIF_N,58onymous_ +V 800,2000,CONT_DIF_N,59onymous_ +V 800,7000,CONT_DIF_P,60onymous_ +V 5600,8000,CONT_DIF_P,61onymous_ +V 3200,8000,CONT_DIF_P,62onymous_ +V 9200,8000,CONT_DIF_P,63onymous_ +V 800,9300,CONT_BODY_N,64onymous_ +V 2000,9300,CONT_BODY_N,65onymous_ +V 4400,9000,CONT_DIF_P,66onymous_ +V 800,6000,CONT_DIF_P,67onymous_ +V 800,8000,CONT_DIF_P,68onymous_ +V 6800,8000,CONT_DIF_P,73onymous_ +V 8000,7000,CONT_DIF_P,72onymous_ +V 2000,6000,CONT_DIF_P,69onymous_ +V 2000,7000,CONT_DIF_P,70onymous_ +V 2000,8000,CONT_DIF_P,71onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_orand5.vbe b/pdks/symbolic/nrflib/cells/rf_fifo_orand5.vbe new file mode 100644 index 000000000..6307f9c8f --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_orand5.vbe @@ -0,0 +1,23 @@ +ENTITY rf_fifo_orand5 IS +PORT ( + a0 : in BIT; + b0 : in BIT; + a1 : in BIT; + b1 : in BIT; + ripplein : in BIT; + rippleout : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_orand5; + +ARCHITECTURE VBE OF rf_fifo_orand5 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_orand5" + SEVERITY WARNING; + + rippleout <= ripplein or (a0 and b0) or (a1 and b1); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_ptreset.ap b/pdks/symbolic/nrflib/cells/rf_fifo_ptreset.ap new file mode 100644 index 000000000..5c4d87d00 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_ptreset.ap @@ -0,0 +1,109 @@ +V ALLIANCE : 6 +H rf_fifo_ptreset,P,23/ 4/2016,100 +A 0,0,10000,10000 +S 4000,3000,4000,6000,400,reset,UP,CALU1 +S 8000,4000,8000,6000,400,nop,UP,CALU1 +S 6000,4000,6000,6000,400,inc,UP,CALU1 +S 2000,4000,2000,8000,400,cks,UP,CALU1 +S 1000,2000,1000,8000,300,y,UP,ALU1 +S 7000,3000,7000,7000,300,x,UP,ALU1 +S 7850,2000,9150,2000,600,pt,RIGHT,CALU2 +S 4850,2000,6150,2000,600,ptm1,RIGHT,CALU2 +S 3000,3000,3000,7000,300,z,UP,ALU1 +S 600,5000,7000,5000,400,48onymous_,RIGHT,POLY +S 1050,7000,7950,7000,300,47onymous_,RIGHT,TALU2 +S 2400,1700,2400,3300,600,46onymous_,UP,NDIF +S 1800,1500,1800,3500,200,45onymous_,UP,NTRANS +S 4800,1700,4800,3300,600,44onymous_,UP,NDIF +S 4200,1500,4200,3500,200,43onymous_,UP,NTRANS +S 7400,1700,7400,3300,1000,42onymous_,UP,NDIF +S 8200,1500,8200,3500,200,41onymous_,UP,NTRANS +S 6000,1700,6000,3300,600,40onymous_,UP,NDIF +S 6600,1500,6600,3500,200,39onymous_,UP,NTRANS +S 10000,7000,10000,9000,300,16onymous_,UP,ALU1 +S 5800,3800,6600,3800,200,17onymous_,RIGHT,POLY +S 9400,3800,9400,6200,200,18onymous_,UP,POLY +S 600,3800,600,6200,200,19onymous_,UP,POLY +S 600,6500,600,9500,200,20onymous_,UP,PTRANS +S 0,6700,0,9300,600,21onymous_,UP,PDIF +S 1200,6700,1200,9300,600,22onymous_,UP,PDIF +S 600,500,600,3500,200,23onymous_,UP,NTRANS +S 0,700,0,3300,600,24onymous_,UP,NDIF +S 1200,700,1200,3300,600,25onymous_,UP,NDIF +S 8800,700,8800,3300,600,29onymous_,UP,NDIF +S 8800,6700,8800,9300,600,28onymous_,UP,PDIF +S 10000,700,10000,3300,600,27onymous_,UP,NDIF +S 10000,6700,10000,9300,600,26onymous_,UP,PDIF +S 0,7000,0,9000,300,15onymous_,UP,ALU1 +S 4800,3000,7200,3000,300,14onymous_,RIGHT,ALU1 +S 7400,2000,7400,3000,300,13onymous_,UP,ALU1 +S 1000,8000,1200,8000,300,12onymous_,RIGHT,ALU1 +S 2080,700,7920,700,600,5nonymous_,RIGHT,PTIE +S 9000,2000,9000,8000,300,6nonymous_,UP,ALU1 +S 5000,2000,6000,2000,300,7nonymous_,RIGHT,ALU1 +S -600,7800,10600,7800,6000,8nonymous_,RIGHT,NWELL +S 0,1000,0,3000,300,9nonymous_,UP,ALU1 +S 10000,1000,10000,3000,300,10onymous_,UP,ALU1 +S 1000,2000,1200,2000,300,11onymous_,RIGHT,ALU1 +S 9400,6500,9400,9500,200,30onymous_,UP,PTRANS +S 9400,500,9400,3500,200,31onymous_,UP,NTRANS +S 6900,8000,7300,8000,1000,32onymous_,RIGHT,PTRANS +S 2700,8000,3100,8000,1000,33onymous_,RIGHT,PTRANS +S 850,7000,8150,7000,600,34onymous_,RIGHT,ALU2 +S 3600,8000,8800,8000,300,35onymous_,RIGHT,ALU1 +S 3600,7600,3600,8400,600,36onymous_,UP,POLY +S 7800,7600,7800,8400,600,37onymous_,UP,POLY +S 8000,7000,8000,8400,600,38onymous_,UP,POLY +S 3600,600,3600,2000,300,2nonymous_,UP,ALU1 +S 3879,9300,6120,9300,600,1nonymous_,RIGHT,NTIE +S 3000,6000,9400,6000,600,0nonymous_,RIGHT,POLY +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 3600,1700,3600,3300,600,3nonymous_,UP,NDIF +S 2400,3000,3000,3000,300,4nonymous_,RIGHT,ALU1 +V 8800,8000,CONT_DIF_P,93onymous_ +V 8800,2000,CONT_DIF_N,94onymous_ +V 7000,9000,CONT_DIF_P,95onymous_ +V 3000,9000,CONT_DIF_P,96onymous_ +V 3600,8000,CONT_POLY,97onymous_ +V 8000,7000,CONT_POLY,98onymous_ +V 1000,7000,CONT_VIA,99onymous_ +V 8000,7000,CONT_VIA,100nymous_ +V 2400,600,CONT_BODY_P,101nymous_ +V 4000,4000,CONT_POLY,102nymous_ +V 1200,2000,CONT_DIF_N,92onymous_ +V 1200,8000,CONT_DIF_P,91onymous_ +V 10000,1000,CONT_DIF_N,90onymous_ +V 0,1000,CONT_DIF_N,89onymous_ +V 10000,9000,CONT_DIF_P,88onymous_ +V 0,9000,CONT_DIF_P,87onymous_ +V 2000,4000,CONT_POLY,86onymous_ +V 6000,4000,CONT_POLY,85onymous_ +V 6000,2000,CONT_DIF_N,84onymous_ +V 7000,5000,CONT_POLY,83onymous_ +V 8000,4000,CONT_POLY,82onymous_ +V 10000,3000,CONT_DIF_N,81onymous_ +V 10000,2000,CONT_DIF_N,80onymous_ +V 0,3000,CONT_DIF_N,79onymous_ +V 0,2000,CONT_DIF_N,78onymous_ +V 10000,7000,CONT_DIF_P,77onymous_ +V 10000,8000,CONT_DIF_P,76onymous_ +V 0,8000,CONT_DIF_P,75onymous_ +V 0,7000,CONT_DIF_P,74onymous_ +V 4800,3000,CONT_DIF_N,73onymous_ +V 3000,7000,CONT_DIF_P,71onymous_ +V 7000,7000,CONT_DIF_P,70onymous_ +V 3000,6000,CONT_POLY,69onymous_ +V 7400,3000,CONT_DIF_N,68onymous_ +V 7400,2000,CONT_DIF_N,67onymous_ +V 4200,9300,CONT_BODY_N,66onymous_ +V 5800,9300,CONT_BODY_N,65onymous_ +V 6000,2000,CONT_VIA,62onymous_ +V 9000,2000,CONT_VIA,61onymous_ +V 2400,3000,CONT_DIF_N,60onymous_ +V 3600,2000,CONT_DIF_N,59onymous_ +V 3600,600,CONT_BODY_P,58onymous_ +V 7600,600,CONT_BODY_P,57onymous_ +V 6200,600,CONT_BODY_P,56onymous_ +V 5000,600,CONT_BODY_P,55onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_ptreset.vbe b/pdks/symbolic/nrflib/cells/rf_fifo_ptreset.vbe new file mode 100644 index 000000000..4be326d40 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_ptreset.vbe @@ -0,0 +1,48 @@ +ENTITY rf_fifo_ptreset IS +PORT ( + nop : in BIT; + inc : in BIT; + cks : in BIT; + reset : in BIT; + ptm1 : in BIT; + pt : inout BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_ptreset; + +ARCHITECTURE VBE OF rf_fifo_ptreset IS + SIGNAL latchm : REG_BIT REGISTER; + SIGNAL latchs : REG_BIT REGISTER; + SIGNAL ckmux : BIT; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_ptreset" + SEVERITY WARNING; + + ckmux <= nop or inc or reset; + + label0 : BLOCK (nop = '1') + BEGIN + latchm <= GUARDED pt; + END BLOCK label0; + + label1 : BLOCK (inc = '1') + BEGIN + latchm <= GUARDED ptm1; + END BLOCK label1; + + label2 : BLOCK (reset = '1') + BEGIN + latchm <= GUARDED '0'; + END BLOCK label2; + + labels : BLOCK (cks = '1') + BEGIN + latchs <= GUARDED (not latchm); + END BLOCK labels; + + pt <= (not latchs); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_ptset.ap b/pdks/symbolic/nrflib/cells/rf_fifo_ptset.ap new file mode 100644 index 000000000..85852c8b7 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_ptset.ap @@ -0,0 +1,116 @@ +V ALLIANCE : 6 +H rf_fifo_ptset,P,22/4/2016,100 +A 0,0,10000,10000 +S 1800,1500,1800,3500,200,4nonymous_,UP,NTRANS +S 2400,1700,2400,3300,600,3nonymous_,UP,NDIF +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 9000,2000,9000,8000,300,0nonymous_,UP,ALU1 +S 5000,2000,6000,2000,300,1nonymous_,RIGHT,ALU1 +S 1050,7000,7950,7000,300,2nonymous_,RIGHT,TALU2 +S 0,6700,0,9300,600,38onymous_,UP,PDIF +S 1200,6700,1200,9300,600,37onymous_,UP,PDIF +S 600,500,600,3500,200,36onymous_,UP,NTRANS +S 0,700,0,3300,600,35onymous_,UP,NDIF +S 1200,700,1200,3300,600,34onymous_,UP,NDIF +S 10000,6700,10000,9300,600,33onymous_,UP,PDIF +S 10000,700,10000,3300,600,32onymous_,UP,NDIF +S 4000,3000,7000,3000,300,12onymous_,RIGHT,ALU1 +S 5600,7000,7000,7000,300,11onymous_,RIGHT,ALU1 +S 4000,3000,4000,6000,300,10onymous_,UP,ALU1 +S 3600,8000,8800,8000,300,9nonymous_,RIGHT,ALU1 +S 6600,1500,6600,3500,200,8nonymous_,UP,NTRANS +S 8200,1500,8200,3500,200,7nonymous_,UP,NTRANS +S 7400,1700,7400,3300,1000,6nonymous_,UP,NDIF +S 6000,1700,6000,3300,600,5nonymous_,UP,NDIF +S 7000,2000,7400,2000,300,13onymous_,RIGHT,ALU1 +S 3600,7600,3600,8400,600,14onymous_,UP,POLY +S 7800,6800,7800,8400,600,15onymous_,UP,POLY +S 1000,8000,1200,8000,300,16onymous_,RIGHT,ALU1 +S 1000,2000,1200,2000,300,17onymous_,RIGHT,ALU1 +S 9400,500,9400,3500,200,28onymous_,UP,NTRANS +S 9400,6500,9400,9500,200,29onymous_,UP,PTRANS +S 8800,700,8800,3300,600,30onymous_,UP,NDIF +S 8800,6700,8800,9300,600,31onymous_,UP,PDIF +S 5000,6500,5000,9500,200,27onymous_,UP,PTRANS +S 5600,6700,5600,9300,600,26onymous_,UP,PDIF +S 4400,6700,4400,9300,600,25onymous_,UP,PDIF +S 3000,5000,9400,5000,200,24onymous_,RIGHT,POLY +S 600,6000,4000,6000,200,23onymous_,RIGHT,POLY +S 2700,8000,3100,8000,1000,22onymous_,RIGHT,PTRANS +S 6900,8000,7300,8000,1000,21onymous_,RIGHT,PTRANS +S 850,7000,8150,7000,600,20onymous_,RIGHT,ALU2 +S 8800,8000,9000,8000,300,19onymous_,RIGHT,ALU1 +S 8800,2000,9000,2000,300,18onymous_,RIGHT,ALU1 +S 600,6500,600,9500,200,39onymous_,UP,PTRANS +S 600,3800,600,6200,200,40onymous_,UP,POLY +S 9400,3800,9400,6200,200,41onymous_,UP,POLY +S 5800,3800,6600,3800,200,42onymous_,RIGHT,POLY +S 10000,7000,10000,9000,300,43onymous_,UP,ALU1 +S 0,7000,0,9000,300,44onymous_,UP,ALU1 +S 2400,2000,3000,2000,300,45onymous_,RIGHT,ALU1 +S 5000,4000,5000,6000,300,46onymous_,UP,ALU1 +S 10000,1000,10000,3000,300,47onymous_,UP,ALU1 +S 0,1000,0,3000,300,48onymous_,UP,ALU1 +S -600,7800,10600,7800,6000,49onymous_,RIGHT,NWELL +S 2000,4000,2000,5000,300,50onymous_,UP,ALU1 +S 8000,4000,8000,5000,300,52onymous_,UP,ALU1 +S 6000,4000,6000,5000,300,53onymous_,UP,ALU1 +S 8000,6000,8000,7000,300,54onymous_,UP,ALU1 +S 2080,700,7920,700,600,55onymous_,RIGHT,PTIE +S 1850,4000,3150,4000,600,cks,RIGHT,CALU2 +S 3850,4000,5150,4000,600,nreset,RIGHT,CALU2 +S 3000,2000,3000,7000,300,z,UP,ALU1 +S 1000,2000,1000,8000,300,y,UP,ALU1 +S 7850,4000,9150,4000,600,nop,RIGHT,CALU2 +S 5850,4000,7150,4000,600,inc,RIGHT,CALU2 +S 4850,2000,6150,2000,600,ptm1,RIGHT,CALU2 +S 7850,2000,9150,2000,600,pt,RIGHT,CALU2 +S 7000,2000,7000,7000,300,x,UP,ALU1 +V 6000,2000,CONT_VIA,56onymous_ +V 9000,2000,CONT_VIA,57onymous_ +V 2400,600,CONT_BODY_P,58onymous_ +V 8000,7000,CONT_POLY,59onymous_ +V 8000,7000,CONT_VIA,60onymous_ +V 1000,7000,CONT_VIA,61onymous_ +V 7000,9000,CONT_DIF_P,62onymous_ +V 3000,9000,CONT_DIF_P,63onymous_ +V 3600,8000,CONT_POLY,64onymous_ +V 4000,6000,CONT_POLY,65onymous_ +V 5000,6000,CONT_POLY,66onymous_ +V 3000,5000,CONT_POLY,67onymous_ +V 5600,7000,CONT_DIF_P,68onymous_ +V 4400,9000,CONT_DIF_P,69onymous_ +V 8800,2000,CONT_DIF_N,70onymous_ +V 8800,8000,CONT_DIF_P,71onymous_ +V 1200,2000,CONT_DIF_N,72onymous_ +V 1200,8000,CONT_DIF_P,73onymous_ +V 2400,2000,CONT_DIF_N,74onymous_ +V 10000,1000,CONT_DIF_N,75onymous_ +V 0,1000,CONT_DIF_N,76onymous_ +V 10000,9000,CONT_DIF_P,77onymous_ +V 0,9000,CONT_DIF_P,78onymous_ +V 2000,4000,CONT_POLY,79onymous_ +V 6000,4000,CONT_POLY,80onymous_ +V 6000,2000,CONT_DIF_N,81onymous_ +V 8000,4000,CONT_POLY,82onymous_ +V 10000,3000,CONT_DIF_N,83onymous_ +V 10000,2000,CONT_DIF_N,84onymous_ +V 0,3000,CONT_DIF_N,85onymous_ +V 0,2000,CONT_DIF_N,86onymous_ +V 10000,7000,CONT_DIF_P,87onymous_ +V 10000,8000,CONT_DIF_P,88onymous_ +V 0,8000,CONT_DIF_P,89onymous_ +V 0,7000,CONT_DIF_P,90onymous_ +V 3600,600,CONT_BODY_P,101nymous_ +V 6400,600,CONT_BODY_P,100nymous_ +V 5000,600,CONT_BODY_P,99onymous_ +V 7600,600,CONT_BODY_P,98onymous_ +V 8000,4000,CONT_VIA,97onymous_ +V 6000,4000,CONT_VIA,96onymous_ +V 5000,4000,CONT_VIA,95onymous_ +V 7400,2000,CONT_DIF_N,94onymous_ +V 7000,7000,CONT_DIF_P,93onymous_ +V 3000,7000,CONT_DIF_P,92onymous_ +V 2000,4000,CONT_VIA,91onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_fifo_ptset.vbe b/pdks/symbolic/nrflib/cells/rf_fifo_ptset.vbe new file mode 100644 index 000000000..8a3c84651 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_fifo_ptset.vbe @@ -0,0 +1,48 @@ +ENTITY rf_fifo_ptset IS +PORT ( + nop : in BIT; + inc : in BIT; + cks : in BIT; + nreset : in BIT; + ptm1 : in BIT; + pt : inout BIT; + vdd : in BIT; + vss : in BIT +); +END rf_fifo_ptset; + +ARCHITECTURE VBE OF rf_fifo_ptset IS + SIGNAL latchm : REG_BIT REGISTER; + SIGNAL latchs : REG_BIT REGISTER; + SIGNAL ckmux : BIT; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_fifo_ptset" + SEVERITY WARNING; + + ckmux <= nop or inc or (not nreset); + + label0 : BLOCK (nop = '1') + BEGIN + latchm <= GUARDED pt ; + END BLOCK label0; + + label1 : BLOCK (inc = '1') + BEGIN + latchm <= GUARDED ptm1 ; + END BLOCK label1; + + label2 : BLOCK (nreset = '0') + BEGIN + latchm <= GUARDED '1' ; + END BLOCK label2; + + labels : BLOCK (cks = '1') + BEGIN + latchs <= GUARDED (not latchm); + END BLOCK labels; + + pt <= (not latchs); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_inmux_buf_2.ap b/pdks/symbolic/nrflib/cells/rf_inmux_buf_2.ap new file mode 100644 index 000000000..7e647bbb2 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_inmux_buf_2.ap @@ -0,0 +1,211 @@ +V ALLIANCE : 6 +H rf_inmux_buf_2,P,22/4/2016,100 +A 0,0,9000,20000 +S 6600,11000,6600,14000,300,4nonymous_,UP,ALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,10600,9000,10600,1200,vdd,RIGHT,CALU1 +S 0,19400,9000,19400,1200,vss,RIGHT,CALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 9000,18000,9000,19000,300,0nonymous_,UP,ALU1 +S 8000,15000,10000,15000,3600,1nonymous_,RIGHT,NWELL +S 1200,16000,3000,16000,600,2nonymous_,RIGHT,POLY +S 600,18000,600,19000,300,3nonymous_,UP,ALU1 +S -600,7800,10000,7800,6000,33onymous_,RIGHT,NWELL +S -600,12200,10000,12200,6000,32onymous_,RIGHT,NWELL +S 8400,500,8400,2300,200,31onymous_,UP,NTRANS +S 7200,500,7200,2300,200,30onymous_,UP,NTRANS +S 6000,500,6000,2300,200,29onymous_,UP,NTRANS +S 3600,500,3600,2300,200,28onymous_,UP,NTRANS +S 2400,500,2400,2300,200,27onymous_,UP,NTRANS +S 1200,2600,1200,5200,200,26onymous_,UP,POLY +S 2400,2600,2400,5200,200,25onymous_,UP,POLY +S 3600,2600,3600,5200,200,24onymous_,UP,POLY +S 9000,11000,9000,14000,300,23onymous_,UP,ALU1 +S 9000,7000,9000,9000,300,22onymous_,UP,ALU1 +S 600,11000,600,14000,300,21onymous_,UP,ALU1 +S 1200,17700,1200,19500,200,20onymous_,UP,NTRANS +S 600,17900,600,19300,600,19onymous_,UP,NDIF +S 1800,17900,1800,19300,600,18onymous_,UP,NDIF +S 1200,9800,3600,9800,200,17onymous_,RIGHT,POLY +S 1800,12000,1800,18000,300,16onymous_,UP,ALU1 +S 1200,14800,1200,17400,200,15onymous_,UP,POLY +S 4200,11000,4200,13000,300,14onymous_,UP,ALU1 +S 3000,10800,3000,12000,300,5nonymous_,UP,ALU1 +S 3000,10080,3000,12519,600,6nonymous_,UP,NTIE +S 3600,9800,3600,13000,200,7nonymous_,UP,POLY +S 2400,9800,2400,13200,200,8nonymous_,UP,POLY +S 2400,13000,3600,13000,600,9nonymous_,RIGHT,POLY +S 1800,13000,3000,13000,300,10onymous_,RIGHT,ALU1 +S 600,10900,600,14300,600,11onymous_,UP,PDIF +S 1800,10900,1800,14300,600,12onymous_,UP,PDIF +S 1200,10700,1200,14500,200,13onymous_,UP,PTRANS +S 9000,17900,9000,19300,600,34onymous_,UP,NDIF +S 1800,5700,1800,9300,600,55onymous_,UP,PDIF +S 600,5700,600,9300,600,56onymous_,UP,PDIF +S 600,6000,600,9000,300,57onymous_,UP,ALU1 +S 1800,2000,1800,8000,300,58onymous_,UP,ALU1 +S 4200,2000,4200,8000,300,59onymous_,UP,ALU1 +S 5400,2000,5400,8000,300,60onymous_,UP,ALU1 +S 7800,2000,7800,8000,300,61onymous_,UP,ALU1 +S 6000,2600,6000,5200,200,62onymous_,UP,POLY +S 7200,2600,7200,5200,200,63onymous_,UP,POLY +S 5400,12000,5400,18000,300,64onymous_,UP,ALU1 +S 8400,14800,8400,17400,200,68onymous_,UP,POLY +S 4800,14800,4800,17400,200,67onymous_,UP,POLY +S 6000,14800,6000,17400,200,66onymous_,UP,POLY +S 7200,14800,7200,17400,200,65onymous_,UP,POLY +S 3000,5700,3000,9300,600,54onymous_,UP,PDIF +S 1200,5500,1200,9500,200,53onymous_,UP,PTRANS +S 2400,5500,2400,9500,200,52onymous_,UP,PTRANS +S 3600,5500,3600,9500,200,51onymous_,UP,PTRANS +S 600,700,600,2100,600,50onymous_,UP,NDIF +S 1800,700,1800,2100,600,49onymous_,UP,NDIF +S 3000,700,3000,2100,600,48onymous_,UP,NDIF +S 4200,700,4200,2100,600,47onymous_,UP,NDIF +S 5400,700,5400,2100,600,46onymous_,UP,NDIF +S 9000,700,9000,2100,600,45onymous_,UP,NDIF +S 7800,700,7800,2100,600,44onymous_,UP,NDIF +S 6600,700,6600,2100,600,43onymous_,UP,NDIF +S 1200,500,1200,2300,200,42onymous_,UP,NTRANS +S 6600,5700,6600,9300,600,41onymous_,UP,PDIF +S 6000,5500,6000,9500,200,40onymous_,UP,PTRANS +S 7200,5500,7200,9500,200,39onymous_,UP,PTRANS +S 5400,5700,5400,9300,600,38onymous_,UP,PDIF +S 7800,5700,7800,9300,600,37onymous_,UP,PDIF +S 4200,5700,4200,9300,600,36onymous_,UP,PDIF +S 9000,10700,9000,14300,600,35onymous_,UP,PDIF +S 6600,17900,6600,19300,600,78onymous_,UP,NDIF +S 8400,17700,8400,19500,200,77onymous_,UP,NTRANS +S 6600,10700,6600,14300,600,76onymous_,UP,PDIF +S 6000,10500,6000,14500,200,75onymous_,UP,PTRANS +S 7200,10500,7200,14500,200,74onymous_,UP,PTRANS +S 4200,10700,4200,14300,600,69onymous_,UP,PDIF +S 8400,10500,8400,14500,200,70onymous_,UP,PTRANS +S 7800,10700,7800,14300,600,71onymous_,UP,PDIF +S 4800,10500,4800,14500,200,72onymous_,UP,PTRANS +S 5400,10700,5400,14300,600,73onymous_,UP,PDIF +S 4200,17900,4200,19300,600,79onymous_,UP,NDIF +S 7800,17900,7800,19300,600,80onymous_,UP,NDIF +S 4800,17700,4800,19500,200,81onymous_,UP,NTRANS +S 5400,17900,5400,19300,600,82onymous_,UP,NDIF +S 7200,17700,7200,19500,200,83onymous_,UP,NTRANS +S 6000,17700,6000,19500,200,84onymous_,UP,NTRANS +S 3800,15000,8400,15000,600,85onymous_,RIGHT,POLY +S 9000,6700,9000,9300,600,86onymous_,UP,PDIF +S 8400,6500,8400,9500,200,87onymous_,UP,PTRANS +S 8400,2600,8400,6200,200,88onymous_,UP,POLY +S 6600,6000,6600,9000,300,89onymous_,UP,ALU1 +S 3000,6000,3000,9000,300,90onymous_,UP,ALU1 +S 4200,4800,8400,4800,600,91onymous_,RIGHT,POLY +S 1200,4800,3600,4800,600,92onymous_,RIGHT,POLY +S 9000,1000,9000,2000,300,93onymous_,UP,ALU1 +S 7800,12000,7800,18000,300,94onymous_,UP,ALU1 +S 1650,3000,5150,3000,600,95onymous_,RIGHT,ALU2 +S 5400,18000,7800,18000,400,96onymous_,RIGHT,ALU1 +S 1650,8000,5150,8000,600,97onymous_,RIGHT,ALU2 +S 6850,3000,7950,3000,600,98onymous_,RIGHT,ALU2 +S 6850,8000,7950,8000,600,99onymous_,RIGHT,ALU2 +S 5400,4600,7800,4600,800,100nymous_,RIGHT,ALU1 +S 1050,8000,7950,8000,300,101nymous_,RIGHT,TALU2 +S 1050,3000,7950,3000,300,102nymous_,RIGHT,TALU2 +S 3000,17680,3000,19120,600,103nymous_,UP,PTIE +S 600,1000,600,2000,300,104nymous_,UP,ALU1 +S 3000,1000,3000,2000,300,105nymous_,UP,ALU1 +S 6600,1000,6600,2000,300,106nymous_,UP,ALU1 +S 4000,14000,4000,18000,300,ck,UP,CALU1 +S 5000,2850,5000,8150,400,sel1,UP,CALU3 +S 7000,2850,7000,8150,400,sel0,UP,CALU3 +S 5850,18000,7150,18000,600,nck,RIGHT,CALU2 +S 3000,14000,3000,18000,300,sel,UP,CALU1 +V 3000,12000,CONT_BODY_N,107nymous_ +V 3000,13000,CONT_POLY,108nymous_ +V 5000,3000,CONT_VIA2,109nymous_ +V 7000,8000,CONT_VIA2,110nymous_ +V 3000,16000,CONT_POLY,111nymous_ +V 3000,10800,CONT_BODY_N,112nymous_ +V 1800,18000,CONT_DIF_N,113nymous_ +V 9000,7000,CONT_DIF_P,153nymous_ +V 9000,8000,CONT_DIF_P,152nymous_ +V 3000,6000,CONT_DIF_P,151nymous_ +V 3000,8000,CONT_DIF_P,150nymous_ +V 3000,7000,CONT_DIF_P,149nymous_ +V 3000,9000,CONT_DIF_P,148nymous_ +V 600,9000,CONT_DIF_P,147nymous_ +V 600,7000,CONT_DIF_P,146nymous_ +V 600,8000,CONT_DIF_P,145nymous_ +V 600,6000,CONT_DIF_P,144nymous_ +V 9000,1000,CONT_DIF_N,143nymous_ +V 6600,1000,CONT_DIF_N,142nymous_ +V 3000,1000,CONT_DIF_N,141nymous_ +V 600,1000,CONT_DIF_N,140nymous_ +V 5400,8000,CONT_DIF_P,139nymous_ +V 7800,7000,CONT_DIF_P,138nymous_ +V 7800,8000,CONT_DIF_P,137nymous_ +V 6600,7000,CONT_DIF_P,136nymous_ +V 6600,6000,CONT_DIF_P,135nymous_ +V 4200,12000,CONT_DIF_P,177nymous_ +V 5400,13000,CONT_DIF_P,176nymous_ +V 5400,14000,CONT_DIF_P,175nymous_ +V 7800,12000,CONT_DIF_P,174nymous_ +V 7800,13000,CONT_DIF_P,173nymous_ +V 7800,14000,CONT_DIF_P,172nymous_ +V 6600,12000,CONT_DIF_P,171nymous_ +V 6600,11000,CONT_DIF_P,170nymous_ +V 6600,13000,CONT_DIF_P,169nymous_ +V 6600,14000,CONT_DIF_P,168nymous_ +V 5400,12000,CONT_DIF_P,167nymous_ +V 4200,11000,CONT_DIF_P,166nymous_ +V 1800,6000,CONT_DIF_P,165nymous_ +V 1800,7000,CONT_DIF_P,164nymous_ +V 1800,8000,CONT_DIF_P,163nymous_ +V 4200,6000,CONT_DIF_P,162nymous_ +V 4200,8000,CONT_DIF_P,161nymous_ +V 4200,7000,CONT_DIF_P,160nymous_ +V 7800,2000,CONT_DIF_N,159nymous_ +V 5400,2000,CONT_DIF_N,158nymous_ +V 4200,2000,CONT_DIF_N,157nymous_ +V 1800,2000,CONT_DIF_N,156nymous_ +V 5400,6000,CONT_DIF_P,155nymous_ +V 7800,6000,CONT_DIF_P,154nymous_ +V 600,18000,CONT_DIF_N,114nymous_ +V 600,19000,CONT_DIF_N,115nymous_ +V 1800,13000,CONT_DIF_P,116nymous_ +V 1800,12000,CONT_DIF_P,117nymous_ +V 1800,14000,CONT_DIF_P,118nymous_ +V 600,12000,CONT_DIF_P,119nymous_ +V 600,13000,CONT_DIF_P,120nymous_ +V 600,14000,CONT_DIF_P,121nymous_ +V 600,11000,CONT_DIF_P,122nymous_ +V 9000,14000,CONT_DIF_P,123nymous_ +V 3000,2000,CONT_DIF_N,124nymous_ +V 6600,2000,CONT_DIF_N,125nymous_ +V 7800,8000,CONT_VIA,126nymous_ +V 9000,19000,CONT_DIF_N,127nymous_ +V 9000,18000,CONT_DIF_N,128nymous_ +V 9000,13000,CONT_DIF_P,129nymous_ +V 9000,12000,CONT_DIF_P,130nymous_ +V 9000,11000,CONT_DIF_P,131nymous_ +V 5400,7000,CONT_DIF_P,132nymous_ +V 6600,9000,CONT_DIF_P,133nymous_ +V 6600,8000,CONT_DIF_P,134nymous_ +V 4200,13000,CONT_DIF_P,178nymous_ +V 7800,18000,CONT_DIF_N,179nymous_ +V 4200,19000,CONT_DIF_N,180nymous_ +V 5400,18000,CONT_DIF_N,181nymous_ +V 6600,19000,CONT_DIF_N,182nymous_ +V 4000,15000,CONT_POLY,183nymous_ +V 9000,9000,CONT_DIF_P,184nymous_ +V 4400,4800,CONT_POLY,185nymous_ +V 4200,3000,CONT_VIA,186nymous_ +V 600,2000,CONT_DIF_N,187nymous_ +V 9000,2000,CONT_DIF_N,188nymous_ +V 3000,19000,CONT_BODY_P,189nymous_ +V 7000,18000,CONT_VIA,190nymous_ +V 1800,3000,CONT_VIA,191nymous_ +V 6000,18000,CONT_VIA,192nymous_ +V 1800,8000,CONT_VIA,193nymous_ +V 5000,8000,CONT_VIA2,194nymous_ +V 4200,8000,CONT_VIA,195nymous_ +V 7000,3000,CONT_VIA2,196nymous_ +V 7800,3000,CONT_VIA,197nymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_inmux_buf_2.vbe b/pdks/symbolic/nrflib/cells/rf_inmux_buf_2.vbe new file mode 100644 index 000000000..29ceb42cd --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_inmux_buf_2.vbe @@ -0,0 +1,24 @@ +ENTITY rf_inmux_buf_2 IS +PORT ( + ck : in BIT; + sel : in BIT; + nck : out BIT; + sel0 : out BIT; + sel1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_inmux_buf_2; + +ARCHITECTURE VBE OF rf_inmux_buf_2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_inmux_buf_2" + SEVERITY WARNING; + + nck <= not ck; + sel1 <= sel; + sel0 <= not sel; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_inmux_buf_4.ap b/pdks/symbolic/nrflib/cells/rf_inmux_buf_4.ap new file mode 100644 index 000000000..24c3a8da2 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_inmux_buf_4.ap @@ -0,0 +1,351 @@ +V ALLIANCE : 6 +H rf_inmux_buf_4,P,22/4/2016,100 +A 0,0,9000,40000 +S 600,1000,600,2000,300,4nonymous_,UP,ALU1 +S 0,10600,9000,10600,1200,vdd,RIGHT,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,30600,9000,30600,1200,vdd,RIGHT,CALU1 +S 0,29400,9000,29400,1200,vdd,RIGHT,CALU1 +S 2000,-150,2000,40150,2400,vss,UP,CALU3 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 0,39400,9000,39400,1200,vss,RIGHT,CALU1 +S 0,20600,9000,20600,1200,vss,RIGHT,CALU1 +S 0,19400,9000,19400,1200,vss,RIGHT,CALU1 +S 3000,12680,3000,13919,600,0nonymous_,UP,NTIE +S 6600,11000,6600,14000,300,1nonymous_,UP,ALU1 +S 3879,29200,7920,29200,600,2nonymous_,RIGHT,NTIE +S 3679,20800,7920,20800,600,3nonymous_,RIGHT,PTIE +S 5250,8000,7950,8000,600,38onymous_,RIGHT,ALU2 +S 9000,11000,9000,14000,300,37onymous_,UP,ALU1 +S 9000,7000,9000,9000,300,36onymous_,UP,ALU1 +S 600,11000,600,14000,300,35onymous_,UP,ALU1 +S 1200,17700,1200,19500,200,34onymous_,UP,NTRANS +S 6600,18000,6600,19000,300,13onymous_,UP,ALU1 +S 9000,18000,9000,19000,300,12onymous_,UP,ALU1 +S 6600,38000,6600,39000,300,11onymous_,UP,ALU1 +S 3000,38000,3000,39000,300,10onymous_,UP,ALU1 +S 600,38000,600,39000,300,9nonymous_,UP,ALU1 +S 600,21000,600,22000,300,8nonymous_,UP,ALU1 +S 600,18000,600,19000,300,7nonymous_,UP,ALU1 +S 6600,1000,6600,2000,300,6nonymous_,UP,ALU1 +S 3000,1000,3000,2000,300,5nonymous_,UP,ALU1 +S 5400,4800,7800,4800,300,14onymous_,RIGHT,ALU1 +S 1800,4800,4200,4800,300,15onymous_,RIGHT,ALU1 +S 5450,8000,7750,8000,300,16onymous_,RIGHT,TALU2 +S 1850,3000,4950,3000,300,17onymous_,RIGHT,TALU2 +S 5450,32000,7750,32000,300,18onymous_,RIGHT,TALU2 +S 1850,37000,4950,37000,300,19onymous_,RIGHT,TALU2 +S 3600,9800,3600,12000,200,30onymous_,UP,POLY +S 2400,9800,2400,12000,200,31onymous_,UP,POLY +S 1200,9800,3600,9800,200,32onymous_,RIGHT,POLY +S 600,17900,600,19300,600,33onymous_,UP,NDIF +S 2400,12000,3600,12000,600,29onymous_,RIGHT,POLY +S 1800,12000,1800,18000,300,28onymous_,UP,ALU1 +S 1800,12000,3000,12000,300,27onymous_,RIGHT,ALU1 +S 3000,13000,4200,13000,300,26onymous_,RIGHT,ALU1 +S 1200,14800,1200,17400,200,25onymous_,UP,POLY +S 4200,11000,4200,13000,300,24onymous_,UP,ALU1 +S 5400,15000,10000,15000,3600,23onymous_,RIGHT,NWELL +S 1200,10700,1200,14500,200,22onymous_,UP,PTRANS +S 1800,10900,1800,14300,600,21onymous_,UP,PDIF +S 600,10900,600,14300,600,20onymous_,UP,PDIF +S 3600,2600,3600,5200,200,39onymous_,UP,POLY +S 2400,2600,2400,5200,200,40onymous_,UP,POLY +S 1200,2600,1200,5200,200,41onymous_,UP,POLY +S 2400,500,2400,2300,200,42onymous_,UP,NTRANS +S 3600,500,3600,2300,200,43onymous_,UP,NTRANS +S 6000,500,6000,2300,200,44onymous_,UP,NTRANS +S 7200,500,7200,2300,200,45onymous_,UP,NTRANS +S 8400,500,8400,2300,200,46onymous_,UP,NTRANS +S -600,12200,10000,12200,6000,47onymous_,RIGHT,NWELL +S -600,7800,10000,7800,6000,48onymous_,RIGHT,NWELL +S 9000,17900,9000,19300,600,49onymous_,UP,NDIF +S 9000,10700,9000,14300,600,50onymous_,UP,PDIF +S 4200,5700,4200,9300,600,51onymous_,UP,PDIF +S 7800,5700,7800,9300,600,52onymous_,UP,PDIF +S 5400,5700,5400,9300,600,53onymous_,UP,PDIF +S 7200,5500,7200,9500,200,54onymous_,UP,PTRANS +S 6000,5500,6000,9500,200,55onymous_,UP,PTRANS +S 6600,5700,6600,9300,600,56onymous_,UP,PDIF +S 1200,500,1200,2300,200,57onymous_,UP,NTRANS +S 6600,700,6600,2100,600,58onymous_,UP,NDIF +S 7800,700,7800,2100,600,59onymous_,UP,NDIF +S 9000,700,9000,2100,600,60onymous_,UP,NDIF +S 5400,700,5400,2100,600,61onymous_,UP,NDIF +S 4200,700,4200,2100,600,62onymous_,UP,NDIF +S 3000,700,3000,2100,600,63onymous_,UP,NDIF +S 1800,700,1800,2100,600,64onymous_,UP,NDIF +S 600,700,600,2100,600,65onymous_,UP,NDIF +S 3600,5500,3600,9500,200,66onymous_,UP,PTRANS +S 2400,5500,2400,9500,200,67onymous_,UP,PTRANS +S 1200,5500,1200,9500,200,68onymous_,UP,PTRANS +S 1800,2000,1800,8000,300,73onymous_,UP,ALU1 +S 600,6000,600,9000,300,72onymous_,UP,ALU1 +S 600,5700,600,9300,600,71onymous_,UP,PDIF +S 1800,5700,1800,9300,600,70onymous_,UP,PDIF +S 3000,5700,3000,9300,600,69onymous_,UP,PDIF +S 4200,2000,4200,8000,300,74onymous_,UP,ALU1 +S 5400,2000,5400,8000,300,75onymous_,UP,ALU1 +S 7800,2000,7800,8000,300,76onymous_,UP,ALU1 +S 6000,2600,6000,5200,200,77onymous_,UP,POLY +S 7200,2600,7200,5200,200,78onymous_,UP,POLY +S 5400,12000,5400,18000,300,79onymous_,UP,ALU1 +S 7800,12000,7800,18000,300,80onymous_,UP,ALU1 +S 7200,14800,7200,17400,200,81onymous_,UP,POLY +S 6000,14800,6000,17400,200,82onymous_,UP,POLY +S 4800,14800,4800,17400,200,83onymous_,UP,POLY +S 8400,14800,8400,17400,200,84onymous_,UP,POLY +S 4200,10700,4200,14300,600,85onymous_,UP,PDIF +S 8400,10500,8400,14500,200,86onymous_,UP,PTRANS +S 7800,10700,7800,14300,600,87onymous_,UP,PDIF +S 4800,10500,4800,14500,200,88onymous_,UP,PTRANS +S 5400,10700,5400,14300,600,89onymous_,UP,PDIF +S 7200,10500,7200,14500,200,90onymous_,UP,PTRANS +S 6000,10500,6000,14500,200,91onymous_,UP,PTRANS +S 6600,10700,6600,14300,600,92onymous_,UP,PDIF +S 8400,17700,8400,19500,200,93onymous_,UP,NTRANS +S 6600,17900,6600,19300,600,94onymous_,UP,NDIF +S 4200,17900,4200,19300,600,95onymous_,UP,NDIF +S 7800,17900,7800,19300,600,96onymous_,UP,NDIF +S 4800,17700,4800,19500,200,97onymous_,UP,NTRANS +S 5400,17900,5400,19300,600,98onymous_,UP,NDIF +S 7200,17700,7200,19500,200,99onymous_,UP,NTRANS +S 6000,17700,6000,19500,200,100nymous_,UP,NTRANS +S 3800,15000,8400,15000,600,101nymous_,RIGHT,POLY +S 9000,6700,9000,9300,600,102nymous_,UP,PDIF +S 8400,6500,8400,9500,200,103nymous_,UP,PTRANS +S 600,31000,600,34000,300,113nymous_,UP,ALU1 +S 5250,32000,7950,32000,600,112nymous_,RIGHT,ALU2 +S 1650,37000,5150,37000,600,111nymous_,RIGHT,ALU2 +S 9000,1000,9000,2000,300,110nymous_,UP,ALU1 +S 1650,3000,5150,3000,600,109nymous_,RIGHT,ALU2 +S 1200,4800,3600,4800,600,108nymous_,RIGHT,POLY +S 4200,4800,8400,4800,600,107nymous_,RIGHT,POLY +S 3000,6000,3000,9000,300,106nymous_,UP,ALU1 +S 6600,6000,6600,9000,300,105nymous_,UP,ALU1 +S 8400,2600,8400,6200,200,104nymous_,UP,POLY +S 8400,30500,8400,33500,200,158nymous_,UP,PTRANS +S 3600,30500,3600,34500,200,157nymous_,UP,PTRANS +S 2400,30500,2400,34500,200,156nymous_,UP,PTRANS +S 1200,30500,1200,34500,200,155nymous_,UP,PTRANS +S 3000,30700,3000,34300,600,154nymous_,UP,PDIF +S 9000,31000,9000,33000,300,114nymous_,UP,ALU1 +S 7800,32000,7800,38000,300,115nymous_,UP,ALU1 +S 5400,32000,5400,38000,300,116nymous_,UP,ALU1 +S 4200,32000,4200,38000,300,117nymous_,UP,ALU1 +S 1800,32000,1800,38000,300,118nymous_,UP,ALU1 +S 9000,38000,9000,39000,300,119nymous_,UP,ALU1 +S 3000,31000,3000,34000,300,120nymous_,UP,ALU1 +S 6600,31000,6600,34000,300,121nymous_,UP,ALU1 +S 1200,34800,1200,37400,200,122nymous_,UP,POLY +S 2400,34800,2400,37400,200,123nymous_,UP,POLY +S 3600,34800,3600,37400,200,124nymous_,UP,POLY +S 1200,30200,3600,30200,200,125nymous_,RIGHT,POLY +S 7200,34800,7200,37400,200,126nymous_,UP,POLY +S 6000,34800,6000,37400,200,127nymous_,UP,POLY +S 1200,35200,3600,35200,600,128nymous_,RIGHT,POLY +S 4200,35200,8400,35200,600,129nymous_,RIGHT,POLY +S 8400,33800,8400,37400,200,130nymous_,UP,POLY +S 7200,37700,7200,39500,200,131nymous_,UP,NTRANS +S 6000,37700,6000,39500,200,132nymous_,UP,NTRANS +S 3600,37700,3600,39500,200,133nymous_,UP,NTRANS +S 2400,37700,2400,39500,200,134nymous_,UP,NTRANS +S 5400,37900,5400,39300,600,135nymous_,UP,NDIF +S 9000,37900,9000,39300,600,136nymous_,UP,NDIF +S 7800,37900,7800,39300,600,137nymous_,UP,NDIF +S 6600,37900,6600,39300,600,138nymous_,UP,NDIF +S 1200,37700,1200,39500,200,139nymous_,UP,NTRANS +S 8400,37700,8400,39500,200,140nymous_,UP,NTRANS +S 600,37900,600,39300,600,141nymous_,UP,NDIF +S 1800,37900,1800,39300,600,142nymous_,UP,NDIF +S 3000,37900,3000,39300,600,143nymous_,UP,NDIF +S 4200,37900,4200,39300,600,144nymous_,UP,NDIF +S 6600,30700,6600,34300,600,145nymous_,UP,PDIF +S 6000,30500,6000,34500,200,146nymous_,UP,PTRANS +S 7200,30500,7200,34500,200,147nymous_,UP,PTRANS +S 5400,30700,5400,34300,600,148nymous_,UP,PDIF +S 7800,30700,7800,34300,600,149nymous_,UP,PDIF +S 4200,30700,4200,34300,600,150nymous_,UP,PDIF +S -600,32200,10000,32200,6000,151nymous_,RIGHT,NWELL +S 600,30700,600,34300,600,152nymous_,UP,PDIF +S 1800,30700,1800,34300,600,153nymous_,UP,PDIF +S 9000,30700,9000,33300,600,159nymous_,UP,PDIF +S 1800,22000,1800,28000,300,160nymous_,UP,ALU1 +S 1800,28000,3000,28000,300,161nymous_,RIGHT,ALU1 +S 600,26000,600,29000,300,162nymous_,UP,ALU1 +S 1200,22600,1200,25200,200,163nymous_,UP,POLY +S 2400,28000,2400,30200,200,164nymous_,UP,POLY +S 3600,28000,3600,30200,200,165nymous_,UP,POLY +S 2400,28000,3600,28000,600,166nymous_,RIGHT,POLY +S 1200,20500,1200,22300,200,167nymous_,UP,NTRANS +S 600,20700,600,22100,600,168nymous_,UP,NDIF +S 1200,25500,1200,29300,200,169nymous_,UP,PTRANS +S 1800,25700,1800,29100,600,170nymous_,UP,PDIF +S 600,25700,600,29100,600,171nymous_,UP,PDIF +S 1800,17900,1800,22100,600,172nymous_,UP,NDIF +S -600,27800,10000,27800,6000,173nymous_,RIGHT,NWELL +S 1200,16000,3000,16000,600,174nymous_,RIGHT,POLY +S 1050,20000,2950,20000,300,175nymous_,RIGHT,TALU2 +S 1050,0,2950,0,300,176nymous_,RIGHT,TALU2 +S 1050,40000,2950,40000,300,177nymous_,RIGHT,TALU2 +S 4000,14000,4000,18000,300,ck,UP,CALU1 +S 5000,2850,5000,37150,400,sel1,UP,CALU3 +S 7000,7850,7000,32150,400,sel0,UP,CALU3 +S 5250,18000,7950,18000,600,nck,RIGHT,CALU2 +S 3000,14000,3000,18000,300,sel,UP,CALU1 +V 2000,40000,CONT_VIA,178nymous_ +V 2000,40000,CONT_VIA2,179nymous_ +V 2000,0,CONT_VIA2,180nymous_ +V 2000,0,CONT_VIA,181nymous_ +V 2000,20000,CONT_VIA,182nymous_ +V 2000,20000,CONT_VIA2,183nymous_ +V 6600,18000,CONT_DIF_N,184nymous_ +V 3000,16000,CONT_POLY,185nymous_ +V 3000,13000,CONT_BODY_N,186nymous_ +V 3000,12000,CONT_POLY,187nymous_ +V 1800,18000,CONT_DIF_N,188nymous_ +V 600,18000,CONT_DIF_N,189nymous_ +V 600,19000,CONT_DIF_N,190nymous_ +V 1800,13000,CONT_DIF_P,191nymous_ +V 1800,12000,CONT_DIF_P,192nymous_ +V 1800,14000,CONT_DIF_P,193nymous_ +V 600,12000,CONT_DIF_P,194nymous_ +V 600,13000,CONT_DIF_P,195nymous_ +V 600,14000,CONT_DIF_P,196nymous_ +V 600,11000,CONT_DIF_P,197nymous_ +V 5000,3000,CONT_VIA2,198nymous_ +V 9000,14000,CONT_DIF_P,199nymous_ +V 3000,2000,CONT_DIF_N,200nymous_ +V 6600,2000,CONT_DIF_N,201nymous_ +V 7000,8000,CONT_VIA2,202nymous_ +V 7800,8000,CONT_VIA,203nymous_ +V 5400,8000,CONT_VIA,204nymous_ +V 9000,19000,CONT_DIF_N,205nymous_ +V 9000,18000,CONT_DIF_N,206nymous_ +V 9000,13000,CONT_DIF_P,207nymous_ +V 9000,12000,CONT_DIF_P,208nymous_ +V 9000,11000,CONT_DIF_P,209nymous_ +V 5400,7000,CONT_DIF_P,210nymous_ +V 6600,9000,CONT_DIF_P,211nymous_ +V 6600,8000,CONT_DIF_P,212nymous_ +V 6600,6000,CONT_DIF_P,213nymous_ +V 6600,7000,CONT_DIF_P,214nymous_ +V 7800,8000,CONT_DIF_P,215nymous_ +V 7800,7000,CONT_DIF_P,216nymous_ +V 5400,8000,CONT_DIF_P,217nymous_ +V 600,1000,CONT_DIF_N,218nymous_ +V 3000,1000,CONT_DIF_N,219nymous_ +V 6600,1000,CONT_DIF_N,220nymous_ +V 9000,1000,CONT_DIF_N,221nymous_ +V 600,6000,CONT_DIF_P,222nymous_ +V 600,8000,CONT_DIF_P,223nymous_ +V 600,7000,CONT_DIF_P,224nymous_ +V 600,9000,CONT_DIF_P,225nymous_ +V 3000,9000,CONT_DIF_P,226nymous_ +V 3000,7000,CONT_DIF_P,227nymous_ +V 3000,8000,CONT_DIF_P,228nymous_ +V 3000,6000,CONT_DIF_P,229nymous_ +V 9000,8000,CONT_DIF_P,230nymous_ +V 9000,7000,CONT_DIF_P,231nymous_ +V 7800,6000,CONT_DIF_P,232nymous_ +V 5400,6000,CONT_DIF_P,233nymous_ +V 1800,2000,CONT_DIF_N,234nymous_ +V 4200,2000,CONT_DIF_N,235nymous_ +V 5400,2000,CONT_DIF_N,236nymous_ +V 7800,2000,CONT_DIF_N,237nymous_ +V 4200,7000,CONT_DIF_P,238nymous_ +V 4200,8000,CONT_DIF_P,239nymous_ +V 4200,6000,CONT_DIF_P,240nymous_ +V 1800,8000,CONT_DIF_P,241nymous_ +V 1800,7000,CONT_DIF_P,242nymous_ +V 1800,6000,CONT_DIF_P,243nymous_ +V 5400,18000,CONT_VIA,244nymous_ +V 7800,18000,CONT_VIA,245nymous_ +V 4200,11000,CONT_DIF_P,246nymous_ +V 5400,12000,CONT_DIF_P,247nymous_ +V 6600,14000,CONT_DIF_P,248nymous_ +V 6600,13000,CONT_DIF_P,249nymous_ +V 6600,11000,CONT_DIF_P,250nymous_ +V 6600,12000,CONT_DIF_P,251nymous_ +V 7800,14000,CONT_DIF_P,252nymous_ +V 7800,13000,CONT_DIF_P,253nymous_ +V 7800,12000,CONT_DIF_P,254nymous_ +V 5400,14000,CONT_DIF_P,255nymous_ +V 5400,13000,CONT_DIF_P,256nymous_ +V 4200,12000,CONT_DIF_P,257nymous_ +V 4200,13000,CONT_DIF_P,258nymous_ +V 7800,18000,CONT_DIF_N,259nymous_ +V 4200,19000,CONT_DIF_N,260nymous_ +V 5400,18000,CONT_DIF_N,261nymous_ +V 6600,19000,CONT_DIF_N,262nymous_ +V 4000,15000,CONT_POLY,263nymous_ +V 9000,9000,CONT_DIF_P,264nymous_ +V 4400,4800,CONT_POLY,265nymous_ +V 4200,33000,CONT_DIF_P,313nymous_ +V 4200,32000,CONT_DIF_P,312nymous_ +V 4200,34000,CONT_DIF_P,311nymous_ +V 1800,32000,CONT_DIF_P,310nymous_ +V 1800,33000,CONT_DIF_P,309nymous_ +V 1800,34000,CONT_DIF_P,308nymous_ +V 600,31000,CONT_DIF_P,307nymous_ +V 3000,31000,CONT_DIF_P,306nymous_ +V 3000,33000,CONT_DIF_P,305nymous_ +V 3000,32000,CONT_DIF_P,304nymous_ +V 3000,34000,CONT_DIF_P,303nymous_ +V 9000,32000,CONT_DIF_P,302nymous_ +V 9000,33000,CONT_DIF_P,301nymous_ +V 7800,34000,CONT_DIF_P,300nymous_ +V 6600,34000,CONT_DIF_P,299nymous_ +V 6600,33000,CONT_DIF_P,298nymous_ +V 4000,20800,CONT_BODY_P,329nymous_ +V 6000,29200,CONT_BODY_N,328nymous_ +V 4200,29200,CONT_BODY_N,327nymous_ +V 600,29000,CONT_DIF_P,326nymous_ +V 1800,27000,CONT_DIF_P,325nymous_ +V 1800,28000,CONT_DIF_P,324nymous_ +V 1800,26000,CONT_DIF_P,323nymous_ +V 600,28000,CONT_DIF_P,322nymous_ +V 600,27000,CONT_DIF_P,321nymous_ +V 600,26000,CONT_DIF_P,320nymous_ +V 1800,22000,CONT_DIF_N,319nymous_ +V 600,22000,CONT_DIF_N,318nymous_ +V 600,21000,CONT_DIF_N,317nymous_ +V 3000,28000,CONT_POLY,316nymous_ +V 9000,31000,CONT_DIF_P,315nymous_ +V 5400,34000,CONT_DIF_P,314nymous_ +V 4200,3000,CONT_VIA,266nymous_ +V 1800,3000,CONT_VIA,267nymous_ +V 600,2000,CONT_DIF_N,268nymous_ +V 9000,2000,CONT_DIF_N,269nymous_ +V 7000,32000,CONT_VIA2,270nymous_ +V 5000,37000,CONT_VIA2,271nymous_ +V 1800,37000,CONT_VIA,272nymous_ +V 5400,32000,CONT_VIA,273nymous_ +V 7800,32000,CONT_VIA,274nymous_ +V 4200,37000,CONT_VIA,275nymous_ +V 4400,35200,CONT_POLY,276nymous_ +V 600,39000,CONT_DIF_N,277nymous_ +V 6600,38000,CONT_DIF_N,278nymous_ +V 3000,38000,CONT_DIF_N,279nymous_ +V 7800,38000,CONT_DIF_N,280nymous_ +V 5400,38000,CONT_DIF_N,281nymous_ +V 4200,38000,CONT_DIF_N,282nymous_ +V 1800,38000,CONT_DIF_N,283nymous_ +V 9000,39000,CONT_DIF_N,284nymous_ +V 6600,39000,CONT_DIF_N,285nymous_ +V 3000,39000,CONT_DIF_N,286nymous_ +V 9000,38000,CONT_DIF_N,287nymous_ +V 600,38000,CONT_DIF_N,288nymous_ +V 6600,32000,CONT_DIF_P,289nymous_ +V 6600,31000,CONT_DIF_P,290nymous_ +V 5400,33000,CONT_DIF_P,291nymous_ +V 600,33000,CONT_DIF_P,292nymous_ +V 600,32000,CONT_DIF_P,293nymous_ +V 600,34000,CONT_DIF_P,294nymous_ +V 5400,32000,CONT_DIF_P,295nymous_ +V 7800,33000,CONT_DIF_P,296nymous_ +V 7800,32000,CONT_DIF_P,297nymous_ +V 6000,20800,CONT_BODY_P,330nymous_ +V 7600,29200,CONT_BODY_N,331nymous_ +V 7600,20800,CONT_BODY_P,332nymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_inmux_buf_4.vbe b/pdks/symbolic/nrflib/cells/rf_inmux_buf_4.vbe new file mode 100644 index 000000000..e0512ca7c --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_inmux_buf_4.vbe @@ -0,0 +1,24 @@ +ENTITY rf_inmux_buf_4 IS +PORT ( + ck : in BIT; + sel : in BIT; + nck : out BIT; + sel0 : out BIT; + sel1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_inmux_buf_4; + +ARCHITECTURE VBE OF rf_inmux_buf_4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_inmux_buf_4" + SEVERITY WARNING; + + nck <= not ck; + sel1 <= sel; + sel0 <= not sel; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_inmux_mem.ap b/pdks/symbolic/nrflib/cells/rf_inmux_mem.ap new file mode 100644 index 000000000..c35d62a44 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_inmux_mem.ap @@ -0,0 +1,106 @@ +V ALLIANCE : 6 +H rf_inmux_mem,P,22/4/2016,100 +A 0,0,9000,10000 +S 5000,2000,6800,2000,300,4nonymous_,RIGHT,ALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 4050,6000,6950,6000,300,0nonymous_,RIGHT,TALU2 +S 5850,6000,7150,6000,600,1nonymous_,RIGHT,ALU2 +S 3850,6000,5150,6000,600,2nonymous_,RIGHT,ALU2 +S 7000,5000,7000,6000,300,3nonymous_,UP,ALU1 +S 1800,2000,1800,8000,300,38onymous_,UP,ALU1 +S 5200,4000,6800,4000,200,37onymous_,RIGHT,POLY +S 6800,4000,6800,6800,200,36onymous_,UP,POLY +S -600,8600,9600,8600,4400,35onymous_,RIGHT,NWELL +S -600,7800,7800,7800,6000,34onymous_,RIGHT,NWELL +S 4400,500,4400,1500,200,13onymous_,UP,NTRANS +S 5200,500,5200,1500,200,12onymous_,UP,NTRANS +S 8200,700,8200,1300,600,11onymous_,UP,NDIF +S 6800,500,6800,1500,200,10onymous_,UP,NTRANS +S 7600,500,7600,1500,200,9nonymous_,UP,NTRANS +S 3000,6000,3000,9000,300,8nonymous_,UP,ALU1 +S 600,6000,600,9000,300,7nonymous_,UP,ALU1 +S 6000,3000,6000,8000,300,6nonymous_,UP,ALU1 +S 5000,2000,5000,6000,300,5nonymous_,UP,ALU1 +S 5200,1800,5200,4000,200,14onymous_,UP,POLY +S 6000,700,6000,3100,600,15onymous_,UP,NDIF +S 6000,700,6000,1300,1000,16onymous_,UP,NDIF +S 5800,700,5800,3100,600,17onymous_,UP,NDIF +S 1200,5500,1200,9500,200,18onymous_,UP,PTRANS +S 2400,5500,2400,9500,200,19onymous_,UP,PTRANS +S 3800,6800,4400,6800,200,30onymous_,RIGHT,POLY +S 5200,5800,5200,6800,200,31onymous_,UP,POLY +S 7600,6800,8200,6800,200,32onymous_,RIGHT,POLY +S 1200,5000,6000,5000,200,33onymous_,RIGHT,POLY +S 3400,7300,3400,9300,1400,29onymous_,UP,PDIF +S 8200,7300,8200,9100,600,28onymous_,UP,PDIF +S 6000,7300,6000,8900,1000,27onymous_,UP,PDIF +S 5200,7100,5200,9100,200,26onymous_,UP,PTRANS +S 4400,7100,4400,9100,200,25onymous_,UP,PTRANS +S 6800,7100,6800,9100,200,24onymous_,UP,PTRANS +S 7600,7100,7600,9100,200,23onymous_,UP,PTRANS +S 1800,5700,1800,9300,600,22onymous_,UP,PDIF +S 3000,5700,3000,6500,600,21onymous_,UP,PDIF +S 600,5700,600,9300,600,20onymous_,UP,PDIF +S 4680,10000,7320,10000,600,39onymous_,RIGHT,NTIE +S 1200,3800,1200,5200,200,40onymous_,UP,POLY +S 2400,3800,2400,5200,200,41onymous_,UP,POLY +S 1800,1700,1800,3300,600,42onymous_,UP,NDIF +S 600,1700,600,3300,600,43onymous_,UP,NDIF +S 1200,1500,1200,3500,200,44onymous_,UP,NTRANS +S 2400,1500,2400,3500,200,45onymous_,UP,NTRANS +S 600,1000,600,3000,300,46onymous_,UP,ALU1 +S 3400,700,3400,1300,1400,47onymous_,UP,NDIF +S 3000,700,3000,3300,600,48onymous_,UP,NDIF +S 280,700,2120,700,600,49onymous_,RIGHT,PTIE +S 3000,1000,3000,3000,300,50onymous_,UP,ALU1 +S 7600,2800,8000,2800,200,51onymous_,RIGHT,POLY +S 3800,2800,4400,2800,200,52onymous_,RIGHT,POLY +S 4400,1800,4400,2800,200,53onymous_,UP,POLY +S 7600,1800,7600,2800,200,54onymous_,UP,POLY +S 7000,5850,7000,6150,400,sel0,UP,CALU3 +S 5000,5850,5000,6150,400,sel1,UP,CALU3 +S 4000,3000,4000,8000,300,datain0,UP,CALU1 +S 8000,3000,8000,8000,300,datain1,UP,CALU1 +S 1850,2000,3150,2000,600,dinx,RIGHT,CALU2 +V 600,8000,CONT_DIF_P,55onymous_ +V 600,9000,CONT_DIF_P,56onymous_ +V 600,6000,CONT_DIF_P,57onymous_ +V 600,7000,CONT_DIF_P,58onymous_ +V 8200,1000,CONT_DIF_N,59onymous_ +V 8200,9000,CONT_DIF_P,60onymous_ +V 6000,3000,CONT_DIF_N,61onymous_ +V 6000,8000,CONT_DIF_P,62onymous_ +V 3000,7000,CONT_DIF_P,63onymous_ +V 3000,8000,CONT_DIF_P,64onymous_ +V 1800,7000,CONT_DIF_P,65onymous_ +V 1800,8000,CONT_DIF_P,66onymous_ +V 1800,6000,CONT_DIF_P,67onymous_ +V 3000,9000,CONT_DIF_P,68onymous_ +V 4000,6600,CONT_POLY,73onymous_ +V 5000,6000,CONT_POLY,72onymous_ +V 6000,10000,CONT_BODY_N,71onymous_ +V 6800,2000,CONT_POLY,70onymous_ +V 3000,6000,CONT_DIF_P,69onymous_ +V 8000,6600,CONT_POLY,74onymous_ +V 6000,5000,CONT_POLY,75onymous_ +V 5000,6000,CONT_VIA,76onymous_ +V 7000,6000,CONT_VIA,77onymous_ +V 7000,6000,CONT_VIA2,78onymous_ +V 5000,6000,CONT_VIA2,79onymous_ +V 7000,10000,CONT_BODY_N,80onymous_ +V 5000,10000,CONT_BODY_N,81onymous_ +V 600,3000,CONT_DIF_N,82onymous_ +V 600,2000,CONT_DIF_N,83onymous_ +V 600,600,CONT_BODY_P,84onymous_ +V 7000,5000,CONT_POLY,94onymous_ +V 4000,3000,CONT_POLY,93onymous_ +V 8000,3000,CONT_POLY,92onymous_ +V 1800,3000,CONT_DIF_N,91onymous_ +V 3000,3000,CONT_DIF_N,90onymous_ +V 3000,2000,CONT_DIF_N,89onymous_ +V 2000,2000,CONT_VIA,88onymous_ +V 1800,2000,CONT_DIF_N,87onymous_ +V 3800,1000,CONT_DIF_N,86onymous_ +V 1800,600,CONT_BODY_P,85onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_inmux_mem.vbe b/pdks/symbolic/nrflib/cells/rf_inmux_mem.vbe new file mode 100644 index 000000000..b0869fa95 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_inmux_mem.vbe @@ -0,0 +1,22 @@ +ENTITY rf_inmux_mem IS +PORT ( + datain0 : in BIT; + datain1 : in BIT; + sel0 : in BIT; + sel1 : in BIT; + dinx : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_inmux_mem; + +ARCHITECTURE VBE OF rf_inmux_mem IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff1_x4" + SEVERITY WARNING; + + dinx <= (sel0 and datain0) or (sel1 and datain1); + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_mid_buf_2.ap b/pdks/symbolic/nrflib/cells/rf_mid_buf_2.ap new file mode 100644 index 000000000..e01c6a228 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_mid_buf_2.ap @@ -0,0 +1,174 @@ +V ALLIANCE : 6 +H rf_mid_buf_2,P,22/4/2016,100 +A 0,0,5000,20000 +S 0,5700,0,12300,600,4nonymous_,UP,PDIF +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,10600,5000,10600,1200,vdd,RIGHT,CALU1 +S 0,19400,5000,19400,1200,vss,RIGHT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 5000,6000,5000,15800,300,0nonymous_,UP,ALU1 +S 2400,6200,2400,14800,300,1nonymous_,UP,ALU1 +S 0,6000,0,15800,300,2nonymous_,UP,ALU1 +S 600,5500,600,12500,200,3nonymous_,UP,PTRANS +S 1800,16400,1800,17200,200,33onymous_,UP,POLY +S 2400,1000,2400,3000,300,32onymous_,UP,ALU1 +S 5000,1000,5000,3000,300,31onymous_,UP,ALU1 +S 0,1000,0,3000,300,30onymous_,UP,ALU1 +S 1200,17900,1200,19300,600,29onymous_,UP,NDIF +S 3000,17900,3000,19300,600,28onymous_,UP,NDIF +S 850,12000,2150,12000,600,27onymous_,RIGHT,ALU2 +S 2850,12000,4150,12000,600,26onymous_,RIGHT,ALU2 +S 850,8000,2150,8000,600,25onymous_,RIGHT,ALU2 +S 2850,8000,4150,8000,600,24onymous_,RIGHT,ALU2 +S 850,3000,2150,3000,600,23onymous_,RIGHT,ALU2 +S 2850,3000,4150,3000,600,22onymous_,RIGHT,ALU2 +S 1000,12000,1400,12000,300,21onymous_,RIGHT,ALU1 +S 3600,12000,4000,12000,300,20onymous_,RIGHT,ALU1 +S 1000,12200,1400,12200,300,19onymous_,RIGHT,ALU1 +S 3600,12200,4000,12200,300,18onymous_,RIGHT,ALU1 +S -1000,8000,6000,8000,6400,17onymous_,RIGHT,NWELL +S 3200,4000,3200,5200,200,16onymous_,UP,POLY +S 4400,4000,4400,5200,200,15onymous_,UP,POLY +S 600,4000,600,5200,200,14onymous_,UP,POLY +S 5000,5700,5000,12300,600,5nonymous_,UP,PDIF +S 2400,5700,2400,12300,600,6nonymous_,UP,PDIF +S 3200,5500,3200,12500,200,7nonymous_,UP,PTRANS +S 1800,5500,1800,12500,200,8nonymous_,UP,PTRANS +S 2600,5700,2600,12300,600,9nonymous_,UP,PDIF +S 3800,5700,3800,12300,600,10onymous_,UP,PDIF +S 4400,5500,4400,12500,200,11onymous_,UP,PTRANS +S 1200,5700,1200,12300,600,12onymous_,UP,PDIF +S 1800,4000,1800,5200,200,13onymous_,UP,POLY +S 600,17000,2000,17000,600,34onymous_,RIGHT,POLY +S 5000,14500,5000,15900,600,55onymous_,UP,PDIF +S 5000,17000,5000,18000,300,56onymous_,UP,ALU1 +S 0,700,0,3500,600,57onymous_,UP,NDIF +S 1200,700,1200,3500,600,58onymous_,UP,NDIF +S 600,500,600,3700,200,59onymous_,UP,NTRANS +S 4400,500,4400,3700,200,60onymous_,UP,NTRANS +S 3800,700,3800,3500,600,61onymous_,UP,NDIF +S 3200,500,3200,3700,200,62onymous_,UP,NTRANS +S 2400,700,2400,3500,600,63onymous_,UP,NDIF +S 2600,700,2600,3500,600,64onymous_,UP,NDIF +S 1200,2000,1200,8000,300,68onymous_,UP,ALU1 +S 3800,2000,3800,8000,300,67onymous_,UP,ALU1 +S 5000,700,5000,3500,600,66onymous_,UP,NDIF +S 1800,500,1800,3700,200,65onymous_,UP,NTRANS +S 3200,14300,3200,16100,200,54onymous_,UP,PTRANS +S 3800,14500,3800,15900,400,53onymous_,UP,PDIF +S 4400,14300,4400,16100,200,52onymous_,UP,PTRANS +S 2600,14500,2600,15900,600,51onymous_,UP,PDIF +S 5000,17900,5000,19300,600,50onymous_,UP,NDIF +S -1000,13000,6000,13000,7600,49onymous_,RIGHT,NWELL +S 0,17900,0,19300,600,48onymous_,UP,NDIF +S 600,14300,600,16100,200,47onymous_,UP,PTRANS +S 1800,14300,1800,16100,200,46onymous_,UP,PTRANS +S 1200,14500,1200,15900,600,45onymous_,UP,PDIF +S 0,14500,0,15900,600,44onymous_,UP,PDIF +S 4400,17700,4400,19500,200,43onymous_,UP,NTRANS +S 4400,17000,5200,17000,600,42onymous_,RIGHT,POLY +S 4400,16400,4400,17400,200,41onymous_,UP,POLY +S 600,17700,600,19500,200,40onymous_,UP,NTRANS +S 3200,4200,4400,4200,200,39onymous_,RIGHT,POLY +S 600,4200,1800,4200,200,38onymous_,RIGHT,POLY +S 4000,13200,4000,18000,300,37onymous_,UP,ALU1 +S 1000,13200,1000,18000,300,36onymous_,UP,ALU1 +S 600,16400,600,17400,200,35onymous_,UP,POLY +S 3000,16000,3000,17000,300,78onymous_,UP,ALU1 +S 1050,12000,3950,12000,300,77onymous_,RIGHT,TALU2 +S 1050,8000,3950,8000,300,76onymous_,RIGHT,TALU2 +S 1050,3000,3950,3000,300,75onymous_,RIGHT,TALU2 +S 0,18000,0,19000,300,74onymous_,UP,ALU1 +S 3600,17700,3600,19500,200,69onymous_,UP,NTRANS +S 3000,18000,4000,18000,300,70onymous_,RIGHT,ALU1 +S 3200,16400,3200,17200,200,71onymous_,UP,POLY +S 3600,16800,3600,17400,200,72onymous_,UP,POLY +S 2800,17000,3600,17000,600,73onymous_,RIGHT,POLY +S 2000,16000,2000,17000,300,79onymous_,UP,ALU1 +S 600,12800,1800,12800,200,80onymous_,RIGHT,POLY +S 1480,13400,3520,13400,600,81onymous_,RIGHT,NTIE +S 2000,13400,3000,13400,300,82onymous_,RIGHT,ALU1 +S 3200,12800,4400,12800,200,83onymous_,RIGHT,POLY +S 4000,12800,4000,13400,600,84onymous_,UP,POLY +S 1000,12800,1000,13400,600,85onymous_,UP,POLY +S 3850,18000,5150,18000,600,nck,RIGHT,CALU2 +S 4000,2850,4000,12150,400,write,UP,CALU3 +S 1000,2850,1000,12150,400,read,UP,CALU3 +S 1850,17000,3150,17000,600,selw,RIGHT,CALU2 +S 1850,16000,3150,16000,600,selr,RIGHT,CALU2 +V 5000,6000,CONT_DIF_P,86onymous_ +V 3800,6000,CONT_DIF_P,87onymous_ +V 2400,6000,CONT_DIF_P,88onymous_ +V 1200,6000,CONT_DIF_P,89onymous_ +V 0,6000,CONT_DIF_P,90onymous_ +V 0,1000,CONT_DIF_N,91onymous_ +V 2400,1000,CONT_DIF_N,92onymous_ +V 5000,1000,CONT_DIF_N,93onymous_ +V 2400,7000,CONT_DIF_P,94onymous_ +V 2400,3000,CONT_DIF_N,95onymous_ +V 4000,3000,CONT_VIA,96onymous_ +V 4000,3000,CONT_VIA2,97onymous_ +V 4000,8000,CONT_VIA,98onymous_ +V 4000,8000,CONT_VIA2,99onymous_ +V 4000,12000,CONT_VIA,100nymous_ +V 4000,12000,CONT_VIA2,101nymous_ +V 1000,13200,CONT_POLY,102nymous_ +V 5000,15800,CONT_DIF_P,103nymous_ +V 0,15800,CONT_DIF_P,104nymous_ +V 2000,17000,CONT_POLY,105nymous_ +V 4000,13200,CONT_POLY,106nymous_ +V 3000,17000,CONT_POLY,107nymous_ +V 1200,18000,CONT_DIF_N,108nymous_ +V 5000,14800,CONT_DIF_P,109nymous_ +V 1200,14800,CONT_DIF_P,110nymous_ +V 0,14800,CONT_DIF_P,111nymous_ +V 3800,14800,CONT_DIF_P,112nymous_ +V 5000,18000,CONT_VIA,113nymous_ +V 1000,3000,CONT_VIA2,153nymous_ +V 1000,8000,CONT_VIA,152nymous_ +V 3000,13400,CONT_BODY_N,160nymous_ +V 2000,13400,CONT_BODY_N,159nymous_ +V 3000,17000,CONT_VIA,158nymous_ +V 2000,16000,CONT_VIA,157nymous_ +V 0,18000,CONT_DIF_N,156nymous_ +V 3000,18000,CONT_DIF_N,155nymous_ +V 1000,3000,CONT_VIA,154nymous_ +V 0,19000,CONT_DIF_N,114nymous_ +V 0,7000,CONT_DIF_P,115nymous_ +V 1200,7000,CONT_DIF_P,116nymous_ +V 1200,8000,CONT_DIF_P,117nymous_ +V 0,8000,CONT_DIF_P,118nymous_ +V 0,3000,CONT_DIF_N,119nymous_ +V 1200,3000,CONT_DIF_N,120nymous_ +V 1200,2000,CONT_DIF_N,121nymous_ +V 0,2000,CONT_DIF_N,122nymous_ +V 3800,8000,CONT_DIF_P,123nymous_ +V 5000,8000,CONT_DIF_P,124nymous_ +V 3800,7000,CONT_DIF_P,125nymous_ +V 5000,7000,CONT_DIF_P,126nymous_ +V 3800,2000,CONT_DIF_N,127nymous_ +V 5000,2000,CONT_DIF_N,128nymous_ +V 3800,3000,CONT_DIF_N,129nymous_ +V 5000,3000,CONT_DIF_N,130nymous_ +V 0,9000,CONT_DIF_P,131nymous_ +V 5000,9000,CONT_DIF_P,132nymous_ +V 0,10000,CONT_DIF_P,133nymous_ +V 0,11000,CONT_DIF_P,134nymous_ +V 5000,10000,CONT_DIF_P,135nymous_ +V 5000,11000,CONT_DIF_P,136nymous_ +V 0,12000,CONT_DIF_P,137nymous_ +V 1200,12000,CONT_DIF_P,138nymous_ +V 3800,12000,CONT_DIF_P,139nymous_ +V 5000,12000,CONT_DIF_P,140nymous_ +V 5000,19000,CONT_DIF_N,141nymous_ +V 5000,17000,CONT_POLY,142nymous_ +V 2400,2000,CONT_DIF_N,143nymous_ +V 2400,8000,CONT_DIF_P,144nymous_ +V 2400,11000,CONT_DIF_P,145nymous_ +V 2400,9000,CONT_DIF_P,146nymous_ +V 2400,10000,CONT_DIF_P,147nymous_ +V 2400,14800,CONT_DIF_P,148nymous_ +V 1000,12000,CONT_VIA2,149nymous_ +V 1000,12000,CONT_VIA,150nymous_ +V 1000,8000,CONT_VIA2,151nymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_mid_buf_2.vbe b/pdks/symbolic/nrflib/cells/rf_mid_buf_2.vbe new file mode 100644 index 000000000..3545d57e9 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_mid_buf_2.vbe @@ -0,0 +1,23 @@ +ENTITY rf_mid_buf_2 IS +PORT ( + selr : in BIT; + selw : in BIT; + nck : in BIT; + read : out BIT; + write : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_mid_buf_2; + +ARCHITECTURE VBE OF rf_mid_buf_2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_mid_buf_2" + SEVERITY WARNING; + + read <= selr; + write <= selw and nck; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_mid_buf_4.ap b/pdks/symbolic/nrflib/cells/rf_mid_buf_4.ap new file mode 100644 index 000000000..6fae045e7 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_mid_buf_4.ap @@ -0,0 +1,303 @@ +V ALLIANCE : 6 +H rf_mid_buf_4,P,22/4/2016,100 +A 0,0,5000,40000 +S 850,28000,2150,28000,600,4nonymous_,RIGHT,ALU2 +S 0,10600,5000,10600,1200,vdd,RIGHT,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,30600,5000,30600,1200,vdd,RIGHT,CALU1 +S 0,29400,5000,29400,1200,vdd,RIGHT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,20600,5000,20600,1200,vss,RIGHT,CALU1 +S 0,19400,5000,19400,1200,vss,RIGHT,CALU1 +S 0,39400,5000,39400,1200,vss,RIGHT,CALU1 +S 2850,3000,4150,3000,600,0nonymous_,RIGHT,ALU2 +S 2850,8000,4150,8000,600,1nonymous_,RIGHT,ALU2 +S 2850,12000,4150,12000,600,2nonymous_,RIGHT,ALU2 +S 850,37000,2150,37000,600,3nonymous_,RIGHT,ALU2 +S 3800,27700,3800,33300,600,33onymous_,UP,PDIF +S 4400,27500,4400,33500,200,32onymous_,UP,PTRANS +S 1800,27500,1800,33500,200,31onymous_,UP,PTRANS +S 5000,27700,5000,33300,600,30onymous_,UP,PDIF +S 3200,27500,3200,33500,200,29onymous_,UP,PTRANS +S 0,27700,0,33300,600,28onymous_,UP,PDIF +S 4400,26600,4400,27200,200,27onymous_,UP,POLY +S 3200,26600,3200,27200,200,26onymous_,UP,POLY +S 1800,26600,1800,27200,200,25onymous_,UP,POLY +S 600,26600,600,27200,200,24onymous_,UP,POLY +S 1000,26800,3800,26800,300,23onymous_,RIGHT,ALU1 +S 1200,24200,1200,26800,300,22onymous_,UP,ALU1 +S 1200,22000,3800,22000,300,21onymous_,RIGHT,ALU1 +S 1200,24200,3800,24200,300,20onymous_,RIGHT,ALU1 +S 50,37000,4950,37000,300,19onymous_,RIGHT,TALU2 +S 50,32000,4950,32000,300,18onymous_,RIGHT,TALU2 +S 50,28000,4950,28000,300,17onymous_,RIGHT,TALU2 +S 50,12000,4950,12000,300,16onymous_,RIGHT,TALU2 +S 50,8000,4950,8000,300,15onymous_,RIGHT,TALU2 +S 50,3000,4950,3000,300,14onymous_,RIGHT,TALU2 +S 850,32000,2150,32000,600,5nonymous_,RIGHT,ALU2 +S 3000,17000,4000,17000,300,6nonymous_,RIGHT,ALU1 +S 1000,23000,2000,23000,300,7nonymous_,RIGHT,ALU1 +S 0,24200,0,33000,300,8nonymous_,UP,ALU1 +S 2600,29000,2600,32000,300,9nonymous_,UP,ALU1 +S 5000,24200,5000,33000,300,10onymous_,UP,ALU1 +S 0,7000,0,15800,300,11onymous_,UP,ALU1 +S 2600,8000,2600,11000,300,12onymous_,UP,ALU1 +S 5000,7000,5000,15800,300,13onymous_,UP,ALU1 +S 600,27500,600,33500,200,34onymous_,UP,PTRANS +S 1800,21500,1800,22300,200,55onymous_,UP,NTRANS +S 1200,21700,1200,22100,600,56onymous_,UP,NDIF +S 600,21500,600,22300,200,57onymous_,UP,NTRANS +S 4400,22600,4400,23600,200,58onymous_,UP,POLY +S 3200,22600,3200,23600,200,59onymous_,UP,POLY +S 1800,22600,1800,23600,200,60onymous_,UP,POLY +S 600,35800,4400,35800,200,61onymous_,RIGHT,POLY +S 4400,33800,4400,36000,200,62onymous_,UP,POLY +S 3200,33800,3200,36000,200,63onymous_,UP,POLY +S 1800,33800,1800,36000,200,64onymous_,UP,POLY +S 1200,37000,3800,37000,300,68onymous_,RIGHT,ALU1 +S -1000,27000,6000,27000,7600,67onymous_,RIGHT,NWELL +S -1000,32200,6000,32200,6400,66onymous_,RIGHT,NWELL +S 600,33800,600,36000,200,65onymous_,UP,POLY +S 4400,21500,4400,22300,200,54onymous_,UP,NTRANS +S 3200,21500,3200,22300,200,53onymous_,UP,NTRANS +S 3800,21700,3800,22100,600,52onymous_,UP,NDIF +S 5000,20900,5000,22100,600,51onymous_,UP,NDIF +S 0,20900,0,22100,600,50onymous_,UP,NDIF +S 2400,20900,2400,22100,600,49onymous_,UP,NDIF +S 2600,20900,2600,22100,600,48onymous_,UP,NDIF +S 600,23000,4400,23000,600,47onymous_,RIGHT,POLY +S 5000,24100,5000,25500,600,46onymous_,UP,PDIF +S 4400,23900,4400,25700,200,45onymous_,UP,PTRANS +S 3800,24100,3800,25500,400,44onymous_,UP,PDIF +S 3200,23900,3200,25700,200,43onymous_,UP,PTRANS +S 2600,24100,2600,25500,600,42onymous_,UP,PDIF +S 3800,22000,3800,24200,300,41onymous_,UP,ALU1 +S 2600,25200,5000,25200,300,40onymous_,RIGHT,ALU1 +S 5000,21000,5000,22000,300,39onymous_,UP,ALU1 +S 0,21000,0,22000,300,38onymous_,UP,ALU1 +S 2600,27700,2600,33300,600,37onymous_,UP,PDIF +S 2400,27700,2400,33300,600,36onymous_,UP,PDIF +S 1200,27700,1200,33300,600,35onymous_,UP,PDIF +S 600,36300,600,39500,200,78onymous_,UP,NTRANS +S 4400,36300,4400,39500,200,77onymous_,UP,NTRANS +S 3800,36500,3800,39300,600,76onymous_,UP,NDIF +S 5000,36500,5000,39300,600,75onymous_,UP,NDIF +S 600,22600,600,23600,200,74onymous_,UP,POLY +S 2400,24100,2400,25500,600,69onymous_,UP,PDIF +S 600,23900,600,25700,200,70onymous_,UP,PTRANS +S 1200,24100,1200,25500,400,71onymous_,UP,PDIF +S 1800,23900,1800,25700,200,72onymous_,UP,PTRANS +S 0,24100,0,25500,600,73onymous_,UP,PDIF +S 1200,36500,1200,39300,600,79onymous_,UP,NDIF +S 1800,36300,1800,39500,200,80onymous_,UP,NTRANS +S 2600,36500,2600,39300,600,81onymous_,UP,NDIF +S 2400,36500,2400,39300,600,82onymous_,UP,NDIF +S 3200,36300,3200,39500,200,83onymous_,UP,NTRANS +S 0,36500,0,39300,600,84onymous_,UP,NDIF +S 1200,28000,3800,28000,300,85onymous_,RIGHT,ALU1 +S 600,26800,4400,26800,600,86onymous_,RIGHT,POLY +S 1200,32000,1200,38000,300,87onymous_,UP,ALU1 +S 3800,32000,3800,38000,300,88onymous_,UP,ALU1 +S 0,37000,0,39200,300,89onymous_,UP,ALU1 +S 5000,37000,5000,39200,300,90onymous_,UP,ALU1 +S 2600,38000,2600,39200,300,91onymous_,UP,ALU1 +S 4400,17000,5200,17000,600,92onymous_,RIGHT,POLY +S 4400,16400,4400,17400,200,93onymous_,UP,POLY +S 600,16400,600,17400,200,94onymous_,UP,POLY +S -200,17000,600,17000,600,95onymous_,RIGHT,POLY +S 1200,17900,1200,19300,600,96onymous_,UP,NDIF +S 600,17700,600,19500,200,97onymous_,UP,NTRANS +S 3800,17900,3800,19300,600,98onymous_,UP,NDIF +S 4400,17700,4400,19500,200,99onymous_,UP,NTRANS +S 2600,15800,5000,15800,300,100nymous_,RIGHT,ALU1 +S 5000,17000,5000,18000,300,101nymous_,UP,ALU1 +S 5000,14500,5000,15900,600,102nymous_,UP,PDIF +S 3800,14500,3800,15900,600,103nymous_,UP,PDIF +S 3200,14300,3200,16100,200,104nymous_,UP,PTRANS +S 4400,14300,4400,16100,200,105nymous_,UP,PTRANS +S 5000,17900,5000,19300,600,106nymous_,UP,NDIF +S 600,4200,4400,4200,200,107nymous_,RIGHT,POLY +S 4400,4000,4400,6200,200,108nymous_,UP,POLY +S 3200,4000,3200,6200,200,109nymous_,UP,POLY +S 1800,4000,1800,6200,200,110nymous_,UP,POLY +S 600,4000,600,6200,200,111nymous_,UP,POLY +S -1000,7800,6000,7800,6400,112nymous_,RIGHT,NWELL +S -1000,13000,6000,13000,7600,113nymous_,RIGHT,NWELL +S 600,12800,600,13400,200,153nymous_,UP,POLY +S 0,6700,0,12300,600,152nymous_,UP,PDIF +S 2600,6700,2600,12300,600,151nymous_,UP,PDIF +S 1800,6500,1800,12500,200,150nymous_,UP,PTRANS +S 4400,6500,4400,12500,200,149nymous_,UP,PTRANS +S 5000,6700,5000,12300,600,148nymous_,UP,PDIF +S 3200,6500,3200,12500,200,147nymous_,UP,PTRANS +S 2400,6700,2400,12300,600,146nymous_,UP,PDIF +S 1200,6700,1200,12300,600,145nymous_,UP,PDIF +S 600,6500,600,12500,200,144nymous_,UP,PTRANS +S 3800,6700,3800,12300,600,143nymous_,UP,PDIF +S 2600,800,2600,2000,300,142nymous_,UP,ALU1 +S 5000,800,5000,3000,300,141nymous_,UP,ALU1 +S 0,800,0,3000,300,140nymous_,UP,ALU1 +S 3800,2000,3800,8000,300,139nymous_,UP,ALU1 +S 1200,2000,1200,8000,300,138nymous_,UP,ALU1 +S 3800,13200,3800,14800,300,137nymous_,UP,ALU1 +S 2600,14800,2600,15800,300,136nymous_,UP,ALU1 +S 1200,13200,1200,18000,300,135nymous_,UP,ALU1 +S 1200,18000,2600,18000,300,164nymous_,RIGHT,ALU1 +S 1800,16400,1800,17400,200,163nymous_,UP,POLY +S 3200,16400,3200,17400,200,162nymous_,UP,POLY +S 1800,17000,3200,17000,600,161nymous_,RIGHT,POLY +S 2400,17900,2400,19300,600,160nymous_,UP,NDIF +S 1800,17700,1800,19500,200,159nymous_,UP,NTRANS +S 3200,17700,3200,19500,200,158nymous_,UP,NTRANS +S 2600,17900,2600,19300,600,157nymous_,UP,NDIF +S 4400,12800,4400,13400,200,156nymous_,UP,POLY +S 3200,12800,3200,13400,200,155nymous_,UP,POLY +S 1800,12800,1800,13400,200,154nymous_,UP,POLY +S 1200,3000,3800,3000,300,114nymous_,RIGHT,ALU1 +S 0,17900,0,19300,600,115nymous_,UP,NDIF +S 2400,14500,2400,15900,600,116nymous_,UP,PDIF +S 600,14300,600,16100,200,117nymous_,UP,PTRANS +S 1200,14500,1200,15900,400,118nymous_,UP,PDIF +S 1800,14300,1800,16100,200,119nymous_,UP,PTRANS +S 0,14500,0,15900,600,120nymous_,UP,PDIF +S 0,17000,0,18000,300,121nymous_,UP,ALU1 +S 5000,700,5000,3500,600,122nymous_,UP,NDIF +S 3800,700,3800,3500,600,123nymous_,UP,NDIF +S 4400,500,4400,3700,200,124nymous_,UP,NTRANS +S 600,500,600,3700,200,125nymous_,UP,NTRANS +S 1200,700,1200,3500,600,126nymous_,UP,NDIF +S 1800,500,1800,3700,200,127nymous_,UP,NTRANS +S 2600,700,2600,3500,600,128nymous_,UP,NDIF +S 2400,700,2400,3500,600,129nymous_,UP,NDIF +S 3200,500,3200,3700,200,130nymous_,UP,NTRANS +S 0,700,0,3500,600,131nymous_,UP,NDIF +S 1200,12000,3800,12000,300,132nymous_,RIGHT,ALU1 +S 600,13200,4400,13200,600,133nymous_,RIGHT,POLY +S 1200,13200,3800,13200,300,134nymous_,RIGHT,ALU1 +S -150,18000,5150,18000,600,nck,RIGHT,CALU2 +S 4000,2850,4000,12150,400,write,UP,CALU3 +S 1000,27850,1000,37150,400,read,UP,CALU3 +S 2850,17000,3150,17000,600,selw,RIGHT,CALU2 +S 1850,23000,2150,23000,600,selr,RIGHT,CALU2 +V 0,25200,CONT_DIF_P,177nymous_ +V 2000,23000,CONT_VIA,176nymous_ +V 2000,23000,CONT_POLY,175nymous_ +V 1200,22000,CONT_DIF_N,174nymous_ +V 2400,21000,CONT_DIF_N,173nymous_ +V 5000,21000,CONT_DIF_N,172nymous_ +V 3800,24200,CONT_DIF_P,171nymous_ +V 2600,25200,CONT_DIF_P,170nymous_ +V 3800,22000,CONT_DIF_N,169nymous_ +V 5000,24200,CONT_DIF_P,168nymous_ +V 5000,25200,CONT_DIF_P,167nymous_ +V 5000,22000,CONT_DIF_N,166nymous_ +V 0,22000,CONT_DIF_N,165nymous_ +V 1200,25200,CONT_DIF_P,178nymous_ +V 5000,33000,CONT_DIF_P,179nymous_ +V 3800,33000,CONT_DIF_P,180nymous_ +V 3800,32000,CONT_DIF_P,181nymous_ +V 5000,32000,CONT_DIF_P,182nymous_ +V 5000,37000,CONT_DIF_N,183nymous_ +V 3800,37000,CONT_DIF_N,184nymous_ +V 5000,39200,CONT_DIF_N,185nymous_ +V 3800,38000,CONT_DIF_N,186nymous_ +V 5000,38000,CONT_DIF_N,187nymous_ +V 1200,32000,CONT_DIF_P,188nymous_ +V 0,32000,CONT_DIF_P,189nymous_ +V 1200,33000,CONT_DIF_P,190nymous_ +V 0,33000,CONT_DIF_P,191nymous_ +V 1200,38000,CONT_DIF_N,192nymous_ +V 0,38000,CONT_DIF_N,193nymous_ +V 0,39200,CONT_DIF_N,194nymous_ +V 1200,37000,CONT_DIF_N,195nymous_ +V 0,37000,CONT_DIF_N,196nymous_ +V 5000,31000,CONT_DIF_P,197nymous_ +V 0,31000,CONT_DIF_P,198nymous_ +V 5000,30000,CONT_DIF_P,199nymous_ +V 5000,29000,CONT_DIF_P,200nymous_ +V 0,30000,CONT_DIF_P,201nymous_ +V 0,29000,CONT_DIF_P,202nymous_ +V 5000,28000,CONT_DIF_P,203nymous_ +V 3800,28000,CONT_DIF_P,204nymous_ +V 1200,28000,CONT_DIF_P,205nymous_ +V 0,28000,CONT_DIF_P,206nymous_ +V 0,21000,CONT_DIF_N,207nymous_ +V 2600,38000,CONT_DIF_N,208nymous_ +V 2600,39200,CONT_DIF_N,209nymous_ +V 2600,32000,CONT_DIF_P,210nymous_ +V 2600,29000,CONT_DIF_P,211nymous_ +V 2600,31000,CONT_DIF_P,212nymous_ +V 2600,30000,CONT_DIF_P,213nymous_ +V 1200,26800,CONT_POLY,214nymous_ +V 3800,26800,CONT_POLY,215nymous_ +V 0,24200,CONT_DIF_P,216nymous_ +V 1200,24200,CONT_DIF_P,217nymous_ +V 2600,26800,CONT_POLY,218nymous_ +V 1000,28000,CONT_VIA,219nymous_ +V 1000,32000,CONT_VIA,220nymous_ +V 1200,37000,CONT_VIA,221nymous_ +V 1000,28000,CONT_VIA2,222nymous_ +V 1000,32000,CONT_VIA2,223nymous_ +V 1200,37000,CONT_VIA2,224nymous_ +V 0,14800,CONT_DIF_P,225nymous_ +V 3800,14800,CONT_DIF_P,226nymous_ +V 5000,14800,CONT_DIF_P,227nymous_ +V 1200,14800,CONT_DIF_P,228nymous_ +V 5000,15800,CONT_DIF_P,229nymous_ +V 2600,15800,CONT_DIF_P,230nymous_ +V 0,18000,CONT_VIA,231nymous_ +V 3000,17000,CONT_VIA,232nymous_ +V 5000,18000,CONT_VIA,233nymous_ +V 5000,17000,CONT_POLY,234nymous_ +V 5000,19000,CONT_DIF_N,235nymous_ +V 5000,7000,CONT_DIF_P,236nymous_ +V 3800,7000,CONT_DIF_P,237nymous_ +V 3800,8000,CONT_DIF_P,238nymous_ +V 5000,8000,CONT_DIF_P,239nymous_ +V 5000,3000,CONT_DIF_N,240nymous_ +V 3800,3000,CONT_DIF_N,241nymous_ +V 5000,800,CONT_DIF_N,242nymous_ +V 3800,2000,CONT_DIF_N,243nymous_ +V 5000,2000,CONT_DIF_N,244nymous_ +V 1200,8000,CONT_DIF_P,245nymous_ +V 0,8000,CONT_DIF_P,246nymous_ +V 1200,7000,CONT_DIF_P,247nymous_ +V 0,7000,CONT_DIF_P,248nymous_ +V 1200,2000,CONT_DIF_N,249nymous_ +V 0,2000,CONT_DIF_N,250nymous_ +V 0,800,CONT_DIF_N,251nymous_ +V 1200,3000,CONT_DIF_N,252nymous_ +V 0,3000,CONT_DIF_N,253nymous_ +V 5000,9000,CONT_DIF_P,254nymous_ +V 0,9000,CONT_DIF_P,255nymous_ +V 5000,10000,CONT_DIF_P,256nymous_ +V 5000,11000,CONT_DIF_P,257nymous_ +V 0,10000,CONT_DIF_P,258nymous_ +V 0,11000,CONT_DIF_P,259nymous_ +V 5000,12000,CONT_DIF_P,260nymous_ +V 3800,12000,CONT_DIF_P,261nymous_ +V 1200,12000,CONT_DIF_P,262nymous_ +V 0,12000,CONT_DIF_P,263nymous_ +V 0,19000,CONT_DIF_N,264nymous_ +V 0,17000,CONT_POLY,265nymous_ +V 2600,2000,CONT_DIF_N,266nymous_ +V 2600,800,CONT_DIF_N,267nymous_ +V 3000,17000,CONT_POLY,268nymous_ +V 2600,8000,CONT_DIF_P,269nymous_ +V 2600,11000,CONT_DIF_P,270nymous_ +V 2600,9000,CONT_DIF_P,271nymous_ +V 2600,10000,CONT_DIF_P,272nymous_ +V 1200,13200,CONT_POLY,273nymous_ +V 3800,13200,CONT_POLY,274nymous_ +V 0,15800,CONT_DIF_P,275nymous_ +V 2600,14800,CONT_DIF_P,276nymous_ +V 1200,15800,CONT_DIF_P,277nymous_ +V 2600,13200,CONT_POLY,278nymous_ +V 4000,12000,CONT_VIA2,279nymous_ +V 4000,12000,CONT_VIA,280nymous_ +V 4000,8000,CONT_VIA2,281nymous_ +V 4000,8000,CONT_VIA,282nymous_ +V 4000,3000,CONT_VIA2,283nymous_ +V 4000,3000,CONT_VIA,284nymous_ +V 2600,18000,CONT_DIF_N,285nymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_mid_buf_4.vbe b/pdks/symbolic/nrflib/cells/rf_mid_buf_4.vbe new file mode 100644 index 000000000..18cc9b4d9 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_mid_buf_4.vbe @@ -0,0 +1,23 @@ +ENTITY rf_mid_buf_4 IS +PORT ( + selr : in BIT; + selw : in BIT; + nck : in BIT; + read : out BIT; + write : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_mid_buf_4; + +ARCHITECTURE VBE OF rf_mid_buf_4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_mid_buf_4" + SEVERITY WARNING; + + read <= selr; + write <= selw and nck; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_mid_mem.ap b/pdks/symbolic/nrflib/cells/rf_mid_mem.ap new file mode 100644 index 000000000..d38dbd9e6 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_mid_mem.ap @@ -0,0 +1,97 @@ +V ALLIANCE : 6 +H rf_mid_mem,P,22/4/2016,100 +A 0,0,5000,10000 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 1050,6000,2950,6000,300,0nonymous_,RIGHT,TALU2 +S 2080,700,3720,700,600,1nonymous_,RIGHT,PTIE +S 5000,1700,5000,2300,600,2nonymous_,UP,NDIF +S 3800,1700,3800,2300,600,3nonymous_,UP,NDIF +S 4400,1500,4400,2500,200,4nonymous_,UP,NTRANS +S 3200,9400,3200,9600,200,38onymous_,UP,POLY +S 1200,9600,3200,9600,200,37onymous_,RIGHT,POLY +S 1200,2000,1200,2800,300,36onymous_,UP,ALU1 +S 5000,4500,5000,5300,600,35onymous_,UP,NDIF +S -600,8600,5600,8600,4400,34onymous_,RIGHT,NWELL +S 2000,5000,3000,5000,300,13onymous_,RIGHT,ALU1 +S 600,5600,2000,5600,300,12onymous_,RIGHT,ALU1 +S 4000,2000,5000,2000,300,11onymous_,RIGHT,ALU1 +S 3000,6000,3000,6800,300,10onymous_,UP,ALU1 +S 5000,4000,5000,5000,300,9nonymous_,UP,ALU1 +S 2000,5000,2000,5600,300,8nonymous_,UP,ALU1 +S 3050,3000,3950,3000,300,7nonymous_,RIGHT,TALU2 +S 2850,3000,4150,3000,600,6nonymous_,RIGHT,ALU2 +S 3200,3000,4200,3000,300,5nonymous_,RIGHT,ALU1 +S 1600,7800,3000,7800,300,14onymous_,RIGHT,ALU1 +S 1600,6600,1600,7800,300,15onymous_,UP,ALU1 +S 600,5600,600,8000,300,16onymous_,UP,ALU1 +S 3800,3000,4400,3000,600,17onymous_,RIGHT,POLY +S 2600,3300,2600,3500,800,18onymous_,UP,NDIF +S 3200,4500,3200,5300,2000,19onymous_,UP,NDIF +S 2000,1400,2000,2200,200,30onymous_,UP,POLY +S 900,1400,1500,1400,200,31onymous_,RIGHT,NTRANS +S 3000,5800,4400,5800,200,32onymous_,RIGHT,POLY +S 2400,7200,4000,7200,200,33onymous_,RIGHT,POLY +S 1800,1400,2000,1400,200,29onymous_,RIGHT,POLY +S 2200,2000,3000,2000,300,28onymous_,RIGHT,ALU1 +S 0,600,0,4600,300,27onymous_,UP,ALU1 +S 1000,4000,1800,4000,200,26onymous_,RIGHT,POLY +S 1200,6600,1800,6600,600,25onymous_,RIGHT,POLY +S 1800,4300,1800,5500,200,24onymous_,UP,NTRANS +S 1800,5800,1800,6800,200,23onymous_,UP,POLY +S 600,4500,600,5300,1600,22onymous_,UP,NDIF +S 0,4600,1000,4600,300,21onymous_,RIGHT,ALU1 +S 4400,4300,4400,5500,200,20onymous_,UP,NTRANS +S 2100,9000,2700,9000,600,39onymous_,RIGHT,PDIF +S 3400,8700,3400,9100,600,40onymous_,UP,PTRANS +S 4100,8400,4300,8400,1400,41onymous_,RIGHT,PDIF +S 2400,7500,2400,8100,200,42onymous_,UP,PTRANS +S 600,7300,600,9100,600,43onymous_,UP,PDIF +S 1800,7300,1800,9100,600,44onymous_,UP,PDIF +S 1200,7100,1200,9300,200,45onymous_,UP,PTRANS +S 1400,3300,1400,3700,1000,46onymous_,UP,NTRANS +S 850,6000,3150,6000,600,47onymous_,RIGHT,ALU2 +S 3000,1700,3000,3500,600,48onymous_,UP,NDIF +S 3200,1700,3200,3500,600,49onymous_,UP,NDIF +S 3600,1700,3600,2300,1000,50onymous_,UP,NDIF +S 0,3500,0,5300,600,51onymous_,UP,NDIF +S 400,3500,400,5300,400,52onymous_,UP,NDIF +S 3879,10000,6120,10000,600,53onymous_,RIGHT,NTIE +S 2200,4000,4000,4000,300,latch,RIGHT,ALU1 +S 2200,2000,2200,4000,300,latch,UP,ALU1 +S 4000,4000,4000,8000,300,latch,UP,ALU1 +S 3850,2000,5150,2000,600,dinx,RIGHT,CALU2 +S 4000,2850,4000,3150,400,write,UP,CALU3 +S 1000,5850,1000,6150,400,read,UP,CALU3 +S 3850,5000,5150,5000,600,rbus,RIGHT,CALU2 +V 3600,600,CONT_BODY_P,54onymous_ +V 5000,10000,CONT_BODY_N,55onymous_ +V 4000,3000,CONT_VIA,56onymous_ +V 4000,3000,CONT_VIA2,57onymous_ +V 4000,3000,CONT_POLY,58onymous_ +V 4000,10000,CONT_BODY_N,59onymous_ +V 5000,5000,CONT_DIF_N,60onymous_ +V 1000,4600,CONT_DIF_N,61onymous_ +V 3000,5000,CONT_DIF_N,62onymous_ +V 1600,6600,CONT_POLY,63onymous_ +V 0,4600,CONT_DIF_N,64onymous_ +V 3000,2000,CONT_DIF_N,65onymous_ +V 1200,800,CONT_DIF_N,66onymous_ +V 2200,2000,CONT_POLY,67onymous_ +V 3000,6000,CONT_POLY,68onymous_ +V 4200,8000,CONT_DIF_P,73onymous_ +V 5000,2000,CONT_DIF_N,72onymous_ +V 1200,2800,CONT_POLY,71onymous_ +V 1200,2000,CONT_DIF_N,70onymous_ +V 4000,7000,CONT_POLY,69onymous_ +V 6000,10000,CONT_BODY_N,83onymous_ +V 0,3600,CONT_DIF_N,82onymous_ +V 2400,600,CONT_BODY_P,81onymous_ +V 5000,5000,CONT_VIA,80onymous_ +V 5000,2000,CONT_VIA,79onymous_ +V 1000,6000,CONT_VIA2,78onymous_ +V 3000,6000,CONT_VIA,77onymous_ +V 600,8000,CONT_DIF_P,76onymous_ +V 1800,9000,CONT_DIF_P,75onymous_ +V 3000,7800,CONT_DIF_P,74onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_mid_mem.vbe b/pdks/symbolic/nrflib/cells/rf_mid_mem.vbe new file mode 100644 index 000000000..abe963940 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_mid_mem.vbe @@ -0,0 +1,30 @@ +ENTITY rf_mid_mem IS +PORT ( + dinx : in BIT; + write : in BIT; + read : in BIT; + rbus : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rf_mid_mem; + +ARCHITECTURE VBE OF rf_mid_mem IS + SIGNAL latch : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_mid_mem" + SEVERITY WARNING; + + label0 : BLOCK (write = '1') + BEGIN + latch <= GUARDED dinx; + END BLOCK label0; + + label1 : BLOCK (read = '1') + BEGIN + rbus <= GUARDED latch; + END BLOCK label1; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_mid_mem_r0.ap b/pdks/symbolic/nrflib/cells/rf_mid_mem_r0.ap new file mode 100644 index 000000000..5d05ce28d --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_mid_mem_r0.ap @@ -0,0 +1,37 @@ +V ALLIANCE : 6 +H rf_mid_mem_r0,P,22/4/2016,100 +A 0,0,5000,10000 +S 3850,2000,5150,2000,600,dinx,RIGHT,CALU2 +S 4000,2850,4000,3150,400,write,UP,CALU3 +S 1000,5850,1000,6150,400,read,UP,CALU3 +S 3850,5000,5150,5000,600,rbus,RIGHT,CALU2 +S 1050,6000,2950,6000,300,obs,RIGHT,TALU2 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 3679,10000,5120,10000,600,0nonymous_,RIGHT,NTIE +S 2280,700,5120,700,600,1nonymous_,RIGHT,PTIE +S 0,4600,3800,4600,300,2nonymous_,RIGHT,ALU1 +S 3800,4500,3800,5300,600,3nonymous_,UP,NDIF +S 4400,4300,4400,5500,200,4nonymous_,UP,NTRANS +S 2000,6000,3000,6000,300,12onymous_,RIGHT,ALU1 +S 5000,4000,5000,5000,300,11onymous_,UP,ALU1 +S 850,6000,3150,6000,600,10onymous_,RIGHT,ALU2 +S 5000,4500,5000,5300,600,9nonymous_,UP,NDIF +S -600,8600,5600,8600,4400,8nonymous_,RIGHT,NWELL +S 3000,5800,4400,5800,200,7nonymous_,RIGHT,POLY +S 0,3300,0,5300,600,6nonymous_,UP,NDIF +S 0,600,0,4600,300,5nonymous_,UP,ALU1 +V 5000,10000,CONT_BODY_N,13onymous_ +V 3800,600,CONT_BODY_P,14onymous_ +V 5000,600,CONT_BODY_P,15onymous_ +V 2600,600,CONT_BODY_P,16onymous_ +V 5000,5000,CONT_VIA,25onymous_ +V 1000,6000,CONT_VIA2,24onymous_ +V 3000,6000,CONT_VIA,23onymous_ +V 0,3400,CONT_DIF_N,22onymous_ +V 3000,6000,CONT_POLY,21onymous_ +V 0,4600,CONT_DIF_N,20onymous_ +V 5000,5000,CONT_DIF_N,19onymous_ +V 4000,10000,CONT_BODY_N,18onymous_ +V 3800,4600,CONT_DIF_N,17onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_mid_mem_r0.vbe b/pdks/symbolic/nrflib/cells/rf_mid_mem_r0.vbe new file mode 100644 index 000000000..71c03d0eb --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_mid_mem_r0.vbe @@ -0,0 +1,25 @@ +ENTITY rf_mid_mem_r0 IS +PORT ( + dinx : in BIT; + write : in BIT; + read : in BIT; + rbus : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rf_mid_mem_r0; + +ARCHITECTURE VBE OF rf_mid_mem_r0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_mid_mem_r0" + SEVERITY WARNING; + + label1 : BLOCK (read = '1') + BEGIN + rbus <= GUARDED '0'; + END BLOCK label1; + + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_out_buf_2.ap b/pdks/symbolic/nrflib/cells/rf_out_buf_2.ap new file mode 100644 index 000000000..4f355a00f --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_out_buf_2.ap @@ -0,0 +1,94 @@ +V ALLIANCE : 6 +H rf_out_buf_2,P,22/4/2016,100 +A 0,0,11000,20000 +S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 +S 0,10600,11000,10600,1200,vdd,RIGHT,CALU1 +S 0,600,11000,600,1200,vss,RIGHT,CALU1 +S 0,19400,11000,19400,1200,vss,RIGHT,CALU1 +S -1000,15000,1000,15000,3600,0nonymous_,RIGHT,NWELL +S 1850,3000,4150,3000,600,1nonymous_,RIGHT,ALU2 +S 1850,8000,4150,8000,600,2nonymous_,RIGHT,ALU2 +S 1850,12000,4150,12000,600,3nonymous_,RIGHT,ALU2 +S 3600,12800,3600,14000,200,4nonymous_,UP,POLY +S 2400,6500,2400,12500,200,16onymous_,UP,PTRANS +S 3000,6700,3000,12300,600,15onymous_,UP,PDIF +S 3600,6500,3600,12500,200,14onymous_,UP,PTRANS +S 1800,6700,1800,12300,600,13onymous_,UP,PDIF +S 4200,6700,4200,12300,600,12onymous_,UP,PDIF +S 2050,3000,3950,3000,300,11onymous_,RIGHT,TALU2 +S 2050,8000,3950,8000,300,10onymous_,RIGHT,TALU2 +S 2050,12000,3950,12000,300,9nonymous_,RIGHT,TALU2 +S 2400,14000,3600,14000,600,8nonymous_,RIGHT,POLY +S 3000,14000,3000,18000,300,7nonymous_,UP,ALU1 +S 2400,12800,2400,14000,200,5nonymous_,UP,POLY +S 3000,12000,3000,13000,300,6nonymous_,UP,ALU1 +S 2400,500,2400,3700,200,17onymous_,UP,NTRANS +S 3600,500,3600,3700,200,18onymous_,UP,NTRANS +S 1800,700,1800,3500,600,19onymous_,UP,NDIF +S 3000,700,3000,3500,600,20onymous_,UP,NDIF +S 4200,700,4200,3500,600,21onymous_,UP,NDIF +S 2400,4000,2400,6200,200,22onymous_,UP,POLY +S 4200,7000,4200,12000,300,33onymous_,UP,ALU1 +S 1800,7000,1800,12000,300,34onymous_,UP,ALU1 +S 1680,19400,9120,19400,600,35onymous_,RIGHT,PTIE +S 5800,280,5800,3720,600,36onymous_,UP,PTIE +S 5800,5680,5800,13719,600,32onymous_,UP,NTIE +S 5800,6000,5800,13400,300,31onymous_,UP,ALU1 +S 5800,600,5800,3000,300,30onymous_,UP,ALU1 +S -600,7800,11600,7800,6000,29onymous_,RIGHT,NWELL +S -600,12200,11600,12200,6000,28onymous_,RIGHT,NWELL +S 3000,2000,3000,8000,300,27onymous_,UP,ALU1 +S 1800,800,1800,3000,300,26onymous_,UP,ALU1 +S 4200,800,4200,3000,300,25onymous_,UP,ALU1 +S 2400,4200,3600,4200,600,24onymous_,RIGHT,POLY +S 3600,4000,3600,6200,200,23onymous_,UP,POLY +S 3000,2850,3000,12150,400,xcks,UP,CALU3 +S 1850,18000,3150,18000,600,nck,RIGHT,CALU2 +V 5800,10600,CONT_BODY_N,38onymous_ +V 3000,14000,CONT_POLY,37onymous_ +V 5800,9300,CONT_BODY_N,39onymous_ +V 3000,3000,CONT_VIA,40onymous_ +V 3000,3000,CONT_VIA2,41onymous_ +V 3000,8000,CONT_VIA,42onymous_ +V 3000,8000,CONT_VIA2,43onymous_ +V 3000,12000,CONT_VIA,44onymous_ +V 3000,12000,CONT_VIA2,45onymous_ +V 4200,12000,CONT_DIF_P,46onymous_ +V 4200,8000,CONT_DIF_P,47onymous_ +V 4200,11000,CONT_DIF_P,48onymous_ +V 3000,7000,CONT_DIF_P,49onymous_ +V 3000,8000,CONT_DIF_P,50onymous_ +V 3000,12000,CONT_DIF_P,51onymous_ +V 4200,9000,CONT_DIF_P,52onymous_ +V 4200,7000,CONT_DIF_P,53onymous_ +V 1800,12000,CONT_DIF_P,54onymous_ +V 1800,11000,CONT_DIF_P,55onymous_ +V 1800,10000,CONT_DIF_P,56onymous_ +V 1800,9000,CONT_DIF_P,57onymous_ +V 1800,8000,CONT_DIF_P,58onymous_ +V 1800,7000,CONT_DIF_P,59onymous_ +V 1800,800,CONT_DIF_N,60onymous_ +V 1800,3000,CONT_DIF_N,61onymous_ +V 3000,2000,CONT_DIF_N,62onymous_ +V 3000,3000,CONT_DIF_N,63onymous_ +V 4200,2000,CONT_DIF_N,64onymous_ +V 4200,800,CONT_DIF_N,65onymous_ +V 4200,3000,CONT_DIF_N,66onymous_ +V 1800,2000,CONT_DIF_N,67onymous_ +V 5600,19400,CONT_BODY_P,68onymous_ +V 5800,12000,CONT_BODY_N,76onymous_ +V 5800,8000,CONT_BODY_N,75onymous_ +V 5800,7000,CONT_BODY_N,74onymous_ +V 5800,600,CONT_BODY_P,73onymous_ +V 5800,3000,CONT_BODY_P,72onymous_ +V 5800,1800,CONT_BODY_P,71onymous_ +V 8800,19400,CONT_BODY_P,83onymous_ +V 7800,19400,CONT_BODY_P,82onymous_ +V 6800,19400,CONT_BODY_P,81onymous_ +V 2000,19400,CONT_BODY_P,80onymous_ +V 3200,19400,CONT_BODY_P,79onymous_ +V 5800,13400,CONT_BODY_N,78onymous_ +V 5800,6000,CONT_BODY_N,77onymous_ +V 4400,19400,CONT_BODY_P,69onymous_ +V 3000,18000,CONT_VIA,70onymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_out_buf_2.vbe b/pdks/symbolic/nrflib/cells/rf_out_buf_2.vbe new file mode 100644 index 000000000..6262aed7b --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_out_buf_2.vbe @@ -0,0 +1,19 @@ +ENTITY rf_out_buf_2 IS +PORT ( + nck : in BIT; + xcks : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_out_buf_2; + +ARCHITECTURE VBE OF rf_out_buf_2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_out_buf_2" + SEVERITY WARNING; + + xcks <= not nck; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_out_buf_4.ap b/pdks/symbolic/nrflib/cells/rf_out_buf_4.ap new file mode 100644 index 000000000..b7c198f00 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_out_buf_4.ap @@ -0,0 +1,178 @@ +V ALLIANCE : 6 +H rf_out_buf_4,P,22/4/2016,100 +A 0,0,11000,40000 +S 0,29400,11000,29400,1200,vdd,RIGHT,CALU1 +S 0,30600,11000,30600,1200,vdd,RIGHT,CALU1 +S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 +S 0,10600,11000,10600,1200,vdd,RIGHT,CALU1 +S 9000,-150,9000,40150,2400,vdd,UP,CALU3 +S 0,19400,11000,19400,1200,vss,RIGHT,CALU1 +S 0,20600,11000,20600,1200,vss,RIGHT,CALU1 +S 0,39400,11000,39400,1200,vss,RIGHT,CALU1 +S 0,600,11000,600,1200,vss,RIGHT,CALU1 +S 880,5600,2120,5600,600,0nonymous_,RIGHT,NTIE +S 880,34400,2120,34400,600,1nonymous_,RIGHT,NTIE +S 3879,34400,5120,34400,600,2nonymous_,RIGHT,NTIE +S 5400,29080,5400,30920,600,3nonymous_,UP,NTIE +S 3879,26600,5120,26600,600,4nonymous_,RIGHT,NTIE +S 2400,12800,2400,27200,200,36onymous_,UP,POLY +S 3600,12800,3600,27200,200,35onymous_,UP,POLY +S 2400,18000,3600,18000,600,34onymous_,RIGHT,POLY +S 1800,800,1800,3000,300,33onymous_,UP,ALU1 +S 3000,2000,3000,8000,300,32onymous_,UP,ALU1 +S 4200,5600,4200,13400,300,31onymous_,UP,ALU1 +S 1800,5600,1800,13400,300,30onymous_,UP,ALU1 +S 3600,4000,3600,6200,200,29onymous_,UP,POLY +S 2400,4000,2400,6200,200,28onymous_,UP,POLY +S 2400,4200,3600,4200,200,27onymous_,RIGHT,POLY +S 1800,700,1800,3500,600,26onymous_,UP,NDIF +S 3000,700,3000,3500,600,25onymous_,UP,NDIF +S 2400,500,2400,3700,200,24onymous_,UP,NTRANS +S 3600,500,3600,3700,200,23onymous_,UP,NTRANS +S 1800,6700,1800,12300,600,22onymous_,UP,PDIF +S 3600,6500,3600,12500,200,21onymous_,UP,PTRANS +S 3000,6700,3000,12300,600,20onymous_,UP,PDIF +S 2400,6500,2400,12500,200,19onymous_,UP,PTRANS +S 4200,6700,4200,12300,600,18onymous_,UP,PDIF +S 5400,600,5400,3000,300,17onymous_,UP,ALU1 +S 3879,13400,5120,13400,600,6nonymous_,RIGHT,NTIE +S 880,26600,2120,26600,600,5nonymous_,RIGHT,NTIE +S 880,13400,2120,13400,600,7nonymous_,RIGHT,NTIE +S 5400,9080,5400,10920,600,8nonymous_,UP,NTIE +S 3879,5600,5120,5600,600,9nonymous_,RIGHT,NTIE +S 5400,280,5400,3320,600,10onymous_,UP,PTIE +S 9200,19080,9200,20920,600,11onymous_,UP,PTIE +S 5600,36680,5600,39720,600,12onymous_,UP,PTIE +S 8050,30000,9950,30000,300,13onymous_,RIGHT,TALU2 +S 8050,10000,9950,10000,300,14onymous_,RIGHT,TALU2 +S 3000,32000,3000,38000,300,55onymous_,UP,ALU1 +S -1000,7800,9200,7800,6400,56onymous_,RIGHT,NWELL +S -1000,13000,9200,13000,7600,57onymous_,RIGHT,NWELL +S -600,7800,11600,7800,6000,58onymous_,RIGHT,NWELL +S -600,12200,11600,12200,6000,59onymous_,RIGHT,NWELL +S -1000,32200,9200,32200,6400,60onymous_,RIGHT,NWELL +S -1000,27000,9200,27000,7600,61onymous_,RIGHT,NWELL +S -600,32200,11600,32200,6000,62onymous_,RIGHT,NWELL +S -600,27800,11600,27800,6000,63onymous_,RIGHT,NWELL +S 2050,3000,3950,3000,300,64onymous_,RIGHT,TALU2 +S 2050,32000,3950,32000,300,68onymous_,RIGHT,TALU2 +S 2050,28000,3950,28000,300,67onymous_,RIGHT,TALU2 +S 2050,12000,3950,12000,300,66onymous_,RIGHT,TALU2 +S 2050,8000,3950,8000,300,65onymous_,RIGHT,TALU2 +S 1800,37000,1800,39200,300,54onymous_,UP,ALU1 +S 4200,26600,4200,34400,300,53onymous_,UP,ALU1 +S 1800,26600,1800,34400,300,52onymous_,UP,ALU1 +S 4200,37000,4200,39200,300,51onymous_,UP,ALU1 +S 2400,33800,2400,36000,200,50onymous_,UP,POLY +S 2400,35800,3600,35800,200,49onymous_,RIGHT,POLY +S 3600,33800,3600,36000,200,48onymous_,UP,POLY +S 3000,36500,3000,39300,600,47onymous_,UP,NDIF +S 1800,36500,1800,39300,600,46onymous_,UP,NDIF +S 4200,36500,4200,39300,600,45onymous_,UP,NDIF +S 2400,36300,2400,39500,200,44onymous_,UP,NTRANS +S 3600,36300,3600,39500,200,43onymous_,UP,NTRANS +S 3000,27700,3000,33300,600,42onymous_,UP,PDIF +S 2400,27500,2400,33500,200,41onymous_,UP,PTRANS +S 1800,27700,1800,33300,600,40onymous_,UP,PDIF +S 3600,27500,3600,33500,200,39onymous_,UP,PTRANS +S 4200,27700,4200,33300,600,38onymous_,UP,PDIF +S 5600,37000,5600,39400,300,37onymous_,UP,ALU1 +S 4200,800,4200,3000,300,16onymous_,UP,ALU1 +S 4200,700,4200,3500,600,15onymous_,UP,NDIF +S 2850,8000,4150,8000,600,77onymous_,RIGHT,ALU2 +S 3000,2850,3000,37150,400,xcks,UP,CALU3 +S 2050,37000,3950,37000,300,69onymous_,RIGHT,TALU2 +S 3000,27000,3000,28000,300,70onymous_,UP,ALU1 +S 3000,17000,3000,18000,300,71onymous_,UP,ALU1 +S 3000,12000,3000,13000,300,72onymous_,UP,ALU1 +S 2850,37000,4150,37000,600,73onymous_,RIGHT,ALU2 +S 2850,32000,4150,32000,600,74onymous_,RIGHT,ALU2 +S 2850,28000,4150,28000,600,75onymous_,RIGHT,ALU2 +S 2850,12000,4150,12000,600,76onymous_,RIGHT,ALU2 +S 2850,3000,4150,3000,600,78onymous_,RIGHT,ALU2 +S 2850,18000,3150,18000,600,nck,RIGHT,CALU2 +V 3000,3000,CONT_VIA,79onymous_ +V 3000,3000,CONT_VIA2,80onymous_ +V 3000,8000,CONT_VIA,81onymous_ +V 3000,8000,CONT_VIA2,82onymous_ +V 3000,12000,CONT_VIA,83onymous_ +V 3000,12000,CONT_VIA2,84onymous_ +V 4200,2000,CONT_DIF_N,85onymous_ +V 4200,800,CONT_DIF_N,86onymous_ +V 4200,3000,CONT_DIF_N,87onymous_ +V 5400,600,CONT_BODY_P,88onymous_ +V 5400,3000,CONT_BODY_P,89onymous_ +V 5400,1800,CONT_BODY_P,90onymous_ +V 5400,9300,CONT_BODY_N,91onymous_ +V 5400,10600,CONT_BODY_N,92onymous_ +V 4200,12000,CONT_DIF_P,93onymous_ +V 4200,11000,CONT_DIF_P,94onymous_ +V 4200,10000,CONT_DIF_P,95onymous_ +V 4200,9000,CONT_DIF_P,96onymous_ +V 4200,8000,CONT_DIF_P,97onymous_ +V 4200,7000,CONT_DIF_P,98onymous_ +V 4200,13400,CONT_BODY_N,99onymous_ +V 4200,5600,CONT_BODY_N,100nymous_ +V 1800,13400,CONT_BODY_N,101nymous_ +V 1800,7000,CONT_DIF_P,102nymous_ +V 1800,8000,CONT_DIF_P,103nymous_ +V 1800,9000,CONT_DIF_P,104nymous_ +V 1800,10000,CONT_DIF_P,105nymous_ +V 1800,11000,CONT_DIF_P,106nymous_ +V 1800,12000,CONT_DIF_P,107nymous_ +V 1800,5600,CONT_BODY_N,108nymous_ +V 3000,12000,CONT_DIF_P,109nymous_ +V 3000,8000,CONT_DIF_P,110nymous_ +V 3000,7000,CONT_DIF_P,111nymous_ +V 3000,3000,CONT_DIF_N,112nymous_ +V 3000,2000,CONT_DIF_N,113nymous_ +V 3000,18000,CONT_VIA,156nymous_ +V 3000,18000,CONT_POLY,155nymous_ +V 1800,38000,CONT_DIF_N,154nymous_ +V 1800,39200,CONT_DIF_N,153nymous_ +V 1800,37000,CONT_DIF_N,152nymous_ +V 9000,30000,CONT_VIA,162nymous_ +V 9000,30000,CONT_VIA2,161nymous_ +V 9000,10000,CONT_VIA2,160nymous_ +V 9000,10000,CONT_VIA,159nymous_ +V 9200,20600,CONT_BODY_P,158nymous_ +V 9200,19400,CONT_BODY_P,157nymous_ +V 1800,3000,CONT_DIF_N,114nymous_ +V 1800,800,CONT_DIF_N,115nymous_ +V 1800,2000,CONT_DIF_N,116nymous_ +V 3000,28000,CONT_VIA,117nymous_ +V 3000,28000,CONT_VIA2,118nymous_ +V 3000,32000,CONT_VIA,119nymous_ +V 3000,32000,CONT_VIA2,120nymous_ +V 3000,37000,CONT_VIA,121nymous_ +V 3000,37000,CONT_VIA2,122nymous_ +V 5400,29400,CONT_BODY_N,123nymous_ +V 5400,30600,CONT_BODY_N,124nymous_ +V 5600,38200,CONT_BODY_P,125nymous_ +V 5600,37000,CONT_BODY_P,126nymous_ +V 5600,39400,CONT_BODY_P,127nymous_ +V 4200,34400,CONT_BODY_N,128nymous_ +V 4200,28000,CONT_DIF_P,129nymous_ +V 4200,29000,CONT_DIF_P,130nymous_ +V 4200,30000,CONT_DIF_P,131nymous_ +V 4200,31000,CONT_DIF_P,132nymous_ +V 4200,32000,CONT_DIF_P,133nymous_ +V 4200,33000,CONT_DIF_P,134nymous_ +V 4200,26600,CONT_BODY_N,135nymous_ +V 1800,26600,CONT_BODY_N,136nymous_ +V 3000,33000,CONT_DIF_P,137nymous_ +V 1800,33000,CONT_DIF_P,138nymous_ +V 1800,32000,CONT_DIF_P,139nymous_ +V 1800,31000,CONT_DIF_P,140nymous_ +V 1800,30000,CONT_DIF_P,141nymous_ +V 1800,29000,CONT_DIF_P,142nymous_ +V 1800,28000,CONT_DIF_P,143nymous_ +V 1800,34400,CONT_BODY_N,144nymous_ +V 3000,28000,CONT_DIF_P,145nymous_ +V 3000,32000,CONT_DIF_P,146nymous_ +V 4200,37000,CONT_DIF_N,147nymous_ +V 4200,38000,CONT_DIF_N,148nymous_ +V 4200,39200,CONT_DIF_N,149nymous_ +V 3000,37000,CONT_DIF_N,150nymous_ +V 3000,38000,CONT_DIF_N,151nymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_out_buf_4.vbe b/pdks/symbolic/nrflib/cells/rf_out_buf_4.vbe new file mode 100644 index 000000000..868f2527a --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_out_buf_4.vbe @@ -0,0 +1,19 @@ +ENTITY rf_out_buf_4 IS +PORT ( + nck : in BIT; + xcks : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_out_buf_4; + +ARCHITECTURE VBE OF rf_out_buf_4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_out_buf_4" + SEVERITY WARNING; + + xcks <= not nck; + +END; diff --git a/pdks/symbolic/nrflib/cells/rf_out_mem.ap b/pdks/symbolic/nrflib/cells/rf_out_mem.ap new file mode 100644 index 000000000..f96a645e8 --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_out_mem.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 6 +H rf_out_mem,P,22/4/2016,100 +A 0,0,11000,10000 +S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,11000,600,1200,vss,RIGHT,CALU1 +S 3879,10000,6920,10000,600,0nonymous_,RIGHT,NTIE +S 6600,5000,8000,5000,300,1nonymous_,RIGHT,ALU1 +S 3000,3000,4200,3000,300,2nonymous_,RIGHT,ALU1 +S 3000,7000,4200,7000,300,3nonymous_,RIGHT,ALU1 +S 4200,7000,4200,8000,300,4nonymous_,UP,ALU1 +S 7800,5700,7800,9300,600,38onymous_,UP,PDIF +S 2400,7500,2400,9500,200,37onymous_,UP,PTRANS +S 9600,5500,9600,9500,200,36onymous_,UP,PTRANS +S 3000,1000,3000,2000,300,15onymous_,UP,ALU1 +S 2000,5200,3600,5200,200,14onymous_,RIGHT,POLY +S 1000,4000,1000,6000,300,13onymous_,UP,ALU1 +S 1000,4200,2400,4200,200,12onymous_,RIGHT,POLY +S 2400,1900,2400,3900,200,11onymous_,UP,NTRANS +S 1800,2100,1800,3700,600,10onymous_,UP,NDIF +S 1000,6200,2400,6200,200,9nonymous_,RIGHT,POLY +S 2400,6200,2400,7200,200,8nonymous_,UP,POLY +S 1600,7000,2000,7000,300,7nonymous_,RIGHT,ALU1 +S 2000,3000,2000,8000,300,6nonymous_,UP,ALU1 +S 3000,3000,3000,7000,300,5nonymous_,UP,ALU1 +S 3000,8000,3000,9000,300,16onymous_,UP,ALU1 +S 3000,700,3000,3700,600,17onymous_,UP,NDIF +S 3600,2700,3600,3900,200,18onymous_,UP,NTRANS +S 4200,3100,4200,3700,600,19onymous_,UP,NDIF +S 5400,2500,5400,3700,600,20onymous_,UP,NDIF +S 4800,2700,4800,3900,200,21onymous_,UP,NTRANS +S 9000,1700,9000,3300,600,32onymous_,UP,NDIF +S 8400,1500,8400,3500,200,33onymous_,UP,NTRANS +S 10200,900,10200,3300,600,34onymous_,UP,NDIF +S 9600,1500,9600,3500,200,35onymous_,UP,NTRANS +S -600,8600,11600,8600,4400,31onymous_,RIGHT,NWELL +S 1200,6800,1200,8400,200,30onymous_,UP,POLY +S 1200,7000,1800,7000,600,29onymous_,RIGHT,POLY +S 7800,5000,9600,5000,600,28onymous_,RIGHT,POLY +S 1600,7800,11600,7800,6000,27onymous_,RIGHT,NWELL +S 7200,6100,7200,7500,200,26onymous_,UP,PTRANS +S 6600,6300,6600,7300,600,25onymous_,UP,PDIF +S 600,6000,1000,6000,300,24onymous_,RIGHT,ALU1 +S 600,6000,600,7400,300,23onymous_,UP,ALU1 +S 5300,1600,5700,1600,800,22onymous_,RIGHT,NTRANS +S 1800,7700,1800,9300,600,39onymous_,UP,PDIF +S 8400,5500,8400,9500,200,40onymous_,UP,PTRANS +S 9000,5700,9000,9300,600,41onymous_,UP,PDIF +S 500,8200,900,8200,600,42onymous_,RIGHT,PTRANS +S 10200,5700,10200,9300,600,43onymous_,UP,PDIF +S 9600,3800,9600,5200,200,44onymous_,UP,POLY +S 8400,3800,8400,5200,200,45onymous_,UP,POLY +S 10200,1000,10200,3000,300,46onymous_,UP,ALU1 +S 10200,6000,10200,9000,300,47onymous_,UP,ALU1 +S 7800,1000,7800,3000,300,48onymous_,UP,ALU1 +S 7800,6000,7800,9000,300,49onymous_,UP,ALU1 +S 3600,4200,3600,5800,200,50onymous_,UP,POLY +S 3600,6100,3600,8500,200,51onymous_,UP,PTRANS +S 4200,6300,4200,8300,600,52onymous_,UP,PDIF +S 3000,6300,3000,9300,600,53onymous_,UP,PDIF +S 6280,700,9320,700,600,54onymous_,RIGHT,PTIE +S 5300,7200,5700,7200,600,55onymous_,RIGHT,PTRANS +S 6600,2000,6600,7000,300,56onymous_,UP,ALU1 +S 5400,3000,5400,6400,300,57onymous_,UP,ALU1 +S 7200,1500,7200,2900,200,58onymous_,UP,NTRANS +S 6600,1700,6600,2700,600,59onymous_,UP,NDIF +S 7200,3200,7200,5800,200,60onymous_,UP,POLY +S 7800,1700,7800,3300,600,61onymous_,UP,NDIF +S 5400,8000,5400,9400,300,62onymous_,UP,ALU1 +S 6000,5400,6000,7400,200,63onymous_,UP,POLY +S 6000,1400,6000,3600,200,64onymous_,UP,POLY +S 5600,4400,7200,4400,600,65onymous_,RIGHT,POLY +S 6000,3400,6600,3400,600,66onymous_,RIGHT,POLY +S 6000,5600,6600,5600,600,67onymous_,RIGHT,POLY +S 2850,5000,4550,5000,600,68onymous_,RIGHT,ALU2 +S 280,700,2120,700,600,72onymous_,RIGHT,PTIE +S 4400,4400,4400,5400,300,71onymous_,UP,ALU1 +S 4200,4400,4800,4400,600,70onymous_,RIGHT,POLY +S 3050,5000,4350,5000,300,69onymous_,RIGHT,TALU2 +S 3000,4850,3000,5150,400,xcks,UP,CALU3 +S -150,5000,1150,5000,600,rbus,RIGHT,CALU2 +S 9000,2000,9000,8000,300,dataout,UP,CALU1 +V 6600,10000,CONT_BODY_N,75onymous_ +V 4200,10000,CONT_BODY_N,74onymous_ +V 5400,10000,CONT_BODY_N,73onymous_ +V 2000,5200,CONT_POLY,76onymous_ +V 1800,3000,CONT_DIF_N,77onymous_ +V 1000,4000,CONT_POLY,78onymous_ +V 3000,1000,CONT_DIF_N,79onymous_ +V 3000,2000,CONT_DIF_N,80onymous_ +V 3000,5000,CONT_VIA2,81onymous_ +V 4200,3000,CONT_DIF_N,82onymous_ +V 5400,3000,CONT_DIF_N,83onymous_ +V 5400,600,CONT_DIF_N,84onymous_ +V 1000,6000,CONT_POLY,85onymous_ +V 1000,5000,CONT_VIA,86onymous_ +V 8000,5000,CONT_POLY,87onymous_ +V 1600,7000,CONT_POLY,88onymous_ +V 10200,2000,CONT_DIF_N,89onymous_ +V 9000,3000,CONT_DIF_N,90onymous_ +V 9000,2000,CONT_DIF_N,91onymous_ +V 7800,2000,CONT_DIF_N,92onymous_ +V 10200,1000,CONT_DIF_N,93onymous_ +V 10200,3000,CONT_DIF_N,94onymous_ +V 7800,3000,CONT_DIF_N,95onymous_ +V 3000,8000,CONT_DIF_P,96onymous_ +V 9000,7000,CONT_DIF_P,97onymous_ +V 9000,6000,CONT_DIF_P,98onymous_ +V 6600,7000,CONT_DIF_P,99onymous_ +V 4200,7000,CONT_DIF_P,100nymous_ +V 1800,8000,CONT_DIF_P,101nymous_ +V 600,9000,CONT_DIF_P,102nymous_ +V 9000,8000,CONT_DIF_P,103nymous_ +V 10200,7000,CONT_DIF_P,113nymous_ +V 4200,8000,CONT_DIF_P,112nymous_ +V 10200,8000,CONT_DIF_P,111nymous_ +V 7800,7000,CONT_DIF_P,110nymous_ +V 7800,8000,CONT_DIF_P,109nymous_ +V 600,7400,CONT_DIF_P,108nymous_ +V 10200,6000,CONT_DIF_P,107nymous_ +V 3000,9000,CONT_DIF_P,106nymous_ +V 7800,9000,CONT_DIF_P,105nymous_ +V 10200,9000,CONT_DIF_P,104nymous_ +V 7800,6000,CONT_DIF_P,114nymous_ +V 9000,600,CONT_BODY_P,115nymous_ +V 6600,600,CONT_BODY_P,116nymous_ +V 7800,600,CONT_BODY_P,117nymous_ +V 6400,5600,CONT_POLY,118nymous_ +V 5400,8000,CONT_DIF_P,119nymous_ +V 4400,5000,CONT_VIA,120nymous_ +V 5400,6400,CONT_DIF_P,121nymous_ +V 6600,2000,CONT_DIF_N,122nymous_ +V 6400,3400,CONT_POLY,123nymous_ +V 5600,4400,CONT_POLY,124nymous_ +V 4400,4400,CONT_POLY,125nymous_ +V 600,600,CONT_BODY_P,126nymous_ +V 1800,600,CONT_BODY_P,127nymous_ +EOF diff --git a/pdks/symbolic/nrflib/cells/rf_out_mem.vbe b/pdks/symbolic/nrflib/cells/rf_out_mem.vbe new file mode 100644 index 000000000..86cd1067f --- /dev/null +++ b/pdks/symbolic/nrflib/cells/rf_out_mem.vbe @@ -0,0 +1,26 @@ +ENTITY rf_out_mem IS +PORT ( + rbus : in BIT; + xcks : in BIT; + dataout : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf_out_mem; + +ARCHITECTURE VBE OF rf_out_mem IS + SIGNAL latch : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf_out_mem" + SEVERITY WARNING; + + label0 : BLOCK (xcks = '1') + BEGIN + latch <= GUARDED rbus; + END BLOCK label0; + + dataout <= latch; + +END; diff --git a/pdks/symbolic/nrflib/check/__init__.py b/pdks/symbolic/nrflib/check/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/pdks/symbolic/nrflib/check/generate.py b/pdks/symbolic/nrflib/check/generate.py new file mode 100755 index 000000000..b1feefb70 --- /dev/null +++ b/pdks/symbolic/nrflib/check/generate.py @@ -0,0 +1,108 @@ +#!/usr/bin/env python +# -*- coding: utf-8 -*- + +try: + import sys + import traceback + import os.path + import optparse + import Cfg + import CRL + import stratus +except ImportError, e: + serror = str(e) + if serror.startswith('No module named'): + module = serror.split()[-1] + print '[ERROR] The <%s> python module or symbol cannot be loaded.' % module + print ' Please check the integrity of the package.' + if str(e).find('cannot open shared object file'): + library = serror.split(':')[0] + print '[ERROR] The <%s> shared library cannot be loaded.' % library + print ' Under RHEL 6, you must be under devtoolset-2.' + print ' (scl enable devtoolset-2 bash)' + sys.exit(1) +except Exception, e: + print '[ERROR] A strange exception occurred while loading the basic Coriolis/Python' + print ' modules. Something may be wrong at Python/C API level.\n' + print ' %s' % e + sys.exit(2) + + +framework = CRL.AllianceFramework.get() + + +if __name__ == '__main__': + parser = optparse.OptionParser() + parser.add_option( '-b', '--bits' , type='int' , dest='bits' , help='Number of bits of each word (2 <= bits <= 64).') + parser.add_option( '-w', '--words', type='int' , dest='words' , help='Number of words in the RAM (32 <= words <= 256).') + parser.add_option( '-m', '--model', type='string', dest='model' , help='The name of the model to generate.') + parser.add_option( '-v', '--verbose' , action='store_true', dest='verbose' , help='First level of verbosity.') + parser.add_option( '-V', '--very-verbose' , action='store_true', dest='veryVerbose', help='Second level of verbosity.') + (options, args) = parser.parse_args() + + modelName = None + if options.verbose: Cfg.getParamBool('misc.verboseLevel1').setBool(True) + if options.veryVerbose: Cfg.getParamBool('misc.verboseLevel2').setBool(True) + if options.model: modelName = options.model + + print framework.getEnvironment().getPrint() + + if not modelName: + print '[ERROR] Missing mandatory argument .' + sys.exit( 1 ) + + if modelName.startswith( 'rf1dr0' ): + cell = stratus.buildModel( 'dpgen_RF1' + , stratus.DoNetlist|stratus.DoLayout + , className ='DpgenRf1dr0' + , modelName = modelName + , parameters={ 'nbit' : options.bits + , 'nword' : options.words + , 'logical' : True + , 'physical' : True + } ) + if modelName.startswith( 'rf1r0' ): + cell = stratus.buildModel( 'dpgen_RF1' + , stratus.DoNetlist|stratus.DoLayout + , className ='DpgenRf1r0' + , modelName = modelName + , parameters={ 'nbit' : options.bits + , 'nword' : options.words + , 'logical' : True + , 'physical' : True + } ) + elif modelName.startswith( 'rf1d' ): + cell = stratus.buildModel( 'dpgen_RF1' + , stratus.DoNetlist|stratus.DoLayout + , className ='DpgenRf1d' + , modelName = modelName + , parameters={ 'nbit' : options.bits + , 'nword' : options.words + , 'logical' : True + , 'physical' : True + } ) + elif modelName.startswith( 'rf1' ): + cell = stratus.buildModel( 'dpgen_RF1' + , stratus.DoNetlist|stratus.DoLayout + , className ='DpgenRf1' + , modelName = modelName + , parameters={ 'nbit' : options.bits + , 'nword' : options.words + , 'logical' : True + , 'physical' : True + } ) + elif modelName.startswith( 'fifo' ): + cell = stratus.buildModel( 'dpgen_RF1' + , stratus.DoNetlist|stratus.DoLayout + , className ='DpgenFifo' + , modelName = modelName + , parameters={ 'nbit' : options.bits + , 'nword' : options.words + , 'logical' : True + , 'physical' : True + } ) + else: + print '[ERROR] Unsupported value: "%s".' % modelName + sys.exit( 1 ) + + sys.exit( 0 ) diff --git a/pdks/symbolic/nrflib/check/scaleCell.py b/pdks/symbolic/nrflib/check/scaleCell.py new file mode 100755 index 000000000..a59957eaa --- /dev/null +++ b/pdks/symbolic/nrflib/check/scaleCell.py @@ -0,0 +1,366 @@ +#!/usr/bin/env python +# -*- coding: utf-8; explicit-buffer-name: "scaleCell.py" -*- + +try: + import sys + import traceback + import os.path + import shutil + import optparse + import math + import Cfg + import Hurricane + from Hurricane import DataBase + from Hurricane import DbU + from Hurricane import Transformation + from Hurricane import Box + from Hurricane import UpdateSession + from Hurricane import Breakpoint + from Hurricane import Net + from Hurricane import NetExternalComponents + from Hurricane import BasicLayer + from Hurricane import ContactLayer + from Hurricane import ViaLayer + from Hurricane import RegularLayer + from Hurricane import TransistorLayer + from Hurricane import DiffusionLayer + from Hurricane import Cell + from Hurricane import Instance + from Hurricane import Net + from Hurricane import Contact + from Hurricane import Horizontal + from Hurricane import Vertical + import Viewer + import CRL + from CRL import RoutingLayerGauge + import helpers + from helpers import trace + from helpers import ErrorMessage +except ImportError, e: + serror = str(e) + if serror.startswith('No module named'): + module = serror.split()[-1] + print '[ERROR] The <%s> python module or symbol cannot be loaded.' % module + print ' Please check the integrity of the package.' + if str(e).find('cannot open shared object file'): + library = serror.split(':')[0] + print '[ERROR] The <%s> shared library cannot be loaded.' % library + print ' Under RHEL 6, you must be under devtoolset-2.' + print ' (scl enable devtoolset-2 bash)' + sys.exit(1) +except Exception, e: + print '[ERROR] A strange exception occurred while loading the basic Coriolis/Python' + print ' modules. Something may be wrong at Python/C API level.\n' + print ' %s' % e + sys.exit(2) + + +framework = CRL.AllianceFramework.get() +scale = 2 + + +def getDeltas ( layer ): + # | Layer | Min W | Delta W | Delta L | + # +---------------+-------+---------+---------+ + deltas = { 'NWELL' : ( 999.0 , 12.0 , 6.0 ) + , 'PWELL' : ( 999.0 , 12.0 , 6.0 ) + , 'NDIF' : ( 999.0 , 0.0 , -1.0 ) + , 'PDIF' : ( 999.0 , 0.0 , -1.0 ) + , 'NTIE' : ( 999.0 , 0.0 , 1.2 ) + , 'PTIE' : ( 999.0 , 0.0 , 1.2 ) + , 'NTRANS' : ( 999.0 , 0.0 , -3.0 ) + , 'PTRANS' : ( 999.0 , 0.0 , -3.0 ) + , 'POLY' : ( 999.0 , 0.0 , 0.0 ) + #, 'METAL1' : ( 1.5 , 1.0 , -1.0 ) + , 'METAL1' : ( 1.5 , 1.0 , 0.0 ) + , 'METAL2' : ( 999.0 , 2.0 , 1.5 ) + #, 'METAL3' : ( 2.0 , 2.0 , 1.5 ) + , 'METAL3' : ( 999.0 , 0.0 , 1.5 ) + , 'BLOCKAGE1' : ( 999.0 , 0.0 , 0.0 ) + , 'BLOCKAGE2' : ( 999.0 , -1.0 , -0.5 ) + , 'BLOCKAGE3' : ( 999.0 , -1.0 , -0.5 ) + , 'BLOCKAGE4' : ( 999.0 , -1.0 , -0.5 ) + } + + dbuLayerDeltas = ( 0, 0, 0 ) + if deltas.has_key(layer.getName()): + deltas = deltas[ layer.getName() ] + dbuLayerDeltas = DbU.fromLambda(deltas[0]), DbU.fromLambda(deltas[1]), DbU.fromLambda(deltas[2]) + else: + print '[WARNING] Layer \"%s\" has no deltas corrections.' % layer.getName() + + return dbuLayerDeltas + + +def scaleCell ( editor, sourceCell ): + global framework + global scale + + if sourceCell == None: + raise ErrorMessage( 3, 'scaleCell.scaleCell(): Mandatory sourceCell argument is None.' ) + scaledCell = None + + print '\n o Processing', sourceCell + + UpdateSession.open() + try: + library = framework.getLibrary( 0 ) + scaledCell = Cell.create( library, sourceCell.getName() ) + + ab = sourceCell.getAbutmentBox() + scaledCell.setAbutmentBox( Box( ab.getXMin()*scale, ab.getYMin()*scale + , ab.getXMax()*scale, ab.getYMax()*scale ) ) + + for net in sourceCell.getNets(): + scaledNet = Net.create( scaledCell, net.getName() ) + if net.isExternal(): scaledNet.setExternal( True ) + if net.isGlobal (): scaledNet.setGlobal ( True ) + scaledNet.setType ( net.getType () ) + scaledNet.setDirection( net.getDirection() ) + + for component in net.getComponents(): + layer = component.getLayer() + dupComponent = None + + if isinstance(component,Contact): + custom_dY = 0 + + if component.getLayer().getName() == 'CONT_BODY_N': + if component.getY() == DbU.fromLambda(47.0): + print '[INFO] Shifted down CONT_BODY_N contact.' + print ' %s' % component + custom_dY = DbU.fromLambda(-1.0) + + if component.getLayer().getName() == 'CONT_BODY_N': + if component.getY() == DbU.fromLambda(3.0): + print '[INFO] Shifted up CONT_BODY_N contact.' + print ' %s' % component + custom_dY = DbU.fromLambda(1.0) + + # Default VIAs get their size through the parser. So they + # are already scaled (to the minimal size). + dupComponent = Contact.create( scaledNet + , layer + , component.getX ()*scale + , component.getY ()*scale + custom_dY + , component.getWidth () # *scale + , component.getHeight() # *scale + ) + print ' |', dupComponent + elif isinstance(component,Horizontal): + custom_dY = 0 + custom_dW = 0 + + if sourceCell.getName() == 'rf_fifo_ptset' or sourceCell.getName() == 'rf_fifo_ptreset': + if component.getLayer().getName() == 'BLOCKAGE2': + if component.getSourceX() == DbU.fromLambda(10.0) \ + and component.getTargetX() == DbU.fromLambda(45.0) \ + and component.getY() == DbU.fromLambda(20.0) \ + and component.getWidth() == DbU.fromLambda( 2.0): + print '[INFO] Removed METAL2 blockage from "%s".' % sourceCell + print ' %s' % component + scaledNet.destroy() + continue + + if sourceCell.getName() == 'rf_inmux_buf_2': + if component.getLayer().getName() == 'METAL1': + if component.getSourceX() == DbU.fromLambda(27.0) \ + and component.getTargetX() == DbU.fromLambda(39.0) \ + and component.getY() == DbU.fromLambda(90.0) \ + and component.getWidth() == DbU.fromLambda( 2.0): + print '[INFO] Enlarge METAL1 to avoid notch.' + print ' %s' % component + custom_dW = DbU.fromLambda(1.0) + + if sourceCell.getName() == 'rf_fifo_clock': + if component.getLayer().getName() == 'METAL1': + if component.getSourceX() == DbU.fromLambda(32.0) \ + and component.getTargetX() == DbU.fromLambda(35.0) \ + and component.getY() == DbU.fromLambda(60.0) \ + and component.getWidth() == DbU.fromLambda( 2.0): + print '[INFO] Enlarge METAL1 to avoid notch.' + print ' %s' % component + custom_dW = DbU.fromLambda(1.0) + + if component.getLayer().getName() == 'NTIE': + if component.getY() == DbU.fromLambda(47.0): + print '[INFO] Shifted down NTIE segment.' + print ' %s' % component + custom_dY = DbU.fromLambda(-1.0) + + if component.getLayer().getName() == 'PTIE': + if component.getY() == DbU.fromLambda(3.0): + print '[INFO] Shifted up PTIE segment.' + print ' %s' % component + custom_dY = DbU.fromLambda(1.0) + + mW, dW, dL = getDeltas( layer ) + + if component.getLayer().getName() == 'METAL1': + if component.getWidth() == DbU.fromLambda(2.0): + print '[INFO] Shrinking METAL1 of 2l width to default contact width.' + print ' %s' % component + mW = DbU.fromLambda( 2.0) + dW = DbU.fromLambda(-1.0) + + if component.getLayer().getName() == 'METAL3' \ + and component.getSourceX() == component.getTargetX(): + print '[WARNING] Rotating badly oriented METAL3 terminal (H -> V).' + print ' %s' % component + + width = component.getWidth()*scale + #if component.getWidth() <= mW: width += dW + + dupComponent = Vertical.create( scaledNet + , layer + , component.getSourceX()*scale + , width + , component.getY()*scale - dL + , component.getY()*scale + dL + ) + print ' |', dupComponent + + else: + if component.getSourceX() > component.getTargetX(): component.invert() + bb = component.getBoundingBox() + + width = component.getWidth()*scale + if component.getWidth() <= mW: width += dW + + if width > 0 and ( (dL > 0) or (bb.getWidth()*scale > abs(2*dL)) ): + dupComponent = Horizontal.create( scaledNet + , layer + , component.getY ()*scale + custom_dY + , width + custom_dW + , component.getDxSource()*scale - dL + , component.getDxTarget()*scale + dL + ) + print ' |', dupComponent + else: + print '[WARNING] Horizontal component too small *or* skipped, not converted.' + + elif isinstance(component,Vertical): + mW, dW, dL = getDeltas( component.getLayer() ) + + if component.getLayer().getName() == 'METAL1' \ + and component.getWidth() == DbU.fromLambda(2.0): + print '[INFO] Shrinking METAL1 of 2l width to default contact width.' + print ' %s' % component + mW = DbU.fromLambda( 2.0) + dW = DbU.fromLambda(-1.0) + + if component.getSourceY() > component.getTargetY(): component.invert() + bb = component.getBoundingBox() + + width = component.getWidth()*scale + if component.getWidth() <= mW: width += dW + + if width > 0 and ( (dL > 0) or (bb.getHeight()*scale > abs(2*dL)) ): + dupComponent = Vertical.create( scaledNet + , layer + , component.getX ()*scale + , width + , component.getDySource()*scale - dL + , component.getDyTarget()*scale + dL + ) + print ' |', dupComponent + else: + print '[WARNING] Vertical component too small *or* skipped, not converted.' + + else: + print '[WARNING] Unchanged component:', component + + if dupComponent and NetExternalComponents.isExternal( component ): + NetExternalComponents.setExternal( dupComponent ) + + except ErrorMessage, e: + print e; errorCode = e.code + except Exception, e: + print '\n\n', e; errorCode = 1 + traceback.print_tb(sys.exc_info()[2]) + + UpdateSession.close() + if scaledCell: + framework.saveCell( scaledCell, CRL.Catalog.State.Physical ) + if editor: + editor.setCell( scaledCell ) + editor.fit() + + return scaledCell + + +def scriptMain ( **kw ): + global framework + + helpers.staticInitialization( quiet=True ) + #helpers.setTraceLevel( 550 ) + + scaledDir = framework.getAllianceLibrary(0).getPath() + alibrary = framework.getAllianceLibrary(1) + if not alibrary: + print '[ERROR] No Library at index 1, please check SYSTEM_LIBRARY in settings.py.' + return 1 + + hasCatal = False + apCount = 0 + vbeCount = 0 + for file in os.listdir( scaledDir ): + if file == 'CATAL': hasCatal = True + if file[-4:] == '.vbe': vbeCount += 1 + if file[-3:] == '.ap': apCount += 1 + + if hasCatal or vbeCount or apCount: + print '[ERROR] Target directory already contains CATAL/.vbe/.ap files.' + print ' You must remove them before proceeding with this script.' + print ' (%s)' % scaledDir + return 1 + + sourceCell = None + if kw.has_key('cell') and kw['cell']: + sourceCell = kw['cell'] + + editor = None + if kw.has_key('editor') and kw['editor']: + editor = kw['editor'] + print ' o Editor detected, running in graphic mode.' + if sourceCell == None: sourceCell = editor.getCell() + + if sourceCell: + scaledCell = scaleCell( editor, sourceCell ) + else: + print ' o Processing library "%s".' % alibrary.getLibrary().getName() + print ' (path:%s)' % alibrary.getPath() + framework.loadLibraryCells( alibrary.getLibrary() ) + for sourceCell in alibrary.getLibrary().getCells(): + scaledCell = scaleCell( editor, sourceCell ) + + print '' + print ' o Direct copy of ".vbe" & CATAL files.' + for file in os.listdir( alibrary.getPath() ): + if file == 'CATAL' or file[-4:] == '.vbe': + print ' | %s' % file + shutil.copy( alibrary.getPath()+'/'+file, scaledDir ) + + return 0 + + +if __name__ == '__main__': + parser = optparse.OptionParser() + parser.add_option( '-c', '--cell', type='string', dest='cell' , help='The name of the chip to build, whithout extension.') + parser.add_option( '-v', '--verbose' , action='store_true', dest='verbose' , help='First level of verbosity.') + parser.add_option( '-V', '--very-verbose' , action='store_true', dest='veryVerbose', help='Second level of verbosity.') + (options, args) = parser.parse_args() + + kw = {} + if options.cell: + kw['cell'] = framework.getCell( options.cell, CRL.Catalog.State.Views ) + if options.verbose: Cfg.getParamBool('misc.verboseLevel1').setBool(True) + if options.veryVerbose: Cfg.getParamBool('misc.verboseLevel2').setBool(True) + + print framework.getEnvironment().getPrint() + + success = scriptMain( **kw ) + shellSuccess = 0 + if not success: shellSuccess = 1 + + sys.exit( shellSuccess ) diff --git a/pdks/symbolic/nsxlib/cells/CATAL b/pdks/symbolic/nsxlib/cells/CATAL new file mode 100644 index 000000000..5657ebeb3 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/CATAL @@ -0,0 +1,93 @@ +a2_x2 C +a2_x4 C +a3_x2 C +a3_x4 C +a4_x2 C +a4_x4 C +an12_x1 C +an12_x4 C +ao22_x2 C +ao22_x4 C +ao2o22_x2 C +ao2o22_x4 C +buf_x2 C +buf_x4 C +buf_x8 C +inv_x1 C +inv_x2 C +inv_x4 C +inv_x8 C +mx2_x2 C +mx2_x4 C +mx3_x2 C +mx3_x4 C +na2_x1 C +na2_x4 C +na3_x1 C +na3_x4 C +na4_x1 C +na4_x4 C +nao22_x1 C +nao22_x4 C +nao2o22_x1 C +nao2o22_x4 C +nmx2_x1 C +nmx2_x4 C +nmx3_x1 C +no2_x1 C +no2_x4 C +no3_x1 C +no3_x4 C +no4_x1 C +no4_x4 C +noa22_x1 C +noa22_x4 C +noa2a22_x1 C +noa2a22_x4 C +noa2a2a23_x1 C +noa2a2a23_x4 C +noa2a2a2a24_x1 C +noa2a2a2a24_x4 C +noa2ao222_x1 C +noa2ao222_x4 C +noa3ao322_x1 C +noa3ao322_x4 C +nts_x1 C +nts_x2 C +nxr2_x1 C +nxr2_x4 C +o2_x2 C +o2_x4 C +o3_x2 C +o3_x4 C +o4_x2 C +o4_x4 C +oa22_x2 C +oa22_x4 C +oa2a22_x2 C +oa2a22_x4 C +oa2a2a23_x2 C +oa2a2a23_x4 C +oa2a2a2a24_x2 C +oa2a2a2a24_x4 C +oa2ao222_x2 C +oa2ao222_x4 C +oa3ao322_x2 C +oa3ao322_x4 C +on12_x1 C +on12_x4 C +one_x0 C +powmid_x0 C +powmid_x0 F +rowend_x0 C +rowend_x0 F +sff1_x4 C +sff1r_x4 C +sff2_x4 C +tie_x0 C +tie_x0 F +ts_x4 C +ts_x8 C +xr2_x1 C +xr2_x4 C +zero_x0 C diff --git a/pdks/symbolic/nsxlib/cells/a2_x2.ap b/pdks/symbolic/nsxlib/cells/a2_x2.ap new file mode 100644 index 000000000..37c7697f6 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a2_x2.ap @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H a2_x2,P,26/ 9/2019,100 +A 0,0,5000,10000 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 3000,2000,ref_ref,i1_10 +R 1000,3000,ref_ref,i0_15 +R 3000,8000,ref_ref,i1_40 +R 3000,7000,ref_ref,i1_35 +R 3000,4000,ref_ref,i1_20 +R 3000,6000,ref_ref,i1_30 +R 4000,4000,ref_ref,q_20 +R 4000,3000,ref_ref,q_15 +R 4000,5000,ref_ref,q_25 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +S 4100,800,4100,2300,600,*,UP,NDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S 3000,800,3000,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 800,2000,1800,2000,300,*,RIGHT,ALU1 +S 1900,2100,1900,8000,300,*,UP,ALU1 +S 800,8100,800,8900,300,*,UP,ALU1 +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 2400,2700,2400,3000,200,*,UP,POLY +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 1800,6700,1800,8300,600,*,UP,PDIF +S 2400,5000,2400,6200,200,*,UP,POLY +S 2400,3000,3000,3000,200,*,RIGHT,POLY +S 2400,5000,3000,5000,200,*,RIGHT,POLY +S 1200,5900,1200,6300,200,*,UP,POLY +S 1200,2700,1200,4100,200,*,UP,POLY +S 2000,4000,3600,4000,200,*,RIGHT,POLY +S 3600,2800,3600,5200,200,*,UP,POLY +S 2400,6500,2400,8500,200,*,UP,PTRANS +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 1200,600,1200,2500,200,*,UP,NTRANS +S 1800,800,1800,2300,600,*,UP,NDIF +S 800,800,800,2300,600,*,UP,NDIF +S 3000,5700,3000,9300,500,*,UP,PDIF +S 700,6700,700,8300,600,*,UP,PDIF +S -300,7800,5300,7800,6000,*,RIGHT,NWELL +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 4000,2000,4000,8000,300,q,UP,ALU1 +S 3000,2100,3000,7900,300,i1,UP,CALU1 +S 1000,3100,1000,6900,300,i0,UP,CALU1 +S 4000,2100,4000,8000,300,q,UP,CALU1 +V 3000,5000,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 3200,9100,CONT_DIF_P,* +V 1700,8000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 1000,6000,CONT_POLY,* +V 800,8000,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 4000,8000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,6000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 3000,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/a2_x2.vbe b/pdks/symbolic/nsxlib/cells/a2_x2.vbe new file mode 100644 index 000000000..8e6db7cd8 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i1_q : NATURAL := 203; + CONSTANT tphh_i0_q : NATURAL := 261; + CONSTANT tpll_i0_q : NATURAL := 388; + CONSTANT tpll_i1_q : NATURAL := 434; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x2; + +ARCHITECTURE behaviour_data_flow OF a2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x2" + SEVERITY WARNING; + q <= (i0 and i1) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/a2_x4.ap b/pdks/symbolic/nsxlib/cells/a2_x4.ap new file mode 100644 index 000000000..4c9c3fc64 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a2_x4.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H a2_x4,P,18/ 9/2019,100 +A 0,0,6000,10000 +R 3000,8000,ref_ref,i1_40 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 1000,7000,ref_ref,i0_35 +R 4000,5000,ref_ref,q_25 +R 3000,2000,ref_ref,i1_10 +R 3000,4000,ref_ref,i1_20 +R 3000,6000,ref_ref,i1_30 +R 3000,7000,ref_ref,i1_35 +R 4000,4000,ref_ref,q_20 +R 4000,3000,ref_ref,q_15 +S 1000,3100,1000,7000,300,i0,UP,CALU1 +S 3000,2100,3000,7900,300,i1,UP,CALU1 +S 1000,3000,1000,7000,300,i0,UP,ALU1 +S 4000,3000,4000,5000,300,q,UP,CALU1 +S 4000,2000,4000,8000,300,q,UP,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 2400,2700,2400,3000,200,*,UP,POLY +S 2400,3000,3000,3000,200,*,RIGHT,POLY +S 2200,5000,2200,6200,200,*,UP,POLY +S 2200,5000,2800,5000,200,*,RIGHT,POLY +S 600,6700,600,8300,400,*,UP,PDIF +S 2900,5700,2900,9300,600,*,UP,PDIF +S 5400,800,5400,2300,600,*,UP,NDIF +S 4800,600,4800,2500,200,*,UP,NTRANS +S 4200,800,4200,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 3000,800,3000,2300,600,*,UP,NDIF +S 1800,800,1800,2300,600,*,UP,NDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S 800,8100,800,8900,300,*,UP,ALU1 +S 5400,1100,5400,1900,300,*,UP,ALU1 +S 1800,6700,1800,8300,600,*,UP,PDIF +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 5400,5700,5400,9300,600,*,UP,PDIF +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 800,2000,1800,2000,300,*,RIGHT,ALU1 +S 2200,6500,2200,8500,200,*,UP,PTRANS +S 1200,5900,1200,6200,200,*,UP,POLY +S 5400,6100,5400,8900,300,*,UP,ALU1 +S 4800,2800,4800,5200,200,*,UP,POLY +S 3600,2800,3600,5200,200,*,UP,POLY +S 2000,4000,4800,4000,200,*,RIGHT,POLY +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 1200,2800,1200,3100,200,*,UP,POLY +S -300,7800,6300,7800,6000,*,RIGHT,NWELL +S 1900,2100,1900,7900,300,*,UP,ALU1 +S 1200,600,1200,2500,200,*,UP,NTRANS +S 800,800,800,2300,600,*,UP,NDIF +V 4000,2000,CONT_DIF_N,* +V 3000,3000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 1800,8000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 5400,6000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,6000,CONT_DIF_P,* +V 3000,900,CONT_DIF_N,* +V 3100,9100,CONT_DIF_P,* +V 5400,9100,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,* +V 1000,3000,CONT_POLY,* +V 5400,2000,CONT_DIF_N,* +V 5400,1000,CONT_DIF_N,* +V 1000,6000,CONT_POLY,* +V 800,8000,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/a2_x4.vbe b/pdks/symbolic/nsxlib/cells/a2_x4.vbe new file mode 100644 index 000000000..f6955d6e9 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphh_i0_q : NATURAL := 338; + CONSTANT tpll_i0_q : NATURAL := 476; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x4; + +ARCHITECTURE behaviour_data_flow OF a2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x4" + SEVERITY WARNING; + q <= (i0 and i1) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/a3_x2.ap b/pdks/symbolic/nsxlib/cells/a3_x2.ap new file mode 100644 index 000000000..4563d1820 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a3_x2.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 6 +H a3_x2,P,18/ 9/2019,100 +A 0,0,6000,10000 +R 5000,8000,ref_ref,q_40 +R 5000,3000,ref_ref,q_15 +R 5000,2000,ref_ref,q_10 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 2000,3000,ref_ref,i1_15 +R 1000,3000,ref_ref,i0_15 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 3000,6000,ref_ref,i2_30 +R 5000,4000,ref_ref,q_20 +R 5000,5000,ref_ref,q_25 +R 5000,6000,ref_ref,q_30 +R 5000,7000,ref_ref,q_35 +R 3000,5000,ref_ref,i2_25 +R 3000,4000,ref_ref,i2_20 +R 3000,3000,ref_ref,i2_15 +S 5000,2100,5000,8000,300,*,UP,ALU1 +S 3000,3100,3000,6000,300,*,UP,ALU1 +S 2000,3100,2000,6000,300,*,UP,ALU1 +S 1000,3100,1000,6000,300,*,UP,ALU1 +S 5000,2100,5000,8000,300,q,UP,CALU1 +S 3000,3100,3000,6000,300,i2,UP,CALU1 +S 2000,3100,2000,6000,300,i1,UP,CALU1 +S 1000,3100,1000,6000,300,i0,UP,CALU1 +S 2400,6100,2400,6400,200,*,UP,POLY +S 4000,800,4000,2300,800,*,UP,NDIF +S 4600,600,4600,2500,200,*,UP,NTRANS +S 4600,2800,4600,5200,200,*,UP,POLY +S 1800,8200,1800,8800,400,*,UP,ALU1 +S 4100,8200,4100,8800,400,*,UP,ALU1 +S 4000,2100,4000,7300,300,*,UP,ALU1 +S 4600,5500,4600,9500,200,*,UP,PTRANS +S 1800,6700,1800,8300,400,*,UP,PDIF +S 800,2000,3900,2000,300,*,RIGHT,ALU1 +S 600,6700,600,8300,400,*,UP,PDIF +S 4100,5700,4100,9300,400,*,UP,PDIF +S 5200,5700,5200,9300,400,*,UP,PDIF +S 5200,800,5200,2300,400,*,UP,NDIF +S 3500,800,3500,3300,400,*,UP,NDIF +S 3400,6500,3400,8500,200,*,UP,PTRANS +S 3400,5200,3400,6200,200,*,UP,POLY +S 2800,5200,3400,5200,200,*,RIGHT,POLY +S 2000,6100,2400,6100,200,*,RIGHT,POLY +S 2000,3800,2000,6100,200,*,UP,POLY +S 700,1700,700,3300,400,*,UP,NDIF +S -300,7800,6300,7800,6000,*,RIGHT,NWELL +S 3000,6700,3000,8300,600,*,UP,PDIF +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 2400,6500,2400,8500,200,*,UP,PTRANS +S 1200,3800,1200,6200,200,*,UP,POLY +S 2800,1500,2800,3500,200,*,UP,NTRANS +S 2000,1500,2000,3500,200,*,UP,NTRANS +S 1200,1500,1200,3500,200,*,UP,NTRANS +S 2800,3800,2800,5200,200,*,UP,POLY +S 800,7400,3900,7400,300,*,RIGHT,ALU1 +S 4100,4000,4600,4000,200,*,RIGHT,POLY +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 800,700,2400,700,600,*,RIGHT,PTIE +V 3000,5000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 4200,900,CONT_DIF_N,* +V 700,700,CONT_BODY_P,* +V 2000,5000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 3600,900,CONT_DIF_N,* +V 1500,700,CONT_BODY_P,* +V 2300,700,CONT_BODY_P,* +V 800,2000,CONT_DIF_N,* +V 1800,8200,CONT_DIF_P,* +V 4100,8200,CONT_DIF_P,* +V 800,7400,CONT_DIF_P,* +V 3000,7400,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/a3_x2.vbe b/pdks/symbolic/nsxlib/cells/a3_x2.vbe new file mode 100644 index 000000000..7a7b521b3 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 290; + CONSTANT tphh_i1_q : NATURAL := 353; + CONSTANT tphh_i0_q : NATURAL := 395; + CONSTANT tpll_i0_q : NATURAL := 435; + CONSTANT tpll_i1_q : NATURAL := 479; + CONSTANT tpll_i2_q : NATURAL := 521; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x2; + +ARCHITECTURE behaviour_data_flow OF a3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x2" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/a3_x4.ap b/pdks/symbolic/nsxlib/cells/a3_x4.ap new file mode 100644 index 000000000..f82bbade7 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a3_x4.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H a3_x4,P,18/ 9/2019,100 +A 0,0,7000,10000 +R 3000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,q_25 +R 5000,4000,ref_ref,q_20 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 5000,3000,ref_ref,q_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,3000,ref_ref,i0_15 +R 3000,5000,ref_ref,i2_25 +R 3000,4000,ref_ref,i2_20 +R 3000,3000,ref_ref,i2_15 +R 2000,3000,ref_ref,i1_15 +S 1000,3100,1000,6000,300,i0,UP,CALU1 +S 2000,3100,2000,6000,300,i1,UP,CALU1 +S 3000,3100,3000,6000,300,i2,UP,CALU1 +S 5000,2000,5000,8000,300,q,UP,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 1800,6300,1800,7900,600,*,UP,PDIF +S 3000,3100,3000,5900,300,*,UP,ALU1 +S 2000,3100,2000,5900,300,*,UP,ALU1 +S 1000,3100,1000,5900,300,*,UP,ALU1 +S 5800,5500,5800,9500,200,*,UP,PTRANS +S 5200,5700,5200,9300,600,*,UP,PDIF +S 4600,5500,4600,9500,200,*,UP,PTRANS +S 5800,2800,5800,5200,200,*,UP,POLY +S 4600,2800,4600,5200,200,*,UP,POLY +S 600,6300,600,7900,600,*,UP,PDIF +S 2400,6100,2400,8100,200,*,UP,PTRANS +S 1200,6100,1200,8100,200,*,UP,PTRANS +S 800,2000,3900,2000,300,*,RIGHT,ALU1 +S 6200,1100,6200,1900,300,*,UP,ALU1 +S 6200,6100,6200,8900,300,*,UP,ALU1 +S 1800,7800,1800,8800,400,*,UP,ALU1 +S 700,6900,3900,6900,300,*,RIGHT,ALU1 +S 3500,6100,3500,8100,200,*,UP,PTRANS +S 3000,6300,3000,7900,600,*,UP,PDIF +S 1200,2800,1200,5800,200,*,UP,POLY +S 2800,600,2800,2500,200,*,UP,NTRANS +S 4200,800,4200,2300,200,*,UP,NDIF +S 3400,800,3400,2300,600,*,UP,NDIF +S 3500,5600,3500,6000,200,*,UP,POLY +S 2800,2800,2800,4000,200,*,UP,POLY +S 4000,4000,5800,4000,400,*,RIGHT,POLY +S 4000,2100,4000,6800,300,*,UP,ALU1 +S -300,7800,7300,7800,6000,*,RIGHT,NWELL +S 5000,2000,5000,8000,300,*,UP,ALU1 +S 6300,800,6300,2300,300,*,UP,NDIF +S 5800,600,5800,2500,200,*,UP,NTRANS +S 5200,800,5200,2300,600,*,UP,NDIF +S 4600,600,4600,2500,200,*,UP,NTRANS +S 3800,800,3800,2300,600,*,UP,NDIF +S 3200,4000,3200,5600,200,*,UP,POLY +S 3200,5600,3500,5600,200,*,RIGHT,POLY +S 2000,5200,2400,5200,200,*,RIGHT,POLY +S 2000,2800,2000,4900,200,*,UP,POLY +S 2400,5200,2400,5800,200,*,UP,POLY +S 4100,5700,4100,9300,400,*,UP,PDIF +S 6400,5700,6400,9300,400,*,UP,PDIF +S 700,800,700,2300,300,*,UP,NDIF +S 2000,600,2000,2500,200,*,UP,NTRANS +S 1200,600,1200,2500,200,*,UP,NTRANS +V 6200,9100,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1800,7800,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 4200,9200,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 6200,2000,CONT_DIF_N,* +V 6200,6000,CONT_DIF_P,* +V 6200,7000,CONT_DIF_P,* +V 6200,8000,CONT_DIF_P,* +V 6200,900,CONT_DIF_N,* +V 4000,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/a3_x4.vbe b/pdks/symbolic/nsxlib/cells/a3_x4.vbe new file mode 100644 index 000000000..556b6b0fc --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 356; + CONSTANT tphh_i1_q : NATURAL := 428; + CONSTANT tphh_i0_q : NATURAL := 478; + CONSTANT tpll_i0_q : NATURAL := 514; + CONSTANT tpll_i1_q : NATURAL := 554; + CONSTANT tpll_i2_q : NATURAL := 592; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x4; + +ARCHITECTURE behaviour_data_flow OF a3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x4" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/a4_x2.ap b/pdks/symbolic/nsxlib/cells/a4_x2.ap new file mode 100644 index 000000000..806f9f6e4 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a4_x2.ap @@ -0,0 +1,102 @@ +V ALLIANCE : 6 +H a4_x2,P,25/ 9/2019,100 +A 0,0,7000,10000 +R 4000,5000,ref_ref,i3_25 +R 4000,6000,ref_ref,i3_30 +R 3000,6000,ref_ref,i2_30 +R 3000,4000,ref_ref,i2_20 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 6000,8000,ref_ref,q_40 +R 6000,7000,ref_ref,q_35 +R 6000,6000,ref_ref,q_30 +R 6000,5000,ref_ref,q_25 +R 6000,4000,ref_ref,q_20 +R 4000,4000,ref_ref,i3_20 +R 4000,3000,ref_ref,i3_15 +R 2000,6000,ref_ref,i1_30 +R 3000,5000,ref_ref,i2_25 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 6000,3000,ref_ref,q_15 +R 6000,2000,ref_ref,q_10 +R 2000,2000,ref_ref,i1_10 +R 3000,2000,ref_ref,i2_10 +R 2000,3000,ref_ref,i1_15 +R 3000,3000,ref_ref,i2_15 +S 5400,5100,5600,5100,200,*,RIGHT,POLY +S 4900,4500,5600,4500,400,*,RIGHT,POLY +S 3200,6500,3200,8500,200,*,UP,PTRANS +S 2000,6500,2000,8500,200,*,UP,PTRANS +S 1100,6500,1100,8500,200,*,UP,PTRANS +S 1100,3800,1100,6200,200,*,UP,POLY +S 1000,3100,1000,5900,300,*,UP,ALU1 +S 5600,600,5600,2500,200,*,UP,NTRANS +S 5200,1200,5200,2300,400,*,UP,NDIF +S 5900,800,5900,2300,400,*,UP,NDIF +S 600,6700,600,8300,600,*,UP,PDIF +S 1700,600,3900,600,600,*,RIGHT,PTIE +S 5400,5100,5400,5300,200,*,UP,POLY +S 2400,1700,2400,3300,400,*,UP,NDIF +S 3300,1700,3300,3300,400,*,UP,NDIF +S 3800,1500,3800,3500,200,*,UP,NTRANS +S 600,8100,600,8900,400,*,UP,ALU1 +S 6000,5700,6000,9300,600,*,UP,PDIF +S 4900,8100,4900,8800,400,*,UP,ALU1 +S 5400,5500,5400,9500,200,*,UP,PTRANS +S 2600,8000,2600,8800,400,*,UP,ALU1 +S 4200,6500,4200,8500,200,*,UP,PTRANS +S 6000,2000,6000,8000,300,*,UP,ALU1 +S 4000,3100,4000,5900,300,*,UP,ALU1 +S 3000,2100,3000,5900,300,*,UP,ALU1 +S 2000,2100,2000,5900,300,*,UP,ALU1 +S 1900,7000,5000,7000,300,*,RIGHT,ALU1 +S 5100,2100,5100,6900,300,*,UP,ALU1 +S 2600,6700,2600,8300,400,*,UP,PDIF +S 3700,6700,3700,8300,200,*,UP,PDIF +S 1500,6700,1500,8300,200,*,UP,PDIF +S 4900,5700,4900,9300,600,*,UP,PDIF +S 1500,1700,1500,3300,400,*,UP,NDIF +S 4300,2000,5000,2000,300,*,RIGHT,ALU1 +S -300,7800,7300,7800,6000,*,RIGHT,NWELL +S 5600,2800,5600,5000,200,*,UP,POLY +S 4200,4000,4200,6200,200,*,UP,POLY +S 3800,3800,3800,4000,200,*,UP,POLY +S 2900,3800,2900,5100,200,*,UP,POLY +S 3200,4900,3200,6200,200,*,UP,POLY +S 700,1300,700,2200,300,*,UP,ALU1 +S 600,1700,600,3300,400,*,UP,NDIF +S 4300,1700,4300,3300,400,*,UP,NDIF +S 2000,1500,2000,3500,200,*,UP,NTRANS +S 2000,3800,2000,6200,200,*,UP,POLY +S 2900,1500,2900,3500,200,*,UP,NTRANS +S 1100,1500,1100,3500,200,*,UP,NTRANS +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 6000,2100,6000,8000,300,q,UP,CALU1 +S 4000,3100,4000,5900,300,i3,UP,CALU1 +S 3000,2100,3000,5900,300,i2,UP,CALU1 +S 2000,2100,2000,5900,300,i1,UP,CALU1 +S 1000,3000,1000,5900,300,i0,UP,CALU1 +V 5000,4500,CONT_POLY,* +V 3600,600,CONT_BODY_P,* +V 2000,600,CONT_BODY_P,* +V 5200,900,CONT_DIF_N,* +V 6000,2000,CONT_DIF_N,* +V 6000,6000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 4900,8100,CONT_DIF_P,* +V 2600,8000,CONT_DIF_P,* +V 3800,7000,CONT_DIF_P,* +V 1600,7000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 2000,5000,CONT_POLY,* +V 4200,2000,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 700,2200,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/a4_x2.vbe b/pdks/symbolic/nsxlib/cells/a4_x2.vbe new file mode 100644 index 000000000..3a6353969 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 374; + CONSTANT tphh_i1_q : NATURAL := 441; + CONSTANT tpll_i3_q : NATURAL := 455; + CONSTANT tphh_i2_q : NATURAL := 482; + CONSTANT tpll_i2_q : NATURAL := 498; + CONSTANT tphh_i3_q : NATURAL := 506; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x2; + +ARCHITECTURE behaviour_data_flow OF a4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/a4_x4.ap b/pdks/symbolic/nsxlib/cells/a4_x4.ap new file mode 100644 index 000000000..a3feaaa41 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a4_x4.ap @@ -0,0 +1,118 @@ +V ALLIANCE : 6 +H a4_x4,P,26/ 9/2019,100 +A 0,0,8000,10000 +R 1000,5000,ref_ref,i0_25 +R 3000,4000,ref_ref,i2_20 +R 3000,3000,ref_ref,i2_15 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 6000,5000,ref_ref,q_25 +R 6000,4000,ref_ref,q_20 +R 6000,3000,ref_ref,q_15 +R 2000,2000,ref_ref,i1_10 +R 3000,2000,ref_ref,i2_10 +R 1000,4000,ref_ref,i0_20 +R 3000,6000,ref_ref,i2_30 +R 4000,6000,ref_ref,i3_30 +R 4000,5000,ref_ref,i3_25 +R 4000,4000,ref_ref,i3_20 +R 4000,3000,ref_ref,i3_15 +R 2000,6000,ref_ref,i1_30 +R 3000,5000,ref_ref,i2_25 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +R 1000,3000,ref_ref,i0_15 +S 700,1700,700,3300,600,*,UP,NDIF +S 6400,2800,6500,2800,200,*,RIGHT,POLY +S 5500,2800,5600,2800,200,*,RIGHT,POLY +S 6900,800,6900,2300,600,*,UP,NDIF +S 6500,600,6500,2500,200,*,UP,NTRANS +S 5600,600,5600,2500,200,*,UP,NTRANS +S 6000,2000,6000,7900,300,*,UP,ALU1 +S 6000,2000,6000,7900,300,q,UP,CALU1 +S 2000,2100,2000,5900,300,i1,UP,CALU1 +S 3000,2100,3000,5900,300,i2,UP,CALU1 +S 4000,3100,4000,5900,300,i3,UP,CALU1 +S 1000,3100,1000,7000,300,i0,UP,CALU1 +S 5100,2100,5100,6900,300,*,UP,ALU1 +S 2900,8100,2900,8800,400,*,UP,ALU1 +S 2900,6700,2900,8300,400,*,UP,PDIF +S 1900,7000,5000,7000,300,*,RIGHT,ALU1 +S 4000,3100,4000,5900,300,*,UP,ALU1 +S 3000,2100,3000,5900,300,*,UP,ALU1 +S 2000,2100,2000,5900,300,*,UP,ALU1 +S 700,1200,700,2000,400,*,UP,ALU1 +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 4400,6500,4400,8500,200,*,UP,PTRANS +S 5500,5500,5500,9500,200,*,UP,PTRANS +S 1100,1500,1100,3500,200,*,UP,NTRANS +S 2900,1500,2900,3500,200,*,UP,NTRANS +S 3800,1500,3800,3500,200,*,UP,NTRANS +S 600,6700,600,8300,600,*,UP,PDIF +S 6800,6100,6800,8900,300,*,UP,ALU1 +S 6800,1100,6800,1900,300,*,UP,ALU1 +S 3900,6700,3900,8300,200,*,UP,PDIF +S 600,8100,600,8900,300,*,UP,ALU1 +S 6400,5500,6400,9500,200,*,UP,PTRANS +S 6900,5700,6900,9300,400,*,UP,PDIF +S 2900,3800,2900,5100,200,*,UP,POLY +S 3800,3800,3800,4000,200,*,UP,POLY +S 1200,5000,1200,6300,200,*,UP,POLY +S 5500,2800,5500,5300,200,*,UP,POLY +S 6400,2800,6400,5300,200,*,UP,POLY +S 6100,5700,6100,9300,200,*,UP,PDIF +S 1700,600,3900,600,600,*,RIGHT,PTIE +S 3400,6500,3400,8500,200,*,UP,PTRANS +S 1800,6700,1800,8300,600,*,UP,PDIF +S 2400,6500,2400,8500,200,*,UP,PTRANS +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 2000,1500,2000,3500,200,*,UP,NTRANS +S 4300,2000,5000,2000,300,*,RIGHT,ALU1 +S -300,7800,8300,7800,6000,*,RIGHT,NWELL +S 1100,3800,1100,5000,200,*,UP,POLY +S 6000,800,6000,2300,200,*,UP,NDIF +S 6000,5700,6000,9300,400,*,UP,PDIF +S 3300,1700,3300,3300,400,*,UP,NDIF +S 2400,1700,2400,3300,400,*,UP,NDIF +S 1500,1700,1500,3300,400,*,UP,NDIF +S 5000,5700,5000,9300,400,*,UP,PDIF +S 2000,6100,2400,6100,200,*,RIGHT,POLY +S 3200,6100,3400,6100,200,*,RIGHT,POLY +S 4200,6100,4400,6100,200,*,RIGHT,POLY +S 2000,3800,2000,6000,200,*,UP,POLY +S 3200,5000,3200,6000,200,*,UP,POLY +S 4200,4000,4200,6000,200,*,UP,POLY +S 4400,6100,4400,6400,200,*,UP,POLY +S 3400,6100,3400,6400,200,*,UP,POLY +S 2400,6100,2400,6400,200,*,UP,POLY +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 5500,5000,6300,5000,400,*,RIGHT,POLY +S 4900,4500,5500,4500,200,*,RIGHT,POLY +V 6900,6000,CONT_DIF_P,* +V 6900,900,CONT_DIF_N,* +V 6900,2000,CONT_DIF_N,* +V 6000,2000,CONT_DIF_N,* +V 2000,5000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 2000,600,CONT_BODY_P,* +V 3600,600,CONT_BODY_P,* +V 600,8000,CONT_DIF_P,* +V 4200,2000,CONT_DIF_N,* +V 5100,9200,CONT_DIF_P,* +V 700,2000,CONT_DIF_N,* +V 4000,7000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 6900,8000,CONT_DIF_P,* +V 6900,7000,CONT_DIF_P,* +V 2900,8100,CONT_DIF_P,* +V 6800,9100,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 4900,4500,CONT_POLY,* +V 5200,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/a4_x4.vbe b/pdks/symbolic/nsxlib/cells/a4_x4.vbe new file mode 100644 index 000000000..4f96afa4c --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/a4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 540; + CONSTANT rdown_i1_q : NATURAL := 540; + CONSTANT rdown_i2_q : NATURAL := 540; + CONSTANT rdown_i3_q : NATURAL := 540; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 505; + CONSTANT tpll_i3_q : NATURAL := 538; + CONSTANT tpll_i2_q : NATURAL := 576; + CONSTANT tphh_i1_q : NATURAL := 578; + CONSTANT tpll_i1_q : NATURAL := 614; + CONSTANT tphh_i2_q : NATURAL := 627; + CONSTANT tpll_i0_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 661; + CONSTANT transistors : NATURAL := 13 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x4; + +ARCHITECTURE behaviour_data_flow OF a4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/an12_x1.ap b/pdks/symbolic/nsxlib/cells/an12_x1.ap new file mode 100644 index 000000000..1fb985f80 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/an12_x1.ap @@ -0,0 +1,77 @@ +V ALLIANCE : 6 +H an12_x1,P,29/ 4/2024,100 +A 0,0,5000,10000 +R 3000,6000,ref_ref,i1_30 +R 3000,7000,ref_ref,i1_35 +R 3000,8000,ref_ref,i1_40 +R 2000,6000,ref_ref,i0_30 +R 2000,5000,ref_ref,i0_25 +R 3000,5000,ref_ref,i1_25 +R 2000,2000,ref_ref,q_10 +R 2000,8000,ref_ref,i0_40 +R 2000,7000,ref_ref,i0_35 +R 3000,4000,ref_ref,i1_20 +R 3000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,q_15 +R 1000,5000,ref_ref,q_25 +S 3500,5100,3800,5100,200,*,RIGHT,POLY +S 3500,2900,3800,2900,200,*,RIGHT,POLY +S 700,5000,800,5000,300,*,RIGHT,ALU1 +S 600,3000,600,4900,300,*,UP,ALU1 +S 1000,5100,1000,8000,300,q,UP,CALU1 +S 1000,5100,1000,7900,300,*,UP,ALU1 +S 3100,5000,3300,5000,300,*,RIGHT,ALU1 +S 1400,2800,1400,4000,200,*,UP,POLY +S 600,3000,900,3000,300,*,RIGHT,ALU1 +S 4100,8200,4100,9300,600,*,UP,NTIE +S 3200,5700,3200,9300,400,*,UP,PDIF +S 2600,4000,4100,4000,200,*,RIGHT,POLY +S 4300,2100,4300,6900,300,*,UP,ALU1 +S 2600,4100,2600,5200,200,*,UP,POLY +S 800,5700,800,8300,600,*,UP,PDIF +S 3800,5500,3800,7500,200,*,UP,PTRANS +S 1200,5700,1200,8300,600,*,UP,PDIF +S 2600,5500,2600,9500,200,*,UP,PTRANS +S 1800,5500,1800,9500,200,*,UP,PTRANS +S 3800,1500,3800,2500,200,*,UP,NTRANS +S 2600,1500,2600,2500,200,*,UP,NTRANS +S 1400,1500,1400,2500,200,*,UP,NTRANS +S 2000,1700,2000,2300,600,*,UP,NDIF +S 2600,2800,2600,4000,200,*,UP,POLY +S 2000,4100,2000,7900,300,*,UP,ALU1 +S 2000,2100,2000,3000,300,*,UP,ALU1 +S 1000,3000,1900,3000,300,*,RIGHT,ALU1 +S 800,1700,800,2300,600,*,UP,NDIF +S 1000,1200,1000,1900,400,*,UP,ALU1 +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 3200,1700,3200,2300,600,*,UP,NDIF +S 3200,1200,3200,2000,400,*,UP,ALU1 +S 4300,1700,4300,2300,400,*,UP,NDIF +S 4300,5700,4300,7300,400,*,UP,PDIF +S 3100,3000,3300,3000,400,*,RIGHT,ALU1 +S -300,7800,5300,7800,6000,*,RIGHT,NWELL +S 1500,4000,2000,4000,400,*,RIGHT,ALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 2000,4100,2000,7900,300,i0,UP,CALU1 +S 3000,3100,3000,7900,300,i1,UP,CALU1 +S 1400,4600,1800,4600,200,*,RIGHT,POLY +S 1800,4700,1800,5200,200,*,UP,POLY +S 1400,4000,1400,4600,200,*,DOWN,POLY +V 3500,5000,CONT_POLY,* +V 3500,3000,CONT_POLY,* +V 4200,6000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 4200,4000,CONT_POLY,* +V 4200,2000,CONT_DIF_N,* +V 3200,2000,CONT_DIF_N,* +V 1000,1900,CONT_DIF_N,* +V 1000,6000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 2000,2000,CONT_DIF_N,* +V 4100,9100,CONT_BODY_N,* +V 1400,4000,CONT_POLY,* +V 3000,9100,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/an12_x1.vbe b/pdks/symbolic/nsxlib/cells/an12_x1.vbe new file mode 100644 index 000000000..10267b443 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/an12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 3640; + CONSTANT rdown_i1_q : NATURAL := 3640; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i0_q : NATURAL := 168; + CONSTANT tphl_i0_q : NATURAL := 200; + CONSTANT tphh_i1_q : NATURAL := 285; + CONSTANT tpll_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x1; + +ARCHITECTURE behaviour_data_flow OF an12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x1" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/an12_x4.ap b/pdks/symbolic/nsxlib/cells/an12_x4.ap new file mode 100644 index 000000000..28d41ad5c --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/an12_x4.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H an12_x4,P,25/ 9/2019,100 +A 0,0,8000,10000 +R 6000,5000,ref_ref,q_25 +R 6000,4000,ref_ref,q_20 +R 5000,7000,ref_ref,i1_35 +R 5000,8000,ref_ref,i1_40 +R 5000,4000,ref_ref,i1_20 +R 5000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i0_25 +R 2000,4000,ref_ref,i0_20 +R 2000,7000,ref_ref,i0_35 +R 2000,6000,ref_ref,i0_30 +R 2000,3000,ref_ref,i0_15 +R 5000,2000,ref_ref,i1_10 +R 6000,3000,ref_ref,q_15 +S 4600,2900,4600,3100,200,*,UP,POLY +S 4600,3200,5000,3200,200,*,RIGHT,POLY +S 1200,6200,1200,6400,200,*,UP,POLY +S 1400,2000,1400,2200,200,*,UP,POLY +S 4600,2700,4600,2800,200,*,UP,POLY +S 4400,5100,5000,5100,200,*,RIGHT,POLY +S 1200,6200,1200,6400,200,*,UP,POLY +S 1200,6100,2100,6100,200,*,RIGHT,POLY +S 4400,5100,4400,6200,200,*,UP,POLY +S 5000,5700,5000,9300,400,*,UP,PDIF +S 7200,5700,7200,9300,400,*,UP,PDIF +S 3000,800,3000,2300,600,*,UP,NDIF +S 3900,2100,3900,7900,300,*,UP,ALU1 +S 5600,2800,5600,5200,200,*,UP,POLY +S 4400,6500,4400,8500,200,*,UP,PTRANS +S 6200,5700,6200,9300,600,*,UP,PDIF +S 5600,5500,5600,9500,200,*,UP,PTRANS +S 3800,6700,3800,8300,600,*,UP,PDIF +S -300,7800,8300,7800,6000,*,RIGHT,NWELL +S 3200,6500,3200,8500,200,*,UP,PTRANS +S 3100,2000,3800,2000,300,*,RIGHT,ALU1 +S 2000,1100,2000,1700,400,*,UP,NDIF +S 7200,800,7200,2300,400,*,UP,NDIF +S 6000,2100,6000,7900,300,*,UP,ALU1 +S 700,1700,700,2600,400,*,UP,NDIF +S 1400,900,1400,1900,200,*,UP,NTRANS +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 1900,1300,1900,1600,400,*,UP,ALU1 +S 800,2700,800,7900,300,*,UP,ALU1 +S 6600,600,6600,2500,200,*,UP,NTRANS +S 5600,600,5600,2500,200,*,UP,NTRANS +S 6200,800,6200,2300,600,*,UP,NDIF +S 5000,800,5000,2300,600,*,UP,NDIF +S 5000,2100,5000,7900,300,*,UP,ALU1 +S 700,6700,700,8300,400,*,UP,PDIF +S 800,1100,800,1700,600,*,UP,NDIF +S 2200,6700,2200,8300,1400,*,UP,PDIF +S 2200,8000,2200,8800,400,*,UP,ALU1 +S 7000,1100,7000,1900,300,*,UP,ALU1 +S 4000,4000,6600,4000,200,*,RIGHT,POLY +S 7000,6100,7000,8900,300,*,UP,ALU1 +S 6600,5500,6600,9500,200,*,UP,PTRANS +S 6600,2800,6600,5200,200,*,UP,POLY +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 3600,2600,3600,2900,200,*,UP,POLY +S 3200,3000,3200,6200,200,*,UP,POLY +S 1400,2300,1800,2300,200,*,RIGHT,POLY +S 3200,2900,3600,2900,200,*,RIGHT,POLY +S 700,5000,3200,5000,200,*,RIGHT,POLY +S 1800,2400,1800,3100,200,*,UP,POLY +S 4100,800,4100,2300,400,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 4600,600,4600,2500,200,*,UP,NTRANS +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 6000,2100,6000,7900,300,q,UP,CALU1 +S 5000,2100,5000,7900,300,i1,UP,CALU1 +S 2000,3100,2000,6900,300,i0,UP,CALU1 +V 5000,3400,CONT_POLY,* +V 800,5000,CONT_POLY,* +V 5000,900,CONT_DIF_N,* +V 7000,900,CONT_DIF_N,* +V 5200,9100,CONT_DIF_P,* +V 7000,9100,CONT_DIF_P,* +V 5000,5000,CONT_POLY,* +V 1900,1600,CONT_DIF_N,* +V 2000,3000,CONT_POLY,* +V 800,2600,CONT_DIF_N,* +V 3800,7000,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 3800,8000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 2000,6000,CONT_POLY,* +V 6000,8000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 6000,2000,CONT_DIF_N,* +V 7000,8000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,6000,CONT_DIF_P,* +V 7000,2000,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 2200,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/an12_x4.vbe b/pdks/symbolic/nsxlib/cells/an12_x4.vbe new file mode 100644 index 000000000..0d030a6cb --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/an12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphl_i0_q : NATURAL := 461; + CONSTANT tplh_i0_q : NATURAL := 471; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x4; + +ARCHITECTURE behaviour_data_flow OF an12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x4" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/ao22_x2.ap b/pdks/symbolic/nsxlib/cells/ao22_x2.ap new file mode 100644 index 000000000..c1bfe031f --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ao22_x2.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H ao22_x2,P,26/ 9/2019,100 +A 0,0,6000,10000 +R 5000,4000,ref_ref,q_20 +R 4000,6000,ref_ref,i2_30 +R 4000,5000,ref_ref,i2_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 1000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 5000,3000,ref_ref,q_15 +R 5000,2000,ref_ref,q_10 +R 2000,6000,ref_ref,i1_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 5000,8000,ref_ref,q_40 +R 5000,7000,ref_ref,q_35 +R 5000,6000,ref_ref,q_30 +R 5000,5000,ref_ref,q_25 +S 3500,2600,3500,2800,200,*,UP,POLY +S 3500,2800,4000,2800,200,*,RIGHT,POLY +S 5000,2100,5000,8000,300,*,UP,ALU1 +S 3500,6300,3500,8300,200,*,UP,PTRANS +S 2400,6300,2400,8300,200,*,UP,PTRANS +S 1200,6300,1200,8300,200,*,UP,PTRANS +S 1800,6500,1800,8100,600,*,UP,PDIF +S 700,6500,700,8100,400,*,UP,PDIF +S 3000,6500,3000,8100,600,*,UP,PDIF +S 2900,4400,4600,4400,200,*,RIGHT,POLY +S 2400,5200,2400,6100,200,*,UP,POLY +S 2000,3800,2600,3800,200,*,RIGHT,POLY +S 2000,5200,2400,5200,200,*,RIGHT,POLY +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 2000,4100,2000,7900,300,*,UP,ALU1 +S 1200,2800,1200,6200,200,*,UP,POLY +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 3000,1700,3000,2300,600,*,UP,NDIF +S -300,7800,6300,7800,6000,*,RIGHT,NWELL +S 4600,5500,4600,9500,200,*,UP,PTRANS +S 4600,2800,4600,5200,200,*,UP,POLY +S 1500,9200,3300,9200,400,*,RIGHT,NTIE +S 4600,600,4600,2500,200,*,UP,NTRANS +S 3500,5200,3500,6200,200,*,UP,POLY +S 1000,4100,1000,6900,300,*,UP,ALU1 +S 800,8000,800,8800,400,*,UP,ALU1 +S 900,2000,2900,2000,300,*,RIGHT,ALU1 +S 700,1700,700,2300,400,*,UP,NDIF +S 2600,1500,2600,2500,200,*,UP,NTRANS +S 3500,1500,3500,2500,200,*,UP,NTRANS +S 2600,2800,2600,3600,200,*,UP,POLY +S 1900,3200,2900,3200,300,*,RIGHT,ALU1 +S 4000,3100,4000,7900,300,*,UP,ALU1 +S 4200,1100,4200,2000,300,*,UP,ALU1 +S 1900,1700,1900,3000,600,*,UP,NDIF +S 4100,800,4100,2300,400,*,UP,NDIF +S 4100,5700,4100,9300,400,*,UP,PDIF +S 5200,5700,5200,9300,400,*,UP,PDIF +S 5200,800,5200,2300,400,*,UP,NDIF +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 5000,2100,5000,8000,300,q,UP,CALU1 +S 4000,3100,4000,7900,300,i2,UP,CALU1 +S 2000,4100,2000,7900,300,i1,UP,CALU1 +S 1000,4100,1000,6900,300,i0,UP,CALU1 +S 3500,5200,4000,5200,200,*,RIGHT,POLY +V 4000,3000,CONT_POLY,* +V 4100,2000,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,* +V 4200,9200,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 4000,5000,CONT_POLY,* +V 3000,4400,CONT_POLY,* +V 1800,9100,CONT_BODY_N,* +V 3000,9100,CONT_BODY_N,* +V 2000,5000,CONT_POLY,* +V 3000,7800,CONT_DIF_P,* +V 3000,6800,CONT_DIF_P,* +V 1900,3100,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/ao22_x2.vbe b/pdks/symbolic/nsxlib/cells/ao22_x2.vbe new file mode 100644 index 000000000..7cfca61f3 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ao22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 420; + CONSTANT tpll_i2_q : NATURAL := 425; + CONSTANT tpll_i0_q : NATURAL := 447; + CONSTANT tphh_i1_q : NATURAL := 493; + CONSTANT tpll_i1_q : NATURAL := 526; + CONSTANT tphh_i0_q : NATURAL := 558; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x2; + +ARCHITECTURE behaviour_data_flow OF ao22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/ao22_x4.ap b/pdks/symbolic/nsxlib/cells/ao22_x4.ap new file mode 100644 index 000000000..638564808 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ao22_x4.ap @@ -0,0 +1,109 @@ +V ALLIANCE : 6 +H ao22_x4,P,25/ 9/2019,100 +A 0,0,8000,10000 +R 6000,5000,ref_ref,q_25 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 6000,3000,ref_ref,q_15 +R 4000,6000,ref_ref,i2_30 +R 4000,5000,ref_ref,i2_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 6000,4000,ref_ref,q_20 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 6000,2000,ref_ref,q_10 +R 6000,8000,ref_ref,q_40 +R 6000,7000,ref_ref,q_35 +R 6000,6000,ref_ref,q_30 +S 2900,2500,2900,3700,200,*,UP,POLY +S 4700,800,4700,2200,600,*,UP,NDIF +S 1200,2700,1200,6200,200,*,UP,POLY +S 700,1600,700,2200,400,*,UP,NDIF +S 4400,1600,4400,2200,400,*,UP,NDIF +S 3400,1600,3400,2200,200,*,UP,NDIF +S 3800,1400,3800,2400,200,*,UP,NTRANS +S 2300,1600,2300,2200,200,*,UP,NDIF +S 2900,1400,2900,2400,200,*,UP,NTRANS +S 1700,1600,1700,2200,200,*,UP,NDIF +S 2000,1600,2000,3000,400,*,UP,NDIF +S 1200,1400,1200,2400,200,*,UP,NTRANS +S 2000,5200,2400,5200,200,*,RIGHT,POLY +S 3600,5200,4000,5200,200,*,RIGHT,POLY +S 3000,4200,6600,4200,200,*,RIGHT,POLY +S 6600,2800,6600,5200,200,*,UP,POLY +S 5400,2800,5400,5200,200,*,UP,POLY +S 3600,5200,3600,6200,200,*,UP,POLY +S 6000,2100,6000,7900,300,*,UP,ALU1 +S 7200,6100,7200,8900,300,*,UP,ALU1 +S 7200,1100,7200,1900,300,*,UP,ALU1 +S 2000,4100,2000,7900,300,*,UP,ALU1 +S 2400,6300,2400,8300,200,*,UP,PTRANS +S 3600,6300,3600,8300,200,*,UP,PTRANS +S 4000,3100,4000,7900,300,*,UP,ALU1 +S 7200,800,7200,2300,600,*,UP,NDIF +S 6600,600,6600,2500,200,*,UP,NTRANS +S 6000,800,6000,2300,600,*,UP,NDIF +S 5400,600,5400,2500,200,*,UP,NTRANS +S 4800,800,4800,2300,400,*,UP,NDIF +S 1200,6300,1200,8300,200,*,UP,PTRANS +S 700,6500,700,8100,400,*,UP,PDIF +S 4800,5700,4800,9300,800,*,UP,PDIF +S 800,8000,800,8700,400,*,UP,ALU1 +S 1000,4100,1000,6900,300,*,UP,ALU1 +S -300,7800,8300,7800,6000,*,RIGHT,NWELL +S 7200,5700,7200,9300,600,*,UP,PDIF +S 6600,5500,6600,9500,200,*,UP,PTRANS +S 6000,5700,6000,9300,600,*,UP,PDIF +S 5400,5500,5400,9500,200,*,UP,PTRANS +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 900,2000,3300,2000,300,*,RIGHT,ALU1 +S 2000,3700,2900,3700,200,*,RIGHT,POLY +S 4200,6500,4200,8100,200,*,UP,PDIF +S 1800,6500,1800,8100,600,*,UP,PDIF +S 3800,2700,3800,3100,200,*,UP,POLY +S 1900,3100,2900,3100,300,*,RIGHT,ALU1 +S 4500,5700,4500,9300,600,*,UP,PDIF +S 1500,9200,3300,9200,400,*,RIGHT,NTIE +S 2400,5400,2400,6000,200,*,UP,POLY +S 3000,6500,3000,8100,600,*,UP,PDIF +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 6000,2100,6000,7900,300,q,UP,CALU1 +S 4000,3100,4000,7900,300,i2,UP,CALU1 +S 2000,4100,2000,7900,300,i1,UP,CALU1 +S 1000,4100,1000,6900,300,i0,UP,CALU1 +V 4900,900,CONT_DIF_N,* +V 7200,900,CONT_DIF_N,* +V 7200,9100,CONT_DIF_P,* +V 4600,9100,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 3400,2000,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 7200,7000,CONT_DIF_P,* +V 7200,8000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 7200,6000,CONT_DIF_P,* +V 6000,2000,CONT_DIF_N,* +V 7200,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 4000,3000,CONT_POLY,* +V 4000,5000,CONT_POLY,* +V 3000,4400,CONT_POLY,* +V 3000,9100,CONT_BODY_N,* +V 1800,9100,CONT_BODY_N,* +V 3000,7800,CONT_DIF_P,* +V 3000,6800,CONT_DIF_P,* +V 2000,5000,CONT_POLY,* +V 2000,3100,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/ao22_x4.vbe b/pdks/symbolic/nsxlib/cells/ao22_x4.vbe new file mode 100644 index 000000000..2995c9cca --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tpll_i2_q : NATURAL := 505; + CONSTANT tphh_i2_q : NATURAL := 526; + CONSTANT tpll_i0_q : NATURAL := 552; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 647; + CONSTANT tphh_i0_q : NATURAL := 674; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x4; + +ARCHITECTURE behaviour_data_flow OF ao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/ao2o22_x2.ap b/pdks/symbolic/nsxlib/cells/ao2o22_x2.ap new file mode 100644 index 000000000..069fb61eb --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ao2o22_x2.ap @@ -0,0 +1,112 @@ +V ALLIANCE : 6 +H ao2o22_x2,P,25/ 9/2019,100 +A 0,0,9000,10000 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +R 8000,7000,ref_ref,q_35 +R 8000,5000,ref_ref,q_25 +R 8000,3000,ref_ref,q_15 +R 8000,2000,ref_ref,q_10 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 2000,4000,ref_ref,i1_20 +R 8000,6000,ref_ref,q_30 +R 8000,4000,ref_ref,q_20 +R 8000,8000,ref_ref,q_40 +R 5000,7000,ref_ref,i3_35 +R 4000,7000,ref_ref,i2_35 +R 1000,7000,ref_ref,i0_35 +R 5000,3000,ref_ref,i3_15 +R 5000,4000,ref_ref,i3_20 +R 5000,5000,ref_ref,i3_25 +R 5000,6000,ref_ref,i3_30 +S 3500,2700,3500,3000,200,*,UP,POLY +S 3400,3100,3400,5900,200,*,UP,POLY +S 3400,3000,3500,3000,200,*,LEFT,POLY +S 3400,6000,3500,6000,200,*,RIGHT,POLY +S 1900,3200,2900,3200,300,*,RIGHT,ALU1 +S 6000,4000,6800,4000,300,*,RIGHT,ALU1 +S 3500,4200,4000,4200,200,*,LEFT,POLY +S 2000,4200,2600,4200,200,*,LEFT,POLY +S 2600,2800,2600,4100,200,*,UP,POLY +S 2400,4300,2400,6100,200,*,UP,POLY +S 3500,1500,3500,2500,200,*,UP,NTRANS +S 4900,1500,4900,2500,200,*,UP,NTRANS +S 3000,1700,3000,2300,600,*,UP,NDIF +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 3000,6500,3000,8100,600,*,UP,PDIF +S 3500,6300,3500,8300,200,*,UP,PTRANS +S 800,8000,800,8800,400,*,UP,ALU1 +S 1000,4100,1000,6900,300,*,UP,ALU1 +S 900,2000,5300,2000,300,*,RIGHT,ALU1 +S 700,1700,700,2300,400,*,UP,NDIF +S 4900,2800,4900,6200,200,*,UP,POLY +S 1500,9200,4500,9200,400,*,RIGHT,NTIE +S 6000,4100,6000,7700,300,*,UP,ALU1 +S 4900,6300,4900,8300,200,*,UP,PTRANS +S 4200,6500,4200,8100,600,*,UP,PDIF +S 7400,600,7400,2500,200,*,UP,NTRANS +S -300,7800,9300,7800,6000,*,RIGHT,NWELL +S 7400,5500,7400,9500,200,*,UP,PTRANS +S 8000,5700,8000,9300,600,*,UP,PDIF +S 7400,2800,7400,5200,200,*,UP,POLY +S 8000,2100,8000,7900,300,*,UP,ALU1 +S 700,6500,700,8100,400,*,UP,PDIF +S 2400,6300,2400,8300,200,*,UP,PTRANS +S 1800,6500,1800,8100,600,*,UP,PDIF +S 3300,7800,5900,7800,300,*,RIGHT,ALU1 +S 1200,6300,1200,8300,200,*,UP,PTRANS +S 6800,800,6800,2300,600,*,UP,NDIF +S 8000,800,8000,2300,600,*,UP,NDIF +S 7000,4000,7300,4000,400,*,RIGHT,POLY +S 5700,6500,5700,9300,600,*,UP,PDIF +S 4200,1000,4200,2300,400,*,UP,NDIF +S 1900,1700,1900,3100,400,*,UP,NDIF +S 6800,5700,6800,9300,600,*,UP,PDIF +S 2600,1500,2600,2500,200,*,UP,NTRANS +S 3000,3200,3000,7900,300,*,UP,ALU1 +S 1200,2800,1200,6200,200,*,UP,POLY +S 5400,1700,5400,2300,600,*,UP,NDIF +S 2000,4100,2000,7900,300,*,UP,ALU1 +S 4000,3100,4000,6900,300,*,UP,ALU1 +S 5000,3100,5000,6900,300,*,UP,ALU1 +S 6800,1100,6800,1900,300,*,UP,ALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 8000,2000,8000,8000,300,q,UP,CALU1 +S 4000,3100,4000,6900,300,i2,UP,CALU1 +S 5000,3100,5000,6900,300,i3,UP,CALU1 +S 2000,4100,2000,7900,300,i1,UP,CALU1 +S 1000,4100,1000,6900,300,i0,UP,CALU1 +V 1900,3200,CONT_DIF_N,* +V 6800,4000,CONT_POLY,* +V 1800,9100,CONT_BODY_N,* +V 3000,9100,CONT_BODY_N,* +V 4200,9100,CONT_BODY_N,* +V 3000,6800,CONT_DIF_P,* +V 3000,7800,CONT_DIF_P,* +V 4200,800,CONT_DIF_N,* +V 8000,8000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 8000,2000,CONT_DIF_N,* +V 6800,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 5400,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 800,2000,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,* +V 6800,9200,CONT_DIF_P,* +V 6800,900,CONT_DIF_N,* +V 5700,9200,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/ao2o22_x2.vbe b/pdks/symbolic/nsxlib/cells/ao2o22_x2.vbe new file mode 100644 index 000000000..c503d1b97 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ao2o22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 432; + CONSTANT tpll_i0_q : NATURAL := 451; + CONSTANT tphh_i3_q : NATURAL := 488; + CONSTANT tphh_i1_q : NATURAL := 508; + CONSTANT tpll_i3_q : NATURAL := 526; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tphh_i0_q : NATURAL := 572; + CONSTANT tpll_i2_q : NATURAL := 627; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x2; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/ao2o22_x4.ap b/pdks/symbolic/nsxlib/cells/ao2o22_x4.ap new file mode 100644 index 000000000..82693de21 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ao2o22_x4.ap @@ -0,0 +1,127 @@ +V ALLIANCE : 6 +H ao2o22_x4,P,25/ 9/2019,100 +A 0,0,10000,10000 +R 8000,2000,ref_ref,q_10 +R 8000,3000,ref_ref,q_15 +R 8000,5000,ref_ref,q_25 +R 8000,7000,ref_ref,q_35 +R 2000,8000,ref_ref,i1_40 +R 5000,6000,ref_ref,i3_30 +R 4000,6000,ref_ref,i2_30 +R 4000,5000,ref_ref,i2_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 2000,4000,ref_ref,i1_20 +R 2000,7000,ref_ref,i1_35 +R 8000,6000,ref_ref,q_30 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 5000,5000,ref_ref,i3_25 +R 5000,4000,ref_ref,i3_20 +R 5000,3000,ref_ref,i3_15 +R 1000,7000,ref_ref,i0_35 +R 4000,7000,ref_ref,i2_35 +R 5000,7000,ref_ref,i3_35 +R 8000,8000,ref_ref,q_40 +R 8000,4000,ref_ref,q_20 +S 2400,6100,2400,6400,200,*,DOWN,POLY +S 2000,5200,2000,6000,200,*,DOWN,POLY +S 2000,6100,2400,6100,200,*,LEFT,POLY +S 3600,6100,3600,6300,200,*,DOWN,POLY +S 4000,4300,4000,6000,200,*,DOWN,POLY +S 3600,6100,4000,6100,200,*,RIGHT,POLY +S 2000,4800,2400,4800,200,*,LEFT,POLY +S 2400,2800,2400,4600,200,*,UP,POLY +S 3600,3800,4000,3800,200,*,RIGHT,POLY +S 3600,2800,3600,3700,200,*,UP,POLY +S 6000,4000,6700,4000,300,*,RIGHT,ALU1 +S 5400,1700,5400,2300,600,*,UP,NDIF +S 4200,6700,4200,8300,600,*,UP,PDIF +S 1200,2800,1200,6200,200,*,UP,POLY +S 2400,1500,2400,2500,200,*,UP,NTRANS +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 3600,1500,3600,2500,200,*,UP,NTRANS +S 3000,1700,3000,2300,600,*,UP,NDIF +S 2400,6500,2400,8500,200,*,UP,PTRANS +S 4800,6500,4800,8500,200,*,UP,PTRANS +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 2000,4100,2000,7900,300,*,UP,ALU1 +S 1900,3000,2900,3000,300,*,RIGHT,ALU1 +S 4000,3100,4000,6900,300,*,UP,ALU1 +S -300,7800,10300,7800,6000,*,RIGHT,NWELL +S 8600,600,8600,2500,200,*,UP,NTRANS +S 9200,800,9200,2300,400,*,UP,NDIF +S 8000,800,8000,2300,600,*,UP,NDIF +S 7400,600,7400,2500,200,*,UP,NTRANS +S 3600,6500,3600,8500,200,*,UP,PTRANS +S 3000,6700,3000,8300,600,*,UP,PDIF +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 1800,6700,1800,8300,600,*,UP,PDIF +S 9000,1100,9000,1900,300,*,UP,ALU1 +S 7000,4000,8600,4000,400,*,RIGHT,POLY +S 5300,6700,5300,8300,400,*,UP,PDIF +S 1800,1700,1800,3100,400,*,UP,NDIF +S 6800,900,6800,2300,400,*,UP,NDIF +S 6000,4100,6000,7900,300,*,UP,ALU1 +S 3300,8000,5900,8000,300,*,RIGHT,ALU1 +S 7400,5500,7400,9500,200,*,UP,PTRANS +S 8600,5500,8600,9500,200,*,UP,PTRANS +S 8000,5700,8000,9300,600,*,UP,PDIF +S 6800,5700,6800,9300,600,*,UP,PDIF +S 8600,2800,8600,5200,200,*,UP,POLY +S 7400,2800,7400,5200,200,*,UP,POLY +S 8000,2100,8000,7900,300,*,UP,ALU1 +S 5000,3100,5000,6900,300,*,UP,ALU1 +S 7000,1100,7000,1900,300,*,UP,ALU1 +S 5700,6700,5700,9100,600,*,UP,PDIF +S 5000,1500,5000,2500,200,*,UP,NTRANS +S 9200,5700,9200,9300,400,*,UP,PDIF +S 9000,6100,9000,8900,300,*,UP,ALU1 +S 700,1700,700,2300,400,*,UP,NDIF +S 800,2000,5300,2000,300,*,RIGHT,ALU1 +S 1000,4100,1000,6900,300,*,UP,ALU1 +S 800,8000,800,8800,400,*,UP,ALU1 +S 700,6700,700,8300,400,*,UP,PDIF +S 4300,900,4300,2300,400,*,UP,NDIF +S 4800,6000,5000,6000,200,*,RIGHT,POLY +S 5000,2800,5000,6000,200,*,UP,POLY +S 4800,6000,4800,6400,200,*,UP,POLY +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 4000,3100,4000,6900,300,i2,UP,CALU1 +S 5000,3100,5000,6900,300,i3,UP,CALU1 +S 2000,4100,2000,7900,300,i1,UP,CALU1 +S 1000,4100,1000,6900,300,i0,UP,CALU1 +S 8000,2100,8000,7900,300,q,UP,CALU1 +V 6700,4000,CONT_POLY,* +V 800,2000,CONT_DIF_N,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 1800,3200,CONT_DIF_N,* +V 4300,800,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,* +V 9000,900,CONT_DIF_N,* +V 5700,9100,CONT_DIF_P,* +V 9000,9100,CONT_DIF_P,* +V 6800,9100,CONT_DIF_P,* +V 6900,900,CONT_DIF_N,* +V 8000,8000,CONT_DIF_P,* +V 1000,5000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 5900,800,CONT_BODY_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 8000,2000,CONT_DIF_N,* +V 3000,7000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 5400,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 5000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 9000,2000,CONT_DIF_N,* +V 7000,2000,CONT_DIF_N,* +V 9000,6000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/ao2o22_x4.vbe b/pdks/symbolic/nsxlib/cells/ao2o22_x4.vbe new file mode 100644 index 000000000..61a5bff61 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 554; + CONSTANT tpll_i0_q : NATURAL := 569; + CONSTANT tphh_i3_q : NATURAL := 606; + CONSTANT tphh_i1_q : NATURAL := 637; + CONSTANT tpll_i3_q : NATURAL := 639; + CONSTANT tpll_i1_q : NATURAL := 666; + CONSTANT tphh_i0_q : NATURAL := 696; + CONSTANT tpll_i2_q : NATURAL := 744; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/buf_x2.ap b/pdks/symbolic/nsxlib/cells/buf_x2.ap new file mode 100644 index 000000000..d54b963a8 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/buf_x2.ap @@ -0,0 +1,59 @@ +V ALLIANCE : 6 +H buf_x2,P,26/ 9/2019,100 +A 0,0,4000,10000 +R 3000,3000,ref_ref,q_15 +R 3000,5000,ref_ref,q_25 +R 3000,2000,ref_ref,q_10 +R 2000,3000,ref_ref,i_15 +R 2000,2000,ref_ref,i_10 +R 2000,6000,ref_ref,i_30 +R 2000,5000,ref_ref,i_25 +R 2000,4000,ref_ref,i_20 +R 3000,4000,ref_ref,q_20 +R 2000,8000,ref_ref,i_40 +R 2000,7000,ref_ref,i_35 +R 3000,8000,ref_ref,q_40 +R 3000,7000,ref_ref,q_35 +R 3000,6000,ref_ref,q_30 +S 3000,2100,3000,7900,300,q,UP,CALU1 +S 2000,2100,2000,7900,300,i,UP,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 3000,5700,3000,9300,600,*,UP,PDIF +S 3000,2100,3000,7900,300,*,UP,ALU1 +S -300,7800,4300,7800,6000,*,RIGHT,NWELL +S 1200,1900,1200,2500,200,*,UP,NTRANS +S 1200,5500,1200,6700,200,*,UP,PTRANS +S 800,2300,800,5900,300,*,UP,ALU1 +S 700,2100,700,2300,400,*,UP,NDIF +S 700,5700,700,6500,400,*,UP,PDIF +S 1900,5700,1900,9300,400,*,UP,PDIF +S 700,4000,2500,4000,400,*,RIGHT,POLY +S 2500,600,2500,2500,200,*,UP,NTRANS +S 2500,5500,2500,9500,200,*,UP,PTRANS +S 2500,2800,2500,5200,200,*,UP,POLY +S 1900,800,1900,2300,400,*,UP,NDIF +S 3000,800,3000,2300,600,*,UP,NDIF +S 900,8200,900,9200,600,*,UP,NTIE +S 900,8400,900,9200,300,*,UP,ALU1 +S 1600,5700,1600,6500,200,*,UP,PDIF +S 1600,2100,1600,2300,200,*,UP,NDIF +S 1200,2800,1600,2800,200,*,RIGHT,POLY +S 1200,2600,1200,2700,200,*,UP,POLY +S 1200,5200,1200,5500,200,*,UP,POLY +S 1200,5200,1600,5200,200,*,RIGHT,POLY +V 1600,3000,CONT_POLY,* +V 900,9100,CONT_BODY_N,* +V 900,8300,CONT_BODY_N,* +V 800,6000,CONT_DIF_P,* +V 800,4000,CONT_POLY,* +V 800,2200,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 2000,900,CONT_DIF_N,* +V 2000,9100,CONT_DIF_P,* +V 1600,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/buf_x2.vbe b/pdks/symbolic/nsxlib/cells/buf_x2.vbe new file mode 100644 index 000000000..e2e4c344e --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/buf_x2.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 6; + CONSTANT rdown_i_q : NATURAL := 1620; + CONSTANT rup_i_q : NATURAL := 1790; + CONSTANT tpll_i_q : NATURAL := 391; + CONSTANT tphh_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x2; + +ARCHITECTURE behaviour_data_flow OF buf_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x2" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/buf_x4.ap b/pdks/symbolic/nsxlib/cells/buf_x4.ap new file mode 100644 index 000000000..6d1b239df --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/buf_x4.ap @@ -0,0 +1,73 @@ +V ALLIANCE : 6 +H buf_x4,P,25/ 9/2019,100 +A 0,0,5000,10000 +R 3000,6000,ref_ref,q_30 +R 3000,7000,ref_ref,q_35 +R 3000,8000,ref_ref,q_40 +R 2000,7000,ref_ref,i_35 +R 2000,8000,ref_ref,i_40 +R 3000,4000,ref_ref,q_20 +R 2000,4000,ref_ref,i_20 +R 2000,5000,ref_ref,i_25 +R 2000,6000,ref_ref,i_30 +R 2000,2000,ref_ref,i_10 +R 2000,3000,ref_ref,i_15 +R 3000,2000,ref_ref,q_10 +R 3000,5000,ref_ref,q_25 +R 3000,3000,ref_ref,q_15 +S 1200,2600,1200,2800,200,*,UP,POLY +S 1200,2800,1600,2800,200,*,RIGHT,POLY +S 1200,5200,1200,5400,200,*,UP,POLY +S 1200,5200,1600,5200,200,*,RIGHT,POLY +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 3000,5700,3000,9300,600,*,UP,PDIF +S 1200,5500,1200,7500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 3600,2800,3600,5200,200,*,UP,POLY +S 2400,2800,2400,5200,200,*,UP,POLY +S 4200,6100,4200,8900,300,*,UP,ALU1 +S 1700,5000,1900,5000,300,*,RIGHT,ALU1 +S -300,7800,5300,7800,6000,*,RIGHT,NWELL +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 900,8500,900,9200,600,*,UP,NTIE +S 1700,5700,1700,7300,400,*,UP,PDIF +S 1700,1700,1700,2300,200,*,UP,NDIF +S 600,4000,3600,4000,400,*,RIGHT,POLY +S 1700,3000,1900,3000,300,*,RIGHT,ALU1 +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 4100,800,4100,1600,300,*,UP,ALU1 +S 800,2100,800,6900,300,*,UP,ALU1 +S 700,1700,700,2300,400,*,UP,NDIF +S 1900,5700,1900,9300,400,*,UP,PDIF +S 700,5700,700,7300,400,*,UP,PDIF +S 4200,800,4200,2300,400,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 3000,800,3000,2300,600,*,UP,NDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S 1900,800,1900,2300,400,*,UP,NDIF +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 2000,2100,2000,7900,300,i,UP,CALU1 +S 3000,2100,3000,7900,300,q,UP,CALU1 +V 900,9100,CONT_BODY_N,* +V 4100,900,CONT_DIF_N,* +V 800,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 4100,2000,CONT_DIF_N,* +V 2000,900,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 800,4000,CONT_POLY,* +V 800,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 1600,5000,CONT_POLY,* +V 1600,3000,CONT_POLY,* +V 2000,9100,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 4200,6000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 4200,9100,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/buf_x4.vbe b/pdks/symbolic/nsxlib/cells/buf_x4.vbe new file mode 100644 index 000000000..0b7726ef9 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/buf_x4.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i : NATURAL := 9; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphh_i_q : NATURAL := 379; + CONSTANT tpll_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x4; + +ARCHITECTURE behaviour_data_flow OF buf_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x4" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/buf_x8.ap b/pdks/symbolic/nsxlib/cells/buf_x8.ap new file mode 100644 index 000000000..b2cbf5613 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/buf_x8.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H buf_x8,P,25/ 9/2019,100 +A 0,0,8000,10000 +R 2000,3000,ref_ref,i_15 +R 2000,8000,ref_ref,i_40 +R 2000,7000,ref_ref,i_35 +R 2000,5000,ref_ref,i_25 +R 2000,6000,ref_ref,i_30 +R 3000,8000,ref_ref,q_40 +R 3000,2000,ref_ref,q_10 +R 3000,5000,ref_ref,q_25 +R 2000,2000,ref_ref,i_10 +R 3000,3000,ref_ref,q_15 +R 3000,4000,ref_ref,q_20 +R 3000,6000,ref_ref,q_30 +R 3000,7000,ref_ref,q_35 +R 2000,4000,ref_ref,i_20 +S 1200,5200,1200,5400,200,*,UP,POLY +S 1200,5200,1600,5200,200,*,RIGHT,POLY +S 1200,2600,1200,2800,200,*,UP,POLY +S 1200,2800,1600,2800,200,*,RIGHT,POLY +S 6300,6800,6300,8900,300,*,UP,ALU1 +S 6500,800,6500,2300,600,*,UP,NDIF +S 600,4000,5800,4000,400,*,RIGHT,POLY +S 6600,3400,7200,3400,600,*,RIGHT,PTIE +S 5800,2800,5800,5200,200,*,UP,POLY +S 5400,5700,5400,9300,400,*,UP,PDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 2400,600,2400,2500,200,*,UP,NTRANS +S 3000,800,3000,2300,600,*,UP,NDIF +S 1200,600,1200,2500,200,*,UP,NTRANS +S 700,800,700,2300,400,*,UP,NDIF +S 1800,800,1800,2300,600,*,UP,NDIF +S 6400,8000,6400,9300,600,*,UP,PDIF +S 7200,5900,7200,6700,300,*,UP,ALU1 +S 7200,5700,7200,6900,600,*,UP,NTIE +S 6600,6800,7200,6800,300,*,RIGHT,ALU1 +S 5800,5500,5800,9500,200,*,UP,PTRANS +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 1700,3000,1900,3000,300,*,RIGHT,ALU1 +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 6600,1100,6600,3300,300,*,UP,ALU1 +S 6700,3400,7300,3400,300,*,RIGHT,ALU1 +S 800,2100,800,7900,300,*,UP,ALU1 +S 700,5700,700,9300,400,*,UP,PDIF +S -300,7800,8300,7800,6000,*,RIGHT,NWELL +S 1700,5000,1900,5000,300,*,RIGHT,ALU1 +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 3000,5700,3000,9300,600,*,UP,PDIF +S 1800,5700,1800,9300,600,*,UP,PDIF +S 3600,2800,3600,5200,200,*,UP,POLY +S 4200,800,4200,2300,600,*,UP,NDIF +S 4800,600,4800,2500,200,*,UP,NTRANS +S 5400,800,5400,2300,600,*,UP,NDIF +S 5800,600,5800,2500,200,*,UP,NTRANS +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 5400,2100,5400,7900,300,*,UP,ALU1 +S 3100,4000,5300,4000,300,*,RIGHT,ALU1 +S 4200,5700,4200,9300,600,*,UP,PDIF +S 4800,2800,4800,5200,200,*,UP,POLY +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 4200,1100,4200,1900,300,*,UP,ALU1 +S 4200,6100,4200,8900,300,*,UP,ALU1 +S 2400,2800,2400,5200,200,*,UP,POLY +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 2000,2100,2000,7900,300,i,UP,CALU1 +S 3000,2100,3000,7900,300,q,UP,CALU1 +V 7200,3400,CONT_BODY_P,* +V 4200,2000,CONT_DIF_N,* +V 4200,8000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 4200,6000,CONT_DIF_P,* +V 6600,2000,CONT_DIF_N,* +V 6600,3400,CONT_BODY_P,* +V 3000,2000,CONT_DIF_N,* +V 5400,6000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,* +V 5400,2000,CONT_DIF_N,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 800,6000,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 800,4000,CONT_POLY,* +V 7200,6800,CONT_BODY_N,* +V 7200,5800,CONT_BODY_N,* +V 6300,8000,CONT_DIF_P,* +V 6300,9200,CONT_DIF_P,* +V 4200,9200,CONT_DIF_P,* +V 1800,9200,CONT_DIF_P,* +V 1800,900,CONT_DIF_N,* +V 4200,900,CONT_DIF_N,* +V 6600,900,CONT_DIF_N,* +V 1600,3000,CONT_POLY,* +V 1600,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/buf_x8.vbe b/pdks/symbolic/nsxlib/cells/buf_x8.vbe new file mode 100644 index 000000000..3b2ecc3bb --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/buf_x8.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i : NATURAL := 15; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphh_i_q : NATURAL := 343; + CONSTANT tpll_i_q : NATURAL := 396; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x8; + +ARCHITECTURE behaviour_data_flow OF buf_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x8" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/inv_x1.ap b/pdks/symbolic/nsxlib/cells/inv_x1.ap new file mode 100644 index 000000000..2c2740202 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/inv_x1.ap @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H inv_x1,P,18/ 9/2019,100 +A 0,0,3000,10000 +R 2000,2000,ref_ref,nq_10 +R 2000,3000,ref_ref,nq_15 +R 2000,4000,ref_ref,nq_20 +R 2000,5000,ref_ref,nq_25 +R 2000,6000,ref_ref,nq_30 +R 2000,7000,ref_ref,nq_35 +R 2000,8000,ref_ref,nq_40 +R 1000,7000,ref_ref,i_35 +R 1000,8000,ref_ref,i_40 +R 1000,5000,ref_ref,i_25 +R 1000,6000,ref_ref,i_30 +R 1000,3000,ref_ref,i_15 +R 1000,4000,ref_ref,i_20 +S 2000,2100,2000,7900,300,nq,UP,CALU1 +S 1000,3100,1000,7900,300,i,UP,CALU1 +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 800,4000,1400,4000,600,*,RIGHT,POLY +S 1400,2800,1400,5200,200,*,UP,POLY +S -300,7800,3300,7800,6000,*,RIGHT,NWELL +S 1000,3100,1000,7900,300,*,UP,ALU1 +S 700,1700,700,2300,400,*,UP,NDIF +S 1000,1200,1000,2000,300,*,UP,ALU1 +S 700,5700,700,9400,400,*,UP,PDIF +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 2000,8400,2000,9300,600,*,UP,NTIE +S 1400,5500,1400,7500,200,*,UP,PTRANS +S 2000,5700,2000,7300,600,*,UP,PDIF +S 1400,1500,1400,2500,200,*,UP,NTRANS +S 2000,1700,2000,2300,600,*,UP,NDIF +V 1000,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 2000,2000,CONT_DIF_N,* +V 2000,7000,CONT_DIF_P,* +V 2000,6000,CONT_DIF_P,* +V 800,9400,CONT_DIF_P,* +V 2000,9100,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/inv_x1.vbe b/pdks/symbolic/nsxlib/cells/inv_x1.vbe new file mode 100644 index 000000000..67e85e029 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/inv_x1.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_i_nq : NATURAL := 3640; + CONSTANT rup_i_nq : NATURAL := 3720; + CONSTANT tphl_i_nq : NATURAL := 101; + CONSTANT tplh_i_nq : NATURAL := 139; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x1; + +ARCHITECTURE behaviour_data_flow OF inv_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x1" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/inv_x2.ap b/pdks/symbolic/nsxlib/cells/inv_x2.ap new file mode 100644 index 000000000..fe8d2491c --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/inv_x2.ap @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H inv_x2,P,27/ 9/2019,100 +A 0,0,3000,10000 +R 1000,6000,ref_ref,i_30 +R 1000,7000,ref_ref,i_35 +R 2000,8000,ref_ref,nq_40 +R 2000,7000,ref_ref,nq_35 +R 2000,6000,ref_ref,nq_30 +R 2000,5000,ref_ref,nq_25 +R 2000,4000,ref_ref,nq_20 +R 2000,3000,ref_ref,nq_15 +R 2000,2000,ref_ref,nq_10 +R 1000,3000,ref_ref,i_15 +R 1000,4000,ref_ref,i_20 +R 1000,5000,ref_ref,i_25 +S 1300,3800,1300,4200,300,*,DOWN,POLY +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 1500,5500,1500,8500,200,*,UP,PTRANS +S 1500,3800,1500,5200,200,*,UP,POLY +S 1500,1500,1500,3500,200,*,UP,NTRANS +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 2000,5700,2000,8300,600,*,UP,PDIF +S 2000,1700,2000,3300,600,*,UP,NDIF +S -300,7800,3300,7800,6000,*,RIGHT,NWELL +S 800,5700,800,8300,400,*,UP,PDIF +S 800,1700,800,3300,400,*,UP,NDIF +S 1000,8000,1000,8700,400,*,UP,ALU1 +S 1000,1100,1000,2000,400,*,UP,ALU1 +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 1000,3100,1000,6900,300,i,UP,CALU1 +S 2000,2100,2000,7900,300,nq,UP,CALU1 +V 1000,4000,CONT_POLY,* +V 2000,3000,CONT_DIF_N,* +V 2000,6000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,2000,CONT_DIF_N,* +V 1000,8000,CONT_DIF_P,* +V 1000,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/inv_x2.vbe b/pdks/symbolic/nsxlib/cells/inv_x2.vbe new file mode 100644 index 000000000..9df0116d3 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/inv_x2.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 12; + CONSTANT rdown_i_nq : NATURAL := 1620; + CONSTANT rup_i_nq : NATURAL := 2420; + CONSTANT tphl_i_nq : NATURAL := 69; + CONSTANT tplh_i_nq : NATURAL := 163; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x2; + +ARCHITECTURE behaviour_data_flow OF inv_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x2" + SEVERITY WARNING; + nq <= not (i) after 800 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/inv_x4.ap b/pdks/symbolic/nsxlib/cells/inv_x4.ap new file mode 100644 index 000000000..e8765ee4c --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/inv_x4.ap @@ -0,0 +1,53 @@ +V ALLIANCE : 6 +H inv_x4,P,26/ 9/2019,100 +A 0,0,4000,10000 +R 1000,6000,ref_ref,i_30 +R 1000,5000,ref_ref,i_25 +R 1000,4000,ref_ref,i_20 +R 1000,3000,ref_ref,i_15 +R 1000,2000,ref_ref,i_10 +R 2000,4000,ref_ref,nq_20 +R 2000,3000,ref_ref,nq_15 +R 2000,2000,ref_ref,nq_10 +R 2000,7000,ref_ref,nq_35 +R 2000,6000,ref_ref,nq_30 +R 2000,5000,ref_ref,nq_25 +R 1000,7000,ref_ref,i_35 +R 1000,8000,ref_ref,i_40 +R 2000,8000,ref_ref,nq_40 +S 1300,3800,1300,4200,300,*,DOWN,POLY +S 1400,3000,2600,3000,400,*,RIGHT,POLY +S 2000,2100,2000,7900,300,nq,UP,CALU1 +S 1000,2100,1000,7900,300,i,UP,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 800,800,800,2300,400,*,UP,NDIF +S 1400,600,1400,2500,200,*,UP,NTRANS +S 2000,800,2000,2300,600,*,UP,NDIF +S 2600,600,2600,2500,200,*,UP,NTRANS +S 3200,800,3200,2300,600,*,UP,NDIF +S 3200,7100,3200,8900,300,*,UP,ALU1 +S 3200,1100,3200,1900,300,*,UP,ALU1 +S 800,5700,800,9300,400,*,UP,PDIF +S 2600,5500,2600,9500,200,*,UP,PTRANS +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 1000,2100,1000,7900,300,*,UP,ALU1 +S 1400,2800,1400,5200,200,*,UP,POLY +S 1400,5500,1400,9500,200,*,UP,PTRANS +S 2000,5700,2000,9300,600,*,UP,PDIF +S 2600,2800,2600,6400,200,*,UP,POLY +S 3200,6900,3200,9300,600,*,UP,PDIF +S -300,7800,4300,7800,6000,*,RIGHT,NWELL +V 1000,4000,CONT_POLY,* +V 3200,9200,CONT_DIF_P,* +V 1000,9200,CONT_DIF_P,* +V 3200,900,CONT_DIF_N,* +V 2000,6000,CONT_DIF_P,* +V 3200,7000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 3200,8000,CONT_DIF_P,* +V 1000,900,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 3200,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/inv_x4.vbe b/pdks/symbolic/nsxlib/cells/inv_x4.vbe new file mode 100644 index 000000000..3091ae3f7 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/inv_x4.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 26; + CONSTANT rdown_i_nq : NATURAL := 810; + CONSTANT rup_i_nq : NATURAL := 1060; + CONSTANT tphl_i_nq : NATURAL := 71; + CONSTANT tplh_i_nq : NATURAL := 143; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x4; + +ARCHITECTURE behaviour_data_flow OF inv_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x4" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/inv_x8.ap b/pdks/symbolic/nsxlib/cells/inv_x8.ap new file mode 100644 index 000000000..f647bdada --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/inv_x8.ap @@ -0,0 +1,85 @@ +V ALLIANCE : 6 +H inv_x8,P,26/ 9/2019,100 +A 0,0,7000,10000 +R 2000,8000,ref_ref,nq_40 +R 1000,2000,ref_ref,i_10 +R 1000,3000,ref_ref,i_15 +R 2000,5000,ref_ref,nq_25 +R 2000,6000,ref_ref,nq_30 +R 2000,7000,ref_ref,nq_35 +R 2000,2000,ref_ref,nq_10 +R 2000,3000,ref_ref,nq_15 +R 2000,4000,ref_ref,nq_20 +R 1000,8000,ref_ref,i_40 +R 1000,7000,ref_ref,i_35 +R 1000,6000,ref_ref,i_30 +R 1000,5000,ref_ref,i_25 +R 1000,4000,ref_ref,i_20 +S 1300,3800,1300,4200,300,*,DOWN,POLY +S 1500,3000,4900,3000,400,*,RIGHT,POLY +S 2000,2100,2000,7900,300,nq,UP,CALU1 +S 1000,2100,1000,7900,300,i,UP,CALU1 +S 6200,5500,6200,7100,600,*,UP,NTIE +S 6200,5900,6200,6700,300,*,UP,ALU1 +S 4900,2800,4900,5200,200,*,UP,POLY +S 4900,5500,4900,9500,200,*,UP,PTRANS +S 800,5700,800,9300,400,*,UP,PDIF +S -300,7800,7300,7800,6000,*,RIGHT,NWELL +S 3800,2800,3800,5200,200,*,UP,POLY +S 2600,2800,2600,5200,200,*,UP,POLY +S 1400,2800,1400,5200,200,*,UP,POLY +S 5600,800,5600,2300,600,*,UP,NDIF +S 4900,600,4900,2500,200,*,UP,NTRANS +S 3800,600,3800,2500,200,*,UP,NTRANS +S 4400,800,4400,2300,600,*,UP,NDIF +S 3200,800,3200,2300,600,*,UP,NDIF +S 2600,600,2600,2500,200,*,UP,NTRANS +S 1400,600,1400,2500,200,*,UP,NTRANS +S 2000,800,2000,2300,600,*,UP,NDIF +S 800,800,800,2300,400,*,UP,NDIF +S 2000,5700,2000,9300,600,*,UP,PDIF +S 1400,5500,1400,9500,200,*,UP,PTRANS +S 3200,5700,3200,9300,600,*,UP,PDIF +S 2600,5500,2600,9500,200,*,UP,PTRANS +S 4400,5700,4400,9300,600,*,UP,PDIF +S 3800,5500,3800,9500,200,*,UP,PTRANS +S 1000,2100,1000,7900,300,*,UP,ALU1 +S 3200,1100,3200,1900,300,*,UP,ALU1 +S 3200,6100,3200,8900,300,*,UP,ALU1 +S 5600,7900,5600,9300,600,*,UP,PDIF +S 4400,2100,4400,7900,300,*,UP,ALU1 +S 2100,4000,4300,4000,300,*,RIGHT,ALU1 +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 5600,1100,5600,3300,300,*,UP,ALU1 +S 5600,3400,6200,3400,300,*,RIGHT,ALU1 +S 5600,6900,5600,8900,300,*,UP,ALU1 +S 5700,6800,6200,6800,300,*,RIGHT,ALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 5300,3400,6000,3400,600,*,RIGHT,PTIE +V 1000,4000,CONT_POLY,* +V 3200,2000,CONT_DIF_N,* +V 5600,3400,CONT_BODY_P,* +V 5600,8000,CONT_DIF_P,* +V 5600,2000,CONT_DIF_N,* +V 4400,2000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 4400,6000,CONT_DIF_P,* +V 4400,7000,CONT_DIF_P,* +V 4400,8000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 3200,6000,CONT_DIF_P,* +V 3200,7000,CONT_DIF_P,* +V 3200,8000,CONT_DIF_P,* +V 2000,6000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 5600,9200,CONT_DIF_P,* +V 3200,9200,CONT_DIF_P,* +V 900,9200,CONT_DIF_P,* +V 6200,5800,CONT_BODY_N,* +V 6200,6800,CONT_BODY_N,* +V 6200,3400,CONT_BODY_P,* +V 900,900,CONT_DIF_N,* +V 3200,900,CONT_DIF_N,* +V 5600,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/inv_x8.vbe b/pdks/symbolic/nsxlib/cells/inv_x8.vbe new file mode 100644 index 000000000..4e6fa0639 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/inv_x8.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i : NATURAL := 54; + CONSTANT rdown_i_nq : NATURAL := 400; + CONSTANT rup_i_nq : NATURAL := 450; + CONSTANT tphl_i_nq : NATURAL := 86; + CONSTANT tplh_i_nq : NATURAL := 133; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x8; + +ARCHITECTURE behaviour_data_flow OF inv_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x8" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/mx2_x2.ap b/pdks/symbolic/nsxlib/cells/mx2_x2.ap new file mode 100644 index 000000000..fe34c3d11 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/mx2_x2.ap @@ -0,0 +1,119 @@ +V ALLIANCE : 6 +H mx2_x2,P,29/ 4/2024,100 +A 0,0,9000,10000 +R 6000,6000,ref_ref,i1_30 +R 6000,7000,ref_ref,i1_35 +R 6000,8000,ref_ref,i1_40 +R 2000,4000,ref_ref,i0_20 +R 2000,3000,ref_ref,i0_15 +R 8000,4000,ref_ref,q_20 +R 8000,3000,ref_ref,q_15 +R 8000,5000,ref_ref,q_25 +R 3000,8000,ref_ref,cmd_40 +R 3000,7000,ref_ref,cmd_35 +R 3000,6000,ref_ref,cmd_30 +R 3000,5000,ref_ref,cmd_25 +R 3000,4000,ref_ref,cmd_20 +R 3000,3000,ref_ref,cmd_15 +R 2000,5000,ref_ref,i0_25 +R 2000,6000,ref_ref,i0_30 +R 2000,7000,ref_ref,i0_35 +R 6000,2000,ref_ref,i1_10 +R 6000,3000,ref_ref,i1_15 +R 6000,4000,ref_ref,i1_20 +R 6000,5000,ref_ref,i1_25 +S 1400,2300,1500,2300,200,*,RIGHT,POLY +S 1400,2400,1400,6200,200,*,UP,POLY +S 1500,1600,1500,2200,200,*,UP,POLY +S 5600,6200,5600,6400,200,*,UP,POLY +S 5600,6200,6100,6200,200,*,RIGHT,POLY +S 800,800,800,2000,400,*,UP,NDIF +S 2400,6300,2400,6500,200,*,UP,POLY +S 1900,6200,2400,6200,200,*,RIGHT,POLY +S 1900,2800,2400,2800,200,*,RIGHT,POLY +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 4800,1800,4800,4000,200,*,UP,POLY +S -300,7800,9300,7800,6000,*,RIGHT,NWELL +S 5000,2100,5000,5300,300,*,UP,ALU1 +S 7000,6100,7000,8900,300,*,UP,ALU1 +S 5600,6500,5600,8500,200,*,UP,PTRANS +S 4000,3100,4000,7900,300,*,UP,ALU1 +S 700,2000,4900,2000,300,*,RIGHT,ALU1 +S 7000,1100,7000,1900,300,*,UP,ALU1 +S 2000,800,2000,1300,400,*,UP,NDIF +S 2400,600,2400,1500,200,*,UP,NTRANS +S 3300,600,3300,1500,200,*,UP,NTRANS +S 4000,800,4000,1300,1000,*,UP,NDIF +S 4000,800,4000,3100,400,*,UP,NDIF +S 4800,600,4800,1500,200,*,UP,NTRANS +S 5700,600,5700,1500,200,*,UP,NTRANS +S 4400,6100,4400,6300,200,*,UP,POLY +S 4000,6700,4000,8300,400,*,UP,PDIF +S 8200,800,8200,2300,400,*,UP,NDIF +S 7600,600,7600,2500,200,*,UP,NTRANS +S 1500,600,1500,1500,200,*,UP,NTRANS +S 5700,2900,6100,2900,200,*,RIGHT,POLY +S 3300,1600,3300,1900,200,*,UP,POLY +S 2400,1700,2400,2800,200,*,UP,POLY +S 3600,6100,3600,6300,200,*,UP,POLY +S 3200,4000,3200,6100,200,*,UP,POLY +S 4700,5300,4700,6100,200,*,UP,POLY +S 4400,6100,4600,6100,200,*,RIGHT,POLY +S 4400,6500,4400,8500,200,*,UP,PTRANS +S 2400,6500,2400,8500,200,*,UP,PTRANS +S 3600,6500,3600,8500,200,*,UP,PTRANS +S 3300,6100,3600,6100,200,*,RIGHT,POLY +S 6000,2100,6000,7900,300,*,UP,ALU1 +S 7600,2800,7600,5200,200,*,UP,POLY +S 7600,5500,7600,9500,200,*,UP,PTRANS +S 7000,5700,7000,6500,600,*,UP,PDIF +S 8200,5700,8200,9300,400,*,UP,PDIF +S 5700,1800,5700,2800,200,*,UP,POLY +S 1400,4000,4800,4000,200,*,RIGHT,POLY +S 700,2100,700,7900,300,*,UP,ALU1 +S 700,6700,700,8300,400,*,UP,PDIF +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 1800,6700,1800,8300,300,*,UP,PDIF +S 2000,8000,2000,9000,400,*,UP,ALU1 +S 1400,6500,1400,8500,200,*,UP,PTRANS +S 6800,6700,6800,9300,600,*,UP,PDIF +S 6300,6700,6300,9300,400,*,UP,PDIF +S 6900,800,6900,2300,400,*,UP,NDIF +S 6500,800,6500,1300,600,*,UP,NDIF +S 3900,4600,7600,4600,200,*,RIGHT,POLY +S 5000,6700,5000,8300,200,*,UP,PDIF +S 3000,6700,3000,8300,200,*,UP,PDIF +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 3000,3100,3000,7900,300,cmd,UP,CALU1 +S 2000,3100,2000,6900,300,i0,UP,CALU1 +S 6000,2100,6000,7900,300,i1,UP,CALU1 +S 8000,2100,8000,8000,300,q,UP,CALU1 +S 8000,2100,8000,8000,300,*,UP,ALU1 +V 800,2200,CONT_DIF_N,* +V 2000,900,CONT_DIF_N,* +V 7000,9100,CONT_DIF_P,* +V 7000,900,CONT_DIF_N,* +V 2000,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 6000,3000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 2000,6000,CONT_POLY,* +V 6000,6000,CONT_POLY,* +V 4000,3000,CONT_DIF_N,* +V 4000,7000,CONT_DIF_P,* +V 5000,5400,CONT_POLY,* +V 7000,6000,CONT_DIF_P,* +V 7000,2000,CONT_DIF_N,* +V 7000,8000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 4000,4800,CONT_POLY,* +V 8000,2000,CONT_DIF_N,* +V 8000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 3200,2000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/mx2_x2.vbe b/pdks/symbolic/nsxlib/cells/mx2_x2.vbe new file mode 100644 index 000000000..401686e9e --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/mx2_x2.vbe @@ -0,0 +1,40 @@ +ENTITY mx2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_cmd_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 451; + CONSTANT tphh_i1_q : NATURAL := 451; + CONSTANT tpll_i0_q : NATURAL := 469; + CONSTANT tpll_i1_q : NATURAL := 469; + CONSTANT tphh_cmd_q : NATURAL := 484; + CONSTANT tphl_cmd_q : NATURAL := 485; + CONSTANT tpll_cmd_q : NATURAL := 522; + CONSTANT tplh_cmd_q : NATURAL := 534; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x2; + +ARCHITECTURE behaviour_data_flow OF mx2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x2" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/mx2_x4.ap b/pdks/symbolic/nsxlib/cells/mx2_x4.ap new file mode 100644 index 000000000..f8af05010 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/mx2_x4.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H mx2_x4,P,25/ 9/2019,100 +A 0,0,10000,10000 +R 6000,8000,ref_ref,i1_40 +R 6000,7000,ref_ref,i1_35 +R 6000,6000,ref_ref,i1_30 +R 6000,5000,ref_ref,i1_25 +R 6000,4000,ref_ref,i1_20 +R 6000,3000,ref_ref,i1_15 +R 6000,2000,ref_ref,i1_10 +R 2000,7000,ref_ref,i0_35 +R 2000,6000,ref_ref,i0_30 +R 2000,5000,ref_ref,i0_25 +R 3000,3000,ref_ref,cmd_15 +R 3000,4000,ref_ref,cmd_20 +R 3000,5000,ref_ref,cmd_25 +R 3000,6000,ref_ref,cmd_30 +R 3000,7000,ref_ref,cmd_35 +R 3000,8000,ref_ref,cmd_40 +R 8000,5000,ref_ref,q_25 +R 8000,3000,ref_ref,q_15 +R 8000,4000,ref_ref,q_20 +R 2000,3000,ref_ref,i0_15 +R 2000,4000,ref_ref,i0_20 +S 800,2000,4900,2000,300,*,RIGHT,ALU1 +S 700,800,700,2100,400,*,DOWN,NDIF +S 2400,6200,2400,6500,200,*,UP,POLY +S 1900,6200,2400,6200,200,*,RIGHT,POLY +S 5600,6200,5600,6500,200,*,UP,POLY +S 5600,6200,6100,6200,200,*,RIGHT,POLY +S 5600,2800,6100,2800,200,*,RIGHT,POLY +S 2000,3100,2000,6900,300,i0,UP,CALU1 +S 3000,3100,3000,7900,300,cmd,UP,CALU1 +S 6000,2100,6000,7900,300,i1,UP,CALU1 +S 8000,2100,8000,7900,300,q,UP,CALU1 +S 8000,2100,8000,7900,300,*,UP,ALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 3300,1600,3300,1800,200,*,UP,POLY +S 1400,1700,1400,6200,200,*,UP,POLY +S 2400,1600,2400,2800,200,*,UP,POLY +S 4700,5300,4700,6200,200,*,UP,POLY +S 6200,6700,6200,8300,200,*,UP,PDIF +S 6700,6700,6700,9300,800,*,UP,PDIF +S 6200,800,6200,1300,200,*,UP,NDIF +S 6700,800,6700,2300,800,*,UP,NDIF +S 3900,4600,8500,4600,200,*,RIGHT,POLY +S 1900,2800,2400,2800,200,*,RIGHT,POLY +S 1400,6500,1400,8500,200,*,UP,PTRANS +S 2000,8000,2000,8800,400,*,UP,ALU1 +S 1800,6700,1800,8300,600,*,UP,PDIF +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 3300,4000,3300,6200,200,*,UP,POLY +S 3300,6500,3300,8500,200,*,UP,PTRANS +S 4700,6500,4700,8500,200,*,UP,PTRANS +S 2400,6500,2400,8500,200,*,UP,PTRANS +S -300,7800,10300,7800,6000,*,RIGHT,NWELL +S 7000,5700,7000,6500,600,*,UP,PDIF +S 7600,5500,7600,9500,200,*,UP,PTRANS +S 7600,2800,7600,5200,200,*,UP,POLY +S 1400,600,1400,1500,200,*,UP,NTRANS +S 2400,600,2400,1500,200,*,UP,NTRANS +S 1800,800,1800,1300,600,*,UP,NDIF +S 3300,600,3300,1500,200,*,UP,NTRANS +S 4000,800,4000,3100,300,*,UP,NDIF +S 9200,800,9200,2300,400,*,UP,NDIF +S 8500,600,8500,2500,200,*,UP,NTRANS +S 8200,800,8200,2300,400,*,UP,NDIF +S 7600,600,7600,2500,200,*,UP,NTRANS +S 5600,600,5600,1500,200,*,UP,NTRANS +S 4700,600,4700,1500,200,*,UP,NTRANS +S 4000,3100,4000,7900,300,*,UP,ALU1 +S 5600,6500,5600,8500,200,*,UP,PTRANS +S 7000,6100,7000,8900,300,*,UP,ALU1 +S 5000,2100,5000,5300,300,*,UP,ALU1 +S 5600,1800,5600,2800,200,*,UP,POLY +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 6000,2100,6000,7900,300,*,UP,ALU1 +S 7000,1100,7000,1900,300,*,UP,ALU1 +S 4000,800,4000,1300,1000,*,UP,NDIF +S 8500,2800,8500,5200,200,*,UP,POLY +S 8500,5500,8500,9500,200,*,UP,PTRANS +S 8200,5700,8200,9300,400,*,UP,PDIF +S 8900,1100,8900,1900,300,*,UP,ALU1 +S 8900,6100,8900,8900,300,*,UP,ALU1 +S 9200,5700,9200,9300,400,*,UP,PDIF +S 4700,1800,4700,4000,200,*,UP,POLY +S 1400,4000,4700,4000,200,*,RIGHT,POLY +S 800,2100,800,7900,300,*,UP,ALU1 +S 700,6700,700,8300,400,*,UP,PDIF +S 4000,6700,4000,8300,1000,*,UP,PDIF +V 700,2300,CONT_DIF_N,* +V 8000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 3200,2000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 4000,4800,CONT_POLY,* +V 5000,5400,CONT_POLY,* +V 7000,6000,CONT_DIF_P,* +V 7000,2000,CONT_DIF_N,* +V 7000,8000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,3000,CONT_DIF_N,* +V 6000,6000,CONT_POLY,* +V 2000,6000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 6000,3000,CONT_POLY,* +V 1900,900,CONT_DIF_N,* +V 8000,2000,CONT_DIF_N,* +V 8900,2000,CONT_DIF_N,* +V 8900,6000,CONT_DIF_P,* +V 8900,7000,CONT_DIF_P,* +V 8900,8000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 7000,9100,CONT_DIF_P,* +V 8900,1000,CONT_DIF_N,* +V 7000,1000,CONT_DIF_N,* +V 8900,9100,CONT_DIF_P,* +V 900,8000,CONT_DIF_P,* +V 900,7000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/mx2_x4.vbe b/pdks/symbolic/nsxlib/cells/mx2_x4.vbe new file mode 100644 index 000000000..ddb1f3ca7 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/mx2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY mx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 564; + CONSTANT tphh_i1_q : NATURAL := 564; + CONSTANT tphl_cmd_q : NATURAL := 574; + CONSTANT tpll_i0_q : NATURAL := 576; + CONSTANT tpll_i1_q : NATURAL := 576; + CONSTANT tphh_cmd_q : NATURAL := 615; + CONSTANT tplh_cmd_q : NATURAL := 631; + CONSTANT tpll_cmd_q : NATURAL := 647; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x4; + +ARCHITECTURE behaviour_data_flow OF mx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x4" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/mx3_x2.ap b/pdks/symbolic/nsxlib/cells/mx3_x2.ap new file mode 100644 index 000000000..cb3890355 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/mx3_x2.ap @@ -0,0 +1,168 @@ +V ALLIANCE : 6 +H mx3_x2,P,18/ 9/2019,100 +A 0,0,13000,10000 +R 1000,7000,ref_ref,cmd1_35 +R 1000,6000,ref_ref,cmd1_30 +R 1000,5000,ref_ref,cmd1_25 +R 1000,4000,ref_ref,cmd1_20 +R 1000,3000,ref_ref,cmd1_15 +R 8000,6000,ref_ref,i0_30 +R 9000,5000,ref_ref,i0_25 +R 12000,5000,ref_ref,q_25 +R 7000,5000,ref_ref,cmd0_25 +R 7000,6000,ref_ref,cmd0_30 +R 8000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i2_25 +R 5000,5000,ref_ref,i1_25 +R 7000,4000,ref_ref,cmd0_20 +S 1000,3100,1000,7000,300,cmd1,UP,CALU1 +S 7000,4100,7000,5900,300,cmd0,UP,CALU1 +S 9000,4100,9000,5900,300,*,UP,ALU1 +S 9000,4000,9000,6000,300,i0,UP,CALU1 +S 8100,4000,8100,4000,300,i0,LEFT,CALU1 +S 8000,6000,8000,6000,300,i0,LEFT,CALU1 +S 5000,5000,5000,5000,300,i1,LEFT,CALU1 +S 3000,5000,3000,5000,300,i2,LEFT,CALU1 +S 12000,2000,12000,3000,300,q,UP,CALU1 +S 12000,6000,12000,8000,300,q,UP,CALU1 +S 0,9400,13000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,13000,600,1200,vss,RIGHT,CALU1 +S 8000,6600,8000,7000,200,*,UP,POLY +S 5300,5900,5300,7200,200,*,UP,POLY +S 8000,7100,8300,7100,200,*,RIGHT,POLY +S 7000,7100,7200,7100,200,*,RIGHT,POLY +S 7300,2300,7600,2300,200,*,RIGHT,POLY +S 11000,4000,11600,4000,200,*,RIGHT,POLY +S 7800,800,7800,1500,400,*,UP,ALU1 +S 11600,3800,11600,5200,200,*,UP,POLY +S 4600,7100,4600,9300,600,*,UP,PDIF +S 12200,1700,12200,3300,400,*,UP,NDIF +S 12200,5700,12200,9300,400,*,UP,PDIF +S 6100,7500,6100,9500,200,*,UP,PTRANS +S 6600,7700,6600,9300,400,*,UP,PDIF +S 9800,7700,9800,9300,600,*,UP,PDIF +S 7200,7500,7200,9500,200,*,UP,PTRANS +S 7800,7700,7800,9300,400,*,UP,PDIF +S 1000,900,1000,1900,300,*,UP,ALU1 +S 1100,7000,3500,7000,300,*,RIGHT,ALU1 +S 8200,2200,8200,3100,200,*,UP,POLY +S 11000,5700,11000,9300,600,*,UP,PDIF +S 4700,3000,5500,3000,300,*,RIGHT,ALU1 +S 2300,6000,4900,6000,300,*,RIGHT,ALU1 +S 4100,5000,4900,5000,300,*,RIGHT,ALU1 +S 3000,4300,3000,4900,300,*,UP,ALU1 +S 2300,3000,3500,3000,300,*,RIGHT,ALU1 +S 1000,1900,1000,3500,600,*,UP,NDIF +S 2200,3100,2200,3500,600,*,UP,NDIF +S 7000,4100,7000,5900,300,*,UP,ALU1 +S 8100,4000,8700,4000,300,*,RIGHT,ALU1 +S 8100,6000,8700,6000,300,*,RIGHT,ALU1 +S 1000,8100,1000,9100,300,*,UP,ALU1 +S 5600,3100,5600,3900,300,*,UP,ALU1 +S 5700,4000,5900,4000,300,*,RIGHT,ALU1 +S 6000,4100,6000,6900,300,*,UP,ALU1 +S 4700,7000,10900,7000,300,*,RIGHT,ALU1 +S 6900,3000,9900,3000,300,*,RIGHT,ALU1 +S 10000,3100,10000,5900,300,*,UP,ALU1 +S 9800,7100,9800,7900,300,*,UP,ALU1 +S 11000,2100,11000,6900,300,*,UP,ALU1 +S 6700,3000,6800,3000,200,*,RIGHT,POLY +S 10200,5500,10200,6900,200,*,UP,PTRANS +S 8000,5000,10200,5000,200,*,RIGHT,POLY +S 8300,7500,8300,9500,200,*,UP,PTRANS +S 7300,700,7300,1900,200,*,UP,NTRANS +S 8200,700,8200,1900,200,*,UP,NTRANS +S 9100,700,9100,1900,200,*,UP,NTRANS +S 9100,2200,9100,4000,200,*,UP,POLY +S 2300,2000,6400,2000,300,*,RIGHT,ALU1 +S 6600,1300,6600,2100,400,*,UP,NDIF +S 6100,1100,6100,2300,200,*,UP,NTRANS +S 6100,2600,6100,7200,200,*,UP,POLY +S 7300,2000,7300,2300,200,*,UP,POLY +S 7200,7100,7200,7300,200,*,UP,POLY +S 8300,7100,8300,7400,200,*,UP,POLY +S 9100,7500,9100,9500,200,*,UP,PTRANS +S 9100,5900,9100,7300,200,*,UP,POLY +S 9800,900,9800,2000,400,*,UP,NDIF +S 3800,1100,3800,2300,200,*,UP,NTRANS +S 3800,2600,3800,3000,200,*,UP,POLY +S 4500,1300,4500,3000,400,*,UP,NDIF +S 3800,7500,3800,9500,200,*,UP,PTRANS +S 2900,1100,2900,2300,200,*,UP,NTRANS +S 2900,2600,2900,7200,200,*,UP,POLY +S 2900,7500,2900,9500,200,*,UP,PTRANS +S 2600,8000,6500,8000,300,*,RIGHT,ALU1 +S 2400,7700,2400,9300,400,*,UP,PDIF +S 1800,5500,1800,6900,200,*,UP,PTRANS +S 2200,5700,2200,6700,400,*,UP,PDIF +S 1800,4000,1800,5200,200,*,UP,POLY +S 1800,2900,1800,3700,200,*,UP,NTRANS +S 11100,8000,11100,9000,400,*,UP,ALU1 +S 7800,8000,7800,9000,400,*,UP,ALU1 +S 2100,3300,2100,5900,300,*,UP,ALU1 +S 9900,2000,11000,2000,300,*,RIGHT,ALU1 +S 12000,3200,12000,7900,300,*,UP,ALU1 +S 1000,5000,1600,5000,400,*,RIGHT,POLY +S 3400,3000,3800,3000,400,*,RIGHT,POLY +S 3800,7100,3800,7300,200,*,UP,POLY +S 12000,2000,12000,3000,300,*,UP,ALU1 +S 7000,2900,7000,7000,200,*,UP,POLY +S 7600,2400,7600,3800,200,*,UP,POLY +S 3800,4000,3800,7000,200,*,UP,POLY +S 5300,7500,5300,9500,200,*,UP,PTRANS +S 3400,7700,3400,9300,400,*,UP,PDIF +S 1000,5700,1000,7900,600,*,UP,PDIF +S 4000,4000,5200,4000,200,*,RIGHT,POLY +S 5000,5000,6000,5000,200,*,RIGHT,POLY +S 8000,3800,8000,6600,200,*,UP,POLY +S 7600,3800,8000,3800,200,*,RIGHT,POLY +S 11600,5500,11600,9500,200,*,UP,PTRANS +S -300,7800,13300,7800,6000,*,RIGHT,NWELL +S 7100,5000,7700,5000,300,*,RIGHT,ALU1 +S 9800,5700,9800,6700,600,*,UP,PDIF +S 5200,2600,5200,4000,200,*,UP,POLY +S 7800,900,7800,1700,400,*,UP,NDIF +S 5200,1100,5200,2300,200,*,UP,NTRANS +S 3400,1300,3400,2100,400,*,UP,NDIF +S 2200,1300,2200,1900,600,*,UP,NDIF +S 9800,3100,9800,3300,600,*,UP,NDIF +S 11600,1500,11600,3500,200,*,UP,NTRANS +S 10200,3800,10200,5200,200,*,UP,POLY +S 10200,2900,10200,3500,200,*,UP,NTRANS +S 10900,1100,10900,3300,400,*,UP,NDIF +V 5000,6000,CONT_POLY,* +V 12000,8000,CONT_DIF_P,* +V 12000,7000,CONT_DIF_P,* +V 12000,6000,CONT_DIF_P,* +V 12000,3000,CONT_DIF_N,* +V 12000,2000,CONT_DIF_N,* +V 7800,1500,CONT_DIF_N,* +V 9900,2000,CONT_DIF_N,* +V 6500,2000,CONT_DIF_N,* +V 2500,8000,CONT_DIF_P,* +V 11100,8000,CONT_DIF_P,* +V 7800,8000,CONT_DIF_P,* +V 10900,800,CONT_DIF_N,* +V 4500,3000,CONT_DIF_N,* +V 8000,5000,CONT_POLY,* +V 8900,6000,CONT_POLY,* +V 9000,4100,CONT_POLY,* +V 11000,4000,CONT_POLY,* +V 2200,3200,CONT_DIF_N,* +V 9800,3200,CONT_DIF_N,* +V 3600,7000,CONT_POLY,* +V 8400,3000,CONT_POLY,* +V 6800,3000,CONT_POLY,* +V 3600,3000,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 2200,2000,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 6600,8000,CONT_DIF_P,* +V 4600,7000,CONT_DIF_P,* +V 9800,8000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 2200,6000,CONT_DIF_P,* +V 9800,6000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/mx3_x2.vbe b/pdks/symbolic/nsxlib/cells/mx3_x2.vbe new file mode 100644 index 000000000..ddc531ad5 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/mx3_x2.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 1620; + CONSTANT rdown_cmd1_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_cmd0_q : NATURAL := 1790; + CONSTANT rup_cmd1_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 538; + CONSTANT tphh_cmd0_q : NATURAL := 573; + CONSTANT tphh_i1_q : NATURAL := 654; + CONSTANT tphh_i2_q : NATURAL := 654; + CONSTANT tpll_i0_q : NATURAL := 658; + CONSTANT tphh_cmd1_q : NATURAL := 664; + CONSTANT tpll_cmd0_q : NATURAL := 680; + CONSTANT tplh_cmd1_q : NATURAL := 738; + CONSTANT tphl_cmd1_q : NATURAL := 739; + CONSTANT tplh_cmd0_q : NATURAL := 768; + CONSTANT tphl_cmd0_q : NATURAL := 792; + CONSTANT tpll_i1_q : NATURAL := 808; + CONSTANT tpll_i2_q : NATURAL := 808; + CONSTANT tpll_cmd1_q : NATURAL := 817; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x2; + +ARCHITECTURE behaviour_data_flow OF mx3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx3_x2" + SEVERITY WARNING; + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) + and i2)))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/mx3_x4.ap b/pdks/symbolic/nsxlib/cells/mx3_x4.ap new file mode 100644 index 000000000..70a34edff --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/mx3_x4.ap @@ -0,0 +1,199 @@ +V ALLIANCE : 6 +H mx3_x4,P,26/ 9/2019,100 +A 0,0,14000,10000 +R 12000,6000,ref_ref,q_30 +R 12000,7000,ref_ref,q_35 +R 12000,8000,ref_ref,q_40 +R 1000,6000,ref_ref,cmd1_30 +R 1000,7000,ref_ref,cmd1_35 +R 3000,5000,ref_ref,i2_25 +R 5000,5000,ref_ref,i1_25 +R 7000,4000,ref_ref,cmd0_20 +R 7000,5000,ref_ref,cmd0_25 +R 7000,6000,ref_ref,cmd0_30 +R 8000,4000,ref_ref,i0_20 +R 12000,5000,ref_ref,q_25 +R 12000,3000,ref_ref,q_15 +R 12000,2000,ref_ref,q_10 +R 9000,5000,ref_ref,i0_25 +R 8000,6000,ref_ref,i0_30 +R 13000,4000,ref_ref,q_20 +R 1000,3000,ref_ref,cmd1_15 +R 1000,4000,ref_ref,cmd1_20 +S 2700,4800,2700,5200,300,*,DOWN,POLY +S 1000,3100,1000,7000,300,*,UP,ALU1 +S 1000,3100,1000,7000,300,cmd1,UP,CALU1 +S 7000,4000,7000,5900,300,cmd0,UP,CALU1 +S 12000,2100,12000,3000,300,*,UP,ALU1 +S 12000,2100,12000,3000,300,q,UP,CALU1 +S 9000,5000,9000,5000,300,i0,LEFT,CALU1 +S 8000,4000,8000,4000,300,i0,LEFT,CALU1 +S 8000,6000,8000,6000,300,i0,LEFT,CALU1 +S 5000,5000,5000,5000,300,i1,LEFT,CALU1 +S 3000,5000,3000,5000,300,i2,LEFT,CALU1 +S 13000,4000,13000,4000,300,q,LEFT,CALU1 +S 12000,5000,12000,8000,300,q,UP,CALU1 +S 0,9400,14000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,14000,600,1200,vss,RIGHT,CALU1 +S 7200,2000,7200,2300,200,*,UP,POLY +S 6000,7100,6000,7300,200,*,UP,POLY +S 7000,7100,7000,7400,200,*,UP,POLY +S 8200,7100,8200,7400,200,*,UP,POLY +S 7800,6600,7800,7000,200,*,UP,POLY +S 6800,2900,6800,7000,200,*,UP,POLY +S 5800,2600,5800,7000,200,*,UP,POLY +S 7400,2400,7400,3800,200,*,UP,POLY +S 5800,7100,6000,7100,200,*,RIGHT,POLY +S 6800,7100,7000,7100,200,*,RIGHT,POLY +S 7800,7100,8200,7100,200,*,RIGHT,POLY +S 7200,2300,7400,2300,200,*,RIGHT,POLY +S 4900,5000,5800,5000,400,*,RIGHT,POLY +S 11200,4000,12600,4000,400,*,RIGHT,POLY +S 4900,2600,4900,3900,200,*,UP,POLY +S 3700,4000,4900,4000,200,*,RIGHT,POLY +S 3400,7000,3500,7000,400,*,RIGHT,POLY +S 3600,4000,3600,7200,200,*,UP,POLY +S 2600,5000,3000,5000,400,*,RIGHT,POLY +S 3300,3000,3500,3000,400,*,RIGHT,POLY +S 800,5000,1400,5000,400,*,RIGHT,POLY +S 4300,7100,4300,9300,600,*,UP,PDIF +S 5000,5900,5000,7200,200,*,UP,POLY +S 6500,3000,6600,3000,200,*,RIGHT,POLY +S 11700,700,12900,700,600,*,RIGHT,PTIE +S -300,7800,14300,7800,6000,*,RIGHT,NWELL +S 12200,3000,12200,5000,300,*,UP,ALU1 +S 12000,5000,12200,5000,300,*,RIGHT,ALU1 +S 12000,5000,12000,7900,300,*,UP,ALU1 +S 800,8100,800,9100,300,*,UP,ALU1 +S 800,900,800,1900,300,*,UP,ALU1 +S 2600,2600,2600,7200,200,*,UP,POLY +S 7800,3800,7800,6600,200,*,UP,POLY +S 4500,7000,10900,7000,300,*,RIGHT,ALU1 +S 5500,4000,5900,4000,300,*,RIGHT,ALU1 +S 6000,4100,6000,6900,300,*,UP,ALU1 +S 9600,7100,9600,7900,300,*,UP,ALU1 +S 8600,4100,8600,5900,300,*,UP,ALU1 +S 11000,2100,11000,6900,300,*,UP,ALU1 +S 9700,2000,10900,2000,300,*,RIGHT,ALU1 +S 2100,2000,6300,2000,300,*,RIGHT,ALU1 +S 13200,5700,13200,9300,400,*,UP,PDIF +S 13200,1700,13200,3300,400,*,UP,NDIF +S 13000,700,13000,2900,300,*,UP,ALU1 +S 13000,6100,13000,9100,400,*,UP,ALU1 +S 11600,1500,11600,3500,200,*,UP,NTRANS +S 12000,1700,12000,3300,400,*,UP,NDIF +S 11600,5500,11600,9500,200,*,UP,PTRANS +S 12000,5700,12000,9300,400,*,UP,PDIF +S 11600,3800,11600,5200,200,*,UP,POLY +S 10900,5700,10900,9300,400,*,UP,PDIF +S 10900,1100,10900,3300,400,*,UP,NDIF +S 9700,5700,9700,6700,400,*,UP,PDIF +S 9100,7500,9100,9500,200,*,UP,PTRANS +S 6700,3000,9700,3000,300,*,RIGHT,ALU1 +S 5400,3100,5400,3900,300,*,UP,ALU1 +S 4500,3000,5300,3000,300,*,RIGHT,ALU1 +S 2100,8000,6300,8000,300,*,RIGHT,ALU1 +S 1100,7000,3300,7000,300,*,RIGHT,ALU1 +S 2100,6000,4700,6000,300,*,RIGHT,ALU1 +S 2000,3300,2000,5900,300,*,UP,ALU1 +S 4100,5000,4900,5000,300,*,RIGHT,ALU1 +S 3000,4300,3000,4900,300,*,UP,ALU1 +S 2100,3000,3300,3000,300,*,RIGHT,ALU1 +S 800,1900,800,3500,600,*,UP,NDIF +S 2000,3100,2000,3500,600,*,UP,NDIF +S 10200,3800,10200,5200,200,*,UP,POLY +S 10200,2900,10200,3500,200,*,UP,NTRANS +S 12300,4000,12900,4000,300,*,RIGHT,ALU1 +S 11100,4000,11100,4000,300,*,LEFT,ALU1 +S 8700,5000,8900,5000,300,*,RIGHT,ALU1 +S 8100,4000,8500,4000,300,*,RIGHT,ALU1 +S 800,5700,800,7900,600,*,UP,PDIF +S 7000,4100,7000,5900,300,*,UP,ALU1 +S 8100,6000,8500,6000,300,*,RIGHT,ALU1 +S 12600,5500,12600,9500,200,*,UP,PTRANS +S 5000,7500,5000,9500,200,*,UP,PTRANS +S 7600,7700,7600,9300,400,*,UP,PDIF +S 7000,7500,7000,9500,200,*,UP,PTRANS +S 8200,7500,8200,9500,200,*,UP,PTRANS +S 9600,7700,9600,9300,600,*,UP,PDIF +S 6400,7700,6400,9300,400,*,UP,PDIF +S 2000,7700,2000,9300,600,*,UP,PDIF +S 2600,7500,2600,9500,200,*,UP,PTRANS +S 3200,7700,3200,9300,400,*,UP,PDIF +S 10200,5500,10200,6900,200,*,UP,PTRANS +S 2000,5700,2000,6700,600,*,UP,PDIF +S 12600,1500,12600,3500,200,*,UP,NTRANS +S 9000,700,9000,1900,200,*,UP,NTRANS +S 7600,900,7600,1700,400,*,UP,NDIF +S 2600,1100,2600,2300,200,*,UP,NTRANS +S 3200,1300,3200,2100,400,*,UP,NDIF +S 8100,700,8100,1900,200,*,UP,NTRANS +S 1600,4000,1600,5200,200,*,UP,POLY +S 1600,5500,1600,6900,200,*,UP,PTRANS +S 3600,7500,3600,9500,200,*,UP,PTRANS +S 6000,7500,6000,9500,200,*,UP,PTRANS +S 4200,1300,4200,3100,400,*,UP,NDIF +S 4900,1100,4900,2300,200,*,UP,NTRANS +S 3500,2600,3500,3000,200,*,UP,POLY +S 7800,5000,10200,5000,200,*,RIGHT,POLY +S 7400,3800,7800,3800,200,*,RIGHT,POLY +S 12600,3800,12600,5200,200,*,UP,POLY +S 8100,2200,8100,3000,200,*,UP,POLY +S 7700,1300,7700,1600,400,*,UP,ALU1 +S 7200,700,7200,1900,200,*,UP,NTRANS +S 6500,900,6500,2100,400,*,UP,NDIF +S 5800,1100,5800,2300,200,*,UP,NTRANS +S 3500,1100,3500,2300,200,*,UP,NTRANS +S 11100,8000,11100,8800,400,*,UP,ALU1 +S 9700,900,9700,2000,400,*,UP,NDIF +S 1600,2900,1600,3700,200,*,UP,NTRANS +S 9000,2000,9000,3800,200,*,UP,POLY +S 8700,3800,9000,3800,200,*,RIGHT,POLY +S 7100,5000,7700,5000,600,*,RIGHT,ALU1 +S 2000,1300,2000,2100,400,*,UP,NDIF +S 9800,3100,9800,6000,300,*,UP,ALU1 +S 9100,6200,9100,7300,200,*,UP,POLY +S 8600,6200,9000,6200,200,*,RIGHT,POLY +V 3000,5000,CONT_POLY,* +V 4800,6000,CONT_POLY,* +V 12000,3000,CONT_DIF_N,* +V 12000,2000,CONT_DIF_N,* +V 6400,2000,CONT_DIF_N,* +V 8600,6000,CONT_POLY,* +V 8600,4000,CONT_POLY,* +V 7600,5000,CONT_POLY,* +V 3400,7000,CONT_POLY,* +V 8200,3000,CONT_POLY,* +V 6600,3000,CONT_POLY,* +V 800,2000,CONT_DIF_N,* +V 2000,6000,CONT_DIF_P,* +V 12000,6000,CONT_DIF_P,* +V 12000,8000,CONT_DIF_P,* +V 12000,7000,CONT_DIF_P,* +V 9600,8000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 6400,8000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 5000,5000,CONT_POLY,* +V 2000,3200,CONT_DIF_N,* +V 13000,2000,CONT_DIF_N,* +V 13000,3000,CONT_DIF_N,* +V 13000,6000,CONT_DIF_P,* +V 13000,7000,CONT_DIF_P,* +V 12000,700,CONT_BODY_P,* +V 10900,800,CONT_DIF_N,* +V 11000,4000,CONT_POLY,* +V 13000,8000,CONT_DIF_P,* +V 13000,9200,CONT_DIF_P,* +V 9800,6000,CONT_DIF_P,* +V 9800,3200,CONT_DIF_N,* +V 9800,2000,CONT_DIF_N,* +V 7700,1600,CONT_DIF_N,* +V 4200,3000,CONT_DIF_N,* +V 2200,2000,CONT_DIF_N,* +V 4300,7000,CONT_DIF_P,* +V 1000,5000,CONT_POLY,* +V 7600,9200,CONT_DIF_P,* +V 3300,3000,CONT_POLY,* +V 11100,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/mx3_x4.vbe b/pdks/symbolic/nsxlib/cells/mx3_x4.vbe new file mode 100644 index 000000000..77baa4489 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/mx3_x4.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 810; + CONSTANT rdown_cmd1_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_cmd0_q : NATURAL := 890; + CONSTANT rup_cmd1_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 640; + CONSTANT tphh_cmd0_q : NATURAL := 683; + CONSTANT tphh_i1_q : NATURAL := 770; + CONSTANT tphh_i2_q : NATURAL := 770; + CONSTANT tpll_i0_q : NATURAL := 774; + CONSTANT tpll_cmd0_q : NATURAL := 779; + CONSTANT tphh_cmd1_q : NATURAL := 792; + CONSTANT tplh_cmd0_q : NATURAL := 844; + CONSTANT tplh_cmd1_q : NATURAL := 846; + CONSTANT tphl_cmd1_q : NATURAL := 872; + CONSTANT tphl_cmd0_q : NATURAL := 922; + CONSTANT tpll_i1_q : NATURAL := 948; + CONSTANT tpll_i2_q : NATURAL := 948; + CONSTANT tpll_cmd1_q : NATURAL := 967; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x4; + +ARCHITECTURE behaviour_data_flow OF mx3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx3_x4" + SEVERITY WARNING; + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) + and i2)))) after 1600 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/na2_x1.ap b/pdks/symbolic/nsxlib/cells/na2_x1.ap new file mode 100644 index 000000000..b746e87eb --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na2_x1.ap @@ -0,0 +1,60 @@ +V ALLIANCE : 6 +H na2_x1,P,26/ 9/2019,100 +A 0,0,4000,10000 +R 1000,3000,ref_ref,i0_15 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 1000,7000,ref_ref,i0_35 +R 2000,7000,ref_ref,nq_35 +R 2000,8000,ref_ref,nq_40 +R 3000,7000,ref_ref,i1_35 +R 3000,6000,ref_ref,i1_30 +R 3000,5000,ref_ref,i1_25 +R 3000,4000,ref_ref,i1_20 +R 3000,3000,ref_ref,i1_15 +R 2000,2000,ref_ref,nq_10 +R 2000,3000,ref_ref,nq_15 +R 2000,4000,ref_ref,nq_20 +R 2000,5000,ref_ref,nq_25 +R 2000,6000,ref_ref,nq_30 +S 1300,4800,1300,5200,300,*,DOWN,POLY +S 1000,5000,1400,5000,200,*,RIGHT,POLY +S 2000,2000,2000,7900,300,nq,UP,CALU1 +S 3000,3100,3000,6900,300,i1,UP,CALU1 +S 1000,3100,1000,6900,300,i0,UP,CALU1 +S 2600,6500,2600,8500,200,*,UP,PTRANS +S 2000,6700,2000,8300,600,*,UP,PDIF +S 1400,6500,1400,8500,200,*,UP,PTRANS +S 800,6700,800,8300,400,*,UP,PDIF +S 800,1700,800,3300,400,*,UP,NDIF +S 3200,6700,3200,8300,400,*,UP,PDIF +S 2600,4000,2600,6200,200,*,UP,POLY +S 2300,3900,3000,3900,200,*,RIGHT,POLY +S 2300,3700,2300,3900,200,*,UP,POLY +S 1400,1500,1400,3500,200,*,UP,NTRANS +S 2100,2000,2700,2000,300,*,RIGHT,ALU1 +S 2300,1500,2300,3500,200,*,UP,NTRANS +S 3000,8000,3000,8700,400,*,UP,ALU1 +S 1000,8000,1000,8700,400,*,UP,ALU1 +S 2000,2000,2000,7900,300,*,UP,ALU1 +S 2800,1700,2800,3300,600,*,UP,NDIF +S 1000,1300,1000,2000,400,*,UP,ALU1 +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 3000,3100,3000,6900,300,*,UP,ALU1 +S -300,7800,4300,7800,6000,*,RIGHT,NWELL +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 2300,700,3200,700,600,*,RIGHT,PTIE +S 2600,4100,3000,4100,400,*,RIGHT,POLY +S 1400,3800,1400,6500,200,*,UP,POLY +V 1000,5000,CONT_POLY,* +V 2500,700,CONT_BODY_P,* +V 2800,2000,CONT_DIF_N,* +V 3000,4000,CONT_POLY,* +V 2000,7000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 1000,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/na2_x1.vbe b/pdks/symbolic/nsxlib/cells/na2_x1.vbe new file mode 100644 index 000000000..486b6aaf0 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 59; + CONSTANT tphl_i1_nq : NATURAL := 111; + CONSTANT tplh_i1_nq : NATURAL := 234; + CONSTANT tplh_i0_nq : NATURAL := 288; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x1; + +ARCHITECTURE behaviour_data_flow OF na2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x1" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 900 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/na2_x4.ap b/pdks/symbolic/nsxlib/cells/na2_x4.ap new file mode 100644 index 000000000..11369890b --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na2_x4.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H na2_x4,P,25/ 9/2019,100 +A 0,0,7000,10000 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 4000,4000,ref_ref,nq_20 +R 4000,3000,ref_ref,nq_15 +R 4000,2000,ref_ref,nq_10 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 4000,5000,ref_ref,nq_25 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +S 2200,4400,2400,4400,200,*,LEFT,POLY +S 2200,3700,2200,4300,200,*,UP,POLY +S 2400,4400,2400,6200,200,*,UP,POLY +S 4000,2100,4000,7000,300,nq,UP,CALU1 +S 800,700,2000,700,600,*,RIGHT,PTIE +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S -300,7800,7300,7800,6000,*,RIGHT,NWELL +S 4500,5500,4500,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,400,*,UP,PDIF +S 4500,3800,4500,5200,200,*,UP,POLY +S 5000,5700,5000,9300,400,*,UP,PDIF +S 2200,1500,2200,3500,200,*,UP,NTRANS +S 1800,1700,1800,3300,600,*,UP,NDIF +S 4000,2100,4000,7000,300,*,UP,ALU1 +S 6300,1700,6300,2300,400,*,UP,NDIF +S 6100,2100,6100,6900,300,*,UP,ALU1 +S 6200,5700,6200,7300,600,*,UP,PDIF +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 2400,6500,2400,8500,200,*,UP,PTRANS +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 3600,3800,3600,5200,200,*,UP,POLY +S 5700,5500,5700,7500,200,*,UP,PTRANS +S 5700,2800,5700,5200,200,*,UP,POLY +S 4500,2800,4500,3800,200,*,UP,POLY +S 900,2000,2900,2000,300,*,RIGHT,ALU1 +S 1300,1500,1300,3500,200,*,UP,NTRANS +S 1500,6500,1500,8500,200,*,UP,PTRANS +S 1800,6700,1800,8300,400,*,UP,PDIF +S 3600,2800,3600,4200,200,*,UP,POLY +S 3100,5700,3100,9300,400,*,UP,PDIF +S 800,6700,800,8300,600,*,UP,PDIF +S 700,1700,700,3300,400,*,UP,NDIF +S 1000,8100,1000,8900,300,*,UP,ALU1 +S 5700,7700,5700,7900,200,*,UP,POLY +S 3700,4000,4900,4000,400,*,RIGHT,POLY +S 5100,4000,6100,4000,300,*,RIGHT,ALU1 +S 5700,1500,5700,2500,200,*,UP,NTRANS +S 4900,1200,4900,1800,400,*,UP,ALU1 +S 2000,8000,5900,8000,300,*,RIGHT,ALU1 +S 1500,6100,1500,6400,200,*,UP,POLY +S 1300,3800,1300,6000,200,*,UP,POLY +S 1300,6100,1500,6100,200,*,RIGHT,POLY +S 4000,800,4000,2300,600,*,UP,NDIF +S 5000,800,5000,2300,400,*,UP,NDIF +S 4500,600,4500,2500,200,*,UP,NTRANS +S 3600,600,3600,2500,200,*,UP,NTRANS +S 2900,800,2900,3300,400,*,UP,NDIF +S 1000,3100,1000,6900,300,i0,UP,CALU1 +S 2000,3100,2000,6900,300,i1,UP,CALU1 +V 3100,900,CONT_DIF_N,* +V 5100,4000,CONT_POLY,* +V 1800,700,CONT_BODY_P,* +V 800,700,CONT_BODY_P,* +V 1000,8000,CONT_DIF_P,* +V 900,2000,CONT_DIF_N,* +V 2000,8000,CONT_DIF_P,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 5800,8000,CONT_POLY,* +V 6100,2000,CONT_DIF_N,* +V 6100,7000,CONT_DIF_P,* +V 6100,6000,CONT_DIF_P,* +V 4900,1900,CONT_DIF_N,* +V 4900,9100,CONT_DIF_P,* +V 3200,9100,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/na2_x4.vbe b/pdks/symbolic/nsxlib/cells/na2_x4.vbe new file mode 100644 index 000000000..c73eca058 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 353; + CONSTANT tphl_i0_nq : NATURAL := 412; + CONSTANT tplh_i0_nq : NATURAL := 552; + CONSTANT tplh_i1_nq : NATURAL := 601; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x4; + +ARCHITECTURE behaviour_data_flow OF na2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x4" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/na3_x1.ap b/pdks/symbolic/nsxlib/cells/na3_x1.ap new file mode 100644 index 000000000..f474bee0d --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na3_x1.ap @@ -0,0 +1,70 @@ +V ALLIANCE : 6 +H na3_x1,P,26/ 9/2019,100 +A 0,0,5000,10000 +R 4000,8000,ref_ref,nq_40 +R 3000,5000,ref_ref,i2_25 +R 3000,6000,ref_ref,i2_30 +R 2000,2000,ref_ref,i1_10 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,2000,ref_ref,i0_10 +R 1000,3000,ref_ref,i0_15 +R 3000,2000,ref_ref,i2_10 +R 4000,7000,ref_ref,nq_35 +R 4000,5000,ref_ref,nq_25 +R 4000,6000,ref_ref,nq_30 +R 4000,4000,ref_ref,nq_20 +R 4000,3000,ref_ref,nq_15 +R 4000,2000,ref_ref,nq_10 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 3000,3000,ref_ref,i2_15 +R 3000,4000,ref_ref,i2_20 +S 1300,3800,1300,4200,300,*,DOWN,POLY +S 4000,2100,4000,7900,300,nq,UP,CALU1 +S 3000,2100,3000,5900,300,i2,UP,CALU1 +S 2000,2100,2000,5900,300,i1,UP,CALU1 +S 1000,2100,1000,6900,300,i0,UP,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 3200,6700,3200,8300,400,*,UP,PDIF +S 3200,2700,3200,3100,200,*,UP,POLY +S 3200,600,3200,2500,200,*,UP,NTRANS +S 2300,600,2300,2500,200,*,UP,NTRANS +S 700,800,700,2300,400,*,UP,NDIF +S 2600,4200,2600,6200,200,*,UP,POLY +S 2300,2800,2300,4100,200,*,UP,POLY +S 1400,2800,1400,6200,200,*,UP,POLY +S 1000,8000,1000,8900,400,*,UP,ALU1 +S 800,6700,800,8300,600,*,UP,PDIF +S 1000,2100,1000,6900,300,*,UP,ALU1 +S 2100,7000,4000,7000,300,*,RIGHT,ALU1 +S 3100,8000,3100,9000,400,*,UP,ALU1 +S 3600,6500,3600,8500,200,*,UP,PTRANS +S 3000,2100,3000,5900,300,*,UP,ALU1 +S 2000,2100,2000,5900,300,*,UP,ALU1 +S 1400,6500,1400,8500,200,*,UP,PTRANS +S 1400,600,1400,2500,200,*,UP,NTRANS +S 4000,2100,4000,7900,300,*,UP,ALU1 +S -300,7800,5300,7800,6000,*,RIGHT,NWELL +S 3800,1700,3800,2300,1000,*,UP,NDIF +S 2900,3200,3600,3200,200,*,RIGHT,POLY +S 3600,3200,3600,6200,200,*,UP,POLY +S 4300,6700,4300,8300,400,*,UP,PDIF +S 2000,6700,2000,8300,600,*,UP,PDIF +S 2600,6500,2600,8500,200,*,UP,PTRANS +S 2300,4100,2600,4100,200,*,RIGHT,POLY +V 1000,4000,CONT_POLY,* +V 1000,8000,CONT_DIF_P,* +V 1000,900,CONT_DIF_N,* +V 3000,3000,CONT_POLY,* +V 4000,2000,CONT_DIF_N,* +V 2000,4000,CONT_POLY,* +V 2000,7000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 3100,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/na3_x1.vbe b/pdks/symbolic/nsxlib/cells/na3_x1.vbe new file mode 100644 index 000000000..d51e12075 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 4120; + CONSTANT rdown_i1_nq : NATURAL := 4120; + CONSTANT rdown_i2_nq : NATURAL := 4120; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 119; + CONSTANT tphl_i1_nq : NATURAL := 171; + CONSTANT tphl_i2_nq : NATURAL := 193; + CONSTANT tplh_i2_nq : NATURAL := 265; + CONSTANT tplh_i1_nq : NATURAL := 316; + CONSTANT tplh_i0_nq : NATURAL := 363; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x1; + +ARCHITECTURE behaviour_data_flow OF na3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/na3_x4.ap b/pdks/symbolic/nsxlib/cells/na3_x4.ap new file mode 100644 index 000000000..55610e5e5 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na3_x4.ap @@ -0,0 +1,105 @@ +V ALLIANCE : 6 +H na3_x4,P,18/ 9/2019,100 +A 0,0,8000,10000 +R 2000,5000,ref_ref,i2_25 +R 2000,4000,ref_ref,i2_20 +R 2000,3000,ref_ref,i2_15 +R 3000,5000,ref_ref,i1_25 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 1000,7000,ref_ref,i0_35 +R 3000,4000,ref_ref,i1_20 +R 3000,3000,ref_ref,i1_15 +R 5000,2000,ref_ref,nq_10 +R 5000,3000,ref_ref,nq_15 +R 5000,4000,ref_ref,nq_20 +R 5000,5000,ref_ref,nq_25 +R 2000,7000,ref_ref,i2_35 +R 2000,6000,ref_ref,i2_30 +R 3000,6000,ref_ref,i1_30 +R 3000,7000,ref_ref,i1_35 +R 1000,6000,ref_ref,i0_30 +S 1000,3100,1000,6900,300,i0,UP,CALU1 +S 2000,3100,2000,6900,300,i2,UP,CALU1 +S 3000,3100,3000,6900,300,i1,UP,CALU1 +S 5000,2100,5000,7000,300,nq,UP,CALU1 +S 5000,2100,5000,7000,300,*,UP,ALU1 +S 3900,800,3900,3300,400,*,UP,NDIF +S 6200,5700,6200,9000,200,*,UP,PDIF +S 2900,4200,3500,4200,200,*,RIGHT,POLY +S 500,6500,500,8100,400,*,UP,PDIF +S 6800,7600,6800,8000,200,*,UP,POLY +S -300,7800,8300,7800,6000,*,RIGHT,NWELL +S 7200,2100,7200,6900,300,*,UP,ALU1 +S 6100,4000,7100,4000,300,*,RIGHT,ALU1 +S 7300,5700,7300,7300,400,*,UP,PDIF +S 7300,1700,7300,2300,400,*,UP,NDIF +S 5700,5500,5700,9500,200,*,UP,PTRANS +S 5700,3800,5700,5200,200,*,UP,POLY +S 3000,3600,3000,3900,200,*,UP,POLY +S 4600,4000,5900,4000,400,*,RIGHT,POLY +S 1000,4000,1200,4000,400,*,RIGHT,POLY +S 3700,800,3700,3300,400,*,UP,NDIF +S 5000,800,5000,2300,400,*,UP,NDIF +S 4600,600,4600,2500,200,*,UP,NTRANS +S 6100,800,6100,2300,400,*,UP,NDIF +S 5700,600,5700,2500,200,*,UP,NTRANS +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 3000,3100,3000,6900,300,*,UP,ALU1 +S 6800,5500,6800,7500,200,*,UP,PTRANS +S 6800,1500,6800,2500,200,*,UP,NTRANS +S 3000,1500,3000,3500,200,*,UP,NTRANS +S 900,2000,3900,2000,300,*,RIGHT,ALU1 +S 700,8000,6900,8000,300,*,RIGHT,ALU1 +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 5200,5700,5200,9300,600,*,UP,PDIF +S 4600,5500,4600,9500,200,*,UP,PTRANS +S 6800,2800,6800,5200,200,*,UP,POLY +S 4600,3800,4600,5200,200,*,UP,POLY +S 4000,2100,4000,7900,300,*,UP,ALU1 +S 1000,5900,1200,5900,200,*,RIGHT,POLY +S 1200,3800,1200,5800,200,*,UP,POLY +S 1200,1500,1200,3500,200,*,UP,NTRANS +S 2100,1500,2100,3500,200,*,UP,NTRANS +S 2100,3800,2100,5200,200,*,UP,POLY +S 1000,6300,1000,8300,200,*,UP,PTRANS +S 2600,6300,2600,8300,200,*,UP,PTRANS +S 3000,6500,3000,8100,400,*,UP,PDIF +S 2600,5200,2600,6100,200,*,UP,POLY +S 2200,5200,2600,5200,200,*,RIGHT,POLY +S 1800,6500,1800,9300,600,*,UP,PDIF +S 1000,5900,1000,6200,200,*,UP,POLY +S 700,1700,700,3300,400,*,UP,NDIF +S 3500,4200,3500,6000,200,*,UP,POLY +S 3500,6300,3500,8300,200,*,UP,PTRANS +S 4600,2800,4600,4200,200,*,UP,POLY +S 4200,5700,4200,9300,400,*,UP,PDIF +S 5700,2800,5700,3800,200,*,UP,POLY +S 6200,1300,6200,1900,400,*,UP,ALU1 +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 1000,700,2800,700,600,*,RIGHT,PTIE +V 6800,8000,CONT_POLY,* +V 4000,9200,CONT_DIF_P,* +V 2000,5000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 5000,2000,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 600,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 7200,7000,CONT_DIF_P,* +V 7200,6000,CONT_DIF_P,* +V 7200,2000,CONT_DIF_N,* +V 6200,9200,CONT_DIF_P,* +V 6200,1900,CONT_DIF_N,* +V 5000,7000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 1800,9200,CONT_DIF_P,* +V 900,700,CONT_BODY_P,* +V 1700,700,CONT_BODY_P,* +V 2500,700,CONT_BODY_P,* +V 3900,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/na3_x4.vbe b/pdks/symbolic/nsxlib/cells/na3_x4.vbe new file mode 100644 index 000000000..160a97f61 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 460; + CONSTANT tphl_i2_nq : NATURAL := 519; + CONSTANT tphl_i0_nq : NATURAL := 556; + CONSTANT tplh_i0_nq : NATURAL := 601; + CONSTANT tplh_i2_nq : NATURAL := 647; + CONSTANT tplh_i1_nq : NATURAL := 691; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x4; + +ARCHITECTURE behaviour_data_flow OF na3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/na4_x1.ap b/pdks/symbolic/nsxlib/cells/na4_x1.ap new file mode 100644 index 000000000..dfcece9c5 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na4_x1.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 6 +H na4_x1,P,26/ 9/2019,100 +A 0,0,6000,10000 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_10 +R 1000,2000,ref_ref,i0_10 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 4000,4000,ref_ref,i3_20 +R 4000,3000,ref_ref,i3_15 +R 4000,2000,ref_ref,i3_10 +R 3000,2000,ref_ref,i2_10 +R 3000,3000,ref_ref,i2_15 +R 3000,4000,ref_ref,i2_20 +R 3000,5000,ref_ref,i2_25 +R 3000,6000,ref_ref,i2_30 +R 3000,7000,ref_ref,i2_35 +R 2000,7000,ref_ref,i1_35 +R 5000,8000,ref_ref,nq_40 +R 5000,2000,ref_ref,nq_10 +R 5000,3000,ref_ref,nq_15 +R 5000,4000,ref_ref,nq_20 +R 5000,5000,ref_ref,nq_25 +R 5000,6000,ref_ref,nq_30 +R 5000,7000,ref_ref,nq_35 +R 4000,7000,ref_ref,i3_35 +R 4000,6000,ref_ref,i3_30 +R 4000,5000,ref_ref,i3_25 +R 2000,6000,ref_ref,i1_30 +S 1300,2800,1300,3200,300,*,DOWN,POLY +S 5000,2100,5000,7900,300,nq,UP,CALU1 +S 4000,2100,4000,6900,300,i3,UP,CALU1 +S 3000,2100,3000,6900,300,i2,UP,CALU1 +S 2000,2100,2000,6900,300,i1,UP,CALU1 +S 1000,2100,1000,6900,300,i0,UP,CALU1 +S 5000,2100,5000,7900,300,*,UP,ALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 3700,5100,3700,6200,200,*,UP,POLY +S 3200,2800,3200,5000,200,*,UP,POLY +S 2900,5100,3600,5100,200,*,RIGHT,POLY +S 1000,3000,1400,3000,400,*,RIGHT,POLY +S 4100,600,4100,2500,200,*,UP,NTRANS +S 3200,600,3200,2500,200,*,UP,NTRANS +S 2300,600,2300,2500,200,*,UP,NTRANS +S 700,800,700,2300,400,*,UP,NDIF +S 1400,600,1400,2500,200,*,UP,NTRANS +S 1400,2800,1400,6200,200,*,UP,POLY +S 2300,2800,2300,6200,200,*,UP,POLY +S 4600,6500,4600,8500,200,*,UP,PTRANS +S 5300,6700,5300,9100,400,*,UP,PDIF +S 1900,8000,5000,8000,300,*,RIGHT,ALU1 +S 4000,2100,4000,6900,300,*,UP,ALU1 +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 2000,2100,2000,6900,300,*,UP,ALU1 +S 1000,2100,1000,6900,300,*,UP,ALU1 +S -300,7800,6300,7800,6000,*,RIGHT,NWELL +S 5000,1700,5000,2300,800,*,UP,NDIF +S 4200,6700,4200,8300,400,*,UP,PDIF +S 3900,4200,4600,4200,200,*,RIGHT,POLY +S 3700,6500,3700,8500,200,*,UP,PTRANS +S 3000,6700,3000,9100,400,*,UP,PDIF +S 2300,6500,2300,8500,200,*,UP,PTRANS +S 1400,6500,1400,8500,200,*,UP,PTRANS +S 1800,6700,1800,8300,400,*,UP,PDIF +S 900,8100,900,8900,300,*,UP,ALU1 +S 700,6700,700,8300,400,*,UP,PDIF +S 4100,2800,4100,3800,200,*,UP,POLY +S 4600,4200,4600,6200,200,*,UP,POLY +V 1000,3000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 1000,900,CONT_DIF_N,* +V 5000,2000,CONT_DIF_N,* +V 4200,8000,CONT_DIF_P,* +V 1900,8000,CONT_DIF_P,* +V 3000,9300,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 5300,9300,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/na4_x1.vbe b/pdks/symbolic/nsxlib/cells/na4_x1.vbe new file mode 100644 index 000000000..07f51ce0b --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 5400; + CONSTANT rdown_i1_nq : NATURAL := 5400; + CONSTANT rdown_i2_nq : NATURAL := 5400; + CONSTANT rdown_i3_nq : NATURAL := 5400; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT rup_i3_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 179; + CONSTANT tphl_i1_nq : NATURAL := 237; + CONSTANT tphl_i2_nq : NATURAL := 269; + CONSTANT tphl_i3_nq : NATURAL := 282; + CONSTANT tplh_i3_nq : NATURAL := 302; + CONSTANT tplh_i2_nq : NATURAL := 350; + CONSTANT tplh_i1_nq : NATURAL := 395; + CONSTANT tplh_i0_nq : NATURAL := 438; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x1; + +ARCHITECTURE behaviour_data_flow OF na4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/na4_x4.ap b/pdks/symbolic/nsxlib/cells/na4_x4.ap new file mode 100644 index 000000000..7299d710e --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na4_x4.ap @@ -0,0 +1,129 @@ +V ALLIANCE : 6 +H na4_x4,P,25/ 9/2019,100 +A 0,0,10000,10000 +R 6000,3000,ref_ref,i1_15 +R 6000,2000,ref_ref,i1_10 +R 5000,2000,ref_ref,i0_10 +R 5000,7000,ref_ref,i0_35 +R 5000,6000,ref_ref,i0_30 +R 5000,5000,ref_ref,i0_25 +R 5000,4000,ref_ref,i0_20 +R 5000,3000,ref_ref,i0_15 +R 7000,4000,ref_ref,i2_20 +R 8000,4000,ref_ref,i3_20 +R 8000,3000,ref_ref,i3_15 +R 8000,2000,ref_ref,i3_10 +R 7000,2000,ref_ref,i2_10 +R 7000,3000,ref_ref,i2_15 +R 3000,3000,ref_ref,nq_15 +R 3000,4000,ref_ref,nq_20 +R 8000,5000,ref_ref,i3_25 +R 3000,2000,ref_ref,nq_10 +R 3000,7000,ref_ref,nq_35 +R 3000,6000,ref_ref,nq_30 +R 3000,5000,ref_ref,nq_25 +R 8000,6000,ref_ref,i3_30 +R 8000,7000,ref_ref,i3_35 +R 6000,4000,ref_ref,i1_20 +R 6000,5000,ref_ref,i1_25 +R 7000,5000,ref_ref,i2_25 +R 7000,6000,ref_ref,i2_30 +R 7000,7000,ref_ref,i2_35 +R 6000,7000,ref_ref,i1_35 +R 6000,6000,ref_ref,i1_30 +S 4600,6700,4600,9300,400,*,UP,PDIF +S 5300,6500,5300,8500,200,*,UP,PTRANS +S 7700,5200,7700,6200,200,*,UP,POLY +S 7900,2800,7900,3800,200,*,UP,POLY +S -300,7800,10300,7800,6000,*,RIGHT,NWELL +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 2200,8000,9000,8000,300,*,RIGHT,ALU1 +S 800,2100,800,5900,300,*,UP,ALU1 +S 900,4000,1100,4000,400,*,RIGHT,ALU1 +S 900,2000,1200,2000,300,*,RIGHT,ALU1 +S 6900,5200,7600,5200,200,*,RIGHT,POLY +S 5300,3100,5300,6200,200,*,UP,POLY +S 5200,2800,5200,3100,200,*,UP,POLY +S 1200,4000,3600,4000,400,*,RIGHT,POLY +S 1200,5000,1600,5000,400,*,RIGHT,POLY +S 1200,5100,1200,5300,200,*,UP,POLY +S 1700,2700,1700,2900,200,*,UP,POLY +S 7900,4100,8600,4100,200,*,RIGHT,POLY +S 1600,3000,1900,3000,400,*,RIGHT,ALU1 +S 1600,5000,1900,5000,400,*,RIGHT,ALU1 +S 9300,6700,9300,9100,400,*,UP,PDIF +S 3600,2800,3600,5200,200,*,UP,POLY +S 4200,5700,4200,9300,600,*,UP,PDIF +S 1200,5500,1200,7500,200,*,UP,PTRANS +S 3000,5700,3000,9300,600,*,UP,PDIF +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 8000,2100,8000,6900,300,*,UP,ALU1 +S 7000,2100,7000,6900,300,*,UP,ALU1 +S 6000,2100,6000,6900,300,*,UP,ALU1 +S 5000,2100,5000,6900,300,*,UP,ALU1 +S 8600,6500,8600,8500,200,*,UP,PTRANS +S 8200,6700,8200,8300,400,*,UP,PDIF +S 7700,6500,7700,8500,200,*,UP,PTRANS +S 7000,6700,7000,9100,400,*,UP,PDIF +S 6300,6500,6300,8500,200,*,UP,PTRANS +S 5800,6700,5800,8300,400,*,UP,PDIF +S 1900,5700,1900,9300,400,*,UP,PDIF +S 800,6100,800,6900,300,*,UP,ALU1 +S 700,5700,700,7300,400,*,UP,PDIF +S 2000,3000,2000,8000,300,*,UP,ALU1 +S 7000,2800,7000,5200,200,*,UP,POLY +S 9000,1700,9000,2300,400,*,UP,NDIF +S 9000,2100,9000,7900,300,*,UP,ALU1 +S 1100,1700,1100,2300,400,*,UP,NDIF +S 8600,4200,8600,6200,200,*,UP,POLY +S 1700,600,1700,2500,200,*,UP,NTRANS +S 2600,600,2600,2500,200,*,UP,NTRANS +S 2000,800,2000,2300,400,*,UP,NDIF +S 3000,800,3000,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 4600,800,4600,2300,600,*,UP,NDIF +S 4200,800,4200,2300,600,*,UP,NDIF +S 6100,600,6100,2500,200,*,UP,NTRANS +S 5200,600,5200,2500,200,*,UP,NTRANS +S 7000,600,7000,2500,200,*,UP,NTRANS +S 7900,600,7900,2500,200,*,UP,NTRANS +S 8600,800,8600,2300,400,*,UP,NDIF +S 900,8200,900,9200,600,*,UP,NTIE +S 2400,5100,2600,5100,200,*,RIGHT,POLY +S 6100,6100,6300,6100,200,*,RIGHT,POLY +S 2600,2800,2600,5000,200,*,UP,POLY +S 6100,2800,6100,6000,200,*,UP,POLY +S 6300,6100,6300,6400,200,*,UP,POLY +S 2400,5100,2400,5400,200,*,UP,POLY +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 8000,2100,8000,6900,300,i3,UP,CALU1 +S 7000,2100,7000,6900,300,i2,UP,CALU1 +S 6000,2100,6000,6900,300,i1,UP,CALU1 +S 5000,2100,5000,6900,300,i0,UP,CALU1 +S 3000,2100,3000,6900,300,nq,UP,CALU1 +V 1800,5000,CONT_POLY,* +V 800,6000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 4200,9200,CONT_DIF_P,* +V 1200,2000,CONT_DIF_N,* +V 9300,9400,CONT_DIF_P,* +V 2100,900,CONT_DIF_N,* +V 900,9100,CONT_BODY_N,* +V 2000,9200,CONT_DIF_P,* +V 5900,8000,CONT_DIF_P,* +V 7000,9400,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 1600,3000,CONT_POLY,* +V 1100,4000,CONT_POLY,* +V 4400,900,CONT_DIF_N,* +V 5000,3000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +V 7000,5000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 8200,8000,CONT_DIF_P,* +V 9000,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/na4_x4.vbe b/pdks/symbolic/nsxlib/cells/na4_x4.vbe new file mode 100644 index 000000000..a67d18901 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/na4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 578; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i3_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 681; + CONSTANT tplh_i2_nq : NATURAL := 689; + CONSTANT tphl_i3_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 731; + CONSTANT tplh_i0_nq : NATURAL := 771; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x4; + +ARCHITECTURE behaviour_data_flow OF na4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/nao22_x1.ap b/pdks/symbolic/nsxlib/cells/nao22_x1.ap new file mode 100644 index 000000000..cdb332f62 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nao22_x1.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H nao22_x1,P,18/ 9/2019,100 +A 0,0,6000,10000 +R 1000,8000,ref_ref,i0_40 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 3000,7000,ref_ref,nq_35 +R 3000,6000,ref_ref,nq_30 +R 4000,2000,ref_ref,i2_10 +R 4000,8000,ref_ref,i2_40 +R 3000,8000,ref_ref,nq_40 +R 2000,8000,ref_ref,i1_40 +R 3000,5000,ref_ref,nq_25 +R 3000,4000,ref_ref,nq_20 +R 3000,3000,ref_ref,nq_15 +R 4000,7000,ref_ref,i2_35 +R 4000,6000,ref_ref,i2_30 +R 4000,5000,ref_ref,i2_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 2000,4000,ref_ref,i1_20 +R 1000,7000,ref_ref,i0_35 +R 2000,7000,ref_ref,i1_35 +S 2000,4100,2000,7900,300,i1,UP,CALU1 +S 1000,4100,1000,7900,300,i0,UP,CALU1 +S 3000,3100,3000,7900,300,nq,UP,CALU1 +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 4000,2100,4000,7900,300,i2,UP,CALU1 +S 5200,2400,5200,3500,600,*,UP,PTIE +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 2000,4000,2700,4000,400,*,RIGHT,POLY +S 3700,4000,4000,4000,400,*,RIGHT,POLY +S 5200,1100,5200,3300,300,*,UP,ALU1 +S 5200,5900,5200,8900,300,*,UP,ALU1 +S 5200,8200,5200,9200,600,*,UP,NTIE +S 5200,5500,5200,6700,600,*,UP,NTIE +S 4200,800,4200,2300,600,*,UP,NDIF +S 3700,600,3700,2500,200,*,UP,NTRANS +S 3100,800,3100,2300,400,*,UP,NDIF +S 2000,800,2000,3100,600,*,UP,NDIF +S 2800,600,2800,2500,200,*,UP,NTRANS +S 2000,4100,2000,7900,300,*,UP,ALU1 +S 4000,2100,4000,7900,300,*,UP,ALU1 +S -300,7800,6300,7800,6000,*,RIGHT,NWELL +S 700,800,700,2300,400,*,UP,NDIF +S 1200,600,1200,2500,200,*,UP,NTRANS +S 1900,3000,3000,3000,300,*,RIGHT,ALU1 +S 1800,5700,1800,9300,600,*,UP,PDIF +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 1200,2800,1200,5200,200,*,UP,POLY +S 1000,4100,1000,7900,300,*,UP,ALU1 +S 2600,5100,2600,5400,200,*,UP,POLY +S 2800,2800,2800,5000,200,*,UP,POLY +S 2600,5100,2800,5100,200,*,RIGHT,POLY +S 3000,5700,3000,9300,400,*,UP,PDIF +S 2600,5500,2600,9500,200,*,UP,PTRANS +S 3700,5500,3700,9500,200,*,UP,PTRANS +S 3700,2800,3700,5200,200,*,UP,POLY +S 900,2000,2900,2000,300,*,RIGHT,ALU1 +S 700,5700,700,9300,400,*,UP,PDIF +S 5200,900,5200,1700,600,*,UP,PTIE +V 800,2000,CONT_DIF_N,* +V 800,9200,CONT_DIF_P,* +V 4100,9200,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 2000,3000,CONT_DIF_N,* +V 5200,900,CONT_BODY_P,* +V 3000,7000,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 5200,5800,CONT_BODY_N,* +V 5200,3400,CONT_BODY_P,* +V 4100,900,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 5200,9100,CONT_BODY_N,* +V 3200,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/nao22_x1.vbe b/pdks/symbolic/nsxlib/cells/nao22_x1.vbe new file mode 100644 index 000000000..13c4e6dec --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nao22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 1790; + CONSTANT tphl_i2_nq : NATURAL := 165; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tplh_i2_nq : NATURAL := 238; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x1; + +ARCHITECTURE behaviour_data_flow OF nao22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 900 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/nao22_x4.ap b/pdks/symbolic/nsxlib/cells/nao22_x4.ap new file mode 100644 index 000000000..81ac4a53b --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nao22_x4.ap @@ -0,0 +1,128 @@ +V ALLIANCE : 6 +H nao22_x4,P,26/ 9/2019,100 +A 0,0,10000,10000 +R 8000,7000,ref_ref,nq_35 +R 8000,6000,ref_ref,nq_30 +R 8000,4000,ref_ref,nq_20 +R 8000,2000,ref_ref,nq_10 +R 8000,3000,ref_ref,nq_15 +R 8000,5000,ref_ref,nq_25 +R 4000,4000,ref_ref,i0_20 +R 8000,8000,ref_ref,nq_40 +R 1000,8000,ref_ref,i2_40 +R 1000,2000,ref_ref,i2_10 +R 1000,5000,ref_ref,i2_25 +R 1000,7000,ref_ref,i2_35 +R 3000,7000,ref_ref,i1_35 +R 4000,7000,ref_ref,i0_35 +R 1000,4000,ref_ref,i2_20 +R 3000,4000,ref_ref,i1_20 +R 3000,5000,ref_ref,i1_25 +R 3000,6000,ref_ref,i1_30 +R 4000,6000,ref_ref,i0_30 +R 4000,5000,ref_ref,i0_25 +R 1000,3000,ref_ref,i2_15 +R 1000,6000,ref_ref,i2_30 +S 1300,3800,1300,4200,300,*,DOWN,POLY +S 8000,2100,8000,7900,300,nq,UP,CALU1 +S 4000,4100,4000,6900,300,i0,UP,CALU1 +S 3000,4100,3000,6900,300,i1,UP,CALU1 +S 1000,2100,1000,7900,300,i2,UP,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 3600,6500,3600,8500,200,*,UP,PTRANS +S 1600,6500,1600,8500,200,*,UP,PTRANS +S 2000,6700,2000,8300,400,*,UP,PDIF +S 3200,6700,3200,8300,400,*,UP,PDIF +S 5600,8300,5600,9400,600,*,UP,NTIE +S 1000,4000,1400,4000,400,*,RIGHT,POLY +S 2600,4000,3000,4000,400,*,RIGHT,POLY +S 7000,4000,8600,4000,400,*,RIGHT,POLY +S 4000,4100,4000,6900,300,*,UP,ALU1 +S 1000,2100,1000,7900,300,*,UP,ALU1 +S 9200,5700,9200,9300,400,*,UP,PDIF +S 9000,6100,9000,8900,300,*,UP,ALU1 +S 9000,1100,9000,1900,300,*,UP,ALU1 +S 700,900,700,2300,400,*,UP,NDIF +S 2400,1500,2400,2500,200,*,UP,NTRANS +S 4000,1500,4000,2500,200,*,UP,NTRANS +S 7600,5500,7600,9500,200,*,UP,PTRANS +S 7200,8100,7200,8900,300,*,UP,ALU1 +S 6200,5000,6600,5000,400,*,RIGHT,POLY +S 3000,4100,3000,6900,300,*,UP,ALU1 +S 3200,1700,3200,3100,600,*,UP,NDIF +S 5700,4000,6900,4000,300,*,RIGHT,ALU1 +S 6600,5100,6600,6900,300,*,UP,ALU1 +S 8000,2100,8000,7900,300,*,UP,ALU1 +S 2300,8000,5500,8000,300,*,RIGHT,ALU1 +S 5600,7100,5600,7900,300,*,UP,ALU1 +S 5700,7000,6500,7000,300,*,RIGHT,ALU1 +S 6200,5500,6200,7500,200,*,UP,PTRANS +S 8600,5500,8600,9500,200,*,UP,PTRANS +S 1400,1500,1400,2500,200,*,UP,NTRANS +S 4400,1700,4400,2300,600,*,UP,NDIF +S 2000,1700,2000,2300,600,*,UP,NDIF +S 5600,1700,5600,2300,600,*,UP,NDIF +S 6200,1500,6200,2500,200,*,UP,NTRANS +S 6200,2800,6200,5200,200,*,UP,POLY +S 8600,2800,8600,5200,200,*,UP,POLY +S 2100,2000,4300,2000,300,*,RIGHT,ALU1 +S 2000,3100,2000,7900,300,*,UP,ALU1 +S 1600,6100,1600,6400,200,*,UP,POLY +S 2600,6100,2600,6400,200,*,UP,POLY +S 3600,6100,3600,6400,200,*,UP,POLY +S 7600,5100,7600,5400,200,*,UP,POLY +S 7400,2800,7400,5000,200,*,UP,POLY +S 4000,2800,4000,6000,200,*,UP,POLY +S 2100,3000,3100,3000,300,*,RIGHT,ALU1 +S 6900,5700,6900,9300,400,*,UP,PDIF +S 8000,5700,8000,9300,400,*,UP,PDIF +S 5600,5700,5600,7300,600,*,UP,PDIF +S -300,7800,10300,7800,6000,*,RIGHT,NWELL +S 800,6700,800,9100,600,*,UP,PDIF +S 4400,6700,4400,9100,600,*,UP,PDIF +S 2600,6500,2600,8500,200,*,UP,PTRANS +S 7000,2100,7000,3900,300,*,UP,ALU1 +S 5700,2000,6900,2000,300,*,RIGHT,ALU1 +S 5600,4100,5600,5900,300,*,UP,ALU1 +S 7400,600,7400,2500,200,*,UP,NTRANS +S 6900,800,6900,2300,400,*,UP,NDIF +S 8000,800,8000,2300,600,*,UP,NDIF +S 8600,600,8600,2500,200,*,UP,NTRANS +S 9200,800,9200,2300,400,*,UP,NDIF +S 1400,6100,1600,6100,200,*,RIGHT,POLY +S 2400,6100,2600,6100,200,*,RIGHT,POLY +S 3600,6100,4000,6100,200,*,RIGHT,POLY +S 7400,5100,7600,5100,200,*,RIGHT,POLY +S 1400,2800,1400,6000,200,*,UP,POLY +S 2400,2800,2400,5900,200,*,UP,POLY +V 1000,4000,CONT_POLY,* +V 3200,3000,CONT_DIF_N,* +V 3000,4000,CONT_POLY,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 9000,2000,CONT_DIF_N,* +V 7200,9200,CONT_DIF_P,* +V 4400,9200,CONT_DIF_P,* +V 800,9200,CONT_DIF_P,* +V 700,800,CONT_DIF_N,* +V 5600,9100,CONT_BODY_N,* +V 5000,800,CONT_BODY_P,* +V 5600,2000,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 7100,8000,CONT_DIF_P,* +V 8000,2000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 4400,2000,CONT_DIF_N,* +V 5600,6000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 7000,900,CONT_DIF_N,* +V 9000,900,CONT_DIF_N,* +V 6800,4000,CONT_POLY,* +V 6800,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/nao22_x4.vbe b/pdks/symbolic/nsxlib/cells/nao22_x4.vbe new file mode 100644 index 000000000..ebdcfc515 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 596; + CONSTANT tplh_i2_nq : NATURAL := 636; + CONSTANT tplh_i0_nq : NATURAL := 650; + CONSTANT tphl_i1_nq : NATURAL := 664; + CONSTANT tplh_i1_nq : NATURAL := 723; + CONSTANT tphl_i0_nq : NATURAL := 732; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x4; + +ARCHITECTURE behaviour_data_flow OF nao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/nao2o22_x1.ap b/pdks/symbolic/nsxlib/cells/nao2o22_x1.ap new file mode 100644 index 000000000..4fb48ef23 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nao2o22_x1.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H nao2o22_x1,P,18/ 9/2019,100 +A 0,0,7000,10000 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,6000,ref_ref,i0_30 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 1000,8000,ref_ref,i0_40 +R 1000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 3000,8000,ref_ref,nq_40 +R 4000,8000,ref_ref,i3_40 +R 5000,8000,ref_ref,i2_40 +R 2000,4000,ref_ref,i1_20 +R 4000,3000,ref_ref,i3_15 +R 4000,4000,ref_ref,i3_20 +R 4000,5000,ref_ref,i3_25 +R 4000,6000,ref_ref,i3_30 +R 3000,7000,ref_ref,nq_35 +R 3000,6000,ref_ref,nq_30 +R 3000,5000,ref_ref,nq_25 +R 3000,4000,ref_ref,nq_20 +R 3000,3000,ref_ref,nq_15 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +R 5000,5000,ref_ref,i2_25 +R 5000,6000,ref_ref,i2_30 +R 5000,7000,ref_ref,i2_35 +R 4000,7000,ref_ref,i3_35 +S 1000,4100,1000,7900,300,i0,UP,CALU1 +S 2000,4100,2000,7900,300,i1,UP,CALU1 +S 3000,3100,3000,7900,300,nq,UP,CALU1 +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 4000,3100,4000,7900,300,i3,UP,CALU1 +S 5000,3100,5000,7900,300,i2,UP,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 3700,4000,4000,4000,400,*,RIGHT,POLY +S 2000,4000,2800,4000,400,*,RIGHT,POLY +S 6200,5500,6200,6700,600,*,UP,NTIE +S 6200,5900,6200,8900,300,*,UP,ALU1 +S 700,5700,700,9300,400,*,UP,PDIF +S 800,2000,5300,2000,300,*,RIGHT,ALU1 +S 5200,5700,5200,7300,600,*,UP,PDIF +S 5400,7500,5400,9300,600,*,UP,PDIF +S -300,7800,7300,7800,6000,*,RIGHT,NWELL +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 1800,5700,1800,9300,600,*,UP,PDIF +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 3000,5700,3000,9300,600,*,UP,PDIF +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 1200,2800,1200,5200,200,*,UP,POLY +S 2800,600,2800,2500,200,*,UP,NTRANS +S 4200,800,4200,2300,600,*,UP,NDIF +S 3700,600,3700,2500,200,*,UP,NTRANS +S 5400,800,5400,2300,600,*,UP,NDIF +S 4800,600,4800,2500,200,*,UP,NTRANS +S 2400,5100,2700,5100,200,*,RIGHT,POLY +S 1900,3000,3000,3000,300,*,RIGHT,ALU1 +S 5000,3100,5000,7900,300,*,UP,ALU1 +S 4000,3100,4000,7900,300,*,UP,ALU1 +S 1000,4100,1000,7900,300,*,UP,ALU1 +S 2000,4100,2000,7900,300,*,UP,ALU1 +S 4800,2800,4800,5200,200,*,UP,POLY +S 2400,5100,2400,5400,200,*,UP,POLY +S 3700,2800,3700,5000,200,*,UP,POLY +S 2800,2800,2800,5100,200,*,UP,POLY +S 3600,5100,3700,5100,200,*,RIGHT,POLY +S 700,800,700,2300,400,*,UP,NDIF +S 1200,600,1200,2500,200,*,UP,NTRANS +S 2000,800,2000,3100,600,*,UP,NDIF +S 3600,5100,3600,5400,200,*,UP,POLY +V 1000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 5400,9200,CONT_DIF_P,* +V 800,9200,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 2000,3000,CONT_DIF_N,* +V 3200,2000,CONT_DIF_N,* +V 6200,5800,CONT_BODY_N,* +V 3000,8000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 4300,900,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 5400,2000,CONT_DIF_N,* +V 3000,7000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/nao2o22_x1.vbe b/pdks/symbolic/nsxlib/cells/nao2o22_x1.vbe new file mode 100644 index 000000000..327e99763 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nao2o22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i3_nq : NATURAL := 174; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tphl_i2_nq : NATURAL := 237; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT tplh_i2_nq : NATURAL := 307; + CONSTANT tplh_i3_nq : NATURAL := 382; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x1; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/nao2o22_x4.ap b/pdks/symbolic/nsxlib/cells/nao2o22_x4.ap new file mode 100644 index 000000000..b47a83713 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nao2o22_x4.ap @@ -0,0 +1,143 @@ +V ALLIANCE : 6 +H nao2o22_x4,P,26/ 9/2019,100 +A 0,0,11000,10000 +R 4000,3000,ref_ref,i3_15 +R 4000,4000,ref_ref,i3_20 +R 4000,5000,ref_ref,i3_25 +R 4000,6000,ref_ref,i3_30 +R 5000,7000,ref_ref,i2_35 +R 4000,7000,ref_ref,i3_35 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +R 5000,4000,ref_ref,i2_20 +R 5000,3000,ref_ref,i2_15 +R 9000,8000,ref_ref,nq_40 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 9000,7000,ref_ref,nq_35 +R 9000,6000,ref_ref,nq_30 +R 9000,4000,ref_ref,nq_20 +R 9000,2000,ref_ref,nq_10 +R 9000,3000,ref_ref,nq_15 +R 9000,5000,ref_ref,nq_25 +R 1000,7000,ref_ref,i0_35 +R 1000,8000,ref_ref,i0_40 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +S 3700,3800,3700,4200,300,*,DOWN,POLY +S 9000,2100,9000,7900,300,nq,UP,CALU1 +S 5000,3100,5000,6900,300,i2,UP,CALU1 +S 4000,3100,4000,6900,300,i3,UP,CALU1 +S 2000,4100,2000,8000,300,i1,UP,CALU1 +S 1000,4100,1000,7900,300,i0,UP,CALU1 +S 5400,1700,5400,2300,600,*,UP,NDIF +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 2000,4100,2000,7900,300,*,UP,ALU1 +S 1000,4100,1000,7900,300,*,UP,ALU1 +S 1900,3000,2900,3000,300,*,RIGHT,ALU1 +S 4000,3100,4000,6900,300,*,UP,ALU1 +S 5000,3100,5000,6900,300,*,UP,ALU1 +S 9000,2100,9000,7900,300,*,UP,ALU1 +S 1200,6100,1400,6100,200,*,RIGHT,POLY +S 2400,6100,2600,6100,200,*,RIGHT,POLY +S 3500,6100,3600,6100,200,*,RIGHT,POLY +S 4600,6100,4900,6100,200,*,RIGHT,POLY +S 1200,2800,1200,6000,200,*,UP,POLY +S 2600,2800,2600,6000,200,*,UP,POLY +S 3500,2800,3500,6000,200,*,UP,POLY +S 4900,2800,4900,6000,200,*,UP,POLY +S 4600,6100,4600,6400,200,*,UP,POLY +S 3600,6100,3600,6400,200,*,UP,POLY +S 2400,6100,2400,6400,200,*,UP,POLY +S 7200,2800,7200,5200,200,*,UP,POLY +S 7600,5100,7600,6900,300,*,UP,ALU1 +S 7200,1500,7200,2500,200,*,UP,NTRANS +S 8400,5500,8400,9500,200,*,UP,PTRANS +S -300,7800,11300,7800,6000,*,RIGHT,NWELL +S 6600,2100,6600,5900,300,*,UP,ALU1 +S 6600,1700,6600,2300,600,*,UP,NDIF +S 6600,5700,6600,7300,600,*,UP,PDIF +S 7200,5500,7200,7500,200,*,UP,PTRANS +S 9000,5700,9000,9300,600,*,UP,PDIF +S 9600,5500,9600,9500,200,*,UP,PTRANS +S 8400,2800,8400,5200,200,*,UP,POLY +S 9600,2800,9600,5200,200,*,UP,POLY +S 6700,4000,7900,4000,300,*,RIGHT,ALU1 +S 3000,6700,3000,8300,600,*,UP,PDIF +S 3600,6500,3600,8500,200,*,UP,PTRANS +S 2400,6500,2400,8500,200,*,UP,PTRANS +S 3000,1700,3000,2300,600,*,UP,NDIF +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 5400,6700,5400,9100,600,*,UP,PDIF +S 1400,6100,1400,6400,200,*,UP,POLY +S 6700,7000,7500,7000,300,*,RIGHT,ALU1 +S 6600,7100,6600,7900,300,*,UP,ALU1 +S 3300,8000,6500,8000,300,*,RIGHT,ALU1 +S 10200,5700,10200,9300,400,*,UP,PDIF +S 10000,6100,10000,8900,300,*,UP,ALU1 +S 10000,1100,10000,1900,300,*,UP,ALU1 +S 8000,1100,8000,1900,300,*,UP,ALU1 +S 700,1700,700,2300,400,*,UP,NDIF +S 900,2000,5300,2000,300,*,RIGHT,ALU1 +S 2600,1500,2600,2500,200,*,UP,NTRANS +S 3500,1500,3500,2500,200,*,UP,NTRANS +S 4200,900,4200,2300,400,*,UP,NDIF +S 4900,1500,4900,2500,200,*,UP,NTRANS +S 700,6700,700,9100,400,*,UP,PDIF +S 1400,6500,1400,8500,200,*,UP,PTRANS +S 1800,6700,1800,8300,400,*,UP,PDIF +S 4600,6500,4600,8500,200,*,UP,PTRANS +S 4200,6700,4200,8300,400,*,UP,PDIF +S 8000,8100,8000,8900,300,*,UP,ALU1 +S 7900,5700,7900,9300,400,*,UP,PDIF +S 10200,800,10200,2300,400,*,UP,NDIF +S 9600,600,9600,2500,200,*,UP,NTRANS +S 8400,600,8400,2500,200,*,UP,NTRANS +S 9000,800,9000,2300,600,*,UP,NDIF +S 7900,800,7900,2300,400,*,UP,NDIF +S 1900,1700,1900,3100,600,*,UP,NDIF +S 2200,4000,2600,4000,400,*,RIGHT,POLY +S 3600,4000,4000,4000,400,*,RIGHT,POLY +S 8000,4000,9600,4000,400,*,RIGHT,POLY +S 7200,5000,7600,5000,400,*,RIGHT,POLY +S 0,600,11000,600,1200,vss,RIGHT,CALU1 +S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 +S 6600,8500,6600,9200,600,*,UP,NTIE +V 4000,4000,CONT_POLY,* +V 8000,9200,CONT_DIF_P,* +V 8000,900,CONT_DIF_N,* +V 10000,900,CONT_DIF_N,* +V 5400,9300,CONT_DIF_P,* +V 6000,800,CONT_BODY_P,* +V 9000,2000,CONT_DIF_N,* +V 3100,2000,CONT_DIF_N,* +V 4200,800,CONT_DIF_N,* +V 6600,9100,CONT_BODY_N,* +V 8000,8000,CONT_DIF_P,* +V 700,9200,CONT_DIF_P,* +V 1900,3000,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 8000,2000,CONT_DIF_N,* +V 10000,2000,CONT_DIF_N,* +V 10000,9200,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,6000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 6600,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 5400,2000,CONT_DIF_N,* +V 3000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 6600,6000,CONT_DIF_P,* +V 7800,4000,CONT_POLY,* +V 7800,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/nao2o22_x4.vbe b/pdks/symbolic/nsxlib/cells/nao2o22_x4.vbe new file mode 100644 index 000000000..b5c506fee --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i3_nq : NATURAL := 607; + CONSTANT tplh_i0_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 664; + CONSTANT tphl_i1_nq : NATURAL := 666; + CONSTANT tplh_i1_nq : NATURAL := 717; + CONSTANT tplh_i2_nq : NATURAL := 721; + CONSTANT tphl_i0_nq : NATURAL := 734; + CONSTANT tplh_i3_nq : NATURAL := 807; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/nmx2_x1.ap b/pdks/symbolic/nsxlib/cells/nmx2_x1.ap new file mode 100644 index 000000000..37e0440ca --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nmx2_x1.ap @@ -0,0 +1,98 @@ +V ALLIANCE : 6 +H nmx2_x1,P,25/ 9/2019,100 +A 0,0,7000,10000 +R 4000,3000,ref_ref,nq_15 +R 6000,3000,ref_ref,i1_15 +R 6000,4000,ref_ref,i1_20 +R 6000,5000,ref_ref,i1_25 +R 6000,6000,ref_ref,i1_30 +R 6000,7000,ref_ref,i1_35 +R 6000,8000,ref_ref,i1_40 +R 4000,7000,ref_ref,nq_35 +R 4000,6000,ref_ref,nq_30 +R 4000,5000,ref_ref,nq_25 +R 4000,4000,ref_ref,nq_20 +R 4000,2000,ref_ref,nq_10 +R 6000,2000,ref_ref,i1_10 +R 2000,7000,ref_ref,i0_35 +R 2000,6000,ref_ref,i0_30 +R 2000,5000,ref_ref,i0_25 +R 2000,4000,ref_ref,i0_20 +R 2000,3000,ref_ref,i0_15 +R 3000,5000,ref_ref,cmd_25 +R 3000,4000,ref_ref,cmd_20 +R 3000,7000,ref_ref,cmd_35 +R 3000,6000,ref_ref,cmd_30 +S 3000,2800,3400,2800,200,*,RIGHT,POLY +S 3400,2600,3400,2800,200,q,UP,POLY +S 2000,2800,2400,2800,200,*,RIGHT,POLY +S 2400,2500,2400,2800,200,*,UP,POLY +S 4600,5300,4600,5400,200,*,UP,POLY +S 4600,5200,5100,5200,200,*,RIGHT,POLY +S 1900,5200,2400,5200,200,*,RIGHT,POLY +S 2400,5200,2400,5500,200,*,UP,POLY +S 3200,5100,3400,5100,200,2,RIGHT,POLY +S 4000,5700,4000,9300,1000,*,UP,PDIF +S -300,7800,7300,7800,6000,*,RIGHT,NWELL +S 700,1700,700,2300,400,*,UP,NDIF +S 3200,4000,3200,5000,200,*,UP,POLY +S 3400,5100,3400,5400,200,*,UP,POLY +S 3000,2100,3000,2900,300,*,UP,ALU1 +S 1900,5700,1900,9300,400,*,UP,PDIF +S 6300,5700,6300,9300,400,*,UP,PDIF +S 700,2000,3000,2000,300,*,RIGHT,ALU1 +S 5000,5100,5000,7900,300,*,UP,ALU1 +S 900,8000,4900,8000,300,*,RIGHT,ALU1 +S 5800,5500,5800,9500,200,*,UP,PTRANS +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 3000,4100,3000,6900,300,*,UP,ALU1 +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 4000,4000,4000,6900,300,*,UP,ALU1 +S 5200,5700,5200,9300,400,*,UP,PDIF +S 4600,5500,4600,9500,200,*,UP,PTRANS +S 5800,2700,5800,3100,200,*,UP,POLY +S 5800,4900,5800,5300,200,*,UP,POLY +S 6300,800,6300,2300,400,*,UP,NDIF +S 5800,600,5800,2500,200,*,UP,NTRANS +S 4600,600,4600,2500,200,*,UP,NTRANS +S 5200,800,5200,2300,400,*,UP,NDIF +S 3400,600,3400,2500,200,*,UP,NTRANS +S 1900,800,1900,2300,400,*,UP,NDIF +S 4000,800,4000,2300,1000,*,UP,NDIF +S 2900,800,2900,2300,200,*,UP,NDIF +S 1200,4000,4600,4000,200,*,RIGHT,POLY +S 4600,2800,4600,4000,200,*,UP,POLY +S 3400,5500,3400,9500,200,*,UP,PTRANS +S 1200,2800,1200,6200,200,*,UP,POLY +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 700,6700,700,8300,400,*,UP,PDIF +S 800,2100,800,7900,300,*,UP,ALU1 +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 6000,2100,6000,7900,300,*,UP,ALU1 +S 2900,5700,2900,9300,200,*,UP,PDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 6000,2100,6000,7900,300,i1,UP,CALU1 +S 4000,2100,4000,4000,300,*,UP,ALU1 +S 4000,2100,4000,6900,300,nq,UP,CALU1 +S 3000,4100,3000,6900,300,cmd,UP,CALU1 +S 2000,3100,2000,6900,300,i0,UP,CALU1 +V 2000,900,CONT_DIF_N,* +V 6200,900,CONT_DIF_N,* +V 4000,7000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 2000,5000,CONT_POLY,* +V 4000,6000,CONT_DIF_P,* +V 5000,5000,CONT_POLY,* +V 4000,2000,CONT_DIF_N,* +V 2000,9200,CONT_DIF_P,* +V 6200,9200,CONT_DIF_P,* +V 3000,3000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 6000,3000,CONT_POLY,* +V 6000,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/nmx2_x1.vbe b/pdks/symbolic/nsxlib/cells/nmx2_x1.vbe new file mode 100644 index 000000000..3f0ab6425 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nmx2_x1.vbe @@ -0,0 +1,40 @@ +ENTITY nmx2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_cmd : NATURAL := 21; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 217; + CONSTANT tphl_i1_nq : NATURAL := 217; + CONSTANT tphl_cmd_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 256; + CONSTANT tplh_i1_nq : NATURAL := 256; + CONSTANT tplh_cmd_nq : NATURAL := 287; + CONSTANT tphh_cmd_nq : NATURAL := 379; + CONSTANT tpll_cmd_nq : NATURAL := 410; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x1; + +ARCHITECTURE behaviour_data_flow OF nmx2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x1" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/nmx2_x4.ap b/pdks/symbolic/nsxlib/cells/nmx2_x4.ap new file mode 100644 index 000000000..4b5568d8a --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nmx2_x4.ap @@ -0,0 +1,148 @@ +V ALLIANCE : 6 +H nmx2_x4,P,25/ 9/2019,100 +A 0,0,12000,10000 +R 2000,5000,ref_ref,i0_25 +R 2000,4000,ref_ref,i0_20 +R 2000,3000,ref_ref,i0_15 +R 3000,8000,ref_ref,cmd_40 +R 3000,7000,ref_ref,cmd_35 +R 3000,6000,ref_ref,cmd_30 +R 3000,5000,ref_ref,cmd_25 +R 3000,4000,ref_ref,cmd_20 +R 3000,3000,ref_ref,cmd_15 +R 10000,8000,ref_ref,nq_40 +R 10000,7000,ref_ref,nq_35 +R 2000,6000,ref_ref,i0_30 +R 2000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i0_40 +R 6000,2000,ref_ref,i1_10 +R 6000,3000,ref_ref,i1_15 +R 6000,4000,ref_ref,i1_20 +R 6000,5000,ref_ref,i1_25 +R 6000,6000,ref_ref,i1_30 +R 6000,7000,ref_ref,i1_35 +R 6000,8000,ref_ref,i1_40 +R 10000,5000,ref_ref,nq_25 +R 10000,2000,ref_ref,nq_10 +R 10000,6000,ref_ref,nq_30 +R 10000,4000,ref_ref,nq_20 +R 10000,3000,ref_ref,nq_15 +S 5600,6200,5600,6500,200,*,UP,POLY +S 5600,6200,6100,6200,200,*,RIGHT,POLY +S 4000,900,4000,1300,1000,*,UP,NDIF +S 6600,600,6600,1500,200,*,UP,NTRANS +S 6200,800,6200,1300,600,*,UP,NDIF +S 5700,600,5700,1500,200,*,UP,NTRANS +S 7400,800,7400,2100,600,*,UP,NDIF +S 1900,6100,2700,6100,200,*,RIGHT,POLY +S 3300,6100,3600,6100,200,*,RIGHT,POLY +S 6800,6100,7000,6100,200,*,RIGHT,POLY +S 1400,1600,1400,1900,200,*,UP,POLY +S 4000,800,4000,3100,600,*,UP,NDIF +S 3300,4000,3300,6000,200,*,UP,POLY +S 2700,6100,2700,6400,200,*,UP,POLY +S 3600,6100,3600,6400,200,*,UP,POLY +S 7000,6100,7000,6400,200,*,UP,POLY +S 6600,1900,6800,1900,200,*,RIGHT,POLY +S 6800,2000,6800,6000,200,*,UP,POLY +S 6600,1600,6600,1900,200,*,UP,POLY +S 1300,1900,1400,1900,200,*,RIGHT,POLY +S 10000,2100,10000,7900,300,*,UP,ALU1 +S 8800,1100,8800,1900,300,*,UP,ALU1 +S 11200,5700,11200,9300,400,*,UP,PDIF +S 11000,6100,11000,8900,300,*,UP,ALU1 +S 11200,700,11200,2300,400,*,UP,NDIF +S 11000,1100,11000,1900,300,*,UP,ALU1 +S 2300,1800,2300,2800,200,*,UP,POLY +S 2300,600,2300,1500,200,*,UP,NTRANS +S 1800,800,1800,1300,600,*,UP,NDIF +S 1400,600,1400,1500,200,*,UP,NTRANS +S 3200,600,3200,1500,200,*,UP,NTRANS +S 700,2000,4900,2000,300,*,RIGHT,ALU1 +S 2000,3100,2000,7900,300,*,UP,ALU1 +S 600,6700,600,8300,600,*,UP,PDIF +S 600,2100,600,7900,300,*,UP,ALU1 +S 4000,6700,4000,8300,1000,*,UP,PDIF +S 4000,3100,4000,7900,300,*,UP,ALU1 +S 5600,6500,5600,8500,200,*,UP,PTRANS +S 5000,2100,5000,5300,300,*,UP,ALU1 +S 4800,600,4800,1500,200,*,UP,NTRANS +S 1300,2000,1300,6200,200,*,UP,POLY +S 4800,1800,4800,4000,200,*,UP,POLY +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 6000,2100,6000,7900,300,*,UP,ALU1 +S -300,7800,12300,7800,6000,*,RIGHT,NWELL +S 7400,6700,7400,8300,600,*,UP,PDIF +S 7400,2100,7400,7900,300,*,UP,ALU1 +S 8800,6100,8800,8900,300,*,UP,ALU1 +S 9400,500,9400,2500,200,*,UP,NTRANS +S 10000,700,10000,2300,600,*,UP,NDIF +S 10600,500,10600,2500,200,*,UP,NTRANS +S 8800,700,8800,2300,600,*,UP,NDIF +S 7600,5000,10600,5000,200,*,RIGHT,POLY +S 9400,2800,9400,5200,200,*,UP,POLY +S 9400,5500,9400,9500,200,*,UP,PTRANS +S 10600,2800,10600,5200,200,*,UP,POLY +S 10600,5500,10600,9500,200,*,UP,PTRANS +S 8800,5700,8800,9300,600,*,UP,PDIF +S 10000,5700,10000,9300,600,*,UP,PDIF +S 5700,1800,5700,2800,200,*,UP,POLY +S 7000,6500,7000,8500,200,*,UP,PTRANS +S 6300,6700,6300,9100,400,*,UP,PDIF +S 4700,6500,4700,8500,200,*,UP,PTRANS +S 3600,6500,3600,8500,200,*,UP,PTRANS +S 2700,6500,2700,8500,200,*,UP,PTRANS +S 2000,6700,2000,9100,400,*,UP,PDIF +S 1300,6500,1300,8500,200,*,UP,PTRANS +S 1300,4000,4800,4000,200,*,RIGHT,POLY +S 4700,5300,4700,6200,200,*,UP,POLY +S 3900,4600,6800,4600,200,*,RIGHT,POLY +S 5700,2800,6100,2800,200,*,RIGHT,POLY +S 600,800,600,2100,600,*,UP,NDIF +S 1900,2800,2300,2800,200,*,RIGHT,POLY +S 3200,1700,3200,1900,200,*,UP,POLY +S 0,600,12000,600,1200,vss,RIGHT,CALU1 +S 0,9400,12000,9400,1200,vdd,RIGHT,CALU1 +S 10000,2100,10000,7900,300,nq,UP,CALU1 +S 6000,2100,6000,7900,300,i1,UP,CALU1 +S 3000,3100,3000,7900,300,cmd,UP,CALU1 +S 2000,3100,2000,7900,300,i0,UP,CALU1 +V 11000,8000,CONT_DIF_P,* +V 11000,9200,CONT_DIF_P,* +V 11000,2000,CONT_DIF_N,* +V 11000,800,CONT_DIF_N,* +V 2000,3000,CONT_POLY,* +V 600,8000,CONT_DIF_P,* +V 600,7000,CONT_DIF_P,* +V 11000,7000,CONT_DIF_P,* +V 11000,6000,CONT_DIF_P,* +V 6000,3000,CONT_POLY,* +V 8800,9100,CONT_DIF_P,* +V 1800,900,CONT_DIF_N,* +V 6200,900,CONT_DIF_N,* +V 8800,900,CONT_DIF_N,* +V 2000,9300,CONT_DIF_P,* +V 6300,9300,CONT_DIF_P,* +V 600,2000,CONT_DIF_N,* +V 10000,2000,CONT_DIF_N,* +V 8800,2000,CONT_DIF_N,* +V 8800,7000,CONT_DIF_P,* +V 8800,8000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 10000,6000,CONT_DIF_P,* +V 8800,6000,CONT_DIF_P,* +V 7600,5000,CONT_POLY,* +V 7400,6800,CONT_DIF_P,* +V 7400,8000,CONT_DIF_P,* +V 7400,2000,CONT_DIF_N,* +V 4000,3000,CONT_DIF_N,* +V 4000,7000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 5000,5400,CONT_POLY,* +V 4000,4800,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 3200,2000,CONT_POLY,* +V 6000,6000,CONT_POLY,* +V 2000,6000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/nmx2_x4.vbe b/pdks/symbolic/nsxlib/cells/nmx2_x4.vbe new file mode 100644 index 000000000..436a6b355 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nmx2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY nmx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_cmd_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 610; + CONSTANT tphl_cmd_nq : NATURAL := 632; + CONSTANT tplh_i0_nq : NATURAL := 653; + CONSTANT tplh_i1_nq : NATURAL := 653; + CONSTANT tphh_cmd_nq : NATURAL := 688; + CONSTANT tpll_cmd_nq : NATURAL := 703; + CONSTANT tplh_cmd_nq : NATURAL := 708; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x4; + +ARCHITECTURE behaviour_data_flow OF nmx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x4" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/nmx3_x1.ap b/pdks/symbolic/nsxlib/cells/nmx3_x1.ap new file mode 100644 index 000000000..cd0e3f118 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nmx3_x1.ap @@ -0,0 +1,158 @@ +V ALLIANCE : 6 +H nmx3_x1,P,26/ 9/2019,100 +A 0,0,12000,10000 +R 9000,5000,ref_ref,i0_25 +R 9000,6000,ref_ref,i0_30 +R 9000,4000,ref_ref,i0_20 +R 11000,4000,ref_ref,nq_20 +R 11000,3000,ref_ref,nq_15 +R 11000,7000,ref_ref,nq_35 +R 1000,3000,ref_ref,cmd1_15 +R 1000,4000,ref_ref,cmd1_20 +R 1000,5000,ref_ref,cmd1_25 +R 1000,6000,ref_ref,cmd1_30 +R 1000,7000,ref_ref,cmd1_35 +R 7000,6000,ref_ref,cmd0_30 +R 7000,5000,ref_ref,cmd0_25 +R 7000,4000,ref_ref,cmd0_20 +R 5000,5000,ref_ref,i1_25 +R 3000,5000,ref_ref,i2_25 +R 11000,2000,ref_ref,nq_10 +R 11000,6000,ref_ref,nq_30 +R 11000,5000,ref_ref,nq_25 +S 9000,4400,9000,6000,300,*,UP,ALU1 +S 7000,4100,7000,6000,300,cmd0,UP,CALU1 +S 1000,3000,1000,7000,300,cmd1,UP,CALU1 +S 9000,5000,9000,5000,300,i0,LEFT,CALU1 +S 9000,5000,9000,6000,400,i0,UP,CALU1 +S 5000,5000,5000,5000,300,i1,LEFT,CALU1 +S 3000,5000,3000,5000,300,i2,LEFT,CALU1 +S 11000,2000,11000,7000,300,nq,UP,CALU1 +S 0,9400,12000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,12000,600,1200,vss,RIGHT,CALU1 +S 1800,2900,1800,3700,200,*,UP,NTRANS +S 4000,4000,5100,4000,200,*,RIGHT,POLY +S 3700,2600,3700,3000,200,*,UP,POLY +S 3700,1100,3700,2300,200,*,UP,NTRANS +S 6500,1300,6500,2100,400,*,UP,NDIF +S 9000,2200,9000,4000,200,*,UP,POLY +S 8100,2200,8100,3000,200,*,UP,POLY +S 8300,7500,8300,9500,200,*,UP,PTRANS +S 3800,7100,3800,7400,200,*,UP,POLY +S 2900,1100,2900,2300,200,*,UP,NTRANS +S 2900,2600,2900,4700,200,*,UP,POLY +S 3000,5100,3000,7000,200,*,UP,POLY +S 10200,2900,10200,3700,200,*,UP,NTRANS +S 10200,4000,10200,5000,200,*,UP,POLY +S 8000,5000,10300,5000,200,*,RIGHT,POLY +S 8000,3800,8000,6600,200,*,UP,POLY +S 5000,5000,6000,5000,200,*,RIGHT,POLY +S 1000,5700,1000,7900,600,*,UP,PDIF +S 4600,7100,4600,9300,600,*,UP,PDIF +S 3400,7700,3400,9300,400,*,UP,PDIF +S 2800,7500,2800,9500,200,*,UP,PTRANS +S 2200,7700,2200,9300,600,*,UP,PDIF +S 9800,7700,9800,9300,600,*,UP,PDIF +S 7800,7700,7800,9300,400,*,UP,PDIF +S 1000,900,1000,1900,300,*,UP,ALU1 +S 1000,8100,1000,9100,300,*,UP,ALU1 +S 7000,4100,7000,5900,300,*,UP,ALU1 +S 11000,1100,11000,3500,600,*,UP,NDIF +S -300,7800,12300,7800,6000,*,RIGHT,NWELL +S 2200,3100,2200,3500,600,*,UP,NDIF +S 1000,2100,1000,3500,600,*,UP,NDIF +S 2300,2000,6500,2000,300,*,RIGHT,ALU1 +S 3000,4300,3000,4900,300,*,UP,ALU1 +S 4100,5000,4900,5000,300,*,RIGHT,ALU1 +S 2300,8000,6500,8000,300,*,RIGHT,ALU1 +S 4700,7000,10900,7000,300,*,RIGHT,ALU1 +S 7000,7100,7400,7100,200,*,RIGHT,POLY +S 4500,1300,4500,3100,600,*,UP,NDIF +S 2800,7100,2800,7400,200,*,UP,POLY +S 7200,2000,7200,2300,200,*,UP,POLY +S 9200,7100,9200,7400,200,*,UP,POLY +S 7600,2400,7600,3800,200,*,UP,POLY +S 6000,2600,6000,7000,200,*,UP,POLY +S 7000,3000,7000,7000,200,*,UP,POLY +S 8000,6600,8000,7000,200,*,UP,POLY +S 7700,1200,7700,1600,400,*,UP,ALU1 +S 9000,700,9000,1900,200,*,UP,NTRANS +S 8100,700,8100,1900,200,*,UP,NTRANS +S 9800,900,9800,1900,600,*,UP,NDIF +S 7200,700,7200,1900,200,*,UP,NTRANS +S 6000,1100,6000,2300,200,*,UP,NTRANS +S 2200,5700,2200,6700,600,*,UP,PDIF +S 7800,900,7800,1700,400,*,UP,NDIF +S 9800,5700,9800,6700,600,*,UP,PDIF +S 8000,7100,8300,7100,200,*,RIGHT,POLY +S 8900,7100,9200,7100,200,*,RIGHT,POLY +S 7200,2300,7600,2300,200,*,RIGHT,POLY +S 2200,1500,2200,2100,600,*,UP,NDIF +S 5200,1100,5200,2300,200,*,UP,NTRANS +S 8900,6000,8900,7000,200,*,UP,POLY +S 9200,7500,9200,9500,200,*,UP,PTRANS +S 7400,7500,7400,9500,200,*,UP,PTRANS +S 6400,7500,6400,9500,200,*,UP,PTRANS +S 5400,7500,5400,9500,200,*,UP,PTRANS +S 3800,7500,3800,9500,200,*,UP,PTRANS +S 1800,5500,1800,6900,200,*,UP,PTRANS +S 1800,4000,1800,5200,200,*,UP,POLY +S 7600,3800,8000,3800,200,*,RIGHT,POLY +S 7100,5000,7700,5000,300,*,RIGHT,ALU1 +S 4600,3100,4600,3900,300,*,UP,ALU1 +S 1100,7000,3500,7000,300,*,RIGHT,ALU1 +S 2100,6000,4900,6000,300,*,RIGHT,ALU1 +S 2100,3000,3500,3000,300,*,RIGHT,ALU1 +S 2000,3100,2000,5900,300,*,UP,ALU1 +S 8300,7100,8300,7400,200,*,UP,POLY +S 7400,7100,7400,7400,200,*,UP,POLY +S 6400,7100,6400,7400,200,*,UP,POLY +S 5400,7100,5400,7400,200,*,UP,POLY +S 10400,5000,10400,5400,200,*,UP,POLY +S 6000,7100,6400,7100,200,*,RIGHT,POLY +S 5200,5900,5200,7100,200,*,UP,POLY +S 5200,7100,5400,7100,200,*,RIGHT,POLY +S 3800,4000,3800,7000,200,*,UP,POLY +S 2800,7100,3000,7100,200,*,RIGHT,POLY +S 9800,3100,9800,3500,600,*,UP,NDIF +S 6900,3000,9900,3000,300,*,RIGHT,ALU1 +S 10000,3100,10000,5900,300,*,UP,ALU1 +S 9800,7100,9800,7900,300,*,UP,ALU1 +S 10400,5500,10400,6900,200,*,UP,PTRANS +S 4700,4000,5900,4000,300,*,RIGHT,ALU1 +S 6000,4100,6000,6900,300,*,UP,ALU1 +S 9900,2000,10900,2000,300,*,RIGHT,ALU1 +S 1000,5000,1600,5000,400,*,RIGHT,POLY +S 5200,2600,5200,4000,200,*,UP,POLY +S 11100,8100,11100,9300,300,*,UP,ALU1 +S 11100,5700,11100,7900,400,*,UP,PDIF +V 9000,4000,CONT_POLY,* +V 9000,6000,CONT_POLY,* +V 10000,5900,CONT_DIF_P,* +V 4500,3000,CONT_DIF_N,* +V 7800,9200,CONT_DIF_P,* +V 9800,3200,CONT_DIF_N,* +V 2200,3200,CONT_DIF_N,* +V 3600,7000,CONT_POLY,* +V 8400,3000,CONT_POLY,* +V 6800,3000,CONT_POLY,* +V 3600,3000,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 9800,2000,CONT_DIF_N,* +V 2200,2000,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 4600,7000,CONT_DIF_P,* +V 2200,8000,CONT_DIF_P,* +V 9800,8000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 2200,6000,CONT_DIF_P,* +V 5000,6000,CONT_POLY,* +V 7800,5000,CONT_POLY,* +V 7700,1600,CONT_DIF_N,* +V 6400,2000,CONT_DIF_N,* +V 6800,8000,CONT_DIF_P,* +V 11000,900,CONT_DIF_N,* +V 11100,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/nmx3_x1.vbe b/pdks/symbolic/nsxlib/cells/nmx3_x1.vbe new file mode 100644 index 000000000..1853919ce --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nmx3_x1.vbe @@ -0,0 +1,55 @@ +ENTITY nmx3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 7420; + CONSTANT rdown_cmd1_nq : NATURAL := 7420; + CONSTANT rdown_i0_nq : NATURAL := 5140; + CONSTANT rdown_i1_nq : NATURAL := 7420; + CONSTANT rdown_i2_nq : NATURAL := 7420; + CONSTANT rup_cmd0_nq : NATURAL := 9760; + CONSTANT rup_cmd1_nq : NATURAL := 9760; + CONSTANT rup_i0_nq : NATURAL := 6680; + CONSTANT rup_i1_nq : NATURAL := 9760; + CONSTANT rup_i2_nq : NATURAL := 9760; + CONSTANT tphl_i0_nq : NATURAL := 315; + CONSTANT tphl_cmd0_nq : NATURAL := 356; + CONSTANT tphl_cmd1_nq : NATURAL := 414; + CONSTANT tphl_i1_nq : NATURAL := 429; + CONSTANT tphl_i2_nq : NATURAL := 429; + CONSTANT tplh_i0_nq : NATURAL := 441; + CONSTANT tplh_cmd0_nq : NATURAL := 495; + CONSTANT tphh_cmd1_nq : NATURAL := 519; + CONSTANT tpll_cmd1_nq : NATURAL := 520; + CONSTANT tplh_cmd1_nq : NATURAL := 566; + CONSTANT tphh_cmd0_nq : NATURAL := 582; + CONSTANT tplh_i1_nq : NATURAL := 582; + CONSTANT tplh_i2_nq : NATURAL := 582; + CONSTANT tpll_cmd0_nq : NATURAL := 586; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x1; + +ARCHITECTURE behaviour_data_flow OF nmx3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx3_x1" + SEVERITY WARNING; + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not + (cmd1) and i2))))) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/no2_x1.ap b/pdks/symbolic/nsxlib/cells/no2_x1.ap new file mode 100644 index 000000000..659466548 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no2_x1.ap @@ -0,0 +1,55 @@ +V ALLIANCE : 6 +H no2_x1,P,18/ 9/2019,100 +A 0,0,4000,10000 +R 1000,7000,ref_ref,nq_35 +R 1000,8000,ref_ref,nq_40 +R 1000,2000,ref_ref,nq_10 +R 3000,5000,ref_ref,i0_25 +R 3000,4000,ref_ref,i0_20 +R 3000,3000,ref_ref,i0_15 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 1000,6000,ref_ref,nq_30 +R 1000,5000,ref_ref,nq_25 +R 1000,4000,ref_ref,nq_20 +R 1000,3000,ref_ref,nq_15 +R 2000,8000,ref_ref,i1_40 +R 3000,8000,ref_ref,i0_40 +R 3000,7000,ref_ref,i0_35 +R 3000,6000,ref_ref,i0_30 +S 1000,2100,1000,7900,300,nq,UP,CALU1 +S 2000,3100,2000,7900,300,i1,UP,CALU1 +S 3000,3100,3000,7900,300,i0,UP,CALU1 +S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,4000,600,1200,vss,RIGHT,CALU1 +S 1000,1100,1000,2300,400,*,UP,NDIF +S 2700,1500,2700,2500,200,*,UP,NTRANS +S 2700,4200,2700,5300,200,*,UP,POLY +S 2700,2800,2700,4200,200,*,UP,POLY +S 2700,5500,2700,9500,200,*,UP,PTRANS +S 1400,5700,1400,8300,400,*,UP,PDIF +S 1700,5500,1700,9500,200,*,UP,PTRANS +S 1700,1500,1700,2500,200,*,UP,NTRANS +S 3200,1200,3200,2000,300,*,UP,ALU1 +S 1100,2000,2200,2000,300,*,RIGHT,ALU1 +S 3300,1700,3300,2300,400,*,UP,NDIF +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 1000,2100,1000,7900,300,*,UP,ALU1 +S -300,7800,4300,7800,6000,*,RIGHT,NWELL +S 1000,5700,1000,8300,600,*,UP,PDIF +S 2000,3100,2000,7900,300,*,UP,ALU1 +S 3300,5700,3300,9300,400,*,UP,PDIF +S 1700,2800,1700,5200,200,*,UP,POLY +V 2100,2000,CONT_DIF_N,* +V 3200,2000,CONT_DIF_N,* +V 1000,8000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1000,6000,CONT_DIF_P,* +V 2000,5000,CONT_POLY,* +V 1000,800,CONT_DIF_N,* +V 3000,4000,CONT_POLY,* +V 3200,9200,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/no2_x1.vbe b/pdks/symbolic/nsxlib/cells/no2_x1.vbe new file mode 100644 index 000000000..37a91f3f6 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tplh_i0_nq : NATURAL := 121; + CONSTANT tplh_i1_nq : NATURAL := 161; + CONSTANT tphl_i1_nq : NATURAL := 193; + CONSTANT tphl_i0_nq : NATURAL := 298; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x1; + +ARCHITECTURE behaviour_data_flow OF no2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x1" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 900 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/no2_x4.ap b/pdks/symbolic/nsxlib/cells/no2_x4.ap new file mode 100644 index 000000000..d79644059 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no2_x4.ap @@ -0,0 +1,93 @@ +V ALLIANCE : 6 +H no2_x4,P,26/ 9/2019,100 +A 0,0,7000,10000 +R 4000,5000,ref_ref,nq_25 +R 4000,4000,ref_ref,nq_20 +R 4000,3000,ref_ref,nq_15 +R 1000,4000,ref_ref,i1_20 +R 1000,5000,ref_ref,i1_25 +R 1000,6000,ref_ref,i1_30 +R 1000,7000,ref_ref,i1_35 +R 2000,5000,ref_ref,i0_25 +R 2000,4000,ref_ref,i0_20 +R 2000,3000,ref_ref,i0_15 +R 1000,3000,ref_ref,i1_15 +R 4000,6000,ref_ref,nq_30 +R 4000,7000,ref_ref,nq_35 +R 2000,7000,ref_ref,i0_35 +R 2000,6000,ref_ref,i0_30 +S 4000,3100,4000,6900,300,nq,UP,CALU1 +S 4000,2100,4000,6900,300,*,UP,ALU1 +S 2000,3100,2000,6900,300,i0,UP,CALU1 +S 1000,3100,1000,6900,300,i1,UP,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S -300,7800,7300,7800,6000,*,RIGHT,NWELL +S 5800,5500,5800,7500,200,*,UP,PTRANS +S 4000,5700,4000,9300,600,*,UP,PDIF +S 3400,5500,3400,9500,200,*,UP,PTRANS +S 4600,5500,4600,9500,200,*,UP,PTRANS +S 5800,1500,5800,2500,200,*,UP,NTRANS +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 5200,1200,5200,2000,400,*,UP,ALU1 +S 5200,5000,5800,5000,400,*,RIGHT,POLY +S 3400,4100,3400,5200,200,*,UP,POLY +S 3800,2800,3800,3900,200,*,UP,POLY +S 2400,1500,2400,2500,200,*,UP,NTRANS +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 700,8000,5300,8000,300,*,RIGHT,ALU1 +S 5400,5100,5400,7900,300,*,UP,ALU1 +S 5800,2800,5800,5200,200,*,UP,POLY +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 3800,600,3800,2500,200,*,UP,NTRANS +S 1400,2900,1500,2900,200,*,RIGHT,POLY +S 2100,5100,2100,5300,200,*,UP,POLY +S 4600,4100,4600,5200,200,*,UP,POLY +S 1000,1100,1000,1900,300,*,UP,ALU1 +S 2100,5500,2100,9500,200,*,UP,PTRANS +S 2800,5700,2800,9300,400,*,UP,PDIF +S 2600,5700,2600,9300,600,*,UP,PDIF +S 600,5700,600,9300,400,*,UP,PDIF +S 800,800,800,2300,400,*,UP,NDIF +S 1900,4800,2400,4800,200,*,RIGHT,POLY +S 1200,2900,1200,5300,200,*,UP,POLY +S 1500,2400,1500,2800,200,*,UP,POLY +S 6200,8200,6200,9200,600,*,UP,NTIE +S 2400,2800,2400,4800,200,*,UP,POLY +S 1900,2000,2900,2000,300,*,RIGHT,ALU1 +S 4200,800,4200,2300,400,*,UP,NDIF +S 5100,800,5100,2300,400,*,UP,NDIF +S 4700,600,4700,2500,200,*,UP,NTRANS +S 3200,800,3200,2300,600,*,UP,NDIF +S 6400,5700,6400,7300,400,*,UP,PDIF +S 6200,6100,6200,6900,300,*,UP,ALU1 +S 6200,2100,6200,5900,300,*,UP,ALU1 +S 5100,4000,6200,4000,300,*,RIGHT,ALU1 +S 5100,5700,5100,9300,400,*,UP,PDIF +S 6300,1700,6300,2300,400,*,UP,NDIF +S 1500,1500,1500,2500,200,*,UP,NTRANS +S 3400,4000,5200,4000,200,*,RIGHT,POLY +S 4600,3400,4600,4000,200,*,UP,POLY +S 4700,2700,4700,3300,200,*,UP,POLY +S 4600,3300,4700,3300,200,*,LEFT,POLY +V 1000,4000,CONT_POLY,* +V 5200,2000,CONT_DIF_N,* +V 6200,9100,CONT_BODY_N,* +V 700,800,CONT_DIF_N,* +V 4200,2000,CONT_DIF_N,* +V 2000,5000,CONT_POLY,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 6200,7000,CONT_DIF_P,* +V 6200,6000,CONT_DIF_P,* +V 6200,2000,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 1900,2000,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,* +V 3300,900,CONT_DIF_N,* +V 2800,9100,CONT_DIF_P,* +V 5000,9100,CONT_DIF_P,* +V 5200,4000,CONT_POLY,* +V 5200,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/no2_x4.vbe b/pdks/symbolic/nsxlib/cells/no2_x4.vbe new file mode 100644 index 000000000..5060db0e8 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tplh_i0_nq : NATURAL := 447; + CONSTANT tplh_i1_nq : NATURAL := 504; + CONSTANT tphl_i1_nq : NATURAL := 522; + CONSTANT tphl_i0_nq : NATURAL := 618; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x4; + +ARCHITECTURE behaviour_data_flow OF no2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x4" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/no3_x1.ap b/pdks/symbolic/nsxlib/cells/no3_x1.ap new file mode 100644 index 000000000..962f1483e --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no3_x1.ap @@ -0,0 +1,74 @@ +V ALLIANCE : 6 +H no3_x1,P,25/ 9/2019,100 +A 0,0,5000,10000 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 2000,8000,ref_ref,i1_40 +R 1000,3000,ref_ref,nq_15 +R 1000,4000,ref_ref,nq_20 +R 1000,5000,ref_ref,nq_25 +R 1000,6000,ref_ref,nq_30 +R 1000,7000,ref_ref,nq_35 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 1000,8000,ref_ref,nq_40 +R 4000,2000,ref_ref,i2_10 +R 2000,4000,ref_ref,i1_20 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 3000,8000,ref_ref,i0_40 +S 3600,2500,3600,2700,200,*,UP,POLY +S 3600,2800,4100,2800,200,*,RIGHT,POLY +S 2600,3800,3100,3800,200,*,RIGHT,POLY +S 2000,4100,2000,7900,300,*,UP,ALU1 +S 3000,4100,3000,7900,300,*,UP,ALU1 +S 1900,1700,1900,2300,400,*,UP,NDIF +S 3100,2000,3100,3000,300,*,UP,ALU1 +S 4000,2100,4000,7900,300,*,UP,ALU1 +S 3700,5500,3700,9500,200,*,UP,PTRANS +S 1900,5500,1900,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,400,*,UP,PDIF +S 1400,5700,1400,8300,400,*,UP,PDIF +S 1000,3000,3000,3000,300,*,RIGHT,ALU1 +S -300,7800,5300,7800,6000,*,RIGHT,NWELL +S 2800,4000,2800,5200,200,*,UP,POLY +S 1000,5700,1000,8300,600,*,UP,PDIF +S 2800,5500,2800,9500,200,*,UP,PTRANS +S 1000,2100,1000,7900,300,*,UP,ALU1 +S 3600,1500,3600,2500,200,*,UP,NTRANS +S 2600,1500,2600,2500,200,*,UP,NTRANS +S 3100,1700,3100,2300,600,*,UP,NDIF +S 2600,2800,2600,3800,200,*,UP,POLY +S 700,1700,700,2300,400,*,UP,NDIF +S 4300,800,4300,2300,400,*,UP,NDIF +S 1400,1500,1400,2500,200,*,UP,NTRANS +S 1400,2800,1400,4800,200,*,UP,POLY +S 2000,1200,2000,1900,300,*,UP,ALU1 +S 1900,5100,1900,5300,200,*,UP,POLY +S 3700,3000,3700,5200,200,*,UP,POLY +S 1400,4900,2100,4900,200,*,RIGHT,POLY +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 2000,4100,2000,7900,300,i1,UP,CALU1 +S 4000,2100,4000,7900,300,i2,UP,CALU1 +S 3000,4100,3000,7900,300,i0,UP,CALU1 +S 1000,2100,1000,7900,300,nq,UP,CALU1 +V 4100,9200,CONT_DIF_P,* +V 1000,6000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 2000,5000,CONT_POLY,* +V 4000,3000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 3100,2000,CONT_DIF_N,* +V 4200,800,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/no3_x1.vbe b/pdks/symbolic/nsxlib/cells/no3_x1.vbe new file mode 100644 index 000000000..6711f8b1f --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT tplh_i2_nq : NATURAL := 192; + CONSTANT tphl_i1_nq : NATURAL := 215; + CONSTANT tplh_i1_nq : NATURAL := 243; + CONSTANT tplh_i0_nq : NATURAL := 246; + CONSTANT tphl_i0_nq : NATURAL := 318; + CONSTANT tphl_i2_nq : NATURAL := 407; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x1; + +ARCHITECTURE behaviour_data_flow OF no3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/no3_x4.ap b/pdks/symbolic/nsxlib/cells/no3_x4.ap new file mode 100644 index 000000000..6e3d0cfa5 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no3_x4.ap @@ -0,0 +1,104 @@ +V ALLIANCE : 6 +H no3_x4,P,26/ 9/2019,100 +A 0,0,8000,10000 +R 5000,3000,ref_ref,nq_15 +R 5000,4000,ref_ref,nq_20 +R 5000,5000,ref_ref,nq_25 +R 1000,3000,ref_ref,i2_15 +R 1000,7000,ref_ref,i2_35 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 5000,7000,ref_ref,nq_35 +R 5000,6000,ref_ref,nq_30 +R 1000,4000,ref_ref,i2_20 +R 3000,3000,ref_ref,i0_15 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 1000,6000,ref_ref,i2_30 +R 1000,5000,ref_ref,i2_25 +S 5000,3100,5000,6900,300,nq,UP,CALU1 +S 1000,3100,1000,6900,300,i2,UP,CALU1 +S 2000,3100,2000,6900,300,i1,UP,CALU1 +S 3000,3100,3000,6900,300,i0,UP,CALU1 +S 1700,1700,1700,2300,400,*,UP,NDIF +S 4400,4000,6200,4000,400,*,RIGHT,POLY +S 4400,4100,4400,5200,200,*,UP,POLY +S 4800,2800,4800,3900,200,*,UP,POLY +S 5600,4000,5600,5200,200,*,UP,POLY +S 6200,5000,6800,5000,400,*,RIGHT,POLY +S 3000,5100,3000,5300,200,*,UP,POLY +S 1100,2700,1100,2900,200,*,UP,POLY +S 3800,2100,3800,7900,300,*,UP,ALU1 +S 700,2000,3800,2000,300,*,RIGHT,ALU1 +S 1100,2900,1100,5200,200,*,UP,POLY +S 2900,4800,3600,4800,200,*,RIGHT,POLY +S 2000,2900,2600,2900,200,*,RIGHT,POLY +S 2000,3000,2000,5200,200,*,UP,POLY +S 2600,2600,2600,2900,200,*,UP,POLY +S 1100,1500,1100,2500,200,*,UP,NTRANS +S -300,7800,8300,7800,6000,*,RIGHT,NWELL +S 3800,5700,3800,9300,600,*,UP,PDIF +S 6800,5500,6800,7500,200,*,UP,PTRANS +S 5000,5700,5000,9300,600,*,UP,PDIF +S 4400,5500,4400,9500,200,*,UP,PTRANS +S 5600,5500,5600,9500,200,*,UP,PTRANS +S 700,8000,6300,8000,300,*,RIGHT,ALU1 +S 6800,2800,6800,5200,200,*,UP,POLY +S 6400,5100,6400,7900,300,*,UP,ALU1 +S 5000,2000,5000,6900,300,*,UP,ALU1 +S 7400,5700,7400,7300,400,*,UP,PDIF +S 7200,2100,7200,5900,300,*,UP,ALU1 +S 6100,4000,7100,4000,300,*,RIGHT,ALU1 +S 3400,5700,3400,9300,600,*,UP,PDIF +S 3000,3100,3000,6900,300,*,UP,ALU1 +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 3600,2800,3600,4800,200,*,UP,POLY +S 6800,1500,6800,2500,200,*,UP,NTRANS +S 3600,1500,3600,2500,200,*,UP,NTRANS +S 2000,5500,2000,9500,200,*,UP,PTRANS +S 600,5700,600,9300,600,*,UP,PDIF +S 3000,1700,3000,2300,600,*,UP,NDIF +S 7300,1700,7300,2300,400,*,UP,NDIF +S 2600,1500,2600,2500,200,*,UP,NTRANS +S 6100,5700,6100,9300,400,*,UP,PDIF +S 6100,800,6100,1600,300,*,UP,ALU1 +S 6100,800,6100,2300,400,*,UP,NDIF +S 5700,600,5700,2500,200,*,UP,NTRANS +S 5200,800,5200,2300,400,*,UP,NDIF +S 4300,800,4300,2300,400,*,UP,NDIF +S 4800,600,4800,2500,200,*,UP,NTRANS +S 3000,5500,3000,9500,200,*,UP,PTRANS +S 1100,5500,1100,9500,200,*,UP,PTRANS +S 600,1700,600,2300,400,*,UP,NDIF +S 1900,900,1900,2300,400,*,UP,NDIF +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 7200,8400,7200,9000,600,*,UP,NTIE +S 5600,2800,5600,3900,200,*,UP,POLY +S 5600,2800,5700,2800,200,*,RIGHT,POLY +V 700,2000,CONT_DIF_N,* +V 6200,2000,CONT_DIF_N,* +V 6000,9100,CONT_DIF_P,* +V 3800,9100,CONT_DIF_P,* +V 7200,6000,CONT_DIF_P,* +V 7200,2000,CONT_DIF_N,* +V 5200,2000,CONT_DIF_N,* +V 3000,5000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 600,8000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 1900,800,CONT_DIF_N,* +V 7200,9100,CONT_BODY_N,* +V 1000,3000,CONT_POLY,* +V 6200,5000,CONT_POLY,* +V 6200,4000,CONT_POLY,* +V 4400,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/no3_x4.vbe b/pdks/symbolic/nsxlib/cells/no3_x4.vbe new file mode 100644 index 000000000..52e3d602b --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 545; + CONSTANT tplh_i0_nq : NATURAL := 561; + CONSTANT tplh_i1_nq : NATURAL := 623; + CONSTANT tphl_i1_nq : NATURAL := 638; + CONSTANT tplh_i2_nq : NATURAL := 640; + CONSTANT tphl_i0_nq : NATURAL := 722; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x4; + +ARCHITECTURE behaviour_data_flow OF no3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/no4_x1.ap b/pdks/symbolic/nsxlib/cells/no4_x1.ap new file mode 100644 index 000000000..dc6553011 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no4_x1.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 6 +H no4_x1,P,25/ 9/2019,100 +A 0,0,6000,10000 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 4000,8000,ref_ref,i2_40 +R 4000,7000,ref_ref,i2_35 +R 2000,4000,ref_ref,i1_20 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 5000,8000,ref_ref,i3_40 +R 5000,7000,ref_ref,i3_35 +R 5000,6000,ref_ref,i3_30 +R 5000,5000,ref_ref,i3_25 +R 5000,4000,ref_ref,i3_20 +R 5000,3000,ref_ref,i3_15 +R 1000,8000,ref_ref,nq_40 +R 1000,3000,ref_ref,nq_15 +R 1000,4000,ref_ref,nq_20 +R 1000,5000,ref_ref,nq_25 +R 1000,6000,ref_ref,nq_30 +R 1000,7000,ref_ref,nq_35 +R 3000,8000,ref_ref,i0_40 +R 4000,4000,ref_ref,i2_20 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +S 2600,3800,3100,3800,200,*,RIGHT,POLY +S 1800,3000,4100,3000,300,*,RIGHT,ALU1 +S 4000,4100,4000,7900,300,*,UP,ALU1 +S 2000,4100,2000,7900,300,*,UP,ALU1 +S 5300,1700,5300,2300,400,*,UP,NDIF +S 4500,5100,4800,5100,200,*,RIGHT,POLY +S 3700,2700,3700,5100,200,*,UP,POLY +S 3600,5100,3700,5100,200,*,RIGHT,POLY +S 4800,2800,4800,5000,200,*,UP,POLY +S 4500,5100,4500,5400,200,*,UP,POLY +S 4200,2000,4200,3000,300,*,UP,ALU1 +S 1000,1200,1000,2000,300,*,UP,ALU1 +S 1400,4800,2000,4800,200,*,RIGHT,POLY +S 3200,1700,3200,2300,400,*,UP,NDIF +S 2000,2000,2000,3000,300,*,UP,ALU1 +S 3200,1300,3200,2000,300,*,UP,ALU1 +S 2600,2800,2600,3800,200,*,UP,POLY +S 2600,1500,2600,2500,200,*,UP,NTRANS +S 1000,3000,1600,3000,300,*,RIGHT,ALU1 +S 3600,5100,3600,5400,200,*,UP,POLY +S 2700,4000,2700,5200,200,*,UP,POLY +S 4500,5500,4500,9500,200,*,UP,PTRANS +S 2700,5500,2700,9500,200,*,UP,PTRANS +S 1400,2800,1400,4800,200,*,UP,POLY +S 1400,1500,1400,2500,200,*,UP,NTRANS +S 3700,1500,3700,2500,200,*,UP,NTRANS +S 5200,1200,5200,1900,400,*,UP,ALU1 +S -300,7800,6300,7800,6000,*,RIGHT,NWELL +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 1000,5700,1000,8300,600,*,UP,PDIF +S 1400,5700,1400,8300,600,*,UP,PDIF +S 1800,1700,1800,2300,600,*,UP,NDIF +S 4200,1700,4200,2300,600,*,UP,NDIF +S 5000,5700,5000,9300,600,*,UP,PDIF +S 4800,1500,4800,2500,200,*,UP,NTRANS +S 5000,3100,5000,7900,300,*,UP,ALU1 +S 1900,5500,1900,9500,200,*,UP,PTRANS +S 1900,5100,1900,5300,200,*,UP,POLY +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 1000,3100,1000,7900,300,*,UP,ALU1 +S 1000,3100,1000,7900,300,nq,UP,CALU1 +S 2000,4100,2000,7900,300,i1,UP,CALU1 +S 5000,3100,5000,7900,300,i3,UP,CALU1 +S 4000,4100,4000,7900,300,i2,UP,CALU1 +S 3000,4100,3000,7900,300,*,UP,ALU1 +S 3000,4100,3000,7900,300,i0,UP,CALU1 +V 2000,5000,CONT_POLY,* +V 5000,9100,CONT_DIF_P,* +V 1000,6000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 5000,4000,CONT_POLY,* +V 4200,2000,CONT_DIF_N,* +V 3000,4000,CONT_POLY,* +V 5200,1900,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 3200,2000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/no4_x1.vbe b/pdks/symbolic/nsxlib/cells/no4_x1.vbe new file mode 100644 index 000000000..5d15a3cd4 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rdown_i3_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT tphl_i1_nq : NATURAL := 230; + CONSTANT tplh_i3_nq : NATURAL := 271; + CONSTANT tplh_i1_nq : NATURAL := 320; + CONSTANT tphl_i0_nq : NATURAL := 330; + CONSTANT tplh_i2_nq : NATURAL := 333; + CONSTANT tplh_i0_nq : NATURAL := 340; + CONSTANT tphl_i2_nq : NATURAL := 419; + CONSTANT tphl_i3_nq : NATURAL := 499; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x1; + +ARCHITECTURE behaviour_data_flow OF no4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x1" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/no4_x4.ap b/pdks/symbolic/nsxlib/cells/no4_x4.ap new file mode 100644 index 000000000..0f6d330d1 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no4_x4.ap @@ -0,0 +1,141 @@ +V ALLIANCE : 6 +H no4_x4,P,26/ 9/2019,100 +A 0,0,10000,10000 +R 3000,5000,ref_ref,i0_25 +R 3000,4000,ref_ref,i0_20 +R 3000,3000,ref_ref,i0_15 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 5000,7000,ref_ref,i3_35 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 3000,8000,ref_ref,i0_40 +R 4000,3000,ref_ref,i2_15 +R 4000,4000,ref_ref,i2_20 +R 5000,3000,ref_ref,i3_15 +R 7000,7000,ref_ref,nq_35 +R 7000,8000,ref_ref,nq_40 +R 7000,3000,ref_ref,nq_15 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 2000,8000,ref_ref,i1_40 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 7000,6000,ref_ref,nq_30 +R 7000,5000,ref_ref,nq_25 +R 7000,4000,ref_ref,nq_20 +R 5000,6000,ref_ref,i3_30 +R 5000,5000,ref_ref,i3_25 +R 5000,4000,ref_ref,i3_20 +R 5000,8000,ref_ref,i3_40 +S 7000,3100,7000,7900,300,nq,UP,CALU1 +S 2000,3100,2000,7900,300,i1,UP,CALU1 +S 3000,3100,3000,7900,300,i0,UP,CALU1 +S 4000,3100,4000,7900,300,i2,UP,CALU1 +S 5000,3100,5000,7900,300,i3,UP,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 8800,5100,8800,5300,200,*,UP,POLY +S 2000,5100,2000,5300,200,*,UP,POLY +S 1700,4800,2100,4800,200,*,RIGHT,POLY +S 1600,2800,1600,4800,200,*,UP,POLY +S 2600,3800,3000,3800,200,*,RIGHT,POLY +S 2500,2800,2500,3800,200,*,UP,POLY +S 4100,2700,4100,2900,200,*,UP,POLY +S 6400,4000,9400,4000,400,*,RIGHT,POLY +S 5000,1500,5000,2500,200,*,UP,NTRANS +S 900,900,900,2300,400,*,UP,NDIF +S 1600,1500,1600,2500,200,*,UP,NTRANS +S 2500,1500,2500,2500,200,*,UP,NTRANS +S 3300,800,3300,2300,600,*,UP,NDIF +S 4100,1500,4100,2500,200,*,UP,NTRANS +S 9200,8300,9200,9200,600,*,UP,NTIE +S 8100,5700,8100,9300,400,*,UP,PDIF +S 8000,6100,8000,8900,300,*,UP,ALU1 +S 9300,1700,9300,2300,400,*,UP,NDIF +S 9200,2100,9200,5900,300,*,UP,ALU1 +S 9200,6100,9200,6900,300,*,UP,ALU1 +S 9300,5700,9300,7300,400,*,UP,PDIF +S 1100,2000,1700,2000,300,*,RIGHT,ALU1 +S 1100,2000,7900,2000,300,*,RIGHT,ALU1 +S 4400,5100,4400,5400,200,*,UP,POLY +S 5000,2600,5000,2900,200,*,UP,POLY +S 7000,3100,7000,7900,300,*,UP,ALU1 +S -300,7800,10300,7800,6000,*,RIGHT,NWELL +S 2800,4000,2800,5200,200,*,UP,POLY +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 4000,3100,4000,7900,300,*,UP,ALU1 +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 8000,2100,8000,4900,300,*,UP,ALU1 +S 1000,2100,1000,5900,300,*,UP,ALU1 +S 1000,6100,1000,7900,300,*,UP,ALU1 +S 2000,3100,2000,7900,300,*,UP,ALU1 +S 1000,5700,1000,8300,600,*,UP,PDIF +S 3600,5100,3600,5400,200,*,UP,POLY +S 3800,3000,3800,5000,200,*,UP,POLY +S 4800,3000,4800,5000,200,*,UP,POLY +S 4800,2900,5000,2900,200,*,RIGHT,POLY +S 4400,5100,4800,5100,200,*,RIGHT,POLY +S 8100,5000,8300,5000,300,*,RIGHT,ALU1 +S 7600,5500,7600,9500,200,*,UP,PTRANS +S 6400,5500,6400,9500,200,*,UP,PTRANS +S 7000,5700,7000,9300,600,*,UP,PDIF +S 5000,3100,5000,7900,300,*,UP,ALU1 +S 5000,5700,5000,9300,600,*,UP,PDIF +S 4400,5500,4400,9500,200,*,UP,PTRANS +S 2800,5500,2800,9500,200,*,UP,PTRANS +S 1400,5700,1400,8300,600,*,UP,PDIF +S 2000,5500,2000,9500,200,*,UP,PTRANS +S 3600,5100,3800,5100,200,*,RIGHT,POLY +S 8800,5500,8800,7500,200,*,UP,PTRANS +S 5800,5700,5800,9300,600,*,UP,PDIF +S 7600,2800,7600,5200,200,*,UP,POLY +S 8100,3000,8300,3000,300,*,RIGHT,ALU1 +S 5600,5700,5600,9300,800,*,UP,PDIF +S 8400,5100,8800,5100,400,*,RIGHT,POLY +S 6200,600,6200,2300,200,*,UP,NTRANS +S 5700,800,5700,2100,400,*,UP,NDIF +S 6200,2500,6200,2800,200,*,UP,POLY +S 7600,600,7600,2300,200,*,UP,NTRANS +S 7600,2500,7600,2800,200,*,UP,POLY +S 6900,800,6900,3100,400,*,UP,NDIF +S 6200,2800,6200,5200,200,*,UP,POLY +S 6200,5200,6400,5200,200,*,RIGHT,POLY +S 8100,800,8100,2100,400,*,UP,NDIF +S 8800,1500,8800,2500,200,*,UP,NTRANS +S 8800,2700,8800,2800,200,*,UP,POLY +S 8400,2800,8800,2800,200,*,LEFT,POLY +V 7000,3000,CONT_DIF_N,* +V 4000,3000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 8400,5000,CONT_POLY,* +V 2000,2000,CONT_DIF_N,* +V 3300,900,CONT_DIF_N,* +V 4500,2000,CONT_DIF_N,* +V 3000,4000,CONT_POLY,* +V 800,900,CONT_DIF_N,* +V 5000,9100,CONT_DIF_P,* +V 5800,9100,CONT_DIF_P,* +V 9200,9100,CONT_BODY_N,* +V 8400,3000,CONT_POLY,* +V 7000,8000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,6000,CONT_DIF_P,* +V 1000,6000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 8000,9200,CONT_DIF_P,* +V 9200,4000,CONT_POLY,* +V 9200,6000,CONT_DIF_P,* +V 9200,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 5800,900,CONT_DIF_N,* +V 8000,900,CONT_DIF_N,* +V 9200,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/no4_x4.vbe b/pdks/symbolic/nsxlib/cells/no4_x4.vbe new file mode 100644 index 000000000..cffb179c4 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/no4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 564; + CONSTANT tphl_i0_nq : NATURAL := 656; + CONSTANT tplh_i3_nq : NATURAL := 693; + CONSTANT tphl_i2_nq : NATURAL := 739; + CONSTANT tplh_i2_nq : NATURAL := 761; + CONSTANT tplh_i1_nq : NATURAL := 768; + CONSTANT tplh_i0_nq : NATURAL := 777; + CONSTANT tphl_i3_nq : NATURAL := 816; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x4; + +ARCHITECTURE behaviour_data_flow OF no4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x4" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa22_x1.ap b/pdks/symbolic/nsxlib/cells/noa22_x1.ap new file mode 100644 index 000000000..f4eb2ae24 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa22_x1.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 6 +H noa22_x1,P,25/ 9/2019,100 +A 0,0,6000,10000 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 4000,3000,ref_ref,i2_15 +R 4000,4000,ref_ref,i2_20 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +R 4000,7000,ref_ref,i2_35 +R 3000,2000,ref_ref,nq_10 +R 3000,3000,ref_ref,nq_15 +R 3000,4000,ref_ref,nq_20 +R 3000,5000,ref_ref,nq_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 1000,2000,ref_ref,i0_10 +R 4000,8000,ref_ref,i2_40 +R 3000,6000,ref_ref,nq_30 +R 3000,7000,ref_ref,nq_35 +R 4000,2000,ref_ref,i2_10 +R 2000,2000,ref_ref,i1_10 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +S 3600,2800,4000,2800,200,*,LEFT,POLY +S 2000,2800,2400,2800,200,*,RIGHT,POLY +S 3600,5200,4000,5200,200,*,LEFT,POLY +S 2000,5200,2400,5200,200,*,RIGHT,POLY +S 4000,2800,4000,5200,200,*,UP,POLY +S 2000,2800,2000,5200,200,*,UP,POLY +S 5200,1000,5200,1700,600,*,UP,PTIE +S 1200,2800,1200,5200,200,*,UP,POLY +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 3000,5700,3000,9300,600,*,UP,PDIF +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 1800,5700,1800,9300,600,*,UP,PDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 1900,7000,2900,7000,300,*,RIGHT,ALU1 +S 2000,2100,2000,5900,300,*,UP,ALU1 +S 1000,2100,1000,5900,300,*,UP,ALU1 +S 4000,2100,4000,7900,300,*,UP,ALU1 +S -300,7800,6300,7800,6000,*,RIGHT,NWELL +S 700,5700,700,9300,400,*,UP,PDIF +S 800,7100,800,7900,300,*,UP,ALU1 +S 900,8000,2900,8000,300,*,RIGHT,ALU1 +S 5200,5600,5200,6800,600,*,UP,NTIE +S 1200,600,1200,2500,200,*,UP,NTRANS +S 700,800,700,2300,400,*,UP,NDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S 1800,800,1800,2300,600,*,UP,NDIF +S 3000,800,3000,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 5200,1100,5200,3300,300,*,UP,ALU1 +S 4200,800,4200,2300,400,*,UP,NDIF +S 4200,5700,4200,9300,400,*,UP,PDIF +S 5200,7300,5200,8300,600,*,UP,NTIE +S 5200,5700,5200,8700,300,*,UP,ALU1 +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 5200,2100,5200,3300,600,*,UP,PTIE +S 4000,2100,4000,7900,300,i2,UP,CALU1 +S 1000,2100,1000,5900,300,i0,UP,CALU1 +S 2000,2100,2000,5900,300,i1,UP,CALU1 +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 3000,2100,3000,6900,300,nq,UP,CALU1 +V 2000,4000,CONT_POLY,* +V 3000,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 800,900,CONT_DIF_N,* +V 800,7000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 4200,9100,CONT_DIF_P,* +V 5200,5900,CONT_BODY_N,* +V 5200,8000,CONT_BODY_N,* +V 5200,3500,CONT_BODY_P,* +V 5200,900,CONT_BODY_P,* +V 4000,900,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 1800,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa22_x1.vbe b/pdks/symbolic/nsxlib/cells/noa22_x1.vbe new file mode 100644 index 000000000..5c13864f3 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 1620; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tphl_i2_nq : NATURAL := 218; + CONSTANT tplh_i2_nq : NATURAL := 241; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x1; + +ARCHITECTURE behaviour_data_flow OF noa22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 900 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa22_x4.ap b/pdks/symbolic/nsxlib/cells/noa22_x4.ap new file mode 100644 index 000000000..90e6b6099 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa22_x4.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H noa22_x4,P,29/ 4/2024,100 +A 0,0,10000,10000 +R 4000,3000,ref_ref,i0_15 +R 4000,2000,ref_ref,i0_10 +R 3000,5000,ref_ref,i1_25 +R 1000,4000,ref_ref,i2_20 +R 1000,3000,ref_ref,i2_15 +R 1000,2000,ref_ref,i2_10 +R 8000,5000,ref_ref,nq_25 +R 8000,3000,ref_ref,nq_15 +R 8000,2000,ref_ref,nq_10 +R 8000,4000,ref_ref,nq_20 +R 8000,6000,ref_ref,nq_30 +R 3000,4000,ref_ref,i1_20 +R 8000,8000,ref_ref,nq_40 +R 8000,7000,ref_ref,nq_35 +R 1000,7000,ref_ref,i2_35 +R 1000,8000,ref_ref,i2_40 +R 1000,5000,ref_ref,i2_25 +R 1000,6000,ref_ref,i2_30 +R 4000,4000,ref_ref,i0_20 +R 4000,5000,ref_ref,i0_25 +R 4000,6000,ref_ref,i0_30 +R 3000,6000,ref_ref,i1_30 +R 3000,3000,ref_ref,i1_15 +R 3000,2000,ref_ref,i1_10 +S 6400,2800,6400,5000,200,*,UP,POLY +S 6200,5100,6400,5100,200,*,RIGHT,POLY +S 7400,2800,7600,2800,200,*,RIGHT,POLY +S 6200,2800,6400,2800,200,*,RIGHT,POLY +S 7400,5200,7600,5200,200,*,RIGHT,POLY +S 3600,2800,4000,2800,200,*,RIGHT,POLY +S 2600,2800,3000,2800,200,*,RIGHT,POLY +S 3600,6200,4000,6200,200,*,RIGHT,POLY +S 2600,6200,3000,6200,200,*,RIGHT,POLY +S 7600,2800,7600,5200,200,*,UP,POLY +S 4000,2800,4000,6200,200,*,UP,POLY +S 3000,2800,3000,6200,200,*,UP,POLY +S 5600,5700,5600,7300,600,*,UP,PDIF +S 6200,5500,6200,7500,200,*,UP,PTRANS +S 8000,5700,8000,9300,600,*,UP,PDIF +S 8600,5500,8600,9500,200,*,UP,PTRANS +S 7400,5500,7400,9500,200,*,UP,PTRANS +S 2000,1700,2000,2300,600,*,UP,NDIF +S 2600,1500,2600,2500,200,*,UP,NTRANS +S 3200,1700,3200,2300,600,*,UP,NDIF +S 2600,6500,2600,8500,200,*,UP,PTRANS +S 4400,6700,4400,8300,600,*,UP,PDIF +S -300,7800,10300,7800,6000,*,RIGHT,NWELL +S 9000,6100,9000,8900,300,*,UP,ALU1 +S 3200,6700,3200,8300,400,*,UP,PDIF +S 2000,6700,2000,8300,400,*,UP,PDIF +S 7000,1100,7000,1900,300,*,UP,ALU1 +S 1000,4000,1400,4000,400,*,RIGHT,POLY +S 8600,2800,8600,5200,200,*,UP,POLY +S 2100,8000,4300,8000,300,*,RIGHT,ALU1 +S 8000,2100,8000,7900,300,*,UP,ALU1 +S 4500,9200,5700,9200,600,*,RIGHT,NTIE +S 4400,1300,4400,2300,600,*,UP,NDIF +S 800,1300,800,2300,600,*,UP,NDIF +S 6200,1500,6200,2500,200,*,UP,NTRANS +S 5600,1700,5600,2300,600,*,UP,NDIF +S 7000,4000,8600,4000,400,*,RIGHT,POLY +S 3600,6500,3600,8500,200,*,UP,PTRANS +S 3600,1500,3600,2500,200,*,UP,NTRANS +S 1600,6500,1600,8500,200,*,UP,PTRANS +S 1600,2800,1600,6200,200,*,UP,POLY +S 1600,1500,1600,2500,200,*,UP,NTRANS +S 6900,5700,6900,9300,400,*,UP,PDIF +S 7000,8100,7000,8900,300,*,UP,ALU1 +S 9200,5700,9200,9300,400,*,UP,PDIF +S 9000,1100,9000,1900,300,*,UP,ALU1 +S 4000,2100,4000,5900,300,*,UP,ALU1 +S 6600,5100,6600,6900,300,*,UP,ALU1 +S 5700,4000,6900,4000,300,*,RIGHT,ALU1 +S 2000,2100,2000,6900,300,*,UP,ALU1 +S 5600,2100,5600,5900,300,*,UP,ALU1 +S 3000,2100,3000,5900,300,*,UP,ALU1 +S 2100,7000,6500,7000,300,*,RIGHT,ALU1 +S 1000,2100,1000,7900,300,*,UP,ALU1 +S 7400,600,7400,2500,200,*,UP,NTRANS +S 6900,800,6900,2300,400,*,UP,NDIF +S 8000,800,8000,2300,600,*,UP,NDIF +S 8600,600,8600,2500,200,*,UP,NTRANS +S 9200,800,9200,2300,400,*,UP,NDIF +S 900,6700,900,8900,400,*,UP,PDIF +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 1000,2100,1000,7900,300,i2,UP,CALU1 +S 3000,2100,3000,5900,300,i1,UP,CALU1 +S 4000,2100,4000,5900,300,i0,UP,CALU1 +S 8000,2100,8000,7900,300,nq,UP,CALU1 +V 900,9300,CONT_DIF_P,* +V 3000,4000,CONT_POLY,* +V 2000,2000,CONT_DIF_N,* +V 5600,2000,CONT_DIF_N,* +V 8000,2000,CONT_DIF_N,* +V 3200,7000,CONT_DIF_P,* +V 7000,4000,CONT_POLY,* +V 6600,5000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 4400,900,CONT_DIF_N,* +V 800,900,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 7000,2000,CONT_DIF_N,* +V 7000,8000,CONT_DIF_P,* +V 7000,9200,CONT_DIF_P,* +V 9000,2000,CONT_DIF_N,* +V 4600,9200,CONT_BODY_N,* +V 5600,9200,CONT_BODY_N,* +V 7000,900,CONT_DIF_N,* +V 9000,900,CONT_DIF_N,* +V 9000,6000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 9000,9200,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 5600,6000,CONT_DIF_P,* +V 4400,8000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa22_x4.vbe b/pdks/symbolic/nsxlib/cells/noa22_x4.vbe new file mode 100644 index 000000000..6288a32e6 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 550; + CONSTANT tphl_i2_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i2_nq : NATURAL := 646; + CONSTANT tplh_i1_nq : NATURAL := 709; + CONSTANT tplh_i0_nq : NATURAL := 740; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x4; + +ARCHITECTURE behaviour_data_flow OF noa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa2a22_x1.ap b/pdks/symbolic/nsxlib/cells/noa2a22_x1.ap new file mode 100644 index 000000000..eedbe787b --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a22_x1.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 6 +H noa2a22_x1,P,25/ 9/2019,100 +A 0,0,7000,10000 +R 4000,5000,ref_ref,i3_25 +R 4000,4000,ref_ref,i3_20 +R 4000,3000,ref_ref,i3_15 +R 1000,2000,ref_ref,i0_10 +R 1000,3000,ref_ref,i0_15 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 4000,2000,ref_ref,i3_10 +R 2000,2000,ref_ref,i1_10 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 4000,6000,ref_ref,i3_30 +R 4000,7000,ref_ref,i3_35 +R 5000,7000,ref_ref,i2_35 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +R 5000,4000,ref_ref,i2_20 +R 5000,3000,ref_ref,i2_15 +R 5000,2000,ref_ref,i2_10 +R 3000,2000,ref_ref,nq_10 +R 3000,3000,ref_ref,nq_15 +R 3000,4000,ref_ref,nq_20 +R 3000,5000,ref_ref,nq_25 +R 3000,6000,ref_ref,nq_30 +R 3000,7000,ref_ref,nq_35 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +S 2000,2800,2400,2800,200,*,LEFT,POLY +S 3600,2800,4000,2800,200,*,RIGHT,POLY +S 3600,5200,4000,5200,200,*,RIGHT,POLY +S 2000,5200,2400,5200,200,*,LEFT,POLY +S 4000,2800,4000,5200,200,*,UP,POLY +S 2000,2800,2000,5200,200,*,UP,POLY +S 4000,2100,4000,6900,300,*,UP,ALU1 +S 5000,2100,5000,6900,300,*,UP,ALU1 +S 2000,2100,2000,5900,300,*,UP,ALU1 +S 1000,2100,1000,5900,300,*,UP,ALU1 +S 1000,8000,5300,8000,300,*,RIGHT,ALU1 +S 700,5700,700,9300,400,*,UP,PDIF +S 3000,5700,3000,9300,600,*,UP,PDIF +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 1800,5700,1800,9300,600,*,UP,PDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S -300,7800,7300,7800,6000,*,RIGHT,NWELL +S 5400,7500,5400,9300,600,*,UP,PDIF +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 1200,2800,1200,5200,200,*,UP,POLY +S 6200,5700,6200,6700,600,*,UP,NTIE +S 4800,2800,4800,5200,200,*,UP,POLY +S 1900,7000,3000,7000,300,*,RIGHT,ALU1 +S 1200,600,1200,2500,200,*,UP,NTRANS +S 700,800,700,2300,400,*,UP,NDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S 1800,800,1800,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 3000,800,3000,2300,600,*,UP,NDIF +S 4800,600,4800,2500,200,*,UP,NTRANS +S 4200,800,4200,2300,600,*,UP,NDIF +S 5400,800,5400,2300,600,*,UP,NDIF +S 5200,5700,5200,7300,400,*,UP,PDIF +S 6200,5900,6200,8900,300,*,UP,ALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 5000,2100,5000,6900,300,i2,UP,CALU1 +S 4000,2100,4000,6900,300,i3,UP,CALU1 +S 3000,2100,3000,6900,300,nq,UP,CALU1 +S 1000,2100,1000,5900,300,i0,UP,CALU1 +S 2000,2100,2000,5900,300,i1,UP,CALU1 +V 1800,7000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 800,900,CONT_DIF_N,* +V 5400,900,CONT_DIF_N,* +V 6200,5800,CONT_BODY_N,* +V 6200,6600,CONT_BODY_N,* +V 5400,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 3000,2000,CONT_DIF_N,* +V 5000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 4200,9100,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa2a22_x1.vbe b/pdks/symbolic/nsxlib/cells/noa2a22_x1.vbe new file mode 100644 index 000000000..d63481981 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i3_nq : NATURAL := 256; + CONSTANT tphl_i2_nq : NATURAL := 284; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i2_nq : NATURAL := 289; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT tphl_i3_nq : NATURAL := 372; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa2a22_x4.ap b/pdks/symbolic/nsxlib/cells/noa2a22_x4.ap new file mode 100644 index 000000000..76e5c6f86 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a22_x4.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 6 +H noa2a22_x4,P,25/ 9/2019,100 +A 0,0,11000,10000 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_10 +R 9000,3000,ref_ref,nq_15 +R 9000,2000,ref_ref,nq_10 +R 9000,4000,ref_ref,nq_20 +R 9000,6000,ref_ref,nq_30 +R 4000,2000,ref_ref,i3_10 +R 4000,3000,ref_ref,i3_15 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 9000,7000,ref_ref,nq_35 +R 9000,5000,ref_ref,nq_25 +R 9000,8000,ref_ref,nq_40 +R 5000,2000,ref_ref,i2_10 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +R 4000,4000,ref_ref,i3_20 +R 4000,5000,ref_ref,i3_25 +R 4000,6000,ref_ref,i3_30 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +S 4600,2800,5000,2800,200,*,RIGHT,POLY +S 3600,2800,4000,2800,200,*,RIGHT,POLY +S 2000,2800,2400,2800,200,*,LEFT,POLY +S 2000,6200,2400,6200,200,*,LEFT,POLY +S 3400,6100,4000,6100,200,*,RIGHT,POLY +S 2000,2800,2000,6200,200,*,UP,POLY +S 4000,2800,4000,6000,200,*,UP,POLY +S 5000,2800,5000,6100,200,*,UP,POLY +S 7600,5100,7600,6900,300,*,UP,ALU1 +S 1900,7000,7500,7000,300,*,RIGHT,ALU1 +S 5000,2100,5000,5900,300,*,UP,ALU1 +S 1900,6700,1900,8300,200,*,UP,PDIF +S 8000,1100,8000,1900,300,*,UP,ALU1 +S 2400,6500,2400,8500,200,*,UP,PTRANS +S 1300,6500,1300,8500,200,*,UP,PTRANS +S 1300,2800,1300,6200,200,*,UP,POLY +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 6600,2100,6600,5900,300,*,UP,ALU1 +S 6600,1700,6600,2300,600,*,UP,NDIF +S 4000,2100,4000,5900,300,*,UP,ALU1 +S 2000,2100,2000,5900,300,*,UP,ALU1 +S 7200,1500,7200,2500,200,*,UP,NTRANS +S 8400,5500,8400,9500,200,*,UP,PTRANS +S 9600,5500,9600,9500,200,*,UP,PTRANS +S 9000,5700,9000,9300,600,*,UP,PDIF +S 7200,5500,7200,7500,200,*,UP,PTRANS +S 6600,5700,6600,7300,600,*,UP,PDIF +S 10200,5700,10200,9300,400,*,UP,PDIF +S 10000,6100,10000,8900,300,*,UP,ALU1 +S 3000,1700,3000,2300,600,*,UP,NDIF +S 10200,1100,10200,1900,300,*,UP,ALU1 +S 6700,4000,7900,4000,300,*,RIGHT,ALU1 +S 9600,2800,9600,5200,200,*,UP,POLY +S 8400,2800,8400,5200,200,*,UP,POLY +S 7200,2800,7200,5200,200,*,UP,POLY +S 8000,8100,8000,8900,300,*,UP,ALU1 +S 7900,5700,7900,9300,400,*,UP,PDIF +S 5000,6500,5000,8500,200,*,UP,PTRANS +S 3400,6500,3400,8500,200,*,UP,PTRANS +S 800,8000,5300,8000,300,*,RIGHT,ALU1 +S 700,6700,700,8300,400,*,UP,PDIF +S 1300,1500,1300,2500,200,*,UP,NTRANS +S 4600,1500,4600,2500,200,*,UP,NTRANS +S 5000,6100,5000,6400,200,*,UP,POLY +S 3400,6100,3400,6400,200,*,UP,POLY +S 3600,1500,3600,2500,200,*,UP,NTRANS +S 4200,1700,4200,2300,600,*,UP,NDIF +S 1800,1700,1800,2300,600,*,UP,NDIF +S 2400,1500,2400,2500,200,*,UP,NTRANS +S 4200,6700,4200,9100,600,*,UP,PDIF +S 5400,900,5400,2300,600,*,UP,NDIF +S -300,7800,11300,7800,6000,*,RIGHT,NWELL +S 9000,2100,9000,7900,300,*,UP,ALU1 +S 7900,800,7900,2300,400,*,UP,NDIF +S 8400,600,8400,2500,200,*,UP,NTRANS +S 9000,800,9000,2300,600,*,UP,NDIF +S 9600,600,9600,2500,200,*,UP,NTRANS +S 10200,800,10200,2300,600,*,UP,NDIF +S 6200,9200,7100,9200,400,*,RIGHT,NTIE +S 7200,5000,7600,5000,400,*,RIGHT,POLY +S 8000,4000,9600,4000,400,*,RIGHT,POLY +S 900,1000,900,1900,400,*,UP,ALU1 +S 0,600,11000,600,1200,vss,RIGHT,CALU1 +S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 +S 1000,3000,1000,5900,300,i0,UP,CALU1 +S 9000,2100,9000,7900,300,nq,UP,CALU1 +S 5000,2100,5000,5900,300,i2,UP,CALU1 +S 4000,2100,4000,5900,300,i3,UP,CALU1 +S 2000,2100,2000,5900,300,i1,UP,CALU1 +S 1000,3000,1000,5900,300,*,UP,ALU1 +V 7800,5000,CONT_POLY,* +V 7800,4000,CONT_POLY,* +V 8000,8000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 8000,2000,CONT_DIF_N,* +V 4200,9300,CONT_DIF_P,* +V 10200,900,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 6600,6000,CONT_DIF_P,* +V 6600,2000,CONT_DIF_N,* +V 10200,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 1800,7000,CONT_DIF_P,* +V 9000,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 9000,6000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 10000,9200,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,6000,CONT_DIF_P,* +V 8000,9200,CONT_DIF_P,* +V 900,1900,CONT_DIF_N,* +V 5000,4000,CONT_POLY,* +V 6800,9100,CONT_BODY_N,* +V 8000,900,CONT_DIF_N,* +V 5400,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa2a22_x4.vbe b/pdks/symbolic/nsxlib/cells/noa2a22_x4.vbe new file mode 100644 index 000000000..93e31d341 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 562; + CONSTANT tphl_i1_nq : NATURAL := 646; + CONSTANT tplh_i3_nq : NATURAL := 677; + CONSTANT tphl_i2_nq : NATURAL := 701; + CONSTANT tplh_i2_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 714; + CONSTANT tplh_i0_nq : NATURAL := 745; + CONSTANT tphl_i3_nq : NATURAL := 805; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa2a2a23_x1.ap b/pdks/symbolic/nsxlib/cells/noa2a2a23_x1.ap new file mode 100644 index 000000000..dea929ffb --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a2a23_x1.ap @@ -0,0 +1,130 @@ +V ALLIANCE : 6 +H noa2a2a23_x1,P,25/ 9/2019,100 +A 0,0,10000,10000 +R 8000,4000,ref_ref,i1_20 +R 1000,6000,ref_ref,nq_30 +R 1000,7000,ref_ref,nq_35 +R 1000,3000,ref_ref,nq_15 +R 1000,4000,ref_ref,nq_20 +R 2000,3000,ref_ref,i5_15 +R 4000,3000,ref_ref,i3_15 +R 4000,5000,ref_ref,i3_25 +R 4000,6000,ref_ref,i3_30 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +R 3000,7000,ref_ref,i4_35 +R 3000,6000,ref_ref,i4_30 +R 1000,2000,ref_ref,nq_10 +R 8000,3000,ref_ref,i1_15 +R 1000,5000,ref_ref,nq_25 +R 3000,5000,ref_ref,i4_25 +R 3000,4000,ref_ref,i4_20 +R 3000,3000,ref_ref,i4_15 +R 5000,5000,ref_ref,i2_25 +R 5000,6000,ref_ref,i2_30 +R 9000,5000,ref_ref,i0_25 +R 9000,4000,ref_ref,i0_20 +R 9000,3000,ref_ref,i0_15 +R 9000,6000,ref_ref,i0_30 +R 8000,6000,ref_ref,i1_30 +R 2000,6000,ref_ref,i5_30 +R 2000,5000,ref_ref,i5_25 +R 2000,4000,ref_ref,i5_20 +R 4000,4000,ref_ref,i3_20 +S 3600,5200,4100,5200,200,*,RIGHT,POLY +S 3600,5200,3600,5500,200,*,UP,POLY +S 7600,5200,7600,5500,200,*,UP,POLY +S 7600,5200,8100,5200,200,*,RIGHT,POLY +S 6200,1000,6200,1700,600,*,UP,PTIE +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 3000,800,3000,2300,600,*,UP,NDIF +S 1000,800,1000,2300,400,*,UP,NDIF +S 1600,600,1600,2500,200,*,UP,NTRANS +S 2500,600,2500,2500,200,*,UP,NTRANS +S 4500,600,4500,2500,200,*,UP,NTRANS +S 5000,800,5000,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 7400,800,7400,2300,600,*,UP,NDIF +S 7900,600,7900,2500,200,*,UP,NTRANS +S 9300,800,9300,2300,400,*,UP,NDIF +S 8800,600,8800,2500,200,*,UP,NTRANS +S 7000,5700,7000,9300,600,*,UP,PDIF +S 5400,5700,5400,9300,600,*,UP,PDIF +S 1000,2000,7300,2000,300,*,RIGHT,ALU1 +S 3000,3100,3000,6900,300,*,UP,ALU1 +S 8000,3100,8000,5900,300,*,UP,ALU1 +S 9000,3100,9000,5900,300,*,UP,ALU1 +S -300,7800,10300,7800,6000,*,RIGHT,NWELL +S 8200,7100,8200,7900,300,*,UP,ALU1 +S 4300,7000,8100,7000,300,*,RIGHT,ALU1 +S 7000,8100,7000,9300,300,*,UP,ALU1 +S 1000,7000,1700,7000,300,*,RIGHT,ALU1 +S 4500,2600,4500,2900,200,*,UP,POLY +S 4500,2900,4800,2900,200,*,RIGHT,POLY +S 3600,2900,3800,2900,200,*,RIGHT,POLY +S 2500,2900,2800,2900,200,*,RIGHT,POLY +S 1600,2900,1800,2900,200,*,RIGHT,POLY +S 7900,2800,7900,5000,200,*,UP,POLY +S 5000,3100,5000,5900,300,*,UP,ALU1 +S 4000,3100,4000,5900,300,*,UP,ALU1 +S 2000,3100,2000,5900,300,*,UP,ALU1 +S 4200,5700,4200,9300,600,*,UP,PDIF +S 1800,5700,1800,9300,600,*,UP,PDIF +S 3000,5700,3000,9300,600,*,UP,PDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 8800,2800,8800,5200,200,*,UP,POLY +S 8800,5500,8800,9500,200,*,UP,PTRANS +S 8200,5700,8200,9300,600,*,UP,PDIF +S 7600,5500,7600,9500,200,*,UP,PTRANS +S 3600,2600,3600,2900,200,*,UP,POLY +S 2500,2600,2500,2900,200,*,UP,POLY +S 2800,3000,2800,5000,200,*,UP,POLY +S 3800,3000,3800,5100,200,*,UP,POLY +S 700,5700,700,9300,400,*,UP,PDIF +S 800,8000,5300,8000,300,*,RIGHT,ALU1 +S 9300,5700,9300,9300,400,*,UP,PDIF +S 9200,700,9200,1900,300,*,UP,ALU1 +S 9200,7100,9200,9100,300,*,UP,ALU1 +S 1600,2700,1600,2900,200,*,UP,POLY +S 1200,5100,1200,5400,200,*,UP,POLY +S 2400,5100,2400,5400,200,*,UP,POLY +S 1800,3000,1800,5000,200,*,UP,POLY +S 4800,3000,4800,5200,200,*,UP,POLY +S 1200,5100,1800,5100,200,*,RIGHT,POLY +S 2400,5100,2800,5100,200,*,RIGHT,POLY +S 1000,2100,1000,6900,300,nq,UP,CALU1 +S 1000,2100,1000,6900,300,*,UP,ALU1 +S 2000,3100,2000,5900,300,i5,UP,CALU1 +S 3000,3100,3000,6900,300,i4,UP,CALU1 +S 4000,3100,4000,5900,300,i3,UP,CALU1 +S 5000,3100,5000,5900,300,i2,UP,CALU1 +S 8000,3100,8000,5900,300,i1,UP,CALU1 +S 9000,3100,9000,5900,300,i0,UP,CALU1 +V 4200,7000,CONT_DIF_P,* +V 1800,7000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 9200,9200,CONT_DIF_P,* +V 9200,8000,CONT_DIF_P,* +V 9200,7000,CONT_DIF_P,* +V 9200,2000,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,* +V 5000,900,CONT_DIF_N,* +V 8000,5000,CONT_POLY,* +V 7000,8000,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +V 9200,900,CONT_DIF_N,* +V 1200,900,CONT_DIF_N,* +V 9000,5000,CONT_POLY,* +V 6200,800,CONT_BODY_P,* +V 7400,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 5000,5000,CONT_POLY,* +V 4000,5000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa2a2a23_x1.vbe b/pdks/symbolic/nsxlib/cells/noa2a2a23_x1.vbe new file mode 100644 index 000000000..2d90886a0 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a2a23_x1.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT rup_i3_nq : NATURAL := 4690; + CONSTANT rup_i4_nq : NATURAL := 4690; + CONSTANT rup_i5_nq : NATURAL := 4690; + CONSTANT tphl_i5_nq : NATURAL := 178; + CONSTANT tphl_i4_nq : NATURAL := 250; + CONSTANT tphl_i2_nq : NATURAL := 307; + CONSTANT tplh_i1_nq : NATURAL := 388; + CONSTANT tphl_i3_nq : NATURAL := 398; + CONSTANT tplh_i4_nq : NATURAL := 416; + CONSTANT tplh_i0_nq : NATURAL := 425; + CONSTANT tplh_i3_nq : NATURAL := 438; + CONSTANT tplh_i5_nq : NATURAL := 464; + CONSTANT tplh_i2_nq : NATURAL := 479; + CONSTANT tphl_i0_nq : NATURAL := 525; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa2a2a23_x4.ap b/pdks/symbolic/nsxlib/cells/noa2a2a23_x4.ap new file mode 100644 index 000000000..2d449ed1c --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a2a23_x4.ap @@ -0,0 +1,166 @@ +V ALLIANCE : 6 +H noa2a2a23_x4,P,25/ 9/2019,100 +A 0,0,13000,10000 +R 10000,8000,ref_ref,nq_40 +R 10000,3000,ref_ref,nq_15 +R 10000,7000,ref_ref,nq_35 +R 10000,6000,ref_ref,nq_30 +R 10000,5000,ref_ref,nq_25 +R 10000,4000,ref_ref,nq_20 +R 8000,3000,ref_ref,i0_15 +R 8000,6000,ref_ref,i0_30 +R 7000,6000,ref_ref,i1_30 +R 7000,5000,ref_ref,i1_25 +R 7000,3000,ref_ref,i1_15 +R 7000,4000,ref_ref,i1_20 +R 8000,5000,ref_ref,i0_25 +R 8000,4000,ref_ref,i0_20 +R 3000,7000,ref_ref,i4_35 +R 3000,6000,ref_ref,i4_30 +R 3000,5000,ref_ref,i4_25 +R 3000,4000,ref_ref,i4_20 +R 3000,3000,ref_ref,i4_15 +R 4000,4000,ref_ref,i3_20 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +R 5000,4000,ref_ref,i2_20 +R 5000,3000,ref_ref,i2_15 +R 4000,6000,ref_ref,i3_30 +R 4000,5000,ref_ref,i3_25 +R 4000,3000,ref_ref,i3_15 +R 2000,3000,ref_ref,i5_15 +R 2000,6000,ref_ref,i5_30 +R 2000,5000,ref_ref,i5_25 +R 2000,4000,ref_ref,i5_20 +S 11400,3000,11800,3000,400,*,RIGHT,POLY +S 11400,2100,11400,2900,300,*,UP,ALU1 +S 12500,1700,12500,2300,400,*,UP,NDIF +S 12200,8300,12200,9200,600,*,UP,NTIE +S 0,9400,13000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,13000,600,1200,vss,RIGHT,CALU1 +S 2400,600,2400,2500,200,*,UP,NTRANS +S 4500,600,4500,2500,200,*,UP,NTRANS +S 5000,800,5000,2300,600,*,UP,NDIF +S 6800,800,6800,2300,600,*,UP,NDIF +S 8800,800,8800,2300,600,*,UP,NDIF +S 8300,600,8300,2500,200,*,UP,NTRANS +S 7400,600,7400,2500,200,*,UP,NTRANS +S 9200,600,9200,2500,200,*,UP,NTRANS +S 10000,800,10000,2900,600,*,UP,NDIF +S 10800,600,10800,2500,200,*,UP,NTRANS +S 11200,800,11200,2300,600,*,UP,NDIF +S 700,8000,5300,8000,300,*,RIGHT,ALU1 +S 4200,5700,4200,9300,600,*,UP,PDIF +S 1800,5700,1800,9300,600,*,UP,PDIF +S 3000,5700,3000,9300,600,*,UP,PDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 9400,4000,10600,4000,200,*,RIGHT,POLY +S 1100,2000,11300,2000,300,*,RIGHT,ALU1 +S 11100,4000,12300,4000,300,*,RIGHT,ALU1 +S 12400,2100,12400,6900,300,*,UP,ALU1 +S 7000,5500,7000,9500,200,*,UP,PTRANS +S 10000,5700,10000,9300,600,*,UP,PDIF +S 11200,5700,11200,9300,600,*,UP,PDIF +S 1200,5100,1800,5100,200,*,RIGHT,POLY +S 2400,5100,2800,5100,200,*,RIGHT,POLY +S 3600,5100,3800,5100,200,*,RIGHT,POLY +S 7000,2900,7400,2900,200,*,RIGHT,POLY +S 4500,2900,4800,2900,200,*,RIGHT,POLY +S 3000,800,3000,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 1000,800,1000,2300,600,*,UP,NDIF +S 1500,600,1500,2500,200,*,UP,NTRANS +S 12500,5700,12500,7300,400,*,UP,PDIF +S 10800,4000,11000,4000,400,*,RIGHT,POLY +S 8800,5700,8800,9300,600,*,UP,PDIF +S 7600,5700,7600,9300,600,*,UP,PDIF +S 8200,5500,8200,9500,200,*,UP,PTRANS +S 11200,7100,11200,9100,300,*,UP,ALU1 +S 7600,7100,7600,7900,300,*,UP,ALU1 +S 8800,7100,8800,9100,300,*,UP,ALU1 +S 8000,3100,8000,5900,300,*,UP,ALU1 +S 4800,3000,4800,5200,200,*,UP,POLY +S 7000,5000,7000,5400,200,*,UP,POLY +S 8200,5000,8200,5400,200,*,UP,POLY +S 5400,5700,5400,8000,600,*,UP,PDIF +S 1800,3000,1800,5100,200,*,UP,POLY +S 1200,5100,1200,5400,200,*,UP,POLY +S 12000,2800,12000,5200,200,*,UP,POLY +S 12000,1500,12000,2500,200,*,UP,NTRANS +S 7000,3100,7000,5900,300,*,UP,ALU1 +S 1000,2100,1000,6800,300,*,UP,ALU1 +S 1100,6900,1700,6900,300,*,RIGHT,ALU1 +S -300,7800,13300,7800,6000,*,RIGHT,NWELL +S 3000,3100,3000,6900,300,*,UP,ALU1 +S 5000,3100,5000,5900,300,*,UP,ALU1 +S 4000,3100,4000,5900,300,*,UP,ALU1 +S 2000,3100,2000,5900,300,*,UP,ALU1 +S 600,5700,600,9300,600,*,UP,PDIF +S 4300,7000,7500,7000,300,*,RIGHT,ALU1 +S 12000,5500,12000,7500,200,*,UP,PTRANS +S 3800,3000,3800,5100,200,*,UP,POLY +S 1500,2900,1800,2900,200,*,RIGHT,POLY +S 2400,2900,2800,2900,200,*,RIGHT,POLY +S 3600,2900,3800,2900,200,*,RIGHT,POLY +S 3600,5100,3600,5400,200,*,UP,POLY +S 7400,2600,7400,2900,200,*,UP,POLY +S 4500,2600,4500,2900,200,*,UP,POLY +S 3600,2600,3600,2900,200,*,UP,POLY +S 2400,2600,2400,2900,200,*,UP,POLY +S 1500,2600,1500,2900,200,*,UP,POLY +S 7000,3000,7000,5000,200,*,UP,POLY +S 8300,2800,8300,5100,200,*,UP,POLY +S 2800,3000,2800,5100,200,*,UP,POLY +S 2400,5100,2400,5400,200,*,UP,POLY +S 10800,2800,10800,5200,200,*,UP,POLY +S 10800,5500,10800,9500,200,*,UP,PTRANS +S 9200,2800,9200,5200,200,*,UP,POLY +S 9200,5500,9200,9500,200,*,UP,PTRANS +S 6400,5700,6400,9300,400,*,UP,PDIF +S 10000,3100,10000,7900,300,nq,UP,CALU1 +S 10000,3100,10000,7900,300,*,UP,ALU1 +S 8000,3100,8000,5900,300,i0,UP,CALU1 +S 7000,3100,7000,5900,300,i1,UP,CALU1 +S 5000,3100,5000,5900,300,i2,UP,CALU1 +S 4000,3100,4000,5900,300,i3,UP,CALU1 +S 3000,3100,3000,6900,300,i4,UP,CALU1 +S 2000,3100,2000,5900,300,i5,UP,CALU1 +V 11400,3000,CONT_POLY,* +V 8800,900,CONT_DIF_N,* +V 12200,9200,CONT_BODY_N,* +V 8800,9200,CONT_DIF_P,* +V 11200,9200,CONT_DIF_P,* +V 11000,4000,CONT_POLY,* +V 12400,7000,CONT_DIF_P,* +V 12400,6000,CONT_DIF_P,* +V 12400,2000,CONT_DIF_N,* +V 10000,7000,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 8800,8000,CONT_DIF_P,* +V 8800,7000,CONT_DIF_P,* +V 7600,8000,CONT_DIF_P,* +V 11200,7000,CONT_DIF_P,* +V 11200,8000,CONT_DIF_P,* +V 10000,6000,CONT_DIF_P,* +V 6800,2000,CONT_DIF_N,* +V 7000,5000,CONT_POLY,* +V 8000,5000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 5400,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 1800,7000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 10000,3000,CONT_DIF_N,* +V 11200,900,CONT_DIF_N,* +V 5000,900,CONT_DIF_N,* +V 1000,900,CONT_DIF_N,* +V 6200,9200,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa2a2a23_x4.vbe b/pdks/symbolic/nsxlib/cells/noa2a2a23_x4.vbe new file mode 100644 index 000000000..328209403 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT tphl_i5_nq : NATURAL := 496; + CONSTANT tphl_i4_nq : NATURAL := 574; + CONSTANT tphl_i2_nq : NATURAL := 620; + CONSTANT tphl_i3_nq : NATURAL := 716; + CONSTANT tplh_i1_nq : NATURAL := 778; + CONSTANT tplh_i0_nq : NATURAL := 814; + CONSTANT tplh_i4_nq : NATURAL := 819; + CONSTANT tplh_i3_nq : NATURAL := 833; + CONSTANT tphl_i0_nq : NATURAL := 834; + CONSTANT tplh_i5_nq : NATURAL := 865; + CONSTANT tplh_i2_nq : NATURAL := 873; + CONSTANT tphl_i1_nq : NATURAL := 955; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1600 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x1.ap b/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x1.ap new file mode 100644 index 000000000..fe7f4f507 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x1.ap @@ -0,0 +1,157 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x1,P,25/ 9/2019,100 +A 0,0,14000,10000 +R 5000,6000,ref_ref,i5_30 +R 6000,3000,ref_ref,i4_15 +R 6000,4000,ref_ref,i4_20 +R 6000,5000,ref_ref,i4_25 +R 5000,5000,ref_ref,i5_25 +R 5000,4000,ref_ref,i5_20 +R 5000,3000,ref_ref,i5_15 +R 3000,6000,ref_ref,i6_30 +R 3000,5000,ref_ref,i6_25 +R 3000,4000,ref_ref,i6_20 +R 1000,4000,ref_ref,i7_20 +R 1000,5000,ref_ref,i7_25 +R 1000,6000,ref_ref,i7_30 +R 2000,2000,ref_ref,nq_10 +R 2000,3000,ref_ref,nq_15 +R 2000,4000,ref_ref,nq_20 +R 2000,5000,ref_ref,nq_25 +R 2000,6000,ref_ref,nq_30 +R 3000,3000,ref_ref,i6_15 +R 7000,5000,ref_ref,i3_25 +R 7000,4000,ref_ref,i3_20 +R 7000,3000,ref_ref,i3_15 +R 6000,6000,ref_ref,i4_30 +R 7000,6000,ref_ref,i3_30 +R 8000,3000,ref_ref,i2_15 +R 8000,4000,ref_ref,i2_20 +R 8000,5000,ref_ref,i2_25 +R 8000,6000,ref_ref,i2_30 +R 11000,3000,ref_ref,i1_15 +R 11000,4000,ref_ref,i1_20 +R 11000,5000,ref_ref,i1_25 +R 11000,6000,ref_ref,i1_30 +R 11000,7000,ref_ref,i1_35 +R 12000,3000,ref_ref,i0_15 +R 12000,4000,ref_ref,i0_20 +R 12000,5000,ref_ref,i0_25 +R 12000,6000,ref_ref,i0_30 +R 12000,7000,ref_ref,i0_35 +R 1000,2000,ref_ref,i7_10 +R 1000,3000,ref_ref,i7_15 +S 2000,2100,2000,6900,300,nq,UP,CALU1 +S 2000,2100,2000,6900,300,*,UP,ALU1 +S 1000,2100,1000,5900,300,i7,UP,CALU1 +S 3000,3100,3000,5900,300,i6,UP,CALU1 +S 5000,3100,5000,5900,300,i5,UP,CALU1 +S 6000,3100,6000,5900,300,i4,UP,CALU1 +S 7000,3100,7000,5900,300,i3,UP,CALU1 +S 8000,3100,8000,5900,300,i2,UP,CALU1 +S 11000,3100,11000,6900,300,i1,UP,CALU1 +S 12000,3100,12000,6900,300,i0,UP,CALU1 +S 1500,2600,1500,2900,200,*,UP,POLY +S 1200,3000,1200,5200,200,*,UP,POLY +S 1200,2900,1500,2900,200,*,RIGHT,POLY +S 800,900,800,2300,400,*,UP,NDIF +S 1900,900,1900,2300,600,*,UP,NDIF +S 1500,700,1500,2500,200,*,UP,NTRANS +S 700,5700,700,9300,400,*,UP,PDIF +S 800,7100,800,7900,300,*,UP,ALU1 +S 12600,5700,12600,9300,600,*,UP,PDIF +S 12000,2800,12000,5200,200,*,UP,POLY +S 10800,2800,10800,5200,200,*,UP,POLY +S 7200,2800,7200,5200,200,*,UP,POLY +S 6000,2800,6000,5200,200,*,UP,POLY +S 4800,2800,4800,5200,200,*,UP,POLY +S 2400,2800,2400,5200,200,*,UP,POLY +S 12600,700,12600,1900,300,*,UP,ALU1 +S -300,7800,14300,7800,6000,*,RIGHT,NWELL +S 3000,7100,3000,7900,300,*,UP,ALU1 +S 700,8000,2900,8000,300,*,RIGHT,ALU1 +S 4300,8000,8900,8000,300,*,RIGHT,ALU1 +S 3100,7000,5300,7000,300,*,RIGHT,ALU1 +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 6000,5500,6000,9500,200,*,UP,PTRANS +S 6600,5700,6600,9300,600,*,UP,PDIF +S 5400,5700,5400,9300,600,*,UP,PDIF +S 7800,5700,7800,9300,600,*,UP,PDIF +S 9000,5700,9000,9300,600,*,UP,PDIF +S 8400,5500,8400,9500,200,*,UP,PTRANS +S 12000,5500,12000,9500,200,*,UP,PTRANS +S 4200,1100,4200,2300,600,*,UP,NDIF +S 12000,700,12000,2500,200,*,UP,NTRANS +S 6600,7100,6600,7900,300,*,UP,ALU1 +S 1000,2100,1000,5900,300,*,UP,ALU1 +S 11400,5700,11400,9300,600,*,UP,PDIF +S 1800,5700,1800,9300,600,*,UP,PDIF +S 3000,5700,3000,9300,600,*,UP,PDIF +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 10200,5700,10200,9300,600,*,UP,PDIF +S 11000,3100,11000,6900,300,*,UP,ALU1 +S 12000,3100,12000,6900,300,*,UP,ALU1 +S 8000,3100,8000,5900,300,*,UP,ALU1 +S 7000,3100,7000,5900,300,*,UP,ALU1 +S 6000,3100,6000,5900,300,*,UP,ALU1 +S 5000,3100,5000,5900,300,*,UP,ALU1 +S 3000,3100,3000,5900,300,*,UP,ALU1 +S 12600,8100,12600,9100,300,*,UP,ALU1 +S 7200,5500,7200,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 10800,5500,10800,9500,200,*,UP,PTRANS +S 5400,900,5400,2300,600,*,UP,NDIF +S 4800,700,4800,2500,200,*,UP,NTRANS +S 6000,700,6000,2500,200,*,UP,NTRANS +S 6600,900,6600,2300,600,*,UP,NDIF +S 7200,700,7200,2500,200,*,UP,NTRANS +S 7800,900,7800,2300,600,*,UP,NDIF +S 2000,2000,10100,2000,300,*,RIGHT,ALU1 +S 7900,7000,9900,7000,300,*,RIGHT,ALU1 +S 10000,7100,10000,7900,300,*,UP,ALU1 +S 10100,8000,11300,8000,300,*,RIGHT,ALU1 +S 2400,700,2400,2500,200,*,UP,NTRANS +S 3000,900,3000,2300,600,*,UP,NDIF +S 2400,5000,3000,5000,400,*,RIGHT,POLY +S 9000,900,9000,2300,600,*,UP,NDIF +S 8400,700,8400,2500,200,*,UP,NTRANS +S 10200,900,10200,2300,600,*,UP,NDIF +S 10800,700,10800,2500,200,*,UP,NTRANS +S 11400,900,11400,2300,600,*,UP,NDIF +S 12600,900,12600,2300,600,*,UP,NDIF +S 0,600,14000,600,1200,vss,RIGHT,CALU1 +S 0,9400,14000,9400,1200,vdd,RIGHT,CALU1 +S 8000,2800,8000,5200,200,*,UP,POLY +S 8000,5200,8400,5200,200,*,LEFT,POLY +S 8000,2800,8400,2800,200,*,LEFT,POLY +V 9100,900,CONT_DIF_N,* +V 4100,900,CONT_DIF_N,* +V 800,900,CONT_DIF_N,* +V 1000,5000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 6000,5000,CONT_POLY,* +V 7000,5000,CONT_POLY,* +V 8000,5000,CONT_POLY,* +V 6600,7000,CONT_DIF_P,* +V 12000,5000,CONT_POLY,* +V 11000,5000,CONT_POLY,* +V 12600,2000,CONT_DIF_N,* +V 12600,8000,CONT_DIF_P,* +V 7800,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,* +V 6600,8000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 11400,8000,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,* +V 10200,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 2000,7000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 6600,2000,CONT_DIF_N,* +V 10400,9100,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x1.vbe b/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x1.vbe new file mode 100644 index 000000000..ed253ca47 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x1.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rdown_i6_nq : NATURAL := 2850; + CONSTANT rdown_i7_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT rup_i4_nq : NATURAL := 6190; + CONSTANT rup_i5_nq : NATURAL := 6190; + CONSTANT rup_i6_nq : NATURAL := 6190; + CONSTANT rup_i7_nq : NATURAL := 6190; + CONSTANT tphl_i7_nq : NATURAL := 200; + CONSTANT tphl_i6_nq : NATURAL := 270; + CONSTANT tphl_i5_nq : NATURAL := 329; + CONSTANT tphl_i4_nq : NATURAL := 419; + CONSTANT tplh_i6_nq : NATURAL := 535; + CONSTANT tphl_i2_nq : NATURAL := 550; + CONSTANT tplh_i1_nq : NATURAL := 562; + CONSTANT tplh_i7_nq : NATURAL := 591; + CONSTANT tplh_i0_nq : NATURAL := 606; + CONSTANT tplh_i4_nq : NATURAL := 613; + CONSTANT tplh_i3_nq : NATURAL := 616; + CONSTANT tphl_i0_nq : NATURAL := 649; + CONSTANT tplh_i2_nq : NATURAL := 662; + CONSTANT tplh_i5_nq : NATURAL := 662; + CONSTANT tphl_i3_nq : NATURAL := 667; + CONSTANT tphl_i1_nq : NATURAL := 775; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x1" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x4.ap b/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x4.ap new file mode 100644 index 000000000..23d72b6e5 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x4.ap @@ -0,0 +1,201 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x4,P,26/ 9/2019,100 +A 0,0,17000,10000 +R 14000,8000,ref_ref,nq_40 +R 14000,4000,ref_ref,nq_20 +R 6000,6000,ref_ref,i4_30 +R 7000,3000,ref_ref,i3_15 +R 7000,4000,ref_ref,i3_20 +R 7000,5000,ref_ref,i3_25 +R 7000,6000,ref_ref,i3_30 +R 8000,3000,ref_ref,i2_15 +R 8000,4000,ref_ref,i2_20 +R 8000,5000,ref_ref,i2_25 +R 1000,6000,ref_ref,i7_30 +R 3000,3000,ref_ref,i6_15 +R 3000,4000,ref_ref,i6_20 +R 3000,5000,ref_ref,i6_25 +R 3000,6000,ref_ref,i6_30 +R 5000,3000,ref_ref,i5_15 +R 5000,4000,ref_ref,i5_20 +R 5000,5000,ref_ref,i5_25 +R 5000,6000,ref_ref,i5_30 +R 6000,3000,ref_ref,i4_15 +R 8000,6000,ref_ref,i2_30 +R 13000,6000,ref_ref,i0_30 +R 13000,5000,ref_ref,i0_25 +R 13000,4000,ref_ref,i0_20 +R 13000,3000,ref_ref,i0_15 +R 11000,3000,ref_ref,i1_15 +R 11000,6000,ref_ref,i1_30 +R 11000,5000,ref_ref,i1_25 +R 11000,4000,ref_ref,i1_20 +R 13000,7000,ref_ref,i0_35 +R 14000,3000,ref_ref,nq_15 +R 14000,7000,ref_ref,nq_35 +R 14000,6000,ref_ref,nq_30 +R 14000,5000,ref_ref,nq_25 +R 1000,2000,ref_ref,i7_10 +R 1000,3000,ref_ref,i7_15 +R 1000,4000,ref_ref,i7_20 +R 1000,5000,ref_ref,i7_25 +R 6000,4000,ref_ref,i4_20 +R 6000,5000,ref_ref,i4_25 +S 15700,2800,15700,3200,300,*,DOWN,POLY +S 15800,2800,15800,5200,200,*,UP,POLY +S 14000,800,14000,2800,400,*,UP,NDIF +S 8400,5200,8400,5500,200,*,UP,POLY +S 8000,5200,8400,5200,200,*,RIGHT,POLY +S 16200,8300,16200,9200,600,*,UP,NTIE +S 8600,800,8600,2300,600,*,UP,NDIF +S 8100,600,8100,2500,200,*,UP,NTRANS +S 10800,800,10800,2300,600,*,UP,NDIF +S 11300,600,11300,2500,200,*,UP,NTRANS +S 12200,600,12200,2500,200,*,UP,NTRANS +S 12800,800,12800,2300,600,*,UP,NDIF +S 15100,800,15100,2300,400,*,UP,NDIF +S 13300,600,13300,2500,200,*,UP,NTRANS +S 14700,600,14700,2500,200,*,UP,NTRANS +S 15800,5500,15800,7500,200,*,UP,PTRANS +S 2100,2000,10700,2000,300,*,RIGHT,ALU1 +S 11000,3100,11000,5900,300,*,UP,ALU1 +S 6100,600,6100,2500,200,*,UP,NTRANS +S 6600,800,6600,2300,600,*,UP,NDIF +S 7200,600,7200,2500,200,*,UP,NTRANS +S 4600,800,4600,2300,600,*,UP,NDIF +S 5200,600,5200,2500,200,*,UP,NTRANS +S 2400,600,2400,2500,200,*,UP,NTRANS +S 3000,800,3000,2300,600,*,UP,NDIF +S 1800,800,1800,2300,600,*,UP,NDIF +S 1200,600,1200,2500,200,*,UP,NTRANS +S 700,800,700,2300,400,*,UP,NDIF +S 11000,2900,11300,2900,200,*,RIGHT,POLY +S 4800,5100,5200,5100,200,*,RIGHT,POLY +S 6100,2800,6100,5100,200,*,UP,POLY +S 8100,2800,8100,5100,200,*,UP,POLY +S 11000,2900,11000,5200,200,*,UP,POLY +S 4800,5100,4800,5400,200,*,UP,POLY +S 11300,2700,11300,2900,200,*,UP,POLY +S 13000,3100,13000,6900,300,*,UP,ALU1 +S 10400,5700,10400,9300,600,*,UP,PDIF +S 11000,5500,11000,9500,200,*,UP,PTRANS +S 14600,5500,14600,9500,200,*,UP,PTRANS +S 12800,5700,12800,9300,600,*,UP,PDIF +S 14000,5700,14000,9300,600,*,UP,PDIF +S 11600,5700,11600,9300,600,*,UP,PDIF +S 12200,5500,12200,9500,200,*,UP,PTRANS +S 11600,7100,11600,7900,300,*,UP,ALU1 +S 14800,4000,15000,4000,400,*,RIGHT,POLY +S 14600,4100,14600,5300,200,*,UP,POLY +S 6000,5100,6000,5300,200,*,UP,POLY +S 12400,4000,12800,4000,400,*,RIGHT,ALU1 +S 1900,7000,1900,7000,300,*,LEFT,ALU1 +S 6600,7100,6600,7900,300,*,UP,ALU1 +S 1000,2100,1000,5900,300,*,UP,ALU1 +S 8000,3100,8000,5900,300,*,UP,ALU1 +S 800,8000,2900,8000,300,*,RIGHT,ALU1 +S 800,7100,800,7900,300,*,UP,ALU1 +S 700,5700,700,9300,400,*,UP,PDIF +S 13300,5500,13300,9500,200,*,UP,PTRANS +S 13300,2800,13300,5200,200,*,UP,POLY +S 15100,5700,15100,9300,400,*,UP,PDIF +S 15000,7100,15000,9100,300,*,UP,ALU1 +S 16300,5700,16300,7300,400,*,UP,PDIF +S 16300,1700,16300,2300,400,*,UP,NDIF +S 4200,5700,4200,9300,600,*,UP,PDIF +S 7200,5500,7200,9500,200,*,UP,PTRANS +S 3000,3100,3000,5900,300,*,UP,ALU1 +S 5000,3100,5000,5900,300,*,UP,ALU1 +S 6000,3100,6000,5900,300,*,UP,ALU1 +S 7000,3100,7000,5900,300,*,UP,ALU1 +S 10900,2000,15300,2000,300,*,RIGHT,ALU1 +S 15400,2100,15400,2900,300,*,UP,ALU1 +S 7900,7000,11500,7000,300,*,RIGHT,ALU1 +S 15100,4000,16300,4000,300,*,RIGHT,ALU1 +S 13400,4000,15000,4000,200,*,RIGHT,POLY +S 12200,2800,12200,5200,200,*,UP,POLY +S 16200,2100,16200,6900,300,*,UP,ALU1 +S 7800,5700,7800,9300,600,*,UP,PDIF +S 5400,5700,5400,9300,600,*,UP,PDIF +S 6600,5700,6600,9300,600,*,UP,PDIF +S 6000,5500,6000,9500,200,*,UP,PTRANS +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 12800,8100,12800,9100,300,*,UP,ALU1 +S 10400,8100,10400,9100,300,*,UP,ALU1 +S 9000,5700,9000,9300,600,*,UP,PDIF +S -300,7800,17300,7800,6000,*,RIGHT,NWELL +S 7200,2800,7200,5200,200,*,UP,POLY +S 15800,600,15800,2500,200,*,UP,NTRANS +S 2400,5000,3000,5000,400,*,RIGHT,POLY +S 5200,2800,5200,5100,200,*,UP,POLY +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 3100,7000,5300,7000,300,*,RIGHT,ALU1 +S 4300,8000,8900,8000,300,*,RIGHT,ALU1 +S 3000,7100,3000,7900,300,*,UP,ALU1 +S 2400,2800,2400,5200,200,*,UP,POLY +S 1200,2800,1200,5200,200,*,UP,POLY +S 8400,5500,8400,9500,200,*,UP,PTRANS +S 1800,5700,1800,9300,600,*,UP,PDIF +S 3000,5700,3000,9300,600,*,UP,PDIF +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 2000,2100,2000,6900,300,*,UP,ALU1 +S 0,600,17000,600,1200,vss,RIGHT,CALU1 +S 0,9400,17000,9400,1200,vdd,RIGHT,CALU1 +S 14000,3000,14000,7900,300,*,UP,ALU1 +S 14000,3000,14000,7900,300,nq,UP,CALU1 +S 13000,3100,13000,7000,300,i0,UP,CALU1 +S 11000,3100,11000,5900,300,i1,UP,CALU1 +S 8000,3100,8000,5900,300,i2,UP,CALU1 +S 7000,3100,7000,5900,300,i3,UP,CALU1 +S 6000,3100,6000,5900,300,i4,UP,CALU1 +S 5000,3100,5000,5900,300,i5,UP,CALU1 +S 3000,3100,3000,5900,300,i6,UP,CALU1 +S 1000,2100,1000,5900,300,i7,UP,CALU1 +S 14600,2800,14600,4000,200,*,UP,POLY +S 14600,2800,14700,2800,200,*,LEFT,POLY +V 14000,2700,CONT_DIF_N,* +V 16200,9200,CONT_BODY_N,* +V 7800,7000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 6600,7000,CONT_DIF_P,* +V 8000,5000,CONT_POLY,* +V 7000,5000,CONT_POLY,* +V 6000,5000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 3000,8000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,* +V 6600,8000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,* +V 1800,7000,CONT_DIF_P,* +V 6600,2000,CONT_DIF_N,* +V 10800,2000,CONT_DIF_N,* +V 14000,7000,CONT_DIF_P,* +V 14000,8000,CONT_DIF_P,* +V 12800,8000,CONT_DIF_P,* +V 10400,8000,CONT_DIF_P,* +V 11600,8000,CONT_DIF_P,* +V 14000,6000,CONT_DIF_P,* +V 15400,3000,CONT_POLY,* +V 11000,4000,CONT_POLY,* +V 16200,7000,CONT_DIF_P,* +V 16200,5800,CONT_DIF_P,* +V 16200,2000,CONT_DIF_N,* +V 15000,9200,CONT_DIF_P,* +V 15000,8000,CONT_DIF_P,* +V 15000,7000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 800,900,CONT_DIF_N,* +V 10400,9200,CONT_DIF_P,* +V 12800,9200,CONT_DIF_P,* +V 5000,5000,CONT_POLY,* +V 12000,4000,CONT_POLY,* +V 2800,2000,CONT_DIF_N,* +V 15200,4000,CONT_POLY,* +V 15300,900,CONT_DIF_N,* +V 12800,900,CONT_DIF_N,* +V 4800,900,CONT_DIF_N,* +V 8500,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x4.vbe b/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x4.vbe new file mode 100644 index 000000000..2499cd710 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2a2a2a24_x4.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4250; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rdown_i7_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT rup_i7_nq : NATURAL := 890; + CONSTANT tphl_i7_nq : NATURAL := 525; + CONSTANT tphl_i6_nq : NATURAL := 606; + CONSTANT tphl_i5_nq : NATURAL := 649; + CONSTANT tphl_i4_nq : NATURAL := 748; + CONSTANT tphl_i2_nq : NATURAL := 867; + CONSTANT tphl_i0_nq : NATURAL := 966; + CONSTANT tphl_i3_nq : NATURAL := 990; + CONSTANT tplh_i6_nq : NATURAL := 999; + CONSTANT tplh_i1_nq : NATURAL := 1005; + CONSTANT tplh_i0_nq : NATURAL := 1049; + CONSTANT tplh_i7_nq : NATURAL := 1052; + CONSTANT tplh_i3_nq : NATURAL := 1061; + CONSTANT tplh_i4_nq : NATURAL := 1061; + CONSTANT tphl_i1_nq : NATURAL := 1097; + CONSTANT tplh_i2_nq : NATURAL := 1106; + CONSTANT tplh_i5_nq : NATURAL := 1109; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x4" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1700 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa2ao222_x1.ap b/pdks/symbolic/nsxlib/cells/noa2ao222_x1.ap new file mode 100644 index 000000000..620fb6c5a --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2ao222_x1.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 6 +H noa2ao222_x1,P,27/ 9/2019,100 +A 0,0,7000,10000 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 3000,5000,ref_ref,i4_25 +R 3000,4000,ref_ref,i4_20 +R 4000,6000,ref_ref,nq_30 +R 4000,5000,ref_ref,nq_25 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +R 5000,5000,ref_ref,i2_25 +R 5000,6000,ref_ref,i2_30 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 3000,7000,ref_ref,i4_35 +R 3000,6000,ref_ref,i4_30 +R 6000,7000,ref_ref,i3_35 +R 6000,6000,ref_ref,i3_30 +R 6000,5000,ref_ref,i3_25 +R 6000,4000,ref_ref,i3_20 +R 6000,3000,ref_ref,i3_15 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 1000,7000,ref_ref,i0_35 +R 2000,7000,ref_ref,i1_35 +R 4000,3000,ref_ref,nq_15 +R 4000,4000,ref_ref,nq_20 +S 4000,3100,4000,7000,300,*,UP,ALU1 +S 3700,4400,3700,5000,200,*,UP,POLY +S 600,1900,600,3300,400,*,UP,NDIF +S 700,1000,700,2000,400,*,UP,ALU1 +S 3000,2000,3000,3000,300,nq,UP,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S -300,7800,7300,7800,6000,*,RIGHT,NWELL +S 3000,5700,3000,8200,400,*,UP,PDIF +S 5400,5700,5400,9300,400,*,UP,PDIF +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 5800,1700,5800,3500,200,*,UP,NTRANS +S 600,5700,600,8200,400,*,UP,PDIF +S 2200,5100,2600,5100,200,*,RIGHT,POLY +S 4400,3900,4800,3900,200,*,RIGHT,POLY +S 4800,3900,4800,5200,200,*,UP,POLY +S 2200,3800,2200,5000,200,*,UP,POLY +S 1000,5500,1000,8400,200,*,UP,PTRANS +S 4400,1700,4400,3500,200,*,UP,NTRANS +S 2600,5500,2600,8400,200,*,UP,PTRANS +S 3700,5500,3700,9500,200,*,UP,PTRANS +S 4400,3600,4400,3900,200,*,UP,POLY +S 3700,5100,3700,5400,200,*,UP,POLY +S 2600,5100,2600,5400,200,*,UP,POLY +S 3000,2000,3000,2900,300,*,UP,ALU1 +S 1700,1900,1700,3300,200,*,UP,NDIF +S 2300,800,4100,800,600,*,RIGHT,PTIE +S 2200,1700,2200,3500,200,*,UP,NTRANS +S 4000,1900,4000,3300,400,*,UP,NDIF +S 3400,1700,3400,3500,200,*,UP,NTRANS +S 6300,1900,6300,3300,400,*,UP,NDIF +S 2800,1900,2800,3300,400,*,UP,NDIF +S 5800,5500,5800,9500,200,*,UP,PTRANS +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 3000,3000,4000,3000,300,*,RIGHT,ALU1 +S 3000,4100,3000,6900,300,*,UP,ALU1 +S 6000,3100,6000,6900,300,*,UP,ALU1 +S 700,8000,6100,8000,300,*,RIGHT,ALU1 +S 5100,1100,5100,3300,400,*,UP,NDIF +S 6300,5700,6300,9300,400,*,UP,PDIF +S 1000,4000,1000,5200,200,*,UP,POLY +S 1100,3700,1100,3900,200,*,UP,POLY +S 5800,3700,5800,5200,200,*,UP,POLY +S 1800,5700,1800,9200,600,*,UP,PDIF +S 1100,1700,1100,3500,200,*,UP,NTRANS +S 4200,5700,4200,9300,400,*,UP,PDIF +S 4100,2000,6100,2000,300,*,RIGHT,ALU1 +S 3000,4000,3000,6900,300,i4,UP,CALU1 +S 6000,3100,6000,6900,300,i3,UP,CALU1 +S 2000,3100,2000,6900,300,i1,UP,CALU1 +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 1000,3100,1000,6900,300,i0,UP,CALU1 +S 3300,3800,3300,4200,300,*,DOWN,POLY +S 3400,4300,3700,4300,200,*,LEFT,POLY +S 3400,3700,3400,4300,200,*,DOWN,POLY +S 4000,3100,4000,6200,300,nq,UP,CALU1 +S 5000,3100,5000,6200,300,i2,UP,CALU1 +S 5000,3100,5000,6200,300,*,UP,ALU1 +V 700,2000,CONT_DIF_N,* +V 4200,7000,CONT_DIF_P,* +V 1800,9400,CONT_DIF_P,* +V 6200,2000,CONT_DIF_N,* +V 4000,2000,CONT_DIF_N,* +V 2800,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 6200,8000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 4000,800,CONT_BODY_P,* +V 3200,800,CONT_BODY_P,* +V 2400,800,CONT_BODY_P,* +V 5100,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa2ao222_x1.vbe b/pdks/symbolic/nsxlib/cells/noa2ao222_x1.vbe new file mode 100644 index 000000000..034393fea --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2ao222_x1.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3210; + CONSTANT rdown_i1_nq : NATURAL := 3210; + CONSTANT rdown_i2_nq : NATURAL := 3210; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 5260; + CONSTANT rup_i1_nq : NATURAL := 5260; + CONSTANT rup_i2_nq : NATURAL := 5260; + CONSTANT rup_i3_nq : NATURAL := 5260; + CONSTANT rup_i4_nq : NATURAL := 3750; + CONSTANT tphl_i2_nq : NATURAL := 186; + CONSTANT tphl_i4_nq : NATURAL := 240; + CONSTANT tphl_i3_nq : NATURAL := 256; + CONSTANT tplh_i4_nq : NATURAL := 309; + CONSTANT tphl_i0_nq : NATURAL := 348; + CONSTANT tplh_i1_nq : NATURAL := 378; + CONSTANT tplh_i0_nq : NATURAL := 422; + CONSTANT tphl_i1_nq : NATURAL := 440; + CONSTANT tplh_i3_nq : NATURAL := 459; + CONSTANT tplh_i2_nq : NATURAL := 473; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x1; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa2ao222_x4.ap b/pdks/symbolic/nsxlib/cells/noa2ao222_x4.ap new file mode 100644 index 000000000..3041113ee --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2ao222_x4.ap @@ -0,0 +1,166 @@ +V ALLIANCE : 6 +H noa2ao222_x4,P,26/ 9/2019,100 +A 0,0,12000,10000 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 1000,7000,ref_ref,i0_35 +R 10000,8000,ref_ref,nq_40 +R 5000,5000,ref_ref,i2_25 +R 5000,4000,ref_ref,i2_20 +R 5000,3000,ref_ref,i2_15 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 3000,7000,ref_ref,i4_35 +R 5000,6000,ref_ref,i2_30 +R 6000,4000,ref_ref,i3_20 +R 6000,5000,ref_ref,i3_25 +R 6000,6000,ref_ref,i3_30 +R 10000,3000,ref_ref,nq_15 +R 10000,7000,ref_ref,nq_35 +R 10000,2000,ref_ref,nq_10 +R 10000,6000,ref_ref,nq_30 +R 10000,5000,ref_ref,nq_25 +R 10000,4000,ref_ref,nq_20 +R 3000,6000,ref_ref,i4_30 +R 3000,5000,ref_ref,i4_25 +R 3000,4000,ref_ref,i4_20 +S 6700,2500,6700,3300,400,*,UP,NDIF +S 600,1900,600,3300,400,*,UP,NDIF +S 3000,4300,3400,4300,200,*,LEFT,POLY +S 3400,4400,3400,5000,200,*,UP,POLY +S 7600,8300,7600,9100,600,*,UP,NTIE +S 6000,4100,6000,5900,300,*,UP,ALU1 +S 1800,5700,1800,9300,600,*,UP,PDIF +S 3700,5500,3700,9500,200,*,UP,PTRANS +S 2600,5500,2600,8400,200,*,UP,PTRANS +S 1000,5500,1000,8400,200,*,UP,PTRANS +S 6100,2300,6100,3500,200,*,UP,NTRANS +S 10100,1700,10100,3300,600,*,UP,NDIF +S 9600,1500,9600,3500,200,*,UP,NTRANS +S 10600,1500,10600,3500,200,*,UP,NTRANS +S 3100,3600,3100,4000,200,*,UP,POLY +S 6100,3600,6100,4000,200,*,UP,POLY +S 3400,5100,3700,5100,200,*,RIGHT,POLY +S 2000,5100,2600,5100,200,*,RIGHT,POLY +S 4700,2300,4700,3500,200,*,UP,NTRANS +S 3900,1900,3900,3300,600,*,UP,NDIF +S 2400,1900,2400,3300,400,*,UP,NDIF +S 3100,2300,3100,3500,200,*,UP,NTRANS +S 2900,2100,2900,2900,300,*,UP,ALU1 +S 1900,1700,1900,3500,200,*,UP,NTRANS +S 3700,5100,3700,5400,200,*,UP,POLY +S 11200,1700,11200,3300,400,*,UP,NDIF +S 5400,1100,5400,3300,400,*,UP,NDIF +S 7900,4000,8900,4000,300,*,RIGHT,ALU1 +S 7800,3100,7800,5900,300,*,UP,ALU1 +S 9400,4000,9400,5200,200,*,UP,POLY +S 9000,4000,10600,4000,400,*,RIGHT,POLY +S 6300,800,8900,800,600,*,RIGHT,PTIE +S 4800,4100,4800,5200,200,*,UP,POLY +S 4100,2000,6500,2000,300,*,RIGHT,ALU1 +S 2700,2000,2800,2000,300,*,RIGHT,ALU1 +S 5800,3900,5800,5200,200,*,UP,POLY +S 6600,2100,6600,3000,300,*,UP,ALU1 +S 7800,2700,7800,3300,600,*,UP,NDIF +S 4700,3700,4700,4100,200,*,UP,POLY +S 2600,5100,2600,5400,200,*,UP,POLY +S 1900,3900,1900,5100,200,*,UP,POLY +S 8900,1700,8900,3300,400,*,UP,NDIF +S 9000,700,9000,2900,300,*,UP,ALU1 +S 11000,700,11000,2900,300,*,UP,ALU1 +S 11000,6100,11000,9300,300,*,UP,ALU1 +S 11100,5700,11100,9300,400,*,UP,PDIF +S 8900,5700,8900,9300,400,*,UP,PDIF +S 9000,8100,9000,9300,300,*,UP,ALU1 +S -300,7800,12300,7800,6000,*,RIGHT,NWELL +S 5000,3100,5000,5900,300,*,UP,ALU1 +S 4200,5700,4200,9300,400,*,UP,PDIF +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 5400,5700,5400,9300,400,*,UP,PDIF +S 600,5700,600,8200,600,*,UP,PDIF +S 3000,5700,3000,8200,400,*,UP,PDIF +S 5800,5500,5800,9500,200,*,UP,PTRANS +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 3000,4100,3000,6900,300,*,UP,ALU1 +S 700,8000,6300,8000,300,*,RIGHT,ALU1 +S 6400,5700,6400,9300,600,*,UP,PDIF +S 2300,800,4100,800,600,*,RIGHT,PTIE +S 1900,3600,1900,4000,200,*,UP,POLY +S 9600,3700,9600,3900,200,*,UP,POLY +S 3100,3000,3900,3000,300,*,RIGHT,ALU1 +S 4000,3100,4000,6900,300,*,UP,ALU1 +S 4100,7000,4100,7000,300,*,LEFT,ALU1 +S 10000,2100,10000,7900,300,*,UP,ALU1 +S 8600,5100,8600,6900,300,*,UP,ALU1 +S 10600,3800,10600,5200,200,*,UP,POLY +S 8200,2500,8200,3500,200,*,UP,NTRANS +S 9400,5500,9400,9500,200,*,UP,PTRANS +S 10000,5700,10000,9300,600,*,UP,PDIF +S 7600,5700,7600,7300,600,*,UP,PDIF +S 8200,5500,8200,7500,200,*,UP,PTRANS +S 10600,5500,10600,9500,200,*,UP,PTRANS +S 4300,7000,8500,7000,300,*,RIGHT,ALU1 +S 1700,1900,1700,3300,200,*,UP,NDIF +S 0,600,12000,600,1200,vss,RIGHT,CALU1 +S 0,9400,12000,9400,1200,vdd,RIGHT,CALU1 +S 1100,1700,1100,3500,200,*,UP,NTRANS +S 600,1100,600,2000,400,*,UP,ALU1 +S 1000,4700,1100,4700,200,*,LEFT,POLY +S 1000,4700,1000,5400,200,*,DOWN,POLY +S 1100,3800,1100,4700,200,*,UP,POLY +S 10000,2100,10000,7900,300,nq,UP,CALU1 +S 6000,4100,6000,5900,300,i3,UP,CALU1 +S 5000,3100,5000,5900,300,i2,UP,CALU1 +S 3000,4100,3000,6900,300,i4,UP,CALU1 +S 2000,3100,2000,6900,300,i1,UP,CALU1 +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 1000,3100,1000,6900,300,i0,UP,CALU1 +S 8200,3800,8200,5400,200,*,UP,POLY +S 8300,4800,8300,5200,300,*,DOWN,POLY +V 6500,3000,CONT_DIF_N,* +V 8800,4000,CONT_POLY,* +V 7800,3000,CONT_DIF_N,* +V 10000,6000,CONT_DIF_P,* +V 7600,9200,CONT_BODY_N,* +V 10000,7000,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 10000,3000,CONT_DIF_N,* +V 10000,2000,CONT_DIF_N,* +V 8600,5000,CONT_POLY,* +V 2400,800,CONT_BODY_P,* +V 3200,800,CONT_BODY_P,* +V 4000,800,CONT_BODY_P,* +V 6000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 6400,8000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 11000,9200,CONT_DIF_P,* +V 9000,9200,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 11000,6000,CONT_DIF_P,* +V 11000,7000,CONT_DIF_P,* +V 11000,8000,CONT_DIF_P,* +V 11000,3000,CONT_DIF_N,* +V 11000,2000,CONT_DIF_N,* +V 9000,3000,CONT_DIF_N,* +V 9000,2000,CONT_DIF_N,* +V 2300,2000,CONT_DIF_N,* +V 3900,2000,CONT_DIF_N,* +V 1800,9400,CONT_DIF_P,* +V 7600,800,CONT_BODY_P,* +V 8600,800,CONT_BODY_P,* +V 6600,800,CONT_BODY_P,* +V 5000,4000,CONT_POLY,* +V 5400,800,CONT_DIF_N,* +V 7800,6000,CONT_DIF_P,* +V 700,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa2ao222_x4.vbe b/pdks/symbolic/nsxlib/cells/noa2ao222_x4.vbe new file mode 100644 index 000000000..89b9f12c5 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 638; + CONSTANT tplh_i4_nq : NATURAL := 664; + CONSTANT tphl_i0_nq : NATURAL := 684; + CONSTANT tphl_i4_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 732; + CONSTANT tplh_i1_nq : NATURAL := 758; + CONSTANT tphl_i1_nq : NATURAL := 780; + CONSTANT tplh_i3_nq : NATURAL := 795; + CONSTANT tplh_i0_nq : NATURAL := 801; + CONSTANT tplh_i2_nq : NATURAL := 809; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa3ao322_x1.ap b/pdks/symbolic/nsxlib/cells/noa3ao322_x1.ap new file mode 100644 index 000000000..15858414c --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa3ao322_x1.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H noa3ao322_x1,P,26/ 9/2019,100 +A 0,0,9000,10000 +R 6000,3000,ref_ref,i3_15 +R 5000,6000,ref_ref,nq_30 +R 5000,5000,ref_ref,nq_25 +R 6000,4000,ref_ref,i3_20 +R 6000,5000,ref_ref,i3_25 +R 6000,6000,ref_ref,i3_30 +R 7000,3000,ref_ref,i4_15 +R 7000,4000,ref_ref,i4_20 +R 7000,5000,ref_ref,i4_25 +R 7000,6000,ref_ref,i4_30 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 8000,7000,ref_ref,i5_35 +R 8000,6000,ref_ref,i5_30 +R 8000,3000,ref_ref,i5_15 +R 8000,4000,ref_ref,i5_20 +R 8000,5000,ref_ref,i5_25 +R 7000,7000,ref_ref,i4_35 +R 5000,4000,ref_ref,nq_20 +R 5000,3000,ref_ref,nq_15 +R 4000,7000,ref_ref,i6_35 +R 4000,6000,ref_ref,i6_30 +R 4000,5000,ref_ref,i6_25 +R 4000,4000,ref_ref,i6_20 +R 3000,7000,ref_ref,i2_35 +R 3000,6000,ref_ref,i2_30 +R 3000,5000,ref_ref,i2_25 +R 3000,4000,ref_ref,i2_20 +R 3000,3000,ref_ref,i2_15 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_10 +S 4800,4000,4800,5100,200,i6,UP,POLY +S 4000,3900,4800,3900,200,*,LEFT,POLY +S 6000,3100,6000,5900,300,i3,UP,CALU1 +S 5000,3100,5000,5900,300,nq,UP,CALU1 +S 1000,3100,1000,6900,300,i0,UP,CALU1 +S 5000,1900,5000,3300,400,*,UP,NDIF +S 600,8100,600,9300,300,*,UP,ALU1 +S 1900,8000,8300,8000,300,*,RIGHT,ALU1 +S 7000,3100,7000,6900,300,*,UP,ALU1 +S 2000,2100,2000,6900,300,*,UP,ALU1 +S 4000,2000,4000,2900,300,*,UP,ALU1 +S 6000,3100,6000,5900,300,*,UP,ALU1 +S 3000,3100,3000,6900,300,*,UP,ALU1 +S 4000,3000,5000,3000,300,*,RIGHT,ALU1 +S 4400,1700,4400,3500,200,*,UP,NTRANS +S 6400,5700,6400,9300,400,*,UP,PDIF +S 5800,5500,5800,9500,200,*,UP,PTRANS +S 5200,5700,5200,9300,400,*,UP,PDIF +S 6800,5500,6800,9500,200,*,UP,PTRANS +S 6800,1700,6800,3500,200,*,UP,NTRANS +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 3600,5500,3600,8500,200,*,UP,PTRANS +S 3700,1300,3700,3300,400,*,UP,NDIF +S 2100,5500,2100,8500,200,*,UP,PTRANS +S 7800,1700,7800,3500,200,*,UP,NTRANS +S 7200,1900,7200,3300,600,*,UP,NDIF +S -300,7800,9300,7800,6000,*,RIGHT,NWELL +S 7800,5500,7800,9500,200,*,UP,PTRANS +S 8400,5700,8400,9300,600,*,UP,PDIF +S 5400,1700,5400,3500,200,*,UP,NTRANS +S 4100,5700,4100,8300,400,*,UP,PDIF +S 2700,5700,2700,8300,600,*,UP,PDIF +S 2700,1300,2700,3300,200,*,UP,NDIF +S 1700,1300,1700,3300,200,*,UP,NDIF +S 7300,5700,7300,9300,200,*,UP,PDIF +S 2900,5700,2900,9200,400,*,UP,PDIF +S 600,5700,600,8300,600,*,UP,PDIF +S 1200,5500,1200,8500,200,*,UP,PTRANS +S 8400,700,8400,1900,300,*,UP,ALU1 +S 2100,5100,2100,5400,200,*,UP,POLY +S 1200,1100,1200,3500,200,*,UP,NTRANS +S 700,1300,700,3300,400,*,UP,NDIF +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 7300,800,8300,800,600,*,RIGHT,PTIE +S 2200,1100,2200,3500,200,*,UP,NTRANS +S 3200,1100,3200,3500,200,*,UP,NTRANS +S 4000,4100,4000,6900,300,*,UP,ALU1 +S 5100,2000,7100,2000,300,*,RIGHT,ALU1 +S 8000,3100,8000,6900,300,*,UP,ALU1 +S 8400,1900,8400,3300,600,*,UP,NDIF +S 2100,5100,2200,5100,200,*,RIGHT,POLY +S 5400,3600,5400,3900,200,*,UP,POLY +S 4800,5100,4800,5400,200,*,UP,POLY +S 3600,5100,3600,5400,200,*,UP,POLY +S 5400,3900,5600,3900,200,*,RIGHT,POLY +S 3200,5100,3600,5100,200,*,RIGHT,POLY +S 6100,1000,6100,3300,400,*,UP,NDIF +S 800,1300,800,1900,300,*,UP,ALU1 +S 7800,3800,7800,5200,200,i5,UP,POLY +S 6800,3800,6800,5200,200,i4,UP,POLY +S 5800,3900,5800,5300,200,i3,UP,POLY +S 3200,3800,3200,5100,200,i2,UP,POLY +S 2200,3800,2200,5000,200,i1,UP,POLY +S 1200,3800,1200,5200,200,i0,UP,POLY +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 4000,4000,4000,6900,300,i6,UP,CALU1 +S 8000,3100,8000,6900,300,i5,UP,CALU1 +S 7000,3100,7000,6900,300,i4,UP,CALU1 +S 5000,3100,5000,6900,300,*,UP,ALU1 +S 3000,3100,3000,6900,300,i2,UP,CALU1 +S 2000,2100,2000,6900,300,i1,UP,CALU1 +S 4000,3800,4400,3800,200,*,LEFT,POLY +V 2900,9400,CONT_DIF_P,* +V 8400,2000,CONT_DIF_N,* +V 8000,4000,CONT_POLY,* +V 7200,2000,CONT_DIF_N,* +V 7000,5000,CONT_POLY,* +V 6000,5000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 600,8000,CONT_DIF_P,* +V 8400,8000,CONT_DIF_P,* +V 5200,7000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 3800,2000,CONT_DIF_N,* +V 2000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 8200,800,CONT_BODY_P,* +V 7400,800,CONT_BODY_P,* +V 800,1900,CONT_DIF_N,* +V 6100,900,CONT_DIF_N,* +V 1600,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa3ao322_x1.vbe b/pdks/symbolic/nsxlib/cells/noa3ao322_x1.vbe new file mode 100644 index 000000000..ff0227769 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa3ao322_x1.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3370; + CONSTANT rdown_i1_nq : NATURAL := 3370; + CONSTANT rdown_i2_nq : NATURAL := 3370; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rdown_i5_nq : NATURAL := 3210; + CONSTANT rdown_i6_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 6700; + CONSTANT rup_i1_nq : NATURAL := 6700; + CONSTANT rup_i2_nq : NATURAL := 6700; + CONSTANT rup_i3_nq : NATURAL := 6700; + CONSTANT rup_i4_nq : NATURAL := 6700; + CONSTANT rup_i5_nq : NATURAL := 6700; + CONSTANT rup_i6_nq : NATURAL := 3690; + CONSTANT tphl_i3_nq : NATURAL := 196; + CONSTANT tphl_i6_nq : NATURAL := 246; + CONSTANT tphl_i4_nq : NATURAL := 264; + CONSTANT tplh_i6_nq : NATURAL := 311; + CONSTANT tphl_i5_nq : NATURAL := 328; + CONSTANT tphl_i0_nq : NATURAL := 396; + CONSTANT tphl_i1_nq : NATURAL := 486; + CONSTANT tplh_i2_nq : NATURAL := 488; + CONSTANT tphl_i2_nq : NATURAL := 546; + CONSTANT tplh_i1_nq : NATURAL := 552; + CONSTANT tplh_i5_nq : NATURAL := 581; + CONSTANT tplh_i3_nq : NATURAL := 599; + CONSTANT tplh_i4_nq : NATURAL := 608; + CONSTANT tplh_i0_nq : NATURAL := 616; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x1; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/noa3ao322_x4.ap b/pdks/symbolic/nsxlib/cells/noa3ao322_x4.ap new file mode 100644 index 000000000..2d6dc9856 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa3ao322_x4.ap @@ -0,0 +1,188 @@ +V ALLIANCE : 6 +H noa3ao322_x4,P,25/ 9/2019,100 +A 0,0,13000,10000 +R 7000,6000,ref_ref,i2_30 +R 7000,5000,ref_ref,i2_25 +R 10000,5000,ref_ref,i3_25 +R 10000,4000,ref_ref,i3_20 +R 10000,3000,ref_ref,i3_15 +R 5000,7000,ref_ref,i0_35 +R 3000,8000,ref_ref,nq_40 +R 3000,2000,ref_ref,nq_10 +R 3000,3000,ref_ref,nq_15 +R 3000,4000,ref_ref,nq_20 +R 3000,5000,ref_ref,nq_25 +R 3000,6000,ref_ref,nq_30 +R 11000,6000,ref_ref,i4_30 +R 11000,7000,ref_ref,i4_35 +R 12000,3000,ref_ref,i5_15 +R 12000,4000,ref_ref,i5_20 +R 6000,4000,ref_ref,i1_20 +R 6000,3000,ref_ref,i1_15 +R 3000,7000,ref_ref,nq_35 +R 7000,4000,ref_ref,i2_20 +R 7000,7000,ref_ref,i2_35 +R 6000,5000,ref_ref,i1_25 +R 6000,6000,ref_ref,i1_30 +R 6000,7000,ref_ref,i1_35 +R 11000,4000,ref_ref,i4_20 +R 11000,3000,ref_ref,i4_15 +R 10000,6000,ref_ref,i3_30 +R 5000,6000,ref_ref,i0_30 +R 5000,5000,ref_ref,i0_25 +R 5000,4000,ref_ref,i0_20 +R 5000,3000,ref_ref,i0_15 +R 12000,7000,ref_ref,i5_35 +R 12000,6000,ref_ref,i5_30 +R 12000,5000,ref_ref,i5_25 +R 10000,7000,ref_ref,i3_35 +R 11000,5000,ref_ref,i4_25 +R 8000,4000,ref_ref,i6_20 +R 8000,5000,ref_ref,i6_25 +R 8000,6000,ref_ref,i6_30 +R 8000,7000,ref_ref,i6_35 +S 8000,4100,8400,4100,400,*,RIGHT,POLY +S 3600,3000,3600,3100,200,*,UP,POLY +S 2000,3200,3600,3200,200,*,RIGHT,POLY +S 3600,5200,3600,5400,200,*,UP,POLY +S 2400,5200,2400,5300,200,*,UP,POLY +S 2000,5200,3600,5200,200,*,RIGHT,POLY +S 700,8600,700,9000,600,*,UP,NTIE +S 5200,1700,5200,3300,200,*,UP,NTRANS +S 6100,1700,6100,3300,200,*,UP,NTRANS +S 6700,6500,6700,8900,400,*,UP,PDIF +S 7400,6100,7400,8500,200,*,UP,PTRANS +S 7900,6300,7900,8300,400,*,UP,PDIF +S 9300,2800,9300,3800,200,*,UP,POLY +S 9300,1700,9300,2500,200,*,UP,NTRANS +S 10100,900,10100,2300,600,*,UP,NDIF +S 10900,2800,10900,4600,200,*,UP,POLY +S 10900,1700,10900,2500,200,*,UP,NTRANS +S 6000,6300,6000,8500,200,*,UP,PTRANS +S 11800,5500,11800,8500,200,*,UP,PTRANS +S 4800,6300,4800,8500,200,*,UP,PTRANS +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 3000,5700,3000,9300,600,*,UP,PDIF +S 5400,6500,5400,8300,600,*,UP,PDIF +S 9800,5500,9800,8500,200,*,UP,PTRANS +S 2400,900,2400,2900,200,*,UP,NTRANS +S 3600,900,3600,2900,200,*,UP,NTRANS +S 3000,1100,3000,2700,600,*,UP,NDIF +S 11800,1700,11800,2500,200,*,UP,NTRANS +S 7000,1700,7000,3300,200,*,UP,NTRANS +S 7600,1900,7600,2700,400,*,UP,NDIF +S 8200,1700,8200,2900,200,*,UP,NTRANS +S 5500,800,8700,800,600,*,RIGHT,PTIE +S 1200,4200,4000,4200,200,*,RIGHT,POLY +S 8200,3200,8200,3800,200,*,UP,POLY +S 5200,3600,5200,4000,200,*,UP,POLY +S 4400,900,4400,3100,600,*,UP,NDIF +S 4100,5700,4100,9300,400,*,UP,PDIF +S 7200,5700,7400,5700,200,*,RIGHT,POLY +S 2400,3000,2400,3200,200,*,UP,POLY +S 7400,5700,7400,5900,200,*,UP,POLY +S 9400,3800,9800,3800,200,*,RIGHT,POLY +S 7000,3600,7000,4000,200,*,UP,POLY +S 4800,3800,5000,3800,200,*,RIGHT,POLY +S 4800,3800,4800,6000,200,*,UP,POLY +S 11800,2800,11800,4000,200,*,UP,POLY +S 9800,3800,9800,5200,200,*,UP,POLY +S 12400,700,12400,1900,300,*,UP,ALU1 +S 700,5000,1900,5000,300,*,RIGHT,ALU1 +S 700,3400,1900,3400,300,*,RIGHT,ALU1 +S 7000,4100,7000,6900,300,*,UP,ALU1 +S 700,5700,700,7700,400,*,UP,PDIF +S 2000,1300,2000,2300,300,*,UP,ALU1 +S 11300,5700,11300,8300,200,*,UP,PDIF +S 8500,1900,8500,2700,400,*,UP,NDIF +S 2000,1100,2000,2700,600,*,UP,NDIF +S 1200,1500,1200,2900,200,*,UP,NTRANS +S 700,1700,700,2700,400,*,UP,NDIF +S 12300,1900,12300,2300,400,*,UP,NDIF +S 12300,5700,12300,8300,400,*,UP,PDIF +S 2000,6100,2000,8900,300,*,UP,ALU1 +S 700,2500,700,6900,300,*,UP,ALU1 +S 8400,5500,8400,8500,200,*,UP,PTRANS +S 6000,4100,6000,6000,200,*,UP,POLY +S 6100,3600,6100,4000,200,*,UP,POLY +S 10900,5500,10900,8500,200,*,UP,PTRANS +S 8800,1900,8800,2300,600,*,UP,NDIF +S 9100,5700,9100,8300,400,*,UP,PDIF +S 1200,3200,1200,5200,200,*,UP,POLY +S 1900,5700,1900,9300,400,*,UP,PDIF +S 1200,5500,1200,7900,200,*,UP,PTRANS +S 9400,5700,9400,8300,200,*,UP,PDIF +S 10300,5700,10300,8300,200,*,UP,PDIF +S -300,7800,13300,7800,6000,*,RIGHT,NWELL +S 6500,1900,6500,3100,200,*,UP,NDIF +S 5500,1900,5500,3100,200,*,UP,NDIF +S 4000,1100,4000,2700,200,*,UP,NDIF +S 4000,2100,4000,3900,300,*,UP,ALU1 +S 5500,8000,12300,8000,300,*,RIGHT,ALU1 +S 12000,3100,12000,6900,300,*,UP,ALU1 +S 8000,4100,8000,6900,300,*,UP,ALU1 +S 11000,3100,11000,6900,300,*,UP,ALU1 +S 6000,3100,6000,6900,300,*,UP,ALU1 +S 5000,3100,5000,6900,300,*,UP,ALU1 +S 7600,2100,7600,2900,300,*,UP,ALU1 +S 7700,3000,8900,3000,300,*,RIGHT,ALU1 +S 4200,8100,4200,9300,300,*,UP,ALU1 +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 4100,2000,7500,2000,300,*,RIGHT,ALU1 +S 9000,3100,9000,6900,300,*,UP,ALU1 +S 10000,3100,10000,6900,300,*,UP,ALU1 +S 8900,2000,11100,2000,300,*,RIGHT,ALU1 +S 8400,4000,8400,5800,200,i6,UP,POLY +S 11800,3800,11800,5200,200,i5,UP,POLY +S 10900,4800,10900,5200,200,i4,UP,POLY +S 7200,4000,7200,5700,200,i2,UP,POLY +S 0,600,13000,600,1200,vss,RIGHT,CALU1 +S 0,9400,13000,9400,1200,vdd,RIGHT,CALU1 +S 12000,3100,12000,6900,300,i5,UP,CALU1 +S 11000,3100,11000,6900,300,i4,UP,CALU1 +S 10000,3100,10000,6900,300,i3,UP,CALU1 +S 8000,4100,8000,6900,300,i6,UP,CALU1 +S 7000,4100,7000,6900,300,i2,UP,CALU1 +S 6000,3100,6000,6900,300,i1,UP,CALU1 +S 5000,3100,5000,6900,300,i0,UP,CALU1 +S 3000,2100,3000,7900,300,nq,UP,CALU1 +V 9000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 11000,5000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 4000,4100,CONT_POLY,* +V 11300,2000,CONT_DIF_N,* +V 800,6000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 2000,9200,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,6000,CONT_DIF_P,* +V 700,9100,CONT_BODY_N,* +V 12200,8000,CONT_DIF_P,* +V 12200,2000,CONT_DIF_N,* +V 800,2400,CONT_DIF_N,* +V 2000,1400,CONT_DIF_N,* +V 2000,2400,CONT_DIF_N,* +V 12000,4000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +V 10000,5000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 7000,4000,CONT_POLY,* +V 7600,800,CONT_BODY_P,* +V 7600,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 8800,2000,CONT_DIF_N,* +V 3000,7000,CONT_DIF_P,* +V 7800,8000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 6700,9300,CONT_DIF_P,* +V 10100,800,CONT_DIF_N,* +V 4400,800,CONT_DIF_N,* +V 2000,3400,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/noa3ao322_x4.vbe b/pdks/symbolic/nsxlib/cells/noa3ao322_x4.vbe new file mode 100644 index 000000000..1fc4b8a6f --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/noa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT tplh_i6_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 729; + CONSTANT tphl_i6_nq : NATURAL := 738; + CONSTANT tphl_i0_nq : NATURAL := 819; + CONSTANT tphl_i4_nq : NATURAL := 821; + CONSTANT tplh_i2_nq : NATURAL := 874; + CONSTANT tplh_i5_nq : NATURAL := 900; + CONSTANT tphl_i5_nq : NATURAL := 907; + CONSTANT tphl_i1_nq : NATURAL := 914; + CONSTANT tplh_i4_nq : NATURAL := 924; + CONSTANT tplh_i3_nq : NATURAL := 926; + CONSTANT tplh_i1_nq : NATURAL := 931; + CONSTANT tplh_i0_nq : NATURAL := 987; + CONSTANT tphl_i2_nq : NATURAL := 990; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1600 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/nts_x1.ap b/pdks/symbolic/nsxlib/cells/nts_x1.ap new file mode 100644 index 000000000..229e13d2e --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nts_x1.ap @@ -0,0 +1,77 @@ +V ALLIANCE : 6 +H nts_x1,P,18/ 9/2019,100 +A 0,0,6000,10000 +R 2000,4000,ref_ref,cmd_20 +R 2000,3000,ref_ref,cmd_15 +R 2000,2000,ref_ref,cmd_10 +R 3000,2000,ref_ref,nq_10 +R 3000,8000,ref_ref,nq_40 +R 3000,7000,ref_ref,nq_35 +R 3000,6000,ref_ref,nq_30 +R 3000,4000,ref_ref,nq_20 +R 3000,3000,ref_ref,nq_15 +R 1000,7000,ref_ref,i_35 +R 1000,6000,ref_ref,i_30 +R 1000,2000,ref_ref,i_10 +R 1000,3000,ref_ref,i_15 +R 1000,4000,ref_ref,i_20 +R 1000,5000,ref_ref,i_25 +R 3000,5000,ref_ref,nq_25 +R 1000,8000,ref_ref,i_40 +R 2000,5000,ref_ref,cmd_25 +R 2000,6000,ref_ref,cmd_30 +R 2000,7000,ref_ref,cmd_35 +R 2000,8000,ref_ref,cmd_40 +S 1000,2100,1000,7900,300,i,UP,CALU1 +S 2000,2100,2000,7900,300,cmd,UP,CALU1 +S 3000,2100,3000,7900,300,nq,UP,CALU1 +S 1200,600,1200,2500,200,*,UP,NTRANS +S 700,800,700,2300,400,*,UP,NDIF +S 1800,800,1800,2300,600,*,UP,NDIF +S 3000,800,3000,2300,600,*,UP,NDIF +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 4800,1500,4800,2500,200,*,UP,NTRANS +S 4200,1700,4200,2300,600,*,UP,NDIF +S 4800,2800,4800,5200,200,*,UP,POLY +S 4200,2100,4200,6900,300,*,UP,ALU1 +S -300,7800,6300,7800,6000,*,RIGHT,NWELL +S 4200,5700,4200,7300,600,*,UP,PDIF +S 1800,5700,1800,9300,600,*,UP,PDIF +S 3000,5700,3000,9300,600,*,UP,PDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 4800,5500,4800,7500,200,*,UP,PTRANS +S 1000,2100,1000,7900,300,*,UP,ALU1 +S 1200,2800,1200,5200,200,*,UP,POLY +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 2000,4000,4800,4000,200,*,RIGHT,POLY +S 700,5700,700,9300,400,*,UP,PDIF +S 5200,700,5200,1900,300,*,UP,ALU1 +S 5300,1700,5300,2300,400,*,UP,NDIF +S 5200,6100,5200,9300,300,*,UP,ALU1 +S 5300,5700,5300,7300,400,*,UP,PDIF +S 2300,2800,2300,4000,200,*,UP,POLY +S 2300,600,2300,2500,200,*,UP,NTRANS +S 2400,5100,4000,5100,200,*,RIGHT,POLY +S 2400,5200,2400,5400,200,*,UP,POLY +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 3900,9200,5100,9200,600,*,RIGHT,NTIE +V 3000,8000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 4200,2000,CONT_DIF_N,* +V 800,9200,CONT_DIF_P,* +V 4200,5100,CONT_POLY,* +V 5200,2000,CONT_DIF_N,* +V 800,900,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 4200,6000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +V 5100,9200,CONT_BODY_N,* +V 5200,6000,CONT_DIF_P,* +V 5200,7000,CONT_DIF_P,* +V 4300,9200,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/nts_x1.vbe b/pdks/symbolic/nsxlib/cells/nts_x1.vbe new file mode 100644 index 000000000..f6cada4ad --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nts_x1.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_cmd : NATURAL := 14; + CONSTANT cin_i : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i_nq : NATURAL := 3210; + CONSTANT tphl_cmd_nq : NATURAL := 41; + CONSTANT tphl_i_nq : NATURAL := 169; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 249; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x1; + +ARCHITECTURE behaviour_data_flow OF nts_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x1" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 800 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/nsxlib/cells/nts_x2.ap b/pdks/symbolic/nsxlib/cells/nts_x2.ap new file mode 100644 index 000000000..85127ed93 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nts_x2.ap @@ -0,0 +1,97 @@ +V ALLIANCE : 6 +H nts_x2,P,25/ 9/2019,100 +A 0,0,8000,10000 +R 3000,4000,ref_ref,nq_20 +R 3000,5000,ref_ref,nq_25 +R 3000,6000,ref_ref,nq_30 +R 3000,3000,ref_ref,nq_15 +R 3000,2000,ref_ref,nq_10 +R 6000,4000,ref_ref,cmd_20 +R 6000,3000,ref_ref,cmd_15 +R 6000,2000,ref_ref,cmd_10 +R 6000,5000,ref_ref,cmd_25 +R 3000,7000,ref_ref,nq_35 +R 6000,7000,ref_ref,cmd_35 +R 6000,6000,ref_ref,cmd_30 +R 3000,8000,ref_ref,nq_40 +R 2000,2000,ref_ref,i_10 +R 2000,3000,ref_ref,i_15 +R 2000,4000,ref_ref,i_20 +R 2000,5000,ref_ref,i_25 +R 2000,6000,ref_ref,i_30 +R 2000,7000,ref_ref,i_35 +R 2000,8000,ref_ref,i_40 +S 7200,8300,7200,9000,600,*,UP,NTIE +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 3000,5700,3000,9300,600,*,UP,PDIF +S 1800,5700,1800,9300,600,*,UP,PDIF +S 1200,2800,1200,5200,200,*,UP,POLY +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 4800,2800,4800,5200,200,*,UP,POLY +S 5600,800,5600,2300,600,*,UP,NDIF +S 5900,5700,5900,9300,400,*,UP,PDIF +S 6400,2900,6600,2900,200,*,RIGHT,POLY +S 2400,2900,4000,2900,200,*,RIGHT,POLY +S 2400,5100,4000,5100,200,*,RIGHT,POLY +S 6600,3000,6600,5200,200,*,UP,POLY +S 3600,2600,3600,2900,200,*,UP,POLY +S 2400,2500,2400,2900,200,*,UP,POLY +S 2400,5100,2400,5400,200,*,UP,POLY +S 3600,5100,3600,5400,200,*,UP,POLY +S 6000,2100,6000,6900,300,*,UP,ALU1 +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 3000,800,3000,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 4200,800,4200,2300,600,*,UP,NDIF +S 4800,600,4800,2500,200,*,UP,NTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 5400,5700,5400,9300,600,*,UP,PDIF +S -300,7800,8300,7800,6000,*,RIGHT,NWELL +S 4100,3000,5900,3000,300,*,RIGHT,ALU1 +S 4100,8000,7300,8000,300,*,RIGHT,ALU1 +S 4000,5100,4000,7900,300,*,UP,ALU1 +S 1200,600,1200,2500,200,*,UP,NTRANS +S 1800,800,1800,2300,600,*,UP,NDIF +S 700,800,700,2300,400,*,UP,NDIF +S 6000,4000,6600,4000,400,*,RIGHT,POLY +S 6600,5500,6600,7500,200,*,UP,PTRANS +S 800,1100,800,1900,300,*,UP,ALU1 +S 7300,2100,7300,7900,300,*,UP,ALU1 +S 7300,5700,7300,7300,400,*,UP,PDIF +S 7100,1700,7100,2300,400,*,UP,NDIF +S 6400,2700,6400,2900,200,*,UP,POLY +S 2400,600,2400,2500,200,*,UP,NTRANS +S 1200,4000,4800,4000,200,*,RIGHT,POLY +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 800,6100,800,8900,300,*,UP,ALU1 +S 700,5700,700,9300,400,*,UP,PDIF +S 6400,1500,6400,2500,200,*,UP,NTRANS +S 6000,2100,6000,6900,300,cmd,UP,CALU1 +S 3000,2100,3000,7900,300,nq,UP,CALU1 +S 2000,2100,2000,7900,300,i,UP,CALU1 +V 4000,4900,CONT_POLY,* +V 4200,3000,CONT_POLY,* +V 800,9200,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 6000,4000,CONT_POLY,* +V 800,900,CONT_DIF_N,* +V 5400,900,CONT_DIF_N,* +V 7200,9200,CONT_BODY_N,* +V 7000,6000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 6000,9200,CONT_DIF_P,* +V 5200,9200,CONT_DIF_P,* +V 7100,2000,CONT_DIF_N,* +V 800,6000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/nts_x2.vbe b/pdks/symbolic/nsxlib/cells/nts_x2.vbe new file mode 100644 index 000000000..4bb47086f --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nts_x2.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_cmd : NATURAL := 18; + CONSTANT cin_i : NATURAL := 28; + CONSTANT rdown_cmd_nq : NATURAL := 1430; + CONSTANT rdown_i_nq : NATURAL := 1430; + CONSTANT rup_cmd_nq : NATURAL := 1600; + CONSTANT rup_i_nq : NATURAL := 1600; + CONSTANT tphl_cmd_nq : NATURAL := 33; + CONSTANT tphl_i_nq : NATURAL := 167; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 330; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x2; + +ARCHITECTURE behaviour_data_flow OF nts_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x2" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 900 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/nsxlib/cells/nxr2_x1.ap b/pdks/symbolic/nsxlib/cells/nxr2_x1.ap new file mode 100644 index 000000000..54bdf3fba --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nxr2_x1.ap @@ -0,0 +1,117 @@ +V ALLIANCE : 6 +H nxr2_x1,P,26/ 9/2019,100 +A 0,0,9000,10000 +R 2000,4000,ref_ref,i0_20 +R 2000,6000,ref_ref,i0_30 +R 2000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i0_40 +R 3000,6000,ref_ref,nq_30 +R 3000,7000,ref_ref,nq_35 +R 3000,2000,ref_ref,nq_10 +R 3000,3000,ref_ref,nq_15 +R 3000,4000,ref_ref,nq_20 +R 3000,5000,ref_ref,nq_25 +R 7000,6000,ref_ref,i1_30 +R 7000,5000,ref_ref,i1_25 +R 7000,4000,ref_ref,i1_20 +R 7000,3000,ref_ref,i1_15 +R 7000,2000,ref_ref,i1_10 +R 2000,2000,ref_ref,i0_10 +R 2000,3000,ref_ref,i0_15 +R 2000,5000,ref_ref,i0_25 +R 7000,8000,ref_ref,i1_40 +R 7000,7000,ref_ref,i1_35 +S 2400,5200,2400,5500,200,*,UP,POLY +S 1200,5200,2400,5200,200,*,RIGHT,POLY +S 2400,2500,2400,2800,200,*,UP,POLY +S 1200,2500,1200,2800,200,*,UP,POLY +S 1200,2800,2400,2800,200,*,RIGHT,POLY +S 6000,2700,6000,2800,200,*,UP,POLY +S 7400,2600,7400,2700,200,*,UP,POLY +S 6000,2800,7400,2800,200,*,RIGHT,POLY +S 6900,5200,7400,5200,200,*,RIGHT,POLY +S 7000,2100,7000,7900,300,i1,UP,CALU1 +S 3000,2100,3000,6900,300,nq,UP,CALU1 +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 2000,2100,2000,7900,300,i0,UP,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 800,2100,800,6900,300,*,UP,ALU1 +S 800,7100,800,7900,300,*,UP,ALU1 +S 700,6700,700,8300,400,*,UP,PDIF +S 700,1700,700,2300,400,*,UP,NDIF +S 7400,6500,7400,8500,200,*,UP,PTRANS +S 7400,1500,7400,2500,200,*,UP,NTRANS +S -300,7800,9300,7800,6000,*,RIGHT,NWELL +S 3100,8000,5300,8000,300,*,RIGHT,ALU1 +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 600,4000,4800,4000,200,*,RIGHT,POLY +S 4800,2800,4800,5200,200,*,UP,POLY +S 1200,5200,1200,6200,200,*,UP,POLY +S 6000,5500,6000,9500,200,*,UP,PTRANS +S 5400,5700,5400,9300,600,*,UP,PDIF +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 3000,5700,3000,9300,600,*,UP,PDIF +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 6600,5700,6600,9300,600,*,UP,PDIF +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 3600,600,3600,2500,200,*,UP,NTRANS +S 7000,2100,7000,7900,300,*,UP,ALU1 +S 6000,4000,8000,4000,200,*,RIGHT,POLY +S 8000,2100,8000,6900,300,*,UP,ALU1 +S 8000,6700,8000,8300,600,*,UP,PDIF +S 8000,1700,8000,2300,600,*,UP,NDIF +S 6000,4000,6000,5200,200,*,UP,POLY +S 4100,5000,6900,5000,300,*,RIGHT,ALU1 +S 4100,3000,4900,3000,300,*,RIGHT,ALU1 +S 1900,800,1900,2300,400,*,UP,NDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S 7600,1700,7600,2300,200,*,UP,NDIF +S 7600,6700,7600,8300,200,*,UP,PDIF +S 5400,6100,5400,7900,300,*,UP,ALU1 +S 8000,7100,8000,7900,300,*,UP,ALU1 +S 3000,2000,4100,2000,300,*,RIGHT,ALU1 +S 3000,7000,4100,7000,300,*,RIGHT,ALU1 +S 5100,4000,5900,4000,300,*,RIGHT,ALU1 +S 5000,3100,5000,3900,300,*,UP,ALU1 +S 3600,2600,3600,2900,200,*,UP,POLY +S 3600,5100,3600,5400,200,*,UP,POLY +S 7400,5200,7400,6200,200,*,UP,POLY +S 3600,5100,4100,5100,200,*,RIGHT,POLY +S 3000,800,3000,2300,600,*,UP,NDIF +S 3600,2900,4100,2900,200,*,RIGHT,POLY +S 1900,5700,1900,9300,400,*,UP,PDIF +S 6600,800,6600,2300,600,*,UP,NDIF +S 6000,600,6000,2500,200,*,UP,NTRANS +S 5400,800,5400,2300,600,*,UP,NDIF +S 4200,800,4200,2300,600,*,UP,NDIF +S 4800,600,4800,2500,200,*,UP,NTRANS +V 2000,3000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 7000,3000,CONT_POLY,* +V 7000,5000,CONT_POLY,* +V 8000,7000,CONT_DIF_P,* +V 8000,2000,CONT_DIF_N,* +V 6000,4000,CONT_POLY,* +V 8000,8000,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,* +V 5400,6000,CONT_DIF_P,* +V 2000,900,CONT_DIF_N,* +V 6600,900,CONT_DIF_N,* +V 600,4000,CONT_POLY,* +V 800,2000,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 2000,9200,CONT_DIF_P,* +V 6600,9200,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 8000,4000,CONT_POLY,* +V 4200,7000,CONT_DIF_P,* +V 4200,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 4200,5000,CONT_POLY,* +V 4200,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/nxr2_x1.vbe b/pdks/symbolic/nsxlib/cells/nxr2_x1.vbe new file mode 100644 index 000000000..1c89dd228 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nxr2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY nxr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i1_nq : NATURAL := 156; + CONSTANT tphl_i0_nq : NATURAL := 288; + CONSTANT tplh_i0_nq : NATURAL := 293; + CONSTANT tplh_i1_nq : NATURAL := 327; + CONSTANT tphh_i0_nq : NATURAL := 366; + CONSTANT tpll_i0_nq : NATURAL := 389; + CONSTANT tphh_i1_nq : NATURAL := 395; + CONSTANT tpll_i1_nq : NATURAL := 503; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x1; + +ARCHITECTURE behaviour_data_flow OF nxr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x1" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/nxr2_x4.ap b/pdks/symbolic/nsxlib/cells/nxr2_x4.ap new file mode 100644 index 000000000..7c5ef305d --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nxr2_x4.ap @@ -0,0 +1,140 @@ +V ALLIANCE : 6 +H nxr2_x4,P,26/ 9/2019,100 +A 0,0,12000,10000 +R 2000,2000,ref_ref,i0_10 +R 7000,7000,ref_ref,i1_35 +R 7000,8000,ref_ref,i1_40 +R 10000,3000,ref_ref,nq_15 +R 10000,4000,ref_ref,nq_20 +R 10000,5000,ref_ref,nq_25 +R 2000,8000,ref_ref,i0_40 +R 7000,3000,ref_ref,i1_15 +R 7000,4000,ref_ref,i1_20 +R 7000,5000,ref_ref,i1_25 +R 7000,6000,ref_ref,i1_30 +R 2000,3000,ref_ref,i0_15 +R 2000,5000,ref_ref,i0_25 +R 2000,4000,ref_ref,i0_20 +R 2000,6000,ref_ref,i0_30 +R 2000,7000,ref_ref,i0_35 +S 7800,8300,7800,9100,600,*,UP,NTIE +S 800,8300,800,9100,600,*,UP,NTIE +S 0,9400,12000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,12000,600,1200,vss,RIGHT,CALU1 +S 7200,5200,7200,5400,200,*,UP,POLY +S 6000,5200,6000,5400,200,*,UP,POLY +S 3600,5200,3600,5300,200,*,UP,POLY +S 3600,2600,3600,2900,200,*,UP,POLY +S 3600,5100,4100,5100,200,*,RIGHT,POLY +S 6000,5100,7200,5100,200,*,RIGHT,POLY +S 3600,2900,4100,2900,200,*,RIGHT,POLY +S 7200,2700,7200,3100,200,*,UP,POLY +S 6500,5700,6500,9300,400,*,UP,PDIF +S 1900,5700,1900,9300,400,*,UP,PDIF +S 700,5700,700,7300,400,*,UP,PDIF +S 800,2100,800,5900,300,*,UP,ALU1 +S 7900,1700,7900,3100,400,*,UP,NDIF +S 11200,1100,11200,1900,300,*,UP,ALU1 +S 11300,5700,11300,9300,400,*,UP,PDIF +S 11200,6100,11200,8900,300,*,UP,ALU1 +S 10000,2100,10000,7900,300,*,UP,ALU1 +S -300,7800,12300,7800,6000,*,RIGHT,NWELL +S 3100,8000,5300,8000,300,*,RIGHT,ALU1 +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 4800,2800,4800,5200,200,*,UP,POLY +S 6000,5500,6000,9500,200,*,UP,PTRANS +S 5400,5700,5400,9300,600,*,UP,PDIF +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 3000,5700,3000,9300,600,*,UP,PDIF +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 7200,1500,7200,2500,200,*,UP,NTRANS +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 9000,2100,9000,3900,300,*,UP,ALU1 +S 700,4000,4800,4000,200,*,RIGHT,POLY +S 9000,4000,10800,4000,400,*,RIGHT,POLY +S 4800,600,4800,2500,200,*,UP,NTRANS +S 6500,800,6500,2300,400,*,UP,NDIF +S 6000,600,6000,2500,200,*,UP,NTRANS +S 9000,800,9000,1900,600,*,UP,NDIF +S 9600,600,9600,2500,200,*,UP,NTRANS +S 9600,5500,9600,9500,200,*,UP,PTRANS +S 10800,5500,10800,9500,200,*,UP,PTRANS +S 5100,4000,5900,4000,300,*,RIGHT,ALU1 +S 6000,4000,8000,4000,200,*,RIGHT,POLY +S 3100,7000,4100,7000,300,*,RIGHT,ALU1 +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 4100,3000,6900,3000,300,*,RIGHT,ALU1 +S 6000,2800,6000,4000,200,*,UP,POLY +S 10800,600,10800,2500,200,*,UP,NTRANS +S 11300,800,11300,2300,400,*,UP,NDIF +S 10200,800,10200,2300,600,*,UP,NDIF +S 9600,2800,9600,5200,200,*,UP,POLY +S 10800,2800,10800,5200,200,*,UP,POLY +S 9000,7100,9000,8900,300,*,UP,ALU1 +S 7000,3100,7000,7900,300,*,UP,ALU1 +S 8000,3100,8000,5700,300,*,UP,ALU1 +S 7800,5700,7800,7300,600,*,UP,PDIF +S 9000,6900,9000,9300,600,*,UP,PDIF +S 10200,5700,10200,9300,600,*,UP,PDIF +S 7200,5500,7200,7500,200,*,UP,PTRANS +S 1200,5500,1200,7500,200,*,UP,PTRANS +S 3100,2000,8900,2000,300,*,RIGHT,ALU1 +S 4100,5000,4900,5000,300,*,RIGHT,ALU1 +S 5000,4100,5000,4900,300,*,UP,ALU1 +S 5400,800,5400,2300,600,*,UP,NDIF +S 4200,800,4200,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 3000,800,3000,2300,600,*,UP,NDIF +S 1900,800,1900,2300,400,*,UP,NDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S 700,1700,700,2300,400,*,UP,NDIF +S 10000,2100,10000,7900,300,nq,UP,CALU1 +S 7000,3100,7000,7900,300,i1,UP,CALU1 +S 2000,2100,2000,7900,300,i0,UP,CALU1 +S 1200,5200,2400,5200,200,*,RIGHT,POLY +S 2400,5200,2400,5500,200,*,UP,POLY +S 1200,5200,1200,5500,200,*,UP,POLY +S 2400,2500,2400,2800,200,*,UP,POLY +S 1200,2800,2400,2800,200,*,RIGHT,POLY +S 1200,2500,1200,2800,200,*,UP,POLY +V 10000,2000,CONT_DIF_N,* +V 4200,3000,CONT_POLY,* +V 4200,5000,CONT_POLY,* +V 4200,7000,CONT_DIF_P,* +V 4200,2000,CONT_DIF_N,* +V 5400,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 11200,9200,CONT_DIF_P,* +V 11200,8000,CONT_DIF_P,* +V 11200,7000,CONT_DIF_P,* +V 11200,6000,CONT_DIF_P,* +V 11200,2000,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 800,4000,CONT_POLY,* +V 800,6000,CONT_DIF_P,* +V 2000,9200,CONT_DIF_P,* +V 6400,9200,CONT_DIF_P,* +V 9000,9200,CONT_DIF_P,* +V 7000,3000,CONT_POLY,* +V 800,9200,CONT_BODY_N,* +V 10000,6000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 7800,9100,CONT_BODY_N,* +V 11200,900,CONT_DIF_N,* +V 9000,900,CONT_DIF_N,* +V 6400,900,CONT_DIF_N,* +V 2000,900,CONT_DIF_N,* +V 9000,4000,CONT_POLY,* +V 8000,5800,CONT_DIF_P,* +V 8000,3000,CONT_DIF_N,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 7000,5000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/nxr2_x4.vbe b/pdks/symbolic/nsxlib/cells/nxr2_x4.vbe new file mode 100644 index 000000000..aa5ea7108 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/nxr2_x4.vbe @@ -0,0 +1,36 @@ +ENTITY nxr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tpll_i1_nq : NATURAL := 453; + CONSTANT tphh_i0_nq : NATURAL := 469; + CONSTANT tpll_i0_nq : NATURAL := 481; + CONSTANT tphl_i0_nq : NATURAL := 522; + CONSTANT tplh_i1_nq : NATURAL := 542; + CONSTANT tphl_i1_nq : NATURAL := 553; + CONSTANT tplh_i0_nq : NATURAL := 553; + CONSTANT tphh_i1_nq : NATURAL := 568; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x4; + +ARCHITECTURE behaviour_data_flow OF nxr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x4" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/o2_x2.ap b/pdks/symbolic/nsxlib/cells/o2_x2.ap new file mode 100644 index 000000000..6827fdb92 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o2_x2.ap @@ -0,0 +1,64 @@ +V ALLIANCE : 6 +H o2_x2,P,25/ 9/2019,100 +A 0,0,5000,10000 +R 1000,5000,ref_ref,i1_25 +R 3000,2000,ref_ref,i0_10 +R 1000,3000,ref_ref,i1_15 +R 1000,4000,ref_ref,i1_20 +R 1000,6000,ref_ref,i1_30 +R 1000,7000,ref_ref,i1_35 +R 4000,5000,ref_ref,q_25 +R 4000,4000,ref_ref,q_20 +R 4000,3000,ref_ref,q_15 +R 3000,4000,ref_ref,i0_20 +R 3000,8000,ref_ref,i0_40 +R 3000,7000,ref_ref,i0_35 +R 3000,6000,ref_ref,i0_30 +S 3600,2800,3600,5200,200,*,UP,POLY +S -300,7800,5300,7800,6000,*,RIGHT,NWELL +S 4000,2100,4000,8000,300,*,UP,ALU1 +S 4200,800,4200,2300,400,*,UP,NDIF +S 2300,5100,2900,5100,200,*,RIGHT,POLY +S 2300,5100,2300,5300,200,*,UP,POLY +S 2400,2700,2400,2900,200,*,UP,POLY +S 1300,3800,1300,4200,200,*,UP,POLY +S 1000,1200,1000,1900,300,*,UP,ALU1 +S 700,1700,700,2300,400,*,UP,NDIF +S 1400,5500,1400,8500,200,*,UP,PTRANS +S 3000,5700,3000,9300,400,*,UP,PDIF +S 2300,5500,2300,8500,200,*,UP,PTRANS +S 2400,2900,2700,2900,200,*,RIGHT,POLY +S 1800,1700,1800,2300,600,*,UP,NDIF +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 700,5700,700,8300,400,*,UP,PDIF +S 1000,5700,1000,8300,600,*,UP,PDIF +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 2000,4000,3600,4000,200,*,RIGHT,POLY +S 1400,2800,1400,5200,200,*,UP,POLY +S 1400,1500,1400,2500,200,*,UP,NTRANS +S 4200,5700,4200,9300,400,*,UP,PDIF +S 1000,8000,1800,8000,300,*,RIGHT,ALU1 +S 1900,2100,1900,7900,300,*,UP,ALU1 +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 2400,1500,2400,2500,200,*,UP,NTRANS +S 3600,600,3600,2500,200,*,UP,NTRANS +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 4000,2000,4000,8000,300,q,UP,CALU1 +S 1000,3000,1000,7000,300,i1,UP,CALU1 +S 3000,2200,3000,8000,300,i0,UP,CALU1 +S 3000,800,3000,2300,400,*,UP,NDIF +V 3200,900,CONT_DIF_N,* +V 4000,8000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +V 1000,1900,CONT_DIF_N,* +V 3000,5000,CONT_POLY,* +V 1900,2000,CONT_DIF_N,* +V 3000,3000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 4000,2000,CONT_DIF_N,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 3200,9100,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/o2_x2.vbe b/pdks/symbolic/nsxlib/cells/o2_x2.vbe new file mode 100644 index 000000000..9e115a06f --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tpll_i0_q : NATURAL := 310; + CONSTANT tphh_i1_q : NATURAL := 335; + CONSTANT tpll_i1_q : NATURAL := 364; + CONSTANT tphh_i0_q : NATURAL := 406; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x2; + +ARCHITECTURE behaviour_data_flow OF o2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x2" + SEVERITY WARNING; + q <= (i0 or i1) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/o2_x4.ap b/pdks/symbolic/nsxlib/cells/o2_x4.ap new file mode 100644 index 000000000..1d2d5a387 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o2_x4.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H o2_x4,P,25/ 9/2019,100 +A 0,0,6000,10000 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 3000,8000,ref_ref,i0_40 +R 3000,4000,ref_ref,i0_20 +R 4000,3000,ref_ref,q_15 +R 4000,4000,ref_ref,q_20 +R 4000,5000,ref_ref,q_25 +R 1000,7000,ref_ref,i1_35 +R 1000,6000,ref_ref,i1_30 +R 1000,4000,ref_ref,i1_20 +R 1000,3000,ref_ref,i1_15 +R 3000,2000,ref_ref,i0_10 +R 1000,5000,ref_ref,i1_25 +S 1000,2800,1000,5100,200,*,UP,POLY +S 1000,5100,1500,5100,200,*,RIGHT,POLY +S 1000,2800,1400,2800,200,*,LEFT,POLY +S 2400,5100,3000,5100,400,*,RIGHT,POLY +S 3000,2000,3000,8000,300,i0,UP,CALU1 +S 1000,3000,1000,7000,300,i1,UP,CALU1 +S 4000,3000,4000,5000,300,q,UP,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 1500,5100,1500,5400,200,*,UP,POLY +S 1100,8000,1800,8000,300,*,RIGHT,ALU1 +S -300,7800,6300,7800,6000,*,RIGHT,NWELL +S 3100,5700,3100,9300,400,*,UP,PDIF +S 1500,5500,1500,8500,200,*,UP,PTRANS +S 1400,1500,1400,2500,200,*,UP,NTRANS +S 5200,1100,5200,1900,300,*,UP,ALU1 +S 5300,5700,5300,9300,400,*,UP,PDIF +S 5200,6100,5200,8900,300,*,UP,ALU1 +S 4000,2000,4000,8000,300,*,UP,ALU1 +S 2000,4000,4800,4000,200,*,RIGHT,POLY +S 4800,2800,4800,5200,200,*,UP,POLY +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 3600,2800,3600,5200,200,*,UP,POLY +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 2400,2700,2400,2900,200,*,UP,POLY +S 2400,5100,2400,5300,200,*,UP,POLY +S 2400,3000,3000,3000,400,*,RIGHT,POLY +S 1000,1100,1000,2000,300,*,UP,ALU1 +S 700,1700,700,2300,400,*,UP,NDIF +S 3100,800,3100,2300,400,*,UP,NDIF +S 4200,800,4200,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 4800,600,4800,2500,200,*,UP,NTRANS +S 1000,5700,1000,8300,600,*,UP,PDIF +S 4200,5700,4200,9300,600,*,UP,PDIF +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 2400,5500,2400,8500,200,*,UP,PTRANS +S 1800,1700,1800,2300,600,*,UP,NDIF +S 2400,1500,2400,2500,200,*,UP,NTRANS +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 1900,2100,1900,7900,300,*,UP,ALU1 +S 5300,800,5300,2300,400,*,UP,NDIF +V 1000,8000,CONT_DIF_P,* +V 2000,2000,CONT_DIF_N,* +V 4000,2000,CONT_DIF_N,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 3000,3000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 1000,2000,CONT_DIF_N,* +V 3200,900,CONT_DIF_N,* +V 5200,900,CONT_DIF_N,* +V 2000,4000,CONT_POLY,* +V 5200,9200,CONT_DIF_P,* +V 5200,8000,CONT_DIF_P,* +V 3200,9200,CONT_DIF_P,* +V 5200,2000,CONT_DIF_N,* +V 5200,6000,CONT_DIF_P,* +V 5200,7000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/o2_x4.vbe b/pdks/symbolic/nsxlib/cells/o2_x4.vbe new file mode 100644 index 000000000..e22a93618 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 394; + CONSTANT tphh_i1_q : NATURAL := 427; + CONSTANT tpll_i1_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 491; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x4; + +ARCHITECTURE behaviour_data_flow OF o2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x4" + SEVERITY WARNING; + q <= (i0 or i1) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/o3_x2.ap b/pdks/symbolic/nsxlib/cells/o3_x2.ap new file mode 100644 index 000000000..891543f47 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o3_x2.ap @@ -0,0 +1,79 @@ +V ALLIANCE : 6 +H o3_x2,P,15/8/2019,100 +A 0,0,6000,10000 +S 2600,2000,2600,3000,300,*,UP,ALU1 +S 1000,4100,1000,6900,300,*,UP,ALU1 +S 2100,2800,2100,5200,200,*,UP,POLY +S 2100,5500,2100,8500,200,*,UP,PTRANS +S 3000,5500,3000,8500,200,*,UP,PTRANS +S 700,1700,700,2300,400,*,UP,NDIF +S 2100,1500,2100,2500,200,*,UP,NTRANS +S 1800,1700,1800,2300,400,*,UP,NDIF +S 3200,1500,3200,2500,200,*,UP,NTRANS +S 4000,3100,4000,7900,300,*,UP,ALU1 +S 3800,1200,3800,2000,300,*,UP,ALU1 +S 1700,1200,1700,2000,300,*,UP,ALU1 +S 1200,5500,1200,8500,200,*,UP,PTRANS +S 5000,2000,5000,8000,300,*,UP,ALU1 +S 4600,2800,4600,5200,200,*,UP,POLY +S 4600,5500,4600,9500,200,*,UP,PTRANS +S 5300,5700,5300,9300,400,*,UP,PDIF +S 800,2000,800,2900,300,*,UP,ALU1 +S 900,3000,3900,3000,300,*,RIGHT,ALU1 +S 3000,4100,3000,6900,300,*,UP,ALU1 +S 2000,4100,2000,6900,300,*,UP,ALU1 +S 700,8000,3900,8000,300,*,RIGHT,ALU1 +S 1200,2800,1200,5200,200,*,UP,POLY +S 1200,1500,1200,2500,200,*,UP,NTRANS +S -300,7800,6300,7800,6000,*,RIGHT,NWELL +S 4600,600,4600,2500,200,*,UP,NTRANS +S 5300,800,5300,2300,400,*,UP,NDIF +S 700,5700,700,8300,400,*,UP,PDIF +S 3700,5700,3700,9300,400,*,UP,PDIF +S 4100,5700,4100,9300,400,*,UP,PDIF +S 3800,1700,3800,2300,300,*,UP,NDIF +S 4100,800,4100,2300,400,*,UP,NDIF +S 2700,1700,2700,2300,200,*,UP,NDIF +S 4000,4000,4500,4000,400,*,RIGHT,POLY +S 3200,2800,3200,4900,200,*,UP,POLY +S 3000,5100,3000,5300,200,*,UP,POLY +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 5000,2000,5000,8000,300,q,UP,CALU1 +S 1000,4000,1000,7000,300,i2,UP,CALU1 +S 2000,4000,2000,7000,300,i1,UP,CALU1 +S 3000,4000,3000,7000,300,i0,UP,CALU1 +V 5000,8000,CONT_DIF_P,* +V 3000,5000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 800,8000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 4200,9200,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 3800,2000,CONT_DIF_N,* +V 1700,2000,CONT_DIF_N,* +V 2600,2000,CONT_DIF_N,* +R 5000,4000,ref_ref,q_20 +R 5000,3000,ref_ref,q_15 +R 5000,2000,ref_ref,q_10 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 1000,5000,ref_ref,i2_25 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 5000,8000,ref_ref,q_40 +R 5000,7000,ref_ref,q_35 +R 5000,6000,ref_ref,q_30 +R 5000,5000,ref_ref,q_25 +R 1000,6000,ref_ref,i2_30 +R 1000,7000,ref_ref,i2_35 +R 1000,4000,ref_ref,i2_20 +EOF diff --git a/pdks/symbolic/nsxlib/cells/o3_x2.vbe b/pdks/symbolic/nsxlib/cells/o3_x2.vbe new file mode 100644 index 000000000..5aad7aba9 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 360; + CONSTANT tpll_i0_q : NATURAL := 407; + CONSTANT tphh_i1_q : NATURAL := 430; + CONSTANT tpll_i1_q : NATURAL := 482; + CONSTANT tphh_i0_q : NATURAL := 494; + CONSTANT tpll_i2_q : NATURAL := 506; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x2; + +ARCHITECTURE behaviour_data_flow OF o3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x2" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/o3_x4.ap b/pdks/symbolic/nsxlib/cells/o3_x4.ap new file mode 100644 index 000000000..07296660c --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o3_x4.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H o3_x4,P,18/ 9/2019,100 +A 0,0,7000,10000 +R 3000,7000,ref_ref,i0_35 +R 5000,5000,ref_ref,q_25 +R 5000,4000,ref_ref,q_20 +R 5000,3000,ref_ref,q_15 +R 1000,5000,ref_ref,i2_25 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 3000,3000,ref_ref,i0_15 +R 3000,6000,ref_ref,i0_30 +R 3000,5000,ref_ref,i0_25 +R 3000,4000,ref_ref,i0_20 +R 1000,6000,ref_ref,i2_30 +R 1000,7000,ref_ref,i2_35 +R 1000,3000,ref_ref,i2_15 +R 1000,4000,ref_ref,i2_20 +S 1000,3100,1000,6900,300,i2,UP,CALU1 +S 2000,3100,2000,6900,300,i1,UP,CALU1 +S 3000,3100,3000,6900,300,i0,UP,CALU1 +S 5000,2100,5000,7900,300,q,UP,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 5200,800,5200,2300,600,*,UP,NDIF +S 4600,600,4600,2500,200,*,UP,NTRANS +S 6300,800,6300,2300,400,*,UP,NDIF +S 5800,600,5800,2500,200,*,UP,NTRANS +S 5800,2800,5800,5200,200,*,UP,POLY +S 5800,5500,5800,9500,200,*,UP,PTRANS +S 5200,5700,5200,9300,600,*,UP,PDIF +S 4600,5500,4600,9500,200,*,UP,PTRANS +S 4600,2800,4600,5200,200,*,UP,POLY +S 1200,5500,1200,8500,200,*,UP,PTRANS +S 700,8000,3900,8000,300,*,RIGHT,ALU1 +S 4000,2100,4000,7900,300,*,UP,ALU1 +S 1200,2800,1200,5200,200,*,UP,POLY +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 3000,3100,3000,6900,300,*,UP,ALU1 +S 3000,1700,3000,2300,600,*,UP,NDIF +S -300,7800,7300,7800,6000,*,RIGHT,NWELL +S 5000,2100,5000,7900,300,*,UP,ALU1 +S 2600,2600,2600,2900,200,*,UP,POLY +S 3500,2600,3500,2900,200,*,UP,POLY +S 2200,3000,2200,5200,200,*,UP,POLY +S 3200,3000,3200,5000,200,*,UP,POLY +S 3200,2900,3500,2900,200,*,RIGHT,POLY +S 2200,2900,2600,2900,200,*,RIGHT,POLY +S 1200,600,1200,2500,200,*,UP,NTRANS +S 2600,600,2600,2500,200,*,UP,NTRANS +S 3500,600,3500,2500,200,*,UP,NTRANS +S 3100,5000,3100,5300,200,*,UP,POLY +S 4100,4000,5800,4000,400,*,RIGHT,POLY +S 1900,800,1900,2300,400,*,UP,NDIF +S 6200,6100,6200,8900,300,*,UP,ALU1 +S 6200,1100,6200,1900,300,*,UP,ALU1 +S 6300,5700,6300,9300,400,*,UP,PDIF +S 4200,5700,4200,9300,400,*,UP,PDIF +S 3800,5700,3800,9300,400,*,UP,PDIF +S 3100,5500,3100,8500,200,*,UP,PTRANS +S 2200,5500,2200,8500,200,*,UP,PTRANS +S 700,1700,700,2300,400,*,UP,NDIF +S 900,2000,3900,2000,300,*,RIGHT,ALU1 +S 700,5700,700,8300,400,*,UP,PDIF +S 4200,800,4200,2300,400,*,UP,NDIF +V 1900,900,CONT_DIF_N,* +V 4200,900,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,* +V 4000,9200,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 5000,8000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 6200,2000,CONT_DIF_N,* +V 6200,6000,CONT_DIF_P,* +V 6200,7000,CONT_DIF_P,* +V 6200,8000,CONT_DIF_P,* +V 6200,9200,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 1000,3000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 6200,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/o3_x4.vbe b/pdks/symbolic/nsxlib/cells/o3_x4.vbe new file mode 100644 index 000000000..1e7ea94f8 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 447; + CONSTANT tpll_i0_q : NATURAL := 501; + CONSTANT tphh_i1_q : NATURAL := 510; + CONSTANT tphh_i0_q : NATURAL := 569; + CONSTANT tpll_i1_q : NATURAL := 585; + CONSTANT tpll_i2_q : NATURAL := 622; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x4; + +ARCHITECTURE behaviour_data_flow OF o3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x4" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/o4_x2.ap b/pdks/symbolic/nsxlib/cells/o4_x2.ap new file mode 100644 index 000000000..c685ed55e --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o4_x2.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 6 +H o4_x2,P,18/ 9/2019,100 +A 0,0,7000,10000 +R 6000,4000,ref_ref,q_20 +R 6000,5000,ref_ref,q_25 +R 6000,7000,ref_ref,q_35 +R 1000,4000,ref_ref,i3_20 +R 1000,5000,ref_ref,i3_25 +R 6000,2000,ref_ref,q_10 +R 6000,3000,ref_ref,q_15 +R 6000,8000,ref_ref,q_40 +R 6000,6000,ref_ref,q_30 +R 4000,7000,ref_ref,i2_35 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 4000,4000,ref_ref,i2_20 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +R 1000,6000,ref_ref,i3_30 +R 1000,7000,ref_ref,i3_35 +R 1000,3000,ref_ref,i3_15 +S 1000,3100,1000,6900,300,i3,UP,CALU1 +S 2000,4100,2000,6900,300,i1,UP,CALU1 +S 2000,4100,2000,6900,300,*,UP,ALU1 +S 3000,4100,3000,6900,300,i0,UP,CALU1 +S 3000,4100,3000,6900,300,*,UP,ALU1 +S 4000,4100,4000,6900,300,i2,UP,CALU1 +S 6000,2100,6000,7900,300,q,UP,CALU1 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 6000,2100,6000,7900,300,*,UP,ALU1 +S 5300,5700,5300,9300,200,*,UP,PDIF +S 5600,5500,5600,9500,200,*,UP,PTRANS +S 5600,2800,5600,5200,200,*,UP,POLY +S 6300,5700,6300,9300,400,*,UP,PDIF +S 4500,1500,4500,2500,200,*,UP,NTRANS +S 4200,1700,4200,2300,400,*,UP,NDIF +S 1800,1700,1800,2300,400,*,UP,NDIF +S 3600,1500,3600,2500,200,*,UP,NTRANS +S 5000,5700,5000,9300,600,*,UP,PDIF +S -300,7800,7300,7800,6000,*,RIGHT,NWELL +S 4000,4100,4000,6900,300,*,UP,ALU1 +S 1200,5100,1300,5100,200,*,RIGHT,POLY +S 1200,3000,1200,5100,200,*,UP,POLY +S 2000,3000,2000,5000,200,*,UP,POLY +S 3200,3000,3200,4100,200,*,UP,POLY +S 4200,3000,4200,5000,200,*,UP,POLY +S 2400,1500,2400,2500,200,*,UP,NTRANS +S 3000,1300,3000,2000,300,*,UP,ALU1 +S 2900,1700,2900,2300,400,*,UP,NDIF +S 4100,2000,4100,3000,300,*,UP,ALU1 +S 5100,3100,5100,7900,300,*,UP,ALU1 +S 2000,5100,2200,5100,200,*,RIGHT,POLY +S 4000,5100,4200,5100,200,*,RIGHT,POLY +S 4200,2900,4500,2900,200,*,RIGHT,POLY +S 3200,2900,3600,2900,200,*,RIGHT,POLY +S 2000,2900,2400,2900,200,*,RIGHT,POLY +S 1200,2900,1300,2900,200,*,RIGHT,POLY +S 5000,1200,5000,2000,300,*,UP,ALU1 +S 2000,3000,5000,3000,300,*,RIGHT,ALU1 +S 2000,2000,2000,2900,300,*,UP,ALU1 +S 1300,1500,1300,2500,200,*,UP,NTRANS +S 1300,5100,1300,5400,200,*,UP,POLY +S 6300,800,6300,2300,400,*,UP,NDIF +S 900,1200,900,1900,300,*,UP,ALU1 +S 700,1700,700,2300,400,*,UP,NDIF +S 900,8000,5000,8000,300,*,RIGHT,ALU1 +S 700,5700,700,8300,400,*,UP,PDIF +S 1300,5500,1300,8500,200,*,UP,PTRANS +S 2200,5500,2200,8500,200,*,UP,PTRANS +S 3100,5500,3100,8500,200,*,UP,PTRANS +S 4000,5500,4000,8500,200,*,UP,PTRANS +S 4700,5700,4700,9300,400,*,UP,PDIF +S 2200,5100,2200,5400,200,*,UP,POLY +S 4000,5100,4000,5400,200,*,UP,POLY +S 4500,2600,4500,2900,200,*,UP,POLY +S 3600,2600,3600,2900,200,*,UP,POLY +S 2400,2600,2400,2900,200,*,UP,POLY +S 1300,2600,1300,2900,200,*,UP,POLY +S 4800,4000,5600,4000,400,*,RIGHT,POLY +S 3100,3900,3100,5200,200,*,UP,POLY +S 5100,1700,5100,2300,200,*,UP,NDIF +S 5600,600,5600,2500,200,*,UP,NTRANS +V 6000,2000,CONT_DIF_N,* +V 6000,6000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 4100,2000,CONT_DIF_N,* +V 5200,9200,CONT_DIF_P,* +V 900,8000,CONT_DIF_P,* +V 900,1900,CONT_DIF_N,* +V 3000,4000,CONT_POLY,* +V 5000,2000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/o4_x2.vbe b/pdks/symbolic/nsxlib/cells/o4_x2.vbe new file mode 100644 index 000000000..09652e62b --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i3_q : NATURAL := 378; + CONSTANT tphh_i1_q : NATURAL := 446; + CONSTANT tphh_i0_q : NATURAL := 508; + CONSTANT tpll_i2_q : NATURAL := 531; + CONSTANT tphh_i2_q : NATURAL := 567; + CONSTANT tpll_i0_q : NATURAL := 601; + CONSTANT tpll_i3_q : NATURAL := 626; + CONSTANT tpll_i1_q : NATURAL := 631; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x2; + +ARCHITECTURE behaviour_data_flow OF o4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x2" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/o4_x4.ap b/pdks/symbolic/nsxlib/cells/o4_x4.ap new file mode 100644 index 000000000..16db4b630 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o4_x4.ap @@ -0,0 +1,126 @@ +V ALLIANCE : 6 +H o4_x4,P,25/ 9/2019,100 +A 0,0,8000,10000 +R 7000,3000,ref_ref,q_15 +R 7000,4000,ref_ref,q_20 +R 7000,5000,ref_ref,q_25 +R 4000,8000,ref_ref,i2_40 +R 4000,7000,ref_ref,i2_35 +R 5000,4000,ref_ref,i3_20 +R 2000,8000,ref_ref,i1_40 +R 5000,8000,ref_ref,i3_40 +R 5000,7000,ref_ref,i3_35 +R 5000,6000,ref_ref,i3_30 +R 5000,5000,ref_ref,i3_25 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 7000,2000,ref_ref,q_10 +R 3000,3000,ref_ref,i0_15 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 4000,6000,ref_ref,i2_30 +R 4000,5000,ref_ref,i2_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 3000,8000,ref_ref,i0_40 +S 6200,3100,6200,4900,300,*,UP,ALU1 +S 7000,2100,7000,6000,300,*,UP,ALU1 +S 6300,6000,6900,6000,300,*,RIGHT,ALU1 +S 1100,2000,1700,2000,300,*,RIGHT,ALU1 +S 6800,600,6800,2500,200,*,UP,NTRANS +S 7300,800,7300,2300,400,*,UP,NDIF +S 5300,800,5300,2300,400,*,UP,NDIF +S 7300,5700,7300,9300,400,*,UP,PDIF +S 4700,5500,4700,9500,200,*,UP,PTRANS +S 3800,5500,3800,9500,200,*,UP,PTRANS +S 2900,5500,2900,9500,200,*,UP,PTRANS +S 5000,5700,5000,9300,400,*,UP,PDIF +S 2300,2800,2300,3800,200,*,UP,POLY +S 1400,2800,1400,4800,200,*,UP,POLY +S 4200,1700,4200,2300,400,*,UP,NDIF +S 1800,1700,1800,2300,400,*,UP,NDIF +S 2000,5000,2000,5400,200,*,UP,POLY +S 5600,600,5600,2500,200,*,UP,NTRANS +S 5600,2600,5600,2900,200,*,UP,POLY +S 6300,800,6300,2300,400,*,UP,NDIF +S 5600,2900,5800,2900,200,*,RIGHT,POLY +S 5600,5500,5600,9500,200,*,UP,PTRANS +S 4000,3100,4000,7900,300,*,UP,ALU1 +S 3000,3100,3000,7900,300,*,UP,ALU1 +S 1000,5700,1000,8300,600,*,UP,PDIF +S 2000,3100,2000,7900,300,*,UP,ALU1 +S 7200,7100,7200,8900,300,*,UP,ALU1 +S 1400,5700,1400,9300,600,*,UP,PDIF +S 4100,2000,4900,2000,300,*,RIGHT,ALU1 +S -300,7800,8300,7800,6000,*,RIGHT,NWELL +S 1000,2100,1000,5900,300,*,UP,ALU1 +S 2000,5500,2000,9500,200,*,UP,PTRANS +S 6800,5500,6800,9500,200,*,UP,PTRANS +S 6200,5700,6200,9300,600,*,UP,PDIF +S 5100,3000,5900,3000,300,*,RIGHT,ALU1 +S 5000,2100,5000,2900,300,*,UP,ALU1 +S 1100,2000,4900,2000,300,*,RIGHT,ALU1 +S 5000,4100,5000,7900,300,*,UP,ALU1 +S 6300,2000,6900,2000,300,*,RIGHT,ALU1 +S 1000,6100,1000,7900,300,*,UP,ALU1 +S 6000,6100,6000,7900,300,*,UP,ALU1 +S 4600,600,4600,2500,200,*,UP,NTRANS +S 3700,600,3700,2500,200,*,UP,NTRANS +S 2300,600,2300,2500,200,*,UP,NTRANS +S 1400,600,1400,2500,200,*,UP,NTRANS +S 700,800,700,2300,400,*,UP,NDIF +S 3000,800,3000,2300,400,*,UP,NDIF +S 2400,3800,3000,3800,200,*,RIGHT,POLY +S 1400,4800,2000,4800,200,*,RIGHT,POLY +S 2800,5100,2900,5100,200,*,RIGHT,POLY +S 4700,5100,4800,5100,200,*,RIGHT,POLY +S 5600,5100,6800,5100,200,*,RIGHT,POLY +S 3700,2900,3800,2900,200,*,RIGHT,POLY +S 4600,2900,4800,2900,200,*,RIGHT,POLY +S 5900,2900,6800,2900,200,*,RIGHT,POLY +S 2800,4000,2800,5000,200,*,UP,POLY +S 3800,3000,3800,5200,200,*,UP,POLY +S 4800,3000,4800,5000,200,*,UP,POLY +S 3700,2600,3700,2900,200,*,UP,POLY +S 4600,2600,4600,2900,200,*,UP,POLY +S 2900,5100,2900,5400,200,*,UP,POLY +S 4700,5100,4700,5400,200,*,UP,POLY +S 5600,5100,5600,5400,200,*,UP,POLY +S 6800,5100,6800,5400,200,*,UP,POLY +S 6800,2600,6800,2900,200,*,UP,POLY +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 7000,2100,7000,6000,300,q,UP,CALU1 +S 5000,4100,5000,7900,300,i3,UP,CALU1 +S 4000,3100,4000,7900,300,i2,UP,CALU1 +S 3000,3100,3000,7900,300,i0,UP,CALU1 +S 2000,3100,2000,7900,300,i1,UP,CALU1 +V 6200,3000,CONT_POLY,* +V 6200,5000,CONT_POLY,* +V 6000,6000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 5200,900,CONT_DIF_N,* +V 6000,2000,CONT_DIF_N,* +V 3000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 1000,6000,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 7200,9200,CONT_DIF_P,* +V 7200,8000,CONT_DIF_P,* +V 7200,7000,CONT_DIF_P,* +V 4200,2000,CONT_DIF_N,* +V 800,900,CONT_DIF_N,* +V 3000,900,CONT_DIF_N,* +V 5100,9200,CONT_DIF_P,* +V 7200,900,CONT_DIF_N,* +V 1000,8000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1800,2000,CONT_DIF_N,* +V 2000,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/o4_x4.vbe b/pdks/symbolic/nsxlib/cells/o4_x4.vbe new file mode 100644 index 000000000..bc869a8fb --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/o4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 492; + CONSTANT tpll_i3_q : NATURAL := 536; + CONSTANT tphh_i0_q : NATURAL := 574; + CONSTANT tpll_i2_q : NATURAL := 611; + CONSTANT tpll_i0_q : NATURAL := 638; + CONSTANT tphh_i2_q : NATURAL := 649; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 721; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x4; + +ARCHITECTURE behaviour_data_flow OF o4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x4" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa22_x2.ap b/pdks/symbolic/nsxlib/cells/oa22_x2.ap new file mode 100644 index 000000000..38c1b6855 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa22_x2.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H oa22_x2,P,25/ 9/2019,100 +A 0,0,6000,10000 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 4000,5000,ref_ref,i2_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 4000,2000,ref_ref,i2_10 +R 5000,2000,ref_ref,q_10 +R 5000,3000,ref_ref,q_15 +R 5000,4000,ref_ref,q_20 +R 5000,5000,ref_ref,q_25 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 1000,2000,ref_ref,i0_10 +R 5000,6000,ref_ref,q_30 +R 5000,7000,ref_ref,q_35 +R 5000,8000,ref_ref,q_40 +R 4000,6000,ref_ref,i2_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 2000,2000,ref_ref,i1_10 +S 2000,2800,2500,2800,200,*,LEFT,POLY +S 2000,6200,2400,6200,200,*,LEFT,POLY +S 1000,6200,1400,6200,200,*,LEFT,POLY +S 1000,2800,1400,2800,200,*,LEFT,POLY +S 1000,2800,1000,6200,200,*,UP,POLY +S 3000,6700,3000,8300,400,*,UP,PDIF +S 1800,6700,1800,8300,400,*,UP,PDIF +S 3000,1700,3000,2300,400,*,UP,NDIF +S 3000,4000,4600,4000,200,*,RIGHT,POLY +S 4100,5700,4100,9300,400,*,UP,PDIF +S 4600,2800,4600,5200,200,*,UP,POLY +S 4600,5500,4600,9500,200,*,UP,PTRANS +S 2000,2100,2000,5900,300,*,UP,ALU1 +S 4000,2100,4000,7900,300,*,UP,ALU1 +S 1000,2100,1000,5900,300,*,UP,ALU1 +S 700,8000,2900,8000,300,*,RIGHT,ALU1 +S 1900,7000,2900,7000,300,*,RIGHT,ALU1 +S 2400,6500,2400,8500,200,*,UP,PTRANS +S -300,7800,6300,7800,6000,*,RIGHT,NWELL +S 5200,5700,5200,9300,600,*,UP,PDIF +S 3400,6500,3400,8500,200,*,UP,PTRANS +S 1400,6500,1400,8500,200,*,UP,PTRANS +S 1000,7100,1000,7900,300,*,UP,ALU1 +S 900,6700,900,8300,600,*,UP,PDIF +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 5200,800,5200,2300,600,*,UP,NDIF +S 4600,600,4600,2500,200,*,UP,NTRANS +S 4200,800,4200,2300,600,*,UP,NDIF +S 3600,5000,4000,5000,400,*,RIGHT,POLY +S 3400,3000,3800,3000,400,*,RIGHT,POLY +S 3400,5000,3400,6200,200,*,UP,POLY +S 3400,2700,3400,2900,200,*,UP,POLY +S 3400,600,3400,2500,200,*,UP,NTRANS +S 2500,600,2500,2500,200,*,UP,NTRANS +S 1400,600,1400,2500,200,*,UP,NTRANS +S 1800,800,1800,2300,400,*,UP,NDIF +S 700,800,700,2300,400,*,UP,NDIF +S 0,600,6000,600,1200,vss,RIGHT,CALU1 +S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 +S 5000,2100,5000,7900,300,q,UP,CALU1 +S 5000,2100,5000,7900,300,*,UP,ALU1 +S 4000,2100,4000,7900,300,i2,UP,CALU1 +S 2000,2100,2000,5900,300,i1,UP,CALU1 +S 1000,2100,1000,5900,300,i0,UP,CALU1 +V 1000,4000,CONT_POLY,* +V 900,900,CONT_DIF_N,* +V 4200,900,CONT_DIF_N,* +V 3000,4000,CONT_POLY,* +V 2000,6000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 4000,5000,CONT_POLY,* +V 4000,3000,CONT_POLY,* +V 3000,8000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 5000,8000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 1000,8000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 4200,9200,CONT_DIF_P,* +V 1900,7000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa22_x2.vbe b/pdks/symbolic/nsxlib/cells/oa22_x2.vbe new file mode 100644 index 000000000..d2d267604 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 390; + CONSTANT tphh_i2_q : NATURAL := 438; + CONSTANT tpll_i2_q : NATURAL := 454; + CONSTANT tphh_i1_q : NATURAL := 488; + CONSTANT tpll_i1_q : NATURAL := 525; + CONSTANT tpll_i0_q : NATURAL := 555; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x2; + +ARCHITECTURE behaviour_data_flow OF oa22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa22_x4.ap b/pdks/symbolic/nsxlib/cells/oa22_x4.ap new file mode 100644 index 000000000..8d120b579 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa22_x4.ap @@ -0,0 +1,104 @@ +V ALLIANCE : 6 +H oa22_x4,P,25/ 9/2019,100 +A 0,0,8000,10000 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 4000,2000,ref_ref,i2_10 +R 6000,8000,ref_ref,q_40 +R 6000,7000,ref_ref,q_35 +R 6000,6000,ref_ref,q_30 +R 6000,5000,ref_ref,q_25 +R 6000,4000,ref_ref,q_20 +R 6000,3000,ref_ref,q_15 +R 6000,2000,ref_ref,q_10 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 4000,3000,ref_ref,i2_15 +R 4000,4000,ref_ref,i2_20 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 2000,2000,ref_ref,i1_10 +R 1000,2000,ref_ref,i0_10 +R 1000,3000,ref_ref,i0_15 +R 1000,4000,ref_ref,i0_20 +S 3600,5300,3600,6200,200,*,UP,POLY +S 3600,5200,4000,5200,200,*,LEFT,POLY +S 3600,2800,4000,2800,200,*,RIGHT,POLY +S 1000,6200,1400,6200,200,*,LEFT,POLY +S 1000,2800,1400,2800,200,*,LEFT,POLY +S 1000,2800,1000,6200,200,*,UP,POLY +S 2000,6200,2400,6200,200,*,LEFT,POLY +S 2000,2800,2400,2800,200,*,LEFT,POLY +S 6600,600,6600,2500,200,*,UP,NTRANS +S 7100,800,7100,2300,600,*,UP,NDIF +S 1800,6700,1800,8300,400,*,UP,PDIF +S 4400,800,4400,2300,600,*,UP,NDIF +S 6000,800,6000,2300,600,*,UP,NDIF +S 5400,600,5400,2500,200,*,UP,NTRANS +S 3000,4000,6600,4000,300,*,RIGHT,POLY +S 5000,5700,5000,9300,200,*,UP,PDIF +S 4600,5700,4600,9300,600,*,UP,PDIF +S 6600,5500,6600,9500,200,*,UP,PTRANS +S 6000,5700,6000,9300,600,*,UP,PDIF +S 5400,5500,5400,9500,200,*,UP,PTRANS +S 5400,2800,5400,5200,200,*,UP,POLY +S 6600,2800,6600,5200,200,*,UP,POLY +S 1800,1700,1800,2300,600,*,UP,NDIF +S 3000,6700,3000,8300,600,*,UP,PDIF +S 2400,6500,2400,8500,200,*,UP,PTRANS +S 3600,6500,3600,8500,200,*,UP,PTRANS +S -300,7800,8300,7800,6000,*,RIGHT,NWELL +S 7100,5700,7100,9300,600,*,UP,PDIF +S 7000,1100,7000,1900,300,*,UP,ALU1 +S 4400,5700,4400,9300,600,*,UP,PDIF +S 700,8000,2900,8000,300,*,RIGHT,ALU1 +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 1000,2100,1000,5900,300,*,UP,ALU1 +S 4000,2100,4000,7900,300,*,UP,ALU1 +S 2000,2100,2000,5900,300,*,UP,ALU1 +S 7200,6100,7200,8900,300,*,UP,ALU1 +S 6000,2100,6000,7900,300,*,UP,ALU1 +S 1900,7000,2900,7000,300,*,RIGHT,ALU1 +S 3000,800,3000,2300,600,*,UP,NDIF +S 5000,800,5000,2300,200,*,UP,NDIF +S 4600,800,4600,2300,600,*,UP,NDIF +S 1400,600,1400,2500,200,*,UP,NTRANS +S 2400,600,2400,2500,200,*,UP,NTRANS +S 3600,600,3600,2500,200,*,UP,NTRANS +S 1400,6500,1400,8500,200,*,UP,PTRANS +S 700,900,700,2300,400,*,UP,NDIF +S 800,6700,800,8300,600,*,UP,PDIF +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 6000,2100,6000,7900,300,q,UP,CALU1 +S 4000,2100,4000,7900,300,i2,UP,CALU1 +S 2000,2100,2000,5900,300,i1,UP,CALU1 +S 1000,2100,1000,5900,300,i0,UP,CALU1 +V 6000,8000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 6000,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 1800,7000,CONT_DIF_P,* +V 4000,3000,CONT_POLY,* +V 4000,5000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 2000,6000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 7100,9200,CONT_DIF_P,* +V 7100,8000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,6000,CONT_DIF_P,* +V 7000,2000,CONT_DIF_N,* +V 4600,9200,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 4600,900,CONT_DIF_N,* +V 7000,900,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 900,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa22_x4.vbe b/pdks/symbolic/nsxlib/cells/oa22_x4.vbe new file mode 100644 index 000000000..fa425e333 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 511; + CONSTANT tphh_i2_q : NATURAL := 523; + CONSTANT tpll_i2_q : NATURAL := 571; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tpll_i0_q : NATURAL := 677; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x4; + +ARCHITECTURE behaviour_data_flow OF oa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa2a22_x2.ap b/pdks/symbolic/nsxlib/cells/oa2a22_x2.ap new file mode 100644 index 000000000..b39727cf5 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a22_x2.ap @@ -0,0 +1,111 @@ +V ALLIANCE : 6 +H oa2a22_x2,P,26/ 9/2019,100 +A 0,0,9000,10000 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 8000,8000,ref_ref,q_40 +R 8000,7000,ref_ref,q_35 +R 1000,5000,ref_ref,i0_25 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +R 2000,3000,ref_ref,i1_15 +R 5000,2000,ref_ref,i3_10 +R 5000,3000,ref_ref,i3_15 +R 5000,4000,ref_ref,i3_20 +R 5000,5000,ref_ref,i3_25 +R 5000,6000,ref_ref,i3_30 +R 4000,6000,ref_ref,i2_30 +R 4000,5000,ref_ref,i2_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 4000,2000,ref_ref,i2_10 +R 2000,2000,ref_ref,i1_10 +R 8000,6000,ref_ref,q_30 +R 8000,4000,ref_ref,q_20 +R 8000,2000,ref_ref,q_10 +R 8000,3000,ref_ref,q_15 +R 8000,5000,ref_ref,q_25 +S 1000,3100,1000,5900,300,i0,UP,CALU1 +S 2000,2100,2000,5900,300,i1,UP,CALU1 +S 4000,2100,4000,5900,300,i2,UP,CALU1 +S 5000,2100,5000,5900,300,i3,UP,CALU1 +S 8000,2100,8000,7900,300,q,UP,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 1100,7800,5300,7800,300,*,RIGHT,ALU1 +S 8000,2100,8000,7900,300,*,UP,ALU1 +S 6800,1100,6800,1900,300,*,UP,ALU1 +S 6800,5700,6800,9300,600,*,UP,PDIF +S 7400,5500,7400,9500,200,*,UP,PTRANS +S 8000,5700,8000,9300,600,*,UP,PDIF +S 1900,7000,6900,7000,300,*,RIGHT,ALU1 +S 7000,4100,7000,6900,300,*,UP,ALU1 +S -300,7800,9300,7800,6000,*,RIGHT,NWELL +S 2400,1500,2400,2500,200,*,UP,NTRANS +S 1800,1700,1800,2300,600,*,UP,NDIF +S 4800,1500,4800,2500,200,*,UP,NTRANS +S 4200,1700,4200,2300,600,*,UP,NDIF +S 3600,1500,3600,2500,200,*,UP,NTRANS +S 3000,1700,3000,2300,600,*,UP,NDIF +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 6800,8100,6800,8900,300,*,UP,ALU1 +S 1400,6300,1400,8300,200,*,UP,PTRANS +S 5000,2100,5000,5900,300,*,UP,ALU1 +S 3400,5800,3400,6100,200,*,UP,POLY +S 7400,600,7400,2500,200,*,UP,NTRANS +S 8000,800,8000,2300,600,*,UP,NDIF +S 4000,2100,4000,5900,300,*,UP,ALU1 +S 2000,2100,2000,5900,300,*,UP,ALU1 +S 4200,6500,4200,8900,600,*,UP,PDIF +S 1400,1500,1400,2500,200,*,UP,NTRANS +S 5600,900,5600,2300,600,*,UP,NDIF +S 700,6500,700,8100,400,*,UP,PDIF +S 2400,6300,2400,8300,200,*,UP,PTRANS +S 1800,6500,1800,8100,400,*,UP,PDIF +S 3000,6500,3000,8100,400,*,UP,PDIF +S 3400,6300,3400,8300,200,*,UP,PTRANS +S 5000,6300,5000,8300,200,*,UP,PTRANS +S 5400,6500,5400,8100,400,*,UP,PDIF +S 3600,4000,4000,4000,400,*,RIGHT,POLY +S 6800,800,6800,2300,600,*,UP,NDIF +S 4800,2600,4800,2900,200,*,UP,POLY +S 5000,3000,5000,6200,200,*,UP,POLY +S 4800,2900,5000,2900,200,*,RIGHT,POLY +S 1000,1100,1000,2000,300,*,UP,ALU1 +S 700,1700,700,2300,400,*,UP,NDIF +S 1000,3100,1000,5900,300,*,UP,ALU1 +S 1000,2800,1400,2800,200,*,LEFT,POLY +S 1000,6000,1400,6000,200,*,LEFT,POLY +S 1000,2800,1000,5900,200,*,UP,POLY +S 2000,2800,2400,2800,200,*,LEFT,POLY +S 2000,6000,2400,6000,200,*,LEFT,POLY +S 2000,2800,2000,5900,200,*,UP,POLY +S 3400,2800,3400,5700,200,*,UP,POLY +S 3400,2800,3600,2800,200,*,LEFT,POLY +S 7000,2800,7000,5200,200,*,UP,POLY +S 7000,2800,7400,2800,200,*,LEFT,POLY +S 7000,5200,7400,5200,200,*,LEFT,POLY +V 5000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 3000,2000,CONT_DIF_N,* +V 7000,4000,CONT_POLY,* +V 8000,2000,CONT_DIF_N,* +V 6800,2000,CONT_DIF_N,* +V 6800,8000,CONT_DIF_P,* +V 1000,2000,CONT_DIF_N,* +V 1900,7000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 6800,900,CONT_DIF_N,* +V 6800,9200,CONT_DIF_P,* +V 5600,900,CONT_DIF_N,* +V 4200,9100,CONT_DIF_P,* +V 5400,7800,CONT_DIF_P,* +V 3000,7800,CONT_DIF_P,* +V 1000,7800,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa2a22_x2.vbe b/pdks/symbolic/nsxlib/cells/oa2a22_x2.vbe new file mode 100644 index 000000000..1c5c40883 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 403; + CONSTANT tpll_i2_q : NATURAL := 487; + CONSTANT tphh_i1_q : NATURAL := 495; + CONSTANT tpll_i3_q : NATURAL := 512; + CONSTANT tpll_i1_q : NATURAL := 534; + CONSTANT tphh_i3_q : NATURAL := 537; + CONSTANT tpll_i0_q : NATURAL := 564; + CONSTANT tphh_i2_q : NATURAL := 646; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa2a22_x4.ap b/pdks/symbolic/nsxlib/cells/oa2a22_x4.ap new file mode 100644 index 000000000..d246888fb --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a22_x4.ap @@ -0,0 +1,125 @@ +V ALLIANCE : 6 +H oa2a22_x4,P,25/ 9/2019,100 +A 0,0,10000,10000 +R 8000,2000,ref_ref,q_10 +R 8000,4000,ref_ref,q_20 +R 2000,3000,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_10 +R 4000,2000,ref_ref,i2_10 +R 4000,3000,ref_ref,i2_15 +R 4000,4000,ref_ref,i2_20 +R 4000,5000,ref_ref,i2_25 +R 8000,3000,ref_ref,q_15 +R 8000,5000,ref_ref,q_25 +R 1000,6000,ref_ref,i0_30 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 8000,6000,ref_ref,q_30 +R 8000,7000,ref_ref,q_35 +R 8000,8000,ref_ref,q_40 +R 1000,2000,ref_ref,i0_10 +R 1000,3000,ref_ref,i0_15 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 4000,6000,ref_ref,i2_30 +R 5000,6000,ref_ref,i3_30 +R 5000,5000,ref_ref,i3_25 +R 5000,4000,ref_ref,i3_20 +R 5000,3000,ref_ref,i3_15 +R 5000,2000,ref_ref,i3_10 +S 3400,6200,4000,6200,200,*,RIGHT,POLY +S 3700,2800,4000,2800,200,*,RIGHT,POLY +S 4000,3000,4000,6000,200,*,UP,POLY +S 2000,6200,2400,6200,200,*,LEFT,POLY +S 2000,2900,2600,2900,200,*,RIGHT,POLY +S 2000,3000,2000,6200,200,*,UP,POLY +S 1000,2100,1000,5900,300,i0,UP,CALU1 +S 4000,2100,4000,5900,300,i2,UP,CALU1 +S 5000,2100,5000,5900,300,i3,UP,CALU1 +S 8000,2100,8000,7900,300,q,UP,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 5000,6100,5000,6400,200,*,UP,POLY +S 4600,2600,4600,2900,200,*,UP,POLY +S 2600,2600,2600,2900,200,*,UP,POLY +S 1500,2600,1500,2900,200,*,UP,POLY +S 1200,3000,1200,6200,200,*,UP,POLY +S 4800,3000,4800,6000,200,*,UP,POLY +S 4800,6100,5000,6100,200,*,RIGHT,POLY +S 4600,2900,4800,2900,200,*,RIGHT,POLY +S 1200,2900,1500,2900,200,*,RIGHT,POLY +S 800,800,800,2300,400,*,UP,NDIF +S 6800,800,6800,2300,600,*,UP,NDIF +S 8000,800,8000,2300,600,*,UP,NDIF +S 7400,600,7400,2500,200,*,UP,NTRANS +S 9100,800,9100,2300,600,*,UP,NDIF +S 8600,600,8600,2500,200,*,UP,NTRANS +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 1800,6700,1800,8300,600,*,UP,PDIF +S 5000,2100,5000,5900,300,*,UP,ALU1 +S 4000,2100,4000,5900,300,*,UP,ALU1 +S 700,8000,5300,8000,300,*,RIGHT,ALU1 +S 2000,2100,2000,5900,300,*,UP,ALU1 +S 1000,2100,1000,5900,300,*,UP,ALU1 +S -300,7800,10300,7800,6000,*,RIGHT,NWELL +S 6800,8100,6800,8900,300,*,UP,ALU1 +S 6800,5700,6800,9300,600,*,UP,PDIF +S 8600,5500,8600,9500,200,*,UP,PTRANS +S 7400,5500,7400,9500,200,*,UP,PTRANS +S 8000,5700,8000,9300,600,*,UP,PDIF +S 1900,7000,6900,7000,300,*,RIGHT,ALU1 +S 7000,4100,7000,6900,300,*,UP,ALU1 +S 9000,6100,9000,8900,300,*,UP,ALU1 +S 7400,2800,7400,5200,200,*,UP,POLY +S 8600,2800,8600,5200,200,*,UP,POLY +S 6800,1100,6800,1900,300,*,UP,ALU1 +S 8000,2100,8000,7900,300,*,UP,ALU1 +S 7000,4100,8600,4100,400,*,RIGHT,POLY +S 700,6700,700,8300,400,*,UP,PDIF +S 3400,6500,3400,8500,200,*,UP,PTRANS +S 1500,1500,1500,2500,200,*,UP,NTRANS +S 2600,1500,2600,2500,200,*,UP,NTRANS +S 2000,1700,2000,2300,600,*,UP,NDIF +S 3700,1500,3700,2500,200,*,UP,NTRANS +S 4600,1500,4600,2500,200,*,UP,NTRANS +S 5000,6500,5000,8500,200,*,UP,PTRANS +S 9100,5700,9100,9300,600,*,UP,PDIF +S 9000,1100,9000,1900,300,*,UP,ALU1 +S 5400,900,5400,2300,600,*,UP,NDIF +S 4200,6700,4200,9100,600,*,UP,PDIF +S 4200,1700,4200,2300,600,*,UP,NDIF +S 3000,1700,3000,2300,600,*,UP,NDIF +S 2400,6500,2400,8500,200,*,UP,PTRANS +S 5400,6700,5400,8300,600,*,UP,PDIF +S 3000,6700,3000,8300,600,*,UP,PDIF +S 2000,2100,2000,5900,300,i1,UP,CALU1 +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 9000,2000,CONT_DIF_N,* +V 800,8000,CONT_DIF_P,* +V 6800,9200,CONT_DIF_P,* +V 6800,900,CONT_DIF_N,* +V 4200,9200,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 1800,7000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 9000,9200,CONT_DIF_P,* +V 6800,8000,CONT_DIF_P,* +V 6800,2000,CONT_DIF_N,* +V 8000,2000,CONT_DIF_N,* +V 5400,900,CONT_DIF_N,* +V 7100,4100,CONT_POLY,* +V 9000,900,CONT_DIF_N,* +V 800,800,CONT_DIF_N,* +V 8000,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa2a22_x4.vbe b/pdks/symbolic/nsxlib/cells/oa2a22_x4.vbe new file mode 100644 index 000000000..a233499c0 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 519; + CONSTANT tpll_i2_q : NATURAL := 596; + CONSTANT tpll_i3_q : NATURAL := 619; + CONSTANT tphh_i1_q : NATURAL := 624; + CONSTANT tphh_i3_q : NATURAL := 644; + CONSTANT tpll_i1_q : NATURAL := 669; + CONSTANT tpll_i0_q : NATURAL := 696; + CONSTANT tphh_i2_q : NATURAL := 763; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa2a2a23_x2.ap b/pdks/symbolic/nsxlib/cells/oa2a2a23_x2.ap new file mode 100644 index 000000000..418422e25 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a2a23_x2.ap @@ -0,0 +1,144 @@ +V ALLIANCE : 6 +H oa2a2a23_x2,P,29/ 4/2024,100 +A 0,0,12000,10000 +R 2000,4000,ref_ref,i5_20 +R 2000,5000,ref_ref,i5_25 +R 2000,6000,ref_ref,i5_30 +R 2000,3000,ref_ref,i5_15 +R 4000,3000,ref_ref,i3_15 +R 4000,5000,ref_ref,i3_25 +R 4000,6000,ref_ref,i3_30 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +R 5000,5000,ref_ref,i2_25 +R 5000,6000,ref_ref,i2_30 +R 4000,4000,ref_ref,i3_20 +R 3000,3000,ref_ref,i4_15 +R 3000,4000,ref_ref,i4_20 +R 3000,5000,ref_ref,i4_25 +R 3000,6000,ref_ref,i4_30 +R 3000,7000,ref_ref,i4_35 +R 11000,4000,ref_ref,q_20 +R 11000,5000,ref_ref,q_25 +R 11000,6000,ref_ref,q_30 +R 9000,3000,ref_ref,i0_15 +R 11000,8000,ref_ref,q_40 +R 11000,7000,ref_ref,q_35 +R 11000,3000,ref_ref,q_15 +R 11000,2000,ref_ref,q_10 +R 9000,4000,ref_ref,i0_20 +R 9000,5000,ref_ref,i0_25 +R 8000,4000,ref_ref,i1_20 +R 8000,3000,ref_ref,i1_15 +R 8000,5000,ref_ref,i1_25 +R 8000,6000,ref_ref,i1_30 +R 9000,6000,ref_ref,i0_30 +S 3600,5100,4000,5100,200,*,RIGHT,POLY +S 9800,2100,9800,3900,300,*,UP,ALU1 +S 6400,1000,6400,1700,600,*,UP,PTIE +S 0,9400,12000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,12000,600,1200,vss,RIGHT,CALU1 +S 8000,5100,8000,5300,200,*,UP,POLY +S 10000,4000,10400,4000,400,*,RIGHT,POLY +S 800,5700,800,9300,600,*,UP,PDIF +S 900,8000,5300,8000,300,*,RIGHT,ALU1 +S 4200,5700,4200,9300,600,*,UP,PDIF +S 1800,5700,1800,9300,600,*,UP,PDIF +S 3000,5700,3000,9300,600,*,UP,PDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 2000,3100,2000,5900,300,*,UP,ALU1 +S 4000,3100,4000,5900,300,*,UP,ALU1 +S 5000,3100,5000,5900,300,*,UP,ALU1 +S 3000,3100,3000,6900,300,*,UP,ALU1 +S 9800,7100,9800,9100,300,*,UP,ALU1 +S 8600,7100,8600,7900,300,*,UP,ALU1 +S 8000,5500,8000,9500,200,*,UP,PTRANS +S 9200,5500,9200,9500,200,*,UP,PTRANS +S 8600,5700,8600,9300,600,*,UP,PDIF +S 9800,5700,9800,9300,600,*,UP,PDIF +S 11000,5700,11000,9300,600,*,UP,PDIF +S 10400,5500,10400,9500,200,*,UP,PTRANS +S 8000,3100,8000,5900,300,*,UP,ALU1 +S 9000,3100,9000,5900,300,*,UP,ALU1 +S 9200,2800,9200,5200,200,*,UP,POLY +S 4300,7000,8500,7000,300,*,RIGHT,ALU1 +S 5400,5700,5400,9300,600,*,UP,PDIF +S 1100,6900,1700,6900,300,*,RIGHT,ALU1 +S 9800,800,9800,2300,600,*,UP,NDIF +S 1100,2000,9900,2000,300,*,RIGHT,ALU1 +S 10400,2800,10400,5200,200,*,UP,POLY +S 7800,800,7800,2300,600,*,UP,NDIF +S 4500,600,4500,2500,200,*,UP,NTRANS +S 9200,600,9200,2500,200,*,UP,NTRANS +S 8300,600,8300,2500,200,*,UP,NTRANS +S 10400,600,10400,2500,200,*,UP,NTRANS +S 11000,800,11000,2300,600,*,UP,NDIF +S 4800,3000,4800,5200,200,*,UP,POLY +S 1600,2900,1800,2900,200,*,RIGHT,POLY +S 2400,2900,2800,2900,200,*,RIGHT,POLY +S 3600,2900,3800,2900,200,*,RIGHT,POLY +S 4500,2900,4800,2900,200,*,RIGHT,POLY +S 8000,2900,8300,2900,200,*,RIGHT,POLY +S 2400,5100,2800,5100,200,*,RIGHT,POLY +S 1200,5100,1800,5100,200,*,RIGHT,POLY +S 3800,3000,3800,5100,200,*,UP,POLY +S 2800,3000,2800,5000,200,*,UP,POLY +S 1800,3000,1800,5000,200,*,UP,POLY +S 8000,3000,8000,5000,200,*,UP,POLY +S 1000,2100,1000,6800,300,*,UP,ALU1 +S 8300,2600,8300,2900,200,*,UP,POLY +S 4500,2700,4500,2900,200,*,UP,POLY +S 3600,2600,3600,2900,200,*,UP,POLY +S 2400,2700,2400,2900,200,*,UP,POLY +S 1600,2700,1600,2900,200,*,UP,POLY +S 2400,5100,2400,5400,200,*,UP,POLY +S 1200,5100,1200,5400,200,*,UP,POLY +S -300,7800,12300,7800,6000,*,RIGHT,NWELL +S 7400,5700,7400,9300,600,*,UP,PDIF +S 7400,8100,7400,9100,300,*,UP,ALU1 +S 1000,800,1000,2300,600,*,UP,NDIF +S 1600,600,1600,2500,200,*,UP,NTRANS +S 2400,600,2400,2500,200,*,UP,NTRANS +S 3600,600,3600,2500,200,*,UP,NTRANS +S 3000,800,3000,2300,600,*,UP,NDIF +S 5000,800,5000,2300,600,*,UP,NDIF +S 11000,2100,11000,7900,300,q,UP,CALU1 +S 11000,2100,11000,7900,300,*,UP,ALU1 +S 9000,3100,9000,5900,300,i0,UP,CALU1 +S 8000,3100,8000,5900,300,i1,UP,CALU1 +S 5000,3100,5000,5900,300,i2,UP,CALU1 +S 4000,3100,4000,5900,300,i3,UP,CALU1 +S 3000,3100,3000,6900,300,i4,UP,CALU1 +S 2000,3100,2000,5900,300,i5,UP,CALU1 +V 9800,4000,CONT_POLY,* +V 11000,7000,CONT_DIF_P,* +V 11000,6000,CONT_DIF_P,* +V 9000,5000,CONT_POLY,* +V 8000,5000,CONT_POLY,* +V 6400,800,CONT_BODY_P,* +V 11000,2000,CONT_DIF_N,* +V 8600,8000,CONT_DIF_P,* +V 9800,7000,CONT_DIF_P,* +V 9800,8000,CONT_DIF_P,* +V 11000,8000,CONT_DIF_P,* +V 1000,900,CONT_DIF_N,* +V 5000,900,CONT_DIF_N,* +V 9800,900,CONT_DIF_N,* +V 7400,8000,CONT_DIF_P,* +V 7800,2000,CONT_DIF_N,* +V 2000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 9800,9200,CONT_DIF_P,* +V 7400,9200,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 1800,7000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 5000,5000,CONT_POLY,* +V 4000,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa2a2a23_x2.vbe b/pdks/symbolic/nsxlib/cells/oa2a2a23_x2.vbe new file mode 100644 index 000000000..189ed7159 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a2a23_x2.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT tphh_i5_q : NATURAL := 321; + CONSTANT tphh_i4_q : NATURAL := 402; + CONSTANT tphh_i2_q : NATURAL := 441; + CONSTANT tphh_i3_q : NATURAL := 540; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT tpll_i4_q : NATURAL := 591; + CONSTANT tpll_i3_q : NATURAL := 600; + CONSTANT tpll_i5_q : NATURAL := 636; + CONSTANT tpll_i2_q : NATURAL := 639; + CONSTANT tphh_i0_q : NATURAL := 653; + CONSTANT tphh_i1_q : NATURAL := 775; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x2" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa2a2a23_x4.ap b/pdks/symbolic/nsxlib/cells/oa2a2a23_x4.ap new file mode 100644 index 000000000..4067c85ff --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a2a23_x4.ap @@ -0,0 +1,156 @@ +V ALLIANCE : 6 +H oa2a2a23_x4,P,18/ 9/2019,100 +A 0,0,13000,10000 +R 8000,5000,ref_ref,i1_25 +R 8000,6000,ref_ref,i1_30 +R 9000,6000,ref_ref,i0_30 +R 9000,3000,ref_ref,i0_15 +R 3000,6000,ref_ref,i4_30 +R 3000,5000,ref_ref,i4_25 +R 3000,4000,ref_ref,i4_20 +R 3000,3000,ref_ref,i4_15 +R 4000,4000,ref_ref,i3_20 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +R 8000,3000,ref_ref,i1_15 +R 8000,4000,ref_ref,i1_20 +R 9000,5000,ref_ref,i0_25 +R 9000,4000,ref_ref,i0_20 +R 11000,2000,ref_ref,q_10 +R 11000,3000,ref_ref,q_15 +R 11000,7000,ref_ref,q_35 +R 3000,7000,ref_ref,i4_35 +R 11000,4000,ref_ref,q_20 +R 11000,5000,ref_ref,q_25 +R 11000,6000,ref_ref,q_30 +R 11000,8000,ref_ref,q_40 +R 2000,4000,ref_ref,i5_20 +R 2000,5000,ref_ref,i5_25 +R 2000,6000,ref_ref,i5_30 +R 2000,3000,ref_ref,i5_15 +R 4000,3000,ref_ref,i3_15 +R 4000,5000,ref_ref,i3_25 +R 4000,6000,ref_ref,i3_30 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +S 2000,3100,2000,5900,300,i5,UP,CALU1 +S 3000,3100,3000,6900,300,i4,UP,CALU1 +S 4000,3100,4000,5900,300,i3,UP,CALU1 +S 5000,3100,5000,5900,300,i2,UP,CALU1 +S 8000,3100,8000,5900,300,i1,UP,CALU1 +S 9000,3100,9000,5900,300,i0,UP,CALU1 +S 11000,2100,11000,7900,300,*,UP,ALU1 +S 11000,2100,11000,7900,300,q,UP,CALU1 +S 7400,8100,7400,9100,300,*,UP,ALU1 +S 10000,4000,11600,4000,200,*,RIGHT,POLY +S 11600,2800,11600,5200,200,*,UP,POLY +S 1100,2000,9900,2000,300,*,RIGHT,ALU1 +S 1000,2100,1000,6800,300,*,UP,ALU1 +S 1100,6900,1700,6900,300,*,RIGHT,ALU1 +S 5400,5700,5400,9300,600,*,UP,PDIF +S 4300,7000,8500,7000,300,*,RIGHT,ALU1 +S 9200,2800,9200,5200,200,*,UP,POLY +S 9000,3100,9000,5900,300,*,UP,ALU1 +S 8000,3100,8000,5900,300,*,UP,ALU1 +S 11600,5500,11600,9500,200,*,UP,PTRANS +S 11000,5700,11000,9300,600,*,UP,PDIF +S 9800,5700,9800,9300,600,*,UP,PDIF +S 8600,5700,8600,9300,600,*,UP,PDIF +S 9200,5500,9200,9500,200,*,UP,PTRANS +S 1800,5700,1800,9300,600,*,UP,PDIF +S 9800,7100,9800,9100,300,*,UP,ALU1 +S 8600,7100,8600,7900,300,*,UP,ALU1 +S 8000,5500,8000,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 700,8000,5300,8000,300,*,RIGHT,ALU1 +S 12100,5700,12100,9300,600,*,UP,PDIF +S 12000,7100,12000,9100,300,*,UP,ALU1 +S 12000,700,12000,1900,300,*,UP,ALU1 +S 700,5700,700,9300,400,*,UP,PDIF +S 9900,2100,9900,3900,300,*,UP,ALU1 +S 10300,2800,10300,5200,200,*,UP,POLY +S 10300,5500,10300,9500,200,*,UP,PTRANS +S 10300,600,10300,2500,200,*,UP,NTRANS +S 3000,5700,3000,9300,600,*,UP,PDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 3600,5500,3600,9500,200,*,UP,PTRANS +S -300,7800,13300,7800,6000,*,RIGHT,NWELL +S 3000,3100,3000,6900,300,*,UP,ALU1 +S 5000,3100,5000,5900,300,*,UP,ALU1 +S 4000,3100,4000,5900,300,*,UP,ALU1 +S 2000,3100,2000,5900,300,*,UP,ALU1 +S 7400,5700,7400,9300,600,*,UP,PDIF +S 11600,600,11600,2500,200,*,UP,NTRANS +S 12200,800,12200,2300,600,*,UP,NDIF +S 11000,800,11000,2300,600,*,UP,NDIF +S 9200,600,9200,2500,200,*,UP,NTRANS +S 9800,800,9800,2300,600,*,UP,NDIF +S 8300,600,8300,2500,200,*,UP,NTRANS +S 7800,800,7800,2300,600,*,UP,NDIF +S 5000,800,5000,2300,600,*,UP,NDIF +S 4400,600,4400,2500,200,*,UP,NTRANS +S 3500,600,3500,2500,200,*,UP,NTRANS +S 3000,800,3000,2300,600,*,UP,NDIF +S 2500,600,2500,2500,200,*,UP,NTRANS +S 1600,600,1600,2500,200,*,UP,NTRANS +S 1000,800,1000,2300,600,*,UP,NDIF +S 1600,2900,1800,2900,200,*,RIGHT,POLY +S 2500,2900,2800,2900,200,*,RIGHT,POLY +S 3500,2900,3800,2900,200,*,RIGHT,POLY +S 4400,2900,4800,2900,200,*,RIGHT,POLY +S 8000,2900,8300,2900,200,*,RIGHT,POLY +S 3600,5100,3800,5100,200,*,RIGHT,POLY +S 2400,5100,2800,5100,200,*,RIGHT,POLY +S 1200,5100,1800,5100,200,*,RIGHT,POLY +S 3800,3100,3800,5000,200,*,UP,POLY +S 4800,3000,4800,5200,200,*,UP,POLY +S 8000,3000,8000,5700,200,*,UP,POLY +S 1800,3000,1800,5000,200,*,UP,POLY +S 2800,3000,2800,5000,200,*,UP,POLY +S 1200,5100,1200,5400,200,*,UP,POLY +S 2400,5100,2400,5400,200,*,UP,POLY +S 3600,5100,3600,5400,200,*,UP,POLY +S 4400,2600,4400,2900,200,*,UP,POLY +S 3500,2700,3500,2900,200,*,UP,POLY +S 2500,2600,2500,2900,200,*,UP,POLY +S 1600,2600,1600,2900,200,*,UP,POLY +S 8300,2700,8300,2900,200,*,UP,POLY +S 0,600,13000,600,1200,vss,RIGHT,CALU1 +S 0,9400,13000,9400,1200,vdd,RIGHT,CALU1 +S 6400,900,6400,1700,600,*,UP,PTIE +V 9800,8000,CONT_DIF_P,* +V 11000,8000,CONT_DIF_P,* +V 11000,7000,CONT_DIF_P,* +V 9800,7000,CONT_DIF_P,* +V 8600,8000,CONT_DIF_P,* +V 7400,8000,CONT_DIF_P,* +V 11000,2000,CONT_DIF_N,* +V 7800,2000,CONT_DIF_N,* +V 2000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 5400,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 1800,7000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 12000,9200,CONT_DIF_P,* +V 12000,8000,CONT_DIF_P,* +V 12000,7000,CONT_DIF_P,* +V 12000,2000,CONT_DIF_N,* +V 9800,9200,CONT_DIF_P,* +V 7400,9200,CONT_DIF_P,* +V 10000,3900,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 800,8000,CONT_DIF_P,* +V 12000,900,CONT_DIF_N,* +V 9800,900,CONT_DIF_N,* +V 5000,900,CONT_DIF_N,* +V 1200,900,CONT_DIF_N,* +V 6400,800,CONT_BODY_P,* +V 11000,6000,CONT_DIF_P,* +V 9000,5000,CONT_POLY,* +V 8000,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa2a2a23_x4.vbe b/pdks/symbolic/nsxlib/cells/oa2a2a23_x4.vbe new file mode 100644 index 000000000..c39f56f93 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT tphh_i5_q : NATURAL := 379; + CONSTANT tphh_i4_q : NATURAL := 464; + CONSTANT tphh_i2_q : NATURAL := 493; + CONSTANT tphh_i3_q : NATURAL := 594; + CONSTANT tpll_i1_q : NATURAL := 613; + CONSTANT tpll_i0_q : NATURAL := 648; + CONSTANT tpll_i4_q : NATURAL := 673; + CONSTANT tpll_i3_q : NATURAL := 677; + CONSTANT tphh_i0_q : NATURAL := 699; + CONSTANT tpll_i5_q : NATURAL := 714; + CONSTANT tpll_i2_q : NATURAL := 715; + CONSTANT tphh_i1_q : NATURAL := 822; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x4" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x2.ap b/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x2.ap new file mode 100644 index 000000000..c592b8694 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x2.ap @@ -0,0 +1,179 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x2,P,25/ 9/2019,100 +A 0,0,15000,10000 +R 3000,6000,ref_ref,i6_30 +R 3000,5000,ref_ref,i6_25 +R 3000,4000,ref_ref,i6_20 +R 3000,3000,ref_ref,i6_15 +R 8000,4000,ref_ref,i2_20 +R 8000,3000,ref_ref,i2_15 +R 7000,6000,ref_ref,i3_30 +R 7000,5000,ref_ref,i3_25 +R 7000,4000,ref_ref,i3_20 +R 7000,3000,ref_ref,i3_15 +R 6000,6000,ref_ref,i4_30 +R 6000,5000,ref_ref,i4_25 +R 6000,4000,ref_ref,i4_20 +R 13000,3000,ref_ref,i0_15 +R 1000,6000,ref_ref,i7_30 +R 1000,5000,ref_ref,i7_25 +R 1000,4000,ref_ref,i7_20 +R 1000,3000,ref_ref,i7_15 +R 1000,2000,ref_ref,i7_10 +R 14000,5000,ref_ref,q_25 +R 13000,7000,ref_ref,i0_35 +R 11000,4000,ref_ref,i1_20 +R 11000,5000,ref_ref,i1_25 +R 11000,6000,ref_ref,i1_30 +R 11000,3000,ref_ref,i1_15 +R 8000,5000,ref_ref,i2_25 +R 8000,6000,ref_ref,i2_30 +R 6000,3000,ref_ref,i4_15 +R 5000,6000,ref_ref,i5_30 +R 5000,5000,ref_ref,i5_25 +R 5000,4000,ref_ref,i5_20 +R 5000,3000,ref_ref,i5_15 +R 14000,3000,ref_ref,q_15 +R 14000,4000,ref_ref,q_20 +R 13000,6000,ref_ref,i0_30 +R 13000,5000,ref_ref,i0_25 +R 13000,4000,ref_ref,i0_20 +S 8000,5200,8400,5200,200,*,RIGHT,POLY +S 8400,5200,8400,5500,200,*,UP,POLY +S 12400,2600,12400,2800,200,*,UP,POLY +S 12400,2800,13000,2800,200,*,RIGHT,POLY +S 12400,5200,12400,5400,200,*,UP,POLY +S 12400,5200,13000,5200,200,*,RIGHT,POLY +S 11500,2500,11500,2800,200,*,UP,POLY +S 11000,2800,11500,2800,200,*,RIGHT,POLY +S 9800,1000,9800,1700,600,*,UP,PTIE +S 6000,5500,6000,9500,200,*,UP,PTRANS +S 6600,5700,6600,9300,600,*,UP,PDIF +S 5400,5700,5400,9300,600,*,UP,PDIF +S 7800,5700,7800,9300,600,*,UP,PDIF +S 8400,5500,8400,9500,200,*,UP,PTRANS +S 1800,5700,1800,9300,600,*,UP,PDIF +S 2400,5000,3000,5000,400,*,RIGHT,POLY +S 9600,4000,13600,4000,400,*,RIGHT,POLY +S 4800,5100,5200,5100,200,*,RIGHT,POLY +S 6100,2800,6100,5000,200,*,UP,POLY +S 4800,5100,4800,5400,200,*,UP,POLY +S 3000,5700,3000,9300,600,*,UP,PDIF +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 7200,5500,7200,9500,200,*,UP,PTRANS +S 3000,3100,3000,5900,300,*,UP,ALU1 +S 5000,3100,5000,5900,300,*,UP,ALU1 +S 6000,3100,6000,5900,300,*,UP,ALU1 +S 7000,3100,7000,5900,300,*,UP,ALU1 +S 8000,3100,8000,5900,300,*,UP,ALU1 +S 1000,2100,1000,5900,300,*,UP,ALU1 +S 6600,7100,6600,7900,300,*,UP,ALU1 +S 1900,7000,1900,7000,300,*,LEFT,ALU1 +S 2000,2100,2000,6900,300,*,UP,ALU1 +S 13600,2800,13600,5200,200,*,UP,POLY +S 11800,5700,11800,9300,600,*,UP,PDIF +S 12400,5500,12400,9500,200,*,UP,PTRANS +S 11200,5500,11200,9500,200,*,UP,PTRANS +S 13000,5700,13000,9300,600,*,UP,PDIF +S 13600,5500,13600,9500,200,*,UP,PTRANS +S 14200,5700,14200,9300,600,*,UP,PDIF +S 4600,800,4600,2300,600,*,UP,NDIF +S 1200,2800,1200,5200,200,*,UP,POLY +S 7200,2800,7200,5200,200,*,UP,POLY +S -300,7800,15300,7800,6000,*,RIGHT,NWELL +S 800,7100,800,7900,300,*,UP,ALU1 +S 700,5700,700,9300,400,*,UP,PDIF +S 8100,2800,8100,5100,200,*,UP,POLY +S 5200,2800,5200,5100,200,*,UP,POLY +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 3100,7000,5300,7000,300,*,RIGHT,ALU1 +S 4300,8000,8900,8000,300,*,RIGHT,ALU1 +S 700,8000,2900,8000,300,*,RIGHT,ALU1 +S 3000,7100,3000,7900,300,*,UP,ALU1 +S 2400,2800,2400,5200,200,*,UP,POLY +S 10600,8100,10600,9100,300,*,UP,ALU1 +S 2100,2000,10900,2000,300,*,RIGHT,ALU1 +S 700,800,700,2300,400,*,UP,NDIF +S 1200,600,1200,2500,200,*,UP,NTRANS +S 2400,600,2400,2500,200,*,UP,NTRANS +S 1800,800,1800,2300,600,*,UP,NDIF +S 3000,800,3000,2300,600,*,UP,NDIF +S 13000,800,13000,2300,600,*,UP,NDIF +S 14200,800,14200,2300,600,*,UP,NDIF +S 13600,600,13600,2500,200,*,UP,NTRANS +S 5200,600,5200,2500,200,*,UP,NTRANS +S 7200,600,7200,2500,200,*,UP,NTRANS +S 6600,800,6600,2300,600,*,UP,NDIF +S 6100,600,6100,2500,200,*,UP,NTRANS +S 8600,800,8600,2300,600,*,UP,NDIF +S 8100,600,8100,2500,200,*,UP,NTRANS +S 11000,800,11000,2300,600,*,UP,NDIF +S 11500,600,11500,2500,200,*,UP,NTRANS +S 12400,600,12400,2500,200,*,UP,NTRANS +S 6000,5100,6000,5400,200,*,UP,POLY +S 11200,4900,11200,5300,200,*,UP,POLY +S 13000,8100,13000,9100,300,*,UP,ALU1 +S 11800,7100,11800,7900,300,*,UP,ALU1 +S 7900,7000,11700,7000,300,*,RIGHT,ALU1 +S 12700,5000,12900,5000,300,*,RIGHT,ALU1 +S 12700,3000,12900,3000,300,*,RIGHT,ALU1 +S 9600,2100,9600,3900,300,*,UP,ALU1 +S 11000,3100,11000,5900,300,*,UP,ALU1 +S 11100,3000,11300,3000,300,*,RIGHT,ALU1 +S 13000,3100,13000,6900,300,*,UP,ALU1 +S 9000,5700,9000,9300,600,*,UP,PDIF +S 10600,5700,10600,9300,600,*,UP,PDIF +S 0,600,15000,600,1200,vss,RIGHT,CALU1 +S 0,9400,15000,9400,1200,vdd,RIGHT,CALU1 +S 14000,2100,14000,7900,300,*,UP,ALU1 +S 14000,2100,14000,7900,300,q,UP,CALU1 +S 13000,3100,13000,6900,300,i0,UP,CALU1 +S 11000,3100,11000,5900,300,i1,UP,CALU1 +S 8000,3100,8000,5900,300,i2,UP,CALU1 +S 7000,3100,7000,5800,300,i3,UP,CALU1 +S 6000,3100,6000,5900,300,i4,UP,CALU1 +S 5000,3100,5000,5900,300,i5,UP,CALU1 +S 1000,2100,1000,5900,300,i7,UP,CALU1 +S 3000,3100,3000,5900,300,i6,UP,CALU1 +V 13000,9200,CONT_DIF_P,* +V 10600,9200,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 13000,5000,CONT_POLY,* +V 13000,3000,CONT_POLY,* +V 11000,3000,CONT_POLY,* +V 11000,5000,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 13000,900,CONT_DIF_N,* +V 8600,900,CONT_DIF_N,* +V 4600,900,CONT_DIF_N,* +V 800,900,CONT_DIF_N,* +V 9600,4000,CONT_POLY,* +V 9800,800,CONT_BODY_P,* +V 11000,2000,CONT_DIF_N,* +V 10600,8000,CONT_DIF_P,* +V 11800,8000,CONT_DIF_P,* +V 7800,7000,CONT_DIF_P,* +V 13000,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 6600,7000,CONT_DIF_P,* +V 8000,5000,CONT_POLY,* +V 7000,5000,CONT_POLY,* +V 6000,5000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 3000,8000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,* +V 6600,8000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,* +V 1800,7000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 6600,2000,CONT_DIF_N,* +V 14000,2000,CONT_DIF_N,* +V 14000,8000,CONT_DIF_P,* +V 14000,7000,CONT_DIF_P,* +V 14000,6000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x2.vbe b/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x2.vbe new file mode 100644 index 000000000..39a24492c --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x2.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rdown_i7_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT rup_i7_q : NATURAL := 1790; + CONSTANT tphh_i7_q : NATURAL := 346; + CONSTANT tphh_i6_q : NATURAL := 426; + CONSTANT tphh_i5_q : NATURAL := 467; + CONSTANT tphh_i4_q : NATURAL := 565; + CONSTANT tphh_i2_q : NATURAL := 682; + CONSTANT tpll_i6_q : NATURAL := 748; + CONSTANT tpll_i1_q : NATURAL := 753; + CONSTANT tphh_i0_q : NATURAL := 780; + CONSTANT tpll_i0_q : NATURAL := 797; + CONSTANT tpll_i7_q : NATURAL := 800; + CONSTANT tphh_i3_q : NATURAL := 803; + CONSTANT tpll_i3_q : NATURAL := 810; + CONSTANT tpll_i4_q : NATURAL := 813; + CONSTANT tpll_i2_q : NATURAL := 856; + CONSTANT tpll_i5_q : NATURAL := 861; + CONSTANT tphh_i1_q : NATURAL := 909; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x2" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1500 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x4.ap b/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x4.ap new file mode 100644 index 000000000..914ae0cea --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x4.ap @@ -0,0 +1,187 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x4,P,25/ 9/2019,100 +A 0,0,16000,10000 +R 3000,6000,ref_ref,i6_30 +R 3000,5000,ref_ref,i6_25 +R 3000,4000,ref_ref,i6_20 +R 3000,3000,ref_ref,i6_15 +R 1000,6000,ref_ref,i7_30 +R 1000,5000,ref_ref,i7_25 +R 1000,4000,ref_ref,i7_20 +R 1000,3000,ref_ref,i7_15 +R 5000,6000,ref_ref,i5_30 +R 6000,3000,ref_ref,i4_15 +R 8000,6000,ref_ref,i2_30 +R 8000,5000,ref_ref,i2_25 +R 8000,4000,ref_ref,i2_20 +R 8000,3000,ref_ref,i2_15 +R 7000,6000,ref_ref,i3_30 +R 7000,5000,ref_ref,i3_25 +R 7000,4000,ref_ref,i3_20 +R 7000,3000,ref_ref,i3_15 +R 1000,2000,ref_ref,i7_10 +R 14000,5000,ref_ref,q_25 +R 13000,7000,ref_ref,i0_35 +R 11000,4000,ref_ref,i1_20 +R 11000,5000,ref_ref,i1_25 +R 11000,6000,ref_ref,i1_30 +R 11000,3000,ref_ref,i1_15 +R 13000,3000,ref_ref,i0_15 +R 6000,4000,ref_ref,i4_20 +R 6000,5000,ref_ref,i4_25 +R 6000,6000,ref_ref,i4_30 +R 5000,5000,ref_ref,i5_25 +R 5000,4000,ref_ref,i5_20 +R 5000,3000,ref_ref,i5_15 +R 14000,3000,ref_ref,q_15 +R 14000,4000,ref_ref,q_20 +R 13000,6000,ref_ref,i0_30 +R 13000,5000,ref_ref,i0_25 +R 13000,4000,ref_ref,i0_20 +S 11000,2800,11600,2800,200,*,RIGHT,POLY +S 12500,2800,13000,2800,200,*,RIGHT,POLY +S 12400,5200,13000,5200,200,*,RIGHT,POLY +S 12400,5200,12400,5300,200,*,UP,POLY +S 8400,5200,8400,5400,200,*,UP,POLY +S 8000,5200,8400,5200,200,*,RIGHT,POLY +S 9800,1000,9800,1700,600,*,UP,PTIE +S 2400,2800,2400,5200,200,*,UP,POLY +S 3000,7100,3000,7900,300,*,UP,ALU1 +S 700,8000,2900,8000,300,*,RIGHT,ALU1 +S 3000,5700,3000,9300,600,*,UP,PDIF +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 7200,5500,7200,9500,200,*,UP,PTRANS +S 3000,3100,3000,5900,300,*,UP,ALU1 +S 5000,3100,5000,5900,300,*,UP,ALU1 +S 6000,3100,6000,5900,300,*,UP,ALU1 +S 7000,3100,7000,5900,300,*,UP,ALU1 +S 8000,3100,8000,5900,300,*,UP,ALU1 +S 1000,2100,1000,5900,300,*,UP,ALU1 +S 12500,2700,12500,2800,200,*,UP,POLY +S 11600,2700,11600,2800,200,*,UP,POLY +S 15300,5700,15300,9300,400,*,UP,PDIF +S 15200,7100,15200,9100,300,*,UP,ALU1 +S 9000,5700,9000,9300,600,*,UP,PDIF +S 6600,7100,6600,7900,300,*,UP,ALU1 +S 1800,5700,1800,9300,600,*,UP,PDIF +S 8400,5500,8400,9500,200,*,UP,PTRANS +S 9600,4000,14800,4000,400,*,RIGHT,POLY +S 6000,5000,6000,5300,200,*,UP,POLY +S 2400,5000,3000,5000,400,*,RIGHT,POLY +S 6100,2800,6100,5100,200,*,UP,POLY +S 8100,2800,8100,4900,200,*,UP,POLY +S 5200,2800,5200,5100,200,*,UP,POLY +S 700,5700,700,9300,400,*,UP,PDIF +S 800,7100,800,7900,300,*,UP,ALU1 +S 15200,700,15200,1900,300,*,UP,ALU1 +S 7800,5700,7800,9300,600,*,UP,PDIF +S 5400,5700,5400,9300,600,*,UP,PDIF +S 6600,5700,6600,9300,600,*,UP,PDIF +S 6000,5500,6000,9500,200,*,UP,PTRANS +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 3100,7000,5300,7000,300,*,RIGHT,ALU1 +S 4300,8000,8900,8000,300,*,RIGHT,ALU1 +S 700,800,700,2300,400,*,UP,NDIF +S 1200,600,1200,2500,200,*,UP,NTRANS +S 13000,3100,13000,6900,300,*,UP,ALU1 +S 13000,5700,13000,9300,600,*,UP,PDIF +S 13600,5500,13600,9500,200,*,UP,PTRANS +S 14200,5700,14200,9300,600,*,UP,PDIF +S 7900,7000,11700,7000,300,*,RIGHT,ALU1 +S 11800,7100,11800,7900,300,*,UP,ALU1 +S 13000,8100,13000,9100,300,*,UP,ALU1 +S 10600,8100,10600,9100,300,*,UP,ALU1 +S 2100,2000,10900,2000,300,*,RIGHT,ALU1 +S 9600,2100,9600,3900,300,*,UP,ALU1 +S 11000,3100,11000,5900,300,*,UP,ALU1 +S 15300,800,15300,2300,400,*,UP,NDIF +S 4800,4900,4800,5300,200,*,UP,POLY +S 11200,4900,11200,5300,200,*,UP,POLY +S 13600,600,13600,2500,200,*,UP,NTRANS +S 14800,600,14800,2500,200,*,UP,NTRANS +S 12500,600,12500,2500,200,*,UP,NTRANS +S 13000,800,13000,2300,600,*,UP,NDIF +S 11000,800,11000,2300,600,*,UP,NDIF +S 11600,600,11600,2500,200,*,UP,NTRANS +S 8600,800,8600,2300,600,*,UP,NDIF +S 8100,600,8100,2500,200,*,UP,NTRANS +S 7200,600,7200,2500,200,*,UP,NTRANS +S 6100,600,6100,2500,200,*,UP,NTRANS +S 14800,5500,14800,9500,200,*,UP,PTRANS +S 11200,5500,11200,9500,200,*,UP,PTRANS +S 12400,5500,12400,9500,200,*,UP,PTRANS +S 11800,5700,11800,9300,600,*,UP,PDIF +S 13600,2800,13600,5200,200,*,UP,POLY +S 14800,2800,14800,5200,200,*,UP,POLY +S 10600,5700,10600,9300,600,*,UP,PDIF +S 7200,2800,7200,5200,200,*,UP,POLY +S 1200,2800,1200,5200,200,*,UP,POLY +S 2400,600,2400,2500,200,*,UP,NTRANS +S 1800,800,1800,2300,600,*,UP,NDIF +S 3000,800,3000,2300,600,*,UP,NDIF +S 4600,800,4600,2300,600,*,UP,NDIF +S 5200,600,5200,2500,200,*,UP,NTRANS +S 6600,800,6600,2300,600,*,UP,NDIF +S 14200,800,14200,2300,600,*,UP,NDIF +S 2000,2100,2000,6900,300,*,UP,ALU1 +S 1900,7000,1900,7000,300,*,LEFT,ALU1 +S -300,7800,16300,7800,6000,*,RIGHT,NWELL +S 0,600,16000,600,1200,vss,RIGHT,CALU1 +S 0,9400,16000,9400,1200,vdd,RIGHT,CALU1 +S 14000,2100,14000,7900,300,q,UP,CALU1 +S 14000,2100,14000,7900,300,*,UP,ALU1 +S 13000,3100,13000,6900,300,i0,UP,CALU1 +S 11000,3100,11000,5900,300,i1,UP,CALU1 +S 8000,3100,8000,5900,300,i2,UP,CALU1 +S 7000,3100,7000,5900,300,i3,UP,CALU1 +S 6000,3100,6000,5900,300,i4,UP,CALU1 +S 5000,3100,5000,5900,300,i5,UP,CALU1 +S 3000,3100,3000,5900,300,i6,UP,CALU1 +S 1000,2100,1000,5900,300,i7,UP,CALU1 +V 800,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 10600,9200,CONT_DIF_P,* +V 13000,9200,CONT_DIF_P,* +V 14000,8000,CONT_DIF_P,* +V 14000,7000,CONT_DIF_P,* +V 14000,6000,CONT_DIF_P,* +V 14000,2000,CONT_DIF_N,* +V 13000,5000,CONT_POLY,* +V 13000,3000,CONT_POLY,* +V 11000,3000,CONT_POLY,* +V 11000,5000,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 15200,900,CONT_DIF_N,* +V 13100,900,CONT_DIF_N,* +V 8600,900,CONT_DIF_N,* +V 4600,900,CONT_DIF_N,* +V 800,900,CONT_DIF_N,* +V 9600,4000,CONT_POLY,* +V 9800,800,CONT_BODY_P,* +V 11000,2000,CONT_DIF_N,* +V 10600,8000,CONT_DIF_P,* +V 11800,8000,CONT_DIF_P,* +V 7800,7000,CONT_DIF_P,* +V 13000,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 6600,7000,CONT_DIF_P,* +V 8000,5000,CONT_POLY,* +V 7000,5000,CONT_POLY,* +V 6000,5000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 1000,5000,CONT_POLY,* +V 3000,8000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,* +V 6600,8000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,* +V 1800,7000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 6600,2000,CONT_DIF_N,* +V 15200,9200,CONT_DIF_P,* +V 15200,8000,CONT_DIF_P,* +V 15200,7000,CONT_DIF_P,* +V 15200,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x4.vbe b/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x4.vbe new file mode 100644 index 000000000..33d168440 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2a2a2a24_x4.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rdown_i7_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT rup_i7_q : NATURAL := 890; + CONSTANT tphh_i7_q : NATURAL := 399; + CONSTANT tphh_i6_q : NATURAL := 487; + CONSTANT tphh_i5_q : NATURAL := 515; + CONSTANT tphh_i4_q : NATURAL := 619; + CONSTANT tphh_i2_q : NATURAL := 726; + CONSTANT tphh_i0_q : NATURAL := 823; + CONSTANT tpll_i1_q : NATURAL := 835; + CONSTANT tpll_i6_q : NATURAL := 845; + CONSTANT tphh_i3_q : NATURAL := 851; + CONSTANT tpll_i0_q : NATURAL := 879; + CONSTANT tpll_i3_q : NATURAL := 895; + CONSTANT tpll_i7_q : NATURAL := 895; + CONSTANT tpll_i4_q : NATURAL := 902; + CONSTANT tpll_i2_q : NATURAL := 940; + CONSTANT tpll_i5_q : NATURAL := 949; + CONSTANT tphh_i1_q : NATURAL := 955; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x4" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1600 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa2ao222_x2.ap b/pdks/symbolic/nsxlib/cells/oa2ao222_x2.ap new file mode 100644 index 000000000..1cb3fbfe2 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2ao222_x2.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H oa2ao222_x2,P,29/ 4/2024,100 +A 0,0,10000,10000 +R 5000,5000,ref_ref,i2_25 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 1000,7000,ref_ref,i0_35 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +R 1000,3000,ref_ref,i0_15 +R 3000,6000,ref_ref,i4_30 +R 3000,5000,ref_ref,i4_25 +R 3000,7000,ref_ref,i4_35 +R 6000,6000,ref_ref,i3_30 +R 6000,5000,ref_ref,i3_25 +R 6000,4000,ref_ref,i3_20 +R 6000,3000,ref_ref,i3_15 +R 5000,6000,ref_ref,i2_30 +R 1000,2000,ref_ref,i0_10 +R 9000,3000,ref_ref,q_15 +R 9000,7000,ref_ref,q_35 +R 9000,2000,ref_ref,q_10 +R 9000,6000,ref_ref,q_30 +R 9000,5000,ref_ref,q_25 +R 9000,4000,ref_ref,q_20 +R 9000,8000,ref_ref,q_40 +R 3000,4000,ref_ref,i4_20 +S 2000,5000,2400,5000,500,*,LEFT,POLY +S 2400,3800,2400,5200,200,*,UP,POLY +S 7800,5200,8200,5200,200,*,LEFT,POLY +S 7800,3900,8500,3900,200,*,RIGHT,POLY +S 7800,4000,7800,5200,200,*,UP,POLY +S 8100,700,9200,700,600,*,RIGHT,PTIE +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 8500,3600,8500,3900,200,*,UP,POLY +S 1600,3600,1600,3900,200,*,UP,POLY +S 1200,4000,1200,5200,200,*,UP,POLY +S 1300,3900,1600,3900,200,*,RIGHT,POLY +S 6200,3700,6200,4100,200,*,UP,POLY +S 4700,3700,4700,4100,200,*,UP,POLY +S 4700,1700,4700,3500,200,*,UP,NTRANS +S 3600,5100,3600,5300,200,*,UP,POLY +S 3200,5100,3600,5100,200,*,RIGHT,POLY +S 3300,3800,3300,4900,200,*,UP,POLY +S 3300,1700,3300,3500,200,*,UP,NTRANS +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 5400,1100,5400,3300,600,*,UP,NDIF +S 6200,1700,6200,3500,200,*,UP,NTRANS +S 1600,1700,1600,3500,200,*,UP,NTRANS +S 3000,5700,3000,9300,400,*,UP,PDIF +S 9000,2100,9000,7900,300,*,UP,ALU1 +S -300,7800,10300,7800,6000,*,RIGHT,NWELL +S 5000,3100,5000,5900,300,*,UP,ALU1 +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,400,*,UP,PDIF +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 5400,5700,5400,9300,400,*,UP,PDIF +S 5800,5500,5800,9500,200,*,UP,PTRANS +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 3000,4100,3000,6900,300,*,UP,ALU1 +S 700,8000,6300,8000,300,*,RIGHT,ALU1 +S 6400,5700,6400,9300,600,*,UP,PDIF +S 1000,2100,1000,6900,300,*,UP,ALU1 +S 4000,1900,4000,3300,600,*,UP,NDIF +S 2300,800,4100,800,600,*,RIGHT,PTIE +S 4000,3100,4000,6900,300,*,UP,ALU1 +S 4100,7000,4100,7000,300,*,LEFT,ALU1 +S 6000,3100,6000,5900,300,*,UP,ALU1 +S 7800,5100,7800,6900,300,*,UP,ALU1 +S 1800,5700,1800,9300,600,*,UP,PDIF +S 4800,4100,4800,5200,200,*,UP,POLY +S 5800,3900,5800,5200,200,*,UP,POLY +S 2400,1700,2400,3500,200,*,UP,NTRANS +S 800,900,800,3300,600,*,UP,NDIF +S 9000,1700,9000,3300,600,*,UP,NDIF +S 8900,5700,8900,9300,600,*,UP,PDIF +S 4300,7000,7700,7000,300,*,RIGHT,ALU1 +S 8200,5500,8200,9500,200,*,UP,PTRANS +S 6900,1900,6900,3300,400,*,UP,NDIF +S 4100,2000,6700,2000,300,*,RIGHT,ALU1 +S 2900,3000,3700,3000,300,*,RIGHT,ALU1 +S 7800,5700,7800,9300,600,*,UP,PDIF +S 7800,8100,7800,9300,300,*,UP,ALU1 +S 8000,1700,8000,3300,600,*,UP,NDIF +S 8100,700,8100,2900,300,*,UP,ALU1 +S 8500,1500,8500,3500,200,*,UP,NTRANS +S 700,5700,700,8200,400,*,UP,PDIF +S 9000,2100,9000,7900,300,q,UP,CALU1 +S 6000,3100,6000,5900,300,i3,UP,CALU1 +S 5000,3100,5000,5900,300,i2,UP,CALU1 +S 3000,4100,3000,6900,300,i4,UP,CALU1 +S 2000,3100,2000,6900,300,i1,UP,CALU1 +S 1000,2100,1000,6900,300,i0,UP,CALU1 +V 7800,4900,CONT_POLY,* +V 4000,800,CONT_BODY_P,* +V 3200,800,CONT_BODY_P,* +V 2400,800,CONT_BODY_P,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 9000,3000,CONT_DIF_N,* +V 9000,2000,CONT_DIF_N,* +V 800,900,CONT_DIF_N,* +V 5400,900,CONT_DIF_N,* +V 2900,3000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 6400,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 4200,7000,CONT_DIF_P,* +V 9200,700,CONT_BODY_P,* +V 8500,700,CONT_BODY_P,* +V 800,8000,CONT_DIF_P,* +V 8100,2000,CONT_DIF_N,* +V 6000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 1800,9200,CONT_DIF_P,* +V 7800,9200,CONT_DIF_P,* +V 6800,2100,CONT_DIF_N,* +V 7800,8000,CONT_DIF_P,* +V 8100,3000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa2ao222_x2.vbe b/pdks/symbolic/nsxlib/cells/oa2ao222_x2.vbe new file mode 100644 index 000000000..2a96b29e2 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2ao222_x2.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT tpll_i4_q : NATURAL := 453; + CONSTANT tphh_i2_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 495; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphh_i3_q : NATURAL := 556; + CONSTANT tphh_i4_q : NATURAL := 558; + CONSTANT tpll_i3_q : NATURAL := 578; + CONSTANT tpll_i0_q : NATURAL := 581; + CONSTANT tphh_i1_q : NATURAL := 598; + CONSTANT tpll_i2_q : NATURAL := 604; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x2; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa2ao222_x4.ap b/pdks/symbolic/nsxlib/cells/oa2ao222_x4.ap new file mode 100644 index 000000000..9a3abaef6 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2ao222_x4.ap @@ -0,0 +1,155 @@ +V ALLIANCE : 6 +H oa2ao222_x4,P,25/ 9/2019,100 +A 0,0,11000,10000 +R 2000,7000,ref_ref,i1_35 +R 1000,7000,ref_ref,i0_35 +R 9000,8000,ref_ref,q_40 +R 9000,4000,ref_ref,q_20 +R 9000,5000,ref_ref,q_25 +R 9000,6000,ref_ref,q_30 +R 9000,2000,ref_ref,q_10 +R 9000,7000,ref_ref,q_35 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 3000,7000,ref_ref,i4_35 +R 3000,6000,ref_ref,i4_30 +R 3000,5000,ref_ref,i4_25 +R 3000,4000,ref_ref,i4_20 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +R 5000,5000,ref_ref,i2_25 +R 5000,6000,ref_ref,i2_30 +R 6000,3000,ref_ref,i3_15 +R 6000,4000,ref_ref,i3_20 +R 6000,5000,ref_ref,i3_25 +R 6000,6000,ref_ref,i3_30 +R 1000,3000,ref_ref,i0_15 +R 9000,3000,ref_ref,q_15 +S 900,3900,1300,3900,400,*,RIGHT,POLY +S 1000,3100,1000,6900,300,i0,UP,CALU1 +S 1000,3100,1000,6900,300,*,UP,ALU1 +S 3000,4100,3000,6900,300,i4,UP,CALU1 +S 2000,3100,2000,6900,300,i1,UP,CALU1 +S 5000,3100,5000,5900,300,i2,UP,CALU1 +S 6000,3100,6000,5900,300,i3,UP,CALU1 +S 600,5700,600,8200,600,*,UP,PDIF +S 5800,5500,5800,9500,200,*,UP,PTRANS +S 2000,3100,2000,6900,300,*,UP,ALU1 +S 3000,4100,3000,6900,300,*,UP,ALU1 +S 700,8000,6300,8000,300,*,RIGHT,ALU1 +S 5200,1100,5200,3300,600,*,UP,NDIF +S 6400,5700,6400,9300,600,*,UP,PDIF +S 2800,1900,2800,3300,600,*,UP,NDIF +S 6400,1900,6400,3300,600,*,UP,NDIF +S 4000,1900,4000,3300,600,*,UP,NDIF +S 7600,4900,8200,4900,600,*,RIGHT,POLY +S 1200,5100,1200,5400,200,*,UP,POLY +S 3600,5100,3600,5400,200,*,UP,POLY +S 4100,2000,6300,2000,300,*,RIGHT,ALU1 +S 5000,3100,5000,5900,300,*,UP,ALU1 +S 4400,3900,4500,3900,200,*,RIGHT,POLY +S 4800,3900,4800,5300,200,*,UP,POLY +S 4600,3900,4800,3900,200,*,RIGHT,POLY +S 2400,1700,2400,3500,200,*,UP,NTRANS +S 9600,5500,9600,9500,200,*,UP,PTRANS +S 10200,5700,10200,9300,600,*,UP,PDIF +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,400,*,UP,PDIF +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 5400,5700,5400,9300,400,*,UP,PDIF +S 2300,800,4100,800,600,*,RIGHT,PTIE +S 2900,2000,2900,2000,300,*,LEFT,ALU1 +S 3100,3000,3900,3000,300,*,RIGHT,ALU1 +S 4000,3100,4000,6900,300,*,UP,ALU1 +S 5800,3900,5800,5200,200,*,UP,POLY +S 4400,3700,4400,3900,200,*,UP,POLY +S 9600,3800,9600,5200,200,*,UP,POLY +S 10200,1700,10200,3300,600,*,UP,NDIF +S 9600,1500,9600,3500,200,*,UP,NTRANS +S 9000,2100,9000,7900,300,*,UP,ALU1 +S -300,7800,11300,7800,6000,*,RIGHT,NWELL +S 4100,7000,4100,7000,300,*,LEFT,ALU1 +S 6000,3100,6000,5900,300,*,UP,ALU1 +S 7800,5100,7800,6900,300,*,UP,ALU1 +S 7600,8100,7600,9300,300,*,UP,ALU1 +S 7600,700,7600,2900,300,*,UP,ALU1 +S 8200,3800,8200,5200,200,*,UP,POLY +S 8800,1700,8800,3300,600,*,UP,NDIF +S 8200,1500,8200,3500,200,*,UP,NTRANS +S 7600,1700,7600,3300,600,*,UP,NDIF +S 7600,5700,7600,9300,600,*,UP,PDIF +S 8200,5500,8200,9500,200,*,UP,PTRANS +S 4300,7000,7700,7000,300,*,RIGHT,ALU1 +S 8800,5700,8800,9300,600,*,UP,PDIF +S 3000,5700,3000,9300,400,*,UP,PDIF +S 1700,1900,1700,3300,200,*,UP,NDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 10000,6100,10000,9300,300,*,UP,ALU1 +S 10000,700,10000,2900,300,*,UP,ALU1 +S 3400,1700,3400,3500,200,*,UP,NTRANS +S 6000,1700,6000,3500,200,*,UP,NTRANS +S 4400,1700,4400,3500,200,*,UP,NTRANS +S 1400,1700,1400,3500,200,*,UP,NTRANS +S 7800,5000,9400,5000,400,*,RIGHT,POLY +S 2900,2200,2900,3000,300,*,UP,ALU1 +S 700,1900,700,3300,400,*,UP,NDIF +S 1000,1000,1000,2000,400,*,UP,ALU1 +S 1800,5700,1800,9300,600,*,UP,PDIF +S 6000,3600,6000,4000,200,*,UP,POLY +S 0,600,11000,600,1200,vss,RIGHT,CALU1 +S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 +S 9000,2000,9000,8000,300,q,UP,CALU1 +S 6100,700,9900,700,600,*,RIGHT,PTIE +S 1200,4200,1200,5100,200,*,UP,POLY +S 1400,3700,1400,4000,200,*,UP,POLY +S 2000,4000,2000,5200,200,*,UP,POLY +S 2000,3800,2400,3800,200,*,LEFT,POLY +S 2000,5200,2400,5200,200,*,LEFT,POLY +S 3000,3800,3400,3800,200,*,LEFT,POLY +S 3000,4000,3000,5100,200,*,UP,POLY +S 3100,5100,3600,5100,200,*,RIGHT,POLY +V 10000,9200,CONT_DIF_P,* +V 1800,9200,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +V 2900,2000,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 7600,9200,CONT_DIF_P,* +V 10000,700,CONT_BODY_P,* +V 8800,700,CONT_BODY_P,* +V 7600,700,CONT_BODY_P,* +V 6400,700,CONT_BODY_P,* +V 7600,8000,CONT_DIF_P,* +V 4000,800,CONT_BODY_P,* +V 3200,800,CONT_BODY_P,* +V 2400,800,CONT_BODY_P,* +V 7600,2000,CONT_DIF_N,* +V 7600,3000,CONT_DIF_N,* +V 5000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 6400,8000,CONT_DIF_P,* +V 600,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 6400,2000,CONT_DIF_N,* +V 4200,7000,CONT_DIF_P,* +V 10000,3000,CONT_DIF_N,* +V 10000,2000,CONT_DIF_N,* +V 10000,8000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,6000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 7800,4900,CONT_POLY,* +V 5200,800,CONT_DIF_N,* +V 9000,2000,CONT_DIF_N,* +V 9000,3000,CONT_DIF_N,* +V 9000,6000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa2ao222_x4.vbe b/pdks/symbolic/nsxlib/cells/oa2ao222_x4.vbe new file mode 100644 index 000000000..d8e7b2abf --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT tpll_i4_q : NATURAL := 529; + CONSTANT tphh_i2_q : NATURAL := 552; + CONSTANT tphh_i0_q : NATURAL := 553; + CONSTANT tpll_i1_q : NATURAL := 616; + CONSTANT tphh_i3_q : NATURAL := 640; + CONSTANT tphh_i4_q : NATURAL := 656; + CONSTANT tpll_i0_q : NATURAL := 657; + CONSTANT tpll_i3_q : NATURAL := 660; + CONSTANT tphh_i1_q : NATURAL := 662; + CONSTANT tpll_i2_q : NATURAL := 693; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa3ao322_x2.ap b/pdks/symbolic/nsxlib/cells/oa3ao322_x2.ap new file mode 100644 index 000000000..0cc8b769f --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa3ao322_x2.ap @@ -0,0 +1,151 @@ +V ALLIANCE : 6 +H oa3ao322_x2,P,29/ 4/2024,100 +A 0,0,11000,10000 +R 9000,7000,ref_ref,i4_35 +R 10000,3000,ref_ref,i5_15 +R 5000,4000,ref_ref,i2_20 +R 4000,7000,ref_ref,i1_35 +R 4000,6000,ref_ref,i1_30 +R 4000,5000,ref_ref,i1_25 +R 4000,4000,ref_ref,i1_20 +R 4000,3000,ref_ref,i1_15 +R 6000,7000,ref_ref,i6_35 +R 6000,6000,ref_ref,i6_30 +R 6000,5000,ref_ref,i6_25 +R 10000,6000,ref_ref,i5_30 +R 10000,5000,ref_ref,i5_25 +R 1000,7000,ref_ref,q_35 +R 1000,6000,ref_ref,q_30 +R 6000,4000,ref_ref,i6_20 +R 5000,7000,ref_ref,i2_35 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +R 8000,5000,ref_ref,i3_25 +R 8000,4000,ref_ref,i3_20 +R 8000,3000,ref_ref,i3_15 +R 10000,4000,ref_ref,i5_20 +R 8000,7000,ref_ref,i3_35 +R 3000,7000,ref_ref,i0_35 +R 1000,8000,ref_ref,q_40 +R 1000,2000,ref_ref,q_10 +R 1000,3000,ref_ref,q_15 +R 1000,4000,ref_ref,q_20 +R 1000,5000,ref_ref,q_25 +R 10000,7000,ref_ref,i5_35 +R 3000,3000,ref_ref,i0_15 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 8000,6000,ref_ref,i3_30 +R 9000,3000,ref_ref,i4_15 +R 9000,4000,ref_ref,i4_20 +R 9000,5000,ref_ref,i4_25 +R 9000,6000,ref_ref,i4_30 +S 7000,5700,7000,8300,600,*,UP,PDIF +S 1000,2100,1000,7900,300,q,UP,CALU1 +S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,11000,600,1200,vss,RIGHT,CALU1 +S 5300,3900,5300,6000,200,i2,UP,POLY +S 8800,4900,8800,5200,200,i4,UP,POLY +S 9800,3800,9800,5200,200,i5,UP,POLY +S 6200,3800,6200,5800,200,i6,UP,POLY +S 5600,1900,5600,2700,400,*,UP,NDIF +S 6200,3200,6200,3800,200,*,UP,POLY +S 5800,6300,5800,8300,400,*,UP,PDIF +S 5000,1700,5000,3300,200,*,UP,NTRANS +S -300,7800,11300,7800,6000,*,RIGHT,NWELL +S 5000,3600,5000,4000,200,*,UP,POLY +S 9800,2800,9800,4000,200,*,UP,POLY +S 2100,1700,2100,3300,200,*,UP,NDIF +S 5300,6100,5300,8500,200,*,UP,PTRANS +S 7300,3100,7300,3800,200,*,UP,POLY +S 9800,5500,9800,8500,200,*,UP,PTRANS +S 6200,1700,6200,2900,200,*,UP,NTRANS +S 3500,1900,3500,3100,200,*,UP,NDIF +S 4500,1900,4500,3100,200,*,UP,NDIF +S 8300,5700,8300,8300,200,*,UP,PDIF +S 9300,5700,9300,8300,200,*,UP,PDIF +S 7400,5700,7400,5900,200,*,UP,PDIF +S 2300,5700,2300,9300,400,*,UP,PDIF +S 3200,3600,3200,4100,200,*,UP,POLY +S 3000,3100,3000,6900,300,*,UP,ALU1 +S 4000,3100,4000,6900,300,*,UP,ALU1 +S 9000,3100,9000,6900,300,*,UP,ALU1 +S 6000,4100,6000,6900,300,*,UP,ALU1 +S 10000,3100,10000,6900,300,*,UP,ALU1 +S 5000,4100,5000,6900,300,*,UP,ALU1 +S 5600,2100,5600,2900,300,*,UP,ALU1 +S 5700,3000,6900,3000,300,*,RIGHT,ALU1 +S 2100,2000,5500,2000,300,*,RIGHT,ALU1 +S 7800,5500,7800,8500,200,*,UP,PTRANS +S 8800,5500,8800,8500,200,*,UP,PTRANS +S 7000,3100,7000,6900,300,*,UP,ALU1 +S 8000,3100,8000,6900,300,*,UP,ALU1 +S 6900,2000,9100,2000,300,*,RIGHT,ALU1 +S 2000,2100,2000,3900,300,*,UP,ALU1 +S 2200,8100,2200,9300,300,*,UP,ALU1 +S 1000,2100,1000,7900,300,*,UP,ALU1 +S 9800,1700,9800,2500,200,*,UP,NTRANS +S 6800,1900,6800,2700,400,*,UP,NDIF +S 3000,4100,3000,6000,200,*,UP,POLY +S 2400,1100,2400,3300,600,*,UP,NDIF +S 1600,1500,1600,3500,200,*,UP,NTRANS +S 1000,1700,1000,3300,600,*,UP,NDIF +S 1000,5700,1000,9300,600,*,UP,PDIF +S 1600,5500,1600,9500,200,*,UP,PTRANS +S 7400,3800,7800,3800,200,*,RIGHT,POLY +S 7800,3800,7800,5200,200,*,UP,POLY +S 10200,700,10200,1900,300,*,UP,ALU1 +S 10300,1900,10300,2300,400,*,UP,NDIF +S 8900,1700,8900,2500,200,*,UP,NTRANS +S 9200,1900,9200,2300,400,*,UP,NDIF +S 8100,900,8100,2300,600,*,UP,NDIF +S 7300,1700,7300,2900,200,*,UP,NTRANS +S 8900,2800,8900,4700,200,*,UP,POLY +S 3200,1700,3200,3300,200,*,UP,NTRANS +S 4100,1700,4100,3300,200,*,UP,NTRANS +S 6200,6100,6200,8500,200,*,UP,PTRANS +S 4100,3600,4100,4000,200,*,UP,POLY +S 3500,8000,10200,8000,300,*,RIGHT,ALU1 +S 10300,5700,10300,8300,400,*,UP,PDIF +S 4600,6500,4600,8900,400,*,UP,PDIF +S 3900,6300,3900,8500,200,*,UP,PTRANS +S 3000,6300,3000,8500,200,*,UP,PTRANS +S 3400,6500,3400,8300,400,*,UP,PDIF +S 3900,3800,3900,6000,200,*,UP,POLY +S 10000,3100,10000,6900,300,i5,UP,CALU1 +S 9000,3100,9000,6900,300,i4,UP,CALU1 +S 8000,3100,8000,6900,300,i3,UP,CALU1 +S 6000,4100,6000,6900,300,i6,UP,CALU1 +S 5000,4100,5000,6900,300,i2,UP,CALU1 +S 4000,3100,4000,6900,300,i1,UP,CALU1 +S 3000,3100,3000,6900,300,i0,UP,CALU1 +S 2000,3800,2000,5200,200,*,UP,POLY +S 1600,5200,2000,5200,200,*,RIGHT,POLY +S 1600,3800,2000,3800,200,*,RIGHT,POLY +V 1000,8000,CONT_DIF_P,* +V 2200,8000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 10200,2000,CONT_DIF_N,* +V 10200,8000,CONT_DIF_P,* +V 4600,9200,CONT_DIF_P,* +V 3000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 5800,8000,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 6800,2000,CONT_DIF_N,* +V 2000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 10000,4000,CONT_POLY,* +V 9000,5000,CONT_POLY,* +V 8000,5000,CONT_POLY,* +V 5600,2000,CONT_DIF_N,* +V 1000,3000,CONT_DIF_N,* +V 7000,7000,CONT_DIF_P,* +V 7000,6000,CONT_DIF_P,* +V 1000,6000,CONT_DIF_P,* +V 9300,2000,CONT_DIF_N,* +V 2400,900,CONT_DIF_N,* +V 8100,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa3ao322_x2.vbe b/pdks/symbolic/nsxlib/cells/oa3ao322_x2.vbe new file mode 100644 index 000000000..dc2a71887 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa3ao322_x2.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT tpll_i6_q : NATURAL := 540; + CONSTANT tphh_i3_q : NATURAL := 560; + CONSTANT tphh_i6_q : NATURAL := 563; + CONSTANT tphh_i0_q : NATURAL := 638; + CONSTANT tphh_i4_q : NATURAL := 649; + CONSTANT tpll_i2_q : NATURAL := 707; + CONSTANT tphh_i5_q : NATURAL := 734; + CONSTANT tpll_i5_q : NATURAL := 734; + CONSTANT tphh_i1_q : NATURAL := 735; + CONSTANT tpll_i4_q : NATURAL := 760; + CONSTANT tpll_i1_q : NATURAL := 764; + CONSTANT tpll_i3_q : NATURAL := 765; + CONSTANT tphh_i2_q : NATURAL := 806; + CONSTANT tpll_i0_q : NATURAL := 820; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x2; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/oa3ao322_x4.ap b/pdks/symbolic/nsxlib/cells/oa3ao322_x4.ap new file mode 100644 index 000000000..0aa9c9d8c --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa3ao322_x4.ap @@ -0,0 +1,168 @@ +V ALLIANCE : 6 +H oa3ao322_x4,P,25/ 9/2019,100 +A 0,0,12000,10000 +R 11000,7000,ref_ref,i5_35 +R 11000,6000,ref_ref,i5_30 +R 5000,6000,ref_ref,i1_30 +R 5000,5000,ref_ref,i1_25 +R 5000,4000,ref_ref,i1_20 +R 5000,3000,ref_ref,i1_15 +R 7000,7000,ref_ref,i6_35 +R 6000,6000,ref_ref,i2_30 +R 6000,7000,ref_ref,i2_35 +R 7000,4000,ref_ref,i6_20 +R 2000,2000,ref_ref,q_10 +R 2000,8000,ref_ref,q_40 +R 4000,7000,ref_ref,i0_35 +R 9000,7000,ref_ref,i3_35 +R 10000,7000,ref_ref,i4_35 +R 10000,6000,ref_ref,i4_30 +R 10000,5000,ref_ref,i4_25 +R 10000,4000,ref_ref,i4_20 +R 10000,3000,ref_ref,i4_15 +R 7000,6000,ref_ref,i6_30 +R 7000,5000,ref_ref,i6_25 +R 4000,3000,ref_ref,i0_15 +R 4000,4000,ref_ref,i0_20 +R 4000,5000,ref_ref,i0_25 +R 4000,6000,ref_ref,i0_30 +R 9000,6000,ref_ref,i3_30 +R 2000,6000,ref_ref,q_30 +R 2000,5000,ref_ref,q_25 +R 2000,4000,ref_ref,q_20 +R 2000,3000,ref_ref,q_15 +R 11000,5000,ref_ref,i5_25 +R 9000,3000,ref_ref,i3_15 +R 11000,4000,ref_ref,i5_20 +R 11000,3000,ref_ref,i5_15 +R 6000,5000,ref_ref,i2_25 +R 9000,5000,ref_ref,i3_25 +R 9000,4000,ref_ref,i3_20 +R 6000,4000,ref_ref,i2_20 +R 2000,7000,ref_ref,q_35 +R 5000,7000,ref_ref,i1_35 +S 7200,5200,7400,5200,200,*,LEFT,POLY +S 6000,5200,6400,5200,200,*,LEFT,POLY +S 7200,4000,7200,5100,200,i6,UP,POLY +S 6000,3900,6000,5200,200,i2,UP,POLY +S 3200,2100,3200,3900,300,*,UP,ALU1 +S 10300,800,11100,800,600,*,RIGHT,PTIE +S 4800,3900,4800,6000,200,*,UP,POLY +S 3900,3900,3900,6000,200,*,UP,POLY +S 4200,3600,4200,4100,200,*,UP,POLY +S 900,5700,900,9300,600,*,UP,PDIF +S 1000,6100,1000,8900,300,*,UP,ALU1 +S 6400,5500,6400,8500,200,*,UP,PTRANS +S 4800,5500,4800,8500,200,*,UP,PTRANS +S 3900,5500,3900,8500,200,*,UP,PTRANS +S 7400,5500,7400,8500,200,*,UP,PTRANS +S 900,1700,900,3300,400,*,UP,NDIF +S 1000,900,1000,2900,300,*,UP,ALU1 +S 5100,3600,5100,4000,200,*,UP,POLY +S 5100,1700,5100,3300,200,*,UP,NTRANS +S 4200,1700,4200,3300,200,*,UP,NTRANS +S 8200,1700,8200,2900,200,*,UP,NTRANS +S 9800,2800,9800,3800,200,*,UP,POLY +S 9800,1700,9800,2500,200,*,UP,NTRANS +S 11300,1900,11300,2300,400,*,UP,NDIF +S 11200,700,11200,1900,300,*,UP,ALU1 +S 4500,8000,11200,8000,300,*,RIGHT,ALU1 +S 11300,5700,11300,8300,400,*,UP,PDIF +S 3200,5700,3200,9300,400,*,UP,PDIF +S 8000,5700,8000,8300,600,*,UP,PDIF +S 4000,3100,4000,6900,300,*,UP,ALU1 +S 5000,3100,5000,6900,300,*,UP,ALU1 +S 10000,3100,10000,6900,300,*,UP,ALU1 +S 7000,4100,7000,6900,300,*,UP,ALU1 +S 11000,3100,11000,6900,300,*,UP,ALU1 +S 7900,2000,10100,2000,300,*,RIGHT,ALU1 +S 9000,3100,9000,6900,300,*,UP,ALU1 +S 8000,3100,8000,6900,300,*,UP,ALU1 +S 3100,2000,6500,2000,300,*,RIGHT,ALU1 +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 3200,8100,3200,9300,300,*,UP,ALU1 +S 6700,3000,7900,3000,300,*,RIGHT,ALU1 +S 1400,1500,1400,3500,200,*,UP,NTRANS +S 2600,5500,2600,9500,200,*,UP,PTRANS +S 2000,5700,2000,9300,600,*,UP,PDIF +S 4400,6500,4400,8300,600,*,UP,PDIF +S 8800,5500,8800,8500,200,*,UP,PTRANS +S 6800,6300,6800,8300,400,*,UP,PDIF +S 10800,5500,10800,8500,200,*,UP,PTRANS +S 9800,5500,9800,8500,200,*,UP,PTRANS +S 1400,5500,1400,9500,200,*,UP,PTRANS +S -300,7800,12300,7800,6000,*,RIGHT,NWELL +S 5600,5700,5600,9200,600,*,UP,PDIF +S 8200,3100,8200,3800,200,*,UP,POLY +S 1400,4000,3000,4000,400,*,RIGHT,POLY +S 8400,5700,8400,8300,200,*,UP,PDIF +S 9300,5700,9300,8300,200,*,UP,PDIF +S 10300,5700,10300,8300,200,*,UP,PDIF +S 5500,1900,5500,3100,200,*,UP,NDIF +S 4500,1900,4500,3100,200,*,UP,NDIF +S 3000,1700,3000,3300,200,*,UP,NDIF +S 10800,1700,10800,2500,200,*,UP,NTRANS +S 6600,1900,6600,2700,400,*,UP,NDIF +S 2600,1500,2600,3500,200,*,UP,NTRANS +S 2000,1700,2000,3300,600,*,UP,NDIF +S 6000,1700,6000,3300,200,*,UP,NTRANS +S 7800,1900,7800,2700,400,*,UP,NDIF +S 3400,1100,3400,3300,600,*,UP,NDIF +S 7200,1700,7200,2900,200,*,UP,NTRANS +S 9000,900,9000,2300,600,*,UP,NDIF +S 10200,1900,10200,2300,600,*,UP,NDIF +S 1400,3800,1400,5200,200,*,UP,POLY +S 7200,3200,7200,3800,200,*,UP,POLY +S 6000,3600,6000,4000,200,*,UP,POLY +S 8400,3800,8800,3800,200,*,RIGHT,POLY +S 8800,3800,8800,5200,200,*,UP,POLY +S 10800,2800,10800,4000,200,*,UP,POLY +S 2600,3800,2600,5200,200,*,UP,POLY +S 6000,4100,6000,6900,300,*,UP,ALU1 +S 6600,2100,6600,2900,300,*,UP,ALU1 +S 10800,3800,10800,5200,200,i5,UP,POLY +S 9800,3800,9800,5200,200,i4,UP,POLY +S 0,600,12000,600,1200,vss,RIGHT,CALU1 +S 0,9300,12000,9300,1200,vdd,RIGHT,CALU1 +S 6000,4000,6000,6900,300,i2,UP,CALU1 +S 7000,4000,7000,6900,300,i6,UP,CALU1 +S 11000,3100,11000,6900,300,i5,UP,CALU1 +S 10000,3100,10000,6900,300,i4,UP,CALU1 +S 9000,3100,9000,6900,300,i3,UP,CALU1 +S 5000,3100,5000,6900,300,i1,UP,CALU1 +S 4000,3100,4000,6900,300,i0,UP,CALU1 +S 2000,2100,2000,7900,300,q,UP,CALU1 +V 3200,4000,CONT_POLY,* +V 1000,9200,CONT_DIF_P,* +V 4400,8000,CONT_DIF_P,* +V 3400,900,CONT_DIF_N,* +V 5600,9300,CONT_DIF_P,* +V 6000,4000,CONT_POLY,* +V 2000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 3200,8000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 6800,8000,CONT_DIF_P,* +V 7800,2000,CONT_DIF_N,* +V 6600,2000,CONT_DIF_N,* +V 2000,3000,CONT_DIF_N,* +V 10200,2000,CONT_DIF_N,* +V 10400,800,CONT_BODY_P,* +V 11200,800,CONT_BODY_P,* +V 5000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 9000,5000,CONT_POLY,* +V 11000,4000,CONT_POLY,* +V 10000,5000,CONT_POLY,* +V 7000,4000,CONT_POLY,* +V 1000,2000,CONT_DIF_N,* +V 1000,3000,CONT_DIF_N,* +V 11200,2000,CONT_DIF_N,* +V 11200,8000,CONT_DIF_P,* +V 9000,800,CONT_DIF_N,* +V 1000,6000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/oa3ao322_x4.vbe b/pdks/symbolic/nsxlib/cells/oa3ao322_x4.vbe new file mode 100644 index 000000000..6f1ad9762 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/oa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT tpll_i6_q : NATURAL := 651; + CONSTANT tphh_i3_q : NATURAL := 673; + CONSTANT tphh_i6_q : NATURAL := 684; + CONSTANT tphh_i0_q : NATURAL := 717; + CONSTANT tphh_i4_q : NATURAL := 758; + CONSTANT tphh_i1_q : NATURAL := 818; + CONSTANT tpll_i2_q : NATURAL := 834; + CONSTANT tphh_i5_q : NATURAL := 839; + CONSTANT tpll_i5_q : NATURAL := 865; + CONSTANT tpll_i1_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 894; + CONSTANT tpll_i4_q : NATURAL := 896; + CONSTANT tpll_i3_q : NATURAL := 898; + CONSTANT tpll_i0_q : NATURAL := 946; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1500 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/on12_x1.ap b/pdks/symbolic/nsxlib/cells/on12_x1.ap new file mode 100644 index 000000000..5a50c4665 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/on12_x1.ap @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H on12_x1,P,25/ 9/2019,100 +A 0,0,5000,10000 +R 3000,4000,ref_ref,q_20 +R 3000,3000,ref_ref,q_15 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 4000,3000,ref_ref,i0_15 +R 4000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,q_25 +R 3000,6000,ref_ref,q_30 +R 4000,7000,ref_ref,i0_35 +R 4000,6000,ref_ref,i0_30 +R 4000,5000,ref_ref,i0_25 +R 4000,8000,ref_ref,i0_40 +R 3000,8000,ref_ref,q_40 +R 3000,7000,ref_ref,q_35 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 3000,2000,ref_ref,q_10 +S 3500,6200,4000,6200,200,*,RIGHT,POLY +S 3500,3800,4000,3800,200,*,RIGHT,POLY +S 4000,3800,4000,6200,200,*,UP,POLY +S 700,900,700,1700,600,*,UP,PTIE +S 2800,700,4100,700,600,*,RIGHT,PTIE +S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,5000,600,1200,vss,RIGHT,CALU1 +S 2000,1100,2000,2000,400,*,UP,ALU1 +S 1900,1700,1900,3300,400,*,UP,NDIF +S 900,5000,2400,5000,200,*,RIGHT,POLY +S 1200,3700,1200,3900,200,*,UP,POLY +S 1200,6200,1200,6300,200,*,UP,POLY +S 2600,3800,2600,6200,200,*,UP,POLY +S 700,2700,700,3300,400,*,UP,NDIF +S 1200,6000,1900,6000,400,*,RIGHT,POLY +S 4000,3100,4000,7900,300,*,UP,ALU1 +S 3100,2000,3700,2000,300,*,RIGHT,ALU1 +S 1200,2500,1200,3500,200,*,UP,NTRANS +S 3000,6700,3000,8300,600,*,UP,PDIF +S -300,7800,5300,7800,6000,*,RIGHT,NWELL +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 3800,1700,3800,3300,400,*,UP,NDIF +S 3500,1500,3500,3500,200,*,UP,NTRANS +S 2600,1500,2600,3500,200,*,UP,NTRANS +S 700,6700,700,8300,400,*,UP,PDIF +S 800,3100,800,7900,300,*,UP,ALU1 +S 1900,6700,1900,9100,400,*,UP,PDIF +S 3500,6500,3500,8500,200,*,UP,PTRANS +S 4200,6700,4200,9100,400,*,UP,PDIF +S 2600,6500,2600,8500,200,*,UP,PTRANS +S 1200,4000,1900,4000,400,*,RIGHT,POLY +S 2000,3100,2000,7900,300,*,UP,ALU1 +S 2000,3100,2000,7900,300,i1,UP,CALU1 +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 3000,2100,3000,7900,300,q,UP,CALU1 +S 4000,3100,4000,7900,300,i0,UP,CALU1 +V 3900,2000,CONT_DIF_N,* +V 800,3000,CONT_DIF_N,* +V 800,5000,CONT_POLY,* +V 2000,2000,CONT_DIF_N,* +V 2000,6000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 700,800,CONT_BODY_P,* +V 4200,700,CONT_BODY_P,* +V 4200,9200,CONT_DIF_P,* +V 1900,9200,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 3100,700,CONT_BODY_P,* +V 4000,4000,CONT_POLY,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/on12_x1.vbe b/pdks/symbolic/nsxlib/cells/on12_x1.vbe new file mode 100644 index 000000000..32688f423 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/on12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3720; + CONSTANT rup_i1_q : NATURAL := 3720; + CONSTANT tphl_i0_q : NATURAL := 111; + CONSTANT tplh_i0_q : NATURAL := 234; + CONSTANT tpll_i1_q : NATURAL := 291; + CONSTANT tphh_i1_q : NATURAL := 314; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x1; + +ARCHITECTURE behaviour_data_flow OF on12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x1" + SEVERITY WARNING; + q <= (not (i0) or i1) after 900 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/on12_x4.ap b/pdks/symbolic/nsxlib/cells/on12_x4.ap new file mode 100644 index 000000000..fa5b25fa1 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/on12_x4.ap @@ -0,0 +1,98 @@ +V ALLIANCE : 6 +H on12_x4,P,18/ 9/2019,100 +A 0,0,8000,10000 +R 2000,6000,ref_ref,i0_30 +R 2000,8000,ref_ref,i0_40 +R 2000,2000,ref_ref,i0_10 +R 6000,5000,ref_ref,q_25 +R 6000,4000,ref_ref,q_20 +R 6000,3000,ref_ref,q_15 +R 5000,4000,ref_ref,i1_20 +R 5000,2000,ref_ref,i1_10 +R 5000,8000,ref_ref,i1_40 +R 5000,7000,ref_ref,i1_35 +R 5000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i0_35 +R 2000,3000,ref_ref,i0_15 +R 2000,4000,ref_ref,i0_20 +R 2000,5000,ref_ref,i0_25 +S 2000,2100,2000,7900,300,i0,UP,CALU1 +S 5000,2100,5000,7900,300,i1,UP,CALU1 +S 6000,2100,6000,7900,300,q,UP,CALU1 +S 6000,2100,6000,7900,300,*,UP,ALU1 +S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,8000,600,1200,vss,RIGHT,CALU1 +S 3800,800,3800,2300,600,*,UP,NDIF +S 1200,2800,1200,3000,200,*,UP,POLY +S 1200,6900,1200,7200,200,*,UP,POLY +S 7300,5700,7300,9300,400,*,UP,PDIF +S 3000,5700,3000,8300,400,*,UP,PDIF +S 4300,5500,4300,8500,200,*,UP,PTRANS +S 5000,5700,5000,9300,400,*,UP,PDIF +S 3400,5500,3400,8500,200,*,UP,PTRANS +S 7200,1100,7200,1900,300,*,UP,ALU1 +S 1200,7500,1200,9500,200,*,UP,PTRANS +S 1800,7700,1800,9300,600,*,UP,PDIF +S 2000,2100,2000,7900,300,*,UP,ALU1 +S -300,7800,8300,7800,6000,*,RIGHT,NWELL +S 4400,3000,5000,3000,400,*,RIGHT,POLY +S 4300,5000,4900,5000,400,*,RIGHT,POLY +S 4400,2700,4400,2900,200,*,UP,POLY +S 4300,5000,4300,5300,200,*,UP,POLY +S 4000,4000,6800,4000,400,*,RIGHT,POLY +S 700,4000,3200,4000,400,*,RIGHT,POLY +S 6800,5500,6800,9500,200,*,UP,PTRANS +S 6200,5700,6200,9300,600,*,UP,PDIF +S 5600,5500,5600,9500,200,*,UP,PTRANS +S 3400,5100,3400,5400,200,*,UP,POLY +S 5600,600,5600,2500,200,*,UP,NTRANS +S 3200,5100,3400,5100,200,*,RIGHT,POLY +S 1200,3000,1900,3000,400,*,RIGHT,POLY +S 1200,7000,1900,7000,400,*,RIGHT,POLY +S 1200,600,1200,2500,200,*,UP,NTRANS +S 2200,800,2200,2300,1400,*,UP,NDIF +S 3200,600,3200,2500,200,*,UP,NTRANS +S 4400,600,4400,2500,200,*,UP,NTRANS +S 5000,800,5000,2300,600,*,UP,NDIF +S 6200,800,6200,2300,600,*,UP,NDIF +S 700,1700,700,2300,400,*,UP,NDIF +S 7200,6100,7200,8900,300,*,UP,ALU1 +S 3200,2800,3200,5100,200,*,UP,POLY +S 6800,2800,6800,5200,200,*,UP,POLY +S 5600,2800,5600,5200,200,*,UP,POLY +S 5000,2100,5000,7900,300,*,UP,ALU1 +S 3100,5800,3700,5800,300,*,RIGHT,ALU1 +S 3800,2100,3800,5700,300,*,UP,ALU1 +S 3000,5900,3000,7900,300,*,UP,ALU1 +S 6800,600,6800,2500,200,*,UP,NTRANS +S 7300,800,7300,2300,400,*,UP,NDIF +S 800,2100,800,7900,300,*,UP,ALU1 +S 700,7700,700,9300,400,*,UP,PDIF +V 5000,3000,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 2000,7000,CONT_POLY,* +V 7200,900,CONT_DIF_N,* +V 5000,900,CONT_DIF_N,* +V 2700,900,CONT_DIF_N,* +V 1800,900,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 3800,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 6000,2000,CONT_DIF_N,* +V 7200,2000,CONT_DIF_N,* +V 5200,9200,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 800,4000,CONT_POLY,* +V 800,8000,CONT_DIF_P,* +V 7200,9200,CONT_DIF_P,* +V 7200,8000,CONT_DIF_P,* +V 7200,7000,CONT_DIF_P,* +V 7200,6000,CONT_DIF_P,* +V 1800,9200,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/on12_x4.vbe b/pdks/symbolic/nsxlib/cells/on12_x4.vbe new file mode 100644 index 000000000..c5f990c6c --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/on12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 394; + CONSTANT tphl_i0_q : NATURAL := 474; + CONSTANT tphh_i1_q : NATURAL := 491; + CONSTANT tplh_i0_q : NATURAL := 499; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x4; + +ARCHITECTURE behaviour_data_flow OF on12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x4" + SEVERITY WARNING; + q <= (not (i0) or i1) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/one_x0.ap b/pdks/symbolic/nsxlib/cells/one_x0.ap new file mode 100644 index 000000000..2858ab3f3 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/one_x0.ap @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H one_x0,P,25/ 9/2019,100 +A 0,0,3000,10000 +R 2000,2000,ref_ref,q_10 +R 2000,3000,ref_ref,q_15 +R 2000,4000,ref_ref,q_20 +R 2000,5000,ref_ref,q_25 +R 2000,6000,ref_ref,q_30 +R 2000,7000,ref_ref,q_35 +R 2000,8000,ref_ref,q_40 +S 1000,5100,1400,5100,400,*,RIGHT,POLY +S 1400,5000,1400,5200,200,*,UP,POLY +S 1000,700,1000,4900,300,*,UP,ALU1 +S 800,6100,800,9300,300,*,UP,ALU1 +S 700,5700,700,7300,800,*,UP,PDIF +S -300,7800,3300,7800,6000,*,RIGHT,NWELL +S 1400,5500,1400,7500,200,*,UP,PTRANS +S 2000,5700,2000,7300,600,*,UP,PDIF +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 700,9100,2300,9100,600,*,RIGHT,NTIE +S 900,1000,2100,1000,600,*,RIGHT,PTIE +S 1000,900,1000,3100,600,*,UP,PTIE +S 1000,1200,2000,1200,400,*,RIGHT,ALU1 +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 2000,2100,2000,7900,300,q,UP,CALU1 +V 2000,7000,CONT_DIF_P,* +V 2000,6000,CONT_DIF_P,* +V 1000,9200,CONT_BODY_N,* +V 1000,5000,CONT_POLY,* +V 800,6000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 2000,9200,CONT_BODY_N,* +V 1000,3000,CONT_BODY_P,* +V 1000,2000,CONT_BODY_P,* +V 2000,1000,CONT_BODY_P,* +V 1000,1000,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/one_x0.vbe b/pdks/symbolic/nsxlib/cells/one_x0.vbe new file mode 100644 index 000000000..e7439c597 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/one_x0.vbe @@ -0,0 +1,20 @@ +ENTITY one_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END one_x0; + +ARCHITECTURE behaviour_data_flow OF one_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on one_x0" + SEVERITY WARNING; + q <= '1'; +END; diff --git a/pdks/symbolic/nsxlib/cells/powmid_x0.ap b/pdks/symbolic/nsxlib/cells/powmid_x0.ap new file mode 100644 index 000000000..8013d349d --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/powmid_x0.ap @@ -0,0 +1,10 @@ +V ALLIANCE : 6 +H powmid_x0,P,15/8/2019,100 +A 0,0,7000,10000 +S 1000,10000,3000,10000,300,*,RIGHT,ALU1 +S 4000,0,6000,0,300,*,RIGHT,ALU1 +S 5000,0,5000,10000,2400,vss,UP,CALU3 +S 0,600,7000,600,1200,vss,RIGHT,CALU1 +S 2000,0,2000,10000,2400,vdd,UP,CALU3 +S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 +EOF diff --git a/pdks/symbolic/nsxlib/cells/powmid_x0.vbe b/pdks/symbolic/nsxlib/cells/powmid_x0.vbe new file mode 100644 index 000000000..52f4c8149 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/powmid_x0.vbe @@ -0,0 +1,18 @@ +ENTITY powmid_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END powmid_x0; + +ARCHITECTURE behaviour_data_flow OF powmid_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on powmid_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/nsxlib/cells/rowend_x0.ap b/pdks/symbolic/nsxlib/cells/rowend_x0.ap new file mode 100644 index 000000000..7d5f8da4c --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/rowend_x0.ap @@ -0,0 +1,7 @@ +V ALLIANCE : 6 +H rowend_x0,P,15/8/2019,100 +A 0,0,1000,10000 +S -300,7800,1300,7800,6000,*,RIGHT,NWELL +S 0,600,1000,600,1200,vss,RIGHT,CALU1 +S 0,9400,1000,9400,1200,vdd,RIGHT,CALU1 +EOF diff --git a/pdks/symbolic/nsxlib/cells/rowend_x0.vbe b/pdks/symbolic/nsxlib/cells/rowend_x0.vbe new file mode 100644 index 000000000..dfe3de719 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/rowend_x0.vbe @@ -0,0 +1,18 @@ +ENTITY rowend_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 250; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END rowend_x0; + +ARCHITECTURE behaviour_data_flow OF rowend_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rowend_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/nsxlib/cells/sff1_x4.ap b/pdks/symbolic/nsxlib/cells/sff1_x4.ap new file mode 100644 index 000000000..259255bf3 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/sff1_x4.ap @@ -0,0 +1,231 @@ +V ALLIANCE : 6 +H sff1_x4,P,25/ 9/2019,100 +A 0,0,18000,10000 +R 16000,7000,ref_ref,q_35 +R 16000,6000,ref_ref,q_30 +R 16000,5000,ref_ref,q_25 +R 16000,3000,ref_ref,q_15 +R 16000,2000,ref_ref,q_10 +R 6000,8000,ref_ref,i_40 +R 5000,5000,ref_ref,i_25 +R 5000,6000,ref_ref,i_30 +R 5000,7000,ref_ref,i_35 +R 2000,2000,ref_ref,ck_10 +R 2000,3000,ref_ref,ck_15 +R 2000,4000,ref_ref,ck_20 +R 2000,5000,ref_ref,ck_25 +R 2000,6000,ref_ref,ck_30 +R 2000,7000,ref_ref,ck_35 +R 2000,8000,ref_ref,ck_40 +R 16000,4000,ref_ref,q_20 +R 5000,4000,ref_ref,i_20 +R 5000,3000,ref_ref,i_15 +R 6000,2000,ref_ref,i_10 +R 16000,8000,ref_ref,q_40 +S 7500,6200,7500,6300,200,*,UP,POLY +S 7000,6200,7500,6200,200,*,RIGHT,POLY +S 0,9400,18000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,18000,600,1200,vss,RIGHT,CALU1 +S 14800,4000,16800,4000,200,sff_s,RIGHT,POLY +S 9000,2100,9000,6900,300,sff_m,UP,ALU1 +S 6000,3100,6000,5900,300,u,UP,ALU1 +S 3200,4000,12000,4000,200,ckr,RIGHT,POLY +S 6800,6700,6800,9300,400,*,UP,PDIF +S 2600,6500,2600,8500,200,*,UP,PTRANS +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 800,7100,800,7900,300,*,UP,ALU1 +S 800,2100,800,6900,300,*,UP,ALU1 +S 700,6700,700,8300,400,*,UP,PDIF +S 1900,6700,1900,9100,400,*,UP,PDIF +S 3000,6700,3000,8300,400,*,UP,PDIF +S 7200,2700,7200,3000,200,*,UP,POLY +S 1200,2700,1200,2900,200,*,UP,POLY +S 1200,6100,1200,6400,200,*,UP,POLY +S 13200,7100,13200,7300,200,*,UP,POLY +S 14200,5100,14600,5100,200,*,RIGHT,POLY +S 14200,2900,14500,2900,200,*,RIGHT,POLY +S 10400,2900,10800,2900,200,*,RIGHT,POLY +S 6200,2700,6200,3000,200,*,UP,POLY +S 7200,2600,7200,3000,200,*,UP,POLY +S 15100,6100,15100,8900,300,*,UP,ALU1 +S 9100,6700,9100,9300,400,*,UP,PDIF +S 10200,7700,10200,9300,400,*,UP,PDIF +S 9800,7500,9800,9500,200,*,UP,PTRANS +S 11200,7700,11200,9300,400,*,UP,PDIF +S 1900,900,1900,2300,400,*,UP,NDIF +S 700,1700,700,2300,400,*,UP,NDIF +S 2600,1500,2600,2500,200,*,UP,NTRANS +S 4000,6000,6000,6000,200,*,RIGHT,POLY +S 7000,3100,7000,4900,300,*,UP,ALU1 +S -300,7800,18300,7800,6000,*,RIGHT,NWELL +S 4800,1500,4800,2500,200,*,UP,NTRANS +S 4200,1700,4200,2300,600,*,UP,NDIF +S 7800,1700,7800,2300,600,*,UP,NDIF +S 13800,1700,13800,2300,600,*,UP,NDIF +S 4200,7700,4200,9300,600,*,UP,PDIF +S 6200,1500,6200,2500,200,*,UP,NTRANS +S 6600,1700,6600,2300,400,*,UP,NDIF +S 8200,2800,8200,4000,200,*,UP,POLY +S 14200,2700,14200,2900,200,*,UP,POLY +S 13200,7100,13200,7300,200,*,UP,POLY +S 14900,5000,16000,5000,300,*,RIGHT,ALU1 +S 14900,3000,16000,3000,300,*,RIGHT,ALU1 +S 4800,6900,4800,7300,200,*,UP,POLY +S 11500,7700,11500,9300,200,*,UP,PDIF +S 6600,7700,6600,9300,200,*,UP,PDIF +S 14900,5700,14900,9300,400,*,UP,PDIF +S 15200,1200,15200,2000,300,*,UP,ALU1 +S 14200,1500,14200,2500,200,*,UP,NTRANS +S 13800,7700,13800,9300,400,*,UP,PDIF +S 13300,1500,13300,2500,200,*,UP,NTRANS +S 13300,2800,13300,5000,200,*,UP,POLY +S 12400,1500,12400,2500,200,*,UP,NTRANS +S 12400,2800,12400,4000,200,*,UP,POLY +S 8200,1500,8200,2500,200,*,UP,NTRANS +S 5500,900,5500,2300,400,*,UP,NDIF +S 2600,2800,2600,6200,200,*,UP,POLY +S 4800,2700,4800,3000,200,*,UP,POLY +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 3000,1700,3000,2300,600,*,UP,NDIF +S 7100,6000,7900,6000,300,*,RIGHT,ALU1 +S 8400,5000,8400,6200,200,*,UP,POLY +S 8000,4100,8000,5900,300,*,UP,ALU1 +S 6000,6200,6000,7200,200,*,UP,POLY +S 7900,7000,8900,7000,300,*,RIGHT,ALU1 +S 7200,1500,7200,2500,200,*,UP,NTRANS +S 8400,6500,8400,8500,200,*,UP,PTRANS +S 12000,7500,12000,9500,200,*,UP,PTRANS +S 13200,7500,13200,9500,200,*,UP,PTRANS +S 12600,7700,12600,9300,600,*,UP,PDIF +S 12700,2000,13700,2000,300,*,RIGHT,ALU1 +S 12700,8000,13700,8000,300,*,RIGHT,ALU1 +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 16000,2100,16000,7900,300,*,UP,ALU1 +S 14200,7500,14200,9500,200,*,UP,PTRANS +S 17200,6100,17200,8900,300,*,UP,ALU1 +S 17200,1100,17200,1900,300,*,UP,ALU1 +S 17300,5700,17300,9300,400,*,UP,PDIF +S 15600,5500,15600,9500,200,*,UP,PTRANS +S 15600,2800,15600,5200,200,*,UP,POLY +S 7500,6500,7500,8500,200,*,UP,PTRANS +S 7800,6700,7800,8300,400,*,UP,PDIF +S 5400,7700,5400,9300,600,*,UP,PDIF +S 4800,7500,4800,9500,200,*,UP,PTRANS +S 6000,7500,6000,9500,200,*,UP,PTRANS +S 16800,5500,16800,9500,200,*,UP,PTRANS +S 16200,5700,16200,9300,600,*,UP,PDIF +S 10800,7500,10800,9500,200,*,UP,PTRANS +S 12000,5000,12000,7200,200,*,UP,POLY +S 16800,2800,16800,5200,200,*,UP,POLY +S 9100,6000,10300,6000,300,*,RIGHT,ALU1 +S 12600,4100,12600,6900,300,*,UP,ALU1 +S 10100,2000,11300,2000,300,*,RIGHT,ALU1 +S 7900,2000,8900,2000,300,*,RIGHT,ALU1 +S 9100,3000,10300,3000,300,*,RIGHT,ALU1 +S 10100,7000,11300,7000,300,*,RIGHT,ALU1 +S 3000,2100,3000,6900,300,*,UP,ALU1 +S 5200,2000,5900,2000,300,*,RIGHT,ALU1 +S 5200,8000,5900,8000,300,*,RIGHT,ALU1 +S 13900,4000,14700,4000,300,*,RIGHT,ALU1 +S 10400,7700,10400,9300,200,*,UP,PDIF +S 2900,700,4300,700,600,*,RIGHT,PTIE +S 6500,700,7900,700,600,*,RIGHT,PTIE +S 12500,700,13900,700,600,*,RIGHT,PTIE +S 13700,2100,13700,7900,300,*,UP,ALU1 +S 16800,600,16800,2500,200,*,UP,NTRANS +S 17300,800,17300,2300,400,*,UP,NDIF +S 16200,800,16200,2300,600,*,UP,NDIF +S 15600,600,15600,2500,200,*,UP,NTRANS +S 14900,800,14900,2300,400,*,UP,NDIF +S 10800,600,10800,1500,200,*,UP,NTRANS +S 11400,800,11400,1300,600,*,UP,NDIF +S 11600,800,11600,2300,600,*,UP,NDIF +S 10200,800,10200,1300,600,*,UP,NDIF +S 9800,600,9800,1500,200,*,UP,NTRANS +S 9000,800,9000,2300,600,*,UP,NDIF +S 10400,6100,10800,6100,200,*,RIGHT,POLY +S 10800,6100,10800,7300,200,*,UP,POLY +S 9800,6900,10100,6900,200,*,RIGHT,POLY +S 9800,7000,9800,7300,200,*,UP,POLY +S 9800,2100,10100,2100,200,*,RIGHT,POLY +S 9800,1700,9800,2000,200,*,UP,POLY +S 10800,1800,10800,2900,200,*,UP,POLY +S 12700,7100,13200,7100,200,*,RIGHT,POLY +S 14200,5100,14200,7200,200,*,UP,POLY +S 12000,4000,12400,4000,200,*,RIGHT,POLY +S 7800,4000,8400,4000,200,*,RIGHT,POLY +S 1200,2900,1900,2900,200,*,RIGHT,POLY +S 1200,6100,2000,6100,200,*,RIGHT,POLY +S 4100,2100,4100,7900,300,*,UP,ALU1 +S 5000,2100,5000,7900,300,*,UP,ALU1 +S 5000,3000,5000,7000,300,i,UP,CALU1 +S 6000,8000,6000,8000,300,i,LEFT,CALU1 +S 6000,2000,6000,2000,300,i,LEFT,CALU1 +S 800,5000,13200,5000,200,nckr,RIGHT,POLY +S 11400,2100,11400,7900,300,y,UP,ALU1 +S 2000,2100,2000,7900,300,ck,UP,CALU1 +S 16000,2100,16000,7900,300,q,UP,CALU1 +V 10200,3000,CONT_POLY,* +V 14800,5000,CONT_POLY,* +V 12600,7000,CONT_POLY,* +V 10200,6000,CONT_POLY,* +V 17200,7000,CONT_DIF_P,* +V 17200,6000,CONT_DIF_P,* +V 17200,2000,CONT_DIF_N,* +V 12800,2000,CONT_DIF_N,* +V 11600,2000,CONT_DIF_N,* +V 7700,2000,CONT_DIF_N,* +V 800,2000,CONT_DIF_N,* +V 10400,9200,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 800,5000,CONT_POLY,* +V 1900,9200,CONT_DIF_P,* +V 15200,9200,CONT_DIF_P,* +V 5400,9200,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 1900,800,CONT_DIF_N,* +V 6100,3000,CONT_POLY,* +V 7100,3000,CONT_POLY,* +V 5000,3000,CONT_POLY,* +V 5000,7000,CONT_POLY,* +V 15100,2100,CONT_DIF_N,* +V 16000,2000,CONT_DIF_N,* +V 16000,8000,CONT_DIF_P,* +V 16000,7000,CONT_DIF_P,* +V 10000,2000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +V 12400,4000,CONT_POLY,* +V 10000,7000,CONT_POLY,* +V 3000,7000,CONT_DIF_P,* +V 14800,4000,CONT_POLY,* +V 3000,700,CONT_BODY_P,* +V 4200,700,CONT_BODY_P,* +V 6600,700,CONT_BODY_P,* +V 7800,700,CONT_BODY_P,* +V 12600,700,CONT_BODY_P,* +V 13700,700,CONT_BODY_P,* +V 5500,800,CONT_DIF_N,* +V 10300,900,CONT_DIF_N,* +V 15200,900,CONT_DIF_N,* +V 17200,900,CONT_DIF_N,* +V 2000,6000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 14500,3000,CONT_POLY,* +V 17200,9200,CONT_DIF_P,* +V 17200,8000,CONT_DIF_P,* +V 4200,8000,CONT_DIF_P,* +V 7000,6000,CONT_POLY,* +V 15000,8000,CONT_DIF_P,* +V 15000,7000,CONT_DIF_P,* +V 15000,6000,CONT_DIF_P,* +V 16000,6000,CONT_DIF_P,* +V 12600,8000,CONT_DIF_P,* +V 11400,8000,CONT_DIF_P,* +V 4200,2000,CONT_DIF_N,* +V 3200,4000,CONT_POLY,* +V 4000,6000,CONT_POLY,* +V 6000,6000,CONT_POLY,* +V 7000,5000,CONT_POLY,* +V 3000,2000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/sff1_x4.vbe b/pdks/symbolic/nsxlib/cells/sff1_x4.vbe new file mode 100644 index 000000000..4756bfddd --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/sff1_x4.vbe @@ -0,0 +1,39 @@ +ENTITY sff1_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tsr_i_ck : NATURAL := 476; + CONSTANT transistors : NATURAL := 26 +); +PORT ( + ck : in BIT; + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff1_x4; + +ARCHITECTURE VBE OF sff1_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff1_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED i; + END BLOCK label0; + + q <= sff_m after 1700 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/sff2_x4.ap b/pdks/symbolic/nsxlib/cells/sff2_x4.ap new file mode 100644 index 000000000..5305f3a37 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/sff2_x4.ap @@ -0,0 +1,262 @@ +V ALLIANCE : 6 +H sff2_x4,P,26/ 9/2019,100 +A 0,0,24000,10000 +R 3000,5000,ref_ref,cmd_25 +R 6000,7000,ref_ref,i1_35 +R 6000,6000,ref_ref,i1_30 +R 6000,5000,ref_ref,i1_25 +R 6000,4000,ref_ref,i1_20 +R 6000,3000,ref_ref,i1_15 +R 9000,2000,ref_ref,ck_10 +R 9000,7000,ref_ref,ck_35 +R 22000,4000,ref_ref,q_20 +R 22000,5000,ref_ref,q_25 +R 22000,3000,ref_ref,q_15 +R 3000,8000,ref_ref,cmd_40 +R 9000,5000,ref_ref,ck_25 +R 9000,4000,ref_ref,ck_20 +R 2000,3000,ref_ref,i0_15 +R 2000,4000,ref_ref,i0_20 +R 2000,5000,ref_ref,i0_25 +R 2000,7000,ref_ref,i0_35 +R 2000,6000,ref_ref,i0_30 +R 2000,8000,ref_ref,i0_40 +R 6000,2000,ref_ref,i1_10 +R 3000,6000,ref_ref,cmd_30 +R 3000,7000,ref_ref,cmd_35 +S 2000,3100,2000,7900,300,i0,UP,CALU1 +S 6000,2100,6000,7000,300,i1,UP,CALU1 +S 9000,2100,9000,6900,300,ck,UP,CALU1 +S 22000,2100,22000,7900,300,q,UP,CALU1 +S 3000,5000,3000,7900,300,cmd,UP,CALU1 +S 13200,6000,13200,6400,200,*,UP,POLY +S 17000,1800,17000,3100,200,*,UP,POLY +S 13500,2600,13500,2800,200,*,UP,POLY +S 12700,1700,12700,2300,600,*,UP,NDIF +S 8200,6100,8700,6100,200,*,RIGHT,POLY +S 4200,6700,4200,8300,400,*,UP,PDIF +S 15100,800,15100,2300,400,*,UP,NDIF +S 15400,800,15400,1300,600,*,UP,NDIF +S 16100,600,16100,1500,200,*,UP,NTRANS +S 17400,800,17400,1300,400,*,UP,NDIF +S 17800,800,17800,2300,600,*,UP,NDIF +S 17000,600,17000,1500,200,*,UP,NTRANS +S 21100,800,21100,2300,400,*,UP,NDIF +S 23300,800,23300,2300,400,*,UP,NDIF +S 22800,600,22800,2500,200,*,UP,NTRANS +S 22200,800,22200,2300,600,*,UP,NDIF +S 21600,600,21600,2500,200,*,UP,NTRANS +S 4500,6700,4500,8300,200,*,UP,PDIF +S 17600,7700,17600,9300,200,*,UP,PDIF +S 16400,7700,16400,9300,200,*,UP,PDIF +S 22000,2100,22000,7900,300,*,UP,ALU1 +S 20400,1500,20400,2500,200,*,UP,NTRANS +S 19200,7500,19200,9500,200,*,UP,PTRANS +S 18000,7500,18000,9500,200,*,UP,PTRANS +S 14400,1500,14400,2500,200,*,UP,NTRANS +S 15600,7500,15600,9500,200,*,UP,PTRANS +S 14400,6500,14400,8500,200,*,UP,PTRANS +S 13200,6500,13200,8500,200,*,UP,PTRANS +S -300,7800,24300,7800,6000,*,RIGHT,NWELL +S 3800,1700,3800,2300,600,*,UP,NDIF +S 9000,900,9000,2300,600,*,UP,NDIF +S 10200,1700,10200,2300,600,*,UP,NDIF +S 11400,900,11400,2300,600,*,UP,NDIF +S 6400,6700,6400,9100,600,*,UP,PDIF +S 18600,7700,18600,9300,600,*,UP,PDIF +S 17200,7700,17200,9300,600,*,UP,PDIF +S 9000,6700,9000,9100,600,*,UP,PDIF +S 22800,5500,22800,9500,200,*,UP,PTRANS +S 22200,5700,22200,9300,600,*,UP,PDIF +S 16800,7500,16800,9500,200,*,UP,PTRANS +S 21000,5700,21000,9300,600,*,UP,PDIF +S 21600,5500,21600,9500,200,*,UP,PTRANS +S 13800,6700,13800,8300,600,*,UP,PDIF +S 5000,2800,5000,5000,200,*,UP,POLY +S 21600,2800,21600,5200,200,*,UP,POLY +S 14400,2800,14400,4000,200,*,UP,POLY +S 18000,5000,18000,7200,200,*,UP,POLY +S 16800,6000,16800,7200,200,*,UP,POLY +S 22800,2800,22800,5200,200,*,UP,POLY +S 14400,5000,14400,6200,200,*,UP,POLY +S 700,2000,4900,2000,300,*,RIGHT,ALU1 +S 600,2100,600,6900,300,*,UP,ALU1 +S 9000,2100,9000,6900,300,*,UP,ALU1 +S 10200,2100,10200,6900,300,*,UP,ALU1 +S 5000,2100,5000,5900,300,*,UP,ALU1 +S 3000,2100,3000,3900,300,*,UP,ALU1 +S 6000,2100,6000,6900,300,*,UP,ALU1 +S 7800,2100,7800,6900,300,*,UP,ALU1 +S 13900,2000,14900,2000,300,*,RIGHT,ALU1 +S 2000,3100,2000,7900,300,*,UP,ALU1 +S 4100,8000,11900,8000,300,*,RIGHT,ALU1 +S 3000,5100,3000,7900,300,*,UP,ALU1 +S 4000,3100,4000,7900,300,*,UP,ALU1 +S 16100,7000,17300,7000,300,*,RIGHT,ALU1 +S 21000,6100,21000,8900,300,*,UP,ALU1 +S 15100,6000,16300,6000,300,*,RIGHT,ALU1 +S 18600,4100,18600,6900,300,*,UP,ALU1 +S 15100,3000,16300,3000,300,*,RIGHT,ALU1 +S 18700,8000,19700,8000,300,*,RIGHT,ALU1 +S 13900,7000,14900,7000,300,*,RIGHT,ALU1 +S 14000,4100,14000,5900,300,*,UP,ALU1 +S 13100,6000,13900,6000,300,*,RIGHT,ALU1 +S 13000,3100,13000,4900,300,*,UP,ALU1 +S 13200,1700,13200,2300,400,*,UP,NDIF +S 16100,2000,17600,2000,300,*,RIGHT,ALU1 +S 18600,1500,18600,2500,200,*,UP,NTRANS +S 19200,2000,19700,2000,300,*,RIGHT,ALU1 +S 3500,6500,3500,8500,200,*,UP,PTRANS +S 4700,6500,4700,8500,200,*,UP,PTRANS +S 5600,6500,5600,8500,200,*,UP,PTRANS +S 8200,6500,8200,8500,200,*,UP,PTRANS +S 20400,3000,21000,3000,400,*,RIGHT,POLY +S 18600,7000,19200,7000,400,*,RIGHT,POLY +S 15600,7000,16200,7000,400,*,RIGHT,POLY +S 20400,2700,20400,2800,200,*,UP,POLY +S 16100,1700,16100,1900,200,*,UP,POLY +S 12200,2700,12200,2900,200,*,UP,POLY +S 2500,2600,2500,2900,200,*,UP,POLY +S 2500,6000,2500,6300,200,*,UP,POLY +S 15900,2000,16100,2000,400,*,RIGHT,POLY +S 16400,3000,16900,3000,400,*,RIGHT,POLY +S 18300,4000,18500,4000,400,*,RIGHT,POLY +S 20200,4900,20200,7200,200,*,UP,POLY +S 20800,4000,22800,4000,400,*,RIGHT,POLY +S 20400,5000,21000,5000,400,*,RIGHT,POLY +S 20900,5000,22000,5000,300,*,RIGHT,ALU1 +S 12500,6700,12500,9300,400,*,UP,PDIF +S 16000,7700,16000,9300,600,*,UP,PDIF +S 15200,7700,15200,9300,600,*,UP,PDIF +S 20200,7500,20200,9500,200,*,UP,PTRANS +S 19800,7700,19800,9300,600,*,UP,PDIF +S 8200,6100,8200,6400,200,*,UP,POLY +S 8200,2700,8200,2900,200,*,UP,POLY +S 20900,3000,22000,3000,300,*,RIGHT,ALU1 +S 2500,6500,2500,8500,200,*,UP,PTRANS +S 3400,2800,3400,4000,200,*,UP,POLY +S 1800,6700,1800,9100,400,*,UP,PDIF +S 600,6700,600,8300,400,*,UP,PDIF +S 1100,2800,1100,6200,200,*,UP,POLY +S 1100,6500,1100,8500,200,*,UP,PTRANS +S 3400,1500,3400,2500,200,*,UP,NTRANS +S 2500,1500,2500,2500,200,*,UP,NTRANS +S 1100,1500,1100,2500,200,*,UP,NTRANS +S 600,1700,600,2300,400,*,UP,NDIF +S 9800,6500,9800,8500,200,*,UP,PTRANS +S 9800,2800,9800,6200,200,*,UP,POLY +S 7700,6700,7700,8300,400,*,UP,PDIF +S 10300,6700,10300,8300,400,*,UP,PDIF +S 11800,7500,11800,9500,200,*,UP,PTRANS +S 11300,7700,11300,9300,400,*,UP,PDIF +S 19200,7100,19200,7200,200,*,UP,POLY +S 15600,7200,15600,7300,200,*,UP,POLY +S 11800,7000,11800,7300,200,*,UP,POLY +S 4700,6100,4700,6300,200,*,UP,POLY +S 5900,2700,5900,2900,200,*,UP,POLY +S 16200,6000,16800,6000,500,*,RIGHT,POLY +S 1200,5200,5000,5200,200,*,RIGHT,POLY +S 3500,5300,3500,6300,200,*,UP,POLY +S 19200,3000,19200,5000,200,*,UP,POLY +S 19200,2900,19500,2900,200,*,RIGHT,POLY +S 18200,2900,18600,2900,200,*,RIGHT,POLY +S 1800,900,1800,2300,400,*,UP,NDIF +S 7700,1700,7700,2300,400,*,UP,NDIF +S 8200,1500,8200,2500,200,*,UP,NTRANS +S 9800,1500,9800,2500,200,*,UP,NTRANS +S 12200,1500,12200,2500,200,*,UP,NTRANS +S 13500,1500,13500,2500,200,*,UP,NTRANS +S 23300,5700,23300,9300,400,*,UP,PDIF +S 23200,1100,23200,1900,300,*,UP,ALU1 +S 21200,1100,21200,1900,300,*,UP,ALU1 +S 19500,1500,19500,2500,200,*,UP,NTRANS +S 4200,1700,4200,3100,600,*,UP,NDIF +S 5000,1500,5000,2500,200,*,UP,NTRANS +S 5900,1500,5900,2500,200,*,UP,NTRANS +S 6600,900,6600,2300,400,*,UP,NDIF +S 18200,3000,18200,4100,200,*,UP,POLY +S 18600,2600,18600,2900,200,*,UP,POLY +S 19500,2600,19500,2900,200,*,UP,POLY +S 23200,6100,23200,8900,300,*,UP,ALU1 +S 19900,4000,20700,4000,300,*,RIGHT,ALU1 +S 17400,2100,17400,7900,300,y,UP,ALU1 +S 8000,5000,19200,5000,200,nckr,RIGHT,POLY +S 15000,2100,15000,6900,300,sff_m,UP,ALU1 +S 19800,2100,19800,7900,300,sff_s,UP,ALU1 +S 10400,4000,18200,4000,500,ckr,RIGHT,POLY +S 12000,3100,12000,7900,300,u,UP,ALU1 +S 0,600,24000,600,1200,vss,RIGHT,CALU1 +S 0,9400,24000,9400,1200,vdd,RIGHT,CALU1 +S 1900,6100,2500,6100,400,*,RIGHT,POLY +S 5700,6100,6000,6100,400,*,RIGHT,POLY +S 5600,6000,5600,6400,200,*,UP,POLY +S 12900,2800,13500,2800,200,*,RIGHT,POLY +S 8200,2900,8800,2900,200,*,RIGHT,POLY +S 1900,2900,2500,2900,400,*,RIGHT,POLY +V 22000,2000,CONT_DIF_N,* +V 14000,2000,CONT_DIF_N,* +V 17800,2000,CONT_DIF_N,* +V 19100,2000,CONT_DIF_N,* +V 21200,2000,CONT_DIF_N,* +V 23200,2000,CONT_DIF_N,* +V 23200,6000,CONT_DIF_P,* +V 23200,7000,CONT_DIF_P,* +V 23200,8000,CONT_DIF_P,* +V 23200,9200,CONT_DIF_P,* +V 22000,6000,CONT_DIF_P,* +V 22000,7000,CONT_DIF_P,* +V 22000,8000,CONT_DIF_P,* +V 20800,4000,CONT_POLY,* +V 13000,5000,CONT_POLY,* +V 13000,3000,CONT_POLY,* +V 20800,5000,CONT_POLY,* +V 16400,3000,CONT_POLY,* +V 18400,4000,CONT_POLY,* +V 14000,4000,CONT_POLY,* +V 11800,7000,CONT_POLY,* +V 10400,4000,CONT_POLY,* +V 6000,3000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 21000,7000,CONT_DIF_P,* +V 13800,7000,CONT_DIF_P,* +V 16000,2000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 2000,6000,CONT_POLY,* +V 21000,8000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 18600,8000,CONT_DIF_P,* +V 17400,8000,CONT_DIF_P,* +V 21000,6000,CONT_DIF_P,* +V 10200,7000,CONT_DIF_P,* +V 7800,7000,CONT_DIF_P,* +V 7800,2000,CONT_DIF_N,* +V 10200,2000,CONT_DIF_N,* +V 8000,5000,CONT_POLY,* +V 9000,900,CONT_DIF_N,* +V 11400,900,CONT_DIF_N,* +V 16600,900,CONT_DIF_N,* +V 21200,900,CONT_DIF_N,* +V 23200,900,CONT_DIF_N,* +V 3100,4000,CONT_POLY,* +V 13100,6000,CONT_POLY,* +V 12100,3000,CONT_POLY,* +V 16200,6000,CONT_POLY,* +V 18600,7000,CONT_POLY,* +V 21000,3000,CONT_POLY,* +V 4900,6000,CONT_POLY,* +V 16200,7000,CONT_POLY,* +V 6000,6000,CONT_POLY,* +V 6700,900,CONT_DIF_N,* +V 1800,800,CONT_DIF_N,* +V 9000,3000,CONT_POLY,* +V 9000,6000,CONT_POLY,* +V 21000,9200,CONT_DIF_P,* +V 16200,9200,CONT_DIF_P,* +V 11400,9200,CONT_DIF_P,* +V 9000,9200,CONT_DIF_P,* +V 4200,3100,CONT_DIF_N,* +V 700,2000,CONT_DIF_N,* +V 700,7000,CONT_DIF_P,* +V 1800,9200,CONT_DIF_P,* +V 6400,9300,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/sff2_x4.vbe b/pdks/symbolic/nsxlib/cells/sff2_x4.vbe new file mode 100644 index 000000000..59eaa6446 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/sff2_x4.vbe @@ -0,0 +1,51 @@ +ENTITY sff2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd : NATURAL := 16; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 7; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_cmd_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thr_cmd_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT tsf_cmd_ck : NATURAL := 833; + CONSTANT tsf_i0_ck : NATURAL := 764; + CONSTANT tsf_i1_ck : NATURAL := 764; + CONSTANT tsr_cmd_ck : NATURAL := 770; + CONSTANT tsr_i0_ck : NATURAL := 666; + CONSTANT tsr_i1_ck : NATURAL := 666; + CONSTANT transistors : NATURAL := 34 +); +PORT ( + ck : in BIT; + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff2_x4; + +ARCHITECTURE VBE OF sff2_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff2_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd))); + END BLOCK label0; + + q <= sff_m after 2000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/tie_x0.ap b/pdks/symbolic/nsxlib/cells/tie_x0.ap new file mode 100644 index 000000000..abad9522e --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/tie_x0.ap @@ -0,0 +1,18 @@ +V ALLIANCE : 6 +H tie_x0,P,17/ 9/2019,100 +A 0,0,2000,10000 +S 1000,6100,1000,9000,600,*,UP,NTIE +S 1000,1100,1000,2900,600,*,UP,PTIE +S 0,9400,2000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,2000,600,1200,vss,RIGHT,CALU1 +S 1000,900,1000,2700,300,*,UP,ALU1 +S 1000,6400,1000,9200,300,*,UP,ALU1 +S -300,7800,2300,7800,6000,*,RIGHT,NWELL +V 1000,2000,CONT_BODY_P,* +V 1000,3000,CONT_BODY_P,* +V 1000,9000,CONT_BODY_N,* +V 1000,1000,CONT_BODY_P,* +V 1000,8000,CONT_BODY_N,* +V 1000,7000,CONT_BODY_N,* +V 1000,6000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/tie_x0.vbe b/pdks/symbolic/nsxlib/cells/tie_x0.vbe new file mode 100644 index 000000000..938a45c77 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/tie_x0.vbe @@ -0,0 +1,18 @@ +ENTITY tie_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 500; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END tie_x0; + +ARCHITECTURE behaviour_data_flow OF tie_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on tie_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/nsxlib/cells/ts_x4.ap b/pdks/symbolic/nsxlib/cells/ts_x4.ap new file mode 100644 index 000000000..0bd4a6e66 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ts_x4.ap @@ -0,0 +1,125 @@ +V ALLIANCE : 6 +H ts_x4,P,18/ 9/2019,100 +A 0,0,10000,10000 +R 3000,6000,ref_ref,cmd_30 +R 3000,7000,ref_ref,cmd_35 +R 3000,8000,ref_ref,cmd_40 +R 3000,4000,ref_ref,cmd_20 +R 3000,5000,ref_ref,cmd_25 +R 2000,5000,ref_ref,q_25 +R 2000,4000,ref_ref,q_20 +R 2000,3000,ref_ref,q_15 +R 8000,6000,ref_ref,i_30 +R 8000,5000,ref_ref,i_25 +R 8000,4000,ref_ref,i_20 +R 3000,2000,ref_ref,cmd_10 +R 8000,3000,ref_ref,i_15 +R 8000,7000,ref_ref,i_35 +S 2000,2100,2000,7900,300,q,UP,CALU1 +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 8000,3100,8000,6900,300,i,UP,CALU1 +S 3000,4000,3000,7900,300,cmd,UP,CALU1 +S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 +S 0,600,10000,600,1200,vss,RIGHT,CALU1 +S 3100,5800,3700,5800,500,*,RIGHT,ALU1 +S 7900,2600,7900,2900,200,*,UP,POLY +S 3800,5700,3800,7200,200,*,UP,POLY +S 7400,5700,7400,6200,200,*,UP,POLY +S 1200,4600,9300,4600,200,*,RIGHT,POLY +S 7000,1700,7000,2300,200,*,UP,NDIF +S 7200,900,7200,2300,400,*,UP,NDIF +S 7900,1500,7900,2500,200,*,UP,NTRANS +S 700,5700,700,9300,400,*,UP,PDIF +S 800,6100,800,8900,300,*,UP,ALU1 +S 800,1100,800,1900,300,*,UP,ALU1 +S 3800,7500,3800,9500,200,*,UP,PTRANS +S 3800,1500,3800,2500,200,*,UP,NTRANS +S 8400,1700,8400,2300,400,*,UP,NDIF +S 7000,6700,7000,8300,400,*,UP,PDIF +S 7400,6500,7400,8500,200,*,UP,PTRANS +S 8100,6700,8100,9300,400,*,UP,PDIF +S 9300,1700,9300,2300,400,*,UP,NDIF +S 9300,6700,9300,8300,400,*,UP,PDIF +S 7100,8000,9000,8000,300,*,RIGHT,ALU1 +S 9200,2100,9200,7900,300,*,UP,ALU1 +S 4800,2200,4800,7900,300,*,UP,ALU1 +S 4300,2100,4700,2100,300,*,RIGHT,ALU1 +S 6400,6500,6400,8500,200,*,UP,PTRANS +S 7000,3700,7000,5300,300,*,UP,ALU1 +S 6000,2100,6000,7900,300,*,UP,ALU1 +S 5000,2900,6400,2900,200,*,RIGHT,POLY +S 7000,3800,8800,3800,200,*,RIGHT,POLY +S 1200,3800,6100,3800,200,*,RIGHT,POLY +S 5000,6100,6400,6100,200,*,RIGHT,POLY +S 6000,6700,6000,8300,600,*,UP,PDIF +S 8800,6100,8800,6400,200,*,UP,POLY +S 3800,5600,7400,5600,200,*,RIGHT,POLY +S 4200,7700,4200,9300,600,*,UP,PDIF +S 3000,2100,3000,7900,300,*,UP,ALU1 +S 4200,1700,4200,2300,600,*,UP,NDIF +S 7000,7100,7000,7900,300,*,UP,ALU1 +S 1200,600,1200,2500,200,*,UP,NTRANS +S 700,800,700,2300,400,*,UP,NDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S 1800,800,1800,2300,600,*,UP,NDIF +S 3000,800,3000,2300,600,*,UP,NDIF +S 3000,2900,3800,2900,200,*,RIGHT,POLY +S 8800,2800,8800,3800,200,*,UP,POLY +S 2400,2800,2400,3800,200,*,UP,POLY +S 1200,2800,1200,3800,200,*,UP,POLY +S 8800,6500,8800,8500,200,*,UP,PTRANS +S 8000,3100,8000,6900,300,*,UP,ALU1 +S 1200,5500,1200,9500,200,*,UP,PTRANS +S 5900,2000,8100,2000,300,*,RIGHT,ALU1 +S 6400,1500,6400,2500,200,*,UP,NTRANS +S 8800,1500,8800,2500,200,*,UP,NTRANS +S 5800,1700,5800,2300,600,*,UP,NDIF +S -300,7800,10300,7800,6000,*,RIGHT,NWELL +S 1200,4600,1200,5200,200,*,UP,POLY +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 2400,4600,2400,5200,200,*,UP,POLY +S 3000,5700,3000,9300,600,*,UP,PDIF +S 1800,5700,1800,9300,600,*,UP,PDIF +S 6400,6100,6400,6400,200,*,UP,POLY +S 3800,2600,3800,2900,200,*,UP,POLY +S 6400,2600,6400,2900,200,*,UP,POLY +S 8200,6100,8800,6100,200,*,RIGHT,POLY +S 4300,8000,4700,8000,400,4,RIGHT,ALU1 +V 4000,5800,CONT_POLY,* +V 5000,6400,CONT_POLY,* +V 6000,2000,CONT_DIF_N,* +V 6000,8000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,3600,CONT_POLY,* +V 7000,5400,CONT_POLY,* +V 7000,3600,CONT_POLY,* +V 8000,6000,CONT_POLY,* +V 8300,2000,CONT_DIF_N,* +V 5400,9200,CONT_BODY_N,* +V 3000,3000,CONT_POLY,* +V 3000,9200,CONT_DIF_P,* +V 3000,900,CONT_DIF_N,* +V 800,900,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 5000,800,CONT_BODY_P,* +V 5000,3000,CONT_POLY,* +V 2000,6000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 7200,800,CONT_DIF_N,* +V 800,6000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 800,9200,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 8100,9200,CONT_DIF_P,* +V 9200,2000,CONT_DIF_N,* +V 9200,4600,CONT_POLY,* +V 9200,7000,CONT_DIF_P,* +V 9200,8000,CONT_DIF_P,* +V 4200,2100,CONT_DIF_N,* +V 4200,8000,CONT_DIF_P,* +V 8000,3000,CONT_POLY,* +V 7000,8000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/ts_x4.vbe b/pdks/symbolic/nsxlib/cells/ts_x4.vbe new file mode 100644 index 000000000..25d28a499 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ts_x4.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphl_cmd_q : NATURAL := 409; + CONSTANT tpll_i_q : NATURAL := 444; + CONSTANT tphh_i_q : NATURAL := 475; + CONSTANT tphh_cmd_q : NATURAL := 492; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x4; + +ARCHITECTURE behaviour_data_flow OF ts_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x4" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1100 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/nsxlib/cells/ts_x8.ap b/pdks/symbolic/nsxlib/cells/ts_x8.ap new file mode 100644 index 000000000..2f2b3fcb6 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ts_x8.ap @@ -0,0 +1,152 @@ +V ALLIANCE : 6 +H ts_x8,P,26/ 9/2019,100 +A 0,0,13000,10000 +R 5000,5000,ref_ref,q_25 +R 6000,5000,ref_ref,cmd_25 +R 6000,4000,ref_ref,cmd_20 +R 11000,6000,ref_ref,i_30 +R 11000,5000,ref_ref,i_25 +R 11000,4000,ref_ref,i_20 +R 5000,4000,ref_ref,q_20 +R 5000,3000,ref_ref,q_15 +R 11000,7000,ref_ref,i_35 +R 11000,3000,ref_ref,i_15 +R 6000,2000,ref_ref,cmd_10 +R 6000,6000,ref_ref,cmd_30 +R 6000,7000,ref_ref,cmd_35 +R 6000,8000,ref_ref,cmd_40 +S 7300,8000,7700,8000,400,*,RIGHT,ALU1 +S 10000,7100,10000,7900,300,*,UP,ALU1 +S -300,7800,13300,7800,6000,*,RIGHT,NWELL +S 9400,1500,9400,2500,200,*,UP,NTRANS +S 6600,1500,6600,2500,200,*,UP,NTRANS +S 9400,6500,9400,8500,200,*,UP,PTRANS +S 7200,7700,7200,9300,600,*,UP,PDIF +S 4200,5500,4200,9500,200,*,UP,PTRANS +S 3600,5700,3600,9300,600,*,UP,PDIF +S 1200,6100,1200,8900,300,*,UP,ALU1 +S 11800,2800,11800,3800,200,*,UP,POLY +S 5400,2800,5400,3800,200,*,UP,POLY +S 4200,2800,4200,3800,200,*,UP,POLY +S 4200,4600,4200,5200,200,*,UP,POLY +S 5400,4600,5400,5200,200,*,UP,POLY +S 1800,4600,1800,5200,200,*,UP,POLY +S 3000,4600,3000,5200,200,*,UP,POLY +S 1800,2800,1800,3800,200,*,UP,POLY +S 3000,2800,3000,3800,200,*,UP,POLY +S 3000,5500,3000,9500,200,*,UP,PTRANS +S 1800,5500,1800,9500,200,*,UP,PTRANS +S 2400,5700,2400,9300,600,*,UP,PDIF +S 5400,5500,5400,9500,200,*,UP,PTRANS +S 6000,5700,6000,9300,600,*,UP,PDIF +S 4800,5700,4800,9300,600,*,UP,PDIF +S 10400,5400,10400,6200,200,*,UP,POLY +S 11000,3100,11000,6900,300,*,UP,ALU1 +S 8800,2100,8800,7900,300,*,UP,ALU1 +S 3600,1100,3600,1900,300,*,UP,ALU1 +S 3600,6100,3600,8900,300,*,UP,ALU1 +S 1200,5700,1200,9300,600,*,UP,PDIF +S 11800,1500,11800,2500,200,*,UP,NTRANS +S 8800,1700,8800,2300,600,*,UP,NDIF +S 7200,1700,7200,2300,600,*,UP,NDIF +S 7900,6100,9400,6100,200,*,RIGHT,POLY +S 7900,2100,7900,7900,300,*,UP,ALU1 +S 9000,6700,9000,8300,600,*,UP,PDIF +S 11000,6100,11800,6100,200,*,RIGHT,POLY +S 11000,2600,11000,3000,200,*,UP,POLY +S 11800,6500,11800,8500,200,*,UP,PTRANS +S 7300,2000,7700,2000,300,*,RIGHT,ALU1 +S 9800,3700,9800,5300,300,*,UP,ALU1 +S 6100,6000,6700,6000,300,*,RIGHT,ALU1 +S 6000,2100,6000,7900,300,*,UP,ALU1 +S 10100,8000,12300,8000,300,*,RIGHT,ALU1 +S 8900,2000,11100,2000,300,*,RIGHT,ALU1 +S 2400,2100,2400,7900,300,*,UP,ALU1 +S 2500,4200,4900,4200,300,*,RIGHT,ALU1 +S 12200,2100,12200,7900,300,*,UP,ALU1 +S 12300,1700,12300,2300,400,*,UP,NDIF +S 12300,6700,12300,8300,400,*,UP,PDIF +S 11000,1500,11000,2500,200,*,UP,NTRANS +S 10200,900,10200,2300,600,*,UP,NDIF +S 11100,6700,11100,9000,400,*,UP,PDIF +S 10400,6500,10400,8500,200,*,UP,PTRANS +S 6800,5400,10400,5400,200,*,RIGHT,POLY +S 6800,5500,6800,7200,200,*,UP,POLY +S 10000,6700,10000,8300,400,*,UP,PDIF +S 6800,7500,6800,9500,200,*,UP,PTRANS +S 1400,1100,1400,1900,300,*,UP,ALU1 +S 3000,600,3000,2500,200,*,UP,NTRANS +S 1800,600,1800,2500,200,*,UP,NTRANS +S 2400,800,2400,2300,600,*,UP,NDIF +S 4800,800,4800,2300,600,*,UP,NDIF +S 4200,600,4200,2500,200,*,UP,NTRANS +S 5400,600,5400,2500,200,*,UP,NTRANS +S 3600,800,3600,2300,600,*,UP,NDIF +S 1300,800,1300,2300,600,*,UP,NDIF +S 1800,3800,8900,3800,200,*,RIGHT,POLY +S 9700,3800,11800,3800,200,*,RIGHT,POLY +S 5900,800,5900,2300,400,*,UP,NDIF +S 1800,4600,12300,4600,200,*,RIGHT,POLY +S 6800,5700,6800,6000,200,*,UP,POLY +S 7900,700,8900,700,400,*,RIGHT,PTIE +S 6400,2900,6600,2900,200,*,RIGHT,POLY +S 7700,2900,9400,2900,200,*,RIGHT,POLY +S 9400,2600,9400,2900,200,*,UP,POLY +S 6600,2600,6600,2900,200,*,UP,POLY +S 9400,6100,9400,6400,200,*,UP,POLY +S 11800,6100,11800,6400,200,*,UP,POLY +S 0,600,13000,600,1200,vss,RIGHT,CALU1 +S 0,9400,13000,9400,1200,vdd,RIGHT,CALU1 +S 6000,4000,6000,7900,300,cmd,UP,CALU1 +S 11000,3100,11000,6900,300,i,UP,CALU1 +S 5000,2100,5000,7900,300,*,UP,ALU1 +S 5000,2100,5000,7900,300,q,UP,CALU1 +S 6200,2800,6200,3200,300,*,DOWN,ALU1 +V 1200,7000,CONT_DIF_P,* +V 1200,6000,CONT_DIF_P,* +V 2400,6000,CONT_DIF_P,* +V 2400,7000,CONT_DIF_P,* +V 2400,8000,CONT_DIF_P,* +V 8800,2000,CONT_DIF_N,* +V 7200,2000,CONT_DIF_N,* +V 3600,2000,CONT_DIF_N,* +V 2400,2000,CONT_DIF_N,* +V 10000,7000,CONT_DIF_P,* +V 3600,900,CONT_DIF_N,* +V 6500,3000,CONT_POLY,* +V 8400,9200,CONT_BODY_N,* +V 11000,6000,CONT_POLY,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 8000,6400,CONT_POLY,* +V 7000,6000,CONT_POLY,* +V 12300,2000,CONT_DIF_N,* +V 10200,900,CONT_DIF_N,* +V 8300,800,CONT_BODY_P,* +V 5800,900,CONT_DIF_N,* +V 1400,900,CONT_DIF_N,* +V 3600,9200,CONT_DIF_P,* +V 1200,9200,CONT_DIF_P,* +V 1400,2000,CONT_DIF_N,* +V 5000,2000,CONT_DIF_N,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 6200,9200,CONT_DIF_P,* +V 11100,9200,CONT_DIF_P,* +V 11400,2000,CONT_DIF_N,* +V 12200,4600,CONT_POLY,* +V 12200,7000,CONT_DIF_P,* +V 12200,8000,CONT_DIF_P,* +V 9800,5400,CONT_POLY,* +V 9800,3600,CONT_POLY,* +V 11000,3000,CONT_POLY,* +V 7800,3000,CONT_POLY,* +V 8800,3600,CONT_POLY,* +V 7200,8000,CONT_DIF_P,* +V 3600,7000,CONT_DIF_P,* +V 3600,8000,CONT_DIF_P,* +V 3600,6000,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 1200,8000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/ts_x8.vbe b/pdks/symbolic/nsxlib/cells/ts_x8.vbe new file mode 100644 index 000000000..c92f94f59 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/ts_x8.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 400; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_cmd_q : NATURAL := 450; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphl_cmd_q : NATURAL := 466; + CONSTANT tpll_i_q : NATURAL := 569; + CONSTANT tphh_i_q : NATURAL := 613; + CONSTANT tphh_cmd_q : NATURAL := 626; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x8; + +ARCHITECTURE behaviour_data_flow OF ts_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x8" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1200 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/nsxlib/cells/xr2_x1.ap b/pdks/symbolic/nsxlib/cells/xr2_x1.ap new file mode 100644 index 000000000..ae0bbf751 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/xr2_x1.ap @@ -0,0 +1,121 @@ +V ALLIANCE : 6 +H xr2_x1,P,26/ 9/2019,100 +A 0,0,9000,10000 +R 7000,7000,ref_ref,i1_35 +R 7000,8000,ref_ref,i1_40 +R 3000,6000,ref_ref,q_30 +R 2000,4000,ref_ref,i0_20 +R 2000,5000,ref_ref,i0_25 +R 2000,3000,ref_ref,i0_15 +R 2000,2000,ref_ref,i0_10 +R 3000,2000,ref_ref,q_10 +R 2000,6000,ref_ref,i0_30 +R 2000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i0_40 +R 7000,2000,ref_ref,i1_10 +R 7000,3000,ref_ref,i1_15 +R 7000,4000,ref_ref,i1_20 +R 7000,5000,ref_ref,i1_25 +R 7000,6000,ref_ref,i1_30 +R 3000,5000,ref_ref,q_25 +R 3000,4000,ref_ref,q_20 +R 3000,3000,ref_ref,q_15 +S 3600,5300,3600,5600,200,*,UP,POLY +S 3600,5200,4100,5200,200,*,RIGHT,POLY +S 1200,5200,2400,5200,200,*,RIGHT,POLY +S 2400,5200,2400,5500,200,*,UP,POLY +S 1200,2500,1200,2800,200,*,UP,POLY +S 1200,2800,2400,2800,200,*,RIGHT,POLY +S 2400,2600,2400,2800,200,*,UP,POLY +S 7000,2100,7000,7900,300,i1,UP,CALU1 +S 3000,2100,3000,5900,300,*,UP,ALU1 +S 3000,2100,3000,5900,300,q,UP,CALU1 +S 2000,2100,2000,7900,300,i0,UP,CALU1 +S 4200,5700,4200,9300,600,*,UP,PDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 3000,5700,3000,9300,600,*,UP,PDIF +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 7200,6500,7200,8500,200,*,UP,PTRANS +S 7200,1500,7200,2500,200,*,UP,NTRANS +S 6000,5100,6000,5400,200,*,UP,POLY +S 6000,2800,6000,4000,200,*,UP,POLY +S 4100,3000,6900,3000,300,*,RIGHT,ALU1 +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 5400,5700,5400,9300,600,*,UP,PDIF +S 6000,5500,6000,9500,200,*,UP,PTRANS +S 1200,5200,1200,6200,200,*,UP,POLY +S 4800,2800,4800,5200,200,*,UP,POLY +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 3100,8000,5300,8000,300,*,RIGHT,ALU1 +S 3600,2600,3600,2900,200,*,UP,POLY +S 6000,5100,7200,5100,200,*,RIGHT,POLY +S 7000,2100,7000,7900,300,*,UP,ALU1 +S 7200,5200,7200,6200,200,*,UP,POLY +S 1200,1500,1200,2500,200,*,UP,NTRANS +S -300,7800,9300,7800,6000,*,RIGHT,NWELL +S 3600,2900,4100,2900,200,*,RIGHT,POLY +S 4200,800,4200,2300,600,*,UP,NDIF +S 1900,800,1900,2300,400,*,UP,NDIF +S 6500,800,6500,2300,400,*,UP,NDIF +S 5400,800,5400,2300,600,*,UP,NDIF +S 6000,600,6000,2500,200,*,UP,NTRANS +S 4800,600,4800,2500,200,*,UP,NTRANS +S 3000,800,3000,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 2400,600,2400,2500,200,*,UP,NTRANS +S 3100,2000,4100,2000,300,*,RIGHT,ALU1 +S 6000,4000,8000,4000,200,*,RIGHT,POLY +S 5000,4100,5000,4900,300,*,UP,ALU1 +S 5100,4000,5900,4000,300,*,RIGHT,ALU1 +S 4100,5000,4900,5000,300,*,RIGHT,ALU1 +S 8000,2100,8000,6900,300,*,UP,ALU1 +S 8000,6700,8000,8300,600,*,UP,PDIF +S 8000,1700,8000,2300,600,*,UP,NDIF +S 5400,6100,5400,7900,300,*,UP,ALU1 +S 4000,6100,4000,6900,300,*,UP,ALU1 +S 3100,6000,3900,6000,300,*,RIGHT,ALU1 +S 8000,7100,8000,7900,300,*,UP,ALU1 +S 3000,7100,3000,7900,300,*,UP,ALU1 +S 7600,6700,7600,8300,200,*,UP,PDIF +S 7600,1700,7600,2300,200,*,UP,NDIF +S 1900,5700,1900,9300,400,*,UP,PDIF +S 6500,5700,6500,9300,400,*,UP,PDIF +S 800,2100,800,6900,300,*,UP,ALU1 +S 800,7100,800,7900,300,*,UP,ALU1 +S 700,6700,700,8300,400,*,UP,PDIF +S 700,1700,700,2300,400,*,UP,NDIF +S 700,4000,4800,4000,200,*,RIGHT,POLY +S 7200,2700,7200,3100,200,*,UP,POLY +S 0,600,9000,600,1200,vss,RIGHT,CALU1 +S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 +S 8000,9200,8300,9200,600,*,RIGHT,NTIE +V 2000,5000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 8000,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 6400,9200,CONT_DIF_P,* +V 7000,5000,CONT_POLY,* +V 3000,8000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 7900,700,CONT_BODY_P,* +V 6400,900,CONT_DIF_N,* +V 2000,900,CONT_DIF_N,* +V 8100,9200,CONT_BODY_N,* +V 7000,3000,CONT_POLY,* +V 800,7000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 800,4000,CONT_POLY,* +V 800,2000,CONT_DIF_N,* +V 2000,9200,CONT_DIF_P,* +V 6000,4000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +V 8000,7000,CONT_DIF_P,* +V 8000,2000,CONT_DIF_N,* +V 5400,7000,CONT_DIF_P,* +V 5400,6000,CONT_DIF_P,* +V 4200,3000,CONT_POLY,* +V 4200,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/xr2_x1.vbe b/pdks/symbolic/nsxlib/cells/xr2_x1.vbe new file mode 100644 index 000000000..925f29ad5 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/xr2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY xr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i1_q : NATURAL := 261; + CONSTANT tphl_i0_q : NATURAL := 292; + CONSTANT tplh_i0_q : NATURAL := 293; + CONSTANT tphh_i0_q : NATURAL := 366; + CONSTANT tphl_i1_q : NATURAL := 377; + CONSTANT tpll_i1_q : NATURAL := 388; + CONSTANT tpll_i0_q : NATURAL := 389; + CONSTANT tphh_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x1; + +ARCHITECTURE behaviour_data_flow OF xr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x1" + SEVERITY WARNING; + q <= (i0 xor i1) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/xr2_x4.ap b/pdks/symbolic/nsxlib/cells/xr2_x4.ap new file mode 100644 index 000000000..310ab98ae --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/xr2_x4.ap @@ -0,0 +1,152 @@ +V ALLIANCE : 6 +H xr2_x4,P,26/ 9/2019,100 +A 0,0,12000,10000 +R 7000,6000,ref_ref,i1_30 +R 7000,7000,ref_ref,i1_35 +R 7000,8000,ref_ref,i1_40 +R 10000,3000,ref_ref,q_15 +R 10000,4000,ref_ref,q_20 +R 2000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i0_40 +R 7000,3000,ref_ref,i1_15 +R 7000,4000,ref_ref,i1_20 +R 7000,5000,ref_ref,i1_25 +R 2000,2000,ref_ref,i0_10 +R 2000,3000,ref_ref,i0_15 +R 2000,5000,ref_ref,i0_25 +R 2000,4000,ref_ref,i0_20 +R 2000,6000,ref_ref,i0_30 +R 10000,5000,ref_ref,q_25 +S 1200,5300,1200,5600,200,*,UP,POLY +S 1200,5200,2400,5200,200,*,RIGHT,POLY +S 2400,5200,2400,5500,200,*,UP,POLY +S 2400,2500,2400,2800,200,*,UP,POLY +S 1200,2500,1200,2800,200,*,UP,POLY +S 1200,2800,2400,2800,200,*,RIGHT,POLY +S 2000,2100,2000,7900,300,i0,UP,CALU1 +S 7000,3100,7000,7900,300,i1,UP,CALU1 +S 10000,2200,10000,7900,300,q,UP,CALU1 +S 10600,5500,10600,9500,200,*,UP,PTRANS +S 9000,4000,10600,4000,400,*,RIGHT,POLY +S 3600,2900,4100,2900,200,*,RIGHT,POLY +S 7200,2600,7200,2900,200,*,UP,POLY +S 6000,2600,6000,2900,200,*,UP,POLY +S 3600,5100,3600,5400,200,*,UP,POLY +S 7200,4900,7200,5300,200,*,UP,POLY +S 10600,2800,10600,5200,200,*,UP,POLY +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 3100,8000,5300,8000,300,*,RIGHT,ALU1 +S 4200,6100,4200,6900,300,*,UP,ALU1 +S 3100,6000,4100,6000,300,*,RIGHT,ALU1 +S 3000,2100,3000,5900,300,*,UP,ALU1 +S 3000,7100,3000,7900,300,*,UP,ALU1 +S 5400,6100,5400,7900,300,*,UP,ALU1 +S 9000,5700,9000,6700,200,*,UP,PDIF +S 9200,5700,9200,6600,200,*,UP,PDIF +S 3600,2600,3600,2900,200,*,UP,POLY +S 3600,5100,4100,5100,200,*,RIGHT,POLY +S 6000,2900,7200,2900,200,*,RIGHT,POLY +S 11300,800,11300,2300,400,*,UP,NDIF +S 10200,800,10200,2300,600,*,UP,NDIF +S 9600,600,9600,2500,200,*,UP,NTRANS +S 9000,800,9000,1900,600,*,UP,NDIF +S 5400,800,5400,2300,600,*,UP,NDIF +S 4800,600,4800,2500,200,*,UP,NTRANS +S 6000,600,6000,2500,200,*,UP,NTRANS +S 11200,1100,11200,1900,300,*,UP,ALU1 +S 11300,5700,11300,9300,400,*,UP,PDIF +S 7900,1700,7900,3100,400,*,UP,NDIF +S 800,2100,800,5900,300,*,UP,ALU1 +S 800,1700,800,2300,600,*,UP,NDIF +S 800,6100,800,6900,300,*,UP,ALU1 +S 1900,800,1900,2300,400,*,UP,NDIF +S 4200,800,4200,2300,600,*,UP,NDIF +S 6500,800,6500,2300,400,*,UP,NDIF +S 11200,6100,11200,8900,300,*,UP,ALU1 +S 9000,6100,9000,8900,300,*,UP,ALU1 +S 8800,5700,8800,6600,200,*,UP,PDIF +S 1200,5500,1200,7500,200,*,UP,PTRANS +S 10600,600,10600,2500,200,*,UP,NTRANS +S 800,4000,4800,4000,200,*,RIGHT,POLY +S 6400,5700,6400,9300,600,*,UP,PDIF +S 2000,5700,2000,9300,600,*,UP,PDIF +S 800,5700,800,7300,600,*,UP,PDIF +S 4800,2800,4800,5200,200,*,UP,POLY +S 6000,5500,6000,9500,200,*,UP,PTRANS +S 5400,5700,5400,9300,600,*,UP,PDIF +S 4800,5500,4800,9500,200,*,UP,PTRANS +S 4200,5700,4200,9300,600,*,UP,PDIF +S 2400,5500,2400,9500,200,*,UP,PTRANS +S 3000,5700,3000,9300,600,*,UP,PDIF +S 3600,5500,3600,9500,200,*,UP,PTRANS +S 7200,1500,7200,2500,200,*,UP,NTRANS +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 6000,4000,8000,4000,200,*,RIGHT,POLY +S 6000,4000,6000,5200,200,*,UP,POLY +S 4100,5000,6900,5000,300,*,RIGHT,ALU1 +S 4100,3000,4900,3000,300,*,RIGHT,ALU1 +S 5000,3100,5000,3900,300,*,UP,ALU1 +S 5100,4000,5900,4000,300,*,RIGHT,ALU1 +S 9600,5500,9600,9500,200,*,UP,PTRANS +S 7200,5500,7200,7500,200,*,UP,PTRANS +S 10200,5700,10200,9300,600,*,UP,PDIF +S 9000,6900,9000,9300,600,*,UP,PDIF +S 7800,5700,7800,7300,600,*,UP,PDIF +S 8000,3100,8000,5700,300,*,UP,ALU1 +S 7000,3100,7000,7900,300,*,UP,ALU1 +S 9600,2800,9600,5200,200,*,UP,POLY +S 9000,2100,9000,3900,300,*,UP,ALU1 +S 3100,2000,8900,2000,300,*,RIGHT,ALU1 +S -300,7800,12300,7800,6000,*,RIGHT,NWELL +S 10000,2100,10000,7900,300,*,UP,ALU1 +S 2400,600,2400,2500,200,*,UP,NTRANS +S 3000,800,3000,2300,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 0,600,12000,600,1200,vss,RIGHT,CALU1 +S 0,9400,12000,9400,1200,vdd,RIGHT,CALU1 +S 1000,8300,1000,9100,600,*,UP,NTIE +S 7800,8300,7800,9100,600,*,UP,NTIE +V 2000,5000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 7000,5000,CONT_POLY,* +V 1000,9200,CONT_BODY_N,* +V 2000,900,CONT_DIF_N,* +V 6400,900,CONT_DIF_N,* +V 9000,900,CONT_DIF_N,* +V 11200,900,CONT_DIF_N,* +V 9000,4000,CONT_POLY,* +V 8000,5800,CONT_DIF_P,* +V 8000,3000,CONT_DIF_N,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 6000,4000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +V 7000,3000,CONT_POLY,* +V 4200,7000,CONT_DIF_P,* +V 4200,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 5400,7000,CONT_DIF_P,* +V 5400,6000,CONT_DIF_P,* +V 7800,9200,CONT_BODY_N,* +V 9000,6000,CONT_DIF_P,* +V 11200,9200,CONT_DIF_P,* +V 11200,8000,CONT_DIF_P,* +V 11200,7000,CONT_DIF_P,* +V 11200,6000,CONT_DIF_P,* +V 11200,2000,CONT_DIF_N,* +V 9000,9200,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 800,4000,CONT_POLY,* +V 800,7000,CONT_DIF_P,* +V 800,6000,CONT_DIF_P,* +V 2000,9200,CONT_DIF_P,* +V 6400,9200,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,6000,CONT_DIF_P,* +V 10000,2000,CONT_DIF_N,* +V 4200,3000,CONT_POLY,* +V 4200,5000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/xr2_x4.vbe b/pdks/symbolic/nsxlib/cells/xr2_x4.vbe new file mode 100644 index 000000000..7e2da9edb --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/xr2_x4.vbe @@ -0,0 +1,36 @@ +ENTITY xr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 357; + CONSTANT tphh_i0_q : NATURAL := 476; + CONSTANT tpll_i0_q : NATURAL := 480; + CONSTANT tphl_i0_q : NATURAL := 521; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphl_i1_q : NATURAL := 541; + CONSTANT tplh_i0_q : NATURAL := 560; + CONSTANT tplh_i1_q : NATURAL := 657; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x4; + +ARCHITECTURE behaviour_data_flow OF xr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x4" + SEVERITY WARNING; + q <= (i0 xor i1) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib/cells/zero_x0.ap b/pdks/symbolic/nsxlib/cells/zero_x0.ap new file mode 100644 index 000000000..8b1484222 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/zero_x0.ap @@ -0,0 +1,36 @@ +V ALLIANCE : 6 +H zero_x0,P,26/ 9/2019,100 +A 0,0,3000,10000 +R 2000,2000,ref_ref,nq_10 +R 2000,3000,ref_ref,nq_15 +R 2000,4000,ref_ref,nq_20 +R 2000,5000,ref_ref,nq_25 +R 2000,6000,ref_ref,nq_30 +R 2000,7000,ref_ref,nq_35 +R 2000,8000,ref_ref,nq_40 +S 2000,2100,2000,7900,300,nq,UP,CALU1 +S 900,9000,2100,9000,600,*,RIGHT,NTIE +S 700,2700,700,3300,400,*,UP,NDIF +S 800,700,800,2900,300,*,UP,ALU1 +S 1000,4100,1000,9300,300,*,UP,ALU1 +S 1400,2500,1400,3500,200,*,UP,NTRANS +S 2000,2700,2000,3300,600,*,UP,NDIF +S -300,7800,3300,7800,6000,*,RIGHT,NWELL +S 2000,2100,2000,7900,300,*,UP,ALU1 +S 1400,3600,1400,4000,200,*,UP,POLY +S 700,1000,2100,1000,600,*,RIGHT,PTIE +S 0,600,3000,600,1200,vss,RIGHT,CALU1 +S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 +S 1000,5900,1000,9100,600,*,UP,NTIE +S 800,3900,1400,3900,400,*,RIGHT,POLY +V 2000,9100,CONT_BODY_N,* +V 2000,900,CONT_BODY_P,* +V 800,900,CONT_BODY_P,* +V 1000,8000,CONT_BODY_N,* +V 1000,7000,CONT_BODY_N,* +V 1000,6000,CONT_BODY_N,* +V 1000,4000,CONT_POLY,* +V 800,3000,CONT_DIF_N,* +V 2000,3000,CONT_DIF_N,* +V 1000,9000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib/cells/zero_x0.vbe b/pdks/symbolic/nsxlib/cells/zero_x0.vbe new file mode 100644 index 000000000..535efebc9 --- /dev/null +++ b/pdks/symbolic/nsxlib/cells/zero_x0.vbe @@ -0,0 +1,20 @@ +ENTITY zero_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END zero_x0; + +ARCHITECTURE behaviour_data_flow OF zero_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on zero_x0" + SEVERITY WARNING; + nq <= '0'; +END; diff --git a/pdks/symbolic/nsxlib2/cells/CATAL b/pdks/symbolic/nsxlib2/cells/CATAL new file mode 100644 index 000000000..76077fdd8 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/CATAL @@ -0,0 +1,94 @@ +a2_x2 C +a2_x4 C +a3_x2 C +a3_x4 C +a4_x2 C +a4_x4 C +an12_x1 C +an12_x4 C +ao22_x2 C +ao22_x4 C +ao2o22_x2 C +ao2o22_x4 C +buf_x2 C +buf_x4 C +buf_x8 C +inv_x1 C +inv_x2 C +inv_x4 C +inv_x8 C +mx2_x2 C +mx2_x4 C +mx3_x2 C +mx3_x4 C +na2_x1 C +na2_x4 C +na3_x1 C +na3_x4 C +na4_x1 C +na4_x4 C +nao22_x1 C +nao22_x4 C +nao2o22_x1 C +nao2o22_x4 C +nmx2_x1 C +nmx2_x4 C +nmx3_x1 C +no2_x1 C +no2_x4 C +no3_x1 C +no3_x4 C +no4_x1 C +no4_x4 C +noa22_x1 C +noa22_x4 C +noa2a22_x1 C +noa2a22_x4 C +noa2a2a23_x1 C +noa2a2a23_x4 C +noa2a2a2a24_x1 C +noa2a2a2a24_x4 C +noa2ao222_x1 C +noa2ao222_x4 C +noa3ao322_x1 C +noa3ao322_x4 C +nts_x1 C +nts_x2 C +nxr2_x1 C +nxr2_x4 C +o2_x2 C +o2_x4 C +o3_x2 C +o3_x4 C +o4_x2 C +o4_x4 C +oa22_x2 C +oa22_x4 C +oa2a22_x2 C +oa2a22_x4 C +oa2a2a23_x2 C +oa2a2a23_x4 C +oa2a2a2a24_x2 C +oa2a2a2a24_x4 C +oa2ao222_x2 C +oa2ao222_x4 C +oa3ao322_x2 C +oa3ao322_x4 C +on12_x1 C +on12_x4 C +one_x0 C +powmid_x0 C +powmid_x0 F +rowend_x0 C +rowend_x0 F +sff1_x4 C +sff1r_x4 C +sff1r2_x4 C +sff2_x4 C +tie_x0 C +tie_x0 F +ts_x4 C +ts_x8 C +xr2_x1 C +xr2_x4 C +zero_x0 C diff --git a/pdks/symbolic/nsxlib2/cells/a2_x2.ap b/pdks/symbolic/nsxlib2/cells/a2_x2.ap new file mode 100644 index 000000000..732b6658b --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a2_x2.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 6 +H a2_x2,P,15/ 8/2024,100 +A 0,0,5000,10000 +R 3000,4000,ref_ref,i1_35 +R 3000,7000,ref_ref,i1_25 +R 3000,5000,ref_ref,i1_20 +R 3000,3000,ref_ref,i1_15 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 3000,2000,ref_ref,i1_10 +R 1000,3000,ref_ref,i0_15 +R 3000,8000,ref_ref,i1_40 +R 3000,6000,ref_ref,i1_30 +R 4000,4000,ref_ref,q_20 +R 4000,3000,ref_ref,q_15 +R 4000,5000,ref_ref,q_25 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +S 1300,2400,1300,3000,200,*,UP,POLY +S 2500,5000,3000,5000,500,*,RIGHT,ALU1 +S 1000,6000,1400,6000,500,*,RIGHT,POLY +S 2500,3000,3100,3000,500,*,RIGHT,ALU1 +S 700,2000,1800,2000,300,*,RIGHT,ALU1 +S 1800,2000,1800,8100,300,*,UP,ALU1 +S 2900,5500,2900,9400,600,*,UP,PDIF +S 4000,1900,4000,8100,300,q,UP,CALU1 +S 4000,1900,4000,8100,300,*,UP,ALU1 +S 3000,1900,3000,8100,300,*,UP,ALU1 +S 3000,1900,3000,8100,300,i1,UP,CALU1 +S 1000,3100,1000,7100,300,i0,UP,CALU1 +S 1000,3100,1000,7100,300,*,UP,ALU1 +S 700,8200,700,9100,300,*,UP,ALU1 +S 0,500,5000,500,1400,vss,RIGHT,CALU1 +S 0,9500,5000,9500,1400,vdd,RIGHT,CALU1 +S 2400,2500,2400,3100,200,*,UP,POLY +S 4100,5500,4100,9400,600,*,UP,PDIF +S 1100,3000,1100,4100,200,*,UP,POLY +S 1000,3000,1400,3000,200,*,LEFT,POLY +S 1800,4000,3600,4000,200,*,RIGHT,POLY +S 3500,600,3500,2500,200,*,UP,NTRANS +S 3500,2500,3500,5600,200,*,UP,POLY +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 2300,4900,2300,6500,200,*,UP,POLY +S 2300,6500,2300,9400,200,*,UP,PTRANS +S 1300,6100,1300,6600,200,*,UP,POLY +S 1800,6500,1800,9400,600,*,UP,PDIF +S 700,6500,700,9400,600,*,UP,PDIF +S 1300,600,1300,2500,200,*,UP,NTRANS +S 1300,6500,1300,9400,200,*,UP,PTRANS +S 4100,600,4100,2500,600,*,UP,NDIF +S 3000,600,3000,2500,600,*,UP,NDIF +S 1800,600,1800,2500,600,*,UP,NDIF +S 800,600,800,2500,600,*,UP,NDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S -500,7500,5500,7500,6000,*,RIGHT,NWELL +S -200,10000,5200,10000,400,*,RIGHT,NTIE +S -200,0,5200,0,400,*,RIGHT,PTIE +B 1800,2000,200,200,CONT_TURN1,* +V 2500,5000,CONT_POLY,* +V 2500,3000,CONT_POLY,* +V 3000,9100,CONT_DIF_P,* +V 1800,4000,CONT_POLY,* +V 1800,8000,CONT_DIF_P,* +V 700,8300,CONT_DIF_P,* +V 700,9100,CONT_DIF_P,* +V 800,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 1000,6000,CONT_POLY,* +V 4000,8000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,6000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 3000,900,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/a2_x2.vbe b/pdks/symbolic/nsxlib2/cells/a2_x2.vbe new file mode 100644 index 000000000..8e6db7cd8 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i1_q : NATURAL := 203; + CONSTANT tphh_i0_q : NATURAL := 261; + CONSTANT tpll_i0_q : NATURAL := 388; + CONSTANT tpll_i1_q : NATURAL := 434; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x2; + +ARCHITECTURE behaviour_data_flow OF a2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x2" + SEVERITY WARNING; + q <= (i0 and i1) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/a2_x4.ap b/pdks/symbolic/nsxlib2/cells/a2_x4.ap new file mode 100644 index 000000000..6a8103e20 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a2_x4.ap @@ -0,0 +1,106 @@ +V ALLIANCE : 6 +H a2_x4,P,15/ 8/2024,100 +A 0,0,6000,10000 +R 3000,4000,ref_ref,i1_40 +R 3000,8000,ref_ref,i1_25 +R 3000,5000,ref_ref,i1_20 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 1000,7000,ref_ref,i0_35 +R 4000,5000,ref_ref,q_25 +R 3000,2000,ref_ref,i1_10 +R 3000,6000,ref_ref,i1_30 +R 3000,7000,ref_ref,i1_35 +R 4000,4000,ref_ref,q_20 +R 4000,3000,ref_ref,q_15 +S 1500,2400,1500,3000,200,*,UP,POLY +S 1000,2400,1000,3500,200,*,UP,POLY +S 400,2000,1900,2000,300,*,RIGHT,ALU1 +S 1800,1900,1800,8200,300,*,UP,ALU1 +S 600,3400,1100,3400,1000,*,RIGHT,ALU1 +S 500,3400,1000,3400,500,*,RIGHT,POLY +S 5000,900,5000,2100,300,*,UP,ALU1 +S 4000,1900,4000,8100,300,q,UP,CALU1 +S 3000,1900,3000,8100,300,*,UP,ALU1 +S 3000,1900,3000,8100,300,i1,UP,CALU1 +S 2700,5000,3100,5000,400,*,RIGHT,ALU1 +S 2700,3000,3100,3000,400,*,RIGHT,ALU1 +S 1400,8000,1900,8000,400,*,RIGHT,ALU1 +S 5000,5900,5000,9200,300,*,UP,ALU1 +S 500,7900,500,9200,300,*,UP,ALU1 +S 0,9500,6000,9500,1400,vdd,RIGHT,CALU1 +S 0,500,6000,500,1400,vss,RIGHT,CALU1 +S 4000,5500,4000,9400,600,*,UP,PDIF +S 2600,6500,2600,9400,600,*,UP,PDIF +S 500,6500,500,9400,400,*,UP,PDIF +S 1500,2900,2900,2900,200,*,RIGHT,POLY +S 1700,4000,4500,4000,200,*,RIGHT,POLY +S 1900,5100,2900,5100,200,*,RIGHT,POLY +S 4000,600,4000,2500,600,*,UP,NDIF +S 4500,600,4500,2500,200,*,UP,NTRANS +S 5000,600,5000,2500,600,*,UP,NDIF +S 4500,2500,4500,5500,200,*,UP,POLY +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 5000,5500,5000,9400,600,*,UP,PDIF +S 3500,600,3500,2500,200,*,UP,NTRANS +S 2800,600,2800,2500,600,*,UP,NDIF +S 2200,600,2200,2500,600,*,UP,NDIF +S 3500,2500,3500,5600,200,*,UP,POLY +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 2000,5000,2000,6500,200,*,UP,POLY +S 2000,6500,2000,9400,200,*,UP,PTRANS +S 1900,600,1900,2500,300,*,DOWN,NDIF +S 1500,600,1500,2500,200,*,UP,NTRANS +S 1500,6500,1500,9400,600,*,UP,PDIF +S 1000,5800,1000,6500,200,*,UP,POLY +S -500,7500,6500,7500,6000,*,RIGHT,NWELL +S 1000,6500,1000,9400,200,*,UP,PTRANS +S 1000,600,1000,2500,200,*,UP,NTRANS +S 400,600,400,2500,600,*,UP,NDIF +S 3100,5500,3100,9400,600,*,UP,PDIF +S 2500,600,2500,2500,600,*,UP,NDIF +S 1000,2800,1000,7200,300,i0,UP,ALU1 +S 1000,2800,1000,7200,300,i0,UP,CALU1 +S 3000,600,3000,2500,600,*,UP,NDIF +S -200,10000,6200,10000,400,*,RIGHT,NTIE +S -200,0,6200,0,400,*,RIGHT,PTIE +B 1800,2000,200,200,CONT_TURN1,* +V 2700,9100,CONT_DIF_P,* +V 1800,4000,CONT_POLY,* +V 2800,5000,CONT_POLY,* +V 2800,3000,CONT_POLY,* +V 5000,1000,CONT_DIF_N,* +V 5000,2000,CONT_DIF_N,* +V 5000,9100,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 3000,900,CONT_DIF_N,* +V 2000,900,CONT_DIF_N,* +V 700,3400,CONT_POLY,* +V 1500,8000,CONT_DIF_P,* +V 500,9100,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 4000,2000,CONT_DIF_N,* +V 4000,8000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,6000,CONT_DIF_P,* +V 1000,6000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/a2_x4.vbe b/pdks/symbolic/nsxlib2/cells/a2_x4.vbe new file mode 100644 index 000000000..f6955d6e9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphh_i0_q : NATURAL := 338; + CONSTANT tpll_i0_q : NATURAL := 476; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x4; + +ARCHITECTURE behaviour_data_flow OF a2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x4" + SEVERITY WARNING; + q <= (i0 and i1) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/a3_x2.ap b/pdks/symbolic/nsxlib2/cells/a3_x2.ap new file mode 100644 index 000000000..79744ce8f --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a3_x2.ap @@ -0,0 +1,100 @@ +V ALLIANCE : 6 +H a3_x2,P,14/ 8/2024,100 +A 0,0,6000,10000 +R 3000,5000,ref_ref,i2_20 +R 3000,4000,ref_ref,i2_25 +R 5000,8000,ref_ref,q_40 +R 5000,3000,ref_ref,q_15 +R 5000,2000,ref_ref,q_10 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 2000,3000,ref_ref,i1_15 +R 1000,3000,ref_ref,i0_15 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 3000,6000,ref_ref,i2_30 +R 5000,4000,ref_ref,q_20 +R 5000,5000,ref_ref,q_25 +R 5000,6000,ref_ref,q_30 +R 5000,7000,ref_ref,q_35 +R 3000,3000,ref_ref,i2_15 +S 5000,1900,5000,8100,300,q,UP,CALU1 +S 5000,1900,5000,8100,300,*,UP,ALU1 +S 400,2000,4100,2000,300,*,RIGHT,ALU1 +S 4000,1900,4000,7500,300,*,UP,ALU1 +S 400,7400,4100,7400,300,*,RIGHT,ALU1 +S 4000,8100,4000,9200,300,*,UP,ALU1 +S 1500,8100,1500,9200,300,*,UP,ALU1 +S 5000,5500,5000,9400,400,*,UP,PDIF +S 3500,6500,3500,9400,400,*,UP,PDIF +S 2500,6500,2500,9400,400,*,UP,PDIF +S 500,6500,500,9400,400,*,UP,PDIF +S 2500,600,2500,3500,400,*,UP,NDIF +S 1500,600,1500,3500,400,*,UP,NDIF +S 500,600,500,3500,400,*,UP,NDIF +S 3900,4000,4500,4000,200,*,RIGHT,POLY +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 4500,3500,4500,5500,200,*,UP,POLY +S 3900,600,3900,3500,800,*,UP,NDIF +S 4500,600,4500,3500,200,*,UP,NTRANS +S 3000,3500,3000,5600,200,*,UP,POLY +S 3500,600,3500,3500,400,*,UP,NDIF +S 3000,600,3000,3500,200,*,UP,NTRANS +S 3000,5600,3000,6500,200,*,UP,POLY +S 3000,6500,3000,9400,200,*,UP,PTRANS +S 2000,6000,2000,6600,200,*,UP,POLY +S 1500,6500,1500,9400,600,*,UP,PDIF +S 2000,6500,2000,9400,200,*,UP,PTRANS +S 1000,600,1000,3500,200,*,UP,NTRANS +S 1000,3500,1000,6500,200,*,UP,POLY +S 1000,6500,1000,9400,200,*,UP,PTRANS +S 5000,600,5000,3500,400,*,UP,NDIF +S 4000,5500,4000,9400,600,*,UP,PDIF +S 2000,3500,2000,6200,200,*,UP,POLY +S -200,9500,6200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,6200,500,1400,vss,RIGHT,CALU1 +S 1000,2800,1000,6000,300,*,UP,ALU1 +S 1000,2800,1000,6000,300,i0,UP,CALU1 +S 2000,2800,2000,6000,300,*,UP,ALU1 +S 2000,2800,2000,6000,300,i1,UP,CALU1 +S 3000,2800,3000,6000,300,*,UP,ALU1 +S 3000,2800,3000,6000,300,i2,UP,CALU1 +S 2000,600,2000,3500,200,*,UP,NTRANS +S -500,7500,6500,7500,6000,*,RIGHT,NWELL +S -200,10000,6200,10000,400,*,RIGHT,NTIE +S -200,0,6200,0,400,*,RIGHT,PTIE +V 2000,4000,CONT_POLY,* +B 4000,2000,200,200,CONT_TURN1,* +B 4000,7400,200,200,CONT_TURN1,* +V 3700,900,CONT_DIF_N,* +V 4000,9200,CONT_DIF_P,* +V 4000,8200,CONT_DIF_P,* +V 3800,4000,CONT_POLY,* +V 2500,7400,CONT_DIF_P,* +V 1500,9200,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 1500,8200,CONT_DIF_P,* +V 500,7400,CONT_DIF_P,* +V 3000,5000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 5000,2000,CONT_DIF_N,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/a3_x2.vbe b/pdks/symbolic/nsxlib2/cells/a3_x2.vbe new file mode 100644 index 000000000..7a7b521b3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 290; + CONSTANT tphh_i1_q : NATURAL := 353; + CONSTANT tphh_i0_q : NATURAL := 395; + CONSTANT tpll_i0_q : NATURAL := 435; + CONSTANT tpll_i1_q : NATURAL := 479; + CONSTANT tpll_i2_q : NATURAL := 521; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x2; + +ARCHITECTURE behaviour_data_flow OF a3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x2" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/a3_x4.ap b/pdks/symbolic/nsxlib2/cells/a3_x4.ap new file mode 100644 index 000000000..be0911014 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a3_x4.ap @@ -0,0 +1,109 @@ +V ALLIANCE : 6 +H a3_x4,P,14/ 8/2024,100 +A 0,0,7000,10000 +R 3000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,q_25 +R 5000,4000,ref_ref,q_20 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 5000,3000,ref_ref,q_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,3000,ref_ref,i0_15 +R 3000,5000,ref_ref,i2_25 +R 3000,4000,ref_ref,i2_20 +R 3000,3000,ref_ref,i2_15 +R 2000,3000,ref_ref,i1_15 +S 1500,600,1500,2500,600,*,UP,NDIF +S 6000,800,6000,2300,300,*,UP,ALU1 +S 5000,1900,5000,8100,300,*,UP,ALU1 +S 5000,1900,5000,8100,300,q,UP,CALU1 +S 4000,1900,4000,7100,300,*,UP,ALU1 +S 400,2000,4100,2000,300,*,RIGHT,ALU1 +S 6000,5900,6000,9200,300,*,UP,ALU1 +S 600,7000,4100,7000,300,*,RIGHT,ALU1 +S 1500,7700,1500,9200,300,*,UP,ALU1 +S -600,7500,7500,7500,6000,*,RIGHT,NWELL +S 600,600,600,2500,600,*,UP,NDIF +S 4000,5500,4000,9400,400,*,UP,PDIF +S 5000,5500,5000,9400,600,*,UP,PDIF +S 2600,600,2600,2500,600,*,UP,NDIF +S 3600,600,3600,2500,600,*,UP,NDIF +S 3900,600,3900,2500,600,*,UP,NDIF +S 6000,600,6000,2500,600,*,UP,NDIF +S 3800,4000,5500,4000,500,*,RIGHT,POLY +S 6000,5500,6000,9400,400,*,UP,PDIF +S 5000,600,5000,2500,600,*,UP,NDIF +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 5500,600,5500,2500,200,*,UP,NTRANS +S 5500,2500,5500,5500,200,*,UP,POLY +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 4500,2500,4500,5600,200,*,UP,POLY +S 4500,600,4500,2500,200,*,UP,NTRANS +S 4000,600,4000,2500,200,*,UP,NDIF +S 3600,6100,3600,8100,600,*,UP,PDIF +S 3000,2500,3000,5900,200,*,UP,POLY +S 3000,600,3000,2500,200,*,UP,NTRANS +S 3000,5600,3000,6200,200,*,UP,POLY +S 3000,6100,3000,8100,200,*,UP,PTRANS +S 2500,6100,2500,8100,600,*,UP,PDIF +S 1600,6100,1600,8100,600,*,UP,PDIF +S 2000,5100,2000,6100,200,*,UP,POLY +S 2000,6100,2000,8100,200,*,UP,PTRANS +S 2000,600,2000,2500,200,*,UP,NTRANS +S 1000,6100,1000,8100,200,*,UP,PTRANS +S 500,6100,500,8100,600,*,UP,PDIF +S 1000,2500,1000,6100,200,*,UP,POLY +S 1000,600,1000,2500,200,*,UP,NTRANS +S 1000,2800,1000,6200,300,*,UP,ALU1 +S 2000,2800,2000,6200,300,*,UP,ALU1 +S 3000,2800,3000,6200,300,*,UP,ALU1 +S 2000,2500,2000,5100,200,*,UP,POLY +S 1000,2800,1000,6200,300,i0,UP,CALU1 +S 3000,2800,3000,6200,300,i2,UP,CALU1 +S 2000,2800,2000,6200,300,i1,UP,CALU1 +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S -200,10000,7200,10000,400,*,RIGHT,NTIE +S -200,0,7200,0,400,*,RIGHT,PTIE +V 2000,4000,CONT_POLY,* +B 4000,7000,200,200,CONT_TURN1,* +B 4000,2000,200,200,CONT_TURN1,* +V 3700,900,CONT_DIF_N,* +V 6000,9100,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 6000,900,CONT_DIF_N,* +V 6000,2200,CONT_DIF_N,* +V 4000,9200,CONT_DIF_P,* +V 2500,7000,CONT_DIF_P,* +V 1500,7800,CONT_DIF_P,* +V 500,7000,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 5000,8000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/a3_x4.vbe b/pdks/symbolic/nsxlib2/cells/a3_x4.vbe new file mode 100644 index 000000000..556b6b0fc --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 356; + CONSTANT tphh_i1_q : NATURAL := 428; + CONSTANT tphh_i0_q : NATURAL := 478; + CONSTANT tpll_i0_q : NATURAL := 514; + CONSTANT tpll_i1_q : NATURAL := 554; + CONSTANT tpll_i2_q : NATURAL := 592; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x4; + +ARCHITECTURE behaviour_data_flow OF a3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x4" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/a4_x2.ap b/pdks/symbolic/nsxlib2/cells/a4_x2.ap new file mode 100644 index 000000000..a018d1539 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a4_x2.ap @@ -0,0 +1,122 @@ +V ALLIANCE : 6 +H a4_x2,P,20/12/2024,100 +A 0,0,7000,10000 +R 4000,5000,ref_ref,i3_25 +R 4000,6000,ref_ref,i3_30 +R 3000,6000,ref_ref,i2_30 +R 3000,4000,ref_ref,i2_20 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 6000,8000,ref_ref,q_40 +R 6000,7000,ref_ref,q_35 +R 6000,6000,ref_ref,q_30 +R 6000,5000,ref_ref,q_25 +R 6000,4000,ref_ref,q_20 +R 4000,4000,ref_ref,i3_20 +R 4000,3000,ref_ref,i3_15 +R 2000,6000,ref_ref,i1_30 +R 3000,5000,ref_ref,i2_25 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 6000,3000,ref_ref,q_15 +R 6000,2000,ref_ref,q_10 +R 2000,2000,ref_ref,i1_10 +R 3000,2000,ref_ref,i2_10 +R 2000,3000,ref_ref,i1_15 +R 3000,3000,ref_ref,i2_15 +S 3700,4000,4200,4000,500,*,RIGHT,POLY +S 4900,5500,4900,9400,600,*,UP,PDIF +S 4500,6500,4500,9400,600,*,UP,PDIF +S 3000,1900,3000,6200,300,*,UP,ALU1 +S 3000,1900,3000,6200,300,i2,UP,CALU1 +S 2000,1900,2000,6200,300,*,UP,ALU1 +S 2000,1900,2000,6200,300,i1,UP,CALU1 +S 1000,2900,1000,6200,300,i0,UP,CALU1 +S 1000,2900,1000,6200,300,*,UP,ALU1 +S 500,800,500,2300,300,*,UP,ALU1 +S 5100,2000,5100,7100,300,*,UP,ALU1 +S 4100,2000,5100,2000,300,*,RIGHT,ALU1 +S 4000,2900,4000,6200,300,*,UP,ALU1 +S 4000,2900,4000,6200,300,i3,UP,CALU1 +S 6000,1900,6000,8100,300,*,UP,ALU1 +S 6000,1900,6000,8100,300,q,UP,CALU1 +S 1400,7000,5200,7000,300,*,RIGHT,ALU1 +S 4700,7700,4700,8900,300,*,UP,ALU1 +S 2500,7800,2500,9100,300,*,UP,ALU1 +S 500,7800,500,9100,300,*,UP,ALU1 +S 4200,1500,4200,3500,400,*,UP,NDIF +S 3700,3500,3700,4100,200,*,UP,POLY +S 3700,1500,3700,3500,200,*,UP,NTRANS +S 5000,600,5000,3100,400,*,UP,NDIF +S 3500,6500,3500,9400,400,*,UP,PDIF +S 6000,600,6000,3100,400,*,UP,NDIF +S 2500,1500,2500,3500,400,*,UP,NDIF +S 500,1500,500,3500,400,*,UP,NDIF +S 5000,4500,5500,4500,500,*,RIGHT,POLY +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 5500,3100,5500,5500,200,*,UP,POLY +S 5500,600,5500,3100,200,*,UP,NTRANS +S 4000,3900,4000,6500,200,*,UP,POLY +S 4000,6500,4000,9400,200,*,UP,PTRANS +S 2500,6500,2500,9400,600,*,UP,PDIF +S 3400,1500,3400,3500,400,*,UP,NDIF +S 3000,3500,3000,5100,200,*,UP,POLY +S 3000,1500,3000,3500,200,*,UP,NTRANS +S 3000,4900,3000,6500,200,*,UP,POLY +S 3000,6500,3000,9400,200,*,UP,PTRANS +S 1000,3500,1000,6500,200,*,UP,POLY +S 1000,6500,1000,9400,200,*,UP,PTRANS +S 500,6500,500,9400,600,*,UP,PDIF +S 1000,1500,1000,3500,200,*,UP,NTRANS +S 1500,1500,1500,3500,400,*,UP,NDIF +S 1500,6500,1500,9400,400,*,UP,PDIF +S 2000,3500,2000,6500,200,*,UP,POLY +S 6000,5500,6000,9400,600,*,UP,PDIF +S 2000,6500,2000,9400,200,*,UP,PTRANS +S -500,7500,7500,7500,6000,*,RIGHT,NWELL +S -200,10000,7200,10000,400,*,RIGHT,NTIE +S -200,0,7200,0,400,*,RIGHT,PTIE +S 2000,1500,2000,3500,200,*,UP,NTRANS +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +V 3000,6000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +B 5100,2000,200,200,CONT_TURN1,* +B 5100,7000,200,200,CONT_TURN1,* +V 4700,7800,CONT_DIF_P,* +V 4700,9100,CONT_DIF_P,* +V 4200,2000,CONT_DIF_N,* +V 5000,900,CONT_DIF_N,* +V 3500,7000,CONT_DIF_P,* +V 2500,9100,CONT_DIF_P,* +V 2500,7900,CONT_DIF_P,* +V 1500,7000,CONT_DIF_P,* +V 500,9100,CONT_DIF_P,* +V 500,7900,CONT_DIF_P,* +V 500,2200,CONT_DIF_N,* +V 5100,4500,CONT_POLY,* +V 6000,2000,CONT_DIF_N,* +V 6000,6000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/a4_x2.vbe b/pdks/symbolic/nsxlib2/cells/a4_x2.vbe new file mode 100644 index 000000000..3a6353969 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 374; + CONSTANT tphh_i1_q : NATURAL := 441; + CONSTANT tpll_i3_q : NATURAL := 455; + CONSTANT tphh_i2_q : NATURAL := 482; + CONSTANT tpll_i2_q : NATURAL := 498; + CONSTANT tphh_i3_q : NATURAL := 506; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x2; + +ARCHITECTURE behaviour_data_flow OF a4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/a4_x4.ap b/pdks/symbolic/nsxlib2/cells/a4_x4.ap new file mode 100644 index 000000000..9435c0296 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a4_x4.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 6 +H a4_x4,P,16/ 8/2024,100 +A 0,0,8000,10000 +R 6000,5000,ref_ref,q_15 +R 6000,3000,ref_ref,q_25 +R 1000,5000,ref_ref,i0_25 +R 3000,4000,ref_ref,i2_20 +R 3000,3000,ref_ref,i2_15 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 6000,4000,ref_ref,q_20 +R 2000,2000,ref_ref,i1_10 +R 3000,2000,ref_ref,i2_10 +R 1000,4000,ref_ref,i0_20 +R 3000,6000,ref_ref,i2_30 +R 4000,6000,ref_ref,i3_30 +R 4000,5000,ref_ref,i3_25 +R 4000,4000,ref_ref,i3_20 +R 4000,3000,ref_ref,i3_15 +R 2000,6000,ref_ref,i1_30 +R 3000,5000,ref_ref,i2_25 +R 1000,6000,ref_ref,i0_30 +R 1000,3000,ref_ref,i0_15 +S 3600,3400,3600,4200,200,*,UP,POLY +S 4000,3800,4000,6600,200,*,UP,POLY +S 3600,4000,4000,4000,500,*,LEFT,POLY +S 3300,1500,3300,3500,400,*,UP,NDIF +S 4100,1500,4100,3500,400,*,UP,NDIF +S 3600,1500,3600,3500,200,*,UP,NTRANS +S 4000,2900,4000,6100,300,*,UP,ALU1 +S 4000,2900,4000,6100,300,i3,UP,CALU1 +S 3000,1900,3000,6100,300,i2,UP,CALU1 +S 3000,1900,3000,6100,300,*,UP,ALU1 +S 2000,1900,2000,6100,300,i1,UP,CALU1 +S 2000,1900,2000,6100,300,*,UP,ALU1 +S 1000,2900,1000,6100,300,*,UP,ALU1 +S 1000,2900,1000,6100,300,i0,UP,CALU1 +S 500,800,500,2100,300,*,UP,ALU1 +S 4100,2000,5100,2000,300,*,RIGHT,ALU1 +S 5100,2000,5100,7000,300,*,UP,ALU1 +S 6000,1900,6000,8100,300,*,UP,ALU1 +S 6000,1900,6000,8100,300,q,UP,CALU1 +S 7000,1100,7000,2400,300,*,UP,ALU1 +S 7000,5900,7000,9200,300,*,UP,ALU1 +S 1400,7000,5100,7000,300,*,RIGHT,ALU1 +S 4500,7800,4500,9200,300,*,DOWN,ALU1 +S 2500,7800,2500,9200,300,*,UP,ALU1 +S 500,7900,500,9200,300,*,UP,ALU1 +S 5000,900,5000,2800,500,*,UP,NDIF +S 7000,900,7000,2800,500,*,UP,NDIF +S 6500,900,6500,2800,200,*,UP,NTRANS +S 6000,900,6000,2800,500,*,UP,NDIF +S 5500,900,5500,2800,200,*,UP,NTRANS +S 5500,5000,6500,5000,400,*,RIGHT,POLY +S 1500,1500,1500,3500,400,*,UP,NDIF +S 500,1500,500,3500,600,*,UP,NDIF +S 7000,5500,7000,9400,400,*,UP,PDIF +S 6500,5500,6500,9400,200,*,UP,PTRANS +S 6500,2500,6500,5500,200,*,UP,POLY +S 4500,6500,4500,9400,600,*,UP,PDIF +S 4000,6500,4000,9400,200,*,UP,PTRANS +S 3500,6500,3500,9400,600,*,UP,PDIF +S 3000,3500,3000,6500,200,*,UP,POLY +S 3000,1500,3000,3500,200,*,UP,NTRANS +S 3000,6100,3000,6600,200,*,UP,POLY +S 3000,6500,3000,9400,200,*,UP,PTRANS +S 2500,6500,2500,9400,600,*,UP,PDIF +S 2000,6000,2000,6600,200,*,UP,POLY +S 2000,6500,2000,9400,200,*,UP,PTRANS +S 1600,6500,1600,9400,600,*,UP,PDIF +S 1000,6500,1000,9400,200,*,UP,PTRANS +S 1000,5000,1000,6500,200,*,UP,POLY +S 1000,3500,1000,5000,200,*,UP,POLY +S 1000,1500,1000,3500,200,*,UP,NTRANS +S 6000,5500,6000,9400,400,*,UP,PDIF +S 2500,1500,2500,3500,400,*,UP,NDIF +S 2000,3500,2000,6100,200,*,UP,POLY +S 5100,5500,5100,9400,400,*,UP,PDIF +S 4900,5500,4900,9400,400,*,UP,PDIF +S 5500,2500,5500,5500,200,*,UP,POLY +S 4800,4500,5500,4500,200,*,RIGHT,POLY +S 600,6500,600,9400,600,*,UP,PDIF +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 2000,1500,2000,3500,200,*,UP,NTRANS +S -500,7500,8500,7500,6000,*,RIGHT,NWELL +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,0,8200,0,400,*,RIGHT,PTIE +S -200,500,8200,500,1400,vss,RIGHT,CALU1 +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +V 3000,6000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 4100,2000,CONT_DIF_N,* +V 7000,1200,CONT_DIF_N,* +B 5100,2000,200,200,CONT_TURN1,* +B 5100,7000,200,200,CONT_TURN1,* +V 5000,1200,CONT_DIF_N,* +V 7000,2300,CONT_DIF_N,* +V 7000,6000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 7000,9100,CONT_DIF_P,* +V 4500,9100,CONT_DIF_P,* +V 4500,7900,CONT_DIF_P,* +V 3500,7000,CONT_DIF_P,* +V 2500,9100,CONT_DIF_P,* +V 2500,7900,CONT_DIF_P,* +V 1500,7000,CONT_DIF_P,* +V 500,9100,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 6000,2000,CONT_DIF_N,* +V 6000,6000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 4900,4500,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/a4_x4.vbe b/pdks/symbolic/nsxlib2/cells/a4_x4.vbe new file mode 100644 index 000000000..4f96afa4c --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/a4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 540; + CONSTANT rdown_i1_q : NATURAL := 540; + CONSTANT rdown_i2_q : NATURAL := 540; + CONSTANT rdown_i3_q : NATURAL := 540; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 505; + CONSTANT tpll_i3_q : NATURAL := 538; + CONSTANT tpll_i2_q : NATURAL := 576; + CONSTANT tphh_i1_q : NATURAL := 578; + CONSTANT tpll_i1_q : NATURAL := 614; + CONSTANT tphh_i2_q : NATURAL := 627; + CONSTANT tpll_i0_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 661; + CONSTANT transistors : NATURAL := 13 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x4; + +ARCHITECTURE behaviour_data_flow OF a4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/an12_x1.ap b/pdks/symbolic/nsxlib2/cells/an12_x1.ap new file mode 100644 index 000000000..2e7b47389 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/an12_x1.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H an12_x1,P,17/ 8/2024,100 +A 0,0,5000,10000 +R 3000,4000,ref_ref,i1_35 +R 3000,7000,ref_ref,i1_25 +R 3000,5000,ref_ref,i1_20 +R 3000,6000,ref_ref,i1_30 +R 3000,8000,ref_ref,i1_40 +R 2000,6000,ref_ref,i0_30 +R 2000,5000,ref_ref,i0_25 +R 2000,2000,ref_ref,q_10 +R 2000,8000,ref_ref,i0_40 +R 2000,7000,ref_ref,i0_35 +R 3000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,q_15 +R 1000,5000,ref_ref,q_25 +S 4200,600,4200,2500,800,*,UP,NDIF +S 4300,1900,4300,6000,400,*,UP,ALU1 +S 2500,4000,4300,4000,200,*,RIGHT,POLY +S 4300,6000,4300,8000,400,*,DOWN,ALU1 +S 3200,5200,3800,5200,200,*,LEFT,POLY +S 3700,5200,3700,5700,200,*,DOWN,POLY +S 3000,5500,3000,9400,800,*,UP,PDIF +S 2500,4900,2500,5500,200,*,UP,POLY +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 3700,5500,3700,9400,200,*,UP,PTRANS +S -500,7500,5600,7500,6000,*,RIGHT,NWELL +S 4200,5500,4200,9400,400,*,UP,PDIF +S 1500,2400,1500,4300,200,*,UP,POLY +S 2800,3000,3600,3000,500,*,RIGHT,ALU1 +S 1600,4000,2100,4000,400,*,RIGHT,ALU1 +S 3000,2900,3000,8100,300,i1,UP,CALU1 +S 3000,2900,3000,8100,300,*,UP,ALU1 +S 2000,3800,2000,8100,300,*,UP,ALU1 +S 2000,3800,2000,8100,300,i0,UP,CALU1 +S 1000,2900,1000,8100,300,q,UP,CALU1 +S 1000,2900,1000,8100,300,*,UP,ALU1 +S 1900,5500,1900,9400,600,*,UP,PDIF +S 3000,800,3000,2100,300,*,UP,ALU1 +S 900,3000,2000,3000,300,*,RIGHT,ALU1 +S 2000,1900,2000,3000,300,*,UP,ALU1 +S 1000,800,1000,2000,300,*,UP,ALU1 +S 2000,600,2000,2500,800,*,UP,NDIF +S 1100,600,1100,2500,600,*,UP,NDIF +S 1500,600,1500,2500,200,*,UP,NTRANS +S 3000,600,3000,2500,600,*,UP,NDIF +S 3500,2500,3500,3100,200,*,UP,POLY +S 3500,600,3500,2500,200,*,UP,NTRANS +S 2500,2500,2500,4900,200,*,UP,POLY +S 2500,600,2500,2500,200,*,UP,NTRANS +S 1500,3900,1500,5500,200,*,UP,POLY +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 1000,5500,1000,9400,600,*,UP,PDIF +S -200,10000,5200,10000,400,*,RIGHT,NTIE +S -200,0,5200,0,400,*,RIGHT,PTIE +S -200,500,5200,500,1400,vss,RIGHT,CALU1 +S -200,9500,5200,9500,1400,vdd,RIGHT,CALU1 +V 4300,2000,CONT_DIF_N,* +V 4300,4000,CONT_POLY,* +V 3300,5000,CONT_POLY,* +V 3100,9100,CONT_DIF_P,* +V 4300,6000,CONT_DIF_P,* +V 4300,7000,CONT_DIF_P,* +V 4300,8000,CONT_DIF_P,* +B 1000,3000,200,200,CONT_TURN1,* +B 2000,3000,200,200,CONT_TURN1,* +V 1000,900,CONT_DIF_N,* +V 1000,1900,CONT_DIF_N,* +V 1700,4000,CONT_POLY,* +V 3000,900,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 1000,6000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 3400,3000,CONT_POLY,* +V 2000,2000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/an12_x1.vbe b/pdks/symbolic/nsxlib2/cells/an12_x1.vbe new file mode 100644 index 000000000..10267b443 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/an12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 3640; + CONSTANT rdown_i1_q : NATURAL := 3640; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i0_q : NATURAL := 168; + CONSTANT tphl_i0_q : NATURAL := 200; + CONSTANT tphh_i1_q : NATURAL := 285; + CONSTANT tpll_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x1; + +ARCHITECTURE behaviour_data_flow OF an12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x1" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/an12_x4.ap b/pdks/symbolic/nsxlib2/cells/an12_x4.ap new file mode 100644 index 000000000..13b2ea9aa --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/an12_x4.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H an12_x4,P,16/ 8/2024,100 +A 0,0,7000,10000 +R 2000,4000,ref_ref,i0_35 +R 2000,7000,ref_ref,i0_25 +R 4000,4000,ref_ref,i1_35 +R 4000,7000,ref_ref,i1_25 +R 4000,5000,ref_ref,i1_20 +R 2000,5000,ref_ref,i0_20 +R 4000,3000,ref_ref,i1_15 +R 5000,3000,ref_ref,q_15 +R 5000,4000,ref_ref,q_20 +R 5000,5000,ref_ref,q_25 +R 4000,8000,ref_ref,i1_40 +R 4000,6000,ref_ref,i1_30 +R 4000,2000,ref_ref,i1_10 +R 2000,6000,ref_ref,i0_30 +R 2000,3000,ref_ref,i0_15 +S 5500,4000,5500,5700,200,*,DOWN,POLY +S 4500,4000,4500,5700,200,*,DOWN,POLY +S 1000,1900,1000,2300,200,*,UP,POLY +S 4800,2000,5600,2000,500,*,LEFT,ALU1 +S 1800,7900,1800,9200,400,*,UP,ALU1 +S 1500,5000,2000,5000,500,*,LEFT,ALU1 +S 2900,4000,3400,4000,400,*,LEFT,ALU1 +S 3600,5000,4100,5000,400,*,RIGHT,ALU1 +S 2000,2800,2000,7100,300,*,UP,ALU1 +S 2000,2800,2000,7100,300,i0,UP,CALU1 +S 900,2300,1800,2300,200,*,RIGHT,POLY +S 500,1600,500,8100,300,*,UP,ALU1 +S 1500,800,1500,1500,300,*,UP,ALU1 +S 3000,2000,3000,8100,300,*,UP,ALU1 +S 4000,1900,4000,8100,300,i1,UP,CALU1 +S 4000,1900,4000,8100,300,*,UP,ALU1 +S 6500,800,6500,2100,300,*,UP,ALU1 +S 6000,5900,6000,9200,300,*,UP,ALU1 +S 5000,1800,5000,8000,300,q,UP,CALU1 +S 5000,1800,5000,8000,300,*,UP,ALU1 +S 1700,2300,1700,3200,200,*,UP,POLY +S 500,4000,2600,4000,200,*,RIGHT,POLY +S 2500,2900,2500,4100,200,*,UP,POLY +S 2400,3000,3600,3000,200,*,RIGHT,POLY +S 3500,2400,3500,3100,200,*,UP,POLY +S 2500,3900,2500,5500,200,*,UP,POLY +S 6000,5500,6000,9400,400,*,UP,PDIF +S 3000,700,3000,2600,500,*,UP,NDIF +S 1500,900,1500,1900,400,*,UP,NDIF +S 500,5500,500,9400,400,*,UP,PDIF +S 4000,2500,4000,3200,200,*,DOWN,POLY +S 4000,5500,4000,9400,400,*,UP,PDIF +S 5500,700,5500,2600,400,*,UP,NDIF +S 5000,5500,5000,9400,600,*,UP,PDIF +S 900,5100,1700,5100,200,*,RIGHT,POLY +S 1000,5100,1000,5500,200,*,DOWN,POLY +S 1700,5500,1700,9400,1000,*,UP,PDIF +S 6500,700,6500,2600,400,*,UP,NDIF +S 6000,700,6000,2600,200,*,UP,NTRANS +S 5000,700,5000,2600,200,*,UP,NTRANS +S 4600,700,4600,2600,600,*,UP,NDIF +S 4000,700,4000,2600,200,*,UP,NTRANS +S 3500,700,3500,2600,200,*,UP,NTRANS +S -200,0,7200,0,400,*,RIGHT,PTIE +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S -500,7500,7500,7500,6000,*,RIGHT,NWELL +S -200,10000,7200,10000,400,*,RIGHT,NTIE +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +S 6000,2500,6000,4100,200,*,UP,POLY +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 3300,4000,6000,4000,200,*,RIGHT,POLY +S 5100,5500,5100,9400,400,*,UP,PDIF +S 5000,2500,5000,4000,200,*,UP,POLY +S 3500,4900,3500,5500,200,*,UP,POLY +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 3000,5500,3000,9400,600,*,UP,PDIF +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 1400,5500,1400,9400,600,*,UP,PDIF +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 1000,900,1000,1900,200,*,UP,NTRANS +S 600,900,600,1900,600,*,UP,NDIF +V 1800,9100,CONT_DIF_P,* +V 4100,3000,CONT_POLY,* +V 1900,3000,CONT_POLY,* +V 3200,4000,CONT_POLY,* +V 1500,1300,CONT_DIF_N,* +V 1800,8000,CONT_DIF_P,* +V 500,6600,CONT_DIF_P,* +V 3000,2100,CONT_DIF_N,* +V 6000,9100,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 6500,900,CONT_DIF_N,* +V 6500,2000,CONT_DIF_N,* +V 5500,2000,CONT_DIF_N,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 4500,900,CONT_DIF_N,* +V 3700,5000,CONT_POLY,* +V 4000,9100,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 1600,5000,CONT_POLY,* +V 500,8000,CONT_DIF_P,* +V 500,4000,CONT_POLY,* +V 500,1700,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/an12_x4.vbe b/pdks/symbolic/nsxlib2/cells/an12_x4.vbe new file mode 100644 index 000000000..0d030a6cb --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/an12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphl_i0_q : NATURAL := 461; + CONSTANT tplh_i0_q : NATURAL := 471; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x4; + +ARCHITECTURE behaviour_data_flow OF an12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x4" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/ao22_x2.ap b/pdks/symbolic/nsxlib2/cells/ao22_x2.ap new file mode 100644 index 000000000..80c95ff44 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ao22_x2.ap @@ -0,0 +1,110 @@ +V ALLIANCE : 6 +H ao22_x2,P,14/ 8/2024,100 +A 0,0,6000,10000 +R 5000,4000,ref_ref,q_20 +R 4000,6000,ref_ref,i2_30 +R 4000,5000,ref_ref,i2_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 1000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 5000,3000,ref_ref,q_15 +R 5000,2000,ref_ref,q_10 +R 2000,6000,ref_ref,i1_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 5000,8000,ref_ref,q_40 +R 5000,7000,ref_ref,q_35 +R 5000,6000,ref_ref,q_30 +R 5000,5000,ref_ref,q_25 +S 4000,2400,4000,3200,200,*,UP,POLY +S 2000,3900,2000,6300,200,*,UP,POLY +S 4400,2000,5200,2000,500,*,LEFT,ALU1 +S 3200,5800,4000,5800,200,*,RIGHT,POLY +S 4000,2800,4000,6200,400,*,DOWN,ALU1 +S 2700,6300,2700,9400,1000,*,UP,PDIF +S 400,1700,2600,1700,300,*,RIGHT,ALU1 +S 2800,2400,2800,7900,300,*,UP,ALU1 +S 1400,2400,2800,2400,300,*,RIGHT,ALU1 +S 3500,800,3500,2100,300,*,UP,ALU1 +S 5000,1900,5000,8100,300,q,UP,CALU1 +S 5000,1900,5000,8100,300,*,UP,ALU1 +S 4000,2800,4000,8100,300,i2,UP,CALU1 +S 4000,2800,4000,8100,300,*,UP,ALU1 +S 2000,4100,2000,8100,300,i1,UP,CALU1 +S 2000,4100,2000,8100,300,*,UP,ALU1 +S 1000,4100,1000,7100,300,i0,UP,CALU1 +S 1000,4100,1000,7100,300,*,UP,ALU1 +S 500,7900,500,9200,300,*,UP,ALU1 +S -600,7500,6500,7500,6000,*,RIGHT,NWELL +S 1500,6300,1500,9400,400,*,UP,PDIF +S 5000,6300,5000,9400,400,*,UP,PDIF +S 2500,700,2500,2600,500,*,UP,NDIF +S 4500,700,4500,2600,400,*,UP,NDIF +S 3300,5800,3300,6300,200,*,UP,POLY +S 2700,4400,4600,4400,200,*,RIGHT,POLY +S 3900,3200,4600,3200,200,*,RIGHT,POLY +S 4500,3200,4500,6300,200,*,UP,POLY +S 4500,6300,4500,9400,200,*,UP,PTRANS +S 4100,6300,4100,9400,400,*,UP,PDIF +S 2800,4400,2800,5200,200,*,UP,POLY +S 3900,6300,3900,9400,1000,*,UP,PDIF +S 3300,6300,3300,9400,200,*,UP,PTRANS +S 2900,3700,3800,3700,200,*,RIGHT,POLY +S 3000,2400,3000,3700,200,*,UP,POLY +S 4000,700,4000,2600,200,*,UP,NTRANS +S 3500,700,3500,2600,600,*,UP,NDIF +S 3000,700,3000,2600,200,*,UP,NTRANS +S 2000,2500,2000,3900,200,*,UP,POLY +S 2000,700,2000,2600,200,*,UP,NTRANS +S 1600,700,1600,2600,600,*,UP,NDIF +S 1000,6300,1000,9400,200,*,UP,PTRANS +S 500,6300,500,9400,400,*,UP,PDIF +S 1000,2500,1000,6400,200,*,UP,POLY +S 1000,700,1000,2600,200,*,UP,NTRANS +S 500,700,500,2600,400,*,UP,NDIF +S 4100,6300,4100,9400,600,*,UP,PDIF +S 2000,6300,2000,9400,200,*,UP,PTRANS +S -200,10000,6200,10000,400,*,RIGHT,NTIE +S -200,0,6200,0,400,*,RIGHT,PTIE +S -200,500,6200,500,1400,vss,RIGHT,CALU1 +S -200,9500,6200,9500,1400,vdd,RIGHT,CALU1 +V 3700,3800,CONT_POLY,* +V 3900,5700,CONT_POLY,* +B 2800,2400,200,200,CONT_TURN1,* +V 3800,9100,CONT_DIF_P,* +V 4500,2000,CONT_DIF_N,* +V 3500,2000,CONT_DIF_N,* +V 2500,1700,CONT_DIF_N,* +V 1500,2400,CONT_DIF_N,* +V 500,9100,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 500,1700,CONT_DIF_N,* +V 2800,5000,CONT_POLY,* +V 2800,6800,CONT_DIF_P,* +V 2800,7800,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/ao22_x2.vbe b/pdks/symbolic/nsxlib2/cells/ao22_x2.vbe new file mode 100644 index 000000000..7cfca61f3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ao22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 420; + CONSTANT tpll_i2_q : NATURAL := 425; + CONSTANT tpll_i0_q : NATURAL := 447; + CONSTANT tphh_i1_q : NATURAL := 493; + CONSTANT tpll_i1_q : NATURAL := 526; + CONSTANT tphh_i0_q : NATURAL := 558; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x2; + +ARCHITECTURE behaviour_data_flow OF ao22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/ao22_x4.ap b/pdks/symbolic/nsxlib2/cells/ao22_x4.ap new file mode 100644 index 000000000..7d4b09c84 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ao22_x4.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 6 +H ao22_x4,P,17/ 8/2024,100 +A 0,0,8000,10000 +R 4000,4000,ref_ref,i2_30 +R 4000,6000,ref_ref,i2_25 +R 4000,5000,ref_ref,i2_20 +R 6000,5000,ref_ref,q_25 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 6000,3000,ref_ref,q_15 +R 4000,3000,ref_ref,i2_15 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 6000,4000,ref_ref,q_20 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 6000,2000,ref_ref,q_10 +R 6000,8000,ref_ref,q_40 +R 6000,7000,ref_ref,q_35 +R 6000,6000,ref_ref,q_30 +S 1000,2500,1000,6300,200,*,UP,POLY +S 3200,5200,3200,6400,200,*,UP,POLY +S 2000,4000,2000,6300,200,*,UP,POLY +S 2600,4300,3100,4300,400,*,LEFT,ALU1 +S 4000,2900,4000,8100,300,i2,UP,CALU1 +S 4000,2900,4000,8100,300,*,UP,ALU1 +S 6000,1900,6000,8100,300,q,UP,CALU1 +S 6000,1900,6000,8100,300,*,UP,ALU1 +S 5000,6000,5000,9200,300,*,DOWN,ALU1 +S 7000,5900,7000,9200,300,*,UP,ALU1 +S 7000,800,7000,2100,300,*,UP,ALU1 +S 5000,800,5000,2100,300,*,UP,ALU1 +S 2700,2400,2700,7900,300,*,UP,ALU1 +S 1500,2400,2700,2400,300,*,RIGHT,ALU1 +S 400,1700,2800,1700,300,*,RIGHT,ALU1 +S 2000,4100,2000,8100,300,i1,UP,CALU1 +S 2000,4100,2000,8100,300,*,UP,ALU1 +S 1000,4100,1000,7100,300,i0,UP,CALU1 +S 1000,4100,1000,7100,300,*,UP,ALU1 +S 500,7900,500,9200,300,*,UP,ALU1 +S 2200,700,2200,2500,200,*,UP,NTRANS +S 500,700,500,2500,400,*,UP,NDIF +S 1000,700,1000,2500,200,*,UP,NTRANS +S 1400,700,1400,2600,200,*,UP,NDIF +S 1700,700,1700,2600,400,*,UP,NDIF +S 500,6300,500,8300,400,*,UP,PDIF +S 4000,6300,4000,8300,1000,*,UP,PDIF +S 3800,700,3800,2500,800,*,UP,NDIF +S 4700,700,4700,2500,1000,*,UP,NDIF +S 2900,4200,6600,4200,200,*,RIGHT,POLY +S 7000,5500,7000,9400,600,*,UP,PDIF +S 6900,700,6900,2500,600,*,UP,NDIF +S 6500,700,6500,2500,200,*,UP,NTRANS +S 6500,2400,6500,5500,200,*,UP,POLY +S 6500,5500,6500,9400,200,*,UP,PTRANS +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 5500,2300,5500,5500,200,*,UP,POLY +S 6100,700,6100,2500,600,*,UP,NDIF +S 5500,700,5500,2500,200,*,UP,NTRANS +S 3100,5200,4200,5200,200,*,RIGHT,POLY +S 3200,6300,3200,8300,200,*,UP,PTRANS +S 2700,6300,2700,8300,800,*,UP,PDIF +S 2000,6300,2000,8300,200,*,UP,PTRANS +S 1600,6300,1600,8300,600,*,UP,PDIF +S 3100,2900,4000,2900,200,*,RIGHT,POLY +S 3200,2400,3200,2900,200,*,UP,POLY +S 2800,700,2800,2500,400,*,UP,NDIF +S 3200,700,3200,2500,200,*,UP,NTRANS +S 2200,2500,2200,4100,200,*,UP,POLY +S 2600,700,2600,2500,200,*,UP,NDIF +S 1000,6300,1000,8300,200,*,UP,PTRANS +S 4900,5500,4900,9400,800,*,UP,PDIF +S 4900,5500,4900,9400,600,*,UP,PDIF +S 6000,5500,6000,9400,600,*,UP,PDIF +S -500,7500,8500,7500,6000,*,RIGHT,NWELL +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,0,8200,0,400,*,RIGHT,PTIE +S -200,500,8200,500,1400,vss,RIGHT,CALU1 +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +V 3000,4200,CONT_POLY,* +V 5000,8000,CONT_DIF_P,* +V 5000,9100,CONT_DIF_P,* +B 2700,2400,200,200,CONT_TURN1,* +V 7000,6000,CONT_DIF_P,* +V 7000,9100,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 7000,900,CONT_DIF_N,* +V 7000,2000,CONT_DIF_N,* +V 5000,6100,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 5000,900,CONT_DIF_N,* +V 3700,900,CONT_DIF_N,* +V 2700,6800,CONT_DIF_P,* +V 2700,7800,CONT_DIF_P,* +V 2700,1700,CONT_DIF_N,* +V 1600,2400,CONT_DIF_N,* +V 500,1700,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 6000,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 4000,3000,CONT_POLY,* +V 4000,5000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/ao22_x4.vbe b/pdks/symbolic/nsxlib2/cells/ao22_x4.vbe new file mode 100644 index 000000000..2995c9cca --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tpll_i2_q : NATURAL := 505; + CONSTANT tphh_i2_q : NATURAL := 526; + CONSTANT tpll_i0_q : NATURAL := 552; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 647; + CONSTANT tphh_i0_q : NATURAL := 674; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x4; + +ARCHITECTURE behaviour_data_flow OF ao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/ao2o22_x2.ap b/pdks/symbolic/nsxlib2/cells/ao2o22_x2.ap new file mode 100644 index 000000000..162422f1a --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ao2o22_x2.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 6 +H ao2o22_x2,P,27/ 9/2024,100 +A 0,0,8000,10000 +R 7000,3000,ref_ref,q_15 +R 7000,4000,ref_ref,q_20 +R 7000,5000,ref_ref,q_25 +R 7000,6000,ref_ref,q_30 +R 7000,7000,ref_ref,q_35 +R 7000,8000,ref_ref,q_40 +R 7000,2000,ref_ref,q_10 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 2000,4000,ref_ref,i1_20 +R 5000,7000,ref_ref,i3_35 +R 4000,7000,ref_ref,i2_35 +R 1000,7000,ref_ref,i0_35 +R 5000,3000,ref_ref,i3_15 +R 5000,4000,ref_ref,i3_20 +R 5000,5000,ref_ref,i3_25 +R 5000,6000,ref_ref,i3_30 +S 4100,6300,4100,9200,1200,*,UP,PDIF +S 2600,6300,2600,9200,800,*,UP,PDIF +S 2700,2400,2700,7800,300,*,UP,ALU1 +S 2600,7700,5700,7700,300,*,RIGHT,ALU1 +S 4700,2500,4700,4100,200,*,UP,POLY +S 5000,3900,5000,6400,200,*,UP,POLY +S 6000,8400,6000,9000,400,*,DOWN,ALU1 +S 5500,6300,5500,9200,800,*,UP,PDIF +S 5000,6300,5000,9200,200,*,UP,PTRANS +S 2200,2500,2200,4100,200,*,UP,POLY +S 2000,4000,2000,6300,200,*,UP,POLY +S 1500,6300,1500,9200,800,*,UP,PDIF +S 2000,6300,2000,9200,200,*,UP,PTRANS +S 5500,4000,6500,4000,500,*,RIGHT,ALU1 +S 7000,1900,7000,8100,300,q,UP,CALU1 +S 7000,1900,7000,8100,300,*,UP,ALU1 +S 5000,2900,5000,7100,300,*,UP,ALU1 +S 5000,2900,5000,7100,300,i3,UP,CALU1 +S 4000,2900,4000,7100,300,i2,UP,CALU1 +S 4000,2900,4000,7100,300,*,UP,ALU1 +S 2000,3800,2000,8100,300,*,UP,ALU1 +S 2000,3800,2000,8100,300,i1,UP,CALU1 +S 5700,4000,5700,7800,300,*,UP,ALU1 +S 6000,700,6000,2000,300,*,UP,ALU1 +S 600,1700,5300,1700,300,*,RIGHT,ALU1 +S 1700,2400,2700,2400,300,*,RIGHT,ALU1 +S 500,7900,500,9200,300,*,UP,ALU1 +S 1000,3800,1000,7200,300,i0,UP,CALU1 +S 1000,3800,1000,7200,300,*,UP,ALU1 +S 500,800,500,2500,400,*,UP,NDIF +S 1400,800,1400,2500,400,*,UP,NDIF +S 1000,800,1000,2500,200,*,UP,NTRANS +S 1800,800,1800,2500,400,*,UP,NDIF +S 1600,900,1600,2600,400,*,UP,NDIF +S 2200,800,2200,2500,200,*,UP,NTRANS +S 6000,600,6000,2500,400,*,UP,NDIF +S 5200,800,5200,2500,400,*,UP,NDIF +S 3900,800,3900,2500,1000,*,UP,NDIF +S 5900,5500,5900,9400,600,*,UP,PDIF +S 6500,600,6500,2500,200,*,UP,NTRANS +S 6500,2500,6500,5500,200,*,UP,POLY +S 6500,5500,6500,9400,200,*,UP,PTRANS +S 4700,800,4700,2500,200,*,UP,NTRANS +S 3100,4000,3900,4000,400,*,RIGHT,POLY +S 3200,6300,3200,9200,200,*,UP,PTRANS +S 3200,2500,3200,6300,200,*,UP,POLY +S 3200,800,3200,2500,200,*,UP,NTRANS +S 2800,800,2800,2500,600,*,UP,NDIF +S 1000,6300,1000,9200,200,*,UP,PTRANS +S 500,6300,500,9200,400,*,UP,PDIF +S 1000,2500,1000,6400,200,*,UP,POLY +S 7000,600,7000,2500,400,*,UP,NDIF +S -200,0,8200,0,400,*,RIGHT,PTIE +S -200,500,8200,500,1400,vss,RIGHT,CALU1 +S -500,7500,8500,7500,6000,*,RIGHT,NWELL +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +S 7000,5500,7000,9400,600,*,UP,PDIF +V 2700,7700,CONT_DIF_P,* +B 5700,7700,200,200,CONT_TURN1,* +V 6000,8400,CONT_DIF_P,* +V 500,8900,CONT_DIF_P,* +V 6000,1000,CONT_DIF_N,* +V 6000,9000,CONT_DIF_P,* +B 2700,2400,200,200,CONT_TURN1,* +B 5700,4000,200,200,CONT_TURN1,* +V 4000,1000,CONT_DIF_N,* +V 4900,4000,CONT_POLY,* +V 6000,1900,CONT_DIF_N,* +V 5200,1700,CONT_DIF_N,* +V 2700,6800,CONT_DIF_P,* +V 2700,1700,CONT_DIF_N,* +V 1600,2400,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 500,1700,CONT_DIF_N,* +V 7000,6000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 6300,4000,CONT_POLY,* +V 7000,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/ao2o22_x2.vbe b/pdks/symbolic/nsxlib2/cells/ao2o22_x2.vbe new file mode 100644 index 000000000..c503d1b97 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ao2o22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 432; + CONSTANT tpll_i0_q : NATURAL := 451; + CONSTANT tphh_i3_q : NATURAL := 488; + CONSTANT tphh_i1_q : NATURAL := 508; + CONSTANT tpll_i3_q : NATURAL := 526; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tphh_i0_q : NATURAL := 572; + CONSTANT tpll_i2_q : NATURAL := 627; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x2; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/ao2o22_x4.ap b/pdks/symbolic/nsxlib2/cells/ao2o22_x4.ap new file mode 100644 index 000000000..df351962f --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ao2o22_x4.ap @@ -0,0 +1,148 @@ +V ALLIANCE : 6 +H ao2o22_x4,P,20/12/2024,100 +A 0,0,9000,10000 +R 5000,3000,ref_ref,i3_15 +R 5000,5000,ref_ref,i3_25 +R 4000,5000,ref_ref,i2_20 +R 4000,4000,ref_ref,i2_25 +R 7000,2000,ref_ref,q_10 +R 7000,3000,ref_ref,q_15 +R 7000,4000,ref_ref,q_20 +R 7000,5000,ref_ref,q_25 +R 7000,6000,ref_ref,q_30 +R 7000,7000,ref_ref,q_35 +R 7000,8000,ref_ref,q_40 +R 2000,8000,ref_ref,i1_40 +R 5000,6000,ref_ref,i3_30 +R 4000,6000,ref_ref,i2_30 +R 4000,3000,ref_ref,i2_15 +R 2000,4000,ref_ref,i1_20 +R 2000,7000,ref_ref,i1_35 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 5000,4000,ref_ref,i3_20 +R 1000,7000,ref_ref,i0_35 +R 4000,7000,ref_ref,i2_35 +R 5000,7000,ref_ref,i3_35 +S 3900,3000,5000,3000,200,*,RIGHT,POLY +S 3000,2500,3000,2900,200,*,UP,POLY +S 4900,6500,4900,9400,1200,*,UP,PDIF +S 3600,6500,3600,9400,600,*,UP,PDIF +S 4700,800,4700,2600,800,*,UP,NDIF +S 3200,2900,3200,6700,200,*,UP,POLY +S 2900,2900,3300,2900,200,*,LEFT,POLY +S 5900,5500,5900,9400,1000,*,UP,PDIF +S 3900,6000,5100,6000,200,*,RIGHT,POLY +S 5000,2900,5000,6000,200,*,UP,POLY +S 4000,2600,4000,3000,200,*,UP,POLY +S 3500,800,3500,2600,800,*,UP,NDIF +S 4000,800,4000,2600,200,*,UP,NTRANS +S 3000,800,3000,2600,200,*,UP,NTRANS +S 4000,6000,4000,6600,200,*,UP,POLY +S 4000,6500,4000,9400,200,*,UP,PTRANS +S 7500,2500,7500,5500,200,*,UP,POLY +S 5700,4000,6100,4000,300,*,RIGHT,ALU1 +S 5900,4000,7500,4000,500,*,RIGHT,POLY +S 1600,2400,2700,2400,300,*,RIGHT,ALU1 +S 2700,2400,2700,8000,300,*,UP,ALU1 +S 4000,2900,4000,7100,300,i2,UP,CALU1 +S 4000,2900,4000,7100,300,*,UP,ALU1 +S 5000,2900,5000,7100,300,i3,UP,CALU1 +S 5000,2900,5000,7100,300,*,UP,ALU1 +S 7000,1900,7000,8100,300,*,UP,ALU1 +S 7000,1900,7000,8100,300,q,UP,CALU1 +S 6000,1200,6000,2100,300,*,UP,ALU1 +S 8000,1200,8000,2100,300,*,UP,ALU1 +S 5700,4000,5700,7900,300,*,UP,ALU1 +S 8000,5900,8000,8800,300,*,UP,ALU1 +S 2000,3800,2000,8100,300,i1,UP,CALU1 +S 2000,3800,2000,8100,300,*,UP,ALU1 +S 1000,3800,1000,7100,300,*,UP,ALU1 +S 1000,3800,1000,7100,300,i0,UP,CALU1 +S 2800,7900,5700,7900,300,*,RIGHT,ALU1 +S 500,7900,500,9200,300,*,UP,ALU1 +S 1500,800,1500,2600,800,*,UP,NDIF +S 8000,700,8000,2600,400,*,UP,NDIF +S 500,6500,500,9400,400,*,UP,PDIF +S 6000,700,6000,2600,400,*,UP,NDIF +S 500,800,500,2600,400,*,UP,NDIF +S 2600,800,2600,2600,600,*,UP,NDIF +S 2600,6500,2600,9400,600,*,UP,PDIF +S 7000,700,7000,2600,400,*,UP,NDIF +S 7500,700,7500,2600,200,*,UP,NTRANS +S 6500,700,6500,2600,200,*,UP,NTRANS +S 7500,5500,7500,9400,200,*,UP,PTRANS +S 6500,2500,6500,5500,200,*,UP,POLY +S 6500,5500,6500,9400,200,*,UP,PTRANS +S 3200,5000,4000,5000,400,*,RIGHT,POLY +S 600,1700,4800,1700,300,*,RIGHT,ALU1 +S 3200,6500,3200,9400,200,*,UP,PTRANS +S 2000,6500,2000,9400,200,*,UP,PTRANS +S 1600,6500,1600,9400,600,*,UP,PDIF +S 2000,2500,2000,6500,200,*,UP,POLY +S 2000,800,2000,2600,200,*,UP,NTRANS +S 1000,800,1000,2600,200,*,UP,NTRANS +S 1000,2500,1000,6500,200,*,UP,POLY +S 1000,6500,1000,9400,200,*,UP,PTRANS +S 7000,5500,7000,9400,400,*,UP,PDIF +S -200,0,9200,0,400,*,RIGHT,PTIE +S -200,500,9200,500,1400,vss,RIGHT,CALU1 +S -500,7500,9500,7500,6000,*,RIGHT,NWELL +S -200,10000,9200,10000,400,*,RIGHT,NTIE +S -200,9500,9200,9500,1400,vdd,RIGHT,CALU1 +S 8000,5500,8000,9400,600,*,UP,PDIF +V 8000,9000,CONT_DIF_P,* +V 6000,9000,CONT_DIF_P,* +V 4700,9000,CONT_DIF_P,* +V 3500,900,CONT_DIF_N,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +B 5900,4000,600,400,CONT_TURN1,* +V 6000,4000,CONT_POLY,* +B 2700,2400,200,200,CONT_TURN1,* +B 5700,7900,200,200,CONT_TURN1,* +V 8000,8000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 8000,900,CONT_DIF_N,* +V 8000,2000,CONT_DIF_N,* +V 6000,900,CONT_DIF_N,* +V 6000,2000,CONT_DIF_N,* +V 4000,5000,CONT_POLY,* +V 4700,1700,CONT_DIF_N,* +V 2500,1700,CONT_DIF_N,* +V 2700,7000,CONT_DIF_P,* +V 2700,7900,CONT_DIF_P,* +V 1500,2400,CONT_DIF_N,* +V 500,1700,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 500,9000,CONT_DIF_P,* +V 7000,2000,CONT_DIF_N,* +V 7000,6000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 5000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/ao2o22_x4.vbe b/pdks/symbolic/nsxlib2/cells/ao2o22_x4.vbe new file mode 100644 index 000000000..61a5bff61 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 554; + CONSTANT tpll_i0_q : NATURAL := 569; + CONSTANT tphh_i3_q : NATURAL := 606; + CONSTANT tphh_i1_q : NATURAL := 637; + CONSTANT tpll_i3_q : NATURAL := 639; + CONSTANT tpll_i1_q : NATURAL := 666; + CONSTANT tphh_i0_q : NATURAL := 696; + CONSTANT tpll_i2_q : NATURAL := 744; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/buf_x2.ap b/pdks/symbolic/nsxlib2/cells/buf_x2.ap new file mode 100644 index 000000000..cecc4c45c --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/buf_x2.ap @@ -0,0 +1,67 @@ +V ALLIANCE : 6 +H buf_x2,P,16/ 8/2024,100 +A 0,0,4000,10000 +R 2000,4000,ref_ref,i_35 +R 2000,7000,ref_ref,i_25 +R 2000,5000,ref_ref,i_20 +R 3000,3000,ref_ref,q_15 +R 3000,5000,ref_ref,q_25 +R 3000,2000,ref_ref,q_10 +R 2000,3000,ref_ref,i_15 +R 2000,2000,ref_ref,i_10 +R 2000,6000,ref_ref,i_30 +R 3000,4000,ref_ref,q_20 +R 2000,8000,ref_ref,i_40 +R 3000,8000,ref_ref,q_40 +R 3000,7000,ref_ref,q_35 +R 3000,6000,ref_ref,q_30 +S 1900,5500,1900,9400,800,*,UP,PDIF +S 1600,1700,1600,2600,600,*,UP,NDIF +S 1000,1700,1000,2600,200,*,UP,NTRANS +S 1600,5500,1600,6700,1000,*,UP,PDIF +S 3000,1900,3000,8100,300,*,UP,ALU1 +S 3000,1900,3000,8100,300,q,UP,CALU1 +S 2000,1900,2000,8100,300,i,UP,CALU1 +S 2000,1900,2000,8100,300,*,UP,ALU1 +S 500,2100,500,6100,300,*,UP,ALU1 +S 500,2000,500,2600,400,*,UP,NDIF +S 500,5500,500,6700,400,*,UP,PDIF +S 2000,700,2000,2600,400,*,UP,NDIF +S 400,4000,2500,4000,400,*,RIGHT,POLY +S 900,5100,1900,5100,200,*,RIGHT,POLY +S 900,3100,1900,3100,200,*,RIGHT,POLY +S 1000,2600,1000,3100,200,*,UP,POLY +S 2500,700,2500,2600,200,*,UP,NTRANS +S 3100,700,3100,2600,600,*,UP,NDIF +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 2500,2500,2500,5600,200,*,UP,POLY +S 1000,5000,1000,5500,200,*,UP,POLY +S 1000,5500,1000,6700,200,*,UP,PTRANS +S 3000,5500,3000,9400,600,*,UP,PDIF +S -200,9500,4200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,4200,500,1400,vss,RIGHT,CALU1 +S -500,7500,4500,7500,6000,*,RIGHT,NWELL +S -200,10000,4200,10000,400,*,RIGHT,NTIE +S -200,0,4200,0,400,*,RIGHT,PTIE +V 1800,3000,CONT_POLY,* +V 1800,5000,CONT_POLY,* +V 2000,9100,CONT_DIF_P,* +V 2000,900,CONT_DIF_N,* +V 500,2200,CONT_DIF_N,* +V 500,4000,CONT_POLY,* +V 500,6000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/buf_x2.vbe b/pdks/symbolic/nsxlib2/cells/buf_x2.vbe new file mode 100644 index 000000000..e2e4c344e --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/buf_x2.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 6; + CONSTANT rdown_i_q : NATURAL := 1620; + CONSTANT rup_i_q : NATURAL := 1790; + CONSTANT tpll_i_q : NATURAL := 391; + CONSTANT tphh_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x2; + +ARCHITECTURE behaviour_data_flow OF buf_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x2" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/buf_x4.ap b/pdks/symbolic/nsxlib2/cells/buf_x4.ap new file mode 100644 index 000000000..05b4ae795 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/buf_x4.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H buf_x4,P,16/ 8/2024,100 +A 0,0,5000,10000 +R 2000,4000,ref_ref,i_35 +R 2000,7000,ref_ref,i_25 +R 2000,5000,ref_ref,i_20 +R 3000,6000,ref_ref,q_30 +R 3000,7000,ref_ref,q_35 +R 3000,8000,ref_ref,q_40 +R 2000,8000,ref_ref,i_40 +R 3000,4000,ref_ref,q_20 +R 2000,6000,ref_ref,i_30 +R 2000,2000,ref_ref,i_10 +R 2000,3000,ref_ref,i_15 +R 3000,2000,ref_ref,q_10 +R 3000,5000,ref_ref,q_25 +R 3000,3000,ref_ref,q_15 +S 2000,5500,2000,9300,800,*,UP,PDIF +S 500,1900,500,7100,300,*,UP,ALU1 +S 2000,1900,2000,8100,300,i,UP,CALU1 +S 2000,1900,2000,8100,300,*,UP,ALU1 +S 3000,1900,3000,8100,300,*,UP,ALU1 +S 3000,1900,3000,8100,300,q,UP,CALU1 +S 4000,800,4000,2100,300,*,UP,ALU1 +S 4000,5900,4000,9200,300,*,UP,ALU1 +S 2000,700,2000,2500,400,*,UP,NDIF +S 4000,700,4000,2500,400,*,UP,NDIF +S 500,1500,500,2500,400,*,UP,NDIF +S 500,5500,500,7500,400,*,UP,PDIF +S 1600,1500,1600,2500,800,*,UP,NDIF +S 1600,5500,1600,7500,800,*,UP,PDIF +S 900,4900,1900,4900,200,*,RIGHT,POLY +S 900,3100,1900,3100,200,*,RIGHT,POLY +S 3000,700,3000,2500,800,*,UP,NDIF +S 3500,700,3500,2500,200,*,UP,NTRANS +S 2500,700,2500,2500,200,*,UP,NTRANS +S 3500,2500,3500,5500,200,*,UP,POLY +S 3500,5500,3500,9300,200,*,UP,PTRANS +S 2500,5500,2500,9300,200,*,UP,PTRANS +S 2500,2500,2500,5500,200,*,UP,POLY +S 1000,4800,1000,5600,200,*,UP,POLY +S 1000,5500,1000,7500,200,*,UP,PTRANS +S 1000,2500,1000,3200,200,*,UP,POLY +S 1000,1500,1000,2500,200,*,UP,NTRANS +S 2900,5500,2900,9300,600,*,UP,PDIF +S 600,4000,3500,4000,400,*,RIGHT,POLY +S 4000,5500,4000,9300,600,*,UP,PDIF +S -500,7500,5500,7500,6000,*,RIGHT,NWELL +S -200,10000,5200,10000,400,*,RIGHT,NTIE +S -200,0,5200,0,400,*,RIGHT,PTIE +S -200,500,5200,500,1400,vss,RIGHT,CALU1 +S -200,9500,5200,9500,1400,vdd,RIGHT,CALU1 +V 4000,900,CONT_DIF_N,* +V 4000,2000,CONT_DIF_N,* +V 1800,3000,CONT_POLY,* +V 1800,5000,CONT_POLY,* +V 4000,9100,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,6000,CONT_DIF_P,* +V 2000,9100,CONT_DIF_P,* +V 2000,900,CONT_DIF_N,* +V 500,2000,CONT_DIF_N,* +V 500,4000,CONT_POLY,* +V 500,6000,CONT_DIF_P,* +V 500,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/buf_x4.vbe b/pdks/symbolic/nsxlib2/cells/buf_x4.vbe new file mode 100644 index 000000000..0b7726ef9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/buf_x4.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i : NATURAL := 9; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphh_i_q : NATURAL := 379; + CONSTANT tpll_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x4; + +ARCHITECTURE behaviour_data_flow OF buf_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x4" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/buf_x8.ap b/pdks/symbolic/nsxlib2/cells/buf_x8.ap new file mode 100644 index 000000000..e361a96da --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/buf_x8.ap @@ -0,0 +1,113 @@ +V ALLIANCE : 6 +H buf_x8,P,16/ 8/2024,100 +A 0,0,7000,10000 +R 2000,4000,ref_ref,i_35 +R 2000,7000,ref_ref,i_25 +R 2000,5000,ref_ref,i_20 +R 2000,2000,ref_ref,i_10 +R 2000,8000,ref_ref,i_40 +R 2000,6000,ref_ref,i_30 +R 2000,3000,ref_ref,i_15 +R 3000,8000,ref_ref,q_40 +R 3000,2000,ref_ref,q_10 +R 3000,5000,ref_ref,q_25 +R 3000,3000,ref_ref,q_15 +R 3000,4000,ref_ref,q_20 +R 3000,6000,ref_ref,q_30 +R 3000,7000,ref_ref,q_35 +S 2000,2800,2000,5200,400,*,DOWN,ALU1 +S 3000,4000,5000,4000,300,*,RIGHT,ALU1 +S 500,1900,500,8100,300,*,UP,ALU1 +S 2000,1900,2000,8100,300,i,UP,CALU1 +S 2000,1900,2000,8100,300,*,UP,ALU1 +S 3000,1900,3000,8100,300,q,UP,CALU1 +S 3000,1900,3000,8100,300,*,UP,ALU1 +S 4000,800,4000,2100,300,*,UP,ALU1 +S 5000,1900,5000,8100,300,*,UP,ALU1 +S 6000,800,6000,2100,300,*,UP,ALU1 +S 6000,5900,6000,9200,300,*,UP,ALU1 +S 4000,5900,4000,9200,300,*,UP,ALU1 +S 6000,600,6000,2500,400,*,UP,NDIF +S 4000,5500,4000,9400,600,*,UP,PDIF +S 5000,600,5000,2500,400,*,UP,NDIF +S 1000,4800,1000,5500,200,*,UP,POLY +S -500,7500,7500,7500,6000,*,RIGHT,NWELL +S -200,10000,7200,10000,400,*,RIGHT,NTIE +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +S -200,0,7200,0,400,*,RIGHT,PTIE +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S 5000,5500,5000,9400,600,*,UP,PDIF +S 5900,5500,5900,9400,600,*,UP,PDIF +S 600,4000,5500,4000,400,*,RIGHT,POLY +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 4000,600,4000,2500,400,*,UP,NDIF +S 4500,600,4500,2500,200,*,UP,NTRANS +S 5500,2500,5500,5500,200,*,UP,POLY +S 4500,2500,4500,5500,200,*,UP,POLY +S 5500,600,5500,2500,200,*,UP,NTRANS +S 900,4900,1900,4900,200,*,LEFT,POLY +S 900,2900,1900,2900,200,*,LEFT,POLY +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 3500,2500,3500,5500,200,*,UP,POLY +S 3500,600,3500,2500,200,*,UP,NTRANS +S 2500,600,2500,2500,200,*,UP,NTRANS +S 2500,2500,2500,5500,200,*,UP,POLY +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 1000,2500,1000,3000,200,*,UP,POLY +S 1600,600,1600,2500,600,*,UP,NDIF +S 1500,5500,1500,9400,600,*,UP,PDIF +S 1000,600,1000,2500,200,*,UP,NTRANS +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 500,5500,500,9400,400,*,UP,PDIF +S 500,600,500,2500,400,*,UP,NDIF +S 2100,5500,2100,9400,600,*,UP,PDIF +S 3000,600,3000,2500,400,*,UP,NDIF +S 2100,600,2100,2500,400,*,UP,NDIF +S 3000,5500,3000,9400,600,*,UP,PDIF +V 7000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 4000,9100,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 6000,9200,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 6000,2000,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 6000,900,CONT_DIF_N,* +V 5000,2000,CONT_DIF_N,* +V 4000,2000,CONT_DIF_N,* +V 1800,5000,CONT_POLY,* +V 1800,3000,CONT_POLY,* +V 1500,900,CONT_DIF_N,* +V 1500,9100,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 500,4000,CONT_POLY,* +V 500,6000,CONT_DIF_P,* +V 500,7000,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/buf_x8.vbe b/pdks/symbolic/nsxlib2/cells/buf_x8.vbe new file mode 100644 index 000000000..3b2ecc3bb --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/buf_x8.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i : NATURAL := 15; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphh_i_q : NATURAL := 343; + CONSTANT tpll_i_q : NATURAL := 396; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x8; + +ARCHITECTURE behaviour_data_flow OF buf_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x8" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/inv_x1.ap b/pdks/symbolic/nsxlib2/cells/inv_x1.ap new file mode 100644 index 000000000..7348939d9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/inv_x1.ap @@ -0,0 +1,51 @@ +V ALLIANCE : 6 +H inv_x1,P,11/ 6/2024,100 +A 0,0,3000,10000 +R 1000,7000,ref_ref,i_35 +R 1000,6000,ref_ref,i_30 +R 1000,5000,ref_ref,i_25 +R 1000,3000,ref_ref,i_15 +R 1000,4000,ref_ref,i_20 +R 2000,2000,ref_ref,nq_10 +R 2000,3000,ref_ref,nq_15 +R 2000,4000,ref_ref,nq_20 +R 2000,5000,ref_ref,nq_25 +R 2000,6000,ref_ref,nq_30 +R 2000,7000,ref_ref,nq_35 +R 2000,8000,ref_ref,nq_40 +S 2000,1900,2000,8100,300,nq,UP,CALU1 +S 2000,1900,2000,8100,300,*,UP,ALU1 +S 1000,2900,1000,7100,300,i,UP,CALU1 +S 1000,7800,1000,8900,300,*,DOWN,ALU1 +S 1000,4000,1600,4000,500,*,LEFT,POLY +S 2000,700,2000,2600,400,*,UP,NDIF +S 1000,700,1000,2600,400,*,UP,NDIF +S 1500,700,1500,2600,200,*,UP,NTRANS +S 2000,5400,2000,9300,400,*,UP,PDIF +S 1000,5400,1000,9300,400,*,UP,PDIF +S 1500,5400,1500,9300,200,*,UP,PTRANS +S 1000,1000,1000,2000,300,*,UP,ALU1 +S 1500,2500,1500,5500,200,*,UP,POLY +S -200,500,3200,500,1400,vss,RIGHT,CALU1 +S -200,9500,3200,9500,1400,vdd,RIGHT,CALU1 +S -500,7500,3500,7500,6000,*,RIGHT,NWELL +S -200,0,3200,0,400,*,RIGHT,PTIE +S -200,10000,3200,10000,400,*,LEFT,NTIE +V 1000,7900,CONT_DIF_P,* +V 1000,1000,CONT_DIF_N,* +V 1000,9000,CONT_DIF_P,* +V 1000,2000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 2000,6000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 0,10000,CONT_BODY_N,* +V 1000,10000,CONT_BODY_N,* +V 2000,10000,CONT_BODY_N,* +V 3000,10000,CONT_BODY_N,* +V 0,0,CONT_BODY_P,* +V 1000,0,CONT_BODY_P,* +V 2000,0,CONT_BODY_P,* +V 3000,0,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/inv_x1.vbe b/pdks/symbolic/nsxlib2/cells/inv_x1.vbe new file mode 100644 index 000000000..67e85e029 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/inv_x1.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_i_nq : NATURAL := 3640; + CONSTANT rup_i_nq : NATURAL := 3720; + CONSTANT tphl_i_nq : NATURAL := 101; + CONSTANT tplh_i_nq : NATURAL := 139; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x1; + +ARCHITECTURE behaviour_data_flow OF inv_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x1" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/inv_x2.ap b/pdks/symbolic/nsxlib2/cells/inv_x2.ap new file mode 100644 index 000000000..ac07bb5f2 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/inv_x2.ap @@ -0,0 +1,52 @@ +V ALLIANCE : 6 +H inv_x2,P,14/ 8/2024,100 +A 0,0,3000,10000 +R 1000,6000,ref_ref,i_30 +R 1000,7000,ref_ref,i_35 +R 2000,8000,ref_ref,nq_40 +R 2000,7000,ref_ref,nq_35 +R 2000,6000,ref_ref,nq_30 +R 2000,5000,ref_ref,nq_25 +R 2000,4000,ref_ref,nq_20 +R 2000,3000,ref_ref,nq_15 +R 2000,2000,ref_ref,nq_10 +R 1000,3000,ref_ref,i_15 +R 1000,4000,ref_ref,i_20 +R 1000,5000,ref_ref,i_25 +S 1500,3400,1500,5700,200,*,UP,POLY +S 1000,8000,1000,9200,300,*,UP,ALU1 +S 1000,2900,1000,7100,300,*,UP,ALU1 +S 1000,2900,1000,7100,300,i,UP,CALU1 +S 2000,1900,2000,8100,300,*,UP,ALU1 +S 2000,1900,2000,8100,300,nq,UP,CALU1 +S 1000,800,1000,2100,300,*,UP,ALU1 +S 1000,1100,1000,3500,400,*,UP,NDIF +S 1000,5500,1000,9400,400,*,UP,PDIF +S 1000,4000,1600,4000,500,*,LEFT,POLY +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 1500,1100,1500,3500,200,*,UP,NTRANS +S 2100,5500,2100,9400,600,*,UP,PDIF +S 2100,1100,2100,3500,600,*,UP,NDIF +S -500,7500,3500,7500,6000,*,RIGHT,NWELL +S -200,10000,3200,10000,400,*,RIGHT,NTIE +S -200,0,3200,0,400,*,RIGHT,PTIE +S -200,500,3200,500,1400,vss,RIGHT,CALU1 +S -200,9500,3200,9500,1400,vdd,RIGHT,CALU1 +V 1000,8100,CONT_DIF_P,* +V 1000,9000,CONT_DIF_P,* +V 1000,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 2000,3000,CONT_DIF_N,* +V 2000,6000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,2000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/inv_x2.vbe b/pdks/symbolic/nsxlib2/cells/inv_x2.vbe new file mode 100644 index 000000000..9df0116d3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/inv_x2.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 12; + CONSTANT rdown_i_nq : NATURAL := 1620; + CONSTANT rup_i_nq : NATURAL := 2420; + CONSTANT tphl_i_nq : NATURAL := 69; + CONSTANT tplh_i_nq : NATURAL := 163; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x2; + +ARCHITECTURE behaviour_data_flow OF inv_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x2" + SEVERITY WARNING; + nq <= not (i) after 800 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/inv_x4.ap b/pdks/symbolic/nsxlib2/cells/inv_x4.ap new file mode 100644 index 000000000..f2d6dfba5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/inv_x4.ap @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H inv_x4,P,11/ 6/2024,100 +A 0,0,4000,10000 +R 1000,6000,ref_ref,i_30 +R 1000,5000,ref_ref,i_25 +R 1000,4000,ref_ref,i_20 +R 1000,3000,ref_ref,i_15 +R 1000,2000,ref_ref,i_10 +R 2000,4000,ref_ref,nq_20 +R 2000,3000,ref_ref,nq_15 +R 2000,2000,ref_ref,nq_10 +R 2000,7000,ref_ref,nq_35 +R 2000,6000,ref_ref,nq_30 +R 2000,5000,ref_ref,nq_25 +R 1000,7000,ref_ref,i_35 +R 1000,8000,ref_ref,i_40 +R 2000,8000,ref_ref,nq_40 +S 1000,1900,1000,8100,300,*,UP,ALU1 +S 1000,1900,1000,8100,300,i,UP,CALU1 +S 2000,1900,2000,8100,300,*,UP,ALU1 +S 2000,1900,2000,8100,300,nq,UP,CALU1 +S 3000,800,3000,2100,300,*,UP,ALU1 +S 3000,5900,3000,9200,300,*,UP,ALU1 +S 2900,600,2900,2500,600,*,UP,NDIF +S 1000,600,1000,2500,400,*,UP,NDIF +S 1000,5500,1000,9400,400,*,UP,PDIF +S 2900,5500,2900,9400,600,*,UP,PDIF +S 900,4000,2500,4000,500,*,RIGHT,POLY +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 1500,2500,1500,5500,200,*,UP,POLY +S 2500,2500,2500,5600,200,*,UP,POLY +S 2500,600,2500,2500,200,*,UP,NTRANS +S 1500,600,1500,2500,200,*,UP,NTRANS +S 2000,600,2000,2500,600,*,UP,NDIF +S 2000,5500,2000,9400,600,*,UP,PDIF +S -200,9500,4200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,4200,500,1400,vss,RIGHT,CALU1 +S -500,7500,4500,7500,6000,*,RIGHT,NWELL +S -200,10000,4200,10000,400,*,RIGHT,NTIE +S -200,0,4200,0,400,*,RIGHT,PTIE +V 3000,9200,CONT_DIF_P,* +V 1000,9200,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 3000,900,CONT_DIF_N,* +V 1000,900,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 2000,6000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,2000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/inv_x4.vbe b/pdks/symbolic/nsxlib2/cells/inv_x4.vbe new file mode 100644 index 000000000..3091ae3f7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/inv_x4.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 26; + CONSTANT rdown_i_nq : NATURAL := 810; + CONSTANT rup_i_nq : NATURAL := 1060; + CONSTANT tphl_i_nq : NATURAL := 71; + CONSTANT tplh_i_nq : NATURAL := 143; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x4; + +ARCHITECTURE behaviour_data_flow OF inv_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x4" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/inv_x8.ap b/pdks/symbolic/nsxlib2/cells/inv_x8.ap new file mode 100644 index 000000000..7153f5064 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/inv_x8.ap @@ -0,0 +1,94 @@ +V ALLIANCE : 6 +H inv_x8,P,11/ 6/2024,100 +A 0,0,6000,10000 +R 2000,8000,ref_ref,nq_40 +R 1000,2000,ref_ref,i_10 +R 1000,3000,ref_ref,i_15 +R 2000,5000,ref_ref,nq_25 +R 2000,6000,ref_ref,nq_30 +R 2000,7000,ref_ref,nq_35 +R 2000,2000,ref_ref,nq_10 +R 2000,3000,ref_ref,nq_15 +R 2000,4000,ref_ref,nq_20 +R 1000,8000,ref_ref,i_40 +R 1000,7000,ref_ref,i_35 +R 1000,6000,ref_ref,i_30 +R 1000,5000,ref_ref,i_25 +R 1000,4000,ref_ref,i_20 +S 2000,4000,4000,4000,300,*,RIGHT,ALU1 +S 5000,800,5000,2100,300,*,UP,ALU1 +S 4000,1900,4000,8100,300,*,UP,ALU1 +S 3000,800,3000,2100,300,*,UP,ALU1 +S 2000,1900,2000,8100,300,*,UP,ALU1 +S 2000,1900,2000,8100,300,nq,UP,CALU1 +S 1000,1900,1000,8100,300,i,UP,CALU1 +S 1000,1900,1000,8100,300,*,UP,ALU1 +S 3000,5900,3000,9200,300,*,UP,ALU1 +S 5000,5900,5000,9200,300,*,UP,ALU1 +S 1000,600,1000,2500,600,*,UP,NDIF +S 5000,600,5000,2500,400,*,UP,NDIF +S 1000,5500,1000,9400,400,*,UP,PDIF +S 2000,600,2000,2500,800,*,UP,NDIF +S 3000,600,3000,2500,400,*,UP,NDIF +S 4000,600,4000,2500,400,*,UP,NDIF +S 900,4000,1500,4000,500,*,RIGHT,POLY +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 1500,2500,1500,5500,200,*,UP,POLY +S 1500,600,1500,2500,200,*,UP,NTRANS +S 900,4000,4500,4000,400,*,RIGHT,POLY +S 4500,2500,4500,5500,200,*,UP,POLY +S 2500,2500,2500,5500,200,*,UP,POLY +S 2500,600,2500,2500,200,*,UP,NTRANS +S 3500,2500,3500,5600,200,*,UP,POLY +S 3500,600,3500,2500,200,*,UP,NTRANS +S 4500,600,4500,2500,200,*,UP,NTRANS +S 1900,5500,1900,9400,600,*,UP,PDIF +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 3100,5500,3100,9400,600,*,UP,PDIF +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 3900,5500,3900,9400,600,*,UP,PDIF +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 4900,5500,4900,9400,600,*,UP,PDIF +S -200,0,6200,0,400,*,RIGHT,PTIE +S -200,500,6200,500,1400,vss,RIGHT,CALU1 +S -500,7500,6500,7500,6000,*,RIGHT,NWELL +S -200,10000,6200,10000,400,*,RIGHT,NTIE +S -200,9500,6200,9500,1400,vdd,RIGHT,CALU1 +V 1000,9200,CONT_DIF_P,* +V 900,900,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 3000,900,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 4000,2000,CONT_DIF_N,* +V 5000,900,CONT_DIF_N,* +V 5000,2000,CONT_DIF_N,* +V 2000,6000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,9200,CONT_DIF_P,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,9200,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 1000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/inv_x8.vbe b/pdks/symbolic/nsxlib2/cells/inv_x8.vbe new file mode 100644 index 000000000..4e6fa0639 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/inv_x8.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i : NATURAL := 54; + CONSTANT rdown_i_nq : NATURAL := 400; + CONSTANT rup_i_nq : NATURAL := 450; + CONSTANT tphl_i_nq : NATURAL := 86; + CONSTANT tplh_i_nq : NATURAL := 133; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x8; + +ARCHITECTURE behaviour_data_flow OF inv_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x8" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/mx2_x2.ap b/pdks/symbolic/nsxlib2/cells/mx2_x2.ap new file mode 100644 index 000000000..ee6e72f30 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/mx2_x2.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 6 +H mx2_x2,P,17/ 8/2024,100 +A 0,0,8000,10000 +R 6000,5000,ref_ref,i1_20 +R 6000,4000,ref_ref,i1_25 +R 6000,3000,ref_ref,i1_15 +R 6000,2000,ref_ref,i1_10 +R 6000,7000,ref_ref,i1_35 +R 6000,8000,ref_ref,i1_40 +R 6000,6000,ref_ref,i1_30 +R 7000,5000,ref_ref,q_25 +R 7000,4000,ref_ref,q_20 +R 7000,3000,ref_ref,q_15 +R 2000,4000,ref_ref,i0_20 +R 2000,3000,ref_ref,i0_15 +R 3000,7000,ref_ref,cmd_35 +R 3000,6000,ref_ref,cmd_30 +R 3000,5000,ref_ref,cmd_25 +R 3000,4000,ref_ref,cmd_20 +R 2000,5000,ref_ref,i0_25 +R 2000,6000,ref_ref,i0_30 +R 2000,7000,ref_ref,i0_35 +S 2500,7400,2500,9400,400,*,UP,PDIF +S 3500,7400,3500,9400,800,*,UP,PDIF +S 3000,7400,3000,9400,200,*,UP,PTRANS +S 3000,6000,3000,7500,200,*,UP,POLY +S 3000,3900,3000,6100,200,*,UP,POLY +S 5300,600,5300,1600,200,*,UP,NTRANS +S 5600,600,5600,1600,400,*,UP,NDIF +S 5800,600,5800,1600,600,*,UP,NDIF +S 4600,600,4600,1600,200,*,UP,NTRANS +S 4300,600,4300,1600,400,*,UP,NDIF +S 3700,600,3700,1600,1000,*,UP,NDIF +S 2800,600,2800,1600,200,*,UP,NTRANS +S 3200,600,3200,1600,400,*,UP,NDIF +S 2100,600,2100,1600,200,*,UP,NTRANS +S 1600,600,1600,1600,400,*,UP,NDIF +S 1100,600,1100,1600,200,*,UP,NTRANS +S 600,600,600,1600,400,*,UP,NDIF +S 2100,5800,2100,7600,200,*,UP,POLY +S 5000,7000,6100,7000,400,*,RIGHT,ALU1 +S 500,2000,4900,2000,300,*,RIGHT,ALU1 +S 3900,800,3900,2900,400,*,UP,NDIF +S 3900,2500,3900,8100,300,*,UP,ALU1 +S 4100,7400,4100,9400,600,*,DOWN,PDIF +S 1000,4000,4700,4000,200,*,RIGHT,POLY +S 4800,2000,4800,5800,300,*,UP,ALU1 +S 4600,1500,4600,4100,200,*,UP,POLY +S 4600,5500,4600,7400,200,*,UP,POLY +S 4600,7400,4600,9400,200,*,UP,PTRANS +S 5400,3000,6100,3000,400,*,RIGHT,ALU1 +S 5900,7400,5900,9400,800,*,DOWN,PDIF +S 5300,1400,5300,3200,200,*,UP,POLY +S 5300,7400,5300,9400,200,*,UP,PTRANS +S 5300,6900,5300,7800,200,*,UP,POLY +S 6000,1900,6000,8100,300,*,UP,ALU1 +S 6000,1900,6000,8100,300,i1,UP,CALU1 +S 3000,3800,3000,7200,300,*,UP,ALU1 +S 3000,3800,3000,7200,300,cmd,UP,CALU1 +S -200,0,8200,0,400,*,RIGHT,PTIE +S -200,500,8200,500,1400,vss,RIGHT,CALU1 +S -500,7500,8500,7500,6000,*,RIGHT,NWELL +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +S 1600,7400,1600,9400,400,*,UP,PDIF +S 1100,7400,1100,9400,200,*,UP,PTRANS +S 1600,7800,1600,9200,400,*,UP,ALU1 +S 2100,7400,2100,9400,200,*,UP,PTRANS +S 1100,4000,1100,7400,200,*,DOWN,POLY +S 1100,2300,1100,4000,200,*,UP,POLY +S 2800,1300,2800,2100,200,*,UP,POLY +S 6000,5500,6000,9400,400,*,UP,PDIF +S 1100,1500,1100,2300,200,*,UP,POLY +S 2100,1500,2100,3200,200,*,UP,POLY +S 3700,4700,6500,4700,200,*,RIGHT,POLY +S 6000,600,6000,2500,400,*,UP,NDIF +S 6500,5500,6500,9400,200,*,UP,PTRANS +S 7000,600,7000,2500,400,*,UP,NDIF +S 7000,1900,7000,8100,300,*,UP,ALU1 +S 7000,1900,7000,8100,300,q,UP,CALU1 +S 6500,2500,6500,5500,200,*,UP,POLY +S 6500,600,6500,2500,200,*,UP,NTRANS +S 600,7400,600,9400,600,*,UP,PDIF +S 500,2000,500,8100,300,*,UP,ALU1 +S 2000,2900,2000,7100,300,i0,UP,CALU1 +S 2000,2900,2000,7100,300,*,UP,ALU1 +S 500,600,500,2200,400,*,UP,NDIF +S 6900,5500,6900,9400,600,*,UP,PDIF +S 7100,5500,7100,9400,400,*,UP,PDIF +V 5200,7000,CONT_POLY,* +B 500,2000,200,200,CONT_TURN1,* +V 3900,2700,CONT_DIF_N,* +V 3900,4900,CONT_POLY,* +V 3900,8000,CONT_DIF_P,* +B 4800,2000,200,200,CONT_TURN1,* +V 4700,5700,CONT_POLY,* +B 4700,5700,400,400,CONT_TURN1,* +V 5500,3000,CONT_POLY,* +V 6000,9100,CONT_DIF_P,* +V 6000,900,CONT_DIF_N,* +V 1600,8000,CONT_DIF_P,* +V 1600,900,CONT_DIF_N,* +V 7000,2000,CONT_DIF_N,* +V 2700,2000,CONT_POLY,* +V 2000,6000,CONT_POLY,* +V 500,8000,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,6000,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 2000,3000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/mx2_x2.vbe b/pdks/symbolic/nsxlib2/cells/mx2_x2.vbe new file mode 100644 index 000000000..401686e9e --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/mx2_x2.vbe @@ -0,0 +1,40 @@ +ENTITY mx2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_cmd_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 451; + CONSTANT tphh_i1_q : NATURAL := 451; + CONSTANT tpll_i0_q : NATURAL := 469; + CONSTANT tpll_i1_q : NATURAL := 469; + CONSTANT tphh_cmd_q : NATURAL := 484; + CONSTANT tphl_cmd_q : NATURAL := 485; + CONSTANT tpll_cmd_q : NATURAL := 522; + CONSTANT tplh_cmd_q : NATURAL := 534; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x2; + +ARCHITECTURE behaviour_data_flow OF mx2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x2" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/mx2_x4.ap b/pdks/symbolic/nsxlib2/cells/mx2_x4.ap new file mode 100644 index 000000000..905151ca2 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/mx2_x4.ap @@ -0,0 +1,158 @@ +V ALLIANCE : 6 +H mx2_x4,P,16/ 8/2024,100 +A 0,0,10000,10000 +R 6000,5000,ref_ref,i1_20 +R 6000,4000,ref_ref,i1_25 +R 8000,5000,ref_ref,q_20 +R 8000,4000,ref_ref,q_25 +R 6000,8000,ref_ref,i1_40 +R 6000,7000,ref_ref,i1_35 +R 6000,6000,ref_ref,i1_30 +R 6000,3000,ref_ref,i1_15 +R 6000,2000,ref_ref,i1_10 +R 2000,7000,ref_ref,i0_35 +R 2000,6000,ref_ref,i0_30 +R 2000,5000,ref_ref,i0_25 +R 3000,3000,ref_ref,cmd_15 +R 3000,4000,ref_ref,cmd_20 +R 3000,5000,ref_ref,cmd_25 +R 3000,6000,ref_ref,cmd_30 +R 3000,7000,ref_ref,cmd_35 +R 3000,8000,ref_ref,cmd_40 +R 8000,3000,ref_ref,q_15 +R 2000,3000,ref_ref,i0_15 +R 2000,4000,ref_ref,i0_20 +S 5900,600,5900,1600,400,*,UP,NDIF +S 6400,600,6400,1600,600,*,UP,NDIF +S 5200,600,5200,1600,200,*,UP,NTRANS +S 5700,600,5700,1600,400,*,UP,NDIF +S 4700,600,4700,1600,200,*,UP,NTRANS +S 4300,600,4300,1600,400,*,UP,NDIF +S 3800,600,3800,1600,1000,*,UP,NDIF +S 3000,600,3000,1600,200,*,UP,NTRANS +S 2300,600,2300,1600,200,*,UP,NTRANS +S 1900,600,1900,1600,600,*,UP,NDIF +S 1300,600,1300,1600,200,*,UP,NTRANS +S 800,600,800,1600,600,*,UP,NDIF +S 1300,1400,1300,4000,200,*,UP,POLY +S 3000,1400,3000,2100,200,*,UP,POLY +S 7500,2400,7500,5600,200,*,UP,POLY +S 1000,4000,1000,6500,200,*,DOWN,POLY +S 3700,2600,3700,8100,300,*,UP,ALU1 +S 6000,1900,6000,8100,300,*,UP,ALU1 +S 6000,1900,6000,8100,300,i1,UP,CALU1 +S 8000,1900,8000,8100,300,q,UP,CALU1 +S 8000,1900,8000,8100,300,*,UP,ALU1 +S 9000,5900,9000,8800,300,*,UP,ALU1 +S 7000,5900,7000,8800,300,*,UP,ALU1 +S 9000,1200,9000,2100,300,*,UP,ALU1 +S 7000,1200,7000,2100,300,*,UP,ALU1 +S 3000,2900,3000,8100,300,*,UP,ALU1 +S 3000,2900,3000,8100,300,cmd,UP,CALU1 +S 2000,2900,2000,7100,300,*,UP,ALU1 +S 2000,2900,2000,7100,300,i0,UP,CALU1 +S 500,2000,4600,2000,300,*,RIGHT,ALU1 +S 4600,2000,4600,5500,300,*,UP,ALU1 +S 500,1900,500,8100,300,*,UP,ALU1 +S 1500,7900,1500,8800,300,*,UP,ALU1 +S 500,600,500,2200,400,*,DOWN,NDIF +S 500,6500,500,8500,400,*,UP,PDIF +S 4900,6500,4900,8500,600,*,UP,PDIF +S 3800,6500,3800,8500,1000,*,UP,PDIF +S 1500,6500,1500,8500,400,*,UP,PDIF +S 2500,6500,2500,8500,400,*,UP,PDIF +S 6300,6500,6300,8500,1000,*,UP,PDIF +S 5700,6500,5700,8500,200,*,UP,PDIF +S 8000,5500,8000,9400,400,*,UP,PDIF +S 8000,600,8000,2500,400,*,UP,NDIF +S 2800,600,2800,1500,400,*,UP,NDIF +S 7500,5500,7500,9400,200,*,UP,PTRANS +S 7000,5500,7000,9400,400,*,DOWN,PDIF +S 7500,600,7500,2500,200,*,UP,NTRANS +S 5200,6100,6100,6100,200,*,RIGHT,POLY +S 5300,6100,5300,6500,200,*,UP,POLY +S 5300,6500,5300,8500,200,*,UP,PTRANS +S 5100,2900,6100,2900,200,*,RIGHT,POLY +S 5200,1500,5200,2900,200,*,UP,POLY +S 3800,600,3800,3000,400,*,UP,NDIF +S 900,4000,4700,4000,200,*,RIGHT,POLY +S -500,7500,10500,7500,6000,*,RIGHT,NWELL +S 2000,5800,2000,6600,200,*,UP,POLY +S 2000,6500,2000,8500,200,*,UP,PTRANS +S 1800,2800,2400,2800,200,*,RIGHT,POLY +S 2300,1500,2300,2800,200,*,UP,POLY +S 1000,6500,1000,8500,200,*,UP,PTRANS +S 7000,600,7000,2500,600,*,UP,NDIF +S 9000,600,9000,2500,400,*,UP,NDIF +S 8500,2500,8500,5500,200,*,UP,POLY +S 4700,1500,4700,4100,200,*,UP,POLY +S 3000,4100,3000,6600,200,*,UP,POLY +S 3600,4700,8500,4700,200,*,RIGHT,POLY +S 4400,5200,4400,6600,200,*,UP,POLY +S 9000,5500,9000,9400,400,*,UP,PDIF +S 3400,6500,3400,8500,400,*,UP,PDIF +S 4400,6500,4400,8500,200,*,UP,PTRANS +S 3000,6500,3000,8500,200,*,UP,PTRANS +S 8500,5500,8500,9400,200,*,UP,PTRANS +S -200,9500,10200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,10200,500,1400,vss,RIGHT,CALU1 +S -200,10000,10200,10000,400,*,RIGHT,NTIE +S -200,0,10200,0,400,*,RIGHT,PTIE +S 8500,600,8500,2500,200,*,UP,NTRANS +V 5700,900,CONT_DIF_N,* +B 4600,2000,200,200,CONT_TURN1,* +V 9000,9100,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 7000,9100,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,6000,CONT_DIF_P,* +V 9000,1000,CONT_DIF_N,* +V 9000,2000,CONT_DIF_N,* +V 7000,1000,CONT_DIF_N,* +V 7000,2000,CONT_DIF_N,* +V 3800,2800,CONT_DIF_N,* +V 3700,8000,CONT_DIF_P,* +V 3700,7000,CONT_DIF_P,* +V 3000,2000,CONT_POLY,* +V 1800,900,CONT_DIF_N,* +V 1500,8000,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 500,7000,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 3700,4800,CONT_POLY,* +V 4600,5400,CONT_POLY,* +V 8000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 3000,4000,CONT_POLY,* +V 6000,6000,CONT_POLY,* +V 2000,6000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 6000,3000,CONT_POLY,* +V 8000,2000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/mx2_x4.vbe b/pdks/symbolic/nsxlib2/cells/mx2_x4.vbe new file mode 100644 index 000000000..ddb1f3ca7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/mx2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY mx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 564; + CONSTANT tphh_i1_q : NATURAL := 564; + CONSTANT tphl_cmd_q : NATURAL := 574; + CONSTANT tpll_i0_q : NATURAL := 576; + CONSTANT tpll_i1_q : NATURAL := 576; + CONSTANT tphh_cmd_q : NATURAL := 615; + CONSTANT tplh_cmd_q : NATURAL := 631; + CONSTANT tpll_cmd_q : NATURAL := 647; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x4; + +ARCHITECTURE behaviour_data_flow OF mx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x4" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/mx3_x2.ap b/pdks/symbolic/nsxlib2/cells/mx3_x2.ap new file mode 100644 index 000000000..ed13f0df6 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/mx3_x2.ap @@ -0,0 +1,209 @@ +V ALLIANCE : 6 +H mx3_x2,P,17/ 8/2024,100 +A 0,0,13000,10000 +R 5000,5000,ref_ref,i1_25 +R 1000,7000,ref_ref,cmd1_35 +R 1000,6000,ref_ref,cmd1_30 +R 1000,5000,ref_ref,cmd1_25 +R 1000,4000,ref_ref,cmd1_20 +R 1000,3000,ref_ref,cmd1_15 +R 8000,6000,ref_ref,i0_30 +R 9000,5000,ref_ref,i0_25 +R 12000,5000,ref_ref,q_25 +R 7000,5000,ref_ref,cmd0_25 +R 7000,6000,ref_ref,cmd0_30 +R 8000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i2_25 +R 7000,4000,ref_ref,cmd0_20 +S 2400,800,2400,2000,600,*,UP,NDIF +S 2400,7500,2400,9400,600,*,UP,PDIF +S 3000,7500,3000,9400,200,*,UP,PTRANS +S 3000,800,3000,2000,200,*,UP,NTRANS +S -500,7500,13500,7500,6000,*,RIGHT,NWELL +S 3000,1900,3000,7600,200,*,UP,POLY +S 11000,700,11000,3500,600,*,UP,NDIF +S 10800,2700,10800,3500,400,*,UP,NDIF +S 1800,3400,1800,5500,200,*,UP,POLY +S 8300,7100,8300,7600,200,*,UP,POLY +S 10300,2700,10300,3500,200,*,UP,NTRANS +S 12000,700,12000,3500,400,*,UP,NDIF +S 11500,700,11500,3500,200,*,UP,NTRANS +S 11500,3400,11500,5500,200,*,UP,POLY +S 10300,3400,10300,5500,200,*,UP,POLY +S 9100,1800,9100,4100,200,*,UP,POLY +S 8300,1800,8300,3300,200,*,UP,POLY +S 6100,2000,6100,7600,200,*,UP,POLY +S 5200,2000,5200,4100,200,*,UP,POLY +S 3800,2000,3800,3400,200,*,UP,POLY +S 4800,5000,6100,5000,300,i1,LEFT,CALU1 +S 4800,5000,6100,5000,300,*,RIGHT,ALU1 +S 6000,3800,6000,6200,300,i1,UP,CALU1 +S 1000,4000,1800,4000,400,*,RIGHT,POLY +S 7800,7800,7800,8800,400,*,UP,ALU1 +S 4600,6900,4600,7400,400,*,DOWN,ALU1 +S 9800,1600,9800,2400,300,*,UP,ALU1 +S 9000,3800,9000,6100,300,i0,UP,CALU1 +S 9000,3800,9000,6100,300,*,UP,ALU1 +S 4400,2400,9800,2400,300,*,LEFT,ALU1 +S 2300,3100,2300,6300,300,*,UP,ALU1 +S 2200,3200,3700,3200,300,*,RIGHT,ALU1 +S 6600,3100,9900,3100,300,*,RIGHT,ALU1 +S 2200,6300,5400,6300,300,*,RIGHT,ALU1 +S 7800,6000,9100,6000,300,*,RIGHT,ALU1 +S 7800,6000,9100,6000,300,i0,LEFT,CALU1 +S 1000,7000,3800,7000,300,*,RIGHT,ALU1 +S 2900,5000,4200,5000,300,i2,RIGHT,CALU1 +S 7000,5000,8200,5000,300,cmd0,LEFT,CALU1 +S 7000,5000,8200,5000,300,*,RIGHT,ALU1 +S 9800,3100,9800,6200,300,*,UP,ALU1 +S 9600,1700,11000,1700,300,*,RIGHT,ALU1 +S 11000,1700,11000,7000,300,*,UP,ALU1 +S 11000,7900,11000,8800,300,*,UP,ALU1 +S 4300,7000,11000,7000,300,*,RIGHT,ALU1 +S 9600,7000,9600,8200,300,*,UP,ALU1 +S 2300,5500,2300,6900,400,*,UP,PDIF +S 8700,800,8700,2000,400,*,UP,NDIF +S 2300,2700,2300,3500,400,*,UP,NDIF +S 4500,800,4500,2700,600,*,UP,NDIF +S 3400,800,3400,2000,400,*,UP,NDIF +S 4200,800,4200,2000,400,*,UP,NDIF +S 3800,800,3800,2000,200,*,UP,NTRANS +S 4800,800,4800,2000,400,*,UP,NDIF +S 5200,800,5200,2000,200,*,UP,NTRANS +S 5600,800,5600,2000,400,*,UP,NDIF +S 6100,800,6100,2000,200,*,UP,NTRANS +S 6600,800,6600,2000,400,*,UP,NDIF +S 12000,5500,12000,9400,400,*,UP,PDIF +S 11000,4000,11600,4000,500,*,RIGHT,POLY +S 11500,5500,11500,9400,200,*,UP,PTRANS +S 11100,5500,11100,9400,600,*,UP,PDIF +S 8000,5000,10400,5000,200,*,RIGHT,POLY +S 10300,5500,10300,6900,200,*,UP,PTRANS +S 8300,800,8300,2000,200,*,UP,NTRANS +S 7500,3800,8100,3800,200,*,RIGHT,POLY +S 7600,2300,7600,3800,200,*,UP,POLY +S 9800,5500,9800,6900,400,*,UP,PDIF +S 10800,5500,10800,6900,600,*,UP,PDIF +S 3800,4000,3800,7500,200,*,UP,POLY +S 9600,800,9600,2000,400,*,UP,NDIF +S 6900,800,6900,2000,400,*,UP,NDIF +S 7800,800,7800,2000,400,*,UP,NDIF +S 1400,2700,1400,3500,400,*,UP,NDIF +S 3700,4000,5200,4000,200,*,RIGHT,POLY +S 7200,2300,7700,2300,200,*,RIGHT,POLY +S 9100,5800,9100,7500,200,*,UP,POLY +S 8000,6600,8000,7100,200,*,UP,POLY +S 7200,7100,7200,7600,200,*,UP,POLY +S 7000,2900,7000,7100,200,*,UP,POLY +S 5300,6200,5300,7500,200,*,UP,POLY +S 4700,7500,4700,9400,600,*,UP,PDIF +S 6600,7500,6600,9400,600,*,UP,PDIF +S 7800,7500,7800,9400,600,*,UP,PDIF +S 8700,7500,8700,9400,200,*,UP,PDIF +S 5700,7500,5700,9400,200,*,DOWN,PDIF +S 4200,7500,4200,9400,200,*,DOWN,PDIF +S 3400,7500,3400,9400,400,*,UP,PDIF +S 1500,5500,1500,6900,400,*,DOWN,PDIF +S 2300,1700,6700,1700,300,*,RIGHT,ALU1 +S 1000,1600,1000,3500,600,*,UP,NDIF +S 1800,2700,1800,3500,200,*,UP,NTRANS +S 9100,800,9100,2000,200,*,UP,NTRANS +S 9800,800,9800,2000,400,*,UP,NDIF +S 7300,800,7300,2000,200,*,UP,NTRANS +S 9800,2800,9800,3400,400,*,UP,NDIF +S 3000,3700,3000,5800,300,i2,UP,CALU1 +S 1000,5500,1000,7900,600,*,UP,PDIF +S 1000,7500,1000,8800,300,*,UP,ALU1 +S 1000,900,1000,2200,300,*,UP,ALU1 +S 1000,2800,1000,7200,300,cmd1,UP,CALU1 +S 2300,8000,6800,8000,300,*,RIGHT,ALU1 +S 6900,7100,7300,7100,200,*,RIGHT,POLY +S 7900,7100,8400,7100,200,*,RIGHT,POLY +S 9600,7500,9600,9400,600,*,UP,PDIF +S 7000,3800,7000,6200,300,*,UP,ALU1 +S 7000,3800,7000,6200,300,cmd0,UP,CALU1 +S 7800,4000,9200,4000,300,i0,LEFT,CALU1 +S 7800,4000,8800,4000,300,*,RIGHT,ALU1 +S 12000,1800,12000,8200,300,*,UP,ALU1 +S 12000,1800,12000,8200,300,q,UP,CALU1 +S 3800,7500,3800,9400,200,*,UP,PTRANS +S 4600,7100,4600,9400,600,*,UP,PDIF +S 5300,7500,5300,9400,200,*,UP,PTRANS +S 6100,7500,6100,9400,200,*,UP,PTRANS +S 7200,7500,7200,9400,200,*,UP,PTRANS +S 8300,7500,8300,9400,200,*,UP,PTRANS +S 9100,7500,9100,9400,200,*,UP,PTRANS +S -200,9500,13200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,13200,500,1400,vss,RIGHT,CALU1 +S 7300,2000,7300,2300,200,*,UP,POLY +S 1800,5500,1800,6900,200,*,UP,PTRANS +S 8000,3800,8000,6600,200,*,UP,POLY +S -200,10000,13200,10000,400,*,RIGHT,NTIE +S -200,0,13200,0,400,*,RIGHT,PTIE +V 10900,1000,CONT_DIF_N,* +V 6000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 7800,1000,CONT_DIF_N,* +V 9800,3100,CONT_DIF_N,* +V 9000,6000,CONT_POLY,* +B 11000,7000,200,200,CONT_TURN1,* +B 11000,1700,200,200,CONT_TURN1,* +B 9800,2400,200,200,CONT_TURN1,* +V 9600,8000,CONT_DIF_P,* +V 11000,8000,CONT_DIF_P,* +V 6600,1700,CONT_DIF_N,* +V 2400,1700,CONT_DIF_N,* +V 2400,8000,CONT_DIF_P,* +V 2300,6300,CONT_DIF_P,* +V 2300,3200,CONT_DIF_N,* +V 5200,6300,CONT_POLY,* +V 1000,7700,CONT_DIF_P,* +V 3600,3200,CONT_POLY,* +V 4500,2400,CONT_DIF_N,* +V 8400,3100,CONT_POLY,* +V 6800,3100,CONT_POLY,* +V 4600,7300,CONT_DIF_P,* +V 9000,4000,CONT_POLY,* +V 9800,1700,CONT_DIF_N,* +V 12000,8000,CONT_DIF_P,* +V 12000,7000,CONT_DIF_P,* +V 12000,6000,CONT_DIF_P,* +V 12000,3000,CONT_DIF_N,* +V 12000,2000,CONT_DIF_N,* +V 7800,8000,CONT_DIF_P,* +V 8000,5000,CONT_POLY,* +V 11000,4000,CONT_POLY,* +V 3600,7000,CONT_POLY,* +V 1000,2000,CONT_DIF_N,* +V 6600,8000,CONT_DIF_P,* +V 9800,6000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +V 13000,0,CONT_BODY_P,* +V 13000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/mx3_x2.vbe b/pdks/symbolic/nsxlib2/cells/mx3_x2.vbe new file mode 100644 index 000000000..ddc531ad5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/mx3_x2.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 1620; + CONSTANT rdown_cmd1_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_cmd0_q : NATURAL := 1790; + CONSTANT rup_cmd1_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 538; + CONSTANT tphh_cmd0_q : NATURAL := 573; + CONSTANT tphh_i1_q : NATURAL := 654; + CONSTANT tphh_i2_q : NATURAL := 654; + CONSTANT tpll_i0_q : NATURAL := 658; + CONSTANT tphh_cmd1_q : NATURAL := 664; + CONSTANT tpll_cmd0_q : NATURAL := 680; + CONSTANT tplh_cmd1_q : NATURAL := 738; + CONSTANT tphl_cmd1_q : NATURAL := 739; + CONSTANT tplh_cmd0_q : NATURAL := 768; + CONSTANT tphl_cmd0_q : NATURAL := 792; + CONSTANT tpll_i1_q : NATURAL := 808; + CONSTANT tpll_i2_q : NATURAL := 808; + CONSTANT tpll_cmd1_q : NATURAL := 817; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x2; + +ARCHITECTURE behaviour_data_flow OF mx3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx3_x2" + SEVERITY WARNING; + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) + and i2)))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/mx3_x4.ap b/pdks/symbolic/nsxlib2/cells/mx3_x4.ap new file mode 100644 index 000000000..19e34af34 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/mx3_x4.ap @@ -0,0 +1,236 @@ +V ALLIANCE : 6 +H mx3_x4,P,17/ 8/2024,100 +A 0,0,14000,10000 +R 7000,5000,ref_ref,cmd0_30 +R 7000,6000,ref_ref,cmd0_25 +R 5000,4000,ref_ref,i1_25 +R 1000,5000,ref_ref,cmd1_25 +R 12000,6000,ref_ref,q_30 +R 12000,7000,ref_ref,q_35 +R 12000,8000,ref_ref,q_40 +R 1000,6000,ref_ref,cmd1_30 +R 1000,7000,ref_ref,cmd1_35 +R 3000,5000,ref_ref,i2_25 +R 7000,4000,ref_ref,cmd0_20 +R 8000,4000,ref_ref,i0_20 +R 12000,5000,ref_ref,q_25 +R 12000,3000,ref_ref,q_15 +R 12000,2000,ref_ref,q_10 +R 9000,5000,ref_ref,i0_25 +R 8000,6000,ref_ref,i0_30 +R 13000,4000,ref_ref,q_20 +R 1000,3000,ref_ref,cmd1_15 +R 1000,4000,ref_ref,cmd1_20 +S 2600,6400,2600,7600,200,*,UP,POLY +S 3000,4000,3000,6400,200,*,UP,POLY +S 2500,6400,3100,6400,200,*,LEFT,POLY +S 2600,1800,2600,4200,200,*,UP,POLY +S 4900,1800,4900,3200,200,*,UP,POLY +S 3600,3200,3600,7600,200,*,UP,POLY +S 3500,3200,5000,3200,200,*,RIGHT,POLY +S 10600,2700,10600,3500,400,*,UP,NDIF +S 10200,2700,10200,3600,200,*,UP,NTRANS +S 9700,2900,9700,3600,400,*,UP,NDIF +S 1600,3500,1600,5600,200,*,UP,POLY +S 5000,6000,5000,7500,200,*,UP,POLY +S 9100,6200,9100,7600,200,*,UP,POLY +S 10200,3400,10200,5600,200,*,UP,POLY +S 11500,3400,11500,5600,200,*,UP,POLY +S 12500,3500,12500,5600,200,*,UP,POLY +S 8200,1800,8200,2500,200,*,UP,POLY +S 5800,1800,5800,7500,200,*,UP,POLY +S 3500,1800,3500,2500,200,*,UP,POLY +S 2500,4000,3100,4000,500,*,RIGHT,POLY +S 800,4000,1700,4000,400,*,RIGHT,POLY +S 800,7700,800,9300,400,*,UP,ALU1 +S 800,600,800,2200,400,*,UP,ALU1 +S 7800,4000,8800,4000,400,*,RIGHT,ALU1 +S 7800,6000,8800,6000,400,*,RIGHT,ALU1 +S 4100,7100,11000,7100,300,*,RIGHT,ALU1 +S 11000,2000,11000,7100,300,*,UP,ALU1 +S 9500,2000,11000,2000,300,*,RIGHT,ALU1 +S 5800,2400,5800,7300,300,*,UP,ALU1 +S 4000,2400,5800,2400,300,*,RIGHT,ALU1 +S 2100,2400,2100,6200,300,*,UP,ALU1 +S 2100,2400,3600,2400,300,*,RIGHT,ALU1 +S 8900,3200,9800,3200,300,*,LEFT,ALU1 +S 6300,2400,8900,2400,300,*,RIGHT,ALU1 +S 8900,2400,8900,3200,300,*,UP,ALU1 +S 10200,5500,10200,6900,200,*,UP,PTRANS +S 9700,5500,9700,6900,400,*,UP,PDIF +S 9700,3000,9700,6400,300,*,UP,ALU1 +S 11000,5500,11000,9400,400,*,UP,PDIF +S 2100,2700,2100,3500,400,*,UP,NDIF +S 5400,7500,5400,9400,600,*,UP,PDIF +S 10700,5500,10700,6900,600,*,UP,PDIF +S 12000,5500,12000,9400,400,*,UP,PDIF +S 13000,5500,13000,9400,400,*,UP,PDIF +S 13000,1500,13000,3500,400,*,UP,NDIF +S 12000,1500,12000,3500,400,*,UP,NDIF +S 7700,700,7700,1900,400,*,UP,NDIF +S 1900,6000,4400,6000,300,*,RIGHT,ALU1 +S 9000,1900,9000,3800,200,*,UP,POLY +S 8200,7100,8200,7500,200,*,UP,POLY +S 8500,6200,9200,6200,200,*,RIGHT,POLY +S 8500,3800,9100,3800,200,*,RIGHT,POLY +S 11100,4000,12600,4000,500,*,RIGHT,POLY +S 12500,1500,12500,3500,200,*,UP,NTRANS +S 12500,5500,12500,9400,200,*,UP,PTRANS +S 11000,1500,11000,3500,400,*,UP,NDIF +S 10800,800,10800,3500,400,*,UP,NDIF +S 11000,7700,11000,9100,300,*,UP,ALU1 +S 11500,5500,11500,9400,200,*,UP,PTRANS +S 11500,1500,11500,3500,200,*,UP,NTRANS +S 9700,6900,9700,8200,300,*,UP,ALU1 +S 8200,700,8200,1900,200,*,UP,NTRANS +S 8600,7500,8600,9400,600,*,UP,PDIF +S 7600,7500,7600,9400,1000,*,UP,PDIF +S 6400,7500,6400,9400,1000,*,UP,PDIF +S 4200,7500,4200,9400,1000,*,UP,PDIF +S 3100,7500,3100,9400,400,*,UP,PDIF +S 1000,5500,1000,6900,600,*,UP,PDIF +S 1200,2700,1200,3500,400,*,UP,NDIF +S 9400,700,9400,1900,400,*,UP,NDIF +S 8500,700,8500,1900,400,*,UP,NDIF +S 6500,700,6500,1900,1000,*,UP,NDIF +S 5300,700,5300,1900,400,*,UP,NDIF +S 4400,700,4400,1900,400,*,UP,NDIF +S 4200,700,4200,2600,400,*,UP,NDIF +S 3900,700,3900,1900,400,*,UP,NDIF +S 3100,700,3100,1900,400,*,UP,NDIF +S 2100,700,2100,1900,400,*,UP,NDIF +S 7100,3800,7900,3800,200,*,RIGHT,POLY +S 7200,2300,7200,3800,200,*,UP,POLY +S 7800,3800,7800,6700,200,*,UP,POLY +S 6400,2200,6400,7100,200,*,UP,POLY +S 8000,3800,8000,6200,300,i0,UP,CALU1 +S 7000,3800,7000,6200,300,*,UP,ALU1 +S 7000,3800,7000,6200,300,cmd0,UP,CALU1 +S 800,1500,800,3500,600,*,UP,NDIF +S 1600,2700,1600,3500,200,*,UP,NTRANS +S 2800,5000,4200,5000,300,i2,RIGHT,CALU1 +S 4200,700,4200,2600,400,*,UP,NDIF +S 5000,3800,5000,6200,300,i1,DOWN,CALU1 +S 3000,3800,3000,5200,300,i2,DOWN,CALU1 +S 11800,4000,13200,4000,300,q,RIGHT,CALU1 +S 12000,1800,12000,8200,300,q,UP,CALU1 +S 12000,1800,12000,8200,300,*,UP,ALU1 +S 4000,6100,5100,6100,200,*,LEFT,POLY +S 7800,5000,9200,5000,300,i0,LEFT,CALU1 +S 7000,5000,10300,5000,200,*,RIGHT,POLY +S 6300,7100,7100,7100,200,*,RIGHT,POLY +S 5800,7500,5800,9400,200,*,UP,PTRANS +S 2000,1700,6600,1700,300,*,RIGHT,ALU1 +S 2600,700,2600,1900,200,*,UP,NTRANS +S 3500,700,3500,1900,200,*,UP,NTRANS +S 4900,700,4900,1900,200,*,UP,NTRANS +S 5800,700,5800,1900,200,*,UP,NTRANS +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 1000,2800,1000,7200,300,cmd1,UP,CALU1 +S -200,9500,14200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,14200,500,1400,vss,RIGHT,CALU1 +S 7200,1900,7200,2400,200,*,UP,POLY +S 7000,7000,7000,7500,200,*,UP,POLY +S 7800,6500,7800,7100,200,*,UP,POLY +S 7700,7100,8300,7100,200,*,RIGHT,POLY +S 4800,5000,5900,5000,400,*,RIGHT,POLY +S 3300,7000,3600,7000,400,*,RIGHT,POLY +S 4300,6900,4300,9400,600,*,UP,PDIF +S -500,7500,14500,7500,6000,*,RIGHT,NWELL +S -200,10000,14200,10000,400,*,RIGHT,NTIE +S -200,0,14200,0,400,*,RIGHT,PTIE +S 13000,400,13000,3200,300,*,UP,ALU1 +S 13000,5800,13000,9400,300,*,UP,ALU1 +S 9100,7500,9100,9400,200,*,UP,PTRANS +S 1800,8000,6600,8000,300,*,RIGHT,ALU1 +S 800,7000,3600,7000,300,*,RIGHT,ALU1 +S 800,5500,800,8100,600,*,UP,PDIF +S 5000,7500,5000,9400,200,*,UP,PTRANS +S 7000,7500,7000,9400,200,*,UP,PTRANS +S 8200,7500,8200,9400,200,*,UP,PTRANS +S 9600,7500,9600,9400,600,*,UP,PDIF +S 2000,7500,2000,9400,600,*,UP,PDIF +S 2600,7500,2600,9400,200,*,UP,PTRANS +S 2000,5500,2000,6900,600,*,UP,PDIF +S 9000,700,9000,1900,200,*,UP,NTRANS +S 1600,5500,1600,6900,200,*,UP,PTRANS +S 3600,7500,3600,9400,200,*,UP,PTRANS +S 7200,700,7200,1900,200,*,UP,NTRANS +S 9700,700,9700,2200,400,*,UP,NDIF +V 3000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 7700,1000,CONT_DIF_N,* +B 11000,2000,200,200,CONT_TURN1,* +B 11000,7100,200,200,CONT_TURN1,* +B 5800,2400,200,200,CONT_TURN1,* +B 2100,2400,200,200,CONT_TURN1,* +B 8900,2400,200,200,CONT_TURN1,* +B 8900,3200,200,200,CONT_TURN1,* +V 9700,6100,CONT_DIF_P,* +V 9700,3200,CONT_DIF_N,* +V 10800,1000,CONT_DIF_N,* +V 11000,8000,CONT_DIF_P,* +V 9700,8000,CONT_DIF_P,* +V 2100,6000,CONT_DIF_P,* +V 2100,1700,CONT_DIF_N,* +V 2100,3200,CONT_DIF_N,* +V 6500,2400,CONT_POLY,* +V 8200,2400,CONT_POLY,* +V 4200,2400,CONT_DIF_N,* +V 3400,2400,CONT_POLY,* +V 9700,2000,CONT_DIF_N,* +V 4200,6000,CONT_POLY,* +V 7000,5000,CONT_POLY,* +V 6400,1700,CONT_DIF_N,* +V 4300,7100,CONT_DIF_P,* +V 800,7900,CONT_DIF_P,* +V 12000,3000,CONT_DIF_N,* +V 12000,2000,CONT_DIF_N,* +V 8600,6000,CONT_POLY,* +V 8600,4000,CONT_POLY,* +V 3400,7000,CONT_POLY,* +V 800,2000,CONT_DIF_N,* +V 12000,6000,CONT_DIF_P,* +V 12000,8000,CONT_DIF_P,* +V 12000,7000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 6400,8000,CONT_DIF_P,* +V 5000,5000,CONT_POLY,* +V 13000,2000,CONT_DIF_N,* +V 13000,3000,CONT_DIF_N,* +V 13000,6000,CONT_DIF_P,* +V 13000,7000,CONT_DIF_P,* +V 11000,4000,CONT_POLY,* +V 13000,8000,CONT_DIF_P,* +V 13000,9200,CONT_DIF_P,* +V 7600,9200,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +V 13000,0,CONT_BODY_P,* +V 13000,10000,CONT_BODY_N,* +V 14000,0,CONT_BODY_P,* +V 14000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/mx3_x4.vbe b/pdks/symbolic/nsxlib2/cells/mx3_x4.vbe new file mode 100644 index 000000000..77baa4489 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/mx3_x4.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 810; + CONSTANT rdown_cmd1_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_cmd0_q : NATURAL := 890; + CONSTANT rup_cmd1_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 640; + CONSTANT tphh_cmd0_q : NATURAL := 683; + CONSTANT tphh_i1_q : NATURAL := 770; + CONSTANT tphh_i2_q : NATURAL := 770; + CONSTANT tpll_i0_q : NATURAL := 774; + CONSTANT tpll_cmd0_q : NATURAL := 779; + CONSTANT tphh_cmd1_q : NATURAL := 792; + CONSTANT tplh_cmd0_q : NATURAL := 844; + CONSTANT tplh_cmd1_q : NATURAL := 846; + CONSTANT tphl_cmd1_q : NATURAL := 872; + CONSTANT tphl_cmd0_q : NATURAL := 922; + CONSTANT tpll_i1_q : NATURAL := 948; + CONSTANT tpll_i2_q : NATURAL := 948; + CONSTANT tpll_cmd1_q : NATURAL := 967; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x4; + +ARCHITECTURE behaviour_data_flow OF mx3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx3_x4" + SEVERITY WARNING; + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) + and i2)))) after 1600 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/na2_x1.ap b/pdks/symbolic/nsxlib2/cells/na2_x1.ap new file mode 100644 index 000000000..bcc0e29a2 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na2_x1.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H na2_x1,P,14/ 8/2024,100 +A 0,0,4000,10000 +R 1000,3000,ref_ref,i0_15 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 1000,7000,ref_ref,i0_35 +R 2000,7000,ref_ref,nq_35 +R 2000,8000,ref_ref,nq_40 +R 3000,7000,ref_ref,i1_35 +R 3000,6000,ref_ref,i1_30 +R 3000,5000,ref_ref,i1_25 +R 3000,4000,ref_ref,i1_20 +R 3000,3000,ref_ref,i1_15 +R 2000,2000,ref_ref,nq_10 +R 2000,3000,ref_ref,nq_15 +R 2000,4000,ref_ref,nq_20 +R 2000,5000,ref_ref,nq_25 +R 2000,6000,ref_ref,nq_30 +S 800,4000,1600,4000,500,*,LEFT,POLY +S 2000,2000,3000,2000,400,*,RIGHT,ALU1 +S 3000,1500,3000,3500,400,*,UP,NDIF +S 1000,1500,1000,3500,400,*,UP,NDIF +S 1000,6500,1000,9400,400,*,UP,PDIF +S 3100,6500,3100,9400,400,*,UP,PDIF +S 3000,7800,3000,8800,300,*,UP,ALU1 +S 2500,6500,2500,9400,200,*,UP,PTRANS +S 2400,4000,3200,4000,500,*,LEFT,POLY +S 2500,4000,2500,6500,200,*,UP,POLY +S 2500,3500,2500,4200,200,*,UP,POLY +S 2500,1500,2500,3500,200,*,UP,NTRANS +S 1000,1200,1000,2200,300,*,UP,ALU1 +S 1500,1500,1500,3500,200,*,UP,NTRANS +S 1500,3500,1500,6500,200,*,UP,POLY +S 1500,6500,1500,9400,200,*,UP,PTRANS +S 1000,7800,1000,8800,300,*,UP,ALU1 +S 2000,6500,2000,9400,400,*,UP,PDIF +S 2000,1500,2000,3500,400,*,UP,NDIF +S 3000,6500,3000,9400,600,*,UP,PDIF +S 2000,1800,2000,8200,300,*,UP,ALU1 +S 2000,1800,2000,8200,300,nq,UP,CALU1 +S 1000,2600,1000,7200,300,*,UP,ALU1 +S 1000,2600,1000,7200,300,i0,UP,CALU1 +S 3000,2800,3000,7200,300,i1,UP,CALU1 +S 3000,2800,3000,7200,300,*,UP,ALU1 +S -500,7500,4500,7500,6000,*,RIGHT,NWELL +S -200,10000,4200,10000,400,*,RIGHT,NTIE +S -200,0,4200,0,400,*,RIGHT,PTIE +S -200,500,4200,500,1400,vss,RIGHT,CALU1 +S -200,9500,4200,9500,1400,vdd,RIGHT,CALU1 +V 1000,4000,CONT_POLY,* +V 3000,9000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 1000,9000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 3000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/na2_x1.vbe b/pdks/symbolic/nsxlib2/cells/na2_x1.vbe new file mode 100644 index 000000000..486b6aaf0 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 59; + CONSTANT tphl_i1_nq : NATURAL := 111; + CONSTANT tplh_i1_nq : NATURAL := 234; + CONSTANT tplh_i0_nq : NATURAL := 288; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x1; + +ARCHITECTURE behaviour_data_flow OF na2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x1" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 900 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/na2_x4.ap b/pdks/symbolic/nsxlib2/cells/na2_x4.ap new file mode 100644 index 000000000..da9077f5a --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na2_x4.ap @@ -0,0 +1,103 @@ +V ALLIANCE : 6 +H na2_x4,P,14/ 8/2024,100 +A 0,0,7000,10000 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 4000,4000,ref_ref,nq_20 +R 4000,3000,ref_ref,nq_15 +R 4000,2000,ref_ref,nq_10 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 4000,5000,ref_ref,nq_25 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +S 1000,2600,1000,6600,200,*,UP,POLY +S 3500,2600,3500,4200,200,*,UP,POLY +S 4500,2500,4500,3800,200,*,UP,POLY +S 5700,2500,5700,5500,200,*,UP,POLY +S 2500,6500,2500,9400,600,*,UP,PDIF +S 500,6500,500,9400,600,*,UP,PDIF +S 4000,5500,4000,9400,400,*,UP,PDIF +S 4000,600,4000,2600,400,*,UP,NDIF +S 2700,600,2700,2600,1000,*,UP,NDIF +S 1300,8000,6000,8000,300,*,RIGHT,ALU1 +S 300,2000,3200,2000,300,*,RIGHT,ALU1 +S 3000,5500,3000,9400,400,*,UP,PDIF +S 2000,6500,2000,9400,200,*,UP,PTRANS +S 1500,6500,1500,9400,400,*,UP,PDIF +S 1000,6500,1000,9400,200,*,UP,PTRANS +S 500,7800,500,8900,300,*,UP,ALU1 +S 2000,2600,2000,6600,200,*,UP,POLY +S 2000,600,2000,2600,200,*,UP,NTRANS +S 1500,600,1500,2600,400,*,UP,NDIF +S 1000,600,1000,2600,200,*,UP,NTRANS +S 500,600,500,2600,400,*,UP,NDIF +S 3500,4000,5200,4000,500,*,RIGHT,POLY +S 5000,800,5000,2100,300,*,UP,ALU1 +S 6200,1800,6200,7200,300,*,UP,ALU1 +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 3500,3800,3500,5600,200,*,UP,POLY +S 3500,600,3500,2600,200,*,UP,NTRANS +S 5200,5500,5200,7500,600,*,UP,PDIF +S 5300,1500,5300,2600,400,*,UP,NDIF +S 6200,1500,6200,2600,400,*,UP,NDIF +S 4500,3800,4500,5600,200,*,UP,POLY +S 5700,7500,5700,8100,200,*,UP,POLY +S -600,7500,7500,7500,6000,*,RIGHT,NWELL +S 3000,1800,3000,8200,300,*,UP,ALU1 +S 4900,4000,6300,4000,300,*,RIGHT,ALU1 +S 5700,1500,5700,2600,200,*,UP,NTRANS +S 5000,600,5000,2600,400,*,UP,NDIF +S 4500,600,4500,2600,200,*,UP,NTRANS +S 1000,2800,1000,7200,300,i0,UP,CALU1 +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 2000,2800,2000,7200,300,i1,UP,CALU1 +S 2000,2800,2000,7200,300,*,UP,ALU1 +S 4000,1800,4000,7200,300,*,UP,ALU1 +S 4000,1800,4000,7200,300,nq,UP,CALU1 +S 6200,5500,6200,7500,600,*,UP,PDIF +S 5000,5500,5000,9400,400,*,UP,PDIF +S 4500,5500,4500,9400,200,*,UP,PTRANS +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S -200,10000,7200,10000,400,*,RIGHT,NTIE +S -200,0,7200,0,400,*,RIGHT,PTIE +S 5700,5500,5700,7500,200,*,UP,PTRANS +V 2700,9100,CONT_DIF_P,* +V 2800,900,CONT_DIF_N,* +V 1500,8000,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 500,2000,CONT_DIF_N,* +V 5000,1900,CONT_DIF_N,* +V 6200,2000,CONT_DIF_N,* +V 6200,6000,CONT_DIF_P,* +V 6200,7000,CONT_DIF_P,* +V 5000,9100,CONT_DIF_P,* +V 5100,4000,CONT_POLY,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 5800,8000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/na2_x4.vbe b/pdks/symbolic/nsxlib2/cells/na2_x4.vbe new file mode 100644 index 000000000..c73eca058 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 353; + CONSTANT tphl_i0_nq : NATURAL := 412; + CONSTANT tplh_i0_nq : NATURAL := 552; + CONSTANT tplh_i1_nq : NATURAL := 601; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x4; + +ARCHITECTURE behaviour_data_flow OF na2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x4" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/na3_x1.ap b/pdks/symbolic/nsxlib2/cells/na3_x1.ap new file mode 100644 index 000000000..586e36308 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na3_x1.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H na3_x1,P,14/ 8/2024,100 +A 0,0,5000,10000 +R 3000,5000,ref_ref,i2_25 +R 3000,6000,ref_ref,i2_30 +R 2000,2000,ref_ref,i1_10 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,2000,ref_ref,i0_10 +R 1000,3000,ref_ref,i0_15 +R 4000,7000,ref_ref,nq_35 +R 4000,5000,ref_ref,nq_25 +R 4000,6000,ref_ref,nq_30 +R 4000,4000,ref_ref,nq_20 +R 4000,3000,ref_ref,nq_15 +R 4000,2000,ref_ref,nq_10 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 3000,3000,ref_ref,i2_15 +R 3000,4000,ref_ref,i2_20 +S 2000,3900,2000,6700,200,*,UP,POLY +S 2500,7800,2500,9100,300,*,UP,ALU1 +S 1500,7200,1500,8500,300,*,UP,ALU1 +S 3000,2800,3000,6500,200,*,UP,POLY +S 1300,7100,4200,7100,400,*,RIGHT,ALU1 +S 2800,2000,4000,2000,400,*,LEFT,ALU1 +S 2500,2500,2500,2800,200,*,UP,POLY +S 2400,2800,3100,2800,200,*,RIGHT,POLY +S 3500,7000,3500,8500,300,*,UP,ALU1 +S 1000,1800,1000,6200,300,i0,UP,CALU1 +S 1000,1800,1000,6200,300,*,UP,ALU1 +S 3500,6500,3500,9400,400,*,UP,PDIF +S 2600,6500,2600,9400,600,*,UP,PDIF +S 1500,600,1500,2500,600,*,DOWN,NDIF +S 500,600,500,2500,400,*,UP,NDIF +S 2500,600,2500,2500,200,*,UP,NTRANS +S 2000,6500,2000,9400,200,*,UP,PTRANS +S 1500,6500,1500,9400,400,*,UP,PDIF +S 1000,5000,1000,6500,200,*,UP,POLY +S 1000,2500,1000,5200,200,*,UP,POLY +S 1000,6500,1000,9400,200,*,UP,PTRANS +S 500,6500,500,9400,600,*,UP,PDIF +S 500,7700,500,8900,300,*,UP,ALU1 +S 1000,600,1000,2500,200,*,UP,NTRANS +S 2300,600,2300,2500,200,*,DOWN,NDIF +S 4000,1800,4000,7200,300,*,UP,ALU1 +S 4000,1800,4000,7200,300,nq,UP,CALU1 +S 2000,2400,2000,4100,200,*,UP,POLY +S 3000,6500,3000,9400,200,*,UP,PTRANS +S 3000,600,3000,2500,400,*,DOWN,NDIF +S 3000,2800,3000,6200,300,*,UP,ALU1 +S 3000,2800,3000,6200,300,i2,UP,CALU1 +S 2000,600,2000,2500,200,*,UP,NTRANS +S 2000,1800,2000,6200,300,i1,UP,CALU1 +S 2000,1800,2000,6200,300,*,UP,ALU1 +S -200,9500,5200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,5200,500,1400,vss,RIGHT,CALU1 +S -500,7500,5500,7500,6000,*,RIGHT,NWELL +S -200,10000,5200,10000,400,*,RIGHT,NTIE +S -200,0,5200,0,400,*,RIGHT,PTIE +V 1000,4000,CONT_POLY,* +V 2500,9000,CONT_DIF_P,* +V 500,9000,CONT_DIF_P,* +V 3000,3000,CONT_POLY,* +V 1500,7300,CONT_DIF_P,* +V 3500,8300,CONT_DIF_P,* +V 3500,7300,CONT_DIF_P,* +V 2500,8000,CONT_DIF_P,* +V 1500,8300,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 500,1000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 2000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/na3_x1.vbe b/pdks/symbolic/nsxlib2/cells/na3_x1.vbe new file mode 100644 index 000000000..d51e12075 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 4120; + CONSTANT rdown_i1_nq : NATURAL := 4120; + CONSTANT rdown_i2_nq : NATURAL := 4120; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 119; + CONSTANT tphl_i1_nq : NATURAL := 171; + CONSTANT tphl_i2_nq : NATURAL := 193; + CONSTANT tplh_i2_nq : NATURAL := 265; + CONSTANT tplh_i1_nq : NATURAL := 316; + CONSTANT tplh_i0_nq : NATURAL := 363; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x1; + +ARCHITECTURE behaviour_data_flow OF na3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/na3_x4.ap b/pdks/symbolic/nsxlib2/cells/na3_x4.ap new file mode 100644 index 000000000..f9fe9028f --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na3_x4.ap @@ -0,0 +1,122 @@ +V ALLIANCE : 6 +H na3_x4,P,14/ 8/2024,100 +A 0,0,8000,10000 +R 2000,5000,ref_ref,i2_25 +R 2000,4000,ref_ref,i2_20 +R 2000,3000,ref_ref,i2_15 +R 3000,5000,ref_ref,i1_25 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 1000,7000,ref_ref,i0_35 +R 3000,4000,ref_ref,i1_20 +R 3000,3000,ref_ref,i1_15 +R 5000,2000,ref_ref,nq_10 +R 5000,3000,ref_ref,nq_15 +R 5000,4000,ref_ref,nq_20 +R 5000,5000,ref_ref,nq_25 +R 2000,7000,ref_ref,i2_35 +R 2000,6000,ref_ref,i2_30 +R 3000,6000,ref_ref,i1_30 +R 3000,7000,ref_ref,i1_35 +R 1000,6000,ref_ref,i0_30 +S 6800,7400,6800,8000,200,*,UP,POLY +S 5500,3500,5500,5600,200,*,UP,POLY +S -500,7500,8600,7500,6000,*,RIGHT,NWELL +S 500,1500,500,3500,400,*,UP,NDIF +S 6000,600,6000,3500,400,*,UP,NDIF +S 6000,5500,6000,9400,400,*,UP,PDIF +S 6300,5500,6300,7500,400,*,UP,PDIF +S 6300,1500,6300,3500,400,*,UP,NDIF +S 1500,1500,1500,3500,600,*,UP,NDIF +S 1500,6300,1500,9400,400,*,UP,PDIF +S 1300,1500,1300,3500,200,*,UP,NDIF +S 7300,1800,7300,7200,300,*,UP,ALU1 +S 4500,4000,5900,4000,500,*,RIGHT,POLY +S 2500,6300,2500,9400,400,*,UP,PDIF +S 6000,1200,6000,3300,300,*,UP,ALU1 +S 5500,600,5500,3500,200,*,UP,NTRANS +S 4500,600,4500,3500,200,*,UP,NTRANS +S 4500,2700,4500,4200,200,*,UP,POLY +S 4500,3600,4500,5600,200,*,UP,POLY +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 3900,600,3900,3500,800,*,UP,NDIF +S 3500,1500,3500,3500,400,*,UP,NDIF +S 2500,1500,2500,3500,400,*,UP,NDIF +S 3000,3500,3000,6400,200,*,UP,POLY +S 2000,3500,2000,4900,200,*,UP,POLY +S 2000,1500,2000,3500,200,*,UP,NTRANS +S 2000,4900,2000,6400,200,*,UP,POLY +S 3000,1500,3000,3500,200,*,UP,NTRANS +S 3000,6300,3000,9400,200,*,UP,PTRANS +S 2000,6300,2000,9400,200,*,UP,PTRANS +S 5000,5500,5000,9400,400,*,UP,PDIF +S 1000,3500,1000,6400,200,*,UP,POLY +S 6800,2700,6800,5500,200,*,UP,POLY +S 3600,6300,3600,9400,800,*,DOWN,PDIF +S 4200,5500,4200,9400,400,*,UP,PDIF +S 400,2000,3900,2000,300,*,RIGHT,ALU1 +S 3700,1800,3700,8200,300,*,UP,ALU1 +S 5800,4000,7400,4000,300,*,RIGHT,ALU1 +S 7300,1500,7300,3500,400,*,UP,NDIF +S 6800,1500,6800,3500,200,*,UP,NTRANS +S 5000,600,5000,3500,400,*,UP,NDIF +S 500,6300,500,9400,400,*,UP,PDIF +S 1000,6300,1000,9400,200,*,UP,PTRANS +S 400,8000,7000,8000,300,*,RIGHT,ALU1 +S 1000,1500,1000,3500,200,*,UP,NTRANS +S 5000,1800,5000,7200,300,*,UP,ALU1 +S 5000,1800,5000,7200,300,nq,UP,CALU1 +S 1000,2800,1000,7200,300,i0,UP,CALU1 +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 2000,2800,2000,7200,300,*,UP,ALU1 +S 2000,2800,2000,7200,300,i2,UP,CALU1 +S 3000,2800,3000,7200,300,*,UP,ALU1 +S 3000,2800,3000,7200,300,i1,UP,CALU1 +S 7300,5500,7300,7500,400,*,UP,PDIF +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,0,8200,0,400,*,RIGHT,PTIE +S 1000,4000,1200,4000,400,*,RIGHT,POLY +S 6800,5500,6800,7500,200,*,UP,PTRANS +S -200,500,8200,500,1400,vss,RIGHT,CALU1 +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +V 3000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 3700,9000,CONT_DIF_P,* +V 7300,6000,CONT_DIF_P,* +V 7300,7000,CONT_DIF_P,* +V 7300,2000,CONT_DIF_N,* +V 4000,900,CONT_DIF_N,* +V 6000,3100,CONT_DIF_N,* +V 6000,1300,CONT_DIF_N,* +V 6000,9000,CONT_DIF_P,* +V 2500,8000,CONT_DIF_P,* +V 1500,9000,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 5000,3000,CONT_DIF_N,* +V 6800,8000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 5000,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 5000,7000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/na3_x4.vbe b/pdks/symbolic/nsxlib2/cells/na3_x4.vbe new file mode 100644 index 000000000..160a97f61 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 460; + CONSTANT tphl_i2_nq : NATURAL := 519; + CONSTANT tphl_i0_nq : NATURAL := 556; + CONSTANT tplh_i0_nq : NATURAL := 601; + CONSTANT tplh_i2_nq : NATURAL := 647; + CONSTANT tplh_i1_nq : NATURAL := 691; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x4; + +ARCHITECTURE behaviour_data_flow OF na3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/na4_x1.ap b/pdks/symbolic/nsxlib2/cells/na4_x1.ap new file mode 100644 index 000000000..9f5c934a7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na4_x1.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H na4_x1,P,14/ 8/2024,100 +A 0,0,6000,10000 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_10 +R 1000,2000,ref_ref,i0_10 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 4000,4000,ref_ref,i3_20 +R 4000,3000,ref_ref,i3_15 +R 3000,2000,ref_ref,i2_10 +R 3000,3000,ref_ref,i2_15 +R 3000,4000,ref_ref,i2_20 +R 3000,5000,ref_ref,i2_25 +R 3000,6000,ref_ref,i2_30 +R 3000,7000,ref_ref,i2_35 +R 2000,7000,ref_ref,i1_35 +R 5000,8000,ref_ref,nq_40 +R 5000,2000,ref_ref,nq_10 +R 5000,3000,ref_ref,nq_15 +R 5000,4000,ref_ref,nq_20 +R 5000,5000,ref_ref,nq_25 +R 5000,6000,ref_ref,nq_30 +R 5000,7000,ref_ref,nq_35 +R 4000,7000,ref_ref,i3_35 +R 4000,6000,ref_ref,i3_30 +R 4000,5000,ref_ref,i3_25 +R 2000,6000,ref_ref,i1_30 +S 1000,2400,1000,6500,200,*,UP,POLY +S 4000,2300,4000,6600,200,*,UP,POLY +S 4300,2000,5200,2000,500,*,LEFT,ALU1 +S 1600,8000,5000,8000,300,*,RIGHT,ALU1 +S -500,7500,6600,7500,6000,*,RIGHT,NWELL +S 4500,600,4500,2500,400,*,UP,NDIF +S 500,6500,500,9400,400,*,UP,PDIF +S 1500,600,1500,2500,600,*,UP,NDIF +S 2500,600,2500,2500,600,*,UP,NDIF +S 2500,6500,2500,9400,400,*,UP,PDIF +S 3500,6500,3500,9400,400,*,UP,PDIF +S 3500,600,3500,2500,600,*,UP,NDIF +S 3000,2500,3000,6500,200,*,UP,POLY +S 4000,600,4000,2500,200,*,UP,NTRANS +S 4500,6500,4500,9400,400,*,UP,PDIF +S 4000,6500,4000,9400,200,*,UP,PTRANS +S 3000,600,3000,2500,200,*,UP,NTRANS +S 2000,3900,2000,6500,200,*,UP,POLY +S 2000,6500,2000,9400,200,*,UP,PTRANS +S 1500,6500,1500,9400,400,*,UP,PDIF +S 1000,6500,1000,9400,200,*,UP,PTRANS +S 1000,600,1000,2500,200,*,UP,NTRANS +S 500,600,500,2500,400,*,UP,NDIF +S 500,7800,500,8800,300,*,UP,ALU1 +S 4000,2800,4000,7200,300,i3,UP,CALU1 +S 4000,2800,4000,7200,300,*,UP,ALU1 +S 2000,2500,2000,3900,200,*,UP,POLY +S 2000,600,2000,2500,200,*,UP,NTRANS +S 3000,6500,3000,9400,200,*,UP,PTRANS +S 5000,1800,5000,8200,300,*,UP,ALU1 +S 5000,1800,5000,8200,300,nq,UP,CALU1 +S 1000,1800,1000,7200,300,i0,UP,CALU1 +S 1000,1800,1000,7200,300,*,UP,ALU1 +S 2000,1800,2000,7200,300,i1,UP,CALU1 +S 2000,1800,2000,7200,300,*,UP,ALU1 +S 3000,1800,3000,7200,300,i2,UP,CALU1 +S 3000,1800,3000,7200,300,*,UP,ALU1 +S -200,9500,6200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,6200,500,1400,vss,RIGHT,CALU1 +S -200,10000,6200,10000,400,*,RIGHT,NTIE +S -200,0,6200,0,400,*,RIGHT,PTIE +V 4500,2000,CONT_DIF_N,* +V 4500,9100,CONT_DIF_P,* +V 3500,8000,CONT_DIF_P,* +V 2500,9100,CONT_DIF_P,* +V 1500,8000,CONT_DIF_P,* +V 500,900,CONT_DIF_N,* +V 500,9100,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 3000,4000,CONT_POLY,* +V 4000,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/na4_x1.vbe b/pdks/symbolic/nsxlib2/cells/na4_x1.vbe new file mode 100644 index 000000000..07f51ce0b --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 5400; + CONSTANT rdown_i1_nq : NATURAL := 5400; + CONSTANT rdown_i2_nq : NATURAL := 5400; + CONSTANT rdown_i3_nq : NATURAL := 5400; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT rup_i3_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 179; + CONSTANT tphl_i1_nq : NATURAL := 237; + CONSTANT tphl_i2_nq : NATURAL := 269; + CONSTANT tphl_i3_nq : NATURAL := 282; + CONSTANT tplh_i3_nq : NATURAL := 302; + CONSTANT tplh_i2_nq : NATURAL := 350; + CONSTANT tplh_i1_nq : NATURAL := 395; + CONSTANT tplh_i0_nq : NATURAL := 438; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x1; + +ARCHITECTURE behaviour_data_flow OF na4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/na4_x4.ap b/pdks/symbolic/nsxlib2/cells/na4_x4.ap new file mode 100644 index 000000000..9276253be --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na4_x4.ap @@ -0,0 +1,141 @@ +V ALLIANCE : 6 +H na4_x4,P,14/ 8/2024,100 +A 0,0,9000,10000 +R 7000,7000,ref_ref,i3_35 +R 7000,6000,ref_ref,i3_30 +R 7000,5000,ref_ref,i3_25 +R 7000,2000,ref_ref,i3_10 +R 7000,3000,ref_ref,i3_15 +R 7000,4000,ref_ref,i3_20 +R 6000,2000,ref_ref,i2_10 +R 6000,3000,ref_ref,i2_15 +R 6000,4000,ref_ref,i2_20 +R 6000,7000,ref_ref,i2_35 +R 6000,6000,ref_ref,i2_30 +R 6000,5000,ref_ref,i2_25 +R 5000,2000,ref_ref,i1_10 +R 5000,7000,ref_ref,i1_35 +R 5000,6000,ref_ref,i1_30 +R 5000,5000,ref_ref,i1_25 +R 5000,3000,ref_ref,i1_15 +R 5000,4000,ref_ref,i1_20 +R 4000,2000,ref_ref,i0_10 +R 4000,3000,ref_ref,i0_15 +R 4000,4000,ref_ref,i0_20 +R 4000,5000,ref_ref,i0_25 +R 4000,6000,ref_ref,i0_30 +R 4000,7000,ref_ref,i0_35 +R 3000,3000,ref_ref,nq_15 +R 3000,4000,ref_ref,nq_20 +R 3000,2000,ref_ref,nq_10 +R 3000,7000,ref_ref,nq_35 +R 3000,6000,ref_ref,nq_30 +R 3000,5000,ref_ref,nq_25 +S 3400,5500,3400,9400,400,*,UP,PDIF +S 1600,5500,1600,9400,400,*,UP,PDIF +S 6000,2400,6000,5200,200,*,UP,POLY +S 5000,2400,5000,6700,200,*,UP,POLY +S 3000,2400,3000,5700,200,*,UP,POLY +S 2000,2400,2000,5600,200,*,UP,POLY +S 1000,2500,1000,3200,200,*,UP,POLY +S 1000,4600,1000,5600,200,*,UP,POLY +S 4000,2400,4000,6600,200,*,DOWN,POLY +S 6000,4900,6000,6700,200,*,UP,POLY +S 7000,3900,7000,6600,200,*,UP,POLY +S 2300,2000,3200,2000,500,*,LEFT,ALU1 +S 2300,6000,3200,6000,500,*,LEFT,ALU1 +S 2300,7000,3200,7000,500,*,LEFT,ALU1 +S 500,5500,500,7500,400,*,UP,PDIF +S 500,600,500,2500,400,*,UP,NDIF +S 7600,600,7600,2500,600,*,UP,NDIF +S 7500,6500,7500,9400,400,*,UP,PDIF +S 6400,600,6400,2500,600,*,UP,NDIF +S 5500,600,5500,2500,600,*,UP,NDIF +S 2500,600,2500,2500,600,*,UP,NDIF +S 4500,600,4500,2500,600,*,UP,NDIF +S 1500,600,1500,2500,400,*,UP,NDIF +S 5500,6500,5500,9400,400,*,UP,PDIF +S 1000,8000,7900,8000,300,*,RIGHT,ALU1 +S 4500,6500,4500,9400,400,*,UP,PDIF +S 3500,6500,3500,9400,600,*,UP,PDIF +S 2500,5500,2500,9400,600,*,UP,PDIF +S 1500,5500,1500,7500,400,*,UP,PDIF +S 7000,2500,7000,4000,200,*,UP,POLY +S 3500,600,3500,2500,600,*,UP,NDIF +S 400,4000,3100,4000,400,*,RIGHT,POLY +S 3000,600,3000,2500,200,*,UP,NTRANS +S 3000,5500,3000,9400,200,*,UP,PTRANS +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 2000,600,2000,2500,200,*,UP,NTRANS +S 1200,2800,1200,8200,300,*,UP,ALU1 +S 1000,5500,1000,7500,200,*,UP,PTRANS +S 1000,600,1000,2500,200,*,UP,NTRANS +S 500,1800,500,7200,300,*,UP,ALU1 +S 4000,6500,4000,9400,200,*,UP,PTRANS +S 5000,6500,5000,9400,200,*,UP,PTRANS +S 6000,6500,6000,9400,200,*,UP,PTRANS +S 7000,6500,7000,9400,200,*,UP,PTRANS +S 4000,600,4000,2500,200,*,UP,NTRANS +S 5000,600,5000,2500,200,*,UP,NTRANS +S 7000,600,7000,2500,200,*,UP,NTRANS +S 6500,6500,6500,9400,400,*,UP,PDIF +S -200,0,9200,0,400,*,RIGHT,PTIE +S -200,500,9200,500,1400,vss,RIGHT,CALU1 +S -500,7500,9500,7500,6000,*,RIGHT,NWELL +S -200,10000,9200,10000,400,*,RIGHT,NTIE +S -200,9500,9200,9500,1400,vdd,RIGHT,CALU1 +S 7700,1800,7700,8200,300,*,UP,ALU1 +S 7000,1800,7000,7200,300,*,UP,ALU1 +S 7000,1800,7000,7200,300,i3,UP,CALU1 +S 6000,600,6000,2500,200,*,UP,NTRANS +S 6000,1800,6000,7200,300,i2,UP,CALU1 +S 6000,1800,6000,7200,300,*,UP,ALU1 +S 5000,1800,5000,7200,300,*,UP,ALU1 +S 5000,1800,5000,7200,300,i1,UP,CALU1 +S 4000,1800,4000,7200,300,*,UP,ALU1 +S 4000,1800,4000,7200,300,i0,UP,CALU1 +S 3000,1800,3000,7200,300,*,UP,ALU1 +S 3000,1800,3000,7200,300,nq,UP,CALU1 +V 7500,9000,CONT_DIF_P,* +V 5500,9000,CONT_DIF_P,* +V 1500,9000,CONT_DIF_P,* +V 3500,9000,CONT_DIF_P,* +V 6000,4000,CONT_POLY,* +V 1200,4800,CONT_POLY,* +V 2500,2000,CONT_DIF_N,* +V 2500,6000,CONT_DIF_P,* +V 2500,7000,CONT_DIF_P,* +V 1500,900,CONT_DIF_N,* +V 1200,3000,CONT_POLY,* +V 500,2000,CONT_DIF_N,* +V 500,4000,CONT_POLY,* +V 500,6000,CONT_DIF_P,* +V 500,7000,CONT_DIF_P,* +V 4500,8000,CONT_DIF_P,* +V 6500,8000,CONT_DIF_P,* +V 3500,900,CONT_DIF_N,* +V 7700,2000,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 7000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/na4_x4.vbe b/pdks/symbolic/nsxlib2/cells/na4_x4.vbe new file mode 100644 index 000000000..a67d18901 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/na4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 578; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i3_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 681; + CONSTANT tplh_i2_nq : NATURAL := 689; + CONSTANT tphl_i3_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 731; + CONSTANT tplh_i0_nq : NATURAL := 771; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x4; + +ARCHITECTURE behaviour_data_flow OF na4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/nao22_x1.ap b/pdks/symbolic/nsxlib2/cells/nao22_x1.ap new file mode 100644 index 000000000..771ab90cd --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nao22_x1.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 6 +H nao22_x1,P,17/ 8/2024,100 +A 0,0,5000,10000 +R 3000,5000,ref_ref,nq_20 +R 3000,4000,ref_ref,nq_25 +R 4000,5000,ref_ref,i2_35 +R 4000,7000,ref_ref,i2_25 +R 1000,8000,ref_ref,i0_40 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 3000,7000,ref_ref,nq_35 +R 3000,6000,ref_ref,nq_30 +R 4000,2000,ref_ref,i2_10 +R 4000,8000,ref_ref,i2_40 +R 3000,8000,ref_ref,nq_40 +R 2000,8000,ref_ref,i1_40 +R 3000,3000,ref_ref,nq_15 +R 4000,6000,ref_ref,i2_30 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 2000,4000,ref_ref,i1_20 +R 1000,7000,ref_ref,i0_35 +R 2000,7000,ref_ref,i1_35 +S 3200,5000,3200,5500,200,*,DOWN,POLY +S 3200,2500,3200,3100,200,*,UP,POLY +S 4000,3100,4000,5000,200,*,UP,POLY +S 3100,5000,4100,5000,200,*,LEFT,POLY +S 3100,3100,4100,3100,200,*,LEFT,POLY +S 3900,5500,3900,9400,800,*,UP,PDIF +S 2000,4200,2000,5700,200,*,UP,POLY +S 2000,2600,2000,4300,200,*,UP,POLY +S 1500,2400,1500,3200,500,*,DOWN,ALU1 +S 1400,3000,3000,3000,400,*,RIGHT,ALU1 +S 2600,6000,3100,6000,400,*,RIGHT,ALU1 +S 2600,8000,3100,8000,400,*,RIGHT,ALU1 +S 1500,5500,1500,9400,600,*,UP,PDIF +S 500,5500,500,9400,400,*,UP,PDIF +S 2600,5500,2600,9400,600,*,UP,PDIF +S 2600,600,2600,2600,600,*,UP,NDIF +S 500,600,500,2600,400,*,UP,NDIF +S 1000,4000,1000,5600,200,*,UP,POLY +S 3700,600,3700,2600,600,*,UP,NDIF +S 3200,600,3200,2600,200,*,UP,NTRANS +S 3200,5500,3200,9400,200,*,UP,PTRANS +S 1000,2600,1000,4000,200,*,UP,POLY +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 2000,600,2000,2600,200,*,UP,NTRANS +S 500,1700,2500,1700,300,*,RIGHT,ALU1 +S 1500,600,1500,2600,400,*,UP,NDIF +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 1000,600,1000,2600,200,*,UP,NTRANS +S 2000,3800,2000,8200,300,i1,UP,CALU1 +S 2000,3800,2000,8200,300,*,UP,ALU1 +S 1000,3800,1000,8200,300,i0,UP,CALU1 +S 1000,3800,1000,8200,300,*,UP,ALU1 +S 3000,2800,3000,8200,300,*,UP,ALU1 +S 3000,2800,3000,8200,300,nq,UP,CALU1 +S 4000,1800,4000,8200,300,i2,UP,CALU1 +S 4000,1800,4000,8200,300,*,UP,ALU1 +S -200,10000,5200,10000,400,*,RIGHT,NTIE +S -200,9500,5200,9500,1400,vdd,RIGHT,CALU1 +S -200,0,5200,0,400,*,RIGHT,PTIE +S -200,500,5200,500,1400,vss,RIGHT,CALU1 +S -500,7500,5500,7500,6000,*,RIGHT,NWELL +V 3700,1000,CONT_DIF_N,* +V 500,9000,CONT_DIF_P,* +V 3700,9000,CONT_DIF_P,* +V 2700,6000,CONT_DIF_P,* +V 2700,8000,CONT_DIF_P,* +V 2500,1700,CONT_DIF_N,* +V 1500,2400,CONT_DIF_N,* +V 500,1700,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/nao22_x1.vbe b/pdks/symbolic/nsxlib2/cells/nao22_x1.vbe new file mode 100644 index 000000000..13c4e6dec --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nao22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 1790; + CONSTANT tphl_i2_nq : NATURAL := 165; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tplh_i2_nq : NATURAL := 238; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x1; + +ARCHITECTURE behaviour_data_flow OF nao22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 900 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/nao22_x4.ap b/pdks/symbolic/nsxlib2/cells/nao22_x4.ap new file mode 100644 index 000000000..c5ca193cc --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nao22_x4.ap @@ -0,0 +1,152 @@ +V ALLIANCE : 6 +H nao22_x4,P,14/ 8/2024,100 +A 0,0,10000,10000 +R 8000,7000,ref_ref,nq_35 +R 8000,6000,ref_ref,nq_30 +R 8000,4000,ref_ref,nq_20 +R 8000,2000,ref_ref,nq_10 +R 8000,3000,ref_ref,nq_15 +R 8000,5000,ref_ref,nq_25 +R 4000,4000,ref_ref,i0_20 +R 8000,8000,ref_ref,nq_40 +R 1000,2000,ref_ref,i2_10 +R 1000,5000,ref_ref,i2_25 +R 1000,7000,ref_ref,i2_35 +R 3000,7000,ref_ref,i1_35 +R 4000,7000,ref_ref,i0_35 +R 1000,4000,ref_ref,i2_20 +R 3000,4000,ref_ref,i1_20 +R 3000,5000,ref_ref,i1_25 +R 3000,6000,ref_ref,i1_30 +R 4000,6000,ref_ref,i0_30 +R 4000,5000,ref_ref,i0_25 +R 1000,3000,ref_ref,i2_15 +R 1000,6000,ref_ref,i2_30 +S 3000,6100,3000,7000,200,*,UP,POLY +S 1000,2000,1000,7100,200,*,UP,POLY +S 4000,2000,4000,6200,200,*,UP,POLY +S 8500,2500,8500,5500,200,*,UP,POLY +S 6200,2400,6200,5500,200,*,UP,POLY +S 7500,2400,7500,4100,200,*,UP,POLY +S 7500,3900,7500,5600,200,*,UP,POLY +S 1000,1800,1000,7200,300,*,UP,ALU1 +S 1000,1800,1000,7200,300,i2,UP,CALU1 +S 1600,8000,2100,8000,400,*,RIGHT,ALU1 +S 2000,8000,6300,8000,300,*,RIGHT,ALU1 +S 6300,4800,6300,8000,300,*,UP,ALU1 +S 5600,3900,5600,6200,300,*,UP,ALU1 +S 5600,4000,6900,4000,300,*,RIGHT,ALU1 +S 2000,2700,3400,2700,300,*,RIGHT,ALU1 +S 2000,2700,2000,8200,300,*,UP,ALU1 +S 3500,6900,3500,8900,400,*,DOWN,PDIF +S 500,1100,500,2100,400,*,UP,NDIF +S 4500,1100,4500,2100,400,*,UP,NDIF +S 9000,600,9000,2500,400,*,UP,NDIF +S 9000,5500,9000,9400,400,*,UP,PDIF +S 7000,5500,7000,9400,400,*,UP,PDIF +S 600,6900,600,8900,600,*,UP,PDIF +S 8000,5500,8000,9400,400,*,UP,PDIF +S 3500,8500,3500,8800,300,*,UP,ALU1 +S 1900,6900,1900,8900,400,*,DOWN,PDIF +S 1500,6900,1500,8900,400,*,DOWN,PDIF +S 1600,1100,1600,2100,600,*,UP,NDIF +S 2700,1100,2700,2100,600,*,UP,NDIF +S 5600,1900,5600,3900,300,*,UP,ALU1 +S 7000,600,7000,2500,400,*,UP,NDIF +S 7000,1200,7000,2200,300,*,UP,ALU1 +S 7000,5700,7000,8800,300,*,UP,ALU1 +S 7500,600,7500,2500,200,*,UP,NTRANS +S 8500,600,8500,2500,200,*,UP,NTRANS +S 8500,5500,8500,9400,200,*,UP,PTRANS +S 7500,5500,7500,9400,200,*,UP,PTRANS +S 3200,1100,3200,2900,600,*,UP,NDIF +S -700,7500,10500,7500,6000,*,RIGHT,NWELL +S 3000,6200,4100,6200,200,*,RIGHT,POLY +S 2200,4000,3000,4000,400,*,RIGHT,POLY +S 2700,6900,2700,8900,400,*,DOWN,PDIF +S 2200,2100,2200,6900,200,*,UP,POLY +S 1800,1900,4600,1900,300,*,RIGHT,ALU1 +S 2200,1100,2200,2100,200,*,UP,NTRANS +S 2200,6900,2200,8900,200,*,UP,PTRANS +S 1000,1100,1000,2100,200,*,UP,NTRANS +S 3500,1100,3500,2100,600,*,UP,NDIF +S 4000,1100,4000,2100,200,*,UP,NTRANS +S 2900,1100,2900,2100,600,*,UP,NDIF +S 3000,6900,3000,8900,200,*,UP,PTRANS +S 1000,6900,1000,8900,200,*,UP,PTRANS +S 500,8500,500,8800,300,*,UP,ALU1 +S 500,1200,500,1500,300,*,DOWN,ALU1 +S 6700,5500,6700,7500,400,*,DOWN,PDIF +S 6600,1500,6600,2500,400,*,UP,NDIF +S 6800,4000,8600,4000,400,*,RIGHT,POLY +S 4000,3800,4000,7200,300,*,UP,ALU1 +S 4000,3800,4000,7200,300,i0,UP,CALU1 +S 3000,3800,3000,7200,300,i1,UP,CALU1 +S 3000,3800,3000,7200,300,*,UP,ALU1 +S 9000,5800,9000,8800,300,*,UP,ALU1 +S 5600,5500,5600,7500,600,*,UP,PDIF +S 5600,1500,5600,2500,600,*,UP,NDIF +S 9000,1200,9000,2200,300,*,UP,ALU1 +S 8000,1800,8000,8200,300,nq,UP,CALU1 +S 8000,1800,8000,8200,300,*,UP,ALU1 +S 8000,600,8000,2500,600,*,UP,NDIF +S -200,9500,10200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,10200,500,1400,vss,RIGHT,CALU1 +S 6200,5500,6200,7500,200,*,UP,PTRANS +S 6200,1500,6200,2500,200,*,UP,NTRANS +S -200,10000,10200,10000,400,*,RIGHT,NTIE +S -200,0,10200,0,400,*,RIGHT,PTIE +B 2000,2700,200,200,CONT_TURN1,* +B 6300,8000,200,200,CONT_TURN1,* +V 7000,7000,CONT_DIF_P,* +V 3500,8700,CONT_DIF_P,* +V 7000,900,CONT_DIF_N,* +V 7000,2000,CONT_DIF_N,* +V 7000,5900,CONT_DIF_P,* +V 7000,9200,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 4500,1900,CONT_DIF_N,* +V 1700,1900,CONT_DIF_N,* +V 1700,8000,CONT_DIF_P,* +V 500,8700,CONT_DIF_P,* +V 500,1300,CONT_DIF_N,* +V 6300,5000,CONT_POLY,* +V 3200,2700,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 9000,2000,CONT_DIF_N,* +V 5600,2000,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 8000,2000,CONT_DIF_N,* +V 5600,6000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 9000,900,CONT_DIF_N,* +V 6800,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/nao22_x4.vbe b/pdks/symbolic/nsxlib2/cells/nao22_x4.vbe new file mode 100644 index 000000000..ebdcfc515 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 596; + CONSTANT tplh_i2_nq : NATURAL := 636; + CONSTANT tplh_i0_nq : NATURAL := 650; + CONSTANT tphl_i1_nq : NATURAL := 664; + CONSTANT tplh_i1_nq : NATURAL := 723; + CONSTANT tphl_i0_nq : NATURAL := 732; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x4; + +ARCHITECTURE behaviour_data_flow OF nao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/nao2o22_x1.ap b/pdks/symbolic/nsxlib2/cells/nao2o22_x1.ap new file mode 100644 index 000000000..80c99a0f8 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nao2o22_x1.ap @@ -0,0 +1,105 @@ +V ALLIANCE : 6 +H nao2o22_x1,P,20/12/2024,100 +A 0,0,6000,10000 +R 5000,5000,ref_ref,i2_15 +R 5000,3000,ref_ref,i2_25 +R 4000,5000,ref_ref,i3_15 +R 4000,3000,ref_ref,i3_25 +R 1000,5000,ref_ref,i0_30 +R 1000,6000,ref_ref,i0_25 +R 2000,5000,ref_ref,i1_30 +R 2000,6000,ref_ref,i1_25 +R 3000,5000,ref_ref,nq_20 +R 3000,4000,ref_ref,nq_25 +R 1000,4000,ref_ref,i0_20 +R 1000,8000,ref_ref,i0_40 +R 1000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 3000,8000,ref_ref,nq_40 +R 4000,8000,ref_ref,i3_40 +R 5000,8000,ref_ref,i2_40 +R 2000,4000,ref_ref,i1_20 +R 4000,4000,ref_ref,i3_20 +R 4000,6000,ref_ref,i3_30 +R 3000,7000,ref_ref,nq_35 +R 3000,6000,ref_ref,nq_30 +R 3000,3000,ref_ref,nq_15 +R 5000,4000,ref_ref,i2_20 +R 5000,6000,ref_ref,i2_30 +R 5000,7000,ref_ref,i2_35 +R 4000,7000,ref_ref,i3_35 +S 3500,4000,4000,4000,500,*,RIGHT,POLY +S 2800,5100,2800,9400,1000,*,UP,PDIF +S 4200,5100,4200,9400,1000,*,UP,PDIF +S 4200,600,4200,2500,1000,*,UP,NDIF +S 5600,5100,5600,9400,600,*,UP,PDIF +S 5600,600,5600,2500,600,*,UP,NDIF +S 5000,2400,5000,5200,200,*,UP,POLY +S -500,7500,6500,7500,6000,*,RIGHT,NWELL +S 5000,600,5000,2500,200,*,UP,NTRANS +S 5000,5100,5000,9400,200,*,UP,PTRANS +S 3500,600,3500,2500,200,*,UP,NTRANS +S 3500,2400,3500,5300,200,*,UP,POLY +S 3500,5100,3500,9400,200,*,UP,PTRANS +S 1500,5100,1500,9400,800,*,UP,PDIF +S 2000,4100,2000,5400,200,*,UP,POLY +S 2000,5100,2000,9400,200,*,UP,PTRANS +S 1700,2200,1700,3200,500,*,UP,ALU1 +S 1800,3000,3200,3000,400,*,RIGHT,ALU1 +S 500,5100,500,9400,400,*,UP,PDIF +S 1000,5100,1000,9400,200,*,UP,PTRANS +S 0,9500,6000,9500,1400,vdd,RIGHT,CALU1 +S 0,500,6000,500,1400,vss,RIGHT,CALU1 +S 500,600,500,2500,400,*,UP,NDIF +S 1700,600,1700,2500,800,*,UP,NDIF +S 1000,600,1000,2500,200,*,UP,NTRANS +S 2800,600,2800,2500,400,*,UP,NDIF +S 1900,4000,2400,4000,500,*,RIGHT,POLY +S 2400,2500,2400,4100,200,*,UP,POLY +S 2400,600,2400,2500,200,*,UP,NTRANS +S 1700,600,1700,2700,400,*,UP,NDIF +S 1000,2400,1000,5400,200,*,UP,POLY +S 3200,600,3200,2500,400,*,UP,NDIF +S 2000,3800,2000,8300,300,*,UP,ALU1 +S 2000,3800,2000,8300,300,i1,UP,CALU1 +S 1000,3800,1000,8300,300,i0,UP,CALU1 +S 1000,3800,1000,8300,300,*,UP,ALU1 +S 600,1700,5400,1700,300,*,RIGHT,ALU1 +S 5000,2800,5000,8300,300,i2,UP,CALU1 +S 5000,2800,5000,8300,300,*,UP,ALU1 +S 4000,2800,4000,8300,300,i3,UP,CALU1 +S 4000,2800,4000,8300,300,*,UP,ALU1 +S 3000,2800,3000,8300,300,*,UP,ALU1 +S 3000,2800,3000,8300,300,nq,UP,CALU1 +S -200,0,6200,0,400,*,RIGHT,PTIE +S -200,10000,6200,10000,400,*,RIGHT,NTIE +V 5500,9000,CONT_DIF_P,* +V 5500,1700,CONT_DIF_N,* +V 1700,2400,CONT_DIF_N,* +V 4200,900,CONT_DIF_N,* +V 3000,1700,CONT_DIF_N,* +V 500,1700,CONT_DIF_N,* +V 500,9200,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 3000,8000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 3000,7000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/nao2o22_x1.vbe b/pdks/symbolic/nsxlib2/cells/nao2o22_x1.vbe new file mode 100644 index 000000000..327e99763 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nao2o22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i3_nq : NATURAL := 174; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tphl_i2_nq : NATURAL := 237; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT tplh_i2_nq : NATURAL := 307; + CONSTANT tplh_i3_nq : NATURAL := 382; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x1; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/nao2o22_x4.ap b/pdks/symbolic/nsxlib2/cells/nao2o22_x4.ap new file mode 100644 index 000000000..97b29de7d --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nao2o22_x4.ap @@ -0,0 +1,168 @@ +V ALLIANCE : 6 +H nao2o22_x4,P,17/ 8/2024,100 +A 0,0,11000,10000 +R 4000,3000,ref_ref,i3_15 +R 4000,4000,ref_ref,i3_20 +R 4000,5000,ref_ref,i3_25 +R 4000,6000,ref_ref,i3_30 +R 5000,7000,ref_ref,i2_35 +R 4000,7000,ref_ref,i3_35 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +R 5000,4000,ref_ref,i2_20 +R 5000,3000,ref_ref,i2_15 +R 9000,8000,ref_ref,nq_40 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 9000,7000,ref_ref,nq_35 +R 9000,6000,ref_ref,nq_30 +R 9000,4000,ref_ref,nq_20 +R 9000,2000,ref_ref,nq_10 +R 9000,3000,ref_ref,nq_15 +R 9000,5000,ref_ref,nq_25 +R 1000,7000,ref_ref,i0_35 +R 1000,8000,ref_ref,i0_40 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +S 3500,4000,3900,4000,600,*,RIGHT,POLY +S 4500,4000,5100,4000,600,*,RIGHT,POLY +S 4500,2400,4500,4400,200,*,UP,POLY +S 4500,1100,4500,2500,200,*,UP,NTRANS +S 4500,4200,4500,6200,200,*,UP,POLY +S 5200,6500,5200,8900,800,*,UP,PDIF +S 2800,6500,2800,8900,1000,*,UP,PDIF +S 3500,2400,3500,6500,200,*,UP,POLY +S 3500,6500,3500,8900,200,*,UP,PTRANS +S 4500,6500,4500,8900,200,*,UP,PTRANS +S 4500,6100,4500,6600,200,*,UP,POLY +S 2800,2700,2800,8100,300,*,UP,ALU1 +S 1500,6500,1500,8900,800,*,UP,PDIF +S 2400,2500,2400,4200,200,*,UP,POLY +S 2000,4000,2000,6600,200,*,DOWN,POLY +S 2000,6500,2000,8900,200,*,UP,PTRANS +S 7200,2500,7200,5600,200,*,UP,POLY +S 2900,8000,6600,8000,300,*,RIGHT,ALU1 +S 6600,4000,8000,4000,300,*,RIGHT,ALU1 +S 6600,7000,7800,7000,300,*,RIGHT,ALU1 +S 7800,4800,7800,7000,300,*,UP,ALU1 +S 6600,7000,6600,8000,300,*,UP,ALU1 +S 1700,2700,3000,2700,300,*,RIGHT,ALU1 +S 10100,600,10100,2500,600,*,UP,NDIF +S 7800,600,7800,2500,800,*,UP,NDIF +S 9000,600,9000,2500,600,*,UP,NDIF +S 8500,600,8500,2500,200,*,UP,NTRANS +S 8500,2500,8500,5500,200,*,UP,POLY +S 8000,5500,8000,9400,400,*,UP,PDIF +S 8500,5500,8500,9400,200,*,UP,PTRANS +S 9500,5500,9500,9400,200,*,UP,PTRANS +S 9500,2500,9500,5600,200,*,UP,POLY +S 9500,600,9500,2500,200,*,UP,NTRANS +S 10100,1100,10100,2200,300,*,UP,ALU1 +S 7800,1100,7800,2200,300,*,UP,ALU1 +S 600,6500,600,8900,600,*,UP,PDIF +S -500,7500,11500,7500,6000,*,RIGHT,NWELL +S 500,1100,500,2500,400,*,UP,NDIF +S 600,2000,5300,2000,300,*,RIGHT,ALU1 +S 5000,1100,5000,2500,600,*,UP,NDIF +S 4100,1100,4100,2500,600,*,UP,NDIF +S 3000,1100,3000,2500,800,*,UP,NDIF +S 1900,4000,2400,4000,500,*,RIGHT,POLY +S 2400,1100,2400,2500,200,*,UP,NTRANS +S 1700,1100,1700,2900,600,*,UP,NDIF +S 1500,1100,1500,2500,400,*,UP,NDIF +S 1000,2500,1000,6500,200,*,UP,POLY +S 1000,6500,1000,8900,200,*,UP,PTRANS +S 1000,1100,1000,2500,200,*,UP,NTRANS +S 10000,5500,10000,9400,400,*,UP,PDIF +S 7700,5500,7700,7500,600,*,UP,PDIF +S 4100,6500,4100,8900,600,*,UP,PDIF +S 2100,1100,2100,2500,400,*,UP,NDIF +S 7700,4000,9600,4000,400,*,RIGHT,POLY +S 7200,5000,7900,5000,400,*,RIGHT,POLY +S 6600,1500,6600,6500,300,*,UP,ALU1 +S 6600,600,6600,2500,600,*,UP,NDIF +S 7200,600,7200,2500,200,*,UP,NTRANS +S 3500,1100,3500,2500,200,*,UP,NTRANS +S 5000,2800,5000,7200,300,*,UP,ALU1 +S 5000,2800,5000,7200,300,i2,UP,CALU1 +S 4000,2800,4000,7200,300,i3,UP,CALU1 +S 4000,2800,4000,7200,300,*,UP,ALU1 +S 2000,3800,2000,8200,300,i1,UP,CALU1 +S 2000,3800,2000,8200,300,*,UP,ALU1 +S 1000,3800,1000,8200,300,*,UP,ALU1 +S 1000,3800,1000,8200,300,i0,UP,CALU1 +S 10000,5800,10000,8800,300,*,UP,ALU1 +S 8000,7800,8000,8800,300,*,UP,ALU1 +S 9000,1800,9000,8200,300,nq,UP,CALU1 +S 9000,1800,9000,8200,300,*,UP,ALU1 +S 6600,5500,6600,7500,600,*,UP,PDIF +S 9000,5500,9000,9400,600,*,UP,PDIF +S -200,10000,11200,10000,400,*,RIGHT,NTIE +S -200,0,11200,0,400,*,RIGHT,PTIE +S 7200,5500,7200,7500,200,*,UP,PTRANS +S -200,500,11200,500,1400,vss,RIGHT,CALU1 +S -200,9500,11200,9500,1400,vdd,RIGHT,CALU1 +V 4000,1300,CONT_DIF_N,* +V 3800,4000,CONT_POLY,* +B 2800,2700,200,200,CONT_TURN1,* +V 2800,7000,CONT_DIF_P,* +V 2800,8000,CONT_DIF_P,* +V 8000,0,CONT_BODY_P,* +B 6600,8000,200,200,CONT_TURN1,* +B 6600,7000,200,200,CONT_TURN1,* +B 7800,7000,200,200,CONT_TURN1,* +V 10100,900,CONT_DIF_N,* +V 10100,2000,CONT_DIF_N,* +V 7800,900,CONT_DIF_N,* +V 7800,2000,CONT_DIF_N,* +V 5100,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 1700,2700,CONT_DIF_N,* +V 500,2000,CONT_DIF_N,* +V 500,8700,CONT_DIF_P,* +V 5200,8700,CONT_DIF_P,* +V 6600,6300,CONT_DIF_P,* +V 6600,1700,CONT_DIF_N,* +V 8000,9200,CONT_DIF_P,* +V 9000,2000,CONT_DIF_N,* +V 8000,8000,CONT_DIF_P,* +V 10000,9200,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,6000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 9000,6000,CONT_DIF_P,* +V 7800,4000,CONT_POLY,* +V 7800,5000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/nao2o22_x4.vbe b/pdks/symbolic/nsxlib2/cells/nao2o22_x4.vbe new file mode 100644 index 000000000..b5c506fee --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i3_nq : NATURAL := 607; + CONSTANT tplh_i0_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 664; + CONSTANT tphl_i1_nq : NATURAL := 666; + CONSTANT tplh_i1_nq : NATURAL := 717; + CONSTANT tplh_i2_nq : NATURAL := 721; + CONSTANT tphl_i0_nq : NATURAL := 734; + CONSTANT tplh_i3_nq : NATURAL := 807; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/nmx2_x1.ap b/pdks/symbolic/nsxlib2/cells/nmx2_x1.ap new file mode 100644 index 000000000..586878ab8 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nmx2_x1.ap @@ -0,0 +1,117 @@ +V ALLIANCE : 6 +H nmx2_x1,P,17/ 8/2024,100 +A 0,0,7000,10000 +R 6000,5000,ref_ref,i1_20 +R 6000,4000,ref_ref,i1_25 +R 2000,5000,ref_ref,i0_20 +R 2000,4000,ref_ref,i0_25 +R 4000,3000,ref_ref,nq_15 +R 6000,3000,ref_ref,i1_15 +R 6000,6000,ref_ref,i1_30 +R 6000,7000,ref_ref,i1_35 +R 6000,8000,ref_ref,i1_40 +R 4000,7000,ref_ref,nq_35 +R 4000,6000,ref_ref,nq_30 +R 4000,5000,ref_ref,nq_25 +R 4000,4000,ref_ref,nq_20 +R 4000,2000,ref_ref,nq_10 +R 6000,2000,ref_ref,i1_10 +R 2000,7000,ref_ref,i0_35 +R 2000,6000,ref_ref,i0_30 +R 2000,3000,ref_ref,i0_15 +R 3000,5000,ref_ref,cmd_25 +R 3000,4000,ref_ref,cmd_20 +R 3000,7000,ref_ref,cmd_35 +R 3000,6000,ref_ref,cmd_30 +S 5700,2500,5700,2800,200,*,UP,POLY +S 5700,5000,5700,5600,200,*,UP,POLY +S 6000,3000,6000,5000,200,*,UP,POLY +S 5600,5000,6100,5000,200,*,RIGHT,POLY +S 3000,2400,3000,2900,200,q,UP,POLY +S 4600,5100,4600,5600,200,*,UP,POLY +S -600,7500,7500,7500,6000,*,RIGHT,NWELL +S 5600,2800,6200,2800,200,*,RIGHT,POLY +S 5000,4800,5000,8000,300,*,UP,ALU1 +S 300,8000,5000,8000,300,*,RIGHT,ALU1 +S 300,2000,3000,2000,300,*,RIGHT,ALU1 +S 3000,2000,3000,3200,300,*,UP,ALU1 +S 2600,600,2600,2500,600,*,UP,NDIF +S 2600,5500,2600,9400,600,*,UP,PDIF +S 2100,2500,2100,3100,200,*,UP,POLY +S 500,6500,500,8500,400,*,UP,PDIF +S 500,1500,500,2500,400,*,UP,NDIF +S 4500,5100,5200,5100,200,*,RIGHT,POLY +S 6200,5500,6200,9400,400,*,UP,PDIF +S 5700,5500,5700,9400,200,*,UP,PTRANS +S 6200,600,6200,2500,400,*,UP,NDIF +S 5700,600,5700,2500,200,*,UP,NTRANS +S 3800,5500,3800,9400,1000,*,UP,PDIF +S 3800,600,3800,2500,1000,*,UP,NDIF +S 3000,4000,3000,5500,200,*,UP,POLY +S 3000,5500,3000,9400,200,*,UP,PTRANS +S 3000,600,3000,2500,200,*,UP,NTRANS +S 2200,4900,2200,5500,200,*,UP,POLY +S 1700,5500,1700,9400,400,*,UP,PDIF +S 2200,5500,2200,9400,200,*,UP,PTRANS +S 2100,600,2100,2500,200,*,UP,NTRANS +S 1600,600,1600,2500,400,*,UP,NDIF +S 1500,1500,1500,2500,400,*,UP,NDIF +S 1500,6500,1500,8500,400,*,UP,PDIF +S 1000,4000,4600,4000,200,*,RIGHT,POLY +S 1000,6500,1000,8500,200,*,UP,PTRANS +S 1000,2400,1000,6500,200,*,UP,POLY +S 1000,1500,1000,2500,200,*,UP,NTRANS +S 500,1800,500,8200,300,*,UP,ALU1 +S 5200,600,5200,2500,800,*,UP,NDIF +S 5200,5500,5200,9400,800,*,UP,PDIF +S 4600,2500,4600,4100,200,*,UP,POLY +S 2000,2800,2000,7200,300,*,UP,ALU1 +S 2000,2800,2000,7200,300,i0,UP,CALU1 +S 3000,3800,3000,7200,300,cmd,UP,CALU1 +S 3000,3800,3000,7200,300,*,UP,ALU1 +S 4000,1800,4000,7200,300,nq,UP,CALU1 +S 4000,1800,4000,4000,300,*,UP,ALU1 +S 6000,1700,6000,8200,300,i1,UP,CALU1 +S 6000,1700,6000,8200,300,*,UP,ALU1 +S 4000,4000,4000,7200,300,*,UP,ALU1 +S 4600,5500,4600,9400,200,*,UP,PTRANS +S -200,10000,7200,10000,400,*,RIGHT,NTIE +S -200,0,7200,0,400,*,RIGHT,PTIE +S 4600,600,4600,2500,200,*,UP,NTRANS +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +V 1600,1000,CONT_DIF_N,* +V 1700,9000,CONT_DIF_P,* +V 6200,9000,CONT_DIF_P,* +V 6200,1000,CONT_DIF_N,* +V 6000,3000,CONT_POLY,* +B 3000,2000,200,200,CONT_TURN1,* +B 5000,8000,200,200,CONT_TURN1,* +V 5000,4900,CONT_POLY,* +V 500,2000,CONT_DIF_N,* +V 500,7000,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 2000,5000,CONT_POLY,* +V 4000,6000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 3000,3000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/nmx2_x1.vbe b/pdks/symbolic/nsxlib2/cells/nmx2_x1.vbe new file mode 100644 index 000000000..3f0ab6425 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nmx2_x1.vbe @@ -0,0 +1,40 @@ +ENTITY nmx2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_cmd : NATURAL := 21; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 217; + CONSTANT tphl_i1_nq : NATURAL := 217; + CONSTANT tphl_cmd_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 256; + CONSTANT tplh_i1_nq : NATURAL := 256; + CONSTANT tplh_cmd_nq : NATURAL := 287; + CONSTANT tphh_cmd_nq : NATURAL := 379; + CONSTANT tpll_cmd_nq : NATURAL := 410; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x1; + +ARCHITECTURE behaviour_data_flow OF nmx2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x1" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/nmx2_x4.ap b/pdks/symbolic/nsxlib2/cells/nmx2_x4.ap new file mode 100644 index 000000000..e193cc9a7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nmx2_x4.ap @@ -0,0 +1,180 @@ +V ALLIANCE : 6 +H nmx2_x4,P,16/ 8/2024,100 +A 0,0,11000,10000 +R 3000,5000,ref_ref,cmd_15 +R 3000,3000,ref_ref,cmd_25 +R 6000,8000,ref_ref,i1_40 +R 6000,7000,ref_ref,i1_35 +R 6000,6000,ref_ref,i1_30 +R 6000,2000,ref_ref,i1_10 +R 6000,3000,ref_ref,i1_15 +R 6000,5000,ref_ref,i1_25 +R 6000,4000,ref_ref,i1_20 +R 9000,8000,ref_ref,nq_40 +R 9000,7000,ref_ref,nq_35 +R 9000,6000,ref_ref,nq_30 +R 9000,5000,ref_ref,nq_25 +R 9000,4000,ref_ref,nq_20 +R 9000,3000,ref_ref,nq_15 +R 9000,2000,ref_ref,nq_10 +R 2000,5000,ref_ref,i0_25 +R 2000,4000,ref_ref,i0_20 +R 2000,3000,ref_ref,i0_15 +R 3000,8000,ref_ref,cmd_40 +R 3000,7000,ref_ref,cmd_35 +R 3000,6000,ref_ref,cmd_30 +R 3000,4000,ref_ref,cmd_20 +R 2000,6000,ref_ref,i0_30 +R 2000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i0_40 +S 4400,1400,4400,3900,200,*,UP,POLY +S 6000,1500,6000,2400,200,*,UP,POLY +S 6000,6100,6000,6600,200,*,UP,POLY +S 4300,5400,4300,6600,200,*,UP,POLY +S 2900,6100,2900,6500,200,*,UP,POLY +S 2300,5800,2300,6600,200,*,UP,POLY +S 1300,1500,1300,6700,200,*,UP,POLY +S 3800,7000,3800,8100,300,*,DOWN,ALU1 +S 4200,5600,4600,5600,200,*,LEFT,POLY +S 3800,600,3800,2600,600,*,UP,NDIF +S 3800,2200,3800,7100,300,*,UP,ALU1 +S 4500,1700,4500,5400,300,*,UP,ALU1 +S 5300,6000,6100,6000,400,*,RIGHT,ALU1 +S 5400,3000,6100,3000,400,*,RIGHT,ALU1 +S 5000,6200,5000,6500,200,*,UP,POLY +S 4900,6200,5500,6200,200,*,LEFT,POLY +S 4900,2800,5500,2800,200,*,RIGHT,POLY +S 5000,1500,5000,2800,200,*,UP,POLY +S 6000,1700,6000,8000,300,*,UP,ALU1 +S 6000,1800,6000,8100,300,i1,UP,CALU1 +S -200,0,11200,0,400,*,RIGHT,PTIE +S -200,500,11200,500,1400,vss,RIGHT,CALU1 +S -500,7500,11500,7500,6000,*,RIGHT,NWELL +S -200,10000,11200,10000,400,*,RIGHT,NTIE +S -200,9500,11200,9500,1400,vdd,RIGHT,CALU1 +S 6600,6500,6600,9200,600,*,UP,PDIF +S 5400,600,5400,1500,600,*,UP,NDIF +S 4700,600,4700,1500,400,*,UP,NDIF +S 6600,5000,9600,5000,200,*,RIGHT,POLY +S 10000,600,10000,2500,400,*,UP,NDIF +S 10000,1200,10000,2100,300,*,UP,ALU1 +S 9500,2500,9500,5500,200,*,UP,POLY +S 10000,5500,10000,9400,400,*,UP,PDIF +S 10000,5900,10000,8800,300,*,UP,ALU1 +S 9500,5500,9500,9400,200,*,UP,PTRANS +S 9000,5500,9000,9400,600,*,UP,PDIF +S 9500,600,9500,2500,200,*,UP,NTRANS +S 9000,600,9000,2500,600,*,UP,NDIF +S 9000,1800,9000,8200,300,*,UP,ALU1 +S 9000,1800,9000,8200,300,nq,UP,CALU1 +S 8500,600,8500,2500,200,*,UP,NTRANS +S 8000,600,8000,2500,600,*,UP,NDIF +S 8000,1200,8000,2100,300,*,UP,ALU1 +S 8500,2500,8500,5500,200,*,UP,POLY +S 8500,5500,8500,9400,200,*,UP,PTRANS +S 8000,5500,8000,9400,600,*,UP,PDIF +S 8000,5900,8000,8800,300,*,UP,ALU1 +S 6700,600,6700,1900,600,*,UP,NDIF +S 6700,1600,6700,8100,300,*,UP,ALU1 +S 6400,600,6400,1500,400,*,UP,NDIF +S 3700,4400,6100,4400,200,*,RIGHT,POLY +S 6000,2400,6000,6100,200,*,UP,POLY +S 6000,600,6000,1500,200,*,UP,NTRANS +S 5000,600,5000,1500,200,*,UP,NTRANS +S 6000,6500,6000,9200,200,*,UP,PTRANS +S 5500,6500,5500,9200,800,*,UP,PDIF +S 1300,3800,4500,3800,200,*,RIGHT,POLY +S 4400,600,4400,1500,200,*,UP,NTRANS +S 200,1700,4400,1700,300,*,RIGHT,ALU1 +S 2900,3800,2900,6100,200,*,UP,POLY +S 5000,6500,5000,9200,200,*,UP,PTRANS +S 4300,6500,4300,9200,200,*,UP,PTRANS +S 3700,600,3700,1500,1000,*,UP,NDIF +S 2600,600,2600,1500,400,*,UP,NDIF +S 3800,6500,3800,9200,800,*,UP,PDIF +S 1800,6500,1800,9200,800,*,UP,PDIF +S 3300,6500,3300,9200,600,*,UP,PDIF +S 2900,1700,2900,2100,400,*,UP,ALU1 +S 2900,1500,2900,1900,200,*,UP,POLY +S 2900,600,2900,1500,200,*,UP,NTRANS +S 2900,6500,2900,9200,200,*,UP,PTRANS +S 2300,6500,2300,9200,200,*,UP,PTRANS +S 500,1700,500,8200,300,*,UP,ALU1 +S 5300,6500,5300,9200,400,*,UP,PDIF +S 2300,1500,2300,3100,200,*,UP,POLY +S 1900,2800,2400,2800,200,*,RIGHT,POLY +S 700,6500,700,9200,800,*,UP,PDIF +S 1800,600,1800,1500,400,*,UP,NDIF +S 1300,6500,1300,9200,200,*,UP,PTRANS +S 1300,600,1300,1500,200,*,UP,NTRANS +S 600,600,600,1900,600,*,UP,NDIF +S 1000,600,1000,1500,400,*,UP,NDIF +S 2000,2800,2000,8200,300,*,UP,ALU1 +S 2000,2800,2000,8200,300,i0,UP,CALU1 +S 3000,2800,3000,8200,300,*,UP,ALU1 +S 3000,2800,3000,8200,300,cmd,UP,CALU1 +S 2300,600,2300,1500,200,*,UP,NTRANS +V 3800,7000,CONT_DIF_P,* +V 3800,8000,CONT_DIF_P,* +V 3800,2400,CONT_DIF_N,* +V 3800,4500,CONT_POLY,* +B 4500,1700,200,200,CONT_TURN1,* +V 4500,5400,CONT_POLY,* +V 5400,6000,CONT_POLY,* +V 5400,3000,CONT_POLY,* +V 2100,6000,CONT_POLY,* +V 2900,3800,CONT_POLY,* +V 5500,900,CONT_DIF_N,* +V 10000,900,CONT_DIF_N,* +V 10000,2000,CONT_DIF_N,* +V 10000,9200,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,6000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 9000,2000,CONT_DIF_N,* +V 8000,900,CONT_DIF_N,* +V 8000,2000,CONT_DIF_N,* +V 8000,9100,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 6000,10000,CONT_BODY_N,* +V 6700,5000,CONT_POLY,* +V 6700,8000,CONT_DIF_P,* +V 6700,6800,CONT_DIF_P,* +V 6700,1700,CONT_DIF_N,* +V 5500,9000,CONT_DIF_P,* +V 2900,2000,CONT_POLY,* +V 1800,9000,CONT_DIF_P,* +V 500,7000,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 500,1700,CONT_DIF_N,* +V 2000,3000,CONT_POLY,* +V 1800,900,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/nmx2_x4.vbe b/pdks/symbolic/nsxlib2/cells/nmx2_x4.vbe new file mode 100644 index 000000000..436a6b355 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nmx2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY nmx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_cmd_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 610; + CONSTANT tphl_cmd_nq : NATURAL := 632; + CONSTANT tplh_i0_nq : NATURAL := 653; + CONSTANT tplh_i1_nq : NATURAL := 653; + CONSTANT tphh_cmd_nq : NATURAL := 688; + CONSTANT tpll_cmd_nq : NATURAL := 703; + CONSTANT tplh_cmd_nq : NATURAL := 708; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x4; + +ARCHITECTURE behaviour_data_flow OF nmx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x4" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/nmx3_x1.ap b/pdks/symbolic/nsxlib2/cells/nmx3_x1.ap new file mode 100644 index 000000000..327d756ac --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nmx3_x1.ap @@ -0,0 +1,205 @@ +V ALLIANCE : 6 +H nmx3_x1,P,17/ 8/2024,100 +A 0,0,12000,10000 +R 7000,5000,ref_ref,cmd0_30 +R 7000,6000,ref_ref,cmd0_25 +R 5000,4000,ref_ref,i1_25 +R 9000,5000,ref_ref,i0_25 +R 9000,6000,ref_ref,i0_30 +R 9000,4000,ref_ref,i0_20 +R 11000,4000,ref_ref,nq_20 +R 11000,3000,ref_ref,nq_15 +R 11000,7000,ref_ref,nq_35 +R 1000,3000,ref_ref,cmd1_15 +R 1000,4000,ref_ref,cmd1_20 +R 1000,5000,ref_ref,cmd1_25 +R 1000,6000,ref_ref,cmd1_30 +R 1000,7000,ref_ref,cmd1_35 +R 7000,4000,ref_ref,cmd0_20 +R 3000,5000,ref_ref,i2_25 +R 11000,2000,ref_ref,nq_10 +R 11000,6000,ref_ref,nq_30 +R 11000,5000,ref_ref,nq_25 +S 2300,7500,2300,9400,800,*,UP,PDIF +S 2300,700,2300,1900,800,*,UP,NDIF +S 3600,4500,4500,4500,200,*,RIGHT,POLY +S 3700,4400,3700,7000,200,*,UP,POLY +S 4400,3300,4400,4500,200,*,UP,POLY +S 4300,3300,5300,3300,200,*,LEFT,POLY +S 5200,1800,5200,3300,200,*,UP,POLY +S 3000,5100,3000,7100,200,*,UP,POLY +S 3000,7500,3000,9400,200,*,UP,PTRANS +S 3000,7100,3000,7600,200,*,UP,POLY +S 3000,700,3000,1900,200,*,UP,NTRANS +S 3000,1900,3000,5100,200,*,UP,POLY +S 10400,5000,10400,5700,200,*,UP,POLY +S 9000,1800,9000,4000,200,*,UP,POLY +S 7200,1900,7200,2300,200,*,UP,POLY +S 3700,1800,3700,3200,200,*,UP,POLY +S 1700,3500,1700,5500,200,*,UP,POLY +S 3700,6900,3700,7600,200,*,UP,POLY +S 5400,7000,5400,7600,200,*,UP,POLY +S 6300,7100,6300,7600,200,*,UP,POLY +S 6900,7100,7400,7100,200,*,RIGHT,POLY +S 7300,7100,7300,7600,200,*,UP,POLY +S 8300,7100,8300,7600,200,*,UP,POLY +S 9200,7100,9200,7500,200,*,UP,POLY +S 1000,4000,1800,4000,400,*,RIGHT,POLY +S 6000,1900,6000,7100,200,*,UP,POLY +S 9700,3000,9700,6000,300,*,UP,ALU1 +S 6700,3000,9700,3000,300,*,RIGHT,ALU1 +S 6000,2700,6000,7700,300,*,UP,ALU1 +S 4500,700,4500,2900,600,*,UP,NDIF +S 4300,2700,6000,2700,300,*,RIGHT,ALU1 +S 2000,1700,6600,1700,300,*,RIGHT,ALU1 +S 3300,700,3300,1900,400,*,UP,NDIF +S 3700,700,3700,1900,200,*,UP,NTRANS +S 4200,700,4200,1900,400,*,UP,NDIF +S 4700,700,4700,1900,400,*,UP,NDIF +S 5200,700,5200,1900,200,*,UP,NTRANS +S 5600,700,5600,1900,400,*,UP,NDIF +S 6000,700,6000,1900,200,*,UP,NTRANS +S 6500,700,6500,1900,600,*,UP,NDIF +S 5000,5000,5000,5200,300,i1,UP,CALU1 +S 9500,1700,9500,2100,400,*,UP,ALU1 +S 9300,2000,11000,2000,300,*,RIGHT,ALU1 +S 9800,7000,11100,7000,300,*,RIGHT,ALU1 +S 2100,6300,4500,6300,300,*,RIGHT,ALU1 +S 2200,3000,2200,6400,300,*,UP,ALU1 +S 3000,2800,3000,5200,300,i2,DOWN,CALU1 +S 11000,1700,11000,7200,300,nq,UP,CALU1 +S 9800,7000,9800,8500,300,*,UP,ALU1 +S 3700,3000,3700,6300,300,*,UP,ALU1 +S 1000,7000,3900,7000,300,*,RIGHT,ALU1 +S 4400,7600,9900,7600,300,*,RIGHT,ALU1 +S 3700,7500,3700,9400,200,*,UP,PTRANS +S 9700,2700,9700,3500,400,*,UP,NDIF +S 8600,700,8600,1900,400,*,UP,NDIF +S 8300,1900,8300,3200,200,*,UP,POLY +S 7700,700,7700,1900,600,*,UP,NDIF +S 8300,700,8300,1900,200,*,UP,NTRANS +S 7300,7500,7300,9400,200,*,UP,PTRANS +S 6800,7500,6800,9400,600,*,UP,PDIF +S 5900,7100,6400,7100,200,*,RIGHT,POLY +S 6300,7500,6300,9400,200,*,UP,PTRANS +S 1700,2700,1700,3500,200,*,UP,NTRANS +S 1700,5500,1700,6900,200,*,UP,PTRANS +S 10600,2700,10600,3500,400,*,UP,NDIF +S 2200,5500,2200,6900,400,*,UP,PDIF +S 1300,5500,1300,6900,600,*,UP,PDIF +S 5000,7500,5000,9400,600,*,UP,PDIF +S 4200,7500,4200,9400,600,*,UP,PDIF +S 3300,7500,3300,9400,600,*,UP,PDIF +S 5900,7500,5900,9400,400,*,UP,PDIF +S 7800,7500,7800,9400,400,*,UP,PDIF +S 8700,7500,8700,9400,400,*,UP,PDIF +S 10900,5500,10900,6900,600,*,UP,PDIF +S 1300,2700,1300,3500,400,*,UP,NDIF +S 2200,2700,2200,3500,400,*,UP,NDIF +S 6800,700,6800,1900,400,*,UP,NDIF +S 9600,700,9600,1900,600,*,UP,NDIF +S 8000,6600,8000,7100,200,*,UP,POLY +S 8900,6000,8900,7100,200,*,UP,POLY +S 8000,5000,10500,5000,200,*,RIGHT,POLY +S 10200,3500,10200,5000,200,*,UP,POLY +S 7600,2300,7600,3800,200,*,UP,POLY +S 7000,2800,7000,7100,200,*,UP,POLY +S 4400,6200,4400,7100,200,*,UP,POLY +S 11000,700,11000,3500,600,*,UP,NDIF +S 10200,2700,10200,3500,200,*,UP,NTRANS +S 1000,2000,1000,3500,600,*,UP,NDIF +S 4300,7000,5500,7000,200,*,RIGHT,POLY +S 8800,7100,9300,7100,200,*,RIGHT,POLY +S 7900,7100,8400,7100,200,*,RIGHT,POLY +S 7500,3800,8100,3800,200,*,RIGHT,POLY +S 5000,3800,5000,5000,300,i1,UP,CALU1 +S 4600,7400,4600,9400,600,*,UP,PDIF +S 1000,5500,1000,7900,600,*,UP,PDIF +S 7000,3800,7000,6200,300,cmd0,UP,CALU1 +S 7000,3800,7000,6200,300,*,UP,ALU1 +S 9000,3800,9000,6300,300,*,UP,ALU1 +S 9000,3800,9000,6300,300,i0,UP,CALU1 +S 7100,5000,8000,5000,300,*,RIGHT,ALU1 +S 11100,5500,11100,8200,400,*,UP,PDIF +S 11100,7800,11100,9300,300,*,UP,ALU1 +S 2000,8300,7000,8300,300,*,RIGHT,ALU1 +S 1000,900,1000,2500,300,*,UP,ALU1 +S 1000,2800,1000,7200,300,cmd1,UP,CALU1 +S 1000,7500,1000,8800,300,*,UP,ALU1 +S 7100,2300,7700,2300,200,*,RIGHT,POLY +S 9800,5500,9800,6900,600,*,UP,PDIF +S 9800,7500,9800,9400,600,*,UP,PDIF +S 5400,7500,5400,9400,200,*,UP,PTRANS +S 8300,7500,8300,9400,200,*,UP,PTRANS +S 9200,7500,9200,9400,200,*,UP,PTRANS +S -200,9500,12200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,12200,500,1400,vss,RIGHT,CALU1 +S 8000,3800,8000,6600,200,*,UP,POLY +S 5000,5000,6000,5000,200,*,RIGHT,POLY +S -500,7500,12500,7500,6000,*,RIGHT,NWELL +S -200,10000,12200,10000,400,*,RIGHT,NTIE +S -200,0,12200,0,400,*,RIGHT,PTIE +S 9000,700,9000,1900,200,*,UP,NTRANS +S 7200,700,7200,1900,200,*,UP,NTRANS +S 10400,5500,10400,6900,200,*,UP,PTRANS +V 1000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 9700,5900,CONT_DIF_P,* +B 9700,3000,200,200,CONT_TURN1,* +B 3650,6300,300,200,CONT_TURN1,* +B 6000,2700,200,200,CONT_TURN1,* +V 4500,2700,CONT_DIF_N,* +V 6500,1700,CONT_DIF_N,* +V 4500,6300,CONT_POLY,* +B 11000,2100,200,200,CONT_TURN1,* +B 9800,7000,200,200,CONT_TURN1,* +V 7800,900,CONT_DIF_N,* +V 9700,3000,CONT_DIF_N,* +V 9500,1700,CONT_DIF_N,* +V 2200,1700,CONT_DIF_N,* +V 3700,3200,CONT_POLY,* +V 2200,6300,CONT_DIF_P,* +V 4600,7600,CONT_DIF_P,* +V 3700,7000,CONT_POLY,* +V 9800,8300,CONT_DIF_P,* +V 6800,8300,CONT_DIF_P,* +V 2200,8300,CONT_DIF_P,* +V 1000,2300,CONT_DIF_N,* +V 1000,7700,CONT_DIF_P,* +V 9000,4000,CONT_POLY,* +V 9000,6000,CONT_POLY,* +V 7800,9200,CONT_DIF_P,* +V 2200,3200,CONT_DIF_N,* +V 8400,3000,CONT_POLY,* +V 6800,3000,CONT_POLY,* +V 5000,5000,CONT_POLY,* +V 7800,5000,CONT_POLY,* +V 11000,900,CONT_DIF_N,* +V 11100,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/nmx3_x1.vbe b/pdks/symbolic/nsxlib2/cells/nmx3_x1.vbe new file mode 100644 index 000000000..1853919ce --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nmx3_x1.vbe @@ -0,0 +1,55 @@ +ENTITY nmx3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 7420; + CONSTANT rdown_cmd1_nq : NATURAL := 7420; + CONSTANT rdown_i0_nq : NATURAL := 5140; + CONSTANT rdown_i1_nq : NATURAL := 7420; + CONSTANT rdown_i2_nq : NATURAL := 7420; + CONSTANT rup_cmd0_nq : NATURAL := 9760; + CONSTANT rup_cmd1_nq : NATURAL := 9760; + CONSTANT rup_i0_nq : NATURAL := 6680; + CONSTANT rup_i1_nq : NATURAL := 9760; + CONSTANT rup_i2_nq : NATURAL := 9760; + CONSTANT tphl_i0_nq : NATURAL := 315; + CONSTANT tphl_cmd0_nq : NATURAL := 356; + CONSTANT tphl_cmd1_nq : NATURAL := 414; + CONSTANT tphl_i1_nq : NATURAL := 429; + CONSTANT tphl_i2_nq : NATURAL := 429; + CONSTANT tplh_i0_nq : NATURAL := 441; + CONSTANT tplh_cmd0_nq : NATURAL := 495; + CONSTANT tphh_cmd1_nq : NATURAL := 519; + CONSTANT tpll_cmd1_nq : NATURAL := 520; + CONSTANT tplh_cmd1_nq : NATURAL := 566; + CONSTANT tphh_cmd0_nq : NATURAL := 582; + CONSTANT tplh_i1_nq : NATURAL := 582; + CONSTANT tplh_i2_nq : NATURAL := 582; + CONSTANT tpll_cmd0_nq : NATURAL := 586; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x1; + +ARCHITECTURE behaviour_data_flow OF nmx3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx3_x1" + SEVERITY WARNING; + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not + (cmd1) and i2))))) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/no2_x1.ap b/pdks/symbolic/nsxlib2/cells/no2_x1.ap new file mode 100644 index 000000000..19c8d5e5d --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no2_x1.ap @@ -0,0 +1,73 @@ +V ALLIANCE : 6 +H no2_x1,P,16/ 8/2024,100 +A 0,0,4000,10000 +R 2000,5000,ref_ref,i1_15 +R 2000,3000,ref_ref,i1_25 +R 1000,7000,ref_ref,nq_35 +R 1000,8000,ref_ref,nq_40 +R 1000,2000,ref_ref,nq_10 +R 3000,5000,ref_ref,i0_25 +R 3000,4000,ref_ref,i0_20 +R 3000,3000,ref_ref,i0_15 +R 2000,4000,ref_ref,i1_20 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 1000,6000,ref_ref,nq_30 +R 1000,5000,ref_ref,nq_25 +R 1000,4000,ref_ref,nq_20 +R 1000,3000,ref_ref,nq_15 +R 2000,8000,ref_ref,i1_40 +R 3000,8000,ref_ref,i0_40 +R 3000,7000,ref_ref,i0_35 +R 3000,6000,ref_ref,i0_30 +S 2500,2400,2500,5100,200,*,UP,POLY +S 1900,5100,2600,5100,200,*,LEFT,POLY +S 2500,4000,3000,4000,500,*,LEFT,POLY +S 1000,2000,2000,2000,400,*,RIGHT,ALU1 +S 3000,1100,3000,2500,400,*,UP,NDIF +S 3000,1200,3000,2000,300,*,UP,ALU1 +S 2500,1100,2500,2500,200,*,UP,NTRANS +S 1500,4000,2000,4000,500,*,RIGHT,POLY +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 1500,3800,1500,5500,200,*,UP,POLY +S 1500,2400,1500,4200,200,*,UP,POLY +S 2000,1100,2000,2500,600,*,UP,NDIF +S 1500,1100,1500,2500,200,*,UP,NTRANS +S 1700,5500,1700,9400,200,*,UP,PDIF +S 2500,5500,2500,9400,400,*,UP,PDIF +S 2000,5000,2000,5500,200,*,DOWN,POLY +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 1000,5500,1000,9400,600,*,UP,PDIF +S 1000,1200,1000,1500,300,*,UP,ALU1 +S 1000,1800,1000,8200,300,nq,UP,CALU1 +S 1000,1800,1000,8200,300,*,UP,ALU1 +S 1000,1100,1000,2500,400,*,UP,NDIF +S 2000,2800,2000,8200,300,i1,UP,CALU1 +S 2000,2800,2000,8200,300,*,UP,ALU1 +S 3000,2800,3000,8200,300,*,UP,ALU1 +S 3000,2800,3000,8200,300,i0,UP,CALU1 +S -200,9500,4200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,4200,500,1400,vss,RIGHT,CALU1 +S -500,7500,4500,7500,6000,*,RIGHT,NWELL +S -200,10000,4200,10000,400,*,RIGHT,NTIE +S -200,0,4200,0,400,*,RIGHT,PTIE +V 3000,4000,CONT_POLY,* +V 1900,4000,CONT_POLY,* +V 3000,1800,CONT_DIF_N,* +V 2500,9000,CONT_DIF_P,* +V 2000,2000,CONT_DIF_N,* +V 1000,1300,CONT_DIF_N,* +V 1000,8000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1000,6000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/no2_x1.vbe b/pdks/symbolic/nsxlib2/cells/no2_x1.vbe new file mode 100644 index 000000000..37a91f3f6 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tplh_i0_nq : NATURAL := 121; + CONSTANT tplh_i1_nq : NATURAL := 161; + CONSTANT tphl_i1_nq : NATURAL := 193; + CONSTANT tphl_i0_nq : NATURAL := 298; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x1; + +ARCHITECTURE behaviour_data_flow OF no2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x1" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 900 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/no2_x4.ap b/pdks/symbolic/nsxlib2/cells/no2_x4.ap new file mode 100644 index 000000000..9d052e982 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no2_x4.ap @@ -0,0 +1,110 @@ +V ALLIANCE : 6 +H no2_x4,P,17/ 8/2024,100 +A 0,0,7000,10000 +R 4000,5000,ref_ref,nq_25 +R 4000,4000,ref_ref,nq_20 +R 4000,3000,ref_ref,nq_15 +R 1000,4000,ref_ref,i1_20 +R 1000,5000,ref_ref,i1_25 +R 1000,6000,ref_ref,i1_30 +R 1000,7000,ref_ref,i1_35 +R 2000,5000,ref_ref,i0_25 +R 2000,4000,ref_ref,i0_20 +R 2000,3000,ref_ref,i0_15 +R 1000,3000,ref_ref,i1_15 +R 4000,6000,ref_ref,nq_30 +R 4000,7000,ref_ref,nq_35 +R 2000,7000,ref_ref,i0_35 +R 2000,6000,ref_ref,i0_30 +S 1400,2000,3000,2000,300,*,RIGHT,ALU1 +S 2600,1500,2600,2500,600,*,DOWN,NDIF +S 1500,5500,1500,9400,400,*,UP,PDIF +S 2600,5500,2600,9400,800,*,UP,PDIF +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 2000,4900,2000,5500,200,*,UP,POLY +S 2000,2400,2000,4900,200,*,UP,POLY +S 2000,1500,2000,2500,200,*,UP,NTRANS +S 1500,1500,1500,2500,400,*,DOWN,NDIF +S 1000,3000,1000,5500,200,*,UP,POLY +S 1000,2400,1000,3000,200,*,UP,POLY +S 1000,1500,1000,2500,200,*,UP,NTRANS +S 600,1500,600,2500,600,*,UP,NDIF +S 500,1200,500,2200,300,*,UP,ALU1 +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 500,5500,500,9400,400,*,UP,PDIF +S 5700,2500,5700,5600,200,*,UP,POLY +S 4500,2400,4500,4000,200,*,UP,POLY +S 3400,4000,5200,4000,200,*,RIGHT,POLY +S 5000,4000,6200,4000,300,*,RIGHT,ALU1 +S 600,8000,5200,8000,300,*,RIGHT,ALU1 +S 5200,4800,5200,8000,300,*,UP,ALU1 +S 3000,2000,3000,8000,300,*,UP,ALU1 +S 3000,600,3000,2500,600,*,UP,NDIF +S 4000,600,4000,2500,400,*,UP,NDIF +S 3500,2500,3500,4000,200,*,UP,POLY +S 3500,600,3500,2500,200,*,UP,NTRANS +S 4500,600,4500,2500,200,*,UP,NTRANS +S 5000,600,5000,2500,400,*,UP,NDIF +S 3500,4000,3500,5500,200,*,UP,POLY +S 4500,4000,4500,5500,200,*,UP,POLY +S 6200,5500,6200,7500,400,*,UP,PDIF +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 5200,5000,5800,5000,500,*,RIGHT,POLY +S 5700,5500,5700,7500,200,*,UP,PTRANS +S 6200,1500,6200,2500,400,*,UP,NDIF +S 5700,1500,5700,2500,200,*,UP,NTRANS +S 5300,1500,5300,2500,400,*,UP,NDIF +S 3100,5500,3100,9400,400,*,UP,PDIF +S 5000,5500,5000,9400,600,*,UP,PDIF +S 5400,5500,5400,7500,400,*,UP,PDIF +S 4000,1800,4000,7200,300,*,UP,ALU1 +S 6200,1800,6200,7200,300,*,UP,ALU1 +S 5200,1200,5200,2200,300,*,UP,ALU1 +S 2000,2800,2000,7200,300,*,UP,ALU1 +S 2000,2800,2000,7200,300,i0,UP,CALU1 +S 1000,2800,1000,7200,300,i1,UP,CALU1 +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 4000,3100,4000,7200,300,nq,UP,CALU1 +S 4000,5500,4000,9400,600,*,UP,PDIF +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S -500,7500,7500,7500,6000,*,RIGHT,NWELL +S -200,10000,7200,10000,400,*,RIGHT,NTIE +S -200,0,7200,0,400,*,RIGHT,PTIE +V 1500,2000,CONT_DIF_N,* +V 500,2000,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +B 5200,8000,200,200,CONT_TURN1,* +B 3000,2000,200,200,CONT_TURN1,* +V 3000,900,CONT_DIF_N,* +V 4000,2000,CONT_DIF_N,* +V 5000,900,CONT_DIF_N,* +V 5100,4000,CONT_POLY,* +V 2900,9100,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 5200,2000,CONT_DIF_N,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 6200,7000,CONT_DIF_P,* +V 6200,6000,CONT_DIF_P,* +V 6200,2000,CONT_DIF_N,* +V 5000,9100,CONT_DIF_P,* +V 5200,5000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/no2_x4.vbe b/pdks/symbolic/nsxlib2/cells/no2_x4.vbe new file mode 100644 index 000000000..5060db0e8 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tplh_i0_nq : NATURAL := 447; + CONSTANT tplh_i1_nq : NATURAL := 504; + CONSTANT tphl_i1_nq : NATURAL := 522; + CONSTANT tphl_i0_nq : NATURAL := 618; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x4; + +ARCHITECTURE behaviour_data_flow OF no2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x4" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/no3_x1.ap b/pdks/symbolic/nsxlib2/cells/no3_x1.ap new file mode 100644 index 000000000..a2a98798f --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no3_x1.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 6 +H no3_x1,P, 7/ 8/2024,100 +A 0,0,5000,10000 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 2000,8000,ref_ref,i1_40 +R 1000,3000,ref_ref,nq_15 +R 1000,4000,ref_ref,nq_20 +R 1000,5000,ref_ref,nq_25 +R 1000,6000,ref_ref,nq_30 +R 1000,7000,ref_ref,nq_35 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 1000,8000,ref_ref,nq_40 +R 4000,2000,ref_ref,i2_10 +R 2000,4000,ref_ref,i1_20 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 3000,8000,ref_ref,i0_40 +S 4300,800,4300,2500,600,*,UP,NDIF +S 1000,3000,3000,3000,300,*,RIGHT,ALU1 +S 3000,1800,3000,3000,300,*,UP,ALU1 +S 4000,5500,4000,9400,600,*,UP,PDIF +S 2000,1200,2000,1900,300,*,UP,ALU1 +S 2000,5500,2000,9400,800,*,UP,PDIF +S 2500,4000,3000,4000,500,*,RIGHT,POLY +S 3500,3000,4000,3000,500,*,RIGHT,POLY +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 3000,5500,3000,9400,600,*,UP,PDIF +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 2500,4000,2500,5500,200,*,UP,POLY +S 3500,2500,3500,5500,200,*,UP,POLY +S 3500,1500,3500,2500,200,*,UP,NTRANS +S 2000,1500,2000,2500,800,*,UP,NDIF +S 3000,1500,3000,2500,600,*,UP,NDIF +S 2500,2500,2500,4000,200,*,UP,POLY +S 2500,1500,2500,2500,200,*,UP,NTRANS +S 1000,1500,1000,2500,400,*,UP,NDIF +S 1500,4000,2100,4000,500,*,RIGHT,POLY +S 1500,4900,1500,5500,200,*,UP,POLY +S -500,7500,5500,7500,6000,*,RIGHT,NWELL +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 1500,2500,1500,4900,200,*,UP,POLY +S 1500,1500,1500,2500,200,*,UP,NTRANS +S 4000,1500,4000,2500,400,*,UP,NDIF +S 3000,3800,3000,8200,300,*,UP,ALU1 +S 3000,3800,3000,8200,300,i0,UP,CALU1 +S 2000,3800,2000,8200,300,*,UP,ALU1 +S 2000,3800,2000,8200,300,i1,UP,CALU1 +S 1000,1800,1000,8200,300,nq,UP,CALU1 +S 1000,1800,1000,8200,300,*,UP,ALU1 +S 4000,1800,4000,8200,300,*,UP,ALU1 +S 4000,1800,4000,8200,300,i2,UP,CALU1 +S 1000,5500,1000,9400,600,*,UP,PDIF +S -200,10000,5200,10000,400,*,RIGHT,NTIE +S -200,0,5200,0,400,*,RIGHT,PTIE +S -200,500,5200,500,1400,vss,RIGHT,CALU1 +S -200,9500,5200,9500,1400,vdd,RIGHT,CALU1 +B 2900,4000,400,400,CONT_TURN1,* +B 1900,4000,400,400,CONT_TURN1,* +V 4300,1100,CONT_DIF_N,* +B 3000,3000,200,200,CONT_TURN1,* +V 2000,2000,CONT_DIF_N,* +V 1000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 2800,4000,CONT_POLY,* +V 1800,4000,CONT_POLY,* +V 3000,2000,CONT_DIF_N,* +V 1000,6000,CONT_DIF_P,* +V 4100,9200,CONT_DIF_P,* +V 4000,3000,CONT_POLY,* +V 1000,2000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/no3_x1.vbe b/pdks/symbolic/nsxlib2/cells/no3_x1.vbe new file mode 100644 index 000000000..6711f8b1f --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT tplh_i2_nq : NATURAL := 192; + CONSTANT tphl_i1_nq : NATURAL := 215; + CONSTANT tplh_i1_nq : NATURAL := 243; + CONSTANT tplh_i0_nq : NATURAL := 246; + CONSTANT tphl_i0_nq : NATURAL := 318; + CONSTANT tphl_i2_nq : NATURAL := 407; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x1; + +ARCHITECTURE behaviour_data_flow OF no3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/no3_x4.ap b/pdks/symbolic/nsxlib2/cells/no3_x4.ap new file mode 100644 index 000000000..86084307b --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no3_x4.ap @@ -0,0 +1,128 @@ +V ALLIANCE : 6 +H no3_x4,P,17/ 8/2024,100 +A 0,0,8000,10000 +R 5000,3000,ref_ref,nq_15 +R 5000,4000,ref_ref,nq_20 +R 5000,5000,ref_ref,nq_25 +R 1000,3000,ref_ref,i2_15 +R 1000,7000,ref_ref,i2_35 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 5000,7000,ref_ref,nq_35 +R 5000,6000,ref_ref,nq_30 +R 1000,4000,ref_ref,i2_20 +R 3000,3000,ref_ref,i0_15 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 1000,6000,ref_ref,i2_30 +R 1000,5000,ref_ref,i2_25 +S 3300,2300,3300,3000,200,*,UP,POLY +S 1400,1500,1400,2500,400,*,UP,NDIF +S 3000,3000,3000,5100,200,*,UP,POLY +S 2900,3000,3400,3000,200,*,LEFT,POLY +S 3000,5100,3000,5600,200,*,UP,POLY +S 2600,5500,2600,9400,600,*,UP,PDIF +S 3000,5500,3000,9400,200,*,UP,PTRANS +S 1600,5500,1600,9400,600,*,UP,PDIF +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 2300,2400,2300,3100,200,*,UP,POLY +S 2000,2900,2000,5500,200,*,UP,POLY +S 2000,1500,2000,2500,400,*,UP,NDIF +S 1600,900,1600,2500,400,*,UP,NDIF +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 500,5500,500,9400,600,*,UP,PDIF +S 1000,2900,1000,5700,200,*,UP,POLY +S 1000,2500,1000,2900,200,*,UP,POLY +S 1000,1500,1000,2500,200,*,UP,NTRANS +S 500,1500,500,2500,400,*,UP,NDIF +S 6700,2500,6700,5500,200,*,UP,POLY +S 4500,4100,4500,5700,200,*,UP,POLY +S 5700,4000,7200,4000,300,*,RIGHT,ALU1 +S 6400,4800,6400,8000,300,*,UP,ALU1 +S 400,8000,6400,8000,300,*,RIGHT,ALU1 +S 3800,2000,3800,8000,300,*,UP,ALU1 +S 500,2000,3800,2000,300,*,RIGHT,ALU1 +S 3900,5500,3900,9400,1000,*,UP,PDIF +S 6200,5000,6800,5000,500,*,RIGHT,POLY +S 6700,5500,6700,7500,200,*,UP,PTRANS +S 4400,4000,5700,4000,400,*,RIGHT,POLY +S 5500,4100,5500,5500,200,*,UP,POLY +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 4700,2400,4700,4000,200,*,UP,POLY +S 7200,600,7200,2500,400,*,UP,NDIF +S 6700,600,6700,2500,200,*,UP,NTRANS +S 4200,600,4200,2500,400,*,UP,NDIF +S 5200,600,5200,2500,400,*,UP,NDIF +S 4700,600,4700,2500,200,*,UP,NTRANS +S 3800,1500,3800,2500,400,*,UP,NDIF +S 2800,1500,2800,2500,400,*,UP,NDIF +S 3300,1500,3300,2500,200,*,UP,NTRANS +S 1900,2900,2400,2900,200,*,RIGHT,POLY +S 2300,1500,2300,2500,200,*,UP,NTRANS +S 6300,5500,6300,7500,400,*,UP,PDIF +S 6000,5500,6000,9400,400,*,UP,PDIF +S 6200,600,6200,2500,600,*,UP,NDIF +S 7200,5500,7200,7500,400,*,UP,PDIF +S 5700,2500,5700,4000,200,*,UP,POLY +S 1600,1500,1600,2500,400,*,UP,NDIF +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 1000,2800,1000,7200,300,i2,UP,CALU1 +S 2000,2800,2000,7200,300,*,UP,ALU1 +S 2000,2800,2000,7200,300,i1,UP,CALU1 +S 3000,2800,3000,7200,300,i0,UP,CALU1 +S 3000,2800,3000,7200,300,*,UP,ALU1 +S 5000,1800,5000,7200,300,*,UP,ALU1 +S 7200,1800,7200,6200,300,*,UP,ALU1 +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 5000,3100,5000,7200,300,nq,UP,CALU1 +S 5000,5500,5000,9400,600,*,UP,PDIF +S -500,7500,8500,7500,6000,*,RIGHT,NWELL +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,0,8200,0,400,*,RIGHT,PTIE +S 5700,600,5700,2500,200,*,UP,NTRANS +S -200,500,8200,500,1400,vss,RIGHT,CALU1 +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +V 3000,4000,CONT_POLY,* +V 2100,3000,CONT_POLY,* +V 1600,1200,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +B 5100,2000,400,400,CONT_TURN1,* +V 5800,4000,CONT_POLY,* +B 6400,8000,200,200,CONT_TURN1,* +B 3800,2000,200,200,CONT_TURN1,* +V 3900,9100,CONT_DIF_P,* +V 4200,900,CONT_DIF_N,* +V 2800,2000,CONT_DIF_N,* +V 6200,900,CONT_DIF_N,* +V 6400,5000,CONT_POLY,* +V 6000,9100,CONT_DIF_P,* +V 7200,6000,CONT_DIF_P,* +V 7200,2000,CONT_DIF_N,* +V 5200,2000,CONT_DIF_N,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 1000,3000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/no3_x4.vbe b/pdks/symbolic/nsxlib2/cells/no3_x4.vbe new file mode 100644 index 000000000..52e3d602b --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 545; + CONSTANT tplh_i0_nq : NATURAL := 561; + CONSTANT tplh_i1_nq : NATURAL := 623; + CONSTANT tphl_i1_nq : NATURAL := 638; + CONSTANT tplh_i2_nq : NATURAL := 640; + CONSTANT tphl_i0_nq : NATURAL := 722; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x4; + +ARCHITECTURE behaviour_data_flow OF no3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/no4_x1.ap b/pdks/symbolic/nsxlib2/cells/no4_x1.ap new file mode 100644 index 000000000..cacf42b06 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no4_x1.ap @@ -0,0 +1,111 @@ +V ALLIANCE : 6 +H no4_x1,P,14/ 8/2024,100 +A 0,0,6000,10000 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 4000,8000,ref_ref,i2_40 +R 4000,7000,ref_ref,i2_35 +R 2000,4000,ref_ref,i1_20 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 5000,8000,ref_ref,i3_40 +R 5000,7000,ref_ref,i3_35 +R 5000,6000,ref_ref,i3_30 +R 5000,5000,ref_ref,i3_25 +R 5000,4000,ref_ref,i3_20 +R 5000,3000,ref_ref,i3_15 +R 1000,8000,ref_ref,nq_40 +R 1000,3000,ref_ref,nq_15 +R 1000,4000,ref_ref,nq_20 +R 1000,5000,ref_ref,nq_25 +R 1000,6000,ref_ref,nq_30 +R 1000,7000,ref_ref,nq_35 +R 3000,8000,ref_ref,i0_40 +R 4000,4000,ref_ref,i2_20 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +S 3000,1400,3000,2500,400,*,UP,NDIF +S 5000,1400,5000,2500,400,*,UP,NDIF +S 4500,1400,4500,2500,200,*,UP,NTRANS +S 4000,1400,4000,2500,600,*,UP,NDIF +S 3500,1400,3500,2500,200,*,UP,NTRANS +S 2500,1400,2500,2500,200,*,UP,NTRANS +S 2000,1400,2000,2500,800,*,UP,NDIF +S 1500,1400,1500,2500,200,*,UP,NTRANS +S 1000,1400,1000,2500,400,*,UP,NDIF +S 1500,2500,1500,5500,200,*,UP,POLY +S 4500,2500,4500,5000,200,*,UP,POLY +S 4500,5000,4500,5600,200,*,UP,POLY +S 3500,2500,3500,5600,200,*,UP,POLY +S 2500,4000,2500,5600,200,*,UP,POLY +S 1500,4000,2000,4000,500,*,RIGHT,POLY +S 1000,3000,4000,3000,300,*,RIGHT,ALU1 +S 4000,1800,4000,3000,300,*,UP,ALU1 +S 2000,1800,2000,3000,300,*,UP,ALU1 +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 3100,5500,3100,9400,600,*,UP,PDIF +S 3000,1200,3000,2200,300,*,UP,ALU1 +S 5000,1200,5000,2100,300,*,UP,ALU1 +S 4500,4000,5100,4000,500,*,RIGHT,POLY +S 3500,4000,3900,4000,500,*,RIGHT,POLY +S 2500,4000,3100,4000,500,*,RIGHT,POLY +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 2500,2500,2500,4000,200,*,UP,POLY +S 2100,5500,2100,9400,600,*,UP,PDIF +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 4100,5500,4100,9400,600,*,UP,PDIF +S 5000,5500,5000,9400,600,*,UP,PDIF +S 1000,5500,1000,9400,600,*,UP,PDIF +S 1000,1200,1000,2200,300,*,UP,ALU1 +S 4000,3800,4000,8200,300,*,UP,ALU1 +S 4000,3800,4000,8200,300,i2,UP,CALU1 +S 3000,3800,3000,8200,300,*,UP,ALU1 +S 3000,3800,3000,8200,300,i0,UP,CALU1 +S 2000,3800,2000,8200,300,i1,UP,CALU1 +S 2000,3800,2000,8200,300,*,UP,ALU1 +S 1000,2800,1000,8200,300,*,UP,ALU1 +S 1000,2800,1000,8200,300,nq,UP,CALU1 +S 5000,2800,5000,8200,300,i3,UP,CALU1 +S 5000,2800,5000,8200,300,*,UP,ALU1 +S 4500,5500,4500,9400,200,*,UP,PTRANS +S -500,7500,6500,7500,6000,*,RIGHT,NWELL +S -200,10000,6200,10000,400,*,RIGHT,NTIE +S -200,0,6200,0,400,*,RIGHT,PTIE +S -200,500,6200,500,1400,vss,RIGHT,CALU1 +S -200,9500,6200,9500,1400,vdd,RIGHT,CALU1 +B 1950,4000,500,400,CONT_TURN1,* +V 1800,4000,CONT_POLY,* +B 3900,4000,400,400,CONT_TURN1,* +B 2900,4000,400,400,CONT_TURN1,* +B 4000,3000,200,200,CONT_TURN1,* +V 5000,1900,CONT_DIF_N,* +V 3800,4000,CONT_POLY,* +V 4000,2000,CONT_DIF_N,* +V 2800,4000,CONT_POLY,* +V 3000,2000,CONT_DIF_N,* +V 5000,9100,CONT_DIF_P,* +V 1000,6000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 5000,4000,CONT_POLY,* +V 2000,2000,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/no4_x1.vbe b/pdks/symbolic/nsxlib2/cells/no4_x1.vbe new file mode 100644 index 000000000..5d15a3cd4 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rdown_i3_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT tphl_i1_nq : NATURAL := 230; + CONSTANT tplh_i3_nq : NATURAL := 271; + CONSTANT tplh_i1_nq : NATURAL := 320; + CONSTANT tphl_i0_nq : NATURAL := 330; + CONSTANT tplh_i2_nq : NATURAL := 333; + CONSTANT tplh_i0_nq : NATURAL := 340; + CONSTANT tphl_i2_nq : NATURAL := 419; + CONSTANT tphl_i3_nq : NATURAL := 499; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x1; + +ARCHITECTURE behaviour_data_flow OF no4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x1" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/no4_x4.ap b/pdks/symbolic/nsxlib2/cells/no4_x4.ap new file mode 100644 index 000000000..dc0c48a36 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no4_x4.ap @@ -0,0 +1,172 @@ +V ALLIANCE : 6 +H no4_x4,P,17/ 8/2024,100 +A 0,0,10000,10000 +R 2000,5000,ref_ref,i1_20 +R 2000,4000,ref_ref,i1_25 +R 3000,5000,ref_ref,i0_25 +R 3000,4000,ref_ref,i0_20 +R 3000,3000,ref_ref,i0_15 +R 2000,3000,ref_ref,i1_15 +R 5000,7000,ref_ref,i3_35 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 3000,8000,ref_ref,i0_40 +R 4000,3000,ref_ref,i2_15 +R 4000,4000,ref_ref,i2_20 +R 5000,3000,ref_ref,i3_15 +R 7000,7000,ref_ref,nq_35 +R 7000,8000,ref_ref,nq_40 +R 7000,3000,ref_ref,nq_15 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 2000,8000,ref_ref,i1_40 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 7000,6000,ref_ref,nq_30 +R 7000,5000,ref_ref,nq_25 +R 7000,4000,ref_ref,nq_20 +R 5000,6000,ref_ref,i3_30 +R 5000,5000,ref_ref,i3_25 +R 5000,4000,ref_ref,i3_20 +R 5000,8000,ref_ref,i3_40 +S 3400,5400,3400,9400,600,*,DOWN,PDIF +S 8000,5400,8000,9400,600,*,UP,PDIF +S 2500,5400,2500,9400,600,*,DOWN,PDIF +S 900,900,900,2500,600,*,UP,NDIF +S 4500,5400,4500,9400,400,*,DOWN,PDIF +S 5700,5400,5700,9400,600,*,UP,PDIF +S 5000,2900,5000,5400,200,*,UP,POLY +S 4000,2900,4000,5500,200,*,UP,POLY +S 3000,3800,3000,5400,200,*,UP,POLY +S 3000,5400,3000,9400,200,*,UP,PTRANS +S 4000,5400,4000,9400,200,*,UP,PTRANS +S 5000,5400,5000,9400,200,*,UP,PTRANS +S 5800,8200,5800,9000,400,*,UP,ALU1 +S 8000,600,8000,2500,400,*,UP,NDIF +S 6900,600,6900,3200,600,*,UP,NDIF +S 1500,2500,1500,4800,200,*,UP,POLY +S 4000,2500,4000,3100,200,*,UP,POLY +S 5000,2400,5000,2900,200,*,UP,POLY +S 7500,600,7500,2500,200,*,UP,NTRANS +S 7200,600,7200,2500,400,*,UP,NDIF +S 5700,600,5700,2500,400,*,UP,NDIF +S 6200,600,6200,2500,200,*,UP,NTRANS +S 6600,600,6600,2500,400,*,UP,NDIF +S 6200,2300,6200,2800,200,*,UP,POLY +S 7500,2300,7500,4000,200,*,UP,POLY +S 8800,2400,8800,3000,200,*,UP,POLY +S 8700,4700,8700,5400,200,*,UP,POLY +S 2000,5100,2000,5400,200,*,UP,POLY +S 7000,2800,7000,8300,300,nq,UP,CALU1 +S 7000,2800,7000,8300,300,*,UP,ALU1 +S 8300,4800,8800,4800,400,*,RIGHT,POLY +S 9200,1800,9200,7200,300,*,UP,ALU1 +S 8200,600,8200,2500,400,*,UP,NDIF +S 8500,1500,8500,2500,400,*,DOWN,NDIF +S 8300,3200,8500,3200,300,*,RIGHT,ALU1 +S 8400,1900,8400,5000,300,*,UP,ALU1 +S 1000,1900,8400,1900,300,*,RIGHT,ALU1 +S 1000,1900,1000,8200,300,*,UP,ALU1 +S 7500,4000,7500,5400,200,*,UP,POLY +S 1400,4800,2100,4800,200,*,RIGHT,POLY +S 2500,2500,2500,3800,200,*,UP,POLY +S 2400,3800,3100,3800,200,*,RIGHT,POLY +S 8300,3000,8900,3000,200,*,LEFT,POLY +S 2000,1500,2000,2500,400,*,DOWN,NDIF +S 1500,1500,1500,2500,200,*,UP,NTRANS +S 5400,1500,5400,2500,400,*,DOWN,NDIF +S 9200,5400,9200,7500,400,*,UP,PDIF +S 8700,5400,8700,7500,200,*,UP,PTRANS +S 7500,5400,7500,9400,200,*,UP,PTRANS +S 4000,1500,4000,2500,200,*,UP,NTRANS +S 6100,5100,6500,5100,200,*,RIGHT,POLY +S 6200,2800,6200,5100,200,*,UP,POLY +S 8400,5400,8400,7500,400,*,UP,PDIF +S 4500,1500,4500,2500,400,*,DOWN,NDIF +S 3600,1500,3600,2500,400,*,DOWN,NDIF +S 2900,1500,2900,2500,400,*,DOWN,NDIF +S 1200,1500,1200,2500,400,*,DOWN,NDIF +S 6400,5100,6400,5400,200,*,UP,POLY +S 6200,4000,9400,4000,400,*,RIGHT,POLY +S 900,1200,900,1300,300,*,UP,ALU1 +S 1000,5400,1000,9400,600,*,UP,PDIF +S 1400,5400,1400,9400,600,*,UP,PDIF +S 2000,2800,2000,8200,300,i1,UP,CALU1 +S 2000,2800,2000,8200,300,*,UP,ALU1 +S 3000,2800,3000,8200,300,i0,UP,CALU1 +S 3000,2800,3000,8200,300,*,UP,ALU1 +S 4000,2800,4000,8200,300,i2,UP,CALU1 +S 4000,2800,4000,8200,300,*,UP,ALU1 +S 5000,2800,5000,8200,300,*,UP,ALU1 +S 5000,2800,5000,8200,300,i3,UP,CALU1 +S 8000,5800,8000,8800,300,*,UP,ALU1 +S 3300,800,3300,2500,600,*,UP,NDIF +S 9300,1500,9300,2500,400,*,UP,NDIF +S 5600,5400,5600,9400,800,*,UP,PDIF +S 5800,5400,5800,9400,600,*,UP,PDIF +S 7000,5400,7000,9400,600,*,UP,PDIF +S 6400,5400,6400,9400,200,*,UP,PTRANS +S 2000,5400,2000,9400,200,*,UP,PTRANS +S -200,9500,10200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,10200,500,1400,vss,RIGHT,CALU1 +S 5000,1500,5000,2500,200,*,UP,NTRANS +S 2500,1500,2500,2500,200,*,UP,NTRANS +S -500,7500,10500,7500,6000,*,RIGHT,NWELL +S -200,10000,10200,10000,400,*,RIGHT,NTIE +S -200,0,10200,0,400,*,RIGHT,PTIE +S 8800,1500,8800,2500,200,*,UP,NTRANS +V 5800,8300,CONT_DIF_P,* +V 6900,3000,CONT_DIF_N,* +V 8000,9000,CONT_DIF_P,* +V 5800,9000,CONT_DIF_P,* +B 1000,1900,200,200,CONT_TURN1,* +B 8400,1900,200,200,CONT_TURN1,* +V 8000,900,CONT_DIF_N,* +V 8400,3200,CONT_POLY,* +V 8400,4800,CONT_POLY,* +V 5700,900,CONT_DIF_N,* +V 9300,2000,CONT_DIF_N,* +V 2000,1900,CONT_DIF_N,* +V 4500,1900,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 900,1100,CONT_DIF_N,* +V 4000,3000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 7000,8000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,6000,CONT_DIF_P,* +V 1000,6000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 9200,4000,CONT_POLY,* +V 9200,6000,CONT_DIF_P,* +V 9200,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/no4_x4.vbe b/pdks/symbolic/nsxlib2/cells/no4_x4.vbe new file mode 100644 index 000000000..cffb179c4 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/no4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 564; + CONSTANT tphl_i0_nq : NATURAL := 656; + CONSTANT tplh_i3_nq : NATURAL := 693; + CONSTANT tphl_i2_nq : NATURAL := 739; + CONSTANT tplh_i2_nq : NATURAL := 761; + CONSTANT tplh_i1_nq : NATURAL := 768; + CONSTANT tplh_i0_nq : NATURAL := 777; + CONSTANT tphl_i3_nq : NATURAL := 816; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x4; + +ARCHITECTURE behaviour_data_flow OF no4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x4" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa22_x1.ap b/pdks/symbolic/nsxlib2/cells/noa22_x1.ap new file mode 100644 index 000000000..ab5f9bedd --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa22_x1.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H noa22_x1,P,17/ 8/2024,100 +A 0,0,5000,10000 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 4000,3000,ref_ref,i2_15 +R 4000,4000,ref_ref,i2_20 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +R 4000,7000,ref_ref,i2_35 +R 3000,2000,ref_ref,nq_10 +R 3000,3000,ref_ref,nq_15 +R 3000,4000,ref_ref,nq_20 +R 3000,5000,ref_ref,nq_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 1000,2000,ref_ref,i0_10 +R 4000,8000,ref_ref,i2_40 +R 3000,6000,ref_ref,nq_30 +R 3000,7000,ref_ref,nq_35 +R 4000,2000,ref_ref,i2_10 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +S 1500,600,1500,2500,600,*,UP,NDIF +S 3500,5500,3500,9400,400,*,UP,PDIF +S 3000,2800,3000,5600,200,*,UP,POLY +S 2900,4000,4100,4000,200,*,LEFT,POLY +S 600,8000,2600,8000,300,*,RIGHT,ALU1 +S 3000,5500,3000,9400,200,*,UP,PTRANS +S 2500,5500,2500,9400,400,*,UP,PDIF +S 2300,2000,3100,2000,400,*,RIGHT,ALU1 +S 3000,2400,3000,2800,200,*,DOWN,POLY +S 3000,600,3000,2500,200,*,UP,NTRANS +S 3500,600,3500,2500,400,*,UP,NDIF +S 2000,600,2000,2500,200,*,UP,NTRANS +S 2000,2500,2000,5200,200,*,UP,POLY +S 2000,5200,2000,5500,200,*,UP,POLY +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 1500,5500,1500,9400,400,*,UP,PDIF +S 1000,600,1000,2500,200,*,UP,NTRANS +S 500,600,500,2500,400,*,UP,NDIF +S 900,5200,1100,5200,200,*,RIGHT,POLY +S 1000,5200,1000,5500,200,*,UP,POLY +S 1000,2500,1000,5300,200,*,UP,POLY +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 500,5500,500,9400,400,*,UP,PDIF +S 500,6800,500,8200,300,*,UP,ALU1 +S 1600,7000,3000,7000,300,*,RIGHT,ALU1 +S 2000,2800,2000,6200,300,*,UP,ALU1 +S 2000,2800,2000,6200,300,i1,UP,CALU1 +S 3000,1800,3000,7200,300,*,UP,ALU1 +S 2400,600,2400,2500,600,*,UP,NDIF +S 2300,600,2300,2500,200,*,UP,NDIF +S 1000,1800,1000,6200,300,i0,UP,CALU1 +S 1000,1800,1000,6200,300,*,UP,ALU1 +S 3000,1800,3000,7200,300,nq,UP,CALU1 +S 4000,1800,4000,8200,300,*,UP,ALU1 +S 4000,1800,4000,8200,300,i2,UP,CALU1 +S -200,10000,5200,10000,400,*,RIGHT,NTIE +S -200,9500,5200,9500,1400,vdd,RIGHT,CALU1 +S -200,0,5200,0,400,*,RIGHT,PTIE +S -200,500,5200,500,1400,vss,RIGHT,CALU1 +S -500,7500,5500,7500,6000,*,RIGHT,NWELL +V 500,7000,CONT_DIF_P,* +V 3500,9000,CONT_DIF_P,* +V 2500,8000,CONT_DIF_P,* +V 2500,2000,CONT_DIF_N,* +V 3500,900,CONT_DIF_N,* +V 1500,7000,CONT_DIF_P,* +V 500,900,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa22_x1.vbe b/pdks/symbolic/nsxlib2/cells/noa22_x1.vbe new file mode 100644 index 000000000..5c13864f3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 1620; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tphl_i2_nq : NATURAL := 218; + CONSTANT tplh_i2_nq : NATURAL := 241; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x1; + +ARCHITECTURE behaviour_data_flow OF noa22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 900 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa22_x4.ap b/pdks/symbolic/nsxlib2/cells/noa22_x4.ap new file mode 100644 index 000000000..bf0d19166 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa22_x4.ap @@ -0,0 +1,154 @@ +V ALLIANCE : 6 +H noa22_x4,P,14/ 8/2024,100 +A 0,0,9000,10000 +R 7000,2000,ref_ref,nq_10 +R 7000,3000,ref_ref,nq_15 +R 7000,4000,ref_ref,nq_20 +R 7000,5000,ref_ref,nq_25 +R 7000,6000,ref_ref,nq_30 +R 7000,7000,ref_ref,nq_35 +R 7000,8000,ref_ref,nq_40 +R 4000,3000,ref_ref,i0_15 +R 4000,2000,ref_ref,i0_10 +R 3000,5000,ref_ref,i1_25 +R 1000,4000,ref_ref,i2_20 +R 1000,3000,ref_ref,i2_15 +R 3000,4000,ref_ref,i1_20 +R 1000,7000,ref_ref,i2_35 +R 1000,5000,ref_ref,i2_25 +R 1000,6000,ref_ref,i2_30 +R 4000,4000,ref_ref,i0_20 +R 4000,5000,ref_ref,i0_25 +R 4000,6000,ref_ref,i0_30 +R 3000,6000,ref_ref,i1_30 +R 3000,3000,ref_ref,i1_15 +R 3000,2000,ref_ref,i1_10 +S 3000,6100,3000,6700,200,*,UP,POLY +S 7500,2300,7500,5500,200,*,UP,POLY +S 5200,2400,5200,5500,200,*,UP,POLY +S 1300,2000,2200,2000,500,*,RIGHT,ALU1 +S 2000,2000,2000,7000,300,*,UP,ALU1 +S 4700,4000,6300,4000,300,*,RIGHT,ALU1 +S 2000,7000,5600,7000,300,*,RIGHT,ALU1 +S 5600,4800,5600,7000,300,*,UP,ALU1 +S 5900,5500,5900,9400,600,*,UP,PDIF +S 6000,7800,6000,8900,300,*,UP,ALU1 +S 8000,1100,8000,2200,300,*,UP,ALU1 +S 6000,600,6000,2500,400,*,UP,NDIF +S 5900,4000,7600,4000,500,*,RIGHT,POLY +S 5200,5000,5700,5000,500,*,RIGHT,POLY +S 5800,5500,5800,7500,600,*,UP,PDIF +S 8000,5500,8000,9400,400,*,UP,PDIF +S 8000,5800,8000,8900,300,*,UP,ALU1 +S 7500,5500,7500,9400,200,*,UP,PTRANS +S 8000,600,8000,2500,400,*,UP,NDIF +S 7500,600,7500,2500,200,*,UP,NTRANS +S 5700,1500,5700,2500,600,*,UP,NDIF +S 6000,1100,6000,2200,300,*,UP,ALU1 +S 5200,1500,5200,2500,200,*,UP,NTRANS +S 5200,5500,5200,7500,200,*,UP,PTRANS +S 4700,1800,4700,6200,300,*,UP,ALU1 +S 3500,1200,3500,1400,300,*,UP,ALU1 +S 3000,1000,3000,2500,200,*,UP,NTRANS +S 2500,1000,2500,2500,600,*,UP,NDIF +S 1900,3900,3100,3900,200,*,RIGHT,POLY +S 2000,2500,2000,3900,200,*,UP,POLY +S 1000,2800,1000,7200,300,i2,UP,CALU1 +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 1500,1000,1500,2500,400,*,UP,NDIF +S 2000,1000,2000,2500,200,*,UP,NTRANS +S 600,1000,600,2500,600,*,UP,NDIF +S 1000,1000,1000,2500,200,*,UP,NTRANS +S 500,1200,500,1400,300,*,UP,ALU1 +S 500,8000,500,9200,300,*,DOWN,ALU1 +S 1900,5600,3000,5600,200,*,RIGHT,POLY +S 1300,8000,3600,8000,300,*,RIGHT,ALU1 +S 2000,5600,2000,6500,200,*,UP,POLY +S 1000,2500,1000,6500,200,*,UP,POLY +S 2400,6500,2400,9400,600,*,UP,PDIF +S 1400,6500,1400,9400,600,*,UP,PDIF +S 3000,6500,3000,9400,200,*,UP,PTRANS +S 2000,6500,2000,9400,200,*,UP,PTRANS +S 1000,6500,1000,9400,200,*,UP,PTRANS +S 500,6500,500,9400,400,*,UP,PDIF +S 3500,1000,3500,2500,400,*,UP,NDIF +S 3500,6500,3500,9400,400,*,UP,PDIF +S 6500,4000,6500,5500,200,*,DOWN,POLY +S 6700,2800,6700,3900,200,*,UP,POLY +S 6500,2500,6500,2800,200,*,DOWN,POLY +S 3000,2500,3000,2800,200,*,DOWN,POLY +S 3000,3900,3000,5700,200,*,UP,POLY +S -200,0,9200,0,400,*,RIGHT,PTIE +S -200,500,9200,500,1400,vss,RIGHT,CALU1 +S -500,7500,9500,7500,6000,*,RIGHT,NWELL +S -200,10000,9200,10000,400,*,RIGHT,NTIE +S -200,9500,9200,9500,1400,vdd,RIGHT,CALU1 +S 6400,2800,6800,2800,200,*,RIGHT,POLY +S 7000,1700,7000,8200,300,nq,UP,CALU1 +S 7000,1700,7000,8200,300,*,UP,ALU1 +S 7100,5500,7100,9400,600,*,UP,PDIF +S 7100,600,7100,2500,600,*,UP,NDIF +S 6500,5500,6500,9400,200,*,UP,PTRANS +S 4700,5500,4700,7500,600,*,UP,PDIF +S 6500,600,6500,2500,200,*,UP,NTRANS +S 4700,1500,4700,2500,600,*,UP,NDIF +S 3000,6200,4100,6200,200,*,RIGHT,POLY +S 2900,2800,4100,2800,200,*,RIGHT,POLY +S 4000,1700,4000,5900,300,i0,UP,CALU1 +S 4000,1700,4000,5900,300,*,UP,ALU1 +S 3000,1800,3000,6200,300,*,UP,ALU1 +S 3000,1800,3000,6200,300,i1,UP,CALU1 +S 4000,2800,4000,6200,200,*,UP,POLY +V 2500,7100,CONT_DIF_P,* +B 2000,2000,200,200,CONT_TURN1,* +B 5600,7000,200,200,CONT_TURN1,* +B 2000,7000,200,200,CONT_TURN1,* +V 6000,9200,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 8000,9200,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 8000,2000,CONT_DIF_N,* +V 8000,900,CONT_DIF_N,* +V 6000,900,CONT_DIF_N,* +V 6000,2000,CONT_DIF_N,* +V 4700,6000,CONT_DIF_P,* +V 4700,2000,CONT_DIF_N,* +V 3500,1200,CONT_DIF_N,* +V 1500,2000,CONT_DIF_N,* +V 500,1200,CONT_DIF_N,* +V 500,8200,CONT_DIF_P,* +V 3500,8000,CONT_DIF_P,* +V 1500,8000,CONT_DIF_P,* +V 500,9200,CONT_DIF_P,* +V 7000,2000,CONT_DIF_N,* +V 7000,6000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 6100,4000,CONT_POLY,* +V 5600,5000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa22_x4.vbe b/pdks/symbolic/nsxlib2/cells/noa22_x4.vbe new file mode 100644 index 000000000..6288a32e6 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 550; + CONSTANT tphl_i2_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i2_nq : NATURAL := 646; + CONSTANT tplh_i1_nq : NATURAL := 709; + CONSTANT tplh_i0_nq : NATURAL := 740; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x4; + +ARCHITECTURE behaviour_data_flow OF noa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa2a22_x1.ap b/pdks/symbolic/nsxlib2/cells/noa2a22_x1.ap new file mode 100644 index 000000000..f4031b4a4 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a22_x1.ap @@ -0,0 +1,99 @@ +V ALLIANCE : 6 +H noa2a22_x1,P,17/ 8/2024,100 +A 0,0,6000,10000 +R 4000,5000,ref_ref,i3_25 +R 4000,4000,ref_ref,i3_20 +R 4000,3000,ref_ref,i3_15 +R 1000,2000,ref_ref,i0_10 +R 1000,3000,ref_ref,i0_15 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 4000,2000,ref_ref,i3_10 +R 2000,2000,ref_ref,i1_10 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 4000,6000,ref_ref,i3_30 +R 4000,7000,ref_ref,i3_35 +R 5000,7000,ref_ref,i2_35 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +R 5000,4000,ref_ref,i2_20 +R 5000,3000,ref_ref,i2_15 +R 5000,2000,ref_ref,i2_10 +R 3000,2000,ref_ref,nq_10 +R 3000,3000,ref_ref,nq_15 +R 3000,4000,ref_ref,nq_20 +R 3000,5000,ref_ref,nq_25 +R 3000,6000,ref_ref,nq_30 +R 3000,7000,ref_ref,nq_35 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +S 3000,600,3000,2500,1400,*,UP,NDIF +S 3000,5500,3000,9400,1400,*,UP,PDIF +S 600,8300,5600,8300,300,*,RIGHT,ALU1 +S 1600,600,1600,2500,600,*,UP,NDIF +S 2000,2500,2000,5500,200,*,UP,POLY +S 2000,600,2000,2500,200,*,UP,NTRANS +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 1500,5500,1500,9400,400,*,UP,PDIF +S 1000,600,1000,2500,200,*,UP,NTRANS +S 500,600,500,2500,400,*,UP,NDIF +S 1000,2500,1000,5500,200,*,UP,POLY +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 500,5500,500,9400,400,*,UP,PDIF +S 4000,2500,4000,5500,200,*,UP,POLY +S 4000,600,4000,2500,200,*,UP,NTRANS +S 4400,600,4400,2500,600,*,UP,NDIF +S 5000,2300,5000,5700,200,*,UP,POLY +S 5000,600,5000,2500,200,*,UP,NTRANS +S 5600,600,5600,2500,600,*,UP,NDIF +S 4000,5500,4000,9400,200,*,UP,PTRANS +S 4500,5500,4500,9400,800,*,UP,PDIF +S 5000,5500,5000,9400,200,*,UP,PTRANS +S 5500,5500,5500,9400,600,*,UP,PDIF +S -500,7500,6600,7500,6000,*,RIGHT,NWELL +S 1400,7000,3100,7000,300,*,RIGHT,ALU1 +S -200,10000,6200,10000,400,*,RIGHT,NTIE +S -200,9500,6200,9500,1400,vdd,RIGHT,CALU1 +S -200,0,6200,0,400,*,RIGHT,PTIE +S -200,500,6200,500,1400,vss,RIGHT,CALU1 +S 2600,600,2600,2500,600,*,UP,NDIF +S 1000,1800,1000,6200,300,i0,UP,CALU1 +S 1000,1800,1000,6200,300,*,UP,ALU1 +S 2000,1800,2000,6200,300,*,UP,ALU1 +S 2000,1800,2000,6200,300,i1,UP,CALU1 +S 3000,1800,3000,7200,300,nq,UP,CALU1 +S 3000,1800,3000,7200,300,*,UP,ALU1 +S 4000,1800,4000,7200,300,*,UP,ALU1 +S 4000,1800,4000,7200,300,i3,UP,CALU1 +S 5000,1800,5000,7200,300,i2,UP,CALU1 +S 5000,1800,5000,7200,300,*,UP,ALU1 +V 3000,8300,CONT_DIF_P,* +V 1500,7000,CONT_DIF_P,* +V 500,1000,CONT_DIF_N,* +V 500,8300,CONT_DIF_P,* +V 5500,1000,CONT_DIF_N,* +V 4500,9000,CONT_DIF_P,* +V 5500,8300,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 3000,2000,CONT_DIF_N,* +V 5000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa2a22_x1.vbe b/pdks/symbolic/nsxlib2/cells/noa2a22_x1.vbe new file mode 100644 index 000000000..d63481981 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i3_nq : NATURAL := 256; + CONSTANT tphl_i2_nq : NATURAL := 284; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i2_nq : NATURAL := 289; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT tphl_i3_nq : NATURAL := 372; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa2a22_x4.ap b/pdks/symbolic/nsxlib2/cells/noa2a22_x4.ap new file mode 100644 index 000000000..f2a3e697e --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a22_x4.ap @@ -0,0 +1,163 @@ +V ALLIANCE : 6 +H noa2a22_x4,P,17/ 8/2024,100 +A 0,0,11000,10000 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_10 +R 9000,3000,ref_ref,nq_15 +R 9000,2000,ref_ref,nq_10 +R 9000,4000,ref_ref,nq_20 +R 9000,6000,ref_ref,nq_30 +R 4000,2000,ref_ref,i3_10 +R 4000,3000,ref_ref,i3_15 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 9000,7000,ref_ref,nq_35 +R 9000,5000,ref_ref,nq_25 +R 9000,8000,ref_ref,nq_40 +R 5000,2000,ref_ref,i2_10 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +R 4000,4000,ref_ref,i3_20 +R 4000,5000,ref_ref,i3_25 +R 4000,6000,ref_ref,i3_30 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +S 8000,600,8000,2500,400,*,UP,NDIF +S 8000,5500,8000,9400,400,*,UP,PDIF +S 10000,5500,10000,9400,400,*,UP,PDIF +S 2700,6500,2700,8500,800,*,UP,PDIF +S 2700,1500,2700,2500,800,*,UP,NDIF +S -500,7500,11500,7500,6000,*,RIGHT,NWELL +S 500,1100,500,2200,500,*,UP,ALU1 +S 1500,1500,1500,2500,600,*,UP,NDIF +S 2000,1500,2000,2500,200,*,UP,NTRANS +S 2000,2500,2000,6500,200,*,UP,POLY +S 2000,6500,2000,8500,200,*,UP,PTRANS +S 1600,6500,1600,8500,600,*,UP,PDIF +S 1000,6500,1000,8500,200,*,UP,PTRANS +S 500,6500,500,8500,400,*,UP,PDIF +S 1000,2500,1000,6500,200,*,UP,POLY +S 1000,1500,1000,2500,200,*,UP,NTRANS +S 500,1500,500,2500,600,*,UP,NDIF +S 8500,2500,8500,5500,200,*,UP,POLY +S 9500,2500,9500,5500,200,*,UP,POLY +S 7100,2500,7100,5500,200,*,UP,POLY +S 4600,2500,4600,2800,200,*,UP,POLY +S 3300,2500,3300,2800,200,*,UP,POLY +S 7700,1500,7700,2500,600,*,UP,NDIF +S 10000,600,10000,2500,600,*,UP,NDIF +S 10000,700,10000,2200,300,*,UP,ALU1 +S 8500,600,8500,2500,200,*,UP,NTRANS +S 9500,600,9500,2500,200,*,UP,NTRANS +S 7100,5000,7700,5000,500,*,RIGHT,POLY +S 7900,4000,9600,4000,200,*,RIGHT,POLY +S 8000,7800,8000,9400,300,*,UP,ALU1 +S 8500,5500,8500,9400,200,*,UP,PTRANS +S 9500,5500,9500,9400,200,*,UP,PTRANS +S 7700,5500,7700,7500,600,*,UP,PDIF +S 7100,5500,7100,7500,200,*,UP,PTRANS +S 7100,1500,7100,2500,200,*,UP,NTRANS +S 4000,1500,4000,2500,800,*,UP,NDIF +S 3200,2800,4100,2800,200,*,RIGHT,POLY +S 3300,1500,3300,2500,200,*,UP,NTRANS +S 2800,1800,2800,7200,300,*,UP,ALU1 +S 3800,6500,3800,8500,400,*,UP,PDIF +S 4500,6500,4500,8500,400,*,UP,PDIF +S 5100,1500,5100,2500,600,*,UP,NDIF +S 5000,2800,5000,6200,200,*,UP,POLY +S 4000,2800,4000,6100,200,*,UP,POLY +S 5500,6500,5500,8500,400,*,UP,PDIF +S 8000,700,8000,2200,300,*,UP,ALU1 +S 6400,4000,8000,4000,300,*,RIGHT,ALU1 +S 10000,5800,10000,9400,300,*,UP,ALU1 +S 600,8000,5600,8000,300,*,RIGHT,ALU1 +S 4500,2800,5100,2800,200,*,RIGHT,POLY +S 3300,6100,4100,6100,200,*,RIGHT,POLY +S 7600,4800,7600,7200,300,*,UP,ALU1 +S 1600,7000,7800,7000,300,*,RIGHT,ALU1 +S 5000,1800,5000,6200,300,*,UP,ALU1 +S 6600,1800,6600,6200,300,*,UP,ALU1 +S 6600,1500,6600,2500,600,*,UP,NDIF +S 4000,1800,4000,6200,300,*,UP,ALU1 +S 2000,1800,2000,6200,300,*,UP,ALU1 +S 9000,5500,9000,9400,600,*,UP,PDIF +S 6600,5500,6600,7500,600,*,UP,PDIF +S 5000,6500,5000,8500,200,*,UP,PTRANS +S 3400,6500,3400,8500,200,*,UP,PTRANS +S 4600,1500,4600,2500,200,*,UP,NTRANS +S 5000,6000,5000,6500,200,*,UP,POLY +S 3400,6000,3400,6500,200,*,UP,POLY +S 4200,6500,4200,9300,600,*,UP,PDIF +S 5400,700,5400,2500,600,*,UP,NDIF +S -200,10000,11200,10000,400,*,RIGHT,NTIE +S -200,0,11200,0,400,*,RIGHT,PTIE +S 9000,1800,9000,8200,300,*,UP,ALU1 +S 9000,600,9000,2500,600,*,UP,NDIF +S -200,500,11200,500,1400,vss,RIGHT,CALU1 +S -200,9500,11200,9500,1400,vdd,RIGHT,CALU1 +S 1000,2700,1000,6200,300,i0,UP,CALU1 +S 9000,1800,9000,8200,300,nq,UP,CALU1 +S 5000,1800,5000,6200,300,i2,UP,CALU1 +S 4000,1800,4000,6200,300,i3,UP,CALU1 +S 2000,1800,2000,6200,300,i1,UP,CALU1 +S 1000,2700,1000,6200,300,*,UP,ALU1 +V 10000,9000,CONT_DIF_P,* +V 8000,9000,CONT_DIF_P,* +V 1500,7000,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 10000,900,CONT_DIF_N,* +V 10000,2000,CONT_DIF_N,* +V 8000,8000,CONT_DIF_P,* +V 5500,8000,CONT_DIF_P,* +V 2800,2000,CONT_DIF_N,* +V 2800,8000,CONT_DIF_P,* +V 7600,5000,CONT_POLY,* +V 4200,9000,CONT_DIF_P,* +V 7800,4000,CONT_POLY,* +V 8000,2000,CONT_DIF_N,* +V 4000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 6600,6000,CONT_DIF_P,* +V 6600,2000,CONT_DIF_N,* +V 9000,2000,CONT_DIF_N,* +V 9000,6000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,6000,CONT_DIF_P,* +V 5000,4000,CONT_POLY,* +V 8000,900,CONT_DIF_N,* +V 5400,900,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa2a22_x4.vbe b/pdks/symbolic/nsxlib2/cells/noa2a22_x4.vbe new file mode 100644 index 000000000..93e31d341 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 562; + CONSTANT tphl_i1_nq : NATURAL := 646; + CONSTANT tplh_i3_nq : NATURAL := 677; + CONSTANT tphl_i2_nq : NATURAL := 701; + CONSTANT tplh_i2_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 714; + CONSTANT tplh_i0_nq : NATURAL := 745; + CONSTANT tphl_i3_nq : NATURAL := 805; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa2a2a23_x1.ap b/pdks/symbolic/nsxlib2/cells/noa2a2a23_x1.ap new file mode 100644 index 000000000..5ccc3d327 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a2a23_x1.ap @@ -0,0 +1,156 @@ +V ALLIANCE : 6 +H noa2a2a23_x1,P,23/12/2024,100 +A 0,0,8000,10000 +R 5000,5000,ref_ref,i2_20 +R 5000,4000,ref_ref,i2_25 +R 4000,5000,ref_ref,i3_30 +R 4000,6000,ref_ref,i3_25 +R 3000,5000,ref_ref,i4_30 +R 3000,6000,ref_ref,i4_25 +R 2000,5000,ref_ref,i5_30 +R 2000,6000,ref_ref,i5_25 +R 6000,5000,ref_ref,i1_25 +R 7000,6000,ref_ref,i0_30 +R 7000,3000,ref_ref,i0_15 +R 7000,4000,ref_ref,i0_20 +R 7000,5000,ref_ref,i0_25 +R 6000,6000,ref_ref,i1_30 +R 6000,3000,ref_ref,i1_15 +R 6000,4000,ref_ref,i1_20 +R 1000,6000,ref_ref,nq_30 +R 1000,7000,ref_ref,nq_35 +R 1000,3000,ref_ref,nq_15 +R 1000,4000,ref_ref,nq_20 +R 2000,3000,ref_ref,i5_15 +R 4000,3000,ref_ref,i3_15 +R 5000,3000,ref_ref,i2_15 +R 1000,2000,ref_ref,nq_10 +R 1000,5000,ref_ref,nq_25 +R 3000,4000,ref_ref,i4_20 +R 3000,3000,ref_ref,i4_15 +R 5000,6000,ref_ref,i2_30 +R 2000,4000,ref_ref,i5_20 +R 4000,4000,ref_ref,i3_20 +S 2900,5000,3300,5000,200,*,RIGHT,POLY +S 3200,4600,3200,5000,200,*,UP,POLY +S 3000,4900,3000,5500,200,*,DOWN,POLY +S 3100,4600,3700,4600,200,*,RIGHT,POLY +S 2500,4000,2700,4000,495,*,RIGHT,POLY +S 3600,3400,3600,4700,200,*,UP,POLY +S 2700,600,2700,2500,800,*,UP,NDIF +S 3900,2900,5100,2900,200,*,RIGHT,POLY +S 5000,2900,5000,5100,200,*,UP,POLY +S 3300,3400,3700,3400,200,*,RIGHT,POLY +S 500,5400,500,9300,400,*,UP,PDIF +S 1000,5400,1000,9300,200,*,UP,PTRANS +S 1500,5400,1500,9300,400,*,UP,PDIF +S 2000,5400,2000,9300,200,*,UP,PTRANS +S 2500,5400,2500,9300,400,*,UP,PDIF +S 3500,5400,3500,9300,400,*,UP,PDIF +S 3000,5400,3000,9300,200,*,UP,PTRANS +S 4000,5400,4000,9300,200,*,UP,PTRANS +S 4400,5400,4400,9300,600,*,UP,PDIF +S 3400,2500,3400,3400,200,*,UP,POLY +S 3400,600,3400,2500,200,*,UP,NTRANS +S 4000,2500,4000,2900,200,*,DOWN,POLY +S 4000,600,4000,2500,200,*,UP,NTRANS +S 4500,600,4500,2500,400,*,UP,NDIF +S 6000,2500,6000,5500,200,*,UP,POLY +S 4000,5100,4000,5500,200,*,UP,POLY +S 2000,4800,2000,5500,200,*,UP,POLY +S 1000,2400,1000,5500,200,*,DOWN,POLY +S 7000,2500,7000,5500,200,*,UP,POLY +S 3900,5100,4900,5100,200,*,RIGHT,POLY +S 800,7000,1600,7000,500,*,LEFT,ALU1 +S 6500,600,6500,2500,600,*,UP,NDIF +S 900,2000,5600,2000,300,*,RIGHT,ALU1 +S 5600,600,5600,2500,600,*,UP,NDIF +S 6000,600,6000,2500,200,*,UP,NTRANS +S -200,0,8300,0,400,*,RIGHT,PTIE +S -200,500,8300,500,1400,vss,RIGHT,CALU1 +S -500,7500,8500,7500,6000,*,RIGHT,NWELL +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +S 7500,600,7500,2500,400,*,UP,NDIF +S 7500,700,7500,2200,300,*,UP,ALU1 +S 7000,600,7000,2500,200,*,UP,NTRANS +S 7500,5500,7500,9400,400,*,UP,PDIF +S 7500,6800,7500,9100,300,*,UP,ALU1 +S 7000,5500,7000,9400,200,*,UP,PTRANS +S 6500,5500,6500,9400,400,*,UP,PDIF +S 6500,7000,6500,8200,300,*,UP,ALU1 +S 6000,5500,6000,9400,200,*,UP,PTRANS +S 5600,5500,5600,9400,600,*,UP,PDIF +S 5500,7800,5500,9300,300,*,UP,ALU1 +S 2000,2800,2000,5200,400,*,DOWN,ALU1 +S 2500,3400,2500,5000,200,*,UP,POLY +S 1900,4900,2600,4900,200,*,RIGHT,POLY +S 900,4000,1800,4000,200,*,RIGHT,POLY +S 2600,4000,3100,4000,400,*,RIGHT,ALU1 +S 3400,7000,6600,7000,300,*,RIGHT,ALU1 +S 1900,2800,2600,2800,200,*,RIGHT,POLY +S 2500,2800,2500,3400,200,*,UP,POLY +S 2000,2500,2000,2800,200,*,DOWN,POLY +S 1500,600,1500,2500,400,*,UP,NDIF +S 2000,600,2000,2500,200,*,UP,NTRANS +S 1000,600,1000,2500,200,*,UP,NTRANS +S 500,600,500,2500,400,*,UP,NDIF +S 3600,4000,4100,4000,500,*,RIGHT,POLY +S 400,8200,4600,8200,300,*,RIGHT,ALU1 +S 7000,2800,7000,6200,300,*,UP,ALU1 +S 7000,2800,7000,6200,300,i0,UP,CALU1 +S 6000,2800,6000,6200,300,*,UP,ALU1 +S 6000,2800,6000,6200,300,i1,UP,CALU1 +S 3000,2800,3000,6200,300,*,UP,ALU1 +S 3000,2800,3000,6200,300,i4,UP,CALU1 +S 1000,1800,1000,7200,300,*,UP,ALU1 +S 1000,1800,1000,7200,300,nq,UP,CALU1 +S 5000,2800,5000,6200,300,*,UP,ALU1 +S 5000,2800,5000,6200,300,i2,UP,CALU1 +S 4000,2800,4000,6200,300,*,UP,ALU1 +S 4000,2800,4000,6200,300,i3,UP,CALU1 +S 2000,2800,2000,6200,300,*,UP,ALU1 +S 2000,2800,2000,6200,300,i5,UP,CALU1 +V 5000,5000,CONT_POLY,* +V 4500,900,CONT_DIF_N,* +V 6000,4000,CONT_POLY,* +V 7000,4000,CONT_POLY,* +B 1000,2000,200,200,CONT_TURN1,* +V 5500,2000,CONT_DIF_N,* +V 7500,900,CONT_DIF_N,* +V 7500,2000,CONT_DIF_N,* +V 7500,9200,CONT_DIF_P,* +V 7500,8000,CONT_DIF_P,* +V 7500,7000,CONT_DIF_P,* +B 6500,7000,200,200,CONT_TURN1,* +V 6500,8000,CONT_DIF_P,* +V 5500,8000,CONT_DIF_P,* +V 2800,4000,CONT_POLY,* +V 1800,4000,CONT_POLY,* +V 2500,2000,CONT_DIF_N,* +V 500,900,CONT_DIF_N,* +V 1500,7000,CONT_DIF_P,* +V 4500,8200,CONT_DIF_P,* +V 3500,7000,CONT_DIF_P,* +V 2500,8200,CONT_DIF_P,* +V 500,8200,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa2a2a23_x1.vbe b/pdks/symbolic/nsxlib2/cells/noa2a2a23_x1.vbe new file mode 100644 index 000000000..2d90886a0 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a2a23_x1.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT rup_i3_nq : NATURAL := 4690; + CONSTANT rup_i4_nq : NATURAL := 4690; + CONSTANT rup_i5_nq : NATURAL := 4690; + CONSTANT tphl_i5_nq : NATURAL := 178; + CONSTANT tphl_i4_nq : NATURAL := 250; + CONSTANT tphl_i2_nq : NATURAL := 307; + CONSTANT tplh_i1_nq : NATURAL := 388; + CONSTANT tphl_i3_nq : NATURAL := 398; + CONSTANT tplh_i4_nq : NATURAL := 416; + CONSTANT tplh_i0_nq : NATURAL := 425; + CONSTANT tplh_i3_nq : NATURAL := 438; + CONSTANT tplh_i5_nq : NATURAL := 464; + CONSTANT tplh_i2_nq : NATURAL := 479; + CONSTANT tphl_i0_nq : NATURAL := 525; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa2a2a23_x4.ap b/pdks/symbolic/nsxlib2/cells/noa2a2a23_x4.ap new file mode 100644 index 000000000..1cddc7f7d --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a2a23_x4.ap @@ -0,0 +1,185 @@ +V ALLIANCE : 6 +H noa2a2a23_x4,P,17/ 8/2024,100 +A 0,0,13000,10000 +R 10000,8000,ref_ref,nq_40 +R 10000,3000,ref_ref,nq_15 +R 10000,7000,ref_ref,nq_35 +R 10000,6000,ref_ref,nq_30 +R 10000,5000,ref_ref,nq_25 +R 10000,4000,ref_ref,nq_20 +R 8000,3000,ref_ref,i0_15 +R 8000,6000,ref_ref,i0_30 +R 7000,6000,ref_ref,i1_30 +R 7000,5000,ref_ref,i1_25 +R 7000,3000,ref_ref,i1_15 +R 7000,4000,ref_ref,i1_20 +R 8000,5000,ref_ref,i0_25 +R 8000,4000,ref_ref,i0_20 +R 3000,6000,ref_ref,i4_30 +R 3000,5000,ref_ref,i4_25 +R 3000,4000,ref_ref,i4_20 +R 3000,3000,ref_ref,i4_15 +R 4000,4000,ref_ref,i3_20 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +R 5000,4000,ref_ref,i2_20 +R 5000,3000,ref_ref,i2_15 +R 4000,6000,ref_ref,i3_30 +R 4000,5000,ref_ref,i3_25 +R 4000,3000,ref_ref,i3_15 +R 2000,3000,ref_ref,i5_15 +R 2000,6000,ref_ref,i5_30 +R 2000,5000,ref_ref,i5_25 +R 2000,4000,ref_ref,i5_20 +S 11300,600,11300,2500,600,*,UP,NDIF +S 1300,5500,1300,9400,800,*,UP,PDIF +S 8700,5500,8700,9400,800,*,UP,PDIF +S 12600,5500,12600,7500,400,*,UP,PDIF +S 8600,600,8600,2500,800,*,UP,NDIF +S 4400,7000,7700,7000,300,*,RIGHT,ALU1 +S 3000,2800,3000,6200,300,i4,UP,CALU1 +S 3000,2800,3000,6200,300,*,UP,ALU1 +S 7700,600,7700,2500,400,*,UP,NDIF +S 8000,600,8000,2500,200,*,UP,NTRANS +S 8000,2500,8000,5500,200,*,UP,POLY +S 7500,5500,7500,9400,800,*,UP,PDIF +S 8000,5500,8000,9400,200,*,UP,PTRANS +S 7500,6900,7500,8200,300,*,UP,ALU1 +S 5000,2500,5000,5600,200,*,UP,POLY +S 4000,2400,4000,5600,200,*,UP,POLY +S 3000,2500,3000,5500,200,*,UP,POLY +S 2000,2500,2000,5600,200,*,UP,POLY +S 2500,600,2500,2500,600,*,UP,NDIF +S 2000,600,2000,2500,200,*,UP,NTRANS +S 1500,600,1500,2500,400,*,UP,NDIF +S 3000,600,3000,2500,200,*,UP,NTRANS +S 3500,600,3500,2500,600,*,UP,NDIF +S 4000,600,4000,2500,200,*,UP,NTRANS +S 4500,600,4500,2500,600,*,UP,NDIF +S 5000,600,5000,2500,200,*,UP,NTRANS +S 5500,600,5500,2500,600,*,UP,NDIF +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 2500,5500,2500,9400,600,*,UP,PDIF +S 3000,5500,3000,9400,200,*,UP,PTRANS +S 3500,5500,3500,9400,600,*,UP,PDIF +S 4000,5500,4000,9400,200,*,UP,PTRANS +S 4600,5500,4600,9400,600,*,UP,PDIF +S 5000,5500,5000,9400,200,*,UP,PTRANS +S 5500,5500,5500,9400,600,*,UP,PDIF +S 9300,2400,9300,5500,200,*,UP,POLY +S 10700,2500,10700,5600,200,*,UP,POLY +S 12000,2500,12000,5500,200,*,UP,POLY +S 11200,6900,11200,9400,400,*,UP,ALU1 +S 8800,6900,8800,9400,400,*,UP,ALU1 +S 10700,4000,11100,4000,500,*,RIGHT,POLY +S 11300,3000,12000,3000,200,*,RIGHT,POLY +S 10700,600,10700,2500,200,*,UP,NTRANS +S 10300,600,10300,2500,400,*,UP,NDIF +S 9700,600,9700,2500,400,*,UP,NDIF +S 10000,2200,10000,8200,300,*,UP,ALU1 +S 800,1700,11600,1700,300,*,RIGHT,ALU1 +S 10000,600,10000,3200,400,*,UP,NDIF +S 9300,600,9300,2500,200,*,UP,NTRANS +S 12500,1800,12500,7200,300,*,UP,ALU1 +S 10700,5500,10700,9400,200,*,UP,PTRANS +S 9300,5500,9300,9400,200,*,UP,PTRANS +S 11600,1500,11600,2500,400,*,UP,NDIF +S 11600,5500,11600,7500,400,*,UP,PDIF +S 10000,5500,10000,9400,1000,*,UP,PDIF +S 6500,5500,6500,9400,400,*,UP,PDIF +S 7400,2500,7400,2900,200,*,UP,POLY +S 9200,4000,10700,4000,200,*,RIGHT,POLY +S 800,6900,2500,6900,300,*,RIGHT,ALU1 +S 1100,8000,5600,8000,300,*,RIGHT,ALU1 +S 11400,1800,11400,3200,300,*,UP,ALU1 +S 12500,1500,12500,2500,400,*,UP,NDIF +S -200,9500,13200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,13200,500,1400,vss,RIGHT,CALU1 +S 6800,600,6800,2500,600,*,UP,NDIF +S 7400,600,7400,2500,200,*,UP,NTRANS +S 10800,4000,12600,4000,300,*,RIGHT,ALU1 +S 7000,5500,7000,9400,200,*,UP,PTRANS +S 11200,5500,11200,9400,600,*,UP,PDIF +S 6900,2900,7500,2900,200,*,RIGHT,POLY +S 8000,2800,8000,6200,300,*,UP,ALU1 +S 7000,4900,7000,5500,200,*,UP,POLY +S 12000,1500,12000,2500,200,*,UP,NTRANS +S 7000,2800,7000,6200,300,*,UP,ALU1 +S 1000,1800,1000,7100,300,*,UP,ALU1 +S -500,7500,13500,7500,6000,*,RIGHT,NWELL +S -200,10000,13200,10000,400,*,RIGHT,NTIE +S -200,0,13200,0,400,*,RIGHT,PTIE +S 5000,2800,5000,6200,300,*,UP,ALU1 +S 4000,2800,4000,6200,300,*,UP,ALU1 +S 2000,2800,2000,6200,300,*,UP,ALU1 +S 12000,5500,12000,7500,200,*,UP,PTRANS +S 7000,2900,7000,5100,200,*,UP,POLY +S 10000,2800,10000,8200,300,nq,UP,CALU1 +S 8000,2800,8000,6200,300,i0,UP,CALU1 +S 7000,2800,7000,6200,300,i1,UP,CALU1 +S 5000,2800,5000,6200,300,i2,UP,CALU1 +S 4000,2800,4000,6200,300,i3,UP,CALU1 +S 2000,2800,2000,6200,300,i5,UP,CALU1 +V 11200,9000,CONT_DIF_P,* +V 8800,9000,CONT_DIF_P,* +V 4500,7000,CONT_DIF_P,* +V 7500,8000,CONT_DIF_P,* +V 1500,900,CONT_DIF_N,* +V 3500,1700,CONT_DIF_N,* +V 5500,900,CONT_DIF_N,* +V 2500,6900,CONT_DIF_P,* +V 3500,8000,CONT_DIF_P,* +V 5600,8000,CONT_DIF_P,* +V 5000,4000,CONT_POLY,* +V 7000,4000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +V 11200,900,CONT_DIF_N,* +V 10000,2400,CONT_DIF_N,* +V 6800,1700,CONT_DIF_N,* +V 12500,2000,CONT_DIF_N,* +V 12500,6000,CONT_DIF_P,* +V 12500,7000,CONT_DIF_P,* +V 6500,9000,CONT_DIF_P,* +V 1300,8000,CONT_DIF_P,* +V 11400,3000,CONT_POLY,* +V 8800,900,CONT_DIF_N,* +V 11000,4000,CONT_POLY,* +V 10000,7000,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 8800,8000,CONT_DIF_P,* +V 8800,7000,CONT_DIF_P,* +V 11200,7000,CONT_DIF_P,* +V 11200,8000,CONT_DIF_P,* +V 10000,6000,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +V 13000,0,CONT_BODY_P,* +V 13000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa2a2a23_x4.vbe b/pdks/symbolic/nsxlib2/cells/noa2a2a23_x4.vbe new file mode 100644 index 000000000..328209403 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT tphl_i5_nq : NATURAL := 496; + CONSTANT tphl_i4_nq : NATURAL := 574; + CONSTANT tphl_i2_nq : NATURAL := 620; + CONSTANT tphl_i3_nq : NATURAL := 716; + CONSTANT tplh_i1_nq : NATURAL := 778; + CONSTANT tplh_i0_nq : NATURAL := 814; + CONSTANT tplh_i4_nq : NATURAL := 819; + CONSTANT tplh_i3_nq : NATURAL := 833; + CONSTANT tphl_i0_nq : NATURAL := 834; + CONSTANT tplh_i5_nq : NATURAL := 865; + CONSTANT tplh_i2_nq : NATURAL := 873; + CONSTANT tphl_i1_nq : NATURAL := 955; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1600 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x1.ap b/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x1.ap new file mode 100644 index 000000000..74e8ed9e9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x1.ap @@ -0,0 +1,198 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x1,P,17/ 8/2024,100 +A 0,0,11100,10000 +R 10000,5000,ref_ref,i0_20 +R 10000,4000,ref_ref,i0_25 +R 9000,5000,ref_ref,i1_25 +R 7000,5000,ref_ref,i2_20 +R 7000,4000,ref_ref,i2_25 +R 6000,5000,ref_ref,i3_20 +R 6000,4000,ref_ref,i3_25 +R 5000,5000,ref_ref,i4_20 +R 5000,4000,ref_ref,i4_25 +R 4000,5000,ref_ref,i5_20 +R 4000,4000,ref_ref,i5_25 +R 10000,7000,ref_ref,i0_35 +R 10000,6000,ref_ref,i0_30 +R 10000,3000,ref_ref,i0_15 +R 9000,6000,ref_ref,i1_30 +R 9000,4000,ref_ref,i1_20 +R 9000,3000,ref_ref,i1_15 +R 7000,6000,ref_ref,i2_30 +R 7000,3000,ref_ref,i2_15 +R 6000,3000,ref_ref,i3_15 +R 6000,6000,ref_ref,i3_30 +R 5000,3000,ref_ref,i4_15 +R 5000,6000,ref_ref,i4_30 +R 4000,3000,ref_ref,i5_15 +R 4000,6000,ref_ref,i5_30 +R 3000,6000,ref_ref,i6_30 +R 3000,5000,ref_ref,i6_25 +R 3000,4000,ref_ref,i6_20 +R 1000,4000,ref_ref,i7_20 +R 1000,5000,ref_ref,i7_25 +R 1000,6000,ref_ref,i7_30 +R 2000,2000,ref_ref,nq_10 +R 2000,3000,ref_ref,nq_15 +R 2000,4000,ref_ref,nq_20 +R 2000,5000,ref_ref,nq_25 +R 2000,6000,ref_ref,nq_30 +R 3000,3000,ref_ref,i6_15 +R 1000,2000,ref_ref,i7_10 +R 1000,3000,ref_ref,i7_15 +S 6900,3200,7300,3200,500,*,RIGHT,POLY +S 5900,3200,6300,3200,500,*,RIGHT,POLY +S 4900,3200,5300,3200,500,*,RIGHT,POLY +S 3900,3200,4300,3200,500,*,RIGHT,POLY +S 4300,2400,4300,3400,200,*,UP,POLY +S 5300,2400,5300,3400,200,*,UP,POLY +S 6300,2400,6300,3400,200,*,UP,POLY +S 7300,2300,7300,3400,200,*,UP,POLY +S 7300,5000,7300,5500,200,*,UP,POLY +S 6300,5000,6300,5500,200,*,UP,POLY +S 5300,5000,5300,5500,200,*,UP,POLY +S 4300,5000,4300,5500,200,*,UP,POLY +S 7000,3100,7000,5000,200,*,UP,POLY +S 6000,3100,6000,5000,200,*,UP,POLY +S 5000,3100,5000,5000,200,*,UP,POLY +S 4000,3100,4000,5000,200,*,UP,POLY +S 6900,5000,7400,5000,200,*,LEFT,POLY +S 5900,5000,6400,5000,200,*,LEFT,POLY +S 4900,5000,5400,5000,200,*,LEFT,POLY +S 3900,5000,4400,5000,200,*,LEFT,POLY +S 10100,2500,10100,5500,200,*,UP,POLY +S 9100,2400,9100,5500,200,*,UP,POLY +S 2500,2500,2500,5500,200,*,UP,POLY +S 1500,2900,1500,5500,200,*,UP,POLY +S 900,4000,1600,4000,500,*,RIGHT,POLY +S 2500,4000,3100,4000,500,*,RIGHT,POLY +S 8800,8000,9800,8000,500,*,RIGHT,ALU1 +S 2000,2000,8800,2000,400,*,RIGHT,ALU1 +S 3000,6900,3000,8200,300,*,UP,ALU1 +S 5800,6800,5800,8100,300,*,UP,ALU1 +S 9000,7000,9000,8000,300,*,UP,ALU1 +S 6800,7000,9000,7000,300,*,RIGHT,ALU1 +S 2800,7000,4800,7000,300,*,RIGHT,ALU1 +S 800,8000,3200,8000,300,*,RIGHT,ALU1 +S 9600,5500,9600,9400,400,*,UP,PDIF +S 9100,700,9100,2500,200,*,UP,NTRANS +S 9600,700,9600,2500,400,*,UP,NDIF +S 10100,700,10100,2500,200,*,UP,NTRANS +S 10600,700,10600,2500,400,*,UP,NDIF +S 10600,1200,10600,2200,300,*,UP,ALU1 +S 10600,7800,10600,8800,300,*,UP,ALU1 +S 9100,5500,9100,9400,200,*,UP,PTRANS +S 10100,5500,10100,9400,200,*,UP,PTRANS +S 10600,5500,10600,9400,400,*,UP,PDIF +S 6800,700,6800,2500,400,*,UP,NDIF +S 7800,700,7800,2500,400,*,UP,NDIF +S 7300,700,7300,2500,200,*,UP,NTRANS +S 6300,700,6300,2500,200,*,UP,NTRANS +S 5300,700,5300,2500,200,*,UP,NTRANS +S 4800,700,4800,2500,600,*,UP,NDIF +S 4300,700,4300,2500,200,*,UP,NTRANS +S 3800,700,3800,2500,400,*,UP,NDIF +S 7700,5500,7700,9400,600,*,UP,PDIF +S 9000,2800,9000,6200,300,*,UP,ALU1 +S 9000,2800,9000,6200,300,i1,UP,CALU1 +S 3700,8000,8000,8000,300,*,RIGHT,ALU1 +S 5800,5500,5800,9400,600,*,UP,PDIF +S 4800,5500,4800,9400,600,*,UP,PDIF +S 6300,5500,6300,9400,200,*,UP,PTRANS +S 6800,5500,6800,9400,400,*,UP,PDIF +S 7300,5500,7300,9400,200,*,UP,PTRANS +S 5300,5500,5300,9400,200,*,UP,PTRANS +S 4300,5500,4300,9400,200,*,UP,PTRANS +S 3800,5500,3800,9400,400,*,UP,PDIF +S 3000,5500,3000,9400,400,*,UP,PDIF +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 2000,5500,2000,9400,600,*,UP,PDIF +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 1000,5500,1000,9400,400,*,UP,PDIF +S 1000,6800,1000,8200,300,*,UP,ALU1 +S 3000,700,3000,2500,400,*,UP,NDIF +S 2500,700,2500,2500,200,*,UP,NTRANS +S 1500,2500,1500,3000,200,*,UP,POLY +S 1500,700,1500,2500,200,*,UP,NTRANS +S 1000,700,1000,2500,400,*,UP,NDIF +S 8600,5500,8600,9400,400,*,UP,PDIF +S 8600,700,8600,2500,400,*,UP,NDIF +S 5800,700,5800,2500,400,*,UP,NDIF +S 2000,700,2000,2500,400,*,UP,NDIF +S -200,0,11200,0,400,*,RIGHT,PTIE +S -200,500,11200,500,1400,vss,RIGHT,CALU1 +S -500,7500,11600,7500,6000,*,RIGHT,NWELL +S -200,10000,11300,10000,400,*,RIGHT,NTIE +S -200,9500,11300,9500,1400,vdd,RIGHT,CALU1 +S 10000,2800,10000,7200,300,*,UP,ALU1 +S 10000,2800,10000,7200,300,i0,UP,CALU1 +S 7000,2800,7000,6200,300,*,UP,ALU1 +S 7000,2800,7000,6200,300,i2,UP,CALU1 +S 6000,2800,6000,6200,300,*,UP,ALU1 +S 6000,2800,6000,6200,300,i3,UP,CALU1 +S 5000,2800,5000,6200,300,*,UP,ALU1 +S 5000,2800,5000,6200,300,i4,UP,CALU1 +S 4000,2800,4000,6200,300,*,UP,ALU1 +S 4000,2800,4000,6200,300,i5,UP,CALU1 +S 2000,1800,2000,7200,300,nq,UP,CALU1 +S 2000,1800,2000,7200,300,*,UP,ALU1 +S 1000,1800,1000,6200,300,i7,UP,CALU1 +S 3000,2800,3000,6200,300,i6,UP,CALU1 +S 1000,1800,1000,6200,300,*,UP,ALU1 +S 3000,2800,3000,6200,300,*,UP,ALU1 +V 10000,3200,CONT_POLY,* +V 9000,3200,CONT_POLY,* +V 7000,3200,CONT_POLY,* +V 6000,3200,CONT_POLY,* +V 5000,3200,CONT_POLY,* +V 4000,3200,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +B 9000,7000,200,200,CONT_TURN1,* +B 9000,8000,200,200,CONT_TURN1,* +V 1000,8000,CONT_DIF_P,* +V 10600,2000,CONT_DIF_N,* +V 9600,8000,CONT_DIF_P,* +V 10600,8000,CONT_DIF_P,* +V 7800,900,CONT_DIF_N,* +V 3800,900,CONT_DIF_N,* +V 6800,7000,CONT_DIF_P,* +V 7800,8000,CONT_DIF_P,* +V 4800,7000,CONT_DIF_P,* +V 3800,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 1000,900,CONT_DIF_N,* +V 8600,2000,CONT_DIF_N,* +V 8600,9100,CONT_DIF_P,* +V 5800,2000,CONT_DIF_N,* +V 5800,7000,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x1.vbe b/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x1.vbe new file mode 100644 index 000000000..ed253ca47 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x1.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rdown_i6_nq : NATURAL := 2850; + CONSTANT rdown_i7_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT rup_i4_nq : NATURAL := 6190; + CONSTANT rup_i5_nq : NATURAL := 6190; + CONSTANT rup_i6_nq : NATURAL := 6190; + CONSTANT rup_i7_nq : NATURAL := 6190; + CONSTANT tphl_i7_nq : NATURAL := 200; + CONSTANT tphl_i6_nq : NATURAL := 270; + CONSTANT tphl_i5_nq : NATURAL := 329; + CONSTANT tphl_i4_nq : NATURAL := 419; + CONSTANT tplh_i6_nq : NATURAL := 535; + CONSTANT tphl_i2_nq : NATURAL := 550; + CONSTANT tplh_i1_nq : NATURAL := 562; + CONSTANT tplh_i7_nq : NATURAL := 591; + CONSTANT tplh_i0_nq : NATURAL := 606; + CONSTANT tplh_i4_nq : NATURAL := 613; + CONSTANT tplh_i3_nq : NATURAL := 616; + CONSTANT tphl_i0_nq : NATURAL := 649; + CONSTANT tplh_i2_nq : NATURAL := 662; + CONSTANT tplh_i5_nq : NATURAL := 662; + CONSTANT tphl_i3_nq : NATURAL := 667; + CONSTANT tphl_i1_nq : NATURAL := 775; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x1" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x4.ap b/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x4.ap new file mode 100644 index 000000000..4d53716fd --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x4.ap @@ -0,0 +1,232 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x4,P,20/12/2024,100 +A 0,0,14000,10000 +R 11000,3000,ref_ref,nq_15 +R 11000,7000,ref_ref,nq_35 +R 11000,6000,ref_ref,nq_30 +R 11000,5000,ref_ref,nq_25 +R 11000,4000,ref_ref,nq_20 +R 10000,6000,ref_ref,i0_30 +R 10000,5000,ref_ref,i0_25 +R 10000,4000,ref_ref,i0_20 +R 10000,3000,ref_ref,i0_15 +R 9000,6000,ref_ref,i1_30 +R 9000,5000,ref_ref,i1_25 +R 9000,3000,ref_ref,i1_15 +R 9000,4000,ref_ref,i1_20 +R 7000,6000,ref_ref,i2_30 +R 7000,3000,ref_ref,i2_15 +R 7000,4000,ref_ref,i2_20 +R 7000,5000,ref_ref,i2_25 +R 6000,6000,ref_ref,i3_30 +R 6000,3000,ref_ref,i3_15 +R 6000,4000,ref_ref,i3_20 +R 6000,5000,ref_ref,i3_25 +R 5000,6000,ref_ref,i4_30 +R 5000,3000,ref_ref,i4_15 +R 5000,4000,ref_ref,i4_20 +R 5000,5000,ref_ref,i4_25 +R 4000,6000,ref_ref,i5_30 +R 4000,4000,ref_ref,i5_20 +R 4000,3000,ref_ref,i5_15 +R 4000,5000,ref_ref,i5_25 +R 2000,6000,ref_ref,i6_30 +R 2000,3000,ref_ref,i6_15 +R 2000,4000,ref_ref,i6_20 +R 2000,5000,ref_ref,i6_25 +R 1000,6000,ref_ref,i7_30 +R 1000,2000,ref_ref,i7_10 +R 1000,3000,ref_ref,i7_15 +R 1000,4000,ref_ref,i7_20 +R 1000,5000,ref_ref,i7_25 +S 12700,3000,13000,3000,498,*,LEFT,POLY +S 13000,3000,13000,5500,200,*,UP,POLY +S 12000,3900,12000,5500,200,*,UP,POLY +S 11000,3900,11000,5500,200,*,DOWN,POLY +S 10000,2500,10000,5500,200,*,UP,POLY +S 9000,2800,9000,5500,200,*,UP,POLY +S 7000,2500,7000,5500,200,*,UP,POLY +S 6000,2400,6000,5500,200,*,UP,POLY +S 5000,2500,5000,5500,200,*,UP,POLY +S 4000,2500,4000,5500,200,*,UP,POLY +S 2000,2500,2000,5500,200,*,UP,POLY +S 1000,2500,1000,5500,200,*,UP,POLY +S 9000,2500,9000,3000,200,*,UP,POLY +S 11000,2500,11000,3900,200,*,UP,POLY +S 12000,2500,12000,3900,200,*,UP,POLY +S 13000,2500,13000,3200,200,*,UP,POLY +S 9400,600,9400,2500,600,*,UP,NDIF +S 1400,7100,2800,7100,300,*,LEFT,ALU1 +S 2400,1700,12600,1700,300,*,RIGHT,ALU1 +S 12600,1700,12600,3200,300,*,UP,ALU1 +S 2500,8000,4600,8000,300,*,RIGHT,ALU1 +S 3500,7000,5400,7000,300,*,RIGHT,ALU1 +S 5400,8000,7600,8000,300,*,RIGHT,ALU1 +S 2700,1700,2700,7100,300,*,UP,ALU1 +S -200,0,14200,0,400,*,RIGHT,PTIE +S -200,500,14200,500,1400,vss,RIGHT,CALU1 +S -500,7500,14500,7500,6000,*,RIGHT,NWELL +S -200,10000,14200,10000,400,*,RIGHT,NTIE +S -200,9500,14200,9500,1400,vdd,RIGHT,CALU1 +S 11900,3900,13600,3900,300,*,RIGHT,ALU1 +S 10900,3900,12100,3900,200,*,RIGHT,POLY +S 13500,1500,13500,2500,400,*,UP,NDIF +S 13500,5500,13500,7500,400,*,UP,PDIF +S 13500,1800,13500,7100,300,*,UP,ALU1 +S 13300,5500,13300,7500,400,*,UP,PDIF +S 13000,5500,13000,7500,200,*,UP,PTRANS +S 13000,600,13000,2500,200,*,UP,NTRANS +S 12600,600,12600,2500,600,*,UP,NDIF +S 12500,5500,12500,9400,400,*,UP,PDIF +S 12500,6900,12500,9400,300,*,UP,ALU1 +S 12000,600,12000,2500,200,*,UP,NTRANS +S 11500,600,11500,2500,400,*,UP,NDIF +S 11000,7000,11600,7000,300,*,RIGHT,ALU1 +S 11500,5900,11500,8100,300,*,DOWN,ALU1 +S 12000,5500,12000,9400,200,*,UP,PTRANS +S 11500,5500,11500,9400,800,*,UP,PDIF +S 11000,2300,11000,7200,300,*,UP,ALU1 +S 11000,2700,11000,7200,300,nq,UP,CALU1 +S 10500,5500,10500,9400,800,*,UP,PDIF +S 11000,5500,11000,9400,200,*,UP,PTRANS +S 10500,7900,10500,9400,300,*,UP,ALU1 +S 11000,600,11000,2500,200,*,UP,NTRANS +S 10600,600,10600,2500,600,*,UP,NDIF +S 10000,2800,10000,6200,300,*,UP,ALU1 +S 10000,2800,10000,6200,300,i0,UP,CALU1 +S 6400,7000,9600,7000,300,*,RIGHT,ALU1 +S 10000,600,10000,2500,200,*,UP,NTRANS +S 10000,5500,10000,9400,200,*,UP,PTRANS +S 9600,5500,9600,9400,600,*,UP,PDIF +S 9500,7000,9500,8100,300,*,UP,ALU1 +S 9000,2800,9000,6200,300,i1,UP,CALU1 +S 9000,2800,9000,6200,300,*,UP,ALU1 +S 9000,600,9000,2500,200,*,UP,NTRANS +S 8600,600,8600,2500,600,*,UP,NDIF +S 9000,5500,9000,9400,200,*,UP,PTRANS +S 8500,7900,8500,9400,300,*,UP,ALU1 +S 8500,5500,8500,9400,600,*,UP,PDIF +S 7500,5500,7500,9400,600,*,UP,PDIF +S 7000,2800,7000,6200,300,i2,UP,CALU1 +S 7000,2800,7000,6200,300,*,UP,ALU1 +S 7000,5500,7000,9400,200,*,UP,PTRANS +S 6500,5500,6500,9400,600,*,UP,PDIF +S 7400,600,7400,2500,600,*,UP,NDIF +S 7000,600,7000,2500,200,*,UP,NTRANS +S 6500,600,6500,2500,600,*,UP,NDIF +S 5500,600,5500,2500,800,*,UP,NDIF +S 6000,2800,6000,6200,300,i3,UP,CALU1 +S 6000,2800,6000,6200,300,*,UP,ALU1 +S 6000,600,6000,2500,200,*,UP,NTRANS +S 6000,5500,6000,9400,200,*,UP,PTRANS +S 5600,5500,5600,9400,600,*,UP,PDIF +S 5500,6900,5500,8100,300,*,UP,ALU1 +S 5000,2800,5000,6200,300,i4,UP,CALU1 +S 5000,2800,5000,6200,300,*,UP,ALU1 +S 5000,600,5000,2500,200,*,UP,NTRANS +S 4500,600,4500,2500,600,*,UP,NDIF +S 5000,5500,5000,9400,200,*,UP,PTRANS +S 4400,5500,4400,9400,600,*,UP,PDIF +S 2500,5500,2500,9400,600,*,UP,PDIF +S 3600,5500,3600,9400,600,*,UP,PDIF +S 4000,5500,4000,9400,200,*,UP,PTRANS +S 3500,600,3500,2500,400,*,UP,NDIF +S 4000,600,4000,2500,200,*,UP,NTRANS +S 4600,600,4600,2500,400,*,UP,NDIF +S 4000,2800,4000,6200,300,i5,UP,CALU1 +S 4000,2800,4000,6200,300,*,UP,ALU1 +S 2000,2800,2000,6200,300,i6,UP,CALU1 +S 2000,2800,2000,6200,300,*,UP,ALU1 +S 1500,600,1500,2500,600,*,UP,NDIF +S 2000,600,2000,2500,200,*,UP,NTRANS +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 1600,5500,1600,9400,600,*,UP,PDIF +S 500,600,500,2500,400,*,UP,NDIF +S 1000,600,1000,2500,200,*,UP,NTRANS +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 500,5500,500,9400,400,*,UP,PDIF +S 500,6900,500,8000,300,*,UP,ALU1 +S 500,8000,2600,8000,300,*,RIGHT,ALU1 +S 2600,600,2600,2500,600,*,UP,NDIF +S 1000,1800,1000,6200,300,*,UP,ALU1 +S 1000,1800,1000,6200,300,i7,UP,CALU1 +V 7000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +B 11150,2700,900,1000,CONT_TURN1,* +V 1500,7100,CONT_DIF_P,* +B 12600,1700,200,200,CONT_TURN1,* +V 12700,3000,CONT_POLY,* +V 2700,1800,CONT_DIF_N,* +V 5500,1800,CONT_DIF_N,* +V 8500,1800,CONT_DIF_N,* +B 11250,2450,700,300,CONT_TURN1,* +V 11500,2400,CONT_DIF_N,* +B 11300,6500,1000,1600,CONT_TURN1,* +V 3500,7000,CONT_DIF_P,* +V 4500,8000,CONT_DIF_P,* +B 2700,7100,200,200,CONT_TURN1,* +V 12000,3900,CONT_POLY,* +V 13500,2000,CONT_DIF_N,* +V 13500,7000,CONT_DIF_P,* +V 13500,5800,CONT_DIF_P,* +V 12500,900,CONT_DIF_N,* +V 12500,9200,CONT_DIF_P,* +V 12500,8000,CONT_DIF_P,* +V 12500,7000,CONT_DIF_P,* +V 11500,8000,CONT_DIF_P,* +V 11500,7000,CONT_DIF_P,* +V 11500,6000,CONT_DIF_P,* +V 10500,9200,CONT_DIF_P,* +V 10500,8000,CONT_DIF_P,* +V 10500,900,CONT_DIF_N,* +B 9500,7000,200,200,CONT_TURN1,* +V 10000,4000,CONT_POLY,* +V 9500,8000,CONT_DIF_P,* +V 9000,4000,CONT_POLY,* +V 8500,9200,CONT_DIF_P,* +V 8500,8000,CONT_DIF_P,* +V 7500,8000,CONT_DIF_P,* +V 6500,7000,CONT_DIF_P,* +V 7500,900,CONT_DIF_N,* +V 5500,7000,CONT_DIF_P,* +V 5500,8000,CONT_DIF_P,* +V 3500,900,CONT_DIF_N,* +V 2500,8000,CONT_DIF_P,* +V 500,7000,CONT_DIF_P,* +V 500,900,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +V 13000,0,CONT_BODY_P,* +V 13000,10000,CONT_BODY_N,* +V 14000,0,CONT_BODY_P,* +V 14000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x4.vbe b/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x4.vbe new file mode 100644 index 000000000..2499cd710 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2a2a2a24_x4.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4250; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rdown_i7_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT rup_i7_nq : NATURAL := 890; + CONSTANT tphl_i7_nq : NATURAL := 525; + CONSTANT tphl_i6_nq : NATURAL := 606; + CONSTANT tphl_i5_nq : NATURAL := 649; + CONSTANT tphl_i4_nq : NATURAL := 748; + CONSTANT tphl_i2_nq : NATURAL := 867; + CONSTANT tphl_i0_nq : NATURAL := 966; + CONSTANT tphl_i3_nq : NATURAL := 990; + CONSTANT tplh_i6_nq : NATURAL := 999; + CONSTANT tplh_i1_nq : NATURAL := 1005; + CONSTANT tplh_i0_nq : NATURAL := 1049; + CONSTANT tplh_i7_nq : NATURAL := 1052; + CONSTANT tplh_i3_nq : NATURAL := 1061; + CONSTANT tplh_i4_nq : NATURAL := 1061; + CONSTANT tphl_i1_nq : NATURAL := 1097; + CONSTANT tplh_i2_nq : NATURAL := 1106; + CONSTANT tplh_i5_nq : NATURAL := 1109; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x4" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1700 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa2ao222_x1.ap b/pdks/symbolic/nsxlib2/cells/noa2ao222_x1.ap new file mode 100644 index 000000000..45c75a9ba --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2ao222_x1.ap @@ -0,0 +1,119 @@ +V ALLIANCE : 6 +H noa2ao222_x1,P,14/ 8/2024,100 +A 0,0,7000,10000 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 3000,5000,ref_ref,i4_25 +R 3000,4000,ref_ref,i4_20 +R 4000,6000,ref_ref,nq_30 +R 4000,5000,ref_ref,nq_25 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +R 5000,5000,ref_ref,i2_25 +R 5000,6000,ref_ref,i2_30 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 3000,7000,ref_ref,i4_35 +R 3000,6000,ref_ref,i4_30 +R 6000,7000,ref_ref,i3_35 +R 6000,6000,ref_ref,i3_30 +R 6000,5000,ref_ref,i3_25 +R 6000,4000,ref_ref,i3_20 +R 6000,3000,ref_ref,i3_15 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 1000,7000,ref_ref,i0_35 +R 2000,7000,ref_ref,i1_35 +R 4000,3000,ref_ref,nq_15 +R 4000,4000,ref_ref,nq_20 +S 1000,3500,1000,4100,200,*,UP,POLY +S 1000,3900,1000,5500,200,*,UP,POLY +S 4500,3500,4500,5500,200,*,UP,POLY +S 5500,3500,5500,5500,200,*,UP,POLY +S 500,700,500,2200,300,*,UP,ALU1 +S 3000,1800,3000,3100,300,*,UP,ALU1 +S 2900,3000,4100,3000,300,*,RIGHT,ALU1 +S 5000,1200,5000,1300,300,*,UP,ALU1 +S 2900,4000,3500,4000,500,*,LEFT,POLY +S 5500,4000,6000,4000,500,*,RIGHT,POLY +S 4400,4000,5100,4000,500,*,RIGHT,POLY +S 2000,4000,2600,4000,500,*,RIGHT,POLY +S 3500,3500,3500,5500,200,*,UP,POLY +S 2500,5100,2500,5500,200,*,UP,POLY +S 2500,3500,2500,5100,200,*,UP,POLY +S 1700,900,1700,3500,1000,*,UP,NDIF +S 2900,900,2900,3500,600,*,UP,NDIF +S 4000,900,4000,3500,400,*,UP,NDIF +S 6000,900,6000,3500,400,*,UP,NDIF +S 5500,900,5500,3500,200,*,UP,NTRANS +S 4500,900,4500,3500,200,*,UP,NTRANS +S 3500,900,3500,3500,200,*,UP,NTRANS +S 2500,900,2500,3500,200,*,UP,NTRANS +S 1000,900,1000,3500,200,*,UP,NTRANS +S 500,900,500,3500,400,*,UP,NDIF +S 500,5500,500,9400,400,*,UP,PDIF +S 4000,5500,4000,9400,400,*,UP,PDIF +S 6000,5500,6000,9400,400,*,UP,PDIF +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 4500,5500,4500,9400,200,*,UP,PTRANS +S -500,7500,7500,7500,6000,*,RIGHT,NWELL +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 1800,5500,1800,9400,1000,*,UP,PDIF +S 5000,5500,5000,9400,600,*,UP,PDIF +S 5000,900,5000,3500,600,*,UP,NDIF +S 3800,2000,6200,2000,300,*,RIGHT,ALU1 +S 400,8000,6200,8000,300,*,RIGHT,ALU1 +S 3000,3800,3000,7200,300,i4,UP,CALU1 +S 5000,2800,5000,7200,300,i2,UP,CALU1 +S 5000,2800,5000,7200,300,*,UP,ALU1 +S 4000,2800,4000,7200,300,*,UP,ALU1 +S 4000,2800,4000,7200,300,nq,UP,CALU1 +S 3000,5500,3000,9400,400,*,UP,PDIF +S 1000,5500,1000,9400,200,*,UP,PTRANS +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S -200,10000,7200,10000,400,*,RIGHT,NTIE +S -200,0,7200,0,400,*,RIGHT,PTIE +S 2000,2800,2000,7200,300,*,UP,ALU1 +S 3000,3800,3000,7200,300,*,UP,ALU1 +S 6000,2800,6000,7200,300,*,UP,ALU1 +S 6000,2800,6000,7200,300,i3,UP,CALU1 +S 2000,2800,2000,7200,300,i1,UP,CALU1 +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 1000,2800,1000,7200,300,i0,UP,CALU1 +B 3000,3000,200,200,CONT_TURN1,* +V 1700,9100,CONT_DIF_P,* +V 5000,1200,CONT_DIF_N,* +V 3100,4000,CONT_POLY,* +V 4900,4000,CONT_POLY,* +V 3000,2000,CONT_DIF_N,* +V 500,2000,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 6000,2000,CONT_DIF_N,* +V 4000,7000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa2ao222_x1.vbe b/pdks/symbolic/nsxlib2/cells/noa2ao222_x1.vbe new file mode 100644 index 000000000..034393fea --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2ao222_x1.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3210; + CONSTANT rdown_i1_nq : NATURAL := 3210; + CONSTANT rdown_i2_nq : NATURAL := 3210; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 5260; + CONSTANT rup_i1_nq : NATURAL := 5260; + CONSTANT rup_i2_nq : NATURAL := 5260; + CONSTANT rup_i3_nq : NATURAL := 5260; + CONSTANT rup_i4_nq : NATURAL := 3750; + CONSTANT tphl_i2_nq : NATURAL := 186; + CONSTANT tphl_i4_nq : NATURAL := 240; + CONSTANT tphl_i3_nq : NATURAL := 256; + CONSTANT tplh_i4_nq : NATURAL := 309; + CONSTANT tphl_i0_nq : NATURAL := 348; + CONSTANT tplh_i1_nq : NATURAL := 378; + CONSTANT tplh_i0_nq : NATURAL := 422; + CONSTANT tphl_i1_nq : NATURAL := 440; + CONSTANT tplh_i3_nq : NATURAL := 459; + CONSTANT tplh_i2_nq : NATURAL := 473; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x1; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa2ao222_x4.ap b/pdks/symbolic/nsxlib2/cells/noa2ao222_x4.ap new file mode 100644 index 000000000..e8f71c368 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2ao222_x4.ap @@ -0,0 +1,197 @@ +V ALLIANCE : 6 +H noa2ao222_x4,P,17/ 8/2024,100 +A 0,0,12000,10000 +R 2000,5000,ref_ref,i1_35 +R 2000,7000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,7000,ref_ref,i0_35 +R 10000,8000,ref_ref,nq_40 +R 5000,5000,ref_ref,i2_25 +R 5000,4000,ref_ref,i2_20 +R 5000,3000,ref_ref,i2_15 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 3000,7000,ref_ref,i4_35 +R 5000,6000,ref_ref,i2_30 +R 6000,4000,ref_ref,i3_20 +R 6000,5000,ref_ref,i3_25 +R 6000,6000,ref_ref,i3_30 +R 10000,3000,ref_ref,nq_15 +R 10000,7000,ref_ref,nq_35 +R 10000,2000,ref_ref,nq_10 +R 10000,6000,ref_ref,nq_30 +R 10000,5000,ref_ref,nq_25 +R 10000,4000,ref_ref,nq_20 +R 3000,6000,ref_ref,i4_30 +R 3000,5000,ref_ref,i4_25 +R 3000,4000,ref_ref,i4_20 +S 6500,2300,6500,3300,300,*,UP,ALU1 +S 6500,2100,6500,3500,400,*,UP,NDIF +S 6000,3500,6000,4100,200,*,UP,POLY +S 6000,2100,6000,3500,200,*,UP,NTRANS +S 11100,5500,11100,9400,600,*,UP,PDIF +S 11100,1500,11100,3500,600,*,UP,NDIF +S 400,8000,6600,8000,300,*,RIGHT,ALU1 +S 4400,5500,4400,9400,1000,*,UP,PDIF +S 5400,1400,5400,3500,600,*,UP,NDIF +S 5600,5500,5600,9400,600,*,UP,PDIF +S 5000,5500,5000,9400,200,*,UP,PTRANS +S 6000,5500,6000,9400,200,*,UP,PTRANS +S 6500,5500,6500,9400,600,*,UP,PDIF +S 6000,3900,6000,5600,200,*,UP,POLY +S 5000,4000,5000,5500,200,*,UP,POLY +S 5100,1700,5100,3500,400,*,UP,NDIF +S 2500,1700,2500,3500,600,*,UP,NDIF +S 4700,1700,4700,3500,200,*,UP,NTRANS +S 3900,1700,3900,3500,1000,*,UP,NDIF +S 3100,1700,3100,3500,200,*,UP,NTRANS +S 8700,4000,10600,4000,400,*,RIGHT,POLY +S 10500,3500,10500,5500,200,*,UP,POLY +S 9500,3900,9500,5500,200,*,UP,POLY +S 1000,3400,1000,4800,200,*,UP,POLY +S 3100,3500,3100,4100,200,*,UP,POLY +S 4700,3500,4700,4200,200,*,UP,POLY +S 9500,3500,9500,4000,200,*,UP,POLY +S 8200,3400,8200,5500,200,*,UP,POLY +S 2900,3000,4100,3000,300,*,RIGHT,ALU1 +S 4000,2900,4000,7000,300,*,UP,ALU1 +S 11000,900,11000,3100,300,*,UP,ALU1 +S 9000,900,9000,3100,300,*,UP,ALU1 +S 5400,1200,5400,1700,500,*,UP,ALU1 +S 3400,5500,3400,9400,400,*,DOWN,PDIF +S 9000,7900,9000,9600,300,*,UP,ALU1 +S 7700,2900,7700,6100,300,*,UP,ALU1 +S 8600,4900,8600,7000,300,*,UP,ALU1 +S 4000,7000,8600,7000,300,*,RIGHT,ALU1 +S 11000,5900,11000,9600,300,*,UP,ALU1 +S 7600,4000,8900,4000,300,*,RIGHT,ALU1 +S 3800,2300,6600,2300,300,*,RIGHT,ALU1 +S 500,800,500,2100,300,*,UP,ALU1 +S 2900,2300,2900,3000,300,*,UP,ALU1 +S 500,5500,500,8400,400,*,UP,PDIF +S 9000,1500,9000,3500,400,*,UP,NDIF +S 8200,5000,8700,5000,500,*,RIGHT,POLY +S 7700,2500,7700,3500,400,*,UP,NDIF +S 4700,4000,5200,4000,500,*,RIGHT,POLY +S 1800,5100,2600,5100,200,*,RIGHT,POLY +S 2500,5100,2500,5500,200,*,UP,POLY +S 2500,5500,2500,8400,200,*,UP,PTRANS +S 2400,1700,2400,3500,600,*,UP,NDIF +S 1400,1700,1400,3500,400,*,UP,NDIF +S 5700,2100,5700,3500,400,*,UP,NDIF +S 8700,2500,8700,3500,400,*,UP,NDIF +S 10000,1500,10000,3500,600,*,UP,NDIF +S 10500,1500,10500,3500,200,*,UP,NTRANS +S 9000,5500,9000,9400,400,*,UP,PDIF +S 10500,5500,10500,9400,200,*,UP,PTRANS +S 9500,5500,9500,9400,200,*,UP,PTRANS +S 9500,1500,9500,3500,200,*,UP,NTRANS +S 8600,5500,8600,7500,400,*,UP,PDIF +S 7700,5500,7700,7500,400,*,UP,PDIF +S 3200,5500,3200,8400,400,*,UP,PDIF +S 2200,5500,2200,8400,400,*,UP,PDIF +S 1400,5500,1400,8400,400,*,UP,PDIF +S 3700,4100,3700,5100,200,*,UP,POLY +S 3000,4100,3800,4100,200,*,LEFT,POLY +S 1900,3800,1900,5100,200,*,UP,POLY +S 1000,1700,1000,3500,200,*,UP,NTRANS +S 500,1700,500,3500,400,*,UP,NDIF +S 6000,3800,6000,6200,300,*,UP,ALU1 +S 1800,5500,1800,9400,600,*,UP,PDIF +S 3700,5500,3700,9400,200,*,UP,PTRANS +S 1000,5500,1000,8400,200,*,UP,PTRANS +S 1900,1700,1900,3500,200,*,UP,NTRANS +S 3700,5000,3700,5500,200,*,UP,POLY +S -500,7500,12500,7500,6000,*,RIGHT,NWELL +S -200,10000,12200,10000,400,*,RIGHT,NTIE +S -200,0,12200,0,400,*,RIGHT,PTIE +S 5000,2800,5000,6200,300,*,UP,ALU1 +S 3000,5500,3000,8400,400,*,UP,PDIF +S 2000,2800,2000,7200,300,*,UP,ALU1 +S 3000,3800,3000,7200,300,*,UP,ALU1 +S 1900,3500,1900,4100,200,*,UP,POLY +S 10000,1800,10000,8200,300,*,UP,ALU1 +S 8200,2500,8200,3500,200,*,UP,NTRANS +S 10000,5500,10000,9400,600,*,UP,PDIF +S 8200,5500,8200,7500,200,*,UP,PTRANS +S -200,500,12200,500,1400,vss,RIGHT,CALU1 +S -200,9500,12200,9500,1400,vdd,RIGHT,CALU1 +S 1000,4600,1000,5500,200,*,DOWN,POLY +S 10000,1800,10000,8200,300,nq,UP,CALU1 +S 6000,3800,6000,6200,300,i3,UP,CALU1 +S 5000,2800,5000,6200,300,i2,UP,CALU1 +S 3000,3800,3000,7200,300,i4,UP,CALU1 +S 2000,2800,2000,7200,300,i1,UP,CALU1 +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 1000,2800,1000,7200,300,i0,UP,CALU1 +B 6500,2300,200,200,CONT_TURN1,* +V 6500,3000,CONT_DIF_N,* +V 9000,9000,CONT_DIF_P,* +V 11000,9000,CONT_DIF_P,* +V 6500,8000,CONT_DIF_P,* +V 2600,2300,CONT_DIF_N,* +B 4150,7000,500,400,CONT_TURN1,* +B 2900,2250,200,300,CONT_TURN1,* +B 8600,7000,200,200,CONT_TURN1,* +B 4000,3000,200,200,CONT_TURN1,* +B 2900,3000,200,200,CONT_TURN1,* +V 7700,6000,CONT_DIF_P,* +V 7700,3000,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 5400,1600,CONT_DIF_N,* +V 3900,2300,CONT_DIF_N,* +V 1800,9100,CONT_DIF_P,* +V 8800,4000,CONT_POLY,* +V 10000,6000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 10000,3000,CONT_DIF_N,* +V 10000,2000,CONT_DIF_N,* +V 8600,5000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 3000,8000,CONT_DIF_P,* +V 4200,7000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 11000,6000,CONT_DIF_P,* +V 11000,7000,CONT_DIF_P,* +V 11000,8000,CONT_DIF_P,* +V 11000,3000,CONT_DIF_N,* +V 11000,2000,CONT_DIF_N,* +V 9000,3000,CONT_DIF_N,* +V 9000,2000,CONT_DIF_N,* +V 5000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa2ao222_x4.vbe b/pdks/symbolic/nsxlib2/cells/noa2ao222_x4.vbe new file mode 100644 index 000000000..89b9f12c5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 638; + CONSTANT tplh_i4_nq : NATURAL := 664; + CONSTANT tphl_i0_nq : NATURAL := 684; + CONSTANT tphl_i4_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 732; + CONSTANT tplh_i1_nq : NATURAL := 758; + CONSTANT tphl_i1_nq : NATURAL := 780; + CONSTANT tplh_i3_nq : NATURAL := 795; + CONSTANT tplh_i0_nq : NATURAL := 801; + CONSTANT tplh_i2_nq : NATURAL := 809; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa3ao322_x1.ap b/pdks/symbolic/nsxlib2/cells/noa3ao322_x1.ap new file mode 100644 index 000000000..badebeec9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa3ao322_x1.ap @@ -0,0 +1,151 @@ +V ALLIANCE : 6 +H noa3ao322_x1,P,17/ 8/2024,100 +A 0,0,9000,10000 +R 6000,3000,ref_ref,i3_15 +R 5000,6000,ref_ref,nq_30 +R 5000,5000,ref_ref,nq_25 +R 6000,4000,ref_ref,i3_20 +R 6000,5000,ref_ref,i3_25 +R 6000,6000,ref_ref,i3_30 +R 7000,3000,ref_ref,i4_15 +R 7000,4000,ref_ref,i4_20 +R 7000,5000,ref_ref,i4_25 +R 7000,6000,ref_ref,i4_30 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 8000,7000,ref_ref,i5_35 +R 8000,6000,ref_ref,i5_30 +R 8000,3000,ref_ref,i5_15 +R 8000,4000,ref_ref,i5_20 +R 8000,5000,ref_ref,i5_25 +R 7000,7000,ref_ref,i4_35 +R 5000,4000,ref_ref,nq_20 +R 5000,3000,ref_ref,nq_15 +R 4000,6000,ref_ref,i6_30 +R 4000,5000,ref_ref,i6_25 +R 4000,4000,ref_ref,i6_20 +R 3000,7000,ref_ref,i2_35 +R 3000,6000,ref_ref,i2_30 +R 3000,5000,ref_ref,i2_25 +R 3000,4000,ref_ref,i2_20 +R 3000,3000,ref_ref,i2_15 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_10 +S 4900,5500,4900,9400,1200,*,UP,PDIF +S 4900,1100,4900,3500,1200,*,UP,NDIF +S 2600,1100,2600,3500,600,*,UP,NDIF +S 6500,5500,6500,9400,600,*,DOWN,PDIF +S 1300,8000,8600,8000,300,*,RIGHT,ALU1 +S 4000,5500,4000,9400,200,*,UP,PTRANS +S 3500,5500,3500,9400,600,*,UP,PDIF +S 4000,3500,4000,5500,200,*,UP,POLY +S 3600,3000,5000,3000,300,*,RIGHT,ALU1 +S 4000,1100,4000,3500,200,*,UP,NTRANS +S 3500,1100,3500,3500,400,*,UP,NDIF +S 3600,1700,3600,3000,300,*,UP,ALU1 +S 3000,3500,3000,5600,200,i2,UP,POLY +S 3000,1100,3000,3500,200,*,UP,NTRANS +S 2500,5500,2500,9400,400,*,UP,PDIF +S 2500,5500,2500,9400,600,*,UP,PDIF +S 3000,5500,3000,9400,200,*,UP,PTRANS +S 2000,3500,2000,5600,200,i1,UP,POLY +S 1500,1100,1500,3500,600,*,UP,NDIF +S 2000,1100,2000,3500,200,*,UP,NTRANS +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 1500,5500,1500,9400,600,*,UP,PDIF +S 1000,1100,1000,3500,200,*,UP,NTRANS +S 500,1100,500,3500,400,*,UP,NDIF +S 500,1200,500,1900,300,*,UP,ALU1 +S 1000,3500,1000,5500,200,i0,UP,POLY +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 400,5500,400,9400,600,*,UP,PDIF +S 500,7800,500,8800,300,*,UP,ALU1 +S 5600,5500,5600,9400,600,*,UP,PDIF +S 6000,3500,6000,5600,200,*,UP,POLY +S 6000,5500,6000,9400,200,*,UP,PTRANS +S 6000,1100,6000,3500,200,*,UP,NTRANS +S 6500,1100,6500,3500,400,*,UP,NDIF +S 6500,1100,6500,1500,500,*,DOWN,ALU1 +S 7000,3500,7000,5600,200,i4,UP,POLY +S 7000,1100,7000,3500,200,*,UP,NTRANS +S 7600,1100,7600,3500,600,*,UP,NDIF +S 8000,3400,8000,5500,200,i5,UP,POLY +S 8000,1100,8000,3500,200,*,UP,NTRANS +S 8500,1100,8500,3500,600,*,UP,NDIF +S 8500,1200,8500,2200,400,*,UP,ALU1 +S 7500,5500,7500,9400,800,*,UP,PDIF +S 7000,5500,7000,9400,200,*,UP,PTRANS +S 8000,5500,8000,9400,200,*,UP,PTRANS +S 8600,5500,8600,9400,600,*,UP,PDIF +S 4700,2000,7400,2000,300,*,RIGHT,ALU1 +S 4000,3800,4000,6200,300,*,UP,ALU1 +S 4000,3800,4000,6200,300,i6,UP,CALU1 +S 6400,1100,6400,3500,400,*,UP,NDIF +S 5700,1100,5700,3500,400,*,UP,NDIF +S 6000,2800,6000,7200,300,i3,UP,CALU1 +S 6000,2800,6000,7200,300,*,UP,ALU1 +S -500,7500,9500,7500,6000,*,RIGHT,NWELL +S 5000,2800,5000,7200,300,nq,UP,CALU1 +S 1000,2800,1000,7200,300,i0,UP,CALU1 +S 7000,2800,7000,7200,300,*,UP,ALU1 +S 2000,1800,2000,7200,300,*,UP,ALU1 +S 3000,2800,3000,7200,300,*,UP,ALU1 +S -200,10000,9200,10000,400,*,RIGHT,NTIE +S -200,0,9200,0,400,*,RIGHT,PTIE +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 8000,2800,8000,7200,300,*,UP,ALU1 +S -200,500,9200,500,1400,vss,RIGHT,CALU1 +S -200,9500,9200,9500,1400,vdd,RIGHT,CALU1 +S 8000,2800,8000,7200,300,i5,UP,CALU1 +S 7000,2800,7000,7200,300,i4,UP,CALU1 +S 5000,2800,5000,7200,300,*,UP,ALU1 +S 3000,2800,3000,7200,300,i2,UP,CALU1 +S 2000,1800,2000,7200,300,i1,UP,CALU1 +V 3500,8000,CONT_DIF_P,* +B 3600,3000,200,200,CONT_TURN1,* +V 3500,1900,CONT_DIF_N,* +V 2500,9000,CONT_DIF_P,* +V 1500,8000,CONT_DIF_P,* +V 500,1900,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 6500,1300,CONT_DIF_N,* +V 7500,2000,CONT_DIF_N,* +V 8500,2000,CONT_DIF_N,* +V 8500,8000,CONT_DIF_P,* +V 7000,4000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa3ao322_x1.vbe b/pdks/symbolic/nsxlib2/cells/noa3ao322_x1.vbe new file mode 100644 index 000000000..ff0227769 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa3ao322_x1.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3370; + CONSTANT rdown_i1_nq : NATURAL := 3370; + CONSTANT rdown_i2_nq : NATURAL := 3370; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rdown_i5_nq : NATURAL := 3210; + CONSTANT rdown_i6_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 6700; + CONSTANT rup_i1_nq : NATURAL := 6700; + CONSTANT rup_i2_nq : NATURAL := 6700; + CONSTANT rup_i3_nq : NATURAL := 6700; + CONSTANT rup_i4_nq : NATURAL := 6700; + CONSTANT rup_i5_nq : NATURAL := 6700; + CONSTANT rup_i6_nq : NATURAL := 3690; + CONSTANT tphl_i3_nq : NATURAL := 196; + CONSTANT tphl_i6_nq : NATURAL := 246; + CONSTANT tphl_i4_nq : NATURAL := 264; + CONSTANT tplh_i6_nq : NATURAL := 311; + CONSTANT tphl_i5_nq : NATURAL := 328; + CONSTANT tphl_i0_nq : NATURAL := 396; + CONSTANT tphl_i1_nq : NATURAL := 486; + CONSTANT tplh_i2_nq : NATURAL := 488; + CONSTANT tphl_i2_nq : NATURAL := 546; + CONSTANT tplh_i1_nq : NATURAL := 552; + CONSTANT tplh_i5_nq : NATURAL := 581; + CONSTANT tplh_i3_nq : NATURAL := 599; + CONSTANT tplh_i4_nq : NATURAL := 608; + CONSTANT tplh_i0_nq : NATURAL := 616; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x1; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/noa3ao322_x4.ap b/pdks/symbolic/nsxlib2/cells/noa3ao322_x4.ap new file mode 100644 index 000000000..076fe20a2 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa3ao322_x4.ap @@ -0,0 +1,217 @@ +V ALLIANCE : 6 +H noa3ao322_x4,P,17/ 8/2024,100 +A 0,0,13000,10000 +R 3000,5000,ref_ref,nq_35 +R 3000,7000,ref_ref,nq_25 +R 7000,6000,ref_ref,i2_30 +R 7000,5000,ref_ref,i2_25 +R 10000,5000,ref_ref,i3_25 +R 10000,4000,ref_ref,i3_20 +R 10000,3000,ref_ref,i3_15 +R 5000,7000,ref_ref,i0_35 +R 3000,8000,ref_ref,nq_40 +R 3000,2000,ref_ref,nq_10 +R 3000,3000,ref_ref,nq_15 +R 3000,4000,ref_ref,nq_20 +R 3000,6000,ref_ref,nq_30 +R 11000,6000,ref_ref,i4_30 +R 11000,7000,ref_ref,i4_35 +R 12000,3000,ref_ref,i5_15 +R 12000,4000,ref_ref,i5_20 +R 6000,4000,ref_ref,i1_20 +R 6000,3000,ref_ref,i1_15 +R 7000,4000,ref_ref,i2_20 +R 7000,7000,ref_ref,i2_35 +R 6000,5000,ref_ref,i1_25 +R 6000,6000,ref_ref,i1_30 +R 6000,7000,ref_ref,i1_35 +R 11000,4000,ref_ref,i4_20 +R 11000,3000,ref_ref,i4_15 +R 10000,6000,ref_ref,i3_30 +R 5000,6000,ref_ref,i0_30 +R 5000,5000,ref_ref,i0_25 +R 5000,4000,ref_ref,i0_20 +R 5000,3000,ref_ref,i0_15 +R 12000,7000,ref_ref,i5_35 +R 12000,6000,ref_ref,i5_30 +R 12000,5000,ref_ref,i5_25 +R 10000,7000,ref_ref,i3_35 +R 11000,5000,ref_ref,i4_25 +R 8000,4000,ref_ref,i6_20 +R 8000,5000,ref_ref,i6_25 +R 8000,6000,ref_ref,i6_30 +R 8000,7000,ref_ref,i6_35 +S 7300,1700,7300,3300,400,*,DOWN,NDIF +S 7000,3300,7000,4100,200,*,UP,POLY +S 7000,1700,7000,3300,200,*,UP,NTRANS +S 5400,7700,12500,7700,300,*,RIGHT,ALU1 +S 9000,5500,9000,8500,1400,*,UP,PDIF +S 4300,6300,4300,8500,800,*,UP,PDIF +S 5600,1700,5600,3300,600,*,UP,NDIF +S 6600,5500,6600,8500,400,*,UP,PDIF +S 6500,6300,6500,8900,400,*,UP,PDIF +S 7500,1900,7500,3000,300,*,UP,ALU1 +S 4000,2000,7700,2000,300,*,RIGHT,ALU1 +S 5000,1700,5000,3300,200,*,UP,NTRANS +S 5000,3300,5000,4100,200,*,UP,POLY +S 5000,3900,5000,6300,200,*,UP,POLY +S 5000,6300,5000,8500,200,*,UP,PTRANS +S 9100,1700,9100,2900,1200,*,UP,NDIF +S 8000,2500,8000,5600,200,i6,UP,POLY +S 8000,1700,8000,2900,200,*,UP,NTRANS +S 7600,5500,7600,8500,600,*,UP,PDIF +S 8000,5500,8000,8500,200,*,UP,PTRANS +S 7000,3900,7000,5800,200,i2,UP,POLY +S 7000,5500,7000,8500,200,*,UP,PTRANS +S 6500,8200,6500,8800,500,*,DOWN,ALU1 +S 7600,3000,9100,3000,300,*,RIGHT,ALU1 +S 9000,3000,9000,7200,300,*,UP,ALU1 +S 10500,5500,10500,8500,800,*,UP,PDIF +S 10000,2600,10000,5500,200,*,UP,POLY +S 10500,800,10500,2900,400,*,UP,NDIF +S 10000,1700,10000,2900,200,*,UP,NTRANS +S 10000,5500,10000,8500,200,*,UP,PTRANS +S 8600,2000,11600,2000,300,*,RIGHT,ALU1 +S 11000,2800,11000,5600,200,i4,UP,POLY +S 11500,5500,11500,8500,600,*,UP,PDIF +S 11000,5500,11000,8500,200,*,UP,PTRANS +S 11000,1700,11000,2900,200,*,UP,NTRANS +S 11500,1700,11500,2900,400,*,UP,NDIF +S 12000,2900,12000,5600,200,i5,UP,POLY +S 12000,1700,12000,2900,200,*,UP,NTRANS +S 12500,1700,12500,2900,400,*,UP,NDIF +S 12500,400,12500,2100,300,*,UP,ALU1 +S 12000,5500,12000,8500,200,*,UP,PTRANS +S 12500,5500,12500,8500,400,*,UP,PDIF +S 1200,2900,1200,5500,200,*,UP,POLY +S 2400,5100,2400,5500,200,*,UP,POLY +S 6000,4000,6000,6400,200,*,UP,POLY +S 10300,1700,10300,2900,400,*,UP,NDIF +S 9700,1700,9700,2900,400,*,UP,NDIF +S 6000,3300,6000,4100,200,*,UP,POLY +S 4200,7900,4200,8800,400,*,UP,ALU1 +S 4000,2000,4000,4200,300,*,UP,ALU1 +S 600,4900,2100,4900,300,*,RIGHT,ALU1 +S 600,3400,2100,3400,300,*,RIGHT,ALU1 +S 700,2300,700,7100,300,*,UP,ALU1 +S 2000,1000,2000,2500,300,*,UP,ALU1 +S 7500,1700,7500,2900,800,*,UP,NDIF +S 6000,1700,6000,3300,200,*,UP,NTRANS +S 4400,900,4400,3300,600,*,UP,NDIF +S 3600,2800,3600,3200,200,*,UP,POLY +S 2500,2800,2500,3200,200,*,UP,POLY +S 1900,3200,3700,3200,200,*,RIGHT,POLY +S 2500,900,2500,2900,200,*,UP,NTRANS +S 5400,6300,5400,8500,600,*,UP,PDIF +S 6500,6300,6500,8500,800,*,UP,PDIF +S 1900,5500,1900,9400,400,*,UP,PDIF +S 1900,5800,1900,9200,300,*,UP,ALU1 +S 1700,5500,1700,7900,400,*,UP,PDIF +S 4100,5500,4100,9400,600,*,UP,PDIF +S 6500,1700,6500,3300,400,*,UP,NDIF +S 4800,1700,4800,3300,200,*,UP,NDIF +S 1600,1500,1600,2900,400,*,UP,NDIF +S 1800,5100,3700,5100,200,*,RIGHT,POLY +S 3600,5100,3600,5500,200,*,UP,POLY +S 6000,6300,6000,8500,200,*,UP,PTRANS +S 2400,5500,2400,9400,200,*,UP,PTRANS +S 3600,5500,3600,9400,200,*,UP,PTRANS +S 3000,5500,3000,9400,600,*,UP,PDIF +S 3600,900,3600,2900,200,*,UP,NTRANS +S 3000,900,3000,2900,600,*,UP,NDIF +S 1100,4200,4100,4200,200,*,RIGHT,POLY +S 7000,3800,7000,7200,300,*,UP,ALU1 +S 700,5500,700,7900,400,*,UP,PDIF +S 8500,1700,8500,2900,400,*,UP,NDIF +S 2000,900,2000,2900,600,*,UP,NDIF +S 1200,1500,1200,2900,200,*,UP,NTRANS +S 700,1500,700,2900,400,*,UP,NDIF +S 1200,5500,1200,7900,200,*,UP,PTRANS +S -500,7500,13500,7500,6000,*,RIGHT,NWELL +S -200,10000,13200,10000,400,*,RIGHT,NTIE +S -200,0,13200,0,400,*,RIGHT,PTIE +S 4000,900,4000,2900,200,*,UP,NDIF +S 12000,2800,12000,7200,300,*,UP,ALU1 +S 8000,3800,8000,7200,300,*,UP,ALU1 +S 11000,2800,11000,7200,300,*,UP,ALU1 +S 6000,2800,6000,7200,300,*,UP,ALU1 +S 5000,2800,5000,7200,300,*,UP,ALU1 +S 3000,1800,3000,8200,300,*,UP,ALU1 +S 10000,2800,10000,7200,300,*,UP,ALU1 +S -200,500,13200,500,1400,vss,RIGHT,CALU1 +S -200,9500,13200,9500,1400,vdd,RIGHT,CALU1 +S 12000,2800,12000,7200,300,i5,UP,CALU1 +S 11000,2800,11000,7200,300,i4,UP,CALU1 +S 10000,2800,10000,7200,300,i3,UP,CALU1 +S 8000,3800,8000,7200,300,i6,UP,CALU1 +S 7000,3800,7000,7200,300,i2,UP,CALU1 +S 6000,2800,6000,7200,300,i1,UP,CALU1 +S 5000,2800,5000,7200,300,i0,UP,CALU1 +S 3000,1800,3000,8200,300,nq,UP,CALU1 +B 7500,3000,200,200,CONT_TURN1,* +V 7500,2100,CONT_DIF_N,* +V 5500,7700,CONT_DIF_P,* +V 7500,7700,CONT_DIF_P,* +V 6500,8400,CONT_DIF_P,* +B 9000,3000,200,200,CONT_TURN1,* +V 9000,6100,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 10500,1000,CONT_DIF_N,* +V 11500,2000,CONT_DIF_N,* +V 12500,2000,CONT_DIF_N,* +V 12500,7700,CONT_DIF_P,* +V 1900,9000,CONT_DIF_P,* +V 10000,4000,CONT_POLY,* +V 11000,4000,CONT_POLY,* +V 2000,1300,CONT_DIF_N,* +B 4000,2000,200,200,CONT_TURN1,* +V 4400,1200,CONT_DIF_N,* +V 2000,4900,CONT_POLY,* +V 8700,2000,CONT_DIF_N,* +V 1900,8000,CONT_DIF_P,* +V 1900,7000,CONT_DIF_P,* +V 1900,6000,CONT_DIF_P,* +V 700,7000,CONT_DIF_P,* +V 700,6000,CONT_DIF_P,* +V 700,2400,CONT_DIF_N,* +V 6000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 4000,4100,CONT_POLY,* +V 2000,2400,CONT_DIF_N,* +V 12000,4000,CONT_POLY,* +V 8000,4000,CONT_POLY,* +V 7000,4000,CONT_POLY,* +V 3000,2000,CONT_DIF_N,* +V 4200,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 2000,3400,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +V 13000,0,CONT_BODY_P,* +V 13000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/noa3ao322_x4.vbe b/pdks/symbolic/nsxlib2/cells/noa3ao322_x4.vbe new file mode 100644 index 000000000..1fc4b8a6f --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/noa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT tplh_i6_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 729; + CONSTANT tphl_i6_nq : NATURAL := 738; + CONSTANT tphl_i0_nq : NATURAL := 819; + CONSTANT tphl_i4_nq : NATURAL := 821; + CONSTANT tplh_i2_nq : NATURAL := 874; + CONSTANT tplh_i5_nq : NATURAL := 900; + CONSTANT tphl_i5_nq : NATURAL := 907; + CONSTANT tphl_i1_nq : NATURAL := 914; + CONSTANT tplh_i4_nq : NATURAL := 924; + CONSTANT tplh_i3_nq : NATURAL := 926; + CONSTANT tplh_i1_nq : NATURAL := 931; + CONSTANT tplh_i0_nq : NATURAL := 987; + CONSTANT tphl_i2_nq : NATURAL := 990; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1600 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/nts_x1.ap b/pdks/symbolic/nsxlib2/cells/nts_x1.ap new file mode 100644 index 000000000..a8d130d60 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nts_x1.ap @@ -0,0 +1,93 @@ +V ALLIANCE : 6 +H nts_x1,P,17/ 8/2024,100 +A 0,0,6000,10000 +R 3000,5000,ref_ref,nq_15 +R 3000,3000,ref_ref,nq_25 +R 2000,5000,ref_ref,cmd_15 +R 2000,3000,ref_ref,cmd_25 +R 2000,4000,ref_ref,cmd_20 +R 2000,2000,ref_ref,cmd_10 +R 3000,2000,ref_ref,nq_10 +R 3000,8000,ref_ref,nq_40 +R 3000,7000,ref_ref,nq_35 +R 3000,6000,ref_ref,nq_30 +R 3000,4000,ref_ref,nq_20 +R 1000,7000,ref_ref,i_35 +R 1000,6000,ref_ref,i_30 +R 1000,2000,ref_ref,i_10 +R 1000,3000,ref_ref,i_15 +R 1000,4000,ref_ref,i_20 +R 1000,5000,ref_ref,i_25 +R 1000,8000,ref_ref,i_40 +R 2000,6000,ref_ref,cmd_30 +R 2000,7000,ref_ref,cmd_35 +R 2000,8000,ref_ref,cmd_40 +S 5100,5500,5100,7500,400,*,UP,PDIF +S 1600,5500,1600,9400,600,*,UP,PDIF +S 4100,5500,4100,7500,600,*,UP,PDIF +S 1900,5100,3800,5100,200,*,RIGHT,POLY +S 2000,2500,2000,4100,200,*,UP,POLY +S 2000,600,2000,2500,200,*,UP,NTRANS +S 1500,600,1500,2500,400,*,UP,NDIF +S 2000,5100,2000,5500,200,*,UP,POLY +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 1000,600,1000,2500,200,*,UP,NTRANS +S 500,600,500,2500,400,*,UP,NDIF +S 1000,2400,1000,5600,200,*,UP,POLY +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 500,5500,500,9400,400,*,UP,PDIF +S 4600,2500,4600,5600,200,*,UP,POLY +S 3700,5100,4200,5100,400,*,RIGHT,ALU1 +S 5100,5800,5100,8800,300,*,UP,ALU1 +S 5100,1200,5100,2200,300,*,UP,ALU1 +S 4100,1800,4100,7200,300,*,UP,ALU1 +S 1900,4000,4600,4000,200,*,RIGHT,POLY +S 2500,600,2500,2500,400,*,UP,NDIF +S 5100,1500,5100,2500,400,*,UP,NDIF +S 4600,1500,4600,2500,200,*,UP,NTRANS +S 4600,5500,4600,7500,200,*,UP,PTRANS +S 2900,600,2900,2500,800,*,UP,NDIF +S 2500,5500,2500,9400,600,*,UP,PDIF +S 1000,1800,1000,8200,300,i,UP,CALU1 +S 2000,1800,2000,8200,300,cmd,UP,CALU1 +S 3000,1800,3000,8200,300,nq,UP,CALU1 +S 4200,1500,4200,2500,600,*,UP,NDIF +S -500,7500,6500,7500,6000,*,RIGHT,NWELL +S -200,10000,6200,10000,400,*,RIGHT,NTIE +S -200,0,6200,0,400,*,RIGHT,PTIE +S 3000,5500,3000,9400,600,*,UP,PDIF +S 1000,1800,1000,8200,300,*,UP,ALU1 +S 3000,1800,3000,8200,300,*,UP,ALU1 +S 2000,1800,2000,8200,300,*,UP,ALU1 +S -200,500,6200,500,1400,vss,RIGHT,CALU1 +S -200,9500,6200,9500,1400,vdd,RIGHT,CALU1 +V 500,1000,CONT_DIF_N,* +V 500,9000,CONT_DIF_P,* +V 5100,7000,CONT_DIF_P,* +V 5100,6000,CONT_DIF_P,* +V 5100,2000,CONT_DIF_N,* +V 4100,2000,CONT_DIF_N,* +V 4100,7000,CONT_DIF_P,* +V 4100,6000,CONT_DIF_P,* +V 3800,5100,CONT_POLY,* +V 3000,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/nts_x1.vbe b/pdks/symbolic/nsxlib2/cells/nts_x1.vbe new file mode 100644 index 000000000..f6cada4ad --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nts_x1.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_cmd : NATURAL := 14; + CONSTANT cin_i : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i_nq : NATURAL := 3210; + CONSTANT tphl_cmd_nq : NATURAL := 41; + CONSTANT tphl_i_nq : NATURAL := 169; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 249; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x1; + +ARCHITECTURE behaviour_data_flow OF nts_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x1" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 800 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/nsxlib2/cells/nts_x2.ap b/pdks/symbolic/nsxlib2/cells/nts_x2.ap new file mode 100644 index 000000000..ef4bf2832 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nts_x2.ap @@ -0,0 +1,118 @@ +V ALLIANCE : 6 +H nts_x2,P,17/ 8/2024,100 +A 0,0,7000,10000 +R 3000,5000,ref_ref,nq_20 +R 3000,4000,ref_ref,nq_25 +R 5500,4000,ref_ref,cmd_20 +R 5000,7000,ref_ref,cmd_35 +R 5000,6000,ref_ref,cmd_30 +R 5000,5000,ref_ref,cmd_25 +R 5000,3000,ref_ref,cmd_15 +R 5000,2000,ref_ref,cmd_10 +R 3000,6000,ref_ref,nq_30 +R 3000,3000,ref_ref,nq_15 +R 3000,2000,ref_ref,nq_10 +R 3000,7000,ref_ref,nq_35 +R 3000,8000,ref_ref,nq_40 +R 2000,2000,ref_ref,i_10 +R 2000,3000,ref_ref,i_15 +R 2000,4000,ref_ref,i_20 +R 2000,5000,ref_ref,i_25 +R 2000,6000,ref_ref,i_30 +R 2000,7000,ref_ref,i_35 +R 2000,8000,ref_ref,i_40 +S 3300,5100,3900,5100,400,*,LEFT,POLY +S 5100,5500,5100,9400,600,*,UP,PDIF +S 3800,4900,3800,8000,300,*,UP,ALU1 +S 4500,4000,4500,5500,200,*,DOWN,POLY +S 4000,5500,4000,9400,800,*,UP,PDIF +S 2400,5100,3900,5100,200,*,RIGHT,POLY +S 3700,8000,6400,8000,300,*,RIGHT,ALU1 +S 1400,4000,4800,4000,200,*,RIGHT,POLY +S 4700,2400,4700,4000,200,*,UP,POLY +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 5900,2500,5900,5600,200,*,UP,POLY +S 1500,2500,1500,5700,200,*,UP,POLY +S 5000,4000,5700,4000,500,*,RIGHT,ALU1 +S 6400,1800,6400,8000,300,*,UP,ALU1 +S 4000,3000,5000,3000,300,*,RIGHT,ALU1 +S 5400,4000,5900,4000,500,*,RIGHT,POLY +S 5000,1800,5000,7200,300,*,UP,ALU1 +S 5000,1800,5000,7200,300,cmd,UP,CALU1 +S 1500,4000,2000,4000,500,*,RIGHT,POLY +S 1000,5500,1000,9400,600,*,UP,PDIF +S 1900,5500,1900,9400,600,*,UP,PDIF +S -500,7500,7500,7500,6000,*,RIGHT,NWELL +S -200,10000,7200,10000,400,*,RIGHT,NTIE +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +S -200,0,7200,0,400,*,RIGHT,PTIE +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S 6400,5500,6400,7500,400,*,UP,PDIF +S 6400,1500,6400,2500,400,*,UP,NDIF +S 5400,1500,5400,2500,400,*,UP,NDIF +S 5200,600,5200,2500,600,*,UP,NDIF +S 5500,5500,5500,7500,400,*,UP,PDIF +S 5900,5500,5900,7500,200,*,UP,PTRANS +S 5900,1500,5900,2500,200,*,UP,NTRANS +S 5100,600,5100,2500,600,*,UP,NDIF +S 4700,600,4700,2500,200,*,UP,NTRANS +S 2400,2900,4300,2900,200,*,RIGHT,POLY +S 1000,1200,1000,2200,300,*,UP,ALU1 +S 1000,600,1000,2500,400,*,UP,NDIF +S 1500,600,1500,2500,200,*,UP,NTRANS +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 2500,5100,2500,5500,200,*,UP,POLY +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 1900,600,1900,2500,600,*,UP,NDIF +S 2500,2400,2500,2900,200,*,UP,POLY +S 2500,600,2500,2500,200,*,UP,NTRANS +S 900,5800,900,8800,300,*,UP,ALU1 +S 4100,600,4100,2500,800,*,UP,NDIF +S 3500,2500,3500,2900,200,*,UP,POLY +S 3500,600,3500,2500,200,*,UP,NTRANS +S 3000,600,3000,2500,800,*,UP,NDIF +S 3500,5100,3500,5500,200,*,UP,POLY +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 2900,5500,2900,9400,600,*,UP,PDIF +S 3000,1800,3000,8200,300,*,UP,ALU1 +S 2000,1800,2000,8200,300,*,UP,ALU1 +S 3000,1800,3000,8200,300,nq,UP,CALU1 +S 2000,1800,2000,8200,300,i,UP,CALU1 +V 3800,5100,CONT_POLY,* +B 3800,8000,200,200,CONT_TURN1,* +B 6400,8000,200,200,CONT_TURN1,* +V 5500,4000,CONT_POLY,* +V 6400,7000,CONT_DIF_P,* +V 6400,6000,CONT_DIF_P,* +V 6400,2000,CONT_DIF_N,* +V 4100,3000,CONT_POLY,* +V 1000,900,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 900,9200,CONT_DIF_P,* +V 900,8000,CONT_DIF_P,* +V 900,7000,CONT_DIF_P,* +V 900,6000,CONT_DIF_P,* +V 5200,900,CONT_DIF_N,* +V 2000,4000,CONT_POLY,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 5200,9200,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/nts_x2.vbe b/pdks/symbolic/nsxlib2/cells/nts_x2.vbe new file mode 100644 index 000000000..4bb47086f --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nts_x2.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_cmd : NATURAL := 18; + CONSTANT cin_i : NATURAL := 28; + CONSTANT rdown_cmd_nq : NATURAL := 1430; + CONSTANT rdown_i_nq : NATURAL := 1430; + CONSTANT rup_cmd_nq : NATURAL := 1600; + CONSTANT rup_i_nq : NATURAL := 1600; + CONSTANT tphl_cmd_nq : NATURAL := 33; + CONSTANT tphl_i_nq : NATURAL := 167; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 330; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x2; + +ARCHITECTURE behaviour_data_flow OF nts_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x2" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 900 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/nsxlib2/cells/nxr2_x1.ap b/pdks/symbolic/nsxlib2/cells/nxr2_x1.ap new file mode 100644 index 000000000..da2dc0609 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nxr2_x1.ap @@ -0,0 +1,143 @@ +V ALLIANCE : 6 +H nxr2_x1,P,16/ 8/2024,100 +A 0,0,8000,10000 +R 6000,4000,ref_ref,i1_40 +R 6000,8000,ref_ref,i1_25 +R 3000,5000,ref_ref,nq_20 +R 3000,4000,ref_ref,nq_25 +R 2000,5000,ref_ref,i0_20 +R 2000,4000,ref_ref,i0_25 +R 6000,5000,ref_ref,i1_20 +R 6000,2000,ref_ref,i1_10 +R 6000,3000,ref_ref,i1_15 +R 6000,7000,ref_ref,i1_35 +R 6000,6000,ref_ref,i1_30 +R 2000,6000,ref_ref,i0_30 +R 2000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i0_40 +R 3000,6000,ref_ref,nq_30 +R 3000,7000,ref_ref,nq_35 +R 3000,2000,ref_ref,nq_10 +R 3000,3000,ref_ref,nq_15 +R 2000,2000,ref_ref,i0_10 +R 2000,3000,ref_ref,i0_15 +S 4400,2500,4400,5700,200,*,UP,POLY +S 5400,2500,5400,2800,200,*,UP,POLY +S 5000,2900,5000,4300,300,*,UP,ALU1 +S 3000,2000,4000,2000,300,*,RIGHT,ALU1 +S 3700,3000,5100,3000,300,*,RIGHT,ALU1 +S 3400,5200,3400,5600,200,*,UP,POLY +S 3400,2400,3400,2800,200,*,UP,POLY +S 3300,5200,4000,5200,200,*,RIGHT,POLY +S 3300,2800,4000,2800,200,*,RIGHT,POLY +S -500,7500,8700,7500,6000,*,RIGHT,NWELL +S 5300,2800,6800,2800,200,*,RIGHT,POLY +S -200,0,8200,0,400,*,RIGHT,PTIE +S -200,500,8200,500,1400,vss,RIGHT,CALU1 +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +S 5800,5200,6800,5200,200,*,RIGHT,POLY +S 7300,1500,7300,2500,200,*,UP,NDIF +S 4900,4100,5300,4100,300,*,RIGHT,ALU1 +S 7300,6500,7300,8500,600,*,UP,PDIF +S 7100,1500,7100,2500,600,*,UP,NDIF +S 7200,1800,7200,8200,300,*,UP,ALU1 +S 6300,1500,6300,2500,600,*,UP,NDIF +S 6700,2500,6700,2800,200,*,UP,POLY +S 6700,1500,6700,2500,200,*,UP,NTRANS +S 3800,5000,6100,5000,300,*,RIGHT,ALU1 +S 6700,5200,6700,6500,200,*,UP,POLY +S 6000,1800,6000,8200,300,*,UP,ALU1 +S 6000,1800,6000,8200,300,i1,UP,CALU1 +S 6700,6500,6700,8500,200,*,UP,PTRANS +S 6200,6500,6200,8500,600,*,UP,PDIF +S 5900,600,5900,2500,600,*,UP,NDIF +S 6000,5500,6000,9400,600,*,UP,PDIF +S 5400,600,5400,2500,200,*,UP,NTRANS +S 5300,4100,7200,4100,200,*,RIGHT,POLY +S 5400,3900,5400,5500,200,*,UP,POLY +S 5400,5500,5400,9400,200,*,UP,PTRANS +S 5000,600,5000,2500,600,*,UP,NDIF +S 800,4000,4500,4000,200,*,RIGHT,POLY +S 4400,600,4400,2500,200,*,UP,NTRANS +S 4000,600,4000,2500,600,*,UP,NDIF +S 3400,600,3400,2500,200,*,UP,NTRANS +S 4900,5800,4900,8100,300,*,UP,ALU1 +S 2700,8000,5000,8000,300,*,RIGHT,ALU1 +S 4900,5500,4900,9400,600,*,UP,PDIF +S 3000,7000,4000,7000,300,*,RIGHT,ALU1 +S 4400,5500,4400,9400,200,*,UP,PTRANS +S 3900,5500,3900,9400,600,*,UP,PDIF +S 3400,5500,3400,9400,200,*,UP,PTRANS +S 2900,5500,2900,9400,600,*,UP,PDIF +S 3000,1800,3000,7000,300,*,UP,ALU1 +S 3000,1800,3000,7000,300,nq,UP,CALU1 +S 700,1800,700,8200,300,*,UP,ALU1 +S 1600,6500,1600,8500,400,*,UP,PDIF +S 1600,1500,1600,2500,400,*,UP,NDIF +S 1200,5200,1200,6500,200,*,UP,POLY +S 2400,5200,2400,5600,200,*,UP,POLY +S 1200,2400,1200,2800,200,*,UP,POLY +S 2400,2400,2400,2800,200,*,UP,POLY +S 1100,5200,2500,5200,200,*,RIGHT,POLY +S 1100,2800,2500,2800,200,*,RIGHT,POLY +S 2000,1800,2000,8200,300,i0,UP,CALU1 +S 700,6500,700,8500,400,*,UP,PDIF +S 700,1500,700,2500,400,*,UP,NDIF +S 2000,1800,2000,8200,300,*,UP,ALU1 +S 2400,5500,2400,9400,200,*,UP,PTRANS +S 1200,6500,1200,8500,200,*,UP,PTRANS +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 1900,600,1900,2500,400,*,UP,NDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S 7600,6500,7600,8500,200,*,UP,PDIF +S 3000,600,3000,2500,600,*,UP,NDIF +S 1900,5500,1900,9400,400,*,UP,PDIF +B 5150,4100,500,400,CONT_TURN1,* +V 3800,5000,CONT_POLY,* +V 3800,3000,CONT_POLY,* +V 5200,4100,CONT_POLY,* +V 7200,4100,CONT_POLY,* +V 7200,8000,CONT_DIF_P,* +V 7200,7000,CONT_DIF_P,* +V 7200,2000,CONT_DIF_N,* +V 6000,3000,CONT_POLY,* +V 6000,5000,CONT_POLY,* +V 5900,900,CONT_DIF_N,* +V 5900,9000,CONT_DIF_P,* +V 3900,2000,CONT_DIF_N,* +V 4900,6000,CONT_DIF_P,* +V 4900,7000,CONT_DIF_P,* +V 4900,8000,CONT_DIF_P,* +V 3900,7000,CONT_DIF_P,* +V 2900,8000,CONT_DIF_P,* +B 5000,3000,200,200,CONT_TURN1,* +B 3000,7000,200,200,CONT_TURN1,* +B 3000,7000,200,200,CONT_TURN1,* +V 1900,900,CONT_DIF_N,* +V 1900,9000,CONT_DIF_P,* +V 700,8000,CONT_DIF_P,* +V 700,7000,CONT_DIF_P,* +V 700,4000,CONT_POLY,* +V 700,2000,CONT_DIF_N,* +V 2000,3000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/nxr2_x1.vbe b/pdks/symbolic/nsxlib2/cells/nxr2_x1.vbe new file mode 100644 index 000000000..1c89dd228 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nxr2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY nxr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i1_nq : NATURAL := 156; + CONSTANT tphl_i0_nq : NATURAL := 288; + CONSTANT tplh_i0_nq : NATURAL := 293; + CONSTANT tplh_i1_nq : NATURAL := 327; + CONSTANT tphh_i0_nq : NATURAL := 366; + CONSTANT tpll_i0_nq : NATURAL := 389; + CONSTANT tphh_i1_nq : NATURAL := 395; + CONSTANT tpll_i1_nq : NATURAL := 503; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x1; + +ARCHITECTURE behaviour_data_flow OF nxr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x1" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/nxr2_x4.ap b/pdks/symbolic/nsxlib2/cells/nxr2_x4.ap new file mode 100644 index 000000000..172a7b1b0 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nxr2_x4.ap @@ -0,0 +1,176 @@ +V ALLIANCE : 6 +H nxr2_x4,P,14/ 8/2024,100 +A 0,0,12000,10000 +R 7000,5000,ref_ref,i1_20 +R 7000,4000,ref_ref,i1_25 +R 2000,5000,ref_ref,i0_20 +R 2000,4000,ref_ref,i0_25 +R 2000,2000,ref_ref,i0_10 +R 7000,7000,ref_ref,i1_35 +R 7000,8000,ref_ref,i1_40 +R 10000,3000,ref_ref,nq_15 +R 10000,4000,ref_ref,nq_20 +R 10000,5000,ref_ref,nq_25 +R 2000,8000,ref_ref,i0_40 +R 7000,3000,ref_ref,i1_15 +R 7000,6000,ref_ref,i1_30 +R 2000,3000,ref_ref,i0_15 +R 2000,6000,ref_ref,i0_30 +R 2000,7000,ref_ref,i0_35 +S 9000,5500,9000,9400,600,*,UP,PDIF +S 9000,600,9000,2500,600,*,UP,NDIF +S 10500,2500,10500,5500,200,*,UP,POLY +S 9500,2400,9500,5600,200,*,UP,POLY +S 4800,2400,4800,5500,200,*,UP,POLY +S 3600,5100,3600,5500,200,*,UP,POLY +S 6000,2500,6000,4100,200,*,UP,POLY +S 7200,2400,7200,3200,200,*,UP,POLY +S 10000,1900,10000,8100,300,*,UP,ALU1 +S 10000,1900,10000,8100,300,nq,UP,CALU1 +S 11000,5900,11000,8800,300,*,UP,ALU1 +S 9000,6900,9000,8800,300,*,UP,ALU1 +S 4100,5000,5000,5000,300,*,RIGHT,ALU1 +S 3000,7000,4300,7000,300,*,RIGHT,ALU1 +S 4100,3000,7000,3000,300,*,RIGHT,ALU1 +S 7900,2900,7900,5900,300,*,UP,ALU1 +S 7000,2900,7000,8200,300,*,UP,ALU1 +S 7000,2900,7000,8200,300,i1,UP,CALU1 +S 5000,4000,6200,4000,300,*,RIGHT,ALU1 +S 5000,4000,5000,5000,300,*,UP,ALU1 +S 11000,1200,11000,2100,300,*,UP,ALU1 +S 3000,2000,9000,2000,300,*,RIGHT,ALU1 +S 9000,2000,9000,4200,300,*,UP,ALU1 +S 3000,2000,3000,7000,300,*,UP,ALU1 +S 700,1900,700,6100,300,*,UP,ALU1 +S 2900,8000,5500,8000,300,*,RIGHT,ALU1 +S 9200,600,9200,2500,400,*,DOWN,NDIF +S 9200,5500,9200,9400,400,*,UP,PDIF +S 10100,5500,10100,9400,600,*,UP,PDIF +S 8900,4000,10600,4000,500,*,RIGHT,POLY +S 11000,5500,11000,9400,400,*,UP,PDIF +S 10500,5500,10500,9400,200,*,UP,PTRANS +S 9500,5500,9500,9400,200,*,UP,PTRANS +S 11000,600,11000,2500,400,*,UP,NDIF +S 10500,600,10500,2500,200,*,UP,NTRANS +S 10100,600,10100,2500,600,*,UP,NDIF +S 9500,600,9500,2500,200,*,UP,NTRANS +S 6700,5500,6700,7500,600,*,UP,PDIF +S 1700,5500,1700,7500,400,*,UP,PDIF +S 6800,1500,6800,2500,400,*,DOWN,NDIF +S 7600,1500,7600,2500,400,*,DOWN,NDIF +S 1600,1500,1600,2500,400,*,UP,NDIF +S 3500,5100,4300,5100,200,*,RIGHT,POLY +S 2400,5200,2400,5600,200,*,UP,POLY +S 3500,2900,4300,2900,200,*,RIGHT,POLY +S 3600,2500,3600,2900,200,*,UP,POLY +S 2400,2400,2400,2800,200,*,UP,POLY +S 1200,2400,1200,2800,200,*,UP,POLY +S -200,9500,12200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,12200,500,1400,vss,RIGHT,CALU1 +S 7200,5100,7200,5500,200,*,UP,POLY +S 6000,5100,6000,5500,200,*,UP,POLY +S 5900,5100,7300,5100,200,*,RIGHT,POLY +S 6500,5500,6500,9400,400,*,UP,PDIF +S 1900,5500,1900,9400,400,*,UP,PDIF +S 700,5500,700,7500,400,*,UP,PDIF +S 7900,1500,7900,3300,400,*,UP,NDIF +S -500,7500,12500,7500,6000,*,RIGHT,NWELL +S -200,10000,12200,10000,400,*,RIGHT,NTIE +S -200,0,12200,0,400,*,RIGHT,PTIE +S 2000,1800,2000,8200,300,*,UP,ALU1 +S 6000,5500,6000,9400,200,*,UP,PTRANS +S 5400,5500,5400,9400,600,*,UP,PDIF +S 4800,5500,4800,9400,200,*,UP,PTRANS +S 4200,5500,4200,9400,600,*,UP,PDIF +S 2400,5500,2400,9400,200,*,UP,PTRANS +S 3000,5500,3000,9400,600,*,UP,PDIF +S 3600,5500,3600,9400,200,*,UP,PTRANS +S 7200,1500,7200,2500,200,*,UP,NTRANS +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 600,4000,4900,4000,200,*,RIGHT,POLY +S 4800,600,4800,2500,200,*,UP,NTRANS +S 6500,600,6500,2500,400,*,UP,NDIF +S 6000,600,6000,2500,200,*,UP,NTRANS +S 5900,4000,8100,4000,200,*,RIGHT,POLY +S 7800,5500,7800,7500,600,*,UP,PDIF +S 7200,5500,7200,7500,200,*,UP,PTRANS +S 1200,5500,1200,7500,200,*,UP,PTRANS +S 5400,600,5400,2500,600,*,UP,NDIF +S 4200,600,4200,2500,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S 3000,600,3000,2500,600,*,UP,NDIF +S 1900,600,1900,2500,400,*,UP,NDIF +S 2400,600,2400,2500,200,*,UP,NTRANS +S 700,1500,700,2500,400,*,UP,NDIF +S 2000,1800,2000,8200,300,i0,UP,CALU1 +S 1100,5200,2500,5200,200,*,RIGHT,POLY +S 1200,5100,1200,5600,200,*,UP,POLY +S 1100,2800,2500,2800,200,*,RIGHT,POLY +V 9000,9000,CONT_DIF_P,* +B 5000,5000,200,200,CONT_TURN1,* +B 5000,4000,200,200,CONT_TURN1,* +B 9000,2000,200,200,CONT_TURN1,* +B 3000,2000,200,200,CONT_TURN1,* +B 3000,7000,200,200,CONT_TURN1,* +V 11000,9200,CONT_DIF_P,* +V 11000,8000,CONT_DIF_P,* +V 11000,7000,CONT_DIF_P,* +V 11000,6000,CONT_DIF_P,* +V 11000,900,CONT_DIF_N,* +V 11000,2000,CONT_DIF_N,* +V 9000,900,CONT_DIF_N,* +V 6500,9200,CONT_DIF_P,* +V 6500,900,CONT_DIF_N,* +V 1900,9200,CONT_DIF_P,* +V 700,6000,CONT_DIF_P,* +V 1900,900,CONT_DIF_N,* +V 700,2000,CONT_DIF_N,* +V 7900,5800,CONT_DIF_P,* +V 7900,3000,CONT_DIF_N,* +V 7900,4000,CONT_POLY,* +V 10000,2000,CONT_DIF_N,* +V 4200,3000,CONT_POLY,* +V 4200,5000,CONT_POLY,* +V 4200,7000,CONT_DIF_P,* +V 4200,2000,CONT_DIF_N,* +V 5400,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 800,4000,CONT_POLY,* +V 7000,3000,CONT_POLY,* +V 10000,6000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 9000,4000,CONT_POLY,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 7000,5000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/nxr2_x4.vbe b/pdks/symbolic/nsxlib2/cells/nxr2_x4.vbe new file mode 100644 index 000000000..aa5ea7108 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/nxr2_x4.vbe @@ -0,0 +1,36 @@ +ENTITY nxr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tpll_i1_nq : NATURAL := 453; + CONSTANT tphh_i0_nq : NATURAL := 469; + CONSTANT tpll_i0_nq : NATURAL := 481; + CONSTANT tphl_i0_nq : NATURAL := 522; + CONSTANT tplh_i1_nq : NATURAL := 542; + CONSTANT tphl_i1_nq : NATURAL := 553; + CONSTANT tplh_i0_nq : NATURAL := 553; + CONSTANT tphh_i1_nq : NATURAL := 568; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x4; + +ARCHITECTURE behaviour_data_flow OF nxr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x4" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/o2_x2.ap b/pdks/symbolic/nsxlib2/cells/o2_x2.ap new file mode 100644 index 000000000..9df13c32c --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o2_x2.ap @@ -0,0 +1,81 @@ +V ALLIANCE : 6 +H o2_x2,P,20/12/2024,100 +A 0,0,5000,10000 +R 3000,5000,ref_ref,i0_20 +R 3000,4000,ref_ref,i0_25 +R 1000,5000,ref_ref,i1_25 +R 3000,2000,ref_ref,i0_10 +R 1000,3000,ref_ref,i1_15 +R 1000,4000,ref_ref,i1_20 +R 1000,6000,ref_ref,i1_30 +R 1000,7000,ref_ref,i1_35 +R 4000,5000,ref_ref,q_25 +R 4000,4000,ref_ref,q_20 +R 4000,3000,ref_ref,q_15 +R 3000,8000,ref_ref,i0_40 +R 3000,7000,ref_ref,i0_35 +R 3000,6000,ref_ref,i0_30 +S 900,4000,1500,4000,500,*,LEFT,POLY +S 900,1500,900,2500,600,*,UP,NDIF +S 2400,2800,3000,2800,200,*,RIGHT,POLY +S 2500,2500,2500,2800,200,*,UP,POLY +S 2500,1500,2500,2500,200,*,UP,NTRANS +S 1500,1500,1500,2500,200,*,UP,NTRANS +S 1500,2400,1500,5500,200,*,UP,POLY +S 1500,5500,1500,8500,200,*,UP,PTRANS +S 800,8000,2100,8000,300,*,RIGHT,ALU1 +S 2000,1800,2000,8200,300,*,UP,ALU1 +S 2300,5000,2300,5500,200,*,UP,POLY +S 3500,2500,3500,5500,200,*,UP,POLY +S 900,1200,900,2100,400,*,UP,ALU1 +S 2200,5000,3000,5000,200,*,RIGHT,POLY +S 3000,5500,3000,9400,400,*,UP,PDIF +S 4000,5500,4000,9400,400,*,UP,PDIF +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 1900,4000,3600,4000,200,*,RIGHT,POLY +S 4000,600,4000,2500,400,*,UP,NDIF +S 3500,600,3500,2500,200,*,UP,NTRANS +S 3000,600,3000,2500,400,*,UP,NDIF +S 2700,5500,2700,8500,400,*,UP,PDIF +S 1900,5500,1900,8500,400,*,UP,PDIF +S 3000,1500,3000,2500,600,*,UP,NDIF +S 1900,1500,1900,2500,600,*,UP,NDIF +S 4000,1800,4000,8200,300,q,UP,CALU1 +S 4000,1800,4000,8200,300,*,UP,ALU1 +S 1000,2800,1000,7200,300,i1,UP,CALU1 +S 3000,1800,3000,8200,300,i0,UP,CALU1 +S 3000,1800,3000,8200,300,*,UP,ALU1 +S -500,7500,5500,7500,6000,*,RIGHT,NWELL +S -200,10000,5200,10000,400,*,RIGHT,NTIE +S -200,0,5200,0,400,*,RIGHT,PTIE +S 2300,5500,2300,8500,200,*,UP,PTRANS +S 1000,5500,1000,8500,600,*,UP,PDIF +S 1000,2800,1000,7200,300,*,UP,ALU1 +S -200,500,5200,500,1400,vss,RIGHT,CALU1 +S -200,9500,5200,9500,1400,vdd,RIGHT,CALU1 +V 2000,2000,CONT_DIF_N,* +V 2100,4000,CONT_POLY,* +V 2900,3000,CONT_POLY,* +V 2900,5000,CONT_POLY,* +V 900,8000,CONT_DIF_P,* +V 3000,9100,CONT_DIF_P,* +V 3000,900,CONT_DIF_N,* +V 900,1900,CONT_DIF_N,* +V 4000,8000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 4000,2000,CONT_DIF_N,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/o2_x2.vbe b/pdks/symbolic/nsxlib2/cells/o2_x2.vbe new file mode 100644 index 000000000..9e115a06f --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tpll_i0_q : NATURAL := 310; + CONSTANT tphh_i1_q : NATURAL := 335; + CONSTANT tpll_i1_q : NATURAL := 364; + CONSTANT tphh_i0_q : NATURAL := 406; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x2; + +ARCHITECTURE behaviour_data_flow OF o2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x2" + SEVERITY WARNING; + q <= (i0 or i1) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/o2_x4.ap b/pdks/symbolic/nsxlib2/cells/o2_x4.ap new file mode 100644 index 000000000..937a0eec5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o2_x4.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H o2_x4,P,16/ 8/2024,100 +A 0,0,6000,10000 +R 1000,5000,ref_ref,i1_35 +R 1000,7000,ref_ref,i1_25 +R 3000,4800,ref_ref,i0_20 +R 3000,4000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 3000,8000,ref_ref,i0_40 +R 4000,3000,ref_ref,q_15 +R 4000,4000,ref_ref,q_20 +R 4000,5000,ref_ref,q_25 +R 1000,6000,ref_ref,i1_30 +R 1000,4000,ref_ref,i1_20 +R 1000,3000,ref_ref,i1_15 +R 3000,2000,ref_ref,i0_10 +S 2400,5000,2400,5500,200,*,UP,POLY +S 1400,2500,1400,2800,200,*,UP,POLY +S 2400,2400,2400,3000,200,*,UP,POLY +S 3000,4000,3000,5000,400,*,UP,ALU1 +S 2300,5000,3000,5000,200,*,RIGHT,POLY +S 2300,3000,3000,3000,200,*,RIGHT,POLY +S 4500,600,4500,2500,200,*,UP,NTRANS +S 5000,5500,5000,9400,400,*,UP,PDIF +S 5000,5800,5000,9200,300,*,UP,ALU1 +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 4100,5500,4100,9400,600,*,UP,PDIF +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 3000,5500,3000,9400,400,*,UP,PDIF +S 900,700,900,2200,300,*,UP,ALU1 +S 1800,4000,4600,4000,200,*,RIGHT,POLY +S 4500,2400,4500,5500,200,*,UP,POLY +S 5000,600,5000,2500,400,*,UP,NDIF +S 5000,800,5000,2200,300,*,UP,ALU1 +S 4100,600,4100,2500,600,*,UP,NDIF +S 3500,2500,3500,5500,200,*,UP,POLY +S 3500,600,3500,2500,200,*,UP,NTRANS +S 3000,600,3000,2500,400,*,UP,NDIF +S 2900,5500,2900,8500,600,*,UP,PDIF +S 2000,5500,2000,8500,600,*,UP,PDIF +S 1000,2800,1000,5100,200,*,UP,POLY +S 1500,5100,1500,5500,200,*,UP,POLY +S 2800,1500,2800,2500,400,*,UP,NDIF +S 2400,1500,2400,2500,200,*,UP,NTRANS +S 900,1500,900,2500,400,*,UP,NDIF +S 4000,1800,4000,8200,300,*,UP,ALU1 +S 4000,1800,4000,8200,300,q,UP,CALU1 +S 3000,1800,3000,8200,300,i0,UP,CALU1 +S 1000,2800,1000,7200,300,i1,UP,CALU1 +S 900,5100,1600,5100,200,*,RIGHT,POLY +S 900,2800,1500,2800,200,*,LEFT,POLY +S -200,9500,6200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,6200,500,1400,vss,RIGHT,CALU1 +S 800,8000,2100,8000,300,*,RIGHT,ALU1 +S -500,7500,6500,7500,6000,*,RIGHT,NWELL +S -200,10000,6200,10000,400,*,RIGHT,NTIE +S -200,0,6200,0,400,*,RIGHT,PTIE +S 1500,5500,1500,8500,200,*,UP,PTRANS +S 1400,1500,1400,2500,200,*,UP,NTRANS +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 1000,5500,1000,8500,600,*,UP,PDIF +S 2400,5500,2400,8500,200,*,UP,PTRANS +S 1800,1500,1800,2500,600,*,UP,NDIF +S 2400,1500,2400,2500,200,*,UP,NTRANS +S 3000,1800,3000,8200,300,*,UP,ALU1 +S 1900,1800,1900,8200,300,*,UP,ALU1 +V 2800,4800,CONT_POLY,* +V 2800,3200,CONT_POLY,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,9200,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 3000,9200,CONT_DIF_P,* +V 5000,900,CONT_DIF_N,* +V 5000,2000,CONT_DIF_N,* +V 3000,900,CONT_DIF_N,* +V 900,2000,CONT_DIF_N,* +V 1900,2000,CONT_DIF_N,* +V 1900,4000,CONT_POLY,* +V 1000,8000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/o2_x4.vbe b/pdks/symbolic/nsxlib2/cells/o2_x4.vbe new file mode 100644 index 000000000..e22a93618 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 394; + CONSTANT tphh_i1_q : NATURAL := 427; + CONSTANT tpll_i1_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 491; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x4; + +ARCHITECTURE behaviour_data_flow OF o2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x4" + SEVERITY WARNING; + q <= (i0 or i1) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/o3_x2.ap b/pdks/symbolic/nsxlib2/cells/o3_x2.ap new file mode 100644 index 000000000..6e6431ba7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o3_x2.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H o3_x2,P,17/ 8/2024,100 +A 0,0,6000,10000 +R 5000,4000,ref_ref,q_20 +R 5000,3000,ref_ref,q_15 +R 5000,2000,ref_ref,q_10 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 1000,5000,ref_ref,i2_25 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 5000,8000,ref_ref,q_40 +R 5000,7000,ref_ref,q_35 +R 5000,6000,ref_ref,q_30 +R 5000,5000,ref_ref,q_25 +R 1000,6000,ref_ref,i2_30 +R 1000,7000,ref_ref,i2_35 +R 1000,4000,ref_ref,i2_20 +S 3600,5500,3600,8500,800,*,UP,PDIF +S 400,8000,4100,8000,300,*,RIGHT,ALU1 +S 3000,2500,3000,5600,200,*,UP,POLY +S 3000,1500,3000,2500,200,*,UP,NTRANS +S 2400,1500,2400,2500,600,*,UP,NDIF +S 2500,1900,2500,3000,300,*,UP,ALU1 +S 3000,5500,3000,8500,200,*,UP,PTRANS +S 2500,5500,2500,8500,400,*,UP,PDIF +S 2000,5500,2000,8500,200,*,UP,PTRANS +S 1500,5500,1500,8500,400,*,UP,PDIF +S 2000,2400,2000,5600,200,*,UP,POLY +S 2000,1500,2000,2500,200,*,UP,NTRANS +S 1500,1500,1500,2500,400,*,UP,NDIF +S 1500,1200,1500,2100,300,*,UP,ALU1 +S 400,3000,4000,3000,300,*,RIGHT,ALU1 +S 1000,1500,1000,2500,200,*,UP,NTRANS +S 500,1500,500,2500,400,*,UP,NDIF +S 500,1900,500,3000,300,*,UP,ALU1 +S 1000,2400,1000,5600,200,*,UP,POLY +S 1000,5500,1000,8500,200,*,UP,PTRANS +S 500,5500,500,8500,400,*,UP,PDIF +S 4500,2500,4500,5600,200,*,UP,POLY +S 3700,1500,3700,2500,600,*,UP,NDIF +S 3700,1200,3700,2100,300,*,UP,ALU1 +S 4000,3000,4000,8000,300,*,UP,ALU1 +S 4000,600,4000,2500,400,*,UP,NDIF +S 3900,4000,4600,4000,500,*,RIGHT,POLY +S 3800,5500,3800,9400,400,*,UP,PDIF +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 5000,600,5000,2500,400,*,UP,NDIF +S 4500,600,4500,2500,200,*,UP,NTRANS +S 3400,1500,3400,2500,200,*,UP,NDIF +S 5000,5500,5000,9400,400,*,UP,PDIF +S 5000,1800,5000,8300,300,q,UP,CALU1 +S 5000,1800,5000,8300,300,*,UP,ALU1 +S 3000,3800,3000,7200,300,i0,UP,CALU1 +S 2000,3800,2000,7200,300,i1,UP,CALU1 +S 1000,3800,1000,7200,300,i2,UP,CALU1 +S 1000,3800,1000,7200,300,*,UP,ALU1 +S 3000,3800,3000,7200,300,*,UP,ALU1 +S 2000,3800,2000,7200,300,*,UP,ALU1 +S -500,7500,6500,7500,6000,*,RIGHT,NWELL +S -200,10000,6200,10000,400,*,RIGHT,NTIE +S -200,0,6200,0,400,*,RIGHT,PTIE +S 4100,5500,4100,9400,400,*,UP,PDIF +S -200,500,6200,500,1400,vss,RIGHT,CALU1 +S -200,9500,6200,9500,1400,vdd,RIGHT,CALU1 +V 2500,2000,CONT_DIF_N,* +V 1500,2000,CONT_DIF_N,* +B 500,3000,200,200,CONT_TURN1,* +V 500,2000,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 3000,4000,CONT_POLY,* +B 4000,8000,200,200,CONT_TURN1,* +B 4000,3000,200,200,CONT_TURN1,* +V 4000,9200,CONT_DIF_P,* +V 3700,2000,CONT_DIF_N,* +V 5000,8000,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 5000,7000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/o3_x2.vbe b/pdks/symbolic/nsxlib2/cells/o3_x2.vbe new file mode 100644 index 000000000..5aad7aba9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 360; + CONSTANT tpll_i0_q : NATURAL := 407; + CONSTANT tphh_i1_q : NATURAL := 430; + CONSTANT tpll_i1_q : NATURAL := 482; + CONSTANT tphh_i0_q : NATURAL := 494; + CONSTANT tpll_i2_q : NATURAL := 506; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x2; + +ARCHITECTURE behaviour_data_flow OF o3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x2" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/o3_x4.ap b/pdks/symbolic/nsxlib2/cells/o3_x4.ap new file mode 100644 index 000000000..59781f4a9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o3_x4.ap @@ -0,0 +1,110 @@ +V ALLIANCE : 6 +H o3_x4,P,17/ 8/2024,100 +A 0,0,7000,10000 +R 3000,7000,ref_ref,i0_35 +R 5000,5000,ref_ref,q_25 +R 5000,4000,ref_ref,q_20 +R 5000,3000,ref_ref,q_15 +R 1000,5000,ref_ref,i2_25 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 3000,3000,ref_ref,i0_15 +R 3000,6000,ref_ref,i0_30 +R 3000,5000,ref_ref,i0_25 +R 3000,4000,ref_ref,i0_20 +R 1000,6000,ref_ref,i2_30 +R 1000,7000,ref_ref,i2_35 +R 1000,3000,ref_ref,i2_15 +R 1000,4000,ref_ref,i2_20 +S 6000,600,6000,2500,400,*,UP,NDIF +S 3600,600,3600,2500,800,*,UP,NDIF +S 6100,5500,6100,9400,400,*,UP,PDIF +S 4000,1900,4000,8000,300,*,UP,ALU1 +S 3000,2500,3000,5600,200,*,UP,POLY +S 2000,2300,2000,5500,200,*,UP,POLY +S 1000,2500,1000,5500,200,*,UP,POLY +S 3000,600,3000,2500,200,*,UP,NTRANS +S 2500,600,2500,2500,400,*,UP,NDIF +S 2000,600,2000,2500,200,*,UP,NTRANS +S 1500,600,1500,2500,400,*,UP,NDIF +S 1000,600,1000,2500,200,*,UP,NTRANS +S 500,600,500,2500,400,*,UP,NDIF +S 400,2000,4000,2000,300,*,RIGHT,ALU1 +S 3000,5500,3000,8500,200,*,UP,PTRANS +S 2500,5500,2500,8500,400,*,UP,PDIF +S 2000,5500,2000,8500,200,*,UP,PTRANS +S 1500,5500,1500,8500,400,*,UP,PDIF +S 1000,5500,1000,8500,200,*,UP,PTRANS +S 500,5500,500,8500,400,*,UP,PDIF +S 400,8000,4000,8000,300,*,RIGHT,ALU1 +S 3900,4000,4500,4000,500,*,LEFT,POLY +S 4400,4000,5500,4000,400,*,RIGHT,POLY +S 6000,800,6000,2200,300,*,UP,ALU1 +S 6000,5800,6000,9200,300,*,UP,ALU1 +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 5500,2500,5500,5500,200,*,UP,POLY +S 5000,600,5000,2500,400,*,UP,NDIF +S 5500,600,5500,2500,200,*,UP,NTRANS +S 4500,600,4500,2500,200,*,UP,NTRANS +S 4500,2500,4500,5500,200,*,UP,POLY +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 5000,5500,5000,9400,400,*,UP,PDIF +S 3400,5500,3400,8500,400,*,UP,PDIF +S 4100,600,4100,2500,400,*,UP,NDIF +S 1000,2800,1000,7200,300,i2,UP,CALU1 +S 2000,2800,2000,7200,300,i1,UP,CALU1 +S 3000,2800,3000,7200,300,i0,UP,CALU1 +S 5000,1800,5000,8200,300,q,UP,CALU1 +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 2000,2800,2000,7200,300,*,UP,ALU1 +S 3000,2800,3000,7200,300,*,UP,ALU1 +S -500,7500,7500,7500,6000,*,RIGHT,NWELL +S -200,10000,7200,10000,400,*,RIGHT,NTIE +S -200,0,7200,0,400,*,RIGHT,PTIE +S 5000,1800,5000,8200,300,*,UP,ALU1 +S 4200,5500,4200,9400,400,*,UP,PDIF +S 3800,5500,3800,9400,400,*,UP,PDIF +B 3950,7950,300,300,CONT_TURN1,* +B 3950,2000,300,200,CONT_TURN1,* +V 2500,2000,CONT_DIF_N,* +V 1500,900,CONT_DIF_N,* +V 500,2000,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 6000,9200,CONT_DIF_P,* +V 3900,9000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 6000,900,CONT_DIF_N,* +V 6000,2000,CONT_DIF_N,* +V 3700,900,CONT_DIF_N,* +V 5000,8000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 2000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/o3_x4.vbe b/pdks/symbolic/nsxlib2/cells/o3_x4.vbe new file mode 100644 index 000000000..1e7ea94f8 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 447; + CONSTANT tpll_i0_q : NATURAL := 501; + CONSTANT tphh_i1_q : NATURAL := 510; + CONSTANT tphh_i0_q : NATURAL := 569; + CONSTANT tpll_i1_q : NATURAL := 585; + CONSTANT tpll_i2_q : NATURAL := 622; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x4; + +ARCHITECTURE behaviour_data_flow OF o3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x4" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/o4_x2.ap b/pdks/symbolic/nsxlib2/cells/o4_x2.ap new file mode 100644 index 000000000..005888a2e --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o4_x2.ap @@ -0,0 +1,121 @@ +V ALLIANCE : 6 +H o4_x2,P,17/ 8/2024,100 +A 0,0,7000,10000 +R 6000,4000,ref_ref,q_20 +R 6000,5000,ref_ref,q_25 +R 6000,7000,ref_ref,q_35 +R 1000,4000,ref_ref,i3_20 +R 1000,5000,ref_ref,i3_25 +R 6000,2000,ref_ref,q_10 +R 6000,3000,ref_ref,q_15 +R 6000,8000,ref_ref,q_40 +R 6000,6000,ref_ref,q_30 +R 4000,7000,ref_ref,i2_35 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 4000,4000,ref_ref,i2_20 +R 4000,5000,ref_ref,i2_25 +R 4000,6000,ref_ref,i2_30 +R 1000,6000,ref_ref,i3_30 +R 1000,7000,ref_ref,i3_35 +S 4600,5500,4600,8500,1000,*,UP,PDIF +S 4700,1500,4700,2500,1000,*,UP,NDIF +S 2400,1500,2400,2500,400,*,UP,NDIF +S 2000,2500,2000,5600,200,*,UP,POLY +S 1000,2500,1000,5700,200,*,UP,POLY +S 400,8000,5100,8000,300,*,RIGHT,ALU1 +S 1000,3800,1000,7200,300,*,UP,ALU1 +S 1000,3800,1000,7200,300,i3,UP,CALU1 +S 1400,3000,5100,3000,300,*,RIGHT,ALU1 +S 4600,1200,4600,2100,400,*,UP,ALU1 +S 2700,1500,2700,2500,400,*,UP,NDIF +S 4000,2400,4000,5500,200,*,UP,POLY +S 3000,2300,3000,5600,200,*,UP,POLY +S 3500,1900,3500,3000,300,*,UP,ALU1 +S 4000,1500,4000,2500,200,*,UP,NTRANS +S 3500,1500,3500,2500,400,*,UP,NDIF +S 3000,1500,3000,2500,200,*,UP,NTRANS +S 2500,1200,2500,2100,400,*,UP,ALU1 +S 2000,1500,2000,2500,200,*,UP,NTRANS +S 1500,1500,1500,2500,400,*,UP,NDIF +S 1500,1900,1500,3000,300,*,UP,ALU1 +S 1000,1500,1000,2500,200,*,UP,NTRANS +S 500,1500,500,2500,400,*,UP,NDIF +S 500,1200,500,2000,400,*,UP,ALU1 +S 4000,5500,4000,8500,200,*,UP,PTRANS +S 3400,5500,3400,8500,600,*,UP,PDIF +S 3000,5500,3000,8500,200,*,UP,PTRANS +S 2500,5500,2500,8500,400,*,UP,PDIF +S 2000,5500,2000,8500,200,*,UP,PTRANS +S 1500,5500,1500,8500,400,*,UP,PDIF +S 1000,5500,1000,8500,200,*,UP,PTRANS +S 500,5500,500,8500,400,*,UP,PDIF +S 5500,2500,5500,5500,200,*,UP,POLY +S 5200,600,5200,2500,400,*,UP,NDIF +S 5100,3000,5100,8000,300,*,UP,ALU1 +S 6000,5500,6000,9400,400,*,UP,PDIF +S 6000,600,6000,2500,400,*,UP,NDIF +S 5100,4000,5600,4000,500,*,RIGHT,POLY +S 1800,4000,2300,4000,500,*,LEFT,POLY +S 800,4000,1300,4000,500,*,LEFT,POLY +S 4900,5500,4900,9400,400,*,UP,PDIF +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 5500,600,5500,2500,200,*,UP,NTRANS +S 2600,1500,2600,2500,400,*,UP,NDIF +S 2000,3800,2000,7200,300,i1,UP,CALU1 +S 2000,3800,2000,7200,300,*,UP,ALU1 +S 3000,3800,3000,7200,300,i0,UP,CALU1 +S 3000,3800,3000,7200,300,*,UP,ALU1 +S 4000,3800,4000,7200,300,i2,UP,CALU1 +S 6000,1800,6000,8200,300,q,UP,CALU1 +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S 6000,1800,6000,8200,300,*,UP,ALU1 +S 5300,5500,5300,9400,200,*,UP,PDIF +S 5000,5500,5000,9400,600,*,UP,PDIF +S -500,7500,7500,7500,6000,*,RIGHT,NWELL +S -200,10000,7200,10000,400,*,RIGHT,NTIE +S -200,0,7200,0,400,*,RIGHT,PTIE +S 4000,3800,4000,7200,300,*,UP,ALU1 +B 1500,3000,200,200,CONT_TURN1,* +V 4600,2000,CONT_DIF_N,* +V 3500,2000,CONT_DIF_N,* +V 2500,2000,CONT_DIF_N,* +V 1500,2000,CONT_DIF_N,* +V 500,1900,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +B 5100,8000,200,200,CONT_TURN1,* +B 5100,3000,200,200,CONT_TURN1,* +V 5000,9200,CONT_DIF_P,* +V 5100,4000,CONT_POLY,* +V 6000,2000,CONT_DIF_N,* +V 6000,6000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 3000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/o4_x2.vbe b/pdks/symbolic/nsxlib2/cells/o4_x2.vbe new file mode 100644 index 000000000..09652e62b --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i3_q : NATURAL := 378; + CONSTANT tphh_i1_q : NATURAL := 446; + CONSTANT tphh_i0_q : NATURAL := 508; + CONSTANT tpll_i2_q : NATURAL := 531; + CONSTANT tphh_i2_q : NATURAL := 567; + CONSTANT tpll_i0_q : NATURAL := 601; + CONSTANT tpll_i3_q : NATURAL := 626; + CONSTANT tpll_i1_q : NATURAL := 631; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x2; + +ARCHITECTURE behaviour_data_flow OF o4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x2" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/o4_x4.ap b/pdks/symbolic/nsxlib2/cells/o4_x4.ap new file mode 100644 index 000000000..86cf87e88 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o4_x4.ap @@ -0,0 +1,142 @@ +V ALLIANCE : 6 +H o4_x4,P,17/ 8/2024,100 +A 0,0,8000,10000 +R 7000,5000,ref_ref,q_20 +R 7000,4000,ref_ref,q_25 +R 7000,3000,ref_ref,q_15 +R 4000,8000,ref_ref,i2_40 +R 4000,7000,ref_ref,i2_35 +R 5000,4000,ref_ref,i3_20 +R 2000,8000,ref_ref,i1_40 +R 5000,8000,ref_ref,i3_40 +R 5000,7000,ref_ref,i3_35 +R 5000,6000,ref_ref,i3_30 +R 5000,5000,ref_ref,i3_25 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 3000,7000,ref_ref,i0_35 +R 7000,2000,ref_ref,q_10 +R 3000,3000,ref_ref,i0_15 +R 2000,3000,ref_ref,i1_15 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i1_35 +R 4000,6000,ref_ref,i2_30 +R 4000,5000,ref_ref,i2_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 3000,8000,ref_ref,i0_40 +S 4000,2900,4000,5700,200,*,UP,POLY +S 2000,2500,2000,4900,200,*,UP,POLY +S 3000,2500,3000,3900,200,*,UP,POLY +S 6200,2000,7200,2000,500,*,RIGHT,ALU1 +S 1300,2000,5400,2000,300,*,RIGHT,ALU1 +S 5300,3000,6200,3000,300,*,RIGHT,ALU1 +S 5400,2000,5400,3000,300,*,UP,ALU1 +S 1700,5500,1700,9400,400,*,DOWN,PDIF +S 7000,1900,7000,6100,300,*,UP,ALU1 +S 7000,1900,7000,6100,300,q,UP,CALU1 +S 1300,2000,1300,8100,300,*,UP,ALU1 +S 7500,6900,7500,9200,300,*,UP,ALU1 +S 6500,5900,6500,8100,300,*,UP,ALU1 +S 6200,2900,6200,5200,300,*,UP,ALU1 +S 5900,2900,7100,2900,200,*,RIGHT,POLY +S 7500,5500,7500,9400,400,*,UP,PDIF +S 2500,5500,2500,9400,400,*,UP,PDIF +S 3500,5500,3500,9400,400,*,UP,PDIF +S 4500,5500,4500,9400,400,*,UP,PDIF +S 5900,5100,7100,5100,200,*,RIGHT,POLY +S 3500,600,3500,2500,400,*,UP,NDIF +S 4500,600,4500,2500,400,*,UP,NDIF +S 5500,600,5500,2500,400,*,UP,NDIF +S 6500,600,6500,2500,400,*,UP,NDIF +S 6000,600,6000,2500,200,*,UP,NTRANS +S 6000,5100,6000,5500,200,*,UP,POLY +S 7000,5100,7000,5500,200,*,UP,POLY +S 6000,2500,6000,2900,200,*,UP,POLY +S 7000,2500,7000,2900,200,*,UP,POLY +S 5500,5500,5500,9400,400,*,UP,PDIF +S 6000,5500,6000,9400,200,*,UP,PTRANS +S 6500,5500,6500,9400,400,*,UP,PDIF +S 7000,5500,7000,9400,200,*,UP,PTRANS +S 5000,2900,5000,5500,200,*,UP,POLY +S 5000,5500,5000,9400,200,*,UP,PTRANS +S 5000,2500,5000,3000,200,*,UP,POLY +S 4000,5500,4000,9400,200,*,UP,PTRANS +S 4000,2500,4000,3000,200,*,UP,POLY +S 3000,3900,3000,5500,200,*,UP,POLY +S 3000,5500,3000,9400,200,*,UP,PTRANS +S 7500,600,7500,2500,400,*,UP,NDIF +S 7000,600,7000,2500,200,*,UP,NTRANS +S 5000,600,5000,2500,200,*,UP,NTRANS +S 4000,600,4000,2500,200,*,UP,NTRANS +S 3000,600,3000,2500,200,*,UP,NTRANS +S 1400,5500,1400,8500,600,*,UP,PDIF +S 2500,600,2500,2500,400,*,UP,NDIF +S 1500,600,1500,2500,400,*,UP,NDIF +S 2000,600,2000,2500,200,*,UP,NTRANS +S 2000,4900,2000,5500,200,*,UP,POLY +S 4000,2800,4000,8200,300,*,UP,ALU1 +S 3000,2800,3000,8200,300,*,UP,ALU1 +S 2000,2800,2000,8200,300,*,UP,ALU1 +S -500,7500,8500,7500,6000,*,RIGHT,NWELL +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,0,8200,0,400,*,RIGHT,PTIE +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 5000,3800,5000,8200,300,*,UP,ALU1 +S -200,500,8200,500,1400,vss,RIGHT,CALU1 +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +S 5000,3800,5000,8200,300,i3,UP,CALU1 +S 4000,2800,4000,8200,300,i2,UP,CALU1 +S 3000,2800,3000,8200,300,i0,UP,CALU1 +S 2000,2800,2000,8200,300,i1,UP,CALU1 +V 2000,4000,CONT_POLY,* +B 6700,6050,800,500,CONT_TURN1,* +B 6200,3000,200,200,CONT_TURN1,* +B 5400,2000,200,200,CONT_TURN1,* +B 5400,3000,200,200,CONT_TURN1,* +B 7000,6000,200,400,CONT_TURN1,* +B 1300,2000,200,200,CONT_TURN1,* +V 4500,2000,CONT_DIF_N,* +V 5500,9100,CONT_DIF_P,* +V 6500,6000,CONT_DIF_P,* +V 6500,7000,CONT_DIF_P,* +V 6500,8000,CONT_DIF_P,* +V 7500,9100,CONT_DIF_P,* +V 7500,8000,CONT_DIF_P,* +V 7500,7000,CONT_DIF_P,* +V 7500,900,CONT_DIF_N,* +V 6500,2000,CONT_DIF_N,* +V 5500,900,CONT_DIF_N,* +V 3500,900,CONT_DIF_N,* +V 1500,900,CONT_DIF_N,* +V 1300,6000,CONT_DIF_P,* +V 1300,7000,CONT_DIF_P,* +V 1300,8000,CONT_DIF_P,* +V 2500,2000,CONT_DIF_N,* +V 6200,3000,CONT_POLY,* +V 6200,5000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/o4_x4.vbe b/pdks/symbolic/nsxlib2/cells/o4_x4.vbe new file mode 100644 index 000000000..bc869a8fb --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/o4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 492; + CONSTANT tpll_i3_q : NATURAL := 536; + CONSTANT tphh_i0_q : NATURAL := 574; + CONSTANT tpll_i2_q : NATURAL := 611; + CONSTANT tpll_i0_q : NATURAL := 638; + CONSTANT tphh_i2_q : NATURAL := 649; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 721; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x4; + +ARCHITECTURE behaviour_data_flow OF o4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x4" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa22_x2.ap b/pdks/symbolic/nsxlib2/cells/oa22_x2.ap new file mode 100644 index 000000000..7efbbc5bf --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa22_x2.ap @@ -0,0 +1,112 @@ +V ALLIANCE : 6 +H oa22_x2,P,14/ 8/2024,100 +A 0,0,6000,10000 +R 4000,5000,ref_ref,i2_20 +R 4000,4000,ref_ref,i2_25 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 4000,3000,ref_ref,i2_15 +R 4000,2000,ref_ref,i2_10 +R 5000,2000,ref_ref,q_10 +R 5000,3000,ref_ref,q_15 +R 5000,4000,ref_ref,q_20 +R 5000,5000,ref_ref,q_25 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 1000,2000,ref_ref,i0_10 +R 5000,6000,ref_ref,q_30 +R 5000,7000,ref_ref,q_35 +R 5000,8000,ref_ref,q_40 +R 4000,6000,ref_ref,i2_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 2000,2000,ref_ref,i1_10 +S 4500,2500,4500,5500,200,*,UP,POLY +S 3400,5200,3400,6500,200,*,UP,POLY +S 2400,6200,2400,6500,200,*,UP,POLY +S 1400,6200,1400,6500,200,*,UP,POLY +S 1400,2500,1400,2800,200,*,DOWN,POLY +S 2500,2400,2500,2800,200,*,DOWN,POLY +S 3500,2500,3500,3100,200,*,UP,POLY +S 3600,3000,4100,3000,400,*,LEFT,ALU1 +S 700,8000,2900,8000,300,*,RIGHT,ALU1 +S 3000,1800,3000,7000,300,*,UP,ALU1 +S 1600,7000,3000,7000,300,*,RIGHT,ALU1 +S 3300,5200,3900,5200,200,*,RIGHT,POLY +S 900,2800,1500,2800,200,*,LEFT,POLY +S 1000,2800,1000,6200,200,*,UP,POLY +S 5000,600,5000,2500,600,*,UP,NDIF +S 4000,5500,4000,9400,400,*,UP,PDIF +S 900,6800,900,8200,300,*,UP,ALU1 +S 5000,5500,5000,9400,600,*,UP,PDIF +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 2900,4000,4600,4000,200,*,RIGHT,POLY +S 4500,600,4500,2500,200,*,UP,NTRANS +S 3500,600,3500,2500,200,*,UP,NTRANS +S 1900,6500,1900,8500,400,*,UP,PDIF +S 2900,6500,2900,8500,400,*,UP,PDIF +S 3800,6500,3800,8500,400,*,UP,PDIF +S 4000,600,4000,2500,800,*,UP,NDIF +S 2000,600,2000,2500,600,*,UP,NDIF +S 3000,600,3000,2500,400,*,UP,NDIF +S 900,600,900,2500,400,*,UP,NDIF +S 900,6200,1500,6200,200,*,LEFT,POLY +S 1800,6200,2500,6200,200,*,LEFT,POLY +S 1800,2800,2600,2800,200,*,LEFT,POLY +S 2000,1800,2000,6200,300,*,UP,ALU1 +S 4000,1800,4000,8200,300,*,UP,ALU1 +S 1000,1800,1000,6200,300,*,UP,ALU1 +S 2400,6500,2400,8500,200,*,UP,PTRANS +S -500,7500,6500,7500,6000,*,RIGHT,NWELL +S -200,10000,6200,10000,400,*,RIGHT,NTIE +S -200,0,6200,0,400,*,RIGHT,PTIE +S 3400,6500,3400,8500,200,*,UP,PTRANS +S 1400,6500,1400,8500,200,*,UP,PTRANS +S 900,6500,900,8500,600,*,UP,PDIF +S 2500,600,2500,2500,200,*,UP,NTRANS +S 1400,600,1400,2500,200,*,UP,NTRANS +S -200,500,6200,500,1400,vss,RIGHT,CALU1 +S -200,9500,6200,9500,1400,vdd,RIGHT,CALU1 +S 5000,1800,5000,8200,300,q,UP,CALU1 +S 5000,1800,5000,8200,300,*,UP,ALU1 +S 4000,1800,4000,8200,300,i2,UP,CALU1 +S 2000,1800,2000,6200,300,i1,UP,CALU1 +S 1000,1800,1000,6200,300,i0,UP,CALU1 +B 3000,7000,200,200,CONT_TURN1,* +V 3800,5000,CONT_POLY,* +V 3700,3000,CONT_POLY,* +V 4000,9100,CONT_DIF_P,* +V 2900,8000,CONT_DIF_P,* +V 900,8000,CONT_DIF_P,* +V 900,7000,CONT_DIF_P,* +V 4000,900,CONT_DIF_N,* +V 900,900,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 2000,6000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 3000,2000,CONT_DIF_N,* +V 5000,8000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,6000,CONT_DIF_P,* +V 5000,2000,CONT_DIF_N,* +V 1900,7000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa22_x2.vbe b/pdks/symbolic/nsxlib2/cells/oa22_x2.vbe new file mode 100644 index 000000000..d2d267604 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 390; + CONSTANT tphh_i2_q : NATURAL := 438; + CONSTANT tpll_i2_q : NATURAL := 454; + CONSTANT tphh_i1_q : NATURAL := 488; + CONSTANT tpll_i1_q : NATURAL := 525; + CONSTANT tpll_i0_q : NATURAL := 555; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x2; + +ARCHITECTURE behaviour_data_flow OF oa22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa22_x4.ap b/pdks/symbolic/nsxlib2/cells/oa22_x4.ap new file mode 100644 index 000000000..d34695cde --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa22_x4.ap @@ -0,0 +1,123 @@ +V ALLIANCE : 6 +H oa22_x4,P,17/ 8/2024,100 +A 0,0,8000,10000 +R 4000,5000,ref_ref,i2_20 +R 4000,4000,ref_ref,i2_25 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 4000,2000,ref_ref,i2_10 +R 6000,8000,ref_ref,q_40 +R 6000,7000,ref_ref,q_35 +R 6000,6000,ref_ref,q_30 +R 6000,5000,ref_ref,q_25 +R 6000,4000,ref_ref,q_20 +R 6000,3000,ref_ref,q_15 +R 6000,2000,ref_ref,q_10 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 4000,3000,ref_ref,i2_15 +R 4000,6000,ref_ref,i2_30 +R 4000,7000,ref_ref,i2_35 +R 4000,8000,ref_ref,i2_40 +R 2000,2000,ref_ref,i1_10 +R 1000,2000,ref_ref,i0_10 +R 1000,3000,ref_ref,i0_15 +R 1000,4000,ref_ref,i0_20 +S 2800,6500,2800,8500,1000,*,UP,PDIF +S 2800,600,2800,2500,1000,*,UP,NDIF +S 1300,7000,3100,7000,300,*,RIGHT,ALU1 +S 2000,2500,2000,6600,200,*,UP,POLY +S 2000,6500,2000,8500,200,*,UP,PTRANS +S 1500,6500,1500,8500,400,*,UP,PDIF +S 2000,600,2000,2500,200,*,UP,NTRANS +S 1600,600,1600,2500,600,*,UP,NDIF +S 1000,2300,1000,6700,200,*,UP,POLY +S 1000,600,1000,2500,200,*,UP,NTRANS +S 500,600,500,2500,400,*,UP,NDIF +S 1000,6500,1000,8500,200,*,UP,PTRANS +S 500,6500,500,8500,600,*,UP,PDIF +S 3600,2400,3600,2900,200,*,UP,POLY +S 3500,5100,4000,5100,200,*,LEFT,POLY +S 3500,2900,4000,2900,200,*,RIGHT,POLY +S 7100,800,7100,2200,300,*,UP,ALU1 +S 7100,5800,7100,9200,300,*,UP,ALU1 +S 5400,5500,5400,9400,200,*,UP,PTRANS +S 4100,6500,4100,8500,600,*,UP,PDIF +S 4200,600,4200,2500,600,*,UP,NDIF +S 3600,5100,3600,6500,200,*,UP,POLY +S 5400,2500,5400,5500,200,*,UP,POLY +S 6600,2300,6600,5500,200,*,UP,POLY +S 600,8000,3200,8000,300,*,RIGHT,ALU1 +S 6600,600,6600,2500,200,*,UP,NTRANS +S 7100,600,7100,2500,600,*,UP,NDIF +S 6000,600,6000,2500,600,*,UP,NDIF +S 5400,600,5400,2500,200,*,UP,NTRANS +S 2900,4000,6700,4000,300,*,RIGHT,POLY +S 5000,5500,5000,9400,200,*,UP,PDIF +S 4600,5500,4600,9400,600,*,UP,PDIF +S 6600,5500,6600,9400,200,*,UP,PTRANS +S 6000,5500,6000,9400,600,*,UP,PDIF +S 3600,6500,3600,8500,200,*,UP,PTRANS +S -500,7500,8500,7500,6000,*,RIGHT,NWELL +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,0,8200,0,400,*,RIGHT,PTIE +S 7100,5500,7100,9400,600,*,UP,PDIF +S 4400,5500,4400,9400,600,*,UP,PDIF +S 3000,1800,3000,7200,300,*,UP,ALU1 +S 1000,1800,1000,6200,300,*,UP,ALU1 +S 4000,1800,4000,8200,300,*,UP,ALU1 +S 2000,1800,2000,6200,300,*,UP,ALU1 +S 6000,1800,6000,8200,300,*,UP,ALU1 +S 5000,600,5000,2500,200,*,UP,NDIF +S 4600,600,4600,2500,600,*,UP,NDIF +S 3600,600,3600,2500,200,*,UP,NTRANS +S -200,500,8200,500,1400,vss,RIGHT,CALU1 +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +S 6000,1800,6000,8200,300,q,UP,CALU1 +S 4000,1800,4000,8200,300,i2,UP,CALU1 +S 2000,1800,2000,6200,300,i1,UP,CALU1 +S 1000,1800,1000,6200,300,i0,UP,CALU1 +B 3000,6950,200,300,CONT_TURN1,* +V 2000,4000,CONT_POLY,* +V 1500,7000,CONT_DIF_P,* +V 500,900,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 3800,5000,CONT_POLY,* +V 3800,3000,CONT_POLY,* +V 7100,900,CONT_DIF_N,* +V 7100,2000,CONT_DIF_N,* +V 7100,6000,CONT_DIF_P,* +V 7100,7000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 6000,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 3000,4000,CONT_POLY,* +V 7100,9200,CONT_DIF_P,* +V 7100,8000,CONT_DIF_P,* +V 4600,9200,CONT_DIF_P,* +V 4600,900,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa22_x4.vbe b/pdks/symbolic/nsxlib2/cells/oa22_x4.vbe new file mode 100644 index 000000000..fa425e333 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 511; + CONSTANT tphh_i2_q : NATURAL := 523; + CONSTANT tpll_i2_q : NATURAL := 571; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tpll_i0_q : NATURAL := 677; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x4; + +ARCHITECTURE behaviour_data_flow OF oa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa2a22_x2.ap b/pdks/symbolic/nsxlib2/cells/oa2a22_x2.ap new file mode 100644 index 000000000..00dbb24a9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a22_x2.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H oa2a22_x2,P,17/ 8/2024,100 +A 0,0,9000,10000 +R 1000,4000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_15 +R 8000,8000,ref_ref,q_40 +R 8000,7000,ref_ref,q_35 +R 1000,5000,ref_ref,i0_25 +R 2000,4000,ref_ref,i1_20 +R 2000,5000,ref_ref,i1_25 +R 2000,6000,ref_ref,i1_30 +R 1000,6000,ref_ref,i0_30 +R 2000,3000,ref_ref,i1_15 +R 5000,2000,ref_ref,i3_10 +R 5000,3000,ref_ref,i3_15 +R 5000,4000,ref_ref,i3_20 +R 5000,5000,ref_ref,i3_25 +R 5000,6000,ref_ref,i3_30 +R 4000,6000,ref_ref,i2_30 +R 4000,5000,ref_ref,i2_25 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 4000,2000,ref_ref,i2_10 +R 2000,2000,ref_ref,i1_10 +R 8000,6000,ref_ref,q_30 +R 8000,4000,ref_ref,q_20 +R 8000,2000,ref_ref,q_10 +R 8000,3000,ref_ref,q_15 +R 8000,5000,ref_ref,q_25 +S 2900,1800,2900,7100,300,*,UP,ALU1 +S 1400,7000,7100,7000,300,*,RIGHT,ALU1 +S 400,7800,5600,7800,300,*,RIGHT,ALU1 +S 2700,6300,2700,8300,1200,*,UP,PDIF +S 2700,1500,2700,2500,1200,*,UP,NDIF +S 2000,1500,2000,2500,200,*,UP,NTRANS +S 1500,1500,1500,2500,400,*,UP,NDIF +S 2000,2500,2000,6300,200,*,UP,POLY +S 2000,6300,2000,8300,200,*,UP,PTRANS +S 1500,6300,1500,8300,400,*,UP,PDIF +S 1000,1500,1000,2500,200,*,UP,NTRANS +S 500,1500,500,2500,400,*,UP,NDIF +S 500,1200,500,2000,300,*,UP,ALU1 +S 1000,2400,1000,6300,200,*,UP,POLY +S 1000,6300,1000,8300,200,*,UP,PTRANS +S 500,6300,500,8300,400,*,UP,PDIF +S 3400,5700,3400,6500,200,*,UP,POLY +S 3400,2500,3400,5800,200,*,UP,POLY +S 4200,8300,4200,8800,500,*,DOWN,ALU1 +S 7100,3800,7100,7000,300,*,UP,ALU1 +S 6900,800,6900,2200,300,*,UP,ALU1 +S 6900,4000,7400,4000,500,*,RIGHT,POLY +S 3400,4000,4100,4000,500,*,RIGHT,POLY +S 5500,6300,5500,8300,400,*,UP,PDIF +S 6900,7800,6900,8800,300,*,UP,ALU1 +S 6900,600,6900,2500,400,*,UP,NDIF +S 7400,2500,7400,5500,200,*,UP,POLY +S 4600,6300,4600,8300,400,*,UP,PDIF +S 3900,6300,3900,8300,400,*,UP,PDIF +S 3700,1500,3700,2500,200,*,UP,NDIF +S 4500,1500,4500,2500,400,*,UP,NDIF +S 4100,2500,4100,2900,200,*,UP,POLY +S 4000,2900,5100,2900,200,*,RIGHT,POLY +S 4100,1500,4100,2500,200,*,UP,NTRANS +S 4900,700,4900,2500,600,*,UP,NDIF +S 4200,6300,4200,8700,600,*,UP,PDIF +S 3400,1500,3400,2500,200,*,UP,NTRANS +S 1000,2800,1000,6200,300,i0,UP,CALU1 +S 2000,1800,2000,6200,300,i1,UP,CALU1 +S 4000,1800,4000,6200,300,i2,UP,CALU1 +S 5000,1800,5000,6200,300,i3,UP,CALU1 +S 8000,1800,8000,8200,300,q,UP,CALU1 +S -200,9500,9200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,9200,500,1400,vss,RIGHT,CALU1 +S 8000,1800,8000,8200,300,*,UP,ALU1 +S 6800,5500,6800,9400,600,*,UP,PDIF +S 7400,5500,7400,9400,200,*,UP,PTRANS +S 8000,5500,8000,9400,600,*,UP,PDIF +S -500,7500,9500,7500,6000,*,RIGHT,NWELL +S -200,10000,9200,10000,400,*,RIGHT,NTIE +S -200,0,9200,0,400,*,RIGHT,PTIE +S 5000,1800,5000,6200,300,*,UP,ALU1 +S 7400,600,7400,2500,200,*,UP,NTRANS +S 8000,600,8000,2500,600,*,UP,NDIF +S 4000,1800,4000,6200,300,*,UP,ALU1 +S 2000,1800,2000,6200,300,*,UP,ALU1 +S 3400,6300,3400,8300,200,*,UP,PTRANS +S 5000,6300,5000,8300,200,*,UP,PTRANS +S 5000,2900,5000,6300,200,*,UP,POLY +S 1000,2800,1000,6200,300,*,UP,ALU1 +V 1500,7000,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 500,7800,CONT_DIF_P,* +B 7100,7000,200,200,CONT_TURN1,* +V 6900,1000,CONT_DIF_N,* +V 5500,7800,CONT_DIF_P,* +V 6900,9100,CONT_DIF_P,* +V 6900,8000,CONT_DIF_P,* +V 6900,2000,CONT_DIF_N,* +V 2900,2000,CONT_DIF_N,* +V 2900,7800,CONT_DIF_P,* +V 4900,900,CONT_DIF_N,* +V 4200,8500,CONT_DIF_P,* +V 7100,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 8000,2000,CONT_DIF_N,* +V 1000,4000,CONT_POLY,* +V 8000,8000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa2a22_x2.vbe b/pdks/symbolic/nsxlib2/cells/oa2a22_x2.vbe new file mode 100644 index 000000000..1c5c40883 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 403; + CONSTANT tpll_i2_q : NATURAL := 487; + CONSTANT tphh_i1_q : NATURAL := 495; + CONSTANT tpll_i3_q : NATURAL := 512; + CONSTANT tpll_i1_q : NATURAL := 534; + CONSTANT tphh_i3_q : NATURAL := 537; + CONSTANT tpll_i0_q : NATURAL := 564; + CONSTANT tphh_i2_q : NATURAL := 646; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa2a22_x4.ap b/pdks/symbolic/nsxlib2/cells/oa2a22_x4.ap new file mode 100644 index 000000000..fe1ee3f64 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a22_x4.ap @@ -0,0 +1,144 @@ +V ALLIANCE : 6 +H oa2a22_x4,P,17/ 8/2024,100 +A 0,0,10000,10000 +R 8000,2000,ref_ref,q_10 +R 8000,4000,ref_ref,q_20 +R 2000,3000,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_10 +R 4000,2000,ref_ref,i2_10 +R 4000,3000,ref_ref,i2_15 +R 4000,4000,ref_ref,i2_20 +R 4000,5000,ref_ref,i2_25 +R 8000,3000,ref_ref,q_15 +R 8000,5000,ref_ref,q_25 +R 1000,6000,ref_ref,i0_30 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 8000,6000,ref_ref,q_30 +R 8000,7000,ref_ref,q_35 +R 8000,8000,ref_ref,q_40 +R 1000,2000,ref_ref,i0_10 +R 1000,3000,ref_ref,i0_15 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 4000,6000,ref_ref,i2_30 +R 5000,6000,ref_ref,i3_30 +R 5000,5000,ref_ref,i3_25 +R 5000,4000,ref_ref,i3_20 +R 5000,3000,ref_ref,i3_15 +R 5000,2000,ref_ref,i3_10 +S 4300,6500,4300,8600,1000,*,UP,PDIF +S 2600,800,2600,1800,1000,*,DOWN,NDIF +S 3300,6500,3300,8600,200,*,UP,PTRANS +S 3300,800,3300,1800,200,*,UP,NTRANS +S 3300,1800,3300,6600,200,*,UP,POLY +S 2700,6500,2700,8600,800,*,DOWN,PDIF +S 500,7700,5600,7700,300,*,RIGHT,ALU1 +S 1400,7000,7000,7000,300,*,RIGHT,ALU1 +S 3900,2900,5100,2900,200,*,RIGHT,POLY +S 5000,2900,5000,6500,200,*,UP,POLY +S 5000,6500,5000,8600,200,*,UP,PTRANS +S 5500,6500,5500,8600,600,*,UP,PDIF +S 2000,1700,2000,6500,200,*,UP,POLY +S 2000,6500,2000,8600,200,*,UP,PTRANS +S 1500,6500,1500,8600,400,*,DOWN,PDIF +S 2000,800,2000,1800,200,*,UP,NTRANS +S 1500,800,1500,1800,400,*,DOWN,NDIF +S 1000,800,1000,1800,200,*,UP,NTRANS +S 500,800,500,1800,400,*,UP,NDIF +S 1000,1800,1000,6500,200,*,UP,POLY +S 1000,6500,1000,8600,200,*,UP,PTRANS +S 500,6500,500,8600,400,*,UP,PDIF +S 4100,8200,4100,8800,500,*,DOWN,ALU1 +S 7000,3900,7000,7000,300,*,UP,ALU1 +S 2700,1500,2700,7000,300,*,UP,ALU1 +S 6900,4100,7500,4100,500,*,RIGHT,POLY +S 7500,4100,8600,4100,400,*,RIGHT,POLY +S 6900,5500,6900,9400,600,*,UP,PDIF +S 6900,7800,6900,9200,300,*,UP,ALU1 +S 6900,600,6900,2500,600,*,UP,NDIF +S 6900,800,6900,2200,300,*,UP,ALU1 +S 7500,600,7500,2500,200,*,UP,NTRANS +S 7500,2500,7500,5500,200,*,UP,POLY +S 7500,5500,7500,9400,200,*,UP,PTRANS +S 9000,600,9000,2500,600,*,UP,NDIF +S 9000,800,9000,2200,300,*,UP,ALU1 +S 8500,600,8500,2500,200,*,UP,NTRANS +S 8500,2500,8500,5600,200,*,UP,POLY +S 8500,5500,8500,9400,200,*,UP,PTRANS +S 3600,800,3600,1800,200,*,UP,NDIF +S 4000,1800,4000,2900,200,*,UP,POLY +S 4000,800,4000,1800,200,*,UP,NTRANS +S 4500,800,4500,1800,600,*,UP,NDIF +S 3200,3900,4100,3900,200,*,LEFT,POLY +S 3700,6500,3700,8600,600,*,UP,PDIF +S 1000,1800,1000,6200,300,i0,UP,CALU1 +S 4000,1800,4000,6200,300,i2,UP,CALU1 +S 5000,1800,5000,6200,300,i3,UP,CALU1 +S 8000,1800,8000,8200,300,q,UP,CALU1 +S -200,9500,10200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,10200,500,1400,vss,RIGHT,CALU1 +S 8000,600,8000,2500,600,*,UP,NDIF +S 5000,1800,5000,6200,300,*,UP,ALU1 +S 4000,1800,4000,6200,300,*,UP,ALU1 +S 2000,1800,2000,6200,300,*,UP,ALU1 +S 1000,1800,1000,6200,300,*,UP,ALU1 +S -500,7500,10500,7500,6000,*,RIGHT,NWELL +S -200,10000,10200,10000,400,*,RIGHT,NTIE +S -200,0,10200,0,400,*,RIGHT,PTIE +S 8000,5500,8000,9400,600,*,UP,PDIF +S 9000,5800,9000,9200,300,*,UP,ALU1 +S 8000,1800,8000,8200,300,*,UP,ALU1 +S 9100,5500,9100,9400,600,*,UP,PDIF +S 2000,1800,2000,6200,300,i1,UP,CALU1 +V 5500,7700,CONT_DIF_P,* +V 1500,7000,CONT_DIF_P,* +V 500,1000,CONT_DIF_N,* +V 500,7700,CONT_DIF_P,* +V 9000,1000,CONT_DIF_N,* +V 6900,1000,CONT_DIF_N,* +V 6900,9000,CONT_DIF_P,* +V 9000,9000,CONT_DIF_P,* +V 4100,8400,CONT_DIF_P,* +B 7000,7000,200,200,CONT_TURN1,* +V 6900,8000,CONT_DIF_P,* +V 6900,2000,CONT_DIF_N,* +V 9000,2000,CONT_DIF_N,* +V 2700,1700,CONT_DIF_N,* +V 2700,7700,CONT_DIF_P,* +V 4600,1000,CONT_DIF_N,* +V 7000,4100,CONT_POLY,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 8000,2000,CONT_DIF_N,* +V 8000,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa2a22_x4.vbe b/pdks/symbolic/nsxlib2/cells/oa2a22_x4.vbe new file mode 100644 index 000000000..a233499c0 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 519; + CONSTANT tpll_i2_q : NATURAL := 596; + CONSTANT tpll_i3_q : NATURAL := 619; + CONSTANT tphh_i1_q : NATURAL := 624; + CONSTANT tphh_i3_q : NATURAL := 644; + CONSTANT tpll_i1_q : NATURAL := 669; + CONSTANT tpll_i0_q : NATURAL := 696; + CONSTANT tphh_i2_q : NATURAL := 763; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa2a2a23_x2.ap b/pdks/symbolic/nsxlib2/cells/oa2a2a23_x2.ap new file mode 100644 index 000000000..0ddc61d1b --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a2a23_x2.ap @@ -0,0 +1,156 @@ +V ALLIANCE : 6 +H oa2a2a23_x2,P,17/ 8/2024,100 +A 0,0,10000,10000 +R 7000,4000,ref_ref,i0_20 +R 9000,2000,ref_ref,q_10 +R 9000,3000,ref_ref,q_15 +R 9000,4000,ref_ref,q_20 +R 9000,5000,ref_ref,q_25 +R 9000,8000,ref_ref,q_40 +R 9000,7000,ref_ref,q_35 +R 9000,6000,ref_ref,q_30 +R 7000,3000,ref_ref,i0_15 +R 7000,6000,ref_ref,i0_30 +R 7000,5000,ref_ref,i0_25 +R 6000,3000,ref_ref,i1_15 +R 6000,6000,ref_ref,i1_30 +R 6000,4000,ref_ref,i1_20 +R 6000,5000,ref_ref,i1_25 +R 4000,6000,ref_ref,i2_30 +R 4000,4000,ref_ref,i2_20 +R 4000,3000,ref_ref,i2_15 +R 4000,5000,ref_ref,i2_25 +R 3000,6000,ref_ref,i3_30 +R 3000,3000,ref_ref,i3_15 +R 3000,4000,ref_ref,i3_20 +R 3000,5000,ref_ref,i3_25 +R 2000,6000,ref_ref,i4_30 +R 2000,5000,ref_ref,i4_25 +R 2000,3000,ref_ref,i4_15 +R 2000,4000,ref_ref,i4_20 +R 1000,6000,ref_ref,i5_30 +R 1000,5000,ref_ref,i5_25 +R 1000,4000,ref_ref,i5_20 +R 1000,3000,ref_ref,i5_15 +S 5400,5500,5400,9400,600,*,UP,PDIF +S 5400,600,5400,2500,600,*,UP,NDIF +S 6500,600,6500,2500,800,*,UP,NDIF +S 6500,7000,6500,8200,300,*,UP,ALU1 +S 6000,5500,6000,9400,200,*,UP,PTRANS +S 6400,5500,6400,9400,600,*,UP,PDIF +S 6000,2500,6000,5500,200,*,UP,POLY +S 6000,600,6000,2500,200,*,UP,NTRANS +S 7000,600,7000,2500,200,*,UP,NTRANS +S 7300,600,7300,2500,400,*,UP,NDIF +S 7000,2500,7000,5500,200,*,UP,POLY +S 7000,5500,7000,9400,200,*,UP,PTRANS +S 8400,2500,8400,5700,200,*,UP,POLY +S 3000,2400,3000,5500,200,*,UP,POLY +S 2000,2500,2000,5500,200,*,UP,POLY +S 1000,2500,1000,5500,200,*,UP,POLY +S 4000,2500,4000,5500,200,*,UP,POLY +S 8400,5500,8400,9400,200,*,UP,PTRANS +S 7900,6800,7900,8800,300,*,UP,ALU1 +S 8400,600,8400,2500,200,*,UP,NTRANS +S 400,2100,8200,2100,300,*,RIGHT,ALU1 +S 8100,2000,8100,4200,300,*,UP,ALU1 +S 300,2100,300,6900,300,*,UP,ALU1 +S -200,0,10200,0,400,*,RIGHT,PTIE +S -200,500,10200,500,1400,vss,RIGHT,CALU1 +S -500,7500,10500,7500,6000,*,RIGHT,NWELL +S -200,10000,10200,10000,400,*,RIGHT,NTIE +S -200,9500,10200,9500,1400,vdd,RIGHT,CALU1 +S 8900,600,8900,2500,600,*,UP,NDIF +S 7800,600,7800,2500,800,*,UP,NDIF +S 8900,5500,8900,9400,600,*,UP,PDIF +S 9000,1800,9000,8200,300,*,UP,ALU1 +S 9000,1800,9000,8200,300,q,UP,CALU1 +S 7700,5500,7700,9400,1000,*,UP,PDIF +S 7000,2800,7000,6200,300,i0,UP,CALU1 +S 7000,2800,7000,6200,300,*,UP,ALU1 +S 6000,2800,6000,6200,300,i1,UP,CALU1 +S 6000,2800,6000,6200,300,*,UP,ALU1 +S 5400,7800,5400,8800,300,*,UP,ALU1 +S 4400,5500,4400,9400,600,*,UP,PDIF +S 4500,600,4500,2500,400,*,UP,NDIF +S 3400,5500,3400,9400,600,*,UP,PDIF +S 3400,7000,6400,7000,300,*,RIGHT,ALU1 +S 4000,5500,4000,9400,200,*,UP,PTRANS +S 4000,2800,4000,6200,300,*,UP,ALU1 +S 4000,2800,4000,6200,300,i2,UP,CALU1 +S 4000,600,4000,2500,200,*,UP,NTRANS +S 3500,600,3500,2500,400,*,UP,NDIF +S 3000,2800,3000,6200,300,*,UP,ALU1 +S 3000,2800,3000,6200,300,i3,UP,CALU1 +S 3000,5500,3000,9400,200,*,UP,PTRANS +S 3000,600,3000,2500,200,*,UP,NTRANS +S 2500,600,2500,2500,400,*,UP,NDIF +S 2500,5500,2500,9400,600,*,UP,PDIF +S 400,8000,4700,8000,300,*,RIGHT,ALU1 +S 2000,2800,2000,6200,300,i4,UP,CALU1 +S 2000,2800,2000,6200,300,*,UP,ALU1 +S 400,6900,1600,6900,300,*,RIGHT,ALU1 +S 1500,5500,1500,9400,600,*,UP,PDIF +S 1500,600,1500,2500,400,*,UP,NDIF +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 2000,600,2000,2500,200,*,UP,NTRANS +S 1000,2800,1000,6200,300,*,UP,ALU1 +S 1000,2800,1000,6200,300,i5,UP,CALU1 +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 500,600,500,2500,400,*,UP,NDIF +S 1000,600,1000,2500,200,*,UP,NTRANS +S 500,5500,500,9400,600,*,UP,PDIF +B 6500,7000,200,200,CONT_TURN1,* +V 6500,8000,CONT_DIF_P,* +V 7900,9000,CONT_DIF_P,* +V 7000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 7900,8100,CONT_DIF_P,* +V 7900,7000,CONT_DIF_P,* +V 7900,1000,CONT_DIF_N,* +V 8200,4000,CONT_POLY,* +B 300,6900,200,200,CONT_TURN1,* +B 300,2100,200,200,CONT_TURN1,* +B 8100,2100,200,200,CONT_TURN1,* +V 9000,2000,CONT_DIF_N,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 5400,9100,CONT_DIF_P,* +V 5400,8000,CONT_DIF_P,* +V 5400,2000,CONT_DIF_N,* +V 4500,8000,CONT_DIF_P,* +V 4500,900,CONT_DIF_N,* +V 3500,7000,CONT_DIF_P,* +V 2500,2000,CONT_DIF_N,* +V 2500,8000,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +V 1500,6900,CONT_DIF_P,* +V 1000,4000,CONT_POLY,* +V 500,900,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa2a2a23_x2.vbe b/pdks/symbolic/nsxlib2/cells/oa2a2a23_x2.vbe new file mode 100644 index 000000000..189ed7159 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a2a23_x2.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT tphh_i5_q : NATURAL := 321; + CONSTANT tphh_i4_q : NATURAL := 402; + CONSTANT tphh_i2_q : NATURAL := 441; + CONSTANT tphh_i3_q : NATURAL := 540; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT tpll_i4_q : NATURAL := 591; + CONSTANT tpll_i3_q : NATURAL := 600; + CONSTANT tpll_i5_q : NATURAL := 636; + CONSTANT tpll_i2_q : NATURAL := 639; + CONSTANT tphh_i0_q : NATURAL := 653; + CONSTANT tphh_i1_q : NATURAL := 775; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x2" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa2a2a23_x4.ap b/pdks/symbolic/nsxlib2/cells/oa2a2a23_x4.ap new file mode 100644 index 000000000..a079ebaff --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a2a23_x4.ap @@ -0,0 +1,176 @@ +V ALLIANCE : 6 +H oa2a2a23_x4,P,17/ 8/2024,100 +A 0,0,11000,10000 +R 9000,4000,ref_ref,q_20 +R 9000,5000,ref_ref,q_25 +R 9000,2000,ref_ref,q_10 +R 9000,3000,ref_ref,q_15 +R 9000,6000,ref_ref,q_30 +R 9000,7000,ref_ref,q_35 +R 9000,8000,ref_ref,q_40 +R 7000,6000,ref_ref,i0_30 +R 7000,3000,ref_ref,i0_15 +R 7000,4000,ref_ref,i0_20 +R 7000,5000,ref_ref,i0_25 +R 6000,3000,ref_ref,i1_15 +R 6000,4000,ref_ref,i1_20 +R 6000,6000,ref_ref,i1_30 +R 6000,5000,ref_ref,i1_25 +R 3000,6000,ref_ref,i4_30 +R 3000,5000,ref_ref,i4_25 +R 3000,4000,ref_ref,i4_20 +R 3000,3000,ref_ref,i4_15 +R 4000,4000,ref_ref,i3_20 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +R 3000,7000,ref_ref,i4_35 +R 2000,4000,ref_ref,i5_20 +R 2000,5000,ref_ref,i5_25 +R 2000,6000,ref_ref,i5_30 +R 2000,3000,ref_ref,i5_15 +R 4000,3000,ref_ref,i3_15 +R 4000,5000,ref_ref,i3_25 +R 4000,6000,ref_ref,i3_30 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +S 4900,5500,4900,9400,600,*,UP,PDIF +S 9500,2400,9500,5600,200,*,UP,POLY +S 8500,2400,8500,5700,200,*,UP,POLY +S 7500,2500,7500,5700,200,*,UP,POLY +S 2500,2500,2500,5600,200,*,UP,POLY +S 4500,2500,4500,5500,200,*,UP,POLY +S 6500,2500,6500,5500,200,*,UP,POLY +S 5900,4000,6500,4000,500,*,RIGHT,POLY +S 8000,1800,8000,4200,300,*,UP,ALU1 +S 1200,1800,1200,7100,300,*,UP,ALU1 +S 8100,4000,8500,4000,500,*,RIGHT,POLY +S 8500,4000,9500,4000,200,*,RIGHT,POLY +S 6900,4000,7500,4000,500,*,RIGHT,POLY +S 4500,4000,5100,4000,500,*,RIGHT,POLY +S 3500,4000,4100,4000,500,*,RIGHT,POLY +S 2500,4000,2900,4000,500,*,RIGHT,POLY +S 1500,4000,2100,4000,500,*,RIGHT,POLY +S 900,8000,5100,8000,300,*,RIGHT,ALU1 +S 7000,600,7000,2500,400,*,UP,NDIF +S 8000,600,8000,2500,400,*,UP,NDIF +S 6900,5500,6900,9400,600,*,UP,PDIF +S 8000,5500,8000,9400,600,*,UP,PDIF +S 8000,6800,8000,9400,300,*,UP,ALU1 +S 6000,600,6000,2500,400,*,UP,NDIF +S 9500,600,9500,2500,200,*,UP,NTRANS +S 8500,600,8500,2500,200,*,UP,NTRANS +S 6500,600,6500,2500,200,*,UP,NTRANS +S 5000,600,5000,2500,400,*,UP,NDIF +S 9500,5500,9500,9400,200,*,UP,PTRANS +S 8500,5500,8500,9400,200,*,UP,PTRANS +S 7500,5500,7500,9400,200,*,UP,PTRANS +S 6500,5500,6500,9400,200,*,UP,PTRANS +S 4000,5500,4000,9400,400,*,UP,PDIF +S 2000,5500,2000,9400,400,*,UP,PDIF +S 1000,5500,1000,9400,400,*,UP,PDIF +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 4000,600,4000,2500,600,*,UP,NDIF +S 2100,600,2100,2500,600,*,UP,NDIF +S 3500,2500,3500,5500,200,*,UP,POLY +S 1500,2500,1500,5500,200,*,UP,POLY +S 4500,600,4500,2500,200,*,UP,NTRANS +S 1500,600,1500,2500,200,*,UP,NTRANS +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 2500,5500,2500,9400,200,*,UP,PTRANS +S -500,7500,11500,7500,6000,*,RIGHT,NWELL +S -200,0,11200,0,400,*,RIGHT,PTIE +S -200,500,11200,500,1400,vss,RIGHT,CALU1 +S -200,10000,11200,10000,400,*,RIGHT,NTIE +S -200,9500,11200,9500,1400,vdd,RIGHT,CALU1 +S 10100,5500,10100,9400,600,*,UP,PDIF +S 10000,6800,10000,9400,300,*,UP,ALU1 +S 9900,600,9900,2500,600,*,UP,NDIF +S 10000,400,10000,2200,300,*,UP,ALU1 +S 10100,600,10100,2500,600,*,UP,NDIF +S 9000,600,9000,2500,600,*,UP,NDIF +S 9000,5500,9000,9400,600,*,UP,PDIF +S 9000,1800,9000,8200,300,*,UP,ALU1 +S 9000,1800,9000,8200,300,q,UP,CALU1 +S 1100,2000,8100,2000,300,*,RIGHT,ALU1 +S 3700,7000,7200,7000,300,*,RIGHT,ALU1 +S 7000,6800,7000,8200,300,*,UP,ALU1 +S 7000,2800,7000,6200,300,*,UP,ALU1 +S 7000,2800,7000,6200,300,i0,UP,CALU1 +S 7500,600,7500,2500,200,*,UP,NTRANS +S 6000,2800,6000,6200,300,*,UP,ALU1 +S 6000,2800,6000,6200,300,i1,UP,CALU1 +S 6000,5500,6000,9400,600,*,UP,PDIF +S 6000,7800,6000,9400,300,*,UP,ALU1 +S 1100,6900,2300,6900,300,*,RIGHT,ALU1 +S 2000,2800,2000,6200,300,i5,UP,CALU1 +S 3000,2800,3000,7200,300,i4,UP,CALU1 +S 4000,2800,4000,6200,300,i3,UP,CALU1 +S 5000,2800,5000,6200,300,i2,UP,CALU1 +S 3000,5500,3000,9400,600,*,UP,PDIF +S 3000,2800,3000,7200,300,*,UP,ALU1 +S 5000,2800,5000,6200,300,*,UP,ALU1 +S 4000,2800,4000,6200,300,*,UP,ALU1 +S 2000,2800,2000,6200,300,*,UP,ALU1 +S 3500,600,3500,2500,200,*,UP,NTRANS +S 3000,600,3000,2500,600,*,UP,NDIF +S 2500,600,2500,2500,200,*,UP,NTRANS +S 1000,600,1000,2500,600,*,UP,NDIF +V 6000,4000,CONT_POLY,* +B 8150,4000,500,400,CONT_TURN1,* +V 1900,4000,CONT_POLY,* +V 8200,4000,CONT_POLY,* +V 7200,4000,CONT_POLY,* +V 4800,4000,CONT_POLY,* +V 3800,4000,CONT_POLY,* +V 2800,4000,CONT_POLY,* +V 8000,9100,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,900,CONT_DIF_N,* +V 6000,2000,CONT_DIF_N,* +V 8000,8000,CONT_DIF_P,* +V 1000,900,CONT_DIF_N,* +V 5000,8000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 2000,6900,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,9200,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 10000,900,CONT_DIF_N,* +V 10000,2000,CONT_DIF_N,* +V 9000,2000,CONT_DIF_N,* +V 9000,6000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 6000,9200,CONT_DIF_P,* +V 3000,2000,CONT_DIF_N,* +V 5000,900,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa2a2a23_x4.vbe b/pdks/symbolic/nsxlib2/cells/oa2a2a23_x4.vbe new file mode 100644 index 000000000..c39f56f93 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT tphh_i5_q : NATURAL := 379; + CONSTANT tphh_i4_q : NATURAL := 464; + CONSTANT tphh_i2_q : NATURAL := 493; + CONSTANT tphh_i3_q : NATURAL := 594; + CONSTANT tpll_i1_q : NATURAL := 613; + CONSTANT tpll_i0_q : NATURAL := 648; + CONSTANT tpll_i4_q : NATURAL := 673; + CONSTANT tpll_i3_q : NATURAL := 677; + CONSTANT tphh_i0_q : NATURAL := 699; + CONSTANT tpll_i5_q : NATURAL := 714; + CONSTANT tpll_i2_q : NATURAL := 715; + CONSTANT tphh_i1_q : NATURAL := 822; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x4" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x2.ap b/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x2.ap new file mode 100644 index 000000000..6b3914bd1 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x2.ap @@ -0,0 +1,199 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x2,P,17/ 8/2024,100 +A 0,0,13000,10000 +R 12000,4000,ref_ref,q_20 +R 12000,5000,ref_ref,q_25 +R 10000,7000,ref_ref,i0_35 +R 10000,6000,ref_ref,i0_30 +R 10000,3000,ref_ref,i0_15 +R 10000,4000,ref_ref,i0_20 +R 10000,5000,ref_ref,i0_25 +R 9000,4000,ref_ref,i1_20 +R 9000,6000,ref_ref,i1_30 +R 9000,5000,ref_ref,i1_25 +R 9000,3000,ref_ref,i1_15 +R 7000,3000,ref_ref,i2_15 +R 7000,4000,ref_ref,i2_20 +R 7000,6000,ref_ref,i2_30 +R 7000,5000,ref_ref,i2_25 +R 6000,3000,ref_ref,i3_15 +R 6000,4000,ref_ref,i3_20 +R 6000,6000,ref_ref,i3_30 +R 6000,5000,ref_ref,i3_25 +R 5000,3000,ref_ref,i4_15 +R 5000,4000,ref_ref,i4_20 +R 5000,6000,ref_ref,i4_30 +R 5000,5000,ref_ref,i4_25 +R 4000,3000,ref_ref,i5_15 +R 4000,4000,ref_ref,i5_20 +R 4000,6000,ref_ref,i5_30 +R 4000,5000,ref_ref,i5_25 +R 3000,6000,ref_ref,i6_30 +R 3000,5000,ref_ref,i6_25 +R 3000,4000,ref_ref,i6_20 +R 3000,3000,ref_ref,i6_15 +R 1000,6000,ref_ref,i7_30 +R 1000,5000,ref_ref,i7_25 +R 1000,4000,ref_ref,i7_20 +R 1000,3000,ref_ref,i7_15 +R 1000,2000,ref_ref,i7_10 +S 8500,600,8500,2500,400,*,UP,NDIF +S 8400,5500,8400,9400,600,*,UP,PDIF +S 8500,7800,8500,9100,400,*,UP,ALU1 +S 1700,5500,1700,9400,800,*,UP,PDIF +S 1700,600,1700,2500,800,*,UP,NDIF +S 9300,7000,9300,8200,300,*,UP,ALU1 +S 9000,5500,9000,9400,200,*,UP,PTRANS +S 9600,5500,9600,9400,600,*,UP,PDIF +S 10000,5500,10000,9400,200,*,UP,PTRANS +S 10600,5500,10600,9400,600,*,UP,PDIF +S 9000,2500,9000,5500,200,*,DOWN,POLY +S 9000,600,9000,2500,200,*,UP,NTRANS +S 9500,600,9500,2500,600,*,UP,NDIF +S 10000,2400,10000,5500,200,*,DOWN,POLY +S 10000,600,10000,2500,200,*,UP,NTRANS +S 10600,600,10600,2500,600,*,UP,NDIF +S 1000,600,1000,2500,200,*,UP,NTRANS +S 500,600,500,2500,400,*,UP,NDIF +S 1000,2500,1000,5600,200,*,UP,POLY +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 500,5500,500,9400,400,*,UP,PDIF +S 500,6800,500,8200,300,*,UP,ALU1 +S 7000,2400,7000,5500,200,*,UP,POLY +S 6000,2500,6000,5500,200,*,UP,POLY +S 4000,2400,4000,5600,200,*,UP,POLY +S 5000,2400,5000,5500,200,*,UP,POLY +S 2100,4000,3100,4000,400,*,RIGHT,POLY +S 10800,7400,10800,8900,400,*,UP,ALU1 +S 6200,7000,9300,7000,300,*,RIGHT,ALU1 +S 11200,2000,11200,4200,300,*,UP,ALU1 +S 1700,2000,11200,2000,300,*,RIGHT,ALU1 +S 1700,2000,1700,7200,300,*,UP,ALU1 +S 3500,600,3500,2500,400,*,UP,NDIF +S 7400,600,7400,2500,600,*,UP,NDIF +S 11100,4000,11500,4000,500,*,RIGHT,POLY +S -500,7500,13500,7500,6000,*,RIGHT,NWELL +S -200,10000,13200,10000,400,*,RIGHT,NTIE +S -200,9500,13200,9500,1400,vdd,RIGHT,CALU1 +S -200,0,13200,0,400,*,RIGHT,PTIE +S -200,500,13200,500,1400,vss,RIGHT,CALU1 +S 10900,5500,10900,9400,600,*,UP,PDIF +S 11000,600,11000,2500,600,*,UP,NDIF +S 11500,600,11500,2500,200,*,UP,NTRANS +S 11900,600,11900,2500,600,*,UP,NDIF +S 11500,2500,11500,5500,200,*,UP,POLY +S 11500,5500,11500,9400,200,*,UP,PTRANS +S 12000,5500,12000,9400,600,*,UP,PDIF +S 12000,1800,12000,3700,300,*,UP,ALU1 +S 12000,3700,12000,8200,300,*,UP,ALU1 +S 12000,3700,12000,8200,300,q,UP,CALU1 +S 7500,5500,7500,9400,400,*,UP,PDIF +S 5500,6800,5500,8200,300,*,UP,ALU1 +S 3500,5500,3500,9400,400,*,UP,PDIF +S 2600,600,2600,2500,600,*,UP,NDIF +S 2200,600,2200,2500,200,*,UP,NTRANS +S 2200,2500,2200,5500,200,*,UP,POLY +S 2600,5500,2600,9400,600,*,UP,PDIF +S 500,8000,2900,8000,300,*,RIGHT,ALU1 +S 2700,6800,2700,8200,300,*,UP,ALU1 +S 2200,5500,2200,9400,200,*,UP,PTRANS +S 6400,600,6400,2500,600,*,UP,NDIF +S 4500,600,4500,2500,400,*,UP,NDIF +S 10000,2800,10000,7200,300,*,UP,ALU1 +S 10000,2800,10000,7200,300,i0,UP,CALU1 +S 9000,2800,9000,6200,300,i1,UP,CALU1 +S 9000,2800,9000,6200,300,*,UP,ALU1 +S 3400,8000,7600,8000,300,*,RIGHT,ALU1 +S 7000,2800,7000,6200,300,i2,UP,CALU1 +S 7000,2800,7000,6200,300,*,UP,ALU1 +S 7000,600,7000,2500,200,*,UP,NTRANS +S 7000,5500,7000,9400,200,*,UP,PTRANS +S 6400,5500,6400,9400,600,*,UP,PDIF +S 6000,2800,6000,6200,300,i3,UP,CALU1 +S 6000,2800,6000,6200,300,*,UP,ALU1 +S 6000,600,6000,2500,200,*,UP,NTRANS +S 6000,5500,6000,9400,200,*,UP,PTRANS +S 5400,600,5400,2500,600,*,UP,NDIF +S 5400,5500,5400,9400,600,*,UP,PDIF +S 5000,2800,5000,6200,300,i4,UP,CALU1 +S 5000,2800,5000,6200,300,*,UP,ALU1 +S 5000,600,5000,2500,200,*,UP,NTRANS +S 5000,5500,5000,9400,200,*,UP,PTRANS +S 2700,7000,4600,7000,300,*,RIGHT,ALU1 +S 4400,5500,4400,9400,600,*,UP,PDIF +S 4000,2800,4000,6200,300,i5,UP,CALU1 +S 4000,2800,4000,6200,300,*,UP,ALU1 +S 4000,600,4000,2500,200,*,UP,NTRANS +S 4000,5500,4000,9400,200,*,UP,PTRANS +S 3000,2800,3000,6200,300,*,UP,ALU1 +S 1000,1800,1000,6200,300,*,UP,ALU1 +S 1000,1800,1000,6200,300,i7,UP,CALU1 +S 3000,2800,3000,6200,300,i6,UP,CALU1 +V 8500,2000,CONT_DIF_N,* +V 8500,9100,CONT_DIF_P,* +V 8500,8000,CONT_DIF_P,* +B 9450,8000,500,400,CONT_TURN1,* +V 9500,8000,CONT_DIF_P,* +V 10700,1000,CONT_DIF_N,* +V 500,1000,CONT_DIF_N,* +V 500,8000,CONT_DIF_P,* +V 500,7000,CONT_DIF_P,* +V 3500,1000,CONT_DIF_N,* +V 7500,1000,CONT_DIF_N,* +V 10000,4000,CONT_POLY,* +V 9000,4000,CONT_POLY,* +V 7000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 10800,8700,CONT_DIF_P,* +V 10800,7600,CONT_DIF_P,* +B 9300,7000,200,200,CONT_TURN1,* +B 11200,2000,200,200,CONT_TURN1,* +B 1700,2000,200,200,CONT_TURN1,* +V 13000,0,CONT_BODY_P,* +V 13000,10000,CONT_BODY_N,* +V 11200,4000,CONT_POLY,* +V 12000,2000,CONT_DIF_N,* +V 12000,8000,CONT_DIF_P,* +V 12000,7000,CONT_DIF_P,* +V 12000,6000,CONT_DIF_P,* +V 7500,8000,CONT_DIF_P,* +V 6500,7000,CONT_DIF_P,* +V 5500,8000,CONT_DIF_P,* +V 5500,7000,CONT_DIF_P,* +V 4500,7000,CONT_DIF_P,* +V 3500,8000,CONT_DIF_P,* +V 2700,2000,CONT_DIF_N,* +V 2700,7000,CONT_DIF_P,* +V 2700,8000,CONT_DIF_P,* +V 5500,2000,CONT_DIF_N,* +V 1700,7000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x2.vbe b/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x2.vbe new file mode 100644 index 000000000..39a24492c --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x2.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rdown_i7_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT rup_i7_q : NATURAL := 1790; + CONSTANT tphh_i7_q : NATURAL := 346; + CONSTANT tphh_i6_q : NATURAL := 426; + CONSTANT tphh_i5_q : NATURAL := 467; + CONSTANT tphh_i4_q : NATURAL := 565; + CONSTANT tphh_i2_q : NATURAL := 682; + CONSTANT tpll_i6_q : NATURAL := 748; + CONSTANT tpll_i1_q : NATURAL := 753; + CONSTANT tphh_i0_q : NATURAL := 780; + CONSTANT tpll_i0_q : NATURAL := 797; + CONSTANT tpll_i7_q : NATURAL := 800; + CONSTANT tphh_i3_q : NATURAL := 803; + CONSTANT tpll_i3_q : NATURAL := 810; + CONSTANT tpll_i4_q : NATURAL := 813; + CONSTANT tpll_i2_q : NATURAL := 856; + CONSTANT tpll_i5_q : NATURAL := 861; + CONSTANT tphh_i1_q : NATURAL := 909; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x2" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1500 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x4.ap b/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x4.ap new file mode 100644 index 000000000..55231a8fc --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x4.ap @@ -0,0 +1,216 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x4,P,17/ 8/2024,100 +A 0,0,13000,10000 +R 5000,4000,ref_ref,i4_20 +R 2000,6000,ref_ref,i6_30 +R 2000,4000,ref_ref,i6_20 +R 2000,3000,ref_ref,i6_15 +R 2000,5000,ref_ref,i6_25 +R 12000,3000,ref_ref,q_15 +R 12000,4000,ref_ref,q_20 +R 12000,5000,ref_ref,q_25 +R 10000,3000,ref_ref,i0_15 +R 10000,4000,ref_ref,i0_20 +R 10000,6000,ref_ref,i0_30 +R 10000,5000,ref_ref,i0_25 +R 9000,3000,ref_ref,i1_15 +R 9000,4000,ref_ref,i1_20 +R 9000,6000,ref_ref,i1_30 +R 9000,5000,ref_ref,i1_25 +R 7000,3000,ref_ref,i2_15 +R 7000,4000,ref_ref,i2_20 +R 7000,6000,ref_ref,i2_30 +R 7000,5000,ref_ref,i2_25 +R 6000,3000,ref_ref,i3_15 +R 6000,4000,ref_ref,i3_20 +R 6000,6000,ref_ref,i3_30 +R 6000,5000,ref_ref,i3_25 +R 5000,3000,ref_ref,i4_15 +R 5000,5000,ref_ref,i4_25 +R 5000,6000,ref_ref,i4_30 +R 4000,6000,ref_ref,i5_30 +R 4000,3000,ref_ref,i5_15 +R 4000,4000,ref_ref,i5_20 +R 4000,5000,ref_ref,i5_25 +R 1000,6000,ref_ref,i7_30 +R 1000,5000,ref_ref,i7_25 +R 1000,4000,ref_ref,i7_20 +R 1000,3000,ref_ref,i7_15 +R 1000,2000,ref_ref,i7_10 +S 9400,600,9400,2800,600,*,UP,NDIF +S 8500,7800,8500,9400,300,*,UP,ALU1 +S 8500,5500,8500,9400,400,*,UP,PDIF +S 8500,600,8500,2800,400,*,UP,NDIF +S 9000,2600,9000,5500,200,*,UP,POLY +S 9000,600,9000,2800,200,*,UP,NTRANS +S 6400,7000,9600,7000,300,*,RIGHT,ALU1 +S 9000,5500,9000,9400,200,*,UP,PTRANS +S 9500,5500,9500,9400,600,*,UP,PDIF +S 9500,7000,9500,8200,300,*,UP,ALU1 +S 10000,5500,10000,9400,200,*,UP,PTRANS +S 10500,5500,10500,9400,600,*,UP,PDIF +S 10500,7800,10500,9400,300,*,UP,ALU1 +S 10000,2600,10000,5500,200,*,UP,POLY +S 10000,600,10000,2800,200,*,UP,NTRANS +S 10500,600,10500,2800,400,*,DOWN,NDIF +S 11000,600,11000,2800,200,*,UP,NTRANS +S 11000,2700,11000,5500,200,*,UP,POLY +S 11000,5500,11000,9400,200,*,UP,PTRANS +S 11500,5500,11500,9400,600,*,UP,PDIF +S 11500,5800,11500,8200,300,*,UP,ALU1 +S 12000,4000,12000,5500,200,*,DOWN,POLY +S 12000,5500,12000,9400,200,*,UP,PTRANS +S 12500,6800,12500,9400,300,*,UP,ALU1 +S 12400,5500,12400,9400,600,*,UP,PDIF +S 11300,600,11300,2800,400,*,DOWN,NDIF +S 6000,2500,6000,5500,200,*,UP,POLY +S 2000,2500,2000,5500,200,*,UP,POLY +S 1000,2500,1000,5600,200,*,UP,POLY +S 4000,2400,4000,5500,200,*,UP,POLY +S 5000,2400,5000,5500,200,*,UP,POLY +S 7000,2500,7000,5500,200,*,UP,POLY +S 12000,2700,12000,4100,200,*,UP,POLY +S 11700,600,11700,2800,400,*,UP,NDIF +S 12000,600,12000,2800,200,*,UP,NTRANS +S 12500,600,12500,2800,400,*,DOWN,NDIF +S 2700,1700,10900,1700,300,*,RIGHT,ALU1 +S 10800,1700,10800,4200,300,*,UP,ALU1 +S 2700,1700,2700,7200,300,*,UP,ALU1 +S 1400,7100,2800,7100,300,*,LEFT,ALU1 +S -200,0,13200,0,400,*,RIGHT,PTIE +S -200,500,13200,500,1400,vss,RIGHT,CALU1 +S -500,7500,13500,7500,6000,*,RIGHT,NWELL +S -200,10000,13200,10000,400,*,RIGHT,NTIE +S -200,9500,13200,9500,1400,vdd,RIGHT,CALU1 +S 7400,5500,7400,9400,600,*,UP,PDIF +S 7500,600,7500,2500,400,*,UP,NDIF +S 7000,600,7000,2500,200,*,UP,NTRANS +S 7000,5500,7000,9400,200,*,UP,PTRANS +S 6500,600,6500,2500,400,*,UP,NDIF +S 6500,5500,6500,9400,600,*,UP,PDIF +S 5600,600,5600,2500,600,*,UP,NDIF +S 6000,600,6000,2500,200,*,UP,NTRANS +S 6000,5500,6000,9400,200,*,UP,PTRANS +S 5400,8000,7600,8000,300,*,RIGHT,ALU1 +S 5600,5500,5600,9400,400,*,UP,PDIF +S 5500,6800,5500,8200,300,*,UP,ALU1 +S 2600,600,2600,2500,600,*,UP,NDIF +S 5000,600,5000,2500,200,*,UP,NTRANS +S 5000,5500,5000,9400,200,*,UP,PTRANS +S 4600,5500,4600,9400,400,*,UP,PDIF +S 4500,600,4500,2500,400,*,UP,NDIF +S 4000,600,4000,2500,200,*,UP,NTRANS +S 3500,600,3500,2500,400,*,UP,NDIF +S 4000,5500,4000,9400,200,*,UP,PTRANS +S 3500,5500,3500,9400,400,*,UP,PDIF +S 3500,7000,5500,7000,300,*,RIGHT,ALU1 +S 2300,8000,4600,8000,300,*,RIGHT,ALU1 +S 2000,2800,2000,6200,300,*,UP,ALU1 +S 2000,2800,2000,6200,300,i6,UP,CALU1 +S 1500,600,1500,2500,400,*,UP,NDIF +S 2000,600,2000,2500,200,*,UP,NTRANS +S 600,600,600,2500,400,*,UP,NDIF +S 1000,600,1000,2500,200,*,UP,NTRANS +S 2400,5500,2400,9400,600,*,UP,PDIF +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 1500,5500,1500,9400,400,*,UP,PDIF +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 500,5500,500,9400,400,*,UP,PDIF +S 500,6800,500,8200,300,*,UP,ALU1 +S 300,8000,2600,8000,300,*,RIGHT,ALU1 +S 12000,1800,12000,3000,300,*,UP,ALU1 +S 12000,2800,12000,6200,300,*,UP,ALU1 +S 10900,4000,12200,4000,400,*,RIGHT,POLY +S 12000,2800,12000,6100,300,q,UP,CALU1 +S 4500,5500,4500,9400,400,*,UP,PDIF +S 10000,2800,10000,6200,300,*,UP,ALU1 +S 10000,2800,10000,6200,300,i0,UP,CALU1 +S 9000,2800,9000,6200,300,i1,UP,CALU1 +S 9000,2800,9000,6200,300,*,UP,ALU1 +S 7000,2800,7000,6200,300,i2,UP,CALU1 +S 7000,2800,7000,6200,300,*,UP,ALU1 +S 6000,2800,6000,6200,300,i3,UP,CALU1 +S 6000,2800,6000,6200,300,*,UP,ALU1 +S 5400,5500,5400,9400,600,*,UP,PDIF +S 5000,2800,5000,6200,300,i4,UP,CALU1 +S 5000,2800,5000,6200,300,*,UP,ALU1 +S 4000,2800,4000,6200,300,i5,UP,CALU1 +S 4000,2800,4000,6200,300,*,UP,ALU1 +S 1000,1800,1000,6200,300,*,UP,ALU1 +S 5400,5500,5400,9400,600,*,UP,PDIF +S 1000,1800,1000,6200,300,i7,UP,CALU1 +V 8500,9100,CONT_DIF_P,* +V 8500,8000,CONT_DIF_P,* +V 8500,1700,CONT_DIF_N,* +B 9500,7000,200,200,CONT_TURN1,* +V 9500,8000,CONT_DIF_P,* +V 10500,9100,CONT_DIF_P,* +V 10500,8000,CONT_DIF_P,* +V 10500,900,CONT_DIF_N,* +V 11500,6000,CONT_DIF_P,* +V 11500,7000,CONT_DIF_P,* +V 11500,8000,CONT_DIF_P,* +V 12500,9100,CONT_DIF_P,* +V 12500,8000,CONT_DIF_P,* +V 12500,7000,CONT_DIF_P,* +B 11600,5950,1000,500,CONT_TURN1,* +B 11700,2050,800,500,CONT_TURN1,* +V 11500,2000,CONT_DIF_N,* +V 12500,900,CONT_DIF_N,* +B 10750,4000,300,400,CONT_TURN1,* +B 10800,1700,200,200,CONT_TURN1,* +V 10000,4000,CONT_POLY,* +V 9000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 7000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 2700,1700,CONT_DIF_N,* +B 2700,1700,200,200,CONT_TURN1,* +B 2700,7100,200,200,CONT_TURN1,* +V 1500,7100,CONT_DIF_P,* +V 500,900,CONT_DIF_N,* +V 7500,8000,CONT_DIF_P,* +V 7500,900,CONT_DIF_N,* +V 6500,7000,CONT_DIF_P,* +V 5500,1700,CONT_DIF_N,* +V 5500,8000,CONT_DIF_P,* +V 5500,7000,CONT_DIF_P,* +V 4500,8000,CONT_DIF_P,* +V 3500,900,CONT_DIF_N,* +V 3500,7000,CONT_DIF_P,* +V 2500,8000,CONT_DIF_P,* +V 500,7000,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 10800,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +V 13000,0,CONT_BODY_P,* +V 13000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x4.vbe b/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x4.vbe new file mode 100644 index 000000000..33d168440 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2a2a2a24_x4.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rdown_i7_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT rup_i7_q : NATURAL := 890; + CONSTANT tphh_i7_q : NATURAL := 399; + CONSTANT tphh_i6_q : NATURAL := 487; + CONSTANT tphh_i5_q : NATURAL := 515; + CONSTANT tphh_i4_q : NATURAL := 619; + CONSTANT tphh_i2_q : NATURAL := 726; + CONSTANT tphh_i0_q : NATURAL := 823; + CONSTANT tpll_i1_q : NATURAL := 835; + CONSTANT tpll_i6_q : NATURAL := 845; + CONSTANT tphh_i3_q : NATURAL := 851; + CONSTANT tpll_i0_q : NATURAL := 879; + CONSTANT tpll_i3_q : NATURAL := 895; + CONSTANT tpll_i7_q : NATURAL := 895; + CONSTANT tpll_i4_q : NATURAL := 902; + CONSTANT tpll_i2_q : NATURAL := 940; + CONSTANT tpll_i5_q : NATURAL := 949; + CONSTANT tphh_i1_q : NATURAL := 955; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x4" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1600 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa2ao222_x2.ap b/pdks/symbolic/nsxlib2/cells/oa2ao222_x2.ap new file mode 100644 index 000000000..c3c339436 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2ao222_x2.ap @@ -0,0 +1,149 @@ +V ALLIANCE : 6 +H oa2ao222_x2,P,17/ 8/2024,100 +A 0,0,9000,10000 +R 8000,2000,ref_ref,q_10 +R 8000,3000,ref_ref,q_15 +R 8000,4000,ref_ref,q_20 +R 8000,5000,ref_ref,q_25 +R 8000,6000,ref_ref,q_30 +R 8000,7000,ref_ref,q_35 +R 8000,8000,ref_ref,q_40 +R 5000,5000,ref_ref,i2_25 +R 1000,4000,ref_ref,i0_20 +R 1000,5000,ref_ref,i0_25 +R 1000,6000,ref_ref,i0_30 +R 1000,7000,ref_ref,i0_35 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +R 1000,3000,ref_ref,i0_15 +R 3000,6000,ref_ref,i4_30 +R 3000,5000,ref_ref,i4_25 +R 3000,7000,ref_ref,i4_35 +R 6000,6000,ref_ref,i3_30 +R 6000,5000,ref_ref,i3_25 +R 6000,4000,ref_ref,i3_20 +R 6000,3000,ref_ref,i3_15 +R 5000,6000,ref_ref,i2_30 +R 1000,2000,ref_ref,i0_10 +R 3000,4000,ref_ref,i4_20 +S 900,5500,900,9400,800,*,UP,PDIF +S 900,700,900,3500,600,*,UP,NDIF +S 6100,5500,6100,9400,600,*,UP,PDIF +S 2800,3000,4000,3000,300,*,RIGHT,ALU1 +S 3800,2000,6200,2000,300,*,RIGHT,ALU1 +S 3900,7000,7300,7000,300,*,RIGHT,ALU1 +S 5100,700,5100,3500,600,*,UP,NDIF +S 5500,700,5500,3500,200,*,UP,NTRANS +S 5500,3400,5500,4000,200,*,UP,POLY +S 5000,5500,5000,9400,800,*,UP,PDIF +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 5500,4000,5500,5500,200,*,UP,POLY +S 4500,4700,4500,5500,200,*,DOWN,POLY +S 4500,700,4500,3500,200,*,UP,NTRANS +S 4500,3400,4500,4900,200,*,UP,POLY +S 4400,4000,5000,4000,500,*,RIGHT,POLY +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 2000,700,2000,3500,600,*,UP,NDIF +S 1500,700,1500,3500,200,*,UP,NTRANS +S 1100,4000,1500,4000,500,*,LEFT,POLY +S 1500,3400,1500,5500,200,*,UP,POLY +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 2000,5500,2000,9400,600,*,UP,PDIF +S 3000,5500,3000,9400,400,*,UP,PDIF +S 2100,4000,2500,4000,500,*,LEFT,POLY +S 2500,3500,2500,5700,200,*,UP,POLY +S 2500,700,2500,3500,200,*,UP,NTRANS +S 3000,700,3000,3500,600,*,UP,NDIF +S 4000,700,4000,3500,600,*,UP,NDIF +S 3500,700,3500,3500,200,*,UP,NTRANS +S 3100,4000,3500,4000,500,*,LEFT,POLY +S 3500,3500,3500,5500,200,*,UP,POLY +S 4000,5500,4000,9400,600,*,UP,PDIF +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 7500,3500,7500,5500,200,*,UP,POLY +S 6000,4000,6500,4000,500,*,RIGHT,ALU1 +S 4000,3000,4000,7000,300,*,UP,ALU1 +S 7000,1200,7000,3100,300,*,UP,ALU1 +S 7300,4700,7300,7000,300,*,UP,ALU1 +S 7000,7900,7000,8800,300,*,UP,ALU1 +S 700,8000,6200,8000,300,*,RIGHT,ALU1 +S 5500,4000,6400,4000,200,*,RIGHT,POLY +S 6000,700,6000,3500,600,*,UP,NDIF +S 7000,5500,7000,9400,400,*,UP,PDIF +S 7000,700,7000,3500,400,*,UP,NDIF +S 7500,700,7500,3500,200,*,UP,NTRANS +S 7500,5500,7500,9400,200,*,UP,PTRANS +S -200,0,9200,0,400,*,RIGHT,PTIE +S -200,500,9200,500,1400,vss,RIGHT,CALU1 +S -500,7500,9500,7500,6000,*,RIGHT,NWELL +S -200,10000,9200,10000,400,*,RIGHT,NTIE +S -200,9500,9200,9500,1400,vdd,RIGHT,CALU1 +S 8000,700,8000,3500,600,*,UP,NDIF +S 8000,5500,8000,9400,400,*,UP,PDIF +S 8000,1800,8000,8200,300,q,UP,CALU1 +S 8000,1800,8000,8200,300,*,UP,ALU1 +S 5000,2800,5000,6200,300,*,UP,ALU1 +S 2000,2800,2000,7200,300,*,UP,ALU1 +S 3000,3800,3000,7200,300,*,UP,ALU1 +S 1000,1800,1000,7200,300,*,UP,ALU1 +S 6000,2800,6000,6200,300,*,UP,ALU1 +S 6000,2800,6000,6200,300,i3,UP,CALU1 +S 5000,2800,5000,6200,300,i2,UP,CALU1 +S 3000,3800,3000,7200,300,i4,UP,CALU1 +S 2000,2800,2000,7200,300,i1,UP,CALU1 +S 1000,1800,1000,7200,300,i0,UP,CALU1 +V 4900,4000,CONT_POLY,* +V 5000,1000,CONT_DIF_N,* +V 2100,4000,CONT_POLY,* +V 2000,9000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 3000,3000,CONT_DIF_N,* +V 4000,2000,CONT_DIF_N,* +V 3100,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +B 7300,7000,200,200,CONT_TURN1,* +B 4000,3000,200,200,CONT_TURN1,* +V 6100,8000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,5900,CONT_DIF_P,* +V 6400,4000,CONT_POLY,* +V 6100,2000,CONT_DIF_N,* +V 7000,2000,CONT_DIF_N,* +V 7000,3000,CONT_DIF_N,* +V 7000,9200,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 800,8000,CONT_DIF_P,* +V 800,1000,CONT_DIF_N,* +V 7300,4900,CONT_POLY,* +V 8000,2000,CONT_DIF_N,* +V 8000,3000,CONT_DIF_N,* +V 8000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa2ao222_x2.vbe b/pdks/symbolic/nsxlib2/cells/oa2ao222_x2.vbe new file mode 100644 index 000000000..2a96b29e2 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2ao222_x2.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT tpll_i4_q : NATURAL := 453; + CONSTANT tphh_i2_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 495; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphh_i3_q : NATURAL := 556; + CONSTANT tphh_i4_q : NATURAL := 558; + CONSTANT tpll_i3_q : NATURAL := 578; + CONSTANT tpll_i0_q : NATURAL := 581; + CONSTANT tphh_i1_q : NATURAL := 598; + CONSTANT tpll_i2_q : NATURAL := 604; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x2; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1200 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa2ao222_x4.ap b/pdks/symbolic/nsxlib2/cells/oa2ao222_x4.ap new file mode 100644 index 000000000..c7baf12a4 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2ao222_x4.ap @@ -0,0 +1,161 @@ +V ALLIANCE : 6 +H oa2ao222_x4,P,17/ 8/2024,100 +A 0,0,10000,10000 +R 8000,8000,ref_ref,q_40 +R 8000,7000,ref_ref,q_35 +R 8000,6000,ref_ref,q_30 +R 8000,5000,ref_ref,q_25 +R 8000,4000,ref_ref,q_20 +R 8000,3000,ref_ref,q_15 +R 8000,2000,ref_ref,q_10 +R 2000,7000,ref_ref,i1_35 +R 1000,7000,ref_ref,i0_35 +R 1000,6000,ref_ref,i0_30 +R 1000,5000,ref_ref,i0_25 +R 1000,4000,ref_ref,i0_20 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 3000,7000,ref_ref,i4_35 +R 3000,6000,ref_ref,i4_30 +R 3000,5000,ref_ref,i4_25 +R 3000,4000,ref_ref,i4_20 +R 5000,3000,ref_ref,i2_15 +R 5000,4000,ref_ref,i2_20 +R 5000,5000,ref_ref,i2_25 +R 5000,6000,ref_ref,i2_30 +R 6000,3000,ref_ref,i3_15 +R 6000,4000,ref_ref,i3_20 +R 6000,5000,ref_ref,i3_25 +R 6000,6000,ref_ref,i3_30 +R 1000,3000,ref_ref,i0_15 +S 5600,900,5600,2700,600,*,UP,NDIF +S -500,7500,10500,7500,6000,*,RIGHT,NWELL +S -200,0,10200,0,400,*,RIGHT,PTIE +S -200,500,10200,500,1400,vss,RIGHT,CALU1 +S -200,10000,10200,10000,400,*,RIGHT,NTIE +S -200,9500,10200,9500,1400,vdd,RIGHT,CALU1 +S 9100,1500,9100,3500,600,*,UP,NDIF +S 9000,400,9000,3200,300,*,UP,ALU1 +S 9100,5500,9100,9400,600,*,UP,PDIF +S 9000,5800,9000,9600,300,*,UP,ALU1 +S 8500,3500,8500,5500,200,*,UP,POLY +S 8500,5500,8500,9400,200,*,UP,PTRANS +S 7900,5500,7900,9400,600,*,UP,PDIF +S 8500,1500,8500,3500,200,*,UP,NTRANS +S 8000,1500,8000,3500,600,*,UP,NDIF +S 8000,1800,8000,8200,300,*,UP,ALU1 +S 8000,1800,8000,8200,300,q,UP,CALU1 +S 3500,7000,7000,7000,300,*,RIGHT,ALU1 +S 7500,3400,7500,5500,200,*,UP,POLY +S 7500,1500,7500,3500,200,*,UP,NTRANS +S 7000,1500,7000,3500,600,*,UP,NDIF +S 7000,400,7000,3200,300,*,UP,ALU1 +S 6700,5000,8500,5000,500,*,RIGHT,POLY +S 6800,4800,6800,7200,300,*,UP,ALU1 +S 7500,5500,7500,9400,200,*,UP,PTRANS +S 6900,5500,6900,9400,600,*,UP,PDIF +S 7000,7800,7000,9600,300,*,UP,ALU1 +S 4200,3200,4200,5500,200,*,UP,POLY +S 4000,2600,4000,3200,200,*,DOWN,POLY +S 3900,3200,4300,3200,200,*,LEFT,POLY +S 4900,4000,6200,4000,500,*,RIGHT,POLY +S 5000,2600,5000,4000,200,*,UP,POLY +S 5000,3800,5000,5500,200,*,UP,POLY +S 5000,5500,5000,9400,200,*,UP,PTRANS +S 5500,5500,5500,9400,600,*,UP,PDIF +S 4000,900,4000,2700,200,*,UP,NTRANS +S 3500,900,3500,2700,600,*,UP,NDIF +S 5000,900,5000,2700,200,*,UP,NTRANS +S 4400,900,4400,2700,600,*,UP,NDIF +S 3500,2000,5900,2000,300,*,RIGHT,ALU1 +S 3000,900,3000,2700,200,*,UP,NTRANS +S 2600,900,2600,2700,600,*,UP,NDIF +S 2500,1800,2500,2900,300,*,UP,ALU1 +S 3000,2700,3000,5600,200,*,UP,POLY +S 3000,5500,3000,9400,200,*,UP,PTRANS +S 2400,5500,2400,9400,600,*,UP,PDIF +S 2000,5500,2000,9400,200,*,UP,PTRANS +S 1600,5500,1600,9400,600,*,UP,PDIF +S 2000,2700,2000,5600,200,*,UP,POLY +S 2000,900,2000,2700,200,*,UP,NTRANS +S 1500,900,1500,2700,600,*,UP,NDIF +S 1000,2700,1000,5700,200,*,UP,POLY +S 1000,900,1000,2700,200,*,UP,NTRANS +S 500,900,500,2700,400,*,UP,NDIF +S 500,700,500,2300,300,*,UP,ALU1 +S 1000,5500,1000,9400,200,*,UP,PTRANS +S 500,5500,500,9400,400,*,UP,PDIF +S 400,8300,5800,8300,300,*,RIGHT,ALU1 +S 4200,4000,5200,4000,300,*,RIGHT,ALU1 +S 4700,5500,4700,9400,400,*,UP,PDIF +S 3600,5500,3600,9400,600,*,UP,PDIF +S 2500,2700,3900,2700,300,*,RIGHT,ALU1 +S 4200,5500,4200,9400,200,*,UP,PTRANS +S 3700,2500,3700,7800,300,*,UP,ALU1 +S 2000,3800,2000,7200,300,i1,UP,CALU1 +S 2000,3800,2000,7200,300,*,UP,ALU1 +S 1000,2800,1000,7200,300,i0,UP,CALU1 +S 1000,2800,1000,7200,300,*,UP,ALU1 +S 3000,3800,3000,7200,300,i4,UP,CALU1 +S 5000,2800,5000,6200,300,i2,UP,CALU1 +S 6000,2800,6000,6200,300,i3,UP,CALU1 +S 3000,3800,3000,7200,300,*,UP,ALU1 +S 5000,2800,5000,6200,300,*,UP,ALU1 +S 6000,2800,6000,6200,300,*,UP,ALU1 +V 7000,9000,CONT_DIF_P,* +V 9000,9000,CONT_DIF_P,* +V 9000,2000,CONT_DIF_N,* +V 9000,3000,CONT_DIF_N,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 8000,3000,CONT_DIF_N,* +V 8000,2000,CONT_DIF_N,* +V 7000,2000,CONT_DIF_N,* +V 7000,3000,CONT_DIF_N,* +V 6800,5000,CONT_POLY,* +V 7000,8000,CONT_DIF_P,* +V 5500,8300,CONT_DIF_P,* +V 3500,2000,CONT_DIF_N,* +V 4500,1300,CONT_DIF_N,* +V 2500,2000,CONT_DIF_N,* +V 2500,8300,CONT_DIF_P,* +V 1500,9100,CONT_DIF_P,* +V 500,2000,CONT_DIF_N,* +V 500,8300,CONT_DIF_P,* +V 4400,4000,CONT_POLY,* +B 4650,4000,900,400,CONT_TURN1,* +B 3700,7300,400,800,CONT_TURN1,* +V 5700,2000,CONT_DIF_N,* +V 3700,7600,CONT_DIF_P,* +V 2000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa2ao222_x4.vbe b/pdks/symbolic/nsxlib2/cells/oa2ao222_x4.vbe new file mode 100644 index 000000000..d8e7b2abf --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT tpll_i4_q : NATURAL := 529; + CONSTANT tphh_i2_q : NATURAL := 552; + CONSTANT tphh_i0_q : NATURAL := 553; + CONSTANT tpll_i1_q : NATURAL := 616; + CONSTANT tphh_i3_q : NATURAL := 640; + CONSTANT tphh_i4_q : NATURAL := 656; + CONSTANT tpll_i0_q : NATURAL := 657; + CONSTANT tpll_i3_q : NATURAL := 660; + CONSTANT tphh_i1_q : NATURAL := 662; + CONSTANT tpll_i2_q : NATURAL := 693; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa3ao322_x2.ap b/pdks/symbolic/nsxlib2/cells/oa3ao322_x2.ap new file mode 100644 index 000000000..a44773096 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa3ao322_x2.ap @@ -0,0 +1,180 @@ +V ALLIANCE : 6 +H oa3ao322_x2,P,17/ 8/2024,100 +A 0,0,11000,10000 +R 9000,7000,ref_ref,i4_35 +R 10000,3000,ref_ref,i5_15 +R 5000,4000,ref_ref,i2_20 +R 4000,7000,ref_ref,i1_35 +R 4000,6000,ref_ref,i1_30 +R 4000,5000,ref_ref,i1_25 +R 4000,4000,ref_ref,i1_20 +R 4000,3000,ref_ref,i1_15 +R 6000,7000,ref_ref,i6_35 +R 6000,6000,ref_ref,i6_30 +R 6000,5000,ref_ref,i6_25 +R 10000,6000,ref_ref,i5_30 +R 10000,5000,ref_ref,i5_25 +R 1000,7000,ref_ref,q_35 +R 1000,6000,ref_ref,q_30 +R 6000,4000,ref_ref,i6_20 +R 5000,7000,ref_ref,i2_35 +R 5000,6000,ref_ref,i2_30 +R 5000,5000,ref_ref,i2_25 +R 8000,5000,ref_ref,i3_25 +R 8000,4000,ref_ref,i3_20 +R 8000,3000,ref_ref,i3_15 +R 10000,4000,ref_ref,i5_20 +R 8000,7000,ref_ref,i3_35 +R 3000,7000,ref_ref,i0_35 +R 1000,8000,ref_ref,q_40 +R 1000,2000,ref_ref,q_10 +R 1000,3000,ref_ref,q_15 +R 1000,4000,ref_ref,q_20 +R 1000,5000,ref_ref,q_25 +R 10000,7000,ref_ref,i5_35 +R 3000,3000,ref_ref,i0_15 +R 3000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,i0_25 +R 3000,6000,ref_ref,i0_30 +R 8000,6000,ref_ref,i3_30 +R 9000,3000,ref_ref,i4_15 +R 9000,4000,ref_ref,i4_20 +R 9000,5000,ref_ref,i4_25 +R 9000,6000,ref_ref,i4_30 +S 3400,8000,10600,8000,300,*,RIGHT,ALU1 +S 7400,800,7400,2500,800,*,UP,NDIF +S 7400,5500,7400,8500,600,*,UP,PDIF +S 6400,2000,9600,2000,300,*,RIGHT,ALU1 +S 8000,800,8000,2500,200,*,UP,NTRANS +S 8500,800,8500,2500,600,*,UP,NDIF +S 8500,5500,8500,8500,600,*,UP,PDIF +S 8000,5500,8000,8500,200,*,UP,PTRANS +S 8000,2500,8000,5600,200,*,UP,POLY +S 9000,2400,9000,5500,200,i4,UP,POLY +S 9000,5500,9000,8500,200,*,UP,PTRANS +S 9000,800,9000,2500,200,*,UP,NTRANS +S 9500,800,9500,2500,400,*,UP,NDIF +S 10000,2400,10000,5500,200,i5,UP,POLY +S 10000,800,10000,2500,200,*,UP,NTRANS +S 10500,800,10500,2500,400,*,UP,NDIF +S 10500,1200,10500,2000,300,*,UP,ALU1 +S 10000,5500,10000,8500,200,*,UP,PTRANS +S 10500,5500,10500,8500,400,*,UP,PDIF +S 6000,3700,6000,6300,200,i6,UP,POLY +S 1500,3300,1500,5700,200,*,UP,POLY +S 3000,3200,3000,4200,200,*,UP,POLY +S 4000,3200,4000,6100,200,*,UP,POLY +S 5000,3300,5000,6100,200,i2,UP,POLY +S 6000,2900,6000,3900,200,*,UP,POLY +S 2000,7900,2000,8800,400,*,UP,ALU1 +S 6300,800,6300,2900,400,*,DOWN,NDIF +S 5300,1700,5300,3300,400,4,DOWN,NDIF +S 5700,800,5700,2900,400,4,UP,NDIF +S 7000,3000,7000,7100,300,*,UP,ALU1 +S 2000,2300,5500,2300,300,*,RIGHT,ALU1 +S 5500,2300,5500,3000,300,*,UP,ALU1 +S 5500,3000,7000,3000,300,*,RIGHT,ALU1 +S 2000,2300,2000,4100,300,*,UP,ALU1 +S 1500,4000,2100,4000,500,*,RIGHT,POLY +S 6900,5500,6900,8500,800,*,UP,PDIF +S 2500,6100,2500,9100,800,*,UP,PDIF +S 6700,800,6700,2500,1000,*,UP,NDIF +S 4500,1700,4500,3300,600,*,UP,NDIF +S 3500,1700,3500,3300,600,*,UP,NDIF +S 2500,1700,2500,3300,400,*,UP,NDIF +S 9400,5500,9400,8500,600,*,UP,PDIF +S 6400,6100,6400,9100,400,*,UP,PDIF +S 4500,6100,4500,9100,400,*,UP,PDIF +S 5500,6100,5500,9100,400,*,UP,PDIF +S 3500,6100,3500,9100,400,*,UP,PDIF +S 2000,800,2000,3300,600,*,UP,NDIF +S 8000,2800,8000,7200,300,i3,UP,CALU1 +S 6000,800,6000,2900,200,*,UP,NTRANS +S 6000,6100,6000,9100,200,*,UP,PTRANS +S 3000,6100,3000,9100,200,*,UP,PTRANS +S 4000,6100,4000,9100,200,*,UP,PTRANS +S 5000,6100,5000,9100,200,*,UP,PTRANS +S 5000,1700,5000,3300,200,*,UP,NTRANS +S 4000,1700,4000,3300,200,*,UP,NTRANS +S 2000,5500,2000,9400,400,*,UP,PDIF +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 1500,800,1500,3300,200,*,UP,NTRANS +S 5500,1700,5500,2900,600,*,UP,NDIF +S 3000,1700,3000,3300,200,*,UP,NTRANS +S 1000,800,1000,3300,600,*,UP,NDIF +S 1000,1800,1000,8200,300,q,UP,CALU1 +S -200,9500,11200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,11200,500,1400,vss,RIGHT,CALU1 +S -500,7500,11500,7500,6000,*,RIGHT,NWELL +S -200,10000,11200,10000,400,*,RIGHT,NTIE +S -200,0,11200,0,400,*,RIGHT,PTIE +S 3000,2800,3000,7200,300,*,UP,ALU1 +S 4000,2800,4000,7200,300,*,UP,ALU1 +S 9000,2800,9000,7200,300,*,UP,ALU1 +S 6000,3800,6000,7200,300,*,UP,ALU1 +S 10000,2800,10000,7200,300,*,UP,ALU1 +S 5000,3800,5000,7200,300,*,UP,ALU1 +S 8000,2800,8000,7200,300,*,UP,ALU1 +S 1000,1800,1000,8200,300,*,UP,ALU1 +S 3000,4000,3000,6100,200,*,UP,POLY +S 1000,5500,1000,9400,600,*,UP,PDIF +S 10000,2800,10000,7200,300,i5,UP,CALU1 +S 9000,2800,9000,7200,300,i4,UP,CALU1 +S 6000,3800,6000,7200,300,i6,UP,CALU1 +S 5000,3800,5000,7200,300,i2,UP,CALU1 +S 4000,2800,4000,7200,300,i1,UP,CALU1 +S 3000,2800,3000,7200,300,i0,UP,CALU1 +V 8500,1300,CONT_DIF_N,* +V 9500,2000,CONT_DIF_N,* +V 10500,2000,CONT_DIF_N,* +V 10500,8000,CONT_DIF_P,* +V 8000,4000,CONT_POLY,* +V 9000,4000,CONT_POLY,* +V 2000,9100,CONT_DIF_P,* +V 2000,1000,CONT_DIF_N,* +B 7000,3000,200,200,CONT_TURN1,* +B 5500,3000,200,200,CONT_TURN1,* +B 2000,2300,200,200,CONT_TURN1,* +V 5500,2300,CONT_DIF_N,* +V 6500,2000,CONT_DIF_N,* +V 7300,2000,CONT_DIF_N,* +V 5500,8000,CONT_DIF_P,* +V 3500,8000,CONT_DIF_P,* +V 4500,8900,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 3000,4000,CONT_POLY,* +V 4000,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 2000,4000,CONT_POLY,* +V 6000,4000,CONT_POLY,* +V 10000,4000,CONT_POLY,* +V 1000,3000,CONT_DIF_N,* +V 7000,7000,CONT_DIF_P,* +V 7000,6000,CONT_DIF_P,* +V 1000,6000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa3ao322_x2.vbe b/pdks/symbolic/nsxlib2/cells/oa3ao322_x2.vbe new file mode 100644 index 000000000..dc2a71887 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa3ao322_x2.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT tpll_i6_q : NATURAL := 540; + CONSTANT tphh_i3_q : NATURAL := 560; + CONSTANT tphh_i6_q : NATURAL := 563; + CONSTANT tphh_i0_q : NATURAL := 638; + CONSTANT tphh_i4_q : NATURAL := 649; + CONSTANT tpll_i2_q : NATURAL := 707; + CONSTANT tphh_i5_q : NATURAL := 734; + CONSTANT tpll_i5_q : NATURAL := 734; + CONSTANT tphh_i1_q : NATURAL := 735; + CONSTANT tpll_i4_q : NATURAL := 760; + CONSTANT tpll_i1_q : NATURAL := 764; + CONSTANT tpll_i3_q : NATURAL := 765; + CONSTANT tphh_i2_q : NATURAL := 806; + CONSTANT tpll_i0_q : NATURAL := 820; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x2; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1400 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/oa3ao322_x4.ap b/pdks/symbolic/nsxlib2/cells/oa3ao322_x4.ap new file mode 100644 index 000000000..cc8883a11 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa3ao322_x4.ap @@ -0,0 +1,204 @@ +V ALLIANCE : 6 +H oa3ao322_x4,P,17/ 8/2024,100 +A 0,0,12000,10000 +R 11000,7000,ref_ref,i5_35 +R 11000,6000,ref_ref,i5_30 +R 5000,6000,ref_ref,i1_30 +R 5000,5000,ref_ref,i1_25 +R 5000,4000,ref_ref,i1_20 +R 5000,3000,ref_ref,i1_15 +R 7000,7000,ref_ref,i6_35 +R 6000,6000,ref_ref,i2_30 +R 6000,7000,ref_ref,i2_35 +R 7000,4000,ref_ref,i6_20 +R 2000,2000,ref_ref,q_10 +R 2000,8000,ref_ref,q_40 +R 4000,7000,ref_ref,i0_35 +R 9000,7000,ref_ref,i3_35 +R 10000,7000,ref_ref,i4_35 +R 10000,6000,ref_ref,i4_30 +R 10000,5000,ref_ref,i4_25 +R 10000,4000,ref_ref,i4_20 +R 10000,3000,ref_ref,i4_15 +R 7000,6000,ref_ref,i6_30 +R 7000,5000,ref_ref,i6_25 +R 4000,3000,ref_ref,i0_15 +R 4000,4000,ref_ref,i0_20 +R 4000,5000,ref_ref,i0_25 +R 4000,6000,ref_ref,i0_30 +R 9000,6000,ref_ref,i3_30 +R 2000,6000,ref_ref,q_30 +R 2000,5000,ref_ref,q_25 +R 2000,4000,ref_ref,q_20 +R 2000,3000,ref_ref,q_15 +R 11000,5000,ref_ref,i5_25 +R 9000,3000,ref_ref,i3_15 +R 11000,4000,ref_ref,i5_20 +R 11000,3000,ref_ref,i5_15 +R 6000,5000,ref_ref,i2_25 +R 9000,5000,ref_ref,i3_25 +R 9000,4000,ref_ref,i3_20 +R 6000,4000,ref_ref,i2_20 +R 2000,7000,ref_ref,q_35 +R 5000,7000,ref_ref,i1_35 +S 8200,5500,8200,8500,800,*,UP,PDIF +S 11000,3800,11000,5500,200,i5,UP,POLY +S 10000,3900,10000,5500,200,i4,UP,POLY +S 9800,2300,9800,4200,200,*,UP,POLY +S 9000,3700,9000,5500,200,*,UP,POLY +S 9000,5500,9000,8500,200,*,UP,PTRANS +S 9500,5500,9500,8500,600,*,UP,PDIF +S 10000,5500,10000,8500,200,*,UP,PTRANS +S 10500,5500,10500,8500,600,*,UP,PDIF +S 11000,5500,11000,8500,200,*,UP,PTRANS +S 11500,5500,11500,8500,400,*,UP,PDIF +S 2900,800,2900,2800,200,*,UP,NDIF +S 10300,1500,10300,2500,600,*,UP,NDIF +S 7500,1400,7500,2800,400,*,UP,NDIF +S 6200,800,6200,2800,400,*,DOWN,NDIF +S 3100,800,3100,2800,200,*,UP,NDIF +S 2900,5500,2900,9400,400,*,UP,PDIF +S 6400,1400,6400,2800,800,*,UP,NDIF +S 8500,1400,8500,2800,400,*,UP,NDIF +S 8000,1400,8000,2800,200,*,UP,NTRANS +S 7000,1400,7000,2800,200,*,UP,NTRANS +S 11300,1500,11300,2500,400,*,UP,NDIF +S 10800,1500,10800,2500,200,*,UP,NTRANS +S 9800,1500,9800,2500,200,*,UP,NTRANS +S 9400,1500,9400,2500,600,*,UP,NDIF +S 3500,2400,3500,6600,200,*,UP,POLY +S 7000,2700,7000,5700,200,*,UP,POLY +S 8000,2800,8000,3900,200,*,UP,POLY +S 9000,600,9000,2800,600,*,UP,NDIF +S 2800,1900,2800,4200,300,*,UP,ALU1 +S 2800,1900,6300,1900,300,*,RIGHT,ALU1 +S 6300,1900,6300,3000,300,*,UP,ALU1 +S 6300,3000,8000,3000,300,*,RIGHT,ALU1 +S 1000,5900,1000,9200,300,*,UP,ALU1 +S 3000,6900,3000,9600,300,*,UP,ALU1 +S 3900,8000,11400,8000,300,*,RIGHT,ALU1 +S 8000,3000,8000,7100,300,*,UP,ALU1 +S 11300,400,11300,2100,300,*,UP,ALU1 +S 7400,2000,10400,2000,300,*,RIGHT,ALU1 +S 1000,600,1000,2100,300,*,UP,ALU1 +S 7600,5500,7600,8500,600,*,UP,PDIF +S 4500,4000,5100,4000,500,*,RIGHT,POLY +S 3500,4000,4100,4000,500,*,RIGHT,POLY +S 1400,4000,3100,4000,500,*,RIGHT,POLY +S 4100,6400,4100,9400,600,*,UP,PDIF +S 5500,2400,5500,3400,200,*,UP,POLY +S 5400,3400,6100,3400,200,*,RIGHT,POLY +S 6000,3400,6000,4100,200,*,UP,POLY +S 5900,800,5900,2400,200,*,UP,NDIF +S 4900,800,4900,2400,600,*,UP,NDIF +S 5500,800,5500,2400,200,*,UP,NTRANS +S 7900,3800,8900,3800,200,*,RIGHT,POLY +S 10800,2200,10800,4100,200,*,UP,POLY +S 6000,3800,6000,5500,200,i2,UP,POLY +S 6500,5500,6500,8500,400,*,UP,PDIF +S 7000,5500,7000,8500,200,*,UP,PTRANS +S 5600,5500,5600,8500,600,*,UP,PDIF +S 6000,5500,6000,8500,200,*,UP,PTRANS +S 5100,6400,5100,9400,600,*,UP,PDIF +S 4000,800,4000,2400,600,*,UP,NDIF +S 1500,2600,1500,5500,200,*,UP,POLY +S 2500,2600,2500,5500,200,*,UP,POLY +S 4500,2300,4500,6400,200,*,UP,POLY +S 4500,800,4500,2400,200,*,UP,NTRANS +S 3500,800,3500,2400,200,*,UP,NTRANS +S 1000,800,1000,2800,400,*,UP,NDIF +S 3000,6400,3000,9400,400,*,UP,PDIF +S 4500,6400,4500,9400,200,*,UP,PTRANS +S 3500,6400,3500,9400,200,*,UP,PTRANS +S 1500,800,1500,2800,200,*,UP,NTRANS +S 2000,800,2000,2800,600,*,UP,NDIF +S 2500,800,2500,2800,200,*,UP,NTRANS +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 900,5500,900,9400,600,*,UP,PDIF +S 4000,2800,4000,7200,300,*,UP,ALU1 +S 5000,2800,5000,7200,300,*,UP,ALU1 +S 10000,2800,10000,7200,300,*,UP,ALU1 +S 7000,3800,7000,7200,300,*,UP,ALU1 +S 11000,2800,11000,7200,300,*,UP,ALU1 +S 9000,2800,9000,7200,300,*,UP,ALU1 +S 2000,1800,2000,8200,300,*,UP,ALU1 +S 2000,5500,2000,9400,600,*,UP,PDIF +S -500,7500,12500,7500,6000,*,RIGHT,NWELL +S -200,10000,12200,10000,400,*,RIGHT,NTIE +S -200,0,12200,0,400,*,RIGHT,PTIE +S 6000,3800,6000,7200,300,*,UP,ALU1 +S -200,500,12200,500,1400,vss,RIGHT,CALU1 +S -200,9500,12200,9500,1400,vdd,RIGHT,CALU1 +S 6000,3700,6000,7200,300,i2,UP,CALU1 +S 7000,3700,7000,7200,300,i6,UP,CALU1 +S 11000,2800,11000,7200,300,i5,UP,CALU1 +S 10000,2800,10000,7200,300,i4,UP,CALU1 +S 9000,2800,9000,7200,300,i3,UP,CALU1 +S 5000,2800,5000,7200,300,i1,UP,CALU1 +S 4000,2800,4000,7200,300,i0,UP,CALU1 +S 2000,1800,2000,8200,300,q,UP,CALU1 +V 11500,8000,CONT_DIF_P,* +V 3000,9000,CONT_DIF_P,* +V 9000,4000,CONT_POLY,* +V 10000,4000,CONT_POLY,* +V 6300,1900,CONT_DIF_N,* +B 6300,3000,200,200,CONT_TURN1,* +B 6300,1900,200,200,CONT_TURN1,* +B 2800,1900,200,200,CONT_TURN1,* +B 8000,3000,200,200,CONT_TURN1,* +V 3000,8000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 4800,4000,CONT_POLY,* +V 3800,4000,CONT_POLY,* +V 2800,4000,CONT_POLY,* +V 11300,2000,CONT_DIF_N,* +V 10300,2000,CONT_DIF_N,* +V 7500,2000,CONT_DIF_N,* +V 6500,8000,CONT_DIF_P,* +V 5000,9100,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 2000,2000,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 3000,1000,CONT_DIF_N,* +V 9000,1000,CONT_DIF_N,* +V 1000,9200,CONT_DIF_P,* +V 6000,4000,CONT_POLY,* +V 2000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 11000,4000,CONT_POLY,* +V 7000,4000,CONT_POLY,* +V 1000,2000,CONT_DIF_N,* +V 1000,6000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/oa3ao322_x4.vbe b/pdks/symbolic/nsxlib2/cells/oa3ao322_x4.vbe new file mode 100644 index 000000000..6f1ad9762 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/oa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT tpll_i6_q : NATURAL := 651; + CONSTANT tphh_i3_q : NATURAL := 673; + CONSTANT tphh_i6_q : NATURAL := 684; + CONSTANT tphh_i0_q : NATURAL := 717; + CONSTANT tphh_i4_q : NATURAL := 758; + CONSTANT tphh_i1_q : NATURAL := 818; + CONSTANT tpll_i2_q : NATURAL := 834; + CONSTANT tphh_i5_q : NATURAL := 839; + CONSTANT tpll_i5_q : NATURAL := 865; + CONSTANT tpll_i1_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 894; + CONSTANT tpll_i4_q : NATURAL := 896; + CONSTANT tpll_i3_q : NATURAL := 898; + CONSTANT tpll_i0_q : NATURAL := 946; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1500 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/on12_x1.ap b/pdks/symbolic/nsxlib2/cells/on12_x1.ap new file mode 100644 index 000000000..34b384069 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/on12_x1.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 6 +H on12_x1,P,14/ 8/2024,100 +A 0,0,5000,10000 +R 3000,4000,ref_ref,q_20 +R 3000,3000,ref_ref,q_15 +R 2000,4000,ref_ref,i1_20 +R 2000,3000,ref_ref,i1_15 +R 4000,3000,ref_ref,i0_15 +R 4000,4000,ref_ref,i0_20 +R 3000,5000,ref_ref,q_25 +R 3000,6000,ref_ref,q_30 +R 4000,7000,ref_ref,i0_35 +R 4000,6000,ref_ref,i0_30 +R 4000,5000,ref_ref,i0_25 +R 4000,8000,ref_ref,i0_40 +R 3000,8000,ref_ref,q_40 +R 3000,7000,ref_ref,q_35 +R 2000,8000,ref_ref,i1_40 +R 2000,7000,ref_ref,i1_35 +R 2000,6000,ref_ref,i1_30 +R 2000,5000,ref_ref,i1_25 +R 3000,2000,ref_ref,q_10 +S 3500,3500,3500,6500,200,*,UP,POLY +S 2500,3500,2500,6500,200,*,UP,POLY +S 1500,6100,1500,6500,200,*,DOWN,POLY +S 1500,3500,1500,4100,200,*,UP,POLY +S 2000,800,2000,2100,300,*,UP,ALU1 +S 2900,2000,4000,2000,400,*,RIGHT,ALU1 +S 1600,6000,2100,6000,400,*,RIGHT,ALU1 +S 1600,4000,2100,4000,400,*,LEFT,ALU1 +S 4000,1500,4000,3500,400,*,UP,NDIF +S 3500,4000,4100,4000,500,*,RIGHT,POLY +S 1400,6100,1900,6100,200,*,LEFT,POLY +S 1400,3900,1900,3900,200,*,LEFT,POLY +S 3000,1500,3000,3500,400,*,UP,NDIF +S 2000,1500,2000,3500,400,*,UP,NDIF +S 1000,1500,1000,3500,400,*,UP,NDIF +S 2000,6500,2000,9300,400,*,UP,PDIF +S 4000,6500,4000,9300,400,*,UP,PDIF +S 1000,6500,1000,9300,400,*,UP,PDIF +S 2500,6500,2500,9300,200,*,UP,PTRANS +S 2500,1500,2500,3500,200,*,UP,NTRANS +S 1500,1500,1500,3500,200,*,UP,NTRANS +S 1500,6500,1500,9300,200,*,UP,PTRANS +S 1000,2800,1000,8200,300,*,UP,ALU1 +S 3500,6500,3500,9300,200,*,UP,PTRANS +S 3000,6500,3000,9300,600,*,UP,PDIF +S -200,9500,5200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,5200,500,1400,vss,RIGHT,CALU1 +S 800,5000,2500,5000,200,*,RIGHT,POLY +S 4000,2800,4000,8200,300,*,UP,ALU1 +S -500,7500,5500,7500,6000,*,RIGHT,NWELL +S -200,10000,5200,10000,400,*,RIGHT,NTIE +S -200,0,5200,0,400,*,RIGHT,PTIE +S 3500,1500,3500,3500,200,*,UP,NTRANS +S 2000,2800,2000,8200,300,*,UP,ALU1 +S 2000,2800,2000,8200,300,i1,UP,CALU1 +S 3000,1800,3000,8200,300,*,UP,ALU1 +S 3000,1800,3000,8200,300,q,UP,CALU1 +S 4000,2800,4000,8200,300,i0,UP,CALU1 +V 1700,6000,CONT_POLY,* +V 1700,4000,CONT_POLY,* +V 4000,9000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 2000,9000,CONT_DIF_P,* +V 1000,3000,CONT_DIF_N,* +V 1000,5000,CONT_POLY,* +V 1000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 4000,4000,CONT_POLY,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/on12_x1.vbe b/pdks/symbolic/nsxlib2/cells/on12_x1.vbe new file mode 100644 index 000000000..32688f423 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/on12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3720; + CONSTANT rup_i1_q : NATURAL := 3720; + CONSTANT tphl_i0_q : NATURAL := 111; + CONSTANT tplh_i0_q : NATURAL := 234; + CONSTANT tpll_i1_q : NATURAL := 291; + CONSTANT tphh_i1_q : NATURAL := 314; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x1; + +ARCHITECTURE behaviour_data_flow OF on12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x1" + SEVERITY WARNING; + q <= (not (i0) or i1) after 900 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/on12_x4.ap b/pdks/symbolic/nsxlib2/cells/on12_x4.ap new file mode 100644 index 000000000..e40ffb631 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/on12_x4.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H on12_x4,P,14/ 8/2024,100 +A 0,0,8000,10000 +R 5000,5000,ref_ref,i1_20 +R 5000,4000,ref_ref,i1_25 +R 2000,6000,ref_ref,i0_30 +R 2000,8000,ref_ref,i0_40 +R 2000,2000,ref_ref,i0_10 +R 6000,5000,ref_ref,q_25 +R 6000,4000,ref_ref,q_20 +R 6000,3000,ref_ref,q_15 +R 5000,2000,ref_ref,i1_10 +R 5000,8000,ref_ref,i1_40 +R 5000,7000,ref_ref,i1_35 +R 5000,6000,ref_ref,i1_30 +R 2000,7000,ref_ref,i0_35 +R 2000,3000,ref_ref,i0_15 +R 2000,4000,ref_ref,i0_20 +R 2000,5000,ref_ref,i0_25 +S 4300,5200,4300,5500,200,*,UP,POLY +S 4500,2400,4500,3200,200,*,UP,POLY +S 5000,4000,5000,6000,400,*,DOWN,ALU1 +S 1500,3000,2100,3000,500,*,LEFT,POLY +S 4600,3100,5100,3100,400,*,RIGHT,ALU1 +S 4000,1800,4000,6200,300,*,UP,ALU1 +S 3000,5800,3000,8200,300,*,UP,ALU1 +S 2800,6000,4200,6000,300,*,RIGHT,ALU1 +S 4200,5200,5000,5200,200,*,LEFT,POLY +S 4400,2900,4800,2900,200,*,LEFT,POLY +S 7000,5500,7000,9400,400,*,UP,PDIF +S 3900,4000,6600,4000,500,*,RIGHT,POLY +S 7000,600,7000,2500,400,*,UP,NDIF +S 1500,7000,1900,7000,400,*,RIGHT,POLY +S 1000,4000,3500,4000,200,*,RIGHT,POLY +S 2500,600,2500,2500,1400,*,UP,NDIF +S 1500,2500,1500,3200,200,*,UP,POLY +S 1500,600,1500,2500,200,*,UP,NTRANS +S 1000,600,1000,2500,600,*,UP,NDIF +S 4000,600,4000,2500,600,*,UP,NDIF +S 1500,6800,1500,7500,200,*,UP,POLY +S 1000,1800,1000,8200,300,*,UP,ALU1 +S 3500,2500,3500,5500,200,*,UP,POLY +S 6500,2500,6500,5500,200,*,UP,POLY +S 5500,2500,5500,5500,200,*,UP,POLY +S 4700,5500,4700,8500,400,*,UP,PDIF +S 4300,5500,4300,8500,200,*,UP,PTRANS +S 6000,5500,6000,9400,400,*,UP,PDIF +S 4000,5500,4000,8500,400,*,UP,PDIF +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 6500,5500,6500,9400,200,*,UP,PTRANS +S 7000,5800,7000,8800,300,*,UP,ALU1 +S 6000,600,6000,2500,600,*,UP,NDIF +S 6500,600,6500,2500,200,*,UP,NTRANS +S 7000,1200,7000,2200,300,*,UP,ALU1 +S 3500,5500,3500,8500,200,*,UP,PTRANS +S 5500,600,5500,2500,200,*,UP,NTRANS +S 4500,600,4500,2500,200,*,UP,NTRANS +S 3500,600,3500,2500,200,*,UP,NTRANS +S 1000,7500,1000,9400,400,*,UP,PDIF +S 1500,7500,1500,9400,200,*,UP,PTRANS +S 1900,7500,1900,9400,600,*,UP,PDIF +S 2000,1800,2000,8200,300,i0,UP,CALU1 +S 5000,1800,5000,8200,300,i1,UP,CALU1 +S 6000,1800,6000,8200,300,q,UP,CALU1 +S 6000,1800,6000,8200,300,*,UP,ALU1 +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,8200,500,1400,vss,RIGHT,CALU1 +S 3000,5500,3000,8500,400,*,UP,PDIF +S 5000,5500,5000,9400,400,*,UP,PDIF +S 2000,1800,2000,8200,300,*,UP,ALU1 +S -500,7500,8500,7500,6000,*,RIGHT,NWELL +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,0,8200,0,400,*,RIGHT,PTIE +S 5000,600,5000,2500,600,*,UP,NDIF +S 5000,1800,5000,8200,300,*,UP,ALU1 +V 2000,3000,CONT_POLY,* +V 1800,7000,CONT_POLY,* +V 4800,5000,CONT_POLY,* +V 4100,4000,CONT_POLY,* +V 4700,3100,CONT_POLY,* +V 1000,4000,CONT_POLY,* +V 2000,900,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 7000,9200,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,6000,CONT_DIF_P,* +V 7000,900,CONT_DIF_N,* +V 7000,2000,CONT_DIF_N,* +V 5000,9200,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 4000,2000,CONT_DIF_N,* +V 3000,900,CONT_DIF_N,* +V 2000,9200,CONT_DIF_P,* +V 5000,900,CONT_DIF_N,* +V 3000,8000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 6000,8000,CONT_DIF_P,* +V 6000,7000,CONT_DIF_P,* +V 6000,6000,CONT_DIF_P,* +V 6000,2000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/on12_x4.vbe b/pdks/symbolic/nsxlib2/cells/on12_x4.vbe new file mode 100644 index 000000000..c5f990c6c --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/on12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 394; + CONSTANT tphl_i0_q : NATURAL := 474; + CONSTANT tphh_i1_q : NATURAL := 491; + CONSTANT tplh_i0_q : NATURAL := 499; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x4; + +ARCHITECTURE behaviour_data_flow OF on12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x4" + SEVERITY WARNING; + q <= (not (i0) or i1) after 1100 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/one_x0.ap b/pdks/symbolic/nsxlib2/cells/one_x0.ap new file mode 100644 index 000000000..24eb25205 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/one_x0.ap @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H one_x0,P,28/ 6/2024,100 +A 0,0,3000,10000 +R 2000,2000,ref_ref,q_10 +R 2000,3000,ref_ref,q_15 +R 2000,4000,ref_ref,q_20 +R 2000,5000,ref_ref,q_25 +R 2000,6000,ref_ref,q_30 +R 2000,7000,ref_ref,q_35 +R 2000,8000,ref_ref,q_40 +S 800,6000,800,8800,400,*,UP,ALU1 +S 1100,700,1100,3400,1200,*,DOWN,NDIF +S 1000,5000,1400,5000,500,*,LEFT,POLY +S 1400,4800,1400,5600,200,*,UP,POLY +S 1100,1200,1100,5200,300,*,UP,ALU1 +S 700,5500,700,7500,800,*,UP,PDIF +S -500,7500,3500,7500,6000,*,RIGHT,NWELL +S -200,10000,3200,10000,400,*,RIGHT,NTIE +S -200,0,3200,0,400,*,RIGHT,PTIE +S 1400,5500,1400,7500,200,*,UP,PTRANS +S 2000,5500,2000,7500,600,*,UP,PDIF +S 2000,1800,2000,8200,300,*,UP,ALU1 +S -200,500,3200,500,1400,vss,RIGHT,CALU1 +S -200,9500,3200,9500,1400,vdd,RIGHT,CALU1 +S 2000,1800,2000,8200,300,q,UP,CALU1 +V 1100,3000,CONT_DIF_N,* +V 1100,2000,CONT_DIF_N,* +V 1100,1000,CONT_DIF_N,* +V 1100,5000,CONT_POLY,* +V 2000,7000,CONT_DIF_P,* +V 2000,6000,CONT_DIF_P,* +V 800,6000,CONT_DIF_P,* +V 800,7000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/one_x0.vbe b/pdks/symbolic/nsxlib2/cells/one_x0.vbe new file mode 100644 index 000000000..e7439c597 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/one_x0.vbe @@ -0,0 +1,20 @@ +ENTITY one_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END one_x0; + +ARCHITECTURE behaviour_data_flow OF one_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on one_x0" + SEVERITY WARNING; + q <= '1'; +END; diff --git a/pdks/symbolic/nsxlib2/cells/powmid_x0.ap b/pdks/symbolic/nsxlib2/cells/powmid_x0.ap new file mode 100644 index 000000000..babaf66e2 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/powmid_x0.ap @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H powmid_x0,P, 7/ 6/2024,100 +A 0,0,7000,10000 +S 3000,800,3000,3500,1600,*,DOWN,NDIF +S 3100,5300,3100,9200,1600,*,DOWN,PDIF +S -200,0,7200,0,400,*,LEFT,PTIE +S -500,7500,7500,7500,6000,*,RIGHT,NWELL +S -200,10000,7200,10000,400,*,LEFT,NTIE +S -200,500,7200,500,1400,vss,RIGHT,CALU1 +S -200,9500,7200,9500,1400,vdd,RIGHT,CALU1 +V 2600,9000,CONT_DIF_P,* +V 3600,9000,CONT_DIF_P,* +V 3500,1000,CONT_DIF_N,* +V 2500,1000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/powmid_x0.vbe b/pdks/symbolic/nsxlib2/cells/powmid_x0.vbe new file mode 100644 index 000000000..52f4c8149 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/powmid_x0.vbe @@ -0,0 +1,18 @@ +ENTITY powmid_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END powmid_x0; + +ARCHITECTURE behaviour_data_flow OF powmid_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on powmid_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/nsxlib2/cells/rowend_x0.ap b/pdks/symbolic/nsxlib2/cells/rowend_x0.ap new file mode 100644 index 000000000..413bc2434 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/rowend_x0.ap @@ -0,0 +1,17 @@ +V ALLIANCE : 6 +H rowend_x0,P,28/ 5/2024,100 +A 0,0,1000,10000 +S 500,6300,500,9400,400,*,DOWN,PDIF +S 500,700,500,3500,400,*,UP,NDIF +S -500,7500,1500,7500,6000,*,RIGHT,NWELL +S -200,10000,1200,10000,400,*,RIGHT,NTIE +S -200,0,1200,0,400,*,RIGHT,PTIE +S -200,500,1200,500,1400,vss,RIGHT,CALU1 +S -200,9500,1200,9500,1400,vdd,RIGHT,CALU1 +V 500,9200,CONT_DIF_P,* +V 500,900,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/rowend_x0.vbe b/pdks/symbolic/nsxlib2/cells/rowend_x0.vbe new file mode 100644 index 000000000..dfe3de719 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/rowend_x0.vbe @@ -0,0 +1,18 @@ +ENTITY rowend_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 250; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END rowend_x0; + +ARCHITECTURE behaviour_data_flow OF rowend_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rowend_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/nsxlib2/cells/sff1_x4.ap b/pdks/symbolic/nsxlib2/cells/sff1_x4.ap new file mode 100644 index 000000000..e92a8d686 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/sff1_x4.ap @@ -0,0 +1,274 @@ +V ALLIANCE : 6 +H sff1_x4,P,20/12/2024,100 +A 0,0,16000,10000 +R 14000,2000,ref_ref,q_10 +R 14000,3000,ref_ref,q_15 +R 14000,4000,ref_ref,q_20 +R 14000,5000,ref_ref,q_25 +R 14000,6000,ref_ref,q_30 +R 14000,7000,ref_ref,q_35 +R 14000,8000,ref_ref,q_40 +R 6000,8000,ref_ref,i_40 +R 5000,5000,ref_ref,i_25 +R 5000,6000,ref_ref,i_30 +R 5000,7000,ref_ref,i_35 +R 2000,3000,ref_ref,ck_15 +R 2000,4000,ref_ref,ck_20 +R 2000,5000,ref_ref,ck_25 +R 2000,6000,ref_ref,ck_30 +R 2000,7000,ref_ref,ck_35 +R 2000,8000,ref_ref,ck_40 +R 5000,4000,ref_ref,i_20 +R 5000,3000,ref_ref,i_15 +R 6000,2000,ref_ref,i_10 +S 5400,7000,5800,7000,498,*,RIGHT,POLY +S 4300,3000,4600,3000,498,*,RIGHT,POLY +S 10800,5700,10800,7500,200,*,UP,POLY +S 10800,2400,10800,4400,200,*,UP,POLY +S 14500,2500,14500,5600,200,*,UP,POLY +S 13500,2500,13500,5500,200,*,UP,POLY +S 11500,5800,11500,7600,200,*,UP,POLY +S 9800,5000,9800,7500,200,*,UP,POLY +S 8800,6400,8800,7500,200,*,UP,POLY +S 7800,6900,7800,7500,200,*,UP,POLY +S 7300,4900,7300,7500,200,*,UP,POLY +S 6300,5700,6300,7500,200,*,UP,POLY +S 5400,6000,5400,7500,200,*,UP,POLY +S 4400,6800,4400,7600,200,*,UP,POLY +S 1000,6200,1000,6500,200,*,UP,POLY +S 1000,2500,1000,3100,200,*,UP,POLY +S 4300,2500,4300,3200,200,*,UP,POLY +S 5600,2400,5600,3200,200,*,UP,POLY +S 6500,2500,6500,3100,200,*,UP,POLY +S 7500,2400,7500,4400,200,*,UP,POLY +S 8500,2400,8500,3600,200,*,UP,POLY +S 12400,2400,12400,3200,200,*,UP,POLY +S 7000,6300,7000,8400,300,*,UP,ALU1 +S 2800,4300,11100,4300,200,ckr,RIGHT,POLY +S 6500,2800,6500,5000,300,*,UP,ALU1 +S 8000,3000,9500,3000,300,*,RIGHT,ALU1 +S 9100,2800,9800,2800,200,*,LEFT,POLY +S 9700,1600,9700,2800,200,*,UP,POLY +S 8400,3600,10300,3600,200,*,RIGHT,POLY +S 8000,2000,8000,6400,300,sff_m,UP,ALU1 +S 6900,6400,8900,6400,300,*,RIGHT,ALU1 +S 7900,7100,10300,7100,300,*,RIGHT,ALU1 +S 6200,5700,7300,5700,300,*,RIGHT,ALU1 +S 2600,6500,2600,9300,600,*,UP,PDIF +S 12400,4000,14600,4000,200,sff_s,RIGHT,POLY +S 2600,1100,2600,2500,600,*,UP,NDIF +S 15000,5500,15000,9400,400,*,UP,PDIF +S 5900,7500,5900,9400,400,*,UP,PDIF +S 7300,4000,7300,5600,300,*,UP,ALU1 +S 10900,4000,10900,5800,300,*,UP,ALU1 +S 12400,3000,14100,3000,300,*,RIGHT,ALU1 +S 14000,600,14000,2500,600,*,UP,NDIF +S 11900,7500,11900,9400,600,*,UP,PDIF +S 10300,7500,10300,9400,800,*,UP,PDIF +S -200,0,16200,0,400,*,RIGHT,PTIE +S -200,500,16200,500,1400,vss,RIGHT,CALU1 +S -600,7500,16600,7500,6000,*,RIGHT,NWELL +S -200,10000,16200,10000,400,*,RIGHT,NTIE +S -200,9500,16200,9500,1400,vdd,RIGHT,CALU1 +S 15000,5900,15000,8800,300,*,UP,ALU1 +S 15000,800,15000,2100,300,*,UP,ALU1 +S 15000,600,15000,2500,400,*,UP,NDIF +S 14500,600,14500,2500,200,*,UP,NTRANS +S 14500,5500,14500,9400,200,*,UP,PTRANS +S 12400,5000,14100,5000,300,*,RIGHT,ALU1 +S 14000,600,14000,2500,400,*,UP,NDIF +S 14000,5500,14000,9400,400,*,UP,PDIF +S 14000,1800,14000,8200,300,q,UP,CALU1 +S 14000,1800,14000,8200,300,*,UP,ALU1 +S 13500,600,13500,2500,200,*,UP,NTRANS +S 13000,600,13000,2500,600,*,UP,NDIF +S 13000,800,13000,2100,300,*,UP,ALU1 +S 12300,7500,12300,9400,800,*,UP,PDIF +S 12300,7500,12300,9400,600,*,UP,PDIF +S 12900,5500,12900,9400,600,*,UP,PDIF +S 13500,5500,13500,9400,200,*,UP,PTRANS +S 13000,5900,13000,8800,300,*,UP,ALU1 +S 11400,5800,12400,5800,200,*,RIGHT,POLY +S 10700,5900,11100,5900,200,*,RIGHT,POLY +S 11500,4000,12500,4000,300,*,RIGHT,ALU1 +S 12300,4900,12300,5800,200,*,UP,POLY +S 12100,1500,12100,2500,200,*,UP,NDIF +S 12400,1500,12400,2500,200,*,UP,NTRANS +S 500,5000,11900,5000,200,nckr,RIGHT,POLY +S 11800,1500,11800,2500,200,*,UP,NTRANS +S 11800,2400,11800,5100,200,*,UP,POLY +S 10300,8000,11700,8000,400,*,RIGHT,ALU1 +S 11300,2000,11700,2000,400,*,RIGHT,ALU1 +S 11600,1800,11600,8200,300,*,UP,ALU1 +S 11300,1500,11300,2500,400,*,UP,NDIF +S 10200,1500,10200,2500,800,*,UP,NDIF +S 10800,1500,10800,2500,200,*,UP,NTRANS +S 10200,1900,10200,7000,300,*,UP,ALU1 +S 11500,7500,11500,9400,200,*,UP,PTRANS +S 10800,7500,10800,9400,200,*,UP,PTRANS +S 3800,6000,5500,6000,200,*,RIGHT,POLY +S 4900,7500,4900,9400,600,*,UP,PDIF +S 5400,7500,5400,9400,200,*,UP,PTRANS +S 4900,700,4900,2500,800,*,UP,NDIF +S 5600,700,5600,2500,200,*,UP,NTRANS +S 5700,2900,5700,7000,300,*,UP,ALU1 +S 4300,3000,5000,3000,400,*,RIGHT,ALU1 +S 4400,7000,5000,7000,400,*,RIGHT,ALU1 +S 4300,700,4300,2500,200,*,UP,NTRANS +S 4400,7500,4400,9400,200,*,UP,PTRANS +S 3900,700,3900,2500,600,*,UP,NDIF +S 3900,7500,3900,9400,600,*,UP,PDIF +S 3800,1900,3800,8100,300,*,UP,ALU1 +S 2700,1900,2700,8100,300,*,UP,ALU1 +S 1200,3000,2000,3000,400,*,RIGHT,ALU1 +S 1300,6000,2000,6000,400,*,RIGHT,ALU1 +S 2000,1100,2000,2500,200,*,UP,NTRANS +S 2000,2500,2000,6600,200,*,UP,POLY +S 2000,6500,2000,9300,200,*,UP,PTRANS +S 1500,1100,1500,2500,400,*,UP,NDIF +S 1500,1100,1500,2200,400,*,DOWN,ALU1 +S 1500,6500,1500,9300,400,*,UP,PDIF +S 900,6200,1500,6200,200,*,RIGHT,POLY +S 1000,6500,1000,9300,200,*,UP,PTRANS +S 900,2900,1400,2900,200,*,RIGHT,POLY +S 1000,1100,1000,2500,200,*,UP,NTRANS +S 500,1100,500,2500,400,*,UP,NDIF +S 500,1900,500,7200,300,*,UP,ALU1 +S 500,6500,500,9300,400,*,UP,PDIF +S 500,6800,500,8100,300,*,UP,ALU1 +S 9100,1000,9100,2300,400,*,UP,ALU1 +S 6900,2000,8000,2000,300,*,RIGHT,ALU1 +S 6200,1500,6200,2500,400,*,UP,NDIF +S 6500,1500,6500,2500,200,*,UP,NTRANS +S 7000,1500,7000,2500,400,*,UP,NDIF +S 7500,1500,7500,2500,200,*,UP,NTRANS +S 5900,700,5900,2500,400,*,UP,NDIF +S 9300,7000,9300,8100,300,*,DOWN,ALU1 +S 1700,3000,2000,3000,400,*,RIGHT,ALU1 +S 5000,2000,6200,2000,300,*,RIGHT,ALU1 +S 5000,2000,5000,8000,300,i,UP,CALU1 +S 5000,2000,5000,8000,300,*,UP,ALU1 +S 5000,8000,6200,8000,300,i,LEFT,CALU1 +S 5000,8000,6200,8000,300,*,RIGHT,ALU1 +S 2000,2800,2000,8200,300,ck,UP,CALU1 +S 2000,2800,2000,8200,300,*,UP,ALU1 +S 5900,1500,5900,2500,400,*,UP,NDIF +S 9300,7500,9300,9400,400,*,UP,PDIF +S 10200,7500,10200,9400,200,*,UP,PDIF +S 8300,7500,8300,9400,400,*,UP,PDIF +S 12900,1500,12900,2500,400,*,UP,NDIF +S 8100,1500,8100,2500,400,*,UP,NDIF +S 9100,1500,9100,2500,600,*,UP,NDIF +S 8500,1500,8500,2500,200,*,UP,NTRANS +S 9700,1500,9700,2500,200,*,UP,NTRANS +S 7800,1500,7800,2500,400,*,UP,NDIF +S 9800,7500,9800,9400,200,*,UP,PTRANS +S 8800,7500,8800,9400,200,*,UP,PTRANS +S 7800,7500,7800,9400,200,*,UP,PTRANS +S 7300,7500,7300,9400,200,*,UP,PTRANS +S 6300,7500,6300,9400,200,*,UP,PTRANS +S 9300,7500,9300,9400,200,*,UP,PDIF +S 6800,7500,6800,9400,400,*,UP,PDIF +S 5200,2000,6200,2000,300,i,LEFT,CALU1 +B 6850,8200,500,400,CONT_TURN1,* +V 6500,4900,CONT_POLY,* +V 6400,5700,CONT_POLY,* +V 10100,3700,CONT_POLY,* +V 9300,3000,CONT_POLY,* +B 10200,7100,200,200,CONT_TURN1,* +V 8800,6400,CONT_POLY,* +B 7000,6400,200,200,CONT_TURN1,* +V 8000,7100,CONT_POLY,* +B 7300,5700,200,200,CONT_TURN1,* +V 7300,4200,CONT_POLY,* +V 10900,4200,CONT_POLY,* +V 15000,9000,CONT_DIF_P,* +V 15000,8000,CONT_DIF_P,* +V 15000,7000,CONT_DIF_P,* +V 15000,6000,CONT_DIF_P,* +V 15000,1000,CONT_DIF_N,* +V 15000,2000,CONT_DIF_N,* +V 14000,2000,CONT_DIF_N,* +V 14000,6000,CONT_DIF_P,* +V 14000,7000,CONT_DIF_P,* +V 14000,8000,CONT_DIF_P,* +V 8300,9100,CONT_DIF_P,* +V 13000,1000,CONT_DIF_N,* +V 13000,2000,CONT_DIF_N,* +V 12000,9000,CONT_DIF_P,* +V 13000,9000,CONT_DIF_P,* +V 13000,8000,CONT_DIF_P,* +V 13000,7000,CONT_DIF_P,* +V 13000,6000,CONT_DIF_P,* +V 10900,5700,CONT_POLY,* +V 12400,5000,CONT_POLY,* +V 12400,4000,CONT_POLY,* +V 12400,3000,CONT_POLY,* +V 11300,2000,CONT_DIF_N,* +V 2900,4200,CONT_POLY,* +V 10200,2000,CONT_DIF_N,* +V 10300,8000,CONT_DIF_P,* +V 4500,7000,CONT_POLY,* +V 4600,3000,CONT_POLY,* +V 4900,1000,CONT_DIF_N,* +V 5700,7000,CONT_POLY,* +V 6500,3000,CONT_POLY,* +V 4900,9100,CONT_DIF_P,* +V 3700,6000,CONT_POLY,* +V 3800,2000,CONT_DIF_N,* +V 3800,8000,CONT_DIF_P,* +V 2700,8000,CONT_DIF_P,* +V 2700,7000,CONT_DIF_P,* +V 2700,2000,CONT_DIF_N,* +V 1500,1500,CONT_DIF_N,* +V 1500,2100,CONT_DIF_N,* +V 1500,9000,CONT_DIF_P,* +V 1300,6000,CONT_POLY,* +V 1200,3000,CONT_POLY,* +V 500,2000,CONT_DIF_N,* +V 500,5000,CONT_POLY,* +V 500,7000,CONT_DIF_P,* +V 500,8000,CONT_DIF_P,* +V 9100,2100,CONT_DIF_N,* +V 7000,2000,CONT_DIF_N,* +B 5000,8000,200,200,CONT_TURN1,* +B 8000,2000,200,200,CONT_TURN1,* +B 5000,2000,200,200,CONT_TURN1,* +V 9300,8000,CONT_DIF_P,* +V 6800,8200,CONT_DIF_P,* +V 5700,3000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +V 13000,0,CONT_BODY_P,* +V 13000,10000,CONT_BODY_N,* +V 14000,0,CONT_BODY_P,* +V 14000,10000,CONT_BODY_N,* +V 15000,0,CONT_BODY_P,* +V 15000,10000,CONT_BODY_N,* +V 16000,0,CONT_BODY_P,* +V 16000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/sff1_x4.vbe b/pdks/symbolic/nsxlib2/cells/sff1_x4.vbe new file mode 100644 index 000000000..4756bfddd --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/sff1_x4.vbe @@ -0,0 +1,39 @@ +ENTITY sff1_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tsr_i_ck : NATURAL := 476; + CONSTANT transistors : NATURAL := 26 +); +PORT ( + ck : in BIT; + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff1_x4; + +ARCHITECTURE VBE OF sff1_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff1_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED i; + END BLOCK label0; + + q <= sff_m after 1700 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/sff1r_x4.ap b/pdks/symbolic/nsxlib2/cells/sff1r_x4.ap new file mode 100644 index 000000000..3941932a3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/sff1r_x4.ap @@ -0,0 +1,297 @@ +V ALLIANCE : 6 +H sff1r_x4,P,17/ 8/2024,100 +A 0,0,17000,10000 +R 15000,2000,ref_ref,q_10 +R 15000,3000,ref_ref,q_15 +R 15000,4000,ref_ref,q_20 +R 15000,5000,ref_ref,q_25 +R 15000,8000,ref_ref,q_40 +R 15000,7000,ref_ref,q_35 +R 15000,6000,ref_ref,q_30 +R 11000,3000,ref_ref,nrst_10 +R 11000,6000,ref_ref,nrst_30b +R 10000,3000,ref_ref,nrst_15 +R 10000,4000,ref_ref,nrst_20 +R 10000,5000,ref_ref,nrst_25 +R 10000,6000,ref_ref,nrst_30 +R 5000,8000,ref_ref,i_40 +R 2000,8000,ref_ref,ck_40 +R 2000,7000,ref_ref,ck_35 +R 2000,6000,ref_ref,ck_30 +R 2000,5000,ref_ref,ck_25 +R 2000,4000,ref_ref,ck_20 +R 2000,3000,ref_ref,ck_15 +R 5000,7000,ref_ref,i_35 +R 5000,6000,ref_ref,i_30 +R 5000,5000,ref_ref,i_25 +R 5000,4000,ref_ref,i_20 +R 5000,3000,ref_ref,i_15 +R 6000,2000,ref_ref,i_10 +S 6700,6000,7500,6000,300,*,RIGHT,ALU1 +S 7400,3800,7400,6100,300,*,UP,ALU1 +S 11800,5000,11800,7300,200,*,DOWN,POLY +S 12400,2800,12400,5100,200,*,UP,POLY +S 7800,6100,7800,7500,200,*,DOWN,POLY +S 7700,6200,9000,6200,200,*,RIGHT,POLY +S 8100,5500,9600,5500,200,*,RIGHT,POLY +S 7200,5000,7200,7100,200,*,DOWN,POLY +S 800,5000,12400,5000,200,nckr,RIGHT,POLY +S 8800,1500,8800,2500,600,*,DOWN,NDIF +S 8800,1100,8800,2500,400,*,DOWN,NDIF +S 15500,2500,15500,5500,200,*,DOWN,POLY +S 9800,7100,9800,7500,200,*,DOWN,POLY +S 8800,6600,8800,7500,200,*,DOWN,POLY +S 4500,6800,4500,7500,200,*,DOWN,POLY +S 1500,5900,1500,7300,200,*,DOWN,POLY +S 8200,2500,8200,2900,200,*,UP,POLY +S 12400,2500,12400,3000,200,*,DOWN,POLY +S 13000,2500,13000,3000,200,*,UP,POLY +S 14500,2400,14500,5500,200,*,DOWN,POLY +S 8100,3600,9800,3600,200,*,RIGHT,POLY +S 7200,3300,8300,3300,300,*,RIGHT,ALU1 +S 8200,3500,8200,6800,300,sff_m,DOWN,ALU1 +S 7500,2500,7500,4100,200,*,DOWN,POLY +S 7500,1500,7500,2500,200,*,UP,NTRANS +S 6500,1500,6500,2500,200,*,UP,NTRANS +S 6500,2500,6500,3200,200,*,UP,POLY +S 7300,1800,7300,3400,300,*,UP,ALU1 +S 9100,1900,9100,8200,300,y,DOWN,ALU1 +S 9000,2000,11000,2000,300,*,RIGHT,ALU1 +S 13400,5200,14000,5200,200,*,RIGHT,POLY +S 13700,5000,15100,5000,300,*,RIGHT,ALU1 +S 9800,6000,11200,6000,400,*,RIGHT,ALU1 +S 9000,8100,11400,8100,300,*,LEFT,ALU1 +S 6200,1500,6200,2500,400,*,DOWN,NDIF +S 9900,3000,11200,3000,400,nrst,RIGHT,CALU1 +S 9300,7500,9300,9400,800,*,DOWN,PDIF +S -200,0,17100,0,400,*,RIGHT,PTIE +S -200,500,17200,500,1400,vss,RIGHT,CALU1 +S -100,10000,17100,10000,400,*,RIGHT,NTIE +S -500,7500,17500,7500,6000,*,RIGHT,NWELL +S -200,9500,17300,9500,1400,vdd,RIGHT,CALU1 +S 13100,4000,15600,4000,200,sff_s,RIGHT,POLY +S 16000,600,16000,2500,400,*,DOWN,NDIF +S 16000,1200,16000,2100,300,*,DOWN,ALU1 +S 16000,5500,16000,9400,600,*,DOWN,PDIF +S 16100,5900,16100,8800,300,*,DOWN,ALU1 +S 15500,5500,15500,9400,200,*,DOWN,PTRANS +S 15100,600,15100,2500,600,*,DOWN,NDIF +S 15500,600,15500,2500,200,*,UP,NTRANS +S 13800,3000,15200,3000,300,*,RIGHT,ALU1 +S 15100,5500,15100,9400,600,*,DOWN,PDIF +S 15000,1800,15000,8200,300,q,DOWN,CALU1 +S 15000,1800,15000,8200,300,*,DOWN,ALU1 +S 14000,6700,14000,9400,800,*,DOWN,PDIF +S 14000,1200,14000,2100,300,*,DOWN,ALU1 +S 12900,3000,13700,3000,200,*,RIGHT,POLY +S 14500,600,14500,2500,200,*,UP,NTRANS +S 13900,600,13900,2500,800,*,DOWN,NDIF +S 13500,1500,13500,2500,400,*,DOWN,NDIF +S 13700,600,13700,2500,400,*,DOWN,NDIF +S 11800,2000,13200,2000,300,*,RIGHT,ALU1 +S 12300,7000,13200,7000,300,*,RIGHT,ALU1 +S 13100,2000,13100,7000,300,*,DOWN,ALU1 +S 12200,5800,12900,5800,200,*,RIGHT,POLY +S 12800,5800,12800,6300,200,*,DOWN,POLY +S 11400,4000,12500,4000,300,*,RIGHT,ALU1 +S 12400,4000,12400,5500,300,*,DOWN,ALU1 +S 12800,6700,12800,9400,200,*,DOWN,PTRANS +S 12800,6300,12800,7700,200,*,UP,POLY +S 14500,5500,14500,9400,200,*,DOWN,PTRANS +S 14000,7800,14000,9100,300,*,DOWN,ALU1 +S 13000,1500,13000,2500,200,*,UP,NTRANS +S 13500,5200,13500,6800,200,*,UP,POLY +S 13500,6700,13500,9400,200,*,DOWN,PTRANS +S 12300,6700,12300,9400,600,*,DOWN,PDIF +S 11800,6700,11800,9400,200,*,DOWN,PTRANS +S 10300,7500,10300,9400,600,*,UP,PDIF +S 11300,6700,11300,9400,600,*,UP,PDIF +S 9700,7200,10200,7200,200,*,RIGHT,POLY +S 10100,5800,10100,7300,200,reset,DOWN,POLY +S 9800,7500,9800,9400,200,*,UP,PTRANS +S 8700,6700,9600,6700,200,*,RIGHT,POLY +S 9500,5400,9500,6800,200,*,DOWN,POLY +S 12400,1500,12400,2500,200,*,UP,NTRANS +S 11900,1500,11900,2500,400,*,DOWN,NDIF +S 3100,4200,11600,4200,200,ckr,RIGHT,POLY +S 11000,1500,11000,2500,400,*,DOWN,NDIF +S 10900,1500,10900,2500,600,*,DOWN,NDIF +S 11400,2500,11400,4200,200,*,DOWN,POLY +S 11400,1500,11400,2500,200,*,UP,NTRANS +S 10400,1500,10400,3200,200,*,UP,POLY +S 10400,1500,10400,2500,200,*,UP,NTRANS +S 9700,2100,9700,3600,200,*,UP,POLY +S 9700,1500,9700,2500,200,*,UP,NTRANS +S 6600,6700,8300,6700,300,*,RIGHT,ALU1 +S 8300,7500,8300,9400,400,*,UP,PDIF +S 7200,7000,7200,7600,200,*,DOWN,POLY +S 7200,7500,7200,9400,200,*,DOWN,PTRANS +S 7800,7500,7800,9400,200,*,DOWN,PTRANS +S 8800,7500,8800,9400,200,*,UP,PTRANS +S 10800,6000,11200,6000,300,nrst,LEFT,CALU1 +S 10000,2800,10000,6100,300,nrst,DOWN,CALU1 +S 9200,1500,9200,2500,600,*,DOWN,NDIF +S 8100,2900,9200,2900,200,*,RIGHT,POLY +S 8200,1500,8200,2500,200,*,UP,NTRANS +S 6600,7500,6600,9400,600,*,UP,PDIF +S 6600,6700,6600,8100,300,*,DOWN,ALU1 +S 6100,7200,6100,7600,200,*,DOWN,POLY +S 6000,7200,6700,7200,200,*,RIGHT,POLY +S 6600,5800,6600,7200,200,*,DOWN,POLY +S 6100,7500,6100,9400,200,*,DOWN,PTRANS +S 7100,1500,7100,2500,800,*,DOWN,NDIF +S 6600,2800,6600,5200,300,*,DOWN,ALU1 +S 5800,1900,5800,3000,200,*,UP,POLY +S 5800,1500,5800,2500,200,*,UP,NTRANS +S 3800,6000,5900,6000,200,*,RIGHT,POLY +S 5800,2800,5800,6200,300,*,DOWN,ALU1 +S 5300,1500,5300,2500,400,*,DOWN,NDIF +S 5100,700,5100,2500,400,*,DOWN,NDIF +S 5100,700,5100,2500,400,*,DOWN,NDIF +S 5000,7000,5000,8200,300,i,UP,CALU1 +S 5500,6100,5500,7500,200,*,UP,POLY +S 5000,7500,5000,9400,800,*,UP,PDIF +S 5500,7500,5500,9400,200,*,DOWN,PTRANS +S 4600,7000,5100,7000,400,*,RIGHT,ALU1 +S 1700,6000,2000,6000,400,*,RIGHT,ALU1 +S 4700,3000,5100,3000,400,*,RIGHT,ALU1 +S 1700,3000,2100,3000,400,*,RIGHT,ALU1 +S 1000,1900,1000,8000,300,*,DOWN,ALU1 +S 4000,1900,4000,8100,300,*,DOWN,ALU1 +S 3000,1900,3000,8100,300,*,DOWN,ALU1 +S 2000,1100,2000,2100,300,*,UP,ALU1 +S 5000,2000,6100,2000,300,i,LEFT,CALU1 +S 4900,2000,6100,2000,300,*,RIGHT,ALU1 +S 5000,2000,5000,7100,300,*,DOWN,ALU1 +S 5000,2000,5000,7100,300,i,DOWN,CALU1 +S 1500,1800,1500,3100,200,*,UP,POLY +S 1400,2900,1800,2900,200,*,RIGHT,POLY +S 4000,1500,4000,2500,400,*,DOWN,NDIF +S 4900,1500,4900,2500,400,*,DOWN,NDIF +S 1000,1500,1000,2500,400,*,DOWN,NDIF +S 2000,1500,2000,2500,600,*,DOWN,NDIF +S 1800,1500,1800,2500,400,*,DOWN,NDIF +S 1500,1500,1500,2500,200,*,UP,NTRANS +S 2500,1500,2500,2500,200,*,UP,NTRANS +S 3000,1500,3000,2500,600,*,DOWN,NDIF +S 4500,1500,4500,2500,200,*,UP,NTRANS +S 4100,7500,4100,9400,600,*,UP,PDIF +S 4500,7500,4500,9400,200,*,DOWN,PTRANS +S 2000,2800,2000,8200,300,*,DOWN,ALU1 +S 2000,2800,2000,8200,300,ck,DOWN,CALU1 +S 2500,1800,2500,7300,200,*,DOWN,POLY +S 4500,1800,4500,3200,200,*,UP,POLY +S 2000,7300,2000,9300,400,*,UP,PDIF +S 3000,7300,3000,9300,400,*,UP,PDIF +S 2500,7300,2500,9300,200,*,DOWN,PTRANS +S 1000,7300,1000,9300,400,*,UP,PDIF +S 1500,7300,1500,9300,200,*,DOWN,PTRANS +V 8100,5600,CONT_POLY,* +B 7400,6000,200,200,CONT_TURN1,* +V 14000,9000,CONT_DIF_P,* +V 8800,1300,CONT_DIF_N,* +B 8200,3450,400,500,CONT_TURN1,* +V 7400,4000,CONT_POLY,* +V 8200,3500,CONT_POLY,* +V 7000,2000,CONT_DIF_N,* +B 7150,2000,500,400,CONT_TURN1,* +B 9200,8100,400,400,CONT_TURN1,* +B 10000,6000,400,400,CONT_TURN1,* +B 10000,3000,400,400,CONT_TURN1,* +V 9300,8100,CONT_DIF_P,* +B 5000,2000,200,200,CONT_TURN1,* +V 13800,5000,CONT_POLY,* +V 13800,3000,CONT_POLY,* +V 5700,6000,CONT_POLY,* +V 16000,900,CONT_DIF_N,* +V 16000,2000,CONT_DIF_N,* +V 16100,9100,CONT_DIF_P,* +V 16100,8000,CONT_DIF_P,* +V 16100,7000,CONT_DIF_P,* +V 16100,6000,CONT_DIF_P,* +V 15000,2000,CONT_DIF_N,* +V 15000,8000,CONT_DIF_P,* +V 15000,7000,CONT_DIF_P,* +V 15000,6000,CONT_DIF_P,* +V 14000,900,CONT_DIF_N,* +V 14000,2000,CONT_DIF_N,* +V 13100,4000,CONT_POLY,* +B 13100,7000,200,200,CONT_TURN1,* +B 13100,2000,200,200,CONT_TURN1,* +V 12400,5600,CONT_POLY,* +B 12400,4000,200,200,CONT_TURN1,* +V 14000,8000,CONT_DIF_P,* +V 12300,7000,CONT_DIF_P,* +V 11300,8100,CONT_DIF_P,* +V 10100,6000,CONT_POLY,* +V 10300,9100,CONT_DIF_P,* +V 8900,6100,CONT_POLY,* +V 11900,2000,CONT_DIF_N,* +V 11400,4000,CONT_POLY,* +V 10900,2000,CONT_DIF_N,* +V 10400,3000,CONT_POLY,* +V 9100,3000,CONT_POLY,* +B 9100,2000,200,200,CONT_TURN1,* +B 8200,6700,200,200,CONT_TURN1,* +V 8300,9100,CONT_DIF_P,* +V 6500,5000,CONT_POLY,* +B 6600,6700,200,200,CONT_TURN1,* +V 6600,8000,CONT_DIF_P,* +V 6600,6000,CONT_POLY,* +B 7300,3300,200,200,CONT_TURN1,* +V 6600,3000,CONT_POLY,* +V 5800,3000,CONT_POLY,* +V 5100,900,CONT_DIF_N,* +V 5000,9100,CONT_DIF_P,* +V 1700,6000,CONT_POLY,* +V 1700,3000,CONT_POLY,* +V 3200,4000,CONT_POLY,* +V 4700,3000,CONT_POLY,* +V 4700,7000,CONT_POLY,* +V 2000,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 2000,9100,CONT_DIF_P,* +V 4000,6000,CONT_POLY,* +V 4000,2000,CONT_DIF_N,* +V 4000,8000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 1000,2000,CONT_DIF_N,* +V 1000,5000,CONT_POLY,* +V 1000,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +V 13000,0,CONT_BODY_P,* +V 13000,10000,CONT_BODY_N,* +V 14000,0,CONT_BODY_P,* +V 14000,10000,CONT_BODY_N,* +V 15000,0,CONT_BODY_P,* +V 15000,10000,CONT_BODY_N,* +V 16000,0,CONT_BODY_P,* +V 16000,10000,CONT_BODY_N,* +V 17000,0,CONT_BODY_P,* +V 17000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/sff1r_x4.vbe b/pdks/symbolic/nsxlib2/cells/sff1r_x4.vbe new file mode 100644 index 000000000..eaa2d5dc1 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/sff1r_x4.vbe @@ -0,0 +1,48 @@ +ENTITY sff1r_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_i : NATURAL := 8; + CONSTANT cin_nrst : NATURAL := 16; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT taf_nrst_q : NATURAL := 500; + CONSTANT tar_nrst_q : NATURAL := 500; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tsr_i_ck : NATURAL := 476; + CONSTANT transistors : NATURAL := 30 +); +PORT ( + ck : in BIT; + i : in BIT; + nrst : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff1r_x4; + +ARCHITECTURE VBE OF sff1r_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + SIGNAL sff_s : REG_BIT REGISTER; -- sff_s + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff1r_x4" + SEVERITY WARNING; + + label0 : BLOCK (ck = '1') + BEGIN + sff_s <= GUARDED (NOT(nrst) OR NOT(sff_m)); + END BLOCK label0; + label1 : BLOCK (NOT(ck) = '1') + BEGIN + sff_m <= GUARDED i; + END BLOCK label1; + + q <= NOT(sff_s) after 1700 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/sff2_x4.ap b/pdks/symbolic/nsxlib2/cells/sff2_x4.ap new file mode 100644 index 000000000..c053caba3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/sff2_x4.ap @@ -0,0 +1,351 @@ +V ALLIANCE : 6 +H sff2_x4,P,17/ 8/2024,100 +A 0,0,24000,10000 +R 2000,5000,ref_ref,i0_20 +R 2000,4000,ref_ref,i0_25 +R 3000,5000,ref_ref,cmd_30 +R 3000,6000,ref_ref,cmd_25 +R 6000,7000,ref_ref,i1_35 +R 6000,6000,ref_ref,i1_30 +R 6000,5000,ref_ref,i1_25 +R 6000,4000,ref_ref,i1_20 +R 6000,3000,ref_ref,i1_15 +R 9000,2000,ref_ref,ck_10 +R 9000,7000,ref_ref,ck_35 +R 22000,4000,ref_ref,q_20 +R 22000,5000,ref_ref,q_25 +R 22000,3000,ref_ref,q_15 +R 3000,8000,ref_ref,cmd_40 +R 9000,5000,ref_ref,ck_25 +R 9000,4000,ref_ref,ck_20 +R 2000,3000,ref_ref,i0_15 +R 2000,7000,ref_ref,i0_35 +R 2000,6000,ref_ref,i0_30 +R 2000,8000,ref_ref,i0_40 +R 6000,2000,ref_ref,i1_10 +R 3000,7000,ref_ref,cmd_35 +S 22800,2500,22800,5500,200,*,UP,POLY +S 21500,2500,21500,5600,200,*,UP,POLY +S 20200,5100,20200,7500,200,*,UP,POLY +S 19200,7000,19200,7500,200,*,UP,POLY +S 18000,4900,18000,7500,200,*,UP,POLY +S 15600,7000,15600,7500,200,*,UP,POLY +S 14400,4900,14400,7400,200,*,UP,POLY +S 11800,6900,11800,7500,200,*,UP,POLY +S 4700,5800,4700,6500,200,*,UP,POLY +S 3500,5200,3500,6500,200,*,UP,POLY +S 2500,6200,2500,6500,200,*,UP,POLY +S 1100,2500,1100,6500,200,*,UP,POLY +S 3400,2500,3400,4200,200,*,UP,POLY +S 5000,2400,5000,5200,200,*,UP,POLY +S 5900,2500,5900,3000,200,*,UP,POLY +S 8200,2400,8200,3000,200,*,UP,POLY +S 12200,2400,12200,3100,200,*,UP,POLY +S 15900,1500,15900,2000,200,*,UP,POLY +S 20400,2400,20400,3100,200,*,UP,POLY +S 13200,5900,13200,7500,200,*,UP,POLY +S 14800,7500,14800,9400,600,*,UP,PDIF +S 15000,2000,15000,8000,300,sff_m,UP,ALU1 +S 13600,7900,15000,7900,300,*,RIGHT,ALU1 +S 12500,7400,12500,9400,400,*,UP,PDIF +S 14400,7400,14400,9400,200,*,UP,PTRANS +S 13800,7400,13800,9400,600,*,UP,PDIF +S 13200,7400,13200,9400,200,*,UP,PTRANS +S 12700,7400,12700,9400,600,*,UP,PDIF +S 11700,3000,12200,3000,400,*,LEFT,ALU1 +S 17400,2000,17400,8200,300,*,UP,ALU1 +S 15800,2000,17900,2000,300,*,RIGHT,ALU1 +S 16000,7000,17500,7000,300,*,RIGHT,ALU1 +S 5000,2000,5000,6200,300,*,UP,ALU1 +S 400,2000,5000,2000,300,*,RIGHT,ALU1 +S 3300,2000,3300,4200,300,*,UP,ALU1 +S 13500,2000,15000,2000,300,*,RIGHT,ALU1 +S 15000,3000,16600,3000,300,*,RIGHT,ALU1 +S 18900,2000,19800,2000,300,*,RIGHT,ALU1 +S 19800,2000,19800,8000,300,sff_s,UP,ALU1 +S 20600,5000,22000,5000,300,*,RIGHT,ALU1 +S 18400,8000,19800,8000,300,*,RIGHT,ALU1 +S 20600,3000,22000,3000,300,*,RIGHT,ALU1 +S 19800,4000,21000,4000,300,*,RIGHT,ALU1 +S 15000,6000,16400,6000,300,*,RIGHT,ALU1 +S 13100,6000,14000,6000,300,*,RIGHT,ALU1 +S 14000,3800,14000,6000,300,*,UP,ALU1 +S 11800,2800,11800,8000,300,*,UP,ALU1 +S 4200,8000,11800,8000,300,*,RIGHT,ALU1 +S 4200,2800,4200,8000,300,*,UP,ALU1 +S 12800,2800,13200,2800,200,*,RIGHT,POLY +S 13100,2500,13100,2800,200,*,UP,POLY +S 13600,1500,13600,2500,400,*,UP,NDIF +S 13100,1500,13100,2500,200,*,UP,NTRANS +S 2500,2500,2500,2900,200,*,UP,POLY +S 1800,2900,2600,2900,200,*,RIGHT,POLY +S 16900,1500,16900,2800,200,*,UP,POLY +S 16300,2800,17000,2800,200,*,RIGHT,POLY +S 19000,1500,19000,2500,400,*,DOWN,NDIF +S 18500,1500,18500,2500,200,*,UP,NTRANS +S 18500,2500,18500,2900,200,*,UP,POLY +S 18500,2900,18500,4000,200,*,UP,POLY +S 21000,600,21000,2500,400,*,UP,NDIF +S 4700,1500,4700,2500,400,*,UP,NDIF +S 1500,1500,1500,2500,400,*,UP,NDIF +S 22200,5500,22200,9400,800,*,UP,PDIF +S 23300,5800,23300,8800,300,*,UP,ALU1 +S 10300,4000,18800,4000,200,ckr,RIGHT,POLY +S 20100,5100,20900,5100,200,*,RIGHT,POLY +S 23300,800,23300,2200,300,*,UP,ALU1 +S 21800,600,21800,2500,400,*,UP,NDIF +S 20800,1500,20800,2500,400,*,DOWN,NDIF +S 19900,1500,19900,2500,400,*,DOWN,NDIF +S 18200,1500,18200,2500,400,*,DOWN,NDIF +S 19500,2500,19500,2900,200,*,UP,POLY +S 21500,600,21500,2500,200,*,UP,NTRANS +S 21000,800,21000,2200,300,*,UP,ALU1 +S 20700,7500,20700,9400,600,*,UP,PDIF +S 21000,5500,21000,9400,600,*,UP,PDIF +S 21000,5800,21000,8800,300,*,UP,ALU1 +S 21500,5500,21500,9400,200,*,UP,PTRANS +S 15000,600,15000,2500,800,*,UP,NDIF +S 14600,1500,14600,2500,400,*,UP,NDIF +S 14100,2500,14100,4000,200,*,UP,POLY +S 14100,1500,14100,2500,200,*,UP,NTRANS +S 12200,7500,12200,9400,400,*,UP,PDIF +S 9300,6500,9300,8500,400,*,UP,PDIF +S 8600,6500,8600,8500,400,*,UP,PDIF +S 16800,6000,16800,7500,200,*,UP,POLY +S 16400,600,16400,1500,600,*,UP,NDIF +S 16900,600,16900,1500,200,*,UP,NTRANS +S 15900,600,15900,1500,200,*,UP,NTRANS +S 12700,1500,12700,2500,600,*,UP,NDIF +S 11800,1500,11800,2500,400,*,UP,NDIF +S 10300,1500,10300,2500,400,*,UP,NDIF +S 8100,2900,9000,2900,200,*,RIGHT,POLY +S 8100,6100,9100,6100,200,*,RIGHT,POLY +S 10300,1800,10300,7200,300,*,UP,ALU1 +S 7700,1800,7700,7200,300,*,UP,ALU1 +S 9200,1500,9200,2500,600,*,UP,NDIF +S 8600,1500,8600,2500,400,*,UP,NDIF +S 9800,2500,9800,6500,200,*,UP,POLY +S 6300,1500,6300,2500,400,*,UP,NDIF +S 5500,1500,5500,2500,400,*,UP,NDIF +S 5500,6100,6100,6100,200,*,RIGHT,POLY +S 5600,6100,5600,6500,200,*,UP,POLY +S 6100,6500,6100,8500,400,*,UP,PDIF +S 4700,6000,5100,6000,400,*,LEFT,POLY +S 5200,6500,5200,8500,400,*,UP,PDIF +S 4200,6500,4200,8500,800,*,UP,PDIF +S 3000,6500,3000,8500,400,*,UP,PDIF +S 2100,6500,2100,8500,400,*,UP,PDIF +S 1500,6500,1500,8500,400,*,UP,PDIF +S 3000,1500,3000,2500,400,*,UP,NDIF +S 2100,1500,2100,2500,400,*,UP,NDIF +S 2500,6100,2500,6300,200,*,DOWN,POLY +S 600,1800,600,7200,300,*,UP,ALU1 +S 15500,7000,16300,7000,200,*,RIGHT,POLY +S 18500,7000,19300,7000,200,*,RIGHT,POLY +S 20700,4000,22900,4000,200,*,RIGHT,POLY +S 18600,3900,18600,7200,300,*,UP,ALU1 +S 16100,6000,16900,6000,200,*,RIGHT,POLY +S 3000,4800,3000,8200,300,cmd,UP,CALU1 +S 1800,6100,2600,6100,200,*,RIGHT,POLY +S 2000,2800,2000,8200,300,i0,UP,CALU1 +S 6000,1800,6000,7300,300,i1,UP,CALU1 +S 9000,1800,9000,7200,300,ck,UP,CALU1 +S 22000,1800,22000,8200,300,q,UP,CALU1 +S 12700,1500,12700,2500,600,*,UP,NDIF +S 15400,600,15400,1500,600,*,UP,NDIF +S 17400,600,17400,1500,400,*,UP,NDIF +S 17800,600,17800,2500,600,*,UP,NDIF +S 23300,600,23300,2500,400,*,UP,NDIF +S 22800,600,22800,2500,200,*,UP,NTRANS +S 22200,600,22200,2500,600,*,UP,NDIF +S 4500,6500,4500,8500,200,*,UP,PDIF +S 17600,7500,17600,9400,200,*,UP,PDIF +S 16400,7500,16400,9400,200,*,UP,PDIF +S 22000,1800,22000,8200,300,*,UP,ALU1 +S 20400,1500,20400,2500,200,*,UP,NTRANS +S 19200,7500,19200,9400,200,*,UP,PTRANS +S 18000,7500,18000,9400,200,*,UP,PTRANS +S 15600,7500,15600,9400,200,*,UP,PTRANS +S -500,7500,24500,7500,6000,*,RIGHT,NWELL +S -200,10000,24200,10000,400,*,RIGHT,NTIE +S -200,0,24200,0,400,*,RIGHT,PTIE +S 3800,1500,3800,2500,600,*,UP,NDIF +S 9000,700,9000,2500,600,*,UP,NDIF +S 11400,700,11400,2500,600,*,UP,NDIF +S 6400,6500,6400,9300,600,*,UP,PDIF +S 18600,7500,18600,9400,600,*,UP,PDIF +S 17200,7500,17200,9400,600,*,UP,PDIF +S 9000,6500,9000,9300,600,*,UP,PDIF +S 22800,5500,22800,9400,200,*,UP,PTRANS +S 16800,7500,16800,9400,200,*,UP,PTRANS +S 9000,1800,9000,7200,300,*,UP,ALU1 +S 6000,1800,6000,7200,300,*,UP,ALU1 +S 2000,2800,2000,8200,300,*,UP,ALU1 +S 3000,4800,3000,8200,300,*,UP,ALU1 +S 13000,2800,13000,5200,300,*,UP,ALU1 +S 3500,6500,3500,8500,200,*,UP,PTRANS +S 4700,6500,4700,8500,200,*,UP,PTRANS +S 5600,6500,5600,8500,200,*,UP,PTRANS +S 8200,6500,8200,8500,200,*,UP,PTRANS +S 15800,2000,16200,2000,400,*,RIGHT,POLY +S 16000,7500,16000,9400,600,*,UP,PDIF +S 15200,7500,15200,9400,600,*,UP,PDIF +S 20200,7500,20200,9400,200,*,UP,PTRANS +S 19800,7500,19800,9400,600,*,UP,PDIF +S 8200,6000,8200,6500,200,*,UP,POLY +S 2500,6500,2500,8500,200,*,UP,PTRANS +S 1800,6500,1800,9300,400,*,UP,PDIF +S 600,6500,600,8500,400,*,UP,PDIF +S 1100,6500,1100,8500,200,*,UP,PTRANS +S 3400,1500,3400,2500,200,*,UP,NTRANS +S 2500,1500,2500,2500,200,*,UP,NTRANS +S 1100,1500,1100,2500,200,*,UP,NTRANS +S 600,1500,600,2500,400,*,UP,NDIF +S 9800,6500,9800,8500,200,*,UP,PTRANS +S 7700,6500,7700,8500,400,*,UP,PDIF +S 10300,6500,10300,8500,400,*,UP,PDIF +S 11800,7500,11800,9400,200,*,UP,PTRANS +S 11300,7500,11300,9400,400,*,UP,PDIF +S 1100,5200,5100,5200,200,*,RIGHT,POLY +S 19200,2900,19200,5100,200,*,UP,POLY +S 19100,2900,19600,2900,200,*,RIGHT,POLY +S 1800,700,1800,2500,400,*,UP,NDIF +S 7700,1500,7700,2500,400,*,UP,NDIF +S 8200,1500,8200,2500,200,*,UP,NTRANS +S 9800,1500,9800,2500,200,*,UP,NTRANS +S 12200,1500,12200,2500,200,*,UP,NTRANS +S 23300,5500,23300,9400,400,*,UP,PDIF +S 19500,1500,19500,2500,200,*,UP,NTRANS +S 4200,1500,4200,3300,600,*,UP,NDIF +S 5000,1500,5000,2500,200,*,UP,NTRANS +S 5900,1500,5900,2500,200,*,UP,NTRANS +S 6600,700,6600,2500,400,*,UP,NDIF +S 7900,5000,19300,5000,200,nckr,RIGHT,POLY +S -200,500,24200,500,1400,vss,RIGHT,CALU1 +S -200,9500,24200,9500,1400,vdd,RIGHT,CALU1 +B 15000,7900,200,200,CONT_TURN1,* +V 13800,7900,CONT_DIF_P,* +B 17700,2050,400,300,CONT_TURN1,* +B 5000,2000,200,200,CONT_TURN1,* +B 15000,2000,200,200,CONT_TURN1,* +B 19800,2000,200,200,CONT_TURN1,* +B 19800,8000,200,200,CONT_TURN1,* +B 14000,6000,200,200,CONT_TURN1,* +B 11800,8000,200,200,CONT_TURN1,* +B 4200,8000,200,200,CONT_TURN1,* +V 13600,2000,CONT_DIF_N,* +V 19000,2000,CONT_DIF_N,* +V 20500,3000,CONT_POLY,* +V 2000,3100,CONT_POLY,* +V 2000,5900,CONT_POLY,* +V 4900,6000,CONT_POLY,* +V 6000,5900,CONT_POLY,* +V 3300,4000,CONT_POLY,* +V 23300,6000,CONT_DIF_P,* +V 23300,7000,CONT_DIF_P,* +V 23300,8000,CONT_DIF_P,* +V 23300,9200,CONT_DIF_P,* +V 23300,900,CONT_DIF_N,* +V 23300,2000,CONT_DIF_N,* +V 21000,900,CONT_DIF_N,* +V 21000,2000,CONT_DIF_N,* +V 21000,9200,CONT_DIF_P,* +V 21000,8000,CONT_DIF_P,* +V 11300,9200,CONT_DIF_P,* +V 16400,900,CONT_DIF_N,* +V 7700,7000,CONT_DIF_P,* +V 10300,7000,CONT_DIF_P,* +V 10300,2000,CONT_DIF_N,* +V 7700,2000,CONT_DIF_N,* +V 600,2000,CONT_DIF_N,* +V 600,7000,CONT_DIF_P,* +V 18600,4100,CONT_POLY,* +V 7800,5000,CONT_POLY,* +V 9000,9000,CONT_DIF_P,* +V 6400,9000,CONT_DIF_P,* +V 6600,900,CONT_DIF_N,* +V 4200,7000,CONT_DIF_P,* +V 1800,900,CONT_DIF_N,* +V 1800,9100,CONT_DIF_P,* +V 22000,2000,CONT_DIF_N,* +V 17800,2000,CONT_DIF_N,* +V 22000,6000,CONT_DIF_P,* +V 22000,7000,CONT_DIF_P,* +V 22000,8000,CONT_DIF_P,* +V 20800,4000,CONT_POLY,* +V 13000,5000,CONT_POLY,* +V 13000,3000,CONT_POLY,* +V 20800,5000,CONT_POLY,* +V 16400,3000,CONT_POLY,* +V 14000,4000,CONT_POLY,* +V 11800,7000,CONT_POLY,* +V 10400,4000,CONT_POLY,* +V 6000,3000,CONT_POLY,* +V 3000,5000,CONT_POLY,* +V 21000,7000,CONT_DIF_P,* +V 16000,2000,CONT_POLY,* +V 18600,8000,CONT_DIF_P,* +V 17400,8000,CONT_DIF_P,* +V 21000,6000,CONT_DIF_P,* +V 9000,900,CONT_DIF_N,* +V 11400,900,CONT_DIF_N,* +V 13100,6000,CONT_POLY,* +V 12100,3000,CONT_POLY,* +V 16200,6000,CONT_POLY,* +V 18600,7000,CONT_POLY,* +V 16200,7000,CONT_POLY,* +V 9000,3000,CONT_POLY,* +V 9000,6000,CONT_POLY,* +V 16200,9200,CONT_DIF_P,* +V 4200,3100,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +V 13000,0,CONT_BODY_P,* +V 13000,10000,CONT_BODY_N,* +V 14000,0,CONT_BODY_P,* +V 14000,10000,CONT_BODY_N,* +V 15000,0,CONT_BODY_P,* +V 15000,10000,CONT_BODY_N,* +V 16000,0,CONT_BODY_P,* +V 16000,10000,CONT_BODY_N,* +V 17000,0,CONT_BODY_P,* +V 17000,10000,CONT_BODY_N,* +V 18000,0,CONT_BODY_P,* +V 18000,10000,CONT_BODY_N,* +V 19000,0,CONT_BODY_P,* +V 19000,10000,CONT_BODY_N,* +V 20000,0,CONT_BODY_P,* +V 20000,10000,CONT_BODY_N,* +V 21000,0,CONT_BODY_P,* +V 21000,10000,CONT_BODY_N,* +V 22000,0,CONT_BODY_P,* +V 22000,10000,CONT_BODY_N,* +V 23000,0,CONT_BODY_P,* +V 23000,10000,CONT_BODY_N,* +V 24000,0,CONT_BODY_P,* +V 24000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/sff2_x4.vbe b/pdks/symbolic/nsxlib2/cells/sff2_x4.vbe new file mode 100644 index 000000000..59eaa6446 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/sff2_x4.vbe @@ -0,0 +1,51 @@ +ENTITY sff2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd : NATURAL := 16; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 7; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_cmd_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thr_cmd_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT tsf_cmd_ck : NATURAL := 833; + CONSTANT tsf_i0_ck : NATURAL := 764; + CONSTANT tsf_i1_ck : NATURAL := 764; + CONSTANT tsr_cmd_ck : NATURAL := 770; + CONSTANT tsr_i0_ck : NATURAL := 666; + CONSTANT tsr_i1_ck : NATURAL := 666; + CONSTANT transistors : NATURAL := 34 +); +PORT ( + ck : in BIT; + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff2_x4; + +ARCHITECTURE VBE OF sff2_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff2_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd))); + END BLOCK label0; + + q <= sff_m after 2000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/tie_x0.ap b/pdks/symbolic/nsxlib2/cells/tie_x0.ap new file mode 100644 index 000000000..930b1c7ba --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/tie_x0.ap @@ -0,0 +1,26 @@ +V ALLIANCE : 6 +H tie_x0,P,28/ 5/2024,100 +A 0,0,2000,10000 +S 1000,800,1000,3200,800,*,UP,NDIF +S 1000,5600,1000,9200,800,*,DOWN,PDIF +S 1000,5800,1000,9200,300,*,UP,ALU1 +S 1000,800,1000,3200,300,*,UP,ALU1 +S -200,9500,2200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,2200,500,1400,vss,RIGHT,CALU1 +S -500,7500,2500,7500,6000,*,RIGHT,NWELL +S -200,10000,2200,10000,400,*,RIGHT,NTIE +S -200,0,2200,0,400,*,RIGHT,PTIE +V 1000,6000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 1000,9000,CONT_DIF_P,* +V 1000,3000,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/tie_x0.vbe b/pdks/symbolic/nsxlib2/cells/tie_x0.vbe new file mode 100644 index 000000000..938a45c77 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/tie_x0.vbe @@ -0,0 +1,18 @@ +ENTITY tie_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 500; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END tie_x0; + +ARCHITECTURE behaviour_data_flow OF tie_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on tie_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/nsxlib2/cells/ts_x4.ap b/pdks/symbolic/nsxlib2/cells/ts_x4.ap new file mode 100644 index 000000000..d9b9a9e48 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ts_x4.ap @@ -0,0 +1,154 @@ +V ALLIANCE : 6 +H ts_x4,P,17/ 8/2024,100 +A 0,0,10000,10000 +R 2000,5000,ref_ref,q_15 +R 2000,3000,ref_ref,q_25 +R 3000,6000,ref_ref,cmd_30 +R 3000,7000,ref_ref,cmd_35 +R 3000,8000,ref_ref,cmd_40 +R 3000,4000,ref_ref,cmd_20 +R 3000,5000,ref_ref,cmd_25 +R 2000,4000,ref_ref,q_20 +R 8000,6000,ref_ref,i_30 +R 8000,5000,ref_ref,i_25 +R 8000,4000,ref_ref,i_20 +R 3000,2000,ref_ref,cmd_10 +R 8000,3000,ref_ref,i_15 +R 8000,7000,ref_ref,i_35 +S 1400,4500,9400,4500,200,*,RIGHT,POLY +S 7400,5600,7400,6500,200,*,UP,POLY +S 3800,5600,3800,7500,200,*,UP,POLY +S 8800,2400,8800,3900,200,*,UP,POLY +S 4800,2100,4800,8300,300,*,UP,ALU1 +S 4200,8000,4800,8000,500,4,RIGHT,ALU1 +S 4300,2100,4800,2100,500,*,RIGHT,ALU1 +S 3000,1800,3000,4000,400,*,DOWN,ALU1 +S 3000,5700,4100,5700,300,*,RIGHT,ALU1 +S 4300,7500,4300,9400,600,*,UP,PDIF +S 3000,2900,3900,2900,200,*,RIGHT,POLY +S 7800,2500,7800,3200,200,*,UP,POLY +S 8300,1500,8300,2500,400,*,UP,NDIF +S 7800,1500,7800,2500,200,*,UP,NTRANS +S 6900,1500,6900,2500,600,*,UP,NDIF +S 7500,1500,7500,2500,200,*,UP,NDIF +S 5700,2000,8500,2000,300,*,RIGHT,ALU1 +S 4700,2900,6500,2900,200,*,RIGHT,POLY +S 1400,3800,6000,3800,200,*,RIGHT,POLY +S 4700,6100,6500,6100,200,*,RIGHT,POLY +S 7900,6100,8900,6100,200,*,RIGHT,POLY +S 6900,8000,9500,8000,300,*,RIGHT,ALU1 +S 9300,1800,9300,8200,300,*,UP,ALU1 +S 7700,6500,7700,8500,400,*,UP,PDIF +S 8400,6500,8400,8500,400,*,UP,PDIF +S 9300,6500,9300,8500,400,*,UP,PDIF +S 6900,6800,6900,8200,300,*,UP,ALU1 +S 6900,6500,6900,8500,400,*,UP,PDIF +S 5900,1800,5900,8200,300,*,UP,ALU1 +S 3000,5500,3000,9400,400,*,UP,PDIF +S 3200,7500,3200,9400,600,*,UP,PDIF +S -500,7500,10500,7500,6000,*,RIGHT,NWELL +S 1900,5500,1900,9400,600,*,UP,PDIF +S 900,5500,900,9400,600,*,UP,PDIF +S 1000,5800,1000,8800,300,*,UP,ALU1 +S 1500,4500,1500,5500,200,*,UP,POLY +S 1500,5500,1500,9400,200,*,UP,PTRANS +S 2500,4500,2500,5500,200,*,UP,POLY +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 3200,1500,3200,2500,600,*,UP,NDIF +S 2000,600,2000,2500,600,*,UP,NDIF +S 1000,600,1000,2500,400,*,UP,NDIF +S 1500,600,1500,2500,200,*,UP,NTRANS +S 1000,1200,1000,2200,300,*,UP,ALU1 +S 1500,2500,1500,3900,200,*,UP,POLY +S 2500,2500,2500,3900,200,*,UP,POLY +S 2500,600,2500,2500,200,*,UP,NTRANS +S 7000,3500,7000,5700,300,*,UP,ALU1 +S 7200,800,7200,2500,400,*,UP,NDIF +S 2000,1800,2000,8200,300,q,UP,CALU1 +S 2000,1800,2000,8200,300,*,UP,ALU1 +S 8000,2800,8000,7200,300,i,UP,CALU1 +S 3000,3700,3000,8200,300,cmd,UP,CALU1 +S -200,9500,10200,9500,1400,vdd,RIGHT,CALU1 +S -200,500,10200,500,1400,vss,RIGHT,CALU1 +S 3800,7500,3800,9400,200,*,UP,PTRANS +S 3800,1500,3800,2500,200,*,UP,NTRANS +S 7400,6500,7400,8500,200,*,UP,PTRANS +S 8100,6500,8100,9400,400,*,UP,PDIF +S 9300,1500,9300,2500,400,*,UP,NDIF +S 6400,6500,6400,8500,200,*,UP,PTRANS +S 6900,3800,8900,3800,200,*,RIGHT,POLY +S 6000,6500,6000,8500,600,*,UP,PDIF +S 8800,6000,8800,6500,200,*,UP,POLY +S 3700,5600,7500,5600,200,*,RIGHT,POLY +S 3000,1800,3000,8200,300,*,UP,ALU1 +S 4200,1500,4200,2500,600,*,UP,NDIF +S 3000,600,3000,2500,600,*,UP,NDIF +S 8800,6500,8800,8500,200,*,UP,PTRANS +S 8000,2800,8000,7200,300,*,UP,ALU1 +S 6400,1500,6400,2500,200,*,UP,NTRANS +S 8800,1500,8800,2500,200,*,UP,NTRANS +S 5800,1500,5800,2500,600,*,UP,NDIF +S -200,10000,10200,10000,400,*,RIGHT,NTIE +S -200,0,10200,0,400,*,RIGHT,PTIE +S 6400,6000,6400,6500,200,*,UP,POLY +S 3800,2500,3800,3000,200,*,UP,POLY +S 6400,2500,6400,3000,200,*,UP,POLY +B 4800,2050,200,300,CONT_TURN1,* +V 3200,3000,CONT_POLY,* +V 7000,5400,CONT_POLY,* +V 9300,2000,CONT_DIF_N,* +V 9300,4600,CONT_POLY,* +V 9300,7000,CONT_DIF_P,* +V 9300,8000,CONT_DIF_P,* +V 6900,7000,CONT_DIF_P,* +V 6900,8000,CONT_DIF_P,* +V 5900,8000,CONT_DIF_P,* +V 5900,7000,CONT_DIF_P,* +V 5900,3700,CONT_POLY,* +V 5900,2000,CONT_DIF_N,* +V 4300,2100,CONT_DIF_N,* +V 4400,8000,CONT_DIF_P,* +V 1000,9200,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 1000,7000,CONT_DIF_P,* +V 1000,6000,CONT_DIF_P,* +V 1000,900,CONT_DIF_N,* +V 1000,2000,CONT_DIF_N,* +V 3000,900,CONT_DIF_N,* +V 3900,5700,CONT_POLY,* +V 7200,1000,CONT_DIF_N,* +V 4800,3000,CONT_POLY,* +V 7000,3700,CONT_POLY,* +V 4800,6200,CONT_POLY,* +V 8000,6000,CONT_POLY,* +V 8300,2000,CONT_DIF_N,* +V 3000,9200,CONT_DIF_P,* +V 2000,2000,CONT_DIF_N,* +V 2000,6000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 8100,9200,CONT_DIF_P,* +V 8000,3000,CONT_POLY,* +V 2000,8000,CONT_DIF_P,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/ts_x4.vbe b/pdks/symbolic/nsxlib2/cells/ts_x4.vbe new file mode 100644 index 000000000..25d28a499 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ts_x4.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphl_cmd_q : NATURAL := 409; + CONSTANT tpll_i_q : NATURAL := 444; + CONSTANT tphh_i_q : NATURAL := 475; + CONSTANT tphh_cmd_q : NATURAL := 492; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x4; + +ARCHITECTURE behaviour_data_flow OF ts_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x4" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1100 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/nsxlib2/cells/ts_x8.ap b/pdks/symbolic/nsxlib2/cells/ts_x8.ap new file mode 100644 index 000000000..3189f6d60 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ts_x8.ap @@ -0,0 +1,190 @@ +V ALLIANCE : 6 +H ts_x8,P,17/ 8/2024,100 +A 1000,0,13000,10000 +R 5000,5000,ref_ref,q_25 +R 6000,5000,ref_ref,cmd_25 +R 6000,4000,ref_ref,cmd_20 +R 11000,6000,ref_ref,i_30 +R 11000,5000,ref_ref,i_25 +R 11000,4000,ref_ref,i_20 +R 5000,4000,ref_ref,q_20 +R 5000,3000,ref_ref,q_15 +R 11000,7000,ref_ref,i_35 +R 11000,3000,ref_ref,i_15 +R 6000,2000,ref_ref,cmd_10 +R 6000,6000,ref_ref,cmd_30 +R 6000,7000,ref_ref,cmd_35 +R 6000,8000,ref_ref,cmd_40 +S 500,7500,13500,7500,6000,*,RIGHT,NWELL +S 800,10000,13200,10000,400,*,RIGHT,NTIE +S 800,9500,13200,9500,1400,vdd,RIGHT,CALU1 +S 800,0,13200,0,400,*,RIGHT,PTIE +S 800,500,13200,500,1400,vss,RIGHT,CALU1 +S 6800,5400,10500,5400,200,*,RIGHT,POLY +S 2400,4500,12400,4500,200,*,RIGHT,POLY +S 5500,4500,5500,5500,200,*,UP,POLY +S 2500,4500,2500,5600,200,*,UP,POLY +S 11400,2100,11400,3900,200,*,UP,POLY +S 8900,2200,11100,2200,300,*,RIGHT,ALU1 +S 8900,2200,8900,8200,300,*,UP,ALU1 +S 10900,1600,10900,2300,400,*,DOWN,ALU1 +S 8900,1600,8900,2400,400,*,UP,ALU1 +S 6000,1900,6000,4100,400,*,DOWN,ALU1 +S 9900,900,9900,1600,400,*,UP,ALU1 +S 7200,8000,7900,8000,400,*,RIGHT,ALU1 +S 6000,3100,6700,3100,400,*,LEFT,ALU1 +S 7300,2000,7900,2000,400,*,RIGHT,ALU1 +S 10300,3000,11000,3000,400,*,RIGHT,ALU1 +S 11800,1700,12400,1700,400,*,LEFT,ALU1 +S 6000,6200,7100,6200,300,*,RIGHT,ALU1 +S 3000,4200,5000,4200,300,*,RIGHT,ALU1 +S 11900,1200,11900,2200,400,*,UP,NDIF +S 12300,1500,12300,8200,300,*,UP,ALU1 +S 9600,3800,11400,3800,200,*,RIGHT,POLY +S 11400,1200,11400,2200,200,*,UP,NTRANS +S 10400,2200,10400,3100,200,*,UP,POLY +S 9400,2200,9400,3000,200,*,UP,POLY +S 10000,1200,10000,2200,600,*,UP,NDIF +S 11000,1200,11000,2200,600,*,UP,NDIF +S 10400,1200,10400,2200,200,*,UP,NTRANS +S 9400,1200,9400,2200,200,*,UP,NTRANS +S 8800,1200,8800,2200,600,*,UP,NDIF +S 11300,6500,11300,8500,400,*,UP,PDIF +S 10900,6500,10900,8500,400,*,UP,PDIF +S 9900,6500,9900,8500,400,*,UP,PDIF +S 6900,2500,6900,2900,200,*,UP,POLY +S 6300,2900,7000,2900,200,*,RIGHT,POLY +S 7400,1500,7400,2500,600,*,UP,NDIF +S 6400,1500,6400,2500,600,*,UP,NDIF +S 6900,1500,6900,2500,200,*,UP,NTRANS +S 2500,3800,9000,3800,200,*,RIGHT,POLY +S 2000,5500,2000,9400,600,*,UP,PDIF +S 2000,5800,2000,9400,300,*,UP,ALU1 +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 3500,4500,3500,5500,200,*,UP,POLY +S 3000,5500,3000,9400,600,*,UP,PDIF +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 4000,5500,4000,9400,600,*,UP,PDIF +S 4000,5800,4000,9400,300,*,UP,ALU1 +S 4500,4500,4500,5500,200,*,UP,POLY +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 6500,7500,6500,9400,600,*,UP,PDIF +S 6900,7500,6900,9400,200,*,UP,PTRANS +S 6900,5300,6900,7600,200,*,UP,POLY +S 7300,7500,7300,9400,600,*,UP,PDIF +S 6100,5500,6100,9400,600,*,UP,PDIF +S 4900,5500,4900,9400,600,*,UP,PDIF +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 4000,800,4000,1800,600,*,UP,NDIF +S 5000,600,5000,2500,600,*,UP,NDIF +S 5500,2400,5500,3900,200,*,UP,POLY +S 4500,2500,4500,3900,200,*,UP,POLY +S 1900,600,1900,2500,600,*,UP,NDIF +S 2000,700,2000,2200,300,*,UP,ALU1 +S 2500,2500,2500,3900,200,*,UP,POLY +S 2500,600,2500,2500,200,*,UP,NTRANS +S 4000,600,4000,2500,600,*,UP,NDIF +S 2900,600,2900,2500,600,*,UP,NDIF +S 3500,2500,3500,3900,200,*,UP,POLY +S 3000,1800,3000,8200,300,*,UP,ALU1 +S 3500,600,3500,2500,200,*,UP,NTRANS +S 4000,700,4000,2200,300,*,UP,ALU1 +S 4500,600,4500,2500,200,*,UP,NTRANS +S 6000,600,6000,2500,400,*,UP,NDIF +S 5500,600,5500,2500,200,*,UP,NTRANS +S 10400,5300,10400,6600,200,*,UP,POLY +S 9700,8000,12400,8000,300,*,RIGHT,ALU1 +S 9900,6800,9900,8200,300,*,UP,ALU1 +S 9800,3500,9800,5500,300,*,UP,ALU1 +S 7700,2900,9500,2900,200,*,RIGHT,POLY +S 9400,6500,9400,8500,200,*,UP,PTRANS +S 11000,2800,11000,7200,300,*,UP,ALU1 +S 7800,6100,9500,6100,200,*,RIGHT,POLY +S 7900,1800,7900,8200,300,*,UP,ALU1 +S 9000,6500,9000,8500,600,*,UP,PDIF +S 10900,6100,11900,6100,200,*,RIGHT,POLY +S 11800,6500,11800,8500,200,*,UP,PTRANS +S 6000,1800,6000,8200,300,*,UP,ALU1 +S 12300,6500,12300,8500,400,*,UP,PDIF +S 11100,6500,11100,9200,400,*,UP,PDIF +S 10400,6500,10400,8500,200,*,UP,PTRANS +S 9400,6000,9400,6500,200,*,UP,POLY +S 11800,6000,11800,6500,200,*,UP,POLY +S 6000,3700,6000,8200,300,cmd,UP,CALU1 +S 11000,2800,11000,7200,300,i,UP,CALU1 +S 5000,1800,5000,8200,300,*,UP,ALU1 +S 5000,1800,5000,8200,300,q,UP,CALU1 +B 8900,2200,200,200,CONT_TURN1,* +B 7900,2000,200,200,CONT_TURN1,* +V 9800,3800,CONT_POLY,* +V 6500,3100,CONT_POLY,* +V 12300,4600,CONT_POLY,* +V 12300,8000,CONT_DIF_P,* +V 12300,7000,CONT_DIF_P,* +V 10900,1700,CONT_DIF_N,* +V 11900,1700,CONT_DIF_N,* +V 8900,1800,CONT_DIF_N,* +V 10400,3000,CONT_POLY,* +V 9900,1400,CONT_DIF_N,* +V 8900,7000,CONT_DIF_P,* +V 8900,8000,CONT_DIF_P,* +V 8900,3700,CONT_POLY,* +V 7400,2000,CONT_DIF_N,* +V 2000,9200,CONT_DIF_P,* +V 2000,6000,CONT_DIF_P,* +V 2000,7000,CONT_DIF_P,* +V 2000,8000,CONT_DIF_P,* +V 3000,6000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 4000,9200,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 4000,6000,CONT_DIF_P,* +V 4000,8000,CONT_DIF_P,* +V 7400,8000,CONT_DIF_P,* +V 6000,9200,CONT_DIF_P,* +V 2000,900,CONT_DIF_N,* +V 2000,2000,CONT_DIF_N,* +V 3000,2000,CONT_DIF_N,* +V 4000,900,CONT_DIF_N,* +V 4000,2000,CONT_DIF_N,* +V 6000,900,CONT_DIF_N,* +V 6900,6200,CONT_POLY,* +V 9900,8000,CONT_DIF_P,* +V 9900,7000,CONT_DIF_P,* +V 9800,5300,CONT_POLY,* +V 11100,9000,CONT_DIF_P,* +V 7900,6200,CONT_POLY,* +V 7900,3000,CONT_POLY,* +V 11000,6000,CONT_POLY,* +V 5000,2000,CONT_DIF_N,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +V 12000,0,CONT_BODY_P,* +V 12000,10000,CONT_BODY_N,* +V 13000,0,CONT_BODY_P,* +V 13000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/ts_x8.vbe b/pdks/symbolic/nsxlib2/cells/ts_x8.vbe new file mode 100644 index 000000000..c92f94f59 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/ts_x8.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 400; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_cmd_q : NATURAL := 450; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphl_cmd_q : NATURAL := 466; + CONSTANT tpll_i_q : NATURAL := 569; + CONSTANT tphh_i_q : NATURAL := 613; + CONSTANT tphh_cmd_q : NATURAL := 626; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x8; + +ARCHITECTURE behaviour_data_flow OF ts_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x8" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1200 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/nsxlib2/cells/xr2_x1.ap b/pdks/symbolic/nsxlib2/cells/xr2_x1.ap new file mode 100644 index 000000000..ea28bbba4 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/xr2_x1.ap @@ -0,0 +1,143 @@ +V ALLIANCE : 6 +H xr2_x1,P,14/ 8/2024,100 +A 0,0,8000,10000 +R 6000,5000,ref_ref,i1_20 +R 6000,4000,ref_ref,i1_25 +R 2000,5000,ref_ref,i0_20 +R 2000,4000,ref_ref,i0_25 +R 6000,2000,ref_ref,i1_10 +R 6000,3000,ref_ref,i1_15 +R 6000,8000,ref_ref,i1_40 +R 6000,7000,ref_ref,i1_35 +R 6000,6000,ref_ref,i1_30 +R 3000,6000,ref_ref,q_30 +R 2000,3000,ref_ref,i0_15 +R 2000,2000,ref_ref,i0_10 +R 3000,2000,ref_ref,q_10 +R 2000,6000,ref_ref,i0_30 +R 2000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i0_40 +R 3000,5000,ref_ref,q_25 +R 3000,4000,ref_ref,q_20 +R 3000,3000,ref_ref,q_15 +S 5500,2400,5500,4000,200,*,UP,POLY +S 6500,2400,6500,3000,200,*,UP,POLY +S 3800,3100,6200,3100,300,*,RIGHT,ALU1 +S 3100,2900,4100,2900,200,*,RIGHT,POLY +S 5900,3100,6400,3100,400,*,LEFT,ALU1 +S 5500,5000,6000,5000,400,*,RIGHT,ALU1 +S 5800,5500,5800,9400,400,*,UP,PDIF +S 700,1900,700,8100,300,*,UP,ALU1 +S 7000,1900,7000,8100,300,*,UP,ALU1 +S 3000,6900,3000,8100,300,*,UP,ALU1 +S 4000,5900,4000,7100,300,*,UP,ALU1 +S 3900,4000,3900,5100,300,*,UP,ALU1 +S 3000,2000,4100,2000,300,*,RIGHT,ALU1 +S 3900,4000,5200,4000,300,*,RIGHT,ALU1 +S 3000,6000,4000,6000,300,*,RIGHT,ALU1 +S 3000,1800,3000,6100,300,*,UP,ALU1 +S 3000,1800,3000,6100,300,q,UP,CALU1 +S 5000,5900,5000,8100,300,*,UP,ALU1 +S 5500,4900,5500,5500,200,*,UP,POLY +S 3400,5200,4100,5200,200,*,RIGHT,POLY +S 6500,5000,6500,7200,200,*,UP,POLY +S 5400,5000,6600,5000,200,*,RIGHT,POLY +S 6100,2900,6600,2900,200,*,RIGHT,POLY +S 5200,4000,6900,4000,200,*,RIGHT,POLY +S 1100,5200,2600,5200,200,*,RIGHT,POLY +S 6900,6500,6900,9400,600,*,UP,PDIF +S 5900,6500,5900,9400,600,*,UP,PDIF +S 5100,5500,5100,9400,600,*,UP,PDIF +S 3900,5500,3900,9400,600,*,UP,PDIF +S 3000,5500,3000,9400,400,*,UP,PDIF +S 2000,5500,2000,9400,400,*,UP,PDIF +S 1700,6500,1700,9400,400,*,UP,PDIF +S 7100,600,7100,2500,600,*,UP,NDIF +S 6000,600,6000,2500,600,*,UP,NDIF +S 5000,600,5000,2500,600,*,UP,NDIF +S 3900,600,3900,2500,800,*,UP,NDIF +S 2900,600,2900,2500,400,*,UP,NDIF +S 2000,600,2000,2500,400,*,UP,NDIF +S 1600,1500,1600,2500,400,*,UP,NDIF +S 1200,2400,1200,2800,200,*,UP,POLY +S 1100,2800,2600,2800,200,*,RIGHT,POLY +S 2500,2500,2500,2800,200,*,UP,POLY +S 1200,5200,1200,6600,200,*,UP,POLY +S 2500,5200,2500,5600,200,*,UP,POLY +S 3200,2500,3200,2900,200,*,UP,POLY +S 600,4000,4500,4000,200,*,RIGHT,POLY +S 3500,5200,3500,5500,200,*,UP,POLY +S 4500,2500,4500,5500,200,*,UP,POLY +S 4500,600,4500,2500,200,*,UP,NTRANS +S 5500,600,5500,2500,200,*,UP,NTRANS +S 6500,600,6500,2500,200,*,UP,NTRANS +S 6500,6500,6500,9400,200,*,UP,PTRANS +S 5500,5500,5500,9400,200,*,UP,PTRANS +S 4500,5500,4500,9400,200,*,UP,PTRANS +S 3500,5500,3500,9400,200,*,UP,PTRANS +S 2900,8000,4900,8000,300,*,RIGHT,ALU1 +S 2500,5500,2500,9400,200,*,UP,PTRANS +S 2500,600,2500,2500,200,*,UP,NTRANS +S 1200,6500,1200,9400,200,*,UP,PTRANS +S 700,6500,700,9400,400,*,UP,PDIF +S -500,7500,8500,7500,6000,*,RIGHT,NWELL +S -200,10000,8200,10000,400,*,RIGHT,NTIE +S -200,9500,8200,9500,1400,vdd,RIGHT,CALU1 +S -200,0,8200,0,400,*,RIGHT,PTIE +S -200,500,8200,500,1400,vss,RIGHT,CALU1 +S 6000,1800,6000,8200,300,i1,UP,CALU1 +S 6000,1800,6000,8200,300,*,UP,ALU1 +S 3200,600,3200,2500,200,*,UP,NTRANS +S 2000,1800,2000,8200,300,i0,UP,CALU1 +S 2000,1800,2000,8200,300,*,UP,ALU1 +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 700,1500,700,2500,400,*,UP,NDIF +V 6000,9000,CONT_DIF_P,* +V 1800,9000,CONT_DIF_P,* +B 3000,6000,200,200,CONT_TURN1,* +B 3000,2000,200,200,CONT_TURN1,* +V 3900,3100,CONT_POLY,* +B 3900,4000,200,200,CONT_TURN1,* +V 3900,5000,CONT_POLY,* +V 5600,5000,CONT_POLY,* +V 6300,3100,CONT_POLY,* +V 5300,4000,CONT_POLY,* +V 4000,2000,CONT_DIF_N,* +V 6000,900,CONT_DIF_N,* +V 7000,2000,CONT_DIF_N,* +V 7000,4000,CONT_POLY,* +V 5000,6000,CONT_DIF_P,* +V 5000,7000,CONT_DIF_P,* +V 5000,8000,CONT_DIF_P,* +V 7000,7000,CONT_DIF_P,* +V 7000,8000,CONT_DIF_P,* +V 4000,6000,CONT_DIF_P,* +V 4000,7000,CONT_DIF_P,* +V 3000,7000,CONT_DIF_P,* +V 3000,8000,CONT_DIF_P,* +V 700,2000,CONT_DIF_N,* +V 700,4000,CONT_POLY,* +V 700,7000,CONT_DIF_P,* +V 700,8000,CONT_DIF_P,* +V 2000,5000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 2000,900,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/xr2_x1.vbe b/pdks/symbolic/nsxlib2/cells/xr2_x1.vbe new file mode 100644 index 000000000..925f29ad5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/xr2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY xr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i1_q : NATURAL := 261; + CONSTANT tphl_i0_q : NATURAL := 292; + CONSTANT tplh_i0_q : NATURAL := 293; + CONSTANT tphh_i0_q : NATURAL := 366; + CONSTANT tphl_i1_q : NATURAL := 377; + CONSTANT tpll_i1_q : NATURAL := 388; + CONSTANT tpll_i0_q : NATURAL := 389; + CONSTANT tphh_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x1; + +ARCHITECTURE behaviour_data_flow OF xr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x1" + SEVERITY WARNING; + q <= (i0 xor i1) after 1000 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/xr2_x4.ap b/pdks/symbolic/nsxlib2/cells/xr2_x4.ap new file mode 100644 index 000000000..a935862e0 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/xr2_x4.ap @@ -0,0 +1,183 @@ +V ALLIANCE : 6 +H xr2_x4,P,14/ 8/2024,100 +A 0,0,11000,10000 +R 6000,5000,ref_ref,i1_20 +R 6000,4000,ref_ref,i1_25 +R 2000,5000,ref_ref,i0_20 +R 2000,4000,ref_ref,i0_25 +R 9000,5000,ref_ref,q_25 +R 9000,3000,ref_ref,q_15 +R 9000,4000,ref_ref,q_20 +R 6000,7000,ref_ref,i1_35 +R 6000,6000,ref_ref,i1_30 +R 6000,3000,ref_ref,i1_15 +R 2000,7000,ref_ref,i0_35 +R 2000,8000,ref_ref,i0_40 +R 2000,2000,ref_ref,i0_10 +R 2000,3000,ref_ref,i0_15 +R 2000,6000,ref_ref,i0_30 +S 9500,2500,9500,5500,200,*,UP,POLY +S 6600,4800,6600,5500,200,*,UP,POLY +S 5400,3900,5400,5500,200,*,UP,POLY +S 4400,2400,4400,5500,200,*,UP,POLY +S 2700,1600,2700,6100,300,*,UP,ALU1 +S 2600,1700,8200,1700,300,*,RIGHT,ALU1 +S 2600,6000,3800,6000,300,*,RIGHT,ALU1 +S 8100,4000,8500,4000,500,*,RIGHT,POLY +S 8100,1600,8100,4200,300,*,UP,ALU1 +S 5000,4000,5500,4000,500,*,RIGHT,POLY +S 5000,2900,5000,4200,300,*,UP,ALU1 +S 3200,3000,5100,3000,300,*,RIGHT,ALU1 +S 8000,5500,8000,9400,400,*,UP,PDIF +S 8000,5800,8000,9400,300,*,UP,ALU1 +S 6100,1500,6100,2500,400,*,UP,NDIF +S 6900,1500,6900,2500,400,*,UP,NDIF +S 6500,1500,6500,2500,200,*,UP,NTRANS +S 7100,1500,7100,2600,400,*,UP,NDIF +S 5300,2900,6600,2900,200,*,RIGHT,POLY +S 6500,2500,6500,2900,200,*,UP,POLY +S 4900,600,4900,2500,400,*,UP,NDIF +S 2400,5200,2400,5600,200,*,UP,POLY +S 2400,2400,2400,2800,200,*,UP,POLY +S 1200,2400,1200,2800,200,*,UP,POLY +S 10000,600,10000,2500,400,*,UP,NDIF +S 10000,800,10000,2200,300,*,UP,ALU1 +S 10000,5500,10000,9400,400,*,UP,PDIF +S 10000,5800,10000,9400,300,*,UP,ALU1 +S 9500,5500,9500,9400,200,*,UP,PTRANS +S 9100,5500,9100,9400,400,*,UP,PDIF +S 8900,5500,8900,9400,200,*,UP,PDIF +S 8500,5500,8500,9400,200,*,UP,PTRANS +S 8500,2500,8500,5500,200,*,UP,POLY +S 9000,600,9000,2500,400,*,UP,NDIF +S 9500,600,9500,2500,200,*,UP,NTRANS +S 8500,600,8500,2500,200,*,UP,NTRANS +S 8100,600,8100,2500,600,*,UP,NDIF +S 7000,5500,7000,7500,600,*,UP,PDIF +S 7100,2500,7100,7000,300,*,UP,ALU1 +S 5200,4000,7200,4000,200,*,RIGHT,POLY +S 700,4000,4400,4000,200,*,RIGHT,POLY +S 4900,5500,4900,9400,600,*,UP,PDIF +S 4000,5500,4000,9400,600,*,UP,PDIF +S 3000,5500,3000,9400,600,*,UP,PDIF +S 1600,5500,1600,7500,600,*,UP,PDIF +S 1700,1500,1700,2500,600,*,UP,NDIF +S 1900,600,1900,2500,400,*,UP,NDIF +S 2900,600,2900,2500,400,*,UP,NDIF +S 3900,600,3900,2500,600,*,UP,NDIF +S 4400,600,4400,2500,200,*,UP,NTRANS +S 3400,600,3400,2500,200,*,UP,NTRANS +S 3400,2500,3400,3200,200,*,UP,POLY +S 5400,2500,5400,2900,200,*,UP,POLY +S 5400,600,5400,2500,200,*,UP,NTRANS +S 5900,600,5900,2500,400,*,UP,NDIF +S 6000,5000,6600,5000,400,*,RIGHT,POLY +S 3400,4800,3400,5500,200,*,UP,POLY +S 2700,8000,5100,8000,300,*,RIGHT,ALU1 +S 2900,6800,2900,8200,300,*,UP,ALU1 +S 3400,5500,3400,9400,200,*,UP,PTRANS +S 3900,5800,3900,7200,300,*,UP,ALU1 +S 4400,5500,4400,9400,200,*,UP,PTRANS +S 4900,5800,4900,8200,300,*,UP,ALU1 +S 5400,5500,5400,9400,200,*,UP,PTRANS +S 5800,5500,5800,9400,600,*,UP,PDIF +S 6200,5500,6200,7500,600,*,UP,PDIF +S 5900,7800,5900,9400,300,*,UP,ALU1 +S 6000,2800,6000,7200,300,i1,UP,CALU1 +S 6000,2800,6000,7200,300,*,UP,ALU1 +S 6600,5500,6600,7500,200,*,UP,PTRANS +S 700,1800,700,7200,300,*,UP,ALU1 +S 3200,5000,6200,5000,300,*,RIGHT,ALU1 +S 8300,4000,9500,4000,200,*,RIGHT,POLY +S -500,7500,11500,7500,6000,*,RIGHT,NWELL +S -200,10000,11200,10000,400,*,RIGHT,NTIE +S -200,0,11200,0,400,*,RIGHT,PTIE +S -200,500,11200,500,1400,vss,RIGHT,CALU1 +S 9000,1800,9000,8200,300,*,UP,ALU1 +S 9000,1800,9000,8200,300,q,UP,CALU1 +S -1200,9500,11200,9500,1400,vdd,RIGHT,CALU1 +S 1200,5200,1200,5700,200,*,UP,POLY +S 1100,5200,2500,5200,200,*,RIGHT,POLY +S 1100,2800,2500,2800,200,*,RIGHT,POLY +S 2000,1800,2000,8200,300,i0,UP,CALU1 +S 2000,1800,2000,8200,300,*,UP,ALU1 +S 800,1500,800,2500,600,*,UP,NDIF +S 1200,5500,1200,7500,200,*,UP,PTRANS +S 2000,5500,2000,9400,600,*,UP,PDIF +S 800,5500,800,7500,600,*,UP,PDIF +S 2400,5500,2400,9400,200,*,UP,PTRANS +S 1200,1500,1200,2500,200,*,UP,NTRANS +S 2400,600,2400,2500,200,*,UP,NTRANS +B 5000,3000,200,200,CONT_TURN1,* +B 3900,6000,200,200,CONT_TURN1,* +B 2700,6000,200,200,CONT_TURN1,* +B 8100,1700,200,200,CONT_TURN1,* +B 2700,1700,200,200,CONT_TURN1,* +V 8100,4000,CONT_POLY,* +V 5000,4000,CONT_POLY,* +V 1900,900,CONT_DIF_N,* +V 1900,9200,CONT_DIF_P,* +V 8000,9200,CONT_DIF_P,* +V 8000,6000,CONT_DIF_P,* +V 8000,7000,CONT_DIF_P,* +V 8000,8000,CONT_DIF_P,* +V 6000,3100,CONT_POLY,* +V 7100,2400,CONT_DIF_N,* +V 10000,900,CONT_DIF_N,* +V 10000,2000,CONT_DIF_N,* +V 10000,6000,CONT_DIF_P,* +V 10000,7000,CONT_DIF_P,* +V 10000,9200,CONT_DIF_P,* +V 10000,8000,CONT_DIF_P,* +V 9000,8000,CONT_DIF_P,* +V 9000,7000,CONT_DIF_P,* +V 9000,6000,CONT_DIF_P,* +V 9000,2000,CONT_DIF_N,* +V 8000,900,CONT_DIF_N,* +V 3900,1700,CONT_DIF_N,* +V 3400,3000,CONT_POLY,* +V 5900,900,CONT_DIF_N,* +V 7100,4000,CONT_POLY,* +V 2900,8000,CONT_DIF_P,* +V 2900,7000,CONT_DIF_P,* +V 3900,7000,CONT_DIF_P,* +V 4900,6000,CONT_DIF_P,* +V 4900,8000,CONT_DIF_P,* +V 4900,7000,CONT_DIF_P,* +V 5900,8000,CONT_DIF_P,* +V 7100,5800,CONT_DIF_P,* +V 7100,6800,CONT_DIF_P,* +V 5900,9200,CONT_DIF_P,* +V 700,7000,CONT_DIF_P,* +V 700,6000,CONT_DIF_P,* +V 700,4000,CONT_POLY,* +V 700,2000,CONT_DIF_N,* +V 3400,5000,CONT_POLY,* +V 6000,5000,CONT_POLY,* +V 2000,5000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +V 4000,0,CONT_BODY_P,* +V 4000,10000,CONT_BODY_N,* +V 5000,0,CONT_BODY_P,* +V 5000,10000,CONT_BODY_N,* +V 6000,0,CONT_BODY_P,* +V 6000,10000,CONT_BODY_N,* +V 7000,0,CONT_BODY_P,* +V 7000,10000,CONT_BODY_N,* +V 8000,0,CONT_BODY_P,* +V 8000,10000,CONT_BODY_N,* +V 9000,0,CONT_BODY_P,* +V 9000,10000,CONT_BODY_N,* +V 10000,0,CONT_BODY_P,* +V 10000,10000,CONT_BODY_N,* +V 11000,0,CONT_BODY_P,* +V 11000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/xr2_x4.vbe b/pdks/symbolic/nsxlib2/cells/xr2_x4.vbe new file mode 100644 index 000000000..7e2da9edb --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/xr2_x4.vbe @@ -0,0 +1,36 @@ +ENTITY xr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 357; + CONSTANT tphh_i0_q : NATURAL := 476; + CONSTANT tpll_i0_q : NATURAL := 480; + CONSTANT tphl_i0_q : NATURAL := 521; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphl_i1_q : NATURAL := 541; + CONSTANT tplh_i0_q : NATURAL := 560; + CONSTANT tplh_i1_q : NATURAL := 657; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x4; + +ARCHITECTURE behaviour_data_flow OF xr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x4" + SEVERITY WARNING; + q <= (i0 xor i1) after 1300 ps; +END; diff --git a/pdks/symbolic/nsxlib2/cells/zero_x0.ap b/pdks/symbolic/nsxlib2/cells/zero_x0.ap new file mode 100644 index 000000000..1bc5f1160 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/zero_x0.ap @@ -0,0 +1,40 @@ +V ALLIANCE : 6 +H zero_x0,P,14/ 8/2024,100 +A 0,0,3000,10000 +R 2000,2000,ref_ref,nq_10 +R 2000,3000,ref_ref,nq_15 +R 2000,4000,ref_ref,nq_20 +R 2000,5000,ref_ref,nq_25 +R 2000,6000,ref_ref,nq_30 +R 2000,7000,ref_ref,nq_35 +R 2000,8000,ref_ref,nq_40 +S 1400,3400,1400,4500,200,*,UP,POLY +S 800,1100,800,3200,400,*,UP,ALU1 +S 800,2500,800,3500,600,*,UP,NDIF +S 1000,6100,1000,9200,1000,*,DOWN,PDIF +S 900,4500,1500,4500,400,*,RIGHT,POLY +S 2000,1800,2000,8200,300,nq,UP,CALU1 +S 1000,3800,1000,9600,300,*,UP,ALU1 +S 1400,2500,1400,3500,200,*,UP,NTRANS +S 2000,2500,2000,3500,600,*,UP,NDIF +S -500,7500,3500,7500,6000,*,RIGHT,NWELL +S -200,10000,3200,10000,400,*,RIGHT,NTIE +S -200,0,3200,0,400,*,RIGHT,PTIE +S 2000,1800,2000,8200,300,*,UP,ALU1 +S -200,500,3200,500,1400,vss,RIGHT,CALU1 +S -200,9500,3200,9500,1400,vdd,RIGHT,CALU1 +V 1000,7000,CONT_DIF_P,* +V 1000,8000,CONT_DIF_P,* +V 1000,9000,CONT_DIF_P,* +V 1000,4600,CONT_POLY,* +V 800,3000,CONT_DIF_N,* +V 2000,3000,CONT_DIF_N,* +V 0,0,CONT_BODY_P,* +V 0,10000,CONT_BODY_N,* +V 1000,0,CONT_BODY_P,* +V 1000,10000,CONT_BODY_N,* +V 2000,0,CONT_BODY_P,* +V 2000,10000,CONT_BODY_N,* +V 3000,0,CONT_BODY_P,* +V 3000,10000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/nsxlib2/cells/zero_x0.vbe b/pdks/symbolic/nsxlib2/cells/zero_x0.vbe new file mode 100644 index 000000000..535efebc9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/cells/zero_x0.vbe @@ -0,0 +1,20 @@ +ENTITY zero_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END zero_x0; + +ARCHITECTURE behaviour_data_flow OF zero_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on zero_x0" + SEVERITY WARNING; + nq <= '0'; +END; diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/__init__.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/Gf180mcuSetup.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/Gf180mcuSetup.py new file mode 100644 index 000000000..0ed42aa56 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/Gf180mcuSetup.py @@ -0,0 +1,96 @@ + +import sys +import os +import socket +from pathlib import Path +from coriolis.designflow.task import ShellEnv + + +__all__ = [ 'Where', 'setupGf180mcu_nsx2 ' ] + + +class Where ( object ): + + coriolisTop = None + allianceTop = None + cellsTop = None + checkToolkit = None + + def __init__ ( self, checkToolkit=None ): + if 'CORIOLIS_TOP' in os.environ: Where.coriolisTop = Path( os.environ['CORIOLIS_TOP'] ) + if 'ALLIANCE_TOP' in os.environ: Where.allianceTop = Path( os.environ['ALLIANCE_TOP'] ) + if 'CELLS_TOP' in os.environ: Where.cellsTop = Path( os.environ['CELLS_TOP'] ) + if Where.coriolisTop and not Where.allianceTop: Where.allianceTop = Where.coriolisTop + #print( Where.coriolisTop, Where.allianceTop ) + if not Where.coriolisTop: + print( 'technos.Where.__init__(): Unable to locate Coriolis top.' ) + if checkToolkit is None: + checkToolkit = Path.home() / 'coriolis-2.x' / 'src' / 'alliance-check-toolkit' + else: + if isinstance(checkToolkit,str): + checkToolkit = Path( checkToolkit ) + if not Where.cellsTop: + Where.cellsTop = checkToolkit / 'cells' + Where.checkToolkit = checkToolkit + if not Where.cellsTop and Where.allianceTop: + Where.cellsTop = Where.allianceTop / 'cells' + ShellEnv.ALLIANCE_TOP = Where.allianceTop.as_posix() + + def __repr__ ( self ): + if not Where.coriolisTop: + return '' + return ''.format( Where.coriolisTop.as_posix() ) + + +def setupGf180mcu_nsx2 ( checkToolkit=None ): + Where( checkToolkit ) + ShellEnv().export() + + pdkDir = Where.checkToolkit / 'dks' / 'gf180mcu_nsx2' / 'libs.tech' + coriolisTechDir = pdkDir / 'coriolis' + if not pdkDir.is_dir(): + print( '[ERROR] technos.setupGf180mcu_nsx2(): PDK directory do *not* exists:' ) + print( ' "{}"'.format(techDir.as_posix()) ) + sys.path.append( coriolisTechDir.as_posix() ) + + cellsTop = Where.checkToolkit / 'cells' + liberty = coriolisTechDir / 'gf180mcu_nsx2' / 'nsxlib2.lib' +# kdrcRules = pdkDir / 'klayout' / 'drc' / 'gf180mcu.drc' + + from coriolis import Cfg + from coriolis import Viewer + from coriolis import CRL + from coriolis.helpers import overlay, l, u, n + from coriolis.designflow.yosys import Yosys + from coriolis.designflow.klayout import DRC + from gf180mcu_nsx2 import techno, nsxlib2 + techno.setup( coriolisTechDir ) + nsxlib2.setup( cellsTop ) + + with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.misc.minTraceLevel = 1900 + cfg.misc.maxTraceLevel = 3000 + cfg.katana.eventsLimit = 1000000 + cfg.katana.termSatReservedLocal = 6 + cfg.katana.termSatThreshold = 9 + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + Yosys.setLiberty( liberty ) +# DRC.setDrcRules( kdrcRules ) + ShellEnv.CHECK_TOOLKIT = Where.checkToolkit.as_posix() + + path = None + for pathVar in [ 'PATH', 'path' ]: + if pathVar in os.environ: + path = os.environ[ pathVar ] + os.environ[ pathVar ] = path + ':' + (Where.allianceTop / 'bin').as_posix() + break + + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/__init__.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/__init__.py new file mode 100644 index 000000000..b87e091fc --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/__init__.py @@ -0,0 +1,5 @@ + +import os +from pathlib import Path + +path = Path( os.path.dirname(os.path.abspath(__file__)) ) diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/gf180mcu.rds b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/gf180mcu.rds new file mode 100644 index 000000000..15b45b77a --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/gf180mcu.rds @@ -0,0 +1,737 @@ +# 20240527 +# --------------------------------------------------------------------------- +# For GF180mcu by Naohiko Shimizu +# --------------------------------------------------------------------------- + + + + +# ------------------------------------------------------------------- +# globals define +# ------------------------------------------------------------------- + +define physical_grid 0.005 +define lambda 0.105 + +table cif_layer +# ------------------------------------------------------------------- +# rds_name cif_name +# ------------------------------------------------------------------- + rds_nwell nwell +# rds_pwell pwel + rds_activ diff + rds_ntie tap + rds_ptie tap + rds_ndif nsdm + rds_pdif psdm + rds_nimp nsdm + rds_pimp psdm + rds_poly poly + rds_alu1 li1 + rds_alu2 met1 + rds_alu3 met2 + rds_alu4 met3 + rds_alu5 met4 + rds_alu6 met5 + rds_cont licon1 + rds_via1 mcon + rds_via2 via + rds_via3 via2 + rds_via4 via3 + rds_via5 via4 + rds_talu8 npc + rds_cpas pad +end + +table gds_layer +# ------------------------------------------------------------------- +# rds_name gds_number gds_datatype +# IHP uses only 0 gds_datatype for drawing +# ------------------------------------------------------------------- + rds_nwell 21 0 + rds_pwell 204 0 + rds_activ 22 0 + rds_ptie 22 0 + rds_ntie 22 0 + rds_pdif 22 0 + rds_ndif 22 0 + rds_pimp 31 0 + rds_nimp 32 0 + rds_poly 30 0 30 10 + rds_alu1 34 0 34 10 + rds_alu2 36 0 36 10 + rds_alu3 42 0 42 10 + rds_alu4 46 0 46 10 + rds_alu5 81 0 81 10 + rds_alu6 53 0 53 10 + rds_cont 33 0 + rds_via1 35 0 + rds_via2 38 0 + rds_via3 40 0 + rds_via4 41 0 + rds_via5 82 0 + rds_cpas 9 0 +# use talu8 as Deep NWELL + rds_talu8 12 0 +end + +table lynx_resistor +# ------------------------------------------------------------------- +# rds_name square_resistor(ohm/square) # typical values +# ------------------------------------------------------------------- +# Poly resistor is differ from N-doped to P-doped. 7 ohm is for N-doped. +# P-doped poly is 260 ohm + + rds_poly 7 + rds_alu1 0.115 + rds_alu2 0.088 + rds_alu3 0.088 + rds_alu4 0.088 + rds_alu5 0.088 + rds_alu6 0.018 + rds_cont 15 + rds_via1 9 + rds_via2 9 + rds_via3 9 + rds_via4 9 + rds_via5 2.2 +end + +table lynx_capa +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- + rds_poly 35.3e-3 51.8e-6 # Ca max POLY_NWELL 2Cf0 max POLY_NWELL + rds_alu1 5.9e-5 8.5e-5 # Ca max M1_NWELL 2Cf0 max M1_NWELL + rds_alu2 6.8e-5 7.9e-5 # Ca max M2_NWELL 2Cf0 max M2_NWELL + rds_alu3 6.8e-5 6.8e-5 # Ca max M3_NWELL 2Cf0 max M3_NWELL + rds_alu4 6.8e-5 6.0e-5 # Ca max M4_NWELL 2Cf0 max M4_NWELL + rds_alu5 6.8e-5 6.0e-5 # hyp + rds_alu6 4.2e-5 6.0e-5 +end + +table lynx_capa_poly +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_poly2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu1 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu3 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu4 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu5 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end +table mbk_to_rds_segment +# ---------------------------------------------------------------------------------- +# mbk_name rds_name1 dlr dwr offset mode rds_name2 dlr dwr offset mode +# ---------------------------------------------------------------------------------- + talu8 rds_talu8 vw 0.00 0.00 .0 all + + nwell rds_nwell vw 0.02 -0.08 .180 all\ + rds_pwell vw 0.02 -1.65 5.875 all \ + rds_pimp vw 0.0 -1.01 .420 all \ + rds_nimp vw 0.0 -2.40 5.500 all + +# pwell rds_pwell vw 0.460 0.280 .0 all +# rds_pimp vw 0.225 0.170 .0 all + + ndif rds_activ vw -0.03 0.020 .0 all\ + rds_ndif vw -0.03 0.020 .0 all + + pdif rds_activ vw -0.03 0.020 .0 all\ + rds_pdif vw -0.03 0.020 .0 all + + ntie rds_ntie vw 0.105 -0.060 .0 all\ + rds_nimp vw 0.430 0.260 .0 all\ +# rds_nwell vw 0.430 0.510 .0 all + + ptie rds_ptie vw 0.105 -0.060 .0 all\ + rds_pimp vw 0.430 0.260 .0 all +# rds_pwell vw 0.430 0.510 .0 all + + ntrans rds_poly vw 0.19 0.07 .0 all\ + rds_activ vw -0.03 0.64 .0 all\ + rds_ndif lcw -0.03 0.32 0. all\ + rds_ndif rcw -0.03 0.32 0. all + + ptrans rds_poly vw 0.19 0.07 .0 all\ + rds_activ vw -0.03 0.64 .0 all\ + rds_pdif lcw -0.03 0.32 0. all\ + rds_pdif rcw -0.03 0.32 0. all + + poly rds_poly vw 0.00 0.07 .0 all + + alu1 rds_alu1 vw 0.01 0.02 .0 all + calu1 rds_alu1 vw 0.01 0.02 .0 all + talu1 rds_talu1 vw 0.01 0.02 .0 all + + alu2 rds_alu2 vw 0.11 0.0 .0 all + calu2 rds_alu2 vw 0.11 0.0 .0 all + talu2 rds_talu2 vw 0.11 0.0 .0 all + + alu3 rds_alu3 vw 0.11 0.0 .0 all + calu3 rds_alu3 vw 0.11 0.0 .0 all + talu3 rds_talu3 vw 0.11 0.0 .0 all + + alu4 rds_alu4 vw 0.15 0.0 .0 all + calu4 rds_alu4 vw 0.15 0.0 .0 all + talu4 rds_talu4 vw 0.15 0.0 .0 all + + alu5 rds_alu5 vw 0.15 0.0 .0 all + calu5 rds_alu5 vw 0.15 0.0 .0 all + talu5 rds_talu5 vw 0.15 0.0 .0 all +end + +table mbk_to_rds_connector +# ------------------------------------------------------------------- +# mbk_name rds_name der dwr +# ------------------------------------------------------------------- +end + +table mbk_to_rds_reference +# ------------------------------------------------------------------- +# mbk_name rds_name width +# ------------------------------------------------------------------- + ref_ref rds_ref 0.390 + ref_con rds_ref 0.390 +end + +table mbk_to_rds_via +# ------------------------------------------------------------------- +# mbk_name rds_name1 width mode rds_name2 width mode ... +## ------------------------------------------------------------------ +# difftap.5 +# licon.7 0.170+0.120*2 + cont_body_n \ + rds_cont 0.220 all\ + rds_alu1 0.390 all\ +# rds_nimp 0.430 all\ + rds_ntie 0.360 all + +# licon.7 0.170+0.120*2 +# difftap.5 + cont_body_p \ + rds_cont 0.220 all\ + rds_alu1 0.390 all\ + rds_pimp 0.360 all\ + rds_ptie 0.360 all + +# licon.5c + cont_dif_n \ + rds_cont 0.220 all\ + rds_alu1 0.390 all\ + rds_activ 0.360 drc\ + rds_ndif 0.360 ext + +# licon.5c + cont_dif_p \ + rds_cont 0.220 all\ + rds_alu1 0.390 all\ + rds_activ 0.360 drc\ + rds_pimp 0.360 all\ + rds_pdif 0.360 ext + +# copy + cont_poly \ + rds_cont 0.220 all\ + rds_poly 0.360 all\ + rds_alu1 0.390 all + + + +# m1.4 +# NPC --> poly2 +# m1.5 + cont_via \ + rds_via1 0.260 all\ + rds_alu1 0.390 all\ + rds_alu2 0.390 all + +# via.1b +# via.5b +# m2.5 + cont_via2 \ + rds_via2 0.260 all\ + rds_alu2 0.390 all\ + rds_alu3 0.380 all + +# via.1b +# via.5b +# m2.5 + cont_via3 \ + rds_via3 0.260 all\ + rds_alu3 0.380 all\ + rds_alu4 0.380 all + + cont_via4 \ + rds_via4 0.260 all\ + rds_alu4 0.380 all\ + rds_alu5 0.380 all + + cont_via5 \ + rds_via5 0.260 all\ + rds_alu5 0.380 all\ + rds_alu6 0.380 all +end + +table mbk_to_rds_bigvia_hole +# ------------------------------------------------------------------- +# mbk_via_name rds_hole_name side step mode +# ------------------------------------------------------------------- +CONT_DIF_P RDS_CONT 0.22 0.50 ALL +CONT_DIF_N RDS_CONT 0.22 0.50 ALL +CONT_BODY_P RDS_CONT 0.22 0.50 ALL +CONT_BODY_N RDS_CONT 0.22 0.50 ALL +CONT_VIA RDS_VIA1 0.26 0.62 ALL +CONT_VIA2 RDS_VIA2 0.26 0.62 ALL +CONT_VIA3 RDS_VIA3 0.26 0.62 ALL +CONT_VIA4 RDS_VIA4 0.26 0.62 ALL +CONT_VIA5 RDS_VIA5 0.26 0.62 ALL +end + +table mbk_to_rds_bigvia_metal +# ------------------------------------------------------------------- +# mbk_via_name rds_name dwr overlap mode +# ------------------------------------------------------------------- +CONT_DIF_P RDS_ALU1 0.12 0.14 ALL +CONT_DIF_N RDS_ALU1 0.12 0.14 ALL +CONT_BODY_P RDS_ALU1 0.12 0.14 ALL +CONT_BODY_N RDS_ALU1 0.12 0.14 ALL +CONT_VIA RDS_ALU2 0.12 0.12 ALL +CONT_VIA2 RDS_ALU3 0.12 0.12 ALL +CONT_VIA3 RDS_ALU4 0.12 0.12 ALL +CONT_VIA4 RDS_ALU5 0.12 0.12 ALL +CONT_VIA5 RDS_ALU6 0.12 0.12 ALL +end + +table mbk_to_rds_turnvia +# ------------------------------------------------------------------- +# mbk_name rds_name dwr mode +# ------------------------------------------------------------------- + cont_turn1 rds_alu1 0.125 all + cont_turn2 rds_alu2 0.00 all + cont_turn3 rds_alu3 0.00 all + cont_turn4 rds_alu4 0.00 all + cont_turn5 rds_alu5 0.00 all +end + +table lynx_bulk_implicit +# ------------------------------------------------------------------- +# rds_name type[explicit|implicit] +# ------------------------------------------------------------------- +end + +table lynx_transistor +# ------------------------------------------------------------------- +# mbk_name trans_name compostion +# ------------------------------------------------------------------- + ntrans ntrans c_x_n rds_poly rds_ndif rds_ndif rds_pwell + ptrans ptrans c_x_p rds_poly rds_pdif rds_pimp rds_nwell +end + +table lynx_diffusion +# ------------------------------------------------------------------- +# rds_name compostion +# ------------------------------------------------------------------- +end + +table lynx_graph +# ------------------------------------------------------------------- +# rds_name in_contact_with rds_name1 rds_name2 ... +# ------------------------------------------------------------------- + rds_ndif rds_cont rds_ndif + rds_pdif rds_cont rds_pdif + rds_poly rds_cont rds_poly + rds_cont rds_pdif rds_ndif rds_poly rds_alu1 rds_cont + rds_alu1 rds_cont rds_via1 rds_ref rds_alu1 + rds_ref rds_cont rds_via1 rds_alu1 rds_ref + RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 + RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 + RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 + RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 + RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 + rds_alu2 rds_via1 rds_via2 rds_alu2 + rds_alu3 rds_via2 rds_via3 rds_alu3 + rds_alu4 rds_via3 rds_via4 rds_alu4 + rds_alu5 rds_via4 rds_via5 rds_alu5 +end + +table s2r_oversize_denotch +# ------------------------------------------------------------------- +# rds_name oversized_value_for_denotching +# ------------------------------------------------------------------- + rds_nwell 0.635 + rds_pwell 0.635 + rds_poly 0.100 + rds_alu1 0.080 + rds_alu2 0.080 + rds_alu3 0.080 + rds_alu4 0.080 + rds_alu5 0.080 + rds_activ 0.130 + rds_ntie 0.190 + rds_ptie 0.190 + rds_nimp 0.150 + rds_pimp 0.150 +end + +table s2r_bloc_ring_width +# ------------------------------------------------------------------- +# rds_name ring_width_to_copy_up +# ------------------------------------------------------------------- + rds_nwell 0. # [ RD_NWEL ] + rds_pwell 0. # [ RD_PWEL ] + rds_poly 0. # [ RD_POLY ] + rds_alu1 0. # [ RD_ALU1 ] + rds_alu2 0. # [ RD_ALU2 ] + rds_alu3 0. # [ RD_ALU3 ] + rds_alu4 0. # [ RD_ALU3 ] + rds_alu5 0. # [ RD_ALU3 ] + rds_activ 0. # [ RD_ACTI ] + rds_ntie 0. # [ RD_NIMP ] + rds_ptie 0. # [ RD_PIMP ] + rds_nimp 0. # [ RD_NIMP ] + rds_pimp 0. # [ RD_PIMP ] +end + +table s2r_minimum_layer_width +# ------------------------------------------------------------------- +# rds_name min_layer_width_to_keep +# ------------------------------------------------------------------- + rds_nwell 1.7 + rds_pwell 0.6 + rds_poly 0.180 + rds_alu1 0.230 + rds_alu2 0.280 + rds_alu3 0.280 + rds_alu4 0.280 + rds_alu5 0.280 + rds_activ 0.220 + rds_ntie 0.220 + rds_ptie 0.220 + rds_nimp 0.400 + rds_pimp 0.400 +end + +table s2r_post_treat +# ------------------------------------------------------------------- +# rds_name s2r_must_treat_or_not second_layer_whenever_scotch +# ------------------------------------------------------------------- + rds_nwell treat rds_pwell + rds_pwell treat rds_nwell + rds_poly treat null + rds_activ treat null + rds_ntie treat rds_pimp + rds_ptie treat rds_nimp + rds_nimp treat rds_ptie + rds_pimp treat rds_ntie + rds_alu1 treat null + rds_alu2 treat null + rds_alu3 treat null + rds_alu4 treat null + rds_alu5 treat null + rds_cont notreat null +end + +DRC_RULES + +layer RDS_NWELL 0.840 ; +layer RDS_PWELL 0.840 ; +layer RDS_NTIE 0.380 ; +layer RDS_PTIE 0.380 ; +layer RDS_NIMP 0.380 ; +layer RDS_PIMP 0.380 ; +layer RDS_ACTIV 0.420 ; +layer RDS_CONT 0.170 ; +layer RDS_POLY 0.150 ; +layer RDS_ALU1 0.140 ; +layer RDS_ALU2 0.140 ; +layer RDS_ALU3 0.140 ; +layer RDS_ALU4 0.300 ; +layer RDS_ALU5 0.300 ; +layer RDS_VIA1 0.140 ; +layer RDS_USER0 0.005 ; +layer RDS_USER1 0.005 ; +layer RDS_USER2 0.005 ; + +regles + +# note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# there is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# ---------------------------------------------------------- + +# check the nwell shapes +# ---------------------- +characterize RDS_NWELL ( + rule 1 : width >= 0.86 ; + rule 2 : intersection_length min 0.86 ; + rule 3 : notch >= 0.6 ; +); +relation RDS_NWELL , RDS_NWELL ( + rule 4 : spacing axial min 0.6 ; +); +characterize RDS_PWELL ( + rule 5 : width >= 0.6 ; + rule 6 : intersection_length min 0.6 ; + rule 7 : notch >= 0.86 ; +); +relation RDS_PWELL , RDS_PWELL ( + rule 8 : spacing axial min 0.86 ; +); + +relation RDS_PWELL , RDS_NWELL ( + rule 9 : spacing axial min 0.0 ; +); + + +relation RDS_NWELL , RDS_ACTI ( + rule 10 : spacing axial min 0.12 ; +); + +# check the RDS_PIMP shapes +# ------------------------- +characterize RDS_PIMP ( + rule 11 : surface min 0.35 ; + rule 12 : width >= 0.4 ; + rule 13 : intersection_length min 0.4 ; + rule 14 : notch >= 0.4 ; +); +relation RDS_PIMP , RDS_PIMP ( + rule 15 : spacing axial min 0.4 ; +); + + +# check the RDS_NIMP shapes +# ------------------------- +characterize RDS_NIMP ( + rule 16 : surface min 0.35 ; + rule 17 : width >= 0.4 ; + rule 18 : intersection_length min 0.4 ; + rule 19 : notch >= 0.4 ; +); +relation RDS_NIMP , RDS_NIMP ( + rule 20 : spacing axial min 0.4 ; +); + + +# check the RDS_PTIE shapes +# ------------------------- +characterize RDS_PTIE ( + rule 21 : surface min 0.205 ; + rule 22 : width >= 0.22 ; + rule 23 : intersection_length min 0.22 ; + rule 24 : notch >= 0.28 ; +); +relation RDS_PTIE , RDS_PTIE ( + rule 25 : spacing axial min 0.28 ; +); + +# check the RDS_NTIE shapes +# ------------------------- +characterize RDS_NTIE ( + rule 26 : surface min 0.205 ; + rule 27 : width >= 0.22 ; + rule 28 : intersection_length min 0.22 ; + rule 29 : notch >= 0.28 ; +); +relation RDS_NTIE , RDS_NTIE ( + rule 30 : spacing axial min 0.28 ; +); + +# check the RDS_ACTI shapes +# ------------------------- +characterize RDS_ACTI ( + rule 31 : surface min 0.205 ; + rule 32 : width >= 0.22 ; + rule 33 : intersection_length min 0.22 ; + rule 34 : notch >= 0.28 ; +); +relation RDS_ACTI, RDS_ACTI ( + rule 35 : spacing axial min 0.28 ; +); + +# check the RDS_NIMP RDS_PTIE exclusion +# ------------------------------------- +define RDS_NIMP , RDS_PTIE intersection -> NPIMP; +characterize NPIMP ( + rule 36 : width = 0. ; +); +undefine NPIMP; + +# check the RDS_NTIE RDS_PIMP exclusion +# ------------------------------------- +define RDS_NTIE , RDS_PIMP intersection -> NPIMP; +characterize NPIMP ( + rule 37 : width = 0. ; +); +undefine NPIMP; + +# check the RDS_POLY shapes +# ------------------------- +characterize RDS_POLY ( + rule 38 : width >= 0.18 ; + rule 39 : intersection_length min 0.18 ; + rule 40 : notch >= 0.24 ; +); +relation RDS_POLY , RDS_POLY ( + rule 41 : spacing axial min 0.24 ; +); + +define RDS_ACTI , RDS_POLY intersection -> channel; + + # check the channel shapes + # ------------------------- + characterize channel ( + rule 42 : width >= 0.28 ; + rule 43 : notch >= 0.24 ; + ); + relation channel , channel ( + rule 44 : spacing axial min 0.24 ; + ); + +undefine channel; + +define RDS_ACTI , RDS_CONT intersection -> cont_diff; + + relation RDS_POLY , cont_diff ( + rule 45 : spacing axial >= 0.15 ; + ); + +# check cont layers, stacking are free +# --------------------------------------- +relation RDS_CONT , RDS_CONT ( + rule 46 : spacing axial >= 0.25 ; +); + +characterize RDS_CONT ( + rule 47 : width = 0.22 ; + rule 48 : length = 0.22 ; +); + +# check RDS_POLY is distant from activ zone of transistor +# ------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + rule 49 : spacing axial >= 0.1 ; +); +undefine cont_diff; + +# check RDS_ALU1 shapes +# --------------------- +characterize RDS_ALU1 ( + rule 50 : surface min 0.145 ; + rule 51 : width >= 0.23 ; + rule 52 : intersection_length min 0.23 ; + rule 53 : notch >= 0.23 ; +); +relation RDS_ALU1 , RDS_ALU1 ( + rule 54 : spacing axial min 0.23 ; +); + + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_VIA1 , RDS_VIA1 ( + rule 55 : spacing axial >= 0.26 ; +); + +characterize RDS_VIA1 ( + rule 56 : width = 0.26 ; + rule 57 : length = 0.26 ; +); + +end rules +DRC_COMMENT +1 (RDS_NWELL) Minimum width 0.86 +2 (RDS_NWELL) Intersection length 0.86 +3 (RDS_NWELL) Notch 0.6 +4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 0.6 +5 (RDS_PWELL) Minimum width 0.6 +6 (RDS_PWELL) Intersection length 0.6 +7 (RDS_PWELL) Notch 0.86 +8 (RDS_PWELL,RDS_PWELL) Manhatan distance min 0.86 +9 (RDS_PWELL,RDS_NWELL) Manhatan distance min 0.0 +10 (RDS_NWELL,RDS_ACTI) Manhatan distance min 0.12 +11 (RDS_PIMP) Minimum area 0.35 +12 (RDS_PIMP) Minimum width 0.4 +13 (RDS_PIMP) Intersection length 0.4 +14 (RDS_PIMP) Notch 0.4 +15 (RDS_PIMP,RDS_PIMP) Manhatan distance min 0.4 +16 (RDS_NIMP) Minimum area 0.35 +17 (RDS_NIMP) Minimum width 0.4 +18 (RDS_NIMP) Intersection length 0.4 +19 (RDS_NIMP) Notch 0.4 +20 (RDS_NIMP,RDS_NIMP) Manhatan distance min 0.4 +21 (RDS_PTITE) Minimum area 0.205 +22 (RDS_PTITE) Minimum width 0.22 +23 (RDS_PTITE) Intersection length 0.22 +24 (RDS_PTITE) Notch 0.28 +25 (RDS_PTITE,RDS_PTITE) Manhatan distance min 0.28 +26 (RDS_NTITE) Minimum area 0.205 +27 (RDS_NTITE) Minimum width 0.22 +28 (RDS_NTITE) Intersection length 0.22 +29 (RDS_NTITE) Notch 0.28 +30 (RDS_NTITE,RDS_NTITE) Manhatan distance min 0.22 +31 (RDS_ACTI) Minimum area 0.205 +32 (RDS_ACTI) Minimum width 0.22 +33 (RDS_ACTI) Intersection length 0.22 +34 (RDS_ACTI) Notch 0.28 +35 (RDS_ACTI,RDS_ACTI) Manhatan distance min 0.28 +36 (RDS_NIMP,RDS_PTIE) intersection width 0. +37 (RDS_PIMP,RDS_NTIE) intersection width 0. +38 (RDS_POLY) Minimum width 0.18 +39 (RDS_POLY) Intersection length 0.18 +40 (RDS_POLY) Notch 0.24 +41 (RDS_POLY,RDS_POLY) Manhatan distance min 0.24 +42 (channel) Minimum width 0.28 +43 (channel) Notch 0.24 +44 (channel) Manhatan distance min 0.24 +45 (cont_diff) Manhatan distance min 0.15 +46 (RDS_CONT,RDS_CONT) Manhatan distance min 0.25 +47 (RDS_CONT) Width 0.22 +48 (RDS_CONT) Length 0.22 +49 (RDS_POLY,RDS_ACTIV) Manhatan distance min 0.07 +50 (RDS_ALU1) Minimum area 0.145 +51 (RDS_ALU1) Minimum width 0.23 +52 (RDS_ALU1) Intersection length 0.23 +53 (RDS_ALU1) Notch 0.23 +54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 0.23 +55 (RDS_VIA1,RDS_VIA1) Manhatan distance min 0.26 +56 (RDS_VIA1) Width 0.26 +57 (RDS_VIA1) Length 0.26 +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/guardring.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/guardring.py new file mode 100644 index 000000000..4c97c23b5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/guardring.py @@ -0,0 +1,72 @@ +#!/usr/bin/env python3 + +import sys +import traceback +from coriolis.Hurricane import DbU, Breakpoint, Cell, DataBase, Net, Horizontal, Vertical, Contact, Instance, Plug, Transformation, NetExternalComponents, BasicLayer, RegularLayer +from coriolis.helpers.io import ErrorMessage, WarningMessage, catch +from coriolis.helpers import loadUserSettings, setTraceLevel, trace, l, u, n +from coriolis.helpers.overlay import UpdateSession +from coriolis.helpers.technology import createBL +from coriolis import CRL + +def addGuardRing (cell): + with UpdateSession(): + #afdn = CRL.AllianceFramework.get() + technology = DataBase.getDB().getTechnology() +# The Guard ring Deep NWell layer uses TALU8 + BlDnWell = createBL( technology, 'dnWell' , BasicLayer.Material.blockage ) + dnwell = RegularLayer.create( technology, 'BLOCKAGE8', BlDnWell ) + technology.setSymbolicLayer( dnwell .getName() ) + + ptie = technology.getLayer( 'PTIE' ) + metal1 = technology.getLayer( 'METAL1' ) + metal2 = technology.getLayer( 'METAL2' ) + via = technology.getLayer( 'VIA12' ) + cntp = technology.getLayer( 'CONT_BODY_P' ) + vss = cell.getNet('vss') + aBox = cell.getAbutmentBox() + xMin = aBox.getXMin() + xMax = aBox.getXMax() + yMin = aBox.getYMin() + yMax = aBox.getYMax() + yCenter = aBox.getYCenter() + yHight = aBox.getHeight() + xWidth = aBox.getWidth() + + vssdn = Net.create(cell,'vssdn') + dnw = Net.create(cell,'dnw') + # tie will connect to vss + #tie = Net.create(cell,'tie') + + Horizontal.create(dnw, dnwell, yCenter, (yHight + l(56)), (xMin - l(34)), (xMax + l(34))) + h1=Horizontal.create(vssdn, ptie, yMax + l(72), l(20), xMin - l(80), xMax + l(80)) + h2=Horizontal.create(vssdn, ptie, yMin - l(72), l(20), xMin - l(80), xMax + l(80)) + Vertical.create(vssdn, ptie, xMax + l(72), l(20), yMin - l(72), yMax + l(72)) + Vertical.create(vssdn, ptie, xMin - l(72), l(20), yMin - l(72), yMax + l(72)) + vss1 = Horizontal.create(vssdn, metal1, yMax + l(72), l(22), xMin - l(84), xMax + l(84)) + vss2 = Horizontal.create(vssdn, metal1, yMin - l(72), l(22), xMin - l(84), xMax + l(84)) + vss3 = Vertical.create(vssdn, metal2, xMax + l(72), l(20), yMin - l(72), yMax + l(72)) + vss4 = Vertical.create(vssdn, metal2, xMin - l(72), l(20), yMin - l(72), yMax + l(72)) + Contact.create(h1, cntp, (xMin+xMax)//2, l(0), xMax + l(85), l(18)) + Contact.create(h2, cntp, (xMin+xMax)//2, l(0), xMax + l(85), l(18)) + Contact.create(h1, via, -l(72), l(0),l(20),l(20)) + Contact.create(h1, via, xMax + l(72), l(0), l(20),l(20)) + Contact.create(h2, via, -l(72), l(0), l(20),l(20)) + Contact.create(h2, via, xMax + l(72), l(0), l(20),l(20)) + + vssdn.setType(Net.Type.GROUND) + vssdn.setExternal(True) + NetExternalComponents.setExternal(vss1) + NetExternalComponents.setExternal(vss2) + NetExternalComponents.setExternal(vss3) + NetExternalComponents.setExternal(vss4) + + vss.merge(vssdn) + + aBox.inflate(l(80)) + cell.setAbutmentBox(aBox) + + return + + + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/nsxlib2.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/nsxlib2.py new file mode 100644 index 000000000..d82e55edc --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/nsxlib2.py @@ -0,0 +1,217 @@ + +import sys +import os.path +from coriolis import Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, \ + BasicLayer, Cell, Net, Horizontal, Vertical, \ + Rectilinear, Box, Point, Instance, Transformation, \ + NetExternalComponents, Pad +import coriolis.Viewer +from coriolis.CRL import AllianceFramework, Environment, Gds, LefImport, \ + CellGauge, RoutingGauge, RoutingLayerGauge +from coriolis.helpers import l, u, n, overlay, io, ndaTopDir +from coriolis.helpers.overlay import CfgCache, UpdateSession +from coriolis.Anabatic import StyleFlags + + +__all__ = [ "setup" ] + + +def _routing (): + """ + Define the routing gauge along with the various P&R tool parameters. + """ + af = AllianceFramework.get() + db = DataBase.getDB() + tech = db.getTechnology() + rg = RoutingGauge.create('nsxlib2') + rg.setSymbolic( True ) + dirM1 = RoutingLayerGauge.Vertical + dirM2 = RoutingLayerGauge.Horizontal + netBuilderStyle = 'HV,3RL+' + routingStyle = StyleFlags.HV + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL1' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.PinOnly # layer usage + , 0 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 7.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL2' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 1 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL3' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 2 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL4' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 3 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 4.0) # wire width + , l( 4.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL5' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 4 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 4.0) # wire width + , l( 4.0) # perpandicular wire width + , l( 4.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL6' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.PowerSupply # layer usage + , 5 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(15.0) # track pitch + , l(12.0) # wire width + , l(12.0) # perpandicular wire width + , l( 4.0) # VIA side + , l( 8.0 ) )) # obstacle dW + af.addRoutingGauge( rg ) + af.setRoutingGauge( 'nsxlib2' ) + + cg = CellGauge.create( 'nsxlib2' + , 'METAL1' # pin layer name. + , l( 10.0) # pitch. + , l(100.0) # cell slice height. + , l( 10.0) # cell slice step. + ) + af.addCellGauge( cg ) + af.setCellGauge( 'nsxlib2' ) + + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + # Place & Route setup + cfg.viewer.minimumSize = 500 + cfg.viewer.pixelThreshold = 2 + cfg.lefImport.minTerminalWidth = 0.0 + cfg.crlcore.groundName = 'vss' + cfg.crlcore.powerName = 'vdd' + cfg.etesian.bloat = 'disabled' + cfg.etesian.aspectRatio = 1.00 + cfg.etesian.aspectRatio = [10, 1000] + cfg.etesian.spaceMargin = 0.10 + cfg.etesian.densityVariation = 0.05 + cfg.etesian.routingDriven = False + cfg.etesian.latchUpDistance = l(2000.0) + #cfg.etesian.diodeName = 'diode' + #cfg.etesian.antennaInsertThreshold = 0.50 + #cfg.etesian.antennaMaxWL = u(250.0) + cfg.etesian.feedNames = 'tie_x0,rowend_x0' + cfg.etesian.defaultFeed = 'tie_x0' + cfg.etesian.cell.zero = 'zero_x0' + cfg.etesian.cell.one = 'one_x0' + cfg.etesian.effort = 2 + cfg.etesian.effort = ( ('Fast' , 1) + , ('Standard', 2) + , ('High' , 3) + , ('Extreme' , 4) + ) + cfg.etesian.graphics = 2 + cfg.etesian.graphics = ( ('Show every step' , 1) + , ('Show lower bound', 2) + , ('Show result only', 3) + ) + cfg.anabatic.routingGauge = 'nsxlib2' + cfg.anabatic.cellGauge = 'nsxlib2' + cfg.anabatic.globalLengthThreshold = 30*l(100.0) + cfg.anabatic.saturateRatio = 0.90 + cfg.anabatic.saturateRp = 10 + cfg.anabatic.topRoutingLayer = 'METAL5' + cfg.anabatic.edgeLength = 192 + cfg.anabatic.edgeWidth = 32 + cfg.anabatic.edgeCostH = 9.0 + cfg.anabatic.edgeCostK = -10.0 + cfg.anabatic.edgeHInc = 1.0 + cfg.anabatic.edgeHScaling = 1.0 + cfg.anabatic.globalIterations = 10 + cfg.anabatic.globalIterations = [ 1, 100 ] + cfg.anabatic.gcell.displayMode = 1 + cfg.anabatic.gcell.displayMode = (("Boundary", 1), ("Density", 2)) + cfg.anabatic.netBuilderStyle = netBuilderStyle + cfg.anabatic.routingStyle = routingStyle + cfg.katana.disableStackedVias = False + cfg.katana.hTracksReservedLocal = 4 + cfg.katana.hTracksReservedLocal = [0, 20] + cfg.katana.vTracksReservedLocal = 3 + cfg.katana.vTracksReservedLocal = [0, 20] + cfg.katana.termSatReservedLocal = 8 + cfg.katana.termSatThreshold = 9 + cfg.katana.eventsLimit = 4000002 + cfg.katana.ripupCost = 3 + cfg.katana.ripupCost = [0, None] + cfg.katana.strapRipupLimit = 16 + cfg.katana.strapRipupLimit = [1, None] + cfg.katana.localRipupLimit = 9 + cfg.katana.localRipupLimit = [1, None] + cfg.katana.globalRipupLimit = 5 + cfg.katana.globalRipupLimit = [1, None] + cfg.katana.longGlobalRipupLimit = 5 + cfg.chip.padCoreSide = 'North' + # Plugins setup + cfg.clockTree.minimumSide = l(100.0) * 6 + cfg.clockTree.buffer = 'buf_x8' + cfg.clockTree.placerEngine = 'Etesian' + cfg.block.spareSide = 10*l(100.0) + cfg.spares.buffer = 'buf_x8' + cfg.spares.maxSinks = 31 + + +def _loadNsxlib2 ( cellsTop ): + """ + Setup for NSXLIB2 Alliance library. It is an symbolic library + from which cells are loaded on demand, so we only setup pathes. + + :param cellsTop: The top directory containing the cells views. + """ + af = AllianceFramework.get() + env = af.getEnvironment() + env.setSCALE_X ( 100 ) + env.setCATALOG ( 'CATAL' ) + env.setPOWER ( 'vdd' ) + env.setGROUND ( 'vss' ) + env.setCLOCK ( '^ck$|m_clock|^clk$' ) + env.setBLOCKAGE( 'blockage[Nn]et.*' ) + env.setPad ( '.*_mpx$' ) + env.setRegister( 'sff.*' ) + env.setWORKING_LIBRARY( '.' ) + env.addSYSTEM_LIBRARY ( library=(cellsTop / 'nsxlib2').as_posix(), mode=Environment.Append ) + + +def setup ( cellsTop ): + _routing() + _loadNsxlib2( cellsTop ) diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/spimodel.cfg b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/spimodel.cfg new file mode 100644 index 000000000..8cd67f76c --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/spimodel.cfg @@ -0,0 +1,5 @@ +# MBK_SPI_MODEL +# configure the transistor models of spi parser/driver +# +nmos_3p3 N +pmos_3p3 P diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/symbolic.dreal b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/symbolic.dreal new file mode 100644 index 000000000..3c39bd85c --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/symbolic.dreal @@ -0,0 +1,127 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Dreal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 02/08/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +dEFINE DREAL_LOWER_FIGURE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_INSTANCE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_CONNECTOR_STEP 0.5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_SEGMENT_STEP 0.7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_REFERENCE_STEP 1.0 + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TAbLE DREAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/symbolic.graal b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/symbolic.graal new file mode 100644 index 000000000..cae4dcf0b --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/symbolic.graal @@ -0,0 +1,386 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Graal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 27/06/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Graal Peek Bound in lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_PEEK_BOUND 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_FIGURE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_INSTANCE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_CONNECTOR_STEP 5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_SEGMENT_STEP 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_REFERENCE_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | Segment Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_NAME + + NWELL Nwell tan Black + PWELL Pwell light_yellow Black + NDIF Ndif lawn_green Black + PDIF Pdif yellow Black + NTIE Ntie spring_green Black + PTIE Ptie light_goldenrod Black + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 GReen Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + TPOLY Tpoly hot_pink Black + TALU1 Talu1 royal_blue Black + TALU2 Talu2 turquoise Black + TALU3 Talu3 light_pink Black + TALU4 Talu4 green Black + TALU5 Talu5 yellow Black + TALU6 Talu6 violet Black + TALU7 Talu7 red Black + TALU8 Talu8 blue Black + CALU1 CAlu1 royal_blue Black + CALU2 CAlu2 Cyan Black + CALU3 CAlu3 light_pink Black + CALU4 CAlu4 green Black + CALU5 CAlu5 yellow Black + CALU6 CAlu6 violet Black + CALU7 CAlu7 red Black + CALU8 CAlu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Transistor Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_TRANSISTOR_NAME + + NTRANS Ntrans lawn_green Black + PTRANS Ptrans yellow Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Connector Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_CONNECTOR_NAME + + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 green Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Length and Width for a symbolic Segment | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_VALUE + + NWELL 4 4 + PWELL 4 4 + NDIF 3 2 # LSX 2 -> 3 + PDIF 3 2 # LSX 2 -> 3 + NTIE 3 1 # LSX 2 -> 3 + PTIE 3 1 # LSX 2 -> 3 + NTRANS 1 5 # LSX 4 -> 5 + PTRANS 1 5 # LSX 4 -> 5 + POLY 1 1 + POLY2 1 1 + ALU1 2 1 # LSX 1 -> 2 + ALU2 2 1 + ALU3 2 1 + ALU4 2 1 + ALU5 2 1 + ALU6 2 1 + ALU7 2 1 + ALU8 2 1 + TPOLY 1 1 + TALU1 2 1 # LSX 1 -> 2 + TALU2 2 1 # LSX 2 -> 1 + TALU3 2 1 # LSX 2 -> 1 + TALU4 2 1 # LSX 2 -> 1 + TALU5 2 1 # LSX 2 -> 1 + TALU6 2 1 # LSX 2 -> 1 + TALU7 2 1 # LSX 2 -> 1 + TALU8 2 1 # LSX 2 -> 1 + CALU1 2 0 + CALU2 2 0 + CALU3 2 0 + CALU4 2 0 + CALU5 2 0 + CALU6 2 0 + CALU7 2 0 + CALU8 2 0 + +END + +# /*------------------------------------------------------------\ +# | | +# | Reference Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_REFERENCE_NAME + + REF_REF Ref_Ref red Black + REF_CON Ref_Con Cyan Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_VIA_NAME + + CONT_DIF_N Cont_NDif lawn_green Black + CONT_DIF_P Cont_PDif yellow Black + CONT_BODY_N Cont_NTie spring_green Black + CONT_BODY_P Cont_PTie light_goldenrod Black + CONT_POLY Cont_Poly red Black + CONT_POLY2 Cont_Poly2 orange Black + CONT_VIA Via_1-2 cyan Black + CONT_VIA2 Via_2-3 light_pink Black + CONT_VIA3 Via_3-4 green Black + CONT_VIA4 Via_4-5 yellow Black + CONT_VIA5 Via_5-6 violet Black + CONT_VIA6 Via_6-7 red Black + CONT_VIA7 Via_7-8 blue Black + C_X_N Cont_CxN orange Black + C_X_P Cont_CxP orange Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Big Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_NAME + + CONT_VIA Big_Via_1-2 cyan Black + CONT_VIA2 Big_Via_2-3 light_pink Black + CONT_VIA3 Big_Via_3-4 green Black + CONT_VIA4 Big_Via_4-5 yellow Black + CONT_VIA5 Big_Via_5-6 violet Black + CONT_VIA6 Big_Via_6-7 red Black + CONT_VIA7 Big_Via_7-8 blue Black + + CONT_TURN1 Turn_Via_1 royal_blue Black + CONT_TURN2 Turn_Via_2 Cyan Black + CONT_TURN3 Turn_Via_3 light_pink Black + CONT_TURN4 Turn_Via_4 green Black + CONT_TURN5 Turn_Via_5 yellow Black + CONT_TURN6 Turn_Via_6 violet Black + CONT_TURN7 Turn_Via_7 red Black + CONT_TURN8 Turn_Via_7 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Size for a symbolic Big Via | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_VALUE + + CONT_VIA 2 + CONT_VIA2 2 + CONT_VIA3 2 + CONT_VIA4 2 + CONT_VIA5 2 + CONT_VIA6 2 + CONT_VIA7 2 + + CONT_TURN1 2 + CONT_TURN2 2 + CONT_TURN3 2 + CONT_TURN4 2 + CONT_TURN5 2 + CONT_TURN6 2 + CONT_TURN7 2 + CONT_TURN8 2 + +END + +# /*------------------------------------------------------------\ +# | | +# | Orient Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_ORIENT_NAME + + NORTH North lawn_green Black + SOUTH South yellow Black + EAST East tan Black + WEST West red Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Symmetry Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SYMMETRY_NAME + + NOSYM No_Sym LightBlue Black + SYM_X Sym_X turquoise Black + SYM_Y Sym_Y cyan Black + SYMXY Sym_XY lightCyan Black + ROT_P Rot_P MediumAquamarine Black + ROT_M Rot_M aquamarine Black + SY_RP Sym_RP green Black + SY_RM Sym_RM MediumSpringGreen Black + +END + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/techno.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/techno.py new file mode 100644 index 000000000..a6b47cbe5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/techno.py @@ -0,0 +1,648 @@ + +from coriolis import CRL, Hurricane, Viewer, Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, BasicLayer, \ + RegularLayer, Cell, Net, Horizontal, Vertical, Rectilinear, \ + Box, Point, NetExternalComponents +from coriolis.technos.common.colors import toRGB +from coriolis.technos.common.patterns import toHexa +from coriolis.helpers import u +from coriolis.helpers.technology import createBL, createVia +from coriolis.helpers.overlay import CfgCache +from coriolis.helpers.analogtechno import Length, Area, Unit, Asymmetric, loadAnalogTechno, addDevice +from coriolis.designflow.task import ShellEnv + + +__all__ = [ "setup" ] + + +""" +Coriolis Design Technological Rules (DTR) for IHP 130nm BiCMOS General Purpose +================================================================================= + +:Version: rev.LIP6-1 +:Date: May 22, 2024 +:Authors: Naohiko Shimizu + +Reference documents: + SG13G2 Process Specification Rev.1.2 + SG13G2 Open Source Layout Rules Rev.0.2 (2024-03-08) + +===================== ======= ============ ==================================== + +""" + + +analogTechnologyTable = \ + ( ('Header', 'Sg13g2', DbU.UnitPowerMicro, 'rev.LIP6-1') + # ------------------------------------------------------------------------------------ + # ( Rule name , [Layer1] , [Layer2] , Value , Rule flags , Reference ) + , ('physicalGrid' , 0.001 , Length , 'Grid Rules') + , ('transistorMinL' , 0.13 , Length , 'Gat.a') + #, ('transistorMinL' , 0.38 , Length , 'lvtn.1a') + #, ('transistorMaxL' , 38 , Length , 'rule0002') + #, ('transistorMinW' , 0.42 , Length , 'activ.2') + #, ('transistorMinW' , 0.36 , Length , 'activ.2b') + #, ('transistorMaxW' , 4000 , Length , 'rule0004') + + # N-WELL (nwm) + , ('minWidth' , 'nwm' , 0.62 , Length , 'NW.a') + , ('minSpacing' , 'nwm' , 0.62 , Length , 'NW.b') + , ('minArea' , 'nwm' , 0 , Area , 'N/A') + + # LVTN (lvtn) + #, ('minWidth' , 'lvtn' , 0.38 , Length , 'lvtn.1a') + #, ('minSpacing' , 'lvtn' , 0.38 , Length , 'lvtn.2') + #, ('minArea' , 'lvtn' , 0.265 , Area , 'lvtn.13') + #, ('minEnclosure' , 'nwm' , 'lvtn' , 0.38 , Length|Asymmetric, 'lvtn.10') + + # ACTIV (activ) + , ('minWidth' , 'activ' , 0.15 , Length , 'Act.a') + , ('minSpacing' , 'activ' , 0.21 , Length , 'Act.b') + , ('minArea' , 'activ' , 0.122 , Area , 'Act.d') + , ('minEnclosure' , 'nwm' , 'activ' , 0.31 , Length|Asymmetric, 'NW.c') + + # Poly1 (poly) + , ('minWidth' , 'poly' , 0.13 , Length , 'Gat.a') + , ('minSpacing' , 'poly' , 0.18 , Length , 'Gat.b') + , ('minGateSpacing' , 'poly' , 0.18 , Length , 'Gat.b') + , ('minArea' , 'poly' , 0.09 , Area , 'Gat.e') + , ('minSpacing' , 'poly' , 'activ' , 0.07 , Length , 'Gat.d') + , ('minExtension' , 'poly' , 'activ' , 0.180 , Length|Asymmetric, 'Gat.c') + , ('minGateExtension' , 'activ' , 'poly' , 0.23 , Length|Asymmetric, 'Act.c') + , ('minExtension' , 'activ' , 'poly' , 0.23 , Length|Asymmetric, 'Act.c') + + # 4.1.6 PPLUS (psdm) + , ('minWidth' , 'psdm' , 0.31 , Length , 'pSD.a') + , ('minSpacing' , 'psdm' , 0.31 , Length , 'pSD.b') + , ('minArea' , 'psdm' , 0.25 , Area , 'pSD.k') + , ('minSpacing' , 'psdm' , 'activ' , 0.180 , Length , 'pSD.d') + , ('minGateExtension' , 'psdm' , 'poly' , 0.00 , Length|Asymmetric, 'N/A') + , ('minOverlap' , 'psdm' , 'activ' , 0.30 , Length , 'pSD.e') + , ('minEnclosure' , 'psdm' , 'activ' , 0.180 , Length|Asymmetric, 'pSD.c') + , ('minStrapEnclosure' , 'psdm' , 'activ' , 0.180 , Length , 'pSD.c') + , ('minSpacing' , 'nsdm' , 'psdm' , 0.00 , Length , 'N/A') + , ('minEnclosure' , 'psdm' , 'poly' , 0.30 , Length|Asymmetric, 'pSD.i') + , ('minLengthEnclosure', 'psdm' , 'activ' , 0 , Length|Asymmetric, 'N/A') + , ('minWidthEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'psdm' , 'activ' , 0.180 , Length|Asymmetric, 'dup. pSD.c') + , ('minStrapEnclosure' , 'psdm' , 0.180 , Length , 'dup. pSD.c') + + # NPLUS (nsdm) no nSD rules + #, ('minWidth' , 'nsdm' , 0.38 , Length , 'nsd.1') + #, ('minSpacing' , 'nsdm' , 0.38 , Length , 'nsd.2') + #, ('minArea' , 'nsdm' , 0.265 , Area , 'nsd.10a') + #, ('minSpacing' , 'nsdm' , 'activ' , 0.130 , Length , 'nsd.7') + #, ('minGateExtension' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minOverlap' , 'nsdm' , 'activ' , 0 , Length , 'N/A') + #, ('minEnclosure' , 'nsdm' , 'activ' , 0.125 , Length|Asymmetric, 'nsd.5a') + #, ('minStrapEnclosure' , 'nsdm' , 'activ' , 0.125 , Length , 'nsd.5b') + #, ('minEnclosure' , 'nsdm' , 'nwm' , 0 , Length|Asymmetric, 'N/A') + #, ('minEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minLengthEnclosure', 'nsdm' , 'activ' , 0 , Length|Asymmetric, 'N/A') + #, ('minWidthEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minGateEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + #, ('minExtension' , 'nsdm' , 'activ' , 0.125 , Length|Asymmetric, 'dup. nsd.5a') + #, ('minStrapEnclosure' , 'nsdm' , 0.215 , Length , 'dup. nsd.5b') + + # LICM1 (CONT) + , ('minWidth' , 'cont' , 0.16 , Length , 'Cnt.a') + , ('minSpacing' , 'cont' , 0.18 , Length , 'Cnt.b') + , ('minGateSpacing' , 'cont' , 'poly' , 0.11 , Length|Asymmetric, 'Cnt.f') + , ('minSpacing' , 'cont' , 'poly' , 0.11 , Length|Asymmetric, 'Cnt.f') + , ('minSpacing' , 'cont' , 'activ' , 0.14 , Length , 'Cnt.e') + #, ('minSpacing' , 'cont' , 'activ' , 0.06 , Length , 'cont.5b') + , ('minEnclosure' , 'activ' , 'cont' , 0.07 , Length|Asymmetric, 'Cnt.c') + , ('minEnclosure' , 'poly' , 'cont' , 0.07 , Length|Asymmetric, 'Cnt.d') + #, ('minEnclosure' , 'psdm' , 'cont' , 0 , Length|Asymmetric, 'N/A') + #, ('minEnclosure' , 'nsdm' , 'cont' , 0 , Length|Asymmetric, 'N/A') + #, ('minGateEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'poly' , 'cont' , 0.07 , Length|Asymmetric, 'dup. Cnt.d') + , ('minExtension' , 'psdm' , 'cont' , 0.09 , Length|Asymmetric, 'Cnt.g2') + #, ('minExtension' , 'nsdm' , 'cont' , 0.25 , Length|Asymmetric, 'dup.') + + # LI1M (M1) + , ('minWidth' , 'M1' , 0.16 , Length , 'M1.a') + , ('minSpacing' , 'M1' , 0.18 , Length , 'M1.b') + , ('minArea' , 'M1' , 0.09 , Area , 'M1.d') + , ('minEnclosure' , 'M1' , 'cont' , 0.05 , Length|Asymmetric, 'M1.c1') + , ('minEnclosure' , 'M1' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # CTM1 (via12) + , ('minWidth' , 'via12' , 0.19 , Length , 'V1.a') + , ('minSpacing' , 'via12' , 0.22 , Length , 'V1.b') + + + # MM1 (M2) + , ('minWidth' , 'M2' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M2' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M2' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M2' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M2' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via23) + , ('minWidth' , 'via23' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via23' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M2' , 'via23' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M2' , 'via23' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + + # MM1 (M3) + , ('minWidth' , 'M3' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M3' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M3' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M3' , 'via23' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M3' , 'via23' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via34) + , ('minWidth' , 'via34' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via34' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M3' , 'via34' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M3' , 'via34' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + # MM1 (M4) + , ('minWidth' , 'M4' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M4' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M4' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M4' , 'via34' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M4' , 'via34' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via45) + , ('minWidth' , 'via45' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via45' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M4' , 'via45' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M4' , 'via45' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + # MM5 (M5) + , ('minWidth' , 'M5' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M5' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M5' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M5' , 'via45' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M5' , 'via45' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via56 TopVia1) + , ('minWidth' , 'via56' , 0.42 , Length , 'TV1.a') + , ('minSpacing' , 'via56' , 0.42 , Length , 'TV1.b') + , ('minEnclosure' , 'M5' , 'via56' , 0.1 , Length|Asymmetric, 'TV1.c') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M5' , 'via56' , 0.1 , Length|Asymmetric, 'dup. TV1.c') + + # MM6 (M6) TopMetal1 + , ('minWidth' , 'M6' , 1.64 , Length , 'TM1.a') + , ('minSpacing' , 'M6' , 1.64 , Length , 'TM1.b') + #, ('minArea' , 'M6' , 0.24 , Area , 'M5.4a') + , ('minEnclosure' , 'M6' , 'via56' , 0.10 , Length|Asymmetric, 'TV1.c') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M6' , 'via56' , 0.10 , Length|Asymmetric, 'dup. TV1.c ') + + # VIM (via56 TopVia2) + , ('minWidth' , 'via56' , 0.90 , Length , 'TV2.a') + , ('minSpacing' , 'via56' , 1.06 , Length , 'TV2.b') + , ('minEnclosure' , 'M6' , 'via56' , 0.5 , Length|Asymmetric, 'TV2.c') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M6' , 'via56' , 0.5 , Length|Asymmetric, 'dup. TV2.c') + + # MM5 (M7) TopMetal2 + , ('minWidth' , 'M7' , 2.00 , Length , 'TM2.a') + , ('minSpacing' , 'M7' , 2.00 , Length , 'TM2.b') + #, ('minArea' , 'M7' , 0.24 , Area , 'M5.4a') + , ('minEnclosure' , 'M7' , 'via56' , 0.50 , Length|Asymmetric, 'TV1.d') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M7' , 'via56' , 0.50 , Length|Asymmetric, 'dup. TV1.d ') + + + + #capm + #, ('minWidth' , 'metcap' , 1.0 , Length , 'capm.1') + #, ('minWidth' , 'metcapdum' , 0.5 , Length , '') + #, ('maxWidth' , 'metcap' , 300.0 , Length , '') + #, ('maxWidth' , 'metbot' , 350.0 , Length , '') + #, ('minSpacing' , 'metcap' , 0.84 , Length , 'capm.2a') + #, ('minSpacing' , 'metbot' , 0.8 , Length , 'metcap.2b') + #, ('minSpacing' , 'cut1' , 'metcap' , 0.50 , Length , '') + #, ('minSpacing' , 'cut2' , 'metcap' , 0.50 , Length , 'capm.5') + #, ('minSpacingOnMetbot', 'cut2' , 0.2 , Length , 'via34.2') + #, ('minSpacingOnMetbot', 'via34' , 0.2 , Length , 'via34.2') + #, ('minSpacingOnMetcap', 'cut2' , 0.2 , Length , 'via34.2') + #, ('minEnclosure' , 'M3' , 'metcap' , 0.14 , Length|Asymmetric, 'capm.3') + #, ('minEnclosure' , 'metbot' , 'cut1' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'metbot' , 'cut2' , 0.04 , Length|Asymmetric, 'via34.14') + #, ('minEnclosure' , 'metcap' , 'cut2' , 0.14 , Length|Asymmetric, 'capm.4') + #, ('minArea' , 'metcap' , 0 , Area , 'na') + #, ('minAreaInMetcap' , 'cut2' , 0 , Area , 'na') + #, ('MIMCap' , 1.25 , Unit , 'na') + #, ('MIMPerimeterCap' , 0.17 , Unit , 'na') + + + #capm + , ('minWidth' , 'capm' , 1.14 , Length , 'MIM.a') + #, ('minWidth' , 'capmdum' , 0.5 , Length , '') + #, ('maxWidth' , 'capm' , 30.0 , Length , '') + #, ('maxWidth' , 'metbot' , 35.0 , Length , '') + , ('minSpacing' , 'capm' , 0.60 , Length , 'MIM.b') + #, ('minSpacing' , 'M4' , 0.8 , Length , 'capm.2b') + , ('minSpacingWide1' , 'M3' , 0.8 , Length , 'capm.2b') + , ('minSpacing' , 'M6' , 'capm' , 0.60 , Length , 'MIM.e') + , ('minSpacing' , 'via34' , 'capm' , 0.50 , Length , 'capm.5') + , ('minSpacingOnMetBot', 'via34' , 0.2 , Length , 'via34.2') + , ('minSpacingOnMetCap', 'via34' , 0.2 , Length , 'via34.2') + , ('minSpacingOnMetBot', 'via23' , 0.2 , Length , 'via34.2 fake') + , ('minSpacingOnMetCap', 'via23' , 0.2 , Length , 'via34.2 fake') + , ('minEnclosure' , 'M5' , 'capm' , 0.60 , Length|Asymmetric, 'MIM.c') + #, ('minEnclosure' , 'M4' , 'via23' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'M4' , 'via34' , 0.04 , Length|Asymmetric, 'via34.14') + #, ('minEnclosure' , 'capm' , 'via23' , 0.14 , Length|Asymmetric, 'capm.4 fake') + , ('minEnclosure' , 'capm' , 'via56' , 0.36 , Length|Asymmetric, 'MIM.d') + , ('minArea' , 'capm' , 1.30 , Area , 'MIM.f') + , ('minAreaInMetcap' , 'via34' , 0 , Area , 'na') + , ('MIMCap' , 1.25 , Unit , 'na') + , ('MIMPerimeterCap' , 0.17 , Unit , 'na') + , ('PIPCap' , 1.25 , Unit , 'na') + , ('PIPPerimeterCap' , 0.17 , Unit , 'na') + + ) + + +def _loadDtr (): + """ + Load design kit physical rules for IHP 130nm. + """ + loadAnalogTechno( analogTechnologyTable, __file__ ) + + +def _loadDevices (): + addDevice( name = 'DifferentialPairBulkConnected' + #, spice = spiceDir+'DiffPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'DifferentialPairBulkUnconnected' + #, spice = spiceDir+'DiffPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'LevelShifterBulkUnconnected' + #, spice = spiceDir+'LevelShifterBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S1', 'S2', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.LS_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.LS_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.LS_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.LS_interdigitated.py' ) + ) + ) + addDevice( name = 'TransistorBulkConnected' + #, spice = spiceDir+'TransistorBulkConnected.spi' + , connectors = ( 'D', 'G', 'S' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'TransistorBulkUnconnected' + #, spice = spiceDir+'TransistorBulkUnconnected.spi' + , connectors = ( 'D', 'G', 'S', 'B' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkConnected' + #, spice = spiceDir+'CCPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkUnconnected' + #, spice = spiceDir+'CCPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkConnected' + #, spice = spiceDir+'CommonSourcePairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkUnconnected' + #, spice = spiceDir+'CommonSourcePairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkConnected' + #, spice = spiceDir+'CurrMirBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkUnconnected' + #, spice = spiceDir+'CurrMirBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'MultiCapacitor' + #, spice = spiceDir+'MIM_OneCapacitor.spi' + , connectors = ( 'T1', 'B1' ) + , layouts = ( ('Matrix', 'coriolis.oroshi.multicapacitor.py' ), + ) + ) + #addDevice( name = 'Resistor' + # #, spice = spiceDir+'MIM_OneCapacitor.spi' + # , connectors = ( 'PIN1', 'PIN2' ) + # , layouts = ( ('Snake', 'coriolis.oroshi.resistorsnake.py' ), + # ) + # ) + + +def _setup_techno ( coriolisTechDir ): + ShellEnv.RDS_TECHNO_NAME = (coriolisTechDir / 'gf180mcu_nsx2' / 'gf180mcu.rds').as_posix() + ShellEnv.GRAAL_TECHNO_NAME = (coriolisTechDir / 'gf180mcu_nsx2' / 'symbolic.graal' ).as_posix() + ShellEnv.DREAL_TECHNO_NAME = (coriolisTechDir / 'gf180mcu_nsx2' / 'symbolic.dreal' ).as_posix() + + db = DataBase.getDB() + CRL.System.get() + + tech = Technology.create(db, 'gf180mcu_nsx2') + + DbU.setPrecision( 2 ) + DbU.setPhysicalsPerGrid( 0.001, DbU.UnitPowerMicro ) + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + cfg.gdsDriver.metricDbu = 1e-09 + cfg.gdsDriver.dbuPerUu = 0.001 + DbU.setGridsPerLambda ( 30 ) + DbU.setSymbolicSnapGridStep( DbU.fromGrid( 1.0 )) + DbU.setPolygonStep ( DbU.fromGrid( 1.0 )) + DbU.setStringMode ( DbU.StringModePhysical, DbU.UnitPowerMicro ) + + createBL( tech, 'poly2' , BasicLayer.Material.other , size=u(1.7), spacing=u(2.5), gds2Layer= 31, gds2DataType= 0 ) + createBL( tech, 'nwm' , BasicLayer.Material.nWell , size=u(0.62), spacing=u(0.62), gds2Layer= 31, gds2DataType= 0 ) + createBL( tech, 'nsdm' , BasicLayer.Material.nImplant, size=u(0.31), spacing=u(0.31), area=0.25, gds2Layer= 7, gds2DataType= 0 ) + createBL( tech, 'psdm' , BasicLayer.Material.pImplant, size=u(0.31), spacing=u(0.31), area=0.25, gds2Layer= 14, gds2DataType= 0 ) + #createBL( tech, 'hvi' , BasicLayer.Material.other , gds2Layer= 75, gds2DataType= 20 ) + createBL( tech, 'activ.pin' , BasicLayer.Material.other , gds2Layer= 1, gds2DataType= 2 ) + #createBL( tech, 'activ.block', BasicLayer.Material.blockage, gds2Layer=1, gds2DataType= 23 ) + createBL( tech, 'poly.pin' , BasicLayer.Material.other , gds2Layer= 5, gds2DataType= 2 ) + #createBL( tech, 'poly.block' , BasicLayer.Material.blockage, gds2Layer=5, gds2DataType= 23 ) + createBL( tech, 'M1.pin' , BasicLayer.Material.other , gds2Layer= 8, gds2DataType= 2 ) + #createBL( tech, 'M1.block' , BasicLayer.Material.blockage, gds2Layer=8, gds2DataType= 23 ) + createBL( tech, 'M2.pin' , BasicLayer.Material.other , gds2Layer= 10, gds2DataType= 2 ) + #createBL( tech, 'M2.block' , BasicLayer.Material.blockage, gds2Layer=10, gds2DataType= 23 ) + createBL( tech, 'M3.pin' , BasicLayer.Material.other , gds2Layer= 30, gds2DataType= 2 ) + #createBL( tech, 'M3.block' , BasicLayer.Material.blockage, gds2Layer=30, gds2DataType= 23 ) + createBL( tech, 'M4.pin' , BasicLayer.Material.other , gds2Layer= 50, gds2DataType= 2 ) + #createBL( tech, 'M4.block' , BasicLayer.Material.blockage, gds2Layer=50, gds2DataType=23 ) + createBL( tech, 'M5.pin' , BasicLayer.Material.other , gds2Layer= 67, gds2DataType= 2 ) + #createBL( tech, 'M5.block' , BasicLayer.Material.blockage, gds2Layer=67, gds2DataType=23 ) + createBL( tech, 'M6.pin' , BasicLayer.Material.other , gds2Layer= 126, gds2DataType= 2 ) + #createBL( tech, 'M6.block' , BasicLayer.Material.blockage, gds2Layer=126, gds2DataType=23 ) + #createBL( tech, 'cont.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 30 ) + #createBL( tech, 'via12.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 50 ) + #createBL( tech, 'via23.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 70 ) + #createBL( tech, 'via34.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 90 ) + #createBL( tech, 'via45.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=110 ) + #createBL( tech, 'via56.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=130 ) + createBL( tech, 'activ' , BasicLayer.Material.active , size=u(0.15), spacing=u(0.21), gds2Layer= 1, gds2DataType= 0 ) + createBL( tech, 'poly' , BasicLayer.Material.poly , size=u(0.13), spacing=u(0.18), gds2Layer= 5, gds2DataType= 0 ) + createBL( tech, 'cont' , BasicLayer.Material.cut , size=u(0.16), spacing=u(0.18), gds2Layer= 6, gds2DataType= 0 ) + createBL( tech, 'M1' , BasicLayer.Material.metal , size=u(0.16), spacing=u(0.18), area=0.009, gds2Layer= 8, gds2DataType= 0 ) + createBL( tech, 'via12' , BasicLayer.Material.cut , size=u(0.19), spacing=u(0.22), gds2Layer= 19, gds2DataType= 0 ) + createBL( tech, 'M2' , BasicLayer.Material.metal , size=u(0.20), spacing=u(0.21), area=0.144, gds2Layer= 10, gds2DataType= 0 ) + createBL( tech, 'via23' , BasicLayer.Material.cut , size=u(0.19), spacing=u(0.22), gds2Layer= 29, gds2DataType= 0 ) + createBL( tech, 'M3' , BasicLayer.Material.metal , size=u(0.19), spacing=u(0.21), area=0.144, gds2Layer= 30, gds2DataType= 0 ) + createBL( tech, 'capm' , BasicLayer.Material.metal ) + createBL( tech, 'via34' , BasicLayer.Material.cut , size=u(0.19 ), spacing=u(0.22), gds2Layer= 49, gds2DataType= 0 ) + createBL( tech, 'M4' , BasicLayer.Material.metal , size=u(0.19 ), spacing=u(0.21 ), area=0.144, gds2Layer= 50, gds2DataType= 0 ) + createBL( tech, 'via45' , BasicLayer.Material.cut , size=u(0.19 ), spacing=u(0.22), gds2Layer= 49, gds2DataType= 0 ) + createBL( tech, 'M5' , BasicLayer.Material.metal , size=u(0.19 ), spacing=u(0.21 ), area=0.144, gds2Layer=67, gds2DataType= 0 ) + createBL( tech, 'via56' , BasicLayer.Material.cut , size=u(0.42 ), spacing=u(0.42 ), gds2Layer= 125, gds2DataType= 0 ) + createBL( tech, 'M6' , BasicLayer.Material.metal , size=u(1.64), spacing=u(1.64), gds2Layer= 126, gds2DataType= 0 ) + createBL( tech, 'hvtp' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 78, gds2DataType= 44 ) + createBL( tech, 'lvtn' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer=125, gds2DataType= 44 ) + createBL( tech, 'areaid_sc' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 4 ) + createBL( tech, 'pad' , BasicLayer.Material.cut , size=u(40.0), spacing=u(1.27), gds2Layer= 76, gds2DataType= 20 ) + createBL( tech, 'areaid_diode' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 23 ) + createBL( tech, 'pnp' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 44 ) + createBL( tech, 'diffres' , BasicLayer.Material.other , gds2Layer= 65, gds2DataType= 13 ) + createBL( tech, 'npn' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 20 ) + createBL( tech, 'polyres' , BasicLayer.Material.other , gds2Layer= 66, gds2DataType= 13 ) + createBL( tech, 'prBoundary' , BasicLayer.Material.other , gds2Layer=235, gds2DataType= 4 ) + + tech.addLayerAlias( 'M2', 'met1' ) + tech.addLayerAlias( 'M3', 'met2' ) + tech.addLayerAlias( 'M4', 'met3' ) + tech.addLayerAlias( 'M5', 'met4' ) + tech.addLayerAlias( 'M6', 'met5' ) + + # ViaLayers + createVia( tech, 'li_via12_M2' , 'M1' , 'via12', 'M2', u(0.17) ) + createVia( tech, 'M2_via_M3' , 'M2' , 'via23' , 'M3', u(0.15) ) + createVia( tech, 'M3_via34_M4' , 'M3' , 'via34', 'M4', u(0.2 ) ) + createVia( tech, 'M4_via45_M5' , 'M4' , 'via45', 'M5', u(0.2 ) ) + createVia( tech, 'M5_via56_M6' , 'M5' , 'via56', 'M6', u(0.8 ) ) + createVia( tech, 'capm_via56', 'capm', 'via56', 'M6', u(0.2 ) ) + + # Blockages + #ech.getLayer('activ' ).setBlockageLayer( tech.getLayer('activ.block') ) + #ech.getLayer('poly') .setBlockageLayer( tech.getLayer('poly.block') ) + #ech.getLayer('M1') .setBlockageLayer( tech.getLayer('M1.block') ) + #ech.getLayer('M2') .setBlockageLayer( tech.getLayer('M2.block') ) + #ech.getLayer('M3') .setBlockageLayer( tech.getLayer('M3.block') ) + #ech.getLayer('M4') .setBlockageLayer( tech.getLayer('M4.block') ) + #ech.getLayer('M5') .setBlockageLayer( tech.getLayer('M5.block') ) + #ech.getLayer('M6') .setBlockageLayer( tech.getLayer('M6.block') ) + #ech.getLayer('cont' ) .setBlockageLayer( tech.getLayer('cont.block') ) + #ech.getLayer('via12') .setBlockageLayer( tech.getLayer('via12.block') ) + #ech.getLayer('via23') .setBlockageLayer( tech.getLayer('via23.block') ) + #ech.getLayer('via34') .setBlockageLayer( tech.getLayer('via34.block') ) + #ech.getLayer('via45') .setBlockageLayer( tech.getLayer('via45.block') ) + #ech.getLayer('via56') .setBlockageLayer( tech.getLayer('via56.block') ) + + # Coriolis internal layers + createBL( tech, 'text.cell' , BasicLayer.Material.other, ) + createBL( tech, 'text.instance', BasicLayer.Material.other, ) + createBL( tech, 'SPL1' , BasicLayer.Material.other, ) + createBL( tech, 'AutoLayer' , BasicLayer.Material.other, ) + createBL( tech, 'gmetalh' , BasicLayer.Material.metal, ) + createBL( tech, 'gcontact' , BasicLayer.Material.cut, ) + createBL( tech, 'gmetalv' , BasicLayer.Material.metal, ) + + # Resistors + # ResistorLayer.create(tech, 'poly_res', 'poly', 'polyres') + # ResistorLayer.create(tech, 'active_res', 'activ' , 'diffres') + + # Transistors + # GateLayer.create(tech, 'hvmosgate' , 'activ' , 'poly', 'hvi') + # GateLayer.create(tech, 'mosgate' , 'activ' , 'poly') + # GateLayer.create(tech, 'mosgate_sc', 'activ' , 'poly') + # TransistorLayer.create(tech, 'nfet_01v8' , 'mosgate' , 'nsdm') + # TransistorLayer.create(tech, 'nfet_01v8_lvt' , 'mosgate' , ('nsdm', 'lvtn')) + # TransistorLayer.create(tech, 'nfet_01v8_sc' , 'mosgate_sc', 'nsdm') + # TransistorLayer.create(tech, 'nfet_g5v0d10v5', 'hvmosgate' , 'nsdm') + # TransistorLayer.create(tech, 'pfet_01v8' , 'mosgate' , 'psdm', 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_hvt' , 'mosgate' , ('psdm', 'hvtp'), 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_lvt' , 'mosgate' , ('psdm', 'lvtn'), 'nwm') + # TransistorLayer.create(tech, 'pfet_g5v0d10v5', 'hvmosgate' , 'psdm', 'nwm') + + # Bipolars + # Not implemented: Bipolar 'pnp_05v5_w0u68l0u68' + # Not implemented: Bipolar 'npn_05v5_w1u00l2u00' + # Not implemented: Bipolar 'pnp_05v5_w3u40l3u40' + # Not implemented: Bipolar 'npn_05v5_w1u00l1u00' + + +def _setup_display (): + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [black] + + threshold = 0.2 if Viewer.Graphics.isHighDpi() else 0.1 + + style = Viewer.DisplayStyle( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - black background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + # Viewer. + style.addDrawingStyle( group='Viewer', name='fallback' , color=toRGB('Gray238' ), border=1, pattern='55AA55AA55AA55AA' ) + style.addDrawingStyle( group='Viewer', name='background' , color=toRGB('Gray50' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='rubber' , color=toRGB('192,0,192' ), border=4, threshold=0.02 ) + style.addDrawingStyle( group='Viewer', name='phantom' , color=toRGB('Seashell4' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries' , color=toRGB('wheat1' ), border=2, pattern='0000000000000000', threshold=0 ) + style.addDrawingStyle( group='Viewer', name='marker' , color=toRGB('80,250,80' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionDraw' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionFill' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='grid' , color=toRGB('White' ), border=1, threshold=2.0 ) + style.addDrawingStyle( group='Viewer', name='spot' , color=toRGB('White' ), border=2, threshold=6.0 ) + style.addDrawingStyle( group='Viewer', name='ghost' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='text.ruler' , color=toRGB('White' ), border=1, threshold= 0.0 ) + style.addDrawingStyle( group='Viewer', name='text.instance' , color=toRGB('White' ), border=1, threshold=400.0 ) + style.addDrawingStyle( group='Viewer', name='text.reference', color=toRGB('White' ), border=1, threshold=200.0 ) + style.addDrawingStyle( group='Viewer', name='undef' , color=toRGB('Violet' ), border=0, pattern='2244118822441188' ) + + # Active Layers. + style.addDrawingStyle(group='Active Layers', name='nwm' , color=toRGB('Tan' ), pattern=toHexa('urgo.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='nsdm' , color=toRGB('LawnGreen'), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='psdm' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='hvtp' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='lvtn' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='activ' , color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='activ.pin', color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly.pin' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + + # Routing Layers. + style.addDrawingStyle(group='Routing Layers', name='M1' , color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M1.pin', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M2' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M2.pin', color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M3' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M3.pin', color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M4' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M4.pin', color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M5' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M5.pin', color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M6' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M6.pin', color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + + # Cuts (VIA holes). + style.addDrawingStyle(group='Cuts (VIA holes', name='cont' , color=toRGB('0,150,150'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via12' , color=toRGB('Aqua' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via23' , color=toRGB('LightPink'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via34' , color=toRGB('Green' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via45' , color=toRGB('Yellow' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via56' , color=toRGB('Violet' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='pad' , color=toRGB('Red' ), threshold=threshold) + + # Blockages. + #style.addDrawingStyle(group='Blockages', name='activ.block', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='poly.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M1.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M2.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M3.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M4.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M5.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M6.block' , color=toRGB('Blue' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='cont.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via12.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via23.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via34.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via45.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via56.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) +# + # Knick & Kite. + style.addDrawingStyle( group='Knik & Kite', name='SPL1' , color=toRGB('Red' ) ) + style.addDrawingStyle( group='Knik & Kite', name='AutoLayer' , color=toRGB('Magenta' ) ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalh' , color=toRGB('128,255,200'), pattern=toHexa('antislash2.32' ), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalv' , color=toRGB('200,200,255'), pattern=toHexa('light_antihash1.8'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gcontact' , color=toRGB('255,255,190'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::Edge' , color=toRGB('255,255,190'), pattern='0000000000000000' , border=4, threshold=0.02 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::GCell', color=toRGB('255,255,190'), pattern='0000000000000000' , border=2, threshold=threshold ) + + Viewer.Graphics.addStyle( style ) + + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [white]. + + style = Viewer.DisplayStyle( 'Alliance.Classic [white]' ) + style.inheritFrom( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - white background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + style.addDrawingStyle( group='Viewer', name='background', color=toRGB('White'), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground', color=toRGB('Black'), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries', color=toRGB('Black'), border=1, pattern='0000000000000000' ) + Viewer.Graphics.addStyle( style ) + + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + +def setup ( coriolisTechDir ): + _setup_techno( coriolisTechDir ) + _setup_display() + try: + from .techno_symb import setup as setupSymbolic + except: + pass + else: + setupSymbolic() + _loadDtr() + _loadDevices() + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/techno_symb.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/techno_symb.py new file mode 100644 index 000000000..3a4afcb6d --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/techno_symb.py @@ -0,0 +1,286 @@ + +from coriolis.helpers import l, u, n +from coriolis.Hurricane import DataBase, Technology, Layer, BasicLayer, DiffusionLayer, \ + TransistorLayer, RegularLayer, ContactLayer, ViaLayer + +__all__ = [ 'setup' ] + + +def setup (): + tech = DataBase.getDB().getTechnology() + tech.addLayerAlias( 'nwm' , 'nWell' ) + tech.addLayerAlias( 'activ' , 'active' ) + #tech.addLayerAlias( 'poly' , 'poly' ) + tech.addLayerAlias( 'psdm' , 'pImplant' ) + tech.addLayerAlias( 'nsdm' , 'nImplant' ) + tech.addLayerAlias( 'cont' , 'cut0' ) + tech.addLayerAlias( 'M1' , 'metal1' ) + tech.addLayerAlias( 'via12' , 'cut1' ) + tech.addLayerAlias( 'M2' , 'metal2' ) + tech.addLayerAlias( 'via23' , 'cut2' ) + tech.addLayerAlias( 'M3' , 'metal3' ) + tech.addLayerAlias( 'via34' , 'cut3' ) + tech.addLayerAlias( 'M4' , 'metal4' ) + tech.addLayerAlias( 'via45' , 'cut4' ) + tech.addLayerAlias( 'M5' , 'metla5' ) + tech.addLayerAlias( 'via56' , 'cut5' ) + tech.addLayerAlias( 'M6' , 'metal6' ) + tech.addLayerAlias( 'M1.block', 'blockage1' ) + tech.addLayerAlias( 'M2.block', 'blockage2' ) + tech.addLayerAlias( 'M3.block', 'blockage3' ) + tech.addLayerAlias( 'M4.block', 'blockage4' ) + tech.addLayerAlias( 'M5.block', 'blockage5' ) + tech.addLayerAlias( 'M6.block', 'blockage6' ) + tech.addLayerAlias( 'capm' , 'metcap' ) + tech.addLayerAlias( 'capm' , 'metcapdum' ) + tech.addLayerAlias( 'M5' , 'metbot' ) + + dnWell = tech.getBasicLayer( 'poly2' ) + nWell = tech.getBasicLayer( 'nwm' ) + active = tech.getBasicLayer( 'activ' ) + poly = tech.getBasicLayer( 'poly' ) + pImplant = tech.getBasicLayer( 'psdm' ) + nImplant = tech.getBasicLayer( 'nsdm' ) + cut0 = tech.getBasicLayer( 'cont' ) + metal1 = tech.getBasicLayer( 'M1' ) + cut1 = tech.getBasicLayer( 'via12' ) + metal2 = tech.getBasicLayer( 'M2' ) + cut2 = tech.getBasicLayer( 'via23' ) + metal3 = tech.getBasicLayer( 'M3' ) + cut3 = tech.getBasicLayer( 'via34' ) + metal4 = tech.getBasicLayer( 'M4' ) + cut4 = tech.getBasicLayer( 'via45' ) + metal5 = tech.getBasicLayer( 'M5' ) + cut5 = tech.getBasicLayer( 'via56' ) + metal6 = tech.getBasicLayer( 'M6' ) + blockage1 = tech.getBasicLayer( 'blockage1' ) + blockage2 = tech.getBasicLayer( 'blockage2' ) + blockage3 = tech.getBasicLayer( 'blockage3' ) + blockage4 = tech.getBasicLayer( 'blockage4' ) + blockage5 = tech.getBasicLayer( 'blockage5' ) + blockage6 = tech.getBasicLayer( 'blockage6' ) + + # Composite/Symbolic layers. + POLY2 = RegularLayer .create( tech, 'POLY2' , dnWell ) + NWELL = RegularLayer .create( tech, 'NWELL' , nWell ) + #PWELL = RegularLayer .create( tech, 'PWELL' , pWell ) + NTIE = DiffusionLayer .create( tech, 'NTIE' , nImplant , active, nWell) + PTIE = DiffusionLayer .create( tech, 'PTIE' , pImplant , active, None) + NDIF = DiffusionLayer .create( tech, 'NDIF' , nImplant , active, None ) + PDIF = DiffusionLayer .create( tech, 'PDIF' , pImplant , active, None ) + GATE = DiffusionLayer .create( tech, 'GATE' , poly , active, None ) + NTRANS = TransistorLayer.create( tech, 'NTRANS' , nImplant , active, poly, None ) + PTRANS = TransistorLayer.create( tech, 'PTRANS' , pImplant , active, poly, nWell ) + POLY = RegularLayer .create( tech, 'POLY' , poly ) + METAL1 = RegularLayer .create( tech, 'METAL1' , metal1 ) + METAL2 = RegularLayer .create( tech, 'METAL2' , metal2 ) + METAL3 = RegularLayer .create( tech, 'METAL3' , metal3 ) + METAL4 = RegularLayer .create( tech, 'METAL4' , metal4 ) + METAL5 = RegularLayer .create( tech, 'METAL5' , metal5 ) + METAL6 = RegularLayer .create( tech, 'METAL6' , metal6 ) + CONT_BODY_N = ContactLayer .create( tech, 'CONT_BODY_N', nImplant , active, cut0, metal1, None ) + CONT_BODY_P = ContactLayer .create( tech, 'CONT_BODY_P', pImplant , active, cut0, metal1, None ) + CONT_DIF_N = ContactLayer .create( tech, 'CONT_DIF_N' , nImplant , active, cut0, metal1, None ) + CONT_DIF_P = ContactLayer .create( tech, 'CONT_DIF_P' , pImplant , active, cut0, metal1, None ) + CONT_POLY = ViaLayer .create( tech, 'CONT_POLY' , poly, cut0, metal1 ) + + # VIAs for symbolic technologies. + VIA12 = ViaLayer .create( tech, 'VIA12' , metal1, cut1, metal2 ) + VIA23 = ViaLayer .create( tech, 'VIA23' , metal2, cut2, metal3 ) + #VIA23cap = ViaLayer .create( tech, 'VIA23cap' , metcap, cut2, metal3 ) + VIA34 = ViaLayer .create( tech, 'VIA34' , metal3, cut3, metal4 ) + VIA45 = ViaLayer .create( tech, 'VIA45' , metal4, cut4, metal5 ) + VIA56 = ViaLayer .create( tech, 'VIA56' , metal5, cut5, metal6 ) + #BLOCKAGE1 = RegularLayer.create( tech, 'BLOCKAGE1' , blockage1 ) + #BLOCKAGE2 = RegularLayer.create( tech, 'BLOCKAGE2' , blockage2 ) + #BLOCKAGE3 = RegularLayer.create( tech, 'BLOCKAGE3' , blockage3 ) + #BLOCKAGE4 = RegularLayer.create( tech, 'BLOCKAGE4' , blockage4 ) + #BLOCKAGE5 = RegularLayer.create( tech, 'BLOCKAGE5' , blockage5 ) + #BLOCKAGE6 = RegularLayer.create( tech, 'BLOCKAGE6' , blockage6 ) + + tech.setSymbolicLayer( CONT_BODY_N.getName() ) + tech.setSymbolicLayer( CONT_BODY_P.getName() ) + tech.setSymbolicLayer( CONT_DIF_N .getName() ) + tech.setSymbolicLayer( CONT_DIF_P .getName() ) + tech.setSymbolicLayer( CONT_POLY .getName() ) + tech.setSymbolicLayer( POLY .getName() ) + tech.setSymbolicLayer( METAL1 .getName() ) + tech.setSymbolicLayer( METAL2 .getName() ) + tech.setSymbolicLayer( METAL3 .getName() ) + tech.setSymbolicLayer( METAL4 .getName() ) + tech.setSymbolicLayer( METAL5 .getName() ) + tech.setSymbolicLayer( METAL6 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE1 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE2 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE3 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE4 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE5 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE6 .getName() ) + tech.setSymbolicLayer( VIA12 .getName() ) + tech.setSymbolicLayer( VIA23 .getName() ) + tech.setSymbolicLayer( VIA34 .getName() ) + tech.setSymbolicLayer( VIA45 .getName() ) + tech.setSymbolicLayer( VIA56 .getName() ) + + NWELL.setExtentionCap( nWell, l(0.0) ) + #PWELL.setExtentionCap( pWell, l(0.0) ) + + NTIE.setMinimalSize ( l(3.0) ) + NTIE.setExtentionCap ( nWell , l(1.5) ) + NTIE.setExtentionWidth( nWell , l(0.5) ) + NTIE.setExtentionCap ( nImplant, l(1.0) ) + NTIE.setExtentionWidth( nImplant, l(0.5) ) + NTIE.setExtentionCap ( active , l(0.5) ) + NTIE.setExtentionWidth( active , l(0.0) ) + + PTIE.setMinimalSize ( l(3.0) ) + PTIE.setExtentionCap ( nWell , l(1.5) ) + PTIE.setExtentionWidth( nWell , l(0.5) ) + PTIE.setExtentionCap ( nImplant, l(1.0) ) + PTIE.setExtentionWidth( nImplant, l(0.5) ) + PTIE.setExtentionCap ( active , l(0.5) ) + PTIE.setExtentionWidth( active , l(0.0) ) + + NDIF.setMinimalSize ( l(3.0) ) + NDIF.setExtentionCap ( nImplant, l(1.0) ) + NDIF.setExtentionWidth( nImplant, l(0.5) ) + NDIF.setExtentionCap ( active , l(0.5) ) + NDIF.setExtentionWidth( active , l(0.0) ) + + PDIF.setMinimalSize ( l(3.0) ) + PDIF.setExtentionCap ( pImplant, l(1.0) ) + PDIF.setExtentionWidth( pImplant, l(0.5) ) + PDIF.setExtentionCap ( active , l(0.5) ) + PDIF.setExtentionWidth( active , l(0.0) ) + + GATE.setMinimalSize ( l(1.0) ) + GATE.setExtentionCap ( poly , l(1.5) ) + + NTRANS.setMinimalSize ( l( 1.0) ) + NTRANS.setExtentionCap ( nImplant, l(-1.0) ) + NTRANS.setExtentionWidth( nImplant, l( 2.5) ) + NTRANS.setExtentionCap ( active , l(-1.5) ) + NTRANS.setExtentionWidth( active , l( 2.0) ) + + PTRANS.setMinimalSize ( l( 1.0) ) + PTRANS.setExtentionCap ( nWell , l(-1.0) ) + PTRANS.setExtentionWidth( nWell , l( 4.5) ) + PTRANS.setExtentionCap ( pImplant, l(-1.0) ) + PTRANS.setExtentionWidth( pImplant, l( 4.0) ) + PTRANS.setExtentionCap ( active , l(-1.5) ) + PTRANS.setExtentionWidth( active , l( 3.0) ) + + POLY .setMinimalSize ( l(1.0) ) + POLY .setExtentionCap ( poly , l(0.5) ) + #POLY2.setMinimalSize ( l(1.0) ) + #POLY2.setExtentionCap ( poly , l(0.5) ) + + METAL1 .setMinimalSize ( l(1.0) ) + METAL1 .setExtentionCap ( metal1 , l(0.5) ) + METAL2 .setMinimalSize ( l(1.0) ) + METAL2 .setExtentionCap ( metal2 , l(1.0) ) + METAL3 .setMinimalSize ( l(1.0) ) + METAL3 .setExtentionCap ( metal3 , l(1.0) ) + METAL4 .setMinimalSize ( l(1.0) ) + METAL4 .setExtentionCap ( metal4 , l(1.0) ) + METAL4 .setMinimalSpacing( l(3.0) ) + METAL5 .setMinimalSize ( l(2.0) ) + METAL5 .setExtentionCap ( metal5 , l(1.0) ) + #METAL6 .setMinimalSize ( l(2.0) ) + #METAL6 .setExtentionCap ( metal6 , l(1.0) ) + #METAL7 .setMinimalSize ( l(2.0) ) + #METAL7 .setExtentionCap ( metal7 , l(1.0) ) + #METAL8 .setMinimalSize ( l(2.0) ) + #METAL8 .setExtentionCap ( metal8 , l(1.0) ) + #METAL9 .setMinimalSize ( l(2.0) ) + #METAL9 .setExtentionCap ( metal9 , l(1.0) ) + #METAL10.setMinimalSize ( l(2.0) ) + #METAL10.setExtentionCap ( metal10 , l(1.0) ) + + # Contacts (i.e. Active <--> Metal) (symbolic). + CONT_BODY_N.setMinimalSize( l( 1.0) ) + CONT_BODY_N.setEnclosure ( nWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( nImplant, l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( active , l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_BODY_P.setMinimalSize( l( 1.0) ) + #CONT_BODY_P.setEnclosure ( pWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( pImplant, l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( active , l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_N.setMinimalSize( l( 1.0) ) + CONT_DIF_N.setEnclosure ( nImplant, l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_P.setMinimalSize( l( 1.0) ) + CONT_DIF_P.setEnclosure ( pImplant, l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_POLY.setMinimalSize( l( 1.0) ) + CONT_POLY.setEnclosure ( poly , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_POLY.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + # VIAs (i.e. Metal <--> Metal) (symbolic). + VIA12 .setMinimalSize ( l( 1.0) ) + VIA12 .setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setEnclosure ( metal2 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setMinimalSpacing( l( 4.0) ) + VIA23 .setMinimalSize ( l( 1.0) ) + VIA23 .setEnclosure ( metal2 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setEnclosure ( metal3 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setMinimalSpacing( l( 4.0) ) + VIA34 .setMinimalSize ( l( 1.0) ) + VIA34 .setEnclosure ( metal3 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setEnclosure ( metal4 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setMinimalSpacing( l( 4.0) ) + VIA45 .setMinimalSize ( l( 1.0) ) + VIA45 .setEnclosure ( metal4 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setMinimalSpacing( l( 4.0) ) + #VIA56 .setMinimalSize ( l( 1.0) ) + #VIA56 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setMinimalSpacing( l( 4.0) ) + #VIA67 .setMinimalSize ( l( 1.0) ) + #VIA67 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSize ( l( 1.0) ) + #VIA78 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA89 .setMinimalSize ( l( 1.0) ) + #VIA89 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setMinimalSpacing( l( 4.0) ) + #VIA910.setMinimalSize ( l( 1.0) ) + #VIA910.setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setEnclosure ( metal10 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setMinimalSpacing( l( 4.0) ) + + # Blockages (symbolic). + #BLOCKAGE1 .setMinimalSize ( l( 1.0) ) + #BLOCKAGE1 .setExtentionCap( blockage1 , l( 0.5) ) + #BLOCKAGE2 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE2 .setExtentionCap( blockage2 , l( 0.5) ) + #BLOCKAGE3 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE3 .setExtentionCap( blockage3 , l( 0.5) ) + #BLOCKAGE4 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE4 .setExtentionCap( blockage4 , l( 0.5) ) + #BLOCKAGE5 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE5 .setExtentionCap( blockage5 , l( 1.0) ) + #BLOCKAGE6 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE6 .setExtentionCap( blockage6 , l( 1.0) ) + #BLOCKAGE7 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE7 .setExtentionCap( blockage7 , l( 1.0) ) + #BLOCKAGE8 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE8 .setExtentionCap( blockage8 , l( 1.0) ) + #BLOCKAGE9 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE9 .setExtentionCap( blockage9 , l( 1.0) ) + #BLOCKAGE10.setMinimalSize ( l( 2.0) ) + #BLOCKAGE10.setExtentionCap( blockage10, l( 1.0) ) diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/typical.lib b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/typical.lib new file mode 100644 index 000000000..0eaff90a6 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/coriolis/gf180mcu_nsx2/typical.lib @@ -0,0 +1 @@ +.lib sm141064.ngspice typical diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/README.md b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/README.md new file mode 100644 index 000000000..2e225076d --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/README.md @@ -0,0 +1,87 @@ +# DRC Documentation + +Explains how to use the runset. + +## Folder Structure + +```text +📦drc + ┣ 📦testing + ┣ 📜GF180_MCU.lyp + ┣ 📜README.md + ┣ 📜gf_018mcu.drc + ┣ 📜gf_018mcu_antenna.drc + ┣ 📜gf_018mcu_density.drc + ┗ 📜run_drc.py + ``` + +## Rule Deck Usage + +The `run_drc.py` script takes a gds file to run DRC rule decks of GF180 technology with switches to select subsets of all checks. + +### **Switches** + +1. **FEOL** : Default is on. Use it for checking Front End Of Line layers (wells, diffusion, polys, contacts). +2. **BEOL** : Default is on. Use it for checking Back End Of Line layers (metal layers, top metal layer, vias). +3. **BEOL** : Default is on. Use it for checking Back End Of Line layers (metal layers, top metal layer, vias). +4. **GF180MCU**=A : combined options of metal_level=3, mim_option=A, metal_top=30K, poly_res=1K, and mim_cap=2 +5. **GF180MCU**=B : combined options of metal_level=4, mim_option=B, metal_top=11K, poly_res=1K, and mim_cap=2 +6. **GF180MCU**=C : combined options of metal_level=5, mim_option=B, metal_top=9K, poly_res=1K, and mim_cap=2 +7. **connectivity** : Default is off. Use it for check connectivity rules. +8. **DENSITY** : Default is off. Use it for check density rules. +9. **DENSITY_only** : Default is off. Use it for check density rules only. +10. **ANTENNA** : Default is off. Use it to turn on Antenna checks. +11. **ANTENNA_only** : Default is off. Use it to turn on Antenna checks only. +12. **OFFGRID** : Default is on. Use it for checking off-grid and acute layers (ongrid of 0.005um and angles 45 deg. unless otherwise stated). + +### Usage + +```bash + run_drc.py (--help| -h) + run_drc.py (--path=) (--gf180mcu=) [--topcell=] [--thr=] [--run_mode=] [--no_feol] [--no_beol] [--connectivity] [--density] [--density_only] [--antenna] [--antenna_only] [--no_offgrid] +``` + +Example: + +```bash + python3 run_drc.py --path=testing/switch_checking/switch_checking.gds --thr=16 --run_mode=flat --gf180mcu=A --antenna --no_offgrid +``` + +### Options + +`--help -h` Print this help message. + +`--path=` The input GDS file path. + +`--gf180mcu=` Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C). + gf180mcu=A: Select metal_top=30K mim_option=A metal_level=3LM + gf180mcu=B: Select metal_top=11K mim_option=B metal_level=4LM + gf180mcu=C: Select metal_top=9K mim_option=B metal_level=5LM + +`--topcell=` Topcell name to use. + +`--thr=` The number of threads used in run. + +`--run_mode=` Select klayout mode Allowed modes (flat , deep, tiling). [default: flat] + +`--no_feol` Turn off FEOL rules from running. + +`--no_beol` Turn off BEOL rules from running. + +`--connectivity` Turn on connectivity rules. + +`--density` Turn on Density rules. + +`--density_only` Turn on Density rules only. + +`--antenna` Turn on Antenna checks. + +`--antenna_only` Turn on Antenna checks only. + +`--no_offgrid` Turn off OFFGRID checking rules. + +### **DRC Outputs** + +Results will appear at the end of the run logs. + +The result is a database file (`.lyrdb`) of all violations in the same directoy of your design. you could view it on your file using klayout. diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/drc.lydrc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/drc.lydrc new file mode 100644 index 000000000..a6118ed19 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/drc.lydrc @@ -0,0 +1,28 @@ + + + + + drc + + + + false + false + 0 + + true + drc_scripts + tools_menu.drc.end + dsl + drc-dsl-xml + +# Read about DRC scripts in the User Manual in "Design Rule Check (DRC)" + +# This is a sample: + +poly = input(6) +active = input(1) +gate = poly & active +gate.width(0.25.micron).output(100, 0) + + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu.drc new file mode 100644 index 000000000..1e5a87a56 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu.drc @@ -0,0 +1,5456 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#=========================================================================================================================== +#------------------------------------------- GF 0.18um MCU DRC RULE DECK -------------------------------------------------- +#=========================================================================================================================== +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf_018mcu.drc -rd input=design.gds -rd report=gp180_drc.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +logger.info("Read in polygons from layers.") + + +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +lvpwell = polygons(204, 0 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +sab = polygons(49 , 0 ) +esd = polygons(24 , 0 ) +contact = polygons(33 , 0 ) +metal1 = polygons(34 , 0 ) +via1 = polygons(35 , 0 ) +metal2 = polygons(36 , 0 ) +via2 = polygons(38 , 0 ) +metal3 = polygons(42 , 0 ) +via3 = polygons(40 , 0 ) +metal4 = polygons(46 , 0 ) +via4 = polygons(41 , 0 ) +metal5 = polygons(81 , 0 ) +via5 = polygons(82 , 0 ) +metaltop = polygons(53 , 0 ) +pad = polygons(37 , 0 ) +resistor = polygons(62 , 0 ) +fhres = polygons(227, 0 ) +fusetop = polygons(75 , 0 ) +fusewindow_d = polygons(96 , 1 ) +polyfuse = polygons(220, 0 ) +mvsd = polygons(210, 0 ) +mvpsd = polygons(11 , 39) +nat = polygons(5 , 0 ) +comp_dummy = polygons(22 , 4 ) +poly2_dummy = polygons(30 , 4 ) +metal1_dummy = polygons(34 , 4 ) +metal2_dummy = polygons(36 , 4 ) +metal3_dummy = polygons(42 , 4 ) +metal4_dummy = polygons(46 , 4 ) +metal5_dummy = polygons(81 , 4 ) +metaltop_dummy = polygons(53 , 4 ) +comp_label = polygons(22 , 10) +poly2_label = polygons(30 , 10) +metal1_label = polygons(34 , 10) +metal2_label = polygons(36 , 10) +metal3_label = polygons(42 , 10) +metal4_label = polygons(46 , 10) +metal5_label = polygons(81 , 10) +metaltop_label = polygons(53 , 10) +metal1_slot = polygons(34 , 3 ) +metal2_slot = polygons(36 , 3 ) +metal3_slot = polygons(42 , 3 ) +metal4_slot = polygons(46 , 3 ) +metal5_slot = polygons(81 , 3 ) +metaltop_slot = polygons(53 , 3 ) +ubmpperi = polygons(183, 0 ) +ubmparray = polygons(184, 0 ) +ubmeplate = polygons(185, 0 ) +schottky_diode = polygons(241, 0 ) +zener = polygons(178, 0 ) +res_mk = polygons(110, 5 ) +opc_drc = polygons(124, 5 ) +ndmy = polygons(111, 5 ) +pmndmy = polygons(152, 5 ) +v5_xtor = polygons(112, 1 ) +cap_mk = polygons(117, 5 ) +mos_cap_mk = polygons(166, 5 ) +ind_mk = polygons(151, 5 ) +diode_mk = polygons(115, 5 ) +drc_bjt = polygons(127, 5 ) +lvs_bjt = polygons(118, 5 ) +mim_l_mk = polygons(117, 10) +latchup_mk = polygons(137, 5 ) +guard_ring_mk = polygons(167, 5 ) +otp_mk = polygons(173, 5 ) +mtpmark = polygons(122, 5 ) +neo_ee_mk = polygons(88 , 17) +sramcore = polygons(108, 5 ) +lvs_rf = polygons(100, 5 ) +lvs_drain = polygons(100, 7 ) +ind_mk = polygons(151, 5 ) +hvpolyrs = polygons(123, 5 ) +lvs_io = polygons(119, 5 ) +probe_mk = polygons(13 , 17) +esd_mk = polygons(24 , 5 ) +lvs_source = polygons(100, 8 ) +well_diode_mk = polygons(153, 51) +ldmos_xtor = polygons(226, 0 ) +plfuse = polygons(125, 5 ) +efuse_mk = polygons(80 , 5 ) +mcell_feol_mk = polygons(11 , 17) +ymtp_mk = polygons(86 , 17) +dev_wf_mk = polygons(128, 17) +metal1_blk = polygons(34 , 5 ) +metal2_blk = polygons(36 , 5 ) +metal3_blk = polygons(42 , 5 ) +metal4_blk = polygons(46 , 5 ) +metal5_blk = polygons(81 , 5 ) +metalt_blk = polygons(53 , 5 ) +pr_bndry = polygons(0 , 0 ) +mdiode = polygons(116, 5 ) +metal1_res = polygons(110, 11) +metal2_res = polygons(110, 12) +metal3_res = polygons(110, 13) +metal4_res = polygons(110, 14) +metal5_res = polygons(110, 15) +metal6_res = polygons(110, 16) +border = polygons(63 , 0 ) + +# ================= COUNT POLYGONS ================= +poly_count = 0 +comp_count = comp.count() +poly_count = poly_count + comp_count +dnwell_count = dnwell.count() +poly_count = poly_count + dnwell_count +nwell_count = nwell.count() +poly_count = poly_count + nwell_count +lvpwell_count = lvpwell.count() +poly_count = poly_count + lvpwell_count +dualgate_count = dualgate.count() +poly_count = poly_count + dualgate_count +poly2_count = poly2.count() +poly_count = poly_count + poly2_count +nplus_count = nplus.count() +poly_count = poly_count + nplus_count +pplus_count = pplus.count() +poly_count = poly_count + pplus_count +sab_count = sab .count() +poly_count = poly_count + sab_count +esd_count = esd .count() +poly_count = poly_count + esd_count +contact_count = contact.count() +poly_count = poly_count + contact_count +metal1_count = metal1.count() +poly_count = poly_count + metal1_count +via1_count = via1.count() +poly_count = poly_count + via1_count +metal2_count = metal2.count() +poly_count = poly_count + metal2_count +via2_count = via2.count() +poly_count = poly_count + via2_count +metal3_count = metal3.count() +poly_count = poly_count + metal3_count +via3_count = via3.count() +poly_count = poly_count + via3_count +metal4_count = metal4.count() +poly_count = poly_count + metal4_count +via4_count = via4.count() +poly_count = poly_count + via4_count +metal5_count = metal5.count() +poly_count = poly_count + metal5_count +via5_count = via5.count() +poly_count = poly_count + via5_count +metaltop_count = metaltop.count() +poly_count = poly_count + metaltop_count +pad_count = pad .count() +poly_count = poly_count + pad_count +resistor_count = resistor.count() +poly_count = poly_count + resistor_count +fhres_count = fhres.count() +poly_count = poly_count + fhres_count +fusetop_count = fusetop.count() +poly_count = poly_count + fusetop_count +fusewindow_d_count = fusewindow_d.count() +poly_count = poly_count + fusewindow_d_count +polyfuse_count = polyfuse.count() +poly_count = poly_count + polyfuse_count +mvsd_count = mvsd.count() +poly_count = poly_count + mvsd_count +mvpsd_count = mvpsd.count() +poly_count = poly_count + mvpsd_count +nat_count = nat .count() +poly_count = poly_count + nat_count +comp_dummy_count = comp_dummy.count() +poly_count = poly_count + comp_dummy_count +poly2_dummy_count = poly2_dummy.count() +poly_count = poly_count + poly2_dummy_count +metal1_dummy_count = metal1_dummy.count() +poly_count = poly_count + metal1_dummy_count +metal2_dummy_count = metal2_dummy.count() +poly_count = poly_count + metal2_dummy_count +metal3_dummy_count = metal3_dummy.count() +poly_count = poly_count + metal3_dummy_count +metal4_dummy_count = metal4_dummy.count() +poly_count = poly_count + metal4_dummy_count +metal5_dummy_count = metal5_dummy.count() +poly_count = poly_count + metal5_dummy_count +metaltop_dummy_count = metaltop_dummy.count() +poly_count = poly_count + metaltop_dummy_count +comp_label_count = comp_label.count() +poly_count = poly_count + comp_label_count +poly2_label_count = poly2_label.count() +poly_count = poly_count + poly2_label_count +metal1_label_count = metal1_label.count() +poly_count = poly_count + metal1_label_count +metal2_label_count = metal2_label.count() +poly_count = poly_count + metal2_label_count +metal3_label_count = metal3_label.count() +poly_count = poly_count + metal3_label_count +metal4_label_count = metal4_label.count() +poly_count = poly_count + metal4_label_count +metal5_label_count = metal5_label.count() +poly_count = poly_count + metal5_label_count +metaltop_label_count = metaltop_label.count() +poly_count = poly_count + metaltop_label_count +metal1_slot_count = metal1_slot.count() +poly_count = poly_count + metal1_slot_count +metal2_slot_count = metal2_slot.count() +poly_count = poly_count + metal2_slot_count +metal3_slot_count = metal3_slot.count() +poly_count = poly_count + metal3_slot_count +metal4_slot_count = metal4_slot.count() +poly_count = poly_count + metal4_slot_count +metal5_slot_count = metal5_slot.count() +poly_count = poly_count + metal5_slot_count +metaltop_slot_count = metaltop_slot.count() +poly_count = poly_count + metaltop_slot_count +ubmpperi_count = ubmpperi.count() +poly_count = poly_count + ubmpperi_count +ubmparray_count = ubmparray.count() +poly_count = poly_count + ubmparray_count +ubmeplate_count = ubmeplate.count() +poly_count = poly_count + ubmeplate_count +schottky_diode_count = schottky_diode.count() +poly_count = poly_count + schottky_diode_count +zener_count = zener.count() +poly_count = poly_count + zener_count +res_mk_count = res_mk.count() +poly_count = poly_count + res_mk_count +opc_drc_count = opc_drc.count() +poly_count = poly_count + opc_drc_count +ndmy_count = ndmy.count() +poly_count = poly_count + ndmy_count +pmndmy_count = pmndmy.count() +poly_count = poly_count + pmndmy_count +v5_xtor_count = v5_xtor.count() +poly_count = poly_count + v5_xtor_count +cap_mk_count = cap_mk.count() +poly_count = poly_count + cap_mk_count +mos_cap_mk_count = mos_cap_mk.count() +poly_count = poly_count + mos_cap_mk_count +ind_mk_count = ind_mk.count() +poly_count = poly_count + ind_mk_count +diode_mk_count = diode_mk.count() +poly_count = poly_count + diode_mk_count +drc_bjt_count = drc_bjt.count() +poly_count = poly_count + drc_bjt_count +lvs_bjt_count = lvs_bjt.count() +poly_count = poly_count + lvs_bjt_count +mim_l_mk_count = mim_l_mk.count() +poly_count = poly_count + mim_l_mk_count +latchup_mk_count = latchup_mk.count() +poly_count = poly_count + latchup_mk_count +guard_ring_mk_count = guard_ring_mk.count() +poly_count = poly_count + guard_ring_mk_count +otp_mk_count = otp_mk.count() +poly_count = poly_count + otp_mk_count +mtpmark_count = mtpmark.count() +poly_count = poly_count + mtpmark_count +neo_ee_mk_count = neo_ee_mk.count() +poly_count = poly_count + neo_ee_mk_count +sramcore_count = sramcore.count() +poly_count = poly_count + sramcore_count +lvs_rf_count = lvs_rf.count() +poly_count = poly_count + lvs_rf_count +lvs_drain_count = lvs_drain.count() +poly_count = poly_count + lvs_drain_count +ind_mk_count = ind_mk.count() +poly_count = poly_count + ind_mk_count +hvpolyrs_count = hvpolyrs.count() +poly_count = poly_count + hvpolyrs_count +lvs_io_count = lvs_io.count() +poly_count = poly_count + lvs_io_count +probe_mk_count = probe_mk.count() +poly_count = poly_count + probe_mk_count +esd_mk_count = esd_mk.count() +poly_count = poly_count + esd_mk_count +lvs_source_count = lvs_source.count() +poly_count = poly_count + lvs_source_count +well_diode_mk_count = well_diode_mk.count() +poly_count = poly_count + well_diode_mk_count +ldmos_xtor_count = ldmos_xtor.count() +poly_count = poly_count + ldmos_xtor_count +plfuse_count = plfuse.count() +poly_count = poly_count + plfuse_count +efuse_mk_count = efuse_mk.count() +poly_count = poly_count + efuse_mk_count +mcell_feol_mk_count = mcell_feol_mk.count() +poly_count = poly_count + mcell_feol_mk_count +ymtp_mk_count = ymtp_mk.count() +poly_count = poly_count + ymtp_mk_count +dev_wf_mk_count = dev_wf_mk.count() +poly_count = poly_count + dev_wf_mk_count +metal1_blk_count = metal1_blk.count() +poly_count = poly_count + metal1_blk_count +metal2_blk_count = metal2_blk.count() +poly_count = poly_count + metal2_blk_count +metal3_blk_count = metal3_blk.count() +poly_count = poly_count + metal3_blk_count +metal4_blk_count = metal4_blk.count() +poly_count = poly_count + metal4_blk_count +metal5_blk_count = metal5_blk.count() +poly_count = poly_count + metal5_blk_count +metalt_blk_count = metalt_blk.count() +poly_count = poly_count + metalt_blk_count +pr_bndry_count = pr_bndry.count() +poly_count = poly_count + pr_bndry_count +mdiode_count = mdiode.count() +poly_count = poly_count + mdiode_count +metal1_res_count = metal1_res.count() +poly_count = poly_count + metal1_res_count +metal2_res_count = metal2_res.count() +poly_count = poly_count + metal2_res_count +metal3_res_count = metal3_res.count() +poly_count = poly_count + metal3_res_count +metal4_res_count = metal4_res.count() +poly_count = poly_count + metal4_res_count +metal5_res_count = metal5_res.count() +poly_count = poly_count + metal5_res_count +metal6_res_count = metal6_res.count() +poly_count = poly_count + metal6_res_count +border_count = border.count() +poly_count = poly_count + border_count + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate +natcompsd = (nat & comp.interacting(poly2)) - tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#------------- METAL LEVEL SWITCHES ------------- +#================================================ + + +if METAL_LEVEL == "6LM" + top_via = via5 + topmin1_via = via4 + top_metal = metaltop + topmin1_metal = metal5 +elsif METAL_LEVEL == "5LM" + top_via = via4 + topmin1_via = via3 + top_metal = metal5 + topmin1_metal = metal4 +elsif METAL_LEVEL == "4LM" + top_via = via3 + topmin1_via = via2 + top_metal = metal4 + topmin1_metal = metal3 +elsif METAL_LEVEL == "3LM" + top_via = via2 + topmin1_via = via1 + top_metal = metal3 + topmin1_metal = metal2 +elsif METAL_LEVEL == "2LM" + top_via = via1 + topmin1_via = via1 + top_metal = metal2 + topmin1_metal = metal1 +end #METAL_LEVEL + +#================================================ +#------------- LAYERS CONNECTIONS --------------- +#================================================ + +if CONNECTIVITY_RULES + + logger.info("Construct connectivity for the design.") + + connect(dnwell, ncomp) + connect(ncomp, contact) + connect(pcomp, contact) + connect(lvpwell, ncomp) + connect(nwell, ncomp) + connect(natcompsd, contact) + connect(mvsd, ncomp) + connect(mvpsd, pcomp) + connect(contact, metal1) + connect(metal1, via1) + connect(via1, metal2) + connect(metal2, via2) + connect(via2, metal3) + connect(metal3, via3) + connect(via3, metal4) + connect(metal4, via4) + connect(via4, metal5) + connect(metal5, via5) + connect(via5, metaltop) + +end #CONNECTIVITY_RULES + +#================================================ +#------------ PRE-DEFINED FUNCTIONS ------------- +#================================================ + +def conn_space(layer,conn_val,not_conn_val, mode) + if conn_val > not_conn_val + raise "ERROR : Wrong connectivity implementation" + end + connected_output = layer.space(conn_val.um, mode).polygons(0.001) + unconnected_errors_unfiltered = layer.space(not_conn_val.um, mode) + singularity_errors = layer.space(0.001.um) + # Filter out the errors arising from the same net + unconnected_errors = DRC::DRCLayer::new(self, RBA::EdgePairs::new) + unconnected_errors_unfiltered.data.each do |ep| + net1 = l2n_data.probe_net(layer.data, ep.first.p1) + net2 = l2n_data.probe_net(layer.data, ep.second.p1) + if !net1 || !net2 + puts "Should not happen ..." + elsif net1.circuit != net2.circuit || net1.cluster_id != net2.cluster_id + # unconnected + unconnected_errors.data.insert(ep) + end + end + unconnected_output = unconnected_errors.polygons.or(singularity_errors.polygons(0.001)) + return connected_output, unconnected_output +end + +def conn_separation(layer1, layer2, conn_val,not_conn_val, mode) + if conn_val > not_conn_val + raise "ERROR : Wrong connectivity implementation" + end + connected_output = layer1.separation(layer2, conn_val.um, mode).polygons(0.001) + unconnected_errors_unfiltered = layer1.separation(layer2, not_conn_val.um, mode) + # Filter out the errors arising from the same net + unconnected_errors = DRC::DRCLayer::new(self, RBA::EdgePairs::new) + unconnected_errors_unfiltered.data.each do |ep| + net1 = l2n_data.probe_net(layer1.data, ep.first.p1) + net2 = l2n_data.probe_net(layer2.data, ep.second.p1) + if !net1 || !net2 + puts "Should not happen ..." + elsif net1.circuit != net2.circuit || net1.cluster_id != net2.cluster_id + # unconnected + unconnected_errors.data.insert(ep) + end + end + unconnected_output = unconnected_errors.polygons(0.001) + return connected_output, unconnected_output +end + +# === IMPLICIT EXTRACTION === +if CONNECTIVITY_RULES + logger.info("Connectivity rules enabled, Netlist object will be generated.") + netlist +end #CONNECTIVITY_RULES + +# === LAYOUT EXTENT === +CHIP = extent.sized(0.0) + +logger.info("Total area of the design is #{CHIP.area()} um^2.") + +logger.info("Total no. of polygons in the design is #{poly_count}") + +logger.info("Initialization and base layers definition.") + +#================================================ +#----------------- MAIN RUNSET ------------------ +#================================================ + +logger.info("Starting GF180MCU DRC rules.") + +if FEOL +logger.info("FEOL section") + +#================================================ +#---------------------DNWELL--------------------- +#================================================ + +# Rule DN.1: Min. DNWELL Width is 1.7µm +logger.info("Executing rule DN.1") +dn1_l1 = dnwell.width(1.7.um, euclidian).polygons(0.001) +dn1_l1.output("DN.1", "DN.1 : Min. DNWELL Width : 1.7µm") +dn1_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_dnwell, unconnected_dnwell = conn_space(dnwell, 2.5, 5.42, euclidian) + +# Rule DN.2a: Min. DNWELL Space (Equi-potential), Merge if the space is less than is 2.5µm +logger.info("Executing rule DN.2a") +dn2a_l1 = connected_dnwell +dn2a_l1.output("DN.2a", "DN.2a : Min. DNWELL Space (Equi-potential), Merge if the space is less than : 2.5µm") +dn2a_l1.forget + +# Rule DN.2b: Min. DNWELL Space (Different potential) is 5.42µm +logger.info("Executing rule DN.2b") +dn2b_l1 = unconnected_dnwell +dn2b_l1.output("DN.2b", "DN.2b : Min. DNWELL Space (Different potential) : 5.42µm") +dn2b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule DN.2b_: Min. DNWELL Space (Different potential) is 5.42µm +logger.info("Executing rule DN.2b_") +dn2b_l1 = dnwell.isolated(5.42.um, euclidian).polygons(0.001) +dn2b_l1.output("DN.2b_", "DN.2b_ : Min. DNWELL Space (Different potential) : 5.42µm") +dn2b_l1.forget + +end #CONNECTIVITY_RULES + +dn3_1 = dnwell.not_inside(pcomp.holes.not(pcomp).interacting(dnwell, 1..1).extents) +dn3_2 = dnwell.inside((pcomp.holes.not(pcomp).covering(nat.or(ncomp).or(nwell).not_interacting(dnwell)))) +# Rule DN.3: Each DNWELL shall be directly surrounded by PCOMP guard ring tied to the P-substrate potential. +logger.info("Executing rule DN.3") +dn3_l1 = dn3_1.or(dn3_2) +dn3_l1.output("DN.3", "DN.3 : Each DNWELL shall be directly surrounded by PCOMP guard ring tied to the P-substrate potential.") +dn3_l1.forget + +dn3_1.forget + +dn3_2.forget + +#================================================ +#--------------------LVPWELL--------------------- +#================================================ + +# Rule LPW.1_3.3V: Min. LVPWELL Width. is 0.6µm +logger.info("Executing rule LPW.1_3.3V") +lpw1_l1 = lvpwell.width(0.6.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +lpw1_l1.output("LPW.1_3.3V", "LPW.1_3.3V : Min. LVPWELL Width. : 0.6µm") +lpw1_l1.forget + +# Rule LPW.1_5V: Min. LVPWELL Width. is 0.74µm +logger.info("Executing rule LPW.1_5V") +lpw1_l1 = lvpwell.width(0.74.um, euclidian).polygons(0.001).overlapping(dualgate) +lpw1_l1.output("LPW.1_5V", "LPW.1_5V : Min. LVPWELL Width. : 0.74µm") +lpw1_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_lvpwell_3p3v, unconnected_lvpwell_3p3v = conn_space(lvpwell, 0.86, 1.4, euclidian) + +connected_lvpwell_5p0v, unconnected_lvpwell_5p0v = conn_space(lvpwell, 0.86, 1.7, euclidian) + +# Rule LPW.2a_3.3V: Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. is 1.4µm +logger.info("Executing rule LPW.2a_3.3V") +lpw2a_l1 = unconnected_lvpwell_3p3v.not_interacting(v5_xtor).not_interacting(dualgate) +lpw2a_l1.output("LPW.2a_3.3V", "LPW.2a_3.3V : Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. : 1.4µm") +lpw2a_l1.forget + +# Rule LPW.2a_5V: Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. is 1.7µm +logger.info("Executing rule LPW.2a_5V") +lpw2a_l1 = unconnected_lvpwell_5p0v.overlapping(dualgate) +lpw2a_l1.output("LPW.2a_5V", "LPW.2a_5V : Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. : 1.7µm") +lpw2a_l1.forget + +# Rule LPW.2b_3.3V: Min. LVPWELL to LVPWELL Space [Equi potential]. is 0.86µm +logger.info("Executing rule LPW.2b_3.3V") +lpw2b_l1 = connected_lvpwell_3p3v.not_interacting(v5_xtor).not_interacting(dualgate) +lpw2b_l1.output("LPW.2b_3.3V", "LPW.2b_3.3V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm") +lpw2b_l1.forget + +# Rule LPW.2b_5V: Min. LVPWELL to LVPWELL Space [Equi potential]. is 0.86µm +logger.info("Executing rule LPW.2b_5V") +lpw2b_l1 = connected_lvpwell_5p0v.overlapping(dualgate) +lpw2b_l1.output("LPW.2b_5V", "LPW.2b_5V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm") +lpw2b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule LPW.2a_3.3V_: Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. is 1.4µm +logger.info("Executing rule LPW.2a_3.3V_") +lpw2a_l1 = lvpwell.isolated(1.4.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +lpw2a_l1.output("LPW.2a_3.3V_", "LPW.2a_3.3V_ : Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. : 1.4µm") +lpw2a_l1.forget + +# Rule LPW.2a_5V_: Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. is 1.7µm +logger.info("Executing rule LPW.2a_5V_") +lpw2a_l1 = lvpwell.isolated(1.7.um, euclidian).polygons(0.001).overlapping(dualgate) +lpw2a_l1.output("LPW.2a_5V_", "LPW.2a_5V_ : Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. : 1.7µm") +lpw2a_l1.forget + +end #CONNECTIVITY_RULES + +# Rule LPW.3_3.3V: Min. DNWELL enclose LVPWELL. is 2.5µm +logger.info("Executing rule LPW.3_3.3V") +lpw3_l1 = dnwell.enclosing(lvpwell, 2.5.um, euclidian).polygons(0.001) +lpw3_l2 = lvpwell.not_outside(dnwell).not(dnwell) +lpw3_l = lpw3_l1.or(lpw3_l2).not_interacting(v5_xtor).not_interacting(dualgate) +lpw3_l.output("LPW.3_3.3V", "LPW.3_3.3V : Min. DNWELL enclose LVPWELL. : 2.5µm") +lpw3_l1.forget +lpw3_l2.forget +lpw3_l.forget + +# Rule LPW.3_5V: Min. DNWELL enclose LVPWELL. is 2.5µm +logger.info("Executing rule LPW.3_5V") +lpw3_l1 = dnwell.enclosing(lvpwell, 2.5.um, euclidian).polygons(0.001) +lpw3_l2 = lvpwell.not_outside(dnwell).not(dnwell) +lpw3_l = lpw3_l1.or(lpw3_l2).overlapping(dualgate) +lpw3_l.output("LPW.3_5V", "LPW.3_5V : Min. DNWELL enclose LVPWELL. : 2.5µm") +lpw3_l1.forget +lpw3_l2.forget +lpw3_l.forget + +# rule LPW.4_3.3V is not a DRC check + +# rule LPW.4_5V is not a DRC check + +# Rule LPW.5_3.3V: LVPWELL resistors must be enclosed by DNWELL. +logger.info("Executing rule LPW.5_3.3V") +lpw5_l1 = lvpwell.inside(res_mk).not_inside(dnwell).not_interacting(v5_xtor).not_interacting(dualgate) +lpw5_l1.output("LPW.5_3.3V", "LPW.5_3.3V : LVPWELL resistors must be enclosed by DNWELL.") +lpw5_l1.forget + +# Rule LPW.5_5V: LVPWELL resistors must be enclosed by DNWELL. +logger.info("Executing rule LPW.5_5V") +lpw5_l1 = lvpwell.inside(res_mk).not_inside(dnwell).overlapping(dualgate) +lpw5_l1.output("LPW.5_5V", "LPW.5_5V : LVPWELL resistors must be enclosed by DNWELL.") +lpw5_l1.forget + +# Rule LPW.11: Min. (LVPWELL outside DNWELL) space to DNWELL. is 1.5µm +logger.info("Executing rule LPW.11") +lpw11_l1 = lvpwell.outside(dnwell).separation(dnwell, 1.5.um, euclidian).polygons(0.001) +lpw11_l1.output("LPW.11", "LPW.11 : Min. (LVPWELL outside DNWELL) space to DNWELL. : 1.5µm") +lpw11_l1.forget + +# Rule LPW.12: LVPWELL cannot overlap with Nwell. +logger.info("Executing rule LPW.12") +lpw12_l1 = lvpwell.not_outside(nwell) +lpw12_l1.output("LPW.12", "LPW.12 : LVPWELL cannot overlap with Nwell.") +lpw12_l1.forget + +#================================================ +#---------------------NWELL---------------------- +#================================================ + +# Rule NW.1a_3.3V: Min. Nwell Width (This is only for litho purpose on the generated area). is 0.86µm +logger.info("Executing rule NW.1a_3.3V") +nw1a_l1 = nwell.width(0.86.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +nw1a_l1.output("NW.1a_3.3V", "NW.1a_3.3V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm") +nw1a_l1.forget + +# Rule NW.1a_5V: Min. Nwell Width (This is only for litho purpose on the generated area). is 0.86µm +logger.info("Executing rule NW.1a_5V") +nw1a_l1 = nwell.width(0.86.um, euclidian).polygons(0.001).overlapping(dualgate) +nw1a_l1.output("NW.1a_5V", "NW.1a_5V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm") +nw1a_l1.forget + +nw_1b = nwell.outside(dnwell).and(res_mk).not(comp).not(poly2) +# Rule NW.1b_3.3V: Min. Nwell Width as a resistor (Outside DNWELL only). is 2µm +logger.info("Executing rule NW.1b_3.3V") +nw1b_l1 = nw_1b.width(2.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +nw1b_l1.output("NW.1b_3.3V", "NW.1b_3.3V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm") +nw1b_l1.forget + +# Rule NW.1b_5V: Min. Nwell Width as a resistor (Outside DNWELL only). is 2µm +logger.info("Executing rule NW.1b_5V") +nw1b_l1 = nw_1b.width(2.um, euclidian).polygons(0.001).overlapping(dualgate) +nw1b_l1.output("NW.1b_5V", "NW.1b_5V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm") +nw1b_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_nwell_3p3v, unconnected_nwell_3p3v = conn_space(nwell, 0.6, 1.4, euclidian) + +connected_nwell_5p0v, unconnected_nwell_5p0v = conn_space(nwell, 0.74, 1.7, euclidian) + +# Rule NW.2a_3.3V: Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. is 0.6µm +logger.info("Executing rule NW.2a_3.3V") +nw2a_l1 = connected_nwell_3p3v.not_inside(ymtp_mk).not_interacting(v5_xtor).not_interacting(dualgate) +nw2a_l1.output("NW.2a_3.3V", "NW.2a_3.3V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.6µm") +nw2a_l1.forget + +# Rule NW.2a_5V: Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. is 0.74µm +logger.info("Executing rule NW.2a_5V") +nw2a_l1 = connected_nwell_5p0v.not_inside(ymtp_mk).overlapping(dualgate) +nw2a_l1.output("NW.2a_5V", "NW.2a_5V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.74µm") +nw2a_l1.forget + +# Rule NW.2b_3.3V: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.4µm +logger.info("Executing rule NW.2b_3.3V") +nw2b_l1 = unconnected_nwell_3p3v.not_interacting(v5_xtor).not_interacting(dualgate) +nw2b_l1.output("NW.2b_3.3V", "NW.2b_3.3V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.4µm") +nw2b_l1.forget + +# Rule NW.2b_5V: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.7µm +logger.info("Executing rule NW.2b_5V") +nw2b_l1 = unconnected_nwell_5p0v.overlapping(dualgate) +nw2b_l1.output("NW.2b_5V", "NW.2b_5V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.7µm") +nw2b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule NW.2b_3.3V_: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.4µm +logger.info("Executing rule NW.2b_3.3V_") +nw2b_l1 = nwell.isolated(1.4.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +nw2b_l1.output("NW.2b_3.3V_", "NW.2b_3.3V_ : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.4µm") +nw2b_l1.forget + +# Rule NW.2b_5V_: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.7µm +logger.info("Executing rule NW.2b_5V_") +nw2b_l1 = nwell.isolated(1.7.um, euclidian).polygons(0.001).overlapping(dualgate) +nw2b_l1.output("NW.2b_5V_", "NW.2b_5V_ : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.7µm") +nw2b_l1.forget + +end #CONNECTIVITY_RULES + +# Rule NW.3_3.3V: Min. Nwell to DNWELL space. is 3.1µm +logger.info("Executing rule NW.3_3.3V") +nw3_l1 = nwell.separation(dnwell, 3.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +nw3_l1.output("NW.3_3.3V", "NW.3_3.3V : Min. Nwell to DNWELL space. : 3.1µm") +nw3_l1.forget + +# Rule NW.3_5V: Min. Nwell to DNWELL space. is 3.1µm +logger.info("Executing rule NW.3_5V") +nw3_l1 = nwell.separation(dnwell, 3.1.um, euclidian).polygons(0.001).overlapping(dualgate) +nw3_l1.output("NW.3_5V", "NW.3_5V : Min. Nwell to DNWELL space. : 3.1µm") +nw3_l1.forget + +# Rule NW.4_3.3V: Min. Nwell to LVPWELL space. +logger.info("Executing rule NW.4_3.3V") +nw4_l1 = nwell.not_outside(lvpwell).not_interacting(v5_xtor).not_interacting(dualgate) +nw4_l1.output("NW.4_3.3V", "NW.4_3.3V : Min. Nwell to LVPWELL space.") +nw4_l1.forget + +# Rule NW.4_5V: Min. Nwell to LVPWELL space. +logger.info("Executing rule NW.4_5V") +nw4_l1 = nwell.not_outside(lvpwell).overlapping(dualgate) +nw4_l1.output("NW.4_5V", "NW.4_5V : Min. Nwell to LVPWELL space.") +nw4_l1.forget + +# Rule NW.5_3.3V: Min. DNWELL enclose Nwell. is 0.5µm +logger.info("Executing rule NW.5_3.3V") +nw5_l1 = dnwell.enclosing(nwell, 0.5.um, euclidian).polygons(0.001) +nw5_l2 = nwell.not_outside(dnwell).not(dnwell) +nw5_l = nw5_l1.or(nw5_l2).not_interacting(v5_xtor).not_interacting(dualgate) +nw5_l.output("NW.5_3.3V", "NW.5_3.3V : Min. DNWELL enclose Nwell. : 0.5µm") +nw5_l1.forget +nw5_l2.forget +nw5_l.forget + +# Rule NW.5_5V: Min. DNWELL enclose Nwell. is 0.5µm +logger.info("Executing rule NW.5_5V") +nw5_l1 = dnwell.enclosing(nwell, 0.5.um, euclidian).polygons(0.001) +nw5_l2 = nwell.not_outside(dnwell).not(dnwell) +nw5_l = nw5_l1.or(nw5_l2).overlapping(dualgate) +nw5_l.output("NW.5_5V", "NW.5_5V : Min. DNWELL enclose Nwell. : 0.5µm") +nw5_l1.forget +nw5_l2.forget +nw5_l.forget + +# Rule NW.6: Nwell resistors can only exist outside DNWELL. +logger.info("Executing rule NW.6") +nw6_l1 = nwell.inside(res_mk).interacting(dnwell) +nw6_l1.output("NW.6", "NW.6 : Nwell resistors can only exist outside DNWELL.") +nw6_l1.forget + +# rule NW.6_5V is not a DRC check + +# rule NW.7_3.3V is not a DRC check + +# rule NW.7_5V is not a DRC check + +#================================================ +#----------------------COMP---------------------- +#================================================ + +# Rule DF.1a_3.3V: Min. COMP Width. is 0.22µm +logger.info("Executing rule DF.1a_3.3V") +df1a_l1 = comp.width(0.22.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df1a_l1.output("DF.1a_3.3V", "DF.1a_3.3V : Min. COMP Width. : 0.22µm") +df1a_l1.forget + +# Rule DF.1a_5V: Min. COMP Width. is 0.3µm +logger.info("Executing rule DF.1a_5V") +df1a_l1 = comp.not_inside(mvsd).not_inside(mvpsd).width(0.3.um, euclidian).polygons(0.001).overlapping(dualgate) +df1a_l1.output("DF.1a_5V", "DF.1a_5V : Min. COMP Width. : 0.3µm") +df1a_l1.forget + +# rule DF.1b_3.3V is not a DRC check + +# rule DF.1b_5V is not a DRC check + +# Rule DF.1c_3.3V: Min. COMP Width for MOSCAP. is 1µm +logger.info("Executing rule DF.1c_3.3V") +df1c_l1 = comp.and(mos_cap_mk).width(1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df1c_l1.output("DF.1c_3.3V", "DF.1c_3.3V : Min. COMP Width for MOSCAP. : 1µm") +df1c_l1.forget + +# Rule DF.1c_5V: Min. COMP Width for MOSCAP. is 1µm +logger.info("Executing rule DF.1c_5V") +df1c_l1 = comp.and(mos_cap_mk).width(1.um, euclidian).polygons(0.001).overlapping(dualgate) +df1c_l1.output("DF.1c_5V", "DF.1c_5V : Min. COMP Width for MOSCAP. : 1µm") +df1c_l1.forget + +df_2a = comp.not(poly2).edges.and(tgate.edges) +# Rule DF.2a_3.3V: Min Channel Width. is nil,0.22µm +logger.info("Executing rule DF.2a_3.3V") +df2a_l1 = df_2a.with_length(nil,0.22.um).extended(0, 0, 0.001, 0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df2a_l1.output("DF.2a_3.3V", "DF.2a_3.3V : Min Channel Width. : nil,0.22µm") +df2a_l1.forget + +# Rule DF.2a_5V: Min Channel Width. is nil,0.3µm +logger.info("Executing rule DF.2a_5V") +df2a_l1 = df_2a.with_length(nil,0.3.um).extended(0, 0, 0.001, 0.001).overlapping(dualgate) +df2a_l1.output("DF.2a_5V", "DF.2a_5V : Min Channel Width. : nil,0.3µm") +df2a_l1.forget + +df_2a.forget + +df_2b = comp.drc(width <= 100.um).polygons(0.001).not_inside(mos_cap_mk) +# Rule DF.2b_3.3V: Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer. +logger.info("Executing rule DF.2b_3.3V") +df2b_l1 = comp.not_inside(mos_cap_mk).not_interacting(df_2b).not_interacting(v5_xtor).not_interacting(dualgate) +df2b_l1.output("DF.2b_3.3V", "DF.2b_3.3V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.") +df2b_l1.forget + +# Rule DF.2b_5V: Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer. +logger.info("Executing rule DF.2b_5V") +df2b_l1 = comp.not_inside(mos_cap_mk).not_interacting(df_2b).overlapping(dualgate) +df2b_l1.output("DF.2b_5V", "DF.2b_5V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.") +df2b_l1.forget + +df_2b.forget + +# Rule DF.3a_3.3V: Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. is 0.28µm +logger.info("Executing rule DF.3a_3.3V") +df3a_l1 = comp.not(otp_mk).space(0.28.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df3a_l1.output("DF.3a_3.3V", "DF.3a_3.3V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.28µm") +df3a_l1.forget + +# Rule DF.3a_5V: Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. is 0.36µm +logger.info("Executing rule DF.3a_5V") +df3a_l1 = comp.not(otp_mk).space(0.36.um, euclidian).polygons(0.001).overlapping(dualgate) +df3a_l1.output("DF.3a_5V", "DF.3a_5V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.36µm") +df3a_l1.forget + +df_3b_same_well = ncomp.inside(nwell).not_outside(pcomp.inside(nwell)).or(ncomp.inside(lvpwell).not_outside(pcomp.inside(lvpwell))) +df_3b_moscap = ncomp.inside(nwell).interacting(pcomp.inside(nwell)).or(ncomp.inside(lvpwell).interacting(pcomp.inside(lvpwell))).inside(mos_cap_mk) +# Rule DF.3b_3.3V: Min./Max. NCOMP Space to PCOMP in the same well for butted COMP (MOSCAP butting is not allowed). +logger.info("Executing rule DF.3b_3.3V") +df3b_l1 = df_3b_same_well.or(df_3b_moscap).not_interacting(v5_xtor).not_interacting(dualgate) +df3b_l1.output("DF.3b_3.3V", "DF.3b_3.3V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP (MOSCAP butting is not allowed).") +df3b_l1.forget + +# Rule DF.3b_5V: Min./Max. NCOMP Space to PCOMP in the same well for butted COMP(MOSCAP butting is not allowed). +logger.info("Executing rule DF.3b_5V") +df3b_l1 = df_3b_same_well.or(df_3b_moscap).overlapping(dualgate) +df3b_l1.output("DF.3b_5V", "DF.3b_5V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP(MOSCAP butting is not allowed).") +df3b_l1.forget + +df_3b_same_well.forget + +df_3b_moscap.forget + +# Rule DF.3c_3.3V: Min. COMP Space in BJT area (area marked by DRC_BJT layer). is 0.32µm +logger.info("Executing rule DF.3c_3.3V") +df3c_l1 = comp.inside(drc_bjt).space(0.32.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df3c_l1.output("DF.3c_3.3V", "DF.3c_3.3V : Min. COMP Space in BJT area (area marked by DRC_BJT layer). : 0.32µm") +df3c_l1.forget + +# Rule DF.3c_5V: Min. COMP Space in BJT area (area marked by DRC_BJT layer) hasn’t been assessed. +logger.info("Executing rule DF.3c_5V") +df3c_l1 = comp.interacting(comp.inside(drc_bjt).and(dualgate).space(10.um, euclidian).polygons(0.001)) +df3c_l1.output("DF.3c_5V", "DF.3c_5V : Min. COMP Space in BJT area (area marked by DRC_BJT layer) hasn’t been assessed.") +df3c_l1.forget + +ntap_dnwell = ncomp.not_interacting(tgate).inside(dnwell) +# Rule DF.4a_3.3V: Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. is 0.12µm +logger.info("Executing rule DF.4a_3.3V") +df4a_l1 = ntap_dnwell.separation(lvpwell.inside(dnwell), 0.12.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df4a_l1.output("DF.4a_3.3V", "DF.4a_3.3V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.12µm") +df4a_l1.forget + +# Rule DF.4a_5V: Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. is 0.16µm +logger.info("Executing rule DF.4a_5V") +df4a_l1 = ntap_dnwell.separation(lvpwell.inside(dnwell), 0.16.um, euclidian).polygons(0.001).overlapping(dualgate) +df4a_l1.output("DF.4a_5V", "DF.4a_5V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.16µm") +df4a_l1.forget + +# Rule DF.4b_3.3V: Min. DNWELL overlap of NCOMP well tap. is 0.62µm +logger.info("Executing rule DF.4b_3.3V") +df4b_l1 = dnwell.enclosing(ncomp.not_interacting(tgate), 0.62.um, euclidian).polygons(0.001) +df4b_l2 = ncomp.not_interacting(tgate).not_outside(dnwell).not(dnwell) +df4b_l = df4b_l1.or(df4b_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df4b_l.output("DF.4b_3.3V", "DF.4b_3.3V : Min. DNWELL overlap of NCOMP well tap. : 0.62µm") +df4b_l1.forget +df4b_l2.forget +df4b_l.forget + +# Rule DF.4b_5V: Min. DNWELL overlap of NCOMP well tap. is 0.66µm +logger.info("Executing rule DF.4b_5V") +df4b_l1 = dnwell.enclosing(ncomp.not_interacting(tgate), 0.66.um, euclidian).polygons(0.001) +df4b_l2 = ncomp.not_interacting(tgate).not_outside(dnwell).not(dnwell) +df4b_l = df4b_l1.or(df4b_l2).overlapping(dualgate) +df4b_l.output("DF.4b_5V", "DF.4b_5V : Min. DNWELL overlap of NCOMP well tap. : 0.66µm") +df4b_l1.forget +df4b_l2.forget +df4b_l.forget + +ntap_dnwell.forget + +nwell_n_dnwell = nwell.outside(dnwell) +# Rule DF.4c_3.3V: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.43µm +logger.info("Executing rule DF.4c_3.3V") +df4c_l1 = nwell_n_dnwell.outside(sramcore).enclosing(pcomp.outside(dnwell), 0.43.um, euclidian).polygons(0.001) +df4c_l2 = pcomp.outside(dnwell).not_outside(nwell_n_dnwell.outside(sramcore)).not(nwell_n_dnwell.outside(sramcore)) +df4c_l = df4c_l1.or(df4c_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df4c_l.output("DF.4c_3.3V", "DF.4c_3.3V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.43µm") +df4c_l1.forget +df4c_l2.forget +df4c_l.forget + +# Rule DF.4c_5V: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.6µm +logger.info("Executing rule DF.4c_5V") +df4c_l1 = nwell_n_dnwell.outside(sramcore).enclosing(pcomp.outside(dnwell), 0.6.um, euclidian).polygons(0.001) +df4c_l2 = pcomp.outside(dnwell).not_outside(nwell_n_dnwell.outside(sramcore)).not(nwell_n_dnwell.outside(sramcore)) +df4c_l = df4c_l1.or(df4c_l2).overlapping(dualgate) +df4c_l.output("DF.4c_5V", "DF.4c_5V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.6µm") +df4c_l1.forget +df4c_l2.forget +df4c_l.forget + +# Rule DF.4d_3.3V: Min. (Nwell overlap of NCOMP) outside DNWELL. is 0.12µm +logger.info("Executing rule DF.4d_3.3V") +df4d_l1 = nwell_n_dnwell.not_inside(ymtp_mk).not_inside(neo_ee_mk).enclosing(ncomp.outside(dnwell).not_inside(ymtp_mk), 0.12.um, euclidian).polygons(0.001) +df4d_l2 = ncomp.outside(dnwell).not_inside(ymtp_mk).not_outside(nwell_n_dnwell.not_inside(ymtp_mk).not_inside(neo_ee_mk)).not(nwell_n_dnwell.not_inside(ymtp_mk).not_inside(neo_ee_mk)) +df4d_l = df4d_l1.or(df4d_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df4d_l.output("DF.4d_3.3V", "DF.4d_3.3V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.12µm") +df4d_l1.forget +df4d_l2.forget +df4d_l.forget + +# Rule DF.4d_5V: Min. (Nwell overlap of NCOMP) outside DNWELL. is 0.16µm +logger.info("Executing rule DF.4d_5V") +df4d_l1 = nwell_n_dnwell.not_inside(ymtp_mk).enclosing(ncomp.outside(dnwell).not_inside(ymtp_mk), 0.16.um, euclidian).polygons(0.001) +df4d_l2 = ncomp.outside(dnwell).not_inside(ymtp_mk).not_outside(nwell_n_dnwell.not_inside(ymtp_mk)).not(nwell_n_dnwell.not_inside(ymtp_mk)) +df4d_l = df4d_l1.or(df4d_l2).overlapping(dualgate) +df4d_l.output("DF.4d_5V", "DF.4d_5V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.16µm") +df4d_l1.forget +df4d_l2.forget +df4d_l.forget + +nwell_n_dnwell.forget + +# Rule DF.4e_3.3V: Min. DNWELL overlap of PCOMP. is 0.93µm +logger.info("Executing rule DF.4e_3.3V") +df4e_l1 = dnwell.enclosing(pcomp, 0.93.um, euclidian).polygons(0.001) +df4e_l2 = pcomp.not_outside(dnwell).not(dnwell) +df4e_l = df4e_l1.or(df4e_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df4e_l.output("DF.4e_3.3V", "DF.4e_3.3V : Min. DNWELL overlap of PCOMP. : 0.93µm") +df4e_l1.forget +df4e_l2.forget +df4e_l.forget + +# Rule DF.4e_5V: Min. DNWELL overlap of PCOMP. is 1.1µm +logger.info("Executing rule DF.4e_5V") +df4e_l1 = dnwell.enclosing(pcomp, 1.1.um, euclidian).polygons(0.001) +df4e_l2 = pcomp.not_outside(dnwell).not(dnwell) +df4e_l = df4e_l1.or(df4e_l2).overlapping(dualgate) +df4e_l.output("DF.4e_5V", "DF.4e_5V : Min. DNWELL overlap of PCOMP. : 1.1µm") +df4e_l1.forget +df4e_l2.forget +df4e_l.forget + +pwell_dnwell = lvpwell.inside(dnwell) +# Rule DF.5_3.3V: Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. is 0.12µm +logger.info("Executing rule DF.5_3.3V") +df5_l1 = pwell_dnwell.enclosing(pcomp.outside(nwell), 0.12.um, euclidian).polygons(0.001) +df5_l2 = pcomp.outside(nwell).not_outside(pwell_dnwell).not(pwell_dnwell) +df5_l = df5_l1.or(df5_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df5_l.output("DF.5_3.3V", "DF.5_3.3V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.12µm") +df5_l1.forget +df5_l2.forget +df5_l.forget + +# Rule DF.5_5V: Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. is 0.16µm +logger.info("Executing rule DF.5_5V") +df5_l1 = pwell_dnwell.enclosing(pcomp.outside(nwell), 0.16.um, euclidian).polygons(0.001) +df5_l2 = pcomp.outside(nwell).not_outside(pwell_dnwell).not(pwell_dnwell) +df5_l = df5_l1.or(df5_l2).overlapping(dualgate) +df5_l.output("DF.5_5V", "DF.5_5V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.16µm") +df5_l1.forget +df5_l2.forget +df5_l.forget + +# Rule DF.6_3.3V: Min. COMP extend beyond gate (it also means source/drain overhang). is 0.24µm +logger.info("Executing rule DF.6_3.3V") +df6_l1 = comp.not(otp_mk).not_inside(ymtp_mk).enclosing(poly2.not_inside(ymtp_mk), 0.24.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df6_l1.output("DF.6_3.3V", "DF.6_3.3V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.24µm") +df6_l1.forget + +# Rule DF.6_5V: Min. COMP extend beyond gate (it also means source/drain overhang). is 0.4µm +logger.info("Executing rule DF.6_5V") +df6_l1 = comp.not(otp_mk).not_inside(mvpsd).not_inside(mvsd).not_inside(ymtp_mk).outside(sramcore).enclosing(poly2.not_inside(ymtp_mk), 0.4.um, euclidian).polygons(0.001).overlapping(dualgate) +df6_l1.output("DF.6_5V", "DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.4µm") +df6_l1.forget + +# Rule DF.7_3.3V: Min. (LVPWELL Spacer to PCOMP) inside DNWELL. is 0.43µm +logger.info("Executing rule DF.7_3.3V") +df7_l1 = pcomp.inside(dnwell).separation(pwell_dnwell, 0.43.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df7_l1.output("DF.7_3.3V", "DF.7_3.3V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.43µm") +df7_l1.forget + +# Rule DF.7_5V: Min. (LVPWELL Spacer to PCOMP) inside DNWELL. is 0.6µm +logger.info("Executing rule DF.7_5V") +df7_l1 = pcomp.inside(dnwell).outside(sramcore).separation(pwell_dnwell, 0.6.um, euclidian).polygons(0.001).overlapping(dualgate) +df7_l1.output("DF.7_5V", "DF.7_5V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.6µm") +df7_l1.forget + +# Rule DF.8_3.3V: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.43µm +logger.info("Executing rule DF.8_3.3V") +df8_l1 = pwell_dnwell.enclosing(ncomp.inside(dnwell), 0.43.um, euclidian).polygons(0.001) +df8_l2 = ncomp.inside(dnwell).not_outside(pwell_dnwell).not(pwell_dnwell) +df8_l = df8_l1.or(df8_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df8_l.output("DF.8_3.3V", "DF.8_3.3V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.43µm") +df8_l1.forget +df8_l2.forget +df8_l.forget + +# Rule DF.8_5V: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.6µm +logger.info("Executing rule DF.8_5V") +df8_l1 = pwell_dnwell.outside(sramcore).enclosing(ncomp.inside(dnwell), 0.6.um, euclidian).polygons(0.001) +df8_l2 = ncomp.inside(dnwell).not_outside(pwell_dnwell.outside(sramcore)).not(pwell_dnwell.outside(sramcore)) +df8_l = df8_l1.or(df8_l2).overlapping(dualgate) +df8_l.output("DF.8_5V", "DF.8_5V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.6µm") +df8_l1.forget +df8_l2.forget +df8_l.forget + +pwell_dnwell.forget + +# Rule DF.9_3.3V: Min. COMP area (um2). is 0.2025µm² +logger.info("Executing rule DF.9_3.3V") +df9_l1 = comp.not(otp_mk).with_area(nil, 0.2025.um).not_interacting(v5_xtor).not_interacting(dualgate) +df9_l1.output("DF.9_3.3V", "DF.9_3.3V : Min. COMP area (um2). : 0.2025µm²") +df9_l1.forget + +# Rule DF.9_5V: Min. COMP area (um2). is 0.2025µm² +logger.info("Executing rule DF.9_5V") +df9_l1 = comp.not(otp_mk).with_area(nil, 0.2025.um).overlapping(dualgate) +df9_l1.output("DF.9_5V", "DF.9_5V : Min. COMP area (um2). : 0.2025µm²") +df9_l1.forget + +# Rule DF.10_3.3V: Min. field area (um2). is 0.26µm² +logger.info("Executing rule DF.10_3.3V") +df10_l1 = comp.holes.not(comp).with_area(nil, 0.26.um).not_interacting(v5_xtor).not_interacting(dualgate) +df10_l1.output("DF.10_3.3V", "DF.10_3.3V : Min. field area (um2). : 0.26µm²") +df10_l1.forget + +# Rule DF.10_5V: Min. field area (um2). is 0.26µm² +logger.info("Executing rule DF.10_5V") +df10_l1 = comp.holes.not(comp).with_area(nil, 0.26.um).overlapping(dualgate) +df10_l1.output("DF.10_5V", "DF.10_5V : Min. field area (um2). : 0.26µm²") +df10_l1.forget + +comp_butt = comp.interacting(ncomp.interacting(pcomp).outside(pcomp)) +# Rule DF.11_3.3V: Min. Length of butting COMP edge. is 0.3µm +logger.info("Executing rule DF.11_3.3V") +df11_l1 = comp_butt.width(0.3.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df11_l1.output("DF.11_3.3V", "DF.11_3.3V : Min. Length of butting COMP edge. : 0.3µm") +df11_l1.forget + +# Rule DF.11_5V: Min. Length of butting COMP edge. is 0.3µm +logger.info("Executing rule DF.11_5V") +df11_l1 = comp_butt.width(0.3.um, euclidian).polygons(0.001).overlapping(dualgate) +df11_l1.output("DF.11_5V", "DF.11_5V : Min. Length of butting COMP edge. : 0.3µm") +df11_l1.forget + +comp_butt.forget + +# Rule DF.12_3.3V: COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking). +logger.info("Executing rule DF.12_3.3V") +df12_l1 = comp.not_interacting(schottky_diode).not_inside(nplus.or(pplus)).not_interacting(v5_xtor).not_interacting(dualgate) +df12_l1.output("DF.12_3.3V", "DF.12_3.3V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).") +df12_l1.forget + +# Rule DF.12_5V: COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking). +logger.info("Executing rule DF.12_5V") +df12_l1 = comp.not_interacting(schottky_diode).not_inside(nplus.or(pplus)).overlapping(dualgate) +df12_l1.output("DF.12_5V", "DF.12_5V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).") +df12_l1.forget + +df13_ncomp = ncomp.inside(nwell.covering(ncomp).covering(pcomp)) +df13_pcomp = pcomp.inside(nwell.covering(ncomp).covering(pcomp)) +# Rule DF.13_3.3V: Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell). +logger.info("Executing rule DF.13_3.3V") +df13_l1 = df13_ncomp.not_interacting(df13_pcomp.sized(20.um)).not_interacting(v5_xtor).not_interacting(dualgate) +df13_l1.output("DF.13_3.3V", "DF.13_3.3V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).") +df13_l1.forget + +# Rule DF.13_5V: Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell). +logger.info("Executing rule DF.13_5V") +df13_l1 = df13_ncomp.not_interacting(df13_pcomp.sized(15.um)).overlapping(dualgate) +df13_l1.output("DF.13_5V", "DF.13_5V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).") +df13_l1.forget + +df13_ncomp.forget + +df13_pcomp.forget + +# Rule DF.14_3.3V: Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell). +logger.info("Executing rule DF.14_3.3V") +df14_l1 = pcomp.outside(nwell).not_interacting(ncomp.outside(nwell).sized(20.um)).not_interacting(v5_xtor).not_interacting(dualgate) +df14_l1.output("DF.14_3.3V", "DF.14_3.3V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).") +df14_l1.forget + +# Rule DF.14_5V: Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell). +logger.info("Executing rule DF.14_5V") +df14_l1 = pcomp.outside(nwell).not_interacting(ncomp.outside(nwell).sized(15.um)).overlapping(dualgate) +df14_l1.output("DF.14_5V", "DF.14_5V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).") +df14_l1.forget + +# rule DF.15a_3.3V is not a DRC check + +# rule DF.15a_5V is not a DRC check + +# rule DF.15b_3.3V is not a DRC check + +# rule DF.15b_5V is not a DRC check + +ncomp_df16 = ncomp.outside(nwell).outside(dnwell) +# Rule DF.16_3.3V: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.43µm +logger.info("Executing rule DF.16_3.3V") +df16_l1 = ncomp_df16.not_inside(ymtp_mk).outside(sramcore).separation(nwell.outside(dnwell).not_inside(ymtp_mk), 0.43.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df16_l1.output("DF.16_3.3V", "DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.43µm") +df16_l1.forget + +# Rule DF.16_5V: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.6µm +logger.info("Executing rule DF.16_5V") +df16_l1 = ncomp_df16.not_inside(ymtp_mk).outside(sramcore).separation(nwell.outside(dnwell).not_inside(ymtp_mk), 0.6.um, euclidian).polygons(0.001).overlapping(dualgate) +df16_l1.output("DF.16_5V", "DF.16_5V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.6µm") +df16_l1.forget + +pcomp_df17 = pcomp.outside(nwell).outside(dnwell) +# Rule DF.17_3.3V: Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). is 0.12µm +logger.info("Executing rule DF.17_3.3V") +df17_l1 = pcomp_df17.separation(nwell.outside(dnwell), 0.12.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df17_l1.output("DF.17_3.3V", "DF.17_3.3V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.12µm") +df17_l1.forget + +# Rule DF.17_5V: Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). is 0.16µm +logger.info("Executing rule DF.17_5V") +df17_l1 = pcomp_df17.separation(nwell.outside(dnwell), 0.16.um, euclidian).polygons(0.001).overlapping(dualgate) +df17_l1.output("DF.17_5V", "DF.17_5V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.16µm") +df17_l1.forget + +# Rule DF.18_3.3V: Min. DNWELL space to (PCOMP outside Nwell and DNWELL). is 2.5µm +logger.info("Executing rule DF.18_3.3V") +df18_l1 = pcomp_df17.separation(dnwell, 2.5.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df18_l1.output("DF.18_3.3V", "DF.18_3.3V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm") +df18_l1.forget + +# Rule DF.18_5V: Min. DNWELL space to (PCOMP outside Nwell and DNWELL). is 2.5µm +logger.info("Executing rule DF.18_5V") +df18_l1 = pcomp_df17.separation(dnwell, 2.5.um, euclidian).polygons(0.001).overlapping(dualgate) +df18_l1.output("DF.18_5V", "DF.18_5V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm") +df18_l1.forget + +pcomp_df17.forget + +# Rule DF.19_3.3V: Min. DNWELL space to (NCOMP outside Nwell and DNWELL). is 3.2µm +logger.info("Executing rule DF.19_3.3V") +df19_l1 = ncomp_df16.separation(dnwell, 3.2.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df19_l1.output("DF.19_3.3V", "DF.19_3.3V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.2µm") +df19_l1.forget + +# Rule DF.19_5V: Min. DNWELL space to (NCOMP outside Nwell and DNWELL). is 3.28µm +logger.info("Executing rule DF.19_5V") +df19_l1 = ncomp_df16.separation(dnwell, 3.28.um, euclidian).polygons(0.001).overlapping(dualgate) +df19_l1.output("DF.19_5V", "DF.19_5V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.28µm") +df19_l1.forget + +ncomp_df16.forget + +#================================================ +#--------------------DUALGATE-------------------- +#================================================ + +# Rule DV.1: Min. Dualgate enclose DNWELL. is 0.5µm +logger.info("Executing rule DV.1") +dv1_l1 = dualgate.enclosing(dnwell, 0.5.um, euclidian).polygons(0.001) +dv1_l2 = dnwell.not_outside(dualgate).not(dualgate) +dv1_l = dv1_l1.or(dv1_l2) +dv1_l.output("DV.1", "DV.1 : Min. Dualgate enclose DNWELL. : 0.5µm") +dv1_l1.forget +dv1_l2.forget +dv1_l.forget + +# Rule DV.2: Min. Dualgate Space. Merge if Space is less than this design rule. is 0.44µm +logger.info("Executing rule DV.2") +dv2_l1 = dualgate.space(0.44.um, euclidian).polygons(0.001) +dv2_l1.output("DV.2", "DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm") +dv2_l1.forget + +# Rule DV.3: Min. Dualgate to COMP space [unrelated]. is 0.24µm +logger.info("Executing rule DV.3") +dv3_l1 = dualgate.separation(comp.outside(dualgate), 0.24.um, euclidian).polygons(0.001) +dv3_l1.output("DV.3", "DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm") +dv3_l1.forget + +# rule DV.4 is not a DRC check + +# Rule DV.5: Min. Dualgate width. is 0.7µm +logger.info("Executing rule DV.5") +dv5_l1 = dualgate.width(0.7.um, euclidian).polygons(0.001) +dv5_l1.output("DV.5", "DV.5 : Min. Dualgate width. : 0.7µm") +dv5_l1.forget + +comp_dv = comp.not(pcomp.outside(nwell)) +# Rule DV.6: Min. Dualgate enclose COMP (except substrate tap). is 0.24µm +logger.info("Executing rule DV.6") +dv6_l1 = dualgate.enclosing(comp_dv, 0.24.um, euclidian).polygons(0.001) +dv6_l2 = comp_dv.not_outside(dualgate).not(dualgate) +dv6_l = dv6_l1.or(dv6_l2) +dv6_l.output("DV.6", "DV.6 : Min. Dualgate enclose COMP (except substrate tap). : 0.24µm") +dv6_l1.forget +dv6_l2.forget +dv6_l.forget + +# Rule DV.7: COMP (except substrate tap) can not be partially overlapped by Dualgate. +logger.info("Executing rule DV.7") +dv7_l1 = dualgate.not_outside(comp_dv).not(dualgate.covering(comp_dv)) +dv7_l1.output("DV.7", "DV.7 : COMP (except substrate tap) can not be partially overlapped by Dualgate.") +dv7_l1.forget + +comp_dv.forget + +# Rule DV.8: Min Dualgate enclose Poly2. is 0.4µm +logger.info("Executing rule DV.8") +dv8_l1 = dualgate.enclosing(poly2, 0.4.um, euclidian).polygons(0.001) +dv8_l2 = poly2.not_outside(dualgate).not(dualgate) +dv8_l = dv8_l1.or(dv8_l2) +dv8_l.output("DV.8", "DV.8 : Min Dualgate enclose Poly2. : 0.4µm") +dv8_l1.forget +dv8_l2.forget +dv8_l.forget + +# Rule DV.9: 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL. +logger.info("Executing rule DV.9") +dv9_l1 = nwell.covering(pgate.and(dualgate)).covering(pgate.not_inside(v5_xtor).not_inside(dualgate)) +dv9_l1.output("DV.9", "DV.9 : 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.") +dv9_l1.forget + +#================================================ +#---------------------POLY2---------------------- +#================================================ + +# Rule PL.1_3.3V: Interconnect Width (outside PLFUSE). is 0.18µm +logger.info("Executing rule PL.1_3.3V") +pl1_l1 = poly2.outside(plfuse).not(ymtp_mk).width(0.18.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl1_l1.output("PL.1_3.3V", "PL.1_3.3V : Interconnect Width (outside PLFUSE). : 0.18µm") +pl1_l1.forget + +# Rule PL.1_5V: Interconnect Width (outside PLFUSE). is 0.2µm +logger.info("Executing rule PL.1_5V") +pl1_l1 = poly2.outside(plfuse).not(ymtp_mk).width(0.2.um, euclidian).polygons(0.001).overlapping(dualgate) +pl1_l1.output("PL.1_5V", "PL.1_5V : Interconnect Width (outside PLFUSE). : 0.2µm") +pl1_l1.forget + +# Rule PL.1a_3.3V: Interconnect Width (inside PLFUSE). is 0.18µm +logger.info("Executing rule PL.1a_3.3V") +pl1a_l1 = poly2.inside(plfuse).width(0.18.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl1a_l1.output("PL.1a_3.3V", "PL.1a_3.3V : Interconnect Width (inside PLFUSE). : 0.18µm") +pl1a_l1.forget + +# Rule PL.1a_5V: Interconnect Width (inside PLFUSE). is 0.18µm +logger.info("Executing rule PL.1a_5V") +pl1a_l1 = poly2.inside(plfuse).width(0.18.um, euclidian).polygons(0.001).overlapping(dualgate) +pl1a_l1.output("PL.1a_5V", "PL.1a_5V : Interconnect Width (inside PLFUSE). : 0.18µm") +pl1a_l1.forget + +# Rule PL.2_3.3V: Gate Width (Channel Length). is 0.28µm +logger.info("Executing rule PL.2_3.3V") +pl2_l1 = poly2.edges.and(tgate.edges).not(otp_mk).not(ymtp_mk).width(0.28.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl2_l1.output("PL.2_3.3V", "PL.2_3.3V : Gate Width (Channel Length). : 0.28µm") +pl2_l1.forget + +pl_2_5v_n = comp.not(poly2).edges.and(ngate.edges).and(v5_xtor).and(dualgate).space(0.6.um, euclidian).polygons +pl_2_5v_p = comp.not(poly2).edges.and(pgate.edges).and(v5_xtor).and(dualgate).space(0.5.um, euclidian).polygons +pl_2_6v_n = comp.not(poly2).edges.and(ngate.edges).not(v5_xtor).and(dualgate).space(0.7.um, euclidian).polygons +pl_2_6v_p = comp.not(poly2).edges.and(pgate.edges).not(v5_xtor).and(dualgate).space(0.55.um, euclidian).polygons +# Rule PL.2_5V: Gate Width (Channel Length). +logger.info("Executing rule PL.2_5V") +pl2_l1 = pl_2_5v_n.or(pl_2_5v_p).or(pl_2_6v_n.or(pl_2_6v_p)) +pl2_l1.output("PL.2_5V", "PL.2_5V : Gate Width (Channel Length).") +pl2_l1.forget + +pl_2_5v_n.forget + +pl_2_5v_p.forget + +pl_2_6v_n.forget + +pl_2_6v_p.forget + +# Rule PL.3a_3.3V: Space on COMP/Field. is 0.24µm +logger.info("Executing rule PL.3a_3.3V") +pl3a_l1 = (tgate).or(poly2.not(comp)).not(otp_mk).space(0.24.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl3a_l1.output("PL.3a_3.3V", "PL.3a_3.3V : Space on COMP/Field. : 0.24µm") +pl3a_l1.forget + +# Rule PL.3a_5V: Space on COMP/Field. is 0.24µm +logger.info("Executing rule PL.3a_5V") +pl3a_l1 = (tgate).or(poly2.not(comp)).not(otp_mk).space(0.24.um, euclidian).polygons(0.001).overlapping(dualgate) +pl3a_l1.output("PL.3a_5V", "PL.3a_5V : Space on COMP/Field. : 0.24µm") +pl3a_l1.forget + +# rule PL.3b_3.3V is not a DRC check + +# rule PL.3b_5V is not a DRC check + +poly_pl = poly2.not(otp_mk).not(ymtp_mk).not(mvsd).not(mvpsd) +comp_pl = comp.not(otp_mk).not(ymtp_mk).not(mvsd).not(mvpsd) +# Rule PL.4_3.3V: Extension beyond COMP to form Poly2 end cap. is 0.22µm +logger.info("Executing rule PL.4_3.3V") +pl4_l1 = poly_pl.enclosing(comp.not(otp_mk).not(ymtp_mk), 0.22.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl4_l1.output("PL.4_3.3V", "PL.4_3.3V : Extension beyond COMP to form Poly2 end cap. : 0.22µm") +pl4_l1.forget + +# Rule PL.4_5V: Extension beyond COMP to form Poly2 end cap. is 0.22µm +logger.info("Executing rule PL.4_5V") +pl4_l1 = poly_pl.enclosing(comp.not(otp_mk).not(ymtp_mk), 0.22.um, euclidian).polygons(0.001).overlapping(dualgate) +pl4_l1.output("PL.4_5V", "PL.4_5V : Extension beyond COMP to form Poly2 end cap. : 0.22µm") +pl4_l1.forget + +# Rule PL.5a_3.3V: Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. is 0.1µm +logger.info("Executing rule PL.5a_3.3V") +pl5a_l1 = poly_pl.separation(comp_pl, 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl5a_l1.output("PL.5a_3.3V", "PL.5a_3.3V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.1µm") +pl5a_l1.forget + +# Rule PL.5a_5V: Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. is 0.3µm +logger.info("Executing rule PL.5a_5V") +pl5a_l1 = poly_pl.outside(sramcore).separation(comp_pl, 0.3.um, euclidian).polygons(0.001).overlapping(dualgate) +pl5a_l1.output("PL.5a_5V", "PL.5a_5V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.3µm") +pl5a_l1.forget + +# Rule PL.5b_3.3V: Space from field Poly2 to related COMP. is 0.1µm +logger.info("Executing rule PL.5b_3.3V") +pl5b_l1 = poly_pl.separation(comp_pl, 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl5b_l1.output("PL.5b_3.3V", "PL.5b_3.3V : Space from field Poly2 to related COMP. : 0.1µm") +pl5b_l1.forget + +# Rule PL.5b_5V: Space from field Poly2 to related COMP. is 0.3µm +logger.info("Executing rule PL.5b_5V") +pl5b_l1 = poly_pl.outside(sramcore).separation(comp_pl, 0.3.um, euclidian).polygons(0.001).overlapping(dualgate) +pl5b_l1.output("PL.5b_5V", "PL.5b_5V : Space from field Poly2 to related COMP. : 0.3µm") +pl5b_l1.forget + +poly_pl.forget + +comp_pl.forget + +poly_90deg = poly2.corners(90.0).sized(0.1).or(poly2.corners(-90.0).sized(0.1)).not(ymtp_mk) +# Rule PL.6: 90 degree bends on the COMP are not allowed. +logger.info("Executing rule PL.6") +pl6_l1 = poly2.corners(90.0).sized(0.1).or(poly2.corners(-90.0).sized(0.1)).not(ymtp_mk).inside(comp.not(ymtp_mk)) +pl6_l1.output("PL.6", "PL.6 : 90 degree bends on the COMP are not allowed.") +pl6_l1.forget + +poly_90deg.forget + +poly_45deg = poly2.edges.with_angle(-45).or(poly2.edges.with_angle(45)) +# Rule PL.7_3.3V: 45 degree bent gate width is 0.3µm +logger.info("Executing rule PL.7_3.3V") +pl7_l1 = poly_45deg.width(0.3.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl7_l1.output("PL.7_3.3V", "PL.7_3.3V : 45 degree bent gate width : 0.3µm") +pl7_l1.forget + +# Rule PL.7_5V: 45 degree bent gate width is 0.7µm +logger.info("Executing rule PL.7_5V") +pl7_l1 = poly_45deg.width(0.7.um, euclidian).polygons(0.001).overlapping(dualgate) +pl7_l1.output("PL.7_5V", "PL.7_5V : 45 degree bent gate width : 0.7µm") +pl7_l1.forget + +poly_45deg.forget + +# Rule PL.9: Poly2 inter connect connecting 3.3V and 5V areas (area inside and outside Dualgate) are not allowed. They shall be done though metal lines only. +logger.info("Executing rule PL.9") +pl9_l1 = poly2.interacting(poly2.not(v5_xtor).not(dualgate)).interacting(poly2.and(dualgate)) +pl9_l1.output("PL.9", "PL.9 : Poly2 inter connect connecting 3.3V and 5V areas (area inside and outside Dualgate) are not allowed. They shall be done though metal lines only.") +pl9_l1.forget + +# rule PL.10 is not a DRC check + +# Rule PL.11: V5_Xtor must enclose 5V device. +logger.info("Executing rule PL.11") +pl11_l1 = v5_xtor.not_interacting(dualgate.or(otp_mk)) +pl11_l1.output("PL.11", "PL.11 : V5_Xtor must enclose 5V device.") +pl11_l1.forget + +# rule PL.12_3.3V is not a DRC check + +# Rule PL.12: V5_Xtor enclose 5V Comp. +logger.info("Executing rule PL.12") +pl12_l1 = comp.interacting(v5_xtor).not(v5_xtor) +pl12_l1.output("PL.12", "PL.12 : V5_Xtor enclose 5V Comp.") +pl12_l1.forget + +#================================================ +#---------------------NPLUS---------------------- +#================================================ + +# Rule NP.1: min. nplus width is 0.4µm +logger.info("Executing rule NP.1") +np1_l1 = nplus.width(0.4.um, euclidian).polygons(0.001) +np1_l1.output("NP.1", "NP.1 : min. nplus width : 0.4µm") +np1_l1.forget + +# Rule NP.2: min. nplus spacing is 0.4µm +logger.info("Executing rule NP.2") +np2_l1 = nplus.space(0.4.um, euclidian).polygons(0.001) +np2_l1.output("NP.2", "NP.2 : min. nplus spacing : 0.4µm") +np2_l1.forget + +# Rule NP.3a: Space to PCOMP for PCOMP: (1) Inside Nwell (2) Outside LVPWELL but inside DNWELL. is 0.16µm +logger.info("Executing rule NP.3a") +np3a_l1 = nplus.separation((pcomp.inside(nwell)).or(pcomp.outside(lvpwell).inside(dnwell)), 0.16.um, euclidian).polygons(0.001) +np3a_l1.output("NP.3a", "NP.3a : Space to PCOMP for PCOMP: (1) Inside Nwell (2) Outside LVPWELL but inside DNWELL. : 0.16µm") +np3a_l1.forget + +np_3bi_extend = lvpwell.inside(dnwell).sized(-0.429.um) +np_3bi = pcomp.edges.and(lvpwell.inside(dnwell).not(np_3bi_extend)) +# Rule NP.3bi: Space to PCOMP: For Inside DNWELL, inside LVPWELL:(i) For PCOMP overlap by LVPWELL < 0.43um. is 0.16µm +logger.info("Executing rule NP.3bi") +np3bi_l1 = nplus.not_outside(lvpwell).inside(dnwell).edges.separation(np_3bi, 0.16.um, euclidian).polygons(0.001) +np3bi_l1.output("NP.3bi", "NP.3bi : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(i) For PCOMP overlap by LVPWELL < 0.43um. : 0.16µm") +np3bi_l1.forget + +np_3bi_extend.forget + +np_3bi.forget + +np_3bii_extend = lvpwell.inside(dnwell).sized(-0.429.um) +np_3bii = pcomp.edges.and(np_3bii_extend) +# Rule NP.3bii: Space to PCOMP: For Inside DNWELL, inside LVPWELL:(ii) For PCOMP overlap by LVPWELL >= 0.43um. is 0.08µm +logger.info("Executing rule NP.3bii") +np3bii_l1 = nplus.not_outside(lvpwell).inside(dnwell).edges.separation(np_3bii, 0.08.um, euclidian).polygons(0.001) +np3bii_l1.output("NP.3bii", "NP.3bii : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(ii) For PCOMP overlap by LVPWELL >= 0.43um. : 0.08µm") +np3bii_l1.forget + +np_3bii_extend.forget + +np_3bii.forget + +np_3ci = pcomp.edges.and(nwell.outside(dnwell).sized(0.429.um)) +# Rule NP.3ci: Space to PCOMP: For Outside DNWELL:(i) For PCOMP space to Nwell < 0.43um. is 0.16µm +logger.info("Executing rule NP.3ci") +np3ci_l1 = nplus.outside(dnwell).edges.separation(np_3ci, 0.16.um, euclidian).polygons +np3ci_l1.output("NP.3ci", "NP.3ci : Space to PCOMP: For Outside DNWELL:(i) For PCOMP space to Nwell < 0.43um. : 0.16µm") +np3ci_l1.forget + +np_3ci.forget + +np_3cii = pcomp.edges.not(nwell.outside(dnwell).sized(0.429.um)) +# Rule NP.3cii: Space to PCOMP: For Outside DNWELL:(ii) For PCOMP space to Nwell >= 0.43um. is 0.08µm +logger.info("Executing rule NP.3cii") +np3cii_l1 = nplus.outside(dnwell).edges.separation(np_3cii, 0.08.um, euclidian).polygons +np3cii_l1.output("NP.3cii", "NP.3cii : Space to PCOMP: For Outside DNWELL:(ii) For PCOMP space to Nwell >= 0.43um. : 0.08µm") +np3cii_l1.forget + +np_3cii.forget + +# Rule NP.3d: Min/max space to a butted PCOMP. +logger.info("Executing rule NP.3d") +np3d_l1 = nplus.not_outside(pcomp) +np3d_l1.output("NP.3d", "NP.3d : Min/max space to a butted PCOMP.") +np3d_l1.forget + +# Rule NP.3e: Space to related PCOMP edge adjacent to a butting edge. +logger.info("Executing rule NP.3e") +np3e_l1 = nplus.not_outside(pcomp) +np3e_l1.output("NP.3e", "NP.3e : Space to related PCOMP edge adjacent to a butting edge.") +np3e_l1.forget + +# Rule NP.4a: Space to related P-channel gate at a butting edge parallel to gate. is 0.32µm +logger.info("Executing rule NP.4a") +np4a_l1 = nplus.edges.and(pcomp.edges).separation(pgate.edges, 0.32.um, projection).polygons(0.001) +np4a_l1.output("NP.4a", "NP.4a : Space to related P-channel gate at a butting edge parallel to gate. : 0.32µm") +np4a_l1.forget + +np_4b_poly = poly2.edges.interacting(pgate.edges.not(pcomp.edges)).centers(0, 0.99).and(pgate.sized(0.32.um)) +# Rule NP.4b: Within 0.32um of channel, space to P-channel gate extension perpendicular to the direction of Poly2. +logger.info("Executing rule NP.4b") +np4b_l1 = nplus.interacting(nplus.edges.separation(np_4b_poly, 0.22.um, projection).polygons(0.001)) +np4b_l1.output("NP.4b", "NP.4b : Within 0.32um of channel, space to P-channel gate extension perpendicular to the direction of Poly2.") +np4b_l1.forget + +np_4b_poly.forget + +# Rule NP.5a: Overlap of N-channel gate. is 0.23µm +logger.info("Executing rule NP.5a") +np5a_l1 = nplus.enclosing(ngate, 0.23.um, euclidian).polygons(0.001) +np5a_l2 = ngate.not_outside(nplus).not(nplus) +np5a_l = np5a_l1.or(np5a_l2) +np5a_l.output("NP.5a", "NP.5a : Overlap of N-channel gate. : 0.23µm") +np5a_l1.forget +np5a_l2.forget +np5a_l.forget + +# Rule NP.5b: Extension beyond COMP for the COMP (1) inside LVPWELL (2) outside Nwell and DNWELL. is 0.16µm +logger.info("Executing rule NP.5b") +np5b_l1 = nplus.not_outside(lvpwell).or(nplus.outside(nwell).outside(dnwell)).edges.not(pplus).enclosing(comp.edges, 0.16.um, euclidian).polygons(0.001) +np5b_l1.output("NP.5b", "NP.5b : Extension beyond COMP for the COMP (1) inside LVPWELL (2) outside Nwell and DNWELL. : 0.16µm") +np5b_l1.forget + +np_5ci_background = nplus.not_inside(lvpwell).inside(dnwell).edges +np_5ci_foreground = ncomp.not_inside(lvpwell).inside(dnwell).edges.not(pplus.edges).and(lvpwell.inside(dnwell).sized(0.429.um)) +# Rule NP.5ci: Extension beyond COMP: For Inside DNWELL: (i)For Nplus < 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. is 0.16µm +logger.info("Executing rule NP.5ci") +np5ci_l1 = np_5ci_background.enclosing(np_5ci_foreground, 0.16.um, projection).polygons(0.001) +np5ci_l1.output("NP.5ci", "NP.5ci : Extension beyond COMP: For Inside DNWELL: (i)For Nplus < 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.16µm") +np5ci_l1.forget + +np_5ci_background.forget + +np_5ci_foreground.forget + +np_5cii_background = nplus.not_inside(lvpwell).inside(dnwell).edges +np_5cii_foreground = ncomp.not_inside(lvpwell).inside(dnwell).edges.not(pplus.edges).not(lvpwell.inside(dnwell).sized(0.429.um)) +# Rule NP.5cii: Extension beyond COMP: For Inside DNWELL: (ii) For Nplus >= 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. is 0.02µm +logger.info("Executing rule NP.5cii") +np5cii_l1 = np_5cii_background.enclosing(np_5cii_foreground, 0.02.um, projection).polygons(0.001) +np5cii_l1.output("NP.5cii", "NP.5cii : Extension beyond COMP: For Inside DNWELL: (ii) For Nplus >= 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.02µm") +np5cii_l1.forget + +np_5cii_background.forget + +np_5cii_foreground.forget + +np_5di_background = nplus.not_outside(nwell).outside(dnwell).edges +np_5di_extend = nwell.outside(dnwell).not(nwell.outside(dnwell).sized(-0.429.um)) +np_5di_foreground = ncomp.not_outside(nwell).outside(dnwell).edges.not(pplus.edges).and(np_5di_extend) +# Rule NP.5di: Extension beyond COMP: For Outside DNWELL, inside Nwell: (i) For Nwell overlap of Nplus < 0.43um. is 0.16µm +logger.info("Executing rule NP.5di") +np5di_l1 = np_5di_background.enclosing(np_5di_foreground, 0.16.um, projection).polygons(0.001) +np5di_l1.output("NP.5di", "NP.5di : Extension beyond COMP: For Outside DNWELL, inside Nwell: (i) For Nwell overlap of Nplus < 0.43um. : 0.16µm") +np5di_l1.forget + +np_5di_background.forget + +np_5di_extend.forget + +np_5di_foreground.forget + +np_5dii_background = nplus.not_outside(nwell).outside(dnwell).edges.not(pplus.edges) +np_5dii_extend = nwell.outside(dnwell).sized(-0.429.um) +np_5dii_foreground = ncomp.not_outside(nwell).outside(dnwell).edges.not(pplus.edges).and(np_5dii_extend) +# Rule NP.5dii: Extension beyond COMP: For Outside DNWELL, inside Nwell: (ii) For Nwell overlap of Nplus >= 0.43um. is 0.02µm +logger.info("Executing rule NP.5dii") +np5dii_l1 = np_5dii_background.enclosing(np_5dii_foreground, 0.02.um, euclidian).polygons(0.001) +np5dii_l1.output("NP.5dii", "NP.5dii : Extension beyond COMP: For Outside DNWELL, inside Nwell: (ii) For Nwell overlap of Nplus >= 0.43um. : 0.02µm") +np5dii_l1.forget + +np_5dii_background.forget + +np_5dii_extend.forget + +np_5dii_foreground.forget + +# Rule NP.6: Overlap with NCOMP butted to PCOMP. is 0.22µm +logger.info("Executing rule NP.6") +np6_l1 = comp.interacting(nplus).enclosing(pcomp.interacting(nplus), 0.22.um, projection).polygons +np6_l1.output("NP.6", "NP.6 : Overlap with NCOMP butted to PCOMP. : 0.22µm") +np6_l1.forget + +# Rule NP.7: Space to unrelated unsalicided Poly2. is 0.18µm +logger.info("Executing rule NP.7") +np7_l1 = nplus.separation(poly2.and(sab), 0.18.um, euclidian).polygons(0.001) +np7_l1.output("NP.7", "NP.7 : Space to unrelated unsalicided Poly2. : 0.18µm") +np7_l1.forget + +# Rule NP.8a: Minimum Nplus area (um2). is 0.35µm² +logger.info("Executing rule NP.8a") +np8a_l1 = nplus.with_area(nil, 0.35.um) +np8a_l1.output("NP.8a", "NP.8a : Minimum Nplus area (um2). : 0.35µm²") +np8a_l1.forget + +# Rule NP.8b: Minimum area enclosed by Nplus (um2). is 0.35µm² +logger.info("Executing rule NP.8b") +np8b_l1 = nplus.holes.with_area(nil, 0.35.um) +np8b_l1.output("NP.8b", "NP.8b : Minimum area enclosed by Nplus (um2). : 0.35µm²") +np8b_l1.forget + +# Rule NP.9: Overlap of unsalicided Poly2. is 0.18µm +logger.info("Executing rule NP.9") +np9_l1 = nplus.enclosing(poly2.and(sab), 0.18.um, euclidian).polygons(0.001) +np9_l2 = poly2.and(sab).not_outside(nplus).not(nplus) +np9_l = np9_l1.or(np9_l2) +np9_l.output("NP.9", "NP.9 : Overlap of unsalicided Poly2. : 0.18µm") +np9_l1.forget +np9_l2.forget +np9_l.forget + +# Rule NP.10: Overlap of unsalicided COMP. is 0.18µm +logger.info("Executing rule NP.10") +np10_l1 = nplus.enclosing(comp.and(sab), 0.18.um, euclidian).polygons(0.001) +np10_l1.output("NP.10", "NP.10 : Overlap of unsalicided COMP. : 0.18µm") +np10_l1.forget + +np_11_in_dnwell = nplus.interacting(nplus.edges.and(pcomp.edges).and(lvpwell.inside(dnwell).not(lvpwell.inside(dnwell).sized(-0.429.um)))) +np_11_out_dnwell = nplus.interacting(nplus.edges.and(pcomp.edges).and(nwell.outside(dnwell).sized(0.429.um))) +# Rule NP.11: Butting Nplus and PCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case). +logger.info("Executing rule NP.11") +np11_l1 = np_11_in_dnwell.or(np_11_out_dnwell) +np11_l1.output("NP.11", "NP.11 : Butting Nplus and PCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case).") +np11_l1.forget + +np_11_in_dnwell.forget + +np_11_out_dnwell.forget + +# Rule NP.12: Overlap with P-channel poly2 gate extension is forbidden within 0.32um of P-channel gate. +logger.info("Executing rule NP.12") +np12_l1 = nplus.interacting(nplus.edges.separation(pgate.edges.and(pcomp.edges), 0.32.um, euclidian).polygons(0.001)) +np12_l1.output("NP.12", "NP.12 : Overlap with P-channel poly2 gate extension is forbidden within 0.32um of P-channel gate.") +np12_l1.forget + +#================================================ +#---------------------PPLUS---------------------- +#================================================ + +# Rule PP.1: min. pplus width is 0.4µm +logger.info("Executing rule PP.1") +pp1_l1 = pplus.width(0.4.um, euclidian).polygons(0.001) +pp1_l1.output("PP.1", "PP.1 : min. pplus width : 0.4µm") +pp1_l1.forget + +# Rule PP.2: min. pplus spacing is 0.4µm +logger.info("Executing rule PP.2") +pp2_l1 = pplus.space(0.4.um, euclidian).polygons(0.001) +pp2_l1.output("PP.2", "PP.2 : min. pplus spacing : 0.4µm") +pp2_l1.forget + +# Rule PP.3a: Space to NCOMP for NCOMP (1) inside LVPWELL (2) outside NWELL and DNWELL. is 0.16µm +logger.info("Executing rule PP.3a") +pp3a_l1 = pplus.separation((ncomp.inside(lvpwell)).or(ncomp.outside(nwell).outside(dnwell)), 0.16.um, euclidian).polygons(0.001) +pp3a_l1.output("PP.3a", "PP.3a : Space to NCOMP for NCOMP (1) inside LVPWELL (2) outside NWELL and DNWELL. : 0.16µm") +pp3a_l1.forget + +pp_3bi = ncomp.edges.not(lvpwell.inside(dnwell).sized(0.429.um)) +# Rule PP.3bi: Space to NCOMP: For Inside DNWELL. (i) NCOMP space to LVPWELL >= 0.43um. is 0.08µm +logger.info("Executing rule PP.3bi") +pp3bi_l1 = pplus.inside(dnwell).edges.separation(pp_3bi, 0.08.um, euclidian).polygons(0.001) +pp3bi_l1.output("PP.3bi", "PP.3bi : Space to NCOMP: For Inside DNWELL. (i) NCOMP space to LVPWELL >= 0.43um. : 0.08µm") +pp3bi_l1.forget + +pp_3bi.forget + +pp_3bii = ncomp.edges.and(lvpwell.inside(dnwell).sized(0.429.um)) +# Rule PP.3bii: Space to NCOMP: For Inside DNWELL. (ii) NCOMP space to LVPWELL < 0.43um. is 0.16µm +logger.info("Executing rule PP.3bii") +pp3bii_l1 = pplus.inside(dnwell).edges.separation(pp_3bii, 0.16.um, euclidian).polygons(0.001) +pp3bii_l1.output("PP.3bii", "PP.3bii : Space to NCOMP: For Inside DNWELL. (ii) NCOMP space to LVPWELL < 0.43um. : 0.16µm") +pp3bii_l1.forget + +pp_3bii.forget + +pp_3ci_extend = nwell.outside(dnwell).sized(-0.429.um) +pp_3ci = ncomp.edges.and(pp_3ci_extend) +# Rule PP.3ci: Space to NCOMP: For Outside DNWELL, inside Nwell: (i) NWELL Overlap of NCOMP >= 0.43um. is 0.08µm +logger.info("Executing rule PP.3ci") +pp3ci_l1 = pplus.outside(dnwell).edges.separation(pp_3ci, 0.08.um, euclidian).polygons(0.001) +pp3ci_l1.output("PP.3ci", "PP.3ci : Space to NCOMP: For Outside DNWELL, inside Nwell: (i) NWELL Overlap of NCOMP >= 0.43um. : 0.08µm") +pp3ci_l1.forget + +pp_3ci_extend.forget + +pp_3ci.forget + +pp_3cii_extend = nwell.outside(dnwell).not(nwell.outside(dnwell).sized(-0.429.um)) +pp_3cii = ncomp.edges.and(pp_3cii_extend) +# Rule PP.3cii: Space to NCOMP: For Outside DNWELL, inside Nwell: (ii) NWELL Overlap of NCOMP 0.43um. is 0.16µm +logger.info("Executing rule PP.3cii") +pp3cii_l1 = pplus.outside(dnwell).edges.separation(pp_3cii, 0.16.um, euclidian).polygons(0.001) +pp3cii_l1.output("PP.3cii", "PP.3cii : Space to NCOMP: For Outside DNWELL, inside Nwell: (ii) NWELL Overlap of NCOMP 0.43um. : 0.16µm") +pp3cii_l1.forget + +pp_3cii_extend.forget + +pp_3cii.forget + +# Rule PP.3d: Min/max space to a butted NCOMP. +logger.info("Executing rule PP.3d") +pp3d_l1 = pplus.not_outside(ncomp) +pp3d_l1.output("PP.3d", "PP.3d : Min/max space to a butted NCOMP.") +pp3d_l1.forget + +# Rule PP.3e: Space to NCOMP edge adjacent to a butting edge. +logger.info("Executing rule PP.3e") +pp3e_l1 = pplus.not_outside(ncomp) +pp3e_l1.output("PP.3e", "PP.3e : Space to NCOMP edge adjacent to a butting edge.") +pp3e_l1.forget + +# Rule PP.4a: Space related to N-channel gate at a butting edge parallel to gate. is 0.32µm +logger.info("Executing rule PP.4a") +pp4a_l1 = pplus.edges.and(ncomp.edges).separation(ngate.edges, 0.32.um, projection).polygons(0.001) +pp4a_l1.output("PP.4a", "PP.4a : Space related to N-channel gate at a butting edge parallel to gate. : 0.32µm") +pp4a_l1.forget + +pp_4b_poly = poly2.edges.interacting(ngate.edges.not(ncomp.edges)).centers(0, 0.99).and(ngate.sized(0.32.um)) +# Rule PP.4b: Within 0.32um of channel, space to N-channel gate extension perpendicular to the direction of Poly2. +logger.info("Executing rule PP.4b") +pp4b_l1 = pplus.interacting(pplus.edges.separation(pp_4b_poly, 0.22.um, projection).polygons(0.001)) +pp4b_l1.output("PP.4b", "PP.4b : Within 0.32um of channel, space to N-channel gate extension perpendicular to the direction of Poly2.") +pp4b_l1.forget + +pp_4b_poly.forget + +# Rule PP.5a: Overlap of P-channel gate. is 0.23µm +logger.info("Executing rule PP.5a") +pp5a_l1 = pplus.enclosing(pgate, 0.23.um, euclidian).polygons(0.001) +pp5a_l2 = pgate.not_outside(pplus).not(pplus) +pp5a_l = pp5a_l1.or(pp5a_l2) +pp5a_l.output("PP.5a", "PP.5a : Overlap of P-channel gate. : 0.23µm") +pp5a_l1.forget +pp5a_l2.forget +pp5a_l.forget + +# Rule PP.5b: Extension beyond COMP for COMP (1) Inside NWELL (2) outside LVPWELL but inside DNWELL. is 0.16µm +logger.info("Executing rule PP.5b") +pp5b_l1 = pplus.not_outside(nwell).or(pplus.outside(lvpwell).inside(dnwell)).edges.not(nplus).enclosing(comp.edges, 0.16.um, euclidian).polygons(0.001) +pp5b_l1.output("PP.5b", "PP.5b : Extension beyond COMP for COMP (1) Inside NWELL (2) outside LVPWELL but inside DNWELL. : 0.16µm") +pp5b_l1.forget + +pp_5ci_background = pplus.not_outside(lvpwell).inside(dnwell).edges.not(nplus.edges) +pp_5ci_extend = lvpwell.inside(dnwell).sized(-0.429.um) +pp_5ci_foreground = pcomp.not_outside(lvpwell).inside(dnwell).edges.not(nplus.edges).inside_part(pp_5ci_extend) +# Rule PP.5ci: Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (i) For LVPWELL overlap of Pplus >= 0.43um for LVPWELL tap. is 0.02µm +logger.info("Executing rule PP.5ci") +pp5ci_l1 = pp_5ci_background.enclosing(pp_5ci_foreground, 0.02.um, euclidian).polygons(0.001) +pp5ci_l1.output("PP.5ci", "PP.5ci : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (i) For LVPWELL overlap of Pplus >= 0.43um for LVPWELL tap. : 0.02µm") +pp5ci_l1.forget + +pp_5ci_background.forget + +pp_5ci_extend.forget + +pp_5ci_foreground.forget + +pp_5cii_background = pplus.not_outside(lvpwell).inside(dnwell).edges +pp_5cii_extend = lvpwell.inside(dnwell).not(lvpwell.inside(dnwell).sized(-0.429.um)) +pp_5cii_foreground = pcomp.not_outside(lvpwell).inside(dnwell).edges.not(nplus.edges).and(pp_5cii_extend) +# Rule PP.5cii: Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (ii) For LVPWELL overlap of Pplus < 0.43um for the LVPWELL tap. is 0.16µm +logger.info("Executing rule PP.5cii") +pp5cii_l1 = pp_5cii_background.enclosing(pp_5cii_foreground, 0.16.um, projection).polygons(0.001) +pp5cii_l1.output("PP.5cii", "PP.5cii : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (ii) For LVPWELL overlap of Pplus < 0.43um for the LVPWELL tap. : 0.16µm") +pp5cii_l1.forget + +pp_5cii_background.forget + +pp_5cii_extend.forget + +pp_5cii_foreground.forget + +pp_5di_background = pplus.outside(dnwell).edges +pp_5di_foreground = pcomp.outside(dnwell).edges.not(nplus.edges).not(nwell.outside(dnwell).sized(0.429.um)) +# Rule PP.5di: Extension beyond COMP: For Outside DNWELL (i) For Pplus to NWELL space >= 0.43um for Pfield or LVPWELL tap. is 0.02µm +logger.info("Executing rule PP.5di") +pp5di_l1 = pp_5di_background.enclosing(pp_5di_foreground, 0.02.um, projection).polygons(0.001) +pp5di_l1.output("PP.5di", "PP.5di : Extension beyond COMP: For Outside DNWELL (i) For Pplus to NWELL space >= 0.43um for Pfield or LVPWELL tap. : 0.02µm") +pp5di_l1.forget + +pp_5di_background.forget + +pp_5di_foreground.forget + +pp_5dii_background = pplus.outside(dnwell).edges +pp_5dii_foreground = pcomp.outside(dnwell).edges.not(nplus.edges).and(nwell.outside(dnwell).sized(0.429.um)) +# Rule PP.5dii: Extension beyond COMP: For Outside DNWELL (ii) For Pplus to NWELL space < 0.43um for Pfield or LVPWELL tap. is 0.16µm +logger.info("Executing rule PP.5dii") +pp5dii_l1 = pp_5dii_background.enclosing(pp_5dii_foreground, 0.16.um, projection).polygons(0.001) +pp5dii_l1.output("PP.5dii", "PP.5dii : Extension beyond COMP: For Outside DNWELL (ii) For Pplus to NWELL space < 0.43um for Pfield or LVPWELL tap. : 0.16µm") +pp5dii_l1.forget + +pp_5dii_background.forget + +pp_5dii_foreground.forget + +# Rule PP.6: Overlap with PCOMP butted to NCOMP. is 0.22µm +logger.info("Executing rule PP.6") +pp6_l1 = comp.interacting(pplus).enclosing(ncomp.interacting(pplus), 0.22.um, projection).polygons +pp6_l1.output("PP.6", "PP.6 : Overlap with PCOMP butted to NCOMP. : 0.22µm") +pp6_l1.forget + +# Rule PP.7: Space to unrelated unsalicided Poly2. is 0.18µm +logger.info("Executing rule PP.7") +pp7_l1 = pplus.separation(poly2.and(sab), 0.18.um, euclidian).polygons(0.001) +pp7_l1.output("PP.7", "PP.7 : Space to unrelated unsalicided Poly2. : 0.18µm") +pp7_l1.forget + +# Rule PP.8a: Minimum Pplus area (um2). is 0.35µm² +logger.info("Executing rule PP.8a") +pp8a_l1 = pplus.with_area(nil, 0.35.um) +pp8a_l1.output("PP.8a", "PP.8a : Minimum Pplus area (um2). : 0.35µm²") +pp8a_l1.forget + +# Rule PP.8b: Minimum area enclosed by Pplus (um2). is 0.35µm² +logger.info("Executing rule PP.8b") +pp8b_l1 = pplus.holes.with_area(nil, 0.35.um) +pp8b_l1.output("PP.8b", "PP.8b : Minimum area enclosed by Pplus (um2). : 0.35µm²") +pp8b_l1.forget + +# Rule PP.9: Overlap of unsalicided Poly2. is 0.18µm +logger.info("Executing rule PP.9") +pp9_l1 = pplus.enclosing(poly2.not_interacting(resistor).and(sab), 0.18.um, euclidian).polygons(0.001) +pp9_l2 = poly2.not_interacting(resistor).and(sab).not_outside(pplus).not(pplus) +pp9_l = pp9_l1.or(pp9_l2) +pp9_l.output("PP.9", "PP.9 : Overlap of unsalicided Poly2. : 0.18µm") +pp9_l1.forget +pp9_l2.forget +pp9_l.forget + +# Rule PP.10: Overlap of unsalicided COMP. is 0.18µm +logger.info("Executing rule PP.10") +pp10_l1 = pplus.enclosing(comp.and(sab), 0.18.um, euclidian).polygons(0.001) +pp10_l1.output("PP.10", "PP.10 : Overlap of unsalicided COMP. : 0.18µm") +pp10_l1.forget + +pp_11_in_dnwell = pplus.interacting(pplus.edges.and(ncomp.edges).and(lvpwell.inside(dnwell).sized(0.429.um))) +pp_11_out_dnwell = pplus.interacting(pplus.edges.and(ncomp.edges).and(nwell.outside(dnwell).not(nwell.outside(dnwell).sized(-0.429.um)))) +# Rule PP.11: Butting Pplus and NCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case). +logger.info("Executing rule PP.11") +pp11_l1 = pp_11_in_dnwell.or(pp_11_out_dnwell) +pp11_l1.output("PP.11", "PP.11 : Butting Pplus and NCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case).") +pp11_l1.forget + +pp_11_in_dnwell.forget + +pp_11_out_dnwell.forget + +# Rule PP.12: Overlap with N-channel Poly2 gate extension is forbidden within 0.32um of N-channel gate. +logger.info("Executing rule PP.12") +pp12_l1 = pplus.interacting(pplus.edges.separation(ngate.edges.and(ncomp.edges), 0.32.um, euclidian).polygons(0.001)) +pp12_l1.output("PP.12", "PP.12 : Overlap with N-channel Poly2 gate extension is forbidden within 0.32um of N-channel gate.") +pp12_l1.forget + +#================================================ +#----------------------SAB----------------------- +#================================================ + +# Rule SB.1: min. sab width is 0.42µm +logger.info("Executing rule SB.1") +sb1_l1 = sab.width(0.42.um, euclidian).polygons(0.001) +sb1_l1.output("SB.1", "SB.1 : min. sab width : 0.42µm") +sb1_l1.forget + +# Rule SB.2: min. sab spacing is 0.42µm +logger.info("Executing rule SB.2") +sb2_l1 = sab.outside(otp_mk).space(0.42.um, euclidian).polygons(0.001) +sb2_l1.output("SB.2", "SB.2 : min. sab spacing : 0.42µm") +sb2_l1.forget + +# Rule SB.3: Space from salicide block to unrelated COMP. is 0.22µm +logger.info("Executing rule SB.3") +sb3_l1 = sab.outside(comp).outside(otp_mk).separation(comp.outside(sab), 0.22.um, euclidian).polygons(0.001) +sb3_l1.output("SB.3", "SB.3 : Space from salicide block to unrelated COMP. : 0.22µm") +sb3_l1.forget + +# Rule SB.4: Space from salicide block to contact. +logger.info("Executing rule SB.4") +sb4_l1 = sab.outside(otp_mk).separation(contact, 0.15.um, euclidian).polygons(0.001).or(sab.outside(otp_mk).and(contact)) +sb4_l1.output("SB.4", "SB.4 : Space from salicide block to contact.") +sb4_l1.forget + +# Rule SB.5a: Space from salicide block to unrelated Poly2 on field. is 0.3µm +logger.info("Executing rule SB.5a") +sb5a_l1 = sab.outside(poly2.not(comp)).outside(otp_mk).separation(poly2.not(comp).outside(sab), 0.3.um, euclidian).polygons(0.001) +sb5a_l1.output("SB.5a", "SB.5a : Space from salicide block to unrelated Poly2 on field. : 0.3µm") +sb5a_l1.forget + +# Rule SB.5b: Space from salicide block to unrelated Poly2 on COMP. is 0.28µm +logger.info("Executing rule SB.5b") +sb5b_l1 = sab.outside(tgate).outside(otp_mk).separation(tgate.outside(sab), 0.28.um, euclidian).polygons(0.001) +sb5b_l1.output("SB.5b", "SB.5b : Space from salicide block to unrelated Poly2 on COMP. : 0.28µm") +sb5b_l1.forget + +# Rule SB.6: Salicide block extension beyond related COMP. is 0.22µm +logger.info("Executing rule SB.6") +sb6_l1 = sab.enclosing(comp, 0.22.um, euclidian).polygons(0.001) +sb6_l1.output("SB.6", "SB.6 : Salicide block extension beyond related COMP. : 0.22µm") +sb6_l1.forget + +# Rule SB.7: COMP extension beyond related salicide block. is 0.22µm +logger.info("Executing rule SB.7") +sb7_l1 = comp.enclosing(sab, 0.22.um, euclidian).polygons +sb7_l1.output("SB.7", "SB.7 : COMP extension beyond related salicide block. : 0.22µm") +sb7_l1.forget + +# Rule SB.8: Non-salicided contacts are forbidden. +logger.info("Executing rule SB.8") +sb8_l1 = contact.inside(sab) +sb8_l1.output("SB.8", "SB.8 : Non-salicided contacts are forbidden.") +sb8_l1.forget + +# Rule SB.9: Salicide block extension beyond unsalicided Poly2. is 0.22µm +logger.info("Executing rule SB.9") +sb9_l1 = sab.outside(otp_mk).enclosing(poly2.and(sab), 0.22.um, euclidian).polygons +sb9_l1.output("SB.9", "SB.9 : Salicide block extension beyond unsalicided Poly2. : 0.22µm") +sb9_l1.forget + +# Rule SB.10: Poly2 extension beyond related salicide block. is 0.22µm +logger.info("Executing rule SB.10") +sb10_l1 = poly2.enclosing(sab, 0.22.um, euclidian).polygons(0.001) +sb10_l1.output("SB.10", "SB.10 : Poly2 extension beyond related salicide block. : 0.22µm") +sb10_l1.forget + +# Rule SB.11: Overlap with COMP. is 0.22µm +logger.info("Executing rule SB.11") +sb11_l1 = sab.outside(otp_mk).overlap(comp, 0.22.um, euclidian).polygons +sb11_l1.output("SB.11", "SB.11 : Overlap with COMP. : 0.22µm") +sb11_l1.forget + +# Rule SB.12: Overlap with Poly2 outside ESD_MK. is 0.22µm +logger.info("Executing rule SB.12") +sb12_l1 = sab.outside(otp_mk).outside(esd_mk).overlap(poly2.outside(otp_mk).outside(esd_mk), 0.22.um, euclidian).polygons +sb12_l1.output("SB.12", "SB.12 : Overlap with Poly2 outside ESD_MK. : 0.22µm") +sb12_l1.forget + +# Rule SB.13: Min. area (um2). is 2µm² +logger.info("Executing rule SB.13") +sb13_l1 = sab.outside(otp_mk).with_area(nil, 2.um) +sb13_l1.output("SB.13", "SB.13 : Min. area (um2). : 2µm²") +sb13_l1.forget + +# Rule SB.14a: Space from unsalicided Nplus Poly2 to unsalicided Pplus Poly2. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at unsalicided Pplus Poly2 corners). is 0.56µm +logger.info("Executing rule SB.14a") +sb14a_l1 = poly2.and(nplus).and(sab).separation(poly2.and(pplus).and(sab), 0.56.um, square).polygons +sb14a_l1.output("SB.14a", "SB.14a : Space from unsalicided Nplus Poly2 to unsalicided Pplus Poly2. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at unsalicided Pplus Poly2 corners). : 0.56µm") +sb14a_l1.forget + +# Rule SB.14b: Space from unsalicided Nplus Poly2 to P-channel gate. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at P-channel gate corners). is 0.56µm +logger.info("Executing rule SB.14b") +sb14b_l1 = poly2.and(nplus).and(sab).separation(pgate, 0.56.um, square).polygons +sb14b_l1.output("SB.14b", "SB.14b : Space from unsalicided Nplus Poly2 to P-channel gate. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at P-channel gate corners). : 0.56µm") +sb14b_l1.forget + +# Rule SB.15a: Space from unsalicided Poly2 to unrelated Nplus/Pplus. is 0.18µm +logger.info("Executing rule SB.15a") +sb15a_l1 = poly2.and(sab).separation(nplus.or(pplus), 0.18.um, euclidian).polygons(0.001) +sb15a_l1.output("SB.15a", "SB.15a : Space from unsalicided Poly2 to unrelated Nplus/Pplus. : 0.18µm") +sb15a_l1.forget + +sb_15b_1 = poly2.interacting(nplus.or(pplus)).and(sab).edges.not(poly2.edges.and(sab)).separation(nplus.or(pplus).edges, 0.32.um, projection).polygons(0.001) +sb_15b_2 = poly2.interacting(nplus.or(pplus)).and(sab).separation(nplus.or(pplus), 0.32.um, projection).polygons(0.001) +# Rule SB.15b: Space from unsalicided Poly2 to unrelated Nplus/Pplus along Poly2 line. is 0.32µm +logger.info("Executing rule SB.15b") +sb15b_l1 = sb_15b_1.and(sb_15b_2).outside(otp_mk) +sb15b_l1.output("SB.15b", "SB.15b : Space from unsalicided Poly2 to unrelated Nplus/Pplus along Poly2 line. : 0.32µm") +sb15b_l1.forget + +sb_15b_1.forget + +sb_15b_2.forget + +# Rule SB.16: SAB layer cannot exist on 3.3V and 5V/6V CMOS transistors' Poly and COMP area of the core circuit (Excluding the transistors used for ESD purpose). It can only exist on CMOS transistors marked by LVS_IO, OTP_MK, ESD_MK layers. +logger.info("Executing rule SB.16") +sb16_l1 = sab.outside(otp_mk).outside(otp_mk.or(lvs_io).or(esd_mk)).not_outside(ngate.or(pgate.and(nwell))) +sb16_l1.output("SB.16", "SB.16 : SAB layer cannot exist on 3.3V and 5V/6V CMOS transistors' Poly and COMP area of the core circuit (Excluding the transistors used for ESD purpose). It can only exist on CMOS transistors marked by LVS_IO, OTP_MK, ESD_MK layers.") +sb16_l1.forget + +#================================================ +#----------------------ESD----------------------- +#================================================ + +# Rule ESD.1: Minimum width of an ESD implant area. is 0.6µm +logger.info("Executing rule ESD.1") +esd1_l1 = esd.width(0.6.um, euclidian).polygons(0.001) +esd1_l1.output("ESD.1", "ESD.1 : Minimum width of an ESD implant area. : 0.6µm") +esd1_l1.forget + +# Rule ESD.2: Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). is 0.6µm +logger.info("Executing rule ESD.2") +esd2_l1 = esd.space(0.6.um, euclidian).polygons(0.001) +esd2_l1.output("ESD.2", "ESD.2 : Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). : 0.6µm") +esd2_l1.forget + +# Rule ESD.3a: Minimum space to NCOMP. is 0.6µm +logger.info("Executing rule ESD.3a") +esd3a_l1 = esd.separation(ncomp, 0.6.um, euclidian).polygons(0.001) +esd3a_l1.output("ESD.3a", "ESD.3a : Minimum space to NCOMP. : 0.6µm") +esd3a_l1.forget + +# Rule ESD.3b: Min/max space to a butted PCOMP. +logger.info("Executing rule ESD.3b") +esd3b_l1 = esd.not_outside(pcomp) +esd3b_l1.output("ESD.3b", "ESD.3b : Min/max space to a butted PCOMP.") +esd3b_l1.forget + +# Rule ESD.4a: Extension beyond NCOMP. is 0.24µm +logger.info("Executing rule ESD.4a") +esd4a_l1 = esd.edges.not_interacting(pcomp).enclosing(ncomp.edges, 0.24.um, euclidian).polygons(0.001) +esd4a_l1.output("ESD.4a", "ESD.4a : Extension beyond NCOMP. : 0.24µm") +esd4a_l1.forget + +# Rule ESD.4b: Minimum overlap of an ESD implant edge to a COMP. is 0.45µm +logger.info("Executing rule ESD.4b") +esd4b_l1 = esd.overlap(comp, 0.45.um, euclidian).polygons(0.001) +esd4b_l1.output("ESD.4b", "ESD.4b : Minimum overlap of an ESD implant edge to a COMP. : 0.45µm") +esd4b_l1.forget + +# Rule ESD.5a: Minimum ESD area (um2). is 0.49µm² +logger.info("Executing rule ESD.5a") +esd5a_l1 = esd.with_area(nil, 0.49.um) +esd5a_l1.output("ESD.5a", "ESD.5a : Minimum ESD area (um2). : 0.49µm²") +esd5a_l1.forget + +# Rule ESD.5b: Minimum field area enclosed by ESD implant (um2). is 0.49µm² +logger.info("Executing rule ESD.5b") +esd5b_l1 = esd.holes.with_area(nil, 0.49.um) +esd5b_l1.output("ESD.5b", "ESD.5b : Minimum field area enclosed by ESD implant (um2). : 0.49µm²") +esd5b_l1.forget + +# Rule ESD.6: Extension perpendicular to Poly2 gate. is 0.45µm +logger.info("Executing rule ESD.6") +esd6_l1 = esd.edges.enclosing(poly2.edges.interacting(tgate.edges), 0.45.um, projection).polygons(0.001) +esd6_l1.output("ESD.6", "ESD.6 : Extension perpendicular to Poly2 gate. : 0.45µm") +esd6_l1.forget + +# Rule ESD.7: No ESD implant inside PCOMP. +logger.info("Executing rule ESD.7") +esd7_l1 = esd.not_outside(pcomp) +esd7_l1.output("ESD.7", "ESD.7 : No ESD implant inside PCOMP.") +esd7_l1.forget + +# Rule ESD.8: Minimum space to Nplus/Pplus. is 0.3µm +logger.info("Executing rule ESD.8") +esd8_l1 = esd.separation(nplus.or(pplus), 0.3.um).polygons +esd8_l1.output("ESD.8", "ESD.8 : Minimum space to Nplus/Pplus. : 0.3µm") +esd8_l1.forget + +# Rule ESD.pl: Minimum gate length of 5V/6V gate NMOS. is 0.8µm +logger.info("Executing rule ESD.pl") +esdpl_l1 = poly2.interacting(esd).edges.and(tgate.edges).width(0.8.um, euclidian).polygons(0.001).overlapping(dualgate) +esdpl_l1.output("ESD.pl", "ESD.pl : Minimum gate length of 5V/6V gate NMOS. : 0.8µm") +esdpl_l1.forget + +# Rule ESD.9: ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices). +logger.info("Executing rule ESD.9") +esd9_l1 = esd.not_inside(dualgate) +esd9_l1.output("ESD.9", "ESD.9 : ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices).") +esd9_l1.forget + +# Rule ESD.10: LVS_IO shall be drawn covering I/O MOS active area by minimum overlap. +logger.info("Executing rule ESD.10") +esd10_l1 = comp.and(esd).not_outside(lvs_io).not(lvs_io) +esd10_l1.output("ESD.10", "ESD.10 : LVS_IO shall be drawn covering I/O MOS active area by minimum overlap.") +esd10_l1.forget + +#================================================ +#--------------------CONTACT--------------------- +#================================================ + +# Rule CO.1: Min/max contact size. is 0.22µm +logger.info("Executing rule CO.1") +co1_l1 = contact.edges.without_length(0.22.um).extended(0, 0, 0.001, 0.001) +co1_l1.output("CO.1", "CO.1 : Min/max contact size. : 0.22µm") +co1_l1.forget + +# Rule CO.2a: min. contact spacing is 0.25µm +logger.info("Executing rule CO.2a") +co2a_l1 = contact.space(0.25.um, euclidian).polygons(0.001) +co2a_l1.output("CO.2a", "CO.2a : min. contact spacing : 0.25µm") +co2a_l1.forget + +merged_co1 = contact.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.63.um , nil).extents.inside(metal1) +contact_mask = merged_co1.size(1).not(contact).with_holes(16, nil) +selected_co1 = contact.interacting(contact_mask) +# Rule CO.2b: Space in 4x4 or larger contact array. is 0.28µm +logger.info("Executing rule CO.2b") +co2b_l1 = selected_co1.space(0.28.um, euclidian).polygons(0.001) +co2b_l1.output("CO.2b", "CO.2b : Space in 4x4 or larger contact array. : 0.28µm") +co2b_l1.forget + +merged_co1.forget + +contact_mask.forget + +selected_co1.forget + +# Rule CO.3: Poly2 overlap of contact. is 0.07µm +logger.info("Executing rule CO.3") +co3_l1 = poly2.enclosing(contact.outside(sramcore), 0.07.um, euclidian).polygons(0.001) +co3_l2 = contact.outside(sramcore).not_outside(poly2).not(poly2) +co3_l = co3_l1.or(co3_l2) +co3_l.output("CO.3", "CO.3 : Poly2 overlap of contact. : 0.07µm") +co3_l1.forget +co3_l2.forget +co3_l.forget + +# Rule CO.4: COMP overlap of contact. is 0.07µm +logger.info("Executing rule CO.4") +co4_l1 = comp.not(mvsd).not(mvpsd).enclosing(contact.outside(sramcore), 0.07.um, euclidian).polygons(0.001) +co4_l2 = contact.outside(sramcore).not_outside(comp.not(mvsd).not(mvpsd)).not(comp.not(mvsd).not(mvpsd)) +co4_l = co4_l1.or(co4_l2) +co4_l.output("CO.4", "CO.4 : COMP overlap of contact. : 0.07µm") +co4_l1.forget +co4_l2.forget +co4_l.forget + +co_5a_ncomp_butted = ncomp.not(pplus).interacting(pcomp.not(nplus)).not_overlapping(pcomp.not(nplus)) +# Rule CO.5a: Nplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). is 0.1µm +logger.info("Executing rule CO.5a") +co5a_l1 = co_5a_ncomp_butted.enclosing(contact, 0.1.um, euclidian).polygons(0.001) +co5a_l2 = contact.not_outside(co_5a_ncomp_butted).not(co_5a_ncomp_butted) +co5a_l = co5a_l1.or(co5a_l2) +co5a_l.output("CO.5a", "CO.5a : Nplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm") +co5a_l1.forget +co5a_l2.forget +co5a_l.forget + +co_5a_ncomp_butted.forget + +co_5b_pcomp_butted = pcomp.not(nplus).interacting(ncomp.not(pplus)).not_overlapping(ncomp.not(pplus)) +# Rule CO.5b: Pplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). is 0.1µm +logger.info("Executing rule CO.5b") +co5b_l1 = co_5b_pcomp_butted.enclosing(contact, 0.1.um, euclidian).polygons(0.001) +co5b_l2 = contact.not_outside(co_5b_pcomp_butted).not(co_5b_pcomp_butted) +co5b_l = co5b_l1.or(co5b_l2) +co5b_l.output("CO.5b", "CO.5b : Pplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm") +co5b_l1.forget +co5b_l2.forget +co5b_l.forget + +co_5b_pcomp_butted.forget + +# Rule CO.6: Metal1 overlap of contact. +logger.info("Executing rule CO.6") +co6_l1 = metal1.enclosing(contact, 0.005.um, euclidian).polygons(0.001).or(contact.not_inside(metal1).not(metal1)) +co6_l1.output("CO.6", "CO.6 : Metal1 overlap of contact.") +co6_l1.forget + +cop6a_cond = metal1.drc( width <= 0.34.um).with_length(0.24.um,nil,both) +cop6a_eol = metal1.edges.with_length(nil, 0.34.um).interacting(cop6a_cond.first_edges).interacting(cop6a_cond.second_edges).not(cop6a_cond.first_edges).not(cop6a_cond.second_edges) +# Rule CO.6a: (i) Metal1 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule CO.6a") +co6a_l1 = cop6a_eol.enclosing(contact.edges,0.06.um, projection).polygons(0.001) +co6a_l1.output("CO.6a", "CO.6a : (i) Metal1 (< 0.34um) end-of-line overlap. : 0.06µm") +co6a_l1.forget + +cop6a_cond.forget + +cop6a_eol.forget + +co_6b_1 = contact.edges.interacting(contact.drc(enclosed(metal1, projection) < 0.04.um).edges.centers(0, 0.5)) +co_6b_2 = contact.edges.interacting(contact.drc(0.04.um <= enclosed(metal1, projection) < 0.06.um).centers(0, 0.5)) +co_6b_3 = co_6b_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule CO.6b: (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap is 0.06µm +logger.info("Executing rule CO.6b") +co6b_l1 = co_6b_2.not_in(co_6b_1).interacting(co_6b_1).or(co_6b_1.interacting(co_6b_3)).not(sramcore).enclosed(metal1.outside(sramcore).edges, 0.06.um).polygons(0.001) +co6b_l1.output("CO.6b", "CO.6b : (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap : 0.06µm") +co6b_l1.forget + +co_6b_1.forget + +co_6b_2.forget + +co_6b_3.forget + +# rule CO.6c is not a DRC check + +# Rule CO.7: Space from COMP contact to Poly2 on COMP. is 0.15µm +logger.info("Executing rule CO.7") +co7_l1 = contact.not_outside(comp).not(otp_mk).separation(tgate.not(otp_mk), 0.15.um, euclidian).polygons(0.001) +co7_l1.output("CO.7", "CO.7 : Space from COMP contact to Poly2 on COMP. : 0.15µm") +co7_l1.forget + +# Rule CO.8: Space from Poly2 contact to COMP. is 0.17µm +logger.info("Executing rule CO.8") +co8_l1 = contact.not_outside(poly2).separation(comp, 0.17.um, euclidian).polygons(0.001) +co8_l1.output("CO.8", "CO.8 : Space from Poly2 contact to COMP. : 0.17µm") +co8_l1.forget + +# Rule CO.9: Contact on NCOMP to PCOMP butting edge is forbidden (contact must not straddle butting edge). +logger.info("Executing rule CO.9") +co9_l1 = contact.interacting(ncomp.edges.and(pcomp.edges)) +co9_l1.output("CO.9", "CO.9 : Contact on NCOMP to PCOMP butting edge is forbidden (contact must not straddle butting edge).") +co9_l1.forget + +# Rule CO.10: Contact on Poly2 gate over COMP is forbidden. +logger.info("Executing rule CO.10") +co10_l1 = contact.not_outside(tgate) +co10_l1.output("CO.10", "CO.10 : Contact on Poly2 gate over COMP is forbidden.") +co10_l1.forget + +# Rule CO.11: Contact on field oxide is forbidden. +logger.info("Executing rule CO.11") +co11_l1 = contact.not_inside(comp.or(poly2)) +co11_l1.output("CO.11", "CO.11 : Contact on field oxide is forbidden.") +co11_l1.forget + +end #FEOL + +if BEOL +logger.info("BEOL section") + +#================================================ +#---------------------METAL1--------------------- +#================================================ + +# Rule M1.1: min. metal1 width is 0.23µm +logger.info("Executing rule M1.1") +m11_l1 = metal1.not(sramcore).width(0.23.um, euclidian).polygons(0.001) +m11_l1.output("M1.1", "M1.1 : min. metal1 width : 0.23µm") +m11_l1.forget + +# Rule M1.2a: min. metal1 spacing is 0.23µm +logger.info("Executing rule M1.2a") +m12a_l1 = metal1.space(0.23.um, euclidian).polygons(0.001) +m12a_l1.output("M1.2a", "M1.2a : min. metal1 spacing : 0.23µm") +m12a_l1.forget + +# Rule M1.2b: Space to wide Metal1 (length & width > 10um) is 0.3µm +logger.info("Executing rule M1.2b") +m12b_l1 = metal1.separation(metal1.not_interacting(metal1.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) +m12b_l1.output("M1.2b", "M1.2b : Space to wide Metal1 (length & width > 10um) : 0.3µm") +m12b_l1.forget + +# Rule M1.3: Minimum Metal1 area is 0.1444µm² +logger.info("Executing rule M1.3") +m13_l1 = metal1.with_area(nil, 0.1444.um) +m13_l1.output("M1.3", "M1.3 : Minimum Metal1 area : 0.1444µm²") +m13_l1.forget + +#================================================ +#---------------------METAL2--------------------- +#================================================ + +# Rule M2.1: min. metal2 width is 0.28µm +logger.info("Executing rule M2.1") +m21_l1 = metal2.width(0.28.um, euclidian).polygons(0.001) +m21_l1.output("M2.1", "M2.1 : min. metal2 width : 0.28µm") +m21_l1.forget + +# Rule M2.2a: min. metal2 spacing is 0.28µm +logger.info("Executing rule M2.2a") +m22a_l1 = metal2.space(0.28.um, euclidian).polygons(0.001) +m22a_l1.output("M2.2a", "M2.2a : min. metal2 spacing : 0.28µm") +m22a_l1.forget + +# Rule M2.2b: Space to wide Metal2 (length & width > 10um) is 0.3µm +logger.info("Executing rule M2.2b") +m22b_l1 = metal2.separation(metal2.not_interacting(metal2.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) +m22b_l1.output("M2.2b", "M2.2b : Space to wide Metal2 (length & width > 10um) : 0.3µm") +m22b_l1.forget + +# Rule M2.3: Minimum metal2 area is 0.1444µm² +logger.info("Executing rule M2.3") +m23_l1 = metal2.with_area(nil, 0.1444.um) +m23_l1.output("M2.3", "M2.3 : Minimum metal2 area : 0.1444µm²") +m23_l1.forget + +#================================================ +#---------------------METAL3--------------------- +#================================================ + +# Rule M3.1: min. metal3 width is 0.28µm +logger.info("Executing rule M3.1") +m31_l1 = metal3.width(0.28.um, euclidian).polygons(0.001) +m31_l1.output("M3.1", "M3.1 : min. metal3 width : 0.28µm") +m31_l1.forget + +# Rule M3.2a: min. metal3 spacing is 0.28µm +logger.info("Executing rule M3.2a") +m32a_l1 = metal3.space(0.28.um, euclidian).polygons(0.001) +m32a_l1.output("M3.2a", "M3.2a : min. metal3 spacing : 0.28µm") +m32a_l1.forget + +# Rule M3.2b: Space to wide Metal3 (length & width > 10um) is 0.3µm +logger.info("Executing rule M3.2b") +m32b_l1 = metal3.separation(metal3.not_interacting(metal3.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) +m32b_l1.output("M3.2b", "M3.2b : Space to wide Metal3 (length & width > 10um) : 0.3µm") +m32b_l1.forget + +# Rule M3.3: Minimum metal3 area is 0.1444µm² +logger.info("Executing rule M3.3") +m33_l1 = metal3.with_area(nil, 0.1444.um) +m33_l1.output("M3.3", "M3.3 : Minimum metal3 area : 0.1444µm²") +m33_l1.forget + +#================================================ +#---------------------METAL4--------------------- +#================================================ + +# Rule M4.1: min. metal4 width is 0.28µm +logger.info("Executing rule M4.1") +m41_l1 = metal4.width(0.28.um, euclidian).polygons(0.001) +m41_l1.output("M4.1", "M4.1 : min. metal4 width : 0.28µm") +m41_l1.forget + +# Rule M4.2a: min. metal4 spacing is 0.28µm +logger.info("Executing rule M4.2a") +m42a_l1 = metal4.space(0.28.um, euclidian).polygons(0.001) +m42a_l1.output("M4.2a", "M4.2a : min. metal4 spacing : 0.28µm") +m42a_l1.forget + +# Rule M4.2b: Space to wide Metal4 (length & width > 10um) is 0.3µm +logger.info("Executing rule M4.2b") +m42b_l1 = metal4.separation(metal4.not_interacting(metal4.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) +m42b_l1.output("M4.2b", "M4.2b : Space to wide Metal4 (length & width > 10um) : 0.3µm") +m42b_l1.forget + +# Rule M4.3: Minimum metal4 area is 0.1444µm² +logger.info("Executing rule M4.3") +m43_l1 = metal4.with_area(nil, 0.1444.um) +m43_l1.output("M4.3", "M4.3 : Minimum metal4 area : 0.1444µm²") +m43_l1.forget + +#================================================ +#---------------------METAL5--------------------- +#================================================ + +# Rule M5.1: min. metal5 width is 0.28µm +logger.info("Executing rule M5.1") +m51_l1 = metal5.width(0.28.um, euclidian).polygons(0.001) +m51_l1.output("M5.1", "M5.1 : min. metal5 width : 0.28µm") +m51_l1.forget + +# Rule M5.2a: min. metal5 spacing is 0.28µm +logger.info("Executing rule M5.2a") +m52a_l1 = metal5.space(0.28.um, euclidian).polygons(0.001) +m52a_l1.output("M5.2a", "M5.2a : min. metal5 spacing : 0.28µm") +m52a_l1.forget + +# Rule M5.2b: Space to wide Metal5 (length & width > 10um) is 0.3µm +logger.info("Executing rule M5.2b") +m52b_l1 = metal5.separation(metal5.not_interacting(metal5.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) +m52b_l1.output("M5.2b", "M5.2b : Space to wide Metal5 (length & width > 10um) : 0.3µm") +m52b_l1.forget + +# Rule M5.3: Minimum metal5 area is 0.1444µm² +logger.info("Executing rule M5.3") +m53_l1 = metal5.with_area(nil, 0.1444.um) +m53_l1.output("M5.3", "M5.3 : Minimum metal5 area : 0.1444µm²") +m53_l1.forget + +#================================================ +#----------------------VIA1---------------------- +#================================================ + +# Rule V1.1: Min/max Via1 size . is 0.26µm +logger.info("Executing rule V1.1") +v11_l1 = via1.edges.without_length(0.26.um).extended(0, 0, 0.001, 0.001) +v11_l1.output("V1.1", "V1.1 : Min/max Via1 size . : 0.26µm") +v11_l1.forget + +# Rule V1.2a: min. via1 spacing is 0.26µm +logger.info("Executing rule V1.2a") +v12a_l1 = via1.space(0.26.um, euclidian).polygons(0.001) +v12a_l1.output("V1.2a", "V1.2a : min. via1 spacing : 0.26µm") +v12a_l1.forget + +merged_via1 = via1.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal1) +via1_mask = merged_via1.size(1).not(via1).with_holes(16, nil) +selected_via1 = via1.interacting(via1_mask) +# Rule V1.2b: Via1 Space in 4x4 or larger via1 array is 0.36µm +logger.info("Executing rule V1.2b") +v12b_l1 = selected_via1.space(0.36.um, euclidian).polygons(0.001) +v12b_l1.output("V1.2b", "V1.2b : Via1 Space in 4x4 or larger via1 array : 0.36µm") +v12b_l1.forget + +merged_via1.forget + +via1_mask.forget + +selected_via1.forget + +# Rule V1.3a: metal-1 overlap of via1. +logger.info("Executing rule V1.3a") +v13a_l1 = via1.not_inside(metal1) +v13a_l1.output("V1.3a", "V1.3a : metal-1 overlap of via1.") +v13a_l1.forget + +# rule V1.3b is not a DRC check + +v1p3c_cond = metal1.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v1p3c_eol = metal1.edges.with_length(nil, 0.34.um).interacting(v1p3c_cond.first_edges).interacting(v1p3c_cond.second_edges).not(v1p3c_cond.first_edges).not(v1p3c_cond.second_edges) +# Rule V1.3c: metal-1 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V1.3c") +v13c_l1 = v1p3c_eol.enclosing(via1.edges,0.06.um, projection).polygons(0.001) +v13c_l1.output("V1.3c", "V1.3c : metal-1 (< 0.34um) end-of-line overlap. : 0.06µm") +v13c_l1.forget + +v1p3c_cond.forget + +v1p3c_eol.forget + +v1_3d_1 = via1.edges.interacting(via1.drc(enclosed(metal1, projection) < 0.04.um).edges.centers(0, 0.5)) +v1_3d_2 = via1.edges.interacting(via1.drc(0.04.um <= enclosed(metal1, projection) < 0.06.um).centers(0, 0.5)) +v1_3d_3 = v1_3d_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V1.3d: If metal-1 overlap via1 by < 0.04um on one side, adjacent metal-1 edges overlap. is 0.06µm +logger.info("Executing rule V1.3d") +v13d_l1 = v1_3d_2.not_in(v1_3d_1).interacting(v1_3d_1).or(v1_3d_1.interacting(v1_3d_3)).enclosed(metal1.edges, 0.06.um).polygons(0.001) +v13d_l1.output("V1.3d", "V1.3d : If metal-1 overlap via1 by < 0.04um on one side, adjacent metal-1 edges overlap. : 0.06µm") +v13d_l1.forget + +v1_3d_1.forget + +v1_3d_2.forget + +v1_3d_3.forget + +# rule V1.3e is not a DRC check + +# Rule V1.4a: metal-2 overlap of via1. +logger.info("Executing rule V1.4a") +v14a_l1 = metal2.enclosing(via1, 0.01.um, euclidian).polygons(0.001).or(via1.not_inside(metal2).not(metal2)) +v14a_l1.output("V1.4a", "V1.4a : metal-2 overlap of via1.") +v14a_l1.forget + +v1p4b_cond = metal2.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v1p4b_eol = metal2.edges.with_length(nil, 0.34.um).interacting(v1p4b_cond.first_edges).interacting(v1p4b_cond.second_edges).not(v1p4b_cond.first_edges).not(v1p4b_cond.second_edges) +# Rule V1.4b: metal-2 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V1.4b") +v14b_l1 = v1p4b_eol.enclosing(via1.edges,0.06.um, projection).polygons(0.001) +v14b_l1.output("V1.4b", "V1.4b : metal-2 (< 0.34um) end-of-line overlap. : 0.06µm") +v14b_l1.forget + +v1p4b_cond.forget + +v1p4b_eol.forget + +v1_4c_1 = via1.edges.interacting(via1.drc(enclosed(metal2, projection) < 0.04.um).edges.centers(0, 0.5)) +v1_4c_2 = via1.edges.interacting(via1.drc(0.04.um <= enclosed(metal2, projection) < 0.06.um).centers(0, 0.5)) +v1_4c_3 = v1_4c_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V1.4c: If metal-2 overlap via1 by < 0.04um on one side, adjacent metal-2 edges overlap. is 0.06µm +logger.info("Executing rule V1.4c") +v14c_l1 = v1_4c_2.not_in(v1_4c_1).interacting(v1_4c_1).or(v1_4c_1.interacting(v1_4c_3)).enclosed(metal2.edges, 0.06.um).polygons(0.001) +v14c_l1.output("V1.4c", "V1.4c : If metal-2 overlap via1 by < 0.04um on one side, adjacent metal-2 edges overlap. : 0.06µm") +v14c_l1.forget + +v1_4c_1.forget + +v1_4c_2.forget + +v1_4c_3.forget + +# rule V1.4d is not a DRC check + +# rule V1.5 is not a DRC check + +#================================================ +#----------------------VIA2---------------------- +#================================================ + +# Rule V2.1: Min/max Via2 size . is 0.26µm +logger.info("Executing rule V2.1") +v21_l1 = via2.edges.without_length(0.26.um).extended(0, 0, 0.001, 0.001) +v21_l1.output("V2.1", "V2.1 : Min/max Via2 size . : 0.26µm") +v21_l1.forget + +# Rule V2.2a: min. via2 spacing is 0.26µm +logger.info("Executing rule V2.2a") +v22a_l1 = via2.space(0.26.um, euclidian).polygons(0.001) +v22a_l1.output("V2.2a", "V2.2a : min. via2 spacing : 0.26µm") +v22a_l1.forget + +merged_via2 = via2.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal2) +via2_mask = merged_via2.size(1).not(via2).with_holes(16, nil) +selected_via2 = via2.interacting(via2_mask) +# Rule V2.2b: Via2 Space in 4x4 or larger via2 array is 0.36µm +logger.info("Executing rule V2.2b") +v22b_l1 = selected_via2.space(0.36.um, euclidian).polygons(0.001) +v22b_l1.output("V2.2b", "V2.2b : Via2 Space in 4x4 or larger via2 array : 0.36µm") +v22b_l1.forget + +merged_via2.forget + +via2_mask.forget + +selected_via2.forget + +# rule V2.3a is not a DRC check + +# Rule V2.3b: metal2 overlap of via2. +logger.info("Executing rule V2.3b") +v23b_l1 = metal2.enclosing(via2, 0.01.um, euclidian).polygons(0.001).or(via2.not_inside(metal2).not(metal2)) +v23b_l1.output("V2.3b", "V2.3b : metal2 overlap of via2.") +v23b_l1.forget + +v2p3c_cond = metal2.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v2p3c_eol = metal2.edges.with_length(nil, 0.34.um).interacting(v2p3c_cond.first_edges).interacting(v2p3c_cond.second_edges).not(v2p3c_cond.first_edges).not(v2p3c_cond.second_edges) +# Rule V2.3c: metal2 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V2.3c") +v23c_l1 = v2p3c_eol.enclosing(via2.edges,0.06.um, projection).polygons(0.001) +v23c_l1.output("V2.3c", "V2.3c : metal2 (< 0.34um) end-of-line overlap. : 0.06µm") +v23c_l1.forget + +v2p3c_cond.forget + +v2p3c_eol.forget + +v2_3d_1 = via2.edges.interacting(via2.drc(enclosed(metal2, projection) < 0.04.um).edges.centers(0, 0.5)) +v2_3d_2 = via2.edges.interacting(via2.drc(0.04.um <= enclosed(metal2, projection) < 0.06.um).centers(0, 0.5)) +v2_3d_3 = v2_3d_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V2.3d: If metal2 overlap via2 by < 0.04um on one side, adjacent metal2 edges overlap. is 0.06µm +logger.info("Executing rule V2.3d") +v23d_l1 = v2_3d_2.not_in(v2_3d_1).interacting(v2_3d_1).or(v2_3d_1.interacting(v2_3d_3)).enclosed(metal2.edges, 0.06.um).polygons(0.001) +v23d_l1.output("V2.3d", "V2.3d : If metal2 overlap via2 by < 0.04um on one side, adjacent metal2 edges overlap. : 0.06µm") +v23d_l1.forget + +v2_3d_1.forget + +v2_3d_2.forget + +v2_3d_3.forget + +# rule V2.3e is not a DRC check + +# Rule V2.4a: metal3 overlap of via2. +logger.info("Executing rule V2.4a") +v24a_l1 = metal3.enclosing(via2, 0.01.um, euclidian).polygons(0.001).or(via2.not_inside(metal3).not(metal3)) +v24a_l1.output("V2.4a", "V2.4a : metal3 overlap of via2.") +v24a_l1.forget + +v2p4b_cond = metal3.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v2p4b_eol = metal3.edges.with_length(nil, 0.34.um).interacting(v2p4b_cond.first_edges).interacting(v2p4b_cond.second_edges).not(v2p4b_cond.first_edges).not(v2p4b_cond.second_edges) +# Rule V2.4b: metal3 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V2.4b") +v24b_l1 = v2p4b_eol.enclosing(via2.edges,0.06.um, projection).polygons(0.001) +v24b_l1.output("V2.4b", "V2.4b : metal3 (< 0.34um) end-of-line overlap. : 0.06µm") +v24b_l1.forget + +v2p4b_cond.forget + +v2p4b_eol.forget + +v2_4c_1 = via2.edges.interacting(via2.drc(enclosed(metal3, projection) < 0.04.um).edges.centers(0, 0.5)) +v2_4c_2 = via2.edges.interacting(via2.drc(0.04.um <= enclosed(metal3, projection) < 0.06.um).centers(0, 0.5)) +v2_4c_3 = v2_4c_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V2.4c: If metal3 overlap via2 by < 0.04um on one side, adjacent metal3 edges overlap. is 0.06µm +logger.info("Executing rule V2.4c") +v24c_l1 = v2_4c_2.not_in(v2_4c_1).interacting(v2_4c_1).or(v2_4c_1.interacting(v2_4c_3)).enclosed(metal3.edges, 0.06.um).polygons(0.001) +v24c_l1.output("V2.4c", "V2.4c : If metal3 overlap via2 by < 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm") +v24c_l1.forget + +v2_4c_1.forget + +v2_4c_2.forget + +v2_4c_3.forget + +# rule V2.4d is not a DRC check + +# rule V2.5 is not a DRC check + +#================================================ +#----------------------VIA3---------------------- +#================================================ + +# Rule V3.1: Min/max Via3 size . is 0.26µm +logger.info("Executing rule V3.1") +v31_l1 = via3.edges.without_length(0.26.um).extended(0, 0, 0.001, 0.001) +v31_l1.output("V3.1", "V3.1 : Min/max Via3 size . : 0.26µm") +v31_l1.forget + +# Rule V3.2a: min. via3 spacing is 0.26µm +logger.info("Executing rule V3.2a") +v32a_l1 = via3.space(0.26.um, euclidian).polygons(0.001) +v32a_l1.output("V3.2a", "V3.2a : min. via3 spacing : 0.26µm") +v32a_l1.forget + +merged_via3 = via3.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal3) +via3_mask = merged_via3.size(1).not(via3).with_holes(16, nil) +selected_via3 = via3.interacting(via3_mask) +# Rule V3.2b: Via3 Space in 4x4 or larger via3 array is 0.36µm +logger.info("Executing rule V3.2b") +v32b_l1 = selected_via3.space(0.36.um, euclidian).polygons(0.001) +v32b_l1.output("V3.2b", "V3.2b : Via3 Space in 4x4 or larger via3 array : 0.36µm") +v32b_l1.forget + +merged_via3.forget + +via3_mask.forget + +selected_via3.forget + +# rule V3.3a is not a DRC check + +# Rule V3.3b: metal3 overlap of via3. +logger.info("Executing rule V3.3b") +v33b_l1 = metal3.enclosing(via3, 0.01.um, euclidian).polygons(0.001).or(via3.not_inside(metal3).not(metal3)) +v33b_l1.output("V3.3b", "V3.3b : metal3 overlap of via3.") +v33b_l1.forget + +v3p3c_cond = metal3.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v3p3c_eol = metal3.edges.with_length(nil, 0.34.um).interacting(v3p3c_cond.first_edges).interacting(v3p3c_cond.second_edges).not(v3p3c_cond.first_edges).not(v3p3c_cond.second_edges) +# Rule V3.3c: metal3 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V3.3c") +v33c_l1 = v3p3c_eol.enclosing(via3.edges,0.06.um, projection).polygons(0.001) +v33c_l1.output("V3.3c", "V3.3c : metal3 (< 0.34um) end-of-line overlap. : 0.06µm") +v33c_l1.forget + +v3p3c_cond.forget + +v3p3c_eol.forget + +v3_3d_1 = via3.edges.interacting(via3.drc(enclosed(metal3, projection) < 0.04.um).edges.centers(0, 0.5)) +v3_3d_2 = via3.edges.interacting(via3.drc(0.04.um <= enclosed(metal3, projection) < 0.06.um).centers(0, 0.5)) +v3_3d_3 = v3_3d_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V3.3d: If metal3 overlap via3 by < 0.04um on one side, adjacent metal3 edges overlap. is 0.06µm +logger.info("Executing rule V3.3d") +v33d_l1 = v3_3d_2.not(v3_3d_1).interacting(v3_3d_1).or(v3_3d_1.interacting(v3_3d_3)).enclosed(metal3.edges, 0.06.um).polygons(0.001) +v33d_l1.output("V3.3d", "V3.3d : If metal3 overlap via3 by < 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm") +v33d_l1.forget + +v3_3d_1.forget + +v3_3d_2.forget + +v3_3d_3.forget + +# rule V3.3e is not a DRC check + +# Rule V3.4a: metal4 overlap of via3. +logger.info("Executing rule V3.4a") +v34a_l1 = metal4.enclosing(via3, 0.01.um, euclidian).polygons(0.001).or(via3.not_inside(metal4).not(metal4)) +v34a_l1.output("V3.4a", "V3.4a : metal4 overlap of via3.") +v34a_l1.forget + +v3p4b_cond = metal4.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v3p4b_eol = metal4.edges.with_length(nil, 0.34.um).interacting(v3p4b_cond.first_edges).interacting(v3p4b_cond.second_edges).not(v3p4b_cond.first_edges).not(v3p4b_cond.second_edges) +# Rule V3.4b: metal4 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V3.4b") +v34b_l1 = v3p4b_eol.enclosing(via3.edges,0.06.um, projection).polygons(0.001) +v34b_l1.output("V3.4b", "V3.4b : metal4 (< 0.34um) end-of-line overlap. : 0.06µm") +v34b_l1.forget + +v3p4b_cond.forget + +v3p4b_eol.forget + +v3_4c_1 = via3.edges.interacting(via3.drc(enclosed(metal4, projection) < 0.04.um).edges.centers(0, 0.5)) +v3_4c_2 = via3.edges.interacting(via3.drc(0.04.um <= enclosed(metal4, projection) < 0.06.um).centers(0, 0.5)) +v3_4c_3 = v3_4c_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V3.4c: If metal4 overlap via3 by < 0.04um on one side, adjacent metal4 edges overlap. is 0.06µm +logger.info("Executing rule V3.4c") +v34c_l1 = v3_4c_2.not_in(v3_4c_1).interacting(v3_4c_1).or(v3_4c_1.interacting(v3_4c_3)).enclosed(metal4.edges, 0.06.um).polygons(0.001) +v34c_l1.output("V3.4c", "V3.4c : If metal4 overlap via3 by < 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm") +v34c_l1.forget + +v3_4c_1.forget + +v3_4c_2.forget + +v3_4c_3.forget + +# rule V3.4d is not a DRC check + +# rule V3.5 is not a DRC check + +#================================================ +#----------------------VIA4---------------------- +#================================================ + +# Rule V4.1: Min/max Via4 size . is 0.26µm +logger.info("Executing rule V4.1") +v41_l1 = via4.edges.without_length(0.26.um).extended(0, 0, 0.001, 0.001) +v41_l1.output("V4.1", "V4.1 : Min/max Via4 size . : 0.26µm") +v41_l1.forget + +# Rule V4.2a: min. via4 spacing is 0.26µm +logger.info("Executing rule V4.2a") +v42a_l1 = via4.space(0.26.um, euclidian).polygons(0.001) +v42a_l1.output("V4.2a", "V4.2a : min. via4 spacing : 0.26µm") +v42a_l1.forget + +merged_via4 = via4.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal4) +via4_mask = merged_via4.size(1).not(via4).with_holes(16, nil) +selected_via4 = via4.interacting(via4_mask) +# Rule V4.2b: Via4 Space in 4x4 or larger Vian array is 0.36µm +logger.info("Executing rule V4.2b") +v42b_l1 = selected_via4.space(0.36.um, euclidian).polygons(0.001) +v42b_l1.output("V4.2b", "V4.2b : Via4 Space in 4x4 or larger Vian array : 0.36µm") +v42b_l1.forget + +merged_via4.forget + +via4_mask.forget + +selected_via4.forget + +# rule V4.3a is not a DRC check + +# Rule V4.3b: metal4 overlap of via4. +logger.info("Executing rule V4.3b") +v43b_l1 = metal4.enclosing(via4, 0.01.um, euclidian).polygons(0.001).or(via4.not_inside(metal4).not(metal4)) +v43b_l1.output("V4.3b", "V4.3b : metal4 overlap of via4.") +v43b_l1.forget + +v4p3c_cond = metal4.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v4p3c_eol = metal4.edges.with_length(nil, 0.34.um).interacting(v4p3c_cond.first_edges).interacting(v4p3c_cond.second_edges).not(v4p3c_cond.first_edges).not(v4p3c_cond.second_edges) +# Rule V4.3c: metal4 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V4.3c") +v43c_l1 = v4p3c_eol.enclosing(via4.edges,0.06.um, projection).polygons(0.001) +v43c_l1.output("V4.3c", "V4.3c : metal4 (< 0.34um) end-of-line overlap. : 0.06µm") +v43c_l1.forget + +v4p3c_cond.forget + +v4p3c_eol.forget + +v4_3d_1 = via4.edges.interacting(via4.drc(enclosed(metal4, projection) < 0.04.um).edges.centers(0, 0.5)) +v4_3d_2 = via4.edges.interacting(via4.drc(0.04.um <= enclosed(metal4, projection) < 0.06.um).centers(0, 0.5)) +v4_3d_3 = v4_3d_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V4.3d: If metal4 overlap Vian by < 0.04um on one side, adjacent metal4 edges overlap. is 0.06µm +logger.info("Executing rule V4.3d") +v43d_l1 = v4_3d_2.not_in(v4_3d_1).interacting(v4_3d_1).or(v4_3d_1.interacting(v4_3d_3)).enclosed(metal4.edges, 0.06.um).polygons(0.001) +v43d_l1.output("V4.3d", "V4.3d : If metal4 overlap Vian by < 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm") +v43d_l1.forget + +v4_3d_1.forget + +v4_3d_2.forget + +v4_3d_3.forget + +# rule V4.3e is not a DRC check + +# Rule V4.4a: metal5 overlap of via4. +logger.info("Executing rule V4.4a") +v44a_l1 = metal5.enclosing(via4, 0.01.um, euclidian).polygons(0.001).or(via4.not_inside(metal5).not(metal5)) +v44a_l1.output("V4.4a", "V4.4a : metal5 overlap of via4.") +v44a_l1.forget + +v4p4b_cond = metal5.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v4p4b_eol = metal5.edges.with_length(nil, 0.34.um).interacting(v4p4b_cond.first_edges).interacting(v4p4b_cond.second_edges).not(v4p4b_cond.first_edges).not(v4p4b_cond.second_edges) +# Rule V4.4b: metal5 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V4.4b") +v44b_l1 = v4p4b_eol.enclosing(via4.edges,0.06.um, projection).polygons(0.001) +v44b_l1.output("V4.4b", "V4.4b : metal5 (< 0.34um) end-of-line overlap. : 0.06µm") +v44b_l1.forget + +v4p4b_cond.forget + +v4p4b_eol.forget + +v4_4c_1 = via4.edges.interacting(via4.drc(enclosed(metal5, projection) < 0.04.um).edges.centers(0, 0.5)) +v4_4c_2 = via4.edges.interacting(via4.drc(0.04.um <= enclosed(metal5, projection) < 0.06.um).centers(0, 0.5)) +v4_4c_3 = v4_4c_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V4.4c: If metal5 overlap via4 by < 0.04um on one side, adjacent metal5 edges overlap. is 0.06µm +logger.info("Executing rule V4.4c") +v44c_l1 = v4_4c_2.not_in(v4_4c_1).interacting(v4_4c_1).or(v4_4c_1.interacting(v4_4c_3)).enclosed(metal5.edges, 0.06.um).polygons(0.001) +v44c_l1.output("V4.4c", "V4.4c : If metal5 overlap via4 by < 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm") +v44c_l1.forget + +v4_4c_1.forget + +v4_4c_2.forget + +v4_4c_3.forget + +# rule V4.4d is not a DRC check + +# rule V4.5 is not a DRC check + +#================================================ +#----------------------VIA5---------------------- +#================================================ + +# Rule V5.1: Min/max Via5 size . is 0.26µm +logger.info("Executing rule V5.1") +v51_l1 = via5.edges.without_length(0.26.um).extended(0, 0, 0.001, 0.001) +v51_l1.output("V5.1", "V5.1 : Min/max Via5 size . : 0.26µm") +v51_l1.forget + +# Rule V5.2a: min. via5 spacing is 0.26µm +logger.info("Executing rule V5.2a") +v52a_l1 = via5.space(0.26.um, euclidian).polygons(0.001) +v52a_l1.output("V5.2a", "V5.2a : min. via5 spacing : 0.26µm") +v52a_l1.forget + +merged_via5 = via5.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal5) +via5_mask = merged_via5.size(1).not(via5).with_holes(16, nil) +selected_via5 = via5.interacting(via5_mask) +# Rule V5.2b: Via5 Space in 4x4 or larger via5 array is 0.36µm +logger.info("Executing rule V5.2b") +v52b_l1 = selected_via5.space(0.36.um, euclidian).polygons(0.001) +v52b_l1.output("V5.2b", "V5.2b : Via5 Space in 4x4 or larger via5 array : 0.36µm") +v52b_l1.forget + +merged_via5.forget + +via5_mask.forget + +selected_via5.forget + +# rule V5.3a is not a DRC check + +# Rule V5.3b: metal5 overlap of via5. +logger.info("Executing rule V5.3b") +v53b_l1 = metal5.enclosing(via5, 0.01.um, euclidian).polygons(0.001).or(via5.not_inside(metal5).not(metal5)) +v53b_l1.output("V5.3b", "V5.3b : metal5 overlap of via5.") +v53b_l1.forget + +v5p3c_cond = metal5.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v5p3c_eol = metal5.edges.with_length(nil, 0.34.um).interacting(v5p3c_cond.first_edges).interacting(v5p3c_cond.second_edges).not(v5p3c_cond.first_edges).not(v5p3c_cond.second_edges) +# Rule V5.3c: metal5 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V5.3c") +v53c_l1 = v5p3c_eol.enclosing(via5.edges,0.06.um, projection).polygons(0.001) +v53c_l1.output("V5.3c", "V5.3c : metal5 (< 0.34um) end-of-line overlap. : 0.06µm") +v53c_l1.forget + +v5p3c_cond.forget + +v5p3c_eol.forget + +v5_3d_1 = via5.edges.interacting(via5.drc(enclosed(metal5, projection) < 0.04.um).edges.centers(0, 0.5)) +v5_3d_2 = via5.edges.interacting(via5.drc(0.04.um <= enclosed(metal5, projection) < 0.06.um).centers(0, 0.5)) +v5_3d_3 = v5_3d_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V5.3d: If metal5 overlap via5 by < 0.04um on one side, adjacent metal5 edges overlap. is 0.06µm +logger.info("Executing rule V5.3d") +v53d_l1 = v5_3d_2.not_in(v5_3d_1).interacting(v5_3d_1).or(v5_3d_1.interacting(v5_3d_3)).enclosed(metal5.edges, 0.06.um).polygons(0.001) +v53d_l1.output("V5.3d", "V5.3d : If metal5 overlap via5 by < 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm") +v53d_l1.forget + +v5_3d_1.forget + +v5_3d_2.forget + +v5_3d_3.forget + +# rule V5.3e is not a DRC check + +# Rule V5.4a: metaltop overlap of via5. +logger.info("Executing rule V5.4a") +v54a_l1 = metaltop.enclosing(via5, 0.01.um, euclidian).polygons(0.001).or(via5.not_inside(metaltop).not(metaltop)) +v54a_l1.output("V5.4a", "V5.4a : metaltop overlap of via5.") +v54a_l1.forget + +v5p4b_cond = metaltop.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v5p4b_eol = metaltop.edges.with_length(nil, 0.34.um).interacting(v5p4b_cond.first_edges).interacting(v5p4b_cond.second_edges).not(v5p4b_cond.first_edges).not(v5p4b_cond.second_edges) +# Rule V5.4b: metaltop (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V5.4b") +v54b_l1 = v5p4b_eol.enclosing(via5.edges,0.06.um, projection).polygons(0.001) +v54b_l1.output("V5.4b", "V5.4b : metaltop (< 0.34um) end-of-line overlap. : 0.06µm") +v54b_l1.forget + +v5p4b_cond.forget + +v5p4b_eol.forget + +v5_4c_1 = via5.edges.interacting(via5.drc(enclosed(metaltop, projection) < 0.04.um).edges.centers(0, 0.5)) +v5_4c_2 = via5.edges.interacting(via5.drc(0.04.um <= enclosed(metaltop, projection) < 0.06.um).centers(0, 0.5)) +v5_4c_3 = v5_4c_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V5.4c: If metaltop overlap via5 by < 0.04um on one side, adjacent metaltop edges overlap. is 0.06µm +logger.info("Executing rule V5.4c") +v54c_l1 = v5_4c_2.not_in(v5_4c_1).interacting(v5_4c_1).or(v5_4c_1.interacting(v5_4c_3)).enclosed(metaltop.edges, 0.06.um).polygons(0.001) +v54c_l1.output("V5.4c", "V5.4c : If metaltop overlap via5 by < 0.04um on one side, adjacent metaltop edges overlap. : 0.06µm") +v54c_l1.forget + +v5_4c_1.forget + +v5_4c_2.forget + +v5_4c_3.forget + +# rule V5.4d is not a DRC check + +# rule V5.5 is not a DRC check + +#================================================ +#--------------------METALTOP-------------------- +#================================================ + +if METAL_TOP == "6K" +logger.info("MetalTop thickness 6k section") + +# Rule MT.1: min. metaltop width is 0.36µm +logger.info("Executing rule MT.1") +mt1_l1 = metaltop.width(0.36.um, euclidian).polygons(0.001) +mt1_l1.output("MT.1", "MT.1 : min. metaltop width : 0.36µm") +mt1_l1.forget + +# Rule MT.2a: min. metaltop spacing is 0.38µm +logger.info("Executing rule MT.2a") +mt2a_l1 = metaltop.space(0.38.um, euclidian).polygons(0.001) +mt2a_l1.output("MT.2a", "MT.2a : min. metaltop spacing : 0.38µm") +mt2a_l1.forget + +# Rule MT.4: Minimum MetalTop area is 0.5625µm² +logger.info("Executing rule MT.4") +mt4_l1 = metaltop.with_area(nil, 0.5625.um) +mt4_l1.output("MT.4", "MT.4 : Minimum MetalTop area : 0.5625µm²") +mt4_l1.forget + +elsif METAL_TOP == "9K" +logger.info("MetalTop thickness 9k/11k section") + +# Rule MT.1: min. metaltop width is 0.44µm +logger.info("Executing rule MT.1") +mt1_l1 = metaltop.width(0.44.um, euclidian).polygons(0.001) +mt1_l1.output("MT.1", "MT.1 : min. metaltop width : 0.44µm") +mt1_l1.forget + +# Rule MT.2a: min. metaltop spacing is 0.46µm +logger.info("Executing rule MT.2a") +mt2a_l1 = metaltop.space(0.46.um, euclidian).polygons(0.001) +mt2a_l1.output("MT.2a", "MT.2a : min. metaltop spacing : 0.46µm") +mt2a_l1.forget + +# Rule MT.4: Minimum MetalTop area is 0.5625µm² +logger.info("Executing rule MT.4") +mt4_l1 = metaltop.with_area(nil, 0.5625.um) +mt4_l1.output("MT.4", "MT.4 : Minimum MetalTop area : 0.5625µm²") +mt4_l1.forget + +elsif METAL_TOP == "30K" +logger.info("MetalTop thickness 30K section") + +# Rule MT30.1a: Min. thick MetalTop width. is 1.8µm +logger.info("Executing rule MT30.1a") +mt301a_l1 = metaltop.width(1.8.um, euclidian).polygons(0.001) +mt301a_l1.output("MT30.1a", "MT30.1a : Min. thick MetalTop width. : 1.8µm") +mt301a_l1.forget + +# Rule MT30.1b: Min width for >1000um long metal line (based on metal edge). is 2.2µm +logger.info("Executing rule MT30.1b") +mt301b_l1 = metaltop.interacting(metaltop.edges.with_length(1000.um, nil)).width(2.2.um, euclidian).polygons(0.001) +mt301b_l1.output("MT30.1b", "MT30.1b : Min width for >1000um long metal line (based on metal edge). : 2.2µm") +mt301b_l1.forget + +# Rule MT30.2: Min. thick MetalTop space. is 1.8µm +logger.info("Executing rule MT30.2") +mt302_l1 = metaltop.space(1.8.um, euclidian).polygons(0.001) +mt302_l1.output("MT30.2", "MT30.2 : Min. thick MetalTop space. : 1.8µm") +mt302_l1.forget + +# Rule MT30.3: The separation of two corners should satisfy the minimum spacing. is 1.8µm +logger.info("Executing rule MT30.3") +mt303_l1 = metaltop.space(1.8.um, euclidian).polygons(0.001) +mt303_l1.output("MT30.3", "MT30.3 : The separation of two corners should satisfy the minimum spacing. : 1.8µm") +mt303_l1.forget + +# Rule MT30.4: The separation of single metal line from a any degree metal line should satisfy the minimum spacing. is 1.8µm +logger.info("Executing rule MT30.4") +mt304_l1 = metaltop.space(1.8.um, euclidian).polygons(0.001) +mt304_l1.output("MT30.4", "MT30.4 : The separation of single metal line from a any degree metal line should satisfy the minimum spacing. : 1.8µm") +mt304_l1.forget + +# Rule MT30.5: Minimum thick MetalTop enclose underlying via (for example: via5 for 6LM case) [Outside Not Allowed]. +logger.info("Executing rule MT30.5") +mt305_l1 = top_metal.enclosing(top_via, 0.12.um, euclidian).polygons(0.001).or(top_via.not_inside(top_metal)) +mt305_l1.output("MT30.5", "MT30.5 : Minimum thick MetalTop enclose underlying via (for example: via5 for 6LM case) [Outside Not Allowed].") +mt305_l1.forget + +mt30p6_cond = top_metal.drc( width <= 0.34.um) +mt30p6_eol = top_metal.edges.with_length(nil, 0.34.um).interacting(mt30p6_cond.first_edges).interacting(mt30p6_cond.second_edges).not(mt30p6_cond.first_edges).not(mt30p6_cond.second_edges) +# Rule MT30.6: Thick MetalTop end-of-line (width <2.5um) enclose underlying via (for example: via5 for 6LM case) [Outside Not Allowed]. +logger.info("Executing rule MT30.6") +mt306_l1 = mt30p6_eol.enclosing(top_via.edges,0.25.um, projection).polygons(0.001).or(top_via.not_inside(top_metal)) +mt306_l1.output("MT30.6", "MT30.6 : Thick MetalTop end-of-line (width <2.5um) enclose underlying via (for example: via5 for 6LM case) [Outside Not Allowed].") +mt306_l1.forget + +mt30p6_cond.forget + +mt30p6_eol.forget + +mt30p8_via_no_mim = top_via.sized(0.18.um).sized(-0.18.um).with_bbox_min(0.78.um , nil).extents.inside(top_metal) +mt30p8_via_mim = top_via.interacting(fusetop).sized(0.3.um).sized(-0.3.um).with_bbox_min(1.02.um , nil).extents.inside(top_metal) +mt30p8_via = mt30p8_via_no_mim.or(mt30p8_via_mim) +mt30p8_mask = mt30p8_via.size(1).not(top_via).with_holes(4, nil) +mt30p8_slct_via = top_via.interacting(mt30p8_mask) +# Rule MT30.8: There shall be minimum 2X2 array of vias (top vias) at one location connecting to 3um thick top metal. +logger.info("Executing rule MT30.8") +mt308_l1 = topmin1_metal.outside(guard_ring_mk).not_interacting(mt30p8_slct_via) +mt308_l1.output("MT30.8", "MT30.8 : There shall be minimum 2X2 array of vias (top vias) at one location connecting to 3um thick top metal.") +mt308_l1.forget + +mt30p8_via.forget + +mt30p8_mask.forget + +mt30p8_slct_via.forget + +end #METAL_TOP + +end #BEOL + +#================================================ +#---------------------MCELL---------------------- +#================================================ + +# Rule MC.1: min. mcell width is 0.4µm +logger.info("Executing rule MC.1") +mc1_l1 = mcell_feol_mk.width(0.4.um, euclidian).polygons(0.001) +mc1_l1.output("MC.1", "MC.1 : min. mcell width : 0.4µm") +mc1_l1.forget + +# Rule MC.2: min. mcell spacing is 0.4µm +logger.info("Executing rule MC.2") +mc2_l1 = mcell_feol_mk.space(0.4.um, euclidian).polygons(0.001) +mc2_l1.output("MC.2", "MC.2 : min. mcell spacing : 0.4µm") +mc2_l1.forget + +# Rule MC.3: Minimum Mcell area is 0.35µm² +logger.info("Executing rule MC.3") +mc3_l1 = mcell_feol_mk.with_area(nil, 0.35.um) +mc3_l1.output("MC.3", "MC.3 : Minimum Mcell area : 0.35µm²") +mc3_l1.forget + +# Rule MC.4: Minimum area enclosed by Mcell is 0.35µm² +logger.info("Executing rule MC.4") +mc4_l1 = mcell_feol_mk.holes.with_area(nil, 0.35.um) +mc4_l1.output("MC.4", "MC.4 : Minimum area enclosed by Mcell : 0.35µm²") +mc4_l1.forget + +#================================================ +#----------------P+ POLY RESISTOR---------------- +#================================================ + +pres_poly = poly2.and(pplus).interacting(sab).interacting(res_mk).not_interacting(resistor) +# Rule PRES.1: Minimum width of Poly2 resistor. is 0.8µm +logger.info("Executing rule PRES.1") +pres1_l1 = pres_poly.width(0.8.um, euclidian).polygons(0.001) +pres1_l1.output("PRES.1", "PRES.1 : Minimum width of Poly2 resistor. : 0.8µm") +pres1_l1.forget + +# Rule PRES.2: Minimum space between Poly2 resistors. is 0.4µm +logger.info("Executing rule PRES.2") +pres2_l1 = pres_poly.isolated(0.4.um, euclidian).polygons(0.001) +pres2_l1.output("PRES.2", "PRES.2 : Minimum space between Poly2 resistors. : 0.4µm") +pres2_l1.forget + +# Rule PRES.3: Minimum space from Poly2 resistor to COMP. +logger.info("Executing rule PRES.3") +pres3_l1 = pres_poly.separation(comp, 0.6.um, euclidian).polygons(0.001).or(comp.not_outside(pres_poly)) +pres3_l1.output("PRES.3", "PRES.3 : Minimum space from Poly2 resistor to COMP.") +pres3_l1.forget + +# Rule PRES.4: Minimum space from Poly2 resistor to unrelated Poly2. is 0.6µm +logger.info("Executing rule PRES.4") +pres4_l1 = pres_poly.separation(poly2.not_interacting(sab), 0.6.um, euclidian).polygons(0.001) +pres4_l1.output("PRES.4", "PRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm") +pres4_l1.forget + +# Rule PRES.5: Minimum Plus implant overlap of Poly2 resistor. is 0.3µm +logger.info("Executing rule PRES.5") +pres5_l1 = pplus.enclosing(pres_poly, 0.3.um, euclidian).polygons(0.001) +pres5_l2 = pres_poly.not_outside(pplus).not(pplus) +pres5_l = pres5_l1.or(pres5_l2) +pres5_l.output("PRES.5", "PRES.5 : Minimum Plus implant overlap of Poly2 resistor. : 0.3µm") +pres5_l1.forget +pres5_l2.forget +pres5_l.forget + +# Rule PRES.6: Minimum salicide block overlap of Poly2 resistor in width direction. is 0.28µm +logger.info("Executing rule PRES.6") +pres6_l1 = sab.enclosing(pres_poly,0.28.um).polygons(0.001) +pres6_l1.output("PRES.6", "PRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm") +pres6_l1.forget + +# Rule PRES.7: Space from salicide block to contact on Poly2 resistor. +logger.info("Executing rule PRES.7") +pres7_l1 = contact.inside(pres_poly).separation(sab,0.22.um).polygons(0.001).or(contact.inside(pres_poly).interacting(sab)) +pres7_l1.output("PRES.7", "PRES.7 : Space from salicide block to contact on Poly2 resistor.") +pres7_l1.forget + +# rule PRES.8 is not a DRC check + +mk_pres9a = res_mk.edges.not(poly2.and(pplus).and(sab).edges).inside_part(poly2) +# Rule PRES.9a: Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. +logger.info("Executing rule PRES.9a") +pres9a_l1 = res_mk.interacting(pres_poly).interacting(mk_pres9a) +pres9a_l1.output("PRES.9a", "PRES.9a : Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2.") +pres9a_l1.forget + +mk_pres9a.forget + +pres9b = res_mk.with_area(15000.01.um,nil).in(res_mk.interacting(res_mk.edges.with_length(80.01.um,nil))) +# Rule PRES.9b: If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. is 20µm +logger.info("Executing rule PRES.9b") +pres9b_l1 = pres9b.interacting(pres_poly).drc(separation(pres9b) < 20.um).polygons(0.001) +pres9b_l1.output("PRES.9b", "PRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm") +pres9b_l1.forget + +pres9b.forget + +pres_poly.forget + +#================================================ +#----------------N+ POLY RESISTOR---------------- +#================================================ + +lres_poly = poly2.and(nplus).interacting(sab).interacting(res_mk) +# Rule LRES.1: Minimum width of Poly2 resistor. is 0.8µm +logger.info("Executing rule LRES.1") +lres1_l1 = lres_poly.width(0.8.um, euclidian).polygons(0.001) +lres1_l1.output("LRES.1", "LRES.1 : Minimum width of Poly2 resistor. : 0.8µm") +lres1_l1.forget + +# Rule LRES.2: Minimum space between Poly2 resistors. is 0.4µm +logger.info("Executing rule LRES.2") +lres2_l1 = lres_poly.isolated(0.4.um, euclidian).polygons(0.001) +lres2_l1.output("LRES.2", "LRES.2 : Minimum space between Poly2 resistors. : 0.4µm") +lres2_l1.forget + +# Rule LRES.3: Minimum space from Poly2 resistor to COMP. +logger.info("Executing rule LRES.3") +lres3_l1 = lres_poly.separation(comp, 0.6.um, euclidian).polygons(0.001).or(comp.not_outside(lres_poly)) +lres3_l1.output("LRES.3", "LRES.3 : Minimum space from Poly2 resistor to COMP.") +lres3_l1.forget + +# Rule LRES.4: Minimum space from Poly2 resistor to unrelated Poly2. is 0.6µm +logger.info("Executing rule LRES.4") +lres4_l1 = lres_poly.separation(poly2.not_interacting(sab), 0.6.um, euclidian).polygons(0.001) +lres4_l1.output("LRES.4", "LRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm") +lres4_l1.forget + +# Rule LRES.5: Minimum Nplus implant overlap of Poly2 resistor. is 0.3µm +logger.info("Executing rule LRES.5") +lres5_l1 = nplus.enclosing(poly2.and(nplus).interacting(sab).interacting(res_mk), 0.3.um, euclidian).polygons(0.001) +lres5_l2 = poly2.and(nplus).interacting(sab).interacting(res_mk).not_outside(nplus).not(nplus) +lres5_l = lres5_l1.or(lres5_l2) +lres5_l.output("LRES.5", "LRES.5 : Minimum Nplus implant overlap of Poly2 resistor. : 0.3µm") +lres5_l1.forget +lres5_l2.forget +lres5_l.forget + +# Rule LRES.6: Minimum salicide block overlap of Poly2 resistor in width direction. is 0.28µm +logger.info("Executing rule LRES.6") +lres6_l1 = sab.enclosing(lres_poly,0.28.um).polygons(0.001) +lres6_l1.output("LRES.6", "LRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm") +lres6_l1.forget + +cont_lres7 = contact.inside(poly2.and(nplus).interacting(sab).interacting(res_mk)) +# Rule LRES.7: Space from salicide block to contact on Poly2 resistor. +logger.info("Executing rule LRES.7") +lres7_l1 = cont_lres7.separation(sab,0.22.um).polygons(0.001).or(cont_lres7.interacting(sab)) +lres7_l1.output("LRES.7", "LRES.7 : Space from salicide block to contact on Poly2 resistor.") +lres7_l1.forget + +cont_lres7.forget + +# rule LRES.8 is not a DRC check + +mk_lres9 = res_mk.edges.not(poly2.and(nplus).and(sab).edges).inside_part(poly2) +# Rule LRES.9a: Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. +logger.info("Executing rule LRES.9a") +lres9a_l1 = res_mk.interacting(lres_poly).interacting(mk_lres9) +lres9a_l1.output("LRES.9a", "LRES.9a : Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. ") +lres9a_l1.forget + +mk_lres9.forget + +lres9b = res_mk.with_area(15000.01.um,nil).in(res_mk.interacting(res_mk.edges.with_length(80.01.um,nil))) +# Rule LRES.9b: If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. is 20µm +logger.info("Executing rule LRES.9b") +lres9b_l1 = res_mk.interacting(lres_poly).drc(separation(lres9b) < 20.um).polygons(0.001) +lres9b_l1.output("LRES.9b", "LRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm") +lres9b_l1.forget + +lres9b.forget + +lres_poly.forget + +#================================================ +#----------------H POLY RESISTOR----------------- +#================================================ + +hres_poly = poly2.interacting(pplus).interacting(sab).interacting(res_mk).interacting(resistor) +hres1_poly = poly2.interacting(pplus).interacting(sab).interacting(res_mk) +# Rule HRES.1: Minimum space. Note : Merge if the spacing is less than 0.4 um. is 0.4µm +logger.info("Executing rule HRES.1") +hres1_l1 = resistor.interacting(hres1_poly).space(0.4.um, euclidian).polygons(0.001) +hres1_l1.output("HRES.1", "HRES.1 : Minimum space. Note : Merge if the spacing is less than 0.4 um. : 0.4µm") +hres1_l1.forget + +# Rule HRES.2: Minimum width of Poly2 resistor. is 1µm +logger.info("Executing rule HRES.2") +hres2_l1 = hres_poly.width(1.um, euclidian).polygons(0.001) +hres2_l1.output("HRES.2", "HRES.2 : Minimum width of Poly2 resistor. : 1µm") +hres2_l1.forget + +# Rule HRES.3: Minimum space between Poly2 resistors. is 0.4µm +logger.info("Executing rule HRES.3") +hres3_l1 = hres_poly.space(0.4.um, euclidian).polygons(0.001) +hres3_l1.output("HRES.3", "HRES.3 : Minimum space between Poly2 resistors. : 0.4µm") +hres3_l1.forget + +# Rule HRES.4: Minimum RESISTOR overlap of Poly2 resistor. is 0.4µm +logger.info("Executing rule HRES.4") +hres4_l1 = resistor.enclosing(hres_poly, 0.4.um, euclidian).polygons(0.001) +hres4_l2 = hres_poly.not_outside(resistor).not(resistor) +hres4_l = hres4_l1.or(hres4_l2) +hres4_l.output("HRES.4", "HRES.4 : Minimum RESISTOR overlap of Poly2 resistor. : 0.4µm") +hres4_l1.forget +hres4_l2.forget +hres4_l.forget + +# Rule HRES.5: Minimum RESISTOR space to unrelated Poly2. is 0.3µm +logger.info("Executing rule HRES.5") +hres5_l1 = resistor.interacting(hres1_poly).separation(poly2.not_interacting(sab), 0.3.um, euclidian).polygons(0.001) +hres5_l1.output("HRES.5", "HRES.5 : Minimum RESISTOR space to unrelated Poly2. : 0.3µm") +hres5_l1.forget + +# Rule HRES.6: Minimum RESISTOR space to COMP. +logger.info("Executing rule HRES.6") +hres6_l1 = resistor.interacting(hres1_poly).separation(comp, 0.3.um, euclidian).polygons(0.001).or(comp.not_outside(resistor.interacting(poly2.interacting(pplus).interacting(sab).interacting(res_mk)))) +hres6_l1.output("HRES.6", "HRES.6 : Minimum RESISTOR space to COMP.") +hres6_l1.forget + +hres1_poly.forget + +# Rule HRES.7: Minimum Pplus overlap of contact on Poly2 resistor. is 0.2µm +logger.info("Executing rule HRES.7") +hres7_l1 = pplus.enclosing(contact.inside(hres_poly), 0.2.um, euclidian).polygons(0.001) +hres7_l2 = contact.inside(hres_poly).not_outside(pplus).not(pplus) +hres7_l = hres7_l1.or(hres7_l2) +hres7_l.output("HRES.7", "HRES.7 : Minimum Pplus overlap of contact on Poly2 resistor. : 0.2µm") +hres7_l1.forget +hres7_l2.forget +hres7_l.forget + +# Rule HRES.8: Space from salicide block to contact on Poly2 resistor. +logger.info("Executing rule HRES.8") +hres8_l1 = contact.inside(hres_poly).separation(sab,0.22.um).polygons(0.001).or(contact.inside(hres_poly).interacting(sab)) +hres8_l1.output("HRES.8", "HRES.8 : Space from salicide block to contact on Poly2 resistor.") +hres8_l1.forget + +hres9_sab = sab.interacting(pplus).interacting(res_mk).interacting(resistor) +hres9_clear_sab = hres9_sab.not(hres_poly) +hres9_bad_inside_edge = hres9_sab.edges.inside_part(hres_poly).extended(0,0,0.001,0.001).interacting(hres9_clear_sab, 1, 1) +hres9_sab_hole = hres9_sab.holes.and(hres_poly) +# Rule HRES.9: Minimum salicide block overlap of Poly2 resistor in width direction. +logger.info("Executing rule HRES.9") +hres9_l1 = hres9_sab.enclosing(hres_poly, 0.28.um, euclidian).polygons(0.001).or(hres9_bad_inside_edge).or(hres9_sab_hole) +hres9_l1.output("HRES.9", "HRES.9 : Minimum salicide block overlap of Poly2 resistor in width direction.") +hres9_l1.forget + +hres9_sab.forget + +hres9_clear_sab.forget + +hres9_bad_inside_edge.forget + +hres9_sab_hole.forget + +pplus1_hres10 = pplus.and(sab).drc(width != 0.1.um) +pplus2_hres10 = pplus.not_overlapping(sab).edges +# Rule HRES.10: Minimum & maximum Pplus overlap of SAB. +logger.info("Executing rule HRES.10") +hres10_l1 = pplus1_hres10.or(pplus2_hres10).extended(0, 0, 0.001, 0.001).interacting(hres_poly) +hres10_l1.output("HRES.10", "HRES.10 : Minimum & maximum Pplus overlap of SAB.") +hres10_l1.forget + +pplus1_hres10.forget + +pplus2_hres10.forget + +# rule HRES.11 is not a DRC check + +mk_hres12a = res_mk.edges.not(poly2.not(pplus).and(sab).edges).inside_part(poly2) +# Rule HRES.12a: P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. +logger.info("Executing rule HRES.12a") +hres12a_l1 = res_mk.interacting(resistor).interacting(mk_hres12a) +hres12a_l1.output("HRES.12a", "HRES.12a : P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. ") +hres12a_l1.forget + +mk_hres12a.forget + +hres12b = res_mk.with_area(15000.01.um,nil).in(res_mk.interacting(res_mk.edges.with_length(80.01.um,nil))) +# Rule HRES.12b: If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer. is 20µm +logger.info("Executing rule HRES.12b") +hres12b_l1 = res_mk.interacting(hres_poly).drc(separation(hres12b) < 20.um).polygons(0.001) +hres12b_l1.output("HRES.12b", "HRES.12b : If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer. : 20µm") +hres12b_l1.forget + +hres12b.forget + +hres_poly.forget + +#================================================ +#------------MIM CAPACITOR OPTION A ------------- +#================================================ + +if MIM_OPTION == "A" +logger.info("MIM Capacitor Option A section") + +mim_virtual = fusetop.sized(1.06.um).and(metal2.interacting(fusetop)) +# Rule MIM.1: Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). is 1.2µm +logger.info("Executing rule MIM.1") +mim1_l1 = metal2.separation(mim_virtual ,transparent, 1.2.um).polygons(0.001) +mim1_l1.output("MIM.1", "MIM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm") +mim1_l1.forget + +# Rule MIM.2: Minimum MiM bottom plate overlap of Via2 layer. [This is applicable for via2 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. is 0.4µm +logger.info("Executing rule MIM.2") +mim2_l1 = metal2.enclosing(via2.overlapping(mim_virtual), 0.4.um, euclidian).polygons(0.001) +mim2_l2 = via2.overlapping(mim_virtual).not_outside(metal2).not(metal2) +mim2_l = mim2_l1.or(mim2_l2) +mim2_l.output("MIM.2", "MIM.2 : Minimum MiM bottom plate overlap of Via2 layer. [This is applicable for via2 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm") +mim2_l1.forget +mim2_l2.forget +mim2_l.forget + +# Rule MIM.3: Minimum MiM bottom plate overlap of Top plate. +logger.info("Executing rule MIM.3") +mim3_l1 = mim_virtual.enclosing(fusetop,0.6.um).polygons(0.001).or(fusetop.not_inside(mim_virtual)) +mim3_l1.output("MIM.3", "MIM.3 : Minimum MiM bottom plate overlap of Top plate.") +mim3_l1.forget + +mim_virtual.forget + +# Rule MIM.4: Minimum MiM top plate (FuseTop) overlap of Via2. is 0.4µm +logger.info("Executing rule MIM.4") +mim4_l1 = fusetop.enclosing(via2, 0.4.um, euclidian).polygons(0.001) +mim4_l2 = via2.not_outside(fusetop).not(fusetop) +mim4_l = mim4_l1.or(mim4_l2) +mim4_l.output("MIM.4", "MIM.4 : Minimum MiM top plate (FuseTop) overlap of Via2. : 0.4µm") +mim4_l1.forget +mim4_l2.forget +mim4_l.forget + +# Rule MIM.5: Minimum spacing between top plate and the Via2 connecting to the bottom plate. is 0.4µm +logger.info("Executing rule MIM.5") +mim5_l1 = fusetop.separation(via2.interacting(metal2), 0.4.um, euclidian).polygons(0.001) +mim5_l1.output("MIM.5", "MIM.5 : Minimum spacing between top plate and the Via2 connecting to the bottom plate. : 0.4µm") +mim5_l1.forget + +# Rule MIM.6: Minimum spacing between unrelated top plates. is 0.6µm +logger.info("Executing rule MIM.6") +mim6_l1 = fusetop.space(0.6.um, euclidian).polygons(0.001) +mim6_l1.output("MIM.6", "MIM.6 : Minimum spacing between unrelated top plates. : 0.6µm") +mim6_l1.forget + +# Rule MIM.7: Min FuseTop enclosure by CAP_MK. +logger.info("Executing rule MIM.7") +mim7_l1 = fusetop.not_inside(cap_mk) +mim7_l1.output("MIM.7", "MIM.7 : Min FuseTop enclosure by CAP_MK.") +mim7_l1.forget + +# Rule MIM.8a: Minimum MIM cap area (defined by FuseTop area) (um2). is 25µm² +logger.info("Executing rule MIM.8a") +mim8a_l1 = fusetop.with_area(nil, 25.um) +mim8a_l1.output("MIM.8a", "MIM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²") +mim8a_l1.forget + +# Rule MIM.8b: Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). is 10000µm +logger.info("Executing rule MIM.8b") +mim8b_l1 = fusetop.with_area(10000.um,nil).not_in(fusetop.with_area(10000.um)) +mim8b_l1.output("MIM.8b", "MIM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm") +mim8b_l1.forget + +# Rule MIM.9: Min. via spacing for sea of via on MIM top plate. is 0.5µm +logger.info("Executing rule MIM.9") +mim9_l1 = via2.inside(fusetop).space(0.5.um, euclidian).polygons(0.001) +mim9_l1.output("MIM.9", "MIM.9 : Min. via spacing for sea of via on MIM top plate. : 0.5µm") +mim9_l1.forget + +# Rule MIM.10: (a) There cannot be any Via1 touching MIM bottom plate Metal2. (b) MIM bottom plate Metal2 can only be connected through the higher Via (Via2). +logger.info("Executing rule MIM.10") +mim10_l1 = via1.interacting(metal2.interacting(fusetop)) +mim10_l1.output("MIM.10", "MIM.10 : (a) There cannot be any Via1 touching MIM bottom plate Metal2. (b) MIM bottom plate Metal2 can only be connected through the higher Via (Via2).") +mim10_l1.forget + +mim11_large_metal2 = metal2.interacting(fusetop).with_area(10000, nil) +mim11_large_metal2_violation = polygon_layer +mim11_large_metal2.data.each do |p| + mim11_metal2_polygon_layer = polygon_layer + mim11_metal2_polygon_layer.data.insert(p) + fuse_in_polygon = fusetop.and(mim11_metal2_polygon_layer) + if(fuse_in_polygon.area > 10000) + mim11_bad_metal2_polygon = mim11_metal2_polygon_layer.interacting(fuse_in_polygon) + mim11_bad_metal2_polygon.data.each do |b| + b.num_points > 0 && mim11_large_metal2_violation.data.insert(b) + end + end +end +# Rule MIM.11: Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIM.8b rule. is -µm +logger.info("Executing rule MIM.11") +mim11_l1 = mim11_large_metal2_violation +mim11_l1.output("MIM.11", "MIM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIM.8b rule. : -µm") +mim11_l1.forget + +mim11_large_metal2.forget + +mim11_large_metal2_violation.forget + +# rule MIM.12 is not a DRC check + +#================================================ +#-------------MIM CAPACITOR OPTION B------------- +#================================================ + +elsif MIM_OPTION == "B" +logger.info("MIM Capacitor Option B section") + +mimtm_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop)) +# Rule MIMTM.1: Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). is 1.2µm +logger.info("Executing rule MIMTM.1") +mimtm1_l1 = topmin1_metal.separation(mimtm_virtual ,transparent, 1.2.um).polygons(0.001) +mimtm1_l1.output("MIMTM.1", "MIMTM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm") +mimtm1_l1.forget + +# Rule MIMTM.2: Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. is 0.4µm +logger.info("Executing rule MIMTM.2") +mimtm2_l1 = topmin1_metal.enclosing(top_via.overlapping(mimtm_virtual), 0.4.um, euclidian).polygons(0.001) +mimtm2_l2 = top_via.overlapping(mimtm_virtual).not_outside(topmin1_metal).not(topmin1_metal) +mimtm2_l = mimtm2_l1.or(mimtm2_l2) +mimtm2_l.output("MIMTM.2", "MIMTM.2 : Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm") +mimtm2_l1.forget +mimtm2_l2.forget +mimtm2_l.forget + +# Rule MIMTM.3: Minimum MiM bottom plate overlap of Top plate. +logger.info("Executing rule MIMTM.3") +mimtm3_l1 = mimtm_virtual.enclosing(fusetop,0.6.um).polygons(0.001).or(fusetop.not_inside(mimtm_virtual)) +mimtm3_l1.output("MIMTM.3", "MIMTM.3 : Minimum MiM bottom plate overlap of Top plate.") +mimtm3_l1.forget + +mimtm_virtual.forget + +# Rule MIMTM.4: Minimum MiM top plate (FuseTop) overlap of Vian-1. is 0.4µm +logger.info("Executing rule MIMTM.4") +mimtm4_l1 = fusetop.enclosing(top_via, 0.4.um, euclidian).polygons(0.001) +mimtm4_l2 = top_via.not_outside(fusetop).not(fusetop) +mimtm4_l = mimtm4_l1.or(mimtm4_l2) +mimtm4_l.output("MIMTM.4", "MIMTM.4 : Minimum MiM top plate (FuseTop) overlap of Vian-1. : 0.4µm") +mimtm4_l1.forget +mimtm4_l2.forget +mimtm4_l.forget + +# Rule MIMTM.5: Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. is 0.4µm +logger.info("Executing rule MIMTM.5") +mimtm5_l1 = fusetop.separation(top_via.interacting(topmin1_metal), 0.4.um, euclidian).polygons(0.001) +mimtm5_l1.output("MIMTM.5", "MIMTM.5 : Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. : 0.4µm") +mimtm5_l1.forget + +# Rule MIMTM.6: Minimum spacing between unrelated top plates. is 0.6µm +logger.info("Executing rule MIMTM.6") +mimtm6_l1 = fusetop.space(0.6.um, euclidian).polygons(0.001) +mimtm6_l1.output("MIMTM.6", "MIMTM.6 : Minimum spacing between unrelated top plates. : 0.6µm") +mimtm6_l1.forget + +# Rule MIMTM.7: Min FuseTop enclosure by CAP_MK. +logger.info("Executing rule MIMTM.7") +mimtm7_l1 = fusetop.not_inside(cap_mk) +mimtm7_l1.output("MIMTM.7", "MIMTM.7 : Min FuseTop enclosure by CAP_MK.") +mimtm7_l1.forget + +# Rule MIMTM.8a: Minimum MIM cap area (defined by FuseTop area) (um2). is 25µm² +logger.info("Executing rule MIMTM.8a") +mimtm8a_l1 = fusetop.with_area(nil, 25.um) +mimtm8a_l1.output("MIMTM.8a", "MIMTM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²") +mimtm8a_l1.forget + +# Rule MIMTM.8b: Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). is 10000µm +logger.info("Executing rule MIMTM.8b") +mimtm8b_l1 = fusetop.with_area(10000.um,nil).not_in(fusetop.with_area(10000.um)) +mimtm8b_l1.output("MIMTM.8b", "MIMTM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm") +mimtm8b_l1.forget + +# Rule MIMTM.9: Min. Via (Vian-1) spacing for sea of Via on MIM top plate. is 0.5µm +logger.info("Executing rule MIMTM.9") +mimtm9_l1 = top_via.inside(fusetop).space(0.5.um, euclidian).polygons(0.001) +mimtm9_l1.output("MIMTM.9", "MIMTM.9 : Min. Via (Vian-1) spacing for sea of Via on MIM top plate. : 0.5µm") +mimtm9_l1.forget + +# Rule MIMTM.10: (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1). +logger.info("Executing rule MIMTM.10") +mimtm10_l1 = topmin1_via.interacting(topmin1_metal.interacting(fusetop)) +mimtm10_l1.output("MIMTM.10", "MIMTM.10 : (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1).") +mimtm10_l1.forget + +mimtm11_large_topmin1_metal = topmin1_metal.interacting(fusetop).with_area(10000, nil) +mimtm11_large_topmin1_metal_violation = polygon_layer +mimtm11_large_topmin1_metal.data.each do |p| + mimtm11_topmin1_metal_polygon_layer = polygon_layer + mimtm11_topmin1_metal_polygon_layer.data.insert(p) + fuse_in_polygon = fusetop.and(mimtm11_topmin1_metal_polygon_layer) + if(fuse_in_polygon.area > 10000) + mimtm11_bad_topmin1_metal_polygon = mimtm11_topmin1_metal_polygon_layer.interacting(fuse_in_polygon) + mimtm11_bad_topmin1_metal_polygon.data.each do |b| + b.num_points > 0 && mimtm11_large_topmin1_metal_violation.data.insert(b) + end + end +end +# Rule MIMTM.11: Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. is -µm +logger.info("Executing rule MIMTM.11") +mimtm11_l1 = mimtm11_large_topmin1_metal_violation +mimtm11_l1.output("MIMTM.11", "MIMTM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. : -µm") +mimtm11_l1.forget + +mimtm11_large_topmin1_metal.forget + +mimtm11_large_topmin1_metal_violation.forget + +# rule MIMTM.12 is not a DRC check + +else +logger.info("No MIM Capacitor Option Selected section") + +end #MIM_OPTION + +#================================================ +#-----------------NATIVE VT NMOS----------------- +#================================================ + +# Rule NAT.1: Min. NAT Overlap of COMP of Native Vt NMOS. is 2µm +logger.info("Executing rule NAT.1") +nat1_l1 = nat.enclosing(ncomp.outside(nwell).interacting(nat), 2.um, euclidian).polygons(0.001) +nat1_l1.output("NAT.1", "NAT.1 : Min. NAT Overlap of COMP of Native Vt NMOS. : 2µm") +nat1_l1.forget + +# Rule NAT.2: Space to unrelated COMP (outside NAT). is 0.3µm +logger.info("Executing rule NAT.2") +nat2_l1 = nat.separation(comp.outside(nat), 0.3.um, euclidian).polygons(0.001) +nat2_l1.output("NAT.2", "NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm") +nat2_l1.forget + +# Rule NAT.3: Space to NWell edge. is 0.5µm +logger.info("Executing rule NAT.3") +nat3_l1 = nat.separation(nwell, 0.5.um, euclidian).polygons(0.001) +nat3_l1.output("NAT.3", "NAT.3 : Space to NWell edge. : 0.5µm") +nat3_l1.forget + +# Rule NAT.4: Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). is 1.8µm +logger.info("Executing rule NAT.4") +nat4_l1 = poly2.edges.and(ngate.edges).not(nwell).interacting(nat).width(1.8.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +nat4_l1.output("NAT.4", "NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm") +nat4_l1.forget + +# Rule NAT.5: Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). is 1.8µm +logger.info("Executing rule NAT.5") +nat5_l1 = poly2.edges.and(ngate.edges).not(nwell).interacting(nat).width(1.8.um, euclidian).polygons(0.001).overlapping(dualgate) +nat5_l1.output("NAT.5", "NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm") +nat5_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_nat, unconnected_nat = conn_space(natcompsd, 10, 10, transparent) + +# Rule NAT.6: Two or more COMPs if connected to different potential are not allowed under same NAT layer. +logger.info("Executing rule NAT.6") +nat6_l1 = comp.and(nat).interacting(unconnected_nat.inside(nat.covering(comp, 2)).not(poly2)) +nat6_l1.output("NAT.6", "NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer.") +nat6_l1.forget + +end #CONNECTIVITY_RULES + +natcompsd.forget + +# Rule NAT.7: Minimum NAT to NAT spacing. is 0.74µm +logger.info("Executing rule NAT.7") +nat7_l1 = nat.space(0.74.um, euclidian).polygons(0.001) +nat7_l1.output("NAT.7", "NAT.7 : Minimum NAT to NAT spacing. : 0.74µm") +nat7_l1.forget + +# Rule NAT.8: Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only. +logger.info("Executing rule NAT.8") +nat8_l1 = nat.not_outside(dualgate).not(dualgate) +nat8_l1.output("NAT.8", "NAT.8 : Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only.") +nat8_l1.forget + +nat9_1 = poly2.and(nat).not(ncomp).interacting(ngate.and(nat) , 2) +nat9_2 = poly2.not(nat).separation(nat, 0.3.um, euclidian).polygons(0.001) +# Rule NAT.9: Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer. +logger.info("Executing rule NAT.9") +nat9_l1 = nat9_1.or(nat9_2) +nat9_l1.output("NAT.9", "NAT.9 : Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer.") +nat9_l1.forget + +nat9_1.forget + +nat9_2.forget + +# Rule NAT.10: Nwell, inside NAT layer are not allowed. +logger.info("Executing rule NAT.10") +nat10_l1 = nwell.inside(nat) +nat10_l1.output("NAT.10", "NAT.10 : Nwell, inside NAT layer are not allowed.") +nat10_l1.forget + +# Rule NAT.11: NCOMP not intersecting to Poly2, is not allowed inside NAT layer. +logger.info("Executing rule NAT.11") +nat11_l1 = ncomp.and(nat).outside(poly2) +nat11_l1.output("NAT.11", "NAT.11 : NCOMP not intersecting to Poly2, is not allowed inside NAT layer.") +nat11_l1.forget + +# Rule NAT.12: Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT). +logger.info("Executing rule NAT.12") +nat12_l1 = poly2.interacting(nat).not_interacting(comp.and(nat)) +nat12_l1.output("NAT.12", "NAT.12 : Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT).") +nat12_l1.forget + +#================================================ +#--------------------DRC_BJT--------------------- +#================================================ + +# Rule BJT.1: Min. DRC_BJT overlap of DNWELL for NPN BJT. +logger.info("Executing rule BJT.1") +bjt1_l1 = dnwell.interacting(drc_bjt).not(dnwell.inside(drc_bjt)) +bjt1_l1.output("BJT.1", "BJT.1 : Min. DRC_BJT overlap of DNWELL for NPN BJT.") +bjt1_l1.forget + +# Rule BJT.2: Min. DRC_BJT overlap of PCOM in Psub. +logger.info("Executing rule BJT.2") +bjt2_l1 = pcomp.outside(nwell).outside(dnwell).interacting(drc_bjt).not(pcomp.outside(nwell).outside(dnwell).inside(drc_bjt)) +bjt2_l1.output("BJT.2", "BJT.2 : Min. DRC_BJT overlap of PCOM in Psub.") +bjt2_l1.forget + +# Rule BJT.3: Minimum space of DRC_BJT layer to unrelated COMP. is 0.1µm +logger.info("Executing rule BJT.3") +bjt3_l1 = comp.outside(drc_bjt).separation(drc_bjt, 0.1.um, euclidian).polygons(0.001) +bjt3_l1.output("BJT.3", "BJT.3 : Minimum space of DRC_BJT layer to unrelated COMP. : 0.1µm") +bjt3_l1.forget + +#================================================ +#--------------DUMMY EXCLUDE LAYERS-------------- +#================================================ + +# rule DE.1 is not a DRC check + +# Rule DE.2: Minimum NDMY or PMNDMY size (x or y dimension in um). is 0.8µm +logger.info("Executing rule DE.2") +de2_l1 = ndmy.or(pmndmy).width(0.8.um, euclidian).polygons(0.001) +de2_l1.output("DE.2", "DE.2 : Minimum NDMY or PMNDMY size (x or y dimension in um). : 0.8µm") +de2_l1.forget + +de3_ndmy_area = ndmy.with_area(15000.um, nil) +# Rule DE.3: If size greater than 15000 um2 then two sides should not be greater than (um). +logger.info("Executing rule DE.3") +de3_l1 = de3_ndmy_area.edges.with_length(80.um, nil).not_interacting(de3_ndmy_area.edges.with_length(nil, 80.um)) +de3_l1.output("DE.3", "DE.3 : If size greater than 15000 um2 then two sides should not be greater than (um).") +de3_l1.forget + +de3_ndmy_area.forget + +# Rule DE.4: Minimum NDMY to NDMY space (Merge if space is less). is 20µm +logger.info("Executing rule DE.4") +de4_l1 = ndmy.space(20.um, euclidian).polygons(0.001) +de4_l1.output("DE.4", "DE.4 : Minimum NDMY to NDMY space (Merge if space is less). : 20µm") +de4_l1.forget + +#================================================ +#--------------------LVS_BJT--------------------- +#================================================ + +vnpn_e = ncomp.interacting(lvs_bjt).inside(dnwell) +vpnp_e = pcomp.inside(nwell).interacting(lvs_bjt) +# Rule LVS_BJT.1: Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers +logger.info("Executing rule LVS_BJT.1") +lvs_l1 = vnpn_e.or(vpnp_e).not_inside(lvs_bjt) +lvs_l1.output("LVS_BJT.1", "LVS_BJT.1 : Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers") +lvs_l1.forget + +vnpn_e.forget + +vpnp_e.forget + +#================================================ +#---------------------OTP_MK--------------------- +#================================================ + +# Rule O.DF.3a: Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. is 0.24µm +logger.info("Executing rule O.DF.3a") +odf3a_l1 = comp.and(otp_mk).space(0.24.um, euclidian).polygons(0.001) +odf3a_l1.output("O.DF.3a", "O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm") +odf3a_l1.forget + +# Rule O.DF.6: Min. COMP extend beyond poly2 (it also means source/drain overhang). is 0.22µm +logger.info("Executing rule O.DF.6") +odf6_l1 = comp.and(otp_mk).enclosing(poly2.and(otp_mk), 0.22.um, euclidian).polygons(0.001) +odf6_l1.output("O.DF.6", "O.DF.6 : Min. COMP extend beyond poly2 (it also means source/drain overhang). : 0.22µm") +odf6_l1.forget + +# Rule O.DF.9: Min. COMP area (um2). is 0.1444µm² +logger.info("Executing rule O.DF.9") +odf9_l1 = comp.and(otp_mk).with_area(nil, 0.1444.um) +odf9_l1.output("O.DF.9", "O.DF.9 : Min. COMP area (um2). : 0.1444µm²") +odf9_l1.forget + +# Rule O.PL.2: Min. poly2 width. is 0.22µm +logger.info("Executing rule O.PL.2") +opl2_l1 = poly2.edges.and(tgate.edges).and(otp_mk).width(0.22.um, euclidian).polygons(0.001) +opl2_l1.output("O.PL.2", "O.PL.2 : Min. poly2 width. : 0.22µm") +opl2_l1.forget + +# Rule O.PL.3a: Min. poly2 Space on COMP. is 0.18µm +logger.info("Executing rule O.PL.3a") +opl3a_l1 = (tgate).or(poly2.not(comp)).and(otp_mk).space(0.18.um, euclidian).polygons(0.001) +opl3a_l1.output("O.PL.3a", "O.PL.3a : Min. poly2 Space on COMP. : 0.18µm") +opl3a_l1.forget + +# Rule O.PL.4: Min. extension beyond COMP to form Poly2 end cap. is 0.14µm +logger.info("Executing rule O.PL.4") +opl4_l1 = poly2.and(otp_mk).enclosing(comp.and(otp_mk), 0.14.um, euclidian).polygons(0.001) +opl4_l1.output("O.PL.4", "O.PL.4 : Min. extension beyond COMP to form Poly2 end cap. : 0.14µm") +opl4_l1.forget + +# rule O.PL.5a is not a DRC check + +# rule O.PL.5b is not a DRC check + +# Rule O.SB.2: Min. salicide Block Space. is 0.28µm +logger.info("Executing rule O.SB.2") +osb2_l1 = sab.and(otp_mk).space(0.28.um, euclidian).polygons(0.001) +osb2_l1.output("O.SB.2", "O.SB.2 : Min. salicide Block Space. : 0.28µm") +osb2_l1.forget + +# Rule O.SB.3: Min. space from salicide block to unrelated COMP. is 0.09µm +logger.info("Executing rule O.SB.3") +osb3_l1 = sab.outside(comp).and(otp_mk).separation(comp.outside(sab), 0.09.um, euclidian).polygons(0.001) +osb3_l1.output("O.SB.3", "O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm") +osb3_l1.forget + +# Rule O.SB.4: Min. space from salicide block to contact. +logger.info("Executing rule O.SB.4") +osb4_l1 = sab.and(otp_mk).separation(contact, 0.03.um, euclidian).polygons(0.001).or(sab.and(otp_mk).and(contact)) +osb4_l1.output("O.SB.4", "O.SB.4 : Min. space from salicide block to contact.") +osb4_l1.forget + +# rule O.SB.5a is not a DRC check + +# Rule O.SB.5b_3.3V: Min. space from salicide block to unrelated Poly2 on COMP. is 0.1µm +logger.info("Executing rule O.SB.5b_3.3V") +osb5b_l1 = sab.outside(tgate).and(otp_mk).separation(tgate.outside(sab), 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +osb5b_l1.output("O.SB.5b_3.3V", "O.SB.5b_3.3V : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm") +osb5b_l1.forget + +# rule O.SB.5b_5V is not a DRC check + +# Rule O.SB.9: Min. salicide block extension beyond unsalicided Poly2. is 0.1µm +logger.info("Executing rule O.SB.9") +osb9_l1 = sab.and(otp_mk).enclosing(poly2.and(sab), 0.1.um, euclidian).polygons +osb9_l1.output("O.SB.9", "O.SB.9 : Min. salicide block extension beyond unsalicided Poly2. : 0.1µm") +osb9_l1.forget + +# Rule O.SB.11: Min. salicide block overlap with COMP. is 0.04µm +logger.info("Executing rule O.SB.11") +osb11_l1 = sab.and(otp_mk).overlap(comp, 0.04.um, euclidian).polygons +osb11_l1.output("O.SB.11", "O.SB.11 : Min. salicide block overlap with COMP. : 0.04µm") +osb11_l1.forget + +# rule O.SB.12 is not a DRC check + +# Rule O.SB.13_3.3V: Min. area of silicide block (um2). is 1.488µm² +logger.info("Executing rule O.SB.13_3.3V") +osb13_l1 = sab.and(otp_mk).with_area(nil, 1.488.um).not_interacting(v5_xtor).not_interacting(dualgate) +osb13_l1.output("O.SB.13_3.3V", "O.SB.13_3.3V : Min. area of silicide block (um2). : 1.488µm²") +osb13_l1.forget + +# Rule O.SB.13_5V: Min. area of silicide block (um2). is 2µm² +logger.info("Executing rule O.SB.13_5V") +osb13_l1 = sab.and(otp_mk).and(v5_xtor).with_area(nil, 2.um) +osb13_l1.output("O.SB.13_5V", "O.SB.13_5V : Min. area of silicide block (um2). : 2µm²") +osb13_l1.forget + +# rule O.SB.15b is not a DRC check + +# Rule O.CO.7: Min. space from COMP contact to Poly2 on COMP. is 0.13µm +logger.info("Executing rule O.CO.7") +oco7_l1 = contact.not_outside(comp).and(otp_mk).separation(tgate.and(otp_mk), 0.13.um, euclidian).polygons(0.001) +oco7_l1.output("O.CO.7", "O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm") +oco7_l1.forget + +# Rule O.PL.ORT: Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. is 0µm +logger.info("Executing rule O.PL.ORT") +oplort_l1 = comp.not(poly2).edges.and(tgate.edges).and(otp_mk).without_angle(0.um).extended(0, 0, 0.001, 0.001) +oplort_l1.output("O.PL.ORT", "O.PL.ORT : Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. : 0µm") +oplort_l1.forget + +#================================================ +#---------------------EFUSE---------------------- +#================================================ + +# Rule EF.01: Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus. +logger.info("Executing rule EF.01") +ef01_l1 = poly2.or(plfuse).interacting(efuse_mk).not_inside(efuse_mk.and(pplus)) +ef01_l1.output("EF.01", "EF.01 : Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus.") +ef01_l1.forget + +# Rule EF.02: Min. Max. PLFUSE width. is 0.18µm +logger.info("Executing rule EF.02") +ef02_l1 = plfuse.drc(width != 0.18.um).extended(0, 0, 0.001, 0.001) +ef02_l1.output("EF.02", "EF.02 : Min. Max. PLFUSE width. : 0.18µm") +ef02_l1.forget + +# Rule EF.03: Min. Max. PLFUSE length. is 1.26µm +logger.info("Executing rule EF.03") +ef03_l1 = plfuse.edges.interacting(poly2.edges.and(plfuse.edges).centers(0, 0.95)).without_length(1.26.um).extended(0, 0, 0.001, 0.001) +ef03_l1.output("EF.03", "EF.03 : Min. Max. PLFUSE length. : 1.26µm") +ef03_l1.forget + +# Rule EF.04a: Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode. +logger.info("Executing rule EF.04a") +ef04a_l1 = plfuse.not_in(plfuse.interacting(poly2.not(plfuse), 2, 2)).inside(efuse_mk).or(plfuse.not(poly2).inside(efuse_mk)) +ef04a_l1.output("EF.04a", "EF.04a : Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode.") +ef04a_l1.forget + +# Rule EF.04b: PLFUSE must be rectangular. is -µm +logger.info("Executing rule EF.04b") +ef04b_l1 = plfuse.non_rectangles +ef04b_l1.output("EF.04b", "EF.04b : PLFUSE must be rectangular. : -µm") +ef04b_l1.forget + +cathode = poly2.inside(efuse_mk).not(lvs_source.or(plfuse)) +# Rule EF.04c: Cathode Poly2 must be rectangular. is -µm +logger.info("Executing rule EF.04c") +ef04c_l1 = cathode.non_rectangles +ef04c_l1.output("EF.04c", "EF.04c : Cathode Poly2 must be rectangular. : -µm") +ef04c_l1.forget + +anode = poly2.and(lvs_source).inside(efuse_mk) +# Rule EF.04d: Anode Poly2 must be rectangular. is -µm +logger.info("Executing rule EF.04d") +ef04d_l1 = anode.non_rectangles +ef04d_l1.output("EF.04d", "EF.04d : Anode Poly2 must be rectangular. : -µm") +ef04d_l1.forget + +# Rule EF.05: Min./Max. LVS_Source overlap Poly2 (at Anode). +logger.info("Executing rule EF.05") +ef05_l1 = poly2.not(plfuse).interacting(lvs_source).not(lvs_source).inside(efuse_mk).or(lvs_source.not(poly2).inside(efuse_mk)) +ef05_l1.output("EF.05", "EF.05 : Min./Max. LVS_Source overlap Poly2 (at Anode).") +ef05_l1.forget + +cathode_width = cathode.edges.not_interacting(cathode.edges.interacting(plfuse)).or(cathode.edges.interacting(plfuse)) +# Rule EF.06: Min./Max. Cathode Poly2 width. is 2.26µm +logger.info("Executing rule EF.06") +ef06_l1 = cathode_width.without_length(2.26.um).extended(0, 0, 0.001, 0.001) +ef06_l1.output("EF.06", "EF.06 : Min./Max. Cathode Poly2 width. : 2.26µm") +ef06_l1.forget + +# Rule EF.07: Min./Max. Cathode Poly2 length. is 1.84µm +logger.info("Executing rule EF.07") +ef07_l1 = cathode.edges.not(cathode_width).without_length(1.84.um).extended(0, 0, 0.001, 0.001) +ef07_l1.output("EF.07", "EF.07 : Min./Max. Cathode Poly2 length. : 1.84µm") +ef07_l1.forget + +anode_width = anode.edges.not_interacting(anode.edges.interacting(plfuse)).or(anode.edges.interacting(plfuse)) +# Rule EF.08: Min./Max. Anode Poly2 width. is 1.06µm +logger.info("Executing rule EF.08") +ef08_l1 = anode_width.without_length(1.06.um).extended(0, 0, 0.001, 0.001) +ef08_l1.output("EF.08", "EF.08 : Min./Max. Anode Poly2 width. : 1.06µm") +ef08_l1.forget + +# Rule EF.09: Min./Max. Anode Poly2 length. is 2.43µm +logger.info("Executing rule EF.09") +ef09_l1 = anode.edges.not(anode_width).without_length(2.43.um).extended(0, 0, 0.001, 0.001) +ef09_l1.output("EF.09", "EF.09 : Min./Max. Anode Poly2 length. : 2.43µm") +ef09_l1.forget + +# Rule EF.10: Min. Cathode Poly2 to Poly2 space. is 0.26µm +logger.info("Executing rule EF.10") +ef10_l1 = cathode.space(0.26.um, euclidian).polygons(0.001) +ef10_l1.output("EF.10", "EF.10 : Min. Cathode Poly2 to Poly2 space. : 0.26µm") +ef10_l1.forget + +# Rule EF.11: Min. Anode Poly2 to Poly2 space. is 0.26µm +logger.info("Executing rule EF.11") +ef11_l1 = anode.space(0.26.um, euclidian).polygons(0.001) +ef11_l1.output("EF.11", "EF.11 : Min. Anode Poly2 to Poly2 space. : 0.26µm") +ef11_l1.forget + +cont_ef = contact.and(plfuse.inside(efuse_mk)) +# Rule EF.12: Min. Space of Cathode Contact to PLFUSE end. +logger.info("Executing rule EF.12") +ef12_l1 = plfuse.inside(efuse_mk).separation(contact.inside(cathode), 0.155.um).polygons(0.001).or(cont_ef) +ef12_l1.output("EF.12", "EF.12 : Min. Space of Cathode Contact to PLFUSE end.") +ef12_l1.forget + +# Rule EF.13: Min. Space of Anode Contact to PLFUSE end. +logger.info("Executing rule EF.13") +ef13_l1 = plfuse.inside(efuse_mk).separation(contact.inside(anode), 0.14.um).polygons(0.001).or(cont_ef) +ef13_l1.output("EF.13", "EF.13 : Min. Space of Anode Contact to PLFUSE end.") +ef13_l1.forget + +cont_ef.forget + +# Rule EF.14: Min. EFUSE_MK enclose LVS_Source. +logger.info("Executing rule EF.14") +ef14_l1 = lvs_source.not_outside(efuse_mk).not(efuse_mk) +ef14_l1.output("EF.14", "EF.14 : Min. EFUSE_MK enclose LVS_Source.") +ef14_l1.forget + +# Rule EF.15: NO Contact is allowed to touch PLFUSE. +logger.info("Executing rule EF.15") +ef15_l1 = plfuse.interacting(contact) +ef15_l1.output("EF.15", "EF.15 : NO Contact is allowed to touch PLFUSE.") +ef15_l1.forget + +# Rule EF.16a: Cathode must contain exact number of Contacts at each ends. is 4µm +logger.info("Executing rule EF.16a") +ef16a_l1 = cathode.not_covering(contact, 4, 4) +ef16a_l1.output("EF.16a", "EF.16a : Cathode must contain exact number of Contacts at each ends. : 4µm") +ef16a_l1.forget + +# Rule EF.16b: Anode must contain exact number of Contacts at each ends. is 4µm +logger.info("Executing rule EF.16b") +ef16b_l1 = anode.not_covering(contact, 4, 4) +ef16b_l1.output("EF.16b", "EF.16b : Anode must contain exact number of Contacts at each ends. : 4µm") +ef16b_l1.forget + +# Rule EF.17: Min. Space of EFUSE_MK to EFUSE_MK. is 0.26µm +logger.info("Executing rule EF.17") +ef17_l1 = efuse_mk.space(0.26.um, euclidian).polygons(0.001) +ef17_l1.output("EF.17", "EF.17 : Min. Space of EFUSE_MK to EFUSE_MK. : 0.26µm") +ef17_l1.forget + +# Rule EF.18: PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2. +logger.info("Executing rule EF.18") +ef18_l1 = plfuse.not_outside(comp.or(nplus).or(esd).or(sab).or(resistor).or(metal1).or(metal2)) +ef18_l1.output("EF.18", "EF.18 : PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2.") +ef18_l1.forget + +# Rule EF.19: Min. PLFUSE space to Metal1, Metal2. +logger.info("Executing rule EF.19") +ef19_l1 = plfuse.not_outside(metal1.or(metal2)) +ef19_l1.output("EF.19", "EF.19 : Min. PLFUSE space to Metal1, Metal2.") +ef19_l1.forget + +# Rule EF.20: Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. is 2.73µm +logger.info("Executing rule EF.20") +ef20_l1 = plfuse.separation(comp.or(nplus).or(esd).or(sab).or(resistor), 2.73.um, euclidian).polygons(0.001) +ef20_l1.output("EF.20", "EF.20 : Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. : 2.73µm") +ef20_l1.forget + +ef_21_fuse = poly2.interacting(plfuse).inside(efuse_mk.and(pplus)).extents.edges +ef_21_anode = anode.edges.not_interacting(anode.edges.interacting(plfuse)) +ef_21_cathode = cathode.edges.not_interacting(cathode.edges.interacting(plfuse)) +# Rule EF.21: Min./Max. eFUSE Poly2 length. is 5.53µm +logger.info("Executing rule EF.21") +ef21_l1 = ef_21_fuse.not_interacting(ef_21_anode.or(ef_21_cathode).centers(0, 0.95)).without_length(5.53.um).extended(0, 0, 0.001, 0.001) +ef21_l1.output("EF.21", "EF.21 : Min./Max. eFUSE Poly2 length. : 5.53µm") +ef21_l1.forget + +ef_21_fuse.forget + +ef_21_anode.forget + +ef_21_cathode.forget + +# Rule EF.22a: Min./Max. Cathode Poly2 overlap with PLFUSE in width direction. is 1.04µm +logger.info("Executing rule EF.22a") +ef22a_l1 = cathode.edges.interacting(plfuse).not(plfuse.edges).without_length(1.04.um).extended(0, 0, 0.001, 0.001) +ef22a_l1.output("EF.22a", "EF.22a : Min./Max. Cathode Poly2 overlap with PLFUSE in width direction. : 1.04µm") +ef22a_l1.forget + +# Rule EF.22b: Min./Max. Anode Poly2 overlap with PLFUSE in width direction. is 0.44µm +logger.info("Executing rule EF.22b") +ef22b_l1 = anode.edges.interacting(plfuse).not(plfuse.edges).without_length(0.44.um).extended(0, 0, 0.001, 0.001) +ef22b_l1.output("EF.22b", "EF.22b : Min./Max. Anode Poly2 overlap with PLFUSE in width direction. : 0.44µm") +ef22b_l1.forget + +#================================================ +#-------------------10V LDNMOS------------------- +#================================================ + +# Rule MDN.1: Min MVSD width (for litho purpose). is 1µm +logger.info("Executing rule MDN.1") +mdn1_l1 = mvsd.width(1.um, euclidian).polygons(0.001) +mdn1_l1.output("MDN.1", "MDN.1 : Min MVSD width (for litho purpose). : 1µm") +mdn1_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_mdn_2a, unconnected_mdn_2b = conn_space(mvsd, 1, 2, euclidian) + +# Rule MDN.2a: Min MVSD space [Same Potential]. is 1µm +logger.info("Executing rule MDN.2a") +mdn2a_l1 = connected_mdn_2a +mdn2a_l1.output("MDN.2a", "MDN.2a : Min MVSD space [Same Potential]. : 1µm") +mdn2a_l1.forget + +# Rule MDN.2b: Min MVSD space [Diff Potential]. is 2µm +logger.info("Executing rule MDN.2b") +mdn2b_l1 = unconnected_mdn_2b +mdn2b_l1.output("MDN.2b", "MDN.2b : Min MVSD space [Diff Potential]. : 2µm") +mdn2b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule MDN.2b: Min MVSD space [Diff Potential]. is 2µm +logger.info("Executing rule MDN.2b") +mdn2b_l1 = mvsd.space(2.um, euclidian).polygons(0.001) +mdn2b_l1.output("MDN.2b", "MDN.2b : Min MVSD space [Diff Potential]. : 2µm") +mdn2b_l1.forget + +end #CONNECTIVITY_RULES + +gate_mdn = poly2.and(comp).inside(ldmos_xtor).inside(dualgate) +# Rule MDN.3a: Min transistor channel length. is 0.6µm +logger.info("Executing rule MDN.3a") +mdn3a_l1 = gate_mdn.enclosing(mvsd, 0.6.um, euclidian).polygons(0.001) +mdn3a_l1.output("MDN.3a", "MDN.3a : Min transistor channel length. : 0.6µm") +mdn3a_l1.forget + +mvsd_mdn = mvsd.edges.and(ncomp).and(poly2) +# Rule MDN.3b: Max transistor channel length. +logger.info("Executing rule MDN.3b") +mdn3b_l1 = poly2.edges.and(ncomp).or(mvsd_mdn).and(ldmos_xtor).and(dualgate).not(ngate.not(mvsd).edges.interacting(poly2.edges.and(ncomp).or(mvsd_mdn)).width(20.001.um).edges) +mdn3b_l1.output("MDN.3b", "MDN.3b : Max transistor channel length.") +mdn3b_l1.forget + +mvsd_mdn.forget + +# Rule MDN.4a: Min transistor channel width. is 4µm +logger.info("Executing rule MDN.4a") +mdn4a_l1 = gate_mdn.edges.not(mvsd).interacting(mvsd).width(4.um, euclidian).polygons(0.001) +mdn4a_l1.output("MDN.4a", "MDN.4a : Min transistor channel width. : 4µm") +mdn4a_l1.forget + +# Rule MDN.4b: Max transistor channel width. +logger.info("Executing rule MDN.4b") +mdn4b_l1 = gate_mdn.not(mvsd).interacting(nplus).not_interacting(gate_mdn.edges.not(mvsd).not(poly2.edges).width(50.001.um).polygons) +mdn4b_l1.output("MDN.4b", "MDN.4b : Max transistor channel width.") +mdn4b_l1.forget + +gate_mdn.forget + +pcomp_mdn5a = pcomp.not_interacting(ncomp).inside(ldmos_xtor).inside(dualgate) +# Rule MDN.5ai: Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. +logger.info("Executing rule MDN.5ai") +mdn5ai_l1 = mvsd.and(pcomp_mdn5a).or(pcomp_mdn5a.separation(mvsd, 1.um, euclidian).polygons(0.001)) +mdn5ai_l1.output("MDN.5ai", "MDN.5ai : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed.") +mdn5ai_l1.forget + +pcomp_mdn5a.forget + +# Rule MDN.5aii: Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. is 0.92µm +logger.info("Executing rule MDN.5aii") +mdn5aii_l1 = pcomp.interacting(ncomp).inside(ldmos_xtor).inside(dualgate).not(nplus).separation(mvsd, 0.92.um, euclidian).polygons(0.001) +mdn5aii_l1.output("MDN.5aii", "MDN.5aii : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. : 0.92µm") +mdn5aii_l1.forget + +ncomp_mdn5b = ncomp.inside(ldmos_xtor).inside(dualgate) +pcomp_mdn5b = pcomp.inside(ldmos_xtor).inside(dualgate) +# Rule MDN.5b: Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP). Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well. +logger.info("Executing rule MDN.5b") +mdn5b_l1 = ncomp_mdn5b.not(poly2).not(mvsd).separation(pcomp_mdn5b, 0.4.um, euclidian).polygons.or(ncomp_mdn5b.not(poly2).not(mvsd).and(pcomp_mdn5b)) +mdn5b_l1.output("MDN.5b", "MDN.5b : Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP). Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well.") +mdn5b_l1.forget + +ncomp_mdn5b.forget + +pcomp_mdn5b.forget + +mdn_5c_ncompsd = ncomp.inside(ldmos_xtor).inside(dualgate).interacting(mvsd).sized(0.36.um).sized(-0.36.um).extents +mdn_5c_error = mdn_5c_ncompsd.edges.centers(0, 0.99).not_interacting(mdn_5c_ncompsd.drc(separation(pcomp, euclidian) <= 15.um).polygons(0.001)) +# Rule MDN.5c: Maximum distance of the nearest edge of the substrate tab from NCOMP edge. is 15µm +logger.info("Executing rule MDN.5c") +mdn5c_l1 = mdn_5c_error.and(ncomp).and(pcomp.holes).extended(0, 0, 0.001, 0.001) +mdn5c_l1.output("MDN.5c", "MDN.5c : Maximum distance of the nearest edge of the substrate tab from NCOMP edge. : 15µm") +mdn5c_l1.forget + +mdn_5c_ncompsd.forget + +mdn_5c_error.forget + +# Rule MDN.6: ALL LDNMOS shall be covered by Dualgate layer. +logger.info("Executing rule MDN.6") +mdn6_l1 = ncomp.not(poly2).not(mvsd).or(ngate.not(mvsd)).or(ncomp.and(mvsd)).inside(ldmos_xtor).not_inside(dualgate) +mdn6_l1.output("MDN.6", "MDN.6 : ALL LDNMOS shall be covered by Dualgate layer.") +mdn6_l1.forget + +# Rule MDN.6a: Min Dualgate enclose NCOMP. +logger.info("Executing rule MDN.6a") +mdn6a_l1 = dualgate.enclosing(ncomp.inside(ldmos_xtor), 0.5.um, euclidian).polygons(0.001).or(ncomp.inside(ldmos_xtor).not_inside(dualgate)) +mdn6a_l1.output("MDN.6a", "MDN.6a : Min Dualgate enclose NCOMP.") +mdn6a_l1.forget + +# Rule MDN.7: Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer. +logger.info("Executing rule MDN.7") +mdn7_l1 = ncomp.interacting(mvsd).not(poly2).not(mvsd).or(ngate.interacting(mvsd).not(mvsd)).or(ncomp.and(mvsd)).inside(dualgate).not_inside(ldmos_xtor) +mdn7_l1.output("MDN.7", "MDN.7 : Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer.") +mdn7_l1.forget + +# Rule MDN.7a: Min LDMOS_XTOR enclose Dualgate. +logger.info("Executing rule MDN.7a") +mdn7a_l1 = dualgate.not_outside(ldmos_xtor).not(ldmos_xtor).or(dualgate.interacting(mvsd).not_inside(ldmos_xtor)) +mdn7a_l1.output("MDN.7a", "MDN.7a : Min LDMOS_XTOR enclose Dualgate.") +mdn7a_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_mdn_8a, unconnected_mdn_8b = conn_separation(mvsd, nwell, 1, 2, euclidian) + +# Rule MDN.8a: Min LDNMOS drain MVSD space to any other equal potential Nwell space. +logger.info("Executing rule MDN.8a") +mdn8a_l1 = connected_mdn_8a.or(mvsd.not_outside(nwell)) +mdn8a_l1.output("MDN.8a", "MDN.8a : Min LDNMOS drain MVSD space to any other equal potential Nwell space.") +mdn8a_l1.forget + +# Rule MDN.8b: Min LDNMOS drain MVSD space to any other different potential Nwell space. +logger.info("Executing rule MDN.8b") +mdn8b_l1 = unconnected_mdn_8b.or(mvsd.not_outside(nwell)) +mdn8b_l1.output("MDN.8b", "MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.") +mdn8b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule MDN.8b: Min LDNMOS drain MVSD space to any other different potential Nwell space. +logger.info("Executing rule MDN.8b") +mdn8b_l1 = mvsd.separation(nwell, 2.um, euclidian).polygons(0.001).or(mvsd.not_outside(nwell)) +mdn8b_l1.output("MDN.8b", "MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.") +mdn8b_l1.forget + +end #CONNECTIVITY_RULES + +# Rule MDN.9: Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. is 4µm +logger.info("Executing rule MDN.9") +mdn9_l1 = mvsd.inside(dualgate).inside(ldmos_xtor).separation(ncomp.not_interacting(mvsd), 4.um, euclidian).polygons(0.001) +mdn9_l1.output("MDN.9", "MDN.9 : Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. : 4µm") +mdn9_l1.forget + +# rule MDN.10 is not a DRC check + +poly_mdn10 = poly2.inside(dualgate).inside(ldmos_xtor.interacting(mvsd)) +# Rule MDN.10a: Min LDNMOS POLY2 width. is 1.2µm +logger.info("Executing rule MDN.10a") +mdn10a_l1 = poly_mdn10.width(1.2.um, euclidian).polygons(0.001) +mdn10a_l1.output("MDN.10a", "MDN.10a : Min LDNMOS POLY2 width. : 1.2µm") +mdn10a_l1.forget + +# Rule MDN.10b: Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). is 0.4µm +logger.info("Executing rule MDN.10b") +mdn10b_l1 = poly_mdn10.edges.enclosing(ncomp.interacting(poly_mdn10).edges.interacting(ncomp.edges.not_interacting(poly2)), 0.4.um, euclidian) +mdn10b_l1.output("MDN.10b", "MDN.10b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). : 0.4µm") +mdn10b_l1.forget + +mdn_10c_all_errors = poly_mdn10.drc(enclosing(ncomp.interacting(poly_mdn10), euclidian) != 0.2.um) +mdn_10c_error_region = ncomp.inside(dualgate).inside(ldmos_xtor).sized(0.36.um).sized(-0.36.um).extents.and(mvsd).and(poly2) +# Rule MDN.10c: Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction. +logger.info("Executing rule MDN.10c") +mdn10c_l1 = mdn_10c_all_errors.and(mdn_10c_error_region) +mdn10c_l1.output("MDN.10c", "MDN.10c : Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction.") +mdn10c_l1.forget + +mdn_10c_all_errors.forget + +mdn_10c_error_region.forget + +mdn_10d_field = ncomp.and(poly2).sized(1.um, 0).and(poly2) +mdn_10d_not_max = ncomp.inside(mvsd).inside(dualgate).inside(ldmos_xtor).drc(separation(mdn_10d_field) <= 0.16.um) +mdn_10d_max = ncomp.sized(0.36.um).sized(-0.36.um).extents.not(mdn_10d_not_max.polygons).not(ncomp).not(poly2).inside(mvsd) +mdn_10d_min = ncomp.inside(mvsd).inside(dualgate).inside(ldmos_xtor).separation(mdn_10d_field , 0.16.um).polygons(0.001) +mdn_10d_overlap = ncomp.inside(mvsd).inside(dualgate).inside(ldmos_xtor).and(poly2) +# Rule MDN.10d: Min/Max POLY2 on field space to LDNMOS drain COMP. +logger.info("Executing rule MDN.10d") +mdn10d_l1 = mdn_10d_max.or(mdn_10d_min).or(mdn_10d_overlap) +mdn10d_l1.output("MDN.10d", "MDN.10d : Min/Max POLY2 on field space to LDNMOS drain COMP.") +mdn10d_l1.forget + +mdn_10d_field.forget + +mdn_10d_not_max.forget + +mdn_10d_max.forget + +mdn_10d_min.forget + +mdn_10d_overlap.forget + +# Rule MDN.10ei: Min POLY2 space to Psub tap (source and body tap non-butted). +logger.info("Executing rule MDN.10ei") +mdn10ei_l1 = poly_mdn10.separation(pcomp.not_interacting(ncomp), 0.4.um).polygons(0.001).or(poly_mdn10.and(pcomp.not(nplus).not_interacting(ncomp.not(pplus)))) +mdn10ei_l1.output("MDN.10ei", "MDN.10ei : Min POLY2 space to Psub tap (source and body tap non-butted).") +mdn10ei_l1.forget + +# Rule MDN.10eii: Min POLY2 space to Psub tap (source and body tap butted). is 0.32µm +logger.info("Executing rule MDN.10eii") +mdn10eii_l1 = poly_mdn10.separation(pcomp.not(nplus).interacting(ncomp.not(pplus)), 0.32.um, euclidian).polygons(0.001) +mdn10eii_l1.output("MDN.10eii", "MDN.10eii : Min POLY2 space to Psub tap (source and body tap butted). : 0.32µm") +mdn10eii_l1.forget + +# Rule MDN.10f: Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed. +logger.info("Executing rule MDN.10f") +mdn10f_l1 = poly_mdn10.not(nplus).interacting(poly_mdn10.and(nplus),2).or(poly2.and(ldmos_xtor).interacting(poly2.not(ldmos_xtor))) +mdn10f_l1.output("MDN.10f", "MDN.10f : Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed.") +mdn10f_l1.forget + +poly_mdn10.forget + +mdn_11_layer = ldmos_xtor.and(mvsd).and(comp).and(poly2).and(nplus) +mdn_11_max = mdn_11_layer.not(mdn_11_layer.drc(width <= 0.4.um).polygons) +mdn_11_min = mdn_11_layer.width(0.4.um).polygons(0.001).not_interacting(mdn_11_max) +mdn_11_no_channel = mvsd.covering(ncomp).outside(tgate).inside(dualgate).inside(ldmos_xtor).or(mvsd.not_covering(ncomp.not_interacting(poly2)).inside(dualgate).inside(ldmos_xtor)) +# Rule MDN.11: Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus). +logger.info("Executing rule MDN.11") +mdn11_l1 = mdn_11_max.or(mdn_11_min).or(mdn_11_no_channel) +mdn11_l1.output("MDN.11", "MDN.11 : Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus).") +mdn11_l1.forget + +mdn_11_layer.forget + +mdn_11_max.forget + +mdn_11_min.forget + +mdn_11_no_channel.forget + +mdn12_a = mvsd.covering(ncomp.not_interacting(poly2)).enclosing(ncomp, 0.5.um, transparent).polygons(0.001).outside(poly2).inside(dualgate).inside(ldmos_xtor) +mdn12_b = mvsd.not_covering(ncomp.not_interacting(poly2)).inside(dualgate).inside(ldmos_xtor) +# Rule MDN.12: Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width. +logger.info("Executing rule MDN.12") +mdn12_l1 = mdn12_a.or(mdn12_b) +mdn12_l1.output("MDN.12", "MDN.12 : Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width.") +mdn12_l1.forget + +mdn12_a.forget + +mdn12_b.forget + +# rule MDN.13 is not a DRC check + +# Rule MDN.13a: Max single finger width. is 50µm +logger.info("Executing rule MDN.13a") +mdn13a_l1 = poly2.and(ncomp).not(mvsd).inside(dualgate).inside(ldmos_xtor).drc(length > 50.um) +mdn13a_l1.output("MDN.13a", "MDN.13a : Max single finger width. : 50µm") +mdn13a_l1.forget + +mdn_source = ncomp.interacting(poly2.and(dualgate).and(ldmos_xtor).and(mvsd)).not(poly2) +mdn_ldnmos = poly2.and(ncomp).and(dualgate).not(mvsd).inside(ldmos_xtor) +# Rule MDN.13b: Layout shall have alternative source & drain. +logger.info("Executing rule MDN.13b") +mdn13b_l1 = mdn_ldnmos.not_interacting(mdn_source,1,1).or(mdn_ldnmos.not_interacting(mvsd,1,1)).or(mdn_source.interacting(mvsd)) +mdn13b_l1.output("MDN.13b", "MDN.13b : Layout shall have alternative source & drain.") +mdn13b_l1.forget + +mdn_13c_source_side = mdn_ldnmos.interacting(mdn_source.interacting(mdn_ldnmos, 2, 2).or(mdn_source.interacting(pcomp.interacting(mdn_source, 2, 2)))) +# Rule MDN.13c: Both sides of the transistor shall be terminated by source. +logger.info("Executing rule MDN.13c") +mdn13c_l1 = mvsd.covering(ncomp.not_interacting(poly2)).interacting(ncomp, 2, 2).interacting(mdn_13c_source_side) +mdn13c_l1.output("MDN.13c", "MDN.13c : Both sides of the transistor shall be terminated by source.") +mdn13c_l1.forget + +mdn_13c_source_side.forget + +mdn_13d_single = mvsd.covering(ncomp.not_interacting(poly2)).interacting(ncomp, 2, 2).inside(ldmos_xtor) +mdn_13d_multi = mvsd.covering(ncomp.not_interacting(poly2)).interacting(ncomp, 3, 3).inside(ldmos_xtor) +mdn_13d_butted_well = mdn_source.sized(1.um).sized(-1.um).extents.not(pcomp).interacting(mdn_ldnmos,2,2) +# Rule MDN.13d: Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap). +logger.info("Executing rule MDN.13d") +mdn13d_l1 = pcomp.holes.covering(mdn_13d_single, 2).or(pcomp.holes.covering(mdn_13d_single).covering(mdn_13d_multi)).or(mdn_13d_butted_well) +mdn13d_l1.output("MDN.13d", "MDN.13d : Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap).") +mdn13d_l1.forget + +mdn_13d_single.forget + +mdn_13d_multi.forget + +mdn_13d_butted_well.forget + +mdn_source.forget + +mdn_ldnmos.forget + +# Rule MDN.14: Min MVSD space to any DNWELL. +logger.info("Executing rule MDN.14") +mdn14_l1 = mvsd.separation(dnwell,6.0.um).polygons(0.001).or(mvsd.not_outside(dnwell)) +mdn14_l1.output("MDN.14", "MDN.14 : Min MVSD space to any DNWELL.") +mdn14_l1.forget + +# Rule MDN.15a: Min LDNMOS drain COMP width. is 0.22µm +logger.info("Executing rule MDN.15a") +mdn15a_l1 = comp.inside(mvsd).inside(dualgate).inside(ldmos_xtor).width(0.22.um, euclidian).polygons(0.001) +mdn15a_l1.output("MDN.15a", "MDN.15a : Min LDNMOS drain COMP width. : 0.22µm") +mdn15a_l1.forget + +# Rule MDN.15b: Min LDNMOS drain COMP enclose contact. is 0µm +logger.info("Executing rule MDN.15b") +mdn15b_l1 = contact.interacting(ncomp.inside(mvsd).inside(dualgate).inside(ldmos_xtor)).not_inside(ncomp.inside(mvsd)) +mdn15b_l1.output("MDN.15b", "MDN.15b : Min LDNMOS drain COMP enclose contact. : 0µm") +mdn15b_l1.forget + +# rule MDN.16 is not a DRC check + +mdn_17_blockages = pcomp.holes.not(ncomp.or(poly2).interacting(mvsd)).covering(dnwell.or(nwell)).inside(dualgate).inside(ldmos_xtor.interacting(mvsd)) +mdn_17_mos_in_gr = ngate.not(mvsd).not_inside(pcomp.holes).inside(dualgate).inside(ldmos_xtor.interacting(mvsd)) +mdn_17_gr_in_ldmos_mk = ldmos_xtor.interacting(mvsd).and(dualgate).not_covering(pcomp) +# Rule MDN.17: It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity. +logger.info("Executing rule MDN.17") +mdn17_l1 = mdn_17_blockages.or(mdn_17_mos_in_gr).or(mdn_17_gr_in_ldmos_mk) +mdn17_l1.output("MDN.17", "MDN.17 : It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity.") +mdn17_l1.forget + +mdn_17_blockages.forget + +mdn_17_mos_in_gr.forget + +mdn_17_gr_in_ldmos_mk.forget + +#================================================ +#-------------------10V LDPMOS------------------- +#================================================ + +mdp_source = (pcomp).interacting(poly2.and(dualgate).and(ldmos_xtor).and(mvpsd)).not(poly2) +ldpmos = poly2.and(pcomp).and(dualgate).not(mvpsd).inside(ldmos_xtor) +# Rule MDP.1: Minimum transistor channel length. is 0.6µm +logger.info("Executing rule MDP.1") +mdp1_l1 = poly2.and(comp).inside(ldmos_xtor).inside(dualgate).enclosing(mvpsd, 0.6.um, euclidian).polygons(0.001) +mdp1_l1.output("MDP.1", "MDP.1 : Minimum transistor channel length. : 0.6µm") +mdp1_l1.forget + +mvpsd_mdp = mvpsd.edges.and(pcomp).and(poly2) +# Rule MDP.1a: Max transistor channel length. +logger.info("Executing rule MDP.1a") +mdp1a_l1 = poly2.edges.and(pcomp).or(mvpsd_mdp).and(ldmos_xtor).and(dualgate).not(pgate.not(mvpsd).edges.interacting(poly2.edges.and(pcomp).or(mvpsd_mdp)).width(20.001.um).edges) +mdp1a_l1.output("MDP.1a", "MDP.1a : Max transistor channel length.") +mdp1a_l1.forget + +mvpsd_mdp.forget + +# Rule MDP.2: Minimum transistor channel width. is 4µm +logger.info("Executing rule MDP.2") +mdp2_l1 = poly2.and(comp).inside(ldmos_xtor).inside(dualgate).edges.not(mvpsd).interacting(mvpsd).width(4.um, euclidian).polygons(0.001) +mdp2_l1.output("MDP.2", "MDP.2 : Minimum transistor channel width. : 4µm") +mdp2_l1.forget + +mdp3_1 = ldpmos.or(mvpsd).or(mdp_source).not_interacting(ncomp.holes).inside(dualgate).inside(ldmos_xtor) +mdp3_2 = ncomp.holes.not_interacting(ncomp.interacting(mdp_source)).not_interacting(mvpsd,1,1).inside(dualgate).inside(ldmos_xtor) +# Rule MDP.3: Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL +logger.info("Executing rule MDP.3") +mdp3_l1 = mdp3_1.or(mdp3_2) +mdp3_l1.output("MDP.3", "MDP.3 : Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL") +mdp3_l1.forget + +ncomp_mdp3ai = ncomp.not_interacting(pcomp).inside(ldmos_xtor).inside(dualgate) +# Rule MDP.3ai: Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed. +logger.info("Executing rule MDP.3ai") +mdp3ai_l1 = ncomp_mdp3ai.separation(mvpsd, 1.um, euclidian).polygons(0.001).or(mvpsd.interacting(ncomp_mdp3ai)) +mdp3ai_l1.output("MDP.3ai", "MDP.3ai : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.") +mdp3ai_l1.forget + +ncomp_mdp3ai.forget + +ncomp_mdp3aii = ncomp.interacting(pcomp).inside(ldmos_xtor).inside(dualgate) +# Rule MDP.3aii: Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed. +logger.info("Executing rule MDP.3aii") +mdp3aii_l1 = ncomp_mdp3aii.separation(mvpsd, 0.92.um, euclidian).polygons(0.001).or(mvpsd.interacting(ncomp_mdp3aii)) +mdp3aii_l1.output("MDP.3aii", "MDP.3aii : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.") +mdp3aii_l1.forget + +ncomp_mdp3aii.forget + +ncomp_mdp3b = ncomp.inside(ldmos_xtor).inside(dualgate) +pcomp_mdp3b = pcomp.inside(dnwell).inside(ldmos_xtor).inside(dualgate) +# Rule MDP.3b: Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. is 0.4µm +logger.info("Executing rule MDP.3b") +mdp3b_l1 = ncomp_mdp3b.not(poly2).not(mvpsd).separation(pcomp_mdp3b.not(poly2).not(mvpsd), 0.4.um, euclidian).polygons(0.001) +mdp3b_l1.output("MDP.3b", "MDP.3b : Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. : 0.4µm") +mdp3b_l1.forget + +ncomp_mdp3b.forget + +pcomp_mdp3b.forget + +# Rule MDP.3c: Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). is 15µm +logger.info("Executing rule MDP.3c") +mdp3c_l1 = ncomp.inside(dnwell).inside(ldmos_xtor).inside(dualgate).not_interacting(ncomp.inside(dnwell).drc(separation(pcomp.inside(dnwell)) <= 15.um).first_edges,4) +mdp3c_l1.output("MDP.3c", "MDP.3c : Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). : 15µm") +mdp3c_l1.forget + +# Rule MDP.3d: The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. is 10µm +logger.info("Executing rule MDP.3d") +mdp3d_l1 = ncomp.interacting(ldmos_xtor.interacting(mvpsd)).interacting(dualgate).not(metal1).edges.not(metal1).with_length(10.001.um, nil) +mdp3d_l1.output("MDP.3d", "MDP.3d : The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. : 10µm") +mdp3d_l1.forget + +mdp4_metal = pcomp.not_interacting(mvpsd).interacting(ldmos_xtor.interacting(mvpsd)).interacting(dualgate).not(metal1).edges.not(metal1).with_length(10.001.um, nil) +# Rule MDP.4: DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. +logger.info("Executing rule MDP.4") +mdp4_l1 = pcomp.interacting(metal1).not_interacting(pcomp.holes).edges.and(ldmos_xtor).and(dualgate).or(mdp4_metal) +mdp4_l1.output("MDP.4", "MDP.4 : DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability.") +mdp4_l1.forget + +mdp4_metal.forget + +# Rule MDP.4a: Min PCOMP (Pplus AND COMP) space to DNWELL. is 2.5µm +logger.info("Executing rule MDP.4a") +mdp4a_l1 = pcomp.inside(ldmos_xtor).inside(dualgate).separation(dnwell.inside(ldmos_xtor).inside(dualgate), 2.5.um, euclidian).polygons(0.001) +mdp4a_l1.output("MDP.4a", "MDP.4a : Min PCOMP (Pplus AND COMP) space to DNWELL. : 2.5µm") +mdp4a_l1.forget + +mdp4b_dnwell_edges = dnwell.inside(ldmos_xtor).inside(dualgate).edges.centers(0, 0.99) +mdp4b_not_error = dnwell.drc(separation(pcomp.inside(ldmos_xtor.interacting(mvpsd)).inside(dualgate).not_interacting(mvpsd), euclidian) <= 15.um).polygons(0.001) +# Rule MDP.4b: Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. is 15µm +logger.info("Executing rule MDP.4b") +mdp4b_l1 = mdp4b_dnwell_edges.not_interacting(mdp4b_not_error).and(pcomp.holes).extended(0, 0, 0.001, 0.001) +mdp4b_l1.output("MDP.4b", "MDP.4b : Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. : 15µm") +mdp4b_l1.forget + +mdp4b_dnwell_edges.forget + +mdp4b_not_error.forget + +# Rule MDP.5: Each LDPMOS shall be covered by Dualgate layer. +logger.info("Executing rule MDP.5") +mdp5_l1 = pcomp.not(poly2).not(mvpsd).or(pgate.not(mvpsd)).or(pcomp.and(mvpsd)).inside(ldmos_xtor).not_inside(dualgate) +mdp5_l1.output("MDP.5", "MDP.5 : Each LDPMOS shall be covered by Dualgate layer.") +mdp5_l1.forget + +# Rule MDP.5a: Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). is 0.5µm +logger.info("Executing rule MDP.5a") +mdp5a_l1 = dualgate.interacting(ldmos_xtor).enclosing(pcomp.inside(ldmos_xtor), 0.5.um, euclidian).polygons(0.001) +mdp5a_l2 = pcomp.inside(ldmos_xtor).not_outside(dualgate.interacting(ldmos_xtor)).not(dualgate.interacting(ldmos_xtor)) +mdp5a_l = mdp5a_l1.or(mdp5a_l2) +mdp5a_l.output("MDP.5a", "MDP.5a : Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). : 0.5µm") +mdp5a_l1.forget +mdp5a_l2.forget +mdp5a_l.forget + +# Rule MDP.6: Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer. +logger.info("Executing rule MDP.6") +mdp6_l1 = mvpsd.not_inside(ldmos_xtor) +mdp6_l1.output("MDP.6", "MDP.6 : Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer.") +mdp6_l1.forget + +# Rule MDP.6a: Minimum LDMOS_XTOR enclose Dualgate. +logger.info("Executing rule MDP.6a") +mdp6a_l1 = ldmos_xtor.not_covering(dualgate) +mdp6a_l1.output("MDP.6a", "MDP.6a : Minimum LDMOS_XTOR enclose Dualgate.") +mdp6a_l1.forget + +# Rule MDP.7: Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. is 2µm +logger.info("Executing rule MDP.7") +mdp7_l1 = ldmos_xtor.separation(nwell.outside(ldmos_xtor), 2.um, euclidian).polygons(0.001) +mdp7_l1.output("MDP.7", "MDP.7 : Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. : 2µm") +mdp7_l1.forget + +# Rule MDP.8: Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. is 1.5µm +logger.info("Executing rule MDP.8") +mdp8_l1 = ldmos_xtor.separation(ncomp.outside(ldmos_xtor), 1.5.um, euclidian).polygons(0.001) +mdp8_l1.output("MDP.8", "MDP.8 : Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. : 1.5µm") +mdp8_l1.forget + +# Rule MDP.9a: Min LDPMOS POLY2 width. is 1.2µm +logger.info("Executing rule MDP.9a") +mdp9a_l1 = poly2.inside(dnwell.and(dualgate).and(ldmos_xtor)).width(1.2.um, euclidian).polygons(0.001) +mdp9a_l1.output("MDP.9a", "MDP.9a : Min LDPMOS POLY2 width. : 1.2µm") +mdp9a_l1.forget + +mdp9b_1 = poly2.inside(dnwell.and(dualgate).and(ldmos_xtor)).edges.interacting(mvpsd).not(mvpsd).enclosing(comp.edges,0.4.um).edges +mdp9b_2 = poly2.inside(dnwell.and(dualgate).and(ldmos_xtor)).edges.interacting(mvpsd).not(mvpsd).interacting(pcomp) +# Rule MDP.9b: Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). is 0.4µm +logger.info("Executing rule MDP.9b") +mdp9b_l1 = mdp9b_1.or(mdp9b_2).extended(0,0,0.001,0.001) +mdp9b_l1.output("MDP.9b", "MDP.9b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). : 0.4µm") +mdp9b_l1.forget + +mdp9b_1.forget + +mdp9b_2.forget + +# Rule MDP.9c: Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction. +logger.info("Executing rule MDP.9c") +mdp9c_l1 = poly2.edges.in(poly2.inside(dnwell.and(dualgate).and(ldmos_xtor)).edges.inside_part(mvpsd)).not_interacting(poly2.drc(enclosing(comp,projection) == 0.2.um)) +mdp9c_l1.output("MDP.9c", "MDP.9c : Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction.") +mdp9c_l1.forget + +# Rule MDP.9d: Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space. +logger.info("Executing rule MDP.9d") +mdp9d_l1 = poly2.inside(dualgate).inside(ldmos_xtor).overlapping(mvpsd.and(pcomp).not(poly2).sized(0.16.um)).or(poly2.inside(dualgate).inside(ldmos_xtor.interacting(mvpsd)).not_interacting(mvpsd.and(pcomp).not(poly2).sized(0.16.um))) +mdp9d_l1.output("MDP.9d", "MDP.9d : Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space.") +mdp9d_l1.forget + +ldpmos_poly2_gate = poly2.interacting(pgate.and(dualgate).not(mvpsd)) +ncomp_not_butted = ncomp.not(pplus).not_interacting(pcomp.not(nplus)).or(ncomp.not(pplus).overlapping(pcomp.not(nplus))) +mdp9ei_1 = ldpmos_poly2_gate.inside(dualgate).inside(ldmos_xtor).separation(ncomp_not_butted, 0.4.um).polygons(0.001) +mdp9ei_2 = ldpmos_poly2_gate.inside(dualgate).inside(ldmos_xtor).and(ncomp_not_butted) +# Rule MDP.9ei: Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted). +logger.info("Executing rule MDP.9ei") +mdp9ei_l1 = mdp9ei_1.or(mdp9ei_2) +mdp9ei_l1.output("MDP.9ei", "MDP.9ei : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted).") +mdp9ei_l1.forget + +ncomp_not_butted.forget + +mdp9ei_1.forget + +mdp9ei_2.forget + +ncomp_butted = ncomp.not(pplus).interacting(pcomp.not(nplus)).not_overlapping(pcomp.not(nplus)) +mdp9eii_1 = ldpmos_poly2_gate.inside(dualgate).inside(ldmos_xtor).separation(ncomp_butted, 0.32.um).polygons(0.001) +mdp9eii_2 = ldpmos_poly2_gate.inside(dualgate).inside(ldmos_xtor).and(ncomp_butted) +# Rule MDP.9eii: Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted). +logger.info("Executing rule MDP.9eii") +mdp9eii_l1 = mdp9eii_1.or(mdp9eii_2) +mdp9eii_l1.output("MDP.9eii", "MDP.9eii : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted).") +mdp9eii_l1.forget + +ncomp_butted.forget + +mdp9eii_1.forget + +mdp9eii_2.forget + +# Rule MDP.9f: Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). is -µm +logger.info("Executing rule MDP.9f") +mdp9f_l1 = poly2.not(pplus).inside(dualgate).inside(ldmos_xtor).interacting(poly2.and(pplus).inside(dualgate).inside(ldmos_xtor),2) +mdp9f_l1.output("MDP.9f", "MDP.9f : Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). : -µm") +mdp9f_l1.forget + +# Rule MDP.10: Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus). +logger.info("Executing rule MDP.10") +mdp10_l1 = mvpsd.inside(dualgate).inside(ldmos_xtor).not_interacting(mvpsd.drc(overlap(ldmos_xtor.and(comp).and(poly2).and(pplus),projection) == 0.4)) +mdp10_l1.output("MDP.10", "MDP.10 : Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus).") +mdp10_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_mdp_10b, unconnected_mdp_10a = conn_space(mvpsd, 1, 2, euclidian) + +# Rule MDP.10a: Min MVPSD space within LDMOS_XTOR marking [diff potential]. is 2µm +logger.info("Executing rule MDP.10a") +mdp10a_l1 = unconnected_mdp_10a +mdp10a_l1.output("MDP.10a", "MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm") +mdp10a_l1.forget + +# Rule MDP.10b: Min MVPSD space [same potential]. Merge if space less than 1um. is 1µm +logger.info("Executing rule MDP.10b") +mdp10b_l1 = connected_mdp_10b +mdp10b_l1.output("MDP.10b", "MDP.10b : Min MVPSD space [same potential]. Merge if space less than 1um. : 1µm") +mdp10b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule MDP.10a: Min MVPSD space within LDMOS_XTOR marking [diff potential]. is 2µm +logger.info("Executing rule MDP.10a") +mdp10a_l1 = mvpsd.space(2.um, euclidian).polygons(0.001) +mdp10a_l1.output("MDP.10a", "MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm") +mdp10a_l1.forget + +end #CONNECTIVITY_RULES + +# Rule MDP.11: Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width. +logger.info("Executing rule MDP.11") +mdp11_l1 = mvpsd.edges.not_interacting(pcomp.edges).enclosing(pcomp.edges, 0.8.um, euclidian).polygons(0.001).or(mvpsd.interacting(mvpsd.edges.and(pcomp.edges))) +mdp11_l1.output("MDP.11", "MDP.11 : Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width.") +mdp11_l1.forget + +# Rule MDP.12: Min DNWELL enclose Nplus guard ring (NCOMP). is 0.66µm +logger.info("Executing rule MDP.12") +mdp12_l1 = dnwell.inside(dualgate).inside(ldmos_xtor).enclosing(ncomp.inside(dualgate).inside(ldmos_xtor), 0.66.um, euclidian).polygons(0.001) +mdp12_l2 = ncomp.inside(dualgate).inside(ldmos_xtor).not_outside(dnwell.inside(dualgate).inside(ldmos_xtor)).not(dnwell.inside(dualgate).inside(ldmos_xtor)) +mdp12_l = mdp12_l1.or(mdp12_l2) +mdp12_l.output("MDP.12", "MDP.12 : Min DNWELL enclose Nplus guard ring (NCOMP). : 0.66µm") +mdp12_l1.forget +mdp12_l2.forget +mdp12_l.forget + +# rule MDP.13 is not a DRC check + +# Rule MDP.13a: Max single finger width. is 50µm +logger.info("Executing rule MDP.13a") +mdp13a_l1 = poly2.and(pcomp).not(mvpsd).inside(dualgate).inside(ldmos_xtor).edges.with_length(50.001.um,nil).extended(0, 0, 0.001, 0.001) +mdp13a_l1.output("MDP.13a", "MDP.13a : Max single finger width. : 50µm") +mdp13a_l1.forget + +# Rule MDP.13b: Layout shall have alternative source & drain. +logger.info("Executing rule MDP.13b") +mdp13b_l1 = ldpmos.not_interacting(mdp_source,1,1).or(ldpmos.not_interacting(mvpsd,1,1)).or(mdp_source.interacting(mvpsd)) +mdp13b_l1.output("MDP.13b", "MDP.13b : Layout shall have alternative source & drain.") +mdp13b_l1.forget + +mdp_13c_source_side = ldpmos.interacting(mdp_source.interacting(ldpmos, 2, 2).or(mdp_source.interacting(ncomp.interacting(mdp_source, 2, 2)))) +# Rule MDP.13c: Both sides of the transistor shall be terminated by source. +logger.info("Executing rule MDP.13c") +mdp13c_l1 = mvpsd.covering(pcomp.not_interacting(poly2)).interacting(pcomp, 2, 2).interacting(mdp_13c_source_side) +mdp13c_l1.output("MDP.13c", "MDP.13c : Both sides of the transistor shall be terminated by source.") +mdp13c_l1.forget + +mdp_13c_source_side.forget + +# rule MDP.14 is not a DRC check + +# Rule MDP.15: Min DNWELL enclosing MVPSD to any DNWELL spacing. is 6µm +logger.info("Executing rule MDP.15") +mdp15_l1 = dnwell.separation(dnwell.covering(mvpsd).inside(dualgate).inside(ldmos_xtor), 6.um, euclidian).polygons(0.001) +mdp15_l1.output("MDP.15", "MDP.15 : Min DNWELL enclosing MVPSD to any DNWELL spacing. : 6µm") +mdp15_l1.forget + +# Rule MDP.16a: Min LDPMOS drain COMP width. is 0.22µm +logger.info("Executing rule MDP.16a") +mdp16a_l1 = comp.inside(mvpsd).inside(dualgate).inside(ldmos_xtor).width(0.22.um, euclidian).polygons(0.001) +mdp16a_l1.output("MDP.16a", "MDP.16a : Min LDPMOS drain COMP width. : 0.22µm") +mdp16a_l1.forget + +# Rule MDP.16b: Min LDPMOS drain COMP enclose contact. is 0µm +logger.info("Executing rule MDP.16b") +mdp16b_l1 = contact.interacting(pcomp.inside(mvpsd).inside(dualgate).inside(ldmos_xtor)).not_inside(pcomp.inside(mvpsd)) +mdp16b_l1.output("MDP.16b", "MDP.16b : Min LDPMOS drain COMP enclose contact. : 0µm") +mdp16b_l1.forget + +mdp17_a1 = mvpsd.inside(dnwell).inside(ldmos_xtor) +mdp17_a2 = ncomp.outside(dnwell).outside(nwell) +# Rule MDP.17a: For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um. +logger.info("Executing rule MDP.17a") +mdp17a_l1 = mdp17_a1.separation(mdp17_a2,transparent,40.um).polygons(0.001).not_interacting(ncomp.and(dnwell).holes) +mdp17a_l1.output("MDP.17a", "MDP.17a : For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um.") +mdp17a_l1.forget + +mdp17_a1.forget + +mdp17_a2.forget + +# Rule MDP.17c: DNWELL guard ring shall have NCOMP tab to be connected to highest potential +logger.info("Executing rule MDP.17c") +mdp17c_l1 = dnwell.with_holes.not_covering(ncomp) +mdp17c_l1.output("MDP.17c", "MDP.17c : DNWELL guard ring shall have NCOMP tab to be connected to highest potential") +mdp17c_l1.forget + +#================================================ +#--------------------YMTP_MK--------------------- +#================================================ + +# Rule Y.NW.2b_3.3V: Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. is 1µm +logger.info("Executing rule Y.NW.2b_3.3V") +ynw2b_l1 = nwell.outside(dnwell).inside(ymtp_mk).space(1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ynw2b_l1.output("Y.NW.2b_3.3V", "Y.NW.2b_3.3V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm") +ynw2b_l1.forget + +# Rule Y.NW.2b_5V: Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. is 1µm +logger.info("Executing rule Y.NW.2b_5V") +ynw2b_l1 = nwell.outside(dnwell).inside(ymtp_mk).space(1.um, euclidian).polygons(0.001).overlapping(dualgate) +ynw2b_l1.output("Y.NW.2b_5V", "Y.NW.2b_5V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm") +ynw2b_l1.forget + +# rule Y.DF.4d_3.3V is not a DRC check + +# rule Y.DF.4d_5V is not a DRC check + +# Rule Y.DF.6_5V: Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. is 0.15µm +logger.info("Executing rule Y.DF.6_5V") +ydf6_l1 = comp.not(otp_mk).inside(ymtp_mk).enclosing(poly2.inside(ymtp_mk), 0.15.um, euclidian).polygons(0.001).overlapping(dualgate) +ydf6_l1.output("Y.DF.6_5V", "Y.DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. : 0.15µm") +ydf6_l1.forget + +# Rule Y.DF.16_3.3V: Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). is 0.27µm +logger.info("Executing rule Y.DF.16_3.3V") +ydf16_l1 = ncomp.outside(nwell).outside(dnwell).separation(nwell.outside(dnwell), 0.27.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ydf16_l1.output("Y.DF.16_3.3V", "Y.DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.27µm") +ydf16_l1.forget + +# Rule Y.DF.16_5V: Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). is 0.23µm +logger.info("Executing rule Y.DF.16_5V") +ydf16_l1 = ncomp.outside(nwell).outside(dnwell).separation(nwell.outside(dnwell), 0.23.um, euclidian).polygons(0.001).overlapping(dualgate) +ydf16_l1.output("Y.DF.16_5V", "Y.DF.16_5V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.23µm") +ydf16_l1.forget + +# Rule Y.PL.1_3.3V: Interconnect Width (inside YMTP_MK). is 0.13µm +logger.info("Executing rule Y.PL.1_3.3V") +ypl1_l1 = poly2.outside(plfuse).and(ymtp_mk).width(0.13.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ypl1_l1.output("Y.PL.1_3.3V", "Y.PL.1_3.3V : Interconnect Width (inside YMTP_MK). : 0.13µm") +ypl1_l1.forget + +# Rule Y.PL.1_5V: Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V. +logger.info("Executing rule Y.PL.1_5V") +ypl1_l1 = poly2.outside(plfuse).and(ymtp_mk).overlapping(dualgate) +ypl1_l1.output("Y.PL.1_5V", "Y.PL.1_5V : Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V.") +ypl1_l1.forget + +# Rule Y.PL.2_3.3V: Gate Width (Channel Length) (inside YMTP_MK). is 0.13µm +logger.info("Executing rule Y.PL.2_3.3V") +ypl2_l1 = poly2.edges.and(tgate.edges).not(otp_mk).and(ymtp_mk).width(0.13.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ypl2_l1.output("Y.PL.2_3.3V", "Y.PL.2_3.3V : Gate Width (Channel Length) (inside YMTP_MK). : 0.13µm") +ypl2_l1.forget + +# Rule Y.PL.2_5V: Gate Width (Channel Length) (inside YMTP_MK). is 0.47µm +logger.info("Executing rule Y.PL.2_5V") +ypl2_l1 = poly2.edges.and(tgate.edges).not(otp_mk).and(ymtp_mk).width(0.47.um, euclidian).polygons(0.001).overlapping(dualgate) +ypl2_l1.output("Y.PL.2_5V", "Y.PL.2_5V : Gate Width (Channel Length) (inside YMTP_MK). : 0.47µm") +ypl2_l1.forget + +# Rule Y.PL.4_5V: Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). is 0.16µm +logger.info("Executing rule Y.PL.4_5V") +ypl4_l1 = poly2.and(ymtp_mk).enclosing(comp.and(ymtp_mk), 0.16.um, euclidian).polygons(0.001).overlapping(dualgate) +ypl4_l1.output("Y.PL.4_5V", "Y.PL.4_5V : Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). : 0.16µm") +ypl4_l1.forget + +# Rule Y.PL.5a_3.3V: Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). is 0.04µm +logger.info("Executing rule Y.PL.5a_3.3V") +ypl5a_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.04.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ypl5a_l1.output("Y.PL.5a_3.3V", "Y.PL.5a_3.3V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.04µm") +ypl5a_l1.forget + +# Rule Y.PL.5a_5V: Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). is 0.2µm +logger.info("Executing rule Y.PL.5a_5V") +ypl5a_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.2.um, euclidian).polygons(0.001).overlapping(dualgate) +ypl5a_l1.output("Y.PL.5a_5V", "Y.PL.5a_5V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.2µm") +ypl5a_l1.forget + +# Rule Y.PL.5b_3.3V: Space from field Poly2 to related COMP (inside YMTP_MK). is 0.04µm +logger.info("Executing rule Y.PL.5b_3.3V") +ypl5b_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.04.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ypl5b_l1.output("Y.PL.5b_3.3V", "Y.PL.5b_3.3V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.04µm") +ypl5b_l1.forget + +# Rule Y.PL.5b_5V: Space from field Poly2 to related COMP (inside YMTP_MK). is 0.2µm +logger.info("Executing rule Y.PL.5b_5V") +ypl5b_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.2.um, euclidian).polygons(0.001).overlapping(dualgate) +ypl5b_l1.output("Y.PL.5b_5V", "Y.PL.5b_5V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.2µm") +ypl5b_l1.forget + +# rule Y.PL.6_3.3V is not a DRC check + +# rule Y.PL.6_5V is not a DRC check + +# rule Y.LU.3_3.3V is not yet implemented + +# rule Y.LU.3_5V is not yet implemented + +#================================================ +#--------------------5V SRAM--------------------- +#================================================ + +# Rule S.DF.4c_MV: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.45µm +logger.info("Executing rule S.DF.4c_MV") +sdf4c_l1 = nwell.outside(dnwell).inside(sramcore).enclosing(pcomp.outside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001) +sdf4c_l2 = pcomp.outside(dnwell).inside(sramcore).not_outside(nwell.outside(dnwell).inside(sramcore)).not(nwell.outside(dnwell).inside(sramcore)) +sdf4c_l = sdf4c_l1.or(sdf4c_l2).overlapping(v5_xtor).overlapping(dualgate) +sdf4c_l.output("S.DF.4c_MV", "S.DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.45µm") +sdf4c_l1.forget +sdf4c_l2.forget +sdf4c_l.forget + +# Rule S.DF.6_MV: Min. COMP extend beyond gate (it also means source/drain overhang). is 0.32µm +logger.info("Executing rule S.DF.6_MV") +sdf6_l1 = comp.inside(sramcore).enclosing(poly2.inside(sramcore), 0.32.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) +sdf6_l1.output("S.DF.6_MV", "S.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.32µm") +sdf6_l1.forget + +# Rule S.DF.7_MV: Min. (LVPWELL Spacer to PCOMP) inside DNWELL. is 0.45µm +logger.info("Executing rule S.DF.7_MV") +sdf7_l1 = pcomp.inside(dnwell).inside(sramcore).separation(lvpwell.inside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) +sdf7_l1.output("S.DF.7_MV", "S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.45µm") +sdf7_l1.forget + +# Rule S.DF.8_MV: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.45µm +logger.info("Executing rule S.DF.8_MV") +sdf8_l1 = lvpwell.inside(dnwell).inside(sramcore).enclosing(ncomp.inside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001) +sdf8_l2 = ncomp.inside(dnwell).inside(sramcore).not_outside(lvpwell.inside(dnwell).inside(sramcore)).not(lvpwell.inside(dnwell).inside(sramcore)) +sdf8_l = sdf8_l1.or(sdf8_l2).overlapping(v5_xtor).overlapping(dualgate) +sdf8_l.output("S.DF.8_MV", "S.DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.45µm") +sdf8_l1.forget +sdf8_l2.forget +sdf8_l.forget + +# Rule S.DF.16_MV: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.45µm +logger.info("Executing rule S.DF.16_MV") +sdf16_l1 = ncomp.outside(nwell).outside(dnwell).inside(sramcore).separation(nwell.outside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) +sdf16_l1.output("S.DF.16_MV", "S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.45µm") +sdf16_l1.forget + +# Rule S.PL.5a_MV: Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. is 0.12µm +logger.info("Executing rule S.PL.5a_MV") +spl5a_l1 = poly2.inside(sramcore).separation(comp.inside(sramcore), 0.12.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) +spl5a_l1.output("S.PL.5a_MV", "S.PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.12µm") +spl5a_l1.forget + +# Rule S.PL.5b_MV: Space from field Poly2 to related COMP. is 0.12µm +logger.info("Executing rule S.PL.5b_MV") +spl5b_l1 = poly2.inside(sramcore).separation(comp.inside(sramcore), 0.12.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) +spl5b_l1.output("S.PL.5b_MV", "S.PL.5b_MV : Space from field Poly2 to related COMP. : 0.12µm") +spl5b_l1.forget + +# Rule S.CO.4_MV: COMP overlap of contact. is 0.04µm +logger.info("Executing rule S.CO.4_MV") +sco4_l1 = comp.inside(sramcore).and(v5_xtor).enclosing(contact.inside(sramcore).and(v5_xtor), 0.04.um, euclidian).polygons(0.001) +sco4_l2 = contact.inside(sramcore).and(v5_xtor).not_outside(comp.inside(sramcore).and(v5_xtor)).not(comp.inside(sramcore).and(v5_xtor)) +sco4_l = sco4_l1.or(sco4_l2) +sco4_l.output("S.CO.4_MV", "S.CO.4_MV : COMP overlap of contact. : 0.04µm") +sco4_l1.forget +sco4_l2.forget +sco4_l.forget + +#================================================ +#-------------------3.3V SRAM-------------------- +#================================================ + +# Rule S.DF.4c_LV: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.4µm +logger.info("Executing rule S.DF.4c_LV") +sdf4c_l1 = nwell.outside(dnwell).inside(sramcore).enclosing(pcomp.outside(dnwell).inside(sramcore), 0.4.um, euclidian).polygons(0.001) +sdf4c_l2 = pcomp.outside(dnwell).inside(sramcore).not_outside(nwell.outside(dnwell).inside(sramcore)).not(nwell.outside(dnwell).inside(sramcore)) +sdf4c_l = sdf4c_l1.or(sdf4c_l2).not_interacting(v5_xtor).not_interacting(dualgate) +sdf4c_l.output("S.DF.4c_LV", "S.DF.4c_LV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.4µm") +sdf4c_l1.forget +sdf4c_l2.forget +sdf4c_l.forget + +# Rule S.DF.16_LV: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.4µm +logger.info("Executing rule S.DF.16_LV") +sdf16_l1 = ncomp.outside(nwell).outside(dnwell).inside(sramcore).separation(nwell.outside(dnwell).inside(sramcore), 0.4.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +sdf16_l1.output("S.DF.16_LV", "S.DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.4µm") +sdf16_l1.forget + +# Rule S.CO.3_LV: Poly2 overlap of contact. is 0.04µm +logger.info("Executing rule S.CO.3_LV") +sco3_l1 = poly2.inside(sramcore).enclosing(contact.inside(sramcore), 0.04.um, euclidian).polygons(0.001) +sco3_l2 = contact.inside(sramcore).not_outside(poly2.inside(sramcore)).not(poly2.inside(sramcore)) +sco3_l = sco3_l1.or(sco3_l2).not_interacting(v5_xtor).not_interacting(dualgate) +sco3_l.output("S.CO.3_LV", "S.CO.3_LV : Poly2 overlap of contact. : 0.04µm") +sco3_l1.forget +sco3_l2.forget +sco3_l.forget + +# Rule S.CO.4_LV: COMP overlap of contact. is 0.03µm +logger.info("Executing rule S.CO.4_LV") +sco4_l1 = comp.inside(sramcore).enclosing(contact.inside(sramcore), 0.03.um, euclidian).polygons(0.001) +sco4_l2 = contact.inside(sramcore).not_outside(comp.inside(sramcore)).not(comp.inside(sramcore)) +sco4_l = sco4_l1.or(sco4_l2).not_interacting(v5_xtor).not_interacting(dualgate) +sco4_l.output("S.CO.4_LV", "S.CO.4_LV : COMP overlap of contact. : 0.03µm") +sco4_l1.forget +sco4_l2.forget +sco4_l.forget + +# Rule S.CO.6_ii_LV: (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap +logger.info("Executing rule S.CO.6_ii_LV") +sco6_l1 = metal1.and(sramcore).enclosing(contact.inside(sramcore), 0.02.um, euclidian).polygons(0.001).or(contact.inside(sramcore).not_inside(metal1.inside(sramcore)).not(metal1.inside(sramcore))).not_interacting(v5_xtor).not_interacting(dualgate) +sco6_l1.output("S.CO.6_ii_LV", "S.CO.6_ii_LV : (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap") +sco6_l1.forget + +# Rule S.M1.1_LV: min. metal1 width is 0.22µm +logger.info("Executing rule S.M1.1_LV") +sm11_l1 = metal1.and(sramcore).width(0.22.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +sm11_l1.output("S.M1.1_LV", "S.M1.1_LV : min. metal1 width : 0.22µm") +sm11_l1.forget + +#================================================ +#-----------------GEOMETRY RULES----------------- +#================================================ + +if OFFGRID +logger.info("OFFGRID-ANGLES section") + +logger.info("Executing rule comp_OFFGRID") +comp.ongrid(0.005).output("comp_OFFGRID", "OFFGRID : OFFGRID vertex on comp") +comp.with_angle(0 .. 45).output("comp_angle", "ACUTE : non 45 degree angle comp") + +logger.info("Executing rule dnwell_OFFGRID") +dnwell.ongrid(0.005).output("dnwell_OFFGRID", "OFFGRID : OFFGRID vertex on dnwell") +dnwell.with_angle(0 .. 45).output("dnwell_angle", "ACUTE : non 45 degree angle dnwell") + +logger.info("Executing rule nwell_OFFGRID") +nwell.ongrid(0.005).output("nwell_OFFGRID", "OFFGRID : OFFGRID vertex on nwell") +nwell.with_angle(0 .. 45).output("nwell_angle", "ACUTE : non 45 degree angle nwell") + +logger.info("Executing rule lvpwell_OFFGRID") +lvpwell.ongrid(0.005).output("lvpwell_OFFGRID", "OFFGRID : OFFGRID vertex on lvpwell") +lvpwell.with_angle(0 .. 45).output("lvpwell_angle", "ACUTE : non 45 degree angle lvpwell") + +logger.info("Executing rule dualgate_OFFGRID") +dualgate.ongrid(0.005).output("dualgate_OFFGRID", "OFFGRID : OFFGRID vertex on dualgate") +dualgate.with_angle(0 .. 45).output("dualgate_angle", "ACUTE : non 45 degree angle dualgate") + +logger.info("Executing rule poly2_OFFGRID") +poly2.ongrid(0.005).output("poly2_OFFGRID", "OFFGRID : OFFGRID vertex on poly2") +poly2.with_angle(0 .. 45).output("poly2_angle", "ACUTE : non 45 degree angle poly2") + +logger.info("Executing rule nplus_OFFGRID") +nplus.ongrid(0.005).output("nplus_OFFGRID", "OFFGRID : OFFGRID vertex on nplus") +nplus.with_angle(0 .. 45).output("nplus_angle", "ACUTE : non 45 degree angle nplus") + +logger.info("Executing rule pplus_OFFGRID") +pplus.ongrid(0.005).output("pplus_OFFGRID", "OFFGRID : OFFGRID vertex on pplus") +pplus.with_angle(0 .. 45).output("pplus_angle", "ACUTE : non 45 degree angle pplus") + +logger.info("Executing rule sab_OFFGRID") +sab.ongrid(0.005).output("sab_OFFGRID", "OFFGRID : OFFGRID vertex on sab") +sab.with_angle(0 .. 45).output("sab_angle", "ACUTE : non 45 degree angle sab") + +logger.info("Executing rule esd_OFFGRID") +esd.ongrid(0.005).output("esd_OFFGRID", "OFFGRID : OFFGRID vertex on esd") +esd.with_angle(0 .. 45).output("esd_angle", "ACUTE : non 45 degree angle esd") + +logger.info("Executing rule contact_OFFGRID") +contact.ongrid(0.005).output("contact_OFFGRID", "OFFGRID : OFFGRID vertex on contact") +contact.with_angle(0 .. 45).output("contact_angle", "ACUTE : non 45 degree angle contact") + +logger.info("Executing rule metal1_OFFGRID") +metal1.ongrid(0.005).output("metal1_OFFGRID", "OFFGRID : OFFGRID vertex on metal1") +metal1.with_angle(0 .. 45).output("metal1_angle", "ACUTE : non 45 degree angle metal1") + +logger.info("Executing rule via1_OFFGRID") +via1.ongrid(0.005).output("via1_OFFGRID", "OFFGRID : OFFGRID vertex on via1") +via1.with_angle(0 .. 45).output("via1_angle", "ACUTE : non 45 degree angle via1") + +logger.info("Executing rule metal2_OFFGRID") +metal2.ongrid(0.005).output("metal2_OFFGRID", "OFFGRID : OFFGRID vertex on metal2") +metal2.with_angle(0 .. 45).output("metal2_angle", "ACUTE : non 45 degree angle metal2") + +logger.info("Executing rule via2_OFFGRID") +via2.ongrid(0.005).output("via2_OFFGRID", "OFFGRID : OFFGRID vertex on via2") +via2.with_angle(0 .. 45).output("via2_angle", "ACUTE : non 45 degree angle via2") + +logger.info("Executing rule metal3_OFFGRID") +metal3.ongrid(0.005).output("metal3_OFFGRID", "OFFGRID : OFFGRID vertex on metal3") +metal3.with_angle(0 .. 45).output("metal3_angle", "ACUTE : non 45 degree angle metal3") + +logger.info("Executing rule via3_OFFGRID") +via3.ongrid(0.005).output("via3_OFFGRID", "OFFGRID : OFFGRID vertex on via3") +via3.with_angle(0 .. 45).output("via3_angle", "ACUTE : non 45 degree angle via3") + +logger.info("Executing rule metal4_OFFGRID") +metal4.ongrid(0.005).output("metal4_OFFGRID", "OFFGRID : OFFGRID vertex on metal4") +metal4.with_angle(0 .. 45).output("metal4_angle", "ACUTE : non 45 degree angle metal4") + +logger.info("Executing rule via4_OFFGRID") +via4.ongrid(0.005).output("via4_OFFGRID", "OFFGRID : OFFGRID vertex on via4") +via4.with_angle(0 .. 45).output("via4_angle", "ACUTE : non 45 degree angle via4") + +logger.info("Executing rule metal5_OFFGRID") +metal5.ongrid(0.005).output("metal5_OFFGRID", "OFFGRID : OFFGRID vertex on metal5") +metal5.with_angle(0 .. 45).output("metal5_angle", "ACUTE : non 45 degree angle metal5") + +logger.info("Executing rule via5_OFFGRID") +via5.ongrid(0.005).output("via5_OFFGRID", "OFFGRID : OFFGRID vertex on via5") +via5.with_angle(0 .. 45).output("via5_angle", "ACUTE : non 45 degree angle via5") + +logger.info("Executing rule metaltop_OFFGRID") +metaltop.ongrid(0.005).output("metaltop_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop") +metaltop.with_angle(0 .. 45).output("metaltop_angle", "ACUTE : non 45 degree angle metaltop") + +logger.info("Executing rule pad_OFFGRID") +pad.ongrid(0.005).output("pad_OFFGRID", "OFFGRID : OFFGRID vertex on pad") +pad.with_angle(0 .. 45).output("pad_angle", "ACUTE : non 45 degree angle pad") + +logger.info("Executing rule resistor_OFFGRID") +resistor.ongrid(0.005).output("resistor_OFFGRID", "OFFGRID : OFFGRID vertex on resistor") +resistor.with_angle(0 .. 45).output("resistor_angle", "ACUTE : non 45 degree angle resistor") + +logger.info("Executing rule fhres_OFFGRID") +fhres.ongrid(0.005).output("fhres_OFFGRID", "OFFGRID : OFFGRID vertex on fhres") +fhres.with_angle(0 .. 45).output("fhres_angle", "ACUTE : non 45 degree angle fhres") + +logger.info("Executing rule fusetop_OFFGRID") +fusetop.ongrid(0.005).output("fusetop_OFFGRID", "OFFGRID : OFFGRID vertex on fusetop") +fusetop.with_angle(0 .. 45).output("fusetop_angle", "ACUTE : non 45 degree angle fusetop") + +logger.info("Executing rule fusewindow_d_OFFGRID") +fusewindow_d.ongrid(0.005).output("fusewindow_d_OFFGRID", "OFFGRID : OFFGRID vertex on fusewindow_d") +fusewindow_d.with_angle(0 .. 45).output("fusewindow_d_angle", "ACUTE : non 45 degree angle fusewindow_d") + +logger.info("Executing rule polyfuse_OFFGRID") +polyfuse.ongrid(0.005).output("polyfuse_OFFGRID", "OFFGRID : OFFGRID vertex on polyfuse") +polyfuse.with_angle(0 .. 45).output("polyfuse_angle", "ACUTE : non 45 degree angle polyfuse") + +logger.info("Executing rule mvsd_OFFGRID") +mvsd.ongrid(0.005).output("mvsd_OFFGRID", "OFFGRID : OFFGRID vertex on mvsd") +mvsd.with_angle(0 .. 45).output("mvsd_angle", "ACUTE : non 45 degree angle mvsd") + +logger.info("Executing rule mvpsd_OFFGRID") +mvpsd.ongrid(0.005).output("mvpsd_OFFGRID", "OFFGRID : OFFGRID vertex on mvpsd") +mvpsd.with_angle(0 .. 45).output("mvpsd_angle", "ACUTE : non 45 degree angle mvpsd") + +logger.info("Executing rule nat_OFFGRID") +nat.ongrid(0.005).output("nat_OFFGRID", "OFFGRID : OFFGRID vertex on nat") +nat.with_angle(0 .. 45).output("nat_angle", "ACUTE : non 45 degree angle nat") + +logger.info("Executing rule comp_dummy_OFFGRID") +comp_dummy.ongrid(0.005).output("comp_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on comp_dummy") +comp_dummy.with_angle(0 .. 45).output("comp_dummy_angle", "ACUTE : non 45 degree angle comp_dummy") + +logger.info("Executing rule poly2_dummy_OFFGRID") +poly2_dummy.ongrid(0.005).output("poly2_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on poly2_dummy") +poly2_dummy.with_angle(0 .. 45).output("poly2_dummy_angle", "ACUTE : non 45 degree angle poly2_dummy") + +logger.info("Executing rule metal1_dummy_OFFGRID") +metal1_dummy.ongrid(0.005).output("metal1_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_dummy") +metal1_dummy.with_angle(0 .. 45).output("metal1_dummy_angle", "ACUTE : non 45 degree angle metal1_dummy") + +logger.info("Executing rule metal2_dummy_OFFGRID") +metal2_dummy.ongrid(0.005).output("metal2_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_dummy") +metal2_dummy.with_angle(0 .. 45).output("metal2_dummy_angle", "ACUTE : non 45 degree angle metal2_dummy") + +logger.info("Executing rule metal3_dummy_OFFGRID") +metal3_dummy.ongrid(0.005).output("metal3_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_dummy") +metal3_dummy.with_angle(0 .. 45).output("metal3_dummy_angle", "ACUTE : non 45 degree angle metal3_dummy") + +logger.info("Executing rule metal4_dummy_OFFGRID") +metal4_dummy.ongrid(0.005).output("metal4_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_dummy") +metal4_dummy.with_angle(0 .. 45).output("metal4_dummy_angle", "ACUTE : non 45 degree angle metal4_dummy") + +logger.info("Executing rule metal5_dummy_OFFGRID") +metal5_dummy.ongrid(0.005).output("metal5_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_dummy") +metal5_dummy.with_angle(0 .. 45).output("metal5_dummy_angle", "ACUTE : non 45 degree angle metal5_dummy") + +logger.info("Executing rule metaltop_dummy_OFFGRID") +metaltop_dummy.ongrid(0.005).output("metaltop_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop_dummy") +metaltop_dummy.with_angle(0 .. 45).output("metaltop_dummy_angle", "ACUTE : non 45 degree angle metaltop_dummy") + +logger.info("Executing rule comp_label_OFFGRID") +comp_label.ongrid(0.005).output("comp_label_OFFGRID", "OFFGRID : OFFGRID vertex on comp_label") +comp_label.with_angle(0 .. 45).output("comp_label_angle", "ACUTE : non 45 degree angle comp_label") + +logger.info("Executing rule poly2_label_OFFGRID") +poly2_label.ongrid(0.005).output("poly2_label_OFFGRID", "OFFGRID : OFFGRID vertex on poly2_label") +poly2_label.with_angle(0 .. 45).output("poly2_label_angle", "ACUTE : non 45 degree angle poly2_label") + +logger.info("Executing rule metal1_label_OFFGRID") +metal1_label.ongrid(0.005).output("metal1_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_label") +metal1_label.with_angle(0 .. 45).output("metal1_label_angle", "ACUTE : non 45 degree angle metal1_label") + +logger.info("Executing rule metal2_label_OFFGRID") +metal2_label.ongrid(0.005).output("metal2_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_label") +metal2_label.with_angle(0 .. 45).output("metal2_label_angle", "ACUTE : non 45 degree angle metal2_label") + +logger.info("Executing rule metal3_label_OFFGRID") +metal3_label.ongrid(0.005).output("metal3_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_label") +metal3_label.with_angle(0 .. 45).output("metal3_label_angle", "ACUTE : non 45 degree angle metal3_label") + +logger.info("Executing rule metal4_label_OFFGRID") +metal4_label.ongrid(0.005).output("metal4_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_label") +metal4_label.with_angle(0 .. 45).output("metal4_label_angle", "ACUTE : non 45 degree angle metal4_label") + +logger.info("Executing rule metal5_label_OFFGRID") +metal5_label.ongrid(0.005).output("metal5_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_label") +metal5_label.with_angle(0 .. 45).output("metal5_label_angle", "ACUTE : non 45 degree angle metal5_label") + +logger.info("Executing rule metaltop_label_OFFGRID") +metaltop_label.ongrid(0.005).output("metaltop_label_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop_label") +metaltop_label.with_angle(0 .. 45).output("metaltop_label_angle", "ACUTE : non 45 degree angle metaltop_label") + +logger.info("Executing rule metal1_slot_OFFGRID") +metal1_slot.ongrid(0.005).output("metal1_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_slot") +metal1_slot.with_angle(0 .. 45).output("metal1_slot_angle", "ACUTE : non 45 degree angle metal1_slot") + +logger.info("Executing rule metal2_slot_OFFGRID") +metal2_slot.ongrid(0.005).output("metal2_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_slot") +metal2_slot.with_angle(0 .. 45).output("metal2_slot_angle", "ACUTE : non 45 degree angle metal2_slot") + +logger.info("Executing rule metal3_slot_OFFGRID") +metal3_slot.ongrid(0.005).output("metal3_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_slot") +metal3_slot.with_angle(0 .. 45).output("metal3_slot_angle", "ACUTE : non 45 degree angle metal3_slot") + +logger.info("Executing rule metal4_slot_OFFGRID") +metal4_slot.ongrid(0.005).output("metal4_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_slot") +metal4_slot.with_angle(0 .. 45).output("metal4_slot_angle", "ACUTE : non 45 degree angle metal4_slot") + +logger.info("Executing rule metal5_slot_OFFGRID") +metal5_slot.ongrid(0.005).output("metal5_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_slot") +metal5_slot.with_angle(0 .. 45).output("metal5_slot_angle", "ACUTE : non 45 degree angle metal5_slot") + +logger.info("Executing rule metaltop_slot_OFFGRID") +metaltop_slot.ongrid(0.005).output("metaltop_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop_slot") +metaltop_slot.with_angle(0 .. 45).output("metaltop_slot_angle", "ACUTE : non 45 degree angle metaltop_slot") + +logger.info("Executing rule ubmpperi_OFFGRID") +ubmpperi.ongrid(0.005).output("ubmpperi_OFFGRID", "OFFGRID : OFFGRID vertex on ubmpperi") +ubmpperi.with_angle(0 .. 45).output("ubmpperi_angle", "ACUTE : non 45 degree angle ubmpperi") + +logger.info("Executing rule ubmparray_OFFGRID") +ubmparray.ongrid(0.005).output("ubmparray_OFFGRID", "OFFGRID : OFFGRID vertex on ubmparray") +ubmparray.with_angle(0 .. 45).output("ubmparray_angle", "ACUTE : non 45 degree angle ubmparray") + +logger.info("Executing rule ubmeplate_OFFGRID") +ubmeplate.ongrid(0.005).output("ubmeplate_OFFGRID", "OFFGRID : OFFGRID vertex on ubmeplate") +ubmeplate.with_angle(0 .. 45).output("ubmeplate_angle", "ACUTE : non 45 degree angle ubmeplate") + +logger.info("Executing rule schottky_diode_OFFGRID") +schottky_diode.ongrid(0.005).output("schottky_diode_OFFGRID", "OFFGRID : OFFGRID vertex on schottky_diode") +schottky_diode.with_angle(0 .. 45).output("schottky_diode_angle", "ACUTE : non 45 degree angle schottky_diode") + +logger.info("Executing rule zener_OFFGRID") +zener.ongrid(0.005).output("zener_OFFGRID", "OFFGRID : OFFGRID vertex on zener") +zener.with_angle(0 .. 45).output("zener_angle", "ACUTE : non 45 degree angle zener") + +logger.info("Executing rule res_mk_OFFGRID") +res_mk.ongrid(0.005).output("res_mk_OFFGRID", "OFFGRID : OFFGRID vertex on res_mk") +res_mk.with_angle(0 .. 45).output("res_mk_angle", "ACUTE : non 45 degree angle res_mk") + +logger.info("Executing rule opc_drc_OFFGRID") +opc_drc.ongrid(0.005).output("opc_drc_OFFGRID", "OFFGRID : OFFGRID vertex on opc_drc") +opc_drc.with_angle(0 .. 45).output("opc_drc_angle", "ACUTE : non 45 degree angle opc_drc") + +logger.info("Executing rule ndmy_OFFGRID") +ndmy.ongrid(0.005).output("ndmy_OFFGRID", "OFFGRID : OFFGRID vertex on ndmy") +ndmy.with_angle(0 .. 45).output("ndmy_angle", "ACUTE : non 45 degree angle ndmy") + +logger.info("Executing rule pmndmy_OFFGRID") +pmndmy.ongrid(0.005).output("pmndmy_OFFGRID", "OFFGRID : OFFGRID vertex on pmndmy") +pmndmy.with_angle(0 .. 45).output("pmndmy_angle", "ACUTE : non 45 degree angle pmndmy") + +logger.info("Executing rule v5_xtor_OFFGRID") +v5_xtor.ongrid(0.005).output("v5_xtor_OFFGRID", "OFFGRID : OFFGRID vertex on v5_xtor") +v5_xtor.with_angle(0 .. 45).output("v5_xtor_angle", "ACUTE : non 45 degree angle v5_xtor") + +logger.info("Executing rule cap_mk_OFFGRID") +cap_mk.ongrid(0.005).output("cap_mk_OFFGRID", "OFFGRID : OFFGRID vertex on cap_mk") +cap_mk.with_angle(0 .. 45).output("cap_mk_angle", "ACUTE : non 45 degree angle cap_mk") + +logger.info("Executing rule mos_cap_mk_OFFGRID") +mos_cap_mk.ongrid(0.005).output("mos_cap_mk_OFFGRID", "OFFGRID : OFFGRID vertex on mos_cap_mk") +mos_cap_mk.with_angle(0 .. 45).output("mos_cap_mk_angle", "ACUTE : non 45 degree angle mos_cap_mk") + +logger.info("Executing rule ind_mk_OFFGRID") +ind_mk.ongrid(0.005).output("ind_mk_OFFGRID", "OFFGRID : OFFGRID vertex on ind_mk") +ind_mk.with_angle(0 .. 45).output("ind_mk_angle", "ACUTE : non 45 degree angle ind_mk") + +logger.info("Executing rule diode_mk_OFFGRID") +diode_mk.ongrid(0.005).output("diode_mk_OFFGRID", "OFFGRID : OFFGRID vertex on diode_mk") +diode_mk.with_angle(0 .. 45).output("diode_mk_angle", "ACUTE : non 45 degree angle diode_mk") + +logger.info("Executing rule drc_bjt_OFFGRID") +drc_bjt.ongrid(0.005).output("drc_bjt_OFFGRID", "OFFGRID : OFFGRID vertex on drc_bjt") +drc_bjt.with_angle(0 .. 45).output("drc_bjt_angle", "ACUTE : non 45 degree angle drc_bjt") + +logger.info("Executing rule lvs_bjt_OFFGRID") +lvs_bjt.ongrid(0.005).output("lvs_bjt_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_bjt") +lvs_bjt.with_angle(0 .. 45).output("lvs_bjt_angle", "ACUTE : non 45 degree angle lvs_bjt") + +logger.info("Executing rule mim_l_mk_OFFGRID") +mim_l_mk.ongrid(0.005).output("mim_l_mk_OFFGRID", "OFFGRID : OFFGRID vertex on mim_l_mk") +mim_l_mk.with_angle(0 .. 45).output("mim_l_mk_angle", "ACUTE : non 45 degree angle mim_l_mk") + +logger.info("Executing rule latchup_mk_OFFGRID") +latchup_mk.ongrid(0.005).output("latchup_mk_OFFGRID", "OFFGRID : OFFGRID vertex on latchup_mk") +latchup_mk.with_angle(0 .. 45).output("latchup_mk_angle", "ACUTE : non 45 degree angle latchup_mk") + +logger.info("Executing rule guard_ring_mk_OFFGRID") +guard_ring_mk.ongrid(0.005).output("guard_ring_mk_OFFGRID", "OFFGRID : OFFGRID vertex on guard_ring_mk") +guard_ring_mk.with_angle(0 .. 45).output("guard_ring_mk_angle", "ACUTE : non 45 degree angle guard_ring_mk") + +logger.info("Executing rule otp_mk_OFFGRID") +otp_mk.ongrid(0.005).output("otp_mk_OFFGRID", "OFFGRID : OFFGRID vertex on otp_mk") +otp_mk.with_angle(0 .. 45).output("otp_mk_angle", "ACUTE : non 45 degree angle otp_mk") + +logger.info("Executing rule mtpmark_OFFGRID") +mtpmark.ongrid(0.005).output("mtpmark_OFFGRID", "OFFGRID : OFFGRID vertex on mtpmark") +mtpmark.with_angle(0 .. 45).output("mtpmark_angle", "ACUTE : non 45 degree angle mtpmark") + +logger.info("Executing rule neo_ee_mk_OFFGRID") +neo_ee_mk.ongrid(0.005).output("neo_ee_mk_OFFGRID", "OFFGRID : OFFGRID vertex on neo_ee_mk") +neo_ee_mk.with_angle(0 .. 45).output("neo_ee_mk_angle", "ACUTE : non 45 degree angle neo_ee_mk") + +logger.info("Executing rule sramcore_OFFGRID") +sramcore.ongrid(0.005).output("sramcore_OFFGRID", "OFFGRID : OFFGRID vertex on sramcore") +sramcore.with_angle(0 .. 45).output("sramcore_angle", "ACUTE : non 45 degree angle sramcore") + +logger.info("Executing rule lvs_rf_OFFGRID") +lvs_rf.ongrid(0.005).output("lvs_rf_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_rf") +lvs_rf.with_angle(0 .. 45).output("lvs_rf_angle", "ACUTE : non 45 degree angle lvs_rf") + +logger.info("Executing rule lvs_drain_OFFGRID") +lvs_drain.ongrid(0.005).output("lvs_drain_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_drain") +lvs_drain.with_angle(0 .. 45).output("lvs_drain_angle", "ACUTE : non 45 degree angle lvs_drain") + +logger.info("Executing rule ind_mk_OFFGRID") +ind_mk.ongrid(0.005).output("ind_mk_OFFGRID", "OFFGRID : OFFGRID vertex on ind_mk") +ind_mk.with_angle(0 .. 45).output("ind_mk_angle", "ACUTE : non 45 degree angle ind_mk") + +logger.info("Executing rule hvpolyrs_OFFGRID") +hvpolyrs.ongrid(0.005).output("hvpolyrs_OFFGRID", "OFFGRID : OFFGRID vertex on hvpolyrs") +hvpolyrs.with_angle(0 .. 45).output("hvpolyrs_angle", "ACUTE : non 45 degree angle hvpolyrs") + +logger.info("Executing rule lvs_io_OFFGRID") +lvs_io.ongrid(0.005).output("lvs_io_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_io") +lvs_io.with_angle(0 .. 45).output("lvs_io_angle", "ACUTE : non 45 degree angle lvs_io") + +logger.info("Executing rule probe_mk_OFFGRID") +probe_mk.ongrid(0.005).output("probe_mk_OFFGRID", "OFFGRID : OFFGRID vertex on probe_mk") +probe_mk.with_angle(0 .. 45).output("probe_mk_angle", "ACUTE : non 45 degree angle probe_mk") + +logger.info("Executing rule esd_mk_OFFGRID") +esd_mk.ongrid(0.005).output("esd_mk_OFFGRID", "OFFGRID : OFFGRID vertex on esd_mk") +esd_mk.with_angle(0 .. 45).output("esd_mk_angle", "ACUTE : non 45 degree angle esd_mk") + +logger.info("Executing rule lvs_source_OFFGRID") +lvs_source.ongrid(0.005).output("lvs_source_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_source") +lvs_source.with_angle(0 .. 45).output("lvs_source_angle", "ACUTE : non 45 degree angle lvs_source") + +logger.info("Executing rule well_diode_mk_OFFGRID") +well_diode_mk.ongrid(0.005).output("well_diode_mk_OFFGRID", "OFFGRID : OFFGRID vertex on well_diode_mk") +well_diode_mk.with_angle(0 .. 45).output("well_diode_mk_angle", "ACUTE : non 45 degree angle well_diode_mk") + +logger.info("Executing rule ldmos_xtor_OFFGRID") +ldmos_xtor.ongrid(0.005).output("ldmos_xtor_OFFGRID", "OFFGRID : OFFGRID vertex on ldmos_xtor") +ldmos_xtor.with_angle(0 .. 45).output("ldmos_xtor_angle", "ACUTE : non 45 degree angle ldmos_xtor") + +logger.info("Executing rule plfuse_OFFGRID") +plfuse.ongrid(0.005).output("plfuse_OFFGRID", "OFFGRID : OFFGRID vertex on plfuse") +plfuse.with_angle(0 .. 45).output("plfuse_angle", "ACUTE : non 45 degree angle plfuse") + +logger.info("Executing rule efuse_mk_OFFGRID") +efuse_mk.ongrid(0.005).output("efuse_mk_OFFGRID", "OFFGRID : OFFGRID vertex on efuse_mk") +efuse_mk.with_angle(0 .. 45).output("efuse_mk_angle", "ACUTE : non 45 degree angle efuse_mk") + +logger.info("Executing rule mcell_feol_mk_OFFGRID") +mcell_feol_mk.ongrid(0.005).output("mcell_feol_mk_OFFGRID", "OFFGRID : OFFGRID vertex on mcell_feol_mk") +mcell_feol_mk.with_angle(0 .. 45).output("mcell_feol_mk_angle", "ACUTE : non 45 degree angle mcell_feol_mk") + +logger.info("Executing rule ymtp_mk_OFFGRID") +ymtp_mk.ongrid(0.005).output("ymtp_mk_OFFGRID", "OFFGRID : OFFGRID vertex on ymtp_mk") +ymtp_mk.with_angle(0 .. 45).output("ymtp_mk_angle", "ACUTE : non 45 degree angle ymtp_mk") + +logger.info("Executing rule dev_wf_mk_OFFGRID") +dev_wf_mk.ongrid(0.005).output("dev_wf_mk_OFFGRID", "OFFGRID : OFFGRID vertex on dev_wf_mk") +dev_wf_mk.with_angle(0 .. 45).output("dev_wf_mk_angle", "ACUTE : non 45 degree angle dev_wf_mk") + +logger.info("Executing rule metal1_blk_OFFGRID") +metal1_blk.ongrid(0.005).output("metal1_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_blk") +metal1_blk.with_angle(0 .. 45).output("metal1_blk_angle", "ACUTE : non 45 degree angle metal1_blk") + +logger.info("Executing rule metal2_blk_OFFGRID") +metal2_blk.ongrid(0.005).output("metal2_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_blk") +metal2_blk.with_angle(0 .. 45).output("metal2_blk_angle", "ACUTE : non 45 degree angle metal2_blk") + +logger.info("Executing rule metal3_blk_OFFGRID") +metal3_blk.ongrid(0.005).output("metal3_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_blk") +metal3_blk.with_angle(0 .. 45).output("metal3_blk_angle", "ACUTE : non 45 degree angle metal3_blk") + +logger.info("Executing rule metal4_blk_OFFGRID") +metal4_blk.ongrid(0.005).output("metal4_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_blk") +metal4_blk.with_angle(0 .. 45).output("metal4_blk_angle", "ACUTE : non 45 degree angle metal4_blk") + +logger.info("Executing rule metal5_blk_OFFGRID") +metal5_blk.ongrid(0.005).output("metal5_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_blk") +metal5_blk.with_angle(0 .. 45).output("metal5_blk_angle", "ACUTE : non 45 degree angle metal5_blk") + +logger.info("Executing rule metalt_blk_OFFGRID") +metalt_blk.ongrid(0.005).output("metalt_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metalt_blk") +metalt_blk.with_angle(0 .. 45).output("metalt_blk_angle", "ACUTE : non 45 degree angle metalt_blk") + +logger.info("Executing rule pr_bndry_OFFGRID") +pr_bndry.ongrid(0.005).output("pr_bndry_OFFGRID", "OFFGRID : OFFGRID vertex on pr_bndry") +pr_bndry.with_angle(0 .. 45).output("pr_bndry_angle", "ACUTE : non 45 degree angle pr_bndry") + +logger.info("Executing rule mdiode_OFFGRID") +mdiode.ongrid(0.005).output("mdiode_OFFGRID", "OFFGRID : OFFGRID vertex on mdiode") +mdiode.with_angle(0 .. 45).output("mdiode_angle", "ACUTE : non 45 degree angle mdiode") + +logger.info("Executing rule metal1_res_OFFGRID") +metal1_res.ongrid(0.005).output("metal1_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_res") +metal1_res.with_angle(0 .. 45).output("metal1_res_angle", "ACUTE : non 45 degree angle metal1_res") + +logger.info("Executing rule metal2_res_OFFGRID") +metal2_res.ongrid(0.005).output("metal2_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_res") +metal2_res.with_angle(0 .. 45).output("metal2_res_angle", "ACUTE : non 45 degree angle metal2_res") + +logger.info("Executing rule metal3_res_OFFGRID") +metal3_res.ongrid(0.005).output("metal3_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_res") +metal3_res.with_angle(0 .. 45).output("metal3_res_angle", "ACUTE : non 45 degree angle metal3_res") + +logger.info("Executing rule metal4_res_OFFGRID") +metal4_res.ongrid(0.005).output("metal4_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_res") +metal4_res.with_angle(0 .. 45).output("metal4_res_angle", "ACUTE : non 45 degree angle metal4_res") + +logger.info("Executing rule metal5_res_OFFGRID") +metal5_res.ongrid(0.005).output("metal5_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_res") +metal5_res.with_angle(0 .. 45).output("metal5_res_angle", "ACUTE : non 45 degree angle metal5_res") + +logger.info("Executing rule metal6_res_OFFGRID") +metal6_res.ongrid(0.005).output("metal6_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal6_res") +metal6_res.with_angle(0 .. 45).output("metal6_res_angle", "ACUTE : non 45 degree angle metal6_res") + +logger.info("Executing rule border_OFFGRID") +border.ongrid(0.005).output("border_OFFGRID", "OFFGRID : OFFGRID vertex on border") +border.with_angle(0 .. 45).output("border_angle", "ACUTE : non 45 degree angle border") + +end #OFFGRID-ANGLES + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Total Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu_1.lym b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu_1.lym new file mode 100644 index 000000000..ce6cb1a1d --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu_1.lym @@ -0,0 +1,35 @@ + + + + + pymacros + + + + true + false + 0 + + false + + + python + + + +import sys +import os + +technology_macros_path = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, technology_macros_path) + +from cells import gf180mcu + +# Instantiate and register the library +gf180mcu() + +print("## gf180mcu PDK Pcells loaded.") +print(sys.path) + + + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu_antenna.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu_antenna.drc new file mode 100644 index 000000000..8e27e2214 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu_antenna.drc @@ -0,0 +1,503 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#=========================================================================================================================== +#------------------------------------------- GF 0.18 um MCU DRC RULE DECK -------------------------------------------------- +#=========================================================================================================================== + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#========================================= +#------------ FILE SETUP ----------------- +#========================================= + +# optionnal for a batch launch : klayout -b -r gf_018mcu_antenna.drc -rd input=design.gds -rd report=gf180_ant_drc.txt + +logger.info("Starting running GF180MCU Klayout antenna checks DRC runset on %s" % [$input]) + +if $input + source($input, $topcell) +end + +logger.info("Loading database to memory is complete.") + + +if $report + logger.info("GF180MCU Klayout antenna checks DRC runset output at: %s" % [$report]) + report("GF180 ANTENNA DRC runset", $report) +else + logger.info("GF180MCU Klayout antenna checks DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180mcu_antenna.lyrdb").path]) + report("GF180 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "gf180mcu_antenna.lyrdb")) +end + +if $thr + threads($thr) +else + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== HIER MODE === + deep + logger.info("flat mode is enabled.") + +end # run_mode + +#====================================================================================================== +#--------------------------------------- LAYER DEFINITIONS -------------------------------------------- +#====================================================================================================== + +comp = polygons(22, 0) +dualgate = polygons(55, 0) +poly2 = polygons(30, 0) +nplus = polygons(32, 0) +pplus = polygons(31, 0) +contact = polygons(33, 0) +metal1 = polygons(34, 0) +via1 = polygons(35, 0) +metal2 = polygons(36, 0) +via2 = polygons(38, 0) +metal3 = polygons(42, 0) +via3 = polygons(40, 0) +metal4 = polygons(46, 0) +via4 = polygons(41, 0) +metal5 = polygons(81, 0) +via5 = polygons(82, 0) +metaltop = polygons(53, 0) +fusetop = polygons(75, 0) + +#====================================================================================================== +#--------------------------------------- LAYER DERIVATIONS -------------------------------------------- +#====================================================================================================== + +tgate = poly2 & comp +thin_gate = tgate.not(dualgate) +thick_gate = tgate.and(dualgate) +diode = nplus & comp + +# === LAYOUT EXTENT === +CHIP = extent.sized(0.0) + +#======================================================================================= +#------------------------------------- SWITCHES ---------------------------------------- +#======================================================================================= + +logger.info("Evaluate switches.") + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = false +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +if METAL_TOP == "6K" + met_top_thick = 0.69.um + +elsif METAL_TOP == "9K" + met_top_thick = 0.99.um + +elsif METAL_TOP == "11K" + met_top_thick = 1.19.um + +elsif METAL_TOP == "30K" + met_top_thick = 3.035.um + +end #METAL_TOP + +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +if METAL_LEVEL == "6LM" + top_via = via5 + topmin1_via = via4 + top_metal = metaltop + topmin1_metal = metal5 +elsif METAL_LEVEL == "5LM" + top_via = via4 + topmin1_via = via3 + top_metal = metal5 + topmin1_metal = metal4 +elsif METAL_LEVEL == "4LM" + top_via = via3 + topmin1_via = via2 + top_metal = metal4 + topmin1_metal = metal3 +elsif METAL_LEVEL == "3LM" + top_via = via2 + topmin1_via = via1 + top_metal = metal3 + topmin1_metal = metal2 +elsif METAL_LEVEL == "2LM" + top_via = via1 + topmin1_via = via1 + top_metal = metal2 + topmin1_metal = metal1 +end #METAL_LEVEL + +#========================================================================================================================= +#---------------------------------------------------- MAIN RUNSET -------------------------------------------------------- +#========================================================================================================================= + +logger.info("Starting GF180MCU ANTENNA DRC rules.") + +#======================================== +#----------------- POLY ----------------- +#======================================== +connect(poly2,tgate ) +connect(poly2,thin_gate ) +connect(poly2,thick_gate) +# Rule ANT.1: Maximum ratio of Poly2 perimeter area to related gate oxide area is 200 +logger.info("Executing rule ANT.1") +antenna_check(tgate,perimeter_only(poly2,0.2.um), 200).output("ANT.1","ANT.1: Maximum ratio of Poly2 perimeter area to related gate oxide area is 200") + +#======================================== +#--------------- CONTACT ---------------- +#======================================== +connect(poly2,contact) +connect(diode,contact) +# Rule ANT.8: Maximum ratio of contact area to related gate oxide area is 10 +logger.info("Executing rule ANT.8") +antenna_check(tgate, contact, 10).output("ANT.8","ANT.8: Maximum ratio of contact area to related gate oxide area is 10") + +#======================================== +#---------------- METAL1 ---------------- +#======================================== +connect(contact,metal1) +# Case (a): Connection to COMP is not present: Flag error (No diode) [Default] +# Rule ANT.2: Maximum ratio of Metal1 perimeter area to related gate oxide area is 400 +# antenna_check(tgate,perimeter_only(metal1,0.54.um), 400).#output("ANT.2","ANT.2: Maximum ratio of Metal1 perimeter area to related gate oxide area is 400") + +# Case (b) Connection to COMP is present: [Thin gate , Thick gate] +# Rule ANT.16_i_ANT.2: Diode filtering for ANT.2 [thin gate] , MF = 2 +logger.info("Executing rule ANT.16_i_ANT.2") +antenna_check(thin_gate,perimeter_only(metal1,0.54.um), 400,[diode,800]).output("ANT.16_i_ANT.2","ANT.16_i_ANT.2: Maximum ratio of Metal1 perimeter area to related thin gate oxide area is 400") + +# Rule ANT.16_ii_ANT.2: Diode filtering for ANT.2 [thick gate] , MF = 15 +logger.info("Executing rule ANT.16_ii_ANT.2") +antenna_check(thick_gate,perimeter_only(metal1,0.54.um), 400,[diode,6000]).output("ANT.16_ii_ANT.2","ANT.16_ii_ANT.2: Maximum ratio of Metal1 perimeter area to related thick gate oxide area is 400") + +#======================================== +#----------------- VIA1 ----------------- +#======================================== +connect(metal1, via1 ) +# Case (a): Connection to COMP is not present: Flag error (No diode) [Default] +# Rule ANT.9: Maximum ratio of Via1 area to related gate oxide area is 20 +# antenna_check(tgate, via1, 20).#output("ANT.9","ANT.9: Maximum ratio of Via1 area to related gate oxide area is 20") + +# Case (b) Connection to COMP is present: [Thin gate , Thick gate] +# Rule ANT.16_i_ANT.9: Diode filtering for ANT.9 [thin gate] +logger.info("Executing rule ANT.16_i_ANT.9") +antenna_check(thin_gate,via1, 20,[diode,40]).output("ANT.16_i_ANT.9","ANT.16_i_ANT.9: Maximum ratio of Via1 area to related thin gate oxide area is 20") + +# Rule ANT.16_ii_ANT.9: Diode filtering for ANT.9 [thick gate] +logger.info("Executing rule ANT.16_ii_ANT.9") +antenna_check(thick_gate,via1, 20,[diode,300]).output("ANT.16_ii_ANT.9","ANT.16_ii_ANT.9: Maximum ratio of Via1 area to related thick gate oxide area is 20") + +#======================================== +#---------------- METAL2 ---------------- +#======================================== +connect(via1, metal2 ) +# Case (a): Connection to COMP is not present: Flag error (No diode) [Default] +# Rule ANT.3: Maximum ratio of Metal2 perimeter area to related gate oxide area is 400 +# antenna_check(tgate,perimeter_only(metal2,0.54.um), 400).#output("ANT.3","ANT.3: Maximum ratio of Metal2 perimeter area to related gate oxide area is 400") + +# Case (b) Connection to COMP is present: [Thin gate , Thick gate] +# Rule ANT.16_i_ANT.3: Diode filtering for ANT.3 [thin gate] +logger.info("Executing rule ANT.16_i_ANT.3") +antenna_check(thin_gate,perimeter_only(metal2,0.54.um), 400,[diode,800]).output("ANT.16_i_ANT.3","ANT.16_i_ANT.3: Maximum ratio of Metal2 perimeter area to related gate oxide area is 400") + +# Rule ANT.16_i_ANT.3: Diode filtering for ANT.3 [thick gate] +logger.info("Executing rule ANT.16_ii_ANT.3") +antenna_check(thick_gate,perimeter_only(metal2,0.54.um), 400,[diode,6000]).output("ANT.16_ii_ANT.3","ANT.16_ii_ANT.3: Maximum ratio of Metal2 perimeter area to related gate oxide area is 400") + +#======================================== +#----------------- VIA2 ----------------- +#======================================== +connect(metal2, via2 ) +# Case (a): Connection to COMP is not present: Flag error (No diode) [Default] +# Rule ANT.10: Maximum ratio of Via2 area to related gate oxide area is 20 +# antenna_check(tgate, via2, 20).#output("ANT.10","ANT.10: Maximum ratio of Via2 area to related gate oxide area is 20") + +# Case (b) Connection to COMP is present: [Thin gate , Thick gate] +# Rule ANT.16_i_ANT.10: Diode filtering for ANT.10 [thin gate] +logger.info("Executing rule ANT.16_i_ANT.10") +antenna_check(thin_gate,via2, 20,[diode,40]).output("ANT.16_i_ANT.10","ANT.16_i_ANT.10: Maximum ratio of Via2 area to related thin gate oxide area is 20") + +# Rule ANT.16_ii_ANT.10: Diode filtering for ANT.10 [thick gate] +logger.info("Executing rule ANT.16_ii_ANT.10") +antenna_check(thick_gate,via2, 20,[diode,300]).output("ANT.16_ii_ANT.10","ANT.16_ii_ANT.10: Maximum ratio of Via2 area to related thick gate oxide area is 20") + +#======================================== +#---------------- METAL3 ---------------- +#======================================== +connect(via2, metal3 ) +# Case (a): Connection to COMP is not present: Flag error (No diode) [Default] +# Rule ANT.4: Maximum ratio of Metal3 perimeter area to related gate oxide area is 400 +# antenna_check(tgate,perimeter_only(metal3,0.54.um), 400).#output("ANT.4","ANT.4: Maximum ratio of Metal3 perimeter area to related gate oxide area is 400") + +# Case (b) Connection to COMP is present: [Thin gate , Thick gate] +# Rule ANT.16_i_ANT.4: Diode filtering for ANT.4 [thin gate] +logger.info("Executing rule ANT.16_i_ANT.4") +antenna_check(thin_gate,perimeter_only(metal3,0.54.um), 400,[diode,800]).output("ANT.16_i_ANT.4","ANT.16_i_ANT.4: Maximum ratio of Metal3 perimeter area to related gate oxide area is 400") + +# Rule ANT.16_i_ANT.4: Diode filtering for ANT.4 [thick gate] +logger.info("Executing rule ANT.16_ii_ANT.4") +antenna_check(thick_gate,perimeter_only(metal3,0.54.um), 400,[diode,6000]).output("ANT.16_ii_ANT.4","ANT.16_ii_ANT.4: Maximum ratio of Metal3 perimeter area to related gate oxide area is 400") + +#======================== +#----- MIM OPTION A ----- +#======================== +if MIM_OPTION == "A" + connect(metal3, fusetop ) + # Rule ANT.14: Maximum ratio of each of the metal3 layer perimeter area to related MIM area is 400 + # antenna_check(fusetop,perimeter_only(metal3,0.54.um), 400).#output("ANT.14","ANT.14: Maximum ratio of each of the metal3 layer perimeter area to related MIM area is 400") + # Rule ANT.16_iii_ANT.14_M3_MIMA: Maximum ratio of each of the metal3 layer perimeter area to related MIM area is 400 + logger.info("Executing rule ANT.16_iii_ANT.14_M3_MIMA") + antenna_check(fusetop,perimeter_only(metal3,0.54.um), 400,[diode,6000]).output("ANT.16_iii_ANT.14_M3_MIMA","ANT.16_iii_ANT.14_M3_MIMA: Maximum ratio of each of the metal3 layer perimeter area to related MIM area is 400") + # Rule ANT.15: Maximum ratio of each of Via2 area to related MIM area is 20 + # antenna_check(fusetop, via2, 20).#output("ANT.15","ANT.15: Maximum ratio of each of Via2 area to related MIM area is 20") + # Rule ANT.16_iii_ANT.15_V2_MIMA: Maximum ratio of each of Via2 area to related MIM area is 20 + logger.info("Executing rule ANT.16_iii_ANT.15_V2_MIMA") + antenna_check(fusetop, via2, 20,[diode,300]).output("ANT.16_iii_ANT.15_V2_MIMA","ANT.16_iii_ANT.15_V2_MIMA: Maximum ratio of each of Via2 area to related MIM area is 20") +end + +#======================================== +#----------------- VIA3 ----------------- +#======================================== +connect(metal3, via3 ) +# Case (a): Connection to COMP is not present: Flag error (No diode) [Default] +# Rule ANT.11: Maximum ratio of Via3 area to related gate oxide area is 20 +# antenna_check(tgate, via3, 20).#output("ANT.11","ANT.11: Maximum ratio of Via3 area to related gate oxide area is 20") + +# Case (b) Connection to COMP is present: [Thin gate , Thick gate] +# Rule ANT.16_i_ANT.11: Diode filtering for ANT.11 [thin gate] +logger.info("Executing rule ANT.16_i_ANT.11") +antenna_check(thin_gate,via3, 20,[diode,40]).output("ANT.16_i_ANT.11","ANT.16_i_ANT.11: Maximum ratio of Via3 area to related thin gate oxide area is 20") + +# Rule ANT.16_ii_ANT.11: Diode filtering for ANT.11 [thick gate] +logger.info("Executing rule ANT.16_ii_ANT.11") +antenna_check(thick_gate,via3, 20,[diode,300]).output("ANT.16_ii_ANT.11","ANT.16_ii_ANT.11: Maximum ratio of Via3 area to related thick gate oxide area is 20") + +#======================== +#----- MIM OPTION A ----- +#======================== +if MIM_OPTION == "A" + # Rule ANT.15: Maximum ratio of each of Via3 area to related MIM area is 20 + # antenna_check(fusetop, via3, 20).#output("ANT.15","ANT.15: Maximum ratio of each of Via3 area to related MIM area is 20") + # Rule ANT.16_iii_ANT.15_V3_MIMA: Maximum ratio of each of Via2 area to related MIM area is 20 + logger.info("Executing rule ANT.16_iii_ANT.15_V3_MIMA") + antenna_check(fusetop, via3, 20,[diode,300]).output("ANT.16_iii_ANT.15_V3_MIMA","ANT.16_iii_ANT.15_V3_MIMA: Maximum ratio of each of Via3 area to related MIM area is 20") +end + +#======================================== +#---------------- METAL4 ---------------- +#======================================== +connect(via3, metal4 ) +# Rule ANT.5: Maximum ratio of Metal4 perimeter area to related gate oxide area is 400 +# antenna_check(tgate,perimeter_only(metal4,0.54.um), 400).#output("ANT.5","ANT.5: Maximum ratio of Metal4 perimeter area to related gate oxide area is 400") + +# Rule ANT.16_i_ANT.5: Diode filtering for ANT.5 [thin gate] +logger.info("Executing rule ANT.16_i_ANT.5") +antenna_check(thin_gate,perimeter_only(metal4,0.54.um), 400,[diode,800]).output("ANT.16_i_ANT.5","ANT.16_i_ANT.5: Maximum ratio of Metal4 perimeter area to related gate oxide area is 400") + +# Rule ANT.16_i_ANT.5: Diode filtering for ANT.5 [thick gate] +logger.info("Executing rule ANT.16_ii_ANT.5") +antenna_check(thick_gate,perimeter_only(metal4,0.54.um), 400,[diode,6000]).output("ANT.16_ii_ANT.5","ANT.16_ii_ANT.5: Maximum ratio of Metal4 perimeter area to related gate oxide area is 400") + +#======================== +#----- MIM OPTION A ----- +#======================== +if MIM_OPTION == "A" + # Rule ANT.14: Maximum ratio of each of the metal4 layer perimeter area to related MIM area is 400 + # antenna_check(fusetop,perimeter_only(metal4,0.54.um), 400).#output("ANT.14","ANT.14: Maximum ratio of each of the metal4 layer perimeter area to related MIM area is 400") + # Rule ANT.16_iii_ANT.14_M4_MIMA: Maximum ratio of each of the metal3 layer perimeter area to related MIM area is 400 + logger.info("Executing rule ANT.16_iii_ANT.15_V3_MIMA") + antenna_check(fusetop,perimeter_only(metal4,0.54.um), 400,[diode,6000]).output("ANT.16_iii_ANT.14_M4_MIMA","ANT.16_iii_ANT.14_M4_MIMA: Maximum ratio of each of the metal4 layer perimeter area to related MIM area is 400") +end + +#======================================== +#----------------- VIA4 ----------------- +#======================================== +connect(metal4, via4 ) +# Case (a): Connection to COMP is not present: Flag error (No diode) [Default] +# Rule ANT.12: Maximum ratio of Via4 area to related gate oxide area is 20 +# antenna_check(tgate, via4, 20).#output("ANT.12","ANT.12: Maximum ratio of Via4 area to related gate oxide area is 20") + +# Case (b) Connection to COMP is present: [Thin gate , Thick gate] +# Rule ANT.16_i_ANT.12: Diode filtering for ANT.12 [thin gate] +logger.info("Executing rule ANT.16_i_ANT.12") +antenna_check(thin_gate,via4, 20,[diode,40]).output("ANT.16_i_ANT.12","ANT.16_i_ANT.12: Maximum ratio of Via4 area to related thin gate oxide area is 20") + +# Rule ANT.16_ii_ANT.12: Diode filtering for ANT.12 [thick gate] +logger.info("Executing rule ANT.16_ii_ANT.12") +antenna_check(thick_gate,via4, 20,[diode,300]).output("ANT.16_ii_ANT.12","ANT.16_ii_ANT.12: Maximum ratio of Via4 area to related thick gate oxide area is 20") + +#======================== +#----- MIM OPTION A ----- +#======================== +if MIM_OPTION == "A" + # Rule ANT.15: Maximum ratio of each of Via4 area to related MIM area is 20 + # antenna_check(fusetop, via4, 20).#output("ANT.15","ANT.15: Maximum ratio of each of Via4 area to related MIM area is 20") + # Rule ANT.16_iii_ANT.15_V4_MIMA: Maximum ratio of each of Via2 area to related MIM area is 20 + logger.info("Executing rule ANT.16_iii_ANT.15_V4_MIMA") + antenna_check(fusetop, via4, 20,[diode,300]).output("ANT.16_iii_ANT.15_V4_MIMA","ANT.16_iii_ANT.15_V4_MIMA: Maximum ratio of each of Via4 area to related MIM area is 20") +end + +#======================================== +#---------------- METAL5 ---------------- +#======================================== +connect(via4, metal5 ) +# Rule ANT.6: Maximum ratio of Metal5 perimeter area to related gate oxide area is 400 +#antenna_check(tgate,perimeter_only(metal5,0.54.um), 400).#output("ANT.6","ANT.6: Maximum ratio of Metal5 perimeter area to related gate oxide area is 400") + +# Rule ANT.16_i_ANT.6: Diode filtering for ANT.6 [thin gate] +logger.info("Executing rule ANT.16_i_ANT.6") +antenna_check(thin_gate,perimeter_only(metal5,0.54.um), 400,[diode,800]).output("ANT.16_i_ANT.6","ANT.16_i_ANT.6: Maximum ratio of Metal5 perimeter area to related gate oxide area is 400") + +# Rule ANT.16_i_ANT.6: Diode filtering for ANT.6 [thick gate] +logger.info("Executing rule ANT.16_ii_ANT.6") +antenna_check(thick_gate,perimeter_only(metal5,0.54.um), 400,[diode,6000]).output("ANT.16_ii_ANT.6","ANT.16_ii_ANT.6: Maximum ratio of Metal5 perimeter area to related gate oxide area is 400") + +#======================== +#----- MIM OPTION A ----- +#======================== +if MIM_OPTION == "A" + # Rule ANT.14: Maximum ratio of each of the metal5 layer perimeter area to related MIM area is 400 + # antenna_check(fusetop,perimeter_only(metal5,0.54.um), 400).#output("ANT.14","ANT.14: Maximum ratio of each of the metal5 layer perimeter area to related MIM area is 400") + # Rule ANT.16_iii_ANT.14_M5_MIMA: Maximum ratio of each of the metal3 layer perimeter area to related MIM area is 400 + logger.info("Executing rule ANT.16_iii_ANT.14_M5_MIMA") + antenna_check(fusetop,perimeter_only(metal5,0.54.um), 400,[diode,6000]).output("ANT.16_iii_ANT.14_M5_MIMA","ANT.16_iii_ANT.14_M5_MIMA: Maximum ratio of each of the metal5 layer perimeter area to related MIM area is 400") +end + +#======================================== +#----------------- VIA5 ----------------- +#======================================== +connect(metal5, via5 ) +# Case (a): Connection to COMP is not present: Flag error (No diode) [Default] +# Rule ANT.13: Maximum ratio of Via5 area to related gate oxide area is 20 +# antenna_check(tgate, via5, 20).#output("ANT.13","ANT.13: Maximum ratio of Via5 area to related gate oxide area is 20") + +# Case (b) Connection to COMP is present: [Thin gate , Thick gate] +# Rule ANT.16_i_ANT.13: Diode filtering for ANT.13 [thin gate] +logger.info("Executing rule ANT.16_i_ANT.13") +antenna_check(thin_gate,via5, 20,[diode,40]).output("ANT.16_i_ANT.13","ANT.16_i_ANT.13: Maximum ratio of Via5 area to related thin gate oxide area is 20") + +# Rule ANT.16_ii_ANT.13: Diode filtering for ANT.13 [thick gate] +logger.info("Executing rule ANT.16_ii_ANT.13") +antenna_check(thick_gate,via5, 20,[diode,300]).output("ANT.16_ii_ANT.13","ANT.16_ii_ANT.13: Maximum ratio of Via5 area to related thick gate oxide area is 20") + +#======================== +#----- MIM OPTION A ----- +#======================== +if MIM_OPTION == "A" + # Rule ANT.15: Maximum ratio of each of Via5 area to related MIM area is 20 + # antenna_check(fusetop, via5, 20).#output("ANT.15","ANT.15: Maximum ratio of each of Via5 area to related MIM area is 20") + # Rule ANT.16_iii_ANT.15_V5_MIMA: Maximum ratio of each of Via2 area to related MIM area is 20 + logger.info("Executing rule ANT.16_iii_ANT.15_V5_MIMA") + antenna_check(fusetop, via5, 20,[diode,300]).output("ANT.16_iii_ANT.15_V5_MIMA","ANT.16_iii_ANT.15_V5_MIMA: Maximum ratio of each of Via5 area to related MIM area is 20") +end + +#======================================== +#--------------- METALTOP --------------- +#======================================== +connect(via5, metaltop) +# Rule ANT.7: Maximum ratio of MetalTop perimeter area to related gate oxide area is 400 +# antenna_check(tgate,perimeter_only(metaltop,met_top_thick), 400).#output("ANT.7","ANT.7: Maximum ratio of MetalTop perimeter area to related gate oxide area is 400") + +# Rule ANT.16_i_ANT.7: Diode filtering for ANT.7 [thin gate] +logger.info("Executing rule ANT.16_i_ANT.7") +antenna_check(thin_gate,perimeter_only(metaltop,met_top_thick), 400,[diode,800]).output("ANT.16_i_ANT.7","ANT.16_i_ANT.7: Maximum ratio of Metaltop perimeter area to related gate oxide area is 400") + +# Rule ANT.16_ii_ANT.7: Diode filtering for ANT.7 [thick gate] +logger.info("Executing rule ANT.16_ii_ANT.7") +antenna_check(thick_gate,perimeter_only(metaltop,met_top_thick), 400,[diode,6000]).output("ANT.16_ii_ANT.7","ANT.16_ii_ANT.7: Maximum ratio of Metaltop perimeter area to related gate oxide area is 400") + +#======================== +#----- MIM OPTION A ----- +#======================== +if MIM_OPTION == "A" + # Rule ANT.14: Maximum ratio of each of the metaltop layer perimeter area to related MIM area is 400 + # antenna_check(fusetop,perimeter_only(metaltop,met_top_thick), 400).#output("ANT.14","ANT.14: Maximum ratio of each of the top metal layer perimeter area to related MIM area is 400") + # Rule ANT.16_iii_ANT.14_MT_MIMA: Maximum ratio of each of the metal3 layer perimeter area to related MIM area is 400 + logger.info("Executing rule ANT.16_iii_ANT.14_MT_MIMA") + antenna_check(fusetop,perimeter_only(metaltop,met_top_thick), 400,[diode,6000]).output("ANT.16_iii_ANT.14_MT_MIMA","ANT.16_iii_ANT.14_MT_MIMA: Maximum ratio of each of the Metaltop layer perimeter area to related MIM area is 400") +end + +#======================== +#----- MIM OPTION B ----- +#======================== +if MIM_OPTION == "B" + connect(metaltop, fusetop ) + # Rule ANT.14: Maximum ratio of each of the metaltop layer perimeter area to related MIM area is 400 + # antenna_check(fusetop,perimeter_only(metaltop,met_top_thick), 400).#output("ANT.14","ANT.14: Maximum ratio of each of the top metal layer perimeter area to related MIM area is 400") + # Rule ANT.16_iii_ANT.14_MT_MIMB: Maximum ratio of each of the metal3 layer perimeter area to related MIM area is 400 + logger.info("Executing rule ANT.16_iii_ANT.14_MT_MIMB") + antenna_check(fusetop,perimeter_only(metaltop,met_top_thick), 400,[diode,6000]).output("ANT.16_iii_ANT.14_MT_MIMB","ANT.16_iii_ANT.14_MT_MIMB: Maximum ratio of each of the metaltop layer perimeter area to related MIM area is 400") +end + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Total Run time %f seconds" % [run_time]) + + +#=================================== +#--------------- END --------------- +#=================================== + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu_density.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu_density.drc new file mode 100644 index 000000000..3956b42e5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/gf180mcu_density.drc @@ -0,0 +1,195 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#=========================================================================================================================== +#------------------------------------------- GF 0.18 um MCU DRC RULE DECK -------------------------------------------------- +#=========================================================================================================================== + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#========================================= +#------------ FILE SETUP ----------------- +#========================================= + +# optionnal for a batch launch : klayout -b -r gf_018mcu_density.drc -rd input=design.gds -rd report=gf180_ant_drc.txt + +logger.info("Starting running GF180MCU Klayout density checks DRC runset on %s" % [$input]) + +if $input + source($input, $topcell) +end + +logger.info("Loading database to memory is complete.") + + +if $report + logger.info("GF180MCU Klayout density checks DRC runset output at: %s" % [$report]) + report("GF180 DENSITY DRC runset", $report) +else + logger.info("GF180MCU Klayout density checks DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180mcu_density.lyrdb").path]) + report("GF180 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "gf180mcu_density.lyrdb")) +end + +if $thr + threads($thr) +else + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#====================================================================================================== +#--------------------------------------- LAYER DEFINITIONS -------------------------------------------- +#====================================================================================================== + +poly2 = polygons(30, 0) +metal1 = polygons(34, 0) +metal2 = polygons(36, 0) +metal3 = polygons(42, 0) +metal4 = polygons(46, 0) +metal5 = polygons(81, 0) +metaltop = polygons(53, 0) + +#====================================================================================================== +#--------------------------------------- LAYER DERIVATIONS -------------------------------------------- +#====================================================================================================== + +# === LAYOUT EXTENT === +CHIP = extent.sized(0.0) + +#======================================================================================= +#------------------------------------- SWITCHES ---------------------------------------- +#======================================================================================= + +logger.info("Evaluate switches.") + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + + +#========================================================================================================================= +#---------------------------------------------------- MAIN RUNSET -------------------------------------------------------- +#========================================================================================================================= + +logger.info("Starting GF180MCU DENSITY DRC rules.") + + +logger.info("Executing rule PL.8") +# Rule PL.8: Poly2 coverage over the entire die shall be 14%. Dummy poly2 lines must be added to meet the minimum poly2 density requirement. +if ((poly2.area / CHIP.area)*100 < 14) + poly2.output("PL.8", "PL.8 : Poly2 coverage over the entire die shall be 14%. Dummy poly2 lines must be added to meet the minimum poly2 density requirement. : 14%") +end + +logger.info("Executing rule M1.4") +# Rule M1.4: Metal1 coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal fill guidelines. Customer needs to ensure enough dummy metal to satisfy Metal1 coverage) +if ((metal1.area / CHIP.area)*100 < 30) + metal1.output("M1.4", "M1.4 : Metal1 coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal fill guidelines. Customer needs to ensure enough dummy metal to satisfy Metal1 coverage) : 30%") +end + +logger.info("Executing rule M2.4") +# Rule M2.4: Metal2 coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal fill guidelines. Customer needs to ensure enough dummy metal to satisfy Metal2 coverage) +if ((metal2.area / CHIP.area)*100 < 30) + metal2.output("M2.4", "M2.4 : Metal2 coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal fill guidelines. Customer needs to ensure enough dummy metal to satisfy Metal2 coverage) : 30%") +end + +logger.info("Executing rule M3.4") +# Rule M3.4: metal3 coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal fill guidelines. Customer needs to ensure enough dummy metal to satisfy metal3 coverage) +if ((metal3.area / CHIP.area)*100 < 30) + metal3.output("M3.4", "M3.4 : metal3 coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal fill guidelines. Customer needs to ensure enough dummy metal to satisfy metal3 coverage) : 30%") +end + +logger.info("Executing rule M4.4") +# Rule M4.4: metal4 coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal fill guidelines. Customer needs to ensure enough dummy metal to satisfy metal4 coverage) +if ((metal4.area / CHIP.area)*100 < 30) + metal4.output("M4.4", "M4.4 : metal4 coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal fill guidelines. Customer needs to ensure enough dummy metal to satisfy metal4 coverage) : 30%") +end + +logger.info("Executing rule M5.4") +# Rule M5.4: metal5 coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal fill guidelines. Customer needs to ensure enough dummy metal to satisfy metal5 coverage) +if ((metal5.area / CHIP.area)*100 < 30) + metal5.output("M5.4", "M5.4 : metal5 coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal fill guidelines. Customer needs to ensure enough dummy metal to satisfy metal5 coverage) : 30%") +end + +if METAL_TOP == "6K" + logger.info("Executing rule MT.3") + # Rule MT.3: MetalTop coverage over the entire die shall be >30% (Refer to section 10.3 for Dummy Metal-fill guidelines. Customer needs to ensure enough dummy metal to satisfy Metaln coverage) + if ((metaltop.area / CHIP.area)*100 < 30) + metaltop.output("MT.3", "MT.3 : MetalTop coverage over the entire die shall be >30% (Refer to section 10.3 for Dummy Metal-fill guidelines. Customer needs to ensure enough dummy metal to satisfy Metaln coverage) : 30%") + end + +elsif METAL_TOP == "9K" + logger.info("Executing rule MT.3") + # Rule MT.3: MetalTop coverage over the entire die shall be >30% (Refer to section 10.3 for Dummy Metal-fill guidelines. Customer needs to ensure enough dummy metal to satisfy Metaln coverage) + if ((metaltop.area / CHIP.area)*100 < 30) + metaltop.output("MT.3", "MT.3 : MetalTop coverage over the entire die shall be >30% (Refer to section 10.3 for Dummy Metal-fill guidelines. Customer needs to ensure enough dummy metal to satisfy Metaln coverage) : 30%") + end + +elsif METAL_TOP == "30K" + logger.info("Executing rule MT30.7") + # Rule MT30.7: Thick MetalTop coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal-fill guidelines. Customer needs to ensure enough dummy metal to satisfy Metaln coverage). + if ((metaltop.area / CHIP.area)*100 < 30) + metaltop.output("MT30.7", "MT30.7 : Thick MetalTop coverage over the entire die shall be >30% (Refer to section 13.0 for Dummy Metal-fill guidelines. Customer needs to ensure enough dummy metal to satisfy Metaln coverage). : 30%") + end + +end #METAL_TOP + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Total Run time %f seconds" % [run_time]) + + +#=================================== +#--------------- END --------------- +#=================================== + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/10v_ldnmos.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/10v_ldnmos.drc new file mode 100644 index 000000000..da06d0575 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/10v_ldnmos.drc @@ -0,0 +1,529 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#--------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (10V LDNMOS) ---------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +sab = polygons(49 , 0 ) +contact = polygons(33 , 0 ) +mvsd = polygons(210, 0 ) +ldmos_xtor = polygons(226, 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#-------------------10V LDNMOS------------------- +#================================================ + +# Rule MDN.1: Min MVSD width (for litho purpose). is 1µm +logger.info("Executing rule MDN.1") +mdn1_l1 = mvsd.width(1.um, euclidian).polygons(0.001) +mdn1_l1.output("MDN.1", "MDN.1 : Min MVSD width (for litho purpose). : 1µm") +mdn1_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_mdn_2a, unconnected_mdn_2b = conn_space(mvsd, 1, 2, euclidian) + +# Rule MDN.2a: Min MVSD space [Same Potential]. is 1µm +logger.info("Executing rule MDN.2a") +mdn2a_l1 = connected_mdn_2a +mdn2a_l1.output("MDN.2a", "MDN.2a : Min MVSD space [Same Potential]. : 1µm") +mdn2a_l1.forget + +# Rule MDN.2b: Min MVSD space [Diff Potential]. is 2µm +logger.info("Executing rule MDN.2b") +mdn2b_l1 = unconnected_mdn_2b +mdn2b_l1.output("MDN.2b", "MDN.2b : Min MVSD space [Diff Potential]. : 2µm") +mdn2b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule MDN.2b: Min MVSD space [Diff Potential]. is 2µm +logger.info("Executing rule MDN.2b") +mdn2b_l1 = mvsd.space(2.um, euclidian).polygons(0.001) +mdn2b_l1.output("MDN.2b", "MDN.2b : Min MVSD space [Diff Potential]. : 2µm") +mdn2b_l1.forget + +end #CONNECTIVITY_RULES + +gate_mdn = poly2.and(comp).inside(ldmos_xtor).inside(dualgate) +# Rule MDN.3a: Min transistor channel length. is 0.6µm +logger.info("Executing rule MDN.3a") +mdn3a_l1 = gate_mdn.enclosing(mvsd, 0.6.um, euclidian).polygons(0.001) +mdn3a_l1.output("MDN.3a", "MDN.3a : Min transistor channel length. : 0.6µm") +mdn3a_l1.forget + +mvsd_mdn = mvsd.edges.and(ncomp).and(poly2) +# Rule MDN.3b: Max transistor channel length. +logger.info("Executing rule MDN.3b") +mdn3b_l1 = poly2.edges.and(ncomp).or(mvsd_mdn).and(ldmos_xtor).and(dualgate).not(ngate.not(mvsd).edges.interacting(poly2.edges.and(ncomp).or(mvsd_mdn)).width(20.001.um).edges) +mdn3b_l1.output("MDN.3b", "MDN.3b : Max transistor channel length.") +mdn3b_l1.forget + +mvsd_mdn.forget +# Rule MDN.4a: Min transistor channel width. is 4µm +logger.info("Executing rule MDN.4a") +mdn4a_l1 = gate_mdn.edges.not(mvsd).interacting(mvsd).width(4.um, euclidian).polygons(0.001) +mdn4a_l1.output("MDN.4a", "MDN.4a : Min transistor channel width. : 4µm") +mdn4a_l1.forget + +# Rule MDN.4b: Max transistor channel width. +logger.info("Executing rule MDN.4b") +mdn4b_l1 = gate_mdn.not(mvsd).interacting(nplus).not_interacting(gate_mdn.edges.not(mvsd).not(poly2.edges).width(50.001.um).polygons) +mdn4b_l1.output("MDN.4b", "MDN.4b : Max transistor channel width.") +mdn4b_l1.forget + +gate_mdn.forget +pcomp_mdn5a = pcomp.not_interacting(ncomp).inside(ldmos_xtor).inside(dualgate) +# Rule MDN.5ai: Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. +logger.info("Executing rule MDN.5ai") +mdn5ai_l1 = mvsd.and(pcomp_mdn5a).or(pcomp_mdn5a.separation(mvsd, 1.um, euclidian).polygons(0.001)) +mdn5ai_l1.output("MDN.5ai", "MDN.5ai : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed.") +mdn5ai_l1.forget + +pcomp_mdn5a.forget +# Rule MDN.5aii: Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. is 0.92µm +logger.info("Executing rule MDN.5aii") +mdn5aii_l1 = pcomp.interacting(ncomp).inside(ldmos_xtor).inside(dualgate).not(nplus).separation(mvsd, 0.92.um, euclidian).polygons(0.001) +mdn5aii_l1.output("MDN.5aii", "MDN.5aii : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. : 0.92µm") +mdn5aii_l1.forget + +ncomp_mdn5b = ncomp.inside(ldmos_xtor).inside(dualgate) +pcomp_mdn5b = pcomp.inside(ldmos_xtor).inside(dualgate) +# Rule MDN.5b: Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP). Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well. +logger.info("Executing rule MDN.5b") +mdn5b_l1 = ncomp_mdn5b.not(poly2).not(mvsd).separation(pcomp_mdn5b, 0.4.um, euclidian).polygons.or(ncomp_mdn5b.not(poly2).not(mvsd).and(pcomp_mdn5b)) +mdn5b_l1.output("MDN.5b", "MDN.5b : Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP). Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well.") +mdn5b_l1.forget + +ncomp_mdn5b.forget +pcomp_mdn5b.forget +mdn_5c_ncompsd = ncomp.inside(ldmos_xtor).inside(dualgate).interacting(mvsd).sized(0.36.um).sized(-0.36.um).extents +mdn_5c_error = mdn_5c_ncompsd.edges.centers(0, 0.99).not_interacting(mdn_5c_ncompsd.drc(separation(pcomp, euclidian) <= 15.um).polygons(0.001)) +# Rule MDN.5c: Maximum distance of the nearest edge of the substrate tab from NCOMP edge. is 15µm +logger.info("Executing rule MDN.5c") +mdn5c_l1 = mdn_5c_error.and(ncomp).and(pcomp.holes).extended(0, 0, 0.001, 0.001) +mdn5c_l1.output("MDN.5c", "MDN.5c : Maximum distance of the nearest edge of the substrate tab from NCOMP edge. : 15µm") +mdn5c_l1.forget + +mdn_5c_ncompsd.forget +mdn_5c_error.forget +# Rule MDN.6: ALL LDNMOS shall be covered by Dualgate layer. +logger.info("Executing rule MDN.6") +mdn6_l1 = ncomp.not(poly2).not(mvsd).or(ngate.not(mvsd)).or(ncomp.and(mvsd)).inside(ldmos_xtor).not_inside(dualgate) +mdn6_l1.output("MDN.6", "MDN.6 : ALL LDNMOS shall be covered by Dualgate layer.") +mdn6_l1.forget + +# Rule MDN.6a: Min Dualgate enclose NCOMP. +logger.info("Executing rule MDN.6a") +mdn6a_l1 = dualgate.enclosing(ncomp.inside(ldmos_xtor), 0.5.um, euclidian).polygons(0.001).or(ncomp.inside(ldmos_xtor).not_inside(dualgate)) +mdn6a_l1.output("MDN.6a", "MDN.6a : Min Dualgate enclose NCOMP.") +mdn6a_l1.forget + +# Rule MDN.7: Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer. +logger.info("Executing rule MDN.7") +mdn7_l1 = ncomp.interacting(mvsd).not(poly2).not(mvsd).or(ngate.interacting(mvsd).not(mvsd)).or(ncomp.and(mvsd)).inside(dualgate).not_inside(ldmos_xtor) +mdn7_l1.output("MDN.7", "MDN.7 : Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer.") +mdn7_l1.forget + +# Rule MDN.7a: Min LDMOS_XTOR enclose Dualgate. +logger.info("Executing rule MDN.7a") +mdn7a_l1 = dualgate.not_outside(ldmos_xtor).not(ldmos_xtor).or(dualgate.interacting(mvsd).not_inside(ldmos_xtor)) +mdn7a_l1.output("MDN.7a", "MDN.7a : Min LDMOS_XTOR enclose Dualgate.") +mdn7a_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_mdn_8a, unconnected_mdn_8b = conn_separation(mvsd, nwell, 1, 2, euclidian) + +# Rule MDN.8a: Min LDNMOS drain MVSD space to any other equal potential Nwell space. +logger.info("Executing rule MDN.8a") +mdn8a_l1 = connected_mdn_8a.or(mvsd.not_outside(nwell)) +mdn8a_l1.output("MDN.8a", "MDN.8a : Min LDNMOS drain MVSD space to any other equal potential Nwell space.") +mdn8a_l1.forget + +# Rule MDN.8b: Min LDNMOS drain MVSD space to any other different potential Nwell space. +logger.info("Executing rule MDN.8b") +mdn8b_l1 = unconnected_mdn_8b.or(mvsd.not_outside(nwell)) +mdn8b_l1.output("MDN.8b", "MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.") +mdn8b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule MDN.8b: Min LDNMOS drain MVSD space to any other different potential Nwell space. +logger.info("Executing rule MDN.8b") +mdn8b_l1 = mvsd.separation(nwell, 2.um, euclidian).polygons(0.001).or(mvsd.not_outside(nwell)) +mdn8b_l1.output("MDN.8b", "MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.") +mdn8b_l1.forget + +end #CONNECTIVITY_RULES + +# Rule MDN.9: Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. is 4µm +logger.info("Executing rule MDN.9") +mdn9_l1 = mvsd.inside(dualgate).inside(ldmos_xtor).separation(ncomp.not_interacting(mvsd), 4.um, euclidian).polygons(0.001) +mdn9_l1.output("MDN.9", "MDN.9 : Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. : 4µm") +mdn9_l1.forget + +# rule MDN.10 is not a DRC check + +poly_mdn10 = poly2.inside(dualgate).inside(ldmos_xtor.interacting(mvsd)) +# Rule MDN.10a: Min LDNMOS POLY2 width. is 1.2µm +logger.info("Executing rule MDN.10a") +mdn10a_l1 = poly_mdn10.width(1.2.um, euclidian).polygons(0.001) +mdn10a_l1.output("MDN.10a", "MDN.10a : Min LDNMOS POLY2 width. : 1.2µm") +mdn10a_l1.forget + +# Rule MDN.10b: Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). is 0.4µm +logger.info("Executing rule MDN.10b") +mdn10b_l1 = poly_mdn10.edges.enclosing(ncomp.interacting(poly_mdn10).edges.interacting(ncomp.edges.not_interacting(poly2)), 0.4.um, euclidian) +mdn10b_l1.output("MDN.10b", "MDN.10b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). : 0.4µm") +mdn10b_l1.forget + +mdn_10c_all_errors = poly_mdn10.drc(enclosing(ncomp.interacting(poly_mdn10), euclidian) != 0.2.um) +mdn_10c_error_region = ncomp.inside(dualgate).inside(ldmos_xtor).sized(0.36.um).sized(-0.36.um).extents.and(mvsd).and(poly2) +# Rule MDN.10c: Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction. +logger.info("Executing rule MDN.10c") +mdn10c_l1 = mdn_10c_all_errors.and(mdn_10c_error_region) +mdn10c_l1.output("MDN.10c", "MDN.10c : Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction.") +mdn10c_l1.forget + +mdn_10c_all_errors.forget +mdn_10c_error_region.forget +mdn_10d_field = ncomp.and(poly2).sized(1.um, 0).and(poly2) +mdn_10d_not_max = ncomp.inside(mvsd).inside(dualgate).inside(ldmos_xtor).drc(separation(mdn_10d_field) <= 0.16.um) +mdn_10d_max = ncomp.sized(0.36.um).sized(-0.36.um).extents.not(mdn_10d_not_max.polygons).not(ncomp).not(poly2).inside(mvsd) +mdn_10d_min = ncomp.inside(mvsd).inside(dualgate).inside(ldmos_xtor).separation(mdn_10d_field , 0.16.um).polygons(0.001) +mdn_10d_overlap = ncomp.inside(mvsd).inside(dualgate).inside(ldmos_xtor).and(poly2) +# Rule MDN.10d: Min/Max POLY2 on field space to LDNMOS drain COMP. +logger.info("Executing rule MDN.10d") +mdn10d_l1 = mdn_10d_max.or(mdn_10d_min).or(mdn_10d_overlap) +mdn10d_l1.output("MDN.10d", "MDN.10d : Min/Max POLY2 on field space to LDNMOS drain COMP.") +mdn10d_l1.forget + +mdn_10d_field.forget +mdn_10d_not_max.forget +mdn_10d_max.forget +mdn_10d_min.forget +mdn_10d_overlap.forget +# Rule MDN.10ei: Min POLY2 space to Psub tap (source and body tap non-butted). +logger.info("Executing rule MDN.10ei") +mdn10ei_l1 = poly_mdn10.separation(pcomp.not_interacting(ncomp), 0.4.um).polygons(0.001).or(poly_mdn10.and(pcomp.not(nplus).not_interacting(ncomp.not(pplus)))) +mdn10ei_l1.output("MDN.10ei", "MDN.10ei : Min POLY2 space to Psub tap (source and body tap non-butted).") +mdn10ei_l1.forget + +# Rule MDN.10eii: Min POLY2 space to Psub tap (source and body tap butted). is 0.32µm +logger.info("Executing rule MDN.10eii") +mdn10eii_l1 = poly_mdn10.separation(pcomp.not(nplus).interacting(ncomp.not(pplus)), 0.32.um, euclidian).polygons(0.001) +mdn10eii_l1.output("MDN.10eii", "MDN.10eii : Min POLY2 space to Psub tap (source and body tap butted). : 0.32µm") +mdn10eii_l1.forget + +# Rule MDN.10f: Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed. +logger.info("Executing rule MDN.10f") +mdn10f_l1 = poly_mdn10.not(nplus).interacting(poly_mdn10.and(nplus),2).or(poly2.and(ldmos_xtor).interacting(poly2.not(ldmos_xtor))) +mdn10f_l1.output("MDN.10f", "MDN.10f : Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed.") +mdn10f_l1.forget + +poly_mdn10.forget +mdn_11_layer = ldmos_xtor.and(mvsd).and(comp).and(poly2).and(nplus) +mdn_11_max = mdn_11_layer.not(mdn_11_layer.drc(width <= 0.4.um).polygons) +mdn_11_min = mdn_11_layer.width(0.4.um).polygons(0.001).not_interacting(mdn_11_max) +mdn_11_no_channel = mvsd.covering(ncomp).outside(tgate).inside(dualgate).inside(ldmos_xtor).or(mvsd.not_covering(ncomp.not_interacting(poly2)).inside(dualgate).inside(ldmos_xtor)) +# Rule MDN.11: Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus). +logger.info("Executing rule MDN.11") +mdn11_l1 = mdn_11_max.or(mdn_11_min).or(mdn_11_no_channel) +mdn11_l1.output("MDN.11", "MDN.11 : Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus).") +mdn11_l1.forget + +mdn_11_layer.forget +mdn_11_max.forget +mdn_11_min.forget +mdn_11_no_channel.forget +mdn12_a = mvsd.covering(ncomp.not_interacting(poly2)).enclosing(ncomp, 0.5.um, transparent).polygons(0.001).outside(poly2).inside(dualgate).inside(ldmos_xtor) +mdn12_b = mvsd.not_covering(ncomp.not_interacting(poly2)).inside(dualgate).inside(ldmos_xtor) +# Rule MDN.12: Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width. +logger.info("Executing rule MDN.12") +mdn12_l1 = mdn12_a.or(mdn12_b) +mdn12_l1.output("MDN.12", "MDN.12 : Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width.") +mdn12_l1.forget + +mdn12_a.forget +mdn12_b.forget +# rule MDN.13 is not a DRC check + +# Rule MDN.13a: Max single finger width. is 50µm +logger.info("Executing rule MDN.13a") +mdn13a_l1 = poly2.and(ncomp).not(mvsd).inside(dualgate).inside(ldmos_xtor).drc(length > 50.um) +mdn13a_l1.output("MDN.13a", "MDN.13a : Max single finger width. : 50µm") +mdn13a_l1.forget + +mdn_source = ncomp.interacting(poly2.and(dualgate).and(ldmos_xtor).and(mvsd)).not(poly2) +mdn_ldnmos = poly2.and(ncomp).and(dualgate).not(mvsd).inside(ldmos_xtor) +# Rule MDN.13b: Layout shall have alternative source & drain. +logger.info("Executing rule MDN.13b") +mdn13b_l1 = mdn_ldnmos.not_interacting(mdn_source,1,1).or(mdn_ldnmos.not_interacting(mvsd,1,1)).or(mdn_source.interacting(mvsd)) +mdn13b_l1.output("MDN.13b", "MDN.13b : Layout shall have alternative source & drain.") +mdn13b_l1.forget + +mdn_13c_source_side = mdn_ldnmos.interacting(mdn_source.interacting(mdn_ldnmos, 2, 2).or(mdn_source.interacting(pcomp.interacting(mdn_source, 2, 2)))) +# Rule MDN.13c: Both sides of the transistor shall be terminated by source. +logger.info("Executing rule MDN.13c") +mdn13c_l1 = mvsd.covering(ncomp.not_interacting(poly2)).interacting(ncomp, 2, 2).interacting(mdn_13c_source_side) +mdn13c_l1.output("MDN.13c", "MDN.13c : Both sides of the transistor shall be terminated by source.") +mdn13c_l1.forget + +mdn_13c_source_side.forget +mdn_13d_single = mvsd.covering(ncomp.not_interacting(poly2)).interacting(ncomp, 2, 2).inside(ldmos_xtor) +mdn_13d_multi = mvsd.covering(ncomp.not_interacting(poly2)).interacting(ncomp, 3, 3).inside(ldmos_xtor) +mdn_13d_butted_well = mdn_source.sized(1.um).sized(-1.um).extents.not(pcomp).interacting(mdn_ldnmos,2,2) +# Rule MDN.13d: Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap). +logger.info("Executing rule MDN.13d") +mdn13d_l1 = pcomp.holes.covering(mdn_13d_single, 2).or(pcomp.holes.covering(mdn_13d_single).covering(mdn_13d_multi)).or(mdn_13d_butted_well) +mdn13d_l1.output("MDN.13d", "MDN.13d : Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap).") +mdn13d_l1.forget + +mdn_13d_single.forget +mdn_13d_multi.forget +mdn_13d_butted_well.forget +mdn_source.forget +mdn_ldnmos.forget +# Rule MDN.14: Min MVSD space to any DNWELL. +logger.info("Executing rule MDN.14") +mdn14_l1 = mvsd.separation(dnwell,6.0.um).polygons(0.001).or(mvsd.not_outside(dnwell)) +mdn14_l1.output("MDN.14", "MDN.14 : Min MVSD space to any DNWELL.") +mdn14_l1.forget + +# Rule MDN.15a: Min LDNMOS drain COMP width. is 0.22µm +logger.info("Executing rule MDN.15a") +mdn15a_l1 = comp.inside(mvsd).inside(dualgate).inside(ldmos_xtor).width(0.22.um, euclidian).polygons(0.001) +mdn15a_l1.output("MDN.15a", "MDN.15a : Min LDNMOS drain COMP width. : 0.22µm") +mdn15a_l1.forget + +# Rule MDN.15b: Min LDNMOS drain COMP enclose contact. is 0µm +logger.info("Executing rule MDN.15b") +mdn15b_l1 = contact.interacting(ncomp.inside(mvsd).inside(dualgate).inside(ldmos_xtor)).not_inside(ncomp.inside(mvsd)) +mdn15b_l1.output("MDN.15b", "MDN.15b : Min LDNMOS drain COMP enclose contact. : 0µm") +mdn15b_l1.forget + +# rule MDN.16 is not a DRC check + +mdn_17_blockages = pcomp.holes.not(ncomp.or(poly2).interacting(mvsd)).covering(dnwell.or(nwell)).inside(dualgate).inside(ldmos_xtor.interacting(mvsd)) +mdn_17_mos_in_gr = ngate.not(mvsd).not_inside(pcomp.holes).inside(dualgate).inside(ldmos_xtor.interacting(mvsd)) +mdn_17_gr_in_ldmos_mk = ldmos_xtor.interacting(mvsd).and(dualgate).not_covering(pcomp) +# Rule MDN.17: It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity. +logger.info("Executing rule MDN.17") +mdn17_l1 = mdn_17_blockages.or(mdn_17_mos_in_gr).or(mdn_17_gr_in_ldmos_mk) +mdn17_l1.output("MDN.17", "MDN.17 : It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity.") +mdn17_l1.forget + +mdn_17_blockages.forget +mdn_17_mos_in_gr.forget +mdn_17_gr_in_ldmos_mk.forget + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/10v_ldpmos.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/10v_ldpmos.drc new file mode 100644 index 000000000..5096d24fe --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/10v_ldpmos.drc @@ -0,0 +1,612 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#--------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (10V LDPMOS) ---------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +sab = polygons(49 , 0 ) +contact = polygons(33 , 0 ) +metal1 = polygons(34 , 0 ) +mvpsd = polygons(11 , 39) +ldmos_xtor = polygons(226, 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) +#================================================ +#------------- LAYERS CONNECTIONS --------------- +#================================================ + +if CONNECTIVITY_RULES + + logger.info("Construct connectivity for the design.") + + connect(dnwell, ncomp) + connect(ncomp, contact) + connect(pcomp, contact) + connect(lvpwell, ncomp) + connect(nwell, ncomp) + connect(natcompsd, contact) + connect(mvsd, ncomp) + connect(mvpsd, pcomp) + connect(contact, metal1) + connect(metal1, via1) + connect(via1, metal2) + connect(metal2, via2) + connect(via2, metal3) + connect(metal3, via3) + connect(via3, metal4) + connect(metal4, via4) + connect(via4, metal5) + connect(metal5, via5) + connect(via5, metaltop) + +end #CONNECTIVITY_RULES + +#================================================ +#------------ PRE-DEFINED FUNCTIONS ------------- +#================================================ + +def conn_space(layer,conn_val,not_conn_val, mode) + if conn_val > not_conn_val + raise "ERROR : Wrong connectivity implementation" + end + connected_output = layer.space(conn_val.um, mode).polygons(0.001) + unconnected_errors_unfiltered = layer.space(not_conn_val.um, mode) + singularity_errors = layer.space(0.001.um) + # Filter out the errors arising from the same net + unconnected_errors = DRC::DRCLayer::new(self, RBA::EdgePairs::new) + unconnected_errors_unfiltered.data.each do |ep| + net1 = l2n_data.probe_net(layer.data, ep.first.p1) + net2 = l2n_data.probe_net(layer.data, ep.second.p1) + if !net1 || !net2 + puts "Should not happen ..." + elsif net1.circuit != net2.circuit || net1.cluster_id != net2.cluster_id + # unconnected + unconnected_errors.data.insert(ep) + end + end + unconnected_output = unconnected_errors.polygons.or(singularity_errors.polygons(0.001)) + return connected_output, unconnected_output +end + +def conn_separation(layer1, layer2, conn_val,not_conn_val, mode) + if conn_val > not_conn_val + raise "ERROR : Wrong connectivity implementation" + end + connected_output = layer1.separation(layer2, conn_val.um, mode).polygons(0.001) + unconnected_errors_unfiltered = layer1.separation(layer2, not_conn_val.um, mode) + # Filter out the errors arising from the same net + unconnected_errors = DRC::DRCLayer::new(self, RBA::EdgePairs::new) + unconnected_errors_unfiltered.data.each do |ep| + net1 = l2n_data.probe_net(layer1.data, ep.first.p1) + net2 = l2n_data.probe_net(layer2.data, ep.second.p1) + if !net1 || !net2 + puts "Should not happen ..." + elsif net1.circuit != net2.circuit || net1.cluster_id != net2.cluster_id + # unconnected + unconnected_errors.data.insert(ep) + end + end + unconnected_output = unconnected_errors.polygons(0.001) + return connected_output, unconnected_output +end + +# === IMPLICIT EXTRACTION === +if CONNECTIVITY_RULES + logger.info("Connectivity rules enabled, Netlist object will be generated.") + netlist +end #CONNECTIVITY_RULES + +# === LAYOUT EXTENT === +CHIP = extent.sized(0.0) + +logger.info("Total area of the design is #{CHIP.area()} um^2.") + + + +#================================================ +#-------------------10V LDPMOS------------------- +#================================================ + +mdp_source = (pcomp).interacting(poly2.and(dualgate).and(ldmos_xtor).and(mvpsd)).not(poly2) +ldpmos = poly2.and(pcomp).and(dualgate).not(mvpsd).inside(ldmos_xtor) +# Rule MDP.1: Minimum transistor channel length. is 0.6µm +logger.info("Executing rule MDP.1") +mdp1_l1 = poly2.and(comp).inside(ldmos_xtor).inside(dualgate).enclosing(mvpsd, 0.6.um, euclidian).polygons(0.001) +mdp1_l1.output("MDP.1", "MDP.1 : Minimum transistor channel length. : 0.6µm") +mdp1_l1.forget + +mvpsd_mdp = mvpsd.edges.and(pcomp).and(poly2) +# Rule MDP.1a: Max transistor channel length. +logger.info("Executing rule MDP.1a") +mdp1a_l1 = poly2.edges.and(pcomp).or(mvpsd_mdp).and(ldmos_xtor).and(dualgate).not(pgate.not(mvpsd).edges.interacting(poly2.edges.and(pcomp).or(mvpsd_mdp)).width(20.001.um).edges) +mdp1a_l1.output("MDP.1a", "MDP.1a : Max transistor channel length.") +mdp1a_l1.forget + +mvpsd_mdp.forget +# Rule MDP.2: Minimum transistor channel width. is 4µm +logger.info("Executing rule MDP.2") +mdp2_l1 = poly2.and(comp).inside(ldmos_xtor).inside(dualgate).edges.not(mvpsd).interacting(mvpsd).width(4.um, euclidian).polygons(0.001) +mdp2_l1.output("MDP.2", "MDP.2 : Minimum transistor channel width. : 4µm") +mdp2_l1.forget + +mdp3_1 = ldpmos.or(mvpsd).or(mdp_source).not_interacting(ncomp.holes).inside(dualgate).inside(ldmos_xtor) +mdp3_2 = ncomp.holes.not_interacting(ncomp.interacting(mdp_source)).not_interacting(mvpsd,1,1).inside(dualgate).inside(ldmos_xtor) +# Rule MDP.3: Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL +logger.info("Executing rule MDP.3") +mdp3_l1 = mdp3_1.or(mdp3_2) +mdp3_l1.output("MDP.3", "MDP.3 : Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL") +mdp3_l1.forget + +ncomp_mdp3ai = ncomp.not_interacting(pcomp).inside(ldmos_xtor).inside(dualgate) +# Rule MDP.3ai: Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed. +logger.info("Executing rule MDP.3ai") +mdp3ai_l1 = ncomp_mdp3ai.separation(mvpsd, 1.um, euclidian).polygons(0.001).or(mvpsd.interacting(ncomp_mdp3ai)) +mdp3ai_l1.output("MDP.3ai", "MDP.3ai : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.") +mdp3ai_l1.forget + +ncomp_mdp3ai.forget +ncomp_mdp3aii = ncomp.interacting(pcomp).inside(ldmos_xtor).inside(dualgate) +# Rule MDP.3aii: Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed. +logger.info("Executing rule MDP.3aii") +mdp3aii_l1 = ncomp_mdp3aii.separation(mvpsd, 0.92.um, euclidian).polygons(0.001).or(mvpsd.interacting(ncomp_mdp3aii)) +mdp3aii_l1.output("MDP.3aii", "MDP.3aii : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.") +mdp3aii_l1.forget + +ncomp_mdp3aii.forget +ncomp_mdp3b = ncomp.inside(ldmos_xtor).inside(dualgate) +pcomp_mdp3b = pcomp.inside(dnwell).inside(ldmos_xtor).inside(dualgate) +# Rule MDP.3b: Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. is 0.4µm +logger.info("Executing rule MDP.3b") +mdp3b_l1 = ncomp_mdp3b.not(poly2).not(mvpsd).separation(pcomp_mdp3b.not(poly2).not(mvpsd), 0.4.um, euclidian).polygons(0.001) +mdp3b_l1.output("MDP.3b", "MDP.3b : Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. : 0.4µm") +mdp3b_l1.forget + +ncomp_mdp3b.forget +pcomp_mdp3b.forget +# Rule MDP.3c: Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). is 15µm +logger.info("Executing rule MDP.3c") +mdp3c_l1 = ncomp.inside(dnwell).inside(ldmos_xtor).inside(dualgate).not_interacting(ncomp.inside(dnwell).drc(separation(pcomp.inside(dnwell)) <= 15.um).first_edges,4) +mdp3c_l1.output("MDP.3c", "MDP.3c : Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). : 15µm") +mdp3c_l1.forget + +# Rule MDP.3d: The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. is 10µm +logger.info("Executing rule MDP.3d") +mdp3d_l1 = ncomp.interacting(ldmos_xtor.interacting(mvpsd)).interacting(dualgate).not(metal1).edges.not(metal1).with_length(10.001.um, nil) +mdp3d_l1.output("MDP.3d", "MDP.3d : The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. : 10µm") +mdp3d_l1.forget + +mdp4_metal = pcomp.not_interacting(mvpsd).interacting(ldmos_xtor.interacting(mvpsd)).interacting(dualgate).not(metal1).edges.not(metal1).with_length(10.001.um, nil) +# Rule MDP.4: DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. +logger.info("Executing rule MDP.4") +mdp4_l1 = pcomp.interacting(metal1).not_interacting(pcomp.holes).edges.and(ldmos_xtor).and(dualgate).or(mdp4_metal) +mdp4_l1.output("MDP.4", "MDP.4 : DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability.") +mdp4_l1.forget + +mdp4_metal.forget +# Rule MDP.4a: Min PCOMP (Pplus AND COMP) space to DNWELL. is 2.5µm +logger.info("Executing rule MDP.4a") +mdp4a_l1 = pcomp.inside(ldmos_xtor).inside(dualgate).separation(dnwell.inside(ldmos_xtor).inside(dualgate), 2.5.um, euclidian).polygons(0.001) +mdp4a_l1.output("MDP.4a", "MDP.4a : Min PCOMP (Pplus AND COMP) space to DNWELL. : 2.5µm") +mdp4a_l1.forget + +mdp4b_dnwell_edges = dnwell.inside(ldmos_xtor).inside(dualgate).edges.centers(0, 0.99) +mdp4b_not_error = dnwell.drc(separation(pcomp.inside(ldmos_xtor.interacting(mvpsd)).inside(dualgate).not_interacting(mvpsd), euclidian) <= 15.um).polygons(0.001) +# Rule MDP.4b: Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. is 15µm +logger.info("Executing rule MDP.4b") +mdp4b_l1 = mdp4b_dnwell_edges.not_interacting(mdp4b_not_error).and(pcomp.holes).extended(0, 0, 0.001, 0.001) +mdp4b_l1.output("MDP.4b", "MDP.4b : Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. : 15µm") +mdp4b_l1.forget + +mdp4b_dnwell_edges.forget +mdp4b_not_error.forget +# Rule MDP.5: Each LDPMOS shall be covered by Dualgate layer. +logger.info("Executing rule MDP.5") +mdp5_l1 = pcomp.not(poly2).not(mvpsd).or(pgate.not(mvpsd)).or(pcomp.and(mvpsd)).inside(ldmos_xtor).not_inside(dualgate) +mdp5_l1.output("MDP.5", "MDP.5 : Each LDPMOS shall be covered by Dualgate layer.") +mdp5_l1.forget + +# Rule MDP.5a: Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). is 0.5µm +logger.info("Executing rule MDP.5a") +mdp5a_l1 = dualgate.interacting(ldmos_xtor).enclosing(pcomp.inside(ldmos_xtor), 0.5.um, euclidian).polygons(0.001) +mdp5a_l2 = pcomp.inside(ldmos_xtor).not_outside(dualgate.interacting(ldmos_xtor)).not(dualgate.interacting(ldmos_xtor)) +mdp5a_l = mdp5a_l1.or(mdp5a_l2) +mdp5a_l.output("MDP.5a", "MDP.5a : Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). : 0.5µm") +mdp5a_l1.forget +mdp5a_l2.forget +mdp5a_l.forget + +# Rule MDP.6: Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer. +logger.info("Executing rule MDP.6") +mdp6_l1 = mvpsd.not_inside(ldmos_xtor) +mdp6_l1.output("MDP.6", "MDP.6 : Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer.") +mdp6_l1.forget + +# Rule MDP.6a: Minimum LDMOS_XTOR enclose Dualgate. +logger.info("Executing rule MDP.6a") +mdp6a_l1 = ldmos_xtor.not_covering(dualgate) +mdp6a_l1.output("MDP.6a", "MDP.6a : Minimum LDMOS_XTOR enclose Dualgate.") +mdp6a_l1.forget + +# Rule MDP.7: Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. is 2µm +logger.info("Executing rule MDP.7") +mdp7_l1 = ldmos_xtor.separation(nwell.outside(ldmos_xtor), 2.um, euclidian).polygons(0.001) +mdp7_l1.output("MDP.7", "MDP.7 : Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. : 2µm") +mdp7_l1.forget + +# Rule MDP.8: Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. is 1.5µm +logger.info("Executing rule MDP.8") +mdp8_l1 = ldmos_xtor.separation(ncomp.outside(ldmos_xtor), 1.5.um, euclidian).polygons(0.001) +mdp8_l1.output("MDP.8", "MDP.8 : Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. : 1.5µm") +mdp8_l1.forget + +# Rule MDP.9a: Min LDPMOS POLY2 width. is 1.2µm +logger.info("Executing rule MDP.9a") +mdp9a_l1 = poly2.inside(dnwell.and(dualgate).and(ldmos_xtor)).width(1.2.um, euclidian).polygons(0.001) +mdp9a_l1.output("MDP.9a", "MDP.9a : Min LDPMOS POLY2 width. : 1.2µm") +mdp9a_l1.forget + +mdp9b_1 = poly2.inside(dnwell.and(dualgate).and(ldmos_xtor)).edges.interacting(mvpsd).not(mvpsd).enclosing(comp.edges,0.4.um).edges +mdp9b_2 = poly2.inside(dnwell.and(dualgate).and(ldmos_xtor)).edges.interacting(mvpsd).not(mvpsd).interacting(pcomp) +# Rule MDP.9b: Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). is 0.4µm +logger.info("Executing rule MDP.9b") +mdp9b_l1 = mdp9b_1.or(mdp9b_2).extended(0,0,0.001,0.001) +mdp9b_l1.output("MDP.9b", "MDP.9b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). : 0.4µm") +mdp9b_l1.forget + +mdp9b_1.forget +mdp9b_2.forget +# Rule MDP.9c: Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction. +logger.info("Executing rule MDP.9c") +mdp9c_l1 = poly2.edges.in(poly2.inside(dnwell.and(dualgate).and(ldmos_xtor)).edges.inside_part(mvpsd)).not_interacting(poly2.drc(enclosing(comp,projection) == 0.2.um)) +mdp9c_l1.output("MDP.9c", "MDP.9c : Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction.") +mdp9c_l1.forget + +# Rule MDP.9d: Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space. +logger.info("Executing rule MDP.9d") +mdp9d_l1 = poly2.inside(dualgate).inside(ldmos_xtor).overlapping(mvpsd.and(pcomp).not(poly2).sized(0.16.um)).or(poly2.inside(dualgate).inside(ldmos_xtor.interacting(mvpsd)).not_interacting(mvpsd.and(pcomp).not(poly2).sized(0.16.um))) +mdp9d_l1.output("MDP.9d", "MDP.9d : Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space.") +mdp9d_l1.forget + +ldpmos_poly2_gate = poly2.interacting(pgate.and(dualgate).not(mvpsd)) +ncomp_not_butted = ncomp.not(pplus).not_interacting(pcomp.not(nplus)).or(ncomp.not(pplus).overlapping(pcomp.not(nplus))) +mdp9ei_1 = ldpmos_poly2_gate.inside(dualgate).inside(ldmos_xtor).separation(ncomp_not_butted, 0.4.um).polygons(0.001) +mdp9ei_2 = ldpmos_poly2_gate.inside(dualgate).inside(ldmos_xtor).and(ncomp_not_butted) +# Rule MDP.9ei: Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted). +logger.info("Executing rule MDP.9ei") +mdp9ei_l1 = mdp9ei_1.or(mdp9ei_2) +mdp9ei_l1.output("MDP.9ei", "MDP.9ei : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted).") +mdp9ei_l1.forget + +ncomp_not_butted.forget +mdp9ei_1.forget +mdp9ei_2.forget +ncomp_butted = ncomp.not(pplus).interacting(pcomp.not(nplus)).not_overlapping(pcomp.not(nplus)) +mdp9eii_1 = ldpmos_poly2_gate.inside(dualgate).inside(ldmos_xtor).separation(ncomp_butted, 0.32.um).polygons(0.001) +mdp9eii_2 = ldpmos_poly2_gate.inside(dualgate).inside(ldmos_xtor).and(ncomp_butted) +# Rule MDP.9eii: Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted). +logger.info("Executing rule MDP.9eii") +mdp9eii_l1 = mdp9eii_1.or(mdp9eii_2) +mdp9eii_l1.output("MDP.9eii", "MDP.9eii : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted).") +mdp9eii_l1.forget + +ncomp_butted.forget +mdp9eii_1.forget +mdp9eii_2.forget +# Rule MDP.9f: Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). is -µm +logger.info("Executing rule MDP.9f") +mdp9f_l1 = poly2.not(pplus).inside(dualgate).inside(ldmos_xtor).interacting(poly2.and(pplus).inside(dualgate).inside(ldmos_xtor),2) +mdp9f_l1.output("MDP.9f", "MDP.9f : Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). : -µm") +mdp9f_l1.forget + +# Rule MDP.10: Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus). +logger.info("Executing rule MDP.10") +mdp10_l1 = mvpsd.inside(dualgate).inside(ldmos_xtor).not_interacting(mvpsd.drc(overlap(ldmos_xtor.and(comp).and(poly2).and(pplus),projection) == 0.4)) +mdp10_l1.output("MDP.10", "MDP.10 : Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus).") +mdp10_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_mdp_10b, unconnected_mdp_10a = conn_space(mvpsd, 1, 2, euclidian) + +# Rule MDP.10a: Min MVPSD space within LDMOS_XTOR marking [diff potential]. is 2µm +logger.info("Executing rule MDP.10a") +mdp10a_l1 = unconnected_mdp_10a +mdp10a_l1.output("MDP.10a", "MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm") +mdp10a_l1.forget + +# Rule MDP.10b: Min MVPSD space [same potential]. Merge if space less than 1um. is 1µm +logger.info("Executing rule MDP.10b") +mdp10b_l1 = connected_mdp_10b +mdp10b_l1.output("MDP.10b", "MDP.10b : Min MVPSD space [same potential]. Merge if space less than 1um. : 1µm") +mdp10b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule MDP.10a: Min MVPSD space within LDMOS_XTOR marking [diff potential]. is 2µm +logger.info("Executing rule MDP.10a") +mdp10a_l1 = mvpsd.space(2.um, euclidian).polygons(0.001) +mdp10a_l1.output("MDP.10a", "MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm") +mdp10a_l1.forget + +end #CONNECTIVITY_RULES + +# Rule MDP.11: Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width. +logger.info("Executing rule MDP.11") +mdp11_l1 = mvpsd.edges.not_interacting(pcomp.edges).enclosing(pcomp.edges, 0.8.um, euclidian).polygons(0.001).or(mvpsd.interacting(mvpsd.edges.and(pcomp.edges))) +mdp11_l1.output("MDP.11", "MDP.11 : Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width.") +mdp11_l1.forget + +# Rule MDP.12: Min DNWELL enclose Nplus guard ring (NCOMP). is 0.66µm +logger.info("Executing rule MDP.12") +mdp12_l1 = dnwell.inside(dualgate).inside(ldmos_xtor).enclosing(ncomp.inside(dualgate).inside(ldmos_xtor), 0.66.um, euclidian).polygons(0.001) +mdp12_l2 = ncomp.inside(dualgate).inside(ldmos_xtor).not_outside(dnwell.inside(dualgate).inside(ldmos_xtor)).not(dnwell.inside(dualgate).inside(ldmos_xtor)) +mdp12_l = mdp12_l1.or(mdp12_l2) +mdp12_l.output("MDP.12", "MDP.12 : Min DNWELL enclose Nplus guard ring (NCOMP). : 0.66µm") +mdp12_l1.forget +mdp12_l2.forget +mdp12_l.forget + +# rule MDP.13 is not a DRC check + +# Rule MDP.13a: Max single finger width. is 50µm +logger.info("Executing rule MDP.13a") +mdp13a_l1 = poly2.and(pcomp).not(mvpsd).inside(dualgate).inside(ldmos_xtor).edges.with_length(50.001.um,nil).extended(0, 0, 0.001, 0.001) +mdp13a_l1.output("MDP.13a", "MDP.13a : Max single finger width. : 50µm") +mdp13a_l1.forget + +# Rule MDP.13b: Layout shall have alternative source & drain. +logger.info("Executing rule MDP.13b") +mdp13b_l1 = ldpmos.not_interacting(mdp_source,1,1).or(ldpmos.not_interacting(mvpsd,1,1)).or(mdp_source.interacting(mvpsd)) +mdp13b_l1.output("MDP.13b", "MDP.13b : Layout shall have alternative source & drain.") +mdp13b_l1.forget + +mdp_13c_source_side = ldpmos.interacting(mdp_source.interacting(ldpmos, 2, 2).or(mdp_source.interacting(ncomp.interacting(mdp_source, 2, 2)))) +# Rule MDP.13c: Both sides of the transistor shall be terminated by source. +logger.info("Executing rule MDP.13c") +mdp13c_l1 = mvpsd.covering(pcomp.not_interacting(poly2)).interacting(pcomp, 2, 2).interacting(mdp_13c_source_side) +mdp13c_l1.output("MDP.13c", "MDP.13c : Both sides of the transistor shall be terminated by source.") +mdp13c_l1.forget + +mdp_13c_source_side.forget +# rule MDP.14 is not a DRC check + +# Rule MDP.15: Min DNWELL enclosing MVPSD to any DNWELL spacing. is 6µm +logger.info("Executing rule MDP.15") +mdp15_l1 = dnwell.separation(dnwell.covering(mvpsd).inside(dualgate).inside(ldmos_xtor), 6.um, euclidian).polygons(0.001) +mdp15_l1.output("MDP.15", "MDP.15 : Min DNWELL enclosing MVPSD to any DNWELL spacing. : 6µm") +mdp15_l1.forget + +# Rule MDP.16a: Min LDPMOS drain COMP width. is 0.22µm +logger.info("Executing rule MDP.16a") +mdp16a_l1 = comp.inside(mvpsd).inside(dualgate).inside(ldmos_xtor).width(0.22.um, euclidian).polygons(0.001) +mdp16a_l1.output("MDP.16a", "MDP.16a : Min LDPMOS drain COMP width. : 0.22µm") +mdp16a_l1.forget + +# Rule MDP.16b: Min LDPMOS drain COMP enclose contact. is 0µm +logger.info("Executing rule MDP.16b") +mdp16b_l1 = contact.interacting(pcomp.inside(mvpsd).inside(dualgate).inside(ldmos_xtor)).not_inside(pcomp.inside(mvpsd)) +mdp16b_l1.output("MDP.16b", "MDP.16b : Min LDPMOS drain COMP enclose contact. : 0µm") +mdp16b_l1.forget + +mdp17_a1 = mvpsd.inside(dnwell).inside(ldmos_xtor) +mdp17_a2 = ncomp.outside(dnwell).outside(nwell) +# Rule MDP.17a: For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um. +logger.info("Executing rule MDP.17a") +mdp17a_l1 = mdp17_a1.separation(mdp17_a2,transparent,40.um).polygons(0.001).not_interacting(ncomp.and(dnwell).holes) +mdp17a_l1.output("MDP.17a", "MDP.17a : For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um.") +mdp17a_l1.forget + +mdp17_a1.forget +mdp17_a2.forget +# Rule MDP.17c: DNWELL guard ring shall have NCOMP tab to be connected to highest potential +logger.info("Executing rule MDP.17c") +mdp17c_l1 = dnwell.with_holes.not_covering(ncomp) +mdp17c_l1.output("MDP.17c", "MDP.17c : DNWELL guard ring shall have NCOMP tab to be connected to highest potential") +mdp17c_l1.forget + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/3.3v_sram.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/3.3v_sram.drc new file mode 100644 index 000000000..db610479a --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/3.3v_sram.drc @@ -0,0 +1,268 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#---------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (3.3V SRAM) ---------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +contact = polygons(33 , 0 ) +metal1 = polygons(34 , 0 ) +sramcore = polygons(108, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#-------------------3.3V SRAM-------------------- +#================================================ + +# Rule S.DF.4c_LV: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.4µm +logger.info("Executing rule S.DF.4c_LV") +sdf4c_l1 = nwell.outside(dnwell).inside(sramcore).enclosing(pcomp.outside(dnwell).inside(sramcore), 0.4.um, euclidian).polygons(0.001) +sdf4c_l2 = pcomp.outside(dnwell).inside(sramcore).not_outside(nwell.outside(dnwell).inside(sramcore)).not(nwell.outside(dnwell).inside(sramcore)) +sdf4c_l = sdf4c_l1.or(sdf4c_l2).not_interacting(v5_xtor).not_interacting(dualgate) +sdf4c_l.output("S.DF.4c_LV", "S.DF.4c_LV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.4µm") +sdf4c_l1.forget +sdf4c_l2.forget +sdf4c_l.forget + +# Rule S.DF.16_LV: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.4µm +logger.info("Executing rule S.DF.16_LV") +sdf16_l1 = ncomp.outside(nwell).outside(dnwell).inside(sramcore).separation(nwell.outside(dnwell).inside(sramcore), 0.4.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +sdf16_l1.output("S.DF.16_LV", "S.DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.4µm") +sdf16_l1.forget + +# Rule S.CO.3_LV: Poly2 overlap of contact. is 0.04µm +logger.info("Executing rule S.CO.3_LV") +sco3_l1 = poly2.inside(sramcore).enclosing(contact.inside(sramcore), 0.04.um, euclidian).polygons(0.001) +sco3_l2 = contact.inside(sramcore).not_outside(poly2.inside(sramcore)).not(poly2.inside(sramcore)) +sco3_l = sco3_l1.or(sco3_l2).not_interacting(v5_xtor).not_interacting(dualgate) +sco3_l.output("S.CO.3_LV", "S.CO.3_LV : Poly2 overlap of contact. : 0.04µm") +sco3_l1.forget +sco3_l2.forget +sco3_l.forget + +# Rule S.CO.4_LV: COMP overlap of contact. is 0.03µm +logger.info("Executing rule S.CO.4_LV") +sco4_l1 = comp.inside(sramcore).enclosing(contact.inside(sramcore), 0.03.um, euclidian).polygons(0.001) +sco4_l2 = contact.inside(sramcore).not_outside(comp.inside(sramcore)).not(comp.inside(sramcore)) +sco4_l = sco4_l1.or(sco4_l2).not_interacting(v5_xtor).not_interacting(dualgate) +sco4_l.output("S.CO.4_LV", "S.CO.4_LV : COMP overlap of contact. : 0.03µm") +sco4_l1.forget +sco4_l2.forget +sco4_l.forget + +# Rule S.CO.6_ii_LV: (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap +logger.info("Executing rule S.CO.6_ii_LV") +sco6_l1 = metal1.and(sramcore).enclosing(contact.inside(sramcore), 0.02.um, euclidian).polygons(0.001).or(contact.inside(sramcore).not(metal1.inside(sramcore))).not_interacting(v5_xtor).not_interacting(dualgate) +sco6_l1.output("S.CO.6_ii_LV", "S.CO.6_ii_LV : (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap") +sco6_l1.forget + +# Rule S.M1.1_LV: min. metal1 width is 0.22µm +logger.info("Executing rule S.M1.1_LV") +sm11_l1 = metal1.and(sramcore).width(0.22.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +sm11_l1.output("S.M1.1_LV", "S.M1.1_LV : min. metal1 width : 0.22µm") +sm11_l1.forget + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/5v_sram.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/5v_sram.drc new file mode 100644 index 000000000..22753ae65 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/5v_sram.drc @@ -0,0 +1,280 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (5V SRAM) ----------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +lvpwell = polygons(204, 0 ) +contact = polygons(33 , 0 ) +sramcore = polygons(108, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#--------------------5V SRAM--------------------- +#================================================ + +# Rule S.DF.4c_MV: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.45µm +logger.info("Executing rule S.DF.4c_MV") +sdf4c_l1 = nwell.outside(dnwell).inside(sramcore).enclosing(pcomp.outside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001) +sdf4c_l2 = pcomp.outside(dnwell).inside(sramcore).not_outside(nwell.outside(dnwell).inside(sramcore)).not(nwell.outside(dnwell).inside(sramcore)) +sdf4c_l = sdf4c_l1.or(sdf4c_l2).overlapping(v5_xtor).overlapping(dualgate) +sdf4c_l.output("S.DF.4c_MV", "S.DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.45µm") +sdf4c_l1.forget +sdf4c_l2.forget +sdf4c_l.forget + +# Rule S.DF.6_MV: Min. COMP extend beyond gate (it also means source/drain overhang). is 0.32µm +logger.info("Executing rule S.DF.6_MV") +sdf6_l1 = comp.inside(sramcore).enclosing(poly2.inside(sramcore), 0.32.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) +sdf6_l1.output("S.DF.6_MV", "S.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.32µm") +sdf6_l1.forget + +# Rule S.DF.7_MV: Min. (LVPWELL Spacer to PCOMP) inside DNWELL. is 0.45µm +logger.info("Executing rule S.DF.7_MV") +sdf7_l1 = pcomp.inside(dnwell).inside(sramcore).separation(lvpwell.inside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) +sdf7_l1.output("S.DF.7_MV", "S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.45µm") +sdf7_l1.forget + +# Rule S.DF.8_MV: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.45µm +logger.info("Executing rule S.DF.8_MV") +sdf8_l1 = lvpwell.inside(dnwell).inside(sramcore).enclosing(ncomp.inside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001) +sdf8_l2 = ncomp.inside(dnwell).inside(sramcore).not_outside(lvpwell.inside(dnwell).inside(sramcore)).not(lvpwell.inside(dnwell).inside(sramcore)) +sdf8_l = sdf8_l1.or(sdf8_l2).overlapping(v5_xtor).overlapping(dualgate) +sdf8_l.output("S.DF.8_MV", "S.DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.45µm") +sdf8_l1.forget +sdf8_l2.forget +sdf8_l.forget + +# Rule S.DF.16_MV: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.45µm +logger.info("Executing rule S.DF.16_MV") +sdf16_l1 = ncomp.outside(nwell).outside(dnwell).inside(sramcore).separation(nwell.outside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) +sdf16_l1.output("S.DF.16_MV", "S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.45µm") +sdf16_l1.forget + +# Rule S.PL.5a_MV: Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. is 0.12µm +logger.info("Executing rule S.PL.5a_MV") +spl5a_l1 = poly2.inside(sramcore).separation(comp.inside(sramcore), 0.12.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) +spl5a_l1.output("S.PL.5a_MV", "S.PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.12µm") +spl5a_l1.forget + +# Rule S.PL.5b_MV: Space from field Poly2 to related COMP. is 0.12µm +logger.info("Executing rule S.PL.5b_MV") +spl5b_l1 = poly2.inside(sramcore).separation(comp.inside(sramcore), 0.12.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) +spl5b_l1.output("S.PL.5b_MV", "S.PL.5b_MV : Space from field Poly2 to related COMP. : 0.12µm") +spl5b_l1.forget + +# Rule S.CO.4_MV: COMP overlap of contact. is 0.04µm +logger.info("Executing rule S.CO.4_MV") +sco4_l1 = comp.inside(sramcore).and(v5_xtor).enclosing(contact.inside(sramcore).and(v5_xtor), 0.04.um, euclidian).polygons(0.001) +sco4_l2 = contact.inside(sramcore).and(v5_xtor).not_outside(comp.inside(sramcore).and(v5_xtor)).not(comp.inside(sramcore).and(v5_xtor)) +sco4_l = sco4_l1.or(sco4_l2) +sco4_l.output("S.CO.4_MV", "S.CO.4_MV : COMP overlap of contact. : 0.04µm") +sco4_l1.forget +sco4_l2.forget +sco4_l.forget + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/comp.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/comp.drc new file mode 100644 index 000000000..f98c6072f --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/comp.drc @@ -0,0 +1,634 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (COMP) ------------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +lvpwell = polygons(204, 0 ) +mvsd = polygons(210, 0 ) +mvpsd = polygons(11 , 39) +schottky_diode = polygons(241, 0 ) +res_mk = polygons(110, 5 ) +cap_mk = polygons(117, 5 ) +mos_cap_mk = polygons(166, 5 ) +drc_bjt = polygons(127, 5 ) +otp_mk = polygons(173, 5 ) +neo_ee_mk = polygons(88 , 17) +sramcore = polygons(108, 5 ) +ymtp_mk = polygons(86 , 17) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#----------------------COMP---------------------- +#================================================ + + +if FEOL +logger.info("FEOL section") + +# Rule FATAL.FATAL: Nplus can’t overlap with pplus +logger.info("Executing rule FATAL.FATAL") +fatalfatal_l1 = nplus.and(pplus) +fatalfatal_l1.output("FATAL.FATAL", "FATAL.FATAL : Nplus can’t overlap with pplus") +fatalfatal_l1.forget + +# Rule DF.1a_3.3V: Min. COMP Width. is 0.22µm +logger.info("Executing rule DF.1a_3.3V") +df1a_l1 = comp.width(0.22.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df1a_l1.output("DF.1a_3.3V", "DF.1a_3.3V : Min. COMP Width. : 0.22µm") +df1a_l1.forget + +# Rule DF.1a_5V: Min. COMP Width. is 0.3µm +logger.info("Executing rule DF.1a_5V") +df1a_l1 = comp.not_inside(mvsd).not_inside(mvpsd).width(0.3.um, euclidian).polygons(0.001).overlapping(dualgate) +df1a_l1.output("DF.1a_5V", "DF.1a_5V : Min. COMP Width. : 0.3µm") +df1a_l1.forget + +# rule DF.1b_3.3V is not a DRC check + +# rule DF.1b_5V is not a DRC check + +# Rule DF.1c_3.3V: Min. COMP Width for MOSCAP. is 1µm +logger.info("Executing rule DF.1c_3.3V") +df1c_l1 = comp.and(mos_cap_mk).width(1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df1c_l1.output("DF.1c_3.3V", "DF.1c_3.3V : Min. COMP Width for MOSCAP. : 1µm") +df1c_l1.forget + +# Rule DF.1c_5V: Min. COMP Width for MOSCAP. is 1µm +logger.info("Executing rule DF.1c_5V") +df1c_l1 = comp.and(mos_cap_mk).width(1.um, euclidian).polygons(0.001).overlapping(dualgate) +df1c_l1.output("DF.1c_5V", "DF.1c_5V : Min. COMP Width for MOSCAP. : 1µm") +df1c_l1.forget + +df_2a = comp.not(poly2).edges.and(tgate.edges) +# Rule DF.2a_3.3V: Min Channel Width. is nil,0.22µm +logger.info("Executing rule DF.2a_3.3V") +df2a_l1 = df_2a.with_length(nil,0.22.um).extended(0, 0, 0.001, 0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df2a_l1.output("DF.2a_3.3V", "DF.2a_3.3V : Min Channel Width. : nil,0.22µm") +df2a_l1.forget + +# Rule DF.2a_5V: Min Channel Width. is nil,0.3µm +logger.info("Executing rule DF.2a_5V") +df2a_l1 = df_2a.with_length(nil,0.3.um).extended(0, 0, 0.001, 0.001).overlapping(dualgate) +df2a_l1.output("DF.2a_5V", "DF.2a_5V : Min Channel Width. : nil,0.3µm") +df2a_l1.forget + +df_2a.forget +df_2b = comp.drc(width <= 100.um).polygons(0.001).not_inside(mos_cap_mk) +# Rule DF.2b_3.3V: Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer. +logger.info("Executing rule DF.2b_3.3V") +df2b_l1 = comp.not_inside(mos_cap_mk).not_interacting(df_2b).not_interacting(v5_xtor).not_interacting(dualgate) +df2b_l1.output("DF.2b_3.3V", "DF.2b_3.3V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.") +df2b_l1.forget + +# Rule DF.2b_5V: Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer. +logger.info("Executing rule DF.2b_5V") +df2b_l1 = comp.not_inside(mos_cap_mk).not_interacting(df_2b).overlapping(dualgate) +df2b_l1.output("DF.2b_5V", "DF.2b_5V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.") +df2b_l1.forget + +df_2b.forget +# Rule DF.3a_3.3V: Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. is 0.28µm +logger.info("Executing rule DF.3a_3.3V") +df3a_l1 = comp.not(otp_mk).space(0.28.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df3a_l1.output("DF.3a_3.3V", "DF.3a_3.3V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.28µm") +df3a_l1.forget + +# Rule DF.3a_5V: Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. is 0.36µm +logger.info("Executing rule DF.3a_5V") +df3a_l1 = comp.not(otp_mk).space(0.36.um, euclidian).polygons(0.001).overlapping(dualgate) +df3a_l1.output("DF.3a_5V", "DF.3a_5V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.36µm") +df3a_l1.forget + +df_3b_same_well = ncomp.inside(nwell).not_outside(pcomp.inside(nwell)).or(ncomp.inside(lvpwell).not_outside(pcomp.inside(lvpwell))) +df_3b_moscap = ncomp.inside(nwell).interacting(pcomp.inside(nwell)).or(ncomp.inside(lvpwell).interacting(pcomp.inside(lvpwell))).inside(mos_cap_mk) +# Rule DF.3b_3.3V: Min./Max. NCOMP Space to PCOMP in the same well for butted COMP (MOSCAP butting is not allowed). +logger.info("Executing rule DF.3b_3.3V") +df3b_l1 = df_3b_same_well.or(df_3b_moscap).not_interacting(v5_xtor).not_interacting(dualgate) +df3b_l1.output("DF.3b_3.3V", "DF.3b_3.3V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP (MOSCAP butting is not allowed).") +df3b_l1.forget + +# Rule DF.3b_5V: Min./Max. NCOMP Space to PCOMP in the same well for butted COMP(MOSCAP butting is not allowed). +logger.info("Executing rule DF.3b_5V") +df3b_l1 = df_3b_same_well.or(df_3b_moscap).overlapping(dualgate) +df3b_l1.output("DF.3b_5V", "DF.3b_5V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP(MOSCAP butting is not allowed).") +df3b_l1.forget + +df_3b_same_well.forget +df_3b_moscap.forget +# Rule DF.3c_3.3V: Min. COMP Space in BJT area (area marked by DRC_BJT layer). is 0.32µm +logger.info("Executing rule DF.3c_3.3V") +df3c_l1 = comp.inside(drc_bjt).space(0.32.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df3c_l1.output("DF.3c_3.3V", "DF.3c_3.3V : Min. COMP Space in BJT area (area marked by DRC_BJT layer). : 0.32µm") +df3c_l1.forget + +# Rule DF.3c_5V: Min. COMP Space in BJT area (area marked by DRC_BJT layer) hasn’t been assessed. +logger.info("Executing rule DF.3c_5V") +df3c_l1 = comp.interacting(comp.inside(drc_bjt).and(dualgate).space(10.um, euclidian).polygons(0.001)) +df3c_l1.output("DF.3c_5V", "DF.3c_5V : Min. COMP Space in BJT area (area marked by DRC_BJT layer) hasn’t been assessed.") +df3c_l1.forget + +ntap_dnwell = ncomp.not_interacting(tgate).inside(dnwell) +# Rule DF.4a_3.3V: Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. is 0.12µm +logger.info("Executing rule DF.4a_3.3V") +df4a_l1 = ntap_dnwell.separation(lvpwell.inside(dnwell), 0.12.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df4a_l1.output("DF.4a_3.3V", "DF.4a_3.3V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.12µm") +df4a_l1.forget + +# Rule DF.4a_5V: Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. is 0.16µm +logger.info("Executing rule DF.4a_5V") +df4a_l1 = ntap_dnwell.separation(lvpwell.inside(dnwell), 0.16.um, euclidian).polygons(0.001).overlapping(dualgate) +df4a_l1.output("DF.4a_5V", "DF.4a_5V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.16µm") +df4a_l1.forget + +# Rule DF.4b_3.3V: Min. DNWELL overlap of NCOMP well tap. is 0.62µm +logger.info("Executing rule DF.4b_3.3V") +df4b_l1 = dnwell.enclosing(ncomp.not_interacting(tgate), 0.62.um, euclidian).polygons(0.001) +df4b_l2 = ncomp.not_interacting(tgate).not_outside(dnwell).not(dnwell) +df4b_l = df4b_l1.or(df4b_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df4b_l.output("DF.4b_3.3V", "DF.4b_3.3V : Min. DNWELL overlap of NCOMP well tap. : 0.62µm") +df4b_l1.forget +df4b_l2.forget +df4b_l.forget + +# Rule DF.4b_5V: Min. DNWELL overlap of NCOMP well tap. is 0.66µm +logger.info("Executing rule DF.4b_5V") +df4b_l1 = dnwell.enclosing(ncomp.not_interacting(tgate), 0.66.um, euclidian).polygons(0.001) +df4b_l2 = ncomp.not_interacting(tgate).not_outside(dnwell).not(dnwell) +df4b_l = df4b_l1.or(df4b_l2).overlapping(dualgate) +df4b_l.output("DF.4b_5V", "DF.4b_5V : Min. DNWELL overlap of NCOMP well tap. : 0.66µm") +df4b_l1.forget +df4b_l2.forget +df4b_l.forget + +ntap_dnwell.forget +nwell_n_dnwell = nwell.outside(dnwell) +# Rule DF.4c_3.3V: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.43µm +logger.info("Executing rule DF.4c_3.3V") +df4c_l1 = nwell_n_dnwell.outside(sramcore).enclosing(pcomp.outside(dnwell), 0.43.um, euclidian).polygons(0.001) +df4c_l2 = pcomp.outside(dnwell).not_outside(nwell_n_dnwell.outside(sramcore)).not(nwell_n_dnwell.outside(sramcore)) +df4c_l = df4c_l1.or(df4c_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df4c_l.output("DF.4c_3.3V", "DF.4c_3.3V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.43µm") +df4c_l1.forget +df4c_l2.forget +df4c_l.forget + +# Rule DF.4c_5V: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.6µm +logger.info("Executing rule DF.4c_5V") +df4c_l1 = nwell_n_dnwell.outside(sramcore).enclosing(pcomp.outside(dnwell), 0.6.um, euclidian).polygons(0.001) +df4c_l2 = pcomp.outside(dnwell).not_outside(nwell_n_dnwell.outside(sramcore)).not(nwell_n_dnwell.outside(sramcore)) +df4c_l = df4c_l1.or(df4c_l2).overlapping(dualgate) +df4c_l.output("DF.4c_5V", "DF.4c_5V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.6µm") +df4c_l1.forget +df4c_l2.forget +df4c_l.forget + +# Rule DF.4d_3.3V: Min. (Nwell overlap of NCOMP) outside DNWELL. is 0.12µm +logger.info("Executing rule DF.4d_3.3V") +df4d_l1 = nwell_n_dnwell.not_inside(ymtp_mk).not_inside(neo_ee_mk).enclosing(ncomp.outside(dnwell).not_inside(ymtp_mk), 0.12.um, euclidian).polygons(0.001) +df4d_l2 = ncomp.outside(dnwell).not_inside(ymtp_mk).not_outside(nwell_n_dnwell.not_inside(ymtp_mk).not_inside(neo_ee_mk)).not(nwell_n_dnwell.not_inside(ymtp_mk).not_inside(neo_ee_mk)) +df4d_l = df4d_l1.or(df4d_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df4d_l.output("DF.4d_3.3V", "DF.4d_3.3V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.12µm") +df4d_l1.forget +df4d_l2.forget +df4d_l.forget + +# Rule DF.4d_5V: Min. (Nwell overlap of NCOMP) outside DNWELL. is 0.16µm +logger.info("Executing rule DF.4d_5V") +df4d_l1 = nwell_n_dnwell.not_inside(ymtp_mk).enclosing(ncomp.outside(dnwell).not_inside(ymtp_mk), 0.16.um, euclidian).polygons(0.001) +df4d_l2 = ncomp.outside(dnwell).not_inside(ymtp_mk).not_outside(nwell_n_dnwell.not_inside(ymtp_mk)).not(nwell_n_dnwell.not_inside(ymtp_mk)) +df4d_l = df4d_l1.or(df4d_l2).overlapping(dualgate) +df4d_l.output("DF.4d_5V", "DF.4d_5V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.16µm") +df4d_l1.forget +df4d_l2.forget +df4d_l.forget + +nwell_n_dnwell.forget +# Rule DF.4e_3.3V: Min. DNWELL overlap of PCOMP. is 0.93µm +logger.info("Executing rule DF.4e_3.3V") +df4e_l1 = dnwell.enclosing(pcomp, 0.93.um, euclidian).polygons(0.001) +df4e_l2 = pcomp.not_outside(dnwell).not(dnwell) +df4e_l = df4e_l1.or(df4e_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df4e_l.output("DF.4e_3.3V", "DF.4e_3.3V : Min. DNWELL overlap of PCOMP. : 0.93µm") +df4e_l1.forget +df4e_l2.forget +df4e_l.forget + +# Rule DF.4e_5V: Min. DNWELL overlap of PCOMP. is 1.1µm +logger.info("Executing rule DF.4e_5V") +df4e_l1 = dnwell.enclosing(pcomp, 1.1.um, euclidian).polygons(0.001) +df4e_l2 = pcomp.not_outside(dnwell).not(dnwell) +df4e_l = df4e_l1.or(df4e_l2).overlapping(dualgate) +df4e_l.output("DF.4e_5V", "DF.4e_5V : Min. DNWELL overlap of PCOMP. : 1.1µm") +df4e_l1.forget +df4e_l2.forget +df4e_l.forget + +pwell_dnwell = lvpwell.inside(dnwell) +# Rule DF.5_3.3V: Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. is 0.12µm +logger.info("Executing rule DF.5_3.3V") +df5_l1 = pwell_dnwell.enclosing(pcomp.outside(nwell), 0.12.um, euclidian).polygons(0.001) +df5_l2 = pcomp.outside(nwell).not_outside(pwell_dnwell).not(pwell_dnwell) +df5_l = df5_l1.or(df5_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df5_l.output("DF.5_3.3V", "DF.5_3.3V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.12µm") +df5_l1.forget +df5_l2.forget +df5_l.forget + +# Rule DF.5_5V: Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. is 0.16µm +logger.info("Executing rule DF.5_5V") +df5_l1 = pwell_dnwell.enclosing(pcomp.outside(nwell), 0.16.um, euclidian).polygons(0.001) +df5_l2 = pcomp.outside(nwell).not_outside(pwell_dnwell).not(pwell_dnwell) +df5_l = df5_l1.or(df5_l2).overlapping(dualgate) +df5_l.output("DF.5_5V", "DF.5_5V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.16µm") +df5_l1.forget +df5_l2.forget +df5_l.forget + +# Rule DF.6_3.3V: Min. COMP extend beyond gate (it also means source/drain overhang). is 0.24µm +logger.info("Executing rule DF.6_3.3V") +df6_l1 = comp.not(otp_mk).not_inside(ymtp_mk).enclosing(poly2.not_inside(ymtp_mk), 0.24.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df6_l1.output("DF.6_3.3V", "DF.6_3.3V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.24µm") +df6_l1.forget + +# Rule DF.6_5V: Min. COMP extend beyond gate (it also means source/drain overhang). is 0.4µm +logger.info("Executing rule DF.6_5V") +df6_l1 = comp.not(otp_mk).not_inside(mvpsd).not_inside(mvsd).not_inside(ymtp_mk).outside(sramcore).enclosing(poly2.not_inside(ymtp_mk), 0.4.um, euclidian).polygons(0.001).overlapping(dualgate) +df6_l1.output("DF.6_5V", "DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.4µm") +df6_l1.forget + +# Rule DF.7_3.3V: Min. (LVPWELL Spacer to PCOMP) inside DNWELL. is 0.43µm +logger.info("Executing rule DF.7_3.3V") +df7_l1 = pcomp.inside(dnwell).separation(pwell_dnwell, 0.43.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df7_l1.output("DF.7_3.3V", "DF.7_3.3V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.43µm") +df7_l1.forget + +# Rule DF.7_5V: Min. (LVPWELL Spacer to PCOMP) inside DNWELL. is 0.6µm +logger.info("Executing rule DF.7_5V") +df7_l1 = pcomp.inside(dnwell).outside(sramcore).separation(pwell_dnwell, 0.6.um, euclidian).polygons(0.001).overlapping(dualgate) +df7_l1.output("DF.7_5V", "DF.7_5V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.6µm") +df7_l1.forget + +# Rule DF.8_3.3V: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.43µm +logger.info("Executing rule DF.8_3.3V") +df8_l1 = pwell_dnwell.enclosing(ncomp.inside(dnwell), 0.43.um, euclidian).polygons(0.001) +df8_l2 = ncomp.inside(dnwell).not_outside(pwell_dnwell).not(pwell_dnwell) +df8_l = df8_l1.or(df8_l2).not_interacting(v5_xtor).not_interacting(dualgate) +df8_l.output("DF.8_3.3V", "DF.8_3.3V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.43µm") +df8_l1.forget +df8_l2.forget +df8_l.forget + +# Rule DF.8_5V: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.6µm +logger.info("Executing rule DF.8_5V") +df8_l1 = pwell_dnwell.outside(sramcore).enclosing(ncomp.inside(dnwell), 0.6.um, euclidian).polygons(0.001) +df8_l2 = ncomp.inside(dnwell).not_outside(pwell_dnwell.outside(sramcore)).not(pwell_dnwell.outside(sramcore)) +df8_l = df8_l1.or(df8_l2).overlapping(dualgate) +df8_l.output("DF.8_5V", "DF.8_5V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.6µm") +df8_l1.forget +df8_l2.forget +df8_l.forget + +pwell_dnwell.forget +# Rule DF.9_3.3V: Min. COMP area (um2). is 0.2025µm² +logger.info("Executing rule DF.9_3.3V") +df9_l1 = comp.not(otp_mk).with_area(nil, 0.2025.um).not_interacting(v5_xtor).not_interacting(dualgate) +df9_l1.output("DF.9_3.3V", "DF.9_3.3V : Min. COMP area (um2). : 0.2025µm²") +df9_l1.forget +# Rule DF.9_5V: Min. COMP area (um2). is 0.2025µm² +logger.info("Executing rule DF.9_5V") +df9_l1 = comp.not(otp_mk).with_area(nil, 0.2025.um).overlapping(dualgate) +df9_l1.output("DF.9_5V", "DF.9_5V : Min. COMP area (um2). : 0.2025µm²") +df9_l1.forget +# Rule DF.10_3.3V: Min. field area (um2). is 0.26µm² +logger.info("Executing rule DF.10_3.3V") +df10_l1 = comp.holes.not(comp).with_area(nil, 0.26.um).not_interacting(v5_xtor).not_interacting(dualgate) +df10_l1.output("DF.10_3.3V", "DF.10_3.3V : Min. field area (um2). : 0.26µm²") +df10_l1.forget +# Rule DF.10_5V: Min. field area (um2). is 0.26µm² +logger.info("Executing rule DF.10_5V") +df10_l1 = comp.holes.not(comp).with_area(nil, 0.26.um).overlapping(dualgate) +df10_l1.output("DF.10_5V", "DF.10_5V : Min. field area (um2). : 0.26µm²") +df10_l1.forget +comp_butt = comp.interacting(ncomp.interacting(pcomp).outside(pcomp)) +# Rule DF.11_3.3V: Min. Length of butting COMP edge. is 0.3µm +logger.info("Executing rule DF.11_3.3V") +df11_l1 = comp_butt.width(0.3.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df11_l1.output("DF.11_3.3V", "DF.11_3.3V : Min. Length of butting COMP edge. : 0.3µm") +df11_l1.forget + +# Rule DF.11_5V: Min. Length of butting COMP edge. is 0.3µm +logger.info("Executing rule DF.11_5V") +df11_l1 = comp_butt.width(0.3.um, euclidian).polygons(0.001).overlapping(dualgate) +df11_l1.output("DF.11_5V", "DF.11_5V : Min. Length of butting COMP edge. : 0.3µm") +df11_l1.forget + +comp_butt.forget +# Rule DF.12_3.3V: COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking). +logger.info("Executing rule DF.12_3.3V") +df12_l1 = comp.not_interacting(schottky_diode).not(nplus.or(pplus)).not_interacting(v5_xtor).not_interacting(dualgate) +df12_l1.output("DF.12_3.3V", "DF.12_3.3V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).") +df12_l1.forget + +# Rule DF.12_5V: COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking). +logger.info("Executing rule DF.12_5V") +df12_l1 = comp.not_interacting(schottky_diode).not(nplus.or(pplus)).overlapping(dualgate) +df12_l1.output("DF.12_5V", "DF.12_5V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).") +df12_l1.forget + +df13_ncomp = ncomp.inside(nwell.covering(ncomp).covering(pcomp)) +df13_pcomp = pcomp.inside(nwell.covering(ncomp).covering(pcomp)) +# Rule DF.13_3.3V: Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell). +logger.info("Executing rule DF.13_3.3V") +df13_l1 = df13_ncomp.not_interacting(df13_pcomp.sized(20.um)).not_interacting(v5_xtor).not_interacting(dualgate) +df13_l1.output("DF.13_3.3V", "DF.13_3.3V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).") +df13_l1.forget + +# Rule DF.13_5V: Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell). +logger.info("Executing rule DF.13_5V") +df13_l1 = df13_ncomp.not_interacting(df13_pcomp.sized(15.um)).overlapping(dualgate) +df13_l1.output("DF.13_5V", "DF.13_5V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).") +df13_l1.forget + +df13_ncomp.forget +df13_pcomp.forget +# Rule DF.14_3.3V: Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell). +logger.info("Executing rule DF.14_3.3V") +df14_l1 = pcomp.outside(nwell).not_interacting(ncomp.outside(nwell).sized(20.um)).not_interacting(v5_xtor).not_interacting(dualgate) +df14_l1.output("DF.14_3.3V", "DF.14_3.3V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).") +df14_l1.forget + +# Rule DF.14_5V: Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell). +logger.info("Executing rule DF.14_5V") +df14_l1 = pcomp.outside(nwell).not_interacting(ncomp.outside(nwell).sized(15.um)).overlapping(dualgate) +df14_l1.output("DF.14_5V", "DF.14_5V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).") +df14_l1.forget + +# rule DF.15a_3.3V is not a DRC check + +# rule DF.15a_5V is not a DRC check + +# rule DF.15b_3.3V is not a DRC check + +# rule DF.15b_5V is not a DRC check + +ncomp_df16 = ncomp.outside(nwell).outside(dnwell) +# Rule DF.16_3.3V: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.43µm +logger.info("Executing rule DF.16_3.3V") +df16_l1 = ncomp_df16.not_inside(ymtp_mk).outside(sramcore).separation(nwell.outside(dnwell).not_inside(ymtp_mk), 0.43.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df16_l1.output("DF.16_3.3V", "DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.43µm") +df16_l1.forget + +# Rule DF.16_5V: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.6µm +logger.info("Executing rule DF.16_5V") +df16_l1 = ncomp_df16.not_inside(ymtp_mk).outside(sramcore).separation(nwell.outside(dnwell).not_inside(ymtp_mk), 0.6.um, euclidian).polygons(0.001).overlapping(dualgate) +df16_l1.output("DF.16_5V", "DF.16_5V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.6µm") +df16_l1.forget + +pcomp_df17 = pcomp.outside(nwell).outside(dnwell) +# Rule DF.17_3.3V: Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). is 0.12µm +logger.info("Executing rule DF.17_3.3V") +df17_l1 = pcomp_df17.separation(nwell.outside(dnwell), 0.12.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df17_l1.output("DF.17_3.3V", "DF.17_3.3V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.12µm") +df17_l1.forget + +# Rule DF.17_5V: Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). is 0.16µm +logger.info("Executing rule DF.17_5V") +df17_l1 = pcomp_df17.separation(nwell.outside(dnwell), 0.16.um, euclidian).polygons(0.001).overlapping(dualgate) +df17_l1.output("DF.17_5V", "DF.17_5V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.16µm") +df17_l1.forget + +# Rule DF.18_3.3V: Min. DNWELL space to (PCOMP outside Nwell and DNWELL). is 2.5µm +logger.info("Executing rule DF.18_3.3V") +df18_l1 = pcomp_df17.separation(dnwell, 2.5.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df18_l1.output("DF.18_3.3V", "DF.18_3.3V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm") +df18_l1.forget + +# Rule DF.18_5V: Min. DNWELL space to (PCOMP outside Nwell and DNWELL). is 2.5µm +logger.info("Executing rule DF.18_5V") +df18_l1 = pcomp_df17.separation(dnwell, 2.5.um, euclidian).polygons(0.001).overlapping(dualgate) +df18_l1.output("DF.18_5V", "DF.18_5V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm") +df18_l1.forget + +pcomp_df17.forget +# Rule DF.19_3.3V: Min. DNWELL space to (NCOMP outside Nwell and DNWELL). is 3.2µm +logger.info("Executing rule DF.19_3.3V") +df19_l1 = ncomp_df16.separation(dnwell, 3.2.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +df19_l1.output("DF.19_3.3V", "DF.19_3.3V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.2µm") +df19_l1.forget + +# Rule DF.19_5V: Min. DNWELL space to (NCOMP outside Nwell and DNWELL). is 3.28µm +logger.info("Executing rule DF.19_5V") +df19_l1 = ncomp_df16.separation(dnwell, 3.28.um, euclidian).polygons(0.001).overlapping(dualgate) +df19_l1.output("DF.19_5V", "DF.19_5V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.28µm") +df19_l1.forget + +ncomp_df16.forget + +end #FEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/contact.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/contact.drc new file mode 100644 index 000000000..c11b86ce5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/contact.drc @@ -0,0 +1,361 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (CONTACT) ----------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +contact = polygons(33 , 0 ) +metal1 = polygons(34 , 0 ) +mvsd = polygons(210, 0 ) +mvpsd = polygons(11 , 39) +otp_mk = polygons(173, 5 ) +sramcore = polygons(108, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#--------------------CONTACT--------------------- +#================================================ + + +if FEOL +logger.info("FEOL section") + +# Rule CO.1: Min/max contact size. is 0.22µm +logger.info("Executing rule CO.1") +co1_l1 = contact.edges.without_length(0.22.um).extended(0, 0, 0.001, 0.001) +co1_l1.output("CO.1", "CO.1 : Min/max contact size. : 0.22µm") +co1_l1.forget + +# Rule CO.2a: min. contact spacing is 0.25µm +logger.info("Executing rule CO.2a") +co2a_l1 = contact.space(0.25.um, euclidian).polygons(0.001) +co2a_l1.output("CO.2a", "CO.2a : min. contact spacing : 0.25µm") +co2a_l1.forget + +merged_co1 = contact.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.63.um , nil).extents.inside(metal1) +contact_mask = merged_co1.size(1).not(contact).with_holes(16, nil) +selected_co1 = contact.interacting(contact_mask) +# Rule CO.2b: Space in 4x4 or larger contact array. is 0.28µm +logger.info("Executing rule CO.2b") +co2b_l1 = selected_co1.space(0.28.um, euclidian).polygons(0.001) +co2b_l1.output("CO.2b", "CO.2b : Space in 4x4 or larger contact array. : 0.28µm") +co2b_l1.forget + +merged_co1.forget +contact_mask.forget +selected_co1.forget +# Rule CO.3: Poly2 overlap of contact. is 0.07µm +logger.info("Executing rule CO.3") +co3_l1 = poly2.enclosing(contact.outside(sramcore), 0.07.um, euclidian).polygons(0.001) +co3_l2 = contact.outside(sramcore).not_outside(poly2).not(poly2) +co3_l = co3_l1.or(co3_l2) +co3_l.output("CO.3", "CO.3 : Poly2 overlap of contact. : 0.07µm") +co3_l1.forget +co3_l2.forget +co3_l.forget + +# Rule CO.4: COMP overlap of contact. is 0.07µm +logger.info("Executing rule CO.4") +co4_l1 = comp.not(mvsd).not(mvpsd).enclosing(contact.outside(sramcore), 0.07.um, euclidian).polygons(0.001) +co4_l2 = contact.outside(sramcore).not_outside(comp.not(mvsd).not(mvpsd)).not(comp.not(mvsd).not(mvpsd)) +co4_l = co4_l1.or(co4_l2) +co4_l.output("CO.4", "CO.4 : COMP overlap of contact. : 0.07µm") +co4_l1.forget +co4_l2.forget +co4_l.forget + +co_5a_ncomp_butted = ncomp.not(pplus).interacting(pcomp.not(nplus)).not_overlapping(pcomp.not(nplus)) +# Rule CO.5a: Nplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). is 0.1µm +logger.info("Executing rule CO.5a") +co5a_l1 = co_5a_ncomp_butted.enclosing(contact, 0.1.um, euclidian).polygons(0.001) +co5a_l2 = contact.not_outside(co_5a_ncomp_butted).not(co_5a_ncomp_butted) +co5a_l = co5a_l1.or(co5a_l2) +co5a_l.output("CO.5a", "CO.5a : Nplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm") +co5a_l1.forget +co5a_l2.forget +co5a_l.forget + +co_5a_ncomp_butted.forget +co_5b_pcomp_butted = pcomp.not(nplus).interacting(ncomp.not(pplus)).not_overlapping(ncomp.not(pplus)) +# Rule CO.5b: Pplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). is 0.1µm +logger.info("Executing rule CO.5b") +co5b_l1 = co_5b_pcomp_butted.enclosing(contact, 0.1.um, euclidian).polygons(0.001) +co5b_l2 = contact.not_outside(co_5b_pcomp_butted).not(co_5b_pcomp_butted) +co5b_l = co5b_l1.or(co5b_l2) +co5b_l.output("CO.5b", "CO.5b : Pplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm") +co5b_l1.forget +co5b_l2.forget +co5b_l.forget + +co_5b_pcomp_butted.forget +# Rule CO.6: Metal1 overlap of contact. +logger.info("Executing rule CO.6") +co6_l1 = metal1.enclosing(contact, 0.005.um, euclidian).polygons(0.001).or(contact.not(metal1)) +co6_l1.output("CO.6", "CO.6 : Metal1 overlap of contact.") +co6_l1.forget + +cop6a_cond = metal1.drc( width <= 0.34.um).with_length(0.24.um,nil,both) +cop6a_eol = metal1.edges.with_length(nil, 0.34.um).interacting(cop6a_cond.first_edges).interacting(cop6a_cond.second_edges).not(cop6a_cond.first_edges).not(cop6a_cond.second_edges) +# Rule CO.6a: (i) Metal1 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule CO.6a") +co6a_l1 = cop6a_eol.enclosing(contact.edges,0.06.um, projection).polygons(0.001) +co6a_l1.output("CO.6a", "CO.6a : (i) Metal1 (< 0.34um) end-of-line overlap. : 0.06µm") +co6a_l1.forget + +cop6a_cond.forget +cop6a_eol.forget +co_6b_1 = contact.edges.interacting(contact.drc(enclosed(metal1, projection) < 0.04.um).edges.centers(0, 0.5)) +co_6b_2 = contact.edges.interacting(contact.drc(0.04.um <= enclosed(metal1, projection) < 0.06.um).centers(0, 0.5)) +co_6b_3 = co_6b_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule CO.6b: (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap is 0.06µm +logger.info("Executing rule CO.6b") +co6b_l1 = co_6b_2.not_in(co_6b_1).interacting(co_6b_1).or(co_6b_1.interacting(co_6b_3)).not(sramcore).enclosed(metal1.outside(sramcore).edges, 0.06.um).polygons(0.001) +co6b_l1.output("CO.6b", "CO.6b : (ii) If Metal1 overlaps contact by < 0.04um on one side, adjacent metal1 edges overlap : 0.06µm") +co6b_l1.forget + +co_6b_1.forget +co_6b_2.forget +co_6b_3.forget +# rule CO.6c is not a DRC check + +# Rule CO.7: Space from COMP contact to Poly2 on COMP. is 0.15µm +logger.info("Executing rule CO.7") +co7_l1 = contact.not_outside(comp).not(otp_mk).separation(tgate.not(otp_mk), 0.15.um, euclidian).polygons(0.001) +co7_l1.output("CO.7", "CO.7 : Space from COMP contact to Poly2 on COMP. : 0.15µm") +co7_l1.forget + +# Rule CO.8: Space from Poly2 contact to COMP. is 0.17µm +logger.info("Executing rule CO.8") +co8_l1 = contact.not_outside(poly2).separation(comp, 0.17.um, euclidian).polygons(0.001) +co8_l1.output("CO.8", "CO.8 : Space from Poly2 contact to COMP. : 0.17µm") +co8_l1.forget + +# Rule CO.9: Contact on NCOMP to PCOMP butting edge is forbidden (contact must not straddle butting edge). +logger.info("Executing rule CO.9") +co9_l1 = contact.interacting(ncomp.edges.and(pcomp.edges)) +co9_l1.output("CO.9", "CO.9 : Contact on NCOMP to PCOMP butting edge is forbidden (contact must not straddle butting edge).") +co9_l1.forget + +# Rule CO.10: Contact on Poly2 gate over COMP is forbidden. +logger.info("Executing rule CO.10") +co10_l1 = contact.not_outside(tgate) +co10_l1.output("CO.10", "CO.10 : Contact on Poly2 gate over COMP is forbidden.") +co10_l1.forget + +# Rule CO.11: Contact on field oxide is forbidden. +logger.info("Executing rule CO.11") +co11_l1 = contact.not(comp.or(poly2)) +co11_l1.output("CO.11", "CO.11 : Contact on field oxide is forbidden.") +co11_l1.forget + +end #FEOL + +if BEOL +logger.info("BEOL section") + + +end #FEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/dnwell.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/dnwell.drc new file mode 100644 index 000000000..c05adeb7c --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/dnwell.drc @@ -0,0 +1,361 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (DNWELL) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +sab = polygons(49 , 0 ) +nat = polygons(5 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) +#================================================ +#------------- LAYERS CONNECTIONS --------------- +#================================================ + +if CONNECTIVITY_RULES + + logger.info("Construct connectivity for the design.") + + connect(dnwell, ncomp) + connect(ncomp, contact) + connect(pcomp, contact) + connect(lvpwell, ncomp) + connect(nwell, ncomp) + connect(natcompsd, contact) + connect(mvsd, ncomp) + connect(mvpsd, pcomp) + connect(contact, metal1) + connect(metal1, via1) + connect(via1, metal2) + connect(metal2, via2) + connect(via2, metal3) + connect(metal3, via3) + connect(via3, metal4) + connect(metal4, via4) + connect(via4, metal5) + connect(metal5, via5) + connect(via5, metaltop) + +end #CONNECTIVITY_RULES + +#================================================ +#------------ PRE-DEFINED FUNCTIONS ------------- +#================================================ + +def conn_space(layer,conn_val,not_conn_val, mode) + if conn_val > not_conn_val + raise "ERROR : Wrong connectivity implementation" + end + connected_output = layer.space(conn_val.um, mode).polygons(0.001) + unconnected_errors_unfiltered = layer.space(not_conn_val.um, mode) + singularity_errors = layer.space(0.001.um) + # Filter out the errors arising from the same net + unconnected_errors = DRC::DRCLayer::new(self, RBA::EdgePairs::new) + unconnected_errors_unfiltered.data.each do |ep| + net1 = l2n_data.probe_net(layer.data, ep.first.p1) + net2 = l2n_data.probe_net(layer.data, ep.second.p1) + if !net1 || !net2 + puts "Should not happen ..." + elsif net1.circuit != net2.circuit || net1.cluster_id != net2.cluster_id + # unconnected + unconnected_errors.data.insert(ep) + end + end + unconnected_output = unconnected_errors.polygons.or(singularity_errors.polygons(0.001)) + return connected_output, unconnected_output +end + +def conn_separation(layer1, layer2, conn_val,not_conn_val, mode) + if conn_val > not_conn_val + raise "ERROR : Wrong connectivity implementation" + end + connected_output = layer1.separation(layer2, conn_val.um, mode).polygons(0.001) + unconnected_errors_unfiltered = layer1.separation(layer2, not_conn_val.um, mode) + # Filter out the errors arising from the same net + unconnected_errors = DRC::DRCLayer::new(self, RBA::EdgePairs::new) + unconnected_errors_unfiltered.data.each do |ep| + net1 = l2n_data.probe_net(layer1.data, ep.first.p1) + net2 = l2n_data.probe_net(layer2.data, ep.second.p1) + if !net1 || !net2 + puts "Should not happen ..." + elsif net1.circuit != net2.circuit || net1.cluster_id != net2.cluster_id + # unconnected + unconnected_errors.data.insert(ep) + end + end + unconnected_output = unconnected_errors.polygons(0.001) + return connected_output, unconnected_output +end + +# === IMPLICIT EXTRACTION === +if CONNECTIVITY_RULES + logger.info("Connectivity rules enabled, Netlist object will be generated.") + netlist +end #CONNECTIVITY_RULES + +# === LAYOUT EXTENT === +CHIP = extent.sized(0.0) + +logger.info("Total area of the design is #{CHIP.area()} um^2.") + + + +#================================================ +#---------------------DNWELL--------------------- +#================================================ + + +if FEOL +logger.info("FEOL section") + +# Rule DN.1: Min. DNWELL Width is 1.7µm +logger.info("Executing rule DN.1") +dn1_l1 = dnwell.width(1.7.um, euclidian).polygons(0.001) +dn1_l1.output("DN.1", "DN.1 : Min. DNWELL Width : 1.7µm") +dn1_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_dnwell, unconnected_dnwell = conn_space(dnwell, 2.5, 5.42, euclidian) + +# Rule DN.2a: Min. DNWELL Space (Equi-potential), Merge if the space is less than is 2.5µm +logger.info("Executing rule DN.2a") +dn2a_l1 = connected_dnwell +dn2a_l1.output("DN.2a", "DN.2a : Min. DNWELL Space (Equi-potential), Merge if the space is less than : 2.5µm") +dn2a_l1.forget + +# Rule DN.2b: Min. DNWELL Space (Different potential) is 5.42µm +logger.info("Executing rule DN.2b") +dn2b_l1 = unconnected_dnwell +dn2b_l1.output("DN.2b", "DN.2b : Min. DNWELL Space (Different potential) : 5.42µm") +dn2b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule DN.2b_: Min. DNWELL Space (Different potential) is 5.42µm +logger.info("Executing rule DN.2b_") +dn2b_l1 = dnwell.isolated(5.42.um, euclidian).polygons(0.001) +dn2b_l1.output("DN.2b_", "DN.2b_ : Min. DNWELL Space (Different potential) : 5.42µm") +dn2b_l1.forget + +end #CONNECTIVITY_RULES + +dn3_1 = dnwell.not_inside(pcomp.holes.not(pcomp).interacting(dnwell, 1..1).extents) +dn3_2 = dnwell.inside((pcomp.holes.not(pcomp).covering(nat.or(ncomp).or(nwell).not_interacting(dnwell)))) +# Rule DN.3: Each DNWELL shall be directly surrounded by PCOMP guard ring tied to the P-substrate potential. +logger.info("Executing rule DN.3") +dn3_l1 = dn3_1.or(dn3_2) +dn3_l1.output("DN.3", "DN.3 : Each DNWELL shall be directly surrounded by PCOMP guard ring tied to the P-substrate potential.") +dn3_l1.forget + +dn3_1.forget +dn3_2.forget + +end #FEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/drc_bjt.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/drc_bjt.drc new file mode 100644 index 000000000..f298cd76e --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/drc_bjt.drc @@ -0,0 +1,236 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (DRC_BJT) ----------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +drc_bjt = polygons(127, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#--------------------DRC_BJT--------------------- +#================================================ + +# Rule BJT.1: Min. DRC_BJT overlap of DNWELL for NPN BJT. +logger.info("Executing rule BJT.1") +bjt1_l1 = dnwell.interacting(drc_bjt).not(dnwell.inside(drc_bjt)) +bjt1_l1.output("BJT.1", "BJT.1 : Min. DRC_BJT overlap of DNWELL for NPN BJT.") +bjt1_l1.forget + +# Rule BJT.2: Min. DRC_BJT overlap of PCOM in Psub. +logger.info("Executing rule BJT.2") +bjt2_l1 = pcomp.outside(nwell).outside(dnwell).interacting(drc_bjt).not(pcomp.outside(nwell).outside(dnwell).inside(drc_bjt)) +bjt2_l1.output("BJT.2", "BJT.2 : Min. DRC_BJT overlap of PCOM in Psub.") +bjt2_l1.forget + +# Rule BJT.3: Minimum space of DRC_BJT layer to unrelated COMP. is 0.1µm +logger.info("Executing rule BJT.3") +bjt3_l1 = comp.outside(drc_bjt).separation(drc_bjt, 0.1.um, euclidian).polygons(0.001) +bjt3_l1.output("BJT.3", "BJT.3 : Minimum space of DRC_BJT layer to unrelated COMP. : 0.1µm") +bjt3_l1.forget + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/dualgate.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/dualgate.drc new file mode 100644 index 000000000..bbbc14ab7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/dualgate.drc @@ -0,0 +1,288 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#---------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (DUALGATE) ----------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#--------------------DUALGATE-------------------- +#================================================ + + +if FEOL +logger.info("FEOL section") + +# Rule DV.1: Min. Dualgate enclose DNWELL. is 0.5µm +logger.info("Executing rule DV.1") +dv1_l1 = dualgate.enclosing(dnwell, 0.5.um, euclidian).polygons(0.001) +dv1_l2 = dnwell.not_outside(dualgate).not(dualgate) +dv1_l = dv1_l1.or(dv1_l2) +dv1_l.output("DV.1", "DV.1 : Min. Dualgate enclose DNWELL. : 0.5µm") +dv1_l1.forget +dv1_l2.forget +dv1_l.forget + +# Rule DV.2: Min. Dualgate Space. Merge if Space is less than this design rule. is 0.44µm +logger.info("Executing rule DV.2") +dv2_l1 = dualgate.space(0.44.um, euclidian).polygons(0.001) +dv2_l1.output("DV.2", "DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm") +dv2_l1.forget + +# Rule DV.3: Min. Dualgate to COMP space [unrelated]. is 0.24µm +logger.info("Executing rule DV.3") +dv3_l1 = dualgate.separation(comp.outside(dualgate), 0.24.um, euclidian).polygons(0.001) +dv3_l1.output("DV.3", "DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm") +dv3_l1.forget + +# rule DV.4 is not a DRC check + +# Rule DV.5: Min. Dualgate width. is 0.7µm +logger.info("Executing rule DV.5") +dv5_l1 = dualgate.width(0.7.um, euclidian).polygons(0.001) +dv5_l1.output("DV.5", "DV.5 : Min. Dualgate width. : 0.7µm") +dv5_l1.forget + +comp_dv = comp.not(pcomp.outside(nwell)) +# Rule DV.6: Min. Dualgate enclose COMP (except substrate tap). is 0.24µm +logger.info("Executing rule DV.6") +dv6_l1 = dualgate.enclosing(comp_dv, 0.24.um, euclidian).polygons(0.001) +dv6_l2 = comp_dv.not_outside(dualgate).not(dualgate) +dv6_l = dv6_l1.or(dv6_l2) +dv6_l.output("DV.6", "DV.6 : Min. Dualgate enclose COMP (except substrate tap). : 0.24µm") +dv6_l1.forget +dv6_l2.forget +dv6_l.forget + +# Rule DV.7: COMP (except substrate tap) can not be partially overlapped by Dualgate. +logger.info("Executing rule DV.7") +dv7_l1 = dualgate.not_outside(comp_dv).not(dualgate.covering(comp_dv)) +dv7_l1.output("DV.7", "DV.7 : COMP (except substrate tap) can not be partially overlapped by Dualgate.") +dv7_l1.forget + +comp_dv.forget +# Rule DV.8: Min Dualgate enclose Poly2. is 0.4µm +logger.info("Executing rule DV.8") +dv8_l1 = dualgate.enclosing(poly2, 0.4.um, euclidian).polygons(0.001) +dv8_l2 = poly2.not_outside(dualgate).not(dualgate) +dv8_l = dv8_l1.or(dv8_l2) +dv8_l.output("DV.8", "DV.8 : Min Dualgate enclose Poly2. : 0.4µm") +dv8_l1.forget +dv8_l2.forget +dv8_l.forget + +# Rule DV.9: 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL. +logger.info("Executing rule DV.9") +dv9_l1 = nwell.covering(pgate.and(dualgate)).covering(pgate.not_inside(v5_xtor).not_inside(dualgate)) +dv9_l1.output("DV.9", "DV.9 : 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.") +dv9_l1.forget + + +end #FEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/dummy_exclude_layers.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/dummy_exclude_layers.drc new file mode 100644 index 000000000..dc0e6f131 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/dummy_exclude_layers.drc @@ -0,0 +1,239 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#---------------------------------------------------- GF 0.18um MCU DRC RULE DECK (DUMMY EXCLUDE LAYERS) ----------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +ndmy = polygons(111, 5 ) +pmndmy = polygons(152, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#--------------DUMMY EXCLUDE LAYERS-------------- +#================================================ + +# rule DE.1 is not a DRC check + +# Rule DE.2: Minimum NDMY or PMNDMY size (x or y dimension in um). is 0.8µm +logger.info("Executing rule DE.2") +de2_l1 = ndmy.or(pmndmy).width(0.8.um, euclidian).polygons(0.001) +de2_l1.output("DE.2", "DE.2 : Minimum NDMY or PMNDMY size (x or y dimension in um). : 0.8µm") +de2_l1.forget + +de3_ndmy_area = ndmy.with_area(15000.um, nil) +# Rule DE.3: If size greater than 15000 um2 then two sides should not be greater than (um). +logger.info("Executing rule DE.3") +de3_l1 = de3_ndmy_area.edges.with_length(80.um, nil).not_interacting(de3_ndmy_area.edges.with_length(nil, 80.um)) +de3_l1.output("DE.3", "DE.3 : If size greater than 15000 um2 then two sides should not be greater than (um).") +de3_l1.forget + +de3_ndmy_area.forget +# Rule DE.4: Minimum NDMY to NDMY space (Merge if space is less). is 20µm +logger.info("Executing rule DE.4") +de4_l1 = ndmy.space(20.um, euclidian).polygons(0.001) +de4_l1.output("DE.4", "DE.4 : Minimum NDMY to NDMY space (Merge if space is less). : 20µm") +de4_l1.forget + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/efuse.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/efuse.drc new file mode 100644 index 000000000..8acbda473 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/efuse.drc @@ -0,0 +1,398 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (EFUSE) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +sab = polygons(49 , 0 ) +esd = polygons(24 , 0 ) +contact = polygons(33 , 0 ) +metal1 = polygons(34 , 0 ) +metal2 = polygons(36 , 0 ) +resistor = polygons(62 , 0 ) +lvs_source = polygons(100, 8 ) +plfuse = polygons(125, 5 ) +efuse_mk = polygons(80 , 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#---------------------EFUSE---------------------- +#================================================ + +# Rule EF.01: Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus. +logger.info("Executing rule EF.01") +ef01_l1 = poly2.or(plfuse).interacting(efuse_mk).not_inside(efuse_mk.and(pplus)) +ef01_l1.output("EF.01", "EF.01 : Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus.") +ef01_l1.forget + +# Rule EF.02: Min. Max. PLFUSE width. is 0.18µm +logger.info("Executing rule EF.02") +ef02_l1 = plfuse.drc(width != 0.18.um).extended(0, 0, 0.001, 0.001) +ef02_l1.output("EF.02", "EF.02 : Min. Max. PLFUSE width. : 0.18µm") +ef02_l1.forget + +# Rule EF.03: Min. Max. PLFUSE length. is 1.26µm +logger.info("Executing rule EF.03") +ef03_l1 = plfuse.edges.interacting(poly2.edges.and(plfuse.edges).centers(0, 0.95)).without_length(1.26.um).extended(0, 0, 0.001, 0.001) +ef03_l1.output("EF.03", "EF.03 : Min. Max. PLFUSE length. : 1.26µm") +ef03_l1.forget + +# Rule EF.04a: Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode. +logger.info("Executing rule EF.04a") +ef04a_l1 = plfuse.not_in(plfuse.interacting(poly2.not(plfuse), 2, 2)).inside(efuse_mk).or(plfuse.not(poly2).inside(efuse_mk)) +ef04a_l1.output("EF.04a", "EF.04a : Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode.") +ef04a_l1.forget + +# Rule EF.04b: PLFUSE must be rectangular. is -µm +logger.info("Executing rule EF.04b") +ef04b_l1 = plfuse.non_rectangles +ef04b_l1.output("EF.04b", "EF.04b : PLFUSE must be rectangular. : -µm") +ef04b_l1.forget + +cathode = poly2.inside(efuse_mk).not(lvs_source.or(plfuse)) +# Rule EF.04c: Cathode Poly2 must be rectangular. is -µm +logger.info("Executing rule EF.04c") +ef04c_l1 = cathode.non_rectangles +ef04c_l1.output("EF.04c", "EF.04c : Cathode Poly2 must be rectangular. : -µm") +ef04c_l1.forget + +anode = poly2.and(lvs_source).inside(efuse_mk) +# Rule EF.04d: Anode Poly2 must be rectangular. is -µm +logger.info("Executing rule EF.04d") +ef04d_l1 = anode.non_rectangles +ef04d_l1.output("EF.04d", "EF.04d : Anode Poly2 must be rectangular. : -µm") +ef04d_l1.forget + +# Rule EF.05: Min./Max. LVS_Source overlap Poly2 (at Anode). +logger.info("Executing rule EF.05") +ef05_l1 = poly2.not(plfuse).interacting(lvs_source).not(lvs_source).inside(efuse_mk).or(lvs_source.not(poly2).inside(efuse_mk)) +ef05_l1.output("EF.05", "EF.05 : Min./Max. LVS_Source overlap Poly2 (at Anode).") +ef05_l1.forget + +cathode_width = cathode.edges.not_interacting(cathode.edges.interacting(plfuse)).or(cathode.edges.interacting(plfuse)) +# Rule EF.06: Min./Max. Cathode Poly2 width. is 2.26µm +logger.info("Executing rule EF.06") +ef06_l1 = cathode_width.without_length(2.26.um).extended(0, 0, 0.001, 0.001) +ef06_l1.output("EF.06", "EF.06 : Min./Max. Cathode Poly2 width. : 2.26µm") +ef06_l1.forget + +# Rule EF.07: Min./Max. Cathode Poly2 length. is 1.84µm +logger.info("Executing rule EF.07") +ef07_l1 = cathode.edges.not(cathode_width).without_length(1.84.um).extended(0, 0, 0.001, 0.001) +ef07_l1.output("EF.07", "EF.07 : Min./Max. Cathode Poly2 length. : 1.84µm") +ef07_l1.forget + +anode_width = anode.edges.not_interacting(anode.edges.interacting(plfuse)).or(anode.edges.interacting(plfuse)) +# Rule EF.08: Min./Max. Anode Poly2 width. is 1.06µm +logger.info("Executing rule EF.08") +ef08_l1 = anode_width.without_length(1.06.um).extended(0, 0, 0.001, 0.001) +ef08_l1.output("EF.08", "EF.08 : Min./Max. Anode Poly2 width. : 1.06µm") +ef08_l1.forget + +# Rule EF.09: Min./Max. Anode Poly2 length. is 2.43µm +logger.info("Executing rule EF.09") +ef09_l1 = anode.edges.not(anode_width).without_length(2.43.um).extended(0, 0, 0.001, 0.001) +ef09_l1.output("EF.09", "EF.09 : Min./Max. Anode Poly2 length. : 2.43µm") +ef09_l1.forget + +# Rule EF.10: Min. Cathode Poly2 to Poly2 space. is 0.26µm +logger.info("Executing rule EF.10") +ef10_l1 = cathode.space(0.26.um, euclidian).polygons(0.001) +ef10_l1.output("EF.10", "EF.10 : Min. Cathode Poly2 to Poly2 space. : 0.26µm") +ef10_l1.forget + +# Rule EF.11: Min. Anode Poly2 to Poly2 space. is 0.26µm +logger.info("Executing rule EF.11") +ef11_l1 = anode.space(0.26.um, euclidian).polygons(0.001) +ef11_l1.output("EF.11", "EF.11 : Min. Anode Poly2 to Poly2 space. : 0.26µm") +ef11_l1.forget + +cont_ef = contact.and(plfuse.inside(efuse_mk)) +# Rule EF.12: Min. Space of Cathode Contact to PLFUSE end. +logger.info("Executing rule EF.12") +ef12_l1 = plfuse.inside(efuse_mk).separation(contact.inside(cathode), 0.155.um).polygons(0.001).or(cont_ef) +ef12_l1.output("EF.12", "EF.12 : Min. Space of Cathode Contact to PLFUSE end.") +ef12_l1.forget + +# Rule EF.13: Min. Space of Anode Contact to PLFUSE end. +logger.info("Executing rule EF.13") +ef13_l1 = plfuse.inside(efuse_mk).separation(contact.inside(anode), 0.14.um).polygons(0.001).or(cont_ef) +ef13_l1.output("EF.13", "EF.13 : Min. Space of Anode Contact to PLFUSE end.") +ef13_l1.forget + +cont_ef.forget +# Rule EF.14: Min. EFUSE_MK enclose LVS_Source. +logger.info("Executing rule EF.14") +ef14_l1 = lvs_source.not_outside(efuse_mk).not(efuse_mk) +ef14_l1.output("EF.14", "EF.14 : Min. EFUSE_MK enclose LVS_Source.") +ef14_l1.forget + +# Rule EF.15: NO Contact is allowed to touch PLFUSE. +logger.info("Executing rule EF.15") +ef15_l1 = plfuse.interacting(contact) +ef15_l1.output("EF.15", "EF.15 : NO Contact is allowed to touch PLFUSE.") +ef15_l1.forget + +# Rule EF.16a: Cathode must contain exact number of Contacts at each ends. is 4µm +logger.info("Executing rule EF.16a") +ef16a_l1 = cathode.not_covering(contact, 4, 4) +ef16a_l1.output("EF.16a", "EF.16a : Cathode must contain exact number of Contacts at each ends. : 4µm") +ef16a_l1.forget + +# Rule EF.16b: Anode must contain exact number of Contacts at each ends. is 4µm +logger.info("Executing rule EF.16b") +ef16b_l1 = anode.not_covering(contact, 4, 4) +ef16b_l1.output("EF.16b", "EF.16b : Anode must contain exact number of Contacts at each ends. : 4µm") +ef16b_l1.forget + +# Rule EF.17: Min. Space of EFUSE_MK to EFUSE_MK. is 0.26µm +logger.info("Executing rule EF.17") +ef17_l1 = efuse_mk.space(0.26.um, euclidian).polygons(0.001) +ef17_l1.output("EF.17", "EF.17 : Min. Space of EFUSE_MK to EFUSE_MK. : 0.26µm") +ef17_l1.forget + +# Rule EF.18: PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2. +logger.info("Executing rule EF.18") +ef18_l1 = plfuse.not_outside(comp.or(nplus).or(esd).or(sab).or(resistor).or(metal1).or(metal2)) +ef18_l1.output("EF.18", "EF.18 : PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2.") +ef18_l1.forget + +# Rule EF.19: Min. PLFUSE space to Metal1, Metal2. +logger.info("Executing rule EF.19") +ef19_l1 = plfuse.not_outside(metal1.or(metal2)) +ef19_l1.output("EF.19", "EF.19 : Min. PLFUSE space to Metal1, Metal2.") +ef19_l1.forget + +# Rule EF.20: Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. is 2.73µm +logger.info("Executing rule EF.20") +ef20_l1 = plfuse.separation(comp.or(nplus).or(esd).or(sab).or(resistor), 2.73.um, euclidian).polygons(0.001) +ef20_l1.output("EF.20", "EF.20 : Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. : 2.73µm") +ef20_l1.forget + +ef_21_fuse = poly2.interacting(plfuse).inside(efuse_mk.and(pplus)).extents.edges +ef_21_anode = anode.edges.not_interacting(anode.edges.interacting(plfuse)) +ef_21_cathode = cathode.edges.not_interacting(cathode.edges.interacting(plfuse)) +# Rule EF.21: Min./Max. eFUSE Poly2 length. is 5.53µm +logger.info("Executing rule EF.21") +ef21_l1 = ef_21_fuse.not_interacting(ef_21_anode.or(ef_21_cathode).centers(0, 0.95)).without_length(5.53.um).extended(0, 0, 0.001, 0.001) +ef21_l1.output("EF.21", "EF.21 : Min./Max. eFUSE Poly2 length. : 5.53µm") +ef21_l1.forget + +ef_21_fuse.forget +ef_21_anode.forget +ef_21_cathode.forget +# Rule EF.22a: Min./Max. Cathode Poly2 overlap with PLFUSE in width direction. is 1.04µm +logger.info("Executing rule EF.22a") +ef22a_l1 = cathode.edges.interacting(plfuse).not(plfuse.edges).without_length(1.04.um).extended(0, 0, 0.001, 0.001) +ef22a_l1.output("EF.22a", "EF.22a : Min./Max. Cathode Poly2 overlap with PLFUSE in width direction. : 1.04µm") +ef22a_l1.forget + +# Rule EF.22b: Min./Max. Anode Poly2 overlap with PLFUSE in width direction. is 0.44µm +logger.info("Executing rule EF.22b") +ef22b_l1 = anode.edges.interacting(plfuse).not(plfuse.edges).without_length(0.44.um).extended(0, 0, 0.001, 0.001) +ef22b_l1.output("EF.22b", "EF.22b : Min./Max. Anode Poly2 overlap with PLFUSE in width direction. : 0.44µm") +ef22b_l1.forget + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/esd.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/esd.drc new file mode 100644 index 000000000..270dbc287 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/esd.drc @@ -0,0 +1,306 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (ESD) ------------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +esd = polygons(24 , 0 ) +lvs_io = polygons(119, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#----------------------ESD----------------------- +#================================================ + + +if FEOL +logger.info("FEOL section") + +# Rule ESD.1: Minimum width of an ESD implant area. is 0.6µm +logger.info("Executing rule ESD.1") +esd1_l1 = esd.width(0.6.um, euclidian).polygons(0.001) +esd1_l1.output("ESD.1", "ESD.1 : Minimum width of an ESD implant area. : 0.6µm") +esd1_l1.forget + +# Rule ESD.2: Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). is 0.6µm +logger.info("Executing rule ESD.2") +esd2_l1 = esd.space(0.6.um, euclidian).polygons(0.001) +esd2_l1.output("ESD.2", "ESD.2 : Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). : 0.6µm") +esd2_l1.forget + +# Rule ESD.3a: Minimum space to NCOMP. is 0.6µm +logger.info("Executing rule ESD.3a") +esd3a_l1 = esd.separation(ncomp, 0.6.um, euclidian).polygons(0.001) +esd3a_l1.output("ESD.3a", "ESD.3a : Minimum space to NCOMP. : 0.6µm") +esd3a_l1.forget + +# Rule ESD.3b: Min/max space to a butted PCOMP. +logger.info("Executing rule ESD.3b") +esd3b_l1 = esd.not_outside(pcomp) +esd3b_l1.output("ESD.3b", "ESD.3b : Min/max space to a butted PCOMP.") +esd3b_l1.forget + +# Rule ESD.4a: Extension beyond NCOMP. is 0.24µm +logger.info("Executing rule ESD.4a") +esd4a_l1 = esd.edges.not_interacting(pcomp).enclosing(ncomp.edges, 0.24.um, euclidian).polygons(0.001) +esd4a_l1.output("ESD.4a", "ESD.4a : Extension beyond NCOMP. : 0.24µm") +esd4a_l1.forget + +# Rule ESD.4b: Minimum overlap of an ESD implant edge to a COMP. is 0.45µm +logger.info("Executing rule ESD.4b") +esd4b_l1 = esd.overlap(comp, 0.45.um, euclidian).polygons(0.001) +esd4b_l1.output("ESD.4b", "ESD.4b : Minimum overlap of an ESD implant edge to a COMP. : 0.45µm") +esd4b_l1.forget + +# Rule ESD.5a: Minimum ESD area (um2). is 0.49µm² +logger.info("Executing rule ESD.5a") +esd5a_l1 = esd.with_area(nil, 0.49.um) +esd5a_l1.output("ESD.5a", "ESD.5a : Minimum ESD area (um2). : 0.49µm²") +esd5a_l1.forget +# Rule ESD.5b: Minimum field area enclosed by ESD implant (um2). is 0.49µm² +logger.info("Executing rule ESD.5b") +esd5b_l1 = esd.holes.with_area(nil, 0.49.um) +esd5b_l1.output("ESD.5b", "ESD.5b : Minimum field area enclosed by ESD implant (um2). : 0.49µm²") +esd5b_l1.forget +# Rule ESD.6: Extension perpendicular to Poly2 gate. is 0.45µm +logger.info("Executing rule ESD.6") +esd6_l1 = esd.edges.enclosing(poly2.edges.interacting(tgate.edges), 0.45.um, projection).polygons(0.001) +esd6_l1.output("ESD.6", "ESD.6 : Extension perpendicular to Poly2 gate. : 0.45µm") +esd6_l1.forget + +# Rule ESD.7: No ESD implant inside PCOMP. +logger.info("Executing rule ESD.7") +esd7_l1 = esd.not_outside(pcomp) +esd7_l1.output("ESD.7", "ESD.7 : No ESD implant inside PCOMP.") +esd7_l1.forget + +# Rule ESD.8: Minimum space to Nplus/Pplus. is 0.3µm +logger.info("Executing rule ESD.8") +esd8_l1 = esd.separation(nplus.or(pplus), 0.3.um).polygons +esd8_l1.output("ESD.8", "ESD.8 : Minimum space to Nplus/Pplus. : 0.3µm") +esd8_l1.forget + +# Rule ESD.pl: Minimum gate length of 5V/6V gate NMOS. is 0.8µm +logger.info("Executing rule ESD.pl") +esdpl_l1 = poly2.interacting(esd).edges.and(tgate.edges).width(0.8.um, euclidian).polygons(0.001).overlapping(dualgate) +esdpl_l1.output("ESD.pl", "ESD.pl : Minimum gate length of 5V/6V gate NMOS. : 0.8µm") +esdpl_l1.forget + +# Rule ESD.9: ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices). +logger.info("Executing rule ESD.9") +esd9_l1 = esd.not_inside(dualgate) +esd9_l1.output("ESD.9", "ESD.9 : ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices).") +esd9_l1.forget + +# Rule ESD.10: LVS_IO shall be drawn covering I/O MOS active area by minimum overlap. +logger.info("Executing rule ESD.10") +esd10_l1 = comp.and(esd).not_outside(lvs_io).not(lvs_io) +esd10_l1.output("ESD.10", "ESD.10 : LVS_IO shall be drawn covering I/O MOS active area by minimum overlap.") +esd10_l1.forget + + +end #FEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/geometry_rules.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/geometry_rules.drc new file mode 100644 index 000000000..37897b9d5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/geometry_rules.drc @@ -0,0 +1,750 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (GEOMETRY RULES) -------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +lvpwell = polygons(204, 0 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +sab = polygons(49 , 0 ) +esd = polygons(24 , 0 ) +contact = polygons(33 , 0 ) +metal1 = polygons(34 , 0 ) +via1 = polygons(35 , 0 ) +metal2 = polygons(36 , 0 ) +via2 = polygons(38 , 0 ) +metal3 = polygons(42 , 0 ) +via3 = polygons(40 , 0 ) +metal4 = polygons(46 , 0 ) +via4 = polygons(41 , 0 ) +metal5 = polygons(81 , 0 ) +via5 = polygons(82 , 0 ) +metaltop = polygons(53 , 0 ) +pad = polygons(37 , 0 ) +resistor = polygons(62 , 0 ) +fhres = polygons(227, 0 ) +fusetop = polygons(75 , 0 ) +fusewindow_d = polygons(96 , 1 ) +polyfuse = polygons(220, 0 ) +mvsd = polygons(210, 0 ) +mvpsd = polygons(11 , 39) +nat = polygons(5 , 0 ) +comp_dummy = polygons(22 , 4 ) +poly2_dummy = polygons(30 , 4 ) +metal1_dummy = polygons(34 , 4 ) +metal2_dummy = polygons(36 , 4 ) +metal3_dummy = polygons(42 , 4 ) +metal4_dummy = polygons(46 , 4 ) +metal5_dummy = polygons(81 , 4 ) +metaltop_dummy = polygons(53 , 4 ) +comp_label = polygons(22 , 10) +poly2_label = polygons(30 , 10) +metal1_label = polygons(34 , 10) +metal2_label = polygons(36 , 10) +metal3_label = polygons(42 , 10) +metal4_label = polygons(46 , 10) +metal5_label = polygons(81 , 10) +metaltop_label = polygons(53 , 10) +metal1_slot = polygons(34 , 3 ) +metal2_slot = polygons(36 , 3 ) +metal3_slot = polygons(42 , 3 ) +metal4_slot = polygons(46 , 3 ) +metal5_slot = polygons(81 , 3 ) +metaltop_slot = polygons(53 , 3 ) +ubmpperi = polygons(183, 0 ) +ubmparray = polygons(184, 0 ) +ubmeplate = polygons(185, 0 ) +schottky_diode = polygons(241, 0 ) +zener = polygons(178, 0 ) +res_mk = polygons(110, 5 ) +opc_drc = polygons(124, 5 ) +ndmy = polygons(111, 5 ) +pmndmy = polygons(152, 5 ) +v5_xtor = polygons(112, 1 ) +cap_mk = polygons(117, 5 ) +mos_cap_mk = polygons(166, 5 ) +ind_mk = polygons(151, 5 ) +diode_mk = polygons(115, 5 ) +drc_bjt = polygons(127, 5 ) +lvs_bjt = polygons(118, 5 ) +mim_l_mk = polygons(117, 10) +latchup_mk = polygons(137, 5 ) +guard_ring_mk = polygons(167, 5 ) +otp_mk = polygons(173, 5 ) +mtpmark = polygons(122, 5 ) +neo_ee_mk = polygons(88 , 17) +sramcore = polygons(108, 5 ) +lvs_rf = polygons(100, 5 ) +lvs_drain = polygons(100, 7 ) +ind_mk = polygons(151, 5 ) +hvpolyrs = polygons(123, 5 ) +lvs_io = polygons(119, 5 ) +probe_mk = polygons(13 , 17) +esd_mk = polygons(24 , 5 ) +lvs_source = polygons(100, 8 ) +well_diode_mk = polygons(153, 51) +ldmos_xtor = polygons(226, 0 ) +plfuse = polygons(125, 5 ) +efuse_mk = polygons(80 , 5 ) +mcell_feol_mk = polygons(11 , 17) +ymtp_mk = polygons(86 , 17) +dev_wf_mk = polygons(128, 17) +metal1_blk = polygons(34 , 5 ) +metal2_blk = polygons(36 , 5 ) +metal3_blk = polygons(42 , 5 ) +metal4_blk = polygons(46 , 5 ) +metal5_blk = polygons(81 , 5 ) +metalt_blk = polygons(53 , 5 ) +pr_bndry = polygons(0 , 0 ) +mdiode = polygons(116, 5 ) +metal1_res = polygons(110, 11) +metal2_res = polygons(110, 12) +metal3_res = polygons(110, 13) +metal4_res = polygons(110, 14) +metal5_res = polygons(110, 15) +metal6_res = polygons(110, 16) +border = polygons(63 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#-----------------GEOMETRY RULES----------------- +#================================================ + +if OFFGRID +logger.info("OFFGRID-ANGLES section") + +logger.info("Executing rule comp_OFFGRID") +comp.ongrid(0.005).output("comp_OFFGRID", "OFFGRID : OFFGRID vertex on comp") +comp.with_angle(0 .. 45).output("comp_angle", "ACUTE : non 45 degree angle comp") + +logger.info("Executing rule dnwell_OFFGRID") +dnwell.ongrid(0.005).output("dnwell_OFFGRID", "OFFGRID : OFFGRID vertex on dnwell") +dnwell.with_angle(0 .. 45).output("dnwell_angle", "ACUTE : non 45 degree angle dnwell") + +logger.info("Executing rule nwell_OFFGRID") +nwell.ongrid(0.005).output("nwell_OFFGRID", "OFFGRID : OFFGRID vertex on nwell") +nwell.with_angle(0 .. 45).output("nwell_angle", "ACUTE : non 45 degree angle nwell") + +logger.info("Executing rule lvpwell_OFFGRID") +lvpwell.ongrid(0.005).output("lvpwell_OFFGRID", "OFFGRID : OFFGRID vertex on lvpwell") +lvpwell.with_angle(0 .. 45).output("lvpwell_angle", "ACUTE : non 45 degree angle lvpwell") + +logger.info("Executing rule dualgate_OFFGRID") +dualgate.ongrid(0.005).output("dualgate_OFFGRID", "OFFGRID : OFFGRID vertex on dualgate") +dualgate.with_angle(0 .. 45).output("dualgate_angle", "ACUTE : non 45 degree angle dualgate") + +logger.info("Executing rule poly2_OFFGRID") +poly2.ongrid(0.005).output("poly2_OFFGRID", "OFFGRID : OFFGRID vertex on poly2") +poly2.with_angle(0 .. 45).output("poly2_angle", "ACUTE : non 45 degree angle poly2") + +logger.info("Executing rule nplus_OFFGRID") +nplus.ongrid(0.005).output("nplus_OFFGRID", "OFFGRID : OFFGRID vertex on nplus") +nplus.with_angle(0 .. 45).output("nplus_angle", "ACUTE : non 45 degree angle nplus") + +logger.info("Executing rule pplus_OFFGRID") +pplus.ongrid(0.005).output("pplus_OFFGRID", "OFFGRID : OFFGRID vertex on pplus") +pplus.with_angle(0 .. 45).output("pplus_angle", "ACUTE : non 45 degree angle pplus") + +logger.info("Executing rule sab_OFFGRID") +sab.ongrid(0.005).output("sab_OFFGRID", "OFFGRID : OFFGRID vertex on sab") +sab.with_angle(0 .. 45).output("sab_angle", "ACUTE : non 45 degree angle sab") + +logger.info("Executing rule esd_OFFGRID") +esd.ongrid(0.005).output("esd_OFFGRID", "OFFGRID : OFFGRID vertex on esd") +esd.with_angle(0 .. 45).output("esd_angle", "ACUTE : non 45 degree angle esd") + +logger.info("Executing rule contact_OFFGRID") +contact.ongrid(0.005).output("contact_OFFGRID", "OFFGRID : OFFGRID vertex on contact") +contact.with_angle(0 .. 45).output("contact_angle", "ACUTE : non 45 degree angle contact") + +logger.info("Executing rule metal1_OFFGRID") +metal1.ongrid(0.005).output("metal1_OFFGRID", "OFFGRID : OFFGRID vertex on metal1") +metal1.with_angle(0 .. 45).output("metal1_angle", "ACUTE : non 45 degree angle metal1") + +logger.info("Executing rule via1_OFFGRID") +via1.ongrid(0.005).output("via1_OFFGRID", "OFFGRID : OFFGRID vertex on via1") +via1.with_angle(0 .. 45).output("via1_angle", "ACUTE : non 45 degree angle via1") + +logger.info("Executing rule metal2_OFFGRID") +metal2.ongrid(0.005).output("metal2_OFFGRID", "OFFGRID : OFFGRID vertex on metal2") +metal2.with_angle(0 .. 45).output("metal2_angle", "ACUTE : non 45 degree angle metal2") + +logger.info("Executing rule via2_OFFGRID") +via2.ongrid(0.005).output("via2_OFFGRID", "OFFGRID : OFFGRID vertex on via2") +via2.with_angle(0 .. 45).output("via2_angle", "ACUTE : non 45 degree angle via2") + +logger.info("Executing rule metal3_OFFGRID") +metal3.ongrid(0.005).output("metal3_OFFGRID", "OFFGRID : OFFGRID vertex on metal3") +metal3.with_angle(0 .. 45).output("metal3_angle", "ACUTE : non 45 degree angle metal3") + +logger.info("Executing rule via3_OFFGRID") +via3.ongrid(0.005).output("via3_OFFGRID", "OFFGRID : OFFGRID vertex on via3") +via3.with_angle(0 .. 45).output("via3_angle", "ACUTE : non 45 degree angle via3") + +logger.info("Executing rule metal4_OFFGRID") +metal4.ongrid(0.005).output("metal4_OFFGRID", "OFFGRID : OFFGRID vertex on metal4") +metal4.with_angle(0 .. 45).output("metal4_angle", "ACUTE : non 45 degree angle metal4") + +logger.info("Executing rule via4_OFFGRID") +via4.ongrid(0.005).output("via4_OFFGRID", "OFFGRID : OFFGRID vertex on via4") +via4.with_angle(0 .. 45).output("via4_angle", "ACUTE : non 45 degree angle via4") + +logger.info("Executing rule metal5_OFFGRID") +metal5.ongrid(0.005).output("metal5_OFFGRID", "OFFGRID : OFFGRID vertex on metal5") +metal5.with_angle(0 .. 45).output("metal5_angle", "ACUTE : non 45 degree angle metal5") + +logger.info("Executing rule via5_OFFGRID") +via5.ongrid(0.005).output("via5_OFFGRID", "OFFGRID : OFFGRID vertex on via5") +via5.with_angle(0 .. 45).output("via5_angle", "ACUTE : non 45 degree angle via5") + +logger.info("Executing rule metaltop_OFFGRID") +metaltop.ongrid(0.005).output("metaltop_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop") +metaltop.with_angle(0 .. 45).output("metaltop_angle", "ACUTE : non 45 degree angle metaltop") + +logger.info("Executing rule pad_OFFGRID") +pad.ongrid(0.005).output("pad_OFFGRID", "OFFGRID : OFFGRID vertex on pad") +pad.with_angle(0 .. 45).output("pad_angle", "ACUTE : non 45 degree angle pad") + +logger.info("Executing rule resistor_OFFGRID") +resistor.ongrid(0.005).output("resistor_OFFGRID", "OFFGRID : OFFGRID vertex on resistor") +resistor.with_angle(0 .. 45).output("resistor_angle", "ACUTE : non 45 degree angle resistor") + +logger.info("Executing rule fhres_OFFGRID") +fhres.ongrid(0.005).output("fhres_OFFGRID", "OFFGRID : OFFGRID vertex on fhres") +fhres.with_angle(0 .. 45).output("fhres_angle", "ACUTE : non 45 degree angle fhres") + +logger.info("Executing rule fusetop_OFFGRID") +fusetop.ongrid(0.005).output("fusetop_OFFGRID", "OFFGRID : OFFGRID vertex on fusetop") +fusetop.with_angle(0 .. 45).output("fusetop_angle", "ACUTE : non 45 degree angle fusetop") + +logger.info("Executing rule fusewindow_d_OFFGRID") +fusewindow_d.ongrid(0.005).output("fusewindow_d_OFFGRID", "OFFGRID : OFFGRID vertex on fusewindow_d") +fusewindow_d.with_angle(0 .. 45).output("fusewindow_d_angle", "ACUTE : non 45 degree angle fusewindow_d") + +logger.info("Executing rule polyfuse_OFFGRID") +polyfuse.ongrid(0.005).output("polyfuse_OFFGRID", "OFFGRID : OFFGRID vertex on polyfuse") +polyfuse.with_angle(0 .. 45).output("polyfuse_angle", "ACUTE : non 45 degree angle polyfuse") + +logger.info("Executing rule mvsd_OFFGRID") +mvsd.ongrid(0.005).output("mvsd_OFFGRID", "OFFGRID : OFFGRID vertex on mvsd") +mvsd.with_angle(0 .. 45).output("mvsd_angle", "ACUTE : non 45 degree angle mvsd") + +logger.info("Executing rule mvpsd_OFFGRID") +mvpsd.ongrid(0.005).output("mvpsd_OFFGRID", "OFFGRID : OFFGRID vertex on mvpsd") +mvpsd.with_angle(0 .. 45).output("mvpsd_angle", "ACUTE : non 45 degree angle mvpsd") + +logger.info("Executing rule nat_OFFGRID") +nat.ongrid(0.005).output("nat_OFFGRID", "OFFGRID : OFFGRID vertex on nat") +nat.with_angle(0 .. 45).output("nat_angle", "ACUTE : non 45 degree angle nat") + +logger.info("Executing rule comp_dummy_OFFGRID") +comp_dummy.ongrid(0.005).output("comp_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on comp_dummy") +comp_dummy.with_angle(0 .. 45).output("comp_dummy_angle", "ACUTE : non 45 degree angle comp_dummy") + +logger.info("Executing rule poly2_dummy_OFFGRID") +poly2_dummy.ongrid(0.005).output("poly2_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on poly2_dummy") +poly2_dummy.with_angle(0 .. 45).output("poly2_dummy_angle", "ACUTE : non 45 degree angle poly2_dummy") + +logger.info("Executing rule metal1_dummy_OFFGRID") +metal1_dummy.ongrid(0.005).output("metal1_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_dummy") +metal1_dummy.with_angle(0 .. 45).output("metal1_dummy_angle", "ACUTE : non 45 degree angle metal1_dummy") + +logger.info("Executing rule metal2_dummy_OFFGRID") +metal2_dummy.ongrid(0.005).output("metal2_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_dummy") +metal2_dummy.with_angle(0 .. 45).output("metal2_dummy_angle", "ACUTE : non 45 degree angle metal2_dummy") + +logger.info("Executing rule metal3_dummy_OFFGRID") +metal3_dummy.ongrid(0.005).output("metal3_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_dummy") +metal3_dummy.with_angle(0 .. 45).output("metal3_dummy_angle", "ACUTE : non 45 degree angle metal3_dummy") + +logger.info("Executing rule metal4_dummy_OFFGRID") +metal4_dummy.ongrid(0.005).output("metal4_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_dummy") +metal4_dummy.with_angle(0 .. 45).output("metal4_dummy_angle", "ACUTE : non 45 degree angle metal4_dummy") + +logger.info("Executing rule metal5_dummy_OFFGRID") +metal5_dummy.ongrid(0.005).output("metal5_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_dummy") +metal5_dummy.with_angle(0 .. 45).output("metal5_dummy_angle", "ACUTE : non 45 degree angle metal5_dummy") + +logger.info("Executing rule metaltop_dummy_OFFGRID") +metaltop_dummy.ongrid(0.005).output("metaltop_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop_dummy") +metaltop_dummy.with_angle(0 .. 45).output("metaltop_dummy_angle", "ACUTE : non 45 degree angle metaltop_dummy") + +logger.info("Executing rule comp_label_OFFGRID") +comp_label.ongrid(0.005).output("comp_label_OFFGRID", "OFFGRID : OFFGRID vertex on comp_label") +comp_label.with_angle(0 .. 45).output("comp_label_angle", "ACUTE : non 45 degree angle comp_label") + +logger.info("Executing rule poly2_label_OFFGRID") +poly2_label.ongrid(0.005).output("poly2_label_OFFGRID", "OFFGRID : OFFGRID vertex on poly2_label") +poly2_label.with_angle(0 .. 45).output("poly2_label_angle", "ACUTE : non 45 degree angle poly2_label") + +logger.info("Executing rule metal1_label_OFFGRID") +metal1_label.ongrid(0.005).output("metal1_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_label") +metal1_label.with_angle(0 .. 45).output("metal1_label_angle", "ACUTE : non 45 degree angle metal1_label") + +logger.info("Executing rule metal2_label_OFFGRID") +metal2_label.ongrid(0.005).output("metal2_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_label") +metal2_label.with_angle(0 .. 45).output("metal2_label_angle", "ACUTE : non 45 degree angle metal2_label") + +logger.info("Executing rule metal3_label_OFFGRID") +metal3_label.ongrid(0.005).output("metal3_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_label") +metal3_label.with_angle(0 .. 45).output("metal3_label_angle", "ACUTE : non 45 degree angle metal3_label") + +logger.info("Executing rule metal4_label_OFFGRID") +metal4_label.ongrid(0.005).output("metal4_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_label") +metal4_label.with_angle(0 .. 45).output("metal4_label_angle", "ACUTE : non 45 degree angle metal4_label") + +logger.info("Executing rule metal5_label_OFFGRID") +metal5_label.ongrid(0.005).output("metal5_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_label") +metal5_label.with_angle(0 .. 45).output("metal5_label_angle", "ACUTE : non 45 degree angle metal5_label") + +logger.info("Executing rule metaltop_label_OFFGRID") +metaltop_label.ongrid(0.005).output("metaltop_label_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop_label") +metaltop_label.with_angle(0 .. 45).output("metaltop_label_angle", "ACUTE : non 45 degree angle metaltop_label") + +logger.info("Executing rule metal1_slot_OFFGRID") +metal1_slot.ongrid(0.005).output("metal1_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_slot") +metal1_slot.with_angle(0 .. 45).output("metal1_slot_angle", "ACUTE : non 45 degree angle metal1_slot") + +logger.info("Executing rule metal2_slot_OFFGRID") +metal2_slot.ongrid(0.005).output("metal2_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_slot") +metal2_slot.with_angle(0 .. 45).output("metal2_slot_angle", "ACUTE : non 45 degree angle metal2_slot") + +logger.info("Executing rule metal3_slot_OFFGRID") +metal3_slot.ongrid(0.005).output("metal3_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_slot") +metal3_slot.with_angle(0 .. 45).output("metal3_slot_angle", "ACUTE : non 45 degree angle metal3_slot") + +logger.info("Executing rule metal4_slot_OFFGRID") +metal4_slot.ongrid(0.005).output("metal4_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_slot") +metal4_slot.with_angle(0 .. 45).output("metal4_slot_angle", "ACUTE : non 45 degree angle metal4_slot") + +logger.info("Executing rule metal5_slot_OFFGRID") +metal5_slot.ongrid(0.005).output("metal5_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_slot") +metal5_slot.with_angle(0 .. 45).output("metal5_slot_angle", "ACUTE : non 45 degree angle metal5_slot") + +logger.info("Executing rule metaltop_slot_OFFGRID") +metaltop_slot.ongrid(0.005).output("metaltop_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop_slot") +metaltop_slot.with_angle(0 .. 45).output("metaltop_slot_angle", "ACUTE : non 45 degree angle metaltop_slot") + +logger.info("Executing rule ubmpperi_OFFGRID") +ubmpperi.ongrid(0.005).output("ubmpperi_OFFGRID", "OFFGRID : OFFGRID vertex on ubmpperi") +ubmpperi.with_angle(0 .. 45).output("ubmpperi_angle", "ACUTE : non 45 degree angle ubmpperi") + +logger.info("Executing rule ubmparray_OFFGRID") +ubmparray.ongrid(0.005).output("ubmparray_OFFGRID", "OFFGRID : OFFGRID vertex on ubmparray") +ubmparray.with_angle(0 .. 45).output("ubmparray_angle", "ACUTE : non 45 degree angle ubmparray") + +logger.info("Executing rule ubmeplate_OFFGRID") +ubmeplate.ongrid(0.005).output("ubmeplate_OFFGRID", "OFFGRID : OFFGRID vertex on ubmeplate") +ubmeplate.with_angle(0 .. 45).output("ubmeplate_angle", "ACUTE : non 45 degree angle ubmeplate") + +logger.info("Executing rule schottky_diode_OFFGRID") +schottky_diode.ongrid(0.005).output("schottky_diode_OFFGRID", "OFFGRID : OFFGRID vertex on schottky_diode") +schottky_diode.with_angle(0 .. 45).output("schottky_diode_angle", "ACUTE : non 45 degree angle schottky_diode") + +logger.info("Executing rule zener_OFFGRID") +zener.ongrid(0.005).output("zener_OFFGRID", "OFFGRID : OFFGRID vertex on zener") +zener.with_angle(0 .. 45).output("zener_angle", "ACUTE : non 45 degree angle zener") + +logger.info("Executing rule res_mk_OFFGRID") +res_mk.ongrid(0.005).output("res_mk_OFFGRID", "OFFGRID : OFFGRID vertex on res_mk") +res_mk.with_angle(0 .. 45).output("res_mk_angle", "ACUTE : non 45 degree angle res_mk") + +logger.info("Executing rule opc_drc_OFFGRID") +opc_drc.ongrid(0.005).output("opc_drc_OFFGRID", "OFFGRID : OFFGRID vertex on opc_drc") +opc_drc.with_angle(0 .. 45).output("opc_drc_angle", "ACUTE : non 45 degree angle opc_drc") + +logger.info("Executing rule ndmy_OFFGRID") +ndmy.ongrid(0.005).output("ndmy_OFFGRID", "OFFGRID : OFFGRID vertex on ndmy") +ndmy.with_angle(0 .. 45).output("ndmy_angle", "ACUTE : non 45 degree angle ndmy") + +logger.info("Executing rule pmndmy_OFFGRID") +pmndmy.ongrid(0.005).output("pmndmy_OFFGRID", "OFFGRID : OFFGRID vertex on pmndmy") +pmndmy.with_angle(0 .. 45).output("pmndmy_angle", "ACUTE : non 45 degree angle pmndmy") + +logger.info("Executing rule v5_xtor_OFFGRID") +v5_xtor.ongrid(0.005).output("v5_xtor_OFFGRID", "OFFGRID : OFFGRID vertex on v5_xtor") +v5_xtor.with_angle(0 .. 45).output("v5_xtor_angle", "ACUTE : non 45 degree angle v5_xtor") + +logger.info("Executing rule cap_mk_OFFGRID") +cap_mk.ongrid(0.005).output("cap_mk_OFFGRID", "OFFGRID : OFFGRID vertex on cap_mk") +cap_mk.with_angle(0 .. 45).output("cap_mk_angle", "ACUTE : non 45 degree angle cap_mk") + +logger.info("Executing rule mos_cap_mk_OFFGRID") +mos_cap_mk.ongrid(0.005).output("mos_cap_mk_OFFGRID", "OFFGRID : OFFGRID vertex on mos_cap_mk") +mos_cap_mk.with_angle(0 .. 45).output("mos_cap_mk_angle", "ACUTE : non 45 degree angle mos_cap_mk") + +logger.info("Executing rule ind_mk_OFFGRID") +ind_mk.ongrid(0.005).output("ind_mk_OFFGRID", "OFFGRID : OFFGRID vertex on ind_mk") +ind_mk.with_angle(0 .. 45).output("ind_mk_angle", "ACUTE : non 45 degree angle ind_mk") + +logger.info("Executing rule diode_mk_OFFGRID") +diode_mk.ongrid(0.005).output("diode_mk_OFFGRID", "OFFGRID : OFFGRID vertex on diode_mk") +diode_mk.with_angle(0 .. 45).output("diode_mk_angle", "ACUTE : non 45 degree angle diode_mk") + +logger.info("Executing rule drc_bjt_OFFGRID") +drc_bjt.ongrid(0.005).output("drc_bjt_OFFGRID", "OFFGRID : OFFGRID vertex on drc_bjt") +drc_bjt.with_angle(0 .. 45).output("drc_bjt_angle", "ACUTE : non 45 degree angle drc_bjt") + +logger.info("Executing rule lvs_bjt_OFFGRID") +lvs_bjt.ongrid(0.005).output("lvs_bjt_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_bjt") +lvs_bjt.with_angle(0 .. 45).output("lvs_bjt_angle", "ACUTE : non 45 degree angle lvs_bjt") + +logger.info("Executing rule mim_l_mk_OFFGRID") +mim_l_mk.ongrid(0.005).output("mim_l_mk_OFFGRID", "OFFGRID : OFFGRID vertex on mim_l_mk") +mim_l_mk.with_angle(0 .. 45).output("mim_l_mk_angle", "ACUTE : non 45 degree angle mim_l_mk") + +logger.info("Executing rule latchup_mk_OFFGRID") +latchup_mk.ongrid(0.005).output("latchup_mk_OFFGRID", "OFFGRID : OFFGRID vertex on latchup_mk") +latchup_mk.with_angle(0 .. 45).output("latchup_mk_angle", "ACUTE : non 45 degree angle latchup_mk") + +logger.info("Executing rule guard_ring_mk_OFFGRID") +guard_ring_mk.ongrid(0.005).output("guard_ring_mk_OFFGRID", "OFFGRID : OFFGRID vertex on guard_ring_mk") +guard_ring_mk.with_angle(0 .. 45).output("guard_ring_mk_angle", "ACUTE : non 45 degree angle guard_ring_mk") + +logger.info("Executing rule otp_mk_OFFGRID") +otp_mk.ongrid(0.005).output("otp_mk_OFFGRID", "OFFGRID : OFFGRID vertex on otp_mk") +otp_mk.with_angle(0 .. 45).output("otp_mk_angle", "ACUTE : non 45 degree angle otp_mk") + +logger.info("Executing rule mtpmark_OFFGRID") +mtpmark.ongrid(0.005).output("mtpmark_OFFGRID", "OFFGRID : OFFGRID vertex on mtpmark") +mtpmark.with_angle(0 .. 45).output("mtpmark_angle", "ACUTE : non 45 degree angle mtpmark") + +logger.info("Executing rule neo_ee_mk_OFFGRID") +neo_ee_mk.ongrid(0.005).output("neo_ee_mk_OFFGRID", "OFFGRID : OFFGRID vertex on neo_ee_mk") +neo_ee_mk.with_angle(0 .. 45).output("neo_ee_mk_angle", "ACUTE : non 45 degree angle neo_ee_mk") + +logger.info("Executing rule sramcore_OFFGRID") +sramcore.ongrid(0.005).output("sramcore_OFFGRID", "OFFGRID : OFFGRID vertex on sramcore") +sramcore.with_angle(0 .. 45).output("sramcore_angle", "ACUTE : non 45 degree angle sramcore") + +logger.info("Executing rule lvs_rf_OFFGRID") +lvs_rf.ongrid(0.005).output("lvs_rf_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_rf") +lvs_rf.with_angle(0 .. 45).output("lvs_rf_angle", "ACUTE : non 45 degree angle lvs_rf") + +logger.info("Executing rule lvs_drain_OFFGRID") +lvs_drain.ongrid(0.005).output("lvs_drain_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_drain") +lvs_drain.with_angle(0 .. 45).output("lvs_drain_angle", "ACUTE : non 45 degree angle lvs_drain") + +logger.info("Executing rule ind_mk_OFFGRID") +ind_mk.ongrid(0.005).output("ind_mk_OFFGRID", "OFFGRID : OFFGRID vertex on ind_mk") +ind_mk.with_angle(0 .. 45).output("ind_mk_angle", "ACUTE : non 45 degree angle ind_mk") + +logger.info("Executing rule hvpolyrs_OFFGRID") +hvpolyrs.ongrid(0.005).output("hvpolyrs_OFFGRID", "OFFGRID : OFFGRID vertex on hvpolyrs") +hvpolyrs.with_angle(0 .. 45).output("hvpolyrs_angle", "ACUTE : non 45 degree angle hvpolyrs") + +logger.info("Executing rule lvs_io_OFFGRID") +lvs_io.ongrid(0.005).output("lvs_io_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_io") +lvs_io.with_angle(0 .. 45).output("lvs_io_angle", "ACUTE : non 45 degree angle lvs_io") + +logger.info("Executing rule probe_mk_OFFGRID") +probe_mk.ongrid(0.005).output("probe_mk_OFFGRID", "OFFGRID : OFFGRID vertex on probe_mk") +probe_mk.with_angle(0 .. 45).output("probe_mk_angle", "ACUTE : non 45 degree angle probe_mk") + +logger.info("Executing rule esd_mk_OFFGRID") +esd_mk.ongrid(0.005).output("esd_mk_OFFGRID", "OFFGRID : OFFGRID vertex on esd_mk") +esd_mk.with_angle(0 .. 45).output("esd_mk_angle", "ACUTE : non 45 degree angle esd_mk") + +logger.info("Executing rule lvs_source_OFFGRID") +lvs_source.ongrid(0.005).output("lvs_source_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_source") +lvs_source.with_angle(0 .. 45).output("lvs_source_angle", "ACUTE : non 45 degree angle lvs_source") + +logger.info("Executing rule well_diode_mk_OFFGRID") +well_diode_mk.ongrid(0.005).output("well_diode_mk_OFFGRID", "OFFGRID : OFFGRID vertex on well_diode_mk") +well_diode_mk.with_angle(0 .. 45).output("well_diode_mk_angle", "ACUTE : non 45 degree angle well_diode_mk") + +logger.info("Executing rule ldmos_xtor_OFFGRID") +ldmos_xtor.ongrid(0.005).output("ldmos_xtor_OFFGRID", "OFFGRID : OFFGRID vertex on ldmos_xtor") +ldmos_xtor.with_angle(0 .. 45).output("ldmos_xtor_angle", "ACUTE : non 45 degree angle ldmos_xtor") + +logger.info("Executing rule plfuse_OFFGRID") +plfuse.ongrid(0.005).output("plfuse_OFFGRID", "OFFGRID : OFFGRID vertex on plfuse") +plfuse.with_angle(0 .. 45).output("plfuse_angle", "ACUTE : non 45 degree angle plfuse") + +logger.info("Executing rule efuse_mk_OFFGRID") +efuse_mk.ongrid(0.005).output("efuse_mk_OFFGRID", "OFFGRID : OFFGRID vertex on efuse_mk") +efuse_mk.with_angle(0 .. 45).output("efuse_mk_angle", "ACUTE : non 45 degree angle efuse_mk") + +logger.info("Executing rule mcell_feol_mk_OFFGRID") +mcell_feol_mk.ongrid(0.005).output("mcell_feol_mk_OFFGRID", "OFFGRID : OFFGRID vertex on mcell_feol_mk") +mcell_feol_mk.with_angle(0 .. 45).output("mcell_feol_mk_angle", "ACUTE : non 45 degree angle mcell_feol_mk") + +logger.info("Executing rule ymtp_mk_OFFGRID") +ymtp_mk.ongrid(0.005).output("ymtp_mk_OFFGRID", "OFFGRID : OFFGRID vertex on ymtp_mk") +ymtp_mk.with_angle(0 .. 45).output("ymtp_mk_angle", "ACUTE : non 45 degree angle ymtp_mk") + +logger.info("Executing rule dev_wf_mk_OFFGRID") +dev_wf_mk.ongrid(0.005).output("dev_wf_mk_OFFGRID", "OFFGRID : OFFGRID vertex on dev_wf_mk") +dev_wf_mk.with_angle(0 .. 45).output("dev_wf_mk_angle", "ACUTE : non 45 degree angle dev_wf_mk") + +logger.info("Executing rule metal1_blk_OFFGRID") +metal1_blk.ongrid(0.005).output("metal1_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_blk") +metal1_blk.with_angle(0 .. 45).output("metal1_blk_angle", "ACUTE : non 45 degree angle metal1_blk") + +logger.info("Executing rule metal2_blk_OFFGRID") +metal2_blk.ongrid(0.005).output("metal2_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_blk") +metal2_blk.with_angle(0 .. 45).output("metal2_blk_angle", "ACUTE : non 45 degree angle metal2_blk") + +logger.info("Executing rule metal3_blk_OFFGRID") +metal3_blk.ongrid(0.005).output("metal3_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_blk") +metal3_blk.with_angle(0 .. 45).output("metal3_blk_angle", "ACUTE : non 45 degree angle metal3_blk") + +logger.info("Executing rule metal4_blk_OFFGRID") +metal4_blk.ongrid(0.005).output("metal4_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_blk") +metal4_blk.with_angle(0 .. 45).output("metal4_blk_angle", "ACUTE : non 45 degree angle metal4_blk") + +logger.info("Executing rule metal5_blk_OFFGRID") +metal5_blk.ongrid(0.005).output("metal5_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_blk") +metal5_blk.with_angle(0 .. 45).output("metal5_blk_angle", "ACUTE : non 45 degree angle metal5_blk") + +logger.info("Executing rule metalt_blk_OFFGRID") +metalt_blk.ongrid(0.005).output("metalt_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metalt_blk") +metalt_blk.with_angle(0 .. 45).output("metalt_blk_angle", "ACUTE : non 45 degree angle metalt_blk") + +logger.info("Executing rule pr_bndry_OFFGRID") +pr_bndry.ongrid(0.005).output("pr_bndry_OFFGRID", "OFFGRID : OFFGRID vertex on pr_bndry") +pr_bndry.with_angle(0 .. 45).output("pr_bndry_angle", "ACUTE : non 45 degree angle pr_bndry") + +logger.info("Executing rule mdiode_OFFGRID") +mdiode.ongrid(0.005).output("mdiode_OFFGRID", "OFFGRID : OFFGRID vertex on mdiode") +mdiode.with_angle(0 .. 45).output("mdiode_angle", "ACUTE : non 45 degree angle mdiode") + +logger.info("Executing rule metal1_res_OFFGRID") +metal1_res.ongrid(0.005).output("metal1_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_res") +metal1_res.with_angle(0 .. 45).output("metal1_res_angle", "ACUTE : non 45 degree angle metal1_res") + +logger.info("Executing rule metal2_res_OFFGRID") +metal2_res.ongrid(0.005).output("metal2_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_res") +metal2_res.with_angle(0 .. 45).output("metal2_res_angle", "ACUTE : non 45 degree angle metal2_res") + +logger.info("Executing rule metal3_res_OFFGRID") +metal3_res.ongrid(0.005).output("metal3_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_res") +metal3_res.with_angle(0 .. 45).output("metal3_res_angle", "ACUTE : non 45 degree angle metal3_res") + +logger.info("Executing rule metal4_res_OFFGRID") +metal4_res.ongrid(0.005).output("metal4_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_res") +metal4_res.with_angle(0 .. 45).output("metal4_res_angle", "ACUTE : non 45 degree angle metal4_res") + +logger.info("Executing rule metal5_res_OFFGRID") +metal5_res.ongrid(0.005).output("metal5_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_res") +metal5_res.with_angle(0 .. 45).output("metal5_res_angle", "ACUTE : non 45 degree angle metal5_res") + +logger.info("Executing rule metal6_res_OFFGRID") +metal6_res.ongrid(0.005).output("metal6_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal6_res") +metal6_res.with_angle(0 .. 45).output("metal6_res_angle", "ACUTE : non 45 degree angle metal6_res") + +logger.info("Executing rule border_OFFGRID") +border.ongrid(0.005).output("border_OFFGRID", "OFFGRID : OFFGRID vertex on border") +border.with_angle(0 .. 45).output("border_angle", "ACUTE : non 45 degree angle border") + +end #OFFGRID-ANGLES + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/h_poly_resistor.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/h_poly_resistor.drc new file mode 100644 index 000000000..e7535fccb --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/h_poly_resistor.drc @@ -0,0 +1,321 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (H POLY RESISTOR) ------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +sab = polygons(49 , 0 ) +contact = polygons(33 , 0 ) +resistor = polygons(62 , 0 ) +res_mk = polygons(110, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#----------------H POLY RESISTOR----------------- +#================================================ + +hres_poly = poly2.interacting(pplus).interacting(sab).interacting(res_mk).interacting(resistor) +hres1_poly = poly2.interacting(pplus).interacting(sab).interacting(res_mk) +# Rule HRES.1: Minimum space. Note : Merge if the spacing is less than 0.4 um. is 0.4µm +logger.info("Executing rule HRES.1") +hres1_l1 = resistor.interacting(hres1_poly).space(0.4.um, euclidian).polygons(0.001) +hres1_l1.output("HRES.1", "HRES.1 : Minimum space. Note : Merge if the spacing is less than 0.4 um. : 0.4µm") +hres1_l1.forget + +# Rule HRES.2: Minimum width of Poly2 resistor. is 1µm +logger.info("Executing rule HRES.2") +hres2_l1 = hres_poly.width(1.um, euclidian).polygons(0.001) +hres2_l1.output("HRES.2", "HRES.2 : Minimum width of Poly2 resistor. : 1µm") +hres2_l1.forget + +# Rule HRES.3: Minimum space between Poly2 resistors. is 0.4µm +logger.info("Executing rule HRES.3") +hres3_l1 = hres_poly.space(0.4.um, euclidian).polygons(0.001) +hres3_l1.output("HRES.3", "HRES.3 : Minimum space between Poly2 resistors. : 0.4µm") +hres3_l1.forget + +# Rule HRES.4: Minimum RESISTOR overlap of Poly2 resistor. is 0.4µm +logger.info("Executing rule HRES.4") +hres4_l1 = resistor.enclosing(hres_poly, 0.4.um, euclidian).polygons(0.001) +hres4_l2 = hres_poly.not_outside(resistor).not(resistor) +hres4_l = hres4_l1.or(hres4_l2) +hres4_l.output("HRES.4", "HRES.4 : Minimum RESISTOR overlap of Poly2 resistor. : 0.4µm") +hres4_l1.forget +hres4_l2.forget +hres4_l.forget + +# Rule HRES.5: Minimum RESISTOR space to unrelated Poly2. is 0.3µm +logger.info("Executing rule HRES.5") +hres5_l1 = resistor.interacting(hres1_poly).separation(poly2.not_interacting(sab), 0.3.um, euclidian).polygons(0.001) +hres5_l1.output("HRES.5", "HRES.5 : Minimum RESISTOR space to unrelated Poly2. : 0.3µm") +hres5_l1.forget + +# Rule HRES.6: Minimum RESISTOR space to COMP. +logger.info("Executing rule HRES.6") +hres6_l1 = resistor.interacting(hres1_poly).separation(comp, 0.3.um, euclidian).polygons(0.001).or(comp.not_outside(resistor.interacting(poly2.interacting(pplus).interacting(sab).interacting(res_mk)))) +hres6_l1.output("HRES.6", "HRES.6 : Minimum RESISTOR space to COMP.") +hres6_l1.forget + +hres1_poly.forget +# Rule HRES.7: Minimum Pplus overlap of contact on Poly2 resistor. is 0.2µm +logger.info("Executing rule HRES.7") +hres7_l1 = pplus.enclosing(contact.inside(hres_poly), 0.2.um, euclidian).polygons(0.001) +hres7_l2 = contact.inside(hres_poly).not_outside(pplus).not(pplus) +hres7_l = hres7_l1.or(hres7_l2) +hres7_l.output("HRES.7", "HRES.7 : Minimum Pplus overlap of contact on Poly2 resistor. : 0.2µm") +hres7_l1.forget +hres7_l2.forget +hres7_l.forget + +# Rule HRES.8: Space from salicide block to contact on Poly2 resistor. +logger.info("Executing rule HRES.8") +hres8_l1 = contact.inside(hres_poly).separation(sab,0.22.um).polygons(0.001).or(contact.inside(hres_poly).interacting(sab)) +hres8_l1.output("HRES.8", "HRES.8 : Space from salicide block to contact on Poly2 resistor.") +hres8_l1.forget + +hres9_sab = sab.interacting(pplus).interacting(res_mk).interacting(resistor) +hres9_clear_sab = hres9_sab.not(hres_poly) +hres9_bad_inside_edge = hres9_sab.edges.inside_part(hres_poly).extended(0,0,0.001,0.001).interacting(hres9_clear_sab, 1, 1) +hres9_sab_hole = hres9_sab.holes.and(hres_poly) +# Rule HRES.9: Minimum salicide block overlap of Poly2 resistor in width direction. +logger.info("Executing rule HRES.9") +hres9_l1 = hres9_sab.enclosing(hres_poly, 0.28.um, euclidian).polygons(0.001).or(hres9_bad_inside_edge).or(hres9_sab_hole) +hres9_l1.output("HRES.9", "HRES.9 : Minimum salicide block overlap of Poly2 resistor in width direction.") +hres9_l1.forget + +hres9_sab.forget +hres9_clear_sab.forget +hres9_bad_inside_edge.forget +hres9_sab_hole.forget +pplus1_hres10 = pplus.and(sab).drc(width != 0.1.um) +pplus2_hres10 = pplus.not_overlapping(sab).edges +# Rule HRES.10: Minimum & maximum Pplus overlap of SAB. +logger.info("Executing rule HRES.10") +hres10_l1 = pplus1_hres10.or(pplus2_hres10).extended(0, 0, 0.001, 0.001).interacting(hres_poly) +hres10_l1.output("HRES.10", "HRES.10 : Minimum & maximum Pplus overlap of SAB.") +hres10_l1.forget + +pplus1_hres10.forget +pplus2_hres10.forget +# rule HRES.11 is not a DRC check + +mk_hres12a = res_mk.edges.not(poly2.not(pplus).and(sab).edges).inside_part(poly2) +# Rule HRES.12a: P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. +logger.info("Executing rule HRES.12a") +hres12a_l1 = res_mk.interacting(resistor).interacting(mk_hres12a) +hres12a_l1.output("HRES.12a", "HRES.12a : P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. ") +hres12a_l1.forget + +mk_hres12a.forget +hres12b = res_mk.with_area(15000.01.um,nil).in(res_mk.interacting(res_mk.edges.with_length(80.01.um,nil))) +# Rule HRES.12b: If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer. is 20µm +logger.info("Executing rule HRES.12b") +hres12b_l1 = res_mk.interacting(hres_poly).drc(separation(hres12b) < 20.um).polygons(0.001) +hres12b_l1.output("HRES.12b", "HRES.12b : If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer. : 20µm") +hres12b_l1.forget + +hres12b.forget +hres_poly.forget + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/lvpwell.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/lvpwell.drc new file mode 100644 index 000000000..2bc38a52a --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/lvpwell.drc @@ -0,0 +1,426 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (LVPWELL) ----------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +lvpwell = polygons(204, 0 ) +sab = polygons(49 , 0 ) +res_mk = polygons(110, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) +#================================================ +#------------- LAYERS CONNECTIONS --------------- +#================================================ + +if CONNECTIVITY_RULES + + logger.info("Construct connectivity for the design.") + + connect(dnwell, ncomp) + connect(ncomp, contact) + connect(pcomp, contact) + connect(lvpwell, ncomp) + connect(nwell, ncomp) + connect(natcompsd, contact) + connect(mvsd, ncomp) + connect(mvpsd, pcomp) + connect(contact, metal1) + connect(metal1, via1) + connect(via1, metal2) + connect(metal2, via2) + connect(via2, metal3) + connect(metal3, via3) + connect(via3, metal4) + connect(metal4, via4) + connect(via4, metal5) + connect(metal5, via5) + connect(via5, metaltop) + +end #CONNECTIVITY_RULES + +#================================================ +#------------ PRE-DEFINED FUNCTIONS ------------- +#================================================ + +def conn_space(layer,conn_val,not_conn_val, mode) + if conn_val > not_conn_val + raise "ERROR : Wrong connectivity implementation" + end + connected_output = layer.space(conn_val.um, mode).polygons(0.001) + unconnected_errors_unfiltered = layer.space(not_conn_val.um, mode) + singularity_errors = layer.space(0.001.um) + # Filter out the errors arising from the same net + unconnected_errors = DRC::DRCLayer::new(self, RBA::EdgePairs::new) + unconnected_errors_unfiltered.data.each do |ep| + net1 = l2n_data.probe_net(layer.data, ep.first.p1) + net2 = l2n_data.probe_net(layer.data, ep.second.p1) + if !net1 || !net2 + puts "Should not happen ..." + elsif net1.circuit != net2.circuit || net1.cluster_id != net2.cluster_id + # unconnected + unconnected_errors.data.insert(ep) + end + end + unconnected_output = unconnected_errors.polygons.or(singularity_errors.polygons(0.001)) + return connected_output, unconnected_output +end + +def conn_separation(layer1, layer2, conn_val,not_conn_val, mode) + if conn_val > not_conn_val + raise "ERROR : Wrong connectivity implementation" + end + connected_output = layer1.separation(layer2, conn_val.um, mode).polygons(0.001) + unconnected_errors_unfiltered = layer1.separation(layer2, not_conn_val.um, mode) + # Filter out the errors arising from the same net + unconnected_errors = DRC::DRCLayer::new(self, RBA::EdgePairs::new) + unconnected_errors_unfiltered.data.each do |ep| + net1 = l2n_data.probe_net(layer1.data, ep.first.p1) + net2 = l2n_data.probe_net(layer2.data, ep.second.p1) + if !net1 || !net2 + puts "Should not happen ..." + elsif net1.circuit != net2.circuit || net1.cluster_id != net2.cluster_id + # unconnected + unconnected_errors.data.insert(ep) + end + end + unconnected_output = unconnected_errors.polygons(0.001) + return connected_output, unconnected_output +end + +# === IMPLICIT EXTRACTION === +if CONNECTIVITY_RULES + logger.info("Connectivity rules enabled, Netlist object will be generated.") + netlist +end #CONNECTIVITY_RULES + +# === LAYOUT EXTENT === +CHIP = extent.sized(0.0) + +logger.info("Total area of the design is #{CHIP.area()} um^2.") + + + +#================================================ +#--------------------LVPWELL--------------------- +#================================================ + + +if FEOL +logger.info("FEOL section") + +# Rule LPW.1_3.3V: Min. LVPWELL Width. is 0.6µm +logger.info("Executing rule LPW.1_3.3V") +lpw1_l1 = lvpwell.width(0.6.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +lpw1_l1.output("LPW.1_3.3V", "LPW.1_3.3V : Min. LVPWELL Width. : 0.6µm") +lpw1_l1.forget + +# Rule LPW.1_5V: Min. LVPWELL Width. is 0.74µm +logger.info("Executing rule LPW.1_5V") +lpw1_l1 = lvpwell.width(0.74.um, euclidian).polygons(0.001).overlapping(dualgate) +lpw1_l1.output("LPW.1_5V", "LPW.1_5V : Min. LVPWELL Width. : 0.74µm") +lpw1_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_lvpwell_3p3v, unconnected_lvpwell_3p3v = conn_space(lvpwell, 0.86, 1.4, euclidian) + +connected_lvpwell_5p0v, unconnected_lvpwell_5p0v = conn_space(lvpwell, 0.86, 1.7, euclidian) + +# Rule LPW.2a_3.3V: Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. is 1.4µm +logger.info("Executing rule LPW.2a_3.3V") +lpw2a_l1 = unconnected_lvpwell_3p3v.not_interacting(v5_xtor).not_interacting(dualgate) +lpw2a_l1.output("LPW.2a_3.3V", "LPW.2a_3.3V : Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. : 1.4µm") +lpw2a_l1.forget + +# Rule LPW.2a_5V: Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. is 1.7µm +logger.info("Executing rule LPW.2a_5V") +lpw2a_l1 = unconnected_lvpwell_5p0v.overlapping(dualgate) +lpw2a_l1.output("LPW.2a_5V", "LPW.2a_5V : Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. : 1.7µm") +lpw2a_l1.forget + +# Rule LPW.2b_3.3V: Min. LVPWELL to LVPWELL Space [Equi potential]. is 0.86µm +logger.info("Executing rule LPW.2b_3.3V") +lpw2b_l1 = connected_lvpwell_3p3v.not_interacting(v5_xtor).not_interacting(dualgate) +lpw2b_l1.output("LPW.2b_3.3V", "LPW.2b_3.3V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm") +lpw2b_l1.forget + +# Rule LPW.2b_5V: Min. LVPWELL to LVPWELL Space [Equi potential]. is 0.86µm +logger.info("Executing rule LPW.2b_5V") +lpw2b_l1 = connected_lvpwell_5p0v.overlapping(dualgate) +lpw2b_l1.output("LPW.2b_5V", "LPW.2b_5V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm") +lpw2b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule LPW.2a_3.3V_: Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. is 1.4µm +logger.info("Executing rule LPW.2a_3.3V_") +lpw2a_l1 = lvpwell.isolated(1.4.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +lpw2a_l1.output("LPW.2a_3.3V_", "LPW.2a_3.3V_ : Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. : 1.4µm") +lpw2a_l1.forget + +# Rule LPW.2a_5V_: Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. is 1.7µm +logger.info("Executing rule LPW.2a_5V_") +lpw2a_l1 = lvpwell.isolated(1.7.um, euclidian).polygons(0.001).overlapping(dualgate) +lpw2a_l1.output("LPW.2a_5V_", "LPW.2a_5V_ : Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. : 1.7µm") +lpw2a_l1.forget + +end #CONNECTIVITY_RULES + +# Rule LPW.3_3.3V: Min. DNWELL enclose LVPWELL. is 2.5µm +logger.info("Executing rule LPW.3_3.3V") +lpw3_l1 = dnwell.enclosing(lvpwell, 2.5.um, euclidian).polygons(0.001) +lpw3_l2 = lvpwell.not_outside(dnwell).not(dnwell) +lpw3_l = lpw3_l1.or(lpw3_l2).not_interacting(v5_xtor).not_interacting(dualgate) +lpw3_l.output("LPW.3_3.3V", "LPW.3_3.3V : Min. DNWELL enclose LVPWELL. : 2.5µm") +lpw3_l1.forget +lpw3_l2.forget +lpw3_l.forget + +# Rule LPW.3_5V: Min. DNWELL enclose LVPWELL. is 2.5µm +logger.info("Executing rule LPW.3_5V") +lpw3_l1 = dnwell.enclosing(lvpwell, 2.5.um, euclidian).polygons(0.001) +lpw3_l2 = lvpwell.not_outside(dnwell).not(dnwell) +lpw3_l = lpw3_l1.or(lpw3_l2).overlapping(dualgate) +lpw3_l.output("LPW.3_5V", "LPW.3_5V : Min. DNWELL enclose LVPWELL. : 2.5µm") +lpw3_l1.forget +lpw3_l2.forget +lpw3_l.forget + +# rule LPW.4_3.3V is not a DRC check + +# rule LPW.4_5V is not a DRC check + +# Rule LPW.5_3.3V: LVPWELL resistors must be enclosed by DNWELL. +logger.info("Executing rule LPW.5_3.3V") +lpw5_l1 = lvpwell.inside(res_mk).not_inside(dnwell).not_interacting(v5_xtor).not_interacting(dualgate) +lpw5_l1.output("LPW.5_3.3V", "LPW.5_3.3V : LVPWELL resistors must be enclosed by DNWELL.") +lpw5_l1.forget + +# Rule LPW.5_5V: LVPWELL resistors must be enclosed by DNWELL. +logger.info("Executing rule LPW.5_5V") +lpw5_l1 = lvpwell.inside(res_mk).not_inside(dnwell).overlapping(dualgate) +lpw5_l1.output("LPW.5_5V", "LPW.5_5V : LVPWELL resistors must be enclosed by DNWELL.") +lpw5_l1.forget + +# Rule LPW.11: Min. (LVPWELL outside DNWELL) space to DNWELL. is 1.5µm +logger.info("Executing rule LPW.11") +lpw11_l1 = lvpwell.outside(dnwell).separation(dnwell, 1.5.um, euclidian).polygons(0.001) +lpw11_l1.output("LPW.11", "LPW.11 : Min. (LVPWELL outside DNWELL) space to DNWELL. : 1.5µm") +lpw11_l1.forget + +# Rule LPW.12: LVPWELL cannot overlap with Nwell. +logger.info("Executing rule LPW.12") +lpw12_l1 = lvpwell.not_outside(nwell) +lpw12_l1.output("LPW.12", "LPW.12 : LVPWELL cannot overlap with Nwell.") +lpw12_l1.forget + + +end #FEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/lvs_bjt.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/lvs_bjt.drc new file mode 100644 index 000000000..007c667ae --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/lvs_bjt.drc @@ -0,0 +1,228 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (LVS_BJT) ----------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +lvs_bjt = polygons(118, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#--------------------LVS_BJT--------------------- +#================================================ + +vnpn_e = ncomp.interacting(lvs_bjt).inside(dnwell) +vpnp_e = pcomp.inside(nwell).interacting(lvs_bjt) +# Rule LVS_BJT.1: Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers +logger.info("Executing rule LVS_BJT.1") +lvs_l1 = vnpn_e.or(vpnp_e).not_inside(lvs_bjt) +lvs_l1.output("LVS_BJT.1", "LVS_BJT.1 : Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers") +lvs_l1.forget + +vnpn_e.forget +vpnp_e.forget + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/mcell.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/mcell.drc new file mode 100644 index 000000000..4c4cf4de6 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/mcell.drc @@ -0,0 +1,238 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (MCELL) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +mcell_feol_mk = polygons(11 , 17) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#---------------------MCELL---------------------- +#================================================ + +# Rule MC.1: min. mcell width is 0.4µm +logger.info("Executing rule MC.1") +mc1_l1 = mcell_feol_mk.width(0.4.um, euclidian).polygons(0.001) +mc1_l1.output("MC.1", "MC.1 : min. mcell width : 0.4µm") +mc1_l1.forget + +# Rule MC.2: min. mcell spacing is 0.4µm +logger.info("Executing rule MC.2") +mc2_l1 = mcell_feol_mk.space(0.4.um, euclidian).polygons(0.001) +mc2_l1.output("MC.2", "MC.2 : min. mcell spacing : 0.4µm") +mc2_l1.forget + +# Rule MC.3: Minimum Mcell area is 0.35µm² +logger.info("Executing rule MC.3") +mc3_l1 = mcell_feol_mk.with_area(nil, 0.35.um) +mc3_l1.output("MC.3", "MC.3 : Minimum Mcell area : 0.35µm²") +mc3_l1.forget +# Rule MC.4: Minimum area enclosed by Mcell is 0.35µm² +logger.info("Executing rule MC.4") +mc4_l1 = mcell_feol_mk.holes.with_area(nil, 0.35.um) +mc4_l1.output("MC.4", "MC.4 : Minimum area enclosed by Mcell : 0.35µm²") +mc4_l1.forget + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal1.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal1.drc new file mode 100644 index 000000000..eb1489eca --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal1.drc @@ -0,0 +1,247 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (METAL1) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +metal1 = polygons(34 , 0 ) +sramcore = polygons(108, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#---------------------METAL1--------------------- +#================================================ + + +if BEOL +logger.info("BEOL section") + +# Rule M1.1: min. metal1 width is 0.23µm +logger.info("Executing rule M1.1") +m11_l1 = metal1.not(sramcore).width(0.23.um, euclidian).polygons(0.001) +m11_l1.output("M1.1", "M1.1 : min. metal1 width : 0.23µm") +m11_l1.forget + +# Rule M1.2a: min. metal1 spacing is 0.23µm +logger.info("Executing rule M1.2a") +m12a_l1 = metal1.space(0.23.um, euclidian).polygons(0.001) +m12a_l1.output("M1.2a", "M1.2a : min. metal1 spacing : 0.23µm") +m12a_l1.forget + +# Rule M1.2b: Space to wide Metal1 (length & width > 10um) is 0.3µm +logger.info("Executing rule M1.2b") +m12b_l1 = metal1.separation(metal1.not_interacting(metal1.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) +m12b_l1.output("M1.2b", "M1.2b : Space to wide Metal1 (length & width > 10um) : 0.3µm") +m12b_l1.forget + +# Rule M1.3: Minimum Metal1 area is 0.1444µm² +logger.info("Executing rule M1.3") +m13_l1 = metal1.with_area(nil, 0.1444.um) +m13_l1.output("M1.3", "M1.3 : Minimum Metal1 area : 0.1444µm²") +m13_l1.forget + +end #BEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal2.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal2.drc new file mode 100644 index 000000000..621d7061d --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal2.drc @@ -0,0 +1,246 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (METAL2) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +metal2 = polygons(36 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#---------------------METAL2--------------------- +#================================================ + + +if BEOL +logger.info("BEOL section") + +# Rule M2.1: min. metal2 width is 0.28µm +logger.info("Executing rule M2.1") +m21_l1 = metal2.width(0.28.um, euclidian).polygons(0.001) +m21_l1.output("M2.1", "M2.1 : min. metal2 width : 0.28µm") +m21_l1.forget + +# Rule M2.2a: min. metal2 spacing is 0.28µm +logger.info("Executing rule M2.2a") +m22a_l1 = metal2.space(0.28.um, euclidian).polygons(0.001) +m22a_l1.output("M2.2a", "M2.2a : min. metal2 spacing : 0.28µm") +m22a_l1.forget + +# Rule M2.2b: Space to wide Metal2 (length & width > 10um) is 0.3µm +logger.info("Executing rule M2.2b") +m22b_l1 = metal2.separation(metal2.not_interacting(metal2.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) +m22b_l1.output("M2.2b", "M2.2b : Space to wide Metal2 (length & width > 10um) : 0.3µm") +m22b_l1.forget + +# Rule M2.3: Minimum metal2 area is 0.1444µm² +logger.info("Executing rule M2.3") +m23_l1 = metal2.with_area(nil, 0.1444.um) +m23_l1.output("M2.3", "M2.3 : Minimum metal2 area : 0.1444µm²") +m23_l1.forget + +end #BEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal3.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal3.drc new file mode 100644 index 000000000..7f58aee0d --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal3.drc @@ -0,0 +1,246 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (METAL3) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +metal3 = polygons(42 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#---------------------METAL3--------------------- +#================================================ + + +if BEOL +logger.info("BEOL section") + +# Rule M3.1: min. metal3 width is 0.28µm +logger.info("Executing rule M3.1") +m31_l1 = metal3.width(0.28.um, euclidian).polygons(0.001) +m31_l1.output("M3.1", "M3.1 : min. metal3 width : 0.28µm") +m31_l1.forget + +# Rule M3.2a: min. metal3 spacing is 0.28µm +logger.info("Executing rule M3.2a") +m32a_l1 = metal3.space(0.28.um, euclidian).polygons(0.001) +m32a_l1.output("M3.2a", "M3.2a : min. metal3 spacing : 0.28µm") +m32a_l1.forget + +# Rule M3.2b: Space to wide Metal3 (length & width > 10um) is 0.3µm +logger.info("Executing rule M3.2b") +m32b_l1 = metal3.separation(metal3.not_interacting(metal3.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) +m32b_l1.output("M3.2b", "M3.2b : Space to wide Metal3 (length & width > 10um) : 0.3µm") +m32b_l1.forget + +# Rule M3.3: Minimum metal3 area is 0.1444µm² +logger.info("Executing rule M3.3") +m33_l1 = metal3.with_area(nil, 0.1444.um) +m33_l1.output("M3.3", "M3.3 : Minimum metal3 area : 0.1444µm²") +m33_l1.forget + +end #BEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal4.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal4.drc new file mode 100644 index 000000000..a267756c6 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal4.drc @@ -0,0 +1,246 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (METAL4) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +metal4 = polygons(46 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#---------------------METAL4--------------------- +#================================================ + + +if BEOL +logger.info("BEOL section") + +# Rule M4.1: min. metal4 width is 0.28µm +logger.info("Executing rule M4.1") +m41_l1 = metal4.width(0.28.um, euclidian).polygons(0.001) +m41_l1.output("M4.1", "M4.1 : min. metal4 width : 0.28µm") +m41_l1.forget + +# Rule M4.2a: min. metal4 spacing is 0.28µm +logger.info("Executing rule M4.2a") +m42a_l1 = metal4.space(0.28.um, euclidian).polygons(0.001) +m42a_l1.output("M4.2a", "M4.2a : min. metal4 spacing : 0.28µm") +m42a_l1.forget + +# Rule M4.2b: Space to wide Metal4 (length & width > 10um) is 0.3µm +logger.info("Executing rule M4.2b") +m42b_l1 = metal4.separation(metal4.not_interacting(metal4.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) +m42b_l1.output("M4.2b", "M4.2b : Space to wide Metal4 (length & width > 10um) : 0.3µm") +m42b_l1.forget + +# Rule M4.3: Minimum metal4 area is 0.1444µm² +logger.info("Executing rule M4.3") +m43_l1 = metal4.with_area(nil, 0.1444.um) +m43_l1.output("M4.3", "M4.3 : Minimum metal4 area : 0.1444µm²") +m43_l1.forget + +end #BEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal5.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal5.drc new file mode 100644 index 000000000..e6b950209 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metal5.drc @@ -0,0 +1,246 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (METAL5) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +metal5 = polygons(81 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#---------------------METAL5--------------------- +#================================================ + + +if BEOL +logger.info("BEOL section") + +# Rule M5.1: min. metal5 width is 0.28µm +logger.info("Executing rule M5.1") +m51_l1 = metal5.width(0.28.um, euclidian).polygons(0.001) +m51_l1.output("M5.1", "M5.1 : min. metal5 width : 0.28µm") +m51_l1.forget + +# Rule M5.2a: min. metal5 spacing is 0.28µm +logger.info("Executing rule M5.2a") +m52a_l1 = metal5.space(0.28.um, euclidian).polygons(0.001) +m52a_l1.output("M5.2a", "M5.2a : min. metal5 spacing : 0.28µm") +m52a_l1.forget + +# Rule M5.2b: Space to wide Metal5 (length & width > 10um) is 0.3µm +logger.info("Executing rule M5.2b") +m52b_l1 = metal5.separation(metal5.not_interacting(metal5.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) +m52b_l1.output("M5.2b", "M5.2b : Space to wide Metal5 (length & width > 10um) : 0.3µm") +m52b_l1.forget + +# Rule M5.3: Minimum metal5 area is 0.1444µm² +logger.info("Executing rule M5.3") +m53_l1 = metal5.with_area(nil, 0.1444.um) +m53_l1.output("M5.3", "M5.3 : Minimum metal5 area : 0.1444µm²") +m53_l1.forget + +end #BEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metaltop.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metaltop.drc new file mode 100644 index 000000000..625c58047 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/metaltop.drc @@ -0,0 +1,381 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#---------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (METALTOP) ----------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +metaltop = polygons(53 , 0 ) +fusetop = polygons(75 , 0 ) +guard_ring_mk = polygons(167, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#------------- METAL LEVEL SWITCHES ------------- +#================================================ + + +if METAL_LEVEL == "6LM" + via4 = polygons(41 , 0 ) + metal5 = polygons(81 , 0 ) + via5 = polygons(82 , 0 ) + metaltop = polygons(53 , 0 ) + top_via = via5 + topmin1_via = via4 + top_metal = metaltop + topmin1_metal = metal5 +elsif METAL_LEVEL == "5LM" + via3 = polygons(40 , 0 ) + metal4 = polygons(46 , 0 ) + via4 = polygons(41 , 0 ) + metal5 = polygons(81 , 0 ) + top_via = via4 + topmin1_via = via3 + top_metal = metal5 + topmin1_metal = metal4 +elsif METAL_LEVEL == "4LM" + via2 = polygons(38 , 0 ) + metal3 = polygons(42 , 0 ) + via3 = polygons(40 , 0 ) + metal4 = polygons(46 , 0 ) + top_via = via3 + topmin1_via = via2 + top_metal = metal4 + topmin1_metal = metal3 +elsif METAL_LEVEL == "3LM" + via1 = polygons(35 , 0 ) + metal2 = polygons(36 , 0 ) + via2 = polygons(38 , 0 ) + metal3 = polygons(42 , 0 ) + top_via = via2 + topmin1_via = via1 + top_metal = metal3 + topmin1_metal = metal2 +elsif METAL_LEVEL == "2LM" + metal1 = polygons(34 , 0 ) + via1 = polygons(35 , 0 ) + metal2 = polygons(36 , 0 ) + top_via = via1 + topmin1_via = via1 + top_metal = metal2 + topmin1_metal = metal1 +end #METAL_LEVEL + + +#================================================ +#--------------------METALTOP-------------------- +#================================================ + + +if BEOL +logger.info("BEOL section") + +if METAL_TOP == "6K" +logger.info("MetalTop thickness 6k section") + +# Rule MT.1: min. metaltop width is 0.36µm +logger.info("Executing rule MT.1") +mt1_l1 = metaltop.width(0.36.um, euclidian).polygons(0.001) +mt1_l1.output("MT.1", "MT.1 : min. metaltop width : 0.36µm") +mt1_l1.forget + +# Rule MT.2a: min. metaltop spacing is 0.38µm +logger.info("Executing rule MT.2a") +mt2a_l1 = metaltop.space(0.38.um, euclidian).polygons(0.001) +mt2a_l1.output("MT.2a", "MT.2a : min. metaltop spacing : 0.38µm") +mt2a_l1.forget + +# Rule MT.4: Minimum MetalTop area is 0.5625µm² +logger.info("Executing rule MT.4") +mt4_l1 = metaltop.with_area(nil, 0.5625.um) +mt4_l1.output("MT.4", "MT.4 : Minimum MetalTop area : 0.5625µm²") +mt4_l1.forget +elsif METAL_TOP == "9K" +logger.info("MetalTop thickness 9k/11k section") + +# Rule MT.1: min. metaltop width is 0.44µm +logger.info("Executing rule MT.1") +mt1_l1 = metaltop.width(0.44.um, euclidian).polygons(0.001) +mt1_l1.output("MT.1", "MT.1 : min. metaltop width : 0.44µm") +mt1_l1.forget + +# Rule MT.2a: min. metaltop spacing is 0.46µm +logger.info("Executing rule MT.2a") +mt2a_l1 = metaltop.space(0.46.um, euclidian).polygons(0.001) +mt2a_l1.output("MT.2a", "MT.2a : min. metaltop spacing : 0.46µm") +mt2a_l1.forget + +# Rule MT.4: Minimum MetalTop area is 0.5625µm² +logger.info("Executing rule MT.4") +mt4_l1 = metaltop.with_area(nil, 0.5625.um) +mt4_l1.output("MT.4", "MT.4 : Minimum MetalTop area : 0.5625µm²") +mt4_l1.forget +elsif METAL_TOP == "30K" +logger.info("MetalTop thickness 30K section") + +# Rule MT30.1a: Min. thick MetalTop width. is 1.8µm +logger.info("Executing rule MT30.1a") +mt301a_l1 = metaltop.width(1.8.um, euclidian).polygons(0.001) +mt301a_l1.output("MT30.1a", "MT30.1a : Min. thick MetalTop width. : 1.8µm") +mt301a_l1.forget + +# Rule MT30.1b: Min width for >1000um long metal line (based on metal edge). is 2.2µm +logger.info("Executing rule MT30.1b") +mt301b_l1 = metaltop.interacting(metaltop.edges.with_length(1000.um, nil)).width(2.2.um, euclidian).polygons(0.001) +mt301b_l1.output("MT30.1b", "MT30.1b : Min width for >1000um long metal line (based on metal edge). : 2.2µm") +mt301b_l1.forget + +# Rule MT30.2: Min. thick MetalTop space. is 1.8µm +logger.info("Executing rule MT30.2") +mt302_l1 = metaltop.space(1.8.um, euclidian).polygons(0.001) +mt302_l1.output("MT30.2", "MT30.2 : Min. thick MetalTop space. : 1.8µm") +mt302_l1.forget + +# Rule MT30.3: The separation of two corners should satisfy the minimum spacing. is 1.8µm +logger.info("Executing rule MT30.3") +mt303_l1 = metaltop.space(1.8.um, euclidian).polygons(0.001) +mt303_l1.output("MT30.3", "MT30.3 : The separation of two corners should satisfy the minimum spacing. : 1.8µm") +mt303_l1.forget + +# Rule MT30.4: The separation of single metal line from a any degree metal line should satisfy the minimum spacing. is 1.8µm +logger.info("Executing rule MT30.4") +mt304_l1 = metaltop.space(1.8.um, euclidian).polygons(0.001) +mt304_l1.output("MT30.4", "MT30.4 : The separation of single metal line from a any degree metal line should satisfy the minimum spacing. : 1.8µm") +mt304_l1.forget + +# Rule MT30.5: Minimum thick MetalTop enclose underlying via (for example: via5 for 6LM case) [Outside Not Allowed]. +logger.info("Executing rule MT30.5") +mt305_l1 = top_metal.enclosing(top_via, 0.12.um, euclidian).polygons(0.001).or(top_via.not_inside(top_metal)) +mt305_l1.output("MT30.5", "MT30.5 : Minimum thick MetalTop enclose underlying via (for example: via5 for 6LM case) [Outside Not Allowed].") +mt305_l1.forget + +mt30p6_cond = top_metal.drc( width <= 0.34.um) +mt30p6_eol = top_metal.edges.with_length(nil, 0.34.um).interacting(mt30p6_cond.first_edges).interacting(mt30p6_cond.second_edges).not(mt30p6_cond.first_edges).not(mt30p6_cond.second_edges) +# Rule MT30.6: Thick MetalTop end-of-line (width <2.5um) enclose underlying via (for example: via5 for 6LM case) [Outside Not Allowed]. +logger.info("Executing rule MT30.6") +mt306_l1 = mt30p6_eol.enclosing(top_via.edges,0.25.um, projection).polygons(0.001).or(top_via.not_inside(top_metal)) +mt306_l1.output("MT30.6", "MT30.6 : Thick MetalTop end-of-line (width <2.5um) enclose underlying via (for example: via5 for 6LM case) [Outside Not Allowed].") +mt306_l1.forget + +mt30p6_cond.forget +mt30p6_eol.forget +mt30p8_via_no_mim = top_via.sized(0.18.um).sized(-0.18.um).with_bbox_min(0.78.um , nil).extents.inside(top_metal) +mt30p8_via_mim = top_via.interacting(fusetop).sized(0.3.um).sized(-0.3.um).with_bbox_min(1.02.um , nil).extents.inside(top_metal) +mt30p8_via = mt30p8_via_no_mim.or(mt30p8_via_mim) +mt30p8_mask = mt30p8_via.size(1).not(top_via).with_holes(4, nil) +mt30p8_slct_via = top_via.interacting(mt30p8_mask) +# Rule MT30.8: There shall be minimum 2X2 array of vias (top vias) at one location connecting to 3um thick top metal. +logger.info("Executing rule MT30.8") +mt308_l1 = topmin1_metal.outside(guard_ring_mk).not_interacting(mt30p8_slct_via) +mt308_l1.output("MT30.8", "MT30.8 : There shall be minimum 2X2 array of vias (top vias) at one location connecting to 3um thick top metal.") +mt308_l1.forget + +mt30p8_via.forget +mt30p8_mask.forget +mt30p8_slct_via.forget +end #METAL_TOP + +end #BEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/mim_capacitor_option_a_.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/mim_capacitor_option_a_.drc new file mode 100644 index 000000000..1797bcd27 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/mim_capacitor_option_a_.drc @@ -0,0 +1,327 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#--------------------------------------------------- GF 0.18um MCU DRC RULE DECK (MIM CAPACITOR OPTION A ) --------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +via1 = polygons(35 , 0 ) +metal2 = polygons(36 , 0 ) +via2 = polygons(38 , 0 ) +fusetop = polygons(75 , 0 ) +cap_mk = polygons(117, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#------------MIM CAPACITOR OPTION A ------------- +#================================================ + +if MIM_OPTION == "A" +logger.info("MIM Capacitor Option A section") + +mim_virtual = fusetop.sized(1.06.um).and(metal2.interacting(fusetop)) +# Rule MIM.1: Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). is 1.2µm +logger.info("Executing rule MIM.1") +mim1_l1 = metal2.separation(mim_virtual ,transparent, 1.2.um).polygons(0.001) +mim1_l1.output("MIM.1", "MIM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm") +mim1_l1.forget + +# Rule MIM.2: Minimum MiM bottom plate overlap of Via2 layer. [This is applicable for via2 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. is 0.4µm +logger.info("Executing rule MIM.2") +mim2_l1 = metal2.enclosing(via2.overlapping(mim_virtual), 0.4.um, euclidian).polygons(0.001) +mim2_l2 = via2.overlapping(mim_virtual).not_outside(metal2).not(metal2) +mim2_l = mim2_l1.or(mim2_l2) +mim2_l.output("MIM.2", "MIM.2 : Minimum MiM bottom plate overlap of Via2 layer. [This is applicable for via2 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm") +mim2_l1.forget +mim2_l2.forget +mim2_l.forget + +# Rule MIM.3: Minimum MiM bottom plate overlap of Top plate. +logger.info("Executing rule MIM.3") +mim3_l1 = mim_virtual.enclosing(fusetop,0.6.um).polygons(0.001).or(fusetop.not_inside(mim_virtual)) +mim3_l1.output("MIM.3", "MIM.3 : Minimum MiM bottom plate overlap of Top plate.") +mim3_l1.forget + +mim_virtual.forget +# Rule MIM.4: Minimum MiM top plate (FuseTop) overlap of Via2. is 0.4µm +logger.info("Executing rule MIM.4") +mim4_l1 = fusetop.enclosing(via2, 0.4.um, euclidian).polygons(0.001) +mim4_l2 = via2.not_outside(fusetop).not(fusetop) +mim4_l = mim4_l1.or(mim4_l2) +mim4_l.output("MIM.4", "MIM.4 : Minimum MiM top plate (FuseTop) overlap of Via2. : 0.4µm") +mim4_l1.forget +mim4_l2.forget +mim4_l.forget + +# Rule MIM.5: Minimum spacing between top plate and the Via2 connecting to the bottom plate. is 0.4µm +logger.info("Executing rule MIM.5") +mim5_l1 = fusetop.separation(via2.interacting(metal2), 0.4.um, euclidian).polygons(0.001) +mim5_l1.output("MIM.5", "MIM.5 : Minimum spacing between top plate and the Via2 connecting to the bottom plate. : 0.4µm") +mim5_l1.forget + +# Rule MIM.6: Minimum spacing between unrelated top plates. is 0.6µm +logger.info("Executing rule MIM.6") +mim6_l1 = fusetop.space(0.6.um, euclidian).polygons(0.001) +mim6_l1.output("MIM.6", "MIM.6 : Minimum spacing between unrelated top plates. : 0.6µm") +mim6_l1.forget + +# Rule MIM.7: Min FuseTop enclosure by CAP_MK. +logger.info("Executing rule MIM.7") +mim7_l1 = fusetop.not_inside(cap_mk) +mim7_l1.output("MIM.7", "MIM.7 : Min FuseTop enclosure by CAP_MK.") +mim7_l1.forget + +# Rule MIM.8a: Minimum MIM cap area (defined by FuseTop area) (um2). is 25µm² +logger.info("Executing rule MIM.8a") +mim8a_l1 = fusetop.with_area(nil, 25.um) +mim8a_l1.output("MIM.8a", "MIM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²") +mim8a_l1.forget +# Rule MIM.8b: Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). is 10000µm +logger.info("Executing rule MIM.8b") +mim8b_l1 = fusetop.with_area(10000.um,nil).not_in(fusetop.with_area(10000.um)) +mim8b_l1.output("MIM.8b", "MIM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm") +mim8b_l1.forget + +# Rule MIM.9: Min. via spacing for sea of via on MIM top plate. is 0.5µm +logger.info("Executing rule MIM.9") +mim9_l1 = via2.inside(fusetop).space(0.5.um, euclidian).polygons(0.001) +mim9_l1.output("MIM.9", "MIM.9 : Min. via spacing for sea of via on MIM top plate. : 0.5µm") +mim9_l1.forget + +# Rule MIM.10: (a) There cannot be any Via1 touching MIM bottom plate Metal2. (b) MIM bottom plate Metal2 can only be connected through the higher Via (Via2). +logger.info("Executing rule MIM.10") +mim10_l1 = via1.interacting(metal2.interacting(fusetop)) +mim10_l1.output("MIM.10", "MIM.10 : (a) There cannot be any Via1 touching MIM bottom plate Metal2. (b) MIM bottom plate Metal2 can only be connected through the higher Via (Via2).") +mim10_l1.forget + +mim11_large_metal2 = metal2.interacting(fusetop).with_area(10000, nil) +mim11_large_metal2_violation = polygon_layer +mim11_large_metal2.data.each do |p| + mim11_metal2_polygon_layer = polygon_layer + mim11_metal2_polygon_layer.data.insert(p) + fuse_in_polygon = fusetop.and(mim11_metal2_polygon_layer) + if(fuse_in_polygon.area > 10000) + mim11_bad_metal2_polygon = mim11_metal2_polygon_layer.interacting(fuse_in_polygon) + mim11_bad_metal2_polygon.data.each do |b| + b.num_points > 0 && mim11_large_metal2_violation.data.insert(b) + end + end +end +# Rule MIM.11: Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIM.8b rule. is -µm +logger.info("Executing rule MIM.11") +mim11_l1 = mim11_large_metal2_violation +mim11_l1.output("MIM.11", "MIM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIM.8b rule. : -µm") +mim11_l1.forget + +mim11_large_metal2.forget +mim11_large_metal2_violation.forget +# rule MIM.12 is not a DRC check + + +else +logger.info("MIM Capacitor Option A not Selected") + +end #MIM_OPTION + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/mim_capacitor_option_b.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/mim_capacitor_option_b.drc new file mode 100644 index 000000000..47c12b393 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/mim_capacitor_option_b.drc @@ -0,0 +1,375 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#--------------------------------------------------- GF 0.18um MCU DRC RULE DECK (MIM CAPACITOR OPTION B) ---------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +fusetop = polygons(75 , 0 ) +cap_mk = polygons(117, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#------------- METAL LEVEL SWITCHES ------------- +#================================================ + + +if METAL_LEVEL == "6LM" + via4 = polygons(41 , 0 ) + metal5 = polygons(81 , 0 ) + via5 = polygons(82 , 0 ) + metaltop = polygons(53 , 0 ) + top_via = via5 + topmin1_via = via4 + top_metal = metaltop + topmin1_metal = metal5 +elsif METAL_LEVEL == "5LM" + via3 = polygons(40 , 0 ) + metal4 = polygons(46 , 0 ) + via4 = polygons(41 , 0 ) + metal5 = polygons(81 , 0 ) + top_via = via4 + topmin1_via = via3 + top_metal = metal5 + topmin1_metal = metal4 +elsif METAL_LEVEL == "4LM" + via2 = polygons(38 , 0 ) + metal3 = polygons(42 , 0 ) + via3 = polygons(40 , 0 ) + metal4 = polygons(46 , 0 ) + top_via = via3 + topmin1_via = via2 + top_metal = metal4 + topmin1_metal = metal3 +elsif METAL_LEVEL == "3LM" + via1 = polygons(35 , 0 ) + metal2 = polygons(36 , 0 ) + via2 = polygons(38 , 0 ) + metal3 = polygons(42 , 0 ) + top_via = via2 + topmin1_via = via1 + top_metal = metal3 + topmin1_metal = metal2 +elsif METAL_LEVEL == "2LM" + metal1 = polygons(34 , 0 ) + via1 = polygons(35 , 0 ) + metal2 = polygons(36 , 0 ) + top_via = via1 + topmin1_via = via1 + top_metal = metal2 + topmin1_metal = metal1 +end #METAL_LEVEL + + +#================================================ +#-------------MIM CAPACITOR OPTION B------------- +#================================================ + +if MIM_OPTION == "B" +logger.info("mim11_metal2_polygon_layer.interacting(fuse_in_polygon) section") + +mimtm_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop)) +# Rule MIMTM.1: Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). is 1.2µm +logger.info("Executing rule MIMTM.1") +mimtm1_l1 = topmin1_metal.separation(mimtm_virtual ,transparent, 1.2.um).polygons(0.001) +mimtm1_l1.output("MIMTM.1", "MIMTM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm") +mimtm1_l1.forget + +# Rule MIMTM.2: Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. is 0.4µm +logger.info("Executing rule MIMTM.2") +mimtm2_l1 = topmin1_metal.enclosing(top_via.overlapping(mimtm_virtual), 0.4.um, euclidian).polygons(0.001) +mimtm2_l2 = top_via.overlapping(mimtm_virtual).not_outside(topmin1_metal).not(topmin1_metal) +mimtm2_l = mimtm2_l1.or(mimtm2_l2) +mimtm2_l.output("MIMTM.2", "MIMTM.2 : Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm") +mimtm2_l1.forget +mimtm2_l2.forget +mimtm2_l.forget + +# Rule MIMTM.3: Minimum MiM bottom plate overlap of Top plate. +logger.info("Executing rule MIMTM.3") +mimtm3_l1 = mimtm_virtual.enclosing(fusetop,0.6.um).polygons(0.001).or(fusetop.not_inside(mimtm_virtual)) +mimtm3_l1.output("MIMTM.3", "MIMTM.3 : Minimum MiM bottom plate overlap of Top plate.") +mimtm3_l1.forget + +mimtm_virtual.forget +# Rule MIMTM.4: Minimum MiM top plate (FuseTop) overlap of Vian-1. is 0.4µm +logger.info("Executing rule MIMTM.4") +mimtm4_l1 = fusetop.enclosing(top_via, 0.4.um, euclidian).polygons(0.001) +mimtm4_l2 = top_via.not_outside(fusetop).not(fusetop) +mimtm4_l = mimtm4_l1.or(mimtm4_l2) +mimtm4_l.output("MIMTM.4", "MIMTM.4 : Minimum MiM top plate (FuseTop) overlap of Vian-1. : 0.4µm") +mimtm4_l1.forget +mimtm4_l2.forget +mimtm4_l.forget + +# Rule MIMTM.5: Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. is 0.4µm +logger.info("Executing rule MIMTM.5") +mimtm5_l1 = fusetop.separation(top_via.interacting(topmin1_metal), 0.4.um, euclidian).polygons(0.001) +mimtm5_l1.output("MIMTM.5", "MIMTM.5 : Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. : 0.4µm") +mimtm5_l1.forget + +# Rule MIMTM.6: Minimum spacing between unrelated top plates. is 0.6µm +logger.info("Executing rule MIMTM.6") +mimtm6_l1 = fusetop.space(0.6.um, euclidian).polygons(0.001) +mimtm6_l1.output("MIMTM.6", "MIMTM.6 : Minimum spacing between unrelated top plates. : 0.6µm") +mimtm6_l1.forget + +# Rule MIMTM.7: Min FuseTop enclosure by CAP_MK. +logger.info("Executing rule MIMTM.7") +mimtm7_l1 = fusetop.not_inside(cap_mk) +mimtm7_l1.output("MIMTM.7", "MIMTM.7 : Min FuseTop enclosure by CAP_MK.") +mimtm7_l1.forget + +# Rule MIMTM.8a: Minimum MIM cap area (defined by FuseTop area) (um2). is 25µm² +logger.info("Executing rule MIMTM.8a") +mimtm8a_l1 = fusetop.with_area(nil, 25.um) +mimtm8a_l1.output("MIMTM.8a", "MIMTM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²") +mimtm8a_l1.forget +# Rule MIMTM.8b: Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). is 10000µm +logger.info("Executing rule MIMTM.8b") +mimtm8b_l1 = fusetop.with_area(10000.um,nil).not_in(fusetop.with_area(10000.um)) +mimtm8b_l1.output("MIMTM.8b", "MIMTM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm") +mimtm8b_l1.forget + +# Rule MIMTM.9: Min. Via (Vian-1) spacing for sea of Via on MIM top plate. is 0.5µm +logger.info("Executing rule MIMTM.9") +mimtm9_l1 = top_via.inside(fusetop).space(0.5.um, euclidian).polygons(0.001) +mimtm9_l1.output("MIMTM.9", "MIMTM.9 : Min. Via (Vian-1) spacing for sea of Via on MIM top plate. : 0.5µm") +mimtm9_l1.forget + +# Rule MIMTM.10: (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1). +logger.info("Executing rule MIMTM.10") +mimtm10_l1 = topmin1_via.interacting(topmin1_metal.interacting(fusetop)) +mimtm10_l1.output("MIMTM.10", "MIMTM.10 : (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1).") +mimtm10_l1.forget + +mimtm11_large_topmin1_metal = topmin1_metal.interacting(fusetop).with_area(10000, nil) +mimtm11_large_topmin1_metal_violation = polygon_layer +mimtm11_large_topmin1_metal.data.each do |p| + mimtm11_topmin1_metal_polygon_layer = polygon_layer + mimtm11_topmin1_metal_polygon_layer.data.insert(p) + fuse_in_polygon = fusetop.and(mimtm11_topmin1_metal_polygon_layer) + if(fuse_in_polygon.area > 10000) + mimtm11_bad_topmin1_metal_polygon = mimtm11_topmin1_metal_polygon_layer.interacting(fuse_in_polygon) + mimtm11_bad_topmin1_metal_polygon.data.each do |b| + b.num_points > 0 && mimtm11_large_topmin1_metal_violation.data.insert(b) + end + end +end +# Rule MIMTM.11: Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. is -µm +logger.info("Executing rule MIMTM.11") +mimtm11_l1 = mimtm11_large_topmin1_metal_violation +mimtm11_l1.output("MIMTM.11", "MIMTM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. : -µm") +mimtm11_l1.forget + +mimtm11_large_topmin1_metal.forget +mimtm11_large_topmin1_metal_violation.forget +# rule MIMTM.12 is not a DRC check + +else +logger.info("MIM Capacitor Option B not Selected") + +end #MIM_OPTION + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/n+_poly_resistor.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/n+_poly_resistor.drc new file mode 100644 index 000000000..2cdb99f48 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/n+_poly_resistor.drc @@ -0,0 +1,287 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (N+ POLY RESISTOR) ------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +sab = polygons(49 , 0 ) +contact = polygons(33 , 0 ) +resistor = polygons(62 , 0 ) +res_mk = polygons(110, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#----------------N+ POLY RESISTOR---------------- +#================================================ + +lres_poly = poly2.and(nplus).interacting(sab).interacting(res_mk) +# Rule LRES.1: Minimum width of Poly2 resistor. is 0.8µm +logger.info("Executing rule LRES.1") +lres1_l1 = lres_poly.width(0.8.um, euclidian).polygons(0.001) +lres1_l1.output("LRES.1", "LRES.1 : Minimum width of Poly2 resistor. : 0.8µm") +lres1_l1.forget + +# Rule LRES.2: Minimum space between Poly2 resistors. is 0.4µm +logger.info("Executing rule LRES.2") +lres2_l1 = lres_poly.isolated(0.4.um, euclidian).polygons(0.001) +lres2_l1.output("LRES.2", "LRES.2 : Minimum space between Poly2 resistors. : 0.4µm") +lres2_l1.forget + +# Rule LRES.3: Minimum space from Poly2 resistor to COMP. +logger.info("Executing rule LRES.3") +lres3_l1 = lres_poly.separation(comp, 0.6.um, euclidian).polygons(0.001).or(comp.not_outside(lres_poly)) +lres3_l1.output("LRES.3", "LRES.3 : Minimum space from Poly2 resistor to COMP.") +lres3_l1.forget + +# Rule LRES.4: Minimum space from Poly2 resistor to unrelated Poly2. is 0.6µm +logger.info("Executing rule LRES.4") +lres4_l1 = lres_poly.separation(poly2.not_interacting(sab), 0.6.um, euclidian).polygons(0.001) +lres4_l1.output("LRES.4", "LRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm") +lres4_l1.forget + +# Rule LRES.5: Minimum Nplus implant overlap of Poly2 resistor. is 0.3µm +logger.info("Executing rule LRES.5") +lres5_l1 = nplus.enclosing(poly2.and(nplus).interacting(sab).interacting(res_mk), 0.3.um, euclidian).polygons(0.001) +lres5_l2 = poly2.and(nplus).interacting(sab).interacting(res_mk).not_outside(nplus).not(nplus) +lres5_l = lres5_l1.or(lres5_l2) +lres5_l.output("LRES.5", "LRES.5 : Minimum Nplus implant overlap of Poly2 resistor. : 0.3µm") +lres5_l1.forget +lres5_l2.forget +lres5_l.forget + +# Rule LRES.6: Minimum salicide block overlap of Poly2 resistor in width direction. is 0.28µm +logger.info("Executing rule LRES.6") +lres6_l1 = sab.enclosing(lres_poly,0.28.um).polygons(0.001) +lres6_l1.output("LRES.6", "LRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm") +lres6_l1.forget + +cont_lres7 = contact.inside(poly2.and(nplus).interacting(sab).interacting(res_mk)) +# Rule LRES.7: Space from salicide block to contact on Poly2 resistor. +logger.info("Executing rule LRES.7") +lres7_l1 = cont_lres7.separation(sab,0.22.um).polygons(0.001).or(cont_lres7.interacting(sab)) +lres7_l1.output("LRES.7", "LRES.7 : Space from salicide block to contact on Poly2 resistor.") +lres7_l1.forget + +cont_lres7.forget +# rule LRES.8 is not a DRC check + +mk_lres9 = res_mk.edges.not(poly2.and(nplus).and(sab).edges).inside_part(poly2) +# Rule LRES.9a: Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. +logger.info("Executing rule LRES.9a") +lres9a_l1 = res_mk.interacting(lres_poly).interacting(mk_lres9) +lres9a_l1.output("LRES.9a", "LRES.9a : Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. ") +lres9a_l1.forget + +mk_lres9.forget +lres9b = res_mk.with_area(15000.01.um,nil).in(res_mk.interacting(res_mk.edges.with_length(80.01.um,nil))) +# Rule LRES.9b: If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. is 20µm +logger.info("Executing rule LRES.9b") +lres9b_l1 = res_mk.interacting(lres_poly).drc(separation(lres9b) < 20.um).polygons(0.001) +lres9b_l1.output("LRES.9b", "LRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm") +lres9b_l1.forget + +lres9b.forget +lres_poly.forget + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/native_vt_nmos.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/native_vt_nmos.drc new file mode 100644 index 000000000..c8215fd8b --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/native_vt_nmos.drc @@ -0,0 +1,309 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (NATIVE VT NMOS) -------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +nwell = polygons(21 , 0 ) +nat = polygons(5 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) +natcompsd = (nat & comp.interacting(poly2)) - tgate + +if CONNECTIVITY_RULES + logger.info("Construct connectivity for NAT layer.") + connect(natcompsd, contact) +end #CONNECTIVITY_RULES + + + +#================================================ +#-----------------NATIVE VT NMOS----------------- +#================================================ + +# Rule NAT.1: Min. NAT Overlap of COMP of Native Vt NMOS. is 2µm +logger.info("Executing rule NAT.1") +nat1_l1 = nat.enclosing(ncomp.outside(nwell).interacting(nat), 2.um, euclidian).polygons(0.001) +nat1_l1.output("NAT.1", "NAT.1 : Min. NAT Overlap of COMP of Native Vt NMOS. : 2µm") +nat1_l1.forget + +# Rule NAT.2: Space to unrelated COMP (outside NAT). is 0.3µm +logger.info("Executing rule NAT.2") +nat2_l1 = nat.separation(comp.outside(nat), 0.3.um, euclidian).polygons(0.001) +nat2_l1.output("NAT.2", "NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm") +nat2_l1.forget + +# Rule NAT.3: Space to NWell edge. is 0.5µm +logger.info("Executing rule NAT.3") +nat3_l1 = nat.separation(nwell, 0.5.um, euclidian).polygons(0.001) +nat3_l1.output("NAT.3", "NAT.3 : Space to NWell edge. : 0.5µm") +nat3_l1.forget + +# Rule NAT.4: Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). is 1.8µm +logger.info("Executing rule NAT.4") +nat4_l1 = poly2.edges.and(ngate.edges).not(nwell).interacting(nat).width(1.8.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +nat4_l1.output("NAT.4", "NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm") +nat4_l1.forget + +# Rule NAT.5: Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). is 1.8µm +logger.info("Executing rule NAT.5") +nat5_l1 = poly2.edges.and(ngate.edges).not(nwell).interacting(nat).width(1.8.um, euclidian).polygons(0.001).overlapping(dualgate) +nat5_l1.output("NAT.5", "NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm") +nat5_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_nat, unconnected_nat = conn_space(natcompsd, 10, 10, transparent) + +# Rule NAT.6: Two or more COMPs if connected to different potential are not allowed under same NAT layer. +logger.info("Executing rule NAT.6") +nat6_l1 = comp.and(nat).interacting(unconnected_nat.inside(nat.covering(comp, 2)).not(poly2)) +nat6_l1.output("NAT.6", "NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer.") +nat6_l1.forget + +end #CONNECTIVITY_RULES + +natcompsd.forget +# Rule NAT.7: Minimum NAT to NAT spacing. is 0.74µm +logger.info("Executing rule NAT.7") +nat7_l1 = nat.space(0.74.um, euclidian).polygons(0.001) +nat7_l1.output("NAT.7", "NAT.7 : Minimum NAT to NAT spacing. : 0.74µm") +nat7_l1.forget + +# Rule NAT.8: Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only. +logger.info("Executing rule NAT.8") +nat8_l1 = nat.not_outside(dualgate).not(dualgate) +nat8_l1.output("NAT.8", "NAT.8 : Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only.") +nat8_l1.forget + +nat9_1 = poly2.and(nat).not(ncomp).interacting(ngate.and(nat) , 2) +nat9_2 = poly2.not(nat).separation(nat, 0.3.um, euclidian).polygons(0.001) +# Rule NAT.9: Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer. +logger.info("Executing rule NAT.9") +nat9_l1 = nat9_1.or(nat9_2) +nat9_l1.output("NAT.9", "NAT.9 : Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer.") +nat9_l1.forget + +nat9_1.forget +nat9_2.forget +# Rule NAT.10: Nwell, inside NAT layer are not allowed. +logger.info("Executing rule NAT.10") +nat10_l1 = nwell.inside(nat) +nat10_l1.output("NAT.10", "NAT.10 : Nwell, inside NAT layer are not allowed.") +nat10_l1.forget + +# Rule NAT.11: NCOMP not intersecting to Poly2, is not allowed inside NAT layer. +logger.info("Executing rule NAT.11") +nat11_l1 = ncomp.and(nat).outside(poly2) +nat11_l1.output("NAT.11", "NAT.11 : NCOMP not intersecting to Poly2, is not allowed inside NAT layer.") +nat11_l1.forget + +# Rule NAT.12: Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT). +logger.info("Executing rule NAT.12") +nat12_l1 = poly2.interacting(nat).not_interacting(comp.and(nat)) +nat12_l1.output("NAT.12", "NAT.12 : Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT).") +nat12_l1.forget + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/nplus.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/nplus.drc new file mode 100644 index 000000000..c9e113659 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/nplus.drc @@ -0,0 +1,420 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (NPLUS) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +lvpwell = polygons(204, 0 ) +sab = polygons(49 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#---------------------NPLUS---------------------- +#================================================ + + +if FEOL +logger.info("FEOL section") + +# Rule NP.1: min. nplus width is 0.4µm +logger.info("Executing rule NP.1") +np1_l1 = nplus.width(0.4.um, euclidian).polygons(0.001) +np1_l1.output("NP.1", "NP.1 : min. nplus width : 0.4µm") +np1_l1.forget + +# Rule NP.2: min. nplus spacing is 0.4µm +logger.info("Executing rule NP.2") +np2_l1 = nplus.space(0.4.um, euclidian).polygons(0.001) +np2_l1.output("NP.2", "NP.2 : min. nplus spacing : 0.4µm") +np2_l1.forget + +# Rule NP.3a: Space to PCOMP for PCOMP: (1) Inside Nwell (2) Outside LVPWELL but inside DNWELL. is 0.16µm +logger.info("Executing rule NP.3a") +np3a_l1 = nplus.separation((pcomp.inside(nwell)).or(pcomp.outside(lvpwell).inside(dnwell)), 0.16.um, euclidian).polygons(0.001) +np3a_l1.output("NP.3a", "NP.3a : Space to PCOMP for PCOMP: (1) Inside Nwell (2) Outside LVPWELL but inside DNWELL. : 0.16µm") +np3a_l1.forget + +np_3bi_extend = lvpwell.inside(dnwell).sized(-0.429.um) +np_3bi = pcomp.edges.and(lvpwell.inside(dnwell).not(np_3bi_extend)) +# Rule NP.3bi: Space to PCOMP: For Inside DNWELL, inside LVPWELL:(i) For PCOMP overlap by LVPWELL < 0.43um. is 0.16µm +logger.info("Executing rule NP.3bi") +np3bi_l1 = nplus.not_outside(lvpwell).inside(dnwell).edges.separation(np_3bi, 0.16.um, euclidian).polygons(0.001) +np3bi_l1.output("NP.3bi", "NP.3bi : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(i) For PCOMP overlap by LVPWELL < 0.43um. : 0.16µm") +np3bi_l1.forget + +np_3bi_extend.forget +np_3bi.forget +np_3bii_extend = lvpwell.inside(dnwell).sized(-0.429.um) +np_3bii = pcomp.edges.and(np_3bii_extend) +# Rule NP.3bii: Space to PCOMP: For Inside DNWELL, inside LVPWELL:(ii) For PCOMP overlap by LVPWELL >= 0.43um. is 0.08µm +logger.info("Executing rule NP.3bii") +np3bii_l1 = nplus.not_outside(lvpwell).inside(dnwell).edges.separation(np_3bii, 0.08.um, euclidian).polygons(0.001) +np3bii_l1.output("NP.3bii", "NP.3bii : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(ii) For PCOMP overlap by LVPWELL >= 0.43um. : 0.08µm") +np3bii_l1.forget + +np_3bii_extend.forget +np_3bii.forget +np_3ci = pcomp.edges.and(nwell.outside(dnwell).sized(0.429.um)) +# Rule NP.3ci: Space to PCOMP: For Outside DNWELL:(i) For PCOMP space to Nwell < 0.43um. is 0.16µm +logger.info("Executing rule NP.3ci") +np3ci_l1 = nplus.outside(dnwell).edges.separation(np_3ci, 0.16.um, euclidian).polygons +np3ci_l1.output("NP.3ci", "NP.3ci : Space to PCOMP: For Outside DNWELL:(i) For PCOMP space to Nwell < 0.43um. : 0.16µm") +np3ci_l1.forget + +np_3ci.forget +np_3cii = pcomp.edges.not(nwell.outside(dnwell).sized(0.429.um)) +# Rule NP.3cii: Space to PCOMP: For Outside DNWELL:(ii) For PCOMP space to Nwell >= 0.43um. is 0.08µm +logger.info("Executing rule NP.3cii") +np3cii_l1 = nplus.outside(dnwell).edges.separation(np_3cii, 0.08.um, euclidian).polygons +np3cii_l1.output("NP.3cii", "NP.3cii : Space to PCOMP: For Outside DNWELL:(ii) For PCOMP space to Nwell >= 0.43um. : 0.08µm") +np3cii_l1.forget + +np_3cii.forget +# Rule NP.3d: Min/max space to a butted PCOMP. +logger.info("Executing rule NP.3d") +np3d_l1 = nplus.not_outside(pcomp) +np3d_l1.output("NP.3d", "NP.3d : Min/max space to a butted PCOMP.") +np3d_l1.forget + +# Rule NP.3e: Space to related PCOMP edge adjacent to a butting edge. +logger.info("Executing rule NP.3e") +np3e_l1 = nplus.not_outside(pcomp) +np3e_l1.output("NP.3e", "NP.3e : Space to related PCOMP edge adjacent to a butting edge.") +np3e_l1.forget + +# Rule NP.4a: Space to related P-channel gate at a butting edge parallel to gate. is 0.32µm +logger.info("Executing rule NP.4a") +np4a_l1 = nplus.edges.and(pcomp.edges).separation(pgate.edges, 0.32.um, projection).polygons(0.001) +np4a_l1.output("NP.4a", "NP.4a : Space to related P-channel gate at a butting edge parallel to gate. : 0.32µm") +np4a_l1.forget + +np_4b_poly = poly2.edges.interacting(pgate.edges.not(pcomp.edges)).centers(0, 0.99).and(pgate.sized(0.32.um)) +# Rule NP.4b: Within 0.32um of channel, space to P-channel gate extension perpendicular to the direction of Poly2. +logger.info("Executing rule NP.4b") +np4b_l1 = nplus.interacting(nplus.edges.separation(np_4b_poly, 0.22.um, projection).polygons(0.001)) +np4b_l1.output("NP.4b", "NP.4b : Within 0.32um of channel, space to P-channel gate extension perpendicular to the direction of Poly2.") +np4b_l1.forget + +np_4b_poly.forget +# Rule NP.5a: Overlap of N-channel gate. is 0.23µm +logger.info("Executing rule NP.5a") +np5a_l1 = nplus.enclosing(ngate, 0.23.um, euclidian).polygons(0.001) +np5a_l2 = ngate.not_outside(nplus).not(nplus) +np5a_l = np5a_l1.or(np5a_l2) +np5a_l.output("NP.5a", "NP.5a : Overlap of N-channel gate. : 0.23µm") +np5a_l1.forget +np5a_l2.forget +np5a_l.forget + +# Rule NP.5b: Extension beyond COMP for the COMP (1) inside LVPWELL (2) outside Nwell and DNWELL. is 0.16µm +logger.info("Executing rule NP.5b") +np5b_l1 = nplus.not_outside(lvpwell).or(nplus.outside(nwell).outside(dnwell)).edges.not(pplus).enclosing(comp.edges, 0.16.um, euclidian).polygons(0.001) +np5b_l1.output("NP.5b", "NP.5b : Extension beyond COMP for the COMP (1) inside LVPWELL (2) outside Nwell and DNWELL. : 0.16µm") +np5b_l1.forget + +np_5ci_background = nplus.not_inside(lvpwell).inside(dnwell).edges +np_5ci_foreground = ncomp.not_inside(lvpwell).inside(dnwell).edges.not(pplus.edges).and(lvpwell.inside(dnwell).sized(0.429.um)) +# Rule NP.5ci: Extension beyond COMP: For Inside DNWELL: (i)For Nplus < 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. is 0.16µm +logger.info("Executing rule NP.5ci") +np5ci_l1 = np_5ci_background.enclosing(np_5ci_foreground, 0.16.um, projection).polygons(0.001) +np5ci_l1.output("NP.5ci", "NP.5ci : Extension beyond COMP: For Inside DNWELL: (i)For Nplus < 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.16µm") +np5ci_l1.forget + +np_5ci_background.forget +np_5ci_foreground.forget +np_5cii_background = nplus.not_inside(lvpwell).inside(dnwell).edges +np_5cii_foreground = ncomp.not_inside(lvpwell).inside(dnwell).edges.not(pplus.edges).not(lvpwell.inside(dnwell).sized(0.429.um)) +# Rule NP.5cii: Extension beyond COMP: For Inside DNWELL: (ii) For Nplus >= 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. is 0.02µm +logger.info("Executing rule NP.5cii") +np5cii_l1 = np_5cii_background.enclosing(np_5cii_foreground, 0.02.um, projection).polygons(0.001) +np5cii_l1.output("NP.5cii", "NP.5cii : Extension beyond COMP: For Inside DNWELL: (ii) For Nplus >= 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.02µm") +np5cii_l1.forget + +np_5cii_background.forget +np_5cii_foreground.forget +np_5di_background = nplus.not_outside(nwell).outside(dnwell).edges +np_5di_extend = nwell.outside(dnwell).not(nwell.outside(dnwell).sized(-0.429.um)) +np_5di_foreground = ncomp.not_outside(nwell).outside(dnwell).edges.not(pplus.edges).and(np_5di_extend) +# Rule NP.5di: Extension beyond COMP: For Outside DNWELL, inside Nwell: (i) For Nwell overlap of Nplus < 0.43um. is 0.16µm +logger.info("Executing rule NP.5di") +np5di_l1 = np_5di_background.enclosing(np_5di_foreground, 0.16.um, projection).polygons(0.001) +np5di_l1.output("NP.5di", "NP.5di : Extension beyond COMP: For Outside DNWELL, inside Nwell: (i) For Nwell overlap of Nplus < 0.43um. : 0.16µm") +np5di_l1.forget + +np_5di_background.forget +np_5di_extend.forget +np_5di_foreground.forget +np_5dii_background = nplus.not_outside(nwell).outside(dnwell).edges.not(pplus.edges) +np_5dii_extend = nwell.outside(dnwell).sized(-0.429.um) +np_5dii_foreground = ncomp.not_outside(nwell).outside(dnwell).edges.not(pplus.edges).and(np_5dii_extend) +# Rule NP.5dii: Extension beyond COMP: For Outside DNWELL, inside Nwell: (ii) For Nwell overlap of Nplus >= 0.43um. is 0.02µm +logger.info("Executing rule NP.5dii") +np5dii_l1 = np_5dii_background.enclosing(np_5dii_foreground, 0.02.um, euclidian).polygons(0.001) +np5dii_l1.output("NP.5dii", "NP.5dii : Extension beyond COMP: For Outside DNWELL, inside Nwell: (ii) For Nwell overlap of Nplus >= 0.43um. : 0.02µm") +np5dii_l1.forget + +np_5dii_background.forget +np_5dii_extend.forget +np_5dii_foreground.forget +# Rule NP.6: Overlap with NCOMP butted to PCOMP. is 0.22µm +logger.info("Executing rule NP.6") +np6_l1 = comp.interacting(nplus).enclosing(pcomp.interacting(nplus), 0.22.um, projection).polygons +np6_l1.output("NP.6", "NP.6 : Overlap with NCOMP butted to PCOMP. : 0.22µm") +np6_l1.forget + +# Rule NP.7: Space to unrelated unsalicided Poly2. is 0.18µm +logger.info("Executing rule NP.7") +np7_l1 = nplus.separation(poly2.and(sab), 0.18.um, euclidian).polygons(0.001) +np7_l1.output("NP.7", "NP.7 : Space to unrelated unsalicided Poly2. : 0.18µm") +np7_l1.forget + +# Rule NP.8a: Minimum Nplus area (um2). is 0.35µm² +logger.info("Executing rule NP.8a") +np8a_l1 = nplus.with_area(nil, 0.35.um) +np8a_l1.output("NP.8a", "NP.8a : Minimum Nplus area (um2). : 0.35µm²") +np8a_l1.forget +# Rule NP.8b: Minimum area enclosed by Nplus (um2). is 0.35µm² +logger.info("Executing rule NP.8b") +np8b_l1 = nplus.holes.with_area(nil, 0.35.um) +np8b_l1.output("NP.8b", "NP.8b : Minimum area enclosed by Nplus (um2). : 0.35µm²") +np8b_l1.forget +# Rule NP.9: Overlap of unsalicided Poly2. is 0.18µm +logger.info("Executing rule NP.9") +np9_l1 = nplus.enclosing(poly2.and(sab), 0.18.um, euclidian).polygons(0.001) +np9_l2 = poly2.and(sab).not_outside(nplus).not(nplus) +np9_l = np9_l1.or(np9_l2) +np9_l.output("NP.9", "NP.9 : Overlap of unsalicided Poly2. : 0.18µm") +np9_l1.forget +np9_l2.forget +np9_l.forget + +# Rule NP.10: Overlap of unsalicided COMP. is 0.18µm +logger.info("Executing rule NP.10") +np10_l1 = nplus.enclosing(comp.and(sab), 0.18.um, euclidian).polygons(0.001) +np10_l1.output("NP.10", "NP.10 : Overlap of unsalicided COMP. : 0.18µm") +np10_l1.forget + +np_11_in_dnwell = nplus.interacting(nplus.edges.and(pcomp.edges).and(lvpwell.inside(dnwell).not(lvpwell.inside(dnwell).sized(-0.429.um)))) +np_11_out_dnwell = nplus.interacting(nplus.edges.and(pcomp.edges).and(nwell.outside(dnwell).sized(0.429.um))) +# Rule NP.11: Butting Nplus and PCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case). +logger.info("Executing rule NP.11") +np11_l1 = np_11_in_dnwell.or(np_11_out_dnwell) +np11_l1.output("NP.11", "NP.11 : Butting Nplus and PCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case).") +np11_l1.forget + +np_11_in_dnwell.forget +np_11_out_dnwell.forget +# Rule NP.12: Overlap with P-channel poly2 gate extension is forbidden within 0.32um of P-channel gate. +logger.info("Executing rule NP.12") +np12_l1 = nplus.interacting(nplus.edges.separation(pgate.edges.and(pcomp.edges), 0.32.um, euclidian).polygons(0.001)) +np12_l1.output("NP.12", "NP.12 : Overlap with P-channel poly2 gate extension is forbidden within 0.32um of P-channel gate.") +np12_l1.forget + + +end #FEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/nwell.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/nwell.drc new file mode 100644 index 000000000..7acdba18c --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/nwell.drc @@ -0,0 +1,448 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (NWELL) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +lvpwell = polygons(204, 0 ) +sab = polygons(49 , 0 ) +res_mk = polygons(110, 5 ) +ymtp_mk = polygons(86 , 17) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) +#================================================ +#------------- LAYERS CONNECTIONS --------------- +#================================================ + +if CONNECTIVITY_RULES + + logger.info("Construct connectivity for the design.") + + connect(dnwell, ncomp) + connect(ncomp, contact) + connect(pcomp, contact) + connect(lvpwell, ncomp) + connect(nwell, ncomp) + connect(natcompsd, contact) + connect(mvsd, ncomp) + connect(mvpsd, pcomp) + connect(contact, metal1) + connect(metal1, via1) + connect(via1, metal2) + connect(metal2, via2) + connect(via2, metal3) + connect(metal3, via3) + connect(via3, metal4) + connect(metal4, via4) + connect(via4, metal5) + connect(metal5, via5) + connect(via5, metaltop) + +end #CONNECTIVITY_RULES + +#================================================ +#------------ PRE-DEFINED FUNCTIONS ------------- +#================================================ + +def conn_space(layer,conn_val,not_conn_val, mode) + if conn_val > not_conn_val + raise "ERROR : Wrong connectivity implementation" + end + connected_output = layer.space(conn_val.um, mode).polygons(0.001) + unconnected_errors_unfiltered = layer.space(not_conn_val.um, mode) + singularity_errors = layer.space(0.001.um) + # Filter out the errors arising from the same net + unconnected_errors = DRC::DRCLayer::new(self, RBA::EdgePairs::new) + unconnected_errors_unfiltered.data.each do |ep| + net1 = l2n_data.probe_net(layer.data, ep.first.p1) + net2 = l2n_data.probe_net(layer.data, ep.second.p1) + if !net1 || !net2 + puts "Should not happen ..." + elsif net1.circuit != net2.circuit || net1.cluster_id != net2.cluster_id + # unconnected + unconnected_errors.data.insert(ep) + end + end + unconnected_output = unconnected_errors.polygons.or(singularity_errors.polygons(0.001)) + return connected_output, unconnected_output +end + +def conn_separation(layer1, layer2, conn_val,not_conn_val, mode) + if conn_val > not_conn_val + raise "ERROR : Wrong connectivity implementation" + end + connected_output = layer1.separation(layer2, conn_val.um, mode).polygons(0.001) + unconnected_errors_unfiltered = layer1.separation(layer2, not_conn_val.um, mode) + # Filter out the errors arising from the same net + unconnected_errors = DRC::DRCLayer::new(self, RBA::EdgePairs::new) + unconnected_errors_unfiltered.data.each do |ep| + net1 = l2n_data.probe_net(layer1.data, ep.first.p1) + net2 = l2n_data.probe_net(layer2.data, ep.second.p1) + if !net1 || !net2 + puts "Should not happen ..." + elsif net1.circuit != net2.circuit || net1.cluster_id != net2.cluster_id + # unconnected + unconnected_errors.data.insert(ep) + end + end + unconnected_output = unconnected_errors.polygons(0.001) + return connected_output, unconnected_output +end + +# === IMPLICIT EXTRACTION === +if CONNECTIVITY_RULES + logger.info("Connectivity rules enabled, Netlist object will be generated.") + netlist +end #CONNECTIVITY_RULES + +# === LAYOUT EXTENT === +CHIP = extent.sized(0.0) + +logger.info("Total area of the design is #{CHIP.area()} um^2.") + + + +#================================================ +#---------------------NWELL---------------------- +#================================================ + + +if FEOL +logger.info("FEOL section") + +# Rule NW.1a_3.3V: Min. Nwell Width (This is only for litho purpose on the generated area). is 0.86µm +logger.info("Executing rule NW.1a_3.3V") +nw1a_l1 = nwell.width(0.86.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +nw1a_l1.output("NW.1a_3.3V", "NW.1a_3.3V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm") +nw1a_l1.forget + +# Rule NW.1a_5V: Min. Nwell Width (This is only for litho purpose on the generated area). is 0.86µm +logger.info("Executing rule NW.1a_5V") +nw1a_l1 = nwell.width(0.86.um, euclidian).polygons(0.001).overlapping(dualgate) +nw1a_l1.output("NW.1a_5V", "NW.1a_5V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm") +nw1a_l1.forget + +nw_1b = nwell.outside(dnwell).and(res_mk).not(comp).not(poly2) +# Rule NW.1b_3.3V: Min. Nwell Width as a resistor (Outside DNWELL only). is 2µm +logger.info("Executing rule NW.1b_3.3V") +nw1b_l1 = nw_1b.width(2.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +nw1b_l1.output("NW.1b_3.3V", "NW.1b_3.3V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm") +nw1b_l1.forget + +# Rule NW.1b_5V: Min. Nwell Width as a resistor (Outside DNWELL only). is 2µm +logger.info("Executing rule NW.1b_5V") +nw1b_l1 = nw_1b.width(2.um, euclidian).polygons(0.001).overlapping(dualgate) +nw1b_l1.output("NW.1b_5V", "NW.1b_5V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm") +nw1b_l1.forget + +if CONNECTIVITY_RULES +logger.info("CONNECTIVITY_RULES section") + +connected_nwell_3p3v, unconnected_nwell_3p3v = conn_space(nwell, 0.6, 1.4, euclidian) + +connected_nwell_5p0v, unconnected_nwell_5p0v = conn_space(nwell, 0.74, 1.7, euclidian) + +# Rule NW.2a_3.3V: Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. is 0.6µm +logger.info("Executing rule NW.2a_3.3V") +nw2a_l1 = connected_nwell_3p3v.not_inside(ymtp_mk).not_interacting(v5_xtor).not_interacting(dualgate) +nw2a_l1.output("NW.2a_3.3V", "NW.2a_3.3V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.6µm") +nw2a_l1.forget + +# Rule NW.2a_5V: Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. is 0.74µm +logger.info("Executing rule NW.2a_5V") +nw2a_l1 = connected_nwell_5p0v.not_inside(ymtp_mk).overlapping(dualgate) +nw2a_l1.output("NW.2a_5V", "NW.2a_5V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.74µm") +nw2a_l1.forget + +# Rule NW.2b_3.3V: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.4µm +logger.info("Executing rule NW.2b_3.3V") +nw2b_l1 = unconnected_nwell_3p3v.not_interacting(v5_xtor).not_interacting(dualgate) +nw2b_l1.output("NW.2b_3.3V", "NW.2b_3.3V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.4µm") +nw2b_l1.forget + +# Rule NW.2b_5V: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.7µm +logger.info("Executing rule NW.2b_5V") +nw2b_l1 = unconnected_nwell_5p0v.overlapping(dualgate) +nw2b_l1.output("NW.2b_5V", "NW.2b_5V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.7µm") +nw2b_l1.forget + +else +logger.info("CONNECTIVITY_RULES disabled section") + +# Rule NW.2b_3.3V_: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.4µm +logger.info("Executing rule NW.2b_3.3V_") +nw2b_l1 = nwell.isolated(1.4.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +nw2b_l1.output("NW.2b_3.3V_", "NW.2b_3.3V_ : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.4µm") +nw2b_l1.forget + +# Rule NW.2b_5V_: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.7µm +logger.info("Executing rule NW.2b_5V_") +nw2b_l1 = nwell.isolated(1.7.um, euclidian).polygons(0.001).overlapping(dualgate) +nw2b_l1.output("NW.2b_5V_", "NW.2b_5V_ : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.7µm") +nw2b_l1.forget + +end #CONNECTIVITY_RULES + +# Rule NW.3_3.3V: Min. Nwell to DNWELL space. is 3.1µm +logger.info("Executing rule NW.3_3.3V") +nw3_l1 = nwell.separation(dnwell, 3.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +nw3_l1.output("NW.3_3.3V", "NW.3_3.3V : Min. Nwell to DNWELL space. : 3.1µm") +nw3_l1.forget + +# Rule NW.3_5V: Min. Nwell to DNWELL space. is 3.1µm +logger.info("Executing rule NW.3_5V") +nw3_l1 = nwell.separation(dnwell, 3.1.um, euclidian).polygons(0.001).overlapping(dualgate) +nw3_l1.output("NW.3_5V", "NW.3_5V : Min. Nwell to DNWELL space. : 3.1µm") +nw3_l1.forget + +# Rule NW.4_3.3V: Min. Nwell to LVPWELL space. +logger.info("Executing rule NW.4_3.3V") +nw4_l1 = nwell.not_outside(lvpwell).not_interacting(v5_xtor).not_interacting(dualgate) +nw4_l1.output("NW.4_3.3V", "NW.4_3.3V : Min. Nwell to LVPWELL space.") +nw4_l1.forget + +# Rule NW.4_5V: Min. Nwell to LVPWELL space. +logger.info("Executing rule NW.4_5V") +nw4_l1 = nwell.not_outside(lvpwell).overlapping(dualgate) +nw4_l1.output("NW.4_5V", "NW.4_5V : Min. Nwell to LVPWELL space.") +nw4_l1.forget + +# Rule NW.5_3.3V: Min. DNWELL enclose Nwell. is 0.5µm +logger.info("Executing rule NW.5_3.3V") +nw5_l1 = dnwell.enclosing(nwell, 0.5.um, euclidian).polygons(0.001) +nw5_l2 = nwell.not_outside(dnwell).not(dnwell) +nw5_l = nw5_l1.or(nw5_l2).not_interacting(v5_xtor).not_interacting(dualgate) +nw5_l.output("NW.5_3.3V", "NW.5_3.3V : Min. DNWELL enclose Nwell. : 0.5µm") +nw5_l1.forget +nw5_l2.forget +nw5_l.forget + +# Rule NW.5_5V: Min. DNWELL enclose Nwell. is 0.5µm +logger.info("Executing rule NW.5_5V") +nw5_l1 = dnwell.enclosing(nwell, 0.5.um, euclidian).polygons(0.001) +nw5_l2 = nwell.not_outside(dnwell).not(dnwell) +nw5_l = nw5_l1.or(nw5_l2).overlapping(dualgate) +nw5_l.output("NW.5_5V", "NW.5_5V : Min. DNWELL enclose Nwell. : 0.5µm") +nw5_l1.forget +nw5_l2.forget +nw5_l.forget + +# Rule NW.6: Nwell resistors can only exist outside DNWELL. +logger.info("Executing rule NW.6") +nw6_l1 = nwell.inside(res_mk).interacting(dnwell) +nw6_l1.output("NW.6", "NW.6 : Nwell resistors can only exist outside DNWELL.") +nw6_l1.forget + +# rule NW.6_5V is not a DRC check + +# rule NW.7_3.3V is not a DRC check + +# rule NW.7_5V is not a DRC check + + +end #FEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/otp_mk.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/otp_mk.drc new file mode 100644 index 000000000..32bb3245a --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/otp_mk.drc @@ -0,0 +1,323 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (OTP_MK) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +sab = polygons(49 , 0 ) +contact = polygons(33 , 0 ) +otp_mk = polygons(173, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#---------------------OTP_MK--------------------- +#================================================ + +# Rule O.DF.3a: Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. is 0.24µm +logger.info("Executing rule O.DF.3a") +odf3a_l1 = comp.and(otp_mk).space(0.24.um, euclidian).polygons(0.001) +odf3a_l1.output("O.DF.3a", "O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm") +odf3a_l1.forget + +# Rule O.DF.6: Min. COMP extend beyond poly2 (it also means source/drain overhang). is 0.22µm +logger.info("Executing rule O.DF.6") +odf6_l1 = comp.and(otp_mk).enclosing(poly2.and(otp_mk), 0.22.um, euclidian).polygons(0.001) +odf6_l1.output("O.DF.6", "O.DF.6 : Min. COMP extend beyond poly2 (it also means source/drain overhang). : 0.22µm") +odf6_l1.forget + +# Rule O.DF.9: Min. COMP area (um2). is 0.1444µm² +logger.info("Executing rule O.DF.9") +odf9_l1 = comp.and(otp_mk).with_area(nil, 0.1444.um) +odf9_l1.output("O.DF.9", "O.DF.9 : Min. COMP area (um2). : 0.1444µm²") +odf9_l1.forget +# Rule O.PL.2: Min. poly2 width. is 0.22µm +logger.info("Executing rule O.PL.2") +opl2_l1 = poly2.edges.and(tgate.edges).and(otp_mk).width(0.22.um, euclidian).polygons(0.001) +opl2_l1.output("O.PL.2", "O.PL.2 : Min. poly2 width. : 0.22µm") +opl2_l1.forget + +# Rule O.PL.3a: Min. poly2 Space on COMP. is 0.18µm +logger.info("Executing rule O.PL.3a") +opl3a_l1 = (tgate).or(poly2.not(comp)).and(otp_mk).space(0.18.um, euclidian).polygons(0.001) +opl3a_l1.output("O.PL.3a", "O.PL.3a : Min. poly2 Space on COMP. : 0.18µm") +opl3a_l1.forget + +# Rule O.PL.4: Min. extension beyond COMP to form Poly2 end cap. is 0.14µm +logger.info("Executing rule O.PL.4") +opl4_l1 = poly2.and(otp_mk).enclosing(comp.and(otp_mk), 0.14.um, euclidian).polygons(0.001) +opl4_l1.output("O.PL.4", "O.PL.4 : Min. extension beyond COMP to form Poly2 end cap. : 0.14µm") +opl4_l1.forget + +# rule O.PL.5a is not a DRC check + +# rule O.PL.5b is not a DRC check + +# Rule O.SB.2: Min. salicide Block Space. is 0.28µm +logger.info("Executing rule O.SB.2") +osb2_l1 = sab.and(otp_mk).space(0.28.um, euclidian).polygons(0.001) +osb2_l1.output("O.SB.2", "O.SB.2 : Min. salicide Block Space. : 0.28µm") +osb2_l1.forget + +# Rule O.SB.3: Min. space from salicide block to unrelated COMP. is 0.09µm +logger.info("Executing rule O.SB.3") +osb3_l1 = sab.outside(comp).and(otp_mk).separation(comp.outside(sab), 0.09.um, euclidian).polygons(0.001) +osb3_l1.output("O.SB.3", "O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm") +osb3_l1.forget + +# Rule O.SB.4: Min. space from salicide block to contact. +logger.info("Executing rule O.SB.4") +osb4_l1 = sab.and(otp_mk).separation(contact, 0.03.um, euclidian).polygons(0.001).or(sab.and(otp_mk).and(contact)) +osb4_l1.output("O.SB.4", "O.SB.4 : Min. space from salicide block to contact.") +osb4_l1.forget + +# rule O.SB.5a is not a DRC check + +# Rule O.SB.5b_3.3V: Min. space from salicide block to unrelated Poly2 on COMP. is 0.1µm +logger.info("Executing rule O.SB.5b_3.3V") +osb5b_l1 = sab.outside(tgate).and(otp_mk).separation(tgate.outside(sab), 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +osb5b_l1.output("O.SB.5b_3.3V", "O.SB.5b_3.3V : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm") +osb5b_l1.forget + +# rule O.SB.5b_5V is not a DRC check + +# Rule O.SB.9: Min. salicide block extension beyond unsalicided Poly2. is 0.1µm +logger.info("Executing rule O.SB.9") +osb9_l1 = sab.and(otp_mk).enclosing(poly2.and(sab), 0.1.um, euclidian).polygons +osb9_l1.output("O.SB.9", "O.SB.9 : Min. salicide block extension beyond unsalicided Poly2. : 0.1µm") +osb9_l1.forget + +# Rule O.SB.11: Min. salicide block overlap with COMP. is 0.04µm +logger.info("Executing rule O.SB.11") +osb11_l1 = sab.and(otp_mk).overlap(comp, 0.04.um, euclidian).polygons +osb11_l1.output("O.SB.11", "O.SB.11 : Min. salicide block overlap with COMP. : 0.04µm") +osb11_l1.forget + +# rule O.SB.12 is not a DRC check + +# Rule O.SB.13_3.3V: Min. area of silicide block (um2). is 1.488µm² +logger.info("Executing rule O.SB.13_3.3V") +osb13_l1 = sab.and(otp_mk).with_area(nil, 1.488.um).not_interacting(v5_xtor).not_interacting(dualgate) +osb13_l1.output("O.SB.13_3.3V", "O.SB.13_3.3V : Min. area of silicide block (um2). : 1.488µm²") +osb13_l1.forget +# Rule O.SB.13_5V: Min. area of silicide block (um2). is 2µm² +logger.info("Executing rule O.SB.13_5V") +osb13_l1 = sab.and(otp_mk).and(v5_xtor).with_area(nil, 2.um) +osb13_l1.output("O.SB.13_5V", "O.SB.13_5V : Min. area of silicide block (um2). : 2µm²") +osb13_l1.forget +# rule O.SB.15b is not a DRC check + +# Rule O.CO.7: Min. space from COMP contact to Poly2 on COMP. is 0.13µm +logger.info("Executing rule O.CO.7") +oco7_l1 = contact.not_outside(comp).and(otp_mk).separation(tgate.and(otp_mk), 0.13.um, euclidian).polygons(0.001) +oco7_l1.output("O.CO.7", "O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm") +oco7_l1.forget + +# Rule O.PL.ORT: Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. is 0µm +logger.info("Executing rule O.PL.ORT") +oplort_l1 = comp.not(poly2).edges.and(tgate.edges).and(otp_mk).without_angle(0.um).extended(0, 0, 0.001, 0.001) +oplort_l1.output("O.PL.ORT", "O.PL.ORT : Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. : 0µm") +oplort_l1.forget + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/p+_poly_resistor.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/p+_poly_resistor.drc new file mode 100644 index 000000000..fc5757716 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/p+_poly_resistor.drc @@ -0,0 +1,285 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (P+ POLY RESISTOR) ------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +sab = polygons(49 , 0 ) +contact = polygons(33 , 0 ) +resistor = polygons(62 , 0 ) +res_mk = polygons(110, 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#----------------P+ POLY RESISTOR---------------- +#================================================ + +pres_poly = poly2.and(pplus).interacting(sab).interacting(res_mk).not_interacting(resistor) +# Rule PRES.1: Minimum width of Poly2 resistor. is 0.8µm +logger.info("Executing rule PRES.1") +pres1_l1 = pres_poly.width(0.8.um, euclidian).polygons(0.001) +pres1_l1.output("PRES.1", "PRES.1 : Minimum width of Poly2 resistor. : 0.8µm") +pres1_l1.forget + +# Rule PRES.2: Minimum space between Poly2 resistors. is 0.4µm +logger.info("Executing rule PRES.2") +pres2_l1 = pres_poly.isolated(0.4.um, euclidian).polygons(0.001) +pres2_l1.output("PRES.2", "PRES.2 : Minimum space between Poly2 resistors. : 0.4µm") +pres2_l1.forget + +# Rule PRES.3: Minimum space from Poly2 resistor to COMP. +logger.info("Executing rule PRES.3") +pres3_l1 = pres_poly.separation(comp, 0.6.um, euclidian).polygons(0.001).or(comp.not_outside(pres_poly)) +pres3_l1.output("PRES.3", "PRES.3 : Minimum space from Poly2 resistor to COMP.") +pres3_l1.forget + +# Rule PRES.4: Minimum space from Poly2 resistor to unrelated Poly2. is 0.6µm +logger.info("Executing rule PRES.4") +pres4_l1 = pres_poly.separation(poly2.not_interacting(sab), 0.6.um, euclidian).polygons(0.001) +pres4_l1.output("PRES.4", "PRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm") +pres4_l1.forget + +# Rule PRES.5: Minimum Plus implant overlap of Poly2 resistor. is 0.3µm +logger.info("Executing rule PRES.5") +pres5_l1 = pplus.enclosing(pres_poly, 0.3.um, euclidian).polygons(0.001) +pres5_l2 = pres_poly.not_outside(pplus).not(pplus) +pres5_l = pres5_l1.or(pres5_l2) +pres5_l.output("PRES.5", "PRES.5 : Minimum Plus implant overlap of Poly2 resistor. : 0.3µm") +pres5_l1.forget +pres5_l2.forget +pres5_l.forget + +# Rule PRES.6: Minimum salicide block overlap of Poly2 resistor in width direction. is 0.28µm +logger.info("Executing rule PRES.6") +pres6_l1 = sab.enclosing(pres_poly,0.28.um).polygons(0.001) +pres6_l1.output("PRES.6", "PRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm") +pres6_l1.forget + +# Rule PRES.7: Space from salicide block to contact on Poly2 resistor. +logger.info("Executing rule PRES.7") +pres7_l1 = contact.inside(pres_poly).separation(sab,0.22.um).polygons(0.001).or(contact.inside(pres_poly).interacting(sab)) +pres7_l1.output("PRES.7", "PRES.7 : Space from salicide block to contact on Poly2 resistor.") +pres7_l1.forget + +# rule PRES.8 is not a DRC check + +mk_pres9a = res_mk.edges.not(poly2.and(pplus).and(sab).edges).inside_part(poly2) +# Rule PRES.9a: Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. +logger.info("Executing rule PRES.9a") +pres9a_l1 = res_mk.interacting(pres_poly).interacting(mk_pres9a) +pres9a_l1.output("PRES.9a", "PRES.9a : Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2.") +pres9a_l1.forget + +mk_pres9a.forget +pres9b = res_mk.with_area(15000.01.um,nil).in(res_mk.interacting(res_mk.edges.with_length(80.01.um,nil))) +# Rule PRES.9b: If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. is 20µm +logger.info("Executing rule PRES.9b") +pres9b_l1 = pres9b.interacting(pres_poly).drc(separation(pres9b) < 20.um).polygons(0.001) +pres9b_l1.output("PRES.9b", "PRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm") +pres9b_l1.forget + +pres9b.forget +pres_poly.forget + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/poly2.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/poly2.drc new file mode 100644 index 000000000..adf86103d --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/poly2.drc @@ -0,0 +1,373 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (POLY2) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +mvsd = polygons(210, 0 ) +mvpsd = polygons(11 , 39) +res_mk = polygons(110, 5 ) +otp_mk = polygons(173, 5 ) +sramcore = polygons(108, 5 ) +plfuse = polygons(125, 5 ) +ymtp_mk = polygons(86 , 17) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#---------------------POLY2---------------------- +#================================================ + + +if FEOL +logger.info("FEOL section") + +# Rule PL.1_3.3V: Interconnect Width (outside PLFUSE). is 0.18µm +logger.info("Executing rule PL.1_3.3V") +pl1_l1 = poly2.outside(plfuse).not(ymtp_mk).width(0.18.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl1_l1.output("PL.1_3.3V", "PL.1_3.3V : Interconnect Width (outside PLFUSE). : 0.18µm") +pl1_l1.forget + +# Rule PL.1_5V: Interconnect Width (outside PLFUSE). is 0.2µm +logger.info("Executing rule PL.1_5V") +pl1_l1 = poly2.outside(plfuse).not(ymtp_mk).width(0.2.um, euclidian).polygons(0.001).overlapping(dualgate) +pl1_l1.output("PL.1_5V", "PL.1_5V : Interconnect Width (outside PLFUSE). : 0.2µm") +pl1_l1.forget + +# Rule PL.1a_3.3V: Interconnect Width (inside PLFUSE). is 0.18µm +logger.info("Executing rule PL.1a_3.3V") +pl1a_l1 = poly2.inside(plfuse).width(0.18.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl1a_l1.output("PL.1a_3.3V", "PL.1a_3.3V : Interconnect Width (inside PLFUSE). : 0.18µm") +pl1a_l1.forget + +# Rule PL.1a_5V: Interconnect Width (inside PLFUSE). is 0.18µm +logger.info("Executing rule PL.1a_5V") +pl1a_l1 = poly2.inside(plfuse).width(0.18.um, euclidian).polygons(0.001).overlapping(dualgate) +pl1a_l1.output("PL.1a_5V", "PL.1a_5V : Interconnect Width (inside PLFUSE). : 0.18µm") +pl1a_l1.forget + +# Rule PL.2_3.3V: Gate Width (Channel Length). is 0.28µm +logger.info("Executing rule PL.2_3.3V") +pl2_l1 = poly2.edges.and(tgate.edges).not(otp_mk).not(ymtp_mk).width(0.28.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl2_l1.output("PL.2_3.3V", "PL.2_3.3V : Gate Width (Channel Length). : 0.28µm") +pl2_l1.forget + +pl_2_5v_n = comp.not(poly2).edges.and(ngate.edges).and(v5_xtor).and(dualgate).space(0.6.um, euclidian).polygons +pl_2_5v_p = comp.not(poly2).edges.and(pgate.edges).and(v5_xtor).and(dualgate).space(0.5.um, euclidian).polygons +pl_2_6v_n = comp.not(poly2).edges.and(ngate.edges).not(v5_xtor).and(dualgate).space(0.7.um, euclidian).polygons +pl_2_6v_p = comp.not(poly2).edges.and(pgate.edges).not(v5_xtor).and(dualgate).space(0.55.um, euclidian).polygons +# Rule PL.2_5V: Gate Width (Channel Length). +logger.info("Executing rule PL.2_5V") +pl2_l1 = pl_2_5v_n.or(pl_2_5v_p).or(pl_2_6v_n.or(pl_2_6v_p)) +pl2_l1.output("PL.2_5V", "PL.2_5V : Gate Width (Channel Length).") +pl2_l1.forget + +pl_2_5v_n.forget +pl_2_5v_p.forget +pl_2_6v_n.forget +pl_2_6v_p.forget +# Rule PL.3a_3.3V: Space on COMP/Field. is 0.24µm +logger.info("Executing rule PL.3a_3.3V") +pl3a_l1 = (tgate).or(poly2.not(comp)).not(otp_mk).space(0.24.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl3a_l1.output("PL.3a_3.3V", "PL.3a_3.3V : Space on COMP/Field. : 0.24µm") +pl3a_l1.forget + +# Rule PL.3a_5V: Space on COMP/Field. is 0.24µm +logger.info("Executing rule PL.3a_5V") +pl3a_l1 = (tgate).or(poly2.not(comp)).not(otp_mk).space(0.24.um, euclidian).polygons(0.001).overlapping(dualgate) +pl3a_l1.output("PL.3a_5V", "PL.3a_5V : Space on COMP/Field. : 0.24µm") +pl3a_l1.forget + +# rule PL.3b_3.3V is not a DRC check + +# rule PL.3b_5V is not a DRC check + +poly_pl = poly2.not(otp_mk).not(ymtp_mk).not(mvsd).not(mvpsd) +comp_pl = comp.not(otp_mk).not(ymtp_mk).not(mvsd).not(mvpsd) +# Rule PL.4_3.3V: Extension beyond COMP to form Poly2 end cap. is 0.22µm +logger.info("Executing rule PL.4_3.3V") +pl4_l1 = poly_pl.enclosing(comp.not(otp_mk).not(ymtp_mk), 0.22.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl4_l1.output("PL.4_3.3V", "PL.4_3.3V : Extension beyond COMP to form Poly2 end cap. : 0.22µm") +pl4_l1.forget + +# Rule PL.4_5V: Extension beyond COMP to form Poly2 end cap. is 0.22µm +logger.info("Executing rule PL.4_5V") +pl4_l1 = poly_pl.enclosing(comp.not(otp_mk).not(ymtp_mk), 0.22.um, euclidian).polygons(0.001).overlapping(dualgate) +pl4_l1.output("PL.4_5V", "PL.4_5V : Extension beyond COMP to form Poly2 end cap. : 0.22µm") +pl4_l1.forget + +# Rule PL.5a_3.3V: Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. is 0.1µm +logger.info("Executing rule PL.5a_3.3V") +pl5a_l1 = poly_pl.separation(comp_pl, 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl5a_l1.output("PL.5a_3.3V", "PL.5a_3.3V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.1µm") +pl5a_l1.forget + +# Rule PL.5a_5V: Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. is 0.3µm +logger.info("Executing rule PL.5a_5V") +pl5a_l1 = poly_pl.outside(sramcore).separation(comp_pl, 0.3.um, euclidian).polygons(0.001).overlapping(dualgate) +pl5a_l1.output("PL.5a_5V", "PL.5a_5V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.3µm") +pl5a_l1.forget + +# Rule PL.5b_3.3V: Space from field Poly2 to related COMP. is 0.1µm +logger.info("Executing rule PL.5b_3.3V") +pl5b_l1 = poly_pl.separation(comp_pl, 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl5b_l1.output("PL.5b_3.3V", "PL.5b_3.3V : Space from field Poly2 to related COMP. : 0.1µm") +pl5b_l1.forget + +# Rule PL.5b_5V: Space from field Poly2 to related COMP. is 0.3µm +logger.info("Executing rule PL.5b_5V") +pl5b_l1 = poly_pl.outside(sramcore).separation(comp_pl, 0.3.um, euclidian).polygons(0.001).overlapping(dualgate) +pl5b_l1.output("PL.5b_5V", "PL.5b_5V : Space from field Poly2 to related COMP. : 0.3µm") +pl5b_l1.forget + +poly_pl.forget +comp_pl.forget +poly_90deg = poly2.corners(90.0).sized(0.1).or(poly2.corners(-90.0).sized(0.1)).not(ymtp_mk) +# Rule PL.6: 90 degree bends on the COMP are not allowed. +logger.info("Executing rule PL.6") +pl6_l1 = poly2.corners(90.0).sized(0.1).or(poly2.corners(-90.0).sized(0.1)).not(ymtp_mk).inside(comp.not(ymtp_mk)) +pl6_l1.output("PL.6", "PL.6 : 90 degree bends on the COMP are not allowed.") +pl6_l1.forget + +poly_90deg.forget +poly_45deg = poly2.edges.with_angle(-45).or(poly2.edges.with_angle(45)) +# Rule PL.7_3.3V: 45 degree bent gate width is 0.3µm +logger.info("Executing rule PL.7_3.3V") +pl7_l1 = poly_45deg.width(0.3.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +pl7_l1.output("PL.7_3.3V", "PL.7_3.3V : 45 degree bent gate width : 0.3µm") +pl7_l1.forget + +# Rule PL.7_5V: 45 degree bent gate width is 0.7µm +logger.info("Executing rule PL.7_5V") +pl7_l1 = poly_45deg.width(0.7.um, euclidian).polygons(0.001).overlapping(dualgate) +pl7_l1.output("PL.7_5V", "PL.7_5V : 45 degree bent gate width : 0.7µm") +pl7_l1.forget + +poly_45deg.forget +# Rule PL.9: Poly2 inter connect connecting 3.3V and 5V areas (area inside and outside Dualgate) are not allowed. They shall be done though metal lines only. +logger.info("Executing rule PL.9") +pl9_l1 = poly2.interacting(poly2.not(v5_xtor).not(dualgate)).interacting(poly2.and(dualgate)) +pl9_l1.output("PL.9", "PL.9 : Poly2 inter connect connecting 3.3V and 5V areas (area inside and outside Dualgate) are not allowed. They shall be done though metal lines only.") +pl9_l1.forget + +# rule PL.10 is not a DRC check + +# Rule PL.11: V5_Xtor must enclose 5V device. +logger.info("Executing rule PL.11") +pl11_l1 = v5_xtor.not_interacting(dualgate.or(otp_mk)) +pl11_l1.output("PL.11", "PL.11 : V5_Xtor must enclose 5V device.") +pl11_l1.forget + +# rule PL.12_3.3V is not a DRC check + +# Rule PL.12: V5_Xtor enclose 5V Comp. +logger.info("Executing rule PL.12") +pl12_l1 = comp.interacting(v5_xtor).not(v5_xtor) +pl12_l1.output("PL.12", "PL.12 : V5_Xtor enclose 5V Comp.") +pl12_l1.forget + + +end #FEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/pplus.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/pplus.drc new file mode 100644 index 000000000..98f534a44 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/pplus.drc @@ -0,0 +1,421 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (PPLUS) ------------------------------------------------------------ +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +lvpwell = polygons(204, 0 ) +sab = polygons(49 , 0 ) +resistor = polygons(62 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#---------------------PPLUS---------------------- +#================================================ + + +if FEOL +logger.info("FEOL section") + +# Rule PP.1: min. pplus width is 0.4µm +logger.info("Executing rule PP.1") +pp1_l1 = pplus.width(0.4.um, euclidian).polygons(0.001) +pp1_l1.output("PP.1", "PP.1 : min. pplus width : 0.4µm") +pp1_l1.forget + +# Rule PP.2: min. pplus spacing is 0.4µm +logger.info("Executing rule PP.2") +pp2_l1 = pplus.space(0.4.um, euclidian).polygons(0.001) +pp2_l1.output("PP.2", "PP.2 : min. pplus spacing : 0.4µm") +pp2_l1.forget + +# Rule PP.3a: Space to NCOMP for NCOMP (1) inside LVPWELL (2) outside NWELL and DNWELL. is 0.16µm +logger.info("Executing rule PP.3a") +pp3a_l1 = pplus.separation((ncomp.inside(lvpwell)).or(ncomp.outside(nwell).outside(dnwell)), 0.16.um, euclidian).polygons(0.001) +pp3a_l1.output("PP.3a", "PP.3a : Space to NCOMP for NCOMP (1) inside LVPWELL (2) outside NWELL and DNWELL. : 0.16µm") +pp3a_l1.forget + +pp_3bi = ncomp.edges.not(lvpwell.inside(dnwell).sized(0.429.um)) +# Rule PP.3bi: Space to NCOMP: For Inside DNWELL. (i) NCOMP space to LVPWELL >= 0.43um. is 0.08µm +logger.info("Executing rule PP.3bi") +pp3bi_l1 = pplus.inside(dnwell).edges.separation(pp_3bi, 0.08.um, euclidian).polygons(0.001) +pp3bi_l1.output("PP.3bi", "PP.3bi : Space to NCOMP: For Inside DNWELL. (i) NCOMP space to LVPWELL >= 0.43um. : 0.08µm") +pp3bi_l1.forget + +pp_3bi.forget +pp_3bii = ncomp.edges.and(lvpwell.inside(dnwell).sized(0.429.um)) +# Rule PP.3bii: Space to NCOMP: For Inside DNWELL. (ii) NCOMP space to LVPWELL < 0.43um. is 0.16µm +logger.info("Executing rule PP.3bii") +pp3bii_l1 = pplus.inside(dnwell).edges.separation(pp_3bii, 0.16.um, euclidian).polygons(0.001) +pp3bii_l1.output("PP.3bii", "PP.3bii : Space to NCOMP: For Inside DNWELL. (ii) NCOMP space to LVPWELL < 0.43um. : 0.16µm") +pp3bii_l1.forget + +pp_3bii.forget +pp_3ci_extend = nwell.outside(dnwell).sized(-0.429.um) +pp_3ci = ncomp.edges.and(pp_3ci_extend) +# Rule PP.3ci: Space to NCOMP: For Outside DNWELL, inside Nwell: (i) NWELL Overlap of NCOMP >= 0.43um. is 0.08µm +logger.info("Executing rule PP.3ci") +pp3ci_l1 = pplus.outside(dnwell).edges.separation(pp_3ci, 0.08.um, euclidian).polygons(0.001) +pp3ci_l1.output("PP.3ci", "PP.3ci : Space to NCOMP: For Outside DNWELL, inside Nwell: (i) NWELL Overlap of NCOMP >= 0.43um. : 0.08µm") +pp3ci_l1.forget + +pp_3ci_extend.forget +pp_3ci.forget +pp_3cii_extend = nwell.outside(dnwell).not(nwell.outside(dnwell).sized(-0.429.um)) +pp_3cii = ncomp.edges.and(pp_3cii_extend) +# Rule PP.3cii: Space to NCOMP: For Outside DNWELL, inside Nwell: (ii) NWELL Overlap of NCOMP 0.43um. is 0.16µm +logger.info("Executing rule PP.3cii") +pp3cii_l1 = pplus.outside(dnwell).edges.separation(pp_3cii, 0.16.um, euclidian).polygons(0.001) +pp3cii_l1.output("PP.3cii", "PP.3cii : Space to NCOMP: For Outside DNWELL, inside Nwell: (ii) NWELL Overlap of NCOMP 0.43um. : 0.16µm") +pp3cii_l1.forget + +pp_3cii_extend.forget +pp_3cii.forget +# Rule PP.3d: Min/max space to a butted NCOMP. +logger.info("Executing rule PP.3d") +pp3d_l1 = pplus.not_outside(ncomp) +pp3d_l1.output("PP.3d", "PP.3d : Min/max space to a butted NCOMP.") +pp3d_l1.forget + +# Rule PP.3e: Space to NCOMP edge adjacent to a butting edge. +logger.info("Executing rule PP.3e") +pp3e_l1 = pplus.not_outside(ncomp) +pp3e_l1.output("PP.3e", "PP.3e : Space to NCOMP edge adjacent to a butting edge.") +pp3e_l1.forget + +# Rule PP.4a: Space related to N-channel gate at a butting edge parallel to gate. is 0.32µm +logger.info("Executing rule PP.4a") +pp4a_l1 = pplus.edges.and(ncomp.edges).separation(ngate.edges, 0.32.um, projection).polygons(0.001) +pp4a_l1.output("PP.4a", "PP.4a : Space related to N-channel gate at a butting edge parallel to gate. : 0.32µm") +pp4a_l1.forget + +pp_4b_poly = poly2.edges.interacting(ngate.edges.not(ncomp.edges)).centers(0, 0.99).and(ngate.sized(0.32.um)) +# Rule PP.4b: Within 0.32um of channel, space to N-channel gate extension perpendicular to the direction of Poly2. +logger.info("Executing rule PP.4b") +pp4b_l1 = pplus.interacting(pplus.edges.separation(pp_4b_poly, 0.22.um, projection).polygons(0.001)) +pp4b_l1.output("PP.4b", "PP.4b : Within 0.32um of channel, space to N-channel gate extension perpendicular to the direction of Poly2.") +pp4b_l1.forget + +pp_4b_poly.forget +# Rule PP.5a: Overlap of P-channel gate. is 0.23µm +logger.info("Executing rule PP.5a") +pp5a_l1 = pplus.enclosing(pgate, 0.23.um, euclidian).polygons(0.001) +pp5a_l2 = pgate.not_outside(pplus).not(pplus) +pp5a_l = pp5a_l1.or(pp5a_l2) +pp5a_l.output("PP.5a", "PP.5a : Overlap of P-channel gate. : 0.23µm") +pp5a_l1.forget +pp5a_l2.forget +pp5a_l.forget + +# Rule PP.5b: Extension beyond COMP for COMP (1) Inside NWELL (2) outside LVPWELL but inside DNWELL. is 0.16µm +logger.info("Executing rule PP.5b") +pp5b_l1 = pplus.not_outside(nwell).or(pplus.outside(lvpwell).inside(dnwell)).edges.not(nplus).enclosing(comp.edges, 0.16.um, euclidian).polygons(0.001) +pp5b_l1.output("PP.5b", "PP.5b : Extension beyond COMP for COMP (1) Inside NWELL (2) outside LVPWELL but inside DNWELL. : 0.16µm") +pp5b_l1.forget + +pp_5ci_background = pplus.not_outside(lvpwell).inside(dnwell).edges.not(nplus.edges) +pp_5ci_extend = lvpwell.inside(dnwell).sized(-0.429.um) +pp_5ci_foreground = pcomp.not_outside(lvpwell).inside(dnwell).edges.not(nplus.edges).inside_part(pp_5ci_extend) +# Rule PP.5ci: Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (i) For LVPWELL overlap of Pplus >= 0.43um for LVPWELL tap. is 0.02µm +logger.info("Executing rule PP.5ci") +pp5ci_l1 = pp_5ci_background.enclosing(pp_5ci_foreground, 0.02.um, euclidian).polygons(0.001) +pp5ci_l1.output("PP.5ci", "PP.5ci : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (i) For LVPWELL overlap of Pplus >= 0.43um for LVPWELL tap. : 0.02µm") +pp5ci_l1.forget + +pp_5ci_background.forget +pp_5ci_extend.forget +pp_5ci_foreground.forget +pp_5cii_background = pplus.not_outside(lvpwell).inside(dnwell).edges +pp_5cii_extend = lvpwell.inside(dnwell).not(lvpwell.inside(dnwell).sized(-0.429.um)) +pp_5cii_foreground = pcomp.not_outside(lvpwell).inside(dnwell).edges.not(nplus.edges).and(pp_5cii_extend) +# Rule PP.5cii: Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (ii) For LVPWELL overlap of Pplus < 0.43um for the LVPWELL tap. is 0.16µm +logger.info("Executing rule PP.5cii") +pp5cii_l1 = pp_5cii_background.enclosing(pp_5cii_foreground, 0.16.um, projection).polygons(0.001) +pp5cii_l1.output("PP.5cii", "PP.5cii : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (ii) For LVPWELL overlap of Pplus < 0.43um for the LVPWELL tap. : 0.16µm") +pp5cii_l1.forget + +pp_5cii_background.forget +pp_5cii_extend.forget +pp_5cii_foreground.forget +pp_5di_background = pplus.outside(dnwell).edges +pp_5di_foreground = pcomp.outside(dnwell).edges.not(nplus.edges).not(nwell.outside(dnwell).sized(0.429.um)) +# Rule PP.5di: Extension beyond COMP: For Outside DNWELL (i) For Pplus to NWELL space >= 0.43um for Pfield or LVPWELL tap. is 0.02µm +logger.info("Executing rule PP.5di") +pp5di_l1 = pp_5di_background.enclosing(pp_5di_foreground, 0.02.um, projection).polygons(0.001) +pp5di_l1.output("PP.5di", "PP.5di : Extension beyond COMP: For Outside DNWELL (i) For Pplus to NWELL space >= 0.43um for Pfield or LVPWELL tap. : 0.02µm") +pp5di_l1.forget + +pp_5di_background.forget +pp_5di_foreground.forget +pp_5dii_background = pplus.outside(dnwell).edges +pp_5dii_foreground = pcomp.outside(dnwell).edges.not(nplus.edges).and(nwell.outside(dnwell).sized(0.429.um)) +# Rule PP.5dii: Extension beyond COMP: For Outside DNWELL (ii) For Pplus to NWELL space < 0.43um for Pfield or LVPWELL tap. is 0.16µm +logger.info("Executing rule PP.5dii") +pp5dii_l1 = pp_5dii_background.enclosing(pp_5dii_foreground, 0.16.um, projection).polygons(0.001) +pp5dii_l1.output("PP.5dii", "PP.5dii : Extension beyond COMP: For Outside DNWELL (ii) For Pplus to NWELL space < 0.43um for Pfield or LVPWELL tap. : 0.16µm") +pp5dii_l1.forget + +pp_5dii_background.forget +pp_5dii_foreground.forget +# Rule PP.6: Overlap with PCOMP butted to NCOMP. is 0.22µm +logger.info("Executing rule PP.6") +pp6_l1 = comp.interacting(pplus).enclosing(ncomp.interacting(pplus), 0.22.um, projection).polygons +pp6_l1.output("PP.6", "PP.6 : Overlap with PCOMP butted to NCOMP. : 0.22µm") +pp6_l1.forget + +# Rule PP.7: Space to unrelated unsalicided Poly2. is 0.18µm +logger.info("Executing rule PP.7") +pp7_l1 = pplus.separation(poly2.and(sab), 0.18.um, euclidian).polygons(0.001) +pp7_l1.output("PP.7", "PP.7 : Space to unrelated unsalicided Poly2. : 0.18µm") +pp7_l1.forget + +# Rule PP.8a: Minimum Pplus area (um2). is 0.35µm² +logger.info("Executing rule PP.8a") +pp8a_l1 = pplus.with_area(nil, 0.35.um) +pp8a_l1.output("PP.8a", "PP.8a : Minimum Pplus area (um2). : 0.35µm²") +pp8a_l1.forget +# Rule PP.8b: Minimum area enclosed by Pplus (um2). is 0.35µm² +logger.info("Executing rule PP.8b") +pp8b_l1 = pplus.holes.with_area(nil, 0.35.um) +pp8b_l1.output("PP.8b", "PP.8b : Minimum area enclosed by Pplus (um2). : 0.35µm²") +pp8b_l1.forget +# Rule PP.9: Overlap of unsalicided Poly2. is 0.18µm +logger.info("Executing rule PP.9") +pp9_l1 = pplus.enclosing(poly2.not_interacting(resistor).and(sab), 0.18.um, euclidian).polygons(0.001) +pp9_l2 = poly2.not_interacting(resistor).and(sab).not_outside(pplus).not(pplus) +pp9_l = pp9_l1.or(pp9_l2) +pp9_l.output("PP.9", "PP.9 : Overlap of unsalicided Poly2. : 0.18µm") +pp9_l1.forget +pp9_l2.forget +pp9_l.forget + +# Rule PP.10: Overlap of unsalicided COMP. is 0.18µm +logger.info("Executing rule PP.10") +pp10_l1 = pplus.enclosing(comp.and(sab), 0.18.um, euclidian).polygons(0.001) +pp10_l1.output("PP.10", "PP.10 : Overlap of unsalicided COMP. : 0.18µm") +pp10_l1.forget + +pp_11_in_dnwell = pplus.interacting(pplus.edges.and(ncomp.edges).and(lvpwell.inside(dnwell).sized(0.429.um))) +pp_11_out_dnwell = pplus.interacting(pplus.edges.and(ncomp.edges).and(nwell.outside(dnwell).not(nwell.outside(dnwell).sized(-0.429.um)))) +# Rule PP.11: Butting Pplus and NCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case). +logger.info("Executing rule PP.11") +pp11_l1 = pp_11_in_dnwell.or(pp_11_out_dnwell) +pp11_l1.output("PP.11", "PP.11 : Butting Pplus and NCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case).") +pp11_l1.forget + +pp_11_in_dnwell.forget +pp_11_out_dnwell.forget +# Rule PP.12: Overlap with N-channel Poly2 gate extension is forbidden within 0.32um of N-channel gate. +logger.info("Executing rule PP.12") +pp12_l1 = pplus.interacting(pplus.edges.separation(ngate.edges.and(ncomp.edges), 0.32.um, euclidian).polygons(0.001)) +pp12_l1.output("PP.12", "PP.12 : Overlap with N-channel Poly2 gate extension is forbidden within 0.32um of N-channel gate.") +pp12_l1.forget + + +end #FEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/sab.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/sab.drc new file mode 100644 index 000000000..387351efd --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/sab.drc @@ -0,0 +1,346 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (SAB) ------------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +nwell = polygons(21 , 0 ) +sab = polygons(49 , 0 ) +esd = polygons(24 , 0 ) +contact = polygons(33 , 0 ) +otp_mk = polygons(173, 5 ) +lvs_io = polygons(119, 5 ) +esd_mk = polygons(24 , 5 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#----------------------SAB----------------------- +#================================================ + + +if FEOL +logger.info("FEOL section") + +# Rule SB.1: min. sab width is 0.42µm +logger.info("Executing rule SB.1") +sb1_l1 = sab.width(0.42.um, euclidian).polygons(0.001) +sb1_l1.output("SB.1", "SB.1 : min. sab width : 0.42µm") +sb1_l1.forget + +# Rule SB.2: min. sab spacing is 0.42µm +logger.info("Executing rule SB.2") +sb2_l1 = sab.outside(otp_mk).space(0.42.um, euclidian).polygons(0.001) +sb2_l1.output("SB.2", "SB.2 : min. sab spacing : 0.42µm") +sb2_l1.forget + +# Rule SB.3: Space from salicide block to unrelated COMP. is 0.22µm +logger.info("Executing rule SB.3") +sb3_l1 = sab.outside(comp).outside(otp_mk).separation(comp.outside(sab), 0.22.um, euclidian).polygons(0.001) +sb3_l1.output("SB.3", "SB.3 : Space from salicide block to unrelated COMP. : 0.22µm") +sb3_l1.forget + +# Rule SB.4: Space from salicide block to contact. +logger.info("Executing rule SB.4") +sb4_l1 = sab.outside(otp_mk).separation(contact, 0.15.um, euclidian).polygons(0.001).or(sab.outside(otp_mk).and(contact)) +sb4_l1.output("SB.4", "SB.4 : Space from salicide block to contact.") +sb4_l1.forget + +# Rule SB.5a: Space from salicide block to unrelated Poly2 on field. is 0.3µm +logger.info("Executing rule SB.5a") +sb5a_l1 = sab.outside(poly2.not(comp)).outside(otp_mk).separation(poly2.not(comp).outside(sab), 0.3.um, euclidian).polygons(0.001) +sb5a_l1.output("SB.5a", "SB.5a : Space from salicide block to unrelated Poly2 on field. : 0.3µm") +sb5a_l1.forget + +# Rule SB.5b: Space from salicide block to unrelated Poly2 on COMP. is 0.28µm +logger.info("Executing rule SB.5b") +sb5b_l1 = sab.outside(tgate).outside(otp_mk).separation(tgate.outside(sab), 0.28.um, euclidian).polygons(0.001) +sb5b_l1.output("SB.5b", "SB.5b : Space from salicide block to unrelated Poly2 on COMP. : 0.28µm") +sb5b_l1.forget + +# Rule SB.6: Salicide block extension beyond related COMP. is 0.22µm +logger.info("Executing rule SB.6") +sb6_l1 = sab.enclosing(comp, 0.22.um, euclidian).polygons(0.001) +sb6_l1.output("SB.6", "SB.6 : Salicide block extension beyond related COMP. : 0.22µm") +sb6_l1.forget + +# Rule SB.7: COMP extension beyond related salicide block. is 0.22µm +logger.info("Executing rule SB.7") +sb7_l1 = comp.enclosing(sab, 0.22.um, euclidian).polygons +sb7_l1.output("SB.7", "SB.7 : COMP extension beyond related salicide block. : 0.22µm") +sb7_l1.forget + +# Rule SB.8: Non-salicided contacts are forbidden. +logger.info("Executing rule SB.8") +sb8_l1 = contact.inside(sab) +sb8_l1.output("SB.8", "SB.8 : Non-salicided contacts are forbidden.") +sb8_l1.forget + +# Rule SB.9: Salicide block extension beyond unsalicided Poly2. is 0.22µm +logger.info("Executing rule SB.9") +sb9_l1 = sab.outside(otp_mk).enclosing(poly2.and(sab), 0.22.um, euclidian).polygons +sb9_l1.output("SB.9", "SB.9 : Salicide block extension beyond unsalicided Poly2. : 0.22µm") +sb9_l1.forget + +# Rule SB.10: Poly2 extension beyond related salicide block. is 0.22µm +logger.info("Executing rule SB.10") +sb10_l1 = poly2.enclosing(sab, 0.22.um, euclidian).polygons(0.001) +sb10_l1.output("SB.10", "SB.10 : Poly2 extension beyond related salicide block. : 0.22µm") +sb10_l1.forget + +# Rule SB.11: Overlap with COMP. is 0.22µm +logger.info("Executing rule SB.11") +sb11_l1 = sab.outside(otp_mk).overlap(comp, 0.22.um, euclidian).polygons +sb11_l1.output("SB.11", "SB.11 : Overlap with COMP. : 0.22µm") +sb11_l1.forget + +# Rule SB.12: Overlap with Poly2 outside ESD_MK. is 0.22µm +logger.info("Executing rule SB.12") +sb12_l1 = sab.outside(otp_mk).outside(esd_mk).overlap(poly2.outside(otp_mk).outside(esd_mk), 0.22.um, euclidian).polygons +sb12_l1.output("SB.12", "SB.12 : Overlap with Poly2 outside ESD_MK. : 0.22µm") +sb12_l1.forget + +# Rule SB.13: Min. area (um2). is 2µm² +logger.info("Executing rule SB.13") +sb13_l1 = sab.outside(otp_mk).with_area(nil, 2.um) +sb13_l1.output("SB.13", "SB.13 : Min. area (um2). : 2µm²") +sb13_l1.forget +# Rule SB.14a: Space from unsalicided Nplus Poly2 to unsalicided Pplus Poly2. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at unsalicided Pplus Poly2 corners). is 0.56µm +logger.info("Executing rule SB.14a") +sb14a_l1 = poly2.and(nplus).and(sab).separation(poly2.and(pplus).and(sab), 0.56.um, square).polygons +sb14a_l1.output("SB.14a", "SB.14a : Space from unsalicided Nplus Poly2 to unsalicided Pplus Poly2. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at unsalicided Pplus Poly2 corners). : 0.56µm") +sb14a_l1.forget + +# Rule SB.14b: Space from unsalicided Nplus Poly2 to P-channel gate. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at P-channel gate corners). is 0.56µm +logger.info("Executing rule SB.14b") +sb14b_l1 = poly2.and(nplus).and(sab).separation(pgate, 0.56.um, square).polygons +sb14b_l1.output("SB.14b", "SB.14b : Space from unsalicided Nplus Poly2 to P-channel gate. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at P-channel gate corners). : 0.56µm") +sb14b_l1.forget + +# Rule SB.15a: Space from unsalicided Poly2 to unrelated Nplus/Pplus. is 0.18µm +logger.info("Executing rule SB.15a") +sb15a_l1 = poly2.and(sab).separation(nplus.or(pplus), 0.18.um, euclidian).polygons(0.001) +sb15a_l1.output("SB.15a", "SB.15a : Space from unsalicided Poly2 to unrelated Nplus/Pplus. : 0.18µm") +sb15a_l1.forget + +sb_15b_1 = poly2.interacting(nplus.or(pplus)).and(sab).edges.not(poly2.edges.and(sab)).separation(nplus.or(pplus).edges, 0.32.um, projection).polygons(0.001) +sb_15b_2 = poly2.interacting(nplus.or(pplus)).and(sab).separation(nplus.or(pplus), 0.32.um, projection).polygons(0.001) +# Rule SB.15b: Space from unsalicided Poly2 to unrelated Nplus/Pplus along Poly2 line. is 0.32µm +logger.info("Executing rule SB.15b") +sb15b_l1 = sb_15b_1.and(sb_15b_2).outside(otp_mk) +sb15b_l1.output("SB.15b", "SB.15b : Space from unsalicided Poly2 to unrelated Nplus/Pplus along Poly2 line. : 0.32µm") +sb15b_l1.forget + +sb_15b_1.forget +sb_15b_2.forget +# Rule SB.16: SAB layer cannot exist on 3.3V and 5V/6V CMOS transistors' Poly and COMP area of the core circuit (Excluding the transistors used for ESD purpose). It can only exist on CMOS transistors marked by LVS_IO, OTP_MK, ESD_MK layers. +logger.info("Executing rule SB.16") +sb16_l1 = sab.outside(otp_mk).outside(otp_mk.or(lvs_io).or(esd_mk)).not_outside(ngate.or(pgate.and(nwell))) +sb16_l1.output("SB.16", "SB.16 : SAB layer cannot exist on 3.3V and 5V/6V CMOS transistors' Poly and COMP area of the core circuit (Excluding the transistors used for ESD purpose). It can only exist on CMOS transistors marked by LVS_IO, OTP_MK, ESD_MK layers.") +sb16_l1.forget + + +end #FEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via1.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via1.drc new file mode 100644 index 000000000..2f47e552a --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via1.drc @@ -0,0 +1,313 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (VIA1) ------------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +metal1 = polygons(34 , 0 ) +via1 = polygons(35 , 0 ) +metal2 = polygons(36 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#----------------------VIA1---------------------- +#================================================ + + +if BEOL +logger.info("BEOL section") + +# Rule V1.1: Min/max Via1 size . is 0.26µm +logger.info("Executing rule V1.1") +v11_l1 = via1.edges.without_length(0.26.um).extended(0, 0, 0.001, 0.001) +v11_l1.output("V1.1", "V1.1 : Min/max Via1 size . : 0.26µm") +v11_l1.forget + +# Rule V1.2a: min. via1 spacing is 0.26µm +logger.info("Executing rule V1.2a") +v12a_l1 = via1.space(0.26.um, euclidian).polygons(0.001) +v12a_l1.output("V1.2a", "V1.2a : min. via1 spacing : 0.26µm") +v12a_l1.forget + +merged_via1 = via1.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal1) +via1_mask = merged_via1.size(1).not(via1).with_holes(16, nil) +selected_via1 = via1.interacting(via1_mask) +# Rule V1.2b: Via1 Space in 4x4 or larger via1 array is 0.36µm +logger.info("Executing rule V1.2b") +v12b_l1 = selected_via1.space(0.36.um, euclidian).polygons(0.001) +v12b_l1.output("V1.2b", "V1.2b : Via1 Space in 4x4 or larger via1 array : 0.36µm") +v12b_l1.forget + +merged_via1.forget +via1_mask.forget +selected_via1.forget +# Rule V1.3a: metal-1 overlap of via1. +logger.info("Executing rule V1.3a") +v13a_l1 = via1.not(metal1) +v13a_l1.output("V1.3a", "V1.3a : metal-1 overlap of via1.") +v13a_l1.forget + +# rule V1.3b is not a DRC check + +v1p3c_cond = metal1.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v1p3c_eol = metal1.edges.with_length(nil, 0.34.um).interacting(v1p3c_cond.first_edges).interacting(v1p3c_cond.second_edges).not(v1p3c_cond.first_edges).not(v1p3c_cond.second_edges) +# Rule V1.3c: metal-1 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V1.3c") +v13c_l1 = v1p3c_eol.enclosing(via1.edges,0.06.um, projection).polygons(0.001) +v13c_l1.output("V1.3c", "V1.3c : metal-1 (< 0.34um) end-of-line overlap. : 0.06µm") +v13c_l1.forget + +v1p3c_cond.forget +v1p3c_eol.forget +v1_3d_1 = via1.edges.interacting(via1.drc(enclosed(metal1, projection) < 0.04.um).edges.centers(0, 0.5)) +v1_3d_2 = via1.edges.interacting(via1.drc(0.04.um <= enclosed(metal1, projection) < 0.06.um).centers(0, 0.5)) +v1_3d_3 = v1_3d_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V1.3d: If metal-1 overlap via1 by < 0.04um on one side, adjacent metal-1 edges overlap. is 0.06µm +logger.info("Executing rule V1.3d") +v13d_l1 = v1_3d_2.not_in(v1_3d_1).interacting(v1_3d_1).or(v1_3d_1.interacting(v1_3d_3)).enclosed(metal1.edges, 0.06.um).polygons(0.001) +v13d_l1.output("V1.3d", "V1.3d : If metal-1 overlap via1 by < 0.04um on one side, adjacent metal-1 edges overlap. : 0.06µm") +v13d_l1.forget + +v1_3d_1.forget +v1_3d_2.forget +v1_3d_3.forget +# rule V1.3e is not a DRC check + +# Rule V1.4a: metal-2 overlap of via1. +logger.info("Executing rule V1.4a") +v14a_l1 = metal2.enclosing(via1, 0.01.um, euclidian).polygons(0.001).or(via1.not(metal2)) +v14a_l1.output("V1.4a", "V1.4a : metal-2 overlap of via1.") +v14a_l1.forget + +v1p4b_cond = metal2.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v1p4b_eol = metal2.edges.with_length(nil, 0.34.um).interacting(v1p4b_cond.first_edges).interacting(v1p4b_cond.second_edges).not(v1p4b_cond.first_edges).not(v1p4b_cond.second_edges) +# Rule V1.4b: metal-2 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V1.4b") +v14b_l1 = v1p4b_eol.enclosing(via1.edges,0.06.um, projection).polygons(0.001) +v14b_l1.output("V1.4b", "V1.4b : metal-2 (< 0.34um) end-of-line overlap. : 0.06µm") +v14b_l1.forget + +v1p4b_cond.forget +v1p4b_eol.forget +v1_4c_1 = via1.edges.interacting(via1.drc(enclosed(metal2, projection) < 0.04.um).edges.centers(0, 0.5)) +v1_4c_2 = via1.edges.interacting(via1.drc(0.04.um <= enclosed(metal2, projection) < 0.06.um).centers(0, 0.5)) +v1_4c_3 = v1_4c_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V1.4c: If metal-2 overlap via1 by < 0.04um on one side, adjacent metal-2 edges overlap. is 0.06µm +logger.info("Executing rule V1.4c") +v14c_l1 = v1_4c_2.not_in(v1_4c_1).interacting(v1_4c_1).or(v1_4c_1.interacting(v1_4c_3)).enclosed(metal2.edges, 0.06.um).polygons(0.001) +v14c_l1.output("V1.4c", "V1.4c : If metal-2 overlap via1 by < 0.04um on one side, adjacent metal-2 edges overlap. : 0.06µm") +v14c_l1.forget + +v1_4c_1.forget +v1_4c_2.forget +v1_4c_3.forget +# rule V1.4d is not a DRC check + +# rule V1.5 is not a DRC check + + +end #BEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via2.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via2.drc new file mode 100644 index 000000000..1428f153b --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via2.drc @@ -0,0 +1,313 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (VIA2) ------------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +metal2 = polygons(36 , 0 ) +via2 = polygons(38 , 0 ) +metal3 = polygons(42 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#----------------------VIA2---------------------- +#================================================ + + +if BEOL +logger.info("BEOL section") + +# Rule V2.1: Min/max Via2 size . is 0.26µm +logger.info("Executing rule V2.1") +v21_l1 = via2.edges.without_length(0.26.um).extended(0, 0, 0.001, 0.001) +v21_l1.output("V2.1", "V2.1 : Min/max Via2 size . : 0.26µm") +v21_l1.forget + +# Rule V2.2a: min. via2 spacing is 0.26µm +logger.info("Executing rule V2.2a") +v22a_l1 = via2.space(0.26.um, euclidian).polygons(0.001) +v22a_l1.output("V2.2a", "V2.2a : min. via2 spacing : 0.26µm") +v22a_l1.forget + +merged_via2 = via2.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal2) +via2_mask = merged_via2.size(1).not(via2).with_holes(16, nil) +selected_via2 = via2.interacting(via2_mask) +# Rule V2.2b: Via2 Space in 4x4 or larger via2 array is 0.36µm +logger.info("Executing rule V2.2b") +v22b_l1 = selected_via2.space(0.36.um, euclidian).polygons(0.001) +v22b_l1.output("V2.2b", "V2.2b : Via2 Space in 4x4 or larger via2 array : 0.36µm") +v22b_l1.forget + +merged_via2.forget +via2_mask.forget +selected_via2.forget +# rule V2.3a is not a DRC check + +# Rule V2.3b: metal2 overlap of via2. +logger.info("Executing rule V2.3b") +v23b_l1 = metal2.enclosing(via2, 0.01.um, euclidian).polygons(0.001).or(via2.not(metal2)) +v23b_l1.output("V2.3b", "V2.3b : metal2 overlap of via2.") +v23b_l1.forget + +v2p3c_cond = metal2.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v2p3c_eol = metal2.edges.with_length(nil, 0.34.um).interacting(v2p3c_cond.first_edges).interacting(v2p3c_cond.second_edges).not(v2p3c_cond.first_edges).not(v2p3c_cond.second_edges) +# Rule V2.3c: metal2 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V2.3c") +v23c_l1 = v2p3c_eol.enclosing(via2.edges,0.06.um, projection).polygons(0.001) +v23c_l1.output("V2.3c", "V2.3c : metal2 (< 0.34um) end-of-line overlap. : 0.06µm") +v23c_l1.forget + +v2p3c_cond.forget +v2p3c_eol.forget +v2_3d_1 = via2.edges.interacting(via2.drc(enclosed(metal2, projection) < 0.04.um).edges.centers(0, 0.5)) +v2_3d_2 = via2.edges.interacting(via2.drc(0.04.um <= enclosed(metal2, projection) < 0.06.um).centers(0, 0.5)) +v2_3d_3 = v2_3d_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V2.3d: If metal2 overlap via2 by < 0.04um on one side, adjacent metal2 edges overlap. is 0.06µm +logger.info("Executing rule V2.3d") +v23d_l1 = v2_3d_2.not_in(v2_3d_1).interacting(v2_3d_1).or(v2_3d_1.interacting(v2_3d_3)).enclosed(metal2.edges, 0.06.um).polygons(0.001) +v23d_l1.output("V2.3d", "V2.3d : If metal2 overlap via2 by < 0.04um on one side, adjacent metal2 edges overlap. : 0.06µm") +v23d_l1.forget + +v2_3d_1.forget +v2_3d_2.forget +v2_3d_3.forget +# rule V2.3e is not a DRC check + +# Rule V2.4a: metal3 overlap of via2. +logger.info("Executing rule V2.4a") +v24a_l1 = metal3.enclosing(via2, 0.01.um, euclidian).polygons(0.001).or(via2.not(metal3)) +v24a_l1.output("V2.4a", "V2.4a : metal3 overlap of via2.") +v24a_l1.forget + +v2p4b_cond = metal3.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v2p4b_eol = metal3.edges.with_length(nil, 0.34.um).interacting(v2p4b_cond.first_edges).interacting(v2p4b_cond.second_edges).not(v2p4b_cond.first_edges).not(v2p4b_cond.second_edges) +# Rule V2.4b: metal3 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V2.4b") +v24b_l1 = v2p4b_eol.enclosing(via2.edges,0.06.um, projection).polygons(0.001) +v24b_l1.output("V2.4b", "V2.4b : metal3 (< 0.34um) end-of-line overlap. : 0.06µm") +v24b_l1.forget + +v2p4b_cond.forget +v2p4b_eol.forget +v2_4c_1 = via2.edges.interacting(via2.drc(enclosed(metal3, projection) < 0.04.um).edges.centers(0, 0.5)) +v2_4c_2 = via2.edges.interacting(via2.drc(0.04.um <= enclosed(metal3, projection) < 0.06.um).centers(0, 0.5)) +v2_4c_3 = v2_4c_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V2.4c: If metal3 overlap via2 by < 0.04um on one side, adjacent metal3 edges overlap. is 0.06µm +logger.info("Executing rule V2.4c") +v24c_l1 = v2_4c_2.not_in(v2_4c_1).interacting(v2_4c_1).or(v2_4c_1.interacting(v2_4c_3)).enclosed(metal3.edges, 0.06.um).polygons(0.001) +v24c_l1.output("V2.4c", "V2.4c : If metal3 overlap via2 by < 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm") +v24c_l1.forget + +v2_4c_1.forget +v2_4c_2.forget +v2_4c_3.forget +# rule V2.4d is not a DRC check + +# rule V2.5 is not a DRC check + + +end #BEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via3.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via3.drc new file mode 100644 index 000000000..e39426380 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via3.drc @@ -0,0 +1,313 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (VIA3) ------------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +metal3 = polygons(42 , 0 ) +via3 = polygons(40 , 0 ) +metal4 = polygons(46 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#----------------------VIA3---------------------- +#================================================ + + +if BEOL +logger.info("BEOL section") + +# Rule V3.1: Min/max Via3 size . is 0.26µm +logger.info("Executing rule V3.1") +v31_l1 = via3.edges.without_length(0.26.um).extended(0, 0, 0.001, 0.001) +v31_l1.output("V3.1", "V3.1 : Min/max Via3 size . : 0.26µm") +v31_l1.forget + +# Rule V3.2a: min. via3 spacing is 0.26µm +logger.info("Executing rule V3.2a") +v32a_l1 = via3.space(0.26.um, euclidian).polygons(0.001) +v32a_l1.output("V3.2a", "V3.2a : min. via3 spacing : 0.26µm") +v32a_l1.forget + +merged_via3 = via3.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal3) +via3_mask = merged_via3.size(1).not(via3).with_holes(16, nil) +selected_via3 = via3.interacting(via3_mask) +# Rule V3.2b: Via3 Space in 4x4 or larger via3 array is 0.36µm +logger.info("Executing rule V3.2b") +v32b_l1 = selected_via3.space(0.36.um, euclidian).polygons(0.001) +v32b_l1.output("V3.2b", "V3.2b : Via3 Space in 4x4 or larger via3 array : 0.36µm") +v32b_l1.forget + +merged_via3.forget +via3_mask.forget +selected_via3.forget +# rule V3.3a is not a DRC check + +# Rule V3.3b: metal3 overlap of via3. +logger.info("Executing rule V3.3b") +v33b_l1 = metal3.enclosing(via3, 0.01.um, euclidian).polygons(0.001).or(via3.not(metal3)) +v33b_l1.output("V3.3b", "V3.3b : metal3 overlap of via3.") +v33b_l1.forget + +v3p3c_cond = metal3.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v3p3c_eol = metal3.edges.with_length(nil, 0.34.um).interacting(v3p3c_cond.first_edges).interacting(v3p3c_cond.second_edges).not(v3p3c_cond.first_edges).not(v3p3c_cond.second_edges) +# Rule V3.3c: metal3 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V3.3c") +v33c_l1 = v3p3c_eol.enclosing(via3.edges,0.06.um, projection).polygons(0.001) +v33c_l1.output("V3.3c", "V3.3c : metal3 (< 0.34um) end-of-line overlap. : 0.06µm") +v33c_l1.forget + +v3p3c_cond.forget +v3p3c_eol.forget +v3_3d_1 = via3.edges.interacting(via3.drc(enclosed(metal3, projection) < 0.04.um).edges.centers(0, 0.5)) +v3_3d_2 = via3.edges.interacting(via3.drc(0.04.um <= enclosed(metal3, projection) < 0.06.um).centers(0, 0.5)) +v3_3d_3 = v3_3d_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V3.3d: If metal3 overlap via3 by < 0.04um on one side, adjacent metal3 edges overlap. is 0.06µm +logger.info("Executing rule V3.3d") +v33d_l1 = v3_3d_2.not(v3_3d_1).interacting(v3_3d_1).or(v3_3d_1.interacting(v3_3d_3)).enclosed(metal3.edges, 0.06.um).polygons(0.001) +v33d_l1.output("V3.3d", "V3.3d : If metal3 overlap via3 by < 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm") +v33d_l1.forget + +v3_3d_1.forget +v3_3d_2.forget +v3_3d_3.forget +# rule V3.3e is not a DRC check + +# Rule V3.4a: metal4 overlap of via3. +logger.info("Executing rule V3.4a") +v34a_l1 = metal4.enclosing(via3, 0.01.um, euclidian).polygons(0.001).or(via3.not(metal4)) +v34a_l1.output("V3.4a", "V3.4a : metal4 overlap of via3.") +v34a_l1.forget + +v3p4b_cond = metal4.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v3p4b_eol = metal4.edges.with_length(nil, 0.34.um).interacting(v3p4b_cond.first_edges).interacting(v3p4b_cond.second_edges).not(v3p4b_cond.first_edges).not(v3p4b_cond.second_edges) +# Rule V3.4b: metal4 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V3.4b") +v34b_l1 = v3p4b_eol.enclosing(via3.edges,0.06.um, projection).polygons(0.001) +v34b_l1.output("V3.4b", "V3.4b : metal4 (< 0.34um) end-of-line overlap. : 0.06µm") +v34b_l1.forget + +v3p4b_cond.forget +v3p4b_eol.forget +v3_4c_1 = via3.edges.interacting(via3.drc(enclosed(metal4, projection) < 0.04.um).edges.centers(0, 0.5)) +v3_4c_2 = via3.edges.interacting(via3.drc(0.04.um <= enclosed(metal4, projection) < 0.06.um).centers(0, 0.5)) +v3_4c_3 = v3_4c_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V3.4c: If metal4 overlap via3 by < 0.04um on one side, adjacent metal4 edges overlap. is 0.06µm +logger.info("Executing rule V3.4c") +v34c_l1 = v3_4c_2.not_in(v3_4c_1).interacting(v3_4c_1).or(v3_4c_1.interacting(v3_4c_3)).enclosed(metal4.edges, 0.06.um).polygons(0.001) +v34c_l1.output("V3.4c", "V3.4c : If metal4 overlap via3 by < 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm") +v34c_l1.forget + +v3_4c_1.forget +v3_4c_2.forget +v3_4c_3.forget +# rule V3.4d is not a DRC check + +# rule V3.5 is not a DRC check + + +end #BEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via4.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via4.drc new file mode 100644 index 000000000..1b95644dc --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via4.drc @@ -0,0 +1,313 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (VIA4) ------------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +metal4 = polygons(46 , 0 ) +via4 = polygons(41 , 0 ) +metal5 = polygons(81 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#----------------------VIA4---------------------- +#================================================ + + +if BEOL +logger.info("BEOL section") + +# Rule V4.1: Min/max Via4 size . is 0.26µm +logger.info("Executing rule V4.1") +v41_l1 = via4.edges.without_length(0.26.um).extended(0, 0, 0.001, 0.001) +v41_l1.output("V4.1", "V4.1 : Min/max Via4 size . : 0.26µm") +v41_l1.forget + +# Rule V4.2a: min. via4 spacing is 0.26µm +logger.info("Executing rule V4.2a") +v42a_l1 = via4.space(0.26.um, euclidian).polygons(0.001) +v42a_l1.output("V4.2a", "V4.2a : min. via4 spacing : 0.26µm") +v42a_l1.forget + +merged_via4 = via4.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal4) +via4_mask = merged_via4.size(1).not(via4).with_holes(16, nil) +selected_via4 = via4.interacting(via4_mask) +# Rule V4.2b: Via4 Space in 4x4 or larger Vian array is 0.36µm +logger.info("Executing rule V4.2b") +v42b_l1 = selected_via4.space(0.36.um, euclidian).polygons(0.001) +v42b_l1.output("V4.2b", "V4.2b : Via4 Space in 4x4 or larger Vian array : 0.36µm") +v42b_l1.forget + +merged_via4.forget +via4_mask.forget +selected_via4.forget +# rule V4.3a is not a DRC check + +# Rule V4.3b: metal4 overlap of via4. +logger.info("Executing rule V4.3b") +v43b_l1 = metal4.enclosing(via4, 0.01.um, euclidian).polygons(0.001).or(via4.not(metal4)) +v43b_l1.output("V4.3b", "V4.3b : metal4 overlap of via4.") +v43b_l1.forget + +v4p3c_cond = metal4.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v4p3c_eol = metal4.edges.with_length(nil, 0.34.um).interacting(v4p3c_cond.first_edges).interacting(v4p3c_cond.second_edges).not(v4p3c_cond.first_edges).not(v4p3c_cond.second_edges) +# Rule V4.3c: metal4 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V4.3c") +v43c_l1 = v4p3c_eol.enclosing(via4.edges,0.06.um, projection).polygons(0.001) +v43c_l1.output("V4.3c", "V4.3c : metal4 (< 0.34um) end-of-line overlap. : 0.06µm") +v43c_l1.forget + +v4p3c_cond.forget +v4p3c_eol.forget +v4_3d_1 = via4.edges.interacting(via4.drc(enclosed(metal4, projection) < 0.04.um).edges.centers(0, 0.5)) +v4_3d_2 = via4.edges.interacting(via4.drc(0.04.um <= enclosed(metal4, projection) < 0.06.um).centers(0, 0.5)) +v4_3d_3 = v4_3d_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V4.3d: If metal4 overlap Vian by < 0.04um on one side, adjacent metal4 edges overlap. is 0.06µm +logger.info("Executing rule V4.3d") +v43d_l1 = v4_3d_2.not_in(v4_3d_1).interacting(v4_3d_1).or(v4_3d_1.interacting(v4_3d_3)).enclosed(metal4.edges, 0.06.um).polygons(0.001) +v43d_l1.output("V4.3d", "V4.3d : If metal4 overlap Vian by < 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm") +v43d_l1.forget + +v4_3d_1.forget +v4_3d_2.forget +v4_3d_3.forget +# rule V4.3e is not a DRC check + +# Rule V4.4a: metal5 overlap of via4. +logger.info("Executing rule V4.4a") +v44a_l1 = metal5.enclosing(via4, 0.01.um, euclidian).polygons(0.001).or(via4.not(metal5)) +v44a_l1.output("V4.4a", "V4.4a : metal5 overlap of via4.") +v44a_l1.forget + +v4p4b_cond = metal5.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v4p4b_eol = metal5.edges.with_length(nil, 0.34.um).interacting(v4p4b_cond.first_edges).interacting(v4p4b_cond.second_edges).not(v4p4b_cond.first_edges).not(v4p4b_cond.second_edges) +# Rule V4.4b: metal5 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V4.4b") +v44b_l1 = v4p4b_eol.enclosing(via4.edges,0.06.um, projection).polygons(0.001) +v44b_l1.output("V4.4b", "V4.4b : metal5 (< 0.34um) end-of-line overlap. : 0.06µm") +v44b_l1.forget + +v4p4b_cond.forget +v4p4b_eol.forget +v4_4c_1 = via4.edges.interacting(via4.drc(enclosed(metal5, projection) < 0.04.um).edges.centers(0, 0.5)) +v4_4c_2 = via4.edges.interacting(via4.drc(0.04.um <= enclosed(metal5, projection) < 0.06.um).centers(0, 0.5)) +v4_4c_3 = v4_4c_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V4.4c: If metal5 overlap via4 by < 0.04um on one side, adjacent metal5 edges overlap. is 0.06µm +logger.info("Executing rule V4.4c") +v44c_l1 = v4_4c_2.not_in(v4_4c_1).interacting(v4_4c_1).or(v4_4c_1.interacting(v4_4c_3)).enclosed(metal5.edges, 0.06.um).polygons(0.001) +v44c_l1.output("V4.4c", "V4.4c : If metal5 overlap via4 by < 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm") +v44c_l1.forget + +v4_4c_1.forget +v4_4c_2.forget +v4_4c_3.forget +# rule V4.4d is not a DRC check + +# rule V4.5 is not a DRC check + + +end #BEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via5.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via5.drc new file mode 100644 index 000000000..6ea3ec0bd --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/via5.drc @@ -0,0 +1,313 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (VIA5) ------------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +metal5 = polygons(81 , 0 ) +via5 = polygons(82 , 0 ) +metaltop = polygons(53 , 0 ) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#----------------------VIA5---------------------- +#================================================ + + +if BEOL +logger.info("BEOL section") + +# Rule V5.1: Min/max Via5 size . is 0.26µm +logger.info("Executing rule V5.1") +v51_l1 = via5.edges.without_length(0.26.um).extended(0, 0, 0.001, 0.001) +v51_l1.output("V5.1", "V5.1 : Min/max Via5 size . : 0.26µm") +v51_l1.forget + +# Rule V5.2a: min. via5 spacing is 0.26µm +logger.info("Executing rule V5.2a") +v52a_l1 = via5.space(0.26.um, euclidian).polygons(0.001) +v52a_l1.output("V5.2a", "V5.2a : min. via5 spacing : 0.26µm") +v52a_l1.forget + +merged_via5 = via5.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal5) +via5_mask = merged_via5.size(1).not(via5).with_holes(16, nil) +selected_via5 = via5.interacting(via5_mask) +# Rule V5.2b: Via5 Space in 4x4 or larger via5 array is 0.36µm +logger.info("Executing rule V5.2b") +v52b_l1 = selected_via5.space(0.36.um, euclidian).polygons(0.001) +v52b_l1.output("V5.2b", "V5.2b : Via5 Space in 4x4 or larger via5 array : 0.36µm") +v52b_l1.forget + +merged_via5.forget +via5_mask.forget +selected_via5.forget +# rule V5.3a is not a DRC check + +# Rule V5.3b: metal5 overlap of via5. +logger.info("Executing rule V5.3b") +v53b_l1 = metal5.enclosing(via5, 0.01.um, euclidian).polygons(0.001).or(via5.not(metal5)) +v53b_l1.output("V5.3b", "V5.3b : metal5 overlap of via5.") +v53b_l1.forget + +v5p3c_cond = metal5.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v5p3c_eol = metal5.edges.with_length(nil, 0.34.um).interacting(v5p3c_cond.first_edges).interacting(v5p3c_cond.second_edges).not(v5p3c_cond.first_edges).not(v5p3c_cond.second_edges) +# Rule V5.3c: metal5 (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V5.3c") +v53c_l1 = v5p3c_eol.enclosing(via5.edges,0.06.um, projection).polygons(0.001) +v53c_l1.output("V5.3c", "V5.3c : metal5 (< 0.34um) end-of-line overlap. : 0.06µm") +v53c_l1.forget + +v5p3c_cond.forget +v5p3c_eol.forget +v5_3d_1 = via5.edges.interacting(via5.drc(enclosed(metal5, projection) < 0.04.um).edges.centers(0, 0.5)) +v5_3d_2 = via5.edges.interacting(via5.drc(0.04.um <= enclosed(metal5, projection) < 0.06.um).centers(0, 0.5)) +v5_3d_3 = v5_3d_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V5.3d: If metal5 overlap via5 by < 0.04um on one side, adjacent metal5 edges overlap. is 0.06µm +logger.info("Executing rule V5.3d") +v53d_l1 = v5_3d_2.not_in(v5_3d_1).interacting(v5_3d_1).or(v5_3d_1.interacting(v5_3d_3)).enclosed(metal5.edges, 0.06.um).polygons(0.001) +v53d_l1.output("V5.3d", "V5.3d : If metal5 overlap via5 by < 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm") +v53d_l1.forget + +v5_3d_1.forget +v5_3d_2.forget +v5_3d_3.forget +# rule V5.3e is not a DRC check + +# Rule V5.4a: metaltop overlap of via5. +logger.info("Executing rule V5.4a") +v54a_l1 = metaltop.enclosing(via5, 0.01.um, euclidian).polygons(0.001).or(via5.not(metaltop)) +v54a_l1.output("V5.4a", "V5.4a : metaltop overlap of via5.") +v54a_l1.forget + +v5p4b_cond = metaltop.drc( width <= 0.34.um).with_length(0.28.um,nil,both) +v5p4b_eol = metaltop.edges.with_length(nil, 0.34.um).interacting(v5p4b_cond.first_edges).interacting(v5p4b_cond.second_edges).not(v5p4b_cond.first_edges).not(v5p4b_cond.second_edges) +# Rule V5.4b: metaltop (< 0.34um) end-of-line overlap. is 0.06µm +logger.info("Executing rule V5.4b") +v54b_l1 = v5p4b_eol.enclosing(via5.edges,0.06.um, projection).polygons(0.001) +v54b_l1.output("V5.4b", "V5.4b : metaltop (< 0.34um) end-of-line overlap. : 0.06µm") +v54b_l1.forget + +v5p4b_cond.forget +v5p4b_eol.forget +v5_4c_1 = via5.edges.interacting(via5.drc(enclosed(metaltop, projection) < 0.04.um).edges.centers(0, 0.5)) +v5_4c_2 = via5.edges.interacting(via5.drc(0.04.um <= enclosed(metaltop, projection) < 0.06.um).centers(0, 0.5)) +v5_4c_3 = v5_4c_1.extended(0, 0, 0, 0.001, joined).corners(90) +# Rule V5.4c: If metaltop overlap via5 by < 0.04um on one side, adjacent metaltop edges overlap. is 0.06µm +logger.info("Executing rule V5.4c") +v54c_l1 = v5_4c_2.not_in(v5_4c_1).interacting(v5_4c_1).or(v5_4c_1.interacting(v5_4c_3)).enclosed(metaltop.edges, 0.06.um).polygons(0.001) +v54c_l1.output("V5.4c", "V5.4c : If metaltop overlap via5 by < 0.04um on one side, adjacent metaltop edges overlap. : 0.06µm") +v54c_l1.forget + +v5_4c_1.forget +v5_4c_2.forget +v5_4c_3.forget +# rule V5.4d is not a DRC check + +# rule V5.5 is not a DRC check + + +end #BEOL + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/ymtp_mk.drc b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/ymtp_mk.drc new file mode 100644 index 000000000..8a2614d72 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/rule_decks/ymtp_mk.drc @@ -0,0 +1,316 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================================================================================================= +#----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (YMTP_MK) ----------------------------------------------------------- +#============================================================================================================================================================= + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +# optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb + +logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) + +if $input + if $topcell + source($input, $topcell) + else + source($input) + end +end + +logger.info("Loading database to memory is complete.") + +if $report + logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) + report("DRC Run Report at", $report) +else + logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) + report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) +end + +if $thr + logger.info("Number of threads to use %s" % [$thr]) + threads($thr) +else + logger.info("Number of threads to use 16") + threads(16) +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + +#================================================ +#------------- LAYERS DEFINITIONS --------------- +#================================================ + +v5_xtor = polygons(112, 1 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +otp_mk = polygons(173, 5 ) +plfuse = polygons(125, 5 ) +ymtp_mk = polygons(86 , 17) + +logger.info("Starting deriving base layers.") +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +ncomp = comp & nplus +pcomp = comp & pplus +tgate = poly2 & comp +ngate = nplus & tgate +pgate = pplus & tgate + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ +logger.info("Evaluate switches.") + +# FEOL +if $feol == "false" + FEOL = $feol + logger.info("FEOL is disabled.") +else + FEOL = "true" + logger.info("FEOL is enabled.") +end # FEOL + +# BEOL +if $beol == "false" + BEOL = $beol + logger.info("BEOL is disabled.") +else + BEOL = "true" + logger.info("BEOL is enabled.") +end # BEOL + +# connectivity rules +if $conn_drc == "true" + CONNECTIVITY_RULES = $conn_drc + logger.info("connectivity rules are enabled.") +else + CONNECTIVITY_RULES = false + logger.info("connectivity rules are disabled.") +end # connectivity rules + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +# WEDGE +if $wedge == "false" + WEDGE = $wedge +else + WEDGE = "true" +end # WEDGE + +logger.info("Wedge enabled %s" % [WEDGE]) + +# BALL +if $ball == "false" + BALL = $ball +else + BALL = "true" +end # BALL + +logger.info("Ball enabled %s" % [BALL]) + +# GOLD +if $gold == "false" + GOLD = $gold +else + GOLD = "true" +end # GOLD + +logger.info("Gold enabled %s" % [GOLD]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = "Nan" +end + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +# OFFGRID +if $offgrid == "false" + OFFGRID = false +else + OFFGRID = true +end # OFFGRID + +logger.info("Offgrid enabled %s" % [OFFGRID]) + +#================================================ +#--------------------YMTP_MK--------------------- +#================================================ + +# Rule Y.NW.2b_3.3V: Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. is 1µm +logger.info("Executing rule Y.NW.2b_3.3V") +ynw2b_l1 = nwell.outside(dnwell).inside(ymtp_mk).space(1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ynw2b_l1.output("Y.NW.2b_3.3V", "Y.NW.2b_3.3V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm") +ynw2b_l1.forget + +# Rule Y.NW.2b_5V: Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. is 1µm +logger.info("Executing rule Y.NW.2b_5V") +ynw2b_l1 = nwell.outside(dnwell).inside(ymtp_mk).space(1.um, euclidian).polygons(0.001).overlapping(dualgate) +ynw2b_l1.output("Y.NW.2b_5V", "Y.NW.2b_5V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm") +ynw2b_l1.forget + +# rule Y.DF.4d_3.3V is not a DRC check + +# rule Y.DF.4d_5V is not a DRC check + +# Rule Y.DF.6_5V: Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. is 0.15µm +logger.info("Executing rule Y.DF.6_5V") +ydf6_l1 = comp.not(otp_mk).inside(ymtp_mk).enclosing(poly2.inside(ymtp_mk), 0.15.um, euclidian).polygons(0.001).overlapping(dualgate) +ydf6_l1.output("Y.DF.6_5V", "Y.DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. : 0.15µm") +ydf6_l1.forget + +# Rule Y.DF.16_3.3V: Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). is 0.27µm +logger.info("Executing rule Y.DF.16_3.3V") +ydf16_l1 = ncomp.outside(nwell).outside(dnwell).separation(nwell.outside(dnwell), 0.27.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ydf16_l1.output("Y.DF.16_3.3V", "Y.DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.27µm") +ydf16_l1.forget + +# Rule Y.DF.16_5V: Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). is 0.23µm +logger.info("Executing rule Y.DF.16_5V") +ydf16_l1 = ncomp.outside(nwell).outside(dnwell).separation(nwell.outside(dnwell), 0.23.um, euclidian).polygons(0.001).overlapping(dualgate) +ydf16_l1.output("Y.DF.16_5V", "Y.DF.16_5V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.23µm") +ydf16_l1.forget + +# Rule Y.PL.1_3.3V: Interconnect Width (inside YMTP_MK). is 0.13µm +logger.info("Executing rule Y.PL.1_3.3V") +ypl1_l1 = poly2.outside(plfuse).and(ymtp_mk).width(0.13.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ypl1_l1.output("Y.PL.1_3.3V", "Y.PL.1_3.3V : Interconnect Width (inside YMTP_MK). : 0.13µm") +ypl1_l1.forget + +# Rule Y.PL.1_5V: Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V. +logger.info("Executing rule Y.PL.1_5V") +ypl1_l1 = poly2.outside(plfuse).and(ymtp_mk).overlapping(dualgate) +ypl1_l1.output("Y.PL.1_5V", "Y.PL.1_5V : Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V.") +ypl1_l1.forget + +# Rule Y.PL.2_3.3V: Gate Width (Channel Length) (inside YMTP_MK). is 0.13µm +logger.info("Executing rule Y.PL.2_3.3V") +ypl2_l1 = poly2.edges.and(tgate.edges).not(otp_mk).and(ymtp_mk).width(0.13.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ypl2_l1.output("Y.PL.2_3.3V", "Y.PL.2_3.3V : Gate Width (Channel Length) (inside YMTP_MK). : 0.13µm") +ypl2_l1.forget + +# Rule Y.PL.2_5V: Gate Width (Channel Length) (inside YMTP_MK). is 0.47µm +logger.info("Executing rule Y.PL.2_5V") +ypl2_l1 = poly2.edges.and(tgate.edges).not(otp_mk).and(ymtp_mk).width(0.47.um, euclidian).polygons(0.001).overlapping(dualgate) +ypl2_l1.output("Y.PL.2_5V", "Y.PL.2_5V : Gate Width (Channel Length) (inside YMTP_MK). : 0.47µm") +ypl2_l1.forget + +# Rule Y.PL.4_5V: Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). is 0.16µm +logger.info("Executing rule Y.PL.4_5V") +ypl4_l1 = poly2.and(ymtp_mk).enclosing(comp.and(ymtp_mk), 0.16.um, euclidian).polygons(0.001).overlapping(dualgate) +ypl4_l1.output("Y.PL.4_5V", "Y.PL.4_5V : Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). : 0.16µm") +ypl4_l1.forget + +# Rule Y.PL.5a_3.3V: Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). is 0.04µm +logger.info("Executing rule Y.PL.5a_3.3V") +ypl5a_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.04.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ypl5a_l1.output("Y.PL.5a_3.3V", "Y.PL.5a_3.3V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.04µm") +ypl5a_l1.forget + +# Rule Y.PL.5a_5V: Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). is 0.2µm +logger.info("Executing rule Y.PL.5a_5V") +ypl5a_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.2.um, euclidian).polygons(0.001).overlapping(dualgate) +ypl5a_l1.output("Y.PL.5a_5V", "Y.PL.5a_5V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.2µm") +ypl5a_l1.forget + +# Rule Y.PL.5b_3.3V: Space from field Poly2 to related COMP (inside YMTP_MK). is 0.04µm +logger.info("Executing rule Y.PL.5b_3.3V") +ypl5b_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.04.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) +ypl5b_l1.output("Y.PL.5b_3.3V", "Y.PL.5b_3.3V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.04µm") +ypl5b_l1.forget + +# Rule Y.PL.5b_5V: Space from field Poly2 to related COMP (inside YMTP_MK). is 0.2µm +logger.info("Executing rule Y.PL.5b_5V") +ypl5b_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.2.um, euclidian).polygons(0.001).overlapping(dualgate) +ypl5b_l1.output("Y.PL.5b_5V", "Y.PL.5b_5V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.2µm") +ypl5b_l1.forget + +# rule Y.PL.6_3.3V is not a DRC check + +# rule Y.PL.6_5V is not a DRC check + +# rule Y.LU.3_3.3V is not yet implemented + +# rule Y.LU.3_5V is not yet implemented + + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Run time %f seconds" % [run_time]) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/run_drc.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/run_drc.py new file mode 100644 index 000000000..9dde969dd --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/run_drc.py @@ -0,0 +1,260 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Run GlobalFoundries 180nm MCU DRC. + +Usage: + run_drc.py (--help| -h) + run_drc.py (--path=) (--gf180mcu=) [--topcell=] [--thr=] [--run_mode=] [--no_feol] [--no_beol] [--connectivity] [--density] [--density_only] [--antenna] [--antenna_only] [--no_offgrid] + +Options: + --help -h Print this help message. + --path= The input GDS file path. + --gf180mcu= Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C). + gf180mcu=A: Select metal_top=30K mim_option=A metal_level=3LM + gf180mcu=B: Select metal_top=11K mim_option=B metal_level=4LM + gf180mcu=C: Select metal_top=9K mim_option=B metal_level=5LM + --topcell= Topcell name to use. + --thr= The number of threads used in run. + --run_mode= Select klayout mode Allowed modes (flat , deep, tiling). [default: flat] + --no_feol Turn off FEOL rules from running. + --no_beol Turn off BEOL rules from running. + --connectivity Turn on connectivity rules. + --density Turn on Density rules. + --density_only Turn on Density rules only. + --antenna Turn on Antenna checks. + --antenna_only Turn on Antenna checks only. + --no_offgrid Turn off OFFGRID checking rules. +""" + +from docopt import docopt +import os +import xml.etree.ElementTree as ET +import logging +import subprocess + +def get_results(rule_deck,rules,lyrdb, type): + + mytree = ET.parse(f"{lyrdb}_{type}_gf{arguments['--gf180mcu']}.lyrdb") + myroot = mytree.getroot() + + violated = [] + + for lrule in rules: + # Loop on database to get the violations of required rule + for z in myroot[7]: + if f"'{lrule}'" == f"{z[1].text}": + violated.append(lrule) + break + + lyrdb_clean = lyrdb.split("/") [-1] + + if len(violated) > 0: + logging.error(f"\nTotal # of DRC violations in {rule_deck}.drc is {len(violated)}. Please check {lyrdb_clean}_{type}_gf{arguments['--gf180mcu']}.lyrdb file For more details") + logging.info("Klayout GDS DRC Not Clean") + logging.info(f"Violated rules are : {violated}\n") + else: + logging.info(f"\nCongratulations !!. No DRC Violations found in {lyrdb_clean} for {rule_deck}.drc rule deck with switch gf{arguments['--gf180mcu']}") + logging.info("Klayout GDS DRC Clean\n") + +def get_top_cell_names(gds_path): + # klayout -b -r script.rb -rd infile=./layouts/caravel.gds.gz + + pdk_root = os.environ['PDK_ROOT'] + pdk = os.environ['PDK'] + + top_cell_names = list() + proc = subprocess.Popen(['klayout','-b', '-r', f"{pdk_root}/{pdk}/utils/get_top_cell_names.rb", "-rd", "infile={}".format(gds_path)], stdout=subprocess.PIPE) + while True: + line = proc.stdout.readline() + if not line: + break + top_cell_names.append(line.decode().strip()) + + return top_cell_names + +def clean_gds_from_many_top_cells(gds_path, topcell): + # klayout -b -r keep_single_top_cell.rb -rd infile=./layouts/caravel.gds.gz -rd topcell=chip_io -rd outfile=test.gds.gz + + pdk_root = os.environ['PDK_ROOT'] + pdk = os.environ['PDK'] + + basename = os.path.basename(gds_path) + dirname = os.path.dirname(gds_path) + main_file_name = basename.split(".")[0] + output_file_path = os.path.join(dirname, "{}_single_top.gds.gz".format(main_file_name)) + + proc = subprocess.Popen(['klayout','-b', '-r', f"{pdk_root}/{pdk}/utils/keep_single_top_cell.rb", "-rd", "infile={}".format(gds_path), "-rd", "topcell={}".format(topcell), "-rd", "outfile={}".format(output_file_path)], stdout=subprocess.PIPE) + + while True: + line = proc.stdout.readline() + if not line: + break + print(line.strip()) + return output_file_path + +def main(): + + # check gds file existance + if os.path.exists(arguments["--path"]): + pass + else: + logging.error("The input GDS file path doesn't exist, please recheck.") + exit() + + # Env. variables + pdk_root = os.environ['PDK_ROOT'] + pdk = os.environ['PDK'] + + # ======= Checking Klayout version ======= + klayout_v_ = os.popen("klayout -v").read() + klayout_v_ = klayout_v_.split("\n")[0] + klayout_v = int (klayout_v_.split(".") [-1]) + + logging.info(f"Your Klayout version is: {klayout_v_}" ) + + if klayout_v < 8: + logging.info(f"Prerequisites at a minimum: KLayout 0.27.8") + logging.error("Using this klayout version has not been assesed in this development. Limits are unknown") + + # Switches used in run + switches = '' + + if arguments["--run_mode"] in ["flat" , "deep", "tiling"]: + switches = switches + f'-rd run_mode={arguments["--run_mode"]} ' + else: + logging.error("Allowed klayout modes are (flat , deep , tiling) only") + exit() + + if arguments["--gf180mcu"] == "A": switches = switches + f'-rd metal_top=30K -rd mim_option=A -rd metal_level=3LM ' + elif arguments["--gf180mcu"] == "B": switches = switches + f'-rd metal_top=11K -rd mim_option=B -rd metal_level=4LM ' + elif arguments["--gf180mcu"] == "C": switches = switches + f'-rd metal_top=9K -rd mim_option=B -rd metal_level=5LM ' + else: + logging.error("gf180mcu switch allowed values are (A , B, C) only") + exit() + + if arguments["--no_feol"]: switches = switches + '-rd feol=false ' + else: switches = switches + '-rd feol=true ' + + if arguments["--no_beol"]: switches = switches + '-rd beol=false ' + else: switches = switches + '-rd beol=true ' + + if arguments["--no_offgrid"]: switches = switches + '-rd offgrid=false ' + else: switches = switches + '-rd offgrid=true ' + + if arguments["--connectivity"]: switches = switches + '-rd conn_drc=true ' + else: switches = switches + '-rd conn_drc=false ' + + if arguments["--density"]: switches = switches + '-rd density=true ' + else: switches = switches + '-rd density=false ' + + # Generate databases + if arguments["--path"]: + path = arguments["--path"] + topcell_name = arguments["--topcell"] + + if ".gds" in path: + name_clean_= path.replace(".gds","") + name_clean = name_clean_.split("/")[-1] + + tc_list = get_top_cell_names(path) + if len(tc_list) < 2: + topcell_name = tc_list[0] + else: + print("## File has multiple topcell names") + # print("## File has multiple topcell names, must provide topcellname.") + # if topcell_name is None: + print("## Will have to stop.") + exit() + + # if not topcell_name is None: + switches = switches + f'-rd topcell={topcell_name}' + + # Removing old db + os.system(f"rm -rf {name_clean_}_main_drc_gf{arguments['--gf180mcu']}.lyrdb {name_clean_}_antenna_gf{arguments['--gf180mcu']}.lyrdb {name_clean_}_density_gf{arguments['--gf180mcu']}.lyrdb") + + # Running DRC using klayout + if (arguments["--antenna_only"]) and not (arguments["--density_only"]): + logging.info(f"Running Global Foundries 180nm MCU antenna checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_antenna.drc -rd input={path} -rd report={name_clean}_antenna_gf{arguments['--gf180mcu']}_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + + elif (arguments["--density_only"]) and not (arguments["--antenna_only"]): + logging.info(f"Running Global Foundries 180nm MCU density checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_density.drc -rd input={path} -rd report={name_clean}_density_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + + elif arguments["--antenna_only"] and arguments["--density_only"]: + logging.info(f"Running Global Foundries 180nm MCU antenna checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_antenna.drc -rd input={path} -rd report={name_clean}_antenna_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + + logging.info(f"Running Global Foundries 180nm MCU density checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_density.drc -rd input={path} -rd report={name_clean}_density_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + + else: + logging.info(f"Running main Global Foundries 180nm MCU runset on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu.drc -rd input={path} -rd report={name_clean}_main_drc_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + if arguments["--antenna"]: + logging.info(f"Running Global Foundries 180nm MCU antenna checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_antenna.drc -rd input={path} -rd report={name_clean}_antenna_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + if arguments["--density"]: + logging.info(f"Running Global Foundries 180nm MCU density checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_density.drc -rd input={path} -rd report={name_clean}_density_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + else: + logging.error("Script only support gds files, please select one") + exit() + else: + logging.error("No provided gds file, please add one") + exit() + + # ======================== Reporting results ======================== + rule_deck_path = [f"{pdk_root}/{pdk}/gf180mcu.drc" , f"{pdk_root}/{pdk}/gf180mcu_antenna.drc" , f"{pdk_root}/{pdk}/gf180mcu_density.drc"] + + # Get rules from rule deck + rules = [] + + # Get rules from rule deck + for runset in rule_deck_path: + with open(runset, 'r') as f: + for line in f: + if ".output" in line: + line_list = line.split('"') + if line_list[1] in rules: + pass + else: + rules.append(line_list[1]) + + # Get results + lyrdbs = [ "main_drc" , "antenna" , "density" ] + runsets = [ "gf180mcu" , "gf180mcu_antenna" , "gf180mcu_density"] + for i,lyrdb in enumerate(lyrdbs): + if os.path.exists(f"{name_clean_}_{lyrdb}_gf{arguments['--gf180mcu']}.lyrdb"): + get_results(runsets[i],rules,name_clean_, lyrdb) + +# ================================================================ +# -------------------------- MAIN -------------------------------- +# ================================================================ + +if __name__ == "__main__": + + # logs format + logging.basicConfig(level=logging.DEBUG, format=f"%(asctime)s | %(levelname)-7s | %(message)s", datefmt='%d-%b-%Y %H:%M:%S') + + # arguments + arguments = docopt(__doc__, version='RUN DRC: 0.1') + + # No. of threads + thrCount = os.cpu_count()*2 if arguments["--thr"] == None else int(arguments["--thr"]) + + # Calling main function + main() diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/run_drc_parallel.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/run_drc_parallel.py new file mode 100644 index 000000000..57c0b1d3f --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/run_drc_parallel.py @@ -0,0 +1,317 @@ +######################################################### + +""" +Run Globalfoundries 180u DRC. + +Usage: + run_drc.py (--help| -h) + run_drc.py (--path=) (--gf180mcu=) [--topcell=] [--thr=] [--run_mode=] [--no_feol] [--no_beol] [--connectivity] [--density] [--density_only] [--antenna] [--antenna_only] [--no_offgrid] + +Options: + --help -h Print this help message. + --path= The input GDS file path. + --gf180mcu= Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C). + gf180mcu=A: Select metal_top=30K mim_option=A metal_level=3LM + gf180mcu=B: Select metal_top=11K mim_option=B metal_level=4LM + gf180mcu=C: Select metal_top=9K mim_option=B metal_level=5LM + --topcell= Topcell name to use. + --thr= The number of threads used in run. + --run_mode= Select klayout mode Allowed modes (flat , deep, tiling). [default: flat] + --no_feol Turn off FEOL rules from running. + --no_beol Turn off BEOL rules from running. + --connectivity Turn on connectivity rules. + --density Turn on Density rules. + --density_only Turn on Density rules only. + --antenna Turn on Antenna checks. + --antenna_only Turn on Antenna checks only. + --no_offgrid Turn off OFFGRID checking rules. +""" + +from docopt import docopt +import os +import xml.etree.ElementTree as ET +import logging +import subprocess +import concurrent.futures +# import logging +# from multiprocessing import Process, log_to_stderr + +def call_simulator(arg): + """ + It runs the simulator with the given rule deck and input file, and saves the output to a database + file + + :param rule_deck_path: The path to the rule deck file + :param path: The path to the GDS file you want to simulate + :param thrCount: number of threads to use + """ + os.system(arg) + +def combine_results(path, rule_decks): + name_clean_= path.replace(".gds","") + path_clean = '/'.join(name_clean_.split("/")[:-1]) + get_category = False + get_item = False + categories = [] + categories_block = [] + items = [] + + for i, rule_deck in enumerate(rule_decks): + if i == 0: continue + with open(f"{name_clean_}_main_drc_gf{arguments['--gf180mcu']}_{i}.lyrdb", 'r') as f: + for line in f: + if "" in line: get_category = False + if get_category == True: categories.append(line) + if "" in line: get_category = True + if "" in line: get_item = False + if get_item == True: items.append(line) + if "" in line: get_item = True + categories = categories[1:-1] + categories_block.append(''.join(categories)) + categories = [] + + with open(f"{name_clean_}_main_drc_gf{arguments['--gf180mcu']}_{0}.lyrdb", "r") as f: + contents = f.readlines() + contents.insert(9, ''.join(categories_block)) + contents.insert(-2, ''.join(items)) + + with open(f"{name_clean_}_main_drc_gf{arguments['--gf180mcu']}.lyrdb", "w") as f: + f.writelines(contents) + + os.system(f"rm -rf {name_clean_}_main_drc_gf{arguments['--gf180mcu']}_*") + os.system(f"mkdir {path_clean}/logs") + os.system(f"mv *.log {path_clean}/logs") + +def get_results(rule_deck,rules,lyrdb, type): + + mytree = ET.parse(f"{lyrdb}_{type}_gf{arguments['--gf180mcu']}.lyrdb") + myroot = mytree.getroot() + + violated = [] + + for lrule in rules: + # Loop on database to get the violations of required rule + for z in myroot[7]: + if f"'{lrule}'" == f"{z[1].text}": + violated.append(lrule) + break + + lyrdb_clean = lyrdb.split("/") [-1] + + if len(violated) > 0: + logging.error(f"\nTotal # of DRC violations in {rule_deck}.drc is {len(violated)}. Please check {lyrdb_clean}_{type}_gf{arguments['--gf180mcu']}.lyrdb file For more details") + logging.info("Klayout GDS DRC Not Clean") + logging.info(f"Violated rules are : {violated}\n") + else: + logging.info(f"\nCongratulations !!. No DRC Violations found in {lyrdb_clean} for {rule_deck}.drc rule deck with switch gf{arguments['--gf180mcu']}") + logging.info("Klayout GDS DRC Clean\n") + +def get_top_cell_names(gds_path): + # klayout -b -r script.rb -rd infile=./layouts/caravel.gds.gz + + pdk_root = os.environ['PDK_ROOT'] + pdk = os.environ['PDK'] + + top_cell_names = list() + proc = subprocess.Popen(['klayout','-b', '-r', f"{pdk_root}/{pdk}/utils/get_top_cell_names.rb", "-rd", "infile={}".format(gds_path)], stdout=subprocess.PIPE) + while True: + line = proc.stdout.readline() + if not line: + break + top_cell_names.append(line.decode().strip()) + + return top_cell_names + +def clean_gds_from_many_top_cells(gds_path, topcell): + # klayout -b -r keep_single_top_cell.rb -rd infile=./layouts/caravel.gds.gz -rd topcell=chip_io -rd outfile=test.gds.gz + + pdk_root = os.environ['PDK_ROOT'] + pdk = os.environ['PDK'] + + basename = os.path.basename(gds_path) + dirname = os.path.dirname(gds_path) + main_file_name = basename.split(".")[0] + output_file_path = os.path.join(dirname, "{}_single_top.gds.gz".format(main_file_name)) + + proc = subprocess.Popen(['klayout','-b', '-r', f"{pdk_root}/{pdk}/utils/keep_single_top_cell.rb", "-rd", "infile={}".format(gds_path), "-rd", "topcell={}".format(topcell), "-rd", "outfile={}".format(output_file_path)], stdout=subprocess.PIPE) + + while True: + line = proc.stdout.readline() + if not line: + break + print(line.strip()) + return output_file_path + +def main(): + + # check gds file existance + if os.path.exists(arguments["--path"]): + pass + else: + logging.error("The input GDS file path doesn't exist, please recheck.") + exit() + + # Env. variables + pdk_root = os.environ['PDK_ROOT'] + pdk = os.environ['PDK'] + + # ======= Checking Klayout version ======= + klayout_v_ = os.popen("klayout -v").read() + klayout_v_ = klayout_v_.split("\n")[0] + klayout_v = int (klayout_v_.split(".") [-1]) + + logging.info(f"Your Klayout version is: {klayout_v_}" ) + + if klayout_v < 8: + logging.info(f"Prerequisites at a minimum: KLayout 0.27.8") + logging.error("Using this klayout version has not been assesed in this development. Limits are unknown") + + # Switches used in run + switches = '' + runs = [] + + if arguments["--run_mode"] in ["flat" , "deep", "tiling"]: + switches = switches + f'-rd run_mode={arguments["--run_mode"]} ' + else: + logging.error("Allowed klayout modes are (flat , deep , tiling) only") + exit() + + if arguments["--gf180mcu"] == "A": switches = switches + f'-rd metal_top=30K -rd mim_option=A -rd metal_level=3LM ' + elif arguments["--gf180mcu"] == "B": switches = switches + f'-rd metal_top=11K -rd mim_option=B -rd metal_level=4LM ' + elif arguments["--gf180mcu"] == "C": switches = switches + f'-rd metal_top=9K -rd mim_option=B -rd metal_level=5LM ' + else: + logging.error("gf180mcu switch allowed values are (A , B, C) only") + exit() + + if arguments["--no_feol"]: switches = switches + '-rd feol=false ' + else: switches = switches + '-rd feol=true ' + + if arguments["--no_beol"]: switches = switches + '-rd beol=false ' + else: switches = switches + '-rd beol=true ' + + if arguments["--no_offgrid"]: switches = switches + '-rd offgrid=false ' + else: switches = switches + '-rd offgrid=true ' + + if arguments["--connectivity"]: switches = switches + '-rd conn_drc=true ' + else: switches = switches + '-rd conn_drc=false ' + + if arguments["--density"]: switches = switches + '-rd density=true ' + else: switches = switches + '-rd density=false ' + + # Generate databases + if arguments["--path"]: + path = arguments["--path"] + topcell_name = arguments["--topcell"] + + if ".gds" in path: + name_clean_= path.replace(".gds","") + name_clean = name_clean_.split("/")[-1] + + tc_list = get_top_cell_names(path) + if len(tc_list) < 2: + topcell_name = tc_list[0] + else: + print("## File has multiple topcell names") + # print("## File has multiple topcell names, must provide topcellname.") + # if topcell_name is None: + print("## Will have to stop.") + exit() + + # if not topcell_name is None: + switches = switches + f'-rd topcell={topcell_name}' + + # Removing old db + os.system(f"rm -rf {name_clean_}_main_drc_gf{arguments['--gf180mcu']}.lyrdb {name_clean_}_antenna_gf{arguments['--gf180mcu']}.lyrdb {name_clean_}_density_gf{arguments['--gf180mcu']}.lyrdb") + + # Running DRC using klayout + if (arguments["--antenna_only"]) and not (arguments["--density_only"]): + logging.info(f"Running Global Foundries 180nm MCU antenna checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_antenna.drc -rd input={path} -rd report={name_clean}_antenna_gf{arguments['--gf180mcu']}_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + + elif (arguments["--density_only"]) and not (arguments["--antenna_only"]): + logging.info(f"Running Global Foundries 180nm MCU density checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_density.drc -rd input={path} -rd report={name_clean}_density_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + + elif arguments["--antenna_only"] and arguments["--density_only"]: + logging.info(f"Running Global Foundries 180nm MCU antenna checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_antenna.drc -rd input={path} -rd report={name_clean}_antenna_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + + logging.info(f"Running Global Foundries 180nm MCU density checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_density.drc -rd input={path} -rd report={name_clean}_density_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + + else: + logging.info(f"Running main Global Foundries 180nm MCU runset on design {name_clean} on cell {topcell_name}:") + rule_decks = os.listdir(f"{os.environ['PDK_ROOT']}/{os.environ['PDK']}/rule_decks/") + for i, rule_deck in enumerate(rule_decks): + #os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu.drc -rd input={path} -rd report={name_clean}_main_drc_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + arg = f"klayout -b -r $PDK_ROOT/$PDK/rule_decks/{rule_deck} -rd input={path} -rd report={name_clean}_main_drc_gf{arguments['--gf180mcu']}_{i}.lyrdb -rd thr={thrCount} {switches} | tee {rule_deck}.log" + runs.append(arg) + + with concurrent.futures.ProcessPoolExecutor(max_workers=thrCount) as executor: + for run in runs: + executor.submit(call_simulator, run) + + # log_to_stderr(logging.DEBUG) + + # # Start the process. + # for run in runs: + # process = Process(target=call_simulator, args=(f"{run}",)) + # process.start() + # process.join() + + combine_results(path, rule_decks) + + if arguments["--antenna"]: + logging.info(f"Running Global Foundries 180nm MCU antenna checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_antenna.drc -rd input={path} -rd report={name_clean}_antenna_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + if arguments["--density"]: + logging.info(f"Running Global Foundries 180nm MCU density checks on design {name_clean} on cell {topcell_name}:") + os.system(f"klayout -b -r $PDK_ROOT/$PDK/gf180mcu_density.drc -rd input={path} -rd report={name_clean}_density_gf{arguments['--gf180mcu']}.lyrdb -rd thr={thrCount} {switches}") + else: + logging.error("Script only support gds files, please select one") + exit() + else: + logging.error("No provided gds file, please add one") + exit() + + # ======================== Reporting results ======================== + rule_deck_path = [f"{pdk_root}/{pdk}/gf180mcu.drc" , f"{pdk_root}/{pdk}/gf180mcu_antenna.drc" , f"{pdk_root}/{pdk}/gf180mcu_density.drc"] + + # Get rules from rule deck + rules = [] + + # Get rules from rule deck + for runset in rule_deck_path: + with open(runset, 'r') as f: + for line in f: + if ".output" in line: + line_list = line.split('"') + if line_list[1] in rules: + pass + else: + rules.append(line_list[1]) + + # Get results + lyrdbs = [ "main_drc" , "antenna" , "density" ] + runsets = [ "gf180mcu" , "gf180mcu_antenna" , "gf180mcu_density"] + for i,lyrdb in enumerate(lyrdbs): + if os.path.exists(f"{name_clean_}_{lyrdb}_gf{arguments['--gf180mcu']}.lyrdb"): + get_results(runsets[i],rules,name_clean_, lyrdb) + +# ================================================================ +# -------------------------- MAIN -------------------------------- +# ================================================================ + +if __name__ == "__main__": + + # logs format + logging.basicConfig(level=logging.DEBUG, format=f"%(asctime)s | %(levelname)-7s | %(message)s", datefmt='%d-%b-%Y %H:%M:%S') + + # arguments + arguments = docopt(__doc__, version='RUN DRC: 0.1') + + # No. of threads + thrCount = os.cpu_count()*2 if arguments["--thr"] == None else int(arguments["--thr"]) + + # Calling main function + main() \ No newline at end of file diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/utils/get_top_cell_names.rb b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/utils/get_top_cell_names.rb new file mode 100644 index 000000000..28ed59f81 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/utils/get_top_cell_names.rb @@ -0,0 +1,33 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +layout = RBA::Layout::new +layout.read($infile) + +#puts "Topcell names" + +for t in layout.top_cells + # puts "Top cells " + t.name + puts t.name +end + +#File.open($outfile,) do |file| +# file.puts "Top cell: " + layout.top_cell.name +# file.puts "Layers:" +# layout.layer_indices.each do |layer_id| +# layer_info = layout.get_info(layer_id) +# file.puts layer_info.to_s +# end +#end + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/utils/keep_single_top_cell.rb b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/utils/keep_single_top_cell.rb new file mode 100644 index 000000000..8670331e7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/drc/utils/keep_single_top_cell.rb @@ -0,0 +1,31 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +layout = RBA::Layout::new +layout.read($infile) + +puts "Topcell names" + +for t in layout.top_cells + if t.name != $topcell + puts "Delete topcell as it's not used for running " + t.name + layout.prune_cell(t.cell_index, -1) + else + puts "Keep topcell " + t.name + end +end + +layout.write($outfile) + + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/gf180mcu.lyp b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/gf180mcu.lyp new file mode 100644 index 000000000..356931914 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/gf180mcu.lyp @@ -0,0 +1,3262 @@ + + + + #55ce57 + #55ce57 + 0 + 0 + I3 + + true + true + false + 1 + false + false + 0 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...*...*...*...* + ..*...*...*...*. + .*...*...*...*.. + *...*...*...*... + + 8 + slash + + + + *...*...*...*... + .*...*...*...*.. + ..*...*...*...*. + ...*...*...*...* + *...*...*...*... + .*...*...*...*.. + ..*...*...*...*. + ...*...*...*...* + *...*...*...*... + .*...*...*...*.. + ..*...*...*...*. + ...*...*...*...* + *...*...*...*... + .*...*...*...*.. + ..*...*...*...*. + ...*...*...*...* + + 9 + backSlash + + + + **......**...... + ..*.......*..... + ...**......**... + .....*.......*.. + ......**......** + *.......*....... + .**......**..... + ...*.......*.... + ....**......**.. + ......*.......*. + *......**......* + .*.......*...... + ..**......**.... + ....*.......*... + .....**......**. + .......*.......* + + 10 + hZigZag + + + + *....*....*..... + *.....*....*.... + .*....*.....*... + ..*....*....*... + ..*.....*....*.. + ...*....*.....*. + ....*....*....*. + ....*.....*....* + *....*....*..... + *.....*....*.... + .*....*.....*... + ..*....*....*... + ..*.....*....*.. + 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................ + + 20 + Xtwo + + + + ................ + ................ + ......*.......*. + ................ + ................ + ................ + ..*.......*..... + ................ + ................ + ................ + ......*.......*. + ................ + ................ + ................ + ..*.......*..... + ................ + + 21 + spareDots + + + + ................ + ................ + ................ + ................ + ................ + ......*.......*. + ................ + ................ + ................ + ................ + ................ + ................ + ..*.......*..... + ................ + ................ + ................ + + 22 + spareDots21 + + + + ................ + ................ + ......*.......*. + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ..*.......*..... + ................ + ................ + ................ + ................ + ................ + + 23 + spareDots22 + + + + ****....****.... + ****....****.... + ****....****.... + ****....****.... + ....****....**** + ....****....**** + ....****....**** + ....****....**** + ****....****.... + ****....****.... + ****....****.... + ****....****.... + ....****....**** + ....****....**** + ....****....**** + ....****....**** + + 24 + checker + + + + ....****....**** + ....****....**** + ....****....**** + ....****....**** + ****....****.... + ****....****.... + ****....****.... + ****....****.... + ....****....**** + ....****....**** + ....****....**** + ....****....**** + ****....****.... + ****....****.... + ****....****.... + ****....****.... + + 25 + checker2 + + + + ................ + ................ + ................ + ................ + .......*........ + ......**........ + .......*........ + .......*........ + .......*........ + .......*........ + ......***....... + ................ + ................ + ................ + ................ + ................ + + 26 + one + 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................ + ................ + ......***....... + .....*...*...... + .....*...*...... + ......***....... + .....*...*...... + .....*...*...... + ......***....... + ................ + ................ + ................ + ................ + ................ + + 33 + eight + + + + *..............* + .*............*. + ..*..........*.. + ...*........*... + ....*......*.... + .....*....*..... + ......*..*...... + .......**....... + .......**....... + ......*..*...... + .....*....*..... + ....*......*.... + ...*........*... + ..*..........*.. + .*............*. + *..............* + + 34 + box45 + + + + .*.*.*.*.*.*.*.* + *.*.*.*.*.*.*.*. + .*.*.*.*.*.*.*.* + *.*.*.*.*.*.*.*. + .*.*.*.*.*.*.*.* + *.*.*.*.*.*.*.*. + .*.*.*.*.*.*.*.* + *.*.*.*.*.*.*.*. + .*.*.*.*.*.*.*.* + *.*.*.*.*.*.*.*. + .*.*.*.*.*.*.*.* + *.*.*.*.*.*.*.*. + .*.*.*.*.*.*.*.* + *.*.*.*.*.*.*.*. + .*.*.*.*.*.*.*.* + *.*.*.*.*.*.*.*. + + 35 + gray50 + + + + *...*...*...*... + ................ + ..*...*...*...*. + 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..*.*.....*.*... + .*...*...*...*.. + *.....*.*.....*. + ...*...*...*...* + *.....*.*.....*. + .*...*...*...*.. + ..*.*.....*.*... + ...*...*...*...* + ..*.*.....*.*... + .*...*...*...*.. + *.....*.*.....*. + ...*...*...*...* + + 39 + lattice + + + + **..**..**..**.. + **..**..**..**.. + ..**..**..**..** + ..**..**..**..** + **..**..**..**.. + **..**..**..**.. + ..**..**..**..** + ..**..**..**..** + **..**..**..**.. + **..**..**..**.. + ..**..**..**..** + ..**..**..**..** + **..**..**..**.. + **..**..**..**.. + ..**..**..**..** + ..**..**..**..** + + 40 + smallChecker + + + + ....*........... + ...*.*.......... + ..*...*......... + .*.....*........ + *.......*....... + .*.......*...... + ..*.......*..... + ...*.......*.... + ....*.......*... + .....*.......*.. + ......*.......*. + .......*.......* + ........*.....*. + .........*...*.. + ..........*.*... + ...........*.... + + 41 + slantBox + + + + .*...*...*...*.. + *...*...*...*... + ...*...*...*...* + ..*...*...*...*. + .*...*...*...*.. + *...*...*...*... + ...*...*...*...* + ..*...*...*...*. + .*...*...*...*.. + *...*...*...*... + ...*...*...*...* + ..*...*...*...*. + .*...*...*...*.. + *...*...*...*... + ...*...*...*...* + ..*...*...*...*. + + 42 + slash2 + + + + ...*.......*.... + ..*.......*..... + .*.......*...... + *.......*....... + .......*.......* + ......*.......*. + .....*.......*.. + ....*.......*... + ...*.......*.... + ..*.......*..... + .*.......*...... + *.......*....... + .......*.......* + ......*.......*. + .....*.......*.. + ....*.......*... + + 43 + bigSlash + + + + ****....****.... + *..*....*..*.... + *..*....*..*.... + ****....****.... + ................ + ................ + ................ + ................ + ****....****.... + *..*....*..*.... + *..*....*..*.... + ****....****.... + ................ + ................ + ................ + ................ + + 44 + boxes + + + + ..**......**.... + .*..*....*..*... + *....*..*....*.. + *....*..*....*.. + .*..*....*..*... + ..**......**.... + ................ + ................ + ..**......**.... + .*..*....*..*... + *....*..*....*.. + *....*..*....*.. + .*..*....*..*... + ..**......**.... + ................ + ................ + + 45 + circles + + + + .**..**..**..**. + ...*...*...*...* + *...*...*...*... + .**..**..**..**. + .**..**..**..**. + *...*...*...*... + ...*...*...*...* + .**..**..**..**. + .**..**..**..**. + ...*...*...*...* + *...*...*...*... + .**..**..**..**. + .**..**..**..**. + *...*...*...*... + ...*...*...*...* + .**..**..**..**. + + 46 + zigzag + + + + ................ + *.*.*.*.*.*.*.*. + ................ + ...*....*....*.. + ................ + *.*.*.*.*.*.*.*. + ................ + ...*....*....*.. + ................ + *.*.*.*.*.*.*.*. + ................ + ...*....*....*.. + ................ + *.*.*.*.*.*.*.*. + ................ + ...*....*....*.. + + 47 + lightMesh + + + + ...............* + ..............*. + .............*.. + ............*... + ...........*.... + ..........*..... + .........*...... + ........*....... + .......*........ + ......*......... + .....*.......... + ....*........... + ...*............ + ..*............. + .*.............. + *............... + + 48 + hugeSlash + + + + *............... + .*.............. + ..*............. + ...*............ + ....*........... + .....*.......... + ......*......... + .......*........ + ........*....... + .........*...... + ..........*..... + ...........*.... + ............*... + .............*.. + ..............*. + ...............* + + 49 + hugeSlash2 + + + + *.........*..... + .....*.......... + ..*.........*... + .......*........ + ....*.........*. + .*.......*...... + ......*......... + ...*.......*.... + ........*....... + .....*.......*.. + *.........*..... + .......*........ + ..*.........*... + .........*...... + ....*.........*. + ...........*.... + + 50 + curve + + + + ....*....*....*. + ..*............. + *.......*....... + .............*.. + .......*........ + ............*... + .....*.......... + ...*.......*.... + *............... + ................ + .........*...... + ................ + ......*........* + ...*............ + *............*.. + ..........*..... + + 51 + curve2 + + + + ...........*.... + ..........*.*... + .........*...*.. + ........*.....*. + .........*...*.. + ..........*.*... + ...........*.... + ................ + ................ + ...*............ + ..*.*........... + .*...*.......... + *.....*......... + .*...*.......... + ..*.*........... + ...*............ + + 52 + diams + + + + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ...*............ + ..*.*........... + .*...*.......... + *.....*......... + .*...*.......... + ..*.*........... + ...*............ + + 53 + sparsediam + + + + .......*.......* + ......*......... + .....*.......... + ................ + ................ + ................ + .*.............. + *............... + .......*.......* + ..............*. + .............*.. + ................ + ................ + ................ + .........*...... + ........*....... + + 54 + rain + + + + * + + 55 + + + + *** + 1 + solid + + + ****.. + 2 + dashed + + + *.. + 3 + dots + + + ***..*.. + 4 + dashDot + + + **.. + 5 + shortDash + + + ****..**.. + 6 + doubleDash + + + *... + 7 + hidden + + + + 8 + + + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/gf180mcu.lyt b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/gf180mcu.lyt new file mode 100644 index 000000000..c5959dcdc --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/gf180mcu.lyt @@ -0,0 +1,233 @@ + + + + gf180mcu + GLOBALFOUNDRIES 0.18UM 3.3V/(5V)6V MCU TECHNOLOGY + + 0.001 + + $PDK_ROOT/$PDK/libs.tech/klayout + gf180mcu.lyp + true + + + 1 + true + true + + + true + layer_map() + true + true + + + true + layer_map() + 0.001 + true + #1 + true + #1 + false + #1 + true + OUTLINE + true + PLACEMENT_BLK + true + REGIONS + true + + 0 + true + .PIN + 2 + true + .PIN + 2 + true + .FILL + 5 + true + .OBS + 3 + true + .BLK + 4 + true + .LABEL + 1 + true + .LABEL + 1 + true + + 0 + true + + 0 + VIA_ + true + default + false + + + + false + true + true + 64 + 0 + 1 + 0 + DATA + 0 + 0 + BORDER + layer_map() + true + + + 0.001 + 1 + 100 + 100 + 0 + 0 + 0 + false + false + false + true + layer_map() + + + 0 + 0.001 + layer_map() + true + false + + + 1 + 0.001 + layer_map() + true + false + true + + + + + + + true + false + false + false + false + false + 8000 + 32000 + LIB + + + 2 + false + false + 1 + * + false + + + 0 + + + false + false + + + 0 + + true + + + + # Provide z stack information here +# +# Each line is one layer. The specification consists of a layer specification, a colon and arguments. +# The arguments are named (like "x=...") or in serial. Parameters are separated by comma or blanks. +# Named arguments are: +# +# zstart The lower z position of the extruded layer in µm +# zstop The upper z position of the extruded layer in µm +# height The height of the extruded layer in µm +# +# 'height', 'zstart' and 'zstop' can be used in any combination. If no value is given for 'zstart', +# the upper level of the previous layer will be used. +# +# If a single unnamed parameter is given, it corresponds to 'height'. Two parameters correspond to +# 'zstart' and 'zstop'. +# +# Examples: +# 1: 0.5 1.5 # extrude layer 1/0 from 0.5 to 1.5 vertically +# 1/0: 0.5 1.5 # same with explicit datatype +# 1: zstop=1.5, zstart=0.5 # same with named parameters +# 1: height=1.0, zstop=1.5 # same with z stop minus height +# 1: 1.0 zstop=1.5 # same with height as unnamed parameter +# +# VARIABLES +# +# You can declare variables with: +# var name = value +# +# You can use variables inside numeric expressions. +# Example: +# var hmetal = 0.48 +# 7/0: 0.5 0.5+hmetal*2 # 2x thick metal +# +# You cannot use variables inside layer specifications currently. +# +# CONDITIONALS +# +# You can enable or disable branches of the table using 'if', 'else', 'elseif' and 'end': +# Example: +# var thick_m1 = true +# if thickm1 +# 1: 0.5 1.5 +# else +# 1: 0.5 1.2 +# end + + + + + 30/0,33/0,Metal1 + Metal1,35/0,Metal2 + Metal2,38/0,Metal3 + Metal3,40/0,Metal4 + Metal4,41/0,Metal5 + Metal5,82/0,53/0 + + Metal1='34/0+34/10' + Metal2='36/0+36/10' + Metal3='42/0+42/10' + Metal4='46/0+46/10' + Metal5='81/0+81/10' + + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/lvs/README.md b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/lvs/README.md new file mode 100644 index 000000000..e63d241b5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/lvs/README.md @@ -0,0 +1,81 @@ +# LVS Documentation + +Explains how to use the runset. + +## Folder Structure + +```text +📦runset + ┣ 📦testing + ┣ 📜README.md + ┣ 📜gf_018mcu.lvs + ┣ 📜gf_018mcu.lyp + ┗ 📜run_lvs.py + ``` + +## Rule Deck Usage + +The `run_lvs.py` script takes a gds file and a netlist to run LVS rule deck of GF180 technology with switches to select subsets of all checks. + +### **Switches** + +1. **GF180MCU**=A : combined options of metal_level=3, mim_option=A, metal_top=30K, poly_res=1K, and mim_cap=2 +2. **GF180MCU**=B : combined options of metal_level=4, mim_option=B, metal_top=11K, poly_res=1K, and mim_cap=2 +3. **GF180MCU**=C : combined options of metal_level=5, mim_option=B, metal_top=9K, poly_res=1K, and mim_cap=2 + +### Usage + +```bash + run_lvs.py (--help| -h) + run_lvs.py (--design=) (--net=) (--gf180mcu=) [--thr=] [--run_mode=] [--metal_top=] [--mim_option=] [--metal_level=] [--poly_res_val=] [--mim_cap_val=] [--no_net_names] [--set_spice_comments] [--set_scale] [--set_verbose] [--set_schematic_simplify] [--set_net_only] [--set_top_lvl_pins] [--set_combine] [--set_purge] [--set_purge_nets] +``` + +Example: + +```bash + python3 run_lvs.py --path=testing/extraction_checking/sample_nmos_3p3.gds --net=sample_nmos_3p3.spice --thr=16 --gf180mcu=B --set_verbose --set_spice_comments +``` + +### Options + +`--help -h` Print this help message. + +`--design=` The input GDS file path. + +`--net=` The input netlist file path. + +`--thr=` The number of threads used in run. + +`run_mode=` Select klayout mode Allowed modes (flat , deep, tiling). [default: flat] + +`--gf180mcu=` Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C). + +`--no_net_names` Discard net names in extracted netlist. + +`--set_spice_comments` Set netlist comments in extracted netlist. + +`--set_scale` Set scale of 1e6 in extracted netlist. + +`--set_verbose` Set verbose mode. + +`--set_schematic_simplify` Set schematic simplification in input netlist. + +`--set_net_only` Set netlist object creation only in extracted netlist. + +`--set_top_lvl_pins` Set top level pins only in extracted netlist. + +`--set_combine` Set netlist combine only in extracted netlist. + +`--set_purge` Set netlist purge all only in extracted netlist. + +`--set_purge_nets` Set netlist purge nets only in extracted netlist. + +### **LVS Outputs** + +Final results will appear at the end of the run logs. + +The output files are : + +1. An extracted netlist (`.cir`). + +2. Database file (`..lvdb`) for comparison results. you could view it on your file using klayout. diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/lvs/gf180mcu.lvs b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/lvs/gf180mcu.lvs new file mode 100644 index 000000000..9a7c6068f --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/lvs/gf180mcu.lvs @@ -0,0 +1,1923 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#=========================================================================================================================== +#------------------------------------------- GF 0.18um MCU LVS RULE DECK -------------------------------------------------- +#=========================================================================================================================== + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} +" +end + +#================================================ +#----------------- FILE SETUP ------------------- +#================================================ + +logger.info("Starting running GF180MCU Klayout LVS runset on %s" % [$input]) + +#=== GET LAYOUT === +if $input + source($input) + logger.info("Layout file: #{$input}") +else + logger.info("No layout loaded, please add your layout file") +end + +#=== GET THREADS === +if $thr + threads($thr) + logger.info("Number of threads: #{$thr}") +else + threads(16) + logger.info("Number of threads: 16") +end + +#=== GET REPORT === +if $report + report_lvs($report) + logger.info("Final report: #{$report}") +else + report_lvs(source.cell_name+".lvsdb") + logger.info("Final report: #{source.cell_name}.lvsdb") +end + +#=== GET SUBSTRATE NAME === +if $lvs_sub + substrate_name = $lvs_sub + logger.info("Substrate name: #{$lvs_sub}") +else + substrate_name = "gf180mcu_gnd" + logger.info("No substrate name given, default name is gf180mcu_gnd") +end + +#=== NET NAMES OPTION === +# true: use net names instead of numbers +# false: use numbers for nets +if $spice_net_names == "true" + spice_with_net_names = true + logger.info("Extracted netlist with net names: #{$spice_net_names}") +else + spice_with_net_names = true + logger.info("Extracted netlist with net names: true") +end + +#=== COMMENTS OPTION === +# true: put in comments with details +# false: no comments +if $spice_comments == "true" + spice_with_comments = true + logger.info("Extracted netlist with comments in details: #{$spice_comments}") +else + spice_with_comments = false + logger.info("Extracted netlist with comments in details: false") +end + +if $target_netlist + target_netlist($target_netlist) + logger.info("Extracted netlist file: #{$target_netlist}") +else + target_netlist(File.join(File.dirname(RBA::CellView::active.filename), source.cell_name+"_extracted.cir"), write_spice(spice_with_net_names, spice_with_comments), "Extracted by KLayout with GF180 LVS runset on : #{Time.now.strftime("%d/%m/%Y %H:%M")}") + logger.info("Extracted netlist file: #{source.cell_name}_extracted.cir") +end + +#=== EXTRACTION SCALE === +if $scale == "true" + device_scaling(1000000) + logger.info("device_scaling: true") +else + logger.info("device_scaling: false") +end + +#=== PRINT DETAILS === +if $verbose == "true" + logger.info("Verbose mode: #{$verbose}") + verbose(true) +else + verbose(false) + logger.info("Verbose mode: false") +end + +# === TILING MODE === +if $run_mode == "tiling" + # use a tile size of 1mm - not used in deep mode- + # tiles(500.um) + # use a tile border of 10 micron: + # tile_borders(10.um) + tiles(1000) + logger.info("Tiling mode is enabled.") + +elsif $run_mode == "deep" + #=== HIER MODE === + deep + logger.info("deep mode is enabled.") + +elsif $run_mode == "flat" + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +else + #=== FLAT MODE === + flat + logger.info("flat mode is enabled.") + +end # run_mode + + +#================================================ +# --------------- CUSTOM CLASSES ---------------- +#================================================ + +#====================== CUSTOM READER ========================= +class SubcircuitModelsReader < RBA::NetlistSpiceReaderDelegate + + def parse_element(s, element) + if element == "C" + super(s + " C=2e-16", element) + elsif element == "R" + super(s + " R=0", element) + else + super + end + end + + # implements the delegate interface: + # take and translate the element + def element(circuit, el, name, model, value, nets, params) + + if el == "C" + if nets.size != 2 + error("Capacitor needs two nodes") + end + + # provide a device class + cls = circuit.netlist.device_class_by_name(model) + if ! cls + cls = RBA::DeviceClassCapacitor::new + cls.name = model + circuit.netlist.add(cls) + end + + # create a device + device = circuit.create_device(cls, name) + + # and configure the device + [ "A", "B" ].each_with_index do |t,index| + device.connect_terminal(t, nets[index]) + end + + # parameters in the model are given in micrometer units, so + # we need to translate the parameter values from SI to um values: + device.set_parameter("A", ((params["W"] || 0.0) * (params["L"] || 0.0)) * 1e12) + device.set_parameter("P", ((params["W"] || 0.0) + (params["L"] || 0.0)) * 2e6) + device.set_parameter("C", (params["C"] || 0.0)) + + elsif el == "R" + if nets.size == 3 + # provide a device class + cls = circuit.netlist.device_class_by_name(model) + if ! cls + cls = RBA::DeviceClassResistorWithBulk::new + cls.name = model + circuit.netlist.add(cls) + end + + # create a device + device = circuit.create_device(cls, name) + + # and configure the device + [ "A", "B", "W" ].each_with_index do |t,index| + device.connect_terminal(t, nets[index]) + end + + elsif nets.size == 2 + # provide a device class + cls = circuit.netlist.device_class_by_name(model) + if ! cls + cls = RBA::DeviceClassResistor::new + cls.name = model + circuit.netlist.add(cls) + end + + # create a device + device = circuit.create_device(cls, name) + + # and configure the device + [ "A", "B" ].each_with_index do |t,index| + device.connect_terminal(t, nets[index]) + end + + else + error("Resistor needs two or three nodes") + + end + + # parameters in the model are given in micrometer units, so + # we need to translate the parameter values from SI to um values: + device.set_parameter("W", ((params["W"] || 0.0) * (params["PAR"] || 1.0)) * 1e6) + device.set_parameter("L", ((params["L"] || 0.0) * (params["S"] || 1.0)) * 1e6) + device.set_parameter("R", (params["R"] * (params["S"] || 1.0) / (params["PAR"] || 1.0))) + + else + return super + + end + return true + + end + +end + +# Instantiate a reader using the new delegate +reader = RBA::NetlistSpiceReader::new(SubcircuitModelsReader::new) + +#=== GET NETLIST === +if $schematic + schematic($schematic, reader) + logger.info("Netlist file: #{$schematic}") +else + puts "No schematic loaded , please add your netlist file" + logger.info("No schematic loaded , please add your netlist file") +end + +class BResistor < RBA::DeviceClassResistorWithBulk + def initialize + super + enable_parameter("R", false) + enable_parameter("W", true) + enable_parameter("L", true) + end +end + +class NResistor < RBA::DeviceClassResistor + def initialize + super + enable_parameter("R", false) + enable_parameter("W", true) + enable_parameter("L", true) + end +end + +class MosCap < RBA::DeviceClassCapacitor + def initialize + super + enable_parameter("C", false) + enable_parameter("A", true) + enable_parameter("P", true) + end +end + +class MIMCap < RBA::DeviceClassCapacitor + def initialize + super + enable_parameter("C", true) + enable_parameter("A", true) + enable_parameter("P", true) + end +end + +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +logger.info("Read in polygons from layers.") + +#=== DRAWINGS === +comp = polygons(22 , 0 ) +dnwell = polygons(12 , 0 ) +nwell = polygons(21 , 0 ) +lvpwell = polygons(204, 0 ) +dualgate = polygons(55 , 0 ) +poly2 = polygons(30 , 0 ) +nplus = polygons(32 , 0 ) +pplus = polygons(31 , 0 ) +sab = polygons(49 , 0 ) +esd = polygons(24 , 0 ) +contact = polygons(33 , 0 ) +metal1 = polygons(34 , 0 ) +via1 = polygons(35 , 0 ) +metal2 = polygons(36 , 0 ) +via2 = polygons(38 , 0 ) +metal3 = polygons(42 , 0 ) +via3 = polygons(40 , 0 ) +metal4 = polygons(46 , 0 ) +via4 = polygons(41 , 0 ) +metal5 = polygons(81 , 0 ) +via5 = polygons(82 , 0 ) +metaltop = polygons(53 , 0 ) +pad = polygons(37 , 0 ) +resistor = polygons(62 , 0 ) +fhres = polygons(227, 0 ) +fusetop = polygons(75 , 0 ) +fusewindow_d = polygons(96 , 1 ) +polyfuse = polygons(220, 0 ) +mvsd = polygons(210, 0 ) +mvpsd = polygons(11 , 39) +nat = polygons(5 , 0 ) +comp_dummy = polygons(22 , 4 ) +poly2_dummy = polygons(30 , 4 ) +metal1_dummy = polygons(34 , 4 ) +metal2_dummy = polygons(36 , 4 ) +metal3_dummy = polygons(42 , 4 ) +metal4_dummy = polygons(46 , 4 ) +metal5_dummy = polygons(81 , 4 ) +metaltop_dummy = polygons(53 , 4 ) +metal1_slot = polygons(34 , 3 ) +metal2_slot = polygons(36 , 3 ) +metal3_slot = polygons(42 , 3 ) +metal4_slot = polygons(46 , 3 ) +metal5_slot = polygons(81 , 3 ) +metaltop_slot = polygons(53 , 3 ) +ubmpperi = polygons(183, 0 ) +ubmparray = polygons(184, 0 ) +ubmeplate = polygons(185, 0 ) +schottky_diode = polygons(241, 0 ) +zener = polygons(178, 0 ) +res_mk = polygons(110, 5 ) +opc_drc = polygons(124, 5 ) +ndmy = polygons(111, 5 ) +pmndmy = polygons(152, 5 ) +v5_xtor = polygons(112, 1 ) +cap_mk = polygons(117, 5 ) +mos_cap_mk = polygons(166, 5 ) +ind_mk = polygons(151, 5 ) +diode_mk = polygons(115, 5 ) +drc_bjt = polygons(127, 5 ) +lvs_bjt = polygons(118, 5 ) +mim_l_mk = polygons(117, 10) +latchup_mk = polygons(137, 5 ) +guard_ring_mk = polygons(167, 5 ) +otp_mk = polygons(173, 5 ) +mtpmark = polygons(122, 5 ) +neo_ee_mk = polygons(88 , 17) +sramcore = polygons(108, 5 ) +lvs_rf = polygons(100, 5 ) +lvs_drain = polygons(100, 7 ) +ind_mk = polygons(151, 5 ) +hvpolyrs = polygons(123, 5 ) +lvs_io = polygons(119, 5 ) +probe_mk = polygons(13 , 17) +esd_mk = polygons(24 , 5 ) +lvs_source = polygons(100, 8 ) +well_diode_mk = polygons(153, 51) +ldmos_xtor = polygons(226, 0 ) +plfuse = polygons(125, 5 ) +efuse_mk = polygons(80 , 5 ) +mcell_feol_mk = polygons(11 , 17) +ymtp_mk = polygons(86 , 17) +dev_wf_mk = polygons(128, 17) +metal1_blk = polygons(34 , 5 ) +metal2_blk = polygons(36 , 5 ) +metal3_blk = polygons(42 , 5 ) +metal4_blk = polygons(46 , 5 ) +metal5_blk = polygons(81 , 5 ) +metalt_blk = polygons(53 , 5 ) +pr_bndry = polygons(0 , 0 ) +mdiode = polygons(116, 5 ) +metal1_res = polygons(110, 11) +metal2_res = polygons(110, 12) +metal3_res = polygons(110, 13) +metal4_res = polygons(110, 14) +metal5_res = polygons(110, 15) +metal6_res = polygons(110, 16) +border = polygons(63 , 0 ) + +logger.info("Read in labels from layers.") + +#=== LABELS === +comp_label = labels(22 , 10) +poly2_label = labels(30 , 10) +metal1_label = labels(34 , 10) +metal2_label = labels(36 , 10) +metal3_label = labels(42 , 10) +metal4_label = labels(46 , 10) +metal5_label = labels(81 , 10) +metaltop_label = labels(53 , 10) + +#=== BULK LAYER === +sub = polygon_layer + +#================================================ +#------------------ SWITCHES -------------------- +#================================================ + +logger.info("Evaluate switches start.") + +# METAL_TOP +if $metal_top + METAL_TOP = $metal_top +else + METAL_TOP = "9K" +end # METAL_TOP + +logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) + +# METAL_LEVEL +if $metal_level + METAL_LEVEL = $metal_level +else + METAL_LEVEL = "6LM" +end # METAL_LEVEL + +logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) + +if $poly_res + POLY_RES = $poly_res +else + POLY_RES = false +end # POLY_RES + +logger.info("POLY_RES Selected is %s" % [POLY_RES]) + +if $mim_option + MIM_OPTION = $mim_option +else + MIM_OPTION = false +end # MIM_OPTION + +if $mim_cap + MIM_CAP = $mim_cap +else + MIM_CAP = false +end # MIM_CAP + +logger.info("MIM Option selected %s" % [MIM_OPTION]) + +if $schematic_simplify + SCH_SIMPLE = $schematic_simplify +else + SCH_SIMPLE = false +end # SCH_SIMPLE + +logger.info("SCH_SIMPLE enabled %s" % [SCH_SIMPLE]) + +if $net_only + NET_ONLY = true +else + NET_ONLY = false +end + +logger.info("NET_ONLY enabled %s" % [NET_ONLY]) + +if $top_lvl_pins + TOP_LVL_PINS = true +else + TOP_LVL_PINS = false +end + +logger.info("TOP_LVL_PINS enabled %s" % [TOP_LVL_PINS]) + + +if $combine + COMBINE = true +else + COMBINE = false +end + +logger.info("COMBINE enabled %s" % [COMBINE]) + +if $purge + PURGE = true +else + PURGE = false +end + +logger.info("PURGE enabled %s" % [PURGE]) + +if $purge_nets + PURGE_NETS = true +else + PURGE_NETS = false +end + +logger.info("PURGE_NETS enabled %s" % [PURGE_NETS]) + +if $net_only || $top_lvl_pins || $combine || $purge || $purge_nets + SIMPLIFY = false +else + SIMPLIFY = true +end # SIMPLIFY + +logger.info("SIMPLIFY enabled %s" % [SIMPLIFY]) + +logger.info("Evaluate switches end.") + +#================================================ +#------------- METAL LEVEL SWITCHES ------------- +#================================================ + +if METAL_LEVEL == "6LM" + top_via = via5 + topmin1_via = via4 + top_metal = metaltop + topmin1_metal = metal5 +elsif METAL_LEVEL == "5LM" + top_via = via4 + topmin1_via = via3 + top_metal = metal5 + topmin1_metal = metal4 +elsif METAL_LEVEL == "4LM" + top_via = via3 + topmin1_via = via2 + top_metal = metal4 + topmin1_metal = metal3 +elsif METAL_LEVEL == "3LM" + top_via = via2 + topmin1_via = via1 + top_metal = metal3 + topmin1_metal = metal2 +elsif METAL_LEVEL == "2LM" + top_via = via1 + topmin1_via = via1 + top_metal = metal2 + topmin1_metal = metal1 +end #METAL_LEVEL + +#================================================================ +#------------------------- MAIN RUNSET -------------------------- +#================================================================ + +logger.info("GF180 LVS rules started") + +#================================================ +#------------- LAYERS DERIVATIONS --------------- +#================================================ + +logger.info("Starting deriving base layers.") + +#================================== +# ------ GENERAL DERIVATIONS ------ +#================================== + +ncomp = comp.and(nplus) +pcomp = comp.and(pplus) +tgate = poly2.and(comp).not(res_mk) + +ngate = nplus.and(tgate) +nsd = ncomp.outside(nwell).interacting(ngate).not(ngate).not(res_mk) +ptap = pcomp.outside(nwell).outside(dnwell).not(res_mk) + +pgate = pplus.and(tgate) +psd = pcomp.inside(nwell).interacting(pgate).not(pgate).not(res_mk) +ntap = ncomp.inside(nwell).not(res_mk) + +ngate_dw = ngate.and(lvpwell).and(dnwell) +ptap_dw = pcomp.inside(lvpwell).inside(dnwell).outside(well_diode_mk).not(res_mk) + +pgate_dw = pgate.inside(dnwell).outside(lvpwell) +ntap_dw = ncomp.outside(lvpwell).inside(dnwell).not(res_mk) + +psd_dw = pcomp.not(lvpwell).and(dnwell).interacting(pgate).not(pgate).not(res_mk) +nwell_con = nwell.not(res_mk) +lvpwell_con = lvpwell.not(res_mk) +poly2_con = poly2.not(res_mk).not(plfuse) + +metal1_con = metal1.not(metal1_res) +metal2_con = metal2.not(metal2_res) +metal3_con = metal3.not(metal3_res) +metaltop_con = metaltop.not(metal6_res) + +#================================== +# ------ MOSFET DERIVATIONS ------- +#================================== + +logger.info("Starting MOSFET DERIVATIONS") + +# ============== +# ---- PMOS ---- +# ============== +logger.info("Starting PMOS layers DERIVATIONS") + +# 3.3V PMOS transistor outside DNWELL +pgate_3p3v = pgate.not(v5_xtor).not(dualgate).not(dnwell).not(sab).not_interacting(mos_cap_mk) + +# 5V PMOS transistor outside DNWELL +pgate_5v = pgate.and(v5_xtor).and(dualgate).not(dnwell).not(sab).not_interacting(mos_cap_mk) + +# 6V PMOS transistor outside DNWELL +pgate_6v = pgate.not(v5_xtor).and(dualgate).not(nat).not(ldmos_xtor).not(dnwell).not(sab).not_interacting(mos_cap_mk) + +# 3.3V PMOS transistor inside DNWELL +pgate_3p3v_dw = pgate_dw.not(v5_xtor).not(dualgate).not(sab).not_interacting(mos_cap_mk) + +# 5V PMOS transistor inside DNWELL +pgate_5v_dw = pgate_dw.and(v5_xtor).and(dualgate).not(sab).not_interacting(mos_cap_mk) + +# 6V PMOS transistor inside DNWELL +pgate_6v_dw = pgate_dw.not(v5_xtor).and(dualgate).not(nat).not(ldmos_xtor).not(sab).not_interacting(mos_cap_mk) + +# LDPMOS transistor +pgate_ldmos = pgate_dw.interacting(mvpsd).not(v5_xtor).and(dualgate).and(ldmos_xtor).and(dnwell).not(mvpsd).not_interacting(mos_cap_mk) +pd_ldmos = psd_dw.not(v5_xtor).and(dualgate).and(ldmos_xtor).and(dnwell).and(mvpsd) +ps_ldmos = psd_dw.not(v5_xtor).and(dualgate).and(ldmos_xtor).and(dnwell).not(mvpsd) +psd_ldmos = pcomp.not(v5_xtor).and(dualgate).and(ldmos_xtor).and(dnwell).interacting(mvpsd).sized(0.29.um).sized(-0.29.um).extents.not(pgate_ldmos) + +# ============== +# ---- NMOS ---- +# ============== +logger.info("Starting NMOS layers DERIVATIONS") + +# 3.3V NMOS transistor outside DNWELL +ngate_3p3v = ngate.not(v5_xtor).not(dualgate).not(dnwell).not(sab).not_interacting(mos_cap_mk) + +# 5V NMOS transistor outside DNWELL +ngate_5v = ngate.and(v5_xtor).and(dualgate).not(dnwell).not(sab).not_interacting(mos_cap_mk) + +# 6V NMOS transistor outside DNWELL +ngate_6v = ngate.not(v5_xtor).and(dualgate).not(nat).not(ldmos_xtor).not(dnwell).not(sab).not_interacting(mos_cap_mk) + +# 3.3V NMOS transistor inside DNWELL +ngate_3p3v_dw = ngate_dw.not(v5_xtor).not(dualgate).not(sab).not_interacting(mos_cap_mk) + +# 5V NMOS transistor inside DNWELL +ngate_5v_dw = ngate_dw.and(v5_xtor).and(dualgate).not(sab).not_interacting(mos_cap_mk) + +# 6V NMOS transistor inside DNWELL +ngate_6v_dw = ngate_dw.not(v5_xtor).and(dualgate).not(nat).not(ldmos_xtor).not(sab).not_interacting(mos_cap_mk) + +# Native Vt NMOS transistor +ngate_nat = ngate.not(v5_xtor).and(dualgate).and(nat).not_interacting(mos_cap_mk) + +# LDNMOS transistor +ngate_ldmos = ngate.interacting(mvsd).not(v5_xtor).and(dualgate).and(ldmos_xtor).not(dnwell).not(mvsd).not_interacting(mos_cap_mk) +nd_ldmos = ncomp.not(ngate).not(v5_xtor).and(dualgate).and(ldmos_xtor).not(dnwell).and(mvsd) +ns_ldmos = nsd.not(v5_xtor).and(dualgate).and(ldmos_xtor).not(dnwell).not(mvsd) +nsd_ldmos = ncomp.not(v5_xtor).and(dualgate).and(ldmos_xtor).not(dnwell).interacting(mvsd).sized(0.37.um).sized(-0.37.um).extents.not(ngate_ldmos) + +#================================ +# ------ BJT DERIVATIONS -------- +#================================ +logger.info("Starting BJT DERIVATIONS") + +# ============== +# ---- vnpn ---- +# ============== +logger.info("Starting vnpn layers DERIVATIONS") + +# vnpn general nodes DERIVATIONS +vnpn_e = ncomp.interacting(lvs_bjt).inside(dnwell) +vnpn_b = pcomp.and(lvpwell).inside(dnwell).inside(drc_bjt) +vnpn_c = ncomp.inside(dnwell).outside(lvs_bjt).inside(drc_bjt) + +# vnpn_10x10 nodes DERIVATIONS +vnpn_10x10_e = vnpn_e.with_area(99.5.um,100.5.um).interacting(vnpn_e.edges.with_length(9.8.um,10.2.um)) +vnpn_10x10_b = vnpn_b.interacting(vnpn_b.extents.interacting(vnpn_10x10_e)) +vnpn_10x10_c = vnpn_c.interacting(vnpn_c.extents.interacting(vnpn_10x10_e)) + +# vnpn_5x5 nodes DERIVATIONS +vnpn_5x5_e = vnpn_e.with_area(24.5.um,25.5.um).interacting(vnpn_e.edges.with_length(4.8.um,5.2.um)) +vnpn_5x5_b = vnpn_b.interacting(vnpn_b.extents.interacting(vnpn_5x5_e)) +vnpn_5x5_c = vnpn_c.interacting(vnpn_c.extents.interacting(vnpn_5x5_e)) + +# vnpn_0p54x16 nodes DERIVATIONS +vnpn_0p54x16_e = vnpn_e.with_area(8.um,9.um).interacting(vnpn_e.edges.with_length(15.5.um,16.5.um)) +vnpn_0p54x16_b = vnpn_b.interacting(vnpn_b.extents.interacting(vnpn_0p54x16_e)) +vnpn_0p54x16_c = vnpn_c.interacting(vnpn_c.extents.interacting(vnpn_0p54x16_e)) + +# vnpn_0p54x8 nodes DERIVATIONS +vnpn_0p54x8_e = vnpn_e.with_area(4.um,5.um).interacting(vnpn_e.edges.with_length(7.5.um,8.5.um)) +vnpn_0p54x8_b = vnpn_b.interacting(vnpn_b.extents.interacting(vnpn_0p54x8_e)) +vnpn_0p54x8_c = vnpn_c.interacting(vnpn_c.extents.interacting(vnpn_0p54x8_e)) + +# vnpn_0p54x4 nodes DERIVATIONS +vnpn_0p54x4_e = vnpn_e.with_area(1.5.um,2.5.um).interacting(vnpn_e.edges.with_length(3.8.um,4.2.um)) +vnpn_0p54x4_b = vnpn_b.interacting(vnpn_b.extents.interacting(vnpn_0p54x4_e)) +vnpn_0p54x4_c = vnpn_c.interacting(vnpn_c.extents.interacting(vnpn_0p54x4_e)) + +# vnpn_0p54x2 nodes DERIVATIONS +vnpn_0p54x2_e = vnpn_e.with_area(0.8.um,1.5.um).interacting(vnpn_e.edges.with_length(1.8.um,2.2.um)) +vnpn_0p54x2_b = vnpn_b.interacting(vnpn_b.extents.interacting(vnpn_0p54x2_e)) +vnpn_0p54x2_c = vnpn_c.interacting(vnpn_c.extents.interacting(vnpn_0p54x2_e)) + +# ============== +# ---- vpnp ---- +# ============== +logger.info("Starting vpnp layers DERIVATIONS") + +# vpnp general nodes DERIVATIONS +vpnp_e = pcomp.inside(nwell).interacting(lvs_bjt) +vpnp_b = ncomp.and(nwell).inside(drc_bjt) +vpnp_c = ptap.outside(lvs_bjt).inside(drc_bjt) + +# vpnp_10x10 nodes DERIVATIONS +vpnp_10x10_e = vpnp_e.with_area(99.5.um,100.5.um).interacting(vpnp_e.edges.with_length(9.8.um,10.2.um)) +vpnp_10x10_b = vpnp_b.interacting(vpnp_b.extents.interacting(vpnp_10x10_e)) +vpnp_10x10_c = vpnp_c.interacting(vpnp_c.extents.interacting(vpnp_10x10_e)) + +# vpnp_5x5 nodes DERIVATIONS +vpnp_5x5_e = vpnp_e.with_area(24.5.um,25.5.um).interacting(vpnp_e.edges.with_length(4.8.um,5.2.um)) +vpnp_5x5_b = vpnp_b.interacting(vpnp_b.extents.interacting(vpnp_5x5_e)) +vpnp_5x5_c = vpnp_c.interacting(vpnp_c.extents.interacting(vpnp_5x5_e)) + +# vpnp_0p42x10 nodes DERIVATIONS +vpnp_0p42x10_e = vpnp_e.with_area(4.um,4.5.um).interacting(vpnp_e.edges.with_length(9.8.um,10.2.um)) +vpnp_0p42x10_b = vpnp_b.interacting(vpnp_b.extents.interacting(vpnp_0p42x10_e)) +vpnp_0p42x10_c = vpnp_c.interacting(vpnp_c.extents.interacting(vpnp_0p42x10_e)) + +# vpnp_0p42x5 nodes DERIVATIONS +vpnp_0p42x5_e = vpnp_e.with_area(2.um,2.2.um).interacting(vpnp_e.edges.with_length(4.8.um,5.2.um)) +vpnp_0p42x5_b = vpnp_b.interacting(vpnp_b.extents.interacting(vpnp_0p42x5_e)) +vpnp_0p42x5_c = vpnp_c.interacting(vpnp_c.extents.interacting(vpnp_0p42x5_e)) + +#================================ +# ----- DIODE DERIVATIONS ------- +#================================ +logger.info("Starting DIODE DERIVATIONS") + +# np_3p3 diode +np_3p3_terminal_n = ncomp.not(v5_xtor).not(dualgate).outside(dnwell).interacting(diode_mk) + +# np_3p3_dw diode +np_3p3_dw_terminal_n = ncomp.not(v5_xtor).not(dualgate).inside(dnwell).interacting(diode_mk) + +# np_6p0 diode +np_6p0_terminal_n = ncomp.and(dualgate).outside(dnwell).interacting(diode_mk) + +# np_6p0_dw diode +np_6p0_dw_terminal_n = ncomp.and(dualgate).inside(dnwell).interacting(diode_mk) + +# pn_3p3 diode +pn_3p3_terminal_p = pcomp.not(v5_xtor).not(dualgate).outside(dnwell).interacting(diode_mk) + +# pn_3p3_dw diode +pn_3p3_dw_terminal_p = pcomp.not(v5_xtor).not(dualgate).inside(dnwell).interacting(diode_mk) + +# pn_6p0 diode +pn_6p0_terminal_p = pcomp.and(dualgate).outside(dnwell).interacting(diode_mk) + +# pn_6p0_dw diode +pn_6p0_dw_terminal_p = pcomp.and(dualgate).inside(dnwell).interacting(diode_mk) + +# nwp_3p3 diode +nwp_3p3_terminal_p = pcomp.not(v5_xtor).not(dualgate).outside(dnwell).interacting(well_diode_mk) +nwp_3p3_terminal_n = well_diode_mk.not(v5_xtor).not(dualgate).covering(nwell) + +# nwp_6p0 diode +nwp_6p0_terminal_p = pcomp.and(dualgate).outside(dnwell).interacting(well_diode_mk) +nwp_6p0_terminal_n = well_diode_mk.and(dualgate).covering(nwell) + +# dnwpw_3p3 diode +dnwpw_3p3_terminal_p = lvpwell.not(v5_xtor).not(dualgate).interacting(well_diode_mk) + +# dnwpw_6p0 diode +dnwpw_6p0_terminal_p = lvpwell.and(dualgate).interacting(well_diode_mk) + +# dnwps_3p3 diode +dnwps_3p3_terminal_p = ptap.extents.not_interacting(lvpwell).not_covering(v5_xtor).not_covering(dualgate).interacting(well_diode_mk) + +# dnwps_6p0 diode +dnwps_6p0_terminal_p = ptap.extents.not_interacting(lvpwell).covering(dualgate).interacting(well_diode_mk) + +# sc_diode diode +sc_diode_terminal_n = ncomp.inside(dnwell).inside(schottky_diode) +sc_diode_terminal_p = metal1.inside(dnwell).not_interacting(sc_diode_terminal_n) + +#================================ +# ---- RESISTOR DERIVATIONS ----- +#================================ +logger.info("Starting RESISTOR DERIVATIONS") + +# =============== +# --DIFF & WELL-- +# =============== + +# NPLUS_U +nplus_u_layer = ncomp.and(lvpwell).and(sab).and(res_mk).not(dnwell) +nplus_cont = ncomp.outside(nwell).not_interacting(ngate).interacting(res_mk).not(res_mk) + +# NPLUS_U_DW +nplus_u_dw_layer = ncomp.and(lvpwell).and(sab).and(res_mk).and(dnwell) + +# PPLUS_U +pplus_u_layer = pcomp.and(nwell).and(sab).and(res_mk).not(dnwell) +pplus_cont = pcomp.inside(nwell).not_interacting(pgate).interacting(res_mk).not(res_mk) + +# PPLUS_U_DW +pplus_u_dw_layer = pcomp.and(sab).and(res_mk).and(dnwell) +pplus_dw_cont = pcomp.not(lvpwell).and(dnwell).not_interacting(pgate).interacting(res_mk).not(res_mk) + +# NPLUS_S +nplus_s_layer = ncomp.and(lvpwell).and(res_mk).not_interacting(sab).not(dnwell) + +# NPLUS_S_DW +nplus_s_dw_layer = ncomp.and(lvpwell).and(res_mk).and(dnwell).not_interacting(sab) + +# PPLUS_S +pplus_s_layer = pcomp.and(nwell).and(res_mk).not_interacting(sab).not(dnwell) + +# PPLUS_S_DW +pplus_s_dw_layer = pcomp.not_interacting(sab).and(res_mk).and(dnwell).not_interacting(sab) + +# NWELL +nwell_res = nwell.and(res_mk).not(dnwell).not_covering(comp) + +# PWELL +pwell_res = lvpwell.and(res_mk).and(dnwell).not_covering(comp) + +# ============== +# ---- POLY ---- +# ============== + +# NPOLYF_U +npolyf_u_layer = nplus.and(poly2).and(sab).and(res_mk).not(dnwell) + +# NPOLYF_U_DW +npolyf_u_dw_layer = nplus.and(poly2).and(sab).and(res_mk).and(dnwell) + +# PPOLYF_U +ppolyf_u_layer = pplus.and(poly2).and(sab).and(res_mk).not_interacting(resistor).not(dnwell) + +# PPOLYF_U_DW +ppolyf_u_dw_layer = pplus.and(poly2).and(sab).and(res_mk).not_interacting(resistor).and(dnwell) + +# NPOLYF_S +npolyf_s_layer = nplus.and(poly2).and(res_mk).not(dnwell).not_interacting(sab) + +# NPOLYF_S_DW +npolyf_s_dw_layer = nplus.and(poly2).and(res_mk).and(dnwell).not_interacting(sab) + +# PPOLYF_S +ppolyf_s_layer = pplus.and(poly2).and(res_mk).not(dnwell).not_interacting(sab) + +# PPOLYF_S_DW +ppolyf_s_dw_layer = pplus.and(poly2).and(res_mk).and(dnwell).not_interacting(sab) + +# ============== +# --H-POLY RES-- +# ============== + +if POLY_RES == "1k" + + # PPOLYF_U_1K + ppolyf_u_1k_layer = poly2.and(sab).and(res_mk).and(resistor).not(dnwell).not(v5_xtor).not(dualgate) + + # PPOLYF_U_DW_1K + ppolyf_u_1k_dw_layer = poly2.and(res_mk).and(dnwell).and(resistor).not(v5_xtor).not(dualgate) + + # PPOLYF_U_1K_6p0 + ppolyf_u_1k_6p0_layer = poly2.and(sab).and(res_mk).and(resistor).not(dnwell).not(v5_xtor).and(dualgate) + + # PPOLYF_U_DW_1K_6p0 + ppolyf_u_1k_6p0_dw_layer = poly2.and(res_mk).and(dnwell).and(resistor).not(v5_xtor).and(dualgate) + +elsif POLY_RES == "2k" + + # PPOLYF_U_2K + ppolyf_u_2k_layer = poly2.and(sab).and(res_mk).and(resistor).not(dnwell).not(v5_xtor).not(dualgate) + + # PPOLYF_U_DW_2K + ppolyf_u_2k_dw_layer = poly2.and(res_mk).and(dnwell).and(resistor).not(v5_xtor).not(dualgate) + + # PPOLYF_U_2K_6p0 + ppolyf_u_2k_6p0_layer = poly2.and(sab).and(res_mk).and(resistor).not(dnwell).not(v5_xtor).and(dualgate) + + # PPOLYF_U_DW_2K_6p0 + ppolyf_u_2k_6p0_dw_layer = poly2.and(res_mk).and(dnwell).and(resistor).not(v5_xtor).and(dualgate) + +elsif POLY_RES == "3k" + + # PPOLYF_U_3K + ppolyf_u_3k_layer = poly2.and(sab).and(res_mk).and(resistor).not(dnwell).not(v5_xtor).not(dualgate) + + # PPOLYF_U_DW_3K + ppolyf_u_3k_dw_layer = poly2.and(res_mk).and(dnwell).and(resistor).not(v5_xtor).not(dualgate) + + # PPOLYF_U_3K_6p0 + ppolyf_u_3k_6p0_layer = poly2.and(sab).and(res_mk).and(resistor).not(dnwell).not(v5_xtor).and(dualgate) + + # PPOLYF_U_DW_3K_6p0 + ppolyf_u_3k_6p0_dw_layer = poly2.and(res_mk).and(dnwell).and(resistor).not(v5_xtor).and(dualgate) + +end + + +# =============== +# ---- METAL ---- +# =============== + +# Metal1 resistor +rm1_res = metal1.and(metal1_res) + +# Metal2 resistor +rm2_res = metal2.and(metal2_res) + +# Metal3 resistor +rm3_res = metal3.and(metal3_res) + +# Metaltop resistor +tm_res = metaltop.and(metal6_res) + +#================================== +# ------ MIMCAP DERIVATIONS ------- +#================================== +logger.info("Starting MIMCAP DERIVATIONS") + +# mim option A +mim_virtual = fusetop.sized(1.06.um).and(metal2.interacting(fusetop)) +metal2_ncap = metal2_con.not(mim_virtual) +fuse_cap = fusetop.interacting(cap_mk).interacting(mim_l_mk) + +# mim_option B +mimtm_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop)) +metal3_ncap = metal3_con.not(mimtm_virtual) +metal4_ncap = metal4.not(mimtm_virtual) +metal5_ncap = metal5.not(mimtm_virtual) + + +#================================== +# ------ MOSCAP DERIVATIONS ------- +#================================== +logger.info("Starting MOSCAP DERIVATIONS") + +# nmoscap_3p3 capacitor +nmos_gate_3p3 = ngate.not(v5_xtor).not(dualgate).outside(dnwell).interacting(mos_cap_mk) + +# nmoscap_3p3_dw capacitor +nmos_gate_3p3_dw = ngate.not(v5_xtor).not(dualgate).inside(dnwell).interacting(mos_cap_mk) + +# pmoscap_3p3 capacitor +pmos_gate_3p3 = pgate.not(v5_xtor).not(dualgate).outside(dnwell).interacting(mos_cap_mk) + +# pmoscap_3p3_dw capacitor +pmos_gate_3p3_dw = pgate.not(v5_xtor).not(dualgate).inside(dnwell).interacting(mos_cap_mk) + +# nmoscap_6p0 capacitor +nmos_gate_6p0 = ngate.and(dualgate).outside(dnwell).interacting(mos_cap_mk) + +# nmoscap_6p0_dw capacitor +nmos_gate_6p0_dw = ngate.and(dualgate).inside(dnwell).interacting(mos_cap_mk) + +# pmoscap_6p0 capacitor +pmos_gate_6p0 = pgate.and(dualgate).outside(dnwell).interacting(mos_cap_mk) + +# pmoscap_6p0_dw capacitor +pmos_gate_6p0_dw = pgate.and(dualgate).inside(dnwell).interacting(mos_cap_mk) + +# nmoscap_3p3_b capacitor +nmoscap_3p3_b = ngate.not(v5_xtor).not(dualgate).inside(nwell).interacting(mos_cap_mk) + +# pmoscap_3p3_b capacitor +pmoscap_3p3_b = pgate.not(v5_xtor).not(dualgate).inside(ptap).interacting(mos_cap_mk) + +# nmoscap_6p0_b capacitor +nmoscap_6p0_b = ngate.and(dualgate).inside(nwell).interacting(mos_cap_mk) + +# pmoscap_6p0_b capacitor +pmoscap_6p0_b = pgate.and(dualgate).inside(ptap).interacting(mos_cap_mk) + +#================================ +# ------ ESD DERIVATIONS -------- +#================================ +logger.info("Starting MOS SAB DERIVATIONS") + +# ============== +# ---- PMOS ---- +# ============== +logger.info("Starting PMOS SAB DERIVATIONS") + +# 3.3V ESD PMOS transistor outside DNWELL +pgate_sab_3p3v = pgate.not(v5_xtor).not(dualgate).not(dnwell).and(esd_mk).interacting(sab) + +# 5V ESD PMOS transistor outside DNWELL +pgate_sab_5v = pgate.and(v5_xtor).and(dualgate).not(dnwell).and(esd_mk).interacting(sab) + +# 6V ESD PMOS transistor outside DNWELL +pgate_sab_6v = pgate.not(v5_xtor).and(dualgate).not(dnwell).and(esd_mk).interacting(sab) + +# 3.3V ESD PMOS transistor inside DNWELL +pgate_dw_sab_3p3v = pgate_dw.not(v5_xtor).not(dualgate).and(esd_mk).interacting(sab) + +# 5V ESD PMOS transistor inside DNWELL +pgate_dw_sab_5v = pgate_dw.and(v5_xtor).and(dualgate).and(esd_mk).interacting(sab) + +# 6V ESD PMOS transistor inside DNWELL +pgate_dw_sab_6v = pgate_dw.not(v5_xtor).and(dualgate).and(esd_mk).interacting(sab) + +# ============== +# ---- NMOS ---- +# ============== +logger.info("Starting NMOS SAB DERIVATIONS") + +# 3.3V ESD NMOS transistor outside DNWELL +ngate_sab_3p3v = ngate.not(v5_xtor).not(dualgate).not(dnwell).and(esd_mk).interacting(sab) + +# 5V ESD NMOS transistor outside DNWELL +ngate_sab_5v = ngate.and(v5_xtor).and(dualgate).not(dnwell).and(esd_mk).interacting(sab) + +# 6V ESD NMOS transistor outside DNWELL +ngate_sab_6v = ngate.not(v5_xtor).and(dualgate).not(dnwell).and(esd_mk).interacting(sab) + +# 3.3V ESD NMOS transistor inside DNWELL +ngate_dw_sab_3p3v = ngate_dw.not(v5_xtor).not(dualgate).and(esd_mk).interacting(sab) + +# 5V ESD NMOS transistor inside DNWELL +ngate_dw_sab_5v = ngate_dw.and(v5_xtor).and(dualgate).and(esd_mk).interacting(sab) + +# 6V ESD NMOS transistor inside DNWELL +ngate_dw_sab_6v = ngate_dw.not(v5_xtor).and(dualgate).and(esd_mk).interacting(sab) + +#================================ +# ------ EFUSE DERIVATIONS ------ +#================================ +logger.info("Starting NMOS EFUSE DERIVATIONS") + +cathode = poly2.inside(efuse_mk).not(lvs_source.or(plfuse)) +anode = poly2.and(lvs_source).inside(efuse_mk) +efuse_link = (poly2).and(plfuse).inside(efuse_mk) +efuse_con_layer = cathode | anode + + +#================================================ +#------------ DEVICES CONNECTIVITY -------------- +#================================================ + +logger.info("Starting GF180 LVS connectivity setup") + +#================================ +# ----- GENERAL CONNECTIONS ----- +#================================ +logger.info("Starting GF180 LVS connectivity setup (Inter-layer)") + +# Inter-layer +connect(sub , ptap) +connect(lvpwell_con , ptap) +connect(lvpwell_con , ptap_dw) +connect(dnwell , ntap_dw) +connect(nwell_con , ntap) +connect(ptap , contact) +connect(ptap_dw , contact) +connect(ntap , contact) +connect(ntap_dw , contact) +connect(psd , contact) +connect(psd_dw , contact) +connect(nsd , contact) +connect(poly2_con , contact) +connect(contact , metal1_con) +connect(metal1_con , via1) +connect(via1 , metal2_ncap) +connect(metal2_ncap , via2) +connect(via2 , metal3_ncap) +connect(metal3_ncap , via3) +connect(via3 , metal4_ncap) +connect(metal4_ncap , via4) +connect(via4 , metal5_ncap) +connect(metal5_ncap , via5) +connect(via5 , metaltop_con) + +logger.info("Starting GF180 LVS connectivity setup (Attaching labels)") + +# Attaching labels +connect(comp , comp_label) +connect(poly2_con , poly2_label) +connect(metal1_con , metal1_label) +connect(metal2_ncap , metal2_label) +connect(metal3_ncap , metal3_label) +connect(metal4_ncap , metal4_label) +connect(metal5_ncap , metal5_label) +connect(metaltop_con, metaltop_label) + +logger.info("Starting GF180 LVS connectivity setup (Global)") + +# Global +connect_global(sub , substrate_name) + +logger.info("Starting GF180 LVS connectivity setup (Multifinger Devices)") + +# Multifinger Devices +connect_implicit("*") + +#================================ +# ----- MOSFET CONNECTIONS ------ +#================================ +logger.info("Starting LVS MOSFET CONNECTIONS") + +connect(psd_dw, contact) + +connect(nd_ldmos, contact) +connect(ns_ldmos, contact) + +connect(pd_ldmos, contact) +connect(ps_ldmos, contact) + + +#================================ +# ------ BJT CONNECTIONS -------- +#================================ +logger.info("Starting LVS BJT CONNECTIONS") + +# ============== +# ---- vnpn ---- +# ============== + +# vnpn_10x10 nodes connections +connect(vnpn_10x10_e,contact) +connect(vnpn_10x10_b,contact) +connect(vnpn_10x10_c,contact) + +# vnpn_5x5 nodes connections +connect(vnpn_5x5_e,contact) +connect(vnpn_5x5_b,contact) +connect(vnpn_5x5_c,contact) + +# vnpn_0p54x16 nodes connections +connect(vnpn_0p54x16_e,contact) +connect(vnpn_0p54x16_b,contact) +connect(vnpn_0p54x16_c,contact) + +# vnpn_0p54x8 nodes connections +connect(vnpn_0p54x8_e,contact) +connect(vnpn_0p54x8_b,contact) +connect(vnpn_0p54x8_c,contact) + +# vnpn_0p54x4 nodes connections +connect(vnpn_0p54x4_e,contact) +connect(vnpn_0p54x4_b,contact) +connect(vnpn_0p54x4_c,contact) + +# vnpn_0p54x2 nodes connections +connect(vnpn_0p54x2_e,contact) +connect(vnpn_0p54x2_b,contact) +connect(vnpn_0p54x2_c,contact) + +# ============== +# ---- vpnp ---- +# ============== + +# vpnp_10x10 nodes connections +connect(vpnp_10x10_e,contact) +connect(vpnp_10x10_b,contact) +connect(vpnp_10x10_c,contact) + +# vpnp_5x5 nodes connections +connect(vpnp_5x5_e,contact) +connect(vpnp_5x5_b,contact) +connect(vpnp_5x5_c,contact) + +# vpnp_0p42x10 nodes connections +connect(vpnp_0p42x10_e,contact) +connect(vpnp_0p42x10_b,contact) +connect(vpnp_0p42x10_c,contact) + +# vpnp_0p42x5 nodes connections +connect(vpnp_0p42x5_e,contact) +connect(vpnp_0p42x5_b,contact) +connect(vpnp_0p42x5_c,contact) + + +#================================ +# ----- DIODE CONNECTIONS ------- +#================================ + +logger.info("Starting LVS DIODE CONNECTIONS") + +# np_3p3 diode +connect(np_3p3_terminal_n,contact) + +# np_3p3_dw diode +connect(np_3p3_dw_terminal_n,contact) + +# np_6p0 diode +connect(np_6p0_terminal_n,contact) + +# np_6p0_dw diode +connect(np_6p0_dw_terminal_n,contact) + +# pn_3p3 diode +connect(pn_3p3_terminal_p,contact) + +# pn_3p3_dw diode +connect(pn_3p3_dw_terminal_p,contact) + +# pn_6p0 diode +connect(pn_6p0_terminal_p,contact) + +# pn_6p0_dw diode +connect(pn_6p0_dw_terminal_p,contact) + +# nwp_3p3 diode +connect(nwp_3p3_terminal_p,contact) +connect(nwp_3p3_terminal_n,nwell) + +# nwp_6p0 diode +connect(nwp_6p0_terminal_p,contact) +connect(nwp_6p0_terminal_n,nwell) + +# dnwpw_3p3 diode +connect(dnwpw_3p3_terminal_p,contact) + +# dnwpw_6p0 diode +connect(dnwpw_6p0_terminal_p,contact) + +# dnwps_3p3 diode +connect(dnwps_3p3_terminal_p,ptap) + +# dnwps_6p0 diode +connect(dnwps_6p0_terminal_p,ptap) + +# sc_diode diode +connect(sc_diode_terminal_n,contact) +connect(sc_diode_terminal_p,schottky_diode) + +#================================ +# ---- RESISTOR DERIVATIONS ----- +#================================ + +logger.info("Starting LVS RESISTOR CONNECTIONS") + +connect(nplus_cont , contact) +connect(pplus_cont , contact) +connect(pplus_dw_cont, contact) + +#================================== +# ------ MIMCAP CONNECTIONS ------- +#================================== + +logger.info("Starting LVS MIMCAP CONNECTIONS") + +if MIM_OPTION == "A" + + # mim option A + connect(metal2,mim_virtual) + connect(fuse_cap,via2) + +elsif MIM_OPTION == "B" + + # mim_option B + connect(topmin1_metal,mimtm_virtual) + connect(fuse_cap,top_via) + +end + +#================================ +# ------ EFUSE CONNECTIONS ------ +#================================ + +logger.info("Starting LVS EFUSE CONNECTIONS") + +connect(cathode, contact) +connect(anode, contact) + + +#================================================ +#------------- DEVICES EXTRACTION --------------- +#================================================ + +logger.info("Starting GF180 LVS DEVICES EXTRACTION") + +#================================ +# ----- MOSFET EXTRACTION ------- +#================================ +logger.info("Starting MOSFET EXTRACTION") + +# ============== +# ---- PMOS ---- +# ============== +logger.info("Starting PMOS EXTRACTION") + +# 3.3V PMOS transistor outside DNWELL +logger.info("Extracting 3.3V PMOS transistor outside DNWEL") +extract_devices(mos4("pmos_3p3"), { "SD" => psd, "G" => pgate_3p3v, "tS" => psd, "tD" => psd, "tG" => poly2_con, "W" => nwell_con }) + +# 5V PMOS transistor outside DNWELL +logger.info("Extracting 5V PMOS transistor outside DNWELL") +extract_devices(mos4("pmos_5p0"), { "SD" => psd, "G" => pgate_5v, "tS" => psd, "tD" => psd, "tG" => poly2_con, "W" => nwell_con }) + +# 6V PMOS transistor outside DNWELL +logger.info("Extracting 6V PMOS transistor outside DNWELL") +extract_devices(mos4("pmos_6p0"), { "SD" => psd, "G" => pgate_6v, "tS" => psd, "tD" => psd, "tG" => poly2_con, "W" => nwell_con }) + +# 3.3V PMOS transistor inside DNWELL +logger.info("Extracting 3.3V PMOS transistor inside DNWELL") +extract_devices(mos4("pmos_3p3_dw"), { "SD" => psd_dw, "G" => pgate_3p3v_dw, "tS" => psd_dw, "tD" => psd_dw, "tG" => poly2_con, "W" => dnwell }) + +# 5V PMOS transistor inside DNWELL +logger.info("Extracting 5V PMOS transistor inside DNWELL") +extract_devices(mos4("pmos_5p0_dw"), { "SD" => psd_dw, "G" => pgate_5v_dw, "tS" => psd_dw, "tD" => psd_dw, "tG" => poly2_con, "W" => dnwell }) + +# 6V PMOS transistor inside DNWELL +logger.info("Extracting 6V PMOS transistor inside DNWELL") +extract_devices(mos4("pmos_6p0_dw"), { "SD" => psd_dw, "G" => pgate_6v_dw, "tS" => psd_dw, "tD" => psd_dw, "tG" => poly2_con, "W" => dnwell }) + +# LDPMOS transistor +logger.info("Extracting LDPMOS transistor") +extract_devices(mos4("pmos_10p0_asym"), { "SD" => psd_ldmos, "G" => pgate_ldmos, "tS" => ps_ldmos, "tD" => pd_ldmos, "tG" => poly2_con, "W" => dnwell }) + +# ============== +# ---- NMOS ---- +# ============== + +logger.info("Starting NMOS EXTRACTION") + +# 3.3V NMOS transistor outside DNWELL +logger.info("3.3V NMOS transistor outside DNWELL") +extract_devices(mos4("nmos_3p3"), { "SD" => nsd, "G" => ngate_3p3v, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => sub }) + +# 5V NMOS transistor outside DNWELL +logger.info("5V NMOS transistor outside DNWELL") +extract_devices(mos4("nmos_5p0"), { "SD" => nsd, "G" => ngate_5v, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => sub }) + +# 6V NMOS transistor outside DNWELL +logger.info("6V NMOS transistor outside DNWELL") +extract_devices(mos4("nmos_6p0"), { "SD" => nsd, "G" => ngate_6v, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => sub }) + +# 3.3V NMOS transistor inside DNWELL +logger.info("3.3V NMOS transistor inside DNWELL") +extract_devices(mos4("nmos_3p3_dw"), { "SD" => nsd, "G" => ngate_3p3v_dw, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => lvpwell_con }) + +# 5V NMOS transistor inside DNWELL +logger.info("5V NMOS transistor inside DNWELL") +extract_devices(mos4("nmos_5p0_dw"), { "SD" => nsd, "G" => ngate_5v_dw, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => lvpwell_con }) + +# 6V NMOS transistor inside DNWELL +logger.info("6V NMOS transistor inside DNWELL") +extract_devices(mos4("nmos_6p0_dw"), { "SD" => nsd, "G" => ngate_6v_dw, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => lvpwell_con }) + +# Native Vt NMOS transistor +logger.info("Native Vt NMOS transistor") +extract_devices(mos4("nmos_6p0_nat"), { "SD" => nsd, "G" => ngate_nat, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => sub }) + +# LDNMOS transistor +logger.info("Extracting LDNMOS transistor") +extract_devices(mos4("nmos_10p0_asym"), { "SD" => nsd_ldmos, "G" => ngate_ldmos, "tS" => ns_ldmos, "tD" => nd_ldmos, "tG" => poly2_con, "W" => sub }) + + +#================================ +# ------- BJT EXTRACTION -------- +#================================ +logger.info("Starting BJT EXTRACTION") + +# ==================== +# ------ vnpn -------- +# ==================== +logger.info("Starting vnpn BJT EXTRACTION") + +# vnpn_10x10 BJT +ignore_parameter("vnpn_10x10","AE") +logger.info("Extracting vnpn_10x10 BJT") +extract_devices(bjt4("vnpn_10x10"), { "C" => vnpn_10x10_c.extents , "B" => vnpn_10x10_b.extents , "E" => vnpn_10x10_e,"S" => sub.extents, + "tC" => vnpn_10x10_c , "tB" => vnpn_10x10_b, "tE" => vnpn_10x10_e, "tS" => sub }) + +# vnpn_5x5 BJT +ignore_parameter("vnpn_5x5","AE") +logger.info("Extracting vnpn_5x5 BJT") +extract_devices(bjt4("vnpn_5x5"), { "C" => vnpn_5x5_c.extents , "B" => vnpn_5x5_b.extents , "E" => vnpn_5x5_e,"S" => sub.extents, + "tC" => vnpn_5x5_c , "tB" => vnpn_5x5_b, "tE" => vnpn_5x5_e, "tS" => sub }) + +# vnpn_0p54x16 BJT +ignore_parameter("vnpn_0p54x16","AE") +logger.info("Extracting vnpn_0p54x16 BJT") +extract_devices(bjt4("vnpn_0p54x16"), { "C" => vnpn_0p54x16_c.extents , "B" => vnpn_0p54x16_b.extents , "E" => vnpn_0p54x16_e,"S" => sub.extents, + "tC" => vnpn_0p54x16_c , "tB" => vnpn_0p54x16_b, "tE" => vnpn_0p54x16_e, "tS" => sub }) + +# vnpn_0p54x8 BJT +ignore_parameter("vnpn_0p54x8","AE") +logger.info("Extracting vnpn_0p54x8 BJT") +extract_devices(bjt4("vnpn_0p54x8"), { "C" => vnpn_0p54x8_c.extents , "B" => vnpn_0p54x8_b.extents , "E" => vnpn_0p54x8_e,"S" => sub.extents, + "tC" => vnpn_0p54x8_c , "tB" => vnpn_0p54x8_b, "tE" => vnpn_0p54x8_e, "tS" => sub }) + +# vnpn_0p54x4 BJT +ignore_parameter("vnpn_0p54x4","AE") +logger.info("Extracting vnpn_0p54x4 BJT") +extract_devices(bjt4("vnpn_0p54x4"), { "C" => vnpn_0p54x4_c.extents , "B" => vnpn_0p54x4_b.extents , "E" => vnpn_0p54x4_e,"S" => sub.extents, + "tC" => vnpn_0p54x4_c , "tB" => vnpn_0p54x4_b, "tE" => vnpn_0p54x4_e, "tS" => sub }) + +# vnpn_0p54x2 BJT +ignore_parameter("vnpn_0p54x2","AE") +logger.info("Extracting vnpn_0p54x2 BJT") +extract_devices(bjt4("vnpn_0p54x2"), { "C" => vnpn_0p54x2_c.extents , "B" => vnpn_0p54x2_b.extents , "E" => vnpn_0p54x2_e,"S" => sub.extents, + "tC" => vnpn_0p54x2_c , "tB" => vnpn_0p54x2_b, "tE" => vnpn_0p54x2_e, "tS" => sub }) + +# ==================== +# ------- vpnp-------- +# ==================== +logger.info("Starting vpnp BJT EXTRACTION") + +# vpnp_10x10 BJT +ignore_parameter("vpnp_10x10","AE") +logger.info("Extracting vpnp_10x10 BJT") +extract_devices(bjt3("vpnp_10x10"), { "C" => vpnp_10x10_c.extents , "B" => vpnp_10x10_b.extents , "E" => vpnp_10x10_e, + "tC" => vpnp_10x10_c , "tB" => vpnp_10x10_b, "tE" => vpnp_10x10_e }) + +# vpnp_5x5 BJT +ignore_parameter("vpnp_5x5","AE") +logger.info("Extracting vpnp_5x5 BJT") +extract_devices(bjt3("vpnp_5x5"), { "C" => vpnp_5x5_c.extents , "B" => vpnp_5x5_b.extents , "E" => vpnp_5x5_e, + "tC" => vpnp_5x5_c , "tB" => vpnp_5x5_b, "tE" => vpnp_5x5_e }) + +# vpnp_0p42x10 BJT +ignore_parameter("vpnp_0p42x10","AE") +logger.info("Extracting vpnp_0p42x10 BJT") +extract_devices(bjt3("vpnp_0p42x10"), { "C" => vpnp_0p42x10_c.extents , "B" => vpnp_0p42x10_b.extents , "E" => vpnp_0p42x10_e, + "tC" => vpnp_0p42x10_c , "tB" => vpnp_0p42x10_b, "tE" => vpnp_0p42x10_e }) + +# vpnp_0p42x5 BJT +ignore_parameter("vpnp_0p42x5","AE") +logger.info("Extracting vpnp_0p42x5 BJT") +extract_devices(bjt3("vpnp_0p42x5"), { "C" => vpnp_0p42x5_c.extents , "B" => vpnp_0p42x5_b.extents , "E" => vpnp_0p42x5_e, + "tC" => vpnp_0p42x5_c , "tB" => vpnp_0p42x5_b, "tE" => vpnp_0p42x5_e }) + + +#================================ +# ------ DIODE EXTRACTION ------- +#================================ +logger.info("Starting DIODE EXTRACTION") + +# np_3p3 diode +logger.info("Extracting np_3p3 diode") +extract_devices(diode("np_3p3"), { "N" => np_3p3_terminal_n , "P" => lvpwell_con}) + +# np_3p3_dw diode +logger.info("Extracting np_3p3_dw diode") +extract_devices(diode("np_3p3_dw"), { "N" => np_3p3_dw_terminal_n , "P" => lvpwell_con}) + +# np_6p0 diode +logger.info("Extracting np_6p0 diode") +extract_devices(diode("np_6p0"), { "N" => np_6p0_terminal_n , "P" => lvpwell_con}) + +# np_6p0_dw diode +logger.info("Extracting np_6p0_dw diode") +extract_devices(diode("np_6p0_dw"), { "N" => np_6p0_dw_terminal_n , "P" => lvpwell_con}) + +# pn_3p3 diode +logger.info("Extracting pn_3p3 diode") +extract_devices(diode("pn_3p3"), { "N" => nwell_con , "P" => pn_3p3_terminal_p}) + +# pn_3p3_dw diode +logger.info("Extractingpn_3p3_dw diode") +extract_devices(diode("pn_3p3_dw"), { "N" => nwell_con , "P" => pn_3p3_dw_terminal_p}) + +# pn_6p0 diode +logger.info("Extracting pn_6p0 diode") +extract_devices(diode("pn_6p0"), { "N" => nwell_con , "P" => pn_6p0_terminal_p}) + +# pn_6p0_dw diode +logger.info("Extracting pn_6p0_dw diode") +extract_devices(diode("pn_6p0_dw"), { "N" => nwell_con , "P" => pn_6p0_dw_terminal_p}) + +# nwp_3p3 diode +logger.info("Extracting nwp_3p3 diode") +extract_devices(diode("nwp_3p3"), { "N" => nwp_3p3_terminal_n , "P" => nwp_3p3_terminal_p}) + +# nwp_6p0 diode +logger.info("Extracting nwp_6p0 diode") +extract_devices(diode("nwp_6p0"), { "N" => nwp_6p0_terminal_n , "P" => nwp_6p0_terminal_p}) + +# dnwpw_3p3 diode +logger.info("Extracting dnwpw_3p3 diode") +extract_devices(diode("dnwpw_3p3"), { "N" => dnwell , "P" => dnwpw_3p3_terminal_p}) + +# dnwpw_6p0 diode +logger.info("Extracting dnwpw_6p0 diode") +extract_devices(diode("dnwpw_6p0"), { "N" => dnwell , "P" => dnwpw_6p0_terminal_p}) + +# dnwps_3p3 diode +logger.info("Extracting dnwps_3p3 diode") +extract_devices(diode("dnwps_3p3"), { "N" => dnwell , "P" => dnwps_3p3_terminal_p}) + +# dnwps_6p0 diode +logger.info("Extracting dnwps_6p0 diode") +extract_devices(diode("dnwps_6p0"), { "N" => dnwell , "P" => dnwps_6p0_terminal_p}) + +# sc_diode diode +logger.info("Extracting sc_diode diode") +extract_devices(diode("sc_diode"), { "N" => sc_diode_terminal_n , "P" => schottky_diode}) + + +#================================ +# ---- RESISTOR EXTRACTIONS ----- +#================================ +logger.info("Starting RESISTOR EXTRACTION") + +# =============== +# --DIFF & WELL-- +# =============== + +# NPLUS_U +logger.info("Extracting NPLUS_U device") +extract_devices(resistor_with_bulk("nplus_u", 60, BResistor), { "R" => nplus_u_layer, "C" => nplus_cont, "W" => sub}) + +# NPLUS_U_DW +logger.info("Extracting NPLUS_U_DW device") +extract_devices(resistor_with_bulk("nplus_u_dw", 60, BResistor), { "R" => nplus_u_dw_layer, "C" => nplus_cont, "W" => lvpwell_con }) + +# PPLUS_U +logger.info("Extracting PPLUS_U device") +extract_devices(resistor_with_bulk("pplus_u", 185, BResistor), { "R" => pplus_u_layer, "C" => pplus_cont, "W" => nwell_con}) + +# PPLUS_U_DW +logger.info("Extracting PPLUS_U_DW device") +extract_devices(resistor_with_bulk("pplus_u_dw", 185, BResistor), { "R" => pplus_u_dw_layer, "C" => pplus_dw_cont, "W" => dnwell }) + +# NPLUS_S +logger.info("Extracting NPLUS_S device") +extract_devices(resistor_with_bulk("nplus_s", 6.3, BResistor), { "R" => nplus_s_layer, "C" => nplus_cont, "W" => sub}) + +# NPLUS_S_DW +logger.info("Extracting NPLUS_S_DW device") +extract_devices(resistor_with_bulk("nplus_s_dw", 6.3, BResistor), { "R" => nplus_s_dw_layer, "C" => nplus_cont, "W" => lvpwell_con }) + +# PPLUS_S +logger.info("Extracting PPLUS_S device") +extract_devices(resistor_with_bulk("pplus_s", 7, BResistor), { "R" => pplus_s_layer, "C" => pplus_cont, "W" => nwell_con}) + +# PPLUS_S_DW +logger.info("Extracting PPLUS_S_DW device") +extract_devices(resistor_with_bulk("pplus_s_dw", 7, BResistor), { "R" => pplus_s_dw_layer, "C" => pplus_dw_cont, "W" => dnwell }) + +# NWELL +logger.info("Extracting NWELL device") +extract_devices(resistor_with_bulk("nwell", 1000, BResistor), { "R" => nwell_res, "C" => nwell_con, "W" => sub}) + +# PWELL +logger.info("Extracting PWELL device") +extract_devices(resistor_with_bulk("pwell", 1000, BResistor), { "R" => pwell_res, "C" => lvpwell_con, "W" => dnwell}) + +# ============== +# ---- POLY ---- +# ============== + +# NPOLYF_U +extract_devices(resistor_with_bulk("npolyf_u", 310, BResistor), { "R" => npolyf_u_layer, "C" => poly2_con, "W" => sub}) + +# NPOLYF_U_DW +extract_devices(resistor_with_bulk("npolyf_u_dw", 310, BResistor), { "R" => npolyf_u_dw_layer, "C" => poly2_con, "W" => dnwell }) + +# PPOLYF_U +extract_devices(resistor_with_bulk("ppolyf_u", 350, BResistor), { "R" => ppolyf_u_layer, "C" => poly2_con, "W" => sub}) + +# PPOLYF_U_DW +extract_devices(resistor_with_bulk("ppolyf_u_dw", 350, BResistor), { "R" => ppolyf_u_dw_layer, "C" => poly2_con, "W" => dnwell }) + +# NPOLYF_S +extract_devices(resistor_with_bulk("npolyf_s", 6.8, BResistor), { "R" => npolyf_s_layer, "C" => poly2_con, "W" => sub}) + +# NPOLYF_S_DW +extract_devices(resistor_with_bulk("npolyf_s_dw", 6.8, BResistor), { "R" => npolyf_s_dw_layer, "C" => poly2_con, "W" => dnwell }) + +# PPOLYF_S +extract_devices(resistor_with_bulk("ppolyf_s", 7.3, BResistor), { "R" => ppolyf_s_layer, "C" => poly2_con, "W" => sub}) + +# PPOLYF_S_DW +extract_devices(resistor_with_bulk("ppolyf_s_dw", 7.3, BResistor), { "R" => ppolyf_s_dw_layer, "C" => poly2_con, "W" => dnwell }) + +# ============== +# --H-POLY RES-- +# ============== + +if POLY_RES == "1k" + + # PPOLYF_U_1K + extract_devices(resistor_with_bulk("ppolyf_u_1k", 1000, BResistor), { "R" => ppolyf_u_1k_layer, "C" => poly2_con, "W" => sub}) + + # PPOLYF_U_DW_1K + extract_devices(resistor_with_bulk("ppolyf_u_1k_dw", 1000, BResistor), { "R" => ppolyf_u_1k_dw_layer, "C" => poly2_con, "W" => dnwell }) + + # PPOLYF_U_1K_6p0 + extract_devices(resistor_with_bulk("ppolyf_u_1k_6p0", 1000, BResistor), { "R" => ppolyf_u_1k_6p0_layer, "C" => poly2_con, "W" => sub}) + + # PPOLYF_U_DW_1K_6p0 + extract_devices(resistor_with_bulk("ppolyf_u_1k_6p0_dw", 1000, BResistor), { "R" => ppolyf_u_1k_6p0_dw_layer, "C" => poly2_con, "W" => dnwell }) + +elsif POLY_RES == "2k" + + # PPOLYF_U_2K + extract_devices(resistor_with_bulk("ppolyf_u_2k", 2000, BResistor), { "R" => ppolyf_u_2k_layer, "C" => poly2_con, "W" => sub}) + + # PPOLYF_U_DW_2K + extract_devices(resistor_with_bulk("ppolyf_u_2k_dw", 2000, BResistor), { "R" => ppolyf_u_2k_dw_layer, "C" => poly2_con, "W" => dnwell }) + + # PPOLYF_U_2K_6p0 + extract_devices(resistor_with_bulk("ppolyf_u_2k_6p0", 2000, BResistor), { "R" => ppolyf_u_2k_6p0_layer, "C" => poly2_con, "W" => sub}) + + # PPOLYF_U_DW_2K_6p0 + extract_devices(resistor_with_bulk("ppolyf_u_2k_6p0_dw", 2000, BResistor), { "R" => ppolyf_u_2k_6p0_dw_layer, "C" => poly2_con, "W" => dnwell }) + +elsif POLY_RES == "3k" + + # PPOLYF_U_3K + extract_devices(resistor_with_bulk("ppolyf_u_3k", 3000, BResistor), { "R" => ppolyf_u_3k_layer, "C" => poly2_con, "W" => sub}) + + # PPOLYF_U_DW_3K + extract_devices(resistor_with_bulk("ppolyf_u_3k_dw", 3000, BResistor), { "R" => ppolyf_u_3k_dw_layer, "C" => poly2_con, "W" => dnwell }) + + # PPOLYF_U_3K_6p0 + extract_devices(resistor_with_bulk("ppolyf_u_3k_6p0", 3000, BResistor), { "R" => ppolyf_u_3k_6p0_layer, "C" => poly2_con, "W" => sub}) + + # PPOLYF_U_DW_3K_6p0 + extract_devices(resistor_with_bulk("ppolyf_u_3k_6p0_dw", 3000, BResistor), { "R" => ppolyf_u_3k_6p0_dw_layer, "C" => poly2_con, "W" => dnwell }) + +end + + +# =============== +# ---- METAL ---- +# =============== + +# RM1 +logger.info("Extracting RM1 device") +extract_devices(resistor("rm1", 0.09, NResistor), { "R" => rm1_res, "C" => metal1_con }) + +# RM2 +logger.info("Extracting RM2 device") +extract_devices(resistor("rm2", 0.09, NResistor), { "R" => rm2_res, "C" => metal2_ncap }) + +# RM3 +logger.info("Extracting RM3 device") +extract_devices(resistor("rm3", 0.09, NResistor), { "R" => rm3_res, "C" => metal3_ncap }) + +if METAL_TOP == "6K" + + # TM6K + logger.info("Extracting TM6K device") + extract_devices(resistor("tm6k", 0.06, NResistor), { "R" => tm_res, "C" => metaltop_con }) + +elsif METAL_TOP == "9K" + + # TM9K + logger.info("Extracting TM9K device") + extract_devices(resistor("tm9k", 0.04, NResistor), { "R" => tm_res, "C" => metaltop_con }) + +elsif METAL_TOP == "11K" + + # TM11K + logger.info("Extracting TM11K device") + extract_devices(resistor("tm11k", 0.04, NResistor), { "R" => tm_res, "C" => metaltop_con }) + +elsif METAL_TOP == "30K" + + # TM30K + logger.info("Extracting TM30K device") + extract_devices(resistor("tm30k", 0.0095, NResistor), { "R" => tm_res, "C" => metaltop_con }) + +end + + +#================================== +# ------- MIMCAP EXTRACTION ------- +#================================== +logger.info("Starting MIMCAP EXTRACTION") + +if MIM_OPTION == "A" + + if MIM_CAP == "1" + + # mim_1p0fF capacitor + logger.info("Extracting mim_1p0fF device") + extract_devices(capacitor("mim_1p0fF", 1.0e-15, MIMCap), { "P1" => mim_virtual, "P2" => fuse_cap }) + tolerance("mim_1p0fF", "C", :relative => 0.25) + + elsif MIM_CAP == "1.5" + + # mim_1p5fF capacitor + logger.info("Extracting mim_1p5fF device") + extract_devices(capacitor("mim_1p5fF", 1.5e-15, MIMCap), { "P1" => mim_virtual, "P2" => fuse_cap }) + tolerance("mim_1p5fF", "C", :relative => 0.25) + + elsif MIM_CAP == "2" + + # mim_single_2p0fF capacitor + logger.info("Extracting mim_single_2p0fF device") + extract_devices(capacitor("mim_single_2p0fF", 2.0e-15, MIMCap), { "P1" => mim_virtual, "P2" => fuse_cap }) + tolerance("mim_single_2p0fF", "C", :relative => 0.25) + + end + +elsif MIM_OPTION == "B" + + if MIM_CAP == "1" + + # mim_1p0fF capacitor + logger.info("Extracting mim_1p0fF device") + extract_devices(capacitor("mim_1p0fF", 1.0e-15, MIMCap), { "P1" => mimtm_virtual, "P2" => fuse_cap }) + tolerance("mim_1p0fF", "C", :relative => 0.25) + + elsif MIM_CAP == "1.5" + + # mim_1p5fF capacitor + logger.info("Extracting mim_1p5fF device") + extract_devices(capacitor("mim_1p5fF", 1.5e-15, MIMCap), { "P1" => mimtm_virtual, "P2" => fuse_cap }) + tolerance("mim_1p5fF", "C", :relative => 0.25) + + elsif MIM_CAP == "2" + + # mim_single_2p0fF capacitor + logger.info("Extracting mim_single_2p0fF device") + extract_devices(capacitor("mim_single_2p0fF", 2.0e-15, MIMCap), { "P1" => mimtm_virtual, "P2" => fuse_cap }) + tolerance("mim_single_2p0fF", "C", :relative => 0.25) + + end + +end + + +#================================== +# ------- MOSCAP EXTRACTION ------- +#================================== +logger.info("Starting MOSCAP EXTRACTION") + +#nmoscap_3p3 +logger.info("Extracting nmoscap_3p3 device") +extract_devices(capacitor("nmoscap_3p3", 4.4e-15, MosCap), { "P1" => nmos_gate_3p3, "P2" => lvpwell_con, "tA" => poly2_con, "tB" => nsd}) + +#nmoscap_3p3_dw +logger.info("Extracting nmoscap_3p3_dw device") +extract_devices(capacitor("nmoscap_3p3_dw", 4.4e-15, MosCap), { "P1" => nmos_gate_3p3_dw, "P2" => lvpwell_con, "tA" => poly2_con, "tB" => nsd }) + +#pmoscap_3p3 +logger.info("Extracting pmoscap_3p3 device") +extract_devices(capacitor("pmoscap_3p3", 4.4e-15, MosCap), { "P1" => pmos_gate_3p3, "P2" => nwell_con, "tA" => poly2_con, "tB" => psd }) + +#pmoscap_3p3_dw +logger.info("Extracting pmoscap_3p3_dw device") +extract_devices(capacitor("pmoscap_3p3_dw", 4.4e-15, MosCap), { "P1" => pmos_gate_3p3_dw, "P2" => dnwell, "tA" => poly2_con, "tB" => psd_dw }) + +#nmoscap_6p0 +logger.info("Extracting nmoscap_6p0 device") +extract_devices(capacitor("nmoscap_6p0", 2.3e-15, MosCap), { "P1" => nmos_gate_6p0, "P2" => lvpwell_con, "tA" => poly2_con, "tB" => nsd }) + +#nmoscap_6p0_dw +logger.info("Extracting nmoscap_6p0_dw device") +extract_devices(capacitor("nmoscap_6p0_dw", 2.3e-15, MosCap), { "P1" => nmos_gate_6p0_dw, "P2" => lvpwell_con, "tA" => poly2_con, "tB" => nsd }) + +#pmoscap_6p0 +logger.info("Extracting pmoscap_6p0 device") +extract_devices(capacitor("pmoscap_6p0", 2.3e-15, MosCap), { "P1" => pmos_gate_6p0, "P2" => nwell_con, "tA" => poly2_con, "tB" => psd }) + +#pmoscap_6p0 +logger.info("Extracting pmoscap_6p0 device") +extract_devices(capacitor("pmoscap_6p0_dw", 2.3e-15, MosCap), { "P1" => pmos_gate_6p0_dw, "P2" => dnwell, "tA" => poly2_con, "tB" => psd_dw }) + +# nmoscap_3p3_b capacitor +extract_devices(capacitor("nmoscap_3p3_b", 4.4e-15, MosCap), { "P1" => nmoscap_3p3_b, "P2" => nwell_con, "tA" => poly2_con, "tB" => ntap }) + +#pmoscap_3p3_b +logger.info("Extracting pmoscap_3p3_b device") +extract_devices(capacitor("pmoscap_3p3_b", 4.4e-15, MosCap), { "P1" => pmoscap_3p3_b, "P2" => ptap, "tA" => poly2_con, "tB" => ptap }) + +#nmoscap_6p0_b +logger.info("Extracting nmoscap_6p0_b device") +extract_devices(capacitor("nmoscap_6p0_b", 2.3e-15, MosCap), { "P1" => nmoscap_6p0_b, "P2" => nwell_con, "tA" => poly2_con, "tB" => ntap }) + +#pmoscap_6p0_b +logger.info("Extracting pmoscap_6p0_b device") +extract_devices(capacitor("pmoscap_6p0_b", 2.3e-15, MosCap), { "P1" => pmoscap_6p0_b, "P2" => ptap, "tA" => poly2_con, "tB" => ptap }) + + +#================================ +# ------- ESD EXTRACTION -------- +#================================ +logger.info("Starting MOS SAB EXTRACTION") + +# ============== +# ---- PMOS ---- +# ============== +logger.info("Starting PMOS SAB EXTRACTION") + +#3.3V ESD PMOS transistor outside DNWELL +logger.info("Extracting 3.3V ESD PMOS transistor outside DNWELL device") +extract_devices(mos4("pmos_3p3_sab"), { "SD" => psd, "G" => pgate_sab_3p3v, "tS" => psd, "tD" => psd, "tG" => poly2_con, "W" => nwell_con }) + +#5V ESD PMOS transistor outside DNWELL +logger.info("Extracting 5V ESD PMOS transistor outside DNWELL device") +extract_devices(mos4("pmos_5p0_sab"), { "SD" => psd, "G" => pgate_sab_5v, "tS" => psd, "tD" => psd, "tG" => poly2_con, "W" => nwell_con }) + +#6V ESD PMOS transistor outside DNWELL +logger.info("Extracting 6V ESD PMOS transistor outside DNWELL device") +extract_devices(mos4("pmos_6p0_sab"), { "SD" => psd, "G" => pgate_sab_6v, "tS" => psd, "tD" => psd, "tG" => poly2_con, "W" => nwell_con }) + +#3.3V ESD PMOS transistor inside DNWELL +logger.info("Extracting 3.3V ESD PMOS transistor inside DNWELL device") +extract_devices(mos4("pmos_3p3_dw_sab"), { "SD" => psd_dw, "G" => pgate_dw_sab_3p3v, "tS" => psd_dw, "tD" => psd_dw, "tG" => poly2_con, "W" => dnwell }) + +#5V ESD PMOS transistor inside DNWELL +logger.info("Extracting 5V ESD PMOS transistor inside DNWELL device") +extract_devices(mos4("pmos_5p0_dw_sab"), { "SD" => psd_dw, "G" => pgate_dw_sab_5v, "tS" => psd_dw, "tD" => psd_dw, "tG" => poly2_con, "W" => dnwell }) + +#6V ESD PMOS transistor inside DNWELL +logger.info("Extracting 6V ESD PMOS transistor inside DNWELL device") +extract_devices(mos4("pmos_6p0_dw_sab"), { "SD" => psd_dw, "G" => pgate_dw_sab_6v, "tS" => psd_dw, "tD" => psd_dw, "tG" => poly2_con, "W" => dnwell }) + +# ============== +# ---- NMOS ---- +# ============== +logger.info("Starting NMOS SAB EXTRACTION") + +#3.3V ESD NMOS transistor outside DNWELL +logger.info("Extracting 3.3V ESD NMOS transistor outside DNWELL device") +extract_devices(mos4("nmos_3p3_sab"), { "SD" => nsd, "G" => ngate_sab_3p3v, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => sub }) + +#5V ESD NMOS transistor outside DNWELL +logger.info("Extracting 5V ESD NMOS transistor outside DNWELL device") +extract_devices(mos4("nmos_5p0_sab"), { "SD" => nsd, "G" => ngate_sab_5v, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => sub }) + +#6V ESD NMOS transistor outside DNWELL +logger.info("Extracting 6V ESD NMOS transistor outside DNWELL device") +extract_devices(mos4("nmos_6p0_sab"), { "SD" => nsd, "G" => ngate_sab_6v, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => sub }) + +#3.3V ESD NMOS transistor inside DNWELL +logger.info("Extracting 3.3V ESD NMOS transistor inside DNWELL device") +extract_devices(mos4("nmos_3p3_dw_sab"), { "SD" => nsd, "G" => ngate_dw_sab_3p3v, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => lvpwell_con }) + +#5V ESD NMOS transistor inside DNWELL +logger.info("Extracting 5V ESD NMOS transistor inside DNWELL device") +extract_devices(mos4("nmos_5p0_dw_sab"), { "SD" => nsd, "G" => ngate_dw_sab_5v, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => lvpwell_con }) + +#6V ESD NMOS transistor inside DNWELL +logger.info("Extracting 6V ESD NMOS transistor inside DNWELL device") +extract_devices(mos4("nmos_6p0_dw_sab"), { "SD" => nsd, "G" => ngate_dw_sab_6v, "tS" => nsd, "tD" => nsd, "tG" => poly2_con, "W" => lvpwell_con }) + + +#================================ +# ------ EFUSE EXTRACTIONS ------ +#================================ +logger.info("Starting EFUSE EXTRACTION") + +extract_devices(resistor("efuse", 28.5714), { "R" => efuse_link, "C" => efuse_con_layer, "tA" => anode, "tB" => cathode }) +ignore_parameter("efuse", "R") + + +#================================================ +#------------- COMPARISON OPTIONS --------------- +#================================================ + +logger.info("Starting GF180 LVS comparison section") + +#=== FLATTEN CELLS === +align + +#=== NETLIST EXTRACTION === +if SIMPLIFY + netlist.simplify +end + +#=== NETLIST OPTIONS === +if NET_ONLY + netlist +end + +if TOP_LVL_PINS + netlist.make_top_level_pins +end + +if COMBINE + netlist.combine_devices +end + +if PURGE + netlist.purge +end + +if PURGE_NETS + netlist.purge_nets +end + +#=== SCHEMATIC OPTIONS === +if SCH_SIMPLE + schematic.simplify +end + +#=== IGNORE EXTREME VALUES === +max_res(1e7) +min_caps(1e-16) + + +compare + +exec_end_time = Time.now +run_time = exec_end_time - exec_start_time +logger.info("DRC Total Run time %f seconds" % [run_time]) + + + + +if ! compare + logger.info("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx") + logger.error("ERROR : Netlists don't match") + logger.info("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx") +else + logger.info("==========================================") + logger.info("INFO : Congratulations! Netlists match.") + logger.info("==========================================") +end + + + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/lvs/run_lvs.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/lvs/run_lvs.py new file mode 100644 index 000000000..e9a6bddd5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/lvs/run_lvs.py @@ -0,0 +1,132 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Run GlobalFoundries 180nm MCU LVS. + +Usage: + run_lvs.py (--help| -h) + run_lvs.py (--design=) (--net=) (--gf180mcu=) [--thr=] [--run_mode=] [--lvs_sub=] [--no_net_names] [--set_spice_comments] [--set_scale] [--set_verbose] [--set_schematic_simplify] [--set_net_only] [--set_top_lvl_pins] [--set_combine] [--set_purge] [--set_purge_nets] + +Options: + --help -h Print this help message. + --design= The input GDS file path. + --net= The input netlist file path. + --gf180mcu= Select combined options of metal_top, mim_option, and metal_level. Allowed values (A, B, C). + gf180mcu=A: Select metal_top=30K mim_option=A metal_level=3LM poly_res=1K, and mim_cap=2 + gf180mcu=B: Select metal_top=11K mim_option=B metal_level=4LM poly_res=1K, and mim_cap=2 + gf180mcu=C: Select metal_top=9K mim_option=B metal_level=5LM poly_res=1K, and mim_cap=2 + --thr= Number of cores to be used by LVS checker + --run_mode= Select klayout mode Allowed modes (flat , deep, tiling). [default: deep] + --lvs_sub= Assign the substrate name used in design. + --no_net_names Discard net names in extracted netlist. + --set_spice_comments Set netlist comments in extracted netlist. + --set_scale Set scale of 1e6 in extracted netlist. + --set_verbose Set verbose mode. + --set_schematic_simplify Set schematic simplification in input netlist. + --set_net_only Set netlist object creation only in extracted netlist. + --set_top_lvl_pins Set top level pins only in extracted netlist. + --set_combine Set netlist combine only in extracted netlist. + --set_purge Set netlist purge all only in extracted netlist. + --set_purge_nets Set netlist purge nets only in extracted netlist. +""" + +from docopt import docopt +import os +import logging + +def main(): + + # Switches used in run + switches = '' + + if args["--run_mode"] in ["flat" , "deep", "tiling"]: + switches = switches + f'-rd run_mode={args["--run_mode"]} ' + else: + logging.error("Allowed klayout modes are (flat , deep , tiling) only") + exit() + + if args["--gf180mcu"] == "A": + switches = switches + f'-rd metal_top=30K -rd mim_option=A -rd metal_level=3LM -rd poly_res=1K -rd mim_cap=2 ' + elif args["--gf180mcu"] == "B": + switches = switches + f'-rd metal_top=11K -rd mim_option=B -rd metal_level=4LM -rd poly_res=1K -rd mim_cap=2 ' + elif args["--gf180mcu"] == "C": + switches = switches + f'-rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd poly_res=1K -rd mim_cap=2 ' + else: + print("gf180mcu switch allowed values are (A , B, C) only") + exit() + + + switches = switches + '-rd spice_net_names=false ' if args["--no_net_names"] else switches + '-rd spice_net_names=true ' + + switches = switches + '-rd spice_comments=true ' if args["--set_spice_comments"] else switches + '-rd spice_comments=false ' + + switches = switches + '-rd scale=true ' if args["--set_scale"] else switches + '-rd scale=false ' + + switches = switches + '-rd verbose=true ' if args["--set_verbose"] else switches + '-rd verbose=false ' + + switches = switches + '-rd schematic_simplify=true ' if args["--set_schematic_simplify"] else switches + '-rd schematic_simplify=false ' + + switches = switches + '-rd net_only=true ' if args["--set_net_only"] else switches + '-rd net_only=false ' + + switches = switches + '-rd top_lvl_pins=true ' if args["--set_top_lvl_pins"] else switches + '-rd top_lvl_pins=false ' + + switches = switches + '-rd combine=true ' if args["--set_combine"] else switches + '-rd combine=false ' + + switches = switches + '-rd purge=true ' if args["--set_purge"] else switches + '-rd purge=false ' + + switches = switches + '-rd purge_nets=true ' if args["--set_purge_nets"] else switches + '-rd purge_nets=false ' + + switches = switches + f'-rd lvs_sub={args["--lvs_sub"]} ' if args["--lvs_sub"] else switches + + + # Generate databases + if args["--design"]: + path = args["--design"] + if args["--design"]: + file_name = args["--net"].split('.') + else: + print("The script must be given a netlist file or a path to be able to run LVS") + exit() + + os.system(f"klayout -b -r gf180mcu.lvs -rd input={path} -rd report={file_name[0]}.lyrdb -rd schematic={args['--net']} -rd target_netlist=extracted_netlist_{file_name[0]}.cir -rd thr={workers_count} {switches}") + + else: + print("The script must be given a layout file or a path to be able to run LVS") + exit() + + +if __name__ == "__main__": + + logging.basicConfig(level=logging.DEBUG, format=f"%(asctime)s | %(levelname)-7s | %(message)s", datefmt='%d-%b-%Y %H:%M:%S') + + # Args + args = docopt(__doc__, version='LVS Checker: 0.1') + workers_count = os.cpu_count()*2 if args["--thr"] == None else int(args["--thr"]) + + # Env. variables + pdk_root = os.environ['PDK_ROOT'] + pdk = os.environ['PDK'] + + # ========= Checking Klayout version ========= + klayout_v_ = os.popen("klayout -v").read() + klayout_v_ = klayout_v_.split("\n")[0] + klayout_v = int (klayout_v_.split(".") [-1]) + + if klayout_v < 8: + logging.warning("Using this klayout version has not been assesed in this development. Limits are unknown") + logging.info(f"Your version is: {klayout_v_}" ) + logging.info(f"Prerequisites at a minimum: KLayout 0.27.8") + + # Calling main function + main() diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/README.md b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/README.md new file mode 100644 index 000000000..882d5558c --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/README.md @@ -0,0 +1,3 @@ +# Pymacros (Pcells) + +Contains klayout pcells generator. diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/__init__.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/__init__.py new file mode 100644 index 000000000..ad96f0e36 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/__init__.py @@ -0,0 +1,93 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#============================================================================ +# ---------------- Pcells Generators for Klayout of GF180MCU ---------------- +#============================================================================ + +import pya + +from .mos import * +from .diode import * +from .bjt import * +from .moscap import * +from .mimcap import * +from .res import * +from .efuse import * + + +# It's a Python class that inherits from the pya.Library class +class gf180mcu(pya.Library): + """ + The library where we will put the PCell into + """ + + def __init__(self): + # Set the description + self.description = "GF180MCU Pcells" + + # Create the PCell declarations + # MOS DEVICES + self.layout().register_pcell("nmos", nmos()) # nmos_3p3 , nmos_5p0 , nmos_6p0 + self.layout().register_pcell("pmos", pmos()) # pmos_3p3 , pmos_5p0 , pmos_6p0 + self.layout().register_pcell("nmos_6p0_nat", nmos_6p0_nat()) + self.layout().register_pcell("nmos_10p0_asym", nmos_10p0_asym()) + self.layout().register_pcell("pmos_10p0_asym", pmos_10p0_asym()) + + # BJT + self.layout().register_pcell("npn_bjt", npn_bjt()) # vnpn_10x10 , vnpn_5x5 , vnpn_0p54x16 , vnpn_0p54x8 , vnpn_0p54x4 , vnpn_0p54x2 + self.layout().register_pcell("pnp_bjt", pnp_bjt()) # vpnp_10x10 , vpnp_5x5 , vpnp_0p42x10 , vpnp_0p42x5 + + # DIODE DEVICES + self.layout().register_pcell("np_diode" , np_diode() ) # np_3p3 , np_6p0 + self.layout().register_pcell("pn_diode" , pn_diode() ) # pn_3p3 , pn_6p0 + self.layout().register_pcell("nwp_diode" , nwp_diode() ) # nwp_3p3 , nwp_6p0 + self.layout().register_pcell("dnwpw_diode", dnwpw_diode()) # dnwpw_3p3 , dnwpw_6p0 + self.layout().register_pcell("dnwps_diode", dnwps_diode()) # dnwps_3p3 , dnwps_6p0 + self.layout().register_pcell("sc_diode" , sc_diode() ) + + #MOSCAP + self.layout().register_pcell("nmoscap" , nmoscap() ) # nmoscap_3p3 , nmoscap_6p0 + self.layout().register_pcell("pmoscap" , pmoscap() ) # pmoscap_3p3 , pmoscap_6p0 + self.layout().register_pcell("nmoscap_b", nmoscap_b()) # nmoscap_3p3_b , nmoscap_6p0_b + self.layout().register_pcell("pmoscap_b", pmoscap_b()) # pmoscap_3p3_b , pmoscap_6p0_b + + #MIMCAP + self.layout().register_pcell("mimcap" , mimcap()) #mimcap (Option-A) , mimcap_tm (Option-B) + + #RES + self.layout().register_pcell("metal_resistor" , metal_resistor() ) + + self.layout().register_pcell("nplus_s_resistor" , nplus_s_resistor() ) + self.layout().register_pcell("pplus_s_resistor" , pplus_s_resistor() ) + + self.layout().register_pcell("nplus_u_resistor" , nplus_u_resistor() ) + self.layout().register_pcell("pplus_u_resistor" , pplus_u_resistor() ) + + self.layout().register_pcell("nwell_resistor" , nwell_resistor() ) + self.layout().register_pcell("pwell_resistor" , pwell_resistor() ) + + self.layout().register_pcell("npolyf_s_resistor" , npolyf_s_resistor()) + self.layout().register_pcell("ppolyf_s_resistor" , ppolyf_s_resistor()) + + self.layout().register_pcell("npolyf_u_resistor" , npolyf_u_resistor()) + self.layout().register_pcell("ppolyf_u_resistor" , ppolyf_u_resistor()) + + self.layout().register_pcell("ppolyf_u_high_Rs_resistor" , ppolyf_u_high_Rs_resistor()) + + #eFuse + # self.layout().register_pcell("efuse" , efuse()) + + # Register us with the name "gf180mcu". + self.register("gf180mcu") diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt.py new file mode 100644 index 000000000..1b92f6625 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt.py @@ -0,0 +1,147 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +# BJT Generator for GF180MCU +######################################################################################################################## + +import pya +from .draw_bjt import * + + +class npn_bjt(pya.PCellDeclarationHelper): + """ + NPN BJT Generator for GF180MCU + """ + + def __init__(self): + + # Important: initialize the super class + super(npn_bjt, self).__init__() + self.Type_handle = self.param("Type", self.TypeList, "Type") + self.Type_handle.add_choice("vnpn_10x10", "vnpn_10x10") + self.Type_handle.add_choice("vnpn_5x5", "vnpn_5x5") + self.Type_handle.add_choice("vnpn_0p54x16", "vnpn_0p54x16") + self.Type_handle.add_choice("vnpn_0p54x8", "vnpn_0p54x8") + self.Type_handle.add_choice("vnpn_0p54x4", "vnpn_0p54x4") + self.Type_handle.add_choice("vnpn_0p54x2", "vnpn_0p54x2") + self.param("Model", self.TypeString, "Model", default="gf180mcu_fd_pr__npn",readonly=True) + + def display_text_impl(self): + # Provide a descriptive text for the cell + return str(self.Type) + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the + # numeric parameter has changed (by comparing against the effective + # radius ru) and set ru to the effective radius. We also update the + # numerical value or the shape, depending on which on has not changed. + pass + + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + # return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + pass + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + # self.r = self.shape.bbox().width() * self.layout.dbu / 2 + # self.l = self.layout.get_info(self.layer) + pass + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + # return pya.Trans(self.shape.bbox().center()) + pass + + def produce_impl(self): + + # This is the main part of the implementation: create the layout + + self.percision = 1/self.layout.dbu + npn_instance = draw_npn(layout=self.layout,device_name=self.Type) + write_cells = pya.CellInstArray(npn_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0),1 , 1) + + self.cell.flatten(1) + self.cell.insert(write_cells) + self.layout.cleanup() + +class pnp_bjt(pya.PCellDeclarationHelper): + """ + PNP BJT Generator for GF180MCU + """ + + def __init__(self): + + # Important: initialize the super class + super(pnp_bjt, self).__init__() + self.Type_handle = self.param("Type", self.TypeList, "Type") + self.Type_handle.add_choice("vpnp_10x10", "vpnp_10x10") + self.Type_handle.add_choice("vpnp_5x5", "vpnp_5x5") + self.Type_handle.add_choice("vpnp_0p42x10", "vpnp_0p42x10") + self.Type_handle.add_choice("vpnp_0p42x5", "vpnp_0p42x5") + self.param("Model", self.TypeString, "Model", default="gf180mcu_fd_pr__pnp",readonly=True) + + def display_text_impl(self): + # Provide a descriptive text for the cell + return str(self.Type) + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the + # numeric parameter has changed (by comparing against the effective + # radius ru) and set ru to the effective radius. We also update the + # numerical value or the shape, depending on which on has not changed. + pass + + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + # return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + pass + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + # self.r = self.shape.bbox().width() * self.layout.dbu / 2 + # self.l = self.layout.get_info(self.layer) + pass + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + # return pya.Trans(self.shape.bbox().center()) + pass + + def produce_impl(self): + + # This is the main part of the implementation: create the layout + + self.percision = 1/self.layout.dbu + pnp_instance = draw_pnp(layout=self.layout,device_name=self.Type) + write_cells = pya.CellInstArray(pnp_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0),1 , 1) + + self.cell.flatten(1) + self.cell.insert(write_cells) + self.layout.cleanup() + + + + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vnpn_0p54x16.gds b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vnpn_0p54x16.gds new file mode 100644 index 000000000..1215796f1 Binary files /dev/null and b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vnpn_0p54x16.gds differ diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vnpn_0p54x2.gds b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vnpn_0p54x2.gds new file mode 100644 index 000000000..bdc6a26aa Binary files /dev/null and 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b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vnpn_10x10.gds new file mode 100644 index 000000000..e5332d683 Binary files /dev/null and b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vnpn_10x10.gds differ diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vnpn_5x5.gds b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vnpn_5x5.gds new file mode 100644 index 000000000..8da96d9d3 Binary files /dev/null and b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vnpn_5x5.gds differ diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_0p42x10.gds b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_0p42x10.gds new file mode 100644 index 000000000..ac927fa20 Binary files /dev/null and b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_0p42x10.gds differ diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_0p42x5.gds b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_0p42x5.gds new file mode 100644 index 000000000..eb79d09b5 Binary files /dev/null and b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_0p42x5.gds differ diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_10x10.gds b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_10x10.gds new file mode 100644 index 000000000..d7fca8090 Binary files /dev/null and b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_10x10.gds differ diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_5x5.gds b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_5x5.gds new file mode 100644 index 000000000..f0aad50e2 Binary files /dev/null and b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/bjt/vpnp_5x5.gds differ diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/diode.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/diode.py new file mode 100644 index 000000000..5fef0c1b4 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/diode.py @@ -0,0 +1,395 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +# Diode Generator for GF180MCU +######################################################################################################################## + +import pya +from .draw_diode import * + +np_l = 0.36 +np_w = 0.22 + +pn_l = 0.36 +pn_w = 0.22 + +nwp_l = 0.36 +nwp_w = 0.22 + +dnwpw_l = 0.36 +dnwpw_w = 0.22 + +dnwps_l = 0.36 +dnwps_w = 0.22 + +sc_l = 1 +sc_w = 0.62 + +class np_diode(pya.PCellDeclarationHelper): + """ + N+/LVPWELL diode (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(np_diode, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.Type_handle = self.param("volt", self.TypeList, "Voltage area") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5/6V", "5/6V") + + self.param("l", self.TypeDouble,"Length", default=np_l, unit="um") + self.param("w", self.TypeDouble,"Width", default=np_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "np_diode(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < np_l: + self.l = np_l + if (self.w) < np_w: + self.w = np_l + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + np_instance = draw_np_diode(self.layout, self.l, self.w , self.volt, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class pn_diode(pya.PCellDeclarationHelper): + """ + P+/Nwell diode (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(pn_diode, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.Type_handle = self.param("volt", self.TypeList, "Voltage area") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5/6V", "5/6V") + + self.param("l", self.TypeDouble,"Length", default=pn_l, unit="um") + self.param("w", self.TypeDouble,"Width", default=pn_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "pn_diode(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < pn_l: + self.l = pn_l + if (self.w) < pn_w: + self.w = pn_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + np_instance = draw_pn_diode(self.layout, self.l, self.w ,self.volt, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class nwp_diode(pya.PCellDeclarationHelper): + """ + Nwell/Psub diode Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(nwp_diode, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.Type_handle = self.param("volt", self.TypeList, "Voltage area") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5/6V", "5/6V") + + self.param("l", self.TypeDouble,"Length", default=nwp_l, unit="um") + self.param("w", self.TypeDouble,"Width", default=nwp_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "nwp_diode(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < nwp_l: + self.l = nwp_l + if (self.w) < nwp_w: + self.w = nwp_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + nwp_instance = draw_nwp_diode(self.layout, self.l, self.w , self.volt) + write_cells = pya.CellInstArray(nwp_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class dnwpw_diode(pya.PCellDeclarationHelper): + """ + LVPWELL/DNWELL diode Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(dnwpw_diode, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.Type_handle = self.param("volt", self.TypeList, "Voltage area") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5/6V", "5/6V") + + self.param("l", self.TypeDouble,"Length", default=dnwpw_l, unit="um") + self.param("w", self.TypeDouble,"Width", default=dnwpw_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "dnwpw_diode(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < dnwpw_l: + self.l = dnwpw_l + if (self.w) < dnwpw_w: + self.w = dnwpw_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dnwpw_instance = draw_dnwpw_diode(self.layout, self.l, self.w , self.volt) + write_cells = pya.CellInstArray(dnwpw_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class dnwps_diode(pya.PCellDeclarationHelper): + """ + LVPWELL/DNWELL diode Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(dnwps_diode, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.Type_handle = self.param("volt", self.TypeList, "Voltage area") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5/6V", "5/6V") + + self.param("l", self.TypeDouble,"Length", default=dnwps_l, unit="um") + self.param("w", self.TypeDouble,"Width", default=dnwps_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "dnwps_diode(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < dnwps_l: + self.l = dnwps_l + if (self.w) < dnwps_w: + self.w = dnwps_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dnwps_instance = draw_dnwps_diode(self.layout, self.l, self.w , self.volt) + write_cells = pya.CellInstArray(dnwps_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class sc_diode(pya.PCellDeclarationHelper): + """ + N+/LVPWELL diode (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(sc_diode, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.param("l", self.TypeDouble,"Length", default=sc_l, unit="um") + self.param("w", self.TypeDouble,"Width", default=sc_w, unit="um",readonly=True) + self.param("m", self.TypeDouble,"no. of fingers", default=4) + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "sc_diode(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < sc_l: + self.l = sc_l + if (self.w) != sc_w: + self.w = sc_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + sc_instance = draw_sc_diode(self.layout, self.l, self.w , self.m, self.pcmpgr) + write_cells = pya.CellInstArray(sc_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + + self.cell.insert(write_cells) + self.cell.flatten(1) diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_bjt.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_bjt.py new file mode 100644 index 000000000..2b81ac22b --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_bjt.py @@ -0,0 +1,66 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +## BJT Pcells Generators for Klayout of GF180MCU +######################################################################################################################## + +import pya +import os + +USER = os.environ['USER'] +gds_path = f"/home/{USER}/.klayout/pymacros/cells/bjt" + + +def draw_npn(layout, device_name): + + if device_name == "vnpn_10x10": + layout.read(f"{gds_path}/vnpn_10x10.gds") + cell_name = "vnpn_10x10" + elif device_name == "vnpn_5x5": + layout.read(f"{gds_path}/vnpn_5x5.gds") + cell_name = "vnpn_5x5" + elif device_name == "vnpn_0p54x16": + layout.read(f"{gds_path}/vnpn_0p54x16.gds") + cell_name = "vnpn_0p54x16" + elif device_name == "vnpn_0p54x8": + layout.read(f"{gds_path}/vnpn_0p54x8.gds") + cell_name = "vnpn_0p54x8" + elif device_name == "vnpn_0p54x4": + layout.read(f"{gds_path}/vnpn_0p54x4.gds") + cell_name = "vnpn_0p54x4" + elif device_name == "vnpn_0p54x2": + layout.read(f"{gds_path}/vnpn_0p54x2.gds") + cell_name = "vnpn_0p54x2" + + return layout.cell(cell_name) + + +def draw_pnp(layout, device_name): + + if device_name == "vpnp_10x10": + layout.read(f"{gds_path}/vpnp_10x10.gds") + cell_name = "vpnp_10x10" + elif device_name == "vpnp_5x5": + layout.read(f"{gds_path}/vpnp_5x5.gds") + cell_name = "vpnp_5x5" + elif device_name == "vpnp_0p42x10": + layout.read(f"{gds_path}/vpnp_0p42x10.gds") + cell_name = "vpnp_0p42x10" + elif device_name == "vpnp_0p42x5": + layout.read(f"{gds_path}/vpnp_0p42x5.gds") + cell_name = "vpnp_0p42x5" + + return layout.cell(cell_name) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_diode.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_diode.py new file mode 100644 index 000000000..a272d04e9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_diode.py @@ -0,0 +1,847 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +## Diode Pcells Generators for Klayout of GF180MCU +######################################################################################################################## + +import pya + +def number_spc_contacts(box_width, min_enc, cont_spacing, cont_width): + """ Calculate number of cantacts in a given dimensions and the free space for symmetry. + By getting the min enclosure,the width of the box,the width ans spacing of the contacts. + Parameters + ----- + box_width (double) : length you place the via or cont. in + min_enc (double) : spacing between the edge of the box and the first contact. + cont_spacing (double) : spacing between different contacts + cont_width (double) : contacts in the same direction + """ + spc_cont = box_width - 2 * min_enc + num_cont = int((spc_cont + cont_spacing) / (cont_width + cont_spacing)) + free_spc = box_width - (num_cont * cont_width + + (num_cont - 1) * cont_spacing) + return num_cont, free_spc + +def draw_np_diode(layout, l, w , volt, deepnwell, pcmpgr): + ''' + Usage:- + used to draw N+/LVPWELL diode (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + volt : String of operating voltage of the diode [3.3V, 5V/6V] + deepnwell : Boolean of using Deep NWELL device + pcmpgr : Boolean of using P+ Guard Ring for Deep NWELL devices only + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + lvpwell = layout.layer(204, 0 ) + comp = layout.layer(22 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + dualgate = layout.layer(55 , 0 ) + diode_mk = layout.layer(115, 5 ) + + # Define variables + dbu_PERCISION = 1/layout.dbu + pcmp2ncmp_spc = 0.48 * dbu_PERCISION + ncmp_w = 0.36 * dbu_PERCISION + pcmp_w = w * dbu_PERCISION + cmp_l = l * dbu_PERCISION + implant_comp_enc = 0.16 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.28 * dbu_PERCISION + dualgate_cmp_enc = 0.24 * dbu_PERCISION + dg_enc_dnwell = 0.5 * dbu_PERCISION + dnwell_enc_lvpwell = 2.5 * dbu_PERCISION + lvpwell_enc_ncmp = 0.6 * dbu_PERCISION + lvpwell_enc_pcmp = 0.16 * dbu_PERCISION + min_cmp_area = 0.2025 * dbu_PERCISION * dbu_PERCISION + tie_violat = 0 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + + # Inserting np cell + cell_index = layout.add_cell("np_diode") + np_diode_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting diffusion + if (cmp_l * ncmp_w) < min_cmp_area: + tie_violat = (min_cmp_area/ncmp_w - cmp_l)/2 + np_diode_cell.shapes(comp).insert(pya.Box(0, -tie_violat, ncmp_w, cmp_l+tie_violat)) + np_diode_cell.shapes(pplus).insert(pya.Box(-implant_comp_enc, -implant_comp_enc-tie_violat, ncmp_w+implant_comp_enc, cmp_l+implant_comp_enc+tie_violat)) + + np_diode_cell.shapes(comp).insert(pya.Box(ncmp_w+pcmp2ncmp_spc, 0, ncmp_w+pcmp2ncmp_spc+pcmp_w, cmp_l)) + np_diode_cell.shapes(nplus).insert(pya.Box(ncmp_w+pcmp2ncmp_spc-implant_comp_enc, -implant_comp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+implant_comp_enc, cmp_l+implant_comp_enc)) + + # Inserting metal + np_diode_cell.shapes(metal1).insert(pya.Box(0, -tie_violat, ncmp_w, cmp_l+tie_violat)) + np_diode_cell.shapes(metal1).insert(pya.Box(ncmp_w+pcmp2ncmp_spc, 0, ncmp_w+pcmp2ncmp_spc+pcmp_w, cmp_l)) + + + # Inserting pcomp contacts + num_ncmp_con_1, ncmp_con_free_spc_1 = number_spc_contacts(ncmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_ncmp_con_2, ncmp_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + ncmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(ncmp_con_free_spc_1 / 2, ncmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_con_1, num_ncmp_con_2) + np_diode_cell.insert(ncmp_con_arr) + + # Inserting ncomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(pcmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(ncmp_w+pcmp2ncmp_spc+pcmp_con_free_spc_1 / 2, pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + np_diode_cell.insert(pcmp_con_arr) + + # Inserting Deep NWELL layers + if deepnwell == True: + np_diode_cell.shapes(lvpwell).insert(pya.Box(-lvpwell_enc_pcmp, -lvpwell_enc_ncmp, ncmp_w+pcmp2ncmp_spc+pcmp_w+lvpwell_enc_ncmp, cmp_l+lvpwell_enc_ncmp)) + np_diode_cell.shapes(dnwell).insert(pya.Box(-lvpwell_enc_pcmp-dnwell_enc_lvpwell, -lvpwell_enc_ncmp-dnwell_enc_lvpwell, ncmp_w+pcmp2ncmp_spc+pcmp_w+lvpwell_enc_ncmp+dnwell_enc_lvpwell, cmp_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell)) + + # Inserting Deep NWELL P+ Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw, ncmp_w+pcmp2ncmp_spc+pcmp_w+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw, cmp_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw) + cmp_outer = pya.Box(-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw-ncmp_w, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw-ncmp_w, ncmp_w+pcmp2ncmp_spc+pcmp_w+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+ncmp_w, cmp_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+ncmp_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + np_diode_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw+implant_comp_enc, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw+implant_comp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw-implant_comp_enc, cmp_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw-implant_comp_enc) + pp_outer = pya.Box(-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw-ncmp_w-implant_comp_enc, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw-ncmp_w-implant_comp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+ncmp_w+implant_comp_enc, cmp_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+ncmp_w+implant_comp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + np_diode_cell.shapes(pplus).insert(pp_gr) + + if volt == "5/6V": + # Inserting marker + np_diode_cell.shapes(diode_mk).insert(pya.Box(-dualgate_cmp_enc, -dualgate_cmp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+dualgate_cmp_enc, cmp_l+dualgate_cmp_enc)) + # Inserting dualgate + if deepnwell == True: + np_diode_cell.shapes(dualgate).insert(pya.Box(-lvpwell_enc_pcmp-dnwell_enc_lvpwell-dg_enc_dnwell, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-dg_enc_dnwell, ncmp_w+pcmp2ncmp_spc+pcmp_w+lvpwell_enc_ncmp+dnwell_enc_lvpwell+dg_enc_dnwell, cmp_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+dg_enc_dnwell)) + else: + np_diode_cell.shapes(dualgate).insert(pya.Box(-dualgate_cmp_enc, -dualgate_cmp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+dualgate_cmp_enc, cmp_l+dualgate_cmp_enc)) + else: + np_diode_cell.shapes(diode_mk).insert(pya.Box(-implant_comp_enc, -implant_comp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+implant_comp_enc, cmp_l+implant_comp_enc)) + + np_diode_cell.flatten(True) + return np_diode_cell + +def draw_pn_diode(layout, l, w , volt, deepnwell, pcmpgr): + ''' + Usage:- + used to draw 3.3V P+/Nwell diode (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diffusion length + w : Float of diffusion width + volt : String of operating voltage of the diode [3.3V, 5V/6V] + deepnwell : Boolean of using Deep NWELL device + pcmpgr : Boolean of using P+ Guard Ring for Deep NWELL devices only + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + nwell = layout.layer(21 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + dualgate = layout.layer(55 , 0 ) + diode_mk = layout.layer(115, 5 ) + + # Define variables + dbu_PERCISION = 1/layout.dbu + pcmp2ncmp_spc = 0.48 * dbu_PERCISION + ncmp_w = 0.36 * dbu_PERCISION + pcmp_w = w * dbu_PERCISION + cmp_l = l * dbu_PERCISION + implant_comp_enc = 0.16 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.28 * dbu_PERCISION + + nwell_ncmp_enc = 0.12 * dbu_PERCISION + nwell_pcmp_enc = 0.43 * dbu_PERCISION + dg_enc_dnwell = 0.5 * dbu_PERCISION + dnwell_enc_nwell = 0.5 * dbu_PERCISION + min_cmp_area = 0.2025 * dbu_PERCISION * dbu_PERCISION + tie_violat = 0 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + dnwell_violat = 0 * dbu_PERCISION + + if volt == "5/6V" or deepnwell == True: + nwell_ncmp_enc = 0.16 * dbu_PERCISION + nwell_pcmp_enc = 0.6 * dbu_PERCISION + dnwell_violat = 0.12 * dbu_PERCISION + + # Inserting pn cell + cell_index = layout.add_cell("pn_diode") + pn_diode_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting diffusion + if (cmp_l * ncmp_w) < min_cmp_area: + tie_violat = (min_cmp_area/ncmp_w - cmp_l)/2 + pn_diode_cell.shapes(comp).insert(pya.Box(0, -tie_violat, ncmp_w, cmp_l+tie_violat)) + pn_diode_cell.shapes(nplus).insert(pya.Box(-implant_comp_enc, -implant_comp_enc-tie_violat, ncmp_w+implant_comp_enc, cmp_l+implant_comp_enc+tie_violat)) + + pn_diode_cell.shapes(comp).insert(pya.Box(ncmp_w+pcmp2ncmp_spc, 0, ncmp_w+pcmp2ncmp_spc+pcmp_w, cmp_l)) + pn_diode_cell.shapes(pplus).insert(pya.Box(ncmp_w+pcmp2ncmp_spc-implant_comp_enc, -implant_comp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+implant_comp_enc, cmp_l+implant_comp_enc)) + + # Inserting metal + pn_diode_cell.shapes(metal1).insert(pya.Box(0, -tie_violat, ncmp_w, cmp_l+tie_violat)) + pn_diode_cell.shapes(metal1).insert(pya.Box(ncmp_w+pcmp2ncmp_spc, 0, ncmp_w+pcmp2ncmp_spc+pcmp_w, cmp_l)) + + # Inserting nwell + pn_diode_cell.shapes(nwell).insert(pya.Box(-nwell_ncmp_enc-dnwell_violat, -nwell_pcmp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+nwell_pcmp_enc, cmp_l+nwell_pcmp_enc)) + + + # Inserting pcomp contacts + num_ncmp_con_1, ncmp_con_free_spc_1 = number_spc_contacts(ncmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_ncmp_con_2, ncmp_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + ncmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(ncmp_con_free_spc_1 / 2, ncmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_con_1, num_ncmp_con_2) + pn_diode_cell.insert(ncmp_con_arr) + + # Inserting ncomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(pcmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(ncmp_w+pcmp2ncmp_spc+pcmp_con_free_spc_1 / 2, pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + pn_diode_cell.insert(pcmp_con_arr) + + # Inserting Deep NWELL layers + if deepnwell == True: + pn_diode_cell.shapes(dnwell).insert(pya.Box(-nwell_ncmp_enc-dnwell_enc_nwell-dnwell_violat, -nwell_pcmp_enc-dnwell_enc_nwell, ncmp_w+pcmp2ncmp_spc+pcmp_w+nwell_pcmp_enc+dnwell_enc_nwell, cmp_l+nwell_pcmp_enc+dnwell_enc_nwell)) + + # Inserting Deep NWELL P+ Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-nwell_ncmp_enc-dnwell_enc_nwell-pcmp_gr2dnw-dnwell_violat, -nwell_pcmp_enc-dnwell_enc_nwell-pcmp_gr2dnw, ncmp_w+pcmp2ncmp_spc+pcmp_w+nwell_pcmp_enc+dnwell_enc_nwell+pcmp_gr2dnw, cmp_l+nwell_pcmp_enc+dnwell_enc_nwell+pcmp_gr2dnw) + cmp_outer = pya.Box(-nwell_ncmp_enc-dnwell_enc_nwell-pcmp_gr2dnw-ncmp_w-dnwell_violat, -nwell_pcmp_enc-dnwell_enc_nwell-pcmp_gr2dnw-ncmp_w, ncmp_w+pcmp2ncmp_spc+pcmp_w+nwell_pcmp_enc+dnwell_enc_nwell+pcmp_gr2dnw+ncmp_w, cmp_l+nwell_pcmp_enc+dnwell_enc_nwell+pcmp_gr2dnw+ncmp_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + pn_diode_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-nwell_ncmp_enc-dnwell_enc_nwell-pcmp_gr2dnw+implant_comp_enc-dnwell_violat, -nwell_pcmp_enc-dnwell_enc_nwell-pcmp_gr2dnw+implant_comp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+nwell_pcmp_enc+dnwell_enc_nwell+pcmp_gr2dnw-implant_comp_enc, cmp_l+nwell_pcmp_enc+dnwell_enc_nwell+pcmp_gr2dnw-implant_comp_enc) + pp_outer = pya.Box(-nwell_ncmp_enc-dnwell_enc_nwell-pcmp_gr2dnw-ncmp_w-implant_comp_enc-dnwell_violat, -nwell_pcmp_enc-dnwell_enc_nwell-pcmp_gr2dnw-ncmp_w-implant_comp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+nwell_pcmp_enc+dnwell_enc_nwell+pcmp_gr2dnw+ncmp_w+implant_comp_enc, cmp_l+nwell_pcmp_enc+dnwell_enc_nwell+pcmp_gr2dnw+ncmp_w+implant_comp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + pn_diode_cell.shapes(pplus).insert(pp_gr) + + if volt == "5/6V": + # Inserting dualgate + if deepnwell == True: + pn_diode_cell.shapes(dualgate).insert(pya.Box(-nwell_ncmp_enc-dnwell_enc_nwell-dg_enc_dnwell-dnwell_violat, -nwell_pcmp_enc-dnwell_enc_nwell-dg_enc_dnwell, ncmp_w+pcmp2ncmp_spc+pcmp_w+nwell_pcmp_enc+dnwell_enc_nwell+dg_enc_dnwell, cmp_l+nwell_pcmp_enc+dnwell_enc_nwell+dg_enc_dnwell)) + else: + pn_diode_cell.shapes(dualgate).insert(pya.Box(-nwell_ncmp_enc-dnwell_violat-dnwell_violat, -nwell_pcmp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+nwell_pcmp_enc, cmp_l+nwell_pcmp_enc)) + + # Inserting marker + pn_diode_cell.shapes(diode_mk).insert(pya.Box(ncmp_w+pcmp2ncmp_spc, 0, ncmp_w+pcmp2ncmp_spc+pcmp_w, cmp_l)) + + pn_diode_cell.flatten(True) + return pn_diode_cell + +def draw_nwp_diode(layout, l, w , volt): + ''' + Usage:- + used to draw 3.3V Nwell/Psub diode by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + volt : String of operating voltage of the diode [3.3V, 5V/6V] + ''' + + # Define layers + comp = layout.layer(22 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + nwell = layout.layer (21 , 0) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + dualgate = layout.layer(55 , 0 ) + well_diode_mk = layout.layer(153, 51) + + # Define variables + dbu_PERCISION = 1/layout.dbu + pcmp2ncmp_spc = 0.44 * dbu_PERCISION + ncmp_w = 0.36 * dbu_PERCISION + pcmp_w = w * dbu_PERCISION + cmp_l = l * dbu_PERCISION + implant_comp_enc = 0.16 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.28 * dbu_PERCISION + dualgate_cmp_enc = 0.24 * dbu_PERCISION + + # Inserting nwp cell + cell_index = layout.add_cell("nwp_diode") + nwp_diode_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting diffusion + nwp_diode_cell.shapes(comp).insert(pya.Box(0, 0, ncmp_w, cmp_l)) + nwp_diode_cell.shapes(pplus).insert(pya.Box(-implant_comp_enc, -implant_comp_enc, ncmp_w+implant_comp_enc, cmp_l+implant_comp_enc)) + + nwp_diode_cell.shapes(comp).insert(pya.Box(ncmp_w+pcmp2ncmp_spc, 0, ncmp_w+pcmp2ncmp_spc+pcmp_w, cmp_l)) + nwp_diode_cell.shapes(nplus).insert(pya.Box(ncmp_w+pcmp2ncmp_spc-implant_comp_enc, -implant_comp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+implant_comp_enc, cmp_l+implant_comp_enc)) + + # Inserting nwell + nwp_diode_cell.shapes(nwell).insert(pya.Box(ncmp_w+pcmp2ncmp_spc-implant_comp_enc, -implant_comp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+implant_comp_enc, cmp_l+implant_comp_enc)) + + # Inserting metal + nwp_diode_cell.shapes(metal1).insert(pya.Box(0, 0, ncmp_w, cmp_l)) + nwp_diode_cell.shapes(metal1).insert(pya.Box(ncmp_w+pcmp2ncmp_spc, 0, ncmp_w+pcmp2ncmp_spc+pcmp_w, cmp_l)) + + # Inserting pcomp contacts + num_ncmp_con_1, ncmp_con_free_spc_1 = number_spc_contacts(ncmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_ncmp_con_2, ncmp_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + ncmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(ncmp_con_free_spc_1 / 2, ncmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_con_1, num_ncmp_con_2) + nwp_diode_cell.insert(ncmp_con_arr) + + # Inserting ncomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(pcmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(ncmp_w+pcmp2ncmp_spc+pcmp_con_free_spc_1 / 2, pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + nwp_diode_cell.insert(pcmp_con_arr) + + if volt == "5/6V": + # Inserting marker + nwp_diode_cell.shapes(well_diode_mk).insert(pya.Box(-dualgate_cmp_enc, -dualgate_cmp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+dualgate_cmp_enc, cmp_l+dualgate_cmp_enc)) + # Inserting dualgate + nwp_diode_cell.shapes(dualgate).insert(pya.Box(-dualgate_cmp_enc, -dualgate_cmp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+dualgate_cmp_enc, cmp_l+dualgate_cmp_enc)) + else: + # Inserting marker + nwp_diode_cell.shapes(well_diode_mk).insert(pya.Box(-implant_comp_enc, -implant_comp_enc, ncmp_w+pcmp2ncmp_spc+pcmp_w+implant_comp_enc, cmp_l+implant_comp_enc)) + + nwp_diode_cell.flatten(True) + return nwp_diode_cell + +def draw_dnwpw_diode(layout, l, w , volt): + ''' + Usage:- + used to draw LVPWELL/DNWELL diode by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + volt : String of operating voltage of the diode [3.3V, 5V/6V] + ''' + + # Define layers + lvpwell = layout.layer(204, 0 ) + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + nwell = layout.layer(21 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + dualgate = layout.layer(55 , 0 ) + well_diode_mk = layout.layer(153, 51) + + # Define variables + dbu_PERCISION = 1/layout.dbu + lvpwell_w = w * dbu_PERCISION + lvpwell_l = l * dbu_PERCISION + dnwell_lvpwell_enc = 2.5 * dbu_PERCISION + lvpwell_pcmp_enc = 0.12 * dbu_PERCISION + cmp_w = 0.36 * dbu_PERCISION + pcmp2ncmp_spc = 0.32 * dbu_PERCISION + implant_comp_enc = 0.16 * dbu_PERCISION + ncmp_ext = 0.56 * dbu_PERCISION + lvpwell_gr_spc = 5 * dbu_PERCISION + cont_spc_tol = 0.11 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + dualgate_lvpwell_enc = 3 * dbu_PERCISION + pcmp2ncmp_spc = 0.32 * dbu_PERCISION + lvpwell_pcmp_enc = 0.12 * dbu_PERCISION + + if volt == "5/6V": + pcmp2ncmp_spc = 0.36 * dbu_PERCISION + lvpwell_pcmp_enc = 0.16 * dbu_PERCISION + + # Inserting dnwpw cell + cell_index = layout.add_cell("dnwpw_diode") + dnwpw_diode_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting lvpwell + dnwpw_diode_cell.shapes(lvpwell).insert(pya.Box(0, 0, lvpwell_w, lvpwell_l)) + + # Inserting dnwell + dnwpw_diode_cell.shapes(dnwell).insert(pya.Box(-dnwell_lvpwell_enc, -dnwell_lvpwell_enc, lvpwell_w+dnwell_lvpwell_enc, lvpwell_l+dnwell_lvpwell_enc)) + + # Inserting p diffusion + dnwpw_diode_cell.shapes(comp).insert(pya.Box(lvpwell_pcmp_enc, lvpwell_pcmp_enc , lvpwell_pcmp_enc+cmp_w, lvpwell_l-lvpwell_pcmp_enc)) # left + dnwpw_diode_cell.shapes(pplus).insert(pya.Box(lvpwell_pcmp_enc-implant_comp_enc, lvpwell_pcmp_enc-implant_comp_enc , lvpwell_pcmp_enc+cmp_w+implant_comp_enc, lvpwell_l-lvpwell_pcmp_enc+implant_comp_enc)) + + dnwpw_diode_cell.shapes(comp).insert(pya.Box(lvpwell_w-lvpwell_pcmp_enc-cmp_w, lvpwell_pcmp_enc , lvpwell_w-lvpwell_pcmp_enc , lvpwell_l-lvpwell_pcmp_enc)) # right + dnwpw_diode_cell.shapes(pplus).insert(pya.Box(lvpwell_w-lvpwell_pcmp_enc-cmp_w-implant_comp_enc, lvpwell_pcmp_enc-implant_comp_enc , lvpwell_w-lvpwell_pcmp_enc+implant_comp_enc , lvpwell_l-lvpwell_pcmp_enc+implant_comp_enc)) + + dnwpw_diode_cell.shapes(comp).insert(pya.Box(lvpwell_pcmp_enc+cmp_w, lvpwell_l-lvpwell_pcmp_enc-cmp_w , lvpwell_w-lvpwell_pcmp_enc-cmp_w , lvpwell_l-lvpwell_pcmp_enc)) # top + dnwpw_diode_cell.shapes(pplus).insert(pya.Box(lvpwell_pcmp_enc+cmp_w+implant_comp_enc, lvpwell_l-lvpwell_pcmp_enc-cmp_w-implant_comp_enc , lvpwell_w-lvpwell_pcmp_enc-cmp_w-implant_comp_enc , lvpwell_l-lvpwell_pcmp_enc+implant_comp_enc)) # top + + dnwpw_diode_cell.shapes(comp).insert(pya.Box(lvpwell_pcmp_enc+cmp_w, lvpwell_pcmp_enc , lvpwell_w-lvpwell_pcmp_enc-cmp_w , lvpwell_pcmp_enc+cmp_w)) # bottom + dnwpw_diode_cell.shapes(pplus).insert(pya.Box(lvpwell_pcmp_enc+cmp_w+implant_comp_enc, lvpwell_pcmp_enc-implant_comp_enc , lvpwell_w-lvpwell_pcmp_enc-cmp_w-implant_comp_enc, lvpwell_pcmp_enc+cmp_w+implant_comp_enc)) # bottom + + # Inserting pcomp metal + dnwpw_diode_cell.shapes(metal1).insert(pya.Box(lvpwell_pcmp_enc, lvpwell_pcmp_enc , lvpwell_pcmp_enc+cmp_w, lvpwell_l-lvpwell_pcmp_enc)) # left + dnwpw_diode_cell.shapes(metal1).insert(pya.Box(lvpwell_w-lvpwell_pcmp_enc-cmp_w, lvpwell_pcmp_enc , lvpwell_w-lvpwell_pcmp_enc , lvpwell_l-lvpwell_pcmp_enc)) # right + dnwpw_diode_cell.shapes(metal1).insert(pya.Box(lvpwell_pcmp_enc+cmp_w, lvpwell_l-lvpwell_pcmp_enc-cmp_w , lvpwell_w-lvpwell_pcmp_enc-cmp_w , lvpwell_l-lvpwell_pcmp_enc)) # top + dnwpw_diode_cell.shapes(metal1).insert(pya.Box(lvpwell_pcmp_enc+cmp_w, lvpwell_pcmp_enc , lvpwell_w-lvpwell_pcmp_enc-cmp_w , lvpwell_pcmp_enc+cmp_w)) # bottom + + # Inserting pcomp contacts + num_pcmp_left_con_1, pcmp_left_con_free_spc_1 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_left_con_2, pcmp_left_con_free_spc_2 = number_spc_contacts(lvpwell_l-2*lvpwell_pcmp_enc, comp_cont_enc, cont_min_spc, cont_size) + pcmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(lvpwell_pcmp_enc+pcmp_left_con_free_spc_1 / 2, lvpwell_pcmp_enc+pcmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_left_con_1, num_pcmp_left_con_2) + dnwpw_diode_cell.insert(pcmp_left_con_arr) + + num_cmp_right_con_1, cmp_right_con_free_spc_1 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_cmp_right_con_2, cmp_right_con_free_spc_2 = number_spc_contacts(lvpwell_l-2*lvpwell_pcmp_enc, comp_cont_enc, cont_min_spc, cont_size) + cmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(lvpwell_w-lvpwell_pcmp_enc-cmp_w+cmp_right_con_free_spc_1 / 2, lvpwell_pcmp_enc+cmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_cmp_right_con_1, num_cmp_right_con_2) + dnwpw_diode_cell.insert(cmp_right_con_arr) + + num_cmp_top_con_1, cmp_top_con_free_spc_1 = number_spc_contacts(lvpwell_w-2*lvpwell_pcmp_enc-2*cmp_w-2*cont_spc_tol, comp_cont_enc, cont_min_spc, cont_size) + num_cmp_top_con_2, cmp_top_con_free_spc_2 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + cmp_top_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(lvpwell_pcmp_enc+cmp_w+cont_spc_tol+cmp_top_con_free_spc_1 / 2, lvpwell_l-lvpwell_pcmp_enc-cmp_w+cmp_top_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_cmp_top_con_1, num_cmp_top_con_2) + dnwpw_diode_cell.insert(cmp_top_con_arr) + + num_cmp_bot_con_1, cmp_bot_con_free_spc_1 = number_spc_contacts(lvpwell_w-2*lvpwell_pcmp_enc-2*cmp_w-2*cont_spc_tol, comp_cont_enc, cont_min_spc, cont_size) + num_cmp_bot_con_2, cmp_bot_con_free_spc_2 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + cmp_bot_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(lvpwell_pcmp_enc+cmp_w+cont_spc_tol+cmp_bot_con_free_spc_1 / 2, lvpwell_pcmp_enc+cmp_bot_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_cmp_bot_con_1, num_cmp_bot_con_2) + dnwpw_diode_cell.insert(cmp_bot_con_arr) + + # Inserting n diffusion + dnwpw_diode_cell.shapes(comp).insert(pya.Box(lvpwell_pcmp_enc-pcmp2ncmp_spc-cmp_w, -ncmp_ext , lvpwell_pcmp_enc-pcmp2ncmp_spc, lvpwell_l+ncmp_ext)) + dnwpw_diode_cell.shapes(nplus).insert(pya.Box(lvpwell_pcmp_enc-pcmp2ncmp_spc-cmp_w-implant_comp_enc, -ncmp_ext-implant_comp_enc , lvpwell_pcmp_enc-pcmp2ncmp_spc+implant_comp_enc, lvpwell_l+ncmp_ext+implant_comp_enc)) + + # Inserting ncomp metal + dnwpw_diode_cell.shapes(metal1).insert(pya.Box(lvpwell_pcmp_enc-pcmp2ncmp_spc-cmp_w, -ncmp_ext , lvpwell_pcmp_enc-pcmp2ncmp_spc, lvpwell_l+ncmp_ext)) + + # Inserting ncomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(lvpwell_l+2*ncmp_ext, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(lvpwell_pcmp_enc-pcmp2ncmp_spc-cmp_w+pcmp_con_free_spc_1 / 2, -ncmp_ext+pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + dnwpw_diode_cell.insert(pcmp_con_arr) + + # Inserting GR + dnwpw_diode_cell.shapes(comp).insert(pya.Box(-lvpwell_gr_spc-cmp_w, -lvpwell_gr_spc-cmp_w, -lvpwell_gr_spc , lvpwell_l+lvpwell_gr_spc+cmp_w)) #left + dnwpw_diode_cell.shapes(pplus).insert(pya.Box(-lvpwell_gr_spc-cmp_w-implant_comp_enc, -lvpwell_gr_spc-cmp_w-implant_comp_enc, -lvpwell_gr_spc+implant_comp_enc , lvpwell_l+lvpwell_gr_spc+cmp_w+implant_comp_enc)) + + dnwpw_diode_cell.shapes(comp).insert(pya.Box(lvpwell_w+lvpwell_gr_spc, -lvpwell_gr_spc-cmp_w, lvpwell_w+lvpwell_gr_spc+cmp_w , lvpwell_l+lvpwell_gr_spc+cmp_w)) #right + dnwpw_diode_cell.shapes(pplus).insert(pya.Box(lvpwell_w+lvpwell_gr_spc-implant_comp_enc, -lvpwell_gr_spc-cmp_w-implant_comp_enc, lvpwell_w+lvpwell_gr_spc+cmp_w+implant_comp_enc , lvpwell_l+lvpwell_gr_spc+cmp_w+implant_comp_enc)) + + dnwpw_diode_cell.shapes(comp).insert(pya.Box(-lvpwell_gr_spc , lvpwell_l+lvpwell_gr_spc , lvpwell_w+lvpwell_gr_spc , lvpwell_l+lvpwell_gr_spc+cmp_w)) #top + dnwpw_diode_cell.shapes(pplus).insert(pya.Box(-lvpwell_gr_spc+implant_comp_enc , lvpwell_l+lvpwell_gr_spc-implant_comp_enc , lvpwell_w+lvpwell_gr_spc-implant_comp_enc , lvpwell_l+lvpwell_gr_spc+cmp_w+implant_comp_enc)) + + dnwpw_diode_cell.shapes(comp).insert(pya.Box(-lvpwell_gr_spc , -lvpwell_gr_spc-cmp_w , lvpwell_w+lvpwell_gr_spc , -lvpwell_gr_spc)) #bot + dnwpw_diode_cell.shapes(pplus).insert(pya.Box(-lvpwell_gr_spc+implant_comp_enc , -lvpwell_gr_spc-cmp_w-implant_comp_enc , lvpwell_w+lvpwell_gr_spc-implant_comp_enc , -lvpwell_gr_spc+implant_comp_enc)) + + # Inserting GR metal + dnwpw_diode_cell.shapes(metal1).insert(pya.Box(-lvpwell_gr_spc-cmp_w, -lvpwell_gr_spc-cmp_w, -lvpwell_gr_spc , lvpwell_l+lvpwell_gr_spc+cmp_w)) #left + dnwpw_diode_cell.shapes(metal1).insert(pya.Box(lvpwell_w+lvpwell_gr_spc, -lvpwell_gr_spc-cmp_w, lvpwell_w+lvpwell_gr_spc+cmp_w , lvpwell_l+lvpwell_gr_spc+cmp_w)) #right + dnwpw_diode_cell.shapes(metal1).insert(pya.Box(-lvpwell_gr_spc , lvpwell_l+lvpwell_gr_spc , lvpwell_w+lvpwell_gr_spc , lvpwell_l+lvpwell_gr_spc+cmp_w)) #top + dnwpw_diode_cell.shapes(metal1).insert(pya.Box(-lvpwell_gr_spc , -lvpwell_gr_spc-cmp_w , lvpwell_w+lvpwell_gr_spc , -lvpwell_gr_spc)) #bot + + # Inserting GR contacts + num_gr_left_con_1, gr_left_con_free_spc_1 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_gr_left_con_2, gr_left_con_free_spc_2 = number_spc_contacts(lvpwell_l+2*lvpwell_gr_spc+2*cmp_w, comp_cont_enc, cont_min_spc, cont_size) + gr_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-lvpwell_gr_spc-cmp_w+gr_left_con_free_spc_1 / 2, -lvpwell_gr_spc-cmp_w+gr_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_left_con_1, num_gr_left_con_2) + dnwpw_diode_cell.insert(gr_left_con_arr) + + num_gr_right_con_1, gr_right_con_free_spc_1 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_gr_right_con_2, gr_right_con_free_spc_2 = number_spc_contacts(lvpwell_l+2*lvpwell_gr_spc+2*cmp_w, comp_cont_enc, cont_min_spc, cont_size) + gr_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(lvpwell_w+lvpwell_gr_spc+gr_right_con_free_spc_1 / 2, -lvpwell_gr_spc-cmp_w+gr_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_right_con_1, num_gr_right_con_2) + dnwpw_diode_cell.insert(gr_right_con_arr) + + num_gr_top_con_1, gr_top_con_free_spc_1 = number_spc_contacts(lvpwell_w+2*lvpwell_gr_spc-2*cont_spc_tol, comp_cont_enc, cont_min_spc, cont_size) + num_gr_top_con_2, gr_top_con_free_spc_2 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + gr_top_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-lvpwell_gr_spc+cont_spc_tol+gr_top_con_free_spc_1 / 2, lvpwell_l+lvpwell_gr_spc+gr_top_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_top_con_1, num_gr_top_con_2) + dnwpw_diode_cell.insert(gr_top_con_arr) + + num_gr_bot_con_1, gr_bot_con_free_spc_1 = number_spc_contacts(lvpwell_w+2*lvpwell_gr_spc-2*cont_spc_tol, comp_cont_enc, cont_min_spc, cont_size) + num_gr_bot_con_2, gr_bot_con_free_spc_2 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + gr_bot_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-lvpwell_gr_spc+cont_spc_tol+gr_bot_con_free_spc_1 / 2, -lvpwell_gr_spc-cmp_w+gr_bot_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_bot_con_1, num_gr_bot_con_2) + dnwpw_diode_cell.insert(gr_bot_con_arr) + + # Inserting marker + dnwpw_diode_cell.shapes(well_diode_mk).insert(pya.Box(0, 0, lvpwell_w, lvpwell_l)) + + if volt == "5/6V": + # Inserting dualgate + dnwpw_diode_cell.shapes(dualgate).insert(pya.Box(-dualgate_lvpwell_enc, -dualgate_lvpwell_enc, lvpwell_w+dualgate_lvpwell_enc, lvpwell_l+dualgate_lvpwell_enc)) + + dnwpw_diode_cell.flatten(True) + return dnwpw_diode_cell + +def draw_dnwps_diode(layout, l, w , volt): + ''' + Usage:- + used to draw LVPWELL/DNWELL diode by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + volt : String of operating voltage of the diode [3.3V, 5V/6V] + ''' + + # Define layers + lvpwell = layout.layer(204, 0 ) + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + nwell = layout.layer (21 , 0) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + dualgate = layout.layer(55 , 0 ) + well_diode_mk = layout.layer(153, 51) + + # Define variables + dbu_PERCISION = 1/layout.dbu + dnwell_w = w * dbu_PERCISION + dnwell_l = l * dbu_PERCISION + dnwell_pcmp_enc = 0.62 * dbu_PERCISION + cmp_w = 0.36 * dbu_PERCISION + pcmp2ncmp_spc = 0.32 * dbu_PERCISION + implant_comp_enc = 0.03 * dbu_PERCISION + ncmp_ext = 0.56 * dbu_PERCISION + lvpwell_gr_spc = 2.5 * dbu_PERCISION + cont_spc_tol = 0.11 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + dualgate_lvpwell_enc = 0.5 * dbu_PERCISION + + if volt == "5/6V": + dnwell_pcmp_enc = 0.66 * dbu_PERCISION + + + # Inserting dnwps cell + cell_index = layout.add_cell("dnwps_diode") + dnwps_diode_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting dnwell + dnwps_diode_cell.shapes(dnwell).insert(pya.Box(0, 0, dnwell_w, dnwell_l)) + + # Inserting n diffusion + dnwps_diode_cell.shapes(comp).insert(pya.Box(dnwell_pcmp_enc, dnwell_pcmp_enc , dnwell_pcmp_enc+cmp_w, dnwell_l-dnwell_pcmp_enc)) # left + dnwps_diode_cell.shapes(nplus).insert(pya.Box(dnwell_pcmp_enc-implant_comp_enc, dnwell_pcmp_enc-implant_comp_enc , dnwell_pcmp_enc+cmp_w+implant_comp_enc, dnwell_l-dnwell_pcmp_enc+implant_comp_enc)) + + dnwps_diode_cell.shapes(comp).insert(pya.Box(dnwell_w-dnwell_pcmp_enc-cmp_w, dnwell_pcmp_enc , dnwell_w-dnwell_pcmp_enc , dnwell_l-dnwell_pcmp_enc)) # right + dnwps_diode_cell.shapes(nplus).insert(pya.Box(dnwell_w-dnwell_pcmp_enc-cmp_w-implant_comp_enc, dnwell_pcmp_enc-implant_comp_enc , dnwell_w-dnwell_pcmp_enc+implant_comp_enc , dnwell_l-dnwell_pcmp_enc+implant_comp_enc)) + + dnwps_diode_cell.shapes(comp).insert(pya.Box(dnwell_pcmp_enc+cmp_w, dnwell_l-dnwell_pcmp_enc-cmp_w , dnwell_w-dnwell_pcmp_enc-cmp_w , dnwell_l-dnwell_pcmp_enc)) # top + dnwps_diode_cell.shapes(nplus).insert(pya.Box(dnwell_pcmp_enc+cmp_w+implant_comp_enc, dnwell_l-dnwell_pcmp_enc-cmp_w-implant_comp_enc , dnwell_w-dnwell_pcmp_enc-cmp_w-implant_comp_enc , dnwell_l-dnwell_pcmp_enc+implant_comp_enc)) # top + + dnwps_diode_cell.shapes(comp).insert(pya.Box(dnwell_pcmp_enc+cmp_w, dnwell_pcmp_enc , dnwell_w-dnwell_pcmp_enc-cmp_w , dnwell_pcmp_enc+cmp_w)) # bottom + dnwps_diode_cell.shapes(nplus).insert(pya.Box(dnwell_pcmp_enc+cmp_w+implant_comp_enc, dnwell_pcmp_enc-implant_comp_enc , dnwell_w-dnwell_pcmp_enc-cmp_w-implant_comp_enc, dnwell_pcmp_enc+cmp_w+implant_comp_enc)) # bottom + + # Inserting ncomp metal + dnwps_diode_cell.shapes(metal1).insert(pya.Box(dnwell_pcmp_enc, dnwell_pcmp_enc , dnwell_pcmp_enc+cmp_w, dnwell_l-dnwell_pcmp_enc)) # left + dnwps_diode_cell.shapes(metal1).insert(pya.Box(dnwell_w-dnwell_pcmp_enc-cmp_w, dnwell_pcmp_enc , dnwell_w-dnwell_pcmp_enc , dnwell_l-dnwell_pcmp_enc)) # right + dnwps_diode_cell.shapes(metal1).insert(pya.Box(dnwell_pcmp_enc+cmp_w, dnwell_l-dnwell_pcmp_enc-cmp_w , dnwell_w-dnwell_pcmp_enc-cmp_w , dnwell_l-dnwell_pcmp_enc)) # top + dnwps_diode_cell.shapes(metal1).insert(pya.Box(dnwell_pcmp_enc+cmp_w, dnwell_pcmp_enc , dnwell_w-dnwell_pcmp_enc-cmp_w , dnwell_pcmp_enc+cmp_w)) # bottom + + # Inserting ncomp contacts + num_pcmp_left_con_1, pcmp_left_con_free_spc_1 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_left_con_2, pcmp_left_con_free_spc_2 = number_spc_contacts(dnwell_l-2*dnwell_pcmp_enc, comp_cont_enc, cont_min_spc, cont_size) + pcmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(dnwell_pcmp_enc+pcmp_left_con_free_spc_1 / 2, dnwell_pcmp_enc+pcmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_left_con_1, num_pcmp_left_con_2) + dnwps_diode_cell.insert(pcmp_left_con_arr) + + num_cmp_right_con_1, cmp_right_con_free_spc_1 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_cmp_right_con_2, cmp_right_con_free_spc_2 = number_spc_contacts(dnwell_l-2*dnwell_pcmp_enc, comp_cont_enc, cont_min_spc, cont_size) + cmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(dnwell_w-dnwell_pcmp_enc-cmp_w+cmp_right_con_free_spc_1 / 2, dnwell_pcmp_enc+cmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_cmp_right_con_1, num_cmp_right_con_2) + dnwps_diode_cell.insert(cmp_right_con_arr) + + num_cmp_top_con_1, cmp_top_con_free_spc_1 = number_spc_contacts(dnwell_w-2*dnwell_pcmp_enc-2*cmp_w-2*cont_spc_tol, comp_cont_enc, cont_min_spc, cont_size) + num_cmp_top_con_2, cmp_top_con_free_spc_2 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + cmp_top_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(dnwell_pcmp_enc+cmp_w+cont_spc_tol+cmp_top_con_free_spc_1 / 2, dnwell_l-dnwell_pcmp_enc-cmp_w+cmp_top_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_cmp_top_con_1, num_cmp_top_con_2) + dnwps_diode_cell.insert(cmp_top_con_arr) + + num_cmp_bot_con_1, cmp_bot_con_free_spc_1 = number_spc_contacts(dnwell_w-2*dnwell_pcmp_enc-2*cmp_w-2*cont_spc_tol, comp_cont_enc, cont_min_spc, cont_size) + num_cmp_bot_con_2, cmp_bot_con_free_spc_2 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + cmp_bot_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(dnwell_pcmp_enc+cmp_w+cont_spc_tol+cmp_bot_con_free_spc_1 / 2, dnwell_pcmp_enc+cmp_bot_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_cmp_bot_con_1, num_cmp_bot_con_2) + dnwps_diode_cell.insert(cmp_bot_con_arr) + + # Inserting GR + dnwps_diode_cell.shapes(comp).insert(pya.Box(-lvpwell_gr_spc-cmp_w, -lvpwell_gr_spc-cmp_w, -lvpwell_gr_spc , dnwell_l+lvpwell_gr_spc+cmp_w)) #left + dnwps_diode_cell.shapes(pplus).insert(pya.Box(-lvpwell_gr_spc-cmp_w-implant_comp_enc, -lvpwell_gr_spc-cmp_w-implant_comp_enc, -lvpwell_gr_spc+implant_comp_enc , dnwell_l+lvpwell_gr_spc+cmp_w+implant_comp_enc)) + + dnwps_diode_cell.shapes(comp).insert(pya.Box(dnwell_w+lvpwell_gr_spc, -lvpwell_gr_spc-cmp_w, dnwell_w+lvpwell_gr_spc+cmp_w , dnwell_l+lvpwell_gr_spc+cmp_w)) #right + dnwps_diode_cell.shapes(pplus).insert(pya.Box(dnwell_w+lvpwell_gr_spc-implant_comp_enc, -lvpwell_gr_spc-cmp_w-implant_comp_enc, dnwell_w+lvpwell_gr_spc+cmp_w+implant_comp_enc , dnwell_l+lvpwell_gr_spc+cmp_w+implant_comp_enc)) + + dnwps_diode_cell.shapes(comp).insert(pya.Box(-lvpwell_gr_spc , dnwell_l+lvpwell_gr_spc , dnwell_w+lvpwell_gr_spc , dnwell_l+lvpwell_gr_spc+cmp_w)) #top + dnwps_diode_cell.shapes(pplus).insert(pya.Box(-lvpwell_gr_spc+implant_comp_enc , dnwell_l+lvpwell_gr_spc-implant_comp_enc , dnwell_w+lvpwell_gr_spc-implant_comp_enc , dnwell_l+lvpwell_gr_spc+cmp_w+implant_comp_enc)) + + dnwps_diode_cell.shapes(comp).insert(pya.Box(-lvpwell_gr_spc , -lvpwell_gr_spc-cmp_w , dnwell_w+lvpwell_gr_spc , -lvpwell_gr_spc)) #bot + dnwps_diode_cell.shapes(pplus).insert(pya.Box(-lvpwell_gr_spc+implant_comp_enc , -lvpwell_gr_spc-cmp_w-implant_comp_enc , dnwell_w+lvpwell_gr_spc-implant_comp_enc , -lvpwell_gr_spc+implant_comp_enc)) + + # Inserting GR metal + dnwps_diode_cell.shapes(metal1).insert(pya.Box(-lvpwell_gr_spc-cmp_w, -lvpwell_gr_spc-cmp_w, -lvpwell_gr_spc , dnwell_l+lvpwell_gr_spc+cmp_w)) #left + dnwps_diode_cell.shapes(metal1).insert(pya.Box(dnwell_w+lvpwell_gr_spc, -lvpwell_gr_spc-cmp_w, dnwell_w+lvpwell_gr_spc+cmp_w , dnwell_l+lvpwell_gr_spc+cmp_w)) #right + dnwps_diode_cell.shapes(metal1).insert(pya.Box(-lvpwell_gr_spc , dnwell_l+lvpwell_gr_spc , dnwell_w+lvpwell_gr_spc , dnwell_l+lvpwell_gr_spc+cmp_w)) #top + dnwps_diode_cell.shapes(metal1).insert(pya.Box(-lvpwell_gr_spc , -lvpwell_gr_spc-cmp_w , dnwell_w+lvpwell_gr_spc , -lvpwell_gr_spc)) #bot + + # Inserting GR contacts + num_gr_left_con_1, gr_left_con_free_spc_1 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_gr_left_con_2, gr_left_con_free_spc_2 = number_spc_contacts(dnwell_l+2*lvpwell_gr_spc+2*cmp_w, comp_cont_enc, cont_min_spc, cont_size) + gr_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-lvpwell_gr_spc-cmp_w+gr_left_con_free_spc_1 / 2, -lvpwell_gr_spc-cmp_w+gr_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_left_con_1, num_gr_left_con_2) + dnwps_diode_cell.insert(gr_left_con_arr) + + num_gr_right_con_1, gr_right_con_free_spc_1 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_gr_right_con_2, gr_right_con_free_spc_2 = number_spc_contacts(dnwell_l+2*lvpwell_gr_spc+2*cmp_w, comp_cont_enc, cont_min_spc, cont_size) + gr_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(dnwell_w+lvpwell_gr_spc+gr_right_con_free_spc_1 / 2, -lvpwell_gr_spc-cmp_w+gr_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_right_con_1, num_gr_right_con_2) + dnwps_diode_cell.insert(gr_right_con_arr) + + num_gr_top_con_1, gr_top_con_free_spc_1 = number_spc_contacts(dnwell_w+2*lvpwell_gr_spc-2*cont_spc_tol, comp_cont_enc, cont_min_spc, cont_size) + num_gr_top_con_2, gr_top_con_free_spc_2 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + gr_top_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-lvpwell_gr_spc+cont_spc_tol+gr_top_con_free_spc_1 / 2, dnwell_l+lvpwell_gr_spc+gr_top_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_top_con_1, num_gr_top_con_2) + dnwps_diode_cell.insert(gr_top_con_arr) + + num_gr_bot_con_1, gr_bot_con_free_spc_1 = number_spc_contacts(dnwell_w+2*lvpwell_gr_spc-2*cont_spc_tol, comp_cont_enc, cont_min_spc, cont_size) + num_gr_bot_con_2, gr_bot_con_free_spc_2 = number_spc_contacts(cmp_w, comp_cont_enc, cont_min_spc, cont_size) + gr_bot_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-lvpwell_gr_spc+cont_spc_tol+gr_bot_con_free_spc_1 / 2, -lvpwell_gr_spc-cmp_w+gr_bot_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_bot_con_1, num_gr_bot_con_2) + dnwps_diode_cell.insert(gr_bot_con_arr) + + # Inserting marker + dnwps_diode_cell.shapes(well_diode_mk).insert(pya.Box(0, 0, dnwell_w, dnwell_l)) + + if volt == "5/6V": + # Inserting dualgate + dnwps_diode_cell.shapes(dualgate).insert(pya.Box(-dualgate_lvpwell_enc, -dualgate_lvpwell_enc, dnwell_w+dualgate_lvpwell_enc, dnwell_l+dualgate_lvpwell_enc)) + + dnwps_diode_cell.flatten(True) + return dnwps_diode_cell + +def draw_sc_diode(layout, l, w , m, pcmpgr): + ''' + Usage:- + used to draw N+/LVPWELL diode (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + m : Integer of number of fingers + pcmpgr : Boolean of using P+ Guard Ring for Deep NWELL devices only + ''' + + # Define layers + comp = layout.layer(22 , 0 ) + nplus = layout.layer(32 , 0 ) + dnwell = layout.layer(12 , 0 ) + pplus = layout.layer(31 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + sc_diode_mk = layout.layer(241, 0 ) + + # Define variables + dbu_PERCISION = 1/layout.dbu + ncmp_metcmp_spc = 0.28 * dbu_PERCISION + ncmp_w = 0.36 * dbu_PERCISION + sc_w = w * dbu_PERCISION + sc_l = l * dbu_PERCISION + implant_comp_enc = 0.03 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + + metcmp_min_spc = 0.92 * dbu_PERCISION + met_cmp_enc_in = 0.23 * dbu_PERCISION + met_ncmp_enc = 0.46 * dbu_PERCISION + dnwell_cmp_enc_x = 0.76 * dbu_PERCISION + dnwell_cmp_enc_y = 1.4 * dbu_PERCISION + sc_mk_cmp_enc = 0.16 * dbu_PERCISION + met_conn_w = 0.23 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + + ncmp_min_spc = 2*ncmp_metcmp_spc + sc_w + cmp_total_w = (m+1)*ncmp_w + m*ncmp_min_spc + + # Inserting np cell + cell_index = layout.add_cell("sc_diode") + sc_diode_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting ncomp sc finger cell + ncmp_cell_index = layout.add_cell("ncomp") + ncmp_cell = layout.cell(ncmp_cell_index) + ncmp_cell.shapes(comp).insert(pya.Box.new(0, 0, ncmp_w, sc_l)) + ncmp_cell.shapes(nplus).insert(pya.Box.new(-implant_comp_enc, -implant_comp_enc, ncmp_w+implant_comp_enc, sc_l+implant_comp_enc)) + ncmp_cell.shapes(metal1).insert(pya.Box.new(0 , -met_cmp_enc_in, ncmp_w, sc_l)) + ## Inserting pcomp contacts + num_ncmp_con_1, ncmp_con_free_spc_1 = number_spc_contacts(ncmp_w, comp_cont_enc, cont_min_spc, cont_size) + num_ncmp_con_2, ncmp_con_free_spc_2 = number_spc_contacts(sc_l, comp_cont_enc, cont_min_spc, cont_size) + ncmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(ncmp_con_free_spc_1 / 2, ncmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_con_1, num_ncmp_con_2) + ncmp_cell.insert(ncmp_con_arr) + + # Inserting comp_metal sc finger cell + met_cmp_cell_index = layout.add_cell("comp_metal") + met_cmp_cell = layout.cell(met_cmp_cell_index) + met_cmp_cell.shapes(comp).insert(pya.Box.new(0, 0, sc_w, sc_l)) + + if m > 1: + met_cmp_cell.shapes(metal1).insert(pya.Box.new(0, 0, sc_w, sc_l+met_cmp_enc_in)) + else: + met_cmp_cell.shapes(metal1).insert(pya.Box.new(0, 0, sc_w, sc_l)) + + ## Inserting comp_metal contacts + num_met_cmp_con_1, met_cmp_con_free_spc_1 = number_spc_contacts(sc_w, comp_cont_enc, cont_min_spc, cont_size) + num_met_cmp_con_2, met_cmp_con_free_spc_2 = number_spc_contacts(sc_l, comp_cont_enc, cont_min_spc, cont_size) + met_cmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(met_cmp_con_free_spc_1 / 2, met_cmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_met_cmp_con_1, num_met_cmp_con_2) + met_cmp_cell.insert(met_cmp_con_arr) + + # Inserting ncomp fingers + ncmp_arr = pya.CellInstArray(ncmp_cell.cell_index(), pya.Trans( + pya.Point(0, 0)), + pya.Vector(ncmp_min_spc + ncmp_w, 0), pya.Vector(0,ncmp_min_spc + ncmp_w), + m+1, 1) + sc_diode_cell.insert(ncmp_arr) + + # Inserting metal comp fingers + metcmp_arr = pya.CellInstArray(met_cmp_cell.cell_index(), pya.Trans( + pya.Point(ncmp_w+ncmp_metcmp_spc, 0)), + pya.Vector(metcmp_min_spc + sc_w, 0), pya.Vector(0,metcmp_min_spc + sc_w), + m, 1) + sc_diode_cell.insert(metcmp_arr) + + # Inserting Deep NWELL + sc_diode_cell.shapes(dnwell).insert(pya.Box(-dnwell_cmp_enc_x, -dnwell_cmp_enc_y, cmp_total_w+dnwell_cmp_enc_x, sc_l+dnwell_cmp_enc_y)) + + # Inserting Deep NWELL P+ Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-dnwell_cmp_enc_x-pcmp_gr2dnw, -dnwell_cmp_enc_y-pcmp_gr2dnw, cmp_total_w+dnwell_cmp_enc_x+pcmp_gr2dnw, sc_l+dnwell_cmp_enc_y+pcmp_gr2dnw) + cmp_outer = pya.Box(-dnwell_cmp_enc_x-ncmp_w-pcmp_gr2dnw, -dnwell_cmp_enc_y-ncmp_w-pcmp_gr2dnw, cmp_total_w+dnwell_cmp_enc_x+ncmp_w+pcmp_gr2dnw, sc_l+dnwell_cmp_enc_y+ncmp_w+pcmp_gr2dnw) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + sc_diode_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-dnwell_cmp_enc_x+implant_comp_enc-pcmp_gr2dnw, -dnwell_cmp_enc_y+implant_comp_enc-pcmp_gr2dnw, cmp_total_w+dnwell_cmp_enc_x-implant_comp_enc+pcmp_gr2dnw, sc_l+dnwell_cmp_enc_y-implant_comp_enc+pcmp_gr2dnw) + pp_outer = pya.Box(-dnwell_cmp_enc_x-ncmp_w-implant_comp_enc-pcmp_gr2dnw, -dnwell_cmp_enc_y-ncmp_w-implant_comp_enc-pcmp_gr2dnw, cmp_total_w+dnwell_cmp_enc_x+ncmp_w+implant_comp_enc+pcmp_gr2dnw, sc_l+dnwell_cmp_enc_y+ncmp_w+implant_comp_enc+pcmp_gr2dnw) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + sc_diode_cell.shapes(pplus).insert(pp_gr) + + # Inserting sc_marker + sc_diode_cell.shapes(sc_diode_mk).insert(pya.Box(-sc_mk_cmp_enc, -sc_mk_cmp_enc, cmp_total_w+sc_mk_cmp_enc, sc_l+sc_mk_cmp_enc)) + + # Inserting connection metal [bottom] + sc_diode_cell.shapes(metal1).insert(pya.Box(0, -met_ncmp_enc, cmp_total_w, -met_ncmp_enc+met_conn_w)) + + # Inserting connection metal [Top] + if m > 1: + sc_diode_cell.shapes(metal1).insert(pya.Box(ncmp_w+ncmp_metcmp_spc, sc_l+met_ncmp_enc-met_conn_w, cmp_total_w-ncmp_w-ncmp_metcmp_spc, sc_l+met_ncmp_enc)) + + sc_diode_cell.flatten(True) + return sc_diode_cell diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_efuse.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_efuse.py new file mode 100644 index 000000000..cfd21ec24 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_efuse.py @@ -0,0 +1,27 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import pya +import os + +USER = os.environ['USER'] +gds_path = f"/home/{USER}/.klayout/pymacros/cells/efuse" + + +def draw_efuse(layout, device_name): + + layout.read(f"{gds_path}/efuse.gds") + cell_name = "efuse_cell" + + return layout.cell(cell_name) diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_mimcap.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_mimcap.py new file mode 100644 index 000000000..94a82e79a --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_mimcap.py @@ -0,0 +1,130 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +## MIM Capacitor Pcells Generators for Klayout of GF180MCU +######################################################################################################################## + +import pya + + +def number_spc_contacts(box_width, min_enc, cont_spacing, cont_width): + """ Calculate number of cantacts in a given dimensions and the free space for symmetry. + By getting the min enclosure,the width of the box,the width ans spacing of the contacts. + Parameters + ---------- + box_width (double) : length you place the via or cont. in + min_enc (double) : spacing between the edge of the box and the first contact. + cont_spacing (double) : spacing between different contacts + cont_width (double) : contacts in the same direction + """ + spc_cont = box_width - 2 * min_enc + num_cont = int((spc_cont + cont_spacing) / (cont_width + cont_spacing)) + free_spc = box_width - (num_cont * cont_width + + (num_cont - 1) * cont_spacing) + return num_cont, free_spc + +def draw_mimcap(layout, l, w , mim_option , metal_level): + ''' + Usage:- + used to draw 1.0fF/um2 MIM capacitor by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + metal2 = layout.layer(36 , 0 ) + metal3 = layout.layer(42 , 0 ) + metal4 = layout.layer(46 , 0 ) + metal5 = layout.layer(81 , 0 ) + metaltop = layout.layer(53 , 0 ) + via2 = layout.layer(38 , 0 ) + via3 = layout.layer(40 , 0 ) + via4 = layout.layer(41 , 0 ) + via5 = layout.layer(82 , 0 ) + fusetop = layout.layer(75 , 0 ) + cap_mk = layout.layer(117, 5 ) + mim_l_mk = layout.layer(117, 10) + + # MIM Option selection + if mim_option == "MIM-A": + topmet = metal3 + botmet = metal2 + topvia = via2 + + elif mim_option == "MIM-B": + if metal_level == "M4": + topmet = metal4 + botmet = metal3 + topvia = via3 + elif metal_level == "M5": + topmet = metal5 + botmet = metal4 + topvia = via4 + elif metal_level == "M6": + topmet = metaltop + botmet = metal5 + topvia = via5 + else: + topmet = metal3 + botmet = metal2 + topvia = via2 + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + topmet_w = w * dbu_PERCISION + topmet_l = l * dbu_PERCISION + top_bot_enc = 0.6 * dbu_PERCISION + mim_l_mk_width = 0.1 * dbu_PERCISION + via_size = 0.26 * dbu_PERCISION + via_min_spc = 0.5 * dbu_PERCISION + met_via_enc = 0.4 * dbu_PERCISION + + # Inserting nmoscap cell + cell_index = layout.add_cell("mimcap") + mimcap_cell = layout.cell(cell_index) + + # Inserting a via cell + cont_cell_index = layout.add_cell("topvia") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(topvia).insert(pya.Box.new(0, 0, via_size, via_size)) + + # Inserting top_metal + mimcap_cell.shapes(topmet).insert(pya.Box(0, 0, topmet_w, topmet_l)) + + # Inserting fusetop + mimcap_cell.shapes(fusetop).insert(pya.Box(0, 0, topmet_w, topmet_l)) + + # Inserting bot_metal + mimcap_cell.shapes(botmet).insert(pya.Box(-top_bot_enc, -top_bot_enc, topmet_w+top_bot_enc, topmet_l+top_bot_enc)) + + # Inserting bottom metal vias + num_left_con_1, left_con_free_spc_1 = number_spc_contacts(topmet_w, met_via_enc, via_min_spc, via_size) + num_left_con_2, left_con_free_spc_2 = number_spc_contacts(topmet_l, met_via_enc, via_min_spc, via_size) + left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(left_con_free_spc_1 / 2, left_con_free_spc_2/2)), + pya.Vector(via_min_spc + via_size, 0), pya.Vector(0,via_min_spc + via_size), + num_left_con_1, num_left_con_2) + mimcap_cell.insert(left_con_arr) + + # Inserting mim_l_mk + mimcap_cell.shapes(mim_l_mk).insert(pya.Box(0, 0,topmet_w, mim_l_mk_width)) + + # Inserting marker + mimcap_cell.shapes(cap_mk).insert(pya.Box(-top_bot_enc, -top_bot_enc, topmet_w+top_bot_enc, topmet_l+top_bot_enc)) + + mimcap_cell.flatten(True) + return mimcap_cell diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_mos.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_mos.py new file mode 100644 index 000000000..6505d17c4 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_mos.py @@ -0,0 +1,1486 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +## MOSFET Pcells Generators for Klayout of GF180MCU +######################################################################################################################## + +import pya + +tol = 1.05 + +def draw_nmos(layout, l, w, ld, nf, grw, bulk, volt, deepnwell, pcmpgr): + ''' + Usage:- + used to draw NMOS transistor by specifying parameters + Arguments:- + layout : Object of layout + l : Float of gate length + w : Float of gate width + ld : Float of diffusion length + nf : Integer of number of fingers + grw : Float of guard ring width [If enabled] + bulk : String of bulk connection type [None, Bulk Tie, Guard Ring] + volt : String of operating voltage of the MOSFET [3.3V, 5V, 6V] + deepnwell : Boolean of using Deep NWELL device + pcmpgr : Boolean of using P+ Guard Ring for Deep NWELL devices only + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + lvpwell = layout.layer(204, 0 ) + dualgate = layout.layer(55 , 0 ) + v5_xtor = layout.layer(112, 1 ) + comp = layout.layer(22 , 0 ) + poly2 = layout.layer(30 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + + # Define variables + dbu_PERCISION = 1/layout.dbu + nf = int(nf) + grw = grw * dbu_PERCISION + ld = ld * dbu_PERCISION + l = l * dbu_PERCISION + w = w * dbu_PERCISION + cmp2cont = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + np_enc_cmp = 0.16 * dbu_PERCISION + pp_enc_cmp = 0.16 * dbu_PERCISION + cont2ply = 0.15 * dbu_PERCISION + ply_ext_cmp = 0.22 * dbu_PERCISION + np_enc_gate = 0.23 * dbu_PERCISION + cont2cont = 0.28 * dbu_PERCISION + dg_enc_ply = 0.4 * dbu_PERCISION + dg_enc_cmp = 0.24 * dbu_PERCISION + cmp2cmp = 0.28 * dbu_PERCISION + ply2gr = 0.1 * dbu_PERCISION + ld_violat = 0 * dbu_PERCISION + tie_violat = 0 * dbu_PERCISION + metal_violat = 0.01 * dbu_PERCISION + min_cmp_area = 0.2025 * dbu_PERCISION * dbu_PERCISION + dg_enc_dnwell = 0.5 * dbu_PERCISION + lvpwell_enc_ncmp = 0.43 * dbu_PERCISION + lvpwell_enc_pcmp = 0.12 * dbu_PERCISION + dnwell_enc_lvpwell = 2.5 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + + if deepnwell == True: + cmp2cmp = 0.36 * dbu_PERCISION + ply2gr = 0.3 * dbu_PERCISION + + if volt == "5V" or volt == "6V": + lvpwell_enc_ncmp = 0.6 * dbu_PERCISION + lvpwell_enc_pcmp = 0.16 * dbu_PERCISION + cmp2cmp = 0.36 * dbu_PERCISION + ply2gr = 0.3 * dbu_PERCISION + cmp2cmp = 0.36 * dbu_PERCISION + + if w < cont_size+2*cmp2cont: + if nf == 1: + if volt == "5V" or volt == "6V": + ld_violat = 0.22 * dbu_PERCISION + else: + ld_violat = 0.02 * dbu_PERCISION + + # Inserting NMOS cell + cell_index = layout.add_cell("nmos") + cell = layout.cell(cell_index) + + w_changed = False + + # Inserting diffusion + if w < cont_size+2*cmp2cont: + cell.shapes(comp).insert(pya.Box(0, (cont_size+2*cmp2cont - w)/2, (2 * (ld + ld_violat) + l + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), w + (cont_size+2*cmp2cont - w)/2)) + w = cont_size+2*cmp2cont + w_changed = True + else: + cell.shapes(comp).insert(pya.Box(0, 0, (2 * ld + l + (nf - 1) * (ld + l + cont2ply - cmp2cont)), w)) + + cell.shapes(nplus).insert(pya.Box(-np_enc_cmp, -np_enc_gate, (2 * (ld + ld_violat) + l + np_enc_cmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), w + np_enc_gate)) + + # Inserting gate/s + # Inserting a gate cell + gate_cell_index = layout.add_cell("gate") + gate_cell = layout.cell(gate_cell_index) + gate_cell.shapes(poly2).insert(pya.Box(ld + ld_violat, -ply_ext_cmp, (ld + ld_violat + l), (w + ply_ext_cmp))) + + # adding gate array + cell.insert(pya.CellInstArray.new(gate_cell_index, pya.Trans.new(pya.Point.new(0, 0)), + pya.Point.new(ld + ld_violat + l + cont2ply - cmp2cont, 0), pya.Point.new(0, 0), int(nf), 1)) + + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + + # Inserting shapes now into the *contact* cell + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Contact array count and postions + nx = int((ld - (cont_size+cmp2cont+cont2ply))/(cont2cont+cont_size)) + 1 + ny = int((w - (cont_size+2*cmp2cont))/(cont2cont+cont_size)) + 1 + dx = (ld - nx * cont_size - (nx - 1) * cont2cont)*cmp2cont/cont_size + dy = (w - ny * cont_size - (ny - 1) * cont2cont)/2 + + # adding contact array and metals + # Left contacts + if not (w_changed == True and nf > 1) and (ld >= 440): + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(dx, dy)), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nx, ny)) + # Left metal + cell.shapes(metal1).insert(pya.Box(-metal_violat, -metal_violat, ld + metal_violat - (cont_size-2*cmp2cont), w + metal_violat)) + + # Adding diffusion to avoid contact violation + if nf == 1 and w_changed == True: + cell.shapes(comp).insert(pya.Box(0, 0, ld - (cont_size-2*cmp2cont), w)) + + # Right contacts and metals for each finger + for i in range(nf): + # Contacts + if not (w_changed == True and nf > 1) and (ld >= 440): + cell.insert(pya.CellInstArray.new(cont_cell_index, + pya.Trans.new(pya.Point.new(((l + ld + ld_violat + cont2ply - cmp2cont) * i + 2 * (ld + ld_violat) + l - cont_size - dx), dy)), + pya.Point.new(-(cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nx, ny)) + # Metals + cell.shapes(metal1).insert(pya.Box((ld + 2 * ld_violat + l + cont2ply - cmp2cont)*(i + 1), - metal_violat, + ld + metal_violat + ld_violat + (ld + ld_violat + l + cont2ply - cmp2cont)*(i + 1) - (cont_size-2*cmp2cont), w + metal_violat)) + + # Adding diffusion to avoid contact violation + if nf == 1 and w_changed == True: + cell.shapes(comp).insert(pya.Box((ld + 2 * ld_violat + l + cont2ply - cmp2cont)*(i + 1), 0, ld + ld_violat + (ld + ld_violat + l + cont2ply - cmp2cont)*(i + 1) - (cont_size-2*cmp2cont), w)) + region = pya.Region.new(cell.begin_shapes_rec(comp)) + region.merge() + cell.clear(comp) + cell.shapes(comp).insert(region) + + if bulk == "Bulk Tie": + if deepnwell == True: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp-ld, + -dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_ncmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell + dg_enc_dnwell)) + + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp-ld, + -dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_ncmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell + dg_enc_dnwell)) + + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp-ld, + -dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_ncmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell + dg_enc_dnwell)) + + # Inserting LVPWELL + cell.shapes(lvpwell).insert(pya.Box(-lvpwell_enc_pcmp-cmp2cmp-ld, -lvpwell_enc_ncmp, + (2 * (ld + ld_violat) + l + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp)) + + # Inserting DNWELL + cell.shapes(dnwell).insert(pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp-ld, -dnwell_enc_lvpwell-lvpwell_enc_ncmp, + (2 * (ld + ld_violat) + l + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell)) + + # Inserting Double Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp-ld-pcmp_gr2dnw, -dnwell_enc_lvpwell-lvpwell_enc_ncmp-pcmp_gr2dnw, + (2 * (ld + ld_violat) + l + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont))+pcmp_gr2dnw, + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell+pcmp_gr2dnw) + cmp_outer = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp-ld-pcmp_gr2dnw-gr_w, -dnwell_enc_lvpwell-lvpwell_enc_ncmp-pcmp_gr2dnw-gr_w, + (2 * (ld + ld_violat) + l + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont))+pcmp_gr2dnw+gr_w, + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell+pcmp_gr2dnw+gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp-ld-pcmp_gr2dnw+pp_enc_cmp, -dnwell_enc_lvpwell-lvpwell_enc_ncmp-pcmp_gr2dnw+pp_enc_cmp, + (2 * (ld + ld_violat) + l + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont))+pcmp_gr2dnw-pp_enc_cmp, + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell+pcmp_gr2dnw-pp_enc_cmp) + pp_outer = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp-ld-pcmp_gr2dnw-gr_w-pp_enc_cmp, -dnwell_enc_lvpwell-lvpwell_enc_ncmp-pcmp_gr2dnw-gr_w-pp_enc_cmp, + (2 * (ld + ld_violat) + l + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont))+pcmp_gr2dnw+gr_w+pp_enc_cmp, + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell+pcmp_gr2dnw+gr_w+pp_enc_cmp) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + cell.shapes(pplus).insert(pp_gr) + + else: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(- (cmp2cmp+dg_enc_cmp) - ld, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + cell.shapes(dualgate).insert(pya.Box(- (cmp2cmp+dg_enc_cmp) - ld, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(- (cmp2cmp+dg_enc_cmp) - ld, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + + # Inserting Tie + if (w * ld) < min_cmp_area: + tie_violat = (min_cmp_area/ld - w)/2 * tol + cell.shapes(comp).insert(pya.Box(- cmp2cmp - ld, -tie_violat, -cmp2cmp, w + tie_violat)) + cell.shapes(pplus).insert(pya.Box(- cmp2cmp - pp_enc_cmp - ld, -pp_enc_cmp-tie_violat, -cmp2cmp+pp_enc_cmp, w + tie_violat + pp_enc_cmp)) + + # Tie contacts + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((- (cmp2cmp+cont_size) - dx * cont_size/(2 *cmp2cont)), dy)), + pya.Point.new(-(cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nx, ny)) + + # Tie metal + cell.shapes(metal1).insert(pya.Box(- cmp2cmp - ld, -tie_violat, -cmp2cmp, w + tie_violat)) + + elif bulk == "Guard Ring": + if deepnwell == True: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp - grw, + -dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_pcmp-(ply_ext_cmp + ply2gr) - grw, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + lvpwell_enc_pcmp + dnwell_enc_lvpwell + dg_enc_dnwell + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + lvpwell_enc_pcmp + dnwell_enc_lvpwell + dg_enc_dnwell))) + + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp - grw, + -dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_pcmp-(ply_ext_cmp + ply2gr) - grw, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + lvpwell_enc_pcmp + dnwell_enc_lvpwell + dg_enc_dnwell + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + lvpwell_enc_pcmp + dnwell_enc_lvpwell + dg_enc_dnwell))) + + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp - grw, + -dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_pcmp-(ply_ext_cmp + ply2gr) - grw, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + lvpwell_enc_pcmp + dnwell_enc_lvpwell + dg_enc_dnwell + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + lvpwell_enc_pcmp + dnwell_enc_lvpwell + dg_enc_dnwell))) + + # Inserting LVPWELL + cell.shapes(lvpwell).insert(pya.Box(-lvpwell_enc_pcmp-cmp2cmp - grw, -lvpwell_enc_pcmp-(ply_ext_cmp + ply2gr) - grw, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + lvpwell_enc_pcmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + lvpwell_enc_pcmp))) + + # Inserting DNWELL + cell.shapes(dnwell).insert(pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp - grw, + -dnwell_enc_lvpwell-lvpwell_enc_pcmp-(ply_ext_cmp + ply2gr) - grw, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + lvpwell_enc_pcmp + dnwell_enc_lvpwell + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + lvpwell_enc_pcmp + dnwell_enc_lvpwell))) + + # Inserting Double Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp - grw - pcmp_gr2dnw, + -dnwell_enc_lvpwell-lvpwell_enc_pcmp-(ply_ext_cmp + ply2gr) - grw - pcmp_gr2dnw, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + lvpwell_enc_pcmp + dnwell_enc_lvpwell + pcmp_gr2dnw + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + pcmp_gr2dnw + lvpwell_enc_pcmp + dnwell_enc_lvpwell)) + cmp_outer = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp - grw - pcmp_gr2dnw - gr_w, + -dnwell_enc_lvpwell-lvpwell_enc_pcmp-(ply_ext_cmp + ply2gr) - grw - pcmp_gr2dnw - gr_w, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + lvpwell_enc_pcmp + dnwell_enc_lvpwell + pcmp_gr2dnw + gr_w + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + pcmp_gr2dnw + gr_w + lvpwell_enc_pcmp + dnwell_enc_lvpwell)) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp - grw - pcmp_gr2dnw + pp_enc_cmp, + -dnwell_enc_lvpwell-lvpwell_enc_pcmp-(ply_ext_cmp + ply2gr) - grw - pcmp_gr2dnw + pp_enc_cmp, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + lvpwell_enc_pcmp + dnwell_enc_lvpwell + pcmp_gr2dnw - pp_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + pcmp_gr2dnw + lvpwell_enc_pcmp + dnwell_enc_lvpwell - pp_enc_cmp)) + pp_outer = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_pcmp-cmp2cmp - grw - pcmp_gr2dnw - gr_w - pp_enc_cmp, + -dnwell_enc_lvpwell-lvpwell_enc_pcmp-(ply_ext_cmp + ply2gr) - grw - pcmp_gr2dnw - gr_w - pp_enc_cmp, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + lvpwell_enc_pcmp + dnwell_enc_lvpwell + pcmp_gr2dnw + gr_w + pp_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + pcmp_gr2dnw + gr_w + pp_enc_cmp + lvpwell_enc_pcmp + dnwell_enc_lvpwell)) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + cell.shapes(pplus).insert(pp_gr) + + else: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(-(cmp2cmp+dg_enc_cmp) - grw, -(ply_ext_cmp+ply2gr+dg_enc_cmp) - grw, (2 * (ld + ld_violat) + l + grw + (cmp2cmp+dg_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + ply_ext_cmp+ply2gr+dg_enc_cmp + grw))) + cell.shapes(dualgate).insert(pya.Box(-(cmp2cmp+dg_enc_cmp) - grw, -(ply_ext_cmp+ply2gr+dg_enc_cmp) - grw, (2 * (ld + ld_violat) + l + grw + (cmp2cmp+dg_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + ply_ext_cmp+ply2gr+dg_enc_cmp + grw))) + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(-(cmp2cmp+dg_enc_cmp) - grw, -(ply_ext_cmp+ply2gr+dg_enc_cmp) - grw, (2 * (ld + ld_violat) + l + grw + (cmp2cmp+dg_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + ply_ext_cmp+ply2gr+dg_enc_cmp + grw))) + + # Inserting guard ring diffusion + cell.shapes(comp).insert( + pya.Polygon( + [ + pya.Point(-cmp2cmp - grw, -(ply_ext_cmp + ply2gr) - grw), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp, -(ply_ext_cmp + ply2gr)), + pya.Point((2 * (ld + ld_violat) + l + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr)), + pya.Point((2 * (ld + ld_violat) + l + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr) - grw), + ], + True, + ) + ) + cell.shapes(pplus).insert( + pya.Polygon( + [ + pya.Point(-(cmp2cmp+pp_enc_cmp) - grw, -(ply_ext_cmp + ply2gr + pp_enc_cmp) - grw), + pya.Point(-(cmp2cmp+pp_enc_cmp) - grw, (w + (ply_ext_cmp + ply2gr - pp_enc_cmp))), + pya.Point(-(cmp2cmp-pp_enc_cmp), (w + (ply_ext_cmp + ply2gr - pp_enc_cmp))), + pya.Point(-(cmp2cmp-pp_enc_cmp), -(ply_ext_cmp + ply2gr - pp_enc_cmp)), + pya.Point((2 * (ld + ld_violat) + l + (cmp2cmp-pp_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr - pp_enc_cmp)), + pya.Point((2 * (ld + ld_violat) + l + (cmp2cmp-pp_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr - pp_enc_cmp))), + pya.Point(-(cmp2cmp+pp_enc_cmp) - grw, (w + (ply_ext_cmp + ply2gr - pp_enc_cmp))), + pya.Point(-(cmp2cmp+pp_enc_cmp) - grw, (w + (ply_ext_cmp + ply2gr + pp_enc_cmp) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + (cmp2cmp+pp_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr + pp_enc_cmp) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + (cmp2cmp+pp_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr + pp_enc_cmp) - grw), + ], + True, + ) + ) + + # Inserting Guard Ring metal + cell.shapes(metal1).insert( + pya.Polygon( + [ + pya.Point(-cmp2cmp - grw, -(ply_ext_cmp + ply2gr) - grw), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp, -(ply_ext_cmp + ply2gr)), + pya.Point((2 * (ld + ld_violat) + l + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr)), + pya.Point((2 * (ld + ld_violat) + l + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr) - grw), + ], + True, + ) + ) + + nxgr = int((grw - (cont_size+2*cmp2cont))/(cont2cont+cont_size)) + 1 + nygr = int(((2 * grw + w + 2*(ply_ext_cmp + ply2gr)) - (cont_size+2*cmp2cont))/(cont2cont+cont_size)) + 1 + dxgr = (grw - nxgr * cont_size - (nxgr - 1) * cont2cont)/2 + dygr = ((2 * grw + w + 2*(ply_ext_cmp + ply2gr)) - nygr * cont_size - (nygr - 1) * cont2cont)/2 + nxgr_h = int(((2 * (ld + ld_violat) + l + 2*cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)) - 2*cont2cont)/(cont2cont+cont_size)) + 1 + dxgr_h = ((2 * (ld + ld_violat) + l + cont2cont + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)) - nxgr_h * cont_size - (nxgr_h - 1) * cont2cont)/2 + + # Inserting Guard Ring contacts + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((-cmp2cmp - grw + dxgr), (-(ply_ext_cmp+ply2gr) - grw + dygr))), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nxgr, nygr)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-(2*cmp2cont) + dxgr_h, -(2*cont_size) - ply2gr - dxgr)), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, -(cont2cont+cont_size)), nxgr_h, nxgr)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(2 * (ld + ld_violat) + l + grw - dxgr + (cmp2cmp-cont_size) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont), (-(ply_ext_cmp+ply2gr) - grw + dygr))), + pya.Point.new(-(cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nxgr, nygr)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((-(2*cmp2cont) + dxgr_h), (w + (ply_ext_cmp+ply2gr) + dxgr))), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nxgr_h, nxgr)) + + else: + if deepnwell == True: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_ncmp,-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_ncmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell + dg_enc_dnwell)) + + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_ncmp,-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_ncmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell + dg_enc_dnwell)) + + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_ncmp,-dg_enc_dnwell-dnwell_enc_lvpwell-lvpwell_enc_ncmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell + dg_enc_dnwell)) + + # Inserting LVPWELL + cell.shapes(lvpwell).insert(pya.Box(-lvpwell_enc_ncmp,-lvpwell_enc_ncmp, + (2 * (ld + ld_violat) + l + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp)) + + # Inserting DNWELL + cell.shapes(dnwell).insert(pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_ncmp,-dnwell_enc_lvpwell-lvpwell_enc_ncmp, + (2 * (ld + ld_violat) + l + dnwell_enc_lvpwell + lvpwell_enc_ncmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell)) + + # Inserting Double Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_ncmp - pcmp_gr2dnw, -dnwell_enc_lvpwell-lvpwell_enc_ncmp - pcmp_gr2dnw , + (2 * (ld + ld_violat) + l + dnwell_enc_lvpwell + lvpwell_enc_ncmp + pcmp_gr2dnw + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell + pcmp_gr2dnw) + cmp_outer = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_ncmp - pcmp_gr2dnw - gr_w, -dnwell_enc_lvpwell-lvpwell_enc_ncmp - pcmp_gr2dnw - gr_w, + (2 * (ld + ld_violat) + l + dnwell_enc_lvpwell + lvpwell_enc_ncmp + pcmp_gr2dnw + gr_w + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell + pcmp_gr2dnw + gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_ncmp - pcmp_gr2dnw + pp_enc_cmp, -dnwell_enc_lvpwell-lvpwell_enc_ncmp - pcmp_gr2dnw + pp_enc_cmp , + (2 * (ld + ld_violat) + l + dnwell_enc_lvpwell + lvpwell_enc_ncmp + pcmp_gr2dnw - pp_enc_cmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell + pcmp_gr2dnw - pp_enc_cmp) + pp_outer = pya.Box(-dnwell_enc_lvpwell-lvpwell_enc_ncmp - pcmp_gr2dnw - gr_w - pp_enc_cmp, -dnwell_enc_lvpwell-lvpwell_enc_ncmp - pcmp_gr2dnw - gr_w - pp_enc_cmp, + (2 * (ld + ld_violat) + l + dnwell_enc_lvpwell + lvpwell_enc_ncmp + pcmp_gr2dnw + gr_w + pp_enc_cmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + lvpwell_enc_ncmp + dnwell_enc_lvpwell + pcmp_gr2dnw + gr_w + pp_enc_cmp) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + cell.shapes(pplus).insert(pp_gr) + + else: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(- dg_enc_cmp, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + cell.shapes(dualgate).insert(pya.Box(- dg_enc_cmp, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(- dg_enc_cmp, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + + cell.flatten(True) + return cell + +def draw_pmos(layout, l, w, ld, nf, grw, bulk, volt, deepnwell, pcmpgr): + ''' + Usage:- + used to draw PMOS transistor by specifying parameters + Arguments:- + layout : Object of layout + l : Float of gate length + w : Float of gate width + ld : Float of diffusion length + nf : Integer of number of fingers + grw : Float of guard ring width [If enabled] + bulk : String of bulk connection type [None, Bulk Tie, Guard Ring] + volt : String of operating voltage of the MOSFET [3.3V, 5V, 6V] + deepnwell : Boolean of using Deep NWELL device + pcmpgr : Boolean of using P+ Guard Ring for Deep NWELL devices only + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + dualgate = layout.layer(55 , 0 ) + v5_xtor = layout.layer(112, 1 ) + nwell = layout.layer(21 , 0 ) + comp = layout.layer(22 , 0 ) + poly2 = layout.layer(30 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + + # Define variables + dbu_PERCISION = 1/layout.dbu + nf = int(nf) + grw = grw * dbu_PERCISION + ld = ld * dbu_PERCISION + l = l * dbu_PERCISION + w = w * dbu_PERCISION + cmp2cont = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + np_enc_cmp = 0.16 * dbu_PERCISION + pp_enc_cmp = 0.16 * dbu_PERCISION + cont2ply = 0.15 * dbu_PERCISION + ply_ext_cmp = 0.22 * dbu_PERCISION + np_enc_gate = 0.23 * dbu_PERCISION + cont2cont = 0.28 * dbu_PERCISION + dg_enc_ply = 0.4 * dbu_PERCISION + dg_enc_cmp = 0.24 * dbu_PERCISION + cmp2cmp = 0.28 * dbu_PERCISION + ply2gr = 0.1 * dbu_PERCISION + nwell_enc_pcomp = 0.43 * dbu_PERCISION + nwell_enc_ncomp = 0.12 * dbu_PERCISION + ld_violat = 0 * dbu_PERCISION + tie_violat = 0 * dbu_PERCISION + metal_violat = 0.01 * dbu_PERCISION + min_cmp_area = 0.2025 * dbu_PERCISION * dbu_PERCISION + dg_enc_dnwell = 0.5 * dbu_PERCISION + dnwell_enc_ncmp = 0.62 * dbu_PERCISION + dnwell_enc_pcmp = 0.93 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + + if deepnwell == True: + cmp2cmp = 0.36 * dbu_PERCISION + ply2gr = 0.3 * dbu_PERCISION + + if volt == "5V" or volt == "6V": + cmp2cmp = 0.36 * dbu_PERCISION + ply2gr = 0.3 * dbu_PERCISION + cmp2cmp = 0.36 * dbu_PERCISION + dnwell_enc_ncmp = 0.66 * dbu_PERCISION + dnwell_enc_pcmp = 1.1 * dbu_PERCISION + nwell_enc_pcomp = 0.6 * dbu_PERCISION + nwell_enc_ncomp = 0.16 * dbu_PERCISION + + if w < cont_size+2*cmp2cont: + if nf == 1: + if volt == "5V" or volt == "6V": + ld_violat = 0.22 * dbu_PERCISION + else: + ld_violat = 0.02 * dbu_PERCISION + + # Inserting PMOS cell + cell_index = layout.add_cell("pmos") + cell = layout.cell(cell_index) + + w_changed = False + + # Inserting diffusion + if w < cont_size+2*cmp2cont: + cell.shapes(comp).insert(pya.Box(0, (cont_size+2*cmp2cont - w)/2, (2 * (ld + ld_violat) + l + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), w + (cont_size+2*cmp2cont - w)/2)) + w = cont_size+2*cmp2cont + w_changed = True + else: + cell.shapes(comp).insert(pya.Box(0, 0, (2 * ld + l + (nf - 1) * (ld + l + cont2ply - cmp2cont)), w)) + + cell.shapes(pplus).insert(pya.Box(-np_enc_cmp, -np_enc_gate, (2 * (ld + ld_violat) + l + np_enc_cmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), w + np_enc_gate)) + + # Inserting gate/s + # Inserting a gate cell + gate_cell_index = layout.add_cell("gate") + gate_cell = layout.cell(gate_cell_index) + gate_cell.shapes(poly2).insert(pya.Box(ld + ld_violat, -ply_ext_cmp, (ld + ld_violat + l), (w + ply_ext_cmp))) + + # adding gate array + cell.insert(pya.CellInstArray.new(gate_cell_index, pya.Trans.new(pya.Point.new(0, 0)), + pya.Point.new(ld + ld_violat + l + cont2ply - cmp2cont, 0), pya.Point.new(0, 0), int(nf), 1)) + + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + + # Inserting shapes now into the *contact* cell + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Contact array count and postions + nx = int((ld - (cont_size+cmp2cont+cont2ply))/(cont2cont+cont_size)) + 1 + ny = int((w - (cont_size+2*cmp2cont))/(cont2cont+cont_size)) + 1 + dx = (ld - nx * cont_size - (nx - 1) * cont2cont)*cmp2cont/cont_size + dy = (w - ny * cont_size - (ny - 1) * cont2cont)/2 + + # adding contact array and metals + # Left contacts + if not (w_changed == True and nf > 1) and (ld >= 440): + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(dx, dy)), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nx, ny)) + # Left metal + cell.shapes(metal1).insert(pya.Box(-metal_violat, -metal_violat, ld + metal_violat - (cont_size-2*cmp2cont), w + metal_violat)) + + # Adding diffusion to avoid contact violation + if nf == 1 and w_changed == True: + cell.shapes(comp).insert(pya.Box(0, 0, ld - (cont_size-2*cmp2cont), w)) + + # Right contacts and metals for each finger + for i in range(nf): + # Contacts + if not (w_changed == True and nf > 1) and (ld >= 440): + cell.insert(pya.CellInstArray.new(cont_cell_index, + pya.Trans.new(pya.Point.new(((l + ld + ld_violat + cont2ply - cmp2cont) * i + 2 * (ld + ld_violat) + l - cont_size - dx), dy)), + pya.Point.new(-(cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nx, ny)) + # Metals + cell.shapes(metal1).insert(pya.Box((ld + 2 * ld_violat + l + cont2ply - cmp2cont)*(i + 1), - metal_violat, + ld + metal_violat + ld_violat + (ld + ld_violat + l + cont2ply - cmp2cont)*(i + 1) - (cont_size-2*cmp2cont), w + metal_violat)) + + # Adding diffusion to avoid contact violation + if nf == 1 and w_changed == True: + cell.shapes(comp).insert(pya.Box((ld + 2 * ld_violat + l + cont2ply - cmp2cont)*(i + 1), 0, ld + ld_violat + (ld + ld_violat + l + cont2ply - cmp2cont)*(i + 1) - (cont_size-2*cmp2cont), w)) + region = pya.Region.new(cell.begin_shapes_rec(comp)) + region.merge() + cell.clear(comp) + cell.shapes(comp).insert(region) + + if bulk == "Bulk Tie": + if deepnwell == True: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_ncmp-cmp2cmp-ld,-dg_enc_dnwell-dnwell_enc_pcmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_pcmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + dg_enc_dnwell)) + + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_ncmp-cmp2cmp-ld,-dg_enc_dnwell-dnwell_enc_pcmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_pcmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + dg_enc_dnwell)) + + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_ncmp-cmp2cmp-ld,-dg_enc_dnwell-dnwell_enc_pcmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_pcmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + dg_enc_dnwell)) + + # Inserting DNWELL + cell.shapes(dnwell).insert(pya.Box(-dnwell_enc_ncmp-cmp2cmp-ld,-dnwell_enc_pcmp, + (2 * (ld + ld_violat) + l + dnwell_enc_pcmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp)) + + # Inserting Double Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-dnwell_enc_ncmp-cmp2cmp-ld-pcmp_gr2dnw, -dnwell_enc_pcmp-pcmp_gr2dnw, + (2 * (ld + ld_violat) + l + dnwell_enc_pcmp + pcmp_gr2dnw + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + pcmp_gr2dnw) + cmp_outer = pya.Box(-dnwell_enc_ncmp-cmp2cmp-ld-pcmp_gr2dnw-gr_w, -dnwell_enc_pcmp-pcmp_gr2dnw-gr_w, + (2 * (ld + ld_violat) + l + dnwell_enc_pcmp + pcmp_gr2dnw + gr_w + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + pcmp_gr2dnw + gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-dnwell_enc_ncmp-cmp2cmp-ld-pcmp_gr2dnw+pp_enc_cmp, -dnwell_enc_pcmp-pcmp_gr2dnw+pp_enc_cmp, + (2 * (ld + ld_violat) + l + dnwell_enc_pcmp + pcmp_gr2dnw - pp_enc_cmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + pcmp_gr2dnw - pp_enc_cmp) + pp_outer = pya.Box(-dnwell_enc_ncmp-cmp2cmp-ld-pcmp_gr2dnw-gr_w- pp_enc_cmp, -dnwell_enc_pcmp-pcmp_gr2dnw-gr_w- pp_enc_cmp, + (2 * (ld + ld_violat) + l + dnwell_enc_pcmp + pcmp_gr2dnw + gr_w + pp_enc_cmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + pcmp_gr2dnw + gr_w + pp_enc_cmp) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + cell.shapes(pplus).insert(pp_gr) + + else: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(- (cmp2cmp+dg_enc_cmp) - ld, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + cell.shapes(dualgate).insert(pya.Box(- (cmp2cmp+dg_enc_cmp) - ld, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(- (cmp2cmp+dg_enc_cmp) - ld, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + + # Inserting nwell + cell.shapes(nwell).insert(pya.Box(- nwell_enc_ncomp - cmp2cmp - ld, -nwell_enc_pcomp, (2 * (ld + ld_violat) + l + nwell_enc_pcomp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + nwell_enc_pcomp)) + + # Inserting Tie + if (w * ld) < min_cmp_area: + tie_violat = (min_cmp_area/ld - w)/2 * tol + cell.shapes(comp).insert(pya.Box(- cmp2cmp - ld, -tie_violat, -cmp2cmp, w + tie_violat)) + cell.shapes(nplus).insert(pya.Box(- cmp2cmp - np_enc_cmp - ld, -np_enc_cmp-tie_violat, -cmp2cmp+np_enc_cmp, w + tie_violat + np_enc_cmp)) + + # Tie contacts + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((- (cmp2cmp+cont_size) - dx * cont_size/(2 *cmp2cont)), dy)), + pya.Point.new(-(cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nx, ny)) + + # Tie metal + cell.shapes(metal1).insert(pya.Box(- cmp2cmp - ld, -tie_violat, -cmp2cmp, w + tie_violat)) + + elif bulk == "Guard Ring": + if deepnwell == True: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_ncmp-cmp2cmp - grw, + -dg_enc_dnwell-dnwell_enc_ncmp-(ply_ext_cmp + ply2gr) - grw, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + dnwell_enc_ncmp + dg_enc_dnwell + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + dnwell_enc_ncmp + dg_enc_dnwell))) + + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_ncmp-cmp2cmp - grw, + -dg_enc_dnwell-dnwell_enc_ncmp-(ply_ext_cmp + ply2gr) - grw, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + dnwell_enc_ncmp + dg_enc_dnwell + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + dnwell_enc_ncmp + dg_enc_dnwell))) + + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_ncmp-cmp2cmp - grw, + -dg_enc_dnwell-dnwell_enc_ncmp-(ply_ext_cmp + ply2gr) - grw, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + dnwell_enc_ncmp + dg_enc_dnwell + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + dnwell_enc_ncmp + dg_enc_dnwell))) + + # Inserting DNWELL + cell.shapes(dnwell).insert(pya.Box(-dnwell_enc_ncmp-cmp2cmp - grw, + -dnwell_enc_ncmp-(ply_ext_cmp + ply2gr) - grw, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + dnwell_enc_ncmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + dnwell_enc_ncmp))) + + # Inserting Double Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-dnwell_enc_ncmp-cmp2cmp - grw - pcmp_gr2dnw, + -dnwell_enc_ncmp-(ply_ext_cmp + ply2gr) - grw - pcmp_gr2dnw, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + dnwell_enc_ncmp + pcmp_gr2dnw + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + dnwell_enc_ncmp + pcmp_gr2dnw)) + cmp_outer = pya.Box(-dnwell_enc_ncmp-cmp2cmp - grw - pcmp_gr2dnw - gr_w, + -dnwell_enc_ncmp-(ply_ext_cmp + ply2gr) - grw - pcmp_gr2dnw - gr_w, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + dnwell_enc_ncmp + pcmp_gr2dnw + gr_w + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + dnwell_enc_ncmp + pcmp_gr2dnw + gr_w)) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-dnwell_enc_ncmp-cmp2cmp - grw - pcmp_gr2dnw + pp_enc_cmp, + -dnwell_enc_ncmp-(ply_ext_cmp + ply2gr) - grw - pcmp_gr2dnw + pp_enc_cmp, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + dnwell_enc_ncmp + pcmp_gr2dnw - pp_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + dnwell_enc_ncmp + pcmp_gr2dnw - pp_enc_cmp)) + pp_outer = pya.Box(-dnwell_enc_ncmp-cmp2cmp - grw - pcmp_gr2dnw - gr_w - pp_enc_cmp, + -dnwell_enc_ncmp-(ply_ext_cmp + ply2gr) - grw - pcmp_gr2dnw - gr_w - pp_enc_cmp, + (2 * (ld + ld_violat) + l + grw + cmp2cmp + dnwell_enc_ncmp + pcmp_gr2dnw + gr_w + pp_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), + (w + (ply_ext_cmp + ply2gr) + grw + dnwell_enc_ncmp + pcmp_gr2dnw + gr_w + pp_enc_cmp)) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + cell.shapes(pplus).insert(pp_gr) + + else: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(-(cmp2cmp+dg_enc_cmp) - grw, -(ply_ext_cmp+ply2gr+dg_enc_cmp) - grw, (2 * (ld + ld_violat) + l + grw + (cmp2cmp+dg_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + ply_ext_cmp+ply2gr+dg_enc_cmp + grw))) + cell.shapes(dualgate).insert(pya.Box(-(cmp2cmp+dg_enc_cmp) - grw, -(ply_ext_cmp+ply2gr+dg_enc_cmp) - grw, (2 * (ld + ld_violat) + l + grw + (cmp2cmp+dg_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + ply_ext_cmp+ply2gr+dg_enc_cmp + grw))) + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(-(cmp2cmp+dg_enc_cmp) - grw, -(ply_ext_cmp+ply2gr+dg_enc_cmp) - grw, (2 * (ld + ld_violat) + l + grw + (cmp2cmp+dg_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + ply_ext_cmp+ply2gr+dg_enc_cmp + grw))) + + # Inserting nwell + cell.shapes(nwell).insert(pya.Box(- nwell_enc_ncomp - cmp2cmp - grw, - ply_ext_cmp - ply2gr - nwell_enc_ncomp - grw, (2 * (ld + ld_violat) + l + grw + nwell_enc_ncomp + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + ply_ext_cmp + ply2gr + nwell_enc_ncomp + grw))) + + # Inserting Guard Ring diffusion + cell.shapes(comp).insert( + pya.Polygon( + [ + pya.Point(-cmp2cmp - grw, -(ply_ext_cmp + ply2gr) - grw), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp, -(ply_ext_cmp + ply2gr)), + pya.Point((2 * (ld + ld_violat) + l + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr)), + pya.Point((2 * (ld + ld_violat) + l + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr) - grw), + ], + True, + ) + ) + cell.shapes(nplus).insert( + pya.Polygon( + [ + pya.Point(-(cmp2cmp+pp_enc_cmp) - grw, -(ply_ext_cmp + ply2gr + pp_enc_cmp) - grw), + pya.Point(-(cmp2cmp+pp_enc_cmp) - grw, (w + (ply_ext_cmp + ply2gr - pp_enc_cmp))), + pya.Point(-(cmp2cmp-pp_enc_cmp), (w + (ply_ext_cmp + ply2gr - pp_enc_cmp))), + pya.Point(-(cmp2cmp-pp_enc_cmp), -(ply_ext_cmp + ply2gr - pp_enc_cmp)), + pya.Point((2 * (ld + ld_violat) + l + (cmp2cmp-pp_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr - pp_enc_cmp)), + pya.Point((2 * (ld + ld_violat) + l + (cmp2cmp-pp_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr - pp_enc_cmp))), + pya.Point(-(cmp2cmp+pp_enc_cmp) - grw, (w + (ply_ext_cmp + ply2gr - pp_enc_cmp))), + pya.Point(-(cmp2cmp+pp_enc_cmp) - grw, (w + (ply_ext_cmp + ply2gr + pp_enc_cmp) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + (cmp2cmp+pp_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr + pp_enc_cmp) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + (cmp2cmp+pp_enc_cmp) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr + pp_enc_cmp) - grw), + ], + True, + ) + ) + + # Inserting Guard Ring metal + cell.shapes(metal1).insert( + pya.Polygon( + [ + pya.Point(-cmp2cmp - grw, -(ply_ext_cmp + ply2gr) - grw), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp, -(ply_ext_cmp + ply2gr)), + pya.Point((2 * (ld + ld_violat) + l + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr)), + pya.Point((2 * (ld + ld_violat) + l + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr))), + pya.Point(-cmp2cmp - grw, (w + (ply_ext_cmp + ply2gr) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), (w + (ply_ext_cmp + ply2gr) + grw)), + pya.Point((2 * (ld + ld_violat) + l + grw + cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), -(ply_ext_cmp + ply2gr) - grw), + ], + True, + ) + ) + + nxgr = int((grw - (cont_size+2*cmp2cont))/(cont2cont+cont_size)) + 1 + nygr = int(((2 * grw + w + 2*(ply_ext_cmp + ply2gr)) - (cont_size+2*cmp2cont))/(cont2cont+cont_size)) + 1 + dxgr = (grw - nxgr * cont_size - (nxgr - 1) * cont2cont)/2 + dygr = ((2 * grw + w + 2*(ply_ext_cmp + ply2gr)) - nygr * cont_size - (nygr - 1) * cont2cont)/2 + nxgr_h = int(((2 * (ld + ld_violat) + l + 2*cmp2cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)) - 2*cont2cont)/(cont2cont+cont_size)) + 1 + dxgr_h = ((2 * (ld + ld_violat) + l + cont2cont + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)) - nxgr_h * cont_size - (nxgr_h - 1) * cont2cont)/2 + + # Inserting Guard Ring contacts + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((-cmp2cmp - grw + dxgr), (-(ply_ext_cmp+ply2gr) - grw + dygr))), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nxgr, nygr)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-(2*cmp2cont) + dxgr_h, -(2*cont_size) - ply2gr - dxgr)), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, -(cont2cont+cont_size)), nxgr_h, nxgr)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(2 * (ld + ld_violat) + l + grw - dxgr + (cmp2cmp-cont_size) + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont), (-(ply_ext_cmp+ply2gr) - grw + dygr))), + pya.Point.new(-(cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nxgr, nygr)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((-(2*cmp2cont) + dxgr_h), (w + (ply_ext_cmp+ply2gr) + dxgr))), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nxgr_h, nxgr)) + + else: + if deepnwell == True: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_pcmp,-dg_enc_dnwell-dnwell_enc_pcmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_pcmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + dg_enc_dnwell)) + + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_pcmp,-dg_enc_dnwell-dnwell_enc_pcmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_pcmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + dg_enc_dnwell)) + + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(-dg_enc_dnwell-dnwell_enc_pcmp,-dg_enc_dnwell-dnwell_enc_pcmp, + (2 * (ld + ld_violat) + l + dg_enc_dnwell + dnwell_enc_pcmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + dg_enc_dnwell)) + + # Inserting DNWELL + cell.shapes(dnwell).insert(pya.Box(-dnwell_enc_pcmp,-dnwell_enc_pcmp, + (2 * (ld + ld_violat) + l + dnwell_enc_pcmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp)) + + # Inserting Double Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-dnwell_enc_pcmp - pcmp_gr2dnw, -dnwell_enc_pcmp - pcmp_gr2dnw, + (2 * (ld + ld_violat) + l + dnwell_enc_pcmp + pcmp_gr2dnw + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + pcmp_gr2dnw) + cmp_outer = pya.Box(-dnwell_enc_pcmp - pcmp_gr2dnw - gr_w, -dnwell_enc_pcmp - pcmp_gr2dnw - gr_w, + (2 * (ld + ld_violat) + l + dnwell_enc_pcmp + pcmp_gr2dnw + gr_w + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + pcmp_gr2dnw + gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-dnwell_enc_pcmp - pcmp_gr2dnw + pp_enc_cmp, -dnwell_enc_pcmp - pcmp_gr2dnw + pp_enc_cmp, + (2 * (ld + ld_violat) + l + dnwell_enc_pcmp + pcmp_gr2dnw - pp_enc_cmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + pcmp_gr2dnw - pp_enc_cmp) + pp_outer = pya.Box(-dnwell_enc_pcmp - pcmp_gr2dnw - gr_w - pp_enc_cmp, -dnwell_enc_pcmp - pcmp_gr2dnw - gr_w - pp_enc_cmp, + (2 * (ld + ld_violat) + l + dnwell_enc_pcmp + pcmp_gr2dnw + gr_w + pp_enc_cmp + (nf - 1) * (ld + ld_violat + l + cont2ply - cmp2cont)), + w + dnwell_enc_pcmp + pcmp_gr2dnw + gr_w + pp_enc_cmp) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + cell.shapes(pplus).insert(pp_gr) + + else: + if volt == "5V": + # Inserting 5V layers + cell.shapes(v5_xtor).insert(pya.Box(- dg_enc_cmp, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + cell.shapes(dualgate).insert(pya.Box(- dg_enc_cmp, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + elif volt == "6V": + # Inserting 6V layers + cell.shapes(dualgate).insert(pya.Box(- dg_enc_cmp, -(dg_enc_ply+ply_ext_cmp), (2 * (ld + ld_violat) + l + dg_enc_cmp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + (dg_enc_ply+ply_ext_cmp))) + + # Inserting NWELL + cell.shapes(nwell).insert(pya.Box(- nwell_enc_pcomp, -nwell_enc_pcomp, (2 * (ld + ld_violat) + l + nwell_enc_pcomp + (nf - 1) * ((ld + ld_violat) + l + cont2ply - cmp2cont)), w + nwell_enc_pcomp)) + + + cell.flatten(True) + return cell + +def draw_nmos_6p0_nat(layout, l, w, ld, nf, grw, bulk): + ''' + Usage:- + used to draw Native NMOS 6V transistor by specifying parameters + Arguments:- + layout : Object of layout + l : Float of gate length + w : Float of gate width + ld : Float of diffusion length + nf : Integer of number of fingers + grw : Float of guard ring width [If enabled] + bulk : String of bulk connection type [None, Bulk Tie, Guard Ring] + ''' + + # Define layers + dualgate = layout.layer(55 , 0 ) + nat = layout.layer(5 , 0 ) + comp = layout.layer(22 , 0 ) + poly2 = layout.layer(30 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + + # Define variables + dbu_PERCISION = 1/layout.dbu + nf = int(nf) + grw = grw * dbu_PERCISION + ld = ld * dbu_PERCISION + l = l * dbu_PERCISION + w = w * dbu_PERCISION + cmp2cont = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + np_enc_cmp = 0.16 * dbu_PERCISION + pp_enc_cmp = 0.16 * dbu_PERCISION + cont2ply = 0.15 * dbu_PERCISION + ply_ext_cmp = 0.22 * dbu_PERCISION + np_enc_gate = 0.23 * dbu_PERCISION + cont2cont = 0.28 * dbu_PERCISION + cmp2cmp = 0.36 * dbu_PERCISION + nat_enc_cmp = 2 * dbu_PERCISION + + # Inserting NMOS cell + cell_index = layout.add_cell("nmos_6p0_nat") + cell = layout.cell(cell_index) + + # Inserting diffusion + cell.shapes(comp).insert(pya.Box(0, 0, (2 * ld + l + (nf - 1) * (ld + l + cont2ply - cmp2cont)), w)) + cell.shapes(nplus).insert(pya.Box(-np_enc_cmp, -np_enc_gate, (2 * ld + l + np_enc_cmp + (nf - 1) * (ld + l + cont2ply - cmp2cont)), w + np_enc_gate)) + cell.shapes(nat).insert(pya.Box(-nat_enc_cmp, -nat_enc_cmp, (2 * ld + l + nat_enc_cmp + (nf - 1) * (ld + l + cont2ply - cmp2cont)), w + nat_enc_cmp)) + cell.shapes(dualgate).insert(pya.Box(-nat_enc_cmp, -nat_enc_cmp, (2 * ld + l + nat_enc_cmp + (nf - 1) * (ld + l + cont2ply - cmp2cont)), w + nat_enc_cmp)) + + # Inserting gate/s + # Inserting a gate cell + gate_cell_index = layout.add_cell("gate") + gate_cell = layout.cell(gate_cell_index) + gate_cell.shapes(poly2).insert(pya.Box(ld, -ply_ext_cmp, (ld + l), (w + ply_ext_cmp))) + + # adding gate array + cell.insert(pya.CellInstArray.new(gate_cell_index, pya.Trans.new(pya.Point.new(0, 0)), + pya.Point.new(ld + l + cont2ply - cmp2cont, 0), pya.Point.new(0, 0), int(nf), 1)) + + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + + # Inserting shapes now into the *contact* cell + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Contact array count and postions + nx = int((ld - (cont_size+cmp2cont+cont2ply))/(cont2cont+cont_size)) + 1 + ny = int((w - (cont_size+2*cmp2cont))/(cont2cont+cont_size)) + 1 + dx = (ld - nx * cont_size - (nx - 1) * cont2cont)*cmp2cont/cont_size + dy = (w - ny * cont_size - (ny - 1) * cont2cont)/2 + + # adding contact array and metals + # Left contacts + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(dx, dy)), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nx, ny)) + # Left metal + cell.shapes(metal1).insert(pya.Box(0, 0, ld - (cont_size-2*cmp2cont), w)) + + # Right contacts and metals for each finger + for i in range(nf): + # Contacts + cell.insert(pya.CellInstArray.new(cont_cell_index, + pya.Trans.new(pya.Point.new(((l + ld + cont2ply - cmp2cont) * i + 2 * ld + l - cont_size - dx), dy)), + pya.Point.new(-(cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nx, ny)) + # Metals + cell.shapes(metal1).insert(pya.Box((ld + l + cont2ply - cmp2cont)*(i + 1), 0, ld + (ld + l + cont2ply - cmp2cont)*(i + 1) - (cont_size-2*cmp2cont), w)) + + if bulk == "Bulk Tie": + # Inserting tie + cell.shapes(comp).insert(pya.Box(- (nat_enc_cmp + cmp2cmp) - ld, 0, -(nat_enc_cmp + cmp2cmp), w)) + cell.shapes(pplus).insert(pya.Box(- (nat_enc_cmp + cmp2cmp + pp_enc_cmp) - ld, -pp_enc_cmp, -(nat_enc_cmp + cmp2cmp - pp_enc_cmp), w + pp_enc_cmp)) + + # Tie contacts + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((- (nat_enc_cmp + cmp2cmp + cont_size) - dx * cont_size/(2 *cmp2cont)), dy)), + pya.Point.new(-(cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nx, ny)) + + # Tie metal + cell.shapes(metal1).insert(pya.Box(- (nat_enc_cmp + cmp2cmp) - ld, 0, -(nat_enc_cmp + cmp2cmp), w)) + + elif bulk == "Guard Ring": + # Inserting Guard Ring diffusion + cell.shapes(comp).insert( + pya.Polygon( + [ + pya.Point(-(nat_enc_cmp + cmp2cmp) - grw, -(nat_enc_cmp + cmp2cmp) - grw), + pya.Point(-(nat_enc_cmp + cmp2cmp) - grw, (w + (nat_enc_cmp + cmp2cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp), (w + (nat_enc_cmp + cmp2cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp), -(nat_enc_cmp + cmp2cmp)), + pya.Point((2 * ld + l + (nat_enc_cmp + cmp2cmp) + (nf - 1) * (ld + l)), -(nat_enc_cmp + cmp2cmp)), + pya.Point((2 * ld + l + (nat_enc_cmp + cmp2cmp) + (nf - 1) * (ld + l)), (w + (nat_enc_cmp + cmp2cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp) - grw, (w + (nat_enc_cmp + cmp2cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp) - grw, (w + (nat_enc_cmp + cmp2cmp) + grw)), + pya.Point((2 * ld + l + grw + (nat_enc_cmp + cmp2cmp) + (nf - 1) * (ld + l)), (w + (nat_enc_cmp + cmp2cmp) + grw)), + pya.Point((2 * ld + l + grw + (nat_enc_cmp + cmp2cmp) + (nf - 1) * (ld + l)), -(nat_enc_cmp + cmp2cmp) - grw), + ], + True, + ) + ) + cell.shapes(pplus).insert( + pya.Polygon( + [ + pya.Point(-(nat_enc_cmp + cmp2cmp + pp_enc_cmp) - grw, -(nat_enc_cmp + cmp2cmp + pp_enc_cmp) - grw), + pya.Point(-(nat_enc_cmp + cmp2cmp + pp_enc_cmp) - grw, (w + (nat_enc_cmp + cmp2cmp - pp_enc_cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp - pp_enc_cmp), (w + (nat_enc_cmp + cmp2cmp - pp_enc_cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp - pp_enc_cmp), -(nat_enc_cmp + cmp2cmp - pp_enc_cmp)), + pya.Point((2 * ld + l + (nat_enc_cmp + cmp2cmp - pp_enc_cmp) + (nf - 1) * (ld + l)), -(nat_enc_cmp + cmp2cmp - pp_enc_cmp)), + pya.Point((2 * ld + l + (nat_enc_cmp + cmp2cmp - pp_enc_cmp) + (nf - 1) * (ld + l)), (w + (nat_enc_cmp + cmp2cmp - pp_enc_cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp + pp_enc_cmp) - grw, (w + (nat_enc_cmp + cmp2cmp - pp_enc_cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp + pp_enc_cmp) - grw, (w + (nat_enc_cmp + cmp2cmp + pp_enc_cmp) + grw)), + pya.Point((2 * ld + l + grw + (nat_enc_cmp + cmp2cmp + pp_enc_cmp) + (nf - 1) * (ld + l)), (w + (nat_enc_cmp + cmp2cmp + pp_enc_cmp) + grw)), + pya.Point((2 * ld + l + grw + (nat_enc_cmp + cmp2cmp + pp_enc_cmp) + (nf - 1) * (ld + l)), -(nat_enc_cmp + cmp2cmp + pp_enc_cmp) - grw), + ], + True, + ) + ) + + # Inserting Guard Ring metal + cell.shapes(metal1).insert( + pya.Polygon( + [ + pya.Point(-(nat_enc_cmp + cmp2cmp) - grw, -(nat_enc_cmp + cmp2cmp) - grw), + pya.Point(-(nat_enc_cmp + cmp2cmp) - grw, (w + (nat_enc_cmp + cmp2cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp), (w + (nat_enc_cmp + cmp2cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp), -(nat_enc_cmp + cmp2cmp)), + pya.Point((2 * ld + l + (nat_enc_cmp + cmp2cmp) + (nf - 1) * (ld + l)), -(nat_enc_cmp + cmp2cmp)), + pya.Point((2 * ld + l + (nat_enc_cmp + cmp2cmp) + (nf - 1) * (ld + l)), (w + (nat_enc_cmp + cmp2cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp) - grw, (w + (nat_enc_cmp + cmp2cmp))), + pya.Point(-(nat_enc_cmp + cmp2cmp) - grw, (w + (nat_enc_cmp + cmp2cmp) + grw)), + pya.Point((2 * ld + l + grw + (nat_enc_cmp + cmp2cmp) + (nf - 1) * (ld + l)), (w + (nat_enc_cmp + cmp2cmp) + grw)), + pya.Point((2 * ld + l + grw + (nat_enc_cmp + cmp2cmp) + (nf - 1) * (ld + l)), -(nat_enc_cmp + cmp2cmp) - grw), + ], + True, + ) + ) + + nxgr = int((grw - (cont_size+2*cmp2cont))/(cont2cont+cont_size)) + 1 + nygr = int(((2 * grw + w + 2*(nat_enc_cmp + cmp2cmp)) - (cont_size+2*cmp2cont))/(cont2cont+cont_size)) + 1 + dxgr = (grw - nxgr * cont_size - (nxgr - 1) * cont2cont)/2 + dygr = ((2 * grw + w + 2*(nat_enc_cmp + cmp2cmp)) - nygr * cont_size - (nygr - 1) * cont2cont)/2 + nxgr_h = int(((2 * ld + l + 2*(nat_enc_cmp + cmp2cmp) + (nf - 1) * (ld + l))- 2*cont2cont)/(cont2cont+cont_size)) + 1 + dxgr_h = ((2 * ld + l + (nat_enc_cmp + cmp2cmp) + (nf - 1) * (ld + l)) - nxgr_h * cont_size - (nxgr_h - 1) * cont2cont)/2 + + # Inserting Guard Ring contacts + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((-(nat_enc_cmp + cmp2cmp) - grw + dxgr), (-(nat_enc_cmp + cmp2cmp) - grw + dygr))), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nxgr, nygr)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-(nat_enc_cmp + cmp2cmp)/2 + dxgr_h, -(nat_enc_cmp + cmp2cmp + cont_size) - dxgr)), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, -(cont2cont+cont_size)), nxgr_h, nxgr)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(2 * ld + l + grw - dxgr + nat_enc_cmp + cmp2cmp - cont_size + (nf - 1) * (ld + l), (-(nat_enc_cmp + cmp2cmp) - grw + dygr))), + pya.Point.new(-(cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nxgr, nygr)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-(nat_enc_cmp + cmp2cmp)/2 + dxgr_h, w + (nat_enc_cmp + cmp2cmp) + dxgr)), + pya.Point.new((cont2cont+cont_size), 0), pya.Point.new(0, (cont2cont+cont_size)), nxgr_h, nxgr)) + + cell.flatten(True) + return cell + +def draw_nmos_10p0_asym(layout, l, w): + ''' + Usage:- + used to draw LDNMOS 10V transistor by specifying parameters + Arguments:- + layout : Object of layout + l : Float of gate length + w : Float of gate width + ''' + + # Define layers + dualgate = layout.layer(55 , 0 ) + ldmos_xtor = layout.layer(226, 0 ) + mvsd = layout.layer(210, 0 ) + comp = layout.layer(22 , 0 ) + poly2 = layout.layer(30 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + + # Define variables + dbu_PERCISION = 1/layout.dbu + l = l * dbu_PERCISION + w = w * dbu_PERCISION + cmp2cont = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + np_enc_cmp = 0.16 * dbu_PERCISION + pp_enc_cmp = 0.16 * dbu_PERCISION + cont2ply = 0.15 * dbu_PERCISION + metal_w = 0.38 * dbu_PERCISION + ply_ext_cmp = 0.4 * dbu_PERCISION + ply_fld = 0.2 * dbu_PERCISION + np_enc_gate = 0.23 * dbu_PERCISION + cont2cont = 0.25 * dbu_PERCISION + cmp2cmp = 0.36 * dbu_PERCISION + cmp2gr = 0.4 * dbu_PERCISION + mvsd_ext_cmp = 0.5 * dbu_PERCISION + mvsd_ov_cmp = 0.4 * dbu_PERCISION + mvsd2gr = 1 * dbu_PERCISION + ply2gr = 0.4 * dbu_PERCISION + drain2ply = 0.16 * dbu_PERCISION + dg_enc_cmp = 0.5 * dbu_PERCISION + + + # Inserting NMOS cell + cell_index = layout.add_cell("nmos_10p0_asym") + cell = layout.cell(cell_index) + + # Inserting layers for LDMOS + cell.shapes(dualgate).insert(pya.Box( + -(dg_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont2ply+cont_size+cmp2cont+mvsd_ov_cmp+cmp2cmp) - l, -(mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size+dg_enc_cmp) - w/2, + (dg_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont2ply+cont_size+cmp2cont+mvsd_ov_cmp+cmp2cmp) + l, (mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size+dg_enc_cmp) + w/2)) + cell.shapes(ldmos_xtor).insert(pya.Box( + -(dg_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont2ply+cont_size+cmp2cont+mvsd_ov_cmp+cmp2cmp) - l, -(mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size+dg_enc_cmp) - w/2, + (dg_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont2ply+cont_size+cmp2cont+mvsd_ov_cmp+cmp2cmp) + l, (mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size+dg_enc_cmp) + w/2)) + + # Inserting drain diffusion + cell.shapes(comp).insert(pya.Box(-cont_size/2, -w/2, cont_size/2, w/2)) + cell.shapes(mvsd).insert(pya.Box(-(cont_size/2+cmp2cmp+mvsd_ov_cmp), -w/2 - mvsd_ext_cmp, (cont_size/2+cmp2cmp+mvsd_ov_cmp), w/2 + mvsd_ext_cmp)) + + # Inserting source diffusion + cell.shapes(comp).insert(pya.Box((cont_size/2+cmp2cmp), -w/2, (cont_size/2+cmp2cmp+mvsd_ov_cmp+cont2ply+cont_size+cmp2cont) + l, w/2)) + cell.shapes(comp).insert(pya.Box(-(cont_size/2+cmp2cmp), -w/2, -(cont_size/2+cmp2cmp+mvsd_ov_cmp+cont2ply+cont_size+cmp2cont) - l, w/2)) + + cell.shapes(nplus).insert(pya.Box(-(cont_size/2+cmp2cmp+mvsd_ov_cmp+cont2ply+cont_size+cmp2cont+np_enc_cmp) - l, -w/2 - np_enc_gate, + (cont_size/2+cmp2cmp+mvsd_ov_cmp+cont2ply+cont_size+cmp2cont+np_enc_cmp) + l, w/2 + np_enc_gate)) + + # Inserting gates + cell.shapes(poly2).insert(pya.Box((cont_size/2+drain2ply), -w/2 - ply_ext_cmp, (cont_size/2+cmp2cmp+mvsd_ov_cmp) + l, w/2 + mvsd_ext_cmp+mvsd2gr-ply2gr)) + cell.shapes(poly2).insert(pya.Box(-(cont_size/2+drain2ply), -w/2 - ply_ext_cmp, -(cont_size/2+cmp2cmp+mvsd_ov_cmp) - l, w/2 + mvsd_ext_cmp+mvsd2gr-ply2gr)) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + + # Inserting shapes now into the *contact* cell + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Contact array count and postions + ny = int((w - (cont_size+2*cmp2cont))/(cont_size+cont2cont)) + 1 + dy = (w - ny * cont_size - (ny - 1) * cont2cont)/2 + ng = int(((l + mvsd_ov_cmp + ply_fld) - (cont_size+2*cmp2cont))/(cont_size+cont2cont)) + 1 + dg = (l + mvsd_ov_cmp + ply_fld - ng * cont_size - (ng - 1) * cont2cont)/2 + + # Inserting contact array and metals + # gate contacts and metal + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((cont_size/2+drain2ply) + dg, w/2 + mvsd_ext_cmp+mvsd2gr-ply2gr-(metal_w+cont_size)/2)), + pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), ng, 1)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-(1.5*cont_size+drain2ply) - dg, w/2 + mvsd_ext_cmp+mvsd2gr-ply2gr-(metal_w+cont_size)/2)), + pya.Point.new(-(cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), ng, 1)) + cell.shapes(metal1).insert(pya.Box((cont_size/2+drain2ply), w/2 + mvsd_ext_cmp+mvsd2gr-ply2gr-metal_w, + (cont_size/2+cmp2cmp+mvsd_ov_cmp) + l, w/2 + mvsd_ext_cmp+mvsd2gr-ply2gr)) + cell.shapes(metal1).insert(pya.Box(-(cont_size/2+drain2ply), w/2 + mvsd_ext_cmp+mvsd2gr-ply2gr-metal_w, + -(cont_size/2+cmp2cmp+mvsd_ov_cmp) - l, w/2 + mvsd_ext_cmp+mvsd2gr-ply2gr)) + + # Drain contacts and metal + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-cont_size/2, -w/2 + dy)), + pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, ny)) + cell.shapes(metal1).insert(pya.Box(-metal_w/2, -w/2, metal_w/2, w/2)) + + # Source contacts and metals + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((cont_size/2+cmp2cmp+mvsd_ov_cmp+cont2ply) + l, -w/2 + dy)), + pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, ny)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-(1.5*cont_size+cmp2cmp+mvsd_ov_cmp+cont2ply) - l, -w/2 + dy)), + pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, ny)) + cell.shapes(metal1).insert(pya.Box((1.5*cont_size+cmp2cmp+mvsd_ov_cmp+cont2ply+cmp2cont-metal_w) + l, -w/2, (1.5*cont_size+cmp2cmp+mvsd_ov_cmp+cont2ply+cmp2cont) + l, w/2)) + cell.shapes(metal1).insert(pya.Box(-(1.5*cont_size+cmp2cmp+mvsd_ov_cmp+cont2ply+cmp2cont-metal_w) - l, -w/2, -(1.5*cont_size+cmp2cmp+mvsd_ov_cmp+cont2ply+cmp2cont) - l, w/2)) + + # Inserting Guard Ring diffusion + cell.shapes(comp).insert( + pya.Polygon( + [ + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, -(mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size) - w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, (mvsd_ext_cmp+mvsd2gr) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, (mvsd_ext_cmp+mvsd2gr) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, -(mvsd_ext_cmp+mvsd2gr) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) + l, -(mvsd_ext_cmp+mvsd2gr) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) + l, (mvsd_ext_cmp+mvsd2gr) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, (mvsd_ext_cmp+mvsd2gr) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, (mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) + l, (mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) + l, -(mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size) - w/2), + ], + True, + ) + ) + + cell.shapes(pplus).insert( + pya.Polygon( + [ + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp+pp_enc_cmp) - l, -(mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size+pp_enc_cmp) - w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp+pp_enc_cmp) - l, (mvsd_ext_cmp+mvsd2gr-pp_enc_cmp) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp-pp_enc_cmp) - l, (mvsd_ext_cmp+mvsd2gr-pp_enc_cmp) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp-pp_enc_cmp) - l, -(mvsd_ext_cmp+mvsd2gr-pp_enc_cmp) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp-pp_enc_cmp) + l, -(mvsd_ext_cmp+mvsd2gr-pp_enc_cmp) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp-pp_enc_cmp) + l, (mvsd_ext_cmp+mvsd2gr-pp_enc_cmp) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp+pp_enc_cmp) - l, (mvsd_ext_cmp+mvsd2gr-pp_enc_cmp) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp+pp_enc_cmp) - l, (mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size+pp_enc_cmp) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp+pp_enc_cmp) + l, (mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size+pp_enc_cmp) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp+pp_enc_cmp) + l, -(mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size+pp_enc_cmp) - w/2), + ], + True, + ) + ) + + cell.shapes(metal1).insert( + pya.Polygon( + [ + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, -(mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size) - w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, (mvsd_ext_cmp+mvsd2gr) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, (mvsd_ext_cmp+mvsd2gr) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, -(mvsd_ext_cmp+mvsd2gr) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) + l, -(mvsd_ext_cmp+mvsd2gr) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) + l, (mvsd_ext_cmp+mvsd2gr) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, (mvsd_ext_cmp+mvsd2gr) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, (mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) + l, (mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) + l, -(mvsd_ext_cmp+mvsd2gr+2*cmp2cont+cont_size) - w/2), + ], + True, + ) + ) + + nygr = int((w + 2*(mvsd_ext_cmp+mvsd2gr+cmp2cont+cont_size)+cont2cont)/(cont_size+cont2cont)) + dygr = (w + 2*(mvsd_ext_cmp+mvsd2gr+cmp2cont+cont_size) - nygr * (cont_size+cont2cont)+ cont2cont)/2 + nxgr_h = int((2 * l + 2*(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp+cmp2cont)- cont2cont)/(cont_size+cont2cont)) + dxgr_h = (2 * l + 2*(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp+cmp2cont) - nxgr_h * (cont_size+cont2cont) + cont2cont)/2 + + # Inserting Guard Ring contacts + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-(cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) - l, + dygr - (mvsd_ext_cmp+mvsd2gr+cmp2cont+cont_size) - w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, nygr)) + + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(dxgr_h - (0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp+cmp2cont) - l, + -(mvsd_ext_cmp+mvsd2gr+cmp2cont+cont_size) - w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), nxgr_h, 1)) + + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((cmp2cont+0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp) + l, + dygr - (mvsd_ext_cmp+mvsd2gr+cmp2cont+cont_size) - w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, nygr)) + + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(dxgr_h - (0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvsd_ov_cmp+cmp2cmp+cmp2cont) - l, + (mvsd_ext_cmp+mvsd2gr+cmp2cont) + w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), nxgr_h, 1)) + + cell.flatten(True) + return cell + +def draw_pmos_10p0_asym(layout, l, w, dgr_en): + ''' + Usage:- + used to draw LDPMOS 10V transistor by specifying parameters + Arguments:- + layout : Object of layout + l : Float of gate length + w : Float of gate width + dgr_en : Boolean to enable double guard ring + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + dualgate = layout.layer(55 , 0 ) + ldmos_xtor = layout.layer(226, 0 ) + mvpsd = layout.layer(11 , 39) + comp = layout.layer(22 , 0 ) + poly2 = layout.layer(30 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + + # Define variables + dbu_PERCISION = 1/layout.dbu + l = l * dbu_PERCISION + w = w * dbu_PERCISION + cmp2cont = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + np_enc_cmp = 0.16 * dbu_PERCISION + pp_enc_cmp = 0.16 * dbu_PERCISION + cont2ply = 0.15 * dbu_PERCISION + metal_w = 0.38 * dbu_PERCISION + ply_ext_cmp = 0.4 * dbu_PERCISION + ply_fld = 0.2 * dbu_PERCISION + np_enc_gate = 0.23 * dbu_PERCISION + cont2cont = 0.25 * dbu_PERCISION + cmp2cmp = 0.36 * dbu_PERCISION + cmp2gr = 0.4 * dbu_PERCISION + mvpsd_ext_cmp = 0.8 * dbu_PERCISION + mvpsd_ov_cmp = 0.4 * dbu_PERCISION + mvpsd2gr = 1 * dbu_PERCISION + ply2gr = 0.4 * dbu_PERCISION + drain2ply = 0.16 * dbu_PERCISION + dnw_enc_cmp = 0.66 * dbu_PERCISION + dg_enc_pcmp = 0.5 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + + + # Inserting PMOS cell + cell_index = layout.add_cell("pmos_10p0_asym") + cell = layout.cell(cell_index) + + # Inserting layers for LDMOS + cell.shapes(dnwell).insert(pya.Box( + -(dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+dnw_enc_cmp) - w/2, + (dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+dnw_enc_cmp) + w/2)) + cell.shapes(dualgate).insert(pya.Box( + -(dg_enc_pcmp+pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+dg_enc_pcmp+pcmp_gr2dnw+dnw_enc_cmp) - w/2, + (dg_enc_pcmp+pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+dg_enc_pcmp+pcmp_gr2dnw+dnw_enc_cmp) + w/2)) + cell.shapes(ldmos_xtor).insert(pya.Box( + -(dg_enc_pcmp+pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+dg_enc_pcmp+pcmp_gr2dnw+dnw_enc_cmp) - w/2, + (dg_enc_pcmp+pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+dg_enc_pcmp+pcmp_gr2dnw+dnw_enc_cmp) + w/2)) + + # Inserting drain diffusion + cell.shapes(comp).insert(pya.Box(-cont_size/2, -w/2, cont_size/2, w/2)) + cell.shapes(mvpsd).insert(pya.Box(-(cont_size/2+cmp2cmp+mvpsd_ov_cmp), -w/2 - mvpsd_ext_cmp, (cont_size/2+cmp2cmp+mvpsd_ov_cmp), w/2 + mvpsd_ext_cmp)) + + # Inserting source diffusion + cell.shapes(comp).insert(pya.Box((cont_size/2+cmp2cmp), -w/2, (cont_size/2+cmp2cmp+mvpsd_ov_cmp+cont2ply+cont_size+cmp2cont) + l, w/2)) + cell.shapes(comp).insert(pya.Box(-(cont_size/2+cmp2cmp), -w/2, -(cont_size/2+cmp2cmp+mvpsd_ov_cmp+cont2ply+cont_size+cmp2cont) - l, w/2)) + + cell.shapes(pplus).insert(pya.Box(-(cont_size/2+cmp2cmp+mvpsd_ov_cmp+cont2ply+cont_size+cmp2cont+np_enc_cmp) - l, -w/2 - np_enc_gate, + (cont_size/2+cmp2cmp+mvpsd_ov_cmp+cont2ply+cont_size+cmp2cont+np_enc_cmp) + l, w/2 + np_enc_gate)) + + # Inserting gates + cell.shapes(poly2).insert(pya.Box((cont_size/2+drain2ply), -w/2 - ply_ext_cmp, (cont_size/2+cmp2cmp+mvpsd_ov_cmp) + l, w/2 + mvpsd_ext_cmp+mvpsd2gr-ply2gr)) + cell.shapes(poly2).insert(pya.Box(-(cont_size/2+drain2ply), -w/2 - ply_ext_cmp, -(cont_size/2+cmp2cmp+mvpsd_ov_cmp) - l, w/2 + mvpsd_ext_cmp+mvpsd2gr-ply2gr)) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + + # Inserting shapes now into the *contact* cell + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Contact array count and postions + ny = int((w - (cont_size+2*cmp2cont))/(cont_size+cont2cont)) + 1 + dy = (w - ny * cont_size - (ny - 1) * cont2cont)/2 + ng = int(((l + mvpsd_ov_cmp + ply_fld) - (cont_size+2*cmp2cont))/(cont_size+cont2cont)) + 1 + dg = (l + mvpsd_ov_cmp + ply_fld - ng * cont_size - (ng - 1) * cont2cont)/2 + + # Inserting contact array and metals + # Gate contacts and metal + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((cont_size/2+drain2ply) + dg, w/2 + mvpsd_ext_cmp+mvpsd2gr-ply2gr-(metal_w+cont_size)/2)), + pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), ng, 1)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-(1.5*cont_size+drain2ply) - dg, w/2 + mvpsd_ext_cmp+mvpsd2gr-ply2gr-(metal_w+cont_size)/2)), + pya.Point.new(-(cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), ng, 1)) + cell.shapes(metal1).insert(pya.Box((cont_size/2+drain2ply), w/2 + mvpsd_ext_cmp+mvpsd2gr-ply2gr-metal_w, + (cont_size/2+cmp2cmp+mvpsd_ov_cmp) + l, w/2 + mvpsd_ext_cmp+mvpsd2gr-ply2gr)) + cell.shapes(metal1).insert(pya.Box(-(cont_size/2+drain2ply), w/2 + mvpsd_ext_cmp+mvpsd2gr-ply2gr-metal_w, + -(cont_size/2+cmp2cmp+mvpsd_ov_cmp) - l, w/2 + mvpsd_ext_cmp+mvpsd2gr-ply2gr)) + + # Drain contacts and metal + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-cont_size/2, -w/2 + dy)), + pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, ny)) + cell.shapes(metal1).insert(pya.Box(-metal_w/2, -w/2, metal_w/2, w/2)) + + # Source contacts and metals + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((cont_size/2+cmp2cmp+mvpsd_ov_cmp+cont2ply) + l, -w/2 + dy)), + pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, ny)) + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-(1.5*cont_size+cmp2cmp+mvpsd_ov_cmp+cont2ply) - l, -w/2 + dy)), + pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, ny)) + cell.shapes(metal1).insert(pya.Box((1.5*cont_size+cmp2cmp+mvpsd_ov_cmp+cont2ply+cmp2cont-metal_w) + l, -w/2, (1.5*cont_size+cmp2cmp+mvpsd_ov_cmp+cont2ply+cmp2cont) + l, w/2)) + cell.shapes(metal1).insert(pya.Box(-(1.5*cont_size+cmp2cmp+mvpsd_ov_cmp+cont2ply+cmp2cont-metal_w) - l, -w/2, -(1.5*cont_size+cmp2cmp+mvpsd_ov_cmp+cont2ply+cmp2cont) - l, w/2)) + + # Inserting Guard Ring diffusion + cell.shapes(comp).insert( + pya.Polygon( + [ + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size) - w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, (mvpsd_ext_cmp+mvpsd2gr) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size) - w/2), + ], + True, + ) + ) + + cell.shapes(nplus).insert( + pya.Polygon( + [ + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+pp_enc_cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pp_enc_cmp) - w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+pp_enc_cmp) - l, (mvpsd_ext_cmp+mvpsd2gr-pp_enc_cmp) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp-pp_enc_cmp) - l, (mvpsd_ext_cmp+mvpsd2gr-pp_enc_cmp) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp-pp_enc_cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr-pp_enc_cmp) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp-pp_enc_cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr-pp_enc_cmp) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp-pp_enc_cmp) + l, (mvpsd_ext_cmp+mvpsd2gr-pp_enc_cmp) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+pp_enc_cmp) - l, (mvpsd_ext_cmp+mvpsd2gr-pp_enc_cmp) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+pp_enc_cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pp_enc_cmp) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+pp_enc_cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pp_enc_cmp) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+pp_enc_cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pp_enc_cmp) - w/2), + ], + True, + ) + ) + + cell.shapes(metal1).insert( + pya.Polygon( + [ + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size) - w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr) + w/2), + pya.Point(-(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr) - w/2), + pya.Point((0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, (mvpsd_ext_cmp+mvpsd2gr) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr) + w/2), + pya.Point(-(2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size) + w/2), + pya.Point((2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size) - w/2), + ], + True, + ) + ) + + nygr = int((w + 2*(mvpsd_ext_cmp+mvpsd2gr+cmp2cont+cont_size)+cont2cont)/(cont_size+cont2cont)) + dygr = (w + 2*(mvpsd_ext_cmp+mvpsd2gr+cmp2cont+cont_size) - nygr * (cont_size+cont2cont)+ cont2cont)/2 + nxgr_h = int((2 * l + 2*(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+cmp2cont)- cont2cont)/(cont_size+cont2cont)) + dxgr_h = (2 * l + 2*(0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+cmp2cont) - nxgr_h * (cont_size+cont2cont) + cont2cont)/2 + + # Inserting Guard Ring contacts + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-(cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, + dygr - (mvpsd_ext_cmp+mvpsd2gr+cmp2cont+cont_size) - w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, nygr)) + + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(dxgr_h - (0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+cmp2cont) - l, + -(mvpsd_ext_cmp+mvpsd2gr+cmp2cont+cont_size) - w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), nxgr_h, 1)) + + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((cmp2cont+0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, + dygr - (mvpsd_ext_cmp+mvpsd2gr+cmp2cont+cont_size) - w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, nygr)) + + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(dxgr_h - (0.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+cmp2cont) - l, + (mvpsd_ext_cmp+mvpsd2gr+cmp2cont) + w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), nxgr_h, 1)) + + # Inserting DNWELL Guard Ring + if dgr_en: + # Inserting DNWELL Guard Ring diffusion + cell.shapes(comp).insert( + pya.Polygon( + [ + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) - w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) - w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) - w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) - w/2), + ], + True, + ) + ) + + cell.shapes(pplus).insert( + pya.Polygon( + [ + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+np_enc_cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp+np_enc_cmp) - w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+np_enc_cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp-np_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp-np_enc_cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp-np_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp-np_enc_cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp-np_enc_cmp) - w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp-np_enc_cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp-np_enc_cmp) - w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp-np_enc_cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp-np_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+np_enc_cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp-np_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+np_enc_cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp+np_enc_cmp) + w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+np_enc_cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp+np_enc_cmp) + w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp+np_enc_cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp+np_enc_cmp) - w/2), + ], + True, + ) + ) + + # Inserting DNWELL Guard Ring metal + cell.shapes(metal1).insert( + pya.Polygon( + [ + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) - w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) - w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) - w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+2*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point(-(pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, (mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, (mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) + w/2), + pya.Point((pcmp_gr2dnw+dnw_enc_cmp+4*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, -(mvpsd_ext_cmp+mvpsd2gr+4*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) - w/2), + ], + True, + ) + ) + + # Inserting DNWELL guard ring contacts + nygr = int((w + 2*(mvpsd_ext_cmp+mvpsd2gr+3*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp)+cont2cont)/(cont_size+cont2cont)) + dygr = (w + 2*(mvpsd_ext_cmp+mvpsd2gr+3*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) - nygr * (cont_size+cont2cont) + cont2cont)/2 + nxgr_h = int((2 * l + 2*(pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+2*cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp)- cont2cont)/(cont_size+cont2cont)) + dxgr_h = (2 * l + 2*(pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+2*cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - nxgr_h * (cont_size+cont2cont) + cont2cont)/2 + + # Inserting DNWELL Guard Ring contacts + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(-(pcmp_gr2dnw+dnw_enc_cmp+3*cmp2cont+2.5*cont_size+cmp2gr+cont_size+cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, + dygr - (mvpsd_ext_cmp+mvpsd2gr+3*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) - w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, nygr)) + + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(dxgr_h - (pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+2*cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, + -(mvpsd_ext_cmp+mvpsd2gr+3*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) - w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, -(cont_size+cont2cont)), nxgr_h, 1)) + + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new((pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+2*cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) + l, + dygr - (mvpsd_ext_cmp+mvpsd2gr+3*cmp2cont+2*cont_size+pcmp_gr2dnw+dnw_enc_cmp) - w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), 1, nygr)) + + cell.insert(pya.CellInstArray.new(cont_cell_index, pya.Trans.new(pya.Point.new(dxgr_h - (pcmp_gr2dnw+dnw_enc_cmp+2*cmp2cont+1.5*cont_size+cmp2gr+cont_size+2*cmp2cont+cont2ply+mvpsd_ov_cmp+cmp2cmp) - l, + mvpsd_ext_cmp+mvpsd2gr+3*cmp2cont+cont_size+pcmp_gr2dnw+dnw_enc_cmp + w/2)), pya.Point.new((cont_size+cont2cont), 0), pya.Point.new(0, (cont_size+cont2cont)), nxgr_h, 1)) + + cell.flatten(True) + return cell diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_moscap.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_moscap.py new file mode 100644 index 000000000..294b691e8 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_moscap.py @@ -0,0 +1,691 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +## MOS capacitor Pcells Generators for Klayout of GF180MCU +######################################################################################################################## + +import pya + +def number_spc_contacts(box_width, min_enc, cont_spacing, cont_width): + """ Calculate number of cantacts in a given dimensions and the free space for symmetry. + By getting the min enclosure,the width of the box,the width ans spacing of the contacts. + Parameters + ---------- + box_width (double) : length you place the via or cont. in + min_enc (double) : spacing between the edge of the box and the first contact. + cont_spacing (double) : spacing between different contacts + cont_width (double) : contacts in the same direction + """ + spc_cont = box_width - 2 * min_enc + num_cont = int((spc_cont + cont_spacing) / (cont_width + cont_spacing)) + free_spc = box_width - (num_cont * cont_width + + (num_cont - 1) * cont_spacing) + return num_cont, free_spc + +def draw_nmoscap(layout, l, w ,volt, deepnwell, pcmpgr): + ''' + Usage:- + used to draw NMOS capacitor (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + lvpwell = layout.layer(204, 0 ) + comp = layout.layer(22 , 0 ) + poly = layout.layer(30 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + contact = layout.layer(33 , 0 ) + lvpwell = layout.layer(204 , 0) + metal1 = layout.layer(34 , 0 ) + mos_cap_mk = layout.layer(166, 5 ) + dualgate = layout.layer(55 , 0 ) + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + cmp_w = w * dbu_PERCISION + cmp_l = l * dbu_PERCISION + poly_ext = 0.46 * dbu_PERCISION + implant_cmp_enc = 0.16 * dbu_PERCISION + cmp_poly_enc = 0.44 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + metal_cmp_ext_x = 0.65 * dbu_PERCISION + metal_cmp_ext_y = 0.76 * dbu_PERCISION + met_width = 1 * dbu_PERCISION + poly_met_enc_x = 0.21 * dbu_PERCISION + poly_met_enc_y = 0.01 * dbu_PERCISION + met_con_min = 0.34 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + cmp_cont_poly_spc = 0.17 * dbu_PERCISION + dual_gate_cmp_enc_x = 0.96 * dbu_PERCISION + dual_gate_cmp_enc_y = 1.36 * dbu_PERCISION + pcmp2ncmp_spc = 0.36 * dbu_PERCISION + ply2gr_spc = 0.3 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + lvpwell_enc_pcmp = 0.12 * dbu_PERCISION + dnwell_enc_lvpwell = 2.5 * dbu_PERCISION + dg_enc_dnwell = 0.5 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + + if volt == "5/6V": + lvpwell_enc_pcmp = 0.16 * dbu_PERCISION + + # Inserting nmoscap cell + cell_index = layout.add_cell("nmoscap") + nmoscap_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting diffusion + nmoscap_cell.shapes(comp).insert(pya.Box(0, 0, cmp_w, cmp_l)) + nmoscap_cell.shapes(nplus).insert(pya.Box(-implant_cmp_enc, -poly_ext, cmp_w+implant_cmp_enc, cmp_l+poly_ext)) + + # Inserting poly + nmoscap_cell.shapes(poly).insert(pya.Box(cmp_poly_enc, -poly_ext, cmp_w-cmp_poly_enc, cmp_l+poly_ext)) + + # Inserting left metal + nmoscap_cell.shapes(metal1).insert(pya.Box(-metal_cmp_ext_x, -metal_cmp_ext_y, -metal_cmp_ext_x+met_width, cmp_l)) + + # Inserting right metal + nmoscap_cell.shapes(metal1).insert(pya.Box(cmp_w+metal_cmp_ext_x-met_width, -metal_cmp_ext_y, cmp_w+metal_cmp_ext_x, cmp_l)) + + # Inserting poly metal + nmoscap_cell.shapes(metal1).insert(pya.Box(cmp_poly_enc+poly_met_enc_x, -poly_ext+poly_met_enc_y, cmp_w-cmp_poly_enc-poly_met_enc_x , cmp_l+poly_ext-poly_met_enc_y)) + + # Inserting left contacts + num_left_con_1, left_con_free_spc_1 = number_spc_contacts(met_con_min, met_cont_enc, cont_min_spc, cont_size) + num_left_con_2, left_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_met_cont_enc_diff+left_con_free_spc_1 / 2, left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_left_con_1, num_left_con_2) + nmoscap_cell.insert(left_con_arr) + + # Inserting right contacts + num_right_con_1, right_con_free_spc_1 = number_spc_contacts(met_con_min, met_cont_enc, cont_min_spc, cont_size) + num_right_con_2, right_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_w-cmp_met_cont_enc_diff-met_con_min+right_con_free_spc_1 / 2, right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_right_con_1, num_right_con_2) + nmoscap_cell.insert(right_con_arr) + + # Inserting top contacts + num_top_con_1, top_con_free_spc_1 = number_spc_contacts(cmp_w-2*cmp_poly_enc-2*poly_met_enc_x, comp_cont_enc, cont_min_spc, cont_size) + num_top_con_2, top_con_free_spc_2 = number_spc_contacts(poly_ext-poly_met_enc_y, comp_cont_enc, cont_min_spc, cont_size) + top_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_poly_enc+poly_met_enc_x+top_con_free_spc_1 / 2, cmp_l+top_con_free_spc_2/2+(cmp_cont_poly_spc-top_con_free_spc_2/2))), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_top_con_1, num_top_con_2) + nmoscap_cell.insert(top_con_arr) + + # Inserting bottom contacts + num_bot_con_1, bot_con_free_spc_1 = number_spc_contacts(cmp_w-2*cmp_poly_enc-2*poly_met_enc_x, comp_cont_enc, cont_min_spc, cont_size) + num_bot_con_2, bot_con_free_spc_2 = number_spc_contacts(poly_ext-poly_met_enc_y, comp_cont_enc, cont_min_spc, cont_size) + bot_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_poly_enc+poly_met_enc_x+bot_con_free_spc_1 / 2, -poly_ext+poly_met_enc_y+bot_con_free_spc_2/2-(cmp_cont_poly_spc-bot_con_free_spc_2/2))), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_bot_con_1, num_bot_con_2) + nmoscap_cell.insert(bot_con_arr) + + # Inserting marker + nmoscap_cell.shapes(mos_cap_mk).insert(pya.Box(0, 0, cmp_w, cmp_l)) + + # Inserting marker + if deepnwell == True: + # Inserting PCOMP Guard Ring + cmp_inner = pya.Box(-pcmp2ncmp_spc, -ply2gr_spc-poly_ext, cmp_w+pcmp2ncmp_spc, cmp_l+poly_ext+ply2gr_spc) + cmp_outer = pya.Box(-pcmp2ncmp_spc-gr_w, -ply2gr_spc-poly_ext-gr_w, cmp_w+pcmp2ncmp_spc+gr_w, cmp_l+poly_ext+gr_w+ply2gr_spc) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + nmoscap_cell.shapes(comp).insert(cmp_gr) + nmoscap_cell.shapes(metal1).insert(cmp_gr) + + pp_inner = pya.Box(-pcmp2ncmp_spc+implant_cmp_enc, -ply2gr_spc-poly_ext+implant_cmp_enc, cmp_w+pcmp2ncmp_spc-implant_cmp_enc, cmp_l+poly_ext+ply2gr_spc-implant_cmp_enc) + pp_outer = pya.Box(-pcmp2ncmp_spc-gr_w-implant_cmp_enc, -ply2gr_spc-poly_ext-gr_w-implant_cmp_enc, cmp_w+pcmp2ncmp_spc+gr_w+implant_cmp_enc, cmp_l+poly_ext+gr_w+ply2gr_spc+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + nmoscap_cell.shapes(pplus).insert(pp_gr) + + # Inserting PCOMP Guard Ring contacts + num_y_con, y_con_free_spc = number_spc_contacts(2*(gr_w+ply2gr_spc+poly_ext)+cmp_l, comp_cont_enc, cont_min_spc, cont_size) + num_x_con, x_con_free_spc = number_spc_contacts(cmp_w+2*(comp_cont_enc+pcmp2ncmp_spc-cont_min_spc), comp_cont_enc, cont_min_spc, cont_size) + + left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-pcmp2ncmp_spc-comp_cont_enc-cont_size, -ply2gr_spc-poly_ext-gr_w+y_con_free_spc/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + 1, num_y_con) + nmoscap_cell.insert(left_con_arr) + + bot_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-pcmp2ncmp_spc+cont_min_spc-comp_cont_enc+x_con_free_spc/2, -ply2gr_spc-poly_ext-comp_cont_enc-cont_size)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_x_con, 1) + nmoscap_cell.insert(bot_con_arr) + + right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_w+pcmp2ncmp_spc+comp_cont_enc, -ply2gr_spc-poly_ext-gr_w+y_con_free_spc/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + 1, num_y_con) + nmoscap_cell.insert(right_con_arr) + + top_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-pcmp2ncmp_spc+cont_min_spc-comp_cont_enc+x_con_free_spc/2, cmp_l+ply2gr_spc+poly_ext+comp_cont_enc)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_x_con, 1) + nmoscap_cell.insert(top_con_arr) + + # Inserting Double Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-pcmp2ncmp_spc-gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw, -ply2gr_spc-poly_ext-gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw, cmp_w+pcmp2ncmp_spc+gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell+pcmp_gr2dnw, cmp_l+poly_ext+gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell+ply2gr_spc+pcmp_gr2dnw) + cmp_outer = pya.Box(-pcmp2ncmp_spc-2*gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw, -ply2gr_spc-poly_ext-2*gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw, cmp_w+pcmp2ncmp_spc+2*gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell+pcmp_gr2dnw, cmp_l+poly_ext+2*gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell+ply2gr_spc+pcmp_gr2dnw) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + nmoscap_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-pcmp2ncmp_spc-gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw+implant_cmp_enc, -ply2gr_spc-poly_ext-gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw+implant_cmp_enc, cmp_w+pcmp2ncmp_spc+gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell+pcmp_gr2dnw-implant_cmp_enc, cmp_l+poly_ext+gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell+ply2gr_spc+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-pcmp2ncmp_spc-2*gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw-implant_cmp_enc, -ply2gr_spc-poly_ext-2*gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw-implant_cmp_enc, cmp_w+pcmp2ncmp_spc+2*gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell+pcmp_gr2dnw+implant_cmp_enc, cmp_l+poly_ext+2*gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell+ply2gr_spc+pcmp_gr2dnw+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + nmoscap_cell.shapes(pplus).insert(pp_gr) + + # Inserting lvpwell + nmoscap_cell.shapes(lvpwell).insert(pya.Box(-pcmp2ncmp_spc-gr_w-lvpwell_enc_pcmp, -ply2gr_spc-poly_ext-gr_w-lvpwell_enc_pcmp, cmp_w+pcmp2ncmp_spc+gr_w+lvpwell_enc_pcmp, cmp_l+poly_ext+gr_w+lvpwell_enc_pcmp+ply2gr_spc)) + + nmoscap_cell.shapes(dnwell).insert(pya.Box(-pcmp2ncmp_spc-gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell, -ply2gr_spc-poly_ext-gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell, cmp_w+pcmp2ncmp_spc+gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell, cmp_l+poly_ext+gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell+ply2gr_spc)) + + else: + # Inserting lvpwell + nmoscap_cell.shapes(lvpwell).insert(pya.Box(0, 0, cmp_w, cmp_l)) + + # Inserting bottom metal + nmoscap_cell.shapes(metal1).insert(pya.Box(-metal_cmp_ext_x, -metal_cmp_ext_y-met_width, cmp_w+metal_cmp_ext_x, -metal_cmp_ext_y)) + + + if volt == "5/6V": + # Inserting dualgate + if deepnwell == True: + nmoscap_cell.shapes(dualgate).insert(pya.Box(-pcmp2ncmp_spc-gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell-dg_enc_dnwell, -ply2gr_spc-poly_ext-gr_w-lvpwell_enc_pcmp-dnwell_enc_lvpwell-dg_enc_dnwell, cmp_w+pcmp2ncmp_spc+gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell+dg_enc_dnwell, cmp_l+poly_ext+pcmp2ncmp_spc+gr_w+lvpwell_enc_pcmp+dnwell_enc_lvpwell+dg_enc_dnwell)) + else: + nmoscap_cell.shapes(dualgate).insert(pya.Box(-dual_gate_cmp_enc_x, -dual_gate_cmp_enc_y, cmp_w+dual_gate_cmp_enc_x, cmp_l+dual_gate_cmp_enc_y)) + + + nmoscap_cell.flatten(True) + return nmoscap_cell + +def draw_pmoscap(layout, l, w , volt, deepnwell, pcmpgr): + ''' + Usage:- + used to draw PMOS capacitor (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + poly = layout.layer(30 , 0 ) + pplus = layout.layer(31 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + nwell = layout.layer(21 , 0 ) + metal1 = layout.layer(34 , 0 ) + mos_cap_mk = layout.layer(166, 5 ) + dualgate = layout.layer(55 , 0 ) + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + cmp_w = w * dbu_PERCISION + cmp_l = l * dbu_PERCISION + poly_ext = 0.46 * dbu_PERCISION + implant_cmp_enc = 0.16 * dbu_PERCISION + cmp_poly_enc = 0.44 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + metal_cmp_ext_x = 0.65 * dbu_PERCISION + met_width = 1 * dbu_PERCISION + poly_met_enc_x = 0.19 * dbu_PERCISION + poly_met_enc_y = 0.01 * dbu_PERCISION + met_con_min = 0.34 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + gr_width = 0.36 * dbu_PERCISION + ncmp_pcmp_spc = 0.36 * dbu_PERCISION + poly_ncmp_spc = 0.3 * dbu_PERCISION + nwell_cmp_enc = 0.16 * dbu_PERCISION + cmp_met_spc = 0.11 * dbu_PERCISION + cont_spc_gr = 0.11 * dbu_PERCISION + dual_gate_cmp_enc_x = 0.96 * dbu_PERCISION + dual_gate_cmp_enc_y = 1.36 * dbu_PERCISION + dnwell_enc_ncmp = 0.62 * dbu_PERCISION + dg_enc_dnwell = 0.5 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + + if volt == "5/6V": + dnwell_enc_ncmp = 0.66 * dbu_PERCISION + + # Inserting pmoscap cell + cell_index = layout.add_cell("pmoscap") + pmoscap_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting diffusion + pmoscap_cell.shapes(comp).insert(pya.Box(0, 0, cmp_w, cmp_l)) + pmoscap_cell.shapes(pplus).insert(pya.Box(-implant_cmp_enc, -poly_ext, cmp_w+implant_cmp_enc, cmp_l+poly_ext)) + + # Inserting poly + pmoscap_cell.shapes(poly).insert(pya.Box(cmp_poly_enc, -poly_ext, cmp_w-cmp_poly_enc, cmp_l+poly_ext)) + + # Inserting left cmp metal + pmoscap_cell.shapes(metal1).insert(pya.Box(-ncmp_pcmp_spc-gr_width, 0 , -metal_cmp_ext_x+met_width, cmp_l)) + + # Inserting right cmp metal + pmoscap_cell.shapes(metal1).insert(pya.Box(cmp_w+metal_cmp_ext_x-met_width, 0, cmp_w+ncmp_pcmp_spc+gr_width, cmp_l)) + + # Inserting top cmp metal + pmoscap_cell.shapes(metal1).insert(pya.Box(cmp_poly_enc+poly_met_enc_x, cmp_l+cmp_met_spc , cmp_w-cmp_poly_enc-poly_met_enc_x , cmp_l+poly_ext-poly_met_enc_y)) + + # Inserting bottom cmp metal + pmoscap_cell.shapes(metal1).insert(pya.Box(cmp_poly_enc+poly_met_enc_x, -poly_ext+poly_met_enc_y, cmp_w-cmp_poly_enc-poly_met_enc_x , -cmp_met_spc)) + + # Inserting left cmp contacts + num_left_con_1, left_con_free_spc_1 = number_spc_contacts(met_con_min, met_cont_enc, cont_min_spc, cont_size) + num_left_con_2, left_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_met_cont_enc_diff+left_con_free_spc_1 / 2, left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_left_con_1, num_left_con_2) + pmoscap_cell.insert(left_con_arr) + + # Inserting right cmp contacts + num_right_con_1, right_con_free_spc_1 = number_spc_contacts(met_con_min, met_cont_enc, cont_min_spc, cont_size) + num_right_con_2, right_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_w-cmp_met_cont_enc_diff-met_con_min+right_con_free_spc_1 / 2, right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_right_con_1, num_right_con_2) + pmoscap_cell.insert(right_con_arr) + + # Inserting top cmp contacts + num_top_con_1, top_con_free_spc_1 = number_spc_contacts(cmp_w-2*cmp_poly_enc-2*poly_met_enc_x, met_cont_enc, cont_min_spc, cont_size) + num_top_con_2, top_con_free_spc_2 = number_spc_contacts(met_con_min, met_cont_enc, cont_min_spc, cont_size) + top_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_poly_enc+poly_met_enc_x+top_con_free_spc_1 / 2, cmp_l+cmp_met_spc+top_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_top_con_1, num_top_con_2) + pmoscap_cell.insert(top_con_arr) + + # Inserting bottom cmp contacts + num_bot_con_1, bot_con_free_spc_1 = number_spc_contacts(cmp_w-2*cmp_poly_enc-2*poly_met_enc_x, met_cont_enc, cont_min_spc, cont_size) + num_bot_con_2, bot_con_free_spc_2 = number_spc_contacts(met_con_min, met_cont_enc, cont_min_spc, cont_size) + bot_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_poly_enc+poly_met_enc_x+bot_con_free_spc_1 / 2, -poly_ext+poly_met_enc_y+bot_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_bot_con_1, num_bot_con_2) + pmoscap_cell.insert(bot_con_arr) + + # Inserting left GR diff + pmoscap_cell.shapes(comp).insert(pya.Box(-ncmp_pcmp_spc-gr_width, -poly_ext-poly_ncmp_spc , -ncmp_pcmp_spc , cmp_l+poly_ext+poly_ncmp_spc)) + pmoscap_cell.shapes(nplus).insert(pya.Box(-ncmp_pcmp_spc-gr_width-implant_cmp_enc, -poly_ext-poly_ncmp_spc+implant_cmp_enc , -ncmp_pcmp_spc+implant_cmp_enc , cmp_l+poly_ext+poly_ncmp_spc-implant_cmp_enc)) + # Inserting right GR diff + pmoscap_cell.shapes(comp).insert(pya.Box(cmp_w+ncmp_pcmp_spc, -poly_ext-poly_ncmp_spc , cmp_w+ncmp_pcmp_spc+gr_width , cmp_l+poly_ext+poly_ncmp_spc)) + pmoscap_cell.shapes(nplus).insert(pya.Box(cmp_w+ncmp_pcmp_spc-implant_cmp_enc, -poly_ext-poly_ncmp_spc+implant_cmp_enc , cmp_w+ncmp_pcmp_spc+gr_width+implant_cmp_enc , cmp_l+poly_ext+poly_ncmp_spc-implant_cmp_enc)) + # Inserting top GR diff + pmoscap_cell.shapes(comp).insert(pya.Box(-ncmp_pcmp_spc-gr_width, cmp_l+poly_ext+poly_ncmp_spc , cmp_w+ncmp_pcmp_spc+gr_width , cmp_l+poly_ext+poly_ncmp_spc+gr_width)) + pmoscap_cell.shapes(nplus).insert(pya.Box(-ncmp_pcmp_spc-gr_width-implant_cmp_enc, cmp_l+poly_ext+poly_ncmp_spc-implant_cmp_enc , cmp_w+ncmp_pcmp_spc+gr_width+implant_cmp_enc , cmp_l+poly_ext+poly_ncmp_spc+gr_width+implant_cmp_enc)) + # Inserting bottom GR diff + pmoscap_cell.shapes(comp).insert(pya.Box(-ncmp_pcmp_spc-gr_width, -poly_ext-poly_ncmp_spc-gr_width , cmp_w+ncmp_pcmp_spc+gr_width , -poly_ext-poly_ncmp_spc)) + pmoscap_cell.shapes(nplus).insert(pya.Box(-ncmp_pcmp_spc-gr_width-implant_cmp_enc, -poly_ext-poly_ncmp_spc-gr_width-implant_cmp_enc , cmp_w+ncmp_pcmp_spc+gr_width+implant_cmp_enc , -poly_ext-poly_ncmp_spc+implant_cmp_enc)) + + # Inserting left GR metal + pmoscap_cell.shapes(metal1).insert(pya.Box(-ncmp_pcmp_spc-gr_width, -poly_ext-poly_ncmp_spc , -ncmp_pcmp_spc , cmp_l+poly_ext+poly_ncmp_spc)) + # Inserting right GR metal + pmoscap_cell.shapes(metal1).insert(pya.Box(cmp_w+ncmp_pcmp_spc, -poly_ext-poly_ncmp_spc , cmp_w+ncmp_pcmp_spc+gr_width , cmp_l+poly_ext+poly_ncmp_spc)) + # Inserting top GR metal + pmoscap_cell.shapes(metal1).insert(pya.Box(-ncmp_pcmp_spc-gr_width, cmp_l+poly_ext+poly_ncmp_spc , cmp_w+ncmp_pcmp_spc+gr_width , cmp_l+poly_ext+poly_ncmp_spc+gr_width)) + # Inserting bottom GR metal + pmoscap_cell.shapes(metal1).insert(pya.Box(-ncmp_pcmp_spc-gr_width, -poly_ext-poly_ncmp_spc-gr_width , cmp_w+ncmp_pcmp_spc+gr_width , -poly_ext-poly_ncmp_spc)) + + # Inserting left GR cont + num_gr_left_con_1, gr_left_con_free_spc_1 = number_spc_contacts(gr_width, comp_cont_enc, cont_min_spc, cont_size) + num_gr_left_con_2, gr_left_con_free_spc_2 = number_spc_contacts(cmp_l+2*poly_ext+2*poly_ncmp_spc-2*cont_spc_gr, comp_cont_enc, cont_min_spc, cont_size) + gr_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-ncmp_pcmp_spc-gr_width+gr_left_con_free_spc_1 / 2, cont_spc_gr-poly_ext-poly_ncmp_spc+gr_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_left_con_1, num_gr_left_con_2) + pmoscap_cell.insert(gr_left_con_arr) + + # Inserting right GR cont + num_gr_right_con_1, gr_right_con_free_spc_1 = number_spc_contacts(gr_width, comp_cont_enc, cont_min_spc, cont_size) + num_gr_right_con_2, gr_right_con_free_spc_2 = number_spc_contacts(cmp_l+2*poly_ext+2*poly_ncmp_spc-2*cont_spc_gr, comp_cont_enc, cont_min_spc, cont_size) + gr_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_w+ncmp_pcmp_spc+gr_right_con_free_spc_1 / 2, cont_spc_gr-poly_ext-poly_ncmp_spc+gr_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_right_con_1, num_gr_right_con_2) + pmoscap_cell.insert(gr_right_con_arr) + + # Inserting top GR cont + num_gr_top_con_1, gr_top_con_free_spc_1 = number_spc_contacts(cmp_w+2*ncmp_pcmp_spc+2*gr_width, comp_cont_enc, cont_min_spc, cont_size) + num_gr_top_con_2, gr_top_con_free_spc_2 = number_spc_contacts(gr_width, comp_cont_enc, cont_min_spc, cont_size) + gr_top_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-ncmp_pcmp_spc-gr_width+comp_cont_enc, cmp_l+poly_ext+poly_ncmp_spc +gr_top_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_top_con_1, num_gr_top_con_2) + pmoscap_cell.insert(gr_top_con_arr) + + # Inserting bottom GR cont + num_gr_top_con_1, gr_top_con_free_spc_1 = number_spc_contacts(cmp_w+2*ncmp_pcmp_spc+2*gr_width, comp_cont_enc, cont_min_spc, cont_size) + num_gr_top_con_2, gr_top_con_free_spc_2 = number_spc_contacts(gr_width, comp_cont_enc, cont_min_spc, cont_size) + gr_top_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-ncmp_pcmp_spc-gr_width+comp_cont_enc, -poly_ext-poly_ncmp_spc-gr_width +gr_top_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_gr_top_con_1, num_gr_top_con_2) + pmoscap_cell.insert(gr_top_con_arr) + + # Inserting marker + pmoscap_cell.shapes(mos_cap_mk).insert(pya.Box(0, 0, cmp_w, cmp_l)) + + # Inserting marker + if deepnwell == True: + # Inserting dnwell + pmoscap_cell.shapes(dnwell).insert(pya.Box(-ncmp_pcmp_spc-gr_width-dnwell_enc_ncmp, -poly_ext-poly_ncmp_spc-gr_width-dnwell_enc_ncmp, cmp_w+ncmp_pcmp_spc+gr_width+dnwell_enc_ncmp , cmp_l+poly_ext+poly_ncmp_spc+gr_width+dnwell_enc_ncmp)) + + # Inserting Double Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-ncmp_pcmp_spc-gr_width-dnwell_enc_ncmp-pcmp_gr2dnw, -poly_ext-poly_ncmp_spc-gr_width-dnwell_enc_ncmp-pcmp_gr2dnw, cmp_w+ncmp_pcmp_spc+gr_width+dnwell_enc_ncmp+pcmp_gr2dnw , cmp_l+poly_ext+poly_ncmp_spc+gr_width+dnwell_enc_ncmp+pcmp_gr2dnw) + cmp_outer = pya.Box(-ncmp_pcmp_spc-2*gr_width-dnwell_enc_ncmp-pcmp_gr2dnw, -poly_ext-poly_ncmp_spc-2*gr_width-dnwell_enc_ncmp-pcmp_gr2dnw, cmp_w+ncmp_pcmp_spc+2*gr_width+dnwell_enc_ncmp+pcmp_gr2dnw , cmp_l+poly_ext+poly_ncmp_spc+2*gr_width+dnwell_enc_ncmp+pcmp_gr2dnw) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + pmoscap_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-ncmp_pcmp_spc-gr_width-dnwell_enc_ncmp-pcmp_gr2dnw+implant_cmp_enc, -poly_ext-poly_ncmp_spc-gr_width-dnwell_enc_ncmp-pcmp_gr2dnw+implant_cmp_enc, cmp_w+ncmp_pcmp_spc+gr_width+dnwell_enc_ncmp+pcmp_gr2dnw-implant_cmp_enc , cmp_l+poly_ext+poly_ncmp_spc+gr_width+dnwell_enc_ncmp+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-ncmp_pcmp_spc-2*gr_width-dnwell_enc_ncmp-pcmp_gr2dnw-implant_cmp_enc, -poly_ext-poly_ncmp_spc-2*gr_width-dnwell_enc_ncmp-pcmp_gr2dnw-implant_cmp_enc, cmp_w+ncmp_pcmp_spc+2*gr_width+dnwell_enc_ncmp+pcmp_gr2dnw+implant_cmp_enc , cmp_l+poly_ext+poly_ncmp_spc+2*gr_width+dnwell_enc_ncmp+pcmp_gr2dnw+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + pmoscap_cell.shapes(pplus).insert(pp_gr) + + else: + # Inserting nwell + pmoscap_cell.shapes(nwell).insert(pya.Box(-ncmp_pcmp_spc-gr_width-nwell_cmp_enc, -poly_ext-poly_ncmp_spc-gr_width-nwell_cmp_enc, cmp_w+ncmp_pcmp_spc+gr_width+nwell_cmp_enc , cmp_l+poly_ext+poly_ncmp_spc+gr_width+nwell_cmp_enc)) + + if volt == "5/6V": + # Inserting dualgate + if deepnwell == True: + pmoscap_cell.shapes(dualgate).insert(pya.Box(-ncmp_pcmp_spc-gr_width-dnwell_enc_ncmp-dg_enc_dnwell, -poly_ext-poly_ncmp_spc-gr_width-dnwell_enc_ncmp-dg_enc_dnwell, cmp_w+ncmp_pcmp_spc+gr_width+dnwell_enc_ncmp+dg_enc_dnwell, cmp_l+poly_ext+poly_ncmp_spc+gr_width+dnwell_enc_ncmp+dg_enc_dnwell)) + else: + pmoscap_cell.shapes(dualgate).insert(pya.Box(-dual_gate_cmp_enc_x, -dual_gate_cmp_enc_y, cmp_w+dual_gate_cmp_enc_x, cmp_l+dual_gate_cmp_enc_y)) + + pmoscap_cell.flatten(True) + return pmoscap_cell + +def draw_nmoscap_b(layout, l, w , volt): + ''' + Usage:- + used to draw 3.3V NMOS capacitor (inside NWell) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + comp = layout.layer(22 , 0 ) + poly = layout.layer(30 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + nwell = layout.layer(21 , 0 ) + metal1 = layout.layer(34 , 0 ) + mos_cap_mk = layout.layer(166, 5 ) + dualgate = layout.layer(55 , 0 ) + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + cmp_w = w * dbu_PERCISION + cmp_l = l * dbu_PERCISION + poly_ext = 0.3 * dbu_PERCISION + implant_cmp_enc = 0.16 * dbu_PERCISION + cmp_poly_enc = 0.44 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + metal_cmp_ext_x = 0.59 * dbu_PERCISION + metal_cmp_ext_y = 2.2 * dbu_PERCISION + met_width = 1 * dbu_PERCISION + poly_met_enc_x = 0.17 * dbu_PERCISION + poly_met_enc_y = 0.01 * dbu_PERCISION + met_con_min = 0.34 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + cmp_cont_poly_spc = 0.17 * dbu_PERCISION + nwell_cmp_enc_x = 0.18 * dbu_PERCISION + nwell_cmp_enc_y = 1.38 * dbu_PERCISION + poly_extra_in = 0.27 * dbu_PERCISION + poly_extra_out = 0.9 * dbu_PERCISION + dualgate_cmp_enc_x = 0.24 * dbu_PERCISION + dualgate_cmp_enc_y = 1.6 * dbu_PERCISION + + # Inserting nmoscap cell + cell_index = layout.add_cell("nmoscap_b") + nmoscap_b_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting diffusion + nmoscap_b_cell.shapes(comp).insert(pya.Box(0, 0, cmp_w, cmp_l)) + nmoscap_b_cell.shapes(nplus).insert(pya.Box(-nwell_cmp_enc_x, -nwell_cmp_enc_y, cmp_w+nwell_cmp_enc_x, cmp_l+nwell_cmp_enc_y)) + + # Inserting nwell + nmoscap_b_cell.shapes(nwell).insert(pya.Box(-nwell_cmp_enc_x, -nwell_cmp_enc_y, cmp_w+nwell_cmp_enc_x, cmp_l+nwell_cmp_enc_y)) + + # Inserting poly + nmoscap_b_cell.shapes(poly).insert(pya.Box(cmp_poly_enc, -poly_ext, cmp_w-cmp_poly_enc, cmp_l+poly_ext)) + + # Inserting extra poly + nmoscap_b_cell.shapes(poly).insert(pya.Box(cmp_poly_enc+poly_extra_in, cmp_l+poly_ext, cmp_w-cmp_poly_enc-poly_extra_in, cmp_l+poly_ext+poly_extra_out)) #top + nmoscap_b_cell.shapes(poly).insert(pya.Box(cmp_poly_enc+poly_extra_in, -poly_ext-poly_extra_out, cmp_w-cmp_poly_enc-poly_extra_in, -poly_ext)) #bot + + # Inserting left metal + nmoscap_b_cell.shapes(metal1).insert(pya.Box(-metal_cmp_ext_x, -metal_cmp_ext_y, -metal_cmp_ext_x+met_width, cmp_l)) + + # Inserting right metal + nmoscap_b_cell.shapes(metal1).insert(pya.Box(cmp_w+metal_cmp_ext_x-met_width, -metal_cmp_ext_y-met_width, cmp_w+metal_cmp_ext_x, cmp_l)) + + # Inserting bottom metal + nmoscap_b_cell.shapes(metal1).insert(pya.Box(-metal_cmp_ext_x, -metal_cmp_ext_y-met_width, cmp_w+metal_cmp_ext_x, -metal_cmp_ext_y)) + + # Inserting poly metal + nmoscap_b_cell.shapes(metal1).insert(pya.Box(cmp_poly_enc+poly_extra_in, -poly_ext-poly_extra_out, cmp_w-cmp_poly_enc-poly_extra_in, cmp_l+poly_ext+poly_extra_out)) + + # Inserting left cmp contacts + num_left_con_1, left_con_free_spc_1 = number_spc_contacts(met_con_min, comp_cont_enc, cont_min_spc, cont_size) + num_left_con_2, left_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_met_cont_enc_diff+left_con_free_spc_1 / 2, left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_left_con_1, num_left_con_2) + nmoscap_b_cell.insert(left_con_arr) + + # Inserting right cmp contacts + num_right_con_1, right_con_free_spc_1 = number_spc_contacts(met_con_min, comp_cont_enc, cont_min_spc, cont_size) + num_right_con_2, right_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_w-cmp_met_cont_enc_diff-met_con_min+right_con_free_spc_1 / 2, right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_right_con_1, num_right_con_2) + nmoscap_b_cell.insert(right_con_arr) + + # Inserting top poly contacts + num_top_con_1, top_con_free_spc_1 = number_spc_contacts(cmp_w-2*cmp_poly_enc-2*poly_extra_in, comp_cont_enc, cont_min_spc, cont_size) + num_top_con_2, top_con_free_spc_2 = number_spc_contacts(poly_extra_out, comp_cont_enc, cont_min_spc, cont_size) + top_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_poly_enc+poly_extra_in+top_con_free_spc_1 / 2, cmp_l+poly_ext+top_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_top_con_1, num_top_con_2) + nmoscap_b_cell.insert(top_con_arr) + + # Inserting bottom poly contacts + num_bot_con_1, bot_con_free_spc_1 = number_spc_contacts(cmp_w-2*cmp_poly_enc-2*poly_extra_in, comp_cont_enc, cont_min_spc, cont_size) + num_bot_con_2, bot_con_free_spc_2 = number_spc_contacts(poly_extra_out, comp_cont_enc, cont_min_spc, cont_size) + bot_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_poly_enc+poly_extra_in+bot_con_free_spc_1 / 2, -poly_ext-poly_extra_out+bot_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_bot_con_1, num_bot_con_2) + nmoscap_b_cell.insert(bot_con_arr) + + # Inserting marker + nmoscap_b_cell.shapes(mos_cap_mk).insert(pya.Box(0, 0, cmp_w, cmp_l)) + + if volt == "5/6V": + # Inserting dualgate + nmoscap_b_cell.shapes(dualgate).insert(pya.Box(-dualgate_cmp_enc_x, -dualgate_cmp_enc_y, cmp_w+dualgate_cmp_enc_x, cmp_l+dualgate_cmp_enc_y)) + + + + nmoscap_b_cell.flatten(True) + return nmoscap_b_cell + +def draw_pmoscap_b(layout, l, w , volt): + ''' + Usage:- + used to draw PMOS capacitor (inside Psub) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + comp = layout.layer(22 , 0 ) + poly = layout.layer(30 , 0 ) + pplus = layout.layer(31 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + mos_cap_mk = layout.layer(166, 5 ) + dualgate = layout.layer(55 , 0 ) + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + cmp_w = w * dbu_PERCISION + cmp_l = l * dbu_PERCISION + poly_ext = 0.3 * dbu_PERCISION + cmp_poly_enc = 0.44 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + metal_cmp_ext_x = 0.59 * dbu_PERCISION + metal_cmp_ext_y = 2.2 * dbu_PERCISION + met_width = 1 * dbu_PERCISION + met_con_min = 0.34 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + nwell_cmp_enc_x = 0.18 * dbu_PERCISION + nwell_cmp_enc_y = 1.38 * dbu_PERCISION + poly_extra_in = 0.27 * dbu_PERCISION + poly_extra_out = 0.9 * dbu_PERCISION + dualgate_cmp_enc_x = 0.24 * dbu_PERCISION + dualgate_cmp_enc_y = 1.6 * dbu_PERCISION + + # Inserting pmoscap cell + cell_index = layout.add_cell("pmoscap_b") + pmoscap_b_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting diffusion + pmoscap_b_cell.shapes(comp).insert(pya.Box(0, 0, cmp_w, cmp_l)) + pmoscap_b_cell.shapes(pplus).insert(pya.Box(-nwell_cmp_enc_x, -nwell_cmp_enc_y, cmp_w+nwell_cmp_enc_x, cmp_l+nwell_cmp_enc_y)) + + # Inserting poly + pmoscap_b_cell.shapes(poly).insert(pya.Box(cmp_poly_enc, -poly_ext, cmp_w-cmp_poly_enc, cmp_l+poly_ext)) + + # Inserting extra poly + pmoscap_b_cell.shapes(poly).insert(pya.Box(cmp_poly_enc+poly_extra_in, cmp_l+poly_ext, cmp_w-cmp_poly_enc-poly_extra_in, cmp_l+poly_ext+poly_extra_out)) #top + pmoscap_b_cell.shapes(poly).insert(pya.Box(cmp_poly_enc+poly_extra_in, -poly_ext-poly_extra_out, cmp_w-cmp_poly_enc-poly_extra_in, -poly_ext)) #bot + + # Inserting left metal + pmoscap_b_cell.shapes(metal1).insert(pya.Box(-metal_cmp_ext_x, -metal_cmp_ext_y, -metal_cmp_ext_x+met_width, cmp_l)) + + # Inserting right metal + pmoscap_b_cell.shapes(metal1).insert(pya.Box(cmp_w+metal_cmp_ext_x-met_width, -metal_cmp_ext_y-met_width, cmp_w+metal_cmp_ext_x, cmp_l)) + + # Inserting bottom metal + pmoscap_b_cell.shapes(metal1).insert(pya.Box(-metal_cmp_ext_x, -metal_cmp_ext_y-met_width, cmp_w+metal_cmp_ext_x, -metal_cmp_ext_y)) + + # Inserting poly metal + pmoscap_b_cell.shapes(metal1).insert(pya.Box(cmp_poly_enc+poly_extra_in, -poly_ext-poly_extra_out, cmp_w-cmp_poly_enc-poly_extra_in, cmp_l+poly_ext+poly_extra_out)) + + # Inserting left cmp contacts + num_left_con_1, left_con_free_spc_1 = number_spc_contacts(met_con_min, comp_cont_enc, cont_min_spc, cont_size) + num_left_con_2, left_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_met_cont_enc_diff+left_con_free_spc_1 / 2, left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_left_con_1, num_left_con_2) + pmoscap_b_cell.insert(left_con_arr) + + # Inserting right cmp contacts + num_right_con_1, right_con_free_spc_1 = number_spc_contacts(met_con_min, comp_cont_enc, cont_min_spc, cont_size) + num_right_con_2, right_con_free_spc_2 = number_spc_contacts(cmp_l, comp_cont_enc, cont_min_spc, cont_size) + right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_w-cmp_met_cont_enc_diff-met_con_min+right_con_free_spc_1 / 2, right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_right_con_1, num_right_con_2) + pmoscap_b_cell.insert(right_con_arr) + + # Inserting top poly contacts + num_top_con_1, top_con_free_spc_1 = number_spc_contacts(cmp_w-2*cmp_poly_enc-2*poly_extra_in, comp_cont_enc, cont_min_spc, cont_size) + num_top_con_2, top_con_free_spc_2 = number_spc_contacts(poly_extra_out, comp_cont_enc, cont_min_spc, cont_size) + top_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_poly_enc+poly_extra_in+top_con_free_spc_1 / 2, cmp_l+poly_ext+top_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_top_con_1, num_top_con_2) + pmoscap_b_cell.insert(top_con_arr) + + # Inserting bottom poly contacts + num_bot_con_1, bot_con_free_spc_1 = number_spc_contacts(cmp_w-2*cmp_poly_enc-2*poly_extra_in, comp_cont_enc, cont_min_spc, cont_size) + num_bot_con_2, bot_con_free_spc_2 = number_spc_contacts(poly_extra_out, comp_cont_enc, cont_min_spc, cont_size) + bot_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(cmp_poly_enc+poly_extra_in+bot_con_free_spc_1 / 2, -poly_ext-poly_extra_out+bot_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_bot_con_1, num_bot_con_2) + pmoscap_b_cell.insert(bot_con_arr) + + # Inserting marker + pmoscap_b_cell.shapes(mos_cap_mk).insert(pya.Box(0, 0, cmp_w, cmp_l)) + + if volt == "5/6V": + # Inserting dualgate + pmoscap_b_cell.shapes(dualgate).insert(pya.Box(-dualgate_cmp_enc_x, -dualgate_cmp_enc_y, cmp_w+dualgate_cmp_enc_x, cmp_l+dualgate_cmp_enc_y)) + + + pmoscap_b_cell.flatten(True) + return pmoscap_b_cell diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_res.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_res.py new file mode 100644 index 000000000..0064ca145 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/draw_res.py @@ -0,0 +1,1468 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +## Resistor Pcells Generators for Klayout of GF180MCU +######################################################################################################################## + +import pya + +tol = 1.05 + +def number_spc_contacts(box_width, min_enc, cont_spacing, cont_width): + """ Calculate number of cantacts in a given dimensions and the free space for symmetry. + By getting the min enclosure,the width of the box,the width ans spacing of the contacts. + Parameters + ---------- + box_width (double) : length you place the via or cont. in + min_enc (double) : spacing between the edge of the box and the first contact. + cont_spacing (double) : spacing between different contacts + cont_width (double) : contacts in the same direction + """ + spc_cont = box_width - 2 * min_enc + num_cont = int((spc_cont + cont_spacing) / (cont_width + cont_spacing)) + free_spc = box_width - (num_cont * cont_width + + (num_cont - 1) * cont_spacing) + return num_cont, free_spc + +def draw_metal_res(layout, l, w , res_type): + ''' + Usage:- + used to draw 2-terminal Metal resistor by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + metal1 = layout.layer(34 , 0 ) + metal2 = layout.layer(36 , 0 ) + metal3 = layout.layer(42 , 0 ) + metaltop = layout.layer(53 , 0 ) + + metal1_res = layout.layer(110, 11 ) + metal2_res = layout.layer(110, 12 ) + metal3_res = layout.layer(110, 13 ) + metaltop_res = layout.layer(110, 16 ) + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + metal_res_w = w * dbu_PERCISION + metal_res_l = l * dbu_PERCISION + + if res_type == "rm1": + metal_res = metal1_res + metal = metal1 + metal_res_enc = 0.23 * dbu_PERCISION + + elif res_type == "rm2": + metal_res = metal2_res + metal = metal2 + metal_res_enc = 0.28 * dbu_PERCISION + + elif res_type == "rm3": + metal_res = metal3_res + metal = metal3 + metal_res_enc = 0.28 * dbu_PERCISION + + elif res_type == "tm6k": + metal_res = metaltop_res + metal = metaltop + metal_res_enc = 0.36 * dbu_PERCISION + + elif res_type == "tm9k" or res_type == "tm11k": + metal_res = metaltop_res + metal = metaltop + metal_res_enc = 0.44 * dbu_PERCISION + + elif res_type == "tm30k": + metal_res = metaltop_res + metal = metaltop + metal_res_enc = 1.8 * dbu_PERCISION + + else: + metal_res = metal1_res + metal = metal1 + metal_res_enc = 0.23 * dbu_PERCISION + + + # Inserting rm cell + cell_index = layout.add_cell("rm") + rm_cell = layout.cell(cell_index) + + # Inserting metal_res + rm_cell.shapes(metal_res).insert(pya.Box(0, 0, metal_res_w, metal_res_l)) + + # Inserting metal + rm_cell.shapes(metal).insert(pya.Box(-metal_res_enc, 0 , metal_res_w+metal_res_enc, metal_res_l)) + + rm_cell.flatten(True) + return rm_cell + +def draw_nplus_s_res(layout, l, w , sub, deepnwell, pcmpgr): + ''' + Usage:- + used to draw 3-terminal salicided n+ diffusion resistor (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + lvpwell = layout.layer(204, 0 ) + pplus = layout.layer(31 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + res_mk = layout.layer(110, 5 ) + + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + nplus_s_res_w = w * dbu_PERCISION + nplus_s_res_l = l * dbu_PERCISION + cmp_res_enc = 0.29 * dbu_PERCISION + implant_cmp_enc = 0.16 * dbu_PERCISION + ncmp_pcmp_spc = 0.72 * dbu_PERCISION + pcmp_width = 0.36 * dbu_PERCISION + metal_width = 0.34 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + min_cmp_area = 0.2025 * dbu_PERCISION * dbu_PERCISION + tie_violat = 0 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + dnwell_enc_lvpwell = 2.5 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + lvpwell_enc_pcmp = 0.12 * dbu_PERCISION + lvpwell_enc_ncmp = 0.43 * dbu_PERCISION + + # Inserting nplus_s_res cell + cell_index = layout.add_cell("nplus_s_resistor") + nplus_s_res_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting res_mk + nplus_s_res_cell.shapes(res_mk).insert(pya.Box(0, 0, nplus_s_res_w, nplus_s_res_l)) + + # Inserting n diffusion + nplus_s_res_cell.shapes(comp).insert(pya.Box(-cmp_res_enc, 0, nplus_s_res_w+cmp_res_enc, nplus_s_res_l)) + nplus_s_res_cell.shapes(nplus).insert(pya.Box(-cmp_res_enc-implant_cmp_enc, -implant_cmp_enc , nplus_s_res_w+cmp_res_enc+implant_cmp_enc, nplus_s_res_l+implant_cmp_enc)) + + # Inserting ncomp metal + nplus_s_res_cell.shapes(metal1).insert(pya.Box(-cont_size-met_cont_enc , cmp_met_cont_enc_diff , met_cont_enc , nplus_s_res_l-cmp_met_cont_enc_diff)) #left + nplus_s_res_cell.shapes(metal1).insert(pya.Box(nplus_s_res_w-met_cont_enc, cmp_met_cont_enc_diff , nplus_s_res_w+cont_size+met_cont_enc , nplus_s_res_l-cmp_met_cont_enc_diff)) # Right + + # Inserting ncomp contacts + num_ncmp_left_con_1, ncmp_left_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_left_con_2, ncmp_left_con_free_spc_2 = number_spc_contacts(nplus_s_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cont_size-met_cont_enc+ncmp_left_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_left_con_1, num_ncmp_left_con_2) + nplus_s_res_cell.insert(ncmp_left_con_arr) + + num_ncmp_right_con_1, ncmp_right_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_right_con_2, ncmp_right_con_free_spc_2 = number_spc_contacts(nplus_s_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(nplus_s_res_w-met_cont_enc+ncmp_right_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_right_con_1, num_ncmp_right_con_2) + nplus_s_res_cell.insert(ncmp_right_con_arr) + + if deepnwell == True: + sub = 1 + # Inserting lvpwell + nplus_s_res_cell.shapes(lvpwell).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp, -lvpwell_enc_ncmp , nplus_s_res_w+cmp_res_enc+lvpwell_enc_ncmp, nplus_s_res_l+lvpwell_enc_ncmp)) + # Inserting dnwell + nplus_s_res_cell.shapes(dnwell).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp-dnwell_enc_lvpwell, -lvpwell_enc_ncmp-dnwell_enc_lvpwell , nplus_s_res_w+cmp_res_enc+lvpwell_enc_ncmp+dnwell_enc_lvpwell, nplus_s_res_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell)) + + # Inserting Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw , nplus_s_res_w+cmp_res_enc+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw, nplus_s_res_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw) + cmp_outer = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw-gr_w, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw-gr_w , nplus_s_res_w+cmp_res_enc+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+gr_w, nplus_s_res_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + nplus_s_res_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw+implant_cmp_enc, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw+implant_cmp_enc , nplus_s_res_w+cmp_res_enc+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw-implant_cmp_enc, nplus_s_res_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw-gr_w-implant_cmp_enc, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw-gr_w-implant_cmp_enc , nplus_s_res_w+cmp_res_enc+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+gr_w+implant_cmp_enc, nplus_s_res_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+gr_w+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + nplus_s_res_cell.shapes(pplus).insert(pp_gr) + + else: + # Inserting lvpwell + nplus_s_res_cell.shapes(lvpwell).insert(pya.Box(-cmp_res_enc-implant_cmp_enc, -implant_cmp_enc , nplus_s_res_w+cmp_res_enc+implant_cmp_enc, nplus_s_res_l+implant_cmp_enc)) + + + if sub == 1: + # Inserting p diffusion + if (nplus_s_res_l * pcmp_width) < min_cmp_area: + tie_violat = (min_cmp_area/pcmp_width - nplus_s_res_l)/2 * tol + nplus_s_res_cell.shapes(comp).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width, -tie_violat, -cmp_res_enc-ncmp_pcmp_spc, nplus_s_res_l+tie_violat)) + nplus_s_res_cell.shapes(pplus).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc-tie_violat , -cmp_res_enc-ncmp_pcmp_spc+implant_cmp_enc, nplus_s_res_l+implant_cmp_enc+tie_violat)) + + # Inserting pcomp metal + nplus_s_res_cell.shapes(metal1).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width, -tie_violat, -cmp_res_enc-ncmp_pcmp_spc, nplus_s_res_l+tie_violat)) + + # Inserting pcomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(pcmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(nplus_s_res_l, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width+pcmp_con_free_spc_1 / 2, pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + nplus_s_res_cell.insert(pcmp_con_arr) + + nplus_s_res_cell.flatten(True) + return nplus_s_res_cell + +def draw_pplus_s_res(layout, l, w, deepnwell, pcmpgr): + ''' + Usage:- + used to draw3-terminal salicided P+ diffusion resistor (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + nwell = layout.layer(21 , 0 ) + pplus = layout.layer(31 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + res_mk = layout.layer(110, 5 ) + + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + pplus_s_res_w = w * dbu_PERCISION + pplus_s_res_l = l * dbu_PERCISION + cmp_res_enc = 0.29 * dbu_PERCISION + implant_cmp_enc = 0.16 * dbu_PERCISION + nwell_pcmp_enc = 0.8 * dbu_PERCISION + nwell_ncmp_enc = 0.12 * dbu_PERCISION + ncmp_pcmp_spc = 0.32 * dbu_PERCISION + ncmp_width = 0.36 * dbu_PERCISION + metal_width = 0.34 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + min_cmp_area = 0.2025 * dbu_PERCISION * dbu_PERCISION + tie_violat = 0 * dbu_PERCISION + dnwell_ncmp_enc = 0.62 * dbu_PERCISION + dnwell_pcmp_enc = 0.93 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + + # Inserting pplus_s_res cell + cell_index = layout.add_cell("pplus_s_resistor") + pplus_s_res_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting res_mk + pplus_s_res_cell.shapes(res_mk).insert(pya.Box(0, 0, pplus_s_res_w, pplus_s_res_l)) + + # Inserting p diffusion + pplus_s_res_cell.shapes(comp).insert(pya.Box(-cmp_res_enc, 0, pplus_s_res_w+cmp_res_enc, pplus_s_res_l)) + pplus_s_res_cell.shapes(pplus).insert(pya.Box(-cmp_res_enc-implant_cmp_enc, -implant_cmp_enc , pplus_s_res_w+cmp_res_enc+implant_cmp_enc, pplus_s_res_l+implant_cmp_enc)) + + # Inserting pcomp metal + pplus_s_res_cell.shapes(metal1).insert(pya.Box(-cont_size-met_cont_enc , cmp_met_cont_enc_diff , met_cont_enc , pplus_s_res_l-cmp_met_cont_enc_diff)) #left + pplus_s_res_cell.shapes(metal1).insert(pya.Box(pplus_s_res_w-met_cont_enc, cmp_met_cont_enc_diff , pplus_s_res_w+cont_size+met_cont_enc , pplus_s_res_l-cmp_met_cont_enc_diff)) # Right + + # Inserting pcomp contacts + num_pcmp_left_con_1, pcmp_left_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_pcmp_left_con_2, pcmp_left_con_free_spc_2 = number_spc_contacts(pplus_s_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + pcmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cont_size-met_cont_enc+pcmp_left_con_free_spc_1 / 2, cmp_met_cont_enc_diff+pcmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_left_con_1, num_pcmp_left_con_2) + pplus_s_res_cell.insert(pcmp_left_con_arr) + + num_pcmp_right_con_1, pcmp_right_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_pcmp_right_con_2, pcmp_right_con_free_spc_2 = number_spc_contacts(pplus_s_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + pcmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(pplus_s_res_w-met_cont_enc+pcmp_right_con_free_spc_1 / 2, cmp_met_cont_enc_diff+pcmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_right_con_1, num_pcmp_right_con_2) + pplus_s_res_cell.insert(pcmp_right_con_arr) + + # Inserting n diffusion + if (pplus_s_res_l * ncmp_width) < min_cmp_area: + tie_violat = (min_cmp_area/ncmp_width - pplus_s_res_l)/2 * tol + pplus_s_res_cell.shapes(comp).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width, -tie_violat, -cmp_res_enc-ncmp_pcmp_spc, pplus_s_res_l+tie_violat)) + pplus_s_res_cell.shapes(nplus).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-implant_cmp_enc, -implant_cmp_enc-tie_violat , -cmp_res_enc-ncmp_pcmp_spc+implant_cmp_enc, pplus_s_res_l+implant_cmp_enc+tie_violat)) + + # Inserting ncomp metal + pplus_s_res_cell.shapes(metal1).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width, -tie_violat, -cmp_res_enc-ncmp_pcmp_spc, pplus_s_res_l+tie_violat)) + + # Inserting ncomp contacts + num_ncmp_con_1, ncmp_con_free_spc_1 = number_spc_contacts(ncmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_ncmp_con_2, ncmp_con_free_spc_2 = number_spc_contacts(pplus_s_res_l, comp_cont_enc, cont_min_spc, cont_size) + ncmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width+ncmp_con_free_spc_1 / 2, ncmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_con_1, num_ncmp_con_2) + pplus_s_res_cell.insert(ncmp_con_arr) + + if deepnwell == True: + # Inserting dnwell + pplus_s_res_cell.shapes(dnwell).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-dnwell_ncmp_enc, -dnwell_pcmp_enc , pplus_s_res_w+cmp_res_enc+dnwell_pcmp_enc, pplus_s_res_l+dnwell_pcmp_enc)) + + # Inserting Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-dnwell_ncmp_enc-pcmp_gr2dnw, -dnwell_pcmp_enc-pcmp_gr2dnw , pplus_s_res_w+cmp_res_enc+dnwell_pcmp_enc+pcmp_gr2dnw, pplus_s_res_l+dnwell_pcmp_enc+pcmp_gr2dnw) + cmp_outer = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-dnwell_ncmp_enc-pcmp_gr2dnw-gr_w, -dnwell_pcmp_enc-pcmp_gr2dnw-gr_w , pplus_s_res_w+cmp_res_enc+dnwell_pcmp_enc+pcmp_gr2dnw+gr_w, pplus_s_res_l+dnwell_pcmp_enc+pcmp_gr2dnw+gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + pplus_s_res_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-dnwell_ncmp_enc-pcmp_gr2dnw+implant_cmp_enc, -dnwell_pcmp_enc-pcmp_gr2dnw+implant_cmp_enc , pplus_s_res_w+cmp_res_enc+dnwell_pcmp_enc+pcmp_gr2dnw-implant_cmp_enc, pplus_s_res_l+dnwell_pcmp_enc+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-dnwell_ncmp_enc-pcmp_gr2dnw-gr_w-implant_cmp_enc, -dnwell_pcmp_enc-pcmp_gr2dnw-gr_w-implant_cmp_enc , pplus_s_res_w+cmp_res_enc+dnwell_pcmp_enc+pcmp_gr2dnw+gr_w+implant_cmp_enc, pplus_s_res_l+dnwell_pcmp_enc+pcmp_gr2dnw+gr_w+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + pplus_s_res_cell.shapes(pplus).insert(pp_gr) + + else: + # Inserting nwell + pplus_s_res_cell.shapes(nwell).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-nwell_ncmp_enc, -nwell_pcmp_enc , pplus_s_res_w+cmp_res_enc+nwell_pcmp_enc, pplus_s_res_l+nwell_pcmp_enc)) + + + pplus_s_res_cell.flatten(True) + return pplus_s_res_cell + +def draw_nplus_u_res(layout, l, w , sub, deepnwell, pcmpgr): + ''' + Usage:- + used to draw 3-terminal unsalicided n+ diffusion resistor (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + lvpwell = layout.layer(204, 0 ) + pplus = layout.layer(31 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + sab = layout.layer(49 , 0 ) + res_mk = layout.layer(110, 5 ) + + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + nplus_u_res_w = w * dbu_PERCISION + nplus_u_res_l = l * dbu_PERCISION + cmp_res_enc = 0.44 * dbu_PERCISION + sab_res_enc = 0.23 * dbu_PERCISION + implant_cmp_enc = 0.18 * dbu_PERCISION + ncmp_pcmp_spc = 0.76 * dbu_PERCISION + pcmp_width = 0.36 * dbu_PERCISION + metal_width = 0.34 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + min_cmp_area = 0.2025 * dbu_PERCISION * dbu_PERCISION + tie_violat = 0 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + dnwell_enc_lvpwell = 2.5 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + lvpwell_enc_pcmp = 0.12 * dbu_PERCISION + lvpwell_enc_ncmp = 0.43 * dbu_PERCISION + + # Inserting nplus_u_res cell + cell_index = layout.add_cell("nplus_u_resistor") + nplus_u_res_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting res_mk + nplus_u_res_cell.shapes(res_mk).insert(pya.Box(0, 0, nplus_u_res_w, nplus_u_res_l)) + + # Inserting sab + nplus_u_res_cell.shapes(sab).insert(pya.Box(0, -sab_res_enc, nplus_u_res_w, nplus_u_res_l+sab_res_enc)) + + # Inserting n diffusion + nplus_u_res_cell.shapes(comp).insert(pya.Box(-cmp_res_enc, 0, nplus_u_res_w+cmp_res_enc, nplus_u_res_l)) + nplus_u_res_cell.shapes(nplus).insert(pya.Box(-cmp_res_enc-implant_cmp_enc, -implant_cmp_enc , nplus_u_res_w+cmp_res_enc+implant_cmp_enc, nplus_u_res_l+implant_cmp_enc)) + + # Inserting ncomp metal + nplus_u_res_cell.shapes(metal1).insert(pya.Box(-cmp_res_enc+cmp_met_cont_enc_diff , cmp_met_cont_enc_diff , -cmp_res_enc+cmp_met_cont_enc_diff+metal_width , nplus_u_res_l-cmp_met_cont_enc_diff)) #left + nplus_u_res_cell.shapes(metal1).insert(pya.Box(nplus_u_res_w+cmp_res_enc-cmp_met_cont_enc_diff-metal_width, cmp_met_cont_enc_diff , nplus_u_res_w+cmp_res_enc-cmp_met_cont_enc_diff , nplus_u_res_l-cmp_met_cont_enc_diff)) # Right + + # Inserting ncomp contacts + num_ncmp_left_con_1, ncmp_left_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_left_con_2, ncmp_left_con_free_spc_2 = number_spc_contacts(nplus_u_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cmp_res_enc+cmp_met_cont_enc_diff+ncmp_left_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_left_con_1, num_ncmp_left_con_2) + nplus_u_res_cell.insert(ncmp_left_con_arr) + + num_ncmp_right_con_1, ncmp_right_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_right_con_2, ncmp_right_con_free_spc_2 = number_spc_contacts(nplus_u_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(nplus_u_res_w+cmp_res_enc-cmp_met_cont_enc_diff-metal_width+ncmp_right_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_right_con_1, num_ncmp_right_con_2) + nplus_u_res_cell.insert(ncmp_right_con_arr) + + if deepnwell == True: + sub = 1 + # Inserting lvpwell + nplus_u_res_cell.shapes(lvpwell).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp, -lvpwell_enc_ncmp , nplus_u_res_w+cmp_res_enc+lvpwell_enc_ncmp, nplus_u_res_l+lvpwell_enc_ncmp)) + # Inserting dnwell + nplus_u_res_cell.shapes(dnwell).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp-dnwell_enc_lvpwell, -lvpwell_enc_ncmp-dnwell_enc_lvpwell , nplus_u_res_w+cmp_res_enc+lvpwell_enc_ncmp+dnwell_enc_lvpwell, nplus_u_res_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell)) + + # Inserting Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw , nplus_u_res_w+cmp_res_enc+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw, nplus_u_res_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw) + cmp_outer = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw-gr_w, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw-gr_w , nplus_u_res_w+cmp_res_enc+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+gr_w, nplus_u_res_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + nplus_u_res_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw+implant_cmp_enc, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw+implant_cmp_enc , nplus_u_res_w+cmp_res_enc+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw-implant_cmp_enc, nplus_u_res_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-lvpwell_enc_pcmp-dnwell_enc_lvpwell-pcmp_gr2dnw-gr_w-implant_cmp_enc, -lvpwell_enc_ncmp-dnwell_enc_lvpwell-pcmp_gr2dnw-gr_w-implant_cmp_enc , nplus_u_res_w+cmp_res_enc+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+gr_w+implant_cmp_enc, nplus_u_res_l+lvpwell_enc_ncmp+dnwell_enc_lvpwell+pcmp_gr2dnw+gr_w+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + nplus_u_res_cell.shapes(pplus).insert(pp_gr) + + else: + # Inserting lvpwell + nplus_u_res_cell.shapes(lvpwell).insert(pya.Box(-cmp_res_enc-implant_cmp_enc, -implant_cmp_enc , nplus_u_res_w+cmp_res_enc+implant_cmp_enc, nplus_u_res_l+implant_cmp_enc)) + + + if sub == 1: + # Inserting p diffusion + if (nplus_u_res_l * pcmp_width) < min_cmp_area: + tie_violat = (min_cmp_area/pcmp_width - nplus_u_res_l)/2 * tol + nplus_u_res_cell.shapes(comp).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width, -tie_violat, -cmp_res_enc-ncmp_pcmp_spc, nplus_u_res_l+tie_violat)) + nplus_u_res_cell.shapes(pplus).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc-tie_violat , -cmp_res_enc-ncmp_pcmp_spc+implant_cmp_enc, nplus_u_res_l+tie_violat+implant_cmp_enc)) + + # Inserting pcomp metal + nplus_u_res_cell.shapes(metal1).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width, -tie_violat, -cmp_res_enc-ncmp_pcmp_spc, nplus_u_res_l+tie_violat)) + + # Inserting pcomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(pcmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(nplus_u_res_l, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cmp_res_enc-ncmp_pcmp_spc-pcmp_width+pcmp_con_free_spc_1 / 2, pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + nplus_u_res_cell.insert(pcmp_con_arr) + + nplus_u_res_cell.flatten(True) + return nplus_u_res_cell + +def draw_pplus_u_res(layout, l, w, deepnwell, pcmpgr): + ''' + Usage:- + used to draw 3-terminal unsalicided P+ diffusion resistor (Outsdie DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + nwell = layout.layer(21 , 0 ) + pplus = layout.layer(31 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + sab = layout.layer(49 , 0 ) + res_mk = layout.layer(110, 5 ) + + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + pplus_u_res_w = w * dbu_PERCISION + pplus_u_res_l = l * dbu_PERCISION + cmp_res_enc = 0.44 * dbu_PERCISION + sab_res_enc = 0.23 * dbu_PERCISION + implant_cmp_enc = 0.18 * dbu_PERCISION + nwell_ncmp_enc = 0.12 * dbu_PERCISION + nwell_pcmp_enc = 0.93 * dbu_PERCISION + ncmp_pcmp_spc = 0.34 * dbu_PERCISION + ncmp_width = 0.36 * dbu_PERCISION + metal_width = 0.34 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + min_cmp_area = 0.2025 * dbu_PERCISION * dbu_PERCISION + tie_violat = 0 * dbu_PERCISION + dnwell_ncmp_enc = 0.62 * dbu_PERCISION + dnwell_pcmp_enc = 0.93 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + + # Inserting pplus_u_res cell + cell_index = layout.add_cell("pplus_u_resistor") + pplus_u_res_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting res_mk + pplus_u_res_cell.shapes(res_mk).insert(pya.Box(0, 0, pplus_u_res_w, pplus_u_res_l)) + + # Inserting sab + pplus_u_res_cell.shapes(sab).insert(pya.Box(0, -sab_res_enc, pplus_u_res_w, pplus_u_res_l+sab_res_enc)) + + # Inserting p diffusion + pplus_u_res_cell.shapes(comp).insert(pya.Box(-cmp_res_enc, 0, pplus_u_res_w+cmp_res_enc, pplus_u_res_l)) + pplus_u_res_cell.shapes(pplus).insert(pya.Box(-cmp_res_enc-implant_cmp_enc, -implant_cmp_enc , pplus_u_res_w+cmp_res_enc+implant_cmp_enc, pplus_u_res_l+implant_cmp_enc)) + + # Inserting pcomp metal + pplus_u_res_cell.shapes(metal1).insert(pya.Box(-cmp_res_enc+cmp_met_cont_enc_diff , cmp_met_cont_enc_diff , -cmp_res_enc+cmp_met_cont_enc_diff+metal_width , pplus_u_res_l-cmp_met_cont_enc_diff)) #left + pplus_u_res_cell.shapes(metal1).insert(pya.Box(pplus_u_res_w+cmp_res_enc-cmp_met_cont_enc_diff-metal_width, cmp_met_cont_enc_diff , pplus_u_res_w+cmp_res_enc-cmp_met_cont_enc_diff , pplus_u_res_l-cmp_met_cont_enc_diff)) # Right + + # Inserting pcomp contacts + num_pcmp_left_con_1, pcmp_left_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_pcmp_left_con_2, pcmp_left_con_free_spc_2 = number_spc_contacts(pplus_u_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + pcmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cmp_res_enc+cmp_met_cont_enc_diff+pcmp_left_con_free_spc_1 / 2, cmp_met_cont_enc_diff+pcmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_left_con_1, num_pcmp_left_con_2) + pplus_u_res_cell.insert(pcmp_left_con_arr) + + num_pcmp_right_con_1, pcmp_right_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_pcmp_right_con_2, pcmp_right_con_free_spc_2 = number_spc_contacts(pplus_u_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + pcmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(pplus_u_res_w+cmp_res_enc-cmp_met_cont_enc_diff-metal_width+pcmp_right_con_free_spc_1 / 2, cmp_met_cont_enc_diff+pcmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_right_con_1, num_pcmp_right_con_2) + pplus_u_res_cell.insert(pcmp_right_con_arr) + + # Inserting n diffusion + if (pplus_u_res_l * ncmp_width) < min_cmp_area: + tie_violat = (min_cmp_area/ncmp_width - pplus_u_res_l)/2 * tol + pplus_u_res_cell.shapes(comp).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width, -tie_violat, -cmp_res_enc-ncmp_pcmp_spc, pplus_u_res_l+tie_violat)) + pplus_u_res_cell.shapes(nplus).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-implant_cmp_enc, -implant_cmp_enc-tie_violat , -cmp_res_enc-ncmp_pcmp_spc+implant_cmp_enc, pplus_u_res_l+implant_cmp_enc+tie_violat)) + + # Inserting ncomp metal + pplus_u_res_cell.shapes(metal1).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width, -tie_violat, -cmp_res_enc-ncmp_pcmp_spc, pplus_u_res_l+tie_violat)) + + # Inserting ncomp contacts + num_ncmp_con_1, ncmp_con_free_spc_1 = number_spc_contacts(ncmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_ncmp_con_2, ncmp_con_free_spc_2 = number_spc_contacts(pplus_u_res_l, comp_cont_enc, cont_min_spc, cont_size) + ncmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width+ncmp_con_free_spc_1 / 2, ncmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_con_1, num_ncmp_con_2) + pplus_u_res_cell.insert(ncmp_con_arr) + + if deepnwell == True: + # Inserting dnwell + pplus_u_res_cell.shapes(dnwell).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-dnwell_ncmp_enc, -dnwell_pcmp_enc , pplus_u_res_w+cmp_res_enc+dnwell_pcmp_enc, pplus_u_res_l+dnwell_pcmp_enc)) + + # Inserting Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-dnwell_ncmp_enc-pcmp_gr2dnw, -dnwell_pcmp_enc-pcmp_gr2dnw , pplus_u_res_w+cmp_res_enc+dnwell_pcmp_enc+pcmp_gr2dnw, pplus_u_res_l+dnwell_pcmp_enc+pcmp_gr2dnw) + cmp_outer = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-dnwell_ncmp_enc-pcmp_gr2dnw-gr_w, -dnwell_pcmp_enc-pcmp_gr2dnw-gr_w , pplus_u_res_w+cmp_res_enc+dnwell_pcmp_enc+pcmp_gr2dnw+gr_w, pplus_u_res_l+dnwell_pcmp_enc+pcmp_gr2dnw+gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + pplus_u_res_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-dnwell_ncmp_enc-pcmp_gr2dnw+implant_cmp_enc, -dnwell_pcmp_enc-pcmp_gr2dnw+implant_cmp_enc , pplus_u_res_w+cmp_res_enc+dnwell_pcmp_enc+pcmp_gr2dnw-implant_cmp_enc, pplus_u_res_l+dnwell_pcmp_enc+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-dnwell_ncmp_enc-pcmp_gr2dnw-gr_w-implant_cmp_enc, -dnwell_pcmp_enc-pcmp_gr2dnw-gr_w-implant_cmp_enc , pplus_u_res_w+cmp_res_enc+dnwell_pcmp_enc+pcmp_gr2dnw+gr_w+implant_cmp_enc, pplus_u_res_l+dnwell_pcmp_enc+pcmp_gr2dnw+gr_w+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + pplus_u_res_cell.shapes(pplus).insert(pp_gr) + + else: + # Inserting nwell + pplus_u_res_cell.shapes(nwell).insert(pya.Box(-cmp_res_enc-ncmp_pcmp_spc-ncmp_width-nwell_ncmp_enc, -nwell_pcmp_enc , pplus_u_res_w+cmp_res_enc+nwell_pcmp_enc, pplus_u_res_l+nwell_pcmp_enc)) + + + pplus_u_res_cell.flatten(True) + return pplus_u_res_cell + +def draw_nwell_res(layout, l, w): + ''' + Usage:- + used to draw 3-terminal Nwell resistor under STI (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + comp = layout.layer(22 , 0 ) + nwell = layout.layer(21 , 0 ) + pplus = layout.layer(31 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + res_mk = layout.layer(110, 5 ) + + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + nwell_res_w = w * dbu_PERCISION + nwell_res_l = l * dbu_PERCISION + nwell_res_enc = 0.48 * dbu_PERCISION + res_nwell_ext = 0.5 * dbu_PERCISION + implant_cmp_enc = 0.16 * dbu_PERCISION + nwell_cmp_enc = 0.12 * dbu_PERCISION + ncmp_pcmp_spc = 0.84 * dbu_PERCISION + cmp_width = 0.36 * dbu_PERCISION + metal_width = 0.34 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + + # Inserting nwell_res cell + cell_index = layout.add_cell("nwell_resistor") + nwell_res_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting res_mk + nwell_res_cell.shapes(res_mk).insert(pya.Box(0, -res_nwell_ext, nwell_res_w, nwell_res_l+res_nwell_ext)) + + # Inserting nwell + nwell_res_cell.shapes(nwell).insert(pya.Box(-nwell_res_enc, 0, nwell_res_w+nwell_res_enc, nwell_res_l)) + + # Inserting n diffusion + nwell_res_cell.shapes(comp).insert(pya.Box(-cmp_width, nwell_cmp_enc, 0, nwell_res_l-nwell_cmp_enc)) #left + nwell_res_cell.shapes(comp).insert(pya.Box(nwell_res_w, nwell_cmp_enc, nwell_res_w+cmp_width, nwell_res_l-nwell_cmp_enc)) #right + nwell_res_cell.shapes(nplus).insert(pya.Box(-cmp_width-implant_cmp_enc, nwell_cmp_enc-implant_cmp_enc , implant_cmp_enc, nwell_res_l-nwell_cmp_enc+implant_cmp_enc)) + nwell_res_cell.shapes(nplus).insert(pya.Box(nwell_res_w-implant_cmp_enc, nwell_cmp_enc-implant_cmp_enc , nwell_res_w+cmp_width+implant_cmp_enc, nwell_res_l-nwell_cmp_enc+implant_cmp_enc)) + + # Inserting ncomp metal + nwell_res_cell.shapes(metal1).insert(pya.Box(-cmp_width, nwell_cmp_enc, 0, nwell_res_l-nwell_cmp_enc)) #left + nwell_res_cell.shapes(metal1).insert(pya.Box(nwell_res_w, nwell_cmp_enc, nwell_res_w+cmp_width, nwell_res_l-nwell_cmp_enc)) #right + + # Inserting ncomp contacts + num_ncmp_left_con_1, ncmp_left_con_free_spc_1 = number_spc_contacts(cmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_ncmp_left_con_2, ncmp_left_con_free_spc_2 = number_spc_contacts(nwell_res_l-2*nwell_cmp_enc, comp_cont_enc, cont_min_spc, cont_size) + ncmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cmp_width+ncmp_left_con_free_spc_1 / 2, nwell_cmp_enc+ncmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_left_con_1, num_ncmp_left_con_2) + nwell_res_cell.insert(ncmp_left_con_arr) + + num_ncmp_right_con_1, ncmp_right_con_free_spc_1 = number_spc_contacts(cmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_ncmp_right_con_2, ncmp_right_con_free_spc_2 = number_spc_contacts(nwell_res_l-2*nwell_cmp_enc, comp_cont_enc, cont_min_spc, cont_size) + ncmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(nwell_res_w+ncmp_right_con_free_spc_1 / 2, nwell_cmp_enc+ncmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_right_con_1, num_ncmp_right_con_2) + nwell_res_cell.insert(ncmp_right_con_arr) + + # Inserting p diffusion + nwell_res_cell.shapes(comp).insert(pya.Box(-cmp_width-ncmp_pcmp_spc-cmp_width, 0, -cmp_width-ncmp_pcmp_spc , nwell_res_l)) + nwell_res_cell.shapes(pplus).insert(pya.Box(-cmp_width-ncmp_pcmp_spc-cmp_width-implant_cmp_enc, -implant_cmp_enc, -cmp_width-ncmp_pcmp_spc+implant_cmp_enc , nwell_res_l+implant_cmp_enc)) + + # Inserting pcomp metal + nwell_res_cell.shapes(metal1).insert(pya.Box(-cmp_width-ncmp_pcmp_spc-cmp_width, 0, -cmp_width-ncmp_pcmp_spc , nwell_res_l)) + + # Inserting pcomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(cmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(nwell_res_l, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cmp_width-ncmp_pcmp_spc-cmp_width+pcmp_con_free_spc_1 / 2, pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + nwell_res_cell.insert(pcmp_con_arr) + + nwell_res_cell.flatten(True) + return nwell_res_cell + +def draw_pwell_res(layout, l, w, pcmpgr): + ''' + Usage:- + used to draw 3-terminal Pwell resistor under STI (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + comp = layout.layer(22 , 0 ) + dnwell = layout.layer(12 , 0 ) + lvpwell = layout.layer(204, 0 ) + pplus = layout.layer(31 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + res_mk = layout.layer(110, 5 ) + + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + pwell_res_w = w * dbu_PERCISION + pwell_res_l = l * dbu_PERCISION + pwell_res_enc = 0.48 * dbu_PERCISION + dnwell_lvpwell_enc = 2.5 * dbu_PERCISION + res_pwell_ext = 0.5 * dbu_PERCISION + implant_cmp_enc = 0.16 * dbu_PERCISION + pwell_cmp_enc = 0.12 * dbu_PERCISION + ncmp_pcmp_spc = 0.84 * dbu_PERCISION + cmp_width = 0.36 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + + # Inserting pwell_res cell + cell_index = layout.add_cell("pwell_resistor") + pwell_res_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting res_mk + pwell_res_cell.shapes(res_mk).insert(pya.Box(0, -res_pwell_ext, pwell_res_w, pwell_res_l+res_pwell_ext)) + + # Inserting pwell + pwell_res_cell.shapes(lvpwell).insert(pya.Box(-pwell_res_enc, 0, pwell_res_w+pwell_res_enc, pwell_res_l)) + + # Inserting DNWELL + pwell_res_cell.shapes(dnwell).insert(pya.Box(-pwell_res_enc-dnwell_lvpwell_enc, -dnwell_lvpwell_enc, pwell_res_w+pwell_res_enc+dnwell_lvpwell_enc, pwell_res_l+dnwell_lvpwell_enc)) + + # Inserting Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-pwell_res_enc-dnwell_lvpwell_enc-pcmp_gr2dnw, -dnwell_lvpwell_enc-pcmp_gr2dnw, pwell_res_w+pwell_res_enc+dnwell_lvpwell_enc+pcmp_gr2dnw, pwell_res_l+dnwell_lvpwell_enc+pcmp_gr2dnw) + cmp_outer = pya.Box(-pwell_res_enc-dnwell_lvpwell_enc-pcmp_gr2dnw-gr_w, -dnwell_lvpwell_enc-pcmp_gr2dnw-gr_w, pwell_res_w+pwell_res_enc+dnwell_lvpwell_enc+pcmp_gr2dnw+gr_w, pwell_res_l+dnwell_lvpwell_enc+pcmp_gr2dnw+gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + pwell_res_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-pwell_res_enc-dnwell_lvpwell_enc-pcmp_gr2dnw+implant_cmp_enc, -dnwell_lvpwell_enc-pcmp_gr2dnw+implant_cmp_enc, pwell_res_w+pwell_res_enc+dnwell_lvpwell_enc+pcmp_gr2dnw-implant_cmp_enc, pwell_res_l+dnwell_lvpwell_enc+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-pwell_res_enc-dnwell_lvpwell_enc-pcmp_gr2dnw-gr_w-implant_cmp_enc, -dnwell_lvpwell_enc-pcmp_gr2dnw-gr_w-implant_cmp_enc, pwell_res_w+pwell_res_enc+dnwell_lvpwell_enc+pcmp_gr2dnw+gr_w+implant_cmp_enc, pwell_res_l+dnwell_lvpwell_enc+pcmp_gr2dnw+gr_w+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + pwell_res_cell.shapes(pplus).insert(pp_gr) + + # Inserting p diffusion + pwell_res_cell.shapes(comp).insert(pya.Box(-cmp_width, pwell_cmp_enc, 0, pwell_res_l-pwell_cmp_enc)) #left + pwell_res_cell.shapes(comp).insert(pya.Box(pwell_res_w, pwell_cmp_enc, pwell_res_w+cmp_width, pwell_res_l-pwell_cmp_enc)) #right + pwell_res_cell.shapes(pplus).insert(pya.Box(-cmp_width-implant_cmp_enc, pwell_cmp_enc-implant_cmp_enc , implant_cmp_enc, pwell_res_l-pwell_cmp_enc+implant_cmp_enc)) + pwell_res_cell.shapes(pplus).insert(pya.Box(pwell_res_w-implant_cmp_enc, pwell_cmp_enc-implant_cmp_enc , pwell_res_w+cmp_width+implant_cmp_enc, pwell_res_l-pwell_cmp_enc+implant_cmp_enc)) + + # Inserting ncomp metal + pwell_res_cell.shapes(metal1).insert(pya.Box(-cmp_width, pwell_cmp_enc, 0, pwell_res_l-pwell_cmp_enc)) #left + pwell_res_cell.shapes(metal1).insert(pya.Box(pwell_res_w, pwell_cmp_enc, pwell_res_w+cmp_width, pwell_res_l-pwell_cmp_enc)) #right + + # Inserting pcomp contacts + num_pcmp_left_con_1, pcmp_left_con_free_spc_1 = number_spc_contacts(cmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_left_con_2, pcmp_left_con_free_spc_2 = number_spc_contacts(pwell_res_l-2*pwell_cmp_enc, comp_cont_enc, cont_min_spc, cont_size) + pcmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cmp_width+pcmp_left_con_free_spc_1 / 2, pwell_cmp_enc+pcmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_left_con_1, num_pcmp_left_con_2) + pwell_res_cell.insert(pcmp_left_con_arr) + + num_ncmp_right_con_1, ncmp_right_con_free_spc_1 = number_spc_contacts(cmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_ncmp_right_con_2, ncmp_right_con_free_spc_2 = number_spc_contacts(pwell_res_l-2*pwell_cmp_enc, comp_cont_enc, cont_min_spc, cont_size) + ncmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(pwell_res_w+ncmp_right_con_free_spc_1 / 2, pwell_cmp_enc+ncmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_right_con_1, num_ncmp_right_con_2) + pwell_res_cell.insert(ncmp_right_con_arr) + + # Inserting n diffusion + pwell_res_cell.shapes(comp).insert(pya.Box(-cmp_width-ncmp_pcmp_spc-cmp_width, 0, -cmp_width-ncmp_pcmp_spc , pwell_res_l)) + pwell_res_cell.shapes(nplus).insert(pya.Box(-cmp_width-ncmp_pcmp_spc-cmp_width-implant_cmp_enc, -implant_cmp_enc, -cmp_width-ncmp_pcmp_spc+implant_cmp_enc , pwell_res_l+implant_cmp_enc)) + + # Inserting pcomp metal + pwell_res_cell.shapes(metal1).insert(pya.Box(-cmp_width-ncmp_pcmp_spc-cmp_width, 0, -cmp_width-ncmp_pcmp_spc , pwell_res_l)) + + # Inserting pcomp contacts + num_ncmp_con_1, ncmp_con_free_spc_1 = number_spc_contacts(cmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_ncmp_con_2, ncmp_con_free_spc_2 = number_spc_contacts(pwell_res_l, comp_cont_enc, cont_min_spc, cont_size) + ncmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cmp_width-ncmp_pcmp_spc-cmp_width+ncmp_con_free_spc_1 / 2, ncmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_con_1, num_ncmp_con_2) + pwell_res_cell.insert(ncmp_con_arr) + + pwell_res_cell.flatten(True) + return pwell_res_cell + +def draw_npolyf_s_res(layout, l, w, deepnwell, pcmpgr): + ''' + Usage:- + used to draw 3-terminal salicided n+ poly resistor (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + poly = layout.layer(30 , 0 ) + pplus = layout.layer(31 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + res_mk = layout.layer(110, 5 ) + + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + npolyf_s_res_w = w * dbu_PERCISION + npolyf_s_res_l = l * dbu_PERCISION + poly_res_enc = 0.29 * dbu_PERCISION + implant_cmp_enc = 0.16 * dbu_PERCISION + implant_poly_enc = 0.3 * dbu_PERCISION + npoly_pcmp_spc = 0.72 * dbu_PERCISION + pcmp_width = 0.36 * dbu_PERCISION + metal_width = 0.34 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + dnwell_enc_ncmp = 0.62 * dbu_PERCISION + dnwell_enc_poly = 1.34 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + + # Inserting npolyf_s_res cell + cell_index = layout.add_cell("npolyf_s_resistor") + npolyf_s_res_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting res_mk + npolyf_s_res_cell.shapes(res_mk).insert(pya.Box(0, 0, npolyf_s_res_w, npolyf_s_res_l)) + + # Inserting n poly + npolyf_s_res_cell.shapes(poly).insert(pya.Box(-poly_res_enc, 0, npolyf_s_res_w+poly_res_enc, npolyf_s_res_l)) + npolyf_s_res_cell.shapes(nplus).insert(pya.Box(-poly_res_enc-implant_poly_enc, -implant_poly_enc , npolyf_s_res_w+poly_res_enc+implant_poly_enc, npolyf_s_res_l+implant_poly_enc)) + + # Inserting ncomp metal + npolyf_s_res_cell.shapes(metal1).insert(pya.Box(-cont_size-met_cont_enc , cmp_met_cont_enc_diff , met_cont_enc , npolyf_s_res_l-cmp_met_cont_enc_diff)) #left + npolyf_s_res_cell.shapes(metal1).insert(pya.Box(npolyf_s_res_w-met_cont_enc, cmp_met_cont_enc_diff , npolyf_s_res_w+cont_size+met_cont_enc , npolyf_s_res_l-cmp_met_cont_enc_diff)) # Right + + # Inserting ncomp contacts + num_ncmp_left_con_1, ncmp_left_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_left_con_2, ncmp_left_con_free_spc_2 = number_spc_contacts(npolyf_s_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cont_size-met_cont_enc+ncmp_left_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_left_con_1, num_ncmp_left_con_2) + npolyf_s_res_cell.insert(ncmp_left_con_arr) + + num_ncmp_right_con_1, ncmp_right_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_right_con_2, ncmp_right_con_free_spc_2 = number_spc_contacts(npolyf_s_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(npolyf_s_res_w-met_cont_enc+ncmp_right_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_right_con_1, num_ncmp_right_con_2) + npolyf_s_res_cell.insert(ncmp_right_con_arr) + + # Inserting p diffusion + npolyf_s_res_cell.shapes(comp).insert(pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width, 0, -poly_res_enc-npoly_pcmp_spc, npolyf_s_res_l)) + + # Inserting pcomp metal + npolyf_s_res_cell.shapes(metal1).insert(pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width, 0, -poly_res_enc-npoly_pcmp_spc, npolyf_s_res_l)) + + # Inserting pcomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(pcmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(npolyf_s_res_l, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-poly_res_enc-npoly_pcmp_spc-pcmp_width+pcmp_con_free_spc_1 / 2, pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + npolyf_s_res_cell.insert(pcmp_con_arr) + + if deepnwell == True: + # Inserting Ntap + npolyf_s_res_cell.shapes(nplus).insert(pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc , -poly_res_enc-npoly_pcmp_spc+implant_cmp_enc, npolyf_s_res_l+implant_cmp_enc)) + + # Inserting dnwell + npolyf_s_res_cell.shapes(dnwell).insert(pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp, -dnwell_enc_poly , npolyf_s_res_w+poly_res_enc+dnwell_enc_poly, npolyf_s_res_l+dnwell_enc_poly)) + + # Inserting Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw, -dnwell_enc_poly-pcmp_gr2dnw , npolyf_s_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw, npolyf_s_res_l+dnwell_enc_poly+pcmp_gr2dnw) + cmp_outer = pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw-gr_w, -dnwell_enc_poly-pcmp_gr2dnw-gr_w , npolyf_s_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw+gr_w, npolyf_s_res_l+dnwell_enc_poly+pcmp_gr2dnw+gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + npolyf_s_res_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw+implant_cmp_enc, -dnwell_enc_poly-pcmp_gr2dnw+implant_cmp_enc , npolyf_s_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw-implant_cmp_enc, npolyf_s_res_l+dnwell_enc_poly+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw-gr_w-implant_cmp_enc, -dnwell_enc_poly-pcmp_gr2dnw-gr_w-implant_cmp_enc , npolyf_s_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw+gr_w+implant_cmp_enc, npolyf_s_res_l+dnwell_enc_poly+pcmp_gr2dnw+gr_w+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + npolyf_s_res_cell.shapes(pplus).insert(pp_gr) + + else: + npolyf_s_res_cell.shapes(pplus).insert(pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc , -poly_res_enc-npoly_pcmp_spc+implant_cmp_enc, npolyf_s_res_l+implant_cmp_enc)) + + + npolyf_s_res_cell.flatten(True) + return npolyf_s_res_cell + +def draw_ppolyf_s_res(layout, l, w, deepnwell, pcmpgr): + ''' + Usage:- + used to draw 3-terminal salicided p+ poly resistor (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + poly = layout.layer(30 , 0 ) + pplus = layout.layer(31 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + res_mk = layout.layer(110, 5 ) + + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + ppolyf_s_res_w = w * dbu_PERCISION + ppolyf_s_res_l = l * dbu_PERCISION + poly_res_enc = 0.29 * dbu_PERCISION + implant_cmp_enc = 0.16 * dbu_PERCISION + implant_poly_enc = 0.3 * dbu_PERCISION + ppoly_pcmp_spc = 0.86 * dbu_PERCISION + pcmp_width = 0.36 * dbu_PERCISION + metal_width = 0.34 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + dnwell_enc_ncmp = 0.62 * dbu_PERCISION + dnwell_enc_poly = 1.34 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + + # Inserting ppolyf_s_res cell + cell_index = layout.add_cell("ppolyf_s_resistor") + ppolyf_s_res_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting res_mk + ppolyf_s_res_cell.shapes(res_mk).insert(pya.Box(0, 0, ppolyf_s_res_w, ppolyf_s_res_l)) + + # Inserting n poly + ppolyf_s_res_cell.shapes(poly).insert(pya.Box(-poly_res_enc, 0, ppolyf_s_res_w+poly_res_enc, ppolyf_s_res_l)) + ppolyf_s_res_cell.shapes(pplus).insert(pya.Box(-poly_res_enc-implant_poly_enc, -implant_poly_enc , ppolyf_s_res_w+poly_res_enc+implant_poly_enc, ppolyf_s_res_l+implant_poly_enc)) + + # Inserting ncomp metal + ppolyf_s_res_cell.shapes(metal1).insert(pya.Box(-cont_size-met_cont_enc , cmp_met_cont_enc_diff , met_cont_enc , ppolyf_s_res_l-cmp_met_cont_enc_diff)) #left + ppolyf_s_res_cell.shapes(metal1).insert(pya.Box(ppolyf_s_res_w-met_cont_enc, cmp_met_cont_enc_diff , ppolyf_s_res_w+cont_size+met_cont_enc , ppolyf_s_res_l-cmp_met_cont_enc_diff)) # Right + + # Inserting ncomp contacts + num_ncmp_left_con_1, ncmp_left_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_left_con_2, ncmp_left_con_free_spc_2 = number_spc_contacts(ppolyf_s_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-cont_size-met_cont_enc+ncmp_left_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_left_con_1, num_ncmp_left_con_2) + ppolyf_s_res_cell.insert(ncmp_left_con_arr) + + num_ncmp_right_con_1, ncmp_right_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_right_con_2, ncmp_right_con_free_spc_2 = number_spc_contacts(ppolyf_s_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(ppolyf_s_res_w-met_cont_enc+ncmp_right_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_right_con_1, num_ncmp_right_con_2) + ppolyf_s_res_cell.insert(ncmp_right_con_arr) + + # Inserting p diffusion + ppolyf_s_res_cell.shapes(comp).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width, 0, -poly_res_enc-ppoly_pcmp_spc, ppolyf_s_res_l)) + + # Inserting pcomp metal + ppolyf_s_res_cell.shapes(metal1).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width, 0, -poly_res_enc-ppoly_pcmp_spc, ppolyf_s_res_l)) + + # Inserting pcomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(pcmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(ppolyf_s_res_l, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-poly_res_enc-ppoly_pcmp_spc-pcmp_width+pcmp_con_free_spc_1 / 2, pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + ppolyf_s_res_cell.insert(pcmp_con_arr) + + if deepnwell == True: + # Inserting Ntap + ppolyf_s_res_cell.shapes(nplus).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc , -poly_res_enc-ppoly_pcmp_spc+implant_cmp_enc, ppolyf_s_res_l+implant_cmp_enc)) + + # Inserting dnwell + ppolyf_s_res_cell.shapes(dnwell).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp, -dnwell_enc_poly , ppolyf_s_res_w+poly_res_enc+dnwell_enc_poly, ppolyf_s_res_l+dnwell_enc_poly)) + + # Inserting Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw, -dnwell_enc_poly-pcmp_gr2dnw , ppolyf_s_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw, ppolyf_s_res_l+dnwell_enc_poly+pcmp_gr2dnw) + cmp_outer = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw-gr_w, -dnwell_enc_poly-pcmp_gr2dnw-gr_w , ppolyf_s_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw+gr_w, ppolyf_s_res_l+dnwell_enc_poly+pcmp_gr2dnw+gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + ppolyf_s_res_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw+implant_cmp_enc, -dnwell_enc_poly-pcmp_gr2dnw+implant_cmp_enc , ppolyf_s_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw-implant_cmp_enc, ppolyf_s_res_l+dnwell_enc_poly+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw-gr_w-implant_cmp_enc, -dnwell_enc_poly-pcmp_gr2dnw-gr_w-implant_cmp_enc , ppolyf_s_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw+gr_w+implant_cmp_enc, ppolyf_s_res_l+dnwell_enc_poly+pcmp_gr2dnw+gr_w+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + ppolyf_s_res_cell.shapes(pplus).insert(pp_gr) + + else: + ppolyf_s_res_cell.shapes(pplus).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc , -poly_res_enc-ppoly_pcmp_spc+implant_cmp_enc, ppolyf_s_res_l+implant_cmp_enc)) + + + ppolyf_s_res_cell.flatten(True) + return ppolyf_s_res_cell + +def draw_npolyf_u_res(layout, l, w, deepnwell, pcmpgr): + ''' + Usage:- + used to draw 3-terminal unsalicided n+ poly resistor (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + poly = layout.layer(30 , 0 ) + pplus = layout.layer(31 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + sab = layout.layer(49 , 0 ) + res_mk = layout.layer(110, 5 ) + + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + npolyf_u_res_w = w * dbu_PERCISION + npolyf_u_res_l = l * dbu_PERCISION + poly_res_enc = 0.51 * dbu_PERCISION + sab_res_enc = 0.28 * dbu_PERCISION + implant_cmp_enc = 0.16 * dbu_PERCISION + implant_poly_enc = 0.3 * dbu_PERCISION + npoly_pcmp_spc = 0.72 * dbu_PERCISION + pcmp_width = 0.36 * dbu_PERCISION + metal_width = 0.34 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + dnwell_enc_ncmp = 0.62 * dbu_PERCISION + dnwell_enc_poly = 1.34 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + + # Inserting npolyf_u_res cell + cell_index = layout.add_cell("npolyf_u_resistor") + npolyf_u_res_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting res_mk + npolyf_u_res_cell.shapes(res_mk).insert(pya.Box(0, 0, npolyf_u_res_w, npolyf_u_res_l)) + + # Inserting sab + npolyf_u_res_cell.shapes(sab).insert(pya.Box(0, -sab_res_enc, npolyf_u_res_w, npolyf_u_res_l+sab_res_enc)) + + # Inserting n poly + npolyf_u_res_cell.shapes(poly).insert(pya.Box(-poly_res_enc, 0, npolyf_u_res_w+poly_res_enc, npolyf_u_res_l)) + npolyf_u_res_cell.shapes(nplus).insert(pya.Box(-poly_res_enc-implant_poly_enc, -implant_poly_enc , npolyf_u_res_w+poly_res_enc+implant_poly_enc, npolyf_u_res_l+implant_poly_enc)) + + # Inserting npoly metal + npolyf_u_res_cell.shapes(metal1).insert(pya.Box(-poly_res_enc+cmp_met_cont_enc_diff , cmp_met_cont_enc_diff , -poly_res_enc+cmp_met_cont_enc_diff+metal_width , npolyf_u_res_l-cmp_met_cont_enc_diff)) #left + npolyf_u_res_cell.shapes(metal1).insert(pya.Box(npolyf_u_res_w+poly_res_enc-cmp_met_cont_enc_diff-metal_width, cmp_met_cont_enc_diff , npolyf_u_res_w+poly_res_enc-cmp_met_cont_enc_diff , npolyf_u_res_l-cmp_met_cont_enc_diff)) # Right + + # Inserting npoly contacts + num_ncmp_left_con_1, ncmp_left_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_left_con_2, ncmp_left_con_free_spc_2 = number_spc_contacts(npolyf_u_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-poly_res_enc+cmp_met_cont_enc_diff+ncmp_left_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_left_con_1, num_ncmp_left_con_2) + npolyf_u_res_cell.insert(ncmp_left_con_arr) + + num_ncmp_right_con_1, ncmp_right_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_right_con_2, ncmp_right_con_free_spc_2 = number_spc_contacts(npolyf_u_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(npolyf_u_res_w+poly_res_enc-cmp_met_cont_enc_diff-metal_width+ncmp_right_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_right_con_1, num_ncmp_right_con_2) + npolyf_u_res_cell.insert(ncmp_right_con_arr) + + + # Inserting p diffusion + npolyf_u_res_cell.shapes(comp).insert(pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width, 0, -poly_res_enc-npoly_pcmp_spc, npolyf_u_res_l)) + + # Inserting pcomp metal + npolyf_u_res_cell.shapes(metal1).insert(pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width, 0, -poly_res_enc-npoly_pcmp_spc, npolyf_u_res_l)) + + # Inserting pcomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(pcmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(npolyf_u_res_l, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-poly_res_enc-npoly_pcmp_spc-pcmp_width+pcmp_con_free_spc_1 / 2, pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + npolyf_u_res_cell.insert(pcmp_con_arr) + + if deepnwell == True: + # Inserting Ntap + npolyf_u_res_cell.shapes(nplus).insert(pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc , -poly_res_enc-npoly_pcmp_spc+implant_cmp_enc, npolyf_u_res_l+implant_cmp_enc)) + + # Inserting dnwell + npolyf_u_res_cell.shapes(dnwell).insert(pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp, -dnwell_enc_poly , npolyf_u_res_w+poly_res_enc+dnwell_enc_poly, npolyf_u_res_l+dnwell_enc_poly)) + + # Inserting Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw, -dnwell_enc_poly-pcmp_gr2dnw , npolyf_u_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw, npolyf_u_res_l+dnwell_enc_poly+pcmp_gr2dnw) + cmp_outer = pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw-gr_w, -dnwell_enc_poly-pcmp_gr2dnw-gr_w , npolyf_u_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw+gr_w, npolyf_u_res_l+dnwell_enc_poly+pcmp_gr2dnw+gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + npolyf_u_res_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw+implant_cmp_enc, -dnwell_enc_poly-pcmp_gr2dnw+implant_cmp_enc , npolyf_u_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw-implant_cmp_enc, npolyf_u_res_l+dnwell_enc_poly+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw-gr_w-implant_cmp_enc, -dnwell_enc_poly-pcmp_gr2dnw-gr_w-implant_cmp_enc , npolyf_u_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw+gr_w+implant_cmp_enc, npolyf_u_res_l+dnwell_enc_poly+pcmp_gr2dnw+gr_w+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + npolyf_u_res_cell.shapes(pplus).insert(pp_gr) + + else: + npolyf_u_res_cell.shapes(pplus).insert(pya.Box(-poly_res_enc-npoly_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc , -poly_res_enc-npoly_pcmp_spc+implant_cmp_enc, npolyf_u_res_l+implant_cmp_enc)) + + + npolyf_u_res_cell.flatten(True) + return npolyf_u_res_cell + +def draw_ppolyf_u_res(layout, l, w, deepnwell, pcmpgr): + ''' + Usage:- + used to draw 3-terminal unsalicided p+ poly resistor (Outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + poly = layout.layer(30 , 0 ) + pplus = layout.layer(31 , 0 ) + nplus = layout.layer(32 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + sab = layout.layer(49 , 0 ) + res_mk = layout.layer(110, 5 ) + + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + ppolyf_u_res_w = w * dbu_PERCISION + ppolyf_u_res_l = l * dbu_PERCISION + poly_res_enc = 0.51 * dbu_PERCISION + sab_res_enc = 0.28 * dbu_PERCISION + implant_cmp_enc = 0.16 * dbu_PERCISION + implant_poly_enc = 0.3 * dbu_PERCISION + ppoly_pcmp_spc = 0.86 * dbu_PERCISION + pcmp_width = 0.36 * dbu_PERCISION + metal_width = 0.34 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + dnwell_enc_ncmp = 0.62 * dbu_PERCISION + dnwell_enc_poly = 1.34 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + + # Inserting ppolyf_u_res cell + cell_index = layout.add_cell("ppolyf_u_resistor") + ppolyf_u_res_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting res_mk + ppolyf_u_res_cell.shapes(res_mk).insert(pya.Box(0, 0, ppolyf_u_res_w, ppolyf_u_res_l)) + + # Inserting sab + ppolyf_u_res_cell.shapes(sab).insert(pya.Box(0, -sab_res_enc, ppolyf_u_res_w, ppolyf_u_res_l+sab_res_enc)) + + # Inserting p poly + ppolyf_u_res_cell.shapes(poly).insert(pya.Box(-poly_res_enc, 0, ppolyf_u_res_w+poly_res_enc, ppolyf_u_res_l)) + ppolyf_u_res_cell.shapes(pplus).insert(pya.Box(-poly_res_enc-implant_poly_enc, -implant_poly_enc , ppolyf_u_res_w+poly_res_enc+implant_poly_enc, ppolyf_u_res_l+implant_poly_enc)) + + # Inserting npoly metal + ppolyf_u_res_cell.shapes(metal1).insert(pya.Box(-poly_res_enc+cmp_met_cont_enc_diff , cmp_met_cont_enc_diff , -poly_res_enc+cmp_met_cont_enc_diff+metal_width , ppolyf_u_res_l-cmp_met_cont_enc_diff)) #left + ppolyf_u_res_cell.shapes(metal1).insert(pya.Box(ppolyf_u_res_w+poly_res_enc-cmp_met_cont_enc_diff-metal_width, cmp_met_cont_enc_diff , ppolyf_u_res_w+poly_res_enc-cmp_met_cont_enc_diff , ppolyf_u_res_l-cmp_met_cont_enc_diff)) # Right + + # Inserting npoly contacts + num_ncmp_left_con_1, ncmp_left_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_left_con_2, ncmp_left_con_free_spc_2 = number_spc_contacts(ppolyf_u_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-poly_res_enc+cmp_met_cont_enc_diff+ncmp_left_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_left_con_1, num_ncmp_left_con_2) + ppolyf_u_res_cell.insert(ncmp_left_con_arr) + + num_ncmp_right_con_1, ncmp_right_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_right_con_2, ncmp_right_con_free_spc_2 = number_spc_contacts(ppolyf_u_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(ppolyf_u_res_w+poly_res_enc-cmp_met_cont_enc_diff-metal_width+ncmp_right_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_right_con_1, num_ncmp_right_con_2) + ppolyf_u_res_cell.insert(ncmp_right_con_arr) + + + # Inserting p diffusion + ppolyf_u_res_cell.shapes(comp).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width, 0, -poly_res_enc-ppoly_pcmp_spc, ppolyf_u_res_l)) + + # Inserting pcomp metal + ppolyf_u_res_cell.shapes(metal1).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width, 0, -poly_res_enc-ppoly_pcmp_spc, ppolyf_u_res_l)) + + # Inserting pcomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(pcmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(ppolyf_u_res_l, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-poly_res_enc-ppoly_pcmp_spc-pcmp_width+pcmp_con_free_spc_1 / 2, pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + ppolyf_u_res_cell.insert(pcmp_con_arr) + + if deepnwell == True: + # Inserting Ntap + ppolyf_u_res_cell.shapes(nplus).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc , -poly_res_enc-ppoly_pcmp_spc+implant_cmp_enc, ppolyf_u_res_l+implant_cmp_enc)) + + # Inserting dnwell + ppolyf_u_res_cell.shapes(dnwell).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp, -dnwell_enc_poly , ppolyf_u_res_w+poly_res_enc+dnwell_enc_poly, ppolyf_u_res_l+dnwell_enc_poly)) + + # Inserting Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw, -dnwell_enc_poly-pcmp_gr2dnw , ppolyf_u_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw, ppolyf_u_res_l+dnwell_enc_poly+pcmp_gr2dnw) + cmp_outer = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw-gr_w, -dnwell_enc_poly-pcmp_gr2dnw-gr_w , ppolyf_u_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw+gr_w, ppolyf_u_res_l+dnwell_enc_poly+pcmp_gr2dnw+gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + ppolyf_u_res_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw+implant_cmp_enc, -dnwell_enc_poly-pcmp_gr2dnw+implant_cmp_enc , ppolyf_u_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw-implant_cmp_enc, ppolyf_u_res_l+dnwell_enc_poly+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw-gr_w-implant_cmp_enc, -dnwell_enc_poly-pcmp_gr2dnw-gr_w-implant_cmp_enc , ppolyf_u_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw+gr_w+implant_cmp_enc, ppolyf_u_res_l+dnwell_enc_poly+pcmp_gr2dnw+gr_w+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + ppolyf_u_res_cell.shapes(pplus).insert(pp_gr) + + else: + ppolyf_u_res_cell.shapes(pplus).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc , -poly_res_enc-ppoly_pcmp_spc+implant_cmp_enc, ppolyf_u_res_l+implant_cmp_enc)) + + + ppolyf_u_res_cell.flatten(True) + return ppolyf_u_res_cell + +def draw_ppolyf_u_high_Rs_res(layout, l, w , volt, deepnwell, pcmpgr): + ''' + Usage:- + used to draw high-Rs p+ poly resistor (outside DNWELL) by specifying parameters + Arguments:- + layout : Object of layout + l : Float of diff length + w : Float of diff width + ''' + + # Define layers + dnwell = layout.layer(12 , 0 ) + comp = layout.layer(22 , 0 ) + poly = layout.layer(30 , 0 ) + nplus = layout.layer(32 , 0 ) + pplus = layout.layer(31 , 0 ) + contact = layout.layer(33 , 0 ) + metal1 = layout.layer(34 , 0 ) + sab = layout.layer(49 , 0 ) + res_mk = layout.layer(110, 5 ) + resistor = layout.layer(62 , 0 ) + dualgate = layout.layer(55 , 0 ) + + # VARIABLES + dbu_PERCISION = 1/layout.dbu + ppolyf_u_high_Rs_res_w = w * dbu_PERCISION + ppolyf_u_high_Rs_res_l = l * dbu_PERCISION + poly_res_enc = 0.64 * dbu_PERCISION + sab_res_enc = 0.28 * dbu_PERCISION + sab_res_ext = 0.1 * dbu_PERCISION + implant_cmp_enc = 0.02 * dbu_PERCISION + implant_poly_enc = 0.18 * dbu_PERCISION + ppoly_pcmp_spc = 0.7 * dbu_PERCISION + pcmp_width = 0.42 * dbu_PERCISION + metal_width = 0.34 * dbu_PERCISION + met_cont_enc = 0.06 * dbu_PERCISION + comp_cont_enc = 0.07 * dbu_PERCISION + cont_size = 0.22 * dbu_PERCISION + cont_min_spc = 0.25 * dbu_PERCISION + cmp_met_cont_enc_diff = 0.01 * dbu_PERCISION + resistor_poly_enc = 0.4 * dbu_PERCISION + dnwell_enc_ncmp = 0.62 * dbu_PERCISION + dnwell_enc_poly = 1.34 * dbu_PERCISION + pcmp_gr2dnw = 2.5 * dbu_PERCISION + gr_w = 0.36 * dbu_PERCISION + dg_enc_dnwell = 0.5 * dbu_PERCISION + + if volt == "5/6V": + dnwell_enc_ncmp = 0.66 * dbu_PERCISION + + + # Inserting ppolyf_u_high_Rs_res cell + cell_index = layout.add_cell("ppolyf_u_high_Rs_resistor") + ppolyf_u_high_Rs_res_cell = layout.cell(cell_index) + + # Inserting a contact cell + cont_cell_index = layout.add_cell("contact") + cont_cell = layout.cell(cont_cell_index) + cont_cell.shapes(contact).insert(pya.Box.new(0, 0, cont_size, cont_size)) + + # Inserting res_mk + ppolyf_u_high_Rs_res_cell.shapes(res_mk).insert(pya.Box(0, 0, ppolyf_u_high_Rs_res_w, ppolyf_u_high_Rs_res_l)) + + # Inserting sab + ppolyf_u_high_Rs_res_cell.shapes(sab).insert(pya.Box(-sab_res_ext, -sab_res_enc, ppolyf_u_high_Rs_res_w+sab_res_ext, ppolyf_u_high_Rs_res_l+sab_res_enc)) + + # Inserting p poly + ppolyf_u_high_Rs_res_cell.shapes(poly).insert(pya.Box(-poly_res_enc, 0, ppolyf_u_high_Rs_res_w+poly_res_enc, ppolyf_u_high_Rs_res_l)) + ppolyf_u_high_Rs_res_cell.shapes(pplus).insert(pya.Box(-poly_res_enc-implant_poly_enc, -implant_poly_enc , 0 , ppolyf_u_high_Rs_res_l+implant_poly_enc)) + ppolyf_u_high_Rs_res_cell.shapes(pplus).insert(pya.Box(ppolyf_u_high_Rs_res_w, -implant_poly_enc , ppolyf_u_high_Rs_res_w+poly_res_enc+implant_poly_enc, ppolyf_u_high_Rs_res_l+implant_poly_enc)) + + # Inserting npoly metal + ppolyf_u_high_Rs_res_cell.shapes(metal1).insert(pya.Box(-poly_res_enc+cmp_met_cont_enc_diff , cmp_met_cont_enc_diff , -poly_res_enc+cmp_met_cont_enc_diff+metal_width , ppolyf_u_high_Rs_res_l-cmp_met_cont_enc_diff)) #left + ppolyf_u_high_Rs_res_cell.shapes(metal1).insert(pya.Box(ppolyf_u_high_Rs_res_w+poly_res_enc-cmp_met_cont_enc_diff-metal_width, cmp_met_cont_enc_diff , ppolyf_u_high_Rs_res_w+poly_res_enc-cmp_met_cont_enc_diff , ppolyf_u_high_Rs_res_l-cmp_met_cont_enc_diff)) # Right + + # Inserting npoly contacts + num_ncmp_left_con_1, ncmp_left_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_left_con_2, ncmp_left_con_free_spc_2 = number_spc_contacts(ppolyf_u_high_Rs_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_left_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-poly_res_enc+cmp_met_cont_enc_diff+ncmp_left_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_left_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_left_con_1, num_ncmp_left_con_2) + ppolyf_u_high_Rs_res_cell.insert(ncmp_left_con_arr) + + num_ncmp_right_con_1, ncmp_right_con_free_spc_1 = number_spc_contacts(metal_width, met_cont_enc, cont_min_spc, cont_size) + num_ncmp_right_con_2, ncmp_right_con_free_spc_2 = number_spc_contacts(ppolyf_u_high_Rs_res_l-2*cmp_met_cont_enc_diff, met_cont_enc, cont_min_spc, cont_size) + ncmp_right_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(ppolyf_u_high_Rs_res_w+poly_res_enc-cmp_met_cont_enc_diff-metal_width+ncmp_right_con_free_spc_1 / 2, cmp_met_cont_enc_diff+ncmp_right_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_ncmp_right_con_1, num_ncmp_right_con_2) + ppolyf_u_high_Rs_res_cell.insert(ncmp_right_con_arr) + + + # Inserting p diffusion + ppolyf_u_high_Rs_res_cell.shapes(comp).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width, 0, -poly_res_enc-ppoly_pcmp_spc, ppolyf_u_high_Rs_res_l)) + + # Inserting pcomp metal + ppolyf_u_high_Rs_res_cell.shapes(metal1).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width, 0, -poly_res_enc-ppoly_pcmp_spc, ppolyf_u_high_Rs_res_l)) + + # Inserting pcomp contacts + num_pcmp_con_1, pcmp_con_free_spc_1 = number_spc_contacts(pcmp_width, comp_cont_enc, cont_min_spc, cont_size) + num_pcmp_con_2, pcmp_con_free_spc_2 = number_spc_contacts(ppolyf_u_high_Rs_res_l, comp_cont_enc, cont_min_spc, cont_size) + pcmp_con_arr = pya.CellInstArray(cont_cell.cell_index(), pya.Trans( + pya.Point(-poly_res_enc-ppoly_pcmp_spc-pcmp_width+pcmp_con_free_spc_1 / 2, pcmp_con_free_spc_2/2)), + pya.Vector(cont_min_spc + cont_size, 0), pya.Vector(0,cont_min_spc + cont_size), + num_pcmp_con_1, num_pcmp_con_2) + ppolyf_u_high_Rs_res_cell.insert(pcmp_con_arr) + + # Inserting resistor + ppolyf_u_high_Rs_res_cell.shapes(resistor).insert(pya.Box(-poly_res_enc-resistor_poly_enc, -resistor_poly_enc , ppolyf_u_high_Rs_res_w+poly_res_enc+resistor_poly_enc, ppolyf_u_high_Rs_res_l+resistor_poly_enc)) + + if deepnwell == True: + # Inserting Ntap + ppolyf_u_high_Rs_res_cell.shapes(nplus).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc , -poly_res_enc-ppoly_pcmp_spc+implant_cmp_enc, ppolyf_u_high_Rs_res_l+implant_cmp_enc)) + + # Inserting dnwell + ppolyf_u_high_Rs_res_cell.shapes(dnwell).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp, -dnwell_enc_poly , ppolyf_u_high_Rs_res_w+poly_res_enc+dnwell_enc_poly, ppolyf_u_high_Rs_res_l+dnwell_enc_poly)) + + # for 5/6V + # Inserting dualgate + if volt == "5/6V": + ppolyf_u_high_Rs_res_cell.shapes(dualgate).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-dg_enc_dnwell, -dnwell_enc_poly-dg_enc_dnwell , ppolyf_u_high_Rs_res_w+poly_res_enc+dnwell_enc_poly+dg_enc_dnwell, ppolyf_u_high_Rs_res_l+dnwell_enc_poly+dg_enc_dnwell)) + + + # Inserting Guard Ring + if pcmpgr == True: + cmp_inner = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw, -dnwell_enc_poly-pcmp_gr2dnw , ppolyf_u_high_Rs_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw, ppolyf_u_high_Rs_res_l+dnwell_enc_poly+pcmp_gr2dnw) + cmp_outer = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw-gr_w, -dnwell_enc_poly-pcmp_gr2dnw-gr_w , ppolyf_u_high_Rs_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw+gr_w, ppolyf_u_high_Rs_res_l+dnwell_enc_poly+pcmp_gr2dnw+gr_w) + cmp_gr = pya.Region(cmp_outer) - pya.Region(cmp_inner) + ppolyf_u_high_Rs_res_cell.shapes(comp).insert(cmp_gr) + + pp_inner = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw+implant_cmp_enc, -dnwell_enc_poly-pcmp_gr2dnw+implant_cmp_enc , ppolyf_u_high_Rs_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw-implant_cmp_enc, ppolyf_u_high_Rs_res_l+dnwell_enc_poly+pcmp_gr2dnw-implant_cmp_enc) + pp_outer = pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-dnwell_enc_ncmp-pcmp_gr2dnw-gr_w-implant_cmp_enc, -dnwell_enc_poly-pcmp_gr2dnw-gr_w-implant_cmp_enc , ppolyf_u_high_Rs_res_w+poly_res_enc+dnwell_enc_poly+pcmp_gr2dnw+gr_w+implant_cmp_enc, ppolyf_u_high_Rs_res_l+dnwell_enc_poly+pcmp_gr2dnw+gr_w+implant_cmp_enc) + pp_gr = pya.Region(pp_outer) - pya.Region(pp_inner) + ppolyf_u_high_Rs_res_cell.shapes(pplus).insert(pp_gr) + + else: + ppolyf_u_high_Rs_res_cell.shapes(pplus).insert(pya.Box(-poly_res_enc-ppoly_pcmp_spc-pcmp_width-implant_cmp_enc, -implant_cmp_enc , -poly_res_enc-ppoly_pcmp_spc+implant_cmp_enc, ppolyf_u_high_Rs_res_l+implant_cmp_enc)) + + # for 5/6V + # Inserting dualgate + if volt == "5/6V": + ppolyf_u_high_Rs_res_cell.shapes(dualgate).insert(pya.Box(-poly_res_enc-resistor_poly_enc, -resistor_poly_enc , ppolyf_u_high_Rs_res_w+poly_res_enc+resistor_poly_enc, ppolyf_u_high_Rs_res_l+resistor_poly_enc)) + + + ppolyf_u_high_Rs_res_cell.flatten(True) + return ppolyf_u_high_Rs_res_cell diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/efuse.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/efuse.py new file mode 100644 index 000000000..af367195c --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/efuse.py @@ -0,0 +1,80 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +# EFuse Generator for GF180MCU +######################################################################################################################## + +import pya +from .draw_efuse import * + +class efuse(pya.PCellDeclarationHelper): + """ + eFuse Generator for GF180MCU + """ + + def __init__(self): + + # Important: initialize the super class + super(efuse, self).__init__() + self.param("Model", self.TypeString, "Model", default="gf180mcu_fd_pr__efuse",readonly=True) + self.param("array_x", self.TypeInt, "Elements in x_direction", default=1) + self.param("array_y", self.TypeInt, "Elements in y_direction", default=1) + self.param("x_spacing", self.TypeDouble, "Spacing in x_direction", default=1,unit="um") + self.param("y_spacing", self.TypeDouble, "Spacing in y_direction", default=1,unit="um") + + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "efuse" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the + # numeric parameter has changed (by comparing against the effective + # radius ru) and set ru to the effective radius. We also update the + # numerical value or the shape, depending on which on has not changed. + pass + + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + # return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + pass + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + # self.r = self.shape.bbox().width() * self.layout.dbu / 2 + # self.l = self.layout.get_info(self.layer) + pass + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + # return pya.Trans(self.shape.bbox().center()) + pass + + def produce_impl(self): + + # This is the main part of the implementation: create the layout + + self.percision = 1/self.layout.dbu + efuse_instance = draw_efuse(layout=self.layout) + write_cells = pya.CellInstArray(efuse_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*self.percision, 0), pya.Vector(0, self.y_spacing*self.percision),self.array_x , self.array_y) + + self.cell.flatten(1) + self.cell.insert(write_cells) + self.layout.cleanup() diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/efuse/efuse.gds b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/efuse/efuse.gds new file mode 100644 index 000000000..ff0bad5d8 Binary files /dev/null and b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/efuse/efuse.gds differ diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/mimcap.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/mimcap.py new file mode 100644 index 000000000..b907ef2ba --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/mimcap.py @@ -0,0 +1,97 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +# MIM Capacitor Generator for GF180MCU +######################################################################################################################## + +import pya +import os +from .draw_mimcap import * + +mim_l = 0.28 +mim_w = 0.28 + +class mimcap(pya.PCellDeclarationHelper): + """ + MIM capacitor Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(mimcap, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.Type_handle = self.param("mim_option", self.TypeList, "MIM-Option") + self.Type_handle.add_choice("MIM-A", "MIM-A") + self.Type_handle.add_choice("MIM-B", "MIM-B") + + self.Type_handle2 = self.param("metal_level", self.TypeList, "Metal level (MIM-B)") + self.Type_handle2.add_choice("M4", "M4") + self.Type_handle2.add_choice("M5", "M5") + self.Type_handle2.add_choice("M6", "M6") + + self.param("l", self.TypeDouble,"Length", default=mim_l, unit="um") + self.param("w", self.TypeDouble,"Width", default=mim_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "mimcap(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < mim_l: + self.l = mim_l + if (self.w) < mim_w: + self.w = mim_w + if (self.mim_option) == "MIM-A": + self.metal_level = "M3" + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + option = os.environ['GF_PDK_OPTION'] + if option == "A": + if (self.mim_option) == "MIM-B": + raise TypeError(f"Current stack ({option}) doesn't allow this option") + else: + if (self.mim_option) == "MIM-A": + raise TypeError(f"Current stack ({option}) doesn't allow this option") + np_instance = draw_mimcap(self.layout, self.l, self.w, self.mim_option , self.metal_level) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + + self.cell.insert(write_cells) + self.cell.flatten(1) diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/mos.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/mos.py new file mode 100644 index 000000000..f308bc272 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/mos.py @@ -0,0 +1,389 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +# MOSFET Generator for GF180MCU +######################################################################################################################## +import pya +from .draw_mos import * + +mos_3p3_l = 0.28 +mos_3p3_w = 0.22 +mos_5_6_w = 0.3 + +nmos_5p0_l = 0.6 +nmos_6p0_l = 0.7 + +pmos_5p0_l = 0.5 +pmos_6p0_l = 0.55 + +nmos_nat_l = 1.8 +nmos_nat_w = 0.8 +mos_grw = 0.36 +mos_ld = 0.44 + +ldmos_l_min = 0.6 +ldmos_l_max = 20 +ldmos_w_min = 4 +ldmos_w_max = 50 + +class nmos(pya.PCellDeclarationHelper): + """ + NMOS Generator for GF180MCU + """ + + def __init__(self): + # Initialize super class. + super(nmos, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Deep NWELL Guard Ring", default=0) + self.Type_handle = self.param("volt", self.TypeList, "Operating Voltage") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5V", "5V") + self.Type_handle.add_choice("6V", "6V") + self.Type_handle = self.param("bulk", self.TypeList, "Bulk Type") + self.Type_handle.add_choice("None", "None") + self.Type_handle.add_choice("Bulk Tie", "Bulk Tie") + self.Type_handle.add_choice("Guard Ring", "Guard Ring") + + self.param("w", self.TypeDouble, "Width", default=mos_3p3_w, unit="um") + self.param("l", self.TypeDouble, "Length", default=mos_3p3_l, unit="um") + self.param("ld", self.TypeDouble, "Diffusion Length", default=mos_ld, unit="um") + self.param("nf", self.TypeInt, "Number of Fingers", default=1) + self.param("grw", self.TypeDouble, "Guard Ring Width", default=mos_grw, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "nmos(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the + # numeric parameter has changed (by comparing against the effective + # radius ru) and set ru to the effective radius. We also update the + # numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if self.volt == "3.3V": + if (self.l) < mos_3p3_l: + self.l = mos_3p3_l + if (self.w) < mos_3p3_w: + self.w = mos_3p3_w + elif self.volt == "5V": + if (self.l) < nmos_5p0_l: + self.l = nmos_5p0_l + if (self.w) < mos_5_6_w: + self.w = mos_5_6_w + elif self.volt == "6V": + if (self.l) < nmos_6p0_l: + self.l = nmos_6p0_l + if (self.w) < mos_5_6_w: + self.w = mos_5_6_w + if (self.grw) < mos_grw: + self.grw = mos_grw + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + instance = draw_nmos(self.layout, self.l, self.w, self.ld, self.nf, self.grw, self.bulk, self.volt, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + self.cell.insert(write_cells) + self.cell.flatten(1) + +class pmos(pya.PCellDeclarationHelper): + """ + PMOS Generator for GF180MCU + """ + + def __init__(self): + # Initialize super class. + super(pmos, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Deep NWELL Guard Ring", default=0) + self.Type_handle = self.param("volt", self.TypeList, "Voltage area") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5V", "5V") + self.Type_handle.add_choice("6V", "6V") + self.Type_handle = self.param("bulk", self.TypeList, "Bulk Type") + self.Type_handle.add_choice("None", "None") + self.Type_handle.add_choice("Bulk Tie", "Bulk Tie") + self.Type_handle.add_choice("Guard Ring", "Guard Ring") + + self.param("w", self.TypeDouble, "Width", default=mos_3p3_w, unit="um") + self.param("l", self.TypeDouble, "Length", default=mos_3p3_l, unit="um") + self.param("ld", self.TypeDouble, "Diffusion Length", default=mos_ld, unit="um") + self.param("nf", self.TypeInt, "Number of Fingers", default=1) + self.param("grw", self.TypeDouble, "Guard Ring Width", default=mos_grw, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "pmos(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the + # numeric parameter has changed (by comparing against the effective + # radius ru) and set ru to the effective radius. We also update the + # numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if self.volt == "3.3V": + if (self.l) < mos_3p3_l: + self.l = mos_3p3_l + if (self.w) < mos_3p3_w: + self.w = mos_3p3_w + elif self.volt == "5V": + if (self.l) < pmos_5p0_l: + self.l = pmos_5p0_l + if (self.w) < mos_5_6_w: + self.w = mos_5_6_w + elif self.volt == "6V": + if (self.l) < pmos_6p0_l: + self.l = pmos_6p0_l + if (self.w) < mos_5_6_w: + self.w = mos_5_6_w + if (self.grw) < mos_grw: + self.grw = mos_grw + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + instance = draw_pmos(self.layout, self.l, self.w, self.ld, self.nf, self.grw, self.bulk, self.volt, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + self.cell.insert(write_cells) + self.cell.flatten(1) + +class nmos_6p0_nat(pya.PCellDeclarationHelper): + """ + 6V Native NMOS Generator for GF180MCU + """ + + def __init__(self): + # Initialize super class. + super(nmos_6p0_nat, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.Type_handle = self.param("bulk", self.TypeList, "Bulk Type") + self.Type_handle.add_choice("None", "None") + self.Type_handle.add_choice("Bulk Tie", "Bulk Tie") + self.Type_handle.add_choice("Guard Ring", "Guard Ring") + + self.param("w", self.TypeDouble, "Width", default=nmos_nat_w, unit="um") + self.param("l", self.TypeDouble, "Length", default=nmos_nat_l, unit="um") + self.param("ld", self.TypeDouble, "Diffusion Length", default=mos_ld, unit="um") + self.param("nf", self.TypeInt, "Number of Fingers", default=1) + self.param("grw", self.TypeDouble, "Guard Ring Width", default=mos_grw, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "nmos_6p0_nat(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the + # numeric parameter has changed (by comparing against the effective + # radius ru) and set ru to the effective radius. We also update the + # numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < nmos_nat_l: + self.l = nmos_nat_l + if (self.w) < nmos_nat_w: + self.w = nmos_nat_w + if (self.grw) < mos_grw: + self.grw = mos_grw + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + instance = draw_nmos_6p0_nat(self.layout, self.l, self.w, self.ld, self.nf, self.grw, self.bulk) + write_cells = pya.CellInstArray(instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + self.cell.insert(write_cells) + self.cell.flatten(1) + +class nmos_10p0_asym(pya.PCellDeclarationHelper): + """ + 10V LDNMOS Generator for GF180MCU + """ + + def __init__(self): + # Initialize super class. + super(nmos_10p0_asym, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + + self.param("w", self.TypeDouble, "Width", default=ldmos_w_min, unit="um") + self.param("l", self.TypeDouble, "Length", default=ldmos_l_min, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "nmos_10p0_asym(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the + # numeric parameter has changed (by comparing against the effective + # radius ru) and set ru to the effective radius. We also update the + # numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < ldmos_l_min: + self.l = ldmos_l_min + if (self.l) > ldmos_l_max: + self.l = ldmos_l_max + if (self.w) < ldmos_w_min: + self.w = ldmos_w_min + if (self.w) > ldmos_w_max: + self.w = ldmos_w_max + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + instance = draw_nmos_10p0_asym(self.layout, self.l, self.w) + write_cells = pya.CellInstArray(instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + self.cell.insert(write_cells) + self.cell.flatten(1) + +class pmos_10p0_asym(pya.PCellDeclarationHelper): + """ + 10V LDPMOS Generator for GF180MCU + """ + + def __init__(self): + # Initialize super class. + super(pmos_10p0_asym, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + + self.param("w", self.TypeDouble, "Width", default=ldmos_w_min, unit="um") + self.param("l", self.TypeDouble, "Length", default=ldmos_l_min, unit="um") + self.param("double_gr", self.TypeBoolean, "Double Guard Ring", default=1) + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "pmos_10p0_asym(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the + # numeric parameter has changed (by comparing against the effective + # radius ru) and set ru to the effective radius. We also update the + # numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < ldmos_l_min: + self.l = ldmos_l_min + if (self.l) > ldmos_l_max: + self.l = ldmos_l_max + if (self.w) < ldmos_w_min: + self.w = ldmos_w_min + if (self.w) > ldmos_w_max: + self.w = ldmos_w_max + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + instance = draw_pmos_10p0_asym(self.layout, self.l, self.w, self.double_gr) + write_cells = pya.CellInstArray(instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + self.cell.insert(write_cells) + self.cell.flatten(1) diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/moscap.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/moscap.py new file mode 100644 index 000000000..25e245bc3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/moscap.py @@ -0,0 +1,272 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +# MOS Capacitor Generator for GF180MCU +######################################################################################################################## + +import pya +from .draw_moscap import * + +nmoscap_l = 0.36 +nmoscap_w = 0.22 + +pmoscap_l = 0.36 +pmoscap_w = 0.22 + +nmoscap_b_l = 0.36 +nmoscap_b_w = 0.22 + +pmoscap_b_l = 0.36 +pmoscap_b_w = 0.22 + +class nmoscap(pya.PCellDeclarationHelper): + """ + NMOS capacitor (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(nmoscap, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.Type_handle = self.param("volt", self.TypeList, "Voltage area") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5/6V", "5/6V") + + self.param("l", self.TypeDouble,"Length", default=nmoscap_l, unit="um") + self.param("w", self.TypeDouble,"Width", default=nmoscap_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "nmoscap(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < nmoscap_l: + self.l = nmoscap_l + if (self.w) < nmoscap_w: + self.w = nmoscap_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + np_instance = draw_nmoscap(self.layout, self.l, self.w , self.volt, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class pmoscap(pya.PCellDeclarationHelper): + """ + 3.3V PMOS capacitor (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(pmoscap, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.Type_handle = self.param("volt", self.TypeList, "Voltage area") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5/6V", "5/6V") + + self.param("l", self.TypeDouble,"Length", default=pmoscap_l, unit="um") + self.param("w", self.TypeDouble,"Width", default=pmoscap_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "pmoscap(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < pmoscap_l: + self.l = pmoscap_l + if (self.w) < pmoscap_w: + self.w = pmoscap_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + np_instance = draw_pmoscap(self.layout, self.l, self.w , self.volt, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class nmoscap_b(pya.PCellDeclarationHelper): + """ + 3.3V NMOS capacitor (inside NWell) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(nmoscap_b, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.Type_handle = self.param("volt", self.TypeList, "Voltage area") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5/6V", "5/6V") + + self.param("l", self.TypeDouble,"Length", default=nmoscap_b_l, unit="um") + self.param("w", self.TypeDouble,"Width", default=nmoscap_b_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "nmoscap_b(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < nmoscap_b_l: + self.l = nmoscap_b_l + if (self.w) < nmoscap_b_w: + self.w = nmoscap_b_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + np_instance = draw_nmoscap_b(self.layout, self.l, self.w , self.volt) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class pmoscap_b(pya.PCellDeclarationHelper): + """ + 3.3V PMOS capacitor (inside Psub) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(pmoscap_b, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.Type_handle = self.param("volt", self.TypeList, "Voltage area") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5/6V", "5/6V") + + self.param("l", self.TypeDouble,"Length", default=pmoscap_b_l, unit="um") + self.param("w", self.TypeDouble,"Width", default=pmoscap_b_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "pmoscap_b(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < pmoscap_b_l: + self.l = pmoscap_b_l + if (self.w) < pmoscap_b_w: + self.w = pmoscap_b_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + np_instance = draw_pmoscap_b(self.layout, self.l, self.w , self.volt) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(0, 0), pya.Vector(0, 0), 1, 1) + + self.cell.insert(write_cells) + self.cell.flatten(1) diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/res.py b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/res.py new file mode 100644 index 000000000..a63ca8ee5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/cells/res.py @@ -0,0 +1,868 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +######################################################################################################################## +# Resistor Generator for GF180MCU +######################################################################################################################## + +import pya +import os +from .draw_res import * + +rm1_l = 0.23 +rm1_w = 0.23 + +rm2_3_l = 0.28 +rm2_3_w = 0.28 + +tm6k_l = 0.36 +tm6k_w = 0.36 + +tm9_11k_l = 0.44 +tm9_11k_w = 0.44 + +tm30k_l = 1.8 +tm30k_w = 1.8 + +nplus_s_l = 0.42 +nplus_s_w = 0.42 + +pplus_s_l = 0.42 +pplus_s_w = 0.42 + +nplus_u_l = 0.42 +nplus_u_w = 0.42 + +pplus_u_l = 0.42 +pplus_u_w = 0.42 + +nwell_l = 0.42 +nwell_w = 0.42 + +pwell_l = 0.42 +pwell_w = 0.42 + +npolyf_s_l = 0.42 +npolyf_s_w = 0.42 + +ppolyf_s_l = 0.42 +ppolyf_s_w = 0.42 + +npolyf_u_l = 0.42 +npolyf_u_w = 0.42 + +ppolyf_u_l = 0.42 +ppolyf_u_w = 0.42 + +ppolyf_u_h_res_l = 0.42 +ppolyf_u_h_res_w = 0.42 + +class metal_resistor(pya.PCellDeclarationHelper): + """ + 2-terminal Metal resistor Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(metal_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.Type_handle = self.param("res_type", self.TypeList, "Metal resistor type") + self.Type_handle.add_choice("rm1", "rm1") + self.Type_handle.add_choice("rm2", "rm2") + self.Type_handle.add_choice("rm3", "rm3") + self.Type_handle.add_choice("tm6k" , "tm6k" ) + self.Type_handle.add_choice("tm9k" , "tm9k" ) + self.Type_handle.add_choice("tm11k" , "tm11k" ) + self.Type_handle.add_choice("tm30k" , "tm30k" ) + + self.param("l", self.TypeDouble,"Width", default=rm1_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=rm1_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "metal_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.res_type) == "rm1": + if (self.l) < rm1_l: + self.l = rm1_l + if (self.w) < rm1_w: + self.w = rm1_w + + if (self.res_type) == "rm2" or (self.res_type) == "rm3": + if (self.l) < rm2_3_l: + self.l = rm2_3_l + if (self.w) < rm2_3_w: + self.w = rm2_3_w + + if (self.res_type) == "tm6k" : + if (self.l) < tm6k_l: + self.l = tm6k_l + if (self.w) < tm6k_w: + self.w = tm6k_w + + if (self.res_type) == "tm9k" or (self.res_type) == "tm11k": + if (self.l) < tm9_11k_l: + self.l = tm9_11k_l + if (self.w) < tm9_11k_w: + self.w = tm9_11k_w + + if (self.res_type) == "tm30k" : + if (self.l) < tm30k_l: + self.l = tm30k_l + if (self.w) < tm30k_w: + self.w = tm30k_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + option = os.environ['GF_PDK_OPTION'] + if option == "A": + if ((self.res_type) == "rm3") or ((self.res_type) == "tm6k") or ((self.res_type) == "tm9k") or ((self.res_type) == "tm11k"): + raise TypeError(f"Current stack ({option}) doesn't allow this option") + elif option == "B": + if ((self.res_type) == "tm6k") or ((self.res_type) == "tm9k") or ((self.res_type) == "tm30k"): + raise TypeError(f"Current stack ({option}) doesn't allow this option") + else: + if ((self.res_type) == "tm6k") or ((self.res_type) == "tm11k") or ((self.res_type) == "tm30k"): + raise TypeError(f"Current stack ({option}) doesn't allow this option") + np_instance = draw_metal_res(self.layout, self.l, self.w , self.res_type) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class nplus_s_resistor(pya.PCellDeclarationHelper): + """ + 3-terminal salicided n+ diffusion resistor (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(nplus_s_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.param("l", self.TypeDouble,"Width", default=nplus_s_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=nplus_s_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + self.param("sub", self.TypeBoolean, "Substrate terminal", default=1) + + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "nplus_s_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < nplus_s_l: + self.l = nplus_s_l + if (self.w) < nplus_s_w: + self.w = nplus_s_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + np_instance = draw_nplus_s_res(self.layout, self.l, self.w , self.sub, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class pplus_s_resistor(pya.PCellDeclarationHelper): + """ + 3-terminal salicided P+ diffusion resistor (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(pplus_s_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.param("l", self.TypeDouble,"Width", default=pplus_s_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=pplus_s_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "pplus_s_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < pplus_s_l: + self.l = pplus_s_l + if (self.w) < pplus_s_w: + self.w = pplus_s_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + np_instance = draw_pplus_s_res(self.layout, self.l, self.w, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class nplus_u_resistor(pya.PCellDeclarationHelper): + """ + 3-terminal unsalicided n+ diffusion resistor (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(nplus_u_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.param("l", self.TypeDouble,"Width", default=nplus_u_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=nplus_u_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + self.param("sub", self.TypeBoolean, "Substrate terminal", default=1) + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "nplus_u_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < nplus_u_l: + self.l = nplus_u_l + if (self.w) < nplus_u_w: + self.w = nplus_u_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + np_instance = draw_nplus_u_res(self.layout, self.l, self.w , self.sub, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class pplus_u_resistor(pya.PCellDeclarationHelper): + """ + 3-terminal salicided P+ diffusion resistor (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(pplus_u_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.param("l", self.TypeDouble,"Width", default=pplus_u_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=pplus_u_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "pplus_u_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < pplus_u_l: + self.l = pplus_u_l + if (self.w) < pplus_u_w: + self.w = pplus_u_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + np_instance = draw_pplus_u_res(self.layout, self.l, self.w, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class nwell_resistor(pya.PCellDeclarationHelper): + """ + 3-terminal Nwell resistor under STI (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(nwell_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("l", self.TypeDouble,"Width", default=nwell_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=nwell_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "nwell_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < nwell_l: + self.l = nwell_l + if (self.w) < nwell_w: + self.w = nwell_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + np_instance = draw_nwell_res(self.layout, self.l, self.w) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class pwell_resistor(pya.PCellDeclarationHelper): + """ + 3-terminal Pwell resistor under STI (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(pwell_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.param("l", self.TypeDouble,"Width", default=pwell_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=pwell_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "pwell_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < pwell_l: + self.l = pwell_l + if (self.w) < pwell_w: + self.w = pwell_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + np_instance = draw_pwell_res(self.layout, self.l, self.w, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class npolyf_s_resistor(pya.PCellDeclarationHelper): + """ + 3-terminal salicided n+ poly resistor (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(npolyf_s_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.param("l", self.TypeDouble,"Width", default=npolyf_s_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=npolyf_s_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "npolyf_s_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < npolyf_s_l: + self.l = npolyf_s_l + if (self.w) < npolyf_s_w: + self.w = npolyf_s_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + np_instance = draw_npolyf_s_res(self.layout, self.l, self.w, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class ppolyf_s_resistor(pya.PCellDeclarationHelper): + """ + 3-terminal salicided p+ poly resistor (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(ppolyf_s_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.param("l", self.TypeDouble,"Width", default=ppolyf_s_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=ppolyf_s_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "ppolyf_s_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < ppolyf_s_l: + self.l = ppolyf_s_l + if (self.w) < ppolyf_s_w: + self.w = ppolyf_s_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + np_instance = draw_ppolyf_s_res(self.layout, self.l, self.w, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class npolyf_u_resistor(pya.PCellDeclarationHelper): + """ + 3-terminal unsalicided n+ poly resistor (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(npolyf_u_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.param("l", self.TypeDouble,"Width", default=npolyf_u_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=npolyf_u_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "npolyf_u_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < npolyf_u_l: + self.l = npolyf_u_l + if (self.w) < npolyf_u_w: + self.w = npolyf_u_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + np_instance = draw_npolyf_u_res(self.layout, self.l, self.w, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class ppolyf_u_resistor(pya.PCellDeclarationHelper): + """ + 3-terminal unsalicided p+ poly resistor (Outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(ppolyf_u_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.param("l", self.TypeDouble,"Width", default=ppolyf_u_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=ppolyf_u_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "ppolyf_u_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < ppolyf_u_l: + self.l = ppolyf_u_l + if (self.w) < ppolyf_u_w: + self.w = ppolyf_u_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + np_instance = draw_ppolyf_u_res(self.layout, self.l, self.w, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) + +class ppolyf_u_high_Rs_resistor(pya.PCellDeclarationHelper): + """ + high-Rs p+ poly resistor (outside DNWELL) Generator for GF180MCU + """ + + def __init__(self): + + # Initializing super class. + super(ppolyf_u_high_Rs_resistor, self).__init__() + + #===================== PARAMETERS DECLARATIONS ===================== + self.param("deepnwell", self.TypeBoolean, "Deep NWELL", default=0) + self.param("pcmpgr", self.TypeBoolean, "Guard Ring", default=0) + self.Type_handle = self.param("volt", self.TypeList, "Voltage area") + self.Type_handle.add_choice("3.3V", "3.3V") + self.Type_handle.add_choice("5/6V", "5/6V") + + self.param("l", self.TypeDouble,"Width", default=ppolyf_u_h_res_l, unit="um") + self.param("w", self.TypeDouble,"Length", default=ppolyf_u_h_res_w, unit="um") + self.param("area", self.TypeDouble,"Area", readonly=True, unit="um^2") + self.param("perim", self.TypeDouble,"Perimeter", readonly=True, unit="um") + self.param("array_x", self.TypeInt,"Repeat X", default=1) + self.param("array_y", self.TypeInt,"Repeat Y", default=1) + self.param("x_spacing", self.TypeDouble,"spacing in x_direction", default=3, unit="um") + self.param("y_spacing", self.TypeDouble,"spacing in y_direction", default=3, unit="um") + + def display_text_impl(self): + # Provide a descriptive text for the cell + return "ppolyf_u_high_Rs_resistor(L=" + ('%.3f' % self.l) + ",W=" + ('%.3f' % self.w) + ")" + + def coerce_parameters_impl(self): + # We employ coerce_parameters_impl to decide whether the handle or the numeric parameter has changed. + # We also update the numerical value or the shape, depending on which on has not changed. + self.area = self.w * self.l + self.perim = 2*(self.w + self.l) + # w,l must be larger or equal than min. values. + if (self.l) < ppolyf_u_h_res_l: + self.l = ppolyf_u_h_res_l + if (self.w) < ppolyf_u_h_res_w: + self.w = ppolyf_u_h_res_w + + def can_create_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we can use any shape which + # has a finite bounding box + return self.shape.is_box() or self.shape.is_polygon() or self.shape.is_path() + + def parameters_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we set r and l from the shape's + # bounding box width and layer + self.r = self.shape.bbox().width() * self.layout.dbu / 2 + self.l = self.layout.get_info(self.layer) + + def transformation_from_shape_impl(self): + # Implement the "Create PCell from shape" protocol: we use the center of the shape's + # bounding box to determine the transformation + return pya.Trans(self.shape.bbox().center()) + + def produce_impl(self): + dbu_PERCISION = 1/self.layout.dbu + np_instance = draw_ppolyf_u_high_Rs_res(self.layout, self.l, self.w , self.volt, self.deepnwell, self.pcmpgr) + write_cells = pya.CellInstArray(np_instance.cell_index(), pya.Trans(pya.Point(0, 0)), + pya.Vector(self.x_spacing*dbu_PERCISION, 0), pya.Vector(0, self.y_spacing*dbu_PERCISION), self.array_x, self.array_y) + + self.cell.insert(write_cells) + self.cell.flatten(1) diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/gf180mcu.lym b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/gf180mcu.lym new file mode 100644 index 000000000..c819e2ea1 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/gf180mcu.lym @@ -0,0 +1,49 @@ + + + + + + pymacros + + + + true + false + + false + + + python + + + +import sys +import os + +technology_macros_path = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, technology_macros_path) + +from cells import gf180mcu + +# Instantiate and register the library +gf180mcu() + +print("## gf180mcu PDK Pcells loaded.") +print(sys.path) + + + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/testing/drc_test/Makefile b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/testing/drc_test/Makefile new file mode 100644 index 000000000..900157fb7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/testing/drc_test/Makefile @@ -0,0 +1,522 @@ +# Copyright 2022 GlobalFoundries PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +#========================================================================= +# ---------------------------------- DRC --------------------------------- +#========================================================================= + +SHELL := /bin/bash +Testing_DIR ?= $(shell pwd) +run_folder := $(shell date +'run_%Y_%m_%d_%H_%M') + + +.DEFAULT_GOAL := all + +all : test-DRC-pcell + +test-DRC-pcell: Add_run-dir test-DRC-bjt test-DRC-diode test-DRC-MIM test-DRC-MOSCAP test-DRC-MOS test-DRC-RES + +#================================= +# --------- RUN FOLDER ---------- +#================================= + +.ONESHELL: +Add_run-dir: + @cd $(Testing_DIR) + @ mkdir -p $(run_folder)/bjt_drc $(run_folder)/diode_drc $(run_folder)/mimcap_drc $(run_folder)/mosfet_drc $(run_folder)/moscap_drc $(run_folder)/res_drc + + +#================================= +# ---------- test-DRC-BJT -------- +#================================= + +.ONESHELL: +test-DRC-bjt: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for BJT pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/bjt_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/bjt_drc/bjt.log + @mv -f ../testcases/bjt_pcells*.lyrdb $(run_folder)/bjt_drc + + +#================================= +# -------- test-DRC-diode ------- +#================================= + +.ONESHELL: +test-DRC-diode: test-DRC-np_diode test-DRC-pn_diode test-DRC-np_dw_diode test-DRC-pn_dw_diode test-DRC-nwp_diode test-DRC-dnwpw_diode test-DRC-dnwps_diode test-DRC-sc_diode + +.ONESHELL: +test-DRC-np_diode: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for np_diode pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/np_diode_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/diode_drc/np_diode.log + @mv -f ../testcases/np_diode_pcells*.lyrdb $(run_folder)/diode_drc + + +.ONESHELL: +test-DRC-pn_diode: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pn_diode pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pn_diode_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/diode_drc/pn_diode.log + @mv -f ../testcases/pn_diode_pcells*.lyrdb $(run_folder)/diode_drc + + +.ONESHELL: +test-DRC-np_dw_diode: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for np_dw_diode pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/np_dw_diode_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/diode_drc/np_dw_diode.log + @mv -f ../testcases/np_dw_diode_pcells*.lyrdb $(run_folder)/diode_drc + + +.ONESHELL: +test-DRC-pn_dw_diode: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pn_dw_diode pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pn_dw_diode_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/diode_drc/pn_dw_diode.log + @mv -f ../testcases/pn_dw_diode_pcells*.lyrdb $(run_folder)/diode_drc + + +.ONESHELL: +test-DRC-nwp_diode: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nwp_diode pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nwp_diode_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/diode_drc/nwp_diode.log + @mv -f ../testcases/nwp_diode_pcells*.lyrdb $(run_folder)/diode_drc + + +.ONESHELL: +test-DRC-dnwpw_diode: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for dnwpw_diode pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/dnwpw_diode_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/diode_drc/dnwpw_diode.log + @mv -f ../testcases/dnwpw_diode_pcells*.lyrdb $(run_folder)/diode_drc + + +.ONESHELL: +test-DRC-dnwps_diode: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for dnwps_diode pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/dnwps_diode_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/diode_drc/dnwps_diode.log + @mv -f ../testcases/dnwps_diode_pcells*.lyrdb $(run_folder)/diode_drc + + +.ONESHELL: +test-DRC-sc_diode: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for sc_diode pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/sc_diode_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/diode_drc/sc_diode.log + @mv -f ../testcases/sc_diode_pcells*.lyrdb $(run_folder)/diode_drc + + +#================================= +# --------- test-DRC-MIM --------- +#================================= + +.ONESHELL: +test-DRC-MIM: test-DRC-MIM-A test-DRC-MIM-B + +.ONESHELL: +test-DRC-MIM-A: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for MIM-A pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/MIM-A_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mimcap_drc/mim_a_gfA.log + @mv -f ../testcases/MIM-A_pcells*.lyrdb $(run_folder)/mimcap_drc + + +.ONESHELL: +test-DRC-MIM-B: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for MIM-B pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/MIM-B_gfB_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mimcap_drc/mim_b_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/MIM-B_gfC_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mimcap_drc/mim_b_gfC.log + @mv -f ../testcases/MIM-B_gfB_pcells*.lyrdb $(run_folder)/mimcap_drc + + + +#================================= +# --------- test-DRC-MOS --------- +#================================= + +.ONESHELL: +test-DRC-MOS: test-DRC-nmos_3p3 test-DRC-nmos_5p0 test-DRC-nmos_6p0 test-DRC-pmos_3p3 test-DRC-pmos_5p0 test-DRC-pmos_6p0 test-DRC-nmos_3p3_dw test-DRC-nmos_5p0_dw test-DRC-nmos_6p0_dw test-DRC-pmos_3p3_dw test-DRC-pmos_5p0_dw test-DRC-pmos_6p0_dw test-DRC-nmos_6p0_nat test-DRC-nmos_10p0_asym test-DRC-pmos_10p0_asym + + +.ONESHELL: +test-DRC-nmos_3p3: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nmos_3p3 pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_3p3_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_3p3_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_3p3_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_3p3_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_3p3_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_3p3_gfC.log + @mv -f ../testcases/nmos_3p3_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-nmos_5p0: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nmos_5p0 pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_5p0_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_5p0_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_5p0_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_5p0_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_5p0_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_5p0_gfC.log + @mv -f ../testcases/nmos_5p0_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-nmos_6p0: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nmos_6p0 pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_6p0_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_6p0_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_6p0_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_6p0_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_6p0_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_6p0_gfC.log + @mv -f ../testcases/nmos_6p0_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-pmos_3p3: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pmos_3p3 pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_3p3_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_3p3_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_3p3_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_3p3_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_3p3_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_3p3_gfC.log + @mv -f ../testcases/pmos_3p3_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-pmos_5p0: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pmos_5p0 pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_5p0_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_5p0_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_5p0_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_5p0_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_5p0_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_5p0_gfC.log + @mv -f ../testcases/pmos_5p0_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-pmos_6p0: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pmos_6p0 pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_6p0_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_6p0_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_6p0_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_6p0_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_6p0_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_6p0_gfC.log + @mv -f ../testcases/pmos_6p0_pcells*.lyrdb $(run_folder)/mosfet_drc + +.ONESHELL: +test-DRC-nmos_3p3_dw: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nmos_3p3_dw pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_3p3_dw_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_3p3_dw_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_3p3_dw_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_3p3_dw_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_3p3_dw_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_3p3_dw_gfC.log + @mv -f ../testcases/nmos_3p3_dw_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-nmos_5p0_dw: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nmos_5p0_dw pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_5p0_dw_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_5p0_dw_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_5p0_dw_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_5p0_dw_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_5p0_dw_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_5p0_dw_gfC.log + @mv -f ../testcases/nmos_5p0_dw_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-nmos_6p0_dw: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nmos_6p0_dw pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_6p0_dw_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_6p0_dw_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_6p0_dw_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_6p0_dw_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_6p0_dw_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_6p0_dw_gfC.log + @mv -f ../testcases/nmos_6p0_dw_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-pmos_3p3_dw: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pmos_3p3_dw pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_3p3_dw_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_3p3_dw_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_3p3_dw_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_3p3_dw_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_3p3_dw_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_3p3_dw_gfC.log + @mv -f ../testcases/pmos_3p3_dw_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-pmos_5p0_dw: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pmos_5p0_dw pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_5p0_dw_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_5p0_dw_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_5p0_dw_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_5p0_dw_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_5p0_dw_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_5p0_dw_gfC.log + @mv -f ../testcases/pmos_5p0_dw_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-pmos_6p0_dw: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pmos_6p0_dw pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_6p0_dw_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_6p0_dw_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_6p0_dw_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_6p0_dw_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_6p0_dw_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_6p0_dw_gfC.log + @mv -f ../testcases/pmos_6p0_dw_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-nmos_6p0_nat: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nmos_6p0_nat pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_6p0_nat_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_6p0_nat_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_6p0_nat_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_6p0_nat_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_6p0_nat_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_6p0_nat_gfC.log + @mv -f ../testcases/nmos_6p0_nat_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-nmos_10p0_asym: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nmos_10p0_asym pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_10p0_asym_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_10p0_asym_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_10p0_asym_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_10p0_asym_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmos_10p0_asym_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/nmos_10p0_asym_gfC.log + @mv -f ../testcases/nmos_10p0_asym_pcells*.lyrdb $(run_folder)/mosfet_drc + + +.ONESHELL: +test-DRC-pmos_10p0_asym: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pmos_10p0_asym pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_10p0_asym_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_10p0_asym_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_10p0_asym_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_10p0_asym_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmos_10p0_asym_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/mosfet_drc/pmos_10p0_asym_gfC.log + @mv -f ../testcases/pmos_10p0_asym_pcells*.lyrdb $(run_folder)/mosfet_drc + + +#================================= +# ------- test-DRC-MOSCAP -------- +#================================= + +.ONESHELL: +test-DRC-MOSCAP: test-DRC-nmoscap test-DRC-pmoscap test-DRC-nmoscap_dw test-DRC-pmoscap_dw test-DRC-nmoscap_b test-DRC-pmoscap + +.ONESHELL: +test-DRC-nmoscap: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nmoscap pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmoscap_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/nmoscap_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmoscap_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/nmoscap_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmoscap_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/nmoscap_gfC.log + @mv -f ../testcases/nmoscap_pcells*.lyrdb $(run_folder)/moscap_drc + + +.ONESHELL: +test-DRC-pmoscap: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pmoscap pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmoscap_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/pmoscap_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmoscap_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/pmoscap_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmoscap_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/pmoscap_gfC.log + @mv -f ../testcases/pmoscap_pcells*.lyrdb $(run_folder)/moscap_drc + + +.ONESHELL: +test-DRC-nmoscap_dw: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nmoscap_dw pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmoscap_dw_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/nmoscap_dw_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmoscap_dw_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/nmoscap_dw_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmoscap_dw_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/nmoscap_dw_gfC.log + @mv -f ../testcases/nmoscap_dw_pcells*.lyrdb $(run_folder)/moscap_drc + + +.ONESHELL: +test-DRC-pmoscap_dw: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pmoscap_dw pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmoscap_dw_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/pmoscap_dw_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmoscap_dw_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/pmoscap_dw_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmoscap_dw_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/pmoscap_dw_gfC.log + @mv -f ../testcases/pmoscap_dw_pcells*.lyrdb $(run_folder)/moscap_drc + + +.ONESHELL: +test-DRC-nmoscap_b: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nmoscap_b pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmoscap_b_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/nmoscap_b_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmoscap_b_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/nmoscap_b_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nmoscap_b_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/nmoscap_b_gfC.log + @mv -f ../testcases/nmoscap_b_pcells*.lyrdb $(run_folder)/moscap_drc + + +.ONESHELL: +test-DRC-pmoscap_b: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pmoscap_b pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmoscap_b_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/pmoscap_b_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmoscap_b_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/pmoscap_b_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pmoscap_b_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/moscap_drc/pmoscap_b_gfC.log + @mv -f ../testcases/pmoscap_b_pcells*.lyrdb $(run_folder)/moscap_drc + + +#================================= +# --------- test-DRC-RES --------- +#================================= + +.ONESHELL: +test-DRC-RES: test-DRC-nplus_u_res test-DRC-nplus_s_res test-DRC-pplus_u_res test-DRC-pplus_s_res test-DRC-npolyf_u_res test-DRC-npolyf_s_res test-DRC-ppolyf_u_res \ + test-DRC-ppolyf_s_res test-DRC-ppolyf_u_high_Rs_res test-DRC-nwell_res test-DRC-pwell_res test-DRC-metal_res + +.ONESHELL: +test-DRC-nplus_u_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nplus_u_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nplus_u_resistor_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/nplus_u_res_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nplus_u_resistor_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/nplus_u_res_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nplus_u_resistor_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/nplus_u_res_gfC.log + @mv -f ../testcases/nplus_u_resistor_pcells*.lyrdb $(run_folder)/res_drc + + +.ONESHELL: +test-DRC-nplus_s_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nplus_s_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nplus_s_resistor_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/nplus_s_res_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nplus_s_resistor_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/nplus_s_res_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nplus_s_resistor_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/nplus_s_res_gfC.log + @mv -f ../testcases/nplus_s_resistor_pcells*.lyrdb $(run_folder)/res_drc + + +.ONESHELL: +test-DRC-pplus_u_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pplus_u_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pplus_u_resistor_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/pplus_u_res_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pplus_u_resistor_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/pplus_u_res_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pplus_u_resistor_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/pplus_u_res_gfC.log + @mv -f ../testcases/pplus_u_resistor_pcells*.lyrdb $(run_folder)/res_drc + + +.ONESHELL: +test-DRC-pplus_s_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pplus_s_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pplus_s_resistor_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/pplus_s_res_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pplus_s_resistor_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/pplus_s_res_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pplus_s_resistor_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/pplus_s_res_gfC.log + @mv -f ../testcases/pplus_s_resistor_pcells*.lyrdb $(run_folder)/res_drc + + +.ONESHELL: +test-DRC-npolyf_u_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for npolyf_u_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/npolyf_u_resistor_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/npolyf_u_res_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/npolyf_u_resistor_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/npolyf_u_res_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/npolyf_u_resistor_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/npolyf_u_res_gfC.log + @mv -f ../testcases/npolyf_u_resistor_pcells*.lyrdb $(run_folder)/res_drc + + +.ONESHELL: +test-DRC-npolyf_s_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for npolyf_s_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/npolyf_s_resistor_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/npolyf_s_res_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/npolyf_s_resistor_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/npolyf_s_res_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/npolyf_s_resistor_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/npolyf_s_res_gfC.log + @mv -f ../testcases/npolyf_s_resistor_pcells*.lyrdb $(run_folder)/res_drc + + +.ONESHELL: +test-DRC-ppolyf_u_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for ppolyf_u_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/ppolyf_u_resistor_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/ppolyf_u_res_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/ppolyf_u_resistor_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/ppolyf_u_res_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/ppolyf_u_resistor_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/ppolyf_u_res_gfC.log + @mv -f ../testcases/ppolyf_u_resistor_pcells*.lyrdb $(run_folder)/res_drc + + +.ONESHELL: +test-DRC-ppolyf_s_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for ppolyf_s_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/ppolyf_s_resistor_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/ppolyf_s_res_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/ppolyf_s_resistor_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/ppolyf_s_res_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/ppolyf_s_resistor_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/ppolyf_s_res_gfC.log + @mv -f ../testcases/ppolyf_s_resistor_pcells*.lyrdb $(run_folder)/res_drc + + +.ONESHELL: +test-DRC-ppolyf_u_high_Rs_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for ppolyf_u_high_Rs_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/ppolyf_u_high_Rs_resistor_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/ppolyf_u_high_Rs_res_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/ppolyf_u_high_Rs_resistor_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/ppolyf_u_high_Rs_res_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/ppolyf_u_high_Rs_resistor_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/ppolyf_u_high_Rs_res_gfC.log + @mv -f ../testcases/ppolyf_u_high_Rs_resistor_pcells*.lyrdb $(run_folder)/res_drc + + +.ONESHELL: +test-DRC-nwell_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for nwell_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nwell_resistor_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/nwell_res_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nwell_resistor_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/nwell_res_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/nwell_resistor_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/nwell_res_gfC.log + @mv -f ../testcases/nwell_resistor_pcells*.lyrdb $(run_folder)/res_drc + + +.ONESHELL: +test-DRC-pwell_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for pwell_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pwell_resistor_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/pwell_res_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pwell_resistor_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/pwell_res_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/pwell_resistor_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/pwell_res_gfC.log + @mv -f ../testcases/pwell_resistor_pcells*.lyrdb $(run_folder)/res_drc + + +.ONESHELL: +test-DRC-metal_res: Add_run-dir + @cd $(Testing_DIR) + @echo "===== test-DRC for metal_res pcells =====" + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/metal_resistor_rm1_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/metal_res_rm1_gfC.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/metal_resistor_rm2_3_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/metal_res_rm2_3_gfC.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/metal_resistor_tm30k_pcells.gds --gf180mcu=A --antenna --no_offgrid |& tee $(run_folder)/res_drc/metal_res_tm30k_gfA.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/metal_resistor_tm11k_pcells.gds --gf180mcu=B --antenna --no_offgrid |& tee $(run_folder)/res_drc/metal_res_tm11k_gfB.log + @python3 $(PDK_ROOT)/$(PDK)/run_drc.py --path=../testcases/metal_resistor_tm9k_pcells.gds --gf180mcu=C --antenna --no_offgrid |& tee $(run_folder)/res_drc/metal_res_tm9k_gfC.log + @mv -f ../testcases/metal_resistor_rm1_pcells*.lyrdb $(run_folder)/res_drc + @mv -f ../testcases/metal_resistor_rm2_3_pcells*.lyrdb $(run_folder)/res_drc + @mv -f ../testcases/metal_resistor_tm30k_pcells*.lyrdb $(run_folder)/res_drc + @mv -f ../testcases/metal_resistor_tm11k_pcells*.lyrdb $(run_folder)/res_drc + @mv -f ../testcases/metal_resistor_tm9k_pcells*.lyrdb $(run_folder)/res_drc + + +#========================== +# --------- HELP ---------- +#========================== + +# Help Target +help: + @echo "\n ==== The following are some of the valid targets for this Makefile ====\n" + @echo "... all (the default if no target is provided )" + @echo "... test-DRC-pcell (To run DRC for on all pcells )" + @echo "... test-DRC-bjt (To run DRC for on bjt pcells )" + @echo "... test-DRC-diode (To run DRC for on diode pcells )" + @echo "... test-DRC-MIM (To run DRC for on MIM pcells )" + @echo "... test-DRC-MOS (To run DRC for on MOS pcells )" + @echo "... test-DRC-MOSCAP (To run DRC for on MOSCAP pcells )" + @echo "... test-DRC-RES (To run DRC for on RES pcells )" + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/testing/testcases/MIM-A_pcells.gds b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/testing/testcases/MIM-A_pcells.gds new file mode 100644 index 000000000..da0fcda90 Binary files /dev/null and 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a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/testing/testcases/sc_diode_pcells.gds b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/testing/testcases/sc_diode_pcells.gds new file mode 100644 index 000000000..119e67da3 Binary files /dev/null and b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/pymacros/testing/testcases/sc_diode_pcells.gds differ diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/requirements.test.txt b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/requirements.test.txt new file mode 100644 index 000000000..39af1e5d7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/libs.tech/klayout/requirements.test.txt @@ -0,0 +1,4 @@ +docopt==0.6.2 +pandas==1.3.4 +sympy==1.9 +numpy==1.22.0 diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/meson.build b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/meson.build new file mode 100644 index 000000000..957629b13 --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/meson.build @@ -0,0 +1,33 @@ + +project( + 'pdk_gf180mcu_nsx2', + version: '0.1.0', + meson_version: '>= 1.2.0', + default_options: ['warning_level=3'] +) + +python = import('python') +py = python.find_installation('python3') +py_deps = py.dependency() + +pdks_dir = py.get_install_dir() / 'pdks' / 'gf180mcu_nsx2' + +find_py = 'find libs.tech/coriolis/gf180mcu_nsx2 -type f -name "*.py"' +res = run_command('sh', '-c', find_py, check:true) +py_files = res.stdout().strip().split('\n') + +py.install_sources( files(py_files), subdir: 'pdks/gf180mcu_nsx2' ) + +klayout_excluded = [ + 'drc/README.md', + 'lvs/README.md', + 'pymacros/README.md', + 'pymacros/testing/drc_test/Makefile', + 'requirements.test.txt', +] + +install_subdir( 'libs.tech/klayout' , + exclude_directories: ['pymacros/testing'], + exclude_files: klayout_excluded, + install_dir: pdks_dir ) + diff --git a/pdks/symbolic/nsxlib2/gf180mcu_nsx2/pyproject.toml b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/pyproject.toml new file mode 100644 index 000000000..1af03744d --- /dev/null +++ b/pdks/symbolic/nsxlib2/gf180mcu_nsx2/pyproject.toml @@ -0,0 +1,25 @@ +[project] +name = "pdk_gf180mcu_nsx2" +version = "0.1.0" +description = "GF180MCU nsxlib2 PDK for Coriolis EDA" +authors = [ { name = "Coriolis EDA Contributers" } ] +requires-python = ">= 3.8" + +[build-system] +requires = [ + "meson", + "meson-python", + "ninja", + "setuptools", + "cibuildwheel", + "build", + "pdm-backend" +] +build-backend = "mesonpy" + +[tool.meson] +build-dir = "build" + +[tool.cibuildwheel] +build = "cp310-*" +skip = ["cp36-*", "cp37-*", "pp*"] diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/README.models b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/README.models new file mode 100644 index 000000000..fe0208e0a --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/README.models @@ -0,0 +1,3 @@ +I got the p8_cmos_models.inc from https://analogicdesign.com/ +They provide some spice models for their books. + diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/Scmos2m1uSetup.py b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/Scmos2m1uSetup.py new file mode 100644 index 000000000..1ef6de20f --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/Scmos2m1uSetup.py @@ -0,0 +1,97 @@ + +import sys +import os +import socket +from pathlib import Path +from coriolis.designflow.task import ShellEnv + + +__all__ = [ 'Where', 'setupScmos2m1u_nsx2 ' ] + + +class Where ( object ): + + coriolisTop = None + allianceTop = None + cellsTop = None + checkToolkit = None + + def __init__ ( self, checkToolkit=None ): + if 'CORIOLIS_TOP' in os.environ: Where.coriolisTop = Path( os.environ['CORIOLIS_TOP'] ) + if 'ALLIANCE_TOP' in os.environ: Where.allianceTop = Path( os.environ['ALLIANCE_TOP'] ) + if 'CELLS_TOP' in os.environ: Where.cellsTop = Path( os.environ['CELLS_TOP'] ) + if Where.coriolisTop and not Where.allianceTop: Where.allianceTop = Where.coriolisTop + #print( Where.coriolisTop, Where.allianceTop ) + if not Where.coriolisTop: + print( 'technos.Where.__init__(): Unable to locate Coriolis top.' ) + if checkToolkit is None: + checkToolkit = Path.home() / 'coriolis-2.x' / 'src' / 'alliance-check-toolkit' + else: + if isinstance(checkToolkit,str): + checkToolkit = Path( checkToolkit ) + if not Where.cellsTop: + Where.cellsTop = checkToolkit / 'cells' + Where.checkToolkit = checkToolkit + if not Where.cellsTop and Where.allianceTop: + Where.cellsTop = Where.allianceTop / 'cells' + ShellEnv.ALLIANCE_TOP = Where.allianceTop.as_posix() + ShellEnv.MBK_CATA_LIB = '.:' + (Where.cellsTop / 'nsxlib2' ).as_posix() + + def __repr__ ( self ): + if not Where.coriolisTop: + return '' + return ''.format( Where.coriolisTop.as_posix() ) + + +def setupScmos2m1u_nsx2 ( checkToolkit=None ): + Where( checkToolkit ) + ShellEnv().export() + + pdkDir = Where.checkToolkit / 'dks' / 'scmos2m1u_nsx2' / 'libs.tech' + coriolisTechDir = pdkDir / 'coriolis' + if not pdkDir.is_dir(): + print( '[ERROR] technos.setupScmos2m1u_nsx2(): PDK directory do *not* exists:' ) + print( ' "{}"'.format(techDir.as_posix()) ) + sys.path.append( coriolisTechDir.as_posix() ) + + cellsTop = Where.checkToolkit / 'cells' + liberty = cellsTop / 'nsxlib2' / 'nsxlib2.lib' +# kdrcRules = pdkDir / 'klayout' / 'drc' / 'drc_SCMOS.lydrc' + + from coriolis import Cfg + from coriolis import Viewer + from coriolis import CRL + from coriolis.helpers import overlay, l, u, n + from coriolis.designflow.yosys import Yosys + from coriolis.designflow.klayout import DRC + from scmos2m1u_nsx2 import techno, nsxlib2 + techno.setup( coriolisTechDir ) + nsxlib2.setup( cellsTop ) + + with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.misc.minTraceLevel = 1900 + cfg.misc.maxTraceLevel = 3000 + cfg.katana.eventsLimit = 1000000 + cfg.katana.termSatReservedLocal = 6 + cfg.katana.termSatThreshold = 9 + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + Yosys.setLiberty( liberty ) +# DRC.setDrcRules( kdrcRules ) + ShellEnv.CHECK_TOOLKIT = Where.checkToolkit.as_posix() + + path = None + for pathVar in [ 'PATH', 'path' ]: + if pathVar in os.environ: + path = os.environ[ pathVar ] + os.environ[ pathVar ] = path + ':' + (Where.allianceTop / 'bin').as_posix() + break + + diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/__init__.py b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/__init__.py new file mode 100644 index 000000000..b87e091fc --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/__init__.py @@ -0,0 +1,5 @@ + +import os +from pathlib import Path + +path = Path( os.path.dirname(os.path.abspath(__file__)) ) diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/nsxlib2.py b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/nsxlib2.py new file mode 100644 index 000000000..d82e55edc --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/nsxlib2.py @@ -0,0 +1,217 @@ + +import sys +import os.path +from coriolis import Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, \ + BasicLayer, Cell, Net, Horizontal, Vertical, \ + Rectilinear, Box, Point, Instance, Transformation, \ + NetExternalComponents, Pad +import coriolis.Viewer +from coriolis.CRL import AllianceFramework, Environment, Gds, LefImport, \ + CellGauge, RoutingGauge, RoutingLayerGauge +from coriolis.helpers import l, u, n, overlay, io, ndaTopDir +from coriolis.helpers.overlay import CfgCache, UpdateSession +from coriolis.Anabatic import StyleFlags + + +__all__ = [ "setup" ] + + +def _routing (): + """ + Define the routing gauge along with the various P&R tool parameters. + """ + af = AllianceFramework.get() + db = DataBase.getDB() + tech = db.getTechnology() + rg = RoutingGauge.create('nsxlib2') + rg.setSymbolic( True ) + dirM1 = RoutingLayerGauge.Vertical + dirM2 = RoutingLayerGauge.Horizontal + netBuilderStyle = 'HV,3RL+' + routingStyle = StyleFlags.HV + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL1' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.PinOnly # layer usage + , 0 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 7.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL2' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 1 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL3' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 2 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL4' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 3 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 4.0) # wire width + , l( 4.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL5' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 4 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 4.0) # wire width + , l( 4.0) # perpandicular wire width + , l( 4.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL6' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.PowerSupply # layer usage + , 5 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(15.0) # track pitch + , l(12.0) # wire width + , l(12.0) # perpandicular wire width + , l( 4.0) # VIA side + , l( 8.0 ) )) # obstacle dW + af.addRoutingGauge( rg ) + af.setRoutingGauge( 'nsxlib2' ) + + cg = CellGauge.create( 'nsxlib2' + , 'METAL1' # pin layer name. + , l( 10.0) # pitch. + , l(100.0) # cell slice height. + , l( 10.0) # cell slice step. + ) + af.addCellGauge( cg ) + af.setCellGauge( 'nsxlib2' ) + + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + # Place & Route setup + cfg.viewer.minimumSize = 500 + cfg.viewer.pixelThreshold = 2 + cfg.lefImport.minTerminalWidth = 0.0 + cfg.crlcore.groundName = 'vss' + cfg.crlcore.powerName = 'vdd' + cfg.etesian.bloat = 'disabled' + cfg.etesian.aspectRatio = 1.00 + cfg.etesian.aspectRatio = [10, 1000] + cfg.etesian.spaceMargin = 0.10 + cfg.etesian.densityVariation = 0.05 + cfg.etesian.routingDriven = False + cfg.etesian.latchUpDistance = l(2000.0) + #cfg.etesian.diodeName = 'diode' + #cfg.etesian.antennaInsertThreshold = 0.50 + #cfg.etesian.antennaMaxWL = u(250.0) + cfg.etesian.feedNames = 'tie_x0,rowend_x0' + cfg.etesian.defaultFeed = 'tie_x0' + cfg.etesian.cell.zero = 'zero_x0' + cfg.etesian.cell.one = 'one_x0' + cfg.etesian.effort = 2 + cfg.etesian.effort = ( ('Fast' , 1) + , ('Standard', 2) + , ('High' , 3) + , ('Extreme' , 4) + ) + cfg.etesian.graphics = 2 + cfg.etesian.graphics = ( ('Show every step' , 1) + , ('Show lower bound', 2) + , ('Show result only', 3) + ) + cfg.anabatic.routingGauge = 'nsxlib2' + cfg.anabatic.cellGauge = 'nsxlib2' + cfg.anabatic.globalLengthThreshold = 30*l(100.0) + cfg.anabatic.saturateRatio = 0.90 + cfg.anabatic.saturateRp = 10 + cfg.anabatic.topRoutingLayer = 'METAL5' + cfg.anabatic.edgeLength = 192 + cfg.anabatic.edgeWidth = 32 + cfg.anabatic.edgeCostH = 9.0 + cfg.anabatic.edgeCostK = -10.0 + cfg.anabatic.edgeHInc = 1.0 + cfg.anabatic.edgeHScaling = 1.0 + cfg.anabatic.globalIterations = 10 + cfg.anabatic.globalIterations = [ 1, 100 ] + cfg.anabatic.gcell.displayMode = 1 + cfg.anabatic.gcell.displayMode = (("Boundary", 1), ("Density", 2)) + cfg.anabatic.netBuilderStyle = netBuilderStyle + cfg.anabatic.routingStyle = routingStyle + cfg.katana.disableStackedVias = False + cfg.katana.hTracksReservedLocal = 4 + cfg.katana.hTracksReservedLocal = [0, 20] + cfg.katana.vTracksReservedLocal = 3 + cfg.katana.vTracksReservedLocal = [0, 20] + cfg.katana.termSatReservedLocal = 8 + cfg.katana.termSatThreshold = 9 + cfg.katana.eventsLimit = 4000002 + cfg.katana.ripupCost = 3 + cfg.katana.ripupCost = [0, None] + cfg.katana.strapRipupLimit = 16 + cfg.katana.strapRipupLimit = [1, None] + cfg.katana.localRipupLimit = 9 + cfg.katana.localRipupLimit = [1, None] + cfg.katana.globalRipupLimit = 5 + cfg.katana.globalRipupLimit = [1, None] + cfg.katana.longGlobalRipupLimit = 5 + cfg.chip.padCoreSide = 'North' + # Plugins setup + cfg.clockTree.minimumSide = l(100.0) * 6 + cfg.clockTree.buffer = 'buf_x8' + cfg.clockTree.placerEngine = 'Etesian' + cfg.block.spareSide = 10*l(100.0) + cfg.spares.buffer = 'buf_x8' + cfg.spares.maxSinks = 31 + + +def _loadNsxlib2 ( cellsTop ): + """ + Setup for NSXLIB2 Alliance library. It is an symbolic library + from which cells are loaded on demand, so we only setup pathes. + + :param cellsTop: The top directory containing the cells views. + """ + af = AllianceFramework.get() + env = af.getEnvironment() + env.setSCALE_X ( 100 ) + env.setCATALOG ( 'CATAL' ) + env.setPOWER ( 'vdd' ) + env.setGROUND ( 'vss' ) + env.setCLOCK ( '^ck$|m_clock|^clk$' ) + env.setBLOCKAGE( 'blockage[Nn]et.*' ) + env.setPad ( '.*_mpx$' ) + env.setRegister( 'sff.*' ) + env.setWORKING_LIBRARY( '.' ) + env.addSYSTEM_LIBRARY ( library=(cellsTop / 'nsxlib2').as_posix(), mode=Environment.Append ) + + +def setup ( cellsTop ): + _routing() + _loadNsxlib2( cellsTop ) diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/p8_cmos_models.inc b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/p8_cmos_models.inc new file mode 100644 index 000000000..76892b108 --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/p8_cmos_models.inc @@ -0,0 +1,30 @@ +********************************************************************** +* SPICE MOSFET Models used in Analog Integrated Circuit Design by Johns & +* Martin +* +* Usage: +* .include cmos_models.inc +********************************************************************** + +.MODEL nmos NMOS LEVEL=8 TOX=1.8E-8 LD=0.08U ++ UO=500 VMAX=2.0E5 PHI=0.6 ++ GAMMA=0.5 NSUB=2.5E16 VTO=0.8 ++ NFS=8.2E11 CGSO=2.5E-10 CGBO=2.5E-10 ++ CJSW=2.5E-10 CGDO=2.5E-10 MJ=0.5 ++ CJ=2.5E-4 PB=0.9 IS=1.0E-16 ++ JS=1.0E-4 KF=600E-27 AF=0.8 ++ RS=600 RD=600 ++ ETA=0.05 KAPPA=0.007 THETA=0.06 ++ XJ=2.7E-7 DELTA=0.7 + +.MODEL pmos PMOS LEVEL=8 TOX=1.8E-8 LD=0.08U ++ UO=165 VMAX=2.7E5 PHI=0.80 ++ GAMMA=0.75 NSUB=5.5E16 VTO=-0.9 ++ NFS=7.6E11 CGSO=2.5E-10 CGBO=2.75E-10 ++ CJSW=3.4E-10 CGDO=2.5E-10 MJ=0.5 ++ CJ=3.7E-4 PB=0.8 IS=1.0E-16 ++ JS=1.0E-4 KF=400E-27 AF=1.0 ++ RS=1200 RD=1200 ++ ETA=0.12 KAPPA=1.5 THETA=0.135 ++ XJ=2.3E-7 DELTA=0.3 + diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/scmos2m1u.rds b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/scmos2m1u.rds new file mode 100644 index 000000000..e726634b3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/scmos2m1u.rds @@ -0,0 +1,1408 @@ + +# ================================================================== +# COPYRIGHT IS UNCERTAIN YET. +# +# This file is a derived from the Alliance cmos.rds, adapted by +# Graham Petley for 0.13um and finally to MOSIS scn6m_deep by +# Naohiko Shimizu. It is a 2lambdas rules. +# This file is a template for MOSIS DEEP where lambda is set 1.0. +# You can scale the lambda and other RDS parameters as wish. +# +# To be used with the nsxlib library. +# +# +##------------------------------------------------------------------- +# PHYSICAL_GRID : +##------------------------------------------------------------------- + +DEFINE PHYSICAL_GRID 0.01 + +##------------------------------------------------------------------- +# LAMBDA : +##------------------------------------------------------------------- + +DEFINE LAMBDA 0.5 + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_SEGMENT : +# +# MBK RDS layer 1 RDS layer 2 +# name name TRANS DLR DWR OFFSET name TRANS DLR DWR OFFSET ... +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_SEGMENT + + PWELL RDS_PWELL VW 0.00 0.0 0.0 ALL + + NWELL RDS_NWELL VW 0.00 0.0 0.0 ALL \ + RDS_PIMP VW 0.00 -5.0 2.0 ALL \ + RDS_NIMP VW 0.00 -10.0 25.5 ALL + + NDIF RDS_NDIF VW -1.00 0.0 0.0 ALL \ + RDS_ACTIV VW -1.00 0.0 0.0 DRC + PDIF RDS_PDIF VW -1.00 0.0 0.0 ALL \ + RDS_ACTIV VW -1.00 0.0 0.0 DRC + + NTIE RDS_NTIE VW 0.00 0.00 0.0 EXT \ + RDS_NTIE VW 0.00 0.00 0.0 DRC \ + RDS_ACTIV VW 0.00 0.00 0.0 DRC \ + RDS_NIMP VW 1.00 2.00 0.0 DRC + PTIE RDS_PTIE VW 0.00 0.00 0.0 EXT \ + RDS_PTIE VW 0.00 0.00 0.0 DRC \ + RDS_ACTIV VW 0.00 0.00 0.0 DRC \ + RDS_PIMP VW 1.00 2.00 0.0 DRC + +# The GATE layer is the poly which makes the +# transistor. It is used to measure the ENDCAP +# value. + NTRANS RDS_POLY VW 0.25 0.00 0.0 ALL \ + RDS_GATE VW 0.25 0.00 0.0 DRC \ + RDS_NDIF LCW -1.00 2.00 0.0 EXT \ + RDS_NDIF RCW -1.00 2.00 0.0 EXT \ + RDS_NDIF VW -1.00 4.00 0.0 DRC \ + RDS_ACTIV VW -1.00 4.00 0.0 ALL + PTRANS RDS_POLY VW 0.25 0.00 0.0 ALL \ + RDS_GATE VW 0.25 0.00 0.0 DRC \ + RDS_PDIF LCW -1.00 2.00 0.0 EXT \ + RDS_PDIF RCW -1.00 2.00 0.0 EXT \ + RDS_PDIF VW -1.00 4.00 0.0 DRC \ + RDS_ACTIV VW -1.00 4.00 0.0 ALL + + POLY RDS_POLY VW 0.00 0.00 0.0 ALL + + + ALU1 RDS_ALU1 VW 0.00 0.00 0.0 ALL + +# Layers VALU2-VALU6 and TALU2-TALU6 are used to +# check for the end overlap of the metal to via. + ALU2 RDS_ALU2 VW 0.000 0.00 0.0 ALL + ALU3 RDS_ALU3 VW 0.000 0.00 0.0 ALL + ALU4 RDS_ALU4 VW 0.000 0.00 0.0 ALL + + CALU1 RDS_ALU1 VW 0.00 0.0 0.0 ALL + CALU2 RDS_ALU2 VW 0.000 0.0 0.0 ALL + CALU3 RDS_ALU3 VW 0.000 0.0 0.0 ALL + CALU4 RDS_ALU4 VW 0.000 0.0 0.0 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_CONNECTOR : +# +# MBK RDS layer +# name name DER DWR +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_CONNECTOR + + POLY RDS_POLY 0.00 0.00 + ALU1 RDS_ALU1 0.00 0.00 + ALU2 RDS_ALU2 0.00 0.00 + ALU3 RDS_ALU3 0.00 0.00 + ALU4 RDS_ALU4 0.00 0.00 + ALU5 RDS_ALU5 0.00 0.00 + ALU6 RDS_ALU6 0.00 0.00 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_REFERENCE : +# +# MBK ref RDS layer +# name name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_REFERENCE + + REF_REF RDS_REF 2.00 + REF_CON RDS_VALU1 2.00 RDS_TVIA1 2.00 RDS_TALU2 2.00 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_VIA : +# +# MBK via RDS layer 1 RDS layer 2 RDS layer 3 RDS layer 4 +# name name width name width name width name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_VIA +# The NIMP/PIMP layers are not visualised in Graal. If you want to +# see the layers, change the keyword for NIMP/PIMP from DRC to ALL. + + CONT_BODY_P\ + RDS_PTIE 2.00 DRC\ + RDS_PTIE 2.00 EXT\ + RDS_CONT 1.00 ALL\ + RDS_ALU1 2.00 ALL\ + RDS_ACTIV 2.00 DRC\ + RDS_PIMP 4.00 DRC + CONT_BODY_N\ + RDS_NTIE 2.00 DRC\ + RDS_NTIE 2.00 EXT\ + RDS_CONT 1.00 ALL\ + RDS_ALU1 2.00 ALL\ + RDS_ACTIV 2.00 DRC\ + RDS_NIMP 4.00 DRC + CONT_DIF_N\ + RDS_NDIF 2.00 ALL\ + RDS_CONT 1.00 ALL\ + RDS_ALU1 2.00 ALL\ + RDS_ACTIV 2.00 DRC\ + RDS_NIMP 4.00 DRC + CONT_DIF_P\ + RDS_PDIF 2.00 ALL\ + RDS_CONT 1.00 ALL\ + RDS_ALU1 2.00 ALL\ + RDS_ACTIV 2.00 DRC\ + RDS_PIMP 4.00 DRC + CONT_POLY\ + RDS_POLY 2.00 ALL\ + RDS_CONT 1.00 ALL\ + RDS_ALU1 2.00 ALL + CONT_VIA\ + RDS_ALU1 2.00 ALL\ + RDS_VIA1 1.00 ALL\ + RDS_ALU2 2.00 ALL + CONT_VIA2\ + RDS_ALU2 2.00 ALL\ + RDS_VIA2 1.00 ALL\ + RDS_ALU3 2.00 ALL + CONT_VIA3\ + RDS_ALU3 2.00 ALL\ + RDS_VIA3 1.00 ALL\ + RDS_ALU4 2.00 ALL + C_X_N\ + RDS_POLY 2.00 ALL\ + RDS_NDIF 1.00 ALL\ + RDS_ACTIV 1.00 ALL + C_X_P\ + RDS_POLY 2.00 ALL\ + RDS_PDIF 1.00 ALL\ + RDS_ACTIV 1.00 ALL +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_HOLE : +# +# MBK via RDS Hole +# name name side step mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_HOLE + +CONT_VIA RDS_VIA1 1.00 2.00 ALL +CONT_VIA2 RDS_VIA2 1.00 2.00 ALL +CONT_VIA3 RDS_VIA3 1.00 2.00 ALL +CONT_VIA4 RDS_VIA4 1.00 2.00 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_METAL : +# +# MBK via RDS layer 1 ... +# name name delta-width overlap mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_METAL + +CONT_VIA RDS_ALU2 0.0 2.00 ALL RDS_ALU2 0.0 2.00 ALL +CONT_VIA2 RDS_ALU2 0.0 2.00 ALL RDS_ALU3 0.0 2.00 ALL +CONT_VIA3 RDS_ALU3 0.0 2.00 ALL RDS_ALU4 0.0 2.00 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_TURNVIA : +# +# MBK via RDS layer 1 ... +# name name DWR MODE +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_TURNVIA + +CONT_TURN1 RDS_ALU1 0.50 ALL +CONT_TURN2 RDS_ALU2 0.50 ALL +CONT_TURN3 RDS_ALU3 0.50 ALL +CONT_TURN4 RDS_ALU4 0.50 ALL + +END + +TABLE MBK_WIRESETTING +X_GRID 10 +Y_GRID 10 +Y_SLICE 100 +WIDTH_VDD 12 +WIDTH_VSS 12 +TRACK_WIDTH_ALU8 0 +TRACK_WIDTH_ALU7 4 +TRACK_WIDTH_ALU6 4 +TRACK_WIDTH_ALU5 4 +TRACK_WIDTH_ALU4 3 +TRACK_WIDTH_ALU3 3 +TRACK_WIDTH_ALU2 3 +TRACK_WIDTH_ALU1 3 +TRACK_SPACING_ALU8 0 +TRACK_SPACING_ALU7 4 +TRACK_SPACING_ALU6 4 +TRACK_SPACING_ALU5 4 +TRACK_SPACING_ALU4 4 +TRACK_SPACING_ALU3 4 +TRACK_SPACING_ALU2 4 +TRACK_SPACING_ALU1 3 +WMIN_ALU1 3 +WMIN_ALU2 3 +DMIN_ALU1_ALU1 5 +DMIN_ALU2_ALU2 5 +WVIA_ALU1 5 +WVIA_ALU2 5 +EXTENSION_ALU2 1 +BV_VIA_VIA 8 +WALIM 60 +END + + +##------------------------------------------------------------------- +# TABLE LYNX_GRAPH : +# +# RDS layer Rds layer 1 Rds layer 2 ... +# name name name ... +##------------------------------------------------------------------- + +TABLE LYNX_GRAPH + +##--------------------------- + + RDS_NDIF RDS_CONT RDS_NDIF + RDS_PDIF RDS_CONT RDS_PDIF + RDS_NTIE RDS_CONT RDS_NTIE + RDS_PTIE RDS_CONT RDS_PTIE + + RDS_POLY RDS_CONT RDS_POLY + RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT + RDS_ALU1 RDS_CONT RDS_VIA1 RDS_ALU1 + + RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 + RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 + RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 + RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 + RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 + RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2 + RDS_ALU3 RDS_VIA2 RDS_VIA3 RDS_ALU3 + RDS_ALU4 RDS_VIA3 RDS_VIA4 RDS_ALU4 + RDS_ALU5 RDS_VIA4 RDS_VIA5 RDS_ALU5 + RDS_ALU6 RDS_VIA5 RDS_ALU6 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_CAPA : +# +# RDS layer Surface capacitance Perimetric capacitance +# name piF / Micron^2 piF / Micron +##------------------------------------------------------------------- + +TABLE LYNX_CAPA +# poly alu0 alu1 alu2 alu3 alu4 alu5 alu6 +# pitch 7 14 14 16 16 16 16 36 + RDS_POLY 10.10E-05 10.00e-05 + RDS_ALU1 3.400e-05 5.300e-05 + RDS_ALU2 1.400e-05 3.600e-05 + RDS_ALU3 0.900e-05 2.900e-05 + RDS_ALU4 0.700e-05 2.400e-05 + RDS_ALU5 0.500e-05 2.100e-05 + RDS_ALU6 0.400e-05 1.900e-05 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_RESISTOR : +# +# RDS layer Surface resistor +# name Ohm / Micron^2 +##------------------------------------------------------------------- + +TABLE LYNX_RESISTOR + + RDS_POLY 8.3 + RDS_ALU1 0.08 + RDS_ALU2 0.08 + RDS_ALU3 0.08 + RDS_ALU4 0.08 + RDS_ALU5 0.07 + RDS_ALU6 0.01 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_TRANSISTOR : +# +# MBK layer Transistor Type MBK via +# name name name +##------------------------------------------------------------------- + +TABLE LYNX_TRANSISTOR + + NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL + PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL + +END + +##------------------------------------------------------------------- +# TABLE LYNX_DIFFUSION : +# +# RDS layer RDS layer +# name name +##------------------------------------------------------------------- + +TABLE LYNX_DIFFUSION +END + +##------------------------------------------------------------------- +# TABLE LYNX_BULK_IMPLICIT : +# +# RDS layer Bulk type +# name EXPLICIT/IMPLICIT +##------------------------------------------------------------------- + +TABLE LYNX_BULK_IMPLICIT +END + + + +##------------------------------------------------------------------- +# TABLE S2R_OVERSIZE_DENOTCH : +##------------------------------------------------------------------- + +TABLE S2R_OVERSIZE_DENOTCH + RDS_NWELL 0.0 + RDS_PWELL 0.0 + RDS_ACTIV 0.0 + RDS_PDIF 0.0 + RDS_NDIF 0.0 + RDS_NTIE 0.0 + RDS_PTIE 0.0 +# The NIMP and PIMP values are used to set the width of WELL and +# IMPlant beyond the Abox. Values set equal to the NIMP/PIMP +# overlap of TIE contact so that thin slivers of IMPlant are not +# inserted between the TIE implant and well edge. + RDS_PIMP 0.0 + RDS_NIMP 0.0 +# Denotch NIMP and PIMP with user layers allowing single implant +# contact between two implant edges. +# Width is (2.5+6.2a)*2+6.1=(0.20+0.08)*2+0.16=0.72. Denotch just below. + RDS_POLY 0.0 + RDS_ALU1 0.0 + RDS_ALU2 0.0 + RDS_ALU3 0.0 + RDS_ALU4 0.0 + RDS_ALU5 0.0 + RDS_ALU6 0.0 +END + +##------------------------------------------------------------------- +# TABLE S2R_BLOC_RING_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_BLOC_RING_WIDTH +END + +##------------------------------------------------------------------- +# TABLE S2R_MINIMUM_LAYER_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_MINIMUM_LAYER_WIDTH + + RDS_NWELL 5.0 + RDS_PWELL 5.0 + RDS_NDIF 1.5 + RDS_PDIF 1.5 + RDS_NTIE 1.5 + RDS_PTIE 1.5 + RDS_PIMP 3.5 + RDS_NIMP 3.5 + RDS_POLY 1.0 + RDS_CONT 1.0 + RDS_ALU1 1.5 + RDS_VIA1 1.0 + RDS_ALU2 1.5 + RDS_VIA2 1.0 + RDS_ALU3 3.0 + RDS_VIA3 1.0 + RDS_ALU4 3.0 + RDS_VIA4 3.0 + RDS_REF 2.0 + +END + +##------------------------------------------------------------------- +# TABLE CIF_LAYER : +##------------------------------------------------------------------- + +TABLE CIF_LAYER +# Layer definitions used by MOSIS +#-------------------------------- + RDS_NWELL CWN + RDS_PWELL CWP + RDS_NDIF CND + RDS_PDIF CPD +# PTIE and NTIE actually provide the implants +# around the cutouts for CONT_BODY_N and _P. + RDS_PTIE CSP + RDS_NTIE CSN + RDS_ACTIV CAA + RDS_PIMP CSP + RDS_NIMP CSN + RDS_POLY CPG + RDS_CONT CCC + RDS_ALU1 CM1 + RDS_VIA1 CV1 + RDS_ALU2 CM2 + RDS_VIA2 CV2 + RDS_ALU3 CM3 + RDS_VIA3 CV3 + RDS_ALU4 CM4 + RDS_VIA4 CV4 + RDS_REF REF +# RDS_TALU8 AB + +# Layer definitions used by Alliance +#----------------------------------- +# RDS_NWELL LNWELL +# RDS_PWELL LPWELL +# RDS_NDIF LNDIF +# RDS_PDIF LPDIF +# RDS_TPOLY LTPOLY +# RDS_VPOLY LVPOLY +# RDS_NTIE LNTIE +# RDS_PTIE LPTIE +# RDS_PIMP LPIMP +# RDS_NIMP LNIMP +# RDS_POLY LPOLY +# RDS_POLY2 LPOLY2 +# RDS_CONT LCONT +# RDS_POLY2 LALU1 +# RDS_ALU1 LALU1 +# RDS_TALU1 LTALU1 +# RDS_VIA1 LVIA +# RDS_ALU2 LALU2 +# RDS_TALU2 LTALU2 +# RDS_VIA2 LVIA2 +# RDS_ALU3 LALU3 +# RDS_TALU3 LTALU3 +# RDS_VIA3 LVIA3 +# RDS_ALU4 LALU4 +# RDS_TALU4 LTALU4 +# RDS_VIA4 LVIA4 +# RDS_REF LREF +END + +##------------------------------------------------------------------- +# TABLE GDS_LAYER : +##------------------------------------------------------------------- + +TABLE GDS_LAYER +# Layer definitions used by MOSIS +#-------------------------------- + RDS_PWELL 41 0 + RDS_NWELL 42 0 + RDS_NDIF 43 0 + RDS_PDIF 43 0 + RDS_PTIE 44 0 + RDS_NTIE 45 0 + RDS_ACTIV 43 0 + RDS_PIMP 44 0 + RDS_NIMP 45 0 + RDS_POLY 46 0 46 + RDS_CONT 25 0 +# RDS_POLY2 49 49 + RDS_ALU1 49 0 49 5 + RDS_VIA1 50 0 + RDS_ALU2 51 0 51 5 + RDS_VIA2 61 0 + RDS_ALU3 62 0 62 5 + RDS_VIA3 30 0 + RDS_ALU4 31 0 31 5 + RDS_VIA4 32 0 +# RDS_REF 24 +# RDS_TALU8 63 + +END + +##------------------------------------------------------------------- +# TABLE S2R_POST_TREAT : +##------------------------------------------------------------------- + +TABLE S2R_POST_TREAT + + RDS_NWELL TREAT NULL + RDS_PWELL TREAT NULL + RDS_NDIF TREAT NULL + RDS_PDIF TREAT NULL + RDS_NTIE TREAT NULL + RDS_PTIE TREAT NULL + RDS_NIMP TREAT NULL + RDS_PIMP TREAT NULL + RDS_ACTIV TREAT NULL + RDS_POLY TREAT NULL + RDS_CONT NOTREAT NULL + RDS_VIA1 NOTREAT NULL + RDS_VIA2 NOTREAT NULL + RDS_VIA3 NOTREAT NULL + RDS_VIA4 NOTREAT NULL + RDS_VIA5 NOTREAT NULL + RDS_ALU1 TREAT NULL + RDS_ALU2 TREAT NULL + RDS_ALU3 TREAT NULL + RDS_ALU4 TREAT NULL + +# Two RDS_TALU8 rectangles are written, one with no name and +# one with the cell name. When merged, the name is lost. +# It is prefered to have a single rectangle with no name rather +# than two, one of which is named. + +END + +##------------------------------------------------------------------- +## All layers used in the regles must be listed here first. +## Otherwise you get an error like : +# DRUC ERR: Undefined RDS LAYER +##------------------------------------------------------------------- +DRC_RULES + +layer RDS_NWELL 5.0; +layer RDS_PWELL 5.0; +layer RDS_NTIE 1.5 ; +layer RDS_PTIE 0.75 ; +layer RDS_NDIF 0.75 ; +layer RDS_PDIF 0.75 ; +layer RDS_ACTIV 0.75 ; +layer RDS_PIMP 2.5 ; +layer RDS_NIMP 2.5 ; +layer RDS_CONT 1.0 ; +layer RDS_VIA1 0.75 ; +layer RDS_VIA2 0.75 ; +layer RDS_VIA3 0.75 ; +layer RDS_VIA4 0.75 ; +layer RDS_VIA5 2.0 ; +layer RDS_POLY 1.0 ; +layer RDS_GATE 1.0 ; +layer RDS_ALU1 0.75 ; +layer RDS_ALU2 0.75 ; +layer RDS_ALU3 0.75 ; +layer RDS_ALU4 0.75 ; + +layer RDS_REF 2.0 ; + +regles + +# Note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# There is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +#----------------------------------------------------------- +# Check the NWELL shapes +#----------------------- +caracterise RDS_NWELL ( + regle 110 : largeur >= 5.0 ; + regle 111 : longueur_inter min 5.0 ; + regle 130 : notch >= 5.0 ; +); +relation RDS_NWELL , RDS_NWELL ( + regle 131 : distance axiale min 3.0 ; +); + +# Check the PWELL shapes +#----------------------- +caracterise RDS_PWELL ( + regle 112 : largeur >= 5.0 ; + regle 113 : longueur_inter min 5.0 ; + regle 132 : notch >= 5.0 ; +); +relation RDS_PWELL , RDS_PWELL ( + regle 133 : distance axiale min 3.0 ; +); + +define RDS_NWELL , RDS_PWELL intersection -> BOTH_WELLS; + +# Check no NWELL and PWELL overlap +#--------------------------------- +# Won't work with PWELL made from symbolic NWELL +caracterise BOTH_WELLS ( + regle 140 : largeur max 0.0 ; +); +relation RDS_PWELL , RDS_NWELL ( + regle 141 : distance axiale min 0.0 ; +); + +undefine BOTH_WELLS; + +# Check the RDS_PDIF shapes +#-------------------------- +caracterise RDS_PDIF ( + regle 210 : largeur >= 1.5 ; + regle 211 : longueur_inter min 1.5 ; + regle 220 : notch >= 1.5 ; +); +relation RDS_PDIF , RDS_PDIF ( + regle 221 : distance axiale min 1.5 ; +); + +# Check the RDS_NDIF shapes +#-------------------------- +caracterise RDS_NDIF ( + regle 212 : largeur >= 1.5 ; + regle 213 : longueur_inter min 1.5 ; + regle 222 : notch >= 1.5 ; +); +relation RDS_NDIF , RDS_NDIF ( + regle 223 : distance axiale min 1.5 ; +); + +# define PSUB and NSUB layers for easier +# understanding of design rules + +# Check RDS_NDIF is outside NWELL +#-------------------------------- +relation RDS_NDIF , RDS_NWELL ( + regle 230 : distance axiale >= 3.0 ; + regle 231 : enveloppe longueur_inter < 0.0 ; + regle 232 : croix longueur_inter < 0.0 ; + regle 233 : intersection longueur_inter < 0.0 ; + regle 234 : extension longueur_inter < 0.0 ; + regle 235 : inclusion longueur_inter < 0.0 ; +); +relation RDS_NWELL , RDS_NDIF ( + regle 236 : marge longueur_inter < 0.0 ; +); + +# Check RDS_PDIF is inside NWELL +#------------------------------- +relation RDS_NWELL , RDS_PDIF ( + regle 237 : enveloppe inferieure min 3.0 ; +); + +# Check RDS_PTIE is outside NWELL +#-------------------------------- +relation RDS_PTIE , RDS_NWELL ( + regle 240 : distance axiale >= 1.5 ; + regle 241 : enveloppe longueur_inter < 0.0 ; + regle 242 : croix longueur_inter < 0.0 ; + regle 243 : intersection longueur_inter < 0.0 ; + regle 244 : extension longueur_inter < 0.0 ; + regle 245 : inclusion longueur_inter < 0.0 ; +); +relation RDS_NWELL , RDS_PTIE ( + regle 246 : marge longueur_inter < 0.0 ; +); + +# Check RDS_NTIE is inside NWELL +#------------------------------- +relation RDS_NWELL , RDS_NTIE ( + regle 247 : enveloppe inferieure min 1.5 ; +); + +# Check NDIF and PDIF separation +#------------------------------- +relation RDS_NDIF , RDS_PTIE ( + regle 250 : distance axiale min 2.0 ; + regle 251 : intersection longueur_inter < 0.0 ; + regle 252 : extension longueur_inter < 0.0 ; + regle 253 : inclusion longueur_inter < 0.0 ; +); +relation RDS_PDIF , RDS_NTIE ( + regle 254 : distance axiale min 2.0 ; + regle 255 : intersection longueur_inter < 0.0 ; + regle 256 : extension longueur_inter < 0.0 ; + regle 257 : inclusion longueur_inter < 0.0 ; +); + +# Check RDS_PDIF is outside PWELL +#--------------------------------- +relation RDS_PDIF , RDS_PWELL ( + regle 260 : distance axiale >= 3.0 ; + regle 261 : enveloppe longueur_inter < 0.0 ; + regle 262 : croix longueur_inter < 0.0 ; + regle 263 : intersection longueur_inter < 0.0 ; + regle 264 : extension longueur_inter < 0.0 ; + regle 265 : inclusion longueur_inter < 0.0 ; +); +relation RDS_PWELL , RDS_PDIF ( + regle 266 : marge longueur_inter < 0.0 ; +); + +# Check RDS_NDIF is inside PWELL +#------------------------------- +relation RDS_PWELL , RDS_NDIF ( + regle 267 : enveloppe inferieure min 3.0 ; +); + +# Check RDS_NTIE is outside PWELL +#-------------------------------- +relation RDS_NTIE , RDS_PWELL ( + regle 270 : distance axiale >= 1.5 ; + regle 271 : enveloppe longueur_inter < 0.0 ; + regle 272 : croix longueur_inter < 0.0 ; + regle 273 : intersection longueur_inter < 0.0 ; + regle 274 : extension longueur_inter < 0.0 ; + regle 275 : inclusion longueur_inter < 0.0 ; +); +relation RDS_PWELL , RDS_NTIE ( + regle 276 : marge longueur_inter < 0.0 ; +); + +# Check RDS_PTIE is inside PWELL +#------------------------------- +relation RDS_PWELL , RDS_PTIE ( + regle 277 : enveloppe inferieure min 1.5 ; +); + +# Check opposite implant diffusion spacings +#------------------------------------------ +# These rules added to flag DRC errors even if +# NWELL and PWELL are not visualised in Graal +#--------------------------------------------- +relation RDS_PDIF , RDS_NDIF ( +# distance is nwell overlap pdif plus nwell space to ndif + regle 280 : distance axiale min 6.0 ; +); +relation RDS_PDIF , RDS_PTIE ( +# distance is nwell overlap pdif plus nwell space to ptie + regle 281 : distance axiale min 4.5 ; +); +relation RDS_NTIE , RDS_NDIF ( +# distance is nwell overlap ntie plus nwell space to ndif + regle 282 : distance axiale min 4.5 ; +); +# distance is nwell overlap ntie plus nwell space to ptie +relation RDS_NTIE , RDS_PTIE ( + regle 283 : distance axiale min 3.0 ; +); + +define RDS_ACTIV , RDS_POLY intersection -> CHANNEL; + +# Check the RDS_POLY shapes +#-------------------------- +caracterise RDS_POLY ( + regle 310 : largeur >= 1.0 ; + regle 311 : longueur_inter >= 1.0 ; + regle 320 : notch >= 1.5 ; +); +relation RDS_POLY , RDS_POLY ( + regle 321 : distance axiale min 1.5 ; +); + +# Check the CHANNEL shapes +#-------------------------- +caracterise CHANNEL ( + regle 322 : notch >= 1.5 ; +); +relation CHANNEL , CHANNEL ( + regle 323 : distance axiale min 1.5 ; +); + +# Check POLY overlap of TRANSISTOR (ENDCAP) +#------------------------------------------ +relation RDS_POLY , RDS_PDIF ( + regle 330 : croix longueur_min min 1.25 ; +); +relation RDS_POLY , RDS_NDIF ( + regle 331 : croix longueur_min min 1.25 ; +); + +# Check SOURCE/DRAIN width +#------------------------- +relation RDS_PDIF , RDS_GATE ( + regle 340 : croix longueur_min min 2.0 ; +); +relation RDS_NDIF , RDS_GATE ( + regle 341 : croix longueur_min min 2.0 ; +); + +# Check RDS_POLY separation to DIF +#--------------------------------- +relation RDS_POLY , RDS_PDIF ( + regle 350 : distance axiale min 0.5 ; +); +relation RDS_POLY , RDS_NDIF ( + regle 351 : distance axiale min 0.5 ; +); +relation RDS_POLY , RDS_PTIE ( + regle 352 : distance axiale min 0.5 ; +); +relation RDS_POLY , RDS_NTIE ( + regle 353 : distance axiale min 0.5 ; +); + +# Check RDS_POLY separation to TRANSISTOR CHANNEL +#------------------------------------------------ +relation RDS_POLY , CHANNEL ( + regle 354 : distance axiale >= 0.5 ; +); + +define RDS_POLY , CHANNEL exclusion -> FIELD_POLY; +define RDS_PDIF , RDS_POLY intersection -> PGATE; + +# Check RDS_POLY does not overlap PDIF +#------------------------------------- +relation PGATE , FIELD_POLY ( + regle 355 : inclusion longueur_inter < 0.0 ; +); +relation FIELD_POLY , PGATE ( + regle 356 : extension longueur_inter < 0.0 ; +); + +undefine PGATE; +define RDS_NDIF , RDS_POLY intersection -> NGATE; + +# Check RDS_POLY does not overlap NDIF +#------------------------------------- +relation NGATE , FIELD_POLY ( + regle 357 : inclusion longueur_inter < 0.0 ; +); +relation FIELD_POLY , NGATE ( + regle 358 : extension longueur_inter < 0.0 ; +); + +undefine NGATE; +define RDS_PDIF , CHANNEL intersection -> PTR; + +# N-select and P-select rules +#---------------------------- +relation PTR , RDS_NIMP ( + regle 410 : distance axiale min 1.5 ; +); + +undefine PTR; +define RDS_NDIF , CHANNEL intersection -> NTR; + +relation NTR , RDS_PIMP ( + regle 411 : distance axiale min 1.5 ; +); + +undefine NTR; +undefine FIELD_POLY; +relation RDS_PIMP , RDS_PDIF ( + regle 420 : enveloppe inferieure min 1.0 ; +); +relation RDS_NIMP , RDS_NDIF ( + regle 422 : enveloppe inferieure min 1.0 ; +); + +define RDS_PIMP , RDS_PWELL intersection -> TIE_PIMP; +define RDS_NIMP , RDS_NWELL intersection -> TIE_NIMP; + +# Check min SELECT widths for TIE implant +#---------------------------------------- +caracterise TIE_PIMP ( + regle 440 : largeur >= 2.0 ; + regle 441 : longueur_inter min 2.0 ; +); +# This is the min NIMP width rule +relation TIE_PIMP , TIE_PIMP ( + regle 444 : distance axiale min 2.0 ; +); +caracterise TIE_NIMP ( + regle 442 : largeur >= 2.0 ; + regle 443 : longueur_inter min 2.0 ; +); +# This is the min PIMP width rule +relation TIE_NIMP , TIE_NIMP ( + regle 445 : distance axiale min 2.0 ; +); + +undefine TIE_NIMP; +undefine TIE_PIMP; +define RDS_POLY , RDS_CONT intersection -> POLY_CONT; + +# Check CONT layer size, separation and overlaps +#----------------------------------------------- +caracterise POLY_CONT ( + regle 510 : largeur max 1.0 ; + regle 511 : largeur min 1.0 ; +); +relation RDS_POLY , RDS_CONT ( + regle 520 : enveloppe inferieure min 0.5 ; +); +relation RDS_CONT , RDS_CONT ( + regle 530 : distance axiale min 2.0 ; +); + +# Check POLY CONTACT separation from TRANSISTOR CHANNEL +#------------------------------------------------------ +relation CHANNEL , POLY_CONT ( + regle 540 : distance axiale >= 1.5 ; +); + +undefine POLY_CONT; +define RDS_CONT , CHANNEL intersection -> BAD_CONT; + +# CONTACT not allowed over TRANSISTOR +#------------------------------------ +caracterise BAD_CONT ( + regle 580 : largeur max 0.0 ; +); + +undefine BAD_CONT; + +define RDS_PDIF , RDS_CONT intersection -> PDIF_CONT; +caracterise PDIF_CONT ( + regle 610 : longueur max 1.0 ; + regle 611 : longueur_inter min 1.0 ; +); +# Check PDIF CONTACT separation from TRANSISTOR CHANNEL +#------------------------------------------------------ +relation CHANNEL , PDIF_CONT ( + regle 640 : distance axiale >= 1.0 ; +); + +undefine PDIF_CONT; +define RDS_NDIF , RDS_CONT intersection -> NDIF_CONT; + +caracterise NDIF_CONT ( + regle 612 : longueur max 1.0 ; + regle 613 : longueur_inter min 1.0 ; +); +# Check NDIF CONTACT separation from TRANSISTOR CHANNEL +#------------------------------------------------------ +relation CHANNEL , NDIF_CONT ( + regle 641 : distance axiale >= 1.0 ; +); + +undefine NDIF_CONT; +define RDS_PTIE , RDS_CONT intersection -> PTIE_CONT; +caracterise PTIE_CONT ( + regle 614 : longueur max 1.0 ; + regle 615 : longueur_inter min 1.0 ; +); +# Check PTIE CONTACT separation from TRANSISTOR CHANNEL +#------------------------------------------------------ +relation CHANNEL , PTIE_CONT ( + regle 642 : distance axiale >= 1.5 ; +); + +undefine PTIE_CONT; +define RDS_NTIE , RDS_CONT intersection -> NTIE_CONT; + +caracterise NTIE_CONT ( + regle 616 : longueur max 1.0 ; + regle 617 : longueur_inter min 1.0 ; +); +# Check NTIE CONTACT separation from TRANSISTOR CHANNEL +#------------------------------------------------------ +relation CHANNEL , NTIE_CONT ( + regle 643 : distance axiale >= 1.5 ; +); + +undefine NTIE_CONT; + +relation RDS_PDIF , RDS_CONT ( + regle 620 : enveloppe inferieure min 0.5 ; +); +relation RDS_NDIF , RDS_CONT ( + regle 621 : enveloppe inferieure min 0.5 ; +); +relation RDS_PTIE , RDS_CONT ( + regle 622 : enveloppe inferieure min 0.5 ; +); +relation RDS_NTIE , RDS_CONT ( + regle 623 : enveloppe inferieure min 0.5 ; +); + +undefine CHANNEL; + +# Check RDS_ALU1 shapes +#---------------------- +caracterise RDS_ALU1 ( + regle 710 : largeur >= 1.5 ; + regle 711 : longueur_inter min 1.5 ; +); +relation RDS_ALU1 , RDS_ALU1 ( + regle 724 : distance axiale min 1.5 ; +); +# Check ALU1 side overlap of CONT +#-------------------------------- + + +# Check VIA layer size and separation +#------------------------------------ +caracterise RDS_VIA1 ( + regle 810 : largeur <= 1.5 ; + regle 811 : largeur >= 1.5 ; +); +relation RDS_VIA1 , RDS_VIA1 ( + regle 820 : distance axiale min 1.5 ; +); + +# Check ALU1 overlap of VIA1 +#--------------------------- +relation RDS_ALU1 , RDS_VIA1 ( +# Case 1: side overlap +# Basic side overlap checked on all sides + regle 830 : enveloppe inferieure min 0.5 ; + regle 831 : marge longueur_inter max 0.5 ; +); +#relation RDS_VIA1 , RDS_ALU1 ( +# regle 832 : intersection longueur_inter max 0.0 ; +#); + + +# Check RDS_ALU2 shapes +#---------------------- +caracterise RDS_ALU2 ( + regle 910 : largeur >= 1.5 ; + regle 911 : longueur_inter min 1.5 ; + regle 920 : notch >= 2.0 ; +); +relation RDS_ALU2 , RDS_ALU2 ( + regle 921 : distance axiale min 2.0 ; +); +# Check ALU2 overlap of VIA1 +#--------------------------- +relation RDS_ALU2 , RDS_VIA1 ( +# Case 1: side overlap +# Basic side overlap checked on all sides + regle 930 : enveloppe inferieure min 0.5 ; + regle 931 : marge longueur_inter max 0.5 ; +); +#relation RDS_VIA1 , RDS_ALU2 ( +# regle 932 : intersection longueur_inter max 0.0 ; +#); + + +# Check VIA2 layer size and separation +#------------------------------------- +caracterise RDS_VIA2 ( + regle 1410 : largeur <= 1.5 ; + regle 1411 : largeur >= 1.5 ; +); +relation RDS_VIA2 , RDS_VIA2 ( + regle 1420 : distance axiale min 1.5 ; +); + +# Check ALU2 overlap of VIA2 +#--------------------------- +relation RDS_ALU2 , RDS_VIA2 ( +# Case 1: side overlap +# Basic side overlap checked on all sides + regle 1430 : enveloppe inferieure min 0.5 ; + regle 1431 : marge longueur_inter max 0.5 ; +); +#relation RDS_VIA2 , RDS_ALU2 ( +# regle 1432 : intersection longueur_inter max 0.0 ; +#); + + +# Check RDS_ALU3 shapes +#---------------------- +caracterise RDS_ALU3 ( + regle 1510 : largeur >= 1.5 ; + regle 1511 : longueur_inter min 1.5 ; + regle 1520 : notch >= 2.0 ; +); +relation RDS_ALU3 , RDS_ALU3 ( + regle 1521 : distance axiale min 1.5 ; +); +# Check ALU3 overlap of VIA2 +#--------------------------- +relation RDS_ALU3 , RDS_VIA2 ( +# Case 1: side overlap +# Basic side overlap checked on all sides + regle 1530 : enveloppe inferieure min 0.5 ; + regle 1531 : marge longueur_inter max 0.5 ; +); +#relation RDS_VIA2 , RDS_ALU3 ( +# regle 1532 : intersection longueur_inter max 0.0 ; +#); + + +# Check VIA3 layer size and separation +#------------------------------------- +caracterise RDS_VIA3 ( + regle 2110 : largeur <= 1.5 ; + regle 2111 : largeur >= 1.5 ; +); +relation RDS_VIA3 , RDS_VIA3 ( + regle 2120 : distance axiale min 1.5 ; +); + +# Check ALU3 overlap of VIA3 +#--------------------------- +relation RDS_ALU3 , RDS_VIA3 ( +# Case 1: side overlap +# Basic side overlap checked on all sides + regle 2130 : enveloppe inferieure min 0.5 ; + regle 2131 : marge longueur_inter max 0.5 ; +); +#relation RDS_VIA3 , RDS_ALU3 ( +# regle 2132 : intersection longueur_inter max 0.0 ; +#); + +# Check RDS_ALU4 shapes +#---------------------- +caracterise RDS_ALU4 ( + regle 2210 : largeur >= 1.5 ; + regle 2211 : longueur_inter min 1.5 ; + regle 2220 : notch >= 2.0 ; +); +relation RDS_ALU4 , RDS_ALU4 ( + regle 2221 : distance axiale min 2.0 ; +); +# Check ALU4 overlap of VIA3 +#--------------------------- +relation RDS_ALU4 , RDS_VIA3 ( +# Case 1: side overlap +# Basic side overlap checked on all sides + regle 2230 : enveloppe inferieure min 0.5 ; + regle 2231 : marge longueur_inter max 0.5 ; +); +#relation RDS_VIA3 , RDS_ALU4 ( +# regle 2232 : intersection longueur_inter max 0.0 ; +#); + + +# Check VIA4 layer size and separation +#------------------------------------- +caracterise RDS_VIA4 ( + regle 2510 : largeur <= 1.5 ; + regle 2511 : largeur >= 1.5 ; +); +relation RDS_VIA4 , RDS_VIA4 ( + regle 2520 : distance axiale min 1.5 ; +); + +# Check ALU4 overlap of VIA4 +#--------------------------- +relation RDS_ALU4 , RDS_VIA4 ( +# Case 1: side overlap +# Basic side overlap checked on all sides + regle 2530 : enveloppe inferieure min 0.5 ; + regle 2531 : marge longueur_inter max 0.5 ; +); +#relation RDS_VIA4 , RDS_ALU4 ( +# regle 2532 : intersection longueur_inter max 0.0 ; +#); + + + + +fin regles +DRC_COMMENT +110 1.1 NWELL Width < 5.0um ( 10 lambda) +111 1.1 NWELL Width < 5.0um ( 10 lambda) +112 1.1 PWELL Width < 5.0um ( 10 lambda) +113 1.1 PWELL Width < 5.0um ( 10 lambda) +130 1.3 NWELL Notch < 3.0 um ( 6 lambda) +131 1.3 NWELL Space < 3.0 um ( 6 lambda) +132 1.3 PWELL Notch < 3.0 um ( 6 lambda) +133 1.3 PWELL Space < 3.0 um ( 6 lambda) +140 1.4 NWELL and PWELL must not overlap (misaligned NWELL?) +141 1.4 NWELL and PWELL Space < 0um +210 2.1a PDIF Width < 1.5 um ( 3 lambda) +211 2.1a PDIF Width < 1.5 um ( 3 lambda) +220 2.2a PDIF Notch < 1.5 um ( 3 lambda) +221 2.2a PDIF Space < 1.5 um ( 3 lambda) +212 2.1a NDIF Width < 1.5 um ( 3 lambda) +213 2.1a NDIF Width < 1.5 um ( 3 lambda) +222 2.2a NDIF Notch < 1.5 um ( 3 lambda) +223 2.2a NDIF Space < 1.5 um ( 3 lambda) +214 2.1b PTIE Width < 1.5 um ( 3 lambda) +215 2.1b PTIE Width < 1.5 um ( 3 lambda) +224 2.2b PTIE Notch < 1.5 um ( 3 lambda) +225 2.2b PTIE Space < 1.5 um ( 3 lambda) +216 2.1b NTIE Width < 1.5 um ( 3 lambda) +217 2.1b NTIE Width < 1.5 um ( 3 lambda) +226 2.2b NTIE Notch < 1.5 um ( 3 lambda) +227 2.2b NTIE Space < 1.5 um ( 3 lambda) +230 2.3a NWELL to NDIF Space < 3.0 um ( 6 lambda) +231 2.3a NDIF must not touch NWELL +232 2.3a NDIF must not touch NWELL +233 2.3a NDIF must not touch NWELL +234 2.3a NDIF must not touch NWELL +235 2.3a NDIF must not touch NWELL +236 2.3a NDIF must not touch NWELL +237 2.3b NWELL Overlap of PDIF < 3.0 um ( 6 lambda) +240 2.4a NWELL to PTIE Space < 1.5 um (3 lambda) +241 2.4a PTIE must not touch NWELL +242 2.4a PTIE must not touch NWELL +243 2.4a PTIE must not touch NWELL +244 2.4a PTIE must not touch NWELL +245 2.4a PTIE must not touch NWELL +246 2.4a PTIE must not touch NWELL +247 2.4b NWELL Overlap of NTIE < 1.5 um (3 lambda) +250 1.25 NDIF to PTIE Space < 2.0 um (4 lambda) +251 1.25 NDIF must not touch or overlap PTIE +252 1.25 NDIF must not touch or overlap PTIE +253 1.25 NDIF must not touch or overlap PTIE +254 1.25 PDIF to NTIE Space < 2.0 um (4 lambda) +255 1.25 PDIF must not touch or overlap NTIE +256 1.25 PDIF must not touch or overlap NTIE +257 1.25 PDIF must not touch or overlap NTIE +260 2.3b PWELL to PDIF Space < 3.0 um (6 lambda) +261 2.3b PDIF must not touch PWELL +262 2.3b PDIF must not touch PWELL +263 2.3b PDIF must not touch PWELL +264 2.3b PDIF must not touch PWELL +265 2.3b PDIF must not touch PWELL +266 2.3b PDIF must not touch PWELL +267 2.3a PWELL Overlap of NDIF 3.0 um (6 lambda) +270 2.4b PWELL to NTIE Space 1.5 um (3 lambda) +271 2.4b NTIE must not touch PWELL +272 2.4b NTIE must not touch PWELL +273 2.4b NTIE must not touch PWELL +274 2.4b NTIE must not touch PWELL +275 2.4b NTIE must not touch PWELL +276 2.4b NTIE must not touch PWELL +277 2.4a PWELL Overlap of PTIE < 1.5 um (3 lambda) +280 2.8a PDIF to NDIF Space < 6.0um (12 lambda) +281 2.8b PDIF to PTIE Space < 4.5um (9 lambda) +282 2.8b NTIE to NDIF Space < 4.5um (9 lambda) +283 2.8c NTIE to PTIE Space < 3.0 um (6 lambda) +310 3.1 POLY Width < 1.0 um (2 lambda) +311 3.1 POLY Width < 1.0 um (2 lambda) +320 3.2 POLY Notch < 1.5 um (3 lambda) +321 3.2 POLY Space < 1.5 um (3 lambda) +322 3.2a CHANNEL Space < 2.0 um (4 lambda) +323 3.2a CHANNEL Space < 2.0 um (4 lambda) +330 3.3 POLY Overlap of P-TRANSISTOR < 1.25 um (2.5 lambda) +331 3.3 POLY Overlap of N-TRANSISTOR < 1.25 um (2.5 lambda) +340 3.4 P-TRANSISTOR SOURCE/DRAIN Width < 2.0 um (4 lambda) +341 3.4 N-TRANSISTOR SOURCE/DRAIN Width < 2.0 um (4 lambda) +350 3.5 PDIF to POLY Space < 0.5 um (1 lambda) +351 3.5 NDIF to POLY Space < 0.5 um (1 lambda) +352 3.5 PTIE to POLY Space < 0.5 um (1 lambda) +353 3.5 NTIE to POLY Space < 0.5 um (1 lambda) +354 3.5a POLY to GATE Space < 0.5 um (1 lambda) +355 3.5 POLY must not touch or overlap PDIF +356 3.5 POLY must not touch or overlap PDIF +357 3.5 POLY must not touch or overlap NDIF +358 3.5 POLY must not touch or overlap NDIF +410 4.1 NIMP to P-TRANSISTOR Space < 1.5 um (3 lambda) +411 4.1 PIMP to N-TRANSISTOR Space < 1.5 um (3 lambda) +420 4.2a PIMP Overlap of PDIF < 1.0 um (2 lambda) +421 4.2b PIMP Overlap of PTIE < 1.0 um (2 lambda) +422 4.2a NIMP Overlap of NDIF < 1.0 um (2 lambda) +423 4.2b NIMP Overlap of NTIE < 1.0 um (2 lambda) +440 4.4 PIMP in PWELL Width < 2.0 um (4 lambda) +441 4.4 PIMP in PWELL Width < 2.0 um (4 lambda) +442 4.4 NIMP in NWELL Width < 2.0 um (4 lambda) +443 4.4 NIMP in NWELL Width < 2.0 um (4 lambda) +444 4.4 PIMP in PWELL Space < 2.0 um (4 lambda) +445 4.4 NIMP in NWELL Space < 2.0 um (4 lambda) +510 5.1 POLY CONTACT Width > 1.0 um (2 lambda) +511 5.1 POLY CONTACT Width < 1.0 um (2 lambda) +520 5.2 POLY Overlap of CONTACT < 0.75um (1.5 lambda) +530 5.3 CONTACT Space < 2.0 um (4 lambda) +540 5.4 POLY CONTACT to CHANNEL Space < 1.0 um (2 lambda) +580 5.8 CONTACT not allowed over TRANSISTOR +610 6.1 PDIF CONTACT Width > 1.0 um (2 lambda) +611 6.1 PDIF CONTACT Width < 1.0 um (2 lambda) +612 6.1 NDIF CONTACT Width > 1.0 um (2 lambda) +613 6.1 NDIF CONTACT Width < 1.0 um (2 lambda) +614 6.1 PTIE CONTACT Width > 1.0 um (2 lambda) +615 6.1 PTIE CONTACT Width < 1.0 um (2 lambda) +616 6.1 NTIE CONTACT Width > 1.0 um (2 lambda) +617 6.1 NTIE CONTACT Width < 1.0 um (2 lambda) +620 6.2a PDIF Overlap of CONT < 0.75um (1.5 lambda) +621 6.2a NDIF Overlap of CONT < 0.75um (1.5 lambda) +622 6.2b PTIE Overlap of CONT < 0.75um (1.5 lambda) +623 6.2b NTIE Overlap of CONT < 0.75um (1.5 lambda) +640 6.4 PDIF CONTACT to CHANNEL Space < 1.0 um (2 lambda) +641 6.4 NDIF CONTACT to CHANNEL Space < 1.0 um (2 lambda) +642 4.1+4.2b+6.2b PTIE CONTACT to CHANNEL Space < 3.25 um (6.5 lambda) +643 4.1+4.2b+6.2b NTIE CONTACT to CHANNEL Space < 3.25 um (6.5 lambda) +710 7.1 ALU1 Width < 1.5 um (3 lambda) +711 7.1 ALU1 Width < 1.5 um (3 lambda) +720 7.2 ALU1 Notch < 1.5 um (3 lambda) +712 7.1 ALU0 Width < 1.5 um (3 lambda) +713 7.1 ALU0 Width < 1.5 um (3 lambda) +721 7.2 ALU0 Notch < 1.5 um (3 lambda) +723 7.2 ALU0 Space < 1.5 um (3 lambda) +724 7.2 ALU1 Space < 1.5 um (3 lambda) +730 7.3a ALU1 side Overlap of CONTACT < 0.5 um (1 lambda) +731 7.3a ALU1 side Overlap of CONTACT < 0.5 um (1 lambda) +732 7.3b ALU1 end Overlap of CONTACT <= 0.5 um (1 lambda) +733 7.3b ALU1 end Overlap of CONTACT < 0.5 um (small) (1 lambda) +734 7.3b ALU1 end Overlap of CONTACT < 0.5 um (big) (1 lambda) +735 7.3b ALU1 end Overlap of CONTACT < 0.5 um (small) (1 lambda) +736 7.3b ALU1 end Overlap of CONTACT < 0.5 um (big) (1 lambda) +750 7.5 REF Width > 1.5 um (3 lambda) +751 7.5 REF Width < 1.5 um (3 lambda) +760 7.6 REF Space < 1.5 um (3 lambda) +770 7.7 ALU1 must not touch or intersect REF +773 7.7 ALU1 Overlap of REF < 0.5 um (1 lambda) +774 7.7 ALU1 Overlap of REF < 0.5 um (1 lambda) +780 7.8 ALU1 end Overlap of REF < 0.5 um (small) (1 lambda) +781 7.8 ALU1 end Overlap of REF < 0.5 um (big) (1 lambda) +810 8.1 VIA1 Width > 1.5 um (3 lambda) +811 8.1 VIA1 Width < 1.5 um (3 lambda) +820 8.2 VIA1 Space < 1.5 um (3 lambda) +830 8.3a ALU1 side Overlap of VIA1 < 0.5 um (1 lambda) +831 8.3a ALU1 side Overlap of VIA1 < 0.5 um (1 lambda) +832 8.3 ALU1 must not touch or intersect VIA1 +833 8.3b ALU1 end Overlap of VIA1 < 0.5 um (small) (1 lambda) +834 8.3b ALU1 end Overlap of VIA1 < 0.5 um (big) (1 lambda) +910 9.1 ALU2 Width < 1.5 um (3 lambda) +911 9.1 ALU2 Width < 1.5 um (3 lambda) +920 9.2 ALU2 Notch < 2.0 um (4 lambda) +921 9.2 ALU2 Space < 2.0 um (4 lambda) +930 9.3a ALU2 side Overlap of VIA1 < 0.5 um (1 lambda) +931 9.3a ALU2 side Overlap of VIA1 < 0.5 um (1 lambda) +932 9.3 ALU2 must not touch or intersect VIA1 +933 9.3b ALU2 end Overlap of VIA1 < 0.5 um (small) (1 lambda) +934 9.3b ALU2 end Overlap of VIA1 < 0.5 um (big) (1 lambda) +1410 14.1 VIA2 Width > 1.5 um (3 lambda) +1411 14.1 VIA2 Width < 1.5 um (3 lambda) +1420 14.2 VIA2 Space < 2.0 um (4 lambda) +1430 14.3a ALU2 side Overlap of VIA2 < 0.5 um (1 lambda) +1431 14.3a ALU2 side Overlap of VIA2 < 0.5 um (1 lambda) +1432 14.3 ALU2 must not touch or intersect VIA2 +1433 14.3b ALU2 end Overlap of VIA2 < 0.5 um (small) (1 lambda) +1434 14.3b ALU2 end Overlap of VIA2 < 0.5 um (big) (1 lambda) +1510 15.1 ALU3 Width < 1.5 um (3 lambda) +1511 15.1 ALU3 Width < 1.5 um (3 lambda) +1520 15.2 ALU3 Notch < 2.0 um (4 lambda) +1521 15.2 ALU3 Space < 2.0 um (4 lambda) +1530 15.3a ALU3 side Overlap of VIA2 < 0.5 um (1 lambda) +1531 15.3a ALU3 side Overlap of VIA2 < 0.5 um (1 lambda) +1532 15.3 ALU3 must not touch or intersect VIA2 +1533 15.3b ALU3 end Overlap of VIA2 < 0.5 um (small) (1 lambda) +1534 15.3b ALU3 end Overlap of VIA2 < 0.5 um (big) (1 lambda) +2110 21.1 VIA3 Width > 1.5 um (3 lambda) +2111 21.1 VIA3 Width < 1.5 um (3 lambda) +2120 21.2 VIA3 Space < 2.0 um (4 lambda) +2130 21.3a ALU3 side Overlap of VIA3 < 0.5 um (1 lambda) +2131 21.3a ALU3 side Overlap of VIA3 < 0.5 um (1 lambda) +2132 21.3 ALU3 must not touch or intersect VIA3 +2133 21.3b ALU3 end Overlap of VIA3 < 0.5 um (small) (1 lambda) +2134 21.3b ALU3 end Overlap of VIA3 < 0.5 um (big) (1 lambda) +2210 22.1 ALU4 Width < 1.5 um (3 lambda) +2211 22.1 ALU4 Width < 1.5 um (3 lambda) +2220 22.2 ALU4 Notch < 2.0 um (4 lambda) +2221 22.2 ALU4 Space < 2.0 um (4 lambda) +2230 22.3a ALU4 side Overlap of VIA3 < 0.5 um (1 lambda) +2231 22.3a ALU4 side Overlap of VIA3 < 0.5 um (1 lambda) +2232 22.3 ALU4 must not touch or intersect VIA3 +2233 22.3b ALU4 end Overlap of VIA3 < 0.5 um (small) (1 lambda) +2234 22.3b ALU4 end Overlap of VIA3 < 0.5 um (big) (1 lambda) +2510 25.1 VIA4 Width > 1.5 um (3 lambda) +2511 25.1 VIA4 Width < 1.5 um (3 lambda) +2520 25.2 VIA4 Space < 2.0 um (4 lambda) +2530 25.3a ALU4 side Overlap of VIA4 < 0.5 um (1 lambda) +2531 25.3a ALU4 side Overlap of VIA4 < 0.5 um (1 lambda) +2532 25.3 ALU4 must not touch or intersect VIA4 +2533 25.3b ALU4 end Overlap of VIA4 < 0.5 um (small) (1 lambda) +2534 25.3b ALU4 end Overlap of VIA4 < 0.5 um (big) (1 lambda) +5010 50.1 AB Overlap of PTIE < 2.0 um (4 lambda) +5011 50.1 AB Overlap of NTIE < 2.0 um (4 lambda) +5020 50.2 AB Overlap of PDIF < 0.75um (1.5 lambda) +5021 50.2 AB Overlap of NDIF < 0.75um (1.5 lambda) +5030 50.3 AB Overlap of POLY < 0.75um (1.5 lambda) +5040 50.4 AB Overlap of ALU1 < 0.75um (1.5 lambda) +5041 50.4 AB Overlap of ALU0 < 0.75um (1.5 lambda) +5050 50.5 AB Overlap of REF < 1.0 um (2 lambda) +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/spimodel.cfg b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/spimodel.cfg new file mode 100644 index 000000000..3261868b3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/spimodel.cfg @@ -0,0 +1,5 @@ +# MBK_SPI_MODEL +# configure the transistor models of spi parser/driver +# +nmos N +pmos P diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/symbolic.dreal b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/symbolic.dreal new file mode 100644 index 000000000..3c39bd85c --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/symbolic.dreal @@ -0,0 +1,127 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Dreal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 02/08/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +dEFINE DREAL_LOWER_FIGURE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_INSTANCE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_CONNECTOR_STEP 0.5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_SEGMENT_STEP 0.7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_REFERENCE_STEP 1.0 + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TAbLE DREAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/symbolic.graal b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/symbolic.graal new file mode 100644 index 000000000..cae4dcf0b --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/symbolic.graal @@ -0,0 +1,386 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Graal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 27/06/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Graal Peek Bound in lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_PEEK_BOUND 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_FIGURE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_INSTANCE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_CONNECTOR_STEP 5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_SEGMENT_STEP 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_REFERENCE_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | Segment Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_NAME + + NWELL Nwell tan Black + PWELL Pwell light_yellow Black + NDIF Ndif lawn_green Black + PDIF Pdif yellow Black + NTIE Ntie spring_green Black + PTIE Ptie light_goldenrod Black + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 GReen Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + TPOLY Tpoly hot_pink Black + TALU1 Talu1 royal_blue Black + TALU2 Talu2 turquoise Black + TALU3 Talu3 light_pink Black + TALU4 Talu4 green Black + TALU5 Talu5 yellow Black + TALU6 Talu6 violet Black + TALU7 Talu7 red Black + TALU8 Talu8 blue Black + CALU1 CAlu1 royal_blue Black + CALU2 CAlu2 Cyan Black + CALU3 CAlu3 light_pink Black + CALU4 CAlu4 green Black + CALU5 CAlu5 yellow Black + CALU6 CAlu6 violet Black + CALU7 CAlu7 red Black + CALU8 CAlu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Transistor Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_TRANSISTOR_NAME + + NTRANS Ntrans lawn_green Black + PTRANS Ptrans yellow Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Connector Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_CONNECTOR_NAME + + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 green Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Length and Width for a symbolic Segment | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_VALUE + + NWELL 4 4 + PWELL 4 4 + NDIF 3 2 # LSX 2 -> 3 + PDIF 3 2 # LSX 2 -> 3 + NTIE 3 1 # LSX 2 -> 3 + PTIE 3 1 # LSX 2 -> 3 + NTRANS 1 5 # LSX 4 -> 5 + PTRANS 1 5 # LSX 4 -> 5 + POLY 1 1 + POLY2 1 1 + ALU1 2 1 # LSX 1 -> 2 + ALU2 2 1 + ALU3 2 1 + ALU4 2 1 + ALU5 2 1 + ALU6 2 1 + ALU7 2 1 + ALU8 2 1 + TPOLY 1 1 + TALU1 2 1 # LSX 1 -> 2 + TALU2 2 1 # LSX 2 -> 1 + TALU3 2 1 # LSX 2 -> 1 + TALU4 2 1 # LSX 2 -> 1 + TALU5 2 1 # LSX 2 -> 1 + TALU6 2 1 # LSX 2 -> 1 + TALU7 2 1 # LSX 2 -> 1 + TALU8 2 1 # LSX 2 -> 1 + CALU1 2 0 + CALU2 2 0 + CALU3 2 0 + CALU4 2 0 + CALU5 2 0 + CALU6 2 0 + CALU7 2 0 + CALU8 2 0 + +END + +# /*------------------------------------------------------------\ +# | | +# | Reference Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_REFERENCE_NAME + + REF_REF Ref_Ref red Black + REF_CON Ref_Con Cyan Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_VIA_NAME + + CONT_DIF_N Cont_NDif lawn_green Black + CONT_DIF_P Cont_PDif yellow Black + CONT_BODY_N Cont_NTie spring_green Black + CONT_BODY_P Cont_PTie light_goldenrod Black + CONT_POLY Cont_Poly red Black + CONT_POLY2 Cont_Poly2 orange Black + CONT_VIA Via_1-2 cyan Black + CONT_VIA2 Via_2-3 light_pink Black + CONT_VIA3 Via_3-4 green Black + CONT_VIA4 Via_4-5 yellow Black + CONT_VIA5 Via_5-6 violet Black + CONT_VIA6 Via_6-7 red Black + CONT_VIA7 Via_7-8 blue Black + C_X_N Cont_CxN orange Black + C_X_P Cont_CxP orange Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Big Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_NAME + + CONT_VIA Big_Via_1-2 cyan Black + CONT_VIA2 Big_Via_2-3 light_pink Black + CONT_VIA3 Big_Via_3-4 green Black + CONT_VIA4 Big_Via_4-5 yellow Black + CONT_VIA5 Big_Via_5-6 violet Black + CONT_VIA6 Big_Via_6-7 red Black + CONT_VIA7 Big_Via_7-8 blue Black + + CONT_TURN1 Turn_Via_1 royal_blue Black + CONT_TURN2 Turn_Via_2 Cyan Black + CONT_TURN3 Turn_Via_3 light_pink Black + CONT_TURN4 Turn_Via_4 green Black + CONT_TURN5 Turn_Via_5 yellow Black + CONT_TURN6 Turn_Via_6 violet Black + CONT_TURN7 Turn_Via_7 red Black + CONT_TURN8 Turn_Via_7 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Size for a symbolic Big Via | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_VALUE + + CONT_VIA 2 + CONT_VIA2 2 + CONT_VIA3 2 + CONT_VIA4 2 + CONT_VIA5 2 + CONT_VIA6 2 + CONT_VIA7 2 + + CONT_TURN1 2 + CONT_TURN2 2 + CONT_TURN3 2 + CONT_TURN4 2 + CONT_TURN5 2 + CONT_TURN6 2 + CONT_TURN7 2 + CONT_TURN8 2 + +END + +# /*------------------------------------------------------------\ +# | | +# | Orient Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_ORIENT_NAME + + NORTH North lawn_green Black + SOUTH South yellow Black + EAST East tan Black + WEST West red Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Symmetry Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SYMMETRY_NAME + + NOSYM No_Sym LightBlue Black + SYM_X Sym_X turquoise Black + SYM_Y Sym_Y cyan Black + SYMXY Sym_XY lightCyan Black + ROT_P Rot_P MediumAquamarine Black + ROT_M Rot_M aquamarine Black + SY_RP Sym_RP green Black + SY_RM Sym_RM MediumSpringGreen Black + +END + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/techno.py b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/techno.py new file mode 100644 index 000000000..b5278db13 --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/techno.py @@ -0,0 +1,647 @@ + +from coriolis import CRL, Hurricane, Viewer, Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, BasicLayer, \ + RegularLayer, Cell, Net, Horizontal, Vertical, Rectilinear, \ + Box, Point, NetExternalComponents +from coriolis.technos.common.colors import toRGB +from coriolis.technos.common.patterns import toHexa +from coriolis.helpers import u +from coriolis.helpers.technology import createBL, createVia +from coriolis.helpers.overlay import CfgCache +from coriolis.helpers.analogtechno import Length, Area, Unit, Asymmetric, loadAnalogTechno, addDevice +from coriolis.designflow.task import ShellEnv + + +__all__ = [ "setup" ] + + +""" +Coriolis Design Technological Rules (DTR) for IHP 130nm BiCMOS General Purpose +================================================================================= + +:Version: rev.LIP6-1 +:Date: May 22, 2024 +:Authors: Naohiko Shimizu + +Reference documents: + SG13G2 Process Specification Rev.1.2 + SG13G2 Open Source Layout Rules Rev.0.2 (2024-03-08) + +===================== ======= ============ ==================================== + +""" + + +analogTechnologyTable = \ + ( ('Header', 'Sg13g2', DbU.UnitPowerMicro, 'rev.LIP6-1') + # ------------------------------------------------------------------------------------ + # ( Rule name , [Layer1] , [Layer2] , Value , Rule flags , Reference ) + , ('physicalGrid' , 0.001 , Length , 'Grid Rules') + , ('transistorMinL' , 0.13 , Length , 'Gat.a') + #, ('transistorMinL' , 0.38 , Length , 'lvtn.1a') + #, ('transistorMaxL' , 38 , Length , 'rule0002') + #, ('transistorMinW' , 0.42 , Length , 'activ.2') + #, ('transistorMinW' , 0.36 , Length , 'activ.2b') + #, ('transistorMaxW' , 4000 , Length , 'rule0004') + + # N-WELL (nwm) + , ('minWidth' , 'nwm' , 0.62 , Length , 'NW.a') + , ('minSpacing' , 'nwm' , 0.62 , Length , 'NW.b') + , ('minArea' , 'nwm' , 0 , Area , 'N/A') + + # LVTN (lvtn) + #, ('minWidth' , 'lvtn' , 0.38 , Length , 'lvtn.1a') + #, ('minSpacing' , 'lvtn' , 0.38 , Length , 'lvtn.2') + #, ('minArea' , 'lvtn' , 0.265 , Area , 'lvtn.13') + #, ('minEnclosure' , 'nwm' , 'lvtn' , 0.38 , Length|Asymmetric, 'lvtn.10') + + # ACTIV (activ) + , ('minWidth' , 'activ' , 0.15 , Length , 'Act.a') + , ('minSpacing' , 'activ' , 0.21 , Length , 'Act.b') + , ('minArea' , 'activ' , 0.122 , Area , 'Act.d') + , ('minEnclosure' , 'nwm' , 'activ' , 0.31 , Length|Asymmetric, 'NW.c') + + # Poly1 (poly) + , ('minWidth' , 'poly' , 0.13 , Length , 'Gat.a') + , ('minSpacing' , 'poly' , 0.18 , Length , 'Gat.b') + , ('minGateSpacing' , 'poly' , 0.18 , Length , 'Gat.b') + , ('minArea' , 'poly' , 0.09 , Area , 'Gat.e') + , ('minSpacing' , 'poly' , 'activ' , 0.07 , Length , 'Gat.d') + , ('minExtension' , 'poly' , 'activ' , 0.180 , Length|Asymmetric, 'Gat.c') + , ('minGateExtension' , 'activ' , 'poly' , 0.23 , Length|Asymmetric, 'Act.c') + , ('minExtension' , 'activ' , 'poly' , 0.23 , Length|Asymmetric, 'Act.c') + + # 4.1.6 PPLUS (psdm) + , ('minWidth' , 'psdm' , 0.31 , Length , 'pSD.a') + , ('minSpacing' , 'psdm' , 0.31 , Length , 'pSD.b') + , ('minArea' , 'psdm' , 0.25 , Area , 'pSD.k') + , ('minSpacing' , 'psdm' , 'activ' , 0.180 , Length , 'pSD.d') + , ('minGateExtension' , 'psdm' , 'poly' , 0.00 , Length|Asymmetric, 'N/A') + , ('minOverlap' , 'psdm' , 'activ' , 0.30 , Length , 'pSD.e') + , ('minEnclosure' , 'psdm' , 'activ' , 0.180 , Length|Asymmetric, 'pSD.c') + , ('minStrapEnclosure' , 'psdm' , 'activ' , 0.180 , Length , 'pSD.c') + , ('minSpacing' , 'nsdm' , 'psdm' , 0.00 , Length , 'N/A') + , ('minEnclosure' , 'psdm' , 'poly' , 0.30 , Length|Asymmetric, 'pSD.i') + , ('minLengthEnclosure', 'psdm' , 'activ' , 0 , Length|Asymmetric, 'N/A') + , ('minWidthEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'psdm' , 'activ' , 0.180 , Length|Asymmetric, 'dup. pSD.c') + , ('minStrapEnclosure' , 'psdm' , 0.180 , Length , 'dup. pSD.c') + + # NPLUS (nsdm) no nSD rules + #, ('minWidth' , 'nsdm' , 0.38 , Length , 'nsd.1') + #, ('minSpacing' , 'nsdm' , 0.38 , Length , 'nsd.2') + #, ('minArea' , 'nsdm' , 0.265 , Area , 'nsd.10a') + #, ('minSpacing' , 'nsdm' , 'activ' , 0.130 , Length , 'nsd.7') + #, ('minGateExtension' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minOverlap' , 'nsdm' , 'activ' , 0 , Length , 'N/A') + #, ('minEnclosure' , 'nsdm' , 'activ' , 0.125 , Length|Asymmetric, 'nsd.5a') + #, ('minStrapEnclosure' , 'nsdm' , 'activ' , 0.125 , Length , 'nsd.5b') + #, ('minEnclosure' , 'nsdm' , 'nwm' , 0 , Length|Asymmetric, 'N/A') + #, ('minEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minLengthEnclosure', 'nsdm' , 'activ' , 0 , Length|Asymmetric, 'N/A') + #, ('minWidthEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minGateEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + #, ('minExtension' , 'nsdm' , 'activ' , 0.125 , Length|Asymmetric, 'dup. nsd.5a') + #, ('minStrapEnclosure' , 'nsdm' , 0.215 , Length , 'dup. nsd.5b') + + # LICM1 (CONT) + , ('minWidth' , 'cont' , 0.16 , Length , 'Cnt.a') + , ('minSpacing' , 'cont' , 0.18 , Length , 'Cnt.b') + , ('minGateSpacing' , 'cont' , 'poly' , 0.11 , Length|Asymmetric, 'Cnt.f') + , ('minSpacing' , 'cont' , 'poly' , 0.11 , Length|Asymmetric, 'Cnt.f') + , ('minSpacing' , 'cont' , 'activ' , 0.14 , Length , 'Cnt.e') + #, ('minSpacing' , 'cont' , 'activ' , 0.06 , Length , 'cont.5b') + , ('minEnclosure' , 'activ' , 'cont' , 0.07 , Length|Asymmetric, 'Cnt.c') + , ('minEnclosure' , 'poly' , 'cont' , 0.07 , Length|Asymmetric, 'Cnt.d') + #, ('minEnclosure' , 'psdm' , 'cont' , 0 , Length|Asymmetric, 'N/A') + #, ('minEnclosure' , 'nsdm' , 'cont' , 0 , Length|Asymmetric, 'N/A') + #, ('minGateEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'poly' , 'cont' , 0.07 , Length|Asymmetric, 'dup. Cnt.d') + , ('minExtension' , 'psdm' , 'cont' , 0.09 , Length|Asymmetric, 'Cnt.g2') + #, ('minExtension' , 'nsdm' , 'cont' , 0.25 , Length|Asymmetric, 'dup.') + + # LI1M (M1) + , ('minWidth' , 'M1' , 0.16 , Length , 'M1.a') + , ('minSpacing' , 'M1' , 0.18 , Length , 'M1.b') + , ('minArea' , 'M1' , 0.09 , Area , 'M1.d') + , ('minEnclosure' , 'M1' , 'cont' , 0.05 , Length|Asymmetric, 'M1.c1') + , ('minEnclosure' , 'M1' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # CTM1 (via12) + , ('minWidth' , 'via12' , 0.19 , Length , 'V1.a') + , ('minSpacing' , 'via12' , 0.22 , Length , 'V1.b') + + + # MM1 (M2) + , ('minWidth' , 'M2' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M2' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M2' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M2' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M2' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via23) + , ('minWidth' , 'via23' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via23' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M2' , 'via23' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M2' , 'via23' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + + # MM1 (M3) + , ('minWidth' , 'M3' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M3' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M3' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M3' , 'via23' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M3' , 'via23' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via34) + , ('minWidth' , 'via34' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via34' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M3' , 'via34' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M3' , 'via34' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + # MM1 (M4) + , ('minWidth' , 'M4' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M4' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M4' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M4' , 'via34' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M4' , 'via34' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via45) + , ('minWidth' , 'via45' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via45' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M4' , 'via45' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M4' , 'via45' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + # MM5 (M5) + , ('minWidth' , 'M5' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M5' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M5' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M5' , 'via45' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M5' , 'via45' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via56 TopVia1) + , ('minWidth' , 'via56' , 0.42 , Length , 'TV1.a') + , ('minSpacing' , 'via56' , 0.42 , Length , 'TV1.b') + , ('minEnclosure' , 'M5' , 'via56' , 0.1 , Length|Asymmetric, 'TV1.c') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M5' , 'via56' , 0.1 , Length|Asymmetric, 'dup. TV1.c') + + # MM6 (M6) TopMetal1 + , ('minWidth' , 'M6' , 1.64 , Length , 'TM1.a') + , ('minSpacing' , 'M6' , 1.64 , Length , 'TM1.b') + #, ('minArea' , 'M6' , 0.24 , Area , 'M5.4a') + , ('minEnclosure' , 'M6' , 'via56' , 0.10 , Length|Asymmetric, 'TV1.c') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M6' , 'via56' , 0.10 , Length|Asymmetric, 'dup. TV1.c ') + + # VIM (via56 TopVia2) + , ('minWidth' , 'via56' , 0.90 , Length , 'TV2.a') + , ('minSpacing' , 'via56' , 1.06 , Length , 'TV2.b') + , ('minEnclosure' , 'M6' , 'via56' , 0.5 , Length|Asymmetric, 'TV2.c') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M6' , 'via56' , 0.5 , Length|Asymmetric, 'dup. TV2.c') + + # MM5 (M7) TopMetal2 + , ('minWidth' , 'M7' , 2.00 , Length , 'TM2.a') + , ('minSpacing' , 'M7' , 2.00 , Length , 'TM2.b') + #, ('minArea' , 'M7' , 0.24 , Area , 'M5.4a') + , ('minEnclosure' , 'M7' , 'via56' , 0.50 , Length|Asymmetric, 'TV1.d') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M7' , 'via56' , 0.50 , Length|Asymmetric, 'dup. TV1.d ') + + + + #capm + #, ('minWidth' , 'metcap' , 1.0 , Length , 'capm.1') + #, ('minWidth' , 'metcapdum' , 0.5 , Length , '') + #, ('maxWidth' , 'metcap' , 300.0 , Length , '') + #, ('maxWidth' , 'metbot' , 350.0 , Length , '') + #, ('minSpacing' , 'metcap' , 0.84 , Length , 'capm.2a') + #, ('minSpacing' , 'metbot' , 0.8 , Length , 'metcap.2b') + #, ('minSpacing' , 'cut1' , 'metcap' , 0.50 , Length , '') + #, ('minSpacing' , 'cut2' , 'metcap' , 0.50 , Length , 'capm.5') + #, ('minSpacingOnMetbot', 'cut2' , 0.2 , Length , 'via34.2') + #, ('minSpacingOnMetbot', 'via34' , 0.2 , Length , 'via34.2') + #, ('minSpacingOnMetcap', 'cut2' , 0.2 , Length , 'via34.2') + #, ('minEnclosure' , 'M3' , 'metcap' , 0.14 , Length|Asymmetric, 'capm.3') + #, ('minEnclosure' , 'metbot' , 'cut1' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'metbot' , 'cut2' , 0.04 , Length|Asymmetric, 'via34.14') + #, ('minEnclosure' , 'metcap' , 'cut2' , 0.14 , Length|Asymmetric, 'capm.4') + #, ('minArea' , 'metcap' , 0 , Area , 'na') + #, ('minAreaInMetcap' , 'cut2' , 0 , Area , 'na') + #, ('MIMCap' , 1.25 , Unit , 'na') + #, ('MIMPerimeterCap' , 0.17 , Unit , 'na') + + + #capm + , ('minWidth' , 'capm' , 1.14 , Length , 'MIM.a') + #, ('minWidth' , 'capmdum' , 0.5 , Length , '') + #, ('maxWidth' , 'capm' , 30.0 , Length , '') + #, ('maxWidth' , 'metbot' , 35.0 , Length , '') + , ('minSpacing' , 'capm' , 0.60 , Length , 'MIM.b') + #, ('minSpacing' , 'M4' , 0.8 , Length , 'capm.2b') + , ('minSpacingWide1' , 'M3' , 0.8 , Length , 'capm.2b') + , ('minSpacing' , 'M6' , 'capm' , 0.60 , Length , 'MIM.e') + , ('minSpacing' , 'via34' , 'capm' , 0.50 , Length , 'capm.5') + , ('minSpacingOnMetBot', 'via34' , 0.2 , Length , 'via34.2') + , ('minSpacingOnMetCap', 'via34' , 0.2 , Length , 'via34.2') + , ('minSpacingOnMetBot', 'via23' , 0.2 , Length , 'via34.2 fake') + , ('minSpacingOnMetCap', 'via23' , 0.2 , Length , 'via34.2 fake') + , ('minEnclosure' , 'M5' , 'capm' , 0.60 , Length|Asymmetric, 'MIM.c') + #, ('minEnclosure' , 'M4' , 'via23' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'M4' , 'via34' , 0.04 , Length|Asymmetric, 'via34.14') + #, ('minEnclosure' , 'capm' , 'via23' , 0.14 , Length|Asymmetric, 'capm.4 fake') + , ('minEnclosure' , 'capm' , 'via56' , 0.36 , Length|Asymmetric, 'MIM.d') + , ('minArea' , 'capm' , 1.30 , Area , 'MIM.f') + , ('minAreaInMetcap' , 'via34' , 0 , Area , 'na') + , ('MIMCap' , 1.25 , Unit , 'na') + , ('MIMPerimeterCap' , 0.17 , Unit , 'na') + , ('PIPCap' , 1.25 , Unit , 'na') + , ('PIPPerimeterCap' , 0.17 , Unit , 'na') + + ) + + +def _loadDtr (): + """ + Load design kit physical rules for IHP 130nm. + """ + loadAnalogTechno( analogTechnologyTable, __file__ ) + + +def _loadDevices (): + addDevice( name = 'DifferentialPairBulkConnected' + #, spice = spiceDir+'DiffPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'DifferentialPairBulkUnconnected' + #, spice = spiceDir+'DiffPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'LevelShifterBulkUnconnected' + #, spice = spiceDir+'LevelShifterBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S1', 'S2', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.LS_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.LS_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.LS_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.LS_interdigitated.py' ) + ) + ) + addDevice( name = 'TransistorBulkConnected' + #, spice = spiceDir+'TransistorBulkConnected.spi' + , connectors = ( 'D', 'G', 'S' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'TransistorBulkUnconnected' + #, spice = spiceDir+'TransistorBulkUnconnected.spi' + , connectors = ( 'D', 'G', 'S', 'B' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkConnected' + #, spice = spiceDir+'CCPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkUnconnected' + #, spice = spiceDir+'CCPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkConnected' + #, spice = spiceDir+'CommonSourcePairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkUnconnected' + #, spice = spiceDir+'CommonSourcePairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkConnected' + #, spice = spiceDir+'CurrMirBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkUnconnected' + #, spice = spiceDir+'CurrMirBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'MultiCapacitor' + #, spice = spiceDir+'MIM_OneCapacitor.spi' + , connectors = ( 'T1', 'B1' ) + , layouts = ( ('Matrix', 'coriolis.oroshi.multicapacitor.py' ), + ) + ) + #addDevice( name = 'Resistor' + # #, spice = spiceDir+'MIM_OneCapacitor.spi' + # , connectors = ( 'PIN1', 'PIN2' ) + # , layouts = ( ('Snake', 'coriolis.oroshi.resistorsnake.py' ), + # ) + # ) + + +def _setup_techno ( coriolisTechDir ): + ShellEnv.RDS_TECHNO_NAME = (coriolisTechDir / 'scmos2m1u_nsx2' / 'scmos2m1u.rds').as_posix() + ShellEnv.GRAAL_TECHNO_NAME = (coriolisTechDir / 'scmos2m1u_nsx2' / 'symbolic.graal' ).as_posix() + ShellEnv.DREAL_TECHNO_NAME = (coriolisTechDir / 'scmos2m1u_nsx2' / 'symbolic.dreal' ).as_posix() + + db = DataBase.getDB() + CRL.System.get() + + tech = Technology.create(db, 'scmos2m1u_nsx2') + + DbU.setPrecision( 2 ) + DbU.setPhysicalsPerGrid( 0.001, DbU.UnitPowerMicro ) + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + cfg.gdsDriver.metricDbu = 1e-09 + cfg.gdsDriver.dbuPerUu = 0.001 + DbU.setGridsPerLambda ( 30 ) + DbU.setSymbolicSnapGridStep( DbU.fromGrid( 1.0 )) + DbU.setPolygonStep ( DbU.fromGrid( 1.0 )) + DbU.setStringMode ( DbU.StringModePhysical, DbU.UnitPowerMicro ) + + createBL( tech, 'nwm' , BasicLayer.Material.nWell , size=u(0.62), spacing=u(0.62), gds2Layer= 31, gds2DataType= 0 ) + createBL( tech, 'nsdm' , BasicLayer.Material.nImplant, size=u(0.31), spacing=u(0.31), area=0.25, gds2Layer= 7, gds2DataType= 0 ) + createBL( tech, 'psdm' , BasicLayer.Material.pImplant, size=u(0.31), spacing=u(0.31), area=0.25, gds2Layer= 14, gds2DataType= 0 ) + #createBL( tech, 'hvi' , BasicLayer.Material.other , gds2Layer= 75, gds2DataType= 20 ) + createBL( tech, 'activ.pin' , BasicLayer.Material.other , gds2Layer= 1, gds2DataType= 2 ) + #createBL( tech, 'activ.block', BasicLayer.Material.blockage, gds2Layer=1, gds2DataType= 23 ) + createBL( tech, 'poly.pin' , BasicLayer.Material.other , gds2Layer= 5, gds2DataType= 2 ) + #createBL( tech, 'poly.block' , BasicLayer.Material.blockage, gds2Layer=5, gds2DataType= 23 ) + createBL( tech, 'M1.pin' , BasicLayer.Material.other , gds2Layer= 8, gds2DataType= 2 ) + #createBL( tech, 'M1.block' , BasicLayer.Material.blockage, gds2Layer=8, gds2DataType= 23 ) + createBL( tech, 'M2.pin' , BasicLayer.Material.other , gds2Layer= 10, gds2DataType= 2 ) + #createBL( tech, 'M2.block' , BasicLayer.Material.blockage, gds2Layer=10, gds2DataType= 23 ) + createBL( tech, 'M3.pin' , BasicLayer.Material.other , gds2Layer= 30, gds2DataType= 2 ) + #createBL( tech, 'M3.block' , BasicLayer.Material.blockage, gds2Layer=30, gds2DataType= 23 ) + createBL( tech, 'M4.pin' , BasicLayer.Material.other , gds2Layer= 50, gds2DataType= 2 ) + #createBL( tech, 'M4.block' , BasicLayer.Material.blockage, gds2Layer=50, gds2DataType=23 ) + createBL( tech, 'M5.pin' , BasicLayer.Material.other , gds2Layer= 67, gds2DataType= 2 ) + #createBL( tech, 'M5.block' , BasicLayer.Material.blockage, gds2Layer=67, gds2DataType=23 ) + createBL( tech, 'M6.pin' , BasicLayer.Material.other , gds2Layer= 126, gds2DataType= 2 ) + #createBL( tech, 'M6.block' , BasicLayer.Material.blockage, gds2Layer=126, gds2DataType=23 ) + #createBL( tech, 'cont.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 30 ) + #createBL( tech, 'via12.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 50 ) + #createBL( tech, 'via23.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 70 ) + #createBL( tech, 'via34.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 90 ) + #createBL( tech, 'via45.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=110 ) + #createBL( tech, 'via56.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=130 ) + createBL( tech, 'activ' , BasicLayer.Material.active , size=u(0.15), spacing=u(0.21), gds2Layer= 1, gds2DataType= 0 ) + createBL( tech, 'poly' , BasicLayer.Material.poly , size=u(0.13), spacing=u(0.18), gds2Layer= 5, gds2DataType= 0 ) + createBL( tech, 'cont' , BasicLayer.Material.cut , size=u(0.16), spacing=u(0.18), gds2Layer= 6, gds2DataType= 0 ) + createBL( tech, 'M1' , BasicLayer.Material.metal , size=u(0.16), spacing=u(0.18), area=0.009, gds2Layer= 8, gds2DataType= 0 ) + createBL( tech, 'via12' , BasicLayer.Material.cut , size=u(0.19), spacing=u(0.22), gds2Layer= 19, gds2DataType= 0 ) + createBL( tech, 'M2' , BasicLayer.Material.metal , size=u(0.20), spacing=u(0.21), area=0.144, gds2Layer= 10, gds2DataType= 0 ) + createBL( tech, 'via23' , BasicLayer.Material.cut , size=u(0.19), spacing=u(0.22), gds2Layer= 29, gds2DataType= 0 ) + createBL( tech, 'M3' , BasicLayer.Material.metal , size=u(0.19), spacing=u(0.21), area=0.144, gds2Layer= 30, gds2DataType= 0 ) + createBL( tech, 'capm' , BasicLayer.Material.metal ) + createBL( tech, 'via34' , BasicLayer.Material.cut , size=u(0.19 ), spacing=u(0.22), gds2Layer= 49, gds2DataType= 0 ) + createBL( tech, 'M4' , BasicLayer.Material.metal , size=u(0.19 ), spacing=u(0.21 ), area=0.144, gds2Layer= 50, gds2DataType= 0 ) + createBL( tech, 'via45' , BasicLayer.Material.cut , size=u(0.19 ), spacing=u(0.22), gds2Layer= 49, gds2DataType= 0 ) + createBL( tech, 'M5' , BasicLayer.Material.metal , size=u(0.19 ), spacing=u(0.21 ), area=0.144, gds2Layer=67, gds2DataType= 0 ) + createBL( tech, 'via56' , BasicLayer.Material.cut , size=u(0.42 ), spacing=u(0.42 ), gds2Layer= 125, gds2DataType= 0 ) + createBL( tech, 'M6' , BasicLayer.Material.metal , size=u(1.64), spacing=u(1.64), gds2Layer= 126, gds2DataType= 0 ) + createBL( tech, 'hvtp' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 78, gds2DataType= 44 ) + createBL( tech, 'lvtn' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer=125, gds2DataType= 44 ) + createBL( tech, 'areaid_sc' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 4 ) + createBL( tech, 'pad' , BasicLayer.Material.cut , size=u(40.0), spacing=u(1.27), gds2Layer= 76, gds2DataType= 20 ) + createBL( tech, 'areaid_diode' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 23 ) + createBL( tech, 'pnp' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 44 ) + createBL( tech, 'diffres' , BasicLayer.Material.other , gds2Layer= 65, gds2DataType= 13 ) + createBL( tech, 'npn' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 20 ) + createBL( tech, 'polyres' , BasicLayer.Material.other , gds2Layer= 66, gds2DataType= 13 ) + createBL( tech, 'prBoundary' , BasicLayer.Material.other , gds2Layer=235, gds2DataType= 4 ) + + tech.addLayerAlias( 'M2', 'met1' ) + tech.addLayerAlias( 'M3', 'met2' ) + tech.addLayerAlias( 'M4', 'met3' ) + tech.addLayerAlias( 'M5', 'met4' ) + tech.addLayerAlias( 'M6', 'met5' ) + + # ViaLayers + createVia( tech, 'li_via12_M2' , 'M1' , 'via12', 'M2', u(0.17) ) + createVia( tech, 'M2_via_M3' , 'M2' , 'via23' , 'M3', u(0.15) ) + createVia( tech, 'M3_via34_M4' , 'M3' , 'via34', 'M4', u(0.2 ) ) + createVia( tech, 'M4_via45_M5' , 'M4' , 'via45', 'M5', u(0.2 ) ) + createVia( tech, 'M5_via56_M6' , 'M5' , 'via56', 'M6', u(0.8 ) ) + createVia( tech, 'capm_via56', 'capm', 'via56', 'M6', u(0.2 ) ) + + # Blockages + #ech.getLayer('activ' ).setBlockageLayer( tech.getLayer('activ.block') ) + #ech.getLayer('poly') .setBlockageLayer( tech.getLayer('poly.block') ) + #ech.getLayer('M1') .setBlockageLayer( tech.getLayer('M1.block') ) + #ech.getLayer('M2') .setBlockageLayer( tech.getLayer('M2.block') ) + #ech.getLayer('M3') .setBlockageLayer( tech.getLayer('M3.block') ) + #ech.getLayer('M4') .setBlockageLayer( tech.getLayer('M4.block') ) + #ech.getLayer('M5') .setBlockageLayer( tech.getLayer('M5.block') ) + #ech.getLayer('M6') .setBlockageLayer( tech.getLayer('M6.block') ) + #ech.getLayer('cont' ) .setBlockageLayer( tech.getLayer('cont.block') ) + #ech.getLayer('via12') .setBlockageLayer( tech.getLayer('via12.block') ) + #ech.getLayer('via23') .setBlockageLayer( tech.getLayer('via23.block') ) + #ech.getLayer('via34') .setBlockageLayer( tech.getLayer('via34.block') ) + #ech.getLayer('via45') .setBlockageLayer( tech.getLayer('via45.block') ) + #ech.getLayer('via56') .setBlockageLayer( tech.getLayer('via56.block') ) + + # Coriolis internal layers + createBL( tech, 'text.cell' , BasicLayer.Material.other, ) + createBL( tech, 'text.instance', BasicLayer.Material.other, ) + createBL( tech, 'SPL1' , BasicLayer.Material.other, ) + createBL( tech, 'AutoLayer' , BasicLayer.Material.other, ) + createBL( tech, 'gmetalh' , BasicLayer.Material.metal, ) + createBL( tech, 'gcontact' , BasicLayer.Material.cut, ) + createBL( tech, 'gmetalv' , BasicLayer.Material.metal, ) + + # Resistors + # ResistorLayer.create(tech, 'poly_res', 'poly', 'polyres') + # ResistorLayer.create(tech, 'active_res', 'activ' , 'diffres') + + # Transistors + # GateLayer.create(tech, 'hvmosgate' , 'activ' , 'poly', 'hvi') + # GateLayer.create(tech, 'mosgate' , 'activ' , 'poly') + # GateLayer.create(tech, 'mosgate_sc', 'activ' , 'poly') + # TransistorLayer.create(tech, 'nfet_01v8' , 'mosgate' , 'nsdm') + # TransistorLayer.create(tech, 'nfet_01v8_lvt' , 'mosgate' , ('nsdm', 'lvtn')) + # TransistorLayer.create(tech, 'nfet_01v8_sc' , 'mosgate_sc', 'nsdm') + # TransistorLayer.create(tech, 'nfet_g5v0d10v5', 'hvmosgate' , 'nsdm') + # TransistorLayer.create(tech, 'pfet_01v8' , 'mosgate' , 'psdm', 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_hvt' , 'mosgate' , ('psdm', 'hvtp'), 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_lvt' , 'mosgate' , ('psdm', 'lvtn'), 'nwm') + # TransistorLayer.create(tech, 'pfet_g5v0d10v5', 'hvmosgate' , 'psdm', 'nwm') + + # Bipolars + # Not implemented: Bipolar 'pnp_05v5_w0u68l0u68' + # Not implemented: Bipolar 'npn_05v5_w1u00l2u00' + # Not implemented: Bipolar 'pnp_05v5_w3u40l3u40' + # Not implemented: Bipolar 'npn_05v5_w1u00l1u00' + + +def _setup_display (): + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [black] + + threshold = 0.2 if Viewer.Graphics.isHighDpi() else 0.1 + + style = Viewer.DisplayStyle( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - black background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + # Viewer. + style.addDrawingStyle( group='Viewer', name='fallback' , color=toRGB('Gray238' ), border=1, pattern='55AA55AA55AA55AA' ) + style.addDrawingStyle( group='Viewer', name='background' , color=toRGB('Gray50' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='rubber' , color=toRGB('192,0,192' ), border=4, threshold=0.02 ) + style.addDrawingStyle( group='Viewer', name='phantom' , color=toRGB('Seashell4' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries' , color=toRGB('wheat1' ), border=2, pattern='0000000000000000', threshold=0 ) + style.addDrawingStyle( group='Viewer', name='marker' , color=toRGB('80,250,80' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionDraw' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionFill' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='grid' , color=toRGB('White' ), border=1, threshold=2.0 ) + style.addDrawingStyle( group='Viewer', name='spot' , color=toRGB('White' ), border=2, threshold=6.0 ) + style.addDrawingStyle( group='Viewer', name='ghost' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='text.ruler' , color=toRGB('White' ), border=1, threshold= 0.0 ) + style.addDrawingStyle( group='Viewer', name='text.instance' , color=toRGB('White' ), border=1, threshold=400.0 ) + style.addDrawingStyle( group='Viewer', name='text.reference', color=toRGB('White' ), border=1, threshold=200.0 ) + style.addDrawingStyle( group='Viewer', name='undef' , color=toRGB('Violet' ), border=0, pattern='2244118822441188' ) + + # Active Layers. + style.addDrawingStyle(group='Active Layers', name='nwm' , color=toRGB('Tan' ), pattern=toHexa('urgo.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='nsdm' , color=toRGB('LawnGreen'), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='psdm' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='hvtp' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='lvtn' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='activ' , color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='activ.pin', color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly.pin' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + + # Routing Layers. + style.addDrawingStyle(group='Routing Layers', name='M1' , color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M1.pin', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M2' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M2.pin', color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M3' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M3.pin', color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M4' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M4.pin', color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M5' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M5.pin', color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M6' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M6.pin', color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + + # Cuts (VIA holes). + style.addDrawingStyle(group='Cuts (VIA holes', name='cont' , color=toRGB('0,150,150'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via12' , color=toRGB('Aqua' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via23' , color=toRGB('LightPink'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via34' , color=toRGB('Green' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via45' , color=toRGB('Yellow' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via56' , color=toRGB('Violet' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='pad' , color=toRGB('Red' ), threshold=threshold) + + # Blockages. + #style.addDrawingStyle(group='Blockages', name='activ.block', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='poly.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M1.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M2.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M3.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M4.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M5.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M6.block' , color=toRGB('Blue' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='cont.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via12.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via23.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via34.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via45.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via56.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) +# + # Knick & Kite. + style.addDrawingStyle( group='Knik & Kite', name='SPL1' , color=toRGB('Red' ) ) + style.addDrawingStyle( group='Knik & Kite', name='AutoLayer' , color=toRGB('Magenta' ) ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalh' , color=toRGB('128,255,200'), pattern=toHexa('antislash2.32' ), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalv' , color=toRGB('200,200,255'), pattern=toHexa('light_antihash1.8'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gcontact' , color=toRGB('255,255,190'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::Edge' , color=toRGB('255,255,190'), pattern='0000000000000000' , border=4, threshold=0.02 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::GCell', color=toRGB('255,255,190'), pattern='0000000000000000' , border=2, threshold=threshold ) + + Viewer.Graphics.addStyle( style ) + + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [white]. + + style = Viewer.DisplayStyle( 'Alliance.Classic [white]' ) + style.inheritFrom( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - white background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + style.addDrawingStyle( group='Viewer', name='background', color=toRGB('White'), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground', color=toRGB('Black'), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries', color=toRGB('Black'), border=1, pattern='0000000000000000' ) + Viewer.Graphics.addStyle( style ) + + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + +def setup ( coriolisTechDir ): + _setup_techno( coriolisTechDir ) + _setup_display() + try: + from .techno_symb import setup as setupSymbolic + except: + pass + else: + setupSymbolic() + _loadDtr() + _loadDevices() + diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/techno_symb.py b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/techno_symb.py new file mode 100644 index 000000000..7993a9a04 --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/coriolis/scmos2m1u_nsx2/techno_symb.py @@ -0,0 +1,284 @@ + +from coriolis.helpers import l, u, n +from coriolis.Hurricane import DataBase, Technology, Layer, BasicLayer, DiffusionLayer, \ + TransistorLayer, RegularLayer, ContactLayer, ViaLayer + +__all__ = [ 'setup' ] + + +def setup (): + tech = DataBase.getDB().getTechnology() + tech.addLayerAlias( 'nwm' , 'nWell' ) + tech.addLayerAlias( 'activ' , 'active' ) + #tech.addLayerAlias( 'poly' , 'poly' ) + tech.addLayerAlias( 'psdm' , 'pImplant' ) + tech.addLayerAlias( 'nsdm' , 'nImplant' ) + tech.addLayerAlias( 'cont' , 'cut0' ) + tech.addLayerAlias( 'M1' , 'metal1' ) + tech.addLayerAlias( 'via12' , 'cut1' ) + tech.addLayerAlias( 'M2' , 'metal2' ) + tech.addLayerAlias( 'via23' , 'cut2' ) + tech.addLayerAlias( 'M3' , 'metal3' ) + tech.addLayerAlias( 'via34' , 'cut3' ) + tech.addLayerAlias( 'M4' , 'metal4' ) + tech.addLayerAlias( 'via45' , 'cut4' ) + tech.addLayerAlias( 'M5' , 'metla5' ) + tech.addLayerAlias( 'via56' , 'cut5' ) + tech.addLayerAlias( 'M6' , 'metal6' ) + tech.addLayerAlias( 'M1.block', 'blockage1' ) + tech.addLayerAlias( 'M2.block', 'blockage2' ) + tech.addLayerAlias( 'M3.block', 'blockage3' ) + tech.addLayerAlias( 'M4.block', 'blockage4' ) + tech.addLayerAlias( 'M5.block', 'blockage5' ) + tech.addLayerAlias( 'M6.block', 'blockage6' ) + tech.addLayerAlias( 'capm' , 'metcap' ) + tech.addLayerAlias( 'capm' , 'metcapdum' ) + tech.addLayerAlias( 'M5' , 'metbot' ) + + nWell = tech.getBasicLayer( 'nwm' ) + active = tech.getBasicLayer( 'activ' ) + poly = tech.getBasicLayer( 'poly' ) + pImplant = tech.getBasicLayer( 'psdm' ) + nImplant = tech.getBasicLayer( 'nsdm' ) + cut0 = tech.getBasicLayer( 'cont' ) + metal1 = tech.getBasicLayer( 'M1' ) + cut1 = tech.getBasicLayer( 'via12' ) + metal2 = tech.getBasicLayer( 'M2' ) + cut2 = tech.getBasicLayer( 'via23' ) + metal3 = tech.getBasicLayer( 'M3' ) + cut3 = tech.getBasicLayer( 'via34' ) + metal4 = tech.getBasicLayer( 'M4' ) + cut4 = tech.getBasicLayer( 'via45' ) + metal5 = tech.getBasicLayer( 'M5' ) + cut5 = tech.getBasicLayer( 'via56' ) + metal6 = tech.getBasicLayer( 'M6' ) + blockage1 = tech.getBasicLayer( 'blockage1' ) + blockage2 = tech.getBasicLayer( 'blockage2' ) + blockage3 = tech.getBasicLayer( 'blockage3' ) + blockage4 = tech.getBasicLayer( 'blockage4' ) + blockage5 = tech.getBasicLayer( 'blockage5' ) + blockage6 = tech.getBasicLayer( 'blockage6' ) + + # Composite/Symbolic layers. + NWELL = RegularLayer .create( tech, 'NWELL' , nWell ) + #PWELL = RegularLayer .create( tech, 'PWELL' , pWell ) + NTIE = DiffusionLayer .create( tech, 'NTIE' , nImplant , active, nWell) + PTIE = DiffusionLayer .create( tech, 'PTIE' , pImplant , active, None) + NDIF = DiffusionLayer .create( tech, 'NDIF' , nImplant , active, None ) + PDIF = DiffusionLayer .create( tech, 'PDIF' , pImplant , active, None ) + GATE = DiffusionLayer .create( tech, 'GATE' , poly , active, None ) + NTRANS = TransistorLayer.create( tech, 'NTRANS' , nImplant , active, poly, None ) + PTRANS = TransistorLayer.create( tech, 'PTRANS' , pImplant , active, poly, nWell ) + POLY = RegularLayer .create( tech, 'POLY' , poly ) + METAL1 = RegularLayer .create( tech, 'METAL1' , metal1 ) + METAL2 = RegularLayer .create( tech, 'METAL2' , metal2 ) + METAL3 = RegularLayer .create( tech, 'METAL3' , metal3 ) + METAL4 = RegularLayer .create( tech, 'METAL4' , metal4 ) + METAL5 = RegularLayer .create( tech, 'METAL5' , metal5 ) + METAL6 = RegularLayer .create( tech, 'METAL6' , metal6 ) + CONT_BODY_N = ContactLayer .create( tech, 'CONT_BODY_N', nImplant , active, cut0, metal1, None ) + CONT_BODY_P = ContactLayer .create( tech, 'CONT_BODY_P', pImplant , active, cut0, metal1, None ) + CONT_DIF_N = ContactLayer .create( tech, 'CONT_DIF_N' , nImplant , active, cut0, metal1, None ) + CONT_DIF_P = ContactLayer .create( tech, 'CONT_DIF_P' , pImplant , active, cut0, metal1, None ) + CONT_POLY = ViaLayer .create( tech, 'CONT_POLY' , poly, cut0, metal1 ) + + # VIAs for symbolic technologies. + VIA12 = ViaLayer .create( tech, 'VIA12' , metal1, cut1, metal2 ) + VIA23 = ViaLayer .create( tech, 'VIA23' , metal2, cut2, metal3 ) + #VIA23cap = ViaLayer .create( tech, 'VIA23cap' , metcap, cut2, metal3 ) + VIA34 = ViaLayer .create( tech, 'VIA34' , metal3, cut3, metal4 ) + VIA45 = ViaLayer .create( tech, 'VIA45' , metal4, cut4, metal5 ) + VIA56 = ViaLayer .create( tech, 'VIA56' , metal5, cut5, metal6 ) + #BLOCKAGE1 = RegularLayer.create( tech, 'BLOCKAGE1' , blockage1 ) + #BLOCKAGE2 = RegularLayer.create( tech, 'BLOCKAGE2' , blockage2 ) + #BLOCKAGE3 = RegularLayer.create( tech, 'BLOCKAGE3' , blockage3 ) + #BLOCKAGE4 = RegularLayer.create( tech, 'BLOCKAGE4' , blockage4 ) + #BLOCKAGE5 = RegularLayer.create( tech, 'BLOCKAGE5' , blockage5 ) + #BLOCKAGE6 = RegularLayer.create( tech, 'BLOCKAGE6' , blockage6 ) + + tech.setSymbolicLayer( CONT_BODY_N.getName() ) + tech.setSymbolicLayer( CONT_BODY_P.getName() ) + tech.setSymbolicLayer( CONT_DIF_N .getName() ) + tech.setSymbolicLayer( CONT_DIF_P .getName() ) + tech.setSymbolicLayer( CONT_POLY .getName() ) + tech.setSymbolicLayer( POLY .getName() ) + tech.setSymbolicLayer( METAL1 .getName() ) + tech.setSymbolicLayer( METAL2 .getName() ) + tech.setSymbolicLayer( METAL3 .getName() ) + tech.setSymbolicLayer( METAL4 .getName() ) + tech.setSymbolicLayer( METAL5 .getName() ) + tech.setSymbolicLayer( METAL6 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE1 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE2 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE3 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE4 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE5 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE6 .getName() ) + tech.setSymbolicLayer( VIA12 .getName() ) + tech.setSymbolicLayer( VIA23 .getName() ) + tech.setSymbolicLayer( VIA34 .getName() ) + tech.setSymbolicLayer( VIA45 .getName() ) + tech.setSymbolicLayer( VIA56 .getName() ) + + NWELL.setExtentionCap( nWell, l(0.0) ) + #PWELL.setExtentionCap( pWell, l(0.0) ) + + NTIE.setMinimalSize ( l(3.0) ) + NTIE.setExtentionCap ( nWell , l(1.5) ) + NTIE.setExtentionWidth( nWell , l(0.5) ) + NTIE.setExtentionCap ( nImplant, l(1.0) ) + NTIE.setExtentionWidth( nImplant, l(0.5) ) + NTIE.setExtentionCap ( active , l(0.5) ) + NTIE.setExtentionWidth( active , l(0.0) ) + + PTIE.setMinimalSize ( l(3.0) ) + PTIE.setExtentionCap ( nWell , l(1.5) ) + PTIE.setExtentionWidth( nWell , l(0.5) ) + PTIE.setExtentionCap ( nImplant, l(1.0) ) + PTIE.setExtentionWidth( nImplant, l(0.5) ) + PTIE.setExtentionCap ( active , l(0.5) ) + PTIE.setExtentionWidth( active , l(0.0) ) + + NDIF.setMinimalSize ( l(3.0) ) + NDIF.setExtentionCap ( nImplant, l(1.0) ) + NDIF.setExtentionWidth( nImplant, l(0.5) ) + NDIF.setExtentionCap ( active , l(0.5) ) + NDIF.setExtentionWidth( active , l(0.0) ) + + PDIF.setMinimalSize ( l(3.0) ) + PDIF.setExtentionCap ( pImplant, l(1.0) ) + PDIF.setExtentionWidth( pImplant, l(0.5) ) + PDIF.setExtentionCap ( active , l(0.5) ) + PDIF.setExtentionWidth( active , l(0.0) ) + + GATE.setMinimalSize ( l(1.0) ) + GATE.setExtentionCap ( poly , l(1.5) ) + + NTRANS.setMinimalSize ( l( 1.0) ) + NTRANS.setExtentionCap ( nImplant, l(-1.0) ) + NTRANS.setExtentionWidth( nImplant, l( 2.5) ) + NTRANS.setExtentionCap ( active , l(-1.5) ) + NTRANS.setExtentionWidth( active , l( 2.0) ) + + PTRANS.setMinimalSize ( l( 1.0) ) + PTRANS.setExtentionCap ( nWell , l(-1.0) ) + PTRANS.setExtentionWidth( nWell , l( 4.5) ) + PTRANS.setExtentionCap ( pImplant, l(-1.0) ) + PTRANS.setExtentionWidth( pImplant, l( 4.0) ) + PTRANS.setExtentionCap ( active , l(-1.5) ) + PTRANS.setExtentionWidth( active , l( 3.0) ) + + POLY .setMinimalSize ( l(1.0) ) + POLY .setExtentionCap ( poly , l(0.5) ) + #POLY2.setMinimalSize ( l(1.0) ) + #POLY2.setExtentionCap ( poly , l(0.5) ) + + METAL1 .setMinimalSize ( l(1.0) ) + METAL1 .setExtentionCap ( metal1 , l(0.5) ) + METAL2 .setMinimalSize ( l(1.0) ) + METAL2 .setExtentionCap ( metal2 , l(1.0) ) + METAL3 .setMinimalSize ( l(1.0) ) + METAL3 .setExtentionCap ( metal3 , l(1.0) ) + METAL4 .setMinimalSize ( l(1.0) ) + METAL4 .setExtentionCap ( metal4 , l(1.0) ) + METAL4 .setMinimalSpacing( l(3.0) ) + METAL5 .setMinimalSize ( l(2.0) ) + METAL5 .setExtentionCap ( metal5 , l(1.0) ) + #METAL6 .setMinimalSize ( l(2.0) ) + #METAL6 .setExtentionCap ( metal6 , l(1.0) ) + #METAL7 .setMinimalSize ( l(2.0) ) + #METAL7 .setExtentionCap ( metal7 , l(1.0) ) + #METAL8 .setMinimalSize ( l(2.0) ) + #METAL8 .setExtentionCap ( metal8 , l(1.0) ) + #METAL9 .setMinimalSize ( l(2.0) ) + #METAL9 .setExtentionCap ( metal9 , l(1.0) ) + #METAL10.setMinimalSize ( l(2.0) ) + #METAL10.setExtentionCap ( metal10 , l(1.0) ) + + # Contacts (i.e. Active <--> Metal) (symbolic). + CONT_BODY_N.setMinimalSize( l( 1.0) ) + CONT_BODY_N.setEnclosure ( nWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( nImplant, l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( active , l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_BODY_P.setMinimalSize( l( 1.0) ) + #CONT_BODY_P.setEnclosure ( pWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( pImplant, l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( active , l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_N.setMinimalSize( l( 1.0) ) + CONT_DIF_N.setEnclosure ( nImplant, l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_P.setMinimalSize( l( 1.0) ) + CONT_DIF_P.setEnclosure ( pImplant, l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_POLY.setMinimalSize( l( 1.0) ) + CONT_POLY.setEnclosure ( poly , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_POLY.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + # VIAs (i.e. Metal <--> Metal) (symbolic). + VIA12 .setMinimalSize ( l( 1.0) ) + VIA12 .setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setEnclosure ( metal2 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setMinimalSpacing( l( 4.0) ) + VIA23 .setMinimalSize ( l( 1.0) ) + VIA23 .setEnclosure ( metal2 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setEnclosure ( metal3 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setMinimalSpacing( l( 4.0) ) + VIA34 .setMinimalSize ( l( 1.0) ) + VIA34 .setEnclosure ( metal3 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setEnclosure ( metal4 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setMinimalSpacing( l( 4.0) ) + VIA45 .setMinimalSize ( l( 1.0) ) + VIA45 .setEnclosure ( metal4 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setMinimalSpacing( l( 4.0) ) + #VIA56 .setMinimalSize ( l( 1.0) ) + #VIA56 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setMinimalSpacing( l( 4.0) ) + #VIA67 .setMinimalSize ( l( 1.0) ) + #VIA67 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSize ( l( 1.0) ) + #VIA78 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA89 .setMinimalSize ( l( 1.0) ) + #VIA89 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setMinimalSpacing( l( 4.0) ) + #VIA910.setMinimalSize ( l( 1.0) ) + #VIA910.setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setEnclosure ( metal10 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setMinimalSpacing( l( 4.0) ) + + # Blockages (symbolic). + #BLOCKAGE1 .setMinimalSize ( l( 1.0) ) + #BLOCKAGE1 .setExtentionCap( blockage1 , l( 0.5) ) + #BLOCKAGE2 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE2 .setExtentionCap( blockage2 , l( 0.5) ) + #BLOCKAGE3 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE3 .setExtentionCap( blockage3 , l( 0.5) ) + #BLOCKAGE4 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE4 .setExtentionCap( blockage4 , l( 0.5) ) + #BLOCKAGE5 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE5 .setExtentionCap( blockage5 , l( 1.0) ) + #BLOCKAGE6 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE6 .setExtentionCap( blockage6 , l( 1.0) ) + #BLOCKAGE7 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE7 .setExtentionCap( blockage7 , l( 1.0) ) + #BLOCKAGE8 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE8 .setExtentionCap( blockage8 , l( 1.0) ) + #BLOCKAGE9 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE9 .setExtentionCap( blockage9 , l( 1.0) ) + #BLOCKAGE10.setMinimalSize ( l( 2.0) ) + #BLOCKAGE10.setExtentionCap( blockage10, l( 1.0) ) diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/LICENSE b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/LICENSE new file mode 100644 index 000000000..d159169d1 --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/LICENSE @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/MOSIS_SCMOS.lyp b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/MOSIS_SCMOS.lyp new file mode 100644 index 000000000..2aa688d34 --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/MOSIS_SCMOS.lyp @@ -0,0 +1,2518 @@ + + + + #ff80ff + #ff80ff + 0 + 0 + C56 + + true + true + false + 2 + false + false + 0 + DeepNwell.drawing - 38/0 + 38/0@1 + + + #ff8000 + #ff8000 + 0 + 0 + C56 + + true + true + false + 2 + false + false + 0 + Nwell.drawing - 42/0 + 42/0@1 + + + #ff8000 + #ff8000 + 0 + 0 + C61 + + true + true + false + 1 + false + false + 0 + Pwell.drawing - 41/0 + 41/0@1 + + + #ff8000 + #ff8000 + 0 + 0 + C68 + + true + true + false + 1 + false + false + 0 + CapWell.drawing - 59/0 + 59/0@1 + + + #00ff00 + #00ff00 + 0 + 0 + C58 + + true + true + false + 1 + false + false + 0 + Active.drawing - 43/0 + 43/0@1 + + + #8c8ca6 + #8c8ca6 + 0 + 0 + C58 + + true + true + false + 1 + false + false + 0 + ThickActive.drawing - 60/0 + 60/0@1 + + + #ffff00 + #ffff00 + 0 + 0 + I1 + + true + true + false + 1 + false + false + 0 + pBase.drawing - 60/0 + 60/0@1 + + + #ff0000 + #ff0000 + 0 + 0 + I11 + + true + true + false + 1 + false + false + 0 + Poly.drawing - 46/0 + 46/0@1 + + + #ff0000 + #ff0000 + 0 + 0 + I1 + + true + true + false + 1 + false + false + 0 + Poly.text - 46/1 + 46/1@1 + + + #008050 + #008050 + 0 + 0 + I1 + + true + true + false + 1 + false + false + 0 + SiBlock.drawing - 29/0 + 29/0@1 + + + #ff80a8 + #ff80a8 + 0 + 0 + C57 + + true + true + false + 1 + false + false + 0 + Nselect.drawing - 45/0 + 45/0@1 + + + #bf4026 + #bf4026 + 0 + 0 + C76 + + true + true + false + 1 + false + false + 0 + Pselect.drawing - 44/0 + 44/0@1 + + + #ff8000 + #ff8000 + 0 + 0 + C76 + + true + true + false + 1 + false + false + 0 + Poly2.drawing - 56/0 + 56/0@1 + + + #802626 + #802626 + 0 + 0 + C66 + + true + true + false + 1 + false + false + 0 + HiRes.drawing - 34/0 + 34/0@1 + + + #00cc66 + #00cc66 + 0 + 0 + I1 + + true + true + false + 1 + false + false + 0 + Contact.drawing - 25/0 + 25/0@1 + + + #00cc66 + #00cc66 + 0 + 0 + I1 + + true + true + false + 2 + false + true + 0 + ContactPoly.drawing - 47/0 + 47/0@1 + + + #00cc66 + #00cc66 + 0 + 0 + I1 + + true + true + false + 2 + false + true + 0 + ContactActive.drawing - 48/0 + 48/0@1 + + + #0000ff + #0000ff + 0 + 0 + C39 + + true + true + false + 1 + false + false + 0 + Metal1.drawing - 49/0 + 49/0@1 + + + #0000ff + #0000ff + 0 + 0 + I1 + + true + true + false + 1 + false + false + 0 + Metal1.text - 49/1 + 49/1@1 + + + #ffff00 + #ffff00 + 0 + 0 + I1 + + true + true + false + 2 + false + true + 0 + Via.drawing - 50/0 + 50/0@1 + + + #00ffff + #00ffff + 0 + 0 + C40 + + true + true + false + 1 + false + false + 0 + Metal2.drawing - 51/0 + 51/0@1 + + + #00ffff + #00ffff + 0 + 0 + I1 + + true + true + false + 1 + false + false + 0 + Metal2.text - 51/1 + 51/1@1 + + + #d9e6ff + #d9e6ff + 0 + 0 + I1 + + true + true + false + 2 + false + true + 0 + Via2.drawing - 61/0 + 61/0@1 + + + #ffff00 + #ffff00 + 0 + 0 + I8 + + true + true + false + 1 + false + false + 0 + Metal3.drawing - 62/0 + 62/0@1 + + + #ffff00 + #ffff00 + 0 + 0 + I1 + + true + true + false + 1 + false + false + 0 + Metal3.text - 62/1 + 62/1@1 + + + #91ff00 + #91ff00 + 0 + 0 + I1 + + true + true + false + 2 + false + true + 0 + Via3.drawing - 30/0 + 30/0@1 + + + #7a732d + #7a732d + 0 + 0 + C39 + + true + true + false + 1 + false + false + 0 + Metal4.drawing - 31/0 + 31/0@1 + + + #7a732d + #7a732d + 0 + 0 + I1 + + true + true + false + 1 + false + false + 0 + Metal4.text - 31/1 + 31/1@1 + + + #8000ff + #8000ff + 0 + 0 + I6 + + true + true + false + 1 + false + false + 0 + CapTopMetal.drawing - 35/0 + 35/0@1 + + + #008000 + #008000 + 0 + 0 + I1 + + true + true + false + 2 + false + true + 0 + Via4.drawing - 32/0 + 32/0@1 + + + #7777ff + #7777ff + 0 + 0 + I11 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a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/MOSIS_SCMOS.lyt b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/MOSIS_SCMOS.lyt new file mode 100644 index 000000000..714dcc92d --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/MOSIS_SCMOS.lyt @@ -0,0 +1,205 @@ + + + MOSIS_SCMOS + MOSIS SCMOS lambda based process + + 0.001 + $(appdata_path)/tech/MOSIS_SCMOS + MOSIS_SCMOS.lyp + true + + + 1 + true + true + + + true + layer_map() + true + true + + + true + layer_map() + 0.001 + true + #1 + true + #1 + false + #1 + true + OUTLINE + true + PLACEMENT_BLK + true + REGIONS + true + + 0 + true + .PIN + 2 + true + .PIN + 2 + true + .FILL + 5 + true + .OBS + 3 + true + .BLK + 4 + true + .LABEL + 1 + true + + 0 + true + + 0 + VIA_ + true + default + false + + + + false + true + true + 64 + 0 + 1 + 0 + DATA + 0 + 0 + BORDER + layer_map() + true + + + 0.001 + 1 + 100 + 100 + 0 + 0 + 0 + false + false + false + true + layer_map() + + + 0 + 0.001 + layer_map() + true + false + + + 1 + 0.001 + layer_map() + true + false + true + + + + + + + true + false + false + false + false + false + 8000 + 32000 + LIB + + + 2 + false + false + 1 + * + false + + + 0 + + + false + false + + + 0 + + true + + + + # Provide z stack information here +# Each line is one layer. The specification consists of a layer specification, a colon and arguments. +# The arguments are named (like "x=...") or in serial. Parameters are separated by comma or blanks. +# Named arguments are: +# +# zstart The lower z position of the extruded layer in µm +# zstop The upper z position of the extruded layer in µm +# height The height of the extruded layer in µm +# +# 'height', 'zstart' and 'zstop' can be used in any combination. If no value is given for 'zstart', # the upper level of the previous layer will be used. +# +# If a single unnamed parameter is given, it corresponds to 'height'. Two parameters correspond to +# 'zstart' and 'zstop'. +# +# Examples: +# 1: 0.5 1.5 # extrude layer 1/0 from 0.5 to 1.5 vertically +# 1/0: 0.5 1.5 # same with explicit datatype +# 1: zstop=1.5, zstart=0.5 # same with named parameters +# 1: height=1.0, zstop=1.5 # same with z stop minus height +# 1: 1.0 zstop=1.5 # same with height as unnamed parameter +42: zstart=-0.1 , height=0.1 +41: zstart=-0.1 , height=0.1 +13: zstart=0.001 , height=0.25 +46: zstart=0.1 , height=0.15 +49: zstart=0.2 , height=0.05 +50: zstart=0.2 , height=0.15 +51: zstart=0.3 , height=0.05 +61: zstart=0.3 , height=0.15 +62: zstart=0.4 , height=0.05 +30: zstart=0.4 , height=0.15 +31: zstart=0.5 , height=0.05 +32: zstart=0.5 , height=0.15 +33: zstart=0.6 , height=0.05 +36: zstart=0.6 , height=0.15 +37: zstart=0.7 , height=0.05 +127: zstart=0.7 , height=0.15 +126: zstart=0.8 , height=0.05 +129: zstart=0.9 , height=0.15 +53: zstart=0.8 , height=0.05 +26: zstart=0.9 , height=0.15 +54: zstart=0.9 , height=0.2 + + + + poly,25,49 + 56,55,49 + 49,50,51 + 51,61,62 + 62,30,31 + 31,32,33 + 33,36,37 + poly='46-34' + + diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/README.md b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/README.md new file mode 100644 index 000000000..3a11d5a0f --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/README.md @@ -0,0 +1,20 @@ +# MOSIS_SCMOS_for_KLayout + +## KLayout (version 0.27 or higher) technology files for MOSIS SCMOS generic process + + * MOSIS_SCMOS.lyt : technology and connections description + * MOSIS_SCMOS.lyp : layers color and shape description + * drc/drc_MOSIS_SCMOS.lydrc : DRC script + +Within KLayout, create the technolgy MOSIS_SCMOS by the menu : **[Tools]-[Manage Technologies]** +Then press + at the bottom left, you will add a new technology that you can call : _MOSIS_SCMOS_ + +Then, you can copy the file **MOSIS_SCMOS.lyp**, **MOSIS_SCMOS.lyt** and the 2 directories **drc** and **lvs** of that repository in your directory : +`$HOME/.klayout/tech/MOSIS_SCMOS (under Linux)` +`#HOMEDATA#/klayout/tech/MOSIS_SCMOS (under Windows)` + +In the the drc/drc_MOSIS_SCMOS.lydrc , set the 4 parameters, by default I set them to : + * LAMBDA = 0.2 + * SUBM = true + * DEEP = false + * NBR_OF_METALS = 6 diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/drc/drc_SCMOS.lydrc b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/drc/drc_SCMOS.lydrc new file mode 100644 index 000000000..bc2498375 --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/libs.tech/klayout/drc/drc_SCMOS.lydrc @@ -0,0 +1,806 @@ + + + + + drc + + + + false + false + + true + drc_scripts + tools_menu.drc.end + dsl + drc-dsl-xml + # +# MOSIS SCMOS DRC +# +######################## +tstart = Time.now + +# optionnal for a batch launch : klayout -b r drc_SCMOS.lydrc -rd input=my_layout.gds -rd topcell=your_topcell -rd output=SCMOS_DRC.lyrdb +if $input + if $topcell + source($input,$topcell) + else + source($input) + end +end + +if $report + report("SCMOS DRC runset", $report) +else + report("SCMOS DRC runset", "SCMOS_DRC.lyrdb") +end + + +# PROCESS OPTIONS +######################## +LAMBDA = 0.5 +SUBM = false +DEEP = false +NBR_OF_METALS = 2 + +DFM = false + +# design rules limits definitions +######################## +R1_3 = ( 6 *LAMBDA ).round(3) +R2_1 = ( 3 *LAMBDA ).round(3) +R2_2 = ( 3 *LAMBDA ).round(3) +R2_4 = ( 3 *LAMBDA ).round(3) +R2_5 = ( 4 *LAMBDA ).round(3) +R3_1 = ( 2 *LAMBDA ).round(3) +R3_5 = ( 1 *LAMBDA ).round(3) +R4_1 = ( 3 *LAMBDA ).round(3) +R4_2 = ( 2 *LAMBDA ).round(3) +R5_1 = ( 2 *LAMBDA ).round(3) +R5_2 = ( 1.5 *LAMBDA ).round(3) +R5_4 = ( 2 *LAMBDA ).round(3) +R5_2_b = ( 1 *LAMBDA ).round(3) +R5_6_b = ( 2 *LAMBDA ).round(3) +R5_7_b = ( 3 *LAMBDA ).round(3) +R6_1 = ( 2 *LAMBDA ).round(3) +R6_2 = ( 1.5 *LAMBDA ).round(3) +R6_4 = ( 2 *LAMBDA ).round(3) +R6_2_b = ( 1 *LAMBDA ).round(3) +R6_5_b = ( 5 *LAMBDA ).round(3) +R6_6_b = ( 2 *LAMBDA ).round(3) +R6_7_b = ( 3 *LAMBDA ).round(3) +R6_8_b = ( 4 *LAMBDA ).round(3) +R7_1 = ( 3 *LAMBDA ).round(3) +R7_3 = ( 1 *LAMBDA ).round(3) +R8_2 = ( 3 *LAMBDA ).round(3) +R8_3 = ( 1 *LAMBDA ).round(3) +R8_4 = ( 2 *LAMBDA ).round(3) +R9_1 = ( 3 *LAMBDA ).round(3) +R9_3 = ( 1 *LAMBDA ).round(3) +R10_1 = ( 60 *LAMBDA ).round(3) +R10_2 = ( 20 *LAMBDA ).round(3) +R10_3 = ( 6 *LAMBDA ).round(3) +R10_4 = ( 30 *LAMBDA ).round(3) +R10_5 = ( 15 *LAMBDA ).round(3) +R11_2 = ( 3 *LAMBDA ).round(3) +R11_4 = ( 2 *LAMBDA ).round(3) +R11_6 = ( 2 *LAMBDA ).round(3) +R12_1 = ( 2 *LAMBDA ).round(3) +R12_2 = ( 3 *LAMBDA ).round(3) +R12_3 = ( 2 *LAMBDA ).round(3) +R12_4 = ( 1 *LAMBDA ).round(3) +R12_5 = ( 2 *LAMBDA ).round(3) +R12_6 = ( 3 *LAMBDA ).round(3) +R13_1 = ( 2 *LAMBDA ).round(3) +R13_3 = ( 3 *LAMBDA ).round(3) +R13_4 = ( 2 *LAMBDA ).round(3) +R13_5 = ( 3 *LAMBDA ).round(3) +R14_2 = ( 3 *LAMBDA ).round(3) +R14_3 = ( 1 *LAMBDA ).round(3) +R14_4 = ( 2 *LAMBDA ).round(3) +if NBR_OF_METALS > 3 + R15_3 = ( 1 *LAMBDA ).round(3) +else + R15_3 = ( 2 *LAMBDA ).round(3) +end +R16_1 = ( 2 *LAMBDA ).round(3) +R16_2 = ( 3 *LAMBDA ).round(3) +R16_3 = ( 2 *LAMBDA ).round(3) +R16_4 = ( 4 *LAMBDA ).round(3) +R16_5 = ( 2 *LAMBDA ).round(3) +R16_6 = ( 2 *LAMBDA ).round(3) +R16_7 = ( 6 *LAMBDA ).round(3) +R16_8 = ( 4 *LAMBDA ).round(3) +R16_9 = ( 2 *LAMBDA ).round(3) +R16_10 = ( 3 *LAMBDA ).round(3) +R16_11 = ( 2 *LAMBDA ).round(3) +R18_1 = ( 3 *LAMBDA ).round(3) +R18_2 = ( 2 *LAMBDA ).round(3) +R18_3 = ( 3 *LAMBDA ).round(3) +R18_4 = ( 2 *LAMBDA ).round(3) +R18_5 = ( 6 *LAMBDA ).round(3) +R20_1 = ( 4 *LAMBDA ).round(3) +R20_2 = ( 4 *LAMBDA ).round(3) +R20_3 = ( 2 *LAMBDA ).round(3) +R20_4 = ( 2 *LAMBDA ).round(3) +R20_5 = ( 2 *LAMBDA ).round(3) +R20_7 = ( 5 *LAMBDA ).round(3) +R20_8 = ( 7 *LAMBDA ).round(3) +R20_9 = ( 2 *LAMBDA ).round(3) +R20_10 = ( 3 *LAMBDA ).round(3) +R21_2 = ( 3 *LAMBDA ).round(3) +R21_3 = ( 1 *LAMBDA ).round(3) +if NBR_OF_METALS > 4 + R22_3 = ( 1 *LAMBDA ).round(3) +else + R22_3 = ( 2 *LAMBDA ).round(3) +end +R23_1 = ( 8 *LAMBDA ).round(3) +R23_2 = ( 4 *LAMBDA ).round(3) +R23_3 = ( 8 *LAMBDA ).round(3) +R23_4 = ( 3 *LAMBDA ).round(3) +R23_5 = ( 2 *LAMBDA ).round(3) +R23_6 = ( 2 *LAMBDA ).round(3) +R23_7 = ( 2 *LAMBDA ).round(3) +R23_8 = ( 4 *LAMBDA ).round(3) +R23_9 = ( 2 *LAMBDA ).round(3) +R24_1 = ( 4 *LAMBDA ).round(3) +R24_2 = ( 4 *LAMBDA ).round(3) +R24_3 = ( 4 *LAMBDA ).round(3) +R24_4 = ( 4 *LAMBDA ).round(3) +R24_5 = ( 3 *LAMBDA ).round(3) +R27_1 = ( 4 *LAMBDA ).round(3) +R27_2 = ( 4 *LAMBDA ).round(3) +R27_3 = ( 2 *LAMBDA ).round(3) +R27_4 = ( 2 *LAMBDA ).round(3) +R27_5 = ( 2 *LAMBDA ).round(3) +R27_7 = ( 5 *LAMBDA ).round(3) +R27_8 = ( 7 *LAMBDA ).round(3) +R27_9 = ( 2 *LAMBDA ).round(3) + + +if !SUBM && !DEEP + R1_1 = ( 10 *LAMBDA ).round(3) + R1_2 = ( 9 *LAMBDA ).round(3) + R2_3 = ( 5 *LAMBDA ).round(3) + R3_2 = ( 2 *LAMBDA ).round(3) + R3_2_a = ( 2 *LAMBDA ).round(3) + R3_3 = ( 2 *LAMBDA ).round(3) + R3_4 = ( 3 *LAMBDA ).round(3) + R4_3 = ( 1 *LAMBDA ).round(3) + R4_4 = ( 2 *LAMBDA ).round(3) + R5_3 = ( 2 *LAMBDA ).round(3) + R5_5_b = ( 4 *LAMBDA ).round(3) + R6_3 = ( 2 *LAMBDA ).round(3) + R7_2 = ( 2 *LAMBDA ).round(3) + R7_4 = ( 4 *LAMBDA ).round(3) + R8_1 = ( 2 *LAMBDA ).round(3) + R8_5 = ( 2 *LAMBDA ).round(3) + R9_2 = ( 3 *LAMBDA ).round(3) + R9_4 = ( 6 *LAMBDA ).round(3) + R11_1 = ( 3 *LAMBDA ).round(3) + R11_3 = ( 2 *LAMBDA ).round(3) + R11_5 = ( 3 *LAMBDA ).round(3) + R13_2 = ( 2 *LAMBDA ).round(3) + R14_1 = ( 2 *LAMBDA ).round(3) + if NBR_OF_METALS > 3 + R15_1 = ( 3 *LAMBDA ).round(3) + R15_2 = ( 3 *LAMBDA ).round(3) + R15_4 = ( 6 *LAMBDA ).round(3) + else + R15_1 = ( 6 *LAMBDA ).round(3) + R15_2 = ( 4 *LAMBDA ).round(3) + R15_4 = ( 8 *LAMBDA ).round(3) + end + R17_1 = ( 10 *LAMBDA ).round(3) + R17_2 = ( 9 *LAMBDA ).round(3) + R17_3 = ( 5 *LAMBDA ).round(3) + R17_4 = ( 5 *LAMBDA ).round(3) + R20_11 = ( 3 *LAMBDA ).round(3) + R21_1 = ( 2 *LAMBDA ).round(3) + if NBR_OF_METALS > 4 + R22_1 = ( 3 *LAMBDA ).round(3) + R22_2 = ( 3 *LAMBDA ).round(3) + R22_4 = ( 6 *LAMBDA ).round(3) + else + R22_1 = ( 6 *LAMBDA ).round(3) + R22_2 = ( 6 *LAMBDA ).round(3) + R22_4 = ( 12 *LAMBDA ).round(3) + end +end + +if SUBM + R1_1 = ( 12 *LAMBDA ).round(3) + R1_2 = ( 18 *LAMBDA ).round(3) + R2_3 = ( 6 *LAMBDA ).round(3) + R3_2 = ( 3 *LAMBDA ).round(3) + R3_2_a = ( 3 *LAMBDA ).round(3) + R3_3 = ( 2 *LAMBDA ).round(3) + R3_4 = ( 3 *LAMBDA ).round(3) + R4_3 = ( 1 *LAMBDA ).round(3) + R4_4 = ( 2 *LAMBDA ).round(3) + R5_3 = ( 3 *LAMBDA ).round(3) + R5_5_b = ( 5 *LAMBDA ).round(3) + R6_3 = ( 3 *LAMBDA ).round(3) + R7_2 = ( 3 *LAMBDA ).round(3) + R7_4 = ( 6 *LAMBDA ).round(3) + R8_1 = ( 2 *LAMBDA ).round(3) + R8_5 = ( 2 *LAMBDA ).round(3) + R9_2 = ( 3 *LAMBDA ).round(3) + R9_4 = ( 6 *LAMBDA ).round(3) + R11_1 = ( 7 *LAMBDA ).round(3) + R11_3 = ( 5 *LAMBDA ).round(3) + R11_5 = ( 6 *LAMBDA ).round(3) + R13_2 = ( 3 *LAMBDA ).round(3) + R14_1 = ( 2 *LAMBDA ).round(3) + if NBR_OF_METALS > 3 + R15_1 = ( 3 *LAMBDA ).round(3) + R15_2 = ( 3 *LAMBDA ).round(3) + R15_4 = ( 6 *LAMBDA ).round(3) + else + R15_1 = ( 5 *LAMBDA ).round(3) + R15_2 = ( 3 *LAMBDA ).round(3) + R15_4 = ( 6 *LAMBDA ).round(3) + end + R17_1 = ( 12 *LAMBDA ).round(3) + R17_2 = ( 18 *LAMBDA ).round(3) + R17_3 = ( 6 *LAMBDA ).round(3) + R17_4 = ( 6 *LAMBDA ).round(3) + R20_11 = ( 5 *LAMBDA ).round(3) + R21_1 = ( 2 *LAMBDA ).round(3) + if NBR_OF_METALS > 4 + R22_1 = ( 3 *LAMBDA ).round(3) + R22_2 = ( 3 *LAMBDA ).round(3) + R22_4 = ( 6 *LAMBDA ).round(3) + else + R22_1 = ( 6 *LAMBDA ).round(3) + R22_2 = ( 6 *LAMBDA ).round(3) + R22_4 = ( 12 *LAMBDA ).round(3) + end + R25_1 = ( 2 *LAMBDA ).round(3) + R25_2 = ( 3 *LAMBDA ).round(3) + R25_3 = ( 1 *LAMBDA ).round(3) + if NBR_OF_METALS > 5 + R26_1 = ( 3 *LAMBDA ).round(3) + R26_2 = ( 3 *LAMBDA ).round(3) + R26_3 = ( 1 *LAMBDA ).round(3) + R26_4 = ( 6 *LAMBDA ).round(3) + else + R26_1 = ( 4 *LAMBDA ).round(3) + R26_2 = ( 4 *LAMBDA ).round(3) + R26_3 = ( 2 *LAMBDA ).round(3) + R26_4 = ( 8 *LAMBDA ).round(3) + end + R28_1 = ( 40 *LAMBDA ).round(3) + R28_2 = ( 12 *LAMBDA ).round(3) + R28_3 = ( 4 *LAMBDA ).round(3) + R28_4 = ( 3 *LAMBDA ).round(3) + R28_5 = ( 4 *LAMBDA ).round(3) + R28_6 = ( 2 *LAMBDA ).round(3) + R28_7 = ( 25 *LAMBDA ).round(3) + R28_8 = ( 4 *LAMBDA ).round(3) + R28_9 = ( 8 *LAMBDA ).round(3) + R28_10 = ( 20 *LAMBDA ).round(3) + R28_11 = ( 40 *LAMBDA ).round(3) + R29_1 = ( 3 *LAMBDA ).round(3) + R29_2 = ( 4 *LAMBDA ).round(3) + R29_3 = ( 1 *LAMBDA ).round(3) + R30_1 = ( 5 *LAMBDA ).round(3) + R30_2 = ( 5 *LAMBDA ).round(3) + R30_3 = ( 1 *LAMBDA ).round(3) + R30_4 = ( 10 *LAMBDA ).round(3) + R31_1 = ( 30 *LAMBDA ).round(3) + R31_2 = ( 50 *LAMBDA ).round(3) + R31_3 = ( 15 *LAMBDA ).round(3) + R31_4 = ( 20 *LAMBDA ).round(3) + R31_5 = ( 35 *LAMBDA ).round(3) + R31_6 = ( 5 *LAMBDA ).round(3) + R31_7 = ( 30 *LAMBDA ).round(3) + R31_8 = ( 10 *LAMBDA ).round(3) +end + +if DEEP + R1_1 = ( 12 *LAMBDA ).round(3) + R1_2 = ( 18 *LAMBDA ).round(3) + R2_3 = ( 6 *LAMBDA ).round(3) + R3_2 = ( 3 *LAMBDA ).round(3) + R3_2_a = ( 4 *LAMBDA ).round(3) + R3_3 = ( 2.5 *LAMBDA ).round(3) + R3_4 = ( 4 *LAMBDA ).round(3) + R4_3 = ( 1.5 *LAMBDA ).round(3) + R4_4 = ( 4 *LAMBDA ).round(3) + R5_3 = ( 4 *LAMBDA ).round(3) + R5_5_b = ( 5 *LAMBDA ).round(3) + R6_3 = ( 4 *LAMBDA ).round(3) + R7_2 = ( 3 *LAMBDA ).round(3) + R7_4 = ( 6 *LAMBDA ).round(3) + R8_1 = ( 3 *LAMBDA ).round(3) + R9_2 = ( 4 *LAMBDA ).round(3) + R9_4 = ( 8 *LAMBDA ).round(3) + R11_1 = ( 7 *LAMBDA ).round(3) + R11_3 = ( 5 *LAMBDA ).round(3) + R11_5 = ( 6 *LAMBDA ).round(3) + R13_2 = ( 3 *LAMBDA ).round(3) + R14_1 = ( 3 *LAMBDA ).round(3) + if NBR_OF_METALS > 3 + R15_1 = ( 3 *LAMBDA ).round(3) + R15_2 = ( 4 *LAMBDA ).round(3) + R15_4 = ( 8 *LAMBDA ).round(3) + else + R15_1 = ( 5 *LAMBDA ).round(3) + R15_2 = ( 3 *LAMBDA ).round(3) + R15_4 = ( 6 *LAMBDA ).round(3) + end + R17_1 = ( 12 *LAMBDA ).round(3) + R17_2 = ( 18 *LAMBDA ).round(3) + R17_3 = ( 6 *LAMBDA ).round(3) + R17_4 = ( 6 *LAMBDA ).round(3) + R20_11 = ( 5 *LAMBDA ).round(3) + R21_1 = ( 3 *LAMBDA ).round(3) + if NBR_OF_METALS > 4 + R22_1 = ( 3 *LAMBDA ).round(3) + R22_2 = ( 4 *LAMBDA ).round(3) + R22_4 = ( 8 *LAMBDA ).round(3) + else + R22_1 = ( 6 *LAMBDA ).round(3) + R22_2 = ( 6 *LAMBDA ).round(3) + R22_4 = ( 12 *LAMBDA ).round(3) + end + R25_1 = ( 3 *LAMBDA ).round(3) + R25_2 = ( 3 *LAMBDA ).round(3) + R25_3 = ( 1 *LAMBDA ).round(3) + if NBR_OF_METALS > 5 + R26_1 = ( 3 *LAMBDA ).round(3) + R26_2 = ( 4 *LAMBDA ).round(3) + R26_3 = ( 1 *LAMBDA ).round(3) + R26_4 = ( 8 *LAMBDA ).round(3) + else + R26_1 = ( 4 *LAMBDA ).round(3) + R26_2 = ( 4 *LAMBDA ).round(3) + R26_3 = ( 2 *LAMBDA ).round(3) + R26_4 = ( 8 *LAMBDA ).round(3) + end + R28_1 = ( 45 *LAMBDA ).round(3) + R28_2 = ( 14 *LAMBDA ).round(3) + R28_3 = ( 5 *LAMBDA ).round(3) + R28_4 = ( 3 *LAMBDA ).round(3) + R28_5 = ( 5 *LAMBDA ).round(3) + R28_6 = ( 2 *LAMBDA ).round(3) + R28_7 = ( 25 *LAMBDA ).round(3) + R28_8 = ( 5 *LAMBDA ).round(3) + R28_9 = ( 9 *LAMBDA ).round(3) + R28_10 = ( 23 *LAMBDA ).round(3) + R28_11 = ( 45 *LAMBDA ).round(3) + R29_1 = ( 4 *LAMBDA ).round(3) + R29_2 = ( 4 *LAMBDA ).round(3) + R29_3 = ( 1 *LAMBDA ).round(3) + R30_1 = ( 5 *LAMBDA ).round(3) + R30_2 = ( 5 *LAMBDA ).round(3) + R30_3 = ( 2 *LAMBDA ).round(3) + R30_4 = ( 10 *LAMBDA ).round(3) + R31_1 = ( 34 *LAMBDA ).round(3) + R31_2 = ( 56 *LAMBDA ).round(3) + R31_3 = ( 17 *LAMBDA ).round(3) + R31_4 = ( 23 *LAMBDA ).round(3) + R31_5 = ( 39 *LAMBDA ).round(3) + R31_6 = ( 6 *LAMBDA ).round(3) + R31_7 = ( 34 *LAMBDA ).round(3) + R31_8 = ( 13 *LAMBDA ).round(3) +end + + +# KLAYOUT setttings +######################## +# Use a tile size of 1mm +tiles(1000.um) +# Use a tile border of 10 micron: +tile_borders(1.um) +#no_borders + +# Use 4 CPU cores +threads(4) +verbose(true) + +# Define a new custom function that selects polygons by their number of holes: +# It will return a new layer containing those polygons with min to max holes. +# max can be nil to omit the upper limit. +class DRC::DRCLayer + def with_holes(min, max) + new_data = RBA::Region::new + self.data.each do |p| + if p.holes >= (min || 0) && (!max || p.holes <= max) + new_data.insert(p) + end + end + DRC::DRCLayer::new(@engine, new_data) + end +end + +# layers definitions +######################## +info("Layers definitions") + + DNW = input(38,0) + NW = input(42,0) + PW = input(41,0) + CW = input(59,0) + AA = input(43,0) + TA = input(60,0) + PBase = input(58,0) + PL = input(46,0) + SB = input(29,0) + Nselect = input(45,0) + Pselect = input(44,0) + PO2 = input(56,0) + HR = input(34,0) + Contact = input(25,0) + ContactPoly = input(47,0) + ContactActive = input(48,0) + ContactPoly2 = input(55, 0) + CT = Contact + ContactPoly + ContactActive + ContactPoly2 + M1 = input(49,0) + V1 = input(50,0) + M2 = input(51,0) + V2 = input(61,0) + M3 = input(62,0) + V3 = input(30,0) + M4 = input(31,0) + CTM = input(35,0) + V4 = input(32,0) + M5 = input(33,0) + V5 = input(36,0) + M6 = input(37,0) + Glass = input(52,0) + Pads = input(26,0) + +# layers processing +######################## +info("Layers processing") +#CHIP = extent.sized(1.0) +NP = AA & Nselect +PP = AA & Pselect +NSTP = NP.and(NW) +PSTP = PP.not(NW) +GATE = PL & AA + +# DRC section +######################## +info("DRC section") + +### Deep NWell +if SUBM || DEEP +DNW.ongrid(0.5*LAMBDA).output("DNW_offgrid", "Offgrid vertex on DNW") +DNW.with_angle(0 .. 45).output("DNW_angle", "Non 45 degree angle DNW") +DNW.edges.and(PW).output("DNW_PW","DNW cannot cross PWell") +DNW.width(R31_1, euclidian).output("31.1 DNW_width", "31.1 : Min. DNW width : #{R31_1}um") +DNW.isolated(R31_2, euclidian).output("31.2 DNW_space", "31.2 : Min. DNW spacing : #{R31_2}um") +NW.enclosing(DNW, R31_3, euclidian).output("31.3 NW_enc_DNW", "31.3 : Min. NWell enclosing DNW : #{R31_3}um") +DNW.enclosing(NW, R31_4, euclidian).output("31.4 DNW_enc_NW", "31.4 : Min. DNW enclosing NWell : #{R31_4}um") +DNW.separation(NW, R31_5, euclidian).output("31.5 DNW_sep_NW", "31.5 : Min. DNW separation NWell : #{R31_5}um") +DNW.not(NW).enclosing(NP, R31_6, euclidian).output("31.6 DNW_enc_NP", "31.6 : Min. PW in DNW enclosing N+ : #{R31_6}um") +DNW.separation(NP, R31_7, euclidian).output("31.7 DNW_sep_NP", "31.7 : Min. DNW separation N+ : #{R31_7}um") +end + +### Nwell / Pwell +NW.ongrid(0.5*LAMBDA).output("NW_offgrid", "Offgrid vertex on NWell") +NW.with_angle(0 .. 45).output("NW_angle", "Non 45 degree angle NWell") +NW.and(PW).output("NW_PW","NW over PW not allowed") +NW.width(R1_1, euclidian).output("1.1 NW_width", "1.1 : Min. NWell width : #{R1_1}um") +NW.isolated(R1_2, euclidian).output("1.2 NW_space", "1.2 : Min. NWell spacing : #{R1_2}um") +NW.and(TA).isolated(18, euclidian).output("1.3 NW_TA_space", "1.3 : Min. NWell-TA spacing : #{R1_3}um") +PW.width(R1_1, euclidian).output("1.1 PW_width", "1.1 : Min. PWell width : #{R1_1}um") +PW.isolated(R1_2, euclidian).output("1.2 PW_space", "1.2 : Min. PWell spacing : #{R1_2}um") +PW.and(TA).isolated(R1_3, euclidian).output("1.3 PW_TA_space", "1.3 : Min. PWell-TA spacing : #{R1_3}um") + +### Active +AA.ongrid(0.5*LAMBDA).output("AA_offgrid", "Offgrid vertex on AA") +AA.with_angle(0 .. 45).output("AA_angle", "Non 45 degree angle AA") +AA.width(R2_1, euclidian).output("2.1 AA_width", "2.1 : Min. active width : #{R2_1}um") +AA.space(R2_2, euclidian).output("2.2 AA_space", "2.2 : Min. active spacing : #{R2_2}3um") +NW.enclosing(PP.interacting(GATE), R2_3, euclidian).output("2.3 NW_enc_PP", "2.3 : Min. NWell enclosing Source/Drain : #{R2_3}um") +PW.enclosing(NP.interacting(GATE), R2_3, euclidian).output("2.3 PW_enc_NP", "2.3 : Min. PWell enclosing Source/Drain : #{R2_3}um") +NW.enclosing(NP, R2_4, euclidian).output("2.4 NW_enc_NP", "2.4 : Min. NWell enclosing Nstrap : #{R2_4}um") +PW.enclosing(PP, R2_4, euclidian).output("2.4 PW_enc_PP", "2.4 : Min. PWell enclosing Pstrap : #{R2_4}um") +NP.separation(PP, R2_5, euclidian).polygons.without_area(0).output("2.5 NP_space_PP", "2.5 : Min. N+ space P+ : #{R2_5}um (if not abutted)") + +### TA Thick Active +TA.ongrid(0.5*LAMBDA).output("TA_offgrid", "Offgrid vertex on TA") +TA.with_angle(0 .. 45).output("TA_angle", "Non 45 degree angle TA") +TA.width(R24_1, euclidian).output("24.1 TA_width", "24.1 : Min. TA width : #{R24_1}um") +TA.space(R24_2, euclidian).output("24.2 TA_space", "24.2 : Min. TA spacing : #{R24_2}um") +TA.enclosing(AA, R24_3, euclidian).output("24.3 TA_enc_AA", "24.3 : Min. TA enclosing Active : #{R24_3}um") +TA.separation(AA, R24_4, euclidian).output("24.4 TA_space_AA", "24.4 : Min. TA spacing Active : #{R24_4}um") +TA.and(GATE).width(R24_5, euclidian).output("24.5 TA_gate_width", "24.5 : Min. TA Gate width : #{R24_5}um") +AA.edges.and(TA).output("24.6 AA_in_TA","24.6 : Active edge cannot cross TA") + +### Poly +PL.ongrid(0.5*LAMBDA).output("POLY_offgrid", "Offgrid vertex on Poly") +PL.with_angle(0 .. 45).output("POLY_angle", "Non 45 degree angle Poly") +PL.width(R3_1, euclidian).output("3.1 POLY_width", "3.1 : Min. Poly width : #{R3_1}um") +PL.space(R3_2, euclidian).output("3.2 Poly_space", "3.2 : Min. Poly spacing : #{R3_2}um") +GATE.space(R3_2_a, euclidian).output("3.2a Gate_space", "3.2a : Min. Gate spacing : #{R3_2_a}um") +PL.enclosing(GATE, R3_3, projection).polygons.without_area(0).output("3.3 PL_enc_GATE", "3.3 : Min. Poly extention Gate : #{R3_3}um") +AA.enclosing(GATE, R3_4, projection).polygons.without_area(0).output("3.4 AA_enc_GATE", "3.4 : Min. Source/Drain length : #{R3_4}um") +PL.not(AA).separation(AA, 1, euclidian).polygons.without_area(0).output("3.5 PL_space_AA", "3.5 : Min. Poly on Field spacing Active : #{R3_5}um") + +### Poly2 +if !DEEP +PO2.ongrid(0.5*LAMBDA).output("POLY2_offgrid", "Offgrid vertex on Poly2") +PO2.with_angle(0 .. 45).output("POLY2_angle", "Non 45 degree angle Poly2") +PO2.width(R12_1, euclidian).output("12.1 POLY2_width", "12.1 : Min. Poly2 width : #{R12_1}um") +PO2.space(R12_2, euclidian).output("12.2 POLY2_space", "12.2 : Min. Poly2 space : #{R12_2}um") +# rule R12.3 not coded +PO2.not(AA).separation(AA, R12_4, euclidian).output("12.4 POLY2_space_AA"," 12.4 : Min. Poly2 on Field spacing Active : #{R12_4}um") +PO2.not(PL).separation(PL, R12_5, euclidian).output("12.5 POLY2_space_PL"," 12.5 : Min. Poly2 spacing Poly : #{R12_5}um") +PO2.enclosing(PL, R12_5, euclidian).output("12.5 POLY2_overlap_PL"," 12.5 : Min. Poly2 overlap of Poly : #{R12_5}um") +PO2.separation(AA.or(PL).and(CT), R12_6, euclidian).output("12.6 POLY2_space_CT"," 12.5 : Min. Poly2 spacing Poly or Active contact: #{R12_6}um") +PO2cap = PL & PO2 +PO2cap.width(R11_1, euclidian).output("11.1 POLY2CAP_width", "11.1 : Min. Poly2 Capacitor width : #{R11_1}um") +PO2cap.space(R11_2, euclidian).output("11.2 POLY2CAP_space", "11.2 : Min. Poly2 Capacitor space : #{R11_2}um") +PL.enclosing(PO2cap, R11_3, euclidian).output("12.3 PL_overlap_POLY2CAP"," 11.3 : Min. Poly overlap of Poly2 Capacitor : #{R11_3}um") +PO2cap.edges.separation(AA.or(NW).edges, R11_4, euclidian).output("11.4 POLY2CAP_space_AA/NW"," 11.4 : Min. Poly2 Capacitor spacing Active or Well: #{R11_4}um") +PO2cap.separation(PL.and(CT), R11_5, euclidian).output("11.5 POLY2CAP_space_PLCT"," 11.5 : Min. Poly2 Capacitor spacing Poly contact: #{R11_5}um") +PO2cap.separation(M1.or(M2).or(M3), R11_6, euclidian).output("11.6 POLY2CAP_space_METAL"," 11.6 : Min. Poly2 Capacitor spacing any Metal: #{R11_6}um") +PO2cap.forget + +### Capacitor Well +CW.ongrid(0.5*LAMBDA).output("CW_offgrid", "Offgrid vertex on CapacitorWell") +CW.with_angle(0 .. 45).output("CW_angle", "Non 45 degree angle CapacitorWell") +CW.width(R17_1, euclidian).output("17.1 CW_width", "17.1 : Min. CapacitorWell width : #{R17_1}um") +CW.space(R17_2, euclidian).output("17.2 CW_space", "17.2 : Min. CapacitorWell space : #{R17_2}um") +AA.not(CW).separation(CW, R17_3, euclidian).output("17.3 CW_space_AA"," 17.3 : Min. CapacitorWell spacing Active : #{R17_3}um") +CW.enclosing(AA, R17_4, euclidian).output("17.4 CW_overlap_AA"," 17.4 : Min. CapacitorWell overlap of Active : #{R17_4}um") +LinCap = PL & CW +LinCap.width(R18_1, euclidian).output("18.1 LC_width", "18.1 : Min. Linear Capacitor width : #{R18_1}um") +LinCap.space(R18_2, euclidian).output("18.2 LC_space", "18.2 : Min. Linear Capacitor space : #{R18_2}um") +LinCap.separation(AA.and(CT), R18_3, euclidian).output("18.3 LC_space_AACT"," 18.3 : Min. Linear Capacitor spacing Active contact : #{R18_3}um") +LinCap.separation(PL.and(CT), R18_4, euclidian).output("18.4 LC_space_PLCT"," 18.4 : Min. Linear Capacitor spacing Poly contact : #{R18_4}um") +LinCap.forget +end + +### N+/P+ Select +Nselect.ongrid(0.5*LAMBDA).output("NSel_offgrid", "Offgrid vertex on Nselect") +Pselect.ongrid(0.5*LAMBDA).output("PSel_offgrid", "Offgrid vertex on Pselect") +Nselect.with_angle(0 .. 45).output("N+_angle", "Non 45 degree angle Nselect") +Pselect.with_angle(0 .. 45).output("N+_angle", "Non 45 degree angle Pselect") +NP.enclosing(GATE, R4_1, projection).polygons.without_area(0).output("4.1 N+_enc_GATE", "4.1 : Min. N+ extention Gate on Source/Drain : #{R4_1}um") +PP.enclosing(GATE, R4_1, projection).polygons.without_area(0).output("4.1 P+_enc_GATE", "4.1 : Min. P+ extention Gate on Source/Drain : #{R4_1}um") +Nselect.enclosing(AA, R4_2, euclidian).output("4.2 N+_enc_AA", "4.2 : Min. N+ enclosing Active : #{R4_2}um") +Pselect.enclosing(AA, R4_2, euclidian).output("4.2 P+_enc_AA", "4.2 : Min. P+ enclosing Active : #{R4_2}um") +Nselect.enclosing(CT, R4_3, euclidian).output("4. N+_enc_CT", "4.3 : Min. N+ enclosing Contact : #{R4_3}um") +Pselect.enclosing(CT, R4_3, euclidian).output("4.3 P+_enc_CT", "4.3 : Min. P+ enclosing Contact : #{R4_3}um") +Nselect.width(R4_4,euclidian).output("4.4 N+_width", "4.4 : Min. N+ width : #{R4_4}um") +Pselect.width(R4_4,euclidian).output("4.4 P+_width", "4.4 : Min. N+ width : #{R4_4}um") +Nselect.space(R4_4,euclidian).output("4.4 N+_space", "4.4 : Min. N+ spacing : #{R4_4}um") +Pselect.space(R4_4,euclidian).output("4.4 P+_space", "4.4 : Min. N+ spacing : #{R4_4}um") +Nselect.and(Pselect).output("4.4 N+_and_P+", "4.4 : N+ over P+ not allowed") + +### HR - High Resistive +HR.ongrid(0.5*LAMBDA).output("HR_offgrid", "Offgrid vertex on HighRes") +HR.with_angle(0 .. 45).output("HR_angle", "Non 45 degree angle HighRes") +HR.width(R27_1, euclidian).output("27.1 HR_width", "27.1 : Min. HiRes width : #{R27_1}um") +HR.space(R27_2, euclidian).output("27.2 HR_space", "27.2 : Min. HiRes spacing : #{R27_2}um") +HR.and(CT).output("27.3 CT_and_HR", "27.3 : Contact on HiRes not allowed") +HR.separation(CT, R27_3, euclidian).output("27.3 HR_space_CT", "27.3 : Min. HiRes space to Contact : #{R27_3}um") +HR.separation(AA, R27_5, euclidian).output("27.4 HR_space_AA", "27.4 : Min. HiRes space to Active : #{R27_4}um") +HR.separation(PO2, R27_5, euclidian).output("27.5 HR_space_PO2", "27.5 : Min. HiRes space to Poly2 : #{R27_5}um") +HR.and(PO2).and(AA).output("27.6 HR_and_active", "27.6 : HiRes Po2 over Active not allowed") +HR.and(PO2).and(NW.or(PW)).output("27.6 HR_and_Well", "27.6 : HiRes Po2 over Well not allowed") +HR.and(PO2).width(R27_7,euclidian).output("27.7 HRPO2_width", "27.7 : Min. HiRes Poly2 width : #{R27_7}um") +HR.and(PO2).space(R27_8,euclidian).output("27.8 HRPO2_space", "27.8 : Min. HiRes Poly2 space : #{R27_8}um") +HR.enclosing(PO2, R27_9, projection).output("27.9 HR_enc_PO2", "27.9 : Min. HiRes enclosing Poly2 : #{R27_9}um") + +### SB - Silicide block +SB.ongrid(0.5*LAMBDA).output("SB_offgrid", "Offgrid vertex on Sil. Block") +SB.with_angle(0 .. 45).output("SB_angle", "Non 45 degree angle Sil. Block") +SB.width(R20_1, euclidian).output("20.1 SB_width", "20.1 : Min. Sil. Block width : #{R20_1}um") +SB.space(R20_2, euclidian).output("20.2 SB_space", "20.2 : Min. Sil. Block spacing : #{R20_2}um") +SB.separation(CT, R20_3, euclidian).output("20.3 SB_space_CT", "20.3 : Min. Sil. Block space to Contact : #{R20_3}um") +SB.and(CT).output("20.3 SB_and_CT", "20.3 : Sil. Block over Contact not allowed") +SB.separation(AA, R20_4, euclidian).output("20.4 SB_space_AA", "20.4 : Min. Sil. Block space to Active : #{R20_4}um") +SB.separation(PL, R20_5, euclidian).output("20.5 SB_space_PL", "20.5 : Min. Sil. Block space to Poly : #{R20_5}um") +SB.and(GATE).output("20.6 SBres_overAA","20.6 : SB resistor over Active not allowed") +SB.and(PL).and(Nselect.or(Pselect)).output("20.6 SBres_over_WELL","20.6 : SB resistor over Well not allowed") +SB.and(PL).width(R20_7,euclidian).output("20.6 SBres_width", "20.7 : Min. SB resistor width : #{R20_7}um") +SB.and(PL).space(R20_7,euclidian).output("20.7 SBres_space", "20.7 : Min. SB resistor space : #{R20_7}um") +SB.enclosing(AA, R20_8, projection).polygons.without_area(0).output("20.8 SB_enc_AA", "20.8 : Min. Sil. Block enclosing Active : #{R20_8}um") +AA.enclosing(SB, R20_9, projection).polygons.without_area(0).output("20.9 AA_enc_SB", "20.9 : Min. Active enclosing Sil. Block : #{R20_9}um") +SB.enclosing(PL, R20_9, projection).output("20.8 SB_enc_PL", "20.8 : Min. Sil. Block enclosing Poly : #{R20_8}um") +PL.enclosing(SB, R20_8, projection).polygons.without_area(0).output("20.9 PL_enc_SB", "20.9 : Min. Poly enclosing Sil. Block : #{R20_9}um") +SB.separation(GATE, R20_11, euclidian).output("20.11 SB_space_GATE", "20.11 : Min. Sil. Block space to Gate : #{R20_11}um") + +### Contact +CT.ongrid(0.5*LAMBDA).output("CT_offgrid", "Offgrid vertex on Contact") +CT.with_angle(0 .. 90).output("CT_angle", "Non 90 degree angle Contact") +CT.and(GATE).output("CT_and_GATE", "Contact on Gate not allowed") +CT.not(M1).output("CT_not_M1", "Contact without Metal1 not recommended") +# CT.drc(length != R5_1).output("5.1 CT_width", "5.1 : Exact Contact width : #{R5_1}um") +CT.width(R5_1).output("5.1 CT_width", "5.1 : Exact Contact width : #{R5_1}um") +CT.without_area(R5_1*R5_1).output("5.1 CT_area", "5.1 : Exact Contact Area : #{R5_1*R5_1}um2") +CT.space(R5_3, euclidian).output("5.3 CT_space", "5.3 : Contact spacing : #{R5_3}um") +PL.enclosing(CT, R5_2_b, euclidian).output("5.2 PL_enc_CT", "5.2 : Min. Poly enclosing Contact : #{R5_2_b}um") +AA.enclosing(CT, R6_2_b, euclidian).output("6.2 AA_enc_CT", "6.2 : Min. Active enclosing Contact : #{R6_2_b}um") +PO2.enclosing(CT, R13_3, euclidian).output("13.3 PO2_enc_CT", "13.3 : Min. Poly2 enclosing Contact : #{R13_3}um") +CT.and(AA).separation(GATE, R5_4, euclidian).output("5.4 CTAA_space_GATE", "5.4 : Min. ActiveContact space to Gate : #{R5_4}um") +CT.and(PL).separation(PL, R5_5_b, euclidian).polygons.without_area(0).output("5.5.b CTPL_space_Poly", "5.5.b : Min. PolyContact space to Poly : #{R5_5_b}um") +CT.and(PL).separation(AA, R5_6_b, euclidian).output("5.6.b CTPL_space_AA", "5.6.b : Min. PolyContact space to AA : #{R5_6_b}um") +# rule 5.7.b not coded +CT.and(AA).separation(AA, R6_5_b, euclidian).polygons.without_area(0).output("6.5.b CTAA_space_AA", "6.5.b : Min. ActiveContact space to AA : #{R6_5_b}um") +CT.and(AA).separation(PL, R6_6_b, euclidian).output("6.6.b CTAA_space_PL", "6.6.b : Min. ActiveContact space to Poly : #{R6_6_b}um") +CT.and(AA).separation(CT.and(PL), R6_7_b, euclidian).output("6.7.b CTAA_space_CTPL", "6.7.b : Min. ActiveContact space to PolyContact : #{R6_7_b}um") +# rule 6.8.b not coded +CT.and(PO2).separation(AA, R13_5, euclidian).output("13.5 CTPO2_space_AA", "13.5 : Min. Poly2Contact space to AA : #{R13_5}um") +CT.and(PO2).separation(PL, R13_5, euclidian).output("13.5 CTPO2_space_PL", "13.5 : Min. Poly2Contact space to Poly : #{R13_5}um") +M1.enclosing(CT, R7_3, euclidian).output("7.3 M1_enc_CT", "7.3 : Min. Metal1 enclosing Contact : #{R7_3}um") + +### Metal 1 +M1.ongrid(0.5*LAMBDA).output("M1_offgrid", "Offgrid vertex on ME1") +M1.with_angle(0 .. 45).output("M1_angle", "Non 45 degree angle ME1") +M1.holes.with_area(0 .. R7_1*R7_1).output("M1_holes", "Min. Metal1 holes area : #{R7_1*R7_1}um2") +M1.width(R7_1, euclidian).output("7.1 M1_width", "7.1 : Min. Metal1 width : #{R7_1}um") +M1.space(R7_2, euclidian).output("7.2 M1_space", "7.2 : Min. Metal1 spacing : #{R7_2}um") +M1.sized(-10*LAMBDA).sized(10*LAMBDA).separation(M1,R7_4,euclidian).polygons.without_area(0).output("7.4 M1_10_space", "7.4 : Space if at least one metal1 line width is > #{10*LAMBDA}um : #{R7_4}um") + +### Via 1 +V1.ongrid(0.5*LAMBDA).output("V1_offgrid", "Offgrid vertex on Via1") +V1.not(M1).output("V1_not_M1", "Via1 without Metal1 not allowed") +V1.not(M2).output("V1_not_M2", "Via1 without Metal2 not allowed") +V1.with_angle(0 .. 90).output("V1_angle", "Non 90 degree angle Via1") +V1.width(R8_1,square).output("8.1 V1_width", "8.1 : Exact Via1 width : #{R8_1}um") +V1.without_area(R8_1*R8_1).output("8.1 V1_width", "8.1 : Exact Via1 width : #{R8_1}um2") +V1.space(R8_2,euclidian).output("8.2 V1_space", "8.2 : Via1 spacing : #{R8_2}um") +M1.enclosing(V1, R8_3, euclidian).output("8.3 M1_enc_V1", "8.3 : Min. Metal1 enclosing Via1 : #{R8_3}um") +M2.enclosing(V1, R8_3, euclidian).output("9.3 M2_enc_V1", "9.3 : Min. Metal2 enclosing Via1 : #{R9_3}um") +if !DEEP && NBR_OF_METALS < 4 + V1.and(CT).or(V1.separation(CT, R8_4, euclidian).polygons).output("8.4 V1_space_CT", "8.4 : Via1 space CT : #{R8_4}um") + V1.separation(PL + AA, R8_5, euclidian).output("8.5 V1_space_PL/AAedges", "8.5 : Via1 space to Poly orActive edges : #{R8_5}um") +end +if DFM + M1.and(M2).not(V1).with_holes(1,1).output("2_V1", "Min. 2 Via1 are needed") +end + +### Metal 2 +M2.ongrid(0.5*LAMBDA).output("M2_offgrid", "Offgrid vertex on ME2") +M2.with_angle(0 .. 45).output("M2_angle", "Non 45 degree angle ME2") +M2.width(R9_1, euclidian).output("9.1 M2_width", "9.1 : Min. Metal2 width : #{R9_1}um") +M2.space(R9_2, euclidian).output("9.2 M2_space", "9.2 : Min. Metal2 spacing : #{R9_2}um") +M2.sized(-10*LAMBDA).sized(10*LAMBDA).separation(M2,R9_4,euclidian).polygons.without_area(0).output("9.4 M2_10_space", "9.4 : Space if at least one metal2 line width is > #{10*LAMBDA}um : #{R9_4}um") + +### Via 2 +V2.ongrid(0.5*LAMBDA).output("V2_offgrid", "Offgrid vertex on Via2") +V2.not(M3).output("V2_not_M3", "Via2 without Metal3 not allowed") +V2.not(M2).output("V2_not_M2", "Via2 without Metal2 not allowed") +V2.with_angle(0 .. 90).output("V2_angle", "Non 90 degree angle Via2") +V2.width(R14_1, square).output("14.1 V2_width", "14.1 : Exact Via2 width : #{R14_1}um") +V2.without_area(R14_1*R14_1).output("14.1 V2_width", "14.1 : Exact Via2 width : #{R14_1}um2") +V2.space(R14_2, euclidian).output("14.2 V2_space", "14.2 : Via2 spacing : #{R14_2}um") +M2.enclosing(V2, R14_3, euclidian).output("14.3 M2_enc_V2", "14.3 : Min. Metal2 enclosing Via2 : #{R14_3}um") +M3.enclosing(V2, R15_3, euclidian).output("15.3 M3_enc_V2", "15.3 : Min. Metal3 enclosing Via2 : #{R15_3}um") +if !DEEP && NBR_OF_METALS < 4 + V2.and(V1).or(V2.separation(V1, R14_4, euclidian).polygons).output("14.4 V2_space_V1", "14.4 : Via2 space Via1 : #{R14_4}um") +end +if DFM + M2.and(M3).not(V2).with_holes(1,1).output("2_V2", "Min. 2 Via2 are needed") +end + +### Metal 3 +M3.ongrid(0.5*LAMBDA).output("M3_offgrid", "Offgrid vertex on ME3") +M3.with_angle(0 .. 45).output("M3_angle", "Non 45 degree angle ME3") +M3.width(R15_1, euclidian).output("15.1 M3_width", "15.1 : Min. Metal3 width : #{R15_1}um") +M3.space(R15_2, euclidian).output("15.2 M3_space", "15.2 : Min. Metal3 spacing : #{R15_2}um") +M3.sized(-10*LAMBDA).sized(10*LAMBDA).separation(M3, R15_4, euclidian).polygons.without_area(0).output("15.4 M3_10_space", "15.4 : Space if at least one metal3 line width is > #{10*LAMBDA}um : #{R15_4}um") + +### Cap Top Metal +if SUBM || DEEP +CTM.ongrid(0.5*LAMBDA).output("CTM_offgrid", "Offgrid vertex on CTM") +CTM.with_angle(0 .. 45).output("CTM_angle", "Non 45 degree angle CTM") +CTM.width(R28_1, euclidian).output("28.1 CTM_width", "28.1 : Min. Cap Top Metal width : #{R28_1}um") +CTM.space(R28_2, euclidian).output("28.2 CTM_space", "28.2 : Min. Cap Top Metal spacing : #{R28_2}um") +if NBR_OF_METALS == 4 + TM = M4 + VT = V3 + TB = V2 +end +if NBR_OF_METALS == 5 + TM = M5 + VT = V4 + VB = V3 +end +if NBR_OF_METALS == 6 + TM = M6 + VT = V5 + VB = V4 +end +TM.enclosing(CTM, R28_3, euclidian).output("28.3 TM_overlap_CTM", "28.3 : Min. Top Metal overlap Cap Top Metal : #{R28_3}um") +CTM.enclosing(VT, R28_4, euclidian).output("28.4 CTM_overlap_VT", "28.4 : Min. Cap Top Metal overlap Top Via : #{R28_4}um") +CTM.separation(VB, R28_5, euclidian).output("28.5 CTM_space_VB", "28.5 : Min. Cap Top Metal space Bottom Via : #{R28_5}um") +CTM.separation(VT, R28_5, euclidian).output("28.5 CTM_space_VT", "28.5 : Min. Cap Top Metal space Top Via : #{R28_5}um") +TM.enclosing(VB, R28_6, euclidian).output("28.6 TM_overlap_VB", "28.6 : Min. Top Metal overlap Bottom Via : #{R28_6}um") +# rule 28.7 not coded +CTM.not_interacting(VT).width(R28_8, euclidian).output("28.8 CTMdummies_width", "28.8 : Min. dummies Cap Top Metal width : #{R28_8}um") +TM.interacting(CTM).space(R28_9, euclidian).output("28.9 VT_space", "28.9 : Min. Top Metal spacing : #{R28_9}um") +VT.interacting(CTM).space(R28_10, euclidian).output("28.10 VT_space", "28.10 : Min. Top Via spacing : #{R28_10}um") +VB.interacting(TM.interacting(CTM)).space(R28_11, euclidian).output("28.11 VB_space", "28.11 : Min. Bottom Via spacing : #{R28_11}um") +CTM.sized(-15.um).sized(15.um).output("28.12 CTM_width", "28.12 : Max. CTM width/length : 30um") +TM.interacting(CTM).sized(-17.5.um).sized(17.5.um).output("28.13 TM_width", "28.13 : Max. Top Metal width/length : 35um") +CTM.and(VB).output("28.14 CTM_VB", "28.14 : no VB under CTM allowed") +CTM.and(AA.or(PL)).output("28.15 CTM_AA", "28.15 : no active or passive circuitry under CTM allowed") +end + +### Via 3 +if NBR_OF_METALS > 3 +V3.ongrid(0.5*LAMBDA).output("V3_offgrid", "Offgrid vertex on Via3") +V3.not(M3).output("V3_not_M3", "Via3 without Metal3 not allowed") +V3.not(M4).output("V3_not_M4", "Via3 without Metal4 not allowed") +V3.with_angle(0 .. 90).output("V3_angle", "Non 90 degree angle Via3") +V3.width(R21_1, square).output("21.1 V3_width", "21.1 : Exact Via3 width : #{R21_1}um") +V3.without_area(R21_1*R21_1).output("21.1 V3_width", "21.1 : Exact Via3 width : #{R21_1}um2") +V3.space(R21_2, euclidian).output("21.2 V3_space", "21.2 : Via3 spacing : #{R21_2}um") +M3.enclosing(V3, R21_3, euclidian).output("21.3 M3_enc_V3", "21.3 : Min. Metal3 enclosing Via3 : #{R21_3}um") +M4.enclosing(V3, R22_3, euclidian).output("22.3 M4_enc_V3", "22.3 : Min. Metal4 enclosing Via3 : #{R22_3}um") +if DFM + M3.and(M4).not(V3).with_holes(1,1).output("2_V3", "Min. 2 Via3 are needed") +end + +### Metal 4 +M4.ongrid(0.5*LAMBDA).output("M4_offgrid", "Offgrid vertex on ME4") +M4.with_angle(0 .. 45).output("M4_angle", "Non 45 degree angle ME4") +M4.width(R22_1, euclidian).output("22.1 M4_width", "22.1 : Min. Metal4 width : #{R22_1}um") +M4.space(R22_2, euclidian).output("22.2 M4_space", "22.2 : Min. Metal4 spacing : #{R22_2}um") +M4.sized(-10*LAMBDA).sized(10*LAMBDA).separation(M4, R22_4, euclidian).polygons.without_area(0).output("22.4 M4_10_space", "22.4 : Space if at least one metal4 line width is > #{10*LAMBDA}um : #{R22_4}um") + +### Via 4 +if NBR_OF_METALS > 4 +V4.ongrid(0.5*LAMBDA).output("V4_offgrid", "Offgrid vertex on Via4") +V4.not(M5).output("V4_not_M5", "Via4 without Metal5 not allowed") +V4.not(M4).output("V4_not_M4", "Via4 without Metal4 not allowed") +V4.with_angle(0 .. 90).output("V4_angle", "Non 90 degree angle Via4") +V4.width(R25_1, square).output("25.1 V4_width", "25.1 : Exact Via4 width : #{R25_1}um") +V4.without_area(R25_1*R25_1).output("25.1 V4_width", "25.1 : Via4 width : #{R25_1}um2") +V4.space(R25_2, euclidian).output("25.2 V4_space", "25.2 : Exact Via4 spacing : #{R25_2}um") +M4.enclosing(V4, R25_3, euclidian).output("25.3 M4_enc_V4", "25.3 : Min. Metal4 enclosing Via4 : #{R25_3}um") +M5.enclosing(V4, R26_3, euclidian).output("26.3 M5_enc_V4", "26.3 : Min. Metal5 enclosing Via4 : #{R26_3}um") +if DFM + M4.and(M5).not(V4).with_holes(1,1).output("2_V4", "Min. 2 Via4 are needed") +end + +### Metal 5 +M5.ongrid(0.5*LAMBDA).output("M5_offgrid", "Offgrid vertex on ME5") +M5.with_angle(0 .. 45).output("M5_angle", "Non 45 degree angle ME5") +M5.width(R26_1, euclidian).output("26.1 M5_width", "26.1 : Min. Metal5 width : #{R26_1}um") +M5.space(R26_2, euclidian).output("26.2 M5_space", "26.2 : Min. Metal5 spacing : #{R26_2}um") +M5.sized(-10*LAMBDA).sized(10*LAMBDA).separation(M5, R26_4, euclidian).polygons.without_area(0).output("26.4 M5_10_space", "26 .4 : Space if at least one metal5 line width is > #{10*LAMBDA}um : #{R26_4}um") + +### Via 5 +if NBR_OF_METALS > 5 +V5.ongrid(0.5*LAMBDA).output("V5_offgrid", "Offgrid vertex on Via5") +V5.not(M5).output("V5_not_M5", "Via5 without Metal5 not allowed") +V5.not(M6).output("V5_not_M6", "Via5 without Metal6 not allowed") +V5.with_angle(0 .. 90).output("V4_angle", "Non 90 degree angle Via5") +V5.width(R29_1, square).output("29.1 V5_width", "29.1 : Exact Via5 width : #{R29_1}um") +V5.without_area(R29_1*R29_1).output("29.1 V5_width", "29.1 : Exact Via5 width : #{R29_1}um2") +V5.space(R29_2, euclidian).output("29.2 V5_space", "29.2 : Via5 spacing : #{R29_2}um") +M5.enclosing(V5, R29_3, euclidian).output("29.3 M5_enc_V5", "29.3 : Min. Metal5 enclosing Via5 : #{R29_3}um") +M6.enclosing(V5, R30_3, euclidian).output("30.3 M3_enc_V5", "30.3 : Min. Metal6 enclosing Via5 : #{R30_3}um") +if DFM + M5.and(M6).not(V5).with_holes(1,1).output("2_V5", "Min. 2 Via5 are needed") +end + +### Metal 6 +M6.ongrid(0.5*LAMBDA).output("M6_offgrid", "Offgrid vertex on ME6") +M6.with_angle(0 .. 45).output("M6_angle", "Non 45 degree angle ME5") +M6.width(R30_1, euclidian).output("30.1 M6_width", "30.1 : Min. Metal6 width : #{R30_1}um") +M6.space(R30_2, euclidian).output("30.2 M6_space", "30.2 : Min. Metal6 spacing : #{R30_2}um") +M6.sized(-10*LAMBDA).sized(10*LAMBDA).separation(M5, 10, euclidian).polygons.without_area(0).output("30.4 M6_10_space", "30.4 : Space if at least one metal6 line width is > #{10*LAMBDA}um : #{R30_4}um") + +end +end +end + +# time spent for the DRC +time = Time.now +hours = ((time - tstart)/3600).to_i +minutes = ((time - tstart)/60 - hours * 60).to_i +seconds = ((time - tstart) - (minutes * 60 + hours * 3600)).to_i +$stdout.write "DRC finished at : #{time.hour}:#{time.min}:#{time.sec} - DRC duration = #{hours} hrs. #{minutes} min. #{seconds} sec.\n" + diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/meson.build b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/meson.build new file mode 100644 index 000000000..791deba52 --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/meson.build @@ -0,0 +1,30 @@ + +project( + 'pdk_scmos2m1u_nsx2', + version: '0.1.0', + meson_version: '>= 1.2.0', + default_options: ['warning_level=3'] +) + +python = import('python') +py = python.find_installation('python3') +py_deps = py.dependency() + +pdks_dir = py.get_install_dir() / 'pdks' / 'scmos2m1u_nsx2' + +find_py = 'find libs.tech/coriolis -type f -name "*.py"' +res = run_command('sh', '-c', find_py, check:true) +py_files = res.stdout().strip().split('\n') + +find_data = 'find libs.tech/coriolis -type f ! -name "*.py"' +res = run_command('sh', '-c', find_data, check:true) +data_files = res.stdout().strip().split('\n') + +py.install_sources( files(py_files) , subdir: 'pdks/scmos2m1u_nsx2' ) +py.install_sources( files(data_files) , subdir: 'pdks/scmos2m1u_nsx2' ) + +install_subdir( 'libs.tech/klayout' , + exclude_files: ['libs.tech/klayout/README.md'], + install_dir: pdks_dir +) + diff --git a/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/pyproject.toml b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/pyproject.toml new file mode 100644 index 000000000..eee139f4e --- /dev/null +++ b/pdks/symbolic/nsxlib2/scmos2m1u_nsx2/pyproject.toml @@ -0,0 +1,25 @@ +[project] +name = "pdk_scmos2m1u_nsx2" +version = "0.1.0" +description = "SCMOS 2M1U nsxlib2 PDK for Coriolis EDA" +authors = [ { name = "Coriolis EDA Contributers" } ] +requires-python = ">= 3.8" + +[build-system] +requires = [ + "meson", + "meson-python", + "ninja", + "setuptools", + "cibuildwheel", + "build", + "pdm-backend" +] +build-backend = "mesonpy" + +[tool.meson] +build-dir = "build" + +[tool.cibuildwheel] +build = "cp310-*" +skip = ["cp36-*", "cp37-*", "pp*"] diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/__init__.py b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/Makefile b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/Makefile new file mode 100644 index 000000000..18245f21a --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/Makefile @@ -0,0 +1,11 @@ +# OSDI dynamic loadble module compile +# we use openvaf to compile the Verilog-A model. +# For the openvaf, see: https://openvaf.semimod.de/ +# + +SOURCE = ../../../../common/libs.tech/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/openvaf/psp103_nqs.va +OSDI = ../../../../common/libs.tech/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/openvaf/psp103_nqs.osdi +OSDIFILE=psp103_nqs.osdi + +$(OSDIFILE): $(SOURCE) + openvaf $(SOURCE) -o $(OSDIFILE) diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/Sg13g2nsx2Setup.py b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/Sg13g2nsx2Setup.py new file mode 100644 index 000000000..c45925c83 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/Sg13g2nsx2Setup.py @@ -0,0 +1,96 @@ + +import sys +import os +import socket +from pathlib import Path +from coriolis.designflow.task import ShellEnv + + +__all__ = [ 'Where', 'setupSg13g2_nsx2 ' ] + + +class Where ( object ): + + coriolisTop = None + allianceTop = None + cellsTop = None + checkToolkit = None + + def __init__ ( self, checkToolkit=None ): + if 'CORIOLIS_TOP' in os.environ: Where.coriolisTop = Path( os.environ['CORIOLIS_TOP'] ) + if 'ALLIANCE_TOP' in os.environ: Where.allianceTop = Path( os.environ['ALLIANCE_TOP'] ) + if 'CELLS_TOP' in os.environ: Where.cellsTop = Path( os.environ['CELLS_TOP'] ) + if Where.coriolisTop and not Where.allianceTop: Where.allianceTop = Where.coriolisTop + #print( Where.coriolisTop, Where.allianceTop ) + if not Where.coriolisTop: + print( 'technos.Where.__init__(): Unable to locate Coriolis top.' ) + if checkToolkit is None: + checkToolkit = Path.home() / 'coriolis-2.x' / 'src' / 'alliance-check-toolkit' + else: + if isinstance(checkToolkit,str): + checkToolkit = Path( checkToolkit ) + if not Where.cellsTop: + Where.cellsTop = checkToolkit / 'cells' + Where.checkToolkit = checkToolkit + if not Where.cellsTop and Where.allianceTop: + Where.cellsTop = Where.allianceTop / 'cells' + ShellEnv.ALLIANCE_TOP = Where.allianceTop.as_posix() + + def __repr__ ( self ): + if not Where.coriolisTop: + return '' + return ''.format( Where.coriolisTop.as_posix() ) + + +def setupSg13g2_nsx2 ( checkToolkit=None ): + Where( checkToolkit ) + ShellEnv().export() + + pdkDir = Where.checkToolkit / 'dks' / 'sg13g2_nsx2' / 'libs.tech' + coriolisTechDir = pdkDir / 'coriolis' + if not pdkDir.is_dir(): + print( '[ERROR] technos.setupSg13g2_nsx2(): PDK directory do *not* exists:' ) + print( ' "{}"'.format(techDir.as_posix()) ) + sys.path.append( coriolisTechDir.as_posix() ) + + cellsTop = Where.checkToolkit / 'cells' + liberty = coriolisTechDir / 'sg13g2_nsx2' / 'nsxlib2.lib' +# kdrcRules = pdkDir / 'klayout' / 'drc_sky130.lydrc' + + from coriolis import Cfg + from coriolis import Viewer + from coriolis import CRL + from coriolis.helpers import overlay, l, u, n + from coriolis.designflow.yosys import Yosys + from coriolis.designflow.klayout import DRC + from sg13g2_nsx2 import techno, nsxlib2 + techno.setup( coriolisTechDir ) + nsxlib2.setup( cellsTop ) + + with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.misc.minTraceLevel = 1900 + cfg.misc.maxTraceLevel = 3000 + cfg.katana.eventsLimit = 1000000 + cfg.katana.termSatReservedLocal = 6 + cfg.katana.termSatThreshold = 9 + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + Yosys.setLiberty( liberty ) +# DRC.setDrcRules( kdrcRules ) + ShellEnv.CHECK_TOOLKIT = Where.checkToolkit.as_posix() + + path = None + for pathVar in [ 'PATH', 'path' ]: + if pathVar in os.environ: + path = os.environ[ pathVar ] + os.environ[ pathVar ] = path + ':' + (Where.allianceTop / 'bin').as_posix() + break + + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/__init__.py b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/__init__.py new file mode 100644 index 000000000..b87e091fc --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/__init__.py @@ -0,0 +1,5 @@ + +import os +from pathlib import Path + +path = Path( os.path.dirname(os.path.abspath(__file__)) ) diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/mos_tt.lib b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/mos_tt.lib new file mode 100644 index 000000000..707b4ca82 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/mos_tt.lib @@ -0,0 +1,5 @@ +*Load MOS tt corner library + +.lib cornerMOSlv.lib mos_tt + +.end diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/nsxlib2.lib b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/nsxlib2.lib new file mode 100644 index 000000000..a68988785 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/nsxlib2.lib @@ -0,0 +1,19770 @@ +/************************************************************************/ +/* */ +/* Avertec Release v3.4p5 (64 bits on Linux 4.4.0-26100-Microsoft) */ +/* argv: /home/nshimizu/lip6/alliance-check-toolkit/bin/buildLib.tcl /home/nshimizu/lip6/alliance-check-toolkit/dks/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spimodel.cfg hspice nsxlib2 -SpiceModel spimodel.cfg mos_tt.lib -OsdiDll psp103_nqs.osdi */ +/* */ +/* User: nshimizu */ +/* Generation date Sat Dec 21 15:53:06 2024 */ +/* */ +/* liberty data flow `nsxlib2.lib` */ +/* */ +/************************************************************************/ + + + +library (nsxlib2.lib) { + + technology (cmos) ; + date : "Sat Dec 21 15:53:06 2024" ; + delay_model : table_lookup ; + nom_voltage : 5.00 ; + nom_temperature : 70.0 ; + nom_process : 1.0 ; + slew_derate_from_library : 1.0 ; + default_fanout_load : 1000.0 ; + default_inout_pin_cap : 1000.0 ; + default_input_pin_cap : 1000.0 ; + default_output_pin_cap : 0.0 ; + voltage_unit : "1V" ; + time_unit : "1ps" ; + capacitive_load_unit (1,ff) ; + pulling_resistance_unit : "1ohm" ; + current_unit : "1mA" ; + leakage_power_unit : "1uW" ; + default_cell_leakage_power : 0.0 ; + input_threshold_pct_rise : 50.0 ; + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_rise : 50.0 ; + output_threshold_pct_fall : 50.0 ; + slew_lower_threshold_pct_fall : 20.0 ; + slew_upper_threshold_pct_fall : 80.0 ; + slew_lower_threshold_pct_rise : 20.0 ; + slew_upper_threshold_pct_rise : 80.0 ; + + lu_table_template (inslew_load_5x5__54) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.22, 4.44, 8.88, 17.76, 35.51"); + } + lu_table_template (inslew_load_5x5__53) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("8.29, 16.58, 33.16, 66.32, 132.64"); + } + lu_table_template (inslew_load_5x5__52) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("8.84, 17.68, 35.35, 70.71, 141.41"); + } + lu_table_template (inslew_load_5x5__51) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("8.16, 16.32, 32.64, 65.27, 130.54"); + } + lu_table_template (inslew_ckslew_5x5__0) { + variable_1 : constrained_pin_transition; + variable_2 : related_pin_transition; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + lu_table_template (inslew_5__0) { + variable_1 : input_net_transition; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + lu_table_template (inslew_load_5x5__50) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.68, 3.36, 6.73, 13.46, 26.92"); + } + lu_table_template (inslew_load_5x5__49) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.27, 4.54, 9.08, 18.16, 36.32"); + } + lu_table_template (inslew_load_5x5__48) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.45, 2.90, 5.80, 11.61, 23.21"); + } + lu_table_template (inslew_load_5x5__47) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.31, 4.63, 9.25, 18.51, 37.02"); + } + lu_table_template (inslew_load_5x5__46) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.30, 2.61, 5.22, 10.44, 20.88"); + } + lu_table_template (inslew_load_5x5__45) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.25, 4.51, 9.02, 18.03, 36.07"); + } + lu_table_template (inslew_load_5x5__44) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.38, 2.75, 5.51, 11.02, 22.03"); + } + lu_table_template (inslew_load_5x5__43) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.37, 2.74, 5.48, 10.96, 21.92"); + } + lu_table_template (inslew_load_5x5__42) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.22, 4.44, 8.89, 17.78, 35.55"); + } + lu_table_template (inslew_load_5x5__41) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.26, 4.51, 9.02, 18.05, 36.10"); + } + lu_table_template (inslew_load_5x5__40) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.32, 4.63, 9.27, 18.53, 37.07"); + } + lu_table_template (inslew_load_5x5__39) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.28, 4.57, 9.14, 18.28, 36.55"); + } + lu_table_template (inslew_load_5x5__38) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.36, 4.73, 9.45, 18.91, 37.82"); + } + lu_table_template (inslew_load_5x5__37) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.37, 4.73, 9.46, 18.93, 37.85"); + } + lu_table_template (inslew_load_5x5__36) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.97, 5.93, 11.87, 23.74, 47.47"); + } + lu_table_template (inslew_load_5x5__35) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.19, 4.39, 8.77, 17.55, 35.09"); + } + lu_table_template (inslew_load_5x5__34) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.66, 5.33, 10.65, 21.30, 42.61"); + } + lu_table_template (inslew_load_5x5__33) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.22, 4.44, 8.87, 17.74, 35.48"); + } + lu_table_template (inslew_load_5x5__32) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.25, 4.50, 8.99, 17.99, 35.98"); + } + lu_table_template (inslew_load_5x5__31) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.22, 4.44, 8.89, 17.78, 35.55"); + } + lu_table_template (inslew_load_5x5__30) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.21, 4.42, 8.83, 17.67, 35.34"); + } + lu_table_template (inslew_load_5x5__29) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.99, 3.98, 7.97, 15.93, 31.87"); + } + lu_table_template (inslew_load_5x5__28) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.13, 4.26, 8.53, 17.06, 34.12"); + } + lu_table_template (inslew_load_5x5__27) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.75, 3.50, 7.01, 14.02, 28.04"); + } + lu_table_template (inslew_load_5x5__26) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.11, 4.23, 8.46, 16.91, 33.82"); + } + lu_table_template (inslew_load_5x5__25) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.58, 3.15, 6.30, 12.60, 25.21"); + } + lu_table_template (inslew_load_5x5__24) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.40, 4.79, 9.58, 19.16, 38.32"); + } + lu_table_template (inslew_load_5x5__23) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.16, 4.32, 8.64, 17.27, 34.55"); + } + lu_table_template (inslew_load_5x5__22) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.37, 4.75, 9.50, 19.00, 38.00"); + } + lu_table_template (inslew_load_5x5__21) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.24, 4.48, 8.97, 17.93, 35.87"); + } + lu_table_template (inslew_load_5x5__20) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.31, 4.62, 9.24, 18.48, 36.96"); + } + lu_table_template (inslew_load_5x5__19) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.26, 4.52, 9.03, 18.06, 36.12"); + } + lu_table_template (inslew_load_5x5__18) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.67, 5.35, 10.69, 21.38, 42.76"); + } + lu_table_template (inslew_load_5x5__17) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.44, 4.88, 9.77, 19.54, 39.07"); + } + lu_table_template (inslew_load_5x5__16) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.29, 4.58, 9.16, 18.32, 36.65"); + } + lu_table_template (inslew_load_5x5__15) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.19, 4.37, 8.75, 17.50, 35.00"); + } + lu_table_template (inslew_load_5x5__14) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.70, 3.41, 6.82, 13.63, 27.27"); + } + lu_table_template (inslew_load_5x5__13) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.33, 4.67, 9.33, 18.66, 37.33"); + } + lu_table_template (inslew_load_5x5__12) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.51, 3.01, 6.02, 12.05, 24.10"); + } + lu_table_template (inslew_load_5x5__11) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.44, 2.88, 5.75, 11.51, 23.02"); + } + lu_table_template (inslew_load_5x5__10) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("4.31, 8.62, 17.24, 34.49, 68.98"); + } + lu_table_template (inslew_load_5x5__9) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.18, 4.35, 8.71, 17.42, 34.84"); + } + lu_table_template (inslew_load_5x5__8) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.20, 4.41, 8.81, 17.62, 35.24"); + } + lu_table_template (inslew_load_5x5__7) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.26, 2.53, 5.05, 10.10, 20.21"); + } + lu_table_template (inslew_load_5x5__6) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.26, 4.51, 9.03, 18.06, 36.12"); + } + lu_table_template (inslew_load_5x5__5) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.69, 3.37, 6.75, 13.50, 27.00"); + } + lu_table_template (inslew_load_5x5__4) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.44, 2.87, 5.75, 11.50, 22.99"); + } + lu_table_template (inslew_load_5x5__3) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.23, 4.46, 8.91, 17.82, 35.65"); + } + lu_table_template (inslew_load_5x5__2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.49, 2.98, 5.96, 11.93, 23.85"); + } + lu_table_template (inslew_load_5x5__1) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.01, 4.03, 8.05, 16.11, 32.22"); + } + lu_table_template (inslew_load_5x5__0) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.36, 2.71, 5.42, 10.85, 21.70"); + } + power_lut_template (energy_inslew_load_5x5__54) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.22, 4.44, 8.88, 17.76, 35.51"); + } + power_lut_template (energy_inslew_load_5x5__53) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("8.29, 16.58, 33.16, 66.32, 132.64"); + } + power_lut_template (energy_inslew_load_5x5__52) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("8.84, 17.68, 35.35, 70.71, 141.41"); + } + power_lut_template (energy_inslew_load_5x5__51) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("8.16, 16.32, 32.64, 65.27, 130.54"); + } + power_lut_template (energy_inslew_5__0) { + variable_1 : input_transition_time; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + power_lut_template (energy_inslew_load_5x5__50) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.68, 3.36, 6.73, 13.46, 26.92"); + } + power_lut_template (energy_inslew_load_5x5__49) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.27, 4.54, 9.08, 18.16, 36.32"); + } + power_lut_template (energy_inslew_load_5x5__48) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.45, 2.90, 5.80, 11.61, 23.21"); + } + power_lut_template (energy_inslew_load_5x5__47) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.31, 4.63, 9.25, 18.51, 37.02"); + } + power_lut_template (energy_inslew_load_5x5__46) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.30, 2.61, 5.22, 10.44, 20.88"); + } + power_lut_template (energy_inslew_load_5x5__45) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.25, 4.51, 9.02, 18.03, 36.07"); + } + power_lut_template (energy_inslew_load_5x5__44) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.38, 2.75, 5.51, 11.02, 22.03"); + } + power_lut_template (energy_inslew_load_5x5__43) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.37, 2.74, 5.48, 10.96, 21.92"); + } + power_lut_template (energy_inslew_load_5x5__42) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.22, 4.44, 8.89, 17.78, 35.55"); + } + power_lut_template (energy_inslew_load_5x5__41) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.26, 4.51, 9.02, 18.05, 36.10"); + } + power_lut_template (energy_inslew_load_5x5__40) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.32, 4.63, 9.27, 18.53, 37.07"); + } + power_lut_template (energy_inslew_load_5x5__39) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.28, 4.57, 9.14, 18.28, 36.55"); + } + power_lut_template (energy_inslew_load_5x5__38) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.36, 4.73, 9.45, 18.91, 37.82"); + } + power_lut_template (energy_inslew_load_5x5__37) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.37, 4.73, 9.46, 18.93, 37.85"); + } + power_lut_template (energy_inslew_load_5x5__36) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.97, 5.93, 11.87, 23.74, 47.47"); + } + power_lut_template (energy_inslew_load_5x5__35) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.19, 4.39, 8.77, 17.55, 35.09"); + } + power_lut_template (energy_inslew_load_5x5__34) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.66, 5.33, 10.65, 21.30, 42.61"); + } + power_lut_template (energy_inslew_load_5x5__33) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.22, 4.44, 8.87, 17.74, 35.48"); + } + power_lut_template (energy_inslew_load_5x5__32) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.25, 4.50, 8.99, 17.99, 35.98"); + } + power_lut_template (energy_inslew_load_5x5__31) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.22, 4.44, 8.89, 17.78, 35.55"); + } + power_lut_template (energy_inslew_load_5x5__30) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.21, 4.42, 8.83, 17.67, 35.34"); + } + power_lut_template (energy_inslew_load_5x5__29) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.99, 3.98, 7.97, 15.93, 31.87"); + } + power_lut_template (energy_inslew_load_5x5__28) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.13, 4.26, 8.53, 17.06, 34.12"); + } + power_lut_template (energy_inslew_load_5x5__27) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.75, 3.50, 7.01, 14.02, 28.04"); + } + power_lut_template (energy_inslew_load_5x5__26) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.11, 4.23, 8.46, 16.91, 33.82"); + } + power_lut_template (energy_inslew_load_5x5__25) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.58, 3.15, 6.30, 12.60, 25.21"); + } + power_lut_template (energy_inslew_load_5x5__24) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.40, 4.79, 9.58, 19.16, 38.32"); + } + power_lut_template (energy_inslew_load_5x5__23) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.16, 4.32, 8.64, 17.27, 34.55"); + } + power_lut_template (energy_inslew_load_5x5__22) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.37, 4.75, 9.50, 19.00, 38.00"); + } + power_lut_template (energy_inslew_load_5x5__21) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.24, 4.48, 8.97, 17.93, 35.87"); + } + power_lut_template (energy_inslew_load_5x5__20) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.31, 4.62, 9.24, 18.48, 36.96"); + } + power_lut_template (energy_inslew_load_5x5__19) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.26, 4.52, 9.03, 18.06, 36.12"); + } + power_lut_template (energy_inslew_load_5x5__18) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.67, 5.35, 10.69, 21.38, 42.76"); + } + power_lut_template (energy_inslew_load_5x5__17) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.44, 4.88, 9.77, 19.54, 39.07"); + } + power_lut_template (energy_inslew_load_5x5__16) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.29, 4.58, 9.16, 18.32, 36.65"); + } + power_lut_template (energy_inslew_load_5x5__15) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.19, 4.37, 8.75, 17.50, 35.00"); + } + power_lut_template (energy_inslew_load_5x5__14) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.70, 3.41, 6.82, 13.63, 27.27"); + } + power_lut_template (energy_inslew_load_5x5__13) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.33, 4.67, 9.33, 18.66, 37.33"); + } + power_lut_template (energy_inslew_load_5x5__12) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.51, 3.01, 6.02, 12.05, 24.10"); + } + power_lut_template (energy_inslew_load_5x5__11) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.44, 2.88, 5.75, 11.51, 23.02"); + } + power_lut_template (energy_inslew_load_5x5__10) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("4.31, 8.62, 17.24, 34.49, 68.98"); + } + power_lut_template (energy_inslew_load_5x5__9) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.18, 4.35, 8.71, 17.42, 34.84"); + } + power_lut_template (energy_inslew_load_5x5__8) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.20, 4.41, 8.81, 17.62, 35.24"); + } + power_lut_template (energy_inslew_load_5x5__7) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.26, 2.53, 5.05, 10.10, 20.21"); + } + power_lut_template (energy_inslew_load_5x5__6) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.26, 4.51, 9.03, 18.06, 36.12"); + } + power_lut_template (energy_inslew_load_5x5__5) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.69, 3.37, 6.75, 13.50, 27.00"); + } + power_lut_template (energy_inslew_load_5x5__4) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.44, 2.87, 5.75, 11.50, 22.99"); + } + power_lut_template (energy_inslew_load_5x5__3) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.23, 4.46, 8.91, 17.82, 35.65"); + } + power_lut_template (energy_inslew_load_5x5__2) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.49, 2.98, 5.96, 11.93, 23.85"); + } + power_lut_template (energy_inslew_load_5x5__1) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.01, 4.03, 8.05, 16.11, 32.22"); + } + power_lut_template (energy_inslew_load_5x5__0) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.36, 2.71, 5.42, 10.85, 21.70"); + } + + + + + cell (a2_x2) { + area : 0.0 ; + cell_leakage_power : 0.0031 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.0042 ; + } + leakage_power () { + when : "i1" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.00038 ; + } + pin (i1) { + direction : input ; + capacitance : 22.05 ; + } + pin (i0) { + direction : input ; + capacitance : 26.48 ; + } + pin (q) { + function : "(i0 & i1)" ; + direction : output ; + capacitance : 5.42 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("43.6, 43.6, 43.6, 48.0, 55.2", \ + "52.1, 52.1, 52.1, 56.6, 64.5", \ + "64.5, 64.5, 64.5, 69.3, 77.8", \ + "85.5, 85.5, 85.5, 90.6, 99.9", \ + "125.0, 125.0, 125.0, 130.1, 140.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("17.0, 17.0, 17.0, 20.6, 27.4", \ + "22.8, 22.8, 22.8, 26.5, 33.5", \ + "34.0, 34.0, 34.0, 37.8, 45.0", \ + "56.2, 56.2, 56.2, 59.9, 67.3", \ + "100.1, 100.1, 100.1, 104.1, 111.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("34.4, 34.4, 34.4, 39.0, 47.1", \ + "36.0, 36.0, 36.0, 40.7, 49.2", \ + "34.1, 34.1, 34.1, 39.0, 47.9", \ + "24.9, 24.9, 24.9, 30.0, 39.4", \ + "2.4, 2.4, 2.4, 7.6, 17.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("17.3, 17.3, 17.3, 21.0, 27.9", \ + "22.9, 22.9, 22.9, 26.6, 33.6", \ + "33.1, 33.1, 33.1, 36.9, 44.0", \ + "52.7, 52.7, 52.7, 56.5, 63.8", \ + "91.1, 91.1, 91.1, 94.9, 102.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("39.3, 39.3, 39.3, 43.7, 51.0", \ + "42.9, 42.9, 42.9, 47.4, 55.2", \ + "46.9, 46.9, 46.9, 51.6, 60.2", \ + "52.0, 52.0, 52.0, 57.1, 66.3", \ + "60.3, 60.3, 60.3, 65.5, 75.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("17.5, 17.5, 17.5, 21.0, 27.9", \ + "22.6, 22.6, 22.6, 26.2, 33.2", \ + "32.7, 32.7, 32.7, 36.4, 43.6", \ + "52.8, 52.8, 52.8, 56.5, 63.9", \ + "92.8, 92.8, 92.8, 96.6, 104.0"); + } + cell_fall (inslew_load_5x5__0) { + values ("37.9, 37.9, 37.9, 42.6, 50.8", \ + "43.0, 43.0, 43.0, 47.8, 56.4", \ + "48.5, 48.5, 48.5, 53.4, 62.6", \ + "55.4, 55.4, 55.4, 60.5, 70.0", \ + "65.9, 65.9, 65.9, 71.1, 81.1"); + } + fall_transition (inslew_load_5x5__0) { + values ("18.9, 18.9, 18.9, 22.6, 29.6", \ + "25.6, 25.6, 25.6, 29.3, 36.4", \ + "38.2, 38.2, 38.2, 41.9, 49.1", \ + "62.5, 62.5, 62.5, 66.3, 73.7", \ + "110.7, 110.7, 110.7, 114.5, 122.0"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("761.8, 761.8, 761.8, 829.6, 965.3", \ + "987.0, 987.0, 987.0, 1054.8, 1190.4", \ + "1432.8, 1432.8, 1432.8, 1500.6, 1636.3", \ + "2321.3, 2321.3, 2321.3, 2389.1, 2524.7", \ + "4095.7, 4095.7, 4095.7, 4163.5, 4299.1"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("722.9, 722.9, 722.9, 790.7, 926.3", \ + "872.6, 872.6, 872.6, 940.4, 1076.0", \ + "1165.8, 1165.8, 1165.8, 1233.7, 1369.3", \ + "1745.3, 1745.3, 1745.3, 1813.1, 1948.7", \ + "2899.4, 2899.4, 2899.4, 2967.2, 3102.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("817.4, 817.4, 817.4, 885.2, 1020.9", \ + "1038.5, 1038.5, 1038.5, 1106.3, 1241.9", \ + "1479.6, 1479.6, 1479.6, 1547.4, 1683.0", \ + "2360.3, 2360.3, 2360.3, 2428.1, 2563.7", \ + "4120.0, 4120.0, 4120.0, 4187.8, 4323.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("805.0, 805.0, 805.0, 872.8, 1008.5", \ + "1006.7, 1006.7, 1006.7, 1074.6, 1210.2", \ + "1404.0, 1404.0, 1404.0, 1471.8, 1607.5", \ + "2193.8, 2193.8, 2193.8, 2261.6, 2397.2", \ + "3769.2, 3769.2, 3769.2, 3837.1, 3972.7"); + } + } + } + } + + cell (a2_x4) { + area : 0.0 ; + cell_leakage_power : 0.0052 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.012 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.0042 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.00038 ; + } + pin (i1) { + direction : input ; + capacitance : 30.10 ; + } + pin (i0) { + direction : input ; + capacitance : 24.86 ; + } + pin (q) { + function : "(i0 & i1)" ; + direction : output ; + capacitance : 8.05 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("58.0, 58.0, 58.0, 61.5, 67.6", \ + "68.5, 68.5, 68.5, 72.0, 78.5", \ + "83.2, 83.2, 83.2, 87.0, 93.8", \ + "106.2, 106.2, 106.2, 110.2, 117.5", \ + "147.8, 147.8, 147.8, 151.6, 159.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("21.4, 21.4, 21.4, 24.2, 29.5", \ + "27.3, 27.3, 27.3, 30.1, 35.5", \ + "38.9, 38.9, 38.9, 41.7, 47.2", \ + "61.6, 61.6, 61.6, 64.4, 69.8", \ + "106.2, 106.2, 106.2, 109.2, 114.8"); + } + cell_fall (inslew_load_5x5__1) { + values ("47.1, 47.1, 47.1, 50.8, 57.5", \ + "51.4, 51.4, 51.4, 55.2, 62.0", \ + "52.5, 52.5, 52.5, 56.3, 63.4", \ + "46.6, 46.6, 46.6, 50.4, 57.7", \ + "26.7, 26.7, 26.7, 30.6, 38.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("22.9, 22.9, 22.9, 25.7, 31.0", \ + "28.7, 28.7, 28.7, 31.5, 36.9", \ + "39.3, 39.3, 39.3, 42.1, 47.6", \ + "59.4, 59.4, 59.4, 62.2, 67.8", \ + "98.4, 98.4, 98.4, 101.2, 106.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("52.5, 52.5, 52.5, 56.0, 62.2", \ + "57.3, 57.3, 57.3, 60.9, 67.3", \ + "63.0, 63.0, 63.0, 66.8, 73.5", \ + "69.8, 69.8, 69.8, 73.8, 81.1", \ + "79.8, 79.8, 79.8, 83.5, 91.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("21.7, 21.7, 21.7, 24.6, 29.8", \ + "26.9, 26.9, 26.9, 29.7, 35.1", \ + "37.3, 37.3, 37.3, 40.0, 45.5", \ + "57.9, 57.9, 57.9, 60.6, 66.0", \ + "98.5, 98.5, 98.5, 101.5, 107.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("50.2, 50.2, 50.2, 54.0, 60.7", \ + "57.6, 57.6, 57.6, 61.3, 68.2", \ + "65.7, 65.7, 65.7, 69.5, 76.6", \ + "74.8, 74.8, 74.8, 78.7, 86.1", \ + "87.2, 87.2, 87.2, 91.1, 98.7"); + } + fall_transition (inslew_load_5x5__1) { + values ("24.4, 24.4, 24.4, 27.2, 32.6", \ + "31.3, 31.3, 31.3, 34.1, 39.5", \ + "44.2, 44.2, 44.2, 47.0, 52.5", \ + "69.0, 69.0, 69.0, 71.8, 77.4", \ + "117.8, 117.8, 117.8, 120.6, 126.2"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1273.4, 1273.4, 1273.4, 1374.0, 1575.4", \ + "1558.4, 1558.4, 1558.4, 1659.1, 1860.5", \ + "2120.5, 2120.5, 2120.5, 2221.2, 2422.5", \ + "3235.2, 3235.2, 3235.2, 3335.9, 3537.2", \ + "5455.6, 5455.6, 5455.6, 5556.3, 5757.6"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1296.4, 1296.4, 1296.4, 1397.1, 1598.4", \ + "1508.6, 1508.6, 1508.6, 1609.3, 1810.6", \ + "1916.3, 1916.3, 1916.3, 2016.9, 2218.3", \ + "2710.5, 2710.5, 2710.5, 2811.2, 3012.5", \ + "4277.8, 4277.8, 4277.8, 4378.5, 4579.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("1331.7, 1331.7, 1331.7, 1432.4, 1633.7", \ + "1603.9, 1603.9, 1603.9, 1704.6, 1905.9", \ + "2148.3, 2148.3, 2148.3, 2249.0, 2450.3", \ + "3233.5, 3233.5, 3233.5, 3334.2, 3535.6", \ + "5399.1, 5399.1, 5399.1, 5499.8, 5701.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("1393.5, 1393.5, 1393.5, 1494.2, 1695.5", \ + "1668.3, 1668.3, 1668.3, 1768.9, 1970.3", \ + "2203.7, 2203.7, 2203.7, 2304.4, 2505.8", \ + "3256.2, 3256.2, 3256.2, 3356.9, 3558.2", \ + "5347.0, 5347.0, 5347.0, 5447.7, 5649.1"); + } + } + } + } + + cell (a3_x2) { + area : 0.0 ; + cell_leakage_power : 0.0047 ; + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 0.0073 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 0.0074 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 0.008 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2)) | (!(i0) & (i1 ^ i2)))" ; + value : 0.00064 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.00033 ; + } + pin (i2) { + direction : input ; + capacitance : 22.01 ; + } + pin (i1) { + direction : input ; + capacitance : 23.07 ; + } + pin (i0) { + direction : input ; + capacitance : 22.01 ; + } + pin (q) { + function : "(i0 & i1 & i2)" ; + direction : output ; + capacitance : 5.96 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("39.6, 39.6, 39.6, 43.6, 50.7", \ + "47.1, 47.1, 47.1, 51.3, 58.7", \ + "58.3, 58.3, 58.3, 62.7, 70.7", \ + "77.8, 77.8, 77.8, 82.2, 90.6", \ + "114.6, 114.6, 114.6, 119.1, 127.6"); + } + rise_transition (inslew_load_5x5__2) { + values ("19.9, 19.9, 19.9, 23.7, 30.9", \ + "27.7, 27.7, 27.7, 31.5, 38.8", \ + "42.6, 42.6, 42.6, 46.4, 53.8", \ + "71.8, 71.8, 71.8, 75.7, 83.3", \ + "129.9, 129.9, 129.9, 133.7, 141.4"); + } + cell_fall (inslew_load_5x5__2) { + values ("28.0, 28.0, 28.0, 31.7, 38.1", \ + "29.5, 29.5, 29.5, 33.4, 40.3", \ + "28.6, 28.6, 28.6, 32.8, 40.2", \ + "23.7, 23.7, 23.7, 27.9, 35.9", \ + "11.6, 11.6, 11.6, 16.0, 24.3"); + } + fall_transition (inslew_load_5x5__2) { + values ("13.6, 13.6, 13.6, 16.3, 21.5", \ + "18.5, 18.5, 18.5, 21.3, 26.6", \ + "27.9, 27.9, 27.9, 30.8, 36.2", \ + "46.2, 46.2, 46.2, 49.1, 54.8", \ + "82.4, 82.4, 82.4, 85.3, 91.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("37.8, 37.8, 37.8, 41.9, 49.0", \ + "41.4, 41.4, 41.4, 45.6, 53.1", \ + "45.6, 45.6, 45.6, 50.0, 58.0", \ + "51.5, 51.5, 51.5, 55.8, 64.2", \ + "61.2, 61.2, 61.2, 65.6, 74.2"); + } + rise_transition (inslew_load_5x5__2) { + values ("21.0, 21.0, 21.0, 24.8, 31.9", \ + "27.9, 27.9, 27.9, 31.7, 39.0", \ + "41.5, 41.5, 41.5, 45.3, 52.6", \ + "68.1, 68.1, 68.1, 71.9, 79.5", \ + "121.1, 121.1, 121.1, 124.9, 132.6"); + } + cell_fall (inslew_load_5x5__2) { + values ("31.9, 31.9, 31.9, 35.7, 42.2", \ + "36.3, 36.3, 36.3, 40.3, 47.3", \ + "41.5, 41.5, 41.5, 45.7, 53.3", \ + "49.2, 49.2, 49.2, 53.4, 61.4", \ + "62.4, 62.4, 62.4, 66.8, 75.2"); + } + fall_transition (inslew_load_5x5__2) { + values ("15.1, 15.1, 15.1, 17.9, 23.1", \ + "20.9, 20.9, 20.9, 23.7, 29.0", \ + "32.0, 32.0, 32.0, 34.9, 40.3", \ + "53.7, 53.7, 53.7, 56.6, 62.3", \ + "96.8, 96.8, 96.8, 99.7, 105.5"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("36.2, 36.2, 36.2, 40.3, 47.5", \ + "35.6, 35.6, 35.6, 39.8, 47.2", \ + "32.0, 32.0, 32.0, 36.4, 44.3", \ + "22.4, 22.4, 22.4, 26.7, 35.1", \ + "1.3, 1.3, 1.3, 5.7, 14.3"); + } + rise_transition (inslew_load_5x5__2) { + values ("22.2, 22.2, 22.2, 25.9, 33.1", \ + "28.3, 28.3, 28.3, 32.0, 39.4", \ + "40.4, 40.4, 40.4, 44.2, 51.6", \ + "64.3, 64.3, 64.3, 68.2, 75.7", \ + "112.1, 112.1, 112.1, 115.9, 123.5"); + } + cell_fall (inslew_load_5x5__2) { + values ("36.0, 36.0, 36.0, 39.8, 46.6", \ + "44.6, 44.6, 44.6, 48.6, 55.8", \ + "58.6, 58.6, 58.6, 62.7, 70.5", \ + "84.6, 84.6, 84.6, 88.9, 97.0", \ + "134.8, 134.8, 134.8, 139.2, 147.7"); + } + fall_transition (inslew_load_5x5__2) { + values ("16.8, 16.8, 16.8, 19.6, 24.8", \ + "23.9, 23.9, 23.9, 26.7, 32.1", \ + "37.7, 37.7, 37.7, 40.6, 46.1", \ + "64.8, 64.8, 64.8, 67.7, 73.5", \ + "118.9, 118.9, 118.9, 121.8, 127.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__2) { + values ("804.7, 804.7, 804.7, 879.3, 1028.3", \ + "1069.5, 1069.5, 1069.5, 1144.0, 1293.1", \ + "1592.3, 1592.3, 1592.3, 1666.8, 1815.9", \ + "2632.7, 2632.7, 2632.7, 2707.3, 2856.4", \ + "4709.9, 4709.9, 4709.9, 4784.4, 4933.5"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("697.0, 697.0, 697.0, 771.5, 920.6", \ + "884.5, 884.5, 884.5, 959.1, 1108.2", \ + "1254.3, 1254.3, 1254.3, 1328.9, 1478.0", \ + "1989.9, 1989.9, 1989.9, 2064.4, 2213.5", \ + "3457.4, 3457.4, 3457.4, 3531.9, 3681.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__2) { + values ("884.9, 884.9, 884.9, 959.5, 1108.6", \ + "1139.2, 1139.2, 1139.2, 1213.8, 1362.9", \ + "1644.9, 1644.9, 1644.9, 1719.4, 1868.5", \ + "2652.3, 2652.3, 2652.3, 2726.9, 2876.0", \ + "4665.2, 4665.2, 4665.2, 4739.7, 4888.8"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("798.3, 798.3, 798.3, 872.8, 1021.9", \ + "1033.6, 1033.6, 1033.6, 1108.1, 1257.2", \ + "1499.7, 1499.7, 1499.7, 1574.3, 1723.3", \ + "2427.5, 2427.5, 2427.5, 2502.0, 2651.1", \ + "4281.2, 4281.2, 4281.2, 4355.7, 4504.8"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__2) { + values ("954.7, 954.7, 954.7, 1029.3, 1178.4", \ + "1190.9, 1190.9, 1190.9, 1265.5, 1414.6", \ + "1662.5, 1662.5, 1662.5, 1737.1, 1886.2", \ + "2604.0, 2604.0, 2604.0, 2678.5, 2827.6", \ + "4484.8, 4484.8, 4484.8, 4559.4, 4708.5"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("914.3, 914.3, 914.3, 988.8, 1137.9", \ + "1228.8, 1228.8, 1228.8, 1303.4, 1452.4", \ + "1854.3, 1854.3, 1854.3, 1928.8, 2077.9", \ + "3101.7, 3101.7, 3101.7, 3176.2, 3325.3", \ + "5595.1, 5595.1, 5595.1, 5669.6, 5818.7"); + } + } + } + } + + cell (a3_x4) { + area : 0.0 ; + cell_leakage_power : 0.0042 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 0.012 ; + } + leakage_power () { + when : "(i0 & (i1 ^ i2))" ; + value : 0.0042 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0))" ; + value : 0.0045 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2)) | (!(i0) & (i1 ^ i2)))" ; + value : 0.00038 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.00019 ; + } + pin (i2) { + direction : input ; + capacitance : 23.20 ; + } + pin (i1) { + direction : input ; + capacitance : 21.79 ; + } + pin (i0) { + direction : input ; + capacitance : 21.79 ; + } + pin (q) { + function : "(i0 & i1 & i2)" ; + direction : output ; + capacitance : 8.91 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("74.6, 74.6, 74.6, 78.5, 85.7", \ + "85.8, 85.8, 85.8, 90.0, 97.3", \ + "100.7, 100.7, 100.7, 104.9, 112.6", \ + "120.8, 120.8, 120.8, 125.2, 133.4", \ + "152.1, 152.1, 152.1, 156.4, 164.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("31.1, 31.1, 31.1, 34.2, 40.2", \ + "37.1, 37.1, 37.1, 40.2, 46.3", \ + "48.9, 48.9, 48.9, 52.0, 58.1", \ + "71.8, 71.8, 71.8, 74.8, 80.9", \ + "116.4, 116.4, 116.4, 119.8, 126.0"); + } + cell_fall (inslew_load_5x5__3) { + values ("68.0, 68.0, 68.0, 72.0, 79.7", \ + "76.6, 76.6, 76.6, 80.7, 88.5", \ + "84.6, 84.6, 84.6, 88.8, 96.7", \ + "88.9, 88.9, 88.9, 93.2, 101.3", \ + "85.7, 85.7, 85.7, 90.0, 98.3"); + } + fall_transition (inslew_load_5x5__3) { + values ("33.2, 33.2, 33.2, 36.3, 42.3", \ + "39.6, 39.6, 39.6, 42.7, 48.7", \ + "51.4, 51.4, 51.4, 54.6, 60.6", \ + "73.7, 73.7, 73.7, 76.8, 82.9", \ + "116.6, 116.6, 116.6, 119.7, 125.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("70.0, 70.0, 70.0, 74.0, 81.2", \ + "75.7, 75.7, 75.7, 79.8, 87.2", \ + "82.2, 82.2, 82.2, 86.4, 94.1", \ + "88.0, 88.0, 88.0, 92.3, 100.5", \ + "92.6, 92.6, 92.6, 96.8, 105.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("31.5, 31.5, 31.5, 34.6, 40.6", \ + "36.9, 36.9, 36.9, 40.0, 46.0", \ + "47.4, 47.4, 47.4, 50.5, 56.5", \ + "68.3, 68.3, 68.3, 71.3, 77.4", \ + "109.3, 109.3, 109.3, 112.7, 118.8"); + } + cell_fall (inslew_load_5x5__3) { + values ("71.3, 71.3, 71.3, 75.4, 83.0", \ + "82.1, 82.1, 82.1, 86.2, 94.0", \ + "95.5, 95.5, 95.5, 99.7, 107.6", \ + "111.6, 111.6, 111.6, 115.8, 124.1", \ + "133.8, 133.8, 133.8, 138.2, 146.6"); + } + fall_transition (inslew_load_5x5__3) { + values ("34.9, 34.9, 34.9, 38.0, 44.0", \ + "42.2, 42.2, 42.2, 45.3, 51.3", \ + "55.9, 55.9, 55.9, 59.0, 65.1", \ + "81.9, 81.9, 81.9, 85.1, 91.2", \ + "132.8, 132.8, 132.8, 136.0, 142.2"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("67.0, 67.0, 67.0, 70.9, 78.2", \ + "67.5, 67.5, 67.5, 71.6, 79.0", \ + "65.5, 65.5, 65.5, 69.8, 77.4", \ + "56.3, 56.3, 56.3, 60.7, 68.8", \ + "32.1, 32.1, 32.1, 36.3, 44.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("32.5, 32.5, 32.5, 35.6, 41.5", \ + "37.1, 37.1, 37.1, 40.2, 46.2", \ + "46.5, 46.5, 46.5, 49.6, 55.7", \ + "65.5, 65.5, 65.5, 68.6, 74.6", \ + "103.1, 103.1, 103.1, 106.4, 112.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("74.8, 74.8, 74.8, 78.9, 86.6", \ + "89.1, 89.1, 89.1, 93.3, 101.1", \ + "110.2, 110.2, 110.2, 114.4, 122.4", \ + "143.9, 143.9, 143.9, 148.2, 156.4", \ + "206.8, 206.8, 206.8, 211.1, 219.6"); + } + fall_transition (inslew_load_5x5__3) { + values ("36.7, 36.7, 36.7, 39.8, 45.8", \ + "45.4, 45.4, 45.4, 48.6, 54.6", \ + "62.1, 62.1, 62.1, 65.2, 71.3", \ + "94.3, 94.3, 94.3, 97.4, 103.6", \ + "158.9, 158.9, 158.9, 162.1, 168.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1521.2, 1521.2, 1521.2, 1632.6, 1855.4", \ + "1761.8, 1761.8, 1761.8, 1873.2, 2096.0", \ + "2239.0, 2239.0, 2239.0, 2350.4, 2573.1", \ + "3177.9, 3177.9, 3177.9, 3289.3, 3512.1", \ + "5043.7, 5043.7, 5043.7, 5155.1, 5377.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1589.0, 1589.0, 1589.0, 1700.4, 1923.2", \ + "1799.1, 1799.1, 1799.1, 1910.5, 2133.3", \ + "2200.8, 2200.8, 2200.8, 2312.2, 2535.0", \ + "2975.2, 2975.2, 2975.2, 3086.6, 3309.4", \ + "4493.1, 4493.1, 4493.1, 4604.5, 4827.3"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1576.5, 1576.5, 1576.5, 1687.9, 1910.7", \ + "1804.4, 1804.4, 1804.4, 1915.8, 2138.5", \ + "2257.1, 2257.1, 2257.1, 2368.5, 2591.3", \ + "3159.5, 3159.5, 3159.5, 3270.9, 3493.7", \ + "4957.4, 4957.4, 4957.4, 5068.8, 5291.6"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1677.6, 1677.6, 1677.6, 1789.0, 2011.8", \ + "1930.9, 1930.9, 1930.9, 2042.3, 2265.1", \ + "2418.9, 2418.9, 2418.9, 2530.3, 2753.1", \ + "3370.4, 3370.4, 3370.4, 3481.8, 3704.6", \ + "5248.6, 5248.6, 5248.6, 5360.0, 5582.8"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1634.8, 1634.8, 1634.8, 1746.2, 1969.0", \ + "1844.6, 1844.6, 1844.6, 1956.0, 2178.8", \ + "2268.8, 2268.8, 2268.8, 2380.2, 2603.0", \ + "3119.6, 3119.6, 3119.6, 3231.0, 3453.8", \ + "4817.7, 4817.7, 4817.7, 4929.1, 5151.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1776.1, 1776.1, 1776.1, 1887.5, 2110.3", \ + "2098.6, 2098.6, 2098.6, 2210.0, 2432.7", \ + "2728.6, 2728.6, 2728.6, 2840.0, 3062.7", \ + "3967.4, 3967.4, 3967.4, 4078.8, 4301.6", \ + "6451.4, 6451.4, 6451.4, 6562.7, 6785.5"); + } + } + } + } + + cell (a4_x2) { + area : 0.0 ; + cell_leakage_power : 0.0028 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 0.0065 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & i0)" ; + value : 0.0049 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3) | (!(i0) & i1 & i2 & i3))" ; + value : 0.0045 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))) | (!(i0) & ((i1 & (i2 ^ i3)) | (!(i1) & i2 & i3))))" ; + value : 0.0004 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))))" ; + value : 0.00021 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.00014 ; + } + pin (i3) { + direction : input ; + capacitance : 26.22 ; + } + pin (i2) { + direction : input ; + capacitance : 21.77 ; + } + pin (i1) { + direction : input ; + capacitance : 21.07 ; + } + pin (i0) { + direction : input ; + capacitance : 20.79 ; + } + pin (q) { + function : "(i1 & i0 & i2 & i3)" ; + direction : output ; + capacitance : 5.75 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("65.0, 65.0, 65.0, 69.4, 77.6", \ + "70.4, 70.4, 70.4, 74.8, 83.2", \ + "79.6, 79.6, 79.6, 84.2, 92.8", \ + "96.8, 96.8, 96.8, 101.5, 110.5", \ + "129.8, 129.8, 129.8, 134.5, 143.8"); + } + rise_transition (inslew_load_5x5__4) { + values ("38.1, 38.1, 38.1, 41.9, 49.2", \ + "47.3, 47.3, 47.3, 51.1, 58.5", \ + "65.9, 65.9, 65.9, 69.7, 77.1", \ + "103.0, 103.0, 103.0, 106.9, 114.4", \ + "176.6, 176.6, 176.6, 180.4, 188.1"); + } + cell_fall (inslew_load_5x5__4) { + values ("36.7, 36.7, 36.7, 40.8, 48.0", \ + "41.4, 41.4, 41.4, 45.6, 53.2", \ + "46.2, 46.2, 46.2, 50.6, 58.6", \ + "51.4, 51.4, 51.4, 55.9, 64.5", \ + "58.9, 58.9, 58.9, 63.5, 72.3"); + } + fall_transition (inslew_load_5x5__4) { + values ("17.6, 17.6, 17.6, 20.6, 26.4", \ + "23.5, 23.5, 23.5, 26.6, 32.4", \ + "34.7, 34.7, 34.7, 37.8, 43.8", \ + "56.5, 56.5, 56.5, 59.7, 65.8", \ + "99.5, 99.5, 99.5, 102.7, 109.2"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("65.8, 65.8, 65.8, 70.2, 78.3", \ + "75.7, 75.7, 75.7, 80.1, 88.4", \ + "93.1, 93.1, 93.1, 97.7, 106.3", \ + "125.4, 125.4, 125.4, 130.1, 139.1", \ + "187.8, 187.8, 187.8, 192.6, 201.9"); + } + rise_transition (inslew_load_5x5__4) { + values ("36.3, 36.3, 36.3, 40.0, 47.3", \ + "46.2, 46.2, 46.2, 50.0, 57.4", \ + "65.7, 65.7, 65.7, 69.5, 77.0", \ + "104.6, 104.6, 104.6, 108.5, 116.1", \ + "182.3, 182.3, 182.3, 186.2, 193.8"); + } + cell_fall (inslew_load_5x5__4) { + values ("34.0, 34.0, 34.0, 38.1, 45.2", \ + "35.5, 35.5, 35.5, 39.7, 47.1", \ + "32.8, 32.8, 32.8, 37.2, 45.0", \ + "22.0, 22.0, 22.0, 26.5, 34.9", \ + "-3.8, -3.8, -3.8, 0.7, 9.5"); + } + fall_transition (inslew_load_5x5__4) { + values ("16.5, 16.5, 16.5, 19.5, 25.2", \ + "21.3, 21.3, 21.3, 24.4, 30.2", \ + "30.3, 30.3, 30.3, 33.4, 39.4", \ + "47.6, 47.6, 47.6, 50.8, 56.9", \ + "81.5, 81.5, 81.5, 84.8, 91.1"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("64.5, 64.5, 64.5, 68.8, 76.9", \ + "77.6, 77.6, 77.6, 82.1, 90.4", \ + "100.3, 100.3, 100.3, 104.9, 113.5", \ + "142.1, 142.1, 142.1, 146.8, 155.8", \ + "222.8, 222.8, 222.8, 227.6, 236.8"); + } + rise_transition (inslew_load_5x5__4) { + values ("33.9, 33.9, 33.9, 37.6, 44.9", \ + "44.0, 44.0, 44.0, 47.8, 55.1", \ + "63.8, 63.8, 63.8, 67.6, 75.0", \ + "102.9, 102.9, 102.9, 106.8, 114.3", \ + "180.8, 180.8, 180.8, 184.7, 192.3"); + } + cell_fall (inslew_load_5x5__4) { + values ("32.0, 32.0, 32.0, 36.1, 43.1", \ + "31.5, 31.5, 31.5, 35.6, 43.0", \ + "24.5, 24.5, 24.5, 28.8, 36.6", \ + "4.4, 4.4, 4.4, 8.9, 17.1", \ + "-41.6, -41.6, -41.6, -37.1, -28.3"); + } + fall_transition (inslew_load_5x5__4) { + values ("15.6, 15.6, 15.6, 18.6, 24.3", \ + "19.8, 19.8, 19.8, 22.9, 28.7", \ + "27.7, 27.7, 27.7, 30.8, 36.8", \ + "42.6, 42.6, 42.6, 45.7, 51.8", \ + "71.4, 71.4, 71.4, 74.6, 80.9"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("62.3, 62.3, 62.3, 66.7, 74.6", \ + "78.7, 78.7, 78.7, 83.1, 91.4", \ + "106.9, 106.9, 106.9, 111.5, 120.0", \ + "158.6, 158.6, 158.6, 163.3, 172.3", \ + "258.8, 258.8, 258.8, 263.6, 272.8"); + } + rise_transition (inslew_load_5x5__4) { + values ("31.6, 31.6, 31.6, 35.3, 42.5", \ + "42.1, 42.1, 42.1, 45.9, 53.2", \ + "62.5, 62.5, 62.5, 66.3, 73.7", \ + "102.4, 102.4, 102.4, 106.3, 113.8", \ + "182.0, 182.0, 182.0, 185.8, 193.5"); + } + cell_fall (inslew_load_5x5__4) { + values ("29.6, 29.6, 29.6, 33.6, 40.5", \ + "27.3, 27.3, 27.3, 31.4, 38.6", \ + "16.5, 16.5, 16.5, 20.7, 28.4", \ + "-12.2, -12.2, -12.2, -7.7, 0.4", \ + "-76.1, -76.1, -76.1, -71.6, -62.9"); + } + fall_transition (inslew_load_5x5__4) { + values ("14.6, 14.6, 14.6, 17.6, 23.3", \ + "18.4, 18.4, 18.4, 21.5, 27.3", \ + "25.2, 25.2, 25.2, 28.4, 34.3", \ + "38.0, 38.0, 38.0, 41.1, 47.2", \ + "62.7, 62.7, 62.7, 65.9, 72.1"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__4) { + values ("1181.8, 1181.8, 1181.8, 1253.6, 1397.3", \ + "1457.9, 1457.9, 1457.9, 1529.8, 1673.5", \ + "2011.9, 2011.9, 2011.9, 2083.8, 2227.5", \ + "3121.8, 3121.8, 3121.8, 3193.6, 3337.3", \ + "5332.5, 5332.5, 5332.5, 5404.4, 5548.1"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("872.5, 872.5, 872.5, 944.3, 1088.0", \ + "1087.1, 1087.1, 1087.1, 1159.0, 1302.7", \ + "1510.7, 1510.7, 1510.7, 1582.5, 1726.2", \ + "2352.8, 2352.8, 2352.8, 2424.6, 2568.3", \ + "4032.5, 4032.5, 4032.5, 4104.4, 4248.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__4) { + values ("1119.9, 1119.9, 1119.9, 1191.8, 1335.4", \ + "1405.5, 1405.5, 1405.5, 1477.4, 1621.1", \ + "1971.8, 1971.8, 1971.8, 2043.6, 2187.3", \ + "3104.6, 3104.6, 3104.6, 3176.4, 3320.1", \ + "5368.1, 5368.1, 5368.1, 5440.0, 5583.7"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("799.9, 799.9, 799.9, 871.7, 1015.4", \ + "957.0, 957.0, 957.0, 1028.9, 1172.6", \ + "1265.0, 1265.0, 1265.0, 1336.9, 1480.6", \ + "1873.8, 1873.8, 1873.8, 1945.7, 2089.4", \ + "3085.2, 3085.2, 3085.2, 3157.0, 3300.7"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__4) { + values ("1038.0, 1038.0, 1038.0, 1109.9, 1253.6", \ + "1317.3, 1317.3, 1317.3, 1389.1, 1532.8", \ + "1870.8, 1870.8, 1870.8, 1942.7, 2086.4", \ + "2973.3, 2973.3, 2973.3, 3045.2, 3188.9", \ + "5174.8, 5174.8, 5174.8, 5246.6, 5390.3"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("747.6, 747.6, 747.6, 819.5, 963.2", \ + "874.9, 874.9, 874.9, 946.7, 1090.4", \ + "1122.6, 1122.6, 1122.6, 1194.5, 1338.2", \ + "1609.2, 1609.2, 1609.2, 1681.0, 1824.7", \ + "2574.6, 2574.6, 2574.6, 2646.5, 2790.2"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__4) { + values ("960.8, 960.8, 960.8, 1032.7, 1176.4", \ + "1240.5, 1240.5, 1240.5, 1312.4, 1456.1", \ + "1792.5, 1792.5, 1792.5, 1864.4, 2008.1", \ + "2888.3, 2888.3, 2888.3, 2960.2, 3103.9", \ + "5075.0, 5075.0, 5075.0, 5146.8, 5290.5"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("689.1, 689.1, 689.1, 761.0, 904.7", \ + "793.0, 793.0, 793.0, 864.9, 1008.6", \ + "991.9, 991.9, 991.9, 1063.7, 1207.4", \ + "1380.2, 1380.2, 1380.2, 1452.0, 1595.7", \ + "2149.1, 2149.1, 2149.1, 2221.0, 2364.7"); + } + } + } + } + + cell (a4_x4) { + area : 0.0 ; + cell_leakage_power : 0.0036 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 0.012 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & i0)" ; + value : 0.0049 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3) | (!(i0) & i1 & i2 & i3))" ; + value : 0.0045 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))) | (!(i0) & ((i1 & (i2 ^ i3)) | (!(i1) & i2 & i3))))" ; + value : 0.0004 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))))" ; + value : 0.00021 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.00014 ; + } + pin (i3) { + direction : input ; + capacitance : 26.66 ; + } + pin (i2) { + direction : input ; + capacitance : 22.80 ; + } + pin (i1) { + direction : input ; + capacitance : 21.74 ; + } + pin (i0) { + direction : input ; + capacitance : 20.76 ; + } + pin (q) { + function : "(i0 & i1 & i2 & i3)" ; + direction : output ; + capacitance : 8.91 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("78.5, 78.5, 78.5, 82.7, 90.2", \ + "82.0, 82.0, 82.0, 86.2, 93.9", \ + "87.4, 87.4, 87.4, 91.8, 99.8", \ + "96.4, 96.4, 96.4, 100.7, 109.1", \ + "112.2, 112.2, 112.2, 116.4, 124.7"); + } + rise_transition (inslew_load_5x5__3) { + values ("42.1, 42.1, 42.1, 45.1, 51.2", \ + "49.5, 49.5, 49.5, 52.5, 58.6", \ + "64.4, 64.4, 64.4, 67.5, 73.5", \ + "94.5, 94.5, 94.5, 97.9, 103.8", \ + "154.3, 154.3, 154.3, 157.7, 164.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("55.2, 55.2, 55.2, 59.3, 66.7", \ + "63.7, 63.7, 63.7, 67.8, 75.5", \ + "74.0, 74.0, 74.0, 78.2, 86.0", \ + "87.0, 87.0, 87.0, 91.3, 99.4", \ + "106.6, 106.6, 106.6, 110.9, 119.3"); + } + fall_transition (inslew_load_5x5__3) { + values ("26.9, 26.9, 26.9, 29.9, 35.8", \ + "34.0, 34.0, 34.0, 37.1, 43.1", \ + "47.4, 47.4, 47.4, 50.5, 56.6", \ + "73.3, 73.3, 73.3, 76.4, 82.6", \ + "124.1, 124.1, 124.1, 127.2, 133.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("80.0, 80.0, 80.0, 84.1, 91.6", \ + "88.3, 88.3, 88.3, 92.5, 100.2", \ + "102.1, 102.1, 102.1, 106.4, 114.5", \ + "126.2, 126.2, 126.2, 130.4, 138.8", \ + "170.7, 170.7, 170.7, 174.9, 183.2"); + } + rise_transition (inslew_load_5x5__3) { + values ("40.6, 40.6, 40.6, 43.6, 49.7", \ + "48.5, 48.5, 48.5, 51.6, 57.6", \ + "64.6, 64.6, 64.6, 67.6, 73.6", \ + "96.1, 96.1, 96.1, 99.4, 105.4", \ + "159.1, 159.1, 159.1, 162.5, 169.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("52.6, 52.6, 52.6, 56.7, 64.0", \ + "58.0, 58.0, 58.0, 62.1, 69.7", \ + "61.1, 61.1, 61.1, 65.3, 73.1", \ + "58.0, 58.0, 58.0, 62.2, 70.2", \ + "42.9, 42.9, 42.9, 47.2, 55.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("25.6, 25.6, 25.6, 28.6, 34.5", \ + "31.6, 31.6, 31.6, 34.6, 40.6", \ + "42.5, 42.5, 42.5, 45.6, 51.7", \ + "63.2, 63.2, 63.2, 66.3, 72.4", \ + "103.4, 103.4, 103.4, 106.5, 112.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("79.8, 79.8, 79.8, 83.9, 91.3", \ + "91.8, 91.8, 91.8, 96.0, 103.6", \ + "111.3, 111.3, 111.3, 115.7, 123.7", \ + "145.3, 145.3, 145.3, 149.6, 158.0", \ + "208.4, 208.4, 208.4, 212.6, 220.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("38.7, 38.7, 38.7, 41.7, 47.8", \ + "46.9, 46.9, 46.9, 49.9, 56.0", \ + "63.0, 63.0, 63.0, 66.0, 72.1", \ + "94.9, 94.9, 94.9, 98.3, 104.2", \ + "158.2, 158.2, 158.2, 161.6, 168.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("50.6, 50.6, 50.6, 54.7, 61.9", \ + "54.3, 54.3, 54.3, 58.4, 65.9", \ + "53.2, 53.2, 53.2, 57.4, 65.1", \ + "40.8, 40.8, 40.8, 45.0, 53.0", \ + "5.4, 5.4, 5.4, 9.7, 18.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("24.6, 24.6, 24.6, 27.7, 33.6", \ + "30.0, 30.0, 30.0, 33.0, 39.0", \ + "39.6, 39.6, 39.6, 42.7, 48.7", \ + "57.5, 57.5, 57.5, 60.6, 66.7", \ + "91.9, 91.9, 91.9, 95.0, 101.2"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("78.9, 78.9, 78.9, 83.0, 90.4", \ + "94.5, 94.5, 94.5, 98.7, 106.3", \ + "119.8, 119.8, 119.8, 124.1, 132.2", \ + "163.9, 163.9, 163.9, 168.2, 176.6", \ + "246.4, 246.4, 246.4, 250.6, 258.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("36.9, 36.9, 36.9, 40.0, 46.0", \ + "45.5, 45.5, 45.5, 48.5, 54.6", \ + "62.2, 62.2, 62.2, 65.2, 71.2", \ + "94.8, 94.8, 94.8, 98.2, 104.1", \ + "159.4, 159.4, 159.4, 162.8, 169.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("48.3, 48.3, 48.3, 52.4, 59.6", \ + "50.4, 50.4, 50.4, 54.5, 61.9", \ + "45.8, 45.8, 45.8, 49.9, 57.6", \ + "25.2, 25.2, 25.2, 29.4, 37.2", \ + "-28.2, -28.2, -28.2, -23.9, -15.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("23.5, 23.5, 23.5, 26.6, 32.5", \ + "28.4, 28.4, 28.4, 31.4, 37.4", \ + "36.9, 36.9, 36.9, 40.0, 46.0", \ + "52.5, 52.5, 52.5, 55.6, 61.7", \ + "82.1, 82.1, 82.1, 85.2, 91.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1874.0, 1874.0, 1874.0, 1985.4, 2208.2", \ + "2191.4, 2191.4, 2191.4, 2302.8, 2525.6", \ + "2829.1, 2829.1, 2829.1, 2940.5, 3163.3", \ + "4112.1, 4112.1, 4112.1, 4223.5, 4446.3", \ + "6671.0, 6671.0, 6671.0, 6782.4, 7005.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1538.3, 1538.3, 1538.3, 1649.7, 1872.5", \ + "1829.1, 1829.1, 1829.1, 1940.5, 2163.2", \ + "2393.9, 2393.9, 2393.9, 2505.3, 2728.1", \ + "3506.8, 3506.8, 3506.8, 3618.2, 3841.0", \ + "5715.0, 5715.0, 5715.0, 5826.4, 6049.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1804.4, 1804.4, 1804.4, 1915.8, 2138.5", \ + "2132.8, 2132.8, 2132.8, 2244.2, 2467.0", \ + "2793.2, 2793.2, 2793.2, 2904.6, 3127.4", \ + "4107.0, 4107.0, 4107.0, 4218.4, 4441.2", \ + "6737.2, 6737.2, 6737.2, 6848.6, 7071.3"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1453.2, 1453.2, 1453.2, 1564.6, 1787.4", \ + "1675.3, 1675.3, 1675.3, 1786.7, 2009.4", \ + "2100.0, 2100.0, 2100.0, 2211.4, 2434.2", \ + "2926.5, 2926.5, 2926.5, 3037.9, 3260.7", \ + "4557.6, 4557.6, 4557.6, 4669.0, 4891.8"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1712.2, 1712.2, 1712.2, 1823.6, 2046.4", \ + "2038.1, 2038.1, 2038.1, 2149.5, 2372.2", \ + "2683.7, 2683.7, 2683.7, 2795.1, 3017.9", \ + "3972.6, 3972.6, 3972.6, 4083.9, 4306.7", \ + "6542.2, 6542.2, 6542.2, 6653.6, 6876.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1391.9, 1391.9, 1391.9, 1503.3, 1726.1", \ + "1577.2, 1577.2, 1577.2, 1688.6, 1911.3", \ + "1929.2, 1929.2, 1929.2, 2040.5, 2263.3", \ + "2605.9, 2605.9, 2605.9, 2717.2, 2940.0", \ + "3932.8, 3932.8, 3932.8, 4044.2, 4267.0"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1626.7, 1626.7, 1626.7, 1738.1, 1960.9", \ + "1955.4, 1955.4, 1955.4, 2066.8, 2289.6", \ + "2603.7, 2603.7, 2603.7, 2715.1, 2937.9", \ + "3890.9, 3890.9, 3890.9, 4002.3, 4225.1", \ + "6454.2, 6454.2, 6454.2, 6565.6, 6788.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1322.6, 1322.6, 1322.6, 1434.0, 1656.8", \ + "1480.2, 1480.2, 1480.2, 1591.6, 1814.4", \ + "1772.6, 1772.6, 1772.6, 1884.0, 2106.7", \ + "2328.2, 2328.2, 2328.2, 2439.6, 2662.4", \ + "3409.5, 3409.5, 3409.5, 3520.9, 3743.7"); + } + } + } + } + + cell (an12_x1) { + area : 0.0 ; + cell_leakage_power : 0.0068 ; + leakage_power () { + when : "(i1 & !(i0))" ; + value : 0.0091 ; + } + leakage_power () { + when : "!(i1)" ; + value : 0.0045 ; + } + pin (i1) { + direction : input ; + capacitance : 21.08 ; + } + pin (i0) { + direction : input ; + capacitance : 23.85 ; + } + pin (q) { + function : "(i1 & !(i0))" ; + direction : output ; + capacitance : 6.75 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__5) { + values ("41.2, 41.2, 41.2, 46.4, 55.9", \ + "48.5, 48.5, 48.5, 54.1, 64.2", \ + "59.8, 59.8, 59.8, 65.8, 76.8", \ + "79.7, 79.7, 79.7, 86.1, 98.2", \ + "117.9, 117.9, 117.9, 124.6, 137.7"); + } + rise_transition (inslew_load_5x5__5) { + values ("25.3, 25.3, 25.3, 32.5, 47.0", \ + "32.1, 32.1, 32.1, 39.4, 53.8", \ + "45.2, 45.2, 45.2, 52.6, 67.2", \ + "71.0, 71.0, 71.0, 78.5, 93.3", \ + "122.1, 122.1, 122.1, 129.7, 144.7"); + } + cell_fall (inslew_load_5x5__5) { + values ("31.0, 31.0, 31.0, 36.1, 45.0", \ + "31.6, 31.6, 31.6, 36.9, 46.4", \ + "28.4, 28.4, 28.4, 34.1, 44.3", \ + "18.6, 18.6, 18.6, 24.5, 35.6", \ + "-4.5, -4.5, -4.5, 1.8, 13.6"); + } + fall_transition (inslew_load_5x5__5) { + values ("17.5, 17.5, 17.5, 21.8, 30.2", \ + "23.0, 23.0, 23.0, 27.4, 35.9", \ + "33.2, 33.2, 33.2, 37.7, 46.4", \ + "52.8, 52.8, 52.8, 57.4, 66.3", \ + "91.4, 91.4, 91.4, 96.1, 105.3"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__5) { + values ("11.4, 11.4, 11.4, 18.5, 30.5", \ + "14.2, 14.2, 14.2, 22.0, 35.8", \ + "19.0, 19.0, 19.0, 27.2, 42.6", \ + "28.1, 28.1, 28.1, 36.6, 53.0", \ + "46.1, 46.1, 46.1, 54.8, 71.8"); + } + rise_transition (inslew_load_5x5__5) { + values ("26.9, 26.9, 26.9, 35.0, 50.7", \ + "47.4, 47.4, 47.4, 55.7, 71.9", \ + "87.5, 87.5, 87.5, 96.0, 112.7", \ + "167.4, 167.4, 167.4, 176.0, 193.0", \ + "326.9, 326.9, 326.9, 335.6, 352.9"); + } + cell_fall (inslew_load_5x5__5) { + values ("8.6, 8.6, 8.6, 14.8, 25.4", \ + "8.5, 8.5, 8.5, 15.4, 27.6", \ + "7.7, 7.7, 7.7, 15.0, 28.6", \ + "5.6, 5.6, 5.6, 13.2, 27.8", \ + "1.2, 1.2, 1.2, 9.0, 24.1"); + } + fall_transition (inslew_load_5x5__5) { + values ("19.5, 19.5, 19.5, 24.3, 33.1", \ + "35.4, 35.4, 35.4, 40.3, 49.7", \ + "66.6, 66.6, 66.6, 71.7, 81.6", \ + "128.7, 128.7, 128.7, 134.0, 144.3", \ + "252.9, 252.9, 252.9, 258.2, 268.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__5) { + values ("835.0, 835.0, 835.0, 919.4, 1088.2", \ + "1107.2, 1107.2, 1107.2, 1191.6, 1360.3", \ + "1648.6, 1648.6, 1648.6, 1733.0, 1901.7", \ + "2729.3, 2729.3, 2729.3, 2813.7, 2982.4", \ + "4889.1, 4889.1, 4889.1, 4973.4, 5142.2"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("762.9, 762.9, 762.9, 847.3, 1016.1", \ + "942.7, 942.7, 942.7, 1027.0, 1195.8", \ + "1296.9, 1296.9, 1296.9, 1381.2, 1550.0", \ + "2001.3, 2001.3, 2001.3, 2085.7, 2254.4", \ + "3407.1, 3407.1, 3407.1, 3491.4, 3660.2"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__5) { + values ("222.6, 222.6, 222.6, 306.9, 475.7", \ + "360.8, 360.8, 360.8, 445.1, 613.9", \ + "637.1, 637.1, 637.1, 721.5, 890.3", \ + "1189.9, 1189.9, 1189.9, 1274.3, 1443.0", \ + "2295.5, 2295.5, 2295.5, 2379.8, 2548.6"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("230.3, 230.3, 230.3, 314.6, 483.4", \ + "376.2, 376.2, 376.2, 460.5, 629.3", \ + "668.0, 668.0, 668.0, 752.3, 921.1", \ + "1251.6, 1251.6, 1251.6, 1335.9, 1504.7", \ + "2418.8, 2418.8, 2418.8, 2503.1, 2671.9"); + } + } + } + } + + cell (an12_x4) { + area : 0.0 ; + cell_leakage_power : 0.0061 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.00038 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 0.013 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.0062 ; + } + pin (i1) { + direction : input ; + capacitance : 19.90 ; + } + pin (i0) { + direction : input ; + capacitance : 25.52 ; + } + pin (q) { + function : "(!(i0) & i1)" ; + direction : output ; + capacitance : 9.03 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("57.2, 57.2, 57.2, 61.1, 67.9", \ + "65.7, 65.7, 65.7, 69.6, 76.8", \ + "79.0, 79.0, 79.0, 83.2, 90.8", \ + "101.8, 101.8, 101.8, 106.2, 114.4", \ + "146.8, 146.8, 146.8, 151.1, 159.6"); + } + rise_transition (inslew_load_5x5__6) { + values ("23.4, 23.4, 23.4, 26.6, 32.4", \ + "29.7, 29.7, 29.7, 32.8, 38.8", \ + "42.2, 42.2, 42.2, 45.3, 51.5", \ + "67.2, 67.2, 67.2, 70.2, 76.3", \ + "117.0, 117.0, 117.0, 120.4, 126.6"); + } + cell_fall (inslew_load_5x5__6) { + values ("40.8, 40.8, 40.8, 44.8, 51.9", \ + "43.8, 43.8, 43.8, 48.0, 55.4", \ + "43.5, 43.5, 43.5, 47.7, 55.5", \ + "36.1, 36.1, 36.1, 40.4, 48.4", \ + "15.3, 15.3, 15.3, 19.6, 28.0"); + } + fall_transition (inslew_load_5x5__6) { + values ("20.1, 20.1, 20.1, 23.2, 29.1", \ + "25.8, 25.8, 25.8, 28.9, 34.9", \ + "36.3, 36.3, 36.3, 39.4, 45.5", \ + "56.2, 56.2, 56.2, 59.4, 65.5", \ + "95.3, 95.3, 95.3, 98.4, 104.7"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__6) { + values ("73.9, 73.9, 73.9, 77.6, 84.3", \ + "72.2, 72.2, 72.2, 76.0, 82.7", \ + "61.2, 61.2, 61.2, 65.1, 72.0", \ + "29.6, 29.6, 29.6, 33.5, 40.6", \ + "-43.6, -43.6, -43.6, -39.5, -32.1"); + } + rise_transition (inslew_load_5x5__6) { + values ("20.1, 20.1, 20.1, 23.2, 29.1", \ + "21.5, 21.5, 21.5, 24.6, 30.5", \ + "23.8, 23.8, 23.8, 27.0, 32.8", \ + "28.0, 28.0, 28.0, 31.1, 37.1", \ + "35.8, 35.8, 35.8, 38.9, 45.0"); + } + cell_fall (inslew_load_5x5__6) { + values ("100.6, 100.6, 100.6, 104.7, 111.9", \ + "120.5, 120.5, 120.5, 124.6, 131.9", \ + "152.3, 152.3, 152.3, 156.5, 164.0", \ + "207.6, 207.6, 207.6, 211.8, 219.6", \ + "309.1, 309.1, 309.1, 313.4, 321.5"); + } + fall_transition (inslew_load_5x5__6) { + values ("20.9, 20.9, 20.9, 24.0, 29.9", \ + "23.9, 23.9, 23.9, 27.0, 32.9", \ + "29.2, 29.2, 29.2, 32.3, 38.3", \ + "39.1, 39.1, 39.1, 42.2, 48.3", \ + "58.0, 58.0, 58.0, 61.1, 67.3"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__6) { + values ("1446.4, 1446.4, 1446.4, 1559.3, 1785.0", \ + "1791.7, 1791.7, 1791.7, 1904.5, 2130.3", \ + "2481.2, 2481.2, 2481.2, 2594.1, 2819.8", \ + "3856.8, 3856.8, 3856.8, 3969.7, 4195.4", \ + "6615.0, 6615.0, 6615.0, 6727.8, 6953.6"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("1323.7, 1323.7, 1323.7, 1436.5, 1662.3", \ + "1565.5, 1565.5, 1565.5, 1678.3, 1904.1", \ + "2032.3, 2032.3, 2032.3, 2145.2, 2370.9", \ + "2949.3, 2949.3, 2949.3, 3062.2, 3287.9", \ + "4769.2, 4769.2, 4769.2, 4882.1, 5107.8"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__6) { + values ("1755.5, 1755.5, 1755.5, 1868.4, 2094.1", \ + "1872.4, 1872.4, 1872.4, 1985.3, 2211.0", \ + "2090.3, 2090.3, 2090.3, 2203.1, 2428.9", \ + "2507.0, 2507.0, 2507.0, 2619.9, 2845.6", \ + "3322.3, 3322.3, 3322.3, 3435.1, 3660.9"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("1941.0, 1941.0, 1941.0, 2053.8, 2279.5", \ + "2235.3, 2235.3, 2235.3, 2348.2, 2573.9", \ + "2810.2, 2810.2, 2810.2, 2923.0, 3148.8", \ + "3944.7, 3944.7, 3944.7, 4057.6, 4283.3", \ + "6196.0, 6196.0, 6196.0, 6308.8, 6534.6"); + } + } + } + } + + cell (ao22_x2) { + area : 0.0 ; + cell_leakage_power : 0.0055 ; + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 0.0085 ; + } + leakage_power () { + when : "((i0 | i1) & i2)" ; + value : 0.0045 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 0.0046 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 0.0091 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.00076 ; + } + pin (i2) { + direction : input ; + capacitance : 26.92 ; + } + pin (i1) { + direction : input ; + capacitance : 23.87 ; + } + pin (i0) { + direction : input ; + capacitance : 23.95 ; + } + pin (q) { + function : "((i0 | i1) & i2)" ; + direction : output ; + capacitance : 5.05 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__7) { + values ("57.5, 57.5, 57.5, 62.3, 70.4", \ + "69.3, 69.3, 69.3, 74.1, 82.8", \ + "87.3, 87.3, 87.3, 92.3, 101.5", \ + "118.0, 118.0, 118.0, 123.2, 133.0", \ + "175.5, 175.5, 175.5, 180.8, 191.1"); + } + rise_transition (inslew_load_5x5__7) { + values ("23.1, 23.1, 23.1, 27.2, 35.0", \ + "30.1, 30.1, 30.1, 34.2, 42.2", \ + "43.6, 43.6, 43.6, 47.8, 55.9", \ + "70.0, 70.0, 70.0, 74.3, 82.6", \ + "122.5, 122.5, 122.5, 126.8, 135.2"); + } + cell_fall (inslew_load_5x5__7) { + values ("51.7, 51.7, 51.7, 56.6, 65.3", \ + "52.6, 52.6, 52.6, 57.5, 66.5", \ + "50.3, 50.3, 50.3, 55.3, 64.7", \ + "40.0, 40.0, 40.0, 45.2, 55.0", \ + "14.3, 14.3, 14.3, 19.5, 29.6"); + } + fall_transition (inslew_load_5x5__7) { + values ("30.1, 30.1, 30.1, 33.7, 40.5", \ + "35.8, 35.8, 35.8, 39.4, 46.3", \ + "47.1, 47.1, 47.1, 50.7, 57.7", \ + "69.1, 69.1, 69.1, 72.8, 79.9", \ + "112.6, 112.6, 112.6, 116.3, 123.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__7) { + values ("52.0, 52.0, 52.0, 56.6, 64.6", \ + "58.3, 58.3, 58.3, 63.1, 71.5", \ + "64.2, 64.2, 64.2, 69.2, 78.2", \ + "69.5, 69.5, 69.5, 74.7, 84.2", \ + "74.6, 74.6, 74.6, 79.8, 89.9"); + } + rise_transition (inslew_load_5x5__7) { + values ("21.1, 21.1, 21.1, 25.2, 32.9", \ + "26.6, 26.6, 26.6, 30.7, 38.6", \ + "36.9, 36.9, 36.9, 41.1, 49.2", \ + "57.0, 57.0, 57.0, 61.3, 69.5", \ + "96.6, 96.6, 96.6, 100.9, 109.3"); + } + cell_fall (inslew_load_5x5__7) { + values ("59.8, 59.8, 59.8, 64.7, 73.4", \ + "68.6, 68.6, 68.6, 73.6, 82.7", \ + "79.5, 79.5, 79.5, 84.6, 94.1", \ + "93.7, 93.7, 93.7, 98.8, 108.7", \ + "115.9, 115.9, 115.9, 121.2, 131.3"); + } + fall_transition (inslew_load_5x5__7) { + values ("30.6, 30.6, 30.6, 34.2, 41.0", \ + "38.4, 38.4, 38.4, 42.0, 49.0", \ + "53.0, 53.0, 53.0, 56.7, 63.8", \ + "81.3, 81.3, 81.3, 85.0, 92.2", \ + "136.8, 136.8, 136.8, 140.6, 148.0"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__7) { + values ("52.0, 52.0, 52.0, 56.8, 64.9", \ + "58.3, 58.3, 58.3, 63.2, 71.8", \ + "67.3, 67.3, 67.3, 72.3, 81.5", \ + "81.8, 81.8, 81.8, 87.0, 96.8", \ + "107.8, 107.8, 107.8, 113.1, 123.3"); + } + rise_transition (inslew_load_5x5__7) { + values ("23.3, 23.3, 23.3, 27.4, 35.3", \ + "29.5, 29.5, 29.5, 33.7, 41.6", \ + "41.8, 41.8, 41.8, 46.0, 54.1", \ + "66.1, 66.1, 66.1, 70.3, 78.6", \ + "114.4, 114.4, 114.4, 118.7, 127.1"); + } + cell_fall (inslew_load_5x5__7) { + values ("40.0, 40.0, 40.0, 44.6, 52.7", \ + "44.1, 44.1, 44.1, 48.8, 57.3", \ + "46.7, 46.7, 46.7, 51.7, 60.7", \ + "46.6, 46.6, 46.6, 51.8, 61.3", \ + "41.9, 41.9, 41.9, 47.1, 57.1"); + } + fall_transition (inslew_load_5x5__7) { + values ("19.3, 19.3, 19.3, 22.8, 29.4", \ + "24.9, 24.9, 24.9, 28.4, 35.2", \ + "35.4, 35.4, 35.4, 39.0, 46.0", \ + "55.8, 55.8, 55.8, 59.5, 66.6", \ + "96.0, 96.0, 96.0, 99.7, 106.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__7) { + values ("958.5, 958.5, 958.5, 1021.6, 1147.9", \ + "1198.1, 1198.1, 1198.1, 1261.2, 1387.5", \ + "1672.9, 1672.9, 1672.9, 1736.0, 1862.3", \ + "2618.3, 2618.3, 2618.3, 2681.5, 2807.8", \ + "4505.3, 4505.3, 4505.3, 4568.5, 4694.8"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("991.9, 991.9, 991.9, 1055.1, 1181.4", \ + "1139.5, 1139.5, 1139.5, 1202.7, 1329.0", \ + "1434.7, 1434.7, 1434.7, 1497.9, 1624.1", \ + "2020.4, 2020.4, 2020.4, 2083.5, 2209.8", \ + "3187.3, 3187.3, 3187.3, 3250.5, 3376.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__7) { + values ("850.7, 850.7, 850.7, 913.9, 1040.2", \ + "1018.1, 1018.1, 1018.1, 1081.3, 1207.6", \ + "1348.0, 1348.0, 1348.0, 1411.1, 1537.4", \ + "2002.0, 2002.0, 2002.0, 2065.1, 2191.4", \ + "3305.2, 3305.2, 3305.2, 3368.3, 3494.6"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("953.8, 953.8, 953.8, 1016.9, 1143.2", \ + "1134.0, 1134.0, 1134.0, 1197.1, 1323.4", \ + "1485.7, 1485.7, 1485.7, 1548.8, 1675.1", \ + "2179.7, 2179.7, 2179.7, 2242.8, 2369.1", \ + "3560.1, 3560.1, 3560.1, 3623.2, 3749.5"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__7) { + values ("1003.7, 1003.7, 1003.7, 1066.8, 1193.1", \ + "1241.8, 1241.8, 1241.8, 1305.0, 1431.3", \ + "1717.1, 1717.1, 1717.1, 1780.2, 1906.5", \ + "2665.8, 2665.8, 2665.8, 2728.9, 2855.2", \ + "4561.3, 4561.3, 4561.3, 4624.5, 4750.8"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("913.5, 913.5, 913.5, 976.6, 1102.9", \ + "1098.5, 1098.5, 1098.5, 1161.7, 1288.0", \ + "1462.9, 1462.9, 1462.9, 1526.1, 1652.3", \ + "2186.2, 2186.2, 2186.2, 2249.4, 2375.6", \ + "3628.1, 3628.1, 3628.1, 3691.2, 3817.5"); + } + } + } + } + + cell (ao22_x4) { + area : 0.0 ; + cell_leakage_power : 0.0064 ; + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 0.0079 ; + } + leakage_power () { + when : "((i0 | i1) & i2)" ; + value : 0.011 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 0.0043 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 0.0085 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.00072 ; + } + pin (i2) { + direction : input ; + capacitance : 25.77 ; + } + pin (i1) { + direction : input ; + capacitance : 22.88 ; + } + pin (i0) { + direction : input ; + capacitance : 22.25 ; + } + pin (q) { + function : "((i0 | i1) & i2)" ; + direction : output ; + capacitance : 8.81 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__8) { + values ("61.1, 61.1, 61.1, 65.0, 71.8", \ + "68.9, 68.9, 68.9, 72.8, 80.0", \ + "76.9, 76.9, 76.9, 81.1, 88.6", \ + "84.1, 84.1, 84.1, 88.5, 96.6", \ + "91.2, 91.2, 91.2, 95.4, 103.9"); + } + rise_transition (inslew_load_5x5__8) { + values ("22.4, 22.4, 22.4, 25.5, 31.3", \ + "27.2, 27.2, 27.2, 30.3, 36.2", \ + "36.6, 36.6, 36.6, 39.7, 45.7", \ + "54.8, 54.8, 54.8, 57.9, 63.8", \ + "90.1, 90.1, 90.1, 93.5, 99.7"); + } + cell_fall (inslew_load_5x5__8) { + values ("102.8, 102.8, 102.8, 107.1, 115.3", \ + "111.3, 111.3, 111.3, 115.6, 123.9", \ + "124.8, 124.8, 124.8, 129.2, 137.6", \ + "146.0, 146.0, 146.0, 150.4, 159.0", \ + "180.9, 180.9, 180.9, 185.4, 194.1"); + } + fall_transition (inslew_load_5x5__8) { + values ("60.2, 60.2, 60.2, 63.4, 69.7", \ + "68.8, 68.8, 68.8, 72.1, 78.4", \ + "86.6, 86.6, 86.6, 89.8, 96.2", \ + "122.2, 122.2, 122.2, 125.4, 131.8", \ + "192.9, 192.9, 192.9, 196.1, 202.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__8) { + values ("57.4, 57.4, 57.4, 61.2, 67.9", \ + "61.2, 61.2, 61.2, 65.1, 72.1", \ + "59.9, 59.9, 59.9, 64.1, 71.4", \ + "46.1, 46.1, 46.1, 50.5, 58.2", \ + "7.5, 7.5, 7.5, 11.7, 20.1"); + } + rise_transition (inslew_load_5x5__8) { + values ("21.1, 21.1, 21.1, 24.2, 29.9", \ + "24.9, 24.9, 24.9, 28.0, 33.9", \ + "32.2, 32.2, 32.2, 35.2, 41.2", \ + "45.8, 45.8, 45.8, 48.8, 54.9", \ + "71.9, 71.9, 71.9, 75.2, 81.2"); + } + cell_fall (inslew_load_5x5__8) { + values ("113.4, 113.4, 113.4, 117.8, 126.0", \ + "133.5, 133.5, 133.5, 137.8, 146.1", \ + "165.3, 165.3, 165.3, 169.7, 178.1", \ + "217.6, 217.6, 217.6, 222.1, 230.7", \ + "311.4, 311.4, 311.4, 315.8, 324.6"); + } + fall_transition (inslew_load_5x5__8) { + values ("61.5, 61.5, 61.5, 64.8, 71.1", \ + "73.2, 73.2, 73.2, 76.4, 82.8", \ + "96.0, 96.0, 96.0, 99.3, 105.7", \ + "140.1, 140.1, 140.1, 143.4, 149.8", \ + "226.8, 226.8, 226.8, 230.1, 236.5"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__8) { + values ("55.3, 55.3, 55.3, 59.1, 65.9", \ + "57.4, 57.4, 57.4, 61.3, 68.4", \ + "56.6, 56.6, 56.6, 60.8, 68.2", \ + "48.3, 48.3, 48.3, 52.7, 60.6", \ + "25.6, 25.6, 25.6, 29.8, 38.3"); + } + rise_transition (inslew_load_5x5__8) { + values ("22.6, 22.6, 22.6, 25.7, 31.5", \ + "26.7, 26.7, 26.7, 29.7, 35.6", \ + "34.8, 34.8, 34.8, 37.8, 43.8", \ + "50.8, 50.8, 50.8, 53.8, 59.8", \ + "82.1, 82.1, 82.1, 85.4, 91.5"); + } + cell_fall (inslew_load_5x5__8) { + values ("72.4, 72.4, 72.4, 76.6, 84.5", \ + "86.0, 86.0, 86.0, 90.2, 98.2", \ + "105.5, 105.5, 105.5, 109.8, 118.0", \ + "135.9, 135.9, 135.9, 140.3, 148.8", \ + "192.4, 192.4, 192.4, 196.8, 205.5"); + } + fall_transition (inslew_load_5x5__8) { + values ("35.8, 35.8, 35.8, 39.0, 45.1", \ + "44.4, 44.4, 44.4, 47.6, 53.8", \ + "60.7, 60.7, 60.7, 63.9, 70.2", \ + "92.3, 92.3, 92.3, 95.6, 102.0", \ + "155.7, 155.7, 155.7, 158.9, 165.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__8) { + values ("1305.5, 1305.5, 1305.5, 1415.7, 1636.0", \ + "1520.3, 1520.3, 1520.3, 1630.4, 1850.7", \ + "1943.6, 1943.6, 1943.6, 2053.8, 2274.0", \ + "2778.1, 2778.1, 2778.1, 2888.2, 3108.5", \ + "4435.8, 4435.8, 4435.8, 4545.9, 4766.2"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("2121.9, 2121.9, 2121.9, 2232.0, 2452.3", \ + "2392.2, 2392.2, 2392.2, 2502.3, 2722.6", \ + "2942.3, 2942.3, 2942.3, 3052.5, 3272.8", \ + "4047.0, 4047.0, 4047.0, 4157.2, 4377.4", \ + "6246.8, 6246.8, 6246.8, 6357.0, 6577.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__8) { + values ("1217.8, 1217.8, 1217.8, 1327.9, 1548.2", \ + "1367.8, 1367.8, 1367.8, 1477.9, 1698.2", \ + "1658.8, 1658.8, 1658.8, 1769.0, 1989.3", \ + "2225.0, 2225.0, 2225.0, 2335.1, 2555.4", \ + "3338.9, 3338.9, 3338.9, 3449.1, 3669.4"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("2118.8, 2118.8, 2118.8, 2228.9, 2449.2", \ + "2456.9, 2456.9, 2456.9, 2567.1, 2787.4", \ + "3123.6, 3123.6, 3123.6, 3233.8, 3454.1", \ + "4425.8, 4425.8, 4425.8, 4535.9, 4756.2", \ + "7000.4, 7000.4, 7000.4, 7110.6, 7330.8"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__8) { + values ("1357.4, 1357.4, 1357.4, 1467.6, 1687.9", \ + "1555.0, 1555.0, 1555.0, 1665.2, 1885.5", \ + "1951.6, 1951.6, 1951.6, 2061.8, 2282.0", \ + "2739.2, 2739.2, 2739.2, 2849.3, 3069.6", \ + "4307.2, 4307.2, 4307.2, 4417.3, 4637.6"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("1673.4, 1673.4, 1673.4, 1783.5, 2003.8", \ + "1977.9, 1977.9, 1977.9, 2088.0, 2308.3", \ + "2570.3, 2570.3, 2570.3, 2680.4, 2900.7", \ + "3736.0, 3736.0, 3736.0, 3846.1, 4066.4", \ + "6071.8, 6071.8, 6071.8, 6181.9, 6402.2"); + } + } + } + } + + cell (ao2o22_x2) { + area : 0.0 ; + cell_leakage_power : 0.0088 ; + leakage_power () { + when : "(!(i3) & !(i2) & i1 & i0)" ; + value : 0.015 ; + } + leakage_power () { + when : "((i0 | i1) & (i2 | i3))" ; + value : 0.0045 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & !(i3))" ; + value : 0.008 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 0.016 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3))" ; + value : 0.0085 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0013 ; + } + pin (i3) { + direction : input ; + capacitance : 24.48 ; + } + pin (i2) { + direction : input ; + capacitance : 29.42 ; + } + pin (i1) { + direction : input ; + capacitance : 23.80 ; + } + pin (i0) { + direction : input ; + capacitance : 23.56 ; + } + pin (q) { + function : "((i3 | i2) & (i0 | i1))" ; + direction : output ; + capacitance : 5.42 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("45.8, 45.8, 45.8, 50.1, 57.5", \ + "55.9, 55.9, 55.9, 60.4, 68.4", \ + "71.8, 71.8, 71.8, 76.5, 85.2", \ + "99.5, 99.5, 99.5, 104.7, 114.0", \ + "152.7, 152.7, 152.7, 157.8, 168.0"); + } + rise_transition (inslew_load_5x5__0) { + values ("17.8, 17.8, 17.8, 21.4, 28.2", \ + "24.1, 24.1, 24.1, 27.8, 34.8", \ + "36.2, 36.2, 36.2, 39.9, 47.2", \ + "60.3, 60.3, 60.3, 63.9, 71.3", \ + "107.8, 107.8, 107.8, 111.8, 119.0"); + } + cell_fall (inslew_load_5x5__0) { + values ("44.4, 44.4, 44.4, 49.2, 57.9", \ + "44.8, 44.8, 44.8, 49.7, 58.6", \ + "42.0, 42.0, 42.0, 47.0, 56.3", \ + "31.8, 31.8, 31.8, 36.9, 46.6", \ + "7.3, 7.3, 7.3, 12.5, 22.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("27.0, 27.0, 27.0, 30.7, 37.8", \ + "33.3, 33.3, 33.3, 37.0, 44.2", \ + "45.6, 45.6, 45.6, 49.3, 56.6", \ + "69.6, 69.6, 69.6, 73.4, 80.8", \ + "117.0, 117.0, 117.0, 120.8, 128.3"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("39.9, 39.9, 39.9, 44.2, 51.3", \ + "44.4, 44.4, 44.4, 48.8, 56.6", \ + "48.4, 48.4, 48.4, 53.0, 61.3", \ + "51.4, 51.4, 51.4, 56.4, 65.5", \ + "54.0, 54.0, 54.0, 59.3, 69.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("16.0, 16.0, 16.0, 19.5, 26.3", \ + "20.9, 20.9, 20.9, 24.5, 31.4", \ + "30.2, 30.2, 30.2, 33.9, 41.0", \ + "48.4, 48.4, 48.4, 52.1, 59.4", \ + "84.6, 84.6, 84.6, 88.3, 95.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("51.1, 51.1, 51.1, 56.0, 64.6", \ + "59.0, 59.0, 59.0, 63.9, 72.9", \ + "68.9, 68.9, 68.9, 73.9, 83.3", \ + "83.1, 83.1, 83.1, 88.3, 98.1", \ + "107.2, 107.2, 107.2, 112.5, 122.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("27.2, 27.2, 27.2, 30.9, 38.0", \ + "35.7, 35.7, 35.7, 39.4, 46.6", \ + "51.5, 51.5, 51.5, 55.2, 62.6", \ + "82.3, 82.3, 82.3, 86.1, 93.6", \ + "143.2, 143.2, 143.2, 147.0, 154.5"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("38.6, 38.6, 38.6, 42.9, 50.2", \ + "38.7, 38.7, 38.7, 43.1, 50.9", \ + "35.0, 35.0, 35.0, 39.6, 47.8", \ + "23.0, 23.0, 23.0, 28.0, 37.0", \ + "-4.5, -4.5, -4.5, 0.8, 10.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("17.3, 17.3, 17.3, 20.8, 27.6", \ + "21.4, 21.4, 21.4, 25.0, 31.9", \ + "29.4, 29.4, 29.4, 33.2, 40.3", \ + "45.4, 45.4, 45.4, 49.1, 56.5", \ + "77.2, 77.2, 77.2, 80.9, 88.2"); + } + cell_fall (inslew_load_5x5__0) { + values ("58.6, 58.6, 58.6, 63.4, 72.3", \ + "71.4, 71.4, 71.4, 76.3, 85.6", \ + "91.5, 91.5, 91.5, 96.6, 106.1", \ + "126.6, 126.6, 126.6, 131.8, 141.8", \ + "193.2, 193.2, 193.2, 198.5, 208.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("31.0, 31.0, 31.0, 34.7, 41.9", \ + "41.4, 41.4, 41.4, 45.2, 52.4", \ + "61.1, 61.1, 61.1, 64.9, 72.3", \ + "99.8, 99.8, 99.8, 103.6, 111.1", \ + "176.4, 176.4, 176.4, 180.2, 187.8"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("44.4, 44.4, 44.4, 48.8, 56.3", \ + "49.8, 49.8, 49.8, 54.3, 62.3", \ + "57.4, 57.4, 57.4, 62.2, 70.8", \ + "69.6, 69.6, 69.6, 74.7, 84.0", \ + "91.9, 91.9, 91.9, 97.1, 107.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("19.2, 19.2, 19.2, 22.9, 29.7", \ + "24.9, 24.9, 24.9, 28.6, 35.6", \ + "36.0, 36.0, 36.0, 39.7, 46.9", \ + "58.2, 58.2, 58.2, 61.8, 69.2", \ + "102.1, 102.1, 102.1, 106.1, 113.3"); + } + cell_fall (inslew_load_5x5__0) { + values ("51.2, 51.2, 51.2, 56.1, 64.9", \ + "55.5, 55.5, 55.5, 60.4, 69.6", \ + "61.1, 61.1, 61.1, 66.1, 75.5", \ + "68.3, 68.3, 68.3, 73.4, 83.3", \ + "79.6, 79.6, 79.6, 84.8, 95.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("30.7, 30.7, 30.7, 34.4, 41.6", \ + "38.6, 38.6, 38.6, 42.4, 49.6", \ + "54.4, 54.4, 54.4, 58.1, 65.5", \ + "85.4, 85.4, 85.4, 89.1, 96.6", \ + "146.9, 146.9, 146.9, 150.7, 158.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("737.6, 737.6, 737.6, 805.4, 941.0", \ + "963.2, 963.2, 963.2, 1031.0, 1166.6", \ + "1409.9, 1409.9, 1409.9, 1477.7, 1613.4", \ + "2300.1, 2300.1, 2300.1, 2367.9, 2503.6", \ + "4077.8, 4077.8, 4077.8, 4145.6, 4281.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("802.1, 802.1, 802.1, 869.9, 1005.5", \ + "947.6, 947.6, 947.6, 1015.4, 1151.0", \ + "1237.6, 1237.6, 1237.6, 1305.4, 1441.1", \ + "1813.4, 1813.4, 1813.4, 1881.2, 2016.8", \ + "2960.0, 2960.0, 2960.0, 3027.8, 3163.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("636.6, 636.6, 636.6, 704.4, 840.0", \ + "795.6, 795.6, 795.6, 863.4, 999.0", \ + "1108.7, 1108.7, 1108.7, 1176.5, 1312.1", \ + "1730.5, 1730.5, 1730.5, 1798.3, 1933.9", \ + "2971.6, 2971.6, 2971.6, 3039.4, 3175.1"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("762.9, 762.9, 762.9, 830.7, 966.3", \ + "942.2, 942.2, 942.2, 1010.0, 1145.6", \ + "1290.8, 1290.8, 1290.8, 1358.6, 1494.2", \ + "1980.9, 1980.9, 1980.9, 2048.7, 2184.3", \ + "3354.0, 3354.0, 3354.0, 3421.8, 3557.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("728.3, 728.3, 728.3, 796.1, 931.8", \ + "877.0, 877.0, 877.0, 944.8, 1080.4", \ + "1172.7, 1172.7, 1172.7, 1240.6, 1376.2", \ + "1762.1, 1762.1, 1762.1, 1829.9, 1965.5", \ + "2938.0, 2938.0, 2938.0, 3005.8, 3141.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("886.4, 886.4, 886.4, 954.2, 1089.8", \ + "1120.6, 1120.6, 1120.6, 1188.4, 1324.0", \ + "1579.8, 1579.8, 1579.8, 1647.6, 1783.2", \ + "2491.2, 2491.2, 2491.2, 2559.0, 2694.6", \ + "4308.1, 4308.1, 4308.1, 4375.9, 4511.6"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("839.4, 839.4, 839.4, 907.2, 1042.8", \ + "1064.0, 1064.0, 1064.0, 1131.8, 1267.5", \ + "1512.0, 1512.0, 1512.0, 1579.8, 1715.5", \ + "2406.5, 2406.5, 2406.5, 2474.4, 2610.0", \ + "4194.3, 4194.3, 4194.3, 4262.1, 4397.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("924.2, 924.2, 924.2, 992.1, 1127.7", \ + "1122.4, 1122.4, 1122.4, 1190.2, 1325.8", \ + "1519.0, 1519.0, 1519.0, 1586.8, 1722.5", \ + "2308.8, 2308.8, 2308.8, 2376.6, 2512.3", \ + "3885.4, 3885.4, 3885.4, 3953.2, 4088.8"); + } + } + } + } + + cell (ao2o22_x4) { + area : 0.0 ; + cell_leakage_power : 0.011 ; + leakage_power () { + when : "(!(i3) & !(i2) & i1 & i0)" ; + value : 0.016 ; + } + leakage_power () { + when : "((i0 | i1) & (i2 | i3))" ; + value : 0.012 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & !(i3))" ; + value : 0.0086 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 0.017 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3))" ; + value : 0.0092 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0014 ; + } + pin (i3) { + direction : input ; + capacitance : 32.72 ; + } + pin (i2) { + direction : input ; + capacitance : 32.38 ; + } + pin (i1) { + direction : input ; + capacitance : 24.30 ; + } + pin (i0) { + direction : input ; + capacitance : 24.03 ; + } + pin (q) { + function : "((i0 | i1) & (i3 | i2))" ; + direction : output ; + capacitance : 8.91 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("68.0, 68.0, 68.0, 71.9, 78.7", \ + "80.2, 80.2, 80.2, 84.1, 91.4", \ + "97.7, 97.7, 97.7, 101.8, 109.4", \ + "124.9, 124.9, 124.9, 129.2, 137.3", \ + "172.9, 172.9, 172.9, 177.1, 185.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("25.0, 25.0, 25.0, 28.1, 34.0", \ + "31.1, 31.1, 31.1, 34.1, 40.1", \ + "42.9, 42.9, 42.9, 46.0, 52.1", \ + "66.2, 66.2, 66.2, 69.2, 75.2", \ + "111.7, 111.7, 111.7, 115.1, 121.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("77.0, 77.0, 77.0, 81.2, 89.0", \ + "80.3, 80.3, 80.3, 84.5, 92.4", \ + "82.6, 82.6, 82.6, 86.9, 94.9", \ + "80.0, 80.0, 80.0, 84.3, 92.5", \ + "66.2, 66.2, 66.2, 70.6, 79.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("45.1, 45.1, 45.1, 48.2, 54.2", \ + "51.6, 51.6, 51.6, 54.7, 60.8", \ + "64.5, 64.5, 64.5, 67.6, 73.8", \ + "90.2, 90.2, 90.2, 93.3, 99.5", \ + "140.6, 140.6, 140.6, 143.7, 150.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("63.2, 63.2, 63.2, 67.0, 73.8", \ + "70.7, 70.7, 70.7, 74.6, 81.7", \ + "77.5, 77.5, 77.5, 81.6, 89.0", \ + "81.3, 81.3, 81.3, 85.6, 93.4", \ + "80.2, 80.2, 80.2, 84.5, 92.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("23.2, 23.2, 23.2, 26.4, 32.2", \ + "28.0, 28.0, 28.0, 31.1, 37.1", \ + "37.2, 37.2, 37.2, 40.3, 46.4", \ + "55.0, 55.0, 55.0, 58.0, 64.1", \ + "89.5, 89.5, 89.5, 92.8, 98.8"); + } + cell_fall (inslew_load_5x5__3) { + values ("86.8, 86.8, 86.8, 91.0, 98.8", \ + "100.0, 100.0, 100.0, 104.2, 112.1", \ + "117.5, 117.5, 117.5, 121.7, 129.9", \ + "141.5, 141.5, 141.5, 145.8, 154.1", \ + "178.8, 178.8, 178.8, 183.1, 191.6"); + } + fall_transition (inslew_load_5x5__3) { + values ("46.1, 46.1, 46.1, 49.3, 55.3", \ + "55.3, 55.3, 55.3, 58.4, 64.5", \ + "72.5, 72.5, 72.5, 75.6, 81.8", \ + "105.5, 105.5, 105.5, 108.6, 114.8", \ + "170.0, 170.0, 170.0, 173.1, 179.3"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("59.5, 59.5, 59.5, 63.4, 70.2", \ + "61.3, 61.3, 61.3, 65.2, 72.2", \ + "59.3, 59.3, 59.3, 63.4, 70.7", \ + "47.7, 47.7, 47.7, 51.9, 59.7", \ + "16.5, 16.5, 16.5, 20.9, 29.2"); + } + rise_transition (inslew_load_5x5__3) { + values ("24.3, 24.3, 24.3, 27.5, 33.3", \ + "28.2, 28.2, 28.2, 31.3, 37.2", \ + "36.0, 36.0, 36.0, 39.1, 45.1", \ + "51.4, 51.4, 51.4, 54.4, 60.5", \ + "81.5, 81.5, 81.5, 84.7, 90.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("93.9, 93.9, 93.9, 98.1, 106.0", \ + "111.3, 111.3, 111.3, 115.5, 123.5", \ + "138.2, 138.2, 138.2, 142.5, 150.7", \ + "182.3, 182.3, 182.3, 186.6, 195.0", \ + "261.8, 261.8, 261.8, 266.2, 274.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("50.3, 50.3, 50.3, 53.5, 59.5", \ + "61.1, 61.1, 61.1, 64.3, 70.4", \ + "82.3, 82.3, 82.3, 85.4, 91.5", \ + "123.2, 123.2, 123.2, 126.3, 132.5", \ + "203.9, 203.9, 203.9, 207.0, 213.2"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("64.6, 64.6, 64.6, 68.4, 75.4", \ + "70.8, 70.8, 70.8, 74.7, 82.0", \ + "78.8, 78.8, 78.8, 83.0, 90.5", \ + "89.4, 89.4, 89.4, 93.7, 101.8", \ + "106.6, 106.6, 106.6, 110.8, 119.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("26.2, 26.2, 26.2, 29.3, 35.2", \ + "31.5, 31.5, 31.5, 34.6, 40.6", \ + "42.1, 42.1, 42.1, 45.1, 51.2", \ + "63.2, 63.2, 63.2, 66.2, 72.2", \ + "105.1, 105.1, 105.1, 108.4, 114.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("83.9, 83.9, 83.9, 88.1, 96.0", \ + "90.8, 90.8, 90.8, 95.0, 103.0", \ + "101.1, 101.1, 101.1, 105.3, 113.5", \ + "115.8, 115.8, 115.8, 120.1, 128.4", \ + "138.9, 138.9, 138.9, 143.3, 151.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("49.0, 49.0, 49.0, 52.1, 58.2", \ + "57.3, 57.3, 57.3, 60.4, 66.5", \ + "73.8, 73.8, 73.8, 76.9, 83.0", \ + "106.8, 106.8, 106.8, 110.0, 116.1", \ + "172.4, 172.4, 172.4, 175.5, 181.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1469.7, 1469.7, 1469.7, 1581.1, 1803.8", \ + "1756.2, 1756.2, 1756.2, 1867.6, 2090.3", \ + "2323.7, 2323.7, 2323.7, 2435.1, 2657.9", \ + "3447.8, 3447.8, 3447.8, 3559.2, 3782.0", \ + "5686.0, 5686.0, 5686.0, 5797.4, 6020.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1897.4, 1897.4, 1897.4, 2008.8, 2231.6", \ + "2122.1, 2122.1, 2122.1, 2233.5, 2456.3", \ + "2569.8, 2569.8, 2569.8, 2681.2, 2904.0", \ + "3461.7, 3461.7, 3461.7, 3573.1, 3795.8", \ + "5229.5, 5229.5, 5229.5, 5340.9, 5563.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1350.1, 1350.1, 1350.1, 1461.5, 1684.3", \ + "1556.3, 1556.3, 1556.3, 1667.7, 1890.5", \ + "1960.7, 1960.7, 1960.7, 2072.1, 2294.9", \ + "2755.6, 2755.6, 2755.6, 2867.0, 3089.8", \ + "4330.0, 4330.0, 4330.0, 4441.4, 4664.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1880.0, 1880.0, 1880.0, 1991.4, 2214.2", \ + "2171.1, 2171.1, 2171.1, 2282.5, 2505.2", \ + "2731.1, 2731.1, 2731.1, 2842.5, 3065.3", \ + "3822.2, 3822.2, 3822.2, 3933.6, 4156.4", \ + "5974.4, 5974.4, 5974.4, 6085.8, 6308.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1453.2, 1453.2, 1453.2, 1564.6, 1787.4", \ + "1637.6, 1637.6, 1637.6, 1749.0, 1971.8", \ + "2007.3, 2007.3, 2007.3, 2118.7, 2341.5", \ + "2740.8, 2740.8, 2740.8, 2852.2, 3075.0", \ + "4197.7, 4197.7, 4197.7, 4309.1, 4531.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("2056.3, 2056.3, 2056.3, 2167.7, 2390.5", \ + "2418.9, 2418.9, 2418.9, 2530.3, 2753.1", \ + "3134.5, 3134.5, 3134.5, 3245.9, 3468.6", \ + "4539.1, 4539.1, 4539.1, 4650.5, 4873.3", \ + "7325.5, 7325.5, 7325.5, 7436.9, 7659.7"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1582.2, 1582.2, 1582.2, 1693.6, 1916.4", \ + "1856.7, 1856.7, 1856.7, 1968.1, 2190.9", \ + "2404.8, 2404.8, 2404.8, 2516.2, 2739.0", \ + "3499.9, 3499.9, 3499.9, 3611.3, 3834.1", \ + "5692.2, 5692.2, 5692.2, 5803.6, 6026.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("2071.2, 2071.2, 2071.2, 2182.6, 2405.4", \ + "2370.4, 2370.4, 2370.4, 2481.7, 2704.5", \ + "2970.4, 2970.4, 2970.4, 3081.8, 3304.5", \ + "4173.0, 4173.0, 4173.0, 4284.4, 4507.2", \ + "6566.9, 6566.9, 6566.9, 6678.3, 6901.0"); + } + } + } + } + + cell (buf_x2) { + area : 0.0 ; + cell_leakage_power : 0.0031 ; + leakage_power () { + when : "i" ; + value : 0.0045 ; + } + leakage_power () { + when : "!(i)" ; + value : 0.0017 ; + } + pin (i) { + direction : input ; + capacitance : 21.43 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 5.42 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("59.5, 59.5, 59.5, 63.9, 71.6", \ + "66.8, 66.8, 66.8, 71.3, 79.3", \ + "73.5, 73.5, 73.5, 78.2, 86.7", \ + "78.0, 78.0, 78.0, 83.0, 92.2", \ + "79.7, 79.7, 79.7, 85.0, 94.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("19.6, 19.6, 19.6, 23.3, 30.2", \ + "24.2, 24.2, 24.2, 27.9, 34.9", \ + "32.9, 32.9, 32.9, 36.6, 43.8", \ + "49.7, 49.7, 49.7, 53.5, 60.8", \ + "82.9, 82.9, 82.9, 86.6, 94.1"); + } + cell_fall (inslew_load_5x5__0) { + values ("70.6, 70.6, 70.6, 75.5, 84.6", \ + "81.3, 81.3, 81.3, 86.2, 95.5", \ + "94.2, 94.2, 94.2, 99.2, 108.7", \ + "109.8, 109.8, 109.8, 114.9, 124.7", \ + "130.8, 130.8, 130.8, 136.1, 146.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("35.0, 35.0, 35.0, 38.7, 45.9", \ + "42.2, 42.2, 42.2, 45.9, 53.2", \ + "55.5, 55.5, 55.5, 59.3, 66.7", \ + "81.1, 81.1, 81.1, 84.9, 92.4", \ + "131.0, 131.0, 131.0, 134.8, 142.3"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__0) { + values ("770.0, 770.0, 770.0, 837.8, 973.5", \ + "891.6, 891.6, 891.6, 959.4, 1095.0", \ + "1131.0, 1131.0, 1131.0, 1198.8, 1334.5", \ + "1603.7, 1603.7, 1603.7, 1671.5, 1807.1", \ + "2543.2, 2543.2, 2543.2, 2611.0, 2746.6"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("946.4, 946.4, 946.4, 1014.2, 1149.8", \ + "1083.3, 1083.3, 1083.3, 1151.2, 1286.8", \ + "1348.1, 1348.1, 1348.1, 1415.9, 1551.5", \ + "1865.6, 1865.6, 1865.6, 1933.4, 2069.0", \ + "2888.0, 2888.0, 2888.0, 2955.8, 3091.4"); + } + } + } + } + + cell (buf_x4) { + area : 0.0 ; + cell_leakage_power : 0.0064 ; + leakage_power () { + when : "i" ; + value : 0.011 ; + } + leakage_power () { + when : "!(i)" ; + value : 0.002 ; + } + pin (i) { + direction : input ; + capacitance : 24.23 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 8.71 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("78.0, 78.0, 78.0, 81.9, 88.8", \ + "90.7, 90.7, 90.7, 94.6, 101.8", \ + "108.0, 108.0, 108.0, 112.2, 119.7", \ + "132.9, 132.9, 132.9, 137.2, 145.3", \ + "175.2, 175.2, 175.2, 179.4, 187.9"); + } + rise_transition (inslew_load_5x5__9) { + values ("24.7, 24.7, 24.7, 27.8, 33.6", \ + "29.9, 29.9, 29.9, 33.0, 39.0", \ + "40.5, 40.5, 40.5, 43.6, 49.7", \ + "61.2, 61.2, 61.2, 64.2, 70.3", \ + "101.9, 101.9, 101.9, 105.2, 111.3"); + } + cell_fall (inslew_load_5x5__9) { + values ("67.8, 67.8, 67.8, 72.0, 79.8", \ + "75.4, 75.4, 75.4, 79.6, 87.6", \ + "81.0, 81.0, 81.0, 85.3, 93.4", \ + "79.7, 79.7, 79.7, 84.0, 92.3", \ + "62.9, 62.9, 62.9, 67.3, 75.9"); + } + fall_transition (inslew_load_5x5__9) { + values ("33.4, 33.4, 33.4, 36.5, 42.7", \ + "39.4, 39.4, 39.4, 42.6, 48.8", \ + "50.3, 50.3, 50.3, 53.5, 59.8", \ + "70.6, 70.6, 70.6, 73.8, 80.1", \ + "109.4, 109.4, 109.4, 112.6, 119.0"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__9) { + values ("1385.4, 1385.4, 1385.4, 1494.3, 1712.0", \ + "1605.6, 1605.6, 1605.6, 1714.5, 1932.2", \ + "2046.4, 2046.4, 2046.4, 2155.3, 2373.1", \ + "2917.4, 2917.4, 2917.4, 3026.3, 3244.1", \ + "4652.2, 4652.2, 4652.2, 4761.1, 4978.8"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("1556.3, 1556.3, 1556.3, 1665.1, 1882.9", \ + "1740.4, 1740.4, 1740.4, 1849.3, 2067.1", \ + "2087.8, 2087.8, 2087.8, 2196.7, 2414.4", \ + "2752.3, 2752.3, 2752.3, 2861.2, 3078.9", \ + "4047.7, 4047.7, 4047.7, 4156.6, 4374.4"); + } + } + } + } + + cell (buf_x8) { + area : 0.0 ; + cell_leakage_power : 0.017 ; + leakage_power () { + when : "i" ; + value : 0.03 ; + } + leakage_power () { + when : "!(i)" ; + value : 0.0045 ; + } + pin (i) { + direction : input ; + capacitance : 26.85 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 17.24 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__10) { + values ("75.1, 75.1, 75.1, 78.7, 85.4", \ + "87.2, 87.2, 87.2, 91.0, 97.9", \ + "103.9, 103.9, 103.9, 107.9, 115.1", \ + "127.6, 127.6, 127.6, 131.8, 139.6", \ + "168.2, 168.2, 168.2, 172.2, 180.4"); + } + rise_transition (inslew_load_5x5__10) { + values ("23.7, 23.7, 23.7, 26.7, 32.4", \ + "29.0, 29.0, 29.0, 32.0, 37.8", \ + "39.6, 39.6, 39.6, 42.6, 48.5", \ + "60.3, 60.3, 60.3, 63.2, 69.1", \ + "101.0, 101.0, 101.0, 104.3, 110.1"); + } + cell_fall (inslew_load_5x5__10) { + values ("66.5, 66.5, 66.5, 70.5, 77.9", \ + "74.0, 74.0, 74.0, 78.0, 85.6", \ + "79.6, 79.6, 79.6, 83.7, 91.3", \ + "78.4, 78.4, 78.4, 82.5, 90.4", \ + "63.0, 63.0, 63.0, 67.1, 75.3"); + } + fall_transition (inslew_load_5x5__10) { + values ("32.5, 32.5, 32.5, 35.5, 41.3", \ + "38.5, 38.5, 38.5, 41.6, 47.4", \ + "49.7, 49.7, 49.7, 52.7, 58.6", \ + "70.3, 70.3, 70.3, 73.3, 79.3", \ + "109.9, 109.9, 109.9, 112.9, 118.9"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__10) { + values ("2609.4, 2609.4, 2609.4, 2824.9, 3256.0", \ + "3041.9, 3041.9, 3041.9, 3257.5, 3688.6", \ + "3905.0, 3905.0, 3905.0, 4120.6, 4551.7", \ + "5610.2, 5610.2, 5610.2, 5825.8, 6256.8", \ + "9004.5, 9004.5, 9004.5, 9220.1, 9651.2"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("2999.7, 2999.7, 2999.7, 3215.2, 3646.3", \ + "3376.6, 3376.6, 3376.6, 3592.2, 4023.3", \ + "4090.3, 4090.3, 4090.3, 4305.9, 4737.0", \ + "5454.6, 5454.6, 5454.6, 5670.1, 6101.2", \ + "8118.4, 8118.4, 8118.4, 8333.9, 8765.0"); + } + } + } + } + + cell (inv_x1) { + area : 0.0 ; + cell_leakage_power : 0.0045 ; + leakage_power () { + when : "!(i)" ; + value : 0.0045 ; + } + pin (i) { + direction : input ; + capacitance : 27.08 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 5.42 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__0) { + values ("1.5, 1.5, 1.5, 5.7, 12.7", \ + "-2.7, -2.7, -2.7, 1.9, 10.2", \ + "-11.6, -11.6, -11.6, -6.6, 2.6", \ + "-29.6, -29.6, -29.6, -24.4, -14.4", \ + "-65.5, -65.5, -65.5, -60.2, -49.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("14.8, 14.8, 14.8, 18.4, 25.2", \ + "26.5, 26.5, 26.5, 30.2, 37.4", \ + "49.6, 49.6, 49.6, 53.5, 60.9", \ + "95.8, 95.8, 95.8, 99.7, 107.4", \ + "188.1, 188.1, 188.1, 192.1, 199.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("12.1, 12.1, 12.1, 16.8, 25.2", \ + "18.2, 18.2, 18.2, 23.2, 32.5", \ + "29.9, 29.9, 29.9, 35.1, 44.9", \ + "53.1, 53.1, 53.1, 58.3, 68.5", \ + "99.2, 99.2, 99.2, 104.4, 114.8"); + } + fall_transition (inslew_load_5x5__0) { + values ("22.2, 22.2, 22.2, 25.9, 33.0", \ + "42.6, 42.6, 42.6, 46.4, 53.7", \ + "82.8, 82.8, 82.8, 86.6, 94.1", \ + "162.9, 162.9, 162.9, 166.7, 174.4", \ + "322.8, 322.8, 322.8, 326.7, 334.4"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__0) { + values ("192.5, 192.5, 192.5, 260.3, 396.0", \ + "317.3, 317.3, 317.3, 385.1, 520.7", \ + "566.7, 566.7, 566.7, 634.5, 770.1", \ + "1065.6, 1065.6, 1065.6, 1133.4, 1269.1", \ + "2063.4, 2063.4, 2063.4, 2131.2, 2266.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("287.9, 287.9, 287.9, 355.7, 491.3", \ + "507.9, 507.9, 507.9, 575.7, 711.3", \ + "948.0, 948.0, 948.0, 1015.8, 1151.4", \ + "1828.2, 1828.2, 1828.2, 1896.0, 2031.6", \ + "3588.5, 3588.5, 3588.5, 3656.3, 3791.9"); + } + } + } + } + + cell (inv_x2) { + area : 0.0 ; + cell_leakage_power : 0.0062 ; + leakage_power () { + when : "!(i)" ; + value : 0.0062 ; + } + pin (i) { + direction : input ; + capacitance : 25.91 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 5.75 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("4.2, 4.2, 4.2, 8.3, 15.3", \ + "3.2, 3.2, 3.2, 7.6, 15.7", \ + "0.8, 0.8, 0.8, 5.5, 14.3", \ + "-3.9, -3.9, -3.9, 0.9, 10.2", \ + "-13.3, -13.3, -13.3, -8.5, 1.0"); + } + rise_transition (inslew_load_5x5__11) { + values ("17.0, 17.0, 17.0, 20.7, 27.8", \ + "31.2, 31.2, 31.2, 35.0, 42.4", \ + "59.4, 59.4, 59.4, 63.3, 70.9", \ + "115.7, 115.7, 115.7, 119.7, 127.4", \ + "228.4, 228.4, 228.4, 232.3, 240.1"); + } + cell_fall (inslew_load_5x5__11) { + values ("8.2, 8.2, 8.2, 12.4, 19.9", \ + "10.5, 10.5, 10.5, 15.1, 23.4", \ + "14.8, 14.8, 14.8, 19.5, 28.5", \ + "23.3, 23.3, 23.3, 28.0, 37.4", \ + "40.0, 40.0, 40.0, 44.8, 54.4"); + } + fall_transition (inslew_load_5x5__11) { + values ("19.6, 19.6, 19.6, 22.8, 28.8", \ + "37.2, 37.2, 37.2, 40.5, 46.8", \ + "72.0, 72.0, 72.0, 75.3, 81.9", \ + "141.4, 141.4, 141.4, 144.8, 151.4", \ + "280.1, 280.1, 280.1, 283.5, 290.3"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__11) { + values ("241.4, 241.4, 241.4, 313.4, 457.2", \ + "410.9, 410.9, 410.9, 482.9, 626.7", \ + "750.0, 750.0, 750.0, 821.9, 965.7", \ + "1428.0, 1428.0, 1428.0, 1499.9, 1643.8", \ + "2784.1, 2784.1, 2784.1, 2856.0, 2999.9"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("295.7, 295.7, 295.7, 367.6, 511.5", \ + "519.5, 519.5, 519.5, 591.4, 735.2", \ + "967.0, 967.0, 967.0, 1038.9, 1182.8", \ + "1862.1, 1862.1, 1862.1, 1934.1, 2077.9", \ + "3652.3, 3652.3, 3652.3, 3724.3, 3868.1"); + } + } + } + } + + cell (inv_x4) { + area : 0.0 ; + cell_leakage_power : 0.012 ; + leakage_power () { + when : "!(i)" ; + value : 0.012 ; + } + pin (i) { + direction : input ; + capacitance : 55.59 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 8.91 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("0.6, 0.6, 0.6, 4.2, 10.4", \ + "-3.6, -3.6, -3.6, 0.3, 7.3", \ + "-12.6, -12.6, -12.6, -8.4, -0.5", \ + "-30.5, -30.5, -30.5, -26.2, -17.9", \ + "-66.4, -66.4, -66.4, -62.0, -53.5"); + } + rise_transition (inslew_load_5x5__3) { + values ("14.2, 14.2, 14.2, 17.2, 22.8", \ + "25.8, 25.8, 25.8, 28.9, 34.9", \ + "48.9, 48.9, 48.9, 52.1, 58.3", \ + "95.1, 95.1, 95.1, 98.3, 104.7", \ + "187.4, 187.4, 187.4, 190.7, 197.1"); + } + cell_fall (inslew_load_5x5__3) { + values ("11.2, 11.2, 11.2, 15.2, 22.3", \ + "17.3, 17.3, 17.3, 21.5, 29.3", \ + "29.0, 29.0, 29.0, 33.3, 41.5", \ + "52.1, 52.1, 52.1, 56.4, 64.9", \ + "98.2, 98.2, 98.2, 102.5, 111.1"); + } + fall_transition (inslew_load_5x5__3) { + values ("21.5, 21.5, 21.5, 24.6, 30.5", \ + "41.9, 41.9, 41.9, 45.0, 51.1", \ + "82.1, 82.1, 82.1, 85.2, 91.5", \ + "162.2, 162.2, 162.2, 165.3, 171.6", \ + "322.1, 322.1, 322.1, 325.3, 331.7"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__3) { + values ("360.8, 360.8, 360.8, 472.2, 695.0", \ + "610.3, 610.3, 610.3, 721.7, 944.5", \ + "1109.2, 1109.2, 1109.2, 1220.6, 1443.4", \ + "2107.0, 2107.0, 2107.0, 2218.4, 2441.2", \ + "4102.6, 4102.6, 4102.6, 4214.0, 4436.8"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("551.5, 551.5, 551.5, 662.9, 885.7", \ + "991.6, 991.6, 991.6, 1103.0, 1325.7", \ + "1871.7, 1871.7, 1871.7, 1983.1, 2205.9", \ + "3632.1, 3632.1, 3632.1, 3743.5, 3966.3", \ + "7152.8, 7152.8, 7152.8, 7264.2, 7487.0"); + } + } + } + } + + cell (inv_x8) { + area : 0.0 ; + cell_leakage_power : 0.03 ; + leakage_power () { + when : "!(i)" ; + value : 0.03 ; + } + pin (i) { + direction : input ; + capacitance : 108.24 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 17.24 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("0.5, 0.5, 0.5, 4.1, 10.0", \ + "-3.7, -3.7, -3.7, 0.1, 7.0", \ + "-12.5, -12.5, -12.5, -8.5, -0.9", \ + "-30.3, -30.3, -30.3, -26.2, -18.1", \ + "-65.8, -65.8, -65.8, -61.6, -53.3"); + } + rise_transition (inslew_load_5x5__10) { + values ("14.1, 14.1, 14.1, 17.0, 22.5", \ + "25.8, 25.8, 25.8, 28.8, 34.5", \ + "48.9, 48.9, 48.9, 52.0, 58.0", \ + "95.3, 95.3, 95.3, 98.3, 104.5", \ + "187.8, 187.8, 187.8, 191.0, 197.2"); + } + cell_fall (inslew_load_5x5__10) { + values ("11.0, 11.0, 11.0, 14.9, 21.9", \ + "17.1, 17.1, 17.1, 21.1, 28.7", \ + "28.7, 28.7, 28.7, 32.8, 40.8", \ + "51.6, 51.6, 51.6, 55.8, 64.0", \ + "97.2, 97.2, 97.2, 101.4, 109.8"); + } + fall_transition (inslew_load_5x5__10) { + values ("21.4, 21.4, 21.4, 24.4, 30.1", \ + "41.7, 41.7, 41.7, 44.8, 50.7", \ + "81.8, 81.8, 81.8, 84.9, 90.9", \ + "161.7, 161.7, 161.7, 164.8, 170.9", \ + "321.4, 321.4, 321.4, 324.5, 330.7"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__10) { + values ("716.8, 716.8, 716.8, 932.3, 1363.4", \ + "1218.0, 1218.0, 1218.0, 1433.5, 1864.6", \ + "2220.4, 2220.4, 2220.4, 2435.9, 2867.0", \ + "4225.2, 4225.2, 4225.2, 4440.8, 4871.9", \ + "8234.9, 8234.9, 8234.9, 8450.5, 8881.6"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("1091.4, 1091.4, 1091.4, 1307.0, 1738.1", \ + "1967.3, 1967.3, 1967.3, 2182.9, 2614.0", \ + "3719.1, 3719.1, 3719.1, 3934.7, 4365.8", \ + "7222.7, 7222.7, 7222.7, 7438.2, 7869.3", \ + "14229.8, 14229.8, 14229.8, 14445.4, 14876.5"); + } + } + } + } + + cell (mx2_x2) { + area : 0.0 ; + cell_leakage_power : 0.0044 ; + leakage_power () { + when : "(!(i1) & i0 & cmd)" ; + value : 0.0038 ; + } + leakage_power () { + when : "(cmd & i1)" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & cmd)" ; + value : 0.002 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 0.0065 ; + } + leakage_power () { + when : "(i1 & !(i0) & !(cmd))" ; + value : 0.0057 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & !(cmd))" ; + value : 0.004 ; + } + pin (i1) { + direction : input ; + capacitance : 21.67 ; + } + pin (i0) { + direction : input ; + capacitance : 23.67 ; + } + pin (cmd) { + direction : input ; + capacitance : 67.50 ; + } + pin (q) { + function : "((i1 & (i0 | cmd)) | (i0 & !(cmd)))" ; + direction : output ; + capacitance : 5.42 ; + timing (maxd_q_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("69.4, 69.4, 69.4, 74.0, 82.1", \ + "79.8, 79.8, 79.8, 84.5, 92.9", \ + "92.9, 92.9, 92.9, 97.9, 106.8", \ + "110.4, 110.4, 110.4, 115.5, 125.0", \ + "137.4, 137.4, 137.4, 142.5, 152.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("25.6, 25.6, 25.6, 29.3, 36.3", \ + "31.1, 31.1, 31.1, 34.8, 42.0", \ + "41.8, 41.8, 41.8, 45.5, 52.9", \ + "62.6, 62.6, 62.6, 66.3, 73.7", \ + "103.3, 103.3, 103.3, 107.4, 114.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("73.9, 73.9, 73.9, 78.8, 88.0", \ + "82.9, 82.9, 82.9, 87.9, 97.2", \ + "91.9, 91.9, 91.9, 96.9, 106.5", \ + "98.7, 98.7, 98.7, 103.9, 113.8", \ + "101.3, 101.3, 101.3, 106.5, 116.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("39.3, 39.3, 39.3, 43.1, 50.3", \ + "46.9, 46.9, 46.9, 50.7, 58.0", \ + "61.1, 61.1, 61.1, 64.9, 72.3", \ + "87.9, 87.9, 87.9, 91.7, 99.1", \ + "139.8, 139.8, 139.8, 143.6, 151.2"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("69.8, 69.8, 69.8, 74.4, 82.6", \ + "78.9, 78.9, 78.9, 83.6, 92.3", \ + "93.6, 93.6, 93.6, 98.7, 107.7", \ + "118.3, 118.3, 118.3, 123.5, 133.3", \ + "165.6, 165.6, 165.6, 170.7, 180.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("28.3, 28.3, 28.3, 32.1, 39.2", \ + "34.6, 34.6, 34.6, 38.3, 45.6", \ + "47.1, 47.1, 47.1, 50.8, 58.2", \ + "72.1, 72.1, 72.1, 75.8, 83.2", \ + "122.1, 122.1, 122.1, 126.2, 133.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("68.6, 68.6, 68.6, 73.5, 82.7", \ + "71.8, 71.8, 71.8, 76.8, 86.2", \ + "74.0, 74.0, 74.0, 79.1, 88.6", \ + "72.1, 72.1, 72.1, 77.3, 87.2", \ + "61.3, 61.3, 61.3, 66.5, 76.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("40.4, 40.4, 40.4, 44.2, 51.4", \ + "47.0, 47.0, 47.0, 50.8, 58.1", \ + "60.3, 60.3, 60.3, 64.1, 71.5", \ + "86.5, 86.5, 86.5, 90.3, 97.8", \ + "138.1, 138.1, 138.1, 141.9, 149.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("69.8, 69.8, 69.8, 74.4, 82.6", \ + "78.9, 78.9, 78.9, 83.6, 92.3", \ + "93.6, 93.6, 93.6, 98.7, 107.7", \ + "118.3, 118.3, 118.3, 123.5, 133.3", \ + "165.6, 165.6, 165.6, 170.7, 180.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("28.3, 28.3, 28.3, 32.1, 39.2", \ + "34.6, 34.6, 34.6, 38.3, 45.6", \ + "47.1, 47.1, 47.1, 50.8, 58.2", \ + "72.1, 72.1, 72.1, 75.8, 83.2", \ + "122.1, 122.1, 122.1, 126.2, 133.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("68.6, 68.6, 68.6, 73.5, 82.7", \ + "71.8, 71.8, 71.8, 76.8, 86.2", \ + "74.0, 74.0, 74.0, 79.1, 88.6", \ + "72.1, 72.1, 72.1, 77.3, 87.2", \ + "61.3, 61.3, 61.3, 66.5, 76.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("40.4, 40.4, 40.4, 44.2, 51.4", \ + "47.0, 47.0, 47.0, 50.8, 58.1", \ + "60.3, 60.3, 60.3, 64.1, 71.5", \ + "86.5, 86.5, 86.5, 90.3, 97.8", \ + "138.1, 138.1, 138.1, 141.9, 149.4"); + } + } + timing (maxd_q_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__0) { + values ("90.0, 90.0, 90.0, 94.5, 102.5", \ + "93.6, 93.6, 93.6, 98.1, 106.2", \ + "93.9, 93.9, 93.9, 98.5, 106.7", \ + "86.3, 86.3, 86.3, 91.1, 99.6", \ + "62.4, 62.4, 62.4, 67.4, 76.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("24.2, 24.2, 24.2, 27.9, 34.9", \ + "25.7, 25.7, 25.7, 29.4, 36.5", \ + "28.4, 28.4, 28.4, 32.1, 39.2", \ + "33.5, 33.5, 33.5, 37.3, 44.5", \ + "43.4, 43.4, 43.4, 47.1, 54.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("114.1, 114.1, 114.1, 119.1, 128.2", \ + "128.4, 128.4, 128.4, 133.4, 142.6", \ + "149.8, 149.8, 149.8, 154.8, 164.2", \ + "183.7, 183.7, 183.7, 188.7, 198.3", \ + "240.8, 240.8, 240.8, 246.0, 255.8"); + } + fall_transition (inslew_load_5x5__0) { + values ("39.0, 39.0, 39.0, 42.8, 50.0", \ + "42.4, 42.4, 42.4, 46.2, 53.5", \ + "48.8, 48.8, 48.8, 52.6, 59.9", \ + "60.7, 60.7, 60.7, 64.5, 71.9", \ + "83.3, 83.3, 83.3, 87.1, 94.6"); + } + } + internal_power (energy_pos_q_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__0) { + values ("787.2, 787.2, 787.2, 855.0, 990.6", \ + "920.3, 920.3, 920.3, 988.1, 1123.7", \ + "1182.8, 1182.8, 1182.8, 1250.6, 1386.2", \ + "1701.3, 1701.3, 1701.3, 1769.1, 1904.7", \ + "2731.7, 2731.7, 2731.7, 2799.5, 2935.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("936.3, 936.3, 936.3, 1004.1, 1139.7", \ + "1067.8, 1067.8, 1067.8, 1135.6, 1271.2", \ + "1319.8, 1319.8, 1319.8, 1387.6, 1523.2", \ + "1807.9, 1807.9, 1807.9, 1875.7, 2011.3", \ + "2768.8, 2768.8, 2768.8, 2836.6, 2972.2"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("905.8, 905.8, 905.8, 973.6, 1109.2", \ + "1085.9, 1085.9, 1085.9, 1153.7, 1289.3", \ + "1445.7, 1445.7, 1445.7, 1513.5, 1649.1", \ + "2165.3, 2165.3, 2165.3, 2233.1, 2368.7", \ + "3607.6, 3607.6, 3607.6, 3675.4, 3811.1"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("1011.3, 1011.3, 1011.3, 1079.1, 1214.7", \ + "1145.1, 1145.1, 1145.1, 1212.9, 1348.5", \ + "1414.8, 1414.8, 1414.8, 1482.6, 1618.2", \ + "1949.8, 1949.8, 1949.8, 2017.6, 2153.3", \ + "3012.0, 3012.0, 3012.0, 3079.8, 3215.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("905.8, 905.8, 905.8, 973.6, 1109.2", \ + "1085.9, 1085.9, 1085.9, 1153.7, 1289.3", \ + "1445.7, 1445.7, 1445.7, 1513.5, 1649.1", \ + "2165.3, 2165.3, 2165.3, 2233.1, 2368.7", \ + "3607.6, 3607.6, 3607.6, 3675.4, 3811.1"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("1011.3, 1011.3, 1011.3, 1079.1, 1214.7", \ + "1145.1, 1145.1, 1145.1, 1212.9, 1348.5", \ + "1414.8, 1414.8, 1414.8, 1482.6, 1618.2", \ + "1949.8, 1949.8, 1949.8, 2017.6, 2153.3", \ + "3012.0, 3012.0, 3012.0, 3079.8, 3215.4"); + } + } + internal_power (energy_neg_q_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__0) { + values ("1107.8, 1107.8, 1107.8, 1175.6, 1311.3", \ + "1206.8, 1206.8, 1206.8, 1274.6, 1410.3", \ + "1398.9, 1398.9, 1398.9, 1466.7, 1602.3", \ + "1778.9, 1778.9, 1778.9, 1846.7, 1982.3", \ + "2532.8, 2532.8, 2532.8, 2600.6, 2736.3"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("1331.4, 1331.4, 1331.4, 1399.3, 1534.9", \ + "1505.9, 1505.9, 1505.9, 1573.7, 1709.3", \ + "1849.2, 1849.2, 1849.2, 1917.0, 2052.6", \ + "2524.7, 2524.7, 2524.7, 2592.5, 2728.1", \ + "3862.9, 3862.9, 3862.9, 3930.7, 4066.3"); + } + } + } + } + + cell (mx2_x4) { + area : 0.0 ; + cell_leakage_power : 0.0067 ; + leakage_power () { + when : "(!(i1) & i0 & cmd)" ; + value : 0.0038 ; + } + leakage_power () { + when : "(cmd & i1)" ; + value : 0.012 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & cmd)" ; + value : 0.002 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 0.013 ; + } + leakage_power () { + when : "(i1 & !(i0) & !(cmd))" ; + value : 0.0057 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & !(cmd))" ; + value : 0.004 ; + } + pin (i1) { + direction : input ; + capacitance : 24.93 ; + } + pin (i0) { + direction : input ; + capacitance : 20.86 ; + } + pin (cmd) { + direction : input ; + capacitance : 61.31 ; + } + pin (q) { + function : "((i0 & (i1 | !(cmd))) | (i1 & cmd))" ; + direction : output ; + capacitance : 8.91 ; + timing (maxd_q_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("101.5, 101.5, 101.5, 105.7, 113.1", \ + "115.3, 115.3, 115.3, 119.5, 127.0", \ + "133.7, 133.7, 133.7, 138.0, 145.8", \ + "157.0, 157.0, 157.0, 161.4, 169.6", \ + "189.9, 189.9, 189.9, 194.1, 202.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("37.5, 37.5, 37.5, 40.6, 46.6", \ + "43.0, 43.0, 43.0, 46.0, 52.1", \ + "54.0, 54.0, 54.0, 57.0, 63.1", \ + "75.3, 75.3, 75.3, 78.4, 84.5", \ + "116.8, 116.8, 116.8, 120.1, 126.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("110.6, 110.6, 110.6, 114.8, 122.8", \ + "123.3, 123.3, 123.3, 127.6, 135.7", \ + "138.8, 138.8, 138.8, 143.1, 151.3", \ + "153.5, 153.5, 153.5, 157.8, 166.1", \ + "164.0, 164.0, 164.0, 168.3, 176.8"); + } + fall_transition (inslew_load_5x5__3) { + values ("60.1, 60.1, 60.1, 63.2, 69.3", \ + "67.8, 67.8, 67.8, 70.9, 77.0", \ + "82.7, 82.7, 82.7, 85.9, 92.0", \ + "110.6, 110.6, 110.6, 113.8, 119.9", \ + "163.9, 163.9, 163.9, 167.0, 173.3"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("100.7, 100.7, 100.7, 104.8, 112.3", \ + "111.2, 111.2, 111.2, 115.4, 123.1", \ + "128.3, 128.3, 128.3, 132.6, 140.5", \ + "156.2, 156.2, 156.2, 160.5, 168.8", \ + "206.5, 206.5, 206.5, 210.7, 219.1"); + } + rise_transition (inslew_load_5x5__3) { + values ("40.3, 40.3, 40.3, 43.4, 49.5", \ + "46.4, 46.4, 46.4, 49.5, 55.6", \ + "59.1, 59.1, 59.1, 62.1, 68.1", \ + "84.1, 84.1, 84.1, 87.4, 93.3", \ + "134.8, 134.8, 134.8, 138.1, 144.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("102.9, 102.9, 102.9, 107.1, 115.1", \ + "107.4, 107.4, 107.4, 111.6, 119.7", \ + "112.9, 112.9, 112.9, 117.2, 125.3", \ + "115.5, 115.5, 115.5, 119.8, 128.1", \ + "109.2, 109.2, 109.2, 113.5, 122.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("60.4, 60.4, 60.4, 63.6, 69.7", \ + "66.7, 66.7, 66.7, 69.8, 75.9", \ + "80.0, 80.0, 80.0, 83.1, 89.3", \ + "106.6, 106.6, 106.6, 109.7, 115.9", \ + "158.9, 158.9, 158.9, 162.0, 168.2"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("100.7, 100.7, 100.7, 104.8, 112.3", \ + "111.2, 111.2, 111.2, 115.4, 123.1", \ + "128.3, 128.3, 128.3, 132.6, 140.5", \ + "156.2, 156.2, 156.2, 160.5, 168.8", \ + "206.5, 206.5, 206.5, 210.7, 219.1"); + } + rise_transition (inslew_load_5x5__3) { + values ("40.3, 40.3, 40.3, 43.4, 49.5", \ + "46.4, 46.4, 46.4, 49.5, 55.6", \ + "59.1, 59.1, 59.1, 62.1, 68.1", \ + "84.1, 84.1, 84.1, 87.4, 93.3", \ + "134.8, 134.8, 134.8, 138.1, 144.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("102.9, 102.9, 102.9, 107.1, 115.1", \ + "107.4, 107.4, 107.4, 111.6, 119.7", \ + "112.9, 112.9, 112.9, 117.2, 125.3", \ + "115.5, 115.5, 115.5, 119.8, 128.1", \ + "109.2, 109.2, 109.2, 113.5, 122.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("60.4, 60.4, 60.4, 63.6, 69.7", \ + "66.7, 66.7, 66.7, 69.8, 75.9", \ + "80.0, 80.0, 80.0, 83.1, 89.3", \ + "106.6, 106.6, 106.6, 109.7, 115.9", \ + "158.9, 158.9, 158.9, 162.0, 168.2"); + } + } + timing (maxd_q_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("118.6, 118.6, 118.6, 122.7, 130.0", \ + "122.4, 122.4, 122.4, 126.5, 133.9", \ + "123.9, 123.9, 123.9, 128.1, 135.5", \ + "119.1, 119.1, 119.1, 123.3, 130.9", \ + "99.5, 99.5, 99.5, 103.8, 111.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("36.0, 36.0, 36.0, 39.1, 45.1", \ + "37.4, 37.4, 37.4, 40.4, 46.5", \ + "40.0, 40.0, 40.0, 43.0, 49.1", \ + "45.1, 45.1, 45.1, 48.2, 54.3", \ + "55.3, 55.3, 55.3, 58.3, 64.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("146.9, 146.9, 146.9, 151.1, 159.1", \ + "162.5, 162.5, 162.5, 166.7, 174.7", \ + "187.0, 187.0, 187.0, 191.3, 199.4", \ + "226.2, 226.2, 226.2, 230.4, 238.6", \ + "290.4, 290.4, 290.4, 294.7, 303.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("59.4, 59.4, 59.4, 62.5, 68.6", \ + "62.7, 62.7, 62.7, 65.9, 72.0", \ + "69.4, 69.4, 69.4, 72.5, 78.6", \ + "81.9, 81.9, 81.9, 85.0, 91.2", \ + "105.5, 105.5, 105.5, 108.6, 114.8"); + } + } + internal_power (energy_pos_q_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1598.7, 1598.7, 1598.7, 1710.1, 1932.9", \ + "1784.9, 1784.9, 1784.9, 1896.3, 2119.1", \ + "2158.9, 2158.9, 2158.9, 2270.3, 2493.1", \ + "2895.9, 2895.9, 2895.9, 3007.3, 3230.1", \ + "4349.0, 4349.0, 4349.0, 4460.4, 4683.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("2122.4, 2122.4, 2122.4, 2233.8, 2456.6", \ + "2335.3, 2335.3, 2335.3, 2446.7, 2669.5", \ + "2753.2, 2753.2, 2753.2, 2864.6, 3087.4", \ + "3547.7, 3547.7, 3547.7, 3659.1, 3881.9", \ + "5083.8, 5083.8, 5083.8, 5195.2, 5418.0"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1746.2, 1746.2, 1746.2, 1857.6, 2080.4", \ + "1984.0, 1984.0, 1984.0, 2095.4, 2318.2", \ + "2470.0, 2470.0, 2470.0, 2581.4, 2804.2", \ + "3441.0, 3441.0, 3441.0, 3552.4, 3775.2", \ + "5395.5, 5395.5, 5395.5, 5506.9, 5729.7"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("2192.6, 2192.6, 2192.6, 2304.0, 2526.8", \ + "2388.8, 2388.8, 2388.8, 2500.2, 2723.0", \ + "2798.1, 2798.1, 2798.1, 2909.5, 3132.3", \ + "3618.3, 3618.3, 3618.3, 3729.7, 3952.5", \ + "5239.4, 5239.4, 5239.4, 5350.8, 5573.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1746.2, 1746.2, 1746.2, 1857.6, 2080.4", \ + "1984.0, 1984.0, 1984.0, 2095.4, 2318.2", \ + "2470.0, 2470.0, 2470.0, 2581.4, 2804.2", \ + "3441.0, 3441.0, 3441.0, 3552.4, 3775.2", \ + "5395.5, 5395.5, 5395.5, 5506.9, 5729.7"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("2192.6, 2192.6, 2192.6, 2304.0, 2526.8", \ + "2388.8, 2388.8, 2388.8, 2500.2, 2723.0", \ + "2798.1, 2798.1, 2798.1, 2909.5, 3132.3", \ + "3618.3, 3618.3, 3618.3, 3729.7, 3952.5", \ + "5239.4, 5239.4, 5239.4, 5350.8, 5573.5"); + } + } + internal_power (energy_neg_q_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1871.9, 1871.9, 1871.9, 1983.3, 2206.1", \ + "1981.8, 1981.8, 1981.8, 2093.2, 2316.0", \ + "2199.1, 2199.1, 2199.1, 2310.5, 2533.3", \ + "2629.5, 2629.5, 2629.5, 2740.9, 2963.7", \ + "3487.5, 3487.5, 3487.5, 3598.9, 3821.6"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("2474.9, 2474.9, 2474.9, 2586.3, 2809.1", \ + "2683.7, 2683.7, 2683.7, 2795.1, 3017.9", \ + "3099.0, 3099.0, 3099.0, 3210.4, 3433.2", \ + "3913.5, 3913.5, 3913.5, 4024.9, 4247.7", \ + "5511.7, 5511.7, 5511.7, 5623.1, 5845.9"); + } + } + } + } + + cell (mx3_x2) { + area : 0.0 ; + cell_leakage_power : 0.0064 ; + leakage_power () { + when : "(i2 & !(i1) & i0 & cmd1 & cmd0)" ; + value : 0.0071 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0 & cmd1 & cmd0)" ; + value : 0.0049 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & i1)" ; + value : 0.0076 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0) & cmd1 & cmd0)" ; + value : 0.005 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & cmd1 & cmd0)" ; + value : 0.0028 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0 & !(cmd1) & cmd0)" ; + value : 0.0086 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & !(cmd1) & cmd0)" ; + value : 0.0042 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & i2) | (!(cmd0) & cmd1 & i0))" ; + value : 0.0091 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i0) & i1 & !(i2)) | (!(cmd0) & cmd1 & !(i0) & i1 & i2))" ; + value : 0.0065 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & i0 & !(i1) & !(i2)) | (!(cmd0) & cmd1 & !(i0) & i1 & !(i2)))" ; + value : 0.0063 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0) & cmd1 & !(cmd0))" ; + value : 0.0044 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & cmd1 & !(cmd0))" ; + value : 0.0043 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0)" ; + value : 0.011 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.0079 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.0058 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.0078 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.0057 ; + } + pin (i2) { + direction : input ; + capacitance : 27.63 ; + } + pin (i1) { + direction : input ; + capacitance : 27.50 ; + } + pin (i0) { + direction : input ; + capacitance : 25.77 ; + } + pin (cmd1) { + direction : input ; + capacitance : 52.45 ; + } + pin (cmd0) { + direction : input ; + capacitance : 51.99 ; + } + pin (q) { + function : "((i0 & ((i1 & (!(cmd0) | i2 | cmd1)) | !(cmd0) | (i2 & !(cmd1)))) | (i1 & cmd0 & (i2 | cmd1)) | (cmd0 & i2 & !(cmd1)))" ; + direction : output ; + capacitance : 6.02 ; + timing (maxd_q_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("84.8, 84.8, 84.8, 89.2, 97.6", \ + "93.1, 93.1, 93.1, 97.5, 106.0", \ + "107.5, 107.5, 107.5, 112.0, 120.5", \ + "133.2, 133.2, 133.2, 137.8, 146.5", \ + "182.7, 182.7, 182.7, 187.4, 196.4"); + } + rise_transition (inslew_load_5x5__12) { + values ("45.3, 45.3, 45.3, 49.1, 56.7", \ + "54.2, 54.2, 54.2, 58.1, 65.7", \ + "72.3, 72.3, 72.3, 76.2, 83.9", \ + "108.3, 108.3, 108.3, 112.2, 120.0", \ + "181.3, 181.3, 181.3, 185.3, 193.0"); + } + cell_fall (inslew_load_5x5__12) { + values ("63.2, 63.2, 63.2, 67.5, 75.4", \ + "67.1, 67.1, 67.1, 71.4, 79.6", \ + "71.7, 71.7, 71.7, 76.1, 84.4", \ + "75.4, 75.4, 75.4, 79.9, 88.4", \ + "77.6, 77.6, 77.6, 82.1, 90.9"); + } + fall_transition (inslew_load_5x5__12) { + values ("35.9, 35.9, 35.9, 39.0, 44.7", \ + "42.5, 42.5, 42.5, 45.6, 51.3", \ + "55.5, 55.5, 55.5, 58.5, 64.5", \ + "81.5, 81.5, 81.5, 84.5, 90.6", \ + "133.0, 133.0, 133.0, 136.1, 142.1"); + } + } + timing (maxd_q_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("78.1, 78.1, 78.1, 82.5, 90.6", \ + "87.9, 87.9, 87.9, 92.4, 100.6", \ + "98.7, 98.7, 98.7, 103.2, 111.7", \ + "109.2, 109.2, 109.2, 113.7, 122.2", \ + "119.0, 119.0, 119.0, 123.6, 132.5"); + } + rise_transition (inslew_load_5x5__12) { + values ("36.8, 36.8, 36.8, 40.7, 48.2", \ + "43.6, 43.6, 43.6, 47.4, 54.9", \ + "56.4, 56.4, 56.4, 60.3, 67.9", \ + "81.0, 81.0, 81.0, 84.9, 92.7", \ + "129.2, 129.2, 129.2, 133.1, 140.8"); + } + cell_fall (inslew_load_5x5__12) { + values ("82.6, 82.6, 82.6, 86.9, 95.1", \ + "95.2, 95.2, 95.2, 99.6, 107.8", \ + "111.3, 111.3, 111.3, 115.7, 124.1", \ + "131.7, 131.7, 131.7, 136.2, 144.8", \ + "161.4, 161.4, 161.4, 166.0, 174.9"); + } + fall_transition (inslew_load_5x5__12) { + values ("44.4, 44.4, 44.4, 47.4, 53.2", \ + "52.5, 52.5, 52.5, 55.5, 61.4", \ + "67.9, 67.9, 67.9, 71.0, 77.0", \ + "97.5, 97.5, 97.5, 100.5, 106.6", \ + "155.3, 155.3, 155.3, 158.4, 164.4"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("64.5, 64.5, 64.5, 68.9, 76.4", \ + "73.2, 73.2, 73.2, 77.6, 85.6", \ + "83.1, 83.1, 83.1, 87.5, 95.8", \ + "94.4, 94.4, 94.4, 98.8, 107.4", \ + "109.5, 109.5, 109.5, 114.1, 122.9"); + } + rise_transition (inslew_load_5x5__12) { + values ("27.6, 27.6, 27.6, 31.4, 38.8", \ + "34.1, 34.1, 34.1, 38.0, 45.5", \ + "46.6, 46.6, 46.6, 50.5, 58.0", \ + "70.7, 70.7, 70.7, 74.6, 82.3", \ + "118.0, 118.0, 118.0, 121.9, 129.6"); + } + cell_fall (inslew_load_5x5__12) { + values ("63.8, 63.8, 63.8, 68.1, 75.9", \ + "72.9, 72.9, 72.9, 77.2, 85.3", \ + "83.3, 83.3, 83.3, 87.7, 96.0", \ + "95.3, 95.3, 95.3, 99.7, 108.2", \ + "111.1, 111.1, 111.1, 115.6, 124.4"); + } + fall_transition (inslew_load_5x5__12) { + values ("32.3, 32.3, 32.3, 35.3, 41.0", \ + "39.5, 39.5, 39.5, 42.5, 48.2", \ + "52.9, 52.9, 52.9, 55.9, 61.8", \ + "78.7, 78.7, 78.7, 81.8, 87.8", \ + "129.4, 129.4, 129.4, 132.5, 138.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("79.4, 79.4, 79.4, 83.9, 92.0", \ + "87.0, 87.0, 87.0, 91.4, 99.8", \ + "97.1, 97.1, 97.1, 101.6, 110.1", \ + "110.4, 110.4, 110.4, 114.9, 123.6", \ + "129.8, 129.8, 129.8, 134.4, 143.3"); + } + rise_transition (inslew_load_5x5__12) { + values ("40.1, 40.1, 40.1, 44.0, 51.5", \ + "47.3, 47.3, 47.3, 51.2, 58.7", \ + "61.1, 61.1, 61.1, 65.0, 72.7", \ + "88.7, 88.7, 88.7, 92.6, 100.3", \ + "143.3, 143.3, 143.3, 147.2, 154.9"); + } + cell_fall (inslew_load_5x5__12) { + values ("82.1, 82.1, 82.1, 86.4, 94.7", \ + "89.1, 89.1, 89.1, 93.5, 101.8", \ + "99.1, 99.1, 99.1, 103.6, 112.0", \ + "113.0, 113.0, 113.0, 117.5, 126.2", \ + "133.5, 133.5, 133.5, 138.1, 147.0"); + } + fall_transition (inslew_load_5x5__12) { + values ("47.2, 47.2, 47.2, 50.3, 56.1", \ + "54.6, 54.6, 54.6, 57.7, 63.6", \ + "69.4, 69.4, 69.4, 72.4, 78.4", \ + "99.1, 99.1, 99.1, 102.1, 108.1", \ + "157.7, 157.7, 157.7, 160.8, 166.9"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("79.4, 79.4, 79.4, 83.9, 92.0", \ + "87.0, 87.0, 87.0, 91.4, 99.8", \ + "97.1, 97.1, 97.1, 101.6, 110.1", \ + "110.4, 110.4, 110.4, 114.9, 123.6", \ + "129.8, 129.8, 129.8, 134.4, 143.3"); + } + rise_transition (inslew_load_5x5__12) { + values ("40.1, 40.1, 40.1, 44.0, 51.5", \ + "47.3, 47.3, 47.3, 51.2, 58.7", \ + "61.1, 61.1, 61.1, 65.0, 72.7", \ + "88.7, 88.7, 88.7, 92.6, 100.3", \ + "143.3, 143.3, 143.3, 147.2, 154.9"); + } + cell_fall (inslew_load_5x5__12) { + values ("82.1, 82.1, 82.1, 86.4, 94.7", \ + "89.1, 89.1, 89.1, 93.5, 101.8", \ + "99.1, 99.1, 99.1, 103.6, 112.0", \ + "113.0, 113.0, 113.0, 117.5, 126.2", \ + "133.5, 133.5, 133.5, 138.1, 147.0"); + } + fall_transition (inslew_load_5x5__12) { + values ("47.2, 47.2, 47.2, 50.3, 56.1", \ + "54.6, 54.6, 54.6, 57.7, 63.6", \ + "69.4, 69.4, 69.4, 72.4, 78.4", \ + "99.1, 99.1, 99.1, 102.1, 108.1", \ + "157.7, 157.7, 157.7, 160.8, 166.9"); + } + } + timing (maxd_q_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("117.9, 117.9, 117.9, 122.3, 130.3", \ + "125.4, 125.4, 125.4, 129.8, 137.9", \ + "131.8, 131.8, 131.8, 136.3, 144.5", \ + "133.4, 133.4, 133.4, 137.8, 146.2", \ + "124.7, 124.7, 124.7, 129.2, 137.7"); + } + rise_transition (inslew_load_5x5__12) { + values ("34.9, 34.9, 34.9, 38.7, 46.2", \ + "37.0, 37.0, 37.0, 40.9, 48.3", \ + "40.9, 40.9, 40.9, 44.8, 52.3", \ + "48.5, 48.5, 48.5, 52.4, 59.9", \ + "63.0, 63.0, 63.0, 66.9, 74.6"); + } + cell_fall (inslew_load_5x5__12) { + values ("149.9, 149.9, 149.9, 154.3, 162.6", \ + "162.9, 162.9, 162.9, 167.3, 175.6", \ + "181.4, 181.4, 181.4, 185.8, 194.1", \ + "208.9, 208.9, 208.9, 213.4, 221.8", \ + "257.1, 257.1, 257.1, 261.6, 270.3"); + } + fall_transition (inslew_load_5x5__12) { + values ("55.0, 55.0, 55.0, 58.1, 64.0", \ + "58.3, 58.3, 58.3, 61.3, 67.3", \ + "64.7, 64.7, 64.7, 67.7, 73.7", \ + "77.4, 77.4, 77.4, 80.5, 86.5", \ + "103.2, 103.2, 103.2, 106.2, 112.2"); + } + } + timing (maxd_q_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("107.7, 107.7, 107.7, 112.2, 120.2", \ + "113.4, 113.4, 113.4, 117.9, 126.0", \ + "117.0, 117.0, 117.0, 121.5, 129.7", \ + "115.3, 115.3, 115.3, 119.7, 128.1", \ + "100.9, 100.9, 100.9, 105.3, 113.8"); + } + rise_transition (inslew_load_5x5__12) { + values ("36.3, 36.3, 36.3, 40.2, 47.7", \ + "38.3, 38.3, 38.3, 42.1, 49.6", \ + "41.8, 41.8, 41.8, 45.7, 53.2", \ + "48.6, 48.6, 48.6, 52.5, 60.1", \ + "61.4, 61.4, 61.4, 65.3, 73.0"); + } + cell_fall (inslew_load_5x5__12) { + values ("128.2, 128.2, 128.2, 132.5, 140.7", \ + "142.7, 142.7, 142.7, 147.1, 155.3", \ + "164.5, 164.5, 164.5, 168.9, 177.2", \ + "197.8, 197.8, 197.8, 202.3, 210.6", \ + "254.7, 254.7, 254.7, 259.1, 267.7"); + } + fall_transition (inslew_load_5x5__12) { + values ("44.8, 44.8, 44.8, 47.8, 53.6", \ + "48.1, 48.1, 48.1, 51.2, 57.0", \ + "54.7, 54.7, 54.7, 57.8, 63.7", \ + "67.0, 67.0, 67.0, 70.0, 76.0", \ + "90.5, 90.5, 90.5, 93.6, 99.6"); + } + } + internal_power (energy_pos_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__12) { + values ("1198.7, 1198.7, 1198.7, 1274.0, 1424.6", \ + "1420.0, 1420.0, 1420.0, 1495.3, 1645.9", \ + "1866.2, 1866.2, 1866.2, 1941.5, 2092.2", \ + "2756.7, 2756.7, 2756.7, 2832.0, 2982.6", \ + "4548.7, 4548.7, 4548.7, 4624.0, 4774.6"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("1096.1, 1096.1, 1096.1, 1171.4, 1322.0", \ + "1266.9, 1266.9, 1266.9, 1342.2, 1492.8", \ + "1605.8, 1605.8, 1605.8, 1681.1, 1831.7", \ + "2284.9, 2284.9, 2284.9, 2360.2, 2510.8", \ + "3637.7, 3637.7, 3637.7, 3713.0, 3863.6"); + } + } + internal_power (energy_pos_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__12) { + values ("941.5, 941.5, 941.5, 1016.8, 1167.4", \ + "1077.6, 1077.6, 1077.6, 1152.9, 1303.5", \ + "1343.2, 1343.2, 1343.2, 1418.5, 1569.1", \ + "1860.9, 1860.9, 1860.9, 1936.2, 2086.9", \ + "2883.5, 2883.5, 2883.5, 2958.8, 3109.4"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("1089.7, 1089.7, 1089.7, 1165.0, 1315.6", \ + "1251.7, 1251.7, 1251.7, 1327.0, 1477.6", \ + "1565.3, 1565.3, 1565.3, 1640.6, 1791.2", \ + "2174.4, 2174.4, 2174.4, 2249.7, 2400.4", \ + "3375.7, 3375.7, 3375.7, 3451.0, 3601.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__12) { + values ("848.6, 848.6, 848.6, 923.9, 1074.6", \ + "1001.6, 1001.6, 1001.6, 1076.9, 1227.5", \ + "1300.2, 1300.2, 1300.2, 1375.6, 1526.2", \ + "1886.9, 1886.9, 1886.9, 1962.2, 2112.9", \ + "3051.0, 3051.0, 3051.0, 3126.3, 3276.9"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("939.0, 939.0, 939.0, 1014.3, 1164.9", \ + "1099.5, 1099.5, 1099.5, 1174.8, 1325.4", \ + "1408.5, 1408.5, 1408.5, 1483.8, 1634.4", \ + "2014.2, 2014.2, 2014.2, 2089.6, 2240.2", \ + "3212.8, 3212.8, 3212.8, 3288.1, 3438.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__12) { + values ("1051.4, 1051.4, 1051.4, 1126.7, 1277.3", \ + "1211.7, 1211.7, 1211.7, 1287.0, 1437.6", \ + "1527.4, 1527.4, 1527.4, 1602.7, 1753.3", \ + "2156.8, 2156.8, 2156.8, 2232.1, 2382.7", \ + "3409.5, 3409.5, 3409.5, 3484.8, 3635.4"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("1193.9, 1193.9, 1193.9, 1269.2, 1419.8", \ + "1357.6, 1357.6, 1357.6, 1432.9, 1583.5", \ + "1685.0, 1685.0, 1685.0, 1760.3, 1910.9", \ + "2342.5, 2342.5, 2342.5, 2417.8, 2568.4", \ + "3648.9, 3648.9, 3648.9, 3724.3, 3874.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__12) { + values ("1051.4, 1051.4, 1051.4, 1126.7, 1277.3", \ + "1211.7, 1211.7, 1211.7, 1287.0, 1437.6", \ + "1527.4, 1527.4, 1527.4, 1602.7, 1753.3", \ + "2156.8, 2156.8, 2156.8, 2232.1, 2382.7", \ + "3409.5, 3409.5, 3409.5, 3484.8, 3635.4"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("1193.9, 1193.9, 1193.9, 1269.2, 1419.8", \ + "1357.6, 1357.6, 1357.6, 1432.9, 1583.5", \ + "1685.0, 1685.0, 1685.0, 1760.3, 1910.9", \ + "2342.5, 2342.5, 2342.5, 2417.8, 2568.4", \ + "3648.9, 3648.9, 3648.9, 3724.3, 3874.9"); + } + } + internal_power (energy_neg_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__12) { + values ("1596.6, 1596.6, 1596.6, 1671.9, 1822.5", \ + "1708.4, 1708.4, 1708.4, 1783.7, 1934.3", \ + "1922.3, 1922.3, 1922.3, 1997.6, 2148.2", \ + "2340.1, 2340.1, 2340.1, 2415.4, 2566.0", \ + "3163.2, 3163.2, 3163.2, 3238.5, 3389.2"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("1918.8, 1918.8, 1918.8, 1994.1, 2144.7", \ + "2081.2, 2081.2, 2081.2, 2156.5, 2307.1", \ + "2403.7, 2403.7, 2403.7, 2479.0, 2629.6", \ + "3044.6, 3044.6, 3044.6, 3119.9, 3270.5", \ + "4326.2, 4326.2, 4326.2, 4401.5, 4552.2"); + } + } + internal_power (energy_neg_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__12) { + values ("1253.6, 1253.6, 1253.6, 1328.9, 1479.5", \ + "1344.5, 1344.5, 1344.5, 1419.8, 1570.4", \ + "1521.5, 1521.5, 1521.5, 1596.8, 1747.4", \ + "1869.1, 1869.1, 1869.1, 1944.4, 2095.0", \ + "2552.4, 2552.4, 2552.4, 2627.7, 2778.3"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("1451.6, 1451.6, 1451.6, 1526.9, 1677.5", \ + "1602.6, 1602.6, 1602.6, 1677.9, 1828.5", \ + "1903.0, 1903.0, 1903.0, 1978.3, 2128.9", \ + "2489.2, 2489.2, 2489.2, 2564.5, 2715.1", \ + "3648.6, 3648.6, 3648.6, 3723.9, 3874.5"); + } + } + } + } + + cell (mx3_x4) { + area : 0.0 ; + cell_leakage_power : 0.0073 ; + leakage_power () { + when : "(i2 & !(i1) & i0 & cmd1 & cmd0)" ; + value : 0.0071 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0 & cmd1 & cmd0)" ; + value : 0.0049 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & i1)" ; + value : 0.012 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0) & cmd1 & cmd0)" ; + value : 0.005 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & cmd1 & cmd0)" ; + value : 0.0028 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0 & !(cmd1) & cmd0)" ; + value : 0.0086 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0 & !(cmd1) & cmd0)" ; + value : 0.0063 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0) & !(cmd1) & cmd0)" ; + value : 0.0065 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & !(cmd1) & cmd0)" ; + value : 0.0042 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & i2) | (!(cmd0) & cmd1 & i0))" ; + value : 0.014 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0) & cmd1 & !(cmd0))" ; + value : 0.0067 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0) & cmd1 & !(cmd0))" ; + value : 0.0066 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0) & cmd1 & !(cmd0))" ; + value : 0.0046 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & cmd1 & !(cmd0))" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0)" ; + value : 0.016 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.0081 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.0061 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.008 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.006 ; + } + pin (i2) { + direction : input ; + capacitance : 36.38 ; + } + pin (i1) { + direction : input ; + capacitance : 35.73 ; + } + pin (i0) { + direction : input ; + capacitance : 27.36 ; + } + pin (cmd1) { + direction : input ; + capacitance : 56.76 ; + } + pin (cmd0) { + direction : input ; + capacitance : 55.66 ; + } + pin (q) { + function : "((i2 & (((i1 | !(cmd1)) & (cmd0 | i0)) | (!(cmd0) & i0))) | (i1 & cmd1 & (cmd0 | i0)) | (!(cmd0) & i0))" ; + direction : output ; + capacitance : 9.33 ; + timing (maxd_q_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__13) { + values ("102.4, 102.4, 102.4, 106.7, 114.4", \ + "108.9, 108.9, 108.9, 113.2, 121.0", \ + "119.5, 119.5, 119.5, 123.8, 131.9", \ + "136.8, 136.8, 136.8, 141.2, 149.6", \ + "167.3, 167.3, 167.3, 171.7, 180.4"); + } + rise_transition (inslew_load_5x5__13) { + values ("49.2, 49.2, 49.2, 52.4, 58.7", \ + "56.0, 56.0, 56.0, 59.1, 65.5", \ + "69.9, 69.9, 69.9, 73.1, 79.4", \ + "98.3, 98.3, 98.3, 101.3, 107.6", \ + "155.5, 155.5, 155.5, 158.7, 165.0"); + } + cell_fall (inslew_load_5x5__13) { + values ("104.7, 104.7, 104.7, 109.0, 117.1", \ + "111.6, 111.6, 111.6, 115.9, 124.1", \ + "122.5, 122.5, 122.5, 126.8, 135.1", \ + "137.1, 137.1, 137.1, 141.5, 149.9", \ + "157.7, 157.7, 157.7, 162.0, 170.6"); + } + fall_transition (inslew_load_5x5__13) { + values ("61.2, 61.2, 61.2, 64.3, 70.4", \ + "68.7, 68.7, 68.7, 71.8, 77.9", \ + "84.4, 84.4, 84.4, 87.5, 93.6", \ + "116.2, 116.2, 116.2, 119.2, 125.4", \ + "179.0, 179.0, 179.0, 182.1, 188.2"); + } + } + timing (maxd_q_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__13) { + values ("99.6, 99.6, 99.6, 103.6, 111.3", \ + "110.8, 110.8, 110.8, 115.0, 122.7", \ + "123.4, 123.4, 123.4, 127.7, 135.6", \ + "133.3, 133.3, 133.3, 137.7, 145.9", \ + "135.9, 135.9, 135.9, 140.4, 148.9"); + } + rise_transition (inslew_load_5x5__13) { + values ("42.7, 42.7, 42.7, 45.9, 52.2", \ + "47.9, 47.9, 47.9, 51.1, 57.4", \ + "58.3, 58.3, 58.3, 61.4, 67.8", \ + "78.1, 78.1, 78.1, 81.2, 87.5", \ + "116.3, 116.3, 116.3, 119.4, 125.7"); + } + cell_fall (inslew_load_5x5__13) { + values ("142.7, 142.7, 142.7, 147.0, 155.3", \ + "160.8, 160.8, 160.8, 165.1, 173.4", \ + "187.2, 187.2, 187.2, 191.6, 200.0", \ + "224.2, 224.2, 224.2, 228.6, 237.1", \ + "278.5, 278.5, 278.5, 282.9, 291.4"); + } + fall_transition (inslew_load_5x5__13) { + values ("81.7, 81.7, 81.7, 84.8, 91.0", \ + "91.4, 91.4, 91.4, 94.5, 100.6", \ + "110.7, 110.7, 110.7, 113.7, 119.9", \ + "147.4, 147.4, 147.4, 150.5, 156.6", \ + "218.3, 218.3, 218.3, 221.5, 227.6"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__13) { + values ("82.4, 82.4, 82.4, 86.4, 93.6", \ + "92.5, 92.5, 92.5, 96.5, 104.0", \ + "103.4, 103.4, 103.4, 107.6, 115.3", \ + "112.9, 112.9, 112.9, 117.2, 125.2", \ + "118.8, 118.8, 118.8, 123.3, 131.7"); + } + rise_transition (inslew_load_5x5__13) { + values ("31.1, 31.1, 31.1, 34.4, 40.5", \ + "36.2, 36.2, 36.2, 39.4, 45.6", \ + "46.2, 46.2, 46.2, 49.4, 55.7", \ + "65.4, 65.4, 65.4, 68.6, 74.9", \ + "103.0, 103.0, 103.0, 106.0, 112.3"); + } + cell_fall (inslew_load_5x5__13) { + values ("106.6, 106.6, 106.6, 110.8, 118.9", \ + "121.2, 121.2, 121.2, 125.4, 133.6", \ + "140.9, 140.9, 140.9, 145.2, 153.5", \ + "166.5, 166.5, 166.5, 170.9, 179.3", \ + "202.9, 202.9, 202.9, 207.2, 215.8"); + } + fall_transition (inslew_load_5x5__13) { + values ("57.4, 57.4, 57.4, 60.6, 66.6", \ + "66.1, 66.1, 66.1, 69.2, 75.3", \ + "83.0, 83.0, 83.0, 86.1, 92.3", \ + "115.1, 115.1, 115.1, 118.2, 124.4", \ + "177.3, 177.3, 177.3, 180.5, 186.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__13) { + values ("98.9, 98.9, 98.9, 103.1, 110.8", \ + "106.0, 106.0, 106.0, 110.3, 118.0", \ + "115.3, 115.3, 115.3, 119.6, 127.5", \ + "124.7, 124.7, 124.7, 129.1, 137.4", \ + "132.2, 132.2, 132.2, 136.7, 145.3"); + } + rise_transition (inslew_load_5x5__13) { + values ("45.2, 45.2, 45.2, 48.4, 54.7", \ + "50.5, 50.5, 50.5, 53.6, 60.0", \ + "61.3, 61.3, 61.3, 64.5, 70.8", \ + "83.3, 83.3, 83.3, 86.3, 92.6", \ + "126.3, 126.3, 126.3, 129.4, 135.6"); + } + cell_fall (inslew_load_5x5__13) { + values ("141.0, 141.0, 141.0, 145.4, 153.7", \ + "151.4, 151.4, 151.4, 155.7, 164.1", \ + "168.5, 168.5, 168.5, 172.9, 181.3", \ + "195.2, 195.2, 195.2, 199.5, 208.1", \ + "237.7, 237.7, 237.7, 242.0, 250.6"); + } + fall_transition (inslew_load_5x5__13) { + values ("84.4, 84.4, 84.4, 87.5, 93.6", \ + "92.6, 92.6, 92.6, 95.7, 101.8", \ + "110.8, 110.8, 110.8, 113.8, 120.0", \ + "146.5, 146.5, 146.5, 149.6, 155.8", \ + "218.0, 218.0, 218.0, 221.2, 227.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__13) { + values ("98.9, 98.9, 98.9, 103.1, 110.8", \ + "106.0, 106.0, 106.0, 110.3, 118.0", \ + "115.3, 115.3, 115.3, 119.6, 127.5", \ + "124.7, 124.7, 124.7, 129.1, 137.4", \ + "132.2, 132.2, 132.2, 136.7, 145.3"); + } + rise_transition (inslew_load_5x5__13) { + values ("45.2, 45.2, 45.2, 48.4, 54.7", \ + "50.5, 50.5, 50.5, 53.6, 60.0", \ + "61.3, 61.3, 61.3, 64.5, 70.8", \ + "83.3, 83.3, 83.3, 86.3, 92.6", \ + "126.3, 126.3, 126.3, 129.4, 135.6"); + } + cell_fall (inslew_load_5x5__13) { + values ("141.0, 141.0, 141.0, 145.4, 153.7", \ + "151.4, 151.4, 151.4, 155.7, 164.1", \ + "168.5, 168.5, 168.5, 172.9, 181.3", \ + "195.2, 195.2, 195.2, 199.5, 208.1", \ + "237.7, 237.7, 237.7, 242.0, 250.6"); + } + fall_transition (inslew_load_5x5__13) { + values ("84.4, 84.4, 84.4, 87.5, 93.6", \ + "92.6, 92.6, 92.6, 95.7, 101.8", \ + "110.8, 110.8, 110.8, 113.8, 120.0", \ + "146.5, 146.5, 146.5, 149.6, 155.8", \ + "218.0, 218.0, 218.0, 221.2, 227.4"); + } + } + timing (maxd_q_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("135.0, 135.0, 135.0, 139.1, 146.6", \ + "143.6, 143.6, 143.6, 147.6, 155.2", \ + "152.0, 152.0, 152.0, 156.1, 163.8", \ + "158.1, 158.1, 158.1, 162.4, 170.1", \ + "158.2, 158.2, 158.2, 162.5, 170.5"); + } + rise_transition (inslew_load_5x5__13) { + values ("37.0, 37.0, 37.0, 40.2, 46.4", \ + "38.7, 38.7, 38.7, 41.9, 48.2", \ + "42.0, 42.0, 42.0, 45.2, 51.5", \ + "48.3, 48.3, 48.3, 51.5, 57.8", \ + "60.7, 60.7, 60.7, 63.9, 70.2"); + } + cell_fall (inslew_load_5x5__13) { + values ("205.9, 205.9, 205.9, 210.2, 218.6", \ + "218.4, 218.4, 218.4, 222.7, 231.1", \ + "235.7, 235.7, 235.7, 240.0, 248.4", \ + "261.4, 261.4, 261.4, 265.8, 274.3", \ + "305.0, 305.0, 305.0, 309.4, 317.9"); + } + fall_transition (inslew_load_5x5__13) { + values ("92.5, 92.5, 92.5, 95.6, 101.7", \ + "96.1, 96.1, 96.1, 99.2, 105.4", \ + "103.2, 103.2, 103.2, 106.2, 112.4", \ + "117.4, 117.4, 117.4, 120.4, 126.6", \ + "146.2, 146.2, 146.2, 149.3, 155.5"); + } + } + timing (maxd_q_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("132.6, 132.6, 132.6, 136.6, 144.3", \ + "138.9, 138.9, 138.9, 143.0, 150.8", \ + "143.8, 143.8, 143.8, 148.0, 155.7", \ + "143.3, 143.3, 143.3, 147.6, 155.4", \ + "130.1, 130.1, 130.1, 134.4, 142.4"); + } + rise_transition (inslew_load_5x5__13) { + values ("42.7, 42.7, 42.7, 45.9, 52.2", \ + "44.2, 44.2, 44.2, 47.4, 53.7", \ + "47.0, 47.0, 47.0, 50.2, 56.5", \ + "52.3, 52.3, 52.3, 55.5, 61.8", \ + "62.6, 62.6, 62.6, 65.8, 72.1"); + } + cell_fall (inslew_load_5x5__13) { + values ("192.8, 192.8, 192.8, 197.1, 205.4", \ + "210.3, 210.3, 210.3, 214.6, 222.9", \ + "236.5, 236.5, 236.5, 240.8, 249.2", \ + "278.2, 278.2, 278.2, 282.6, 291.0", \ + "348.6, 348.6, 348.6, 352.9, 361.5"); + } + fall_transition (inslew_load_5x5__13) { + values ("82.8, 82.8, 82.8, 85.9, 92.1", \ + "87.0, 87.0, 87.0, 90.1, 96.2", \ + "94.7, 94.7, 94.7, 97.8, 104.0", \ + "110.0, 110.0, 110.0, 113.0, 119.2", \ + "139.2, 139.2, 139.2, 142.3, 148.4"); + } + } + internal_power (energy_pos_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__13) { + values ("1933.6, 1933.6, 1933.6, 2050.2, 2283.5", \ + "2185.8, 2185.8, 2185.8, 2302.5, 2535.8", \ + "2699.5, 2699.5, 2699.5, 2816.1, 3049.4", \ + "3732.2, 3732.2, 3732.2, 3848.8, 4082.1", \ + "5813.7, 5813.7, 5813.7, 5930.4, 6163.7"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("2244.4, 2244.4, 2244.4, 2361.0, 2594.3", \ + "2489.7, 2489.7, 2489.7, 2606.4, 2839.7", \ + "2996.3, 2996.3, 2996.3, 3113.0, 3346.3", \ + "4016.6, 4016.6, 4016.6, 4133.3, 4366.6", \ + "6044.8, 6044.8, 6044.8, 6161.5, 6394.8"); + } + } + internal_power (energy_pos_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__13) { + values ("1645.5, 1645.5, 1645.5, 1762.2, 1995.5", \ + "1807.0, 1807.0, 1807.0, 1923.7, 2157.0", \ + "2128.9, 2128.9, 2128.9, 2245.6, 2478.9", \ + "2753.3, 2753.3, 2753.3, 2869.9, 3103.2", \ + "3975.6, 3975.6, 3975.6, 4092.2, 4325.6"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("2571.7, 2571.7, 2571.7, 2688.4, 2921.7", \ + "2834.3, 2834.3, 2834.3, 2951.0, 3184.3", \ + "3359.5, 3359.5, 3359.5, 3476.2, 3709.5", \ + "4371.1, 4371.1, 4371.1, 4487.8, 4721.1", \ + "6341.4, 6341.4, 6341.4, 6458.1, 6691.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__13) { + values ("1425.6, 1425.6, 1425.6, 1542.3, 1775.6", \ + "1603.9, 1603.9, 1603.9, 1720.6, 1953.9", \ + "1956.7, 1956.7, 1956.7, 2073.4, 2306.7", \ + "2646.7, 2646.7, 2646.7, 2763.3, 2996.6", \ + "4005.0, 4005.0, 4005.0, 4121.6, 4355.0"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("2055.0, 2055.0, 2055.0, 2171.6, 2404.9", \ + "2308.0, 2308.0, 2308.0, 2424.7, 2658.0", \ + "2804.5, 2804.5, 2804.5, 2921.1, 3154.4", \ + "3761.2, 3761.2, 3761.2, 3877.8, 4111.1", \ + "5633.1, 5633.1, 5633.1, 5749.7, 5983.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__13) { + values ("1766.3, 1766.3, 1766.3, 1882.9, 2116.2", \ + "1947.8, 1947.8, 1947.8, 2064.4, 2297.7", \ + "2318.9, 2318.9, 2318.9, 2435.6, 2668.9", \ + "3061.7, 3061.7, 3061.7, 3178.3, 3411.6", \ + "4534.9, 4534.9, 4534.9, 4651.5, 4884.8"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("2694.5, 2694.5, 2694.5, 2811.2, 3044.5", \ + "2937.9, 2937.9, 2937.9, 3054.6, 3287.9", \ + "3462.6, 3462.6, 3462.6, 3579.2, 3812.5", \ + "4499.5, 4499.5, 4499.5, 4616.2, 4849.5", \ + "6576.1, 6576.1, 6576.1, 6692.8, 6926.1"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__13) { + values ("1766.3, 1766.3, 1766.3, 1882.9, 2116.2", \ + "1947.8, 1947.8, 1947.8, 2064.4, 2297.7", \ + "2318.9, 2318.9, 2318.9, 2435.6, 2668.9", \ + "3061.7, 3061.7, 3061.7, 3178.3, 3411.6", \ + "4534.9, 4534.9, 4534.9, 4651.5, 4884.8"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("2694.5, 2694.5, 2694.5, 2811.2, 3044.5", \ + "2937.9, 2937.9, 2937.9, 3054.6, 3287.9", \ + "3462.6, 3462.6, 3462.6, 3579.2, 3812.5", \ + "4499.5, 4499.5, 4499.5, 4616.2, 4849.5", \ + "6576.1, 6576.1, 6576.1, 6692.8, 6926.1"); + } + } + internal_power (energy_neg_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__13) { + values ("2237.3, 2237.3, 2237.3, 2353.9, 2587.3", \ + "2368.0, 2368.0, 2368.0, 2484.7, 2718.0", \ + "2620.9, 2620.9, 2620.9, 2737.6, 2970.9", \ + "3115.5, 3115.5, 3115.5, 3232.1, 3465.5", \ + "4094.7, 4094.7, 4094.7, 4211.4, 4444.7"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("3503.1, 3503.1, 3503.1, 3619.7, 3853.0", \ + "3699.9, 3699.9, 3699.9, 3816.6, 4049.9", \ + "4088.4, 4088.4, 4088.4, 4205.0, 4438.3", \ + "4864.1, 4864.1, 4864.1, 4980.7, 5214.1", \ + "6423.0, 6423.0, 6423.0, 6539.6, 6773.0"); + } + } + internal_power (energy_neg_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__13) { + values ("1994.0, 1994.0, 1994.0, 2110.7, 2344.0", \ + "2092.0, 2092.0, 2092.0, 2208.7, 2442.0", \ + "2282.3, 2282.3, 2282.3, 2399.0, 2632.3", \ + "2656.9, 2656.9, 2656.9, 2773.6, 3006.9", \ + "3397.3, 3397.3, 3397.3, 3514.0, 3747.3"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("2981.7, 2981.7, 2981.7, 3098.4, 3331.7", \ + "3178.2, 3178.2, 3178.2, 3294.8, 3528.1", \ + "3559.1, 3559.1, 3559.1, 3675.8, 3909.1", \ + "4312.0, 4312.0, 4312.0, 4428.6, 4661.9", \ + "5791.8, 5791.8, 5791.8, 5908.4, 6141.7"); + } + } + } + } + + cell (na2_x1) { + area : 0.0 ; + cell_leakage_power : 0.0033 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.0049 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.0004 ; + } + pin (i1) { + direction : input ; + capacitance : 29.36 ; + } + pin (i0) { + direction : input ; + capacitance : 28.71 ; + } + pin (nq) { + function : "(!(i1) | !(i0))" ; + direction : output ; + capacitance : 6.82 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__14) { + values ("9.6, 9.6, 9.6, 15.1, 24.4", \ + "10.2, 10.2, 10.2, 16.4, 27.3", \ + "10.6, 10.6, 10.6, 17.3, 29.7", \ + "11.1, 11.1, 11.1, 18.1, 31.5", \ + "11.9, 11.9, 11.9, 19.1, 33.2"); + } + rise_transition (inslew_load_5x5__14) { + values ("21.8, 21.8, 21.8, 27.4, 37.9", \ + "37.1, 37.1, 37.1, 42.9, 53.9", \ + "67.4, 67.4, 67.4, 73.3, 84.8", \ + "127.9, 127.9, 127.9, 133.9, 145.7", \ + "248.8, 248.8, 248.8, 254.8, 266.8"); + } + cell_fall (inslew_load_5x5__14) { + values ("14.8, 14.8, 14.8, 21.1, 32.7", \ + "17.0, 17.0, 17.0, 23.8, 36.5", \ + "20.5, 20.5, 20.5, 27.8, 41.6", \ + "27.2, 27.2, 27.2, 34.8, 49.3", \ + "40.4, 40.4, 40.4, 48.1, 63.1"); + } + fall_transition (inslew_load_5x5__14) { + values ("30.5, 30.5, 30.5, 37.4, 51.1", \ + "50.2, 50.2, 50.2, 57.3, 71.1", \ + "89.2, 89.2, 89.2, 96.3, 110.4", \ + "167.0, 167.0, 167.0, 174.1, 188.4", \ + "322.3, 322.3, 322.3, 329.5, 343.9"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__14) { + values ("4.8, 4.8, 4.8, 11.0, 21.0", \ + "1.2, 1.2, 1.2, 8.3, 20.5", \ + "-6.5, -6.5, -6.5, 1.2, 15.3", \ + "-22.6, -22.6, -22.6, -14.3, 1.1", \ + "-54.9, -54.9, -54.9, -46.3, -29.8"); + } + rise_transition (inslew_load_5x5__14) { + values ("17.4, 17.4, 17.4, 23.1, 33.9", \ + "29.4, 29.4, 29.4, 35.4, 46.8", \ + "53.2, 53.2, 53.2, 59.4, 71.4", \ + "100.6, 100.6, 100.6, 107.0, 119.4", \ + "195.3, 195.3, 195.3, 201.8, 214.7"); + } + cell_fall (inslew_load_5x5__14) { + values ("16.1, 16.1, 16.1, 23.6, 36.8", \ + "22.8, 22.8, 22.8, 30.9, 45.6", \ + "35.1, 35.1, 35.1, 43.6, 59.7", \ + "59.1, 59.1, 59.1, 67.9, 84.8", \ + "106.7, 106.7, 106.7, 115.6, 133.1"); + } + fall_transition (inslew_load_5x5__14) { + values ("28.3, 28.3, 28.3, 35.6, 49.8", \ + "50.6, 50.6, 50.6, 58.1, 72.6", \ + "94.3, 94.3, 94.3, 101.9, 116.8", \ + "181.2, 181.2, 181.2, 188.8, 204.1", \ + "354.6, 354.6, 354.6, 362.3, 377.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__14) { + values ("255.7, 255.7, 255.7, 340.9, 511.3", \ + "397.7, 397.7, 397.7, 482.9, 653.4", \ + "681.8, 681.8, 681.8, 767.0, 937.4", \ + "1249.8, 1249.8, 1249.8, 1335.1, 1505.5", \ + "2386.0, 2386.0, 2386.0, 2471.2, 2641.7"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("305.6, 305.6, 305.6, 390.8, 561.2", \ + "475.3, 475.3, 475.3, 560.5, 730.9", \ + "814.6, 814.6, 814.6, 899.8, 1070.3", \ + "1493.4, 1493.4, 1493.4, 1578.6, 1749.0", \ + "2850.9, 2850.9, 2850.9, 2936.2, 3106.6"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__14) { + values ("183.1, 183.1, 183.1, 268.4, 438.8", \ + "281.1, 281.1, 281.1, 366.3, 536.7", \ + "477.0, 477.0, 477.0, 562.2, 732.6", \ + "868.7, 868.7, 868.7, 953.9, 1124.3", \ + "1652.2, 1652.2, 1652.2, 1737.4, 1907.8"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("255.5, 255.5, 255.5, 340.7, 511.2", \ + "425.8, 425.8, 425.8, 511.0, 681.5", \ + "766.4, 766.4, 766.4, 851.6, 1022.1", \ + "1447.6, 1447.6, 1447.6, 1532.8, 1703.3", \ + "2810.0, 2810.0, 2810.0, 2895.2, 3065.7"); + } + } + } + } + + cell (na2_x4) { + area : 0.0 ; + cell_leakage_power : 0.011 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.0022 ; + } + leakage_power () { + when : "(i0 ^ i1)" ; + value : 0.017 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.013 ; + } + pin (i1) { + direction : input ; + capacitance : 24.61 ; + } + pin (i0) { + direction : input ; + capacitance : 24.61 ; + } + pin (nq) { + function : "(!(i0) | !(i1))" ; + direction : output ; + capacitance : 8.75 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("85.7, 85.7, 85.7, 89.3, 95.8", \ + "89.0, 89.0, 89.0, 92.6, 99.2", \ + "90.3, 90.3, 90.3, 93.9, 100.6", \ + "85.6, 85.6, 85.6, 89.3, 96.2", \ + "68.4, 68.4, 68.4, 72.2, 79.4"); + } + rise_transition (inslew_load_5x5__15) { + values ("21.4, 21.4, 21.4, 24.4, 30.0", \ + "22.7, 22.7, 22.7, 25.7, 31.4", \ + "25.4, 25.4, 25.4, 28.4, 34.1", \ + "30.7, 30.7, 30.7, 33.7, 39.5", \ + "41.0, 41.0, 41.0, 44.0, 49.9"); + } + cell_fall (inslew_load_5x5__15) { + values ("98.8, 98.8, 98.8, 102.7, 109.9", \ + "111.9, 111.9, 111.9, 115.9, 123.1", \ + "131.4, 131.4, 131.4, 135.3, 142.6", \ + "161.9, 161.9, 161.9, 165.9, 173.4", \ + "212.7, 212.7, 212.7, 216.7, 224.4"); + } + fall_transition (inslew_load_5x5__15) { + values ("31.0, 31.0, 31.0, 33.9, 39.5", \ + "33.9, 33.9, 33.9, 36.8, 42.4", \ + "39.3, 39.3, 39.3, 42.2, 47.8", \ + "49.2, 49.2, 49.2, 52.1, 57.8", \ + "68.0, 68.0, 68.0, 70.9, 76.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("90.6, 90.6, 90.6, 94.2, 100.7", \ + "98.1, 98.1, 98.1, 101.8, 108.4", \ + "107.8, 107.8, 107.8, 111.5, 118.2", \ + "120.4, 120.4, 120.4, 124.2, 131.2", \ + "137.9, 137.9, 137.9, 141.8, 149.1"); + } + rise_transition (inslew_load_5x5__15) { + values ("21.8, 21.8, 21.8, 24.8, 30.4", \ + "23.5, 23.5, 23.5, 26.5, 32.2", \ + "26.9, 26.9, 26.9, 29.9, 35.6", \ + "33.6, 33.6, 33.6, 36.6, 42.4", \ + "46.6, 46.6, 46.6, 49.6, 55.5"); + } + cell_fall (inslew_load_5x5__15) { + values ("95.3, 95.3, 95.3, 99.1, 106.3", \ + "102.8, 102.8, 102.8, 106.7, 113.9", \ + "112.9, 112.9, 112.9, 116.9, 124.2", \ + "126.0, 126.0, 126.0, 130.0, 137.5", \ + "143.0, 143.0, 143.0, 147.0, 154.7"); + } + fall_transition (inslew_load_5x5__15) { + values ("31.2, 31.2, 31.2, 34.1, 39.7", \ + "33.7, 33.7, 33.7, 36.6, 42.2", \ + "38.5, 38.5, 38.5, 41.4, 47.1", \ + "47.5, 47.5, 47.5, 50.4, 56.1", \ + "64.4, 64.4, 64.4, 67.3, 73.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__15) { + values ("1686.7, 1686.7, 1686.7, 1796.1, 2014.8", \ + "1842.9, 1842.9, 1842.9, 1952.3, 2171.0", \ + "2151.7, 2151.7, 2151.7, 2261.1, 2479.8", \ + "2766.1, 2766.1, 2766.1, 2875.4, 3094.2", \ + "3988.0, 3988.0, 3988.0, 4097.3, 4316.1"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("2014.1, 2014.1, 2014.1, 2123.4, 2342.2", \ + "2279.8, 2279.8, 2279.8, 2389.2, 2607.9", \ + "2800.4, 2800.4, 2800.4, 2909.8, 3128.5", \ + "3822.1, 3822.1, 3822.1, 3931.5, 4150.2", \ + "5843.6, 5843.6, 5843.6, 5953.0, 6171.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__15) { + values ("1777.4, 1777.4, 1777.4, 1886.7, 2105.5", \ + "1992.0, 1992.0, 1992.0, 2101.4, 2320.1", \ + "2418.9, 2418.9, 2418.9, 2528.3, 2747.0", \ + "3269.2, 3269.2, 3269.2, 3378.6, 3597.3", \ + "4961.3, 4961.3, 4961.3, 5070.7, 5289.4"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("2070.5, 2070.5, 2070.5, 2179.9, 2398.6", \ + "2323.7, 2323.7, 2323.7, 2433.0, 2651.8", \ + "2822.7, 2822.7, 2822.7, 2932.0, 3150.7", \ + "3808.5, 3808.5, 3808.5, 3917.9, 4136.6", \ + "5757.4, 5757.4, 5757.4, 5866.8, 6085.5"); + } + } + } + } + + cell (na3_x1) { + area : 0.0 ; + cell_leakage_power : 0.0023 ; + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 0.0045 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 0.0042 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2)) | (!(i0) & (i1 ^ i2)))" ; + value : 0.00038 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.00019 ; + } + pin (i2) { + direction : input ; + capacitance : 26.65 ; + } + pin (i1) { + direction : input ; + capacitance : 26.22 ; + } + pin (i0) { + direction : input ; + capacitance : 25.17 ; + } + pin (nq) { + function : "((!(i1) | !(i0)) | !(i2))" ; + direction : output ; + capacitance : 9.16 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("12.1, 12.1, 12.1, 18.9, 30.6", \ + "12.4, 12.4, 12.4, 20.3, 34.1", \ + "11.5, 11.5, 11.5, 20.4, 36.4", \ + "9.0, 9.0, 9.0, 18.5, 36.4", \ + "3.7, 3.7, 3.7, 13.6, 32.6"); + } + rise_transition (inslew_load_5x5__16) { + values ("24.3, 24.3, 24.3, 31.6, 45.5", \ + "39.1, 39.1, 39.1, 46.7, 61.2", \ + "68.2, 68.2, 68.2, 76.0, 91.3", \ + "126.1, 126.1, 126.1, 134.2, 149.9", \ + "241.9, 241.9, 241.9, 250.0, 266.2"); + } + cell_fall (inslew_load_5x5__16) { + values ("25.3, 25.3, 25.3, 35.2, 54.4", \ + "29.6, 29.6, 29.6, 40.1, 60.1", \ + "37.4, 37.4, 37.4, 48.4, 69.5", \ + "52.2, 52.2, 52.2, 63.6, 85.7", \ + "81.4, 81.4, 81.4, 93.0, 115.9"); + } + fall_transition (inslew_load_5x5__16) { + values ("51.2, 51.2, 51.2, 65.4, 94.1", \ + "76.9, 76.9, 76.9, 91.1, 119.7", \ + "128.1, 128.1, 128.1, 142.3, 170.6", \ + "230.0, 230.0, 230.0, 244.3, 272.7", \ + "433.7, 433.7, 433.7, 448.0, 476.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("8.7, 8.7, 8.7, 16.0, 28.1", \ + "5.3, 5.3, 5.3, 14.1, 28.9", \ + "-2.9, -2.9, -2.9, 7.1, 24.7", \ + "-20.6, -20.6, -20.6, -9.6, 10.4", \ + "-56.5, -56.5, -56.5, -45.0, -23.1"); + } + rise_transition (inslew_load_5x5__16) { + values ("20.9, 20.9, 20.9, 28.4, 42.4", \ + "32.8, 32.8, 32.8, 40.7, 55.5", \ + "56.0, 56.0, 56.0, 64.3, 80.0", \ + "102.1, 102.1, 102.1, 110.6, 127.1", \ + "194.0, 194.0, 194.0, 202.8, 219.9"); + } + cell_fall (inslew_load_5x5__16) { + values ("25.5, 25.5, 25.5, 36.2, 56.0", \ + "33.6, 33.6, 33.6, 45.1, 66.4", \ + "48.4, 48.4, 48.4, 60.5, 83.5", \ + "77.1, 77.1, 77.1, 89.7, 113.9", \ + "134.0, 134.0, 134.0, 146.8, 172.0"); + } + fall_transition (inslew_load_5x5__16) { + values ("46.0, 46.0, 46.0, 60.4, 89.2", \ + "73.3, 73.3, 73.3, 87.8, 116.5", \ + "126.9, 126.9, 126.9, 141.5, 170.4", \ + "233.4, 233.4, 233.4, 248.0, 277.2", \ + "445.9, 445.9, 445.9, 460.7, 490.1"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("5.3, 5.3, 5.3, 13.2, 25.8", \ + "-0.7, -0.7, -0.7, 8.9, 24.6", \ + "-14.3, -14.3, -14.3, -3.1, 16.0", \ + "-42.6, -42.6, -42.6, -30.2, -7.9", \ + "-100.0, -100.0, -100.0, -86.8, -62.1"); + } + rise_transition (inslew_load_5x5__16) { + values ("17.8, 17.8, 17.8, 25.4, 39.7", \ + "27.8, 27.8, 27.8, 35.9, 51.1", \ + "47.1, 47.1, 47.1, 55.8, 72.0", \ + "85.6, 85.6, 85.6, 94.7, 111.9", \ + "162.3, 162.3, 162.3, 171.6, 189.7"); + } + cell_fall (inslew_load_5x5__16) { + values ("25.6, 25.6, 25.6, 37.6, 59.0", \ + "37.7, 37.7, 37.7, 50.8, 74.4", \ + "59.7, 59.7, 59.7, 73.6, 99.6", \ + "102.4, 102.4, 102.4, 116.8, 144.5", \ + "187.0, 187.0, 187.0, 201.7, 230.6"); + } + fall_transition (inslew_load_5x5__16) { + values ("41.3, 41.3, 41.3, 56.3, 85.8", \ + "70.8, 70.8, 70.8, 86.0, 115.9", \ + "127.6, 127.6, 127.6, 143.1, 173.4", \ + "240.1, 240.1, 240.1, 255.7, 286.5", \ + "464.4, 464.4, 464.4, 480.0, 511.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__16) { + values ("291.9, 291.9, 291.9, 406.4, 635.5", \ + "425.0, 425.0, 425.0, 539.5, 768.6", \ + "691.1, 691.1, 691.1, 805.6, 1034.7", \ + "1223.4, 1223.4, 1223.4, 1337.9, 1567.0", \ + "2287.9, 2287.9, 2287.9, 2402.5, 2631.5"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("373.5, 373.5, 373.5, 488.0, 717.0", \ + "542.9, 542.9, 542.9, 657.4, 886.4", \ + "881.7, 881.7, 881.7, 996.2, 1225.3", \ + "1559.4, 1559.4, 1559.4, 1673.9, 1903.0", \ + "2914.7, 2914.7, 2914.7, 3029.2, 3258.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__16) { + values ("234.5, 234.5, 234.5, 349.0, 578.1", \ + "327.9, 327.9, 327.9, 442.4, 671.4", \ + "514.6, 514.6, 514.6, 629.1, 858.2", \ + "888.1, 888.1, 888.1, 1002.6, 1231.7", \ + "1635.1, 1635.1, 1635.1, 1749.6, 1978.7"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("326.9, 326.9, 326.9, 441.5, 670.5", \ + "493.2, 493.2, 493.2, 607.7, 836.8", \ + "825.8, 825.8, 825.8, 940.3, 1169.4", \ + "1491.0, 1491.0, 1491.0, 1605.5, 1834.6", \ + "2821.3, 2821.3, 2821.3, 2935.9, 3164.9"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__16) { + values ("184.3, 184.3, 184.3, 298.8, 527.9", \ + "254.1, 254.1, 254.1, 368.6, 597.7", \ + "393.7, 393.7, 393.7, 508.2, 737.2", \ + "672.8, 672.8, 672.8, 787.3, 1016.4", \ + "1231.1, 1231.1, 1231.1, 1345.6, 1574.7"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("274.7, 274.7, 274.7, 389.2, 618.3", \ + "434.9, 434.9, 434.9, 549.4, 778.5", \ + "755.3, 755.3, 755.3, 869.8, 1098.9", \ + "1396.1, 1396.1, 1396.1, 1510.6, 1739.7", \ + "2677.7, 2677.7, 2677.7, 2792.3, 3021.3"); + } + } + } + } + + cell (na3_x4) { + area : 0.0 ; + cell_leakage_power : 0.017 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 0.0049 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2)) | (!(i0) & i1 & i2))" ; + value : 0.025 ; + } + leakage_power () { + when : "((!(i0) & (!(i1) | !(i2))) | (!(i1) & !(i2)))" ; + value : 0.021 ; + } + pin (i2) { + direction : input ; + capacitance : 20.96 ; + } + pin (i1) { + direction : input ; + capacitance : 20.96 ; + } + pin (i0) { + direction : input ; + capacitance : 22.47 ; + } + pin (nq) { + function : "(!(i0) | !(i2) | !(i1))" ; + direction : output ; + capacitance : 9.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("60.7, 60.7, 60.7, 64.1, 69.9", \ + "59.7, 59.7, 59.7, 63.0, 68.9", \ + "51.3, 51.3, 51.3, 54.7, 60.8", \ + "27.6, 27.6, 27.6, 31.1, 37.3", \ + "-28.1, -28.1, -28.1, -24.5, -18.0"); + } + rise_transition (inslew_load_5x5__17) { + values ("15.7, 15.7, 15.7, 18.8, 24.7", \ + "17.0, 17.0, 17.0, 20.1, 26.0", \ + "19.3, 19.3, 19.3, 22.5, 28.4", \ + "23.7, 23.7, 23.7, 26.8, 32.8", \ + "31.8, 31.8, 31.8, 34.9, 40.9"); + } + cell_fall (inslew_load_5x5__17) { + values ("110.0, 110.0, 110.0, 113.4, 119.8", \ + "130.8, 130.8, 130.8, 134.2, 140.7", \ + "165.2, 165.2, 165.2, 168.7, 175.3", \ + "226.4, 226.4, 226.4, 230.0, 236.6", \ + "342.2, 342.2, 342.2, 345.8, 352.7"); + } + fall_transition (inslew_load_5x5__17) { + values ("29.1, 29.1, 29.1, 31.5, 36.0", \ + "33.4, 33.4, 33.4, 35.8, 40.4", \ + "41.5, 41.5, 41.5, 43.9, 48.5", \ + "57.0, 57.0, 57.0, 59.4, 64.1", \ + "87.4, 87.4, 87.4, 89.8, 94.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("66.9, 66.9, 66.9, 70.2, 76.1", \ + "71.1, 71.1, 71.1, 74.4, 80.4", \ + "73.8, 73.8, 73.8, 77.3, 83.4", \ + "73.1, 73.1, 73.1, 76.7, 83.0", \ + "64.3, 64.3, 64.3, 67.9, 74.7"); + } + rise_transition (inslew_load_5x5__17) { + values ("16.4, 16.4, 16.4, 19.5, 25.4", \ + "18.1, 18.1, 18.1, 21.3, 27.2", \ + "21.5, 21.5, 21.5, 24.6, 30.5", \ + "27.6, 27.6, 27.6, 30.7, 36.8", \ + "39.3, 39.3, 39.3, 42.4, 48.5"); + } + cell_fall (inslew_load_5x5__17) { + values ("108.6, 108.6, 108.6, 112.1, 118.5", \ + "119.7, 119.7, 119.7, 123.1, 129.7", \ + "138.4, 138.4, 138.4, 141.9, 148.5", \ + "171.3, 171.3, 171.3, 174.8, 181.5", \ + "231.7, 231.7, 231.7, 235.3, 242.2"); + } + fall_transition (inslew_load_5x5__17) { + values ("30.4, 30.4, 30.4, 32.8, 37.3", \ + "34.2, 34.2, 34.2, 36.6, 41.1", \ + "41.4, 41.4, 41.4, 43.8, 48.5", \ + "55.7, 55.7, 55.7, 58.1, 62.8", \ + "83.7, 83.7, 83.7, 86.1, 90.9"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("63.8, 63.8, 63.8, 67.2, 73.0", \ + "64.8, 64.8, 64.8, 68.2, 74.2", \ + "61.4, 61.4, 61.4, 64.8, 70.9", \ + "47.3, 47.3, 47.3, 50.8, 57.1", \ + "11.6, 11.6, 11.6, 15.2, 21.8"); + } + rise_transition (inslew_load_5x5__17) { + values ("16.0, 16.0, 16.0, 19.2, 25.1", \ + "17.5, 17.5, 17.5, 20.6, 26.5", \ + "20.3, 20.3, 20.3, 23.4, 29.3", \ + "25.3, 25.3, 25.3, 28.4, 34.5", \ + "34.8, 34.8, 34.8, 38.0, 44.0"); + } + cell_fall (inslew_load_5x5__17) { + values ("108.7, 108.7, 108.7, 112.1, 118.5", \ + "124.2, 124.2, 124.2, 127.6, 134.1", \ + "150.3, 150.3, 150.3, 153.8, 160.3", \ + "196.6, 196.6, 196.6, 200.1, 206.8", \ + "283.4, 283.4, 283.4, 287.0, 293.9"); + } + fall_transition (inslew_load_5x5__17) { + values ("29.7, 29.7, 29.7, 32.0, 36.6", \ + "33.6, 33.6, 33.6, 36.0, 40.5", \ + "41.2, 41.2, 41.2, 43.6, 48.2", \ + "55.9, 55.9, 55.9, 58.3, 63.0", \ + "84.8, 84.8, 84.8, 87.2, 91.9"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__17) { + values ("1612.6, 1612.6, 1612.6, 1734.7, 1978.9", \ + "1742.5, 1742.5, 1742.5, 1864.6, 2108.8", \ + "1994.3, 1994.3, 1994.3, 2116.4, 2360.6", \ + "2485.0, 2485.0, 2485.0, 2607.1, 2851.3", \ + "3451.4, 3451.4, 3451.4, 3573.5, 3817.7"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("2244.2, 2244.2, 2244.2, 2366.3, 2610.5", \ + "2619.9, 2619.9, 2619.9, 2742.0, 2986.2", \ + "3347.0, 3347.0, 3347.0, 3469.1, 3713.3", \ + "4780.6, 4780.6, 4780.6, 4902.7, 5146.9", \ + "7628.2, 7628.2, 7628.2, 7750.3, 7994.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__17) { + values ("1752.9, 1752.9, 1752.9, 1875.0, 2119.2", \ + "1968.5, 1968.5, 1968.5, 2090.6, 2334.8", \ + "2392.3, 2392.3, 2392.3, 2514.4, 2758.6", \ + "3227.3, 3227.3, 3227.3, 3349.4, 3593.6", \ + "4879.3, 4879.3, 4879.3, 5001.4, 5245.6"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("2412.8, 2412.8, 2412.8, 2534.9, 2779.1", \ + "2774.9, 2774.9, 2774.9, 2897.0, 3141.2", \ + "3490.1, 3490.1, 3490.1, 3612.2, 3856.4", \ + "4914.3, 4914.3, 4914.3, 5036.4, 5280.6", \ + "7750.5, 7750.5, 7750.5, 7872.6, 8116.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__17) { + values ("1680.5, 1680.5, 1680.5, 1802.6, 2046.8", \ + "1843.1, 1843.1, 1843.1, 1965.2, 2209.4", \ + "2162.3, 2162.3, 2162.3, 2284.4, 2528.6", \ + "2787.3, 2787.3, 2787.3, 2909.4, 3153.6", \ + "4021.3, 4021.3, 4021.3, 4143.4, 4387.6"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("2326.2, 2326.2, 2326.2, 2448.3, 2692.5", \ + "2690.1, 2690.1, 2690.1, 2812.2, 3056.4", \ + "3407.0, 3407.0, 3407.0, 3529.1, 3773.3", \ + "4828.6, 4828.6, 4828.6, 4950.7, 5194.9", \ + "7656.5, 7656.5, 7656.5, 7778.6, 8022.8"); + } + } + } + } + + cell (na4_x1) { + area : 0.0 ; + cell_leakage_power : 0.0019 ; + leakage_power () { + when : "(!(i3) & i2 & i1 & i0)" ; + value : 0.0045 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3) | (!(i0) & i1 & i2 & i3))" ; + value : 0.0042 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))) | (!(i0) & ((i1 & (i2 ^ i3)) | (!(i1) & i2 & i3))))" ; + value : 0.00038 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))))" ; + value : 0.00019 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.00013 ; + } + pin (i3) { + direction : input ; + capacitance : 25.52 ; + } + pin (i2) { + direction : input ; + capacitance : 24.74 ; + } + pin (i1) { + direction : input ; + capacitance : 24.74 ; + } + pin (i0) { + direction : input ; + capacitance : 25.09 ; + } + pin (nq) { + function : "(((!(i3) | !(i1)) | !(i0)) | !(i2))" ; + direction : output ; + capacitance : 10.69 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("14.2, 14.2, 14.2, 21.7, 34.7", \ + "14.7, 14.7, 14.7, 23.6, 39.1", \ + "14.2, 14.2, 14.2, 24.2, 42.3", \ + "11.8, 11.8, 11.8, 22.7, 43.0", \ + "6.6, 6.6, 6.6, 18.0, 39.9"); + } + rise_transition (inslew_load_5x5__18) { + values ("26.4, 26.4, 26.4, 34.8, 50.8", \ + "41.2, 41.2, 41.2, 50.0, 66.8", \ + "70.4, 70.4, 70.4, 79.5, 97.1", \ + "128.4, 128.4, 128.4, 137.7, 156.0", \ + "244.2, 244.2, 244.2, 253.7, 272.4"); + } + cell_fall (inslew_load_5x5__18) { + values ("36.0, 36.0, 36.0, 49.7, 76.5", \ + "41.6, 41.6, 41.6, 55.6, 82.9", \ + "52.1, 52.1, 52.1, 66.5, 94.6", \ + "72.5, 72.5, 72.5, 87.3, 116.3", \ + "113.0, 113.0, 113.0, 128.0, 157.7"); + } + fall_transition (inslew_load_5x5__18) { + values ("75.6, 75.6, 75.6, 98.0, 143.2", \ + "107.7, 107.7, 107.7, 129.9, 174.5", \ + "171.6, 171.6, 171.6, 193.5, 237.6", \ + "298.0, 298.0, 298.0, 321.1, 364.8", \ + "551.6, 551.6, 551.6, 573.6, 617.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("11.2, 11.2, 11.2, 19.2, 32.6", \ + "8.3, 8.3, 8.3, 18.0, 34.3", \ + "0.4, 0.4, 0.4, 11.6, 31.3", \ + "-16.9, -16.9, -16.9, -4.5, 18.2", \ + "-52.7, -52.7, -52.7, -39.5, -14.4"); + } + rise_transition (inslew_load_5x5__18) { + values ("23.4, 23.4, 23.4, 31.9, 48.1", \ + "35.3, 35.3, 35.3, 44.4, 61.4", \ + "58.7, 58.7, 58.7, 68.2, 86.3", \ + "104.9, 104.9, 104.9, 114.7, 133.8", \ + "196.9, 196.9, 196.9, 207.0, 226.8"); + } + cell_fall (inslew_load_5x5__18) { + values ("35.7, 35.7, 35.7, 49.8, 76.9", \ + "45.2, 45.2, 45.2, 59.9, 88.0", \ + "62.6, 62.6, 62.6, 77.9, 107.4", \ + "96.3, 96.3, 96.3, 112.2, 143.0", \ + "163.0, 163.0, 163.0, 179.3, 211.1"); + } + fall_transition (inslew_load_5x5__18) { + values ("68.9, 68.9, 68.9, 91.2, 136.5", \ + "102.4, 102.4, 102.4, 125.0, 169.5", \ + "168.1, 168.1, 168.1, 190.5, 235.6", \ + "299.0, 299.0, 299.0, 321.3, 365.9", \ + "560.2, 560.2, 560.2, 582.6, 627.3"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("8.7, 8.7, 8.7, 17.1, 30.8", \ + "3.4, 3.4, 3.4, 13.7, 30.8", \ + "-9.6, -9.6, -9.6, 2.7, 23.7", \ + "-37.5, -37.5, -37.5, -23.6, 1.2", \ + "-94.6, -94.6, -94.6, -79.6, -51.6"); + } + rise_transition (inslew_load_5x5__18) { + values ("20.9, 20.9, 20.9, 29.5, 45.8", \ + "31.0, 31.0, 31.0, 40.3, 57.6", \ + "50.6, 50.6, 50.6, 60.5, 79.0", \ + "89.2, 89.2, 89.2, 99.6, 119.4", \ + "166.0, 166.0, 166.0, 176.8, 197.6"); + } + cell_fall (inslew_load_5x5__18) { + values ("33.6, 33.6, 33.6, 48.3, 76.1", \ + "46.0, 46.0, 46.0, 61.6, 90.9", \ + "68.6, 68.6, 68.6, 85.1, 116.4", \ + "112.6, 112.6, 112.6, 129.7, 162.8", \ + "199.7, 199.7, 199.7, 217.2, 251.6"); + } + fall_transition (inslew_load_5x5__18) { + values ("60.7, 60.7, 60.7, 83.5, 128.9", \ + "95.1, 95.1, 95.1, 117.7, 163.3", \ + "162.0, 162.0, 162.0, 184.8, 230.0", \ + "294.5, 294.5, 294.5, 317.4, 363.0", \ + "558.8, 558.8, 558.8, 581.8, 627.7"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("5.8, 5.8, 5.8, 14.7, 28.9", \ + "-1.5, -1.5, -1.5, 9.7, 27.6", \ + "-18.5, -18.5, -18.5, -4.9, 17.3", \ + "-54.4, -54.4, -54.4, -38.9, -11.9", \ + "-127.5, -127.5, -127.5, -110.6, -79.7"); + } + rise_transition (inslew_load_5x5__18) { + values ("18.2, 18.2, 18.2, 27.0, 43.5", \ + "27.0, 27.0, 27.0, 36.6, 54.1", \ + "43.9, 43.9, 43.9, 54.3, 73.2", \ + "77.3, 77.3, 77.3, 88.1, 108.7", \ + "143.4, 143.4, 143.4, 154.8, 176.6"); + } + cell_fall (inslew_load_5x5__18) { + values ("30.1, 30.1, 30.1, 45.3, 74.1", \ + "44.8, 44.8, 44.8, 61.5, 92.2", \ + "71.7, 71.7, 71.7, 89.5, 122.8", \ + "124.0, 124.0, 124.0, 142.5, 178.0", \ + "227.7, 227.7, 227.7, 246.7, 283.7"); + } + fall_transition (inslew_load_5x5__18) { + values ("52.3, 52.3, 52.3, 74.7, 121.2", \ + "87.2, 87.2, 87.2, 110.4, 156.2", \ + "154.6, 154.6, 154.6, 178.0, 224.4", \ + "287.8, 287.8, 287.8, 311.4, 358.4", \ + "553.4, 553.4, 553.4, 577.1, 624.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__18) { + values ("324.4, 324.4, 324.4, 458.0, 725.3", \ + "457.5, 457.5, 457.5, 591.1, 858.4", \ + "723.6, 723.6, 723.6, 857.2, 1124.5", \ + "1255.9, 1255.9, 1255.9, 1389.5, 1656.8", \ + "2320.4, 2320.4, 2320.4, 2454.1, 2721.3"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("430.0, 430.0, 430.0, 563.6, 830.9", \ + "599.4, 599.4, 599.4, 733.1, 1000.3", \ + "938.3, 938.3, 938.3, 1071.9, 1339.2", \ + "1615.9, 1615.9, 1615.9, 1749.6, 2016.8", \ + "2971.3, 2971.3, 2971.3, 3104.9, 3372.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__18) { + values ("271.3, 271.3, 271.3, 405.0, 672.2", \ + "364.7, 364.7, 364.7, 498.3, 765.6", \ + "551.5, 551.5, 551.5, 685.1, 952.4", \ + "924.9, 924.9, 924.9, 1058.6, 1325.9", \ + "1671.9, 1671.9, 1671.9, 1805.6, 2072.8"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("388.0, 388.0, 388.0, 521.7, 788.9", \ + "554.3, 554.3, 554.3, 688.0, 955.2", \ + "886.9, 886.9, 886.9, 1020.6, 1287.8", \ + "1552.1, 1552.1, 1552.1, 1685.7, 1953.0", \ + "2882.4, 2882.4, 2882.4, 3016.1, 3283.4"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__18) { + values ("230.0, 230.0, 230.0, 363.7, 630.9", \ + "299.8, 299.8, 299.8, 433.4, 700.7", \ + "439.4, 439.4, 439.4, 573.0, 840.3", \ + "718.5, 718.5, 718.5, 852.2, 1119.4", \ + "1276.8, 1276.8, 1276.8, 1410.4, 1677.7"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("338.1, 338.1, 338.1, 471.7, 739.0", \ + "498.3, 498.3, 498.3, 631.9, 899.2", \ + "818.7, 818.7, 818.7, 952.3, 1219.6", \ + "1459.5, 1459.5, 1459.5, 1593.1, 1860.4", \ + "2741.1, 2741.1, 2741.1, 2874.7, 3142.0"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__18) { + values ("188.1, 188.1, 188.1, 321.7, 589.0", \ + "242.5, 242.5, 242.5, 376.1, 643.4", \ + "351.3, 351.3, 351.3, 485.0, 752.3", \ + "569.0, 569.0, 569.0, 702.7, 970.0", \ + "1004.5, 1004.5, 1004.5, 1138.1, 1405.4"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("287.0, 287.0, 287.0, 420.6, 687.9", \ + "440.3, 440.3, 440.3, 574.0, 841.2", \ + "747.0, 747.0, 747.0, 880.6, 1147.9", \ + "1360.3, 1360.3, 1360.3, 1494.0, 1761.3", \ + "2587.1, 2587.1, 2587.1, 2720.7, 2988.0"); + } + } + } + } + + cell (na4_x4) { + area : 0.0 ; + cell_leakage_power : 0.011 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 0.0045 ; + } + leakage_power () { + when : "((i0 & ((i1 & (i2 ^ i3)) | (!(i1) & i2 & i3))) | (!(i0) & i1 & i2 & i3))" ; + value : 0.016 ; + } + leakage_power () { + when : "((!(i0) & (!(i1) | !(i2) | !(i3))) | (!(i1) & (!(i2) | !(i3))) | (!(i2) & !(i3)))" ; + value : 0.012 ; + } + pin (i3) { + direction : input ; + capacitance : 25.44 ; + } + pin (i2) { + direction : input ; + capacitance : 26.85 ; + } + pin (i1) { + direction : input ; + capacitance : 25.79 ; + } + pin (i0) { + direction : input ; + capacitance : 25.44 ; + } + pin (nq) { + function : "(!(i3) | !(i2) | !(i1) | !(i0))" ; + direction : output ; + capacitance : 9.03 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("69.8, 69.8, 69.8, 73.4, 79.6", \ + "74.2, 74.2, 74.2, 77.9, 84.2", \ + "77.6, 77.6, 77.6, 81.4, 88.0", \ + "77.5, 77.5, 77.5, 81.4, 88.2", \ + "69.5, 69.5, 69.5, 73.5, 80.8"); + } + rise_transition (inslew_load_5x5__19) { + values ("14.7, 14.7, 14.7, 17.7, 23.4", \ + "16.0, 16.0, 16.0, 19.0, 24.7", \ + "18.4, 18.4, 18.4, 21.5, 27.3", \ + "23.0, 23.0, 23.0, 26.2, 32.0", \ + "31.7, 31.7, 31.7, 34.8, 40.9"); + } + cell_fall (inslew_load_5x5__19) { + values ("147.8, 147.8, 147.8, 152.1, 160.0", \ + "161.3, 161.3, 161.3, 165.6, 173.6", \ + "185.3, 185.3, 185.3, 189.6, 197.7", \ + "229.5, 229.5, 229.5, 233.9, 242.2", \ + "311.9, 311.9, 311.9, 316.3, 324.8"); + } + fall_transition (inslew_load_5x5__19) { + values ("46.7, 46.7, 46.7, 49.9, 56.0", \ + "52.2, 52.2, 52.2, 55.3, 61.5", \ + "62.9, 62.9, 62.9, 66.0, 72.2", \ + "84.0, 84.0, 84.0, 87.2, 93.4", \ + "125.3, 125.3, 125.3, 128.5, 134.7"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("66.9, 66.9, 66.9, 70.6, 76.7", \ + "68.2, 68.2, 68.2, 71.9, 78.2", \ + "64.9, 64.9, 64.9, 68.6, 75.1", \ + "51.0, 51.0, 51.0, 54.8, 61.5", \ + "14.9, 14.9, 14.9, 18.8, 25.9"); + } + rise_transition (inslew_load_5x5__19) { + values ("14.4, 14.4, 14.4, 17.4, 23.1", \ + "15.5, 15.5, 15.5, 18.5, 24.2", \ + "17.5, 17.5, 17.5, 20.6, 26.3", \ + "21.2, 21.2, 21.2, 24.3, 30.2", \ + "28.3, 28.3, 28.3, 31.4, 37.4"); + } + cell_fall (inslew_load_5x5__19) { + values ("146.5, 146.5, 146.5, 150.7, 158.6", \ + "164.7, 164.7, 164.7, 168.9, 176.9", \ + "196.7, 196.7, 196.7, 201.0, 209.1", \ + "254.9, 254.9, 254.9, 259.3, 267.6", \ + "365.2, 365.2, 365.2, 369.5, 378.0"); + } + fall_transition (inslew_load_5x5__19) { + values ("45.5, 45.5, 45.5, 48.7, 54.8", \ + "51.3, 51.3, 51.3, 54.5, 60.7", \ + "62.4, 62.4, 62.4, 65.6, 71.7", \ + "84.1, 84.1, 84.1, 87.3, 93.5", \ + "126.8, 126.8, 126.8, 129.9, 136.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("64.5, 64.5, 64.5, 68.1, 74.2", \ + "63.7, 63.7, 63.7, 67.4, 73.6", \ + "55.9, 55.9, 55.9, 59.6, 66.0", \ + "32.3, 32.3, 32.3, 36.0, 42.8", \ + "-23.5, -23.5, -23.5, -19.6, -12.6"); + } + rise_transition (inslew_load_5x5__19) { + values ("14.3, 14.3, 14.3, 17.2, 22.9", \ + "15.2, 15.2, 15.2, 18.2, 23.9", \ + "16.9, 16.9, 16.9, 19.9, 25.7", \ + "20.1, 20.1, 20.1, 23.1, 29.0", \ + "26.0, 26.0, 26.0, 29.2, 35.1"); + } + cell_fall (inslew_load_5x5__19) { + values ("143.1, 143.1, 143.1, 147.4, 155.2", \ + "165.2, 165.2, 165.2, 169.4, 177.4", \ + "203.4, 203.4, 203.4, 207.7, 215.8", \ + "272.6, 272.6, 272.6, 276.9, 285.2", \ + "403.9, 403.9, 403.9, 408.2, 416.7"); + } + fall_transition (inslew_load_5x5__19) { + values ("44.2, 44.2, 44.2, 47.4, 53.5", \ + "50.1, 50.1, 50.1, 53.3, 59.4", \ + "61.5, 61.5, 61.5, 64.6, 70.8", \ + "83.5, 83.5, 83.5, 86.7, 92.9", \ + "126.7, 126.7, 126.7, 129.9, 136.2"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("61.8, 61.8, 61.8, 65.5, 71.5", \ + "59.4, 59.4, 59.4, 63.1, 69.3", \ + "48.0, 48.0, 48.0, 51.7, 58.1", \ + "17.3, 17.3, 17.3, 21.1, 27.7", \ + "-53.3, -53.3, -53.3, -49.4, -42.5"); + } + rise_transition (inslew_load_5x5__19) { + values ("14.1, 14.1, 14.1, 17.0, 22.7", \ + "14.9, 14.9, 14.9, 17.9, 23.6", \ + "16.4, 16.4, 16.4, 19.4, 25.2", \ + "19.2, 19.2, 19.2, 22.3, 28.1", \ + "24.4, 24.4, 24.4, 27.6, 33.5"); + } + cell_fall (inslew_load_5x5__19) { + values ("138.4, 138.4, 138.4, 142.6, 150.5", \ + "163.9, 163.9, 163.9, 168.1, 176.1", \ + "207.2, 207.2, 207.2, 211.5, 219.6", \ + "285.1, 285.1, 285.1, 289.4, 297.7", \ + "433.4, 433.4, 433.4, 437.7, 446.2"); + } + fall_transition (inslew_load_5x5__19) { + values ("42.7, 42.7, 42.7, 45.9, 52.0", \ + "48.9, 48.9, 48.9, 52.0, 58.2", \ + "60.4, 60.4, 60.4, 63.6, 69.8", \ + "82.6, 82.6, 82.6, 85.7, 92.0", \ + "126.0, 126.0, 126.0, 129.2, 135.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__19) { + values ("1712.4, 1712.4, 1712.4, 1825.2, 2051.0", \ + "1907.6, 1907.6, 1907.6, 2020.4, 2246.2", \ + "2292.6, 2292.6, 2292.6, 2405.5, 2631.3", \ + "3054.8, 3054.8, 3054.8, 3167.6, 3393.4", \ + "4567.8, 4567.8, 4567.8, 4680.7, 4906.5"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("2767.8, 2767.8, 2767.8, 2880.7, 3106.5", \ + "3140.9, 3140.9, 3140.9, 3253.8, 3479.6", \ + "3883.0, 3883.0, 3883.0, 3995.9, 4221.7", \ + "5363.6, 5363.6, 5363.6, 5476.5, 5702.2", \ + "8297.8, 8297.8, 8297.8, 8410.7, 8636.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__19) { + values ("1647.7, 1647.7, 1647.7, 1760.6, 1986.4", \ + "1792.4, 1792.4, 1792.4, 1905.3, 2131.1", \ + "2076.2, 2076.2, 2076.2, 2189.1, 2414.9", \ + "2634.3, 2634.3, 2634.3, 2747.2, 2973.0", \ + "3740.9, 3740.9, 3740.9, 3853.8, 4079.6"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("2682.3, 2682.3, 2682.3, 2795.1, 3020.9", \ + "3064.6, 3064.6, 3064.6, 3177.5, 3403.2", \ + "3813.0, 3813.0, 3813.0, 3925.9, 4151.7", \ + "5302.6, 5302.6, 5302.6, 5415.5, 5641.3", \ + "8266.3, 8266.3, 8266.3, 8379.2, 8605.0"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__19) { + values ("1597.5, 1597.5, 1597.5, 1710.4, 1936.2", \ + "1711.6, 1711.6, 1711.6, 1824.5, 2050.3", \ + "1933.3, 1933.3, 1933.3, 2046.2, 2271.9", \ + "2369.4, 2369.4, 2369.4, 2482.3, 2708.1", \ + "3229.9, 3229.9, 3229.9, 3342.8, 3568.5"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("2582.9, 2582.9, 2582.9, 2695.8, 2921.6", \ + "2963.5, 2963.5, 2963.5, 3076.3, 3302.1", \ + "3710.4, 3710.4, 3710.4, 3823.2, 4049.0", \ + "5187.6, 5187.6, 5187.6, 5300.5, 5526.3", \ + "8122.9, 8122.9, 8122.9, 8235.8, 8461.6"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__19) { + values ("1545.7, 1545.7, 1545.7, 1658.6, 1884.3", \ + "1639.9, 1639.9, 1639.9, 1752.7, 1978.5", \ + "1821.0, 1821.0, 1821.0, 1933.8, 2159.6", \ + "2175.7, 2175.7, 2175.7, 2288.5, 2514.3", \ + "2873.6, 2873.6, 2873.6, 2986.5, 3212.2"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("2477.3, 2477.3, 2477.3, 2590.2, 2816.0", \ + "2859.0, 2859.0, 2859.0, 2971.9, 3197.7", \ + "3598.8, 3598.8, 3598.8, 3711.7, 3937.5", \ + "5052.7, 5052.7, 5052.7, 5165.5, 5391.3", \ + "7942.0, 7942.0, 7942.0, 8054.9, 8280.6"); + } + } + } + } + + cell (nao22_x1) { + area : 0.0 ; + cell_leakage_power : 0.0062 ; + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 0.0091 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 0.0049 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 0.0098 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.00081 ; + } + pin (i2) { + direction : input ; + capacitance : 29.79 ; + } + pin (i1) { + direction : input ; + capacitance : 22.90 ; + } + pin (i0) { + direction : input ; + capacitance : 22.20 ; + } + pin (nq) { + function : "(!(i2) | (!(i1) & !(i0)))" ; + direction : output ; + capacitance : 9.24 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("9.7, 9.7, 9.7, 17.1, 30.2", \ + "4.4, 4.4, 4.4, 12.8, 27.7", \ + "-7.8, -7.8, -7.8, 1.6, 18.8", \ + "-33.7, -33.7, -33.7, -23.3, -4.0", \ + "-86.2, -86.2, -86.2, -75.3, -54.3"); + } + rise_transition (inslew_load_5x5__20) { + values ("29.4, 29.4, 29.4, 39.3, 59.1", \ + "42.5, 42.5, 42.5, 52.7, 72.5", \ + "68.3, 68.3, 68.3, 78.7, 99.2", \ + "119.4, 119.4, 119.4, 130.1, 151.2", \ + "221.4, 221.4, 221.4, 232.4, 253.9"); + } + cell_fall (inslew_load_5x5__20) { + values ("25.5, 25.5, 25.5, 34.4, 50.6", \ + "36.9, 36.9, 36.9, 46.7, 64.7", \ + "58.0, 58.0, 58.0, 68.3, 88.0", \ + "98.8, 98.8, 98.8, 109.6, 130.5", \ + "180.0, 180.0, 180.0, 191.0, 212.6"); + } + fall_transition (inslew_load_5x5__20) { + values ("36.9, 36.9, 36.9, 46.5, 65.4", \ + "63.3, 63.3, 63.3, 73.2, 92.4", \ + "114.7, 114.7, 114.7, 124.7, 144.4", \ + "216.6, 216.6, 216.6, 226.7, 246.7", \ + "419.9, 419.9, 419.9, 430.0, 450.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("12.0, 12.0, 12.0, 21.4, 37.0", \ + "11.7, 11.7, 11.7, 22.5, 40.9", \ + "9.8, 9.8, 9.8, 21.7, 43.0", \ + "5.0, 5.0, 5.0, 17.6, 41.3", \ + "-5.0, -5.0, -5.0, 8.1, 33.3"); + } + rise_transition (inslew_load_5x5__20) { + values ("27.4, 27.4, 27.4, 38.4, 59.6", \ + "44.5, 44.5, 44.5, 56.0, 78.0", \ + "78.1, 78.1, 78.1, 90.0, 112.9", \ + "144.6, 144.6, 144.6, 156.8, 180.5", \ + "277.4, 277.4, 277.4, 289.7, 314.0"); + } + cell_fall (inslew_load_5x5__20) { + values ("17.2, 17.2, 17.2, 27.0, 44.0", \ + "21.6, 21.6, 21.6, 32.5, 52.0", \ + "28.7, 28.7, 28.7, 40.6, 62.4", \ + "42.1, 42.1, 42.1, 54.5, 78.1", \ + "68.2, 68.2, 68.2, 81.0, 105.7"); + } + fall_transition (inslew_load_5x5__20) { + values ("28.7, 28.7, 28.7, 38.5, 57.6", \ + "48.9, 48.9, 48.9, 59.1, 78.7", \ + "88.2, 88.2, 88.2, 98.6, 118.9", \ + "166.0, 166.0, 166.0, 176.6, 197.4", \ + "321.2, 321.2, 321.2, 331.9, 353.1"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("7.5, 7.5, 7.5, 13.3, 23.2", \ + "4.6, 4.6, 4.6, 11.4, 23.3", \ + "-2.2, -2.2, -2.2, 5.3, 19.2", \ + "-16.8, -16.8, -16.8, -8.6, 6.7", \ + "-46.3, -46.3, -46.3, -37.8, -21.3"); + } + rise_transition (inslew_load_5x5__20) { + values ("20.0, 20.0, 20.0, 25.7, 36.6", \ + "32.4, 32.4, 32.4, 38.4, 49.9", \ + "56.9, 56.9, 56.9, 63.1, 75.2", \ + "105.5, 105.5, 105.5, 111.9, 124.4", \ + "202.5, 202.5, 202.5, 209.1, 222.0"); + } + cell_fall (inslew_load_5x5__20) { + values ("22.1, 22.1, 22.1, 30.1, 44.9", \ + "28.9, 28.9, 28.9, 37.4, 53.4", \ + "41.4, 41.4, 41.4, 50.4, 67.6", \ + "65.9, 65.9, 65.9, 75.2, 93.2", \ + "114.4, 114.4, 114.4, 123.9, 142.5"); + } + fall_transition (inslew_load_5x5__20) { + values ("38.0, 38.0, 38.0, 47.4, 66.0", \ + "62.3, 62.3, 62.3, 71.6, 90.2", \ + "109.9, 109.9, 109.9, 119.3, 138.0", \ + "204.8, 204.8, 204.8, 214.2, 233.1", \ + "394.2, 394.2, 394.2, 403.8, 422.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__20) { + values ("276.0, 276.0, 276.0, 391.4, 622.4", \ + "368.5, 368.5, 368.5, 484.0, 715.0", \ + "553.7, 553.7, 553.7, 669.2, 900.1", \ + "923.9, 923.9, 923.9, 1039.4, 1270.4", \ + "1664.5, 1664.5, 1664.5, 1780.0, 2011.0"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("368.7, 368.7, 368.7, 484.2, 715.2", \ + "580.2, 580.2, 580.2, 695.7, 926.7", \ + "1003.3, 1003.3, 1003.3, 1118.8, 1349.8", \ + "1849.6, 1849.6, 1849.6, 1965.0, 2196.0", \ + "3542.0, 3542.0, 3542.0, 3657.5, 3888.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__20) { + values ("222.1, 222.1, 222.1, 337.6, 568.6", \ + "328.7, 328.7, 328.7, 444.2, 675.2", \ + "541.9, 541.9, 541.9, 657.4, 888.3", \ + "968.2, 968.2, 968.2, 1083.7, 1314.7", \ + "1821.0, 1821.0, 1821.0, 1936.4, 2167.4"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("261.2, 261.2, 261.2, 376.7, 607.7", \ + "406.9, 406.9, 406.9, 522.3, 753.3", \ + "698.2, 698.2, 698.2, 813.7, 1044.7", \ + "1280.9, 1280.9, 1280.9, 1396.4, 1627.4", \ + "2446.4, 2446.4, 2446.4, 2561.9, 2792.9"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__20) { + values ("293.0, 293.0, 293.0, 408.5, 639.5", \ + "427.8, 427.8, 427.8, 543.3, 774.3", \ + "697.4, 697.4, 697.4, 812.9, 1043.9", \ + "1236.5, 1236.5, 1236.5, 1352.0, 1583.0", \ + "2314.8, 2314.8, 2314.8, 2430.3, 2661.3"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("407.5, 407.5, 407.5, 523.0, 754.0", \ + "628.0, 628.0, 628.0, 743.5, 974.5", \ + "1069.1, 1069.1, 1069.1, 1184.6, 1415.6", \ + "1951.2, 1951.2, 1951.2, 2066.7, 2297.7", \ + "3715.5, 3715.5, 3715.5, 3831.0, 4062.0"); + } + } + } + } + + cell (nao22_x4) { + area : 0.0 ; + cell_leakage_power : 0.011 ; + leakage_power () { + when : "((i0 | i1) & i2)" ; + value : 0.002 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 0.014 ; + } + leakage_power () { + when : "((i0 & i1 & !(i2)) | (!(i0) & !(i1) & i2))" ; + value : 0.015 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.012 ; + } + pin (i2) { + direction : input ; + capacitance : 26.37 ; + } + pin (i1) { + direction : input ; + capacitance : 30.76 ; + } + pin (i0) { + direction : input ; + capacitance : 29.69 ; + } + pin (nq) { + function : "(!(i2) | (!(i0) & !(i1)))" ; + direction : output ; + capacitance : 8.97 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("110.9, 110.9, 110.9, 114.7, 121.6", \ + "111.6, 111.6, 111.6, 115.5, 122.4", \ + "107.5, 107.5, 107.5, 111.4, 118.5", \ + "91.2, 91.2, 91.2, 95.3, 102.6", \ + "48.7, 48.7, 48.7, 53.0, 60.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("24.8, 24.8, 24.8, 27.9, 33.8", \ + "26.2, 26.2, 26.2, 29.3, 35.2", \ + "28.9, 28.9, 28.9, 32.1, 38.0", \ + "34.3, 34.3, 34.3, 37.4, 43.4", \ + "44.6, 44.6, 44.6, 47.7, 53.8"); + } + cell_fall (inslew_load_5x5__21) { + values ("127.0, 127.0, 127.0, 131.1, 138.8", \ + "146.3, 146.3, 146.3, 150.4, 158.2", \ + "176.5, 176.5, 176.5, 180.7, 188.5", \ + "226.8, 226.8, 226.8, 231.1, 239.1", \ + "316.0, 316.0, 316.0, 320.2, 328.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("34.2, 34.2, 34.2, 37.3, 43.3", \ + "37.6, 37.6, 37.6, 40.7, 46.7", \ + "43.9, 43.9, 43.9, 47.0, 53.0", \ + "55.5, 55.5, 55.5, 58.6, 64.8", \ + "77.7, 77.7, 77.7, 80.9, 87.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("118.5, 118.5, 118.5, 122.3, 129.2", \ + "127.0, 127.0, 127.0, 130.9, 137.9", \ + "135.1, 135.1, 135.1, 139.1, 146.3", \ + "141.2, 141.2, 141.2, 145.3, 152.7", \ + "142.1, 142.1, 142.1, 146.4, 154.2"); + } + rise_transition (inslew_load_5x5__21) { + values ("24.9, 24.9, 24.9, 28.0, 33.9", \ + "26.8, 26.8, 26.8, 30.0, 35.9", \ + "30.5, 30.5, 30.5, 33.6, 39.6", \ + "37.5, 37.5, 37.5, 40.6, 46.6", \ + "50.9, 50.9, 50.9, 54.0, 60.1"); + } + cell_fall (inslew_load_5x5__21) { + values ("119.0, 119.0, 119.0, 123.1, 130.8", \ + "132.1, 132.1, 132.1, 136.2, 143.9", \ + "149.6, 149.6, 149.6, 153.7, 161.5", \ + "174.1, 174.1, 174.1, 178.3, 186.2", \ + "211.2, 211.2, 211.2, 215.4, 223.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("33.2, 33.2, 33.2, 36.3, 42.2", \ + "35.9, 35.9, 35.9, 39.0, 45.0", \ + "40.9, 40.9, 40.9, 44.0, 50.0", \ + "50.1, 50.1, 50.1, 53.2, 59.3", \ + "67.5, 67.5, 67.5, 70.6, 76.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("95.1, 95.1, 95.1, 98.9, 105.6", \ + "99.4, 99.4, 99.4, 103.2, 110.0", \ + "100.6, 100.6, 100.6, 104.5, 111.4", \ + "94.9, 94.9, 94.9, 98.9, 106.1", \ + "74.4, 74.4, 74.4, 78.6, 86.1"); + } + rise_transition (inslew_load_5x5__21) { + values ("22.0, 22.0, 22.0, 25.2, 31.0", \ + "23.4, 23.4, 23.4, 26.6, 32.4", \ + "26.0, 26.0, 26.0, 29.1, 35.1", \ + "31.1, 31.1, 31.1, 34.2, 40.2", \ + "41.1, 41.1, 41.1, 44.2, 50.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("122.0, 122.0, 122.0, 126.1, 133.8", \ + "135.0, 135.0, 135.0, 139.1, 146.9", \ + "155.7, 155.7, 155.7, 159.9, 167.7", \ + "189.4, 189.4, 189.4, 193.6, 201.5", \ + "248.4, 248.4, 248.4, 252.7, 260.9"); + } + fall_transition (inslew_load_5x5__21) { + values ("34.4, 34.4, 34.4, 37.5, 43.5", \ + "37.5, 37.5, 37.5, 40.6, 46.6", \ + "43.3, 43.3, 43.3, 46.4, 52.5", \ + "54.3, 54.3, 54.3, 57.4, 63.5", \ + "75.5, 75.5, 75.5, 78.6, 84.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1723.4, 1723.4, 1723.4, 1835.5, 2059.6", \ + "1824.6, 1824.6, 1824.6, 1936.7, 2160.9", \ + "2025.7, 2025.7, 2025.7, 2137.8, 2361.9", \ + "2419.1, 2419.1, 2419.1, 2531.2, 2755.3", \ + "3195.6, 3195.6, 3195.6, 3307.7, 3531.9"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1980.4, 1980.4, 1980.4, 2092.5, 2316.7", \ + "2197.8, 2197.8, 2197.8, 2309.9, 2534.0", \ + "2620.3, 2620.3, 2620.3, 2732.4, 2956.6", \ + "3445.5, 3445.5, 3445.5, 3557.6, 3781.7", \ + "5072.0, 5072.0, 5072.0, 5184.0, 5408.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1699.6, 1699.6, 1699.6, 1811.7, 2035.8", \ + "1830.7, 1830.7, 1830.7, 1942.8, 2167.0", \ + "2082.4, 2082.4, 2082.4, 2194.5, 2418.6", \ + "2572.4, 2572.4, 2572.4, 2684.5, 2908.7", \ + "3537.9, 3537.9, 3537.9, 3650.0, 3874.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1890.9, 1890.9, 1890.9, 2003.0, 2227.1", \ + "2054.0, 2054.0, 2054.0, 2166.1, 2390.2", \ + "2366.9, 2366.9, 2366.9, 2479.0, 2703.2", \ + "2975.1, 2975.1, 2975.1, 3087.2, 3311.4", \ + "4170.0, 4170.0, 4170.0, 4282.1, 4506.2"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1618.5, 1618.5, 1618.5, 1730.6, 1954.7", \ + "1740.5, 1740.5, 1740.5, 1852.5, 2076.7", \ + "1976.5, 1976.5, 1976.5, 2088.6, 2312.8", \ + "2442.9, 2442.9, 2442.9, 2554.9, 2779.1", \ + "3367.3, 3367.3, 3367.3, 3479.4, 3703.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2013.2, 2013.2, 2013.2, 2125.3, 2349.4", \ + "2226.0, 2226.0, 2226.0, 2338.0, 2562.2", \ + "2646.1, 2646.1, 2646.1, 2758.2, 2982.4", \ + "3473.1, 3473.1, 3473.1, 3585.2, 3809.4", \ + "5114.2, 5114.2, 5114.2, 5226.2, 5450.4"); + } + } + } + } + + cell (nao2o22_x1) { + area : 0.0 ; + cell_leakage_power : 0.011 ; + leakage_power () { + when : "(!(i3) & !(i2) & i1 & i0)" ; + value : 0.017 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & !(i3))" ; + value : 0.0092 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 0.018 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3))" ; + value : 0.0099 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0015 ; + } + pin (i3) { + direction : input ; + capacitance : 27.17 ; + } + pin (i2) { + direction : input ; + capacitance : 22.09 ; + } + pin (i1) { + direction : input ; + capacitance : 26.89 ; + } + pin (i0) { + direction : input ; + capacitance : 22.52 ; + } + pin (nq) { + function : "((!(i3) & !(i2)) | (!(i1) & !(i0)))" ; + direction : output ; + capacitance : 9.50 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("8.1, 8.1, 8.1, 15.1, 27.7", \ + "1.2, 1.2, 1.2, 9.4, 23.8", \ + "-14.4, -14.4, -14.4, -5.0, 11.8", \ + "-47.3, -47.3, -47.3, -36.9, -17.7", \ + "-114.1, -114.1, -114.1, -103.0, -81.9"); + } + rise_transition (inslew_load_5x5__22) { + values ("27.4, 27.4, 27.4, 36.8, 55.4", \ + "38.9, 38.9, 38.9, 48.6, 67.2", \ + "61.4, 61.4, 61.4, 71.4, 90.7", \ + "105.9, 105.9, 105.9, 116.2, 136.2", \ + "194.5, 194.5, 194.5, 205.0, 225.7"); + } + cell_fall (inslew_load_5x5__22) { + values ("28.6, 28.6, 28.6, 38.0, 55.2", \ + "42.7, 42.7, 42.7, 53.0, 71.9", \ + "68.8, 68.8, 68.8, 79.6, 100.2", \ + "119.4, 119.4, 119.4, 130.6, 152.4", \ + "219.9, 219.9, 219.9, 231.4, 253.9"); + } + fall_transition (inslew_load_5x5__22) { + values ("39.9, 39.9, 39.9, 50.3, 70.9", \ + "68.9, 68.9, 68.9, 79.5, 100.3", \ + "125.0, 125.0, 125.0, 135.7, 156.9", \ + "236.0, 236.0, 236.0, 246.9, 268.4", \ + "457.5, 457.5, 457.5, 468.4, 490.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("9.8, 9.8, 9.8, 18.9, 34.0", \ + "7.1, 7.1, 7.1, 17.7, 35.8", \ + "0.2, 0.2, 0.2, 12.2, 33.3", \ + "-14.5, -14.5, -14.5, -1.6, 22.1", \ + "-44.5, -44.5, -44.5, -31.1, -5.4"); + } + rise_transition (inslew_load_5x5__22) { + values ("25.1, 25.1, 25.1, 35.6, 55.5", \ + "40.0, 40.0, 40.0, 50.9, 71.8", \ + "69.0, 69.0, 69.0, 80.4, 102.3", \ + "126.6, 126.6, 126.6, 138.4, 161.2", \ + "241.5, 241.5, 241.5, 253.5, 277.0"); + } + cell_fall (inslew_load_5x5__22) { + values ("19.9, 19.9, 19.9, 30.2, 48.3", \ + "27.2, 27.2, 27.2, 38.6, 58.9", \ + "39.9, 39.9, 39.9, 52.1, 74.6", \ + "64.1, 64.1, 64.1, 76.8, 101.1", \ + "112.1, 112.1, 112.1, 125.1, 150.4"); + } + fall_transition (inslew_load_5x5__22) { + values ("31.0, 31.0, 31.0, 41.7, 62.3", \ + "53.8, 53.8, 53.8, 64.7, 85.9", \ + "97.8, 97.8, 97.8, 109.0, 130.7", \ + "185.0, 185.0, 185.0, 196.3, 218.6", \ + "358.9, 358.9, 358.9, 370.3, 392.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("13.1, 13.1, 13.1, 19.7, 31.8", \ + "9.6, 9.6, 9.6, 17.0, 30.6", \ + "0.9, 0.9, 0.9, 9.2, 24.6", \ + "-17.8, -17.8, -17.8, -8.8, 8.3", \ + "-56.1, -56.1, -56.1, -46.6, -28.3"); + } + rise_transition (inslew_load_5x5__22) { + values ("33.9, 33.9, 33.9, 43.1, 61.6", \ + "48.8, 48.8, 48.8, 58.2, 76.6", \ + "78.1, 78.1, 78.1, 87.7, 106.6", \ + "136.2, 136.2, 136.2, 146.1, 165.4", \ + "252.3, 252.3, 252.3, 262.3, 282.0"); + } + cell_fall (inslew_load_5x5__22) { + values ("30.0, 30.0, 30.0, 38.2, 53.9", \ + "39.6, 39.6, 39.6, 48.4, 65.1", \ + "57.4, 57.4, 57.4, 66.7, 84.5", \ + "92.0, 92.0, 92.0, 101.6, 120.3", \ + "160.7, 160.7, 160.7, 170.5, 192.0"); + } + fall_transition (inslew_load_5x5__22) { + values ("46.8, 46.8, 46.8, 57.0, 77.3", \ + "73.7, 73.7, 73.7, 83.8, 104.0", \ + "126.6, 126.6, 126.6, 136.8, 157.0", \ + "231.8, 231.8, 231.8, 242.0, 262.4", \ + "441.9, 441.9, 441.9, 452.1, 474.9"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("16.4, 16.4, 16.4, 24.6, 38.8", \ + "18.5, 18.5, 18.5, 27.9, 44.5", \ + "21.0, 21.0, 21.0, 31.4, 50.4", \ + "25.0, 25.0, 25.0, 36.0, 56.9", \ + "32.3, 32.3, 32.3, 43.7, 65.9"); + } + rise_transition (inslew_load_5x5__22) { + values ("32.5, 32.5, 32.5, 42.7, 62.4", \ + "51.8, 51.8, 51.8, 62.3, 82.7", \ + "89.5, 89.5, 89.5, 100.3, 121.4", \ + "164.2, 164.2, 164.2, 175.3, 197.1", \ + "313.4, 313.4, 313.4, 324.6, 346.8"); + } + cell_fall (inslew_load_5x5__22) { + values ("21.5, 21.5, 21.5, 30.2, 46.4", \ + "24.1, 24.1, 24.1, 33.7, 51.4", \ + "27.9, 27.9, 27.9, 38.2, 57.6", \ + "34.3, 34.3, 34.3, 45.1, 66.0", \ + "46.4, 46.4, 46.4, 57.6, 79.5"); + } + fall_transition (inslew_load_5x5__22) { + values ("37.0, 37.0, 37.0, 47.2, 67.5", \ + "56.9, 56.9, 56.9, 67.1, 87.4", \ + "95.8, 95.8, 95.8, 106.2, 126.8", \ + "173.2, 173.2, 173.2, 183.8, 204.6", \ + "327.7, 327.7, 327.7, 338.3, 359.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__22) { + values ("276.2, 276.2, 276.2, 395.0, 632.5", \ + "359.1, 359.1, 359.1, 477.9, 715.4", \ + "524.9, 524.9, 524.9, 643.7, 881.2", \ + "856.5, 856.5, 856.5, 975.3, 1212.8", \ + "1519.7, 1519.7, 1519.7, 1638.5, 1876.0"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("391.2, 391.2, 391.2, 510.0, 747.5", \ + "615.3, 615.3, 615.3, 734.0, 971.5", \ + "1063.4, 1063.4, 1063.4, 1182.1, 1419.6", \ + "1959.6, 1959.6, 1959.6, 2078.3, 2315.8", \ + "3752.0, 3752.0, 3752.0, 3870.7, 4108.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__22) { + values ("213.7, 213.7, 213.7, 332.5, 569.9", \ + "308.7, 308.7, 308.7, 427.4, 664.9", \ + "498.6, 498.6, 498.6, 617.4, 854.9", \ + "878.5, 878.5, 878.5, 997.3, 1234.8", \ + "1638.3, 1638.3, 1638.3, 1757.1, 1994.6"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("279.9, 279.9, 279.9, 398.7, 636.1", \ + "441.1, 441.1, 441.1, 559.8, 797.3", \ + "763.4, 763.4, 763.4, 882.2, 1119.7", \ + "1408.1, 1408.1, 1408.1, 1526.9, 1764.3", \ + "2697.5, 2697.5, 2697.5, 2816.2, 3053.7"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__22) { + values ("363.7, 363.7, 363.7, 482.5, 720.0", \ + "485.8, 485.8, 485.8, 604.5, 842.0", \ + "729.8, 729.8, 729.8, 848.5, 1086.0", \ + "1217.9, 1217.9, 1217.9, 1336.6, 1574.1", \ + "2194.0, 2194.0, 2194.0, 2312.8, 2550.3"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("493.9, 493.9, 493.9, 612.6, 850.1", \ + "731.5, 731.5, 731.5, 850.3, 1087.8", \ + "1206.8, 1206.8, 1206.8, 1325.6, 1563.1", \ + "2157.4, 2157.4, 2157.4, 2276.2, 2513.7", \ + "4058.6, 4058.6, 4058.6, 4177.4, 4414.8"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__22) { + values ("305.3, 305.3, 305.3, 424.0, 661.5", \ + "443.4, 443.4, 443.4, 562.1, 799.6", \ + "719.7, 719.7, 719.7, 838.4, 1075.9", \ + "1272.2, 1272.2, 1272.2, 1391.0, 1628.4", \ + "2377.3, 2377.3, 2377.3, 2496.0, 2733.5"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("366.8, 366.8, 366.8, 485.5, 723.0", \ + "525.8, 525.8, 525.8, 644.5, 882.0", \ + "843.8, 843.8, 843.8, 962.5, 1200.0", \ + "1479.7, 1479.7, 1479.7, 1598.5, 1836.0", \ + "2751.6, 2751.6, 2751.6, 2870.4, 3107.9"); + } + } + } + } + + cell (nao2o22_x4) { + area : 0.0 ; + cell_leakage_power : 0.016 ; + leakage_power () { + when : "(!(i3) & !(i2) & i1 & i0)" ; + value : 0.023 ; + } + leakage_power () { + when : "((i0 | i1) & (i2 | i3))" ; + value : 0.0045 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 0.024 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))))" ; + value : 0.018 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.013 ; + } + pin (i3) { + direction : input ; + capacitance : 28.18 ; + } + pin (i2) { + direction : input ; + capacitance : 31.86 ; + } + pin (i1) { + direction : input ; + capacitance : 29.01 ; + } + pin (i0) { + direction : input ; + capacitance : 23.23 ; + } + pin (nq) { + function : "(!((i0 | i1)) | (!(i2) & !(i3)))" ; + direction : output ; + capacitance : 8.97 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("81.2, 81.2, 81.2, 84.9, 91.2", \ + "80.8, 80.8, 80.8, 84.5, 91.0", \ + "75.3, 75.3, 75.3, 79.0, 85.7", \ + "57.0, 57.0, 57.0, 60.8, 67.7", \ + "11.8, 11.8, 11.8, 15.8, 23.1"); + } + rise_transition (inslew_load_5x5__21) { + values ("16.3, 16.3, 16.3, 19.3, 25.0", \ + "17.5, 17.5, 17.5, 20.5, 26.2", \ + "19.8, 19.8, 19.8, 22.8, 28.6", \ + "24.1, 24.1, 24.1, 27.2, 33.1", \ + "32.4, 32.4, 32.4, 35.5, 41.5"); + } + cell_fall (inslew_load_5x5__21) { + values ("129.0, 129.0, 129.0, 133.1, 140.8", \ + "149.1, 149.1, 149.1, 153.3, 161.1", \ + "181.3, 181.3, 181.3, 185.5, 193.4", \ + "237.3, 237.3, 237.3, 241.5, 249.7", \ + "340.5, 340.5, 340.5, 344.8, 353.1"); + } + fall_transition (inslew_load_5x5__21) { + values ("36.9, 36.9, 36.9, 40.0, 46.0", \ + "41.4, 41.4, 41.4, 44.5, 50.6", \ + "49.9, 49.9, 49.9, 53.0, 59.1", \ + "66.2, 66.2, 66.2, 69.4, 75.5", \ + "98.0, 98.0, 98.0, 101.1, 107.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("88.9, 88.9, 88.9, 92.6, 98.9", \ + "96.0, 96.0, 96.0, 99.7, 106.3", \ + "102.2, 102.2, 102.2, 105.9, 112.6", \ + "105.2, 105.2, 105.2, 109.1, 116.0", \ + "101.7, 101.7, 101.7, 105.8, 113.2"); + } + rise_transition (inslew_load_5x5__21) { + values ("16.4, 16.4, 16.4, 19.4, 25.1", \ + "18.0, 18.0, 18.0, 21.1, 26.8", \ + "21.0, 21.0, 21.0, 24.0, 29.9", \ + "26.5, 26.5, 26.5, 29.6, 35.5", \ + "37.1, 37.1, 37.1, 40.2, 46.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("121.0, 121.0, 121.0, 125.1, 132.8", \ + "134.1, 134.1, 134.1, 138.3, 146.0", \ + "152.0, 152.0, 152.0, 156.2, 164.0", \ + "178.3, 178.3, 178.3, 182.6, 190.6", \ + "221.0, 221.0, 221.0, 225.2, 233.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("35.6, 35.6, 35.6, 38.7, 44.7", \ + "39.1, 39.1, 39.1, 42.3, 48.3", \ + "45.7, 45.7, 45.7, 48.9, 54.9", \ + "58.3, 58.3, 58.3, 61.4, 67.6", \ + "82.6, 82.6, 82.6, 85.8, 92.0"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("87.0, 87.0, 87.0, 90.7, 97.1", \ + "89.8, 89.8, 89.8, 93.5, 100.1", \ + "90.8, 90.8, 90.8, 94.5, 101.3", \ + "86.2, 86.2, 86.2, 90.1, 97.1", \ + "69.4, 69.4, 69.4, 73.5, 81.0"); + } + rise_transition (inslew_load_5x5__21) { + values ("17.0, 17.0, 17.0, 20.0, 25.8", \ + "18.5, 18.5, 18.5, 21.5, 27.3", \ + "21.4, 21.4, 21.4, 24.5, 30.3", \ + "26.9, 26.9, 26.9, 30.0, 36.0", \ + "37.7, 37.7, 37.7, 40.7, 46.8"); + } + cell_fall (inslew_load_5x5__21) { + values ("129.2, 129.2, 129.2, 133.4, 141.1", \ + "142.9, 142.9, 142.9, 147.1, 154.9", \ + "165.2, 165.2, 165.2, 169.5, 177.3", \ + "203.2, 203.2, 203.2, 207.5, 215.6", \ + "271.9, 271.9, 271.9, 276.2, 284.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("38.0, 38.0, 38.0, 41.1, 47.1", \ + "41.9, 41.9, 41.9, 45.0, 51.1", \ + "49.7, 49.7, 49.7, 52.8, 58.9", \ + "64.7, 64.7, 64.7, 67.9, 74.0", \ + "94.2, 94.2, 94.2, 97.3, 103.5"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("95.3, 95.3, 95.3, 99.0, 105.4", \ + "106.1, 106.1, 106.1, 109.9, 116.5", \ + "120.5, 120.5, 120.5, 124.3, 131.1", \ + "140.1, 140.1, 140.1, 144.0, 151.2", \ + "170.6, 170.6, 170.6, 174.8, 182.4"); + } + rise_transition (inslew_load_5x5__21) { + values ("17.1, 17.1, 17.1, 20.2, 25.9", \ + "19.1, 19.1, 19.1, 22.2, 27.9", \ + "22.7, 22.7, 22.7, 25.9, 31.7", \ + "29.6, 29.6, 29.6, 32.7, 38.7", \ + "42.9, 42.9, 42.9, 45.9, 52.0"); + } + cell_fall (inslew_load_5x5__21) { + values ("120.8, 120.8, 120.8, 124.9, 132.6", \ + "127.7, 127.7, 127.7, 131.9, 139.6", \ + "135.9, 135.9, 135.9, 140.1, 147.9", \ + "144.5, 144.5, 144.5, 148.7, 156.7", \ + "152.7, 152.7, 152.7, 157.0, 165.2"); + } + fall_transition (inslew_load_5x5__21) { + values ("36.5, 36.5, 36.5, 39.6, 45.6", \ + "39.5, 39.5, 39.5, 42.6, 48.6", \ + "45.2, 45.2, 45.2, 48.3, 54.4", \ + "56.3, 56.3, 56.3, 59.4, 65.5", \ + "77.6, 77.6, 77.6, 80.8, 86.9"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1684.1, 1684.1, 1684.1, 1796.1, 2020.3", \ + "1807.4, 1807.4, 1807.4, 1919.5, 2143.6", \ + "2052.8, 2052.8, 2052.8, 2164.8, 2389.0", \ + "2536.0, 2536.0, 2536.0, 2648.0, 2872.2", \ + "3490.6, 3490.6, 3490.6, 3602.7, 3826.8"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2262.7, 2262.7, 2262.7, 2374.8, 2598.9", \ + "2565.4, 2565.4, 2565.4, 2677.4, 2901.6", \ + "3153.4, 3153.4, 3153.4, 3265.5, 3489.6", \ + "4312.1, 4312.1, 4312.1, 4424.2, 4648.3", \ + "6609.1, 6609.1, 6609.1, 6721.2, 6945.4"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1654.9, 1654.9, 1654.9, 1767.0, 1991.2", \ + "1809.0, 1809.0, 1809.0, 1921.1, 2145.3", \ + "2105.8, 2105.8, 2105.8, 2217.9, 2442.1", \ + "2686.3, 2686.3, 2686.3, 2798.4, 3022.5", \ + "3833.3, 3833.3, 3833.3, 3945.4, 4169.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2145.4, 2145.4, 2145.4, 2257.5, 2481.7", \ + "2368.5, 2368.5, 2368.5, 2480.6, 2704.7", \ + "2797.8, 2797.8, 2797.8, 2909.9, 3134.0", \ + "3638.0, 3638.0, 3638.0, 3750.1, 3974.2", \ + "5297.5, 5297.5, 5297.5, 5409.6, 5633.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1790.2, 1790.2, 1790.2, 1902.3, 2126.5", \ + "1958.0, 1958.0, 1958.0, 2070.1, 2294.2", \ + "2292.0, 2292.0, 2292.0, 2404.1, 2628.2", \ + "2953.9, 2953.9, 2953.9, 3065.9, 3290.1", \ + "4267.8, 4267.8, 4267.8, 4379.8, 4604.0"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2378.4, 2378.4, 2378.4, 2490.4, 2714.6", \ + "2665.3, 2665.3, 2665.3, 2777.4, 3001.5", \ + "3236.0, 3236.0, 3236.0, 3348.0, 3572.2", \ + "4365.9, 4365.9, 4365.9, 4478.0, 4702.2", \ + "6612.5, 6612.5, 6612.5, 6724.6, 6948.8"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1761.9, 1761.9, 1761.9, 1874.0, 2098.2", \ + "1962.0, 1962.0, 1962.0, 2074.0, 2298.2", \ + "2350.9, 2350.9, 2350.9, 2463.0, 2687.1", \ + "3115.9, 3115.9, 3115.9, 3228.0, 3452.1", \ + "4632.6, 4632.6, 4632.6, 4744.7, 4968.8"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2249.7, 2249.7, 2249.7, 2361.7, 2585.9", \ + "2448.1, 2448.1, 2448.1, 2560.1, 2784.3", \ + "2840.5, 2840.5, 2840.5, 2952.6, 3176.8", \ + "3615.6, 3615.6, 3615.6, 3727.7, 3951.9", \ + "5146.9, 5146.9, 5146.9, 5259.0, 5483.2"); + } + } + } + } + + cell (nmx2_x1) { + area : 0.0 ; + cell_leakage_power : 0.0065 ; + leakage_power () { + when : "(!(i1) & i0 & cmd)" ; + value : 0.0088 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & cmd)" ; + value : 0.0046 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 0.002 ; + } + leakage_power () { + when : "(i1 & !(i0) & !(cmd))" ; + value : 0.011 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & !(cmd))" ; + value : 0.0066 ; + } + pin (i1) { + direction : input ; + capacitance : 26.15 ; + } + pin (i0) { + direction : input ; + capacitance : 18.98 ; + } + pin (cmd) { + direction : input ; + capacitance : 52.89 ; + } + pin (nq) { + function : "((!(i1) & (!(i0) | cmd)) | (!(i0) & !(cmd)))" ; + direction : output ; + capacitance : 8.64 ; + timing (maxd_nq_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__23) { + values ("50.9, 50.9, 50.9, 59.7, 74.4", \ + "60.3, 60.3, 60.3, 69.8, 85.9", \ + "74.3, 74.3, 74.3, 84.9, 102.9", \ + "98.7, 98.7, 98.7, 110.0, 130.2", \ + "144.0, 144.0, 144.0, 156.3, 178.5"); + } + rise_transition (inslew_load_5x5__23) { + values ("25.7, 25.7, 25.7, 36.0, 55.7", \ + "33.2, 33.2, 33.2, 43.8, 63.9", \ + "47.6, 47.6, 47.6, 58.4, 79.1", \ + "75.4, 75.4, 75.4, 86.5, 107.9", \ + "130.4, 130.4, 130.4, 141.8, 163.8"); + } + cell_fall (inslew_load_5x5__23) { + values ("40.1, 40.1, 40.1, 49.4, 65.5", \ + "41.7, 41.7, 41.7, 51.5, 68.3", \ + "39.2, 39.2, 39.2, 49.6, 67.7", \ + "28.5, 28.5, 28.5, 39.5, 59.3", \ + "2.3, 2.3, 2.3, 13.9, 35.3"); + } + fall_transition (inslew_load_5x5__23) { + values ("24.1, 24.1, 24.1, 33.7, 52.5", \ + "29.9, 29.9, 29.9, 39.6, 58.5", \ + "40.5, 40.5, 40.5, 50.3, 69.4", \ + "60.3, 60.3, 60.3, 70.4, 89.8", \ + "98.9, 98.9, 98.9, 109.1, 129.0"); + } + } + timing (maxd_nq_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("10.8, 10.8, 10.8, 19.7, 34.7", \ + "9.6, 9.6, 9.6, 20.0, 37.7", \ + "5.9, 5.9, 5.9, 17.4, 37.9", \ + "-2.2, -2.2, -2.2, 9.9, 32.7", \ + "-19.1, -19.1, -19.1, -6.4, 17.8"); + } + rise_transition (inslew_load_5x5__23) { + values ("26.1, 26.1, 26.1, 36.5, 56.4", \ + "42.4, 42.4, 42.4, 53.3, 74.0", \ + "74.4, 74.4, 74.4, 85.6, 107.3", \ + "137.8, 137.8, 137.8, 149.3, 171.7", \ + "264.3, 264.3, 264.3, 276.0, 299.0"); + } + cell_fall (inslew_load_5x5__23) { + values ("17.8, 17.8, 17.8, 27.5, 44.4", \ + "23.1, 23.1, 23.1, 33.8, 53.0", \ + "32.1, 32.1, 32.1, 43.6, 64.9", \ + "49.0, 49.0, 49.0, 61.1, 84.0", \ + "82.4, 82.4, 82.4, 94.7, 118.8"); + } + fall_transition (inslew_load_5x5__23) { + values ("29.1, 29.1, 29.1, 38.9, 57.8", \ + "50.2, 50.2, 50.2, 60.2, 79.6", \ + "91.0, 91.0, 91.0, 101.3, 121.3", \ + "172.0, 172.0, 172.0, 182.4, 202.9", \ + "333.4, 333.4, 333.4, 343.9, 364.7"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("12.6, 12.6, 12.6, 19.2, 31.4", \ + "10.0, 10.0, 10.0, 17.4, 31.0", \ + "3.4, 3.4, 3.4, 11.6, 26.9", \ + "-10.5, -10.5, -10.5, -1.7, 14.9", \ + "-39.0, -39.0, -39.0, -29.9, -12.2"); + } + rise_transition (inslew_load_5x5__23) { + values ("33.2, 33.2, 33.2, 42.4, 60.9", \ + "49.3, 49.3, 49.3, 58.6, 77.1", \ + "81.0, 81.0, 81.0, 90.6, 109.4", \ + "144.2, 144.2, 144.2, 153.9, 173.1", \ + "270.4, 270.4, 270.4, 280.3, 299.8"); + } + cell_fall (inslew_load_5x5__23) { + values ("24.6, 24.6, 24.6, 32.3, 46.9", \ + "32.5, 32.5, 32.5, 40.8, 56.4", \ + "47.1, 47.1, 47.1, 55.8, 72.5", \ + "75.6, 75.6, 75.6, 84.6, 102.2", \ + "132.2, 132.2, 132.2, 141.4, 159.5"); + } + fall_transition (inslew_load_5x5__23) { + values ("40.7, 40.7, 40.7, 50.0, 68.4", \ + "66.0, 66.0, 66.0, 75.3, 93.7", \ + "115.8, 115.8, 115.8, 125.1, 143.6", \ + "214.8, 214.8, 214.8, 224.2, 242.8", \ + "412.6, 412.6, 412.6, 422.0, 440.7"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("12.6, 12.6, 12.6, 19.2, 31.4", \ + "10.0, 10.0, 10.0, 17.4, 31.0", \ + "3.4, 3.4, 3.4, 11.6, 26.9", \ + "-10.5, -10.5, -10.5, -1.7, 14.9", \ + "-39.0, -39.0, -39.0, -29.9, -12.2"); + } + rise_transition (inslew_load_5x5__23) { + values ("33.2, 33.2, 33.2, 42.4, 60.9", \ + "49.3, 49.3, 49.3, 58.6, 77.1", \ + "81.0, 81.0, 81.0, 90.6, 109.4", \ + "144.2, 144.2, 144.2, 153.9, 173.1", \ + "270.4, 270.4, 270.4, 280.3, 299.8"); + } + cell_fall (inslew_load_5x5__23) { + values ("24.6, 24.6, 24.6, 32.3, 46.9", \ + "32.5, 32.5, 32.5, 40.8, 56.4", \ + "47.1, 47.1, 47.1, 55.8, 72.5", \ + "75.6, 75.6, 75.6, 84.6, 102.2", \ + "132.2, 132.2, 132.2, 141.4, 159.5"); + } + fall_transition (inslew_load_5x5__23) { + values ("40.7, 40.7, 40.7, 50.0, 68.4", \ + "66.0, 66.0, 66.0, 75.3, 93.7", \ + "115.8, 115.8, 115.8, 125.1, 143.6", \ + "214.8, 214.8, 214.8, 224.2, 242.8", \ + "412.6, 412.6, 412.6, 422.0, 440.7"); + } + } + internal_power (energy_pos_nq_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__23) { + values ("591.7, 591.7, 591.7, 699.6, 915.5", \ + "750.8, 750.8, 750.8, 858.7, 1074.6", \ + "1066.6, 1066.6, 1066.6, 1174.5, 1390.4", \ + "1695.6, 1695.6, 1695.6, 1803.6, 2019.5", \ + "2952.1, 2952.1, 2952.1, 3060.1, 3276.0"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("565.8, 565.8, 565.8, 673.7, 889.6", \ + "666.6, 666.6, 666.6, 774.6, 990.5", \ + "864.2, 864.2, 864.2, 972.2, 1188.1", \ + "1255.1, 1255.1, 1255.1, 1363.1, 1579.0", \ + "2033.4, 2033.4, 2033.4, 2141.3, 2357.2"); + } + } + internal_power (energy_neg_nq_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__23) { + values ("207.4, 207.4, 207.4, 315.4, 531.3", \ + "306.9, 306.9, 306.9, 414.8, 630.8", \ + "505.8, 505.8, 505.8, 613.8, 829.7", \ + "903.7, 903.7, 903.7, 1011.6, 1227.5", \ + "1699.4, 1699.4, 1699.4, 1807.4, 2023.3"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("253.3, 253.3, 253.3, 361.2, 577.1", \ + "398.6, 398.6, 398.6, 506.5, 722.4", \ + "689.2, 689.2, 689.2, 797.2, 1013.1", \ + "1270.5, 1270.5, 1270.5, 1378.4, 1594.3", \ + "2433.0, 2433.0, 2433.0, 2540.9, 2756.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__23) { + values ("324.6, 324.6, 324.6, 432.6, 648.5", \ + "449.3, 449.3, 449.3, 557.3, 773.2", \ + "698.8, 698.8, 698.8, 806.7, 1022.6", \ + "1197.7, 1197.7, 1197.7, 1305.6, 1521.6", \ + "2195.5, 2195.5, 2195.5, 2303.5, 2519.4"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("418.8, 418.8, 418.8, 526.8, 742.7", \ + "638.8, 638.8, 638.8, 746.8, 962.7", \ + "1078.9, 1078.9, 1078.9, 1186.9, 1402.8", \ + "1959.1, 1959.1, 1959.1, 2067.1, 2283.0", \ + "3719.5, 3719.5, 3719.5, 3827.4, 4043.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__23) { + values ("324.6, 324.6, 324.6, 432.6, 648.5", \ + "449.3, 449.3, 449.3, 557.3, 773.2", \ + "698.8, 698.8, 698.8, 806.7, 1022.6", \ + "1197.7, 1197.7, 1197.7, 1305.6, 1521.6", \ + "2195.5, 2195.5, 2195.5, 2303.5, 2519.4"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("418.8, 418.8, 418.8, 526.8, 742.7", \ + "638.8, 638.8, 638.8, 746.8, 962.7", \ + "1078.9, 1078.9, 1078.9, 1186.9, 1402.8", \ + "1959.1, 1959.1, 1959.1, 2067.1, 2283.0", \ + "3719.5, 3719.5, 3719.5, 3827.4, 4043.3"); + } + } + } + } + + cell (nmx2_x4) { + area : 0.0 ; + cell_leakage_power : 0.0099 ; + leakage_power () { + when : "(cmd & i1)" ; + value : 0.0017 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & cmd)" ; + value : 0.013 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 0.0034 ; + } + leakage_power () { + when : "(i1 & !(i0) & !(cmd))" ; + value : 0.016 ; + } + leakage_power () { + when : "(!((cmd ^ i0)) & !(i1))" ; + value : 0.015 ; + } + pin (i1) { + direction : input ; + capacitance : 22.62 ; + } + pin (i0) { + direction : input ; + capacitance : 22.51 ; + } + pin (cmd) { + direction : input ; + capacitance : 61.19 ; + } + pin (nq) { + function : "((!(i0) & (!(i1) | !(cmd))) | (!(i1) & cmd))" ; + direction : output ; + capacitance : 8.97 ; + timing (maxd_nq_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("180.1, 180.1, 180.1, 184.0, 191.1", \ + "199.7, 199.7, 199.7, 203.6, 210.7", \ + "230.8, 230.8, 230.8, 234.7, 241.9", \ + "282.4, 282.4, 282.4, 286.4, 293.8", \ + "372.6, 372.6, 372.6, 376.7, 384.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("28.1, 28.1, 28.1, 31.2, 37.1", \ + "29.1, 29.1, 29.1, 32.2, 38.2", \ + "31.0, 31.0, 31.0, 34.1, 40.1", \ + "34.6, 34.6, 34.6, 37.6, 43.7", \ + "41.1, 41.1, 41.1, 44.1, 50.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("142.1, 142.1, 142.1, 146.2, 153.7", \ + "142.4, 142.4, 142.4, 146.5, 154.0", \ + "136.2, 136.2, 136.2, 140.3, 147.9", \ + "114.9, 114.9, 114.9, 119.0, 126.6", \ + "62.3, 62.3, 62.3, 66.4, 74.1"); + } + fall_transition (inslew_load_5x5__21) { + values ("27.9, 27.9, 27.9, 31.0, 36.9", \ + "28.4, 28.4, 28.4, 31.5, 37.5", \ + "29.4, 29.4, 29.4, 32.5, 38.5", \ + "31.2, 31.2, 31.2, 34.3, 40.2", \ + "34.4, 34.4, 34.4, 37.5, 43.4"); + } + } + timing (maxd_nq_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("134.7, 134.7, 134.7, 138.6, 145.7", \ + "141.8, 141.8, 141.8, 145.7, 152.9", \ + "145.1, 145.1, 145.1, 149.1, 156.4", \ + "137.4, 137.4, 137.4, 141.6, 149.0", \ + "105.9, 105.9, 105.9, 110.2, 118.0"); + } + rise_transition (inslew_load_5x5__21) { + values ("28.0, 28.0, 28.0, 31.1, 37.0", \ + "29.9, 29.9, 29.9, 33.0, 38.9", \ + "33.3, 33.3, 33.3, 36.4, 42.4", \ + "39.6, 39.6, 39.6, 42.7, 48.8", \ + "51.4, 51.4, 51.4, 54.4, 60.5"); + } + cell_fall (inslew_load_5x5__21) { + values ("136.6, 136.6, 136.6, 140.7, 148.2", \ + "154.5, 154.5, 154.5, 158.6, 166.2", \ + "180.4, 180.4, 180.4, 184.6, 192.3", \ + "220.0, 220.0, 220.0, 224.2, 232.0", \ + "285.6, 285.6, 285.6, 289.9, 297.9"); + } + fall_transition (inslew_load_5x5__21) { + values ("29.1, 29.1, 29.1, 32.2, 38.1", \ + "31.6, 31.6, 31.6, 34.7, 40.7", \ + "36.3, 36.3, 36.3, 39.4, 45.4", \ + "44.9, 44.9, 44.9, 48.0, 54.1", \ + "61.2, 61.2, 61.2, 64.4, 70.5"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("129.1, 129.1, 129.1, 133.0, 140.0", \ + "130.6, 130.6, 130.6, 134.5, 141.6", \ + "127.8, 127.8, 127.8, 131.7, 139.0", \ + "112.4, 112.4, 112.4, 116.6, 124.0", \ + "70.2, 70.2, 70.2, 74.5, 82.2"); + } + rise_transition (inslew_load_5x5__21) { + values ("28.2, 28.2, 28.2, 31.3, 37.2", \ + "29.7, 29.7, 29.7, 32.8, 38.8", \ + "32.8, 32.8, 32.8, 35.9, 41.9", \ + "38.8, 38.8, 38.8, 41.9, 47.9", \ + "50.2, 50.2, 50.2, 53.2, 59.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("140.1, 140.1, 140.1, 144.2, 151.7", \ + "156.1, 156.1, 156.1, 160.2, 167.9", \ + "182.6, 182.6, 182.6, 186.8, 194.5", \ + "228.2, 228.2, 228.2, 232.4, 240.2", \ + "311.2, 311.2, 311.2, 315.5, 323.7"); + } + fall_transition (inslew_load_5x5__21) { + values ("30.5, 30.5, 30.5, 33.6, 39.6", \ + "33.3, 33.3, 33.3, 36.4, 42.4", \ + "38.8, 38.8, 38.8, 41.9, 47.9", \ + "49.0, 49.0, 49.0, 52.1, 58.2", \ + "69.0, 69.0, 69.0, 72.1, 78.3"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("129.1, 129.1, 129.1, 133.0, 140.0", \ + "130.6, 130.6, 130.6, 134.5, 141.6", \ + "127.8, 127.8, 127.8, 131.7, 139.0", \ + "112.4, 112.4, 112.4, 116.6, 124.0", \ + "70.2, 70.2, 70.2, 74.5, 82.2"); + } + rise_transition (inslew_load_5x5__21) { + values ("28.2, 28.2, 28.2, 31.3, 37.2", \ + "29.7, 29.7, 29.7, 32.8, 38.8", \ + "32.8, 32.8, 32.8, 35.9, 41.9", \ + "38.8, 38.8, 38.8, 41.9, 47.9", \ + "50.2, 50.2, 50.2, 53.2, 59.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("140.1, 140.1, 140.1, 144.2, 151.7", \ + "156.1, 156.1, 156.1, 160.2, 167.9", \ + "182.6, 182.6, 182.6, 186.8, 194.5", \ + "228.2, 228.2, 228.2, 232.4, 240.2", \ + "311.2, 311.2, 311.2, 315.5, 323.7"); + } + fall_transition (inslew_load_5x5__21) { + values ("30.5, 30.5, 30.5, 33.6, 39.6", \ + "33.3, 33.3, 33.3, 36.4, 42.4", \ + "38.8, 38.8, 38.8, 41.9, 47.9", \ + "49.0, 49.0, 49.0, 52.1, 58.2", \ + "69.0, 69.0, 69.0, 72.1, 78.3"); + } + } + internal_power (energy_pos_nq_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__21) { + values ("2361.6, 2361.6, 2361.6, 2473.6, 2697.8", \ + "2568.0, 2568.0, 2568.0, 2680.1, 2904.2", \ + "2971.4, 2971.4, 2971.4, 3083.5, 3307.7", \ + "3763.7, 3763.7, 3763.7, 3875.8, 4099.9", \ + "5328.3, 5328.3, 5328.3, 5440.4, 5664.6"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2232.7, 2232.7, 2232.7, 2344.8, 2568.9", \ + "2319.3, 2319.3, 2319.3, 2431.4, 2655.5", \ + "2485.6, 2485.6, 2485.6, 2597.6, 2821.8", \ + "2808.4, 2808.4, 2808.4, 2920.5, 3144.7", \ + "3443.7, 3443.7, 3443.7, 3555.8, 3779.9"); + } + } + internal_power (energy_neg_nq_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1956.5, 1956.5, 1956.5, 2068.6, 2292.8", \ + "2075.3, 2075.3, 2075.3, 2187.3, 2411.5", \ + "2297.2, 2297.2, 2297.2, 2409.3, 2633.4", \ + "2718.0, 2718.0, 2718.0, 2830.1, 3054.3", \ + "3532.2, 3532.2, 3532.2, 3644.3, 3868.4"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1989.7, 1989.7, 1989.7, 2101.8, 2325.9", \ + "2166.8, 2166.8, 2166.8, 2278.9, 2503.0", \ + "2511.9, 2511.9, 2511.9, 2624.0, 2848.1", \ + "3186.2, 3186.2, 3186.2, 3298.3, 3522.4", \ + "4512.8, 4512.8, 4512.8, 4624.9, 4849.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("2032.3, 2032.3, 2032.3, 2144.4, 2368.6", \ + "2147.1, 2147.1, 2147.1, 2259.2, 2483.4", \ + "2376.0, 2376.0, 2376.0, 2488.0, 2712.2", \ + "2822.4, 2822.4, 2822.4, 2934.5, 3158.7", \ + "3698.8, 3698.8, 3698.8, 3810.9, 4035.1"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2142.0, 2142.0, 2142.0, 2254.1, 2478.2", \ + "2374.7, 2374.7, 2374.7, 2486.8, 2711.0", \ + "2836.7, 2836.7, 2836.7, 2948.8, 3173.0", \ + "3747.2, 3747.2, 3747.2, 3859.3, 4083.5", \ + "5566.0, 5566.0, 5566.0, 5678.0, 5902.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("2032.3, 2032.3, 2032.3, 2144.4, 2368.6", \ + "2147.1, 2147.1, 2147.1, 2259.2, 2483.4", \ + "2376.0, 2376.0, 2376.0, 2488.0, 2712.2", \ + "2822.4, 2822.4, 2822.4, 2934.5, 3158.7", \ + "3698.8, 3698.8, 3698.8, 3810.9, 4035.1"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2142.0, 2142.0, 2142.0, 2254.1, 2478.2", \ + "2374.7, 2374.7, 2374.7, 2486.8, 2711.0", \ + "2836.7, 2836.7, 2836.7, 2948.8, 3173.0", \ + "3747.2, 3747.2, 3747.2, 3859.3, 4083.5", \ + "5566.0, 5566.0, 5566.0, 5678.0, 5902.2"); + } + } + } + } + + cell (nmx3_x1) { + area : 0.0 ; + cell_leakage_power : 0.0053 ; + leakage_power () { + when : "(i2 & !(i1) & i0 & cmd1 & cmd0)" ; + value : 0.0071 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0 & cmd1 & cmd0)" ; + value : 0.0049 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0) & cmd1 & cmd0)" ; + value : 0.005 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & cmd1 & cmd0)" ; + value : 0.0028 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0 & !(cmd1) & cmd0)" ; + value : 0.0086 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & !(cmd1) & cmd0)" ; + value : 0.0042 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & i2) | (!(cmd0) & cmd1 & i0))" ; + value : 0.0014 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i0) & i1 & !(i2)) | (!(cmd0) & cmd1 & !(i0) & i1 & i2))" ; + value : 0.0065 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & i0 & !(i1) & !(i2)) | (!(cmd0) & cmd1 & !(i0) & i1 & !(i2)))" ; + value : 0.0063 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0) & cmd1 & !(cmd0))" ; + value : 0.0044 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & cmd1 & !(cmd0))" ; + value : 0.0043 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0)" ; + value : 0.0029 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.0079 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.0058 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.0078 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & !(cmd1) & !(cmd0))" ; + value : 0.0057 ; + } + pin (i2) { + direction : input ; + capacitance : 27.49 ; + } + pin (i1) { + direction : input ; + capacitance : 32.64 ; + } + pin (i0) { + direction : input ; + capacitance : 25.83 ; + } + pin (cmd1) { + direction : input ; + capacitance : 54.92 ; + } + pin (cmd0) { + direction : input ; + capacitance : 53.19 ; + } + pin (nq) { + function : "((!(i0) & ((!(i1) & (!(cmd0) | !(i2) | cmd1)) | !(cmd0) | (!(i2) & !(cmd1)))) | (!(i1) & cmd0 & (!(i2) | cmd1)) | (cmd0 & !(i2) & !(cmd1)))" ; + direction : output ; + capacitance : 9.58 ; + timing (maxd_nq_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__24) { + values ("102.2, 102.2, 102.2, 119.8, 154.0", \ + "114.6, 114.6, 114.6, 132.5, 166.9", \ + "131.9, 131.9, 131.9, 150.1, 185.2", \ + "157.9, 157.9, 157.9, 176.7, 212.7", \ + "203.4, 203.4, 203.4, 222.9, 260.4"); + } + rise_transition (inslew_load_5x5__24) { + values ("88.7, 88.7, 88.7, 118.5, 178.9", \ + "98.8, 98.8, 98.8, 128.4, 188.4", \ + "118.7, 118.7, 118.7, 148.1, 207.4", \ + "156.7, 156.7, 156.7, 186.8, 245.4", \ + "233.0, 233.0, 233.0, 262.4, 322.3"); + } + cell_fall (inslew_load_5x5__24) { + values ("79.5, 79.5, 79.5, 92.8, 118.0", \ + "86.1, 86.1, 86.1, 99.8, 125.4", \ + "91.0, 91.0, 91.0, 105.2, 131.7", \ + "90.2, 90.2, 90.2, 105.0, 132.9", \ + "78.1, 78.1, 78.1, 93.7, 123.2"); + } + fall_transition (inslew_load_5x5__24) { + values ("57.6, 57.6, 57.6, 74.1, 107.0", \ + "64.0, 64.0, 64.0, 80.4, 113.3", \ + "75.9, 75.9, 75.9, 92.3, 125.3", \ + "98.2, 98.2, 98.2, 114.7, 147.5", \ + "141.5, 141.5, 141.5, 158.1, 191.0"); + } + } + timing (maxd_nq_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__24) { + values ("84.3, 84.3, 84.3, 105.5, 143.2", \ + "96.9, 96.9, 96.9, 119.5, 158.9", \ + "114.8, 114.8, 114.8, 139.4, 182.0", \ + "142.6, 142.6, 142.6, 169.6, 216.9", \ + "192.6, 192.6, 192.6, 222.3, 275.1"); + } + rise_transition (inslew_load_5x5__24) { + values ("57.5, 57.5, 57.5, 89.4, 152.9", \ + "67.3, 67.3, 67.3, 99.6, 162.8", \ + "85.6, 85.6, 85.6, 118.5, 182.6", \ + "120.5, 120.5, 120.5, 154.2, 219.6", \ + "189.0, 189.0, 189.0, 223.4, 290.5"); + } + cell_fall (inslew_load_5x5__24) { + values ("64.5, 64.5, 64.5, 83.8, 118.2", \ + "69.0, 69.0, 69.0, 89.4, 124.9", \ + "70.3, 70.3, 70.3, 92.2, 129.9", \ + "64.1, 64.1, 64.1, 88.1, 129.4", \ + "43.2, 43.2, 43.2, 69.5, 115.7"); + } + fall_transition (inslew_load_5x5__24) { + values ("45.5, 45.5, 45.5, 70.4, 120.2", \ + "51.2, 51.2, 51.2, 76.3, 125.9", \ + "61.4, 61.4, 61.4, 86.9, 136.6", \ + "80.5, 80.5, 80.5, 106.5, 157.1", \ + "117.0, 117.0, 117.0, 143.7, 195.4"); + } + } + timing (maxd_nq_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("27.4, 27.4, 27.4, 40.1, 64.4", \ + "29.0, 29.0, 29.0, 42.8, 68.6", \ + "29.9, 29.9, 29.9, 45.1, 73.5", \ + "29.6, 29.6, 29.6, 46.2, 77.3", \ + "27.5, 27.5, 27.5, 45.0, 78.7"); + } + rise_transition (inslew_load_5x5__24) { + values ("54.5, 54.5, 54.5, 74.4, 114.8", \ + "73.8, 73.8, 73.8, 93.9, 134.1", \ + "112.6, 112.6, 112.6, 132.9, 173.0", \ + "189.8, 189.8, 189.8, 210.4, 251.1", \ + "343.8, 343.8, 343.8, 364.7, 406.0"); + } + cell_fall (inslew_load_5x5__24) { + values ("38.7, 38.7, 38.7, 54.7, 85.9", \ + "44.8, 44.8, 44.8, 61.4, 93.6", \ + "55.4, 55.4, 55.4, 72.9, 106.5", \ + "75.2, 75.2, 75.2, 93.5, 128.9", \ + "113.9, 113.9, 113.9, 132.7, 171.2"); + } + fall_transition (inslew_load_5x5__24) { + values ("70.5, 70.5, 70.5, 94.6, 143.5", \ + "97.9, 97.9, 97.9, 121.8, 169.8", \ + "151.9, 151.9, 151.9, 175.7, 223.6", \ + "260.0, 260.0, 260.0, 283.8, 331.4", \ + "475.9, 475.9, 475.9, 499.8, 549.5"); + } + } + timing (maxd_nq_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("30.4, 30.4, 30.4, 50.6, 87.8", \ + "36.4, 36.4, 36.4, 60.1, 101.1", \ + "44.2, 44.2, 44.2, 71.3, 118.7", \ + "56.4, 56.4, 56.4, 86.4, 140.5", \ + "78.5, 78.5, 78.5, 110.5, 170.4"); + } + rise_transition (inslew_load_5x5__24) { + values ("52.6, 52.6, 52.6, 83.8, 147.8", \ + "75.7, 75.7, 75.7, 108.4, 172.0", \ + "119.7, 119.7, 119.7, 153.4, 219.0", \ + "206.0, 206.0, 206.0, 240.7, 308.3", \ + "377.6, 377.6, 377.6, 412.9, 482.3"); + } + cell_fall (inslew_load_5x5__24) { + values ("27.6, 27.6, 27.6, 46.7, 80.7", \ + "30.7, 30.7, 30.7, 52.9, 91.0", \ + "32.7, 32.7, 32.7, 58.1, 102.4", \ + "33.5, 33.5, 33.5, 61.6, 112.4", \ + "32.9, 32.9, 32.9, 63.0, 119.2"); + } + fall_transition (inslew_load_5x5__24) { + values ("43.8, 43.8, 43.8, 68.6, 118.5", \ + "63.0, 63.0, 63.0, 88.7, 138.5", \ + "99.5, 99.5, 99.5, 126.0, 177.3", \ + "171.1, 171.1, 171.1, 198.4, 251.4", \ + "313.3, 313.3, 313.3, 341.1, 395.7"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("23.1, 23.1, 23.1, 38.8, 66.0", \ + "26.5, 26.5, 26.5, 44.8, 76.1", \ + "30.4, 30.4, 30.4, 51.2, 87.7", \ + "36.1, 36.1, 36.1, 59.0, 100.5", \ + "46.3, 46.3, 46.3, 70.5, 116.1"); + } + rise_transition (inslew_load_5x5__24) { + values ("40.4, 40.4, 40.4, 62.1, 104.4", \ + "60.2, 60.2, 60.2, 82.7, 125.9", \ + "98.6, 98.6, 98.6, 121.8, 166.6", \ + "174.3, 174.3, 174.3, 198.2, 244.6", \ + "325.1, 325.1, 325.1, 349.5, 397.3"); + } + cell_fall (inslew_load_5x5__24) { + values ("23.2, 23.2, 23.2, 38.8, 65.9", \ + "26.1, 26.1, 26.1, 44.0, 75.1", \ + "29.1, 29.1, 29.1, 49.3, 85.1", \ + "33.0, 33.0, 33.0, 55.1, 95.5", \ + "39.7, 39.7, 39.7, 62.9, 106.9"); + } + fall_transition (inslew_load_5x5__24) { + values ("35.1, 35.1, 35.1, 52.1, 85.5", \ + "53.6, 53.6, 53.6, 71.2, 105.1", \ + "89.2, 89.2, 89.2, 107.5, 142.6", \ + "159.6, 159.6, 159.6, 178.4, 215.0", \ + "299.7, 299.7, 299.7, 318.9, 356.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("33.7, 33.7, 33.7, 51.8, 86.5", \ + "37.8, 37.8, 37.8, 57.3, 93.7", \ + "43.3, 43.3, 43.3, 64.7, 104.2", \ + "51.6, 51.6, 51.6, 74.9, 118.4", \ + "66.6, 66.6, 66.6, 91.2, 138.3"); + } + rise_transition (inslew_load_5x5__24) { + values ("64.6, 64.6, 64.6, 94.7, 155.8", \ + "86.9, 86.9, 86.9, 116.9, 177.3", \ + "131.2, 131.2, 131.2, 161.6, 221.6", \ + "219.1, 219.1, 219.1, 249.9, 310.7", \ + "394.2, 394.2, 394.2, 425.4, 487.2"); + } + cell_fall (inslew_load_5x5__24) { + values ("32.4, 32.4, 32.4, 49.3, 81.3", \ + "36.0, 36.0, 36.0, 54.5, 88.7", \ + "40.2, 40.2, 40.2, 60.7, 98.4", \ + "46.3, 46.3, 46.3, 68.5, 110.0", \ + "56.6, 56.6, 56.6, 80.0, 124.7"); + } + fall_transition (inslew_load_5x5__24) { + values ("55.2, 55.2, 55.2, 79.4, 128.1", \ + "76.3, 76.3, 76.3, 100.5, 149.0", \ + "117.5, 117.5, 117.5, 142.0, 190.5", \ + "198.9, 198.9, 198.9, 223.9, 273.2", \ + "361.1, 361.1, 361.1, 386.4, 436.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("33.7, 33.7, 33.7, 51.8, 86.5", \ + "37.8, 37.8, 37.8, 57.3, 93.7", \ + "43.3, 43.3, 43.3, 64.7, 104.2", \ + "51.6, 51.6, 51.6, 74.9, 118.4", \ + "66.6, 66.6, 66.6, 91.2, 138.3"); + } + rise_transition (inslew_load_5x5__24) { + values ("64.6, 64.6, 64.6, 94.7, 155.8", \ + "86.9, 86.9, 86.9, 116.9, 177.3", \ + "131.2, 131.2, 131.2, 161.6, 221.6", \ + "219.1, 219.1, 219.1, 249.9, 310.7", \ + "394.2, 394.2, 394.2, 425.4, 487.2"); + } + cell_fall (inslew_load_5x5__24) { + values ("32.4, 32.4, 32.4, 49.3, 81.3", \ + "36.0, 36.0, 36.0, 54.5, 88.7", \ + "40.2, 40.2, 40.2, 60.7, 98.4", \ + "46.3, 46.3, 46.3, 68.5, 110.0", \ + "56.6, 56.6, 56.6, 80.0, 124.7"); + } + fall_transition (inslew_load_5x5__24) { + values ("55.2, 55.2, 55.2, 79.4, 128.1", \ + "76.3, 76.3, 76.3, 100.5, 149.0", \ + "117.5, 117.5, 117.5, 142.0, 190.5", \ + "198.9, 198.9, 198.9, 223.9, 273.2", \ + "361.1, 361.1, 361.1, 386.4, 436.5"); + } + } + internal_power (energy_pos_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__24) { + values ("858.3, 858.3, 858.3, 978.1, 1217.6", \ + "977.1, 977.1, 977.1, 1096.9, 1336.4", \ + "1213.3, 1213.3, 1213.3, 1333.0, 1572.6", \ + "1681.7, 1681.7, 1681.7, 1801.5, 2041.0", \ + "2616.7, 2616.7, 2616.7, 2736.5, 2976.0"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("853.7, 853.7, 853.7, 973.4, 1213.0", \ + "939.2, 939.2, 939.2, 1059.0, 1298.5", \ + "1105.8, 1105.8, 1105.8, 1225.5, 1465.1", \ + "1432.1, 1432.1, 1432.1, 1551.8, 1791.4", \ + "2078.4, 2078.4, 2078.4, 2198.1, 2437.7"); + } + } + internal_power (energy_pos_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__24) { + values ("600.9, 600.9, 600.9, 720.7, 960.2", \ + "707.5, 707.5, 707.5, 827.3, 1066.8", \ + "919.2, 919.2, 919.2, 1039.0, 1278.5", \ + "1340.7, 1340.7, 1340.7, 1460.5, 1700.0", \ + "2182.8, 2182.8, 2182.8, 2302.6, 2542.1"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("565.4, 565.4, 565.4, 685.2, 924.7", \ + "633.4, 633.4, 633.4, 753.2, 992.7", \ + "767.3, 767.3, 767.3, 887.1, 1126.6", \ + "1033.0, 1033.0, 1033.0, 1152.7, 1392.3", \ + "1561.6, 1561.6, 1561.6, 1681.3, 1920.9"); + } + } + internal_power (energy_neg_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__24) { + values ("292.3, 292.3, 292.3, 412.1, 651.6", \ + "374.5, 374.5, 374.5, 494.2, 733.8", \ + "538.8, 538.8, 538.8, 658.6, 898.1", \ + "867.5, 867.5, 867.5, 987.3, 1226.8", \ + "1524.9, 1524.9, 1524.9, 1644.6, 1884.2"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("329.9, 329.9, 329.9, 449.7, 689.2", \ + "443.1, 443.1, 443.1, 562.8, 802.4", \ + "669.3, 669.3, 669.3, 789.1, 1028.6", \ + "1121.9, 1121.9, 1121.9, 1241.7, 1481.2", \ + "2027.0, 2027.0, 2027.0, 2146.8, 2386.3"); + } + } + internal_power (energy_neg_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__24) { + values ("172.4, 172.4, 172.4, 292.2, 531.7", \ + "225.1, 225.1, 225.1, 344.8, 584.4", \ + "330.4, 330.4, 330.4, 450.2, 689.7", \ + "541.0, 541.0, 541.0, 660.8, 900.3", \ + "962.3, 962.3, 962.3, 1082.1, 1321.6"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("174.5, 174.5, 174.5, 294.3, 533.8", \ + "229.2, 229.2, 229.2, 349.0, 588.5", \ + "338.7, 338.7, 338.7, 458.5, 698.0", \ + "557.6, 557.6, 557.6, 677.4, 916.9", \ + "995.5, 995.5, 995.5, 1115.3, 1354.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__24) { + values ("184.1, 184.1, 184.1, 303.8, 543.4", \ + "248.3, 248.3, 248.3, 368.1, 607.6", \ + "376.9, 376.9, 376.9, 496.7, 736.2", \ + "634.1, 634.1, 634.1, 753.9, 993.4", \ + "1148.4, 1148.4, 1148.4, 1268.2, 1507.7"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("193.5, 193.5, 193.5, 313.2, 552.8", \ + "267.1, 267.1, 267.1, 386.9, 626.4", \ + "414.5, 414.5, 414.5, 534.3, 773.8", \ + "709.3, 709.3, 709.3, 829.0, 1068.6", \ + "1298.8, 1298.8, 1298.8, 1418.5, 1658.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__24) { + values ("237.9, 237.9, 237.9, 357.7, 597.2", \ + "302.2, 302.2, 302.2, 422.0, 661.5", \ + "430.8, 430.8, 430.8, 550.5, 790.1", \ + "687.9, 687.9, 687.9, 807.7, 1047.2", \ + "1202.3, 1202.3, 1202.3, 1322.0, 1561.6"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("244.6, 244.6, 244.6, 364.3, 603.9", \ + "318.2, 318.2, 318.2, 438.0, 677.5", \ + "465.6, 465.6, 465.6, 585.4, 824.9", \ + "760.4, 760.4, 760.4, 880.1, 1119.7", \ + "1349.9, 1349.9, 1349.9, 1469.6, 1709.2"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__24) { + values ("237.9, 237.9, 237.9, 357.7, 597.2", \ + "302.2, 302.2, 302.2, 422.0, 661.5", \ + "430.8, 430.8, 430.8, 550.5, 790.1", \ + "687.9, 687.9, 687.9, 807.7, 1047.2", \ + "1202.3, 1202.3, 1202.3, 1322.0, 1561.6"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("244.6, 244.6, 244.6, 364.3, 603.9", \ + "318.2, 318.2, 318.2, 438.0, 677.5", \ + "465.6, 465.6, 465.6, 585.4, 824.9", \ + "760.4, 760.4, 760.4, 880.1, 1119.7", \ + "1349.9, 1349.9, 1349.9, 1469.6, 1709.2"); + } + } + } + } + + cell (no2_x1) { + area : 0.0 ; + cell_leakage_power : 0.0061 ; + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.0061 ; + } + pin (i1) { + direction : input ; + capacitance : 28.12 ; + } + pin (i0) { + direction : input ; + capacitance : 29.53 ; + } + pin (nq) { + function : "(!(i1) & !(i0))" ; + direction : output ; + capacitance : 6.30 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("6.4, 6.4, 6.4, 11.7, 21.3", \ + "0.0, 0.0, 0.0, 6.0, 17.1", \ + "-14.3, -14.3, -14.3, -7.4, 5.2", \ + "-43.9, -43.9, -43.9, -36.5, -22.3", \ + "-103.8, -103.8, -103.8, -95.9, -80.8"); + } + rise_transition (inslew_load_5x5__25) { + values ("25.5, 25.5, 25.5, 32.4, 45.8", \ + "37.7, 37.7, 37.7, 44.7, 58.5", \ + "61.7, 61.7, 61.7, 69.0, 83.2", \ + "109.3, 109.3, 109.3, 116.8, 131.4", \ + "204.4, 204.4, 204.4, 212.0, 227.0"); + } + cell_fall (inslew_load_5x5__25) { + values ("22.5, 22.5, 22.5, 28.9, 40.3", \ + "33.8, 33.8, 33.8, 40.6, 53.3", \ + "54.9, 54.9, 54.9, 62.1, 75.8", \ + "96.4, 96.4, 96.4, 103.8, 118.2", \ + "178.9, 178.9, 178.9, 186.4, 201.2"); + } + fall_transition (inslew_load_5x5__25) { + values ("30.0, 30.0, 30.0, 35.5, 46.3", \ + "54.2, 54.2, 54.2, 59.8, 70.8", \ + "101.5, 101.5, 101.5, 107.3, 118.6", \ + "195.7, 195.7, 195.7, 201.5, 213.0", \ + "383.6, 383.6, 383.6, 389.4, 401.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("7.5, 7.5, 7.5, 14.6, 26.4", \ + "5.4, 5.4, 5.4, 13.5, 27.5", \ + "0.3, 0.3, 0.3, 9.1, 25.1", \ + "-10.3, -10.3, -10.3, -1.0, 16.4", \ + "-31.8, -31.8, -31.8, -22.3, -3.8"); + } + rise_transition (inslew_load_5x5__25) { + values ("22.9, 22.9, 22.9, 30.7, 45.5", \ + "38.6, 38.6, 38.6, 46.7, 62.2", \ + "69.4, 69.4, 69.4, 77.8, 93.9", \ + "130.7, 130.7, 130.7, 139.2, 155.9", \ + "253.0, 253.0, 253.0, 261.6, 278.7"); + } + cell_fall (inslew_load_5x5__25) { + values ("13.9, 13.9, 13.9, 21.0, 33.5", \ + "18.7, 18.7, 18.7, 26.5, 40.5", \ + "27.4, 27.4, 27.4, 35.6, 51.0", \ + "44.1, 44.1, 44.1, 52.6, 68.9", \ + "77.3, 77.3, 77.3, 85.9, 102.9"); + } + fall_transition (inslew_load_5x5__25) { + values ("23.0, 23.0, 23.0, 28.8, 39.8", \ + "42.4, 42.4, 42.4, 48.3, 59.8", \ + "80.4, 80.4, 80.4, 86.5, 98.4", \ + "155.9, 155.9, 155.9, 162.2, 174.4", \ + "306.8, 306.8, 306.8, 313.0, 325.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__25) { + values ("230.3, 230.3, 230.3, 309.1, 466.7", \ + "314.0, 314.0, 314.0, 392.8, 550.4", \ + "481.4, 481.4, 481.4, 560.2, 717.7", \ + "816.1, 816.1, 816.1, 894.9, 1052.5", \ + "1485.6, 1485.6, 1485.6, 1564.4, 1721.9"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("332.9, 332.9, 332.9, 411.6, 569.2", \ + "539.2, 539.2, 539.2, 618.0, 775.5", \ + "951.9, 951.9, 951.9, 1030.7, 1188.3", \ + "1777.3, 1777.3, 1777.3, 1856.1, 2013.7", \ + "3428.2, 3428.2, 3428.2, 3507.0, 3664.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__25) { + values ("173.5, 173.5, 173.5, 252.3, 409.9", \ + "268.3, 268.3, 268.3, 347.1, 504.6", \ + "457.8, 457.8, 457.8, 536.6, 694.1", \ + "836.8, 836.8, 836.8, 915.6, 1073.2", \ + "1594.9, 1594.9, 1594.9, 1673.7, 1831.2"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("225.3, 225.3, 225.3, 304.1, 461.6", \ + "371.8, 371.8, 371.8, 450.6, 608.2", \ + "664.9, 664.9, 664.9, 743.7, 901.3", \ + "1251.1, 1251.1, 1251.1, 1329.8, 1487.4", \ + "2423.3, 2423.3, 2423.3, 2502.1, 2659.7"); + } + } + } + } + + cell (no2_x4) { + area : 0.0 ; + cell_leakage_power : 0.0087 ; + leakage_power () { + when : "(i0 | i1)" ; + value : 0.002 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.015 ; + } + pin (i1) { + direction : input ; + capacitance : 21.15 ; + } + pin (i0) { + direction : input ; + capacitance : 21.15 ; + } + pin (nq) { + function : "(!(i0) & !(i1))" ; + direction : output ; + capacitance : 8.46 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__26) { + values ("85.7, 85.7, 85.7, 89.2, 95.6", \ + "82.3, 82.3, 82.3, 85.8, 92.2", \ + "70.1, 70.1, 70.1, 73.7, 80.2", \ + "37.7, 37.7, 37.7, 41.3, 48.0", \ + "-36.2, -36.2, -36.2, -32.3, -25.3"); + } + rise_transition (inslew_load_5x5__26) { + values ("20.4, 20.4, 20.4, 23.4, 28.8", \ + "21.5, 21.5, 21.5, 24.5, 30.0", \ + "23.7, 23.7, 23.7, 26.6, 32.2", \ + "27.8, 27.8, 27.8, 30.7, 36.3", \ + "35.6, 35.6, 35.6, 38.5, 44.2"); + } + cell_fall (inslew_load_5x5__26) { + values ("114.5, 114.5, 114.5, 118.4, 125.5", \ + "137.0, 137.0, 137.0, 140.9, 148.1", \ + "173.7, 173.7, 173.7, 177.6, 185.0", \ + "237.6, 237.6, 237.6, 241.5, 249.0", \ + "355.1, 355.1, 355.1, 359.1, 366.9"); + } + fall_transition (inslew_load_5x5__26) { + values ("28.8, 28.8, 28.8, 31.7, 37.3", \ + "32.3, 32.3, 32.3, 35.2, 40.8", \ + "38.6, 38.6, 38.6, 41.6, 47.3", \ + "50.5, 50.5, 50.5, 53.5, 59.2", \ + "73.1, 73.1, 73.1, 76.1, 81.9"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__26) { + values ("91.0, 91.0, 91.0, 94.5, 100.9", \ + "93.0, 93.0, 93.0, 96.6, 103.1", \ + "89.7, 89.7, 89.7, 93.3, 99.9", \ + "74.1, 74.1, 74.1, 77.8, 84.7", \ + "33.4, 33.4, 33.4, 37.3, 44.4"); + } + rise_transition (inslew_load_5x5__26) { + values ("20.4, 20.4, 20.4, 23.4, 28.8", \ + "21.9, 21.9, 21.9, 24.9, 30.4", \ + "24.8, 24.8, 24.8, 27.7, 33.2", \ + "30.0, 30.0, 30.0, 33.0, 38.6", \ + "40.3, 40.3, 40.3, 43.1, 48.9"); + } + cell_fall (inslew_load_5x5__26) { + values ("105.2, 105.2, 105.2, 109.1, 116.2", \ + "121.8, 121.8, 121.8, 125.7, 132.9", \ + "146.8, 146.8, 146.8, 150.8, 158.1", \ + "187.5, 187.5, 187.5, 191.5, 198.9", \ + "258.6, 258.6, 258.6, 262.6, 270.3"); + } + fall_transition (inslew_load_5x5__26) { + values ("27.8, 27.8, 27.8, 30.7, 36.3", \ + "30.7, 30.7, 30.7, 33.6, 39.3", \ + "36.1, 36.1, 36.1, 39.0, 44.7", \ + "46.1, 46.1, 46.1, 49.0, 54.7", \ + "64.9, 64.9, 64.9, 67.9, 73.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__26) { + values ("1595.8, 1595.8, 1595.8, 1701.5, 1912.9", \ + "1693.8, 1693.8, 1693.8, 1799.5, 2010.9", \ + "1886.3, 1886.3, 1886.3, 1992.0, 2203.4", \ + "2262.3, 2262.3, 2262.3, 2368.0, 2579.3", \ + "3003.1, 3003.1, 3003.1, 3108.7, 3320.1"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("1914.9, 1914.9, 1914.9, 2020.6, 2232.0", \ + "2208.2, 2208.2, 2208.2, 2313.8, 2525.2", \ + "2781.5, 2781.5, 2781.5, 2887.2, 3098.6", \ + "3909.6, 3909.6, 3909.6, 4015.3, 4226.6", \ + "6141.3, 6141.3, 6141.3, 6246.9, 6458.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__26) { + values ("1537.2, 1537.2, 1537.2, 1642.9, 1854.2", \ + "1660.3, 1660.3, 1660.3, 1766.0, 1977.4", \ + "1898.4, 1898.4, 1898.4, 2004.1, 2215.5", \ + "2362.8, 2362.8, 2362.8, 2468.5, 2679.9", \ + "3277.6, 3277.6, 3277.6, 3383.3, 3594.7"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("1783.3, 1783.3, 1783.3, 1889.0, 2100.4", \ + "2013.1, 2013.1, 2013.1, 2118.8, 2330.2", \ + "2459.7, 2459.7, 2459.7, 2565.4, 2776.7", \ + "3335.4, 3335.4, 3335.4, 3441.1, 3652.5", \ + "5065.5, 5065.5, 5065.5, 5171.2, 5382.5"); + } + } + } + } + + cell (no3_x1) { + area : 0.0 ; + cell_leakage_power : 0.0059 ; + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.0059 ; + } + pin (i2) { + direction : input ; + capacitance : 26.08 ; + } + pin (i1) { + direction : input ; + capacitance : 26.54 ; + } + pin (i0) { + direction : input ; + capacitance : 25.60 ; + } + pin (nq) { + function : "((!(i1) & !(i0)) & !(i2))" ; + direction : output ; + capacitance : 7.01 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__27) { + values ("13.3, 13.3, 13.3, 21.1, 35.3", \ + "8.5, 8.5, 8.5, 17.5, 33.7", \ + "-3.3, -3.3, -3.3, 7.0, 25.7", \ + "-28.9, -28.9, -28.9, -17.5, 3.8", \ + "-81.5, -81.5, -81.5, -69.3, -46.0"); + } + rise_transition (inslew_load_5x5__27) { + values ("34.5, 34.5, 34.5, 45.7, 68.2", \ + "48.0, 48.0, 48.0, 59.5, 82.1", \ + "74.0, 74.0, 74.0, 86.0, 109.3", \ + "125.6, 125.6, 125.6, 137.9, 162.0", \ + "228.3, 228.3, 228.3, 240.8, 265.6"); + } + cell_fall (inslew_load_5x5__27) { + values ("27.7, 27.7, 27.7, 37.0, 53.8", \ + "38.5, 38.5, 38.5, 48.8, 67.6", \ + "57.8, 57.8, 57.8, 68.8, 89.6", \ + "94.8, 94.8, 94.8, 106.4, 128.7", \ + "168.0, 168.0, 168.0, 180.0, 203.3"); + } + fall_transition (inslew_load_5x5__27) { + values ("33.4, 33.4, 33.4, 42.0, 58.8", \ + "57.2, 57.2, 57.2, 66.0, 83.1", \ + "103.2, 103.2, 103.2, 112.2, 129.8", \ + "194.2, 194.2, 194.2, 203.3, 221.4", \ + "375.6, 375.6, 375.6, 384.8, 403.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__27) { + values ("11.3, 11.3, 11.3, 21.2, 37.7", \ + "9.5, 9.5, 9.5, 21.1, 40.8", \ + "4.0, 4.0, 4.0, 17.0, 40.1", \ + "-8.1, -8.1, -8.1, 5.9, 31.9", \ + "-33.1, -33.1, -33.1, -18.4, 9.5"); + } + rise_transition (inslew_load_5x5__27) { + values ("28.6, 28.6, 28.6, 41.0, 64.8", \ + "45.1, 45.1, 45.1, 58.1, 82.9", \ + "77.2, 77.2, 77.2, 90.6, 116.5", \ + "140.6, 140.6, 140.6, 154.4, 181.3", \ + "267.0, 267.0, 267.0, 281.1, 308.7"); + } + cell_fall (inslew_load_5x5__27) { + values ("18.6, 18.6, 18.6, 28.9, 46.7", \ + "24.5, 24.5, 24.5, 35.9, 56.2", \ + "34.5, 34.5, 34.5, 46.8, 69.4", \ + "53.4, 53.4, 53.4, 66.3, 90.8", \ + "90.6, 90.6, 90.6, 103.9, 129.6"); + } + fall_transition (inslew_load_5x5__27) { + values ("25.8, 25.8, 25.8, 34.7, 51.6", \ + "46.0, 46.0, 46.0, 55.2, 72.6", \ + "85.1, 85.1, 85.1, 94.5, 112.7", \ + "162.5, 162.5, 162.5, 172.1, 190.9", \ + "316.8, 316.8, 316.8, 326.6, 345.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__27) { + values ("12.6, 12.6, 12.6, 19.5, 32.8", \ + "3.9, 3.9, 3.9, 11.7, 26.0", \ + "-15.5, -15.5, -15.5, -6.6, 9.6", \ + "-57.0, -57.0, -57.0, -47.0, -28.4", \ + "-142.1, -142.1, -142.1, -131.2, -110.5"); + } + rise_transition (inslew_load_5x5__27) { + values ("39.3, 39.3, 39.3, 50.2, 72.1", \ + "49.7, 49.7, 49.7, 60.7, 82.9", \ + "70.7, 70.7, 70.7, 81.9, 104.0", \ + "112.1, 112.1, 112.1, 123.6, 146.3", \ + "194.3, 194.3, 194.3, 206.0, 229.3"); + } + cell_fall (inslew_load_5x5__27) { + values ("35.5, 35.5, 35.5, 44.2, 60.3", \ + "52.7, 52.7, 52.7, 62.1, 79.8", \ + "84.4, 84.4, 84.4, 94.4, 113.6", \ + "146.0, 146.0, 146.0, 156.4, 176.7", \ + "268.3, 268.3, 268.3, 279.0, 300.0"); + } + fall_transition (inslew_load_5x5__27) { + values ("40.5, 40.5, 40.5, 49.0, 65.7", \ + "69.4, 69.4, 69.4, 78.0, 94.8", \ + "125.2, 125.2, 125.2, 133.9, 151.0", \ + "235.8, 235.8, 235.8, 244.6, 261.9", \ + "456.2, 456.2, 456.2, 465.0, 482.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__27) { + values ("221.0, 221.0, 221.0, 308.7, 483.9", \ + "283.3, 283.3, 283.3, 370.9, 546.1", \ + "407.7, 407.7, 407.7, 495.4, 670.6", \ + "656.7, 656.7, 656.7, 744.3, 919.5", \ + "1154.5, 1154.5, 1154.5, 1242.2, 1417.4"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("278.6, 278.6, 278.6, 366.3, 541.5", \ + "416.5, 416.5, 416.5, 504.1, 679.4", \ + "692.3, 692.3, 692.3, 779.9, 955.2", \ + "1243.8, 1243.8, 1243.8, 1331.4, 1506.7", \ + "2346.9, 2346.9, 2346.9, 2434.5, 2609.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__27) { + values ("156.4, 156.4, 156.4, 244.0, 419.2", \ + "225.1, 225.1, 225.1, 312.7, 488.0", \ + "362.6, 362.6, 362.6, 450.2, 625.5", \ + "637.6, 637.6, 637.6, 725.2, 900.5", \ + "1187.6, 1187.6, 1187.6, 1275.2, 1450.4"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("194.8, 194.8, 194.8, 282.5, 457.7", \ + "302.1, 302.1, 302.1, 389.7, 564.9", \ + "516.5, 516.5, 516.5, 604.1, 779.4", \ + "945.4, 945.4, 945.4, 1033.0, 1208.3", \ + "1803.2, 1803.2, 1803.2, 1890.8, 2066.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__27) { + values ("269.1, 269.1, 269.1, 356.7, 532.0", \ + "321.9, 321.9, 321.9, 409.5, 584.8", \ + "427.4, 427.4, 427.4, 515.0, 690.3", \ + "638.5, 638.5, 638.5, 726.1, 901.4", \ + "1060.6, 1060.6, 1060.6, 1148.3, 1323.5"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("364.4, 364.4, 364.4, 452.0, 627.2", \ + "548.9, 548.9, 548.9, 636.6, 811.8", \ + "918.1, 918.1, 918.1, 1005.7, 1180.9", \ + "1656.3, 1656.3, 1656.3, 1744.0, 1919.2", \ + "3132.9, 3132.9, 3132.9, 3220.5, 3395.8"); + } + } + } + } + + cell (no3_x4) { + area : 0.0 ; + cell_leakage_power : 0.011 ; + leakage_power () { + when : "(i0 | i1 | i2)" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.017 ; + } + pin (i2) { + direction : input ; + capacitance : 21.50 ; + } + pin (i1) { + direction : input ; + capacitance : 23.62 ; + } + pin (i0) { + direction : input ; + capacitance : 23.62 ; + } + pin (nq) { + function : "(!(i0) & !(i1) & !(i2))" ; + direction : output ; + capacitance : 8.53 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__28) { + values ("75.1, 75.1, 75.1, 78.6, 84.7", \ + "68.6, 68.6, 68.6, 72.2, 78.4", \ + "52.8, 52.8, 52.8, 56.4, 62.7", \ + "14.4, 14.4, 14.4, 18.0, 24.5", \ + "-70.8, -70.8, -70.8, -67.0, -60.3"); + } + rise_transition (inslew_load_5x5__28) { + values ("15.9, 15.9, 15.9, 18.7, 24.2", \ + "16.7, 16.7, 16.7, 19.6, 25.1", \ + "18.4, 18.4, 18.4, 21.3, 26.8", \ + "21.7, 21.7, 21.7, 24.7, 30.2", \ + "27.9, 27.9, 27.9, 30.9, 36.6"); + } + cell_fall (inslew_load_5x5__28) { + values ("132.1, 132.1, 132.1, 136.0, 143.4", \ + "159.2, 159.2, 159.2, 163.2, 170.6", \ + "205.3, 205.3, 205.3, 209.3, 216.8", \ + "288.8, 288.8, 288.8, 292.9, 300.7", \ + "448.4, 448.4, 448.4, 452.5, 460.5"); + } + fall_transition (inslew_load_5x5__28) { + values ("34.4, 34.4, 34.4, 37.3, 43.0", \ + "39.5, 39.5, 39.5, 42.4, 48.2", \ + "49.1, 49.1, 49.1, 52.1, 57.9", \ + "67.6, 67.6, 67.6, 70.6, 76.5", \ + "103.9, 103.9, 103.9, 106.9, 112.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__28) { + values ("77.4, 77.4, 77.4, 81.0, 87.0", \ + "76.6, 76.6, 76.6, 80.1, 86.3", \ + "69.1, 69.1, 69.1, 72.7, 79.0", \ + "46.5, 46.5, 46.5, 50.1, 56.6", \ + "-7.8, -7.8, -7.8, -4.1, 2.9"); + } + rise_transition (inslew_load_5x5__28) { + values ("15.6, 15.6, 15.6, 18.4, 23.8", \ + "16.7, 16.7, 16.7, 19.6, 25.0", \ + "18.9, 18.9, 18.9, 21.8, 27.3", \ + "22.9, 22.9, 22.9, 25.9, 31.5", \ + "30.7, 30.7, 30.7, 33.6, 39.4"); + } + cell_fall (inslew_load_5x5__28) { + values ("123.7, 123.7, 123.7, 127.6, 134.9", \ + "144.2, 144.2, 144.2, 148.2, 155.6", \ + "177.2, 177.2, 177.2, 181.2, 188.7", \ + "234.1, 234.1, 234.1, 238.1, 245.8", \ + "339.5, 339.5, 339.5, 343.6, 351.5"); + } + fall_transition (inslew_load_5x5__28) { + values ("33.1, 33.1, 33.1, 36.0, 41.7", \ + "37.4, 37.4, 37.4, 40.4, 46.1", \ + "45.5, 45.5, 45.5, 48.5, 54.3", \ + "60.9, 60.9, 60.9, 63.9, 69.7", \ + "90.9, 90.9, 90.9, 93.9, 99.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__28) { + values ("80.0, 80.0, 80.0, 83.6, 89.5", \ + "84.1, 84.1, 84.1, 87.7, 93.8", \ + "84.0, 84.0, 84.0, 87.5, 93.9", \ + "74.5, 74.5, 74.5, 78.2, 84.8", \ + "45.7, 45.7, 45.7, 49.6, 56.6"); + } + rise_transition (inslew_load_5x5__28) { + values ("15.3, 15.3, 15.3, 18.2, 23.6", \ + "16.8, 16.8, 16.8, 19.6, 25.1", \ + "19.4, 19.4, 19.4, 22.4, 27.9", \ + "24.4, 24.4, 24.4, 27.4, 33.0", \ + "33.9, 33.9, 33.9, 36.8, 42.6"); + } + cell_fall (inslew_load_5x5__28) { + values ("114.6, 114.6, 114.6, 118.6, 125.9", \ + "130.5, 130.5, 130.5, 134.4, 141.8", \ + "153.7, 153.7, 153.7, 157.7, 165.2", \ + "191.1, 191.1, 191.1, 195.1, 202.8", \ + "256.9, 256.9, 256.9, 261.0, 268.9"); + } + fall_transition (inslew_load_5x5__28) { + values ("31.8, 31.8, 31.8, 34.7, 40.4", \ + "35.6, 35.6, 35.6, 38.5, 44.3", \ + "42.6, 42.6, 42.6, 45.6, 51.3", \ + "55.9, 55.9, 55.9, 58.8, 64.7", \ + "81.5, 81.5, 81.5, 84.5, 90.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__28) { + values ("1699.6, 1699.6, 1699.6, 1806.2, 2019.5", \ + "1794.5, 1794.5, 1794.5, 1901.1, 2114.3", \ + "1983.3, 1983.3, 1983.3, 2089.9, 2303.1", \ + "2358.6, 2358.6, 2358.6, 2465.3, 2678.5", \ + "3099.9, 3099.9, 3099.9, 3206.5, 3419.7"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("2257.2, 2257.2, 2257.2, 2363.8, 2577.0", \ + "2629.4, 2629.4, 2629.4, 2736.0, 2949.2", \ + "3356.2, 3356.2, 3356.2, 3462.8, 3676.0", \ + "4791.8, 4791.8, 4791.8, 4898.4, 5111.7", \ + "7645.9, 7645.9, 7645.9, 7752.5, 7965.8"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__28) { + values ("1635.9, 1635.9, 1635.9, 1742.5, 1955.7", \ + "1753.2, 1753.2, 1753.2, 1859.8, 2073.1", \ + "1984.8, 1984.8, 1984.8, 2091.4, 2304.6", \ + "2438.1, 2438.1, 2438.1, 2544.8, 2758.0", \ + "3333.4, 3333.4, 3333.4, 3440.1, 3653.3"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("2125.8, 2125.8, 2125.8, 2232.4, 2445.7", \ + "2421.2, 2421.2, 2421.2, 2527.8, 2741.1", \ + "2996.5, 2996.5, 2996.5, 3103.1, 3316.3", \ + "4125.8, 4125.8, 4125.8, 4232.4, 4445.7", \ + "6366.2, 6366.2, 6366.2, 6472.9, 6686.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__28) { + values ("1558.7, 1558.7, 1558.7, 1665.3, 1878.5", \ + "1699.2, 1699.2, 1699.2, 1805.8, 2019.0", \ + "1969.0, 1969.0, 1969.0, 2075.6, 2288.8", \ + "2494.8, 2494.8, 2494.8, 2601.4, 2814.7", \ + "3532.1, 3532.1, 3532.1, 3638.7, 3851.9"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("1995.6, 1995.6, 1995.6, 2102.2, 2315.4", \ + "2239.9, 2239.9, 2239.9, 2346.6, 2559.8", \ + "2712.6, 2712.6, 2712.6, 2819.2, 3032.4", \ + "3637.3, 3637.3, 3637.3, 3743.9, 3957.2", \ + "5465.9, 5465.9, 5465.9, 5572.6, 5785.8"); + } + } + } + } + + cell (no4_x1) { + area : 0.0 ; + cell_leakage_power : 0.0088 ; + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0088 ; + } + pin (i3) { + direction : input ; + capacitance : 27.23 ; + } + pin (i2) { + direction : input ; + capacitance : 25.14 ; + } + pin (i1) { + direction : input ; + capacitance : 25.74 ; + } + pin (i0) { + direction : input ; + capacitance : 27.03 ; + } + pin (nq) { + function : "(((!(i1) & !(i0)) & !(i2)) & !(i3))" ; + direction : output ; + capacitance : 7.97 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__29) { + values ("21.7, 21.7, 21.7, 32.0, 51.9", \ + "22.3, 22.3, 22.3, 34.2, 55.7", \ + "21.0, 21.0, 21.0, 34.3, 58.6", \ + "16.4, 16.4, 16.4, 30.8, 57.8", \ + "5.8, 5.8, 5.8, 21.0, 50.2"); + } + rise_transition (inslew_load_5x5__29) { + values ("47.5, 47.5, 47.5, 64.1, 97.9", \ + "67.0, 67.0, 67.0, 84.1, 117.6", \ + "104.8, 104.8, 104.8, 122.3, 156.6", \ + "179.6, 179.6, 179.6, 197.5, 232.6", \ + "328.7, 328.7, 328.7, 346.8, 382.6"); + } + cell_fall (inslew_load_5x5__29) { + values ("24.0, 24.0, 24.0, 34.0, 51.7", \ + "29.1, 29.1, 29.1, 40.5, 60.8", \ + "36.8, 36.8, 36.8, 49.4, 72.5", \ + "50.4, 50.4, 50.4, 63.9, 89.3", \ + "76.6, 76.6, 76.6, 90.6, 117.7"); + } + fall_transition (inslew_load_5x5__29) { + values ("30.5, 30.5, 30.5, 39.5, 56.9", \ + "49.8, 49.8, 49.8, 59.1, 77.0", \ + "86.9, 86.9, 86.9, 96.6, 115.4", \ + "160.3, 160.3, 160.3, 170.3, 189.9", \ + "306.4, 306.4, 306.4, 316.7, 336.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__29) { + values ("15.5, 15.5, 15.5, 27.2, 46.9", \ + "18.4, 18.4, 18.4, 31.7, 55.2", \ + "22.2, 22.2, 22.2, 37.1, 63.9", \ + "28.8, 28.8, 28.8, 44.7, 74.5", \ + "41.2, 41.2, 41.2, 57.8, 89.6"); + } + rise_transition (inslew_load_5x5__29) { + values ("36.5, 36.5, 36.5, 53.6, 86.1", \ + "57.4, 57.4, 57.4, 75.2, 109.8", \ + "98.5, 98.5, 98.5, 116.8, 152.6", \ + "180.2, 180.2, 180.2, 198.8, 235.5", \ + "343.1, 343.1, 343.1, 362.0, 399.4"); + } + cell_fall (inslew_load_5x5__29) { + values ("16.3, 16.3, 16.3, 27.3, 45.8", \ + "17.6, 17.6, 17.6, 30.2, 51.9", \ + "18.5, 18.5, 18.5, 32.4, 57.3", \ + "18.9, 18.9, 18.9, 33.8, 61.5", \ + "19.0, 19.0, 19.0, 34.5, 64.2"); + } + fall_transition (inslew_load_5x5__29) { + values ("24.2, 24.2, 24.2, 33.5, 51.0", \ + "40.9, 40.9, 40.9, 50.7, 69.0", \ + "73.4, 73.4, 73.4, 83.6, 103.0", \ + "137.5, 137.5, 137.5, 148.1, 168.5", \ + "265.3, 265.3, 265.3, 276.1, 297.3"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__29) { + values ("24.9, 24.9, 24.9, 34.8, 53.9", \ + "21.9, 21.9, 21.9, 32.6, 52.9", \ + "13.7, 13.7, 13.7, 25.6, 47.9", \ + "-4.9, -4.9, -4.9, 8.0, 32.7", \ + "-44.1, -44.1, -44.1, -30.3, -3.5"); + } + rise_transition (inslew_load_5x5__29) { + values ("56.9, 56.9, 56.9, 73.6, 107.2", \ + "73.4, 73.4, 73.4, 90.0, 123.5", \ + "106.3, 106.3, 106.3, 123.1, 156.4", \ + "171.4, 171.4, 171.4, 188.5, 222.3", \ + "301.1, 301.1, 301.1, 318.5, 352.9"); + } + cell_fall (inslew_load_5x5__29) { + values ("30.4, 30.4, 30.4, 39.7, 56.8", \ + "40.1, 40.1, 40.1, 50.6, 69.8", \ + "56.9, 56.9, 56.9, 68.4, 89.9", \ + "88.5, 88.5, 88.5, 100.7, 124.0", \ + "150.6, 150.6, 150.6, 163.2, 187.9"); + } + fall_transition (inslew_load_5x5__29) { + values ("36.1, 36.1, 36.1, 44.9, 62.3", \ + "58.7, 58.7, 58.7, 67.8, 85.4", \ + "102.6, 102.6, 102.6, 111.9, 130.1", \ + "189.3, 189.3, 189.3, 198.8, 217.6", \ + "362.0, 362.0, 362.0, 371.7, 390.9"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__29) { + values ("24.2, 24.2, 24.2, 33.7, 52.4", \ + "16.2, 16.2, 16.2, 26.2, 45.6", \ + "-0.6, -0.6, -0.6, 10.1, 30.6", \ + "-36.7, -36.7, -36.7, -24.9, -2.4", \ + "-111.1, -111.1, -111.1, -98.5, -74.0"); + } + rise_transition (inslew_load_5x5__29) { + values ("62.5, 62.5, 62.5, 79.2, 112.8", \ + "75.4, 75.4, 75.4, 91.8, 124.8", \ + "101.3, 101.3, 101.3, 118.5, 150.8", \ + "153.7, 153.7, 153.7, 170.1, 202.9", \ + "257.9, 257.9, 257.9, 274.6, 307.8"); + } + cell_fall (inslew_load_5x5__29) { + values ("36.9, 36.9, 36.9, 45.8, 62.4", \ + "53.0, 53.0, 53.0, 62.7, 81.0", \ + "82.4, 82.4, 82.4, 92.8, 112.8", \ + "139.4, 139.4, 139.4, 150.3, 171.6", \ + "252.3, 252.3, 252.3, 263.6, 288.8"); + } + fall_transition (inslew_load_5x5__29) { + values ("42.1, 42.1, 42.1, 50.9, 68.2", \ + "69.9, 69.9, 69.9, 78.7, 96.2", \ + "123.7, 123.7, 123.7, 132.7, 150.5", \ + "230.3, 230.3, 230.3, 239.4, 257.5", \ + "442.9, 442.9, 442.9, 452.1, 473.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__29) { + values ("247.5, 247.5, 247.5, 347.1, 546.3", \ + "324.5, 324.5, 324.5, 424.1, 623.3", \ + "478.5, 478.5, 478.5, 578.1, 777.3", \ + "786.5, 786.5, 786.5, 886.1, 1085.3", \ + "1402.6, 1402.6, 1402.6, 1502.2, 1701.3"); + } + fall_power (energy_inslew_load_5x5__29) { + values ("259.0, 259.0, 259.0, 358.6, 557.8", \ + "366.7, 366.7, 366.7, 466.3, 665.5", \ + "582.1, 582.1, 582.1, 681.7, 880.9", \ + "1012.9, 1012.9, 1012.9, 1112.5, 1311.6", \ + "1874.4, 1874.4, 1874.4, 1974.0, 2173.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__29) { + values ("179.6, 179.6, 179.6, 279.2, 478.4", \ + "259.7, 259.7, 259.7, 359.3, 558.5", \ + "419.8, 419.8, 419.8, 519.4, 718.6", \ + "740.0, 740.0, 740.0, 839.6, 1038.8", \ + "1380.4, 1380.4, 1380.4, 1480.0, 1679.2"); + } + fall_power (energy_inslew_load_5x5__29) { + values ("186.2, 186.2, 186.2, 285.8, 485.0", \ + "272.8, 272.8, 272.8, 372.4, 571.6", \ + "446.0, 446.0, 446.0, 545.6, 744.8", \ + "792.5, 792.5, 792.5, 892.1, 1091.3", \ + "1485.4, 1485.4, 1485.4, 1585.0, 1784.2"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__29) { + values ("306.0, 306.0, 306.0, 405.6, 604.8", \ + "376.3, 376.3, 376.3, 475.9, 675.0", \ + "516.7, 516.7, 516.7, 616.3, 815.5", \ + "797.6, 797.6, 797.6, 897.2, 1096.3", \ + "1359.3, 1359.3, 1359.3, 1458.9, 1658.1"); + } + fall_power (energy_inslew_load_5x5__29) { + values ("328.8, 328.8, 328.8, 428.4, 627.6", \ + "469.0, 469.0, 469.0, 568.6, 767.8", \ + "749.3, 749.3, 749.3, 848.9, 1048.1", \ + "1310.0, 1310.0, 1310.0, 1409.6, 1608.8", \ + "2431.4, 2431.4, 2431.4, 2531.0, 2730.2"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__29) { + values ("344.7, 344.7, 344.7, 444.3, 643.5", \ + "403.8, 403.8, 403.8, 503.4, 702.5", \ + "521.9, 521.9, 521.9, 621.5, 820.6", \ + "758.0, 758.0, 758.0, 857.6, 1056.8", \ + "1230.4, 1230.4, 1230.4, 1330.0, 1529.2"); + } + fall_power (energy_inslew_load_5x5__29) { + values ("409.8, 409.8, 409.8, 509.4, 708.6", \ + "601.8, 601.8, 601.8, 701.4, 900.5", \ + "985.6, 985.6, 985.6, 1085.2, 1284.4", \ + "1753.4, 1753.4, 1753.4, 1853.0, 2052.2", \ + "3288.9, 3288.9, 3288.9, 3388.5, 3587.6"); + } + } + } + } + + cell (no4_x4) { + area : 0.0 ; + cell_leakage_power : 0.011 ; + leakage_power () { + when : "(i0 | i1 | i2 | i3)" ; + value : 0.002 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.019 ; + } + pin (i3) { + direction : input ; + capacitance : 21.19 ; + } + pin (i2) { + direction : input ; + capacitance : 21.90 ; + } + pin (i1) { + direction : input ; + capacitance : 22.25 ; + } + pin (i0) { + direction : input ; + capacitance : 23.30 ; + } + pin (nq) { + function : "(!(i3) & !(i2) & !(i0) & !(i1))" ; + direction : output ; + capacitance : 8.83 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__30) { + values ("138.2, 138.2, 138.2, 142.1, 149.1", \ + "144.5, 144.5, 144.5, 148.5, 155.5", \ + "151.1, 151.1, 151.1, 155.2, 162.4", \ + "154.8, 154.8, 154.8, 159.0, 166.4", \ + "151.7, 151.7, 151.7, 155.9, 163.8"); + } + rise_transition (inslew_load_5x5__30) { + values ("29.6, 29.6, 29.6, 32.6, 38.4", \ + "31.6, 31.6, 31.6, 34.6, 40.4", \ + "35.4, 35.4, 35.4, 38.4, 44.2", \ + "42.6, 42.6, 42.6, 45.6, 51.5", \ + "56.7, 56.7, 56.7, 59.7, 65.6"); + } + cell_fall (inslew_load_5x5__30) { + values ("123.1, 123.1, 123.1, 127.2, 134.8", \ + "137.4, 137.4, 137.4, 141.5, 149.1", \ + "157.0, 157.0, 157.0, 161.1, 168.8", \ + "185.4, 185.4, 185.4, 189.5, 197.3", \ + "229.0, 229.0, 229.0, 233.1, 241.1"); + } + fall_transition (inslew_load_5x5__30) { + values ("35.4, 35.4, 35.4, 38.5, 44.4", \ + "38.1, 38.1, 38.1, 41.2, 47.1", \ + "43.0, 43.0, 43.0, 46.1, 52.0", \ + "52.0, 52.0, 52.0, 55.1, 61.1", \ + "68.7, 68.7, 68.7, 71.8, 77.9"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__30) { + values ("130.1, 130.1, 130.1, 133.9, 140.9", \ + "141.9, 141.9, 141.9, 145.8, 152.8", \ + "155.1, 155.1, 155.1, 159.1, 166.3", \ + "171.1, 171.1, 171.1, 175.3, 182.7", \ + "192.7, 192.7, 192.7, 196.9, 204.8"); + } + rise_transition (inslew_load_5x5__30) { + values ("28.4, 28.4, 28.4, 31.4, 37.1", \ + "30.7, 30.7, 30.7, 33.7, 39.6", \ + "34.9, 34.9, 34.9, 37.9, 43.8", \ + "43.0, 43.0, 43.0, 45.9, 51.8", \ + "58.5, 58.5, 58.5, 61.5, 67.4"); + } + cell_fall (inslew_load_5x5__30) { + values ("115.0, 115.0, 115.0, 119.0, 126.6", \ + "125.9, 125.9, 125.9, 129.9, 137.5", \ + "138.8, 138.8, 138.8, 142.9, 150.5", \ + "154.0, 154.0, 154.0, 158.1, 165.8", \ + "171.8, 171.8, 171.8, 176.0, 183.9"); + } + fall_transition (inslew_load_5x5__30) { + values ("34.6, 34.6, 34.6, 37.6, 43.5", \ + "37.0, 37.0, 37.0, 40.1, 46.0", \ + "41.4, 41.4, 41.4, 44.4, 50.4", \ + "49.4, 49.4, 49.4, 52.4, 58.4", \ + "64.2, 64.2, 64.2, 67.3, 73.4"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__30) { + values ("142.5, 142.5, 142.5, 146.5, 153.5", \ + "143.5, 143.5, 143.5, 147.5, 154.6", \ + "141.4, 141.4, 141.4, 145.4, 152.6", \ + "130.2, 130.2, 130.2, 134.3, 141.7", \ + "97.9, 97.9, 97.9, 102.1, 109.9"); + } + rise_transition (inslew_load_5x5__30) { + values ("30.6, 30.6, 30.6, 33.6, 39.4", \ + "32.2, 32.2, 32.2, 35.2, 41.0", \ + "35.4, 35.4, 35.4, 38.4, 44.3", \ + "41.7, 41.7, 41.7, 44.6, 50.5", \ + "53.9, 53.9, 53.9, 56.8, 62.7"); + } + cell_fall (inslew_load_5x5__30) { + values ("130.0, 130.0, 130.0, 134.0, 141.6", \ + "148.7, 148.7, 148.7, 152.8, 160.4", \ + "176.9, 176.9, 176.9, 181.0, 188.7", \ + "222.2, 222.2, 222.2, 226.4, 234.2", \ + "299.8, 299.8, 299.8, 304.0, 312.0"); + } + fall_transition (inslew_load_5x5__30) { + values ("36.2, 36.2, 36.2, 39.2, 45.2", \ + "39.2, 39.2, 39.2, 42.3, 48.3", \ + "44.8, 44.8, 44.8, 47.9, 53.9", \ + "55.1, 55.1, 55.1, 58.2, 64.2", \ + "74.6, 74.6, 74.6, 77.7, 83.8"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__30) { + values ("142.4, 142.4, 142.4, 146.4, 153.4", \ + "136.9, 136.9, 136.9, 140.9, 148.0", \ + "124.5, 124.5, 124.5, 128.5, 135.7", \ + "94.7, 94.7, 94.7, 98.8, 106.1", \ + "26.6, 26.6, 26.6, 30.7, 38.3"); + } + rise_transition (inslew_load_5x5__30) { + values ("31.2, 31.2, 31.2, 34.2, 40.1", \ + "32.4, 32.4, 32.4, 35.4, 41.2", \ + "34.9, 34.9, 34.9, 37.9, 43.7", \ + "39.8, 39.8, 39.8, 42.8, 48.7", \ + "49.6, 49.6, 49.6, 52.6, 58.5"); + } + cell_fall (inslew_load_5x5__30) { + values ("137.3, 137.3, 137.3, 141.3, 148.9", \ + "161.7, 161.7, 161.7, 165.8, 173.5", \ + "201.9, 201.9, 201.9, 206.0, 213.7", \ + "270.9, 270.9, 270.9, 275.1, 283.0", \ + "395.9, 395.9, 395.9, 400.1, 408.2"); + } + fall_transition (inslew_load_5x5__30) { + values ("37.0, 37.0, 37.0, 40.1, 46.0", \ + "40.6, 40.6, 40.6, 43.7, 49.6", \ + "47.2, 47.2, 47.2, 50.3, 56.3", \ + "59.6, 59.6, 59.6, 62.6, 68.7", \ + "82.8, 82.8, 82.8, 85.9, 92.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__30) { + values ("2147.1, 2147.1, 2147.1, 2257.5, 2478.3", \ + "2297.4, 2297.4, 2297.4, 2407.9, 2628.7", \ + "2593.8, 2593.8, 2593.8, 2704.3, 2925.1", \ + "3175.0, 3175.0, 3175.0, 3285.4, 3506.3", \ + "4324.9, 4324.9, 4324.9, 4435.3, 4656.2"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("2224.2, 2224.2, 2224.2, 2334.7, 2555.5", \ + "2419.0, 2419.0, 2419.0, 2529.4, 2750.3", \ + "2796.9, 2796.9, 2796.9, 2907.3, 3128.1", \ + "3532.8, 3532.8, 3532.8, 3643.2, 3864.1", \ + "4978.3, 4978.3, 4978.3, 5088.7, 5309.6"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__30) { + values ("2024.8, 2024.8, 2024.8, 2135.2, 2356.1", \ + "2197.8, 2197.8, 2197.8, 2308.2, 2529.1", \ + "2518.8, 2518.8, 2518.8, 2629.3, 2850.1", \ + "3148.9, 3148.9, 3148.9, 3259.3, 3480.2", \ + "4395.2, 4395.2, 4395.2, 4505.7, 4726.5"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("2121.2, 2121.2, 2121.2, 2231.7, 2452.5", \ + "2286.2, 2286.2, 2286.2, 2396.6, 2617.5", \ + "2603.6, 2603.6, 2603.6, 2714.0, 2934.9", \ + "3221.1, 3221.1, 3221.1, 3331.5, 3552.4", \ + "4429.5, 4429.5, 4429.5, 4539.9, 4760.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__30) { + values ("2249.5, 2249.5, 2249.5, 2359.9, 2580.7", \ + "2378.5, 2378.5, 2378.5, 2488.9, 2709.7", \ + "2636.2, 2636.2, 2636.2, 2746.7, 2967.5", \ + "3148.4, 3148.4, 3148.4, 3258.8, 3479.6", \ + "4163.1, 4163.1, 4163.1, 4273.5, 4494.4"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("2319.9, 2319.9, 2319.9, 2430.3, 2651.2", \ + "2558.0, 2558.0, 2558.0, 2668.4, 2889.3", \ + "3021.0, 3021.0, 3021.0, 3131.4, 3352.3", \ + "3927.5, 3927.5, 3927.5, 4037.9, 4258.7", \ + "5714.2, 5714.2, 5714.2, 5824.6, 6045.5"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__30) { + values ("2316.1, 2316.1, 2316.1, 2426.5, 2647.4", \ + "2415.7, 2415.7, 2415.7, 2526.1, 2747.0", \ + "2624.8, 2624.8, 2624.8, 2735.2, 2956.1", \ + "3038.6, 3038.6, 3038.6, 3149.1, 3369.9", \ + "3865.8, 3865.8, 3865.8, 3976.2, 4197.1"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("2425.8, 2425.8, 2425.8, 2536.2, 2757.1", \ + "2730.4, 2730.4, 2730.4, 2840.8, 3061.7", \ + "3325.4, 3325.4, 3325.4, 3435.8, 3656.7", \ + "4494.2, 4494.2, 4494.2, 4604.6, 4825.5", \ + "6802.7, 6802.7, 6802.7, 6913.1, 7133.9"); + } + } + } + } + + cell (noa22_x1) { + area : 0.0 ; + cell_leakage_power : 0.0076 ; + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 0.0091 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0))" ; + value : 0.0088 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.0049 ; + } + pin (i2) { + direction : input ; + capacitance : 27.53 ; + } + pin (i1) { + direction : input ; + capacitance : 21.77 ; + } + pin (i0) { + direction : input ; + capacitance : 23.11 ; + } + pin (nq) { + function : "((!(i1) & !(i2)) | (!(i0) & !(i2)))" ; + direction : output ; + capacitance : 8.89 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("15.7, 15.7, 15.7, 24.1, 38.7", \ + "18.9, 18.9, 18.9, 28.4, 45.4", \ + "23.9, 23.9, 23.9, 34.4, 53.5", \ + "33.2, 33.2, 33.2, 44.2, 65.1", \ + "51.2, 51.2, 51.2, 62.6, 84.6"); + } + rise_transition (inslew_load_5x5__31) { + values ("31.8, 31.8, 31.8, 42.2, 62.4", \ + "52.3, 52.3, 52.3, 63.1, 84.0", \ + "92.6, 92.6, 92.6, 103.6, 125.2", \ + "172.5, 172.5, 172.5, 183.8, 205.9", \ + "332.1, 332.1, 332.1, 343.5, 366.1"); + } + cell_fall (inslew_load_5x5__31) { + values ("16.6, 16.6, 16.6, 25.2, 40.7", \ + "17.7, 17.7, 17.7, 27.1, 44.2", \ + "18.7, 18.7, 18.7, 28.7, 47.6", \ + "19.8, 19.8, 19.8, 30.4, 50.6", \ + "21.5, 21.5, 21.5, 32.4, 53.6"); + } + fall_transition (inslew_load_5x5__31) { + values ("31.9, 31.9, 31.9, 41.5, 60.5", \ + "50.5, 50.5, 50.5, 60.2, 79.3", \ + "87.0, 87.0, 87.0, 96.9, 116.2", \ + "159.6, 159.6, 159.6, 169.6, 189.3", \ + "304.5, 304.5, 304.5, 314.6, 334.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("10.9, 10.9, 10.9, 20.0, 35.2", \ + "9.8, 9.8, 9.8, 20.3, 38.4", \ + "6.1, 6.1, 6.1, 17.9, 38.8", \ + "-2.0, -2.0, -2.0, 10.5, 33.8", \ + "-18.9, -18.9, -18.9, -5.8, 19.1"); + } + rise_transition (inslew_load_5x5__31) { + values ("26.4, 26.4, 26.4, 37.0, 57.4", \ + "42.7, 42.7, 42.7, 53.8, 75.1", \ + "74.7, 74.7, 74.7, 86.2, 108.4", \ + "138.1, 138.1, 138.1, 149.9, 173.0", \ + "264.6, 264.6, 264.6, 276.6, 300.3"); + } + cell_fall (inslew_load_5x5__31) { + values ("18.1, 18.1, 18.1, 28.1, 45.3", \ + "23.4, 23.4, 23.4, 34.4, 54.0", \ + "32.4, 32.4, 32.4, 44.3, 66.1", \ + "49.4, 49.4, 49.4, 61.8, 85.3", \ + "82.7, 82.7, 82.7, 95.4, 120.1"); + } + fall_transition (inslew_load_5x5__31) { + values ("29.4, 29.4, 29.4, 39.4, 58.8", \ + "50.5, 50.5, 50.5, 60.8, 80.7", \ + "91.3, 91.3, 91.3, 101.9, 122.4", \ + "172.3, 172.3, 172.3, 183.0, 204.1", \ + "333.7, 333.7, 333.7, 344.5, 365.9"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("13.0, 13.0, 13.0, 19.7, 32.2", \ + "10.4, 10.4, 10.4, 18.0, 31.9", \ + "3.9, 3.9, 3.9, 12.3, 27.9", \ + "-10.0, -10.0, -10.0, -1.0, 16.0", \ + "-38.5, -38.5, -38.5, -29.1, -11.0"); + } + rise_transition (inslew_load_5x5__31) { + values ("33.8, 33.8, 33.8, 43.3, 62.2", \ + "49.9, 49.9, 49.9, 59.5, 78.4", \ + "81.6, 81.6, 81.6, 91.5, 110.8", \ + "144.8, 144.8, 144.8, 154.8, 174.6", \ + "271.0, 271.0, 271.0, 281.2, 301.3"); + } + cell_fall (inslew_load_5x5__31) { + values ("19.8, 19.8, 19.8, 26.5, 38.6", \ + "26.5, 26.5, 26.5, 33.9, 47.5", \ + "38.5, 38.5, 38.5, 46.5, 61.5", \ + "61.8, 61.8, 61.8, 70.1, 86.2", \ + "108.0, 108.0, 108.0, 116.5, 133.2"); + } + fall_transition (inslew_load_5x5__31) { + values ("28.3, 28.3, 28.3, 34.1, 45.2", \ + "48.8, 48.8, 48.8, 54.8, 66.3", \ + "89.1, 89.1, 89.1, 95.2, 107.2", \ + "169.3, 169.3, 169.3, 175.5, 187.8", \ + "329.3, 329.3, 329.3, 335.6, 348.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__31) { + values ("273.3, 273.3, 273.3, 384.4, 606.6", \ + "411.5, 411.5, 411.5, 522.6, 744.8", \ + "687.9, 687.9, 687.9, 799.0, 1021.2", \ + "1240.7, 1240.7, 1240.7, 1351.8, 1574.0", \ + "2346.2, 2346.2, 2346.2, 2457.3, 2679.5"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("305.2, 305.2, 305.2, 416.3, 638.5", \ + "451.1, 451.1, 451.1, 562.2, 784.4", \ + "742.9, 742.9, 742.9, 854.0, 1076.2", \ + "1326.5, 1326.5, 1326.5, 1437.6, 1659.8", \ + "2493.7, 2493.7, 2493.7, 2604.8, 2827.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__31) { + values ("210.6, 210.6, 210.6, 321.7, 543.9", \ + "310.0, 310.0, 310.0, 421.1, 643.3", \ + "509.0, 509.0, 509.0, 620.1, 842.3", \ + "906.8, 906.8, 906.8, 1017.9, 1240.1", \ + "1702.6, 1702.6, 1702.6, 1813.7, 2035.8"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("256.4, 256.4, 256.4, 367.5, 589.7", \ + "401.7, 401.7, 401.7, 512.8, 735.0", \ + "692.4, 692.4, 692.4, 803.5, 1025.7", \ + "1273.6, 1273.6, 1273.6, 1384.7, 1606.9", \ + "2436.1, 2436.1, 2436.1, 2547.2, 2769.4"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__31) { + values ("331.2, 331.2, 331.2, 442.3, 664.5", \ + "455.9, 455.9, 455.9, 567.0, 789.2", \ + "705.4, 705.4, 705.4, 816.5, 1038.7", \ + "1204.3, 1204.3, 1204.3, 1315.4, 1537.6", \ + "2202.1, 2202.1, 2202.1, 2313.2, 2535.4"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("401.3, 401.3, 401.3, 512.4, 734.6", \ + "621.4, 621.4, 621.4, 732.5, 954.7", \ + "1061.5, 1061.5, 1061.5, 1172.6, 1394.8", \ + "1941.6, 1941.6, 1941.6, 2052.7, 2274.9", \ + "3702.0, 3702.0, 3702.0, 3813.1, 4035.3"); + } + } + } + } + + cell (noa22_x4) { + area : 0.0 ; + cell_leakage_power : 0.012 ; + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 0.018 ; + } + leakage_power () { + when : "((i0 & i1) | i2)" ; + value : 0.002 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.015 ; + } + pin (i2) { + direction : input ; + capacitance : 23.90 ; + } + pin (i1) { + direction : input ; + capacitance : 32.35 ; + } + pin (i0) { + direction : input ; + capacitance : 33.00 ; + } + pin (nq) { + function : "((!(i1) & !(i2)) | (!(i2) & !(i0)))" ; + direction : output ; + capacitance : 8.99 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__32) { + values ("121.4, 121.4, 121.4, 125.2, 132.2", \ + "134.5, 134.5, 134.5, 138.4, 145.5", \ + "153.1, 153.1, 153.1, 157.1, 164.5", \ + "181.5, 181.5, 181.5, 185.7, 193.3", \ + "228.5, 228.5, 228.5, 232.8, 240.8"); + } + rise_transition (inslew_load_5x5__32) { + values ("25.7, 25.7, 25.7, 28.8, 34.7", \ + "28.1, 28.1, 28.1, 31.3, 37.2", \ + "32.8, 32.8, 32.8, 35.9, 42.0", \ + "41.9, 41.9, 41.9, 45.0, 51.1", \ + "59.6, 59.6, 59.6, 62.6, 68.7"); + } + cell_fall (inslew_load_5x5__32) { + values ("108.6, 108.6, 108.6, 112.7, 120.4", \ + "114.4, 114.4, 114.4, 118.5, 126.3", \ + "120.5, 120.5, 120.5, 124.7, 132.5", \ + "124.8, 124.8, 124.8, 129.0, 136.9", \ + "123.2, 123.2, 123.2, 127.5, 135.6"); + } + fall_transition (inslew_load_5x5__32) { + values ("33.4, 33.4, 33.4, 36.5, 42.5", \ + "35.7, 35.7, 35.7, 38.8, 44.8", \ + "39.9, 39.9, 39.9, 43.0, 49.1", \ + "47.8, 47.8, 47.8, 50.9, 57.0", \ + "62.6, 62.6, 62.6, 65.8, 71.9"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__32) { + values ("116.2, 116.2, 116.2, 120.1, 127.0", \ + "124.9, 124.9, 124.9, 128.8, 135.9", \ + "134.3, 134.3, 134.3, 138.3, 145.5", \ + "143.5, 143.5, 143.5, 147.7, 155.2", \ + "151.5, 151.5, 151.5, 155.7, 163.6"); + } + rise_transition (inslew_load_5x5__32) { + values ("25.1, 25.1, 25.1, 28.2, 34.1", \ + "27.1, 27.1, 27.1, 30.2, 36.2", \ + "30.9, 30.9, 30.9, 34.0, 40.0", \ + "38.1, 38.1, 38.1, 41.2, 47.3", \ + "52.2, 52.2, 52.2, 55.2, 61.3"); + } + cell_fall (inslew_load_5x5__32) { + values ("113.0, 113.0, 113.0, 117.1, 124.8", \ + "124.8, 124.8, 124.8, 128.9, 136.6", \ + "140.2, 140.2, 140.2, 144.3, 152.2", \ + "161.0, 161.0, 161.0, 165.2, 173.1", \ + "191.1, 191.1, 191.1, 195.4, 203.5"); + } + fall_transition (inslew_load_5x5__32) { + values ("33.3, 33.3, 33.3, 36.4, 42.4", \ + "35.9, 35.9, 35.9, 39.0, 45.0", \ + "40.7, 40.7, 40.7, 43.8, 49.9", \ + "49.5, 49.5, 49.5, 52.7, 58.8", \ + "66.1, 66.1, 66.1, 69.3, 75.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__32) { + values ("114.2, 114.2, 114.2, 118.0, 125.0", \ + "118.6, 118.6, 118.6, 122.5, 129.6", \ + "123.0, 123.0, 123.0, 127.0, 134.3", \ + "124.9, 124.9, 124.9, 129.0, 136.5", \ + "120.4, 120.4, 120.4, 124.7, 132.5"); + } + rise_transition (inslew_load_5x5__32) { + values ("25.6, 25.6, 25.6, 28.7, 34.6", \ + "27.4, 27.4, 27.4, 30.6, 36.5", \ + "31.1, 31.1, 31.1, 34.2, 40.2", \ + "38.3, 38.3, 38.3, 41.4, 47.5", \ + "52.3, 52.3, 52.3, 55.4, 61.5"); + } + cell_fall (inslew_load_5x5__32) { + values ("102.7, 102.7, 102.7, 106.8, 114.4", \ + "115.4, 115.4, 115.4, 119.5, 127.2", \ + "133.5, 133.5, 133.5, 137.7, 145.4", \ + "160.6, 160.6, 160.6, 164.8, 172.7", \ + "203.8, 203.8, 203.8, 208.1, 216.2"); + } + fall_transition (inslew_load_5x5__32) { + values ("31.4, 31.4, 31.4, 34.5, 40.5", \ + "34.0, 34.0, 34.0, 37.1, 43.1", \ + "38.9, 38.9, 38.9, 42.0, 48.0", \ + "47.7, 47.7, 47.7, 50.9, 57.0", \ + "64.3, 64.3, 64.3, 67.5, 73.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__32) { + values ("1905.2, 1905.2, 1905.2, 2017.6, 2242.5", \ + "2116.2, 2116.2, 2116.2, 2228.6, 2453.5", \ + "2528.6, 2528.6, 2528.6, 2641.0, 2865.8", \ + "3341.9, 3341.9, 3341.9, 3454.3, 3679.1", \ + "4956.2, 4956.2, 4956.2, 5068.6, 5293.5"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("2069.8, 2069.8, 2069.8, 2182.2, 2407.1", \ + "2248.7, 2248.7, 2248.7, 2361.1, 2586.0", \ + "2601.3, 2601.3, 2601.3, 2713.7, 2938.6", \ + "3293.0, 3293.0, 3293.0, 3405.4, 3630.3", \ + "4656.8, 4656.8, 4656.8, 4769.2, 4994.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__32) { + values ("1830.1, 1830.1, 1830.1, 1942.5, 2167.3", \ + "1990.7, 1990.7, 1990.7, 2103.2, 2328.0", \ + "2302.2, 2302.2, 2302.2, 2414.7, 2639.5", \ + "2914.6, 2914.6, 2914.6, 3027.0, 3251.9", \ + "4124.9, 4124.9, 4124.9, 4237.4, 4462.2"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("2026.2, 2026.2, 2026.2, 2138.6, 2363.5", \ + "2218.3, 2218.3, 2218.3, 2330.7, 2555.5", \ + "2590.9, 2590.9, 2590.9, 2703.4, 2928.2", \ + "3318.8, 3318.8, 3318.8, 3431.3, 3656.1", \ + "4751.8, 4751.8, 4751.8, 4864.2, 5089.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__32) { + values ("1942.7, 1942.7, 1942.7, 2055.1, 2280.0", \ + "2117.0, 2117.0, 2117.0, 2229.4, 2454.3", \ + "2465.3, 2465.3, 2465.3, 2577.7, 2802.6", \ + "3156.6, 3156.6, 3156.6, 3269.0, 3493.9", \ + "4529.1, 4529.1, 4529.1, 4641.6, 4866.4"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("2077.8, 2077.8, 2077.8, 2190.3, 2415.1", \ + "2325.9, 2325.9, 2325.9, 2438.3, 2663.2", \ + "2812.2, 2812.2, 2812.2, 2924.6, 3149.5", \ + "3766.7, 3766.7, 3766.7, 3879.1, 4103.9", \ + "5652.3, 5652.3, 5652.3, 5764.7, 5989.6"); + } + } + } + } + + cell (noa2a22_x1) { + area : 0.0 ; + cell_leakage_power : 0.0061 ; + leakage_power () { + when : "(!(i3) & i2 & !(i1) & i0)" ; + value : 0.0091 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3) | (!(i0) & i1 & i2 & !(i3)))" ; + value : 0.0088 ; + } + leakage_power () { + when : "(i3 & !(i2) & i1 & !(i0))" ; + value : 0.0085 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & !(i1) & i2 & !(i3)))" ; + value : 0.0049 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & !(i2) & i3)))" ; + value : 0.0046 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.00076 ; + } + pin (i3) { + direction : input ; + capacitance : 22.33 ; + } + pin (i2) { + direction : input ; + capacitance : 23.73 ; + } + pin (i1) { + direction : input ; + capacitance : 22.05 ; + } + pin (i0) { + direction : input ; + capacitance : 22.05 ; + } + pin (nq) { + function : "((((!(i1) & !(i3)) | (!(i1) & !(i2))) | (!(i0) & !(i3))) | (!(i0) & !(i2)))" ; + direction : output ; + capacitance : 8.87 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__33) { + values ("15.5, 15.5, 15.5, 23.9, 38.4", \ + "18.7, 18.7, 18.7, 28.2, 45.1", \ + "23.8, 23.8, 23.8, 34.2, 53.3", \ + "33.0, 33.0, 33.0, 44.0, 64.9", \ + "51.1, 51.1, 51.1, 62.4, 84.4"); + } + rise_transition (inslew_load_5x5__33) { + values ("31.7, 31.7, 31.7, 42.1, 62.2", \ + "52.2, 52.2, 52.2, 63.0, 83.8", \ + "92.5, 92.5, 92.5, 103.5, 125.1", \ + "172.4, 172.4, 172.4, 183.7, 205.8", \ + "332.0, 332.0, 332.0, 343.4, 365.9"); + } + cell_fall (inslew_load_5x5__33) { + values ("16.6, 16.6, 16.6, 25.1, 40.6", \ + "17.7, 17.7, 17.7, 27.0, 44.1", \ + "18.7, 18.7, 18.7, 28.7, 47.5", \ + "19.8, 19.8, 19.8, 30.3, 50.5", \ + "21.5, 21.5, 21.5, 32.4, 53.5"); + } + fall_transition (inslew_load_5x5__33) { + values ("31.9, 31.9, 31.9, 41.4, 60.4", \ + "50.5, 50.5, 50.5, 60.2, 79.2", \ + "87.0, 87.0, 87.0, 96.8, 116.2", \ + "159.6, 159.6, 159.6, 169.5, 189.2", \ + "304.5, 304.5, 304.5, 314.6, 334.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__33) { + values ("10.8, 10.8, 10.8, 19.8, 34.9", \ + "9.6, 9.6, 9.6, 20.1, 38.1", \ + "6.0, 6.0, 6.0, 17.7, 38.6", \ + "-2.1, -2.1, -2.1, 10.3, 33.6", \ + "-19.0, -19.0, -19.0, -6.0, 18.9"); + } + rise_transition (inslew_load_5x5__33) { + values ("26.3, 26.3, 26.3, 36.9, 57.2", \ + "42.7, 42.7, 42.7, 53.8, 75.0", \ + "74.6, 74.6, 74.6, 86.1, 108.3", \ + "138.0, 138.0, 138.0, 149.8, 172.8", \ + "264.6, 264.6, 264.6, 276.6, 300.1"); + } + cell_fall (inslew_load_5x5__33) { + values ("18.1, 18.1, 18.1, 28.0, 45.2", \ + "23.4, 23.4, 23.4, 34.4, 54.0", \ + "32.4, 32.4, 32.4, 44.2, 66.0", \ + "49.3, 49.3, 49.3, 61.7, 85.2", \ + "82.7, 82.7, 82.7, 95.4, 120.0"); + } + fall_transition (inslew_load_5x5__33) { + values ("29.4, 29.4, 29.4, 39.4, 58.8", \ + "50.4, 50.4, 50.4, 60.7, 80.7", \ + "91.3, 91.3, 91.3, 101.8, 122.4", \ + "172.3, 172.3, 172.3, 182.9, 204.0", \ + "333.7, 333.7, 333.7, 344.5, 365.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__33) { + values ("16.1, 16.1, 16.1, 22.6, 34.8", \ + "13.8, 13.8, 13.8, 21.2, 34.7", \ + "7.6, 7.6, 7.6, 15.8, 31.1", \ + "-6.0, -6.0, -6.0, 2.7, 19.6", \ + "-34.4, -34.4, -34.4, -25.2, -7.1"); + } + rise_transition (inslew_load_5x5__33) { + values ("37.8, 37.8, 37.8, 47.2, 66.1", \ + "53.9, 53.9, 53.9, 63.5, 82.4", \ + "85.8, 85.8, 85.8, 95.5, 114.8", \ + "149.1, 149.1, 149.1, 159.0, 178.6", \ + "275.3, 275.3, 275.3, 285.4, 305.4"); + } + cell_fall (inslew_load_5x5__33) { + values ("28.0, 28.0, 28.0, 35.8, 50.5", \ + "36.2, 36.2, 36.2, 44.5, 60.3", \ + "50.9, 50.9, 50.9, 59.7, 76.7", \ + "79.5, 79.5, 79.5, 88.7, 106.6", \ + "136.2, 136.2, 136.2, 145.6, 164.1"); + } + fall_transition (inslew_load_5x5__33) { + values ("44.7, 44.7, 44.7, 54.2, 73.2", \ + "70.0, 70.0, 70.0, 79.5, 98.4", \ + "119.8, 119.8, 119.8, 129.3, 148.3", \ + "218.8, 218.8, 218.8, 228.4, 247.5", \ + "416.6, 416.6, 416.6, 426.2, 445.5"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__33) { + values ("12.4, 12.4, 12.4, 19.2, 31.7", \ + "7.0, 7.0, 7.0, 14.8, 28.9", \ + "-6.1, -6.1, -6.1, 2.8, 19.2", \ + "-34.3, -34.3, -34.3, -24.3, -5.7", \ + "-92.1, -92.1, -92.1, -81.4, -61.0"); + } + rise_transition (inslew_load_5x5__33) { + values ("32.9, 32.9, 32.9, 42.4, 61.3", \ + "45.5, 45.5, 45.5, 55.2, 74.2", \ + "70.1, 70.1, 70.1, 80.1, 99.7", \ + "118.7, 118.7, 118.7, 129.1, 149.3", \ + "215.6, 215.6, 215.6, 226.1, 246.9"); + } + cell_fall (inslew_load_5x5__33) { + values ("30.3, 30.3, 30.3, 39.0, 55.1", \ + "43.0, 43.0, 43.0, 52.6, 70.3", \ + "66.1, 66.1, 66.1, 76.3, 95.8", \ + "110.7, 110.7, 110.7, 121.4, 142.1", \ + "199.2, 199.2, 199.2, 210.1, 231.6"); + } + fall_transition (inslew_load_5x5__33) { + values ("41.7, 41.7, 41.7, 51.5, 70.7", \ + "69.2, 69.2, 69.2, 79.1, 98.6", \ + "122.5, 122.5, 122.5, 132.5, 152.4", \ + "227.8, 227.8, 227.8, 238.0, 258.2", \ + "438.0, 438.0, 438.0, 448.2, 468.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__33) { + values ("273.1, 273.1, 273.1, 384.0, 605.8", \ + "411.3, 411.3, 411.3, 522.2, 744.0", \ + "687.7, 687.7, 687.7, 798.6, 1020.3", \ + "1240.5, 1240.5, 1240.5, 1351.3, 1573.1", \ + "2346.0, 2346.0, 2346.0, 2456.9, 2678.7"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("305.0, 305.0, 305.0, 415.9, 637.7", \ + "450.9, 450.9, 450.9, 561.8, 783.6", \ + "742.7, 742.7, 742.7, 853.6, 1075.4", \ + "1326.3, 1326.3, 1326.3, 1437.2, 1659.0", \ + "2493.5, 2493.5, 2493.5, 2604.4, 2826.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__33) { + values ("210.4, 210.4, 210.4, 321.2, 543.0", \ + "309.8, 309.8, 309.8, 420.7, 642.5", \ + "508.7, 508.7, 508.7, 619.6, 841.4", \ + "906.6, 906.6, 906.6, 1017.5, 1239.3", \ + "1702.3, 1702.3, 1702.3, 1813.2, 2035.0"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("256.2, 256.2, 256.2, 367.1, 588.9", \ + "401.5, 401.5, 401.5, 512.4, 734.2", \ + "692.1, 692.1, 692.1, 803.0, 1024.8", \ + "1273.4, 1273.4, 1273.4, 1384.3, 1606.0", \ + "2435.9, 2435.9, 2435.9, 2546.8, 2768.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__33) { + values ("378.5, 378.5, 378.5, 489.4, 711.2", \ + "503.2, 503.2, 503.2, 614.1, 835.9", \ + "752.7, 752.7, 752.7, 863.6, 1085.3", \ + "1251.6, 1251.6, 1251.6, 1362.5, 1584.2", \ + "2249.4, 2249.4, 2249.4, 2360.3, 2582.1"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("465.1, 465.1, 465.1, 576.0, 797.8", \ + "685.2, 685.2, 685.2, 796.1, 1017.8", \ + "1125.3, 1125.3, 1125.3, 1236.1, 1457.9", \ + "2005.4, 2005.4, 2005.4, 2116.3, 2338.1", \ + "3765.8, 3765.8, 3765.8, 3876.7, 4098.4"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__33) { + values ("315.5, 315.5, 315.5, 426.4, 648.2", \ + "401.3, 401.3, 401.3, 512.2, 734.0", \ + "572.9, 572.9, 572.9, 683.8, 905.6", \ + "916.0, 916.0, 916.0, 1026.9, 1248.7", \ + "1602.3, 1602.3, 1602.3, 1713.2, 1935.0"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("405.7, 405.7, 405.7, 516.6, 738.4", \ + "614.6, 614.6, 614.6, 725.4, 947.2", \ + "1032.3, 1032.3, 1032.3, 1143.1, 1364.9", \ + "1867.7, 1867.7, 1867.7, 1978.5, 2200.3", \ + "3538.5, 3538.5, 3538.5, 3649.3, 3871.1"); + } + } + } + } + + cell (noa2a22_x4) { + area : 0.0 ; + cell_leakage_power : 0.011 ; + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3))" ; + value : 0.015 ; + } + leakage_power () { + when : "((i0 & i1) | (i2 & i3))" ; + value : 0.002 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))))" ; + value : 0.014 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.012 ; + } + pin (i3) { + direction : input ; + capacitance : 28.56 ; + } + pin (i2) { + direction : input ; + capacitance : 25.04 ; + } + pin (i1) { + direction : input ; + capacitance : 22.22 ; + } + pin (i0) { + direction : input ; + capacitance : 21.98 ; + } + pin (nq) { + function : "((!(i0) & (!(i3) | !(i2))) | (!((i3 & i2)) & !(i1)))" ; + direction : output ; + capacitance : 8.97 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("122.5, 122.5, 122.5, 126.3, 133.2", \ + "135.8, 135.8, 135.8, 139.6, 146.6", \ + "153.1, 153.1, 153.1, 157.0, 164.3", \ + "177.7, 177.7, 177.7, 181.8, 189.3", \ + "216.1, 216.1, 216.1, 220.5, 228.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("24.3, 24.3, 24.3, 27.4, 33.2", \ + "26.8, 26.8, 26.8, 29.9, 35.8", \ + "31.3, 31.3, 31.3, 34.4, 40.4", \ + "40.2, 40.2, 40.2, 43.2, 49.3", \ + "57.3, 57.3, 57.3, 60.3, 66.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("115.5, 115.5, 115.5, 119.6, 127.1", \ + "122.1, 122.1, 122.1, 126.2, 133.8", \ + "129.6, 129.6, 129.6, 133.7, 141.5", \ + "136.5, 136.5, 136.5, 140.7, 148.5", \ + "140.1, 140.1, 140.1, 144.3, 152.4"); + } + fall_transition (inslew_load_5x5__21) { + values ("30.9, 30.9, 30.9, 34.0, 40.0", \ + "33.2, 33.2, 33.2, 36.2, 42.2", \ + "37.4, 37.4, 37.4, 40.5, 46.5", \ + "45.5, 45.5, 45.5, 48.6, 54.7", \ + "61.0, 61.0, 61.0, 64.1, 70.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("118.2, 118.2, 118.2, 122.0, 128.8", \ + "127.4, 127.4, 127.4, 131.3, 138.2", \ + "136.5, 136.5, 136.5, 140.4, 147.5", \ + "143.1, 143.1, 143.1, 147.2, 154.5", \ + "144.1, 144.1, 144.1, 148.3, 156.0"); + } + rise_transition (inslew_load_5x5__21) { + values ("23.7, 23.7, 23.7, 26.8, 32.7", \ + "25.7, 25.7, 25.7, 28.9, 34.7", \ + "29.5, 29.5, 29.5, 32.6, 38.5", \ + "36.5, 36.5, 36.5, 39.6, 45.6", \ + "50.2, 50.2, 50.2, 53.2, 59.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("120.8, 120.8, 120.8, 124.9, 132.5", \ + "133.9, 133.9, 133.9, 138.0, 145.6", \ + "151.2, 151.2, 151.2, 155.4, 163.1", \ + "175.0, 175.0, 175.0, 179.2, 187.1", \ + "210.9, 210.9, 210.9, 215.1, 223.2"); + } + fall_transition (inslew_load_5x5__21) { + values ("30.7, 30.7, 30.7, 33.8, 39.8", \ + "33.4, 33.4, 33.4, 36.5, 42.4", \ + "38.2, 38.2, 38.2, 41.3, 47.3", \ + "47.3, 47.3, 47.3, 50.4, 56.5", \ + "64.5, 64.5, 64.5, 67.6, 73.7"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("118.7, 118.7, 118.7, 122.5, 129.4", \ + "122.8, 122.8, 122.8, 126.7, 133.6", \ + "126.1, 126.1, 126.1, 130.0, 137.1", \ + "124.9, 124.9, 124.9, 129.1, 136.4", \ + "113.4, 113.4, 113.4, 117.6, 125.4"); + } + rise_transition (inslew_load_5x5__21) { + values ("24.7, 24.7, 24.7, 27.8, 33.6", \ + "26.4, 26.4, 26.4, 29.6, 35.5", \ + "30.0, 30.0, 30.0, 33.1, 39.1", \ + "37.0, 37.0, 37.0, 40.0, 46.1", \ + "50.5, 50.5, 50.5, 53.5, 59.5"); + } + cell_fall (inslew_load_5x5__21) { + values ("127.1, 127.1, 127.1, 131.2, 138.8", \ + "139.7, 139.7, 139.7, 143.8, 151.5", \ + "159.8, 159.8, 159.8, 163.9, 171.7", \ + "192.1, 192.1, 192.1, 196.3, 204.2", \ + "249.5, 249.5, 249.5, 253.8, 262.0"); + } + fall_transition (inslew_load_5x5__21) { + values ("32.6, 32.6, 32.6, 35.6, 41.6", \ + "35.5, 35.5, 35.5, 38.6, 44.6", \ + "41.1, 41.1, 41.1, 44.2, 50.3", \ + "51.9, 51.9, 51.9, 55.0, 61.1", \ + "72.8, 72.8, 72.8, 76.0, 82.1"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("114.7, 114.7, 114.7, 118.5, 125.3", \ + "115.8, 115.8, 115.8, 119.6, 126.5", \ + "112.4, 112.4, 112.4, 116.3, 123.3", \ + "96.9, 96.9, 96.9, 100.9, 108.2", \ + "54.9, 54.9, 54.9, 59.1, 66.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("24.1, 24.1, 24.1, 27.2, 33.1", \ + "25.5, 25.5, 25.5, 28.6, 34.5", \ + "28.4, 28.4, 28.4, 31.5, 37.4", \ + "33.8, 33.8, 33.8, 36.9, 42.9", \ + "44.2, 44.2, 44.2, 47.3, 53.4"); + } + cell_fall (inslew_load_5x5__21) { + values ("132.0, 132.0, 132.0, 136.1, 143.7", \ + "151.1, 151.1, 151.1, 155.2, 162.9", \ + "181.0, 181.0, 181.0, 185.2, 193.0", \ + "230.3, 230.3, 230.3, 234.5, 242.4", \ + "319.6, 319.6, 319.6, 323.8, 332.0"); + } + fall_transition (inslew_load_5x5__21) { + values ("32.3, 32.3, 32.3, 35.3, 41.3", \ + "35.5, 35.5, 35.5, 38.6, 44.6", \ + "41.6, 41.6, 41.6, 44.7, 50.8", \ + "53.1, 53.1, 53.1, 56.2, 62.3", \ + "75.3, 75.3, 75.3, 78.4, 84.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1703.8, 1703.8, 1703.8, 1815.9, 2040.1", \ + "1876.1, 1876.1, 1876.1, 1988.2, 2212.4", \ + "2206.2, 2206.2, 2206.2, 2318.3, 2542.4", \ + "2852.8, 2852.8, 2852.8, 2964.9, 3189.0", \ + "4130.9, 4130.9, 4130.9, 4243.0, 4467.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1837.0, 1837.0, 1837.0, 1949.0, 2173.2", \ + "1984.0, 1984.0, 1984.0, 2096.1, 2320.2", \ + "2274.5, 2274.5, 2274.5, 2386.6, 2610.8", \ + "2846.5, 2846.5, 2846.5, 2958.6, 3182.8", \ + "3974.9, 3974.9, 3974.9, 4087.0, 4311.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1646.2, 1646.2, 1646.2, 1758.3, 1982.5", \ + "1779.5, 1779.5, 1779.5, 1891.6, 2115.8", \ + "2033.1, 2033.1, 2033.1, 2145.2, 2369.4", \ + "2524.1, 2524.1, 2524.1, 2636.1, 2860.3", \ + "3488.5, 3488.5, 3488.5, 3600.6, 3824.7"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1802.4, 1802.4, 1802.4, 1914.5, 2138.6", \ + "1963.0, 1963.0, 1963.0, 2075.1, 2299.2", \ + "2272.8, 2272.8, 2272.8, 2384.9, 2609.0", \ + "2877.0, 2877.0, 2877.0, 2989.1, 3213.2", \ + "4064.3, 4064.3, 4064.3, 4176.4, 4400.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1779.9, 1779.9, 1779.9, 1892.0, 2116.1", \ + "1916.1, 1916.1, 1916.1, 2028.2, 2252.3", \ + "2189.0, 2189.0, 2189.0, 2301.1, 2525.2", \ + "2727.9, 2727.9, 2727.9, 2840.0, 3064.2", \ + "3795.1, 3795.1, 3795.1, 3907.1, 4131.3"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1977.5, 1977.5, 1977.5, 2089.6, 2313.7", \ + "2187.6, 2187.6, 2187.6, 2299.7, 2523.9", \ + "2602.1, 2602.1, 2602.1, 2714.2, 2938.4", \ + "3423.1, 3423.1, 3423.1, 3535.2, 3759.3", \ + "5054.6, 5054.6, 5054.6, 5166.7, 5390.8"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1723.0, 1723.0, 1723.0, 1835.1, 2059.2", \ + "1824.0, 1824.0, 1824.0, 1936.1, 2160.2", \ + "2026.0, 2026.0, 2026.0, 2138.0, 2362.2", \ + "2420.7, 2420.7, 2420.7, 2532.8, 2757.0", \ + "3197.0, 3197.0, 3197.0, 3309.0, 3533.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1933.8, 1933.8, 1933.8, 2045.9, 2270.1", \ + "2147.5, 2147.5, 2147.5, 2259.5, 2483.7", \ + "2566.0, 2566.0, 2566.0, 2678.1, 2902.2", \ + "3385.3, 3385.3, 3385.3, 3497.4, 3721.6", \ + "5009.7, 5009.7, 5009.7, 5121.8, 5346.0"); + } + } + } + } + + cell (noa2a2a23_x1) { + area : 0.0 ; + cell_leakage_power : 0.0082 ; + leakage_power () { + when : "(i5 & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 0.014 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & (i4 ^ i5)))) | (!(i0) & i1 & (i2 ^ i3) & (i4 ^ i5)))" ; + value : 0.013 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i0) & !(i1) & i2 & !(i3) & !(i4) & i5))" ; + value : 0.0095 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & (i3 ^ i4) & !(i5)) | (!(i1) & !(i2) & i3 & i4 & !(i5))))" ; + value : 0.0088 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & (i3 ^ i4) & !(i5)) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))))))" ; + value : 0.0092 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i1) & !(i2) & (i3 ^ i4) & !(i5))))" ; + value : 0.005 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))))" ; + value : 0.0053 ; + } + leakage_power () { + when : "(!(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0011 ; + } + pin (i5) { + direction : input ; + capacitance : 25.63 ; + } + pin (i4) { + direction : input ; + capacitance : 32.20 ; + } + pin (i3) { + direction : input ; + capacitance : 30.72 ; + } + pin (i2) { + direction : input ; + capacitance : 29.52 ; + } + pin (i1) { + direction : input ; + capacitance : 21.77 ; + } + pin (i0) { + direction : input ; + capacitance : 21.77 ; + } + pin (nq) { + function : "(((((((((!(i5) & !(i3)) & !(i0)) | ((!(i5) & !(i3)) & !(i1))) | ((!(i5) & !(i2)) & !(i0))) | ((!(i5) & !(i2)) & !(i1))) | ((!(i4) & !(i3)) & !(i0))) | ((!(i4) & !(i3)) & !(i1))) | ((!(i4) & !(i2)) & !(i0))) | ((!(i4) & !(i2)) & !(i1)))" ; + direction : output ; + capacitance : 10.65 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("31.1, 31.1, 31.1, 40.9, 60.1", \ + "29.8, 29.8, 29.8, 40.0, 60.1", \ + "25.8, 25.8, 25.8, 36.9, 58.0", \ + "16.4, 16.4, 16.4, 28.1, 50.9", \ + "-3.8, -3.8, -3.8, 8.4, 32.5"); + } + rise_transition (inslew_load_5x5__34) { + values ("68.0, 68.0, 68.0, 84.8, 118.6", \ + "87.8, 87.8, 87.8, 104.2, 137.4", \ + "126.9, 126.9, 126.9, 143.4, 177.0", \ + "205.7, 205.7, 205.7, 222.3, 255.3", \ + "363.1, 363.1, 363.1, 379.8, 413.0"); + } + cell_fall (inslew_load_5x5__34) { + values ("38.1, 38.1, 38.1, 46.9, 64.1", \ + "47.0, 47.0, 47.0, 56.4, 74.6", \ + "62.4, 62.4, 62.4, 72.5, 92.1", \ + "91.4, 91.4, 91.4, 102.1, 123.0", \ + "148.3, 148.3, 148.3, 159.4, 183.2"); + } + fall_transition (inslew_load_5x5__34) { + values ("56.9, 56.9, 56.9, 68.3, 91.2", \ + "82.2, 82.2, 82.2, 93.5, 116.3", \ + "132.0, 132.0, 132.0, 143.4, 166.1", \ + "231.1, 231.1, 231.1, 242.6, 265.4", \ + "429.0, 429.0, 429.0, 440.5, 465.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("26.7, 26.7, 26.7, 36.6, 56.0", \ + "22.0, 22.0, 22.0, 32.5, 52.8", \ + "10.8, 10.8, 10.8, 22.4, 44.3", \ + "-14.2, -14.2, -14.2, -1.4, 22.6", \ + "-66.5, -66.5, -66.5, -52.8, -26.5"); + } + rise_transition (inslew_load_5x5__34) { + values ("60.8, 60.8, 60.8, 77.5, 111.3", \ + "75.9, 75.9, 75.9, 92.3, 125.4", \ + "105.1, 105.1, 105.1, 121.7, 155.7", \ + "164.2, 164.2, 164.2, 181.0, 214.3", \ + "281.8, 281.8, 281.8, 298.8, 332.7"); + } + cell_fall (inslew_load_5x5__34) { + values ("41.6, 41.6, 41.6, 51.2, 69.4", \ + "55.4, 55.4, 55.4, 66.0, 86.1", \ + "79.4, 79.4, 79.4, 91.0, 113.2", \ + "124.6, 124.6, 124.6, 137.0, 161.0", \ + "213.3, 213.3, 213.3, 226.3, 251.6"); + } + fall_transition (inslew_load_5x5__34) { + values ("54.2, 54.2, 54.2, 65.8, 88.8", \ + "81.9, 81.9, 81.9, 93.6, 116.7", \ + "135.3, 135.3, 135.3, 147.3, 170.9", \ + "240.9, 240.9, 240.9, 253.0, 277.0", \ + "451.1, 451.1, 451.1, 463.4, 487.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("29.5, 29.5, 29.5, 39.9, 60.0", \ + "34.1, 34.1, 34.1, 45.3, 66.6", \ + "40.9, 40.9, 40.9, 53.3, 76.5", \ + "52.9, 52.9, 52.9, 66.1, 91.3", \ + "75.8, 75.8, 75.8, 89.6, 116.3"); + } + rise_transition (inslew_load_5x5__34) { + values ("58.2, 58.2, 58.2, 75.3, 109.2", \ + "82.2, 82.2, 82.2, 99.0, 133.2", \ + "129.2, 129.2, 129.2, 146.3, 180.2", \ + "222.7, 222.7, 222.7, 240.0, 274.3", \ + "409.2, 409.2, 409.2, 426.7, 461.4"); + } + cell_fall (inslew_load_5x5__34) { + values ("25.0, 25.0, 25.0, 34.4, 52.2", \ + "26.9, 26.9, 26.9, 37.3, 56.7", \ + "28.5, 28.5, 28.5, 40.0, 61.4", \ + "30.1, 30.1, 30.1, 42.3, 65.7", \ + "32.1, 32.1, 32.1, 44.9, 69.7"); + } + fall_transition (inslew_load_5x5__34) { + values ("41.1, 41.1, 41.1, 52.5, 75.3", \ + "59.8, 59.8, 59.8, 71.3, 94.0", \ + "96.5, 96.5, 96.5, 108.2, 131.1", \ + "169.2, 169.2, 169.2, 181.1, 204.5", \ + "314.2, 314.2, 314.2, 326.2, 350.0"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("25.0, 25.0, 25.0, 35.7, 55.8", \ + "25.6, 25.6, 25.6, 37.4, 59.2", \ + "24.1, 24.1, 24.1, 37.3, 61.7", \ + "18.7, 18.7, 18.7, 33.2, 60.3", \ + "6.3, 6.3, 6.3, 21.6, 51.0"); + } + rise_transition (inslew_load_5x5__34) { + values ("51.2, 51.2, 51.2, 68.4, 102.2", \ + "70.1, 70.1, 70.1, 87.1, 120.8", \ + "106.9, 106.9, 106.9, 124.3, 158.4", \ + "179.6, 179.6, 179.6, 197.3, 232.2", \ + "324.5, 324.5, 324.5, 342.4, 378.0"); + } + cell_fall (inslew_load_5x5__34) { + values ("27.8, 27.8, 27.8, 38.4, 57.6", \ + "34.2, 34.2, 34.2, 46.2, 68.0", \ + "44.0, 44.0, 44.0, 57.3, 82.0", \ + "61.4, 61.4, 61.4, 75.7, 102.9", \ + "95.1, 95.1, 95.1, 110.0, 138.9"); + } + fall_transition (inslew_load_5x5__34) { + values ("39.1, 39.1, 39.1, 50.8, 73.9", \ + "60.4, 60.4, 60.4, 72.5, 95.9", \ + "101.5, 101.5, 101.5, 113.9, 138.1", \ + "182.6, 182.6, 182.6, 195.3, 220.2", \ + "344.1, 344.1, 344.1, 357.0, 382.5"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("19.1, 19.1, 19.1, 31.9, 53.4", \ + "23.7, 23.7, 23.7, 38.4, 64.1", \ + "30.4, 30.4, 30.4, 46.9, 76.5", \ + "42.2, 42.2, 42.2, 59.9, 92.9", \ + "64.9, 64.9, 64.9, 83.3, 118.7"); + } + rise_transition (inslew_load_5x5__34) { + values ("38.8, 38.8, 38.8, 56.8, 91.0", \ + "61.5, 61.5, 61.5, 80.2, 116.5", \ + "105.6, 105.6, 105.6, 124.9, 162.4", \ + "192.8, 192.8, 192.8, 212.5, 251.1", \ + "366.5, 366.5, 366.5, 386.4, 425.9"); + } + cell_fall (inslew_load_5x5__34) { + values ("17.3, 17.3, 17.3, 29.2, 49.5", \ + "18.4, 18.4, 18.4, 32.0, 55.6", \ + "18.4, 18.4, 18.4, 33.6, 60.7", \ + "16.9, 16.9, 16.9, 33.2, 63.5", \ + "13.2, 13.2, 13.2, 30.2, 62.6"); + } + fall_transition (inslew_load_5x5__34) { + values ("28.6, 28.6, 28.6, 40.6, 63.9", \ + "45.9, 45.9, 45.9, 58.4, 82.4", \ + "79.2, 79.2, 79.2, 92.2, 117.2", \ + "145.1, 145.1, 145.1, 158.4, 184.3", \ + "276.2, 276.2, 276.2, 289.8, 316.5"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("24.5, 24.5, 24.5, 36.6, 57.7", \ + "34.2, 34.2, 34.2, 47.9, 72.4", \ + "51.3, 51.3, 51.3, 66.3, 93.9", \ + "83.7, 83.7, 83.7, 99.6, 129.7", \ + "147.7, 147.7, 147.7, 164.1, 195.9"); + } + rise_transition (inslew_load_5x5__34) { + values ("46.1, 46.1, 46.1, 64.0, 98.1", \ + "74.7, 74.7, 74.7, 93.1, 129.1", \ + "130.3, 130.3, 130.3, 149.1, 186.1", \ + "240.4, 240.4, 240.4, 259.5, 297.2", \ + "459.7, 459.7, 459.7, 479.1, 517.4"); + } + cell_fall (inslew_load_5x5__34) { + values ("15.5, 15.5, 15.5, 25.7, 44.2", \ + "12.6, 12.6, 12.6, 24.1, 44.8", \ + "4.9, 4.9, 4.9, 17.8, 41.2", \ + "-11.9, -11.9, -11.9, 1.9, 28.0", \ + "-46.6, -46.6, -46.6, -32.0, -3.9"); + } + fall_transition (inslew_load_5x5__34) { + values ("30.7, 30.7, 30.7, 42.1, 64.9", \ + "45.3, 45.3, 45.3, 57.1, 80.0", \ + "73.9, 73.9, 73.9, 86.0, 109.5", \ + "130.7, 130.7, 130.7, 143.0, 167.2", \ + "243.8, 243.8, 243.8, 256.3, 281.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__34) { + values ("506.8, 506.8, 506.8, 639.9, 906.2", \ + "631.5, 631.5, 631.5, 764.6, 1031.0", \ + "880.9, 880.9, 880.9, 1014.1, 1280.4", \ + "1379.8, 1379.8, 1379.8, 1513.0, 1779.3", \ + "2377.7, 2377.7, 2377.7, 2510.8, 2777.1"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("607.8, 607.8, 607.8, 741.0, 1007.3", \ + "827.9, 827.9, 827.9, 961.0, 1227.4", \ + "1268.0, 1268.0, 1268.0, 1401.1, 1667.4", \ + "2148.1, 2148.1, 2148.1, 2281.3, 2547.6", \ + "3908.5, 3908.5, 3908.5, 4041.7, 4308.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__34) { + values ("443.8, 443.8, 443.8, 576.9, 843.3", \ + "529.6, 529.6, 529.6, 662.7, 929.0", \ + "701.1, 701.1, 701.1, 834.3, 1100.6", \ + "1044.3, 1044.3, 1044.3, 1177.4, 1443.8", \ + "1730.6, 1730.6, 1730.6, 1863.7, 2130.1"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("548.4, 548.4, 548.4, 681.6, 947.9", \ + "757.3, 757.3, 757.3, 890.4, 1156.7", \ + "1175.0, 1175.0, 1175.0, 1308.1, 1574.4", \ + "2010.4, 2010.4, 2010.4, 2143.5, 2409.8", \ + "3681.2, 3681.2, 3681.2, 3814.3, 4080.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__34) { + values ("423.7, 423.7, 423.7, 556.9, 823.2", \ + "561.9, 561.9, 561.9, 695.1, 961.4", \ + "838.3, 838.3, 838.3, 971.4, 1237.8", \ + "1391.1, 1391.1, 1391.1, 1524.2, 1790.5", \ + "2496.6, 2496.6, 2496.6, 2629.8, 2896.1"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("412.6, 412.6, 412.6, 545.7, 812.0", \ + "558.5, 558.5, 558.5, 691.6, 957.9", \ + "850.3, 850.3, 850.3, 983.4, 1249.7", \ + "1433.9, 1433.9, 1433.9, 1567.0, 1833.3", \ + "2601.1, 2601.1, 2601.1, 2734.2, 3000.5"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__34) { + values ("360.9, 360.9, 360.9, 494.1, 760.4", \ + "460.4, 460.4, 460.4, 593.6, 859.9", \ + "659.3, 659.3, 659.3, 792.5, 1058.8", \ + "1057.2, 1057.2, 1057.2, 1190.4, 1456.7", \ + "1852.9, 1852.9, 1852.9, 1986.1, 2252.4"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("363.7, 363.7, 363.7, 496.9, 763.2", \ + "509.1, 509.1, 509.1, 642.2, 908.5", \ + "799.7, 799.7, 799.7, 932.8, 1199.2", \ + "1380.9, 1380.9, 1380.9, 1514.1, 1780.4", \ + "2543.4, 2543.4, 2543.4, 2676.6, 2942.9"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__34) { + values ("239.4, 239.4, 239.4, 372.6, 638.9", \ + "345.7, 345.7, 345.7, 478.8, 745.2", \ + "558.2, 558.2, 558.2, 691.4, 957.7", \ + "983.3, 983.3, 983.3, 1116.4, 1382.7", \ + "1833.4, 1833.4, 1833.4, 1966.5, 2232.8"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("241.1, 241.1, 241.1, 374.2, 640.5", \ + "349.0, 349.0, 349.0, 482.1, 748.4", \ + "564.8, 564.8, 564.8, 697.9, 964.3", \ + "996.4, 996.4, 996.4, 1129.6, 1395.9", \ + "1859.7, 1859.7, 1859.7, 1992.9, 2259.2"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__34) { + values ("301.7, 301.7, 301.7, 434.8, 701.1", \ + "446.1, 446.1, 446.1, 579.3, 845.6", \ + "735.1, 735.1, 735.1, 868.3, 1134.6", \ + "1313.0, 1313.0, 1313.0, 1446.2, 1712.5", \ + "2468.8, 2468.8, 2468.8, 2602.0, 2868.3"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("284.6, 284.6, 284.6, 417.8, 684.1", \ + "387.9, 387.9, 387.9, 521.1, 787.4", \ + "594.4, 594.4, 594.4, 727.6, 993.9", \ + "1007.4, 1007.4, 1007.4, 1140.6, 1406.9", \ + "1833.5, 1833.5, 1833.5, 1966.7, 2233.0"); + } + } + } + } + + cell (noa2a2a23_x4) { + area : 0.0 ; + cell_leakage_power : 0.017 ; + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & (i4 ^ i5)) | (!(i2) & i3 & !(i4) & i5))) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5))" ; + value : 0.025 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & !(i5)) | (!(i0) & i1 & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & (i4 ^ i5)))))" ; + value : 0.024 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & (i3 ^ i4) & !(i5)) | (!(i1) & !(i2) & i3 & i4 & !(i5))))" ; + value : 0.02 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & ((i3 & !(i4) & !(i5)) | (!(i3) & (i4 ^ i5)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i1) & ((i2 & !(i3) & (i4 ^ i5)) | (!(i2) & i3 & !(i4) & i5))))))" ; + value : 0.021 ; + } + leakage_power () { + when : "((i0 & i1) | (i2 & i3) | (i4 & i5))" ; + value : 0.002 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i1) & !(i2) & (i3 ^ i4) & !(i5))))" ; + value : 0.016 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))))" ; + value : 0.017 ; + } + leakage_power () { + when : "(!(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.013 ; + } + pin (i5) { + direction : input ; + capacitance : 22.13 ; + } + pin (i4) { + direction : input ; + capacitance : 21.77 ; + } + pin (i3) { + direction : input ; + capacitance : 22.48 ; + } + pin (i2) { + direction : input ; + capacitance : 22.13 ; + } + pin (i1) { + direction : input ; + capacitance : 24.59 ; + } + pin (i0) { + direction : input ; + capacitance : 21.77 ; + } + pin (nq) { + function : "((!(i4) & ((!(i2) & (!(i1) | !(i0))) | (!((i1 & i0)) & !(i3)))) | (!(i2) & !((i1 & i0)) & !(i5)) | (!((i1 & i0)) & !(i3) & !(i5)))" ; + direction : output ; + capacitance : 8.77 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("127.9, 127.9, 127.9, 131.7, 138.6", \ + "131.0, 131.0, 131.0, 134.9, 141.9", \ + "135.1, 135.1, 135.1, 139.0, 146.2", \ + "138.1, 138.1, 138.1, 142.2, 149.6", \ + "137.7, 137.7, 137.7, 142.0, 149.7"); + } + rise_transition (inslew_load_5x5__35) { + values ("27.1, 27.1, 27.1, 30.1, 36.0", \ + "29.2, 29.2, 29.2, 32.3, 38.1", \ + "33.6, 33.6, 33.6, 36.7, 42.6", \ + "42.1, 42.1, 42.1, 45.1, 51.1", \ + "59.0, 59.0, 59.0, 61.9, 67.9"); + } + cell_fall (inslew_load_5x5__35) { + values ("116.1, 116.1, 116.1, 120.1, 127.6", \ + "128.7, 128.7, 128.7, 132.7, 140.3", \ + "148.2, 148.2, 148.2, 152.3, 159.9", \ + "179.5, 179.5, 179.5, 183.7, 191.4", \ + "234.9, 234.9, 234.9, 239.1, 247.1"); + } + fall_transition (inslew_load_5x5__35) { + values ("32.0, 32.0, 32.0, 35.1, 40.9", \ + "35.0, 35.0, 35.0, 38.0, 43.9", \ + "40.6, 40.6, 40.6, 43.7, 49.6", \ + "51.2, 51.2, 51.2, 54.3, 60.3", \ + "71.8, 71.8, 71.8, 74.9, 80.9"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("122.3, 122.3, 122.3, 126.0, 132.9", \ + "121.5, 121.5, 121.5, 125.3, 132.2", \ + "117.3, 117.3, 117.3, 121.2, 128.3", \ + "103.5, 103.5, 103.5, 107.6, 114.9", \ + "68.2, 68.2, 68.2, 72.4, 80.0"); + } + rise_transition (inslew_load_5x5__35) { + values ("26.3, 26.3, 26.3, 29.3, 35.1", \ + "27.9, 27.9, 27.9, 31.0, 36.8", \ + "31.2, 31.2, 31.2, 34.2, 40.1", \ + "37.7, 37.7, 37.7, 40.7, 46.6", \ + "50.4, 50.4, 50.4, 53.3, 59.3"); + } + cell_fall (inslew_load_5x5__35) { + values ("120.6, 120.6, 120.6, 124.6, 132.1", \ + "139.1, 139.1, 139.1, 143.1, 150.7", \ + "167.8, 167.8, 167.8, 171.9, 179.5", \ + "215.6, 215.6, 215.6, 219.7, 227.5", \ + "300.5, 300.5, 300.5, 304.7, 312.8"); + } + fall_transition (inslew_load_5x5__35) { + values ("31.8, 31.8, 31.8, 34.8, 40.6", \ + "35.1, 35.1, 35.1, 38.1, 44.0", \ + "41.1, 41.1, 41.1, 44.1, 50.1", \ + "52.4, 52.4, 52.4, 55.5, 61.4", \ + "73.9, 73.9, 73.9, 77.0, 83.1"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("125.4, 125.4, 125.4, 129.2, 136.0", \ + "136.0, 136.0, 136.0, 139.8, 146.8", \ + "152.8, 152.8, 152.8, 156.7, 164.0", \ + "179.6, 179.6, 179.6, 183.7, 191.2", \ + "225.3, 225.3, 225.3, 229.6, 237.6"); + } + rise_transition (inslew_load_5x5__35) { + values ("26.1, 26.1, 26.1, 29.1, 34.9", \ + "28.7, 28.7, 28.7, 31.7, 37.5", \ + "33.9, 33.9, 33.9, 36.9, 42.8", \ + "44.1, 44.1, 44.1, 47.1, 53.1", \ + "64.1, 64.1, 64.1, 67.0, 72.9"); + } + cell_fall (inslew_load_5x5__35) { + values ("101.8, 101.8, 101.8, 105.8, 113.2", \ + "107.9, 107.9, 107.9, 111.9, 119.4", \ + "114.6, 114.6, 114.6, 118.7, 126.2", \ + "120.5, 120.5, 120.5, 124.6, 132.3", \ + "122.7, 122.7, 122.7, 126.8, 134.7"); + } + fall_transition (inslew_load_5x5__35) { + values ("30.1, 30.1, 30.1, 33.1, 39.0", \ + "32.4, 32.4, 32.4, 35.4, 41.3", \ + "36.7, 36.7, 36.7, 39.7, 45.6", \ + "44.8, 44.8, 44.8, 47.8, 53.8", \ + "60.0, 60.0, 60.0, 63.1, 69.1"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("119.8, 119.8, 119.8, 123.5, 130.3", \ + "126.1, 126.1, 126.1, 129.9, 136.8", \ + "133.9, 133.9, 133.9, 137.8, 144.9", \ + "141.9, 141.9, 141.9, 146.0, 153.3", \ + "149.2, 149.2, 149.2, 153.5, 161.2"); + } + rise_transition (inslew_load_5x5__35) { + values ("25.3, 25.3, 25.3, 28.3, 34.1", \ + "27.4, 27.4, 27.4, 30.4, 36.2", \ + "31.5, 31.5, 31.5, 34.5, 40.4", \ + "39.5, 39.5, 39.5, 42.5, 48.5", \ + "55.2, 55.2, 55.2, 58.1, 64.0"); + } + cell_fall (inslew_load_5x5__35) { + values ("106.2, 106.2, 106.2, 110.2, 117.6", \ + "118.1, 118.1, 118.1, 122.1, 129.6", \ + "133.7, 133.7, 133.7, 137.8, 145.4", \ + "155.7, 155.7, 155.7, 159.8, 167.5", \ + "188.8, 188.8, 188.8, 193.0, 200.9"); + } + fall_transition (inslew_load_5x5__35) { + values ("29.9, 29.9, 29.9, 32.9, 38.7", \ + "32.6, 32.6, 32.6, 35.6, 41.5", \ + "37.4, 37.4, 37.4, 40.5, 46.3", \ + "46.4, 46.4, 46.4, 49.4, 55.4", \ + "63.2, 63.2, 63.2, 66.3, 72.3"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("114.5, 114.5, 114.5, 118.2, 125.0", \ + "127.8, 127.8, 127.8, 131.6, 138.5", \ + "146.1, 146.1, 146.1, 150.0, 157.1", \ + "173.4, 173.4, 173.4, 177.5, 184.9", \ + "218.5, 218.5, 218.5, 222.8, 230.6"); + } + rise_transition (inslew_load_5x5__35) { + values ("24.1, 24.1, 24.1, 27.1, 32.8", \ + "26.7, 26.7, 26.7, 29.8, 35.6", \ + "31.7, 31.7, 31.7, 34.8, 40.6", \ + "41.3, 41.3, 41.3, 44.3, 50.3", \ + "60.0, 60.0, 60.0, 62.9, 68.8"); + } + cell_fall (inslew_load_5x5__35) { + values ("95.8, 95.8, 95.8, 99.8, 107.2", \ + "102.9, 102.9, 102.9, 107.0, 114.4", \ + "109.6, 109.6, 109.6, 113.7, 121.2", \ + "113.7, 113.7, 113.7, 117.8, 125.5", \ + "111.7, 111.7, 111.7, 115.9, 123.7"); + } + fall_transition (inslew_load_5x5__35) { + values ("28.7, 28.7, 28.7, 31.7, 37.5", \ + "30.9, 30.9, 30.9, 33.9, 39.8", \ + "35.0, 35.0, 35.0, 38.0, 43.9", \ + "42.4, 42.4, 42.4, 45.5, 51.4", \ + "56.3, 56.3, 56.3, 59.4, 65.4"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("120.3, 120.3, 120.3, 124.0, 130.8", \ + "139.2, 139.2, 139.2, 143.1, 150.0", \ + "168.4, 168.4, 168.4, 172.4, 179.5", \ + "217.7, 217.7, 217.7, 221.9, 229.4", \ + "307.7, 307.7, 307.7, 312.1, 320.1"); + } + rise_transition (inslew_load_5x5__35) { + values ("24.8, 24.8, 24.8, 27.9, 33.6", \ + "28.1, 28.1, 28.1, 31.2, 37.0", \ + "34.3, 34.3, 34.3, 37.4, 43.3", \ + "46.3, 46.3, 46.3, 49.3, 55.3", \ + "69.7, 69.7, 69.7, 72.7, 78.6"); + } + cell_fall (inslew_load_5x5__35) { + values ("91.8, 91.8, 91.8, 95.8, 103.2", \ + "93.6, 93.6, 93.6, 97.6, 105.0", \ + "91.6, 91.6, 91.6, 95.6, 103.2", \ + "80.3, 80.3, 80.3, 84.4, 92.0", \ + "48.3, 48.3, 48.3, 52.5, 60.2"); + } + fall_transition (inslew_load_5x5__35) { + values ("28.8, 28.8, 28.8, 31.9, 37.7", \ + "30.7, 30.7, 30.7, 33.7, 39.5", \ + "34.2, 34.2, 34.2, 37.2, 43.1", \ + "40.7, 40.7, 40.7, 43.7, 49.6", \ + "52.8, 52.8, 52.8, 55.8, 61.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__35) { + values ("2162.3, 2162.3, 2162.3, 2272.0, 2491.3", \ + "2373.7, 2373.7, 2373.7, 2483.3, 2702.7", \ + "2802.9, 2802.9, 2802.9, 2912.6, 3131.9", \ + "3650.5, 3650.5, 3650.5, 3760.2, 3979.5", \ + "5347.9, 5347.9, 5347.9, 5457.5, 5676.9"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("2298.4, 2298.4, 2298.4, 2408.0, 2627.4", \ + "2612.4, 2612.4, 2612.4, 2722.1, 2941.4", \ + "3233.6, 3233.6, 3233.6, 3343.3, 3562.6", \ + "4463.0, 4463.0, 4463.0, 4572.7, 4792.1", \ + "6910.7, 6910.7, 6910.7, 7020.4, 7239.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__35) { + values ("2066.3, 2066.3, 2066.3, 2176.0, 2395.3", \ + "2217.8, 2217.8, 2217.8, 2327.5, 2546.9", \ + "2522.5, 2522.5, 2522.5, 2632.2, 2851.5", \ + "3131.8, 3131.8, 3131.8, 3241.5, 3460.8", \ + "4343.3, 4343.3, 4343.3, 4453.0, 4672.3"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("2230.6, 2230.6, 2230.6, 2340.3, 2559.6", \ + "2543.0, 2543.0, 2543.0, 2652.7, 2872.1", \ + "3155.7, 3155.7, 3155.7, 3265.4, 3484.7", \ + "4363.0, 4363.0, 4363.0, 4472.7, 4692.0", \ + "6755.8, 6755.8, 6755.8, 6865.4, 7084.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__35) { + values ("2037.0, 2037.0, 2037.0, 2146.7, 2366.0", \ + "2281.6, 2281.6, 2281.6, 2391.2, 2610.6", \ + "2771.9, 2771.9, 2771.9, 2881.6, 3100.9", \ + "3743.4, 3743.4, 3743.4, 3853.0, 4072.4", \ + "5677.1, 5677.1, 5677.1, 5786.8, 6006.2"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("2043.0, 2043.0, 2043.0, 2152.6, 2372.0", \ + "2260.6, 2260.6, 2260.6, 2370.2, 2589.6", \ + "2688.8, 2688.8, 2688.8, 2798.5, 3017.8", \ + "3534.3, 3534.3, 3534.3, 3643.9, 3863.3", \ + "5206.7, 5206.7, 5206.7, 5316.4, 5535.7"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__35) { + values ("1942.4, 1942.4, 1942.4, 2052.1, 2271.5", \ + "2126.4, 2126.4, 2126.4, 2236.1, 2455.4", \ + "2494.3, 2494.3, 2494.3, 2604.0, 2823.3", \ + "3220.4, 3220.4, 3220.4, 3330.1, 3549.4", \ + "4662.3, 4662.3, 4662.3, 4772.0, 4991.3"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("1987.7, 1987.7, 1987.7, 2097.4, 2316.7", \ + "2216.6, 2216.6, 2216.6, 2326.3, 2545.6", \ + "2661.3, 2661.3, 2661.3, 2770.9, 2990.3", \ + "3533.9, 3533.9, 3533.9, 3643.6, 3862.9", \ + "5257.4, 5257.4, 5257.4, 5367.0, 5586.4"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__35) { + values ("1770.4, 1770.4, 1770.4, 1880.1, 2099.4", \ + "1985.5, 1985.5, 1985.5, 2095.1, 2314.5", \ + "2402.1, 2402.1, 2402.1, 2511.8, 2731.1", \ + "3220.9, 3220.9, 3220.9, 3330.5, 3549.9", \ + "4844.4, 4844.4, 4844.4, 4954.1, 5173.4"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("1826.4, 1826.4, 1826.4, 1936.1, 2155.4", \ + "2004.2, 2004.2, 2004.2, 2113.9, 2333.2", \ + "2347.6, 2347.6, 2347.6, 2457.2, 2676.6", \ + "3019.5, 3019.5, 3019.5, 3129.2, 3348.6", \ + "4343.3, 4343.3, 4343.3, 4453.0, 4672.3"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__35) { + values ("1863.2, 1863.2, 1863.2, 1972.9, 2192.2", \ + "2143.5, 2143.5, 2143.5, 2253.1, 2472.5", \ + "2686.1, 2686.1, 2686.1, 2795.8, 3015.1", \ + "3758.0, 3758.0, 3758.0, 3867.7, 4087.0", \ + "5886.6, 5886.6, 5886.6, 5996.2, 6215.6"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("1875.0, 1875.0, 1875.0, 1984.7, 2204.0", \ + "2035.4, 2035.4, 2035.4, 2145.1, 2364.4", \ + "2352.5, 2352.5, 2352.5, 2462.2, 2681.5", \ + "2973.8, 2973.8, 2973.8, 3083.5, 3302.8", \ + "4198.3, 4198.3, 4198.3, 4307.9, 4527.3"); + } + } + } + } + + cell (noa2a2a2a24_x1) { + area : 0.0 ; + cell_leakage_power : 0.0097 ; + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5 & !(i6) & i7))" ; + value : 0.017 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & !(i5) & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))))) | (!(i0) & i1 & ((i2 & !(i3) & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))) | (!(i2) & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 0.016 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7)))) | (!(i1) & !(i2) & i3 & i4 & !(i5) & i6 & !(i7))))" ; + value : 0.012 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & (i4 ^ i5) & (i6 ^ i7)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))))) | (!(i1) & ((i2 & !(i3) & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))))))" ; + value : 0.013 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i1) & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7))))))" ; + value : 0.0086 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))))))" ; + value : 0.0089 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7))))" ; + value : 0.0092 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7))))))))" ; + value : 0.005 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))))" ; + value : 0.0053 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0014 ; + } + pin (i7) { + direction : input ; + capacitance : 28.89 ; + } + pin (i6) { + direction : input ; + capacitance : 27.31 ; + } + pin (i5) { + direction : input ; + capacitance : 28.60 ; + } + pin (i4) { + direction : input ; + capacitance : 28.60 ; + } + pin (i3) { + direction : input ; + capacitance : 28.60 ; + } + pin (i2) { + direction : input ; + capacitance : 28.95 ; + } + pin (i1) { + direction : input ; + capacitance : 22.00 ; + } + pin (i0) { + direction : input ; + capacitance : 21.92 ; + } + pin (nq) { + function : "((((((((((((((((((!(i6) & !(i4)) & !(i3)) & !(i1)) | (((!(i6) & !(i4)) & !(i3)) & !(i0))) | (((!(i6) & !(i4)) & !(i2)) & !(i1))) | (((!(i6) & !(i4)) & !(i2)) & !(i0))) | (((!(i6) & !(i5)) & !(i3)) & !(i1))) | (((!(i6) & !(i5)) & !(i3)) & !(i0))) | (((!(i6) & !(i5)) & !(i2)) & !(i1))) | (((!(i6) & !(i5)) & !(i2)) & !(i0))) | (((!(i7) & !(i4)) & !(i3)) & !(i1))) | (((!(i7) & !(i4)) & !(i3)) & !(i0))) | (((!(i7) & !(i4)) & !(i2)) & !(i1))) | (((!(i7) & !(i4)) & !(i2)) & !(i0))) | (((!(i7) & !(i5)) & !(i3)) & !(i1))) | (((!(i7) & !(i5)) & !(i3)) & !(i0))) | (((!(i7) & !(i5)) & !(i2)) & !(i1))) | (((!(i7) & !(i5)) & !(i2)) & !(i0)))" ; + direction : output ; + capacitance : 11.87 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("51.0, 51.0, 51.0, 64.6, 92.0", \ + "49.4, 49.4, 49.4, 63.3, 91.0", \ + "45.9, 45.9, 45.9, 60.3, 88.8", \ + "38.0, 38.0, 38.0, 53.1, 82.6", \ + "20.9, 20.9, 20.9, 36.6, 67.4"); + } + rise_transition (inslew_load_5x5__36) { + values ("108.2, 108.2, 108.2, 133.3, 183.7", \ + "130.1, 130.1, 130.1, 154.9, 205.0", \ + "175.1, 175.1, 175.1, 199.4, 248.5", \ + "266.6, 266.6, 266.6, 290.6, 338.8", \ + "447.0, 447.0, 447.0, 474.6, 522.4"); + } + cell_fall (inslew_load_5x5__36) { + values ("42.9, 42.9, 42.9, 53.0, 72.9", \ + "52.7, 52.7, 52.7, 63.6, 84.6", \ + "69.9, 69.9, 69.9, 81.6, 104.1", \ + "102.3, 102.3, 102.3, 114.6, 138.6", \ + "165.5, 165.5, 165.5, 178.3, 205.5"); + } + fall_transition (inslew_load_5x5__36) { + values ("62.7, 62.7, 62.7, 76.1, 103.2", \ + "88.8, 88.8, 88.8, 102.1, 128.8", \ + "140.2, 140.2, 140.2, 153.5, 180.1", \ + "242.5, 242.5, 242.5, 255.9, 282.7", \ + "446.7, 446.7, 446.7, 460.2, 489.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("45.8, 45.8, 45.8, 59.5, 86.9", \ + "40.6, 40.6, 40.6, 54.6, 82.4", \ + "29.3, 29.3, 29.3, 44.1, 73.0", \ + "4.9, 4.9, 4.9, 20.7, 51.3", \ + "-46.5, -46.5, -46.5, -29.6, 3.0"); + } + rise_transition (inslew_load_5x5__36) { + values ("99.0, 99.0, 99.0, 124.1, 174.4", \ + "114.8, 114.8, 114.8, 139.5, 189.4", \ + "147.9, 147.9, 147.9, 172.1, 220.9", \ + "213.7, 213.7, 213.7, 239.6, 287.6", \ + "346.4, 346.4, 346.4, 370.8, 419.4"); + } + cell_fall (inslew_load_5x5__36) { + values ("46.6, 46.6, 46.6, 57.6, 78.4", \ + "61.7, 61.7, 61.7, 73.8, 96.7", \ + "87.7, 87.7, 87.7, 101.0, 126.3", \ + "136.4, 136.4, 136.4, 150.6, 178.1", \ + "231.8, 231.8, 231.8, 246.7, 277.5"); + } + fall_transition (inslew_load_5x5__36) { + values ("59.9, 59.9, 59.9, 73.4, 100.7", \ + "88.5, 88.5, 88.5, 102.2, 129.3", \ + "143.5, 143.5, 143.5, 157.5, 185.0", \ + "252.2, 252.2, 252.2, 266.3, 294.4", \ + "468.4, 468.4, 468.4, 482.8, 512.9"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("48.7, 48.7, 48.7, 62.6, 90.2", \ + "53.4, 53.4, 53.4, 67.8, 96.2", \ + "61.2, 61.2, 61.2, 76.6, 106.2", \ + "75.0, 75.0, 75.0, 91.2, 122.6", \ + "100.8, 100.8, 100.8, 117.7, 150.8"); + } + rise_transition (inslew_load_5x5__36) { + values ("96.7, 96.7, 96.7, 121.9, 172.7", \ + "123.5, 123.5, 123.5, 148.3, 198.2", \ + "176.8, 176.8, 176.8, 202.4, 251.4", \ + "284.0, 284.0, 284.0, 308.7, 357.8", \ + "497.9, 497.9, 497.9, 522.7, 572.2"); + } + cell_fall (inslew_load_5x5__36) { + values ("37.6, 37.6, 37.6, 48.0, 68.0", \ + "41.3, 41.3, 41.3, 52.6, 74.2", \ + "45.5, 45.5, 45.5, 58.0, 81.7", \ + "50.6, 50.6, 50.6, 64.2, 90.4", \ + "58.7, 58.7, 58.7, 73.1, 101.1"); + } + fall_transition (inslew_load_5x5__36) { + values ("56.1, 56.1, 56.1, 69.5, 96.4", \ + "75.5, 75.5, 75.5, 88.8, 115.6", \ + "113.5, 113.5, 113.5, 127.1, 153.8", \ + "188.9, 188.9, 188.9, 202.7, 229.9", \ + "339.1, 339.1, 339.1, 353.0, 380.6"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("43.6, 43.6, 43.6, 57.5, 85.2", \ + "44.1, 44.1, 44.1, 58.8, 87.5", \ + "43.1, 43.1, 43.1, 59.0, 89.4", \ + "38.1, 38.1, 38.1, 55.4, 88.4", \ + "25.3, 25.3, 25.3, 43.8, 79.4"); + } + rise_transition (inslew_load_5x5__36) { + values ("87.7, 87.7, 87.7, 112.8, 163.6", \ + "108.2, 108.2, 108.2, 132.9, 182.6", \ + "148.6, 148.6, 148.6, 173.3, 223.4", \ + "229.8, 229.8, 229.8, 254.7, 304.2", \ + "391.5, 391.5, 391.5, 416.7, 466.7"); + } + cell_fall (inslew_load_5x5__36) { + values ("41.9, 41.9, 41.9, 53.1, 74.2", \ + "50.9, 50.9, 50.9, 63.6, 87.2", \ + "63.9, 63.9, 63.9, 78.3, 105.1", \ + "86.0, 86.0, 86.0, 101.8, 131.7", \ + "127.4, 127.4, 127.4, 144.1, 176.5"); + } + fall_transition (inslew_load_5x5__36) { + values ("54.3, 54.3, 54.3, 67.9, 95.1", \ + "76.8, 76.8, 76.8, 90.7, 117.8", \ + "119.8, 119.8, 119.8, 134.1, 162.0", \ + "204.3, 204.3, 204.3, 218.9, 247.7", \ + "372.0, 372.0, 372.0, 386.9, 416.4"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("34.5, 34.5, 34.5, 49.2, 77.6", \ + "39.3, 39.3, 39.3, 54.3, 84.2", \ + "46.0, 46.0, 46.0, 63.4, 95.7", \ + "56.2, 56.2, 56.2, 75.2, 111.0", \ + "74.2, 74.2, 74.2, 94.4, 133.1"); + } + rise_transition (inslew_load_5x5__36) { + values ("69.0, 69.0, 69.0, 94.4, 145.5", \ + "92.6, 92.6, 92.6, 116.3, 166.9", \ + "139.2, 139.2, 139.2, 164.5, 214.3", \ + "231.1, 231.1, 231.1, 256.8, 307.8", \ + "413.9, 413.9, 413.9, 440.0, 491.8"); + } + cell_fall (inslew_load_5x5__36) { + values ("28.6, 28.6, 28.6, 40.9, 63.0", \ + "32.0, 32.0, 32.0, 46.2, 71.6", \ + "34.8, 34.8, 34.8, 51.1, 80.5", \ + "37.5, 37.5, 37.5, 55.4, 88.6", \ + "40.8, 40.8, 40.8, 59.8, 96.0"); + } + fall_transition (inslew_load_5x5__36) { + values ("39.7, 39.7, 39.7, 53.4, 80.5", \ + "58.1, 58.1, 58.1, 72.3, 99.8", \ + "93.1, 93.1, 93.1, 107.8, 136.4", \ + "161.8, 161.8, 161.8, 177.0, 206.8", \ + "298.3, 298.3, 298.3, 313.9, 344.6"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("39.6, 39.6, 39.6, 54.2, 82.3", \ + "48.2, 48.2, 48.2, 63.2, 92.8", \ + "64.7, 64.7, 64.7, 81.2, 112.4", \ + "94.4, 94.4, 94.4, 112.1, 145.9", \ + "152.2, 152.2, 152.2, 170.6, 206.4"); + } + rise_transition (inslew_load_5x5__36) { + values ("77.6, 77.6, 77.6, 103.0, 154.2", \ + "106.5, 106.5, 106.5, 131.4, 181.7", \ + "166.5, 166.5, 166.5, 191.6, 241.3", \ + "284.1, 284.1, 284.1, 309.4, 359.9", \ + "518.4, 518.4, 518.4, 544.0, 595.0"); + } + cell_fall (inslew_load_5x5__36) { + values ("25.3, 25.3, 25.3, 36.3, 57.0", \ + "24.2, 24.2, 24.2, 36.6, 59.3", \ + "19.1, 19.1, 19.1, 33.0, 58.7", \ + "6.1, 6.1, 6.1, 21.5, 50.2", \ + "-21.7, -21.7, -21.7, -5.4, 25.9"); + } + fall_transition (inslew_load_5x5__36) { + values ("41.4, 41.4, 41.4, 54.7, 81.5", \ + "56.9, 56.9, 56.9, 70.4, 97.1", \ + "87.1, 87.1, 87.1, 100.9, 128.0", \ + "146.6, 146.6, 146.6, 160.8, 188.7", \ + "265.1, 265.1, 265.1, 279.6, 308.1"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("21.1, 21.1, 21.1, 36.0, 64.9", \ + "27.7, 27.7, 27.7, 45.0, 74.5", \ + "39.4, 39.4, 39.4, 58.9, 94.1", \ + "61.4, 61.4, 61.4, 82.5, 121.8", \ + "104.3, 104.3, 104.3, 126.4, 168.7"); + } + rise_transition (inslew_load_5x5__36) { + values ("46.9, 46.9, 46.9, 71.1, 121.5", \ + "72.3, 72.3, 72.3, 97.7, 145.1", \ + "122.2, 122.2, 122.2, 148.5, 200.0", \ + "221.4, 221.4, 221.4, 248.3, 301.2", \ + "419.3, 419.3, 419.3, 446.6, 500.6"); + } + cell_fall (inslew_load_5x5__36) { + values ("18.2, 18.2, 18.2, 31.9, 55.1", \ + "17.2, 17.2, 17.2, 33.3, 60.4", \ + "12.5, 12.5, 12.5, 30.8, 62.7", \ + "1.0, 1.0, 1.0, 21.0, 57.5", \ + "-23.3, -23.3, -23.3, -2.0, 38.0"); + } + fall_transition (inslew_load_5x5__36) { + values ("29.3, 29.3, 29.3, 43.3, 70.5", \ + "44.7, 44.7, 44.7, 59.4, 87.4", \ + "74.2, 74.2, 74.2, 89.6, 119.0", \ + "132.1, 132.1, 132.1, 148.2, 179.0", \ + "247.4, 247.4, 247.4, 263.8, 295.9"); + } + } + timing (maxd_nq_i7_negative_unate) { + related_pin : "i7" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("26.2, 26.2, 26.2, 40.7, 69.6", \ + "37.5, 37.5, 37.5, 53.9, 82.4", \ + "59.2, 59.2, 59.2, 77.3, 110.9", \ + "101.3, 101.3, 101.3, 120.6, 157.3", \ + "184.6, 184.6, 184.6, 204.7, 243.5"); + } + rise_transition (inslew_load_5x5__36) { + values ("54.8, 54.8, 54.8, 78.8, 130.0", \ + "86.6, 86.6, 86.6, 111.7, 159.0", \ + "149.0, 149.0, 149.0, 174.9, 225.9", \ + "273.4, 273.4, 273.4, 299.8, 352.0", \ + "521.9, 521.9, 521.9, 548.6, 601.5"); + } + cell_fall (inslew_load_5x5__36) { + values ("16.2, 16.2, 16.2, 28.0, 49.3", \ + "11.4, 11.4, 11.4, 25.0, 49.0", \ + "-0.4, -0.4, -0.4, 15.0, 42.6", \ + "-26.4, -26.4, -26.4, -9.3, 22.1", \ + "-80.1, -80.1, -80.1, -61.7, -27.1"); + } + fall_transition (inslew_load_5x5__36) { + values ("31.2, 31.2, 31.2, 44.7, 71.4", \ + "44.1, 44.1, 44.1, 57.9, 84.7", \ + "69.0, 69.0, 69.0, 83.3, 110.9", \ + "118.0, 118.0, 118.0, 132.8, 161.4", \ + "215.6, 215.6, 215.6, 230.7, 260.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__36) { + values ("622.6, 622.6, 622.6, 771.0, 1067.7", \ + "740.1, 740.1, 740.1, 888.4, 1185.1", \ + "975.0, 975.0, 975.0, 1123.3, 1420.0", \ + "1444.8, 1444.8, 1444.8, 1593.2, 1889.9", \ + "2384.5, 2384.5, 2384.5, 2532.8, 2829.5"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("643.5, 643.5, 643.5, 791.8, 1088.5", \ + "860.8, 860.8, 860.8, 1009.2, 1305.9", \ + "1295.5, 1295.5, 1295.5, 1443.9, 1740.6", \ + "2164.9, 2164.9, 2164.9, 2313.3, 2610.0", \ + "3903.7, 3903.7, 3903.7, 4052.1, 4348.8"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__36) { + values ("562.8, 562.8, 562.8, 711.1, 1007.8", \ + "642.9, 642.9, 642.9, 791.2, 1087.9", \ + "803.1, 803.1, 803.1, 951.5, 1248.2", \ + "1123.6, 1123.6, 1123.6, 1271.9, 1568.6", \ + "1764.5, 1764.5, 1764.5, 1912.9, 2209.6"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("585.8, 585.8, 585.8, 734.1, 1030.8", \ + "791.5, 791.5, 791.5, 939.9, 1236.6", \ + "1203.1, 1203.1, 1203.1, 1351.4, 1648.1", \ + "2026.1, 2026.1, 2026.1, 2174.4, 2471.1", \ + "3672.1, 3672.1, 3672.1, 3820.5, 4117.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__36) { + values ("555.2, 555.2, 555.2, 703.5, 1000.2", \ + "686.6, 686.6, 686.6, 835.0, 1131.7", \ + "949.6, 949.6, 949.6, 1097.9, 1394.6", \ + "1475.4, 1475.4, 1475.4, 1623.8, 1920.5", \ + "2527.2, 2527.2, 2527.2, 2675.6, 2972.2"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("558.8, 558.8, 558.8, 707.1, 1003.8", \ + "703.6, 703.6, 703.6, 852.0, 1148.7", \ + "993.4, 993.4, 993.4, 1141.7, 1438.4", \ + "1572.9, 1572.9, 1572.9, 1721.2, 2017.9", \ + "2731.9, 2731.9, 2731.9, 2880.2, 3176.9"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__36) { + values ("494.1, 494.1, 494.1, 642.4, 939.1", \ + "587.0, 587.0, 587.0, 735.4, 1032.1", \ + "772.9, 772.9, 772.9, 921.2, 1217.9", \ + "1144.6, 1144.6, 1144.6, 1292.9, 1589.6", \ + "1888.0, 1888.0, 1888.0, 2036.4, 2333.1"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("512.8, 512.8, 512.8, 661.2, 957.9", \ + "657.9, 657.9, 657.9, 806.2, 1102.9", \ + "948.0, 948.0, 948.0, 1096.3, 1393.0", \ + "1528.1, 1528.1, 1528.1, 1676.5, 1973.2", \ + "2688.4, 2688.4, 2688.4, 2836.8, 3133.5"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__36) { + values ("383.7, 383.7, 383.7, 532.0, 828.7", \ + "483.7, 483.7, 483.7, 632.1, 928.8", \ + "683.8, 683.8, 683.8, 832.2, 1128.9", \ + "1084.0, 1084.0, 1084.0, 1232.4, 1529.1", \ + "1884.4, 1884.4, 1884.4, 2032.7, 2329.4"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("347.0, 347.0, 347.0, 495.3, 792.0", \ + "455.2, 455.2, 455.2, 603.6, 900.3", \ + "671.7, 671.7, 671.7, 820.1, 1116.8", \ + "1104.7, 1104.7, 1104.7, 1253.1, 1549.8", \ + "1970.7, 1970.7, 1970.7, 2119.1, 2415.8"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__36) { + values ("442.7, 442.7, 442.7, 591.1, 887.8", \ + "579.3, 579.3, 579.3, 727.6, 1024.3", \ + "852.4, 852.4, 852.4, 1000.8, 1297.5", \ + "1398.7, 1398.7, 1398.7, 1547.0, 1843.7", \ + "2491.2, 2491.2, 2491.2, 2639.6, 2936.3"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("389.2, 389.2, 389.2, 537.6, 834.3", \ + "493.7, 493.7, 493.7, 642.0, 938.7", \ + "702.6, 702.6, 702.6, 850.9, 1147.6", \ + "1120.3, 1120.3, 1120.3, 1268.7, 1565.4", \ + "1955.9, 1955.9, 1955.9, 2104.2, 2400.9"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__36) { + values ("251.5, 251.5, 251.5, 399.8, 696.5", \ + "354.7, 354.7, 354.7, 503.0, 799.7", \ + "561.0, 561.0, 561.0, 709.3, 1006.0", \ + "973.6, 973.6, 973.6, 1121.9, 1418.6", \ + "1798.8, 1798.8, 1798.8, 1947.1, 2243.8"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("232.9, 232.9, 232.9, 381.2, 677.9", \ + "317.4, 317.4, 317.4, 465.8, 762.5", \ + "486.5, 486.5, 486.5, 634.8, 931.5", \ + "824.7, 824.7, 824.7, 973.0, 1269.7", \ + "1501.0, 1501.0, 1501.0, 1649.3, 1946.0"); + } + } + internal_power (energy_neg_nq_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__36) { + values ("308.4, 308.4, 308.4, 456.8, 753.4", \ + "445.9, 445.9, 445.9, 594.3, 891.0", \ + "721.0, 721.0, 721.0, 869.4, 1166.1", \ + "1271.2, 1271.2, 1271.2, 1419.5, 1716.2", \ + "2371.5, 2371.5, 2371.5, 2519.8, 2816.5"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("273.5, 273.5, 273.5, 421.9, 718.6", \ + "352.6, 352.6, 352.6, 501.0, 797.6", \ + "510.8, 510.8, 510.8, 659.1, 955.8", \ + "827.1, 827.1, 827.1, 975.5, 1272.2", \ + "1459.9, 1459.9, 1459.9, 1608.2, 1904.9"); + } + } + } + } + + cell (noa2a2a2a24_x4) { + area : 0.0 ; + cell_leakage_power : 0.022 ; + leakage_power () { + when : "(i7 & !(i6) & i5 & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 0.03 ; + } + leakage_power () { + when : "(!(i7) & i6 & !(i5) & i4 & i3 & !(i2) & i1 & !(i0))" ; + value : 0.028 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))) | (!(i2) & i3 & (i4 ^ i5) & (i6 ^ i7)))) | (!(i0) & i1 & ((i2 & !(i3) & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))))" ; + value : 0.029 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7))) | (!(i0) & !(i1) & i2 & !(i3) & !(i4) & i5 & !(i6) & i7))" ; + value : 0.026 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))))))) | (!(i0) & ((i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & (i4 ^ i5) & (i6 ^ i7)))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))) | (!(i2) & i3 & (i4 ^ i5) & (i6 ^ i7)))))))" ; + value : 0.025 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & (i4 ^ i5) & (i6 ^ i7)))))))))" ; + value : 0.021 ; + } + leakage_power () { + when : "((i0 & i1) | (i2 & i3) | (i4 & i5) | (i6 & i7))" ; + value : 0.0045 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))))))" ; + value : 0.017 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.013 ; + } + pin (i7) { + direction : input ; + capacitance : 22.05 ; + } + pin (i6) { + direction : input ; + capacitance : 21.77 ; + } + pin (i5) { + direction : input ; + capacitance : 21.77 ; + } + pin (i4) { + direction : input ; + capacitance : 21.77 ; + } + pin (i3) { + direction : input ; + capacitance : 22.13 ; + } + pin (i2) { + direction : input ; + capacitance : 21.77 ; + } + pin (i1) { + direction : input ; + capacitance : 22.48 ; + } + pin (i0) { + direction : input ; + capacitance : 21.77 ; + } + pin (nq) { + function : "((!(i7) & ((!(i5) & ((!(i3) & (!(i1) | !(i0))) | (!((i1 & i0)) & !(i2)))) | (!(i3) & !((i1 & i0)) & !(i4)) | (!((i1 & i0)) & !(i2) & !(i4)))) | (!(i5) & ((!(i3) & !((i1 & i0)) & !(i6)) | (!((i1 & i0)) & !(i2) & !(i6)))) | (!(i3) & !((i1 & i0)) & !(i4) & !(i6)) | (!((i1 & i0)) & !(i2) & !(i4) & !(i6)))" ; + direction : output ; + capacitance : 9.46 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("111.5, 111.5, 111.5, 115.5, 122.5", \ + "110.3, 110.3, 110.3, 114.3, 121.4", \ + "106.9, 106.9, 106.9, 110.9, 118.2", \ + "97.2, 97.2, 97.2, 101.3, 109.0", \ + "74.2, 74.2, 74.2, 78.6, 86.6"); + } + rise_transition (inslew_load_5x5__37) { + values ("21.5, 21.5, 21.5, 24.8, 30.9", \ + "23.3, 23.3, 23.3, 26.6, 32.7", \ + "26.8, 26.8, 26.8, 30.0, 36.2", \ + "33.8, 33.8, 33.8, 37.1, 43.4", \ + "48.1, 48.1, 48.1, 51.3, 57.6"); + } + cell_fall (inslew_load_5x5__37) { + values ("125.4, 125.4, 125.4, 129.7, 137.8", \ + "141.2, 141.2, 141.2, 145.6, 153.7", \ + "168.4, 168.4, 168.4, 172.8, 181.0", \ + "216.4, 216.4, 216.4, 220.9, 229.4", \ + "308.7, 308.7, 308.7, 313.2, 322.0"); + } + fall_transition (inslew_load_5x5__37) { + values ("34.8, 34.8, 34.8, 38.0, 44.3", \ + "39.1, 39.1, 39.1, 42.4, 48.7", \ + "47.6, 47.6, 47.6, 50.9, 57.3", \ + "64.2, 64.2, 64.2, 67.5, 74.0", \ + "97.3, 97.3, 97.3, 100.6, 107.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("106.6, 106.6, 106.6, 110.5, 117.5", \ + "101.8, 101.8, 101.8, 105.8, 112.8", \ + "91.4, 91.4, 91.4, 95.4, 102.5", \ + "67.3, 67.3, 67.3, 71.4, 78.8", \ + "14.1, 14.1, 14.1, 18.4, 26.2"); + } + rise_transition (inslew_load_5x5__37) { + values ("20.8, 20.8, 20.8, 24.0, 30.1", \ + "22.0, 22.0, 22.0, 25.3, 31.4", \ + "24.6, 24.6, 24.6, 27.9, 34.0", \ + "29.9, 29.9, 29.9, 33.2, 39.4", \ + "40.2, 40.2, 40.2, 43.4, 49.8"); + } + cell_fall (inslew_load_5x5__37) { + values ("129.8, 129.8, 129.8, 134.1, 142.1", \ + "152.3, 152.3, 152.3, 156.6, 164.7", \ + "189.4, 189.4, 189.4, 193.8, 202.0", \ + "255.2, 255.2, 255.2, 259.7, 268.2", \ + "379.3, 379.3, 379.3, 383.8, 392.6"); + } + fall_transition (inslew_load_5x5__37) { + values ("34.4, 34.4, 34.4, 37.6, 43.9", \ + "39.2, 39.2, 39.2, 42.5, 48.8", \ + "48.4, 48.4, 48.4, 51.7, 58.1", \ + "66.1, 66.1, 66.1, 69.4, 75.8", \ + "100.8, 100.8, 100.8, 104.1, 110.6"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("109.9, 109.9, 109.9, 113.9, 120.8", \ + "115.4, 115.4, 115.4, 119.3, 126.4", \ + "123.2, 123.2, 123.2, 127.2, 134.4", \ + "134.7, 134.7, 134.7, 138.9, 146.6", \ + "152.5, 152.5, 152.5, 157.0, 165.1"); + } + rise_transition (inslew_load_5x5__37) { + values ("20.7, 20.7, 20.7, 23.9, 29.9", \ + "22.7, 22.7, 22.7, 26.0, 32.1", \ + "26.9, 26.9, 26.9, 30.2, 36.4", \ + "35.2, 35.2, 35.2, 38.4, 44.7", \ + "51.6, 51.6, 51.6, 54.7, 61.1"); + } + cell_fall (inslew_load_5x5__37) { + values ("118.9, 118.9, 118.9, 123.3, 131.3", \ + "127.9, 127.9, 127.9, 132.2, 140.3", \ + "140.7, 140.7, 140.7, 145.1, 153.2", \ + "158.7, 158.7, 158.7, 163.2, 171.5", \ + "187.3, 187.3, 187.3, 191.8, 200.5"); + } + fall_transition (inslew_load_5x5__37) { + values ("33.6, 33.6, 33.6, 36.9, 43.2", \ + "36.9, 36.9, 36.9, 40.2, 46.5", \ + "43.3, 43.3, 43.3, 46.6, 52.9", \ + "55.7, 55.7, 55.7, 59.0, 65.4", \ + "79.8, 79.8, 79.8, 83.1, 89.6"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("105.1, 105.1, 105.1, 109.0, 115.9", \ + "106.7, 106.7, 106.7, 110.7, 117.7", \ + "107.2, 107.2, 107.2, 111.2, 118.4", \ + "103.0, 103.0, 103.0, 107.1, 114.6", \ + "87.7, 87.7, 87.7, 92.1, 100.0"); + } + rise_transition (inslew_load_5x5__37) { + values ("19.9, 19.9, 19.9, 23.1, 29.2", \ + "21.5, 21.5, 21.5, 24.8, 30.9", \ + "24.8, 24.8, 24.8, 28.1, 34.3", \ + "31.2, 31.2, 31.2, 34.4, 40.7", \ + "43.8, 43.8, 43.8, 47.0, 53.4"); + } + cell_fall (inslew_load_5x5__37) { + values ("124.0, 124.0, 124.0, 128.4, 136.4", \ + "139.7, 139.7, 139.7, 144.0, 152.1", \ + "162.7, 162.7, 162.7, 167.1, 175.3", \ + "198.8, 198.8, 198.8, 203.3, 211.7", \ + "261.9, 261.9, 261.9, 266.4, 275.1"); + } + fall_transition (inslew_load_5x5__37) { + values ("33.4, 33.4, 33.4, 36.6, 42.9", \ + "37.2, 37.2, 37.2, 40.5, 46.8", \ + "44.5, 44.5, 44.5, 47.8, 54.1", \ + "58.3, 58.3, 58.3, 61.6, 68.0", \ + "85.2, 85.2, 85.2, 88.5, 95.0"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("97.5, 97.5, 97.5, 101.3, 108.1", \ + "103.2, 103.2, 103.2, 107.1, 114.1", \ + "113.1, 113.1, 113.1, 117.1, 124.2", \ + "124.0, 124.0, 124.0, 128.1, 135.6", \ + "138.3, 138.3, 138.3, 142.7, 150.7"); + } + rise_transition (inslew_load_5x5__37) { + values ("18.5, 18.5, 18.5, 21.7, 27.7", \ + "20.3, 20.3, 20.3, 23.5, 29.6", \ + "24.1, 24.1, 24.1, 27.4, 33.5", \ + "31.4, 31.4, 31.4, 34.6, 40.9", \ + "45.5, 45.5, 45.5, 48.7, 55.1"); + } + cell_fall (inslew_load_5x5__37) { + values ("109.7, 109.7, 109.7, 114.0, 121.9", \ + "120.3, 120.3, 120.3, 124.6, 132.6", \ + "132.8, 132.8, 132.8, 137.2, 145.3", \ + "148.3, 148.3, 148.3, 152.8, 161.0", \ + "169.9, 169.9, 169.9, 174.4, 183.0"); + } + fall_transition (inslew_load_5x5__37) { + values ("31.0, 31.0, 31.0, 34.2, 40.5", \ + "34.3, 34.3, 34.3, 37.5, 43.8", \ + "40.3, 40.3, 40.3, 43.6, 49.9", \ + "51.7, 51.7, 51.7, 55.0, 61.4", \ + "73.6, 73.6, 73.6, 76.9, 83.4"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("102.4, 102.4, 102.4, 106.3, 113.1", \ + "112.0, 112.0, 112.0, 116.0, 123.0", \ + "129.7, 129.7, 129.7, 133.7, 140.9", \ + "157.9, 157.9, 157.9, 162.1, 169.8", \ + "207.8, 207.8, 207.8, 212.3, 220.4"); + } + rise_transition (inslew_load_5x5__37) { + values ("19.2, 19.2, 19.2, 22.4, 28.4", \ + "21.5, 21.5, 21.5, 24.7, 30.8", \ + "26.2, 26.2, 26.2, 29.5, 35.7", \ + "35.4, 35.4, 35.4, 38.6, 45.0", \ + "53.5, 53.5, 53.5, 56.6, 63.0"); + } + cell_fall (inslew_load_5x5__37) { + values ("104.9, 104.9, 104.9, 109.3, 117.2", \ + "109.1, 109.1, 109.1, 113.4, 121.5", \ + "112.0, 112.0, 112.0, 116.3, 124.5", \ + "110.0, 110.0, 110.0, 114.5, 122.7", \ + "97.9, 97.9, 97.9, 102.4, 111.0"); + } + fall_transition (inslew_load_5x5__37) { + values ("31.2, 31.2, 31.2, 34.4, 40.7", \ + "33.9, 33.9, 33.9, 37.1, 43.4", \ + "39.0, 39.0, 39.0, 42.3, 48.6", \ + "48.8, 48.8, 48.8, 52.1, 58.5", \ + "67.8, 67.8, 67.8, 71.1, 77.6"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("84.9, 84.9, 84.9, 88.8, 95.3", \ + "95.5, 95.5, 95.5, 99.3, 106.2", \ + "111.1, 111.1, 111.1, 115.0, 122.1", \ + "133.8, 133.8, 133.8, 137.9, 145.4", \ + "172.1, 172.1, 172.1, 176.5, 184.5"); + } + rise_transition (inslew_load_5x5__37) { + values ("16.7, 16.7, 16.7, 19.8, 25.8", \ + "18.9, 18.9, 18.9, 22.1, 28.1", \ + "23.0, 23.0, 23.0, 26.2, 32.3", \ + "30.8, 30.8, 30.8, 34.1, 40.4", \ + "46.1, 46.1, 46.1, 49.3, 55.7"); + } + cell_fall (inslew_load_5x5__37) { + values ("99.3, 99.3, 99.3, 103.6, 111.5", \ + "106.0, 106.0, 106.0, 110.3, 118.2", \ + "111.0, 111.0, 111.0, 115.3, 123.4", \ + "111.5, 111.5, 111.5, 115.9, 124.1", \ + "103.2, 103.2, 103.2, 107.7, 116.2"); + } + fall_transition (inslew_load_5x5__37) { + values ("29.4, 29.4, 29.4, 32.6, 38.8", \ + "32.2, 32.2, 32.2, 35.5, 41.7", \ + "37.4, 37.4, 37.4, 40.7, 47.0", \ + "47.1, 47.1, 47.1, 50.4, 56.8", \ + "65.7, 65.7, 65.7, 69.1, 75.5"); + } + } + timing (maxd_nq_i7_negative_unate) { + related_pin : "i7" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("89.7, 89.7, 89.7, 93.6, 100.3", \ + "103.8, 103.8, 103.8, 107.7, 114.6", \ + "127.9, 127.9, 127.9, 131.9, 139.0", \ + "168.3, 168.3, 168.3, 172.5, 180.2", \ + "242.6, 242.6, 242.6, 247.1, 255.2"); + } + rise_transition (inslew_load_5x5__37) { + values ("17.4, 17.4, 17.4, 20.5, 26.5", \ + "20.0, 20.0, 20.0, 23.2, 29.2", \ + "25.0, 25.0, 25.0, 28.3, 34.4", \ + "34.7, 34.7, 34.7, 38.0, 44.3", \ + "53.8, 53.8, 53.8, 56.9, 63.3"); + } + cell_fall (inslew_load_5x5__37) { + values ("94.9, 94.9, 94.9, 99.2, 107.1", \ + "96.0, 96.0, 96.0, 100.4, 108.3", \ + "92.2, 92.2, 92.2, 96.5, 104.6", \ + "76.9, 76.9, 76.9, 81.3, 89.5", \ + "37.4, 37.4, 37.4, 41.8, 50.2"); + } + fall_transition (inslew_load_5x5__37) { + values ("29.5, 29.5, 29.5, 32.8, 39.0", \ + "31.8, 31.8, 31.8, 35.1, 41.4", \ + "36.2, 36.2, 36.2, 39.5, 45.8", \ + "44.4, 44.4, 44.4, 47.7, 54.1", \ + "60.2, 60.2, 60.2, 63.5, 70.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__37) { + values ("2258.5, 2258.5, 2258.5, 2376.8, 2613.3", \ + "2470.5, 2470.5, 2470.5, 2588.8, 2825.3", \ + "2897.6, 2897.6, 2897.6, 3015.9, 3252.5", \ + "3759.2, 3759.2, 3759.2, 3877.5, 4114.0", \ + "5487.3, 5487.3, 5487.3, 5605.6, 5842.2"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("2484.7, 2484.7, 2484.7, 2603.0, 2839.6", \ + "2864.5, 2864.5, 2864.5, 2982.8, 3219.4", \ + "3620.6, 3620.6, 3620.6, 3738.9, 3975.5", \ + "5122.7, 5122.7, 5122.7, 5241.0, 5477.6", \ + "8130.1, 8130.1, 8130.1, 8248.4, 8485.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__37) { + values ("2158.2, 2158.2, 2158.2, 2276.5, 2513.1", \ + "2306.0, 2306.0, 2306.0, 2424.3, 2660.9", \ + "2607.9, 2607.9, 2607.9, 2726.2, 2962.8", \ + "3221.3, 3221.3, 3221.3, 3339.6, 3576.1", \ + "4433.9, 4433.9, 4433.9, 4552.2, 4788.7"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("2409.8, 2409.8, 2409.8, 2528.1, 2764.7", \ + "2797.1, 2797.1, 2797.1, 2915.3, 3151.9", \ + "3555.2, 3555.2, 3555.2, 3673.4, 3910.0", \ + "5054.9, 5054.9, 5054.9, 5173.2, 5409.8", \ + "8037.3, 8037.3, 8037.3, 8155.5, 8392.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__37) { + values ("2146.2, 2146.2, 2146.2, 2264.5, 2501.1", \ + "2389.2, 2389.2, 2389.2, 2507.5, 2744.1", \ + "2879.6, 2879.6, 2879.6, 2997.9, 3234.4", \ + "3853.4, 3853.4, 3853.4, 3971.7, 4208.3", \ + "5802.5, 5802.5, 5802.5, 5920.7, 6157.3"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("2356.0, 2356.0, 2356.0, 2474.3, 2710.9", \ + "2621.8, 2621.8, 2621.8, 2740.1, 2976.7", \ + "3149.1, 3149.1, 3149.1, 3267.4, 3504.0", \ + "4194.4, 4194.4, 4194.4, 4312.6, 4549.2", \ + "6269.8, 6269.8, 6269.8, 6388.1, 6624.7"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__37) { + values ("2047.6, 2047.6, 2047.6, 2165.9, 2402.5", \ + "2227.4, 2227.4, 2227.4, 2345.7, 2582.3", \ + "2592.9, 2592.9, 2592.9, 2711.2, 2947.8", \ + "3314.6, 3314.6, 3314.6, 3432.9, 3669.5", \ + "4757.2, 4757.2, 4757.2, 4875.5, 5112.1"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("2298.0, 2298.0, 2298.0, 2416.3, 2652.9", \ + "2583.9, 2583.9, 2583.9, 2702.2, 2938.8", \ + "3142.7, 3142.7, 3142.7, 3261.0, 3497.6", \ + "4240.1, 4240.1, 4240.1, 4358.3, 4594.9", \ + "6415.7, 6415.7, 6415.7, 6534.0, 6770.6"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__37) { + values ("1866.5, 1866.5, 1866.5, 1984.8, 2221.4", \ + "2062.0, 2062.0, 2062.0, 2180.3, 2416.9", \ + "2465.7, 2465.7, 2465.7, 2584.0, 2820.6", \ + "3261.2, 3261.2, 3261.2, 3379.5, 3616.0", \ + "4838.7, 4838.7, 4838.7, 4957.0, 5193.6"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("2050.9, 2050.9, 2050.9, 2169.2, 2405.8", \ + "2277.9, 2277.9, 2277.9, 2396.2, 2632.8", \ + "2715.5, 2715.5, 2715.5, 2833.8, 3070.3", \ + "3570.1, 3570.1, 3570.1, 3688.4, 3925.0", \ + "5259.1, 5259.1, 5259.1, 5377.4, 5613.9"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__37) { + values ("1963.7, 1963.7, 1963.7, 2081.9, 2318.5", \ + "2221.9, 2221.9, 2221.9, 2340.2, 2576.7", \ + "2750.0, 2750.0, 2750.0, 2868.3, 3104.9", \ + "3797.8, 3797.8, 3797.8, 3916.1, 4152.7", \ + "5883.2, 5883.2, 5883.2, 6001.5, 6238.0"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("2102.0, 2102.0, 2102.0, 2220.3, 2456.8", \ + "2302.5, 2302.5, 2302.5, 2420.8, 2657.4", \ + "2696.9, 2696.9, 2696.9, 2815.2, 3051.8", \ + "3473.8, 3473.8, 3473.8, 3592.1, 3828.7", \ + "5013.3, 5013.3, 5013.3, 5131.6, 5368.1"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__37) { + values ("1645.8, 1645.8, 1645.8, 1764.1, 2000.6", \ + "1864.3, 1864.3, 1864.3, 1982.6, 2219.1", \ + "2288.0, 2288.0, 2288.0, 2406.2, 2642.8", \ + "3123.9, 3123.9, 3123.9, 3242.2, 3478.8", \ + "4780.7, 4780.7, 4780.7, 4899.0, 5135.6"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("1881.2, 1881.2, 1881.2, 1999.5, 2236.1", \ + "2068.4, 2068.4, 2068.4, 2186.6, 2423.2", \ + "2426.0, 2426.0, 2426.0, 2544.3, 2780.9", \ + "3120.5, 3120.5, 3120.5, 3238.8, 3475.4", \ + "4490.5, 4490.5, 4490.5, 4608.8, 4845.3"); + } + } + internal_power (energy_neg_nq_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__37) { + values ("1738.9, 1738.9, 1738.9, 1857.2, 2093.8", \ + "2012.8, 2012.8, 2012.8, 2131.1, 2367.7", \ + "2557.3, 2557.3, 2557.3, 2675.6, 2912.2", \ + "3631.1, 3631.1, 3631.1, 3749.4, 3986.0", \ + "5766.3, 5766.3, 5766.3, 5884.5, 6121.1"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("1929.9, 1929.9, 1929.9, 2048.2, 2284.8", \ + "2091.2, 2091.2, 2091.2, 2209.4, 2446.0", \ + "2405.9, 2405.9, 2405.9, 2524.2, 2760.8", \ + "3022.4, 3022.4, 3022.4, 3140.7, 3377.2", \ + "4237.1, 4237.1, 4237.1, 4355.4, 4592.0"); + } + } + } + } + + cell (noa2ao222_x1) { + area : 0.0 ; + cell_leakage_power : 0.013 ; + leakage_power () { + when : "(!(i4) & i3 & i2 & !(i1) & i0)" ; + value : 0.021 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & i4) | (!(i0) & i1 & i2 & i3 & !(i4)))" ; + value : 0.02 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & !(i0))" ; + value : 0.019 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & !(i0))" ; + value : 0.0075 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & !(i4)) | (!(i0) & ((i1 & (i2 ^ i3) & !(i4)) | (!(i1) & i2 & i3 & !(i4)))))" ; + value : 0.014 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4)) | (!(i0) & !(i1) & (i2 ^ i3) & !(i4)))" ; + value : 0.008 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.013 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0017 ; + } + pin (i4) { + direction : input ; + capacitance : 24.91 ; + } + pin (i3) { + direction : input ; + capacitance : 24.24 ; + } + pin (i2) { + direction : input ; + capacitance : 26.13 ; + } + pin (i1) { + direction : input ; + capacitance : 25.19 ; + } + pin (i0) { + direction : input ; + capacitance : 20.22 ; + } + pin (nq) { + function : "(((((!(i2) & !(i3)) & !(i1)) | ((!(i2) & !(i3)) & !(i0))) | (!(i4) & !(i1))) | (!(i4) & !(i0)))" ; + direction : output ; + capacitance : 9.45 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("30.8, 30.8, 30.8, 39.6, 56.8", \ + "34.2, 34.2, 34.2, 43.3, 61.2", \ + "40.5, 40.5, 40.5, 50.0, 68.5", \ + "52.7, 52.7, 52.7, 62.6, 81.8", \ + "76.9, 76.9, 76.9, 86.9, 106.7"); + } + rise_transition (inslew_load_5x5__38) { + values ("67.0, 67.0, 67.0, 81.9, 111.9", \ + "94.6, 94.6, 94.6, 109.2, 138.7", \ + "148.9, 148.9, 148.9, 164.3, 193.3", \ + "258.1, 258.1, 258.1, 272.7, 303.8", \ + "476.7, 476.7, 476.7, 491.3, 520.5"); + } + cell_fall (inslew_load_5x5__38) { + values ("20.2, 20.2, 20.2, 26.5, 38.3", \ + "23.0, 23.0, 23.0, 29.9, 42.9", \ + "27.3, 27.3, 27.3, 34.7, 48.9", \ + "34.9, 34.9, 34.9, 42.7, 57.8", \ + "49.7, 49.7, 49.7, 57.7, 73.4"); + } + fall_transition (inslew_load_5x5__38) { + values ("36.2, 36.2, 36.2, 43.5, 58.1", \ + "56.2, 56.2, 56.2, 63.6, 78.1", \ + "95.6, 95.6, 95.6, 103.1, 117.8", \ + "174.0, 174.0, 174.0, 181.6, 196.5", \ + "330.6, 330.6, 330.6, 338.2, 353.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("24.5, 24.5, 24.5, 33.5, 50.9", \ + "23.4, 23.4, 23.4, 32.8, 50.9", \ + "20.2, 20.2, 20.2, 30.2, 49.4", \ + "12.9, 12.9, 12.9, 23.5, 43.9", \ + "-2.2, -2.2, -2.2, 8.7, 30.1"); + } + rise_transition (inslew_load_5x5__38) { + values ("56.9, 56.9, 56.9, 71.7, 101.6", \ + "77.8, 77.8, 77.8, 92.4, 121.7", \ + "118.6, 118.6, 118.6, 133.2, 163.3", \ + "200.8, 200.8, 200.8, 215.5, 244.9", \ + "365.2, 365.2, 365.2, 380.0, 409.5"); + } + cell_fall (inslew_load_5x5__38) { + values ("22.4, 22.4, 22.4, 29.7, 42.8", \ + "29.5, 29.5, 29.5, 37.5, 52.4", \ + "41.8, 41.8, 41.8, 50.5, 67.0", \ + "65.5, 65.5, 65.5, 74.6, 92.2", \ + "112.1, 112.1, 112.1, 121.4, 139.8"); + } + fall_transition (inslew_load_5x5__38) { + values ("34.2, 34.2, 34.2, 41.8, 56.6", \ + "56.5, 56.5, 56.5, 64.3, 79.5", \ + "100.0, 100.0, 100.0, 108.0, 123.7", \ + "186.4, 186.4, 186.4, 194.5, 210.5", \ + "358.8, 358.8, 358.8, 366.9, 383.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("30.3, 30.3, 30.3, 40.9, 60.1", \ + "46.3, 46.3, 46.3, 57.9, 79.3", \ + "75.9, 75.9, 75.9, 88.3, 111.6", \ + "133.5, 133.5, 133.5, 146.3, 171.1", \ + "247.7, 247.7, 247.7, 260.8, 286.5"); + } + rise_transition (inslew_load_5x5__38) { + values ("52.2, 52.2, 52.2, 68.1, 99.2", \ + "89.1, 89.1, 89.1, 105.3, 137.2", \ + "160.3, 160.3, 160.3, 176.7, 209.2", \ + "300.8, 300.8, 300.8, 317.4, 350.3", \ + "580.8, 580.8, 580.8, 597.5, 630.7"); + } + cell_fall (inslew_load_5x5__38) { + values ("9.9, 9.9, 9.9, 16.9, 29.6", \ + "2.9, 2.9, 2.9, 11.1, 25.8", \ + "-13.1, -13.1, -13.1, -3.7, 13.3", \ + "-47.0, -47.0, -47.0, -36.7, -17.3", \ + "-116.0, -116.0, -116.0, -105.0, -83.9"); + } + fall_transition (inslew_load_5x5__38) { + values ("25.2, 25.2, 25.2, 32.7, 47.2", \ + "36.4, 36.4, 36.4, 44.2, 59.2", \ + "58.3, 58.3, 58.3, 66.4, 82.0", \ + "101.4, 101.4, 101.4, 109.7, 126.0", \ + "187.1, 187.1, 187.1, 195.7, 212.5"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("29.7, 29.7, 29.7, 39.0, 57.0", \ + "39.6, 39.6, 39.6, 49.4, 68.3", \ + "58.0, 58.0, 58.0, 68.4, 88.4", \ + "94.1, 94.1, 94.1, 104.9, 125.9", \ + "165.8, 165.8, 165.8, 176.8, 198.5"); + } + rise_transition (inslew_load_5x5__38) { + values ("58.0, 58.0, 58.0, 73.2, 103.3", \ + "90.0, 90.0, 90.0, 104.8, 135.3", \ + "152.9, 152.9, 152.9, 167.9, 197.7", \ + "278.1, 278.1, 278.1, 293.2, 323.3", \ + "528.2, 528.2, 528.2, 543.3, 573.6"); + } + cell_fall (inslew_load_5x5__38) { + values ("14.5, 14.5, 14.5, 21.1, 33.3", \ + "11.1, 11.1, 11.1, 18.7, 32.5", \ + "2.5, 2.5, 2.5, 11.0, 26.7", \ + "-16.0, -16.0, -16.0, -6.8, 10.4", \ + "-54.1, -54.1, -54.1, -44.5, -26.0"); + } + fall_transition (inslew_load_5x5__38) { + values ("29.9, 29.9, 29.9, 37.3, 51.8", \ + "44.1, 44.1, 44.1, 51.7, 66.5", \ + "72.0, 72.0, 72.0, 79.8, 95.0", \ + "127.2, 127.2, 127.2, 135.1, 150.8", \ + "237.3, 237.3, 237.3, 245.4, 261.3"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("14.7, 14.7, 14.7, 23.8, 39.3", \ + "18.6, 18.6, 18.6, 28.8, 46.7", \ + "25.2, 25.2, 25.2, 36.3, 56.4", \ + "37.7, 37.7, 37.7, 49.2, 71.1", \ + "62.2, 62.2, 62.2, 74.0, 97.0"); + } + rise_transition (inslew_load_5x5__38) { + values ("30.4, 30.4, 30.4, 41.5, 62.9", \ + "51.8, 51.8, 51.8, 63.3, 85.4", \ + "93.7, 93.7, 93.7, 105.4, 128.3", \ + "176.9, 176.9, 176.9, 188.8, 212.3", \ + "342.9, 342.9, 342.9, 355.0, 378.8"); + } + cell_fall (inslew_load_5x5__38) { + values ("11.6, 11.6, 11.6, 20.0, 34.4", \ + "11.6, 11.6, 11.6, 21.1, 37.7", \ + "10.3, 10.3, 10.3, 20.6, 39.4", \ + "6.9, 6.9, 6.9, 17.7, 38.3", \ + "-0.2, -0.2, -0.2, 10.8, 32.5"); + } + fall_transition (inslew_load_5x5__38) { + values ("24.0, 24.0, 24.0, 32.0, 47.1", \ + "40.6, 40.6, 40.6, 48.9, 64.6", \ + "73.0, 73.0, 73.0, 81.5, 97.9", \ + "137.3, 137.3, 137.3, 145.9, 162.9", \ + "265.5, 265.5, 265.5, 274.3, 291.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__38) { + values ("509.4, 509.4, 509.4, 627.6, 863.9", \ + "695.4, 695.4, 695.4, 813.6, 1049.9", \ + "1067.4, 1067.4, 1067.4, 1185.6, 1422.0", \ + "1811.5, 1811.5, 1811.5, 1929.6, 2166.0", \ + "3299.6, 3299.6, 3299.6, 3417.7, 3654.1"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("494.2, 494.2, 494.2, 612.4, 848.8", \ + "719.2, 719.2, 719.2, 837.4, 1073.7", \ + "1169.1, 1169.1, 1169.1, 1287.3, 1523.7", \ + "2069.1, 2069.1, 2069.1, 2187.2, 2423.6", \ + "3868.9, 3868.9, 3868.9, 3987.1, 4223.4"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__38) { + values ("419.1, 419.1, 419.1, 537.3, 773.6", \ + "550.8, 550.8, 550.8, 669.0, 905.3", \ + "814.2, 814.2, 814.2, 932.4, 1168.7", \ + "1341.0, 1341.0, 1341.0, 1459.2, 1695.6", \ + "2394.7, 2394.7, 2394.7, 2512.8, 2749.2"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("426.3, 426.3, 426.3, 544.5, 780.9", \ + "647.9, 647.9, 647.9, 766.1, 1002.4", \ + "1091.0, 1091.0, 1091.0, 1209.1, 1445.5", \ + "1977.1, 1977.1, 1977.1, 2095.3, 2331.7", \ + "3749.5, 3749.5, 3749.5, 3867.7, 4104.0"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__38) { + values ("365.7, 365.7, 365.7, 483.9, 720.3", \ + "562.7, 562.7, 562.7, 680.9, 917.2", \ + "956.6, 956.6, 956.6, 1074.7, 1311.1", \ + "1744.3, 1744.3, 1744.3, 1862.5, 2098.9", \ + "3319.8, 3319.8, 3319.8, 3438.0, 3674.4"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("303.9, 303.9, 303.9, 422.1, 658.5", \ + "399.6, 399.6, 399.6, 517.8, 754.2", \ + "591.0, 591.0, 591.0, 709.1, 945.5", \ + "973.6, 973.6, 973.6, 1091.8, 1328.2", \ + "1739.0, 1739.0, 1739.0, 1857.2, 2093.6"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__38) { + values ("439.2, 439.2, 439.2, 557.4, 793.7", \ + "638.4, 638.4, 638.4, 756.6, 992.9", \ + "1036.8, 1036.8, 1036.8, 1155.0, 1391.3", \ + "1833.6, 1833.6, 1833.6, 1951.8, 2188.1", \ + "3427.2, 3427.2, 3427.2, 3545.4, 3781.7"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("383.4, 383.4, 383.4, 501.6, 738.0", \ + "521.4, 521.4, 521.4, 639.6, 875.9", \ + "797.3, 797.3, 797.3, 915.5, 1151.9", \ + "1349.1, 1349.1, 1349.1, 1467.3, 1703.7", \ + "2452.8, 2452.8, 2452.8, 2571.0, 2807.4"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__38) { + values ("264.2, 264.2, 264.2, 382.4, 618.7", \ + "410.2, 410.2, 410.2, 528.4, 764.8", \ + "702.2, 702.2, 702.2, 820.4, 1056.8", \ + "1286.3, 1286.3, 1286.3, 1404.5, 1640.8", \ + "2454.4, 2454.4, 2454.4, 2572.6, 2808.9"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("263.4, 263.4, 263.4, 381.6, 618.0", \ + "408.7, 408.7, 408.7, 526.9, 763.2", \ + "699.2, 699.2, 699.2, 817.4, 1053.8", \ + "1280.2, 1280.2, 1280.2, 1398.4, 1634.8", \ + "2442.3, 2442.3, 2442.3, 2560.5, 2796.8"); + } + } + } + } + + cell (noa2ao222_x4) { + area : 0.0 ; + cell_leakage_power : 0.017 ; + leakage_power () { + when : "((i0 ^ i1) & i2 & i3 & !(i4))" ; + value : 0.025 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & !(i3) & i4)" ; + value : 0.023 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & !(i4)) | (!(i0) & ((i1 & (i2 ^ i3) & !(i4)) | (!(i1) & i2 & i3 & !(i4)))))" ; + value : 0.021 ; + } + leakage_power () { + when : "((i0 & i1) | ((i2 | i3) & i4))" ; + value : 0.002 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4)) | (!(i0) & ((i1 & !(i2) & !(i3) & !(i4)) | (!(i1) & (i2 ^ i3) & !(i4)))))" ; + value : 0.017 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.02 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.013 ; + } + pin (i4) { + direction : input ; + capacitance : 21.29 ; + } + pin (i3) { + direction : input ; + capacitance : 18.34 ; + } + pin (i2) { + direction : input ; + capacitance : 23.55 ; + } + pin (i1) { + direction : input ; + capacitance : 21.16 ; + } + pin (i0) { + direction : input ; + capacitance : 18.35 ; + } + pin (nq) { + function : "((!(i4) & (!(i0) | !(i1))) | (!((i0 & i1)) & !(i3) & !(i2)))" ; + direction : output ; + capacitance : 9.14 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("127.1, 127.1, 127.1, 130.9, 137.8", \ + "134.2, 134.2, 134.2, 138.1, 145.1", \ + "145.4, 145.4, 145.4, 149.3, 156.6", \ + "162.5, 162.5, 162.5, 166.5, 174.1", \ + "190.3, 190.3, 190.3, 194.5, 202.4"); + } + rise_transition (inslew_load_5x5__39) { + values ("27.4, 27.4, 27.4, 30.5, 36.5", \ + "30.0, 30.0, 30.0, 33.1, 39.1", \ + "35.0, 35.0, 35.0, 38.2, 44.2", \ + "45.2, 45.2, 45.2, 48.3, 54.4", \ + "65.1, 65.1, 65.1, 68.1, 74.3"); + } + cell_fall (inslew_load_5x5__39) { + values ("100.5, 100.5, 100.5, 104.5, 111.9", \ + "109.0, 109.0, 109.0, 113.0, 120.5", \ + "120.8, 120.8, 120.8, 124.8, 132.4", \ + "137.2, 137.2, 137.2, 141.3, 149.0", \ + "161.1, 161.1, 161.1, 165.3, 173.2"); + } + fall_transition (inslew_load_5x5__39) { + values ("28.7, 28.7, 28.7, 31.7, 37.4", \ + "31.1, 31.1, 31.1, 34.1, 39.9", \ + "35.9, 35.9, 35.9, 38.9, 44.7", \ + "44.8, 44.8, 44.8, 47.8, 53.7", \ + "61.8, 61.8, 61.8, 64.8, 70.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("120.9, 120.9, 120.9, 124.7, 131.6", \ + "123.8, 123.8, 123.8, 127.7, 134.6", \ + "125.9, 125.9, 125.9, 129.7, 136.9", \ + "124.0, 124.0, 124.0, 127.9, 135.4", \ + "112.6, 112.6, 112.6, 116.8, 124.5"); + } + rise_transition (inslew_load_5x5__39) { + values ("26.5, 26.5, 26.5, 29.7, 35.6", \ + "28.5, 28.5, 28.5, 31.6, 37.6", \ + "32.3, 32.3, 32.3, 35.5, 41.5", \ + "40.1, 40.1, 40.1, 43.2, 49.3", \ + "55.1, 55.1, 55.1, 58.2, 64.4"); + } + cell_fall (inslew_load_5x5__39) { + values ("104.9, 104.9, 104.9, 108.9, 116.3", \ + "119.2, 119.2, 119.2, 123.2, 130.7", \ + "140.1, 140.1, 140.1, 144.1, 151.7", \ + "173.0, 173.0, 173.0, 177.2, 184.9", \ + "229.0, 229.0, 229.0, 233.2, 241.2"); + } + fall_transition (inslew_load_5x5__39) { + values ("28.5, 28.5, 28.5, 31.5, 37.2", \ + "31.3, 31.3, 31.3, 34.3, 40.1", \ + "36.5, 36.5, 36.5, 39.6, 45.4", \ + "46.2, 46.2, 46.2, 49.3, 55.2", \ + "64.7, 64.7, 64.7, 67.7, 73.7"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("121.9, 121.9, 121.9, 125.8, 132.7", \ + "142.1, 142.1, 142.1, 145.9, 152.9", \ + "172.9, 172.9, 172.9, 176.8, 184.1", \ + "225.7, 225.7, 225.7, 229.8, 237.4", \ + "323.1, 323.1, 323.1, 327.4, 335.3"); + } + rise_transition (inslew_load_5x5__39) { + values ("25.6, 25.6, 25.6, 28.7, 34.6", \ + "29.2, 29.2, 29.2, 32.4, 38.4", \ + "36.0, 36.0, 36.0, 39.1, 45.2", \ + "49.0, 49.0, 49.0, 52.1, 58.3", \ + "74.6, 74.6, 74.6, 77.6, 83.7"); + } + cell_fall (inslew_load_5x5__39) { + values ("88.7, 88.7, 88.7, 92.7, 100.0", \ + "90.0, 90.0, 90.0, 94.1, 101.4", \ + "87.1, 87.1, 87.1, 91.1, 98.6", \ + "73.8, 73.8, 73.8, 77.9, 85.5", \ + "38.0, 38.0, 38.0, 42.2, 50.0"); + } + fall_transition (inslew_load_5x5__39) { + values ("27.1, 27.1, 27.1, 30.1, 35.8", \ + "28.9, 28.9, 28.9, 31.9, 37.6", \ + "32.2, 32.2, 32.2, 35.2, 41.0", \ + "38.3, 38.3, 38.3, 41.3, 47.2", \ + "49.8, 49.8, 49.8, 52.8, 58.8"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("117.6, 117.6, 117.6, 121.5, 128.4", \ + "125.3, 125.3, 125.3, 129.2, 136.1", \ + "135.9, 135.9, 135.9, 139.8, 146.9", \ + "149.5, 149.5, 149.5, 153.5, 161.0", \ + "168.7, 168.7, 168.7, 172.9, 180.7"); + } + rise_transition (inslew_load_5x5__39) { + values ("25.7, 25.7, 25.7, 28.8, 34.7", \ + "28.0, 28.0, 28.0, 31.2, 37.1", \ + "32.7, 32.7, 32.7, 35.8, 41.8", \ + "41.7, 41.7, 41.7, 44.8, 50.9", \ + "59.3, 59.3, 59.3, 62.4, 68.6"); + } + cell_fall (inslew_load_5x5__39) { + values ("104.8, 104.8, 104.8, 108.8, 116.2", \ + "114.0, 114.0, 114.0, 118.0, 125.5", \ + "126.0, 126.0, 126.0, 130.1, 137.6", \ + "141.8, 141.8, 141.8, 145.9, 153.6", \ + "163.8, 163.8, 163.8, 167.9, 175.9"); + } + fall_transition (inslew_load_5x5__39) { + values ("28.9, 28.9, 28.9, 31.9, 37.7", \ + "31.3, 31.3, 31.3, 34.4, 40.2", \ + "35.9, 35.9, 35.9, 38.9, 44.8", \ + "44.4, 44.4, 44.4, 47.5, 53.4", \ + "60.6, 60.6, 60.6, 63.7, 69.6"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("99.5, 99.5, 99.5, 103.3, 110.1", \ + "107.5, 107.5, 107.5, 111.4, 118.2", \ + "116.6, 116.6, 116.6, 120.4, 127.3", \ + "126.1, 126.1, 126.1, 130.0, 137.4", \ + "136.7, 136.7, 136.7, 140.9, 148.5"); + } + rise_transition (inslew_load_5x5__39) { + values ("22.5, 22.5, 22.5, 25.6, 31.4", \ + "24.7, 24.7, 24.7, 27.8, 33.7", \ + "28.9, 28.9, 28.9, 32.1, 38.0", \ + "37.0, 37.0, 37.0, 40.1, 46.2", \ + "52.7, 52.7, 52.7, 55.8, 62.0"); + } + cell_fall (inslew_load_5x5__39) { + values ("95.6, 95.6, 95.6, 99.6, 107.0", \ + "106.3, 106.3, 106.3, 110.3, 117.8", \ + "120.8, 120.8, 120.8, 124.9, 132.4", \ + "141.6, 141.6, 141.6, 145.8, 153.4", \ + "173.7, 173.7, 173.7, 177.9, 185.9"); + } + fall_transition (inslew_load_5x5__39) { + values ("27.5, 27.5, 27.5, 30.5, 36.2", \ + "30.2, 30.2, 30.2, 33.2, 38.9", \ + "34.9, 34.9, 34.9, 37.9, 43.7", \ + "43.8, 43.8, 43.8, 46.8, 52.7", \ + "60.5, 60.5, 60.5, 63.5, 69.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__39) { + values ("2057.7, 2057.7, 2057.7, 2171.9, 2400.3", \ + "2288.0, 2288.0, 2288.0, 2402.2, 2630.6", \ + "2745.4, 2745.4, 2745.4, 2859.7, 3088.1", \ + "3661.0, 3661.0, 3661.0, 3775.2, 4003.6", \ + "5483.7, 5483.7, 5483.7, 5598.0, 5826.4"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("2003.4, 2003.4, 2003.4, 2117.6, 2346.0", \ + "2252.0, 2252.0, 2252.0, 2366.3, 2594.7", \ + "2744.5, 2744.5, 2744.5, 2858.7, 3087.1", \ + "3717.3, 3717.3, 3717.3, 3831.5, 4059.9", \ + "5645.0, 5645.0, 5645.0, 5759.2, 5987.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1961.4, 1961.4, 1961.4, 2075.6, 2304.0", \ + "2128.8, 2128.8, 2128.8, 2243.0, 2471.5", \ + "2460.5, 2460.5, 2460.5, 2574.7, 2803.1", \ + "3123.3, 3123.3, 3123.3, 3237.6, 3466.0", \ + "4440.5, 4440.5, 4440.5, 4554.7, 4783.1"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("1947.2, 1947.2, 1947.2, 2061.4, 2289.9", \ + "2204.2, 2204.2, 2204.2, 2318.4, 2546.8", \ + "2706.1, 2706.1, 2706.1, 2820.4, 3048.8", \ + "3692.1, 3692.1, 3692.1, 3806.3, 4034.8", \ + "5645.2, 5645.2, 5645.2, 5759.4, 5987.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1836.9, 1836.9, 1836.9, 1951.1, 2179.5", \ + "2121.8, 2121.8, 2121.8, 2236.0, 2464.5", \ + "2670.9, 2670.9, 2670.9, 2785.1, 3013.5", \ + "3752.4, 3752.4, 3752.4, 3866.6, 4095.1", \ + "5900.6, 5900.6, 5900.6, 6014.9, 6243.3"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("1799.9, 1799.9, 1799.9, 1914.1, 2142.5", \ + "1951.4, 1951.4, 1951.4, 2065.7, 2294.1", \ + "2248.3, 2248.3, 2248.3, 2362.5, 2590.9", \ + "2830.7, 2830.7, 2830.7, 2944.9, 3173.3", \ + "3979.2, 3979.2, 3979.2, 4093.4, 4321.8"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1873.9, 1873.9, 1873.9, 1988.2, 2216.6", \ + "2068.3, 2068.3, 2068.3, 2182.5, 2411.0", \ + "2455.6, 2455.6, 2455.6, 2569.9, 2798.3", \ + "3220.4, 3220.4, 3220.4, 3334.7, 3563.1", \ + "4739.4, 4739.4, 4739.4, 4853.6, 5082.1"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("1939.9, 1939.9, 1939.9, 2054.1, 2282.6", \ + "2149.2, 2149.2, 2149.2, 2263.4, 2491.9", \ + "2559.9, 2559.9, 2559.9, 2674.2, 2902.6", \ + "3367.7, 3367.7, 3367.7, 3481.9, 3710.3", \ + "4963.9, 4963.9, 4963.9, 5078.1, 5306.6"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1638.2, 1638.2, 1638.2, 1752.4, 1980.8", \ + "1823.6, 1823.6, 1823.6, 1937.9, 2166.3", \ + "2185.2, 2185.2, 2185.2, 2299.5, 2527.9", \ + "2897.0, 2897.0, 2897.0, 3011.2, 3239.7", \ + "4307.3, 4307.3, 4307.3, 4421.5, 4650.0"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("1782.6, 1782.6, 1782.6, 1896.8, 2125.2", \ + "1997.9, 1997.9, 1997.9, 2112.1, 2340.6", \ + "2414.7, 2414.7, 2414.7, 2528.9, 2757.4", \ + "3234.2, 3234.2, 3234.2, 3348.4, 3576.8", \ + "4852.4, 4852.4, 4852.4, 4966.6, 5195.1"); + } + } + } + } + + cell (noa3ao322_x1) { + area : 0.0 ; + cell_leakage_power : 0.013 ; + leakage_power () { + when : "(!(i6) & i5 & i4 & i3 & !(i2) & i1 & i0)" ; + value : 0.025 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 0.0073 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & i6) | (!(i1) & i2 & i3 & i4 & i5 & !(i6)))) | (!(i0) & i1 & i2 & i3 & i4 & i5 & !(i6)))" ; + value : 0.024 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & !(i4) & !(i5) & i6)" ; + value : 0.023 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & i2 & i1 & !(i0))" ; + value : 0.0072 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))) | (!(i0) & (i1 ^ i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))" ; + value : 0.0077 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & !(i6)))" ; + value : 0.002 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i1) & ((i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i2) & i3 & i4 & i5 & !(i6)))))) | (!(i0) & ((i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!((i1 & i2)) & i3 & i4 & i5 & !(i6)))))" ; + value : 0.019 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!(i1) & ((i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))))) | (!(i0) & ((i1 & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!((i1 & i2)) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))))" ; + value : 0.013 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 0.0075 ; + } + leakage_power () { + when : "((!(i0) & !((i1 & i2)) & !(i3) & !(i4) & !(i5) & i6) | (!(i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6))" ; + value : 0.018 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0018 ; + } + pin (i6) { + direction : input ; + capacitance : 18.69 ; + } + pin (i5) { + direction : input ; + capacitance : 19.59 ; + } + pin (i4) { + direction : input ; + capacitance : 19.59 ; + } + pin (i3) { + direction : input ; + capacitance : 19.59 ; + } + pin (i2) { + direction : input ; + capacitance : 19.59 ; + } + pin (i1) { + direction : input ; + capacitance : 19.87 ; + } + pin (i0) { + direction : input ; + capacitance : 19.24 ; + } + pin (nq) { + function : "((((((!(i6) & !(i2)) | (!(i6) & !(i1))) | (!(i6) & !(i0))) | (((!(i3) & !(i4)) & !(i5)) & !(i2))) | (((!(i3) & !(i4)) & !(i5)) & !(i1))) | (((!(i3) & !(i4)) & !(i5)) & !(i0)))" ; + direction : output ; + capacitance : 9.27 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("46.0, 46.0, 46.0, 56.7, 78.1", \ + "49.3, 49.3, 49.3, 60.2, 81.9", \ + "55.9, 55.9, 55.9, 67.3, 89.4", \ + "69.1, 69.1, 69.1, 80.6, 103.3", \ + "95.6, 95.6, 95.6, 107.3, 130.5"); + } + rise_transition (inslew_load_5x5__40) { + values ("98.5, 98.5, 98.5, 118.0, 157.2", \ + "129.3, 129.3, 129.3, 148.7, 187.7", \ + "191.4, 191.4, 191.4, 210.5, 248.9", \ + "316.4, 316.4, 316.4, 335.3, 373.1", \ + "567.2, 567.2, 567.2, 585.9, 623.4"); + } + cell_fall (inslew_load_5x5__40) { + values ("31.1, 31.1, 31.1, 38.8, 53.8", \ + "36.3, 36.3, 36.3, 44.4, 60.1", \ + "45.4, 45.4, 45.4, 54.0, 70.5", \ + "62.8, 62.8, 62.8, 71.7, 89.0", \ + "96.9, 96.9, 96.9, 106.0, 124.0"); + } + fall_transition (inslew_load_5x5__40) { + values ("58.9, 58.9, 58.9, 70.2, 92.9", \ + "85.4, 85.4, 85.4, 96.9, 119.3", \ + "138.0, 138.0, 138.0, 149.2, 171.6", \ + "242.7, 242.7, 242.7, 254.0, 276.5", \ + "452.1, 452.1, 452.1, 463.3, 485.9"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("39.8, 39.8, 39.8, 50.6, 72.2", \ + "38.1, 38.1, 38.1, 49.2, 71.1", \ + "34.4, 34.4, 34.4, 45.9, 68.7", \ + "26.4, 26.4, 26.4, 38.5, 62.0", \ + "9.9, 9.9, 9.9, 22.3, 46.7"); + } + rise_transition (inslew_load_5x5__40) { + values ("87.7, 87.7, 87.7, 107.3, 146.4", \ + "110.1, 110.1, 110.1, 129.4, 168.3", \ + "155.8, 155.8, 155.8, 174.8, 212.9", \ + "248.3, 248.3, 248.3, 267.0, 304.6", \ + "429.9, 429.9, 429.9, 448.8, 489.8"); + } + cell_fall (inslew_load_5x5__40) { + values ("31.8, 31.8, 31.8, 39.9, 55.5", \ + "40.9, 40.9, 40.9, 49.6, 66.3", \ + "57.1, 57.1, 57.1, 66.4, 84.4", \ + "88.3, 88.3, 88.3, 98.1, 117.1", \ + "150.0, 150.0, 150.0, 160.1, 179.8"); + } + fall_transition (inslew_load_5x5__40) { + values ("53.9, 53.9, 53.9, 65.4, 88.1", \ + "81.9, 81.9, 81.9, 93.3, 116.1", \ + "136.9, 136.9, 136.9, 148.4, 171.3", \ + "246.0, 246.0, 246.0, 257.6, 280.6", \ + "463.8, 463.8, 463.8, 475.4, 498.6"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("34.2, 34.2, 34.2, 45.1, 66.8", \ + "29.3, 29.3, 29.3, 40.7, 62.7", \ + "19.2, 19.2, 19.2, 31.0, 54.0", \ + "-2.2, -2.2, -2.2, 10.3, 34.7", \ + "-46.6, -46.6, -46.6, -33.3, -7.5"); + } + rise_transition (inslew_load_5x5__40) { + values ("78.0, 78.0, 78.0, 97.5, 136.7", \ + "95.5, 95.5, 95.5, 114.7, 153.4", \ + "131.6, 131.6, 131.6, 150.5, 188.4", \ + "202.7, 202.7, 202.7, 221.7, 261.0", \ + "346.2, 346.2, 346.2, 365.3, 403.2"); + } + cell_fall (inslew_load_5x5__40) { + values ("32.7, 32.7, 32.7, 41.7, 58.5", \ + "46.0, 46.0, 46.0, 55.9, 74.4", \ + "69.6, 69.6, 69.6, 80.2, 100.5", \ + "114.9, 114.9, 114.9, 126.1, 147.8", \ + "204.5, 204.5, 204.5, 216.0, 238.6"); + } + fall_transition (inslew_load_5x5__40) { + values ("49.6, 49.6, 49.6, 61.3, 84.7", \ + "79.9, 79.9, 79.9, 91.8, 115.4", \ + "138.1, 138.1, 138.1, 150.2, 174.2", \ + "253.1, 253.1, 253.1, 265.4, 289.7", \ + "482.3, 482.3, 482.3, 494.6, 519.2"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("31.5, 31.5, 31.5, 42.6, 65.7", \ + "48.7, 48.7, 48.7, 61.6, 85.1", \ + "81.3, 81.3, 81.3, 95.0, 121.2", \ + "145.4, 145.4, 145.4, 159.6, 187.3", \ + "272.9, 272.9, 272.9, 287.4, 316.0"); + } + rise_transition (inslew_load_5x5__40) { + values ("59.0, 59.0, 59.0, 77.3, 117.4", \ + "98.8, 98.8, 98.8, 118.6, 156.9", \ + "176.5, 176.5, 176.5, 196.7, 236.8", \ + "330.9, 330.9, 330.9, 351.3, 391.8", \ + "638.9, 638.9, 638.9, 659.5, 700.3"); + } + cell_fall (inslew_load_5x5__40) { + values ("10.9, 10.9, 10.9, 18.3, 31.6", \ + "2.8, 2.8, 2.8, 11.6, 27.1", \ + "-16.0, -16.0, -16.0, -5.8, 12.5", \ + "-56.5, -56.5, -56.5, -45.0, -23.7", \ + "-139.3, -139.3, -139.3, -126.8, -103.1"); + } + fall_transition (inslew_load_5x5__40) { + values ("26.2, 26.2, 26.2, 34.1, 49.6", \ + "36.3, 36.3, 36.3, 44.5, 60.5", \ + "55.7, 55.7, 55.7, 64.4, 81.1", \ + "93.8, 93.8, 93.8, 102.9, 120.5", \ + "169.4, 169.4, 169.4, 178.7, 197.1"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("37.2, 37.2, 37.2, 48.8, 71.3", \ + "51.4, 51.4, 51.4, 63.5, 86.9", \ + "78.1, 78.1, 78.1, 90.8, 115.3", \ + "129.9, 129.9, 129.9, 143.1, 168.8", \ + "233.0, 233.0, 233.0, 246.4, 272.9"); + } + rise_transition (inslew_load_5x5__40) { + values ("71.3, 71.3, 71.3, 91.1, 131.0", \ + "109.6, 109.6, 109.6, 129.2, 169.0", \ + "185.2, 185.2, 185.2, 204.8, 243.8", \ + "334.5, 334.5, 334.5, 354.2, 393.5", \ + "632.5, 632.5, 632.5, 652.3, 691.8"); + } + cell_fall (inslew_load_5x5__40) { + values ("15.0, 15.0, 15.0, 22.0, 34.9", \ + "9.5, 9.5, 9.5, 17.7, 32.5", \ + "-3.9, -3.9, -3.9, 5.3, 22.5", \ + "-33.3, -33.3, -33.3, -22.9, -3.4", \ + "-93.8, -93.8, -93.8, -82.7, -61.4"); + } + fall_transition (inslew_load_5x5__40) { + values ("30.3, 30.3, 30.3, 38.2, 53.6", \ + "42.5, 42.5, 42.5, 50.6, 66.3", \ + "66.0, 66.0, 66.0, 74.4, 90.8", \ + "112.4, 112.4, 112.4, 121.1, 138.1", \ + "204.6, 204.6, 204.6, 213.5, 231.0"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("41.3, 41.3, 41.3, 52.4, 74.1", \ + "50.9, 50.9, 50.9, 62.4, 84.8", \ + "69.2, 69.2, 69.2, 81.1, 104.3", \ + "105.2, 105.2, 105.2, 117.5, 141.5", \ + "177.0, 177.0, 177.0, 189.5, 214.1"); + } + rise_transition (inslew_load_5x5__40) { + values ("83.5, 83.5, 83.5, 103.1, 142.6", \ + "119.4, 119.4, 119.4, 138.6, 177.5", \ + "190.7, 190.7, 190.7, 209.8, 248.0", \ + "330.6, 330.6, 330.6, 349.8, 390.3", \ + "612.5, 612.5, 612.5, 631.8, 670.0"); + } + cell_fall (inslew_load_5x5__40) { + values ("18.8, 18.8, 18.8, 25.5, 38.2", \ + "16.9, 16.9, 16.9, 24.5, 38.7", \ + "11.0, 11.0, 11.0, 19.5, 35.5", \ + "-2.4, -2.4, -2.4, 6.7, 24.3", \ + "-30.8, -30.8, -30.8, -21.1, -2.2"); + } + fall_transition (inslew_load_5x5__40) { + values ("34.4, 34.4, 34.4, 42.2, 57.7", \ + "49.7, 49.7, 49.7, 57.7, 73.3", \ + "79.7, 79.7, 79.7, 87.8, 103.8", \ + "139.0, 139.0, 139.0, 147.3, 163.7", \ + "257.2, 257.2, 257.2, 265.6, 282.4"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("13.5, 13.5, 13.5, 22.5, 37.8", \ + "16.2, 16.2, 16.2, 26.3, 44.2", \ + "20.1, 20.1, 20.1, 31.2, 51.5", \ + "27.3, 27.3, 27.3, 39.0, 61.1", \ + "41.3, 41.3, 41.3, 53.4, 76.7"); + } + rise_transition (inslew_load_5x5__40) { + values ("29.3, 29.3, 29.3, 40.2, 61.2", \ + "49.3, 49.3, 49.3, 60.6, 82.5", \ + "88.6, 88.6, 88.6, 100.2, 122.8", \ + "166.6, 166.6, 166.6, 178.4, 201.6", \ + "322.2, 322.2, 322.2, 334.1, 357.8"); + } + cell_fall (inslew_load_5x5__40) { + values ("13.1, 13.1, 13.1, 21.8, 36.7", \ + "14.3, 14.3, 14.3, 24.1, 41.3", \ + "15.4, 15.4, 15.4, 26.0, 45.5", \ + "16.8, 16.8, 16.8, 28.0, 49.2", \ + "19.2, 19.2, 19.2, 30.7, 53.0"); + } + fall_transition (inslew_load_5x5__40) { + values ("25.2, 25.2, 25.2, 33.6, 49.6", \ + "42.8, 42.8, 42.8, 51.5, 68.1", \ + "77.2, 77.2, 77.2, 86.1, 103.3", \ + "145.2, 145.2, 145.2, 154.3, 172.1", \ + "281.1, 281.1, 281.1, 290.3, 308.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__40) { + values ("572.8, 572.8, 572.8, 688.6, 920.3", \ + "742.3, 742.3, 742.3, 858.2, 1089.8", \ + "1081.3, 1081.3, 1081.3, 1197.2, 1428.8", \ + "1759.4, 1759.4, 1759.4, 1875.2, 2106.9", \ + "3115.5, 3115.5, 3115.5, 3231.3, 3463.0"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("559.0, 559.0, 559.0, 674.8, 906.4", \ + "782.7, 782.7, 782.7, 898.6, 1130.2", \ + "1230.3, 1230.3, 1230.3, 1346.1, 1577.8", \ + "2125.4, 2125.4, 2125.4, 2241.2, 2472.9", \ + "3915.6, 3915.6, 3915.6, 4031.4, 4263.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__40) { + values ("500.4, 500.4, 500.4, 616.3, 847.9", \ + "619.0, 619.0, 619.0, 734.8, 966.5", \ + "856.2, 856.2, 856.2, 972.0, 1203.7", \ + "1330.5, 1330.5, 1330.5, 1446.4, 1678.0", \ + "2279.2, 2279.2, 2279.2, 2395.1, 2626.7"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("500.3, 500.3, 500.3, 616.1, 847.8", \ + "719.3, 719.3, 719.3, 835.2, 1066.8", \ + "1157.5, 1157.5, 1157.5, 1273.3, 1505.0", \ + "2033.7, 2033.7, 2033.7, 2149.5, 2381.2", \ + "3786.2, 3786.2, 3786.2, 3902.0, 4133.7"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__40) { + values ("437.7, 437.7, 437.7, 553.5, 785.2", \ + "526.1, 526.1, 526.1, 641.9, 873.6", \ + "702.8, 702.8, 702.8, 818.7, 1050.3", \ + "1056.4, 1056.4, 1056.4, 1172.2, 1403.9", \ + "1763.5, 1763.5, 1763.5, 1879.3, 2111.0"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("434.8, 434.8, 434.8, 550.6, 782.2", \ + "645.4, 645.4, 645.4, 761.3, 992.9", \ + "1066.7, 1066.7, 1066.7, 1182.6, 1414.2", \ + "1909.4, 1909.4, 1909.4, 2025.2, 2256.9", \ + "3594.7, 3594.7, 3594.7, 3710.6, 3942.2"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__40) { + values ("351.2, 351.2, 351.2, 467.0, 698.7", \ + "530.1, 530.1, 530.1, 646.0, 877.6", \ + "888.0, 888.0, 888.0, 1003.8, 1235.4", \ + "1603.6, 1603.6, 1603.6, 1719.4, 1951.1", \ + "3034.9, 3034.9, 3034.9, 3150.7, 3382.4"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("291.6, 291.6, 291.6, 407.4, 639.1", \ + "364.1, 364.1, 364.1, 479.9, 711.6", \ + "509.1, 509.1, 509.1, 624.9, 856.6", \ + "799.1, 799.1, 799.1, 914.9, 1146.6", \ + "1379.0, 1379.0, 1379.0, 1494.9, 1726.5"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__40) { + values ("425.9, 425.9, 425.9, 541.8, 773.4", \ + "608.7, 608.7, 608.7, 724.5, 956.2", \ + "974.1, 974.1, 974.1, 1090.0, 1321.6", \ + "1705.1, 1705.1, 1705.1, 1820.9, 2052.6", \ + "3167.0, 3167.0, 3167.0, 3282.9, 3514.5"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("355.6, 355.6, 355.6, 471.4, 703.1", \ + "453.5, 453.5, 453.5, 569.4, 801.0", \ + "649.4, 649.4, 649.4, 765.3, 996.9", \ + "1041.2, 1041.2, 1041.2, 1157.0, 1388.7", \ + "1824.8, 1824.8, 1824.8, 1940.6, 2172.3"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__40) { + values ("490.9, 490.9, 490.9, 606.8, 838.4", \ + "673.3, 673.3, 673.3, 789.2, 1020.8", \ + "1038.2, 1038.2, 1038.2, 1154.0, 1385.7", \ + "1767.8, 1767.8, 1767.8, 1883.6, 2115.3", \ + "3227.0, 3227.0, 3227.0, 3342.8, 3574.5"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("421.1, 421.1, 421.1, 536.9, 768.6", \ + "561.6, 561.6, 561.6, 677.5, 909.1", \ + "842.7, 842.7, 842.7, 958.5, 1190.2", \ + "1404.7, 1404.7, 1404.7, 1520.6, 1752.2", \ + "2528.8, 2528.8, 2528.8, 2644.7, 2876.3"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__40) { + values ("249.3, 249.3, 249.3, 365.1, 596.8", \ + "382.8, 382.8, 382.8, 498.6, 730.3", \ + "649.7, 649.7, 649.7, 765.5, 997.2", \ + "1183.5, 1183.5, 1183.5, 1299.4, 1531.0", \ + "2251.2, 2251.2, 2251.2, 2367.1, 2598.7"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("261.2, 261.2, 261.2, 377.1, 608.7", \ + "406.7, 406.7, 406.7, 522.5, 754.2", \ + "697.5, 697.5, 697.5, 813.3, 1045.0", \ + "1279.1, 1279.1, 1279.1, 1395.0, 1626.6", \ + "2442.4, 2442.4, 2442.4, 2558.2, 2789.9"); + } + } + } + } + + cell (noa3ao322_x4) { + area : 0.0 ; + cell_leakage_power : 0.016 ; + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 0.017 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i0) & i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))" ; + value : 0.021 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & ((i3 & i4 & i5 & !(i6)) | (!(i3) & !(i4) & !(i5) & i6))) | (!(i0) & i1 & i2 & ((i3 & i4 & i5 & !(i6)) | (!(i3) & !(i4) & !(i5) & i6))))" ; + value : 0.023 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))) | (!(i1) & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))))" ; + value : 0.016 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & i4 & i5 & !(i6)) | (!(i3) & !(i4) & !(i5) & i6))) | (!(i0) & ((i1 & !(i2) & ((i3 & i4 & i5 & !(i6)) | (!(i3) & !(i4) & !(i5) & i6))) | (!(i1) & ((i2 & ((i3 & i4 & i5 & !(i6)) | (!(i3) & !(i4) & !(i5) & i6))) | (i3 & i4 & i5 & !(i6)))))))" ; + value : 0.02 ; + } + leakage_power () { + when : "((!(i0) & !((i1 & i2)) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i1) & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))" ; + value : 0.018 ; + } + leakage_power () { + when : "((i0 & i1 & i2) | ((i3 | i4 | i5) & i6))" ; + value : 0.0031 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 0.015 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!(i0) & ((i1 & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!(i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6))))" ; + value : 0.019 ; + } + leakage_power () { + when : "((!(i0) & !((i1 & i2)) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)))" ; + value : 0.013 ; + } + pin (i6) { + direction : input ; + capacitance : 20.17 ; + } + pin (i5) { + direction : input ; + capacitance : 19.04 ; + } + pin (i4) { + direction : input ; + capacitance : 19.39 ; + } + pin (i3) { + direction : input ; + capacitance : 19.74 ; + } + pin (i2) { + direction : input ; + capacitance : 19.32 ; + } + pin (i1) { + direction : input ; + capacitance : 20.47 ; + } + pin (i0) { + direction : input ; + capacitance : 20.47 ; + } + pin (nq) { + function : "((!((i5 | i4 | i3)) & (!(i1) | !(i2) | !(i0))) | (!((i1 & i2 & i0)) & !(i6)))" ; + direction : output ; + capacitance : 9.02 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("155.4, 155.4, 155.4, 159.2, 166.1", \ + "163.3, 163.3, 163.3, 167.2, 174.2", \ + "178.4, 178.4, 178.4, 182.3, 189.6", \ + "205.2, 205.2, 205.2, 209.3, 216.8", \ + "255.2, 255.2, 255.2, 259.4, 267.3"); + } + rise_transition (inslew_load_5x5__41) { + values ("30.3, 30.3, 30.3, 33.5, 39.4", \ + "33.3, 33.3, 33.3, 36.4, 42.4", \ + "39.4, 39.4, 39.4, 42.5, 48.5", \ + "51.7, 51.7, 51.7, 54.7, 60.8", \ + "76.6, 76.6, 76.6, 79.4, 85.4"); + } + cell_fall (inslew_load_5x5__41) { + values ("117.6, 117.6, 117.6, 121.6, 129.0", \ + "124.0, 124.0, 124.0, 128.0, 135.4", \ + "133.4, 133.4, 133.4, 137.4, 144.9", \ + "147.0, 147.0, 147.0, 151.1, 158.7", \ + "167.7, 167.7, 167.7, 171.9, 179.9"); + } + fall_transition (inslew_load_5x5__41) { + values ("30.1, 30.1, 30.1, 33.0, 38.7", \ + "32.9, 32.9, 32.9, 35.9, 41.6", \ + "38.4, 38.4, 38.4, 41.4, 47.2", \ + "49.4, 49.4, 49.4, 52.4, 58.3", \ + "70.9, 70.9, 70.9, 73.9, 79.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("149.4, 149.4, 149.4, 153.2, 160.0", \ + "152.4, 152.4, 152.4, 156.2, 163.2", \ + "157.0, 157.0, 157.0, 160.9, 168.1", \ + "163.2, 163.2, 163.2, 167.2, 174.7", \ + "169.6, 169.6, 169.6, 173.8, 181.5"); + } + rise_transition (inslew_load_5x5__41) { + values ("29.3, 29.3, 29.3, 32.5, 38.4", \ + "31.5, 31.5, 31.5, 34.6, 40.5", \ + "36.0, 36.0, 36.0, 39.1, 45.1", \ + "45.4, 45.4, 45.4, 48.4, 54.5", \ + "63.6, 63.6, 63.6, 66.6, 72.6"); + } + cell_fall (inslew_load_5x5__41) { + values ("119.3, 119.3, 119.3, 123.2, 130.6", \ + "130.8, 130.8, 130.8, 134.8, 142.2", \ + "148.5, 148.5, 148.5, 152.6, 160.1", \ + "176.7, 176.7, 176.7, 180.8, 188.5", \ + "225.7, 225.7, 225.7, 229.9, 237.9"); + } + fall_transition (inslew_load_5x5__41) { + values ("29.5, 29.5, 29.5, 32.4, 38.1", \ + "32.6, 32.6, 32.6, 35.6, 41.3", \ + "38.5, 38.5, 38.5, 41.5, 47.3", \ + "50.1, 50.1, 50.1, 53.1, 59.0", \ + "72.7, 72.7, 72.7, 75.7, 81.6"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("131.4, 131.4, 131.4, 135.2, 142.0", \ + "127.2, 127.2, 127.2, 131.0, 137.8", \ + "117.5, 117.5, 117.5, 121.4, 128.3", \ + "95.6, 95.6, 95.6, 99.5, 106.8", \ + "45.0, 45.0, 45.0, 49.1, 56.6"); + } + rise_transition (inslew_load_5x5__41) { + values ("26.7, 26.7, 26.7, 29.9, 35.7", \ + "28.2, 28.2, 28.2, 31.3, 37.2", \ + "31.1, 31.1, 31.1, 34.2, 40.2", \ + "37.4, 37.4, 37.4, 40.5, 46.5", \ + "49.5, 49.5, 49.5, 52.6, 58.7"); + } + cell_fall (inslew_load_5x5__41) { + values ("125.8, 125.8, 125.8, 129.7, 137.1", \ + "147.4, 147.4, 147.4, 151.4, 158.8", \ + "182.5, 182.5, 182.5, 186.6, 194.1", \ + "243.7, 243.7, 243.7, 247.8, 255.6", \ + "357.7, 357.7, 357.7, 361.9, 369.9"); + } + fall_transition (inslew_load_5x5__41) { + values ("29.5, 29.5, 29.5, 32.5, 38.2", \ + "33.6, 33.6, 33.6, 36.5, 42.3", \ + "41.2, 41.2, 41.2, 44.2, 50.0", \ + "55.8, 55.8, 55.8, 58.8, 64.6", \ + "84.3, 84.3, 84.3, 87.2, 93.1"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("129.0, 129.0, 129.0, 132.8, 139.6", \ + "145.9, 145.9, 145.9, 149.7, 156.5", \ + "175.6, 175.6, 175.6, 179.4, 186.6", \ + "224.0, 224.0, 224.0, 228.0, 235.5", \ + "311.9, 311.9, 311.9, 316.1, 323.9"); + } + rise_transition (inslew_load_5x5__41) { + values ("25.0, 25.0, 25.0, 28.1, 33.9", \ + "28.1, 28.1, 28.1, 31.3, 37.1", \ + "34.5, 34.5, 34.5, 37.6, 43.6", \ + "46.7, 46.7, 46.7, 49.7, 55.8", \ + "70.7, 70.7, 70.7, 73.6, 79.6"); + } + cell_fall (inslew_load_5x5__41) { + values ("106.3, 106.3, 106.3, 110.3, 117.5", \ + "109.4, 109.4, 109.4, 113.3, 120.6", \ + "109.3, 109.3, 109.3, 113.3, 120.7", \ + "100.2, 100.2, 100.2, 104.3, 111.8", \ + "71.2, 71.2, 71.2, 75.3, 83.0"); + } + fall_transition (inslew_load_5x5__41) { + values ("26.3, 26.3, 26.3, 29.3, 34.9", \ + "28.2, 28.2, 28.2, 31.1, 36.8", \ + "31.7, 31.7, 31.7, 34.7, 40.4", \ + "38.6, 38.6, 38.6, 41.6, 47.3", \ + "51.7, 51.7, 51.7, 54.7, 60.5"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("136.3, 136.3, 136.3, 140.2, 146.9", \ + "149.1, 149.1, 149.1, 152.9, 159.7", \ + "170.1, 170.1, 170.1, 174.0, 181.1", \ + "205.7, 205.7, 205.7, 209.7, 217.2", \ + "268.3, 268.3, 268.3, 272.5, 280.3"); + } + rise_transition (inslew_load_5x5__41) { + values ("26.4, 26.4, 26.4, 29.6, 35.4", \ + "29.3, 29.3, 29.3, 32.4, 38.3", \ + "35.0, 35.0, 35.0, 38.1, 44.1", \ + "46.4, 46.4, 46.4, 49.5, 55.6", \ + "68.9, 68.9, 68.9, 71.8, 77.9"); + } + cell_fall (inslew_load_5x5__41) { + values ("112.3, 112.3, 112.3, 116.2, 123.5", \ + "117.9, 117.9, 117.9, 121.9, 129.2", \ + "123.6, 123.6, 123.6, 127.6, 135.0", \ + "126.6, 126.6, 126.6, 130.7, 138.2", \ + "122.9, 122.9, 122.9, 127.1, 134.9"); + } + fall_transition (inslew_load_5x5__41) { + values ("27.2, 27.2, 27.2, 30.1, 35.8", \ + "29.3, 29.3, 29.3, 32.3, 38.0", \ + "33.6, 33.6, 33.6, 36.5, 42.3", \ + "41.6, 41.6, 41.6, 44.6, 50.4", \ + "57.2, 57.2, 57.2, 60.2, 66.0"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("140.8, 140.8, 140.8, 144.7, 151.5", \ + "148.2, 148.2, 148.2, 152.0, 158.9", \ + "160.4, 160.4, 160.4, 164.3, 171.4", \ + "179.9, 179.9, 179.9, 183.9, 191.4", \ + "212.3, 212.3, 212.3, 216.5, 224.3"); + } + rise_transition (inslew_load_5x5__41) { + values ("27.6, 27.6, 27.6, 30.8, 36.6", \ + "30.2, 30.2, 30.2, 33.3, 39.2", \ + "35.4, 35.4, 35.4, 38.4, 44.4", \ + "45.6, 45.6, 45.6, 48.7, 54.8", \ + "66.2, 66.2, 66.2, 69.1, 75.2"); + } + cell_fall (inslew_load_5x5__41) { + values ("117.9, 117.9, 117.9, 121.9, 129.2", \ + "127.5, 127.5, 127.5, 131.5, 138.9", \ + "141.5, 141.5, 141.5, 145.6, 153.0", \ + "162.1, 162.1, 162.1, 166.2, 173.8", \ + "195.2, 195.2, 195.2, 199.3, 207.2"); + } + fall_transition (inslew_load_5x5__41) { + values ("28.0, 28.0, 28.0, 31.0, 36.7", \ + "30.7, 30.7, 30.7, 33.7, 39.4", \ + "35.8, 35.8, 35.8, 38.8, 44.6", \ + "45.8, 45.8, 45.8, 48.8, 54.7", \ + "65.3, 65.3, 65.3, 68.3, 74.2"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("95.8, 95.8, 95.8, 99.4, 105.9", \ + "102.7, 102.7, 102.7, 106.4, 113.0", \ + "107.1, 107.1, 107.1, 110.9, 117.6", \ + "105.2, 105.2, 105.2, 109.0, 115.9", \ + "89.9, 89.9, 89.9, 93.9, 101.3"); + } + rise_transition (inslew_load_5x5__41) { + values ("19.0, 19.0, 19.0, 22.0, 27.7", \ + "21.0, 21.0, 21.0, 24.0, 29.7", \ + "24.5, 24.5, 24.5, 27.6, 33.4", \ + "31.0, 31.0, 31.0, 34.1, 40.0", \ + "43.7, 43.7, 43.7, 46.7, 52.8"); + } + cell_fall (inslew_load_5x5__41) { + values ("112.4, 112.4, 112.4, 116.3, 123.5", \ + "128.2, 128.2, 128.2, 132.2, 139.5", \ + "151.6, 151.6, 151.6, 155.7, 163.1", \ + "188.8, 188.8, 188.8, 192.9, 200.5", \ + "254.1, 254.1, 254.1, 258.2, 266.2"); + } + fall_transition (inslew_load_5x5__41) { + values ("26.2, 26.2, 26.2, 29.1, 34.8", \ + "29.3, 29.3, 29.3, 32.3, 38.0", \ + "35.1, 35.1, 35.1, 38.1, 43.9", \ + "46.0, 46.0, 46.0, 49.0, 54.9", \ + "67.2, 67.2, 67.2, 70.2, 76.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__41) { + values ("2428.7, 2428.7, 2428.7, 2541.5, 2767.1", \ + "2682.5, 2682.5, 2682.5, 2795.3, 3020.9", \ + "3194.5, 3194.5, 3194.5, 3307.3, 3532.9", \ + "4230.9, 4230.9, 4230.9, 4343.7, 4569.4", \ + "6310.8, 6310.8, 6310.8, 6423.7, 6649.3"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("2157.8, 2157.8, 2157.8, 2270.6, 2496.3", \ + "2393.8, 2393.8, 2393.8, 2506.6, 2732.3", \ + "2864.8, 2864.8, 2864.8, 2977.7, 3203.3", \ + "3805.9, 3805.9, 3805.9, 3918.7, 4144.3", \ + "5677.7, 5677.7, 5677.7, 5790.5, 6016.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__41) { + values ("2335.1, 2335.1, 2335.1, 2447.9, 2673.6", \ + "2517.1, 2517.1, 2517.1, 2629.9, 2855.6", \ + "2890.8, 2890.8, 2890.8, 3003.6, 3229.2", \ + "3651.9, 3651.9, 3651.9, 3764.8, 3990.4", \ + "5156.1, 5156.1, 5156.1, 5268.9, 5494.5"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("2097.6, 2097.6, 2097.6, 2210.4, 2436.1", \ + "2342.9, 2342.9, 2342.9, 2455.7, 2681.4", \ + "2824.9, 2824.9, 2824.9, 2937.7, 3163.3", \ + "3783.7, 3783.7, 3783.7, 3896.5, 4122.1", \ + "5687.2, 5687.2, 5687.2, 5800.0, 6025.7"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__41) { + values ("2155.1, 2155.1, 2155.1, 2267.9, 2493.5", \ + "2276.0, 2276.0, 2276.0, 2388.8, 2614.5", \ + "2524.6, 2524.6, 2524.6, 2637.4, 2863.0", \ + "3038.0, 3038.0, 3038.0, 3150.8, 3376.4", \ + "4046.3, 4046.3, 4046.3, 4159.2, 4384.8"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("2086.8, 2086.8, 2086.8, 2199.6, 2425.2", \ + "2393.7, 2393.7, 2393.7, 2506.5, 2732.1", \ + "2994.2, 2994.2, 2994.2, 3107.0, 3332.6", \ + "4178.1, 4178.1, 4178.1, 4291.0, 4516.6", \ + "6527.9, 6527.9, 6527.9, 6640.7, 6866.3"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__41) { + values ("1958.7, 1958.7, 1958.7, 2071.5, 2297.2", \ + "2197.2, 2197.2, 2197.2, 2310.0, 2535.6", \ + "2682.4, 2682.4, 2682.4, 2795.2, 3020.8", \ + "3622.4, 3622.4, 3622.4, 3735.2, 3960.9", \ + "5487.9, 5487.9, 5487.9, 5600.8, 5826.4"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("1844.9, 1844.9, 1844.9, 1957.7, 2183.3", \ + "1976.5, 1976.5, 1976.5, 2089.3, 2314.9", \ + "2237.6, 2237.6, 2237.6, 2350.4, 2576.0", \ + "2751.1, 2751.1, 2751.1, 2863.9, 3089.5", \ + "3763.6, 3763.6, 3763.6, 3876.4, 4102.0"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__41) { + values ("2080.8, 2080.8, 2080.8, 2193.6, 2419.2", \ + "2305.6, 2305.6, 2305.6, 2418.4, 2644.1", \ + "2754.8, 2754.8, 2754.8, 2867.6, 3093.2", \ + "3654.6, 3654.6, 3654.6, 3767.4, 3993.0", \ + "5438.8, 5438.8, 5438.8, 5551.7, 5777.3"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("1931.9, 1931.9, 1931.9, 2044.7, 2270.3", \ + "2093.4, 2093.4, 2093.4, 2206.2, 2431.9", \ + "2416.5, 2416.5, 2416.5, 2529.3, 2754.9", \ + "3051.6, 3051.6, 3051.6, 3164.4, 3390.0", \ + "4310.2, 4310.2, 4310.2, 4423.0, 4648.6"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__41) { + values ("2186.2, 2186.2, 2186.2, 2299.0, 2524.7", \ + "2389.8, 2389.8, 2389.8, 2502.7, 2728.3", \ + "2808.2, 2808.2, 2808.2, 2921.0, 3146.6", \ + "3639.9, 3639.9, 3639.9, 3752.7, 3978.3", \ + "5304.2, 5304.2, 5304.2, 5417.0, 5642.7"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("2017.5, 2017.5, 2017.5, 2130.3, 2356.0", \ + "2229.6, 2229.6, 2229.6, 2342.4, 2568.0", \ + "2649.2, 2649.2, 2649.2, 2762.0, 2987.6", \ + "3482.3, 3482.3, 3482.3, 3595.1, 3820.7", \ + "5136.2, 5136.2, 5136.2, 5249.0, 5474.7"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__41) { + values ("1622.8, 1622.8, 1622.8, 1735.6, 1961.2", \ + "1773.1, 1773.1, 1773.1, 1886.0, 2111.6", \ + "2058.5, 2058.5, 2058.5, 2171.3, 2396.9", \ + "2610.4, 2610.4, 2610.4, 2723.2, 2948.8", \ + "3694.6, 3694.6, 3694.6, 3807.5, 4033.1"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("1827.2, 1827.2, 1827.2, 1940.0, 2165.6", \ + "2052.2, 2052.2, 2052.2, 2165.0, 2390.6", \ + "2489.1, 2489.1, 2489.1, 2601.9, 2827.5", \ + "3344.3, 3344.3, 3344.3, 3457.1, 3682.7", \ + "5038.7, 5038.7, 5038.7, 5151.5, 5377.1"); + } + } + } + } + + cell (nxr2_x1) { + area : 0.0 ; + cell_leakage_power : 0.0078 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.0091 ; + } + leakage_power () { + when : "(i0 ^ i1)" ; + value : 0.002 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.012 ; + } + pin (i1) { + direction : input ; + capacitance : 41.91 ; + } + pin (i0) { + direction : input ; + capacitance : 37.63 ; + } + pin (nq) { + function : "!((i1 ^ i0))" ; + direction : output ; + capacitance : 8.89 ; + timing (maxd_nq_i0_positive_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__42) { + values ("66.3, 66.3, 66.3, 75.8, 91.8", \ + "77.4, 77.4, 77.4, 87.6, 104.8", \ + "93.4, 93.4, 93.4, 104.3, 123.3", \ + "118.9, 118.9, 118.9, 130.7, 151.7", \ + "166.1, 166.1, 166.1, 178.7, 201.7"); + } + rise_transition (inslew_load_5x5__42) { + values ("31.1, 31.1, 31.1, 41.8, 62.4", \ + "38.4, 38.4, 38.4, 49.4, 70.3", \ + "52.5, 52.5, 52.5, 63.8, 85.3", \ + "79.9, 79.9, 79.9, 91.4, 113.5", \ + "134.1, 134.1, 134.1, 145.9, 168.7"); + } + cell_fall (inslew_load_5x5__42) { + values ("53.6, 53.6, 53.6, 63.6, 81.0", \ + "57.4, 57.4, 57.4, 67.8, 86.0", \ + "57.6, 57.6, 57.6, 68.5, 87.8", \ + "49.5, 49.5, 49.5, 60.9, 81.6", \ + "25.0, 25.0, 25.0, 37.0, 59.1"); + } + fall_transition (inslew_load_5x5__42) { + values ("30.6, 30.6, 30.6, 40.6, 60.0", \ + "36.4, 36.4, 36.4, 46.5, 66.1", \ + "47.0, 47.0, 47.0, 57.3, 77.1", \ + "66.9, 66.9, 66.9, 77.3, 97.4", \ + "105.1, 105.1, 105.1, 115.6, 136.2"); + } + } + timing (maxd_nq_i1_positive_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__42) { + values ("66.2, 66.2, 66.2, 73.2, 86.1", \ + "75.5, 75.5, 75.5, 82.9, 96.5", \ + "87.7, 87.7, 87.7, 95.8, 110.6", \ + "105.6, 105.6, 105.6, 114.5, 130.9", \ + "137.4, 137.4, 137.4, 147.1, 165.2"); + } + rise_transition (inslew_load_5x5__42) { + values ("35.9, 35.9, 35.9, 45.5, 64.3", \ + "41.4, 41.4, 41.4, 51.1, 70.0", \ + "52.0, 52.0, 52.0, 61.8, 81.1", \ + "72.5, 72.5, 72.5, 82.5, 102.2", \ + "113.1, 113.1, 113.1, 123.4, 143.6"); + } + cell_fall (inslew_load_5x5__42) { + values ("65.0, 65.0, 65.0, 73.8, 89.9", \ + "70.7, 70.7, 70.7, 79.8, 96.4", \ + "74.3, 74.3, 74.3, 83.8, 101.2", \ + "72.7, 72.7, 72.7, 82.6, 101.1", \ + "60.7, 60.7, 60.7, 71.1, 90.8"); + } + fall_transition (inslew_load_5x5__42) { + values ("42.5, 42.5, 42.5, 52.3, 71.5", \ + "50.2, 50.2, 50.2, 59.9, 79.2", \ + "63.9, 63.9, 63.9, 73.7, 93.1", \ + "89.5, 89.5, 89.5, 99.5, 119.1", \ + "139.0, 139.0, 139.0, 149.1, 169.0"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__42) { + values ("16.1, 16.1, 16.1, 22.6, 34.8", \ + "13.8, 13.8, 13.8, 21.2, 34.8", \ + "7.6, 7.6, 7.6, 15.8, 31.1", \ + "-6.0, -6.0, -6.0, 2.7, 19.6", \ + "-34.4, -34.4, -34.4, -25.1, -7.1"); + } + rise_transition (inslew_load_5x5__42) { + values ("37.8, 37.8, 37.8, 47.3, 66.2", \ + "54.0, 54.0, 54.0, 63.6, 82.4", \ + "85.8, 85.8, 85.8, 95.6, 114.9", \ + "149.1, 149.1, 149.1, 159.0, 178.7", \ + "275.4, 275.4, 275.4, 285.5, 305.5"); + } + cell_fall (inslew_load_5x5__42) { + values ("28.0, 28.0, 28.0, 35.8, 50.6", \ + "36.2, 36.2, 36.2, 44.5, 60.3", \ + "50.9, 50.9, 50.9, 59.8, 76.7", \ + "79.5, 79.5, 79.5, 88.7, 106.6", \ + "136.2, 136.2, 136.2, 145.6, 164.1"); + } + fall_transition (inslew_load_5x5__42) { + values ("44.7, 44.7, 44.7, 54.2, 73.2", \ + "70.0, 70.0, 70.0, 79.5, 98.4", \ + "119.8, 119.8, 119.8, 129.3, 148.3", \ + "218.9, 218.9, 218.9, 228.5, 247.6", \ + "416.6, 416.6, 416.6, 426.3, 445.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__42) { + values ("15.5, 15.5, 15.5, 23.9, 38.4", \ + "18.7, 18.7, 18.7, 28.3, 45.2", \ + "23.8, 23.8, 23.8, 34.2, 53.4", \ + "33.0, 33.0, 33.0, 44.1, 65.0", \ + "51.1, 51.1, 51.1, 62.4, 84.5"); + } + rise_transition (inslew_load_5x5__42) { + values ("31.7, 31.7, 31.7, 42.2, 62.3", \ + "52.3, 52.3, 52.3, 63.0, 83.9", \ + "92.5, 92.5, 92.5, 103.6, 125.2", \ + "172.5, 172.5, 172.5, 183.7, 205.9", \ + "332.0, 332.0, 332.0, 343.4, 366.0"); + } + cell_fall (inslew_load_5x5__42) { + values ("16.6, 16.6, 16.6, 25.2, 40.7", \ + "17.7, 17.7, 17.7, 27.1, 44.2", \ + "18.7, 18.7, 18.7, 28.8, 47.6", \ + "19.8, 19.8, 19.8, 30.4, 50.6", \ + "21.5, 21.5, 21.5, 32.4, 53.6"); + } + fall_transition (inslew_load_5x5__42) { + values ("31.9, 31.9, 31.9, 41.5, 60.5", \ + "50.5, 50.5, 50.5, 60.2, 79.3", \ + "87.0, 87.0, 87.0, 96.9, 116.2", \ + "159.6, 159.6, 159.6, 169.6, 189.3", \ + "304.5, 304.5, 304.5, 314.6, 334.6"); + } + } + internal_power (energy_pos_nq_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__42) { + values ("792.7, 792.7, 792.7, 903.8, 1126.0", \ + "952.4, 952.4, 952.4, 1063.5, 1285.7", \ + "1269.4, 1269.4, 1269.4, 1380.5, 1602.7", \ + "1899.9, 1899.9, 1899.9, 2011.0, 2233.2", \ + "3159.7, 3159.7, 3159.7, 3270.8, 3493.1"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("776.3, 776.3, 776.3, 887.4, 1109.7", \ + "879.2, 879.2, 879.2, 990.3, 1212.5", \ + "1079.5, 1079.5, 1079.5, 1190.6, 1412.8", \ + "1473.0, 1473.0, 1473.0, 1584.1, 1806.3", \ + "2253.3, 2253.3, 2253.3, 2364.4, 2586.6"); + } + } + internal_power (energy_pos_nq_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__42) { + values ("880.4, 880.4, 880.4, 991.5, 1213.7", \ + "1034.1, 1034.1, 1034.1, 1145.2, 1367.4", \ + "1339.4, 1339.4, 1339.4, 1450.5, 1672.7", \ + "1947.1, 1947.1, 1947.1, 2058.2, 2280.4", \ + "3161.9, 3161.9, 3161.9, 3273.0, 3495.2"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("911.4, 911.4, 911.4, 1022.5, 1244.7", \ + "1031.2, 1031.2, 1031.2, 1142.3, 1364.5", \ + "1262.4, 1262.4, 1262.4, 1373.5, 1595.7", \ + "1715.2, 1715.2, 1715.2, 1826.3, 2048.5", \ + "2612.0, 2612.0, 2612.0, 2723.1, 2945.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__42) { + values ("378.8, 378.8, 378.8, 489.9, 712.1", \ + "503.5, 503.5, 503.5, 614.6, 836.8", \ + "752.9, 752.9, 752.9, 864.0, 1086.3", \ + "1251.8, 1251.8, 1251.8, 1363.0, 1585.2", \ + "2249.7, 2249.7, 2249.7, 2360.8, 2583.0"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("465.4, 465.4, 465.4, 576.5, 798.7", \ + "685.4, 685.4, 685.4, 796.5, 1018.7", \ + "1125.5, 1125.5, 1125.5, 1236.6, 1458.8", \ + "2005.7, 2005.7, 2005.7, 2116.8, 2339.0", \ + "3766.0, 3766.0, 3766.0, 3877.1, 4099.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__42) { + values ("273.3, 273.3, 273.3, 384.4, 606.7", \ + "411.5, 411.5, 411.5, 522.6, 744.8", \ + "687.9, 687.9, 687.9, 799.0, 1021.2", \ + "1240.7, 1240.7, 1240.7, 1351.8, 1574.0", \ + "2346.2, 2346.2, 2346.2, 2457.3, 2679.5"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("305.2, 305.2, 305.2, 416.3, 638.6", \ + "451.1, 451.1, 451.1, 562.2, 784.5", \ + "742.9, 742.9, 742.9, 854.0, 1076.3", \ + "1326.5, 1326.5, 1326.5, 1437.6, 1659.9", \ + "2493.7, 2493.7, 2493.7, 2604.8, 2827.1"); + } + } + } + } + + cell (nxr2_x4) { + area : 0.0 ; + cell_leakage_power : 0.012 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.012 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.011 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 0.01 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.015 ; + } + pin (i1) { + direction : input ; + capacitance : 37.12 ; + } + pin (i0) { + direction : input ; + capacitance : 34.81 ; + } + pin (nq) { + function : "!((i1 ^ i0))" ; + direction : output ; + capacitance : 8.91 ; + timing (maxd_nq_i0_positive_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("67.5, 67.5, 67.5, 71.4, 78.4", \ + "76.4, 76.4, 76.4, 80.5, 87.7", \ + "90.6, 90.6, 90.6, 94.8, 102.4", \ + "114.2, 114.2, 114.2, 118.6, 126.8", \ + "159.4, 159.4, 159.4, 163.6, 172.0"); + } + rise_transition (inslew_load_5x5__3) { + values ("27.1, 27.1, 27.1, 30.2, 36.1", \ + "33.3, 33.3, 33.3, 36.4, 42.4", \ + "45.6, 45.6, 45.6, 48.7, 54.8", \ + "70.3, 70.3, 70.3, 73.3, 79.4", \ + "119.5, 119.5, 119.5, 122.9, 129.1"); + } + cell_fall (inslew_load_5x5__3) { + values ("69.0, 69.0, 69.0, 73.2, 80.9", \ + "72.5, 72.5, 72.5, 76.7, 84.5", \ + "75.2, 75.2, 75.2, 79.4, 87.4", \ + "74.4, 74.4, 74.4, 78.7, 86.9", \ + "65.8, 65.8, 65.8, 70.1, 78.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("40.5, 40.5, 40.5, 43.6, 49.6", \ + "47.4, 47.4, 47.4, 50.5, 56.6", \ + "60.9, 60.9, 60.9, 64.0, 70.1", \ + "87.7, 87.7, 87.7, 90.8, 97.0", \ + "140.5, 140.5, 140.5, 143.6, 149.8"); + } + } + timing (maxd_nq_i1_positive_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("73.2, 73.2, 73.2, 77.0, 84.0", \ + "88.4, 88.4, 88.4, 92.5, 99.7", \ + "112.1, 112.1, 112.1, 116.3, 123.9", \ + "152.3, 152.3, 152.3, 156.7, 164.9", \ + "228.8, 228.8, 228.8, 233.1, 241.5"); + } + rise_transition (inslew_load_5x5__3) { + values ("26.6, 26.6, 26.6, 29.6, 35.5", \ + "33.4, 33.4, 33.4, 36.5, 42.5", \ + "46.9, 46.9, 46.9, 49.9, 56.0", \ + "73.2, 73.2, 73.2, 76.3, 82.4", \ + "125.5, 125.5, 125.5, 128.9, 135.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("65.3, 65.3, 65.3, 69.4, 77.1", \ + "66.0, 66.0, 66.0, 70.1, 77.9", \ + "62.3, 62.3, 62.3, 66.6, 74.5", \ + "47.2, 47.2, 47.2, 51.5, 59.6", \ + "7.5, 7.5, 7.5, 11.8, 20.2"); + } + fall_transition (inslew_load_5x5__3) { + values ("38.4, 38.4, 38.4, 41.5, 47.5", \ + "43.8, 43.8, 43.8, 46.9, 53.0", \ + "54.7, 54.7, 54.7, 57.8, 63.9", \ + "75.7, 75.7, 75.7, 78.8, 85.0", \ + "116.7, 116.7, 116.7, 119.8, 126.0"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("102.3, 102.3, 102.3, 106.1, 112.9", \ + "107.8, 107.8, 107.8, 111.6, 118.6", \ + "110.4, 110.4, 110.4, 114.2, 121.3", \ + "104.7, 104.7, 104.7, 108.7, 116.0", \ + "81.8, 81.8, 81.8, 86.0, 93.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("24.0, 24.0, 24.0, 27.2, 33.0", \ + "25.6, 25.6, 25.6, 28.6, 34.5", \ + "28.3, 28.3, 28.3, 31.4, 37.4", \ + "33.4, 33.4, 33.4, 36.5, 42.5", \ + "43.3, 43.3, 43.3, 46.3, 52.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("131.0, 131.0, 131.0, 135.1, 142.8", \ + "146.7, 146.7, 146.7, 150.8, 158.6", \ + "169.6, 169.6, 169.6, 173.8, 181.6", \ + "205.0, 205.0, 205.0, 209.2, 217.2", \ + "265.5, 265.5, 265.5, 269.8, 278.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("40.0, 40.0, 40.0, 43.1, 49.1", \ + "43.4, 43.4, 43.4, 46.5, 52.6", \ + "49.9, 49.9, 49.9, 53.1, 59.1", \ + "62.1, 62.1, 62.1, 65.2, 71.4", \ + "85.5, 85.5, 85.5, 88.6, 94.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("94.4, 94.4, 94.4, 98.2, 105.1", \ + "98.0, 98.0, 98.0, 101.9, 108.8", \ + "97.4, 97.4, 97.4, 101.3, 108.4", \ + "87.1, 87.1, 87.1, 91.0, 98.3", \ + "56.2, 56.2, 56.2, 60.4, 67.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("24.1, 24.1, 24.1, 27.2, 33.1", \ + "25.4, 25.4, 25.4, 28.5, 34.4", \ + "27.7, 27.7, 27.7, 30.8, 36.7", \ + "32.1, 32.1, 32.1, 35.1, 41.1", \ + "40.6, 40.6, 40.6, 43.7, 49.7"); + } + cell_fall (inslew_load_5x5__3) { + values ("133.3, 133.3, 133.3, 137.5, 145.2", \ + "150.5, 150.5, 150.5, 154.7, 162.5", \ + "176.5, 176.5, 176.5, 180.7, 188.6", \ + "218.2, 218.2, 218.2, 222.5, 230.6", \ + "293.3, 293.3, 293.3, 297.6, 305.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("42.1, 42.1, 42.1, 45.2, 51.2", \ + "46.2, 46.2, 46.2, 49.4, 55.4", \ + "54.1, 54.1, 54.1, 57.2, 63.3", \ + "68.9, 68.9, 68.9, 72.0, 78.1", \ + "97.6, 97.6, 97.6, 100.8, 107.0"); + } + } + internal_power (energy_pos_nq_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1705.8, 1705.8, 1705.8, 1817.2, 2040.0", \ + "2050.5, 2050.5, 2050.5, 2161.9, 2384.7", \ + "2738.6, 2738.6, 2738.6, 2850.0, 3072.8", \ + "4114.7, 4114.7, 4114.7, 4226.1, 4448.9", \ + "6873.8, 6873.8, 6873.8, 6985.2, 7208.0"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1962.8, 1962.8, 1962.8, 2074.2, 2297.0", \ + "2233.6, 2233.6, 2233.6, 2345.0, 2567.8", \ + "2767.4, 2767.4, 2767.4, 2878.8, 3101.6", \ + "3834.0, 3834.0, 3834.0, 3945.4, 4168.2", \ + "5952.3, 5952.3, 5952.3, 6063.7, 6286.5"); + } + } + internal_power (energy_pos_nq_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1635.4, 1635.4, 1635.4, 1746.8, 1969.6", \ + "1982.4, 1982.4, 1982.4, 2093.8, 2316.6", \ + "2671.0, 2671.0, 2671.0, 2782.4, 3005.2", \ + "4036.8, 4036.8, 4036.8, 4148.2, 4371.0", \ + "6767.7, 6767.7, 6767.7, 6879.1, 7101.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1856.7, 1856.7, 1856.7, 1968.1, 2190.9", \ + "2056.0, 2056.0, 2056.0, 2167.4, 2390.2", \ + "2456.4, 2456.4, 2456.4, 2567.8, 2790.6", \ + "3245.0, 3245.0, 3245.0, 3356.3, 3579.1", \ + "4799.1, 4799.1, 4799.1, 4910.5, 5133.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("1979.7, 1979.7, 1979.7, 2091.1, 2313.9", \ + "2113.3, 2113.3, 2113.3, 2224.7, 2447.5", \ + "2369.7, 2369.7, 2369.7, 2481.1, 2703.9", \ + "2866.8, 2866.8, 2866.8, 2978.2, 3201.0", \ + "3844.5, 3844.5, 3844.5, 3955.8, 4178.6"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("2390.7, 2390.7, 2390.7, 2502.1, 2724.9", \ + "2623.5, 2623.5, 2623.5, 2734.9, 2957.7", \ + "3078.0, 3078.0, 3078.0, 3189.4, 3412.2", \ + "3965.5, 3965.5, 3965.5, 4076.8, 4299.6", \ + "5720.2, 5720.2, 5720.2, 5831.6, 6054.4"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("2005.5, 2005.5, 2005.5, 2116.9, 2339.7", \ + "2134.3, 2134.3, 2134.3, 2245.7, 2468.5", \ + "2381.4, 2381.4, 2381.4, 2492.8, 2715.6", \ + "2863.3, 2863.3, 2863.3, 2974.7, 3197.5", \ + "3816.8, 3816.8, 3816.8, 3928.2, 4151.0"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("2483.5, 2483.5, 2483.5, 2594.9, 2817.6", \ + "2748.3, 2748.3, 2748.3, 2859.7, 3082.4", \ + "3263.2, 3263.2, 3263.2, 3374.5, 3597.3", \ + "4270.0, 4270.0, 4270.0, 4381.4, 4604.2", \ + "6267.4, 6267.4, 6267.4, 6378.8, 6601.6"); + } + } + } + } + + cell (o2_x2) { + area : 0.0 ; + cell_leakage_power : 0.0042 ; + leakage_power () { + when : "(i0 | i1)" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.0039 ; + } + pin (i1) { + direction : input ; + capacitance : 25.83 ; + } + pin (i0) { + direction : input ; + capacitance : 20.81 ; + } + pin (q) { + function : "(i0 | i1)" ; + direction : output ; + capacitance : 5.48 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("56.0, 56.0, 56.0, 60.4, 67.9", \ + "70.0, 70.0, 70.0, 74.6, 82.7", \ + "93.0, 93.0, 93.0, 97.8, 106.6", \ + "134.4, 134.4, 134.4, 139.6, 149.1", \ + "216.9, 216.9, 216.9, 222.1, 232.4"); + } + rise_transition (inslew_load_5x5__43) { + values ("18.3, 18.3, 18.3, 21.9, 28.9", \ + "24.8, 24.8, 24.8, 28.5, 35.6", \ + "37.3, 37.3, 37.3, 41.1, 48.4", \ + "62.1, 62.1, 62.1, 65.8, 73.2", \ + "111.5, 111.5, 111.5, 115.7, 123.1"); + } + cell_fall (inslew_load_5x5__43) { + values ("43.5, 43.5, 43.5, 48.4, 57.1", \ + "41.5, 41.5, 41.5, 46.4, 55.4", \ + "32.7, 32.7, 32.7, 37.7, 47.0", \ + "9.1, 9.1, 9.1, 14.2, 23.8", \ + "-45.0, -45.0, -45.0, -39.8, -29.7"); + } + fall_transition (inslew_load_5x5__43) { + values ("26.7, 26.7, 26.7, 30.5, 37.6", \ + "31.7, 31.7, 31.7, 35.5, 42.7", \ + "41.5, 41.5, 41.5, 45.3, 52.6", \ + "60.2, 60.2, 60.2, 64.1, 71.5", \ + "96.8, 96.8, 96.8, 100.6, 108.2"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("49.6, 49.6, 49.6, 53.9, 61.1", \ + "58.1, 58.1, 58.1, 62.6, 70.5", \ + "69.7, 69.7, 69.7, 74.4, 82.9", \ + "87.4, 87.4, 87.4, 92.6, 101.8", \ + "119.2, 119.2, 119.2, 124.5, 134.6"); + } + rise_transition (inslew_load_5x5__43) { + values ("16.6, 16.6, 16.6, 20.1, 27.0", \ + "21.8, 21.8, 21.8, 25.5, 32.5", \ + "32.0, 32.0, 32.0, 35.8, 43.0", \ + "51.9, 51.9, 51.9, 55.7, 63.1", \ + "91.3, 91.3, 91.3, 95.1, 102.6"); + } + cell_fall (inslew_load_5x5__43) { + values ("50.4, 50.4, 50.4, 55.3, 64.0", \ + "54.9, 54.9, 54.9, 59.9, 68.9", \ + "57.2, 57.2, 57.2, 62.2, 71.6", \ + "54.2, 54.2, 54.2, 59.4, 69.1", \ + "41.8, 41.8, 41.8, 47.1, 57.2"); + } + fall_transition (inslew_load_5x5__43) { + values ("27.0, 27.0, 27.0, 30.8, 37.9", \ + "34.0, 34.0, 34.0, 37.8, 45.0", \ + "46.8, 46.8, 46.8, 50.6, 58.0", \ + "71.4, 71.4, 71.4, 75.2, 82.7", \ + "119.4, 119.4, 119.4, 123.2, 130.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__43) { + values ("777.7, 777.7, 777.7, 846.2, 983.2", \ + "999.7, 999.7, 999.7, 1068.2, 1205.2", \ + "1440.0, 1440.0, 1440.0, 1508.5, 1645.5", \ + "2317.0, 2317.0, 2317.0, 2385.5, 2522.5", \ + "4073.4, 4073.4, 4073.4, 4141.9, 4278.9"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("809.0, 809.0, 809.0, 877.5, 1014.5", \ + "918.0, 918.0, 918.0, 986.5, 1123.5", \ + "1134.2, 1134.2, 1134.2, 1202.7, 1339.7", \ + "1560.1, 1560.1, 1560.1, 1628.6, 1765.6", \ + "2403.6, 2403.6, 2403.6, 2472.1, 2609.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__43) { + values ("675.7, 675.7, 675.7, 744.2, 881.2", \ + "840.3, 840.3, 840.3, 908.8, 1045.8", \ + "1165.5, 1165.5, 1165.5, 1234.0, 1371.0", \ + "1811.3, 1811.3, 1811.3, 1879.8, 2016.8", \ + "3099.0, 3099.0, 3099.0, 3167.5, 3304.5"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("769.1, 769.1, 769.1, 837.6, 974.6", \ + "908.7, 908.7, 908.7, 977.2, 1114.2", \ + "1177.3, 1177.3, 1177.3, 1245.8, 1382.8", \ + "1704.4, 1704.4, 1704.4, 1772.9, 1909.9", \ + "2748.6, 2748.6, 2748.6, 2817.1, 2954.1"); + } + } + } + } + + cell (o2_x4) { + area : 0.0 ; + cell_leakage_power : 0.0092 ; + leakage_power () { + when : "(i0 | i1)" ; + value : 0.012 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.0069 ; + } + pin (i1) { + direction : input ; + capacitance : 24.39 ; + } + pin (i0) { + direction : input ; + capacitance : 23.45 ; + } + pin (q) { + function : "(i0 | i1)" ; + direction : output ; + capacitance : 8.97 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("42.7, 42.7, 42.7, 46.4, 52.5", \ + "47.9, 47.9, 47.9, 51.7, 58.3", \ + "52.7, 52.7, 52.7, 56.6, 63.6", \ + "56.7, 56.7, 56.7, 61.0, 68.6", \ + "60.6, 60.6, 60.6, 65.0, 73.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("14.8, 14.8, 14.8, 17.7, 23.4", \ + "19.4, 19.4, 19.4, 22.5, 28.3", \ + "28.4, 28.4, 28.4, 31.5, 37.4", \ + "45.9, 45.9, 45.9, 48.9, 55.0", \ + "80.4, 80.4, 80.4, 83.6, 89.5"); + } + cell_fall (inslew_load_5x5__21) { + values ("70.7, 70.7, 70.7, 74.8, 82.6", \ + "77.7, 77.7, 77.7, 81.9, 89.8", \ + "88.5, 88.5, 88.5, 92.7, 100.9", \ + "105.4, 105.4, 105.4, 109.7, 118.1", \ + "135.0, 135.0, 135.0, 139.3, 147.9"); + } + fall_transition (inslew_load_5x5__21) { + values ("41.5, 41.5, 41.5, 44.6, 50.6", \ + "50.3, 50.3, 50.3, 53.5, 59.6", \ + "67.6, 67.6, 67.6, 70.8, 76.9", \ + "102.4, 102.4, 102.4, 105.5, 111.7", \ + "171.3, 171.3, 171.3, 174.4, 180.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("69.9, 69.9, 69.9, 73.6, 80.4", \ + "81.3, 81.3, 81.3, 85.2, 92.2", \ + "96.3, 96.3, 96.3, 100.4, 107.8", \ + "117.5, 117.5, 117.5, 121.8, 129.8", \ + "152.2, 152.2, 152.2, 156.5, 165.0"); + } + rise_transition (inslew_load_5x5__21) { + values ("22.1, 22.1, 22.1, 25.2, 31.0", \ + "27.4, 27.4, 27.4, 30.6, 36.5", \ + "38.0, 38.0, 38.0, 41.0, 47.1", \ + "58.5, 58.5, 58.5, 61.5, 67.5", \ + "98.4, 98.4, 98.4, 101.8, 107.8"); + } + cell_fall (inslew_load_5x5__21) { + values ("73.5, 73.5, 73.5, 77.6, 85.4", \ + "81.7, 81.7, 81.7, 85.9, 93.7", \ + "88.7, 88.7, 88.7, 93.0, 101.0", \ + "90.8, 90.8, 90.8, 95.1, 103.4", \ + "82.8, 82.8, 82.8, 87.1, 95.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("39.3, 39.3, 39.3, 42.4, 48.4", \ + "46.6, 46.6, 46.6, 49.7, 55.8", \ + "60.1, 60.1, 60.1, 63.2, 69.3", \ + "85.4, 85.4, 85.4, 88.5, 94.7", \ + "134.3, 134.3, 134.3, 137.5, 143.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1175.7, 1175.7, 1175.7, 1287.7, 1511.9", \ + "1444.4, 1444.4, 1444.4, 1556.5, 1780.7", \ + "1973.9, 1973.9, 1973.9, 2086.0, 2310.2", \ + "3024.0, 3024.0, 3024.0, 3136.1, 3360.3", \ + "5115.7, 5115.7, 5115.7, 5227.7, 5451.9"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1772.2, 1772.2, 1772.2, 1884.3, 2108.5", \ + "2096.4, 2096.4, 2096.4, 2208.5, 2432.6", \ + "2736.8, 2736.8, 2736.8, 2848.9, 3073.1", \ + "4020.4, 4020.4, 4020.4, 4132.5, 4356.6", \ + "6579.6, 6579.6, 6579.6, 6691.6, 6915.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1227.2, 1227.2, 1227.2, 1339.2, 1563.4", \ + "1444.9, 1444.9, 1444.9, 1557.0, 1781.1", \ + "1876.4, 1876.4, 1876.4, 1988.5, 2212.6", \ + "2726.9, 2726.9, 2726.9, 2839.0, 3063.2", \ + "4415.0, 4415.0, 4415.0, 4527.1, 4751.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1602.1, 1602.1, 1602.1, 1714.1, 1938.3", \ + "1822.2, 1822.2, 1822.2, 1934.3, 2158.4", \ + "2238.7, 2238.7, 2238.7, 2350.8, 2574.9", \ + "3039.1, 3039.1, 3039.1, 3151.2, 3375.4", \ + "4604.8, 4604.8, 4604.8, 4716.9, 4941.1"); + } + } + } + } + + cell (o3_x2) { + area : 0.0 ; + cell_leakage_power : 0.0052 ; + leakage_power () { + when : "(i0 | i1 | i2)" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.0059 ; + } + pin (i2) { + direction : input ; + capacitance : 20.24 ; + } + pin (i1) { + direction : input ; + capacitance : 20.24 ; + } + pin (i0) { + direction : input ; + capacitance : 19.89 ; + } + pin (q) { + function : "(i0 | i1 | i2)" ; + direction : output ; + capacitance : 5.51 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__44) { + values ("61.1, 61.1, 61.1, 65.6, 73.3", \ + "75.8, 75.8, 75.8, 80.4, 88.6", \ + "99.2, 99.2, 99.2, 104.1, 113.0", \ + "141.1, 141.1, 141.1, 146.4, 156.0", \ + "223.8, 223.8, 223.8, 229.0, 239.4"); + } + rise_transition (inslew_load_5x5__44) { + values ("19.7, 19.7, 19.7, 23.4, 30.4", \ + "26.1, 26.1, 26.1, 29.9, 37.1", \ + "38.6, 38.6, 38.6, 42.4, 49.8", \ + "63.3, 63.3, 63.3, 67.0, 74.5", \ + "112.4, 112.4, 112.4, 116.6, 124.1"); + } + cell_fall (inslew_load_5x5__44) { + values ("65.7, 65.7, 65.7, 70.7, 80.1", \ + "62.9, 62.9, 62.9, 68.0, 77.5", \ + "55.2, 55.2, 55.2, 60.4, 70.0", \ + "34.7, 34.7, 34.7, 39.9, 49.9", \ + "-12.5, -12.5, -12.5, -7.2, 3.0"); + } + fall_transition (inslew_load_5x5__44) { + values ("42.4, 42.4, 42.4, 46.2, 53.6", \ + "47.7, 47.7, 47.7, 51.5, 59.0", \ + "58.7, 58.7, 58.7, 62.6, 70.0", \ + "80.8, 80.8, 80.8, 84.6, 92.2", \ + "124.4, 124.4, 124.4, 128.2, 135.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__44) { + values ("56.0, 56.0, 56.0, 60.4, 67.9", \ + "65.4, 65.4, 65.4, 69.9, 78.0", \ + "77.9, 77.9, 77.9, 82.7, 91.3", \ + "96.4, 96.4, 96.4, 101.6, 110.9", \ + "128.7, 128.7, 128.7, 134.0, 144.2"); + } + rise_transition (inslew_load_5x5__44) { + values ("18.2, 18.2, 18.2, 21.9, 28.8", \ + "23.5, 23.5, 23.5, 27.3, 34.4", \ + "33.7, 33.7, 33.7, 37.5, 44.8", \ + "53.5, 53.5, 53.5, 57.3, 64.8", \ + "92.7, 92.7, 92.7, 96.6, 104.1"); + } + cell_fall (inslew_load_5x5__44) { + values ("68.3, 68.3, 68.3, 73.3, 82.6", \ + "72.4, 72.4, 72.4, 77.5, 86.9", \ + "76.0, 76.0, 76.0, 81.2, 90.9", \ + "76.5, 76.5, 76.5, 81.7, 91.7", \ + "70.4, 70.4, 70.4, 75.8, 86.1"); + } + fall_transition (inslew_load_5x5__44) { + values ("40.9, 40.9, 40.9, 44.7, 52.0", \ + "47.9, 47.9, 47.9, 51.7, 59.1", \ + "62.0, 62.0, 62.0, 65.9, 73.4", \ + "89.6, 89.6, 89.6, 93.4, 101.0", \ + "143.7, 143.7, 143.7, 147.6, 155.2"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__44) { + values ("50.7, 50.7, 50.7, 55.1, 62.4", \ + "56.5, 56.5, 56.5, 61.1, 68.9", \ + "61.5, 61.5, 61.5, 66.2, 74.6", \ + "64.0, 64.0, 64.0, 69.1, 78.3", \ + "63.3, 63.3, 63.3, 68.7, 78.7"); + } + rise_transition (inslew_load_5x5__44) { + values ("16.8, 16.8, 16.8, 20.4, 27.3", \ + "21.4, 21.4, 21.4, 25.1, 32.1", \ + "30.1, 30.1, 30.1, 33.9, 41.1", \ + "46.9, 46.9, 46.9, 50.6, 58.1", \ + "79.9, 79.9, 79.9, 83.7, 91.2"); + } + cell_fall (inslew_load_5x5__44) { + values ("71.5, 71.5, 71.5, 76.5, 85.8", \ + "83.0, 83.0, 83.0, 88.1, 97.6", \ + "97.1, 97.1, 97.1, 102.3, 112.1", \ + "116.2, 116.2, 116.2, 121.5, 131.6", \ + "146.5, 146.5, 146.5, 151.8, 162.2"); + } + fall_transition (inslew_load_5x5__44) { + values ("39.8, 39.8, 39.8, 43.6, 50.9", \ + "49.2, 49.2, 49.2, 53.0, 60.5", \ + "66.5, 66.5, 66.5, 70.4, 77.9", \ + "99.9, 99.9, 99.9, 103.8, 111.4", \ + "165.4, 165.4, 165.4, 169.3, 177.0"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__44) { + values ("855.5, 855.5, 855.5, 924.3, 1062.0", \ + "1077.5, 1077.5, 1077.5, 1146.3, 1284.0", \ + "1518.0, 1518.0, 1518.0, 1586.8, 1724.5", \ + "2395.3, 2395.3, 2395.3, 2464.2, 2601.8", \ + "4152.2, 4152.2, 4152.2, 4221.0, 4358.7"); + } + fall_power (energy_inslew_load_5x5__44) { + values ("1056.9, 1056.9, 1056.9, 1125.8, 1263.4", \ + "1170.3, 1170.3, 1170.3, 1239.2, 1376.9", \ + "1400.7, 1400.7, 1400.7, 1469.5, 1607.2", \ + "1863.1, 1863.1, 1863.1, 1931.9, 2069.6", \ + "2782.7, 2782.7, 2782.7, 2851.5, 2989.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__44) { + values ("767.9, 767.9, 767.9, 836.7, 974.4", \ + "932.7, 932.7, 932.7, 1001.6, 1139.3", \ + "1258.5, 1258.5, 1258.5, 1327.3, 1465.0", \ + "1905.0, 1905.0, 1905.0, 1973.8, 2111.5", \ + "3193.4, 3193.4, 3193.4, 3262.2, 3399.9"); + } + fall_power (energy_inslew_load_5x5__44) { + values ("1005.8, 1005.8, 1005.8, 1074.6, 1212.3", \ + "1147.1, 1147.1, 1147.1, 1216.0, 1353.7", \ + "1430.7, 1430.7, 1430.7, 1499.6, 1637.3", \ + "1990.9, 1990.9, 1990.9, 2059.7, 2197.4", \ + "3102.4, 3102.4, 3102.4, 3171.2, 3308.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__44) { + values ("687.4, 687.4, 687.4, 756.2, 893.9", \ + "817.8, 817.8, 817.8, 886.6, 1024.3", \ + "1073.6, 1073.6, 1073.6, 1142.4, 1280.1", \ + "1579.2, 1579.2, 1579.2, 1648.1, 1785.7", \ + "2584.8, 2584.8, 2584.8, 2653.6, 2791.3"); + } + fall_power (energy_inslew_load_5x5__44) { + values ("944.0, 944.0, 944.0, 1012.9, 1150.6", \ + "1116.2, 1116.2, 1116.2, 1185.1, 1322.8", \ + "1444.3, 1444.3, 1444.3, 1513.2, 1650.9", \ + "2087.8, 2087.8, 2087.8, 2156.6, 2294.3", \ + "3362.3, 3362.3, 3362.3, 3431.2, 3568.8"); + } + } + } + } + + cell (o3_x4) { + area : 0.0 ; + cell_leakage_power : 0.013 ; + leakage_power () { + when : "(i0 | i1 | i2)" ; + value : 0.012 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.014 ; + } + pin (i2) { + direction : input ; + capacitance : 21.06 ; + } + pin (i1) { + direction : input ; + capacitance : 21.77 ; + } + pin (i0) { + direction : input ; + capacitance : 21.41 ; + } + pin (q) { + function : "(i0 | i1 | i2)" ; + direction : output ; + capacitance : 8.97 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("48.4, 48.4, 48.4, 52.1, 58.4", \ + "54.8, 54.8, 54.8, 58.5, 65.2", \ + "61.2, 61.2, 61.2, 65.1, 72.3", \ + "67.7, 67.7, 67.7, 72.0, 79.7", \ + "75.5, 75.5, 75.5, 79.9, 88.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("16.1, 16.1, 16.1, 19.1, 24.8", \ + "20.8, 20.8, 20.8, 23.9, 29.7", \ + "29.8, 29.8, 29.8, 33.0, 38.9", \ + "47.5, 47.5, 47.5, 50.5, 56.7", \ + "82.2, 82.2, 82.2, 85.4, 91.4"); + } + cell_fall (inslew_load_5x5__21) { + values ("107.5, 107.5, 107.5, 111.8, 119.9", \ + "114.2, 114.2, 114.2, 118.5, 126.7", \ + "126.6, 126.6, 126.6, 130.9, 139.2", \ + "149.4, 149.4, 149.4, 153.7, 162.2", \ + "190.9, 190.9, 190.9, 195.3, 203.9"); + } + fall_transition (inslew_load_5x5__21) { + values ("67.1, 67.1, 67.1, 70.3, 76.4", \ + "77.2, 77.2, 77.2, 80.3, 86.5", \ + "98.0, 98.0, 98.0, 101.2, 107.4", \ + "140.7, 140.7, 140.7, 143.9, 150.1", \ + "224.8, 224.8, 224.8, 227.9, 234.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("44.9, 44.9, 44.9, 48.6, 54.8", \ + "47.2, 47.2, 47.2, 50.9, 57.5", \ + "44.2, 44.2, 44.2, 48.0, 55.0", \ + "29.6, 29.6, 29.6, 33.8, 41.3", \ + "-7.2, -7.2, -7.2, -2.8, 5.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("15.2, 15.2, 15.2, 18.2, 23.9", \ + "19.0, 19.0, 19.0, 22.1, 27.9", \ + "26.3, 26.3, 26.3, 29.4, 35.3", \ + "40.0, 40.0, 40.0, 43.1, 49.1", \ + "66.7, 66.7, 66.7, 69.7, 75.8"); + } + cell_fall (inslew_load_5x5__21) { + values ("109.9, 109.9, 109.9, 114.1, 122.2", \ + "124.8, 124.8, 124.8, 129.1, 137.3", \ + "151.3, 151.3, 151.3, 155.7, 164.0", \ + "199.7, 199.7, 199.7, 204.1, 212.6", \ + "291.2, 291.2, 291.2, 295.5, 304.2"); + } + fall_transition (inslew_load_5x5__21) { + values ("65.1, 65.1, 65.1, 68.2, 74.4", \ + "77.2, 77.2, 77.2, 80.3, 86.5", \ + "101.4, 101.4, 101.4, 104.6, 110.8", \ + "150.1, 150.1, 150.1, 153.3, 159.5", \ + "247.2, 247.2, 247.2, 250.3, 256.5"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("42.1, 42.1, 42.1, 45.8, 51.9", \ + "41.9, 41.9, 41.9, 45.6, 52.1", \ + "33.1, 33.1, 33.1, 36.9, 43.8", \ + "5.7, 5.7, 5.7, 9.8, 17.1", \ + "-59.1, -59.1, -59.1, -54.8, -46.9"); + } + rise_transition (inslew_load_5x5__21) { + values ("14.5, 14.5, 14.5, 17.4, 23.1", \ + "17.9, 17.9, 17.9, 20.9, 26.6", \ + "24.0, 24.0, 24.0, 27.2, 33.0", \ + "35.5, 35.5, 35.5, 38.6, 44.6", \ + "57.4, 57.4, 57.4, 60.4, 66.5"); + } + cell_fall (inslew_load_5x5__21) { + values ("114.7, 114.7, 114.7, 119.0, 127.1", \ + "139.5, 139.5, 139.5, 143.8, 152.0", \ + "181.2, 181.2, 181.2, 185.5, 193.9", \ + "255.2, 255.2, 255.2, 259.5, 268.1", \ + "394.7, 394.7, 394.7, 399.1, 407.8"); + } + fall_transition (inslew_load_5x5__21) { + values ("64.6, 64.6, 64.6, 67.7, 73.9", \ + "79.4, 79.4, 79.4, 82.5, 88.7", \ + "108.1, 108.1, 108.1, 111.3, 117.5", \ + "164.1, 164.1, 164.1, 167.2, 173.4", \ + "274.6, 274.6, 274.6, 277.7, 283.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1297.1, 1297.1, 1297.1, 1409.2, 1633.4", \ + "1565.7, 1565.7, 1565.7, 1677.8, 1901.9", \ + "2095.2, 2095.2, 2095.2, 2207.3, 2431.5", \ + "3144.4, 3144.4, 3144.4, 3256.5, 3480.6", \ + "5233.2, 5233.2, 5233.2, 5345.3, 5569.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2435.1, 2435.1, 2435.1, 2547.2, 2771.4", \ + "2780.3, 2780.3, 2780.3, 2892.4, 3116.6", \ + "3486.6, 3486.6, 3486.6, 3598.6, 3822.8", \ + "4922.0, 4922.0, 4922.0, 5034.0, 5258.2", \ + "7764.6, 7764.6, 7764.6, 7876.7, 8100.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1196.5, 1196.5, 1196.5, 1308.6, 1532.8", \ + "1383.9, 1383.9, 1383.9, 1496.0, 1720.1", \ + "1748.6, 1748.6, 1748.6, 1860.7, 2084.8", \ + "2463.1, 2463.1, 2463.1, 2575.1, 2799.3", \ + "3876.0, 3876.0, 3876.0, 3988.1, 4212.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2356.2, 2356.2, 2356.2, 2468.3, 2692.4", \ + "2752.6, 2752.6, 2752.6, 2864.7, 3088.9", \ + "3549.8, 3549.8, 3549.8, 3661.9, 3886.1", \ + "5147.8, 5147.8, 5147.8, 5259.9, 5484.1", \ + "8337.7, 8337.7, 8337.7, 8449.8, 8673.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1118.1, 1118.1, 1118.1, 1230.2, 1454.4", \ + "1262.2, 1262.2, 1262.2, 1374.3, 1598.4", \ + "1538.2, 1538.2, 1538.2, 1650.3, 1874.5", \ + "2071.9, 2071.9, 2071.9, 2184.0, 2408.2", \ + "3118.8, 3118.8, 3118.8, 3230.9, 3455.1"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2290.9, 2290.9, 2290.9, 2403.0, 2627.2", \ + "2746.3, 2746.3, 2746.3, 2858.4, 3082.6", \ + "3639.5, 3639.5, 3639.5, 3751.6, 3975.8", \ + "5394.3, 5394.3, 5394.3, 5506.3, 5730.5", \ + "8876.4, 8876.4, 8876.4, 8988.5, 9212.7"); + } + } + } + } + + cell (o4_x2) { + area : 0.0 ; + cell_leakage_power : 0.0062 ; + leakage_power () { + when : "(i0 | i1 | i2 | i3)" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0078 ; + } + pin (i3) { + direction : input ; + capacitance : 24.96 ; + } + pin (i2) { + direction : input ; + capacitance : 19.89 ; + } + pin (i1) { + direction : input ; + capacitance : 24.61 ; + } + pin (i0) { + direction : input ; + capacitance : 20.59 ; + } + pin (q) { + function : "(i2 | i0 | i1 | i3)" ; + direction : output ; + capacitance : 5.48 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("56.8, 56.8, 56.8, 61.2, 68.7", \ + "66.4, 66.4, 66.4, 70.9, 78.9", \ + "79.0, 79.0, 79.0, 83.8, 92.5", \ + "97.8, 97.8, 97.8, 103.0, 112.3", \ + "130.2, 130.2, 130.2, 135.5, 145.6"); + } + rise_transition (inslew_load_5x5__43) { + values ("18.5, 18.5, 18.5, 22.1, 29.1", \ + "23.8, 23.8, 23.8, 27.5, 34.6", \ + "34.0, 34.0, 34.0, 37.8, 45.0", \ + "53.9, 53.9, 53.9, 57.7, 65.1", \ + "93.2, 93.2, 93.2, 97.1, 104.5"); + } + cell_fall (inslew_load_5x5__43) { + values ("87.8, 87.8, 87.8, 92.9, 102.4", \ + "91.1, 91.1, 91.1, 96.3, 105.9", \ + "95.4, 95.4, 95.4, 100.6, 110.5", \ + "99.1, 99.1, 99.1, 104.4, 114.5", \ + "100.7, 100.7, 100.7, 106.0, 116.3"); + } + fall_transition (inslew_load_5x5__43) { + values ("55.2, 55.2, 55.2, 59.0, 66.4", \ + "62.9, 62.9, 62.9, 66.8, 74.2", \ + "78.8, 78.8, 78.8, 82.6, 90.1", \ + "110.6, 110.6, 110.6, 114.5, 122.0", \ + "173.8, 173.8, 173.8, 177.7, 185.3"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("52.6, 52.6, 52.6, 57.0, 64.3", \ + "58.8, 58.8, 58.8, 63.3, 71.2", \ + "64.1, 64.1, 64.1, 68.8, 77.2", \ + "67.0, 67.0, 67.0, 72.1, 81.3", \ + "66.6, 66.6, 66.6, 71.9, 81.9"); + } + rise_transition (inslew_load_5x5__43) { + values ("17.4, 17.4, 17.4, 21.0, 27.9", \ + "21.9, 21.9, 21.9, 25.7, 32.7", \ + "30.7, 30.7, 30.7, 34.5, 41.7", \ + "47.5, 47.5, 47.5, 51.3, 58.7", \ + "80.7, 80.7, 80.7, 84.4, 91.9"); + } + cell_fall (inslew_load_5x5__43) { + values ("84.8, 84.8, 84.8, 89.8, 99.3", \ + "93.9, 93.9, 93.9, 99.0, 108.7", \ + "107.4, 107.4, 107.4, 112.6, 122.5", \ + "128.0, 128.0, 128.0, 133.2, 143.4", \ + "162.3, 162.3, 162.3, 167.6, 178.0"); + } + fall_transition (inslew_load_5x5__43) { + values ("51.4, 51.4, 51.4, 55.2, 62.6", \ + "60.9, 60.9, 60.9, 64.7, 72.1", \ + "79.0, 79.0, 79.0, 82.9, 90.4", \ + "115.4, 115.4, 115.4, 119.2, 126.8", \ + "187.1, 187.1, 187.1, 190.9, 198.6"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("61.5, 61.5, 61.5, 66.0, 73.7", \ + "76.1, 76.1, 76.1, 80.7, 88.9", \ + "99.8, 99.8, 99.8, 104.6, 113.5", \ + "141.7, 141.7, 141.7, 146.9, 156.5", \ + "224.5, 224.5, 224.5, 229.7, 240.0"); + } + rise_transition (inslew_load_5x5__43) { + values ("19.8, 19.8, 19.8, 23.5, 30.5", \ + "26.3, 26.3, 26.3, 30.0, 37.2", \ + "38.8, 38.8, 38.8, 42.6, 49.9", \ + "63.5, 63.5, 63.5, 67.2, 74.7", \ + "112.8, 112.8, 112.8, 117.0, 124.4"); + } + cell_fall (inslew_load_5x5__43) { + values ("86.9, 86.9, 86.9, 92.0, 101.5", \ + "83.3, 83.3, 83.3, 88.4, 98.1", \ + "75.6, 75.6, 75.6, 80.8, 90.6", \ + "57.9, 57.9, 57.9, 63.2, 73.2", \ + "17.3, 17.3, 17.3, 22.5, 32.8"); + } + fall_transition (inslew_load_5x5__43) { + values ("57.5, 57.5, 57.5, 61.3, 68.8", \ + "63.4, 63.4, 63.4, 67.2, 74.7", \ + "75.9, 75.9, 75.9, 79.7, 87.2", \ + "102.1, 102.1, 102.1, 105.9, 113.5", \ + "152.8, 152.8, 152.8, 156.6, 164.2"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("48.0, 48.0, 48.0, 52.3, 59.4", \ + "51.2, 51.2, 51.2, 55.7, 63.4", \ + "50.4, 50.4, 50.4, 55.1, 63.4", \ + "40.9, 40.9, 40.9, 45.9, 54.8", \ + "14.3, 14.3, 14.3, 19.6, 29.3"); + } + rise_transition (inslew_load_5x5__43) { + values ("16.1, 16.1, 16.1, 19.7, 26.5", \ + "20.1, 20.1, 20.1, 23.8, 30.8", \ + "27.8, 27.8, 27.8, 31.6, 38.7", \ + "42.3, 42.3, 42.3, 46.1, 53.5", \ + "70.8, 70.8, 70.8, 74.5, 82.0"); + } + cell_fall (inslew_load_5x5__43) { + values ("84.9, 84.9, 84.9, 90.0, 99.4", \ + "101.9, 101.9, 101.9, 107.0, 116.7", \ + "126.5, 126.5, 126.5, 131.7, 141.6", \ + "166.1, 166.1, 166.1, 171.3, 181.5", \ + "237.0, 237.0, 237.0, 242.3, 252.7"); + } + fall_transition (inslew_load_5x5__43) { + values ("49.2, 49.2, 49.2, 53.0, 60.4", \ + "61.2, 61.2, 61.2, 65.0, 72.4", \ + "83.4, 83.4, 83.4, 87.2, 94.7", \ + "126.1, 126.1, 126.1, 130.0, 137.6", \ + "210.4, 210.4, 210.4, 214.2, 221.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__43) { + values ("779.7, 779.7, 779.7, 848.2, 985.2", \ + "944.6, 944.6, 944.6, 1013.1, 1150.1", \ + "1270.6, 1270.6, 1270.6, 1339.1, 1476.1", \ + "1917.1, 1917.1, 1917.1, 1985.6, 2122.6", \ + "3205.5, 3205.5, 3205.5, 3274.0, 3411.0"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("1190.2, 1190.2, 1190.2, 1258.7, 1395.7", \ + "1339.0, 1339.0, 1339.0, 1407.5, 1544.5", \ + "1640.7, 1640.7, 1640.7, 1709.2, 1846.2", \ + "2246.6, 2246.6, 2246.6, 2315.1, 2452.1", \ + "3453.6, 3453.6, 3453.6, 3522.1, 3659.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__43) { + values ("713.9, 713.9, 713.9, 782.4, 919.4", \ + "844.3, 844.3, 844.3, 912.8, 1049.8", \ + "1100.3, 1100.3, 1100.3, 1168.8, 1305.8", \ + "1606.2, 1606.2, 1606.2, 1674.7, 1811.7", \ + "2612.0, 2612.0, 2612.0, 2680.5, 2817.5"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("1104.0, 1104.0, 1104.0, 1172.5, 1309.5", \ + "1276.7, 1276.7, 1276.7, 1345.2, 1482.2", \ + "1614.0, 1614.0, 1614.0, 1682.5, 1819.5", \ + "2288.2, 2288.2, 2288.2, 2356.7, 2493.7", \ + "3628.4, 3628.4, 3628.4, 3696.9, 3833.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__43) { + values ("859.9, 859.9, 859.9, 928.4, 1065.4", \ + "1081.9, 1081.9, 1081.9, 1150.4, 1287.4", \ + "1522.4, 1522.4, 1522.4, 1590.9, 1727.9", \ + "2399.7, 2399.7, 2399.7, 2468.2, 2605.2", \ + "4156.6, 4156.6, 4156.6, 4225.1, 4362.1"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("1243.7, 1243.7, 1243.7, 1312.2, 1449.2", \ + "1362.8, 1362.8, 1362.8, 1431.3, 1568.3", \ + "1609.4, 1609.4, 1609.4, 1677.9, 1814.9", \ + "2115.4, 2115.4, 2115.4, 2183.9, 2320.9", \ + "3109.8, 3109.8, 3109.8, 3178.3, 3315.3"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__43) { + values ("643.2, 643.2, 643.2, 711.7, 848.7", \ + "748.8, 748.8, 748.8, 817.3, 954.3", \ + "955.2, 955.2, 955.2, 1023.7, 1160.7", \ + "1360.6, 1360.6, 1360.6, 1429.1, 1566.1", \ + "2164.6, 2164.6, 2164.6, 2233.1, 2370.2"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("1029.8, 1029.8, 1029.8, 1098.3, 1235.3", \ + "1232.8, 1232.8, 1232.8, 1301.3, 1438.3", \ + "1620.5, 1620.5, 1620.5, 1689.0, 1826.0", \ + "2379.5, 2379.5, 2379.5, 2448.0, 2585.0", \ + "3884.8, 3884.8, 3884.8, 3953.3, 4090.3"); + } + } + } + } + + cell (o4_x4) { + area : 0.0 ; + cell_leakage_power : 0.015 ; + leakage_power () { + when : "(i0 | i1 | i2 | i3)" ; + value : 0.012 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.018 ; + } + pin (i3) { + direction : input ; + capacitance : 22.40 ; + } + pin (i2) { + direction : input ; + capacitance : 23.38 ; + } + pin (i1) { + direction : input ; + capacitance : 22.33 ; + } + pin (i0) { + direction : input ; + capacitance : 22.33 ; + } + pin (q) { + function : "(i3 | i2 | i0 | i1)" ; + direction : output ; + capacitance : 9.02 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__45) { + values ("36.5, 36.5, 36.5, 40.1, 46.0", \ + "36.7, 36.7, 36.7, 40.4, 46.8", \ + "30.7, 30.7, 30.7, 34.5, 41.4", \ + "12.0, 12.0, 12.0, 16.2, 23.6", \ + "-31.1, -31.1, -31.1, -26.7, -18.7"); + } + rise_transition (inslew_load_5x5__45) { + values ("13.1, 13.1, 13.1, 16.1, 21.7", \ + "16.9, 16.9, 16.9, 19.9, 25.6", \ + "23.9, 23.9, 23.9, 27.1, 32.9", \ + "37.4, 37.4, 37.4, 40.5, 46.6", \ + "63.9, 63.9, 63.9, 66.9, 72.9"); + } + cell_fall (inslew_load_5x5__45) { + values ("90.9, 90.9, 90.9, 95.2, 103.2", \ + "106.9, 106.9, 106.9, 111.2, 119.4", \ + "134.8, 134.8, 134.8, 139.1, 147.5", \ + "186.8, 186.8, 186.8, 191.2, 199.7", \ + "286.4, 286.4, 286.4, 290.8, 299.5"); + } + fall_transition (inslew_load_5x5__45) { + values ("55.2, 55.2, 55.2, 58.3, 64.4", \ + "68.6, 68.6, 68.6, 71.7, 77.9", \ + "94.6, 94.6, 94.6, 97.7, 103.9", \ + "146.8, 146.8, 146.8, 149.9, 156.1", \ + "250.6, 250.6, 250.6, 253.7, 259.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__45) { + values ("33.3, 33.3, 33.3, 36.8, 42.6", \ + "31.1, 31.1, 31.1, 34.8, 41.0", \ + "20.2, 20.2, 20.2, 23.9, 30.7", \ + "-8.9, -8.9, -8.9, -4.9, 2.4", \ + "-73.9, -73.9, -73.9, -69.6, -61.7"); + } + rise_transition (inslew_load_5x5__45) { + values ("12.3, 12.3, 12.3, 15.2, 20.8", \ + "15.7, 15.7, 15.7, 18.7, 24.4", \ + "21.9, 21.9, 21.9, 25.0, 30.8", \ + "33.5, 33.5, 33.5, 36.6, 42.6", \ + "56.2, 56.2, 56.2, 59.1, 65.2"); + } + cell_fall (inslew_load_5x5__45) { + values ("84.2, 84.2, 84.2, 88.4, 96.3", \ + "104.2, 104.2, 104.2, 108.5, 116.6", \ + "141.0, 141.0, 141.0, 145.3, 153.7", \ + "206.8, 206.8, 206.8, 211.2, 219.7", \ + "333.8, 333.8, 333.8, 338.2, 346.9"); + } + fall_transition (inslew_load_5x5__45) { + values ("49.9, 49.9, 49.9, 53.0, 59.2", \ + "64.0, 64.0, 64.0, 67.2, 73.3", \ + "92.7, 92.7, 92.7, 95.8, 102.0", \ + "147.8, 147.8, 147.8, 150.9, 157.1", \ + "257.3, 257.3, 257.3, 260.4, 266.6"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__45) { + values ("39.7, 39.7, 39.7, 43.3, 49.3", \ + "42.9, 42.9, 42.9, 46.7, 53.2", \ + "44.1, 44.1, 44.1, 48.0, 54.9", \ + "40.6, 40.6, 40.6, 44.9, 52.4", \ + "29.3, 29.3, 29.3, 33.8, 42.1"); + } + rise_transition (inslew_load_5x5__45) { + values ("13.9, 13.9, 13.9, 16.9, 22.5", \ + "18.4, 18.4, 18.4, 21.4, 27.1", \ + "26.7, 26.7, 26.7, 29.8, 35.8", \ + "43.0, 43.0, 43.0, 46.1, 52.2", \ + "75.3, 75.3, 75.3, 78.4, 84.3"); + } + cell_fall (inslew_load_5x5__45) { + values ("94.4, 94.4, 94.4, 98.7, 106.7", \ + "104.4, 104.4, 104.4, 108.7, 116.9", \ + "122.3, 122.3, 122.3, 126.6, 134.9", \ + "155.0, 155.0, 155.0, 159.4, 167.9", \ + "217.6, 217.6, 217.6, 222.0, 230.7"); + } + fall_transition (inslew_load_5x5__45) { + values ("59.4, 59.4, 59.4, 62.6, 68.7", \ + "71.0, 71.0, 71.0, 74.2, 80.4", \ + "94.8, 94.8, 94.8, 97.9, 104.2", \ + "141.6, 141.6, 141.6, 144.8, 151.0", \ + "235.9, 235.9, 235.9, 239.0, 245.2"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__45) { + values ("43.6, 43.6, 43.6, 47.3, 53.5", \ + "51.8, 51.8, 51.8, 55.6, 62.3", \ + "63.7, 63.7, 63.7, 67.6, 74.8", \ + "83.0, 83.0, 83.0, 87.3, 95.1", \ + "119.1, 119.1, 119.1, 123.5, 132.0"); + } + rise_transition (inslew_load_5x5__45) { + values ("15.0, 15.0, 15.0, 18.0, 23.7", \ + "20.4, 20.4, 20.4, 23.5, 29.3", \ + "31.0, 31.0, 31.0, 34.1, 40.1", \ + "51.9, 51.9, 51.9, 54.8, 60.9", \ + "93.0, 93.0, 93.0, 96.3, 102.2"); + } + cell_fall (inslew_load_5x5__45) { + values ("94.0, 94.0, 94.0, 98.3, 106.4", \ + "96.5, 96.5, 96.5, 100.8, 109.0", \ + "101.5, 101.5, 101.5, 105.8, 114.2", \ + "110.0, 110.0, 110.0, 114.3, 122.8", \ + "125.5, 125.5, 125.5, 129.9, 138.5"); + } + fall_transition (inslew_load_5x5__45) { + values ("62.1, 62.1, 62.1, 65.2, 71.4", \ + "71.7, 71.7, 71.7, 74.9, 81.0", \ + "91.5, 91.5, 91.5, 94.6, 100.8", \ + "131.9, 131.9, 131.9, 135.0, 141.3", \ + "213.5, 213.5, 213.5, 216.6, 222.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__45) { + values ("960.2, 960.2, 960.2, 1072.9, 1298.3", \ + "1136.8, 1136.8, 1136.8, 1249.5, 1474.9", \ + "1480.5, 1480.5, 1480.5, 1593.2, 1818.6", \ + "2154.5, 2154.5, 2154.5, 2267.2, 2492.6", \ + "3491.4, 3491.4, 3491.4, 3604.1, 3829.5"); + } + fall_power (energy_inslew_load_5x5__45) { + values ("1952.5, 1952.5, 1952.5, 2065.2, 2290.6", \ + "2376.0, 2376.0, 2376.0, 2488.7, 2714.1", \ + "3205.4, 3205.4, 3205.4, 3318.1, 3543.5", \ + "4871.2, 4871.2, 4871.2, 4983.9, 5209.3", \ + "8189.6, 8189.6, 8189.6, 8302.3, 8527.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__45) { + values ("876.4, 876.4, 876.4, 989.1, 1214.6", \ + "1019.8, 1019.8, 1019.8, 1132.5, 1358.0", \ + "1296.1, 1296.1, 1296.1, 1408.9, 1634.3", \ + "1833.8, 1833.8, 1833.8, 1946.5, 2172.0", \ + "2896.2, 2896.2, 2896.2, 3008.9, 3234.4"); + } + fall_power (energy_inslew_load_5x5__45) { + values ("1772.5, 1772.5, 1772.5, 1885.2, 2110.6", \ + "2210.0, 2210.0, 2210.0, 2322.8, 2548.2", \ + "3094.9, 3094.9, 3094.9, 3207.6, 3433.0", \ + "4820.6, 4820.6, 4820.6, 4933.3, 5158.7", \ + "8258.7, 8258.7, 8258.7, 8371.4, 8596.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__45) { + values ("1045.3, 1045.3, 1045.3, 1158.0, 1383.4", \ + "1277.0, 1277.0, 1277.0, 1389.7, 1615.1", \ + "1731.4, 1731.4, 1731.4, 1844.2, 2069.6", \ + "2630.9, 2630.9, 2630.9, 2743.6, 2969.0", \ + "4421.7, 4421.7, 4421.7, 4534.4, 4759.8"); + } + fall_power (energy_inslew_load_5x5__45) { + values ("2099.6, 2099.6, 2099.6, 2212.3, 2437.7", \ + "2479.8, 2479.8, 2479.8, 2592.5, 2817.9", \ + "3250.9, 3250.9, 3250.9, 3363.6, 3589.0", \ + "4778.9, 4778.9, 4778.9, 4891.6, 5117.0", \ + "7848.1, 7848.1, 7848.1, 7960.8, 8186.2"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__45) { + values ("1159.8, 1159.8, 1159.8, 1272.5, 1497.9", \ + "1485.6, 1485.6, 1485.6, 1598.3, 1823.8", \ + "2130.8, 2130.8, 2130.8, 2243.5, 2468.9", \ + "3413.5, 3413.5, 3413.5, 3526.3, 3751.7", \ + "5974.1, 5974.1, 5974.1, 6086.9, 6312.3"); + } + fall_power (energy_inslew_load_5x5__45) { + values ("2191.4, 2191.4, 2191.4, 2304.1, 2529.5", \ + "2516.8, 2516.8, 2516.8, 2629.5, 2854.9", \ + "3177.3, 3177.3, 3177.3, 3290.0, 3515.4", \ + "4518.5, 4518.5, 4518.5, 4631.2, 4856.7", \ + "7216.8, 7216.8, 7216.8, 7329.6, 7555.0"); + } + } + } + } + + cell (oa22_x2) { + area : 0.0 ; + cell_leakage_power : 0.0068 ; + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 0.0091 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0))" ; + value : 0.0088 ; + } + leakage_power () { + when : "((i0 & i1) | i2)" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.0049 ; + } + pin (i2) { + direction : input ; + capacitance : 22.08 ; + } + pin (i1) { + direction : input ; + capacitance : 20.40 ; + } + pin (i0) { + direction : input ; + capacitance : 27.70 ; + } + pin (q) { + function : "((i0 & (i2 | i1)) | i2)" ; + direction : output ; + capacitance : 5.48 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("32.8, 32.8, 32.8, 37.1, 44.2", \ + "28.4, 28.4, 28.4, 32.8, 40.3", \ + "14.8, 14.8, 14.8, 19.3, 27.3", \ + "-18.7, -18.7, -18.7, -13.9, -5.2", \ + "-91.5, -91.5, -91.5, -86.3, -77.0"); + } + rise_transition (inslew_load_5x5__43) { + values ("15.4, 15.4, 15.4, 19.0, 25.8", \ + "18.4, 18.4, 18.4, 22.0, 28.9", \ + "24.1, 24.1, 24.1, 27.8, 34.9", \ + "35.0, 35.0, 35.0, 38.8, 46.1", \ + "56.6, 56.6, 56.6, 60.3, 67.7"); + } + cell_fall (inslew_load_5x5__43) { + values ("82.0, 82.0, 82.0, 87.0, 96.3", \ + "104.7, 104.7, 104.7, 109.8, 119.4", \ + "144.4, 144.4, 144.4, 149.6, 159.5", \ + "218.1, 218.1, 218.1, 223.4, 233.7", \ + "361.4, 361.4, 361.4, 366.7, 377.2"); + } + fall_transition (inslew_load_5x5__43) { + values ("43.4, 43.4, 43.4, 47.2, 54.5", \ + "57.7, 57.7, 57.7, 61.5, 68.9", \ + "85.2, 85.2, 85.2, 89.0, 96.6", \ + "139.2, 139.2, 139.2, 143.0, 150.6", \ + "246.4, 246.4, 246.4, 250.3, 257.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("37.2, 37.2, 37.2, 41.5, 48.5", \ + "36.9, 36.9, 36.9, 41.3, 48.9", \ + "29.9, 29.9, 29.9, 34.5, 42.6", \ + "9.0, 9.0, 9.0, 13.8, 22.7", \ + "-38.3, -38.3, -38.3, -33.1, -23.5"); + } + rise_transition (inslew_load_5x5__43) { + values ("15.2, 15.2, 15.2, 18.8, 25.6", \ + "18.9, 18.9, 18.9, 22.5, 29.5", \ + "25.7, 25.7, 25.7, 29.4, 36.5", \ + "38.7, 38.7, 38.7, 42.5, 49.8", \ + "64.3, 64.3, 64.3, 68.0, 75.5"); + } + cell_fall (inslew_load_5x5__43) { + values ("75.1, 75.1, 75.1, 80.1, 89.3", \ + "92.6, 92.6, 92.6, 97.7, 107.2", \ + "121.0, 121.0, 121.0, 126.1, 136.0", \ + "171.1, 171.1, 171.1, 176.4, 186.5", \ + "266.6, 266.6, 266.6, 271.9, 282.3"); + } + fall_transition (inslew_load_5x5__43) { + values ("39.6, 39.6, 39.6, 43.4, 50.7", \ + "51.5, 51.5, 51.5, 55.3, 62.7", \ + "74.1, 74.1, 74.1, 77.9, 85.4", \ + "118.1, 118.1, 118.1, 122.0, 129.6", \ + "205.4, 205.4, 205.4, 209.2, 216.9"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("30.6, 30.6, 30.6, 34.5, 41.0", \ + "30.2, 30.2, 30.2, 34.5, 41.7", \ + "25.1, 25.1, 25.1, 29.6, 37.5", \ + "10.0, 10.0, 10.0, 14.8, 23.6", \ + "-23.5, -23.5, -23.5, -18.3, -8.7"); + } + rise_transition (inslew_load_5x5__43) { + values ("12.0, 12.0, 12.0, 15.6, 22.2", \ + "15.9, 15.9, 15.9, 19.5, 26.3", \ + "23.0, 23.0, 23.0, 26.7, 33.7", \ + "36.7, 36.7, 36.7, 40.5, 47.8", \ + "64.0, 64.0, 64.0, 67.6, 75.1"); + } + cell_fall (inslew_load_5x5__43) { + values ("72.9, 72.9, 72.9, 77.9, 87.3", \ + "85.6, 85.6, 85.6, 90.7, 100.2", \ + "108.4, 108.4, 108.4, 113.6, 123.5", \ + "151.3, 151.3, 151.3, 156.5, 166.7", \ + "234.6, 234.6, 234.6, 239.9, 250.4"); + } + fall_transition (inslew_load_5x5__43) { + values ("42.6, 42.6, 42.6, 46.4, 53.7", \ + "54.4, 54.4, 54.4, 58.2, 65.6", \ + "77.5, 77.5, 77.5, 81.3, 88.8", \ + "123.9, 123.9, 123.9, 127.7, 135.3", \ + "216.5, 216.5, 216.5, 220.3, 228.0"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__43) { + values ("690.4, 690.4, 690.4, 758.9, 895.9", \ + "789.3, 789.3, 789.3, 857.8, 994.8", \ + "985.2, 985.2, 985.2, 1053.7, 1190.7", \ + "1372.7, 1372.7, 1372.7, 1441.2, 1578.2", \ + "2143.5, 2143.5, 2143.5, 2212.0, 2349.0"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("1062.4, 1062.4, 1062.4, 1130.9, 1267.9", \ + "1352.9, 1352.9, 1352.9, 1421.4, 1558.4", \ + "1923.4, 1923.4, 1923.4, 1991.9, 2128.9", \ + "3054.8, 3054.8, 3054.8, 3123.3, 3260.3", \ + "5310.5, 5310.5, 5310.5, 5379.0, 5516.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__43) { + values ("645.5, 645.5, 645.5, 714.0, 851.0", \ + "756.8, 756.8, 756.8, 825.3, 962.3", \ + "974.6, 974.6, 974.6, 1043.1, 1180.1", \ + "1404.2, 1404.2, 1404.2, 1472.7, 1609.7", \ + "2258.5, 2258.5, 2258.5, 2327.0, 2464.0"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("960.0, 960.0, 960.0, 1028.5, 1165.5", \ + "1191.4, 1191.4, 1191.4, 1259.9, 1396.9", \ + "1643.2, 1643.2, 1643.2, 1711.7, 1848.7", \ + "2536.2, 2536.2, 2536.2, 2604.7, 2741.7", \ + "4314.4, 4314.4, 4314.4, 4382.9, 4519.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__43) { + values ("687.9, 687.9, 687.9, 756.4, 893.4", \ + "843.1, 843.1, 843.1, 911.6, 1048.6", \ + "1149.5, 1149.5, 1149.5, 1218.0, 1355.0", \ + "1758.3, 1758.3, 1758.3, 1826.8, 1963.8", \ + "2972.5, 2972.5, 2972.5, 3041.0, 3178.0"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("1078.2, 1078.2, 1078.2, 1146.7, 1283.7", \ + "1342.1, 1342.1, 1342.1, 1410.6, 1547.6", \ + "1865.6, 1865.6, 1865.6, 1934.1, 2071.1", \ + "2915.3, 2915.3, 2915.3, 2983.8, 3120.8", \ + "5013.7, 5013.7, 5013.7, 5082.2, 5219.2"); + } + } + } + } + + cell (oa22_x4) { + area : 0.0 ; + cell_leakage_power : 0.0086 ; + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 0.0091 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0))" ; + value : 0.0088 ; + } + leakage_power () { + when : "((i0 & i1) | i2)" ; + value : 0.012 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.0049 ; + } + pin (i2) { + direction : input ; + capacitance : 23.42 ; + } + pin (i1) { + direction : input ; + capacitance : 23.83 ; + } + pin (i0) { + direction : input ; + capacitance : 24.88 ; + } + pin (q) { + function : "((i0 & (i2 | i1)) | i2)" ; + direction : output ; + capacitance : 8.97 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("55.3, 55.3, 55.3, 59.1, 65.9", \ + "53.9, 53.9, 53.9, 57.8, 64.7", \ + "44.7, 44.7, 44.7, 48.6, 55.9", \ + "16.4, 16.4, 16.4, 20.6, 28.2", \ + "-51.4, -51.4, -51.4, -47.0, -38.9"); + } + rise_transition (inslew_load_5x5__21) { + values ("22.9, 22.9, 22.9, 26.0, 31.9", \ + "25.8, 25.8, 25.8, 28.9, 34.9", \ + "31.7, 31.7, 31.7, 34.8, 40.9", \ + "43.1, 43.1, 43.1, 46.2, 52.3", \ + "65.0, 65.0, 65.0, 68.1, 74.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("129.1, 129.1, 129.1, 133.4, 141.5", \ + "155.0, 155.0, 155.0, 159.3, 167.6", \ + "199.2, 199.2, 199.2, 203.5, 211.9", \ + "277.5, 277.5, 277.5, 281.8, 290.4", \ + "429.0, 429.0, 429.0, 433.4, 442.0"); + } + fall_transition (inslew_load_5x5__21) { + values ("70.5, 70.5, 70.5, 73.6, 79.8", \ + "84.5, 84.5, 84.5, 87.7, 93.9", \ + "112.4, 112.4, 112.4, 115.6, 121.8", \ + "166.9, 166.9, 166.9, 170.0, 176.3", \ + "276.7, 276.7, 276.7, 279.8, 286.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("61.6, 61.6, 61.6, 65.4, 72.2", \ + "65.9, 65.9, 65.9, 69.7, 76.7", \ + "64.8, 64.8, 64.8, 68.9, 76.2", \ + "50.4, 50.4, 50.4, 54.6, 62.3", \ + "8.4, 8.4, 8.4, 12.8, 21.1"); + } + rise_transition (inslew_load_5x5__21) { + values ("22.8, 22.8, 22.8, 25.9, 31.8", \ + "26.6, 26.6, 26.6, 29.7, 35.7", \ + "33.9, 33.9, 33.9, 37.0, 43.0", \ + "47.4, 47.4, 47.4, 50.5, 56.6", \ + "73.4, 73.4, 73.4, 76.5, 82.6"); + } + cell_fall (inslew_load_5x5__21) { + values ("122.8, 122.8, 122.8, 127.0, 135.1", \ + "143.8, 143.8, 143.8, 148.1, 156.3", \ + "177.9, 177.9, 177.9, 182.2, 190.6", \ + "234.1, 234.1, 234.1, 238.4, 246.9", \ + "334.3, 334.3, 334.3, 338.7, 347.3"); + } + fall_transition (inslew_load_5x5__21) { + values ("66.7, 66.7, 66.7, 69.9, 76.0", \ + "78.4, 78.4, 78.4, 81.5, 87.7", \ + "101.5, 101.5, 101.5, 104.7, 110.9", \ + "146.2, 146.2, 146.2, 149.4, 155.6", \ + "234.1, 234.1, 234.1, 237.3, 243.5"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("48.3, 48.3, 48.3, 52.0, 58.3", \ + "51.6, 51.6, 51.6, 55.3, 62.0", \ + "50.5, 50.5, 50.5, 54.4, 61.4", \ + "39.3, 39.3, 39.3, 43.5, 51.0", \ + "8.7, 8.7, 8.7, 13.0, 21.2"); + } + rise_transition (inslew_load_5x5__21) { + values ("16.1, 16.1, 16.1, 19.1, 24.9", \ + "20.1, 20.1, 20.1, 23.2, 29.0", \ + "27.5, 27.5, 27.5, 30.6, 36.6", \ + "41.7, 41.7, 41.7, 44.8, 50.9", \ + "69.2, 69.2, 69.2, 72.3, 78.4"); + } + cell_fall (inslew_load_5x5__21) { + values ("117.5, 117.5, 117.5, 121.8, 129.9", \ + "131.2, 131.2, 131.2, 135.5, 143.7", \ + "156.3, 156.3, 156.3, 160.7, 169.0", \ + "201.6, 201.6, 201.6, 206.0, 214.5", \ + "291.4, 291.4, 291.4, 295.8, 304.4"); + } + fall_transition (inslew_load_5x5__21) { + values ("68.5, 68.5, 68.5, 71.7, 77.8", \ + "79.7, 79.7, 79.7, 82.8, 89.0", \ + "103.0, 103.0, 103.0, 106.1, 112.3", \ + "149.0, 149.0, 149.0, 152.2, 158.4", \ + "243.8, 243.8, 243.8, 246.9, 253.2"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1408.1, 1408.1, 1408.1, 1520.1, 1744.3", \ + "1536.7, 1536.7, 1536.7, 1648.8, 1872.9", \ + "1794.4, 1794.4, 1794.4, 1906.5, 2130.7", \ + "2299.9, 2299.9, 2299.9, 2412.0, 2636.2", \ + "3295.5, 3295.5, 3295.5, 3407.5, 3631.7"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2523.5, 2523.5, 2523.5, 2635.6, 2859.8", \ + "2961.5, 2961.5, 2961.5, 3073.6, 3297.8", \ + "3832.2, 3832.2, 3832.2, 3944.3, 4168.4", \ + "5547.1, 5547.1, 5547.1, 5659.2, 5883.4", \ + "8996.3, 8996.3, 8996.3, 9108.4, 9332.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1363.2, 1363.2, 1363.2, 1475.3, 1699.4", \ + "1515.1, 1515.1, 1515.1, 1627.2, 1851.4", \ + "1810.5, 1810.5, 1810.5, 1922.6, 2146.8", \ + "2381.8, 2381.8, 2381.8, 2493.9, 2718.1", \ + "3503.5, 3503.5, 3503.5, 3615.6, 3839.7"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2381.5, 2381.5, 2381.5, 2493.6, 2717.8", \ + "2735.3, 2735.3, 2735.3, 2847.4, 3071.5", \ + "3438.4, 3438.4, 3438.4, 3550.5, 3774.6", \ + "4813.8, 4813.8, 4813.8, 4925.9, 5150.0", \ + "7532.0, 7532.0, 7532.0, 7644.1, 7868.3"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1301.6, 1301.6, 1301.6, 1413.7, 1637.9", \ + "1499.0, 1499.0, 1499.0, 1611.1, 1835.2", \ + "1884.2, 1884.2, 1884.2, 1996.3, 2220.5", \ + "2639.7, 2639.7, 2639.7, 2751.8, 2976.0", \ + "4134.3, 4134.3, 4134.3, 4246.4, 4470.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2504.5, 2504.5, 2504.5, 2616.6, 2840.8", \ + "2879.8, 2879.8, 2879.8, 2991.9, 3216.1", \ + "3653.3, 3653.3, 3653.3, 3765.4, 3989.5", \ + "5188.8, 5188.8, 5188.8, 5300.9, 5525.0", \ + "8317.0, 8317.0, 8317.0, 8429.1, 8653.2"); + } + } + } + } + + cell (oa2a22_x2) { + area : 0.0 ; + cell_leakage_power : 0.0029 ; + leakage_power () { + when : "(i3 & !(i2) & !(i1) & i0)" ; + value : 0.0039 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & !(i0))" ; + value : 0.0036 ; + } + leakage_power () { + when : "((i0 & !(i1) & i2 & !(i3)) | (!(i0) & i1 & !(i2) & i3))" ; + value : 0.0038 ; + } + leakage_power () { + when : "((i0 & i1) | (i2 & i3))" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i0) & (i1 ^ i2) & !(i3))" ; + value : 0.002 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & !(i1) & !(i2) & i3))" ; + value : 0.0021 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.00036 ; + } + pin (i3) { + direction : input ; + capacitance : 25.39 ; + } + pin (i2) { + direction : input ; + capacitance : 29.19 ; + } + pin (i1) { + direction : input ; + capacitance : 21.52 ; + } + pin (i0) { + direction : input ; + capacitance : 21.60 ; + } + pin (q) { + function : "((i0 & ((i3 & i2) | i1)) | (i3 & i2))" ; + direction : output ; + capacitance : 5.48 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("58.2, 58.2, 58.2, 62.7, 70.8", \ + "61.9, 61.9, 61.9, 66.6, 74.9", \ + "64.7, 64.7, 64.7, 69.6, 78.4", \ + "64.7, 64.7, 64.7, 69.9, 79.2", \ + "59.4, 59.4, 59.4, 64.6, 74.8"); + } + rise_transition (inslew_load_5x5__43) { + values ("24.1, 24.1, 24.1, 27.9, 34.9", \ + "28.8, 28.8, 28.8, 32.6, 39.8", \ + "38.2, 38.2, 38.2, 42.0, 49.3", \ + "56.8, 56.8, 56.8, 60.5, 68.0", \ + "93.5, 93.5, 93.5, 97.4, 104.8"); + } + cell_fall (inslew_load_5x5__43) { + values ("70.9, 70.9, 70.9, 75.9, 85.1", \ + "83.0, 83.0, 83.0, 88.1, 97.5", \ + "99.2, 99.2, 99.2, 104.4, 114.0", \ + "123.0, 123.0, 123.0, 128.2, 138.2", \ + "163.2, 163.2, 163.2, 168.4, 178.8"); + } + fall_transition (inslew_load_5x5__43) { + values ("38.0, 38.0, 38.0, 41.8, 49.1", \ + "47.3, 47.3, 47.3, 51.1, 58.5", \ + "64.7, 64.7, 64.7, 68.5, 75.9", \ + "98.1, 98.1, 98.1, 101.9, 109.5", \ + "163.9, 163.9, 163.9, 167.8, 175.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("63.9, 63.9, 63.9, 68.4, 76.5", \ + "73.7, 73.7, 73.7, 78.3, 86.7", \ + "85.9, 85.9, 85.9, 90.8, 99.7", \ + "102.5, 102.5, 102.5, 107.7, 117.2", \ + "129.0, 129.0, 129.0, 134.2, 144.4"); + } + rise_transition (inslew_load_5x5__43) { + values ("23.7, 23.7, 23.7, 27.4, 34.5", \ + "29.3, 29.3, 29.3, 33.1, 40.3", \ + "40.0, 40.0, 40.0, 43.8, 51.2", \ + "61.0, 61.0, 61.0, 64.7, 72.2", \ + "102.0, 102.0, 102.0, 106.1, 113.4"); + } + cell_fall (inslew_load_5x5__43) { + values ("66.9, 66.9, 66.9, 71.9, 81.0", \ + "75.4, 75.4, 75.4, 80.4, 89.7", \ + "83.3, 83.3, 83.3, 88.5, 98.0", \ + "89.1, 89.1, 89.1, 94.3, 104.2", \ + "90.7, 90.7, 90.7, 96.0, 106.2"); + } + fall_transition (inslew_load_5x5__43) { + values ("35.8, 35.8, 35.8, 39.6, 46.9", \ + "43.6, 43.6, 43.6, 47.3, 54.7", \ + "57.7, 57.7, 57.7, 61.5, 68.9", \ + "84.4, 84.4, 84.4, 88.3, 95.8", \ + "136.5, 136.5, 136.5, 140.3, 147.9"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("72.9, 72.9, 72.9, 77.5, 85.7", \ + "88.2, 88.2, 88.2, 93.0, 101.6", \ + "112.3, 112.3, 112.3, 117.4, 126.5", \ + "153.7, 153.7, 153.7, 159.0, 168.8", \ + "232.7, 232.7, 232.7, 237.9, 248.2"); + } + rise_transition (inslew_load_5x5__43) { + values ("27.0, 27.0, 27.0, 30.7, 37.9", \ + "34.0, 34.0, 34.0, 37.8, 45.0", \ + "47.7, 47.7, 47.7, 51.5, 58.9", \ + "74.7, 74.7, 74.7, 78.4, 85.9", \ + "128.2, 128.2, 128.2, 132.3, 139.8"); + } + cell_fall (inslew_load_5x5__43) { + values ("63.0, 63.0, 63.0, 68.0, 77.2", \ + "63.3, 63.3, 63.3, 68.3, 77.6", \ + "59.0, 59.0, 59.0, 64.1, 73.6", \ + "42.5, 42.5, 42.5, 47.7, 57.5", \ + "0.3, 0.3, 0.3, 5.6, 15.7"); + } + fall_transition (inslew_load_5x5__43) { + values ("37.4, 37.4, 37.4, 41.2, 48.4", \ + "42.7, 42.7, 42.7, 46.5, 53.8", \ + "53.3, 53.3, 53.3, 57.1, 64.5", \ + "73.7, 73.7, 73.7, 77.6, 85.1", \ + "113.6, 113.6, 113.6, 117.4, 125.0"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("67.6, 67.6, 67.6, 72.2, 80.4", \ + "76.6, 76.6, 76.6, 81.4, 90.0", \ + "91.2, 91.2, 91.2, 96.2, 105.3", \ + "115.8, 115.8, 115.8, 121.1, 130.8", \ + "163.3, 163.3, 163.3, 168.5, 178.8"); + } + rise_transition (inslew_load_5x5__43) { + values ("27.6, 27.6, 27.6, 31.4, 38.6", \ + "33.9, 33.9, 33.9, 37.7, 45.0", \ + "46.6, 46.6, 46.6, 50.3, 57.7", \ + "71.8, 71.8, 71.8, 75.6, 83.0", \ + "122.3, 122.3, 122.3, 126.4, 133.9"); + } + cell_fall (inslew_load_5x5__43) { + values ("66.7, 66.7, 66.7, 71.6, 80.9", \ + "69.9, 69.9, 69.9, 74.9, 84.3", \ + "72.0, 72.0, 72.0, 77.1, 86.7", \ + "69.9, 69.9, 69.9, 75.1, 85.0", \ + "58.9, 58.9, 58.9, 64.2, 74.4"); + } + fall_transition (inslew_load_5x5__43) { + values ("39.5, 39.5, 39.5, 43.3, 50.6", \ + "46.1, 46.1, 46.1, 49.9, 57.3", \ + "59.5, 59.5, 59.5, 63.3, 70.8", \ + "85.8, 85.8, 85.8, 89.6, 97.1", \ + "137.5, 137.5, 137.5, 141.3, 148.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__43) { + values ("750.6, 750.6, 750.6, 819.1, 956.1", \ + "874.7, 874.7, 874.7, 943.2, 1080.2", \ + "1123.2, 1123.2, 1123.2, 1191.7, 1328.7", \ + "1617.5, 1617.5, 1617.5, 1686.0, 1823.0", \ + "2603.0, 2603.0, 2603.0, 2671.5, 2808.5"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("907.5, 907.5, 907.5, 976.0, 1113.0", \ + "1077.1, 1077.1, 1077.1, 1145.6, 1282.6", \ + "1404.0, 1404.0, 1404.0, 1472.5, 1609.5", \ + "2045.4, 2045.4, 2045.4, 2113.9, 2250.9", \ + "3318.6, 3318.6, 3318.6, 3387.1, 3524.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__43) { + values ("718.5, 718.5, 718.5, 787.0, 924.0", \ + "851.6, 851.6, 851.6, 920.1, 1057.1", \ + "1113.6, 1113.6, 1113.6, 1182.1, 1319.1", \ + "1631.5, 1631.5, 1631.5, 1700.0, 1837.0", \ + "2661.5, 2661.5, 2661.5, 2730.0, 2867.0"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("849.9, 849.9, 849.9, 918.4, 1055.4", \ + "981.9, 981.9, 981.9, 1050.4, 1187.4", \ + "1232.6, 1232.6, 1232.6, 1301.1, 1438.1", \ + "1719.4, 1719.4, 1719.4, 1787.9, 1924.9", \ + "2678.5, 2678.5, 2678.5, 2747.0, 2884.0"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__43) { + values ("834.3, 834.3, 834.3, 902.8, 1039.8", \ + "1015.2, 1015.2, 1015.2, 1083.7, 1220.7", \ + "1373.9, 1373.9, 1373.9, 1442.4, 1579.4", \ + "2086.3, 2086.3, 2086.3, 2154.8, 2291.8", \ + "3510.0, 3510.0, 3510.0, 3578.5, 3715.5"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("926.6, 926.6, 926.6, 995.1, 1132.1", \ + "1025.8, 1025.8, 1025.8, 1094.3, 1231.3", \ + "1224.9, 1224.9, 1224.9, 1293.4, 1430.4", \ + "1615.8, 1615.8, 1615.8, 1684.3, 1821.3", \ + "2387.5, 2387.5, 2387.5, 2456.0, 2593.0"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__43) { + values ("875.0, 875.0, 875.0, 943.5, 1080.5", \ + "1055.2, 1055.2, 1055.2, 1123.7, 1260.7", \ + "1414.9, 1414.9, 1414.9, 1483.4, 1620.4", \ + "2134.5, 2134.5, 2134.5, 2203.0, 2340.0", \ + "3576.9, 3576.9, 3576.9, 3645.4, 3782.4"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("982.9, 982.9, 982.9, 1051.4, 1188.4", \ + "1116.6, 1116.6, 1116.6, 1185.1, 1322.2", \ + "1386.4, 1386.4, 1386.4, 1454.9, 1591.9", \ + "1921.0, 1921.0, 1921.0, 1989.5, 2126.5", \ + "2982.7, 2982.7, 2982.7, 3051.2, 3188.2"); + } + } + } + } + + cell (oa2a22_x4) { + area : 0.0 ; + cell_leakage_power : 0.0039 ; + leakage_power () { + when : "(i3 & !(i2) & !(i1) & i0)" ; + value : 0.0039 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & !(i0))" ; + value : 0.0036 ; + } + leakage_power () { + when : "((i0 & !(i1) & i2 & !(i3)) | (!(i0) & i1 & !(i2) & i3))" ; + value : 0.0038 ; + } + leakage_power () { + when : "((i0 & i1) | (i2 & i3))" ; + value : 0.012 ; + } + leakage_power () { + when : "(!(i0) & (i1 ^ i2) & !(i3))" ; + value : 0.002 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & !(i1) & !(i2) & i3))" ; + value : 0.0021 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.00036 ; + } + pin (i3) { + direction : input ; + capacitance : 29.02 ; + } + pin (i2) { + direction : input ; + capacitance : 28.31 ; + } + pin (i1) { + direction : input ; + capacitance : 25.14 ; + } + pin (i0) { + direction : input ; + capacitance : 24.79 ; + } + pin (q) { + function : "((i0 & ((i3 & i2) | i1)) | (i3 & i2))" ; + direction : output ; + capacitance : 8.97 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("91.9, 91.9, 91.9, 96.0, 103.4", \ + "98.1, 98.1, 98.1, 102.3, 109.8", \ + "105.6, 105.6, 105.6, 109.9, 117.7", \ + "112.4, 112.4, 112.4, 116.9, 125.1", \ + "116.6, 116.6, 116.6, 120.8, 129.4"); + } + rise_transition (inslew_load_5x5__21) { + values ("36.9, 36.9, 36.9, 40.0, 46.0", \ + "41.5, 41.5, 41.5, 44.6, 50.7", \ + "51.2, 51.2, 51.2, 54.3, 60.3", \ + "70.7, 70.7, 70.7, 73.7, 79.8", \ + "109.0, 109.0, 109.0, 112.3, 118.5"); + } + cell_fall (inslew_load_5x5__21) { + values ("105.9, 105.9, 105.9, 110.2, 118.2", \ + "120.8, 120.8, 120.8, 125.1, 133.2", \ + "141.3, 141.3, 141.3, 145.6, 153.8", \ + "168.3, 168.3, 168.3, 172.7, 181.1", \ + "207.8, 207.8, 207.8, 212.1, 220.7"); + } + fall_transition (inslew_load_5x5__21) { + values ("57.8, 57.8, 57.8, 61.0, 67.1", \ + "66.7, 66.7, 66.7, 69.9, 76.0", \ + "84.2, 84.2, 84.2, 87.3, 93.5", \ + "117.4, 117.4, 117.4, 120.5, 126.7", \ + "181.8, 181.8, 181.8, 184.9, 191.2"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("98.7, 98.7, 98.7, 102.9, 110.2", \ + "112.6, 112.6, 112.6, 116.8, 124.4", \ + "131.6, 131.6, 131.6, 135.9, 143.7", \ + "156.7, 156.7, 156.7, 161.1, 169.4", \ + "194.0, 194.0, 194.0, 198.2, 206.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("36.4, 36.4, 36.4, 39.5, 45.6", \ + "42.1, 42.1, 42.1, 45.2, 51.3", \ + "53.5, 53.5, 53.5, 56.5, 62.6", \ + "75.4, 75.4, 75.4, 78.5, 84.5", \ + "118.1, 118.1, 118.1, 121.5, 127.7"); + } + cell_fall (inslew_load_5x5__21) { + values ("102.3, 102.3, 102.3, 106.5, 114.5", \ + "114.3, 114.3, 114.3, 118.6, 126.7", \ + "127.8, 127.8, 127.8, 132.1, 140.3", \ + "139.0, 139.0, 139.0, 143.3, 151.7", \ + "143.0, 143.0, 143.0, 147.4, 155.9"); + } + fall_transition (inslew_load_5x5__21) { + values ("55.8, 55.8, 55.8, 58.9, 65.0", \ + "63.3, 63.3, 63.3, 66.5, 72.6", \ + "77.8, 77.8, 77.8, 80.9, 87.1", \ + "104.7, 104.7, 104.7, 107.8, 114.1", \ + "156.2, 156.2, 156.2, 159.3, 165.6"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("107.4, 107.4, 107.4, 111.6, 119.1", \ + "126.3, 126.3, 126.3, 130.5, 138.2", \ + "155.7, 155.7, 155.7, 160.0, 168.1", \ + "204.1, 204.1, 204.1, 208.5, 216.9", \ + "292.1, 292.1, 292.1, 296.3, 304.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("39.9, 39.9, 39.9, 42.9, 49.0", \ + "46.9, 46.9, 46.9, 50.0, 56.1", \ + "61.2, 61.2, 61.2, 64.2, 70.3", \ + "89.0, 89.0, 89.0, 92.3, 98.3", \ + "144.2, 144.2, 144.2, 147.6, 154.1"); + } + cell_fall (inslew_load_5x5__21) { + values ("95.9, 95.9, 95.9, 100.1, 108.1", \ + "97.5, 97.5, 97.5, 101.7, 109.8", \ + "96.3, 96.3, 96.3, 100.5, 108.7", \ + "83.6, 83.6, 83.6, 87.9, 96.3", \ + "44.0, 44.0, 44.0, 48.3, 56.8"); + } + fall_transition (inslew_load_5x5__21) { + values ("56.3, 56.3, 56.3, 59.5, 65.6", \ + "61.2, 61.2, 61.2, 64.4, 70.5", \ + "71.5, 71.5, 71.5, 74.7, 80.8", \ + "91.9, 91.9, 91.9, 95.1, 101.3", \ + "131.2, 131.2, 131.2, 134.3, 140.6"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("100.8, 100.8, 100.8, 105.0, 112.5", \ + "111.5, 111.5, 111.5, 115.7, 123.4", \ + "128.7, 128.7, 128.7, 133.0, 140.9", \ + "156.9, 156.9, 156.9, 161.2, 169.6", \ + "207.9, 207.9, 207.9, 212.1, 220.5"); + } + rise_transition (inslew_load_5x5__21) { + values ("40.5, 40.5, 40.5, 43.5, 49.6", \ + "46.5, 46.5, 46.5, 49.6, 55.7", \ + "59.3, 59.3, 59.3, 62.3, 68.4", \ + "84.6, 84.6, 84.6, 87.8, 93.8", \ + "135.5, 135.5, 135.5, 138.9, 145.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("99.6, 99.6, 99.6, 103.8, 111.8", \ + "104.1, 104.1, 104.1, 108.4, 116.5", \ + "109.1, 109.1, 109.1, 113.4, 121.6", \ + "111.1, 111.1, 111.1, 115.4, 123.8", \ + "103.9, 103.9, 103.9, 108.3, 116.8"); + } + fall_transition (inslew_load_5x5__21) { + values ("58.5, 58.5, 58.5, 61.7, 67.8", \ + "64.9, 64.9, 64.9, 68.0, 74.1", \ + "78.1, 78.1, 78.1, 81.3, 87.4", \ + "104.7, 104.7, 104.7, 107.8, 114.1", \ + "156.9, 156.9, 156.9, 160.0, 166.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1586.1, 1586.1, 1586.1, 1698.2, 1922.4", \ + "1759.2, 1759.2, 1759.2, 1871.3, 2095.5", \ + "2113.9, 2113.9, 2113.9, 2225.9, 2450.1", \ + "2826.2, 2826.2, 2826.2, 2938.2, 3162.4", \ + "4242.8, 4242.8, 4242.8, 4354.8, 4579.0"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2076.7, 2076.7, 2076.7, 2188.8, 2412.9", \ + "2335.4, 2335.4, 2335.4, 2447.4, 2671.6", \ + "2846.5, 2846.5, 2846.5, 2958.6, 3182.7", \ + "3831.8, 3831.8, 3831.8, 3943.9, 4168.1", \ + "5762.9, 5762.9, 5762.9, 5875.0, 6099.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1548.7, 1548.7, 1548.7, 1660.7, 1884.9", \ + "1741.6, 1741.6, 1741.6, 1853.7, 2077.8", \ + "2127.9, 2127.9, 2127.9, 2240.0, 2464.2", \ + "2887.6, 2887.6, 2887.6, 2999.7, 3223.9", \ + "4389.1, 4389.1, 4389.1, 4501.2, 4725.3"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1999.2, 1999.2, 1999.2, 2111.3, 2335.5", \ + "2208.1, 2208.1, 2208.1, 2320.1, 2544.3", \ + "2614.3, 2614.3, 2614.3, 2726.3, 2950.5", \ + "3384.4, 3384.4, 3384.4, 3496.5, 3720.6", \ + "4875.4, 4875.4, 4875.4, 4987.5, 5211.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1703.0, 1703.0, 1703.0, 1815.1, 2039.3", \ + "1957.5, 1957.5, 1957.5, 2069.6, 2293.8", \ + "2469.0, 2469.0, 2469.0, 2581.1, 2805.3", \ + "3483.0, 3483.0, 3483.0, 3595.1, 3819.3", \ + "5504.6, 5504.6, 5504.6, 5616.7, 5840.8"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2073.5, 2073.5, 2073.5, 2185.6, 2409.7", \ + "2219.6, 2219.6, 2219.6, 2331.7, 2555.8", \ + "2523.3, 2523.3, 2523.3, 2635.3, 2859.5", \ + "3126.2, 3126.2, 3126.2, 3238.3, 3462.4", \ + "4301.3, 4301.3, 4301.3, 4413.4, 4637.5"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1746.0, 1746.0, 1746.0, 1858.1, 2082.3", \ + "1984.2, 1984.2, 1984.2, 2096.3, 2320.5", \ + "2472.1, 2472.1, 2472.1, 2584.2, 2808.4", \ + "3446.9, 3446.9, 3446.9, 3559.0, 3783.2", \ + "5408.0, 5408.0, 5408.0, 5520.1, 5744.3"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2157.2, 2157.2, 2157.2, 2269.3, 2493.5", \ + "2356.8, 2356.8, 2356.8, 2468.9, 2693.1", \ + "2770.1, 2770.1, 2770.1, 2882.2, 3106.4", \ + "3598.5, 3598.5, 3598.5, 3710.6, 3934.7", \ + "5234.9, 5234.9, 5234.9, 5347.0, 5571.2"); + } + } + } + } + + cell (oa2a2a23_x2) { + area : 0.0 ; + cell_leakage_power : 0.0078 ; + leakage_power () { + when : "(i5 & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 0.014 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & (i4 ^ i5)))) | (!(i0) & i1 & (i2 ^ i3) & (i4 ^ i5)))" ; + value : 0.013 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i0) & !(i1) & i2 & !(i3) & !(i4) & i5))" ; + value : 0.0095 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & (i3 ^ i4) & !(i5)) | (!(i1) & !(i2) & i3 & i4 & !(i5))))" ; + value : 0.0088 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & (i3 ^ i4) & !(i5)) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))))))" ; + value : 0.0092 ; + } + leakage_power () { + when : "((i0 & i1) | (i2 & i3) | (i4 & i5))" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i1) & !(i2) & (i3 ^ i4) & !(i5))))" ; + value : 0.005 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))))" ; + value : 0.0053 ; + } + leakage_power () { + when : "(!(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0011 ; + } + pin (i5) { + direction : input ; + capacitance : 21.77 ; + } + pin (i4) { + direction : input ; + capacitance : 21.77 ; + } + pin (i3) { + direction : input ; + capacitance : 22.13 ; + } + pin (i2) { + direction : input ; + capacitance : 21.77 ; + } + pin (i1) { + direction : input ; + capacitance : 21.77 ; + } + pin (i0) { + direction : input ; + capacitance : 21.77 ; + } + pin (q) { + function : "((i5 & ((i3 & ((i0 & i1) | i2 | i4)) | (i0 & i1) | i4)) | (i3 & ((i0 & i1) | i2)) | (i0 & i1))" ; + direction : output ; + capacitance : 5.48 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("54.0, 54.0, 54.0, 58.5, 66.5", \ + "62.2, 62.2, 62.2, 66.9, 75.2", \ + "75.1, 75.1, 75.1, 80.1, 89.0", \ + "97.5, 97.5, 97.5, 102.8, 112.3", \ + "141.8, 141.8, 141.8, 146.9, 157.3"); + } + rise_transition (inslew_load_5x5__43) { + values ("22.4, 22.4, 22.4, 26.1, 33.2", \ + "28.7, 28.7, 28.7, 32.5, 39.6", \ + "41.0, 41.0, 41.0, 44.8, 52.2", \ + "65.7, 65.7, 65.7, 69.4, 76.9", \ + "115.0, 115.0, 115.0, 119.1, 126.5"); + } + cell_fall (inslew_load_5x5__43) { + values ("68.7, 68.7, 68.7, 73.7, 83.0", \ + "70.7, 70.7, 70.7, 75.7, 85.2", \ + "73.2, 73.2, 73.2, 78.3, 88.1", \ + "75.1, 75.1, 75.1, 80.4, 90.4", \ + "75.9, 75.9, 75.9, 81.2, 91.6"); + } + fall_transition (inslew_load_5x5__43) { + values ("43.9, 43.9, 43.9, 47.7, 55.0", \ + "51.9, 51.9, 51.9, 55.7, 63.1", \ + "68.5, 68.5, 68.5, 72.4, 79.8", \ + "101.0, 101.0, 101.0, 104.8, 112.4", \ + "166.4, 166.4, 166.4, 170.2, 177.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("58.9, 58.9, 58.9, 63.5, 71.4", \ + "72.6, 72.6, 72.6, 77.2, 85.6", \ + "94.4, 94.4, 94.4, 99.4, 108.3", \ + "132.9, 132.9, 132.9, 138.1, 147.8", \ + "206.5, 206.5, 206.5, 211.6, 222.0"); + } + rise_transition (inslew_load_5x5__43) { + values ("21.8, 21.8, 21.8, 25.5, 32.5", \ + "28.7, 28.7, 28.7, 32.5, 39.7", \ + "42.1, 42.1, 42.1, 45.9, 53.2", \ + "68.4, 68.4, 68.4, 72.1, 79.6", \ + "120.3, 120.3, 120.3, 124.4, 131.9"); + } + cell_fall (inslew_load_5x5__43) { + values ("63.5, 63.5, 63.5, 68.5, 77.8", \ + "61.8, 61.8, 61.8, 66.8, 76.3", \ + "56.2, 56.2, 56.2, 61.3, 70.9", \ + "40.9, 40.9, 40.9, 46.1, 56.0", \ + "5.5, 5.5, 5.5, 10.8, 21.1"); + } + fall_transition (inslew_load_5x5__43) { + values ("40.9, 40.9, 40.9, 44.6, 51.9", \ + "46.9, 46.9, 46.9, 50.7, 58.1", \ + "59.2, 59.2, 59.2, 63.0, 70.5", \ + "83.9, 83.9, 83.9, 87.7, 95.3", \ + "132.9, 132.9, 132.9, 136.7, 144.3"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("43.0, 43.0, 43.0, 47.4, 54.9", \ + "45.3, 45.3, 45.3, 49.8, 57.8", \ + "46.1, 46.1, 46.1, 50.8, 59.4", \ + "43.6, 43.6, 43.6, 48.7, 57.9", \ + "35.4, 35.4, 35.4, 40.7, 50.7"); + } + rise_transition (inslew_load_5x5__43) { + values ("18.6, 18.6, 18.6, 22.2, 29.1", \ + "23.2, 23.2, 23.2, 26.9, 34.0", \ + "32.3, 32.3, 32.3, 36.1, 43.4", \ + "50.5, 50.5, 50.5, 54.2, 61.6", \ + "86.5, 86.5, 86.5, 90.3, 97.7"); + } + cell_fall (inslew_load_5x5__43) { + values ("66.9, 66.9, 66.9, 71.9, 81.2", \ + "76.0, 76.0, 76.0, 81.1, 90.5", \ + "90.9, 90.9, 90.9, 96.1, 105.8", \ + "116.5, 116.5, 116.5, 121.8, 131.9", \ + "164.2, 164.2, 164.2, 169.6, 179.9"); + } + fall_transition (inslew_load_5x5__43) { + values ("40.0, 40.0, 40.0, 43.8, 51.1", \ + "49.8, 49.8, 49.8, 53.6, 61.0", \ + "69.6, 69.6, 69.6, 73.4, 80.9", \ + "108.6, 108.6, 108.6, 112.4, 120.0", \ + "186.1, 186.1, 186.1, 189.9, 197.6"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("47.8, 47.8, 47.8, 52.2, 59.7", \ + "55.2, 55.2, 55.2, 59.7, 67.8", \ + "64.3, 64.3, 64.3, 69.1, 77.7", \ + "77.4, 77.4, 77.4, 82.6, 91.9", \ + "99.8, 99.8, 99.8, 105.1, 115.2"); + } + rise_transition (inslew_load_5x5__43) { + values ("18.2, 18.2, 18.2, 21.8, 28.7", \ + "23.6, 23.6, 23.6, 27.3, 34.4", \ + "33.9, 33.9, 33.9, 37.7, 44.9", \ + "54.2, 54.2, 54.2, 57.9, 65.4", \ + "94.2, 94.2, 94.2, 98.1, 105.5"); + } + cell_fall (inslew_load_5x5__43) { + values ("61.8, 61.8, 61.8, 66.7, 75.9", \ + "66.8, 66.8, 66.8, 71.8, 81.2", \ + "72.8, 72.8, 72.8, 77.9, 87.5", \ + "79.2, 79.2, 79.2, 84.4, 94.4", \ + "87.0, 87.0, 87.0, 92.2, 102.5"); + } + fall_transition (inslew_load_5x5__43) { + values ("37.1, 37.1, 37.1, 40.8, 48.1", \ + "44.9, 44.9, 44.9, 48.7, 56.0", \ + "60.5, 60.5, 60.5, 64.3, 71.7", \ + "91.0, 91.0, 91.0, 94.8, 102.4", \ + "151.3, 151.3, 151.3, 155.1, 162.7"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("39.8, 39.8, 39.8, 44.1, 51.2", \ + "42.7, 42.7, 42.7, 47.2, 54.9", \ + "43.3, 43.3, 43.3, 48.0, 56.3", \ + "39.0, 39.0, 39.0, 44.1, 53.2", \ + "26.5, 26.5, 26.5, 31.8, 41.7"); + } + rise_transition (inslew_load_5x5__43) { + values ("15.6, 15.6, 15.6, 19.2, 26.0", \ + "20.1, 20.1, 20.1, 23.8, 30.8", \ + "28.6, 28.6, 28.6, 32.4, 39.6", \ + "45.1, 45.1, 45.1, 48.9, 56.3", \ + "77.8, 77.8, 77.8, 81.5, 89.0"); + } + cell_fall (inslew_load_5x5__43) { + values ("57.6, 57.6, 57.6, 62.6, 71.6", \ + "69.0, 69.0, 69.0, 74.0, 83.4", \ + "85.1, 85.1, 85.1, 90.2, 99.8", \ + "110.8, 110.8, 110.8, 116.0, 126.1", \ + "157.0, 157.0, 157.0, 162.3, 172.7"); + } + fall_transition (inslew_load_5x5__43) { + values ("32.5, 32.5, 32.5, 36.2, 43.5", \ + "42.5, 42.5, 42.5, 46.3, 53.6", \ + "61.4, 61.4, 61.4, 65.2, 72.6", \ + "97.9, 97.9, 97.9, 101.8, 109.3", \ + "170.3, 170.3, 170.3, 174.1, 181.8"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("35.3, 35.3, 35.3, 39.6, 46.8", \ + "33.7, 33.7, 33.7, 38.1, 45.8", \ + "26.4, 26.4, 26.4, 31.0, 39.3", \ + "7.3, 7.3, 7.3, 12.3, 21.2", \ + "-34.7, -34.7, -34.7, -29.5, -19.8"); + } + rise_transition (inslew_load_5x5__43) { + values ("16.0, 16.0, 16.0, 19.5, 26.4", \ + "19.7, 19.7, 19.7, 23.4, 30.3", \ + "26.9, 26.9, 26.9, 30.7, 37.8", \ + "41.1, 41.1, 41.1, 44.9, 52.2", \ + "69.3, 69.3, 69.3, 73.0, 80.5"); + } + cell_fall (inslew_load_5x5__43) { + values ("62.7, 62.7, 62.7, 67.7, 76.8", \ + "79.6, 79.6, 79.6, 84.6, 94.1", \ + "106.5, 106.5, 106.5, 111.7, 121.5", \ + "155.0, 155.0, 155.0, 160.3, 170.4", \ + "247.8, 247.8, 247.8, 253.2, 263.6"); + } + fall_transition (inslew_load_5x5__43) { + values ("35.2, 35.2, 35.2, 39.0, 46.3", \ + "47.8, 47.8, 47.8, 51.6, 59.0", \ + "71.3, 71.3, 71.3, 75.1, 82.6", \ + "117.3, 117.3, 117.3, 121.1, 128.7", \ + "208.4, 208.4, 208.4, 212.3, 219.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__43) { + values ("1110.8, 1110.8, 1110.8, 1179.3, 1316.3", \ + "1393.7, 1393.7, 1393.7, 1462.2, 1599.2", \ + "1958.3, 1958.3, 1958.3, 2026.8, 2163.8", \ + "3086.2, 3086.2, 3086.2, 3154.7, 3291.7", \ + "5345.4, 5345.4, 5345.4, 5413.9, 5550.9"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("1264.8, 1264.8, 1264.8, 1333.3, 1470.3", \ + "1474.0, 1474.0, 1474.0, 1542.5, 1679.5", \ + "1899.0, 1899.0, 1899.0, 1967.5, 2104.5", \ + "2741.7, 2741.7, 2741.7, 2810.2, 2947.2", \ + "4433.1, 4433.1, 4433.1, 4501.6, 4638.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__43) { + values ("1045.4, 1045.4, 1045.4, 1113.9, 1250.9", \ + "1323.9, 1323.9, 1323.9, 1392.4, 1529.4", \ + "1876.0, 1876.0, 1876.0, 1944.5, 2081.5", \ + "2975.6, 2975.6, 2975.6, 3044.1, 3181.1", \ + "5171.5, 5171.5, 5171.5, 5240.0, 5377.0"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("1169.7, 1169.7, 1169.7, 1238.2, 1375.2", \ + "1319.3, 1319.3, 1319.3, 1387.8, 1524.8", \ + "1620.7, 1620.7, 1620.7, 1689.2, 1826.2", \ + "2225.2, 2225.2, 2225.2, 2293.7, 2430.7", \ + "3430.8, 3430.8, 3430.8, 3499.3, 3636.3"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__43) { + values ("876.4, 876.4, 876.4, 944.9, 1081.9", \ + "1069.2, 1069.2, 1069.2, 1137.7, 1274.7", \ + "1453.0, 1453.0, 1453.0, 1521.5, 1658.5", \ + "2219.0, 2219.0, 2219.0, 2287.5, 2424.5", \ + "3748.7, 3748.7, 3748.7, 3817.2, 3954.2"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("1140.6, 1140.6, 1140.6, 1209.1, 1346.1", \ + "1382.6, 1382.6, 1382.6, 1451.1, 1588.1", \ + "1868.0, 1868.0, 1868.0, 1936.5, 2073.5", \ + "2833.6, 2833.6, 2833.6, 2902.1, 3039.1", \ + "4761.7, 4761.7, 4761.7, 4830.2, 4967.2"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__43) { + values ("823.6, 823.6, 823.6, 892.1, 1029.1", \ + "1023.5, 1023.5, 1023.5, 1092.0, 1229.0", \ + "1418.2, 1418.2, 1418.2, 1486.7, 1623.7", \ + "2203.2, 2203.2, 2203.2, 2271.7, 2408.7", \ + "3769.6, 3769.6, 3769.6, 3838.1, 3975.1"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("1047.0, 1047.0, 1047.0, 1115.5, 1252.5", \ + "1228.8, 1228.8, 1228.8, 1297.3, 1434.3", \ + "1592.3, 1592.3, 1592.3, 1660.8, 1797.8", \ + "2313.2, 2313.2, 2313.2, 2381.7, 2518.7", \ + "3748.8, 3748.8, 3748.8, 3817.3, 3954.3"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__43) { + values ("675.6, 675.6, 675.6, 744.1, 881.1", \ + "828.7, 828.7, 828.7, 897.2, 1034.2", \ + "1130.1, 1130.1, 1130.1, 1198.6, 1335.6", \ + "1727.6, 1727.6, 1727.6, 1796.1, 1933.1", \ + "2919.4, 2919.4, 2919.4, 2987.9, 3124.9"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("877.3, 877.3, 877.3, 945.8, 1082.8", \ + "1089.2, 1089.2, 1089.2, 1157.7, 1294.7", \ + "1500.7, 1500.7, 1500.7, 1569.2, 1706.2", \ + "2313.0, 2313.0, 2313.0, 2381.5, 2518.5", \ + "3930.6, 3930.6, 3930.6, 3999.1, 4136.1"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__43) { + values ("722.2, 722.2, 722.2, 790.7, 927.7", \ + "863.1, 863.1, 863.1, 931.6, 1068.6", \ + "1142.5, 1142.5, 1142.5, 1211.0, 1348.0", \ + "1698.5, 1698.5, 1698.5, 1767.0, 1904.0", \ + "2807.6, 2807.6, 2807.6, 2876.1, 3013.1"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("968.6, 968.6, 968.6, 1037.1, 1174.1", \ + "1245.6, 1245.6, 1245.6, 1314.1, 1451.1", \ + "1782.7, 1782.7, 1782.7, 1851.2, 1988.3", \ + "2847.8, 2847.8, 2847.8, 2916.3, 3053.3", \ + "4971.0, 4971.0, 4971.0, 5039.5, 5176.5"); + } + } + } + } + + cell (oa2a2a23_x4) { + area : 0.0 ; + cell_leakage_power : 0.0086 ; + leakage_power () { + when : "(i5 & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 0.014 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & (i4 ^ i5)))) | (!(i0) & i1 & (i2 ^ i3) & (i4 ^ i5)))" ; + value : 0.013 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i0) & !(i1) & i2 & !(i3) & !(i4) & i5))" ; + value : 0.0095 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & (i3 ^ i4) & !(i5)) | (!(i1) & !(i2) & i3 & i4 & !(i5))))" ; + value : 0.0088 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & (i3 ^ i4) & !(i5)) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))))))" ; + value : 0.0092 ; + } + leakage_power () { + when : "((i0 & i1) | (i2 & i3) | (i4 & i5))" ; + value : 0.012 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i1) & !(i2) & (i3 ^ i4) & !(i5))))" ; + value : 0.005 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))))" ; + value : 0.0053 ; + } + leakage_power () { + when : "(!(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0011 ; + } + pin (i5) { + direction : input ; + capacitance : 27.44 ; + } + pin (i4) { + direction : input ; + capacitance : 26.19 ; + } + pin (i3) { + direction : input ; + capacitance : 27.44 ; + } + pin (i2) { + direction : input ; + capacitance : 27.44 ; + } + pin (i1) { + direction : input ; + capacitance : 27.44 ; + } + pin (i0) { + direction : input ; + capacitance : 28.15 ; + } + pin (q) { + function : "((i4 & ((i3 & ((i1 & i0) | i2 | i5)) | (i1 & i0) | i5)) | (i3 & ((i1 & i0) | i2)) | (i1 & i0))" ; + direction : output ; + capacitance : 8.97 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("70.2, 70.2, 70.2, 74.1, 81.2", \ + "79.4, 79.4, 79.4, 83.5, 90.8", \ + "93.8, 93.8, 93.8, 98.0, 105.7", \ + "117.8, 117.8, 117.8, 122.2, 130.4", \ + "163.6, 163.6, 163.6, 167.8, 176.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("28.2, 28.2, 28.2, 31.3, 37.3", \ + "34.5, 34.5, 34.5, 37.6, 43.6", \ + "46.9, 46.9, 46.9, 50.0, 56.1", \ + "71.8, 71.8, 71.8, 74.9, 80.9", \ + "121.5, 121.5, 121.5, 124.9, 131.1"); + } + cell_fall (inslew_load_5x5__21) { + values ("94.8, 94.8, 94.8, 99.1, 107.1", \ + "97.4, 97.4, 97.4, 101.7, 109.8", \ + "100.9, 100.9, 100.9, 105.2, 113.5", \ + "104.7, 104.7, 104.7, 109.0, 117.4", \ + "107.4, 107.4, 107.4, 111.8, 120.3"); + } + fall_transition (inslew_load_5x5__21) { + values ("59.7, 59.7, 59.7, 62.8, 68.9", \ + "67.4, 67.4, 67.4, 70.5, 76.7", \ + "83.7, 83.7, 83.7, 86.9, 93.1", \ + "116.4, 116.4, 116.4, 119.5, 125.7", \ + "182.2, 182.2, 182.2, 185.3, 191.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("76.1, 76.1, 76.1, 80.0, 87.0", \ + "91.5, 91.5, 91.5, 95.6, 102.9", \ + "115.6, 115.6, 115.6, 119.9, 127.6", \ + "156.4, 156.4, 156.4, 160.8, 169.0", \ + "233.5, 233.5, 233.5, 237.7, 246.2"); + } + rise_transition (inslew_load_5x5__21) { + values ("27.7, 27.7, 27.7, 30.8, 36.8", \ + "34.6, 34.6, 34.6, 37.7, 43.8", \ + "48.2, 48.2, 48.2, 51.3, 57.4", \ + "74.8, 74.8, 74.8, 77.9, 84.0", \ + "127.6, 127.6, 127.6, 130.9, 137.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("89.8, 89.8, 89.8, 94.0, 102.0", \ + "88.7, 88.7, 88.7, 93.0, 101.1", \ + "84.8, 84.8, 84.8, 89.1, 97.3", \ + "72.0, 72.0, 72.0, 76.3, 84.6", \ + "39.3, 39.3, 39.3, 43.7, 52.2"); + } + fall_transition (inslew_load_5x5__21) { + values ("56.6, 56.6, 56.6, 59.8, 65.9", \ + "62.3, 62.3, 62.3, 65.4, 71.6", \ + "74.8, 74.8, 74.8, 77.9, 84.1", \ + "99.4, 99.4, 99.4, 102.5, 108.7", \ + "148.8, 148.8, 148.8, 151.9, 158.2"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("59.6, 59.6, 59.6, 63.4, 70.3", \ + "63.5, 63.5, 63.5, 67.4, 74.6", \ + "66.4, 66.4, 66.4, 70.6, 78.0", \ + "66.2, 66.2, 66.2, 70.6, 78.4", \ + "60.1, 60.1, 60.1, 64.3, 72.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("24.3, 24.3, 24.3, 27.4, 33.2", \ + "28.9, 28.9, 28.9, 32.0, 38.0", \ + "38.2, 38.2, 38.2, 41.3, 47.4", \ + "56.7, 56.7, 56.7, 59.7, 65.8", \ + "92.9, 92.9, 92.9, 96.3, 102.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("93.6, 93.6, 93.6, 97.8, 105.8", \ + "104.0, 104.0, 104.0, 108.2, 116.3", \ + "120.8, 120.8, 120.8, 125.1, 133.4", \ + "149.0, 149.0, 149.0, 153.3, 161.8", \ + "199.0, 199.0, 199.0, 203.4, 211.9"); + } + fall_transition (inslew_load_5x5__21) { + values ("55.8, 55.8, 55.8, 58.9, 65.0", \ + "65.6, 65.6, 65.6, 68.7, 74.9", \ + "85.2, 85.2, 85.2, 88.4, 94.6", \ + "124.6, 124.6, 124.6, 127.7, 134.0", \ + "202.7, 202.7, 202.7, 205.8, 212.0"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("65.7, 65.7, 65.7, 69.5, 76.4", \ + "75.6, 75.6, 75.6, 79.5, 86.7", \ + "87.8, 87.8, 87.8, 91.9, 99.4", \ + "103.9, 103.9, 103.9, 108.2, 116.2", \ + "128.8, 128.8, 128.8, 133.0, 141.5"); + } + rise_transition (inslew_load_5x5__21) { + values ("23.9, 23.9, 23.9, 27.1, 32.9", \ + "29.4, 29.4, 29.4, 32.5, 38.5", \ + "40.1, 40.1, 40.1, 43.1, 49.2", \ + "60.8, 60.8, 60.8, 63.8, 69.9", \ + "101.2, 101.2, 101.2, 104.5, 110.6"); + } + cell_fall (inslew_load_5x5__21) { + values ("88.7, 88.7, 88.7, 92.9, 100.8", \ + "95.2, 95.2, 95.2, 99.5, 107.5", \ + "103.8, 103.8, 103.8, 108.1, 116.3", \ + "113.5, 113.5, 113.5, 117.9, 126.2", \ + "124.4, 124.4, 124.4, 128.8, 137.3"); + } + fall_transition (inslew_load_5x5__21) { + values ("52.8, 52.8, 52.8, 56.0, 62.1", \ + "60.7, 60.7, 60.7, 63.8, 69.9", \ + "76.2, 76.2, 76.2, 79.3, 85.5", \ + "107.1, 107.1, 107.1, 110.3, 116.5", \ + "168.0, 168.0, 168.0, 171.2, 177.4"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("58.5, 58.5, 58.5, 62.3, 69.0", \ + "64.7, 64.7, 64.7, 68.5, 75.5", \ + "69.0, 69.0, 69.0, 73.1, 80.5", \ + "68.4, 68.4, 68.4, 72.7, 80.5", \ + "58.9, 58.9, 58.9, 63.3, 71.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("21.4, 21.4, 21.4, 24.5, 30.4", \ + "26.1, 26.1, 26.1, 29.2, 35.1", \ + "34.9, 34.9, 34.9, 38.0, 44.0", \ + "51.9, 51.9, 51.9, 54.9, 61.0", \ + "84.9, 84.9, 84.9, 88.2, 94.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("85.7, 85.7, 85.7, 90.0, 97.8", \ + "101.1, 101.1, 101.1, 105.4, 113.4", \ + "121.8, 121.8, 121.8, 126.1, 134.3", \ + "151.8, 151.8, 151.8, 156.1, 164.6", \ + "201.8, 201.8, 201.8, 206.2, 214.7"); + } + fall_transition (inslew_load_5x5__21) { + values ("48.6, 48.6, 48.6, 51.7, 57.8", \ + "59.2, 59.2, 59.2, 62.3, 68.4", \ + "78.6, 78.6, 78.6, 81.8, 87.9", \ + "115.9, 115.9, 115.9, 119.0, 125.2", \ + "188.9, 188.9, 188.9, 192.0, 198.3"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("52.6, 52.6, 52.6, 56.3, 63.1", \ + "53.0, 53.0, 53.0, 56.8, 63.7", \ + "48.5, 48.5, 48.5, 52.4, 59.8", \ + "32.4, 32.4, 32.4, 36.6, 44.3", \ + "-7.2, -7.2, -7.2, -2.8, 5.5"); + } + rise_transition (inslew_load_5x5__21) { + values ("21.6, 21.6, 21.6, 24.7, 30.6", \ + "25.4, 25.4, 25.4, 28.5, 34.4", \ + "32.8, 32.8, 32.8, 35.9, 41.9", \ + "47.4, 47.4, 47.4, 50.4, 56.6", \ + "75.9, 75.9, 75.9, 79.1, 85.1"); + } + cell_fall (inslew_load_5x5__21) { + values ("90.9, 90.9, 90.9, 95.1, 103.0", \ + "110.7, 110.7, 110.7, 114.9, 123.0", \ + "141.4, 141.4, 141.4, 145.7, 154.0", \ + "193.2, 193.2, 193.2, 197.5, 206.0", \ + "288.8, 288.8, 288.8, 293.1, 301.7"); + } + fall_transition (inslew_load_5x5__21) { + values ("51.6, 51.6, 51.6, 54.7, 60.8", \ + "64.3, 64.3, 64.3, 67.5, 73.6", \ + "88.4, 88.4, 88.4, 91.5, 97.7", \ + "134.9, 134.9, 134.9, 138.1, 144.3", \ + "226.8, 226.8, 226.8, 229.9, 236.1"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1769.8, 1769.8, 1769.8, 1881.9, 2106.1", \ + "2114.1, 2114.1, 2114.1, 2226.2, 2450.3", \ + "2802.6, 2802.6, 2802.6, 2914.7, 3138.9", \ + "4178.7, 4178.7, 4178.7, 4290.8, 4515.0", \ + "6937.9, 6937.9, 6937.9, 7050.0, 7274.1"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2394.3, 2394.3, 2394.3, 2506.4, 2730.5", \ + "2681.9, 2681.9, 2681.9, 2793.9, 3018.1", \ + "3275.5, 3275.5, 3275.5, 3387.5, 3611.7", \ + "4464.4, 4464.4, 4464.4, 4576.5, 4800.7", \ + "6852.0, 6852.0, 6852.0, 6964.1, 7188.3"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1699.4, 1699.4, 1699.4, 1811.5, 2035.7", \ + "2046.5, 2046.5, 2046.5, 2158.6, 2382.7", \ + "2735.1, 2735.1, 2735.1, 2847.2, 3071.3", \ + "4101.8, 4101.8, 4101.8, 4213.9, 4438.1", \ + "6832.8, 6832.8, 6832.8, 6944.9, 7169.0"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2267.1, 2267.1, 2267.1, 2379.2, 2603.3", \ + "2472.6, 2472.6, 2472.6, 2584.6, 2808.8", \ + "2907.3, 2907.3, 2907.3, 3019.4, 3243.6", \ + "3769.8, 3769.8, 3769.8, 3881.8, 4106.0", \ + "5499.9, 5499.9, 5499.9, 5612.0, 5836.2"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1494.6, 1494.6, 1494.6, 1606.7, 1830.9", \ + "1733.3, 1733.3, 1733.3, 1845.4, 2069.6", \ + "2210.7, 2210.7, 2210.7, 2322.8, 2546.9", \ + "3161.5, 3161.5, 3161.5, 3273.6, 3497.7", \ + "5055.6, 5055.6, 5055.6, 5167.7, 5391.9"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2229.2, 2229.2, 2229.2, 2341.3, 2565.5", \ + "2574.2, 2574.2, 2574.2, 2686.3, 2910.5", \ + "3264.3, 3264.3, 3264.3, 3376.4, 3600.6", \ + "4648.8, 4648.8, 4648.8, 4760.9, 4985.1", \ + "7403.8, 7403.8, 7403.8, 7515.9, 7740.1"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1439.3, 1439.3, 1439.3, 1551.4, 1775.6", \ + "1694.9, 1694.9, 1694.9, 1807.0, 2031.1", \ + "2197.5, 2197.5, 2197.5, 2309.6, 2533.8", \ + "3190.4, 3190.4, 3190.4, 3302.5, 3526.6", \ + "5164.1, 5164.1, 5164.1, 5276.2, 5500.4"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2104.8, 2104.8, 2104.8, 2216.9, 2441.1", \ + "2368.9, 2368.9, 2368.9, 2481.0, 2705.1", \ + "2895.2, 2895.2, 2895.2, 3007.3, 3231.5", \ + "3946.2, 3946.2, 3946.2, 4058.3, 4282.4", \ + "6028.7, 6028.7, 6028.7, 6140.8, 6365.0"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1266.7, 1266.7, 1266.7, 1378.8, 1603.0", \ + "1467.4, 1467.4, 1467.4, 1579.5, 1803.7", \ + "1859.4, 1859.4, 1859.4, 1971.5, 2195.6", \ + "2628.8, 2628.8, 2628.8, 2740.9, 2965.0", \ + "4153.6, 4153.6, 4153.6, 4265.7, 4489.8"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1893.5, 1893.5, 1893.5, 2005.6, 2229.8", \ + "2222.5, 2222.5, 2222.5, 2334.6, 2558.7", \ + "2845.2, 2845.2, 2845.2, 2957.2, 3181.4", \ + "4056.2, 4056.2, 4056.2, 4168.3, 4392.5", \ + "6450.1, 6450.1, 6450.1, 6562.2, 6786.4"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1314.8, 1314.8, 1314.8, 1426.9, 1651.1", \ + "1492.9, 1492.9, 1492.9, 1605.0, 1829.1", \ + "1847.6, 1847.6, 1847.6, 1959.7, 2183.8", \ + "2550.5, 2550.5, 2550.5, 2662.6, 2886.7", \ + "3946.3, 3946.3, 3946.3, 4058.4, 4282.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2019.1, 2019.1, 2019.1, 2131.2, 2355.4", \ + "2432.1, 2432.1, 2432.1, 2544.2, 2768.3", \ + "3228.0, 3228.0, 3228.0, 3340.1, 3564.3", \ + "4789.1, 4789.1, 4789.1, 4901.2, 5125.3", \ + "7885.7, 7885.7, 7885.7, 7997.8, 8221.9"); + } + } + } + } + + cell (oa2a2a2a24_x2) { + area : 0.0 ; + cell_leakage_power : 0.0098 ; + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & !(i5) & i6 & !(i7)) | (!(i0) & i1 & ((i2 & !(i3) & i4 & !(i5) & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))))))" ; + value : 0.017 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))) | (!(i0) & i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))))" ; + value : 0.018 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7)))) | (!(i0) & ((i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))))))) | (!(i1) & ((i2 & !(i3) & i4 & !(i5) & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))))))))" ; + value : 0.013 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))))))" ; + value : 0.014 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i1) & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7))))))" ; + value : 0.0092 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))))))" ; + value : 0.0095 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7))))" ; + value : 0.0099 ; + } + leakage_power () { + when : "((i0 & i1) | (i2 & i3) | (i4 & i5) | (i6 & i7))" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7))))))))" ; + value : 0.0054 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))))" ; + value : 0.0057 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0015 ; + } + pin (i7) { + direction : input ; + capacitance : 22.40 ; + } + pin (i6) { + direction : input ; + capacitance : 29.26 ; + } + pin (i5) { + direction : input ; + capacitance : 22.48 ; + } + pin (i4) { + direction : input ; + capacitance : 22.13 ; + } + pin (i3) { + direction : input ; + capacitance : 21.77 ; + } + pin (i2) { + direction : input ; + capacitance : 22.13 ; + } + pin (i1) { + direction : input ; + capacitance : 21.77 ; + } + pin (i0) { + direction : input ; + capacitance : 22.40 ; + } + pin (q) { + function : "((i6 & ((i5 & ((i3 & ((i0 & i1) | i2 | i4 | i7)) | (i0 & i1) | i4 | i7)) | (i3 & ((i0 & i1) | i2 | i7)) | (i0 & i1) | i7)) | (i5 & ((i3 & ((i0 & i1) | i2 | i4)) | (i0 & i1) | i4)) | (i3 & ((i0 & i1) | i2)) | (i0 & i1))" ; + direction : output ; + capacitance : 5.22 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("58.0, 58.0, 58.0, 62.4, 70.1", \ + "66.4, 66.4, 66.4, 70.9, 79.0", \ + "79.5, 79.5, 79.5, 84.3, 92.9", \ + "102.1, 102.1, 102.1, 107.1, 116.5", \ + "146.3, 146.3, 146.3, 151.2, 161.0"); + } + rise_transition (inslew_load_5x5__46) { + values ("23.7, 23.7, 23.7, 27.2, 34.0", \ + "29.8, 29.8, 29.8, 33.4, 40.3", \ + "42.1, 42.1, 42.1, 45.7, 52.8", \ + "66.5, 66.5, 66.5, 70.1, 77.2", \ + "115.3, 115.3, 115.3, 119.2, 126.4"); + } + cell_fall (inslew_load_5x5__46) { + values ("105.0, 105.0, 105.0, 109.9, 119.3", \ + "107.5, 107.5, 107.5, 112.4, 121.9", \ + "112.3, 112.3, 112.3, 117.3, 126.9", \ + "120.3, 120.3, 120.3, 125.4, 135.2", \ + "134.7, 134.7, 134.7, 139.8, 149.8"); + } + fall_transition (inslew_load_5x5__46) { + values ("68.1, 68.1, 68.1, 71.8, 78.9", \ + "77.5, 77.5, 77.5, 81.2, 88.3", \ + "96.6, 96.6, 96.6, 100.3, 107.5", \ + "136.1, 136.1, 136.1, 139.7, 147.0", \ + "215.8, 215.8, 215.8, 219.4, 226.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("63.2, 63.2, 63.2, 67.5, 75.3", \ + "77.3, 77.3, 77.3, 81.8, 89.9", \ + "99.5, 99.5, 99.5, 104.3, 112.9", \ + "138.3, 138.3, 138.3, 143.4, 152.7", \ + "212.0, 212.0, 212.0, 216.9, 226.7"); + } + rise_transition (inslew_load_5x5__46) { + values ("23.1, 23.1, 23.1, 26.6, 33.4", \ + "29.9, 29.9, 29.9, 33.5, 40.4", \ + "43.2, 43.2, 43.2, 46.8, 53.9", \ + "69.3, 69.3, 69.3, 72.8, 80.0", \ + "120.6, 120.6, 120.6, 124.6, 131.8"); + } + cell_fall (inslew_load_5x5__46) { + values ("98.5, 98.5, 98.5, 103.4, 112.7", \ + "96.3, 96.3, 96.3, 101.3, 110.6", \ + "91.7, 91.7, 91.7, 96.7, 106.2", \ + "80.6, 80.6, 80.6, 85.6, 95.3", \ + "53.8, 53.8, 53.8, 58.9, 68.8"); + } + fall_transition (inslew_load_5x5__46) { + values ("64.1, 64.1, 64.1, 67.7, 74.9", \ + "70.7, 70.7, 70.7, 74.4, 81.5", \ + "84.8, 84.8, 84.8, 88.4, 95.6", \ + "114.0, 114.0, 114.0, 117.6, 124.9", \ + "171.4, 171.4, 171.4, 175.1, 182.3"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("53.7, 53.7, 53.7, 58.0, 65.6", \ + "57.0, 57.0, 57.0, 61.4, 69.3", \ + "59.0, 59.0, 59.0, 63.6, 72.1", \ + "57.7, 57.7, 57.7, 62.6, 71.6", \ + "50.3, 50.3, 50.3, 55.3, 65.0"); + } + rise_transition (inslew_load_5x5__46) { + values ("22.1, 22.1, 22.1, 25.6, 32.4", \ + "26.7, 26.7, 26.7, 30.3, 37.1", \ + "35.8, 35.8, 35.8, 39.4, 46.4", \ + "53.8, 53.8, 53.8, 57.4, 64.5", \ + "89.5, 89.5, 89.5, 93.2, 100.3"); + } + cell_fall (inslew_load_5x5__46) { + values ("101.6, 101.6, 101.6, 106.5, 115.8", \ + "111.4, 111.4, 111.4, 116.3, 125.8", \ + "129.1, 129.1, 129.1, 134.1, 143.7", \ + "161.4, 161.4, 161.4, 166.4, 176.2", \ + "222.8, 222.8, 222.8, 227.9, 237.9"); + } + fall_transition (inslew_load_5x5__46) { + values ("63.3, 63.3, 63.3, 67.0, 74.1", \ + "74.6, 74.6, 74.6, 78.2, 85.4", \ + "97.7, 97.7, 97.7, 101.3, 108.6", \ + "143.4, 143.4, 143.4, 147.1, 154.4", \ + "235.6, 235.6, 235.6, 239.2, 246.5"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("59.4, 59.4, 59.4, 63.7, 71.3", \ + "68.4, 68.4, 68.4, 72.8, 80.7", \ + "79.3, 79.3, 79.3, 84.0, 92.4", \ + "94.0, 94.0, 94.0, 98.9, 107.9", \ + "117.4, 117.4, 117.4, 122.4, 132.1"); + } + rise_transition (inslew_load_5x5__46) { + values ("21.8, 21.8, 21.8, 25.3, 32.0", \ + "27.2, 27.2, 27.2, 30.8, 37.6", \ + "37.5, 37.5, 37.5, 41.1, 48.1", \ + "57.8, 57.8, 57.8, 61.3, 68.4", \ + "97.5, 97.5, 97.5, 101.3, 108.4"); + } + cell_fall (inslew_load_5x5__46) { + values ("95.2, 95.2, 95.2, 100.1, 109.3", \ + "100.2, 100.2, 100.2, 105.1, 114.5", \ + "108.3, 108.3, 108.3, 113.2, 122.8", \ + "119.7, 119.7, 119.7, 124.7, 134.4", \ + "137.3, 137.3, 137.3, 142.3, 152.3"); + } + fall_transition (inslew_load_5x5__46) { + values ("59.5, 59.5, 59.5, 63.1, 70.2", \ + "68.0, 68.0, 68.0, 71.7, 78.8", \ + "86.0, 86.0, 86.0, 89.6, 96.8", \ + "121.1, 121.1, 121.1, 124.7, 132.0", \ + "191.7, 191.7, 191.7, 195.4, 202.7"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("49.3, 49.3, 49.3, 53.6, 60.8", \ + "53.9, 53.9, 53.9, 58.3, 66.0", \ + "56.2, 56.2, 56.2, 60.7, 68.9", \ + "53.5, 53.5, 53.5, 58.4, 67.2", \ + "42.1, 42.1, 42.1, 47.2, 56.7"); + } + rise_transition (inslew_load_5x5__46) { + values ("18.4, 18.4, 18.4, 21.9, 28.6", \ + "23.0, 23.0, 23.0, 26.5, 33.3", \ + "31.5, 31.5, 31.5, 35.1, 42.0", \ + "48.0, 48.0, 48.0, 51.6, 58.7", \ + "80.4, 80.4, 80.4, 84.0, 91.2"); + } + cell_fall (inslew_load_5x5__46) { + values ("84.9, 84.9, 84.9, 89.8, 98.9", \ + "94.4, 94.4, 94.4, 99.3, 108.5", \ + "112.6, 112.6, 112.6, 117.5, 127.0", \ + "141.3, 141.3, 141.3, 146.4, 156.1", \ + "192.7, 192.7, 192.7, 197.8, 207.7"); + } + fall_transition (inslew_load_5x5__46) { + values ("51.8, 51.8, 51.8, 55.4, 62.5", \ + "61.4, 61.4, 61.4, 65.0, 72.1", \ + "82.0, 82.0, 82.0, 85.7, 92.9", \ + "122.2, 122.2, 122.2, 125.8, 133.1", \ + "201.6, 201.6, 201.6, 205.2, 212.5"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("43.9, 43.9, 43.9, 48.2, 55.5", \ + "43.5, 43.5, 43.5, 47.8, 55.5", \ + "37.5, 37.5, 37.5, 42.0, 50.1", \ + "19.7, 19.7, 19.7, 24.5, 33.1", \ + "-21.5, -21.5, -21.5, -16.4, -7.0"); + } + rise_transition (inslew_load_5x5__46) { + values ("18.7, 18.7, 18.7, 22.2, 28.8", \ + "22.4, 22.4, 22.4, 25.9, 32.7", \ + "29.6, 29.6, 29.6, 33.2, 40.1", \ + "43.8, 43.8, 43.8, 47.4, 54.5", \ + "71.8, 71.8, 71.8, 75.3, 82.5"); + } + cell_fall (inslew_load_5x5__46) { + values ("91.1, 91.1, 91.1, 96.0, 105.1", \ + "105.5, 105.5, 105.5, 110.5, 119.8", \ + "133.8, 133.8, 133.8, 138.8, 148.3", \ + "185.4, 185.4, 185.4, 190.4, 200.2", \ + "283.3, 283.3, 283.3, 288.4, 298.4"); + } + fall_transition (inslew_load_5x5__46) { + values ("55.6, 55.6, 55.6, 59.2, 66.3", \ + "67.8, 67.8, 67.8, 71.4, 78.6", \ + "93.6, 93.6, 93.6, 97.2, 104.5", \ + "144.8, 144.8, 144.8, 148.4, 155.7", \ + "246.2, 246.2, 246.2, 249.8, 257.1"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("42.0, 42.0, 42.0, 46.2, 53.1", \ + "43.3, 43.3, 43.3, 47.6, 55.1", \ + "39.2, 39.2, 39.2, 43.6, 51.6", \ + "23.9, 23.9, 23.9, 28.6, 37.2", \ + "-13.0, -13.0, -13.0, -8.0, 1.4"); + } + rise_transition (inslew_load_5x5__46) { + values ("16.1, 16.1, 16.1, 19.6, 26.1", \ + "20.1, 20.1, 20.1, 23.6, 30.3", \ + "27.3, 27.3, 27.3, 30.9, 37.8", \ + "41.3, 41.3, 41.3, 44.9, 52.0", \ + "68.7, 68.7, 68.7, 72.3, 79.4"); + } + cell_fall (inslew_load_5x5__46) { + values ("68.6, 68.6, 68.6, 73.4, 82.3", \ + "83.3, 83.3, 83.3, 88.2, 97.3", \ + "107.7, 107.7, 107.7, 112.7, 122.1", \ + "149.7, 149.7, 149.7, 154.7, 164.4", \ + "227.9, 227.9, 227.9, 232.9, 242.9"); + } + fall_transition (inslew_load_5x5__46) { + values ("41.8, 41.8, 41.8, 45.4, 52.4", \ + "53.4, 53.4, 53.4, 57.0, 64.1", \ + "75.6, 75.6, 75.6, 79.3, 86.5", \ + "118.9, 118.9, 118.9, 122.6, 129.9", \ + "204.6, 204.6, 204.6, 208.3, 215.6"); + } + } + timing (maxd_q_i7_positive_unate) { + related_pin : "i7" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("37.2, 37.2, 37.2, 41.4, 48.4", \ + "33.9, 33.9, 33.9, 38.2, 45.6", \ + "22.4, 22.4, 22.4, 26.8, 34.7", \ + "-6.6, -6.6, -6.6, -1.8, 6.6", \ + "-70.6, -70.6, -70.6, -65.7, -56.6"); + } + rise_transition (inslew_load_5x5__46) { + values ("16.4, 16.4, 16.4, 19.8, 26.4", \ + "19.5, 19.5, 19.5, 23.1, 29.7", \ + "25.6, 25.6, 25.6, 29.2, 36.0", \ + "37.4, 37.4, 37.4, 41.0, 48.0", \ + "60.5, 60.5, 60.5, 64.1, 71.2"); + } + cell_fall (inslew_load_5x5__46) { + values ("74.6, 74.6, 74.6, 79.4, 88.4", \ + "93.0, 93.0, 93.0, 97.9, 107.1", \ + "129.0, 129.0, 129.0, 134.0, 143.5", \ + "193.8, 193.8, 193.8, 198.8, 208.6", \ + "318.7, 318.7, 318.7, 323.7, 333.7"); + } + fall_transition (inslew_load_5x5__46) { + values ("45.3, 45.3, 45.3, 49.0, 56.0", \ + "58.8, 58.8, 58.8, 62.5, 69.6", \ + "86.8, 86.8, 86.8, 90.5, 97.7", \ + "140.7, 140.7, 140.7, 144.4, 151.6", \ + "247.7, 247.7, 247.7, 251.3, 258.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__46) { + values ("1197.5, 1197.5, 1197.5, 1262.7, 1393.2", \ + "1480.2, 1480.2, 1480.2, 1545.4, 1675.9", \ + "2044.7, 2044.7, 2044.7, 2110.0, 2240.5", \ + "3172.6, 3172.6, 3172.6, 3237.9, 3368.4", \ + "5431.9, 5431.9, 5431.9, 5497.1, 5627.6"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("1687.2, 1687.2, 1687.2, 1752.4, 1882.9", \ + "1911.8, 1911.8, 1911.8, 1977.0, 2107.5", \ + "2365.0, 2365.0, 2365.0, 2430.3, 2560.8", \ + "3284.2, 3284.2, 3284.2, 3349.5, 3479.9", \ + "5131.4, 5131.4, 5131.4, 5196.6, 5327.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__46) { + values ("1132.1, 1132.1, 1132.1, 1197.3, 1327.8", \ + "1410.5, 1410.5, 1410.5, 1475.8, 1606.3", \ + "1962.9, 1962.9, 1962.9, 2028.2, 2158.7", \ + "3062.8, 3062.8, 3062.8, 3128.0, 3258.5", \ + "5258.9, 5258.9, 5258.9, 5324.2, 5454.7"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("1581.5, 1581.5, 1581.5, 1646.8, 1777.3", \ + "1738.2, 1738.2, 1738.2, 1803.4, 1933.9", \ + "2058.9, 2058.9, 2058.9, 2124.2, 2254.7", \ + "2713.2, 2713.2, 2713.2, 2778.5, 2909.0", \ + "4011.2, 4011.2, 4011.2, 4076.5, 4207.0"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__46) { + values ("1096.2, 1096.2, 1096.2, 1161.5, 1292.0", \ + "1288.8, 1288.8, 1288.8, 1354.0, 1484.5", \ + "1673.1, 1673.1, 1673.1, 1738.4, 1868.9", \ + "2439.8, 2439.8, 2439.8, 2505.1, 2635.6", \ + "3970.0, 3970.0, 3970.0, 4035.2, 4165.7"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("1568.3, 1568.3, 1568.3, 1633.5, 1764.0", \ + "1825.7, 1825.7, 1825.7, 1891.0, 2021.5", \ + "2348.1, 2348.1, 2348.1, 2413.4, 2543.9", \ + "3388.5, 3388.5, 3388.5, 3453.8, 3584.2", \ + "5476.3, 5476.3, 5476.3, 5541.6, 5672.1"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__46) { + values ("1043.9, 1043.9, 1043.9, 1109.2, 1239.7", \ + "1244.4, 1244.4, 1244.4, 1309.6, 1440.1", \ + "1640.3, 1640.3, 1640.3, 1705.5, 1836.0", \ + "2426.6, 2426.6, 2426.6, 2491.8, 2622.3", \ + "3993.9, 3993.9, 3993.9, 4059.2, 4189.7"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("1464.1, 1464.1, 1464.1, 1529.4, 1659.9", \ + "1654.7, 1654.7, 1654.7, 1719.9, 1850.4", \ + "2044.6, 2044.6, 2044.6, 2109.9, 2240.4", \ + "2816.1, 2816.1, 2816.1, 2881.4, 3011.9", \ + "4365.3, 4365.3, 4365.3, 4430.5, 4561.0"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__46) { + values ("847.4, 847.4, 847.4, 912.7, 1043.2", \ + "1001.5, 1001.5, 1001.5, 1066.7, 1197.2", \ + "1303.9, 1303.9, 1303.9, 1369.1, 1499.6", \ + "1902.9, 1902.9, 1902.9, 1968.1, 2098.6", \ + "3095.7, 3095.7, 3095.7, 3160.9, 3291.4"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("1272.4, 1272.4, 1272.4, 1337.7, 1468.2", \ + "1479.9, 1479.9, 1479.9, 1545.1, 1675.6", \ + "1912.0, 1912.0, 1912.0, 1977.3, 2107.8", \ + "2764.8, 2764.8, 2764.8, 2830.1, 2960.6", \ + "4461.2, 4461.2, 4461.2, 4526.5, 4657.0"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__46) { + values ("893.7, 893.7, 893.7, 959.0, 1089.5", \ + "1034.4, 1034.4, 1034.4, 1099.7, 1230.2", \ + "1314.5, 1314.5, 1314.5, 1379.8, 1510.3", \ + "1871.5, 1871.5, 1871.5, 1936.7, 2067.2", \ + "2981.4, 2981.4, 2981.4, 3046.7, 3177.2"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("1374.7, 1374.7, 1374.7, 1440.0, 1570.5", \ + "1648.6, 1648.6, 1648.6, 1713.8, 1844.3", \ + "2212.1, 2212.1, 2212.1, 2277.4, 2407.9", \ + "3335.3, 3335.3, 3335.3, 3400.6, 3531.1", \ + "5572.4, 5572.4, 5572.4, 5637.7, 5768.2"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__46) { + values ("711.4, 711.4, 711.4, 776.6, 907.1", \ + "835.2, 835.2, 835.2, 900.4, 1030.9", \ + "1076.7, 1076.7, 1076.7, 1142.0, 1272.5", \ + "1554.1, 1554.1, 1554.1, 1619.4, 1749.9", \ + "2503.4, 2503.4, 2503.4, 2568.7, 2699.2"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("1033.4, 1033.4, 1033.4, 1098.7, 1229.2", \ + "1265.7, 1265.7, 1265.7, 1330.9, 1461.4", \ + "1720.1, 1720.1, 1720.1, 1785.4, 1915.9", \ + "2617.5, 2617.5, 2617.5, 2682.8, 2813.3", \ + "4403.1, 4403.1, 4403.1, 4468.4, 4598.8"); + } + } + internal_power (energy_pos_q_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__46) { + values ("756.3, 756.3, 756.3, 821.5, 952.0", \ + "866.5, 866.5, 866.5, 931.8, 1062.2", \ + "1084.2, 1084.2, 1084.2, 1149.5, 1280.0", \ + "1515.9, 1515.9, 1515.9, 1581.1, 1711.6", \ + "2374.9, 2374.9, 2374.9, 2440.2, 2570.7"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("1130.7, 1130.7, 1130.7, 1196.0, 1326.5", \ + "1418.2, 1418.2, 1418.2, 1483.5, 1614.0", \ + "2004.7, 2004.7, 2004.7, 2070.0, 2200.5", \ + "3157.0, 3157.0, 3157.0, 3222.2, 3352.7", \ + "5453.1, 5453.1, 5453.1, 5518.3, 5648.8"); + } + } + } + } + + cell (oa2a2a2a24_x4) { + area : 0.0 ; + cell_leakage_power : 0.01 ; + leakage_power () { + when : "(i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7))))))))))" ; + value : 0.011 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & i0)" ; + value : 0.0067 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5 & !(i6) & i7))" ; + value : 0.019 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & !(i5) & i6 & !(i7)) | (!(i0) & i1 & ((i2 & !(i3) & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))) | (!(i2) & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 0.018 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))))) | (!(i0) & i1 & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7))))" ; + value : 0.015 ; + } + leakage_power () { + when : "(!(i0) & i1 & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7))))))))))" ; + value : 0.01 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & !(i0))" ; + value : 0.0063 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((i2 & !(i3) & i4 & !(i5) & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7))))))" ; + value : 0.013 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7))))" ; + value : 0.0093 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7))))))))" ; + value : 0.0096 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7)))" ; + value : 0.0099 ; + } + leakage_power () { + when : "((i0 & (i1 | (i2 & (i3 | (i4 & i5) | (i6 & i7))) | (!(i2) & ((i3 & ((i4 & (i5 | !((i6 ^ i7)))) | (!(i4) & ((!(i5) & i6) | (i6 & i7))))) | (!(i3) & ((i4 & (i5 | i6)) | (i6 & i7))))))) | (!(i0) & ((i1 & ((i2 & (i3 | (i4 & (i5 | !((i6 ^ i7)))) | (!(i4) & ((!(i5) & i6) | (i6 & i7))))) | (!(i2) & ((i3 & ((i4 & (i5 | !((i6 ^ i7)))) | (!(i4) & ((i5 & !((i6 ^ i7))) | (!(i5) & (i6 | i7)))))) | (!(i3) & ((i4 & (i5 | i6 | i7)) | (i5 & i6) | (i6 & i7))))))) | (!(i1) & ((i2 & (i3 | (i4 & (i5 | i7)) | (i5 & (i6 | i7)) | (i6 & i7))) | (i3 & ((i4 & (i5 | (i6 & i7))) | ((i5 | i6) & i7))) | (i4 & i5) | (i6 & i7))))))" ; + value : 0.014 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7))))))" ; + value : 0.0054 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7)))))" ; + value : 0.0058 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0016 ; + } + pin (i7) { + direction : input ; + capacitance : 22.40 ; + } + pin (i6) { + direction : input ; + capacitance : 21.77 ; + } + pin (i5) { + direction : input ; + capacitance : 22.13 ; + } + pin (i4) { + direction : input ; + capacitance : 22.13 ; + } + pin (i3) { + direction : input ; + capacitance : 21.77 ; + } + pin (i2) { + direction : input ; + capacitance : 21.77 ; + } + pin (i1) { + direction : input ; + capacitance : 21.85 ; + } + pin (i0) { + direction : input ; + capacitance : 21.85 ; + } + pin (q) { + function : "((i7 & ((i5 & ((i3 & ((i0 & i1) | i2 | i4 | i6)) | (i0 & i1) | i4 | i6)) | (i3 & ((i0 & i1) | i2 | i6)) | (i0 & i1) | i6)) | (i5 & ((i3 & ((i0 & i1) | i2 | i4)) | (i0 & i1) | i4)) | (i3 & ((i0 & i1) | i2)) | (i0 & i1))" ; + direction : output ; + capacitance : 9.25 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("66.0, 66.0, 66.0, 69.8, 76.6", \ + "73.8, 73.8, 73.8, 77.7, 84.6", \ + "85.6, 85.6, 85.6, 89.5, 96.8", \ + "103.8, 103.8, 103.8, 107.8, 115.4", \ + "137.3, 137.3, 137.3, 141.4, 149.3"); + } + rise_transition (inslew_load_5x5__47) { + values ("28.2, 28.2, 28.2, 31.3, 37.3", \ + "34.5, 34.5, 34.5, 37.6, 43.7", \ + "47.0, 47.0, 47.0, 50.2, 56.3", \ + "71.9, 71.9, 71.9, 75.1, 81.3", \ + "122.1, 122.1, 122.1, 125.3, 131.4"); + } + cell_fall (inslew_load_5x5__47) { + values ("128.6, 128.6, 128.6, 132.6, 140.4", \ + "133.3, 133.3, 133.3, 137.3, 145.2", \ + "142.2, 142.2, 142.2, 146.2, 154.1", \ + "159.4, 159.4, 159.4, 163.4, 171.4", \ + "192.2, 192.2, 192.2, 196.3, 204.3"); + } + fall_transition (inslew_load_5x5__47) { + values ("81.9, 81.9, 81.9, 84.8, 90.4", \ + "92.4, 92.4, 92.4, 95.3, 100.9", \ + "113.3, 113.3, 113.3, 116.2, 121.9", \ + "156.2, 156.2, 156.2, 159.1, 165.0", \ + "243.2, 243.2, 243.2, 246.1, 252.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("72.0, 72.0, 72.0, 75.7, 82.6", \ + "86.1, 86.1, 86.1, 89.9, 96.9", \ + "107.6, 107.6, 107.6, 111.5, 118.8", \ + "143.3, 143.3, 143.3, 147.2, 154.9", \ + "208.5, 208.5, 208.5, 212.6, 220.5"); + } + rise_transition (inslew_load_5x5__47) { + values ("27.8, 27.8, 27.8, 30.9, 36.9", \ + "34.9, 34.9, 34.9, 38.1, 44.1", \ + "48.9, 48.9, 48.9, 52.0, 58.1", \ + "76.2, 76.2, 76.2, 79.3, 85.6", \ + "130.3, 130.3, 130.3, 133.4, 139.6"); + } + cell_fall (inslew_load_5x5__47) { + values ("121.2, 121.2, 121.2, 125.3, 133.0", \ + "120.8, 120.8, 120.8, 124.8, 132.6", \ + "119.5, 119.5, 119.5, 123.5, 131.4", \ + "115.2, 115.2, 115.2, 119.2, 127.1", \ + "103.6, 103.6, 103.6, 107.6, 115.6"); + } + fall_transition (inslew_load_5x5__47) { + values ("77.5, 77.5, 77.5, 80.3, 85.9", \ + "84.8, 84.8, 84.8, 87.7, 93.3", \ + "99.8, 99.8, 99.8, 102.8, 108.3", \ + "131.2, 131.2, 131.2, 134.1, 139.9", \ + "195.2, 195.2, 195.2, 198.1, 204.0"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("72.4, 72.4, 72.4, 76.2, 83.1", \ + "77.6, 77.6, 77.6, 81.5, 88.4", \ + "83.3, 83.3, 83.3, 87.1, 94.4", \ + "87.5, 87.5, 87.5, 91.4, 99.1", \ + "88.8, 88.8, 88.8, 92.9, 100.7"); + } + rise_transition (inslew_load_5x5__47) { + values ("30.6, 30.6, 30.6, 33.7, 39.7", \ + "35.8, 35.8, 35.8, 39.0, 45.0", \ + "46.2, 46.2, 46.2, 49.4, 55.5", \ + "66.9, 66.9, 66.9, 70.1, 76.3", \ + "107.9, 107.9, 107.9, 111.0, 117.3"); + } + cell_fall (inslew_load_5x5__47) { + values ("122.5, 122.5, 122.5, 126.5, 134.3", \ + "131.5, 131.5, 131.5, 135.6, 143.4", \ + "147.7, 147.7, 147.7, 151.7, 159.6", \ + "176.8, 176.8, 176.8, 180.8, 188.8", \ + "229.6, 229.6, 229.6, 233.6, 241.6"); + } + fall_transition (inslew_load_5x5__47) { + values ("75.9, 75.9, 75.9, 78.8, 84.3", \ + "86.0, 86.0, 86.0, 88.9, 94.4", \ + "107.0, 107.0, 107.0, 109.9, 115.5", \ + "150.1, 150.1, 150.1, 153.0, 158.8", \ + "234.4, 234.4, 234.4, 237.3, 243.2"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("78.7, 78.7, 78.7, 82.5, 89.4", \ + "90.7, 90.7, 90.7, 94.6, 101.6", \ + "106.4, 106.4, 106.4, 110.3, 117.7", \ + "127.8, 127.8, 127.8, 131.7, 139.4", \ + "160.9, 160.9, 160.9, 165.1, 172.9"); + } + rise_transition (inslew_load_5x5__47) { + values ("30.3, 30.3, 30.3, 33.4, 39.4", \ + "36.4, 36.4, 36.4, 39.6, 45.6", \ + "48.5, 48.5, 48.5, 51.6, 57.7", \ + "71.7, 71.7, 71.7, 74.9, 81.1", \ + "117.5, 117.5, 117.5, 120.7, 126.9"); + } + cell_fall (inslew_load_5x5__47) { + values ("116.6, 116.6, 116.6, 120.7, 128.4", \ + "121.3, 121.3, 121.3, 125.4, 133.2", \ + "128.6, 128.6, 128.6, 132.6, 140.5", \ + "138.3, 138.3, 138.3, 142.3, 150.2", \ + "150.6, 150.6, 150.6, 154.7, 162.6"); + } + fall_transition (inslew_load_5x5__47) { + values ("72.3, 72.3, 72.3, 75.1, 80.7", \ + "79.9, 79.9, 79.9, 82.8, 88.3", \ + "96.1, 96.1, 96.1, 99.0, 104.6", \ + "128.6, 128.6, 128.6, 131.5, 137.3", \ + "194.0, 194.0, 194.0, 197.0, 202.8"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("68.8, 68.8, 68.8, 72.5, 79.3", \ + "76.8, 76.8, 76.8, 80.7, 87.6", \ + "84.1, 84.1, 84.1, 88.0, 95.2", \ + "88.2, 88.2, 88.2, 92.1, 99.7", \ + "85.8, 85.8, 85.8, 89.9, 97.6"); + } + rise_transition (inslew_load_5x5__47) { + values ("26.5, 26.5, 26.5, 29.6, 35.5", \ + "31.7, 31.7, 31.7, 34.9, 40.9", \ + "41.7, 41.7, 41.7, 44.9, 51.0", \ + "60.9, 60.9, 60.9, 64.0, 70.2", \ + "98.2, 98.2, 98.2, 101.3, 107.6"); + } + cell_fall (inslew_load_5x5__47) { + values ("107.7, 107.7, 107.7, 111.7, 119.4", \ + "117.1, 117.1, 117.1, 121.2, 128.9", \ + "134.7, 134.7, 134.7, 138.8, 146.6", \ + "162.4, 162.4, 162.4, 166.4, 174.3", \ + "208.0, 208.0, 208.0, 212.0, 220.0"); + } + fall_transition (inslew_load_5x5__47) { + values ("65.5, 65.5, 65.5, 68.3, 73.8", \ + "73.9, 73.9, 73.9, 76.7, 82.3", \ + "92.7, 92.7, 92.7, 95.6, 101.2", \ + "130.1, 130.1, 130.1, 133.0, 138.7", \ + "203.7, 203.7, 203.7, 206.6, 212.5"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("62.5, 62.5, 62.5, 66.2, 73.0", \ + "64.2, 64.2, 64.2, 68.0, 74.9", \ + "62.1, 62.1, 62.1, 66.0, 73.1", \ + "49.7, 49.7, 49.7, 53.6, 61.1", \ + "16.4, 16.4, 16.4, 20.5, 28.2"); + } + rise_transition (inslew_load_5x5__47) { + values ("26.8, 26.8, 26.8, 29.8, 35.8", \ + "30.9, 30.9, 30.9, 34.0, 40.0", \ + "39.3, 39.3, 39.3, 42.4, 48.5", \ + "55.6, 55.6, 55.6, 58.8, 65.0", \ + "87.8, 87.8, 87.8, 90.9, 97.2"); + } + cell_fall (inslew_load_5x5__47) { + values ("113.3, 113.3, 113.3, 117.4, 125.1", \ + "127.3, 127.3, 127.3, 131.4, 139.2", \ + "154.4, 154.4, 154.4, 158.4, 166.3", \ + "202.3, 202.3, 202.3, 206.3, 214.2", \ + "291.4, 291.4, 291.4, 295.5, 303.5"); + } + fall_transition (inslew_load_5x5__47) { + values ("69.0, 69.0, 69.0, 71.8, 77.4", \ + "79.9, 79.9, 79.9, 82.7, 88.3", \ + "103.6, 103.6, 103.6, 106.5, 112.1", \ + "150.8, 150.8, 150.8, 153.7, 159.5", \ + "244.7, 244.7, 244.7, 247.6, 253.5"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("61.9, 61.9, 61.9, 65.6, 72.3", \ + "67.0, 67.0, 67.0, 70.8, 77.6", \ + "68.2, 68.2, 68.2, 72.1, 79.2", \ + "59.8, 59.8, 59.8, 63.6, 71.1", \ + "31.7, 31.7, 31.7, 35.8, 43.4"); + } + rise_transition (inslew_load_5x5__47) { + values ("23.9, 23.9, 23.9, 27.0, 32.9", \ + "28.5, 28.5, 28.5, 31.6, 37.6", \ + "37.2, 37.2, 37.2, 40.4, 46.4", \ + "53.5, 53.5, 53.5, 56.7, 62.8", \ + "85.1, 85.1, 85.1, 88.3, 94.5"); + } + cell_fall (inslew_load_5x5__47) { + values ("93.7, 93.7, 93.7, 97.7, 105.3", \ + "105.8, 105.8, 105.8, 109.8, 117.5", \ + "133.2, 133.2, 133.2, 137.3, 145.1", \ + "174.2, 174.2, 174.2, 178.3, 186.1", \ + "246.2, 246.2, 246.2, 250.3, 258.3"); + } + fall_transition (inslew_load_5x5__47) { + values ("56.5, 56.5, 56.5, 59.3, 64.9", \ + "65.5, 65.5, 65.5, 68.4, 73.9", \ + "87.5, 87.5, 87.5, 90.4, 95.9", \ + "128.0, 128.0, 128.0, 130.9, 136.6", \ + "207.4, 207.4, 207.4, 210.3, 216.2"); + } + } + timing (maxd_q_i7_positive_unate) { + related_pin : "i7" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("55.8, 55.8, 55.8, 59.5, 66.2", \ + "55.1, 55.1, 55.1, 58.8, 65.7", \ + "47.8, 47.8, 47.8, 51.7, 58.6", \ + "24.3, 24.3, 24.3, 28.2, 35.5", \ + "-32.0, -32.0, -32.0, -28.1, -20.4"); + } + rise_transition (inslew_load_5x5__47) { + values ("24.1, 24.1, 24.1, 27.2, 33.1", \ + "27.7, 27.7, 27.7, 30.8, 36.7", \ + "34.8, 34.8, 34.8, 37.9, 44.0", \ + "48.5, 48.5, 48.5, 51.7, 57.8", \ + "75.2, 75.2, 75.2, 78.3, 84.6"); + } + cell_fall (inslew_load_5x5__47) { + values ("99.2, 99.2, 99.2, 103.2, 110.9", \ + "115.4, 115.4, 115.4, 119.4, 127.1", \ + "152.2, 152.2, 152.2, 156.2, 164.1", \ + "214.0, 214.0, 214.0, 218.1, 226.0", \ + "329.7, 329.7, 329.7, 333.7, 341.8"); + } + fall_transition (inslew_load_5x5__47) { + values ("59.9, 59.9, 59.9, 62.7, 68.3", \ + "71.1, 71.1, 71.1, 73.9, 79.5", \ + "97.7, 97.7, 97.7, 100.6, 106.2", \ + "147.8, 147.8, 147.8, 150.7, 156.5", \ + "246.9, 246.9, 246.9, 249.8, 255.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__47) { + values ("1856.7, 1856.7, 1856.7, 1972.4, 2203.7", \ + "2215.4, 2215.4, 2215.4, 2331.1, 2562.4", \ + "2930.9, 2930.9, 2930.9, 3046.6, 3278.0", \ + "4361.4, 4361.4, 4361.4, 4477.1, 4708.5", \ + "7227.3, 7227.3, 7227.3, 7343.0, 7574.4"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("3195.7, 3195.7, 3195.7, 3311.4, 3542.8", \ + "3591.6, 3591.6, 3591.6, 3707.3, 3938.6", \ + "4383.4, 4383.4, 4383.4, 4499.0, 4730.4", \ + "5992.6, 5992.6, 5992.6, 6108.3, 6339.6", \ + "9239.5, 9239.5, 9239.5, 9355.2, 9586.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__47) { + values ("1786.4, 1786.4, 1786.4, 1902.0, 2133.4", \ + "2157.5, 2157.5, 2157.5, 2273.1, 2504.5", \ + "2892.9, 2892.9, 2892.9, 3008.6, 3240.0", \ + "4351.1, 4351.1, 4351.1, 4466.8, 4698.1", \ + "7255.2, 7255.2, 7255.2, 7370.9, 7602.2"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("3015.3, 3015.3, 3015.3, 3131.0, 3362.4", \ + "3291.9, 3291.9, 3291.9, 3407.6, 3639.0", \ + "3851.3, 3851.3, 3851.3, 3967.0, 4198.4", \ + "5002.0, 5002.0, 5002.0, 5117.7, 5349.1", \ + "7334.5, 7334.5, 7334.5, 7450.1, 7681.5"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__47) { + values ("1833.2, 1833.2, 1833.2, 1948.9, 2180.2", \ + "2092.1, 2092.1, 2092.1, 2207.8, 2439.1", \ + "2609.9, 2609.9, 2609.9, 2725.6, 2956.9", \ + "3644.3, 3644.3, 3644.3, 3759.9, 3991.3", \ + "5703.2, 5703.2, 5703.2, 5818.9, 6050.3"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("2954.6, 2954.6, 2954.6, 3070.3, 3301.6", \ + "3327.1, 3327.1, 3327.1, 3442.7, 3674.1", \ + "4091.6, 4091.6, 4091.6, 4207.3, 4438.6", \ + "5647.2, 5647.2, 5647.2, 5762.9, 5994.3", \ + "8716.0, 8716.0, 8716.0, 8831.7, 9063.0"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__47) { + values ("1777.1, 1777.1, 1777.1, 1892.7, 2124.1", \ + "2056.1, 2056.1, 2056.1, 2171.8, 2403.2", \ + "2608.8, 2608.8, 2608.8, 2724.5, 2955.8", \ + "3696.4, 3696.4, 3696.4, 3812.1, 4043.4", \ + "5854.5, 5854.5, 5854.5, 5970.2, 6201.5"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("2808.4, 2808.4, 2808.4, 2924.1, 3155.4", \ + "3084.5, 3084.5, 3084.5, 3200.1, 3431.5", \ + "3659.7, 3659.7, 3659.7, 3775.4, 4006.7", \ + "4813.7, 4813.7, 4813.7, 4929.4, 5160.8", \ + "7132.4, 7132.4, 7132.4, 7248.1, 7479.5"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__47) { + values ("1532.5, 1532.5, 1532.5, 1648.2, 1879.5", \ + "1755.2, 1755.2, 1755.2, 1870.9, 2102.3", \ + "2188.5, 2188.5, 2188.5, 2304.2, 2535.5", \ + "3036.7, 3036.7, 3036.7, 3152.4, 3383.7", \ + "4712.3, 4712.3, 4712.3, 4828.0, 5059.4"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("2538.8, 2538.8, 2538.8, 2654.4, 2885.8", \ + "2840.3, 2840.3, 2840.3, 2956.0, 3187.3", \ + "3490.3, 3490.3, 3490.3, 3606.0, 3837.4", \ + "4785.2, 4785.2, 4785.2, 4900.8, 5132.2", \ + "7349.1, 7349.1, 7349.1, 7464.7, 7696.1"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__47) { + values ("1581.6, 1581.6, 1581.6, 1697.2, 1928.6", \ + "1775.2, 1775.2, 1775.2, 1890.9, 2122.3", \ + "2164.4, 2164.4, 2164.4, 2280.0, 2511.4", \ + "2933.5, 2933.5, 2933.5, 3049.2, 3280.5", \ + "4458.9, 4458.9, 4458.9, 4574.6, 4806.0"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("2682.7, 2682.7, 2682.7, 2798.3, 3029.7", \ + "3080.1, 3080.1, 3080.1, 3195.8, 3427.1", \ + "3920.2, 3920.2, 3920.2, 4035.9, 4267.2", \ + "5596.8, 5596.8, 5596.8, 5712.5, 5943.9", \ + "8938.6, 8938.6, 8938.6, 9054.3, 9285.6"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__47) { + values ("1365.0, 1365.0, 1365.0, 1480.7, 1712.1", \ + "1549.1, 1549.1, 1549.1, 1664.8, 1896.1", \ + "1905.5, 1905.5, 1905.5, 2021.2, 2252.6", \ + "2596.5, 2596.5, 2596.5, 2712.2, 2943.5", \ + "3955.8, 3955.8, 3955.8, 4071.5, 4302.8"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("2201.8, 2201.8, 2201.8, 2317.5, 2548.8", \ + "2519.4, 2519.4, 2519.4, 2635.1, 2866.4", \ + "3246.9, 3246.9, 3246.9, 3362.6, 3594.0", \ + "4624.8, 4624.8, 4624.8, 4740.5, 4971.8", \ + "7346.8, 7346.8, 7346.8, 7462.4, 7693.8"); + } + } + internal_power (energy_pos_q_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__47) { + values ("1411.7, 1411.7, 1411.7, 1527.4, 1758.8", \ + "1567.9, 1567.9, 1567.9, 1683.6, 1915.0", \ + "1878.6, 1878.6, 1878.6, 1994.2, 2225.6", \ + "2489.4, 2489.4, 2489.4, 2605.1, 2836.5", \ + "3694.0, 3694.0, 3694.0, 3809.7, 4041.1"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("2340.2, 2340.2, 2340.2, 2455.9, 2687.3", \ + "2743.0, 2743.0, 2743.0, 2858.7, 3090.0", \ + "3649.7, 3649.7, 3649.7, 3765.4, 3996.7", \ + "5393.8, 5393.8, 5393.8, 5509.5, 5740.8", \ + "8856.3, 8856.3, 8856.3, 8972.0, 9203.4"); + } + } + } + } + + cell (oa2ao222_x2) { + area : 0.0 ; + cell_leakage_power : 0.014 ; + leakage_power () { + when : "(!(i4) & i3 & i2 & !(i1) & i0)" ; + value : 0.023 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & i4) | (!(i0) & i1 & i2 & i3 & !(i4)))" ; + value : 0.022 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & !(i0))" ; + value : 0.021 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & !(i0))" ; + value : 0.0083 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & !(i4)) | (!(i0) & !(i1) & i2 & i3 & !(i4)))" ; + value : 0.016 ; + } + leakage_power () { + when : "((i0 & i1) | ((i2 | i3) & i4))" ; + value : 0.0076 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4)) | (!(i0) & !(i1) & (i2 ^ i3) & !(i4)))" ; + value : 0.0089 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & (i2 ^ i3) & !(i4)) | (!(i1) & !(i2) & !(i3) & i4)))" ; + value : 0.015 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0019 ; + } + pin (i4) { + direction : input ; + capacitance : 23.31 ; + } + pin (i3) { + direction : input ; + capacitance : 23.12 ; + } + pin (i2) { + direction : input ; + capacitance : 26.25 ; + } + pin (i1) { + direction : input ; + capacitance : 24.29 ; + } + pin (i0) { + direction : input ; + capacitance : 24.21 ; + } + pin (q) { + function : "((i4 & ((i0 & i1) | i3 | i2)) | (i0 & i1))" ; + direction : output ; + capacitance : 6.02 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("35.1, 35.1, 35.1, 39.2, 46.2", \ + "38.6, 38.6, 38.6, 42.8, 50.3", \ + "42.8, 42.8, 42.8, 47.3, 55.3", \ + "49.4, 49.4, 49.4, 53.8, 62.3", \ + "60.9, 60.9, 60.9, 65.5, 74.2"); + } + rise_transition (inslew_load_5x5__12) { + values ("18.2, 18.2, 18.2, 22.0, 29.2", \ + "24.7, 24.7, 24.7, 28.5, 35.8", \ + "37.5, 37.5, 37.5, 41.3, 48.8", \ + "62.6, 62.6, 62.6, 66.5, 74.2", \ + "112.8, 112.8, 112.8, 116.6, 124.3"); + } + cell_fall (inslew_load_5x5__12) { + values ("54.6, 54.6, 54.6, 59.0, 66.8", \ + "60.4, 60.4, 60.4, 64.7, 72.9", \ + "71.1, 71.1, 71.1, 75.5, 83.8", \ + "91.5, 91.5, 91.5, 95.9, 104.6", \ + "131.1, 131.1, 131.1, 135.6, 144.5"); + } + fall_transition (inslew_load_5x5__12) { + values ("34.5, 34.5, 34.5, 37.5, 43.2", \ + "44.4, 44.4, 44.4, 47.5, 53.2", \ + "64.4, 64.4, 64.4, 67.4, 73.4", \ + "103.9, 103.9, 103.9, 107.0, 113.0", \ + "183.4, 183.4, 183.4, 186.5, 192.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("38.7, 38.7, 38.7, 42.8, 49.7", \ + "46.7, 46.7, 46.7, 51.0, 58.5", \ + "59.4, 59.4, 59.4, 63.9, 72.0", \ + "82.3, 82.3, 82.3, 86.8, 95.3", \ + "126.3, 126.3, 126.3, 130.9, 139.7"); + } + rise_transition (inslew_load_5x5__12) { + values ("17.7, 17.7, 17.7, 21.5, 28.7", \ + "25.1, 25.1, 25.1, 28.9, 36.3", \ + "39.3, 39.3, 39.3, 43.2, 50.6", \ + "67.3, 67.3, 67.3, 71.2, 78.9", \ + "123.0, 123.0, 123.0, 126.8, 134.5"); + } + cell_fall (inslew_load_5x5__12) { + values ("47.9, 47.9, 47.9, 52.2, 60.0", \ + "48.9, 48.9, 48.9, 53.2, 61.2", \ + "49.8, 49.8, 49.8, 54.1, 62.4", \ + "49.6, 49.6, 49.6, 54.1, 62.6", \ + "47.5, 47.5, 47.5, 52.1, 60.9"); + } + fall_transition (inslew_load_5x5__12) { + values ("30.8, 30.8, 30.8, 33.7, 39.4", \ + "38.3, 38.3, 38.3, 41.3, 47.0", \ + "53.2, 53.2, 53.2, 56.2, 62.1", \ + "83.2, 83.2, 83.2, 86.3, 92.3", \ + "143.2, 143.2, 143.2, 146.2, 152.3"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("26.1, 26.1, 26.1, 30.1, 36.7", \ + "20.7, 20.7, 20.7, 24.8, 31.8", \ + "5.9, 5.9, 5.9, 10.2, 17.7", \ + "-28.2, -28.2, -28.2, -23.8, -15.6", \ + "-99.9, -99.9, -99.9, -95.4, -86.9"); + } + rise_transition (inslew_load_5x5__12) { + values ("14.8, 14.8, 14.8, 18.5, 25.6", \ + "18.6, 18.6, 18.6, 22.4, 29.6", \ + "25.8, 25.8, 25.8, 29.6, 37.0", \ + "39.8, 39.8, 39.8, 43.7, 51.1", \ + "67.2, 67.2, 67.2, 71.1, 78.8"); + } + cell_fall (inslew_load_5x5__12) { + values ("56.1, 56.1, 56.1, 60.4, 68.0", \ + "76.4, 76.4, 76.4, 80.7, 88.8", \ + "111.6, 111.6, 111.6, 116.0, 124.4", \ + "178.3, 178.3, 178.3, 182.8, 191.5", \ + "309.2, 309.2, 309.2, 313.8, 322.8"); + } + fall_transition (inslew_load_5x5__12) { + values ("29.7, 29.7, 29.7, 32.6, 38.3", \ + "43.2, 43.2, 43.2, 46.2, 52.0", \ + "68.7, 68.7, 68.7, 71.8, 77.8", \ + "118.9, 118.9, 118.9, 121.9, 127.9", \ + "218.5, 218.5, 218.5, 221.6, 227.7"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("30.1, 30.1, 30.1, 34.2, 40.9", \ + "28.1, 28.1, 28.1, 32.2, 39.4", \ + "20.2, 20.2, 20.2, 24.6, 32.3", \ + "1.5, 1.5, 1.5, 5.9, 14.3", \ + "-39.0, -39.0, -39.0, -34.5, -25.9"); + } + rise_transition (inslew_load_5x5__12) { + values ("16.3, 16.3, 16.3, 20.0, 27.2", \ + "21.0, 21.0, 21.0, 24.9, 32.1", \ + "30.2, 30.2, 30.2, 34.0, 41.4", \ + "48.1, 48.1, 48.1, 51.9, 59.4", \ + "83.4, 83.4, 83.4, 87.3, 95.0"); + } + cell_fall (inslew_load_5x5__12) { + values ("54.1, 54.1, 54.1, 58.4, 66.1", \ + "66.6, 66.6, 66.6, 70.8, 79.0", \ + "89.5, 89.5, 89.5, 93.9, 102.2", \ + "133.3, 133.3, 133.3, 137.8, 146.5", \ + "219.4, 219.4, 219.4, 224.0, 232.9"); + } + fall_transition (inslew_load_5x5__12) { + values ("31.4, 31.4, 31.4, 34.4, 40.1", \ + "42.7, 42.7, 42.7, 45.8, 51.5", \ + "65.2, 65.2, 65.2, 68.3, 74.3", \ + "109.9, 109.9, 109.9, 112.9, 119.0", \ + "199.1, 199.1, 199.1, 202.1, 208.1"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("29.7, 29.7, 29.7, 33.6, 40.3", \ + "31.2, 31.2, 31.2, 35.3, 42.4", \ + "30.4, 30.4, 30.4, 34.8, 42.5", \ + "25.9, 25.9, 25.9, 30.3, 38.7", \ + "15.2, 15.2, 15.2, 19.7, 28.3"); + } + rise_transition (inslew_load_5x5__12) { + values ("14.6, 14.6, 14.6, 18.3, 25.4", \ + "20.2, 20.2, 20.2, 24.0, 31.3", \ + "30.9, 30.9, 30.9, 34.7, 42.1", \ + "51.6, 51.6, 51.6, 55.5, 63.0", \ + "92.8, 92.8, 92.8, 96.6, 104.4"); + } + cell_fall (inslew_load_5x5__12) { + values ("37.1, 37.1, 37.1, 41.1, 48.2", \ + "44.5, 44.5, 44.5, 48.7, 56.3", \ + "55.8, 55.8, 55.8, 60.1, 68.3", \ + "75.9, 75.9, 75.9, 80.3, 88.7", \ + "113.8, 113.8, 113.8, 118.3, 127.0"); + } + fall_transition (inslew_load_5x5__12) { + values ("19.2, 19.2, 19.2, 22.1, 27.6", \ + "27.2, 27.2, 27.2, 30.1, 35.8", \ + "42.5, 42.5, 42.5, 45.5, 51.2", \ + "72.5, 72.5, 72.5, 75.5, 81.5", \ + "132.1, 132.1, 132.1, 135.2, 141.2"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__12) { + values ("966.4, 966.4, 966.4, 1041.7, 1192.3", \ + "1268.1, 1268.1, 1268.1, 1343.4, 1494.0", \ + "1870.0, 1870.0, 1870.0, 1945.3, 2095.9", \ + "3071.4, 3071.4, 3071.4, 3146.7, 3297.3", \ + "5472.4, 5472.4, 5472.4, 5547.7, 5698.4"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("1239.7, 1239.7, 1239.7, 1315.1, 1465.7", \ + "1574.8, 1574.8, 1574.8, 1650.2, 1800.8", \ + "2247.3, 2247.3, 2247.3, 2322.6, 2473.2", \ + "3587.3, 3587.3, 3587.3, 3662.6, 3813.2", \ + "6273.5, 6273.5, 6273.5, 6348.8, 6499.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__12) { + values ("889.9, 889.9, 889.9, 965.2, 1115.8", \ + "1201.3, 1201.3, 1201.3, 1276.6, 1427.2", \ + "1817.9, 1817.9, 1817.9, 1893.2, 2043.9", \ + "3047.6, 3047.6, 3047.6, 3122.9, 3273.6", \ + "5504.2, 5504.2, 5504.2, 5579.5, 5730.1"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("1092.3, 1092.3, 1092.3, 1167.6, 1318.3", \ + "1336.6, 1336.6, 1336.6, 1411.9, 1562.5", \ + "1824.7, 1824.7, 1824.7, 1900.1, 2050.7", \ + "2804.1, 2804.1, 2804.1, 2879.4, 3030.1", \ + "4762.5, 4762.5, 4762.5, 4837.8, 4988.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__12) { + values ("738.9, 738.9, 738.9, 814.2, 964.8", \ + "877.3, 877.3, 877.3, 952.6, 1103.2", \ + "1150.6, 1150.6, 1150.6, 1225.9, 1376.5", \ + "1692.2, 1692.2, 1692.2, 1767.5, 1918.1", \ + "2770.5, 2770.5, 2770.5, 2845.8, 2996.4"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("1029.5, 1029.5, 1029.5, 1104.8, 1255.4", \ + "1419.8, 1419.8, 1419.8, 1495.1, 1645.7", \ + "2180.2, 2180.2, 2180.2, 2255.5, 2406.1", \ + "3689.6, 3689.6, 3689.6, 3764.9, 3915.6", \ + "6701.8, 6701.8, 6701.8, 6777.2, 6927.8"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__12) { + values ("836.3, 836.3, 836.3, 911.6, 1062.2", \ + "1030.1, 1030.1, 1030.1, 1105.4, 1256.0", \ + "1414.0, 1414.0, 1414.0, 1489.3, 1639.9", \ + "2178.6, 2178.6, 2178.6, 2253.9, 2404.6", \ + "3704.7, 3704.7, 3704.7, 3780.0, 3930.6"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("1126.5, 1126.5, 1126.5, 1201.8, 1352.4", \ + "1489.5, 1489.5, 1489.5, 1564.8, 1715.5", \ + "2214.7, 2214.7, 2214.7, 2290.0, 2440.6", \ + "3661.0, 3661.0, 3661.0, 3736.3, 3886.9", \ + "6551.8, 6551.8, 6551.8, 6627.1, 6777.7"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__12) { + values ("691.2, 691.2, 691.2, 766.5, 917.1", \ + "902.1, 902.1, 902.1, 977.4, 1128.0", \ + "1317.7, 1317.7, 1317.7, 1393.0, 1543.6", \ + "2144.4, 2144.4, 2144.4, 2219.7, 2370.3", \ + "3794.9, 3794.9, 3794.9, 3870.2, 4020.9"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("785.3, 785.3, 785.3, 860.6, 1011.2", \ + "1048.9, 1048.9, 1048.9, 1124.2, 1274.8", \ + "1568.9, 1568.9, 1568.9, 1644.2, 1794.8", \ + "2603.5, 2603.5, 2603.5, 2678.8, 2829.4", \ + "4668.6, 4668.6, 4668.6, 4743.9, 4894.6"); + } + } + } + } + + cell (oa2ao222_x4) { + area : 0.0 ; + cell_leakage_power : 0.0077 ; + leakage_power () { + when : "(!(i4) & i3 & i2 & !(i1) & i0)" ; + value : 0.013 ; + } + leakage_power () { + when : "(!(i0) & i1 & (i2 ^ i3) & !(i4))" ; + value : 0.0086 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & !(i0))" ; + value : 0.0047 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & !(i4)) | (!(i0) & !(i1) & i2 & i3 & !(i4)))" ; + value : 0.0089 ; + } + leakage_power () { + when : "((i0 & (i1 | i4)) | (i1 & ((i2 & i3) | i4)) | ((i2 | i3) & i4))" ; + value : 0.012 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4)) | (!(i0) & !(i1) & (i2 ^ i3) & !(i4)))" ; + value : 0.005 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0083 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0011 ; + } + pin (i4) { + direction : input ; + capacitance : 21.29 ; + } + pin (i3) { + direction : input ; + capacitance : 34.28 ; + } + pin (i2) { + direction : input ; + capacitance : 22.99 ; + } + pin (i1) { + direction : input ; + capacitance : 21.29 ; + } + pin (i0) { + direction : input ; + capacitance : 21.92 ; + } + pin (q) { + function : "(((i3 | i2) & ((i0 & i1) | i4)) | (i0 & i1))" ; + direction : output ; + capacitance : 9.14 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__39) { + values ("68.7, 68.7, 68.7, 72.5, 79.5", \ + "78.7, 78.7, 78.7, 82.6, 89.9", \ + "94.9, 94.9, 94.9, 99.0, 106.6", \ + "123.1, 123.1, 123.1, 127.4, 135.3", \ + "177.3, 177.3, 177.3, 181.7, 190.1"); + } + rise_transition (inslew_load_5x5__39) { + values ("28.2, 28.2, 28.2, 31.4, 37.3", \ + "34.9, 34.9, 34.9, 38.1, 44.2", \ + "48.4, 48.4, 48.4, 51.5, 57.7", \ + "75.2, 75.2, 75.2, 78.3, 84.5", \ + "129.3, 129.3, 129.3, 132.4, 138.5"); + } + cell_fall (inslew_load_5x5__39) { + values ("86.4, 86.4, 86.4, 90.6, 98.5", \ + "88.0, 88.0, 88.0, 92.2, 100.1", \ + "89.2, 89.2, 89.2, 93.5, 101.6", \ + "88.4, 88.4, 88.4, 92.6, 100.9", \ + "81.6, 81.6, 81.6, 85.8, 94.3"); + } + fall_transition (inslew_load_5x5__39) { + values ("54.4, 54.4, 54.4, 57.4, 63.4", \ + "61.5, 61.5, 61.5, 64.6, 70.6", \ + "76.8, 76.8, 76.8, 79.8, 85.8", \ + "107.0, 107.0, 107.0, 110.0, 116.0", \ + "167.8, 167.8, 167.8, 170.8, 176.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__39) { + values ("74.3, 74.3, 74.3, 78.1, 85.0", \ + "90.5, 90.5, 90.5, 94.4, 101.7", \ + "116.4, 116.4, 116.4, 120.6, 128.2", \ + "161.3, 161.3, 161.3, 165.6, 173.6", \ + "245.6, 245.6, 245.6, 250.0, 258.5"); + } + rise_transition (inslew_load_5x5__39) { + values ("27.5, 27.5, 27.5, 30.7, 36.7", \ + "35.0, 35.0, 35.0, 38.2, 44.2", \ + "49.6, 49.6, 49.6, 52.7, 58.9", \ + "78.2, 78.2, 78.2, 81.3, 87.5", \ + "135.0, 135.0, 135.0, 138.1, 144.2"); + } + cell_fall (inslew_load_5x5__39) { + values ("81.7, 81.7, 81.7, 85.9, 93.7", \ + "79.9, 79.9, 79.9, 84.1, 92.0", \ + "74.0, 74.0, 74.0, 78.2, 86.2", \ + "57.3, 57.3, 57.3, 61.5, 69.7", \ + "16.6, 16.6, 16.6, 20.9, 29.3"); + } + fall_transition (inslew_load_5x5__39) { + values ("51.6, 51.6, 51.6, 54.6, 60.5", \ + "56.9, 56.9, 56.9, 59.9, 65.9", \ + "68.5, 68.5, 68.5, 71.5, 77.5", \ + "91.1, 91.1, 91.1, 94.2, 100.2", \ + "136.7, 136.7, 136.7, 139.7, 145.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__39) { + values ("57.5, 57.5, 57.5, 61.3, 68.1", \ + "59.1, 59.1, 59.1, 62.9, 69.9", \ + "56.7, 56.7, 56.7, 60.6, 67.9", \ + "44.7, 44.7, 44.7, 48.8, 56.5", \ + "13.1, 13.1, 13.1, 17.5, 25.6"); + } + rise_transition (inslew_load_5x5__39) { + values ("23.9, 23.9, 23.9, 27.0, 33.0", \ + "28.0, 28.0, 28.0, 31.1, 37.1", \ + "36.1, 36.1, 36.1, 39.2, 45.3", \ + "52.0, 52.0, 52.0, 55.1, 61.3", \ + "83.3, 83.3, 83.3, 86.3, 92.5"); + } + cell_fall (inslew_load_5x5__39) { + values ("90.7, 90.7, 90.7, 94.8, 102.6", \ + "108.6, 108.6, 108.6, 112.8, 120.7", \ + "136.0, 136.0, 136.0, 140.2, 148.4", \ + "181.5, 181.5, 181.5, 185.8, 194.1", \ + "264.3, 264.3, 264.3, 268.5, 276.9"); + } + fall_transition (inslew_load_5x5__39) { + values ("50.5, 50.5, 50.5, 53.6, 59.5", \ + "62.2, 62.2, 62.2, 65.2, 71.2", \ + "84.6, 84.6, 84.6, 87.6, 93.6", \ + "127.8, 127.8, 127.8, 130.8, 136.8", \ + "213.0, 213.0, 213.0, 216.1, 222.2"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__39) { + values ("62.3, 62.3, 62.3, 66.1, 73.0", \ + "67.1, 67.1, 67.1, 70.9, 78.0", \ + "71.8, 71.8, 71.8, 75.8, 83.3", \ + "75.3, 75.3, 75.3, 79.5, 87.3", \ + "76.5, 76.5, 76.5, 80.8, 89.1"); + } + rise_transition (inslew_load_5x5__39) { + values ("25.8, 25.8, 25.8, 28.9, 34.9", \ + "30.8, 30.8, 30.8, 33.9, 40.0", \ + "40.8, 40.8, 40.8, 43.9, 50.1", \ + "60.7, 60.7, 60.7, 63.8, 70.0", \ + "100.2, 100.2, 100.2, 103.2, 109.4"); + } + cell_fall (inslew_load_5x5__39) { + values ("86.1, 86.1, 86.1, 90.3, 98.1", \ + "95.3, 95.3, 95.3, 99.5, 107.4", \ + "109.7, 109.7, 109.7, 113.9, 122.0", \ + "132.7, 132.7, 132.7, 136.9, 145.2", \ + "172.5, 172.5, 172.5, 176.7, 185.1"); + } + fall_transition (inslew_load_5x5__39) { + values ("51.1, 51.1, 51.1, 54.2, 60.1", \ + "60.4, 60.4, 60.4, 63.4, 69.4", \ + "78.7, 78.7, 78.7, 81.8, 87.8", \ + "115.4, 115.4, 115.4, 118.5, 124.5", \ + "188.1, 188.1, 188.1, 191.2, 197.3"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__39) { + values ("64.1, 64.1, 64.1, 67.9, 74.7", \ + "74.7, 74.7, 74.7, 78.5, 85.6", \ + "88.5, 88.5, 88.5, 92.5, 100.0", \ + "108.5, 108.5, 108.5, 112.8, 120.6", \ + "141.9, 141.9, 141.9, 146.3, 154.6"); + } + rise_transition (inslew_load_5x5__39) { + values ("23.9, 23.9, 23.9, 27.0, 32.9", \ + "29.8, 29.8, 29.8, 33.0, 39.0", \ + "41.3, 41.3, 41.3, 44.4, 50.6", \ + "63.6, 63.6, 63.6, 66.7, 72.9", \ + "107.8, 107.8, 107.8, 110.8, 116.9"); + } + cell_fall (inslew_load_5x5__39) { + values ("63.2, 63.2, 63.2, 67.2, 74.7", \ + "70.6, 70.6, 70.6, 74.7, 82.4", \ + "76.7, 76.7, 76.7, 80.9, 88.8", \ + "79.0, 79.0, 79.0, 83.2, 91.3", \ + "74.1, 74.1, 74.1, 78.3, 86.7"); + } + fall_transition (inslew_load_5x5__39) { + values ("33.4, 33.4, 33.4, 36.4, 42.2", \ + "40.7, 40.7, 40.7, 43.7, 49.6", \ + "54.1, 54.1, 54.1, 57.1, 63.1", \ + "79.5, 79.5, 79.5, 82.5, 88.5", \ + "129.1, 129.1, 129.1, 132.1, 138.1"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1681.2, 1681.2, 1681.2, 1795.5, 2023.9", \ + "2037.7, 2037.7, 2037.7, 2151.9, 2380.3", \ + "2749.0, 2749.0, 2749.0, 2863.2, 3091.6", \ + "4171.0, 4171.0, 4171.0, 4285.2, 4513.7", \ + "7023.2, 7023.2, 7023.2, 7137.4, 7365.8"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("2255.0, 2255.0, 2255.0, 2369.2, 2597.7", \ + "2527.7, 2527.7, 2527.7, 2641.9, 2870.4", \ + "3094.3, 3094.3, 3094.3, 3208.5, 3437.0", \ + "4224.0, 4224.0, 4224.0, 4338.2, 4566.6", \ + "6491.2, 6491.2, 6491.2, 6605.4, 6833.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1610.1, 1610.1, 1610.1, 1724.3, 1952.7", \ + "1970.0, 1970.0, 1970.0, 2084.3, 2312.7", \ + "2681.9, 2681.9, 2681.9, 2796.1, 3024.5", \ + "4094.2, 4094.2, 4094.2, 4208.4, 4436.8", \ + "6909.1, 6909.1, 6909.1, 7023.3, 7251.7"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("2133.4, 2133.4, 2133.4, 2247.6, 2476.1", \ + "2329.1, 2329.1, 2329.1, 2443.3, 2671.7", \ + "2742.5, 2742.5, 2742.5, 2856.7, 3085.1", \ + "3557.0, 3557.0, 3557.0, 3671.2, 3899.6", \ + "5192.1, 5192.1, 5192.1, 5306.3, 5534.7"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1395.6, 1395.6, 1395.6, 1509.8, 1738.2", \ + "1583.6, 1583.6, 1583.6, 1697.8, 1926.3", \ + "1959.6, 1959.6, 1959.6, 2073.8, 2302.3", \ + "2704.7, 2704.7, 2704.7, 2818.9, 3047.3", \ + "4183.9, 4183.9, 4183.9, 4298.2, 4526.6"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("2031.2, 2031.2, 2031.2, 2145.4, 2373.8", \ + "2421.8, 2421.8, 2421.8, 2536.0, 2764.4", \ + "3181.9, 3181.9, 3181.9, 3296.1, 3524.5", \ + "4672.0, 4672.0, 4672.0, 4786.2, 5014.7", \ + "7628.5, 7628.5, 7628.5, 7742.7, 7971.1"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1517.7, 1517.7, 1517.7, 1632.0, 1860.4", \ + "1765.6, 1765.6, 1765.6, 1879.8, 2108.3", \ + "2262.4, 2262.4, 2262.4, 2376.6, 2605.0", \ + "3251.1, 3251.1, 3251.1, 3365.3, 3593.7", \ + "5222.6, 5222.6, 5222.6, 5336.8, 5565.2"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("2109.6, 2109.6, 2109.6, 2223.8, 2452.3", \ + "2442.2, 2442.2, 2442.2, 2556.4, 2784.9", \ + "3105.6, 3105.6, 3105.6, 3219.8, 3448.3", \ + "4432.5, 4432.5, 4432.5, 4546.7, 4775.1", \ + "7073.8, 7073.8, 7073.8, 7188.0, 7416.5"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1368.9, 1368.9, 1368.9, 1483.1, 1711.5", \ + "1637.4, 1637.4, 1637.4, 1751.6, 1980.1", \ + "2163.6, 2163.6, 2163.6, 2277.8, 2506.3", \ + "3203.1, 3203.1, 3203.1, 3317.3, 3545.8", \ + "5271.4, 5271.4, 5271.4, 5385.6, 5614.0"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("1583.1, 1583.1, 1583.1, 1697.3, 1925.8", \ + "1833.9, 1833.9, 1833.9, 1948.2, 2176.6", \ + "2310.9, 2310.9, 2310.9, 2425.1, 2653.6", \ + "3236.6, 3236.6, 3236.6, 3350.8, 3579.2", \ + "5061.5, 5061.5, 5061.5, 5175.7, 5404.2"); + } + } + } + } + + cell (oa3ao322_x2) { + area : 0.0 ; + cell_leakage_power : 0.0089 ; + leakage_power () { + when : "(i0 & i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 0.0095 ; + } + leakage_power () { + when : "(i6 & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 0.015 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 0.0047 ; + } + leakage_power () { + when : "(i0 & !(i1) & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 0.0093 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & i4 & i5 & !(i6)) | (!(i0) & i1 & i2 & i3 & i4 & i5 & !(i6)))" ; + value : 0.019 ; + } + leakage_power () { + when : "(!(i0) & i1 & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 0.0092 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i1) & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & ((i4 & i5 & !(i6)) | (!(i4) & !(i5) & i6))))))) | (!(i0) & i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & ((i4 & i5 & !(i6)) | (!(i4) & !(i5) & i6))))))" ; + value : 0.014 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & !(i4) & !(i5) & !(i6))" ; + value : 0.0044 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!(i0) & (i1 ^ i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))" ; + value : 0.0062 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & !(i6)))" ; + value : 0.0013 ; + } + leakage_power () { + when : "((!(i0) & !((i1 & i2)) & i3 & i4 & i5 & !(i6)) | (!(i1) & !(i2) & i3 & i4 & i5 & !(i6)))" ; + value : 0.016 ; + } + leakage_power () { + when : "((i0 & i1 & i2) | ((i3 | i4 | i5) & i6))" ; + value : 0.0065 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 0.006 ; + } + leakage_power () { + when : "((!(i0) & !((i1 & i2)) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & ((i4 & i5 & !(i6)) | (!(i4) & !(i5) & i6))))) | (!(i1) & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & ((i4 & i5 & !(i6)) | (!(i4) & !(i5) & i6))))))" ; + value : 0.011 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0012 ; + } + pin (i6) { + direction : input ; + capacitance : 23.18 ; + } + pin (i5) { + direction : input ; + capacitance : 21.13 ; + } + pin (i4) { + direction : input ; + capacitance : 21.13 ; + } + pin (i3) { + direction : input ; + capacitance : 21.13 ; + } + pin (i2) { + direction : input ; + capacitance : 19.67 ; + } + pin (i1) { + direction : input ; + capacitance : 20.30 ; + } + pin (i0) { + direction : input ; + capacitance : 21.00 ; + } + pin (q) { + function : "((i6 & ((i2 & i1 & i0) | i5 | i4 | i3)) | (i2 & i1 & i0))" ; + direction : output ; + capacitance : 5.80 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("72.2, 72.2, 72.2, 76.6, 84.8", \ + "81.6, 81.6, 81.6, 86.1, 94.4", \ + "98.3, 98.3, 98.3, 102.9, 111.5", \ + "129.1, 129.1, 129.1, 133.8, 142.9", \ + "190.6, 190.6, 190.6, 195.4, 204.8"); + } + rise_transition (inslew_load_5x5__48) { + values ("37.5, 37.5, 37.5, 41.3, 48.6", \ + "46.7, 46.7, 46.7, 50.5, 58.0", \ + "65.3, 65.3, 65.3, 69.1, 76.6", \ + "102.0, 102.0, 102.0, 105.9, 113.4", \ + "176.3, 176.3, 176.3, 180.2, 187.9"); + } + cell_fall (inslew_load_5x5__48) { + values ("90.9, 90.9, 90.9, 95.4, 104.1", \ + "92.8, 92.8, 92.8, 97.4, 106.1", \ + "96.6, 96.6, 96.6, 101.2, 110.0", \ + "102.6, 102.6, 102.6, 107.2, 116.2", \ + "113.1, 113.1, 113.1, 117.8, 127.0"); + } + fall_transition (inslew_load_5x5__48) { + values ("58.5, 58.5, 58.5, 61.7, 67.9", \ + "67.3, 67.3, 67.3, 70.6, 76.9", \ + "85.3, 85.3, 85.3, 88.6, 95.0", \ + "122.1, 122.1, 122.1, 125.4, 131.9", \ + "196.5, 196.5, 196.5, 199.8, 206.3"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("73.4, 73.4, 73.4, 77.8, 85.9", \ + "87.5, 87.5, 87.5, 92.0, 100.3", \ + "111.7, 111.7, 111.7, 116.3, 124.9", \ + "156.3, 156.3, 156.3, 161.0, 170.1", \ + "242.3, 242.3, 242.3, 247.1, 256.5"); + } + rise_transition (inslew_load_5x5__48) { + values ("35.6, 35.6, 35.6, 39.5, 46.7", \ + "45.4, 45.4, 45.4, 49.2, 56.6", \ + "64.3, 64.3, 64.3, 68.2, 75.7", \ + "102.0, 102.0, 102.0, 105.9, 113.5", \ + "177.1, 177.1, 177.1, 181.0, 188.7"); + } + cell_fall (inslew_load_5x5__48) { + values ("85.4, 85.4, 85.4, 90.0, 98.6", \ + "83.0, 83.0, 83.0, 87.5, 96.2", \ + "77.8, 77.8, 77.8, 82.4, 91.2", \ + "64.7, 64.7, 64.7, 69.3, 78.3", \ + "35.5, 35.5, 35.5, 40.1, 49.3"); + } + fall_transition (inslew_load_5x5__48) { + values ("55.2, 55.2, 55.2, 58.5, 64.6", \ + "61.5, 61.5, 61.5, 64.8, 71.0", \ + "74.6, 74.6, 74.6, 77.9, 84.2", \ + "101.7, 101.7, 101.7, 105.0, 111.5", \ + "155.2, 155.2, 155.2, 158.5, 165.0"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("76.3, 76.3, 76.3, 80.7, 88.9", \ + "95.9, 95.9, 95.9, 100.3, 108.7", \ + "128.7, 128.7, 128.7, 133.3, 141.9", \ + "188.0, 188.0, 188.0, 192.8, 201.9", \ + "302.1, 302.1, 302.1, 306.9, 316.3"); + } + rise_transition (inslew_load_5x5__48) { + values ("34.5, 34.5, 34.5, 38.3, 45.6", \ + "44.9, 44.9, 44.9, 48.7, 56.1", \ + "65.0, 65.0, 65.0, 68.8, 76.3", \ + "104.2, 104.2, 104.2, 108.1, 115.7", \ + "182.2, 182.2, 182.2, 186.1, 193.8"); + } + cell_fall (inslew_load_5x5__48) { + values ("80.6, 80.6, 80.6, 85.2, 93.7", \ + "75.5, 75.5, 75.5, 80.1, 88.7", \ + "64.6, 64.6, 64.6, 69.2, 77.9", \ + "40.3, 40.3, 40.3, 44.9, 53.8", \ + "-13.7, -13.7, -13.7, -9.0, 0.0"); + } + fall_transition (inslew_load_5x5__48) { + values ("52.3, 52.3, 52.3, 55.6, 61.7", \ + "57.1, 57.1, 57.1, 60.4, 66.6", \ + "67.4, 67.4, 67.4, 70.7, 76.9", \ + "89.0, 89.0, 89.0, 92.2, 98.7", \ + "130.7, 130.7, 130.7, 134.0, 140.5"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("41.4, 41.4, 41.4, 45.6, 52.7", \ + "39.0, 39.0, 39.0, 43.3, 50.8", \ + "27.7, 27.7, 27.7, 32.1, 40.0", \ + "-2.8, -2.8, -2.8, 1.7, 10.1", \ + "-71.9, -71.9, -71.9, -67.3, -58.6"); + } + rise_transition (inslew_load_5x5__48) { + values ("19.4, 19.4, 19.4, 23.1, 30.2", \ + "23.1, 23.1, 23.1, 26.8, 34.0", \ + "30.0, 30.0, 30.0, 33.8, 41.0", \ + "43.0, 43.0, 43.0, 46.8, 54.3", \ + "68.3, 68.3, 68.3, 72.1, 79.7"); + } + cell_fall (inslew_load_5x5__48) { + values ("86.4, 86.4, 86.4, 91.0, 99.5", \ + "109.8, 109.8, 109.8, 114.3, 123.1", \ + "150.4, 150.4, 150.4, 155.0, 163.8", \ + "222.9, 222.9, 222.9, 227.5, 236.6", \ + "362.0, 362.0, 362.0, 366.7, 375.9"); + } + fall_transition (inslew_load_5x5__48) { + values ("48.8, 48.8, 48.8, 52.0, 58.1", \ + "63.3, 63.3, 63.3, 66.5, 72.8", \ + "91.6, 91.6, 91.6, 94.9, 101.4", \ + "146.2, 146.2, 146.2, 149.4, 155.9", \ + "254.2, 254.2, 254.2, 257.4, 263.9"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("44.7, 44.7, 44.7, 48.9, 56.2", \ + "44.4, 44.4, 44.4, 48.8, 56.4", \ + "38.0, 38.0, 38.0, 42.4, 50.5", \ + "18.2, 18.2, 18.2, 22.7, 31.1", \ + "-28.2, -28.2, -28.2, -23.5, -14.6"); + } + rise_transition (inslew_load_5x5__48) { + values ("20.6, 20.6, 20.6, 24.4, 31.5", \ + "24.9, 24.9, 24.9, 28.7, 35.9", \ + "33.1, 33.1, 33.1, 36.9, 44.1", \ + "48.7, 48.7, 48.7, 52.5, 60.0", \ + "79.2, 79.2, 79.2, 83.1, 90.6"); + } + cell_fall (inslew_load_5x5__48) { + values ("85.9, 85.9, 85.9, 90.5, 99.0", \ + "101.3, 101.3, 101.3, 105.8, 114.6", \ + "129.0, 129.0, 129.0, 133.6, 142.5", \ + "180.5, 180.5, 180.5, 185.2, 194.2", \ + "279.8, 279.8, 279.8, 284.5, 293.7"); + } + fall_transition (inslew_load_5x5__48) { + values ("50.9, 50.9, 50.9, 54.1, 60.3", \ + "63.2, 63.2, 63.2, 66.4, 72.7", \ + "87.5, 87.5, 87.5, 90.8, 97.2", \ + "136.3, 136.3, 136.3, 139.5, 146.0", \ + "233.3, 233.3, 233.3, 236.5, 243.0"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("47.8, 47.8, 47.8, 52.1, 59.4", \ + "50.6, 50.6, 50.6, 55.1, 62.8", \ + "51.3, 51.3, 51.3, 55.7, 63.9", \ + "46.8, 46.8, 46.8, 51.4, 59.9", \ + "32.9, 32.9, 32.9, 37.6, 46.6"); + } + rise_transition (inslew_load_5x5__48) { + values ("21.9, 21.9, 21.9, 25.6, 32.8", \ + "27.1, 27.1, 27.1, 30.9, 38.1", \ + "37.2, 37.2, 37.2, 41.0, 48.3", \ + "56.8, 56.8, 56.8, 60.6, 68.1", \ + "95.5, 95.5, 95.5, 99.4, 107.0"); + } + cell_fall (inslew_load_5x5__48) { + values ("88.8, 88.8, 88.8, 93.4, 102.0", \ + "98.9, 98.9, 98.9, 103.5, 112.2", \ + "117.0, 117.0, 117.0, 121.6, 130.5", \ + "151.0, 151.0, 151.0, 155.7, 164.7", \ + "216.5, 216.5, 216.5, 221.2, 230.4"); + } + fall_transition (inslew_load_5x5__48) { + values ("54.8, 54.8, 54.8, 58.0, 64.2", \ + "65.8, 65.8, 65.8, 69.1, 75.3", \ + "88.3, 88.3, 88.3, 91.6, 98.0", \ + "133.0, 133.0, 133.0, 136.3, 142.8", \ + "223.1, 223.1, 223.1, 226.3, 232.8"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("43.1, 43.1, 43.1, 47.3, 54.4", \ + "47.5, 47.5, 47.5, 51.9, 59.5", \ + "51.0, 51.0, 51.0, 55.4, 63.6", \ + "52.6, 52.6, 52.6, 57.2, 65.7", \ + "51.9, 51.9, 51.9, 56.6, 65.7"); + } + rise_transition (inslew_load_5x5__48) { + values ("19.0, 19.0, 19.0, 22.7, 29.8", \ + "24.9, 24.9, 24.9, 28.6, 35.8", \ + "35.9, 35.9, 35.9, 39.7, 47.0", \ + "57.4, 57.4, 57.4, 61.2, 68.7", \ + "99.7, 99.7, 99.7, 103.6, 111.1"); + } + cell_fall (inslew_load_5x5__48) { + values ("49.0, 49.0, 49.0, 53.3, 61.1", \ + "57.5, 57.5, 57.5, 61.9, 70.0", \ + "68.4, 68.4, 68.4, 72.9, 81.4", \ + "85.0, 85.0, 85.0, 89.5, 98.4", \ + "114.0, 114.0, 114.0, 118.6, 127.7"); + } + fall_transition (inslew_load_5x5__48) { + values ("25.3, 25.3, 25.3, 28.4, 34.4", \ + "33.3, 33.3, 33.3, 36.4, 42.5", \ + "48.3, 48.3, 48.3, 51.4, 57.6", \ + "77.3, 77.3, 77.3, 80.6, 86.9", \ + "135.0, 135.0, 135.0, 138.2, 144.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__48) { + values ("1201.9, 1201.9, 1201.9, 1274.4, 1419.5", \ + "1481.4, 1481.4, 1481.4, 1554.0, 1699.0", \ + "2041.3, 2041.3, 2041.3, 2113.8, 2258.9", \ + "3157.2, 3157.2, 3157.2, 3229.7, 3374.8", \ + "5400.5, 5400.5, 5400.5, 5473.1, 5618.2"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("1491.4, 1491.4, 1491.4, 1564.0, 1709.0", \ + "1710.2, 1710.2, 1710.2, 1782.8, 1927.8", \ + "2151.4, 2151.4, 2151.4, 2223.9, 2369.0", \ + "3044.1, 3044.1, 3044.1, 3116.6, 3261.7", \ + "4839.7, 4839.7, 4839.7, 4912.3, 5057.3"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__48) { + values ("1136.3, 1136.3, 1136.3, 1208.8, 1353.9", \ + "1414.6, 1414.6, 1414.6, 1487.1, 1632.2", \ + "1965.1, 1965.1, 1965.1, 2037.7, 2182.7", \ + "3064.8, 3064.8, 3064.8, 3137.4, 3282.4", \ + "5260.7, 5260.7, 5260.7, 5333.2, 5478.3"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("1403.7, 1403.7, 1403.7, 1476.2, 1621.3", \ + "1556.7, 1556.7, 1556.7, 1629.2, 1774.3", \ + "1868.6, 1868.6, 1868.6, 1941.2, 2086.2", \ + "2505.5, 2505.5, 2505.5, 2578.0, 2723.1", \ + "3769.7, 3769.7, 3769.7, 3842.3, 3987.3"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__48) { + values ("1074.3, 1074.3, 1074.3, 1146.8, 1291.9", \ + "1351.7, 1351.7, 1351.7, 1424.2, 1569.3", \ + "1897.9, 1897.9, 1897.9, 1970.4, 2115.5", \ + "2980.7, 2980.7, 2980.7, 3053.2, 3198.3", \ + "5140.3, 5140.3, 5140.3, 5212.8, 5357.9"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("1326.7, 1326.7, 1326.7, 1399.2, 1544.3", \ + "1441.1, 1441.1, 1441.1, 1513.7, 1658.7", \ + "1679.4, 1679.4, 1679.4, 1751.9, 1897.0", \ + "2168.5, 2168.5, 2168.5, 2241.0, 2386.1", \ + "3130.0, 3130.0, 3130.0, 3202.6, 3347.6"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__48) { + values ("797.6, 797.6, 797.6, 870.2, 1015.2", \ + "898.0, 898.0, 898.0, 970.6, 1115.6", \ + "1093.5, 1093.5, 1093.5, 1166.1, 1311.1", \ + "1476.7, 1476.7, 1476.7, 1549.2, 1694.3", \ + "2234.2, 2234.2, 2234.2, 2306.7, 2451.8"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("1219.4, 1219.4, 1219.4, 1291.9, 1437.0", \ + "1529.6, 1529.6, 1529.6, 1602.2, 1747.2", \ + "2141.6, 2141.6, 2141.6, 2214.1, 2359.2", \ + "3338.9, 3338.9, 3338.9, 3411.5, 3556.5", \ + "5719.8, 5719.8, 5719.8, 5792.3, 5937.4"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__48) { + values ("861.0, 861.0, 861.0, 933.5, 1078.6", \ + "988.5, 988.5, 988.5, 1061.0, 1206.1", \ + "1239.3, 1239.3, 1239.3, 1311.8, 1456.9", \ + "1733.8, 1733.8, 1733.8, 1806.3, 1951.4", \ + "2715.7, 2715.7, 2715.7, 2788.2, 2933.3"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("1302.5, 1302.5, 1302.5, 1375.0, 1520.1", \ + "1585.2, 1585.2, 1585.2, 1657.7, 1802.8", \ + "2147.9, 2147.9, 2147.9, 2220.4, 2365.5", \ + "3275.1, 3275.1, 3275.1, 3347.6, 3492.7", \ + "5522.8, 5522.8, 5522.8, 5595.3, 5740.4"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__48) { + values ("925.2, 925.2, 925.2, 997.8, 1142.8", \ + "1096.8, 1096.8, 1096.8, 1169.4, 1314.4", \ + "1436.8, 1436.8, 1436.8, 1509.4, 1654.4", \ + "2111.5, 2111.5, 2111.5, 2184.0, 2329.1", \ + "3455.8, 3455.8, 3455.8, 3528.4, 3673.4"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("1399.7, 1399.7, 1399.7, 1472.2, 1617.3", \ + "1664.1, 1664.1, 1664.1, 1736.6, 1881.7", \ + "2198.6, 2198.6, 2198.6, 2271.1, 2416.2", \ + "3264.1, 3264.1, 3264.1, 3336.6, 3481.7", \ + "5403.2, 5403.2, 5403.2, 5475.7, 5620.8"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__48) { + values ("759.0, 759.0, 759.0, 831.5, 976.6", \ + "939.4, 939.4, 939.4, 1012.0, 1157.1", \ + "1293.3, 1293.3, 1293.3, 1365.9, 1511.0", \ + "1994.8, 1994.8, 1994.8, 2067.3, 2212.4", \ + "3392.3, 3392.3, 3392.3, 3464.8, 3609.9"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("860.1, 860.1, 860.1, 932.6, 1077.7", \ + "1068.2, 1068.2, 1068.2, 1140.8, 1285.8", \ + "1475.1, 1475.1, 1475.1, 1547.6, 1692.7", \ + "2279.4, 2279.4, 2279.4, 2352.0, 2497.0", \ + "3882.2, 3882.2, 3882.2, 3954.7, 4099.8"); + } + } + } + } + + cell (oa3ao322_x4) { + area : 0.0 ; + cell_leakage_power : 0.007 ; + leakage_power () { + when : "(i0 & i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 0.0071 ; + } + leakage_power () { + when : "(i0 & i1 & !(i2) & !(i3) & ((i4 & i5 & !(i6)) | (!(i4) & !(i5) & i6)))" ; + value : 0.01 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 0.0043 ; + } + leakage_power () { + when : "(i0 & ((i1 & !(i2) & i3 & (i4 ^ i5) & !(i6)) | (!(i1) & i2 & !(i3) & !(i4) & !(i5) & i6)))" ; + value : 0.0099 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & i4 & i5 & !(i6)) | (!(i0) & i1 & i2 & i3 & i4 & i5 & !(i6)))" ; + value : 0.013 ; + } + leakage_power () { + when : "(!(i0) & i1 & i2 & i3 & (i4 ^ i5) & !(i6))" ; + value : 0.0096 ; + } + leakage_power () { + when : "((i0 & !(i1) & i2 & i3 & (i4 ^ i5) & !(i6)) | (!(i0) & i1 & i2 & !(i3) & i4 & i5 & !(i6)))" ; + value : 0.0097 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & (i4 ^ i5) & !(i6))" ; + value : 0.0069 ; + } + leakage_power () { + when : "((i0 & !(i1) & i2 & !(i3) & i4 & i5 & !(i6)) | (!(i0) & i1 & i2 & !(i3) & !(i4) & !(i5) & i6))" ; + value : 0.0098 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & !(i4) & !(i5) & !(i6))" ; + value : 0.004 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & i5 & !(i6)) | (!(i0) & (i1 ^ i2) & i3 & i4 & i5 & !(i6)))" ; + value : 0.0095 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & (i4 ^ i5) & !(i6)) | (!(i0) & (i1 ^ i2) & i3 & (i4 ^ i5) & !(i6)))" ; + value : 0.0066 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & (i4 ^ i5) & !(i6)) | (!(i0) & (i1 ^ i2) & !(i3) & (i4 ^ i5) & !(i6)))" ; + value : 0.0038 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & i3 & !(i4) & !(i5) & !(i6)) | (!(i2) & !(i3) & !(i4) & !(i5) & i6))) | (!(i0) & ((i1 & ((i2 & i3 & !(i4) & !(i5) & !(i6)) | (!(i2) & !(i3) & !(i4) & !(i5) & i6))) | (!(i1) & i2 & !(i3) & !(i4) & !(i5) & i6))))" ; + value : 0.0068 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & !(i6)))" ; + value : 0.00095 ; + } + leakage_power () { + when : "(!(i6) & i5 & i4 & i3 & !(i2) & !(i1) & !(i0))" ; + value : 0.0093 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & i3 & !(i2) & !(i1) & !(i0))" ; + value : 0.0036 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 0.0065 ; + } + leakage_power () { + when : "((i0 & i1 & i2) | ((i3 | i4 | i5) & i6))" ; + value : 0.012 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & !(i4) & !(i5) & !(i6)) | (!(i0) & ((i1 & !(i2) & i3 & !(i4) & !(i5) & !(i6)) | (!(i1) & ((i2 & i3 & !(i4) & !(i5) & !(i6)) | (!(i2) & !(i3) & (i4 ^ i5) & !(i6)))))))" ; + value : 0.0037 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & i4 & i5 & !(i6)) | (!(i0) & ((i1 & !(i2) & !(i3) & i4 & i5 & !(i6)) | (!(i1) & ((i2 & !(i3) & i4 & i5 & !(i6)) | (!(i2) & !(i3) & !(i4) & !(i5) & i6))))))" ; + value : 0.0067 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0008 ; + } + pin (i6) { + direction : input ; + capacitance : 20.11 ; + } + pin (i5) { + direction : input ; + capacitance : 21.92 ; + } + pin (i4) { + direction : input ; + capacitance : 21.57 ; + } + pin (i3) { + direction : input ; + capacitance : 23.54 ; + } + pin (i2) { + direction : input ; + capacitance : 24.26 ; + } + pin (i1) { + direction : input ; + capacitance : 30.19 ; + } + pin (i0) { + direction : input ; + capacitance : 30.54 ; + } + pin (q) { + function : "((i6 & ((i0 & i1 & i2) | i5 | i4 | i3)) | (i0 & i1 & i2))" ; + direction : output ; + capacitance : 9.08 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("93.9, 93.9, 93.9, 98.0, 105.4", \ + "102.1, 102.1, 102.1, 106.2, 113.9", \ + "116.2, 116.2, 116.2, 120.4, 128.2", \ + "141.1, 141.1, 141.1, 145.4, 153.7", \ + "189.0, 189.0, 189.0, 193.3, 201.8"); + } + rise_transition (inslew_load_5x5__49) { + values ("44.8, 44.8, 44.8, 47.9, 54.0", \ + "52.4, 52.4, 52.4, 55.5, 61.7", \ + "67.9, 67.9, 67.9, 71.0, 77.2", \ + "99.5, 99.5, 99.5, 102.4, 108.6", \ + "162.3, 162.3, 162.3, 165.5, 171.6"); + } + cell_fall (inslew_load_5x5__49) { + values ("149.5, 149.5, 149.5, 153.7, 161.9", \ + "153.5, 153.5, 153.5, 157.7, 165.9", \ + "160.8, 160.8, 160.8, 165.0, 173.3", \ + "175.1, 175.1, 175.1, 179.3, 187.7", \ + "200.2, 200.2, 200.2, 204.4, 212.7"); + } + fall_transition (inslew_load_5x5__49) { + values ("95.5, 95.5, 95.5, 98.5, 104.5", \ + "105.5, 105.5, 105.5, 108.5, 114.5", \ + "125.3, 125.3, 125.3, 128.3, 134.3", \ + "166.5, 166.5, 166.5, 169.5, 175.5", \ + "250.3, 250.3, 250.3, 253.4, 259.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("95.7, 95.7, 95.7, 99.8, 107.2", \ + "109.2, 109.2, 109.2, 113.3, 120.9", \ + "131.7, 131.7, 131.7, 135.9, 143.8", \ + "170.9, 170.9, 170.9, 175.2, 183.5", \ + "246.0, 246.0, 246.0, 250.3, 258.8"); + } + rise_transition (inslew_load_5x5__49) { + values ("43.2, 43.2, 43.2, 46.4, 52.5", \ + "51.2, 51.2, 51.2, 54.3, 60.5", \ + "67.3, 67.3, 67.3, 70.4, 76.5", \ + "99.5, 99.5, 99.5, 102.4, 108.6", \ + "164.0, 164.0, 164.0, 167.2, 173.4"); + } + cell_fall (inslew_load_5x5__49) { + values ("143.6, 143.6, 143.6, 147.8, 156.0", \ + "142.7, 142.7, 142.7, 146.9, 155.1", \ + "140.3, 140.3, 140.3, 144.6, 152.8", \ + "134.1, 134.1, 134.1, 138.3, 146.7", \ + "117.6, 117.6, 117.6, 121.8, 130.2"); + } + fall_transition (inslew_load_5x5__49) { + values ("91.9, 91.9, 91.9, 94.9, 100.9", \ + "98.8, 98.8, 98.8, 101.8, 107.8", \ + "113.1, 113.1, 113.1, 116.1, 122.1", \ + "143.2, 143.2, 143.2, 146.2, 152.2", \ + "205.0, 205.0, 205.0, 208.1, 214.1"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("99.9, 99.9, 99.9, 104.0, 111.4", \ + "119.8, 119.8, 119.8, 123.9, 131.5", \ + "151.8, 151.8, 151.8, 156.0, 163.9", \ + "206.6, 206.6, 206.6, 211.0, 219.2", \ + "309.1, 309.1, 309.1, 313.3, 321.8"); + } + rise_transition (inslew_load_5x5__49) { + values ("42.4, 42.4, 42.4, 45.5, 51.6", \ + "51.2, 51.2, 51.2, 54.3, 60.4", \ + "68.3, 68.3, 68.3, 71.4, 77.5", \ + "102.0, 102.0, 102.0, 104.9, 111.1", \ + "168.7, 168.7, 168.7, 171.9, 178.1"); + } + cell_fall (inslew_load_5x5__49) { + values ("138.3, 138.3, 138.3, 142.5, 150.7", \ + "134.4, 134.4, 134.4, 138.7, 146.8", \ + "126.5, 126.5, 126.5, 130.8, 139.0", \ + "108.2, 108.2, 108.2, 112.5, 120.8", \ + "65.6, 65.6, 65.6, 69.8, 78.2"); + } + fall_transition (inslew_load_5x5__49) { + values ("88.5, 88.5, 88.5, 91.5, 97.5", \ + "93.8, 93.8, 93.8, 96.8, 102.8", \ + "104.8, 104.8, 104.8, 107.8, 113.8", \ + "128.6, 128.6, 128.6, 131.6, 137.6", \ + "176.2, 176.2, 176.2, 179.3, 185.3"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("73.0, 73.0, 73.0, 76.8, 83.9", \ + "73.9, 73.9, 73.9, 77.8, 85.0", \ + "69.8, 69.8, 69.8, 73.8, 81.3", \ + "51.1, 51.1, 51.1, 55.2, 62.9", \ + "1.2, 1.2, 1.2, 5.4, 13.5"); + } + rise_transition (inslew_load_5x5__49) { + values ("29.8, 29.8, 29.8, 33.0, 39.0", \ + "33.2, 33.2, 33.2, 36.3, 42.4", \ + "40.1, 40.1, 40.1, 43.2, 49.3", \ + "53.7, 53.7, 53.7, 56.8, 62.9", \ + "80.0, 80.0, 80.0, 83.1, 89.2"); + } + cell_fall (inslew_load_5x5__49) { + values ("141.4, 141.4, 141.4, 145.6, 153.7", \ + "165.9, 165.9, 165.9, 170.2, 178.3", \ + "207.5, 207.5, 207.5, 211.8, 220.1", \ + "278.0, 278.0, 278.0, 282.2, 290.6", \ + "405.5, 405.5, 405.5, 409.7, 418.0"); + } + fall_transition (inslew_load_5x5__49) { + values ("83.6, 83.6, 83.6, 86.6, 92.5", \ + "97.9, 97.9, 97.9, 100.9, 106.9", \ + "125.6, 125.6, 125.6, 128.6, 134.6", \ + "179.7, 179.7, 179.7, 182.8, 188.8", \ + "285.8, 285.8, 285.8, 289.0, 295.1"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("95.0, 95.0, 95.0, 99.0, 106.3", \ + "104.0, 104.0, 104.0, 108.1, 115.5", \ + "115.2, 115.2, 115.2, 119.3, 126.9", \ + "126.4, 126.4, 126.4, 130.7, 138.6", \ + "136.4, 136.4, 136.4, 140.7, 149.0"); + } + rise_transition (inslew_load_5x5__49) { + values ("37.6, 37.6, 37.6, 40.7, 46.8", \ + "42.5, 42.5, 42.5, 45.6, 51.8", \ + "52.5, 52.5, 52.5, 55.6, 61.8", \ + "72.3, 72.3, 72.3, 75.4, 81.5", \ + "111.2, 111.2, 111.2, 114.2, 120.3"); + } + cell_fall (inslew_load_5x5__49) { + values ("135.0, 135.0, 135.0, 139.2, 147.3", \ + "145.1, 145.1, 145.1, 149.3, 157.5", \ + "161.7, 161.7, 161.7, 165.9, 174.2", \ + "186.5, 186.5, 186.5, 190.7, 199.0", \ + "223.6, 223.6, 223.6, 227.8, 236.2"); + } + fall_transition (inslew_load_5x5__49) { + values ("82.5, 82.5, 82.5, 85.5, 91.5", \ + "90.8, 90.8, 90.8, 93.8, 99.8", \ + "108.4, 108.4, 108.4, 111.4, 117.4", \ + "144.2, 144.2, 144.2, 147.2, 153.2", \ + "214.3, 214.3, 214.3, 217.4, 223.5"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("99.1, 99.1, 99.1, 103.1, 110.5", \ + "111.2, 111.2, 111.2, 115.3, 122.8", \ + "129.1, 129.1, 129.1, 133.3, 141.0", \ + "155.5, 155.5, 155.5, 159.7, 167.8", \ + "198.3, 198.3, 198.3, 202.6, 211.0"); + } + rise_transition (inslew_load_5x5__49) { + values ("39.2, 39.2, 39.2, 42.3, 48.4", \ + "45.2, 45.2, 45.2, 48.3, 54.4", \ + "57.2, 57.2, 57.2, 60.3, 66.5", \ + "81.2, 81.2, 81.2, 84.3, 90.4", \ + "128.7, 128.7, 128.7, 131.8, 137.9"); + } + cell_fall (inslew_load_5x5__49) { + values ("137.2, 137.2, 137.2, 141.4, 149.6", \ + "141.1, 141.1, 141.1, 145.3, 153.4", \ + "147.0, 147.0, 147.0, 151.3, 159.5", \ + "153.5, 153.5, 153.5, 157.8, 166.1", \ + "157.4, 157.4, 157.4, 161.6, 170.0"); + } + fall_transition (inslew_load_5x5__49) { + values ("86.0, 86.0, 86.0, 89.0, 95.0", \ + "92.8, 92.8, 92.8, 95.8, 101.8", \ + "107.9, 107.9, 107.9, 110.9, 116.9", \ + "138.6, 138.6, 138.6, 141.6, 147.6", \ + "200.4, 200.4, 200.4, 203.5, 209.5"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("88.4, 88.4, 88.4, 92.3, 99.5", \ + "100.9, 100.9, 100.9, 104.9, 112.3", \ + "119.1, 119.1, 119.1, 123.3, 130.9", \ + "146.8, 146.8, 146.8, 151.1, 159.1", \ + "193.1, 193.1, 193.1, 197.4, 205.8"); + } + rise_transition (inslew_load_5x5__49) { + values ("34.6, 34.6, 34.6, 37.8, 43.8", \ + "40.8, 40.8, 40.8, 43.9, 50.0", \ + "53.1, 53.1, 53.1, 56.2, 62.4", \ + "77.5, 77.5, 77.5, 80.6, 86.7", \ + "125.7, 125.7, 125.7, 128.7, 134.9"); + } + cell_fall (inslew_load_5x5__49) { + values ("79.3, 79.3, 79.3, 83.4, 91.0", \ + "89.1, 89.1, 89.1, 93.2, 100.9", \ + "98.3, 98.3, 98.3, 102.5, 110.4", \ + "104.1, 104.1, 104.1, 108.3, 116.4", \ + "101.8, 101.8, 101.8, 106.0, 114.3"); + } + fall_transition (inslew_load_5x5__49) { + values ("42.3, 42.3, 42.3, 45.3, 51.2", \ + "49.8, 49.8, 49.8, 52.8, 58.7", \ + "63.4, 63.4, 63.4, 66.4, 72.4", \ + "89.1, 89.1, 89.1, 92.1, 98.1", \ + "138.7, 138.7, 138.7, 141.7, 147.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__49) { + values ("2049.1, 2049.1, 2049.1, 2162.6, 2389.6", \ + "2379.8, 2379.8, 2379.8, 2493.3, 2720.4", \ + "3046.7, 3046.7, 3046.7, 3160.2, 3387.3", \ + "4388.7, 4388.7, 4388.7, 4502.2, 4729.2", \ + "7074.1, 7074.1, 7074.1, 7187.6, 7414.7"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("3220.0, 3220.0, 3220.0, 3333.5, 3560.6", \ + "3545.0, 3545.0, 3545.0, 3658.5, 3885.6", \ + "4194.1, 4194.1, 4194.1, 4307.7, 4534.7", \ + "5524.2, 5524.2, 5524.2, 5637.7, 5864.7", \ + "8220.3, 8220.3, 8220.3, 8333.9, 8560.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__49) { + values ("1973.0, 1973.0, 1973.0, 2086.5, 2313.5", \ + "2304.3, 2304.3, 2304.3, 2417.8, 2644.8", \ + "2968.6, 2968.6, 2968.6, 3082.1, 3309.2", \ + "4295.6, 4295.6, 4295.6, 4409.1, 4636.2", \ + "6962.0, 6962.0, 6962.0, 7075.6, 7302.6"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("3092.8, 3092.8, 3092.8, 3206.3, 3433.3", \ + "3319.1, 3319.1, 3319.1, 3432.6, 3659.6", \ + "3777.8, 3777.8, 3777.8, 3891.3, 4118.3", \ + "4732.2, 4732.2, 4732.2, 4845.7, 5072.8", \ + "6678.2, 6678.2, 6678.2, 6791.7, 7018.8"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__49) { + values ("1906.7, 1906.7, 1906.7, 2020.2, 2247.2", \ + "2245.5, 2245.5, 2245.5, 2359.0, 2586.0", \ + "2914.4, 2914.4, 2914.4, 3027.9, 3254.9", \ + "4237.7, 4237.7, 4237.7, 4351.2, 4578.2", \ + "6879.4, 6879.4, 6879.4, 6992.9, 7220.0"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("2978.9, 2978.9, 2978.9, 3092.5, 3319.5", \ + "3149.7, 3149.7, 3149.7, 3263.2, 3490.3", \ + "3498.3, 3498.3, 3498.3, 3611.8, 3838.8", \ + "4236.9, 4236.9, 4236.9, 4350.4, 4577.5", \ + "5715.9, 5715.9, 5715.9, 5829.5, 6056.5"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__49) { + values ("1519.3, 1519.3, 1519.3, 1632.8, 1859.8", \ + "1651.1, 1651.1, 1651.1, 1764.6, 1991.7", \ + "1917.5, 1917.5, 1917.5, 2031.0, 2258.1", \ + "2445.5, 2445.5, 2445.5, 2559.0, 2786.0", \ + "3484.7, 3484.7, 3484.7, 3598.2, 3825.2"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("2768.3, 2768.3, 2768.3, 2881.8, 3108.9", \ + "3187.6, 3187.6, 3187.6, 3301.1, 3528.2", \ + "4007.7, 4007.7, 4007.7, 4121.2, 4348.3", \ + "5617.9, 5617.9, 5617.9, 5731.4, 5958.5", \ + "8796.9, 8796.9, 8796.9, 8910.4, 9137.4"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__49) { + values ("1739.4, 1739.4, 1739.4, 1852.9, 2079.9", \ + "1925.8, 1925.8, 1925.8, 2039.3, 2266.4", \ + "2300.9, 2300.9, 2300.9, 2414.4, 2641.4", \ + "3046.6, 3046.6, 3046.6, 3160.1, 3387.2", \ + "4522.5, 4522.5, 4522.5, 4636.0, 4863.1"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("2766.9, 2766.9, 2766.9, 2880.4, 3107.5", \ + "3020.1, 3020.1, 3020.1, 3133.6, 3360.6", \ + "3551.0, 3551.0, 3551.0, 3664.5, 3891.6", \ + "4622.6, 4622.6, 4622.6, 4736.1, 4963.2", \ + "6741.2, 6741.2, 6741.2, 6854.7, 7081.7"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__49) { + values ("1823.4, 1823.4, 1823.4, 1936.9, 2163.9", \ + "2057.8, 2057.8, 2057.8, 2171.3, 2398.3", \ + "2530.3, 2530.3, 2530.3, 2643.9, 2870.9", \ + "3472.8, 3472.8, 3472.8, 3586.3, 3813.4", \ + "5347.0, 5347.0, 5347.0, 5460.5, 5687.5"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("2888.5, 2888.5, 2888.5, 3002.0, 3229.0", \ + "3104.6, 3104.6, 3104.6, 3218.1, 3445.1", \ + "3568.4, 3568.4, 3568.4, 3682.0, 3909.0", \ + "4509.4, 4509.4, 4509.4, 4622.9, 4850.0", \ + "6401.1, 6401.1, 6401.1, 6514.6, 6741.7"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__49) { + values ("1606.5, 1606.5, 1606.5, 1720.0, 1947.0", \ + "1845.4, 1845.4, 1845.4, 1958.9, 2185.9", \ + "2324.8, 2324.8, 2324.8, 2438.4, 2665.4", \ + "3276.2, 3276.2, 3276.2, 3389.7, 3616.7", \ + "5165.9, 5165.9, 5165.9, 5279.4, 5506.4"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("1803.4, 1803.4, 1803.4, 1916.9, 2143.9", \ + "2037.5, 2037.5, 2037.5, 2151.0, 2378.0", \ + "2479.2, 2479.2, 2479.2, 2592.7, 2819.7", \ + "3328.2, 3328.2, 3328.2, 3441.7, 3668.7", \ + "4987.3, 4987.3, 4987.3, 5100.9, 5327.9"); + } + } + } + } + + cell (on12_x1) { + area : 0.0 ; + cell_leakage_power : 0.0049 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.0045 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.0049 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 0.0004 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.0098 ; + } + pin (i1) { + direction : input ; + capacitance : 21.16 ; + } + pin (i0) { + direction : input ; + capacitance : 26.94 ; + } + pin (q) { + function : "(!(i0) | i1)" ; + direction : output ; + capacitance : 6.73 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__50) { + values ("34.9, 34.9, 34.9, 40.0, 48.5", \ + "38.4, 38.4, 38.4, 43.9, 53.4", \ + "41.9, 41.9, 41.9, 48.0, 58.6", \ + "45.8, 45.8, 45.8, 52.4, 64.2", \ + "51.6, 51.6, 51.6, 58.4, 71.2"); + } + rise_transition (inslew_load_5x5__50) { + values ("17.4, 17.4, 17.4, 22.8, 33.3", \ + "23.1, 23.1, 23.1, 28.7, 39.4", \ + "33.9, 33.9, 33.9, 39.7, 50.7", \ + "55.1, 55.1, 55.1, 60.9, 72.3", \ + "96.9, 96.9, 96.9, 102.8, 114.6"); + } + cell_fall (inslew_load_5x5__50) { + values ("38.3, 38.3, 38.3, 44.3, 55.4", \ + "42.5, 42.5, 42.5, 48.9, 60.5", \ + "47.3, 47.3, 47.3, 54.0, 66.4", \ + "53.8, 53.8, 53.8, 60.8, 74.1", \ + "64.5, 64.5, 64.5, 71.8, 85.8"); + } + fall_transition (inslew_load_5x5__50) { + values ("25.3, 25.3, 25.3, 32.1, 45.7", \ + "31.8, 31.8, 31.8, 38.6, 52.2", \ + "44.2, 44.2, 44.2, 51.1, 64.7", \ + "68.4, 68.4, 68.4, 75.4, 89.2", \ + "116.3, 116.3, 116.3, 123.4, 137.3"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__50) { + values ("5.3, 5.3, 5.3, 11.5, 21.6", \ + "2.4, 2.4, 2.4, 9.5, 21.6", \ + "-4.1, -4.1, -4.1, 3.6, 17.6", \ + "-17.7, -17.7, -17.7, -9.4, 5.9", \ + "-44.9, -44.9, -44.9, -36.4, -20.0"); + } + rise_transition (inslew_load_5x5__50) { + values ("17.8, 17.8, 17.8, 23.7, 34.6", \ + "30.3, 30.3, 30.3, 36.4, 48.0", \ + "55.1, 55.1, 55.1, 61.4, 73.5", \ + "104.4, 104.4, 104.4, 110.8, 123.4", \ + "202.9, 202.9, 202.9, 209.5, 222.3"); + } + cell_fall (inslew_load_5x5__50) { + values ("15.4, 15.4, 15.4, 22.9, 36.0", \ + "21.3, 21.3, 21.3, 29.4, 44.1", \ + "32.1, 32.1, 32.1, 40.6, 56.6", \ + "53.0, 53.0, 53.0, 61.8, 78.7", \ + "94.4, 94.4, 94.4, 103.4, 120.9"); + } + fall_transition (inslew_load_5x5__50) { + values ("27.6, 27.6, 27.6, 34.9, 48.9", \ + "49.3, 49.3, 49.3, 56.7, 71.1", \ + "91.6, 91.6, 91.6, 99.2, 114.0", \ + "175.8, 175.8, 175.8, 183.5, 198.6", \ + "344.0, 344.0, 344.0, 351.7, 366.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__50) { + values ("723.0, 723.0, 723.0, 807.1, 975.3", \ + "935.0, 935.0, 935.0, 1019.1, 1187.4", \ + "1355.9, 1355.9, 1355.9, 1440.0, 1608.3", \ + "2194.2, 2194.2, 2194.2, 2278.3, 2446.6", \ + "3868.8, 3868.8, 3868.8, 3953.0, 4121.2"); + } + fall_power (energy_inslew_load_5x5__50) { + values ("751.2, 751.2, 751.2, 835.3, 1003.6", \ + "948.9, 948.9, 948.9, 1033.0, 1201.2", \ + "1341.0, 1341.0, 1341.0, 1425.1, 1593.4", \ + "2122.6, 2122.6, 2122.6, 2206.7, 2374.9", \ + "3683.5, 3683.5, 3683.5, 3767.6, 3935.9"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__50) { + values ("185.1, 185.1, 185.1, 269.2, 437.5", \ + "286.0, 286.0, 286.0, 370.2, 538.4", \ + "487.9, 487.9, 487.9, 572.1, 740.3", \ + "891.7, 891.7, 891.7, 975.9, 1144.1", \ + "1699.4, 1699.4, 1699.4, 1783.5, 1951.7"); + } + fall_power (energy_inslew_load_5x5__50) { + values ("247.2, 247.2, 247.2, 331.3, 499.6", \ + "410.3, 410.3, 410.3, 494.4, 662.7", \ + "736.5, 736.5, 736.5, 820.6, 988.9", \ + "1388.9, 1388.9, 1388.9, 1473.0, 1641.2", \ + "2693.6, 2693.6, 2693.6, 2777.7, 2946.0"); + } + } + } + } + + cell (on12_x4) { + area : 0.0 ; + cell_leakage_power : 0.012 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.012 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.0091 ; + } + leakage_power () { + when : "!(i0)" ; + value : 0.016 ; + } + pin (i1) { + direction : input ; + capacitance : 22.77 ; + } + pin (i0) { + direction : input ; + capacitance : 26.69 ; + } + pin (q) { + function : "(i1 | !(i0))" ; + direction : output ; + capacitance : 8.97 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("52.8, 52.8, 52.8, 56.5, 63.0", \ + "59.8, 59.8, 59.8, 63.6, 70.4", \ + "67.0, 67.0, 67.0, 71.0, 78.2", \ + "74.1, 74.1, 74.1, 78.3, 86.1", \ + "83.4, 83.4, 83.4, 87.8, 96.1"); + } + rise_transition (inslew_load_5x5__21) { + values ("17.2, 17.2, 17.2, 20.2, 26.0", \ + "21.9, 21.9, 21.9, 25.0, 30.8", \ + "30.9, 30.9, 30.9, 34.0, 40.0", \ + "48.4, 48.4, 48.4, 51.5, 57.6", \ + "82.9, 82.9, 82.9, 86.2, 92.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("85.5, 85.5, 85.5, 89.7, 97.6", \ + "92.6, 92.6, 92.6, 96.8, 104.8", \ + "103.5, 103.5, 103.5, 107.8, 116.0", \ + "119.4, 119.4, 119.4, 123.7, 132.1", \ + "144.9, 144.9, 144.9, 149.2, 157.8"); + } + fall_transition (inslew_load_5x5__21) { + values ("49.8, 49.8, 49.8, 53.0, 59.1", \ + "58.1, 58.1, 58.1, 61.3, 67.4", \ + "74.8, 74.8, 74.8, 78.0, 84.2", \ + "108.3, 108.3, 108.3, 111.4, 117.7", \ + "174.7, 174.7, 174.7, 177.8, 184.1"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("85.9, 85.9, 85.9, 89.6, 96.0", \ + "96.5, 96.5, 96.5, 100.2, 106.7", \ + "111.0, 111.0, 111.0, 114.8, 121.5", \ + "132.5, 132.5, 132.5, 136.4, 143.4", \ + "166.7, 166.7, 166.7, 170.9, 178.4"); + } + rise_transition (inslew_load_5x5__21) { + values ("16.5, 16.5, 16.5, 19.5, 25.2", \ + "18.2, 18.2, 18.2, 21.2, 27.0", \ + "21.3, 21.3, 21.3, 24.4, 30.2", \ + "27.2, 27.2, 27.2, 30.3, 36.3", \ + "38.5, 38.5, 38.5, 41.6, 47.7"); + } + cell_fall (inslew_load_5x5__21) { + values ("114.3, 114.3, 114.3, 118.5, 126.4", \ + "120.9, 120.9, 120.9, 125.1, 133.0", \ + "127.0, 127.0, 127.0, 131.2, 139.2", \ + "130.9, 130.9, 130.9, 135.2, 143.4", \ + "129.7, 129.7, 129.7, 134.1, 142.4"); + } + fall_transition (inslew_load_5x5__21) { + values ("47.5, 47.5, 47.5, 50.6, 56.7", \ + "51.0, 51.0, 51.0, 54.2, 60.3", \ + "57.2, 57.2, 57.2, 60.3, 66.4", \ + "69.1, 69.1, 69.1, 72.3, 78.5", \ + "92.1, 92.1, 92.1, 95.3, 101.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1423.9, 1423.9, 1423.9, 1536.0, 1760.1", \ + "1692.9, 1692.9, 1692.9, 1805.0, 2029.2", \ + "2224.0, 2224.0, 2224.0, 2336.1, 2560.2", \ + "3274.2, 3274.2, 3274.2, 3386.2, 3610.4", \ + "5369.0, 5369.0, 5369.0, 5481.1, 5705.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2148.2, 2148.2, 2148.2, 2260.3, 2484.5", \ + "2456.5, 2456.5, 2456.5, 2568.6, 2792.7", \ + "3077.4, 3077.4, 3077.4, 3189.5, 3413.6", \ + "4320.9, 4320.9, 4320.9, 4433.0, 4657.1", \ + "6797.4, 6797.4, 6797.4, 6909.4, 7133.6"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1840.7, 1840.7, 1840.7, 1952.8, 2176.9", \ + "2058.6, 2058.6, 2058.6, 2170.7, 2394.9", \ + "2487.3, 2487.3, 2487.3, 2599.4, 2823.6", \ + "3335.7, 3335.7, 3335.7, 3447.7, 3671.9", \ + "5018.1, 5018.1, 5018.1, 5130.1, 5354.3"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2499.9, 2499.9, 2499.9, 2612.0, 2836.1", \ + "2728.7, 2728.7, 2728.7, 2840.8, 3064.9", \ + "3161.8, 3161.8, 3161.8, 3273.9, 3498.1", \ + "4017.2, 4017.2, 4017.2, 4129.3, 4353.4", \ + "5703.9, 5703.9, 5703.9, 5815.9, 6040.1"); + } + } + } + } + + cell (one_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + pin (q) { + function : "1" ; + direction : output ; + capacitance : 3.13 ; + } + } + + cell (powmid_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + } + + cell (rowend_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + } + + cell (sff1r_x4) { + area : 0.0 ; + cell_leakage_power : 0.01 ; + leakage_power () { + when : "(!(q) & nrst & i & ck)" ; + value : 0.0058 ; + } + leakage_power () { + when : "(ck & i & !(nrst))" ; + value : 0.0025 ; + } + leakage_power () { + when : "(ck & !(i) & !(nrst))" ; + value : 0.0044 ; + } + leakage_power () { + when : "((ck & i & nrst & q) | (!(ck) & i & nrst & !(q)))" ; + value : 0.015 ; + } + leakage_power () { + when : "(q & !(nrst) & i & !(ck))" ; + value : 0.0097 ; + } + leakage_power () { + when : "((ck & !(i) & nrst & q) | (!(ck) & i & !(nrst) & !(q)))" ; + value : 0.019 ; + } + leakage_power () { + when : "((ck & !(i) & nrst & !(q)) | (!(ck) & nrst & q))" ; + value : 0.0077 ; + } + leakage_power () { + when : "(!(q) & nrst & !(i) & !(ck))" ; + value : 0.017 ; + } + leakage_power () { + when : "(q & !(nrst) & !(i) & !(ck))" ; + value : 0.006 ; + } + leakage_power () { + when : "(!(q) & !(nrst) & !(i) & !(ck))" ; + value : 0.016 ; + } + ff(iq,iq_neg) { + clocked_on : "ck" ; + next_state : "i" ; + clear : "!(nrst)" ; + + } + pin (nrst) { + direction : input ; + capacitance : 25.55 ; + internal_power (energy_nrst) { + rise_power (energy_inslew_5__0) { + values ("1313.1, 1419.3, 1631.7, 2056.6, 2906.3"); + } + fall_power (energy_inslew_5__0) { + values ("1268.9, 1313.3, 1402.2, 1579.9, 1935.3"); + } + } + } + pin (i) { + direction : input ; + capacitance : 19.54 ; + timing (i_ck_setup_rising) { + timing_type : setup_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("-193.6, -212.8, -241.9, -283.8, -340.9", \ + "-182.1, -201.3, -230.4, -272.3, -329.4", \ + "-165.5, -184.7, -213.8, -255.7, -312.8", \ + "-140.4, -159.6, -188.7, -230.6, -287.7", \ + "-97.4, -116.6, -145.7, -187.6, -244.7"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("-307.1, -325.2, -353.0, -394.7, -457.0", \ + "-301.5, -319.6, -347.4, -389.1, -451.4", \ + "-297.9, -316.0, -343.8, -385.5, -447.8", \ + "-299.3, -317.4, -345.2, -386.9, -449.2", \ + "-311.3, -329.4, -357.2, -398.9, -461.2"); + } + } + timing (i_ck_hold_rising) { + timing_type : hold_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("279.2, 298.4, 327.5, 369.4, 426.5", \ + "267.7, 286.9, 316.0, 357.9, 415.0", \ + "251.1, 270.3, 299.4, 341.3, 398.4", \ + "226.0, 245.2, 274.3, 316.2, 373.3", \ + "183.0, 202.2, 231.3, 273.2, 330.3"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("343.4, 361.5, 389.3, 431.0, 493.3", \ + "337.8, 355.9, 383.7, 425.4, 487.7", \ + "334.2, 352.3, 380.1, 421.8, 484.1", \ + "335.6, 353.7, 381.5, 423.2, 485.5", \ + "347.6, 365.7, 393.5, 435.2, 497.5"); + } + } + internal_power (energy_i) { + rise_power (energy_inslew_5__0) { + values ("1164.8, 1303.7, 1580.0, 2130.2, 3230.1"); + } + fall_power (energy_inslew_5__0) { + values ("1154.8, 1250.2, 1437.1, 1805.9, 2539.3"); + } + } + } + pin (ck) { + direction : input ; + capacitance : 22.71 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("4280.5, 4421.9, 4709.5, 5287.0, 6433.9"); + } + fall_power (energy_inslew_5__0) { + values ("4303.5, 4401.7, 4595.9, 4973.8, 5716.0"); + } + } + } + pin (q) { + function : "iq" ; + direction : output ; + capacitance : 32.64 ; + timing (maxd_q_ck_rising_edge) { + timing_type : rising_edge ; + related_pin : "ck" ; + cell_fall (inslew_load_5x5__51) { + values ("211.1, 211.1, 211.1, 224.6, 248.4", \ + "226.9, 226.9, 226.9, 240.4, 264.3", \ + "248.2, 248.2, 248.2, 261.7, 285.9", \ + "272.6, 272.6, 272.6, 286.3, 310.8", \ + "291.6, 291.6, 291.6, 305.5, 330.6"); + } + fall_transition (inslew_load_5x5__51) { + values ("57.0, 57.0, 57.0, 67.8, 88.4", \ + "58.4, 58.4, 58.4, 69.2, 89.8", \ + "61.1, 61.1, 61.1, 71.9, 92.6", \ + "66.1, 66.1, 66.1, 76.9, 97.7", \ + "73.9, 73.9, 73.9, 84.9, 105.8"); + } + cell_rise (inslew_load_5x5__51) { + values ("278.9, 278.9, 278.9, 290.8, 310.9", \ + "297.4, 297.4, 297.4, 309.3, 329.4", \ + "324.8, 324.8, 324.8, 336.7, 356.9", \ + "363.2, 363.2, 363.2, 375.2, 395.5", \ + "412.8, 412.8, 412.8, 424.9, 445.4"); + } + rise_transition (inslew_load_5x5__51) { + values ("42.5, 42.5, 42.5, 53.0, 72.8", \ + "42.6, 42.6, 42.6, 53.1, 72.9", \ + "43.0, 43.0, 43.0, 53.5, 73.3", \ + "43.8, 43.8, 43.8, 54.3, 74.1", \ + "45.2, 45.2, 45.2, 55.7, 75.6"); + } + } + internal_power (energy_nun_q_ck) { + related_pin : "ck" ; + rise_power (energy_inslew_load_5x5__51) { + values ("1647.2, 1647.2, 1647.2, 2055.1, 2871.0", \ + "1649.6, 1649.6, 1649.6, 2057.6, 2873.5", \ + "1657.1, 1657.1, 1657.1, 2065.1, 2881.0", \ + "1672.1, 1672.1, 1672.1, 2080.0, 2895.9", \ + "1699.5, 1699.5, 1699.5, 2107.5, 2923.4"); + } + fall_power (energy_inslew_load_5x5__51) { + values ("2020.0, 2020.0, 2020.0, 2427.9, 3243.8", \ + "2048.2, 2048.2, 2048.2, 2456.1, 3272.0", \ + "2105.4, 2105.4, 2105.4, 2513.3, 3329.2", \ + "2208.4, 2208.4, 2208.4, 2616.3, 3432.2", \ + "2372.9, 2372.9, 2372.9, 2780.9, 3596.8"); + } + } + } + } + + cell (sff1_x4) { + area : 0.0 ; + cell_leakage_power : 0.014 ; + leakage_power () { + when : "(q & i & ck)" ; + value : 0.017 ; + } + leakage_power () { + when : "(!(q) & i & ck)" ; + value : 0.007 ; + } + leakage_power () { + when : "(q & !(i) & ck)" ; + value : 0.023 ; + } + leakage_power () { + when : "(!(q) & !(i) & ck)" ; + value : 0.011 ; + } + ff(iq,iq_neg) { + clocked_on : "ck" ; + next_state : "i" ; + + } + pin (i) { + direction : input ; + capacitance : 21.88 ; + timing (i_ck_setup_rising) { + timing_type : setup_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("-155.9, -172.6, -196.4, -228.9, -277.3", \ + "-151.5, -168.2, -192.0, -224.5, -272.9", \ + "-148.7, -165.4, -189.2, -221.7, -270.1", \ + "-149.1, -165.8, -189.6, -222.1, -270.5", \ + "-155.8, -172.5, -196.3, -228.8, -277.2"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("-245.4, -261.0, -283.7, -316.8, -371.5", \ + "-236.6, -252.2, -274.9, -308.0, -362.7", \ + "-224.1, -239.7, -262.4, -295.5, -350.2", \ + "-204.5, -220.1, -242.8, -275.9, -330.6", \ + "-169.5, -185.1, -207.8, -240.9, -295.6"); + } + } + timing (i_ck_hold_rising) { + timing_type : hold_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("212.4, 229.1, 252.9, 285.4, 333.8", \ + "208.0, 224.7, 248.5, 281.0, 329.4", \ + "205.2, 221.9, 245.7, 278.2, 326.6", \ + "205.6, 222.3, 246.1, 278.6, 327.0", \ + "212.3, 229.0, 252.8, 285.3, 333.7"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("276.6, 292.2, 314.9, 348.0, 402.7", \ + "267.8, 283.4, 306.1, 339.2, 393.9", \ + "255.3, 270.9, 293.6, 326.7, 381.4", \ + "235.7, 251.3, 274.0, 307.1, 361.8", \ + "200.7, 216.3, 239.0, 272.1, 326.8"); + } + } + internal_power (energy_i) { + rise_power (energy_inslew_5__0) { + values ("1023.5, 1176.5, 1478.0, 2075.9, 3267.9"); + } + fall_power (energy_inslew_5__0) { + values ("1057.1, 1233.1, 1582.1, 2277.1, 3664.9"); + } + } + } + pin (ck) { + direction : input ; + capacitance : 20.44 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("4223.0, 4420.8, 4819.1, 5612.2, 7194.0"); + } + fall_power (energy_inslew_5__0) { + values ("4208.4, 4347.9, 4619.7, 5150.4, 6195.1"); + } + } + } + pin (q) { + function : "iq" ; + direction : output ; + capacitance : 35.35 ; + timing (maxd_q_ck_rising_edge) { + timing_type : rising_edge ; + related_pin : "ck" ; + cell_fall (inslew_load_5x5__52) { + values ("185.3, 185.3, 185.3, 199.7, 225.0", \ + "200.2, 200.2, 200.2, 214.6, 240.0", \ + "219.4, 219.4, 219.4, 233.9, 259.6", \ + "240.3, 240.3, 240.3, 255.0, 281.1", \ + "259.1, 259.1, 259.1, 274.0, 300.8"); + } + fall_transition (inslew_load_5x5__52) { + values ("56.9, 56.9, 56.9, 68.5, 90.7", \ + "58.6, 58.6, 58.6, 70.1, 92.4", \ + "61.6, 61.6, 61.6, 73.2, 95.5", \ + "66.8, 66.8, 66.8, 78.5, 100.9", \ + "75.2, 75.2, 75.2, 87.0, 109.6"); + } + cell_rise (inslew_load_5x5__52) { + values ("213.6, 213.6, 213.6, 225.1, 244.0", \ + "229.6, 229.6, 229.6, 241.2, 260.1", \ + "251.9, 251.9, 251.9, 263.6, 282.6", \ + "281.0, 281.0, 281.0, 292.7, 311.9", \ + "321.5, 321.5, 321.5, 333.4, 352.9"); + } + rise_transition (inslew_load_5x5__52) { + values ("32.1, 32.1, 32.1, 43.0, 63.6", \ + "32.3, 32.3, 32.3, 43.3, 63.9", \ + "32.8, 32.8, 32.8, 43.7, 64.3", \ + "33.5, 33.5, 33.5, 44.4, 65.1", \ + "34.8, 34.8, 34.8, 45.8, 66.6"); + } + } + internal_power (energy_nun_q_ck) { + related_pin : "ck" ; + rise_power (energy_inslew_load_5x5__52) { + values ("1437.8, 1437.8, 1437.8, 1879.7, 2763.5", \ + "1441.7, 1441.7, 1441.7, 1883.7, 2767.5", \ + "1450.2, 1450.2, 1450.2, 1892.1, 2776.0", \ + "1463.7, 1463.7, 1463.7, 1905.6, 2789.4", \ + "1489.6, 1489.6, 1489.6, 1931.6, 2815.4"); + } + fall_power (energy_inslew_load_5x5__52) { + values ("2012.4, 2012.4, 2012.4, 2454.3, 3338.1", \ + "2045.8, 2045.8, 2045.8, 2487.7, 3371.6", \ + "2109.2, 2109.2, 2109.2, 2551.1, 3434.9", \ + "2217.4, 2217.4, 2217.4, 2659.4, 3543.2", \ + "2393.5, 2393.5, 2393.5, 2835.4, 3719.2"); + } + } + } + } + + cell (sff2_x4) { + area : 0.0 ; + cell_leakage_power : 0.013 ; + leakage_power () { + when : "(!(q) & !(i1) & i0 & cmd & ck)" ; + value : 0.0092 ; + } + leakage_power () { + when : "(ck & cmd & i1 & q)" ; + value : 0.015 ; + } + leakage_power () { + when : "(ck & cmd & i1 & !(q))" ; + value : 0.0054 ; + } + leakage_power () { + when : "(q & !(i1) & !(i0) & cmd & ck)" ; + value : 0.019 ; + } + leakage_power () { + when : "(!(q) & !(i1) & !(i0) & cmd & ck)" ; + value : 0.0074 ; + } + leakage_power () { + when : "(ck & !(cmd) & i0 & q)" ; + value : 0.017 ; + } + leakage_power () { + when : "(ck & !(cmd) & i0 & !(q))" ; + value : 0.0073 ; + } + leakage_power () { + when : "(q & i1 & !(i0) & !(cmd) & ck)" ; + value : 0.023 ; + } + leakage_power () { + when : "(!(q) & i1 & !(i0) & !(cmd) & ck)" ; + value : 0.011 ; + } + leakage_power () { + when : "(ck & !((cmd ^ i0)) & !(i1) & q)" ; + value : 0.021 ; + } + leakage_power () { + when : "(!(q) & !(i1) & !(i0) & !(cmd) & ck)" ; + value : 0.0093 ; + } + ff(iq,iq_neg) { + clocked_on : "ck" ; + next_state : "((cmd & i1) | (!(cmd) & i0))" ; + + } + pin (i1) { + direction : input ; + capacitance : 16.98 ; + timing (i1_ck_setup_rising) { + timing_type : setup_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("-207.4, -226.0, -254.1, -294.4, -349.6", \ + "-196.6, -215.2, -243.3, -283.6, -338.8", \ + "-179.0, -197.6, -225.7, -266.0, -321.2", \ + "-149.1, -167.7, -195.8, -236.1, -291.3", \ + "-93.4, -112.0, -140.1, -180.4, -235.6"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("-318.7, -336.5, -363.7, -404.6, -466.1", \ + "-315.5, -333.3, -360.5, -401.4, -462.9", \ + "-313.3, -331.1, -358.3, -399.2, -460.7", \ + "-314.6, -332.4, -359.6, -400.5, -462.0", \ + "-323.3, -341.1, -368.3, -409.2, -470.7"); + } + } + timing (i1_ck_hold_rising) { + timing_type : hold_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("266.2, 284.8, 312.9, 353.2, 408.4", \ + "255.4, 274.0, 302.1, 342.4, 397.6", \ + "237.8, 256.4, 284.5, 324.8, 380.0", \ + "207.9, 226.5, 254.6, 294.9, 350.1", \ + "152.2, 170.8, 198.9, 239.2, 294.4"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("344.1, 361.9, 389.1, 430.0, 491.5", \ + "340.9, 358.7, 385.9, 426.8, 488.3", \ + "338.7, 356.5, 383.7, 424.6, 486.1", \ + "340.0, 357.8, 385.0, 425.9, 487.4", \ + "348.7, 366.5, 393.7, 434.6, 496.1"); + } + } + internal_power (energy_i1) { + rise_power (energy_inslew_5__0) { + values ("945.1, 1095.1, 1394.6, 1992.7, 3191.2"); + } + fall_power (energy_inslew_5__0) { + values ("938.6, 1038.3, 1237.6, 1633.8, 2424.0"); + } + } + } + pin (i0) { + direction : input ; + capacitance : 20.49 ; + timing (i0_ck_setup_rising) { + timing_type : setup_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("-207.4, -226.0, -254.1, -294.4, -349.6", \ + "-196.6, -215.2, -243.3, -283.6, -338.8", \ + "-179.0, -197.6, -225.7, -266.0, -321.2", \ + "-149.1, -167.7, -195.8, -236.1, -291.3", \ + "-93.4, -112.0, -140.1, -180.4, -235.6"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("-318.7, -336.5, -363.7, -404.6, -466.1", \ + "-315.5, -333.3, -360.5, -401.4, -462.9", \ + "-313.3, -331.1, -358.3, -399.2, -460.7", \ + "-314.6, -332.4, -359.6, -400.5, -462.0", \ + "-323.3, -341.1, -368.3, -409.2, -470.7"); + } + } + timing (i0_ck_hold_rising) { + timing_type : hold_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("266.2, 284.8, 312.9, 353.2, 408.4", \ + "255.4, 274.0, 302.1, 342.4, 397.6", \ + "237.8, 256.4, 284.5, 324.8, 380.0", \ + "207.9, 226.5, 254.6, 294.9, 350.1", \ + "152.2, 170.8, 198.9, 239.2, 294.4"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("344.1, 361.9, 389.1, 430.0, 491.5", \ + "340.9, 358.7, 385.9, 426.8, 488.3", \ + "338.7, 356.5, 383.7, 424.6, 486.1", \ + "340.0, 357.8, 385.0, 425.9, 487.4", \ + "348.7, 366.5, 393.7, 434.6, 496.1"); + } + } + internal_power (energy_i0) { + rise_power (energy_inslew_5__0) { + values ("945.1, 1095.1, 1394.6, 1992.7, 3191.2"); + } + fall_power (energy_inslew_5__0) { + values ("938.6, 1038.3, 1237.6, 1633.8, 2424.0"); + } + } + } + pin (cmd) { + direction : input ; + capacitance : 54.12 ; + timing (cmd_ck_setup_rising) { + timing_type : setup_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("-210.6, -229.2, -257.3, -297.6, -352.8", \ + "-200.2, -218.8, -246.9, -287.2, -342.4", \ + "-186.2, -204.8, -232.9, -273.2, -328.4", \ + "-165.7, -184.3, -212.4, -252.7, -307.9", \ + "-132.4, -151.0, -179.1, -219.4, -274.6"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("-187.4, -206.0, -234.1, -274.4, -329.6", \ + "-183.5, -202.1, -230.2, -270.5, -325.7", \ + "-182.9, -201.5, -229.6, -269.9, -325.1", \ + "-190.0, -208.6, -236.7, -277.0, -332.2", \ + "-212.8, -231.4, -259.5, -299.8, -355.0"); + } + } + timing (cmd_ck_hold_rising) { + timing_type : hold_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("297.9, 315.7, 342.9, 383.8, 445.3", \ + "284.2, 302.0, 329.2, 370.1, 431.6", \ + "263.9, 281.7, 308.9, 349.8, 411.3", \ + "231.6, 249.4, 276.6, 317.5, 379.0", \ + "173.7, 191.5, 218.7, 259.6, 321.1"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("341.3, 359.1, 386.3, 427.2, 488.7", \ + "334.0, 351.8, 379.0, 419.9, 481.4", \ + "327.1, 344.9, 372.1, 413.0, 474.5", \ + "321.5, 339.3, 366.5, 407.4, 468.9", \ + "318.1, 335.9, 363.1, 404.0, 465.5"); + } + } + internal_power (energy_cmd) { + rise_power (energy_inslew_5__0) { + values ("2133.6, 2289.4, 2597.6, 3208.6, 4427.9"); + } + fall_power (energy_inslew_5__0) { + values ("2064.1, 2156.0, 2335.6, 2690.6, 3396.0"); + } + } + } + pin (ck) { + direction : input ; + capacitance : 22.25 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("4026.9, 4168.5, 4456.4, 5033.7, 6180.3"); + } + fall_power (energy_inslew_5__0) { + values ("4038.5, 4136.8, 4330.7, 4707.9, 5449.1"); + } + } + } + pin (q) { + function : "iq" ; + direction : output ; + capacitance : 33.16 ; + timing (maxd_q_ck_rising_edge) { + timing_type : rising_edge ; + related_pin : "ck" ; + cell_fall (inslew_load_5x5__53) { + values ("215.0, 215.0, 215.0, 228.7, 252.9", \ + "231.0, 231.0, 231.0, 244.7, 269.1", \ + "252.7, 252.7, 252.7, 266.5, 291.2", \ + "278.4, 278.4, 278.4, 292.3, 317.3", \ + "300.3, 300.3, 300.3, 314.4, 340.0"); + } + fall_transition (inslew_load_5x5__53) { + values ("59.4, 59.4, 59.4, 70.3, 91.3", \ + "60.8, 60.8, 60.8, 71.7, 92.7", \ + "63.5, 63.5, 63.5, 74.5, 95.6", \ + "68.6, 68.6, 68.6, 79.6, 100.7", \ + "76.7, 76.7, 76.7, 87.8, 109.1"); + } + cell_rise (inslew_load_5x5__53) { + values ("259.8, 259.8, 259.8, 271.1, 289.6", \ + "277.6, 277.6, 277.6, 289.0, 307.6", \ + "303.8, 303.8, 303.8, 315.2, 333.9", \ + "340.2, 340.2, 340.2, 351.7, 370.5", \ + "386.7, 386.7, 386.7, 398.3, 417.4"); + } + rise_transition (inslew_load_5x5__53) { + values ("33.7, 33.7, 33.7, 44.0, 63.6", \ + "33.8, 33.8, 33.8, 44.2, 63.8", \ + "34.2, 34.2, 34.2, 44.6, 64.2", \ + "34.9, 34.9, 34.9, 45.4, 65.0", \ + "36.2, 36.2, 36.2, 46.7, 66.4"); + } + } + internal_power (energy_nun_q_ck) { + related_pin : "ck" ; + rise_power (energy_inslew_load_5x5__53) { + values ("1455.7, 1455.7, 1455.7, 1870.2, 2699.2", \ + "1459.2, 1459.2, 1459.2, 1873.7, 2702.7", \ + "1466.7, 1466.7, 1466.7, 1881.2, 2710.2", \ + "1480.7, 1480.7, 1480.7, 1895.2, 2724.1", \ + "1505.6, 1505.6, 1505.6, 1920.1, 2749.1"); + } + fall_power (energy_inslew_load_5x5__53) { + values ("2053.3, 2053.3, 2053.3, 2467.8, 3296.8", \ + "2081.5, 2081.5, 2081.5, 2496.0, 3325.0", \ + "2139.6, 2139.6, 2139.6, 2554.1, 3383.1", \ + "2244.3, 2244.3, 2244.3, 2658.8, 3487.8", \ + "2414.2, 2414.2, 2414.2, 2828.7, 3657.7"); + } + } + } + } + + cell (tie_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + } + + cell (xr2_x1) { + area : 0.0 ; + cell_leakage_power : 0.01 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.014 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 0.01 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.0065 ; + } + pin (i1) { + direction : input ; + capacitance : 47.83 ; + } + pin (i0) { + direction : input ; + capacitance : 39.32 ; + } + pin (q) { + function : "(i1 ^ i0)" ; + direction : output ; + capacitance : 8.88 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__54) { + values ("69.7, 69.7, 69.7, 79.3, 95.5", \ + "85.1, 85.1, 85.1, 95.5, 113.0", \ + "110.3, 110.3, 110.3, 121.4, 140.8", \ + "155.0, 155.0, 155.0, 167.0, 188.4", \ + "242.9, 242.9, 242.9, 255.5, 279.1"); + } + rise_transition (inslew_load_5x5__54) { + values ("32.0, 32.0, 32.0, 42.8, 63.4", \ + "40.7, 40.7, 40.7, 51.7, 72.7", \ + "57.3, 57.3, 57.3, 68.5, 90.1", \ + "89.7, 89.7, 89.7, 101.2, 123.5", \ + "154.5, 154.5, 154.5, 166.2, 189.2"); + } + cell_fall (inslew_load_5x5__54) { + values ("41.7, 41.7, 41.7, 51.2, 67.7", \ + "41.1, 41.1, 41.1, 51.0, 68.3", \ + "32.6, 32.6, 32.6, 43.1, 61.4", \ + "7.3, 7.3, 7.3, 18.4, 38.2", \ + "-51.4, -51.4, -51.4, -39.7, -18.3"); + } + fall_transition (inslew_load_5x5__54) { + values ("24.8, 24.8, 24.8, 34.7, 54.0", \ + "29.6, 29.6, 29.6, 39.7, 59.0", \ + "38.1, 38.1, 38.1, 48.2, 67.8", \ + "53.5, 53.5, 53.5, 63.8, 83.7", \ + "82.7, 82.7, 82.7, 93.2, 113.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__54) { + values ("46.0, 46.0, 46.0, 54.0, 67.7", \ + "52.4, 52.4, 52.4, 61.0, 76.0", \ + "60.6, 60.6, 60.6, 70.0, 86.6", \ + "72.9, 72.9, 72.9, 83.1, 101.5", \ + "94.4, 94.4, 94.4, 105.1, 125.3"); + } + rise_transition (inslew_load_5x5__54) { + values ("27.4, 27.4, 27.4, 37.6, 57.4", \ + "35.2, 35.2, 35.2, 45.7, 65.9", \ + "50.0, 50.0, 50.0, 60.7, 81.4", \ + "78.6, 78.6, 78.6, 89.5, 110.7", \ + "134.8, 134.8, 134.8, 146.0, 167.7"); + } + cell_fall (inslew_load_5x5__54) { + values ("44.1, 44.1, 44.1, 52.4, 67.5", \ + "47.8, 47.8, 47.8, 56.4, 72.1", \ + "50.4, 50.4, 50.4, 59.5, 76.2", \ + "51.2, 51.2, 51.2, 60.9, 78.8", \ + "49.4, 49.4, 49.4, 59.6, 78.9"); + } + fall_transition (inslew_load_5x5__54) { + values ("28.8, 28.8, 28.8, 38.4, 57.4", \ + "34.8, 34.8, 34.8, 44.4, 63.3", \ + "46.1, 46.1, 46.1, 55.8, 74.8", \ + "67.9, 67.9, 67.9, 77.7, 96.8", \ + "110.8, 110.8, 110.8, 120.7, 140.1"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__54) { + values ("16.2, 16.2, 16.2, 22.7, 34.9", \ + "13.9, 13.9, 13.9, 21.3, 34.8", \ + "7.8, 7.8, 7.8, 15.9, 31.2", \ + "-5.9, -5.9, -5.9, 2.9, 19.7", \ + "-34.3, -34.3, -34.3, -25.0, -7.0"); + } + rise_transition (inslew_load_5x5__54) { + values ("38.0, 38.0, 38.0, 47.4, 66.3", \ + "54.1, 54.1, 54.1, 63.7, 82.5", \ + "85.9, 85.9, 85.9, 95.7, 114.9", \ + "149.2, 149.2, 149.2, 159.2, 178.8", \ + "275.5, 275.5, 275.5, 285.6, 305.6"); + } + cell_fall (inslew_load_5x5__54) { + values ("28.1, 28.1, 28.1, 35.9, 50.6", \ + "36.2, 36.2, 36.2, 44.6, 60.4", \ + "51.0, 51.0, 51.0, 59.8, 76.8", \ + "79.6, 79.6, 79.6, 88.8, 106.7", \ + "136.3, 136.3, 136.3, 145.7, 164.2"); + } + fall_transition (inslew_load_5x5__54) { + values ("44.8, 44.8, 44.8, 54.3, 73.3", \ + "70.1, 70.1, 70.1, 79.6, 98.5", \ + "119.9, 119.9, 119.9, 129.4, 148.4", \ + "218.9, 218.9, 218.9, 228.5, 247.6", \ + "416.7, 416.7, 416.7, 426.4, 445.6"); + } + } + timing (maxd_q_i1_negative_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__54) { + values ("12.5, 12.5, 12.5, 19.3, 31.8", \ + "7.1, 7.1, 7.1, 14.9, 29.1", \ + "-6.0, -6.0, -6.0, 2.9, 19.3", \ + "-34.2, -34.2, -34.2, -24.2, -5.5", \ + "-91.9, -91.9, -91.9, -81.2, -60.8"); + } + rise_transition (inslew_load_5x5__54) { + values ("33.0, 33.0, 33.0, 42.5, 61.5", \ + "45.6, 45.6, 45.6, 55.4, 74.4", \ + "70.2, 70.2, 70.2, 80.3, 99.9", \ + "118.9, 118.9, 118.9, 129.2, 149.5", \ + "215.8, 215.8, 215.8, 226.3, 247.1"); + } + cell_fall (inslew_load_5x5__54) { + values ("30.4, 30.4, 30.4, 39.1, 55.2", \ + "43.1, 43.1, 43.1, 52.7, 70.5", \ + "66.2, 66.2, 66.2, 76.5, 95.9", \ + "110.9, 110.9, 110.9, 121.6, 142.3", \ + "199.3, 199.3, 199.3, 210.3, 231.8"); + } + fall_transition (inslew_load_5x5__54) { + values ("41.8, 41.8, 41.8, 51.6, 70.8", \ + "69.3, 69.3, 69.3, 79.2, 98.7", \ + "122.6, 122.6, 122.6, 132.6, 152.5", \ + "227.9, 227.9, 227.9, 238.1, 258.3", \ + "438.1, 438.1, 438.1, 448.3, 468.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__54) { + values ("840.7, 840.7, 840.7, 951.7, 1173.6", \ + "1045.0, 1045.0, 1045.0, 1156.0, 1377.9", \ + "1450.9, 1450.9, 1450.9, 1561.8, 1783.8", \ + "2259.6, 2259.6, 2259.6, 2370.5, 2592.5", \ + "3878.5, 3878.5, 3878.5, 3989.5, 4211.5"); + } + fall_power (energy_inslew_load_5x5__54) { + values ("738.8, 738.8, 738.8, 849.7, 1071.7", \ + "827.3, 827.3, 827.3, 938.3, 1160.2", \ + "998.5, 998.5, 998.5, 1109.5, 1331.4", \ + "1334.2, 1334.2, 1334.2, 1445.2, 1667.2", \ + "1998.5, 1998.5, 1998.5, 2109.4, 2331.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__54) { + values ("836.6, 836.6, 836.6, 947.6, 1169.5", \ + "1056.0, 1056.0, 1056.0, 1167.0, 1389.0", \ + "1491.6, 1491.6, 1491.6, 1602.6, 1824.5", \ + "2358.9, 2358.9, 2358.9, 2469.9, 2691.8", \ + "4090.9, 4090.9, 4090.9, 4201.9, 4423.9"); + } + fall_power (energy_inslew_load_5x5__54) { + values ("847.7, 847.7, 847.7, 958.7, 1180.6", \ + "1026.3, 1026.3, 1026.3, 1137.3, 1359.2", \ + "1379.7, 1379.7, 1379.7, 1490.7, 1712.6", \ + "2082.7, 2082.7, 2082.7, 2193.6, 2415.6", \ + "3486.0, 3486.0, 3486.0, 3597.0, 3818.9"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__54) { + values ("380.2, 380.2, 380.2, 491.2, 713.1", \ + "504.9, 504.9, 504.9, 615.9, 837.9", \ + "754.4, 754.4, 754.4, 865.4, 1087.3", \ + "1253.3, 1253.3, 1253.3, 1364.3, 1586.2", \ + "2251.1, 2251.1, 2251.1, 2362.1, 2584.0"); + } + fall_power (energy_inslew_load_5x5__54) { + values ("466.3, 466.3, 466.3, 577.3, 799.2", \ + "686.3, 686.3, 686.3, 797.3, 1019.3", \ + "1126.4, 1126.4, 1126.4, 1237.4, 1459.3", \ + "2006.6, 2006.6, 2006.6, 2117.6, 2339.5", \ + "3767.0, 3767.0, 3767.0, 3877.9, 4099.9"); + } + } + internal_power (energy_neg_q_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__54) { + values ("317.2, 317.2, 317.2, 428.2, 650.2", \ + "403.0, 403.0, 403.0, 514.0, 735.9", \ + "574.6, 574.6, 574.6, 685.6, 907.5", \ + "917.7, 917.7, 917.7, 1028.7, 1250.7", \ + "1604.0, 1604.0, 1604.0, 1715.0, 1937.0"); + } + fall_power (energy_inslew_load_5x5__54) { + values ("406.9, 406.9, 406.9, 517.9, 739.8", \ + "615.7, 615.7, 615.7, 726.7, 948.6", \ + "1033.4, 1033.4, 1033.4, 1144.4, 1366.3", \ + "1868.8, 1868.8, 1868.8, 1979.8, 2201.7", \ + "3539.6, 3539.6, 3539.6, 3650.6, 3872.6"); + } + } + } + } + + cell (xr2_x4) { + area : 0.0 ; + cell_leakage_power : 0.012 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 0.0091 ; + } + leakage_power () { + when : "(i0 ^ i1)" ; + value : 0.013 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.012 ; + } + pin (i1) { + direction : input ; + capacitance : 38.91 ; + } + pin (i0) { + direction : input ; + capacitance : 34.81 ; + } + pin (q) { + function : "(i0 ^ i1)" ; + direction : output ; + capacitance : 8.97 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("61.8, 61.8, 61.8, 65.7, 72.6", \ + "70.5, 70.5, 70.5, 74.4, 81.7", \ + "84.3, 84.3, 84.3, 88.5, 96.1", \ + "107.5, 107.5, 107.5, 111.9, 120.1", \ + "152.9, 152.9, 152.9, 157.1, 165.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("25.1, 25.1, 25.1, 28.2, 34.1", \ + "31.4, 31.4, 31.4, 34.5, 40.5", \ + "43.9, 43.9, 43.9, 47.0, 53.1", \ + "68.9, 68.9, 68.9, 72.0, 78.0", \ + "118.8, 118.8, 118.8, 122.1, 128.4"); + } + cell_fall (inslew_load_5x5__21) { + values ("62.8, 62.8, 62.8, 66.9, 74.6", \ + "65.9, 65.9, 65.9, 70.1, 77.9", \ + "68.1, 68.1, 68.1, 72.4, 80.4", \ + "66.6, 66.6, 66.6, 70.9, 79.1", \ + "57.5, 57.5, 57.5, 61.8, 70.3"); + } + fall_transition (inslew_load_5x5__21) { + values ("37.1, 37.1, 37.1, 40.2, 46.2", \ + "43.9, 43.9, 43.9, 47.0, 53.1", \ + "57.6, 57.6, 57.6, 60.8, 66.9", \ + "84.5, 84.5, 84.5, 87.7, 93.9", \ + "137.6, 137.6, 137.6, 140.7, 147.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("53.1, 53.1, 53.1, 56.8, 63.6", \ + "56.3, 56.3, 56.3, 60.2, 67.2", \ + "58.5, 58.5, 58.5, 62.6, 69.9", \ + "57.5, 57.5, 57.5, 61.8, 69.6", \ + "50.7, 50.7, 50.7, 55.0, 63.4"); + } + rise_transition (inslew_load_5x5__21) { + values ("21.9, 21.9, 21.9, 25.0, 30.8", \ + "26.5, 26.5, 26.5, 29.7, 35.6", \ + "35.9, 35.9, 35.9, 39.0, 45.0", \ + "54.4, 54.4, 54.4, 57.3, 63.4", \ + "90.7, 90.7, 90.7, 94.1, 100.0"); + } + cell_fall (inslew_load_5x5__21) { + values ("67.1, 67.1, 67.1, 71.3, 79.0", \ + "78.8, 78.8, 78.8, 83.0, 90.8", \ + "94.8, 94.8, 94.8, 99.1, 107.1", \ + "119.0, 119.0, 119.0, 123.3, 131.7", \ + "160.6, 160.6, 160.6, 165.0, 173.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("35.8, 35.8, 35.8, 38.9, 44.9", \ + "45.1, 45.1, 45.1, 48.2, 54.3", \ + "62.7, 62.7, 62.7, 65.8, 72.0", \ + "96.7, 96.7, 96.7, 99.9, 106.1", \ + "163.8, 163.8, 163.8, 166.9, 173.1"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("93.8, 93.8, 93.8, 97.5, 104.3", \ + "98.9, 98.9, 98.9, 102.7, 109.5", \ + "100.7, 100.7, 100.7, 104.5, 111.5", \ + "94.1, 94.1, 94.1, 98.1, 105.3", \ + "70.3, 70.3, 70.3, 74.5, 82.0"); + } + rise_transition (inslew_load_5x5__21) { + values ("21.7, 21.7, 21.7, 24.9, 30.7", \ + "23.3, 23.3, 23.3, 26.4, 32.2", \ + "26.1, 26.1, 26.1, 29.2, 35.1", \ + "31.2, 31.2, 31.2, 34.3, 40.3", \ + "41.1, 41.1, 41.1, 44.2, 50.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("120.8, 120.8, 120.8, 124.9, 132.6", \ + "136.0, 136.0, 136.0, 140.1, 147.9", \ + "158.0, 158.0, 158.0, 162.2, 170.0", \ + "192.2, 192.2, 192.2, 196.4, 204.5", \ + "251.6, 251.6, 251.6, 255.9, 264.1"); + } + fall_transition (inslew_load_5x5__21) { + values ("35.8, 35.8, 35.8, 38.9, 44.9", \ + "39.3, 39.3, 39.3, 42.4, 48.4", \ + "45.8, 45.8, 45.8, 48.9, 55.0", \ + "57.9, 57.9, 57.9, 61.0, 67.1", \ + "81.3, 81.3, 81.3, 84.4, 90.6"); + } + } + timing (maxd_q_i1_negative_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("105.7, 105.7, 105.7, 109.5, 116.5", \ + "112.6, 112.6, 112.6, 116.5, 123.5", \ + "117.8, 117.8, 117.8, 121.8, 129.0", \ + "117.3, 117.3, 117.3, 121.4, 128.8", \ + "104.9, 104.9, 104.9, 109.2, 116.9"); + } + rise_transition (inslew_load_5x5__21) { + values ("25.2, 25.2, 25.2, 28.3, 34.2", \ + "27.1, 27.1, 27.1, 30.3, 36.2", \ + "30.7, 30.7, 30.7, 33.8, 39.7", \ + "37.2, 37.2, 37.2, 40.3, 46.4", \ + "49.8, 49.8, 49.8, 52.9, 59.0"); + } + cell_fall (inslew_load_5x5__21) { + values ("117.9, 117.9, 117.9, 122.0, 129.7", \ + "129.9, 129.9, 129.9, 134.1, 141.8", \ + "146.9, 146.9, 146.9, 151.1, 158.9", \ + "171.7, 171.7, 171.7, 176.0, 183.9", \ + "213.5, 213.5, 213.5, 217.7, 225.9"); + } + fall_transition (inslew_load_5x5__21) { + values ("36.8, 36.8, 36.8, 39.9, 45.9", \ + "39.1, 39.1, 39.1, 42.2, 48.3", \ + "43.8, 43.8, 43.8, 46.9, 53.0", \ + "52.8, 52.8, 52.8, 56.0, 62.1", \ + "70.4, 70.4, 70.4, 73.5, 79.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1558.2, 1558.2, 1558.2, 1670.3, 1894.5", \ + "1904.0, 1904.0, 1904.0, 2016.1, 2240.2", \ + "2592.0, 2592.0, 2592.0, 2704.1, 2928.3", \ + "3968.1, 3968.1, 3968.1, 4080.2, 4304.4", \ + "6726.8, 6726.8, 6726.8, 6838.9, 7063.0"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1786.5, 1786.5, 1786.5, 1898.6, 2122.8", \ + "2053.8, 2053.8, 2053.8, 2165.9, 2390.1", \ + "2591.1, 2591.1, 2591.1, 2703.2, 2927.4", \ + "3656.0, 3656.0, 3656.0, 3768.1, 3992.2", \ + "5772.5, 5772.5, 5772.5, 5884.6, 6108.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1331.5, 1331.5, 1331.5, 1443.6, 1667.7", \ + "1570.7, 1570.7, 1570.7, 1682.8, 1906.9", \ + "2048.1, 2048.1, 2048.1, 2160.1, 2384.3", \ + "2997.4, 2997.4, 2997.4, 3109.4, 3333.6", \ + "4891.0, 4891.0, 4891.0, 5003.1, 5227.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1650.3, 1650.3, 1650.3, 1762.4, 1986.6", \ + "1983.9, 1983.9, 1983.9, 2096.0, 2320.1", \ + "2630.0, 2630.0, 2630.0, 2742.0, 2966.2", \ + "3899.2, 3899.2, 3899.2, 4011.3, 4235.4", \ + "6418.3, 6418.3, 6418.3, 6530.4, 6754.5"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("1792.5, 1792.5, 1792.5, 1904.6, 2128.8", \ + "1925.8, 1925.8, 1925.8, 2037.9, 2262.1", \ + "2181.4, 2181.4, 2181.4, 2293.5, 2517.7", \ + "2677.4, 2677.4, 2677.4, 2789.5, 3013.7", \ + "3653.8, 3653.8, 3653.8, 3765.9, 3990.1"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2163.2, 2163.2, 2163.2, 2275.3, 2499.5", \ + "2396.2, 2396.2, 2396.2, 2508.3, 2732.4", \ + "2848.6, 2848.6, 2848.6, 2960.6, 3184.8", \ + "3733.4, 3733.4, 3733.4, 3845.4, 4069.6", \ + "5485.9, 5485.9, 5485.9, 5598.0, 5822.2"); + } + } + internal_power (energy_neg_q_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("2061.4, 2061.4, 2061.4, 2173.5, 2397.7", \ + "2220.9, 2220.9, 2220.9, 2333.0, 2557.2", \ + "2522.8, 2522.8, 2522.8, 2634.9, 2859.1", \ + "3107.6, 3107.6, 3107.6, 3219.7, 3443.8", \ + "4255.2, 4255.2, 4255.2, 4367.3, 4591.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("2330.1, 2330.1, 2330.1, 2442.2, 2666.4", \ + "2532.3, 2532.3, 2532.3, 2644.4, 2868.5", \ + "2936.5, 2936.5, 2936.5, 3048.6, 3272.7", \ + "3733.7, 3733.7, 3733.7, 3845.8, 4070.0", \ + "5316.6, 5316.6, 5316.6, 5428.7, 5652.9"); + } + } + } + } + + cell (zero_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + pin (nq) { + function : "0" ; + direction : output ; + capacitance : 2.56 ; + } + } + +} diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/nsxlib2.py b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/nsxlib2.py new file mode 100644 index 000000000..d82e55edc --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/nsxlib2.py @@ -0,0 +1,217 @@ + +import sys +import os.path +from coriolis import Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, \ + BasicLayer, Cell, Net, Horizontal, Vertical, \ + Rectilinear, Box, Point, Instance, Transformation, \ + NetExternalComponents, Pad +import coriolis.Viewer +from coriolis.CRL import AllianceFramework, Environment, Gds, LefImport, \ + CellGauge, RoutingGauge, RoutingLayerGauge +from coriolis.helpers import l, u, n, overlay, io, ndaTopDir +from coriolis.helpers.overlay import CfgCache, UpdateSession +from coriolis.Anabatic import StyleFlags + + +__all__ = [ "setup" ] + + +def _routing (): + """ + Define the routing gauge along with the various P&R tool parameters. + """ + af = AllianceFramework.get() + db = DataBase.getDB() + tech = db.getTechnology() + rg = RoutingGauge.create('nsxlib2') + rg.setSymbolic( True ) + dirM1 = RoutingLayerGauge.Vertical + dirM2 = RoutingLayerGauge.Horizontal + netBuilderStyle = 'HV,3RL+' + routingStyle = StyleFlags.HV + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL1' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.PinOnly # layer usage + , 0 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 7.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL2' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 1 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL3' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 2 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL4' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 3 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 4.0) # wire width + , l( 4.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL5' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 4 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 4.0) # wire width + , l( 4.0) # perpandicular wire width + , l( 4.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL6' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.PowerSupply # layer usage + , 5 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(15.0) # track pitch + , l(12.0) # wire width + , l(12.0) # perpandicular wire width + , l( 4.0) # VIA side + , l( 8.0 ) )) # obstacle dW + af.addRoutingGauge( rg ) + af.setRoutingGauge( 'nsxlib2' ) + + cg = CellGauge.create( 'nsxlib2' + , 'METAL1' # pin layer name. + , l( 10.0) # pitch. + , l(100.0) # cell slice height. + , l( 10.0) # cell slice step. + ) + af.addCellGauge( cg ) + af.setCellGauge( 'nsxlib2' ) + + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + # Place & Route setup + cfg.viewer.minimumSize = 500 + cfg.viewer.pixelThreshold = 2 + cfg.lefImport.minTerminalWidth = 0.0 + cfg.crlcore.groundName = 'vss' + cfg.crlcore.powerName = 'vdd' + cfg.etesian.bloat = 'disabled' + cfg.etesian.aspectRatio = 1.00 + cfg.etesian.aspectRatio = [10, 1000] + cfg.etesian.spaceMargin = 0.10 + cfg.etesian.densityVariation = 0.05 + cfg.etesian.routingDriven = False + cfg.etesian.latchUpDistance = l(2000.0) + #cfg.etesian.diodeName = 'diode' + #cfg.etesian.antennaInsertThreshold = 0.50 + #cfg.etesian.antennaMaxWL = u(250.0) + cfg.etesian.feedNames = 'tie_x0,rowend_x0' + cfg.etesian.defaultFeed = 'tie_x0' + cfg.etesian.cell.zero = 'zero_x0' + cfg.etesian.cell.one = 'one_x0' + cfg.etesian.effort = 2 + cfg.etesian.effort = ( ('Fast' , 1) + , ('Standard', 2) + , ('High' , 3) + , ('Extreme' , 4) + ) + cfg.etesian.graphics = 2 + cfg.etesian.graphics = ( ('Show every step' , 1) + , ('Show lower bound', 2) + , ('Show result only', 3) + ) + cfg.anabatic.routingGauge = 'nsxlib2' + cfg.anabatic.cellGauge = 'nsxlib2' + cfg.anabatic.globalLengthThreshold = 30*l(100.0) + cfg.anabatic.saturateRatio = 0.90 + cfg.anabatic.saturateRp = 10 + cfg.anabatic.topRoutingLayer = 'METAL5' + cfg.anabatic.edgeLength = 192 + cfg.anabatic.edgeWidth = 32 + cfg.anabatic.edgeCostH = 9.0 + cfg.anabatic.edgeCostK = -10.0 + cfg.anabatic.edgeHInc = 1.0 + cfg.anabatic.edgeHScaling = 1.0 + cfg.anabatic.globalIterations = 10 + cfg.anabatic.globalIterations = [ 1, 100 ] + cfg.anabatic.gcell.displayMode = 1 + cfg.anabatic.gcell.displayMode = (("Boundary", 1), ("Density", 2)) + cfg.anabatic.netBuilderStyle = netBuilderStyle + cfg.anabatic.routingStyle = routingStyle + cfg.katana.disableStackedVias = False + cfg.katana.hTracksReservedLocal = 4 + cfg.katana.hTracksReservedLocal = [0, 20] + cfg.katana.vTracksReservedLocal = 3 + cfg.katana.vTracksReservedLocal = [0, 20] + cfg.katana.termSatReservedLocal = 8 + cfg.katana.termSatThreshold = 9 + cfg.katana.eventsLimit = 4000002 + cfg.katana.ripupCost = 3 + cfg.katana.ripupCost = [0, None] + cfg.katana.strapRipupLimit = 16 + cfg.katana.strapRipupLimit = [1, None] + cfg.katana.localRipupLimit = 9 + cfg.katana.localRipupLimit = [1, None] + cfg.katana.globalRipupLimit = 5 + cfg.katana.globalRipupLimit = [1, None] + cfg.katana.longGlobalRipupLimit = 5 + cfg.chip.padCoreSide = 'North' + # Plugins setup + cfg.clockTree.minimumSide = l(100.0) * 6 + cfg.clockTree.buffer = 'buf_x8' + cfg.clockTree.placerEngine = 'Etesian' + cfg.block.spareSide = 10*l(100.0) + cfg.spares.buffer = 'buf_x8' + cfg.spares.maxSinks = 31 + + +def _loadNsxlib2 ( cellsTop ): + """ + Setup for NSXLIB2 Alliance library. It is an symbolic library + from which cells are loaded on demand, so we only setup pathes. + + :param cellsTop: The top directory containing the cells views. + """ + af = AllianceFramework.get() + env = af.getEnvironment() + env.setSCALE_X ( 100 ) + env.setCATALOG ( 'CATAL' ) + env.setPOWER ( 'vdd' ) + env.setGROUND ( 'vss' ) + env.setCLOCK ( '^ck$|m_clock|^clk$' ) + env.setBLOCKAGE( 'blockage[Nn]et.*' ) + env.setPad ( '.*_mpx$' ) + env.setRegister( 'sff.*' ) + env.setWORKING_LIBRARY( '.' ) + env.addSYSTEM_LIBRARY ( library=(cellsTop / 'nsxlib2').as_posix(), mode=Environment.Append ) + + +def setup ( cellsTop ): + _routing() + _loadNsxlib2( cellsTop ) diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/sg13g2_nsx2.rds b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/sg13g2_nsx2.rds new file mode 100644 index 000000000..137dcb591 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/sg13g2_nsx2.rds @@ -0,0 +1,660 @@ +# 20240522 +# --------------------------------------------------------------------------- +# For IHP SG13G2 by Naohiko Shimizu +# --------------------------------------------------------------------------- + + + + +# ------------------------------------------------------------------- +# globals define +# ------------------------------------------------------------------- + +define physical_grid 0.001 +define lambda 0.075 + +table cif_layer +# ------------------------------------------------------------------- +# rds_name cif_name +# ------------------------------------------------------------------- + rds_nwell nwell +# rds_pwell pwel + rds_activ diff + rds_ntie tap + rds_ptie tap + rds_ndif nsdm + rds_pdif psdm + rds_nimp nsdm + rds_pimp psdm + rds_poly poly + rds_alu1 li1 + rds_alu2 met1 + rds_alu3 met2 + rds_alu4 met3 + rds_alu5 met4 + rds_alu6 met5 + rds_cont licon1 + rds_via1 mcon + rds_via2 via + rds_via3 via2 + rds_via4 via3 + rds_via5 via4 + rds_poly2 npc + rds_cpas pad +end + +table gds_layer +# ------------------------------------------------------------------- +# rds_name gds_number gds_datatype +# IHP uses only 0 gds_datatype for drawing +# ------------------------------------------------------------------- + rds_nwell 31 0 + rds_pwell 46 0 + rds_activ 1 0 + rds_ptie 1 0 + rds_ntie 1 0 + rds_pdif 1 0 + rds_ndif 1 0 + rds_pimp 14 0 + rds_nimp 7 0 + rds_poly 5 0 + rds_alu1 8 0 8 2 + rds_alu2 10 0 10 2 + rds_alu3 30 0 30 2 + rds_alu4 50 0 50 2 + rds_alu5 67 0 67 2 + rds_alu6 126 0 126 2 + rds_cont 6 0 + rds_via1 19 0 + rds_via2 29 0 + rds_via3 49 0 + rds_via4 66 0 + rds_via5 125 0 +# rds_poly2 95 20 + rds_cpas 9 0 +end + +table lynx_resistor +# ------------------------------------------------------------------- +# rds_name square_resistor(ohm/square) # typical values +# ------------------------------------------------------------------- +# Poly resistor is differ from N-doped to P-doped. 7 ohm is for N-doped. +# P-doped poly is 260 ohm + + rds_poly 7 + rds_alu1 0.115 + rds_alu2 0.088 + rds_alu3 0.088 + rds_alu4 0.088 + rds_alu5 0.088 + rds_alu6 0.018 + rds_cont 15 + rds_via1 9 + rds_via2 9 + rds_via3 9 + rds_via4 9 + rds_via5 2.2 +end + +table lynx_capa +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- + rds_poly 35.3e-3 51.8e-6 # Ca max POLY_NWELL 2Cf0 max POLY_NWELL + rds_alu1 5.9e-5 8.5e-5 # Ca max M1_NWELL 2Cf0 max M1_NWELL + rds_alu2 6.8e-5 7.9e-5 # Ca max M2_NWELL 2Cf0 max M2_NWELL + rds_alu3 6.8e-5 6.8e-5 # Ca max M3_NWELL 2Cf0 max M3_NWELL + rds_alu4 6.8e-5 6.0e-5 # Ca max M4_NWELL 2Cf0 max M4_NWELL + rds_alu5 6.8e-5 6.0e-5 # hyp + rds_alu6 4.2e-5 6.0e-5 +end + +table lynx_capa_poly +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_poly2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu1 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu3 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu4 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu5 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end +table mbk_to_rds_segment +# ---------------------------------------------------------------------------------- +# mbk_name rds_name1 dlr dwr offset mode rds_name2 dlr dwr offset mode +# ---------------------------------------------------------------------------------- + + nwell rds_nwell vw 0.460 0.280 .0 all\ + rds_pimp vw 0.0 -0.720 .240 all \ + rds_nimp vw 0.0 -1.68 3.9 all + +# pwell rds_pwell vw 0.460 0.280 .0 all +# rds_pimp vw 0.225 0.170 .0 all + + ndif rds_activ vw 0.01 0.015 .0 all\ + rds_nimp vw 0.01 0.015 .0 all\ + rds_ndif vw 0.01 0.015 .0 ext + + pdif rds_activ vw 0.01 0.015 .0 all\ + rds_pimp vw 0.19 0.380 .0 all\ + rds_pdif vw 0.01 0.015 .0 all + + ntie rds_ntie vw 0.010 0.015 .0 all\ + rds_nimp vw 0.270 0.120 .0 all\ + rds_nwell vw 0.460 0.510 .0 all + + ptie rds_ptie vw 0.010 0.015 .0 all\ + rds_pimp vw 0.270 0.040 .0 all +# rds_pwell vw 0.460 0.510 .0 all + + ntrans rds_poly vw 0.19 -0.020 .0 all\ + rds_activ vw 0.01 0.48 .0 drc\ + rds_nimp vw 0.01 0.48 .0 drc\ + rds_ndif lcw 0.01 0.24 -0.005 all\ + rds_ndif rcw 0.01 0.24 -0.005 all + + ptrans rds_poly vw 0.19 -0.020 .0 all\ + rds_activ vw 0.01 0.48 .0 drc\ + rds_pimp vw 0.01 0.48 .0 all\ + rds_pdif lcw 0.01 0.24 -0.005 all\ + rds_pdif rcw 0.01 0.24 -0.005 all + + poly rds_poly vw 0.0 -0.020 .0 all + + alu1 rds_alu1 vw 0.005 0.01 .0 all + calu1 rds_alu1 vw 0.005 0.01 .0 all + talu1 rds_talu1 vw 0.005 0.01 .0 all + + alu2 rds_alu2 vw 0.11 0.01 .0 all + calu2 rds_alu2 vw 0.11 0.01 .0 all + talu2 rds_talu2 vw 0.11 0.01 .0 all + + alu3 rds_alu3 vw 0.11 0.0 .0 all + calu3 rds_alu3 vw 0.11 0.0 .0 all + talu3 rds_talu3 vw 0.11 0.0 .0 all + + alu4 rds_alu4 vw 0.15 0.0 .0 all + calu4 rds_alu4 vw 0.15 0.0 .0 all + talu4 rds_talu4 vw 0.15 0.0 .0 all + + alu5 rds_alu5 vw 0.15 0.0 .0 all + calu5 rds_alu5 vw 0.15 0.0 .0 all + talu5 rds_talu5 vw 0.15 0.0 .0 all +end + +table mbk_to_rds_connector +# ------------------------------------------------------------------- +# mbk_name rds_name der dwr +# ------------------------------------------------------------------- +end + +table mbk_to_rds_reference +# ------------------------------------------------------------------- +# mbk_name rds_name width +# ------------------------------------------------------------------- + ref_ref rds_ref 0.330 + ref_con rds_ref 0.330 +end + +table mbk_to_rds_via +# ------------------------------------------------------------------- +# mbk_name rds_name1 width mode rds_name2 width mode ... +## ------------------------------------------------------------------ +# difftap.5 +# licon.7 0.170+0.120*2 + cont_body_n \ + rds_cont 0.160 all\ + rds_alu1 0.300 all\ +# rds_nimp 0.430 all\ + rds_ntie 0.300 ext + +# licon.7 0.170+0.120*2 +# difftap.5 + cont_body_p \ + rds_cont 0.160 all\ + rds_alu1 0.300 all\ + rds_pimp 0.340 all\ + rds_ptie 0.300 ext + +# licon.5c + cont_dif_n \ + rds_cont 0.160 all\ + rds_alu1 0.300 all\ + rds_activ 0.300 drc\ + rds_ndif 0.420 ext + +# licon.5c + cont_dif_p \ + rds_cont 0.160 all\ + rds_alu1 0.300 all\ + rds_activ 0.300 drc\ + rds_pimp 0.340 all\ + rds_pdif 0.420 ext + +# copy + cont_poly \ + rds_cont 0.160 all\ + rds_poly 0.300 all\ + rds_alu1 0.300 all + + + +# m1.4 +# NPC --> poly2 +# m1.5 + cont_via \ + rds_via1 0.190 all\ + rds_alu1 0.300 all\ + rds_alu2 0.380 all + +# via.1b +# via.5b +# m2.5 + cont_via2 \ + rds_via2 0.190 all\ + rds_alu2 0.380 all\ + rds_alu3 0.380 all + +# via.1b +# via.5b +# m2.5 + cont_via3 \ + rds_via3 0.190 all\ + rds_alu3 0.380 all\ + rds_alu4 0.380 all + + cont_via4 \ + rds_via4 0.190 all\ + rds_alu4 0.380 all\ + rds_alu5 0.380 all +end + +table mbk_to_rds_bigvia_hole +# ------------------------------------------------------------------- +# mbk_via_name rds_hole_name side step mode +# ------------------------------------------------------------------- +end + +table mbk_to_rds_bigvia_metal +# ------------------------------------------------------------------- +# mbk_via_name rds_name dwr overlap mode +# ------------------------------------------------------------------- +end + +table mbk_to_rds_turnvia +# ------------------------------------------------------------------- +# mbk_name rds_name dwr mode +# ------------------------------------------------------------------- + cont_turn1 rds_alu1 0.085 all + cont_turn2 rds_alu2 0.01 all + cont_turn3 rds_alu3 0.01 all + cont_turn4 rds_alu4 0.01 all + cont_turn5 rds_alu5 0.01 all +end + +table lynx_bulk_implicit +# ------------------------------------------------------------------- +# rds_name type[explicit|implicit] +# ------------------------------------------------------------------- +end + +table lynx_transistor +# ------------------------------------------------------------------- +# mbk_name trans_name compostion +# ------------------------------------------------------------------- + ntrans ntrans c_x_n rds_poly rds_ndif rds_ndif rds_pwell + ptrans ptrans c_x_p rds_poly rds_pdif rds_pimp rds_nwell +end + +table lynx_diffusion +# ------------------------------------------------------------------- +# rds_name compostion +# ------------------------------------------------------------------- +end + +table lynx_graph +# ------------------------------------------------------------------- +# rds_name in_contact_with rds_name1 rds_name2 ... +# ------------------------------------------------------------------- + rds_ndif rds_cont rds_ndif + rds_pdif rds_cont rds_pdif + rds_poly rds_cont rds_poly + rds_cont rds_pdif rds_ndif rds_poly rds_alu1 rds_cont + rds_alu1 rds_cont rds_via1 rds_ref rds_alu1 + rds_ref rds_cont rds_via1 rds_alu1 rds_ref + RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 + RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 + RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 + RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 + RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 + rds_alu2 rds_via1 rds_via2 rds_alu2 + rds_alu3 rds_via2 rds_via3 rds_alu3 + rds_alu4 rds_via3 rds_via4 rds_alu4 + rds_alu5 rds_via4 rds_via5 rds_alu5 +end + +table s2r_oversize_denotch +# ------------------------------------------------------------------- +# rds_name oversized_value_for_denotching +# ------------------------------------------------------------------- + rds_nwell 0.635 + rds_pwell 0.635 + rds_poly 0.100 + rds_alu1 0.080 + rds_alu2 0.080 + rds_alu3 0.080 + rds_alu4 0.080 + rds_alu5 0.080 + rds_activ 0.130 + rds_ntie 0.190 + rds_ptie 0.190 + rds_nimp 0.150 + rds_pimp 0.150 +end + +table s2r_bloc_ring_width +# ------------------------------------------------------------------- +# rds_name ring_width_to_copy_up +# ------------------------------------------------------------------- + rds_nwell 0. # [ RD_NWEL ] + rds_pwell 0. # [ RD_PWEL ] + rds_poly 0. # [ RD_POLY ] + rds_alu1 0. # [ RD_ALU1 ] + rds_alu2 0. # [ RD_ALU2 ] + rds_alu3 0. # [ RD_ALU3 ] + rds_alu4 0. # [ RD_ALU3 ] + rds_alu5 0. # [ RD_ALU3 ] + rds_activ 0. # [ RD_ACTI ] + rds_ntie 0. # [ RD_NIMP ] + rds_ptie 0. # [ RD_PIMP ] + rds_nimp 0. # [ RD_NIMP ] + rds_pimp 0. # [ RD_PIMP ] +end + +table s2r_minimum_layer_width +# ------------------------------------------------------------------- +# rds_name min_layer_width_to_keep +# ------------------------------------------------------------------- + rds_nwell 0.840 + rds_pwell 0.840 + rds_poly 0.150 + rds_alu1 0.170 + rds_alu2 0.170 + rds_alu3 0.170 + rds_alu4 0.300 + rds_alu5 0.300 + rds_activ 0.420 + rds_ntie 0.380 + rds_ptie 0.380 + rds_nimp 0.310 + rds_pimp 0.310 +end + +table s2r_post_treat +# ------------------------------------------------------------------- +# rds_name s2r_must_treat_or_not second_layer_whenever_scotch +# ------------------------------------------------------------------- + rds_nwell treat rds_pwell + rds_pwell treat rds_nwell + rds_poly treat null + rds_activ treat null + rds_ntie treat rds_pimp + rds_ptie treat rds_nimp + rds_nimp treat rds_ptie + rds_pimp treat rds_ntie + rds_alu1 treat null + rds_alu2 treat null + rds_alu3 treat null + rds_alu4 treat null + rds_alu5 treat null + rds_cont notreat null +end + +DRC_RULES + +layer RDS_NWELL 0.840 ; +layer RDS_NTIE 0.380 ; +layer RDS_PTIE 0.380 ; +layer RDS_NIMP 0.380 ; +layer RDS_PIMP 0.380 ; +layer RDS_ACTIV 0.420 ; +layer RDS_CONT 0.170 ; +layer RDS_POLY 0.150 ; +layer RDS_ALU1 0.170 ; +layer RDS_ALU2 0.170 ; +layer RDS_ALU3 0.170 ; +layer RDS_ALU4 0.300 ; +layer RDS_ALU5 0.300 ; +layer RDS_USER0 0.005 ; +layer RDS_USER1 0.005 ; +layer RDS_USER2 0.005 ; + +regles + +# note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# there is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# ---------------------------------------------------------- + +# check the nwell shapes +# ---------------------- +characterize RDS_NWELL ( + rule 1 : width >= 0.620 ; + rule 2 : intersection_length min 0.620 ; + rule 3 : notch >= 0.62 ; +); +relation RDS_NWELL , RDS_NWELL ( + rule 4 : spacing axial min 0.62 ; +); +relation RDS_NWELL , RDS_ACTI ( + rule 5 : spacing axial min 0.31 ; +); + +# check the RDS_PIMP shapes +# ------------------------- +characterize RDS_PIMP ( + rule 6 : surface min 0.25 ; + rule 7 : width >= 0.310 ; + rule 8 : intersection_length min 0.310 ; + rule 9 : notch >= 0.310 ; +); +relation RDS_PIMP , RDS_PIMP ( + rule 10 : spacing axial min 0.310 ; +); + + +# check the RDS_PTIE shapes +# ------------------------- +characterize RDS_PTIE ( + rule 16 : surface min 0.255 ; + rule 17 : width >= 0.380 ; + rule 18 : intersection_length min 0.380 ; + rule 19 : notch >= 0.380 ; +); +relation RDS_PTIE , RDS_PTIE ( + rule 20 : spacing axial min 0.380 ; +); + +# check the RDS_NTIE shapes +# ------------------------- +characterize RDS_NTIE ( + rule 21 : surface min 0.265 ; + rule 22 : width >= 0.380 ; + rule 23 : intersection_length min 0.380 ; + rule 24 : notch >= 0.380 ; +); +relation RDS_NTIE , RDS_NTIE ( + rule 25 : spacing axial min 0.380 ; +); + +# check the RDS_ACTI shapes +# ------------------------- +characterize RDS_ACTI ( + rule 26 : surface min 0.125 ; + rule 27 : width >= 0.15 ; + rule 28 : intersection_length min 0.15 ; + rule 29 : notch >= 0.21 ; +); +relation RDS_ACTI, RDS_ACTI ( + rule 30 : spacing axial min 0.210 ; +); + +# check the RDS_NIMP RDS_PTIE exclusion +# ------------------------------------- +define RDS_NIMP , RDS_PTIE intersection -> NPIMP; +characterize NPIMP ( + rule 31 : width = 0. ; +); +undefine NPIMP; + +# check the RDS_NTIE RDS_PIMP exclusion +# ------------------------------------- +define RDS_NTIE , RDS_PIMP intersection -> NPIMP; +characterize NPIMP ( + rule 32 : width = 0. ; +); +undefine NPIMP; + +# check the RDS_POLY shapes +# ------------------------- +characterize RDS_POLY ( + rule 33 : width >= 0.130 ; + rule 34 : intersection_length min 0.130 ; + rule 35 : notch >= 0.18 ; +); +relation RDS_POLY , RDS_POLY ( + rule 36 : spacing axial min 0.18 ; +); + +define RDS_ACTI , RDS_POLY intersection -> channel; + + # check the channel shapes + # ------------------------- + characterize channel ( + rule 37 : notch >= 0.18 ; + ); + relation channel , channel ( + rule 38 : spacing axial min 0.18 ; + ); + +undefine channel; + +define RDS_ACTI , RDS_CONT intersection -> cont_diff; + + relation RDS_POLY , cont_diff ( + rule 39 : spacing axial >= 0.11 ; + ); + +undefine cont_diff; + +# check RDS_ALU1 shapes +# --------------------- +characterize RDS_ALU1 ( + rule 40 : surface min 0.090 ; + rule 41 : width >= 0.160 ; + rule 42 : intersection_length min 0.160 ; + rule 43 : notch >= 0.180 ; +); +relation RDS_ALU1 , RDS_ALU1 ( + rule 44 : spacing axial min 0.180 ; +); + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_CONT , RDS_CONT ( + rule 45 : spacing axial >= 0.180 ; +); + +characterize RDS_CONT ( + rule 46 : width = 0.160 ; + rule 47 : length = 0.160 ; +); + +# check RDS_POLY is distant from activ zone of transistor +# ------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + rule 48 : spacing axial >= 0.07 ; +); + +end rules +DRC_COMMENT +1 (RDS_NWELL) Minimum width 0.620 +2 (RDS_NWELL) Intersection length 0.620 +3 (RDS_NWELL) Notch 0.62 +4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 0.62 +5 (RDS_NWELL,RDS_ACTI) Manhatan distance min 0.310 +6 (RDS_PIMP) Minimum area 0.25 +7 (RDS_PIMP) Minimum width 0.310 +8 (RDS_PIMP) Intersection length 0.310 +9 (RDS_PIMP) Notch 0.310 +10 (RDS_PIMP,RDS_PIMP) Manhatan distance min 0.310 +16 (RDS_PTITE) Minimum area 0.255 +17 (RDS_PTITE) Minimum width 0.380 +18 (RDS_PTITE) Intersection length 0.380 +19 (RDS_PTITE) Notch 0.380 +20 (RDS_PTITE,RDS_PTITE) Manhatan distance min 0.380 +21 (RDS_NTITE) Minimum area 0.265 +22 (RDS_NTITE) Minimum width 0.380 +23 (RDS_NTITE) Intersection length 0.380 +24 (RDS_NTITE) Notch 0.380 +25 (RDS_NTITE,RDS_NTITE) Manhatan distance min 0.380 +26 (RDS_ACTI) Minimum area 0.125 +27 (RDS_ACTI) Minimum width 0.15 +28 (RDS_ACTI) Intersection length 0.15 +29 (RDS_ACTI) Notch 0.210 +30 (RDS_ACTI,RDS_ACTI) Manhatan distance min 0.210 +31 (RDS_NIMP,RDS_PTIE) intersection width 0. +32 (RDS_PIMP,RDS_NTIE) intersection width 0. +33 (RDS_POLY) Minimum width 0.130 +34 (RDS_POLY) Intersection length 0.130 +35 (RDS_POLY) Notch 0.18 +36 (RDS_POLY,RDS_POLY) Manhatan distance min 0.18 +37 (channel) Notch 0.18 +38 (channel) Manhatan distance min 0.18 +39 (cont_diff) Manhatan distance min 0.11 +40 (RDS_ALU1) Minimum area 0.090 +41 (RDS_ALU1) Minimum width 0.160 +42 (RDS_ALU1) Intersection length 0.160 +43 (RDS_ALU1) Notch 0.180 +44 (RDS_ALU1,RDS_ALU1) Manhatan distance min 0.180 +45 (RDS_CONT,RDS_CONT) Manhatan distance min 0.180 +46 (RDS_CONT) Width 0.160 +47 (RDS_CONT) Length 0.160 +48 (RDS_POLY,RDS_ACTIV) Manhatan distance min 0.07 +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a2_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a2_x2.spi new file mode 100644 index 000000000..55ba9d06b --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a2_x2.spi @@ -0,0 +1,27 @@ +* Spice description of a2_x2 +* Spice driver version -824762597 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:10 + +* INTERF i0 i1 q vdd vss + + +.subckt a2_x2 5 2 3 1 4 +* NET 1 = vdd +* NET 2 = i1 +* NET 3 = q +* NET 4 = vss +* NET 5 = i0 +Xtr_00006 3 7 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 1 2 7 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00004 7 5 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00003 3 7 4 4 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 6 5 7 4 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 4 2 6 4 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C7 1 4 1.50705e-15 +C6 2 4 1.61474e-14 +C5 3 4 1.93831e-15 +C4 4 4 1.26852e-15 +C3 5 4 2.05714e-14 +C1 7 4 2.16616e-14 +.ends a2_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a2_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a2_x4.spi new file mode 100644 index 000000000..7cb458349 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a2_x4.spi @@ -0,0 +1,29 @@ +* Spice description of a2_x4 +* Spice driver version 83533595 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:10 + +* INTERF i0 i1 q vdd vss + + +.subckt a2_x4 4 3 2 1 7 +* NET 1 = vdd +* NET 2 = q +* NET 3 = i1 +* NET 4 = i0 +* NET 7 = vss +Xtr_00008 1 6 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 6 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 1 3 6 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00005 6 4 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00004 7 6 2 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 2 6 7 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 7 3 5 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 5 4 6 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C7 1 7 2.4749e-15 +C6 2 7 1.08178e-15 +C5 3 7 2.41961e-14 +C4 4 7 1.8952e-14 +C2 6 7 3.58946e-14 +C1 7 7 1.83543e-15 +.ends a2_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a3_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a3_x2.spi new file mode 100644 index 000000000..ed5c64554 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a3_x2.spi @@ -0,0 +1,31 @@ +* Spice description of a3_x2 +* Spice driver version 947625755 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:11 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt a3_x2 6 7 2 3 1 5 +* NET 1 = vdd +* NET 2 = i2 +* NET 3 = q +* NET 5 = vss +* NET 6 = i0 +* NET 7 = i1 +Xtr_00008 3 9 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 1 2 9 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00006 9 7 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00005 1 6 9 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00004 3 9 5 5 sg13_lv_nmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00003 5 2 4 5 sg13_lv_nmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00002 8 6 9 5 sg13_lv_nmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00001 4 7 8 5 sg13_lv_nmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +C9 1 5 2.04488e-15 +C8 2 5 1.47087e-14 +C7 3 5 1.93831e-15 +C5 5 5 1.569e-15 +C4 6 5 1.47087e-14 +C3 7 5 1.57645e-14 +C1 9 5 1.44675e-14 +.ends a3_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a3_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a3_x4.spi new file mode 100644 index 000000000..a9e082f22 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a3_x4.spi @@ -0,0 +1,33 @@ +* Spice description of a3_x4 +* Spice driver version 1526161179 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:11 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt a3_x4 7 6 2 4 1 5 +* NET 1 = vdd +* NET 2 = i2 +* NET 4 = q +* NET 5 = vss +* NET 6 = i1 +* NET 7 = i0 +Xtr_00010 1 9 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 4 9 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 1 2 9 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00007 9 6 1 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00006 1 7 9 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00005 5 9 4 5 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 4 9 5 5 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 5 2 3 5 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 3 6 8 5 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 8 7 9 5 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C9 1 5 2.74664e-15 +C8 2 5 1.82833e-14 +C6 4 5 1.93831e-15 +C5 5 5 2.12095e-15 +C4 6 5 1.68755e-14 +C3 7 5 1.68755e-14 +C1 9 5 4.27676e-14 +.ends a3_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a4_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a4_x2.spi new file mode 100644 index 000000000..db4ea5842 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a4_x2.spi @@ -0,0 +1,35 @@ +* Spice description of a4_x2 +* Spice driver version 354148123 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:11 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt a4_x2 8 9 4 3 2 1 11 +* NET 1 = vdd +* NET 2 = q +* NET 3 = i3 +* NET 4 = i2 +* NET 8 = i0 +* NET 9 = i1 +* NET 11 = vss +Xtr_00010 2 7 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 1 3 7 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00008 7 4 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00007 7 8 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00006 1 9 7 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00005 7 3 6 11 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00004 2 7 11 11 sg13_lv_nmos L=0.13U W=1.89U AS=0.4536P AD=0.4536P PS=4.27U PD=4.27U +Xtr_00003 6 4 5 11 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00002 10 8 11 11 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00001 5 9 10 11 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +C11 1 11 2.61062e-15 +C10 2 11 1.93831e-15 +C9 3 11 2.01651e-14 +C8 4 11 1.57159e-14 +C5 7 11 1.80612e-14 +C4 8 11 1.47363e-14 +C3 9 11 1.5012e-14 +C1 11 11 2.06464e-15 +.ends a4_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a4_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a4_x4.spi new file mode 100644 index 000000000..e49642117 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/a4_x4.spi @@ -0,0 +1,37 @@ +* Spice description of a4_x4 +* Spice driver version -233447653 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:11 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt a4_x4 8 9 4 3 2 1 11 +* NET 1 = vdd +* NET 2 = q +* NET 3 = i3 +* NET 4 = i2 +* NET 8 = i0 +* NET 9 = i1 +* NET 11 = vss +Xtr_00012 1 7 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 1 3 7 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00010 7 4 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00009 1 9 7 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00008 7 8 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00007 2 7 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 7 3 6 11 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00005 11 7 2 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 2 7 11 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 6 4 5 11 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00002 10 8 11 11 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00001 5 9 10 11 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +C11 1 11 3.56469e-15 +C10 2 11 1.93831e-15 +C9 3 11 2.06059e-14 +C8 4 11 1.67441e-14 +C5 7 11 3.59331e-14 +C4 8 11 1.47087e-14 +C3 9 11 1.56883e-14 +C1 11 11 2.56145e-15 +.ends a4_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/an12_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/an12_x1.spi new file mode 100644 index 000000000..5277beba3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/an12_x1.spi @@ -0,0 +1,27 @@ +* Spice description of an12_x1 +* Spice driver version 1731657499 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:12 + +* INTERF i0 i1 q vdd vss + + +.subckt an12_x1 5 3 7 1 6 +* NET 1 = vdd +* NET 3 = i1 +* NET 5 = i0 +* NET 6 = vss +* NET 7 = q +Xtr_00006 1 4 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 4 3 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00004 2 5 7 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00003 7 5 6 6 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 4 3 6 6 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 6 4 7 6 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C7 1 6 1.33828e-15 +C5 3 6 1.40667e-14 +C4 4 6 2.12482e-14 +C3 5 6 1.68442e-14 +C2 6 6 1.85553e-15 +C1 7 6 2.05558e-15 +.ends an12_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/an12_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/an12_x4.spi new file mode 100644 index 000000000..92d1b682f --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/an12_x4.spi @@ -0,0 +1,32 @@ +* Spice description of an12_x4 +* Spice driver version -239829221 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:12 + +* INTERF i0 i1 q vdd vss + + +.subckt an12_x4 6 2 3 1 7 +* NET 1 = vdd +* NET 2 = i1 +* NET 3 = q +* NET 6 = i0 +* NET 7 = vss +Xtr_00010 1 5 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 3 5 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 1 2 5 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 5 8 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 1 6 8 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 7 5 3 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 3 5 7 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 7 2 4 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 4 8 5 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 7 6 8 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C8 1 7 2.7798e-15 +C7 2 7 1.28896e-14 +C6 3 7 2.05583e-15 +C4 5 7 3.67275e-14 +C3 6 7 1.97583e-14 +C2 7 7 2.24803e-15 +C1 8 7 2.82635e-14 +.ends an12_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao22_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao22_x2.spi new file mode 100644 index 000000000..158fca136 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao22_x2.spi @@ -0,0 +1,32 @@ +* Spice description of ao22_x2 +* Spice driver version -74666213 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:12 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt ao22_x2 7 6 3 4 2 5 +* NET 2 = vdd +* NET 3 = i2 +* NET 4 = q +* NET 5 = vss +* NET 6 = i1 +* NET 7 = i0 +Xtr_00008 4 8 2 2 sg13_lv_pmos L=0.13U W=2.34U AS=0.5616P AD=0.5616P PS=5.17U PD=5.17U +Xtr_00007 2 3 8 2 sg13_lv_pmos L=0.13U W=2.34U AS=0.5616P AD=0.5616P PS=5.17U PD=5.17U +Xtr_00006 1 7 2 2 sg13_lv_pmos L=0.13U W=2.34U AS=0.5616P AD=0.5616P PS=5.17U PD=5.17U +Xtr_00005 8 6 1 2 sg13_lv_pmos L=0.13U W=2.34U AS=0.5616P AD=0.5616P PS=5.17U PD=5.17U +Xtr_00004 4 8 5 5 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 5 3 9 5 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 9 6 8 5 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 8 7 9 5 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C8 2 5 1.86267e-15 +C7 3 5 2.07938e-14 +C6 4 5 1.99952e-15 +C5 5 5 1.75005e-15 +C4 6 5 1.77448e-14 +C3 7 5 1.7821e-14 +C2 8 5 3.01232e-14 +C1 9 5 4.17738e-16 +.ends ao22_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao22_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao22_x4.spi new file mode 100644 index 000000000..f85c51b45 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao22_x4.spi @@ -0,0 +1,34 @@ +* Spice description of ao22_x4 +* Spice driver version -49991909 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:12 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt ao22_x4 7 4 5 3 2 6 +* NET 2 = vdd +* NET 3 = q +* NET 4 = i1 +* NET 5 = i2 +* NET 6 = vss +* NET 7 = i0 +Xtr_00010 2 8 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 3 8 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 2 5 8 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00007 8 4 1 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00006 1 7 2 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00005 9 4 8 6 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00004 8 7 9 6 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00003 6 8 3 6 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00002 3 8 6 6 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00001 6 5 9 6 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +C8 2 6 3.50537e-15 +C7 3 6 1.93831e-15 +C6 4 6 1.80968e-14 +C5 5 6 2.09881e-14 +C4 6 6 2.61776e-15 +C3 7 6 1.74691e-14 +C2 8 6 3.96706e-14 +C1 9 6 4.45309e-16 +.ends ao22_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao2o22_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao2o22_x2.spi new file mode 100644 index 000000000..7b93a1049 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao2o22_x2.spi @@ -0,0 +1,36 @@ +* Spice description of ao2o22_x2 +* Spice driver version -1532334309 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:13 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt ao2o22_x2 9 5 7 6 4 3 8 +* NET 3 = vdd +* NET 4 = q +* NET 5 = i1 +* NET 6 = i3 +* NET 7 = i2 +* NET 8 = vss +* NET 9 = i0 +Xtr_00010 3 6 1 3 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00009 10 5 2 3 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00008 4 10 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 1 7 10 3 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00006 2 9 3 3 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00005 10 9 11 8 sg13_lv_nmos L=0.13U W=1.29U AS=0.3096P AD=0.3096P PS=3.07U PD=3.07U +Xtr_00004 11 5 10 8 sg13_lv_nmos L=0.13U W=1.29U AS=0.3096P AD=0.3096P PS=3.07U PD=3.07U +Xtr_00003 4 10 8 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 11 6 8 8 sg13_lv_nmos L=0.13U W=1.29U AS=0.3096P AD=0.3096P PS=3.07U PD=3.07U +Xtr_00001 8 7 11 8 sg13_lv_nmos L=0.13U W=1.29U AS=0.3096P AD=0.3096P PS=3.07U PD=3.07U +C9 3 8 2.46702e-15 +C8 4 8 1.93831e-15 +C7 5 8 1.81795e-14 +C6 6 8 1.88558e-14 +C5 7 8 2.37925e-14 +C4 8 8 2.3241e-15 +C3 9 8 1.79313e-14 +C2 10 8 1.61079e-14 +C1 11 8 8.18684e-16 +.ends ao2o22_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao2o22_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao2o22_x4.spi new file mode 100644 index 000000000..f4631fd24 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ao2o22_x4.spi @@ -0,0 +1,38 @@ +* Spice description of ao2o22_x4 +* Spice driver version 1826103067 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:13 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt ao2o22_x4 9 8 6 5 4 3 7 +* NET 3 = vdd +* NET 4 = q +* NET 5 = i3 +* NET 6 = i2 +* NET 7 = vss +* NET 8 = i1 +* NET 9 = i0 +Xtr_00012 3 5 1 3 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00011 3 10 4 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 4 10 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 1 6 10 3 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00008 10 8 2 3 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00007 2 9 3 3 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00006 11 5 7 7 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00005 7 6 11 7 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00004 7 10 4 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 4 10 7 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 11 8 10 7 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00001 10 9 11 7 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +C9 3 7 3.23798e-15 +C8 4 7 1.93831e-15 +C7 5 7 2.69505e-14 +C6 6 7 2.66081e-14 +C5 7 7 2.7382e-15 +C4 8 7 1.85314e-14 +C3 9 7 1.82557e-14 +C2 10 7 4.1784e-14 +C1 11 7 7.49757e-16 +.ends ao2o22_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/buf_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/buf_x2.spi new file mode 100644 index 000000000..655127599 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/buf_x2.spi @@ -0,0 +1,23 @@ +* Spice description of buf_x2 +* Spice driver version 1659420443 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:13 + +* INTERF i q vdd vss + + +.subckt buf_x2 3 2 1 4 +* NET 1 = vdd +* NET 2 = q +* NET 3 = i +* NET 4 = vss +Xtr_00004 2 5 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00003 1 3 5 1 sg13_lv_pmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00002 4 3 5 4 sg13_lv_nmos L=0.13U W=0.69U AS=0.1656P AD=0.1656P PS=1.87U PD=1.87U +Xtr_00001 2 5 4 4 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C5 1 4 1.10757e-15 +C4 2 4 1.93831e-15 +C3 3 4 1.88002e-14 +C2 4 4 1.10757e-15 +C1 5 4 3.0571e-14 +.ends buf_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/buf_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/buf_x4.spi new file mode 100644 index 000000000..fb92a667c --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/buf_x4.spi @@ -0,0 +1,25 @@ +* Spice description of buf_x4 +* Spice driver version -1111933157 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:14 + +* INTERF i q vdd vss + + +.subckt buf_x4 3 2 1 4 +* NET 1 = vdd +* NET 2 = q +* NET 3 = i +* NET 4 = vss +Xtr_00006 1 5 2 1 sg13_lv_pmos L=0.13U W=2.87U AS=0.6888P AD=0.6888P PS=6.22U PD=6.22U +Xtr_00005 2 5 1 1 sg13_lv_pmos L=0.13U W=2.87U AS=0.6888P AD=0.6888P PS=6.22U PD=6.22U +Xtr_00004 1 3 5 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00003 4 5 2 4 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00002 2 5 4 4 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00001 4 3 5 4 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C5 1 4 2.02028e-15 +C4 2 4 1.93831e-15 +C3 3 4 2.05599e-14 +C2 4 4 1.63195e-15 +C1 5 4 4.69917e-14 +.ends buf_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/buf_x8.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/buf_x8.spi new file mode 100644 index 000000000..9997f4e88 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/buf_x8.spi @@ -0,0 +1,29 @@ +* Spice description of buf_x8 +* Spice driver version 2057223963 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:14 + +* INTERF i q vdd vss + + +.subckt buf_x8 3 2 1 4 +* NET 1 = vdd +* NET 2 = q +* NET 3 = i +* NET 4 = vss +Xtr_00010 2 5 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 1 5 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 1 5 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 5 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 1 3 5 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 2 5 4 4 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 4 5 2 4 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 4 5 2 4 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 2 5 4 4 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 4 3 5 4 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C5 1 4 3.16371e-15 +C4 2 4 3.29763e-15 +C3 3 4 1.98449e-14 +C2 4 4 2.38705e-15 +C1 5 4 8.3284e-14 +.ends buf_x8 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x1.spi new file mode 100644 index 000000000..ed8f3f4b7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x1.spi @@ -0,0 +1,20 @@ +* Spice description of inv_x1 +* Spice driver version 212172571 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:14 + +* INTERF i nq vdd vss + + +.subckt inv_x1 2 4 1 3 +* NET 1 = vdd +* NET 2 = i +* NET 3 = vss +* NET 4 = nq +Xtr_00002 4 2 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00001 4 2 3 3 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C4 1 3 1.08664e-15 +C3 2 3 2.00735e-14 +C2 3 3 1.07285e-15 +C1 4 3 1.93831e-15 +.ends inv_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x2.spi new file mode 100644 index 000000000..366bca77a --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x2.spi @@ -0,0 +1,20 @@ +* Spice description of inv_x2 +* Spice driver version -1336692965 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:14 + +* INTERF i nq vdd vss + + +.subckt inv_x2 2 4 1 3 +* NET 1 = vdd +* NET 2 = i +* NET 3 = vss +* NET 4 = nq +Xtr_00002 4 2 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00001 4 2 3 3 sg13_lv_nmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +C4 1 3 1.10043e-15 +C3 2 3 1.81907e-14 +C2 3 3 1.0579e-15 +C1 4 3 1.99462e-15 +.ends inv_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x4.spi new file mode 100644 index 000000000..f9bdae9a7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x4.spi @@ -0,0 +1,22 @@ +* Spice description of inv_x4 +* Spice driver version -650809573 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:15 + +* INTERF i nq vdd vss + + +.subckt inv_x4 2 4 1 3 +* NET 1 = vdd +* NET 2 = i +* NET 3 = vss +* NET 4 = nq +Xtr_00004 4 2 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00003 1 2 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00002 3 2 4 3 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 4 2 3 3 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C4 1 3 1.78957e-15 +C3 2 3 4.15659e-14 +C2 3 3 1.40124e-15 +C1 4 3 1.93831e-15 +.ends inv_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x8.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x8.spi new file mode 100644 index 000000000..c03e6fbf4 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/inv_x8.spi @@ -0,0 +1,26 @@ +* Spice description of inv_x8 +* Spice driver version -937222373 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:15 + +* INTERF i nq vdd vss + + +.subckt inv_x8 2 4 1 3 +* NET 1 = vdd +* NET 2 = i +* NET 3 = vss +* NET 4 = nq +Xtr_00008 4 2 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 1 2 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 4 2 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 1 2 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00004 4 2 3 3 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 3 2 4 3 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 4 2 3 3 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 3 2 4 3 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C4 1 3 2.93299e-15 +C3 2 3 8.01992e-14 +C2 3 3 2.15634e-15 +C1 4 3 3.29763e-15 +.ends inv_x8 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx2_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx2_x2.spi new file mode 100644 index 000000000..ec72fcad1 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx2_x2.spi @@ -0,0 +1,36 @@ +* Spice description of mx2_x2 +* Spice driver version -1308258533 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:15 + +* INTERF cmd i0 i1 q vdd vss + + +.subckt mx2_x2 9 10 4 5 3 11 +* NET 3 = vdd +* NET 4 = i1 +* NET 5 = q +* NET 9 = cmd +* NET 10 = i0 +* NET 11 = vss +Xtr_00012 7 9 2 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00011 1 12 7 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00010 3 4 1 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00009 3 9 12 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 2 10 3 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00007 5 7 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 11 4 8 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 8 9 7 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 7 12 6 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 6 10 11 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 11 9 12 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 5 7 11 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C10 3 11 2.28632e-15 +C9 4 11 1.80023e-14 +C8 5 11 1.93831e-15 +C6 7 11 2.45636e-14 +C4 9 11 6.01647e-14 +C3 10 11 2.00085e-14 +C2 11 11 2.08674e-15 +C1 12 11 1.82808e-14 +.ends mx2_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx2_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx2_x4.spi new file mode 100644 index 000000000..f7eff87ba --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx2_x4.spi @@ -0,0 +1,38 @@ +* Spice description of mx2_x4 +* Spice driver version -375185637 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:15 + +* INTERF cmd i0 i1 q vdd vss + + +.subckt mx2_x4 9 10 5 4 3 11 +* NET 3 = vdd +* NET 4 = q +* NET 5 = i1 +* NET 9 = cmd +* NET 10 = i0 +* NET 11 = vss +Xtr_00014 4 7 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 3 5 2 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00012 1 10 3 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00011 3 9 12 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00010 2 12 7 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00009 7 9 1 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 3 7 4 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 11 5 6 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00006 6 9 7 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 7 12 8 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 8 10 11 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 11 9 12 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 4 7 11 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 11 7 4 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C10 3 11 3.87147e-15 +C9 4 11 1.93831e-15 +C8 5 11 2.12638e-14 +C6 7 11 4.32593e-14 +C4 9 11 5.39741e-14 +C3 10 11 1.7193e-14 +C2 11 11 3.02522e-15 +C1 12 11 1.60395e-14 +.ends mx2_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx3_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx3_x2.spi new file mode 100644 index 000000000..68e259f97 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx3_x2.spi @@ -0,0 +1,51 @@ +* Spice description of mx3_x2 +* Spice driver version -1653113061 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:16 + +* INTERF cmd0 cmd1 i0 i1 i2 q vdd vss + + +.subckt mx3_x2 9 17 7 11 13 6 5 19 +* NET 5 = vdd +* NET 6 = q +* NET 7 = i0 +* NET 9 = cmd0 +* NET 11 = i1 +* NET 13 = i2 +* NET 17 = cmd1 +* NET 19 = vss +Xtr_00020 4 13 3 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00019 6 16 5 5 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00018 5 9 10 5 sg13_lv_pmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00017 16 17 4 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00016 2 18 16 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00015 3 11 2 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00014 5 10 3 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00013 1 9 5 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00012 16 7 1 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00011 18 17 5 5 sg13_lv_pmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00010 15 13 14 19 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00009 19 9 10 19 sg13_lv_nmos L=0.13U W=0.62U AS=0.1488P AD=0.1488P PS=1.72U PD=1.72U +Xtr_00008 6 16 19 19 sg13_lv_nmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +Xtr_00007 16 18 15 19 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00006 12 17 16 19 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00005 14 11 12 19 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00004 8 10 19 19 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00003 18 17 19 19 sg13_lv_nmos L=0.13U W=0.62U AS=0.1488P AD=0.1488P PS=1.72U PD=1.72U +Xtr_00002 16 7 8 19 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00001 19 9 14 19 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +C17 3 19 7.34803e-16 +C15 5 19 3.74668e-15 +C14 6 19 2.04976e-15 +C13 7 19 2.1941e-14 +C11 9 19 4.54419e-14 +C10 10 19 3.07557e-14 +C9 11 19 2.36681e-14 +C7 13 19 2.37976e-14 +C6 14 19 7.21018e-16 +C4 16 19 1.96303e-14 +C3 17 19 4.58965e-14 +C2 18 19 1.72385e-14 +C1 19 19 3.47767e-15 +.ends mx3_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx3_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx3_x4.spi new file mode 100644 index 000000000..a44e3d345 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/mx3_x4.spi @@ -0,0 +1,53 @@ +* Spice description of mx3_x4 +* Spice driver version 812166939 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:16 + +* INTERF cmd0 cmd1 i0 i1 i2 q vdd vss + + +.subckt mx3_x4 8 16 7 10 12 6 5 18 +* NET 5 = vdd +* NET 6 = q +* NET 7 = i0 +* NET 8 = cmd0 +* NET 10 = i1 +* NET 12 = i2 +* NET 16 = cmd1 +* NET 18 = vss +Xtr_00022 5 8 9 5 sg13_lv_pmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00021 5 15 6 5 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00020 6 15 5 5 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00019 4 10 3 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00018 15 7 1 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00017 3 19 15 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00016 5 9 4 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00015 1 8 5 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00014 2 12 4 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00013 19 16 5 5 sg13_lv_pmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00012 15 16 2 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00011 18 8 9 18 sg13_lv_nmos L=0.13U W=0.69U AS=0.1656P AD=0.1656P PS=1.87U PD=1.87U +Xtr_00010 18 15 6 18 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00009 6 15 18 18 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 11 9 18 18 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00007 19 16 18 18 sg13_lv_nmos L=0.13U W=0.62U AS=0.1488P AD=0.1488P PS=1.72U PD=1.72U +Xtr_00006 14 12 17 18 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00005 15 19 14 18 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00004 13 16 15 18 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00003 17 10 13 18 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00002 15 7 11 18 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00001 18 8 17 18 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +C16 4 18 7.7616e-16 +C15 5 18 4.67336e-15 +C14 6 18 2.2446e-15 +C13 7 18 2.3532e-14 +C12 8 18 4.89787e-14 +C11 9 18 3.20805e-14 +C10 10 18 3.18977e-14 +C8 12 18 3.25523e-14 +C5 15 18 3.5902e-14 +C4 16 18 5.02108e-14 +C3 17 18 7.48589e-16 +C2 18 18 4.19931e-15 +C1 19 18 1.93794e-14 +.ends mx3_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na2_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na2_x1.spi new file mode 100644 index 000000000..8397082c1 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na2_x1.spi @@ -0,0 +1,24 @@ +* Spice description of na2_x1 +* Spice driver version 1377578779 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:16 + +* INTERF i0 i1 nq vdd vss + + +.subckt na2_x1 4 2 3 1 6 +* NET 1 = vdd +* NET 2 = i1 +* NET 3 = nq +* NET 4 = i0 +* NET 6 = vss +Xtr_00004 1 2 3 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00003 3 4 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00002 3 2 5 6 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00001 5 4 6 6 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +C6 1 6 1.55588e-15 +C5 2 6 2.33033e-14 +C4 3 6 2.08024e-15 +C3 4 6 2.26546e-14 +C1 6 6 1.24726e-15 +.ends na2_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na2_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na2_x4.spi new file mode 100644 index 000000000..d6322b316 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na2_x4.spi @@ -0,0 +1,32 @@ +* Spice description of na2_x4 +* Spice driver version 1444142875 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:17 + +* INTERF i0 i1 nq vdd vss + + +.subckt na2_x4 6 5 3 1 4 +* NET 1 = vdd +* NET 3 = nq +* NET 4 = vss +* NET 5 = i1 +* NET 6 = i0 +Xtr_00010 1 5 8 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00009 8 6 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00008 3 2 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 1 2 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 2 8 1 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00005 4 5 7 4 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00004 7 6 8 4 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00003 3 2 4 4 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00002 2 8 4 4 sg13_lv_nmos L=0.13U W=0.84U AS=0.2016P AD=0.2016P PS=2.17U PD=2.17U +Xtr_00001 4 2 3 4 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +C8 1 4 2.06581e-15 +C7 2 4 4.33156e-14 +C6 3 4 1.66143e-15 +C5 4 4 2.03707e-15 +C4 5 4 1.8559e-14 +C3 6 4 1.8559e-14 +C1 8 4 1.79825e-14 +.ends na2_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na3_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na3_x1.spi new file mode 100644 index 000000000..35e393996 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na3_x1.spi @@ -0,0 +1,28 @@ +* Spice description of na3_x1 +* Spice driver version 1547018011 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:17 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt na3_x1 5 6 2 4 1 8 +* NET 1 = vdd +* NET 2 = i2 +* NET 4 = nq +* NET 5 = i0 +* NET 6 = i1 +* NET 8 = vss +Xtr_00006 1 6 4 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00005 4 5 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00004 4 2 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00003 4 2 3 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 7 5 8 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 3 6 7 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C8 1 8 1.85553e-15 +C7 2 8 2.07469e-14 +C5 4 8 2.74648e-15 +C4 5 8 1.92629e-14 +C3 6 8 2.03187e-14 +C1 8 8 1.33828e-15 +.ends na3_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na3_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na3_x4.spi new file mode 100644 index 000000000..d0c56ed3b --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na3_x4.spi @@ -0,0 +1,36 @@ +* Spice description of na3_x4 +* Spice driver version -935764197 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:17 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt na3_x4 8 3 7 5 1 6 +* NET 1 = vdd +* NET 3 = i1 +* NET 5 = nq +* NET 6 = vss +* NET 7 = i2 +* NET 8 = i0 +Xtr_00012 1 2 5 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 5 2 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 1 3 10 1 sg13_lv_pmos L=0.13U W=2.34U AS=0.5616P AD=0.5616P PS=5.17U PD=5.17U +Xtr_00009 10 7 1 1 sg13_lv_pmos L=0.13U W=2.34U AS=0.5616P AD=0.5616P PS=5.17U PD=5.17U +Xtr_00008 1 8 10 1 sg13_lv_pmos L=0.13U W=2.34U AS=0.5616P AD=0.5616P PS=5.17U PD=5.17U +Xtr_00007 2 10 1 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00006 6 2 5 6 sg13_lv_nmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00005 5 2 6 6 sg13_lv_nmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00004 4 7 9 6 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00003 6 3 4 6 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00002 2 10 6 6 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00001 9 8 10 6 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +C10 1 6 2.08674e-15 +C9 2 6 3.73407e-14 +C8 3 6 1.46876e-14 +C6 5 6 1.71774e-15 +C5 6 6 2.43438e-15 +C4 7 6 1.46876e-14 +C3 8 6 1.61992e-14 +C1 10 6 1.76796e-14 +.ends na3_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na4_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na4_x1.spi new file mode 100644 index 000000000..37727f5de --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na4_x1.spi @@ -0,0 +1,32 @@ +* Spice description of na4_x1 +* Spice driver version 62734107 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:17 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt na4_x1 8 7 2 3 6 1 10 +* NET 1 = vdd +* NET 2 = i2 +* NET 3 = i3 +* NET 6 = nq +* NET 7 = i1 +* NET 8 = i0 +* NET 10 = vss +Xtr_00008 1 3 6 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00007 1 7 6 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00006 6 8 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00005 6 2 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00004 6 3 4 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 4 2 5 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 9 8 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 5 7 9 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C10 1 10 1.87762e-15 +C9 2 10 1.88347e-14 +C8 3 10 1.96148e-14 +C5 6 10 2.53966e-15 +C4 7 10 1.88347e-14 +C3 8 10 1.91866e-14 +C1 10 10 1.569e-15 +.ends na4_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na4_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na4_x4.spi new file mode 100644 index 000000000..2b893a464 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/na4_x4.spi @@ -0,0 +1,40 @@ +* Spice description of na4_x4 +* Spice driver version 1928847131 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:18 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt na4_x4 5 6 3 2 9 1 11 +* NET 1 = vdd +* NET 2 = i3 +* NET 3 = i2 +* NET 5 = i0 +* NET 6 = i1 +* NET 9 = nq +* NET 11 = vss +Xtr_00014 1 12 9 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 9 12 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 1 10 12 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00011 10 5 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00010 1 6 10 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00009 10 3 1 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00008 1 2 10 1 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00007 11 12 9 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00006 9 12 11 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 11 10 12 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 8 5 11 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 7 6 8 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 10 2 4 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 4 3 7 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C12 1 11 2.43007e-15 +C11 2 11 1.95386e-14 +C10 3 11 2.09464e-14 +C8 5 11 1.95386e-14 +C7 6 11 1.98905e-14 +C4 9 11 2.05734e-15 +C3 10 11 1.52642e-14 +C2 11 11 2.31745e-15 +C1 12 11 4.72809e-14 +.ends na4_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao22_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao22_x1.spi new file mode 100644 index 000000000..00d9d5e01 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao22_x1.spi @@ -0,0 +1,29 @@ +* Spice description of nao22_x1 +* Spice driver version -1818972389 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:18 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt nao22_x1 6 5 3 7 1 4 +* NET 1 = vdd +* NET 3 = i2 +* NET 4 = vss +* NET 5 = i1 +* NET 6 = i0 +* NET 7 = nq +Xtr_00006 1 3 7 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 7 5 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00004 2 6 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00003 4 3 8 4 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00002 8 5 7 4 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00001 7 6 8 4 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +C8 1 4 1.39459e-15 +C6 3 4 2.26299e-14 +C5 4 4 1.33828e-15 +C4 5 4 1.57434e-14 +C3 6 4 1.50395e-14 +C2 7 4 2.15177e-15 +C1 8 4 3.90167e-16 +.ends nao22_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao22_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao22_x4.spi new file mode 100644 index 000000000..b598c39b2 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao22_x4.spi @@ -0,0 +1,37 @@ +* Spice description of nao22_x4 +* Spice driver version -333807845 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:18 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt nao22_x4 6 5 8 4 2 10 +* NET 2 = vdd +* NET 4 = nq +* NET 5 = i1 +* NET 6 = i0 +* NET 8 = i2 +* NET 10 = vss +Xtr_00012 2 3 4 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 4 3 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 1 5 7 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00009 2 6 1 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 7 8 2 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00007 2 7 3 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00006 4 3 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 10 3 4 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 7 5 9 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 9 8 10 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 9 6 7 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 10 7 3 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C9 2 10 3.87331e-15 +C8 3 10 4.01623e-14 +C7 4 10 1.99345e-15 +C6 5 10 2.70914e-14 +C5 6 10 2.60261e-14 +C4 7 10 1.64383e-14 +C3 8 10 2.27061e-14 +C2 9 10 5.00451e-16 +C1 10 10 3.03967e-15 +.ends nao22_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao2o22_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao2o22_x1.spi new file mode 100644 index 000000000..43f043695 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao2o22_x1.spi @@ -0,0 +1,33 @@ +* Spice description of nao2o22_x1 +* Spice driver version 9346843 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:19 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt nao2o22_x1 8 6 4 5 9 2 7 +* NET 2 = vdd +* NET 4 = i2 +* NET 5 = i3 +* NET 6 = i1 +* NET 7 = vss +* NET 8 = i0 +* NET 9 = nq +Xtr_00008 2 4 1 2 sg13_lv_pmos L=0.13U W=3.24U AS=0.7776P AD=0.7776P PS=6.97U PD=6.97U +Xtr_00007 1 5 9 2 sg13_lv_pmos L=0.13U W=3.24U AS=0.7776P AD=0.7776P PS=6.97U PD=6.97U +Xtr_00006 9 6 3 2 sg13_lv_pmos L=0.13U W=3.24U AS=0.7776P AD=0.7776P PS=6.97U PD=6.97U +Xtr_00005 3 8 2 2 sg13_lv_pmos L=0.13U W=3.24U AS=0.7776P AD=0.7776P PS=6.97U PD=6.97U +Xtr_00004 10 4 7 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 7 5 10 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 9 8 10 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 10 6 9 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C9 2 7 1.55555e-15 +C7 4 7 1.46389e-14 +C6 5 7 1.97158e-14 +C5 6 7 1.94401e-14 +C4 7 7 1.49924e-15 +C3 8 7 1.50671e-14 +C2 9 7 2.09132e-15 +C1 10 7 8.3247e-16 +.ends nao2o22_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao2o22_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao2o22_x4.spi new file mode 100644 index 000000000..40df5d6f9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nao2o22_x4.spi @@ -0,0 +1,41 @@ +* Spice description of nao2o22_x4 +* Spice driver version 2054246171 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:19 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt nao2o22_x4 10 7 6 8 4 3 9 +* NET 3 = vdd +* NET 4 = nq +* NET 6 = i2 +* NET 7 = i1 +* NET 8 = i3 +* NET 9 = vss +* NET 10 = i0 +Xtr_00014 1 8 11 3 sg13_lv_pmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +Xtr_00013 3 6 1 3 sg13_lv_pmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +Xtr_00012 11 7 2 3 sg13_lv_pmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +Xtr_00011 4 5 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 3 5 4 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 2 10 3 3 sg13_lv_pmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +Xtr_00008 3 11 5 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00007 12 6 9 9 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00006 4 5 9 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 9 5 4 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 12 7 11 9 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00003 11 10 12 9 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00002 9 11 5 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 9 8 12 9 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +C10 3 9 3.67183e-15 +C9 4 9 1.99345e-15 +C8 5 9 3.99639e-14 +C7 6 9 2.71959e-14 +C6 7 9 2.43397e-14 +C5 8 9 2.35092e-14 +C4 9 9 3.25477e-15 +C3 10 9 1.8559e-14 +C2 11 9 2.18104e-14 +C1 12 9 8.18684e-16 +.ends nao2o22_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nmx2_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nmx2_x1.spi new file mode 100644 index 000000000..1ffa884a2 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nmx2_x1.spi @@ -0,0 +1,34 @@ +* Spice description of nmx2_x1 +* Spice driver version 1104228123 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:19 + +* INTERF cmd i0 i1 nq vdd vss + + +.subckt nmx2_x1 8 9 4 7 3 10 +* NET 3 = vdd +* NET 4 = i1 +* NET 7 = nq +* NET 8 = cmd +* NET 9 = i0 +* NET 10 = vss +* NET 11 = q +Xtr_00010 3 4 1 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 7 8 2 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 2 9 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 3 8 11 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00006 1 11 7 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 10 4 5 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 7 11 6 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 6 9 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 10 8 11 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 5 8 7 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C9 3 10 1.85602e-15 +C8 4 10 1.9138e-14 +C5 7 10 1.66327e-15 +C4 8 10 4.22155e-14 +C3 9 10 1.19689e-14 +C2 10 10 1.85602e-15 +C1 11 10 1.52849e-14 +.ends nmx2_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nmx2_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nmx2_x4.spi new file mode 100644 index 000000000..0692d069d --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nmx2_x4.spi @@ -0,0 +1,41 @@ +* Spice description of nmx2_x4 +* Spice driver version -119070949 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:20 + +* INTERF cmd i0 i1 nq vdd vss + + +.subckt nmx2_x4 10 11 6 4 3 13 +* NET 3 = vdd +* NET 4 = nq +* NET 6 = i1 +* NET 10 = cmd +* NET 11 = i0 +* NET 13 = vss +Xtr_00016 3 5 4 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00015 4 5 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00014 5 8 3 3 sg13_lv_pmos L=0.13U W=2.04U AS=0.4896P AD=0.4896P PS=4.57U PD=4.57U +Xtr_00013 3 6 2 3 sg13_lv_pmos L=0.13U W=2.04U AS=0.4896P AD=0.4896P PS=4.57U PD=4.57U +Xtr_00012 2 12 8 3 sg13_lv_pmos L=0.13U W=2.04U AS=0.4896P AD=0.4896P PS=4.57U PD=4.57U +Xtr_00011 8 10 1 3 sg13_lv_pmos L=0.13U W=2.04U AS=0.4896P AD=0.4896P PS=4.57U PD=4.57U +Xtr_00010 1 11 3 3 sg13_lv_pmos L=0.13U W=2.04U AS=0.4896P AD=0.4896P PS=4.57U PD=4.57U +Xtr_00009 3 10 12 3 sg13_lv_pmos L=0.13U W=2.04U AS=0.4896P AD=0.4896P PS=4.57U PD=4.57U +Xtr_00008 13 5 4 13 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00007 4 5 13 13 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00006 5 8 13 13 sg13_lv_nmos L=0.13U W=0.69U AS=0.1656P AD=0.1656P PS=1.87U PD=1.87U +Xtr_00005 13 6 9 13 sg13_lv_nmos L=0.13U W=0.69U AS=0.1656P AD=0.1656P PS=1.87U PD=1.87U +Xtr_00004 9 10 8 13 sg13_lv_nmos L=0.13U W=0.69U AS=0.1656P AD=0.1656P PS=1.87U PD=1.87U +Xtr_00003 8 12 7 13 sg13_lv_nmos L=0.13U W=0.69U AS=0.1656P AD=0.1656P PS=1.87U PD=1.87U +Xtr_00002 13 10 12 13 sg13_lv_nmos L=0.13U W=0.69U AS=0.1656P AD=0.1656P PS=1.87U PD=1.87U +Xtr_00001 7 11 13 13 sg13_lv_nmos L=0.13U W=0.69U AS=0.1656P AD=0.1656P PS=1.87U PD=1.87U +C11 3 13 4.03259e-15 +C10 4 13 1.99345e-15 +C9 5 13 3.60063e-14 +C8 6 13 1.83395e-14 +C6 8 13 3.066e-14 +C4 10 13 5.26214e-14 +C3 11 13 1.82277e-14 +C2 12 13 1.58286e-14 +C1 13 13 3.25593e-15 +.ends nmx2_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nmx3_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nmx3_x1.spi new file mode 100644 index 000000000..23ce75c52 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nmx3_x1.spi @@ -0,0 +1,48 @@ +* Spice description of nmx3_x1 +* Spice driver version 658792219 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:20 + +* INTERF cmd0 cmd1 i0 i1 i2 nq vdd vss + + +.subckt nmx3_x1 9 15 6 10 12 14 5 16 +* NET 5 = vdd +* NET 6 = i0 +* NET 9 = cmd0 +* NET 10 = i1 +* NET 12 = i2 +* NET 14 = nq +* NET 15 = cmd1 +* NET 16 = vss +Xtr_00018 3 12 4 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00017 14 15 3 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00016 5 8 4 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00015 4 10 2 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00014 17 15 5 5 sg13_lv_pmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00013 2 17 14 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00012 1 9 5 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00011 14 6 1 5 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00010 5 9 8 5 sg13_lv_pmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00009 13 12 18 16 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00008 14 17 13 16 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00007 11 15 14 16 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00006 18 10 11 16 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00005 7 8 16 16 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00004 17 15 16 16 sg13_lv_nmos L=0.13U W=0.62U AS=0.1488P AD=0.1488P PS=1.72U PD=1.72U +Xtr_00003 16 9 8 16 sg13_lv_nmos L=0.13U W=0.62U AS=0.1488P AD=0.1488P PS=1.72U PD=1.72U +Xtr_00002 14 6 7 16 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00001 16 9 18 16 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +C15 4 16 8.03731e-16 +C14 5 16 3.45557e-15 +C13 6 16 2.20034e-14 +C11 8 16 3.07436e-14 +C10 9 16 4.6641e-14 +C9 10 16 2.88137e-14 +C7 12 16 2.36579e-14 +C5 14 16 3.48588e-15 +C4 15 16 4.83739e-14 +C3 16 16 3.28831e-15 +C2 17 16 2.23881e-14 +C1 18 16 7.48589e-16 +.ends nmx3_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no2_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no2_x1.spi new file mode 100644 index 000000000..6dca592ac --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no2_x1.spi @@ -0,0 +1,24 @@ +* Spice description of no2_x1 +* Spice driver version 1034870555 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:20 + +* INTERF i0 i1 nq vdd vss + + +.subckt no2_x1 3 4 5 1 6 +* NET 1 = vdd +* NET 3 = i0 +* NET 4 = i1 +* NET 5 = nq +* NET 6 = vss +Xtr_00004 2 4 5 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00003 1 3 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00002 6 3 5 6 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00001 5 4 6 6 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +C6 1 6 1.10757e-15 +C4 3 6 2.32077e-14 +C3 4 6 2.17999e-14 +C2 5 6 2.13655e-15 +C1 6 6 1.31919e-15 +.ends no2_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no2_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no2_x4.spi new file mode 100644 index 000000000..e5c65bb17 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no2_x4.spi @@ -0,0 +1,32 @@ +* Spice description of no2_x4 +* Spice driver version -176578789 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:20 + +* INTERF i0 i1 nq vdd vss + + +.subckt no2_x4 5 6 4 1 8 +* NET 1 = vdd +* NET 4 = nq +* NET 5 = i0 +* NET 6 = i1 +* NET 8 = vss +Xtr_00010 1 5 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 2 6 7 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 1 3 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 4 3 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 3 7 1 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00005 8 5 7 8 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 7 6 8 8 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 4 3 8 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 8 3 4 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 3 7 8 8 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C8 1 8 1.85602e-15 +C6 3 8 3.21505e-14 +C5 4 8 1.48222e-15 +C4 5 8 1.53915e-14 +C3 6 8 1.53915e-14 +C2 7 8 2.21735e-14 +C1 8 8 2.19172e-15 +.ends no2_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no3_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no3_x1.spi new file mode 100644 index 000000000..61f7aeaf9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no3_x1.spi @@ -0,0 +1,28 @@ +* Spice description of no3_x1 +* Spice driver version -202014949 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:21 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt no3_x1 4 6 5 8 1 7 +* NET 1 = vdd +* NET 4 = i0 +* NET 5 = i2 +* NET 6 = i1 +* NET 7 = vss +* NET 8 = nq +Xtr_00006 1 5 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 2 4 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00004 3 6 8 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00003 7 5 8 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 8 4 7 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 7 6 8 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C8 1 7 1.33828e-15 +C5 4 7 1.98384e-14 +C4 5 7 2.03159e-14 +C3 6 7 2.07834e-14 +C2 7 7 1.43662e-15 +C1 8 7 2.53758e-15 +.ends no3_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no3_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no3_x4.spi new file mode 100644 index 000000000..aa94fff7a --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no3_x4.spi @@ -0,0 +1,36 @@ +* Spice description of no3_x4 +* Spice driver version -686907621 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:21 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt no3_x4 5 7 8 6 1 10 +* NET 1 = vdd +* NET 5 = i0 +* NET 6 = nq +* NET 7 = i1 +* NET 8 = i2 +* NET 10 = vss +Xtr_00012 1 5 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 2 7 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 3 8 9 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 4 9 1 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 1 4 6 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 6 4 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 10 8 9 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 4 9 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 6 4 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 10 5 9 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 9 7 10 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 10 4 6 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C10 1 10 2.08674e-15 +C7 4 10 3.54006e-14 +C6 5 10 1.78551e-14 +C5 6 10 1.5562e-15 +C4 7 10 1.78551e-14 +C3 8 10 1.57434e-14 +C2 9 10 2.23053e-14 +C1 10 10 2.08674e-15 +.ends no3_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no4_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no4_x1.spi new file mode 100644 index 000000000..983ad5ba9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no4_x1.spi @@ -0,0 +1,32 @@ +* Spice description of no4_x1 +* Spice driver version 145178395 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:21 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt no4_x1 7 8 6 5 9 1 10 +* NET 1 = vdd +* NET 5 = i3 +* NET 6 = i2 +* NET 7 = i0 +* NET 8 = i1 +* NET 9 = nq +* NET 10 = vss +Xtr_00008 3 6 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 7 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 4 8 9 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 1 5 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00004 10 5 9 10 sg13_lv_nmos L=0.13U W=0.84U AS=0.2016P AD=0.2016P PS=2.17U PD=2.17U +Xtr_00003 9 6 10 10 sg13_lv_nmos L=0.13U W=0.84U AS=0.2016P AD=0.2016P PS=2.17U PD=2.17U +Xtr_00002 10 7 9 10 sg13_lv_nmos L=0.13U W=0.84U AS=0.2016P AD=0.2016P PS=2.17U PD=2.17U +Xtr_00001 9 8 10 10 sg13_lv_nmos L=0.13U W=0.84U AS=0.2016P AD=0.2016P PS=2.17U PD=2.17U +C10 1 10 1.569e-15 +C6 5 10 2.13371e-14 +C5 6 10 1.9251e-14 +C4 7 10 2.11354e-14 +C3 8 10 1.98531e-14 +C2 9 10 2.56699e-15 +C1 10 10 2.08691e-15 +.ends no4_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no4_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no4_x4.spi new file mode 100644 index 000000000..0682a95cb --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/no4_x4.spi @@ -0,0 +1,40 @@ +* Spice description of no4_x4 +* Spice driver version -229077221 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:22 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt no4_x4 7 10 8 9 6 1 12 +* NET 1 = vdd +* NET 6 = nq +* NET 7 = i0 +* NET 8 = i2 +* NET 9 = i3 +* NET 10 = i1 +* NET 12 = vss +Xtr_00014 2 7 3 1 sg13_lv_pmos L=0.13U W=3.02U AS=0.7248P AD=0.7248P PS=6.52U PD=6.52U +Xtr_00013 4 8 2 1 sg13_lv_pmos L=0.13U W=3.02U AS=0.7248P AD=0.7248P PS=6.52U PD=6.52U +Xtr_00012 1 9 4 1 sg13_lv_pmos L=0.13U W=3.02U AS=0.7248P AD=0.7248P PS=6.52U PD=6.52U +Xtr_00011 5 11 1 1 sg13_lv_pmos L=0.13U W=1.59U AS=0.3816P AD=0.3816P PS=3.67U PD=3.67U +Xtr_00010 1 5 6 1 sg13_lv_pmos L=0.13U W=3.02U AS=0.7248P AD=0.7248P PS=6.52U PD=6.52U +Xtr_00009 6 5 1 1 sg13_lv_pmos L=0.13U W=3.02U AS=0.7248P AD=0.7248P PS=6.52U PD=6.52U +Xtr_00008 3 10 11 1 sg13_lv_pmos L=0.13U W=3.02U AS=0.7248P AD=0.7248P PS=6.52U PD=6.52U +Xtr_00007 12 5 6 12 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00006 6 5 12 12 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 11 10 12 12 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 11 8 12 12 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 12 9 11 12 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 12 7 11 12 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 5 11 12 12 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C12 1 12 3.30366e-15 +C8 5 12 5.13782e-14 +C7 6 12 1.74532e-15 +C6 7 12 1.74269e-14 +C5 8 12 1.60191e-14 +C4 9 12 1.53152e-14 +C3 10 12 1.63711e-14 +C2 11 12 1.96921e-14 +C1 12 12 2.64543e-15 +.ends no4_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa22_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa22_x1.spi new file mode 100644 index 000000000..3860ff421 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa22_x1.spi @@ -0,0 +1,29 @@ +* Spice description of noa22_x1 +* Spice driver version 1120378651 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:22 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt noa22_x1 6 5 3 4 1 8 +* NET 1 = vdd +* NET 3 = i2 +* NET 4 = nq +* NET 5 = i1 +* NET 6 = i0 +* NET 8 = vss +Xtr_00006 1 3 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 2 5 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00004 4 6 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00003 8 3 4 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 4 5 7 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 7 6 8 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C8 1 8 1.33828e-15 +C7 2 8 6.41311e-16 +C6 3 8 2.05182e-14 +C5 4 8 1.91482e-15 +C4 5 8 1.47638e-14 +C3 6 8 1.60954e-14 +C1 8 8 1.39459e-15 +.ends noa22_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa22_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa22_x4.spi new file mode 100644 index 000000000..f30a6a3b7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa22_x4.spi @@ -0,0 +1,37 @@ +* Spice description of noa22_x4 +* Spice driver version -1923674341 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:22 + +* INTERF i0 i1 i2 nq vdd vss + + +.subckt noa22_x4 4 7 8 3 2 10 +* NET 2 = vdd +* NET 3 = nq +* NET 4 = i0 +* NET 7 = i1 +* NET 8 = i2 +* NET 10 = vss +Xtr_00012 2 6 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 2 9 6 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00010 1 4 9 2 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00009 9 7 1 2 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00008 1 8 2 2 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00007 3 6 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 10 6 3 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 10 9 6 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 10 4 5 10 sg13_lv_nmos L=0.13U W=1.14U AS=0.2736P AD=0.2736P PS=2.77U PD=2.77U +Xtr_00003 5 7 9 10 sg13_lv_nmos L=0.13U W=1.14U AS=0.2736P AD=0.2736P PS=2.77U PD=2.77U +Xtr_00002 9 8 10 10 sg13_lv_nmos L=0.13U W=1.14U AS=0.2736P AD=0.2736P PS=2.77U PD=2.77U +Xtr_00001 3 6 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C10 1 10 4.31523e-16 +C9 2 10 3.40524e-15 +C8 3 10 2.02102e-15 +C7 4 10 2.76544e-14 +C5 6 10 4.3149e-14 +C4 7 10 2.70057e-14 +C3 8 10 1.8559e-14 +C2 9 10 2.07676e-14 +C1 10 10 2.93362e-15 +.ends noa22_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a22_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a22_x1.spi new file mode 100644 index 000000000..9cbac592d --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a22_x1.spi @@ -0,0 +1,33 @@ +* Spice description of noa2a22_x1 +* Spice driver version -496750821 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:22 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt noa2a22_x1 8 7 4 3 6 1 10 +* NET 1 = vdd +* NET 3 = i3 +* NET 4 = i2 +* NET 6 = nq +* NET 7 = i1 +* NET 8 = i0 +* NET 10 = vss +Xtr_00008 2 7 6 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 6 8 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 1 3 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 2 4 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00004 6 7 9 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 9 8 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 5 3 6 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 10 4 5 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C10 1 10 1.569e-15 +C9 2 10 8.6004e-16 +C8 3 10 1.53152e-14 +C7 4 10 1.6723e-14 +C5 6 10 1.89763e-15 +C4 7 10 1.50395e-14 +C3 8 10 1.50395e-14 +C1 10 10 1.62531e-15 +.ends noa2a22_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a22_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a22_x4.spi new file mode 100644 index 000000000..7e207ed30 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a22_x4.spi @@ -0,0 +1,41 @@ +* Spice description of noa2a22_x4 +* Spice driver version -1866387685 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:23 + +* INTERF i0 i1 i2 i3 nq vdd vss + + +.subckt noa2a22_x4 10 9 6 5 3 2 12 +* NET 2 = vdd +* NET 3 = nq +* NET 5 = i3 +* NET 6 = i2 +* NET 9 = i1 +* NET 10 = i0 +* NET 12 = vss +Xtr_00014 1 9 7 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00013 7 10 1 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00012 3 4 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 2 4 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 2 7 4 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00009 1 6 2 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 2 5 1 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00007 7 9 11 12 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00006 11 10 12 12 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 3 4 12 12 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 12 4 3 12 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 12 7 4 12 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 8 5 7 12 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 12 6 8 12 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C12 1 12 8.6004e-16 +C11 2 12 3.78095e-15 +C10 3 12 1.99345e-15 +C9 4 12 3.13076e-14 +C8 5 12 2.4894e-14 +C7 6 12 2.13745e-14 +C6 7 12 2.15407e-14 +C4 9 12 1.8559e-14 +C3 10 12 1.83108e-14 +C1 12 12 3.58223e-15 +.ends noa2a22_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a23_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a23_x1.spi new file mode 100644 index 000000000..c1c0b4c7e --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a23_x1.spi @@ -0,0 +1,42 @@ +* Spice description of noa2a2a23_x1 +* Spice driver version -647590117 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:23 + +* INTERF i0 i1 i2 i3 i4 i5 nq vdd vss + + +.subckt noa2a2a23_x1 5 4 8 7 11 12 10 1 14 +* NET 1 = vdd +* NET 4 = i1 +* NET 5 = i0 +* NET 7 = i3 +* NET 8 = i2 +* NET 10 = nq +* NET 11 = i4 +* NET 12 = i5 +* NET 14 = vss +Xtr_00012 10 12 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 3 11 10 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 2 7 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 3 8 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 1 5 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 4 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 9 7 10 14 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 14 8 9 14 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 6 4 10 14 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 14 5 6 14 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 10 11 13 14 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 13 12 14 14 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C14 1 14 2.72688e-15 +C13 2 14 7.65866e-16 +C12 3 14 7.49757e-16 +C11 4 14 1.47638e-14 +C10 5 14 1.47638e-14 +C8 7 14 2.37121e-14 +C7 8 14 2.25066e-14 +C5 10 14 2.47172e-15 +C4 11 14 2.51924e-14 +C3 12 14 1.86241e-14 +C1 14 14 2.42542e-15 +.ends noa2a2a23_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a23_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a23_x4.spi new file mode 100644 index 000000000..97738bfb1 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a23_x4.spi @@ -0,0 +1,50 @@ +* Spice description of noa2a2a23_x4 +* Spice driver version 1658261275 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:23 + +* INTERF i0 i1 i2 i3 i4 i5 nq vdd vss + + +.subckt noa2a2a23_x4 6 7 11 10 9 15 5 1 16 +* NET 1 = vdd +* NET 5 = nq +* NET 6 = i0 +* NET 7 = i1 +* NET 9 = i4 +* NET 10 = i3 +* NET 11 = i2 +* NET 15 = i5 +* NET 16 = vss +Xtr_00018 1 6 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00017 14 15 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00016 3 9 14 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00015 2 10 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00014 3 11 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 1 4 5 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 5 4 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 2 7 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 4 14 1 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00009 16 6 8 16 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00008 13 15 16 16 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00007 14 9 13 16 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00006 12 10 14 16 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 16 11 12 16 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 16 4 5 16 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 5 4 16 16 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 8 7 14 16 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 4 14 16 16 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C16 1 16 4.23171e-15 +C15 2 16 7.50427e-16 +C14 3 16 7.91113e-16 +C13 4 16 3.53148e-14 +C12 5 16 1.80046e-15 +C11 6 16 1.47638e-14 +C10 7 16 1.75794e-14 +C8 9 16 1.47638e-14 +C7 10 16 1.54677e-14 +C6 11 16 1.51158e-14 +C3 14 16 1.91094e-14 +C2 15 16 1.51158e-14 +C1 16 16 3.35293e-15 +.ends noa2a2a23_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a2a24_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a2a24_x1.spi new file mode 100644 index 000000000..de2e18bad --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a2a24_x1.spi @@ -0,0 +1,51 @@ +* Spice description of noa2a2a2a24_x1 +* Spice driver version -970170597 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:24 + +* INTERF i0 i1 i2 i3 i4 i5 i6 i7 nq vdd vss + + +.subckt noa2a2a2a24_x1 6 5 8 9 11 12 13 16 15 1 18 +* NET 1 = vdd +* NET 5 = i1 +* NET 6 = i0 +* NET 8 = i2 +* NET 9 = i3 +* NET 11 = i4 +* NET 12 = i5 +* NET 13 = i6 +* NET 15 = nq +* NET 16 = i7 +* NET 18 = vss +Xtr_00016 2 5 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00015 1 6 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00014 2 9 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 3 8 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 3 11 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 4 12 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 4 13 15 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 15 16 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 7 5 15 18 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00007 18 6 7 18 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00006 18 8 10 18 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00005 10 9 15 18 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00004 15 11 14 18 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00003 14 12 18 18 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00002 15 13 17 18 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00001 17 16 18 18 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +C18 1 18 2.93601e-15 +C17 2 18 7.8987e-16 +C16 3 18 1.0009e-15 +C15 4 18 1.26767e-15 +C14 5 18 1.51158e-14 +C13 6 18 1.50395e-14 +C11 8 18 2.20688e-14 +C10 9 18 2.17169e-14 +C8 11 18 2.17169e-14 +C7 12 18 2.17169e-14 +C6 13 18 2.04337e-14 +C4 15 18 2.67991e-15 +C3 16 18 2.20064e-14 +C1 18 18 3.03119e-15 +.ends noa2a2a2a24_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a2a24_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a2a24_x4.spi new file mode 100644 index 000000000..a159f655f --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2a2a2a24_x4.spi @@ -0,0 +1,59 @@ +* Spice description of noa2a2a2a24_x4 +* Spice driver version -108110053 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:24 + +* INTERF i0 i1 i2 i3 i4 i5 i6 i7 nq vdd vss + + +.subckt noa2a2a2a24_x4 6 7 10 11 13 14 17 18 9 2 20 +* NET 2 = vdd +* NET 6 = i0 +* NET 7 = i1 +* NET 9 = nq +* NET 10 = i2 +* NET 11 = i3 +* NET 13 = i4 +* NET 14 = i5 +* NET 17 = i6 +* NET 18 = i7 +* NET 20 = vss +Xtr_00022 5 15 2 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00021 2 5 9 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00020 9 5 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00019 2 6 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00018 1 7 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00017 3 10 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00016 1 11 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00015 3 13 4 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00014 4 14 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 4 17 15 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 15 18 4 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 5 15 20 20 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00010 20 5 9 20 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00009 9 5 20 20 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00008 20 6 8 20 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00007 8 7 15 20 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00006 20 10 12 20 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 12 11 15 20 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 15 13 16 20 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 16 14 20 20 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 15 17 19 20 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 19 18 20 20 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C20 1 20 7.52081e-16 +C19 2 20 4.51629e-15 +C18 3 20 9.61383e-16 +C17 4 20 9.61383e-16 +C16 5 20 2.9742e-14 +C15 6 20 1.47638e-14 +C14 7 20 1.54677e-14 +C12 9 20 2.48991e-15 +C11 10 20 1.47638e-14 +C10 11 20 1.51158e-14 +C8 13 20 1.47638e-14 +C7 14 20 1.47638e-14 +C6 15 20 2.02278e-14 +C4 17 20 1.47638e-14 +C3 18 20 1.50395e-14 +C1 20 20 3.63995e-15 +.ends noa2a2a2a24_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2ao222_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2ao222_x1.spi new file mode 100644 index 000000000..58f1406e4 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2ao222_x1.spi @@ -0,0 +1,38 @@ +* Spice description of noa2ao222_x1 +* Spice driver version -1590604005 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:24 + +* INTERF i0 i1 i2 i3 i4 nq vdd vss + + +.subckt noa2ao222_x1 10 9 5 4 6 7 3 12 +* NET 3 = vdd +* NET 4 = i3 +* NET 5 = i2 +* NET 6 = i4 +* NET 7 = nq +* NET 9 = i1 +* NET 10 = i0 +* NET 12 = vss +Xtr_00010 2 4 1 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 1 5 7 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 7 6 2 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 9 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 3 10 2 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 8 4 12 12 sg13_lv_nmos L=0.13U W=1.97U AS=0.4728P AD=0.4728P PS=4.42U PD=4.42U +Xtr_00004 12 5 8 12 sg13_lv_nmos L=0.13U W=1.97U AS=0.4728P AD=0.4728P PS=4.42U PD=4.42U +Xtr_00003 8 6 7 12 sg13_lv_nmos L=0.13U W=1.97U AS=0.4728P AD=0.4728P PS=4.42U PD=4.42U +Xtr_00002 7 9 11 12 sg13_lv_nmos L=0.13U W=1.97U AS=0.4728P AD=0.4728P PS=4.42U PD=4.42U +Xtr_00001 11 10 12 12 sg13_lv_nmos L=0.13U W=1.97U AS=0.4728P AD=0.4728P PS=4.42U PD=4.42U +C11 2 12 9.70324e-16 +C10 3 12 1.79971e-15 +C9 4 12 1.6245e-14 +C8 5 12 1.8135e-14 +C7 6 12 1.69143e-14 +C6 7 12 1.72074e-15 +C5 8 12 4.45309e-16 +C4 9 12 1.719e-14 +C3 10 12 1.2224e-14 +C1 12 12 2.1056e-15 +.ends noa2ao222_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2ao222_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2ao222_x4.spi new file mode 100644 index 000000000..440e93ee5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa2ao222_x4.spi @@ -0,0 +1,46 @@ +* Spice description of noa2ao222_x4 +* Spice driver version -677781733 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:24 + +* INTERF i0 i1 i2 i3 i4 nq vdd vss + + +.subckt noa2ao222_x4 10 11 7 5 8 4 3 14 +* NET 3 = vdd +* NET 4 = nq +* NET 5 = i3 +* NET 7 = i2 +* NET 8 = i4 +* NET 10 = i0 +* NET 11 = i1 +* NET 14 = vss +Xtr_00016 1 7 13 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00015 2 5 1 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00014 2 11 3 3 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00013 3 6 4 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 4 6 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 13 8 2 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 3 10 2 3 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00009 3 13 6 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 9 5 14 14 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00007 14 7 9 14 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00006 9 8 13 14 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00005 14 6 4 14 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00004 4 6 14 14 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00003 12 10 14 14 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00002 13 11 12 14 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00001 14 13 6 14 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C13 2 14 1.02547e-15 +C12 3 14 4.03924e-15 +C11 4 14 2.04976e-15 +C10 5 14 1.20245e-14 +C9 6 14 3.26631e-14 +C8 7 14 1.66732e-14 +C7 8 14 1.44119e-14 +C6 9 14 6.83154e-16 +C5 10 14 1.25759e-14 +C4 11 14 1.53915e-14 +C2 13 14 1.75274e-14 +C1 14 14 4.10029e-15 +.ends noa2ao222_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa3ao322_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa3ao322_x1.spi new file mode 100644 index 000000000..271b5c21d --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa3ao322_x1.spi @@ -0,0 +1,46 @@ +* Spice description of noa3ao322_x1 +* Spice driver version -600080613 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:25 + +* INTERF i0 i1 i2 i3 i4 i5 i6 nq vdd vss + + +.subckt noa3ao322_x1 14 13 9 5 6 7 8 10 4 16 +* NET 4 = vdd +* NET 5 = i3 +* NET 6 = i4 +* NET 7 = i5 +* NET 8 = i6 +* NET 9 = i2 +* NET 10 = nq +* NET 13 = i1 +* NET 14 = i0 +* NET 16 = vss +Xtr_00014 10 8 3 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 3 9 4 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 4 13 3 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 3 14 4 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 2 5 10 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 1 6 2 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 3 7 1 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 11 8 10 16 sg13_lv_nmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +Xtr_00006 10 9 12 16 sg13_lv_nmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +Xtr_00005 12 13 15 16 sg13_lv_nmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +Xtr_00004 15 14 16 16 sg13_lv_nmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +Xtr_00003 16 5 11 16 sg13_lv_nmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +Xtr_00002 11 6 16 16 sg13_lv_nmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +Xtr_00001 16 7 11 16 sg13_lv_nmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +C14 3 16 1.17711e-15 +C13 4 16 2.45714e-15 +C12 5 16 1.1872e-14 +C11 6 16 1.1872e-14 +C10 7 16 1.1872e-14 +C9 8 16 1.09687e-14 +C8 9 16 1.1872e-14 +C7 10 16 1.74831e-15 +C6 11 16 4.86665e-16 +C4 13 16 1.21477e-14 +C3 14 16 1.15201e-14 +C1 16 16 2.6875e-15 +.ends noa3ao322_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa3ao322_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa3ao322_x4.spi new file mode 100644 index 000000000..4f82013db --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/noa3ao322_x4.spi @@ -0,0 +1,54 @@ +* Spice description of noa3ao322_x4 +* Spice driver version 939536155 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:25 + +* INTERF i0 i1 i2 i3 i4 i5 i6 nq vdd vss + + +.subckt noa3ao322_x4 13 10 8 6 7 5 9 15 4 18 +* NET 4 = vdd +* NET 5 = i5 +* NET 6 = i3 +* NET 7 = i4 +* NET 8 = i2 +* NET 9 = i6 +* NET 10 = i1 +* NET 13 = i0 +* NET 15 = nq +* NET 18 = vss +Xtr_00020 3 13 4 4 sg13_lv_pmos L=0.13U W=1.67U AS=0.4008P AD=0.4008P PS=3.82U PD=3.82U +Xtr_00019 16 9 3 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00018 3 8 4 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00017 1 6 16 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00016 2 7 1 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00015 3 5 2 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00014 4 10 3 4 sg13_lv_pmos L=0.13U W=1.67U AS=0.4008P AD=0.4008P PS=3.82U PD=3.82U +Xtr_00013 15 17 4 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 4 17 15 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 4 16 17 4 sg13_lv_pmos L=0.13U W=1.82U AS=0.4368P AD=0.4368P PS=4.12U PD=4.12U +Xtr_00010 16 8 12 18 sg13_lv_nmos L=0.13U W=1.22U AS=0.2928P AD=0.2928P PS=2.92U PD=2.92U +Xtr_00009 14 13 18 18 sg13_lv_nmos L=0.13U W=1.22U AS=0.2928P AD=0.2928P PS=2.92U PD=2.92U +Xtr_00008 11 9 16 18 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00007 18 6 11 18 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00006 11 7 18 18 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00005 18 5 11 18 sg13_lv_nmos L=0.13U W=0.92U AS=0.2208P AD=0.2208P PS=2.32U PD=2.32U +Xtr_00004 12 10 14 18 sg13_lv_nmos L=0.13U W=1.22U AS=0.2928P AD=0.2928P PS=2.92U PD=2.92U +Xtr_00003 15 17 18 18 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00002 18 17 15 18 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00001 18 16 17 18 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +C16 3 18 1.14954e-15 +C15 4 18 4.15369e-15 +C14 5 18 1.39837e-14 +C13 6 18 1.46876e-14 +C12 7 18 1.43356e-14 +C11 8 18 1.3708e-14 +C10 9 18 1.51158e-14 +C9 10 18 1.57434e-14 +C8 11 18 5.28022e-16 +C6 13 18 1.57434e-14 +C4 15 18 1.93714e-15 +C3 16 18 2.50312e-14 +C2 17 18 2.64316e-14 +C1 18 18 3.85405e-15 +.ends noa3ao322_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nts_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nts_x1.spi new file mode 100644 index 000000000..6c7b5f11c --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nts_x1.spi @@ -0,0 +1,27 @@ +* Spice description of nts_x1 +* Spice driver version -1531891941 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:25 + +* INTERF cmd i nq vdd vss + + +.subckt nts_x1 5 6 4 2 8 +* NET 2 = vdd +* NET 4 = nq +* NET 5 = cmd +* NET 6 = i +* NET 8 = vss +Xtr_00006 4 3 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 1 6 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00004 2 5 3 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00003 4 5 7 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 7 6 8 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 8 5 3 8 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C7 2 8 2.09702e-15 +C6 3 8 1.23468e-14 +C5 4 8 1.99345e-15 +C4 5 8 3.10765e-14 +C3 6 8 1.62948e-14 +C1 8 8 1.765e-15 +.ends nts_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nts_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nts_x2.spi new file mode 100644 index 000000000..8a1273e30 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nts_x2.spi @@ -0,0 +1,31 @@ +* Spice description of nts_x2 +* Spice driver version -335233253 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:26 + +* INTERF cmd i nq vdd vss + + +.subckt nts_x2 5 8 6 3 10 +* NET 3 = vdd +* NET 5 = cmd +* NET 6 = nq +* NET 8 = i +* NET 10 = vss +Xtr_00010 3 8 1 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 4 5 3 3 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 2 8 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 6 4 2 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 1 4 6 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 4 5 10 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 10 8 7 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 9 8 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 6 5 9 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 7 5 6 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C8 3 10 2.44035e-15 +C7 4 10 1.77683e-14 +C6 5 10 3.37537e-14 +C5 6 10 1.99345e-15 +C3 8 10 4.38962e-14 +C1 10 10 2.05203e-15 +.ends nts_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nxr2_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nxr2_x1.spi new file mode 100644 index 000000000..911eefa8d --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nxr2_x1.spi @@ -0,0 +1,35 @@ +* Spice description of nxr2_x1 +* Spice driver version 838659867 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:26 + +* INTERF i0 i1 nq vdd vss + + +.subckt nxr2_x1 8 3 7 2 9 +* NET 2 = vdd +* NET 3 = i1 +* NET 7 = nq +* NET 8 = i0 +* NET 9 = vss +Xtr_00012 4 3 2 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00011 2 4 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 1 10 7 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 7 3 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 1 8 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 8 10 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00006 4 3 9 9 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 9 3 6 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 6 10 7 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 7 4 5 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 9 8 10 9 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 5 8 9 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C10 1 9 8.63047e-16 +C9 2 9 2.08674e-15 +C8 3 9 3.12373e-14 +C7 4 9 2.7614e-14 +C4 7 9 1.91539e-15 +C3 8 9 2.69501e-14 +C2 9 9 2.08674e-15 +C1 10 9 2.86016e-14 +.ends nxr2_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nxr2_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nxr2_x4.spi new file mode 100644 index 000000000..3b830e243 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/nxr2_x4.spi @@ -0,0 +1,40 @@ +* Spice description of nxr2_x4 +* Spice driver version -378462437 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:26 + +* INTERF i0 i1 nq vdd vss + + +.subckt nxr2_x4 9 5 3 2 10 +* NET 2 = vdd +* NET 3 = nq +* NET 5 = i1 +* NET 9 = i0 +* NET 10 = vss +Xtr_00016 2 8 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00015 3 8 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00014 2 5 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 1 11 8 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 1 9 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 8 4 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 4 5 2 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00009 2 9 11 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 10 8 3 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00007 3 8 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00006 4 5 10 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 10 9 11 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 7 11 8 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 10 4 7 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 8 5 6 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 6 9 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C11 1 10 4.7288e-16 +C10 2 10 4.06914e-15 +C9 3 10 1.93831e-15 +C8 4 10 2.84373e-14 +C7 5 10 2.64414e-14 +C4 8 10 4.33976e-14 +C3 9 10 2.41345e-14 +C2 10 10 3.30443e-15 +C1 11 10 3.00018e-14 +.ends nxr2_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o2_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o2_x2.spi new file mode 100644 index 000000000..6d3e8ac8f --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o2_x2.spi @@ -0,0 +1,27 @@ +* Spice description of o2_x2 +* Spice driver version -524144869 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:26 + +* INTERF i0 i1 q vdd vss + + +.subckt o2_x2 3 5 4 1 7 +* NET 1 = vdd +* NET 3 = i0 +* NET 4 = q +* NET 5 = i1 +* NET 7 = vss +Xtr_00006 2 5 6 1 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00005 4 6 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00004 1 3 2 1 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00003 7 3 6 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 6 5 7 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 4 6 7 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C7 1 7 1.33828e-15 +C5 3 7 1.60398e-14 +C4 4 7 1.99345e-15 +C3 5 7 2.10614e-14 +C2 6 7 2.09836e-14 +C1 7 7 1.52357e-15 +.ends o2_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o2_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o2_x4.spi new file mode 100644 index 000000000..707728a6d --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o2_x4.spi @@ -0,0 +1,30 @@ +* Spice description of o2_x4 +* Spice driver version 1602862875 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:27 + +* INTERF i0 i1 q vdd vss + + +.subckt o2_x4 3 5 4 1 6 +* NET 1 = vdd +* NET 3 = i0 +* NET 4 = q +* NET 5 = i1 +* NET 6 = vss +Xtr_00009 1 7 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 4 7 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 5 7 1 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00006 1 3 2 1 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00005 6 7 4 6 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 4 7 6 6 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 6 3 7 6 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 7 5 6 6 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 6 3 7 6 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C7 1 6 2.26478e-15 +C5 3 6 1.72387e-14 +C4 4 6 1.99345e-15 +C3 5 6 1.96148e-14 +C2 6 6 2.14138e-15 +C1 7 6 3.57653e-14 +.ends o2_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o3_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o3_x2.spi new file mode 100644 index 000000000..e5d98db2f --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o3_x2.spi @@ -0,0 +1,31 @@ +* Spice description of o3_x2 +* Spice driver version 447168283 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:27 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt o3_x2 4 6 7 5 2 8 +* NET 2 = vdd +* NET 4 = i0 +* NET 5 = q +* NET 6 = i1 +* NET 7 = i2 +* NET 8 = vss +Xtr_00008 2 4 1 2 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00007 1 6 3 2 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00006 3 7 9 2 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00005 5 9 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00004 8 4 9 8 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 9 6 8 8 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 8 7 9 8 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 5 9 8 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C8 2 8 1.569e-15 +C6 4 8 1.51158e-14 +C5 5 8 2.02102e-15 +C4 6 8 1.54677e-14 +C3 7 8 1.54677e-14 +C2 8 8 1.87712e-15 +C1 9 8 2.30956e-14 +.ends o3_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o3_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o3_x4.spi new file mode 100644 index 000000000..c9e781a9f --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o3_x4.spi @@ -0,0 +1,33 @@ +* Spice description of o3_x4 +* Spice driver version -424849637 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:27 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt o3_x4 4 6 7 5 1 8 +* NET 1 = vdd +* NET 4 = i0 +* NET 5 = q +* NET 6 = i1 +* NET 7 = i2 +* NET 8 = vss +Xtr_00010 1 4 2 1 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00009 2 6 3 1 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00008 3 7 9 1 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00007 1 9 5 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 5 9 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 8 4 9 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 9 6 8 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 8 7 9 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 8 9 5 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 5 9 8 8 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C9 1 8 2.4955e-15 +C6 4 8 1.53915e-14 +C5 5 8 1.99345e-15 +C4 6 8 1.57434e-14 +C3 7 8 1.50395e-14 +C2 8 8 2.16348e-15 +C1 9 8 4.0414e-14 +.ends o3_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o4_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o4_x2.spi new file mode 100644 index 000000000..fb01334bd --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o4_x2.spi @@ -0,0 +1,35 @@ +* Spice description of o4_x2 +* Spice driver version 139452187 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:28 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt o4_x2 7 8 6 9 5 2 11 +* NET 2 = vdd +* NET 5 = q +* NET 6 = i2 +* NET 7 = i0 +* NET 8 = i1 +* NET 9 = i3 +* NET 11 = vss +Xtr_00010 2 6 3 2 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00009 3 7 1 2 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00008 1 8 4 2 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00007 4 9 10 2 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00006 5 10 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00005 11 6 10 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 10 7 11 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 11 8 10 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 10 9 11 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 5 10 11 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C10 2 11 1.79971e-15 +C7 5 11 1.99345e-15 +C6 6 11 1.51158e-14 +C5 7 11 1.58197e-14 +C4 8 11 1.98407e-14 +C3 9 11 2.01926e-14 +C2 10 11 2.10053e-14 +C1 11 11 2.28515e-15 +.ends o4_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o4_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o4_x4.spi new file mode 100644 index 000000000..90c4e2499 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/o4_x4.spi @@ -0,0 +1,37 @@ +* Spice description of o4_x4 +* Spice driver version 1147682587 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:28 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt o4_x4 7 10 8 6 5 1 11 +* NET 1 = vdd +* NET 5 = q +* NET 6 = i3 +* NET 7 = i0 +* NET 8 = i2 +* NET 10 = i1 +* NET 11 = vss +Xtr_00012 5 9 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 1 9 5 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 1 6 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 2 8 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 4 7 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 3 10 9 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 5 9 11 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 11 9 5 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 11 6 9 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 9 8 11 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 11 7 9 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 9 10 11 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C11 1 11 2.51826e-15 +C7 5 11 2.04386e-15 +C6 6 11 1.53915e-14 +C5 7 11 1.53152e-14 +C4 8 11 1.63711e-14 +C3 9 11 2.30545e-14 +C2 10 11 1.53152e-14 +C1 11 11 2.19936e-15 +.ends o4_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa22_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa22_x2.spi new file mode 100644 index 000000000..00103247a --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa22_x2.spi @@ -0,0 +1,32 @@ +* Spice description of oa22_x2 +* Spice driver version 1876659995 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:28 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt oa22_x2 6 7 3 4 2 9 +* NET 2 = vdd +* NET 3 = i2 +* NET 4 = q +* NET 6 = i0 +* NET 7 = i1 +* NET 9 = vss +Xtr_00008 4 5 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 1 7 5 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00006 2 3 1 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00005 5 6 1 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00004 4 5 9 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 9 3 5 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 5 7 8 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 8 6 9 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C9 1 9 6.68882e-16 +C8 2 9 1.569e-15 +C7 3 9 1.71681e-14 +C6 4 9 1.99345e-15 +C5 5 9 2.0875e-14 +C4 6 9 2.27823e-14 +C3 7 9 1.54884e-14 +C1 9 9 1.62531e-15 +.ends oa22_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa22_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa22_x4.spi new file mode 100644 index 000000000..cb3395ba2 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa22_x4.spi @@ -0,0 +1,34 @@ +* Spice description of oa22_x4 +* Spice driver version -2051023077 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:28 + +* INTERF i0 i1 i2 q vdd vss + + +.subckt oa22_x4 7 6 4 3 2 9 +* NET 2 = vdd +* NET 3 = q +* NET 4 = i2 +* NET 6 = i1 +* NET 7 = i0 +* NET 9 = vss +Xtr_00010 1 6 5 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00009 5 7 1 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 3 5 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 5 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 2 4 1 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00005 5 6 8 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 8 7 9 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 9 5 3 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 3 5 9 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 9 4 5 9 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C9 1 9 4.7288e-16 +C8 2 9 2.72621e-15 +C7 3 9 1.99345e-15 +C6 4 9 1.85034e-14 +C5 5 9 4.70695e-14 +C4 6 9 1.89109e-14 +C3 7 9 1.99668e-14 +C1 9 9 2.39419e-15 +.ends oa22_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a22_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a22_x2.spi new file mode 100644 index 000000000..3a3432b04 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a22_x2.spi @@ -0,0 +1,36 @@ +* Spice description of oa2a22_x2 +* Spice driver version -794095845 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:29 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt oa2a22_x2 9 8 4 5 3 2 11 +* NET 2 = vdd +* NET 3 = q +* NET 4 = i2 +* NET 5 = i3 +* NET 8 = i1 +* NET 9 = i0 +* NET 11 = vss +Xtr_00010 1 8 6 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00009 6 9 1 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 3 6 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 4 1 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00006 1 5 2 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00005 6 8 10 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 10 9 11 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 11 5 7 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 7 4 6 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 3 6 11 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C11 1 11 8.87611e-16 +C10 2 11 2.58763e-15 +C9 3 11 1.99345e-15 +C8 4 11 2.55258e-14 +C7 5 11 2.17265e-14 +C6 6 11 2.06663e-14 +C4 8 11 1.78551e-14 +C3 9 11 1.79313e-14 +C1 11 11 2.73703e-15 +.ends oa2a22_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a22_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a22_x4.spi new file mode 100644 index 000000000..a93e68b6e --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a22_x4.spi @@ -0,0 +1,38 @@ +* Spice description of oa2a22_x4 +* Spice driver version -1049809125 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:29 + +* INTERF i0 i1 i2 i3 q vdd vss + + +.subckt oa2a22_x4 9 8 4 5 3 2 11 +* NET 2 = vdd +* NET 3 = q +* NET 4 = i2 +* NET 5 = i3 +* NET 8 = i1 +* NET 9 = i0 +* NET 11 = vss +Xtr_00012 2 4 1 2 sg13_lv_pmos L=0.13U W=1.59U AS=0.3816P AD=0.3816P PS=3.67U PD=3.67U +Xtr_00011 1 5 2 2 sg13_lv_pmos L=0.13U W=1.59U AS=0.3816P AD=0.3816P PS=3.67U PD=3.67U +Xtr_00010 1 8 7 2 sg13_lv_pmos L=0.13U W=1.59U AS=0.3816P AD=0.3816P PS=3.67U PD=3.67U +Xtr_00009 7 9 1 2 sg13_lv_pmos L=0.13U W=1.59U AS=0.3816P AD=0.3816P PS=3.67U PD=3.67U +Xtr_00008 3 7 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 7 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 6 4 7 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 7 8 10 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 10 9 11 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 3 7 11 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 11 7 3 11 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 11 5 6 11 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C11 1 11 8.73826e-16 +C10 2 11 3.58371e-15 +C9 3 11 1.99345e-15 +C8 4 11 2.45421e-14 +C7 5 11 2.52459e-14 +C5 7 11 4.07614e-14 +C4 8 11 2.13745e-14 +C3 9 11 2.10226e-14 +C1 11 11 3.10676e-15 +.ends oa2a22_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a23_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a23_x2.spi new file mode 100644 index 000000000..ce5efda63 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a23_x2.spi @@ -0,0 +1,45 @@ +* Spice description of oa2a2a23_x2 +* Spice driver version 478379803 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:29 + +* INTERF i0 i1 i2 i3 i4 i5 q vdd vss + + +.subckt oa2a2a23_x2 6 5 8 9 12 13 4 2 15 +* NET 2 = vdd +* NET 4 = q +* NET 5 = i1 +* NET 6 = i0 +* NET 8 = i2 +* NET 9 = i3 +* NET 12 = i4 +* NET 13 = i5 +* NET 15 = vss +Xtr_00014 1 5 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 2 6 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 4 11 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 3 8 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 1 9 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 3 12 11 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 11 13 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 7 5 11 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00006 15 6 7 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 4 11 15 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 15 8 10 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 10 9 11 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 11 12 14 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 14 13 15 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C15 1 15 7.38296e-16 +C14 2 15 3.13433e-15 +C13 3 15 7.63542e-16 +C12 4 15 1.99345e-15 +C11 5 15 1.47638e-14 +C10 6 15 1.47638e-14 +C8 8 15 1.47638e-14 +C7 9 15 1.51158e-14 +C5 11 15 1.70376e-14 +C4 12 15 1.47638e-14 +C3 13 15 1.47638e-14 +C1 15 15 2.60448e-15 +.ends oa2a2a23_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a23_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a23_x4.spi new file mode 100644 index 000000000..f342479d5 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a23_x4.spi @@ -0,0 +1,47 @@ +* Spice description of oa2a2a23_x4 +* Spice driver version -94044389 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:30 + +* INTERF i0 i1 i2 i3 i4 i5 q vdd vss + + +.subckt oa2a2a23_x4 6 5 8 9 10 13 4 1 15 +* NET 1 = vdd +* NET 4 = q +* NET 5 = i1 +* NET 6 = i0 +* NET 8 = i2 +* NET 9 = i3 +* NET 10 = i4 +* NET 13 = i5 +* NET 15 = vss +Xtr_00016 1 12 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00015 4 12 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00014 1 6 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 2 5 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 12 13 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 3 8 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 2 9 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 3 10 12 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 15 12 4 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00007 4 12 15 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00006 7 5 12 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 15 8 11 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 14 13 15 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 15 6 7 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 11 9 12 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 12 10 14 15 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C15 1 15 4.05966e-15 +C14 2 15 7.91783e-16 +C13 3 15 7.49757e-16 +C12 4 15 1.99345e-15 +C11 5 15 2.04337e-14 +C10 6 15 2.11376e-14 +C8 8 15 2.04337e-14 +C7 9 15 2.04337e-14 +C6 10 15 1.9177e-14 +C4 12 15 3.59026e-14 +C3 13 15 2.04337e-14 +C1 15 15 3.19779e-15 +.ends oa2a2a23_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a2a24_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a2a24_x2.spi new file mode 100644 index 000000000..67fce9d60 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a2a24_x2.spi @@ -0,0 +1,54 @@ +* Spice description of oa2a2a2a24_x2 +* Spice driver version -293425381 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:30 + +* INTERF i0 i1 i2 i3 i4 i5 i6 i7 q vdd vss + + +.subckt oa2a2a2a24_x2 7 6 9 10 13 14 12 17 5 2 19 +* NET 2 = vdd +* NET 5 = q +* NET 6 = i1 +* NET 7 = i0 +* NET 9 = i2 +* NET 10 = i3 +* NET 12 = i6 +* NET 13 = i4 +* NET 14 = i5 +* NET 17 = i7 +* NET 19 = vss +Xtr_00018 1 6 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00017 2 7 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00016 16 17 4 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00015 5 16 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00014 4 12 16 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 3 9 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 1 10 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 3 13 4 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 4 14 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 8 6 16 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00008 19 7 8 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00007 18 17 19 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00006 5 16 19 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 16 12 18 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 19 9 11 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 11 10 16 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 16 13 15 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 15 14 19 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C19 1 19 8.40703e-16 +C18 2 19 3.69579e-15 +C17 3 19 1.0009e-15 +C16 4 19 1.26767e-15 +C15 5 19 1.73337e-15 +C14 6 19 1.47638e-14 +C13 7 19 1.53915e-14 +C11 9 19 1.51158e-14 +C10 10 19 1.47638e-14 +C8 12 19 2.22545e-14 +C7 13 19 1.51158e-14 +C6 14 19 1.54677e-14 +C4 16 19 2.02548e-14 +C3 17 19 1.53915e-14 +C1 19 19 3.35293e-15 +.ends oa2a2a2a24_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a2a24_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a2a24_x4.spi new file mode 100644 index 000000000..836abaa83 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2a2a2a24_x4.spi @@ -0,0 +1,56 @@ +* Spice description of oa2a2a2a24_x4 +* Spice driver version -1199456485 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:30 + +* INTERF i0 i1 i2 i3 i4 i5 i6 i7 q vdd vss + + +.subckt oa2a2a2a24_x4 6 5 9 10 12 13 16 17 7 1 19 +* NET 1 = vdd +* NET 5 = i1 +* NET 6 = i0 +* NET 7 = q +* NET 9 = i2 +* NET 10 = i3 +* NET 12 = i4 +* NET 13 = i5 +* NET 16 = i6 +* NET 17 = i7 +* NET 19 = vss +Xtr_00020 2 5 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00019 1 6 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00018 7 14 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00017 1 14 7 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00016 3 9 2 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00015 2 10 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00014 3 12 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 4 13 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 4 16 14 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 14 17 4 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 8 5 14 19 sg13_lv_nmos L=0.13U W=1.67U AS=0.4008P AD=0.4008P PS=3.82U PD=3.82U +Xtr_00009 19 6 8 19 sg13_lv_nmos L=0.13U W=1.67U AS=0.4008P AD=0.4008P PS=3.82U PD=3.82U +Xtr_00008 7 14 19 19 sg13_lv_nmos L=0.13U W=1.67U AS=0.4008P AD=0.4008P PS=3.82U PD=3.82U +Xtr_00007 19 14 7 19 sg13_lv_nmos L=0.13U W=1.67U AS=0.4008P AD=0.4008P PS=3.82U PD=3.82U +Xtr_00006 19 9 11 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 11 10 14 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 14 12 15 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 15 13 19 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 14 16 18 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 18 17 19 19 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C19 1 19 4.32693e-15 +C18 2 19 7.65866e-16 +C17 3 19 1.00274e-15 +C16 4 19 1.05788e-15 +C15 5 19 1.44119e-14 +C14 6 19 1.44119e-14 +C13 7 19 1.95175e-15 +C11 9 19 1.47638e-14 +C10 10 19 1.47638e-14 +C8 12 19 1.51158e-14 +C7 13 19 1.51158e-14 +C6 14 19 3.59233e-14 +C4 16 19 1.47638e-14 +C3 17 19 1.53915e-14 +C1 19 19 3.40924e-15 +.ends oa2a2a2a24_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2ao222_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2ao222_x2.spi new file mode 100644 index 000000000..899c551ac --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2ao222_x2.spi @@ -0,0 +1,41 @@ +* Spice description of oa2ao222_x2 +* Spice driver version 154930971 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:30 + +* INTERF i0 i1 i2 i3 i4 q vdd vss + + +.subckt oa2ao222_x2 11 10 6 4 7 5 3 13 +* NET 3 = vdd +* NET 4 = i3 +* NET 5 = q +* NET 6 = i2 +* NET 7 = i4 +* NET 10 = i1 +* NET 11 = i0 +* NET 13 = vss +Xtr_00012 2 4 1 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 1 6 8 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 2 10 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 3 11 2 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 8 7 2 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 5 8 3 3 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00006 9 4 13 13 sg13_lv_nmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +Xtr_00005 13 6 9 13 sg13_lv_nmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +Xtr_00004 12 11 13 13 sg13_lv_nmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +Xtr_00003 8 10 12 13 sg13_lv_nmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +Xtr_00002 9 7 8 13 sg13_lv_nmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +Xtr_00001 5 8 13 13 sg13_lv_nmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +C12 2 13 9.28968e-16 +C11 3 13 2.49967e-15 +C10 4 13 1.4838e-14 +C9 5 13 2.04976e-15 +C8 6 13 1.79701e-14 +C7 7 13 1.50299e-14 +C6 8 13 1.20682e-14 +C5 9 13 4.45309e-16 +C4 10 13 1.60095e-14 +C3 11 13 1.59333e-14 +C1 13 13 2.69383e-15 +.ends oa2ao222_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2ao222_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2ao222_x4.spi new file mode 100644 index 000000000..a92929718 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa2ao222_x4.spi @@ -0,0 +1,43 @@ +* Spice description of oa2ao222_x4 +* Spice driver version -542638309 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:31 + +* INTERF i0 i1 i2 i3 i4 q vdd vss + + +.subckt oa2ao222_x4 11 10 5 6 7 4 2 13 +* NET 2 = vdd +* NET 4 = q +* NET 5 = i2 +* NET 6 = i3 +* NET 7 = i4 +* NET 10 = i1 +* NET 11 = i0 +* NET 13 = vss +Xtr_00014 2 8 4 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 4 8 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 3 6 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 8 7 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 3 10 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 2 11 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 1 5 8 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 13 8 4 13 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00006 4 8 13 13 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00005 13 5 9 13 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00004 9 6 13 13 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00003 9 7 8 13 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00002 8 10 12 13 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00001 12 11 13 13 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +C12 2 13 3.60538e-15 +C11 3 13 9.15182e-16 +C10 4 13 2.04976e-15 +C9 5 13 1.61058e-14 +C8 6 13 2.74006e-14 +C7 7 13 1.44119e-14 +C6 8 13 3.68461e-14 +C5 9 13 4.45309e-16 +C4 10 13 1.44119e-14 +C3 11 13 1.50395e-14 +C1 13 13 3.71516e-15 +.ends oa2ao222_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa3ao322_x2.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa3ao322_x2.spi new file mode 100644 index 000000000..99d99cfd4 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa3ao322_x2.spi @@ -0,0 +1,50 @@ +* Spice description of oa3ao322_x2 +* Spice driver version -1912381669 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:31 + +* INTERF i0 i1 i2 i3 i4 i5 i6 q vdd vss + + +.subckt oa3ao322_x2 12 11 10 7 5 6 8 17 4 16 +* NET 4 = vdd +* NET 5 = i4 +* NET 6 = i5 +* NET 7 = i3 +* NET 8 = i6 +* NET 10 = i2 +* NET 11 = i1 +* NET 12 = i0 +* NET 15 = 4 +* NET 16 = vss +* NET 17 = q +Xtr_00016 2 7 15 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00015 1 5 2 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00014 3 6 1 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00013 15 8 3 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00012 3 12 4 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00011 4 11 3 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00010 3 10 4 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00009 4 15 17 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 16 7 9 16 sg13_lv_nmos L=0.13U W=1.29U AS=0.3096P AD=0.3096P PS=3.07U PD=3.07U +Xtr_00007 9 5 16 16 sg13_lv_nmos L=0.13U W=1.29U AS=0.3096P AD=0.3096P PS=3.07U PD=3.07U +Xtr_00006 16 6 9 16 sg13_lv_nmos L=0.13U W=1.29U AS=0.3096P AD=0.3096P PS=3.07U PD=3.07U +Xtr_00005 9 8 15 16 sg13_lv_nmos L=0.13U W=1.59U AS=0.3816P AD=0.3816P PS=3.67U PD=3.67U +Xtr_00004 15 10 13 16 sg13_lv_nmos L=0.13U W=1.22U AS=0.2928P AD=0.2928P PS=2.92U PD=2.92U +Xtr_00003 13 11 14 16 sg13_lv_nmos L=0.13U W=1.22U AS=0.2928P AD=0.2928P PS=2.92U PD=2.92U +Xtr_00002 16 15 17 16 sg13_lv_nmos L=0.13U W=1.89U AS=0.4536P AD=0.4536P PS=4.27U PD=4.27U +Xtr_00001 14 12 16 16 sg13_lv_nmos L=0.13U W=1.22U AS=0.2928P AD=0.2928P PS=2.92U PD=2.92U +C15 3 16 1.16332e-15 +C14 4 16 2.96417e-15 +C13 5 16 1.53915e-14 +C12 6 16 1.53915e-14 +C11 7 16 1.53915e-14 +C10 8 16 1.68755e-14 +C9 9 16 6.11902e-16 +C8 10 16 1.40599e-14 +C7 11 16 1.46876e-14 +C6 12 16 1.53915e-14 +C3 15 16 1.92872e-14 +C2 16 16 2.891e-15 +C1 17 16 1.99345e-15 +.ends oa3ao322_x2 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa3ao322_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa3ao322_x4.spi new file mode 100644 index 000000000..24f89243e --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/oa3ao322_x4.spi @@ -0,0 +1,51 @@ +* Spice description of oa3ao322_x4 +* Spice driver version -79270117 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:31 + +* INTERF i0 i1 i2 i3 i4 i5 i6 q vdd vss + + +.subckt oa3ao322_x4 12 11 9 8 5 6 7 16 4 17 +* NET 4 = vdd +* NET 5 = i4 +* NET 6 = i5 +* NET 7 = i6 +* NET 8 = i3 +* NET 9 = i2 +* NET 11 = i1 +* NET 12 = i0 +* NET 16 = q +* NET 17 = vss +Xtr_00018 1 8 15 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00017 2 5 1 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00016 3 6 2 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00015 15 7 3 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00014 3 9 4 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00013 4 11 3 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00012 3 12 4 4 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00011 4 15 16 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 16 15 4 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 17 8 10 17 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00008 10 7 15 17 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00007 17 6 10 17 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00006 10 5 17 17 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 15 9 13 17 sg13_lv_nmos L=0.13U W=1.22U AS=0.2928P AD=0.2928P PS=2.92U PD=2.92U +Xtr_00004 13 11 14 17 sg13_lv_nmos L=0.13U W=1.22U AS=0.2928P AD=0.2928P PS=2.92U PD=2.92U +Xtr_00003 14 12 17 17 sg13_lv_nmos L=0.13U W=1.22U AS=0.2928P AD=0.2928P PS=2.92U PD=2.92U +Xtr_00002 16 15 17 17 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00001 17 15 16 17 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +C15 3 17 1.20468e-15 +C14 4 17 4.17826e-15 +C13 5 17 1.67993e-14 +C12 6 17 1.71512e-14 +C11 7 17 1.47776e-14 +C10 8 17 1.8207e-14 +C9 9 17 1.8649e-14 +C8 10 17 5.28022e-16 +C7 11 17 2.45808e-14 +C6 12 17 2.49328e-14 +C3 15 17 4.18428e-14 +C2 16 17 1.99345e-15 +C1 17 17 3.62334e-15 +.ends oa3ao322_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/on12_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/on12_x1.spi new file mode 100644 index 000000000..d6d38d793 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/on12_x1.spi @@ -0,0 +1,27 @@ +* Spice description of on12_x1 +* Spice driver version -1095123173 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:32 + +* INTERF i0 i1 q vdd vss + + +.subckt on12_x1 2 5 4 1 6 +* NET 1 = vdd +* NET 2 = i0 +* NET 4 = q +* NET 5 = i1 +* NET 6 = vss +Xtr_00006 4 7 1 1 sg13_lv_pmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +Xtr_00005 1 5 7 1 sg13_lv_pmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +Xtr_00004 1 2 4 1 sg13_lv_pmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +Xtr_00003 3 7 6 6 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00002 6 5 7 6 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00001 4 2 3 6 sg13_lv_nmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +C7 1 6 1.39459e-15 +C6 2 6 2.09852e-14 +C4 4 6 2.09437e-15 +C3 5 6 1.52052e-14 +C2 6 6 1.51933e-15 +C1 7 6 2.0721e-14 +.ends on12_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/on12_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/on12_x4.spi new file mode 100644 index 000000000..bcb49bf2b --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/on12_x4.spi @@ -0,0 +1,32 @@ +* Spice description of on12_x4 +* Spice driver version -1939906789 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:32 + +* INTERF i0 i1 q vdd vss + + +.subckt on12_x4 6 4 3 1 7 +* NET 1 = vdd +* NET 3 = q +* NET 4 = i1 +* NET 6 = i0 +* NET 7 = vss +Xtr_00010 1 4 2 1 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00009 3 5 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 1 5 3 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 8 5 1 sg13_lv_pmos L=0.13U W=2.27U AS=0.5448P AD=0.5448P PS=5.02U PD=5.02U +Xtr_00006 1 6 8 1 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 7 6 8 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 7 5 3 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 3 5 7 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 7 4 5 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 5 8 7 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C8 1 7 2.72738e-15 +C6 3 7 1.99345e-15 +C5 4 7 1.67485e-14 +C4 5 7 5.12005e-14 +C3 6 7 2.18904e-14 +C2 7 7 2.39536e-15 +C1 8 7 2.36181e-14 +.ends on12_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/one_x0.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/one_x0.spi new file mode 100644 index 000000000..621adf228 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/one_x0.spi @@ -0,0 +1,17 @@ +* Spice description of one_x0 +* Spice driver version 1861938971 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:32 + +* INTERF q vdd vss + + +.subckt one_x0 2 1 3 +* NET 1 = vdd +* NET 2 = q +* NET 3 = vss +Xtr_00001 2 3 1 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +C3 1 3 1.33045e-15 +C2 2 3 1.88083e-15 +C1 3 3 1.14082e-14 +.ends one_x0 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/powmid_x0.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/powmid_x0.spi new file mode 100644 index 000000000..ca3a318eb --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/powmid_x0.spi @@ -0,0 +1,14 @@ +* Spice description of powmid_x0 +* Spice driver version 512347931 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:52 + +* INTERF vdd vss + + +.subckt powmid_x0 1 2 +* NET 1 = vdd +* NET 2 = vss +C2 1 2 1.85602e-15 +C1 2 2 1.85602e-15 +.ends powmid_x0 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/rowend_x0.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/rowend_x0.spi new file mode 100644 index 000000000..0ddde8d76 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/rowend_x0.spi @@ -0,0 +1,14 @@ +* Spice description of rowend_x0 +* Spice driver version -785486053 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:52 + +* INTERF vdd vss + + +.subckt rowend_x0 1 2 +* NET 1 = vdd +* NET 2 = vss +C2 1 2 4.15422e-16 +C1 2 2 4.15422e-16 +.ends rowend_x0 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/sff1_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/sff1_x4.spi new file mode 100644 index 000000000..7476c5274 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/sff1_x4.spi @@ -0,0 +1,56 @@ +* Spice description of sff1_x4 +* Spice driver version 698367771 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:33 + +* INTERF ck i q vdd vss + + +.subckt sff1_x4 15 12 6 4 16 +* NET 4 = vdd +* NET 6 = q +* NET 8 = sff_s +* NET 11 = sff_m +* NET 12 = i +* NET 14 = ckr +* NET 15 = ck +* NET 16 = vss +* NET 17 = nckr +Xtr_00026 4 8 6 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00025 6 8 4 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00024 4 6 1 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00023 1 14 8 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00022 2 13 4 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00021 4 12 13 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00020 14 17 4 4 sg13_lv_pmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +Xtr_00019 4 15 17 4 sg13_lv_pmos L=0.13U W=2.12U AS=0.5088P AD=0.5088P PS=4.72U PD=4.72U +Xtr_00018 8 17 7 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00017 7 11 4 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00016 4 7 3 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00015 3 17 11 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00014 11 14 2 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00013 16 8 6 16 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00012 6 8 16 16 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00011 16 6 5 16 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00010 5 17 8 16 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00009 8 14 7 16 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00008 10 13 16 16 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00007 16 12 13 16 sg13_lv_nmos L=0.13U W=1.37U AS=0.3288P AD=0.3288P PS=3.22U PD=3.22U +Xtr_00006 14 17 16 16 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00005 16 15 17 16 sg13_lv_nmos L=0.13U W=1.07U AS=0.2568P AD=0.2568P PS=2.62U PD=2.62U +Xtr_00004 11 17 10 16 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 9 14 11 16 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 16 7 9 16 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 7 11 16 16 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C14 4 16 5.29879e-15 +C12 6 16 2.48321e-14 +C11 7 16 2.08974e-14 +C10 8 16 3.38702e-14 +C7 11 16 1.89138e-14 +C6 12 16 1.7213e-14 +C5 13 16 2.91713e-14 +C4 14 16 7.53833e-14 +C3 15 16 1.53328e-14 +C2 16 16 4.9751e-15 +C1 17 16 9.52956e-14 +.ends sff1_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/sff1r_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/sff1r_x4.spi new file mode 100644 index 000000000..280feefbe --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/sff1r_x4.spi @@ -0,0 +1,61 @@ +* Spice description of sff1r_x4 +* Spice driver version -1876422885 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:33 + +* INTERF ck i nrst q vdd vss + + +.subckt sff1r_x4 17 14 7 5 4 18 +* NET 4 = vdd +* NET 5 = q +* NET 7 = nrst +* NET 9 = sff_s +* NET 10 = y +* NET 11 = sff_m +* NET 14 = i +* NET 15 = ckr +* NET 17 = ck +* NET 18 = vss +* NET 19 = nckr +Xtr_00028 5 9 4 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00027 9 15 1 4 sg13_lv_pmos L=0.13U W=2.04U AS=0.4896P AD=0.4896P PS=4.57U PD=4.57U +Xtr_00026 4 9 5 4 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00025 1 5 4 4 sg13_lv_pmos L=0.13U W=2.04U AS=0.4896P AD=0.4896P PS=4.57U PD=4.57U +Xtr_00024 10 19 9 4 sg13_lv_pmos L=0.13U W=2.04U AS=0.4896P AD=0.4896P PS=4.57U PD=4.57U +Xtr_00023 4 7 10 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00022 11 19 3 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00021 3 10 4 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00020 10 11 4 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00019 2 15 11 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00018 4 16 2 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00017 16 14 4 4 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00016 4 19 15 4 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00015 19 17 4 4 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00014 13 15 11 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00013 11 19 12 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00012 18 9 5 18 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00011 5 9 18 18 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00010 18 5 6 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00009 6 19 9 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00008 9 15 10 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00007 10 7 8 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00006 8 11 18 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 18 10 13 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 12 16 18 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 18 17 19 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 15 19 18 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 18 14 16 18 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C16 4 18 5.21376e-15 +C15 5 18 2.123e-14 +C13 7 18 2.20053e-14 +C11 9 18 3.47422e-14 +C10 10 18 2.30769e-14 +C9 11 18 3.6015e-14 +C6 14 18 1.59913e-14 +C5 15 18 7.76489e-14 +C4 16 18 2.74223e-14 +C3 17 18 1.9047e-14 +C2 18 18 4.83623e-15 +C1 19 18 1.01179e-13 +.ends sff1r_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/sff2_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/sff2_x4.spi new file mode 100644 index 000000000..290b9b6fb --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/sff2_x4.spi @@ -0,0 +1,69 @@ +* Spice description of sff2_x4 +* Spice driver version 1979735835 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:33 + +* INTERF ck cmd i0 i1 q vdd vss + + +.subckt sff2_x4 15 21 22 16 7 6 24 +* NET 6 = vdd +* NET 7 = q +* NET 8 = sff_s +* NET 12 = sff_m +* NET 14 = ckr +* NET 15 = ck +* NET 16 = i1 +* NET 17 = nckr +* NET 21 = cmd +* NET 22 = i0 +* NET 24 = vss +Xtr_00034 3 17 12 6 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00033 12 14 2 6 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00032 7 8 6 6 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00031 1 14 8 6 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00030 8 17 10 6 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00029 6 10 3 6 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00028 6 8 7 6 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00027 10 12 6 6 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00026 19 21 5 6 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00025 4 23 19 6 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00024 6 16 4 6 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00023 6 15 17 6 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00022 6 7 1 6 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00021 5 22 6 6 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00020 6 21 23 6 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00019 14 17 6 6 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00018 2 19 6 6 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00017 12 17 11 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00016 8 14 10 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00015 7 8 24 24 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00014 13 14 12 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00013 10 12 24 24 sg13_lv_nmos L=0.13U W=0.69U AS=0.1656P AD=0.1656P PS=1.87U PD=1.87U +Xtr_00012 24 10 13 24 sg13_lv_nmos L=0.13U W=0.69U AS=0.1656P AD=0.1656P PS=1.87U PD=1.87U +Xtr_00011 24 8 7 24 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00010 24 7 9 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00009 19 23 20 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00008 20 22 24 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00007 24 21 23 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00006 24 15 17 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 14 17 24 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 11 19 24 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00003 9 17 8 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 18 21 19 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 24 16 18 24 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C19 6 24 7.22839e-15 +C18 7 24 2.26378e-14 +C17 8 24 3.39914e-14 +C15 10 24 1.74015e-14 +C13 12 24 2.35107e-14 +C11 14 24 6.87917e-14 +C10 15 24 1.85796e-14 +C9 16 24 1.33142e-14 +C8 17 24 9.65074e-14 +C6 19 24 1.38621e-14 +C4 21 24 4.67908e-14 +C3 22 24 1.68199e-14 +C2 23 24 2.03955e-14 +C1 24 24 6.56202e-15 +.ends sff2_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/tie_x0.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/tie_x0.spi new file mode 100644 index 000000000..1740971a7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/tie_x0.spi @@ -0,0 +1,14 @@ +* Spice description of tie_x0 +* Spice driver version -146899173 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:52 + +* INTERF vdd vss + + +.subckt tie_x0 1 2 +* NET 1 = vdd +* NET 2 = vss +C2 1 2 1.28561e-15 +C1 2 2 1.09145e-15 +.ends tie_x0 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ts_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ts_x4.spi new file mode 100644 index 000000000..7920a74f2 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ts_x4.spi @@ -0,0 +1,36 @@ +* Spice description of ts_x4 +* Spice driver version -934093029 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:33 + +* INTERF cmd i q vdd vss + + +.subckt ts_x4 4 3 8 1 7 +* NET 1 = vdd +* NET 3 = i +* NET 4 = cmd +* NET 5 = 4 +* NET 7 = vss +* NET 8 = q +Xtr_00012 8 2 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 1 2 8 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 5 4 1 1 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00009 1 4 2 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 2 5 6 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00007 2 3 1 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00006 6 3 7 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 8 6 7 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 7 6 8 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 5 4 7 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00002 7 5 6 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 2 4 6 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C8 1 7 3.18881e-15 +C7 2 7 4.01796e-14 +C6 3 7 1.54884e-14 +C5 4 7 5.58087e-14 +C4 5 7 2.39072e-14 +C3 6 7 3.08055e-14 +C2 7 7 2.80048e-15 +C1 8 7 1.99345e-15 +.ends ts_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ts_x8.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ts_x8.spi new file mode 100644 index 000000000..52d0705d0 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/ts_x8.spi @@ -0,0 +1,39 @@ +* Spice description of ts_x8 +* Spice driver version -1800691941 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:34 + +* INTERF cmd i q vdd vss + + +.subckt ts_x8 5 2 8 1 7 +* NET 1 = vdd +* NET 2 = i +* NET 5 = cmd +* NET 7 = vss +* NET 8 = q +Xtr_00016 8 3 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00015 1 3 8 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00014 8 3 1 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 4 5 1 1 sg13_lv_pmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00012 1 3 8 1 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 3 4 6 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00010 3 2 1 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00009 1 5 3 1 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00008 3 5 6 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00007 6 2 7 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00006 7 4 6 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00005 4 5 7 7 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00004 8 6 7 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 7 6 8 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 8 6 7 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 7 6 8 7 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C8 1 7 4.4563e-15 +C7 2 7 1.6293e-14 +C6 3 7 5.47511e-14 +C5 4 7 2.46492e-14 +C4 5 7 5.76416e-14 +C3 6 7 4.78196e-14 +C2 7 7 3.75281e-15 +C1 8 7 3.38035e-15 +.ends ts_x8 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/xr2_x1.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/xr2_x1.spi new file mode 100644 index 000000000..59cc0f368 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/xr2_x1.spi @@ -0,0 +1,35 @@ +* Spice description of xr2_x1 +* Spice driver version 1355063067 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:34 + +* INTERF i0 i1 q vdd vss + + +.subckt xr2_x1 8 4 7 2 10 +* NET 2 = vdd +* NET 4 = i1 +* NET 7 = q +* NET 8 = i0 +* NET 10 = vss +Xtr_00012 3 4 2 2 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00011 2 4 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00010 1 9 7 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00009 7 3 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 1 8 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00007 2 8 9 2 sg13_lv_pmos L=0.13U W=2.19U AS=0.5256P AD=0.5256P PS=4.87U PD=4.87U +Xtr_00006 5 9 7 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 10 3 5 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 3 4 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 6 8 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 7 4 6 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00001 10 8 9 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C10 1 10 1.03148e-15 +C9 2 10 2.08674e-15 +C8 3 10 2.63298e-14 +C7 4 10 3.49155e-14 +C4 7 10 1.90461e-15 +C3 8 10 2.7654e-14 +C2 9 10 2.85741e-14 +C1 10 10 2.08674e-15 +.ends xr2_x1 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/xr2_x4.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/xr2_x4.spi new file mode 100644 index 000000000..d991df033 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/xr2_x4.spi @@ -0,0 +1,40 @@ +* Spice description of xr2_x4 +* Spice driver version -1670058213 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:34 + +* INTERF i0 i1 q vdd vss + + +.subckt xr2_x4 9 4 3 2 10 +* NET 2 = vdd +* NET 3 = q +* NET 4 = i1 +* NET 9 = i0 +* NET 10 = vss +Xtr_00016 2 8 3 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00015 3 8 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00014 8 4 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00013 1 11 8 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00012 2 5 1 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00011 5 4 2 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00010 2 9 11 2 sg13_lv_pmos L=0.13U W=1.52U AS=0.3648P AD=0.3648P PS=3.52U PD=3.52U +Xtr_00009 1 9 2 2 sg13_lv_pmos L=0.13U W=2.94U AS=0.7056P AD=0.7056P PS=6.37U PD=6.37U +Xtr_00008 5 4 10 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00007 10 8 3 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00006 3 8 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00005 6 11 8 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00004 8 5 7 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00003 10 4 6 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +Xtr_00002 10 9 11 10 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +Xtr_00001 7 9 10 10 sg13_lv_nmos L=0.13U W=1.44U AS=0.3456P AD=0.3456P PS=3.37U PD=3.37U +C11 1 10 1.14176e-15 +C10 2 10 4.67871e-15 +C9 3 10 1.99345e-15 +C8 4 10 2.82379e-14 +C7 5 10 3.09307e-14 +C4 8 10 3.4793e-14 +C3 9 10 2.41345e-14 +C2 10 10 3.14264e-15 +C1 11 10 2.81118e-14 +.ends xr2_x4 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/zero_x0.spi b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/zero_x0.spi new file mode 100644 index 000000000..7c39cb53a --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spi/zero_x0.spi @@ -0,0 +1,17 @@ +* Spice description of zero_x0 +* Spice driver version 2011418395 +* Date ( dd/mm/yyyy hh:mm:ss ): 21/12/2024 at 16:03:35 + +* INTERF nq vdd vss + + +.subckt zero_x0 3 1 2 +* NET 1 = vdd +* NET 2 = vss +* NET 3 = nq +Xtr_00001 3 1 2 2 sg13_lv_nmos L=0.13U W=0.77U AS=0.1848P AD=0.1848P PS=2.02U PD=2.02U +C3 1 2 1.34211e-14 +C2 2 2 1.17529e-15 +C1 3 2 1.82452e-15 +.ends zero_x0 + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spimodel.cfg b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spimodel.cfg new file mode 100644 index 000000000..b2c49ed44 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/spimodel.cfg @@ -0,0 +1,5 @@ +# MBK_SPI_MODEL +# configure the transistor models of spi parser/driver +# +sg13_lv_nmos N SUBCKT +sg13_lv_pmos P SUBCKT diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/symbolic.dreal b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/symbolic.dreal new file mode 100644 index 000000000..3c39bd85c --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/symbolic.dreal @@ -0,0 +1,127 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Dreal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 02/08/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +dEFINE DREAL_LOWER_FIGURE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_INSTANCE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_CONNECTOR_STEP 0.5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_SEGMENT_STEP 0.7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_REFERENCE_STEP 1.0 + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TAbLE DREAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/symbolic.graal b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/symbolic.graal new file mode 100644 index 000000000..cae4dcf0b --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/symbolic.graal @@ -0,0 +1,386 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Graal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 27/06/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Graal Peek Bound in lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_PEEK_BOUND 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_FIGURE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_INSTANCE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_CONNECTOR_STEP 5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_SEGMENT_STEP 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_REFERENCE_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | Segment Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_NAME + + NWELL Nwell tan Black + PWELL Pwell light_yellow Black + NDIF Ndif lawn_green Black + PDIF Pdif yellow Black + NTIE Ntie spring_green Black + PTIE Ptie light_goldenrod Black + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 GReen Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + TPOLY Tpoly hot_pink Black + TALU1 Talu1 royal_blue Black + TALU2 Talu2 turquoise Black + TALU3 Talu3 light_pink Black + TALU4 Talu4 green Black + TALU5 Talu5 yellow Black + TALU6 Talu6 violet Black + TALU7 Talu7 red Black + TALU8 Talu8 blue Black + CALU1 CAlu1 royal_blue Black + CALU2 CAlu2 Cyan Black + CALU3 CAlu3 light_pink Black + CALU4 CAlu4 green Black + CALU5 CAlu5 yellow Black + CALU6 CAlu6 violet Black + CALU7 CAlu7 red Black + CALU8 CAlu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Transistor Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_TRANSISTOR_NAME + + NTRANS Ntrans lawn_green Black + PTRANS Ptrans yellow Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Connector Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_CONNECTOR_NAME + + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 green Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Length and Width for a symbolic Segment | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_VALUE + + NWELL 4 4 + PWELL 4 4 + NDIF 3 2 # LSX 2 -> 3 + PDIF 3 2 # LSX 2 -> 3 + NTIE 3 1 # LSX 2 -> 3 + PTIE 3 1 # LSX 2 -> 3 + NTRANS 1 5 # LSX 4 -> 5 + PTRANS 1 5 # LSX 4 -> 5 + POLY 1 1 + POLY2 1 1 + ALU1 2 1 # LSX 1 -> 2 + ALU2 2 1 + ALU3 2 1 + ALU4 2 1 + ALU5 2 1 + ALU6 2 1 + ALU7 2 1 + ALU8 2 1 + TPOLY 1 1 + TALU1 2 1 # LSX 1 -> 2 + TALU2 2 1 # LSX 2 -> 1 + TALU3 2 1 # LSX 2 -> 1 + TALU4 2 1 # LSX 2 -> 1 + TALU5 2 1 # LSX 2 -> 1 + TALU6 2 1 # LSX 2 -> 1 + TALU7 2 1 # LSX 2 -> 1 + TALU8 2 1 # LSX 2 -> 1 + CALU1 2 0 + CALU2 2 0 + CALU3 2 0 + CALU4 2 0 + CALU5 2 0 + CALU6 2 0 + CALU7 2 0 + CALU8 2 0 + +END + +# /*------------------------------------------------------------\ +# | | +# | Reference Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_REFERENCE_NAME + + REF_REF Ref_Ref red Black + REF_CON Ref_Con Cyan Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_VIA_NAME + + CONT_DIF_N Cont_NDif lawn_green Black + CONT_DIF_P Cont_PDif yellow Black + CONT_BODY_N Cont_NTie spring_green Black + CONT_BODY_P Cont_PTie light_goldenrod Black + CONT_POLY Cont_Poly red Black + CONT_POLY2 Cont_Poly2 orange Black + CONT_VIA Via_1-2 cyan Black + CONT_VIA2 Via_2-3 light_pink Black + CONT_VIA3 Via_3-4 green Black + CONT_VIA4 Via_4-5 yellow Black + CONT_VIA5 Via_5-6 violet Black + CONT_VIA6 Via_6-7 red Black + CONT_VIA7 Via_7-8 blue Black + C_X_N Cont_CxN orange Black + C_X_P Cont_CxP orange Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Big Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_NAME + + CONT_VIA Big_Via_1-2 cyan Black + CONT_VIA2 Big_Via_2-3 light_pink Black + CONT_VIA3 Big_Via_3-4 green Black + CONT_VIA4 Big_Via_4-5 yellow Black + CONT_VIA5 Big_Via_5-6 violet Black + CONT_VIA6 Big_Via_6-7 red Black + CONT_VIA7 Big_Via_7-8 blue Black + + CONT_TURN1 Turn_Via_1 royal_blue Black + CONT_TURN2 Turn_Via_2 Cyan Black + CONT_TURN3 Turn_Via_3 light_pink Black + CONT_TURN4 Turn_Via_4 green Black + CONT_TURN5 Turn_Via_5 yellow Black + CONT_TURN6 Turn_Via_6 violet Black + CONT_TURN7 Turn_Via_7 red Black + CONT_TURN8 Turn_Via_7 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Size for a symbolic Big Via | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_VALUE + + CONT_VIA 2 + CONT_VIA2 2 + CONT_VIA3 2 + CONT_VIA4 2 + CONT_VIA5 2 + CONT_VIA6 2 + CONT_VIA7 2 + + CONT_TURN1 2 + CONT_TURN2 2 + CONT_TURN3 2 + CONT_TURN4 2 + CONT_TURN5 2 + CONT_TURN6 2 + CONT_TURN7 2 + CONT_TURN8 2 + +END + +# /*------------------------------------------------------------\ +# | | +# | Orient Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_ORIENT_NAME + + NORTH North lawn_green Black + SOUTH South yellow Black + EAST East tan Black + WEST West red Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Symmetry Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SYMMETRY_NAME + + NOSYM No_Sym LightBlue Black + SYM_X Sym_X turquoise Black + SYM_Y Sym_Y cyan Black + SYMXY Sym_XY lightCyan Black + ROT_P Rot_P MediumAquamarine Black + ROT_M Rot_M aquamarine Black + SY_RP Sym_RP green Black + SY_RM Sym_RM MediumSpringGreen Black + +END + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/techno.py b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/techno.py new file mode 100644 index 000000000..664b538ec --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/techno.py @@ -0,0 +1,647 @@ + +from coriolis import CRL, Hurricane, Viewer, Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, BasicLayer, \ + RegularLayer, Cell, Net, Horizontal, Vertical, Rectilinear, \ + Box, Point, NetExternalComponents +from coriolis.technos.common.colors import toRGB +from coriolis.technos.common.patterns import toHexa +from coriolis.helpers import u +from coriolis.helpers.technology import createBL, createVia +from coriolis.helpers.overlay import CfgCache +from coriolis.helpers.analogtechno import Length, Area, Unit, Asymmetric, loadAnalogTechno, addDevice +from coriolis.designflow.task import ShellEnv + + +__all__ = [ "setup" ] + + +""" +Coriolis Design Technological Rules (DTR) for IHP 130nm BiCMOS General Purpose +================================================================================= + +:Version: rev.LIP6-1 +:Date: May 22, 2024 +:Authors: Naohiko Shimizu + +Reference documents: + SG13G2 Process Specification Rev.1.2 + SG13G2 Open Source Layout Rules Rev.0.2 (2024-03-08) + +===================== ======= ============ ==================================== + +""" + + +analogTechnologyTable = \ + ( ('Header', 'Sg13g2', DbU.UnitPowerMicro, 'rev.LIP6-1') + # ------------------------------------------------------------------------------------ + # ( Rule name , [Layer1] , [Layer2] , Value , Rule flags , Reference ) + , ('physicalGrid' , 0.001 , Length , 'Grid Rules') + , ('transistorMinL' , 0.13 , Length , 'Gat.a') + #, ('transistorMinL' , 0.38 , Length , 'lvtn.1a') + #, ('transistorMaxL' , 38 , Length , 'rule0002') + #, ('transistorMinW' , 0.42 , Length , 'activ.2') + #, ('transistorMinW' , 0.36 , Length , 'activ.2b') + #, ('transistorMaxW' , 4000 , Length , 'rule0004') + + # N-WELL (nwm) + , ('minWidth' , 'nwm' , 0.62 , Length , 'NW.a') + , ('minSpacing' , 'nwm' , 0.62 , Length , 'NW.b') + , ('minArea' , 'nwm' , 0 , Area , 'N/A') + + # LVTN (lvtn) + #, ('minWidth' , 'lvtn' , 0.38 , Length , 'lvtn.1a') + #, ('minSpacing' , 'lvtn' , 0.38 , Length , 'lvtn.2') + #, ('minArea' , 'lvtn' , 0.265 , Area , 'lvtn.13') + #, ('minEnclosure' , 'nwm' , 'lvtn' , 0.38 , Length|Asymmetric, 'lvtn.10') + + # ACTIV (activ) + , ('minWidth' , 'activ' , 0.15 , Length , 'Act.a') + , ('minSpacing' , 'activ' , 0.21 , Length , 'Act.b') + , ('minArea' , 'activ' , 0.122 , Area , 'Act.d') + , ('minEnclosure' , 'nwm' , 'activ' , 0.31 , Length|Asymmetric, 'NW.c') + + # Poly1 (poly) + , ('minWidth' , 'poly' , 0.13 , Length , 'Gat.a') + , ('minSpacing' , 'poly' , 0.18 , Length , 'Gat.b') + , ('minGateSpacing' , 'poly' , 0.18 , Length , 'Gat.b') + , ('minArea' , 'poly' , 0.09 , Area , 'Gat.e') + , ('minSpacing' , 'poly' , 'activ' , 0.07 , Length , 'Gat.d') + , ('minExtension' , 'poly' , 'activ' , 0.180 , Length|Asymmetric, 'Gat.c') + , ('minGateExtension' , 'activ' , 'poly' , 0.23 , Length|Asymmetric, 'Act.c') + , ('minExtension' , 'activ' , 'poly' , 0.23 , Length|Asymmetric, 'Act.c') + + # 4.1.6 PPLUS (psdm) + , ('minWidth' , 'psdm' , 0.31 , Length , 'pSD.a') + , ('minSpacing' , 'psdm' , 0.31 , Length , 'pSD.b') + , ('minArea' , 'psdm' , 0.25 , Area , 'pSD.k') + , ('minSpacing' , 'psdm' , 'activ' , 0.180 , Length , 'pSD.d') + , ('minGateExtension' , 'psdm' , 'poly' , 0.00 , Length|Asymmetric, 'N/A') + , ('minOverlap' , 'psdm' , 'activ' , 0.30 , Length , 'pSD.e') + , ('minEnclosure' , 'psdm' , 'activ' , 0.180 , Length|Asymmetric, 'pSD.c') + , ('minStrapEnclosure' , 'psdm' , 'activ' , 0.180 , Length , 'pSD.c') + , ('minSpacing' , 'nsdm' , 'psdm' , 0.00 , Length , 'N/A') + , ('minEnclosure' , 'psdm' , 'poly' , 0.30 , Length|Asymmetric, 'pSD.i') + , ('minLengthEnclosure', 'psdm' , 'activ' , 0 , Length|Asymmetric, 'N/A') + , ('minWidthEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'psdm' , 'activ' , 0.180 , Length|Asymmetric, 'dup. pSD.c') + , ('minStrapEnclosure' , 'psdm' , 0.180 , Length , 'dup. pSD.c') + + # NPLUS (nsdm) no nSD rules + #, ('minWidth' , 'nsdm' , 0.38 , Length , 'nsd.1') + #, ('minSpacing' , 'nsdm' , 0.38 , Length , 'nsd.2') + #, ('minArea' , 'nsdm' , 0.265 , Area , 'nsd.10a') + #, ('minSpacing' , 'nsdm' , 'activ' , 0.130 , Length , 'nsd.7') + #, ('minGateExtension' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minOverlap' , 'nsdm' , 'activ' , 0 , Length , 'N/A') + #, ('minEnclosure' , 'nsdm' , 'activ' , 0.125 , Length|Asymmetric, 'nsd.5a') + #, ('minStrapEnclosure' , 'nsdm' , 'activ' , 0.125 , Length , 'nsd.5b') + #, ('minEnclosure' , 'nsdm' , 'nwm' , 0 , Length|Asymmetric, 'N/A') + #, ('minEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minLengthEnclosure', 'nsdm' , 'activ' , 0 , Length|Asymmetric, 'N/A') + #, ('minWidthEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + #, ('minGateEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + #, ('minExtension' , 'nsdm' , 'activ' , 0.125 , Length|Asymmetric, 'dup. nsd.5a') + #, ('minStrapEnclosure' , 'nsdm' , 0.215 , Length , 'dup. nsd.5b') + + # LICM1 (CONT) + , ('minWidth' , 'cont' , 0.16 , Length , 'Cnt.a') + , ('minSpacing' , 'cont' , 0.18 , Length , 'Cnt.b') + , ('minGateSpacing' , 'cont' , 'poly' , 0.11 , Length|Asymmetric, 'Cnt.f') + , ('minSpacing' , 'cont' , 'poly' , 0.11 , Length|Asymmetric, 'Cnt.f') + , ('minSpacing' , 'cont' , 'activ' , 0.14 , Length , 'Cnt.e') + #, ('minSpacing' , 'cont' , 'activ' , 0.06 , Length , 'cont.5b') + , ('minEnclosure' , 'activ' , 'cont' , 0.07 , Length|Asymmetric, 'Cnt.c') + , ('minEnclosure' , 'poly' , 'cont' , 0.07 , Length|Asymmetric, 'Cnt.d') + #, ('minEnclosure' , 'psdm' , 'cont' , 0 , Length|Asymmetric, 'N/A') + #, ('minEnclosure' , 'nsdm' , 'cont' , 0 , Length|Asymmetric, 'N/A') + #, ('minGateEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'poly' , 'cont' , 0.07 , Length|Asymmetric, 'dup. Cnt.d') + , ('minExtension' , 'psdm' , 'cont' , 0.09 , Length|Asymmetric, 'Cnt.g2') + #, ('minExtension' , 'nsdm' , 'cont' , 0.25 , Length|Asymmetric, 'dup.') + + # LI1M (M1) + , ('minWidth' , 'M1' , 0.16 , Length , 'M1.a') + , ('minSpacing' , 'M1' , 0.18 , Length , 'M1.b') + , ('minArea' , 'M1' , 0.09 , Area , 'M1.d') + , ('minEnclosure' , 'M1' , 'cont' , 0.05 , Length|Asymmetric, 'M1.c1') + , ('minEnclosure' , 'M1' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # CTM1 (via12) + , ('minWidth' , 'via12' , 0.19 , Length , 'V1.a') + , ('minSpacing' , 'via12' , 0.22 , Length , 'V1.b') + + + # MM1 (M2) + , ('minWidth' , 'M2' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M2' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M2' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M2' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M2' , 'via12' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via23) + , ('minWidth' , 'via23' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via23' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M2' , 'via23' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M2' , 'via23' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + + # MM1 (M3) + , ('minWidth' , 'M3' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M3' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M3' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M3' , 'via23' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M3' , 'via23' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via34) + , ('minWidth' , 'via34' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via34' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M3' , 'via34' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M3' , 'via34' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + # MM1 (M4) + , ('minWidth' , 'M4' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M4' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M4' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M4' , 'via34' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M4' , 'via34' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via45) + , ('minWidth' , 'via45' , 0.19 , Length , 'Vn.a') + , ('minSpacing' , 'via45' , 0.22 , Length , 'Vn.b') + , ('minEnclosure' , 'M4' , 'via45' , 0.05 , Length|Asymmetric, 'Vn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M4' , 'via45' , 0.05 , Length|Asymmetric, 'dup. Vn.c1') + + # MM5 (M5) + , ('minWidth' , 'M5' , 0.20 , Length , 'Mn.a') + , ('minSpacing' , 'M5' , 0.21 , Length , 'Mn.b') + , ('minArea' , 'M5' , 0.144 , Area , 'Mn.d') + , ('minEnclosure' , 'M5' , 'via45' , 0.05 , Length|Asymmetric, 'Mn.c1') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M5' , 'via45' , 0.05 , Length|Asymmetric, 'Mn.c1') + + # VIM (via56 TopVia1) + , ('minWidth' , 'via56' , 0.42 , Length , 'TV1.a') + , ('minSpacing' , 'via56' , 0.42 , Length , 'TV1.b') + , ('minEnclosure' , 'M5' , 'via56' , 0.1 , Length|Asymmetric, 'TV1.c') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M5' , 'via56' , 0.1 , Length|Asymmetric, 'dup. TV1.c') + + # MM6 (M6) TopMetal1 + , ('minWidth' , 'M6' , 1.64 , Length , 'TM1.a') + , ('minSpacing' , 'M6' , 1.64 , Length , 'TM1.b') + #, ('minArea' , 'M6' , 0.24 , Area , 'M5.4a') + , ('minEnclosure' , 'M6' , 'via56' , 0.10 , Length|Asymmetric, 'TV1.c') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M6' , 'via56' , 0.10 , Length|Asymmetric, 'dup. TV1.c ') + + # VIM (via56 TopVia2) + , ('minWidth' , 'via56' , 0.90 , Length , 'TV2.a') + , ('minSpacing' , 'via56' , 1.06 , Length , 'TV2.b') + , ('minEnclosure' , 'M6' , 'via56' , 0.5 , Length|Asymmetric, 'TV2.c') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'M6' , 'via56' , 0.5 , Length|Asymmetric, 'dup. TV2.c') + + # MM5 (M7) TopMetal2 + , ('minWidth' , 'M7' , 2.00 , Length , 'TM2.a') + , ('minSpacing' , 'M7' , 2.00 , Length , 'TM2.b') + #, ('minArea' , 'M7' , 0.24 , Area , 'M5.4a') + , ('minEnclosure' , 'M7' , 'via56' , 0.50 , Length|Asymmetric, 'TV1.d') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'M7' , 'via56' , 0.50 , Length|Asymmetric, 'dup. TV1.d ') + + + + #capm + #, ('minWidth' , 'metcap' , 1.0 , Length , 'capm.1') + #, ('minWidth' , 'metcapdum' , 0.5 , Length , '') + #, ('maxWidth' , 'metcap' , 300.0 , Length , '') + #, ('maxWidth' , 'metbot' , 350.0 , Length , '') + #, ('minSpacing' , 'metcap' , 0.84 , Length , 'capm.2a') + #, ('minSpacing' , 'metbot' , 0.8 , Length , 'metcap.2b') + #, ('minSpacing' , 'cut1' , 'metcap' , 0.50 , Length , '') + #, ('minSpacing' , 'cut2' , 'metcap' , 0.50 , Length , 'capm.5') + #, ('minSpacingOnMetbot', 'cut2' , 0.2 , Length , 'via34.2') + #, ('minSpacingOnMetbot', 'via34' , 0.2 , Length , 'via34.2') + #, ('minSpacingOnMetcap', 'cut2' , 0.2 , Length , 'via34.2') + #, ('minEnclosure' , 'M3' , 'metcap' , 0.14 , Length|Asymmetric, 'capm.3') + #, ('minEnclosure' , 'metbot' , 'cut1' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'metbot' , 'cut2' , 0.04 , Length|Asymmetric, 'via34.14') + #, ('minEnclosure' , 'metcap' , 'cut2' , 0.14 , Length|Asymmetric, 'capm.4') + #, ('minArea' , 'metcap' , 0 , Area , 'na') + #, ('minAreaInMetcap' , 'cut2' , 0 , Area , 'na') + #, ('MIMCap' , 1.25 , Unit , 'na') + #, ('MIMPerimeterCap' , 0.17 , Unit , 'na') + + + #capm + , ('minWidth' , 'capm' , 1.14 , Length , 'MIM.a') + #, ('minWidth' , 'capmdum' , 0.5 , Length , '') + #, ('maxWidth' , 'capm' , 30.0 , Length , '') + #, ('maxWidth' , 'metbot' , 35.0 , Length , '') + , ('minSpacing' , 'capm' , 0.60 , Length , 'MIM.b') + #, ('minSpacing' , 'M4' , 0.8 , Length , 'capm.2b') + , ('minSpacingWide1' , 'M3' , 0.8 , Length , 'capm.2b') + , ('minSpacing' , 'M6' , 'capm' , 0.60 , Length , 'MIM.e') + , ('minSpacing' , 'via34' , 'capm' , 0.50 , Length , 'capm.5') + , ('minSpacingOnMetBot', 'via34' , 0.2 , Length , 'via34.2') + , ('minSpacingOnMetCap', 'via34' , 0.2 , Length , 'via34.2') + , ('minSpacingOnMetBot', 'via23' , 0.2 , Length , 'via34.2 fake') + , ('minSpacingOnMetCap', 'via23' , 0.2 , Length , 'via34.2 fake') + , ('minEnclosure' , 'M5' , 'capm' , 0.60 , Length|Asymmetric, 'MIM.c') + #, ('minEnclosure' , 'M4' , 'via23' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'M4' , 'via34' , 0.04 , Length|Asymmetric, 'via34.14') + #, ('minEnclosure' , 'capm' , 'via23' , 0.14 , Length|Asymmetric, 'capm.4 fake') + , ('minEnclosure' , 'capm' , 'via56' , 0.36 , Length|Asymmetric, 'MIM.d') + , ('minArea' , 'capm' , 1.30 , Area , 'MIM.f') + , ('minAreaInMetcap' , 'via34' , 0 , Area , 'na') + , ('MIMCap' , 1.25 , Unit , 'na') + , ('MIMPerimeterCap' , 0.17 , Unit , 'na') + , ('PIPCap' , 1.25 , Unit , 'na') + , ('PIPPerimeterCap' , 0.17 , Unit , 'na') + + ) + + +def _loadDtr (): + """ + Load design kit physical rules for IHP 130nm. + """ + loadAnalogTechno( analogTechnologyTable, __file__ ) + + +def _loadDevices (): + addDevice( name = 'DifferentialPairBulkConnected' + #, spice = spiceDir+'DiffPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'DifferentialPairBulkUnconnected' + #, spice = spiceDir+'DiffPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'LevelShifterBulkUnconnected' + #, spice = spiceDir+'LevelShifterBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S1', 'S2', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.LS_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.LS_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.LS_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.LS_interdigitated.py' ) + ) + ) + addDevice( name = 'TransistorBulkConnected' + #, spice = spiceDir+'TransistorBulkConnected.spi' + , connectors = ( 'D', 'G', 'S' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'TransistorBulkUnconnected' + #, spice = spiceDir+'TransistorBulkUnconnected.spi' + , connectors = ( 'D', 'G', 'S', 'B' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkConnected' + #, spice = spiceDir+'CCPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkUnconnected' + #, spice = spiceDir+'CCPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkConnected' + #, spice = spiceDir+'CommonSourcePairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkUnconnected' + #, spice = spiceDir+'CommonSourcePairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkConnected' + #, spice = spiceDir+'CurrMirBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkUnconnected' + #, spice = spiceDir+'CurrMirBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'MultiCapacitor' + #, spice = spiceDir+'MIM_OneCapacitor.spi' + , connectors = ( 'T1', 'B1' ) + , layouts = ( ('Matrix', 'coriolis.oroshi.multicapacitor.py' ), + ) + ) + #addDevice( name = 'Resistor' + # #, spice = spiceDir+'MIM_OneCapacitor.spi' + # , connectors = ( 'PIN1', 'PIN2' ) + # , layouts = ( ('Snake', 'coriolis.oroshi.resistorsnake.py' ), + # ) + # ) + + +def _setup_techno ( coriolisTechDir ): + ShellEnv.RDS_TECHNO_NAME = (coriolisTechDir / 'sg13g2_nsx2' / 'sg13g2.rds').as_posix() + ShellEnv.GRAAL_TECHNO_NAME = (coriolisTechDir / 'sg13g2_nsx2' / 'symbolic.graal' ).as_posix() + ShellEnv.DREAL_TECHNO_NAME = (coriolisTechDir / 'sg13g2_nsx2' / 'symbolic.dreal' ).as_posix() + + db = DataBase.getDB() + CRL.System.get() + + tech = Technology.create(db, 'sg13g2_nsx2') + + DbU.setPrecision( 2 ) + DbU.setPhysicalsPerGrid( 0.001, DbU.UnitPowerMicro ) + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + cfg.gdsDriver.metricDbu = 1e-09 + cfg.gdsDriver.dbuPerUu = 0.001 + DbU.setGridsPerLambda ( 30 ) + DbU.setSymbolicSnapGridStep( DbU.fromGrid( 1.0 )) + DbU.setPolygonStep ( DbU.fromGrid( 1.0 )) + DbU.setStringMode ( DbU.StringModePhysical, DbU.UnitPowerMicro ) + + createBL( tech, 'nwm' , BasicLayer.Material.nWell , size=u(0.62), spacing=u(0.62), gds2Layer= 31, gds2DataType= 0 ) + createBL( tech, 'nsdm' , BasicLayer.Material.nImplant, size=u(0.31), spacing=u(0.31), area=0.25, gds2Layer= 7, gds2DataType= 0 ) + createBL( tech, 'psdm' , BasicLayer.Material.pImplant, size=u(0.31), spacing=u(0.31), area=0.25, gds2Layer= 14, gds2DataType= 0 ) + #createBL( tech, 'hvi' , BasicLayer.Material.other , gds2Layer= 75, gds2DataType= 20 ) + createBL( tech, 'activ.pin' , BasicLayer.Material.other , gds2Layer= 1, gds2DataType= 2 ) + #createBL( tech, 'activ.block', BasicLayer.Material.blockage, gds2Layer=1, gds2DataType= 23 ) + createBL( tech, 'poly.pin' , BasicLayer.Material.other , gds2Layer= 5, gds2DataType= 2 ) + #createBL( tech, 'poly.block' , BasicLayer.Material.blockage, gds2Layer=5, gds2DataType= 23 ) + createBL( tech, 'M1.pin' , BasicLayer.Material.other , gds2Layer= 8, gds2DataType= 2 ) + #createBL( tech, 'M1.block' , BasicLayer.Material.blockage, gds2Layer=8, gds2DataType= 23 ) + createBL( tech, 'M2.pin' , BasicLayer.Material.other , gds2Layer= 10, gds2DataType= 2 ) + #createBL( tech, 'M2.block' , BasicLayer.Material.blockage, gds2Layer=10, gds2DataType= 23 ) + createBL( tech, 'M3.pin' , BasicLayer.Material.other , gds2Layer= 30, gds2DataType= 2 ) + #createBL( tech, 'M3.block' , BasicLayer.Material.blockage, gds2Layer=30, gds2DataType= 23 ) + createBL( tech, 'M4.pin' , BasicLayer.Material.other , gds2Layer= 50, gds2DataType= 2 ) + #createBL( tech, 'M4.block' , BasicLayer.Material.blockage, gds2Layer=50, gds2DataType=23 ) + createBL( tech, 'M5.pin' , BasicLayer.Material.other , gds2Layer= 67, gds2DataType= 2 ) + #createBL( tech, 'M5.block' , BasicLayer.Material.blockage, gds2Layer=67, gds2DataType=23 ) + createBL( tech, 'M6.pin' , BasicLayer.Material.other , gds2Layer= 126, gds2DataType= 2 ) + #createBL( tech, 'M6.block' , BasicLayer.Material.blockage, gds2Layer=126, gds2DataType=23 ) + #createBL( tech, 'cont.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 30 ) + #createBL( tech, 'via12.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 50 ) + #createBL( tech, 'via23.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 70 ) + #createBL( tech, 'via34.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 90 ) + #createBL( tech, 'via45.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=110 ) + #createBL( tech, 'via56.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=130 ) + createBL( tech, 'activ' , BasicLayer.Material.active , size=u(0.15), spacing=u(0.21), gds2Layer= 1, gds2DataType= 0 ) + createBL( tech, 'poly' , BasicLayer.Material.poly , size=u(0.13), spacing=u(0.18), gds2Layer= 5, gds2DataType= 0 ) + createBL( tech, 'cont' , BasicLayer.Material.cut , size=u(0.16), spacing=u(0.18), gds2Layer= 6, gds2DataType= 0 ) + createBL( tech, 'M1' , BasicLayer.Material.metal , size=u(0.16), spacing=u(0.18), area=0.009, gds2Layer= 8, gds2DataType= 0 ) + createBL( tech, 'via12' , BasicLayer.Material.cut , size=u(0.19), spacing=u(0.22), gds2Layer= 19, gds2DataType= 0 ) + createBL( tech, 'M2' , BasicLayer.Material.metal , size=u(0.20), spacing=u(0.21), area=0.144, gds2Layer= 10, gds2DataType= 0 ) + createBL( tech, 'via23' , BasicLayer.Material.cut , size=u(0.19), spacing=u(0.22), gds2Layer= 29, gds2DataType= 0 ) + createBL( tech, 'M3' , BasicLayer.Material.metal , size=u(0.19), spacing=u(0.21), area=0.144, gds2Layer= 30, gds2DataType= 0 ) + createBL( tech, 'capm' , BasicLayer.Material.metal ) + createBL( tech, 'via34' , BasicLayer.Material.cut , size=u(0.19 ), spacing=u(0.22), gds2Layer= 49, gds2DataType= 0 ) + createBL( tech, 'M4' , BasicLayer.Material.metal , size=u(0.19 ), spacing=u(0.21 ), area=0.144, gds2Layer= 50, gds2DataType= 0 ) + createBL( tech, 'via45' , BasicLayer.Material.cut , size=u(0.19 ), spacing=u(0.22), gds2Layer= 49, gds2DataType= 0 ) + createBL( tech, 'M5' , BasicLayer.Material.metal , size=u(0.19 ), spacing=u(0.21 ), area=0.144, gds2Layer=67, gds2DataType= 0 ) + createBL( tech, 'via56' , BasicLayer.Material.cut , size=u(0.42 ), spacing=u(0.42 ), gds2Layer= 125, gds2DataType= 0 ) + createBL( tech, 'M6' , BasicLayer.Material.metal , size=u(1.64), spacing=u(1.64), gds2Layer= 126, gds2DataType= 0 ) + createBL( tech, 'hvtp' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 78, gds2DataType= 44 ) + createBL( tech, 'lvtn' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer=125, gds2DataType= 44 ) + createBL( tech, 'areaid_sc' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 4 ) + createBL( tech, 'pad' , BasicLayer.Material.cut , size=u(40.0), spacing=u(1.27), gds2Layer= 76, gds2DataType= 20 ) + createBL( tech, 'areaid_diode' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 23 ) + createBL( tech, 'pnp' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 44 ) + createBL( tech, 'diffres' , BasicLayer.Material.other , gds2Layer= 65, gds2DataType= 13 ) + createBL( tech, 'npn' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 20 ) + createBL( tech, 'polyres' , BasicLayer.Material.other , gds2Layer= 66, gds2DataType= 13 ) + createBL( tech, 'prBoundary' , BasicLayer.Material.other , gds2Layer=235, gds2DataType= 4 ) + + tech.addLayerAlias( 'M2', 'met1' ) + tech.addLayerAlias( 'M3', 'met2' ) + tech.addLayerAlias( 'M4', 'met3' ) + tech.addLayerAlias( 'M5', 'met4' ) + tech.addLayerAlias( 'M6', 'met5' ) + + # ViaLayers + createVia( tech, 'li_via12_M2' , 'M1' , 'via12', 'M2', u(0.17) ) + createVia( tech, 'M2_via_M3' , 'M2' , 'via23' , 'M3', u(0.15) ) + createVia( tech, 'M3_via34_M4' , 'M3' , 'via34', 'M4', u(0.2 ) ) + createVia( tech, 'M4_via45_M5' , 'M4' , 'via45', 'M5', u(0.2 ) ) + createVia( tech, 'M5_via56_M6' , 'M5' , 'via56', 'M6', u(0.8 ) ) + createVia( tech, 'capm_via56', 'capm', 'via56', 'M6', u(0.2 ) ) + + # Blockages + #ech.getLayer('activ' ).setBlockageLayer( tech.getLayer('activ.block') ) + #ech.getLayer('poly') .setBlockageLayer( tech.getLayer('poly.block') ) + #ech.getLayer('M1') .setBlockageLayer( tech.getLayer('M1.block') ) + #ech.getLayer('M2') .setBlockageLayer( tech.getLayer('M2.block') ) + #ech.getLayer('M3') .setBlockageLayer( tech.getLayer('M3.block') ) + #ech.getLayer('M4') .setBlockageLayer( tech.getLayer('M4.block') ) + #ech.getLayer('M5') .setBlockageLayer( tech.getLayer('M5.block') ) + #ech.getLayer('M6') .setBlockageLayer( tech.getLayer('M6.block') ) + #ech.getLayer('cont' ) .setBlockageLayer( tech.getLayer('cont.block') ) + #ech.getLayer('via12') .setBlockageLayer( tech.getLayer('via12.block') ) + #ech.getLayer('via23') .setBlockageLayer( tech.getLayer('via23.block') ) + #ech.getLayer('via34') .setBlockageLayer( tech.getLayer('via34.block') ) + #ech.getLayer('via45') .setBlockageLayer( tech.getLayer('via45.block') ) + #ech.getLayer('via56') .setBlockageLayer( tech.getLayer('via56.block') ) + + # Coriolis internal layers + createBL( tech, 'text.cell' , BasicLayer.Material.other, ) + createBL( tech, 'text.instance', BasicLayer.Material.other, ) + createBL( tech, 'SPL1' , BasicLayer.Material.other, ) + createBL( tech, 'AutoLayer' , BasicLayer.Material.other, ) + createBL( tech, 'gmetalh' , BasicLayer.Material.metal, ) + createBL( tech, 'gcontact' , BasicLayer.Material.cut, ) + createBL( tech, 'gmetalv' , BasicLayer.Material.metal, ) + + # Resistors + # ResistorLayer.create(tech, 'poly_res', 'poly', 'polyres') + # ResistorLayer.create(tech, 'active_res', 'activ' , 'diffres') + + # Transistors + # GateLayer.create(tech, 'hvmosgate' , 'activ' , 'poly', 'hvi') + # GateLayer.create(tech, 'mosgate' , 'activ' , 'poly') + # GateLayer.create(tech, 'mosgate_sc', 'activ' , 'poly') + # TransistorLayer.create(tech, 'nfet_01v8' , 'mosgate' , 'nsdm') + # TransistorLayer.create(tech, 'nfet_01v8_lvt' , 'mosgate' , ('nsdm', 'lvtn')) + # TransistorLayer.create(tech, 'nfet_01v8_sc' , 'mosgate_sc', 'nsdm') + # TransistorLayer.create(tech, 'nfet_g5v0d10v5', 'hvmosgate' , 'nsdm') + # TransistorLayer.create(tech, 'pfet_01v8' , 'mosgate' , 'psdm', 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_hvt' , 'mosgate' , ('psdm', 'hvtp'), 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_lvt' , 'mosgate' , ('psdm', 'lvtn'), 'nwm') + # TransistorLayer.create(tech, 'pfet_g5v0d10v5', 'hvmosgate' , 'psdm', 'nwm') + + # Bipolars + # Not implemented: Bipolar 'pnp_05v5_w0u68l0u68' + # Not implemented: Bipolar 'npn_05v5_w1u00l2u00' + # Not implemented: Bipolar 'pnp_05v5_w3u40l3u40' + # Not implemented: Bipolar 'npn_05v5_w1u00l1u00' + + +def _setup_display (): + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [black] + + threshold = 0.2 if Viewer.Graphics.isHighDpi() else 0.1 + + style = Viewer.DisplayStyle( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - black background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + # Viewer. + style.addDrawingStyle( group='Viewer', name='fallback' , color=toRGB('Gray238' ), border=1, pattern='55AA55AA55AA55AA' ) + style.addDrawingStyle( group='Viewer', name='background' , color=toRGB('Gray50' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='rubber' , color=toRGB('192,0,192' ), border=4, threshold=0.02 ) + style.addDrawingStyle( group='Viewer', name='phantom' , color=toRGB('Seashell4' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries' , color=toRGB('wheat1' ), border=2, pattern='0000000000000000', threshold=0 ) + style.addDrawingStyle( group='Viewer', name='marker' , color=toRGB('80,250,80' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionDraw' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionFill' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='grid' , color=toRGB('White' ), border=1, threshold=2.0 ) + style.addDrawingStyle( group='Viewer', name='spot' , color=toRGB('White' ), border=2, threshold=6.0 ) + style.addDrawingStyle( group='Viewer', name='ghost' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='text.ruler' , color=toRGB('White' ), border=1, threshold= 0.0 ) + style.addDrawingStyle( group='Viewer', name='text.instance' , color=toRGB('White' ), border=1, threshold=400.0 ) + style.addDrawingStyle( group='Viewer', name='text.reference', color=toRGB('White' ), border=1, threshold=200.0 ) + style.addDrawingStyle( group='Viewer', name='undef' , color=toRGB('Violet' ), border=0, pattern='2244118822441188' ) + + # Active Layers. + style.addDrawingStyle(group='Active Layers', name='nwm' , color=toRGB('Tan' ), pattern=toHexa('urgo.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='nsdm' , color=toRGB('LawnGreen'), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='psdm' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='hvtp' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='lvtn' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='activ' , color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='activ.pin', color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly.pin' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + + # Routing Layers. + style.addDrawingStyle(group='Routing Layers', name='M1' , color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M1.pin', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M2' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M2.pin', color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M3' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M3.pin', color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M4' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M4.pin', color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M5' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M5.pin', color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M6' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='M6.pin', color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + + # Cuts (VIA holes). + style.addDrawingStyle(group='Cuts (VIA holes', name='cont' , color=toRGB('0,150,150'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via12' , color=toRGB('Aqua' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via23' , color=toRGB('LightPink'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via34' , color=toRGB('Green' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via45' , color=toRGB('Yellow' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via56' , color=toRGB('Violet' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='pad' , color=toRGB('Red' ), threshold=threshold) + + # Blockages. + #style.addDrawingStyle(group='Blockages', name='activ.block', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='poly.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M1.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M2.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M3.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M4.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M5.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='M6.block' , color=toRGB('Blue' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='cont.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via12.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via23.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via34.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via45.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + #style.addDrawingStyle(group='Blockages', name='via56.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) +# + # Knick & Kite. + style.addDrawingStyle( group='Knik & Kite', name='SPL1' , color=toRGB('Red' ) ) + style.addDrawingStyle( group='Knik & Kite', name='AutoLayer' , color=toRGB('Magenta' ) ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalh' , color=toRGB('128,255,200'), pattern=toHexa('antislash2.32' ), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalv' , color=toRGB('200,200,255'), pattern=toHexa('light_antihash1.8'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gcontact' , color=toRGB('255,255,190'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::Edge' , color=toRGB('255,255,190'), pattern='0000000000000000' , border=4, threshold=0.02 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::GCell', color=toRGB('255,255,190'), pattern='0000000000000000' , border=2, threshold=threshold ) + + Viewer.Graphics.addStyle( style ) + + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [white]. + + style = Viewer.DisplayStyle( 'Alliance.Classic [white]' ) + style.inheritFrom( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - white background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + style.addDrawingStyle( group='Viewer', name='background', color=toRGB('White'), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground', color=toRGB('Black'), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries', color=toRGB('Black'), border=1, pattern='0000000000000000' ) + Viewer.Graphics.addStyle( style ) + + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + +def setup ( coriolisTechDir ): + _setup_techno( coriolisTechDir ) + _setup_display() + try: + from .techno_symb import setup as setupSymbolic + except: + pass + else: + setupSymbolic() + _loadDtr() + _loadDevices() + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/techno_symb.py b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/techno_symb.py new file mode 100644 index 000000000..7993a9a04 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/coriolis/sg13g2_nsx2/techno_symb.py @@ -0,0 +1,284 @@ + +from coriolis.helpers import l, u, n +from coriolis.Hurricane import DataBase, Technology, Layer, BasicLayer, DiffusionLayer, \ + TransistorLayer, RegularLayer, ContactLayer, ViaLayer + +__all__ = [ 'setup' ] + + +def setup (): + tech = DataBase.getDB().getTechnology() + tech.addLayerAlias( 'nwm' , 'nWell' ) + tech.addLayerAlias( 'activ' , 'active' ) + #tech.addLayerAlias( 'poly' , 'poly' ) + tech.addLayerAlias( 'psdm' , 'pImplant' ) + tech.addLayerAlias( 'nsdm' , 'nImplant' ) + tech.addLayerAlias( 'cont' , 'cut0' ) + tech.addLayerAlias( 'M1' , 'metal1' ) + tech.addLayerAlias( 'via12' , 'cut1' ) + tech.addLayerAlias( 'M2' , 'metal2' ) + tech.addLayerAlias( 'via23' , 'cut2' ) + tech.addLayerAlias( 'M3' , 'metal3' ) + tech.addLayerAlias( 'via34' , 'cut3' ) + tech.addLayerAlias( 'M4' , 'metal4' ) + tech.addLayerAlias( 'via45' , 'cut4' ) + tech.addLayerAlias( 'M5' , 'metla5' ) + tech.addLayerAlias( 'via56' , 'cut5' ) + tech.addLayerAlias( 'M6' , 'metal6' ) + tech.addLayerAlias( 'M1.block', 'blockage1' ) + tech.addLayerAlias( 'M2.block', 'blockage2' ) + tech.addLayerAlias( 'M3.block', 'blockage3' ) + tech.addLayerAlias( 'M4.block', 'blockage4' ) + tech.addLayerAlias( 'M5.block', 'blockage5' ) + tech.addLayerAlias( 'M6.block', 'blockage6' ) + tech.addLayerAlias( 'capm' , 'metcap' ) + tech.addLayerAlias( 'capm' , 'metcapdum' ) + tech.addLayerAlias( 'M5' , 'metbot' ) + + nWell = tech.getBasicLayer( 'nwm' ) + active = tech.getBasicLayer( 'activ' ) + poly = tech.getBasicLayer( 'poly' ) + pImplant = tech.getBasicLayer( 'psdm' ) + nImplant = tech.getBasicLayer( 'nsdm' ) + cut0 = tech.getBasicLayer( 'cont' ) + metal1 = tech.getBasicLayer( 'M1' ) + cut1 = tech.getBasicLayer( 'via12' ) + metal2 = tech.getBasicLayer( 'M2' ) + cut2 = tech.getBasicLayer( 'via23' ) + metal3 = tech.getBasicLayer( 'M3' ) + cut3 = tech.getBasicLayer( 'via34' ) + metal4 = tech.getBasicLayer( 'M4' ) + cut4 = tech.getBasicLayer( 'via45' ) + metal5 = tech.getBasicLayer( 'M5' ) + cut5 = tech.getBasicLayer( 'via56' ) + metal6 = tech.getBasicLayer( 'M6' ) + blockage1 = tech.getBasicLayer( 'blockage1' ) + blockage2 = tech.getBasicLayer( 'blockage2' ) + blockage3 = tech.getBasicLayer( 'blockage3' ) + blockage4 = tech.getBasicLayer( 'blockage4' ) + blockage5 = tech.getBasicLayer( 'blockage5' ) + blockage6 = tech.getBasicLayer( 'blockage6' ) + + # Composite/Symbolic layers. + NWELL = RegularLayer .create( tech, 'NWELL' , nWell ) + #PWELL = RegularLayer .create( tech, 'PWELL' , pWell ) + NTIE = DiffusionLayer .create( tech, 'NTIE' , nImplant , active, nWell) + PTIE = DiffusionLayer .create( tech, 'PTIE' , pImplant , active, None) + NDIF = DiffusionLayer .create( tech, 'NDIF' , nImplant , active, None ) + PDIF = DiffusionLayer .create( tech, 'PDIF' , pImplant , active, None ) + GATE = DiffusionLayer .create( tech, 'GATE' , poly , active, None ) + NTRANS = TransistorLayer.create( tech, 'NTRANS' , nImplant , active, poly, None ) + PTRANS = TransistorLayer.create( tech, 'PTRANS' , pImplant , active, poly, nWell ) + POLY = RegularLayer .create( tech, 'POLY' , poly ) + METAL1 = RegularLayer .create( tech, 'METAL1' , metal1 ) + METAL2 = RegularLayer .create( tech, 'METAL2' , metal2 ) + METAL3 = RegularLayer .create( tech, 'METAL3' , metal3 ) + METAL4 = RegularLayer .create( tech, 'METAL4' , metal4 ) + METAL5 = RegularLayer .create( tech, 'METAL5' , metal5 ) + METAL6 = RegularLayer .create( tech, 'METAL6' , metal6 ) + CONT_BODY_N = ContactLayer .create( tech, 'CONT_BODY_N', nImplant , active, cut0, metal1, None ) + CONT_BODY_P = ContactLayer .create( tech, 'CONT_BODY_P', pImplant , active, cut0, metal1, None ) + CONT_DIF_N = ContactLayer .create( tech, 'CONT_DIF_N' , nImplant , active, cut0, metal1, None ) + CONT_DIF_P = ContactLayer .create( tech, 'CONT_DIF_P' , pImplant , active, cut0, metal1, None ) + CONT_POLY = ViaLayer .create( tech, 'CONT_POLY' , poly, cut0, metal1 ) + + # VIAs for symbolic technologies. + VIA12 = ViaLayer .create( tech, 'VIA12' , metal1, cut1, metal2 ) + VIA23 = ViaLayer .create( tech, 'VIA23' , metal2, cut2, metal3 ) + #VIA23cap = ViaLayer .create( tech, 'VIA23cap' , metcap, cut2, metal3 ) + VIA34 = ViaLayer .create( tech, 'VIA34' , metal3, cut3, metal4 ) + VIA45 = ViaLayer .create( tech, 'VIA45' , metal4, cut4, metal5 ) + VIA56 = ViaLayer .create( tech, 'VIA56' , metal5, cut5, metal6 ) + #BLOCKAGE1 = RegularLayer.create( tech, 'BLOCKAGE1' , blockage1 ) + #BLOCKAGE2 = RegularLayer.create( tech, 'BLOCKAGE2' , blockage2 ) + #BLOCKAGE3 = RegularLayer.create( tech, 'BLOCKAGE3' , blockage3 ) + #BLOCKAGE4 = RegularLayer.create( tech, 'BLOCKAGE4' , blockage4 ) + #BLOCKAGE5 = RegularLayer.create( tech, 'BLOCKAGE5' , blockage5 ) + #BLOCKAGE6 = RegularLayer.create( tech, 'BLOCKAGE6' , blockage6 ) + + tech.setSymbolicLayer( CONT_BODY_N.getName() ) + tech.setSymbolicLayer( CONT_BODY_P.getName() ) + tech.setSymbolicLayer( CONT_DIF_N .getName() ) + tech.setSymbolicLayer( CONT_DIF_P .getName() ) + tech.setSymbolicLayer( CONT_POLY .getName() ) + tech.setSymbolicLayer( POLY .getName() ) + tech.setSymbolicLayer( METAL1 .getName() ) + tech.setSymbolicLayer( METAL2 .getName() ) + tech.setSymbolicLayer( METAL3 .getName() ) + tech.setSymbolicLayer( METAL4 .getName() ) + tech.setSymbolicLayer( METAL5 .getName() ) + tech.setSymbolicLayer( METAL6 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE1 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE2 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE3 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE4 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE5 .getName() ) + #tech.setSymbolicLayer( BLOCKAGE6 .getName() ) + tech.setSymbolicLayer( VIA12 .getName() ) + tech.setSymbolicLayer( VIA23 .getName() ) + tech.setSymbolicLayer( VIA34 .getName() ) + tech.setSymbolicLayer( VIA45 .getName() ) + tech.setSymbolicLayer( VIA56 .getName() ) + + NWELL.setExtentionCap( nWell, l(0.0) ) + #PWELL.setExtentionCap( pWell, l(0.0) ) + + NTIE.setMinimalSize ( l(3.0) ) + NTIE.setExtentionCap ( nWell , l(1.5) ) + NTIE.setExtentionWidth( nWell , l(0.5) ) + NTIE.setExtentionCap ( nImplant, l(1.0) ) + NTIE.setExtentionWidth( nImplant, l(0.5) ) + NTIE.setExtentionCap ( active , l(0.5) ) + NTIE.setExtentionWidth( active , l(0.0) ) + + PTIE.setMinimalSize ( l(3.0) ) + PTIE.setExtentionCap ( nWell , l(1.5) ) + PTIE.setExtentionWidth( nWell , l(0.5) ) + PTIE.setExtentionCap ( nImplant, l(1.0) ) + PTIE.setExtentionWidth( nImplant, l(0.5) ) + PTIE.setExtentionCap ( active , l(0.5) ) + PTIE.setExtentionWidth( active , l(0.0) ) + + NDIF.setMinimalSize ( l(3.0) ) + NDIF.setExtentionCap ( nImplant, l(1.0) ) + NDIF.setExtentionWidth( nImplant, l(0.5) ) + NDIF.setExtentionCap ( active , l(0.5) ) + NDIF.setExtentionWidth( active , l(0.0) ) + + PDIF.setMinimalSize ( l(3.0) ) + PDIF.setExtentionCap ( pImplant, l(1.0) ) + PDIF.setExtentionWidth( pImplant, l(0.5) ) + PDIF.setExtentionCap ( active , l(0.5) ) + PDIF.setExtentionWidth( active , l(0.0) ) + + GATE.setMinimalSize ( l(1.0) ) + GATE.setExtentionCap ( poly , l(1.5) ) + + NTRANS.setMinimalSize ( l( 1.0) ) + NTRANS.setExtentionCap ( nImplant, l(-1.0) ) + NTRANS.setExtentionWidth( nImplant, l( 2.5) ) + NTRANS.setExtentionCap ( active , l(-1.5) ) + NTRANS.setExtentionWidth( active , l( 2.0) ) + + PTRANS.setMinimalSize ( l( 1.0) ) + PTRANS.setExtentionCap ( nWell , l(-1.0) ) + PTRANS.setExtentionWidth( nWell , l( 4.5) ) + PTRANS.setExtentionCap ( pImplant, l(-1.0) ) + PTRANS.setExtentionWidth( pImplant, l( 4.0) ) + PTRANS.setExtentionCap ( active , l(-1.5) ) + PTRANS.setExtentionWidth( active , l( 3.0) ) + + POLY .setMinimalSize ( l(1.0) ) + POLY .setExtentionCap ( poly , l(0.5) ) + #POLY2.setMinimalSize ( l(1.0) ) + #POLY2.setExtentionCap ( poly , l(0.5) ) + + METAL1 .setMinimalSize ( l(1.0) ) + METAL1 .setExtentionCap ( metal1 , l(0.5) ) + METAL2 .setMinimalSize ( l(1.0) ) + METAL2 .setExtentionCap ( metal2 , l(1.0) ) + METAL3 .setMinimalSize ( l(1.0) ) + METAL3 .setExtentionCap ( metal3 , l(1.0) ) + METAL4 .setMinimalSize ( l(1.0) ) + METAL4 .setExtentionCap ( metal4 , l(1.0) ) + METAL4 .setMinimalSpacing( l(3.0) ) + METAL5 .setMinimalSize ( l(2.0) ) + METAL5 .setExtentionCap ( metal5 , l(1.0) ) + #METAL6 .setMinimalSize ( l(2.0) ) + #METAL6 .setExtentionCap ( metal6 , l(1.0) ) + #METAL7 .setMinimalSize ( l(2.0) ) + #METAL7 .setExtentionCap ( metal7 , l(1.0) ) + #METAL8 .setMinimalSize ( l(2.0) ) + #METAL8 .setExtentionCap ( metal8 , l(1.0) ) + #METAL9 .setMinimalSize ( l(2.0) ) + #METAL9 .setExtentionCap ( metal9 , l(1.0) ) + #METAL10.setMinimalSize ( l(2.0) ) + #METAL10.setExtentionCap ( metal10 , l(1.0) ) + + # Contacts (i.e. Active <--> Metal) (symbolic). + CONT_BODY_N.setMinimalSize( l( 1.0) ) + CONT_BODY_N.setEnclosure ( nWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( nImplant, l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( active , l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_BODY_P.setMinimalSize( l( 1.0) ) + #CONT_BODY_P.setEnclosure ( pWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( pImplant, l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( active , l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_N.setMinimalSize( l( 1.0) ) + CONT_DIF_N.setEnclosure ( nImplant, l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_P.setMinimalSize( l( 1.0) ) + CONT_DIF_P.setEnclosure ( pImplant, l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_POLY.setMinimalSize( l( 1.0) ) + CONT_POLY.setEnclosure ( poly , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_POLY.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + # VIAs (i.e. Metal <--> Metal) (symbolic). + VIA12 .setMinimalSize ( l( 1.0) ) + VIA12 .setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setEnclosure ( metal2 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setMinimalSpacing( l( 4.0) ) + VIA23 .setMinimalSize ( l( 1.0) ) + VIA23 .setEnclosure ( metal2 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setEnclosure ( metal3 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setMinimalSpacing( l( 4.0) ) + VIA34 .setMinimalSize ( l( 1.0) ) + VIA34 .setEnclosure ( metal3 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setEnclosure ( metal4 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setMinimalSpacing( l( 4.0) ) + VIA45 .setMinimalSize ( l( 1.0) ) + VIA45 .setEnclosure ( metal4 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setMinimalSpacing( l( 4.0) ) + #VIA56 .setMinimalSize ( l( 1.0) ) + #VIA56 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setMinimalSpacing( l( 4.0) ) + #VIA67 .setMinimalSize ( l( 1.0) ) + #VIA67 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSize ( l( 1.0) ) + #VIA78 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA89 .setMinimalSize ( l( 1.0) ) + #VIA89 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setMinimalSpacing( l( 4.0) ) + #VIA910.setMinimalSize ( l( 1.0) ) + #VIA910.setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setEnclosure ( metal10 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setMinimalSpacing( l( 4.0) ) + + # Blockages (symbolic). + #BLOCKAGE1 .setMinimalSize ( l( 1.0) ) + #BLOCKAGE1 .setExtentionCap( blockage1 , l( 0.5) ) + #BLOCKAGE2 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE2 .setExtentionCap( blockage2 , l( 0.5) ) + #BLOCKAGE3 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE3 .setExtentionCap( blockage3 , l( 0.5) ) + #BLOCKAGE4 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE4 .setExtentionCap( blockage4 , l( 0.5) ) + #BLOCKAGE5 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE5 .setExtentionCap( blockage5 , l( 1.0) ) + #BLOCKAGE6 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE6 .setExtentionCap( blockage6 , l( 1.0) ) + #BLOCKAGE7 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE7 .setExtentionCap( blockage7 , l( 1.0) ) + #BLOCKAGE8 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE8 .setExtentionCap( blockage8 , l( 1.0) ) + #BLOCKAGE9 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE9 .setExtentionCap( blockage9 , l( 1.0) ) + #BLOCKAGE10.setMinimalSize ( l( 2.0) ) + #BLOCKAGE10.setExtentionCap( blockage10, l( 1.0) ) diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/klayout/sg13g2.lydrc b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/klayout/sg13g2.lydrc new file mode 100644 index 000000000..da9e16eb6 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/klayout/sg13g2.lydrc @@ -0,0 +1,768 @@ + + + + + + drc + + + + false + false + + true + drc_scripts + tools_menu.drc.end + dsl + drc-dsl-xml + +application = RBA::Application.instance +#main_window = application.main_window +#if main_window +# curr_layout_view = main_window.current_view() +# unless curr_layout_view +# layout_path = RBA::FileDialog::ask_open_file_name("Chose your layout file.", ".", "GDSII files (*.GDS *.gds *.GDS.gz *.gds.gz *.GDS2 *.gds2 *.GDS2.gz *.gds2.gz);; All files (*)") +# main_window.load_layout(layout_path, 1) +# curr_layout_view = main_window.current_view() +# end +#end +#active_layout = RBA::CellView::active.layout +#active_cellname = RBA::CellView::active.cell_name +#source(active_layout, active_cellname) +if $input + source($input, $top_cell) +end + +if $report == "" + report("SG13G2 DRC runset") +elsif $report + report("SG13G2 DRC runset", $report) +else + report("SG13G2 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "sg13g2_drc.txt")) +end +#if $input.dbu != 0.001 +# puts "WARNING: Layout dbu value (" + $input.dbu.to_s + " ) deviates from rule file dbu value (0.001). This will scale the layout and may not be intended." +#end +#report("design rules: sg13g2 | layout cell: " + active_cellname, "sg13g2.lyrdb") + +deep + +# Initial definitions of control flow variables +conditional_enabled = {} +conditional_enabled[:density] = false +conditional_enabled[:sanityRules] = true + +class DRC::DRCLayer + def ext_and(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self & other + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_area(constraint) + output_layer = self.dup + constraint.each do |expression| + output_layer.data.min_coherence = true + relation = expression[0] + value = expression[1].to_i + if relation == ">" + output_layer = output_layer.with_area((value + 1), nil) + elsif relation == "<" + output_layer = output_layer.with_area(nil, value) + elsif relation == "==" + output_layer = output_layer.with_area(value) + elsif relation == "!=" + output_layer = output_layer.without_area(value) + elsif relation == ">=" + output_layer = output_layer.with_area(value, nil) + elsif relation == "<=" + output_layer = output_layer.with_area(nil, (value + 1)) + else + raise "invalid expression" + end + end + return output_layer + end + + def ext_constraint_satisfied(value, constraint) + output_bool = true + constraint.each do |expression| + if expression[0] == ">" + output_bool = output_bool && (value > expression[1]) + elsif expression[0] == "<" + output_bool = output_bool && (value < expression[1]) + elsif expression[0] == "==" + output_bool = output_bool && (value == expression[1]) + elsif expression[0] == "!=" + output_bool = output_bool && (value != expression[1]) + elsif expression[0] == ">=" + output_bool = output_bool && (value >= expression[1]) + elsif expression[0] == "<=" + output_bool = output_bool && (value <= expression[1]) + else + raise "invalid expression" + end + end + return output_bool + end + + def ext_covering(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self.covering(other.inside(self)) + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_not(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self - other + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_or(other) + self_min_coherence_state = self.data.min_coherence? + other_min_coherence_state = other.data.min_coherence? + self.data.min_coherence = true + other.data.min_coherence = true + output_layer = self | other + self.data.min_coherence = self_min_coherence_state + other.data.min_coherence = other_min_coherence_state + return output_layer + end + + def ext_rectangles(axis_aligned = false, use_bbox = false, constraint1 = nil, constraint2 = nil, aspect_ratio_constraint = nil, inverted: false) + self_min_coherence_state = self.data.min_coherence? + self.data.min_coherence = true + if ( ( constraint1 && ( !constraint2 || constraint1.length() > 1 || constraint1[0][0] != "==") ) || + ( constraint2 && ( constraint2.length() > 1 || constraint2[0][0] != "==" ) ) || + ( constraint1 && constraint2 && constraint1[0][1] != constraint2[0][1] ) ) + raise "ext_rectangle: unsupported options" + end + square = constraint1 ? true : false + shape_filter = + if use_bbox + @engine.extents + elsif axis_aligned + @engine.rectangles + else + @engine.if_all((@engine.corners == 270).count == 4, @engine.corners.count == 4) + end + if square + if use_bbox + shape_filter = @engine.if_all((@engine.extents.length == constraint1[0][1]).count == 4) + else + square_filter = (@engine.length == constraint1[0][1]).count == 4 + shape_filter = @engine.if_all(shape_filter, square_filter) + end + end + if inverted + output_layer = self.drc(! shape_filter) + else + output_layer = self.drc(shape_filter) + end + self.data.min_coherence = self_min_coherence_state + return output_layer + end + + def ext_ring + holes = self.holes + hulls = self.hulls + covering = hulls.covering(holes) + result = covering.and(self) + return result + end + + def ext_interacting_with_text(text_layer_number, text) + text_layer = @engine.labels(text_layer_number) + initial_merged_semantics = self.data.merged_semantics? + self.data.merged_semantics = false + result = self.interacting(text_layer.texts(text)) + self.data.merged_semantics = initial_merged_semantics + return result + end + + def ext_with_density(range, *args) + if self.is_empty? + return DRC::DRCLayer::new(@engine, RBA::Region::new()) + end + origin = 'cc' + tile_size = nil + tile_step = nil + arguments = [range] + args.each do |a| + if a.is_a?(DRC::DRCTileSize) + tile_size = a + arguments.push(tile_size) + elsif a.is_a?(DRC::DRCTileStep) + tile_step = a + arguments.push(tile_step) + elsif a.is_a?(String) + origin = a + else + raise "argument error" + end + end + bbox = @engine.extent.bbox + if origin == 'll' + origin_x = bbox.left + origin_y = bbox.bottom + tile_origin = DRC::DRCTileOrigin::new(origin_x, origin_y) + arguments.push(tile_origin) + elsif origin != 'cc' + raise "Unkown origin: 'cc' or 'll' expected" + end + if tile_size + return self.with_density(*arguments) + else + tile_size = DRC::DRCTileSize::new(bbox.width, bbox.height) + tile_count = DRC::DRCTileCount::new(1,2) + enlarged_bbox = bbox.enlarged(1.1).to_itype(@engine.dbu) + boundary_layer = DRC::DRCLayer::new(@engine, RBA::Region::new(enlarged_bbox)) + tile_boundary = DRC::DRCTileBoundary::new(boundary_layer) + result = self.with_density(*arguments, tile_size, tile_count, tile_boundary) + return result.raw.overlapping(DRC::DRCLayer::new(@engine, RBA::Region::new(bbox.to_itype(@engine.dbu)))) + end + end +end +NWell_org = source.polygons("31/0") +NWell_pin_org = source.polygons("31/2") +Activ_org = source.polygons("1/0") +Activ_pin_org = source.polygons("1/2") +Activ_filler_org = source.polygons("1/22") +ThickGateOx_org = source.polygons("44/0") +GatPoly_org = source.polygons("5/0") +GatPoly_pin_org = source.polygons("5/2") +GatPoly_filler_org = source.polygons("5/22") +Cont_org = source.polygons("6/0") +Metal1_org = source.polygons("8/0") +Metal1_pin_org = source.polygons("8/2") +Metal1_filler_org = source.polygons("8/22") +Metal1_slit_org = source.polygons("8/24") +Via1_org = source.polygons("19/0") +Metal2_org = source.polygons("10/0") +Metal2_pin_org = source.polygons("10/2") +Metal2_filler_org = source.polygons("10/22") +Metal2_slit_org = source.polygons("10/24") +Via2_org = source.polygons("29/0") +Metal3_org = source.polygons("30/0") +Metal3_pin_org = source.polygons("30/2") +Metal3_filler_org = source.polygons("30/22") +Metal3_slit_org = source.polygons("30/24") +Via3_org = source.polygons("49/0") +Metal4_org = source.polygons("50/0") +Metal4_pin_org = source.polygons("50/2") +Metal4_filler_org = source.polygons("50/22") +Metal4_slit_org = source.polygons("50/24") +Via4_org = source.polygons("66/0") +Metal5_org = source.polygons("67/0") +Metal5_pin_org = source.polygons("67/2") +Metal5_filler_org = source.polygons("67/22") +Metal5_slit_org = source.polygons("67/24") +TopVia1_org = source.polygons("125/0") +TopMetal1_org = source.polygons("126/0") +TopMetal1_pin_org = source.polygons("126/2") +TopMetal1_filler_org = source.polygons("126/22") +TopMetal1_slit_org = source.polygons("126/24") +Vmim_org = source.polygons("129/0") +TopVia2_org = source.polygons("133/0") +TopMetal2_org = source.polygons("134/0") +TopMetal2_pin_org = source.polygons("134/2") +TopMetal2_filler_org = source.polygons("134/22") +TopMetal2_slit_org = source.polygons("134/24") +Passiv_org = source.polygons("9/0") +EdgeSeal_org = source.polygons("39/0") +BiWind_org = source.polygons("3/0") +PEmWind_org = source.polygons("11/0") +BasPoly_org = source.polygons("13/0") +DeepCo_org = source.polygons("35/0") +PEmPoly_org = source.polygons("53/0", "70/0") +EmPoly_org = source.polygons("55/0") +LDMOS_org = source.polygons("57/0") +PBiWind_org = source.polygons("58/0") +Flash_org = source.polygons("71/0") +ColWind_org = source.polygons("139/0") +SRAM_org = source.polygons("25/0") +TRANS_org = source.polygons("26/0") +NoDRC = source.polygons("62/0") +LBE_org = source.polygons("157/0") +NWell = NWell_org.ext_not(NoDRC) +Activ = Activ_org.ext_not(NoDRC) +ThickGateOx = ThickGateOx_org.ext_not(NoDRC) +GatPoly = GatPoly_org.ext_not(NoDRC) +Cont = Cont_org.ext_not(NoDRC) +ActFiller = Activ_filler_org.ext_not(NoDRC) +GatFiller = GatPoly_filler_org.ext_not(NoDRC) +Activ_pin = Activ_pin_org.ext_not(NoDRC) +GatPoly_pin = GatPoly_pin_org.ext_not(NoDRC) +NWell_pin = NWell_pin_org.ext_not(NoDRC) +Metal1 = Metal1_org.ext_not(NoDRC) +Via1 = Via1_org.ext_not(NoDRC) +Metal2 = Metal2_org.ext_not(NoDRC) +Via2 = Via2_org.ext_not(NoDRC) +Metal3 = Metal3_org.ext_not(NoDRC) +Via3 = Via3_org.ext_not(NoDRC) +Metal4 = Metal4_org.ext_not(NoDRC) +Via4 = Via4_org.ext_not(NoDRC) +Metal5 = Metal5_org.ext_not(NoDRC) +Vmim = Vmim_org.ext_not(NoDRC) +TopMetal1 = TopMetal1_org.ext_not(NoDRC) +TopVia2 = TopVia2_org.ext_not(NoDRC) +TopMetal2 = TopMetal2_org.ext_not(NoDRC) +Passiv = Passiv_org.ext_not(NoDRC) +EdgeSeal = EdgeSeal_org.ext_not(NoDRC) +M1Filler = Metal1_filler_org.ext_not(NoDRC) +M2Filler = Metal2_filler_org.ext_not(NoDRC) +M3Filler = Metal3_filler_org.ext_not(NoDRC) +M4Filler = Metal4_filler_org.ext_not(NoDRC) +M5Filler = Metal5_filler_org.ext_not(NoDRC) +TopMet1Filler = TopMetal1_filler_org.ext_not(NoDRC) +TopMet2Filler = TopMetal2_filler_org.ext_not(NoDRC) +M1Slit = Metal1_slit_org.ext_not(NoDRC) +M2Slit = Metal2_slit_org.ext_not(NoDRC) +M3Slit = Metal3_slit_org.ext_not(NoDRC) +M4Slit = Metal4_slit_org.ext_not(NoDRC) +M5Slit = Metal5_slit_org.ext_not(NoDRC) +TopMet1Slit = TopMetal1_slit_org.ext_not(NoDRC) +TopMet2Slit = TopMetal2_slit_org.ext_not(NoDRC) +Metal1_pin = Metal1_pin_org.ext_not(NoDRC) +Metal2_pin = Metal2_pin_org.ext_not(NoDRC) +Metal3_pin = Metal3_pin_org.ext_not(NoDRC) +Metal4_pin = Metal4_pin_org.ext_not(NoDRC) +Metal5_pin = Metal5_pin_org.ext_not(NoDRC) +TopMetal1_pin = TopMetal1_pin_org.ext_not(NoDRC) +TopMetal2_pin = TopMetal2_pin_org.ext_not(NoDRC) +TRANS = TRANS_org.ext_not(NoDRC) +SRAM = SRAM_org.ext_not(NoDRC) +LBE = LBE_org.ext_not(NoDRC) +TopVia1 = NoDRC.ext_or(Vmim_org).ext_or(TopVia1_org.ext_not(NoDRC)) +Activ_Act_a = Activ.width(150) +ThickGateOx_TGO_f = ThickGateOx.width(860) +Cont_SQ = Cont.ext_rectangles(true, false, [["==", 160]], [["==", 160]], nil) +ContBar = Cont.ext_area([[">", (0.16*0.16)*1000.0*1000.0]]) +Act_density = ActFiller.ext_or(Activ) +Gat_density = GatFiller.ext_or(GatPoly) +Act_Nsram = Activ.ext_not(SRAM) +GP_Nsram = GatPoly.ext_not(SRAM) +M1_Nsram = Metal1.ext_not(SRAM) +M2_Nsram = Metal2.ext_not(SRAM) +M3_Nsram = Metal3.ext_not(SRAM) +M4_Nsram = Metal4.ext_not(SRAM) +M5_Nsram = Metal5.ext_not(SRAM) +M1_density = M1Filler.ext_or(Metal1).ext_not(M1Slit) +M2_density = M2Filler.ext_or(Metal2).ext_not(M2Slit) +M3_density = M3Filler.ext_or(Metal3).ext_not(M3Slit) +M4_density = M4Filler.ext_or(Metal4).ext_not(M4Slit) +M5_density = M5Filler.ext_or(Metal5).ext_not(M5Slit) +TM1_density = TopMet1Filler.ext_or(TopMetal1).ext_not(TopMet1Slit) +TM2_density = TopMet2Filler.ext_or(TopMetal2).ext_not(TopMet2Slit) +emi2Pin = Metal2_pin.ext_and(TRANS).ext_interacting_with_text(63, "E") +GP_Nsram_Gat_a = GP_Nsram.width(130) +GP_Nsram_Gat_b = GP_Nsram.space(180) +transG2L = TRANS.ext_interacting_with_text(63, "npn13G2L").ext_covering(emi2Pin) + +-> do + Activ_Act_a.dup +end.().output("Act.a", "Min. Activ width = 0.15") + +-> do + Act_Nsram.space(210) +end.().output("Act.b", "Act.b: Min. Activ space or notch = 0.21") + +-> do + ThickGateOx_TGO_f.dup +end.().output("TGO.f", "Min. ThickGateOx width = 0.86") + +-> do + GP_Nsram_Gat_a.dup +end.().output("Gat.a", "Min GatPoly width = 0.13") + +-> do + GP_Nsram_Gat_b.dup +end.().output("Gat.b", "Min. GatPoly space or notch = 0.18") + +-> do + GP_Nsram.separation(Act_Nsram, 70) +end.().output("Gat.d", "Min. GatPoly to Activ space = 0.07") + +-> do + Cont.merged(true, 0).outside(EdgeSeal).ext_not(ContBar.ext_or(Cont_SQ)) +end.().output("Cnt.a", "Min.and max. size of Cont = 0.16") + +-> do + Cont.merged(true, 0).outside(EdgeSeal).space(180) +end.().output("Cnt.b", "Min. Cont space = 0.18") + +-> do + Passiv.width(2100) +end.().output("Pas.a", "Min. Passiv width = 2.10") + +-> do + Passiv.space(3500) +end.().output("Pas.b", "Min. Passiv space or notch = 3.50") + +-> do + Metal1.width(160) +end.().output("M1.a", "Min. width of Metal1 = 0.16") + +-> do + M1_Nsram.space(180) +end.().output("M1.b", "Min. Metal1 space or notch = 0.18") + +-> do + Metal2.width(200) +end.().output("M2.a", "Min. width of Metal2 = 0.2") + +-> do + M2_Nsram.space(210) +end.().output("M2.b", "Min. Metal2 space or notch = 0.21") + +-> do + Metal3.width(200) +end.().output("M3.a", "Min. width of Metal3 = 0.2") + +-> do + M3_Nsram.space(210) +end.().output("M3.b", "Min. Metal3 space or notch = 0.21") + +-> do + Metal4.width(200) +end.().output("M4.a", "Min. width of Metal4 = 0.2") + +-> do + M4_Nsram.space(210) +end.().output("M4.b", "Min. Metal4 space or notch = 0.21") + +-> do + Metal5.width(200) +end.().output("M5.a", "Min. width of Metal5 = 0.2") + +-> do + M5_Nsram.space(210) +end.().output("M5.b", "Min. Metal5 space or notch = 0.21") + +-> do + Via1.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) +end.().output("Via1.a", "Via1.a: Min. and Maxi. size of Via1 = 0.19") + +-> do + Via1.ext_not(EdgeSeal).space(220) +end.().output("Via1.b", "Via1.b: Min. Via1 space = 0.22") + +-> do + Via2.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) +end.().output("Via2.a", "Via2.a: Min. and Maxi. size of Via2 = 0.19") + +-> do + Via2.ext_not(EdgeSeal).space(220) +end.().output("Via2.b", "Via2.b: Min. Via2 space = 0.22") + +-> do + Via3.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) +end.().output("Via3.a", "Via3.a: Min. and Maxi. size of Via3 = 0.19") + +-> do + Via3.ext_not(EdgeSeal).space(220) +end.().output("Via3.b", "Via3.b: Min. Via3 space = 0.22") + +-> do + Via4.ext_not(EdgeSeal).merged(true, 0).outside(transG2L).ext_rectangles(false, false, [["==", 190]], [["==", 190]], nil, inverted: true) +end.().output("Via4.a", "Via4.a: Min. and Maxi. size of Via4 = 0.19") + +-> do + Via4.ext_not(EdgeSeal).space(220) +end.().output("Via4.b", "Via4.b: Min. Via4 space = 0.22") + +-> do + Vmim.ext_or(TopVia1.ext_not(EdgeSeal)).ext_rectangles(false, false, [["==", 420]], [["==", 420]], nil, inverted: true) +end.().output("TV1.a", "Min.and Max. TopVia1 (µm²) = 0.42") + +-> do + TopVia1.ext_or(Vmim).space(420) +end.().output("TV1.b", "Min. TopVia1 space = 0.42") + +-> do + TopMetal1.width(1640) +end.().output("TM1.a", "Min. width of TopMetal1 = 1.64") + +-> do + TopMetal1.space(1640) +end.().output("TM1.b", "Min. TopMetal1 space or notch = 1.64") + +-> do + TopMetal2.width(2000) +end.().output("TM2.a", "Min. width of TopMetal2 = 2.0") + +-> do + TopMetal2.space(2000) +end.().output("TM2.b", "Min. TopMetal2 space or notch = 2.0") + +-> do + TopVia2.ext_not(EdgeSeal).ext_rectangles(false, false, [["==", 900]], [["==", 900]], nil, inverted: true) +end.().output("TV2.a", "Min.and Max. TopVia2 = 0.90") + +-> do + TopVia2.space(1060) +end.().output("TV2.b", "Min. TopVia2 space = 1.06") + +if conditional_enabled[:density] + + -> do + Act_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("aFil.g", "Min. global Activ coverage = 35.0 %") + + -> do + Act_density.ext_with_density(0.55 .. 1.0, 'll') + end.().output("aFil.g1", "Max. global Activ coverage = 55.0 %") + + -> do + Act_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("aFil.g2", "Min. Active coverage ratio for any 800 x 800 µm² chip area = 25.0 %") + + -> do + Act_density.ext_with_density(0.65 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("aFil.g3", "Max. Active coverage ratio for any 800 x 800 µm² chip area = 65.0 %") + + -> do + Gat_density.ext_with_density(0.0 .. 0.15, 'll') + end.().output("GFil.g", "Min. global GatPoly density [%] = 15.0") + + -> do + M1_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M1.j", "Min. global Metal1 density [%] = 35.0") + + -> do + M1_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M1.k", "Max. global Metal1 density [%] = 60.0") + + -> do + M2_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M2.j", "Min. global Metal2 density [%] = 35.0") + + -> do + M2_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M2.k", "Max. global Metal2 density [%] = 60.0") + + -> do + M3_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M3.j", "Min. global Metal3 density [%] = 35.0") + + -> do + M3_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M3.k", "Max. global Metal3 density [%] = 60.0") + + -> do + M4_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M4.j", "Min. global Metal4 density [%] = 35.0") + + -> do + M4_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M4.k", "Max. global Metal4 density [%] = 60.0") + + -> do + M5_density.ext_with_density(0.0 .. 0.35, 'll') + end.().output("M5.j", "Min. global Metal5 density [%] = 35.0") + + -> do + M5_density.ext_with_density(0.6 .. 1.0, 'll') + end.().output("M5.k", "Max. global Metal5 density [%] = 60.0") + + -> do + M1_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M1Fil.h", "Min. Metal coverage MM1Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") + + -> do + M1_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M1Fil.k", "Max. Metal coverage MM1Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") + + -> do + M2_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M2Fil.h", "Min. Metal coverage MM2Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") + + -> do + M2_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M2Fil.k", "Max. Metal coverage MM2Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") + + -> do + M3_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M3Fil.h", "Min. Metal coverage MM3Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") + + -> do + M3_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M3Fil.k", "Max. Metal coverage MM3Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") + + -> do + M4_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M4Fil.h", "Min. Metal coverage MM4Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") + + -> do + M4_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M4Fil.k", "Max. Metal coverage MM4Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") + + -> do + M5_density.ext_with_density(0.0 .. 0.25, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M5Fil.h", "Min. Metal coverage MM5Filler ratio for any 800 x 800 µm² chip area [%] = 25.0") + + -> do + M5_density.ext_with_density(0.75 .. 1.0, 'll', tile_size(800.0), tile_step(400.0)) + end.().output("M5Fil.k", "Max. Metal coverage MM5Filler ratio for any 800 x 800 µm² chip area [%] = 75.0") + + -> do + TM1_density.ext_with_density(0.0 .. 0.25, 'll') + end.().output("TM1.c", "Min. global TopMetal1 density [%] = 25.00") + + -> do + TM1_density.ext_with_density(0.7 .. 1.0, 'll') + end.().output("TM1.d", "Max. global TopMetal1 density [%] = 70.00") + + -> do + TM2_density.ext_with_density(0.0 .. 0.25, 'll') + end.().output("TM2.c", "Min. global TopMetal1 density [%] = 25.0") + + -> do + TM2_density.ext_with_density(0.7 .. 1.0, 'll') + end.().output("TM2.c1", "Max. global TopMetal1 density [%] = 70.0") + + -> do + LBE.ext_with_density(0.2 .. 1.0, 'll') + end.().output("LBE.i", "Max. global LBE density [%] = 20.0 %") + +end + +if conditional_enabled[:sanityRules] + + -> do + Activ_pin.ext_not(Activ) + end.().output("forbidden.a", "Activ enclosure of Activ_pin = 0.0") + + -> do + GatPoly_pin.ext_not(GatPoly) + end.().output("forbidden.b", "GatPoly enclosure of GatPoly_pin = 0.0") + + -> do + NWell_pin.ext_not(NWell) + end.().output("forbidden.c", "NWell enclosure of NWell_pin = 0.0") + + -> do + Metal1_pin.ext_not(Metal1) + end.().output("forbidden.d", "Metal1 enclosure of Metal1_pin = 0.0") + + -> do + Metal2_pin.ext_not(Metal2) + end.().output("forbidden.f.M1", "Metal2 enclosure of Metal2_pin = 0.0") + + -> do + Metal3_pin.ext_not(Metal3) + end.().output("forbidden.f.M2", "Metal3 enclosure of Metal3_pin = 0.0") + + -> do + Metal4_pin.ext_not(Metal4) + end.().output("forbidden.f.M3", "Metal4 enclosure of Metal4_pin = 0.0") + + -> do + Metal5_pin.ext_not(Metal5) + end.().output("forbidden.f.M4", "Metal5 enclosure of Metal5_pin = 0.0") + + -> do + TopMetal1_pin.ext_not(TopMetal1) + end.().output("forbidden.f.M5", "TopMetal1 enclosure of TopMetal1_pin = 0.0") + + -> do + TopMetal2_pin.ext_not(TopMetal2) + end.().output("forbidden.f.MT1", "TopMetal2 enclosure of TopMetal2_pin = 0.0") + + -> do + BiWind_org.dup + end.().output("forbidden.Biwind", "Biwind forbidden layer in 0.13um designs") + + -> do + PEmWind_org.dup + end.().output("forbidden.PEmWind", "PEmWind forbidden layer in 0.13um designs") + + -> do + BasPoly_org.dup + end.().output("forbidden.BasPoly", "BasPoly forbidden layer in 0.13um designs") + + -> do + DeepCo_org.dup + end.().output("forbidden.DeepCo", "DeepCo forbidden layer in 0.13um designs") + + -> do + PEmPoly_org.dup + end.().output("forbidden.PEmPoly", "PEmPoly forbidden layer in 0.13um designs") + + -> do + EmPoly_org.dup + end.().output("forbidden.EmPoly", "EmPoly forbidden layer in 0.13um designs") + + -> do + LDMOS_org.dup + end.().output("forbidden.LDMOS", "LDMOS forbidden layer in 0.13um designs") + + -> do + PBiWind_org.dup + end.().output("forbidden.PBiWind", "PBiWind forbidden layer in 0.13um designs") + + -> do + Flash_org.dup + end.().output("forbidden.Flash", "Flash forbidden layer in 0.13um designs") + + -> do + ColWind_org.dup + end.().output("forbidden.ColWind", "ColWind forbidden layer in 0.13um designs") + +end + +-> do + LBE.width(100000) +end.().output("LBE.a", "LBE.a: Min. width of LBE = 100.0") + +-> do + LBE.drc(width > 1500000) +end.().output("LBE.b", "LBE.b: Max. width of LBE = 1500.0") + +-> do + LBE.ext_area([[">", 250000.0*1000.0*1000.0]]) +end.().output("LBE.b1", "LBE.b1: Max allowed LBE area = 250000.0") + +-> do + LBE.space(100000) +end.().output("LBE.c", "LBE.c: Min. LBE space or notch = 100.0") + +-> (;lbe_in_seal) do + lbe_in_seal = LBE.merged(true, 0).inside(EdgeSeal.holes.merge) + lbe_in_seal.separation(EdgeSeal, 150000) +end.().output("LBE.d", "LBE.d: Min. space of LBE to inner edge of Edge Seal = 150.0") + +-> do + LBE.ext_ring.dup +end.().output("LBE.h", "LBE.h: No LBE ring allowed") + + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/klayout/sg13g2.lyp b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/klayout/sg13g2.lyp new file mode 100644 index 000000000..6c8cf9703 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/klayout/sg13g2.lyp @@ -0,0 +1,7016 @@ + + + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + 0 + Activ.drw + 1/0 + + + #00ff00 + #00ff00 + 0 + 0 + C1 + C1 + true + true + false + 1 + false + 0 + Activ.lbl + 1/1 + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + 0 + Activ.pin + 1/2 + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + 0 + Activ.net + 1/3 + + + #00ff00 + #00ff00 + 0 + 0 + C1 + C1 + false + true + false + 1 + false + 0 + Activ.bnd + 1/4 + + + #ffff00 + #ffff00 + 0 + 0 + I1 + C2 + true + true + false + 1 + false + 0 + Activ.lvs + 1/19 + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + 0 + Activ.msk + 1/20 + + + #00ff00 + #00ff00 + 0 + 0 + C3 + C0 + true + true + false + 1 + false + 0 + Activ.flr + 1/22 + + + #00ff00 + #00ff00 + 0 + 0 + I1 + C3 + true + true + false + 3 + false + 0 + Activ.nfl + 1/23 + + + #00cc66 + #00cc66 + 0 + 0 + C4 + C2 + false + true + false + 1 + false + 0 + Activ.opc + 1/26 + + + #00ff00 + #00ff00 + 0 + 0 + C5 + C2 + false + true + false + 1 + false + 0 + Activ.iop + 1/27 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + Activ.noq + 1/28 + + + #268c6b + #268c6b + 0 + 0 + C6 + C2 + false + true + false + 1 + false + 0 + BiWind.drw + 3/0 + + + #0000ff + #0000ff + 0 + 0 + I1 + C4 + false + true + false + 1 + false + 0 + BiWind.opc + 3/26 + + + #bf4026 + #bf4026 + 0 + 0 + C6 + C1 + true + true + false + 1 + false + 0 + GatPoly.drw + 5/0 + + + #bf4026 + #bf4026 + 0 + 0 + C1 + C1 + true + true + false + 1 + false + 0 + GatPoly.lbl + 5/1 + + + #bf4026 + #bf4026 + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + GatPoly.pin + 5/2 + + + #bf4026 + #bf4026 + 0 + 0 + C6 + C1 + false + true + false + 1 + false + 0 + GatPoly.net + 5/3 + + + #bf4026 + #bf4026 + 0 + 0 + C6 + C1 + false + true + false + 1 + false + 0 + GatPoly.bnd + 5/4 + + + #bf4026 + #bf4026 + 0 + 0 + C6 + C2 + true + true + false + 1 + false + 0 + GatPoly.flr + 5/22 + + + #bf4026 + #bf4026 + 0 + 0 + I1 + C3 + true + true + false + 3 + false + 0 + GatPoly.nfl + 5/23 + + + #ffff00 + #9900e6 + 0 + 0 + I1 + C5 + false + true + false + 1 + false + 0 + GatPoly.opc + 5/26 + + + #ffff00 + #ffff00 + 0 + 0 + C7 + C2 + false + true + false + 1 + false + 0 + GatPoly.iop + 5/27 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + GatPoly.noq + 5/28 + + + #00ffff + #00ffff + 0 + 0 + C8 + C1 + true + true + false + 1 + false + 0 + Cont.drw + 6/0 + + + #00ffff + #00ffff + 0 + 0 + C8 + C1 + false + true + false + 1 + false + 0 + Cont.net + 6/3 + + + #00ffff + #00ffff + 0 + 0 + C8 + C1 + false + true + false + 1 + false + 0 + Cont.bnd + 6/4 + + + #39bfff + #ffff00 + 0 + 0 + I1 + C5 + false + true + false + 1 + false + 0 + Cont.opc + 6/26 + + + #00cc66 + #00cc66 + 0 + 0 + C9 + C2 + false + true + false + 1 + false + 0 + nSD.drw + 7/0 + + + #00cc66 + #00cc66 + 0 + 0 + C10 + C2 + true + true + false + 1 + false + 0 + nSD.blk + 7/21 + + + #39bfff + #39bfff + 0 + 0 + C11 + C1 + true + true + false + 1 + false + 0 + Metal1.drw + 8/0 + + + #39bfff + #39bfff + 0 + 0 + C11 + C2 + false + true + false + 1 + false + 0 + Metal1.lbl + 8/1 + + + #39bfff + #39bfff + 0 + 0 + C11 + C2 + true + true + false + 1 + false + 0 + Metal1.pin + 8/2 + + + #39bfff + #39bfff + 0 + 0 + C11 + C2 + false + true + false + 1 + false + 0 + Metal1.net + 8/3 + + + #39bfff + #39bfff + 0 + 0 + I1 + C2 + false + true + false + 1 + false + 0 + Metal1.bnd + 8/4 + + + #39bfff + #39bfff + 0 + 0 + C11 + C1 + true + true + false + 1 + false + 0 + Metal1.msk + 8/20 + + + #39bfff + #39bfff + 0 + 0 + C11 + C0 + true + true + false + 1 + false + 0 + Metal1.flr + 8/22 + + + #39bfff + #39bfff + 0 + 0 + I1 + C3 + true + true + false + 3 + false + 0 + Metal1.nfl + 8/23 + + + #39bfff + #39bfff + 0 + 0 + I1 + C0 + true + true + false + 1 + false + 0 + Metal1.slt + 8/24 + + + #39bfff + #39bfff + 0 + 0 + C11 + C1 + true + true + false + 1 + false + 0 + Metal1.txt + 8/25 + + + #00ffff + #ffff00 + 0 + 0 + I1 + C6 + false + true + false + 1 + false + 0 + Metal1.opc + 8/26 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + Metal1.noq + 8/28 + + + #bf4026 + #bf4026 + 0 + 0 + C13 + C3 + true + true + false + 3 + false + 0 + Metal1.res + 8/29 + + + #39bfff + #39bfff + 0 + 0 + I1 + C4 + true + true + false + 1 + false + 0 + Metal1.iprb + 8/33 + + + #39bfff + #39bfff + 0 + 0 + I1 + C4 + true + true + false + 1 + false + 0 + Metal1.difp + 8/34 + + + #e61f0d + #e61f0d + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + Passiv.drw + 9/0 + + + #e61f0d + #e61f0d + 0 + 0 + C1 + C2 + false + true + false + 1 + false + 0 + Passiv.lbl + 9/1 + + + #e61f0d + #e61f0d + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + Passiv.pin + 9/2 + + + #e61f0d + #e61f0d + 0 + 0 + C1 + C2 + false + true + false + 1 + false + 0 + Passiv.net + 9/3 + + + #e61f0d + #e61f0d + 0 + 0 + C1 + C2 + false + true + false + 1 + false + 0 + Passiv.bnd + 9/4 + + + #e61f0d + #e61f0d + 0 + 0 + C1 + C7 + false + true + false + 3 + false + 0 + Passiv.pdl + 9/40 + + + #e61f0d + #e61f0d + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + Passiv.sbp + 9/36 + + + #e61f0d + #e61f0d + 0 + 0 + C1 + C2 + true + true + false + 1 + false + 0 + Passiv.pil + 9/35 + + + #ccccd9 + #ccccd9 + 0 + 0 + C14 + C2 + true + true + false + 1 + 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.........*...... + ........*....... + .......*........ + ......*......... + .....*.......... + ....*........... + ...*............ + ..*............. + .*.............. + *............... + + 11 + m1 + + + + *.....*.....*... + .....*.....*.... + ....*.....*..... + ...*.....*.....* + ..*.....*.....*. + .*.....*.....*.. + *.....*.....*... + .....*.....*.... + ....*.....*..... + ...*.....*.....* + ..*.....*.....*. + .*.....*.....*.. + *.....*.....*... + .....*.....*.... + ....*.....*..... + ...*.....*.....* + + 12 + M1stp + + + + *..*..*..*..*..* + ..*..*..*..*..*. + .*..*..*..*..*.. + *..*..*..*..*..* + ..*..*..*..*..*. + .*..*..*..*..*.. + *..*..*..*..*..* + ..*..*..*..*..*. + .*..*..*..*..*.. + *..*..*..*..*..* + ..*..*..*..*..*. + .*..*..*..*..*.. + *..*..*..*..*..* + ..*..*..*..*..*. + .*..*..*..*..*.. + *..*..*..*..*..* + + 13 + stipple16 + + + + ...*............ + ..*............. + .*.............. + *............... + ...............* + ..............*. + .............*.. + ............*... + ...........*.... + ..........*..... + .........*...... + ........*....... + .......*........ + ......*......... + .....*.......... + ....*........... + + 14 + m2 + + + + .....*.....*.... + ....*.....*..... + ...*.....*.....* + ..*.....*.....*. + .*.....*.....*.. + *.....*.....*... + .....*.....*.... + ....*.....*..... + ...*.....*.....* + ..*.....*.....*. + .*.....*.....*.. + *.....*.....*... + .....*.....*.... + ....*.....*..... + ...*.....*.....* + ..*.....*.....*. + + 15 + Polystp + + + + ................ + *...*...*...*... + ................ + ..*...*...*...*. + ................ + *...*...*...*... + ................ + ..*...*...*...*. + ................ + *...*...*...*... + ................ + ..*...*...*...*. + ................ + *...*...*...*... + ................ + ..*...*...*...*. + + 16 + stipple15 + + + + ................ + ................ + ..*.*.*......... + ................ + ...*.*.*........ + ................ + ................ + ..........*.*.*. + ................ + ...........*.*.* + *.*.*........... + ................ + .*.*.*.......... + .........*.*.*.. + ................ + ..........*.*.*. + + 17 + stipple39 + + + + *............... + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + + 18 + dot1 + + + + ....*........... + ...*............ + ..*............. + .*.............. + *............... + ...............* + ..............*. + .............*.. + ............*... + ...........*.... + ..........*..... + .........*...... + ........*....... + .......*........ + ......*......... + .....*.......... + + 19 + v1 + + + + ....*........... + .....*.......... + ......*......... + .......*........ + ........*....... + .........*...... + ..........*..... + ...........*.... + ............*... + .............*.. + ..............*. + ...............* + *............... + .*.............. + ..*............. + ...*............ + + 20 + tm1 + + + + ................ + .............*.. + ..*............. + ........*....... + ................ + ................ + ................ + ....*........... + ................ + ............*... + ................ + ................ + ...*....*....... + ................ + ..............*. + ................ + + 21 + stipple12 + + + + .*.............. + ..*............. + ...*............ + ....*........... + .....*.......... + ......*......... + .......*........ + ........*....... + .........*...... + ..........*..... + ...........*.... + ............*... + .............*.. + ..............*. + ...............* + *............... + + 22 + v2 + + + + *............... + .*.............. + ..*............. + ...*............ + ....*........... + .....*.......... + ......*......... + .......*........ + ........*....... + .........*...... + ..........*..... + ...........*.... + ............*... + .............*.. + ..............*. + ...............* + + 23 + m3 + + + + ..*.....*.....*. + .*.....*.....*.. + *.....*.....*... + .....*.....*.... + ....*.....*..... + ...*.....*.....* + ..*.....*.....*. + .*.....*.....*.. + *.....*.....*... + .....*.....*.... + ....*.....*..... + ...*.....*.....* + ..*.....*.....*. + .*.....*.....*.. + *.....*.....*... + .....*.....*.... + + 24 + M3stp + + + + **......**...... + ..*.......*..... + ...**......**... + .....*.......*.. + ......**......** + *.......*....... + .**......**..... + ...*.......*.... + ....**......**.. + ......*.......*. + *......**......* + .*.......*...... + ..**......**.... + ....*.......*... + .....**......**. + .......*.......* + + 25 + hZigZag + + + + ................ + ................ + .....*****...... + ....*.....*..... + ...*.......*.... + ..*.........*... + .*...........*.. + .*...........*.. + .*...........*.. + .*...........*.. + .*...........*.. + ..*.........*... + ...*.......*.... + ....*.....*..... + .....*****...... + ................ + + 26 + stipple113 + + + + ...*...*.*...*.. + ..*..***.***..*. + .*...*.....*...* + *..***..*..***.. + ...*...*.*...*.. + .***..*...*..*** + .*...*.....*...* + **..*..***..*..* + ...*...*.*...*.. + ..*..***.***..*. + .*...*.....*...* + *..***..*..***.. + ...*...*.*...*.. + .***..*...*..*** + .*...*.....*...* + **..*..***..*..* + + 27 + stipple105 + + + + ................ + ................ + ................ + ...***.......... + ...***.......... + ...***.......... + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + ................ + + 28 + dot2 + + + + ................ + ...........*.... + ................ + ...*............ + ................ + ................ + ................ + .......*...*.... + ................ + ................ + ................ + ................ + ..*..........*.. + ................ + .....*.......... + ................ + + 29 + stipple13 + + + + .*...*...*...*.. + ................ + ...*...*...*...* + ................ + .*...*...*...*.. + ................ + ...*...*...*...* + ................ + .*...*...*...*.. + ................ + ...*...*...*...* + ................ + .*...*...*...*.. + ................ + ...*...*...*...* + ................ + + 30 + dots10 + + + + .............*.. + ..............*. + ...............* + *............... + .*.............. + ..*............. + ...*............ + ....*........... + .....*.......... + ......*......... + .......*........ + ........*....... + .........*...... + ..........*..... + ...........*.... + ............*... + + 31 + v3 + + + + ............*... + .............*.. + ..............*. + ...............* + *............... + .*.............. + ..*............. + ...*............ + ....*........... + .....*.......... + ......*......... + .......*........ + ........*....... + .........*...... + ..........*..... + ...........*.... + + 32 + m4 + + + + .......*........ + ......*......... + .....*.......... + ....*........... + ...*............ + ..*............. + .*.............. + *............... + ...............* + ..............*. + .............*.. + ............*... + ...........*.... + ..........*..... + .........*...... + ........*....... + + 33 + m5 + + + + ......*......... + .....*.......... + ....*........... + ...*............ + ..*............. + .*.............. + *............... + ...............* + ..............*. + .............*.. + ............*... + ...........*.... + ..........*..... + .........*...... + ........*....... + .......*........ + + 34 + v4 + + + + ...........*.... + ..........*..... + .........*...... + ........*....... + .......*........ + ......*......... + .....*.......... + ....*........... + ...*............ + ..*............. + .*.............. + *............... + ...............* + ..............*. + .............*.. + ............*... + + 35 + m6 + + + + ....*.......*... + .....*.......*.. + ......*.......*. + .......*.......* + *.......*....... + .*.......*...... + ..*.......*..... + ...*.......*.... + ....*.......*... + .....*.......*.. + ......*.......*. + .......*.......* + *.......*....... + .*.......*...... + ..*.......*..... + ...*.......*.... + + 36 + stipple14 + + + + .......*.......* + ......*.......*. + .....*.......*.. + ....*.......*... + ...*.......*.... + ..*.......*..... + .*.......*...... + *.......*....... + .......*.......* + ......*.......*. + .....*.......*.. + ....*.......*... + ...*.......*.... + ..*.......*..... + .*.......*...... + *.......*....... + + 37 + metal2S + + + + ............*... + .............*.. + ..............*. + ...............* + *............... + .*.............. + ..*............. + ...*............ + ....*........... + .....*.......... + ......*......... + .......*........ + ........*....... + .........*...... + ..........*..... + ...........*.... + + 38 + tnal + + + + *...*...*...*... + ................ + ..*...*...*...*. + ................ + *...*...*...*... + ................ + ..*...*...*...*. + ................ + *...*...*...*... + ................ + ..*...*...*...*. + ................ + *...*...*...*... + ................ + ..*...*...*...*. + ................ + + 39 + stipple103 + + + + ......*...*..... + ................ + ..*............. + .............*.. + ................ + ................ + *..............* + ................ + .......*........ + ................ + *..............* + ................ + ................ + ...*.........*.. + ................ + ......*...*..... + + 40 + stipple45 + + + + ................ + ................ + .*........*..... + ................ + ................ + .*..*.....*..*.. + ................ + ........*....... + ................ + ................ + ........*..*.... + ....*........... + ................ + ................ + ....*..*........ + ................ + + 41 + stipple46 + + + + ................ + .............*.. + ................ + ..*....*........ + ................ + ..........*...*. + ................ + ......*......... + ................ + .*.............. + ............*... + ................ + ....*........... + ........*....... + ................ + *..............* + + 42 + stipple47 + + + + ................ + ................ + ..............*. + ................ + ................ + ................ + ..*............. + ................ + ........*....... + .............*.. + ................ + ................ + ................ + .*.............. + ................ + ................ + + 43 + stipple48 + + + + .............*.. + ..*....*........ + ................ + ................ + ......*.....*... + ..*............. + ................ + ........*....... + *............... + ............*... + ..*............. + ......*......... + ................ + .........*...... + ....*.........*. + ..*............. + + 44 + stipple49 + + + + *.*.*.*.*.*.*.*. + *.*.*.*.*.*.*.*. + *.*.*.*.*.*.*.*. + *.*.*.*.*.*.*.*. + .*.*.*.*.*.*.*.* + .*.*.*.*.*.*.*.* + .*.*.*.*.*.*.*.* + .*.*.*.*.*.*.*.* + *.*.*.*.*.*.*.*. + *.*.*.*.*.*.*.*. + *.*.*.*.*.*.*.*. + *.*.*.*.*.*.*.*. + .*.*.*.*.*.*.*.* + .*.*.*.*.*.*.*.* + .*.*.*.*.*.*.*.* + .*.*.*.*.*.*.*.* + + 45 + stipple41 + + + + ...*............ + ....*........... + .....*.......... + ......*......... + .......*........ + ........*....... + .........*...... + ..........*..... + ...........*.... + ............*... + .............*.. + ..............*. + ...............* + *............... + .*.............. + ..*............. + + 46 + tv1 + + + + ................ + ....*........... + ...*.*.......... + ..*...*......... + .*.....*........ + *********....... + ................ + ................ + ................ + ...........*.... + ..........*.*... + .........*...*.. + ........*.....*. + .......********* + ................ + ................ + + 47 + triangle + + + + .......*........ + ........*....... + .........*...... + ..........*..... + ...........*.... + ............*... + .............*.. + ..............*. + ...............* + *............... + .*.............. + ..*............. + ...*............ + ....*........... + .....*.......... + ......*......... + + 48 + tv2 + + + + ......*......... + .......*........ + ........*....... + .........*...... + ..........*..... + ...........*.... + ............*... + .............*.. + ..............*. + ...............* + *............... + .*.............. + ..*............. + ...*............ + ....*........... + .....*.......... + + 49 + tm2 + + + + ..........*..... + ................ + ..*............. + .....*....*...*. + ...........*.... + .*.............. + ................ + .....*...*...... + ...........*..*. + ..*............. + .*......*....... + ......*........* + .....*.......... + ..*.........*... + ....*........... + ........*....... + + 50 + stipple37 + + + + ................ + ................ + ...*.......*.... + ...*.......*.... + ...*.......*.... + ...*.......*.... + ...*.......*.... + ...*.......*.... + ...*...*...*.... + ...*...*...*.... + .......*........ + .......*........ + .......*........ + .......*........ + .......*........ + .......*........ + + 51 + stipple63 + + + + ................ + ............*... + ..*.....*....... + .....*.......*.. + ................ + ...*.......*...* + ................ + .*........*..*.. + .......*........ + ...*...........* + .*.............. + .....*..*....... + ..*..........*.. + .......*........ + ...*....*...*... + ................ + + 52 + stipple42 + + + + ...**......**... + ..*..*....*..*.. + .*....*..*....*. + *......**......* + *......**......* + .*....*..*....*. + ..*..*....*..*.. + ...**......**... + ...**......**... + ..*..*....*..*.. + .*....*..*....*. + *......**......* + *......**......* + .*....*..*....*. + ..*..*....*..*.. + ...**......**... + + 53 + stipple11 + + + + ...**......**... + ..*..*....*..*.. + .*....*..*....*. + *......**......* + *......**......* + .*....*..*....*. + ..*..*....*..*.. + ...**......**... + ...**......**... + ..*..*....*..*.. + .*....*..*....*. + *......**......* + *......**......* + .*....*..*....*. + ..*..*....*..*.. + ...**......**... + + 54 + stipple57 + + + ****.. + 0 + dashed + + + * + 1 + lineStyle0 + + + *** + 2 + solid + + + *.. + 3 + tdots + + + *.. + 4 + dots + + + **.. + 5 + shortDash + + + ****..**.. + 6 + doubleDash + + + ****........ + 7 + tdots2 + + + *** + 8 + thickLine + + + *** + 9 + mLine + + + **..**..**..**. + 10 + lineStyle1 + + + ***..*.. + 11 + dashDot + + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/klayout/sg13g2.lyt b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/klayout/sg13g2.lyt new file mode 100644 index 000000000..d73e740b9 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/libs.tech/klayout/sg13g2.lyt @@ -0,0 +1,197 @@ + + + + sg13g2 + IHP SiGe 130nm technology + + 0.001 + $(appdata_path)/tech + $(appdata_path)/tech + sg13g2.lyp + true + + + 1 + true + true + + + true + layer_map() + true + true + + + true + layer_map() + 0.001 + true + #1 + true + #1 + false + #1 + true + OUTLINE + true + PLACEMENT_BLK + true + REGIONS + true + + 0 + true + .PIN + 2 + true + .PIN + 2 + true + .FILL + 5 + true + .OBS + 3 + true + .BLK + 4 + true + .LABEL + 1 + true + .LABEL + 1 + true + + 0 + true + + 0 + VIA_ + true + default + false + + merged.lef + + + false + true + true + 64 + 0 + 1 + 0 + DATA + 0 + 0 + BORDER + layer_map() + true + + + 0.001 + 1 + 100 + 100 + 0 + 0 + 0 + false + false + false + true + layer_map() + + + 0 + 0.001 + layer_map() + true + false + + + 1 + 0.001 + layer_map() + true + false + true + + + + + + GDS2 + + true + false + false + false + false + false + 8000 + 32000 + LIB + + + 2 + true + true + 1 + * + false + + + 0 + + + false + false + + + 0 + + true + + + + GatPoly,Cont,Metal1 + Diff,Cont,Metal1 + Metal1,Via1,Metal2 + Metal2,Via2,Metal3 + Metal3,Via3,Metal4 + Metal4,Via4,Metal5 + Metal5,TopVia1,TopMetal1 + TopMetal1,TopVia2,TopMetal2 + SalBlock='28/0' + Activ='1/0-Salblock' + GatPoly='5/0-SalBlock' + Diff='Activ-GatPoly' + Cont='6/0' + Metal1='8/0-8/29' + Via1='19/0' + Metal2='10/0-10/29' + Via2='29/0' + Metal3='30/0-30/29' + Via3='49/0' + Metal4='50/0-50/29' + Via4='66/0' + Metal5='67/0-67/29' + TopVia1='125/0' + TopMetal1='126/0-126/29' + TopVia2='133/0' + TopMetal2='134/0-134/29' + + diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/meson.build b/pdks/symbolic/nsxlib2/sg13g2_nsx2/meson.build new file mode 100644 index 000000000..b1d9b0575 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/meson.build @@ -0,0 +1,42 @@ + +project( + 'pdk_sg13g2_nsx2', + version: '0.1.0', + meson_version: '>= 1.2.0', + default_options: ['warning_level=3'] +) + +python = import('python') +py = python.find_installation('python3') +py_deps = py.dependency() + +pdks_dir = py.get_install_dir() / 'pdks' / 'sg13g2_nsx2' + +py_files = [ + 'libs.tech/coriolis/sg13g2_nsx2/__init__.py', + 'libs.tech/coriolis/sg13g2_nsx2/nsxlib2.py', + 'libs.tech/coriolis/sg13g2_nsx2/Sg13g2nsx2Setup.py', + 'libs.tech/coriolis/sg13g2_nsx2/techno_symb.py', + 'libs.tech/coriolis/sg13g2_nsx2/techno.py', +] + +data_files = [ + 'libs.tech/coriolis/sg13g2_nsx2/mos_tt.lib', + 'libs.tech/coriolis/sg13g2_nsx2/nsxlib2.lib', + 'libs.tech/coriolis/sg13g2_nsx2/spimodel.cfg', + 'libs.tech/coriolis/sg13g2_nsx2/symbolic.dreal', + 'libs.tech/coriolis/sg13g2_nsx2/symbolic.graal', + 'libs.tech/coriolis/sg13g2_nsx2/sg13g2_nsx2.rds', +] + +klayout_files = [ + 'libs.tech/klayout/sg13g2.lydrc', + 'libs.tech/klayout/sg13g2.lyp', + 'libs.tech/klayout/sg13g2.lyt', +] + +py.install_sources( files(py_files) , subdir: 'pdks/sg13g2_nsx2' ) +py.install_sources( files(data_files) , subdir: 'pdks/sg13g2_nsx2' ) +py.install_sources( files(klayout_files) , subdir: 'pdks/sg13g2_nsx2' ) + +install_subdir( 'libs.tech/coriolis/sg13g2_nsx2/spi' , install_dir: pdks_dir / 'sg13g2_lsx' ) diff --git a/pdks/symbolic/nsxlib2/sg13g2_nsx2/pyproject.toml b/pdks/symbolic/nsxlib2/sg13g2_nsx2/pyproject.toml new file mode 100644 index 000000000..cdee63834 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sg13g2_nsx2/pyproject.toml @@ -0,0 +1,25 @@ +[project] +name = "pdk_sg13g2_nsx2" +version = "0.1.0" +description = "IHP sg13g2 nsxlib2 PDK for Coriolis EDA" +authors = [ { name = "Coriolis EDA Contributers" } ] +requires-python = ">= 3.8" + +[build-system] +requires = [ + "meson", + "meson-python", + "ninja", + "setuptools", + "cibuildwheel", + "build", + "pdm-backend" +] +build-backend = "mesonpy" + +[tool.meson] +build-dir = "build" + +[tool.cibuildwheel] +build = "cp310-*" +skip = ["cp36-*", "cp37-*", "pp*"] diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/__init__.py b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/Sky130nsx2Setup.py b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/Sky130nsx2Setup.py new file mode 100644 index 000000000..9f3db00a7 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/Sky130nsx2Setup.py @@ -0,0 +1,96 @@ + +import sys +import os +import socket +from pathlib import Path +from coriolis.designflow.task import ShellEnv + + +__all__ = [ 'Where', 'setupSky130_nsx2' ] + + +class Where ( object ): + + coriolisTop = None + allianceTop = None + cellsTop = None + checkToolkit = None + + def __init__ ( self, checkToolkit=None ): + if 'CORIOLIS_TOP' in os.environ: Where.coriolisTop = Path( os.environ['CORIOLIS_TOP'] ) + if 'ALLIANCE_TOP' in os.environ: Where.allianceTop = Path( os.environ['ALLIANCE_TOP'] ) + if 'CELLS_TOP' in os.environ: Where.cellsTop = Path( os.environ['CELLS_TOP'] ) + if Where.coriolisTop and not Where.allianceTop: Where.allianceTop = Where.coriolisTop + #print( Where.coriolisTop, Where.allianceTop ) + if not Where.coriolisTop: + print( 'technos.Where.__init__(): Unable to locate Coriolis top.' ) + if checkToolkit is None: + checkToolkit = Path.home() / 'coriolis-2.x' / 'src' / 'alliance-check-toolkit' + else: + if isinstance(checkToolkit,str): + checkToolkit = Path( checkToolkit ) + if not Where.cellsTop: + Where.cellsTop = checkToolkit / 'cells' + Where.checkToolkit = checkToolkit + if not Where.cellsTop and Where.allianceTop: + Where.cellsTop = Where.allianceTop / 'cells' + ShellEnv.ALLIANCE_TOP = Where.allianceTop.as_posix() + + def __repr__ ( self ): + if not Where.coriolisTop: + return '' + return ''.format( Where.coriolisTop.as_posix() ) + +def setupSky130_nsx2 ( checkToolkit=None ): + Where( checkToolkit ) + ShellEnv().export() + + pdkDir = Where.checkToolkit / 'dks' / 'sky130_nsx2' / 'libs.tech' + coriolisTechDir = pdkDir / 'coriolis' + if not pdkDir.is_dir(): + print( '[ERROR] technos.setupSky130_nsx2(): PDK directory do *not* exists:' ) + print( ' "{}"'.format(techDir.as_posix()) ) + sys.path.append( coriolisTechDir.as_posix() ) + + cellsTop = Where.checkToolkit / 'cells' + liberty = coriolisTechDir / 'sky130_nsx2' / 'nsxlib2.lib' + print(liberty) + kdrcRules = pdkDir / 'klayout' / 'drc_sky130.lydrc' + + from coriolis import Cfg + from coriolis import Viewer + from coriolis import CRL + from coriolis.helpers import overlay, l, u, n + from coriolis.designflow.yosys import Yosys + from coriolis.designflow.klayout import DRC + from sky130_nsx2 import techno, nsxlib2 + techno.setup( coriolisTechDir ) + nsxlib2.setup( cellsTop ) + + with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.misc.minTraceLevel = 1900 + cfg.misc.maxTraceLevel = 3000 + cfg.katana.eventsLimit = 1000000 + cfg.katana.termSatReservedLocal = 6 + cfg.katana.termSatThreshold = 9 + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + Yosys.setLiberty( liberty ) + DRC.setDrcRules( kdrcRules ) + ShellEnv.CHECK_TOOLKIT = Where.checkToolkit.as_posix() + + path = None + for pathVar in [ 'PATH', 'path' ]: + if pathVar in os.environ: + path = os.environ[ pathVar ] + os.environ[ pathVar ] = path + ':' + (Where.allianceTop / 'bin').as_posix() + break + + diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/__init__.py b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/__init__.py new file mode 100644 index 000000000..b87e091fc --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/__init__.py @@ -0,0 +1,5 @@ + +import os +from pathlib import Path + +path = Path( os.path.dirname(os.path.abspath(__file__)) ) diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/nsxlib2.lib b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/nsxlib2.lib new file mode 100644 index 000000000..1a15097a3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/nsxlib2.lib @@ -0,0 +1,19966 @@ +/************************************************************************/ +/* */ +/* Avertec Release v3.4p5 (64 bits on Linux 4.4.0-26100-Microsoft) */ +/* argv: /home/nshimizu/lip6/alliance-check-toolkit/bin/buildLib.tcl /opt/alliance/etc/spimodel.cfg hspice nsxlib2 -SpiceModel sky130_fd_pr__nfet_01v8__mismatch.corner.spice sky130_fd_pr__nfet_01v8__tt.pm3.spice sky130_fd_pr__nfet_01v8__tt.corner.spice sky130_fd_pr__pfet_01v8__mismatch.corner.spice sky130_fd_pr__pfet_01v8__tt.pm3.spice sky130_fd_pr__pfet_01v8__tt.corner.spice parameters/lod.spice */ +/* */ +/* User: nshimizu */ +/* Generation date Fri Dec 20 14:55:45 2024 */ +/* */ +/* liberty data flow `nsxlib2.lib` */ +/* */ +/************************************************************************/ + + + +library (nsxlib2.lib) { + + technology (cmos) ; + date : "Fri Dec 20 14:55:45 2024" ; + delay_model : table_lookup ; + nom_voltage : 5.00 ; + nom_temperature : 70.0 ; + nom_process : 1.0 ; + slew_derate_from_library : 1.0 ; + default_fanout_load : 1000.0 ; + default_inout_pin_cap : 1000.0 ; + default_input_pin_cap : 1000.0 ; + default_output_pin_cap : 0.0 ; + voltage_unit : "1V" ; + time_unit : "1ps" ; + capacitive_load_unit (1,ff) ; + pulling_resistance_unit : "1ohm" ; + current_unit : "1mA" ; + leakage_power_unit : "1uW" ; + default_cell_leakage_power : 0.0 ; + input_threshold_pct_rise : 50.0 ; + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_rise : 50.0 ; + output_threshold_pct_fall : 50.0 ; + slew_lower_threshold_pct_fall : 20.0 ; + slew_upper_threshold_pct_fall : 80.0 ; + slew_lower_threshold_pct_rise : 20.0 ; + slew_upper_threshold_pct_rise : 80.0 ; + + lu_table_template (inslew_load_5x5__54) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.04, 2.08, 4.16, 8.32, 16.64"); + } + lu_table_template (inslew_load_5x5__53) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.94, 3.88, 7.76, 15.52, 31.05"); + } + lu_table_template (inslew_load_5x5__52) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.97, 3.93, 7.86, 15.72, 31.44"); + } + lu_table_template (inslew_load_5x5__51) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.13, 4.25, 8.51, 17.01, 34.02"); + } + lu_table_template (inslew_ckslew_5x5__0) { + variable_1 : constrained_pin_transition; + variable_2 : related_pin_transition; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + lu_table_template (inslew_5__0) { + variable_1 : input_net_transition; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + lu_table_template (inslew_load_5x5__50) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.76, 1.52, 3.04, 6.08, 12.15"); + } + lu_table_template (inslew_load_5x5__49) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.07, 2.15, 4.30, 8.59, 17.18"); + } + lu_table_template (inslew_load_5x5__48) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.72, 1.43, 2.87, 5.73, 11.47"); + } + lu_table_template (inslew_load_5x5__47) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.11, 2.23, 4.46, 8.92, 17.84"); + } + lu_table_template (inslew_load_5x5__46) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.62, 1.24, 2.47, 4.95, 9.89"); + } + lu_table_template (inslew_load_5x5__45) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.06, 2.12, 4.23, 8.47, 16.93"); + } + lu_table_template (inslew_load_5x5__44) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.65, 1.31, 2.61, 5.23, 10.46"); + } + lu_table_template (inslew_load_5x5__43) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.65, 1.30, 2.60, 5.20, 10.40"); + } + lu_table_template (inslew_load_5x5__42) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.04, 2.08, 4.16, 8.32, 16.64"); + } + lu_table_template (inslew_load_5x5__41) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.07, 2.13, 4.26, 8.53, 17.06"); + } + lu_table_template (inslew_load_5x5__40) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.13, 2.26, 4.53, 9.05, 18.10"); + } + lu_table_template (inslew_load_5x5__39) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.08, 2.16, 4.33, 8.65, 17.30"); + } + lu_table_template (inslew_load_5x5__38) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.17, 2.34, 4.69, 9.38, 18.75"); + } + lu_table_template (inslew_load_5x5__37) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.12, 2.23, 4.47, 8.93, 17.86"); + } + lu_table_template (inslew_load_5x5__36) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.52, 3.04, 6.08, 12.16, 24.31"); + } + lu_table_template (inslew_load_5x5__35) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.03, 2.05, 4.11, 8.21, 16.42"); + } + lu_table_template (inslew_load_5x5__34) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.32, 2.64, 5.29, 10.58, 21.15"); + } + lu_table_template (inslew_load_5x5__33) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.04, 2.08, 4.15, 8.30, 16.61"); + } + lu_table_template (inslew_load_5x5__32) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.05, 2.11, 4.21, 8.43, 16.86"); + } + lu_table_template (inslew_load_5x5__31) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.04, 2.08, 4.16, 8.32, 16.63"); + } + lu_table_template (inslew_load_5x5__30) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.03, 2.06, 4.12, 8.24, 16.47"); + } + lu_table_template (inslew_load_5x5__29) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.01, 2.01, 4.02, 8.05, 16.09"); + } + lu_table_template (inslew_load_5x5__28) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.00, 1.99, 3.98, 7.97, 15.94"); + } + lu_table_template (inslew_load_5x5__27) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.85, 1.70, 3.40, 6.81, 13.62"); + } + lu_table_template (inslew_load_5x5__26) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.99, 1.97, 3.95, 7.89, 15.78"); + } + lu_table_template (inslew_load_5x5__25) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.54, 3.08, 6.17, 12.34"); + } + lu_table_template (inslew_load_5x5__24) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.13, 2.25, 4.51, 9.02, 18.04"); + } + lu_table_template (inslew_load_5x5__23) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.01, 2.02, 4.04, 8.07, 16.14"); + } + lu_table_template (inslew_load_5x5__22) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.10, 2.20, 4.40, 8.81, 17.61"); + } + lu_table_template (inslew_load_5x5__21) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.05, 2.10, 4.20, 8.40, 16.81"); + } + lu_table_template (inslew_load_5x5__20) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.09, 2.19, 4.38, 8.75, 17.51"); + } + lu_table_template (inslew_load_5x5__19) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.06, 2.12, 4.24, 8.47, 16.94"); + } + lu_table_template (inslew_load_5x5__18) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.09, 2.19, 4.38, 8.75, 17.51"); + } + lu_table_template (inslew_load_5x5__17) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.24, 2.48, 4.95, 9.90, 19.80"); + } + lu_table_template (inslew_load_5x5__16) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.98, 1.96, 3.92, 7.85, 15.70"); + } + lu_table_template (inslew_load_5x5__15) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.03, 2.06, 4.13, 8.26, 16.51"); + } + lu_table_template (inslew_load_5x5__14) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.53, 3.07, 6.13, 12.27"); + } + lu_table_template (inslew_load_5x5__13) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.11, 2.21, 4.42, 8.85, 17.69"); + } + lu_table_template (inslew_load_5x5__12) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.76, 1.52, 3.03, 6.07, 12.13"); + } + lu_table_template (inslew_load_5x5__11) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.71, 1.41, 2.83, 5.66, 11.31"); + } + lu_table_template (inslew_load_5x5__10) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.02, 4.03, 8.06, 16.12, 32.25"); + } + lu_table_template (inslew_load_5x5__9) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.01, 2.03, 4.05, 8.11, 16.22"); + } + lu_table_template (inslew_load_5x5__8) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.02, 2.05, 4.09, 8.18, 16.36"); + } + lu_table_template (inslew_load_5x5__7) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.61, 1.23, 2.45, 4.91, 9.81"); + } + lu_table_template (inslew_load_5x5__6) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.06, 2.12, 4.23, 8.47, 16.94"); + } + lu_table_template (inslew_load_5x5__5) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.87, 1.74, 3.49, 6.97, 13.94"); + } + lu_table_template (inslew_load_5x5__4) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.71, 1.42, 2.84, 5.68, 11.36"); + } + lu_table_template (inslew_load_5x5__3) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.04, 2.09, 4.17, 8.35, 16.70"); + } + lu_table_template (inslew_load_5x5__2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.75, 1.51, 3.02, 6.03, 12.07"); + } + lu_table_template (inslew_load_5x5__1) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.94, 1.87, 3.75, 7.50, 15.00"); + } + lu_table_template (inslew_load_5x5__0) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.64, 1.29, 2.57, 5.15, 10.29"); + } + power_lut_template (energy_inslew_load_5x5__54) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.04, 2.08, 4.16, 8.32, 16.64"); + } + power_lut_template (energy_inslew_load_5x5__53) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.94, 3.88, 7.76, 15.52, 31.05"); + } + power_lut_template (energy_inslew_load_5x5__52) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.97, 3.93, 7.86, 15.72, 31.44"); + } + power_lut_template (energy_inslew_load_5x5__51) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.13, 4.25, 8.51, 17.01, 34.02"); + } + power_lut_template (energy_inslew_5__0) { + variable_1 : input_transition_time; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + power_lut_template (energy_inslew_load_5x5__50) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.76, 1.52, 3.04, 6.08, 12.15"); + } + power_lut_template (energy_inslew_load_5x5__49) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.07, 2.15, 4.30, 8.59, 17.18"); + } + power_lut_template (energy_inslew_load_5x5__48) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.72, 1.43, 2.87, 5.73, 11.47"); + } + power_lut_template (energy_inslew_load_5x5__47) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.11, 2.23, 4.46, 8.92, 17.84"); + } + power_lut_template (energy_inslew_load_5x5__46) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.62, 1.24, 2.47, 4.95, 9.89"); + } + power_lut_template (energy_inslew_load_5x5__45) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.06, 2.12, 4.23, 8.47, 16.93"); + } + power_lut_template (energy_inslew_load_5x5__44) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.65, 1.31, 2.61, 5.23, 10.46"); + } + power_lut_template (energy_inslew_load_5x5__43) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.65, 1.30, 2.60, 5.20, 10.40"); + } + power_lut_template (energy_inslew_load_5x5__42) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.04, 2.08, 4.16, 8.32, 16.64"); + } + power_lut_template (energy_inslew_load_5x5__41) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.07, 2.13, 4.26, 8.53, 17.06"); + } + power_lut_template (energy_inslew_load_5x5__40) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.13, 2.26, 4.53, 9.05, 18.10"); + } + power_lut_template (energy_inslew_load_5x5__39) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.08, 2.16, 4.33, 8.65, 17.30"); + } + power_lut_template (energy_inslew_load_5x5__38) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.17, 2.34, 4.69, 9.38, 18.75"); + } + power_lut_template (energy_inslew_load_5x5__37) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.12, 2.23, 4.47, 8.93, 17.86"); + } + power_lut_template (energy_inslew_load_5x5__36) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.52, 3.04, 6.08, 12.16, 24.31"); + } + power_lut_template (energy_inslew_load_5x5__35) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.03, 2.05, 4.11, 8.21, 16.42"); + } + power_lut_template (energy_inslew_load_5x5__34) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.32, 2.64, 5.29, 10.58, 21.15"); + } + power_lut_template (energy_inslew_load_5x5__33) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.04, 2.08, 4.15, 8.30, 16.61"); + } + power_lut_template (energy_inslew_load_5x5__32) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.05, 2.11, 4.21, 8.43, 16.86"); + } + power_lut_template (energy_inslew_load_5x5__31) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.04, 2.08, 4.16, 8.32, 16.63"); + } + power_lut_template (energy_inslew_load_5x5__30) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.03, 2.06, 4.12, 8.24, 16.47"); + } + power_lut_template (energy_inslew_load_5x5__29) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.01, 2.01, 4.02, 8.05, 16.09"); + } + power_lut_template (energy_inslew_load_5x5__28) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.00, 1.99, 3.98, 7.97, 15.94"); + } + power_lut_template (energy_inslew_load_5x5__27) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.85, 1.70, 3.40, 6.81, 13.62"); + } + power_lut_template (energy_inslew_load_5x5__26) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.99, 1.97, 3.95, 7.89, 15.78"); + } + power_lut_template (energy_inslew_load_5x5__25) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.54, 3.08, 6.17, 12.34"); + } + power_lut_template (energy_inslew_load_5x5__24) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.13, 2.25, 4.51, 9.02, 18.04"); + } + power_lut_template (energy_inslew_load_5x5__23) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.01, 2.02, 4.04, 8.07, 16.14"); + } + power_lut_template (energy_inslew_load_5x5__22) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.10, 2.20, 4.40, 8.81, 17.61"); + } + power_lut_template (energy_inslew_load_5x5__21) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.05, 2.10, 4.20, 8.40, 16.81"); + } + power_lut_template (energy_inslew_load_5x5__20) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.09, 2.19, 4.38, 8.75, 17.51"); + } + power_lut_template (energy_inslew_load_5x5__19) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.06, 2.12, 4.24, 8.47, 16.94"); + } + power_lut_template (energy_inslew_load_5x5__18) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.09, 2.19, 4.38, 8.75, 17.51"); + } + power_lut_template (energy_inslew_load_5x5__17) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.24, 2.48, 4.95, 9.90, 19.80"); + } + power_lut_template (energy_inslew_load_5x5__16) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.98, 1.96, 3.92, 7.85, 15.70"); + } + power_lut_template (energy_inslew_load_5x5__15) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.03, 2.06, 4.13, 8.26, 16.51"); + } + power_lut_template (energy_inslew_load_5x5__14) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.53, 3.07, 6.13, 12.27"); + } + power_lut_template (energy_inslew_load_5x5__13) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.11, 2.21, 4.42, 8.85, 17.69"); + } + power_lut_template (energy_inslew_load_5x5__12) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.76, 1.52, 3.03, 6.07, 12.13"); + } + power_lut_template (energy_inslew_load_5x5__11) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.71, 1.41, 2.83, 5.66, 11.31"); + } + power_lut_template (energy_inslew_load_5x5__10) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.02, 4.03, 8.06, 16.12, 32.25"); + } + power_lut_template (energy_inslew_load_5x5__9) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.01, 2.03, 4.05, 8.11, 16.22"); + } + power_lut_template (energy_inslew_load_5x5__8) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.02, 2.05, 4.09, 8.18, 16.36"); + } + power_lut_template (energy_inslew_load_5x5__7) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.61, 1.23, 2.45, 4.91, 9.81"); + } + power_lut_template (energy_inslew_load_5x5__6) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.06, 2.12, 4.23, 8.47, 16.94"); + } + power_lut_template (energy_inslew_load_5x5__5) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.87, 1.74, 3.49, 6.97, 13.94"); + } + power_lut_template (energy_inslew_load_5x5__4) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.71, 1.42, 2.84, 5.68, 11.36"); + } + power_lut_template (energy_inslew_load_5x5__3) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.04, 2.09, 4.17, 8.35, 16.70"); + } + power_lut_template (energy_inslew_load_5x5__2) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.75, 1.51, 3.02, 6.03, 12.07"); + } + power_lut_template (energy_inslew_load_5x5__1) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.94, 1.87, 3.75, 7.50, 15.00"); + } + power_lut_template (energy_inslew_load_5x5__0) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.64, 1.29, 2.57, 5.15, 10.29"); + } + + + + + cell (a2_x2) { + area : 0.0 ; + cell_leakage_power : 3.9 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 3.3 ; + } + leakage_power () { + when : "(!(i0) | !(i1))" ; + value : 4.4 ; + } + pin (i1) { + direction : input ; + capacitance : 6.03 ; + } + pin (i0) { + direction : input ; + capacitance : 5.74 ; + } + pin (q) { + function : "(i0 & i1)" ; + direction : output ; + capacitance : 2.57 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("30.4, 30.4, 30.4, 35.3, 43.9", \ + "31.1, 31.1, 31.1, 36.1, 45.2", \ + "28.3, 28.3, 28.3, 33.6, 43.3", \ + "19.2, 19.2, 19.2, 24.7, 34.9", \ + "-1.9, -1.9, -1.9, 3.7, 14.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("23.4, 23.4, 23.4, 30.2, 43.2", \ + "33.0, 33.0, 33.0, 39.7, 52.8", \ + "50.2, 50.2, 50.2, 56.9, 70.2", \ + "82.5, 82.5, 82.5, 89.3, 102.7", \ + "145.8, 145.8, 145.8, 152.8, 166.2"); + } + cell_fall (inslew_load_5x5__0) { + values ("41.4, 41.4, 41.4, 46.4, 55.0", \ + "50.7, 50.7, 50.7, 55.9, 65.2", \ + "65.7, 65.7, 65.7, 71.0, 80.5", \ + "92.2, 92.2, 92.2, 97.8, 108.1", \ + "143.0, 143.0, 143.0, 148.6, 159.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("22.8, 22.8, 22.8, 26.2, 32.6", \ + "34.2, 34.2, 34.2, 37.6, 44.1", \ + "55.2, 55.2, 55.2, 58.7, 65.5", \ + "96.5, 96.5, 96.5, 100.0, 106.7", \ + "178.3, 178.3, 178.3, 181.7, 188.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("32.4, 32.4, 32.4, 37.4, 46.2", \ + "29.5, 29.5, 29.5, 34.6, 43.8", \ + "19.5, 19.5, 19.5, 24.8, 34.5", \ + "-4.6, -4.6, -4.6, 0.8, 11.0", \ + "-56.6, -56.6, -56.6, -51.0, -40.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("26.9, 26.9, 26.9, 33.6, 46.7", \ + "35.0, 35.0, 35.0, 41.7, 54.8", \ + "49.6, 49.6, 49.6, 56.3, 69.6", \ + "77.2, 77.2, 77.2, 84.0, 97.4", \ + "131.1, 131.1, 131.1, 137.9, 151.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("50.6, 50.6, 50.6, 55.8, 64.6", \ + "65.6, 65.6, 65.6, 70.7, 80.3", \ + "91.0, 91.0, 91.0, 96.4, 106.2", \ + "138.1, 138.1, 138.1, 143.7, 154.3", \ + "230.1, 230.1, 230.1, 235.7, 246.8"); + } + fall_transition (inslew_load_5x5__0) { + values ("27.8, 27.8, 27.8, 31.2, 37.7", \ + "41.4, 41.4, 41.4, 44.9, 51.4", \ + "67.0, 67.0, 67.0, 70.4, 77.2", \ + "116.9, 116.9, 116.9, 120.4, 127.2", \ + "216.4, 216.4, 216.4, 219.8, 226.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("244.3, 244.3, 244.3, 276.4, 340.8", \ + "317.2, 317.2, 317.2, 349.4, 413.7", \ + "460.8, 460.8, 460.8, 493.0, 557.3", \ + "745.6, 745.6, 745.6, 777.8, 842.1", \ + "1313.9, 1313.9, 1313.9, 1346.1, 1410.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("306.0, 306.0, 306.0, 338.2, 402.5", \ + "424.8, 424.8, 424.8, 456.9, 521.3", \ + "657.4, 657.4, 657.4, 689.5, 753.9", \ + "1119.6, 1119.6, 1119.6, 1151.8, 1216.2", \ + "2042.4, 2042.4, 2042.4, 2074.6, 2139.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("295.6, 295.6, 295.6, 327.7, 392.1", \ + "360.3, 360.3, 360.3, 392.5, 456.8", \ + "487.5, 487.5, 487.5, 519.6, 584.0", \ + "739.8, 739.8, 739.8, 772.0, 836.3", \ + "1242.5, 1242.5, 1242.5, 1274.7, 1339.0"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("379.4, 379.4, 379.4, 411.5, 475.9", \ + "528.6, 528.6, 528.6, 560.7, 625.1", \ + "821.1, 821.1, 821.1, 853.3, 917.6", \ + "1402.5, 1402.5, 1402.5, 1434.7, 1499.0", \ + "2563.4, 2563.4, 2563.4, 2595.5, 2659.9"); + } + } + } + } + + cell (a2_x4) { + area : 0.0 ; + cell_leakage_power : 4.4 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 3.3 ; + } + leakage_power () { + when : "(!(i0) | !(i1))" ; + value : 5.4 ; + } + pin (i1) { + direction : input ; + capacitance : 6.23 ; + } + pin (i0) { + direction : input ; + capacitance : 5.79 ; + } + pin (q) { + function : "(i0 & i1)" ; + direction : output ; + capacitance : 3.75 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("42.0, 42.0, 42.0, 45.8, 52.8", \ + "44.5, 44.5, 44.5, 48.4, 55.6", \ + "43.8, 43.8, 43.8, 47.8, 55.2", \ + "36.3, 36.3, 36.3, 40.4, 48.2", \ + "17.2, 17.2, 17.2, 21.2, 29.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("29.6, 29.6, 29.6, 34.5, 44.2", \ + "39.2, 39.2, 39.2, 44.1, 53.8", \ + "56.6, 56.6, 56.6, 61.6, 71.3", \ + "89.6, 89.6, 89.6, 94.4, 104.3", \ + "153.5, 153.5, 153.5, 158.6, 168.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("55.1, 55.1, 55.1, 59.0, 66.2", \ + "66.6, 66.6, 66.6, 70.5, 77.6", \ + "83.4, 83.4, 83.4, 87.4, 94.8", \ + "111.8, 111.8, 111.8, 115.9, 123.9", \ + "165.0, 165.0, 165.0, 169.1, 177.2"); + } + fall_transition (inslew_load_5x5__1) { + values ("30.8, 30.8, 30.8, 33.3, 38.1", \ + "42.4, 42.4, 42.4, 44.9, 49.8", \ + "64.2, 64.2, 64.2, 66.6, 71.5", \ + "106.6, 106.6, 106.6, 109.1, 114.0", \ + "190.8, 190.8, 190.8, 193.2, 198.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("42.5, 42.5, 42.5, 46.3, 53.4", \ + "41.0, 41.0, 41.0, 44.9, 52.1", \ + "32.8, 32.8, 32.8, 36.7, 44.1", \ + "10.5, 10.5, 10.5, 14.6, 22.3", \ + "-39.7, -39.7, -39.7, -35.7, -27.6"); + } + rise_transition (inslew_load_5x5__1) { + values ("32.7, 32.7, 32.7, 37.6, 47.3", \ + "40.7, 40.7, 40.7, 45.6, 55.3", \ + "55.5, 55.5, 55.5, 60.5, 70.2", \ + "83.7, 83.7, 83.7, 88.5, 98.4", \ + "138.1, 138.1, 138.1, 143.2, 153.0"); + } + cell_fall (inslew_load_5x5__1) { + values ("63.8, 63.8, 63.8, 67.6, 74.9", \ + "80.4, 80.4, 80.4, 84.3, 91.4", \ + "107.3, 107.3, 107.3, 111.4, 119.0", \ + "156.4, 156.4, 156.4, 160.5, 168.6", \ + "251.1, 251.1, 251.1, 255.2, 263.4"); + } + fall_transition (inslew_load_5x5__1) { + values ("35.8, 35.8, 35.8, 38.3, 43.1", \ + "49.8, 49.8, 49.8, 52.2, 57.2", \ + "76.0, 76.0, 76.0, 78.5, 83.4", \ + "127.4, 127.4, 127.4, 129.9, 134.8", \ + "229.6, 229.6, 229.6, 232.0, 236.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__1) { + values ("439.8, 439.8, 439.8, 486.6, 580.4", \ + "543.0, 543.0, 543.0, 589.9, 683.6", \ + "742.8, 742.8, 742.8, 789.7, 883.4", \ + "1134.5, 1134.5, 1134.5, 1181.4, 1275.2", \ + "1911.7, 1911.7, 1911.7, 1958.6, 2052.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("556.3, 556.3, 556.3, 603.1, 696.9", \ + "723.5, 723.5, 723.5, 770.3, 864.1", \ + "1047.3, 1047.3, 1047.3, 1094.2, 1187.9", \ + "1687.4, 1687.4, 1687.4, 1734.2, 1828.0", \ + "2962.5, 2962.5, 2962.5, 3009.3, 3103.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__1) { + values ("499.7, 499.7, 499.7, 546.6, 640.3", \ + "589.2, 589.2, 589.2, 636.1, 729.8", \ + "764.3, 764.3, 764.3, 811.2, 905.0", \ + "1107.9, 1107.9, 1107.9, 1154.7, 1248.5", \ + "1788.3, 1788.3, 1788.3, 1835.1, 1928.9"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("649.7, 649.7, 649.7, 696.6, 790.3", \ + "857.3, 857.3, 857.3, 904.1, 997.9", \ + "1259.7, 1259.7, 1259.7, 1306.6, 1400.3", \ + "2056.6, 2056.6, 2056.6, 2103.5, 2197.2", \ + "3644.9, 3644.9, 3644.9, 3691.7, 3785.5"); + } + } + } + } + + cell (a3_x2) { + area : 0.0 ; + cell_leakage_power : 4.7 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 5 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2))" ; + value : 4.4 ; + } + pin (i2) { + direction : input ; + capacitance : 6.57 ; + } + pin (i1) { + direction : input ; + capacitance : 6.59 ; + } + pin (i0) { + direction : input ; + capacitance : 6.57 ; + } + pin (q) { + function : "(i0 & i1 & i2)" ; + direction : output ; + capacitance : 3.02 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("32.4, 32.4, 32.4, 37.9, 47.5", \ + "32.9, 32.9, 32.9, 38.4, 48.3", \ + "28.5, 28.5, 28.5, 34.0, 44.3", \ + "14.3, 14.3, 14.3, 20.0, 30.8", \ + "-18.2, -18.2, -18.2, -12.5, -1.3"); + } + rise_transition (inslew_load_5x5__2) { + values ("26.5, 26.5, 26.5, 34.3, 49.5", \ + "37.4, 37.4, 37.4, 45.1, 60.3", \ + "56.0, 56.0, 56.0, 63.8, 79.0", \ + "90.1, 90.1, 90.1, 97.9, 113.2", \ + "155.7, 155.7, 155.7, 163.5, 179.0"); + } + cell_fall (inslew_load_5x5__2) { + values ("40.7, 40.7, 40.7, 45.3, 53.3", \ + "50.0, 50.0, 50.0, 55.1, 63.7", \ + "64.2, 64.2, 64.2, 69.2, 78.8", \ + "90.0, 90.0, 90.0, 95.1, 104.8", \ + "139.0, 139.0, 139.0, 144.3, 154.3"); + } + fall_transition (inslew_load_5x5__2) { + values ("20.3, 20.3, 20.3, 23.3, 28.6", \ + "30.6, 30.6, 30.6, 33.4, 39.0", \ + "48.9, 48.9, 48.9, 52.4, 57.8", \ + "84.7, 84.7, 84.7, 88.0, 94.6", \ + "156.0, 156.0, 156.0, 159.0, 165.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("39.3, 39.3, 39.3, 44.9, 54.7", \ + "37.6, 37.6, 37.6, 43.1, 53.1", \ + "28.5, 28.5, 28.5, 34.0, 44.4", \ + "4.3, 4.3, 4.3, 10.0, 20.7", \ + "-50.0, -50.0, -50.0, -44.3, -33.1"); + } + rise_transition (inslew_load_5x5__2) { + values ("33.8, 33.8, 33.8, 41.6, 56.8", \ + "43.1, 43.1, 43.1, 50.8, 66.0", \ + "59.4, 59.4, 59.4, 67.2, 82.4", \ + "89.7, 89.7, 89.7, 97.5, 112.8", \ + "147.6, 147.6, 147.6, 155.5, 170.9"); + } + cell_fall (inslew_load_5x5__2) { + values ("50.0, 50.0, 50.0, 54.8, 63.0", \ + "63.0, 63.0, 63.0, 68.4, 77.4", \ + "84.8, 84.8, 84.8, 89.8, 99.4", \ + "123.9, 123.9, 123.9, 129.0, 138.8", \ + "199.4, 199.4, 199.4, 204.6, 214.7"); + } + fall_transition (inslew_load_5x5__2) { + values ("25.3, 25.3, 25.3, 28.2, 33.7", \ + "37.0, 37.0, 37.0, 39.8, 45.4", \ + "57.8, 57.8, 57.8, 61.2, 66.9", \ + "98.8, 98.8, 98.8, 102.0, 108.6", \ + "180.4, 180.4, 180.4, 183.4, 189.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("43.8, 43.8, 43.8, 49.3, 59.3", \ + "39.3, 39.3, 39.3, 44.8, 55.0", \ + "25.7, 25.7, 25.7, 31.3, 41.7", \ + "-8.2, -8.2, -8.2, -2.5, 8.3", \ + "-82.5, -82.5, -82.5, -76.8, -65.7"); + } + rise_transition (inslew_load_5x5__2) { + values ("40.4, 40.4, 40.4, 48.1, 63.3", \ + "48.0, 48.0, 48.0, 55.8, 71.0", \ + "62.4, 62.4, 62.4, 70.1, 85.4", \ + "89.2, 89.2, 89.2, 97.0, 112.4", \ + "140.6, 140.6, 140.6, 148.4, 163.8"); + } + cell_fall (inslew_load_5x5__2) { + values ("57.9, 57.9, 57.9, 63.0, 71.5", \ + "74.9, 74.9, 74.9, 80.1, 89.4", \ + "103.8, 103.8, 103.8, 108.8, 118.4", \ + "156.8, 156.8, 156.8, 161.9, 171.9", \ + "259.6, 259.6, 259.6, 264.9, 275.1"); + } + fall_transition (inslew_load_5x5__2) { + values ("29.8, 29.8, 29.8, 32.5, 38.1", \ + "42.7, 42.7, 42.7, 45.9, 51.4", \ + "66.6, 66.6, 66.6, 69.9, 76.0", \ + "113.3, 113.3, 113.3, 116.4, 123.0", \ + "206.1, 206.1, 206.1, 209.1, 215.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__2) { + values ("301.5, 301.5, 301.5, 339.2, 414.6", \ + "374.8, 374.8, 374.8, 412.5, 487.9", \ + "517.8, 517.8, 517.8, 555.5, 630.9", \ + "800.5, 800.5, 800.5, 838.2, 913.6", \ + "1363.6, 1363.6, 1363.6, 1401.3, 1476.7"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("349.3, 349.3, 349.3, 387.0, 462.4", \ + "481.4, 481.4, 481.4, 519.1, 594.5", \ + "738.9, 738.9, 738.9, 776.7, 852.1", \ + "1249.8, 1249.8, 1249.8, 1287.5, 1362.9", \ + "2269.2, 2269.2, 2269.2, 2306.9, 2382.3"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__2) { + values ("384.0, 384.0, 384.0, 421.7, 497.1", \ + "450.4, 450.4, 450.4, 488.1, 563.5", \ + "579.9, 579.9, 579.9, 617.6, 693.0", \ + "835.4, 835.4, 835.4, 873.1, 948.5", \ + "1342.6, 1342.6, 1342.6, 1380.3, 1455.7"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("440.1, 440.1, 440.1, 477.8, 553.2", \ + "595.0, 595.0, 595.0, 632.7, 708.1", \ + "896.8, 896.8, 896.8, 934.5, 1009.9", \ + "1495.6, 1495.6, 1495.6, 1533.3, 1608.7", \ + "2690.6, 2690.6, 2690.6, 2728.3, 2803.7"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__2) { + values ("466.4, 466.4, 466.4, 504.1, 579.5", \ + "526.5, 526.5, 526.5, 564.2, 639.6", \ + "644.9, 644.9, 644.9, 682.6, 758.0", \ + "878.9, 878.9, 878.9, 916.6, 992.0", \ + "1342.8, 1342.8, 1342.8, 1380.5, 1455.9"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("523.7, 523.7, 523.7, 561.4, 636.8", \ + "703.6, 703.6, 703.6, 741.3, 816.7", \ + "1054.5, 1054.5, 1054.5, 1092.2, 1167.6", \ + "1750.8, 1750.8, 1750.8, 1788.5, 1863.9", \ + "3139.9, 3139.9, 3139.9, 3177.6, 3253.0"); + } + } + } + } + + cell (a3_x4) { + area : 0.0 ; + cell_leakage_power : 4.2 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 3 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2))" ; + value : 5.4 ; + } + pin (i2) { + direction : input ; + capacitance : 4.79 ; + } + pin (i1) { + direction : input ; + capacitance : 4.75 ; + } + pin (i0) { + direction : input ; + capacitance : 4.75 ; + } + pin (q) { + function : "(i0 & i1 & i2)" ; + direction : output ; + capacitance : 4.17 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("50.2, 50.2, 50.2, 54.5, 62.3", \ + "53.6, 53.6, 53.6, 57.9, 66.0", \ + "53.7, 53.7, 53.7, 58.1, 66.3", \ + "46.5, 46.5, 46.5, 51.0, 59.7", \ + "26.0, 26.0, 26.0, 30.5, 39.4"); + } + rise_transition (inslew_load_5x5__3) { + values ("38.0, 38.0, 38.0, 43.5, 54.2", \ + "47.3, 47.3, 47.3, 52.8, 63.5", \ + "64.2, 64.2, 64.2, 69.7, 80.6", \ + "96.4, 96.4, 96.4, 101.8, 112.7", \ + "158.8, 158.8, 158.8, 164.5, 175.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("65.8, 65.8, 65.8, 69.9, 77.9", \ + "78.6, 78.6, 78.6, 82.9, 90.8", \ + "97.0, 97.0, 97.0, 101.6, 109.8", \ + "127.5, 127.5, 127.5, 132.0, 140.8", \ + "183.3, 183.3, 183.3, 187.9, 196.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("38.1, 38.1, 38.1, 40.9, 46.2", \ + "50.1, 50.1, 50.1, 52.8, 58.4", \ + "72.3, 72.3, 72.3, 75.1, 80.5", \ + "115.5, 115.5, 115.5, 118.3, 123.8", \ + "201.2, 201.2, 201.2, 203.9, 209.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("53.3, 53.3, 53.3, 57.7, 65.6", \ + "53.5, 53.5, 53.5, 57.8, 66.0", \ + "47.7, 47.7, 47.7, 52.2, 60.4", \ + "29.0, 29.0, 29.0, 33.6, 42.2", \ + "-15.6, -15.6, -15.6, -11.1, -2.1"); + } + rise_transition (inslew_load_5x5__3) { + values ("42.8, 42.8, 42.8, 48.2, 59.0", \ + "50.7, 50.7, 50.7, 56.2, 67.0", \ + "65.7, 65.7, 65.7, 71.2, 82.1", \ + "94.3, 94.3, 94.3, 99.7, 110.7", \ + "149.8, 149.8, 149.8, 155.5, 166.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("75.1, 75.1, 75.1, 79.4, 87.3", \ + "92.0, 92.0, 92.0, 96.4, 104.4", \ + "118.6, 118.6, 118.6, 123.2, 131.6", \ + "165.3, 165.3, 165.3, 169.9, 178.9", \ + "253.8, 253.8, 253.8, 258.4, 267.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("43.9, 43.9, 43.9, 46.7, 52.1", \ + "57.8, 57.8, 57.8, 60.5, 66.1", \ + "83.8, 83.8, 83.8, 86.6, 92.0", \ + "134.3, 134.3, 134.3, 137.1, 142.6", \ + "234.7, 234.7, 234.7, 237.4, 242.8"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("54.4, 54.4, 54.4, 58.8, 66.9", \ + "50.3, 50.3, 50.3, 54.6, 62.8", \ + "37.6, 37.6, 37.6, 42.0, 50.3", \ + "5.3, 5.3, 5.3, 9.8, 18.5", \ + "-67.2, -67.2, -67.2, -62.6, -53.7"); + } + rise_transition (inslew_load_5x5__3) { + values ("47.0, 47.0, 47.0, 52.5, 63.3", \ + "53.3, 53.3, 53.3, 58.9, 69.7", \ + "65.9, 65.9, 65.9, 71.4, 82.3", \ + "90.2, 90.2, 90.2, 95.7, 106.6", \ + "137.2, 137.2, 137.2, 142.8, 153.7"); + } + cell_fall (inslew_load_5x5__3) { + values ("84.0, 84.0, 84.0, 88.3, 96.1", \ + "106.0, 106.0, 106.0, 110.5, 118.6", \ + "143.1, 143.1, 143.1, 147.6, 156.2", \ + "210.8, 210.8, 210.8, 215.4, 224.3", \ + "341.7, 341.7, 341.7, 346.3, 355.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("49.7, 49.7, 49.7, 52.5, 58.0", \ + "66.1, 66.1, 66.1, 68.8, 74.3", \ + "97.2, 97.2, 97.2, 99.9, 105.4", \ + "158.0, 158.0, 158.0, 160.7, 166.2", \ + "278.7, 278.7, 278.7, 281.4, 286.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("487.1, 487.1, 487.1, 539.3, 643.6", \ + "580.5, 580.5, 580.5, 632.6, 737.0", \ + "759.3, 759.3, 759.3, 811.5, 915.8", \ + "1109.1, 1109.1, 1109.1, 1161.3, 1265.7", \ + "1801.3, 1801.3, 1801.3, 1853.5, 1957.8"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("610.0, 610.0, 610.0, 662.2, 766.5", \ + "766.7, 766.7, 766.7, 818.9, 923.2", \ + "1066.8, 1066.8, 1066.8, 1119.0, 1223.3", \ + "1657.6, 1657.6, 1657.6, 1709.8, 1814.1", \ + "2833.1, 2833.1, 2833.1, 2885.2, 2989.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("555.8, 555.8, 555.8, 608.0, 712.3", \ + "638.6, 638.6, 638.6, 690.8, 795.2", \ + "800.3, 800.3, 800.3, 852.5, 956.9", \ + "1116.3, 1116.3, 1116.3, 1168.4, 1272.8", \ + "1741.5, 1741.5, 1741.5, 1793.6, 1898.0"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("704.3, 704.3, 704.3, 756.5, 860.8", \ + "890.0, 890.0, 890.0, 942.2, 1046.5", \ + "1246.6, 1246.6, 1246.6, 1298.8, 1403.2", \ + "1949.4, 1949.4, 1949.4, 2001.6, 2105.9", \ + "3348.1, 3348.1, 3348.1, 3400.3, 3504.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("620.6, 620.6, 620.6, 672.7, 777.1", \ + "689.6, 689.6, 689.6, 741.8, 846.1", \ + "828.1, 828.1, 828.1, 880.3, 984.6", \ + "1100.4, 1100.4, 1100.4, 1152.6, 1256.9", \ + "1637.9, 1637.9, 1637.9, 1690.1, 1794.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("799.1, 799.1, 799.1, 851.3, 955.7", \ + "1023.5, 1023.5, 1023.5, 1075.7, 1180.0", \ + "1459.0, 1459.0, 1459.0, 1511.2, 1615.5", \ + "2318.9, 2318.9, 2318.9, 2371.0, 2475.4", \ + "4031.2, 4031.2, 4031.2, 4083.4, 4187.8"); + } + } + } + } + + cell (a4_x2) { + area : 0.0 ; + cell_leakage_power : 5.5 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 6.7 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2) | !(i3))" ; + value : 4.4 ; + } + pin (i3) { + direction : input ; + capacitance : 5.68 ; + } + pin (i2) { + direction : input ; + capacitance : 5.81 ; + } + pin (i1) { + direction : input ; + capacitance : 5.79 ; + } + pin (i0) { + direction : input ; + capacitance : 5.66 ; + } + pin (q) { + function : "(i1 & i0 & i2 & i3)" ; + direction : output ; + capacitance : 2.84 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("67.9, 67.9, 67.9, 73.4, 83.6", \ + "65.2, 65.2, 65.2, 70.8, 81.2", \ + "57.8, 57.8, 57.8, 63.3, 74.0", \ + "39.0, 39.0, 39.0, 44.7, 55.5", \ + "-3.6, -3.6, -3.6, 2.1, 13.3"); + } + rise_transition (inslew_load_5x5__4) { + values ("64.8, 64.8, 64.8, 72.1, 86.6", \ + "74.5, 74.5, 74.5, 81.8, 96.4", \ + "93.7, 93.7, 93.7, 101.1, 115.7", \ + "131.8, 131.8, 131.8, 139.2, 153.9", \ + "206.8, 206.8, 206.8, 214.3, 229.1"); + } + cell_fall (inslew_load_5x5__4) { + values ("57.6, 57.6, 57.6, 62.5, 71.2", \ + "71.8, 71.8, 71.8, 76.9, 86.2", \ + "94.4, 94.4, 94.4, 100.0, 109.9", \ + "136.4, 136.4, 136.4, 141.6, 151.7", \ + "217.1, 217.1, 217.1, 222.4, 232.7"); + } + fall_transition (inslew_load_5x5__4) { + values ("29.9, 29.9, 29.9, 33.1, 38.9", \ + "41.7, 41.7, 41.7, 44.8, 50.7", \ + "64.2, 64.2, 64.2, 67.0, 73.0", \ + "107.1, 107.1, 107.1, 110.6, 116.6", \ + "192.4, 192.4, 192.4, 195.9, 202.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("64.4, 64.4, 64.4, 69.9, 79.9", \ + "66.7, 66.7, 66.7, 72.3, 82.6", \ + "67.7, 67.7, 67.7, 73.2, 83.9", \ + "64.4, 64.4, 64.4, 70.1, 80.9", \ + "53.4, 53.4, 53.4, 59.1, 70.4"); + } + rise_transition (inslew_load_5x5__4) { + values ("58.2, 58.2, 58.2, 65.5, 80.0", \ + "69.9, 69.9, 69.9, 77.3, 91.8", \ + "92.6, 92.6, 92.6, 100.0, 114.6", \ + "136.6, 136.6, 136.6, 144.1, 158.8", \ + "223.3, 223.3, 223.3, 230.8, 245.6"); + } + cell_fall (inslew_load_5x5__4) { + values ("51.4, 51.4, 51.4, 56.3, 64.9", \ + "61.2, 61.2, 61.2, 66.2, 75.1", \ + "74.8, 74.8, 74.8, 80.2, 89.9", \ + "98.0, 98.0, 98.0, 103.1, 113.5", \ + "141.6, 141.6, 141.6, 146.8, 156.9"); + } + fall_transition (inslew_load_5x5__4) { + values ("26.6, 26.6, 26.6, 29.7, 35.5", \ + "36.4, 36.4, 36.4, 39.6, 45.5", \ + "55.1, 55.1, 55.1, 57.9, 64.0", \ + "91.0, 91.0, 91.0, 94.3, 100.1", \ + "161.6, 161.6, 161.6, 165.2, 171.8"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("58.7, 58.7, 58.7, 64.0, 74.0", \ + "64.9, 64.9, 64.9, 70.5, 80.6", \ + "72.6, 72.6, 72.6, 78.0, 88.7", \ + "82.5, 82.5, 82.5, 88.2, 99.0", \ + "98.2, 98.2, 98.2, 104.0, 115.3"); + } + rise_transition (inslew_load_5x5__4) { + values ("50.6, 50.6, 50.6, 58.0, 72.4", \ + "64.2, 64.2, 64.2, 71.5, 86.1", \ + "89.5, 89.5, 89.5, 96.9, 111.4", \ + "138.2, 138.2, 138.2, 145.6, 160.3", \ + "234.0, 234.0, 234.0, 241.4, 256.3"); + } + cell_fall (inslew_load_5x5__4) { + values ("45.1, 45.1, 45.1, 49.9, 58.3", \ + "51.3, 51.3, 51.3, 56.2, 64.9", \ + "57.8, 57.8, 57.8, 63.0, 72.6", \ + "66.6, 66.6, 66.6, 71.9, 82.1", \ + "81.5, 81.5, 81.5, 86.7, 96.6"); + } + fall_transition (inslew_load_5x5__4) { + values ("23.3, 23.3, 23.3, 26.4, 32.1", \ + "31.7, 31.7, 31.7, 34.9, 40.7", \ + "47.6, 47.6, 47.6, 50.6, 56.6", \ + "78.5, 78.5, 78.5, 81.6, 87.4", \ + "138.7, 138.7, 138.7, 142.2, 148.7"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("51.1, 51.1, 51.1, 56.5, 66.2", \ + "60.7, 60.7, 60.7, 66.1, 76.2", \ + "74.0, 74.0, 74.0, 79.5, 90.1", \ + "95.5, 95.5, 95.5, 101.2, 112.0", \ + "134.9, 134.9, 134.9, 140.6, 152.0"); + } + rise_transition (inslew_load_5x5__4) { + values ("42.7, 42.7, 42.7, 50.1, 64.4", \ + "57.8, 57.8, 57.8, 65.2, 79.6", \ + "85.3, 85.3, 85.3, 92.7, 107.2", \ + "137.9, 137.9, 137.9, 145.4, 160.1", \ + "241.4, 241.4, 241.4, 248.8, 263.7"); + } + cell_fall (inslew_load_5x5__4) { + values ("37.9, 37.9, 37.9, 42.7, 50.7", \ + "40.7, 40.7, 40.7, 45.6, 54.2", \ + "41.4, 41.4, 41.4, 46.5, 55.7", \ + "38.2, 38.2, 38.2, 43.7, 53.6", \ + "30.0, 30.0, 30.0, 35.3, 45.2"); + } + fall_transition (inslew_load_5x5__4) { + values ("19.8, 19.8, 19.8, 22.8, 28.4", \ + "27.0, 27.0, 27.0, 30.2, 35.9", \ + "40.8, 40.8, 40.8, 43.9, 49.9", \ + "67.9, 67.9, 67.9, 70.7, 76.7", \ + "120.2, 120.2, 120.2, 123.7, 129.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__4) { + values ("532.5, 532.5, 532.5, 568.0, 638.9", \ + "605.3, 605.3, 605.3, 640.8, 711.7", \ + "751.1, 751.1, 751.1, 786.6, 857.6", \ + "1042.6, 1042.6, 1042.6, 1078.1, 1149.1", \ + "1623.6, 1623.6, 1623.6, 1659.1, 1730.1"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("483.7, 483.7, 483.7, 519.2, 590.1", \ + "634.2, 634.2, 634.2, 669.6, 740.6", \ + "929.4, 929.4, 929.4, 964.9, 1035.8", \ + "1515.8, 1515.8, 1515.8, 1551.3, 1622.2", \ + "2686.2, 2686.2, 2686.2, 2721.7, 2792.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__4) { + values ("474.1, 474.1, 474.1, 509.6, 580.6", \ + "558.0, 558.0, 558.0, 593.5, 664.5", \ + "724.3, 724.3, 724.3, 759.8, 830.8", \ + "1054.5, 1054.5, 1054.5, 1090.0, 1161.0", \ + "1711.9, 1711.9, 1711.9, 1747.4, 1818.4"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("423.5, 423.5, 423.5, 459.0, 530.0", \ + "544.4, 544.4, 544.4, 579.9, 650.9", \ + "781.0, 781.0, 781.0, 816.5, 887.5", \ + "1250.5, 1250.5, 1250.5, 1286.0, 1356.9", \ + "2187.2, 2187.2, 2187.2, 2222.7, 2293.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__4) { + values ("408.8, 408.8, 408.8, 444.3, 515.2", \ + "501.2, 501.2, 501.2, 536.7, 607.7", \ + "681.9, 681.9, 681.9, 717.4, 788.4", \ + "1039.8, 1039.8, 1039.8, 1075.3, 1146.3", \ + "1752.2, 1752.2, 1752.2, 1787.7, 1858.7"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("365.6, 365.6, 365.6, 401.1, 472.1", \ + "465.7, 465.7, 465.7, 501.2, 572.1", \ + "661.2, 661.2, 661.2, 696.7, 767.6", \ + "1048.6, 1048.6, 1048.6, 1084.1, 1155.1", \ + "1821.4, 1821.4, 1821.4, 1856.9, 1927.9"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__4) { + values ("343.4, 343.4, 343.4, 378.9, 449.8", \ + "442.2, 442.2, 442.2, 477.7, 548.7", \ + "633.9, 633.9, 633.9, 669.4, 740.4", \ + "1012.9, 1012.9, 1012.9, 1048.4, 1119.3", \ + "1767.6, 1767.6, 1767.6, 1803.1, 1874.0"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("304.3, 304.3, 304.3, 339.7, 410.7", \ + "388.7, 388.7, 388.7, 424.2, 495.2", \ + "553.6, 553.6, 553.6, 589.0, 660.0", \ + "880.1, 880.1, 880.1, 915.6, 986.6", \ + "1531.2, 1531.2, 1531.2, 1566.6, 1637.6"); + } + } + } + } + + cell (a4_x4) { + area : 0.0 ; + cell_leakage_power : 6 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 6.7 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2) | !(i3))" ; + value : 5.4 ; + } + pin (i3) { + direction : input ; + capacitance : 5.75 ; + } + pin (i2) { + direction : input ; + capacitance : 5.83 ; + } + pin (i1) { + direction : input ; + capacitance : 5.80 ; + } + pin (i0) { + direction : input ; + capacitance : 5.64 ; + } + pin (q) { + function : "(i0 & i1 & i2 & i3)" ; + direction : output ; + capacitance : 4.17 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("72.6, 72.6, 72.6, 77.0, 85.3", \ + "69.2, 69.2, 69.2, 73.6, 82.0", \ + "60.2, 60.2, 60.2, 64.7, 73.3", \ + "37.8, 37.8, 37.8, 42.4, 51.2", \ + "-12.4, -12.4, -12.4, -7.8, 1.1"); + } + rise_transition (inslew_load_5x5__3) { + values ("65.5, 65.5, 65.5, 71.0, 82.0", \ + "73.6, 73.6, 73.6, 79.1, 90.0", \ + "89.9, 89.9, 89.9, 95.3, 106.3", \ + "122.3, 122.3, 122.3, 127.8, 138.7", \ + "186.2, 186.2, 186.2, 191.9, 203.1"); + } + cell_fall (inslew_load_5x5__3) { + values ("76.8, 76.8, 76.8, 81.1, 89.0", \ + "95.3, 95.3, 95.3, 99.8, 107.7", \ + "125.6, 125.6, 125.6, 130.1, 138.6", \ + "180.0, 180.0, 180.0, 184.5, 193.5", \ + "283.9, 283.9, 283.9, 288.5, 297.6"); + } + fall_transition (inslew_load_5x5__3) { + values ("43.1, 43.1, 43.1, 45.9, 51.4", \ + "57.5, 57.5, 57.5, 60.3, 65.8", \ + "84.7, 84.7, 84.7, 87.5, 92.9", \ + "137.7, 137.7, 137.7, 140.5, 146.1", \ + "242.9, 242.9, 242.9, 245.7, 251.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("70.2, 70.2, 70.2, 74.6, 82.8", \ + "71.8, 71.8, 71.8, 76.3, 84.6", \ + "71.2, 71.2, 71.2, 75.7, 84.4", \ + "64.0, 64.0, 64.0, 68.6, 77.4", \ + "43.9, 43.9, 43.9, 48.5, 57.4"); + } + rise_transition (inslew_load_5x5__3) { + values ("60.0, 60.0, 60.0, 65.5, 76.4", \ + "69.9, 69.9, 69.9, 75.4, 86.3", \ + "89.1, 89.1, 89.1, 94.5, 105.5", \ + "126.6, 126.6, 126.6, 132.2, 143.1", \ + "200.5, 200.5, 200.5, 206.2, 217.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("70.0, 70.0, 70.0, 74.2, 82.2", \ + "83.9, 83.9, 83.9, 88.2, 96.1", \ + "104.3, 104.3, 104.3, 108.8, 117.1", \ + "138.5, 138.5, 138.5, 143.1, 151.9", \ + "201.5, 201.5, 201.5, 206.1, 215.2"); + } + fall_transition (inslew_load_5x5__3) { + values ("39.0, 39.0, 39.0, 41.9, 47.2", \ + "51.2, 51.2, 51.2, 53.9, 59.5", \ + "73.9, 73.9, 73.9, 76.6, 82.1", \ + "117.9, 117.9, 117.9, 120.6, 126.2", \ + "205.1, 205.1, 205.1, 207.9, 213.3"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("66.0, 66.0, 66.0, 70.3, 78.5", \ + "71.7, 71.7, 71.7, 76.1, 84.4", \ + "77.7, 77.7, 77.7, 82.2, 90.8", \ + "83.4, 83.4, 83.4, 88.0, 96.8", \ + "89.0, 89.0, 89.0, 93.6, 102.5"); + } + rise_transition (inslew_load_5x5__3) { + values ("53.8, 53.8, 53.8, 59.4, 70.2", \ + "65.0, 65.0, 65.0, 70.6, 81.5", \ + "86.7, 86.7, 86.7, 92.1, 103.1", \ + "128.3, 128.3, 128.3, 133.9, 144.7", \ + "210.0, 210.0, 210.0, 215.6, 226.9"); + } + cell_fall (inslew_load_5x5__3) { + values ("63.2, 63.2, 63.2, 67.3, 75.3", \ + "73.2, 73.2, 73.2, 77.5, 85.4", \ + "86.2, 86.2, 86.2, 90.6, 98.8", \ + "104.9, 104.9, 104.9, 109.4, 118.1", \ + "136.8, 136.8, 136.8, 141.4, 150.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("35.0, 35.0, 35.0, 37.9, 43.2", \ + "45.5, 45.5, 45.5, 48.3, 53.8", \ + "65.0, 65.0, 65.0, 67.7, 73.2", \ + "102.7, 102.7, 102.7, 105.4, 110.9", \ + "177.0, 177.0, 177.0, 179.8, 185.3"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("59.8, 59.8, 59.8, 64.1, 72.2", \ + "69.5, 69.5, 69.5, 73.9, 82.1", \ + "81.2, 81.2, 81.2, 85.7, 94.2", \ + "97.8, 97.8, 97.8, 102.4, 111.2", \ + "126.1, 126.1, 126.1, 130.7, 139.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("47.0, 47.0, 47.0, 52.6, 63.4", \ + "60.0, 60.0, 60.0, 65.5, 76.4", \ + "83.4, 83.4, 83.4, 88.9, 99.9", \ + "128.4, 128.4, 128.4, 134.0, 144.8", \ + "216.5, 216.5, 216.5, 222.2, 233.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("55.5, 55.5, 55.5, 59.9, 67.6", \ + "62.3, 62.3, 62.3, 66.5, 74.5", \ + "68.9, 68.9, 68.9, 73.3, 81.3", \ + "75.1, 75.1, 75.1, 79.7, 88.2", \ + "82.0, 82.0, 82.0, 86.6, 95.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("30.7, 30.7, 30.7, 33.5, 38.8", \ + "39.9, 39.9, 39.9, 42.7, 48.1", \ + "56.9, 56.9, 56.9, 59.6, 65.2", \ + "89.7, 89.7, 89.7, 92.5, 98.0", \ + "154.4, 154.4, 154.4, 157.2, 162.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("802.3, 802.3, 802.3, 854.5, 958.8", \ + "893.9, 893.9, 893.9, 946.0, 1050.4", \ + "1078.6, 1078.6, 1078.6, 1130.8, 1235.1", \ + "1448.8, 1448.8, 1448.8, 1500.9, 1605.3", \ + "2186.4, 2186.4, 2186.4, 2238.6, 2342.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("793.9, 793.9, 793.9, 846.1, 950.4", \ + "1012.0, 1012.0, 1012.0, 1064.2, 1168.6", \ + "1435.1, 1435.1, 1435.1, 1487.3, 1591.7", \ + "2271.6, 2271.6, 2271.6, 2323.8, 2428.1", \ + "3937.5, 3937.5, 3937.5, 3989.7, 4094.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("730.4, 730.4, 730.4, 782.6, 887.0", \ + "838.6, 838.6, 838.6, 890.8, 995.1", \ + "1050.6, 1050.6, 1050.6, 1102.8, 1207.2", \ + "1472.3, 1472.3, 1472.3, 1524.5, 1628.8", \ + "2310.5, 2310.5, 2310.5, 2362.7, 2467.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("714.8, 714.8, 714.8, 767.0, 871.3", \ + "892.8, 892.8, 892.8, 945.0, 1049.4", \ + "1236.2, 1236.2, 1236.2, 1288.4, 1392.8", \ + "1913.3, 1913.3, 1913.3, 1965.5, 2069.9", \ + "3261.1, 3261.1, 3261.1, 3313.3, 3417.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("651.0, 651.0, 651.0, 703.2, 807.5", \ + "769.9, 769.9, 769.9, 822.1, 926.4", \ + "1003.3, 1003.3, 1003.3, 1055.5, 1159.9", \ + "1462.8, 1462.8, 1462.8, 1515.0, 1619.3", \ + "2375.4, 2375.4, 2375.4, 2427.6, 2531.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("638.4, 638.4, 638.4, 690.6, 795.0", \ + "787.9, 787.9, 787.9, 840.1, 944.5", \ + "1075.1, 1075.1, 1075.1, 1127.3, 1231.7", \ + "1640.5, 1640.5, 1640.5, 1692.7, 1797.0", \ + "2763.8, 2763.8, 2763.8, 2816.0, 2920.3"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__3) { + values ("568.3, 568.3, 568.3, 620.5, 724.9", \ + "699.8, 699.8, 699.8, 751.9, 856.3", \ + "948.8, 948.8, 948.8, 1001.0, 1105.4", \ + "1437.6, 1437.6, 1437.6, 1489.8, 1594.1", \ + "2408.0, 2408.0, 2408.0, 2460.2, 2564.5"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("557.2, 557.2, 557.2, 609.4, 713.7", \ + "684.9, 684.9, 684.9, 737.1, 841.5", \ + "930.1, 930.1, 930.1, 982.2, 1086.6", \ + "1411.8, 1411.8, 1411.8, 1464.0, 1568.3", \ + "2367.9, 2367.9, 2367.9, 2420.1, 2524.4"); + } + } + } + } + + cell (an12_x1) { + area : 0.0 ; + cell_leakage_power : 4.9 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 8.9 ; + } + leakage_power () { + when : "(i0 ^ i1)" ; + value : 4.4 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 1.5 ; + } + pin (i1) { + direction : input ; + capacitance : 6.78 ; + } + pin (i0) { + direction : input ; + capacitance : 6.72 ; + } + pin (q) { + function : "(i1 & !(i0))" ; + direction : output ; + capacitance : 3.49 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__5) { + values ("50.0, 50.0, 50.0, 59.2, 77.3", \ + "54.4, 54.4, 54.4, 63.7, 81.9", \ + "58.0, 58.0, 58.0, 67.5, 86.1", \ + "62.6, 62.6, 62.6, 72.2, 91.0", \ + "70.0, 70.0, 70.0, 79.7, 98.9"); + } + rise_transition (inslew_load_5x5__5) { + values ("61.9, 61.9, 61.9, 78.1, 111.0", \ + "78.6, 78.6, 78.6, 94.9, 127.3", \ + "105.8, 105.8, 105.8, 122.0, 154.3", \ + "156.7, 156.7, 156.7, 172.7, 204.7", \ + "256.9, 256.9, 256.9, 272.6, 304.3"); + } + cell_fall (inslew_load_5x5__5) { + values ("36.9, 36.9, 36.9, 42.5, 52.2", \ + "42.7, 42.7, 42.7, 48.7, 59.5", \ + "51.1, 51.1, 51.1, 57.6, 69.6", \ + "66.1, 66.1, 66.1, 73.0, 85.7", \ + "93.8, 93.8, 93.8, 101.2, 115.3"); + } + fall_transition (inslew_load_5x5__5) { + values ("23.2, 23.2, 23.2, 27.5, 35.5", \ + "33.7, 33.7, 33.7, 38.2, 46.5", \ + "53.7, 53.7, 53.7, 58.3, 66.9", \ + "92.7, 92.7, 92.7, 97.3, 106.4", \ + "170.2, 170.2, 170.2, 174.9, 184.1"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__5) { + values ("28.0, 28.0, 28.0, 38.7, 58.6", \ + "44.5, 44.5, 44.5, 55.5, 76.3", \ + "73.4, 73.4, 73.4, 84.7, 106.4", \ + "128.9, 128.9, 128.9, 140.4, 162.9", \ + "238.8, 238.8, 238.8, 250.4, 273.3"); + } + rise_transition (inslew_load_5x5__5) { + values ("56.3, 56.3, 56.3, 73.0, 106.2", \ + "105.0, 105.0, 105.0, 121.5, 154.5", \ + "195.7, 195.7, 195.7, 212.3, 245.4", \ + "373.5, 373.5, 373.5, 390.2, 423.5", \ + "727.5, 727.5, 727.5, 744.2, 777.6"); + } + cell_fall (inslew_load_5x5__5) { + values ("2.8, 2.8, 2.8, 9.6, 20.6", \ + "-5.0, -5.0, -5.0, 2.9, 16.3", \ + "-21.8, -21.8, -21.8, -12.8, 2.9", \ + "-56.1, -56.1, -56.1, -46.5, -28.7", \ + "-125.0, -125.0, -125.0, -115.0, -95.9"); + } + fall_transition (inslew_load_5x5__5) { + values ("14.5, 14.5, 14.5, 19.5, 28.1", \ + "25.3, 25.3, 25.3, 30.7, 40.3", \ + "46.3, 46.3, 46.3, 52.0, 62.7", \ + "87.6, 87.6, 87.6, 93.7, 105.1", \ + "170.0, 170.0, 170.0, 176.3, 188.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__5) { + values ("344.5, 344.5, 344.5, 388.1, 475.2", \ + "448.8, 448.8, 448.8, 492.4, 579.6", \ + "655.7, 655.7, 655.7, 699.3, 786.4", \ + "1067.7, 1067.7, 1067.7, 1111.2, 1198.4", \ + "1890.6, 1890.6, 1890.6, 1934.1, 2021.3"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("352.5, 352.5, 352.5, 396.0, 483.2", \ + "494.1, 494.1, 494.1, 537.7, 624.8", \ + "774.2, 774.2, 774.2, 817.8, 904.9", \ + "1333.2, 1333.2, 1333.2, 1376.7, 1463.9", \ + "2449.9, 2449.9, 2449.9, 2493.4, 2580.6"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__5) { + values ("140.8, 140.8, 140.8, 184.4, 271.6", \ + "235.0, 235.0, 235.0, 278.6, 365.8", \ + "423.4, 423.4, 423.4, 467.0, 554.1", \ + "800.2, 800.2, 800.2, 843.7, 930.9", \ + "1553.7, 1553.7, 1553.7, 1597.3, 1684.4"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("78.6, 78.6, 78.6, 122.2, 209.3", \ + "116.7, 116.7, 116.7, 160.3, 247.5", \ + "193.0, 193.0, 193.0, 236.6, 323.7", \ + "345.5, 345.5, 345.5, 389.1, 476.2", \ + "650.5, 650.5, 650.5, 694.1, 781.2"); + } + } + } + } + + cell (an12_x4) { + area : 0.0 ; + cell_leakage_power : 8.1 ; + leakage_power () { + when : "i0" ; + value : 9.9 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 8.9 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 5.4 ; + } + pin (i1) { + direction : input ; + capacitance : 6.85 ; + } + pin (i0) { + direction : input ; + capacitance : 5.88 ; + } + pin (q) { + function : "(!(i0) & i1)" ; + direction : output ; + capacitance : 4.23 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("48.1, 48.1, 48.1, 52.4, 60.3", \ + "52.3, 52.3, 52.3, 56.7, 64.9", \ + "56.8, 56.8, 56.8, 61.3, 69.7", \ + "61.7, 61.7, 61.7, 66.4, 75.3", \ + "68.9, 68.9, 68.9, 73.5, 82.5"); + } + rise_transition (inslew_load_5x5__6) { + values ("36.2, 36.2, 36.2, 41.7, 52.6", \ + "47.3, 47.3, 47.3, 52.9, 63.9", \ + "68.4, 68.4, 68.4, 74.0, 85.1", \ + "109.5, 109.5, 109.5, 115.0, 126.1", \ + "189.9, 189.9, 189.9, 195.7, 207.0"); + } + cell_fall (inslew_load_5x5__6) { + values ("45.4, 45.4, 45.4, 49.9, 57.5", \ + "52.8, 52.8, 52.8, 57.1, 65.2", \ + "62.9, 62.9, 62.9, 67.4, 75.4", \ + "78.9, 78.9, 78.9, 83.6, 92.3", \ + "108.1, 108.1, 108.1, 112.8, 121.9"); + } + fall_transition (inslew_load_5x5__6) { + values ("27.3, 27.3, 27.3, 30.0, 35.4", \ + "37.9, 37.9, 37.9, 40.8, 46.2", \ + "58.3, 58.3, 58.3, 61.0, 66.6", \ + "97.9, 97.9, 97.9, 100.7, 106.3", \ + "176.8, 176.8, 176.8, 179.6, 185.1"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__6) { + values ("61.5, 61.5, 61.5, 65.8, 73.5", \ + "61.0, 61.0, 61.0, 65.3, 73.2", \ + "54.6, 54.6, 54.6, 59.0, 67.1", \ + "36.3, 36.3, 36.3, 40.8, 49.1", \ + "-4.7, -4.7, -4.7, -0.1, 8.6"); + } + rise_transition (inslew_load_5x5__6) { + values ("30.4, 30.4, 30.4, 36.0, 46.9", \ + "35.7, 35.7, 35.7, 41.3, 52.1", \ + "44.9, 44.9, 44.9, 50.5, 61.4", \ + "62.0, 62.0, 62.0, 67.6, 78.7", \ + "94.8, 94.8, 94.8, 100.3, 111.4"); + } + cell_fall (inslew_load_5x5__6) { + values ("70.3, 70.3, 70.3, 74.6, 81.9", \ + "87.2, 87.2, 87.2, 91.6, 99.1", \ + "114.0, 114.0, 114.0, 118.3, 126.3", \ + "161.8, 161.8, 161.8, 166.2, 174.1", \ + "252.2, 252.2, 252.2, 256.9, 265.4"); + } + fall_transition (inslew_load_5x5__6) { + values ("21.1, 21.1, 21.1, 23.9, 29.3", \ + "26.3, 26.3, 26.3, 29.1, 34.5", \ + "35.4, 35.4, 35.4, 38.3, 43.6", \ + "52.5, 52.5, 52.5, 55.2, 60.8", \ + "85.5, 85.5, 85.5, 88.4, 93.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__6) { + values ("559.2, 559.2, 559.2, 612.1, 717.9", \ + "702.2, 702.2, 702.2, 755.1, 861.0", \ + "983.5, 983.5, 983.5, 1036.5, 1142.3", \ + "1542.7, 1542.7, 1542.7, 1595.6, 1701.5", \ + "2656.7, 2656.7, 2656.7, 2709.6, 2815.4"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("592.0, 592.0, 592.0, 644.9, 750.8", \ + "778.7, 778.7, 778.7, 831.6, 937.5", \ + "1144.2, 1144.2, 1144.2, 1197.1, 1303.0", \ + "1869.9, 1869.9, 1869.9, 1922.8, 2028.7", \ + "3317.8, 3317.8, 3317.8, 3370.7, 3476.5"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__6) { + values ("618.6, 618.6, 618.6, 671.5, 777.4", \ + "722.0, 722.0, 722.0, 775.0, 880.8", \ + "920.7, 920.7, 920.7, 973.6, 1079.5", \ + "1311.2, 1311.2, 1311.2, 1364.1, 1470.0", \ + "2084.1, 2084.1, 2084.1, 2137.1, 2242.9"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("646.5, 646.5, 646.5, 699.5, 805.3", \ + "808.0, 808.0, 808.0, 860.9, 966.8", \ + "1117.3, 1117.3, 1117.3, 1170.2, 1276.1", \ + "1725.3, 1725.3, 1725.3, 1778.2, 1884.1", \ + "2933.8, 2933.8, 2933.8, 2986.7, 3092.5"); + } + } + } + } + + cell (ao22_x2) { + area : 0.0 ; + cell_leakage_power : 3.1 ; + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 2.9 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 4.2 ; + } + leakage_power () { + when : "(!((i0 | i1)) | !(i2))" ; + value : 2.1 ; + } + pin (i2) { + direction : input ; + capacitance : 6.38 ; + } + pin (i1) { + direction : input ; + capacitance : 5.91 ; + } + pin (i0) { + direction : input ; + capacitance : 5.78 ; + } + pin (q) { + function : "((i0 | i1) & i2)" ; + direction : output ; + capacitance : 2.45 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__7) { + values ("40.8, 40.8, 40.8, 46.9, 57.7", \ + "46.2, 46.2, 46.2, 52.5, 63.7", \ + "51.7, 51.7, 51.7, 58.0, 69.8", \ + "57.9, 57.9, 57.9, 64.3, 76.8", \ + "67.0, 67.0, 67.0, 73.6, 86.3"); + } + rise_transition (inslew_load_5x5__7) { + values ("31.0, 31.0, 31.0, 39.5, 56.0", \ + "44.2, 44.2, 44.2, 52.7, 69.3", \ + "67.6, 67.6, 67.6, 76.1, 92.9", \ + "111.5, 111.5, 111.5, 120.1, 137.0", \ + "197.1, 197.1, 197.1, 205.7, 222.8"); + } + cell_fall (inslew_load_5x5__7) { + values ("63.1, 63.1, 63.1, 69.0, 79.4", \ + "68.2, 68.2, 68.2, 74.1, 85.1", \ + "76.2, 76.2, 76.2, 82.1, 93.3", \ + "90.7, 90.7, 90.7, 96.8, 108.5", \ + "119.0, 119.0, 119.0, 125.2, 137.3"); + } + fall_transition (inslew_load_5x5__7) { + values ("39.0, 39.0, 39.0, 42.5, 49.3", \ + "51.1, 51.1, 51.1, 54.7, 61.7", \ + "73.9, 73.9, 73.9, 78.0, 85.1", \ + "119.4, 119.4, 119.4, 123.5, 131.3", \ + "209.4, 209.4, 209.4, 213.3, 221.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__7) { + values ("31.8, 31.8, 31.8, 37.9, 48.4", \ + "30.3, 30.3, 30.3, 36.4, 47.3", \ + "21.0, 21.0, 21.0, 27.2, 38.7", \ + "-3.6, -3.6, -3.6, 2.8, 14.8", \ + "-57.4, -57.4, -57.4, -51.0, -38.4"); + } + rise_transition (inslew_load_5x5__7) { + values ("24.8, 24.8, 24.8, 33.4, 49.9", \ + "34.8, 34.8, 34.8, 43.3, 59.9", \ + "51.4, 51.4, 51.4, 59.9, 76.6", \ + "81.5, 81.5, 81.5, 90.0, 106.9", \ + "138.7, 138.7, 138.7, 147.3, 164.3"); + } + cell_fall (inslew_load_5x5__7) { + values ("54.1, 54.1, 54.1, 59.7, 69.3", \ + "68.2, 68.2, 68.2, 74.3, 84.8", \ + "91.1, 91.1, 91.1, 97.0, 108.1", \ + "133.0, 133.0, 133.0, 139.1, 150.7", \ + "214.1, 214.1, 214.1, 220.3, 232.4"); + } + fall_transition (inslew_load_5x5__7) { + values ("28.9, 28.9, 28.9, 32.5, 39.3", \ + "43.1, 43.1, 43.1, 46.6, 53.4", \ + "68.1, 68.1, 68.1, 72.1, 79.1", \ + "116.7, 116.7, 116.7, 120.8, 128.5", \ + "213.3, 213.3, 213.3, 217.2, 225.2"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__7) { + values ("41.2, 41.2, 41.2, 47.3, 58.2", \ + "41.8, 41.8, 41.8, 48.0, 59.3", \ + "38.6, 38.6, 38.6, 44.9, 56.6", \ + "27.3, 27.3, 27.3, 33.8, 46.1", \ + "1.0, 1.0, 1.0, 7.6, 20.3"); + } + rise_transition (inslew_load_5x5__7) { + values ("34.0, 34.0, 34.0, 42.5, 59.1", \ + "45.0, 45.0, 45.0, 53.5, 70.2", \ + "65.0, 65.0, 65.0, 73.5, 90.3", \ + "102.6, 102.6, 102.6, 111.2, 128.1", \ + "175.7, 175.7, 175.7, 184.3, 201.4"); + } + cell_fall (inslew_load_5x5__7) { + values ("44.2, 44.2, 44.2, 49.5, 58.9", \ + "53.1, 53.1, 53.1, 58.8, 68.9", \ + "66.9, 66.9, 66.9, 72.7, 83.8", \ + "91.7, 91.7, 91.7, 97.8, 109.0", \ + "139.2, 139.2, 139.2, 145.3, 157.3"); + } + fall_transition (inslew_load_5x5__7) { + values ("24.2, 24.2, 24.2, 27.8, 34.3", \ + "34.7, 34.7, 34.7, 38.2, 45.0", \ + "54.2, 54.2, 54.2, 57.9, 64.8", \ + "92.1, 92.1, 92.1, 96.2, 103.6", \ + "167.7, 167.7, 167.7, 171.6, 179.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__7) { + values ("286.7, 286.7, 286.7, 317.4, 378.7", \ + "369.8, 369.8, 369.8, 400.5, 461.8", \ + "533.2, 533.2, 533.2, 563.9, 625.2", \ + "857.4, 857.4, 857.4, 888.1, 949.4", \ + "1504.0, 1504.0, 1504.0, 1534.7, 1596.0"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("409.9, 409.9, 409.9, 440.5, 501.9", \ + "526.4, 526.4, 526.4, 557.1, 618.4", \ + "755.8, 755.8, 755.8, 786.4, 847.8", \ + "1213.8, 1213.8, 1213.8, 1244.5, 1305.8", \ + "2125.7, 2125.7, 2125.7, 2156.4, 2217.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__7) { + values ("225.7, 225.7, 225.7, 256.4, 317.7", \ + "274.6, 274.6, 274.6, 305.2, 366.6", \ + "369.0, 369.0, 369.0, 399.7, 461.0", \ + "555.1, 555.1, 555.1, 585.7, 647.1", \ + "924.5, 924.5, 924.5, 955.2, 1016.5"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("310.8, 310.8, 310.8, 341.4, 402.8", \ + "429.9, 429.9, 429.9, 460.5, 521.9", \ + "659.7, 659.7, 659.7, 690.4, 751.7", \ + "1114.4, 1114.4, 1114.4, 1145.1, 1206.4", \ + "2021.0, 2021.0, 2021.0, 2051.7, 2113.0"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__7) { + values ("324.5, 324.5, 324.5, 355.2, 416.5", \ + "398.1, 398.1, 398.1, 428.8, 490.1", \ + "543.3, 543.3, 543.3, 573.9, 635.3", \ + "831.6, 831.6, 831.6, 862.3, 923.6", \ + "1406.5, 1406.5, 1406.5, 1437.1, 1498.5"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("371.0, 371.0, 371.0, 401.6, 463.0", \ + "503.1, 503.1, 503.1, 533.7, 595.1", \ + "763.9, 763.9, 763.9, 794.6, 855.9", \ + "1283.4, 1283.4, 1283.4, 1314.0, 1375.4", \ + "2321.2, 2321.2, 2321.2, 2351.8, 2413.2"); + } + } + } + } + + cell (ao22_x4) { + area : 0.0 ; + cell_leakage_power : 3 ; + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 1.5 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 2 ; + } + leakage_power () { + when : "(!((i0 | i1)) | !(i2))" ; + value : 5.4 ; + } + pin (i2) { + direction : input ; + capacitance : 4.99 ; + } + pin (i1) { + direction : input ; + capacitance : 4.76 ; + } + pin (i0) { + direction : input ; + capacitance : 4.62 ; + } + pin (q) { + function : "((i0 | i1) & i2)" ; + direction : output ; + capacitance : 4.09 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__8) { + values ("44.3, 44.3, 44.3, 48.5, 56.1", \ + "45.1, 45.1, 45.1, 49.4, 57.3", \ + "40.3, 40.3, 40.3, 44.6, 52.8", \ + "22.7, 22.7, 22.7, 27.2, 35.8", \ + "-18.9, -18.9, -18.9, -14.4, -5.6"); + } + rise_transition (inslew_load_5x5__8) { + values ("31.4, 31.4, 31.4, 36.8, 47.3", \ + "39.5, 39.5, 39.5, 44.9, 55.5", \ + "54.3, 54.3, 54.3, 59.7, 70.4", \ + "81.8, 81.8, 81.8, 87.2, 98.0", \ + "134.9, 134.9, 134.9, 140.4, 151.3"); + } + cell_fall (inslew_load_5x5__8) { + values ("128.7, 128.7, 128.7, 133.2, 141.5", \ + "148.1, 148.1, 148.1, 152.7, 161.2", \ + "182.3, 182.3, 182.3, 187.0, 195.8", \ + "247.5, 247.5, 247.5, 252.1, 261.3", \ + "376.6, 376.6, 376.6, 381.2, 390.4"); + } + fall_transition (inslew_load_5x5__8) { + values ("80.9, 80.9, 80.9, 83.6, 89.3", \ + "101.3, 101.3, 101.3, 104.1, 109.7", \ + "139.6, 139.6, 139.6, 142.5, 148.1", \ + "215.5, 215.5, 215.5, 218.3, 224.2", \ + "367.5, 367.5, 367.5, 370.2, 375.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__8) { + values ("39.6, 39.6, 39.6, 43.8, 51.3", \ + "36.1, 36.1, 36.1, 40.4, 48.1", \ + "21.4, 21.4, 21.4, 25.7, 33.7", \ + "-18.1, -18.1, -18.1, -13.6, -5.3", \ + "-107.5, -107.5, -107.5, -102.9, -94.2"); + } + rise_transition (inslew_load_5x5__8) { + values ("28.5, 28.5, 28.5, 33.9, 44.4", \ + "34.9, 34.9, 34.9, 40.3, 50.8", \ + "45.6, 45.6, 45.6, 51.1, 61.6", \ + "64.7, 64.7, 64.7, 70.1, 80.8", \ + "100.2, 100.2, 100.2, 105.8, 116.4"); + } + cell_fall (inslew_load_5x5__8) { + values ("114.7, 114.7, 114.7, 119.1, 127.2", \ + "144.9, 144.9, 144.9, 149.4, 157.8", \ + "194.6, 194.6, 194.6, 199.3, 208.0", \ + "286.4, 286.4, 286.4, 291.0, 300.2", \ + "464.1, 464.1, 464.1, 468.8, 478.0"); + } + fall_transition (inslew_load_5x5__8) { + values ("66.7, 66.7, 66.7, 69.5, 75.2", \ + "89.2, 89.2, 89.2, 92.0, 97.6", \ + "129.3, 129.3, 129.3, 132.2, 137.8", \ + "207.0, 207.0, 207.0, 209.9, 215.7", \ + "360.9, 360.9, 360.9, 363.8, 369.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__8) { + values ("44.2, 44.2, 44.2, 48.5, 56.1", \ + "41.4, 41.4, 41.4, 45.6, 53.6", \ + "29.7, 29.7, 29.7, 34.1, 42.2", \ + "-1.1, -1.1, -1.1, 3.4, 11.9", \ + "-70.2, -70.2, -70.2, -65.7, -56.8"); + } + rise_transition (inslew_load_5x5__8) { + values ("34.1, 34.1, 34.1, 39.4, 50.0", \ + "40.8, 40.8, 40.8, 46.2, 56.8", \ + "53.4, 53.4, 53.4, 58.8, 69.5", \ + "76.9, 76.9, 76.9, 82.3, 93.0", \ + "121.9, 121.9, 121.9, 127.4, 138.2"); + } + cell_fall (inslew_load_5x5__8) { + values ("83.5, 83.5, 83.5, 87.8, 96.0", \ + "105.1, 105.1, 105.1, 109.5, 117.6", \ + "141.0, 141.0, 141.0, 145.5, 154.0", \ + "206.7, 206.7, 206.7, 211.4, 220.3", \ + "333.3, 333.3, 333.3, 337.9, 347.1"); + } + fall_transition (inslew_load_5x5__8) { + values ("49.1, 49.1, 49.1, 52.1, 57.6", \ + "65.5, 65.5, 65.5, 68.3, 74.1", \ + "96.2, 96.2, 96.2, 99.0, 104.6", \ + "156.1, 156.1, 156.1, 159.0, 164.6", \ + "275.0, 275.0, 275.0, 277.8, 283.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__8) { + values ("452.4, 452.4, 452.4, 503.6, 605.8", \ + "535.2, 535.2, 535.2, 586.4, 688.6", \ + "694.2, 694.2, 694.2, 745.3, 847.6", \ + "1002.4, 1002.4, 1002.4, 1053.5, 1155.8", \ + "1611.1, 1611.1, 1611.1, 1662.2, 1764.5"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("1006.0, 1006.0, 1006.0, 1057.2, 1159.4", \ + "1241.0, 1241.0, 1241.0, 1292.2, 1394.4", \ + "1690.4, 1690.4, 1690.4, 1741.5, 1843.8", \ + "2583.5, 2583.5, 2583.5, 2634.6, 2736.9", \ + "4370.2, 4370.2, 4370.2, 4421.3, 4523.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__8) { + values ("404.2, 404.2, 404.2, 455.4, 557.6", \ + "458.5, 458.5, 458.5, 509.7, 611.9", \ + "557.5, 557.5, 557.5, 608.7, 710.9", \ + "743.3, 743.3, 743.3, 794.4, 896.7", \ + "1102.3, 1102.3, 1102.3, 1153.4, 1255.7"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("843.7, 843.7, 843.7, 894.8, 997.1", \ + "1089.2, 1089.2, 1089.2, 1140.3, 1242.6", \ + "1540.8, 1540.8, 1540.8, 1592.0, 1694.2", \ + "2424.1, 2424.1, 2424.1, 2475.3, 2577.5", \ + "4178.2, 4178.2, 4178.2, 4229.4, 4331.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__8) { + values ("507.0, 507.0, 507.0, 558.1, 660.4", \ + "578.2, 578.2, 578.2, 629.4, 731.6", \ + "716.7, 716.7, 716.7, 767.8, 870.1", \ + "985.8, 985.8, 985.8, 1036.9, 1139.2", \ + "1515.2, 1515.2, 1515.2, 1566.3, 1668.6"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("773.0, 773.0, 773.0, 824.2, 926.4", \ + "990.3, 990.3, 990.3, 1041.4, 1143.7", \ + "1409.6, 1409.6, 1409.6, 1460.7, 1563.0", \ + "2237.4, 2237.4, 2237.4, 2288.5, 2390.8", \ + "3886.1, 3886.1, 3886.1, 3937.2, 4039.5"); + } + } + } + } + + cell (ao2o22_x2) { + area : 0.0 ; + cell_leakage_power : 2.9 ; + leakage_power () { + when : "(i3 & !(i2) & !(i1) & i0)" ; + value : 1.4 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 3.3 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & i3) | (!(i1) & i2))) | (i1 & !(i2) & i3))" ; + value : 2.3 ; + } + leakage_power () { + when : "(!((i0 | i1)) | (!(i2) & !(i3)))" ; + value : 4.4 ; + } + pin (i3) { + direction : input ; + capacitance : 5.57 ; + } + pin (i2) { + direction : input ; + capacitance : 5.63 ; + } + pin (i1) { + direction : input ; + capacitance : 5.56 ; + } + pin (i0) { + direction : input ; + capacitance : 5.44 ; + } + pin (q) { + function : "((i3 | i2) & (i0 | i1))" ; + direction : output ; + capacitance : 2.57 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("41.1, 41.1, 41.1, 46.2, 55.1", \ + "44.9, 44.9, 44.9, 50.1, 59.5", \ + "47.4, 47.4, 47.4, 52.8, 62.7", \ + "47.8, 47.8, 47.8, 53.4, 63.9", \ + "44.9, 44.9, 44.9, 50.5, 61.5"); + } + rise_transition (inslew_load_5x5__0) { + values ("29.8, 29.8, 29.8, 36.5, 49.6", \ + "40.2, 40.2, 40.2, 46.9, 60.1", \ + "59.1, 59.1, 59.1, 65.9, 79.2", \ + "95.2, 95.2, 95.2, 101.9, 115.5", \ + "165.7, 165.7, 165.7, 172.7, 186.2"); + } + cell_fall (inslew_load_5x5__0) { + values ("82.4, 82.4, 82.4, 87.6, 97.3", \ + "91.9, 91.9, 91.9, 97.3, 107.1", \ + "107.5, 107.5, 107.5, 113.1, 123.4", \ + "137.1, 137.1, 137.1, 142.7, 153.6", \ + "195.0, 195.0, 195.0, 200.6, 211.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("49.4, 49.4, 49.4, 52.9, 59.6", \ + "63.5, 63.5, 63.5, 67.0, 73.9", \ + "90.4, 90.4, 90.4, 93.9, 100.7", \ + "144.0, 144.0, 144.0, 147.5, 154.5", \ + "249.5, 249.5, 249.5, 253.0, 260.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("33.5, 33.5, 33.5, 38.4, 47.1", \ + "31.0, 31.0, 31.0, 36.0, 45.1", \ + "20.1, 20.1, 20.1, 25.4, 35.0", \ + "-7.6, -7.6, -7.6, -2.1, 7.9", \ + "-68.1, -68.1, -68.1, -62.5, -51.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("25.2, 25.2, 25.2, 31.9, 44.9", \ + "32.8, 32.8, 32.8, 39.6, 52.7", \ + "46.2, 46.2, 46.2, 53.0, 66.2", \ + "70.8, 70.8, 70.8, 77.6, 91.0", \ + "118.3, 118.3, 118.3, 125.1, 138.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("68.7, 68.7, 68.7, 73.8, 83.3", \ + "88.0, 88.0, 88.0, 93.3, 102.9", \ + "119.4, 119.4, 119.4, 124.9, 135.1", \ + "177.2, 177.2, 177.2, 182.8, 193.6", \ + "289.4, 289.4, 289.4, 295.0, 306.1"); + } + fall_transition (inslew_load_5x5__0) { + values ("37.0, 37.0, 37.0, 40.5, 47.1", \ + "53.4, 53.4, 53.4, 56.9, 63.8", \ + "83.3, 83.3, 83.3, 86.8, 93.7", \ + "141.4, 141.4, 141.4, 144.8, 151.9", \ + "256.3, 256.3, 256.3, 259.7, 266.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("39.6, 39.6, 39.6, 44.6, 53.6", \ + "34.5, 34.5, 34.5, 39.7, 49.0", \ + "18.6, 18.6, 18.6, 23.8, 33.5", \ + "-20.6, -20.6, -20.6, -15.2, -5.2", \ + "-106.8, -106.8, -106.8, -101.2, -90.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("31.4, 31.4, 31.4, 38.2, 51.3", \ + "37.7, 37.7, 37.7, 44.4, 57.6", \ + "49.0, 49.0, 49.0, 55.8, 69.0", \ + "69.7, 69.7, 69.7, 76.5, 89.9", \ + "109.2, 109.2, 109.2, 116.0, 129.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("89.9, 89.9, 89.9, 95.1, 104.8", \ + "115.8, 115.8, 115.8, 121.3, 131.2", \ + "159.5, 159.5, 159.5, 165.1, 175.6", \ + "241.2, 241.2, 241.2, 246.9, 257.8", \ + "400.9, 400.9, 400.9, 406.6, 417.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("49.0, 49.0, 49.0, 52.5, 59.3", \ + "68.7, 68.7, 68.7, 72.2, 79.0", \ + "104.2, 104.2, 104.2, 107.7, 114.6", \ + "173.5, 173.5, 173.5, 177.0, 184.0", \ + "311.1, 311.1, 311.1, 314.6, 321.4"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("46.3, 46.3, 46.3, 51.4, 60.6", \ + "46.1, 46.1, 46.1, 51.3, 60.8", \ + "41.0, 41.0, 41.0, 46.3, 56.3", \ + "25.3, 25.3, 25.3, 30.8, 41.3", \ + "-10.8, -10.8, -10.8, -5.2, 5.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("35.8, 35.8, 35.8, 42.5, 55.7", \ + "44.4, 44.4, 44.4, 51.1, 64.3", \ + "60.5, 60.5, 60.5, 67.3, 80.6", \ + "91.5, 91.5, 91.5, 98.2, 111.7", \ + "151.8, 151.8, 151.8, 158.8, 172.2"); + } + cell_fall (inslew_load_5x5__0) { + values ("104.9, 104.9, 104.9, 110.3, 120.0", \ + "121.5, 121.5, 121.5, 127.0, 137.2", \ + "151.2, 151.2, 151.2, 156.8, 167.4", \ + "208.0, 208.0, 208.0, 213.7, 224.6", \ + "320.8, 320.8, 320.8, 326.5, 337.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("62.6, 62.6, 62.6, 66.1, 73.0", \ + "80.6, 80.6, 80.6, 84.1, 90.9", \ + "114.6, 114.6, 114.6, 118.1, 125.0", \ + "182.3, 182.3, 182.3, 185.7, 192.7", \ + "317.6, 317.6, 317.6, 321.0, 327.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("299.0, 299.0, 299.0, 331.1, 395.5", \ + "377.6, 377.6, 377.6, 409.7, 474.1", \ + "531.7, 531.7, 531.7, 563.8, 628.2", \ + "836.7, 836.7, 836.7, 868.9, 933.2", \ + "1444.4, 1444.4, 1444.4, 1476.5, 1540.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("484.0, 484.0, 484.0, 516.1, 580.5", \ + "607.9, 607.9, 607.9, 640.1, 704.4", \ + "849.9, 849.9, 849.9, 882.1, 946.4", \ + "1333.7, 1333.7, 1333.7, 1365.8, 1430.2", \ + "2294.4, 2294.4, 2294.4, 2326.6, 2390.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("241.3, 241.3, 241.3, 273.5, 337.8", \ + "288.9, 288.9, 288.9, 321.1, 385.4", \ + "380.1, 380.1, 380.1, 412.3, 476.6", \ + "558.5, 558.5, 558.5, 590.7, 655.0", \ + "912.7, 912.7, 912.7, 944.9, 1009.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("371.1, 371.1, 371.1, 403.3, 467.6", \ + "502.6, 502.6, 502.6, 534.7, 599.1", \ + "753.6, 753.6, 753.6, 785.7, 850.1", \ + "1248.5, 1248.5, 1248.5, 1280.7, 1345.0", \ + "2233.9, 2233.9, 2233.9, 2266.1, 2330.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("321.0, 321.0, 321.0, 353.1, 417.5", \ + "361.6, 361.6, 361.6, 393.8, 458.1", \ + "440.5, 440.5, 440.5, 472.6, 537.0", \ + "593.7, 593.7, 593.7, 625.8, 690.2", \ + "895.7, 895.7, 895.7, 927.9, 992.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("492.1, 492.1, 492.1, 524.3, 588.6", \ + "652.9, 652.9, 652.9, 685.1, 749.4", \ + "957.9, 957.9, 957.9, 990.1, 1054.4", \ + "1561.1, 1561.1, 1561.1, 1593.3, 1657.6", \ + "2763.1, 2763.1, 2763.1, 2795.3, 2859.6"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("377.3, 377.3, 377.3, 409.5, 473.8", \ + "446.9, 446.9, 446.9, 479.0, 543.4", \ + "584.0, 584.0, 584.0, 616.2, 680.5", \ + "855.7, 855.7, 855.7, 887.9, 952.2", \ + "1396.3, 1396.3, 1396.3, 1428.4, 1492.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("615.5, 615.5, 615.5, 647.7, 712.0", \ + "775.9, 775.9, 775.9, 808.1, 872.4", \ + "1088.8, 1088.8, 1088.8, 1121.0, 1185.3", \ + "1712.7, 1712.7, 1712.7, 1744.9, 1809.2", \ + "2960.8, 2960.8, 2960.8, 2992.9, 3057.3"); + } + } + } + } + + cell (ao2o22_x4) { + area : 0.0 ; + cell_leakage_power : 3.1 ; + leakage_power () { + when : "(i3 & !(i2) & !(i1) & i0)" ; + value : 1.4 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 3.3 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & i3) | (!(i1) & i2))) | (i1 & !(i2) & i3))" ; + value : 2.3 ; + } + leakage_power () { + when : "(!((i0 | i1)) | (!(i2) & !(i3)))" ; + value : 5.4 ; + } + pin (i3) { + direction : input ; + capacitance : 5.89 ; + } + pin (i2) { + direction : input ; + capacitance : 5.81 ; + } + pin (i1) { + direction : input ; + capacitance : 5.68 ; + } + pin (i0) { + direction : input ; + capacitance : 5.55 ; + } + pin (q) { + function : "((i0 | i1) & (i3 | i2))" ; + direction : output ; + capacitance : 4.17 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("50.2, 50.2, 50.2, 54.5, 62.2", \ + "54.6, 54.6, 54.6, 58.9, 67.0", \ + "56.8, 56.8, 56.8, 61.2, 69.4", \ + "54.1, 54.1, 54.1, 58.7, 67.3", \ + "42.9, 42.9, 42.9, 47.5, 56.4"); + } + rise_transition (inslew_load_5x5__3) { + values ("35.1, 35.1, 35.1, 40.5, 51.3", \ + "45.1, 45.1, 45.1, 50.6, 61.3", \ + "63.2, 63.2, 63.2, 68.7, 79.7", \ + "97.8, 97.8, 97.8, 103.2, 114.2", \ + "164.8, 164.8, 164.8, 170.4, 181.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("109.7, 109.7, 109.7, 114.2, 122.3", \ + "121.6, 121.6, 121.6, 126.1, 134.5", \ + "141.9, 141.9, 141.9, 146.4, 155.2", \ + "180.2, 180.2, 180.2, 184.8, 193.8", \ + "255.0, 255.0, 255.0, 259.6, 268.6"); + } + fall_transition (inslew_load_5x5__3) { + values ("66.4, 66.4, 66.4, 69.1, 74.6", \ + "81.8, 81.8, 81.8, 84.6, 90.1", \ + "111.2, 111.2, 111.2, 113.9, 119.5", \ + "169.7, 169.7, 169.7, 172.5, 178.0", \ + "287.2, 287.2, 287.2, 290.0, 295.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("43.9, 43.9, 43.9, 48.1, 55.8", \ + "42.8, 42.8, 42.8, 47.1, 55.0", \ + "32.9, 32.9, 32.9, 37.3, 45.5", \ + "4.3, 4.3, 4.3, 8.8, 17.2", \ + "-62.1, -62.1, -62.1, -57.5, -48.7"); + } + rise_transition (inslew_load_5x5__3) { + values ("31.1, 31.1, 31.1, 36.6, 47.3", \ + "38.6, 38.6, 38.6, 44.1, 54.8", \ + "51.6, 51.6, 51.6, 57.2, 68.0", \ + "75.4, 75.4, 75.4, 80.8, 91.8", \ + "120.5, 120.5, 120.5, 126.0, 136.9"); + } + cell_fall (inslew_load_5x5__3) { + values ("96.2, 96.2, 96.2, 100.6, 108.5", \ + "118.6, 118.6, 118.6, 123.2, 131.4", \ + "155.5, 155.5, 155.5, 160.1, 168.8", \ + "222.5, 222.5, 222.5, 227.1, 236.1", \ + "351.9, 351.9, 351.9, 356.5, 365.6"); + } + fall_transition (inslew_load_5x5__3) { + values ("53.4, 53.4, 53.4, 56.1, 61.7", \ + "71.3, 71.3, 71.3, 74.0, 79.5", \ + "103.6, 103.6, 103.6, 106.3, 111.8", \ + "166.7, 166.7, 166.7, 169.4, 174.9", \ + "291.8, 291.8, 291.8, 294.5, 300.1"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("48.4, 48.4, 48.4, 52.7, 60.4", \ + "44.3, 44.3, 44.3, 48.6, 56.6", \ + "29.4, 29.4, 29.4, 33.7, 41.9", \ + "-9.8, -9.8, -9.8, -5.3, 3.1", \ + "-99.2, -99.2, -99.2, -94.6, -85.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("36.8, 36.8, 36.8, 42.2, 53.0", \ + "42.8, 42.8, 42.8, 48.3, 59.1", \ + "53.9, 53.9, 53.9, 59.5, 70.3", \ + "74.2, 74.2, 74.2, 79.6, 90.6", \ + "112.1, 112.1, 112.1, 117.6, 128.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("117.7, 117.7, 117.7, 122.2, 130.3", \ + "146.6, 146.6, 146.6, 151.2, 159.7", \ + "195.3, 195.3, 195.3, 199.9, 208.8", \ + "285.5, 285.5, 285.5, 290.1, 299.2", \ + "460.8, 460.8, 460.8, 465.4, 474.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("66.5, 66.5, 66.5, 69.2, 74.7", \ + "87.3, 87.3, 87.3, 90.1, 95.6", \ + "125.9, 125.9, 125.9, 128.7, 134.3", \ + "199.9, 199.9, 199.9, 202.6, 208.1", \ + "347.5, 347.5, 347.5, 350.3, 355.8"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("54.1, 54.1, 54.1, 58.5, 66.4", \ + "54.2, 54.2, 54.2, 58.5, 66.7", \ + "48.9, 48.9, 48.9, 53.3, 61.5", \ + "30.9, 30.9, 30.9, 35.5, 44.1", \ + "-11.9, -11.9, -11.9, -7.4, 1.5"); + } + rise_transition (inslew_load_5x5__3) { + values ("40.7, 40.7, 40.7, 46.2, 56.9", \ + "48.8, 48.8, 48.8, 54.3, 65.1", \ + "64.2, 64.2, 64.2, 69.7, 80.6", \ + "93.8, 93.8, 93.8, 99.2, 110.2", \ + "150.9, 150.9, 150.9, 156.6, 167.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("133.3, 133.3, 133.3, 137.9, 146.3", \ + "152.6, 152.6, 152.6, 157.2, 165.9", \ + "187.1, 187.1, 187.1, 191.7, 200.6", \ + "253.1, 253.1, 253.1, 257.7, 266.7", \ + "384.0, 384.0, 384.0, 388.7, 397.8"); + } + fall_transition (inslew_load_5x5__3) { + values ("80.8, 80.8, 80.8, 83.6, 89.0", \ + "100.4, 100.4, 100.4, 103.1, 108.6", \ + "137.4, 137.4, 137.4, 140.1, 145.7", \ + "210.8, 210.8, 210.8, 213.6, 219.1", \ + "358.1, 358.1, 358.1, 360.9, 366.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("511.0, 511.0, 511.0, 563.1, 667.5", \ + "618.8, 618.8, 618.8, 670.9, 775.3", \ + "826.1, 826.1, 826.1, 878.3, 982.6", \ + "1232.2, 1232.2, 1232.2, 1284.4, 1388.7", \ + "2036.8, 2036.8, 2036.8, 2089.0, 2193.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("930.4, 930.4, 930.4, 982.6, 1086.9", \ + "1128.3, 1128.3, 1128.3, 1180.5, 1284.9", \ + "1511.9, 1511.9, 1511.9, 1564.1, 1668.4", \ + "2278.2, 2278.2, 2278.2, 2330.3, 2434.7", \ + "3813.0, 3813.0, 3813.0, 3865.2, 3969.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("443.3, 443.3, 443.3, 495.5, 599.8", \ + "512.6, 512.6, 512.6, 564.7, 669.1", \ + "642.0, 642.0, 642.0, 694.2, 798.6", \ + "889.2, 889.2, 889.2, 941.3, 1045.7", \ + "1371.6, 1371.6, 1371.6, 1423.8, 1528.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("760.3, 760.3, 760.3, 812.5, 916.9", \ + "976.0, 976.0, 976.0, 1028.2, 1132.6", \ + "1378.9, 1378.9, 1378.9, 1431.1, 1535.5", \ + "2172.1, 2172.1, 2172.1, 2224.3, 2328.6", \ + "3749.3, 3749.3, 3749.3, 3801.5, 3905.8"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("542.7, 542.7, 542.7, 594.8, 699.2", \ + "601.1, 601.1, 601.1, 653.3, 757.7", \ + "712.9, 712.9, 712.9, 765.1, 869.5", \ + "926.0, 926.0, 926.0, 978.1, 1082.5", \ + "1338.2, 1338.2, 1338.2, 1390.4, 1494.7"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("943.3, 943.3, 943.3, 995.4, 1099.8", \ + "1198.9, 1198.9, 1198.9, 1251.1, 1355.5", \ + "1684.2, 1684.2, 1684.2, 1736.3, 1840.7", \ + "2626.7, 2626.7, 2626.7, 2678.9, 2783.2", \ + "4510.3, 4510.3, 4510.3, 4562.5, 4666.9"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__3) { + values ("609.3, 609.3, 609.3, 661.5, 765.8", \ + "701.8, 701.8, 701.8, 754.0, 858.3", \ + "883.2, 883.2, 883.2, 935.4, 1039.7", \ + "1239.7, 1239.7, 1239.7, 1291.9, 1396.2", \ + "1944.9, 1944.9, 1944.9, 1997.1, 2101.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1130.3, 1130.3, 1130.3, 1182.4, 1286.8", \ + "1383.7, 1383.7, 1383.7, 1435.9, 1540.2", \ + "1872.6, 1872.6, 1872.6, 1924.8, 2029.2", \ + "2846.1, 2846.1, 2846.1, 2898.3, 3002.6", \ + "4795.4, 4795.4, 4795.4, 4847.6, 4952.0"); + } + } + } + } + + cell (buf_x2) { + area : 0.0 ; + cell_leakage_power : 4.6 ; + leakage_power () { + when : "i" ; + value : 4.9 ; + } + leakage_power () { + when : "!(i)" ; + value : 4.4 ; + } + pin (i) { + direction : input ; + capacitance : 3.37 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 2.57 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("32.3, 32.3, 32.3, 37.2, 45.8", \ + "30.3, 30.3, 30.3, 35.4, 44.4", \ + "20.3, 20.3, 20.3, 25.5, 35.1", \ + "-5.7, -5.7, -5.7, -0.3, 9.7", \ + "-63.1, -63.1, -63.1, -57.5, -46.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("23.5, 23.5, 23.5, 30.2, 43.2", \ + "32.1, 32.1, 32.1, 38.8, 51.8", \ + "46.8, 46.8, 46.8, 53.5, 66.7", \ + "73.5, 73.5, 73.5, 80.3, 93.7", \ + "125.2, 125.2, 125.2, 132.0, 145.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("63.3, 63.3, 63.3, 68.3, 77.9", \ + "80.6, 80.6, 80.6, 85.8, 95.3", \ + "109.3, 109.3, 109.3, 114.8, 124.9", \ + "162.5, 162.5, 162.5, 168.1, 179.0", \ + "265.8, 265.8, 265.8, 271.5, 282.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("39.6, 39.6, 39.6, 43.0, 49.4", \ + "55.4, 55.4, 55.4, 58.8, 65.5", \ + "85.2, 85.2, 85.2, 88.6, 95.2", \ + "143.7, 143.7, 143.7, 147.1, 153.8", \ + "260.1, 260.1, 260.1, 263.4, 270.0"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__0) { + values ("199.8, 199.8, 199.8, 231.9, 296.3", \ + "242.9, 242.9, 242.9, 275.1, 339.4", \ + "324.9, 324.9, 324.9, 357.1, 421.4", \ + "484.5, 484.5, 484.5, 516.7, 581.0", \ + "800.0, 800.0, 800.0, 832.2, 896.5"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("324.4, 324.4, 324.4, 356.6, 420.9", \ + "434.0, 434.0, 434.0, 466.2, 530.6", \ + "646.4, 646.4, 646.4, 678.6, 742.9", \ + "1066.8, 1066.8, 1066.8, 1099.0, 1163.3", \ + "1905.1, 1905.1, 1905.1, 1937.3, 2001.7"); + } + } + } + } + + cell (buf_x4) { + area : 0.0 ; + cell_leakage_power : 3 ; + leakage_power () { + when : "i" ; + value : 1 ; + } + leakage_power () { + when : "!(i)" ; + value : 5 ; + } + pin (i) { + direction : input ; + capacitance : 4.28 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 4.05 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("49.5, 49.5, 49.5, 53.8, 61.6", \ + "55.2, 55.2, 55.2, 59.7, 67.7", \ + "60.2, 60.2, 60.2, 64.7, 73.0", \ + "63.3, 63.3, 63.3, 67.9, 76.7", \ + "63.6, 63.6, 63.6, 68.2, 77.5"); + } + rise_transition (inslew_load_5x5__9) { + values ("29.9, 29.9, 29.9, 35.4, 46.2", \ + "40.3, 40.3, 40.3, 45.7, 56.6", \ + "59.0, 59.0, 59.0, 64.5, 75.5", \ + "94.5, 94.5, 94.5, 100.0, 111.0", \ + "163.5, 163.5, 163.5, 169.2, 180.2"); + } + cell_fall (inslew_load_5x5__9) { + values ("58.5, 58.5, 58.5, 62.9, 71.0", \ + "68.0, 68.0, 68.0, 72.2, 80.4", \ + "80.5, 80.5, 80.5, 85.0, 93.2", \ + "99.4, 99.4, 99.4, 104.1, 112.9", \ + "132.4, 132.4, 132.4, 137.1, 146.3"); + } + fall_transition (inslew_load_5x5__9) { + values ("34.9, 34.9, 34.9, 37.8, 43.2", \ + "45.4, 45.4, 45.4, 48.3, 53.8", \ + "65.4, 65.4, 65.4, 68.1, 73.7", \ + "104.2, 104.2, 104.2, 107.0, 112.5", \ + "181.1, 181.1, 181.1, 183.8, 189.5"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__9) { + values ("408.7, 408.7, 408.7, 459.4, 560.8", \ + "505.8, 505.8, 505.8, 556.5, 657.8", \ + "692.3, 692.3, 692.3, 743.0, 844.4", \ + "1056.8, 1056.8, 1056.8, 1107.5, 1208.9", \ + "1778.2, 1778.2, 1778.2, 1828.9, 1930.3"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("528.3, 528.3, 528.3, 579.0, 680.4", \ + "658.1, 658.1, 658.1, 708.8, 810.1", \ + "909.5, 909.5, 909.5, 960.2, 1061.5", \ + "1405.9, 1405.9, 1405.9, 1456.5, 1557.9", \ + "2393.6, 2393.6, 2393.6, 2444.3, 2545.6"); + } + } + } + } + + cell (buf_x8) { + area : 0.0 ; + cell_leakage_power : 9.9 ; + leakage_power () { + when : "i" ; + value : 4.4 ; + } + leakage_power () { + when : "!(i)" ; + value : 15 ; + } + pin (i) { + direction : input ; + capacitance : 7.17 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 8.06 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__10) { + values ("50.9, 50.9, 50.9, 55.1, 62.5", \ + "57.2, 57.2, 57.2, 61.4, 69.1", \ + "62.9, 62.9, 62.9, 67.2, 75.1", \ + "67.2, 67.2, 67.2, 71.6, 80.0", \ + "70.6, 70.6, 70.6, 74.9, 83.5"); + } + rise_transition (inslew_load_5x5__10) { + values ("31.9, 31.9, 31.9, 37.2, 47.6", \ + "43.0, 43.0, 43.0, 48.3, 58.7", \ + "62.9, 62.9, 62.9, 68.2, 78.7", \ + "100.8, 100.8, 100.8, 106.0, 116.5", \ + "174.0, 174.0, 174.0, 179.4, 190.1"); + } + cell_fall (inslew_load_5x5__10) { + values ("59.8, 59.8, 59.8, 63.7, 71.5", \ + "69.0, 69.0, 69.0, 73.1, 80.7", \ + "81.3, 81.3, 81.3, 85.6, 93.4", \ + "99.5, 99.5, 99.5, 103.9, 112.4", \ + "131.3, 131.3, 131.3, 135.7, 144.4"); + } + fall_transition (inslew_load_5x5__10) { + values ("36.1, 36.1, 36.1, 38.8, 43.8", \ + "47.2, 47.2, 47.2, 49.8, 55.1", \ + "68.1, 68.1, 68.1, 70.7, 75.9", \ + "109.0, 109.0, 109.0, 111.6, 116.7", \ + "190.0, 190.0, 190.0, 192.5, 197.7"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__10) { + values ("853.0, 853.0, 853.0, 953.8, 1155.4", \ + "1060.1, 1060.1, 1060.1, 1160.9, 1362.5", \ + "1457.8, 1457.8, 1457.8, 1558.6, 1760.2", \ + "2234.4, 2234.4, 2234.4, 2335.1, 2536.7", \ + "3770.1, 3770.1, 3770.1, 3870.9, 4072.4"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("1104.7, 1104.7, 1104.7, 1205.4, 1407.0", \ + "1382.7, 1382.7, 1382.7, 1483.5, 1685.1", \ + "1920.1, 1920.1, 1920.1, 2020.9, 2222.5", \ + "2982.0, 2982.0, 2982.0, 3082.7, 3284.3", \ + "5093.9, 5093.9, 5093.9, 5194.6, 5396.2"); + } + } + } + } + + cell (inv_x1) { + area : 0.0 ; + cell_leakage_power : 2.2 ; + leakage_power () { + when : "i" ; + value : 4.4 ; + } + leakage_power () { + when : "!(i)" ; + value : 0.0001 ; + } + pin (i) { + direction : input ; + capacitance : 6.41 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 2.57 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__0) { + values ("12.5, 12.5, 12.5, 17.6, 26.9", \ + "16.7, 16.7, 16.7, 22.1, 32.3", \ + "23.9, 23.9, 23.9, 29.5, 40.3", \ + "37.6, 37.6, 37.6, 43.4, 54.6", \ + "64.7, 64.7, 64.7, 70.6, 82.0"); + } + rise_transition (inslew_load_5x5__0) { + values ("35.0, 35.0, 35.0, 41.7, 55.0", \ + "64.2, 64.2, 64.2, 71.1, 84.6", \ + "121.0, 121.0, 121.0, 127.9, 141.6", \ + "233.7, 233.7, 233.7, 240.6, 254.5", \ + "458.6, 458.6, 458.6, 465.6, 479.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("5.7, 5.7, 5.7, 10.5, 18.7", \ + "4.6, 4.6, 4.6, 9.8, 19.1", \ + "1.8, 1.8, 1.8, 7.2, 17.4", \ + "-4.1, -4.1, -4.1, 1.3, 12.0", \ + "-16.2, -16.2, -16.2, -10.6, 0.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("16.7, 16.7, 16.7, 20.2, 26.6", \ + "32.2, 32.2, 32.2, 35.8, 42.5", \ + "62.3, 62.3, 62.3, 66.0, 73.1", \ + "122.3, 122.3, 122.3, 126.0, 133.3", \ + "241.9, 241.9, 241.9, 245.6, 253.1"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__0) { + values ("132.2, 132.2, 132.2, 164.4, 228.7", \ + "230.5, 230.5, 230.5, 262.7, 327.0", \ + "427.0, 427.0, 427.0, 459.2, 523.5", \ + "820.1, 820.1, 820.1, 852.3, 916.6", \ + "1606.2, 1606.2, 1606.2, 1638.4, 1702.7"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("103.8, 103.8, 103.8, 136.0, 200.3", \ + "177.3, 177.3, 177.3, 209.5, 273.8", \ + "324.2, 324.2, 324.2, 356.4, 420.7", \ + "618.1, 618.1, 618.1, 650.2, 714.6", \ + "1205.7, 1205.7, 1205.7, 1237.9, 1302.2"); + } + } + } + } + + cell (inv_x2) { + area : 0.0 ; + cell_leakage_power : 2.2 ; + leakage_power () { + when : "i" ; + value : 4.4 ; + } + leakage_power () { + when : "!(i)" ; + value : 0.00017 ; + } + pin (i) { + direction : input ; + capacitance : 7.15 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 2.83 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("16.3, 16.3, 16.3, 21.6, 31.3", \ + "24.5, 24.5, 24.5, 30.1, 40.6", \ + "39.4, 39.4, 39.4, 45.1, 56.2", \ + "68.1, 68.1, 68.1, 73.9, 85.4", \ + "125.1, 125.1, 125.1, 131.0, 142.7"); + } + rise_transition (inslew_load_5x5__11) { + values ("39.2, 39.2, 39.2, 46.6, 61.0", \ + "73.6, 73.6, 73.6, 81.0, 95.7", \ + "139.8, 139.8, 139.8, 147.3, 162.1", \ + "271.0, 271.0, 271.0, 278.5, 293.5", \ + "532.8, 532.8, 532.8, 540.3, 555.4"); + } + cell_fall (inslew_load_5x5__11) { + values ("2.3, 2.3, 2.3, 6.9, 14.6", \ + "-2.0, -2.0, -2.0, 3.0, 12.0", \ + "-11.2, -11.2, -11.2, -5.9, 4.0", \ + "-30.0, -30.0, -30.0, -24.5, -13.8", \ + "-67.6, -67.6, -67.6, -62.0, -51.0"); + } + fall_transition (inslew_load_5x5__11) { + values ("14.1, 14.1, 14.1, 17.2, 23.0", \ + "26.6, 26.6, 26.6, 30.0, 36.1", \ + "51.4, 51.4, 51.4, 54.8, 61.3", \ + "100.5, 100.5, 100.5, 104.0, 110.9", \ + "198.7, 198.7, 198.7, 202.2, 209.3"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__11) { + values ("157.0, 157.0, 157.0, 192.4, 263.1", \ + "276.6, 276.6, 276.6, 311.9, 382.6", \ + "515.7, 515.7, 515.7, 551.0, 621.7", \ + "993.8, 993.8, 993.8, 1029.2, 1099.9", \ + "1950.2, 1950.2, 1950.2, 1985.5, 2056.2"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("99.3, 99.3, 99.3, 134.7, 205.4", \ + "165.4, 165.4, 165.4, 200.7, 271.4", \ + "297.5, 297.5, 297.5, 332.9, 403.6", \ + "561.9, 561.9, 561.9, 597.2, 667.9", \ + "1090.5, 1090.5, 1090.5, 1125.9, 1196.6"); + } + } + } + } + + cell (inv_x4) { + area : 0.0 ; + cell_leakage_power : 2.7 ; + leakage_power () { + when : "i" ; + value : 5.4 ; + } + leakage_power () { + when : "!(i)" ; + value : 0.00065 ; + } + pin (i) { + direction : input ; + capacitance : 13.06 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 4.17 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("11.5, 11.5, 11.5, 15.8, 23.5", \ + "15.7, 15.7, 15.7, 20.1, 28.5", \ + "22.8, 22.8, 22.8, 27.4, 36.3", \ + "36.5, 36.5, 36.5, 41.2, 50.4", \ + "63.7, 63.7, 63.7, 68.4, 77.7"); + } + rise_transition (inslew_load_5x5__3) { + values ("33.6, 33.6, 33.6, 39.2, 50.0", \ + "62.9, 62.9, 62.9, 68.5, 79.5", \ + "119.6, 119.6, 119.6, 125.3, 136.5", \ + "232.3, 232.3, 232.3, 238.0, 249.3", \ + "457.2, 457.2, 457.2, 462.9, 474.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("4.7, 4.7, 4.7, 8.7, 15.8", \ + "3.6, 3.6, 3.6, 7.9, 15.7", \ + "0.7, 0.7, 0.7, 5.2, 13.6", \ + "-5.2, -5.2, -5.2, -0.6, 8.0", \ + "-17.3, -17.3, -17.3, -12.8, -3.8"); + } + fall_transition (inslew_load_5x5__3) { + values ("16.1, 16.1, 16.1, 18.9, 24.3", \ + "31.5, 31.5, 31.5, 34.4, 40.0", \ + "61.6, 61.6, 61.6, 64.6, 70.5", \ + "121.5, 121.5, 121.5, 124.6, 130.6", \ + "241.1, 241.1, 241.1, 244.2, 250.3"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__3) { + values ("252.3, 252.3, 252.3, 304.4, 408.8", \ + "448.8, 448.8, 448.8, 501.0, 605.3", \ + "841.9, 841.9, 841.9, 894.1, 998.4", \ + "1628.0, 1628.0, 1628.0, 1680.2, 1784.5", \ + "3200.3, 3200.3, 3200.3, 3252.5, 3356.8"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("195.5, 195.5, 195.5, 247.7, 352.1", \ + "342.4, 342.4, 342.4, 394.6, 499.0", \ + "636.3, 636.3, 636.3, 688.5, 792.8", \ + "1223.9, 1223.9, 1223.9, 1276.1, 1380.5", \ + "2399.3, 2399.3, 2399.3, 2451.4, 2555.8"); + } + } + } + } + + cell (inv_x8) { + area : 0.0 ; + cell_leakage_power : 7.7 ; + leakage_power () { + when : "i" ; + value : 15 ; + } + leakage_power () { + when : "!(i)" ; + value : 0.00088 ; + } + pin (i) { + direction : input ; + capacitance : 25.27 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 8.06 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("11.3, 11.3, 11.3, 15.5, 23.0", \ + "15.5, 15.5, 15.5, 19.8, 28.0", \ + "22.7, 22.7, 22.7, 27.1, 35.7", \ + "36.4, 36.4, 36.4, 40.9, 49.8", \ + "63.5, 63.5, 63.5, 68.0, 77.1"); + } + rise_transition (inslew_load_5x5__10) { + values ("33.5, 33.5, 33.5, 38.8, 49.3", \ + "62.7, 62.7, 62.7, 68.1, 78.7", \ + "119.4, 119.4, 119.4, 124.9, 135.7", \ + "232.1, 232.1, 232.1, 237.6, 248.5", \ + "457.0, 457.0, 457.0, 462.5, 473.5"); + } + cell_fall (inslew_load_5x5__10) { + values ("4.5, 4.5, 4.5, 8.5, 15.3", \ + "3.4, 3.4, 3.4, 7.6, 15.2", \ + "0.6, 0.6, 0.6, 4.9, 13.1", \ + "-5.3, -5.3, -5.3, -1.0, 7.5", \ + "-17.5, -17.5, -17.5, -13.1, -4.4"); + } + fall_transition (inslew_load_5x5__10) { + values ("15.9, 15.9, 15.9, 18.7, 23.9", \ + "31.4, 31.4, 31.4, 34.2, 39.6", \ + "61.5, 61.5, 61.5, 64.4, 70.1", \ + "121.4, 121.4, 121.4, 124.4, 130.2", \ + "241.0, 241.0, 241.0, 244.0, 249.9"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__10) { + values ("501.0, 501.0, 501.0, 601.7, 803.3", \ + "894.0, 894.0, 894.0, 994.8, 1196.4", \ + "1680.2, 1680.2, 1680.2, 1781.0, 1982.5", \ + "3252.5, 3252.5, 3252.5, 3353.2, 3554.8", \ + "6397.0, 6397.0, 6397.0, 6497.8, 6699.4"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("387.5, 387.5, 387.5, 488.3, 689.8", \ + "681.3, 681.3, 681.3, 782.1, 983.6", \ + "1269.0, 1269.0, 1269.0, 1369.8, 1571.3", \ + "2444.3, 2444.3, 2444.3, 2545.1, 2746.6", \ + "4795.0, 4795.0, 4795.0, 4895.7, 5097.3"); + } + } + } + } + + cell (mx2_x2) { + area : 0.0 ; + cell_leakage_power : 3.5 ; + leakage_power () { + when : "(cmd & i1)" ; + value : 2.5 ; + } + leakage_power () { + when : "(cmd & !(i1))" ; + value : 5.5 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(cmd) & !(i0))" ; + value : 4.4 ; + } + pin (i1) { + direction : input ; + capacitance : 4.34 ; + } + pin (i0) { + direction : input ; + capacitance : 4.01 ; + } + pin (cmd) { + direction : input ; + capacitance : 7.94 ; + } + pin (q) { + function : "((i1 & (i0 | cmd)) | (i0 & !(cmd)))" ; + direction : output ; + capacitance : 2.57 ; + timing (maxd_q_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("47.2, 47.2, 47.2, 52.3, 61.4", \ + "49.6, 49.6, 49.6, 54.9, 64.3", \ + "48.1, 48.1, 48.1, 53.4, 63.3", \ + "38.3, 38.3, 38.3, 43.8, 54.2", \ + "13.1, 13.1, 13.1, 18.6, 29.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("33.3, 33.3, 33.3, 40.1, 53.2", \ + "42.8, 42.8, 42.8, 49.5, 62.7", \ + "59.5, 59.5, 59.5, 66.3, 79.6", \ + "91.2, 91.2, 91.2, 97.9, 111.4", \ + "152.6, 152.6, 152.6, 159.6, 173.0"); + } + cell_fall (inslew_load_5x5__0) { + values ("70.3, 70.3, 70.3, 75.3, 84.9", \ + "83.4, 83.4, 83.4, 88.6, 98.2", \ + "103.7, 103.7, 103.7, 109.2, 119.2", \ + "139.0, 139.0, 139.0, 144.6, 155.4", \ + "205.7, 205.7, 205.7, 211.3, 222.4"); + } + fall_transition (inslew_load_5x5__0) { + values ("40.7, 40.7, 40.7, 44.2, 50.7", \ + "54.1, 54.1, 54.1, 57.5, 64.3", \ + "79.2, 79.2, 79.2, 82.7, 89.4", \ + "128.3, 128.3, 128.3, 131.8, 138.6", \ + "225.6, 225.6, 225.6, 229.1, 235.9"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("56.2, 56.2, 56.2, 61.5, 70.9", \ + "60.7, 60.7, 60.7, 65.9, 75.8", \ + "65.4, 65.4, 65.4, 70.9, 80.9", \ + "69.9, 69.9, 69.9, 75.5, 86.2", \ + "75.2, 75.2, 75.2, 80.8, 91.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("42.6, 42.6, 42.6, 49.4, 62.6", \ + "53.4, 53.4, 53.4, 60.2, 73.5", \ + "74.4, 74.4, 74.4, 81.2, 94.6", \ + "115.2, 115.2, 115.2, 121.9, 135.4", \ + "195.1, 195.1, 195.1, 202.1, 215.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("89.1, 89.1, 89.1, 94.4, 104.0", \ + "98.0, 98.0, 98.0, 103.5, 113.3", \ + "113.4, 113.4, 113.4, 118.9, 129.3", \ + "142.5, 142.5, 142.5, 148.1, 159.1", \ + "199.0, 199.0, 199.0, 204.6, 215.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("57.2, 57.2, 57.2, 60.6, 67.4", \ + "71.2, 71.2, 71.2, 74.7, 81.5", \ + "98.9, 98.9, 98.9, 102.3, 109.1", \ + "154.3, 154.3, 154.3, 157.7, 164.7", \ + "263.6, 263.6, 263.6, 267.0, 273.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("56.2, 56.2, 56.2, 61.5, 70.9", \ + "60.7, 60.7, 60.7, 65.9, 75.8", \ + "65.4, 65.4, 65.4, 70.9, 80.9", \ + "69.9, 69.9, 69.9, 75.5, 86.2", \ + "75.2, 75.2, 75.2, 80.8, 91.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("42.6, 42.6, 42.6, 49.4, 62.6", \ + "53.4, 53.4, 53.4, 60.2, 73.5", \ + "74.4, 74.4, 74.4, 81.2, 94.6", \ + "115.2, 115.2, 115.2, 121.9, 135.4", \ + "195.1, 195.1, 195.1, 202.1, 215.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("89.1, 89.1, 89.1, 94.4, 104.0", \ + "98.0, 98.0, 98.0, 103.5, 113.3", \ + "113.4, 113.4, 113.4, 118.9, 129.3", \ + "142.5, 142.5, 142.5, 148.1, 159.1", \ + "199.0, 199.0, 199.0, 204.6, 215.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("57.2, 57.2, 57.2, 60.6, 67.4", \ + "71.2, 71.2, 71.2, 74.7, 81.5", \ + "98.9, 98.9, 98.9, 102.3, 109.1", \ + "154.3, 154.3, 154.3, 157.7, 164.7", \ + "263.6, 263.6, 263.6, 267.0, 273.7"); + } + } + timing (maxd_q_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__0) { + values ("75.9, 75.9, 75.9, 81.0, 90.2", \ + "84.1, 84.1, 84.1, 89.3, 98.6", \ + "94.5, 94.5, 94.5, 99.8, 109.5", \ + "109.7, 109.7, 109.7, 115.1, 125.1", \ + "134.0, 134.0, 134.0, 139.6, 150.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("34.9, 34.9, 34.9, 41.6, 54.8", \ + "40.7, 40.7, 40.7, 47.4, 60.6", \ + "51.1, 51.1, 51.1, 57.8, 71.1", \ + "70.5, 70.5, 70.5, 77.3, 90.7", \ + "107.8, 107.8, 107.8, 114.6, 128.1"); + } + cell_fall (inslew_load_5x5__0) { + values ("80.2, 80.2, 80.2, 85.4, 94.7", \ + "87.4, 87.4, 87.4, 92.5, 102.0", \ + "95.0, 95.0, 95.0, 100.1, 109.7", \ + "103.8, 103.8, 103.8, 109.1, 118.8", \ + "115.8, 115.8, 115.8, 121.4, 131.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("33.4, 33.4, 33.4, 36.8, 43.3", \ + "38.6, 38.6, 38.6, 42.2, 48.6", \ + "47.3, 47.3, 47.3, 50.7, 57.4", \ + "62.9, 62.9, 62.9, 66.3, 73.2", \ + "93.1, 93.1, 93.1, 96.6, 103.3"); + } + } + internal_power (energy_pos_q_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__0) { + values ("245.6, 245.6, 245.6, 277.7, 342.1", \ + "295.9, 295.9, 295.9, 328.1, 392.4", \ + "392.3, 392.3, 392.3, 424.5, 488.8", \ + "580.7, 580.7, 580.7, 612.9, 677.2", \ + "953.8, 953.8, 953.8, 986.0, 1050.3"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("341.1, 341.1, 341.1, 373.2, 437.6", \ + "433.8, 433.8, 433.8, 466.0, 530.3", \ + "613.5, 613.5, 613.5, 645.6, 710.0", \ + "967.7, 967.7, 967.7, 999.9, 1064.2", \ + "1672.7, 1672.7, 1672.7, 1704.9, 1769.2"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("330.0, 330.0, 330.0, 362.2, 426.5", \ + "401.3, 401.3, 401.3, 433.5, 497.8", \ + "542.7, 542.7, 542.7, 574.8, 639.2", \ + "822.9, 822.9, 822.9, 855.0, 919.4", \ + "1381.3, 1381.3, 1381.3, 1413.5, 1477.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("478.4, 478.4, 478.4, 510.5, 574.9", \ + "586.8, 586.8, 586.8, 618.9, 683.3", \ + "801.2, 801.2, 801.2, 833.4, 897.8", \ + "1231.1, 1231.1, 1231.1, 1263.3, 1327.6", \ + "2084.3, 2084.3, 2084.3, 2116.5, 2180.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("330.0, 330.0, 330.0, 362.2, 426.5", \ + "401.3, 401.3, 401.3, 433.5, 497.8", \ + "542.7, 542.7, 542.7, 574.8, 639.2", \ + "822.9, 822.9, 822.9, 855.0, 919.4", \ + "1381.3, 1381.3, 1381.3, 1413.5, 1477.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("478.4, 478.4, 478.4, 510.5, 574.9", \ + "586.8, 586.8, 586.8, 618.9, 683.3", \ + "801.2, 801.2, 801.2, 833.4, 897.8", \ + "1231.1, 1231.1, 1231.1, 1263.3, 1327.6", \ + "2084.3, 2084.3, 2084.3, 2116.5, 2180.8"); + } + } + internal_power (energy_neg_q_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__0) { + values ("368.9, 368.9, 368.9, 401.1, 465.5", \ + "447.3, 447.3, 447.3, 479.4, 543.8", \ + "599.9, 599.9, 599.9, 632.1, 696.4", \ + "901.8, 901.8, 901.8, 934.0, 998.3", \ + "1501.9, 1501.9, 1501.9, 1534.1, 1598.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("394.7, 394.7, 394.7, 426.9, 491.2", \ + "465.4, 465.4, 465.4, 497.5, 561.9", \ + "597.4, 597.4, 597.4, 629.6, 693.9", \ + "854.5, 854.5, 854.5, 886.7, 951.0", \ + "1363.9, 1363.9, 1363.9, 1396.0, 1460.4"); + } + } + } + } + + cell (mx2_x4) { + area : 0.0 ; + cell_leakage_power : 3.9 ; + leakage_power () { + when : "(cmd & i1)" ; + value : 2.5 ; + } + leakage_power () { + when : "(cmd & !(i1))" ; + value : 6.4 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(cmd) & !(i0))" ; + value : 5.4 ; + } + pin (i1) { + direction : input ; + capacitance : 4.30 ; + } + pin (i0) { + direction : input ; + capacitance : 3.93 ; + } + pin (cmd) { + direction : input ; + capacitance : 8.01 ; + } + pin (q) { + function : "((i0 & (i1 | !(cmd))) | (i1 & cmd))" ; + direction : output ; + capacitance : 4.17 ; + timing (maxd_q_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("68.5, 68.5, 68.5, 72.8, 80.9", \ + "74.1, 74.1, 74.1, 78.5, 86.7", \ + "76.7, 76.7, 76.7, 81.2, 89.6", \ + "71.2, 71.2, 71.2, 75.8, 84.6", \ + "50.1, 50.1, 50.1, 54.7, 63.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("46.9, 46.9, 46.9, 52.4, 63.1", \ + "56.3, 56.3, 56.3, 61.8, 72.6", \ + "73.8, 73.8, 73.8, 79.2, 90.2", \ + "106.4, 106.4, 106.4, 111.9, 122.8", \ + "168.9, 168.9, 168.9, 174.6, 185.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("103.9, 103.9, 103.9, 108.3, 116.3", \ + "118.8, 118.8, 118.8, 123.4, 131.6", \ + "142.1, 142.1, 142.1, 146.7, 155.3", \ + "181.0, 181.0, 181.0, 185.6, 194.5", \ + "251.5, 251.5, 251.5, 256.1, 265.2"); + } + fall_transition (inslew_load_5x5__3) { + values ("62.1, 62.1, 62.1, 64.8, 70.2", \ + "75.6, 75.6, 75.6, 78.4, 83.8", \ + "101.2, 101.2, 101.2, 103.9, 109.3", \ + "151.7, 151.7, 151.7, 154.4, 159.9", \ + "251.6, 251.6, 251.6, 254.3, 259.7"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("75.6, 75.6, 75.6, 80.0, 88.1", \ + "81.6, 81.6, 81.6, 86.0, 94.3", \ + "88.4, 88.4, 88.4, 92.9, 101.5", \ + "95.4, 95.4, 95.4, 100.0, 108.9", \ + "103.2, 103.2, 103.2, 107.8, 116.7"); + } + rise_transition (inslew_load_5x5__3) { + values ("55.7, 55.7, 55.7, 61.2, 72.0", \ + "66.5, 66.5, 66.5, 71.9, 82.9", \ + "87.6, 87.6, 87.6, 93.1, 104.0", \ + "128.8, 128.8, 128.8, 134.5, 145.3", \ + "209.8, 209.8, 209.8, 215.4, 226.7"); + } + cell_fall (inslew_load_5x5__3) { + values ("121.5, 121.5, 121.5, 126.0, 134.3", \ + "131.0, 131.0, 131.0, 135.6, 144.1", \ + "147.6, 147.6, 147.6, 152.2, 161.0", \ + "178.6, 178.6, 178.6, 183.2, 192.1", \ + "237.8, 237.8, 237.8, 242.4, 251.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("78.5, 78.5, 78.5, 81.3, 86.7", \ + "92.7, 92.7, 92.7, 95.4, 100.8", \ + "120.6, 120.6, 120.6, 123.3, 128.8", \ + "177.0, 177.0, 177.0, 179.7, 185.2", \ + "290.7, 290.7, 290.7, 293.3, 298.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("75.6, 75.6, 75.6, 80.0, 88.1", \ + "81.6, 81.6, 81.6, 86.0, 94.3", \ + "88.4, 88.4, 88.4, 92.9, 101.5", \ + "95.4, 95.4, 95.4, 100.0, 108.9", \ + "103.2, 103.2, 103.2, 107.8, 116.7"); + } + rise_transition (inslew_load_5x5__3) { + values ("55.7, 55.7, 55.7, 61.2, 72.0", \ + "66.5, 66.5, 66.5, 71.9, 82.9", \ + "87.6, 87.6, 87.6, 93.1, 104.0", \ + "128.8, 128.8, 128.8, 134.5, 145.3", \ + "209.8, 209.8, 209.8, 215.4, 226.7"); + } + cell_fall (inslew_load_5x5__3) { + values ("121.5, 121.5, 121.5, 126.0, 134.3", \ + "131.0, 131.0, 131.0, 135.6, 144.1", \ + "147.6, 147.6, 147.6, 152.2, 161.0", \ + "178.6, 178.6, 178.6, 183.2, 192.1", \ + "237.8, 237.8, 237.8, 242.4, 251.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("78.5, 78.5, 78.5, 81.3, 86.7", \ + "92.7, 92.7, 92.7, 95.4, 100.8", \ + "120.6, 120.6, 120.6, 123.3, 128.8", \ + "177.0, 177.0, 177.0, 179.7, 185.2", \ + "290.7, 290.7, 290.7, 293.3, 298.7"); + } + } + timing (maxd_q_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("96.9, 96.9, 96.9, 101.2, 109.4", \ + "106.9, 106.9, 106.9, 111.2, 119.4", \ + "120.2, 120.2, 120.2, 124.6, 132.8", \ + "138.9, 138.9, 138.9, 143.4, 152.0", \ + "167.2, 167.2, 167.2, 171.8, 180.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("48.2, 48.2, 48.2, 53.7, 64.4", \ + "53.9, 53.9, 53.9, 59.5, 70.3", \ + "64.6, 64.6, 64.6, 70.1, 81.0", \ + "84.7, 84.7, 84.7, 90.1, 101.1", \ + "122.8, 122.8, 122.8, 128.4, 139.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("112.5, 112.5, 112.5, 116.9, 124.7", \ + "120.1, 120.1, 120.1, 124.6, 132.5", \ + "128.8, 128.8, 128.8, 133.2, 141.4", \ + "139.6, 139.6, 139.6, 144.2, 152.6", \ + "154.6, 154.6, 154.6, 159.2, 167.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("54.9, 54.9, 54.9, 57.6, 63.1", \ + "60.1, 60.1, 60.1, 62.7, 68.2", \ + "68.6, 68.6, 68.6, 71.3, 76.7", \ + "84.4, 84.4, 84.4, 87.1, 92.5", \ + "115.3, 115.3, 115.3, 118.0, 123.5"); + } + } + internal_power (energy_pos_q_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("520.7, 520.7, 520.7, 572.9, 677.3", \ + "602.0, 602.0, 602.0, 654.1, 758.5", \ + "756.5, 756.5, 756.5, 808.7, 913.0", \ + "1053.0, 1053.0, 1053.0, 1105.2, 1209.6", \ + "1632.3, 1632.3, 1632.3, 1684.5, 1788.8"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("778.5, 778.5, 778.5, 830.7, 935.0", \ + "927.5, 927.5, 927.5, 979.7, 1084.0", \ + "1212.9, 1212.9, 1212.9, 1265.1, 1369.4", \ + "1778.7, 1778.7, 1778.7, 1830.9, 1935.3", \ + "2901.3, 2901.3, 2901.3, 2953.4, 3057.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("632.5, 632.5, 632.5, 684.7, 789.0", \ + "738.2, 738.2, 738.2, 790.4, 894.7", \ + "948.0, 948.0, 948.0, 1000.1, 1104.5", \ + "1362.8, 1362.8, 1362.8, 1415.0, 1519.3", \ + "2186.6, 2186.6, 2186.6, 2238.8, 2343.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("983.3, 983.3, 983.3, 1035.5, 1139.9", \ + "1149.5, 1149.5, 1149.5, 1201.7, 1306.0", \ + "1478.9, 1478.9, 1478.9, 1531.0, 1635.4", \ + "2142.9, 2142.9, 2142.9, 2195.1, 2299.4", \ + "3476.5, 3476.5, 3476.5, 3528.7, 3633.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("632.5, 632.5, 632.5, 684.7, 789.0", \ + "738.2, 738.2, 738.2, 790.4, 894.7", \ + "948.0, 948.0, 948.0, 1000.1, 1104.5", \ + "1362.8, 1362.8, 1362.8, 1415.0, 1519.3", \ + "2186.6, 2186.6, 2186.6, 2238.8, 2343.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("983.3, 983.3, 983.3, 1035.5, 1139.9", \ + "1149.5, 1149.5, 1149.5, 1201.7, 1306.0", \ + "1478.9, 1478.9, 1478.9, 1531.0, 1635.4", \ + "2142.9, 2142.9, 2142.9, 2195.1, 2299.4", \ + "3476.5, 3476.5, 3476.5, 3528.7, 3633.0"); + } + } + internal_power (energy_neg_q_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__3) { + values ("645.9, 645.9, 645.9, 698.1, 802.4", \ + "742.9, 742.9, 742.9, 795.1, 899.4", \ + "930.8, 930.8, 930.8, 983.0, 1087.4", \ + "1299.3, 1299.3, 1299.3, 1351.4, 1455.8", \ + "2024.7, 2024.7, 2024.7, 2076.9, 2181.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("801.7, 801.7, 801.7, 853.9, 958.3", \ + "893.0, 893.0, 893.0, 945.1, 1049.5", \ + "1059.4, 1059.4, 1059.4, 1111.6, 1215.9", \ + "1381.6, 1381.6, 1381.6, 1433.8, 1538.1", \ + "2020.0, 2020.0, 2020.0, 2072.2, 2176.5"); + } + } + } + } + + cell (mx3_x2) { + area : 0.0 ; + cell_leakage_power : 3.5 ; + leakage_power () { + when : "(cmd0 & cmd1 & i0 & i1)" ; + value : 4.3 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i0) & i1)" ; + value : 3.9 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i1))" ; + value : 7.1 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & i0 & i2) | (!(cmd0) & cmd1 & i0 & i1 & i2))" ; + value : 3 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0 & cmd1 & !(cmd0))" ; + value : 2.9 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i0) & i2) | (!(cmd0) & cmd1 & i0 & !(i2)))" ; + value : 2.6 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i2)) | (!(cmd0) & cmd1 & !(i0)))" ; + value : 5.8 ; + } + leakage_power () { + when : "(i2 & i1 & i0 & !(cmd1) & !(cmd0))" ; + value : 1.7 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0 & !(cmd1) & !(cmd0))" ; + value : 1.6 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & !(i1))" ; + value : 1.3 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & !(i0))" ; + value : 4.4 ; + } + pin (i2) { + direction : input ; + capacitance : 3.90 ; + } + pin (i1) { + direction : input ; + capacitance : 4.00 ; + } + pin (i0) { + direction : input ; + capacitance : 4.25 ; + } + pin (cmd1) { + direction : input ; + capacitance : 6.82 ; + } + pin (cmd0) { + direction : input ; + capacitance : 6.90 ; + } + pin (q) { + function : "((i0 & ((i1 & (!(cmd0) | i2 | cmd1)) | !(cmd0) | (i2 & !(cmd1)))) | (i1 & cmd0 & (i2 | cmd1)) | (cmd0 & i2 & !(cmd1)))" ; + direction : output ; + capacitance : 3.03 ; + timing (maxd_q_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("85.3, 85.3, 85.3, 91.0, 101.8", \ + "87.8, 87.8, 87.8, 93.6, 104.5", \ + "89.7, 89.7, 89.7, 95.5, 106.7", \ + "88.0, 88.0, 88.0, 93.8, 105.0", \ + "78.3, 78.3, 78.3, 84.3, 95.8"); + } + rise_transition (inslew_load_5x5__12) { + values ("75.8, 75.8, 75.8, 83.6, 99.1", \ + "87.5, 87.5, 87.5, 95.3, 110.8", \ + "110.5, 110.5, 110.5, 118.4, 133.9", \ + "156.0, 156.0, 156.0, 163.9, 179.5", \ + "245.7, 245.7, 245.7, 253.6, 269.3"); + } + cell_fall (inslew_load_5x5__12) { + values ("109.7, 109.7, 109.7, 114.8, 124.8", \ + "120.2, 120.2, 120.2, 125.3, 135.1", \ + "138.4, 138.4, 138.4, 143.7, 153.7", \ + "171.9, 171.9, 171.9, 177.2, 187.5", \ + "237.4, 237.4, 237.4, 242.8, 253.2"); + } + fall_transition (inslew_load_5x5__12) { + values ("66.2, 66.2, 66.2, 69.8, 75.6", \ + "79.6, 79.6, 79.6, 83.1, 89.5", \ + "105.5, 105.5, 105.5, 108.9, 115.8", \ + "157.3, 157.3, 157.3, 160.7, 167.6", \ + "261.6, 261.6, 261.6, 264.8, 271.4"); + } + } + timing (maxd_q_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("65.0, 65.0, 65.0, 70.7, 81.0", \ + "67.8, 67.8, 67.8, 73.4, 83.9", \ + "63.4, 63.4, 63.4, 69.1, 79.9", \ + "42.7, 42.7, 42.7, 48.4, 59.6", \ + "-10.8, -10.8, -10.8, -4.9, 6.3"); + } + rise_transition (inslew_load_5x5__12) { + values ("52.0, 52.0, 52.0, 59.9, 75.2", \ + "61.5, 61.5, 61.5, 69.3, 84.7", \ + "77.7, 77.7, 77.7, 85.5, 100.9", \ + "107.0, 107.0, 107.0, 114.9, 130.4", \ + "162.3, 162.3, 162.3, 170.2, 185.8"); + } + cell_fall (inslew_load_5x5__12) { + values ("101.7, 101.7, 101.7, 106.7, 116.7", \ + "120.3, 120.3, 120.3, 125.4, 135.3", \ + "148.7, 148.7, 148.7, 153.9, 163.8", \ + "198.2, 198.2, 198.2, 203.5, 213.8", \ + "291.4, 291.4, 291.4, 296.7, 307.2"); + } + fall_transition (inslew_load_5x5__12) { + values ("55.5, 55.5, 55.5, 59.0, 64.6", \ + "69.9, 69.9, 69.9, 73.4, 79.3", \ + "95.9, 95.9, 95.9, 99.4, 106.2", \ + "145.7, 145.7, 145.7, 149.1, 156.0", \ + "244.8, 244.8, 244.8, 248.1, 254.7"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("54.0, 54.0, 54.0, 59.6, 69.6", \ + "55.9, 55.9, 55.9, 61.6, 71.9", \ + "51.8, 51.8, 51.8, 57.5, 68.1", \ + "34.0, 34.0, 34.0, 39.8, 50.9", \ + "-10.8, -10.8, -10.8, -5.0, 6.3"); + } + rise_transition (inslew_load_5x5__12) { + values ("40.7, 40.7, 40.7, 48.5, 63.8", \ + "50.9, 50.9, 50.9, 58.7, 74.0", \ + "68.7, 68.7, 68.7, 76.5, 92.0", \ + "101.0, 101.0, 101.0, 108.8, 124.3", \ + "162.4, 162.4, 162.4, 170.3, 186.0"); + } + cell_fall (inslew_load_5x5__12) { + values ("76.2, 76.2, 76.2, 81.7, 91.0", \ + "90.8, 90.8, 90.8, 95.9, 105.9", \ + "113.8, 113.8, 113.8, 119.0, 128.8", \ + "153.9, 153.9, 153.9, 159.1, 169.3", \ + "229.4, 229.4, 229.4, 234.7, 245.1"); + } + fall_transition (inslew_load_5x5__12) { + values ("41.8, 41.8, 41.8, 44.7, 50.5", \ + "54.3, 54.3, 54.3, 57.7, 63.3", \ + "77.2, 77.2, 77.2, 80.7, 86.9", \ + "122.2, 122.2, 122.2, 125.7, 132.5", \ + "211.8, 211.8, 211.8, 215.0, 221.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("75.8, 75.8, 75.8, 81.5, 92.0", \ + "77.8, 77.8, 77.8, 83.6, 94.3", \ + "75.2, 75.2, 75.2, 81.0, 91.9", \ + "60.2, 60.2, 60.2, 65.9, 77.2", \ + "19.3, 19.3, 19.3, 25.2, 36.5"); + } + rise_transition (inslew_load_5x5__12) { + values ("63.8, 63.8, 63.8, 71.7, 87.0", \ + "73.3, 73.3, 73.3, 81.1, 96.6", \ + "91.3, 91.3, 91.3, 99.1, 114.6", \ + "125.0, 125.0, 125.0, 132.9, 148.4", \ + "189.8, 189.8, 189.8, 197.6, 213.3"); + } + cell_fall (inslew_load_5x5__12) { + values ("133.3, 133.3, 133.3, 138.4, 148.3", \ + "149.8, 149.8, 149.8, 155.0, 164.9", \ + "176.6, 176.6, 176.6, 181.8, 191.9", \ + "225.8, 225.8, 225.8, 231.1, 241.4", \ + "321.7, 321.7, 321.7, 327.0, 337.5"); + } + fall_transition (inslew_load_5x5__12) { + values ("76.1, 76.1, 76.1, 79.6, 85.8", \ + "92.3, 92.3, 92.3, 95.7, 102.5", \ + "121.5, 121.5, 121.5, 124.9, 131.8", \ + "179.0, 179.0, 179.0, 182.3, 189.1", \ + "294.1, 294.1, 294.1, 297.2, 303.8"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("75.8, 75.8, 75.8, 81.5, 92.0", \ + "77.8, 77.8, 77.8, 83.6, 94.3", \ + "75.2, 75.2, 75.2, 81.0, 91.9", \ + "60.2, 60.2, 60.2, 65.9, 77.2", \ + "19.3, 19.3, 19.3, 25.2, 36.5"); + } + rise_transition (inslew_load_5x5__12) { + values ("63.8, 63.8, 63.8, 71.7, 87.0", \ + "73.3, 73.3, 73.3, 81.1, 96.6", \ + "91.3, 91.3, 91.3, 99.1, 114.6", \ + "125.0, 125.0, 125.0, 132.9, 148.4", \ + "189.8, 189.8, 189.8, 197.6, 213.3"); + } + cell_fall (inslew_load_5x5__12) { + values ("133.3, 133.3, 133.3, 138.4, 148.3", \ + "149.8, 149.8, 149.8, 155.0, 164.9", \ + "176.6, 176.6, 176.6, 181.8, 191.9", \ + "225.8, 225.8, 225.8, 231.1, 241.4", \ + "321.7, 321.7, 321.7, 327.0, 337.5"); + } + fall_transition (inslew_load_5x5__12) { + values ("76.1, 76.1, 76.1, 79.6, 85.8", \ + "92.3, 92.3, 92.3, 95.7, 102.5", \ + "121.5, 121.5, 121.5, 124.9, 131.8", \ + "179.0, 179.0, 179.0, 182.3, 189.1", \ + "294.1, 294.1, 294.1, 297.2, 303.8"); + } + } + timing (maxd_q_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("108.1, 108.1, 108.1, 113.7, 124.3", \ + "120.7, 120.7, 120.7, 126.4, 137.0", \ + "139.8, 139.8, 139.8, 145.6, 156.4", \ + "171.8, 171.8, 171.8, 177.6, 188.7", \ + "228.7, 228.7, 228.7, 234.5, 245.8"); + } + rise_transition (inslew_load_5x5__12) { + values ("60.1, 60.1, 60.1, 67.9, 83.2", \ + "68.0, 68.0, 68.0, 75.8, 91.2", \ + "82.9, 82.9, 82.9, 90.7, 106.2", \ + "111.1, 111.1, 111.1, 119.0, 134.5", \ + "166.1, 166.1, 166.1, 173.9, 189.6"); + } + cell_fall (inslew_load_5x5__12) { + values ("165.1, 165.1, 165.1, 170.3, 180.0", \ + "172.7, 172.7, 172.7, 177.9, 187.7", \ + "177.0, 177.0, 177.0, 182.2, 192.2", \ + "177.8, 177.8, 177.8, 183.1, 193.2", \ + "175.0, 175.0, 175.0, 180.3, 190.6"); + } + fall_transition (inslew_load_5x5__12) { + values ("81.4, 81.4, 81.4, 84.9, 91.3", \ + "89.6, 89.6, 89.6, 93.1, 99.7", \ + "101.2, 101.2, 101.2, 104.6, 111.4", \ + "121.6, 121.6, 121.6, 125.0, 131.9", \ + "160.8, 160.8, 160.8, 164.2, 171.1"); + } + } + timing (maxd_q_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("103.9, 103.9, 103.9, 109.5, 120.0", \ + "115.4, 115.4, 115.4, 121.1, 131.6", \ + "131.1, 131.1, 131.1, 136.8, 147.5", \ + "153.6, 153.6, 153.6, 159.4, 170.4", \ + "188.4, 188.4, 188.4, 194.2, 205.4"); + } + rise_transition (inslew_load_5x5__12) { + values ("56.9, 56.9, 56.9, 64.8, 80.1", \ + "63.8, 63.8, 63.8, 71.7, 87.0", \ + "76.1, 76.1, 76.1, 83.9, 99.3", \ + "98.6, 98.6, 98.6, 106.5, 121.9", \ + "141.7, 141.7, 141.7, 149.5, 165.1"); + } + cell_fall (inslew_load_5x5__12) { + values ("116.3, 116.3, 116.3, 121.5, 131.3", \ + "115.5, 115.5, 115.5, 120.7, 130.6", \ + "121.5, 121.5, 121.5, 126.6, 136.7", \ + "124.1, 124.1, 124.1, 129.2, 139.1", \ + "121.6, 121.6, 121.6, 126.9, 136.9"); + } + fall_transition (inslew_load_5x5__12) { + values ("51.6, 51.6, 51.6, 54.9, 60.6", \ + "52.9, 52.9, 52.9, 56.2, 61.9", \ + "61.7, 61.7, 61.7, 65.2, 71.0", \ + "76.4, 76.4, 76.4, 79.9, 86.1", \ + "104.2, 104.2, 104.2, 107.6, 114.5"); + } + } + internal_power (energy_pos_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__12) { + values ("532.0, 532.0, 532.0, 569.9, 645.7", \ + "604.6, 604.6, 604.6, 642.5, 718.4", \ + "749.6, 749.6, 749.6, 787.5, 863.3", \ + "1039.0, 1039.0, 1039.0, 1077.0, 1152.8", \ + "1615.2, 1615.2, 1615.2, 1653.1, 1728.9"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("650.9, 650.9, 650.9, 688.8, 764.6", \ + "773.3, 773.3, 773.3, 811.2, 887.0", \ + "1013.7, 1013.7, 1013.7, 1051.6, 1127.5", \ + "1494.8, 1494.8, 1494.8, 1532.7, 1608.5", \ + "2459.0, 2459.0, 2459.0, 2496.9, 2572.8"); + } + } + internal_power (energy_pos_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__12) { + values ("354.4, 354.4, 354.4, 392.3, 468.1", \ + "399.0, 399.0, 399.0, 436.9, 512.7", \ + "480.3, 480.3, 480.3, 518.2, 594.0", \ + "634.2, 634.2, 634.2, 672.1, 747.9", \ + "932.6, 932.6, 932.6, 970.5, 1046.3"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("470.0, 470.0, 470.0, 507.9, 583.7", \ + "572.8, 572.8, 572.8, 610.7, 686.5", \ + "765.7, 765.7, 765.7, 803.6, 879.4", \ + "1139.3, 1139.3, 1139.3, 1177.2, 1253.0", \ + "1883.9, 1883.9, 1883.9, 1921.8, 1997.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__12) { + values ("322.6, 322.6, 322.6, 360.5, 436.4", \ + "373.9, 373.9, 373.9, 411.8, 487.6", \ + "470.5, 470.5, 470.5, 508.4, 584.2", \ + "655.6, 655.6, 655.6, 693.5, 769.3", \ + "1018.7, 1018.7, 1018.7, 1056.6, 1132.4"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("412.8, 412.8, 412.8, 450.7, 526.5", \ + "516.0, 516.0, 516.0, 553.9, 629.7", \ + "712.1, 712.1, 712.1, 750.0, 825.8", \ + "1100.6, 1100.6, 1100.6, 1138.5, 1214.3", \ + "1873.5, 1873.5, 1873.5, 1911.4, 1987.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__12) { + values ("441.0, 441.0, 441.0, 478.9, 554.7", \ + "491.7, 491.7, 491.7, 529.6, 605.4", \ + "590.5, 590.5, 590.5, 628.4, 704.2", \ + "782.0, 782.0, 782.0, 819.9, 895.8", \ + "1157.9, 1157.9, 1157.9, 1195.8, 1271.6"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("634.9, 634.9, 634.9, 672.8, 748.6", \ + "755.6, 755.6, 755.6, 793.6, 869.4", \ + "982.1, 982.1, 982.1, 1020.1, 1095.9", \ + "1430.1, 1430.1, 1430.1, 1468.0, 1543.8", \ + "2325.9, 2325.9, 2325.9, 2363.8, 2439.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__12) { + values ("441.0, 441.0, 441.0, 478.9, 554.7", \ + "491.7, 491.7, 491.7, 529.6, 605.4", \ + "590.5, 590.5, 590.5, 628.4, 704.2", \ + "782.0, 782.0, 782.0, 819.9, 895.8", \ + "1157.9, 1157.9, 1157.9, 1195.8, 1271.6"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("634.9, 634.9, 634.9, 672.8, 748.6", \ + "755.6, 755.6, 755.6, 793.6, 869.4", \ + "982.1, 982.1, 982.1, 1020.1, 1095.9", \ + "1430.1, 1430.1, 1430.1, 1468.0, 1543.8", \ + "2325.9, 2325.9, 2325.9, 2363.8, 2439.6"); + } + } + internal_power (energy_neg_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__12) { + values ("583.8, 583.8, 583.8, 621.7, 697.5", \ + "672.8, 672.8, 672.8, 710.7, 786.5", \ + "846.1, 846.1, 846.1, 884.0, 959.8", \ + "1187.9, 1187.9, 1187.9, 1225.8, 1301.6", \ + "1867.5, 1867.5, 1867.5, 1905.4, 1981.2"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("773.6, 773.6, 773.6, 811.5, 887.3", \ + "854.2, 854.2, 854.2, 892.1, 967.9", \ + "990.5, 990.5, 990.5, 1028.5, 1104.3", \ + "1248.6, 1248.6, 1248.6, 1286.5, 1362.4", \ + "1755.6, 1755.6, 1755.6, 1793.5, 1869.3"); + } + } + internal_power (energy_neg_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__12) { + values ("475.7, 475.7, 475.7, 513.7, 589.5", \ + "547.8, 547.8, 547.8, 585.7, 661.5", \ + "686.3, 686.3, 686.3, 724.3, 800.1", \ + "957.9, 957.9, 957.9, 995.8, 1071.6", \ + "1495.2, 1495.2, 1495.2, 1533.1, 1608.9"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("518.2, 518.2, 518.2, 556.1, 631.9", \ + "558.4, 558.4, 558.4, 596.3, 672.1", \ + "668.3, 668.3, 668.3, 706.2, 782.0", \ + "872.5, 872.5, 872.5, 910.5, 986.3", \ + "1272.7, 1272.7, 1272.7, 1310.6, 1386.4"); + } + } + } + } + + cell (mx3_x4) { + area : 0.0 ; + cell_leakage_power : 3.8 ; + leakage_power () { + when : "(cmd0 & cmd1 & i0 & i1)" ; + value : 4.3 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i0) & i1)" ; + value : 3.9 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i1))" ; + value : 8.1 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & i0 & i2) | (!(cmd0) & cmd1 & i0 & i1 & i2))" ; + value : 3 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0 & cmd1 & !(cmd0))" ; + value : 2.9 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i0) & i2) | (!(cmd0) & cmd1 & i0 & !(i2)))" ; + value : 2.6 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i2)) | (!(cmd0) & cmd1 & !(i0)))" ; + value : 6.7 ; + } + leakage_power () { + when : "(i2 & i1 & i0 & !(cmd1) & !(cmd0))" ; + value : 1.7 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0 & !(cmd1) & !(cmd0))" ; + value : 1.6 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & !(i1))" ; + value : 1.3 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & !(i0))" ; + value : 5.4 ; + } + pin (i2) { + direction : input ; + capacitance : 4.01 ; + } + pin (i1) { + direction : input ; + capacitance : 3.95 ; + } + pin (i0) { + direction : input ; + capacitance : 4.05 ; + } + pin (cmd1) { + direction : input ; + capacitance : 7.20 ; + } + pin (cmd0) { + direction : input ; + capacitance : 6.93 ; + } + pin (q) { + function : "((i2 & (((i1 | !(cmd1)) & (cmd0 | i0)) | (!(cmd0) & i0))) | (i1 & cmd1 & (cmd0 | i0)) | (!(cmd0) & i0))" ; + direction : output ; + capacitance : 4.42 ; + timing (maxd_q_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__13) { + values ("92.3, 92.3, 92.3, 96.9, 105.6", \ + "93.8, 93.8, 93.8, 98.5, 107.3", \ + "93.8, 93.8, 93.8, 98.5, 107.5", \ + "87.5, 87.5, 87.5, 92.3, 101.5", \ + "67.4, 67.4, 67.4, 72.1, 81.4"); + } + rise_transition (inslew_load_5x5__13) { + values ("77.0, 77.0, 77.0, 82.8, 94.4", \ + "86.3, 86.3, 86.3, 92.1, 103.7", \ + "105.2, 105.2, 105.2, 111.0, 122.6", \ + "143.1, 143.1, 143.1, 148.9, 160.4", \ + "217.7, 217.7, 217.7, 223.7, 235.3"); + } + cell_fall (inslew_load_5x5__13) { + values ("158.6, 158.6, 158.6, 163.3, 172.3", \ + "173.5, 173.5, 173.5, 178.2, 187.3", \ + "200.2, 200.2, 200.2, 204.8, 214.0", \ + "251.1, 251.1, 251.1, 255.2, 264.4", \ + "351.3, 351.3, 351.3, 355.5, 363.7"); + } + fall_transition (inslew_load_5x5__13) { + values ("100.7, 100.7, 100.7, 103.5, 109.0", \ + "117.5, 117.5, 117.5, 120.3, 125.8", \ + "150.1, 150.1, 150.1, 152.9, 158.4", \ + "215.3, 215.3, 215.3, 218.2, 223.9", \ + "346.2, 346.2, 346.2, 349.2, 355.3"); + } + } + timing (maxd_q_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__13) { + values ("77.0, 77.0, 77.0, 81.6, 90.1", \ + "80.7, 80.7, 80.7, 85.3, 93.9", \ + "78.2, 78.2, 78.2, 82.9, 91.6", \ + "58.5, 58.5, 58.5, 63.2, 72.2", \ + "2.5, 2.5, 2.5, 7.3, 16.5"); + } + rise_transition (inslew_load_5x5__13) { + values ("58.0, 58.0, 58.0, 63.9, 75.3", \ + "65.5, 65.5, 65.5, 71.4, 82.8", \ + "79.3, 79.3, 79.3, 85.2, 96.7", \ + "104.4, 104.4, 104.4, 110.2, 121.8", \ + "151.2, 151.2, 151.2, 156.9, 168.5"); + } + cell_fall (inslew_load_5x5__13) { + values ("162.9, 162.9, 162.9, 167.6, 176.6", \ + "186.6, 186.6, 186.6, 191.3, 200.3", \ + "224.7, 224.7, 224.7, 229.4, 238.5", \ + "292.6, 292.6, 292.6, 296.7, 306.0", \ + "420.2, 420.2, 420.2, 424.4, 432.6"); + } + fall_transition (inslew_load_5x5__13) { + values ("96.8, 96.8, 96.8, 99.5, 105.1", \ + "114.5, 114.5, 114.5, 117.3, 122.8", \ + "147.0, 147.0, 147.0, 149.8, 155.3", \ + "209.8, 209.8, 209.8, 212.8, 218.4", \ + "334.5, 334.5, 334.5, 337.5, 343.6"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__13) { + values ("63.9, 63.9, 63.9, 68.4, 76.7", \ + "66.9, 66.9, 66.9, 71.4, 79.9", \ + "63.5, 63.5, 63.5, 68.1, 76.7", \ + "45.0, 45.0, 45.0, 49.7, 58.6", \ + "-4.7, -4.7, -4.7, 0.0, 9.3"); + } + rise_transition (inslew_load_5x5__13) { + values ("44.6, 44.6, 44.6, 50.4, 61.8", \ + "53.0, 53.0, 53.0, 58.8, 70.2", \ + "68.0, 68.0, 68.0, 73.8, 85.3", \ + "95.3, 95.3, 95.3, 101.1, 112.7", \ + "147.0, 147.0, 147.0, 152.8, 164.3"); + } + cell_fall (inslew_load_5x5__13) { + values ("118.3, 118.3, 118.3, 122.9, 131.5", \ + "137.9, 137.9, 137.9, 142.6, 151.4", \ + "169.9, 169.9, 169.9, 174.6, 183.6", \ + "226.1, 226.1, 226.1, 230.7, 239.9", \ + "332.6, 332.6, 332.6, 336.8, 345.2"); + } + fall_transition (inslew_load_5x5__13) { + values ("69.8, 69.8, 69.8, 72.6, 78.1", \ + "85.2, 85.2, 85.2, 88.0, 93.5", \ + "114.3, 114.3, 114.3, 117.1, 122.7", \ + "171.5, 171.5, 171.5, 174.3, 179.9", \ + "284.4, 284.4, 284.4, 287.4, 293.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__13) { + values ("85.0, 85.0, 85.0, 89.5, 98.1", \ + "87.2, 87.2, 87.2, 91.8, 100.5", \ + "84.7, 84.7, 84.7, 89.4, 98.2", \ + "68.4, 68.4, 68.4, 73.1, 82.2", \ + "22.2, 22.2, 22.2, 26.9, 36.2"); + } + rise_transition (inslew_load_5x5__13) { + values ("67.1, 67.1, 67.1, 73.0, 84.5", \ + "74.8, 74.8, 74.8, 80.6, 92.2", \ + "89.8, 89.8, 89.8, 95.6, 107.2", \ + "118.2, 118.2, 118.2, 124.0, 135.6", \ + "172.6, 172.6, 172.6, 178.4, 189.9"); + } + cell_fall (inslew_load_5x5__13) { + values ("200.3, 200.3, 200.3, 205.1, 214.1", \ + "222.3, 222.3, 222.3, 226.9, 236.0", \ + "258.7, 258.7, 258.7, 263.1, 272.4", \ + "328.1, 328.1, 328.1, 332.3, 341.1", \ + "461.7, 461.7, 461.7, 465.9, 474.2"); + } + fall_transition (inslew_load_5x5__13) { + values ("122.4, 122.4, 122.4, 125.2, 130.8", \ + "142.8, 142.8, 142.8, 145.6, 151.1", \ + "179.4, 179.4, 179.4, 182.3, 187.8", \ + "251.5, 251.5, 251.5, 254.5, 260.4", \ + "395.9, 395.9, 395.9, 398.9, 404.9"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__13) { + values ("85.0, 85.0, 85.0, 89.5, 98.1", \ + "87.2, 87.2, 87.2, 91.8, 100.5", \ + "84.7, 84.7, 84.7, 89.4, 98.2", \ + "68.4, 68.4, 68.4, 73.1, 82.2", \ + "22.2, 22.2, 22.2, 26.9, 36.2"); + } + rise_transition (inslew_load_5x5__13) { + values ("67.1, 67.1, 67.1, 73.0, 84.5", \ + "74.8, 74.8, 74.8, 80.6, 92.2", \ + "89.8, 89.8, 89.8, 95.6, 107.2", \ + "118.2, 118.2, 118.2, 124.0, 135.6", \ + "172.6, 172.6, 172.6, 178.4, 189.9"); + } + cell_fall (inslew_load_5x5__13) { + values ("200.3, 200.3, 200.3, 205.1, 214.1", \ + "222.3, 222.3, 222.3, 226.9, 236.0", \ + "258.7, 258.7, 258.7, 263.1, 272.4", \ + "328.1, 328.1, 328.1, 332.3, 341.1", \ + "461.7, 461.7, 461.7, 465.9, 474.2"); + } + fall_transition (inslew_load_5x5__13) { + values ("122.4, 122.4, 122.4, 125.2, 130.8", \ + "142.8, 142.8, 142.8, 145.6, 151.1", \ + "179.4, 179.4, 179.4, 182.3, 187.8", \ + "251.5, 251.5, 251.5, 254.5, 260.4", \ + "395.9, 395.9, 395.9, 398.9, 404.9"); + } + } + timing (maxd_q_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("117.1, 117.1, 117.1, 121.7, 130.2", \ + "131.9, 131.9, 131.9, 136.5, 145.1", \ + "155.3, 155.3, 155.3, 160.0, 168.7", \ + "194.7, 194.7, 194.7, 199.4, 208.4", \ + "265.2, 265.2, 265.2, 270.0, 279.2"); + } + rise_transition (inslew_load_5x5__13) { + values ("60.8, 60.8, 60.8, 66.6, 78.1", \ + "67.8, 67.8, 67.8, 73.6, 85.1", \ + "81.3, 81.3, 81.3, 87.1, 98.7", \ + "107.3, 107.3, 107.3, 113.1, 124.7", \ + "157.9, 157.9, 157.9, 163.7, 175.2"); + } + cell_fall (inslew_load_5x5__13) { + values ("227.1, 227.1, 227.1, 231.9, 241.0", \ + "236.1, 236.1, 236.1, 240.7, 249.8", \ + "239.2, 239.2, 239.2, 243.9, 253.0", \ + "236.6, 236.6, 236.6, 241.1, 250.3", \ + "225.8, 225.8, 225.8, 230.0, 239.1"); + } + fall_transition (inslew_load_5x5__13) { + values ("126.2, 126.2, 126.2, 129.0, 134.5", \ + "136.7, 136.7, 136.7, 139.5, 145.0", \ + "150.4, 150.4, 150.4, 153.2, 158.8", \ + "173.8, 173.8, 173.8, 176.7, 182.2", \ + "218.2, 218.2, 218.2, 221.2, 226.8"); + } + } + timing (maxd_q_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("116.2, 116.2, 116.2, 120.8, 129.4", \ + "128.5, 128.5, 128.5, 133.1, 141.7", \ + "144.9, 144.9, 144.9, 149.5, 158.2", \ + "167.8, 167.8, 167.8, 172.5, 181.4", \ + "201.3, 201.3, 201.3, 206.0, 215.2"); + } + rise_transition (inslew_load_5x5__13) { + values ("61.7, 61.7, 61.7, 67.6, 79.0", \ + "67.4, 67.4, 67.4, 73.3, 84.7", \ + "77.7, 77.7, 77.7, 83.5, 95.1", \ + "96.8, 96.8, 96.8, 102.6, 114.2", \ + "132.9, 132.9, 132.9, 138.7, 150.2"); + } + cell_fall (inslew_load_5x5__13) { + values ("176.1, 176.1, 176.1, 180.7, 189.7", \ + "176.3, 176.3, 176.3, 180.9, 189.9", \ + "185.1, 185.1, 185.1, 189.8, 198.8", \ + "193.5, 193.5, 193.5, 198.2, 207.3", \ + "201.0, 201.0, 201.0, 205.6, 214.8"); + } + fall_transition (inslew_load_5x5__13) { + values ("91.9, 91.9, 91.9, 94.7, 100.3", \ + "93.6, 93.6, 93.6, 96.4, 101.9", \ + "104.4, 104.4, 104.4, 107.2, 112.8", \ + "122.7, 122.7, 122.7, 125.5, 131.0", \ + "157.4, 157.4, 157.4, 160.2, 165.7"); + } + } + internal_power (energy_pos_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__13) { + values ("837.7, 837.7, 837.7, 893.0, 1003.5", \ + "930.8, 930.8, 930.8, 986.1, 1096.6", \ + "1119.5, 1119.5, 1119.5, 1174.8, 1285.4", \ + "1497.8, 1497.8, 1497.8, 1553.1, 1663.6", \ + "2250.1, 2250.1, 2250.1, 2305.4, 2416.0"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("1285.6, 1285.6, 1285.6, 1340.9, 1451.4", \ + "1489.2, 1489.2, 1489.2, 1544.5, 1655.1", \ + "1886.7, 1886.7, 1886.7, 1942.0, 2052.6", \ + "2683.8, 2683.8, 2683.8, 2739.1, 2849.6", \ + "4285.9, 4285.9, 4285.9, 4341.2, 4451.8"); + } + } + internal_power (energy_pos_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__13) { + values ("617.0, 617.0, 617.0, 672.3, 782.9", \ + "678.5, 678.5, 678.5, 733.8, 844.4", \ + "794.8, 794.8, 794.8, 850.0, 960.6", \ + "1010.6, 1010.6, 1010.6, 1065.9, 1176.4", \ + "1422.1, 1422.1, 1422.1, 1477.4, 1588.0"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("1122.7, 1122.7, 1122.7, 1178.0, 1288.6", \ + "1309.8, 1309.8, 1309.8, 1365.1, 1475.7", \ + "1657.7, 1657.7, 1657.7, 1713.0, 1823.6", \ + "2336.8, 2336.8, 2336.8, 2392.1, 2502.7", \ + "3690.0, 3690.0, 3690.0, 3745.3, 3855.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__13) { + values ("535.9, 535.9, 535.9, 591.2, 701.8", \ + "607.8, 607.8, 607.8, 663.1, 773.6", \ + "741.4, 741.4, 741.4, 796.7, 907.3", \ + "993.2, 993.2, 993.2, 1048.5, 1159.1", \ + "1480.1, 1480.1, 1480.1, 1535.4, 1646.0"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("898.9, 898.9, 898.9, 954.2, 1064.7", \ + "1075.0, 1075.0, 1075.0, 1130.3, 1240.9", \ + "1412.3, 1412.3, 1412.3, 1467.6, 1578.2", \ + "2078.2, 2078.2, 2078.2, 2133.5, 2244.1", \ + "3402.2, 3402.2, 3402.2, 3457.5, 3568.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__13) { + values ("723.2, 723.2, 723.2, 778.5, 889.1", \ + "791.3, 791.3, 791.3, 846.6, 957.1", \ + "926.2, 926.2, 926.2, 981.4, 1092.0", \ + "1186.3, 1186.3, 1186.3, 1241.6, 1352.2", \ + "1691.6, 1691.6, 1691.6, 1746.9, 1857.5"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("1410.2, 1410.2, 1410.2, 1465.5, 1576.1", \ + "1628.9, 1628.9, 1628.9, 1684.2, 1794.8", \ + "2032.0, 2032.0, 2032.0, 2087.3, 2197.9", \ + "2829.9, 2829.9, 2829.9, 2885.2, 2995.8", \ + "4428.7, 4428.7, 4428.7, 4484.0, 4594.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__13) { + values ("723.2, 723.2, 723.2, 778.5, 889.1", \ + "791.3, 791.3, 791.3, 846.6, 957.1", \ + "926.2, 926.2, 926.2, 981.4, 1092.0", \ + "1186.3, 1186.3, 1186.3, 1241.6, 1352.2", \ + "1691.6, 1691.6, 1691.6, 1746.9, 1857.5"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("1410.2, 1410.2, 1410.2, 1465.5, 1576.1", \ + "1628.9, 1628.9, 1628.9, 1684.2, 1794.8", \ + "2032.0, 2032.0, 2032.0, 2087.3, 2197.9", \ + "2829.9, 2829.9, 2829.9, 2885.2, 2995.8", \ + "4428.7, 4428.7, 4428.7, 4484.0, 4594.6"); + } + } + internal_power (energy_neg_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__13) { + values ("848.1, 848.1, 848.1, 903.4, 1013.9", \ + "963.6, 963.6, 963.6, 1018.9, 1129.5", \ + "1189.7, 1189.7, 1189.7, 1245.0, 1355.6", \ + "1634.6, 1634.6, 1634.6, 1689.9, 1800.4", \ + "2515.8, 2515.8, 2515.8, 2571.1, 2681.6"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("1554.1, 1554.1, 1554.1, 1609.4, 1720.0", \ + "1683.6, 1683.6, 1683.6, 1738.9, 1849.5", \ + "1877.2, 1877.2, 1877.2, 1932.5, 2043.1", \ + "2228.2, 2228.2, 2228.2, 2283.5, 2394.1", \ + "2909.0, 2909.0, 2909.0, 2964.3, 3074.9"); + } + } + internal_power (energy_neg_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__13) { + values ("747.1, 747.1, 747.1, 802.4, 913.0", \ + "832.8, 832.8, 832.8, 888.1, 998.7", \ + "996.7, 996.7, 996.7, 1052.0, 1162.6", \ + "1315.0, 1315.0, 1315.0, 1370.3, 1480.8", \ + "1938.3, 1938.3, 1938.3, 1993.5, 2104.1"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("1149.1, 1149.1, 1149.1, 1204.4, 1315.0", \ + "1197.3, 1197.3, 1197.3, 1252.6, 1363.2", \ + "1358.4, 1358.4, 1358.4, 1413.7, 1524.3", \ + "1649.8, 1649.8, 1649.8, 1705.1, 1815.7", \ + "2215.8, 2215.8, 2215.8, 2271.1, 2381.7"); + } + } + } + } + + cell (na2_x1) { + area : 0.0 ; + cell_leakage_power : 0.83 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 3.3 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.00011 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 9e-05 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 1.9e-06 ; + } + pin (i1) { + direction : input ; + capacitance : 5.92 ; + } + pin (i0) { + direction : input ; + capacitance : 5.93 ; + } + pin (nq) { + function : "(!(i1) | !(i0))" ; + direction : output ; + capacitance : 3.07 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__14) { + values ("30.7, 30.7, 30.7, 38.2, 52.2", \ + "45.5, 45.5, 45.5, 53.6, 68.8", \ + "72.1, 72.1, 72.1, 80.6, 96.9", \ + "123.4, 123.4, 123.4, 132.2, 149.3", \ + "225.0, 225.0, 225.0, 233.9, 251.5"); + } + rise_transition (inslew_load_5x5__14) { + values ("55.5, 55.5, 55.5, 66.9, 89.4", \ + "96.1, 96.1, 96.1, 107.6, 130.4", \ + "173.3, 173.3, 173.3, 184.9, 208.0", \ + "325.3, 325.3, 325.3, 337.1, 360.4", \ + "628.2, 628.2, 628.2, 640.0, 663.6"); + } + cell_fall (inslew_load_5x5__14) { + values ("9.8, 9.8, 9.8, 15.2, 25.0", \ + "2.7, 2.7, 2.7, 9.0, 20.5", \ + "-13.4, -13.4, -13.4, -6.1, 7.2", \ + "-47.2, -47.2, -47.2, -39.2, -24.2", \ + "-115.8, -115.8, -115.8, -107.4, -91.1"); + } + fall_transition (inslew_load_5x5__14) { + values ("23.8, 23.8, 23.8, 29.3, 40.0", \ + "34.9, 34.9, 34.9, 40.7, 51.7", \ + "56.4, 56.4, 56.4, 62.4, 74.0", \ + "98.8, 98.8, 98.8, 105.0, 117.2", \ + "183.0, 183.0, 183.0, 189.4, 202.0"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__14) { + values ("19.8, 19.8, 19.8, 28.3, 43.2", \ + "29.0, 29.0, 29.0, 38.0, 54.4", \ + "44.9, 44.9, 44.9, 54.3, 72.1", \ + "75.5, 75.5, 75.5, 85.1, 103.8", \ + "135.8, 135.8, 135.8, 145.6, 164.9"); + } + rise_transition (inslew_load_5x5__14) { + values ("40.3, 40.3, 40.3, 52.0, 74.8", \ + "73.9, 73.9, 73.9, 85.7, 108.9", \ + "137.7, 137.7, 137.7, 149.6, 173.2", \ + "263.6, 263.6, 263.6, 275.7, 299.5", \ + "514.5, 514.5, 514.5, 526.6, 550.7"); + } + cell_fall (inslew_load_5x5__14) { + values ("5.9, 5.9, 5.9, 12.9, 24.6", \ + "1.5, 1.5, 1.5, 9.5, 23.3", \ + "-8.0, -8.0, -8.0, 0.6, 16.3", \ + "-27.9, -27.9, -27.9, -18.7, -1.5", \ + "-67.8, -67.8, -67.8, -58.4, -40.2"); + } + fall_transition (inslew_load_5x5__14) { + values ("18.0, 18.0, 18.0, 24.1, 35.3", \ + "31.0, 31.0, 31.0, 37.3, 49.2", \ + "56.2, 56.2, 56.2, 62.7, 75.3", \ + "106.2, 106.2, 106.2, 112.9, 125.9", \ + "205.8, 205.8, 205.8, 212.6, 226.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__14) { + values ("171.7, 171.7, 171.7, 210.0, 286.7", \ + "268.5, 268.5, 268.5, 306.8, 383.5", \ + "462.1, 462.1, 462.1, 500.4, 577.1", \ + "849.3, 849.3, 849.3, 887.7, 964.3", \ + "1623.8, 1623.8, 1623.8, 1662.1, 1738.8"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("124.4, 124.4, 124.4, 162.8, 239.5", \ + "164.1, 164.1, 164.1, 202.5, 279.1", \ + "243.5, 243.5, 243.5, 281.8, 358.5", \ + "402.2, 402.2, 402.2, 440.5, 517.2", \ + "719.6, 719.6, 719.6, 758.0, 834.6"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__14) { + values ("116.5, 116.5, 116.5, 154.8, 231.5", \ + "192.5, 192.5, 192.5, 230.9, 307.6", \ + "344.7, 344.7, 344.7, 383.0, 459.7", \ + "648.9, 648.9, 648.9, 687.2, 763.9", \ + "1257.4, 1257.4, 1257.4, 1295.7, 1372.4"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("80.3, 80.3, 80.3, 118.7, 195.3", \ + "124.4, 124.4, 124.4, 162.8, 239.4", \ + "212.6, 212.6, 212.6, 251.0, 327.6", \ + "389.0, 389.0, 389.0, 427.4, 504.0", \ + "741.8, 741.8, 741.8, 780.2, 856.8"); + } + } + } + } + + cell (na2_x4) { + area : 0.0 ; + cell_leakage_power : 4.9 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 8.7 ; + } + leakage_power () { + when : "(!(i0) | !(i1))" ; + value : 1 ; + } + pin (i1) { + direction : input ; + capacitance : 5.90 ; + } + pin (i0) { + direction : input ; + capacitance : 5.90 ; + } + pin (nq) { + function : "(!(i0) | !(i1))" ; + direction : output ; + capacitance : 4.13 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("80.0, 80.0, 80.0, 84.2, 91.7", \ + "94.2, 94.2, 94.2, 98.4, 106.1", \ + "115.3, 115.3, 115.3, 119.4, 127.5", \ + "150.2, 150.2, 150.2, 154.5, 162.7", \ + "213.8, 213.8, 213.8, 218.3, 226.8"); + } + rise_transition (inslew_load_5x5__15) { + values ("33.4, 33.4, 33.4, 38.8, 49.3", \ + "41.3, 41.3, 41.3, 46.6, 57.3", \ + "55.2, 55.2, 55.2, 60.6, 71.2", \ + "80.9, 80.9, 80.9, 86.4, 97.1", \ + "130.6, 130.6, 130.6, 135.9, 146.6"); + } + cell_fall (inslew_load_5x5__15) { + values ("65.0, 65.0, 65.0, 69.0, 76.4", \ + "66.6, 66.6, 66.6, 70.5, 78.0", \ + "64.7, 64.7, 64.7, 68.7, 76.2", \ + "55.6, 55.6, 55.6, 59.8, 67.3", \ + "31.4, 31.4, 31.4, 35.7, 43.7"); + } + fall_transition (inslew_load_5x5__15) { + values ("29.3, 29.3, 29.3, 31.9, 36.7", \ + "32.7, 32.7, 32.7, 35.3, 40.1", \ + "38.7, 38.7, 38.7, 41.2, 46.2", \ + "49.6, 49.6, 49.6, 52.2, 57.2", \ + "70.7, 70.7, 70.7, 73.3, 78.3"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("92.1, 92.1, 92.1, 96.3, 103.9", \ + "111.6, 111.6, 111.6, 115.8, 123.6", \ + "143.0, 143.0, 143.0, 147.2, 155.3", \ + "198.2, 198.2, 198.2, 202.6, 210.9", \ + "302.6, 302.6, 302.6, 307.1, 315.7"); + } + rise_transition (inslew_load_5x5__15) { + values ("36.9, 36.9, 36.9, 42.3, 52.9", \ + "46.2, 46.2, 46.2, 51.5, 62.1", \ + "62.5, 62.5, 62.5, 67.9, 78.6", \ + "93.2, 93.2, 93.2, 98.5, 109.3", \ + "152.9, 152.9, 152.9, 158.2, 168.9"); + } + cell_fall (inslew_load_5x5__15) { + values ("69.2, 69.2, 69.2, 73.2, 80.7", \ + "67.0, 67.0, 67.0, 70.9, 78.5", \ + "57.8, 57.8, 57.8, 61.8, 69.3", \ + "33.5, 33.5, 33.5, 37.7, 45.2", \ + "-21.0, -21.0, -21.0, -16.7, -8.8"); + } + fall_transition (inslew_load_5x5__15) { + values ("30.7, 30.7, 30.7, 33.3, 38.2", \ + "33.5, 33.5, 33.5, 36.1, 41.0", \ + "38.6, 38.6, 38.6, 41.1, 46.2", \ + "47.9, 47.9, 47.9, 50.4, 55.5", \ + "65.8, 65.8, 65.8, 68.4, 73.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__15) { + values ("611.5, 611.5, 611.5, 663.1, 766.3", \ + "760.4, 760.4, 760.4, 811.9, 915.1", \ + "1046.8, 1046.8, 1046.8, 1098.4, 1201.6", \ + "1609.0, 1609.0, 1609.0, 1660.6, 1763.8", \ + "2723.1, 2723.1, 2723.1, 2774.7, 2877.9"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("609.5, 609.5, 609.5, 661.1, 764.3", \ + "695.4, 695.4, 695.4, 747.0, 850.2", \ + "859.9, 859.9, 859.9, 911.5, 1014.7", \ + "1180.5, 1180.5, 1180.5, 1232.1, 1335.3", \ + "1814.3, 1814.3, 1814.3, 1865.9, 1969.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__15) { + values ("699.2, 699.2, 699.2, 750.8, 854.0", \ + "882.6, 882.6, 882.6, 934.2, 1037.4", \ + "1236.8, 1236.8, 1236.8, 1288.4, 1391.6", \ + "1933.5, 1933.5, 1933.5, 1985.1, 2088.3", \ + "3317.9, 3317.9, 3317.9, 3369.5, 3472.7"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("671.0, 671.0, 671.0, 722.5, 825.7", \ + "745.2, 745.2, 745.2, 796.8, 900.0", \ + "889.8, 889.8, 889.8, 941.4, 1044.6", \ + "1171.2, 1171.2, 1171.2, 1222.8, 1326.0", \ + "1726.8, 1726.8, 1726.8, 1778.4, 1881.6"); + } + } + } + } + + cell (na3_x1) { + area : 0.0 ; + cell_leakage_power : 0.71 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 5 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 0.0001 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 8.2e-05 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0))" ; + value : 8e-05 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 1.7e-06 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 1.6e-06 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 7.7e-07 ; + } + pin (i2) { + direction : input ; + capacitance : 5.72 ; + } + pin (i1) { + direction : input ; + capacitance : 5.84 ; + } + pin (i0) { + direction : input ; + capacitance : 5.81 ; + } + pin (nq) { + function : "((!(i1) | !(i0)) | !(i2))" ; + direction : output ; + capacitance : 3.92 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("37.0, 37.0, 37.0, 46.1, 63.1", \ + "51.0, 51.0, 51.0, 60.9, 79.7", \ + "75.5, 75.5, 75.5, 86.2, 106.6", \ + "122.3, 122.3, 122.3, 133.5, 155.2", \ + "214.3, 214.3, 214.3, 225.8, 248.5"); + } + rise_transition (inslew_load_5x5__16) { + values ("65.2, 65.2, 65.2, 79.6, 108.1", \ + "104.0, 104.0, 104.0, 118.7, 147.6", \ + "178.1, 178.1, 178.1, 192.9, 222.4", \ + "323.9, 323.9, 323.9, 338.9, 368.8", \ + "614.3, 614.3, 614.3, 629.4, 659.6"); + } + cell_fall (inslew_load_5x5__16) { + values ("21.0, 21.0, 21.0, 28.6, 43.2", \ + "15.5, 15.5, 15.5, 23.9, 39.9", \ + "2.2, 2.2, 2.2, 11.8, 29.6", \ + "-26.5, -26.5, -26.5, -16.0, 3.8", \ + "-86.0, -86.0, -86.0, -74.7, -53.0"); + } + fall_transition (inslew_load_5x5__16) { + values ("41.7, 41.7, 41.7, 52.0, 72.6", \ + "54.5, 54.5, 54.5, 64.9, 85.4", \ + "79.7, 79.7, 79.7, 90.2, 110.9", \ + "129.4, 129.4, 129.4, 140.1, 161.2", \ + "228.2, 228.2, 228.2, 239.1, 260.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("28.6, 28.6, 28.6, 38.3, 56.0", \ + "37.1, 37.1, 37.1, 47.8, 67.6", \ + "51.1, 51.1, 51.1, 62.7, 84.6", \ + "77.1, 77.1, 77.1, 89.3, 112.9", \ + "127.8, 127.8, 127.8, 140.4, 165.2"); + } + rise_transition (inslew_load_5x5__16) { + values ("52.7, 52.7, 52.7, 67.3, 96.0", \ + "84.7, 84.7, 84.7, 99.6, 128.8", \ + "145.6, 145.6, 145.6, 160.8, 190.7", \ + "265.7, 265.7, 265.7, 281.1, 311.5", \ + "504.8, 504.8, 504.8, 520.3, 551.1"); + } + cell_fall (inslew_load_5x5__16) { + values ("18.7, 18.7, 18.7, 27.2, 42.8", \ + "16.6, 16.6, 16.6, 26.4, 44.0", \ + "10.3, 10.3, 10.3, 21.2, 41.2", \ + "-4.0, -4.0, -4.0, 7.8, 30.0", \ + "-33.8, -33.8, -33.8, -21.4, 2.4"); + } + fall_transition (inslew_load_5x5__16) { + values ("34.3, 34.3, 34.3, 44.7, 65.4", \ + "49.4, 49.4, 49.4, 60.1, 81.0", \ + "78.6, 78.6, 78.6, 89.5, 110.9", \ + "136.2, 136.2, 136.2, 147.3, 169.3", \ + "250.8, 250.8, 250.8, 262.1, 284.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("19.1, 19.1, 19.1, 29.8, 48.4", \ + "23.1, 23.1, 23.1, 34.9, 56.1", \ + "28.8, 28.8, 28.8, 41.6, 65.2", \ + "38.8, 38.8, 38.8, 52.3, 77.9", \ + "57.9, 57.9, 57.9, 71.8, 98.8"); + } + rise_transition (inslew_load_5x5__16) { + values ("39.5, 39.5, 39.5, 54.5, 83.4", \ + "66.5, 66.5, 66.5, 81.8, 111.5", \ + "118.1, 118.1, 118.1, 133.7, 164.2", \ + "219.7, 219.7, 219.7, 235.5, 266.7", \ + "422.1, 422.1, 422.1, 438.1, 469.8"); + } + cell_fall (inslew_load_5x5__16) { + values ("13.5, 13.5, 13.5, 23.5, 40.6", \ + "14.2, 14.2, 14.2, 25.6, 45.3", \ + "13.9, 13.9, 13.9, 26.3, 48.7", \ + "12.1, 12.1, 12.1, 25.3, 49.9", \ + "8.0, 8.0, 8.0, 21.5, 47.7"); + } + fall_transition (inslew_load_5x5__16) { + values ("25.8, 25.8, 25.8, 36.7, 57.6", \ + "42.7, 42.7, 42.7, 53.9, 75.4", \ + "75.2, 75.2, 75.2, 86.6, 108.8", \ + "139.2, 139.2, 139.2, 150.9, 173.7", \ + "266.7, 266.7, 266.7, 278.5, 301.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__16) { + values ("201.8, 201.8, 201.8, 250.9, 349.0", \ + "293.6, 293.6, 293.6, 342.6, 440.8", \ + "477.1, 477.1, 477.1, 526.2, 624.3", \ + "844.2, 844.2, 844.2, 893.2, 991.3", \ + "1578.2, 1578.2, 1578.2, 1627.3, 1725.4"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("171.3, 171.3, 171.3, 220.4, 318.5", \ + "212.1, 212.1, 212.1, 261.1, 359.3", \ + "293.6, 293.6, 293.6, 342.7, 440.8", \ + "456.8, 456.8, 456.8, 505.8, 603.9", \ + "783.0, 783.0, 783.0, 832.0, 930.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__16) { + values ("155.1, 155.1, 155.1, 204.2, 302.3", \ + "226.6, 226.6, 226.6, 275.6, 373.7", \ + "369.4, 369.4, 369.4, 418.5, 516.6", \ + "655.1, 655.1, 655.1, 704.2, 802.3", \ + "1226.5, 1226.5, 1226.5, 1275.5, 1373.7"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("133.6, 133.6, 133.6, 182.7, 280.8", \ + "178.7, 178.7, 178.7, 227.8, 325.9", \ + "268.8, 268.8, 268.8, 317.9, 416.0", \ + "449.1, 449.1, 449.1, 498.2, 596.3", \ + "809.6, 809.6, 809.6, 858.7, 956.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__16) { + values ("108.7, 108.7, 108.7, 157.8, 255.9", \ + "166.1, 166.1, 166.1, 215.1, 313.2", \ + "280.7, 280.7, 280.7, 329.8, 427.9", \ + "509.9, 509.9, 509.9, 559.0, 657.1", \ + "968.5, 968.5, 968.5, 1017.5, 1115.6"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("94.6, 94.6, 94.6, 143.6, 241.7", \ + "142.4, 142.4, 142.4, 191.5, 289.6", \ + "238.2, 238.2, 238.2, 287.2, 385.3", \ + "429.6, 429.6, 429.6, 478.7, 576.8", \ + "812.6, 812.6, 812.6, 861.7, 959.8"); + } + } + } + } + + cell (na3_x4) { + area : 0.0 ; + cell_leakage_power : 6.4 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 12 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2))" ; + value : 1 ; + } + pin (i2) { + direction : input ; + capacitance : 5.99 ; + } + pin (i1) { + direction : input ; + capacitance : 5.99 ; + } + pin (i0) { + direction : input ; + capacitance : 6.03 ; + } + pin (nq) { + function : "(!(i0) | !(i2) | !(i1))" ; + direction : output ; + capacitance : 4.95 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("62.4, 62.4, 62.4, 67.0, 75.3", \ + "66.6, 66.6, 66.6, 71.3, 79.6", \ + "68.4, 68.4, 68.4, 73.1, 81.6", \ + "65.0, 65.0, 65.0, 69.6, 78.4", \ + "51.2, 51.2, 51.2, 56.0, 65.0"); + } + rise_transition (inslew_load_5x5__17) { + values ("26.3, 26.3, 26.3, 32.8, 45.3", \ + "32.9, 32.9, 32.9, 39.3, 51.8", \ + "44.0, 44.0, 44.0, 50.4, 62.9", \ + "63.5, 63.5, 63.5, 69.9, 82.4", \ + "98.6, 98.6, 98.6, 105.0, 117.6"); + } + cell_fall (inslew_load_5x5__17) { + values ("78.9, 78.9, 78.9, 83.2, 90.5", \ + "88.3, 88.3, 88.3, 93.9, 101.4", \ + "104.5, 104.5, 104.5, 108.5, 116.5", \ + "128.9, 128.9, 128.9, 132.8, 140.3", \ + "171.9, 171.9, 171.9, 175.8, 183.6"); + } + fall_transition (inslew_load_5x5__17) { + values ("31.1, 31.1, 31.1, 33.0, 37.5", \ + "36.2, 36.2, 36.2, 38.7, 43.1", \ + "46.2, 46.2, 46.2, 48.9, 52.8", \ + "63.9, 63.9, 63.9, 66.7, 71.6", \ + "98.6, 98.6, 98.6, 101.1, 106.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("78.7, 78.7, 78.7, 83.4, 91.7", \ + "90.8, 90.8, 90.8, 95.4, 103.9", \ + "107.3, 107.3, 107.3, 111.9, 120.6", \ + "133.4, 133.4, 133.4, 138.1, 147.0", \ + "178.1, 178.1, 178.1, 182.7, 191.9"); + } + rise_transition (inslew_load_5x5__17) { + values ("32.5, 32.5, 32.5, 38.9, 51.4", \ + "41.0, 41.0, 41.0, 47.4, 59.9", \ + "55.6, 55.6, 55.6, 62.0, 74.5", \ + "81.6, 81.6, 81.6, 87.9, 100.6", \ + "131.1, 131.1, 131.1, 137.5, 150.2"); + } + cell_fall (inslew_load_5x5__17) { + values ("89.3, 89.3, 89.3, 94.8, 102.3", \ + "90.4, 90.4, 90.4, 95.9, 103.6", \ + "90.1, 90.1, 90.1, 94.0, 102.0", \ + "82.3, 82.3, 82.3, 86.1, 93.8", \ + "60.5, 60.5, 60.5, 64.4, 72.1"); + } + fall_transition (inslew_load_5x5__17) { + values ("35.4, 35.4, 35.4, 37.8, 42.2", \ + "39.1, 39.1, 39.1, 42.0, 46.2", \ + "46.9, 46.9, 46.9, 49.8, 53.7", \ + "60.8, 60.8, 60.8, 63.6, 68.2", \ + "87.9, 87.9, 87.9, 90.4, 95.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("70.9, 70.9, 70.9, 75.6, 84.0", \ + "78.6, 78.6, 78.6, 83.3, 91.7", \ + "87.2, 87.2, 87.2, 91.8, 100.4", \ + "96.6, 96.6, 96.6, 101.2, 110.0", \ + "108.0, 108.0, 108.0, 112.7, 121.9"); + } + rise_transition (inslew_load_5x5__17) { + values ("29.5, 29.5, 29.5, 35.9, 48.4", \ + "37.0, 37.0, 37.0, 43.4, 55.9", \ + "49.4, 49.4, 49.4, 55.8, 68.3", \ + "71.7, 71.7, 71.7, 78.0, 90.6", \ + "112.5, 112.5, 112.5, 118.8, 131.4"); + } + cell_fall (inslew_load_5x5__17) { + values ("86.0, 86.0, 86.0, 90.5, 97.8", \ + "91.3, 91.3, 91.3, 96.9, 104.5", \ + "99.9, 99.9, 99.9, 103.8, 111.9", \ + "109.4, 109.4, 109.4, 113.3, 120.9", \ + "122.6, 122.6, 122.6, 126.5, 134.2"); + } + fall_transition (inslew_load_5x5__17) { + values ("33.6, 33.6, 33.6, 35.5, 40.0", \ + "37.8, 37.8, 37.8, 40.5, 44.8", \ + "46.9, 46.9, 46.9, 49.7, 53.6", \ + "62.9, 62.9, 62.9, 65.7, 70.4", \ + "94.2, 94.2, 94.2, 96.7, 102.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__17) { + values ("641.2, 641.2, 641.2, 703.1, 826.9", \ + "759.2, 759.2, 759.2, 821.1, 944.9", \ + "985.2, 985.2, 985.2, 1047.1, 1170.8", \ + "1427.1, 1427.1, 1427.1, 1489.0, 1612.7", \ + "2294.7, 2294.7, 2294.7, 2356.6, 2480.3"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("739.4, 739.4, 739.4, 801.3, 925.1", \ + "874.5, 874.5, 874.5, 936.4, 1060.2", \ + "1130.6, 1130.6, 1130.6, 1192.5, 1316.3", \ + "1629.5, 1629.5, 1629.5, 1691.4, 1815.2", \ + "2615.4, 2615.4, 2615.4, 2677.3, 2801.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__17) { + values ("791.2, 791.2, 791.2, 853.0, 976.8", \ + "967.3, 967.3, 967.3, 1029.2, 1153.0", \ + "1308.5, 1308.5, 1308.5, 1370.4, 1494.2", \ + "1976.0, 1976.0, 1976.0, 2037.9, 2161.7", \ + "3303.0, 3303.0, 3303.0, 3364.9, 3488.6"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("887.9, 887.9, 887.9, 949.8, 1073.5", \ + "993.7, 993.7, 993.7, 1055.6, 1179.3", \ + "1200.1, 1200.1, 1200.1, 1262.0, 1385.8", \ + "1605.3, 1605.3, 1605.3, 1667.2, 1791.0", \ + "2406.9, 2406.9, 2406.9, 2468.8, 2592.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__17) { + values ("716.5, 716.5, 716.5, 778.4, 902.1", \ + "858.4, 858.4, 858.4, 920.3, 1044.0", \ + "1131.3, 1131.3, 1131.3, 1193.2, 1317.0", \ + "1666.6, 1666.6, 1666.6, 1728.4, 1852.2", \ + "2720.5, 2720.5, 2720.5, 2782.4, 2906.1"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("816.1, 816.1, 816.1, 878.0, 1001.8", \ + "939.0, 939.0, 939.0, 1000.9, 1124.6", \ + "1174.0, 1174.0, 1174.0, 1235.8, 1359.6", \ + "1632.9, 1632.9, 1632.9, 1694.8, 1818.5", \ + "2540.3, 2540.3, 2540.3, 2602.2, 2725.9"); + } + } + } + } + + cell (na4_x1) { + area : 0.0 ; + cell_leakage_power : 0.67 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 6.7 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & i0)" ; + value : 0.0001 ; + } + leakage_power () { + when : "(i3 & !(i2) & i1 & i0)" ; + value : 8.2e-05 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & i0)" ; + value : 8e-05 ; + } + leakage_power () { + when : "(i3 & i2 & i1 & !(i0))" ; + value : 7.9e-05 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & i3)" ; + value : 1.6e-06 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3)) | (!(i0) & ((i1 & i2 & !(i3)) | (!(i1) & i2 & i3))))" ; + value : 1.7e-06 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & (i1 ^ i2) & !(i3)))" ; + value : 7.7e-07 ; + } + leakage_power () { + when : "(i3 & !(i2) & !(i1) & !(i0))" ; + value : 7.6e-07 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 4.7e-07 ; + } + pin (i3) { + direction : input ; + capacitance : 5.82 ; + } + pin (i2) { + direction : input ; + capacitance : 5.93 ; + } + pin (i1) { + direction : input ; + capacitance : 5.93 ; + } + pin (i0) { + direction : input ; + capacitance : 5.94 ; + } + pin (nq) { + function : "(((!(i3) | !(i1)) | !(i0)) | !(i2))" ; + direction : output ; + capacitance : 4.38 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("42.3, 42.3, 42.3, 52.1, 70.7", \ + "56.8, 56.8, 56.8, 67.6, 87.9", \ + "81.8, 81.8, 81.8, 93.4, 115.7", \ + "128.8, 128.8, 128.8, 141.1, 165.0", \ + "221.0, 221.0, 221.0, 233.7, 258.8"); + } + rise_transition (inslew_load_5x5__18) { + values ("73.5, 73.5, 73.5, 89.5, 121.3", \ + "112.5, 112.5, 112.5, 128.8, 160.9", \ + "186.6, 186.6, 186.6, 203.1, 235.8", \ + "332.6, 332.6, 332.6, 349.3, 382.5", \ + "623.0, 623.0, 623.0, 639.9, 673.4"); + } + cell_fall (inslew_load_5x5__18) { + values ("32.3, 32.3, 32.3, 42.0, 61.1", \ + "26.9, 26.9, 26.9, 37.1, 57.2", \ + "14.5, 14.5, 14.5, 25.7, 47.2", \ + "-12.4, -12.4, -12.4, -0.1, 23.2", \ + "-68.5, -68.5, -68.5, -55.4, -30.2"); + } + fall_transition (inslew_load_5x5__18) { + values ("64.1, 64.1, 64.1, 79.4, 109.9", \ + "78.9, 78.9, 78.9, 93.9, 124.0", \ + "107.8, 107.8, 107.8, 122.8, 153.2", \ + "165.6, 165.6, 165.6, 180.8, 211.0", \ + "280.8, 280.8, 280.8, 296.1, 326.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("35.1, 35.1, 35.1, 45.4, 64.4", \ + "44.3, 44.3, 44.3, 55.7, 77.0", \ + "58.9, 58.9, 58.9, 71.4, 95.1", \ + "85.2, 85.2, 85.2, 98.6, 124.4", \ + "136.2, 136.2, 136.2, 150.1, 177.3"); + } + rise_transition (inslew_load_5x5__18) { + values ("62.3, 62.3, 62.3, 78.5, 110.3", \ + "94.5, 94.5, 94.5, 111.0, 143.4", \ + "155.6, 155.6, 155.6, 172.4, 205.5", \ + "275.8, 275.8, 275.8, 292.9, 326.7", \ + "515.0, 515.0, 515.0, 532.3, 566.6"); + } + cell_fall (inslew_load_5x5__18) { + values ("29.8, 29.8, 29.8, 40.0, 59.7", \ + "28.6, 28.6, 28.6, 39.8, 60.8", \ + "23.7, 23.7, 23.7, 36.0, 59.1", \ + "11.3, 11.3, 11.3, 24.8, 50.3", \ + "-15.0, -15.0, -15.0, -0.8, 26.6"); + } + fall_transition (inslew_load_5x5__18) { + values ("54.8, 54.8, 54.8, 70.0, 100.5", \ + "72.2, 72.2, 72.2, 87.4, 117.9", \ + "105.9, 105.9, 105.9, 121.3, 151.7", \ + "172.5, 172.5, 172.5, 188.1, 219.0", \ + "304.9, 304.9, 304.9, 320.7, 352.0"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("27.6, 27.6, 27.6, 38.5, 58.1", \ + "32.5, 32.5, 32.5, 44.8, 67.0", \ + "38.9, 38.9, 38.9, 52.5, 77.7", \ + "49.4, 49.4, 49.4, 64.0, 91.6", \ + "68.8, 68.8, 68.8, 84.0, 113.5"); + } + rise_transition (inslew_load_5x5__18) { + values ("51.2, 51.2, 51.2, 67.5, 99.5", \ + "78.5, 78.5, 78.5, 95.2, 127.9", \ + "130.3, 130.3, 130.3, 147.4, 181.0", \ + "232.1, 232.1, 232.1, 249.6, 284.0", \ + "434.6, 434.6, 434.6, 452.3, 487.4"); + } + cell_fall (inslew_load_5x5__18) { + values ("25.0, 25.0, 25.0, 36.2, 56.7", \ + "27.0, 27.0, 27.0, 39.3, 61.9", \ + "28.2, 28.2, 28.2, 41.8, 67.0", \ + "28.4, 28.4, 28.4, 43.1, 70.9", \ + "27.5, 27.5, 27.5, 43.0, 72.7"); + } + fall_transition (inslew_load_5x5__18) { + values ("44.1, 44.1, 44.1, 59.5, 90.1", \ + "63.6, 63.6, 63.6, 79.2, 109.9", \ + "101.0, 101.0, 101.0, 116.8, 147.9", \ + "174.5, 174.5, 174.5, 190.5, 222.2", \ + "320.6, 320.6, 320.6, 336.9, 369.0"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("18.7, 18.7, 18.7, 30.6, 51.1", \ + "19.8, 19.8, 19.8, 33.3, 56.9", \ + "19.5, 19.5, 19.5, 34.5, 61.4", \ + "17.4, 17.4, 17.4, 33.3, 63.2", \ + "12.0, 12.0, 12.0, 28.6, 60.5"); + } + rise_transition (inslew_load_5x5__18) { + values ("39.0, 39.0, 39.0, 55.7, 87.9", \ + "62.5, 62.5, 62.5, 79.7, 112.8", \ + "107.2, 107.2, 107.2, 124.9, 159.1", \ + "195.4, 195.4, 195.4, 213.4, 248.6", \ + "370.9, 370.9, 370.9, 389.1, 425.1"); + } + cell_fall (inslew_load_5x5__18) { + values ("18.1, 18.1, 18.1, 30.5, 52.0", \ + "22.6, 22.6, 22.6, 36.5, 60.8", \ + "29.0, 29.0, 29.0, 44.2, 71.7", \ + "40.1, 40.1, 40.1, 56.3, 86.4", \ + "61.6, 61.6, 61.6, 78.2, 110.2"); + } + fall_transition (inslew_load_5x5__18) { + values ("33.0, 33.0, 33.0, 48.6, 79.2", \ + "54.2, 54.2, 54.2, 70.2, 101.3", \ + "94.4, 94.4, 94.4, 110.7, 142.7", \ + "173.3, 173.3, 173.3, 189.9, 222.5", \ + "330.3, 330.3, 330.3, 347.0, 380.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__18) { + values ("230.1, 230.1, 230.1, 284.8, 394.3", \ + "321.9, 321.9, 321.9, 376.6, 486.0", \ + "505.4, 505.4, 505.4, 560.1, 669.6", \ + "872.4, 872.4, 872.4, 927.2, 1036.6", \ + "1606.5, 1606.5, 1606.5, 1661.3, 1770.7"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("210.7, 210.7, 210.7, 265.4, 374.9", \ + "251.5, 251.5, 251.5, 306.2, 415.6", \ + "333.0, 333.0, 333.0, 387.8, 497.2", \ + "496.2, 496.2, 496.2, 550.9, 660.3", \ + "822.4, 822.4, 822.4, 877.1, 986.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__18) { + values ("187.5, 187.5, 187.5, 242.2, 351.7", \ + "258.9, 258.9, 258.9, 313.6, 423.1", \ + "401.8, 401.8, 401.8, 456.5, 565.9", \ + "687.5, 687.5, 687.5, 742.2, 851.6", \ + "1258.8, 1258.8, 1258.8, 1313.6, 1423.0"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("176.8, 176.8, 176.8, 231.5, 340.9", \ + "221.8, 221.8, 221.8, 276.6, 386.0", \ + "312.0, 312.0, 312.0, 366.7, 476.1", \ + "492.2, 492.2, 492.2, 547.0, 656.4", \ + "852.8, 852.8, 852.8, 907.5, 1016.9"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__18) { + values ("147.0, 147.0, 147.0, 201.8, 311.2", \ + "204.4, 204.4, 204.4, 259.1, 368.5", \ + "319.0, 319.0, 319.0, 373.7, 483.1", \ + "548.2, 548.2, 548.2, 603.0, 712.4", \ + "1006.7, 1006.7, 1006.7, 1061.5, 1170.9"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("139.0, 139.0, 139.0, 193.7, 303.1", \ + "186.8, 186.8, 186.8, 241.5, 351.0", \ + "282.6, 282.6, 282.6, 337.3, 446.7", \ + "474.0, 474.0, 474.0, 528.8, 638.2", \ + "857.0, 857.0, 857.0, 911.7, 1021.1"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__18) { + values ("104.6, 104.6, 104.6, 159.4, 268.8", \ + "151.8, 151.8, 151.8, 206.5, 316.0", \ + "246.2, 246.2, 246.2, 300.9, 410.4", \ + "435.0, 435.0, 435.0, 489.7, 599.1", \ + "812.5, 812.5, 812.5, 867.2, 976.7"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("101.5, 101.5, 101.5, 156.2, 265.7", \ + "151.1, 151.1, 151.1, 205.8, 315.2", \ + "250.1, 250.1, 250.1, 304.9, 414.3", \ + "448.3, 448.3, 448.3, 503.0, 612.5", \ + "844.6, 844.6, 844.6, 899.3, 1008.8"); + } + } + } + } + + cell (na4_x4) { + area : 0.0 ; + cell_leakage_power : 6.5 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 12 ; + } + leakage_power () { + when : "(!(i0) | !(i1) | !(i2) | !(i3))" ; + value : 1 ; + } + pin (i3) { + direction : input ; + capacitance : 5.95 ; + } + pin (i2) { + direction : input ; + capacitance : 5.99 ; + } + pin (i1) { + direction : input ; + capacitance : 5.96 ; + } + pin (i0) { + direction : input ; + capacitance : 5.95 ; + } + pin (nq) { + function : "(!(i3) | !(i2) | !(i1) | !(i0))" ; + direction : output ; + capacitance : 4.24 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("78.8, 78.8, 78.8, 83.0, 90.7", \ + "90.5, 90.5, 90.5, 94.8, 102.6", \ + "106.7, 106.7, 106.7, 111.1, 119.2", \ + "132.7, 132.7, 132.7, 137.1, 145.4", \ + "178.1, 178.1, 178.1, 182.8, 191.6"); + } + rise_transition (inslew_load_5x5__19) { + values ("28.2, 28.2, 28.2, 33.7, 44.5", \ + "34.3, 34.3, 34.3, 39.9, 50.8", \ + "45.2, 45.2, 45.2, 50.8, 61.7", \ + "64.8, 64.8, 64.8, 70.4, 81.4", \ + "103.0, 103.0, 103.0, 108.5, 119.5"); + } + cell_fall (inslew_load_5x5__19) { + values ("123.8, 123.8, 123.8, 128.1, 136.0", \ + "125.1, 125.1, 125.1, 129.4, 137.4", \ + "125.2, 125.2, 125.2, 129.7, 137.8", \ + "121.1, 121.1, 121.1, 125.8, 134.2", \ + "107.4, 107.4, 107.4, 112.0, 121.0"); + } + fall_transition (inslew_load_5x5__19) { + values ("50.1, 50.1, 50.1, 52.8, 58.5", \ + "55.0, 55.0, 55.0, 57.7, 63.3", \ + "64.4, 64.4, 64.4, 67.1, 72.7", \ + "83.0, 83.0, 83.0, 85.8, 91.2", \ + "119.5, 119.5, 119.5, 122.2, 127.7"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("72.8, 72.8, 72.8, 77.1, 84.7", \ + "80.4, 80.4, 80.4, 84.7, 92.4", \ + "88.8, 88.8, 88.8, 93.2, 101.1", \ + "98.8, 98.8, 98.8, 103.2, 111.5", \ + "112.3, 112.3, 112.3, 116.8, 125.5"); + } + rise_transition (inslew_load_5x5__19) { + values ("26.3, 26.3, 26.3, 31.9, 42.7", \ + "31.7, 31.7, 31.7, 37.2, 48.1", \ + "40.8, 40.8, 40.8, 46.3, 57.2", \ + "57.4, 57.4, 57.4, 63.0, 74.0", \ + "88.8, 88.8, 88.8, 94.3, 105.4"); + } + cell_fall (inslew_load_5x5__19) { + values ("117.8, 117.8, 117.8, 122.1, 130.1", \ + "125.0, 125.0, 125.0, 129.3, 137.2", \ + "134.7, 134.7, 134.7, 139.2, 147.4", \ + "148.7, 148.7, 148.7, 153.3, 161.8", \ + "170.7, 170.7, 170.7, 175.3, 184.3"); + } + fall_transition (inslew_load_5x5__19) { + values ("47.0, 47.0, 47.0, 49.7, 55.2", \ + "52.8, 52.8, 52.8, 55.5, 61.1", \ + "64.0, 64.0, 64.0, 66.7, 72.2", \ + "85.3, 85.3, 85.3, 88.1, 93.6", \ + "127.2, 127.2, 127.2, 129.9, 135.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("66.6, 66.6, 66.6, 70.9, 78.3", \ + "70.8, 70.8, 70.8, 75.1, 82.7", \ + "73.1, 73.1, 73.1, 77.4, 85.3", \ + "70.6, 70.6, 70.6, 75.0, 83.2", \ + "59.2, 59.2, 59.2, 63.7, 72.3"); + } + rise_transition (inslew_load_5x5__19) { + values ("24.5, 24.5, 24.5, 30.0, 40.8", \ + "29.1, 29.1, 29.1, 34.7, 45.5", \ + "37.2, 37.2, 37.2, 42.7, 53.6", \ + "51.6, 51.6, 51.6, 57.2, 68.2", \ + "78.3, 78.3, 78.3, 83.8, 94.9"); + } + cell_fall (inslew_load_5x5__19) { + values ("109.1, 109.1, 109.1, 113.3, 121.3", \ + "121.0, 121.0, 121.0, 125.3, 133.2", \ + "138.8, 138.8, 138.8, 143.3, 151.4", \ + "167.9, 167.9, 167.9, 172.5, 181.0", \ + "220.1, 220.1, 220.1, 224.8, 233.8"); + } + fall_transition (inslew_load_5x5__19) { + values ("43.2, 43.2, 43.2, 46.0, 51.4", \ + "50.0, 50.0, 50.0, 52.8, 58.4", \ + "62.5, 62.5, 62.5, 65.2, 70.7", \ + "86.1, 86.1, 86.1, 88.9, 94.3", \ + "132.3, 132.3, 132.3, 135.0, 140.6"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("59.1, 59.1, 59.1, 63.3, 70.7", \ + "60.7, 60.7, 60.7, 65.0, 72.5", \ + "57.7, 57.7, 57.7, 62.0, 69.8", \ + "45.0, 45.0, 45.0, 49.3, 57.5", \ + "13.9, 13.9, 13.9, 18.4, 26.8"); + } + rise_transition (inslew_load_5x5__19) { + values ("22.3, 22.3, 22.3, 27.9, 38.7", \ + "26.5, 26.5, 26.5, 32.1, 42.9", \ + "33.8, 33.8, 33.8, 39.3, 50.2", \ + "46.6, 46.6, 46.6, 52.2, 63.1", \ + "70.0, 70.0, 70.0, 75.5, 86.6"); + } + cell_fall (inslew_load_5x5__19) { + values ("98.0, 98.0, 98.0, 102.2, 110.3", \ + "114.2, 114.2, 114.2, 118.5, 126.5", \ + "138.8, 138.8, 138.8, 143.3, 151.3", \ + "180.7, 180.7, 180.7, 185.3, 193.8", \ + "258.9, 258.9, 258.9, 263.5, 272.6"); + } + fall_transition (inslew_load_5x5__19) { + values ("39.3, 39.3, 39.3, 42.1, 47.5", \ + "47.0, 47.0, 47.0, 49.7, 55.3", \ + "60.5, 60.5, 60.5, 63.2, 68.7", \ + "85.9, 85.9, 85.9, 88.7, 94.1", \ + "135.5, 135.5, 135.5, 138.2, 143.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__19) { + values ("712.7, 712.7, 712.7, 765.6, 871.5", \ + "863.8, 863.8, 863.8, 916.7, 1022.6", \ + "1156.8, 1156.8, 1156.8, 1209.8, 1315.6", \ + "1732.7, 1732.7, 1732.7, 1785.6, 1891.5", \ + "2879.6, 2879.6, 2879.6, 2932.5, 3038.4"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("1035.0, 1035.0, 1035.0, 1087.9, 1193.8", \ + "1141.6, 1141.6, 1141.6, 1194.5, 1300.4", \ + "1351.5, 1351.5, 1351.5, 1404.5, 1510.4", \ + "1769.6, 1769.6, 1769.6, 1822.5, 1928.4", \ + "2599.4, 2599.4, 2599.4, 2652.3, 2758.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__19) { + values ("653.1, 653.1, 653.1, 706.0, 811.9", \ + "774.4, 774.4, 774.4, 827.3, 933.2", \ + "1007.9, 1007.9, 1007.9, 1060.8, 1166.7", \ + "1467.9, 1467.9, 1467.9, 1520.8, 1626.7", \ + "2378.4, 2378.4, 2378.4, 2431.3, 2537.2"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("958.9, 958.9, 958.9, 1011.9, 1117.8", \ + "1082.6, 1082.6, 1082.6, 1135.6, 1241.5", \ + "1324.0, 1324.0, 1324.0, 1377.0, 1482.8", \ + "1797.5, 1797.5, 1797.5, 1850.5, 1956.3", \ + "2736.4, 2736.4, 2736.4, 2789.3, 2895.2"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__19) { + values ("595.7, 595.7, 595.7, 648.6, 754.5", \ + "695.8, 695.8, 695.8, 748.7, 854.6", \ + "888.6, 888.6, 888.6, 941.5, 1047.4", \ + "1267.0, 1267.0, 1267.0, 1320.0, 1425.8", \ + "2012.7, 2012.7, 2012.7, 2065.7, 2171.6"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("872.0, 872.0, 872.0, 925.0, 1030.9", \ + "1010.2, 1010.2, 1010.2, 1063.1, 1169.0", \ + "1274.4, 1274.4, 1274.4, 1327.3, 1433.2", \ + "1790.1, 1790.1, 1790.1, 1843.1, 1949.0", \ + "2810.9, 2810.9, 2810.9, 2863.9, 2969.8"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__19) { + values ("534.6, 534.6, 534.6, 587.6, 693.4", \ + "619.3, 619.3, 619.3, 672.2, 778.1", \ + "782.3, 782.3, 782.3, 835.3, 941.1", \ + "1101.3, 1101.3, 1101.3, 1154.3, 1260.2", \ + "1728.8, 1728.8, 1728.8, 1781.8, 1887.7"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("783.5, 783.5, 783.5, 836.4, 942.3", \ + "933.7, 933.7, 933.7, 986.6, 1092.5", \ + "1214.7, 1214.7, 1214.7, 1267.6, 1373.5", \ + "1761.4, 1761.4, 1761.4, 1814.4, 1920.3", \ + "2843.1, 2843.1, 2843.1, 2896.1, 3002.0"); + } + } + } + } + + cell (nao22_x1) { + area : 0.0 ; + cell_leakage_power : 3.4 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 8.8 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 0.00018 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 6 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0))" ; + value : 8.9 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 9.1e-05 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 0.00022 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 3.8e-06 ; + } + pin (i2) { + direction : input ; + capacitance : 7.23 ; + } + pin (i1) { + direction : input ; + capacitance : 6.78 ; + } + pin (i0) { + direction : input ; + capacitance : 6.76 ; + } + pin (nq) { + function : "(!(i2) | (!(i1) & !(i0)))" ; + direction : output ; + capacitance : 4.38 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("38.5, 38.5, 38.5, 50.3, 73.4", \ + "41.1, 41.1, 41.1, 53.2, 77.0", \ + "45.2, 45.2, 45.2, 57.7, 82.1", \ + "52.5, 52.5, 52.5, 65.4, 90.6", \ + "66.6, 66.6, 66.6, 79.7, 105.6"); + } + rise_transition (inslew_load_5x5__20) { + values ("85.4, 85.4, 85.4, 105.6, 146.5", \ + "120.5, 120.5, 120.5, 140.5, 180.8", \ + "188.0, 188.0, 188.0, 208.9, 248.5", \ + "322.8, 322.8, 322.8, 342.7, 382.5", \ + "592.0, 592.0, 592.0, 611.9, 651.7"); + } + cell_fall (inslew_load_5x5__20) { + values ("18.6, 18.6, 18.6, 26.5, 40.5", \ + "22.5, 22.5, 22.5, 31.3, 47.3", \ + "28.2, 28.2, 28.2, 37.9, 55.7", \ + "38.5, 38.5, 38.5, 48.6, 67.9", \ + "58.2, 58.2, 58.2, 68.7, 89.0"); + } + fall_transition (inslew_load_5x5__20) { + values ("28.5, 28.5, 28.5, 36.4, 51.8", \ + "47.7, 47.7, 47.7, 55.9, 71.7", \ + "84.8, 84.8, 84.8, 93.1, 109.4", \ + "158.0, 158.0, 158.0, 166.5, 183.2", \ + "303.8, 303.8, 303.8, 312.4, 329.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("28.0, 28.0, 28.0, 41.4, 66.0", \ + "40.0, 40.0, 40.0, 54.0, 80.1", \ + "60.1, 60.1, 60.1, 74.7, 102.4", \ + "98.0, 98.0, 98.0, 113.1, 142.2", \ + "172.8, 172.8, 172.8, 188.1, 218.1"); + } + rise_transition (inslew_load_5x5__20) { + values ("56.1, 56.1, 56.1, 76.9, 118.6", \ + "98.1, 98.1, 98.1, 118.9, 160.4", \ + "176.2, 176.2, 176.2, 197.3, 239.0", \ + "329.4, 329.4, 329.4, 350.6, 392.6", \ + "634.0, 634.0, 634.0, 655.3, 697.7"); + } + cell_fall (inslew_load_5x5__20) { + values ("8.9, 8.9, 8.9, 18.2, 33.4", \ + "4.4, 4.4, 4.4, 15.2, 33.4", \ + "-5.9, -5.9, -5.9, 6.1, 27.3", \ + "-27.9, -27.9, -27.9, -14.9, 8.9", \ + "-72.5, -72.5, -72.5, -58.9, -33.1"); + } + fall_transition (inslew_load_5x5__20) { + values ("19.8, 19.8, 19.8, 28.2, 43.8", \ + "32.6, 32.6, 32.6, 41.4, 57.9", \ + "57.1, 57.1, 57.1, 66.4, 83.8", \ + "105.5, 105.5, 105.5, 115.1, 133.5", \ + "201.8, 201.8, 201.8, 211.6, 230.7"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("24.9, 24.9, 24.9, 32.2, 45.6", \ + "31.0, 31.0, 31.0, 39.1, 54.2", \ + "41.0, 41.0, 41.0, 49.8, 66.4", \ + "59.6, 59.6, 59.6, 68.7, 86.5", \ + "95.7, 95.7, 95.7, 105.2, 123.7"); + } + rise_transition (inslew_load_5x5__20) { + values ("51.8, 51.8, 51.8, 62.9, 84.7", \ + "82.7, 82.7, 82.7, 94.1, 116.3", \ + "142.4, 142.4, 142.4, 153.9, 176.7", \ + "260.6, 260.6, 260.6, 272.2, 295.4", \ + "496.2, 496.2, 496.2, 508.0, 531.4"); + } + cell_fall (inslew_load_5x5__20) { + values ("18.2, 18.2, 18.2, 25.2, 38.0", \ + "17.5, 17.5, 17.5, 25.3, 39.6", \ + "14.3, 14.3, 14.3, 22.9, 38.9", \ + "6.6, 6.6, 6.6, 15.8, 33.3", \ + "-9.2, -9.2, -9.2, 0.2, 18.7"); + } + fall_transition (inslew_load_5x5__20) { + values ("31.7, 31.7, 31.7, 39.3, 54.5", \ + "48.1, 48.1, 48.1, 55.9, 71.2", \ + "80.2, 80.2, 80.2, 88.1, 103.7", \ + "143.6, 143.6, 143.6, 151.6, 167.6", \ + "269.8, 269.8, 269.8, 278.1, 294.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__20) { + values ("212.3, 212.3, 212.3, 267.0, 376.4", \ + "289.9, 289.9, 289.9, 344.6, 454.0", \ + "445.1, 445.1, 445.1, 499.8, 609.2", \ + "755.5, 755.5, 755.5, 810.3, 919.7", \ + "1376.5, 1376.5, 1376.5, 1431.2, 1540.6"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("159.7, 159.7, 159.7, 214.4, 323.8", \ + "237.9, 237.9, 237.9, 292.6, 402.0", \ + "394.1, 394.1, 394.1, 448.8, 558.3", \ + "706.7, 706.7, 706.7, 761.4, 870.8", \ + "1331.8, 1331.8, 1331.8, 1386.5, 1495.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__20) { + values ("136.7, 136.7, 136.7, 191.4, 300.9", \ + "215.1, 215.1, 215.1, 269.8, 379.2", \ + "371.7, 371.7, 371.7, 426.4, 535.8", \ + "685.0, 685.0, 685.0, 739.7, 849.1", \ + "1311.5, 1311.5, 1311.5, 1366.2, 1475.7"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("92.8, 92.8, 92.8, 147.5, 256.9", \ + "134.6, 134.6, 134.6, 189.3, 298.7", \ + "218.2, 218.2, 218.2, 272.9, 382.3", \ + "385.4, 385.4, 385.4, 440.1, 549.5", \ + "719.8, 719.8, 719.8, 774.5, 883.9"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__20) { + values ("214.2, 214.2, 214.2, 268.9, 378.4", \ + "318.6, 318.6, 318.6, 373.3, 482.7", \ + "527.4, 527.4, 527.4, 582.1, 691.5", \ + "945.0, 945.0, 945.0, 999.7, 1109.1", \ + "1780.1, 1780.1, 1780.1, 1834.8, 1944.2"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("185.7, 185.7, 185.7, 240.4, 349.8", \ + "258.1, 258.1, 258.1, 312.8, 422.2", \ + "402.9, 402.9, 402.9, 457.6, 567.0", \ + "692.5, 692.5, 692.5, 747.2, 856.6", \ + "1271.7, 1271.7, 1271.7, 1326.4, 1435.8"); + } + } + } + } + + cell (nao22_x4) { + area : 0.0 ; + cell_leakage_power : 5.1 ; + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 6.9 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 7.4 ; + } + leakage_power () { + when : "(!((i0 | i1)) | !(i2))" ; + value : 1 ; + } + pin (i2) { + direction : input ; + capacitance : 4.25 ; + } + pin (i1) { + direction : input ; + capacitance : 4.03 ; + } + pin (i0) { + direction : input ; + capacitance : 4.08 ; + } + pin (nq) { + function : "(!(i2) | (!(i0) & !(i1)))" ; + direction : output ; + capacitance : 4.20 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("119.0, 119.0, 119.0, 123.3, 131.5", \ + "123.7, 123.7, 123.7, 128.1, 136.3", \ + "130.5, 130.5, 130.5, 134.9, 143.3", \ + "139.5, 139.5, 139.5, 144.0, 152.7", \ + "153.1, 153.1, 153.1, 157.6, 166.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("48.6, 48.6, 48.6, 54.2, 65.0", \ + "55.4, 55.4, 55.4, 60.9, 71.8", \ + "68.4, 68.4, 68.4, 73.9, 84.9", \ + "93.3, 93.3, 93.3, 98.7, 109.7", \ + "141.8, 141.8, 141.8, 147.6, 158.4"); + } + cell_fall (inslew_load_5x5__21) { + values ("93.0, 93.0, 93.0, 97.3, 105.2", \ + "104.8, 104.8, 104.8, 108.9, 117.0", \ + "121.6, 121.6, 121.6, 125.8, 133.7", \ + "148.0, 148.0, 148.0, 152.5, 160.5", \ + "194.3, 194.3, 194.3, 198.9, 207.4"); + } + fall_transition (inslew_load_5x5__21) { + values ("34.6, 34.6, 34.6, 37.4, 42.6", \ + "39.3, 39.3, 39.3, 42.1, 47.4", \ + "47.8, 47.8, 47.8, 50.5, 56.0", \ + "63.8, 63.8, 63.8, 66.5, 71.9", \ + "94.9, 94.9, 94.9, 97.6, 103.0"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("108.0, 108.0, 108.0, 112.3, 120.3", \ + "123.6, 123.6, 123.6, 127.9, 136.1", \ + "147.6, 147.6, 147.6, 152.1, 160.3", \ + "188.0, 188.0, 188.0, 192.5, 201.2", \ + "262.6, 262.6, 262.6, 267.1, 276.1"); + } + rise_transition (inslew_load_5x5__21) { + values ("42.5, 42.5, 42.5, 48.0, 58.8", \ + "50.9, 50.9, 50.9, 56.5, 67.3", \ + "66.4, 66.4, 66.4, 71.9, 82.8", \ + "95.6, 95.6, 95.6, 101.0, 112.0", \ + "151.8, 151.8, 151.8, 157.5, 168.5"); + } + cell_fall (inslew_load_5x5__21) { + values ("82.2, 82.2, 82.2, 86.5, 94.3", \ + "85.3, 85.3, 85.3, 89.5, 97.5", \ + "85.2, 85.2, 85.2, 89.4, 97.4", \ + "77.5, 77.5, 77.5, 81.8, 89.6", \ + "54.7, 54.7, 54.7, 59.2, 67.4"); + } + fall_transition (inslew_load_5x5__21) { + values ("32.6, 32.6, 32.6, 35.3, 40.6", \ + "35.9, 35.9, 35.9, 38.7, 43.9", \ + "41.8, 41.8, 41.8, 44.6, 49.9", \ + "52.8, 52.8, 52.8, 55.5, 61.0", \ + "73.7, 73.7, 73.7, 76.4, 81.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("91.8, 91.8, 91.8, 96.1, 103.9", \ + "102.2, 102.2, 102.2, 106.6, 114.6", \ + "116.4, 116.4, 116.4, 120.8, 129.0", \ + "137.9, 137.9, 137.9, 142.4, 150.9", \ + "174.8, 174.8, 174.8, 179.5, 188.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("37.5, 37.5, 37.5, 43.0, 53.8", \ + "44.1, 44.1, 44.1, 49.6, 60.4", \ + "56.0, 56.0, 56.0, 61.6, 72.4", \ + "78.4, 78.4, 78.4, 83.9, 94.9", \ + "121.7, 121.7, 121.7, 127.2, 138.1"); + } + cell_fall (inslew_load_5x5__21) { + values ("92.2, 92.2, 92.2, 96.4, 104.4", \ + "98.0, 98.0, 98.0, 102.1, 110.2", \ + "104.5, 104.5, 104.5, 108.7, 116.6", \ + "111.4, 111.4, 111.4, 115.8, 123.8", \ + "119.0, 119.0, 119.0, 123.6, 132.0"); + } + fall_transition (inslew_load_5x5__21) { + values ("35.4, 35.4, 35.4, 38.2, 43.4", \ + "39.3, 39.3, 39.3, 42.2, 47.4", \ + "46.8, 46.8, 46.8, 49.5, 54.9", \ + "60.7, 60.7, 60.7, 63.4, 68.9", \ + "87.9, 87.9, 87.9, 90.7, 96.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("737.3, 737.3, 737.3, 789.8, 894.9", \ + "838.0, 838.0, 838.0, 890.5, 995.5", \ + "1036.3, 1036.3, 1036.3, 1088.9, 1193.9", \ + "1424.6, 1424.6, 1424.6, 1477.1, 1582.2", \ + "2198.9, 2198.9, 2198.9, 2251.4, 2356.4"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("669.9, 669.9, 669.9, 722.4, 827.4", \ + "767.3, 767.3, 767.3, 819.8, 924.9", \ + "953.2, 953.2, 953.2, 1005.8, 1110.8", \ + "1316.3, 1316.3, 1316.3, 1368.8, 1473.9", \ + "2035.3, 2035.3, 2035.3, 2087.9, 2192.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("640.4, 640.4, 640.4, 693.0, 798.0", \ + "757.6, 757.6, 757.6, 810.2, 915.2", \ + "981.2, 981.2, 981.2, 1033.7, 1138.8", \ + "1417.6, 1417.6, 1417.6, 1470.2, 1575.2", \ + "2279.6, 2279.6, 2279.6, 2332.1, 2437.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("610.2, 610.2, 610.2, 662.8, 767.8", \ + "672.6, 672.6, 672.6, 725.1, 830.1", \ + "789.2, 789.2, 789.2, 841.7, 946.7", \ + "1014.3, 1014.3, 1014.3, 1066.8, 1171.9", \ + "1456.4, 1456.4, 1456.4, 1508.9, 1613.9"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("633.0, 633.0, 633.0, 685.5, 790.6", \ + "742.9, 742.9, 742.9, 795.4, 900.5", \ + "954.6, 954.6, 954.6, 1007.1, 1112.2", \ + "1370.1, 1370.1, 1370.1, 1422.6, 1527.6", \ + "2192.8, 2192.8, 2192.8, 2245.3, 2350.4"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("693.6, 693.6, 693.6, 746.1, 851.1", \ + "779.5, 779.5, 779.5, 832.0, 937.0", \ + "946.2, 946.2, 946.2, 998.8, 1103.8", \ + "1273.1, 1273.1, 1273.1, 1325.7, 1430.7", \ + "1920.6, 1920.6, 1920.6, 1973.1, 2078.1"); + } + } + } + } + + cell (nao2o22_x1) { + area : 0.0 ; + cell_leakage_power : 2.2 ; + leakage_power () { + when : "(!(i3) & !(i2) & i1 & i0)" ; + value : 0.00033 ; + } + leakage_power () { + when : "(!(i3) & i2 & !(i1) & i0)" ; + value : 3 ; + } + leakage_power () { + when : "((i0 & ((i1 & i2 & !(i3)) | (!(i1) & i3))) | (i1 & i2 & !(i3)))" ; + value : 5.9 ; + } + leakage_power () { + when : "(i1 & i3)" ; + value : 8.8 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & !(i3))" ; + value : 0.00017 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 0.00041 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3))" ; + value : 0.00021 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 7e-06 ; + } + pin (i3) { + direction : input ; + capacitance : 7.23 ; + } + pin (i2) { + direction : input ; + capacitance : 7.17 ; + } + pin (i1) { + direction : input ; + capacitance : 7.09 ; + } + pin (i0) { + direction : input ; + capacitance : 7.05 ; + } + pin (nq) { + function : "((!(i3) & !(i2)) | (!(i1) & !(i0)))" ; + direction : output ; + capacitance : 4.40 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("33.5, 33.5, 33.5, 44.3, 65.1", \ + "32.7, 32.7, 32.7, 43.7, 65.2", \ + "29.8, 29.8, 29.8, 41.4, 63.7", \ + "23.2, 23.2, 23.2, 35.2, 58.5", \ + "9.1, 9.1, 9.1, 21.4, 45.5"); + } + rise_transition (inslew_load_5x5__22) { + values ("79.0, 79.0, 79.0, 97.3, 134.1", \ + "109.0, 109.0, 109.0, 127.0, 163.3", \ + "166.8, 166.8, 166.8, 184.9, 221.8", \ + "282.6, 282.6, 282.6, 300.7, 336.8", \ + "513.8, 513.8, 513.8, 532.0, 568.2"); + } + cell_fall (inslew_load_5x5__22) { + values ("22.1, 22.1, 22.1, 30.2, 44.8", \ + "29.5, 29.5, 29.5, 38.4, 54.8", \ + "41.9, 41.9, 41.9, 51.5, 69.6", \ + "65.1, 65.1, 65.1, 75.3, 94.7", \ + "111.0, 111.0, 111.0, 121.4, 141.6"); + } + fall_transition (inslew_load_5x5__22) { + values ("31.4, 31.4, 31.4, 39.9, 56.4", \ + "53.8, 53.8, 53.8, 62.4, 79.3", \ + "96.6, 96.6, 96.6, 105.4, 122.6", \ + "180.9, 180.9, 180.9, 189.8, 207.5", \ + "348.9, 348.9, 348.9, 357.9, 375.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("24.2, 24.2, 24.2, 36.5, 58.9", \ + "32.1, 32.1, 32.1, 45.1, 69.2", \ + "44.9, 44.9, 44.9, 58.6, 84.5", \ + "68.6, 68.6, 68.6, 82.9, 110.3", \ + "115.2, 115.2, 115.2, 129.7, 158.1"); + } + rise_transition (inslew_load_5x5__22) { + values ("51.8, 51.8, 51.8, 70.7, 108.5", \ + "88.4, 88.4, 88.4, 107.4, 145.0", \ + "157.1, 157.1, 157.1, 176.4, 214.5", \ + "292.2, 292.2, 292.2, 311.7, 350.2", \ + "561.2, 561.2, 561.2, 580.7, 619.6"); + } + cell_fall (inslew_load_5x5__22) { + values ("11.2, 11.2, 11.2, 20.8, 36.7", \ + "9.6, 9.6, 9.6, 20.5, 39.1", \ + "4.5, 4.5, 4.5, 16.6, 37.9", \ + "-6.6, -6.6, -6.6, 6.1, 29.9", \ + "-29.5, -29.5, -29.5, -16.3, 9.0"); + } + fall_transition (inslew_load_5x5__22) { + values ("21.5, 21.5, 21.5, 30.4, 47.1", \ + "36.4, 36.4, 36.4, 45.7, 63.2", \ + "65.0, 65.0, 65.0, 74.6, 93.0", \ + "121.4, 121.4, 121.4, 131.2, 150.4", \ + "233.7, 233.7, 233.7, 243.7, 263.3"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("49.0, 49.0, 49.0, 59.4, 79.9", \ + "53.8, 53.8, 53.8, 64.5, 85.5", \ + "62.3, 62.3, 62.3, 73.2, 94.7", \ + "78.2, 78.2, 78.2, 89.4, 111.5", \ + "109.2, 109.2, 109.2, 120.7, 143.3"); + } + rise_transition (inslew_load_5x5__22) { + values ("105.5, 105.5, 105.5, 123.9, 161.0", \ + "143.9, 143.9, 143.9, 162.1, 198.7", \ + "219.5, 219.5, 219.5, 237.4, 273.4", \ + "367.9, 367.9, 367.9, 385.9, 423.8", \ + "666.3, 666.3, 666.3, 684.2, 720.2"); + } + cell_fall (inslew_load_5x5__22) { + values ("27.9, 27.9, 27.9, 34.7, 47.9", \ + "31.0, 31.0, 31.0, 38.5, 52.9", \ + "34.7, 34.7, 34.7, 43.0, 58.8", \ + "40.4, 40.4, 40.4, 49.3, 66.5", \ + "50.8, 50.8, 50.8, 60.0, 78.2"); + } + fall_transition (inslew_load_5x5__22) { + values ("41.6, 41.6, 41.6, 49.8, 66.1", \ + "61.2, 61.2, 61.2, 69.4, 85.7", \ + "99.2, 99.2, 99.2, 107.5, 124.0", \ + "174.3, 174.3, 174.3, 182.8, 199.6", \ + "324.1, 324.1, 324.1, 332.6, 349.6"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("40.4, 40.4, 40.4, 51.6, 73.2", \ + "54.6, 54.6, 54.6, 66.5, 89.3", \ + "79.2, 79.2, 79.2, 91.7, 115.8", \ + "125.7, 125.7, 125.7, 138.7, 164.0", \ + "217.2, 217.2, 217.2, 230.4, 256.6"); + } + rise_transition (inslew_load_5x5__22) { + values ("76.9, 76.9, 76.9, 96.0, 133.5", \ + "121.9, 121.9, 121.9, 140.6, 178.1", \ + "206.5, 206.5, 206.5, 225.4, 262.9", \ + "372.5, 372.5, 372.5, 391.5, 429.4", \ + "702.9, 702.9, 702.9, 722.1, 760.2"); + } + cell_fall (inslew_load_5x5__22) { + values ("18.6, 18.6, 18.6, 26.0, 39.8", \ + "14.0, 14.0, 14.0, 22.6, 38.3", \ + "2.1, 2.1, 2.1, 12.0, 30.1", \ + "-24.0, -24.0, -24.0, -13.1, 7.4", \ + "-78.2, -78.2, -78.2, -66.5, -44.0"); + } + fall_transition (inslew_load_5x5__22) { + values ("31.5, 31.5, 31.5, 39.8, 56.2", \ + "44.3, 44.3, 44.3, 52.8, 69.4", \ + "68.8, 68.8, 68.8, 77.6, 94.8", \ + "116.8, 116.8, 116.8, 125.9, 143.8", \ + "212.0, 212.0, 212.0, 221.4, 239.9"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__22) { + values ("214.4, 214.4, 214.4, 269.4, 379.5", \ + "286.3, 286.3, 286.3, 341.4, 451.5", \ + "430.3, 430.3, 430.3, 485.3, 595.4", \ + "718.1, 718.1, 718.1, 773.2, 883.3", \ + "1293.9, 1293.9, 1293.9, 1348.9, 1459.0"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("176.1, 176.1, 176.1, 231.2, 341.2", \ + "265.6, 265.6, 265.6, 320.6, 430.7", \ + "444.5, 444.5, 444.5, 499.5, 609.6", \ + "802.4, 802.4, 802.4, 857.4, 967.5", \ + "1518.1, 1518.1, 1518.1, 1573.1, 1683.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__22) { + values ("133.2, 133.2, 133.2, 188.2, 298.3", \ + "207.7, 207.7, 207.7, 262.7, 372.8", \ + "356.6, 356.6, 356.6, 411.7, 521.7", \ + "654.6, 654.6, 654.6, 709.6, 819.7", \ + "1250.5, 1250.5, 1250.5, 1305.5, 1415.6"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("100.9, 100.9, 100.9, 155.9, 266.0", \ + "150.4, 150.4, 150.4, 205.5, 315.5", \ + "249.5, 249.5, 249.5, 304.5, 414.6", \ + "447.6, 447.6, 447.6, 502.6, 612.7", \ + "843.8, 843.8, 843.8, 898.9, 1008.9"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__22) { + values ("296.5, 296.5, 296.5, 351.5, 461.6", \ + "394.0, 394.0, 394.0, 449.0, 559.1", \ + "588.9, 588.9, 588.9, 644.0, 754.0", \ + "978.9, 978.9, 978.9, 1033.9, 1144.0", \ + "1758.8, 1758.8, 1758.8, 1813.8, 1923.9"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("244.8, 244.8, 244.8, 299.8, 409.9", \ + "330.7, 330.7, 330.7, 385.7, 495.8", \ + "502.5, 502.5, 502.5, 557.6, 667.6", \ + "846.2, 846.2, 846.2, 901.2, 1011.3", \ + "1533.4, 1533.4, 1533.4, 1588.5, 1698.5"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__22) { + values ("211.4, 211.4, 211.4, 266.5, 376.5", \ + "307.6, 307.6, 307.6, 362.6, 472.7", \ + "500.0, 500.0, 500.0, 555.0, 665.1", \ + "884.7, 884.7, 884.7, 939.7, 1049.8", \ + "1654.1, 1654.1, 1654.1, 1709.2, 1819.2"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("168.3, 168.3, 168.3, 223.4, 333.4", \ + "213.0, 213.0, 213.0, 268.1, 378.1", \ + "302.5, 302.5, 302.5, 357.5, 467.6", \ + "481.3, 481.3, 481.3, 536.4, 646.4", \ + "839.1, 839.1, 839.1, 894.1, 1004.2"); + } + } + } + } + + cell (nao2o22_x4) { + area : 0.0 ; + cell_leakage_power : 6.2 ; + leakage_power () { + when : "(i0 & ((i1 & i2 & !(i3)) | (!(i1) & i2 & i3)))" ; + value : 7.4 ; + } + leakage_power () { + when : "(!(i3) & i2 & !(i1) & i0)" ; + value : 6.6 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3) | (!(i0) & i1 & i2 & !(i3)))" ; + value : 7.5 ; + } + leakage_power () { + when : "(i1 & i3)" ; + value : 8.3 ; + } + leakage_power () { + when : "(!((i0 | i1)) | (!(i2) & !(i3)))" ; + value : 1 ; + } + pin (i3) { + direction : input ; + capacitance : 4.88 ; + } + pin (i2) { + direction : input ; + capacitance : 4.93 ; + } + pin (i1) { + direction : input ; + capacitance : 4.89 ; + } + pin (i0) { + direction : input ; + capacitance : 4.81 ; + } + pin (nq) { + function : "(!((i0 | i1)) | (!(i2) & !(i3)))" ; + direction : output ; + capacitance : 4.20 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("94.0, 94.0, 94.0, 98.3, 106.1", \ + "99.4, 99.4, 99.4, 103.7, 111.7", \ + "107.1, 107.1, 107.1, 111.5, 119.7", \ + "118.9, 118.9, 118.9, 123.4, 131.9", \ + "137.8, 137.8, 137.8, 142.4, 151.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("36.2, 36.2, 36.2, 41.7, 52.5", \ + "43.2, 43.2, 43.2, 48.7, 59.5", \ + "56.1, 56.1, 56.1, 61.7, 72.5", \ + "80.3, 80.3, 80.3, 85.8, 96.8", \ + "128.8, 128.8, 128.8, 134.5, 145.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("87.9, 87.9, 87.9, 92.2, 100.1", \ + "96.1, 96.1, 96.1, 100.3, 108.3", \ + "105.0, 105.0, 105.0, 109.3, 117.1", \ + "114.9, 114.9, 114.9, 119.4, 127.5", \ + "127.9, 127.9, 127.9, 132.5, 141.2"); + } + fall_transition (inslew_load_5x5__21) { + values ("34.7, 34.7, 34.7, 37.5, 42.7", \ + "40.4, 40.4, 40.4, 43.2, 48.5", \ + "50.2, 50.2, 50.2, 52.9, 58.4", \ + "68.0, 68.0, 68.0, 70.7, 76.1", \ + "102.2, 102.2, 102.2, 105.0, 110.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("83.4, 83.4, 83.4, 87.7, 95.3", \ + "96.6, 96.6, 96.6, 101.0, 108.8", \ + "114.9, 114.9, 114.9, 119.2, 127.4", \ + "144.9, 144.9, 144.9, 149.3, 157.8", \ + "198.1, 198.1, 198.1, 202.8, 211.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("30.2, 30.2, 30.2, 35.7, 46.4", \ + "37.7, 37.7, 37.7, 43.2, 54.0", \ + "50.7, 50.7, 50.7, 56.2, 67.1", \ + "74.2, 74.2, 74.2, 79.7, 90.7", \ + "120.8, 120.8, 120.8, 126.3, 137.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("78.9, 78.9, 78.9, 83.2, 91.0", \ + "81.4, 81.4, 81.4, 85.5, 93.6", \ + "78.6, 78.6, 78.6, 82.8, 90.8", \ + "64.8, 64.8, 64.8, 69.2, 77.1", \ + "29.3, 29.3, 29.3, 33.9, 42.2"); + } + fall_transition (inslew_load_5x5__21) { + values ("32.5, 32.5, 32.5, 35.3, 40.5", \ + "37.0, 37.0, 37.0, 39.9, 45.1", \ + "44.7, 44.7, 44.7, 47.5, 52.9", \ + "58.4, 58.4, 58.4, 61.1, 66.6", \ + "84.0, 84.0, 84.0, 86.8, 92.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("109.2, 109.2, 109.2, 113.5, 121.5", \ + "117.3, 117.3, 117.3, 121.6, 129.8", \ + "130.0, 130.0, 130.0, 134.4, 142.7", \ + "151.6, 151.6, 151.6, 156.1, 164.8", \ + "190.1, 190.1, 190.1, 194.6, 203.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("41.4, 41.4, 41.4, 46.9, 57.7", \ + "49.1, 49.1, 49.1, 54.7, 65.5", \ + "62.9, 62.9, 62.9, 68.5, 79.4", \ + "90.1, 90.1, 90.1, 95.5, 106.5", \ + "143.9, 143.9, 143.9, 149.7, 160.6"); + } + cell_fall (inslew_load_5x5__21) { + values ("98.7, 98.7, 98.7, 102.8, 110.9", \ + "104.2, 104.2, 104.2, 108.4, 116.4", \ + "108.9, 108.9, 108.9, 113.2, 121.0", \ + "111.0, 111.0, 111.0, 115.6, 123.7", \ + "108.2, 108.2, 108.2, 112.8, 121.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("38.6, 38.6, 38.6, 41.5, 46.7", \ + "43.6, 43.6, 43.6, 46.4, 51.8", \ + "52.8, 52.8, 52.8, 55.5, 61.1", \ + "69.9, 69.9, 69.9, 72.6, 78.0", \ + "102.7, 102.7, 102.7, 105.5, 110.9"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("100.7, 100.7, 100.7, 105.0, 112.8", \ + "118.0, 118.0, 118.0, 122.3, 130.4", \ + "145.4, 145.4, 145.4, 149.8, 158.0", \ + "192.1, 192.1, 192.1, 196.6, 205.3", \ + "278.5, 278.5, 278.5, 283.1, 292.0"); + } + rise_transition (inslew_load_5x5__21) { + values ("35.6, 35.6, 35.6, 41.1, 51.9", \ + "44.4, 44.4, 44.4, 49.9, 60.7", \ + "59.0, 59.0, 59.0, 64.6, 75.5", \ + "86.8, 86.8, 86.8, 92.2, 103.2", \ + "141.6, 141.6, 141.6, 147.3, 158.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("89.4, 89.4, 89.4, 93.6, 101.6", \ + "88.5, 88.5, 88.5, 92.6, 100.7", \ + "79.6, 79.6, 79.6, 83.8, 91.8", \ + "52.8, 52.8, 52.8, 57.2, 65.1", \ + "-11.1, -11.1, -11.1, -6.5, 1.8"); + } + fall_transition (inslew_load_5x5__21) { + values ("36.1, 36.1, 36.1, 39.0, 44.2", \ + "39.8, 39.8, 39.8, 42.6, 47.9", \ + "46.3, 46.3, 46.3, 49.1, 54.5", \ + "57.9, 57.9, 57.9, 60.6, 66.1", \ + "79.4, 79.4, 79.4, 82.2, 87.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("713.1, 713.1, 713.1, 765.6, 870.6", \ + "845.4, 845.4, 845.4, 897.9, 1003.0", \ + "1103.1, 1103.1, 1103.1, 1155.6, 1260.6", \ + "1610.5, 1610.5, 1610.5, 1663.0, 1768.0", \ + "2629.5, 2629.5, 2629.5, 2682.1, 2787.1"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("715.6, 715.6, 715.6, 768.1, 873.2", \ + "822.3, 822.3, 822.3, 874.9, 979.9", \ + "1019.9, 1019.9, 1019.9, 1072.5, 1177.5", \ + "1399.2, 1399.2, 1399.2, 1451.7, 1556.8", \ + "2145.1, 2145.1, 2145.1, 2197.6, 2302.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("597.1, 597.1, 597.1, 649.6, 754.7", \ + "722.8, 722.8, 722.8, 775.3, 880.4", \ + "959.9, 959.9, 959.9, 1012.4, 1117.5", \ + "1419.8, 1419.8, 1419.8, 1472.3, 1577.4", \ + "2338.1, 2338.1, 2338.1, 2390.7, 2495.7"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("656.6, 656.6, 656.6, 709.1, 814.2", \ + "734.6, 734.6, 734.6, 787.1, 892.2", \ + "877.1, 877.1, 877.1, 929.6, 1034.6", \ + "1145.7, 1145.7, 1145.7, 1198.2, 1303.3", \ + "1666.8, 1666.8, 1666.8, 1719.3, 1824.3"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("819.8, 819.8, 819.8, 872.3, 977.4", \ + "969.2, 969.2, 969.2, 1021.7, 1126.8", \ + "1257.0, 1257.0, 1257.0, 1309.5, 1414.5", \ + "1829.9, 1829.9, 1829.9, 1882.4, 1987.5", \ + "2978.4, 2978.4, 2978.4, 3030.9, 3135.9"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("823.3, 823.3, 823.3, 875.8, 980.8", \ + "925.7, 925.7, 925.7, 978.2, 1083.2", \ + "1122.4, 1122.4, 1122.4, 1175.0, 1280.0", \ + "1504.0, 1504.0, 1504.0, 1556.6, 1661.6", \ + "2254.9, 2254.9, 2254.9, 2307.5, 2412.5"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__21) { + values ("708.4, 708.4, 708.4, 760.9, 865.9", \ + "860.0, 860.0, 860.0, 912.5, 1017.5", \ + "1142.5, 1142.5, 1142.5, 1195.0, 1300.0", \ + "1696.5, 1696.5, 1696.5, 1749.0, 1854.1", \ + "2803.9, 2803.9, 2803.9, 2856.5, 2961.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("754.2, 754.2, 754.2, 806.8, 911.8", \ + "820.3, 820.3, 820.3, 872.8, 977.9", \ + "942.7, 942.7, 942.7, 995.2, 1100.2", \ + "1172.7, 1172.7, 1172.7, 1225.2, 1330.2", \ + "1616.3, 1616.3, 1616.3, 1668.8, 1773.8"); + } + } + } + } + + cell (nmx2_x1) { + area : 0.0 ; + cell_leakage_power : 3.8 ; + leakage_power () { + when : "(i1 & i0 & cmd)" ; + value : 6.9 ; + } + leakage_power () { + when : "(i1 & !(i0) & cmd)" ; + value : 7 ; + } + leakage_power () { + when : "(cmd & !(i1))" ; + value : 1 ; + } + leakage_power () { + when : "(i1 & i0 & !(cmd))" ; + value : 5.9 ; + } + leakage_power () { + when : "(!(i1) & i0 & !(cmd))" ; + value : 6 ; + } + leakage_power () { + when : "(i1 & !(i0) & !(cmd))" ; + value : 0.00023 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & !(cmd))" ; + value : 0.00013 ; + } + pin (i1) { + direction : input ; + capacitance : 7.03 ; + } + pin (i0) { + direction : input ; + capacitance : 6.56 ; + } + pin (cmd) { + direction : input ; + capacitance : 10.20 ; + } + pin (nq) { + function : "((!(i1) & (!(i0) | cmd)) | (!(i0) & !(cmd)))" ; + direction : output ; + capacitance : 4.04 ; + timing (maxd_nq_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__23) { + values ("48.3, 48.3, 48.3, 60.5, 82.8", \ + "55.1, 55.1, 55.1, 67.5, 90.4", \ + "61.9, 61.9, 61.9, 74.7, 98.5", \ + "69.4, 69.4, 69.4, 82.8, 107.8", \ + "80.3, 80.3, 80.3, 94.0, 120.2"); + } + rise_transition (inslew_load_5x5__23) { + values ("38.4, 38.4, 38.4, 57.9, 96.2", \ + "53.8, 53.8, 53.8, 73.0, 111.4", \ + "79.4, 79.4, 79.4, 98.6, 136.8", \ + "126.1, 126.1, 126.1, 145.4, 183.6", \ + "215.7, 215.7, 215.7, 235.2, 273.8"); + } + cell_fall (inslew_load_5x5__23) { + values ("46.8, 46.8, 46.8, 56.6, 72.7", \ + "52.4, 52.4, 52.4, 62.9, 80.4", \ + "59.7, 59.7, 59.7, 70.6, 90.0", \ + "69.8, 69.8, 69.8, 81.9, 102.9", \ + "88.3, 88.3, 88.3, 99.8, 123.4"); + } + fall_transition (inslew_load_5x5__23) { + values ("27.6, 27.6, 27.6, 35.9, 51.5", \ + "36.4, 36.4, 36.4, 44.7, 60.6", \ + "52.8, 52.8, 52.8, 61.3, 77.6", \ + "84.7, 84.7, 84.7, 93.3, 110.1", \ + "147.9, 147.9, 147.9, 156.7, 173.8"); + } + } + timing (maxd_nq_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("26.1, 26.1, 26.1, 38.6, 61.5", \ + "36.6, 36.6, 36.6, 49.7, 74.1", \ + "54.0, 54.0, 54.0, 67.7, 93.7", \ + "86.8, 86.8, 86.8, 100.9, 128.3", \ + "151.3, 151.3, 151.3, 165.7, 194.0"); + } + rise_transition (inslew_load_5x5__23) { + values ("53.4, 53.4, 53.4, 72.7, 111.1", \ + "93.4, 93.4, 93.4, 112.7, 150.9", \ + "167.9, 167.9, 167.9, 187.4, 225.9", \ + "314.0, 314.0, 314.0, 333.6, 372.6", \ + "604.8, 604.8, 604.8, 624.5, 663.8"); + } + cell_fall (inslew_load_5x5__23) { + values ("9.4, 9.4, 9.4, 18.6, 33.6", \ + "5.9, 5.9, 5.9, 16.4, 34.2", \ + "-2.7, -2.7, -2.7, 8.9, 29.5", \ + "-20.9, -20.9, -20.9, -8.4, 14.5", \ + "-58.0, -58.0, -58.0, -45.0, -20.4"); + } + fall_transition (inslew_load_5x5__23) { + values ("20.1, 20.1, 20.1, 28.4, 43.9", \ + "33.6, 33.6, 33.6, 42.3, 58.6", \ + "59.5, 59.5, 59.5, 68.5, 85.7", \ + "110.6, 110.6, 110.6, 119.9, 137.9", \ + "212.4, 212.4, 212.4, 221.8, 240.4"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("47.9, 47.9, 47.9, 58.6, 79.7", \ + "55.5, 55.5, 55.5, 66.4, 88.1", \ + "69.4, 69.4, 69.4, 80.6, 102.6", \ + "96.5, 96.5, 96.5, 107.8, 130.3", \ + "149.9, 149.9, 149.9, 161.4, 184.3"); + } + rise_transition (inslew_load_5x5__23) { + values ("101.7, 101.7, 101.7, 120.4, 158.2", \ + "144.5, 144.5, 144.5, 163.0, 200.4", \ + "227.9, 227.9, 227.9, 246.2, 282.9", \ + "392.0, 392.0, 392.0, 412.2, 448.6", \ + "721.1, 721.1, 721.1, 739.5, 776.1"); + } + cell_fall (inslew_load_5x5__23) { + values ("21.6, 21.6, 21.6, 28.2, 40.6", \ + "22.1, 22.1, 22.1, 29.5, 43.3", \ + "21.2, 21.2, 21.2, 29.3, 44.6", \ + "17.8, 17.8, 17.8, 26.5, 43.2", \ + "10.2, 10.2, 10.2, 19.2, 36.9"); + } + fall_transition (inslew_load_5x5__23) { + values ("35.0, 35.0, 35.0, 42.6, 57.6", \ + "52.5, 52.5, 52.5, 60.1, 75.2", \ + "86.4, 86.4, 86.4, 94.2, 109.5", \ + "153.6, 153.6, 153.6, 161.5, 177.1", \ + "287.4, 287.4, 287.4, 295.4, 311.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("47.9, 47.9, 47.9, 58.6, 79.7", \ + "55.5, 55.5, 55.5, 66.4, 88.1", \ + "69.4, 69.4, 69.4, 80.6, 102.6", \ + "96.5, 96.5, 96.5, 107.8, 130.3", \ + "149.9, 149.9, 149.9, 161.4, 184.3"); + } + rise_transition (inslew_load_5x5__23) { + values ("101.7, 101.7, 101.7, 120.4, 158.2", \ + "144.5, 144.5, 144.5, 163.0, 200.4", \ + "227.9, 227.9, 227.9, 246.2, 282.9", \ + "392.0, 392.0, 392.0, 412.2, 448.6", \ + "721.1, 721.1, 721.1, 739.5, 776.1"); + } + cell_fall (inslew_load_5x5__23) { + values ("21.6, 21.6, 21.6, 28.2, 40.6", \ + "22.1, 22.1, 22.1, 29.5, 43.3", \ + "21.2, 21.2, 21.2, 29.3, 44.6", \ + "17.8, 17.8, 17.8, 26.5, 43.2", \ + "10.2, 10.2, 10.2, 19.2, 36.9"); + } + fall_transition (inslew_load_5x5__23) { + values ("35.0, 35.0, 35.0, 42.6, 57.6", \ + "52.5, 52.5, 52.5, 60.1, 75.2", \ + "86.4, 86.4, 86.4, 94.2, 109.5", \ + "153.6, 153.6, 153.6, 161.5, 177.1", \ + "287.4, 287.4, 287.4, 295.4, 311.2"); + } + } + internal_power (energy_pos_nq_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__23) { + values ("239.9, 239.9, 239.9, 290.3, 391.2", \ + "300.7, 300.7, 300.7, 351.2, 452.1", \ + "419.9, 419.9, 419.9, 470.3, 571.2", \ + "656.0, 656.0, 656.0, 706.4, 807.3", \ + "1126.3, 1126.3, 1126.3, 1176.7, 1277.6"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("259.6, 259.6, 259.6, 310.1, 411.0", \ + "332.2, 332.2, 332.2, 382.7, 483.6", \ + "475.5, 475.5, 475.5, 526.0, 626.9", \ + "760.8, 760.8, 760.8, 811.2, 912.1", \ + "1330.3, 1330.3, 1330.3, 1380.7, 1481.6"); + } + } + internal_power (energy_neg_nq_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__23) { + values ("127.9, 127.9, 127.9, 178.4, 279.3", \ + "201.9, 201.9, 201.9, 252.3, 353.2", \ + "349.7, 349.7, 349.7, 400.2, 501.1", \ + "645.4, 645.4, 645.4, 695.8, 796.7", \ + "1236.8, 1236.8, 1236.8, 1287.2, 1388.1"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("89.5, 89.5, 89.5, 140.0, 240.9", \ + "132.2, 132.2, 132.2, 182.6, 283.5", \ + "217.4, 217.4, 217.4, 267.9, 368.8", \ + "387.9, 387.9, 387.9, 438.4, 539.3", \ + "729.0, 729.0, 729.0, 779.4, 880.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__23) { + values ("258.6, 258.6, 258.6, 309.1, 410.0", \ + "356.9, 356.9, 356.9, 407.3, 508.2", \ + "553.4, 553.4, 553.4, 603.9, 704.8", \ + "946.5, 946.5, 946.5, 996.9, 1097.8", \ + "1732.6, 1732.6, 1732.6, 1783.1, 1884.0"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("197.3, 197.3, 197.3, 247.7, 348.6", \ + "270.7, 270.7, 270.7, 321.2, 422.1", \ + "417.6, 417.6, 417.6, 468.1, 569.0", \ + "711.5, 711.5, 711.5, 761.9, 862.8", \ + "1299.1, 1299.1, 1299.1, 1349.6, 1450.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__23) { + values ("258.6, 258.6, 258.6, 309.1, 410.0", \ + "356.9, 356.9, 356.9, 407.3, 508.2", \ + "553.4, 553.4, 553.4, 603.9, 704.8", \ + "946.5, 946.5, 946.5, 996.9, 1097.8", \ + "1732.6, 1732.6, 1732.6, 1783.1, 1884.0"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("197.3, 197.3, 197.3, 247.7, 348.6", \ + "270.7, 270.7, 270.7, 321.2, 422.1", \ + "417.6, 417.6, 417.6, 468.1, 569.0", \ + "711.5, 711.5, 711.5, 761.9, 862.8", \ + "1299.1, 1299.1, 1299.1, 1349.6, 1450.5"); + } + } + } + } + + cell (nmx2_x4) { + area : 0.0 ; + cell_leakage_power : 4.9 ; + leakage_power () { + when : "(cmd & i1)" ; + value : 8.5 ; + } + leakage_power () { + when : "(cmd & !(i1))" ; + value : 2.5 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 7.2 ; + } + leakage_power () { + when : "(!(cmd) & !(i0))" ; + value : 1.3 ; + } + pin (i1) { + direction : input ; + capacitance : 4.91 ; + } + pin (i0) { + direction : input ; + capacitance : 4.68 ; + } + pin (cmd) { + direction : input ; + capacitance : 9.13 ; + } + pin (nq) { + function : "((!(i0) & (!(i1) | !(cmd))) | (!(i1) & cmd))" ; + direction : output ; + capacitance : 4.20 ; + timing (maxd_nq_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("126.4, 126.4, 126.4, 130.7, 138.6", \ + "137.7, 137.7, 137.7, 142.1, 150.1", \ + "152.3, 152.3, 152.3, 156.6, 164.8", \ + "174.4, 174.4, 174.4, 178.8, 187.0", \ + "210.8, 210.8, 210.8, 215.3, 223.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("39.7, 39.7, 39.7, 45.2, 56.0", \ + "43.4, 43.4, 43.4, 48.9, 59.7", \ + "49.3, 49.3, 49.3, 54.9, 65.7", \ + "60.0, 60.0, 60.0, 65.6, 76.5", \ + "80.0, 80.0, 80.0, 85.5, 96.5"); + } + cell_fall (inslew_load_5x5__21) { + values ("110.1, 110.1, 110.1, 114.6, 122.2", \ + "117.3, 117.3, 117.3, 121.7, 129.5", \ + "125.9, 125.9, 125.9, 130.1, 138.1", \ + "136.0, 136.0, 136.0, 140.2, 148.2", \ + "149.7, 149.7, 149.7, 154.0, 161.9"); + } + fall_transition (inslew_load_5x5__21) { + values ("29.3, 29.3, 29.3, 32.0, 37.3", \ + "31.3, 31.3, 31.3, 34.0, 39.3", \ + "34.7, 34.7, 34.7, 37.5, 42.7", \ + "41.0, 41.0, 41.0, 43.8, 49.1", \ + "53.0, 53.0, 53.0, 55.7, 61.2"); + } + } + timing (maxd_nq_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("110.8, 110.8, 110.8, 115.1, 123.1", \ + "124.0, 124.0, 124.0, 128.4, 136.6", \ + "143.5, 143.5, 143.5, 148.0, 156.3", \ + "175.1, 175.1, 175.1, 179.6, 188.3", \ + "231.3, 231.3, 231.3, 235.9, 244.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("43.7, 43.7, 43.7, 49.2, 60.0", \ + "51.8, 51.8, 51.8, 57.3, 68.2", \ + "66.6, 66.6, 66.6, 72.2, 83.1", \ + "94.7, 94.7, 94.7, 100.2, 111.2", \ + "149.0, 149.0, 149.0, 154.8, 165.7"); + } + cell_fall (inslew_load_5x5__21) { + values ("83.7, 83.7, 83.7, 88.1, 95.8", \ + "89.8, 89.8, 89.8, 94.2, 102.0", \ + "95.0, 95.0, 95.0, 99.1, 107.2", \ + "97.8, 97.8, 97.8, 102.1, 109.9", \ + "95.9, 95.9, 95.9, 100.5, 108.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("29.1, 29.1, 29.1, 31.8, 37.1", \ + "32.6, 32.6, 32.6, 35.4, 40.6", \ + "38.8, 38.8, 38.8, 41.7, 46.9", \ + "50.6, 50.6, 50.6, 53.3, 58.8", \ + "72.9, 72.9, 72.9, 75.6, 81.0"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("139.2, 139.2, 139.2, 143.6, 151.8", \ + "148.7, 148.7, 148.7, 153.1, 161.3", \ + "164.3, 164.3, 164.3, 168.8, 177.3", \ + "191.6, 191.6, 191.6, 196.2, 205.0", \ + "242.7, 242.7, 242.7, 247.2, 256.2"); + } + rise_transition (inslew_load_5x5__21) { + values ("55.4, 55.4, 55.4, 60.9, 71.8", \ + "63.6, 63.6, 63.6, 69.2, 80.1", \ + "79.6, 79.6, 79.6, 85.0, 96.0", \ + "110.5, 110.5, 110.5, 116.0, 126.9", \ + "171.3, 171.3, 171.3, 177.0, 188.1"); + } + cell_fall (inslew_load_5x5__21) { + values ("97.3, 97.3, 97.3, 101.7, 109.5", \ + "105.7, 105.7, 105.7, 109.9, 117.9", \ + "116.6, 116.6, 116.6, 120.8, 128.8", \ + "132.1, 132.1, 132.1, 136.5, 144.5", \ + "156.5, 156.5, 156.5, 161.1, 169.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("32.6, 32.6, 32.6, 35.4, 40.6", \ + "36.7, 36.7, 36.7, 39.5, 44.7", \ + "44.3, 44.3, 44.3, 47.1, 52.5", \ + "58.8, 58.8, 58.8, 61.4, 66.9", \ + "86.9, 86.9, 86.9, 89.6, 95.0"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("139.2, 139.2, 139.2, 143.6, 151.8", \ + "148.7, 148.7, 148.7, 153.1, 161.3", \ + "164.3, 164.3, 164.3, 168.8, 177.3", \ + "191.6, 191.6, 191.6, 196.2, 205.0", \ + "242.7, 242.7, 242.7, 247.2, 256.2"); + } + rise_transition (inslew_load_5x5__21) { + values ("55.4, 55.4, 55.4, 60.9, 71.8", \ + "63.6, 63.6, 63.6, 69.2, 80.1", \ + "79.6, 79.6, 79.6, 85.0, 96.0", \ + "110.5, 110.5, 110.5, 116.0, 126.9", \ + "171.3, 171.3, 171.3, 177.0, 188.1"); + } + cell_fall (inslew_load_5x5__21) { + values ("97.3, 97.3, 97.3, 101.7, 109.5", \ + "105.7, 105.7, 105.7, 109.9, 117.9", \ + "116.6, 116.6, 116.6, 120.8, 128.8", \ + "132.1, 132.1, 132.1, 136.5, 144.5", \ + "156.5, 156.5, 156.5, 161.1, 169.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("32.6, 32.6, 32.6, 35.4, 40.6", \ + "36.7, 36.7, 36.7, 39.5, 44.7", \ + "44.3, 44.3, 44.3, 47.1, 52.5", \ + "58.8, 58.8, 58.8, 61.4, 66.9", \ + "86.9, 86.9, 86.9, 89.6, 95.0"); + } + } + internal_power (energy_pos_nq_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__21) { + values ("721.6, 721.6, 721.6, 774.1, 879.1", \ + "812.4, 812.4, 812.4, 864.9, 969.9", \ + "978.9, 978.9, 978.9, 1031.4, 1136.4", \ + "1302.1, 1302.1, 1302.1, 1354.6, 1459.7", \ + "1937.6, 1937.6, 1937.6, 1990.1, 2095.1"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("724.7, 724.7, 724.7, 777.2, 882.2", \ + "809.9, 809.9, 809.9, 862.4, 967.5", \ + "973.3, 973.3, 973.3, 1025.8, 1130.8", \ + "1292.7, 1292.7, 1292.7, 1345.2, 1450.3", \ + "1924.5, 1924.5, 1924.5, 1977.0, 2082.1"); + } + } + internal_power (energy_neg_nq_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__21) { + values ("659.9, 659.9, 659.9, 712.4, 817.4", \ + "772.8, 772.8, 772.8, 825.3, 930.4", \ + "989.0, 989.0, 989.0, 1041.5, 1146.5", \ + "1409.7, 1409.7, 1409.7, 1462.2, 1567.2", \ + "2242.2, 2242.2, 2242.2, 2294.7, 2399.7"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("598.7, 598.7, 598.7, 651.3, 756.3", \ + "670.4, 670.4, 670.4, 722.9, 828.0", \ + "804.6, 804.6, 804.6, 857.1, 962.2", \ + "1065.0, 1065.0, 1065.0, 1117.5, 1222.6", \ + "1576.7, 1576.7, 1576.7, 1629.2, 1734.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("852.7, 852.7, 852.7, 905.2, 1010.2", \ + "981.0, 981.0, 981.0, 1033.5, 1138.6", \ + "1234.1, 1234.1, 1234.1, 1286.6, 1391.7", \ + "1733.8, 1733.8, 1733.8, 1786.3, 1891.3", \ + "2732.2, 2732.2, 2732.2, 2784.8, 2889.8"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("705.2, 705.2, 705.2, 757.7, 862.7", \ + "800.6, 800.6, 800.6, 853.1, 958.1", \ + "985.4, 985.4, 985.4, 1037.9, 1143.0", \ + "1348.4, 1348.4, 1348.4, 1400.9, 1505.9", \ + "2067.8, 2067.8, 2067.8, 2120.3, 2225.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("852.7, 852.7, 852.7, 905.2, 1010.2", \ + "981.0, 981.0, 981.0, 1033.5, 1138.6", \ + "1234.1, 1234.1, 1234.1, 1286.6, 1391.7", \ + "1733.8, 1733.8, 1733.8, 1786.3, 1891.3", \ + "2732.2, 2732.2, 2732.2, 2784.8, 2889.8"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("705.2, 705.2, 705.2, 757.7, 862.7", \ + "800.6, 800.6, 800.6, 853.1, 958.1", \ + "985.4, 985.4, 985.4, 1037.9, 1143.0", \ + "1348.4, 1348.4, 1348.4, 1400.9, 1505.9", \ + "2067.8, 2067.8, 2067.8, 2120.3, 2225.3"); + } + } + } + } + + cell (nmx3_x1) { + area : 0.0 ; + cell_leakage_power : 2.1 ; + leakage_power () { + when : "(cmd0 & cmd1 & i0 & i1)" ; + value : 4.3 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i0) & i1)" ; + value : 3.9 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & i0 & i2) | (!(cmd0) & cmd1 & i0 & i1 & i2))" ; + value : 3 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0 & cmd1 & !(cmd0))" ; + value : 2.9 ; + } + leakage_power () { + when : "((cmd0 & ((cmd1 & !(i1)) | (!(cmd1) & !(i0) & i2))) | (!(cmd0) & cmd1 & i0 & !(i2)))" ; + value : 2.6 ; + } + leakage_power () { + when : "(i2 & i1 & i0 & !(cmd1) & !(cmd0))" ; + value : 1.7 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0 & !(cmd1) & !(cmd0))" ; + value : 1.6 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i2)) | (!(cmd0) & ((cmd1 & !(i0)) | (!(cmd1) & i0 & !(i1)))))" ; + value : 1.3 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & !(i0) & i2)" ; + value : 0.00025 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & !(i0) & !(i2))" ; + value : 0.0002 ; + } + pin (i2) { + direction : input ; + capacitance : 3.83 ; + } + pin (i1) { + direction : input ; + capacitance : 3.91 ; + } + pin (i0) { + direction : input ; + capacitance : 3.95 ; + } + pin (cmd1) { + direction : input ; + capacitance : 6.90 ; + } + pin (cmd0) { + direction : input ; + capacitance : 6.83 ; + } + pin (nq) { + function : "((!(i0) & ((!(i1) & (!(cmd0) | !(i2) | cmd1)) | !(cmd0) | (!(i2) & !(cmd1)))) | (!(i1) & cmd0 & (!(i2) | cmd1)) | (cmd0 & !(i2) & !(cmd1)))" ; + direction : output ; + capacitance : 4.51 ; + timing (maxd_nq_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__24) { + values ("132.9, 132.9, 132.9, 169.3, 242.3", \ + "143.8, 143.8, 143.8, 180.1, 253.0", \ + "152.1, 152.1, 152.1, 188.5, 261.4", \ + "160.2, 160.2, 160.2, 197.2, 270.5", \ + "171.7, 171.7, 171.7, 209.2, 282.3"); + } + rise_transition (inslew_load_5x5__24) { + values ("197.5, 197.5, 197.5, 263.6, 396.1", \ + "228.8, 228.8, 228.8, 294.7, 427.1", \ + "273.3, 273.3, 273.3, 338.7, 470.6", \ + "350.8, 350.8, 350.8, 416.4, 547.8", \ + "498.5, 498.5, 498.5, 565.0, 695.6"); + } + cell_fall (inslew_load_5x5__24) { + values ("65.6, 65.6, 65.6, 77.2, 99.1", \ + "74.4, 74.4, 74.4, 86.9, 110.1", \ + "87.3, 87.3, 87.3, 100.9, 126.2", \ + "108.5, 108.5, 108.5, 123.5, 151.4", \ + "146.8, 146.8, 146.8, 163.1, 194.4"); + } + fall_transition (inslew_load_5x5__24) { + values ("49.7, 49.7, 49.7, 63.3, 90.5", \ + "59.6, 59.6, 59.6, 73.4, 100.5", \ + "78.4, 78.4, 78.4, 92.4, 119.7", \ + "114.7, 114.7, 114.7, 129.1, 157.2", \ + "186.9, 186.9, 186.9, 201.5, 230.2"); + } + } + timing (maxd_nq_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__24) { + values ("72.1, 72.1, 72.1, 109.6, 183.6", \ + "71.6, 71.6, 71.6, 109.9, 184.3", \ + "79.5, 79.5, 79.5, 118.7, 193.7", \ + "86.3, 86.3, 86.3, 126.5, 203.3", \ + "92.3, 92.3, 92.3, 133.8, 212.7"); + } + rise_transition (inslew_load_5x5__24) { + values ("81.2, 81.2, 81.2, 149.1, 286.4", \ + "88.1, 88.1, 88.1, 155.4, 291.9", \ + "122.2, 122.2, 122.2, 188.7, 324.0", \ + "178.7, 178.7, 178.7, 245.2, 378.5", \ + "283.4, 283.4, 283.4, 349.3, 481.8"); + } + cell_fall (inslew_load_5x5__24) { + values ("54.0, 54.0, 54.0, 72.4, 103.1", \ + "60.3, 60.3, 60.3, 80.8, 114.5", \ + "67.9, 67.9, 67.9, 91.2, 129.7", \ + "78.1, 78.1, 78.1, 104.9, 149.6", \ + "95.3, 95.3, 95.3, 125.1, 177.2"); + } + fall_transition (inslew_load_5x5__24) { + values ("36.6, 36.6, 36.6, 56.7, 95.8", \ + "44.4, 44.4, 44.4, 65.1, 104.6", \ + "58.9, 58.9, 58.9, 80.3, 120.9", \ + "87.0, 87.0, 87.0, 108.9, 151.2", \ + "141.0, 141.0, 141.0, 164.7, 208.6"); + } + } + timing (maxd_nq_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("90.6, 90.6, 90.6, 114.7, 162.8", \ + "105.7, 105.7, 105.7, 130.1, 178.6", \ + "132.9, 132.9, 132.9, 158.0, 207.0", \ + "185.8, 185.8, 185.8, 211.0, 260.9", \ + "290.3, 290.3, 290.3, 316.0, 366.8"); + } + rise_transition (inslew_load_5x5__24) { + values ("173.2, 173.2, 173.2, 217.5, 306.6", \ + "224.7, 224.7, 224.7, 268.5, 357.0", \ + "323.7, 323.7, 323.7, 366.9, 454.2", \ + "521.0, 521.0, 521.0, 563.7, 649.5", \ + "916.1, 916.1, 916.1, 958.3, 1043.1"); + } + cell_fall (inslew_load_5x5__24) { + values ("35.1, 35.1, 35.1, 48.5, 74.5", \ + "32.9, 32.9, 32.9, 47.1, 74.4", \ + "25.7, 25.7, 25.7, 41.4, 71.0", \ + "7.9, 7.9, 7.9, 25.2, 57.9", \ + "-30.4, -30.4, -30.4, -11.8, 23.8"); + } + fall_transition (inslew_load_5x5__24) { + values ("61.0, 61.0, 61.0, 80.4, 119.5", \ + "76.2, 76.2, 76.2, 95.6, 134.0", \ + "106.3, 106.3, 106.3, 125.7, 164.0", \ + "166.0, 166.0, 166.0, 185.6, 224.3", \ + "284.6, 284.6, 284.6, 304.5, 343.8"); + } + } + timing (maxd_nq_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("56.7, 56.7, 56.7, 95.4, 170.1", \ + "78.7, 78.7, 78.7, 118.6, 194.7", \ + "115.0, 115.0, 115.0, 156.3, 234.8", \ + "181.3, 181.3, 181.3, 224.0, 305.9", \ + "310.7, 310.7, 310.7, 354.4, 439.2"); + } + rise_transition (inslew_load_5x5__24) { + values ("97.1, 97.1, 97.1, 164.2, 300.7", \ + "153.1, 153.1, 153.1, 219.2, 353.5", \ + "251.9, 251.9, 251.9, 318.9, 450.3", \ + "441.6, 441.6, 441.6, 507.2, 641.2", \ + "816.9, 816.9, 816.9, 882.7, 1013.6"); + } + cell_fall (inslew_load_5x5__24) { + values ("18.0, 18.0, 18.0, 34.7, 63.6", \ + "12.3, 12.3, 12.3, 32.9, 66.4", \ + "-3.5, -3.5, -3.5, 21.4, 62.2", \ + "-39.7, -39.7, -39.7, -10.4, 39.1", \ + "-115.6, -115.6, -115.6, -82.7, -24.4"); + } + fall_transition (inslew_load_5x5__24) { + values ("30.5, 30.5, 30.5, 50.3, 89.7", \ + "40.7, 40.7, 40.7, 61.7, 101.4", \ + "59.6, 59.6, 59.6, 81.8, 123.5", \ + "95.8, 95.8, 95.8, 119.3, 163.5", \ + "167.0, 167.0, 167.0, 191.5, 238.4"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("45.1, 45.1, 45.1, 71.3, 121.0", \ + "62.4, 62.4, 62.4, 90.0, 141.6", \ + "91.8, 91.8, 91.8, 120.8, 175.4", \ + "146.9, 146.9, 146.9, 177.2, 234.9", \ + "255.0, 255.0, 255.0, 286.1, 346.6"); + } + rise_transition (inslew_load_5x5__24) { + values ("79.6, 79.6, 79.6, 124.2, 214.6", \ + "127.0, 127.0, 127.0, 171.4, 260.4", \ + "214.5, 214.5, 214.5, 258.9, 347.4", \ + "384.9, 384.9, 384.9, 429.7, 518.4", \ + "723.3, 723.3, 723.3, 768.2, 857.8"); + } + cell_fall (inslew_load_5x5__24) { + values ("14.4, 14.4, 14.4, 28.6, 52.3", \ + "8.7, 8.7, 8.7, 25.9, 54.1", \ + "-6.0, -6.0, -6.0, 14.5, 48.7", \ + "-38.4, -38.4, -38.4, -14.8, 25.9", \ + "-105.3, -105.3, -105.3, -79.5, -32.7"); + } + fall_transition (inslew_load_5x5__24) { + values ("25.1, 25.1, 25.1, 39.4, 66.8", \ + "36.1, 36.1, 36.1, 51.4, 79.7", \ + "56.9, 56.9, 56.9, 73.2, 103.4", \ + "97.1, 97.1, 97.1, 114.5, 147.0", \ + "176.8, 176.8, 176.8, 194.9, 229.7"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("98.1, 98.1, 98.1, 135.1, 208.8", \ + "120.1, 120.1, 120.1, 157.6, 231.7", \ + "156.9, 156.9, 156.9, 195.2, 270.0", \ + "227.4, 227.4, 227.4, 265.9, 342.6", \ + "366.4, 366.4, 366.4, 405.4, 482.6"); + } + rise_transition (inslew_load_5x5__24) { + values ("176.2, 176.2, 176.2, 242.9, 377.2", \ + "238.3, 238.3, 238.3, 304.4, 437.9", \ + "350.2, 350.2, 350.2, 415.6, 547.5", \ + "569.1, 569.1, 569.1, 633.7, 763.8", \ + "1005.3, 1005.3, 1005.3, 1069.3, 1197.8"); + } + cell_fall (inslew_load_5x5__24) { + values ("27.9, 27.9, 27.9, 42.4, 69.4", \ + "24.0, 24.0, 24.0, 40.6, 70.4", \ + "11.7, 11.7, 11.7, 31.1, 65.7", \ + "-18.2, -18.2, -18.2, 4.3, 44.8", \ + "-82.6, -82.6, -82.6, -57.3, -10.8"); + } + fall_transition (inslew_load_5x5__24) { + values ("45.6, 45.6, 45.6, 65.1, 104.0", \ + "57.4, 57.4, 57.4, 77.2, 115.9", \ + "79.7, 79.7, 79.7, 100.1, 139.7", \ + "122.6, 122.6, 122.6, 143.9, 185.0", \ + "207.2, 207.2, 207.2, 229.1, 272.0"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("98.1, 98.1, 98.1, 135.1, 208.8", \ + "120.1, 120.1, 120.1, 157.6, 231.7", \ + "156.9, 156.9, 156.9, 195.2, 270.0", \ + "227.4, 227.4, 227.4, 265.9, 342.6", \ + "366.4, 366.4, 366.4, 405.4, 482.6"); + } + rise_transition (inslew_load_5x5__24) { + values ("176.2, 176.2, 176.2, 242.9, 377.2", \ + "238.3, 238.3, 238.3, 304.4, 437.9", \ + "350.2, 350.2, 350.2, 415.6, 547.5", \ + "569.1, 569.1, 569.1, 633.7, 763.8", \ + "1005.3, 1005.3, 1005.3, 1069.3, 1197.8"); + } + cell_fall (inslew_load_5x5__24) { + values ("27.9, 27.9, 27.9, 42.4, 69.4", \ + "24.0, 24.0, 24.0, 40.6, 70.4", \ + "11.7, 11.7, 11.7, 31.1, 65.7", \ + "-18.2, -18.2, -18.2, 4.3, 44.8", \ + "-82.6, -82.6, -82.6, -57.3, -10.8"); + } + fall_transition (inslew_load_5x5__24) { + values ("45.6, 45.6, 45.6, 65.1, 104.0", \ + "57.4, 57.4, 57.4, 77.2, 115.9", \ + "79.7, 79.7, 79.7, 100.1, 139.7", \ + "122.6, 122.6, 122.6, 143.9, 185.0", \ + "207.2, 207.2, 207.2, 229.1, 272.0"); + } + } + internal_power (energy_pos_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__24) { + values ("271.3, 271.3, 271.3, 327.6, 440.4", \ + "312.4, 312.4, 312.4, 368.8, 481.5", \ + "392.8, 392.8, 392.8, 449.2, 561.9", \ + "552.2, 552.2, 552.2, 608.6, 721.3", \ + "870.0, 870.0, 870.0, 926.3, 1039.1"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("268.1, 268.1, 268.1, 324.5, 437.2", \ + "329.8, 329.8, 329.8, 386.1, 498.9", \ + "451.3, 451.3, 451.3, 507.6, 620.4", \ + "693.2, 693.2, 693.2, 749.6, 862.3", \ + "1176.4, 1176.4, 1176.4, 1232.7, 1345.5"); + } + } + internal_power (energy_pos_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__24) { + values ("163.5, 163.5, 163.5, 219.9, 332.6", \ + "197.5, 197.5, 197.5, 253.9, 366.6", \ + "264.6, 264.6, 264.6, 321.0, 433.7", \ + "398.0, 398.0, 398.0, 454.3, 567.1", \ + "664.0, 664.0, 664.0, 720.3, 833.1"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("174.2, 174.2, 174.2, 230.5, 343.3", \ + "222.7, 222.7, 222.7, 279.0, 391.8", \ + "319.0, 319.0, 319.0, 375.3, 488.1", \ + "511.1, 511.1, 511.1, 567.5, 680.2", \ + "895.1, 895.1, 895.1, 951.5, 1064.3"); + } + } + internal_power (energy_neg_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__24) { + values ("221.9, 221.9, 221.9, 278.3, 391.0", \ + "279.6, 279.6, 279.6, 336.0, 448.7", \ + "395.1, 395.1, 395.1, 451.4, 564.2", \ + "626.0, 626.0, 626.0, 682.3, 795.1", \ + "1087.7, 1087.7, 1087.7, 1144.1, 1256.8"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("162.0, 162.0, 162.0, 218.4, 331.1", \ + "193.7, 193.7, 193.7, 250.1, 362.8", \ + "257.2, 257.2, 257.2, 313.6, 426.3", \ + "384.1, 384.1, 384.1, 440.5, 553.2", \ + "637.9, 637.9, 637.9, 694.3, 807.0"); + } + } + internal_power (energy_neg_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__24) { + values ("92.9, 92.9, 92.9, 149.3, 262.0", \ + "126.3, 126.3, 126.3, 182.6, 295.4", \ + "193.0, 193.0, 193.0, 249.4, 362.1", \ + "326.5, 326.5, 326.5, 382.8, 495.6", \ + "593.4, 593.4, 593.4, 649.8, 762.5"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("65.8, 65.8, 65.8, 122.2, 234.9", \ + "78.4, 78.4, 78.4, 134.8, 247.5", \ + "103.7, 103.7, 103.7, 160.0, 272.8", \ + "154.1, 154.1, 154.1, 210.5, 323.2", \ + "255.0, 255.0, 255.0, 311.4, 424.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__24) { + values ("102.2, 102.2, 102.2, 158.6, 271.3", \ + "144.9, 144.9, 144.9, 201.3, 314.0", \ + "230.2, 230.2, 230.2, 286.6, 399.3", \ + "400.9, 400.9, 400.9, 457.3, 570.0", \ + "742.3, 742.3, 742.3, 798.7, 911.4"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("71.2, 71.2, 71.2, 127.5, 240.3", \ + "89.1, 89.1, 89.1, 145.5, 258.2", \ + "125.0, 125.0, 125.0, 181.4, 294.1", \ + "196.9, 196.9, 196.9, 253.2, 366.0", \ + "340.6, 340.6, 340.6, 396.9, 509.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__24) { + values ("158.0, 158.0, 158.0, 214.4, 327.1", \ + "200.7, 200.7, 200.7, 257.1, 369.8", \ + "286.1, 286.1, 286.1, 342.4, 455.2", \ + "456.8, 456.8, 456.8, 513.1, 625.9", \ + "798.2, 798.2, 798.2, 854.5, 967.3"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("112.3, 112.3, 112.3, 168.6, 281.4", \ + "130.2, 130.2, 130.2, 186.6, 299.3", \ + "166.2, 166.2, 166.2, 222.5, 335.3", \ + "238.0, 238.0, 238.0, 294.4, 407.1", \ + "381.7, 381.7, 381.7, 438.0, 550.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__24) { + values ("158.0, 158.0, 158.0, 214.4, 327.1", \ + "200.7, 200.7, 200.7, 257.1, 369.8", \ + "286.1, 286.1, 286.1, 342.4, 455.2", \ + "456.8, 456.8, 456.8, 513.1, 625.9", \ + "798.2, 798.2, 798.2, 854.5, 967.3"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("112.3, 112.3, 112.3, 168.6, 281.4", \ + "130.2, 130.2, 130.2, 186.6, 299.3", \ + "166.2, 166.2, 166.2, 222.5, 335.3", \ + "238.0, 238.0, 238.0, 294.4, 407.1", \ + "381.7, 381.7, 381.7, 438.0, 550.8"); + } + } + } + } + + cell (no2_x1) { + area : 0.0 ; + cell_leakage_power : 2 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 1.5 ; + } + leakage_power () { + when : "i1" ; + value : 4.4 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.0002 ; + } + pin (i1) { + direction : input ; + capacitance : 6.38 ; + } + pin (i0) { + direction : input ; + capacitance : 6.42 ; + } + pin (nq) { + function : "(!(i1) & !(i0))" ; + direction : output ; + capacitance : 3.08 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("32.5, 32.5, 32.5, 41.0, 57.5", \ + "33.5, 33.5, 33.5, 42.2, 59.1", \ + "34.5, 34.5, 34.5, 43.5, 61.0", \ + "35.6, 35.6, 35.6, 44.9, 63.1", \ + "37.3, 37.3, 37.3, 46.7, 65.4"); + } + rise_transition (inslew_load_5x5__25) { + values ("76.9, 76.9, 76.9, 91.2, 119.8", \ + "109.4, 109.4, 109.4, 123.4, 151.6", \ + "172.1, 172.1, 172.1, 186.2, 215.1", \ + "297.8, 297.8, 297.8, 311.8, 339.9", \ + "548.8, 548.8, 548.8, 562.8, 591.0"); + } + cell_fall (inslew_load_5x5__25) { + values ("18.0, 18.0, 18.0, 23.9, 34.5", \ + "22.8, 22.8, 22.8, 29.4, 41.5", \ + "30.7, 30.7, 30.7, 37.8, 51.2", \ + "45.4, 45.4, 45.4, 52.9, 67.3", \ + "74.3, 74.3, 74.3, 82.0, 96.9"); + } + fall_transition (inslew_load_5x5__25) { + values ("24.6, 24.6, 24.6, 29.5, 38.9", \ + "43.8, 43.8, 43.8, 48.9, 58.7", \ + "81.0, 81.0, 81.0, 86.2, 96.4", \ + "154.5, 154.5, 154.5, 159.9, 170.4", \ + "301.1, 301.1, 301.1, 306.6, 317.3"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("22.2, 22.2, 22.2, 32.0, 50.1", \ + "31.5, 31.5, 31.5, 41.8, 61.0", \ + "47.4, 47.4, 47.4, 58.1, 78.5", \ + "77.6, 77.6, 77.6, 88.6, 110.0", \ + "137.4, 137.4, 137.4, 148.5, 170.5"); + } + rise_transition (inslew_load_5x5__25) { + values ("49.0, 49.0, 49.0, 63.7, 93.3", \ + "87.2, 87.2, 87.2, 102.1, 131.3", \ + "159.7, 159.7, 159.7, 174.6, 204.3", \ + "302.4, 302.4, 302.4, 317.5, 347.4", \ + "586.8, 586.8, 586.8, 601.9, 632.0"); + } + cell_fall (inslew_load_5x5__25) { + values ("7.2, 7.2, 7.2, 14.5, 26.6", \ + "3.7, 3.7, 3.7, 12.1, 26.3", \ + "-4.4, -4.4, -4.4, 4.7, 21.1", \ + "-21.4, -21.4, -21.4, -11.8, 6.2", \ + "-55.8, -55.8, -55.8, -45.8, -26.7"); + } + fall_transition (inslew_load_5x5__25) { + values ("16.5, 16.5, 16.5, 22.0, 31.9", \ + "30.1, 30.1, 30.1, 35.9, 46.5", \ + "56.2, 56.2, 56.2, 62.4, 73.8", \ + "108.0, 108.0, 108.0, 114.3, 126.5", \ + "211.2, 211.2, 211.2, 217.6, 230.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__25) { + values ("188.6, 188.6, 188.6, 227.2, 304.3", \ + "260.0, 260.0, 260.0, 298.6, 375.7", \ + "402.8, 402.8, 402.8, 441.4, 518.5", \ + "688.5, 688.5, 688.5, 727.0, 804.1", \ + "1259.7, 1259.7, 1259.7, 1298.3, 1375.4"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("147.0, 147.0, 147.0, 185.5, 262.7", \ + "224.3, 224.3, 224.3, 262.8, 340.0", \ + "378.9, 378.9, 378.9, 417.4, 494.6", \ + "688.1, 688.1, 688.1, 726.6, 803.7", \ + "1306.4, 1306.4, 1306.4, 1345.0, 1422.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__25) { + values ("112.9, 112.9, 112.9, 151.4, 228.6", \ + "184.8, 184.8, 184.8, 223.4, 300.5", \ + "328.6, 328.6, 328.6, 367.2, 444.3", \ + "616.3, 616.3, 616.3, 654.9, 732.0", \ + "1191.7, 1191.7, 1191.7, 1230.2, 1307.3"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("78.7, 78.7, 78.7, 117.2, 194.4", \ + "121.2, 121.2, 121.2, 159.8, 236.9", \ + "206.2, 206.2, 206.2, 244.8, 321.9", \ + "376.3, 376.3, 376.3, 414.8, 492.0", \ + "716.4, 716.4, 716.4, 755.0, 832.1"); + } + } + } + } + + cell (no2_x4) { + area : 0.0 ; + cell_leakage_power : 6.9 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 9.8 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 6.9 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 9.9 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 1 ; + } + pin (i1) { + direction : input ; + capacitance : 5.74 ; + } + pin (i0) { + direction : input ; + capacitance : 5.74 ; + } + pin (nq) { + function : "(!(i0) & !(i1))" ; + direction : output ; + capacitance : 3.95 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__26) { + values ("92.2, 92.2, 92.2, 96.4, 103.9", \ + "89.6, 89.6, 89.6, 93.6, 101.3", \ + "81.5, 81.5, 81.5, 85.7, 93.4", \ + "60.9, 60.9, 60.9, 65.1, 73.1", \ + "14.0, 14.0, 14.0, 18.4, 26.7"); + } + rise_transition (inslew_load_5x5__26) { + values ("40.5, 40.5, 40.5, 45.6, 55.8", \ + "45.5, 45.5, 45.5, 50.7, 60.8", \ + "54.8, 54.8, 54.8, 60.1, 70.3", \ + "73.0, 73.0, 73.0, 78.2, 88.5", \ + "108.2, 108.2, 108.2, 113.4, 123.6"); + } + cell_fall (inslew_load_5x5__26) { + values ("91.6, 91.6, 91.6, 95.7, 103.2", \ + "112.4, 112.4, 112.4, 116.3, 123.9", \ + "145.3, 145.3, 145.3, 149.4, 156.8", \ + "203.3, 203.3, 203.3, 207.6, 215.3", \ + "313.0, 313.0, 313.0, 317.3, 325.6"); + } + fall_transition (inslew_load_5x5__26) { + values ("32.9, 32.9, 32.9, 35.5, 40.4", \ + "38.9, 38.9, 38.9, 41.5, 46.5", \ + "49.5, 49.5, 49.5, 52.0, 57.2", \ + "69.4, 69.4, 69.4, 72.0, 77.1", \ + "108.3, 108.3, 108.3, 110.9, 116.0"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__26) { + values ("80.8, 80.8, 80.8, 84.8, 92.2", \ + "87.7, 87.7, 87.7, 91.8, 99.4", \ + "95.6, 95.6, 95.6, 99.8, 107.5", \ + "105.1, 105.1, 105.1, 109.3, 117.4", \ + "118.0, 118.0, 118.0, 122.4, 130.7"); + } + rise_transition (inslew_load_5x5__26) { + values ("34.7, 34.7, 34.7, 39.8, 50.0", \ + "41.4, 41.4, 41.4, 46.5, 56.7", \ + "53.3, 53.3, 53.3, 58.6, 68.8", \ + "75.8, 75.8, 75.8, 80.9, 91.3", \ + "118.9, 118.9, 118.9, 124.1, 134.3"); + } + cell_fall (inslew_load_5x5__26) { + values ("76.4, 76.4, 76.4, 80.6, 88.0", \ + "86.4, 86.4, 86.4, 90.3, 97.9", \ + "99.2, 99.2, 99.2, 103.2, 110.7", \ + "117.8, 117.8, 117.8, 121.9, 129.4", \ + "148.0, 148.0, 148.0, 152.4, 160.3"); + } + fall_transition (inslew_load_5x5__26) { + values ("30.5, 30.5, 30.5, 33.1, 38.0", \ + "34.9, 34.9, 34.9, 37.5, 42.4", \ + "42.7, 42.7, 42.7, 45.3, 50.4", \ + "57.2, 57.2, 57.2, 59.7, 64.8", \ + "85.1, 85.1, 85.1, 87.7, 92.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__26) { + values ("707.4, 707.4, 707.4, 756.7, 855.4", \ + "800.3, 800.3, 800.3, 849.6, 948.2", \ + "981.7, 981.7, 981.7, 1031.0, 1129.6", \ + "1342.5, 1342.5, 1342.5, 1391.8, 1490.5", \ + "2058.2, 2058.2, 2058.2, 2107.5, 2206.2"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("711.4, 711.4, 711.4, 760.8, 859.4", \ + "866.9, 866.9, 866.9, 916.2, 1014.9", \ + "1163.4, 1163.4, 1163.4, 1212.7, 1311.4", \ + "1745.9, 1745.9, 1745.9, 1795.2, 1893.9", \ + "2902.5, 2902.5, 2902.5, 2951.8, 3050.4"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__26) { + values ("582.3, 582.3, 582.3, 631.6, 730.3", \ + "694.3, 694.3, 694.3, 743.6, 842.3", \ + "909.6, 909.6, 909.6, 958.9, 1057.5", \ + "1331.4, 1331.4, 1331.4, 1380.7, 1479.3", \ + "2166.0, 2166.0, 2166.0, 2215.3, 2314.0"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("610.7, 610.7, 610.7, 660.0, 758.7", \ + "711.6, 711.6, 711.6, 760.9, 859.5", \ + "903.6, 903.6, 903.6, 953.0, 1051.6", \ + "1277.5, 1277.5, 1277.5, 1326.8, 1425.5", \ + "2017.3, 2017.3, 2017.3, 2066.6, 2165.3"); + } + } + } + } + + cell (no3_x1) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 4.4 ; + } + leakage_power () { + when : "((i0 & !(i1)) | (!(i0) & i1 & i2))" ; + value : 1.5 ; + } + leakage_power () { + when : "(i1 & !(i2))" ; + value : 4.5 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 1.3 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.00014 ; + } + pin (i2) { + direction : input ; + capacitance : 6.06 ; + } + pin (i1) { + direction : input ; + capacitance : 5.84 ; + } + pin (i0) { + direction : input ; + capacitance : 5.83 ; + } + pin (nq) { + function : "((!(i1) & !(i0)) & !(i2))" ; + direction : output ; + capacitance : 3.40 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__27) { + values ("49.1, 49.1, 49.1, 62.8, 89.8", \ + "52.7, 52.7, 52.7, 66.9, 94.7", \ + "58.1, 58.1, 58.1, 72.8, 101.4", \ + "67.2, 67.2, 67.2, 82.4, 112.2", \ + "84.2, 84.2, 84.2, 99.8, 130.6"); + } + rise_transition (inslew_load_5x5__27) { + values ("99.9, 99.9, 99.9, 123.7, 171.6", \ + "134.8, 134.8, 134.8, 158.2, 205.5", \ + "201.1, 201.1, 201.1, 225.4, 271.8", \ + "333.1, 333.1, 333.1, 356.4, 403.1", \ + "596.5, 596.5, 596.5, 619.9, 666.4"); + } + cell_fall (inslew_load_5x5__27) { + values ("24.2, 24.2, 24.2, 32.9, 48.5", \ + "28.4, 28.4, 28.4, 38.4, 56.3", \ + "33.2, 33.2, 33.2, 44.4, 64.9", \ + "40.5, 40.5, 40.5, 52.6, 75.4", \ + "53.6, 53.6, 53.6, 66.3, 90.7"); + } + fall_transition (inslew_load_5x5__27) { + values ("28.4, 28.4, 28.4, 36.2, 51.2", \ + "47.1, 47.1, 47.1, 55.3, 70.9", \ + "82.4, 82.4, 82.4, 91.0, 107.4", \ + "151.6, 151.6, 151.6, 160.4, 177.6", \ + "288.9, 288.9, 288.9, 297.9, 315.7"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__27) { + values ("27.0, 27.0, 27.0, 42.3, 70.7", \ + "37.0, 37.0, 37.0, 52.5, 82.3", \ + "52.6, 52.6, 52.6, 69.2, 100.4", \ + "81.5, 81.5, 81.5, 98.7, 131.7", \ + "138.0, 138.0, 138.0, 155.5, 189.8"); + } + rise_transition (inslew_load_5x5__27) { + values ("57.2, 57.2, 57.2, 81.6, 129.8", \ + "97.0, 97.0, 97.0, 120.4, 168.9", \ + "170.4, 170.4, 170.4, 194.5, 242.0", \ + "314.0, 314.0, 314.0, 338.3, 386.5", \ + "599.6, 599.6, 599.6, 624.0, 672.6"); + } + cell_fall (inslew_load_5x5__27) { + values ("12.6, 12.6, 12.6, 23.1, 40.1", \ + "10.5, 10.5, 10.5, 22.6, 42.9", \ + "4.0, 4.0, 4.0, 17.6, 41.3", \ + "-10.3, -10.3, -10.3, 4.2, 30.9", \ + "-40.0, -40.0, -40.0, -24.8, 4.0"); + } + fall_transition (inslew_load_5x5__27) { + values ("19.3, 19.3, 19.3, 27.7, 43.1", \ + "33.9, 33.9, 33.9, 42.9, 59.3", \ + "61.6, 61.6, 61.6, 71.1, 88.7", \ + "115.7, 115.7, 115.7, 125.6, 144.5", \ + "223.4, 223.4, 223.4, 233.6, 253.3"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__27) { + values ("63.3, 63.3, 63.3, 76.7, 103.2", \ + "57.8, 57.8, 57.8, 71.5, 98.4", \ + "47.6, 47.6, 47.6, 61.3, 88.4", \ + "27.2, 27.2, 27.2, 41.1, 69.1", \ + "-13.5, -13.5, -13.5, 0.6, 28.7"); + } + rise_transition (inslew_load_5x5__27) { + values ("135.6, 135.6, 135.6, 159.2, 206.5", \ + "163.6, 163.6, 163.6, 187.3, 234.7", \ + "218.1, 218.1, 218.1, 241.5, 288.4", \ + "328.4, 328.4, 328.4, 351.4, 397.5", \ + "550.9, 550.9, 550.9, 573.5, 619.0"); + } + cell_fall (inslew_load_5x5__27) { + values ("32.5, 32.5, 32.5, 40.5, 55.2", \ + "46.2, 46.2, 46.2, 54.9, 71.2", \ + "69.6, 69.6, 69.6, 79.0, 97.0", \ + "114.0, 114.0, 114.0, 123.9, 143.2", \ + "201.4, 201.4, 201.4, 211.7, 231.8"); + } + fall_transition (inslew_load_5x5__27) { + values ("35.5, 35.5, 35.5, 43.1, 58.1", \ + "61.7, 61.7, 61.7, 69.4, 84.5", \ + "111.1, 111.1, 111.1, 119.0, 134.5", \ + "208.2, 208.2, 208.2, 216.2, 232.0", \ + "401.3, 401.3, 401.3, 409.3, 425.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__27) { + values ("168.1, 168.1, 168.1, 210.6, 295.7", \ + "218.0, 218.0, 218.0, 260.6, 345.7", \ + "317.9, 317.9, 317.9, 360.5, 445.6", \ + "517.7, 517.7, 517.7, 560.3, 645.4", \ + "917.4, 917.4, 917.4, 959.9, 1045.0"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("124.7, 124.7, 124.7, 167.2, 252.3", \ + "171.9, 171.9, 171.9, 214.4, 299.5", \ + "266.4, 266.4, 266.4, 308.9, 394.0", \ + "455.3, 455.3, 455.3, 497.9, 583.0", \ + "833.2, 833.2, 833.2, 875.8, 960.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__27) { + values ("95.4, 95.4, 95.4, 137.9, 223.0", \ + "145.6, 145.6, 145.6, 188.1, 273.2", \ + "246.1, 246.1, 246.1, 288.6, 373.7", \ + "447.1, 447.1, 447.1, 489.6, 574.7", \ + "849.1, 849.1, 849.1, 891.6, 976.7"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("71.4, 71.4, 71.4, 113.9, 199.0", \ + "102.8, 102.8, 102.8, 145.3, 230.4", \ + "165.6, 165.6, 165.6, 208.1, 293.2", \ + "291.2, 291.2, 291.2, 333.7, 418.8", \ + "542.3, 542.3, 542.3, 584.9, 670.0"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__27) { + values ("230.4, 230.4, 230.4, 272.9, 358.0", \ + "275.7, 275.7, 275.7, 318.2, 403.3", \ + "366.2, 366.2, 366.2, 408.7, 493.8", \ + "547.2, 547.2, 547.2, 589.7, 674.8", \ + "909.2, 909.2, 909.2, 951.8, 1036.9"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("178.7, 178.7, 178.7, 221.3, 306.4", \ + "260.0, 260.0, 260.0, 302.6, 387.7", \ + "422.6, 422.6, 422.6, 465.1, 550.2", \ + "747.7, 747.7, 747.7, 790.2, 875.3", \ + "1397.9, 1397.9, 1397.9, 1440.4, 1525.5"); + } + } + } + } + + cell (no3_x4) { + area : 0.0 ; + cell_leakage_power : 6.9 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 9.8 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 6.7 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2)) | (i1 & !(i2)))" ; + value : 6.9 ; + } + leakage_power () { + when : "(!(i0) & i2)" ; + value : 9.9 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 1 ; + } + pin (i2) { + direction : input ; + capacitance : 5.75 ; + } + pin (i1) { + direction : input ; + capacitance : 5.81 ; + } + pin (i0) { + direction : input ; + capacitance : 5.81 ; + } + pin (nq) { + function : "(!(i0) & !(i1) & !(i2))" ; + direction : output ; + capacitance : 3.98 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__28) { + values ("98.8, 98.8, 98.8, 102.9, 110.5", \ + "89.9, 89.9, 89.9, 94.1, 101.8", \ + "72.3, 72.3, 72.3, 76.4, 84.3", \ + "36.0, 36.0, 36.0, 40.2, 48.1", \ + "-39.5, -39.5, -39.5, -35.2, -26.9"); + } + rise_transition (inslew_load_5x5__28) { + values ("39.8, 39.8, 39.8, 45.0, 55.2", \ + "43.9, 43.9, 43.9, 49.1, 59.4", \ + "51.6, 51.6, 51.6, 56.9, 67.2", \ + "66.3, 66.3, 66.3, 71.6, 82.0", \ + "96.1, 96.1, 96.1, 101.2, 111.6"); + } + cell_fall (inslew_load_5x5__28) { + values ("108.3, 108.3, 108.3, 112.3, 120.0", \ + "135.8, 135.8, 135.8, 139.8, 147.3", \ + "180.6, 180.6, 180.6, 184.8, 192.5", \ + "261.9, 261.9, 261.9, 266.3, 274.5", \ + "418.9, 418.9, 418.9, 423.3, 431.9"); + } + fall_transition (inslew_load_5x5__28) { + values ("37.8, 37.8, 37.8, 40.5, 45.5", \ + "47.3, 47.3, 47.3, 49.9, 55.1", \ + "63.8, 63.8, 63.8, 66.3, 71.5", \ + "95.0, 95.0, 95.0, 97.6, 102.7", \ + "156.1, 156.1, 156.1, 158.6, 163.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__28) { + values ("89.4, 89.4, 89.4, 93.5, 100.9", \ + "89.4, 89.4, 89.4, 93.5, 101.1", \ + "86.3, 86.3, 86.3, 90.4, 98.3", \ + "76.9, 76.9, 76.9, 81.1, 89.1", \ + "52.5, 52.5, 52.5, 56.8, 65.1"); + } + rise_transition (inslew_load_5x5__28) { + values ("34.5, 34.5, 34.5, 39.7, 49.9", \ + "39.7, 39.7, 39.7, 44.8, 55.1", \ + "49.3, 49.3, 49.3, 54.6, 64.8", \ + "67.0, 67.0, 67.0, 72.2, 82.7", \ + "102.3, 102.3, 102.3, 107.5, 117.9"); + } + cell_fall (inslew_load_5x5__28) { + values ("97.4, 97.4, 97.4, 101.3, 109.0", \ + "113.1, 113.1, 113.1, 117.1, 124.7", \ + "135.2, 135.2, 135.2, 139.3, 146.8", \ + "170.6, 170.6, 170.6, 175.0, 182.9", \ + "234.7, 234.7, 234.7, 239.1, 247.6"); + } + fall_transition (inslew_load_5x5__28) { + values ("35.1, 35.1, 35.1, 37.8, 42.8", \ + "42.4, 42.4, 42.4, 45.0, 50.1", \ + "54.6, 54.6, 54.6, 57.2, 62.4", \ + "77.3, 77.3, 77.3, 79.9, 85.0", \ + "121.0, 121.0, 121.0, 123.6, 128.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__28) { + values ("73.1, 73.1, 73.1, 77.2, 84.4", \ + "79.8, 79.8, 79.8, 83.9, 91.3", \ + "87.4, 87.4, 87.4, 91.5, 99.2", \ + "96.5, 96.5, 96.5, 100.7, 108.6", \ + "108.0, 108.0, 108.0, 112.4, 120.7"); + } + rise_transition (inslew_load_5x5__28) { + values ("27.8, 27.8, 27.8, 33.1, 43.3", \ + "34.0, 34.0, 34.0, 39.2, 49.4", \ + "45.0, 45.0, 45.0, 50.2, 60.5", \ + "64.6, 64.6, 64.6, 69.8, 80.3", \ + "102.8, 102.8, 102.8, 108.0, 118.4"); + } + cell_fall (inslew_load_5x5__28) { + values ("82.8, 82.8, 82.8, 87.0, 94.5", \ + "91.7, 91.7, 91.7, 95.6, 103.3", \ + "100.7, 100.7, 100.7, 104.8, 112.2", \ + "109.9, 109.9, 109.9, 114.2, 122.0", \ + "121.4, 121.4, 121.4, 125.8, 134.0"); + } + fall_transition (inslew_load_5x5__28) { + values ("31.8, 31.8, 31.8, 34.5, 39.5", \ + "37.9, 37.9, 37.9, 40.6, 45.6", \ + "48.0, 48.0, 48.0, 50.6, 55.9", \ + "66.1, 66.1, 66.1, 68.7, 73.9", \ + "100.7, 100.7, 100.7, 103.3, 108.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__28) { + values ("825.0, 825.0, 825.0, 874.8, 974.4", \ + "912.2, 912.2, 912.2, 962.0, 1061.6", \ + "1082.4, 1082.4, 1082.4, 1132.2, 1231.8", \ + "1420.5, 1420.5, 1420.5, 1470.3, 1569.9", \ + "2101.5, 2101.5, 2101.5, 2151.3, 2250.9"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("840.5, 840.5, 840.5, 890.3, 989.9", \ + "1045.2, 1045.2, 1045.2, 1095.0, 1194.6", \ + "1430.3, 1430.3, 1430.3, 1480.1, 1579.7", \ + "2182.8, 2182.8, 2182.8, 2232.6, 2332.2", \ + "3675.1, 3675.1, 3675.1, 3724.9, 3824.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__28) { + values ("710.0, 710.0, 710.0, 759.8, 859.4", \ + "811.4, 811.4, 811.4, 861.2, 960.8", \ + "1010.2, 1010.2, 1010.2, 1060.0, 1159.6", \ + "1398.4, 1398.4, 1398.4, 1448.2, 1547.8", \ + "2176.7, 2176.7, 2176.7, 2226.5, 2326.1"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("752.6, 752.6, 752.6, 802.4, 902.0", \ + "892.2, 892.2, 892.2, 942.0, 1041.6", \ + "1149.8, 1149.8, 1149.8, 1199.6, 1299.2", \ + "1647.0, 1647.0, 1647.0, 1696.8, 1796.4", \ + "2626.7, 2626.7, 2626.7, 2676.5, 2776.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__28) { + values ("574.0, 574.0, 574.0, 623.8, 723.4", \ + "682.9, 682.9, 682.9, 732.7, 832.3", \ + "893.5, 893.5, 893.5, 943.3, 1042.9", \ + "1302.0, 1302.0, 1302.0, 1351.8, 1451.4", \ + "2114.4, 2114.4, 2114.4, 2164.2, 2263.8"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("657.8, 657.8, 657.8, 707.6, 807.2", \ + "765.3, 765.3, 765.3, 815.1, 914.7", \ + "960.3, 960.3, 960.3, 1010.1, 1109.7", \ + "1330.9, 1330.9, 1330.9, 1380.7, 1480.3", \ + "2055.9, 2055.9, 2055.9, 2105.7, 2205.3"); + } + } + } + } + + cell (no4_x1) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 4.4 ; + } + leakage_power () { + when : "((i0 & (i1 ^ (i2 | !(i3)))) | (!(i0) & i1 & i2))" ; + value : 1.5 ; + } + leakage_power () { + when : "((i0 & i1 & !(i3)) | (i1 & !(i2) & !(i3)))" ; + value : 4.5 ; + } + leakage_power () { + when : "((!(i0) & ((!(i1) & (i2 | i3)) | (!(i2) & i3))) | (!(i1) & !(i2) & i3))" ; + value : 1.3 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.0002 ; + } + pin (i3) { + direction : input ; + capacitance : 6.04 ; + } + pin (i2) { + direction : input ; + capacitance : 5.93 ; + } + pin (i1) { + direction : input ; + capacitance : 5.93 ; + } + pin (i0) { + direction : input ; + capacitance : 5.95 ; + } + pin (nq) { + function : "(((!(i1) & !(i0)) & !(i2)) & !(i3))" ; + direction : output ; + capacitance : 4.02 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__29) { + values ("71.1, 71.1, 71.1, 92.5, 134.6", \ + "85.6, 85.6, 85.6, 107.4, 150.1", \ + "109.8, 109.8, 109.8, 132.0, 175.9", \ + "155.8, 155.8, 155.8, 178.4, 222.9", \ + "246.0, 246.0, 246.0, 269.0, 314.5"); + } + rise_transition (inslew_load_5x5__29) { + values ("133.8, 133.8, 133.8, 171.6, 247.7", \ + "185.2, 185.2, 185.2, 222.6, 298.1", \ + "280.0, 280.0, 280.0, 317.0, 391.4", \ + "466.4, 466.4, 466.4, 502.9, 576.3", \ + "833.3, 833.3, 833.3, 870.0, 946.9"); + } + cell_fall (inslew_load_5x5__29) { + values ("21.3, 21.3, 21.3, 31.0, 48.0", \ + "19.3, 19.3, 19.3, 31.0, 51.3", \ + "11.2, 11.2, 11.2, 25.0, 49.3", \ + "-8.2, -8.2, -8.2, 7.2, 35.6", \ + "-49.5, -49.5, -49.5, -32.7, -1.0"); + } + fall_transition (inslew_load_5x5__29) { + values ("26.4, 26.4, 26.4, 35.0, 51.3", \ + "40.3, 40.3, 40.3, 49.6, 66.8", \ + "66.3, 66.3, 66.3, 76.3, 95.0", \ + "116.5, 116.5, 116.5, 127.3, 147.6", \ + "216.0, 216.0, 216.0, 227.2, 248.9"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__29) { + values ("39.8, 39.8, 39.8, 62.6, 105.6", \ + "55.7, 55.7, 55.7, 79.2, 124.0", \ + "87.1, 87.1, 87.1, 110.9, 157.1", \ + "146.7, 146.7, 146.7, 170.7, 218.3", \ + "261.0, 261.0, 261.0, 285.8, 334.1"); + } + rise_transition (inslew_load_5x5__29) { + values ("77.4, 77.4, 77.4, 115.4, 192.1", \ + "126.6, 126.6, 126.6, 164.9, 240.9", \ + "223.8, 223.8, 223.8, 261.2, 337.4", \ + "413.7, 413.7, 413.7, 450.5, 525.4", \ + "786.2, 786.2, 786.2, 823.6, 897.7"); + } + cell_fall (inslew_load_5x5__29) { + values ("11.4, 11.4, 11.4, 22.8, 41.1", \ + "5.0, 5.0, 5.0, 18.9, 41.3", \ + "-10.3, -10.3, -10.3, 6.0, 33.3", \ + "-43.1, -43.1, -43.1, -24.8, 7.3", \ + "-110.1, -110.1, -110.1, -90.4, -54.2"); + } + fall_transition (inslew_load_5x5__29) { + values ("18.7, 18.7, 18.7, 28.0, 44.6", \ + "30.2, 30.2, 30.2, 40.3, 58.3", \ + "51.7, 51.7, 51.7, 62.8, 82.7", \ + "93.5, 93.5, 93.5, 105.4, 127.4", \ + "176.4, 176.4, 176.4, 188.9, 212.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__29) { + values ("98.6, 98.6, 98.6, 119.6, 161.2", \ + "106.7, 106.7, 106.7, 128.0, 170.1", \ + "119.8, 119.8, 119.8, 141.2, 183.8", \ + "145.3, 145.3, 145.3, 167.3, 210.1", \ + "196.3, 196.3, 196.3, 218.1, 261.4"); + } + rise_transition (inslew_load_5x5__29) { + values ("187.9, 187.9, 187.9, 225.4, 300.9", \ + "235.5, 235.5, 235.5, 273.0, 348.0", \ + "323.4, 323.4, 323.4, 360.5, 435.3", \ + "497.1, 497.1, 497.1, 533.9, 607.8", \ + "845.2, 845.2, 845.2, 881.6, 954.6"); + } + cell_fall (inslew_load_5x5__29) { + values ("27.3, 27.3, 27.3, 36.3, 52.6", \ + "30.5, 30.5, 30.5, 41.0, 60.0", \ + "33.0, 33.0, 33.0, 45.0, 67.0", \ + "34.7, 34.7, 34.7, 48.0, 72.9", \ + "36.2, 36.2, 36.2, 50.3, 77.4"); + } + fall_transition (inslew_load_5x5__29) { + values ("31.3, 31.3, 31.3, 39.7, 56.0", \ + "49.0, 49.0, 49.0, 57.8, 74.6", \ + "82.2, 82.2, 82.2, 91.5, 109.3", \ + "147.0, 147.0, 147.0, 156.7, 175.6", \ + "275.5, 275.5, 275.5, 285.6, 305.2"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__29) { + values ("119.2, 119.2, 119.2, 139.9, 181.3", \ + "118.7, 118.7, 118.7, 139.7, 181.5", \ + "116.4, 116.4, 116.4, 137.6, 179.8", \ + "113.5, 113.5, 113.5, 134.6, 176.7", \ + "109.8, 109.8, 109.8, 130.8, 172.9"); + } + rise_transition (inslew_load_5x5__29) { + values ("233.0, 233.0, 233.0, 270.2, 344.9", \ + "274.9, 274.9, 274.9, 312.0, 386.2", \ + "353.2, 353.2, 353.2, 390.5, 465.1", \ + "506.7, 506.7, 506.7, 544.0, 618.6", \ + "814.7, 814.7, 814.7, 851.6, 925.7"); + } + cell_fall (inslew_load_5x5__29) { + values ("33.6, 33.6, 33.6, 42.1, 57.8", \ + "45.4, 45.4, 45.4, 54.9, 72.5", \ + "65.3, 65.3, 65.3, 75.6, 95.2", \ + "102.4, 102.4, 102.4, 113.4, 134.6", \ + "175.1, 175.1, 175.1, 186.5, 208.9"); + } + fall_transition (inslew_load_5x5__29) { + values ("37.0, 37.0, 37.0, 45.2, 61.4", \ + "61.4, 61.4, 61.4, 69.8, 86.2", \ + "107.7, 107.7, 107.7, 116.4, 133.3", \ + "198.7, 198.7, 198.7, 207.6, 225.0", \ + "379.8, 379.8, 379.8, 388.8, 406.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__29) { + values ("179.4, 179.4, 179.4, 229.7, 330.3", \ + "234.6, 234.6, 234.6, 284.9, 385.5", \ + "345.0, 345.0, 345.0, 395.3, 495.9", \ + "565.8, 565.8, 565.8, 616.1, 716.7", \ + "1007.4, 1007.4, 1007.4, 1057.7, 1158.3"); + } + fall_power (energy_inslew_load_5x5__29) { + values ("113.4, 113.4, 113.4, 163.7, 264.3", \ + "143.3, 143.3, 143.3, 193.6, 294.1", \ + "203.0, 203.0, 203.0, 253.2, 353.8", \ + "322.3, 322.3, 322.3, 372.6, 473.2", \ + "561.1, 561.1, 561.1, 611.4, 712.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__29) { + values ("106.4, 106.4, 106.4, 156.7, 257.3", \ + "159.1, 159.1, 159.1, 209.4, 310.0", \ + "264.4, 264.4, 264.4, 314.7, 415.3", \ + "475.1, 475.1, 475.1, 525.4, 626.0", \ + "896.5, 896.5, 896.5, 946.8, 1047.4"); + } + fall_power (energy_inslew_load_5x5__29) { + values ("68.5, 68.5, 68.5, 118.8, 219.4", \ + "90.3, 90.3, 90.3, 140.5, 241.1", \ + "133.7, 133.7, 133.7, 184.0, 284.5", \ + "220.5, 220.5, 220.5, 270.8, 371.4", \ + "394.2, 394.2, 394.2, 444.4, 545.0"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__29) { + values ("247.7, 247.7, 247.7, 298.0, 398.6", \ + "302.4, 302.4, 302.4, 352.7, 453.3", \ + "411.9, 411.9, 411.9, 462.2, 562.8", \ + "630.9, 630.9, 630.9, 681.2, 781.8", \ + "1068.8, 1068.8, 1068.8, 1119.1, 1219.7"); + } + fall_power (energy_inslew_load_5x5__29) { + values ("149.0, 149.0, 149.0, 199.3, 299.9", \ + "195.3, 195.3, 195.3, 245.6, 346.2", \ + "287.9, 287.9, 287.9, 338.2, 438.8", \ + "473.2, 473.2, 473.2, 523.5, 624.1", \ + "843.7, 843.7, 843.7, 894.0, 994.6"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__29) { + values ("305.0, 305.0, 305.0, 355.3, 455.8", \ + "355.8, 355.8, 355.8, 406.1, 506.7", \ + "457.5, 457.5, 457.5, 507.8, 608.3", \ + "660.8, 660.8, 660.8, 711.1, 811.7", \ + "1067.4, 1067.4, 1067.4, 1117.7, 1218.3"); + } + fall_power (energy_inslew_load_5x5__29) { + values ("196.3, 196.3, 196.3, 246.6, 347.2", \ + "276.8, 276.8, 276.8, 327.1, 427.7", \ + "437.7, 437.7, 437.7, 488.0, 588.6", \ + "759.6, 759.6, 759.6, 809.9, 910.4", \ + "1403.3, 1403.3, 1403.3, 1453.6, 1554.1"); + } + } + } + } + + cell (no4_x4) { + area : 0.0 ; + cell_leakage_power : 6.9 ; + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & i0)" ; + value : 7.6 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & i3) | (!(i1) & i2))) | (!(i0) & i1 & i2))" ; + value : 7.5 ; + } + leakage_power () { + when : "((i0 & i1 & (i2 | !(i3))) | (i1 & !(i2) & !(i3)))" ; + value : 11 ; + } + leakage_power () { + when : "((!(i0) & ((!(i1) & (i2 | i3)) | (!(i2) & i3))) | (!(i1) & !(i2) & i3))" ; + value : 7.3 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 1.4 ; + } + pin (i3) { + direction : input ; + capacitance : 5.97 ; + } + pin (i2) { + direction : input ; + capacitance : 5.99 ; + } + pin (i1) { + direction : input ; + capacitance : 6.00 ; + } + pin (i0) { + direction : input ; + capacitance : 6.03 ; + } + pin (nq) { + function : "(!(i3) & !(i2) & !(i0) & !(i1))" ; + direction : output ; + capacitance : 4.12 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__30) { + values ("149.6, 149.6, 149.6, 153.8, 161.6", \ + "163.7, 163.7, 163.7, 167.9, 175.9", \ + "186.0, 186.0, 186.0, 190.4, 198.6", \ + "226.2, 226.2, 226.2, 230.5, 238.9", \ + "301.8, 301.8, 301.8, 306.1, 314.6"); + } + rise_transition (inslew_load_5x5__30) { + values ("57.3, 57.3, 57.3, 62.5, 73.0", \ + "66.7, 66.7, 66.7, 71.9, 82.3", \ + "83.9, 83.9, 83.9, 89.1, 99.5", \ + "117.1, 117.1, 117.1, 122.5, 132.9", \ + "181.6, 181.6, 181.6, 187.0, 197.8"); + } + cell_fall (inslew_load_5x5__30) { + values ("88.6, 88.6, 88.6, 92.9, 100.4", \ + "94.8, 94.8, 94.8, 99.0, 106.7", \ + "98.8, 98.8, 98.8, 102.8, 110.7", \ + "98.4, 98.4, 98.4, 102.5, 110.1", \ + "88.7, 88.7, 88.7, 92.9, 100.7"); + } + fall_transition (inslew_load_5x5__30) { + values ("32.6, 32.6, 32.6, 35.2, 40.4", \ + "36.3, 36.3, 36.3, 39.0, 44.0", \ + "42.7, 42.7, 42.7, 45.5, 50.6", \ + "54.6, 54.6, 54.6, 57.3, 62.7", \ + "77.3, 77.3, 77.3, 79.8, 85.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__30) { + values ("116.5, 116.5, 116.5, 120.6, 128.3", \ + "133.9, 133.9, 133.9, 138.1, 145.8", \ + "166.0, 166.0, 166.0, 170.2, 178.4", \ + "223.7, 223.7, 223.7, 228.0, 236.4", \ + "330.2, 330.2, 330.2, 334.5, 343.0"); + } + rise_transition (inslew_load_5x5__30) { + values ("45.8, 45.8, 45.8, 51.1, 61.3", \ + "55.4, 55.4, 55.4, 60.7, 71.1", \ + "73.9, 73.9, 73.9, 79.0, 89.5", \ + "109.1, 109.1, 109.1, 114.5, 124.8", \ + "176.8, 176.8, 176.8, 182.2, 193.0"); + } + cell_fall (inslew_load_5x5__30) { + values ("76.8, 76.8, 76.8, 81.1, 88.5", \ + "78.0, 78.0, 78.0, 82.3, 89.9", \ + "73.7, 73.7, 73.7, 77.8, 85.6", \ + "57.1, 57.1, 57.1, 61.1, 68.9", \ + "15.6, 15.6, 15.6, 19.8, 27.5"); + } + fall_transition (inslew_load_5x5__30) { + values ("30.7, 30.7, 30.7, 33.3, 38.5", \ + "33.9, 33.9, 33.9, 36.5, 41.6", \ + "39.3, 39.3, 39.3, 42.0, 47.1", \ + "49.2, 49.2, 49.2, 51.9, 57.2", \ + "68.0, 68.0, 68.0, 70.6, 76.0"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__30) { + values ("179.0, 179.0, 179.0, 183.2, 191.3", \ + "185.9, 185.9, 185.9, 190.2, 198.3", \ + "196.3, 196.3, 196.3, 200.7, 209.0", \ + "215.7, 215.7, 215.7, 220.0, 228.4", \ + "252.2, 252.2, 252.2, 256.5, 265.0"); + } + rise_transition (inslew_load_5x5__30) { + values ("68.2, 68.2, 68.2, 73.4, 83.8", \ + "76.7, 76.7, 76.7, 81.9, 92.3", \ + "92.3, 92.3, 92.3, 97.6, 107.9", \ + "122.8, 122.8, 122.8, 128.2, 138.7", \ + "183.8, 183.8, 183.8, 189.1, 199.9"); + } + cell_fall (inslew_load_5x5__30) { + values ("96.0, 96.0, 96.0, 100.3, 107.9", \ + "107.9, 107.9, 107.9, 112.1, 119.8", \ + "123.3, 123.3, 123.3, 127.3, 135.1", \ + "145.3, 145.3, 145.3, 149.4, 157.1", \ + "181.1, 181.1, 181.1, 185.4, 193.4"); + } + fall_transition (inslew_load_5x5__30) { + values ("33.9, 33.9, 33.9, 36.5, 41.6", \ + "38.3, 38.3, 38.3, 41.0, 46.1", \ + "46.2, 46.2, 46.2, 49.0, 54.2", \ + "61.0, 61.0, 61.0, 63.7, 69.1", \ + "89.6, 89.6, 89.6, 92.2, 97.5"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__30) { + values ("200.1, 200.1, 200.1, 204.4, 212.6", \ + "197.9, 197.9, 197.9, 202.3, 210.5", \ + "191.9, 191.9, 191.9, 196.3, 204.6", \ + "181.1, 181.1, 181.1, 185.4, 193.9", \ + "160.1, 160.1, 160.1, 164.4, 172.9"); + } + rise_transition (inslew_load_5x5__30) { + values ("77.0, 77.0, 77.0, 82.1, 92.6", \ + "84.2, 84.2, 84.2, 89.5, 99.8", \ + "97.8, 97.8, 97.8, 103.1, 113.4", \ + "123.9, 123.9, 123.9, 129.3, 139.7", \ + "176.3, 176.3, 176.3, 181.6, 192.4"); + } + cell_fall (inslew_load_5x5__30) { + values ("103.8, 103.8, 103.8, 108.0, 115.7", \ + "125.6, 125.6, 125.6, 129.6, 137.5", \ + "160.3, 160.3, 160.3, 164.4, 172.1", \ + "221.4, 221.4, 221.4, 225.5, 233.3", \ + "336.3, 336.3, 336.3, 340.7, 348.8"); + } + fall_transition (inslew_load_5x5__30) { + values ("35.2, 35.2, 35.2, 37.9, 43.0", \ + "41.2, 41.2, 41.2, 44.0, 49.0", \ + "51.9, 51.9, 51.9, 54.6, 59.9", \ + "72.3, 72.3, 72.3, 74.9, 80.2", \ + "111.9, 111.9, 111.9, 114.6, 119.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__30) { + values ("911.6, 911.6, 911.6, 963.1, 1066.0", \ + "1059.2, 1059.2, 1059.2, 1110.7, 1213.6", \ + "1341.0, 1341.0, 1341.0, 1392.5, 1495.4", \ + "1898.0, 1898.0, 1898.0, 1949.5, 2052.4", \ + "2995.5, 2995.5, 2995.5, 3046.9, 3149.9"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("690.2, 690.2, 690.2, 741.6, 844.6", \ + "770.0, 770.0, 770.0, 821.5, 924.4", \ + "920.1, 920.1, 920.1, 971.6, 1074.5", \ + "1208.3, 1208.3, 1208.3, 1259.7, 1362.7", \ + "1774.9, 1774.9, 1774.9, 1826.3, 1929.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__30) { + values ("720.8, 720.8, 720.8, 772.3, 875.2", \ + "869.3, 869.3, 869.3, 920.8, 1023.7", \ + "1160.3, 1160.3, 1160.3, 1211.7, 1314.7", \ + "1734.0, 1734.0, 1734.0, 1785.5, 1888.5", \ + "2860.5, 2860.5, 2860.5, 2912.0, 3014.9"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("618.3, 618.3, 618.3, 669.8, 772.7", \ + "681.2, 681.2, 681.2, 732.7, 835.6", \ + "798.1, 798.1, 798.1, 849.6, 952.5", \ + "1021.4, 1021.4, 1021.4, 1072.8, 1175.8", \ + "1458.6, 1458.6, 1458.6, 1510.0, 1613.0"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__30) { + values ("1094.4, 1094.4, 1094.4, 1145.9, 1248.8", \ + "1233.7, 1233.7, 1233.7, 1285.1, 1388.1", \ + "1499.0, 1499.0, 1499.0, 1550.5, 1653.4", \ + "2025.8, 2025.8, 2025.8, 2077.2, 2180.2", \ + "3080.9, 3080.9, 3080.9, 3132.3, 3235.3"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("743.7, 743.7, 743.7, 795.2, 898.1", \ + "850.4, 850.4, 850.4, 901.9, 1004.8", \ + "1053.1, 1053.1, 1053.1, 1104.6, 1207.5", \ + "1447.9, 1447.9, 1447.9, 1499.4, 1602.3", \ + "2227.3, 2227.3, 2227.3, 2278.8, 2381.7"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__30) { + values ("1244.6, 1244.6, 1244.6, 1296.0, 1399.0", \ + "1367.0, 1367.0, 1367.0, 1418.4, 1521.4", \ + "1601.6, 1601.6, 1601.6, 1653.1, 1756.0", \ + "2063.5, 2063.5, 2063.5, 2115.0, 2217.9", \ + "2990.8, 2990.8, 2990.8, 3042.3, 3145.2"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("810.5, 810.5, 810.5, 861.9, 964.9", \ + "972.5, 972.5, 972.5, 1024.0, 1126.9", \ + "1282.4, 1282.4, 1282.4, 1333.9, 1436.8", \ + "1892.1, 1892.1, 1892.1, 1943.6, 2046.5", \ + "3101.9, 3101.9, 3101.9, 3153.4, 3256.3"); + } + } + } + } + + cell (noa22_x1) { + area : 0.0 ; + cell_leakage_power : 3.8 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 8.8 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 8.9 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 0.0002 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 5.9 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0))" ; + value : 0.00018 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 3 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.0001 ; + } + pin (i2) { + direction : input ; + capacitance : 7.06 ; + } + pin (i1) { + direction : input ; + capacitance : 6.52 ; + } + pin (i0) { + direction : input ; + capacitance : 6.68 ; + } + pin (nq) { + function : "((!(i1) & !(i2)) | (!(i0) & !(i2)))" ; + direction : output ; + capacitance : 4.16 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("37.2, 37.2, 37.2, 49.3, 72.1", \ + "53.9, 53.9, 53.9, 66.5, 90.5", \ + "83.1, 83.1, 83.1, 96.2, 121.4", \ + "138.8, 138.8, 138.8, 152.3, 178.6", \ + "248.8, 248.8, 248.8, 262.5, 289.6"); + } + rise_transition (inslew_load_5x5__31) { + values ("71.1, 71.1, 71.1, 91.2, 130.6", \ + "119.6, 119.6, 119.6, 139.3, 178.6", \ + "210.4, 210.4, 210.4, 230.1, 269.3", \ + "388.3, 388.3, 388.3, 408.1, 447.7", \ + "742.3, 742.3, 742.3, 762.2, 802.0"); + } + cell_fall (inslew_load_5x5__31) { + values ("13.1, 13.1, 13.1, 20.6, 34.1", \ + "6.6, 6.6, 6.6, 15.3, 30.9", \ + "-8.7, -8.7, -8.7, 1.2, 19.4", \ + "-41.5, -41.5, -41.5, -30.3, -9.6", \ + "-108.3, -108.3, -108.3, -96.3, -73.6"); + } + fall_transition (inslew_load_5x5__31) { + values ("26.3, 26.3, 26.3, 34.2, 49.7", \ + "37.7, 37.7, 37.7, 46.0, 61.8", \ + "59.7, 59.7, 59.7, 68.3, 84.8", \ + "102.8, 102.8, 102.8, 111.8, 129.1", \ + "188.5, 188.5, 188.5, 197.7, 215.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("26.1, 26.1, 26.1, 38.8, 62.3", \ + "36.5, 36.5, 36.5, 50.0, 75.0", \ + "54.0, 54.0, 54.0, 68.1, 94.8", \ + "86.8, 86.8, 86.8, 101.4, 129.5", \ + "151.4, 151.4, 151.4, 166.2, 195.3"); + } + rise_transition (inslew_load_5x5__31) { + values ("54.1, 54.1, 54.1, 73.7, 113.4", \ + "93.8, 93.8, 93.8, 113.7, 153.0", \ + "168.3, 168.3, 168.3, 188.3, 228.0", \ + "314.4, 314.4, 314.4, 334.6, 374.7", \ + "605.3, 605.3, 605.3, 625.5, 666.0"); + } + cell_fall (inslew_load_5x5__31) { + values ("9.7, 9.7, 9.7, 19.1, 34.4", \ + "6.2, 6.2, 6.2, 17.0, 35.2", \ + "-2.3, -2.3, -2.3, 9.6, 30.7", \ + "-20.5, -20.5, -20.5, -7.7, 15.8", \ + "-57.6, -57.6, -57.6, -44.3, -18.9"); + } + fall_transition (inslew_load_5x5__31) { + values ("20.3, 20.3, 20.3, 28.8, 44.8", \ + "33.9, 33.9, 33.9, 42.8, 59.5", \ + "59.8, 59.8, 59.8, 69.1, 86.7", \ + "110.9, 110.9, 110.9, 120.5, 139.0", \ + "212.7, 212.7, 212.7, 222.4, 241.6"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("43.9, 43.9, 43.9, 55.0, 76.8", \ + "51.4, 51.4, 51.4, 62.8, 85.1", \ + "65.3, 65.3, 65.3, 76.8, 99.5", \ + "92.2, 92.2, 92.2, 104.0, 127.2", \ + "145.6, 145.6, 145.6, 157.5, 181.1"); + } + rise_transition (inslew_load_5x5__31) { + values ("94.8, 94.8, 94.8, 114.0, 152.9", \ + "137.7, 137.7, 137.7, 156.7, 195.2", \ + "221.2, 221.2, 221.2, 240.0, 277.8", \ + "385.2, 385.2, 385.2, 406.1, 443.5", \ + "714.4, 714.4, 714.4, 733.3, 771.0"); + } + cell_fall (inslew_load_5x5__31) { + values ("16.1, 16.1, 16.1, 22.2, 32.9", \ + "16.1, 16.1, 16.1, 23.1, 35.7", \ + "14.0, 14.0, 14.0, 21.8, 36.4", \ + "8.4, 8.4, 8.4, 16.8, 32.9", \ + "-3.5, -3.5, -3.5, 5.2, 22.3"); + } + fall_transition (inslew_load_5x5__31) { + values ("24.2, 24.2, 24.2, 29.3, 38.7", \ + "40.0, 40.0, 40.0, 45.3, 55.4", \ + "70.5, 70.5, 70.5, 76.1, 86.9", \ + "130.6, 130.6, 130.6, 136.5, 147.9", \ + "250.4, 250.4, 250.4, 256.4, 268.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__31) { + values ("179.8, 179.8, 179.8, 231.8, 335.8", \ + "274.0, 274.0, 274.0, 326.0, 430.0", \ + "462.4, 462.4, 462.4, 514.4, 618.4", \ + "839.2, 839.2, 839.2, 891.2, 995.1", \ + "1592.7, 1592.7, 1592.7, 1644.7, 1748.6"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("132.3, 132.3, 132.3, 184.3, 288.2", \ + "170.4, 170.4, 170.4, 222.4, 326.4", \ + "246.7, 246.7, 246.7, 298.7, 402.6", \ + "399.2, 399.2, 399.2, 451.2, 555.1", \ + "704.2, 704.2, 704.2, 756.2, 860.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__31) { + values ("129.5, 129.5, 129.5, 181.4, 285.4", \ + "203.4, 203.4, 203.4, 255.4, 359.3", \ + "351.2, 351.2, 351.2, 403.2, 507.2", \ + "646.9, 646.9, 646.9, 698.9, 802.9", \ + "1238.3, 1238.3, 1238.3, 1290.3, 1394.3"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("91.1, 91.1, 91.1, 143.0, 247.0", \ + "133.7, 133.7, 133.7, 185.7, 289.6", \ + "218.9, 218.9, 218.9, 270.9, 374.9", \ + "389.5, 389.5, 389.5, 441.5, 545.4", \ + "730.5, 730.5, 730.5, 782.5, 886.5"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__31) { + values ("240.0, 240.0, 240.0, 292.0, 396.0", \ + "338.3, 338.3, 338.3, 390.3, 494.2", \ + "534.8, 534.8, 534.8, 586.8, 690.8", \ + "927.9, 927.9, 927.9, 979.9, 1083.9", \ + "1714.0, 1714.0, 1714.0, 1766.0, 1870.0"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("177.0, 177.0, 177.0, 229.0, 333.0", \ + "250.5, 250.5, 250.5, 302.5, 406.4", \ + "397.4, 397.4, 397.4, 449.4, 553.3", \ + "691.2, 691.2, 691.2, 743.2, 847.2", \ + "1278.9, 1278.9, 1278.9, 1330.9, 1434.8"); + } + } + } + } + + cell (noa22_x4) { + area : 0.0 ; + cell_leakage_power : 6.1 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 8.7 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 7.8 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 6.8 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !(i2))" ; + value : 1 ; + } + pin (i2) { + direction : input ; + capacitance : 5.38 ; + } + pin (i1) { + direction : input ; + capacitance : 5.61 ; + } + pin (i0) { + direction : input ; + capacitance : 5.60 ; + } + pin (nq) { + function : "((!(i1) & !(i2)) | (!(i2) & !(i0)))" ; + direction : output ; + capacitance : 4.21 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__32) { + values ("117.3, 117.3, 117.3, 121.6, 129.7", \ + "143.5, 143.5, 143.5, 147.9, 156.2", \ + "186.5, 186.5, 186.5, 191.0, 199.5", \ + "264.6, 264.6, 264.6, 269.3, 278.1", \ + "414.4, 414.4, 414.4, 419.0, 427.9"); + } + rise_transition (inslew_load_5x5__32) { + values ("44.5, 44.5, 44.5, 50.0, 60.8", \ + "55.8, 55.8, 55.8, 61.3, 72.2", \ + "76.0, 76.0, 76.0, 81.5, 92.5", \ + "114.2, 114.2, 114.2, 119.7, 130.6", \ + "188.6, 188.6, 188.6, 194.3, 205.6"); + } + cell_fall (inslew_load_5x5__32) { + values ("75.0, 75.0, 75.0, 79.4, 87.2", \ + "71.4, 71.4, 71.4, 75.7, 83.6", \ + "58.6, 58.6, 58.6, 62.8, 70.9", \ + "26.0, 26.0, 26.0, 30.2, 38.2", \ + "-46.7, -46.7, -46.7, -42.2, -34.2"); + } + fall_transition (inslew_load_5x5__32) { + values ("31.9, 31.9, 31.9, 34.6, 39.9", \ + "34.3, 34.3, 34.3, 37.1, 42.3", \ + "38.6, 38.6, 38.6, 41.4, 46.7", \ + "46.5, 46.5, 46.5, 49.2, 54.7", \ + "61.4, 61.4, 61.4, 64.1, 69.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__32) { + values ("103.7, 103.7, 103.7, 108.1, 116.0", \ + "124.0, 124.0, 124.0, 128.4, 136.6", \ + "156.0, 156.0, 156.0, 160.5, 168.8", \ + "211.5, 211.5, 211.5, 216.1, 224.8", \ + "316.3, 316.3, 316.3, 320.9, 329.9"); + } + rise_transition (inslew_load_5x5__32) { + values ("40.4, 40.4, 40.4, 45.9, 56.7", \ + "50.1, 50.1, 50.1, 55.7, 66.5", \ + "67.3, 67.3, 67.3, 72.8, 83.8", \ + "99.7, 99.7, 99.7, 105.2, 116.2", \ + "162.3, 162.3, 162.3, 168.0, 179.0"); + } + cell_fall (inslew_load_5x5__32) { + values ("71.5, 71.5, 71.5, 76.0, 83.7", \ + "71.2, 71.2, 71.2, 75.6, 83.5", \ + "64.7, 64.7, 64.7, 68.9, 76.9", \ + "45.3, 45.3, 45.3, 49.5, 57.4", \ + "-0.8, -0.8, -0.8, 3.7, 11.7"); + } + fall_transition (inslew_load_5x5__32) { + values ("30.7, 30.7, 30.7, 33.4, 38.7", \ + "33.5, 33.5, 33.5, 36.3, 41.5", \ + "38.5, 38.5, 38.5, 41.3, 46.6", \ + "47.8, 47.8, 47.8, 50.5, 56.1", \ + "65.4, 65.4, 65.4, 68.1, 73.6"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__32) { + values ("128.5, 128.5, 128.5, 132.8, 141.0", \ + "144.2, 144.2, 144.2, 148.6, 156.9", \ + "170.4, 170.4, 170.4, 174.9, 183.4", \ + "219.2, 219.2, 219.2, 223.9, 232.7", \ + "312.8, 312.8, 312.8, 317.3, 326.3"); + } + rise_transition (inslew_load_5x5__32) { + values ("50.3, 50.3, 50.3, 55.9, 66.8", \ + "60.2, 60.2, 60.2, 65.8, 76.7", \ + "78.7, 78.7, 78.7, 84.2, 95.2", \ + "114.3, 114.3, 114.3, 119.8, 130.8", \ + "184.3, 184.3, 184.3, 190.0, 201.3"); + } + cell_fall (inslew_load_5x5__32) { + values ("73.8, 73.8, 73.8, 78.3, 86.0", \ + "77.2, 77.2, 77.2, 81.5, 89.4", \ + "77.8, 77.8, 77.8, 82.0, 90.1", \ + "72.2, 72.2, 72.2, 76.5, 84.4", \ + "53.8, 53.8, 53.8, 58.4, 66.6"); + } + fall_transition (inslew_load_5x5__32) { + values ("30.6, 30.6, 30.6, 33.4, 38.6", \ + "34.0, 34.0, 34.0, 36.8, 42.0", \ + "40.1, 40.1, 40.1, 42.9, 48.2", \ + "51.3, 51.3, 51.3, 54.0, 59.6", \ + "72.7, 72.7, 72.7, 75.5, 80.9"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__32) { + values ("725.3, 725.3, 725.3, 778.0, 883.4", \ + "904.0, 904.0, 904.0, 956.7, 1062.1", \ + "1242.1, 1242.1, 1242.1, 1294.7, 1400.1", \ + "1903.1, 1903.1, 1903.1, 1955.8, 2061.1", \ + "3215.6, 3215.6, 3215.6, 3268.3, 3373.7"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("646.5, 646.5, 646.5, 699.2, 804.6", \ + "698.7, 698.7, 698.7, 751.4, 856.8", \ + "797.5, 797.5, 797.5, 850.2, 955.5", \ + "987.7, 987.7, 987.7, 1040.3, 1145.7", \ + "1360.5, 1360.5, 1360.5, 1413.2, 1518.6"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__32) { + values ("648.8, 648.8, 648.8, 701.5, 806.9", \ + "797.2, 797.2, 797.2, 849.9, 955.3", \ + "1077.6, 1077.6, 1077.6, 1130.3, 1235.6", \ + "1624.8, 1624.8, 1624.8, 1677.5, 1782.9", \ + "2707.8, 2707.8, 2707.8, 2760.5, 2865.8"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("598.0, 598.0, 598.0, 650.6, 756.0", \ + "657.8, 657.8, 657.8, 710.5, 815.9", \ + "771.0, 771.0, 771.0, 823.7, 929.0", \ + "990.1, 990.1, 990.1, 1042.8, 1148.2", \ + "1419.7, 1419.7, 1419.7, 1472.4, 1577.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__32) { + values ("825.0, 825.0, 825.0, 877.7, 983.1", \ + "993.6, 993.6, 993.6, 1046.3, 1151.6", \ + "1320.3, 1320.3, 1320.3, 1373.0, 1478.3", \ + "1966.6, 1966.6, 1966.6, 2019.3, 2124.7", \ + "3256.0, 3256.0, 3256.0, 3308.7, 3414.1"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("658.3, 658.3, 658.3, 711.0, 816.4", \ + "745.4, 745.4, 745.4, 798.1, 903.5", \ + "913.3, 913.3, 913.3, 966.0, 1071.3", \ + "1239.6, 1239.6, 1239.6, 1292.3, 1397.7", \ + "1884.3, 1884.3, 1884.3, 1936.9, 2042.3"); + } + } + } + } + + cell (noa2a22_x1) { + area : 0.0 ; + cell_leakage_power : 4 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 18 ; + } + leakage_power () { + when : "(!(i3) & i2 & !(i1) & i0)" ; + value : 0.0002 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3)" ; + value : 12 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3) | (!(i0) & i1 & i2 & !(i3)))" ; + value : 0.00018 ; + } + leakage_power () { + when : "(i3 & !(i2) & i1 & !(i0))" ; + value : 0.00016 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 6.1 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & !(i1) & i2 & !(i3)))" ; + value : 0.0001 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & !(i2) & i3)))" ; + value : 8.4e-05 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 3.5e-06 ; + } + pin (i3) { + direction : input ; + capacitance : 6.79 ; + } + pin (i2) { + direction : input ; + capacitance : 6.83 ; + } + pin (i1) { + direction : input ; + capacitance : 6.65 ; + } + pin (i0) { + direction : input ; + capacitance : 6.65 ; + } + pin (nq) { + function : "((((!(i1) & !(i3)) | (!(i1) & !(i2))) | (!(i0) & !(i3))) | (!(i0) & !(i2)))" ; + direction : output ; + capacitance : 4.15 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__33) { + values ("36.7, 36.7, 36.7, 48.8, 71.6", \ + "53.5, 53.5, 53.5, 66.0, 90.0", \ + "82.7, 82.7, 82.7, 95.7, 120.8", \ + "138.4, 138.4, 138.4, 151.9, 178.1", \ + "248.4, 248.4, 248.4, 262.1, 289.1"); + } + rise_transition (inslew_load_5x5__33) { + values ("70.9, 70.9, 70.9, 90.9, 130.3", \ + "119.5, 119.5, 119.5, 139.1, 178.3", \ + "210.2, 210.2, 210.2, 229.9, 269.0", \ + "388.1, 388.1, 388.1, 407.9, 447.4", \ + "742.1, 742.1, 742.1, 761.9, 801.7"); + } + cell_fall (inslew_load_5x5__33) { + values ("13.0, 13.0, 13.0, 20.5, 34.0", \ + "6.5, 6.5, 6.5, 15.3, 30.8", \ + "-8.7, -8.7, -8.7, 1.2, 19.4", \ + "-41.5, -41.5, -41.5, -30.3, -9.6", \ + "-108.3, -108.3, -108.3, -96.4, -73.7"); + } + fall_transition (inslew_load_5x5__33) { + values ("26.3, 26.3, 26.3, 34.2, 49.6", \ + "37.7, 37.7, 37.7, 45.9, 61.7", \ + "59.7, 59.7, 59.7, 68.3, 84.8", \ + "102.8, 102.8, 102.8, 111.7, 129.0", \ + "188.5, 188.5, 188.5, 197.6, 215.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__33) { + values ("25.8, 25.8, 25.8, 38.2, 61.8", \ + "36.2, 36.2, 36.2, 49.6, 74.5", \ + "53.6, 53.6, 53.6, 67.7, 94.3", \ + "86.5, 86.5, 86.5, 101.0, 129.1", \ + "151.1, 151.1, 151.1, 165.9, 194.9"); + } + rise_transition (inslew_load_5x5__33) { + values ("54.1, 54.1, 54.1, 73.4, 113.1", \ + "93.7, 93.7, 93.7, 113.5, 152.7", \ + "168.1, 168.1, 168.1, 188.1, 227.7", \ + "314.3, 314.3, 314.3, 334.4, 374.4", \ + "605.1, 605.1, 605.1, 625.3, 665.7"); + } + cell_fall (inslew_load_5x5__33) { + values ("9.7, 9.7, 9.7, 19.0, 34.4", \ + "6.2, 6.2, 6.2, 17.0, 35.1", \ + "-2.3, -2.3, -2.3, 9.6, 30.6", \ + "-20.6, -20.6, -20.6, -7.8, 15.7", \ + "-57.6, -57.6, -57.6, -44.3, -19.0"); + } + fall_transition (inslew_load_5x5__33) { + values ("20.3, 20.3, 20.3, 28.8, 44.7", \ + "33.9, 33.9, 33.9, 42.8, 59.5", \ + "59.8, 59.8, 59.8, 69.0, 86.7", \ + "110.9, 110.9, 110.9, 120.4, 138.9", \ + "212.7, 212.7, 212.7, 222.4, 241.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__33) { + values ("52.0, 52.0, 52.0, 63.0, 84.7", \ + "59.8, 59.8, 59.8, 71.1, 93.1", \ + "73.8, 73.8, 73.8, 85.2, 107.7", \ + "100.9, 100.9, 100.9, 112.5, 135.5", \ + "154.3, 154.3, 154.3, 166.2, 189.7"); + } + rise_transition (inslew_load_5x5__33) { + values ("108.9, 108.9, 108.9, 128.2, 167.1", \ + "151.6, 151.6, 151.6, 170.7, 209.2", \ + "234.9, 234.9, 234.9, 253.7, 291.6", \ + "401.1, 401.1, 401.1, 419.7, 457.1", \ + "728.2, 728.2, 728.2, 747.0, 784.7"); + } + cell_fall (inslew_load_5x5__33) { + values ("25.5, 25.5, 25.5, 32.1, 44.6", \ + "26.5, 26.5, 26.5, 33.8, 47.6", \ + "25.9, 25.9, 25.9, 34.0, 49.4", \ + "22.8, 22.8, 22.8, 31.6, 48.5", \ + "15.3, 15.3, 15.3, 24.5, 42.5"); + } + fall_transition (inslew_load_5x5__33) { + values ("39.2, 39.2, 39.2, 47.0, 62.4", \ + "56.8, 56.8, 56.8, 64.6, 80.0", \ + "90.8, 90.8, 90.8, 98.7, 114.5", \ + "158.0, 158.0, 158.0, 166.1, 182.2", \ + "291.9, 291.9, 291.9, 300.1, 316.4"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__33) { + values ("40.7, 40.7, 40.7, 51.9, 73.7", \ + "42.2, 42.2, 42.2, 53.7, 76.3", \ + "44.1, 44.1, 44.1, 56.0, 79.2", \ + "46.9, 46.9, 46.9, 59.2, 83.2", \ + "51.6, 51.6, 51.6, 64.1, 89.0"); + } + rise_transition (inslew_load_5x5__33) { + values ("89.4, 89.4, 89.4, 108.6, 147.4", \ + "122.6, 122.6, 122.6, 141.5, 179.7", \ + "186.5, 186.5, 186.5, 206.4, 243.9", \ + "314.3, 314.3, 314.3, 333.2, 370.9", \ + "569.5, 569.5, 569.5, 588.4, 626.2"); + } + cell_fall (inslew_load_5x5__33) { + values ("24.3, 24.3, 24.3, 31.7, 45.4", \ + "29.7, 29.7, 29.7, 38.1, 53.6", \ + "37.9, 37.9, 37.9, 47.1, 64.5", \ + "52.4, 52.4, 52.4, 62.3, 81.2", \ + "80.6, 80.6, 80.6, 90.9, 110.8"); + } + fall_transition (inslew_load_5x5__33) { + values ("33.6, 33.6, 33.6, 41.6, 57.2", \ + "54.0, 54.0, 54.0, 62.2, 78.1", \ + "93.0, 93.0, 93.0, 101.3, 117.8", \ + "169.8, 169.8, 169.8, 178.3, 195.2", \ + "322.8, 322.8, 322.8, 331.4, 348.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__33) { + values ("179.8, 179.8, 179.8, 231.7, 335.4", \ + "273.9, 273.9, 273.9, 325.8, 429.6", \ + "462.3, 462.3, 462.3, 514.2, 618.0", \ + "839.1, 839.1, 839.1, 891.0, 994.8", \ + "1592.6, 1592.6, 1592.6, 1644.5, 1748.3"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("132.2, 132.2, 132.2, 184.1, 287.9", \ + "170.3, 170.3, 170.3, 222.2, 326.0", \ + "246.6, 246.6, 246.6, 298.5, 402.3", \ + "399.1, 399.1, 399.1, 451.0, 554.8", \ + "704.1, 704.1, 704.1, 756.0, 859.8"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__33) { + values ("129.4, 129.4, 129.4, 181.3, 285.1", \ + "203.3, 203.3, 203.3, 255.2, 359.0", \ + "351.2, 351.2, 351.2, 403.0, 506.8", \ + "646.8, 646.8, 646.8, 698.7, 802.5", \ + "1238.2, 1238.2, 1238.2, 1290.1, 1393.9"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("91.0, 91.0, 91.0, 142.9, 246.7", \ + "133.6, 133.6, 133.6, 185.5, 289.3", \ + "218.9, 218.9, 218.9, 270.8, 374.6", \ + "389.4, 389.4, 389.4, 441.3, 545.1", \ + "730.4, 730.4, 730.4, 782.3, 886.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__33) { + values ("278.0, 278.0, 278.0, 329.9, 433.7", \ + "376.3, 376.3, 376.3, 428.2, 532.0", \ + "572.8, 572.8, 572.8, 624.7, 728.5", \ + "965.9, 965.9, 965.9, 1017.8, 1121.6", \ + "1752.0, 1752.0, 1752.0, 1803.9, 1907.7"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("225.7, 225.7, 225.7, 277.6, 381.4", \ + "299.2, 299.2, 299.2, 351.1, 454.9", \ + "446.1, 446.1, 446.1, 498.0, 601.8", \ + "739.9, 739.9, 739.9, 791.8, 895.6", \ + "1327.6, 1327.6, 1327.6, 1379.5, 1483.3"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__33) { + values ("222.5, 222.5, 222.5, 274.4, 378.2", \ + "295.3, 295.3, 295.3, 347.2, 451.0", \ + "441.0, 441.0, 441.0, 492.9, 596.7", \ + "732.3, 732.3, 732.3, 784.2, 888.0", \ + "1315.0, 1315.0, 1315.0, 1366.9, 1470.7"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("184.7, 184.7, 184.7, 236.6, 340.4", \ + "263.0, 263.0, 263.0, 314.9, 418.7", \ + "419.4, 419.4, 419.4, 471.3, 575.1", \ + "732.4, 732.4, 732.4, 784.3, 888.1", \ + "1358.2, 1358.2, 1358.2, 1410.1, 1513.9"); + } + } + } + } + + cell (noa2a22_x4) { + area : 0.0 ; + cell_leakage_power : 6.5 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 9.5 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3)" ; + value : 8.3 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 7.2 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!(i2) | !(i3)))" ; + value : 1 ; + } + pin (i3) { + direction : input ; + capacitance : 4.18 ; + } + pin (i2) { + direction : input ; + capacitance : 4.08 ; + } + pin (i1) { + direction : input ; + capacitance : 4.01 ; + } + pin (i0) { + direction : input ; + capacitance : 3.88 ; + } + pin (nq) { + function : "((!(i0) & (!(i3) | !(i2))) | (!((i3 & i2)) & !(i1)))" ; + direction : output ; + capacitance : 4.20 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("118.2, 118.2, 118.2, 122.5, 130.6", \ + "139.7, 139.7, 139.7, 144.1, 152.3", \ + "175.3, 175.3, 175.3, 179.7, 188.2", \ + "238.8, 238.8, 238.8, 243.4, 252.2", \ + "359.7, 359.7, 359.7, 364.2, 373.1"); + } + rise_transition (inslew_load_5x5__21) { + values ("46.1, 46.1, 46.1, 51.6, 62.4", \ + "56.1, 56.1, 56.1, 61.7, 72.6", \ + "74.7, 74.7, 74.7, 80.2, 91.2", \ + "109.9, 109.9, 109.9, 115.4, 126.3", \ + "178.4, 178.4, 178.4, 184.1, 195.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("84.3, 84.3, 84.3, 88.6, 96.5", \ + "83.1, 83.1, 83.1, 87.2, 95.3", \ + "75.2, 75.2, 75.2, 79.4, 87.4", \ + "52.2, 52.2, 52.2, 56.5, 64.3", \ + "-1.6, -1.6, -1.6, 2.9, 11.0"); + } + fall_transition (inslew_load_5x5__21) { + values ("33.7, 33.7, 33.7, 36.5, 41.7", \ + "36.5, 36.5, 36.5, 39.4, 44.5", \ + "41.5, 41.5, 41.5, 44.3, 49.6", \ + "50.9, 50.9, 50.9, 53.6, 59.2", \ + "68.7, 68.7, 68.7, 71.3, 76.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("106.2, 106.2, 106.2, 110.6, 118.5", \ + "121.7, 121.7, 121.7, 126.1, 134.3", \ + "146.1, 146.1, 146.1, 150.5, 158.8", \ + "186.7, 186.7, 186.7, 191.2, 199.9", \ + "261.3, 261.3, 261.3, 265.8, 274.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("42.3, 42.3, 42.3, 47.8, 58.6", \ + "50.7, 50.7, 50.7, 56.3, 67.1", \ + "66.2, 66.2, 66.2, 71.7, 82.7", \ + "95.4, 95.4, 95.4, 100.8, 111.8", \ + "151.7, 151.7, 151.7, 157.4, 168.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("82.0, 82.0, 82.0, 86.3, 94.2", \ + "85.2, 85.2, 85.2, 89.4, 97.4", \ + "84.9, 84.9, 84.9, 89.1, 97.1", \ + "77.1, 77.1, 77.1, 81.4, 89.2", \ + "54.2, 54.2, 54.2, 58.8, 67.0"); + } + fall_transition (inslew_load_5x5__21) { + values ("32.5, 32.5, 32.5, 35.2, 40.5", \ + "35.8, 35.8, 35.8, 38.6, 43.8", \ + "41.7, 41.7, 41.7, 44.5, 49.8", \ + "52.7, 52.7, 52.7, 55.4, 60.9", \ + "73.6, 73.6, 73.6, 76.3, 81.7"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("136.6, 136.6, 136.6, 141.0, 149.2", \ + "148.0, 148.0, 148.0, 152.5, 160.7", \ + "167.0, 167.0, 167.0, 171.5, 180.0", \ + "201.6, 201.6, 201.6, 206.3, 215.1", \ + "266.8, 266.8, 266.8, 271.4, 280.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("54.6, 54.6, 54.6, 60.1, 71.0", \ + "63.2, 63.2, 63.2, 68.7, 79.7", \ + "79.9, 79.9, 79.9, 85.3, 96.3", \ + "112.5, 112.5, 112.5, 118.0, 128.8", \ + "175.5, 175.5, 175.5, 181.2, 192.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("99.3, 99.3, 99.3, 103.4, 111.5", \ + "105.5, 105.5, 105.5, 109.6, 117.7", \ + "112.4, 112.4, 112.4, 116.7, 124.5", \ + "119.6, 119.6, 119.6, 124.0, 132.0", \ + "127.5, 127.5, 127.5, 132.2, 140.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("36.9, 36.9, 36.9, 39.7, 44.9", \ + "40.7, 40.7, 40.7, 43.6, 48.9", \ + "48.1, 48.1, 48.1, 50.8, 56.3", \ + "62.1, 62.1, 62.1, 64.8, 70.2", \ + "89.3, 89.3, 89.3, 92.0, 97.4"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("123.9, 123.9, 123.9, 128.3, 136.5", \ + "128.8, 128.8, 128.8, 133.2, 141.4", \ + "135.5, 135.5, 135.5, 140.0, 148.3", \ + "144.7, 144.7, 144.7, 149.2, 157.9", \ + "158.3, 158.3, 158.3, 162.8, 171.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("50.3, 50.3, 50.3, 55.8, 66.6", \ + "56.9, 56.9, 56.9, 62.5, 73.4", \ + "69.9, 69.9, 69.9, 75.4, 86.4", \ + "94.8, 94.8, 94.8, 100.2, 111.2", \ + "143.4, 143.4, 143.4, 149.2, 160.0"); + } + cell_fall (inslew_load_5x5__21) { + values ("98.0, 98.0, 98.0, 102.2, 110.2", \ + "110.1, 110.1, 110.1, 114.3, 122.3", \ + "127.2, 127.2, 127.2, 131.5, 139.3", \ + "153.9, 153.9, 153.9, 158.3, 166.4", \ + "200.4, 200.4, 200.4, 205.0, 213.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("35.5, 35.5, 35.5, 38.4, 43.6", \ + "40.2, 40.2, 40.2, 43.0, 48.3", \ + "48.7, 48.7, 48.7, 51.4, 57.0", \ + "64.7, 64.7, 64.7, 67.4, 72.8", \ + "95.8, 95.8, 95.8, 98.6, 104.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("699.4, 699.4, 699.4, 751.9, 856.9", \ + "843.3, 843.3, 843.3, 895.8, 1000.8", \ + "1119.5, 1119.5, 1119.5, 1172.0, 1277.0", \ + "1658.8, 1658.8, 1658.8, 1711.4, 1816.4", \ + "2729.1, 2729.1, 2729.1, 2781.6, 2886.6"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("645.5, 645.5, 645.5, 698.1, 803.1", \ + "699.1, 699.1, 699.1, 751.6, 856.7", \ + "800.4, 800.4, 800.4, 852.9, 957.9", \ + "996.4, 996.4, 996.4, 1048.9, 1153.9", \ + "1380.3, 1380.3, 1380.3, 1432.8, 1537.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("637.0, 637.0, 637.0, 689.5, 794.5", \ + "754.0, 754.0, 754.0, 806.6, 911.6", \ + "978.1, 978.1, 978.1, 1030.7, 1135.7", \ + "1414.6, 1414.6, 1414.6, 1467.1, 1572.1", \ + "2276.6, 2276.6, 2276.6, 2329.1, 2434.1"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("608.0, 608.0, 608.0, 660.5, 765.5", \ + "670.3, 670.3, 670.3, 722.8, 827.8", \ + "786.9, 786.9, 786.9, 839.4, 944.4", \ + "1012.0, 1012.0, 1012.0, 1064.5, 1169.6", \ + "1453.7, 1453.7, 1453.7, 1506.2, 1611.2"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("834.3, 834.3, 834.3, 886.9, 991.9", \ + "967.6, 967.6, 967.6, 1020.1, 1125.2", \ + "1229.7, 1229.7, 1229.7, 1282.2, 1387.3", \ + "1751.1, 1751.1, 1751.1, 1803.6, 1908.6", \ + "2781.1, 2781.1, 2781.1, 2833.6, 2938.6"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("733.2, 733.2, 733.2, 785.7, 890.7", \ + "818.5, 818.5, 818.5, 871.0, 976.1", \ + "985.0, 985.0, 985.0, 1037.5, 1142.6", \ + "1312.1, 1312.1, 1312.1, 1364.6, 1469.6", \ + "1959.6, 1959.6, 1959.6, 2012.1, 2117.2"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__21) { + values ("763.3, 763.3, 763.3, 815.8, 920.8", \ + "863.5, 863.5, 863.5, 916.0, 1021.0", \ + "1061.7, 1061.7, 1061.7, 1114.2, 1219.2", \ + "1450.1, 1450.1, 1450.1, 1502.6, 1607.6", \ + "2224.8, 2224.8, 2224.8, 2277.3, 2382.3"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("695.2, 695.2, 695.2, 747.7, 852.7", \ + "792.7, 792.7, 792.7, 845.2, 950.2", \ + "978.8, 978.8, 978.8, 1031.3, 1136.4", \ + "1342.0, 1342.0, 1342.0, 1394.5, 1499.5", \ + "2061.4, 2061.4, 2061.4, 2113.9, 2218.9"); + } + } + } + } + + cell (noa2a2a23_x1) { + area : 0.0 ; + cell_leakage_power : 9.7 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5))" ; + value : 18 ; + } + leakage_power () { + when : "(i0 & i1 & ((!(i2) & ((!(i3) & (!(i4) | !(i5))) | (!(i4) & !(i5)))) | (!(i3) & !(i4) & !(i5))))" ; + value : 11 ; + } + leakage_power () { + when : "(i5 & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 0.00031 ; + } + leakage_power () { + when : "((i0 | i1) & i2 & i3 & i4 & i5)" ; + value : 35 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5))" ; + value : 0.00029 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5)" ; + value : 30 ; + } + leakage_power () { + when : "(!(i5) & i4 & i3 & !(i2) & i1 & !(i0))" ; + value : 0.00025 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & !(i5)) | (!(i0) & i1 & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))))" ; + value : 0.00027 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & (i4 ^ i5)) | (!(i3) & i4 & i5))) | (!(i2) & i3 & i4 & i5))) | (!(i1) & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))))) | (!(i0) & ((i1 & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))) | (i2 & i3 & (i4 ^ i5)))))" ; + value : 24 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & i3 & !(i4) & !(i5)) | (!(i2) & !(i3) & i4 & i5))) | (i2 & i3 & !(i4) & !(i5)))" ; + value : 12 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i0) & !(i1) & i2 & !(i3) & !(i4) & i5))" ; + value : 0.00021 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & (i3 ^ i4) & !(i5)) | (!(i1) & !(i2) & i3 & i4 & !(i5))))" ; + value : 0.00017 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & (i3 ^ i4) & !(i5)) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))))))" ; + value : 0.00019 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & i4 & i5)" ; + value : 36 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i1) & !(i2) & (i3 ^ i4) & !(i5))))" ; + value : 8.6e-05 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))))" ; + value : 0.00011 ; + } + leakage_power () { + when : "(!(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.2e-06 ; + } + pin (i5) { + direction : input ; + capacitance : 6.78 ; + } + pin (i4) { + direction : input ; + capacitance : 6.71 ; + } + pin (i3) { + direction : input ; + capacitance : 6.69 ; + } + pin (i2) { + direction : input ; + capacitance : 6.73 ; + } + pin (i1) { + direction : input ; + capacitance : 6.52 ; + } + pin (i0) { + direction : input ; + capacitance : 6.52 ; + } + pin (nq) { + function : "(((((((((!(i5) & !(i3)) & !(i0)) | ((!(i5) & !(i3)) & !(i1))) | ((!(i5) & !(i2)) & !(i0))) | ((!(i5) & !(i2)) & !(i1))) | ((!(i4) & !(i3)) & !(i0))) | ((!(i4) & !(i3)) & !(i1))) | ((!(i4) & !(i2)) & !(i0))) | ((!(i4) & !(i2)) & !(i1)))" ; + direction : output ; + capacitance : 5.29 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("108.7, 108.7, 108.7, 129.2, 170.0", \ + "121.8, 121.8, 121.8, 142.5, 183.6", \ + "145.6, 145.6, 145.6, 166.4, 207.8", \ + "193.5, 193.5, 193.5, 214.2, 255.6", \ + "290.0, 290.0, 290.0, 310.7, 352.0"); + } + rise_transition (inslew_load_5x5__34) { + values ("212.0, 212.0, 212.0, 248.9, 323.0", \ + "272.5, 272.5, 272.5, 309.3, 383.1", \ + "386.5, 386.5, 386.5, 423.4, 497.4", \ + "611.5, 611.5, 611.5, 648.3, 722.0", \ + "1062.0, 1062.0, 1062.0, 1098.5, 1171.7"); + } + cell_fall (inslew_load_5x5__34) { + values ("32.4, 32.4, 32.4, 40.3, 55.6", \ + "34.2, 34.2, 34.2, 42.9, 59.7", \ + "34.4, 34.4, 34.4, 44.2, 62.9", \ + "31.9, 31.9, 31.9, 42.7, 63.4", \ + "24.8, 24.8, 24.8, 36.3, 58.6"); + } + fall_transition (inslew_load_5x5__34) { + values ("46.9, 46.9, 46.9, 56.9, 76.5", \ + "64.5, 64.5, 64.5, 74.4, 94.0", \ + "98.7, 98.7, 98.7, 108.7, 128.6", \ + "166.0, 166.0, 166.0, 176.3, 196.6", \ + "300.0, 300.0, 300.0, 310.4, 331.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("92.4, 92.4, 92.4, 112.9, 153.8", \ + "96.7, 96.7, 96.7, 117.6, 159.0", \ + "104.1, 104.1, 104.1, 125.1, 166.8", \ + "119.9, 119.9, 119.9, 140.8, 182.5", \ + "152.2, 152.2, 152.2, 173.2, 215.0"); + } + rise_transition (inslew_load_5x5__34) { + values ("182.8, 182.8, 182.8, 219.6, 293.5", \ + "228.4, 228.4, 228.4, 265.1, 338.8", \ + "313.6, 313.6, 313.6, 350.4, 424.2", \ + "483.0, 483.0, 483.0, 519.4, 592.3", \ + "822.6, 822.6, 822.6, 858.6, 931.0"); + } + cell_fall (inslew_load_5x5__34) { + values ("32.0, 32.0, 32.0, 40.8, 57.1", \ + "38.4, 38.4, 38.4, 48.3, 66.8", \ + "47.4, 47.4, 47.4, 58.5, 79.4", \ + "62.6, 62.6, 62.6, 74.7, 97.8", \ + "91.1, 91.1, 91.1, 103.8, 128.6"); + } + fall_transition (inslew_load_5x5__34) { + values ("41.5, 41.5, 41.5, 51.5, 71.3", \ + "62.1, 62.1, 62.1, 72.3, 92.3", \ + "101.3, 101.3, 101.3, 111.8, 132.4", \ + "178.3, 178.3, 178.3, 189.1, 210.3", \ + "331.3, 331.3, 331.3, 342.3, 364.0"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("85.4, 85.4, 85.4, 106.2, 147.4", \ + "106.5, 106.5, 106.5, 127.5, 169.1", \ + "143.4, 143.4, 143.4, 164.9, 207.0", \ + "214.8, 214.8, 214.8, 236.3, 279.0", \ + "356.3, 356.3, 356.3, 378.0, 421.2"); + } + rise_transition (inslew_load_5x5__34) { + values ("160.7, 160.7, 160.7, 198.1, 273.4", \ + "223.7, 223.7, 223.7, 260.8, 335.5", \ + "340.5, 340.5, 340.5, 377.2, 451.2", \ + "570.5, 570.5, 570.5, 606.8, 679.8", \ + "1029.1, 1029.1, 1029.1, 1065.1, 1137.4"); + } + cell_fall (inslew_load_5x5__34) { + values ("23.5, 23.5, 23.5, 31.9, 47.8", \ + "18.7, 18.7, 18.7, 28.4, 46.3", \ + "5.1, 5.1, 5.1, 16.5, 37.4", \ + "-26.1, -26.1, -26.1, -13.0, 11.3", \ + "-91.9, -91.9, -91.9, -77.5, -50.1"); + } + fall_transition (inslew_load_5x5__34) { + values ("36.9, 36.9, 36.9, 46.8, 66.5", \ + "48.7, 48.7, 48.7, 58.9, 78.6", \ + "71.2, 71.2, 71.2, 81.8, 102.2", \ + "114.8, 114.8, 114.8, 125.8, 147.3", \ + "200.9, 200.9, 200.9, 212.3, 234.7"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("71.1, 71.1, 71.1, 92.0, 133.4", \ + "84.6, 84.6, 84.6, 105.9, 147.8", \ + "107.5, 107.5, 107.5, 129.2, 172.2", \ + "151.4, 151.4, 151.4, 173.5, 217.1", \ + "237.8, 237.8, 237.8, 260.3, 304.7"); + } + rise_transition (inslew_load_5x5__34) { + values ("135.4, 135.4, 135.4, 172.6, 247.7", \ + "185.9, 185.9, 185.9, 222.8, 297.2", \ + "280.1, 280.1, 280.1, 316.5, 389.9", \ + "466.1, 466.1, 466.1, 502.1, 574.4", \ + "833.0, 833.0, 833.0, 873.0, 944.6"); + } + cell_fall (inslew_load_5x5__34) { + values ("22.4, 22.4, 22.4, 32.0, 49.2", \ + "20.9, 20.9, 20.9, 32.3, 52.5", \ + "14.0, 14.0, 14.0, 27.3, 51.2", \ + "-3.0, -3.0, -3.0, 11.9, 39.4", \ + "-39.4, -39.4, -39.4, -23.2, 7.2"); + } + fall_transition (inslew_load_5x5__34) { + values ("31.7, 31.7, 31.7, 41.9, 61.7", \ + "45.8, 45.8, 45.8, 56.4, 76.9", \ + "72.2, 72.2, 72.2, 83.5, 105.0", \ + "123.7, 123.7, 123.7, 135.5, 158.3", \ + "225.8, 225.8, 225.8, 238.0, 261.8"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("40.0, 40.0, 40.0, 62.4, 104.8", \ + "56.9, 56.9, 56.9, 79.9, 124.1", \ + "90.5, 90.5, 90.5, 113.6, 159.3", \ + "153.7, 153.7, 153.7, 177.6, 224.7", \ + "276.1, 276.1, 276.1, 300.7, 348.7"); + } + rise_transition (inslew_load_5x5__34) { + values ("77.9, 77.9, 77.9, 115.4, 191.3", \ + "127.7, 127.7, 127.7, 165.3, 240.5", \ + "227.0, 227.0, 227.0, 263.2, 338.8", \ + "419.6, 419.6, 419.6, 456.2, 530.2", \ + "799.1, 799.1, 799.1, 836.2, 909.7"); + } + cell_fall (inslew_load_5x5__34) { + values ("10.1, 10.1, 10.1, 21.7, 40.3", \ + "3.0, 3.0, 3.0, 16.9, 39.6", \ + "-13.8, -13.8, -13.8, 2.5, 30.0", \ + "-49.6, -49.6, -49.6, -31.1, 1.2", \ + "-122.5, -122.5, -122.5, -102.6, -66.0"); + } + fall_transition (inslew_load_5x5__34) { + values ("20.6, 20.6, 20.6, 31.4, 51.4", \ + "31.1, 31.1, 31.1, 42.6, 63.8", \ + "50.9, 50.9, 50.9, 63.3, 86.0", \ + "89.6, 89.6, 89.6, 102.6, 127.2", \ + "166.2, 166.2, 166.2, 179.8, 205.8"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("54.0, 54.0, 54.0, 75.6, 117.6", \ + "77.4, 77.4, 77.4, 99.8, 143.1", \ + "123.0, 123.0, 123.0, 145.9, 190.2", \ + "210.6, 210.6, 210.6, 233.8, 279.3", \ + "381.0, 381.0, 381.0, 404.6, 451.1"); + } + rise_transition (inslew_load_5x5__34) { + values ("100.8, 100.8, 100.8, 138.5, 214.8", \ + "161.2, 161.2, 161.2, 198.7, 274.2", \ + "278.2, 278.2, 278.2, 316.7, 390.8", \ + "507.7, 507.7, 507.7, 544.8, 619.0", \ + "960.0, 960.0, 960.0, 997.0, 1071.1"); + } + cell_fall (inslew_load_5x5__34) { + values ("13.3, 13.3, 13.3, 22.7, 39.4", \ + "4.1, 4.1, 4.1, 15.4, 34.9", \ + "-17.7, -17.7, -17.7, -4.1, 19.3", \ + "-64.9, -64.9, -64.9, -49.1, -21.0", \ + "-162.5, -162.5, -162.5, -144.8, -112.4"); + } + fall_transition (inslew_load_5x5__34) { + values ("26.5, 26.5, 26.5, 36.5, 56.2", \ + "35.4, 35.4, 35.4, 46.0, 66.0", \ + "52.2, 52.2, 52.2, 63.4, 84.7", \ + "84.4, 84.4, 84.4, 96.5, 119.2", \ + "147.9, 147.9, 147.9, 160.5, 184.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__34) { + values ("373.5, 373.5, 373.5, 439.6, 571.8", \ + "471.8, 471.8, 471.8, 537.9, 670.1", \ + "668.3, 668.3, 668.3, 734.4, 866.6", \ + "1061.4, 1061.4, 1061.4, 1127.5, 1259.7", \ + "1847.5, 1847.5, 1847.5, 1913.6, 2045.9"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("277.8, 277.8, 277.8, 343.9, 476.1", \ + "351.2, 351.2, 351.2, 417.4, 549.6", \ + "498.2, 498.2, 498.2, 564.3, 696.5", \ + "792.0, 792.0, 792.0, 858.1, 990.3", \ + "1379.7, 1379.7, 1379.7, 1445.8, 1578.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__34) { + values ("318.0, 318.0, 318.0, 384.1, 516.3", \ + "390.8, 390.8, 390.8, 456.9, 589.1", \ + "536.5, 536.5, 536.5, 602.6, 734.8", \ + "827.9, 827.9, 827.9, 894.0, 1026.2", \ + "1410.6, 1410.6, 1410.6, 1476.7, 1608.9"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("236.8, 236.8, 236.8, 302.9, 435.1", \ + "315.0, 315.0, 315.0, 381.1, 513.4", \ + "471.5, 471.5, 471.5, 537.6, 669.8", \ + "784.4, 784.4, 784.4, 850.5, 982.8", \ + "1410.3, 1410.3, 1410.3, 1476.4, 1608.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__34) { + values ("289.7, 289.7, 289.7, 355.8, 488.0", \ + "383.9, 383.9, 383.9, 450.0, 582.2", \ + "572.3, 572.3, 572.3, 638.4, 770.6", \ + "949.1, 949.1, 949.1, 1015.2, 1147.4", \ + "1702.6, 1702.6, 1702.6, 1768.7, 1900.9"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("203.1, 203.1, 203.1, 269.2, 401.4", \ + "241.2, 241.2, 241.2, 307.3, 439.5", \ + "317.5, 317.5, 317.5, 383.6, 515.8", \ + "470.0, 470.0, 470.0, 536.1, 668.3", \ + "775.0, 775.0, 775.0, 841.1, 973.3"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__34) { + values ("239.4, 239.4, 239.4, 305.5, 437.7", \ + "313.3, 313.3, 313.3, 379.4, 511.6", \ + "461.1, 461.1, 461.1, 527.2, 659.4", \ + "756.8, 756.8, 756.8, 822.9, 955.1", \ + "1348.2, 1348.2, 1348.2, 1414.3, 1546.5"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("161.9, 161.9, 161.9, 228.0, 360.2", \ + "204.5, 204.5, 204.5, 270.6, 402.8", \ + "289.7, 289.7, 289.7, 355.9, 488.1", \ + "460.3, 460.3, 460.3, 526.4, 658.6", \ + "801.3, 801.3, 801.3, 867.4, 999.6"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__34) { + values ("141.7, 141.7, 141.7, 207.8, 340.0", \ + "212.3, 212.3, 212.3, 278.4, 410.7", \ + "353.7, 353.7, 353.7, 419.8, 552.0", \ + "636.4, 636.4, 636.4, 702.6, 834.8", \ + "1201.9, 1201.9, 1201.9, 1268.0, 1400.2"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("88.4, 88.4, 88.4, 154.5, 286.7", \ + "115.5, 115.5, 115.5, 181.6, 313.8", \ + "169.7, 169.7, 169.7, 235.8, 368.0", \ + "278.2, 278.2, 278.2, 344.3, 476.5", \ + "495.2, 495.2, 495.2, 561.3, 693.5"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__34) { + values ("188.0, 188.0, 188.0, 254.1, 386.3", \ + "274.8, 274.8, 274.8, 340.9, 473.1", \ + "448.6, 448.6, 448.6, 514.7, 646.9", \ + "796.1, 796.1, 796.1, 862.2, 994.4", \ + "1491.0, 1491.0, 1491.0, 1557.1, 1689.3"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("130.6, 130.6, 130.6, 196.7, 328.9", \ + "154.2, 154.2, 154.2, 220.3, 352.5", \ + "201.4, 201.4, 201.4, 267.5, 399.7", \ + "295.7, 295.7, 295.7, 361.8, 494.0", \ + "484.4, 484.4, 484.4, 550.6, 682.8"); + } + } + } + } + + cell (noa2a2a23_x4) { + area : 0.0 ; + cell_leakage_power : 25 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5))" ; + value : 23 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & ((i3 & !(i4) & !(i5)) | (!(i3) & (i4 ^ i5))))))" ; + value : 17 ; + } + leakage_power () { + when : "(!(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 16 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5)" ; + value : 35 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & !(i3) & i4 & i5)" ; + value : 30 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & ((i3 & (i4 ^ i5)) | (!(i3) & i4 & i5))) | (!(i2) & i3 & i4 & i5))) | (i2 & i3 & (i4 ^ i5)))" ; + value : 29 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & i3 & !(i4) & !(i5)) | (!(i2) & !(i3) & i4 & i5))) | (i2 & i3 & !(i4) & !(i5)))" ; + value : 18 ; + } + leakage_power () { + when : "((!((i0 | i1)) & (i2 | i3) & i4 & i5) | (i2 & i3 & i4 & i5))" ; + value : 41 ; + } + leakage_power () { + when : "(i5 & i4 & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 42 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !((i2 & i3)) & (!(i4) | !(i5)))" ; + value : 1 ; + } + pin (i5) { + direction : input ; + capacitance : 6.53 ; + } + pin (i4) { + direction : input ; + capacitance : 6.52 ; + } + pin (i3) { + direction : input ; + capacitance : 6.54 ; + } + pin (i2) { + direction : input ; + capacitance : 6.53 ; + } + pin (i1) { + direction : input ; + capacitance : 6.59 ; + } + pin (i0) { + direction : input ; + capacitance : 6.52 ; + } + pin (nq) { + function : "((!(i4) & ((!(i2) & (!(i1) | !(i0))) | (!((i1 & i0)) & !(i3)))) | (!(i2) & !((i1 & i0)) & !(i5)) | (!((i1 & i0)) & !(i3) & !(i5)))" ; + direction : output ; + capacitance : 4.11 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("189.8, 189.8, 189.8, 194.1, 202.4", \ + "205.0, 205.0, 205.0, 209.4, 217.9", \ + "232.0, 232.0, 232.0, 236.5, 245.1", \ + "284.6, 284.6, 284.6, 289.1, 297.8", \ + "388.1, 388.1, 388.1, 392.6, 401.4"); + } + rise_transition (inslew_load_5x5__35) { + values ("72.5, 72.5, 72.5, 77.9, 88.6", \ + "84.6, 84.6, 84.6, 89.9, 100.7", \ + "106.9, 106.9, 106.9, 112.3, 123.0", \ + "150.2, 150.2, 150.2, 155.9, 166.5", \ + "236.5, 236.5, 236.5, 242.0, 253.2"); + } + cell_fall (inslew_load_5x5__35) { + values ("98.5, 98.5, 98.5, 102.5, 110.4", \ + "104.6, 104.6, 104.6, 108.7, 116.5", \ + "111.8, 111.8, 111.8, 116.0, 123.7", \ + "119.7, 119.7, 119.7, 124.0, 131.8", \ + "128.4, 128.4, 128.4, 132.9, 141.2"); + } + fall_transition (inslew_load_5x5__35) { + values ("36.5, 36.5, 36.5, 39.3, 44.4", \ + "40.3, 40.3, 40.3, 43.1, 48.3", \ + "47.6, 47.6, 47.6, 50.3, 55.7", \ + "61.4, 61.4, 61.4, 64.0, 69.4", \ + "88.3, 88.3, 88.3, 91.0, 96.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("172.3, 172.3, 172.3, 176.6, 184.7", \ + "178.7, 178.7, 178.7, 183.0, 191.3", \ + "188.8, 188.8, 188.8, 193.2, 201.7", \ + "208.6, 208.6, 208.6, 213.1, 221.8", \ + "247.1, 247.1, 247.1, 251.6, 260.3"); + } + rise_transition (inslew_load_5x5__35) { + values ("66.7, 66.7, 66.7, 72.1, 82.8", \ + "75.8, 75.8, 75.8, 81.2, 91.9", \ + "92.8, 92.8, 92.8, 98.1, 108.8", \ + "125.5, 125.5, 125.5, 131.0, 141.6", \ + "190.7, 190.7, 190.7, 196.3, 207.3"); + } + cell_fall (inslew_load_5x5__35) { + values ("97.3, 97.3, 97.3, 101.4, 109.2", \ + "109.3, 109.3, 109.3, 113.3, 121.2", \ + "126.2, 126.2, 126.2, 130.4, 138.1", \ + "152.8, 152.8, 152.8, 157.1, 165.0", \ + "198.9, 198.9, 198.9, 203.4, 211.8"); + } + fall_transition (inslew_load_5x5__35) { + values ("35.3, 35.3, 35.3, 38.1, 43.2", \ + "39.8, 39.8, 39.8, 42.6, 47.8", \ + "48.2, 48.2, 48.2, 50.9, 56.3", \ + "64.0, 64.0, 64.0, 66.6, 71.9", \ + "94.5, 94.5, 94.5, 97.2, 102.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("164.6, 164.6, 164.6, 168.9, 176.9", \ + "188.4, 188.4, 188.4, 192.8, 201.1", \ + "229.4, 229.4, 229.4, 233.8, 242.4", \ + "305.8, 305.8, 305.8, 310.2, 319.0", \ + "454.7, 454.7, 454.7, 459.2, 468.0"); + } + rise_transition (inslew_load_5x5__35) { + values ("62.3, 62.3, 62.3, 67.7, 78.4", \ + "74.9, 74.9, 74.9, 80.3, 91.0", \ + "98.0, 98.0, 98.0, 103.3, 114.0", \ + "142.3, 142.3, 142.3, 147.9, 158.5", \ + "230.2, 230.2, 230.2, 235.7, 246.9"); + } + cell_fall (inslew_load_5x5__35) { + values ("87.2, 87.2, 87.2, 91.3, 99.1", \ + "86.4, 86.4, 86.4, 90.4, 98.3", \ + "78.8, 78.8, 78.8, 82.9, 90.7", \ + "56.3, 56.3, 56.3, 60.5, 68.1", \ + "2.5, 2.5, 2.5, 6.9, 14.9"); + } + fall_transition (inslew_load_5x5__35) { + values ("34.2, 34.2, 34.2, 37.0, 42.1", \ + "36.9, 36.9, 36.9, 39.7, 44.8", \ + "41.9, 41.9, 41.9, 44.6, 49.8", \ + "51.1, 51.1, 51.1, 53.7, 59.2", \ + "68.6, 68.6, 68.6, 71.3, 76.6"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("148.8, 148.8, 148.8, 153.1, 161.1", \ + "165.2, 165.2, 165.2, 169.5, 177.7", \ + "191.7, 191.7, 191.7, 196.1, 204.5", \ + "240.6, 240.6, 240.6, 245.1, 253.8", \ + "333.9, 333.9, 333.9, 338.4, 347.1"); + } + rise_transition (inslew_load_5x5__35) { + values ("57.1, 57.1, 57.1, 62.5, 73.1", \ + "67.3, 67.3, 67.3, 72.7, 83.4", \ + "86.1, 86.1, 86.1, 91.4, 102.2", \ + "122.2, 122.2, 122.2, 127.7, 138.3", \ + "193.5, 193.5, 193.5, 199.0, 210.1"); + } + cell_fall (inslew_load_5x5__35) { + values ("85.5, 85.5, 85.5, 89.7, 97.4", \ + "89.1, 89.1, 89.1, 93.2, 101.1", \ + "89.2, 89.2, 89.2, 93.3, 101.2", \ + "81.9, 81.9, 81.9, 86.1, 93.8", \ + "59.2, 59.2, 59.2, 63.7, 71.7"); + } + fall_transition (inslew_load_5x5__35) { + values ("33.1, 33.1, 33.1, 35.8, 40.9", \ + "36.3, 36.3, 36.3, 39.1, 44.2", \ + "42.2, 42.2, 42.2, 44.9, 50.2", \ + "53.1, 53.1, 53.1, 55.7, 61.1", \ + "73.7, 73.7, 73.7, 76.4, 81.6"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("114.4, 114.4, 114.4, 118.6, 126.5", \ + "135.5, 135.5, 135.5, 139.8, 147.8", \ + "173.8, 173.8, 173.8, 178.1, 186.4", \ + "243.1, 243.1, 243.1, 247.7, 256.3", \ + "373.0, 373.0, 373.0, 377.4, 386.1"); + } + rise_transition (inslew_load_5x5__35) { + values ("45.0, 45.0, 45.0, 50.3, 60.9", \ + "55.5, 55.5, 55.5, 61.0, 71.6", \ + "75.4, 75.4, 75.4, 80.7, 91.5", \ + "113.3, 113.3, 113.3, 118.7, 129.3", \ + "186.3, 186.3, 186.3, 191.9, 202.9"); + } + cell_fall (inslew_load_5x5__35) { + values ("71.1, 71.1, 71.1, 75.4, 83.0", \ + "69.2, 69.2, 69.2, 73.4, 81.1", \ + "59.3, 59.3, 59.3, 63.4, 71.3", \ + "32.5, 32.5, 32.5, 36.7, 44.4", \ + "-28.5, -28.5, -28.5, -24.2, -16.3"); + } + fall_transition (inslew_load_5x5__35) { + values ("30.6, 30.6, 30.6, 33.3, 38.4", \ + "33.1, 33.1, 33.1, 35.9, 41.0", \ + "37.7, 37.7, 37.7, 40.5, 45.6", \ + "46.1, 46.1, 46.1, 48.8, 54.1", \ + "61.9, 61.9, 61.9, 64.5, 69.9"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("129.7, 129.7, 129.7, 133.9, 141.9", \ + "157.6, 157.6, 157.6, 161.9, 170.0", \ + "207.9, 207.9, 207.9, 212.3, 220.7", \ + "301.4, 301.4, 301.4, 305.9, 314.6", \ + "479.6, 479.6, 479.6, 484.1, 492.8"); + } + rise_transition (inslew_load_5x5__35) { + values ("49.9, 49.9, 49.9, 55.4, 65.9", \ + "62.3, 62.3, 62.3, 67.8, 78.4", \ + "86.0, 86.0, 86.0, 91.3, 102.1", \ + "130.3, 130.3, 130.3, 135.9, 146.5", \ + "217.1, 217.1, 217.1, 222.6, 233.7"); + } + cell_fall (inslew_load_5x5__35) { + values ("74.6, 74.6, 74.6, 78.9, 86.5", \ + "69.5, 69.5, 69.5, 73.6, 81.4", \ + "53.6, 53.6, 53.6, 57.7, 65.6", \ + "14.3, 14.3, 14.3, 18.4, 26.2", \ + "-72.4, -72.4, -72.4, -68.1, -60.3"); + } + fall_transition (inslew_load_5x5__35) { + values ("31.8, 31.8, 31.8, 34.5, 39.6", \ + "34.0, 34.0, 34.0, 36.7, 41.8", \ + "37.8, 37.8, 37.8, 40.6, 45.7", \ + "44.9, 44.9, 44.9, 47.6, 52.9", \ + "58.1, 58.1, 58.1, 60.7, 66.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__35) { + values ("1242.8, 1242.8, 1242.8, 1294.1, 1396.7", \ + "1462.7, 1462.7, 1462.7, 1514.0, 1616.7", \ + "1886.9, 1886.9, 1886.9, 1938.2, 2040.9", \ + "2726.9, 2726.9, 2726.9, 2778.2, 2880.9", \ + "4406.2, 4406.2, 4406.2, 4457.5, 4560.1"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("885.6, 885.6, 885.6, 936.9, 1039.6", \ + "1007.4, 1007.4, 1007.4, 1058.8, 1161.4", \ + "1246.6, 1246.6, 1246.6, 1297.9, 1400.5", \ + "1718.8, 1718.8, 1718.8, 1770.1, 1872.7", \ + "2656.6, 2656.6, 2656.6, 2707.9, 2810.6"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__35) { + values ("1128.3, 1128.3, 1128.3, 1179.7, 1282.3", \ + "1293.0, 1293.0, 1293.0, 1344.3, 1447.0", \ + "1610.0, 1610.0, 1610.0, 1661.3, 1764.0", \ + "2237.6, 2237.6, 2237.6, 2288.9, 2391.6", \ + "3494.4, 3494.4, 3494.4, 3545.7, 3648.4"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("829.7, 829.7, 829.7, 881.1, 983.7", \ + "965.0, 965.0, 965.0, 1016.3, 1119.0", \ + "1227.7, 1227.7, 1227.7, 1279.0, 1381.7", \ + "1744.2, 1744.2, 1744.2, 1795.6, 1898.2", \ + "2769.6, 2769.6, 2769.6, 2820.9, 2923.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__35) { + values ("1056.3, 1056.3, 1056.3, 1107.6, 1210.3", \ + "1277.3, 1277.3, 1277.3, 1328.7, 1431.3", \ + "1699.1, 1699.1, 1699.1, 1750.5, 1853.1", \ + "2532.7, 2532.7, 2532.7, 2584.0, 2686.7", \ + "4195.5, 4195.5, 4195.5, 4246.8, 4349.5"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("782.6, 782.6, 782.6, 833.9, 936.6", \ + "854.4, 854.4, 854.4, 905.7, 1008.3", \ + "992.8, 992.8, 992.8, 1044.1, 1146.8", \ + "1263.1, 1263.1, 1263.1, 1314.4, 1417.1", \ + "1795.2, 1795.2, 1795.2, 1846.5, 1949.2"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__35) { + values ("954.1, 954.1, 954.1, 1005.4, 1108.1", \ + "1130.0, 1130.0, 1130.0, 1181.3, 1284.0", \ + "1467.0, 1467.0, 1467.0, 1518.3, 1621.0", \ + "2132.8, 2132.8, 2132.8, 2184.1, 2286.8", \ + "3460.9, 3460.9, 3460.9, 3512.2, 3614.9"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("727.1, 727.1, 727.1, 778.5, 881.1", \ + "810.4, 810.4, 810.4, 861.7, 964.4", \ + "969.2, 969.2, 969.2, 1020.5, 1123.2", \ + "1278.3, 1278.3, 1278.3, 1329.6, 1432.3", \ + "1887.8, 1887.8, 1887.8, 1939.1, 2041.8"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__35) { + values ("737.6, 737.6, 737.6, 788.9, 891.5", \ + "911.6, 911.6, 911.6, 962.9, 1065.5", \ + "1251.4, 1251.4, 1251.4, 1302.7, 1405.4", \ + "1920.4, 1920.4, 1920.4, 1971.7, 2074.4", \ + "3240.0, 3240.0, 3240.0, 3291.3, 3394.0"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("623.0, 623.0, 623.0, 674.3, 776.9", \ + "681.7, 681.7, 681.7, 733.0, 835.6", \ + "793.1, 793.1, 793.1, 844.5, 947.1", \ + "1007.2, 1007.2, 1007.2, 1058.5, 1161.2", \ + "1428.3, 1428.3, 1428.3, 1479.6, 1582.3"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__35) { + values ("831.9, 831.9, 831.9, 883.2, 985.9", \ + "1041.8, 1041.8, 1041.8, 1093.1, 1195.8", \ + "1453.7, 1453.7, 1453.7, 1505.0, 1607.6", \ + "2255.6, 2255.6, 2255.6, 2306.9, 2409.6", \ + "3847.8, 3847.8, 3847.8, 3899.1, 4001.8"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("680.4, 680.4, 680.4, 731.7, 834.4", \ + "730.9, 730.9, 730.9, 782.2, 884.9", \ + "826.1, 826.1, 826.1, 877.5, 980.1", \ + "1009.1, 1009.1, 1009.1, 1060.4, 1163.1", \ + "1367.4, 1367.4, 1367.4, 1418.8, 1521.4"); + } + } + } + } + + cell (noa2a2a2a24_x1) { + area : 0.0 ; + cell_leakage_power : 22 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5) & (i6 ^ i7))" ; + value : 28 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & (i4 ^ i5) & (i6 ^ i7))))))" ; + value : 22 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 20 ; + } + leakage_power () { + when : "(i7 & !(i6) & i5 & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 0.00038 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5 & !(i6) & i7))" ; + value : 0.00036 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5 & (i6 ^ i7))" ; + value : 42 ; + } + leakage_power () { + when : "(!(i7) & i6 & !(i5) & i4 & i3 & !(i2) & i1 & !(i0))" ; + value : 0.0003 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & !(i5) & i6 & !(i7)) | (!(i0) & i1 & ((i2 & !(i3) & i4 & !(i5) & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))" ; + value : 0.00032 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & !(i5) & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))) | (!(i0) & i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))))" ; + value : 0.00034 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & !(i4) & !(i5) & i6 & i7)" ; + value : 36 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i0) & i1 & !(i2) & !(i3) & !(i4) & !(i5) & i6 & i7))" ; + value : 47 ; + } + leakage_power () { + when : "(i2 & i3 & i4 & i5 & i6 & i7)" ; + value : 71 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i2) & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i1) & ((i2 & i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & !(i3) & i4 & i5 & (i6 ^ i7)))))) | (!(i0) & ((i1 & ((i2 & i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & !(i3) & i4 & i5 & (i6 ^ i7)))) | (i2 & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 35 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))) | (!(i1) & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & !(i3) & i4 & i5 & !(i6) & !(i7)))))) | (!(i0) & ((i1 & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & !(i3) & i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))" ; + value : 23 ; + } + leakage_power () { + when : "((i0 & i1 & (((i2 | i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!((i2 | i3)) & ((i4 | i5) ^ (i6 | i7))))) | (i2 & i3 & !(i4) & !(i5) & !(i6) & !(i7)))" ; + value : 21 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7))) | (!(i0) & !(i1) & i2 & !(i3) & !(i4) & i5 & !(i6) & i7))" ; + value : 0.00029 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7)))) | (!(i1) & !(i2) & i3 & i4 & !(i5) & i6 & !(i7))))" ; + value : 0.00023 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i1) & (i2 ^ i3) & (i4 ^ i5) & i6 & i7))))" ; + value : 60 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7)))) | (!(i0) & ((i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))) | (!(i1) & ((i2 & !(i3) & i4 & !(i5) & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))))" ; + value : 0.00025 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))))))" ; + value : 0.00027 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3) & !(i4) & !(i5) & i6 & i7)" ; + value : 49 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & (i4 | i5) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (!(i0) & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & (i4 | i5) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (!(i1) & ((i2 & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))" ; + value : 48 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & !(i3) & i4 & i5 & i6 & i7))) | (!(i1) & ((i2 & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i3 & i4 & i5 & !(i6) & !(i7)))))) | (!(i0) & ((!(i1) & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i2 & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i3 & i4 & i5 & !(i6) & !(i7)))))" ; + value : 24 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i1) & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7))))))" ; + value : 0.00016 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((!(i2) & ((!(i3) & (i4 | i5) & i6 & i7) | (i4 & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7)))" ; + value : 72 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))))))" ; + value : 0.00017 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7))))" ; + value : 0.00019 ; + } + leakage_power () { + when : "(i7 & i6 & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 73 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7))))))))" ; + value : 8.1e-05 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))))" ; + value : 9.9e-05 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 6.5e-06 ; + } + pin (i7) { + direction : input ; + capacitance : 6.65 ; + } + pin (i6) { + direction : input ; + capacitance : 6.49 ; + } + pin (i5) { + direction : input ; + capacitance : 6.56 ; + } + pin (i4) { + direction : input ; + capacitance : 6.56 ; + } + pin (i3) { + direction : input ; + capacitance : 6.56 ; + } + pin (i2) { + direction : input ; + capacitance : 6.57 ; + } + pin (i1) { + direction : input ; + capacitance : 6.43 ; + } + pin (i0) { + direction : input ; + capacitance : 6.56 ; + } + pin (nq) { + function : "((((((((((((((((((!(i6) & !(i4)) & !(i3)) & !(i1)) | (((!(i6) & !(i4)) & !(i3)) & !(i0))) | (((!(i6) & !(i4)) & !(i2)) & !(i1))) | (((!(i6) & !(i4)) & !(i2)) & !(i0))) | (((!(i6) & !(i5)) & !(i3)) & !(i1))) | (((!(i6) & !(i5)) & !(i3)) & !(i0))) | (((!(i6) & !(i5)) & !(i2)) & !(i1))) | (((!(i6) & !(i5)) & !(i2)) & !(i0))) | (((!(i7) & !(i4)) & !(i3)) & !(i1))) | (((!(i7) & !(i4)) & !(i3)) & !(i0))) | (((!(i7) & !(i4)) & !(i2)) & !(i1))) | (((!(i7) & !(i4)) & !(i2)) & !(i0))) | (((!(i7) & !(i5)) & !(i3)) & !(i1))) | (((!(i7) & !(i5)) & !(i3)) & !(i0))) | (((!(i7) & !(i5)) & !(i2)) & !(i1))) | (((!(i7) & !(i5)) & !(i2)) & !(i0)))" ; + direction : output ; + capacitance : 6.08 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("182.8, 182.8, 182.8, 214.0, 276.5", \ + "201.8, 201.8, 201.8, 233.2, 295.8", \ + "235.5, 235.5, 235.5, 267.1, 330.1", \ + "302.1, 302.1, 302.1, 333.7, 396.8", \ + "436.5, 436.5, 436.5, 468.0, 531.0"); + } + rise_transition (inslew_load_5x5__36) { + values ("342.6, 342.6, 342.6, 399.1, 512.4", \ + "417.8, 417.8, 417.8, 474.0, 586.7", \ + "560.2, 560.2, 560.2, 616.4, 728.9", \ + "838.8, 838.8, 838.8, 895.3, 1008.2", \ + "1393.1, 1393.1, 1393.1, 1449.6, 1562.5"); + } + cell_fall (inslew_load_5x5__36) { + values ("36.3, 36.3, 36.3, 45.8, 64.3", \ + "39.3, 39.3, 39.3, 49.7, 69.7", \ + "41.8, 41.8, 41.8, 53.4, 75.5", \ + "43.7, 43.7, 43.7, 56.4, 80.8", \ + "45.0, 45.0, 45.0, 58.6, 84.9"); + } + fall_transition (inslew_load_5x5__36) { + values ("51.6, 51.6, 51.6, 63.7, 87.9", \ + "70.2, 70.2, 70.2, 82.3, 106.2", \ + "106.3, 106.3, 106.3, 118.6, 142.7", \ + "177.5, 177.5, 177.5, 190.0, 214.7", \ + "319.3, 319.3, 319.3, 331.9, 357.0"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("162.3, 162.3, 162.3, 193.5, 256.0", \ + "170.4, 170.4, 170.4, 201.9, 264.6", \ + "183.1, 183.1, 183.1, 214.8, 278.1", \ + "208.6, 208.6, 208.6, 240.4, 303.8", \ + "261.8, 261.8, 261.8, 293.4, 356.6"); + } + rise_transition (inslew_load_5x5__36) { + values ("305.7, 305.7, 305.7, 362.2, 475.4", \ + "362.0, 362.0, 362.0, 418.0, 530.5", \ + "467.5, 467.5, 467.5, 523.7, 636.1", \ + "672.7, 672.7, 672.7, 729.2, 842.1", \ + "1081.4, 1081.4, 1081.4, 1137.7, 1250.5"); + } + cell_fall (inslew_load_5x5__36) { + values ("36.2, 36.2, 36.2, 46.5, 66.0", \ + "44.0, 44.0, 44.0, 55.7, 77.4", \ + "55.6, 55.6, 55.6, 68.7, 93.2", \ + "75.5, 75.5, 75.5, 89.7, 116.9", \ + "113.1, 113.1, 113.1, 128.2, 157.3"); + } + fall_transition (inslew_load_5x5__36) { + values ("45.9, 45.9, 45.9, 58.2, 82.6", \ + "67.6, 67.6, 67.6, 80.1, 104.5", \ + "108.9, 108.9, 108.9, 121.7, 146.7", \ + "189.9, 189.9, 189.9, 203.0, 228.7", \ + "350.9, 350.9, 350.9, 364.2, 390.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("152.2, 152.2, 152.2, 183.6, 246.4", \ + "178.7, 178.7, 178.7, 210.3, 273.3", \ + "222.8, 222.8, 222.8, 254.6, 318.0", \ + "308.1, 308.1, 308.1, 339.9, 403.5", \ + "478.2, 478.2, 478.2, 510.0, 573.5"); + } + rise_transition (inslew_load_5x5__36) { + values ("280.2, 280.2, 280.2, 337.3, 451.9", \ + "359.1, 359.1, 359.1, 416.0, 530.0", \ + "501.1, 501.1, 501.1, 557.9, 671.7", \ + "776.9, 776.9, 776.9, 833.6, 947.1", \ + "1326.6, 1326.6, 1326.6, 1382.9, 1495.7"); + } + cell_fall (inslew_load_5x5__36) { + values ("32.6, 32.6, 32.6, 42.2, 60.9", \ + "29.7, 29.7, 29.7, 40.6, 61.2", \ + "19.1, 19.1, 19.1, 31.8, 55.6", \ + "-7.4, -7.4, -7.4, 7.2, 34.8", \ + "-65.4, -65.4, -65.4, -48.9, -17.7"); + } + fall_transition (inslew_load_5x5__36) { + values ("47.1, 47.1, 47.1, 59.3, 83.5", \ + "59.8, 59.8, 59.8, 72.0, 96.0", \ + "83.8, 83.8, 83.8, 96.5, 121.1", \ + "130.5, 130.5, 130.5, 143.7, 169.3", \ + "222.2, 222.2, 222.2, 235.9, 262.7"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("134.7, 134.7, 134.7, 166.1, 229.0", \ + "151.6, 151.6, 151.6, 183.3, 246.5", \ + "178.4, 178.4, 178.4, 210.4, 274.1", \ + "230.2, 230.2, 230.2, 262.3, 326.2", \ + "333.8, 333.8, 333.8, 366.0, 430.0"); + } + rise_transition (inslew_load_5x5__36) { + values ("248.5, 248.5, 248.5, 305.6, 420.1", \ + "310.9, 310.9, 310.9, 367.6, 481.4", \ + "422.5, 422.5, 422.5, 479.2, 592.8", \ + "640.3, 640.3, 640.3, 696.5, 809.2", \ + "1074.6, 1074.6, 1074.6, 1130.3, 1242.1"); + } + cell_fall (inslew_load_5x5__36) { + values ("32.6, 32.6, 32.6, 43.2, 62.9", \ + "33.6, 33.6, 33.6, 46.0, 68.6", \ + "30.2, 30.2, 30.2, 44.8, 71.5", \ + "18.3, 18.3, 18.3, 35.0, 66.0", \ + "-9.5, -9.5, -9.5, 8.7, 43.6"); + } + fall_transition (inslew_load_5x5__36) { + values ("42.0, 42.0, 42.0, 54.2, 78.7", \ + "57.2, 57.2, 57.2, 69.9, 94.5", \ + "85.5, 85.5, 85.5, 98.9, 124.6", \ + "140.4, 140.4, 140.4, 154.4, 181.4", \ + "248.5, 248.5, 248.5, 263.0, 291.3"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("96.9, 96.9, 96.9, 128.8, 192.0", \ + "117.7, 117.7, 117.7, 150.0, 213.8", \ + "153.0, 153.0, 153.0, 185.6, 250.2", \ + "221.8, 221.8, 221.8, 255.0, 321.1", \ + "356.3, 356.3, 356.3, 389.9, 456.5"); + } + rise_transition (inslew_load_5x5__36) { + values ("178.5, 178.5, 178.5, 235.9, 351.7", \ + "241.0, 241.0, 241.0, 298.1, 413.2", \ + "352.5, 352.5, 352.5, 409.1, 522.9", \ + "574.8, 574.8, 574.8, 630.6, 743.0", \ + "1015.2, 1015.2, 1015.2, 1070.5, 1181.5"); + } + cell_fall (inslew_load_5x5__36) { + values ("24.1, 24.1, 24.1, 35.6, 56.0", \ + "20.4, 20.4, 20.4, 34.3, 58.4", \ + "7.7, 7.7, 7.7, 24.5, 53.7", \ + "-22.6, -22.6, -22.6, -3.0, 32.0", \ + "-87.5, -87.5, -87.5, -65.6, -25.1"); + } + fall_transition (inslew_load_5x5__36) { + values ("33.3, 33.3, 33.3, 45.7, 70.0", \ + "45.2, 45.2, 45.2, 58.3, 83.2", \ + "66.9, 66.9, 66.9, 81.0, 107.5", \ + "108.5, 108.5, 108.5, 123.5, 152.1", \ + "190.1, 190.1, 190.1, 205.9, 236.4"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("113.1, 113.1, 113.1, 144.8, 208.0", \ + "142.1, 142.1, 142.1, 174.1, 237.7", \ + "192.1, 192.1, 192.1, 224.4, 288.5", \ + "289.9, 289.9, 289.9, 323.1, 387.7", \ + "482.0, 482.0, 482.0, 514.9, 580.2"); + } + rise_transition (inslew_load_5x5__36) { + values ("207.5, 207.5, 207.5, 265.1, 381.1", \ + "283.9, 283.9, 283.9, 341.3, 456.6", \ + "420.3, 420.3, 420.3, 477.2, 591.7", \ + "690.1, 690.1, 690.1, 746.4, 859.7", \ + "1224.6, 1224.6, 1224.6, 1280.4, 1392.4"); + } + cell_fall (inslew_load_5x5__36) { + values ("24.9, 24.9, 24.9, 35.1, 54.2", \ + "18.3, 18.3, 18.3, 30.2, 51.7", \ + "0.1, 0.1, 0.1, 14.3, 39.9", \ + "-42.3, -42.3, -42.3, -25.3, 5.3", \ + "-132.8, -132.8, -132.8, -113.4, -77.4"); + } + fall_transition (inslew_load_5x5__36) { + values ("38.5, 38.5, 38.5, 50.6, 74.8", \ + "48.4, 48.4, 48.4, 60.8, 84.9", \ + "66.7, 66.7, 66.7, 79.8, 104.9", \ + "101.5, 101.5, 101.5, 115.5, 142.2", \ + "169.2, 169.2, 169.2, 184.0, 212.5"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("49.3, 49.3, 49.3, 82.1, 146.4", \ + "74.9, 74.9, 74.9, 108.8, 173.9", \ + "112.6, 112.6, 112.6, 147.1, 214.4", \ + "193.9, 193.9, 193.9, 229.2, 298.2", \ + "354.5, 354.5, 354.5, 390.3, 460.8"); + } + rise_transition (inslew_load_5x5__36) { + values ("94.4, 94.4, 94.4, 151.0, 267.9", \ + "162.3, 162.3, 162.3, 219.7, 335.6", \ + "269.8, 269.8, 269.8, 326.3, 441.3", \ + "491.4, 491.4, 491.4, 548.0, 663.5", \ + "934.0, 934.0, 934.0, 990.5, 1103.7"); + } + cell_fall (inslew_load_5x5__36) { + values ("12.1, 12.1, 12.1, 25.5, 47.4", \ + "3.7, 3.7, 3.7, 20.3, 46.8", \ + "-16.6, -16.6, -16.6, 3.6, 36.4", \ + "-60.5, -60.5, -60.5, -36.9, 3.0", \ + "-150.8, -150.8, -150.8, -124.5, -77.7"); + } + fall_transition (inslew_load_5x5__36) { + values ("22.1, 22.1, 22.1, 35.1, 59.6", \ + "31.5, 31.5, 31.5, 45.5, 71.1", \ + "48.7, 48.7, 48.7, 63.9, 91.6", \ + "81.7, 81.7, 81.7, 98.2, 128.5", \ + "146.9, 146.9, 146.9, 164.3, 197.1"); + } + } + timing (maxd_nq_i7_negative_unate) { + related_pin : "i7" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("64.9, 64.9, 64.9, 97.4, 161.5", \ + "98.2, 98.2, 98.2, 131.2, 195.8", \ + "149.1, 149.1, 149.1, 182.9, 249.3", \ + "256.4, 256.4, 256.4, 290.8, 358.1", \ + "468.4, 468.4, 468.4, 503.0, 571.3"); + } + rise_transition (inslew_load_5x5__36) { + values ("120.9, 120.9, 120.9, 178.5, 295.7", \ + "201.3, 201.3, 201.3, 259.0, 375.4", \ + "329.5, 329.5, 329.5, 386.9, 502.4", \ + "594.6, 594.6, 594.6, 651.2, 764.7", \ + "1116.2, 1116.2, 1116.2, 1172.7, 1289.6"); + } + cell_fall (inslew_load_5x5__36) { + values ("14.8, 14.8, 14.8, 26.0, 45.9", \ + "4.7, 4.7, 4.7, 18.2, 41.3", \ + "-19.7, -19.7, -19.7, -3.1, 24.9", \ + "-73.6, -73.6, -73.6, -53.6, -19.1", \ + "-186.1, -186.1, -186.1, -163.0, -121.7"); + } + fall_transition (inslew_load_5x5__36) { + values ("28.0, 28.0, 28.0, 40.2, 64.3", \ + "35.9, 35.9, 35.9, 48.8, 73.2", \ + "50.5, 50.5, 50.5, 64.3, 90.2", \ + "77.9, 77.9, 77.9, 92.9, 121.0", \ + "131.1, 131.1, 131.1, 147.2, 177.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__36) { + values ("458.0, 458.0, 458.0, 534.0, 686.0", \ + "550.6, 550.6, 550.6, 626.5, 778.5", \ + "735.6, 735.6, 735.6, 811.6, 963.5", \ + "1105.6, 1105.6, 1105.6, 1181.6, 1333.6", \ + "1845.8, 1845.8, 1845.8, 1921.8, 2073.7"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("290.9, 290.9, 290.9, 366.9, 518.9", \ + "365.5, 365.5, 365.5, 441.5, 593.5", \ + "514.8, 514.8, 514.8, 590.7, 742.7", \ + "813.2, 813.2, 813.2, 889.2, 1041.1", \ + "1410.1, 1410.1, 1410.1, 1486.1, 1638.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__36) { + values ("405.3, 405.3, 405.3, 481.3, 633.3", \ + "473.4, 473.4, 473.4, 549.3, 701.3", \ + "609.4, 609.4, 609.4, 685.4, 837.4", \ + "881.6, 881.6, 881.6, 957.5, 1109.5", \ + "1425.8, 1425.8, 1425.8, 1501.8, 1653.8"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("251.8, 251.8, 251.8, 327.8, 479.8", \ + "330.7, 330.7, 330.7, 406.7, 558.6", \ + "488.4, 488.4, 488.4, 564.3, 716.3", \ + "803.7, 803.7, 803.7, 879.7, 1031.7", \ + "1434.5, 1434.5, 1434.5, 1510.5, 1662.4"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__36) { + values ("383.8, 383.8, 383.8, 459.8, 611.7", \ + "473.2, 473.2, 473.2, 549.2, 701.1", \ + "652.0, 652.0, 652.0, 728.0, 879.9", \ + "1009.6, 1009.6, 1009.6, 1085.5, 1237.5", \ + "1724.7, 1724.7, 1724.7, 1800.7, 1952.6"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("255.2, 255.2, 255.2, 331.2, 483.2", \ + "294.6, 294.6, 294.6, 370.5, 522.5", \ + "373.2, 373.2, 373.2, 449.2, 601.2", \ + "530.6, 530.6, 530.6, 606.6, 758.5", \ + "845.3, 845.3, 845.3, 921.3, 1073.3"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__36) { + values ("335.9, 335.9, 335.9, 411.9, 563.9", \ + "405.6, 405.6, 405.6, 481.6, 633.6", \ + "545.1, 545.1, 545.1, 621.1, 773.0", \ + "824.0, 824.0, 824.0, 900.0, 1051.9", \ + "1381.8, 1381.8, 1381.8, 1457.8, 1609.8"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("216.1, 216.1, 216.1, 292.1, 444.1", \ + "259.7, 259.7, 259.7, 335.7, 487.6", \ + "346.8, 346.8, 346.8, 422.8, 574.7", \ + "521.0, 521.0, 521.0, 597.0, 748.9", \ + "869.4, 869.4, 869.4, 945.4, 1097.4"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__36) { + values ("245.6, 245.6, 245.6, 321.5, 473.5", \ + "312.7, 312.7, 312.7, 388.7, 540.7", \ + "447.0, 447.0, 447.0, 523.0, 675.0", \ + "715.7, 715.7, 715.7, 791.7, 943.6", \ + "1253.0, 1253.0, 1253.0, 1329.0, 1481.0"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("157.8, 157.8, 157.8, 233.8, 385.8", \ + "185.8, 185.8, 185.8, 261.7, 413.7", \ + "241.6, 241.6, 241.6, 317.6, 469.5", \ + "353.3, 353.3, 353.3, 429.3, 581.3", \ + "576.7, 576.7, 576.7, 652.7, 804.7"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__36) { + values ("290.0, 290.0, 290.0, 366.0, 517.9", \ + "373.4, 373.4, 373.4, 449.3, 601.3", \ + "540.1, 540.1, 540.1, 616.1, 768.0", \ + "873.6, 873.6, 873.6, 949.6, 1101.5", \ + "1540.6, 1540.6, 1540.6, 1616.6, 1768.5"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("197.5, 197.5, 197.5, 273.5, 425.5", \ + "221.8, 221.8, 221.8, 297.8, 449.8", \ + "270.4, 270.4, 270.4, 346.4, 498.4", \ + "367.7, 367.7, 367.7, 443.6, 595.6", \ + "562.1, 562.1, 562.1, 638.1, 790.0"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__36) { + values ("145.6, 145.6, 145.6, 221.6, 373.6", \ + "209.3, 209.3, 209.3, 285.3, 437.3", \ + "336.8, 336.8, 336.8, 412.8, 564.7", \ + "591.7, 591.7, 591.7, 667.7, 819.7", \ + "1101.6, 1101.6, 1101.6, 1177.5, 1329.5"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("89.5, 89.5, 89.5, 165.5, 317.4", \ + "108.9, 108.9, 108.9, 184.9, 336.9", \ + "147.8, 147.8, 147.8, 223.8, 375.7", \ + "225.5, 225.5, 225.5, 301.5, 453.4", \ + "380.9, 380.9, 380.9, 456.9, 608.8"); + } + } + internal_power (energy_neg_nq_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__36) { + values ("187.4, 187.4, 187.4, 263.4, 415.4", \ + "264.8, 264.8, 264.8, 340.7, 492.7", \ + "419.4, 419.4, 419.4, 495.4, 647.3", \ + "728.7, 728.7, 728.7, 804.7, 956.6", \ + "1347.2, 1347.2, 1347.2, 1423.2, 1575.2"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("129.8, 129.8, 129.8, 205.8, 357.8", \ + "146.3, 146.3, 146.3, 222.2, 374.2", \ + "179.1, 179.1, 179.1, 255.1, 407.1", \ + "244.9, 244.9, 244.9, 320.9, 472.8", \ + "376.4, 376.4, 376.4, 452.4, 604.3"); + } + } + } + } + + cell (noa2a2a2a24_x4) { + area : 0.0 ; + cell_leakage_power : 46 ; + leakage_power () { + when : "(i0 & i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & i4 & i5 & (i6 ^ i7)))) | (!(i2) & i3 & i4 & i5 & (i6 ^ i7))))" ; + value : 40 ; + } + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5) & (i6 ^ i7))" ; + value : 34 ; + } + leakage_power () { + when : "(i0 & i1 & ((!(i2) & ((!(i3) & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!(i4) & !(i5) & !(i6) & !(i7)))) | (!(i3) & !(i4) & !(i5) & !(i6) & !(i7))))" ; + value : 26 ; + } + leakage_power () { + when : "((i0 | i1) & i2 & i3 & i4 & i5 & i6 & i7)" ; + value : 76 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5 & i6 & i7)" ; + value : 65 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5 & (i6 ^ i7))" ; + value : 47 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5 & !(i6) & !(i7))" ; + value : 29 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6 & i7)" ; + value : 52 ; + } + leakage_power () { + when : "((i0 & ((i1 & (i2 ^ i3) & (i4 ^ i5) & i6 & i7) | (!(i1) & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))) | (i2 & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 41 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))) | (!(i1) & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & !(i3) & i4 & i5 & !(i6) & !(i7)))))) | (!(i0) & ((i1 & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & !(i3) & i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))" ; + value : 28 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))) | (!(i4) & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))))))))) | (i2 & i3 & !(i4) & !(i5) & !(i6) & !(i7)))" ; + value : 27 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & (i4 | i5) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & (i4 | i5) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (!(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))) | (i3 & i4 & i5 & (i6 ^ i7)))))))" ; + value : 53 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3) & (i4 ^ i5) & i6 & i7)" ; + value : 66 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & i4 & i5 & i6 & i7)" ; + value : 77 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & i6 & i7) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7))))))" ; + value : 54 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & !(i3) & i4 & i5 & i6 & i7))) | (i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i0) & ((!(i1) & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))))" ; + value : 30 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & !(i3) & !((i4 & i5)) & i6 & i7)" ; + value : 78 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !((i2 & i3)) & !((i4 & i5)) & (!(i6) | !(i7)))" ; + value : 1 ; + } + pin (i7) { + direction : input ; + capacitance : 6.65 ; + } + pin (i6) { + direction : input ; + capacitance : 6.52 ; + } + pin (i5) { + direction : input ; + capacitance : 6.52 ; + } + pin (i4) { + direction : input ; + capacitance : 6.52 ; + } + pin (i3) { + direction : input ; + capacitance : 6.53 ; + } + pin (i2) { + direction : input ; + capacitance : 6.52 ; + } + pin (i1) { + direction : input ; + capacitance : 6.54 ; + } + pin (i0) { + direction : input ; + capacitance : 6.52 ; + } + pin (nq) { + function : "((!(i7) & ((!(i5) & ((!(i3) & (!(i1) | !(i0))) | (!((i1 & i0)) & !(i2)))) | (!(i3) & !((i1 & i0)) & !(i4)) | (!((i1 & i0)) & !(i2) & !(i4)))) | (!(i5) & ((!(i3) & !((i1 & i0)) & !(i6)) | (!((i1 & i0)) & !(i2) & !(i6)))) | (!(i3) & !((i1 & i0)) & !(i4) & !(i6)) | (!((i1 & i0)) & !(i2) & !(i4) & !(i6)))" ; + direction : output ; + capacitance : 4.47 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("191.7, 191.7, 191.7, 196.4, 205.2", \ + "200.3, 200.3, 200.3, 205.1, 214.1", \ + "213.1, 213.1, 213.1, 217.9, 227.2", \ + "237.1, 237.1, 237.1, 241.9, 251.4", \ + "284.9, 284.9, 284.9, 289.7, 299.2"); + } + rise_transition (inslew_load_5x5__37) { + values ("68.6, 68.6, 68.6, 74.5, 86.1", \ + "78.8, 78.8, 78.8, 84.6, 96.3", \ + "98.0, 98.0, 98.0, 103.7, 115.4", \ + "134.9, 134.9, 134.9, 140.9, 152.4", \ + "207.2, 207.2, 207.2, 213.2, 225.3"); + } + cell_fall (inslew_load_5x5__37) { + values ("112.3, 112.3, 112.3, 116.7, 125.2", \ + "122.8, 122.8, 122.8, 127.3, 135.6", \ + "138.1, 138.1, 138.1, 142.8, 151.2", \ + "162.1, 162.1, 162.1, 167.0, 175.7", \ + "203.7, 203.7, 203.7, 208.6, 218.0"); + } + fall_transition (inslew_load_5x5__37) { + values ("42.3, 42.3, 42.3, 45.3, 51.0", \ + "48.5, 48.5, 48.5, 51.4, 57.2", \ + "59.9, 59.9, 59.9, 62.7, 68.6", \ + "81.6, 81.6, 81.6, 84.5, 90.2", \ + "123.8, 123.8, 123.8, 126.7, 132.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("176.6, 176.6, 176.6, 181.3, 190.0", \ + "177.2, 177.2, 177.2, 181.9, 190.7", \ + "175.2, 175.2, 175.2, 179.9, 189.0", \ + "170.7, 170.7, 170.7, 175.6, 184.9", \ + "161.6, 161.6, 161.6, 166.5, 176.0"); + } + rise_transition (inslew_load_5x5__37) { + values ("63.7, 63.7, 63.7, 69.6, 81.2", \ + "71.3, 71.3, 71.3, 77.1, 88.8", \ + "85.6, 85.6, 85.6, 91.4, 103.1", \ + "113.5, 113.5, 113.5, 119.3, 130.9", \ + "167.3, 167.3, 167.3, 173.4, 185.1"); + } + cell_fall (inslew_load_5x5__37) { + values ("110.2, 110.2, 110.2, 114.6, 123.1", \ + "127.3, 127.3, 127.3, 131.8, 140.2", \ + "153.8, 153.8, 153.8, 158.4, 166.8", \ + "198.8, 198.8, 198.8, 203.7, 212.5", \ + "282.4, 282.4, 282.4, 287.3, 296.8"); + } + fall_transition (inslew_load_5x5__37) { + values ("40.5, 40.5, 40.5, 43.5, 49.1", \ + "47.8, 47.8, 47.8, 50.7, 56.5", \ + "60.9, 60.9, 60.9, 63.7, 69.6", \ + "85.6, 85.6, 85.6, 88.5, 94.2", \ + "133.8, 133.8, 133.8, 136.7, 142.6"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("170.7, 170.7, 170.7, 175.4, 184.1", \ + "186.4, 186.4, 186.4, 191.1, 199.9", \ + "209.6, 209.6, 209.6, 214.4, 223.6", \ + "252.2, 252.2, 252.2, 257.1, 266.5", \ + "334.8, 334.8, 334.8, 339.6, 349.1"); + } + rise_transition (inslew_load_5x5__37) { + values ("60.5, 60.5, 60.5, 66.4, 78.0", \ + "71.1, 71.1, 71.1, 77.0, 88.6", \ + "90.1, 90.1, 90.1, 95.9, 107.6", \ + "126.6, 126.6, 126.6, 132.6, 144.1", \ + "197.6, 197.6, 197.6, 203.6, 215.6"); + } + cell_fall (inslew_load_5x5__37) { + values ("106.6, 106.6, 106.6, 111.0, 119.5", \ + "109.5, 109.5, 109.5, 114.0, 122.4", \ + "108.6, 108.6, 108.6, 113.1, 121.4", \ + "97.6, 97.6, 97.6, 102.3, 110.9", \ + "65.8, 65.8, 65.8, 70.7, 79.7"); + } + fall_transition (inslew_load_5x5__37) { + values ("40.8, 40.8, 40.8, 43.8, 49.4", \ + "45.1, 45.1, 45.1, 48.0, 53.8", \ + "53.0, 53.0, 53.0, 55.8, 61.8", \ + "67.5, 67.5, 67.5, 70.3, 76.1", \ + "95.0, 95.0, 95.0, 98.0, 103.7"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("157.7, 157.7, 157.7, 162.3, 171.0", \ + "166.4, 166.4, 166.4, 171.1, 179.8", \ + "177.6, 177.6, 177.6, 182.4, 191.4", \ + "196.9, 196.9, 196.9, 201.8, 211.1", \ + "233.1, 233.1, 233.1, 237.9, 247.4"); + } + rise_transition (inslew_load_5x5__37) { + values ("56.3, 56.3, 56.3, 62.2, 73.8", \ + "64.7, 64.7, 64.7, 70.6, 82.2", \ + "79.7, 79.7, 79.7, 85.6, 97.2", \ + "108.9, 108.9, 108.9, 114.7, 126.3", \ + "165.5, 165.5, 165.5, 171.6, 183.2"); + } + cell_fall (inslew_load_5x5__37) { + values ("104.8, 104.8, 104.8, 109.2, 117.7", \ + "113.3, 113.3, 113.3, 117.7, 126.2", \ + "121.1, 121.1, 121.1, 125.7, 134.0", \ + "127.3, 127.3, 127.3, 132.0, 140.6", \ + "130.3, 130.3, 130.3, 135.2, 144.4"); + } + fall_transition (inslew_load_5x5__37) { + values ("39.0, 39.0, 39.0, 42.0, 47.6", \ + "44.3, 44.3, 44.3, 47.3, 53.0", \ + "53.7, 53.7, 53.7, 56.5, 62.4", \ + "70.7, 70.7, 70.7, 73.5, 79.3", \ + "103.2, 103.2, 103.2, 106.2, 111.9"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("130.4, 130.4, 130.4, 135.0, 143.5", \ + "143.7, 143.7, 143.7, 148.3, 157.0", \ + "163.6, 163.6, 163.6, 168.4, 177.2", \ + "199.7, 199.7, 199.7, 204.5, 213.7", \ + "265.3, 265.3, 265.3, 270.1, 279.7"); + } + rise_transition (inslew_load_5x5__37) { + values ("47.1, 47.1, 47.1, 53.0, 64.4", \ + "55.7, 55.7, 55.7, 61.6, 73.1", \ + "70.5, 70.5, 70.5, 76.4, 88.0", \ + "100.0, 100.0, 100.0, 105.8, 117.5", \ + "157.1, 157.1, 157.1, 163.2, 174.8"); + } + cell_fall (inslew_load_5x5__37) { + values ("93.7, 93.7, 93.7, 98.1, 106.5", \ + "97.0, 97.0, 97.0, 101.4, 109.9", \ + "94.6, 94.6, 94.6, 99.1, 107.4", \ + "79.4, 79.4, 79.4, 84.1, 92.5", \ + "38.5, 38.5, 38.5, 43.4, 52.3"); + } + fall_transition (inslew_load_5x5__37) { + values ("36.2, 36.2, 36.2, 39.2, 44.7", \ + "40.5, 40.5, 40.5, 43.5, 49.1", \ + "48.1, 48.1, 48.1, 51.0, 56.8", \ + "61.4, 61.4, 61.4, 64.2, 70.1", \ + "86.2, 86.2, 86.2, 89.2, 94.9"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("142.8, 142.8, 142.8, 147.3, 156.0", \ + "161.5, 161.5, 161.5, 166.2, 174.9", \ + "191.5, 191.5, 191.5, 196.3, 205.3", \ + "247.9, 247.9, 247.9, 252.8, 262.2", \ + "352.8, 352.8, 352.8, 357.6, 367.1"); + } + rise_transition (inslew_load_5x5__37) { + values ("51.1, 51.1, 51.1, 57.0, 68.5", \ + "61.4, 61.4, 61.4, 67.3, 78.9", \ + "79.4, 79.4, 79.4, 85.2, 96.9", \ + "114.8, 114.8, 114.8, 120.7, 132.3", \ + "183.0, 183.0, 183.0, 189.1, 200.9"); + } + cell_fall (inslew_load_5x5__37) { + values ("96.2, 96.2, 96.2, 100.6, 109.1", \ + "95.1, 95.1, 95.1, 99.5, 108.0", \ + "85.6, 85.6, 85.6, 90.1, 98.5", \ + "56.7, 56.7, 56.7, 61.3, 69.7", \ + "-12.8, -12.8, -12.8, -7.9, 0.9"); + } + fall_transition (inslew_load_5x5__37) { + values ("38.0, 38.0, 38.0, 41.0, 46.5", \ + "41.5, 41.5, 41.5, 44.5, 50.1", \ + "47.8, 47.8, 47.8, 50.7, 56.5", \ + "59.1, 59.1, 59.1, 61.9, 67.8", \ + "79.9, 79.9, 79.9, 82.8, 88.5"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("95.9, 95.9, 95.9, 100.4, 108.6", \ + "114.4, 114.4, 114.4, 119.0, 127.5", \ + "138.4, 138.4, 138.4, 143.0, 151.8", \ + "187.3, 187.3, 187.3, 192.1, 201.2", \ + "278.0, 278.0, 278.0, 282.8, 292.4"); + } + rise_transition (inslew_load_5x5__37) { + values ("35.3, 35.3, 35.3, 41.2, 52.6", \ + "45.3, 45.3, 45.3, 51.2, 62.6", \ + "60.0, 60.0, 60.0, 65.9, 77.4", \ + "89.2, 89.2, 89.2, 95.0, 106.7", \ + "146.5, 146.5, 146.5, 152.6, 164.1"); + } + cell_fall (inslew_load_5x5__37) { + values ("78.0, 78.0, 78.0, 82.7, 90.8", \ + "77.1, 77.1, 77.1, 81.5, 89.9", \ + "66.9, 66.9, 66.9, 71.3, 79.8", \ + "36.9, 36.9, 36.9, 41.5, 49.8", \ + "-32.7, -32.7, -32.7, -27.9, -19.3"); + } + fall_transition (inslew_load_5x5__37) { + values ("32.3, 32.3, 32.3, 35.2, 40.8", \ + "36.1, 36.1, 36.1, 39.1, 44.7", \ + "42.5, 42.5, 42.5, 45.5, 51.1", \ + "53.6, 53.6, 53.6, 56.4, 62.3", \ + "73.8, 73.8, 73.8, 76.7, 82.4"); + } + } + timing (maxd_nq_i7_negative_unate) { + related_pin : "i7" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("108.2, 108.2, 108.2, 112.8, 121.0", \ + "131.4, 131.4, 131.4, 136.0, 144.6", \ + "164.8, 164.8, 164.8, 169.5, 178.3", \ + "231.1, 231.1, 231.1, 235.9, 245.2", \ + "356.2, 356.2, 356.2, 361.0, 370.5"); + } + rise_transition (inslew_load_5x5__37) { + values ("39.4, 39.4, 39.4, 45.2, 56.6", \ + "50.8, 50.8, 50.8, 56.7, 68.2", \ + "67.7, 67.7, 67.7, 73.6, 85.3", \ + "102.3, 102.3, 102.3, 108.1, 119.7", \ + "169.3, 169.3, 169.3, 175.4, 187.1"); + } + cell_fall (inslew_load_5x5__37) { + values ("82.4, 82.4, 82.4, 86.9, 95.2", \ + "78.2, 78.2, 78.2, 82.6, 91.0", \ + "62.5, 62.5, 62.5, 66.9, 75.4", \ + "20.9, 20.9, 20.9, 25.5, 33.8", \ + "-72.8, -72.8, -72.8, -68.0, -59.5"); + } + fall_transition (inslew_load_5x5__37) { + values ("34.3, 34.3, 34.3, 37.3, 42.8", \ + "37.5, 37.5, 37.5, 40.5, 46.0", \ + "42.8, 42.8, 42.8, 45.8, 51.5", \ + "52.2, 52.2, 52.2, 55.0, 60.9", \ + "69.0, 69.0, 69.0, 71.9, 77.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__37) { + values ("1372.7, 1372.7, 1372.7, 1428.5, 1540.2", \ + "1582.1, 1582.1, 1582.1, 1637.9, 1749.5", \ + "1989.2, 1989.2, 1989.2, 2045.0, 2156.7", \ + "2793.2, 2793.2, 2793.2, 2849.0, 2960.6", \ + "4390.7, 4390.7, 4390.7, 4446.5, 4558.1"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("1012.9, 1012.9, 1012.9, 1068.7, 1180.4", \ + "1166.9, 1166.9, 1166.9, 1222.8, 1334.4", \ + "1467.3, 1467.3, 1467.3, 1523.1, 1634.7", \ + "2058.6, 2058.6, 2058.6, 2114.4, 2226.0", \ + "3229.8, 3229.8, 3229.8, 3285.6, 3397.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__37) { + values ("1263.3, 1263.3, 1263.3, 1319.1, 1430.7", \ + "1419.2, 1419.2, 1419.2, 1475.0, 1586.7", \ + "1722.3, 1722.3, 1722.3, 1778.1, 1889.7", \ + "2320.2, 2320.2, 2320.2, 2376.0, 2487.7", \ + "3506.3, 3506.3, 3506.3, 3562.1, 3673.8"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("946.9, 946.9, 946.9, 1002.7, 1114.4", \ + "1121.2, 1121.2, 1121.2, 1177.0, 1288.6", \ + "1454.6, 1454.6, 1454.6, 1510.4, 1622.0", \ + "2106.4, 2106.4, 2106.4, 2162.2, 2273.9", \ + "3399.1, 3399.1, 3399.1, 3454.9, 3566.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__37) { + values ("1209.3, 1209.3, 1209.3, 1265.1, 1376.8", \ + "1419.4, 1419.4, 1419.4, 1475.2, 1586.9", \ + "1815.9, 1815.9, 1815.9, 1871.7, 1983.4", \ + "2596.7, 2596.7, 2596.7, 2652.5, 2764.1", \ + "4146.7, 4146.7, 4146.7, 4202.5, 4314.2"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("956.3, 956.3, 956.3, 1012.1, 1123.8", \ + "1050.9, 1050.9, 1050.9, 1106.7, 1218.3", \ + "1231.9, 1231.9, 1231.9, 1287.7, 1399.3", \ + "1581.3, 1581.3, 1581.3, 1637.1, 1748.8", \ + "2265.7, 2265.7, 2265.7, 2321.5, 2433.1"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__37) { + values ("1113.0, 1113.0, 1113.0, 1168.8, 1280.4", \ + "1278.7, 1278.7, 1278.7, 1334.5, 1446.2", \ + "1591.0, 1591.0, 1591.0, 1646.8, 1758.4", \ + "2207.0, 2207.0, 2207.0, 2262.8, 2374.5", \ + "3431.8, 3431.8, 3431.8, 3487.6, 3599.3"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("891.8, 891.8, 891.8, 947.6, 1059.3", \ + "1004.3, 1004.3, 1004.3, 1060.1, 1171.7", \ + "1213.4, 1213.4, 1213.4, 1269.2, 1380.8", \ + "1616.0, 1616.0, 1616.0, 1671.8, 1783.4", \ + "2406.0, 2406.0, 2406.0, 2461.8, 2573.4"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__37) { + values ("923.2, 923.2, 923.2, 979.0, 1090.6", \ + "1086.3, 1086.3, 1086.3, 1142.1, 1253.7", \ + "1389.6, 1389.6, 1389.6, 1445.4, 1557.0", \ + "1995.9, 1995.9, 1995.9, 2051.8, 2163.4", \ + "3198.8, 3198.8, 3198.8, 3254.6, 3366.3"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("799.8, 799.8, 799.8, 855.7, 967.3", \ + "883.4, 883.4, 883.4, 939.3, 1050.9", \ + "1036.8, 1036.8, 1036.8, 1092.6, 1204.3", \ + "1324.7, 1324.7, 1324.7, 1380.6, 1492.2", \ + "1882.7, 1882.7, 1882.7, 1938.5, 2050.1"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__37) { + values ("1012.2, 1012.2, 1012.2, 1068.0, 1179.6", \ + "1210.6, 1210.6, 1210.6, 1266.5, 1378.1", \ + "1581.2, 1581.2, 1581.2, 1637.1, 1748.7", \ + "2318.9, 2318.9, 2318.9, 2374.7, 2486.3", \ + "3778.9, 3778.9, 3778.9, 3834.7, 3946.3"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("865.6, 865.6, 865.6, 921.4, 1033.1", \ + "935.3, 935.3, 935.3, 991.1, 1102.7", \ + "1065.3, 1065.3, 1065.3, 1121.2, 1232.8", \ + "1310.9, 1310.9, 1310.9, 1366.7, 1478.3", \ + "1784.4, 1784.4, 1784.4, 1840.2, 1951.8"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__37) { + values ("703.5, 703.5, 703.5, 759.3, 870.9", \ + "872.7, 872.7, 872.7, 928.6, 1040.2", \ + "1162.9, 1162.9, 1162.9, 1218.7, 1330.3", \ + "1749.1, 1749.1, 1749.1, 1804.9, 1916.5", \ + "2918.4, 2918.4, 2918.4, 2974.2, 3085.8"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("684.4, 684.4, 684.4, 740.2, 851.8", \ + "751.6, 751.6, 751.6, 807.4, 919.1", \ + "871.6, 871.6, 871.6, 927.5, 1039.1", \ + "1094.0, 1094.0, 1094.0, 1149.8, 1261.4", \ + "1521.2, 1521.2, 1521.2, 1577.0, 1688.6"); + } + } + internal_power (energy_neg_nq_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__37) { + values ("787.8, 787.8, 787.8, 843.6, 955.2", \ + "987.0, 987.0, 987.0, 1042.8, 1154.5", \ + "1331.3, 1331.3, 1331.3, 1387.1, 1498.7", \ + "2029.8, 2029.8, 2029.8, 2085.6, 2197.2", \ + "3417.5, 3417.5, 3417.5, 3473.4, 3585.0"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("753.1, 753.1, 753.1, 808.9, 920.6", \ + "809.2, 809.2, 809.2, 865.0, 976.6", \ + "911.2, 911.2, 911.2, 967.1, 1078.7", \ + "1098.5, 1098.5, 1098.5, 1154.3, 1265.9", \ + "1456.1, 1456.1, 1456.1, 1511.9, 1623.5"); + } + } + } + } + + cell (noa2ao222_x1) { + area : 0.0 ; + cell_leakage_power : 4.3 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & !(i4))" ; + value : 6.1 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & i0)" ; + value : 11 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 5.7 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & !(i1) & i0)" ; + value : 0.00068 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & i0)" ; + value : 0.0006 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & i1 & !(i0))" ; + value : 0.00064 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & i4)" ; + value : 15 ; + } + leakage_power () { + when : "(!(i0) & i1 & (i2 ^ i3) & !(i4))" ; + value : 0.00042 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & !(i0))" ; + value : 0.00055 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & !(i0))" ; + value : 0.00019 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & !(i4)) | (!(i0) & !(i1) & i2 & i3 & !(i4)))" ; + value : 0.00046 ; + } + leakage_power () { + when : "((!((i0 | i1)) & i2 & i4) | (i2 & i3 & i4))" ; + value : 18 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & (i3 ^ i4)) | (!(i2) & i3 & i4))) | (!(i2) & i3 & i4))" ; + value : 12 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4)) | (!(i0) & !(i1) & (i2 ^ i3) & !(i4)))" ; + value : 0.00024 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.00037 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 1.2e-05 ; + } + pin (i4) { + direction : input ; + capacitance : 7.22 ; + } + pin (i3) { + direction : input ; + capacitance : 7.34 ; + } + pin (i2) { + direction : input ; + capacitance : 7.37 ; + } + pin (i1) { + direction : input ; + capacitance : 7.35 ; + } + pin (i0) { + direction : input ; + capacitance : 7.31 ; + } + pin (nq) { + function : "(((((!(i2) & !(i3)) & !(i1)) | ((!(i2) & !(i3)) & !(i0))) | (!(i4) & !(i1))) | (!(i4) & !(i0)))" ; + direction : output ; + capacitance : 4.69 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("113.0, 113.0, 113.0, 131.1, 167.3", \ + "137.0, 137.0, 137.0, 155.3, 191.7", \ + "179.9, 179.9, 179.9, 198.3, 235.0", \ + "265.1, 265.1, 265.1, 283.4, 320.0", \ + "435.7, 435.7, 435.7, 453.9, 490.4"); + } + rise_transition (inslew_load_5x5__38) { + values ("216.1, 216.1, 216.1, 248.8, 314.5", \ + "296.4, 296.4, 296.4, 329.0, 394.3", \ + "445.0, 445.0, 445.0, 477.8, 543.3", \ + "736.9, 736.9, 736.9, 769.6, 835.2", \ + "1318.4, 1318.4, 1318.4, 1351.1, 1416.4"); + } + cell_fall (inslew_load_5x5__38) { + values ("19.5, 19.5, 19.5, 25.1, 35.6", \ + "16.4, 16.4, 16.4, 22.8, 34.9", \ + "7.2, 7.2, 7.2, 14.7, 28.7", \ + "-13.4, -13.4, -13.4, -5.1, 10.6", \ + "-56.7, -56.7, -56.7, -47.8, -30.5"); + } + fall_transition (inslew_load_5x5__38) { + values ("31.8, 31.8, 31.8, 38.0, 50.3", \ + "44.7, 44.7, 44.7, 51.2, 63.7", \ + "69.8, 69.8, 69.8, 76.5, 89.5", \ + "119.2, 119.2, 119.2, 126.1, 139.6", \ + "217.3, 217.3, 217.3, 224.4, 238.3"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("92.0, 92.0, 92.0, 110.2, 146.5", \ + "106.2, 106.2, 106.2, 124.7, 161.4", \ + "131.2, 131.2, 131.2, 149.7, 186.6", \ + "181.4, 181.4, 181.4, 199.8, 236.6", \ + "282.5, 282.5, 282.5, 300.8, 337.6"); + } + rise_transition (inslew_load_5x5__38) { + values ("178.9, 178.9, 178.9, 211.4, 276.8", \ + "242.3, 242.3, 242.3, 274.8, 340.0", \ + "359.0, 359.0, 359.0, 391.7, 457.1", \ + "588.6, 588.6, 588.6, 621.1, 686.4", \ + "1047.4, 1047.4, 1047.4, 1079.7, 1144.5"); + } + cell_fall (inslew_load_5x5__38) { + values ("18.2, 18.2, 18.2, 25.1, 37.3", \ + "18.5, 18.5, 18.5, 26.4, 40.8", \ + "16.3, 16.3, 16.3, 25.3, 41.9", \ + "10.2, 10.2, 10.2, 20.0, 38.5", \ + "-3.0, -3.0, -3.0, 7.1, 27.0"); + } + fall_transition (inslew_load_5x5__38) { + values ("27.4, 27.4, 27.4, 34.0, 46.7", \ + "43.1, 43.1, 43.1, 50.1, 63.4", \ + "73.2, 73.2, 73.2, 80.5, 94.5", \ + "132.6, 132.6, 132.6, 140.0, 154.7", \ + "250.5, 250.5, 250.5, 258.2, 273.3"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("60.7, 60.7, 60.7, 79.9, 117.2", \ + "95.4, 95.4, 95.4, 114.9, 153.0", \ + "153.4, 153.4, 153.4, 173.2, 211.9", \ + "261.6, 261.6, 261.6, 281.7, 321.3", \ + "473.9, 473.9, 473.9, 494.2, 534.5"); + } + rise_transition (inslew_load_5x5__38) { + values ("106.0, 106.0, 106.0, 139.5, 207.0", \ + "184.9, 184.9, 184.9, 218.0, 284.7", \ + "323.3, 323.3, 323.3, 355.9, 421.6", \ + "584.4, 584.4, 584.4, 617.2, 685.1", \ + "1102.6, 1102.6, 1102.6, 1135.4, 1200.9"); + } + cell_fall (inslew_load_5x5__38) { + values ("10.8, 10.8, 10.8, 17.1, 28.4", \ + "0.2, 0.2, 0.2, 7.9, 21.7", \ + "-25.2, -25.2, -25.2, -15.5, 1.6", \ + "-81.0, -81.0, -81.0, -69.1, -47.9", \ + "-197.0, -197.0, -197.0, -183.2, -157.9"); + } + fall_transition (inslew_load_5x5__38) { + values ("23.2, 23.2, 23.2, 29.6, 42.0", \ + "30.4, 30.4, 30.4, 37.3, 50.2", \ + "43.5, 43.5, 43.5, 51.0, 65.2", \ + "68.2, 68.2, 68.2, 76.4, 92.0", \ + "116.1, 116.1, 116.1, 124.9, 142.0"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("88.6, 88.6, 88.6, 107.0, 143.6", \ + "118.7, 118.7, 118.7, 137.3, 174.2", \ + "170.2, 170.2, 170.2, 188.9, 226.1", \ + "268.6, 268.6, 268.6, 287.5, 325.6", \ + "464.0, 464.0, 464.0, 482.9, 520.6"); + } + rise_transition (inslew_load_5x5__38) { + values ("163.1, 163.1, 163.1, 196.2, 262.8", \ + "242.1, 242.1, 242.1, 275.1, 341.4", \ + "383.9, 383.9, 383.9, 416.6, 482.3", \ + "659.6, 659.6, 659.6, 692.0, 757.1", \ + "1207.6, 1207.6, 1207.6, 1239.8, 1304.4"); + } + cell_fall (inslew_load_5x5__38) { + values ("15.2, 15.2, 15.2, 21.1, 32.0", \ + "7.3, 7.3, 7.3, 14.4, 27.3", \ + "-12.4, -12.4, -12.4, -3.8, 11.8", \ + "-56.3, -56.3, -56.3, -46.1, -27.4", \ + "-147.5, -147.5, -147.5, -136.1, -114.5"); + } + fall_transition (inslew_load_5x5__38) { + values ("27.4, 27.4, 27.4, 33.7, 46.0", \ + "36.4, 36.4, 36.4, 43.0, 55.8", \ + "53.2, 53.2, 53.2, 60.4, 74.0", \ + "85.6, 85.6, 85.6, 93.2, 107.9", \ + "149.2, 149.2, 149.2, 157.2, 172.8"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("30.9, 30.9, 30.9, 44.9, 71.1", \ + "48.5, 48.5, 48.5, 62.8, 90.2", \ + "78.0, 78.0, 78.0, 92.9, 121.5", \ + "134.1, 134.1, 134.1, 149.4, 179.2", \ + "244.6, 244.6, 244.6, 260.1, 290.7"); + } + rise_transition (inslew_load_5x5__38) { + values ("60.0, 60.0, 60.0, 82.3, 127.1", \ + "110.2, 110.2, 110.2, 132.3, 176.7", \ + "201.7, 201.7, 201.7, 224.0, 268.2", \ + "380.3, 380.3, 380.3, 402.8, 447.4", \ + "735.2, 735.2, 735.2, 757.7, 802.5"); + } + cell_fall (inslew_load_5x5__38) { + values ("5.6, 5.6, 5.6, 14.2, 28.1", \ + "-2.0, -2.0, -2.0, 8.3, 25.4", \ + "-18.9, -18.9, -18.9, -7.0, 13.5", \ + "-53.9, -53.9, -53.9, -40.8, -17.2", \ + "-124.6, -124.6, -124.6, -110.8, -84.9"); + } + fall_transition (inslew_load_5x5__38) { + values ("17.0, 17.0, 17.0, 24.2, 37.3", \ + "27.4, 27.4, 27.4, 35.2, 49.4", \ + "47.3, 47.3, 47.3, 55.7, 71.1", \ + "86.6, 86.6, 86.6, 95.3, 111.9", \ + "164.7, 164.7, 164.7, 173.7, 191.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__38) { + values ("388.6, 388.6, 388.6, 447.2, 564.4", \ + "516.6, 516.6, 516.6, 575.2, 692.4", \ + "772.6, 772.6, 772.6, 831.2, 948.4", \ + "1284.5, 1284.5, 1284.5, 1343.1, 1460.4", \ + "2308.5, 2308.5, 2308.5, 2367.1, 2484.3"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("243.1, 243.1, 243.1, 301.7, 418.9", \ + "307.6, 307.6, 307.6, 366.2, 483.5", \ + "436.8, 436.8, 436.8, 495.4, 612.6", \ + "695.0, 695.0, 695.0, 753.6, 870.9", \ + "1211.6, 1211.6, 1211.6, 1270.2, 1387.4"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__38) { + values ("316.7, 316.7, 316.7, 375.3, 492.5", \ + "416.8, 416.8, 416.8, 475.4, 592.6", \ + "617.0, 617.0, 617.0, 675.6, 792.8", \ + "1017.4, 1017.4, 1017.4, 1076.0, 1193.2", \ + "1818.2, 1818.2, 1818.2, 1876.8, 1994.0"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("185.7, 185.7, 185.7, 244.3, 361.5", \ + "256.5, 256.5, 256.5, 315.2, 432.4", \ + "398.2, 398.2, 398.2, 456.9, 574.1", \ + "681.7, 681.7, 681.7, 740.3, 857.5", \ + "1248.5, 1248.5, 1248.5, 1307.1, 1424.3"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__38) { + values ("222.2, 222.2, 222.2, 280.8, 398.0", \ + "323.6, 323.6, 323.6, 382.2, 499.4", \ + "526.3, 526.3, 526.3, 584.9, 702.1", \ + "931.8, 931.8, 931.8, 990.4, 1107.7", \ + "1742.9, 1742.9, 1742.9, 1801.5, 1918.7"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("154.8, 154.8, 154.8, 213.4, 330.7", \ + "174.3, 174.3, 174.3, 232.9, 350.1", \ + "213.3, 213.3, 213.3, 271.9, 389.1", \ + "291.2, 291.2, 291.2, 349.8, 467.0", \ + "447.0, 447.0, 447.0, 505.6, 622.8"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__38) { + values ("308.4, 308.4, 308.4, 367.0, 484.3", \ + "423.1, 423.1, 423.1, 481.7, 598.9", \ + "652.3, 652.3, 652.3, 710.9, 828.1", \ + "1110.8, 1110.8, 1110.8, 1169.4, 1286.6", \ + "2027.7, 2027.7, 2027.7, 2086.3, 2203.5"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("196.0, 196.0, 196.0, 254.6, 371.8", \ + "228.0, 228.0, 228.0, 286.6, 403.8", \ + "292.1, 292.1, 292.1, 350.7, 467.9", \ + "420.3, 420.3, 420.3, 478.9, 596.1", \ + "676.6, 676.6, 676.6, 735.2, 852.4"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__38) { + values ("157.6, 157.6, 157.6, 216.2, 333.4", \ + "252.0, 252.0, 252.0, 310.6, 427.8", \ + "440.8, 440.8, 440.8, 499.4, 616.6", \ + "818.4, 818.4, 818.4, 877.0, 994.2", \ + "1573.7, 1573.7, 1573.7, 1632.3, 1749.5"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("90.7, 90.7, 90.7, 149.3, 266.6", \ + "127.4, 127.4, 127.4, 186.0, 303.2", \ + "200.7, 200.7, 200.7, 259.3, 376.6", \ + "347.4, 347.4, 347.4, 406.0, 523.2", \ + "640.7, 640.7, 640.7, 699.3, 816.6"); + } + } + } + } + + cell (noa2ao222_x4) { + area : 0.0 ; + cell_leakage_power : 12 ; + leakage_power () { + when : "(i4 & i3 & i2 & i1 & i0)" ; + value : 12 ; + } + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & !(i4))" ; + value : 8.2 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & i3) ^ i4))" ; + value : 10 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 8 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3 & i4)" ; + value : 18 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & i3 & i4)" ; + value : 14 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & i2 & i4)" ; + value : 23 ; + } + leakage_power () { + when : "((i0 & !(i1) & i2 & !(i3) & i4) | (!(i0) & ((i1 & i2 & !(i3) & i4) | (!(i1) & !(i2) & i3 & i4))))" ; + value : 17 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!((i2 | i3)) | !(i4)))" ; + value : 1 ; + } + pin (i4) { + direction : input ; + capacitance : 6.41 ; + } + pin (i3) { + direction : input ; + capacitance : 5.81 ; + } + pin (i2) { + direction : input ; + capacitance : 6.40 ; + } + pin (i1) { + direction : input ; + capacitance : 5.61 ; + } + pin (i0) { + direction : input ; + capacitance : 5.54 ; + } + pin (nq) { + function : "((!(i4) & (!(i0) | !(i1))) | (!((i0 & i1)) & !(i3) & !(i2)))" ; + direction : output ; + capacitance : 4.33 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("197.0, 197.0, 197.0, 201.5, 210.0", \ + "221.1, 221.1, 221.1, 225.7, 234.3", \ + "263.5, 263.5, 263.5, 268.1, 277.0", \ + "344.5, 344.5, 344.5, 349.1, 358.2", \ + "503.7, 503.7, 503.7, 508.3, 517.3"); + } + rise_transition (inslew_load_5x5__39) { + values ("75.5, 75.5, 75.5, 81.2, 92.5", \ + "89.3, 89.3, 89.3, 94.9, 106.2", \ + "114.4, 114.4, 114.4, 120.0, 131.3", \ + "163.4, 163.4, 163.4, 169.0, 180.2", \ + "260.2, 260.2, 260.2, 266.1, 277.5"); + } + cell_fall (inslew_load_5x5__39) { + values ("86.3, 86.3, 86.3, 90.4, 98.2", \ + "86.6, 86.6, 86.6, 90.7, 98.5", \ + "81.3, 81.3, 81.3, 85.5, 93.2", \ + "63.7, 63.7, 63.7, 68.1, 75.9", \ + "20.5, 20.5, 20.5, 25.0, 33.4"); + } + fall_transition (inslew_load_5x5__39) { + values ("33.6, 33.6, 33.6, 36.3, 41.3", \ + "36.4, 36.4, 36.4, 39.0, 44.2", \ + "41.6, 41.6, 41.6, 44.2, 49.6", \ + "51.3, 51.3, 51.3, 54.0, 59.3", \ + "70.1, 70.1, 70.1, 72.8, 78.0"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("179.6, 179.6, 179.6, 184.1, 192.5", \ + "194.9, 194.9, 194.9, 199.5, 208.0", \ + "221.1, 221.1, 221.1, 225.6, 234.4", \ + "269.9, 269.9, 269.9, 274.6, 283.6", \ + "365.1, 365.1, 365.1, 369.7, 378.7"); + } + rise_transition (inslew_load_5x5__39) { + values ("69.5, 69.5, 69.5, 75.3, 86.5", \ + "80.3, 80.3, 80.3, 86.0, 97.2", \ + "100.1, 100.1, 100.1, 105.7, 117.0", \ + "138.7, 138.7, 138.7, 144.3, 155.5", \ + "215.3, 215.3, 215.3, 221.1, 232.3"); + } + cell_fall (inslew_load_5x5__39) { + values ("85.0, 85.0, 85.0, 89.0, 96.9", \ + "89.9, 89.9, 89.9, 94.0, 101.8", \ + "92.6, 92.6, 92.6, 96.8, 104.5", \ + "90.8, 90.8, 90.8, 95.2, 103.1", \ + "80.0, 80.0, 80.0, 84.5, 93.0"); + } + fall_transition (inslew_load_5x5__39) { + values ("32.5, 32.5, 32.5, 35.2, 40.2", \ + "35.9, 35.9, 35.9, 38.6, 43.7", \ + "42.0, 42.0, 42.0, 44.6, 50.0", \ + "53.4, 53.4, 53.4, 56.1, 61.3", \ + "75.4, 75.4, 75.4, 78.0, 83.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("135.7, 135.7, 135.7, 140.1, 148.4", \ + "168.8, 168.8, 168.8, 173.3, 181.6", \ + "224.9, 224.9, 224.9, 229.4, 238.1", \ + "327.7, 327.7, 327.7, 332.4, 341.4", \ + "525.6, 525.6, 525.6, 530.2, 539.2"); + } + rise_transition (inslew_load_5x5__39) { + values ("52.8, 52.8, 52.8, 58.4, 69.5", \ + "67.5, 67.5, 67.5, 73.2, 84.4", \ + "93.8, 93.8, 93.8, 99.5, 110.8", \ + "143.2, 143.2, 143.2, 148.7, 159.9", \ + "239.8, 239.8, 239.8, 245.7, 257.0"); + } + cell_fall (inslew_load_5x5__39) { + values ("73.4, 73.4, 73.4, 77.6, 85.4", \ + "67.7, 67.7, 67.7, 71.8, 79.6", \ + "50.6, 50.6, 50.6, 54.7, 62.5", \ + "8.3, 8.3, 8.3, 12.6, 20.2", \ + "-84.7, -84.7, -84.7, -80.2, -72.3"); + } + fall_transition (inslew_load_5x5__39) { + values ("30.9, 30.9, 30.9, 33.6, 38.6", \ + "33.0, 33.0, 33.0, 35.7, 40.8", \ + "36.6, 36.6, 36.6, 39.3, 44.4", \ + "43.1, 43.1, 43.1, 45.7, 51.1", \ + "55.2, 55.2, 55.2, 57.9, 63.1"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("163.8, 163.8, 163.8, 168.3, 176.6", \ + "183.9, 183.9, 183.9, 188.4, 196.9", \ + "218.4, 218.4, 218.4, 222.9, 231.7", \ + "282.4, 282.4, 282.4, 287.0, 296.0", \ + "406.2, 406.2, 406.2, 410.8, 419.8"); + } + rise_transition (inslew_load_5x5__39) { + values ("63.8, 63.8, 63.8, 69.6, 80.7", \ + "75.5, 75.5, 75.5, 81.2, 92.5", \ + "97.2, 97.2, 97.2, 102.8, 114.1", \ + "139.0, 139.0, 139.0, 144.5, 155.8", \ + "221.5, 221.5, 221.5, 227.4, 238.6"); + } + cell_fall (inslew_load_5x5__39) { + values ("88.9, 88.9, 88.9, 93.0, 100.8", \ + "90.4, 90.4, 90.4, 94.5, 102.3", \ + "86.5, 86.5, 86.5, 90.7, 98.4", \ + "71.0, 71.0, 71.0, 75.4, 83.2", \ + "31.2, 31.2, 31.2, 35.8, 44.0"); + } + fall_transition (inslew_load_5x5__39) { + values ("33.3, 33.3, 33.3, 36.0, 41.1", \ + "36.2, 36.2, 36.2, 38.8, 44.0", \ + "41.3, 41.3, 41.3, 43.9, 49.2", \ + "50.7, 50.7, 50.7, 53.3, 58.6", \ + "68.7, 68.7, 68.7, 71.4, 76.6"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("99.5, 99.5, 99.5, 103.9, 111.9", \ + "118.3, 118.3, 118.3, 122.6, 130.9", \ + "148.2, 148.2, 148.2, 152.7, 161.0", \ + "198.8, 198.8, 198.8, 203.4, 212.2", \ + "293.8, 293.8, 293.8, 298.5, 307.5"); + } + rise_transition (inslew_load_5x5__39) { + values ("41.3, 41.3, 41.3, 46.9, 58.0", \ + "51.5, 51.5, 51.5, 57.2, 68.3", \ + "69.7, 69.7, 69.7, 75.4, 86.6", \ + "103.8, 103.8, 103.8, 109.4, 120.7", \ + "170.0, 170.0, 170.0, 175.7, 186.8"); + } + cell_fall (inslew_load_5x5__39) { + values ("70.9, 70.9, 70.9, 75.1, 82.8", \ + "72.4, 72.4, 72.4, 76.5, 84.3", \ + "69.6, 69.6, 69.6, 73.7, 81.5", \ + "57.6, 57.6, 57.6, 62.0, 69.7", \ + "27.1, 27.1, 27.1, 31.7, 39.9"); + } + fall_transition (inslew_load_5x5__39) { + values ("29.9, 29.9, 29.9, 32.6, 37.6", \ + "33.0, 33.0, 33.0, 35.7, 40.7", \ + "38.4, 38.4, 38.4, 41.1, 46.3", \ + "48.5, 48.5, 48.5, 51.1, 56.5", \ + "67.9, 67.9, 67.9, 70.5, 75.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1215.2, 1215.2, 1215.2, 1269.3, 1377.4", \ + "1440.4, 1440.4, 1440.4, 1494.4, 1602.6", \ + "1868.8, 1868.8, 1868.8, 1922.9, 2031.0", \ + "2717.1, 2717.1, 2717.1, 2771.2, 2879.3", \ + "4410.1, 4410.1, 4410.1, 4464.2, 4572.3"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("776.0, 776.0, 776.0, 830.0, 938.2", \ + "853.0, 853.0, 853.0, 907.0, 1015.2", \ + "1002.7, 1002.7, 1002.7, 1056.8, 1165.0", \ + "1295.4, 1295.4, 1295.4, 1349.5, 1457.6", \ + "1873.7, 1873.7, 1873.7, 1927.8, 2035.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1107.0, 1107.0, 1107.0, 1161.0, 1269.2", \ + "1281.7, 1281.7, 1281.7, 1335.8, 1444.0", \ + "1615.6, 1615.6, 1615.6, 1669.7, 1777.8", \ + "2276.1, 2276.1, 2276.1, 2330.2, 2438.3", \ + "3597.6, 3597.6, 3597.6, 3651.6, 3759.8"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("723.2, 723.2, 723.2, 777.3, 885.5", \ + "811.9, 811.9, 811.9, 866.0, 974.1", \ + "981.7, 981.7, 981.7, 1035.8, 1144.0", \ + "1313.6, 1313.6, 1313.6, 1367.7, 1475.9", \ + "1969.4, 1969.4, 1969.4, 2023.4, 2131.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__39) { + values ("838.5, 838.5, 838.5, 892.6, 1000.7", \ + "1063.4, 1063.4, 1063.4, 1117.4, 1225.6", \ + "1487.1, 1487.1, 1487.1, 1541.2, 1649.4", \ + "2306.9, 2306.9, 2306.9, 2361.0, 2469.1", \ + "3935.9, 3935.9, 3935.9, 3990.0, 4098.2"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("665.4, 665.4, 665.4, 719.4, 827.6", \ + "711.5, 711.5, 711.5, 765.6, 873.8", \ + "797.1, 797.1, 797.1, 851.2, 959.3", \ + "961.3, 961.3, 961.3, 1015.4, 1123.6", \ + "1280.8, 1280.8, 1280.8, 1334.8, 1443.0"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1009.5, 1009.5, 1009.5, 1063.6, 1171.8", \ + "1196.2, 1196.2, 1196.2, 1250.3, 1358.5", \ + "1554.4, 1554.4, 1554.4, 1608.5, 1716.6", \ + "2260.3, 2260.3, 2260.3, 2314.4, 2422.6", \ + "3669.7, 3669.7, 3669.7, 3723.7, 3831.9"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("742.2, 742.2, 742.2, 796.3, 904.5", \ + "811.5, 811.5, 811.5, 865.6, 973.7", \ + "944.0, 944.0, 944.0, 998.0, 1106.2", \ + "1201.6, 1201.6, 1201.6, 1255.6, 1363.8", \ + "1708.2, 1708.2, 1708.2, 1762.3, 1870.5"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__39) { + values ("681.1, 681.1, 681.1, 735.2, 843.4", \ + "847.0, 847.0, 847.0, 901.1, 1009.2", \ + "1163.9, 1163.9, 1163.9, 1218.0, 1326.2", \ + "1780.8, 1780.8, 1780.8, 1834.9, 1943.1", \ + "3003.3, 3003.3, 3003.3, 3057.4, 3165.6"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("613.1, 613.1, 613.1, 667.2, 775.4", \ + "686.5, 686.5, 686.5, 740.5, 848.7", \ + "826.6, 826.6, 826.6, 880.7, 988.8", \ + "1099.7, 1099.7, 1099.7, 1153.8, 1261.9", \ + "1637.9, 1637.9, 1637.9, 1692.0, 1800.2"); + } + } + } + } + + cell (noa3ao322_x1) { + area : 0.0 ; + cell_leakage_power : 7.5 ; + leakage_power () { + when : "(i6 & i5 & i4 & i3 & i2 & i1 & i0)" ; + value : 26 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 9.1 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 8.5 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & i2 & i1 & i0)" ; + value : 8.3 ; + } + leakage_power () { + when : "(!(i6) & i5 & i4 & i3 & !(i2) & i1 & i0)" ; + value : 0.00068 ; + } + leakage_power () { + when : "(i6 & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 0.00059 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 0.00015 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3 & i4 & i5 & !(i6))" ; + value : 0.00065 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & i4 & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & i4 & !(i5) & i6))" ; + value : 21 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & !(i4) & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & !(i4) & !(i5) & i6))" ; + value : 20 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 0.00048 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 0.00031 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & !(i4) & !(i5) & i6)" ; + value : 0.00055 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & i2 & i1 & !(i0))" ; + value : 0.00014 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & !(i5) & i6) | (!(i0) & (i1 ^ i2) & i3 & !(i5) & i6))" ; + value : 24 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & !(i6)))" ; + value : 1.2e-05 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i1) & !(i2) & i3 & i4 & i5 & !(i6)))) | (!(i0) & !((i1 & i2)) & i3 & i4 & i5 & !(i6)))" ; + value : 0.00051 ; + } + leakage_power () { + when : "((!(i0) & ((!((i1 | i2)) & i3 & (i4 | !(i5)) & i6) | (i3 & i4 & i5 & i6))) | (!((i1 & i2)) & i3 & i4 & i5 & i6))" ; + value : 27 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!(i1) & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))) | (!(i0) & !((i1 & i2)) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))" ; + value : 0.00035 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & (i5 ^ i6)) | (!(i4) & i5 & i6))) | (!(i3) & i4 & i5 & i6))) | ((i3 ^ i4) & i5 & i6))) | (!(i1) & ((!(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))) | ((i3 ^ i4) & i5 & i6))))) | (!(i0) & ((!((i1 & i2)) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))) | ((i3 ^ i4) & i5 & i6))))" ; + value : 18 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((!(i3) & !((i4 & i5)) & i6) | (!(i4) & !(i5) & i6))) | (!(i3) & (i4 ^ i5) & i6))) | (i2 & !(i3) & (i4 ^ i5) & i6) | (!(i3) & !(i4) & i5 & i6))) | (i1 & i2 & !(i3) & (i4 ^ i5) & i6) | (!(i3) & !(i4) & i5 & i6))" ; + value : 17 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))) | (!(i0) & !((i1 & i2)) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))" ; + value : 0.00018 ; + } + leakage_power () { + when : "((!(i0) & !((i1 & i2)) & !(i3) & !(i4) & !(i5) & i6) | (!(i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6))" ; + value : 0.00042 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 1e-05 ; + } + pin (i6) { + direction : input ; + capacitance : 6.81 ; + } + pin (i5) { + direction : input ; + capacitance : 7.09 ; + } + pin (i4) { + direction : input ; + capacitance : 7.09 ; + } + pin (i3) { + direction : input ; + capacitance : 7.09 ; + } + pin (i2) { + direction : input ; + capacitance : 7.09 ; + } + pin (i1) { + direction : input ; + capacitance : 7.23 ; + } + pin (i0) { + direction : input ; + capacitance : 7.08 ; + } + pin (nq) { + function : "((((((!(i6) & !(i2)) | (!(i6) & !(i1))) | (!(i6) & !(i0))) | (((!(i3) & !(i4)) & !(i5)) & !(i2))) | (((!(i3) & !(i4)) & !(i5)) & !(i1))) | (((!(i3) & !(i4)) & !(i5)) & !(i0)))" ; + direction : output ; + capacitance : 4.53 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("186.2, 186.2, 186.2, 209.4, 255.8", \ + "218.6, 218.6, 218.6, 241.9, 288.4", \ + "275.5, 275.5, 275.5, 298.9, 345.7", \ + "387.2, 387.2, 387.2, 410.6, 457.5", \ + "611.0, 611.0, 611.0, 634.4, 681.2"); + } + rise_transition (inslew_load_5x5__40) { + values ("344.5, 344.5, 344.5, 386.6, 470.9", \ + "443.7, 443.7, 443.7, 485.6, 569.4", \ + "627.7, 627.7, 627.7, 669.6, 753.3", \ + "987.9, 987.9, 987.9, 1029.9, 1113.9", \ + "1703.6, 1703.6, 1703.6, 1745.7, 1829.9"); + } + cell_fall (inslew_load_5x5__40) { + values ("31.0, 31.0, 31.0, 37.4, 50.0", \ + "29.4, 29.4, 29.4, 36.4, 50.0", \ + "23.6, 23.6, 23.6, 31.4, 46.5", \ + "9.2, 9.2, 9.2, 17.8, 34.5", \ + "-21.7, -21.7, -21.7, -12.4, 5.6"); + } + fall_transition (inslew_load_5x5__40) { + values ("51.3, 51.3, 51.3, 60.3, 78.2", \ + "66.3, 66.3, 66.3, 75.2, 93.2", \ + "95.7, 95.7, 95.7, 104.8, 122.7", \ + "154.2, 154.2, 154.2, 163.3, 181.5", \ + "270.5, 270.5, 270.5, 279.8, 298.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("163.8, 163.8, 163.8, 187.0, 233.5", \ + "183.9, 183.9, 183.9, 207.3, 254.0", \ + "217.8, 217.8, 217.8, 241.4, 288.4", \ + "284.8, 284.8, 284.8, 308.3, 355.5", \ + "419.9, 419.9, 419.9, 443.5, 490.4"); + } + rise_transition (inslew_load_5x5__40) { + values ("304.2, 304.2, 304.2, 346.2, 430.4", \ + "382.1, 382.1, 382.1, 423.8, 507.5", \ + "525.8, 525.8, 525.8, 567.5, 651.2", \ + "805.6, 805.6, 805.6, 847.6, 931.6", \ + "1361.6, 1361.6, 1361.6, 1403.7, 1487.7"); + } + cell_fall (inslew_load_5x5__40) { + values ("29.2, 29.2, 29.2, 36.1, 49.4", \ + "31.5, 31.5, 31.5, 39.3, 54.0", \ + "33.0, 33.0, 33.0, 41.7, 58.3", \ + "33.4, 33.4, 33.4, 43.0, 61.4", \ + "32.7, 32.7, 32.7, 42.8, 62.6"); + } + fall_transition (inslew_load_5x5__40) { + values ("44.0, 44.0, 44.0, 53.0, 71.0", \ + "61.5, 61.5, 61.5, 70.7, 88.7", \ + "95.3, 95.3, 95.3, 104.6, 123.0", \ + "162.0, 162.0, 162.0, 171.4, 190.1", \ + "294.6, 294.6, 294.6, 304.2, 323.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("140.8, 140.8, 140.8, 164.1, 210.6", \ + "152.1, 152.1, 152.1, 175.7, 222.5", \ + "169.8, 169.8, 169.8, 193.5, 240.9", \ + "205.4, 205.4, 205.4, 229.1, 276.5", \ + "278.6, 278.6, 278.6, 302.2, 349.3"); + } + rise_transition (inslew_load_5x5__40) { + values ("263.0, 263.0, 263.0, 304.9, 389.0", \ + "326.3, 326.3, 326.3, 367.8, 451.2", \ + "441.5, 441.5, 441.5, 483.3, 566.9", \ + "665.0, 665.0, 665.0, 707.1, 791.1", \ + "1109.8, 1109.8, 1109.8, 1151.8, 1235.8"); + } + cell_fall (inslew_load_5x5__40) { + values ("27.0, 27.0, 27.0, 35.0, 49.6", \ + "33.2, 33.2, 33.2, 42.3, 59.2", \ + "41.9, 41.9, 41.9, 52.2, 71.3", \ + "56.9, 56.9, 56.9, 68.0, 89.0", \ + "85.4, 85.4, 85.4, 97.0, 119.4"); + } + fall_transition (inslew_load_5x5__40) { + values ("37.2, 37.2, 37.2, 46.5, 64.8", \ + "57.8, 57.8, 57.8, 67.4, 86.1", \ + "96.7, 96.7, 96.7, 106.5, 125.7", \ + "172.9, 172.9, 172.9, 182.8, 202.6", \ + "324.2, 324.2, 324.2, 334.3, 354.4"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("73.0, 73.0, 73.0, 97.3, 145.1", \ + "112.8, 112.8, 112.8, 137.4, 185.7", \ + "180.4, 180.4, 180.4, 205.3, 254.7", \ + "306.6, 306.6, 306.6, 331.8, 381.5", \ + "551.4, 551.4, 551.4, 576.8, 627.2"); + } + rise_transition (inslew_load_5x5__40) { + values ("126.1, 126.1, 126.1, 169.2, 256.2", \ + "215.0, 215.0, 215.0, 257.9, 344.2", \ + "370.6, 370.6, 370.6, 413.0, 498.3", \ + "666.5, 666.5, 666.5, 708.4, 792.5", \ + "1246.3, 1246.3, 1246.3, 1287.9, 1371.4"); + } + cell_fall (inslew_load_5x5__40) { + values ("12.6, 12.6, 12.6, 19.0, 30.5", \ + "1.8, 1.8, 1.8, 9.7, 23.8", \ + "-24.7, -24.7, -24.7, -14.6, 3.0", \ + "-84.1, -84.1, -84.1, -71.5, -49.1", \ + "-209.3, -209.3, -209.3, -194.1, -166.6"); + } + fall_transition (inslew_load_5x5__40) { + values ("24.6, 24.6, 24.6, 31.2, 44.1", \ + "31.3, 31.3, 31.3, 38.5, 51.9", \ + "43.3, 43.3, 43.3, 51.2, 65.8", \ + "65.2, 65.2, 65.2, 74.0, 90.3", \ + "107.0, 107.0, 107.0, 116.7, 134.8"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("108.2, 108.2, 108.2, 131.9, 179.0", \ + "147.8, 147.8, 147.8, 171.6, 219.1", \ + "212.7, 212.7, 212.7, 236.7, 284.4", \ + "334.5, 334.5, 334.5, 358.5, 406.5", \ + "572.7, 572.7, 572.7, 596.9, 645.2"); + } + rise_transition (inslew_load_5x5__40) { + values ("192.3, 192.3, 192.3, 235.1, 321.2", \ + "287.3, 287.3, 287.3, 329.9, 415.5", \ + "450.2, 450.2, 450.2, 492.6, 577.6", \ + "760.4, 760.4, 760.4, 802.4, 886.9", \ + "1374.0, 1374.0, 1374.0, 1415.8, 1499.5"); + } + cell_fall (inslew_load_5x5__40) { + values ("16.8, 16.8, 16.8, 22.7, 33.9", \ + "7.9, 7.9, 7.9, 15.2, 28.5", \ + "-14.8, -14.8, -14.8, -5.7, 10.7", \ + "-66.4, -66.4, -66.4, -55.2, -34.8", \ + "-175.6, -175.6, -175.6, -162.4, -137.9"); + } + fall_transition (inslew_load_5x5__40) { + values ("28.6, 28.6, 28.6, 35.1, 47.9", \ + "36.4, 36.4, 36.4, 43.4, 56.6", \ + "50.7, 50.7, 50.7, 58.2, 72.5", \ + "77.3, 77.3, 77.3, 85.6, 101.2", \ + "128.8, 128.8, 128.8, 137.6, 154.6"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("143.3, 143.3, 143.3, 166.7, 213.5", \ + "181.2, 181.2, 181.2, 204.7, 251.7", \ + "242.7, 242.7, 242.7, 266.3, 313.6", \ + "360.3, 360.3, 360.3, 384.0, 431.2", \ + "594.0, 594.0, 594.0, 617.6, 664.8"); + } + rise_transition (inslew_load_5x5__40) { + values ("260.3, 260.3, 260.3, 302.8, 388.0", \ + "360.1, 360.1, 360.1, 402.4, 487.1", \ + "533.2, 533.2, 533.2, 575.5, 660.2", \ + "867.0, 867.0, 867.0, 909.3, 993.9", \ + "1528.9, 1528.9, 1528.9, 1571.1, 1655.5"); + } + cell_fall (inslew_load_5x5__40) { + values ("19.0, 19.0, 19.0, 24.8, 35.8", \ + "12.4, 12.4, 12.4, 19.3, 32.2", \ + "-5.0, -5.0, -5.0, 3.2, 18.8", \ + "-44.9, -44.9, -44.9, -35.0, -16.5", \ + "-128.6, -128.6, -128.6, -117.5, -96.2"); + } + fall_transition (inslew_load_5x5__40) { + values ("30.9, 30.9, 30.9, 37.4, 50.2", \ + "40.5, 40.5, 40.5, 47.3, 60.4", \ + "58.5, 58.5, 58.5, 65.8, 79.7", \ + "93.2, 93.2, 93.2, 100.9, 115.8", \ + "161.3, 161.3, 161.3, 169.3, 185.1"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("29.3, 29.3, 29.3, 42.8, 68.1", \ + "44.8, 44.8, 44.8, 58.7, 85.2", \ + "71.2, 71.2, 71.2, 85.8, 113.6", \ + "121.2, 121.2, 121.2, 136.2, 165.3", \ + "219.7, 219.7, 219.7, 234.9, 264.9"); + } + rise_transition (inslew_load_5x5__40) { + values ("58.6, 58.6, 58.6, 80.0, 123.2", \ + "105.6, 105.6, 105.6, 126.7, 169.5", \ + "192.5, 192.5, 192.5, 214.1, 256.7", \ + "362.4, 362.4, 362.4, 384.1, 427.3", \ + "700.2, 700.2, 700.2, 722.0, 765.4"); + } + cell_fall (inslew_load_5x5__40) { + values ("6.6, 6.6, 6.6, 15.4, 29.6", \ + "0.0, 0.0, 0.0, 10.5, 27.8", \ + "-14.9, -14.9, -14.9, -2.9, 17.8", \ + "-45.9, -45.9, -45.9, -32.8, -9.0", \ + "-108.4, -108.4, -108.4, -94.7, -68.8"); + } + fall_transition (inslew_load_5x5__40) { + values ("17.5, 17.5, 17.5, 25.0, 38.5", \ + "28.6, 28.6, 28.6, 36.6, 51.2", \ + "49.7, 49.7, 49.7, 58.2, 74.0", \ + "91.4, 91.4, 91.4, 100.3, 117.1", \ + "174.2, 174.2, 174.2, 183.4, 201.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__40) { + values ("468.0, 468.0, 468.0, 524.5, 637.7", \ + "587.5, 587.5, 587.5, 644.1, 757.2", \ + "826.6, 826.6, 826.6, 883.2, 996.3", \ + "1304.8, 1304.8, 1304.8, 1361.3, 1474.5", \ + "2261.1, 2261.1, 2261.1, 2317.7, 2430.8"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("293.5, 293.5, 293.5, 350.1, 463.2", \ + "359.6, 359.6, 359.6, 416.1, 529.3", \ + "491.7, 491.7, 491.7, 548.3, 661.4", \ + "756.1, 756.1, 756.1, 812.6, 925.8", \ + "1284.7, 1284.7, 1284.7, 1341.3, 1454.4"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__40) { + values ("409.0, 409.0, 409.0, 465.6, 578.7", \ + "501.8, 501.8, 501.8, 558.3, 671.5", \ + "687.4, 687.4, 687.4, 743.9, 857.1", \ + "1058.5, 1058.5, 1058.5, 1115.1, 1228.2", \ + "1800.8, 1800.8, 1800.8, 1857.4, 1970.5"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("246.0, 246.0, 246.0, 302.5, 415.6", \ + "317.9, 317.9, 317.9, 374.5, 487.6", \ + "461.9, 461.9, 461.9, 518.5, 631.6", \ + "749.8, 749.8, 749.8, 806.4, 919.5", \ + "1325.6, 1325.6, 1325.6, 1382.2, 1495.3"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__40) { + values ("350.1, 350.1, 350.1, 406.7, 519.8", \ + "424.2, 424.2, 424.2, 480.8, 593.9", \ + "572.4, 572.4, 572.4, 629.0, 742.1", \ + "868.8, 868.8, 868.8, 925.4, 1038.5", \ + "1461.6, 1461.6, 1461.6, 1518.1, 1631.3"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("196.3, 196.3, 196.3, 252.9, 366.0", \ + "272.2, 272.2, 272.2, 328.7, 441.9", \ + "423.9, 423.9, 423.9, 480.5, 593.6", \ + "727.4, 727.4, 727.4, 783.9, 897.1", \ + "1334.3, 1334.3, 1334.3, 1390.9, 1504.0"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__40) { + values ("210.8, 210.8, 210.8, 267.4, 380.5", \ + "297.5, 297.5, 297.5, 354.1, 467.2", \ + "470.9, 470.9, 470.9, 527.5, 640.6", \ + "817.8, 817.8, 817.8, 874.4, 987.5", \ + "1511.5, 1511.5, 1511.5, 1568.1, 1681.2"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("155.1, 155.1, 155.1, 211.7, 324.8", \ + "168.9, 168.9, 168.9, 225.4, 338.6", \ + "196.4, 196.4, 196.4, 253.0, 366.1", \ + "251.4, 251.4, 251.4, 308.0, 421.1", \ + "361.5, 361.5, 361.5, 418.0, 531.2"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__40) { + values ("291.3, 291.3, 291.3, 347.9, 461.0", \ + "388.0, 388.0, 388.0, 444.6, 557.7", \ + "581.4, 581.4, 581.4, 638.0, 751.1", \ + "968.3, 968.3, 968.3, 1024.9, 1138.0", \ + "1742.0, 1742.0, 1742.0, 1798.6, 1911.7"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("190.6, 190.6, 190.6, 247.2, 360.3", \ + "210.8, 210.8, 210.8, 267.4, 380.5", \ + "251.3, 251.3, 251.3, 307.8, 421.0", \ + "332.1, 332.1, 332.1, 388.7, 501.8", \ + "493.8, 493.8, 493.8, 550.3, 663.4"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__40) { + values ("371.6, 371.6, 371.6, 428.2, 541.3", \ + "480.0, 480.0, 480.0, 536.6, 649.7", \ + "696.7, 696.7, 696.7, 753.2, 866.4", \ + "1130.0, 1130.0, 1130.0, 1186.6, 1299.7", \ + "1996.8, 1996.8, 1996.8, 2053.3, 2166.5"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("213.3, 213.3, 213.3, 269.8, 383.0", \ + "246.5, 246.5, 246.5, 303.0, 416.1", \ + "312.8, 312.8, 312.8, 369.4, 482.5", \ + "445.6, 445.6, 445.6, 502.2, 615.3", \ + "711.2, 711.2, 711.2, 767.8, 880.9"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__40) { + values ("149.7, 149.7, 149.7, 206.3, 319.4", \ + "238.6, 238.6, 238.6, 295.2, 408.3", \ + "416.4, 416.4, 416.4, 473.0, 586.1", \ + "772.0, 772.0, 772.0, 828.6, 941.7", \ + "1483.2, 1483.2, 1483.2, 1539.8, 1652.9"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("89.8, 89.8, 89.8, 146.4, 259.5", \ + "127.4, 127.4, 127.4, 183.9, 297.1", \ + "202.5, 202.5, 202.5, 259.0, 372.1", \ + "352.6, 352.6, 352.6, 409.2, 522.3", \ + "652.9, 652.9, 652.9, 709.5, 822.6"); + } + } + } + } + + cell (noa3ao322_x4) { + area : 0.0 ; + cell_leakage_power : 12 ; + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 10 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 9.8 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & i2 & i1 & i0)" ; + value : 9.7 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & !(i5) & i6))" ; + value : 15 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & (i5 ^ i6)) | (!(i4) & i5 & i6))) | (!(i3) & i4 & i5 & i6))) | (!(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))))) | ((i3 ^ i4) & i5 & i6))) | (i1 & (i3 ^ i4) & i5 & i6))" ; + value : 14 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & !(i5) & i6) | (!(i0) & (i1 ^ i2) & i3 & !(i5) & i6))" ; + value : 16 ; + } + leakage_power () { + when : "((!((i0 | i1 | i2)) & i3 & (i4 | !(i5)) & i6) | (i3 & i4 & i5 & i6))" ; + value : 17 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((!(i3) & !((i4 & i5)) & i6) | (!(i4) & !(i5) & i6))) | (!(i3) & !(i4) & i5 & i6))) | (!(i1) & !(i3) & (i4 ^ i5) & i6))) | (!(i0) & ((!(i1) & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))) | (!(i3) & (i4 ^ i5) & i6))))" ; + value : 13 ; + } + leakage_power () { + when : "(!((i0 & i1 & i2)) & (!((i3 | i4 | i5)) | !(i6)))" ; + value : 1.4 ; + } + pin (i6) { + direction : input ; + capacitance : 4.96 ; + } + pin (i5) { + direction : input ; + capacitance : 5.06 ; + } + pin (i4) { + direction : input ; + capacitance : 5.07 ; + } + pin (i3) { + direction : input ; + capacitance : 5.08 ; + } + pin (i2) { + direction : input ; + capacitance : 5.33 ; + } + pin (i1) { + direction : input ; + capacitance : 4.74 ; + } + pin (i0) { + direction : input ; + capacitance : 4.74 ; + } + pin (nq) { + function : "((!((i5 | i4 | i3)) & (!(i1) | !(i2) | !(i0))) | (!((i1 & i2 & i0)) & !(i6)))" ; + direction : output ; + capacitance : 4.26 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("284.3, 284.3, 284.3, 288.8, 297.5", \ + "318.3, 318.3, 318.3, 322.8, 331.6", \ + "376.4, 376.4, 376.4, 381.0, 389.9", \ + "489.1, 489.1, 489.1, 493.6, 502.6", \ + "712.0, 712.0, 712.0, 716.6, 725.6"); + } + rise_transition (inslew_load_5x5__41) { + values ("98.1, 98.1, 98.1, 103.6, 114.8", \ + "115.8, 115.8, 115.8, 121.3, 132.5", \ + "148.0, 148.0, 148.0, 153.4, 164.5", \ + "210.0, 210.0, 210.0, 215.7, 226.8", \ + "332.0, 332.0, 332.0, 337.8, 349.3"); + } + cell_fall (inslew_load_5x5__41) { + values ("107.4, 107.4, 107.4, 111.6, 119.2", \ + "108.0, 108.0, 108.0, 112.2, 119.8", \ + "105.0, 105.0, 105.0, 109.4, 117.0", \ + "93.0, 93.0, 93.0, 97.5, 105.6", \ + "62.0, 62.0, 62.0, 66.5, 75.1"); + } + fall_transition (inslew_load_5x5__41) { + values ("40.1, 40.1, 40.1, 42.7, 48.0", \ + "43.6, 43.6, 43.6, 46.1, 51.5", \ + "50.3, 50.3, 50.3, 52.9, 58.1", \ + "63.4, 63.4, 63.4, 66.0, 71.2", \ + "88.8, 88.8, 88.8, 91.4, 96.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("263.5, 263.5, 263.5, 268.0, 276.6", \ + "284.7, 284.7, 284.7, 289.2, 298.0", \ + "319.4, 319.4, 319.4, 323.9, 332.8", \ + "386.6, 386.6, 386.6, 391.1, 400.1", \ + "520.0, 520.0, 520.0, 524.5, 533.4"); + } + rise_transition (inslew_load_5x5__41) { + values ("91.2, 91.2, 91.2, 96.8, 107.9", \ + "104.9, 104.9, 104.9, 110.4, 121.6", \ + "129.8, 129.8, 129.8, 135.3, 146.4", \ + "177.3, 177.3, 177.3, 183.0, 194.0", \ + "270.9, 270.9, 270.9, 276.7, 288.0"); + } + cell_fall (inslew_load_5x5__41) { + values ("105.0, 105.0, 105.0, 109.2, 116.8", \ + "111.1, 111.1, 111.1, 115.3, 122.9", \ + "117.5, 117.5, 117.5, 121.9, 129.6", \ + "123.1, 123.1, 123.1, 127.5, 135.7", \ + "127.1, 127.1, 127.1, 131.6, 140.3"); + } + fall_transition (inslew_load_5x5__41) { + values ("38.3, 38.3, 38.3, 40.9, 46.1", \ + "42.5, 42.5, 42.5, 45.1, 50.4", \ + "50.5, 50.5, 50.5, 53.1, 58.3", \ + "65.7, 65.7, 65.7, 68.4, 73.6", \ + "95.5, 95.5, 95.5, 98.1, 103.3"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("231.3, 231.3, 231.3, 235.7, 244.2", \ + "240.3, 240.3, 240.3, 244.7, 253.3", \ + "251.6, 251.6, 251.6, 256.1, 264.8", \ + "273.6, 273.6, 273.6, 278.2, 287.1", \ + "319.7, 319.7, 319.7, 324.3, 333.2"); + } + rise_transition (inslew_load_5x5__41) { + values ("80.9, 80.9, 80.9, 86.4, 97.6", \ + "91.4, 91.4, 91.4, 96.9, 108.1", \ + "110.5, 110.5, 110.5, 116.0, 127.1", \ + "146.9, 146.9, 146.9, 152.4, 163.4", \ + "218.1, 218.1, 218.1, 223.9, 235.0"); + } + cell_fall (inslew_load_5x5__41) { + values ("102.4, 102.4, 102.4, 106.5, 114.2", \ + "116.8, 116.8, 116.8, 121.0, 128.6", \ + "138.0, 138.0, 138.0, 142.4, 150.2", \ + "173.1, 173.1, 173.1, 177.6, 185.9", \ + "237.0, 237.0, 237.0, 241.5, 250.2"); + } + fall_transition (inslew_load_5x5__41) { + values ("36.4, 36.4, 36.4, 39.1, 44.2", \ + "42.2, 42.2, 42.2, 44.8, 50.1", \ + "52.6, 52.6, 52.6, 55.3, 60.5", \ + "72.5, 72.5, 72.5, 75.1, 80.3", \ + "111.3, 111.3, 111.3, 114.0, 119.2"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("153.1, 153.1, 153.1, 157.4, 165.7", \ + "184.8, 184.8, 184.8, 189.2, 197.5", \ + "238.1, 238.1, 238.1, 242.6, 251.2", \ + "335.7, 335.7, 335.7, 340.3, 349.2", \ + "525.4, 525.4, 525.4, 530.0, 538.9"); + } + rise_transition (inslew_load_5x5__41) { + values ("53.6, 53.6, 53.6, 59.2, 70.2", \ + "67.2, 67.2, 67.2, 72.9, 83.9", \ + "91.2, 91.2, 91.2, 96.7, 107.9", \ + "136.6, 136.6, 136.6, 142.1, 153.2", \ + "224.8, 224.8, 224.8, 230.6, 241.7"); + } + cell_fall (inslew_load_5x5__41) { + values ("87.3, 87.3, 87.3, 91.3, 99.1", \ + "83.5, 83.5, 83.5, 87.6, 95.3", \ + "68.7, 68.7, 68.7, 72.9, 80.5", \ + "29.4, 29.4, 29.4, 33.7, 41.4", \ + "-60.9, -60.9, -60.9, -56.4, -48.4"); + } + fall_transition (inslew_load_5x5__41) { + values ("32.9, 32.9, 32.9, 35.5, 40.6", \ + "35.4, 35.4, 35.4, 38.0, 43.1", \ + "39.7, 39.7, 39.7, 42.3, 47.5", \ + "47.4, 47.4, 47.4, 50.0, 55.3", \ + "61.6, 61.6, 61.6, 64.3, 69.4"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("192.1, 192.1, 192.1, 196.5, 204.7", \ + "221.7, 221.7, 221.7, 226.2, 234.6", \ + "269.4, 269.4, 269.4, 274.0, 282.7", \ + "358.7, 358.7, 358.7, 363.4, 372.3", \ + "532.4, 532.4, 532.4, 537.0, 545.8"); + } + rise_transition (inslew_load_5x5__41) { + values ("66.6, 66.6, 66.6, 72.2, 83.3", \ + "80.7, 80.7, 80.7, 86.3, 97.4", \ + "105.0, 105.0, 105.0, 110.5, 121.7", \ + "151.3, 151.3, 151.3, 156.8, 167.8", \ + "241.5, 241.5, 241.5, 247.3, 258.5"); + } + cell_fall (inslew_load_5x5__41) { + values ("95.6, 95.6, 95.6, 99.7, 107.4", \ + "94.3, 94.3, 94.3, 98.5, 106.1", \ + "84.8, 84.8, 84.8, 89.0, 96.6", \ + "56.3, 56.3, 56.3, 60.7, 68.5", \ + "-11.6, -11.6, -11.6, -7.2, 1.1"); + } + fall_transition (inslew_load_5x5__41) { + values ("34.8, 34.8, 34.8, 37.5, 42.6", \ + "37.7, 37.7, 37.7, 40.3, 45.4", \ + "42.7, 42.7, 42.7, 45.3, 50.6", \ + "52.0, 52.0, 52.0, 54.6, 59.8", \ + "69.5, 69.5, 69.5, 72.1, 77.2"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("228.8, 228.8, 228.8, 233.3, 241.7", \ + "255.7, 255.7, 255.7, 260.2, 268.8", \ + "297.5, 297.5, 297.5, 302.1, 310.9", \ + "376.8, 376.8, 376.8, 381.4, 390.4", \ + "533.2, 533.2, 533.2, 537.8, 546.6"); + } + rise_transition (inslew_load_5x5__41) { + values ("79.2, 79.2, 79.2, 84.8, 95.9", \ + "93.5, 93.5, 93.5, 99.1, 110.2", \ + "118.7, 118.7, 118.7, 124.2, 135.3", \ + "166.4, 166.4, 166.4, 172.0, 182.9", \ + "259.8, 259.8, 259.8, 265.6, 276.9"); + } + cell_fall (inslew_load_5x5__41) { + values ("100.6, 100.6, 100.6, 104.7, 112.4", \ + "102.8, 102.8, 102.8, 107.0, 114.6", \ + "100.9, 100.9, 100.9, 105.2, 112.8", \ + "88.9, 88.9, 88.9, 93.4, 101.3", \ + "56.3, 56.3, 56.3, 60.8, 69.3"); + } + fall_transition (inslew_load_5x5__41) { + values ("36.0, 36.0, 36.0, 38.7, 43.8", \ + "39.5, 39.5, 39.5, 42.1, 47.3", \ + "45.8, 45.8, 45.8, 48.4, 53.7", \ + "57.9, 57.9, 57.9, 60.6, 65.7", \ + "81.0, 81.0, 81.0, 83.6, 88.8"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("92.4, 92.4, 92.4, 96.7, 104.5", \ + "104.7, 104.7, 104.7, 109.0, 117.0", \ + "122.7, 122.7, 122.7, 127.1, 135.3", \ + "150.7, 150.7, 150.7, 155.2, 163.7", \ + "199.8, 199.8, 199.8, 204.4, 213.3"); + } + rise_transition (inslew_load_5x5__41) { + values ("35.6, 35.6, 35.6, 41.2, 52.1", \ + "43.3, 43.3, 43.3, 48.9, 59.8", \ + "57.2, 57.2, 57.2, 62.8, 73.8", \ + "83.0, 83.0, 83.0, 88.6, 99.7", \ + "133.2, 133.2, 133.2, 138.7, 149.8"); + } + cell_fall (inslew_load_5x5__41) { + values ("82.7, 82.7, 82.7, 86.8, 94.5", \ + "89.0, 89.0, 89.0, 93.1, 100.8", \ + "94.5, 94.5, 94.5, 98.7, 106.3", \ + "98.0, 98.0, 98.0, 102.5, 110.4", \ + "98.6, 98.6, 98.6, 103.1, 111.6"); + } + fall_transition (inslew_load_5x5__41) { + values ("30.9, 30.9, 30.9, 33.6, 38.6", \ + "35.3, 35.3, 35.3, 37.9, 43.0", \ + "42.9, 42.9, 42.9, 45.5, 50.8", \ + "57.0, 57.0, 57.0, 59.7, 64.8", \ + "84.2, 84.2, 84.2, 86.8, 92.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__41) { + values ("1544.7, 1544.7, 1544.7, 1598.0, 1704.6", \ + "1813.9, 1813.9, 1813.9, 1867.2, 1973.8", \ + "2318.1, 2318.1, 2318.1, 2371.4, 2478.0", \ + "3308.4, 3308.4, 3308.4, 3361.7, 3468.3", \ + "5273.3, 5273.3, 5273.3, 5326.6, 5433.2"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("909.7, 909.7, 909.7, 963.0, 1069.6", \ + "993.4, 993.4, 993.4, 1046.7, 1153.3", \ + "1159.7, 1159.7, 1159.7, 1213.0, 1319.6", \ + "1488.1, 1488.1, 1488.1, 1541.4, 1648.0", \ + "2138.0, 2138.0, 2138.0, 2191.3, 2297.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__41) { + values ("1432.1, 1432.1, 1432.1, 1485.4, 1592.0", \ + "1638.6, 1638.6, 1638.6, 1691.9, 1798.5", \ + "2026.0, 2026.0, 2026.0, 2079.3, 2185.9", \ + "2782.7, 2782.7, 2782.7, 2836.0, 2942.6", \ + "4284.8, 4284.8, 4284.8, 4338.1, 4444.7"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("853.0, 853.0, 853.0, 906.3, 1012.9", \ + "951.9, 951.9, 951.9, 1005.2, 1111.8", \ + "1144.1, 1144.1, 1144.1, 1197.4, 1304.0", \ + "1521.2, 1521.2, 1521.2, 1574.5, 1681.1", \ + "2267.1, 2267.1, 2267.1, 2320.4, 2427.0"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__41) { + values ("1281.7, 1281.7, 1281.7, 1335.0, 1441.6", \ + "1442.5, 1442.5, 1442.5, 1495.8, 1602.4", \ + "1744.2, 1744.2, 1744.2, 1797.5, 1904.1", \ + "2331.1, 2331.1, 2331.1, 2384.4, 2491.0", \ + "3495.0, 3495.0, 3495.0, 3548.3, 3654.9"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("805.9, 805.9, 805.9, 859.2, 965.8", \ + "938.8, 938.8, 938.8, 992.1, 1098.7", \ + "1191.7, 1191.7, 1191.7, 1245.0, 1351.6", \ + "1686.2, 1686.2, 1686.2, 1739.5, 1846.1", \ + "2666.7, 2666.7, 2666.7, 2720.0, 2826.6"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__41) { + values ("859.1, 859.1, 859.1, 912.4, 1019.1", \ + "1053.9, 1053.9, 1053.9, 1107.2, 1213.8", \ + "1411.2, 1411.2, 1411.2, 1464.5, 1571.1", \ + "2104.1, 2104.1, 2104.1, 2157.4, 2264.0", \ + "3472.8, 3472.8, 3472.8, 3526.1, 3632.7"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("706.7, 706.7, 706.7, 760.0, 866.6", \ + "752.3, 752.3, 752.3, 805.6, 912.2", \ + "834.9, 834.9, 834.9, 888.2, 994.8", \ + "990.2, 990.2, 990.2, 1043.5, 1150.1", \ + "1286.0, 1286.0, 1286.0, 1339.3, 1445.9"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__41) { + values ("1055.4, 1055.4, 1055.4, 1108.7, 1215.3", \ + "1260.4, 1260.4, 1260.4, 1313.7, 1420.3", \ + "1630.0, 1630.0, 1630.0, 1683.3, 1789.9", \ + "2348.6, 2348.6, 2348.6, 2401.9, 2508.5", \ + "3771.9, 3771.9, 3771.9, 3825.2, 3931.8"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("763.2, 763.2, 763.2, 816.5, 923.1", \ + "818.7, 818.7, 818.7, 872.0, 978.7", \ + "923.2, 923.2, 923.2, 976.5, 1083.1", \ + "1121.5, 1121.5, 1121.5, 1174.8, 1281.4", \ + "1505.9, 1505.9, 1505.9, 1559.2, 1665.8"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__41) { + values ("1247.0, 1247.0, 1247.0, 1300.3, 1406.9", \ + "1459.5, 1459.5, 1459.5, 1512.8, 1619.4", \ + "1847.1, 1847.1, 1847.1, 1900.4, 2007.0", \ + "2598.9, 2598.9, 2598.9, 2652.2, 2758.8", \ + "4091.2, 4091.2, 4091.2, 4144.5, 4251.1"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("799.9, 799.9, 799.9, 853.2, 959.9", \ + "874.5, 874.5, 874.5, 927.8, 1034.4", \ + "1017.7, 1017.7, 1017.7, 1071.0, 1177.6", \ + "1295.9, 1295.9, 1295.9, 1349.2, 1455.8", \ + "1841.7, 1841.7, 1841.7, 1895.0, 2001.6"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__41) { + values ("641.7, 641.7, 641.7, 695.0, 801.6", \ + "763.6, 763.6, 763.6, 816.9, 923.5", \ + "998.4, 998.4, 998.4, 1051.7, 1158.3", \ + "1454.7, 1454.7, 1454.7, 1508.0, 1614.6", \ + "2358.9, 2358.9, 2358.9, 2412.2, 2518.8"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("653.7, 653.7, 653.7, 707.0, 813.6", \ + "742.3, 742.3, 742.3, 795.6, 902.2", \ + "907.6, 907.6, 907.6, 960.9, 1067.5", \ + "1226.4, 1226.4, 1226.4, 1279.7, 1386.3", \ + "1854.8, 1854.8, 1854.8, 1908.1, 2014.7"); + } + } + } + } + + cell (nxr2_x1) { + area : 0.0 ; + cell_leakage_power : 7 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 2 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 7.1 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 19 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.00026 ; + } + pin (i1) { + direction : input ; + capacitance : 10.42 ; + } + pin (i0) { + direction : input ; + capacitance : 10.17 ; + } + pin (nq) { + function : "!((i1 ^ i0))" ; + direction : output ; + capacitance : 4.16 ; + timing (maxd_nq_i0_positive_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__42) { + values ("46.8, 46.8, 46.8, 59.1, 81.9", \ + "53.3, 53.3, 53.3, 65.8, 89.2", \ + "59.9, 59.9, 59.9, 72.8, 97.2", \ + "67.5, 67.5, 67.5, 81.1, 106.6", \ + "78.5, 78.5, 78.5, 92.6, 119.4"); + } + rise_transition (inslew_load_5x5__42) { + values ("38.3, 38.3, 38.3, 58.3, 98.1", \ + "53.5, 53.5, 53.5, 72.9, 112.6", \ + "79.0, 79.0, 79.0, 98.5, 137.8", \ + "125.5, 125.5, 125.5, 145.4, 184.6", \ + "215.3, 215.3, 215.3, 235.3, 275.1"); + } + cell_fall (inslew_load_5x5__42) { + values ("45.9, 45.9, 45.9, 55.9, 72.2", \ + "51.5, 51.5, 51.5, 62.2, 80.0", \ + "58.9, 58.9, 58.9, 69.9, 89.7", \ + "69.2, 69.2, 69.2, 81.6, 102.9", \ + "88.1, 88.1, 88.1, 99.9, 124.2"); + } + fall_transition (inslew_load_5x5__42) { + values ("27.4, 27.4, 27.4, 35.8, 51.8", \ + "36.2, 36.2, 36.2, 44.7, 61.0", \ + "52.7, 52.7, 52.7, 61.5, 78.2", \ + "84.9, 84.9, 84.9, 93.7, 111.0", \ + "148.6, 148.6, 148.6, 157.7, 175.2"); + } + } + timing (maxd_nq_i1_positive_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__42) { + values ("66.1, 66.1, 66.1, 77.1, 98.8", \ + "69.0, 69.0, 69.0, 80.2, 102.0", \ + "69.7, 69.7, 69.7, 81.1, 103.4", \ + "67.2, 67.2, 67.2, 78.8, 101.5", \ + "59.2, 59.2, 59.2, 71.1, 94.5"); + } + rise_transition (inslew_load_5x5__42) { + values ("77.1, 77.1, 77.1, 96.4, 135.8", \ + "88.8, 88.8, 88.8, 108.1, 147.0", \ + "109.5, 109.5, 109.5, 128.7, 167.2", \ + "148.7, 148.7, 148.7, 167.6, 205.7", \ + "224.2, 224.2, 224.2, 243.2, 282.4"); + } + cell_fall (inslew_load_5x5__42) { + values ("64.2, 64.2, 64.2, 72.0, 86.5", \ + "74.8, 74.8, 74.8, 83.1, 98.4", \ + "90.9, 90.9, 90.9, 99.7, 116.3", \ + "118.5, 118.5, 118.5, 128.1, 145.9", \ + "171.0, 171.0, 171.0, 180.5, 199.4"); + } + fall_transition (inslew_load_5x5__42) { + values ("43.0, 43.0, 43.0, 51.0, 66.6", \ + "55.5, 55.5, 55.5, 63.5, 79.3", \ + "78.7, 78.7, 78.7, 86.9, 102.9", \ + "124.0, 124.0, 124.0, 132.3, 148.5", \ + "213.7, 213.7, 213.7, 222.0, 238.5"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__42) { + values ("52.1, 52.1, 52.1, 63.1, 84.8", \ + "59.8, 59.8, 59.8, 71.2, 93.2", \ + "73.8, 73.8, 73.8, 85.2, 107.8", \ + "100.9, 100.9, 100.9, 112.6, 135.7", \ + "154.4, 154.4, 154.4, 166.2, 189.8"); + } + rise_transition (inslew_load_5x5__42) { + values ("108.9, 108.9, 108.9, 128.3, 167.3", \ + "151.7, 151.7, 151.7, 170.8, 209.4", \ + "235.0, 235.0, 235.0, 253.9, 291.8", \ + "401.1, 401.1, 401.1, 419.8, 457.3", \ + "728.2, 728.2, 728.2, 747.1, 784.9"); + } + cell_fall (inslew_load_5x5__42) { + values ("25.6, 25.6, 25.6, 32.1, 44.6", \ + "26.5, 26.5, 26.5, 33.8, 47.7", \ + "26.0, 26.0, 26.0, 34.1, 49.5", \ + "22.8, 22.8, 22.8, 31.6, 48.5", \ + "15.3, 15.3, 15.3, 24.6, 42.6"); + } + fall_transition (inslew_load_5x5__42) { + values ("39.2, 39.2, 39.2, 47.0, 62.5", \ + "56.8, 56.8, 56.8, 64.6, 80.1", \ + "90.8, 90.8, 90.8, 98.8, 114.5", \ + "158.0, 158.0, 158.0, 166.2, 182.2", \ + "291.9, 291.9, 291.9, 300.1, 316.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__42) { + values ("36.7, 36.7, 36.7, 48.8, 71.7", \ + "53.5, 53.5, 53.5, 66.1, 90.1", \ + "82.7, 82.7, 82.7, 95.8, 120.9", \ + "138.4, 138.4, 138.4, 151.9, 178.3", \ + "248.4, 248.4, 248.4, 262.1, 289.2"); + } + rise_transition (inslew_load_5x5__42) { + values ("70.9, 70.9, 70.9, 91.0, 130.5", \ + "119.5, 119.5, 119.5, 139.1, 178.5", \ + "210.2, 210.2, 210.2, 230.0, 269.1", \ + "388.1, 388.1, 388.1, 408.0, 447.6", \ + "742.1, 742.1, 742.1, 762.0, 801.8"); + } + cell_fall (inslew_load_5x5__42) { + values ("13.1, 13.1, 13.1, 20.6, 34.1", \ + "6.6, 6.6, 6.6, 15.3, 30.9", \ + "-8.7, -8.7, -8.7, 1.2, 19.4", \ + "-41.5, -41.5, -41.5, -30.3, -9.5", \ + "-108.2, -108.2, -108.2, -96.3, -73.6"); + } + fall_transition (inslew_load_5x5__42) { + values ("26.3, 26.3, 26.3, 34.2, 49.7", \ + "37.7, 37.7, 37.7, 46.0, 61.8", \ + "59.7, 59.7, 59.7, 68.3, 84.8", \ + "102.9, 102.9, 102.9, 111.8, 129.1", \ + "188.5, 188.5, 188.5, 197.7, 215.7"); + } + } + internal_power (energy_pos_nq_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__42) { + values ("234.4, 234.4, 234.4, 286.5, 390.5", \ + "295.3, 295.3, 295.3, 347.3, 451.3", \ + "414.3, 414.3, 414.3, 466.3, 570.3", \ + "650.1, 650.1, 650.1, 702.1, 806.1", \ + "1120.5, 1120.5, 1120.5, 1172.6, 1276.6"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("253.8, 253.8, 253.8, 305.8, 409.8", \ + "326.4, 326.4, 326.4, 378.4, 482.5", \ + "469.7, 469.7, 469.7, 521.7, 625.7", \ + "754.8, 754.8, 754.8, 806.8, 910.9", \ + "1324.3, 1324.3, 1324.3, 1376.3, 1480.4"); + } + } + internal_power (energy_pos_nq_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__42) { + values ("331.7, 331.7, 331.7, 383.8, 487.8", \ + "392.1, 392.1, 392.1, 444.1, 548.1", \ + "510.6, 510.6, 510.6, 562.6, 666.6", \ + "745.2, 745.2, 745.2, 797.3, 901.3", \ + "1213.0, 1213.0, 1213.0, 1265.0, 1369.0"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("364.0, 364.0, 364.0, 416.0, 520.1", \ + "457.0, 457.0, 457.0, 509.0, 613.0", \ + "639.2, 639.2, 639.2, 691.2, 795.2", \ + "1001.0, 1001.0, 1001.0, 1053.0, 1157.1", \ + "1723.2, 1723.2, 1723.2, 1775.2, 1879.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__42) { + values ("278.2, 278.2, 278.2, 330.2, 434.2", \ + "376.4, 376.4, 376.4, 428.5, 532.5", \ + "573.0, 573.0, 573.0, 625.0, 729.0", \ + "966.1, 966.1, 966.1, 1018.1, 1122.1", \ + "1752.2, 1752.2, 1752.2, 1804.2, 1908.2"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("225.9, 225.9, 225.9, 277.9, 381.9", \ + "299.3, 299.3, 299.3, 351.3, 455.4", \ + "446.2, 446.2, 446.2, 498.2, 602.3", \ + "740.1, 740.1, 740.1, 792.1, 896.1", \ + "1327.7, 1327.7, 1327.7, 1379.7, 1483.8"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__42) { + values ("179.9, 179.9, 179.9, 231.9, 335.9", \ + "274.1, 274.1, 274.1, 326.1, 430.1", \ + "462.4, 462.4, 462.4, 514.5, 618.5", \ + "839.2, 839.2, 839.2, 891.2, 995.3", \ + "1592.7, 1592.7, 1592.7, 1644.7, 1748.8"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("132.3, 132.3, 132.3, 184.4, 288.4", \ + "170.5, 170.5, 170.5, 222.5, 326.5", \ + "246.7, 246.7, 246.7, 298.7, 402.8", \ + "399.2, 399.2, 399.2, 451.2, 555.3", \ + "704.3, 704.3, 704.3, 756.3, 860.3"); + } + } + } + } + + cell (nxr2_x4) { + area : 0.0 ; + cell_leakage_power : 11 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 8.1 ; + } + leakage_power () { + when : "(i0 ^ i1)" ; + value : 6.4 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 18 ; + } + pin (i1) { + direction : input ; + capacitance : 10.19 ; + } + pin (i0) { + direction : input ; + capacitance : 10.09 ; + } + pin (nq) { + function : "!((i1 ^ i0))" ; + direction : output ; + capacitance : 4.17 ; + timing (maxd_nq_i0_positive_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("58.1, 58.1, 58.1, 62.4, 70.4", \ + "63.2, 63.2, 63.2, 67.5, 75.7", \ + "68.6, 68.6, 68.6, 73.1, 81.5", \ + "74.4, 74.4, 74.4, 79.0, 87.8", \ + "81.9, 81.9, 81.9, 86.5, 95.4"); + } + rise_transition (inslew_load_5x5__3) { + values ("42.8, 42.8, 42.8, 48.2, 59.0", \ + "53.6, 53.6, 53.6, 59.2, 70.0", \ + "74.7, 74.7, 74.7, 80.1, 91.1", \ + "115.5, 115.5, 115.5, 121.0, 131.9", \ + "195.7, 195.7, 195.7, 201.4, 212.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("91.7, 91.7, 91.7, 96.2, 104.2", \ + "100.4, 100.4, 100.4, 104.9, 113.2", \ + "115.1, 115.1, 115.1, 119.7, 128.4", \ + "143.2, 143.2, 143.2, 147.8, 156.8", \ + "197.9, 197.9, 197.9, 202.5, 211.6"); + } + fall_transition (inslew_load_5x5__3) { + values ("59.4, 59.4, 59.4, 62.2, 67.8", \ + "74.0, 74.0, 74.0, 76.8, 82.3", \ + "102.5, 102.5, 102.5, 105.3, 110.8", \ + "159.6, 159.6, 159.6, 162.4, 168.0", \ + "272.8, 272.8, 272.8, 275.5, 281.0"); + } + } + timing (maxd_nq_i1_positive_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("58.2, 58.2, 58.2, 62.6, 70.4", \ + "68.9, 68.9, 68.9, 73.2, 81.4", \ + "83.9, 83.9, 83.9, 88.4, 96.9", \ + "108.3, 108.3, 108.3, 112.9, 121.8", \ + "153.2, 153.2, 153.2, 157.8, 166.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("39.4, 39.4, 39.4, 44.9, 55.7", \ + "52.5, 52.5, 52.5, 58.0, 68.8", \ + "76.7, 76.7, 76.7, 82.1, 93.1", \ + "123.3, 123.3, 123.3, 128.9, 139.8", \ + "214.9, 214.9, 214.9, 220.5, 231.8"); + } + cell_fall (inslew_load_5x5__3) { + values ("80.7, 80.7, 80.7, 85.1, 93.0", \ + "83.5, 83.5, 83.5, 87.9, 96.1", \ + "86.5, 86.5, 86.5, 91.1, 99.6", \ + "90.8, 90.8, 90.8, 95.4, 104.3", \ + "97.0, 97.0, 97.0, 101.6, 110.6"); + } + fall_transition (inslew_load_5x5__3) { + values ("52.6, 52.6, 52.6, 55.3, 60.9", \ + "63.8, 63.8, 63.8, 66.6, 72.1", \ + "86.0, 86.0, 86.0, 88.8, 94.3", \ + "129.9, 129.9, 129.9, 132.7, 138.3", \ + "218.0, 218.0, 218.0, 220.8, 226.3"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("83.9, 83.9, 83.9, 88.2, 95.9", \ + "92.8, 92.8, 92.8, 97.2, 105.1", \ + "104.5, 104.5, 104.5, 108.8, 117.0", \ + "121.2, 121.2, 121.2, 125.7, 134.1", \ + "149.0, 149.0, 149.0, 153.6, 162.4"); + } + rise_transition (inslew_load_5x5__3) { + values ("35.9, 35.9, 35.9, 41.4, 52.1", \ + "41.8, 41.8, 41.8, 47.3, 58.1", \ + "52.4, 52.4, 52.4, 58.0, 68.8", \ + "72.5, 72.5, 72.5, 77.9, 88.9", \ + "111.3, 111.3, 111.3, 116.8, 127.7"); + } + cell_fall (inslew_load_5x5__3) { + values ("88.3, 88.3, 88.3, 92.5, 100.5", \ + "95.8, 95.8, 95.8, 100.0, 108.0", \ + "104.1, 104.1, 104.1, 108.4, 116.3", \ + "113.7, 113.7, 113.7, 118.2, 126.3", \ + "126.9, 126.9, 126.9, 131.5, 140.1"); + } + fall_transition (inslew_load_5x5__3) { + values ("35.5, 35.5, 35.5, 38.3, 43.6", \ + "40.6, 40.6, 40.6, 43.4, 48.8", \ + "49.4, 49.4, 49.4, 52.2, 57.8", \ + "65.6, 65.6, 65.6, 68.4, 73.9", \ + "96.9, 96.9, 96.9, 99.7, 105.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("83.4, 83.4, 83.4, 87.7, 95.5", \ + "89.9, 89.9, 89.9, 94.2, 102.2", \ + "97.5, 97.5, 97.5, 101.8, 110.0", \ + "107.0, 107.0, 107.0, 111.4, 119.7", \ + "119.3, 119.3, 119.3, 123.9, 132.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("38.0, 38.0, 38.0, 43.4, 54.2", \ + "42.6, 42.6, 42.6, 48.1, 58.8", \ + "51.1, 51.1, 51.1, 56.6, 67.4", \ + "67.1, 67.1, 67.1, 72.6, 83.5", \ + "98.1, 98.1, 98.1, 103.5, 114.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("96.6, 96.6, 96.6, 100.8, 108.8", \ + "105.9, 105.9, 105.9, 110.2, 118.1", \ + "117.7, 117.7, 117.7, 122.1, 130.1", \ + "134.0, 134.0, 134.0, 138.5, 146.9", \ + "159.9, 159.9, 159.9, 164.5, 173.3"); + } + fall_transition (inslew_load_5x5__3) { + values ("40.5, 40.5, 40.5, 43.3, 48.7", \ + "46.6, 46.6, 46.6, 49.4, 54.9", \ + "57.3, 57.3, 57.3, 60.0, 65.6", \ + "76.7, 76.7, 76.7, 79.5, 85.0", \ + "114.3, 114.3, 114.3, 117.1, 122.6"); + } + } + internal_power (energy_pos_nq_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("673.7, 673.7, 673.7, 725.9, 830.2", \ + "816.4, 816.4, 816.4, 868.5, 972.9", \ + "1098.5, 1098.5, 1098.5, 1150.7, 1255.0", \ + "1658.4, 1658.4, 1658.4, 1710.6, 1815.0", \ + "2773.6, 2773.6, 2773.6, 2825.8, 2930.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("976.1, 976.1, 976.1, 1028.2, 1132.6", \ + "1198.0, 1198.0, 1198.0, 1250.2, 1354.6", \ + "1636.7, 1636.7, 1636.7, 1688.9, 1793.2", \ + "2516.0, 2516.0, 2516.0, 2568.2, 2672.6", \ + "4264.8, 4264.8, 4264.8, 4317.0, 4421.3"); + } + } + internal_power (energy_pos_nq_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("611.9, 611.9, 611.9, 664.1, 768.4", \ + "772.7, 772.7, 772.7, 824.9, 929.2", \ + "1084.8, 1084.8, 1084.8, 1137.0, 1241.3", \ + "1702.0, 1702.0, 1702.0, 1754.1, 1858.5", \ + "2930.4, 2930.4, 2930.4, 2982.6, 3086.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("862.3, 862.3, 862.3, 914.5, 1018.9", \ + "1030.4, 1030.4, 1030.4, 1082.6, 1186.9", \ + "1364.7, 1364.7, 1364.7, 1416.9, 1521.2", \ + "2029.2, 2029.2, 2029.2, 2081.4, 2185.7", \ + "3362.1, 3362.1, 3362.1, 3414.3, 3518.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("657.7, 657.7, 657.7, 709.9, 814.2", \ + "766.8, 766.8, 766.8, 819.0, 923.3", \ + "977.3, 977.3, 977.3, 1029.5, 1133.8", \ + "1391.4, 1391.4, 1391.4, 1443.6, 1547.9", \ + "2213.5, 2213.5, 2213.5, 2265.7, 2370.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("729.6, 729.6, 729.6, 781.8, 886.1", \ + "833.2, 833.2, 833.2, 885.4, 989.7", \ + "1026.6, 1026.6, 1026.6, 1078.7, 1183.1", \ + "1400.3, 1400.3, 1400.3, 1452.5, 1556.9", \ + "2136.2, 2136.2, 2136.2, 2188.4, 2292.8"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("711.9, 711.9, 711.9, 764.1, 868.4", \ + "810.6, 810.6, 810.6, 862.8, 967.2", \ + "1002.8, 1002.8, 1002.8, 1054.9, 1159.3", \ + "1381.3, 1381.3, 1381.3, 1433.4, 1537.8", \ + "2132.2, 2132.2, 2132.2, 2184.4, 2288.8"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("816.6, 816.6, 816.6, 868.8, 973.1", \ + "935.2, 935.2, 935.2, 987.4, 1091.7", \ + "1157.4, 1157.4, 1157.4, 1209.6, 1314.0", \ + "1582.2, 1582.2, 1582.2, 1634.3, 1738.7", \ + "2420.5, 2420.5, 2420.5, 2472.7, 2577.0"); + } + } + } + } + + cell (o2_x2) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.76 ; + } + leakage_power () { + when : "i1" ; + value : 1.9 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 4.4 ; + } + pin (i1) { + direction : input ; + capacitance : 4.95 ; + } + pin (i0) { + direction : input ; + capacitance : 5.16 ; + } + pin (q) { + function : "(i0 | i1)" ; + direction : output ; + capacitance : 2.60 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("46.7, 46.7, 46.7, 51.8, 60.8", \ + "56.0, 56.0, 56.0, 61.3, 70.8", \ + "69.3, 69.3, 69.3, 74.7, 84.8", \ + "91.1, 91.1, 91.1, 96.7, 107.4", \ + "131.7, 131.7, 131.7, 137.4, 148.4"); + } + rise_transition (inslew_load_5x5__43) { + values ("29.6, 29.6, 29.6, 36.4, 49.5", \ + "42.4, 42.4, 42.4, 49.2, 62.5", \ + "65.6, 65.6, 65.6, 72.5, 86.0", \ + "110.3, 110.3, 110.3, 117.1, 130.7", \ + "197.7, 197.7, 197.7, 204.8, 218.6"); + } + cell_fall (inslew_load_5x5__43) { + values ("68.2, 68.2, 68.2, 73.3, 83.0", \ + "70.7, 70.7, 70.7, 76.0, 85.7", \ + "73.9, 73.9, 73.9, 79.4, 89.5", \ + "78.3, 78.3, 78.3, 84.0, 94.7", \ + "85.3, 85.3, 85.3, 91.0, 102.2"); + } + fall_transition (inslew_load_5x5__43) { + values ("43.6, 43.6, 43.6, 47.2, 53.8", \ + "54.7, 54.7, 54.7, 58.2, 65.0", \ + "76.5, 76.5, 76.5, 79.9, 86.8", \ + "119.2, 119.2, 119.2, 122.7, 129.6", \ + "205.2, 205.2, 205.2, 208.7, 215.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("37.0, 37.0, 37.0, 42.0, 50.7", \ + "38.8, 38.8, 38.8, 44.0, 53.2", \ + "36.5, 36.5, 36.5, 41.8, 51.7", \ + "26.9, 26.9, 26.9, 32.4, 42.8", \ + "3.6, 3.6, 3.6, 9.2, 20.2"); + } + rise_transition (inslew_load_5x5__43) { + values ("24.4, 24.4, 24.4, 31.2, 44.4", \ + "34.3, 34.3, 34.3, 41.1, 54.3", \ + "51.6, 51.6, 51.6, 58.5, 71.8", \ + "83.9, 83.9, 83.9, 90.7, 104.3", \ + "146.8, 146.8, 146.8, 153.8, 167.3"); + } + cell_fall (inslew_load_5x5__43) { + values ("57.3, 57.3, 57.3, 62.6, 71.8", \ + "69.1, 69.1, 69.1, 74.2, 83.9", \ + "87.3, 87.3, 87.3, 92.8, 102.8", \ + "119.9, 119.9, 119.9, 125.6, 136.3", \ + "182.3, 182.3, 182.3, 188.0, 199.2"); + } + fall_transition (inslew_load_5x5__43) { + values ("33.0, 33.0, 33.0, 36.4, 43.0", \ + "46.1, 46.1, 46.1, 49.6, 56.3", \ + "71.1, 71.1, 71.1, 74.6, 81.4", \ + "119.8, 119.8, 119.8, 123.2, 130.1", \ + "216.5, 216.5, 216.5, 219.9, 226.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__43) { + values ("289.8, 289.8, 289.8, 322.3, 387.3", \ + "381.2, 381.2, 381.2, 413.7, 478.7", \ + "559.9, 559.9, 559.9, 592.5, 657.5", \ + "914.1, 914.1, 914.1, 946.6, 1011.6", \ + "1620.1, 1620.1, 1620.1, 1652.7, 1717.7"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("424.0, 424.0, 424.0, 456.5, 521.5", \ + "520.6, 520.6, 520.6, 553.1, 618.1", \ + "712.8, 712.8, 712.8, 745.3, 810.3", \ + "1094.2, 1094.2, 1094.2, 1126.7, 1191.8", \ + "1859.3, 1859.3, 1859.3, 1891.8, 1956.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__43) { + values ("225.7, 225.7, 225.7, 258.2, 323.3", \ + "284.2, 284.2, 284.2, 316.8, 381.8", \ + "397.5, 397.5, 397.5, 430.0, 495.1", \ + "620.2, 620.2, 620.2, 652.7, 717.7", \ + "1062.8, 1062.8, 1062.8, 1095.3, 1160.3"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("319.6, 319.6, 319.6, 352.1, 417.1", \ + "424.9, 424.9, 424.9, 457.4, 522.4", \ + "630.2, 630.2, 630.2, 662.8, 727.8", \ + "1036.4, 1036.4, 1036.4, 1068.9, 1133.9", \ + "1846.4, 1846.4, 1846.4, 1878.9, 1943.9"); + } + } + } + } + + cell (o2_x4) { + area : 0.0 ; + cell_leakage_power : 2.7 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 0.76 ; + } + leakage_power () { + when : "i1" ; + value : 1.9 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 5.4 ; + } + pin (i1) { + direction : input ; + capacitance : 5.00 ; + } + pin (i0) { + direction : input ; + capacitance : 6.29 ; + } + pin (q) { + function : "(i0 | i1)" ; + direction : output ; + capacitance : 4.20 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("33.4, 33.4, 33.4, 37.6, 45.0", \ + "32.6, 32.6, 32.6, 36.8, 44.5", \ + "24.7, 24.7, 24.7, 29.1, 37.2", \ + "3.0, 3.0, 3.0, 7.5, 15.9", \ + "-45.8, -45.8, -45.8, -41.2, -32.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("23.0, 23.0, 23.0, 28.6, 39.3", \ + "31.8, 31.8, 31.8, 37.4, 48.1", \ + "47.0, 47.0, 47.0, 52.5, 63.4", \ + "74.8, 74.8, 74.8, 80.3, 91.3", \ + "128.6, 128.6, 128.6, 134.2, 145.1"); + } + cell_fall (inslew_load_5x5__21) { + values ("107.6, 107.6, 107.6, 112.1, 120.3", \ + "127.4, 127.4, 127.4, 132.0, 140.5", \ + "162.8, 162.8, 162.8, 167.4, 176.4", \ + "231.0, 231.0, 231.0, 235.6, 244.7", \ + "366.6, 366.6, 366.6, 371.3, 380.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("66.5, 66.5, 66.5, 69.2, 74.7", \ + "87.4, 87.4, 87.4, 90.1, 95.6", \ + "126.8, 126.8, 126.8, 129.5, 135.1", \ + "204.8, 204.8, 204.8, 207.5, 213.0", \ + "360.8, 360.8, 360.8, 363.5, 369.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("53.5, 53.5, 53.5, 57.8, 65.5", \ + "58.1, 58.1, 58.1, 62.5, 70.4", \ + "59.2, 59.2, 59.2, 63.7, 71.9", \ + "52.8, 52.8, 52.8, 57.4, 66.1", \ + "32.3, 32.3, 32.3, 36.9, 45.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("32.7, 32.7, 32.7, 38.2, 49.0", \ + "42.8, 42.8, 42.8, 48.3, 59.1", \ + "60.6, 60.6, 60.6, 66.2, 77.1", \ + "93.9, 93.9, 93.9, 99.3, 110.3", \ + "157.5, 157.5, 157.5, 163.3, 174.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("84.3, 84.3, 84.3, 88.7, 96.5", \ + "97.6, 97.6, 97.6, 102.1, 110.2", \ + "118.1, 118.1, 118.1, 122.7, 131.2", \ + "153.2, 153.2, 153.2, 157.8, 166.8", \ + "218.4, 218.4, 218.4, 223.0, 232.1"); + } + fall_transition (inslew_load_5x5__21) { + values ("48.9, 48.9, 48.9, 51.6, 57.2", \ + "62.2, 62.2, 62.2, 64.9, 70.4", \ + "87.5, 87.5, 87.5, 90.3, 95.7", \ + "137.3, 137.3, 137.3, 140.0, 145.6", \ + "236.0, 236.0, 236.0, 238.7, 244.1"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("424.3, 424.3, 424.3, 476.8, 581.9", \ + "519.0, 519.0, 519.0, 571.5, 676.5", \ + "700.0, 700.0, 700.0, 752.5, 857.6", \ + "1053.1, 1053.1, 1053.1, 1105.6, 1210.7", \ + "1753.0, 1753.0, 1753.0, 1805.5, 1910.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("939.3, 939.3, 939.3, 991.8, 1096.8", \ + "1210.9, 1210.9, 1210.9, 1263.4, 1368.5", \ + "1734.4, 1734.4, 1734.4, 1787.0, 1892.0", \ + "2775.1, 2775.1, 2775.1, 2827.6, 2932.6", \ + "4855.4, 4855.4, 4855.4, 4907.9, 5013.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("443.4, 443.4, 443.4, 495.9, 601.0", \ + "534.8, 534.8, 534.8, 587.3, 692.3", \ + "706.8, 706.8, 706.8, 759.3, 864.4", \ + "1038.8, 1038.8, 1038.8, 1091.3, 1196.3", \ + "1690.4, 1690.4, 1690.4, 1743.0, 1848.0"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("686.3, 686.3, 686.3, 738.8, 843.8", \ + "846.6, 846.6, 846.6, 899.1, 1004.1", \ + "1157.7, 1157.7, 1157.7, 1210.2, 1315.2", \ + "1772.9, 1772.9, 1772.9, 1825.4, 1930.5", \ + "2995.8, 2995.8, 2995.8, 3048.3, 3153.3"); + } + } + } + } + + cell (o3_x2) { + area : 0.0 ; + cell_leakage_power : 1.9 ; + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 0.69 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2)) | (i1 & !(i2)))" ; + value : 0.76 ; + } + leakage_power () { + when : "(!((i0 & !(i1))) & i2)" ; + value : 1.9 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 4.4 ; + } + pin (i2) { + direction : input ; + capacitance : 4.76 ; + } + pin (i1) { + direction : input ; + capacitance : 4.76 ; + } + pin (i0) { + direction : input ; + capacitance : 4.75 ; + } + pin (q) { + function : "(i0 | i1 | i2)" ; + direction : output ; + capacitance : 2.61 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__44) { + values ("51.7, 51.7, 51.7, 56.9, 66.0", \ + "61.5, 61.5, 61.5, 66.9, 76.5", \ + "75.3, 75.3, 75.3, 80.8, 90.9", \ + "97.4, 97.4, 97.4, 103.1, 113.9", \ + "137.9, 137.9, 137.9, 143.6, 154.7"); + } + rise_transition (inslew_load_5x5__44) { + values ("32.2, 32.2, 32.2, 39.0, 52.3", \ + "44.9, 44.9, 44.9, 51.8, 65.2", \ + "68.0, 68.0, 68.0, 75.0, 88.6", \ + "112.5, 112.5, 112.5, 119.3, 133.0", \ + "199.4, 199.4, 199.4, 206.5, 220.4"); + } + cell_fall (inslew_load_5x5__44) { + values ("129.1, 129.1, 129.1, 134.7, 144.9", \ + "134.0, 134.0, 134.0, 139.6, 150.1", \ + "142.1, 142.1, 142.1, 147.8, 158.7", \ + "158.8, 158.8, 158.8, 164.5, 175.7", \ + "193.3, 193.3, 193.3, 199.1, 210.4"); + } + fall_transition (inslew_load_5x5__44) { + values ("79.0, 79.0, 79.0, 82.6, 89.5", \ + "94.0, 94.0, 94.0, 97.6, 104.5", \ + "122.3, 122.3, 122.3, 125.8, 132.8", \ + "178.1, 178.1, 178.1, 181.6, 188.7", \ + "290.2, 290.2, 290.2, 293.7, 300.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__44) { + values ("45.7, 45.7, 45.7, 50.8, 59.8", \ + "48.9, 48.9, 48.9, 54.1, 63.5", \ + "48.1, 48.1, 48.1, 53.5, 63.5", \ + "39.6, 39.6, 39.6, 45.2, 55.7", \ + "17.0, 17.0, 17.0, 22.7, 33.7"); + } + rise_transition (inslew_load_5x5__44) { + values ("28.9, 28.9, 28.9, 35.7, 49.0", \ + "38.8, 38.8, 38.8, 45.7, 59.0", \ + "56.2, 56.2, 56.2, 63.1, 76.6", \ + "88.5, 88.5, 88.5, 95.4, 109.1", \ + "151.2, 151.2, 151.2, 158.2, 171.9"); + } + cell_fall (inslew_load_5x5__44) { + values ("109.1, 109.1, 109.1, 114.6, 124.5", \ + "122.7, 122.7, 122.7, 128.3, 138.5", \ + "145.2, 145.2, 145.2, 150.9, 161.6", \ + "187.9, 187.9, 187.9, 193.6, 204.7", \ + "271.4, 271.4, 271.4, 277.2, 288.5"); + } + fall_transition (inslew_load_5x5__44) { + values ("64.0, 64.0, 64.0, 67.5, 74.4", \ + "80.3, 80.3, 80.3, 83.8, 90.7", \ + "110.6, 110.6, 110.6, 114.2, 121.1", \ + "170.8, 170.8, 170.8, 174.3, 181.4", \ + "291.2, 291.2, 291.2, 294.7, 301.6"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__44) { + values ("38.0, 38.0, 38.0, 43.0, 51.8", \ + "36.7, 36.7, 36.7, 41.8, 51.0", \ + "26.9, 26.9, 26.9, 32.2, 42.0", \ + "0.3, 0.3, 0.3, 5.8, 16.0", \ + "-59.8, -59.8, -59.8, -54.1, -43.2"); + } + rise_transition (inslew_load_5x5__44) { + values ("24.8, 24.8, 24.8, 31.7, 44.9", \ + "33.2, 33.2, 33.2, 40.1, 53.4", \ + "47.5, 47.5, 47.5, 54.3, 67.8", \ + "73.2, 73.2, 73.2, 80.1, 93.7", \ + "122.4, 122.4, 122.4, 129.3, 143.0"); + } + cell_fall (inslew_load_5x5__44) { + values ("83.5, 83.5, 83.5, 88.7, 98.5", \ + "103.4, 103.4, 103.4, 108.9, 118.8", \ + "136.8, 136.8, 136.8, 142.4, 153.0", \ + "198.0, 198.0, 198.0, 203.7, 214.8", \ + "317.0, 317.0, 317.0, 322.7, 334.1"); + } + fall_transition (inslew_load_5x5__44) { + values ("46.6, 46.6, 46.6, 50.2, 56.9", \ + "64.2, 64.2, 64.2, 67.7, 74.7", \ + "96.2, 96.2, 96.2, 99.8, 106.7", \ + "158.6, 158.6, 158.6, 162.1, 169.2", \ + "282.4, 282.4, 282.4, 285.9, 292.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__44) { + values ("321.6, 321.6, 321.6, 354.3, 419.6", \ + "413.4, 413.4, 413.4, 446.1, 511.5", \ + "592.5, 592.5, 592.5, 625.2, 690.6", \ + "947.1, 947.1, 947.1, 979.7, 1045.1", \ + "1653.3, 1653.3, 1653.3, 1686.0, 1751.4"); + } + fall_power (energy_inslew_load_5x5__44) { + values ("641.1, 641.1, 641.1, 673.8, 739.2", \ + "755.9, 755.9, 755.9, 788.6, 854.0", \ + "977.7, 977.7, 977.7, 1010.3, 1075.7", \ + "1418.8, 1418.8, 1418.8, 1451.4, 1516.8", \ + "2302.5, 2302.5, 2302.5, 2335.2, 2400.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__44) { + values ("276.9, 276.9, 276.9, 309.6, 375.0", \ + "336.6, 336.6, 336.6, 369.3, 434.7", \ + "451.1, 451.1, 451.1, 483.8, 549.1", \ + "674.7, 674.7, 674.7, 707.4, 772.8", \ + "1118.1, 1118.1, 1118.1, 1150.8, 1216.1"); + } + fall_power (energy_inslew_load_5x5__44) { + values ("524.3, 524.3, 524.3, 557.0, 622.3", \ + "644.5, 644.5, 644.5, 677.2, 742.5", \ + "875.3, 875.3, 875.3, 907.9, 973.3", \ + "1334.5, 1334.5, 1334.5, 1367.1, 1432.5", \ + "2253.5, 2253.5, 2253.5, 2286.1, 2351.5"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__44) { + values ("227.9, 227.9, 227.9, 260.6, 325.9", \ + "271.5, 271.5, 271.5, 304.1, 369.5", \ + "353.9, 353.9, 353.9, 386.5, 451.9", \ + "513.0, 513.0, 513.0, 545.7, 611.0", \ + "826.4, 826.4, 826.4, 859.0, 924.4"); + } + fall_power (energy_inslew_load_5x5__44) { + values ("390.8, 390.8, 390.8, 423.5, 488.8", \ + "514.2, 514.2, 514.2, 546.8, 612.2", \ + "748.4, 748.4, 748.4, 781.1, 846.4", \ + "1209.1, 1209.1, 1209.1, 1241.8, 1307.1", \ + "2127.3, 2127.3, 2127.3, 2160.0, 2225.3"); + } + } + } + } + + cell (o3_x4) { + area : 0.0 ; + cell_leakage_power : 2.2 ; + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 0.69 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2)) | (i1 & !(i2)))" ; + value : 0.76 ; + } + leakage_power () { + when : "(!((i0 & !(i1))) & i2)" ; + value : 1.9 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 5.4 ; + } + pin (i2) { + direction : input ; + capacitance : 5.80 ; + } + pin (i1) { + direction : input ; + capacitance : 5.82 ; + } + pin (i0) { + direction : input ; + capacitance : 5.81 ; + } + pin (q) { + function : "(i0 | i1 | i2)" ; + direction : output ; + capacitance : 4.20 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("37.0, 37.0, 37.0, 41.3, 48.7", \ + "37.1, 37.1, 37.1, 41.3, 49.1", \ + "30.5, 30.5, 30.5, 34.8, 43.0", \ + "10.7, 10.7, 10.7, 15.1, 23.7", \ + "-35.3, -35.3, -35.3, -30.7, -21.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("24.7, 24.7, 24.7, 30.2, 40.9", \ + "33.6, 33.6, 33.6, 39.2, 50.0", \ + "49.1, 49.1, 49.1, 54.7, 65.5", \ + "77.5, 77.5, 77.5, 83.0, 94.0", \ + "132.2, 132.2, 132.2, 137.8, 148.8"); + } + cell_fall (inslew_load_5x5__21) { + values ("190.8, 190.8, 190.8, 195.4, 204.3", \ + "220.8, 220.8, 220.8, 225.4, 234.4", \ + "272.9, 272.9, 272.9, 277.5, 286.5", \ + "374.6, 374.6, 374.6, 379.3, 388.4", \ + "578.7, 578.7, 578.7, 582.8, 592.0"); + } + fall_transition (inslew_load_5x5__21) { + values ("114.4, 114.4, 114.4, 117.2, 122.8", \ + "144.1, 144.1, 144.1, 146.9, 152.5", \ + "198.7, 198.7, 198.7, 201.5, 207.0", \ + "305.3, 305.3, 305.3, 308.1, 313.7", \ + "516.9, 516.9, 516.9, 520.0, 525.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("33.8, 33.8, 33.8, 38.0, 45.4", \ + "29.9, 29.9, 29.9, 34.2, 41.8", \ + "14.1, 14.1, 14.1, 18.4, 26.4", \ + "-27.2, -27.2, -27.2, -22.7, -14.4", \ + "-119.1, -119.1, -119.1, -114.5, -105.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("23.0, 23.0, 23.0, 28.5, 39.3", \ + "30.4, 30.4, 30.4, 35.9, 46.7", \ + "42.4, 42.4, 42.4, 47.9, 58.7", \ + "63.2, 63.2, 63.2, 68.7, 79.7", \ + "101.7, 101.7, 101.7, 107.2, 118.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("161.1, 161.1, 161.1, 165.7, 174.3", \ + "198.2, 198.2, 198.2, 202.8, 211.7", \ + "258.3, 258.3, 258.3, 263.0, 272.0", \ + "372.8, 372.8, 372.8, 377.4, 386.5", \ + "599.4, 599.4, 599.4, 603.7, 612.9"); + } + fall_transition (inslew_load_5x5__21) { + values ("93.6, 93.6, 93.6, 96.4, 101.9", \ + "123.6, 123.6, 123.6, 126.4, 132.0", \ + "175.3, 175.3, 175.3, 178.1, 183.7", \ + "275.4, 275.4, 275.4, 278.2, 283.7", \ + "473.8, 473.8, 473.8, 476.9, 482.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("30.2, 30.2, 30.2, 34.4, 41.6", \ + "23.8, 23.8, 23.8, 28.1, 35.6", \ + "3.1, 3.1, 3.1, 7.5, 15.3", \ + "-48.9, -48.9, -48.9, -44.5, -36.3", \ + "-164.2, -164.2, -164.2, -159.7, -151.1"); + } + rise_transition (inslew_load_5x5__21) { + values ("21.1, 21.1, 21.1, 26.7, 37.4", \ + "27.7, 27.7, 27.7, 33.2, 44.0", \ + "38.1, 38.1, 38.1, 43.6, 54.4", \ + "55.1, 55.1, 55.1, 60.7, 71.6", \ + "85.8, 85.8, 85.8, 91.3, 102.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("129.1, 129.1, 129.1, 133.7, 142.0", \ + "170.7, 170.7, 170.7, 175.3, 184.1", \ + "237.4, 237.4, 237.4, 242.0, 251.1", \ + "360.7, 360.7, 360.7, 365.3, 374.4", \ + "601.0, 601.0, 601.0, 605.5, 614.7"); + } + fall_transition (inslew_load_5x5__21) { + values ("72.1, 72.1, 72.1, 74.9, 80.4", \ + "101.5, 101.5, 101.5, 104.3, 109.8", \ + "151.4, 151.4, 151.4, 154.2, 159.8", \ + "246.7, 246.7, 246.7, 249.5, 255.0", \ + "434.9, 434.9, 434.9, 437.8, 443.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("459.3, 459.3, 459.3, 511.8, 616.8", \ + "556.4, 556.4, 556.4, 608.9, 713.9", \ + "741.5, 741.5, 741.5, 794.0, 899.0", \ + "1101.5, 1101.5, 1101.5, 1154.0, 1259.0", \ + "1813.7, 1813.7, 1813.7, 1866.2, 1971.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1424.8, 1424.8, 1424.8, 1477.3, 1582.4", \ + "1772.0, 1772.0, 1772.0, 1824.5, 1929.5", \ + "2426.3, 2426.3, 2426.3, 2478.8, 2583.9", \ + "3713.0, 3713.0, 3713.0, 3765.5, 3870.5", \ + "6276.0, 6276.0, 6276.0, 6328.5, 6433.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("420.3, 420.3, 420.3, 472.8, 577.8", \ + "484.7, 484.7, 484.7, 537.2, 642.3", \ + "602.2, 602.2, 602.2, 654.7, 759.7", \ + "822.6, 822.6, 822.6, 875.1, 980.1", \ + "1248.0, 1248.0, 1248.0, 1300.6, 1405.6"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1186.0, 1186.0, 1186.0, 1238.6, 1343.6", \ + "1526.6, 1526.6, 1526.6, 1579.1, 1684.1", \ + "2137.8, 2137.8, 2137.8, 2190.3, 2295.3", \ + "3330.7, 3330.7, 3330.7, 3383.2, 3488.3", \ + "5704.0, 5704.0, 5704.0, 5756.5, 5861.5"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("378.7, 378.7, 378.7, 431.2, 536.2", \ + "429.3, 429.3, 429.3, 481.8, 586.8", \ + "518.3, 518.3, 518.3, 570.8, 675.9", \ + "679.1, 679.1, 679.1, 731.6, 836.6", \ + "983.0, 983.0, 983.0, 1035.5, 1140.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("936.7, 936.7, 936.7, 989.2, 1094.2", \ + "1262.3, 1262.3, 1262.3, 1314.8, 1419.8", \ + "1838.6, 1838.6, 1838.6, 1891.1, 1996.1", \ + "2952.1, 2952.1, 2952.1, 3004.6, 3109.6", \ + "5160.3, 5160.3, 5160.3, 5212.8, 5317.8"); + } + } + } + } + + cell (o4_x2) { + area : 0.0 ; + cell_leakage_power : 1.7 ; + leakage_power () { + when : "((i0 & (i1 ^ i3)) | (!(i0) & i1 & !((i2 ^ i3))))" ; + value : 0.76 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i3)) | (!(i0) & ((i1 & i2 & !(i3)) | (!(i1) & i2 & i3))))" ; + value : 0.69 ; + } + leakage_power () { + when : "(!(i3) & i2 & !(i1) & !(i0))" ; + value : 0.66 ; + } + leakage_power () { + when : "((i0 & i1 & i3) | (!(i0) & !(i2) & i3))" ; + value : 1.9 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 4.4 ; + } + pin (i3) { + direction : input ; + capacitance : 4.82 ; + } + pin (i2) { + direction : input ; + capacitance : 4.75 ; + } + pin (i1) { + direction : input ; + capacitance : 4.81 ; + } + pin (i0) { + direction : input ; + capacitance : 4.77 ; + } + pin (q) { + function : "(i2 | i0 | i1 | i3)" ; + direction : output ; + capacitance : 2.60 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("49.6, 49.6, 49.6, 54.7, 63.8", \ + "53.3, 53.3, 53.3, 58.5, 68.0", \ + "53.3, 53.3, 53.3, 58.6, 68.6", \ + "45.4, 45.4, 45.4, 50.9, 61.5", \ + "23.2, 23.2, 23.2, 28.9, 39.9"); + } + rise_transition (inslew_load_5x5__43) { + values ("30.9, 30.9, 30.9, 37.7, 51.0", \ + "40.8, 40.8, 40.8, 47.6, 60.9", \ + "58.2, 58.2, 58.2, 65.1, 78.6", \ + "90.6, 90.6, 90.6, 97.5, 111.1", \ + "153.2, 153.2, 153.2, 160.2, 173.9"); + } + cell_fall (inslew_load_5x5__43) { + values ("180.0, 180.0, 180.0, 185.6, 196.2", \ + "199.1, 199.1, 199.1, 204.8, 215.6", \ + "229.4, 229.4, 229.4, 235.0, 246.1", \ + "287.6, 287.6, 287.6, 293.3, 304.5", \ + "404.0, 404.0, 404.0, 409.7, 421.1"); + } + fall_transition (inslew_load_5x5__43) { + values ("103.4, 103.4, 103.4, 107.0, 113.9", \ + "124.8, 124.8, 124.8, 128.3, 135.3", \ + "163.1, 163.1, 163.1, 166.6, 173.7", \ + "237.3, 237.3, 237.3, 240.8, 247.8", \ + "385.4, 385.4, 385.4, 389.0, 395.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("45.3, 45.3, 45.3, 50.4, 59.3", \ + "45.4, 45.4, 45.4, 50.6, 59.9", \ + "37.4, 37.4, 37.4, 42.7, 52.5", \ + "12.5, 12.5, 12.5, 18.0, 28.2", \ + "-46.3, -46.3, -46.3, -40.6, -29.7"); + } + rise_transition (inslew_load_5x5__43) { + values ("28.6, 28.6, 28.6, 35.4, 48.6", \ + "37.1, 37.1, 37.1, 43.9, 57.2", \ + "51.5, 51.5, 51.5, 58.4, 71.8", \ + "77.6, 77.6, 77.6, 84.5, 98.1", \ + "127.0, 127.0, 127.0, 133.9, 147.5"); + } + cell_fall (inslew_load_5x5__43) { + values ("145.7, 145.7, 145.7, 151.3, 161.6", \ + "169.6, 169.6, 169.6, 175.2, 185.8", \ + "209.1, 209.1, 209.1, 214.8, 225.8", \ + "282.8, 282.8, 282.8, 288.6, 299.7", \ + "428.1, 428.1, 428.1, 433.9, 445.2"); + } + fall_transition (inslew_load_5x5__43) { + values ("82.1, 82.1, 82.1, 85.7, 92.6", \ + "103.7, 103.7, 103.7, 107.3, 114.2", \ + "142.3, 142.3, 142.3, 145.8, 152.9", \ + "216.9, 216.9, 216.9, 220.3, 227.4", \ + "365.6, 365.6, 365.6, 369.1, 376.0"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("54.6, 54.6, 54.6, 59.7, 68.9", \ + "64.7, 64.7, 64.7, 70.0, 79.7", \ + "78.8, 78.8, 78.8, 84.2, 94.4", \ + "101.0, 101.0, 101.0, 106.6, 117.4", \ + "141.5, 141.5, 141.5, 147.2, 158.3"); + } + rise_transition (inslew_load_5x5__43) { + values ("33.7, 33.7, 33.7, 40.5, 53.7", \ + "46.3, 46.3, 46.3, 53.1, 66.5", \ + "69.4, 69.4, 69.4, 76.3, 89.9", \ + "113.8, 113.8, 113.8, 120.6, 134.2", \ + "200.5, 200.5, 200.5, 207.6, 221.5"); + } + cell_fall (inslew_load_5x5__43) { + values ("208.5, 208.5, 208.5, 214.1, 224.9", \ + "219.7, 219.7, 219.7, 225.4, 236.4", \ + "238.2, 238.2, 238.2, 243.9, 255.0", \ + "274.7, 274.7, 274.7, 280.4, 291.6", \ + "349.2, 349.2, 349.2, 355.0, 366.3"); + } + fall_transition (inslew_load_5x5__43) { + values ("122.2, 122.2, 122.2, 125.8, 132.8", \ + "141.9, 141.9, 141.9, 145.4, 152.5", \ + "179.2, 179.2, 179.2, 182.7, 189.8", \ + "251.9, 251.9, 251.9, 255.3, 262.4", \ + "396.1, 396.1, 396.1, 399.7, 406.6"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("38.4, 38.4, 38.4, 43.4, 52.1", \ + "35.3, 35.3, 35.3, 40.4, 49.6", \ + "21.3, 21.3, 21.3, 26.6, 36.2", \ + "-15.6, -15.6, -15.6, -10.2, -0.1", \ + "-98.4, -98.4, -98.4, -92.8, -82.1"); + } + rise_transition (inslew_load_5x5__43) { + values ("25.0, 25.0, 25.0, 31.8, 44.9", \ + "32.5, 32.5, 32.5, 39.3, 52.5", \ + "45.0, 45.0, 45.0, 51.8, 65.2", \ + "67.0, 67.0, 67.0, 73.9, 87.4", \ + "108.0, 108.0, 108.0, 114.9, 128.5"); + } + cell_fall (inslew_load_5x5__43) { + values ("109.3, 109.3, 109.3, 114.7, 124.5", \ + "135.3, 135.3, 135.3, 140.9, 151.1", \ + "181.3, 181.3, 181.3, 186.9, 197.7", \ + "267.5, 267.5, 267.5, 273.2, 284.4", \ + "434.2, 434.2, 434.2, 439.9, 451.2"); + } + fall_transition (inslew_load_5x5__43) { + values ("60.2, 60.2, 60.2, 63.7, 70.6", \ + "81.1, 81.1, 81.1, 84.6, 91.5", \ + "119.7, 119.7, 119.7, 123.2, 130.2", \ + "194.9, 194.9, 194.9, 198.4, 205.5", \ + "341.7, 341.7, 341.7, 345.3, 352.2"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__43) { + values ("301.0, 301.0, 301.0, 333.5, 398.5", \ + "360.9, 360.9, 360.9, 393.4, 458.4", \ + "475.9, 475.9, 475.9, 508.4, 573.5", \ + "700.2, 700.2, 700.2, 732.7, 797.7", \ + "1143.9, 1143.9, 1143.9, 1176.4, 1241.4"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("755.9, 755.9, 755.9, 788.4, 853.4", \ + "898.8, 898.8, 898.8, 931.3, 996.3", \ + "1165.1, 1165.1, 1165.1, 1197.7, 1262.7", \ + "1687.7, 1687.7, 1687.7, 1720.2, 1785.2", \ + "2731.4, 2731.4, 2731.4, 2763.9, 2828.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__43) { + values ("271.1, 271.1, 271.1, 303.6, 368.6", \ + "315.9, 315.9, 315.9, 348.4, 413.4", \ + "399.5, 399.5, 399.5, 432.0, 497.0", \ + "560.2, 560.2, 560.2, 592.7, 657.7", \ + "874.7, 874.7, 874.7, 907.2, 972.2"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("608.3, 608.3, 608.3, 640.8, 705.8", \ + "750.0, 750.0, 750.0, 782.5, 847.5", \ + "1013.6, 1013.6, 1013.6, 1046.1, 1111.2", \ + "1530.0, 1530.0, 1530.0, 1562.5, 1627.5", \ + "2560.7, 2560.7, 2560.7, 2593.2, 2658.2"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__43) { + values ("340.2, 340.2, 340.2, 372.7, 437.7", \ + "432.0, 432.0, 432.0, 464.5, 529.5", \ + "611.3, 611.3, 611.3, 643.8, 708.9", \ + "966.0, 966.0, 966.0, 998.6, 1063.6", \ + "1672.5, 1672.5, 1672.5, 1705.0, 1770.0"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("884.9, 884.9, 884.9, 917.4, 982.4", \ + "1020.4, 1020.4, 1020.4, 1052.9, 1117.9", \ + "1282.8, 1282.8, 1282.8, 1315.3, 1380.4", \ + "1799.0, 1799.0, 1799.0, 1831.5, 1896.5", \ + "2826.5, 2826.5, 2826.5, 2859.0, 2924.0"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__43) { + values ("228.2, 228.2, 228.2, 260.7, 325.7", \ + "263.7, 263.7, 263.7, 296.2, 361.2", \ + "329.2, 329.2, 329.2, 361.7, 426.7", \ + "453.4, 453.4, 453.4, 485.9, 550.9", \ + "694.2, 694.2, 694.2, 726.7, 791.7"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("455.0, 455.0, 455.0, 487.5, 552.5", \ + "591.0, 591.0, 591.0, 623.5, 688.5", \ + "849.6, 849.6, 849.6, 882.1, 947.1", \ + "1358.0, 1358.0, 1358.0, 1390.5, 1455.5", \ + "2359.2, 2359.2, 2359.2, 2391.7, 2456.8"); + } + } + } + } + + cell (o4_x4) { + area : 0.0 ; + cell_leakage_power : 3.4 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 4.4 ; + } + leakage_power () { + when : "((i0 & (i1 ^ (i2 | !(i3)))) | (!(i0) & i1 & i2))" ; + value : 1.5 ; + } + leakage_power () { + when : "((i0 & i1 & !(i3)) | (i1 & !(i2) & !(i3)))" ; + value : 4.5 ; + } + leakage_power () { + when : "((!(i0) & ((!(i1) & (i2 | i3)) | (!(i2) & i3))) | (!(i1) & !(i2) & i3))" ; + value : 1.3 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.4 ; + } + pin (i3) { + direction : input ; + capacitance : 6.66 ; + } + pin (i2) { + direction : input ; + capacitance : 6.82 ; + } + pin (i1) { + direction : input ; + capacitance : 6.79 ; + } + pin (i0) { + direction : input ; + capacitance : 6.79 ; + } + pin (q) { + function : "(i3 | i2 | i0 | i1)" ; + direction : output ; + capacitance : 4.23 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__45) { + values ("36.9, 36.9, 36.9, 41.2, 48.6", \ + "33.8, 33.8, 33.8, 38.1, 45.9", \ + "19.2, 19.2, 19.2, 23.5, 31.6", \ + "-19.6, -19.6, -19.6, -15.1, -6.8", \ + "-107.3, -107.3, -107.3, -102.6, -93.8"); + } + rise_transition (inslew_load_5x5__45) { + values ("24.3, 24.3, 24.3, 29.9, 40.7", \ + "31.7, 31.7, 31.7, 37.3, 48.1", \ + "44.1, 44.1, 44.1, 49.6, 60.6", \ + "65.5, 65.5, 65.5, 71.1, 82.2", \ + "105.4, 105.4, 105.4, 111.0, 122.1"); + } + cell_fall (inslew_load_5x5__45) { + values ("157.0, 157.0, 157.0, 161.6, 170.3", \ + "190.7, 190.7, 190.7, 195.3, 204.3", \ + "245.9, 245.9, 245.9, 250.6, 259.7", \ + "350.2, 350.2, 350.2, 354.9, 364.1", \ + "554.2, 554.2, 554.2, 558.5, 567.8"); + } + fall_transition (inslew_load_5x5__45) { + values ("94.6, 94.6, 94.6, 97.4, 103.0", \ + "123.1, 123.1, 123.1, 125.9, 131.6", \ + "172.6, 172.6, 172.6, 175.5, 181.1", \ + "268.3, 268.3, 268.3, 271.1, 276.7", \ + "458.1, 458.1, 458.1, 461.2, 466.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__45) { + values ("32.4, 32.4, 32.4, 36.6, 43.9", \ + "27.0, 27.0, 27.0, 31.2, 38.9", \ + "7.9, 7.9, 7.9, 12.3, 20.2", \ + "-40.5, -40.5, -40.5, -36.0, -27.7", \ + "-147.7, -147.7, -147.7, -143.1, -134.3"); + } + rise_transition (inslew_load_5x5__45) { + values ("21.9, 21.9, 21.9, 27.5, 38.3", \ + "28.7, 28.7, 28.7, 34.3, 45.1", \ + "39.6, 39.6, 39.6, 45.2, 56.1", \ + "57.9, 57.9, 57.9, 63.5, 74.5", \ + "91.1, 91.1, 91.1, 96.6, 107.8"); + } + cell_fall (inslew_load_5x5__45) { + values ("124.9, 124.9, 124.9, 129.5, 138.0", \ + "160.0, 160.0, 160.0, 164.6, 173.4", \ + "220.5, 220.5, 220.5, 225.2, 234.3", \ + "333.8, 333.8, 333.8, 338.5, 347.7", \ + "553.5, 553.5, 553.5, 558.0, 567.3"); + } + fall_transition (inslew_load_5x5__45) { + values ("73.5, 73.5, 73.5, 76.4, 82.0", \ + "100.4, 100.4, 100.4, 103.2, 108.9", \ + "148.9, 148.9, 148.9, 151.8, 157.4", \ + "242.5, 242.5, 242.5, 245.3, 250.9", \ + "426.8, 426.8, 426.8, 429.8, 435.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__45) { + values ("39.8, 39.8, 39.8, 44.1, 51.6", \ + "39.3, 39.3, 39.3, 43.7, 51.5", \ + "30.9, 30.9, 30.9, 35.2, 43.5", \ + "6.2, 6.2, 6.2, 10.7, 19.3", \ + "-51.0, -51.0, -51.0, -46.3, -37.3"); + } + rise_transition (inslew_load_5x5__45) { + values ("25.7, 25.7, 25.7, 31.3, 42.1", \ + "34.2, 34.2, 34.2, 39.8, 50.7", \ + "48.8, 48.8, 48.8, 54.4, 65.4", \ + "75.4, 75.4, 75.4, 80.9, 92.1", \ + "125.8, 125.8, 125.8, 131.5, 142.5"); + } + cell_fall (inslew_load_5x5__45) { + values ("189.1, 189.1, 189.1, 193.7, 202.6", \ + "218.5, 218.5, 218.5, 223.2, 232.3", \ + "267.1, 267.1, 267.1, 271.7, 280.9", \ + "360.3, 360.3, 360.3, 365.0, 374.2", \ + "546.5, 546.5, 546.5, 550.7, 560.0"); + } + fall_transition (inslew_load_5x5__45) { + values ("116.1, 116.1, 116.1, 118.9, 124.6", \ + "145.0, 145.0, 145.0, 147.8, 153.5", \ + "196.3, 196.3, 196.3, 199.1, 204.7", \ + "295.8, 295.8, 295.8, 298.6, 304.2", \ + "493.3, 493.3, 493.3, 496.5, 502.1"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__45) { + values ("43.9, 43.9, 43.9, 48.1, 55.7", \ + "48.9, 48.9, 48.9, 53.3, 61.2", \ + "53.2, 53.2, 53.2, 57.6, 66.0", \ + "56.0, 56.0, 56.0, 60.6, 69.4", \ + "57.3, 57.3, 57.3, 61.9, 71.0"); + } + rise_transition (inslew_load_5x5__45) { + values ("27.9, 27.9, 27.9, 33.4, 44.3", \ + "38.7, 38.7, 38.7, 44.3, 55.2", \ + "58.2, 58.2, 58.2, 63.8, 74.8", \ + "95.1, 95.1, 95.1, 100.7, 111.8", \ + "167.0, 167.0, 167.0, 172.8, 184.0"); + } + cell_fall (inslew_load_5x5__45) { + values ("216.5, 216.5, 216.5, 221.1, 230.1", \ + "238.3, 238.3, 238.3, 243.0, 252.1", \ + "276.9, 276.9, 276.9, 281.6, 290.8", \ + "352.9, 352.9, 352.9, 357.6, 366.9", \ + "506.5, 506.5, 506.5, 510.7, 519.9"); + } + fall_transition (inslew_load_5x5__45) { + values ("135.7, 135.7, 135.7, 138.5, 144.3", \ + "163.0, 163.0, 163.0, 165.9, 171.5", \ + "214.8, 214.8, 214.8, 217.6, 223.2", \ + "316.3, 316.3, 316.3, 319.1, 324.7", \ + "517.5, 517.5, 517.5, 520.7, 526.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__45) { + values ("448.0, 448.0, 448.0, 500.9, 606.7", \ + "515.2, 515.2, 515.2, 568.1, 674.0", \ + "638.6, 638.6, 638.6, 691.6, 797.4", \ + "870.6, 870.6, 870.6, 923.5, 1029.3", \ + "1318.7, 1318.7, 1318.7, 1371.7, 1477.5"); + } + fall_power (energy_inslew_load_5x5__45) { + values ("1228.6, 1228.6, 1228.6, 1281.5, 1387.4", \ + "1559.9, 1559.9, 1559.9, 1612.9, 1718.7", \ + "2158.8, 2158.8, 2158.8, 2211.8, 2317.6", \ + "3326.4, 3326.4, 3326.4, 3379.3, 3485.2", \ + "5651.3, 5651.3, 5651.3, 5704.2, 5810.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__45) { + values ("395.9, 395.9, 395.9, 448.8, 554.7", \ + "450.9, 450.9, 450.9, 503.8, 609.6", \ + "549.4, 549.4, 549.4, 602.3, 708.2", \ + "729.9, 729.9, 729.9, 782.9, 888.7", \ + "1073.3, 1073.3, 1073.3, 1126.3, 1232.1"); + } + fall_power (energy_inslew_load_5x5__45) { + values ("971.0, 971.0, 971.0, 1023.9, 1129.8", \ + "1281.2, 1281.2, 1281.2, 1334.1, 1440.0", \ + "1856.7, 1856.7, 1856.7, 1909.7, 2015.5", \ + "2978.4, 2978.4, 2978.4, 3031.3, 3137.1", \ + "5199.3, 5199.3, 5199.3, 5252.2, 5358.1"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__45) { + values ("482.9, 482.9, 482.9, 535.8, 641.6", \ + "571.7, 571.7, 571.7, 624.6, 730.5", \ + "739.2, 739.2, 739.2, 792.1, 897.9", \ + "1062.7, 1062.7, 1062.7, 1115.6, 1221.4", \ + "1697.5, 1697.5, 1697.5, 1750.4, 1856.2"); + } + fall_power (energy_inslew_load_5x5__45) { + values ("1489.5, 1489.5, 1489.5, 1542.4, 1648.2", \ + "1831.1, 1831.1, 1831.1, 1884.0, 1989.8", \ + "2459.3, 2459.3, 2459.3, 2512.2, 2618.1", \ + "3689.1, 3689.1, 3689.1, 3742.0, 3847.8", \ + "6140.0, 6140.0, 6140.0, 6193.0, 6298.8"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__45) { + values ("538.6, 538.6, 538.6, 591.5, 697.4", \ + "677.7, 677.7, 677.7, 730.6, 836.5", \ + "948.5, 948.5, 948.5, 1001.4, 1107.2", \ + "1481.7, 1481.7, 1481.7, 1534.6, 1640.4", \ + "2542.2, 2542.2, 2542.2, 2595.1, 2701.0"); + } + fall_power (energy_inslew_load_5x5__45) { + values ("1722.5, 1722.5, 1722.5, 1775.4, 1881.3", \ + "2055.2, 2055.2, 2055.2, 2108.2, 2214.0", \ + "2695.8, 2695.8, 2695.8, 2748.7, 2854.5", \ + "3959.2, 3959.2, 3959.2, 4012.1, 4117.9", \ + "6474.5, 6474.5, 6474.5, 6527.4, 6633.3"); + } + } + } + } + + cell (oa22_x2) { + area : 0.0 ; + cell_leakage_power : 2.2 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 2 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 1.5 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 0.89 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !(i2))" ; + value : 4.4 ; + } + pin (i2) { + direction : input ; + capacitance : 5.17 ; + } + pin (i1) { + direction : input ; + capacitance : 4.83 ; + } + pin (i0) { + direction : input ; + capacitance : 5.04 ; + } + pin (q) { + function : "((i0 & (i2 | i1)) | i2)" ; + direction : output ; + capacitance : 2.60 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("28.7, 28.7, 28.7, 33.7, 42.4", \ + "20.2, 20.2, 20.2, 25.3, 34.3", \ + "-3.0, -3.0, -3.0, 2.3, 11.7", \ + "-57.2, -57.2, -57.2, -51.8, -41.9", \ + "-174.0, -174.0, -174.0, -168.5, -158.1"); + } + rise_transition (inslew_load_5x5__43) { + values ("24.9, 24.9, 24.9, 31.7, 44.8", \ + "30.1, 30.1, 30.1, 36.9, 50.1", \ + "38.8, 38.8, 38.8, 45.6, 58.9", \ + "54.2, 54.2, 54.2, 61.0, 74.5", \ + "82.5, 82.5, 82.5, 89.4, 103.0"); + } + cell_fall (inslew_load_5x5__43) { + values ("95.2, 95.2, 95.2, 100.5, 110.2", \ + "130.8, 130.8, 130.8, 136.4, 146.6", \ + "191.1, 191.1, 191.1, 196.8, 207.6", \ + "304.4, 304.4, 304.4, 310.1, 321.3", \ + "526.4, 526.4, 526.4, 532.2, 543.5"); + } + fall_transition (inslew_load_5x5__43) { + values ("53.9, 53.9, 53.9, 57.4, 64.3", \ + "79.7, 79.7, 79.7, 83.3, 90.1", \ + "125.4, 125.4, 125.4, 128.9, 135.9", \ + "213.7, 213.7, 213.7, 217.1, 224.2", \ + "388.4, 388.4, 388.4, 392.0, 398.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("26.1, 26.1, 26.1, 31.0, 39.6", \ + "19.4, 19.4, 19.4, 24.4, 33.3", \ + "-0.1, -0.1, -0.1, 5.1, 14.5", \ + "-45.8, -45.8, -45.8, -40.4, -30.5", \ + "-143.5, -143.5, -143.5, -138.0, -127.5"); + } + rise_transition (inslew_load_5x5__43) { + values ("21.3, 21.3, 21.3, 28.1, 41.2", \ + "27.5, 27.5, 27.5, 34.3, 47.4", \ + "37.7, 37.7, 37.7, 44.5, 57.8", \ + "55.8, 55.8, 55.8, 62.7, 76.1", \ + "89.9, 89.9, 89.9, 96.8, 110.4"); + } + cell_fall (inslew_load_5x5__43) { + values ("78.8, 78.8, 78.8, 84.0, 93.7", \ + "108.1, 108.1, 108.1, 113.5, 123.4", \ + "156.5, 156.5, 156.5, 162.1, 172.7", \ + "246.8, 246.8, 246.8, 252.5, 263.6", \ + "423.8, 423.8, 423.8, 429.5, 440.8"); + } + fall_transition (inslew_load_5x5__43) { + values ("44.0, 44.0, 44.0, 47.5, 54.2", \ + "66.5, 66.5, 66.5, 70.0, 76.9", \ + "105.8, 105.8, 105.8, 109.3, 116.2", \ + "182.0, 182.0, 182.0, 185.5, 192.6", \ + "333.0, 333.0, 333.0, 336.5, 343.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("24.0, 24.0, 24.0, 29.0, 37.4", \ + "19.1, 19.1, 19.1, 24.1, 33.0", \ + "3.5, 3.5, 3.5, 8.7, 18.1", \ + "-33.4, -33.4, -33.4, -28.0, -17.9", \ + "-112.0, -112.0, -112.0, -106.4, -95.7"); + } + rise_transition (inslew_load_5x5__43) { + values ("19.0, 19.0, 19.0, 25.9, 38.9", \ + "26.7, 26.7, 26.7, 33.5, 46.6", \ + "39.3, 39.3, 39.3, 46.1, 59.4", \ + "61.8, 61.8, 61.8, 68.7, 82.2", \ + "105.1, 105.1, 105.1, 111.9, 125.5"); + } + cell_fall (inslew_load_5x5__43) { + values ("102.0, 102.0, 102.0, 107.4, 117.2", \ + "129.5, 129.5, 129.5, 135.1, 145.4", \ + "178.7, 178.7, 178.7, 184.3, 195.2", \ + "273.8, 273.8, 273.8, 279.5, 290.7", \ + "463.2, 463.2, 463.2, 469.0, 480.3"); + } + fall_transition (inslew_load_5x5__43) { + values ("62.9, 62.9, 62.9, 66.4, 73.3", \ + "88.3, 88.3, 88.3, 91.8, 98.7", \ + "135.4, 135.4, 135.4, 138.9, 145.9", \ + "227.9, 227.9, 227.9, 231.4, 238.4", \ + "412.3, 412.3, 412.3, 415.8, 422.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__43) { + values ("267.3, 267.3, 267.3, 299.8, 364.8", \ + "295.9, 295.9, 295.9, 328.5, 393.5", \ + "349.5, 349.5, 349.5, 382.0, 447.0", \ + "452.2, 452.2, 452.2, 484.7, 549.7", \ + "652.1, 652.1, 652.1, 684.6, 749.7"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("482.7, 482.7, 482.7, 515.2, 580.3", \ + "669.0, 669.0, 669.0, 701.5, 766.5", \ + "1015.6, 1015.6, 1015.6, 1048.1, 1113.1", \ + "1696.1, 1696.1, 1696.1, 1728.6, 1793.7", \ + "3049.6, 3049.6, 3049.6, 3082.1, 3147.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__43) { + values ("214.1, 214.1, 214.1, 246.6, 311.6", \ + "247.3, 247.3, 247.3, 279.8, 344.8", \ + "309.8, 309.8, 309.8, 342.3, 407.3", \ + "430.6, 430.6, 430.6, 463.2, 528.2", \ + "668.3, 668.3, 668.3, 700.9, 765.9"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("394.9, 394.9, 394.9, 427.4, 492.4", \ + "554.5, 554.5, 554.5, 587.0, 652.0", \ + "849.9, 849.9, 849.9, 882.5, 947.5", \ + "1431.0, 1431.0, 1431.0, 1463.5, 1528.5", \ + "2586.6, 2586.6, 2586.6, 2619.1, 2684.1"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__43) { + values ("247.3, 247.3, 247.3, 279.9, 344.9", \ + "297.1, 297.1, 297.1, 329.6, 394.7", \ + "393.2, 393.2, 393.2, 425.7, 490.7", \ + "581.0, 581.0, 581.0, 613.5, 678.5", \ + "953.6, 953.6, 953.6, 986.1, 1051.1"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("547.1, 547.1, 547.1, 579.6, 644.6", \ + "744.3, 744.3, 744.3, 776.8, 841.8", \ + "1122.8, 1122.8, 1122.8, 1155.3, 1220.3", \ + "1872.9, 1872.9, 1872.9, 1905.4, 1970.4", \ + "3370.3, 3370.3, 3370.3, 3402.8, 3467.8"); + } + } + } + } + + cell (oa22_x4) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 2 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 1.5 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 0.89 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !(i2))" ; + value : 5.4 ; + } + pin (i2) { + direction : input ; + capacitance : 5.17 ; + } + pin (i1) { + direction : input ; + capacitance : 4.93 ; + } + pin (i0) { + direction : input ; + capacitance : 4.96 ; + } + pin (q) { + function : "((i0 & (i2 | i1)) | i2)" ; + direction : output ; + capacitance : 4.20 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("39.5, 39.5, 39.5, 43.8, 51.5", \ + "33.0, 33.0, 33.0, 37.3, 45.1", \ + "12.9, 12.9, 12.9, 17.3, 25.4", \ + "-37.5, -37.5, -37.5, -33.1, -24.8", \ + "-150.4, -150.4, -150.4, -145.8, -137.2"); + } + rise_transition (inslew_load_5x5__21) { + values ("31.4, 31.4, 31.4, 36.9, 47.7", \ + "36.6, 36.6, 36.6, 42.2, 53.0", \ + "45.9, 45.9, 45.9, 51.4, 62.2", \ + "62.0, 62.0, 62.0, 67.6, 78.5", \ + "91.4, 91.4, 91.4, 96.9, 107.9"); + } + cell_fall (inslew_load_5x5__21) { + values ("128.3, 128.3, 128.3, 132.9, 141.3", \ + "165.2, 165.2, 165.2, 169.8, 178.5", \ + "227.4, 227.4, 227.4, 232.0, 241.0", \ + "343.5, 343.5, 343.5, 348.1, 357.2", \ + "570.0, 570.0, 570.0, 574.5, 583.7"); + } + fall_transition (inslew_load_5x5__21) { + values ("75.8, 75.8, 75.8, 78.6, 84.1", \ + "102.0, 102.0, 102.0, 104.7, 110.2", \ + "149.1, 149.1, 149.1, 151.9, 157.4", \ + "239.4, 239.4, 239.4, 242.1, 247.6", \ + "418.9, 418.9, 418.9, 421.7, 427.2"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("38.9, 38.9, 38.9, 43.1, 50.7", \ + "34.9, 34.9, 34.9, 39.3, 47.0", \ + "19.2, 19.2, 19.2, 23.5, 31.6", \ + "-22.4, -22.4, -22.4, -17.9, -9.6", \ + "-116.3, -116.3, -116.3, -111.7, -103.0"); + } + rise_transition (inslew_load_5x5__21) { + values ("28.4, 28.4, 28.4, 33.9, 44.7", \ + "34.8, 34.8, 34.8, 40.3, 51.1", \ + "45.6, 45.6, 45.6, 51.2, 62.0", \ + "64.6, 64.6, 64.6, 70.1, 81.1", \ + "99.8, 99.8, 99.8, 105.3, 116.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("112.4, 112.4, 112.4, 116.9, 125.0", \ + "142.8, 142.8, 142.8, 147.4, 156.0", \ + "193.4, 193.4, 193.4, 198.0, 206.9", \ + "286.6, 286.6, 286.6, 291.2, 300.3", \ + "467.4, 467.4, 467.4, 472.1, 481.3"); + } + fall_transition (inslew_load_5x5__21) { + values ("65.6, 65.6, 65.6, 68.3, 73.9", \ + "88.2, 88.2, 88.2, 91.0, 96.5", \ + "128.6, 128.6, 128.6, 131.3, 136.9", \ + "206.9, 206.9, 206.9, 209.6, 215.1", \ + "362.0, 362.0, 362.0, 364.7, 370.2"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("33.2, 33.2, 33.2, 37.4, 44.8", \ + "30.2, 30.2, 30.2, 34.5, 42.2", \ + "17.1, 17.1, 17.1, 21.4, 29.5", \ + "-17.1, -17.1, -17.1, -12.6, -4.3", \ + "-93.4, -93.4, -93.4, -88.8, -80.0"); + } + rise_transition (inslew_load_5x5__21) { + values ("23.2, 23.2, 23.2, 28.7, 39.4", \ + "31.0, 31.0, 31.0, 36.5, 47.3", \ + "44.1, 44.1, 44.1, 49.7, 60.5", \ + "67.4, 67.4, 67.4, 72.9, 83.9", \ + "111.5, 111.5, 111.5, 117.0, 128.0"); + } + cell_fall (inslew_load_5x5__21) { + values ("134.2, 134.2, 134.2, 138.8, 147.2", \ + "162.4, 162.4, 162.4, 167.0, 175.9", \ + "212.7, 212.7, 212.7, 217.3, 226.4", \ + "310.6, 310.6, 310.6, 315.3, 324.4", \ + "503.4, 503.4, 503.4, 507.9, 517.1"); + } + fall_transition (inslew_load_5x5__21) { + values ("84.3, 84.3, 84.3, 87.1, 92.6", \ + "110.2, 110.2, 110.2, 113.0, 118.5", \ + "158.4, 158.4, 158.4, 161.2, 166.7", \ + "253.3, 253.3, 253.3, 256.1, 261.5", \ + "442.5, 442.5, 442.5, 445.4, 450.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("473.1, 473.1, 473.1, 525.6, 630.7", \ + "518.4, 518.4, 518.4, 571.0, 676.0", \ + "602.8, 602.8, 602.8, 655.3, 760.4", \ + "759.4, 759.4, 759.4, 811.9, 916.9", \ + "1056.8, 1056.8, 1056.8, 1109.3, 1214.4"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("982.4, 982.4, 982.4, 1034.9, 1140.0", \ + "1277.1, 1277.1, 1277.1, 1329.6, 1434.7", \ + "1823.7, 1823.7, 1823.7, 1876.2, 1981.2", \ + "2882.4, 2882.4, 2882.4, 2934.9, 3039.9", \ + "4992.1, 4992.1, 4992.1, 5044.6, 5149.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("412.0, 412.0, 412.0, 464.5, 569.6", \ + "466.0, 466.0, 466.0, 518.5, 623.6", \ + "564.9, 564.9, 564.9, 617.5, 722.5", \ + "749.0, 749.0, 749.0, 801.6, 906.6", \ + "1103.1, 1103.1, 1103.1, 1155.6, 1260.6"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("851.2, 851.2, 851.2, 903.7, 1008.8", \ + "1104.1, 1104.1, 1104.1, 1156.7, 1261.7", \ + "1569.7, 1569.7, 1569.7, 1622.2, 1727.3", \ + "2480.6, 2480.6, 2480.6, 2533.1, 2638.1", \ + "4289.1, 4289.1, 4289.1, 4341.6, 4446.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("421.1, 421.1, 421.1, 473.6, 578.6", \ + "495.2, 495.2, 495.2, 547.8, 652.8", \ + "633.7, 633.7, 633.7, 686.3, 791.3", \ + "897.8, 897.8, 897.8, 950.3, 1055.3", \ + "1414.8, 1414.8, 1414.8, 1467.3, 1572.4"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1078.4, 1078.4, 1078.4, 1131.0, 1236.0", \ + "1384.5, 1384.5, 1384.5, 1437.0, 1542.1", \ + "1965.2, 1965.2, 1965.2, 2017.7, 2122.7", \ + "3113.9, 3113.9, 3113.9, 3166.4, 3271.4", \ + "5408.0, 5408.0, 5408.0, 5460.5, 5565.6"); + } + } + } + } + + cell (oa2a22_x2) { + area : 0.0 ; + cell_leakage_power : 3.3 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 4.1 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3)" ; + value : 2.9 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 1.8 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!(i2) | !(i3)))" ; + value : 4.4 ; + } + pin (i3) { + direction : input ; + capacitance : 4.09 ; + } + pin (i2) { + direction : input ; + capacitance : 4.09 ; + } + pin (i1) { + direction : input ; + capacitance : 3.99 ; + } + pin (i0) { + direction : input ; + capacitance : 3.86 ; + } + pin (q) { + function : "((i0 & ((i3 & i2) | i1)) | (i3 & i2))" ; + direction : output ; + capacitance : 2.60 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("49.1, 49.1, 49.1, 54.3, 63.6", \ + "47.3, 47.3, 47.3, 52.6, 62.3", \ + "38.6, 38.6, 38.6, 43.9, 54.0", \ + "14.1, 14.1, 14.1, 19.6, 30.0", \ + "-41.8, -41.8, -41.8, -36.1, -25.2"); + } + rise_transition (inslew_load_5x5__43) { + values ("37.8, 37.8, 37.8, 44.6, 57.9", \ + "45.4, 45.4, 45.4, 52.2, 65.6", \ + "59.6, 59.6, 59.6, 66.4, 79.9", \ + "86.4, 86.4, 86.4, 93.3, 106.9", \ + "138.5, 138.5, 138.5, 145.4, 159.0"); + } + cell_fall (inslew_load_5x5__43) { + values ("81.0, 81.0, 81.0, 86.2, 96.0", \ + "99.5, 99.5, 99.5, 105.0, 114.8", \ + "130.9, 130.9, 130.9, 136.5, 146.9", \ + "188.6, 188.6, 188.6, 194.3, 205.4", \ + "299.8, 299.8, 299.8, 305.6, 316.8"); + } + fall_transition (inslew_load_5x5__43) { + values ("47.7, 47.7, 47.7, 51.2, 57.9", \ + "63.6, 63.6, 63.6, 67.0, 73.9", \ + "93.9, 93.9, 93.9, 97.4, 104.3", \ + "153.4, 153.4, 153.4, 156.8, 163.9", \ + "271.4, 271.4, 271.4, 274.9, 281.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("48.7, 48.7, 48.7, 53.9, 63.1", \ + "51.4, 51.4, 51.4, 56.7, 66.3", \ + "50.1, 50.1, 50.1, 55.5, 65.5", \ + "40.4, 40.4, 40.4, 46.0, 56.5", \ + "15.3, 15.3, 15.3, 20.9, 31.9"); + } + rise_transition (inslew_load_5x5__43) { + values ("34.4, 34.4, 34.4, 41.2, 54.5", \ + "43.7, 43.7, 43.7, 50.5, 63.9", \ + "60.5, 60.5, 60.5, 67.4, 80.8", \ + "92.1, 92.1, 92.1, 98.9, 112.6", \ + "153.4, 153.4, 153.4, 160.4, 174.0"); + } + cell_fall (inslew_load_5x5__43) { + values ("71.1, 71.1, 71.1, 76.2, 85.9", \ + "84.2, 84.2, 84.2, 89.5, 99.2", \ + "104.8, 104.8, 104.8, 110.3, 120.5", \ + "140.1, 140.1, 140.1, 145.8, 156.6", \ + "206.5, 206.5, 206.5, 212.2, 223.4"); + } + fall_transition (inslew_load_5x5__43) { + values ("41.7, 41.7, 41.7, 45.2, 51.9", \ + "54.8, 54.8, 54.8, 58.3, 65.2", \ + "79.9, 79.9, 79.9, 83.4, 90.3", \ + "128.7, 128.7, 128.7, 132.2, 139.1", \ + "225.4, 225.4, 225.4, 228.9, 235.8"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("61.8, 61.8, 61.8, 67.1, 76.6", \ + "72.6, 72.6, 72.6, 77.9, 87.9", \ + "87.7, 87.7, 87.7, 93.2, 103.5", \ + "111.8, 111.8, 111.8, 117.5, 128.4", \ + "155.8, 155.8, 155.8, 161.5, 172.5"); + } + rise_transition (inslew_load_5x5__43) { + values ("42.8, 42.8, 42.8, 49.6, 62.9", \ + "55.7, 55.7, 55.7, 62.6, 76.0", \ + "79.9, 79.9, 79.9, 86.8, 100.4", \ + "126.6, 126.6, 126.6, 133.5, 147.1", \ + "218.1, 218.1, 218.1, 225.2, 239.1"); + } + cell_fall (inslew_load_5x5__43) { + values ("84.6, 84.6, 84.6, 89.9, 99.6", \ + "87.6, 87.6, 87.6, 93.0, 102.9", \ + "91.1, 91.1, 91.1, 96.7, 106.9", \ + "95.7, 95.7, 95.7, 101.4, 112.2", \ + "102.0, 102.0, 102.0, 107.7, 118.8"); + } + fall_transition (inslew_load_5x5__43) { + values ("54.1, 54.1, 54.1, 57.6, 64.5", \ + "64.7, 64.7, 64.7, 68.1, 75.1", \ + "85.7, 85.7, 85.7, 89.2, 96.1", \ + "127.2, 127.2, 127.2, 130.7, 137.7", \ + "210.6, 210.6, 210.6, 214.1, 221.0"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("61.6, 61.6, 61.6, 66.9, 76.6", \ + "66.6, 66.6, 66.6, 72.0, 81.9", \ + "71.7, 71.7, 71.7, 77.2, 87.5", \ + "76.6, 76.6, 76.6, 82.3, 93.1", \ + "82.2, 82.2, 82.2, 87.8, 98.9"); + } + rise_transition (inslew_load_5x5__43) { + values ("46.3, 46.3, 46.3, 53.1, 66.5", \ + "57.1, 57.1, 57.1, 63.9, 77.4", \ + "77.9, 77.9, 77.9, 84.8, 98.4", \ + "118.6, 118.6, 118.6, 125.5, 139.1", \ + "198.4, 198.4, 198.4, 205.5, 219.3"); + } + cell_fall (inslew_load_5x5__43) { + values ("95.5, 95.5, 95.5, 100.9, 110.7", \ + "104.5, 104.5, 104.5, 110.0, 120.1", \ + "120.0, 120.0, 120.0, 125.6, 136.1", \ + "148.9, 148.9, 148.9, 154.6, 165.7", \ + "205.0, 205.0, 205.0, 210.7, 221.9"); + } + fall_transition (inslew_load_5x5__43) { + values ("61.0, 61.0, 61.0, 64.4, 71.4", \ + "74.9, 74.9, 74.9, 78.4, 85.3", \ + "102.3, 102.3, 102.3, 105.8, 112.7", \ + "157.3, 157.3, 157.3, 160.8, 167.9", \ + "265.9, 265.9, 265.9, 269.4, 276.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__43) { + values ("286.5, 286.5, 286.5, 319.0, 384.0", \ + "329.6, 329.6, 329.6, 362.1, 427.2", \ + "413.8, 413.8, 413.8, 446.3, 511.3", \ + "578.5, 578.5, 578.5, 611.0, 676.1", \ + "904.3, 904.3, 904.3, 936.8, 1001.8"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("403.2, 403.2, 403.2, 435.7, 500.7", \ + "517.5, 517.5, 517.5, 550.0, 615.0", \ + "740.4, 740.4, 740.4, 772.9, 837.9", \ + "1181.6, 1181.6, 1181.6, 1214.1, 1279.1", \ + "2059.9, 2059.9, 2059.9, 2092.4, 2157.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__43) { + values ("254.1, 254.1, 254.1, 286.6, 351.6", \ + "304.4, 304.4, 304.4, 336.9, 402.0", \ + "401.0, 401.0, 401.0, 433.5, 498.5", \ + "589.6, 589.6, 589.6, 622.1, 687.2", \ + "962.8, 962.8, 962.8, 995.3, 1060.3"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("351.6, 351.6, 351.6, 384.1, 449.1", \ + "443.6, 443.6, 443.6, 476.1, 541.1", \ + "623.7, 623.7, 623.7, 656.2, 721.2", \ + "977.9, 977.9, 977.9, 1010.5, 1075.5", \ + "1683.1, 1683.1, 1683.1, 1715.6, 1780.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__43) { + values ("329.5, 329.5, 329.5, 362.0, 427.0", \ + "410.1, 410.1, 410.1, 442.6, 507.7", \ + "567.4, 567.4, 567.4, 599.9, 664.9", \ + "877.7, 877.7, 877.7, 910.2, 975.2", \ + "1495.4, 1495.4, 1495.4, 1527.9, 1592.9"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("454.3, 454.3, 454.3, 486.8, 551.8", \ + "534.6, 534.6, 534.6, 567.1, 632.1", \ + "694.8, 694.8, 694.8, 727.3, 792.4", \ + "1013.4, 1013.4, 1013.4, 1045.9, 1110.9", \ + "1651.8, 1651.8, 1651.8, 1684.4, 1749.4"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__43) { + values ("362.0, 362.0, 362.0, 394.5, 459.5", \ + "433.5, 433.5, 433.5, 466.0, 531.0", \ + "574.9, 574.9, 574.9, 607.4, 672.4", \ + "855.5, 855.5, 855.5, 888.0, 953.0", \ + "1414.1, 1414.1, 1414.1, 1446.6, 1511.6"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("512.9, 512.9, 512.9, 545.4, 610.4", \ + "621.0, 621.0, 621.0, 653.5, 718.6", \ + "835.2, 835.2, 835.2, 867.7, 932.7", \ + "1264.9, 1264.9, 1264.9, 1297.4, 1362.4", \ + "2118.3, 2118.3, 2118.3, 2150.8, 2215.8"); + } + } + } + } + + cell (oa2a22_x4) { + area : 0.0 ; + cell_leakage_power : 4.6 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 5.6 ; + } + leakage_power () { + when : "(i0 & i1 & (!(i2) | !(i3)))" ; + value : 5.7 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3)" ; + value : 4 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 2.4 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!(i2) | !(i3)))" ; + value : 5.4 ; + } + pin (i3) { + direction : input ; + capacitance : 4.28 ; + } + pin (i2) { + direction : input ; + capacitance : 4.26 ; + } + pin (i1) { + direction : input ; + capacitance : 4.17 ; + } + pin (i0) { + direction : input ; + capacitance : 4.16 ; + } + pin (q) { + function : "((i0 & ((i3 & i2) | i1)) | (i3 & i2))" ; + direction : output ; + capacitance : 4.20 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("69.1, 69.1, 69.1, 73.4, 81.6", \ + "69.7, 69.7, 69.7, 74.2, 82.4", \ + "65.1, 65.1, 65.1, 69.5, 78.0", \ + "46.4, 46.4, 46.4, 51.0, 59.7", \ + "-0.7, -0.7, -0.7, 3.9, 12.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("51.0, 51.0, 51.0, 56.6, 67.4", \ + "58.7, 58.7, 58.7, 64.3, 75.2", \ + "73.8, 73.8, 73.8, 79.3, 90.3", \ + "102.5, 102.5, 102.5, 108.0, 119.0", \ + "157.5, 157.5, 157.5, 163.3, 174.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("108.9, 108.9, 108.9, 113.4, 121.5", \ + "127.9, 127.9, 127.9, 132.5, 140.9", \ + "159.8, 159.8, 159.8, 164.4, 173.3", \ + "217.0, 217.0, 217.0, 221.7, 230.7", \ + "325.1, 325.1, 325.1, 329.7, 338.9"); + } + fall_transition (inslew_load_5x5__21) { + values ("66.3, 66.3, 66.3, 69.1, 74.6", \ + "82.0, 82.0, 82.0, 84.8, 90.3", \ + "112.2, 112.2, 112.2, 115.0, 120.5", \ + "172.0, 172.0, 172.0, 174.8, 180.2", \ + "290.7, 290.7, 290.7, 293.4, 298.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("70.1, 70.1, 70.1, 74.4, 82.5", \ + "76.3, 76.3, 76.3, 80.7, 89.0", \ + "80.4, 80.4, 80.4, 84.9, 93.4", \ + "78.0, 78.0, 78.0, 82.6, 91.4", \ + "63.4, 63.4, 63.4, 67.9, 76.9"); + } + rise_transition (inslew_load_5x5__21) { + values ("47.8, 47.8, 47.8, 53.3, 64.2", \ + "57.5, 57.5, 57.5, 63.1, 74.0", \ + "75.6, 75.6, 75.6, 81.1, 92.2", \ + "109.6, 109.6, 109.6, 115.1, 126.0", \ + "174.8, 174.8, 174.8, 180.5, 191.6"); + } + cell_fall (inslew_load_5x5__21) { + values ("99.5, 99.5, 99.5, 104.0, 112.0", \ + "113.3, 113.3, 113.3, 117.9, 126.1", \ + "134.6, 134.6, 134.6, 139.2, 147.8", \ + "169.6, 169.6, 169.6, 174.2, 183.3", \ + "231.9, 231.9, 231.9, 236.5, 245.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("60.4, 60.4, 60.4, 63.1, 68.6", \ + "73.3, 73.3, 73.3, 76.0, 81.5", \ + "97.9, 97.9, 97.9, 100.7, 106.1", \ + "146.7, 146.7, 146.7, 149.5, 155.0", \ + "243.2, 243.2, 243.2, 245.8, 251.3"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("82.6, 82.6, 82.6, 87.0, 95.2", \ + "96.1, 96.1, 96.1, 100.6, 109.0", \ + "115.7, 115.7, 115.7, 120.3, 129.0", \ + "146.5, 146.5, 146.5, 151.1, 160.0", \ + "200.7, 200.7, 200.7, 205.3, 214.4"); + } + rise_transition (inslew_load_5x5__21) { + values ("56.4, 56.4, 56.4, 62.0, 72.8", \ + "69.7, 69.7, 69.7, 75.2, 86.2", \ + "95.4, 95.4, 95.4, 100.8, 111.8", \ + "144.4, 144.4, 144.4, 150.1, 161.0", \ + "240.7, 240.7, 240.7, 246.4, 257.8"); + } + cell_fall (inslew_load_5x5__21) { + values ("111.5, 111.5, 111.5, 116.0, 124.3", \ + "114.3, 114.3, 114.3, 118.9, 127.3", \ + "117.5, 117.5, 117.5, 122.1, 130.8", \ + "120.9, 120.9, 120.9, 125.5, 134.5", \ + "122.9, 122.9, 122.9, 127.5, 136.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("72.5, 72.5, 72.5, 75.2, 80.7", \ + "82.6, 82.6, 82.6, 85.4, 90.8", \ + "103.0, 103.0, 103.0, 105.8, 111.2", \ + "144.9, 144.9, 144.9, 147.6, 153.2", \ + "226.8, 226.8, 226.8, 229.5, 234.9"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("81.7, 81.7, 81.7, 86.1, 94.3", \ + "88.7, 88.7, 88.7, 93.1, 101.5", \ + "97.7, 97.7, 97.7, 102.3, 111.0", \ + "109.0, 109.0, 109.0, 113.6, 122.5", \ + "125.0, 125.0, 125.0, 129.6, 138.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("59.9, 59.9, 59.9, 65.4, 76.4", \ + "71.0, 71.0, 71.0, 76.5, 87.5", \ + "93.2, 93.2, 93.2, 98.6, 109.6", \ + "136.2, 136.2, 136.2, 141.9, 152.8", \ + "221.1, 221.1, 221.1, 226.8, 238.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("121.9, 121.9, 121.9, 126.5, 134.9", \ + "130.2, 130.2, 130.2, 134.8, 143.4", \ + "144.5, 144.5, 144.5, 149.1, 158.0", \ + "170.8, 170.8, 170.8, 175.4, 184.4", \ + "220.2, 220.2, 220.2, 224.9, 234.0"); + } + fall_transition (inslew_load_5x5__21) { + values ("79.2, 79.2, 79.2, 82.0, 87.4", \ + "92.6, 92.6, 92.6, 95.3, 100.8", \ + "119.2, 119.2, 119.2, 122.0, 127.5", \ + "173.3, 173.3, 173.3, 176.0, 181.5", \ + "280.5, 280.5, 280.5, 283.2, 288.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("574.8, 574.8, 574.8, 627.3, 732.4", \ + "644.6, 644.6, 644.6, 697.1, 802.1", \ + "782.1, 782.1, 782.1, 834.6, 939.6", \ + "1050.1, 1050.1, 1050.1, 1102.6, 1207.6", \ + "1574.3, 1574.3, 1574.3, 1626.8, 1731.8"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("847.3, 847.3, 847.3, 899.8, 1004.9", \ + "1026.0, 1026.0, 1026.0, 1078.6, 1183.6", \ + "1373.5, 1373.5, 1373.5, 1426.0, 1531.0", \ + "2063.3, 2063.3, 2063.3, 2115.8, 2220.9", \ + "3435.1, 3435.1, 3435.1, 3487.6, 3592.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("532.7, 532.7, 532.7, 585.2, 690.2", \ + "617.8, 617.8, 617.8, 670.3, 775.3", \ + "779.8, 779.8, 779.8, 832.3, 937.3", \ + "1091.1, 1091.1, 1091.1, 1143.6, 1248.7", \ + "1701.2, 1701.2, 1701.2, 1753.7, 1858.8"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("770.7, 770.7, 770.7, 823.2, 928.2", \ + "915.0, 915.0, 915.0, 967.5, 1072.6", \ + "1194.2, 1194.2, 1194.2, 1246.8, 1351.8", \ + "1748.6, 1748.6, 1748.6, 1801.1, 1906.1", \ + "2847.3, 2847.3, 2847.3, 2899.8, 3004.8"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("639.1, 639.1, 639.1, 691.6, 796.6", \ + "766.0, 766.0, 766.0, 818.5, 923.5", \ + "1014.2, 1014.2, 1014.2, 1066.7, 1171.8", \ + "1500.1, 1500.1, 1500.1, 1552.7, 1657.7", \ + "2463.3, 2463.3, 2463.3, 2515.8, 2620.9"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("923.7, 923.7, 923.7, 976.2, 1081.2", \ + "1043.8, 1043.8, 1043.8, 1096.3, 1201.3", \ + "1284.9, 1284.9, 1284.9, 1337.5, 1442.5", \ + "1776.3, 1776.3, 1776.3, 1828.9, 1933.9", \ + "2743.0, 2743.0, 2743.0, 2795.5, 2900.5"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__21) { + values ("683.4, 683.4, 683.4, 736.0, 841.0", \ + "794.1, 794.1, 794.1, 846.6, 951.6", \ + "1015.7, 1015.7, 1015.7, 1068.3, 1173.3", \ + "1453.9, 1453.9, 1453.9, 1506.5, 1611.5", \ + "2325.3, 2325.3, 2325.3, 2377.8, 2482.8"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1008.8, 1008.8, 1008.8, 1061.3, 1166.4", \ + "1169.5, 1169.5, 1169.5, 1222.0, 1327.0", \ + "1489.7, 1489.7, 1489.7, 1542.2, 1647.2", \ + "2135.6, 2135.6, 2135.6, 2188.1, 2293.2", \ + "3420.4, 3420.4, 3420.4, 3473.0, 3578.0"); + } + } + } + } + + cell (oa2a2a23_x2) { + area : 0.0 ; + cell_leakage_power : 21 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5))" ; + value : 18 ; + } + leakage_power () { + when : "(i0 & i1 & ((!(i2) & ((!(i3) & (!(i4) | !(i5))) | (!(i4) & !(i5)))) | (!(i3) & !(i4) & !(i5))))" ; + value : 11 ; + } + leakage_power () { + when : "((i0 | i1) & i2 & i3 & i4 & i5)" ; + value : 35 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5)" ; + value : 30 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & (i4 ^ i5)) | (!(i3) & i4 & i5))) | (!(i2) & i3 & i4 & i5))) | (!(i1) & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))))) | (!(i0) & ((i1 & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))) | (i2 & i3 & (i4 ^ i5)))))" ; + value : 24 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & i3 & !(i4) & !(i5)) | (!(i2) & !(i3) & i4 & i5))) | (i2 & i3 & !(i4) & !(i5)))" ; + value : 12 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & i4 & i5)" ; + value : 36 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !((i2 & i3)) & (!(i4) | !(i5)))" ; + value : 4.4 ; + } + pin (i5) { + direction : input ; + capacitance : 6.52 ; + } + pin (i4) { + direction : input ; + capacitance : 6.52 ; + } + pin (i3) { + direction : input ; + capacitance : 6.53 ; + } + pin (i2) { + direction : input ; + capacitance : 6.52 ; + } + pin (i1) { + direction : input ; + capacitance : 6.52 ; + } + pin (i0) { + direction : input ; + capacitance : 6.52 ; + } + pin (q) { + function : "((i5 & ((i3 & ((i0 & i1) | i2 | i4)) | (i0 & i1) | i4)) | (i3 & ((i0 & i1) | i2)) | (i0 & i1))" ; + direction : output ; + capacitance : 2.60 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("55.6, 55.6, 55.6, 60.9, 70.4", \ + "60.3, 60.3, 60.3, 65.6, 75.5", \ + "65.1, 65.1, 65.1, 70.6, 80.8", \ + "70.0, 70.0, 70.0, 75.7, 86.5", \ + "76.0, 76.0, 76.0, 81.7, 92.8"); + } + rise_transition (inslew_load_5x5__43) { + values ("41.3, 41.3, 41.3, 48.1, 61.5", \ + "52.1, 52.1, 52.1, 58.9, 72.4", \ + "72.7, 72.7, 72.7, 79.6, 93.2", \ + "112.9, 112.9, 112.9, 119.7, 133.4", \ + "191.8, 191.8, 191.8, 198.9, 212.7"); + } + cell_fall (inslew_load_5x5__43) { + values ("138.4, 138.4, 138.4, 144.1, 154.5", \ + "151.4, 151.4, 151.4, 157.0, 167.7", \ + "174.3, 174.3, 174.3, 180.0, 190.9", \ + "220.1, 220.1, 220.1, 225.8, 237.0", \ + "312.7, 312.7, 312.7, 318.4, 329.7"); + } + fall_transition (inslew_load_5x5__43) { + values ("87.0, 87.0, 87.0, 90.6, 97.6", \ + "107.0, 107.0, 107.0, 110.6, 117.6", \ + "144.7, 144.7, 144.7, 148.4, 155.6", \ + "219.2, 219.2, 219.2, 222.8, 229.9", \ + "368.2, 368.2, 368.2, 371.7, 378.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("55.6, 55.6, 55.6, 60.8, 70.2", \ + "65.7, 65.7, 65.7, 71.0, 80.8", \ + "79.9, 79.9, 79.9, 85.4, 95.7", \ + "103.4, 103.4, 103.4, 109.1, 119.9", \ + "146.6, 146.6, 146.6, 152.3, 163.4"); + } + rise_transition (inslew_load_5x5__43) { + values ("38.0, 38.0, 38.0, 44.8, 58.1", \ + "50.9, 50.9, 50.9, 57.7, 71.1", \ + "74.6, 74.6, 74.6, 81.5, 95.1", \ + "120.4, 120.4, 120.4, 127.3, 141.0", \ + "210.6, 210.6, 210.6, 217.6, 231.6"); + } + cell_fall (inslew_load_5x5__43) { + values ("122.5, 122.5, 122.5, 128.0, 138.3", \ + "126.8, 126.8, 126.8, 132.4, 142.9", \ + "133.6, 133.6, 133.6, 139.3, 150.1", \ + "148.0, 148.0, 148.0, 153.6, 164.7", \ + "177.3, 177.3, 177.3, 183.1, 194.3"); + } + fall_transition (inslew_load_5x5__43) { + values ("77.3, 77.3, 77.3, 80.9, 87.8", \ + "92.3, 92.3, 92.3, 96.0, 102.9", \ + "120.6, 120.6, 120.6, 124.2, 131.3", \ + "176.5, 176.5, 176.5, 180.1, 187.3", \ + "288.7, 288.7, 288.7, 292.3, 299.5"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("46.1, 46.1, 46.1, 51.3, 60.6", \ + "44.2, 44.2, 44.2, 49.4, 59.0", \ + "34.9, 34.9, 34.9, 40.3, 50.3", \ + "10.0, 10.0, 10.0, 15.5, 25.9", \ + "-46.4, -46.4, -46.4, -40.7, -29.8"); + } + rise_transition (inslew_load_5x5__43) { + values ("35.0, 35.0, 35.0, 41.8, 55.1", \ + "42.6, 42.6, 42.6, 49.4, 62.8", \ + "56.5, 56.5, 56.5, 63.4, 76.9", \ + "83.0, 83.0, 83.0, 89.9, 103.5", \ + "134.2, 134.2, 134.2, 141.2, 154.8"); + } + cell_fall (inslew_load_5x5__43) { + values ("116.0, 116.0, 116.0, 121.5, 131.7", \ + "136.9, 136.9, 136.9, 142.5, 152.9", \ + "173.4, 173.4, 173.4, 179.0, 189.9", \ + "242.8, 242.8, 242.8, 248.5, 259.6", \ + "380.6, 380.6, 380.6, 386.2, 397.6"); + } + fall_transition (inslew_load_5x5__43) { + values ("70.2, 70.2, 70.2, 73.8, 80.7", \ + "90.9, 90.9, 90.9, 94.6, 101.5", \ + "129.5, 129.5, 129.5, 133.1, 140.2", \ + "205.4, 205.4, 205.4, 209.0, 216.2", \ + "357.2, 357.2, 357.2, 360.6, 367.8"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("45.7, 45.7, 45.7, 50.8, 60.0", \ + "48.0, 48.0, 48.0, 53.3, 62.8", \ + "46.1, 46.1, 46.1, 51.5, 61.5", \ + "36.0, 36.0, 36.0, 41.5, 52.1", \ + "10.4, 10.4, 10.4, 16.0, 27.1"); + } + rise_transition (inslew_load_5x5__43) { + values ("31.9, 31.9, 31.9, 38.7, 51.9", \ + "41.1, 41.1, 41.1, 47.9, 61.3", \ + "57.6, 57.6, 57.6, 64.5, 78.0", \ + "88.8, 88.8, 88.8, 95.6, 109.3", \ + "149.3, 149.3, 149.3, 156.4, 170.0"); + } + cell_fall (inslew_load_5x5__43) { + values ("102.0, 102.0, 102.0, 107.5, 117.4", \ + "115.5, 115.5, 115.5, 121.1, 131.4", \ + "138.2, 138.2, 138.2, 143.8, 154.5", \ + "181.0, 181.0, 181.0, 186.7, 197.8", \ + "264.5, 264.5, 264.5, 270.3, 281.5"); + } + fall_transition (inslew_load_5x5__43) { + values ("61.7, 61.7, 61.7, 65.3, 72.3", \ + "78.4, 78.4, 78.4, 82.0, 88.9", \ + "109.4, 109.4, 109.4, 113.0, 120.0", \ + "170.8, 170.8, 170.8, 174.4, 181.6", \ + "293.5, 293.5, 293.5, 297.0, 304.3"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("34.0, 34.0, 34.0, 39.0, 47.8", \ + "31.1, 31.1, 31.1, 36.2, 45.4", \ + "19.5, 19.5, 19.5, 24.8, 34.4", \ + "-9.9, -9.9, -9.9, -4.4, 5.8", \ + "-73.8, -73.8, -73.8, -68.2, -57.4"); + } + rise_transition (inslew_load_5x5__43) { + values ("24.9, 24.9, 24.9, 31.7, 44.9", \ + "32.4, 32.4, 32.4, 39.3, 52.5", \ + "45.5, 45.5, 45.5, 52.3, 65.7", \ + "69.2, 69.2, 69.2, 76.1, 89.7", \ + "115.2, 115.2, 115.2, 122.0, 135.7"); + } + cell_fall (inslew_load_5x5__43) { + values ("72.8, 72.8, 72.8, 78.0, 87.7", \ + "90.2, 90.2, 90.2, 95.6, 105.5", \ + "123.3, 123.3, 123.3, 128.9, 139.4", \ + "185.8, 185.8, 185.8, 191.5, 202.5", \ + "305.6, 305.6, 305.6, 311.4, 322.6"); + } + fall_transition (inslew_load_5x5__43) { + values ("42.7, 42.7, 42.7, 46.3, 53.0", \ + "59.3, 59.3, 59.3, 62.8, 69.8", \ + "91.7, 91.7, 91.7, 95.4, 102.3", \ + "155.6, 155.6, 155.6, 159.2, 166.4", \ + "281.3, 281.3, 281.3, 284.9, 292.1"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("35.6, 35.6, 35.6, 40.6, 49.6", \ + "29.8, 29.8, 29.8, 34.9, 44.1", \ + "12.6, 12.6, 12.6, 17.9, 27.5", \ + "-28.8, -28.8, -28.8, -23.3, -13.2", \ + "-118.1, -118.1, -118.1, -112.5, -101.8"); + } + rise_transition (inslew_load_5x5__43) { + values ("28.3, 28.3, 28.3, 35.1, 48.3", \ + "34.5, 34.5, 34.5, 41.3, 54.6", \ + "45.5, 45.5, 45.5, 52.3, 65.7", \ + "65.4, 65.4, 65.4, 72.3, 85.9", \ + "103.7, 103.7, 103.7, 110.5, 124.2"); + } + cell_fall (inslew_load_5x5__43) { + values ("85.8, 85.8, 85.8, 91.1, 100.9", \ + "109.7, 109.7, 109.7, 115.2, 125.4", \ + "155.0, 155.0, 155.0, 160.6, 171.3", \ + "241.0, 241.0, 241.0, 246.7, 257.8", \ + "408.0, 408.0, 408.0, 413.6, 424.9"); + } + fall_transition (inslew_load_5x5__43) { + values ("50.4, 50.4, 50.4, 53.9, 60.9", \ + "70.4, 70.4, 70.4, 73.9, 80.9", \ + "109.4, 109.4, 109.4, 113.0, 120.1", \ + "185.0, 185.0, 185.0, 188.6, 195.8", \ + "334.7, 334.7, 334.7, 338.1, 345.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__43) { + values ("500.1, 500.1, 500.1, 532.6, 597.6", \ + "608.1, 608.1, 608.1, 640.6, 705.7", \ + "822.5, 822.5, 822.5, 855.0, 920.0", \ + "1249.2, 1249.2, 1249.2, 1281.7, 1346.7", \ + "2100.6, 2100.6, 2100.6, 2133.1, 2198.1"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("857.6, 857.6, 857.6, 890.1, 955.1", \ + "1044.6, 1044.6, 1044.6, 1077.1, 1142.1", \ + "1408.8, 1408.8, 1408.8, 1441.3, 1506.3", \ + "2132.2, 2132.2, 2132.2, 2164.7, 2229.8", \ + "3579.6, 3579.6, 3579.6, 3612.2, 3677.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__43) { + values ("448.7, 448.7, 448.7, 481.2, 546.2", \ + "568.0, 568.0, 568.0, 600.5, 665.5", \ + "802.1, 802.1, 802.1, 834.6, 899.6", \ + "1266.8, 1266.8, 1266.8, 1299.3, 1364.3", \ + "2193.9, 2193.9, 2193.9, 2226.4, 2291.4"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("759.0, 759.0, 759.0, 791.5, 856.5", \ + "898.7, 898.7, 898.7, 931.2, 996.2", \ + "1169.7, 1169.7, 1169.7, 1202.2, 1267.2", \ + "1709.2, 1709.2, 1709.2, 1741.7, 1806.7", \ + "2790.2, 2790.2, 2790.2, 2822.7, 2887.7"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__43) { + values ("405.7, 405.7, 405.7, 438.3, 503.3", \ + "467.7, 467.7, 467.7, 500.2, 565.2", \ + "588.9, 588.9, 588.9, 621.4, 686.4", \ + "828.3, 828.3, 828.3, 860.8, 925.8", \ + "1303.3, 1303.3, 1303.3, 1335.8, 1400.8"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("699.5, 699.5, 699.5, 732.1, 797.1", \ + "885.7, 885.7, 885.7, 918.2, 983.2", \ + "1245.1, 1245.1, 1245.1, 1277.6, 1342.6", \ + "1959.0, 1959.0, 1959.0, 1991.5, 2056.6", \ + "3385.7, 3385.7, 3385.7, 3418.2, 3483.2"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__43) { + values ("354.9, 354.9, 354.9, 387.4, 452.4", \ + "426.2, 426.2, 426.2, 458.7, 523.7", \ + "564.7, 564.7, 564.7, 597.2, 662.2", \ + "837.6, 837.6, 837.6, 870.1, 935.2", \ + "1380.1, 1380.1, 1380.1, 1412.6, 1477.7"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("611.7, 611.7, 611.7, 644.2, 709.2", \ + "759.2, 759.2, 759.2, 791.7, 856.8", \ + "1044.6, 1044.6, 1044.6, 1077.1, 1142.1", \ + "1612.8, 1612.8, 1612.8, 1645.3, 1710.3", \ + "2749.1, 2749.1, 2749.1, 2781.6, 2846.6"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__43) { + values ("260.7, 260.7, 260.7, 293.2, 358.2", \ + "310.2, 310.2, 310.2, 342.8, 407.8", \ + "405.2, 405.2, 405.2, 437.7, 502.7", \ + "591.1, 591.1, 591.1, 623.6, 688.6", \ + "960.0, 960.0, 960.0, 992.5, 1057.5"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("429.9, 429.9, 429.9, 462.4, 527.4", \ + "573.7, 573.7, 573.7, 606.3, 671.3", \ + "858.9, 858.9, 858.9, 891.5, 956.5", \ + "1425.1, 1425.1, 1425.1, 1457.6, 1522.6", \ + "2548.8, 2548.8, 2548.8, 2581.4, 2646.4"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__43) { + values ("313.0, 313.0, 313.0, 345.5, 410.5", \ + "355.2, 355.2, 355.2, 387.7, 452.8", \ + "436.8, 436.8, 436.8, 469.3, 534.3", \ + "596.2, 596.2, 596.2, 628.7, 693.7", \ + "911.1, 911.1, 911.1, 943.6, 1008.6"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("510.1, 510.1, 510.1, 542.6, 607.7", \ + "685.3, 685.3, 685.3, 717.8, 782.8", \ + "1032.3, 1032.3, 1032.3, 1064.8, 1129.8", \ + "1715.0, 1715.0, 1715.0, 1747.5, 1812.5", \ + "3074.3, 3074.3, 3074.3, 3106.8, 3171.9"); + } + } + } + } + + cell (oa2a2a23_x4) { + area : 0.0 ; + cell_leakage_power : 21 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5))" ; + value : 18 ; + } + leakage_power () { + when : "(i0 & i1 & ((!(i2) & ((!(i3) & (!(i4) | !(i5))) | (!(i4) & !(i5)))) | (!(i3) & !(i4) & !(i5))))" ; + value : 11 ; + } + leakage_power () { + when : "((i0 | i1) & i2 & i3 & i4 & i5)" ; + value : 35 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5)" ; + value : 30 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & (i4 ^ i5)) | (!(i3) & i4 & i5))) | (!(i2) & i3 & i4 & i5))) | (!(i1) & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))))) | (!(i0) & ((i1 & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))) | (i2 & i3 & (i4 ^ i5)))))" ; + value : 24 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & i3 & !(i4) & !(i5)) | (!(i2) & !(i3) & i4 & i5))) | (i2 & i3 & !(i4) & !(i5)))" ; + value : 12 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & i4 & i5)" ; + value : 36 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !((i2 & i3)) & (!(i4) | !(i5)))" ; + value : 5.4 ; + } + pin (i5) { + direction : input ; + capacitance : 6.58 ; + } + pin (i4) { + direction : input ; + capacitance : 6.72 ; + } + pin (i3) { + direction : input ; + capacitance : 6.58 ; + } + pin (i2) { + direction : input ; + capacitance : 6.58 ; + } + pin (i1) { + direction : input ; + capacitance : 6.58 ; + } + pin (i0) { + direction : input ; + capacitance : 6.60 ; + } + pin (q) { + function : "((i4 & ((i3 & ((i1 & i0) | i2 | i5)) | (i1 & i0) | i5)) | (i3 & ((i1 & i0) | i2)) | (i1 & i0))" ; + direction : output ; + capacitance : 4.20 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("64.9, 64.9, 64.9, 69.3, 77.4", \ + "70.5, 70.5, 70.5, 74.9, 83.2", \ + "76.6, 76.6, 76.6, 81.1, 89.7", \ + "83.0, 83.0, 83.0, 87.7, 96.5", \ + "90.8, 90.8, 90.8, 95.4, 104.4"); + } + rise_transition (inslew_load_5x5__21) { + values ("47.3, 47.3, 47.3, 52.8, 63.7", \ + "58.1, 58.1, 58.1, 63.6, 74.6", \ + "79.0, 79.0, 79.0, 84.5, 95.6", \ + "119.8, 119.8, 119.8, 125.4, 136.4", \ + "199.8, 199.8, 199.8, 205.5, 216.8"); + } + cell_fall (inslew_load_5x5__21) { + values ("163.6, 163.6, 163.6, 168.2, 177.0", \ + "177.1, 177.1, 177.1, 181.7, 190.7", \ + "201.2, 201.2, 201.2, 205.8, 214.8", \ + "248.7, 248.7, 248.7, 253.3, 262.4", \ + "344.8, 344.8, 344.8, 349.4, 358.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("104.2, 104.2, 104.2, 107.0, 112.6", \ + "124.8, 124.8, 124.8, 127.6, 133.3", \ + "163.9, 163.9, 163.9, 166.7, 172.3", \ + "240.8, 240.8, 240.8, 243.6, 249.2", \ + "394.7, 394.7, 394.7, 397.6, 403.2"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("65.5, 65.5, 65.5, 69.9, 77.9", \ + "76.8, 76.8, 76.8, 81.2, 89.5", \ + "92.7, 92.7, 92.7, 97.2, 105.8", \ + "117.8, 117.8, 117.8, 122.5, 131.4", \ + "163.1, 163.1, 163.1, 167.7, 176.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("44.0, 44.0, 44.0, 49.6, 60.4", \ + "56.9, 56.9, 56.9, 62.5, 73.5", \ + "81.2, 81.2, 81.2, 86.7, 97.7", \ + "127.7, 127.7, 127.7, 133.4, 144.4", \ + "219.1, 219.1, 219.1, 224.8, 236.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("147.4, 147.4, 147.4, 151.9, 160.6", \ + "152.4, 152.4, 152.4, 157.0, 165.9", \ + "160.1, 160.1, 160.1, 164.7, 173.7", \ + "175.7, 175.7, 175.7, 180.3, 189.4", \ + "207.9, 207.9, 207.9, 212.5, 221.7"); + } + fall_transition (inslew_load_5x5__21) { + values ("94.1, 94.1, 94.1, 96.9, 102.5", \ + "109.7, 109.7, 109.7, 112.4, 118.1", \ + "138.8, 138.8, 138.8, 141.6, 147.3", \ + "196.5, 196.5, 196.5, 199.4, 204.9", \ + "312.5, 312.5, 312.5, 315.3, 320.9"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("55.7, 55.7, 55.7, 60.1, 68.0", \ + "55.0, 55.0, 55.0, 59.3, 67.5", \ + "47.6, 47.6, 47.6, 52.1, 60.4", \ + "24.8, 24.8, 24.8, 29.3, 38.0", \ + "-29.2, -29.2, -29.2, -24.6, -15.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("41.1, 41.1, 41.1, 46.6, 57.5", \ + "48.6, 48.6, 48.6, 54.2, 65.1", \ + "62.9, 62.9, 62.9, 68.4, 79.4", \ + "90.0, 90.0, 90.0, 95.5, 106.5", \ + "142.0, 142.0, 142.0, 147.8, 158.7"); + } + cell_fall (inslew_load_5x5__21) { + values ("141.0, 141.0, 141.0, 145.5, 154.1", \ + "162.5, 162.5, 162.5, 167.1, 175.9", \ + "200.2, 200.2, 200.2, 204.8, 213.8", \ + "271.8, 271.8, 271.8, 276.4, 285.6", \ + "413.4, 413.4, 413.4, 418.0, 427.2"); + } + fall_transition (inslew_load_5x5__21) { + values ("87.0, 87.0, 87.0, 89.9, 95.4", \ + "108.4, 108.4, 108.4, 111.2, 116.8", \ + "148.0, 148.0, 148.0, 150.8, 156.5", \ + "226.4, 226.4, 226.4, 229.2, 234.8", \ + "383.1, 383.1, 383.1, 385.9, 391.6"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("56.2, 56.2, 56.2, 60.5, 68.3", \ + "60.1, 60.1, 60.1, 64.5, 72.6", \ + "60.6, 60.6, 60.6, 65.1, 73.4", \ + "52.8, 52.8, 52.8, 57.4, 66.1", \ + "29.7, 29.7, 29.7, 34.2, 43.2"); + } + rise_transition (inslew_load_5x5__21) { + values ("38.0, 38.0, 38.0, 43.5, 54.4", \ + "47.4, 47.4, 47.4, 53.0, 63.8", \ + "64.4, 64.4, 64.4, 69.9, 80.9", \ + "96.3, 96.3, 96.3, 101.8, 112.9", \ + "157.9, 157.9, 157.9, 163.6, 174.7"); + } + cell_fall (inslew_load_5x5__21) { + values ("126.8, 126.8, 126.8, 131.4, 139.9", \ + "141.2, 141.2, 141.2, 145.8, 154.4", \ + "165.2, 165.2, 165.2, 169.8, 178.8", \ + "209.7, 209.7, 209.7, 214.3, 223.4", \ + "296.8, 296.8, 296.8, 301.4, 310.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("78.3, 78.3, 78.3, 81.1, 86.6", \ + "95.3, 95.3, 95.3, 98.1, 103.7", \ + "127.1, 127.1, 127.1, 129.9, 135.6", \ + "190.4, 190.4, 190.4, 193.2, 198.8", \ + "317.3, 317.3, 317.3, 320.1, 325.6"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("45.6, 45.6, 45.6, 49.9, 57.6", \ + "45.0, 45.0, 45.0, 49.3, 57.2", \ + "36.2, 36.2, 36.2, 40.6, 48.8", \ + "9.9, 9.9, 9.9, 14.4, 22.9", \ + "-51.4, -51.4, -51.4, -46.7, -37.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("31.4, 31.4, 31.4, 36.9, 47.7", \ + "39.2, 39.2, 39.2, 44.7, 55.5", \ + "52.5, 52.5, 52.5, 58.1, 69.0", \ + "77.2, 77.2, 77.2, 82.7, 93.8", \ + "124.0, 124.0, 124.0, 129.7, 140.6"); + } + cell_fall (inslew_load_5x5__21) { + values ("98.0, 98.0, 98.0, 102.4, 110.6", \ + "116.6, 116.6, 116.6, 121.2, 129.6", \ + "151.5, 151.5, 151.5, 156.1, 165.0", \ + "216.2, 216.2, 216.2, 220.9, 229.9", \ + "339.9, 339.9, 339.9, 344.5, 353.7"); + } + fall_transition (inslew_load_5x5__21) { + values ("58.8, 58.8, 58.8, 61.6, 67.2", \ + "75.7, 75.7, 75.7, 78.6, 84.1", \ + "109.6, 109.6, 109.6, 112.4, 118.0", \ + "175.1, 175.1, 175.1, 177.9, 183.5", \ + "305.2, 305.2, 305.2, 308.0, 313.6"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("45.9, 45.9, 45.9, 50.2, 57.9", \ + "41.6, 41.6, 41.6, 45.9, 53.9", \ + "26.7, 26.7, 26.7, 31.1, 39.3", \ + "-11.6, -11.6, -11.6, -7.2, 1.3", \ + "-98.3, -98.3, -98.3, -93.6, -84.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("34.5, 34.5, 34.5, 40.0, 50.8", \ + "40.7, 40.7, 40.7, 46.2, 57.1", \ + "52.0, 52.0, 52.0, 57.6, 68.5", \ + "72.8, 72.8, 72.8, 78.3, 89.3", \ + "111.9, 111.9, 111.9, 117.5, 128.4"); + } + cell_fall (inslew_load_5x5__21) { + values ("110.8, 110.8, 110.8, 115.3, 123.6", \ + "136.1, 136.1, 136.1, 140.6, 149.2", \ + "182.8, 182.8, 182.8, 187.4, 196.4", \ + "271.4, 271.4, 271.4, 276.0, 285.1", \ + "442.3, 442.3, 442.3, 447.0, 456.2"); + } + fall_transition (inslew_load_5x5__21) { + values ("66.8, 66.8, 66.8, 69.6, 75.2", \ + "87.3, 87.3, 87.3, 90.1, 95.7", \ + "127.4, 127.4, 127.4, 130.2, 135.9", \ + "205.5, 205.5, 205.5, 208.3, 213.9", \ + "360.3, 360.3, 360.3, 363.1, 368.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("753.5, 753.5, 753.5, 806.0, 911.0", \ + "896.1, 896.1, 896.1, 948.6, 1053.6", \ + "1178.6, 1178.6, 1178.6, 1231.1, 1336.2", \ + "1739.3, 1739.3, 1739.3, 1791.9, 1896.9", \ + "2854.9, 2854.9, 2854.9, 2907.4, 3012.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1458.6, 1458.6, 1458.6, 1511.1, 1616.1", \ + "1734.0, 1734.0, 1734.0, 1786.6, 1891.6", \ + "2266.1, 2266.1, 2266.1, 2318.6, 2423.7", \ + "3319.4, 3319.4, 3319.4, 3372.0, 3477.0", \ + "5427.2, 5427.2, 5427.2, 5479.8, 5584.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("692.0, 692.0, 692.0, 744.6, 849.6", \ + "852.8, 852.8, 852.8, 905.3, 1010.4", \ + "1166.1, 1166.1, 1166.1, 1218.6, 1323.7", \ + "1784.1, 1784.1, 1784.1, 1836.6, 1941.6", \ + "3013.3, 3013.3, 3013.3, 3065.8, 3170.8"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1316.7, 1316.7, 1316.7, 1369.2, 1474.2", \ + "1522.9, 1522.9, 1522.9, 1575.4, 1680.5", \ + "1919.2, 1919.2, 1919.2, 1971.7, 2076.8", \ + "2706.0, 2706.0, 2706.0, 2758.5, 2863.5", \ + "4283.9, 4283.9, 4283.9, 4336.4, 4441.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("639.8, 639.8, 639.8, 692.3, 797.4", \ + "725.5, 725.5, 725.5, 778.0, 883.1", \ + "893.4, 893.4, 893.4, 945.9, 1050.9", \ + "1222.0, 1222.0, 1222.0, 1274.5, 1379.5", \ + "1869.0, 1869.0, 1869.0, 1921.5, 2026.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1227.8, 1227.8, 1227.8, 1280.3, 1385.4", \ + "1505.1, 1505.1, 1505.1, 1557.6, 1662.6", \ + "2034.0, 2034.0, 2034.0, 2086.5, 2191.5", \ + "3083.3, 3083.3, 3083.3, 3135.8, 3240.9", \ + "5182.3, 5182.3, 5182.3, 5234.8, 5339.9"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__21) { + values ("579.3, 579.3, 579.3, 631.8, 736.9", \ + "680.9, 680.9, 680.9, 733.4, 838.5", \ + "875.4, 875.4, 875.4, 928.0, 1033.0", \ + "1253.5, 1253.5, 1253.5, 1306.0, 1411.1", \ + "1999.8, 1999.8, 1999.8, 2052.3, 2157.4"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("1102.2, 1102.2, 1102.2, 1154.7, 1259.8", \ + "1321.9, 1321.9, 1321.9, 1374.4, 1479.4", \ + "1743.3, 1743.3, 1743.3, 1795.8, 1900.8", \ + "2582.3, 2582.3, 2582.3, 2634.8, 2739.8", \ + "4262.3, 4262.3, 4262.3, 4314.8, 4419.9"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__21) { + values ("465.3, 465.3, 465.3, 517.9, 622.9", \ + "540.0, 540.0, 540.0, 592.5, 697.6", \ + "679.2, 679.2, 679.2, 731.7, 836.7", \ + "946.9, 946.9, 946.9, 999.4, 1104.4", \ + "1470.4, 1470.4, 1470.4, 1523.0, 1628.0"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("837.9, 837.9, 837.9, 890.4, 995.5", \ + "1053.7, 1053.7, 1053.7, 1106.3, 1211.3", \ + "1485.4, 1485.4, 1485.4, 1537.9, 1643.0", \ + "2330.3, 2330.3, 2330.3, 2382.8, 2487.8", \ + "4012.6, 4012.6, 4012.6, 4065.1, 4170.1"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__21) { + values ("526.4, 526.4, 526.4, 578.9, 684.0", \ + "588.5, 588.5, 588.5, 641.1, 746.1", \ + "707.7, 707.7, 707.7, 760.2, 865.2", \ + "935.7, 935.7, 935.7, 988.2, 1093.2", \ + "1379.9, 1379.9, 1379.9, 1432.4, 1537.4"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("952.7, 952.7, 952.7, 1005.2, 1110.2", \ + "1215.0, 1215.0, 1215.0, 1267.5, 1372.5", \ + "1732.8, 1732.8, 1732.8, 1785.3, 1890.3", \ + "2750.8, 2750.8, 2750.8, 2803.3, 2908.3", \ + "4774.5, 4774.5, 4774.5, 4827.0, 4932.0"); + } + } + } + } + + cell (oa2a2a2a24_x2) { + area : 0.0 ; + cell_leakage_power : 40 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5) & (i6 ^ i7))" ; + value : 28 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & (i4 ^ i5) & (i6 ^ i7))))))" ; + value : 22 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 20 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5 & (i6 ^ i7))" ; + value : 42 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & !(i4) & !(i5) & i6 & i7)" ; + value : 36 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i0) & i1 & !(i2) & !(i3) & !(i4) & !(i5) & i6 & i7))" ; + value : 47 ; + } + leakage_power () { + when : "(i2 & i3 & i4 & i5 & i6 & i7)" ; + value : 71 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i2) & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i1) & ((i2 & i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & !(i3) & i4 & i5 & (i6 ^ i7)))))) | (!(i0) & ((i1 & ((i2 & i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & !(i3) & i4 & i5 & (i6 ^ i7)))) | (i2 & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 35 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))) | (!(i1) & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & !(i3) & i4 & i5 & !(i6) & !(i7)))))) | (!(i0) & ((i1 & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & !(i3) & i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))" ; + value : 23 ; + } + leakage_power () { + when : "((i0 & i1 & (((i2 | i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!((i2 | i3)) & ((i4 | i5) ^ (i6 | i7))))) | (i2 & i3 & !(i4) & !(i5) & !(i6) & !(i7)))" ; + value : 21 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i1) & (i2 ^ i3) & (i4 ^ i5) & i6 & i7))))" ; + value : 60 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3) & !(i4) & !(i5) & i6 & i7)" ; + value : 49 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & (i4 | i5) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (!(i0) & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & (i4 | i5) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (!(i1) & ((i2 & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))" ; + value : 48 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & !(i3) & i4 & i5 & i6 & i7))) | (!(i1) & ((i2 & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i3 & i4 & i5 & !(i6) & !(i7)))))) | (!(i0) & ((!(i1) & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i2 & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i3 & i4 & i5 & !(i6) & !(i7)))))" ; + value : 24 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((!(i2) & ((!(i3) & (i4 | i5) & i6 & i7) | (i4 & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7)))" ; + value : 72 ; + } + leakage_power () { + when : "(i7 & i6 & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 73 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !((i2 & i3)) & !((i4 & i5)) & (!(i6) | !(i7)))" ; + value : 4.4 ; + } + pin (i7) { + direction : input ; + capacitance : 6.66 ; + } + pin (i6) { + direction : input ; + capacitance : 6.62 ; + } + pin (i5) { + direction : input ; + capacitance : 6.54 ; + } + pin (i4) { + direction : input ; + capacitance : 6.53 ; + } + pin (i3) { + direction : input ; + capacitance : 6.52 ; + } + pin (i2) { + direction : input ; + capacitance : 6.53 ; + } + pin (i1) { + direction : input ; + capacitance : 6.52 ; + } + pin (i0) { + direction : input ; + capacitance : 6.66 ; + } + pin (q) { + function : "((i6 & ((i5 & ((i3 & ((i0 & i1) | i2 | i4 | i7)) | (i0 & i1) | i4 | i7)) | (i3 & ((i0 & i1) | i2 | i7)) | (i0 & i1) | i7)) | (i5 & ((i3 & ((i0 & i1) | i2 | i4)) | (i0 & i1) | i4)) | (i3 & ((i0 & i1) | i2)) | (i0 & i1))" ; + direction : output ; + capacitance : 2.47 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("57.1, 57.1, 57.1, 62.1, 71.3", \ + "61.8, 61.8, 61.8, 66.9, 76.4", \ + "66.7, 66.7, 66.7, 72.0, 81.8", \ + "71.8, 71.8, 71.8, 77.2, 87.5", \ + "77.7, 77.7, 77.7, 83.1, 93.7"); + } + rise_transition (inslew_load_5x5__46) { + values ("42.0, 42.0, 42.0, 48.5, 61.3", \ + "52.7, 52.7, 52.7, 59.3, 72.1", \ + "73.3, 73.3, 73.3, 79.9, 92.8", \ + "113.3, 113.3, 113.3, 119.9, 132.9", \ + "192.1, 192.1, 192.1, 198.8, 212.0"); + } + cell_fall (inslew_load_5x5__46) { + values ("222.1, 222.1, 222.1, 227.5, 237.9", \ + "243.2, 243.2, 243.2, 248.6, 259.1", \ + "280.3, 280.3, 280.3, 285.8, 296.4", \ + "353.5, 353.5, 353.5, 358.9, 369.6", \ + "500.7, 500.7, 500.7, 505.9, 516.6"); + } + fall_transition (inslew_load_5x5__46) { + values ("135.9, 135.9, 135.9, 139.4, 146.2", \ + "162.0, 162.0, 162.0, 165.5, 172.4", \ + "211.6, 211.6, 211.6, 215.1, 222.0", \ + "308.8, 308.8, 308.8, 312.2, 319.1", \ + "501.6, 501.6, 501.6, 505.2, 512.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("57.1, 57.1, 57.1, 62.1, 71.1", \ + "67.4, 67.4, 67.4, 72.4, 81.9", \ + "81.9, 81.9, 81.9, 87.1, 97.0", \ + "105.4, 105.4, 105.4, 110.8, 121.2", \ + "148.5, 148.5, 148.5, 153.9, 164.5"); + } + rise_transition (inslew_load_5x5__46) { + values ("38.7, 38.7, 38.7, 45.2, 57.9", \ + "51.5, 51.5, 51.5, 58.1, 70.9", \ + "75.2, 75.2, 75.2, 81.8, 94.8", \ + "120.9, 120.9, 120.9, 127.5, 140.5", \ + "210.8, 210.8, 210.8, 217.5, 230.8"); + } + cell_fall (inslew_load_5x5__46) { + values ("201.1, 201.1, 201.1, 206.5, 216.8", \ + "211.0, 211.0, 211.0, 216.4, 226.8", \ + "226.9, 226.9, 226.9, 232.3, 242.8", \ + "258.2, 258.2, 258.2, 263.5, 274.2", \ + "322.3, 322.3, 322.3, 327.7, 338.5"); + } + fall_transition (inslew_load_5x5__46) { + values ("123.1, 123.1, 123.1, 126.6, 133.4", \ + "142.8, 142.8, 142.8, 146.3, 153.2", \ + "179.8, 179.8, 179.8, 183.3, 190.2", \ + "252.0, 252.0, 252.0, 255.5, 262.3", \ + "395.4, 395.4, 395.4, 398.8, 405.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("53.2, 53.2, 53.2, 58.3, 67.3", \ + "52.0, 52.0, 52.0, 57.1, 66.4", \ + "43.9, 43.9, 43.9, 49.1, 58.7", \ + "20.3, 20.3, 20.3, 25.6, 35.6", \ + "-35.0, -35.0, -35.0, -29.6, -19.1"); + } + rise_transition (inslew_load_5x5__46) { + values ("39.5, 39.5, 39.5, 46.0, 58.7", \ + "46.8, 46.8, 46.8, 53.4, 66.1", \ + "60.8, 60.8, 60.8, 67.4, 80.3", \ + "87.4, 87.4, 87.4, 93.9, 107.0", \ + "138.5, 138.5, 138.5, 145.2, 158.2"); + } + cell_fall (inslew_load_5x5__46) { + values ("191.5, 191.5, 191.5, 196.8, 207.1", \ + "219.8, 219.8, 219.8, 225.2, 235.6", \ + "266.9, 266.9, 266.9, 272.3, 282.9", \ + "357.2, 357.2, 357.2, 362.6, 373.3", \ + "537.4, 537.4, 537.4, 542.6, 553.4"); + } + fall_transition (inslew_load_5x5__46) { + values ("115.0, 115.0, 115.0, 118.5, 125.3", \ + "142.4, 142.4, 142.4, 145.8, 152.7", \ + "191.5, 191.5, 191.5, 194.9, 201.8", \ + "286.7, 286.7, 286.7, 290.1, 297.0", \ + "476.0, 476.0, 476.0, 479.5, 486.4"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("53.5, 53.5, 53.5, 58.4, 67.4", \ + "56.8, 56.8, 56.8, 61.9, 71.2", \ + "56.5, 56.5, 56.5, 61.6, 71.3", \ + "47.6, 47.6, 47.6, 52.9, 63.1", \ + "23.1, 23.1, 23.1, 28.4, 39.0"); + } + rise_transition (inslew_load_5x5__46) { + values ("36.4, 36.4, 36.4, 42.9, 55.5", \ + "45.6, 45.6, 45.6, 52.1, 64.9", \ + "62.2, 62.2, 62.2, 68.8, 81.7", \ + "93.5, 93.5, 93.5, 100.0, 113.1", \ + "154.0, 154.0, 154.0, 160.7, 173.8"); + } + cell_fall (inslew_load_5x5__46) { + values ("173.5, 173.5, 173.5, 178.9, 189.1", \ + "192.2, 192.2, 192.2, 197.6, 208.0", \ + "221.9, 221.9, 221.9, 227.3, 237.8", \ + "278.5, 278.5, 278.5, 283.8, 294.5", \ + "391.4, 391.4, 391.4, 396.8, 407.6"); + } + fall_transition (inslew_load_5x5__46) { + values ("104.1, 104.1, 104.1, 107.6, 114.3", \ + "125.8, 125.8, 125.8, 129.3, 136.1", \ + "164.6, 164.6, 164.6, 168.0, 174.9", \ + "240.0, 240.0, 240.0, 243.5, 250.4", \ + "390.3, 390.3, 390.3, 393.7, 400.6"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("45.5, 45.5, 45.5, 50.4, 59.2", \ + "44.6, 44.6, 44.6, 49.7, 58.7", \ + "35.5, 35.5, 35.5, 40.6, 50.1", \ + "8.7, 8.7, 8.7, 14.0, 23.9", \ + "-53.4, -53.4, -53.4, -48.0, -37.6"); + } + rise_transition (inslew_load_5x5__46) { + values ("31.5, 31.5, 31.5, 38.0, 50.6", \ + "39.0, 39.0, 39.0, 45.5, 58.2", \ + "52.2, 52.2, 52.2, 58.8, 71.6", \ + "76.4, 76.4, 76.4, 83.0, 95.9", \ + "122.5, 122.5, 122.5, 129.1, 142.1"); + } + cell_fall (inslew_load_5x5__46) { + values ("136.4, 136.4, 136.4, 141.7, 151.6", \ + "159.1, 159.1, 159.1, 164.4, 174.6", \ + "196.6, 196.6, 196.6, 202.0, 212.5", \ + "269.9, 269.9, 269.9, 275.3, 285.9", \ + "412.5, 412.5, 412.5, 417.9, 428.7"); + } + fall_transition (inslew_load_5x5__46) { + values ("81.0, 81.0, 81.0, 84.5, 91.1", \ + "102.6, 102.6, 102.6, 106.1, 112.8", \ + "140.9, 140.9, 140.9, 144.3, 151.2", \ + "217.0, 217.0, 217.0, 220.4, 227.3", \ + "368.0, 368.0, 368.0, 371.4, 378.3"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("45.8, 45.8, 45.8, 50.8, 59.6", \ + "41.4, 41.4, 41.4, 46.4, 55.5", \ + "26.2, 26.2, 26.2, 31.3, 40.8", \ + "-12.6, -12.6, -12.6, -7.4, 2.4", \ + "-99.9, -99.9, -99.9, -94.5, -84.2"); + } + rise_transition (inslew_load_5x5__46) { + values ("34.6, 34.6, 34.6, 41.1, 53.7", \ + "40.7, 40.7, 40.7, 47.2, 60.0", \ + "51.8, 51.8, 51.8, 58.3, 71.1", \ + "72.1, 72.1, 72.1, 78.6, 91.6", \ + "110.6, 110.6, 110.6, 117.1, 130.2"); + } + cell_fall (inslew_load_5x5__46) { + values ("152.8, 152.8, 152.8, 158.2, 168.2", \ + "183.4, 183.4, 183.4, 188.8, 199.1", \ + "235.3, 235.3, 235.3, 240.7, 251.2", \ + "337.4, 337.4, 337.4, 342.7, 353.4", \ + "535.5, 535.5, 535.5, 540.8, 551.5"); + } + fall_transition (inslew_load_5x5__46) { + values ("91.0, 91.0, 91.0, 94.5, 101.2", \ + "117.2, 117.2, 117.2, 120.7, 127.4", \ + "163.7, 163.7, 163.7, 167.1, 174.0", \ + "255.5, 255.5, 255.5, 258.9, 265.8", \ + "437.2, 437.2, 437.2, 440.7, 447.6"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("34.5, 34.5, 34.5, 39.3, 47.7", \ + "30.0, 30.0, 30.0, 34.9, 43.7", \ + "14.0, 14.0, 14.0, 19.0, 28.2", \ + "-25.8, -25.8, -25.8, -20.6, -11.0", \ + "-113.0, -113.0, -113.0, -107.6, -97.4"); + } + rise_transition (inslew_load_5x5__46) { + values ("25.0, 25.0, 25.0, 31.5, 44.0", \ + "31.6, 31.6, 31.6, 38.1, 50.7", \ + "42.6, 42.6, 42.6, 49.1, 61.9", \ + "62.3, 62.3, 62.3, 68.9, 81.7", \ + "99.6, 99.6, 99.6, 106.1, 119.2"); + } + cell_fall (inslew_load_5x5__46) { + values ("90.2, 90.2, 90.2, 95.3, 104.7", \ + "118.1, 118.1, 118.1, 123.4, 133.2", \ + "158.0, 158.0, 158.0, 163.4, 173.7", \ + "243.2, 243.2, 243.2, 248.6, 259.1", \ + "410.2, 410.2, 410.2, 415.6, 426.3"); + } + fall_transition (inslew_load_5x5__46) { + values ("52.9, 52.9, 52.9, 56.3, 63.0", \ + "76.5, 76.5, 76.5, 79.9, 86.6", \ + "113.0, 113.0, 113.0, 116.4, 123.2", \ + "189.3, 189.3, 189.3, 192.8, 199.7", \ + "339.2, 339.2, 339.2, 342.6, 349.5"); + } + } + timing (maxd_q_i7_positive_unate) { + related_pin : "i7" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("35.9, 35.9, 35.9, 40.8, 49.4", \ + "28.9, 28.9, 28.9, 33.8, 42.6", \ + "8.3, 8.3, 8.3, 13.3, 22.5", \ + "-41.3, -41.3, -41.3, -36.1, -26.5", \ + "-149.6, -149.6, -149.6, -144.3, -134.2"); + } + rise_transition (inslew_load_5x5__46) { + values ("28.4, 28.4, 28.4, 34.9, 47.5", \ + "33.8, 33.8, 33.8, 40.3, 52.9", \ + "43.1, 43.1, 43.1, 49.6, 62.3", \ + "59.6, 59.6, 59.6, 66.2, 79.1", \ + "90.5, 90.5, 90.5, 97.1, 110.1"); + } + cell_fall (inslew_load_5x5__46) { + values ("106.0, 106.0, 106.0, 111.2, 120.7", \ + "140.6, 140.6, 140.6, 145.9, 155.9", \ + "193.5, 193.5, 193.5, 198.9, 209.3", \ + "303.3, 303.3, 303.3, 308.7, 319.3", \ + "519.1, 519.1, 519.1, 524.5, 535.2"); + } + fall_transition (inslew_load_5x5__46) { + values ("62.3, 62.3, 62.3, 65.7, 72.4", \ + "89.7, 89.7, 89.7, 93.2, 99.9", \ + "133.1, 133.1, 133.1, 136.6, 143.4", \ + "222.3, 222.3, 222.3, 225.8, 232.7", \ + "399.9, 399.9, 399.9, 403.4, 410.2"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__46) { + values ("515.1, 515.1, 515.1, 546.0, 607.9", \ + "623.2, 623.2, 623.2, 654.1, 715.9", \ + "837.7, 837.7, 837.7, 868.6, 930.4", \ + "1264.4, 1264.4, 1264.4, 1295.3, 1357.1", \ + "2115.8, 2115.8, 2115.8, 2146.7, 2208.5"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("1173.6, 1173.6, 1173.6, 1204.5, 1266.3", \ + "1388.8, 1388.8, 1388.8, 1419.7, 1481.5", \ + "1807.5, 1807.5, 1807.5, 1838.4, 1900.2", \ + "2635.7, 2635.7, 2635.7, 2666.6, 2728.4", \ + "4286.6, 4286.6, 4286.6, 4317.5, 4379.3"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__46) { + values ("463.7, 463.7, 463.7, 494.6, 556.5", \ + "583.0, 583.0, 583.0, 613.9, 675.8", \ + "817.3, 817.3, 817.3, 848.2, 910.1", \ + "1282.2, 1282.2, 1282.2, 1313.1, 1374.9", \ + "2209.3, 2209.3, 2209.3, 2240.2, 2302.1"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("1060.9, 1060.9, 1060.9, 1091.8, 1153.6", \ + "1221.7, 1221.7, 1221.7, 1252.6, 1314.5", \ + "1533.3, 1533.3, 1533.3, 1564.2, 1626.0", \ + "2147.8, 2147.8, 2147.8, 2178.8, 2240.6", \ + "3372.7, 3372.7, 3372.7, 3403.6, 3465.5"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__46) { + values ("471.5, 471.5, 471.5, 502.4, 564.3", \ + "533.2, 533.2, 533.2, 564.1, 626.0", \ + "655.1, 655.1, 655.1, 686.0, 747.8", \ + "895.3, 895.3, 895.3, 926.2, 988.0", \ + "1370.9, 1370.9, 1370.9, 1401.8, 1463.6"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("1004.8, 1004.8, 1004.8, 1035.7, 1097.6", \ + "1221.4, 1221.4, 1221.4, 1252.3, 1314.1", \ + "1629.6, 1629.6, 1629.6, 1660.5, 1722.3", \ + "2432.7, 2432.7, 2432.7, 2463.6, 2525.4", \ + "4034.9, 4034.9, 4034.9, 4065.8, 4127.7"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__46) { + values ("420.4, 420.4, 420.4, 451.4, 513.2", \ + "492.6, 492.6, 492.6, 523.5, 585.3", \ + "631.9, 631.9, 631.9, 662.8, 724.6", \ + "905.8, 905.8, 905.8, 936.7, 998.5", \ + "1449.1, 1449.1, 1449.1, 1480.0, 1541.8"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("905.5, 905.5, 905.5, 936.4, 998.3", \ + "1076.6, 1076.6, 1076.6, 1107.5, 1169.3", \ + "1398.1, 1398.1, 1398.1, 1429.0, 1490.8", \ + "2031.7, 2031.7, 2031.7, 2062.6, 2124.4", \ + "3296.2, 3296.2, 3296.2, 3327.1, 3389.0"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__46) { + values ("349.5, 349.5, 349.5, 380.4, 442.2", \ + "400.0, 400.0, 400.0, 430.9, 492.7", \ + "496.7, 496.7, 496.7, 527.6, 589.4", \ + "684.6, 684.6, 684.6, 715.5, 777.3", \ + "1054.6, 1054.6, 1054.6, 1085.5, 1147.4"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("711.2, 711.2, 711.2, 742.1, 803.9", \ + "878.4, 878.4, 878.4, 909.3, 971.1", \ + "1191.1, 1191.1, 1191.1, 1222.0, 1283.8", \ + "1814.7, 1814.7, 1814.7, 1845.6, 1907.4", \ + "3056.4, 3056.4, 3056.4, 3087.3, 3149.1"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__46) { + values ("401.1, 401.1, 401.1, 432.0, 493.8", \ + "444.0, 444.0, 444.0, 474.9, 536.7", \ + "526.7, 526.7, 526.7, 557.6, 619.5", \ + "687.7, 687.7, 687.7, 718.6, 780.4", \ + "1004.2, 1004.2, 1004.2, 1035.1, 1096.9"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("802.2, 802.2, 802.2, 833.1, 894.9", \ + "1006.3, 1006.3, 1006.3, 1037.2, 1099.0", \ + "1388.0, 1388.0, 1388.0, 1419.0, 1480.8", \ + "2146.6, 2146.6, 2146.6, 2177.5, 2239.3", \ + "3656.1, 3656.1, 3656.1, 3687.0, 3748.8"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__46) { + values ("262.8, 262.8, 262.8, 293.7, 355.6", \ + "301.4, 301.4, 301.4, 332.3, 394.1", \ + "373.7, 373.7, 373.7, 404.6, 466.4", \ + "513.1, 513.1, 513.1, 544.0, 605.8", \ + "787.5, 787.5, 787.5, 818.4, 880.2"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("484.9, 484.9, 484.9, 515.8, 577.7", \ + "656.8, 656.8, 656.8, 687.7, 749.5", \ + "953.1, 953.1, 953.1, 984.0, 1045.8", \ + "1561.1, 1561.1, 1561.1, 1592.0, 1653.8", \ + "2764.5, 2764.5, 2764.5, 2795.5, 2857.3"); + } + } + internal_power (energy_pos_q_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__46) { + values ("315.8, 315.8, 315.8, 346.7, 408.5", \ + "348.1, 348.1, 348.1, 379.1, 440.9", \ + "409.5, 409.5, 409.5, 440.4, 502.3", \ + "527.6, 527.6, 527.6, 558.5, 620.3", \ + "758.0, 758.0, 758.0, 788.9, 850.7"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("570.4, 570.4, 570.4, 601.3, 663.1", \ + "772.8, 772.8, 772.8, 803.7, 865.5", \ + "1126.6, 1126.6, 1126.6, 1157.5, 1219.4", \ + "1845.9, 1845.9, 1845.9, 1876.8, 1938.6", \ + "3280.2, 3280.2, 3280.2, 3311.1, 3373.0"); + } + } + } + } + + cell (oa2a2a2a24_x4) { + area : 0.0 ; + cell_leakage_power : 40 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & (i4 ^ i5) & (i6 ^ i7))" ; + value : 28 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & (i4 ^ i5) & (i6 ^ i7))))))" ; + value : 22 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 20 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & i4 & i5 & (i6 ^ i7))" ; + value : 42 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 ^ i3) & !(i4) & !(i5) & i6 & i7)" ; + value : 36 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i0) & i1 & !(i2) & !(i3) & !(i4) & !(i5) & i6 & i7))" ; + value : 47 ; + } + leakage_power () { + when : "(i2 & i3 & i4 & i5 & i6 & i7)" ; + value : 71 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i2) & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i1) & ((i2 & i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & !(i3) & i4 & i5 & (i6 ^ i7)))))) | (!(i0) & ((i1 & ((i2 & i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & !(i3) & i4 & i5 & (i6 ^ i7)))) | (i2 & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 35 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))) | (!(i1) & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & !(i3) & i4 & i5 & !(i6) & !(i7)))))) | (!(i0) & ((i1 & ((i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & !(i3) & i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))" ; + value : 23 ; + } + leakage_power () { + when : "((i0 & i1 & (((i2 | i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!((i2 | i3)) & ((i4 | i5) ^ (i6 | i7))))) | (i2 & i3 & !(i4) & !(i5) & !(i6) & !(i7)))" ; + value : 21 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i1) & (i2 ^ i3) & (i4 ^ i5) & i6 & i7))))" ; + value : 60 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3) & !(i4) & !(i5) & i6 & i7)" ; + value : 49 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & (i4 | i5) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (!(i0) & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & (i4 | i5) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (!(i1) & ((i2 & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))" ; + value : 48 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & !(i3) & i4 & i5 & i6 & i7))) | (!(i1) & ((i2 & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i3 & i4 & i5 & !(i6) & !(i7)))))) | (!(i0) & ((!(i1) & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i2 & ((i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))) | (i3 & i4 & i5 & !(i6) & !(i7)))))" ; + value : 24 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((!(i2) & ((!(i3) & (i4 | i5) & i6 & i7) | (i4 & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7)))" ; + value : 72 ; + } + leakage_power () { + when : "(i7 & i6 & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 73 ; + } + leakage_power () { + when : "(!((i0 & i1)) & !((i2 & i3)) & !((i4 & i5)) & (!(i6) | !(i7)))" ; + value : 5.4 ; + } + pin (i7) { + direction : input ; + capacitance : 6.66 ; + } + pin (i6) { + direction : input ; + capacitance : 6.52 ; + } + pin (i5) { + direction : input ; + capacitance : 6.53 ; + } + pin (i4) { + direction : input ; + capacitance : 6.53 ; + } + pin (i3) { + direction : input ; + capacitance : 6.52 ; + } + pin (i2) { + direction : input ; + capacitance : 6.52 ; + } + pin (i1) { + direction : input ; + capacitance : 6.82 ; + } + pin (i0) { + direction : input ; + capacitance : 6.82 ; + } + pin (q) { + function : "((i7 & ((i5 & ((i3 & ((i0 & i1) | i2 | i4 | i6)) | (i0 & i1) | i4 | i6)) | (i3 & ((i0 & i1) | i2 | i6)) | (i0 & i1) | i6)) | (i5 & ((i3 & ((i0 & i1) | i2 | i4)) | (i0 & i1) | i4)) | (i3 & ((i0 & i1) | i2)) | (i0 & i1))" ; + direction : output ; + capacitance : 4.46 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("61.2, 61.2, 61.2, 65.6, 73.7", \ + "65.0, 65.0, 65.0, 69.5, 77.8", \ + "67.5, 67.5, 67.5, 71.9, 80.5", \ + "65.8, 65.8, 65.8, 70.4, 79.2", \ + "56.4, 56.4, 56.4, 61.1, 70.2"); + } + rise_transition (inslew_load_5x5__47) { + values ("46.5, 46.5, 46.5, 52.3, 63.8", \ + "57.2, 57.2, 57.2, 63.0, 74.5", \ + "77.7, 77.7, 77.7, 83.5, 95.1", \ + "117.0, 117.0, 117.0, 122.9, 134.5", \ + "194.2, 194.2, 194.2, 200.0, 211.6"); + } + cell_fall (inslew_load_5x5__47) { + values ("244.5, 244.5, 244.5, 248.7, 256.7", \ + "270.2, 270.2, 270.2, 274.4, 282.5", \ + "315.1, 315.1, 315.1, 319.5, 327.7", \ + "402.9, 402.9, 402.9, 407.3, 415.8", \ + "578.8, 578.8, 578.8, 583.1, 592.0"); + } + fall_transition (inslew_load_5x5__47) { + values ("151.4, 151.4, 151.4, 154.0, 159.5", \ + "180.4, 180.4, 180.4, 183.1, 188.5", \ + "234.8, 234.8, 234.8, 237.7, 243.0", \ + "341.8, 341.8, 341.8, 344.7, 350.2", \ + "554.2, 554.2, 554.2, 557.1, 562.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("61.4, 61.4, 61.4, 65.8, 73.9", \ + "70.4, 70.4, 70.4, 74.9, 83.2", \ + "82.0, 82.0, 82.0, 86.5, 95.0", \ + "97.9, 97.9, 97.9, 102.5, 111.4", \ + "123.9, 123.9, 123.9, 128.5, 137.7"); + } + rise_transition (inslew_load_5x5__47) { + values ("43.2, 43.2, 43.2, 49.0, 60.4", \ + "56.1, 56.1, 56.1, 61.9, 73.4", \ + "79.8, 79.8, 79.8, 85.7, 97.2", \ + "125.2, 125.2, 125.2, 131.1, 142.7", \ + "214.3, 214.3, 214.3, 220.1, 231.8"); + } + cell_fall (inslew_load_5x5__47) { + values ("222.3, 222.3, 222.3, 226.5, 234.5", \ + "236.7, 236.7, 236.7, 240.9, 249.0", \ + "260.4, 260.4, 260.4, 264.7, 272.8", \ + "306.3, 306.3, 306.3, 310.7, 319.1", \ + "399.4, 399.4, 399.4, 403.8, 412.6"); + } + fall_transition (inslew_load_5x5__47) { + values ("137.8, 137.8, 137.8, 140.4, 145.9", \ + "160.0, 160.0, 160.0, 162.7, 168.2", \ + "201.9, 201.9, 201.9, 204.7, 210.1", \ + "283.6, 283.6, 283.6, 286.6, 292.0", \ + "445.8, 445.8, 445.8, 448.7, 454.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("68.2, 68.2, 68.2, 72.7, 80.9", \ + "69.2, 69.2, 69.2, 73.6, 82.0", \ + "64.6, 64.6, 64.6, 69.1, 77.6", \ + "46.1, 46.1, 46.1, 50.7, 59.4", \ + "-0.9, -0.9, -0.9, 3.7, 12.8"); + } + rise_transition (inslew_load_5x5__47) { + values ("51.7, 51.7, 51.7, 57.5, 68.9", \ + "60.1, 60.1, 60.1, 65.9, 77.4", \ + "76.3, 76.3, 76.3, 82.1, 93.7", \ + "106.9, 106.9, 106.9, 112.8, 124.4", \ + "165.9, 165.9, 165.9, 171.7, 183.4"); + } + cell_fall (inslew_load_5x5__47) { + values ("208.2, 208.2, 208.2, 212.3, 220.4", \ + "233.4, 233.4, 233.4, 237.6, 245.7", \ + "274.7, 274.7, 274.7, 279.0, 287.1", \ + "353.5, 353.5, 353.5, 357.9, 366.3", \ + "510.2, 510.2, 510.2, 514.6, 523.4"); + } + fall_transition (inslew_load_5x5__47) { + values ("127.6, 127.6, 127.6, 130.3, 135.7", \ + "153.1, 153.1, 153.1, 155.8, 161.2", \ + "199.0, 199.0, 199.0, 201.7, 207.1", \ + "287.9, 287.9, 287.9, 290.8, 296.2", \ + "464.8, 464.8, 464.8, 467.7, 473.4"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("68.9, 68.9, 68.9, 73.4, 81.5", \ + "75.2, 75.2, 75.2, 79.6, 88.0", \ + "79.0, 79.0, 79.0, 83.5, 92.0", \ + "76.3, 76.3, 76.3, 80.9, 89.7", \ + "60.9, 60.9, 60.9, 65.5, 74.6"); + } + rise_transition (inslew_load_5x5__47) { + values ("48.3, 48.3, 48.3, 54.1, 65.5", \ + "58.9, 58.9, 58.9, 64.7, 76.2", \ + "78.3, 78.3, 78.3, 84.2, 95.7", \ + "114.5, 114.5, 114.5, 120.4, 132.0", \ + "184.1, 184.1, 184.1, 190.0, 201.6"); + } + cell_fall (inslew_load_5x5__47) { + values ("191.5, 191.5, 191.5, 195.7, 203.9", \ + "207.9, 207.9, 207.9, 212.0, 220.0", \ + "233.1, 233.1, 233.1, 237.3, 245.4", \ + "280.7, 280.7, 280.7, 285.1, 293.3", \ + "375.3, 375.3, 375.3, 379.7, 388.4"); + } + fall_transition (inslew_load_5x5__47) { + values ("117.4, 117.4, 117.4, 120.1, 125.4", \ + "137.6, 137.6, 137.6, 140.3, 145.7", \ + "173.9, 173.9, 173.9, 176.6, 182.0", \ + "244.2, 244.2, 244.2, 247.0, 252.4", \ + "384.4, 384.4, 384.4, 387.3, 393.0"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("61.1, 61.1, 61.1, 65.5, 73.5", \ + "63.2, 63.2, 63.2, 67.7, 75.9", \ + "58.7, 58.7, 58.7, 63.1, 71.6", \ + "38.0, 38.0, 38.0, 42.6, 51.2", \ + "-15.5, -15.5, -15.5, -10.9, -1.9"); + } + rise_transition (inslew_load_5x5__47) { + values ("42.9, 42.9, 42.9, 48.7, 60.1", \ + "51.7, 51.7, 51.7, 57.5, 69.0", \ + "67.4, 67.4, 67.4, 73.2, 84.7", \ + "95.6, 95.6, 95.6, 101.5, 113.1", \ + "148.9, 148.9, 148.9, 154.8, 166.4"); + } + cell_fall (inslew_load_5x5__47) { + values ("157.5, 157.5, 157.5, 161.6, 170.1", \ + "177.8, 177.8, 177.8, 182.0, 190.2", \ + "211.4, 211.4, 211.4, 215.5, 223.6", \ + "275.9, 275.9, 275.9, 280.2, 288.4", \ + "400.5, 400.5, 400.5, 404.9, 413.5"); + } + fall_transition (inslew_load_5x5__47) { + values ("96.0, 96.0, 96.0, 98.7, 103.9", \ + "116.1, 116.1, 116.1, 118.8, 124.1", \ + "151.7, 151.7, 151.7, 154.4, 159.8", \ + "222.6, 222.6, 222.6, 225.4, 230.8", \ + "363.4, 363.4, 363.4, 366.3, 371.9"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("60.8, 60.8, 60.8, 65.2, 73.3", \ + "58.5, 58.5, 58.5, 63.0, 71.2", \ + "47.0, 47.0, 47.0, 51.4, 60.0", \ + "13.6, 13.6, 13.6, 18.1, 26.6", \ + "-66.1, -66.1, -66.1, -61.5, -52.6"); + } + rise_transition (inslew_load_5x5__47) { + values ("46.3, 46.3, 46.3, 52.1, 63.6", \ + "53.2, 53.2, 53.2, 59.0, 70.5", \ + "66.3, 66.3, 66.3, 72.1, 83.6", \ + "90.0, 90.0, 90.0, 95.9, 107.5", \ + "134.5, 134.5, 134.5, 140.4, 152.0"); + } + cell_fall (inslew_load_5x5__47) { + values ("172.6, 172.6, 172.6, 176.7, 185.0", \ + "200.2, 200.2, 200.2, 204.4, 212.4", \ + "247.0, 247.0, 247.0, 251.2, 259.3", \ + "337.9, 337.9, 337.9, 342.3, 350.6", \ + "514.2, 514.2, 514.2, 518.6, 527.4"); + } + fall_transition (inslew_load_5x5__47) { + values ("105.3, 105.3, 105.3, 108.1, 113.3", \ + "129.8, 129.8, 129.8, 132.5, 137.9", \ + "173.2, 173.2, 173.2, 175.8, 181.2", \ + "258.7, 258.7, 258.7, 261.5, 266.9", \ + "428.3, 428.3, 428.3, 431.2, 437.0"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("50.7, 50.7, 50.7, 55.0, 63.0", \ + "49.6, 49.6, 49.6, 54.0, 62.1", \ + "38.5, 38.5, 38.5, 42.9, 51.3", \ + "5.2, 5.2, 5.2, 9.7, 18.3", \ + "-73.6, -73.6, -73.6, -69.0, -60.2"); + } + rise_transition (inslew_load_5x5__47) { + values ("35.9, 35.9, 35.9, 41.8, 53.1", \ + "43.7, 43.7, 43.7, 49.6, 61.0", \ + "57.1, 57.1, 57.1, 62.9, 74.3", \ + "80.4, 80.4, 80.4, 86.2, 97.8", \ + "123.8, 123.8, 123.8, 129.7, 141.3"); + } + cell_fall (inslew_load_5x5__47) { + values ("116.0, 116.0, 116.0, 120.5, 128.9", \ + "141.4, 141.4, 141.4, 145.5, 154.1", \ + "178.5, 178.5, 178.5, 182.7, 190.7", \ + "255.3, 255.3, 255.3, 259.5, 267.7", \ + "404.7, 404.7, 404.7, 409.1, 417.6"); + } + fall_transition (inslew_load_5x5__47) { + values ("70.2, 70.2, 70.2, 72.7, 77.9", \ + "92.0, 92.0, 92.0, 94.8, 99.9", \ + "126.1, 126.1, 126.1, 128.8, 134.2", \ + "197.2, 197.2, 197.2, 200.0, 205.3", \ + "337.2, 337.2, 337.2, 340.1, 345.7"); + } + } + timing (maxd_q_i7_positive_unate) { + related_pin : "i7" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("51.0, 51.0, 51.0, 55.4, 63.4", \ + "46.3, 46.3, 46.3, 50.8, 58.9", \ + "29.7, 29.7, 29.7, 34.2, 42.5", \ + "-14.0, -14.0, -14.0, -9.6, -1.0", \ + "-114.9, -114.9, -114.9, -110.3, -101.6"); + } + rise_transition (inslew_load_5x5__47) { + values ("39.4, 39.4, 39.4, 45.2, 56.6", \ + "45.6, 45.6, 45.6, 51.4, 62.8", \ + "56.8, 56.8, 56.8, 62.6, 74.1", \ + "76.5, 76.5, 76.5, 82.3, 93.9", \ + "112.5, 112.5, 112.5, 118.3, 130.0"); + } + cell_fall (inslew_load_5x5__47) { + values ("130.3, 130.3, 130.3, 134.6, 143.1", \ + "162.0, 162.0, 162.0, 166.1, 174.5", \ + "211.1, 211.1, 211.1, 215.3, 223.3", \ + "310.4, 310.4, 310.4, 314.8, 323.0", \ + "505.0, 505.0, 505.0, 509.3, 518.1"); + } + fall_transition (inslew_load_5x5__47) { + values ("79.1, 79.1, 79.1, 81.7, 86.8", \ + "104.5, 104.5, 104.5, 107.2, 112.5", \ + "145.0, 145.0, 145.0, 147.7, 153.2", \ + "228.2, 228.2, 228.2, 231.0, 236.3", \ + "393.7, 393.7, 393.7, 396.7, 402.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__47) { + values ("786.8, 786.8, 786.8, 842.5, 954.0", \ + "927.2, 927.2, 927.2, 982.9, 1094.4", \ + "1205.2, 1205.2, 1205.2, 1261.0, 1372.5", \ + "1754.4, 1754.4, 1754.4, 1810.1, 1921.6", \ + "2845.8, 2845.8, 2845.8, 2901.5, 3013.0"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("2068.6, 2068.6, 2068.6, 2124.4, 2235.9", \ + "2448.8, 2448.8, 2448.8, 2504.6, 2616.1", \ + "3178.4, 3178.4, 3178.4, 3234.2, 3345.7", \ + "4619.5, 4619.5, 4619.5, 4675.2, 4786.7", \ + "7487.7, 7487.7, 7487.7, 7543.5, 7655.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__47) { + values ("716.9, 716.9, 716.9, 772.7, 884.2", \ + "877.3, 877.3, 877.3, 933.1, 1044.6", \ + "1188.9, 1188.9, 1188.9, 1244.7, 1356.2", \ + "1802.4, 1802.4, 1802.4, 1858.1, 1969.6", \ + "3021.4, 3021.4, 3021.4, 3077.1, 3188.6"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("1880.7, 1880.7, 1880.7, 1936.5, 2048.0", \ + "2172.1, 2172.1, 2172.1, 2227.9, 2339.4", \ + "2731.3, 2731.3, 2731.3, 2787.1, 2898.6", \ + "3831.5, 3831.5, 3831.5, 3887.2, 3998.7", \ + "6020.1, 6020.1, 6020.1, 6075.9, 6187.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__47) { + values ("788.8, 788.8, 788.8, 844.6, 956.1", \ + "883.0, 883.0, 883.0, 938.8, 1050.3", \ + "1068.5, 1068.5, 1068.5, 1124.3, 1235.8", \ + "1430.4, 1430.4, 1430.4, 1486.1, 1597.6", \ + "2140.5, 2140.5, 2140.5, 2196.3, 2307.8"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("1753.3, 1753.3, 1753.3, 1809.1, 1920.5", \ + "2080.0, 2080.0, 2080.0, 2135.8, 2247.3", \ + "2687.2, 2687.2, 2687.2, 2742.9, 2854.4", \ + "3876.6, 3876.6, 3876.6, 3932.4, 4043.9", \ + "6247.7, 6247.7, 6247.7, 6303.4, 6414.9"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__47) { + values ("725.4, 725.4, 725.4, 781.1, 892.6", \ + "838.4, 838.4, 838.4, 894.1, 1005.6", \ + "1054.7, 1054.7, 1054.7, 1110.4, 1221.9", \ + "1472.5, 1472.5, 1472.5, 1528.2, 1639.7", \ + "2292.8, 2292.8, 2292.8, 2348.6, 2460.0"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("1609.6, 1609.6, 1609.6, 1665.4, 1776.9", \ + "1867.6, 1867.6, 1867.6, 1923.4, 2034.9", \ + "2346.3, 2346.3, 2346.3, 2402.1, 2513.6", \ + "3284.6, 3284.6, 3284.6, 3340.4, 3451.9", \ + "5158.8, 5158.8, 5158.8, 5214.5, 5326.0"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__47) { + values ("634.5, 634.5, 634.5, 690.3, 801.8", \ + "719.5, 719.5, 719.5, 775.3, 886.8", \ + "878.4, 878.4, 878.4, 934.2, 1045.6", \ + "1179.1, 1179.1, 1179.1, 1234.8, 1346.3", \ + "1761.9, 1761.9, 1761.9, 1817.6, 1929.1"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("1323.3, 1323.3, 1323.3, 1379.1, 1490.6", \ + "1577.2, 1577.2, 1577.2, 1633.0, 1744.5", \ + "2043.6, 2043.6, 2043.6, 2099.3, 2210.8", \ + "2973.7, 2973.7, 2973.7, 3029.4, 3140.9", \ + "4826.7, 4826.7, 4826.7, 4882.4, 4993.9"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__47) { + values ("699.0, 699.0, 699.0, 754.7, 866.2", \ + "767.9, 767.9, 767.9, 823.7, 935.2", \ + "902.2, 902.2, 902.2, 957.9, 1069.4", \ + "1158.1, 1158.1, 1158.1, 1213.9, 1325.4", \ + "1652.0, 1652.0, 1652.0, 1707.8, 1819.3"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("1455.1, 1455.1, 1455.1, 1510.8, 1622.3", \ + "1764.7, 1764.7, 1764.7, 1820.4, 1931.9", \ + "2333.4, 2333.4, 2333.4, 2389.1, 2500.6", \ + "3463.3, 3463.3, 3463.3, 3519.0, 3630.5", \ + "5709.7, 5709.7, 5709.7, 5765.4, 5876.9"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__47) { + values ("523.3, 523.3, 523.3, 579.0, 690.5", \ + "592.2, 592.2, 592.2, 647.9, 759.4", \ + "717.4, 717.4, 717.4, 773.2, 884.7", \ + "950.4, 950.4, 950.4, 1006.1, 1117.6", \ + "1398.6, 1398.6, 1398.6, 1454.4, 1565.9"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("989.2, 989.2, 989.2, 1045.0, 1156.5", \ + "1254.7, 1254.7, 1254.7, 1310.4, 1421.9", \ + "1698.7, 1698.7, 1698.7, 1754.4, 1865.9", \ + "2613.3, 2613.3, 2613.3, 2669.0, 2780.5", \ + "4425.7, 4425.7, 4425.7, 4481.5, 4593.0"); + } + } + internal_power (energy_pos_q_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__47) { + values ("588.4, 588.4, 588.4, 644.2, 755.7", \ + "644.3, 644.3, 644.3, 700.0, 811.5", \ + "750.0, 750.0, 750.0, 805.8, 917.3", \ + "947.1, 947.1, 947.1, 1002.9, 1114.4", \ + "1321.4, 1321.4, 1321.4, 1377.1, 1488.6"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("1113.4, 1113.4, 1113.4, 1169.1, 1280.6", \ + "1425.2, 1425.2, 1425.2, 1480.9, 1592.4", \ + "1954.4, 1954.4, 1954.4, 2010.2, 2121.7", \ + "3033.1, 3033.1, 3033.1, 3088.8, 3200.3", \ + "5186.2, 5186.2, 5186.2, 5241.9, 5353.4"); + } + } + } + } + + cell (oa2ao222_x2) { + area : 0.0 ; + cell_leakage_power : 10 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & !(i4))" ; + value : 6.1 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & i0)" ; + value : 11 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 5.7 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & i4)" ; + value : 15 ; + } + leakage_power () { + when : "((!((i0 | i1)) & i2 & i4) | (i2 & i3 & i4))" ; + value : 18 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & (i3 ^ i4)) | (!(i2) & i3 & i4))) | (!(i2) & i3 & i4))" ; + value : 12 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!((i2 | i3)) | !(i4)))" ; + value : 4.4 ; + } + pin (i4) { + direction : input ; + capacitance : 7.41 ; + } + pin (i3) { + direction : input ; + capacitance : 7.49 ; + } + pin (i2) { + direction : input ; + capacitance : 7.45 ; + } + pin (i1) { + direction : input ; + capacitance : 7.57 ; + } + pin (i0) { + direction : input ; + capacitance : 7.69 ; + } + pin (q) { + function : "((i4 & ((i0 & i1) | i3 | i2)) | (i0 & i1))" ; + direction : output ; + capacitance : 3.03 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("42.4, 42.4, 42.4, 47.9, 57.8", \ + "43.3, 43.3, 43.3, 48.9, 59.1", \ + "40.1, 40.1, 40.1, 45.7, 56.3", \ + "28.0, 28.0, 28.0, 33.8, 44.9", \ + "-0.8, -0.8, -0.8, 5.0, 16.3"); + } + rise_transition (inslew_load_5x5__12) { + values ("34.2, 34.2, 34.2, 42.0, 57.3", \ + "45.0, 45.0, 45.0, 52.8, 68.1", \ + "64.4, 64.4, 64.4, 72.2, 87.6", \ + "100.8, 100.8, 100.8, 108.6, 124.1", \ + "171.2, 171.2, 171.2, 179.1, 194.7"); + } + cell_fall (inslew_load_5x5__12) { + values ("122.7, 122.7, 122.7, 127.8, 137.7", \ + "141.1, 141.1, 141.1, 146.3, 156.3", \ + "172.9, 172.9, 172.9, 178.2, 188.5", \ + "235.7, 235.7, 235.7, 241.1, 251.5", \ + "361.8, 361.8, 361.8, 367.2, 377.8"); + } + fall_transition (inslew_load_5x5__12) { + values ("73.5, 73.5, 73.5, 77.0, 83.1", \ + "95.8, 95.8, 95.8, 99.2, 106.0", \ + "137.1, 137.1, 137.1, 140.5, 147.4", \ + "218.1, 218.1, 218.1, 221.3, 228.0", \ + "379.2, 379.2, 379.2, 382.5, 389.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("41.3, 41.3, 41.3, 46.9, 56.7", \ + "46.5, 46.5, 46.5, 52.1, 62.2", \ + "50.9, 50.9, 50.9, 56.6, 67.2", \ + "54.5, 54.5, 54.5, 60.3, 71.4", \ + "57.8, 57.8, 57.8, 63.6, 75.0"); + } + rise_transition (inslew_load_5x5__12) { + values ("30.7, 30.7, 30.7, 38.6, 53.8", \ + "44.0, 44.0, 44.0, 51.8, 67.1", \ + "67.3, 67.3, 67.3, 75.1, 90.5", \ + "110.7, 110.7, 110.7, 118.5, 134.0", \ + "195.1, 195.1, 195.1, 203.0, 218.6"); + } + cell_fall (inslew_load_5x5__12) { + values ("104.7, 104.7, 104.7, 109.8, 119.8", \ + "115.0, 115.0, 115.0, 120.2, 130.0", \ + "132.0, 132.0, 132.0, 137.3, 147.4", \ + "165.9, 165.9, 165.9, 171.2, 181.6", \ + "234.6, 234.6, 234.6, 240.0, 250.5"); + } + fall_transition (inslew_load_5x5__12) { + values ("63.1, 63.1, 63.1, 66.6, 72.5", \ + "81.0, 81.0, 81.0, 84.5, 90.9", \ + "113.8, 113.8, 113.8, 117.2, 124.1", \ + "178.1, 178.1, 178.1, 181.5, 188.2", \ + "306.7, 306.7, 306.7, 309.9, 316.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("32.7, 32.7, 32.7, 38.3, 48.0", \ + "26.3, 26.3, 26.3, 31.8, 41.7", \ + "6.4, 6.4, 6.4, 12.0, 22.2", \ + "-42.4, -42.4, -42.4, -36.7, -26.1", \ + "-149.7, -149.7, -149.7, -143.9, -132.8"); + } + rise_transition (inslew_load_5x5__12) { + values ("27.2, 27.2, 27.2, 35.1, 50.3", \ + "34.2, 34.2, 34.2, 42.0, 57.3", \ + "45.6, 45.6, 45.6, 53.4, 68.7", \ + "65.2, 65.2, 65.2, 73.0, 88.4", \ + "100.8, 100.8, 100.8, 108.6, 124.1"); + } + cell_fall (inslew_load_5x5__12) { + values ("81.2, 81.2, 81.2, 86.7, 96.2", \ + "110.6, 110.6, 110.6, 115.8, 125.8", \ + "158.2, 158.2, 158.2, 163.5, 173.5", \ + "245.4, 245.4, 245.4, 250.7, 261.1", \ + "415.8, 415.8, 415.8, 421.2, 431.7"); + } + fall_transition (inslew_load_5x5__12) { + values ("44.1, 44.1, 44.1, 47.1, 53.0", \ + "65.7, 65.7, 65.7, 69.3, 75.2", \ + "103.4, 103.4, 103.4, 106.8, 113.7", \ + "175.3, 175.3, 175.3, 178.6, 185.4", \ + "315.9, 315.9, 315.9, 319.1, 325.6"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("37.5, 37.5, 37.5, 43.1, 52.9", \ + "33.4, 33.4, 33.4, 38.9, 49.0", \ + "18.8, 18.8, 18.8, 24.4, 34.8", \ + "-18.5, -18.5, -18.5, -12.8, -2.1", \ + "-101.1, -101.1, -101.1, -95.4, -84.1"); + } + rise_transition (inslew_load_5x5__12) { + values ("30.7, 30.7, 30.7, 38.6, 53.8", \ + "38.6, 38.6, 38.6, 46.4, 61.7", \ + "52.3, 52.3, 52.3, 60.1, 75.5", \ + "76.8, 76.8, 76.8, 84.6, 100.0", \ + "122.5, 122.5, 122.5, 130.4, 145.9"); + } + cell_fall (inslew_load_5x5__12) { + values ("103.4, 103.4, 103.4, 108.5, 118.5", \ + "128.3, 128.3, 128.3, 133.5, 143.3", \ + "169.5, 169.5, 169.5, 174.8, 185.0", \ + "248.1, 248.1, 248.1, 253.4, 263.8", \ + "401.5, 401.5, 401.5, 406.9, 417.4"); + } + fall_transition (inslew_load_5x5__12) { + values ("59.4, 59.4, 59.4, 62.9, 68.7", \ + "81.6, 81.6, 81.6, 85.1, 91.5", \ + "120.7, 120.7, 120.7, 124.2, 131.0", \ + "196.9, 196.9, 196.9, 200.3, 207.0", \ + "348.5, 348.5, 348.5, 351.7, 358.3"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__12) { + values ("28.3, 28.3, 28.3, 33.8, 43.4", \ + "26.0, 26.0, 26.0, 31.6, 41.4", \ + "15.4, 15.4, 15.4, 21.0, 31.3", \ + "-12.0, -12.0, -12.0, -6.2, 4.5", \ + "-71.8, -71.8, -71.8, -66.1, -54.8"); + } + rise_transition (inslew_load_5x5__12) { + values ("22.0, 22.0, 22.0, 29.9, 45.1", \ + "32.2, 32.2, 32.2, 40.1, 55.3", \ + "49.0, 49.0, 49.0, 56.8, 72.1", \ + "78.9, 78.9, 78.9, 86.7, 102.1", \ + "135.5, 135.5, 135.5, 143.3, 158.9"); + } + cell_fall (inslew_load_5x5__12) { + values ("49.7, 49.7, 49.7, 54.6, 63.1", \ + "63.9, 63.9, 63.9, 69.4, 78.7", \ + "87.5, 87.5, 87.5, 92.7, 102.7", \ + "131.0, 131.0, 131.0, 136.2, 146.4", \ + "215.2, 215.2, 215.2, 220.6, 231.0"); + } + fall_transition (inslew_load_5x5__12) { + values ("27.0, 27.0, 27.0, 30.1, 35.8", \ + "41.2, 41.2, 41.2, 44.1, 50.0", \ + "66.3, 66.3, 66.3, 69.8, 75.8", \ + "115.3, 115.3, 115.3, 118.7, 125.6", \ + "212.7, 212.7, 212.7, 216.0, 222.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__12) { + values ("479.5, 479.5, 479.5, 517.4, 593.3", \ + "577.4, 577.4, 577.4, 615.3, 691.1", \ + "770.3, 770.3, 770.3, 808.2, 884.0", \ + "1152.4, 1152.4, 1152.4, 1190.3, 1266.1", \ + "1913.9, 1913.9, 1913.9, 1951.8, 2027.6"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("869.7, 869.7, 869.7, 907.6, 983.4", \ + "1113.7, 1113.7, 1113.7, 1151.6, 1227.4", \ + "1585.6, 1585.6, 1585.6, 1623.5, 1699.3", \ + "2520.6, 2520.6, 2520.6, 2558.6, 2634.4", \ + "4387.3, 4387.3, 4387.3, 4425.2, 4501.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__12) { + values ("406.4, 406.4, 406.4, 444.3, 520.2", \ + "517.9, 517.9, 517.9, 555.8, 631.7", \ + "735.8, 735.8, 735.8, 773.7, 849.5", \ + "1167.6, 1167.6, 1167.6, 1205.6, 1281.4", \ + "2028.4, 2028.4, 2028.4, 2066.3, 2142.2"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("743.1, 743.1, 743.1, 781.0, 856.9", \ + "937.3, 937.3, 937.3, 975.2, 1051.0", \ + "1311.7, 1311.7, 1311.7, 1349.6, 1425.4", \ + "2053.3, 2053.3, 2053.3, 2091.2, 2167.0", \ + "3535.7, 3535.7, 3535.7, 3573.6, 3649.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__12) { + values ("373.2, 373.2, 373.2, 411.1, 487.0", \ + "412.6, 412.6, 412.6, 450.5, 526.3", \ + "486.3, 486.3, 486.3, 524.2, 600.1", \ + "627.4, 627.4, 627.4, 665.3, 741.1", \ + "901.9, 901.9, 901.9, 939.8, 1015.6"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("558.4, 558.4, 558.4, 596.3, 672.1", \ + "769.9, 769.9, 769.9, 807.8, 883.6", \ + "1164.7, 1164.7, 1164.7, 1202.6, 1278.4", \ + "1937.8, 1937.8, 1937.8, 1975.8, 2051.6", \ + "3467.6, 3467.6, 3467.6, 3505.5, 3581.3"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__12) { + values ("423.1, 423.1, 423.1, 461.0, 536.8", \ + "477.9, 477.9, 477.9, 515.8, 591.6", \ + "583.5, 583.5, 583.5, 621.4, 697.3", \ + "789.3, 789.3, 789.3, 827.3, 903.1", \ + "1195.0, 1195.0, 1195.0, 1232.9, 1308.7"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("721.8, 721.8, 721.8, 759.7, 835.5", \ + "951.0, 951.0, 951.0, 988.9, 1064.7", \ + "1384.6, 1384.6, 1384.6, 1422.5, 1498.3", \ + "2240.7, 2240.7, 2240.7, 2278.6, 2354.4", \ + "3948.3, 3948.3, 3948.3, 3986.2, 4062.0"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__12) { + values ("288.5, 288.5, 288.5, 326.4, 402.3", \ + "353.3, 353.3, 353.3, 391.3, 467.1", \ + "478.4, 478.4, 478.4, 516.3, 592.1", \ + "724.1, 724.1, 724.1, 762.0, 837.8", \ + "1211.7, 1211.7, 1211.7, 1249.6, 1325.4"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("408.6, 408.6, 408.6, 446.5, 522.3", \ + "575.0, 575.0, 575.0, 613.0, 688.8", \ + "897.0, 897.0, 897.0, 934.9, 1010.8", \ + "1534.4, 1534.4, 1534.4, 1572.3, 1648.1", \ + "2805.2, 2805.2, 2805.2, 2843.2, 2919.0"); + } + } + } + } + + cell (oa2ao222_x4) { + area : 0.0 ; + cell_leakage_power : 10 ; + leakage_power () { + when : "(i0 & i1 & (i2 ^ i3) & !(i4))" ; + value : 6.1 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & i0)" ; + value : 11 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 5.7 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & i4)" ; + value : 15 ; + } + leakage_power () { + when : "((!((i0 | i1)) & i2 & i4) | (i2 & i3 & i4))" ; + value : 18 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & (i3 ^ i4)) | (!(i2) & i3 & i4))) | (!(i2) & i3 & i4))" ; + value : 12 ; + } + leakage_power () { + when : "(!((i0 & i1)) & (!((i2 | i3)) | !(i4)))" ; + value : 5.4 ; + } + pin (i4) { + direction : input ; + capacitance : 6.41 ; + } + pin (i3) { + direction : input ; + capacitance : 6.58 ; + } + pin (i2) { + direction : input ; + capacitance : 6.59 ; + } + pin (i1) { + direction : input ; + capacitance : 6.41 ; + } + pin (i0) { + direction : input ; + capacitance : 6.56 ; + } + pin (q) { + function : "(((i3 | i2) & ((i0 & i1) | i4)) | (i0 & i1))" ; + direction : output ; + capacitance : 4.33 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__39) { + values ("64.3, 64.3, 64.3, 68.7, 76.9", \ + "71.0, 71.0, 71.0, 75.4, 83.8", \ + "79.6, 79.6, 79.6, 84.1, 92.7", \ + "91.7, 91.7, 91.7, 96.3, 105.3", \ + "111.5, 111.5, 111.5, 116.1, 125.2"); + } + rise_transition (inslew_load_5x5__39) { + values ("47.8, 47.8, 47.8, 53.4, 64.5", \ + "59.7, 59.7, 59.7, 65.5, 76.6", \ + "82.8, 82.8, 82.8, 88.5, 99.8", \ + "128.1, 128.1, 128.1, 133.7, 145.0", \ + "216.9, 216.9, 216.9, 222.8, 234.1"); + } + cell_fall (inslew_load_5x5__39) { + values ("145.6, 145.6, 145.6, 150.2, 158.9", \ + "156.1, 156.1, 156.1, 160.7, 169.6", \ + "174.6, 174.6, 174.6, 179.2, 188.1", \ + "212.2, 212.2, 212.2, 216.2, 225.2", \ + "288.5, 288.5, 288.5, 292.6, 300.7"); + } + fall_transition (inslew_load_5x5__39) { + values ("94.0, 94.0, 94.0, 96.7, 102.2", \ + "113.0, 113.0, 113.0, 115.7, 121.1", \ + "149.1, 149.1, 149.1, 151.8, 157.2", \ + "219.8, 219.8, 219.8, 222.7, 228.3", \ + "361.3, 361.3, 361.3, 364.3, 370.2"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__39) { + values ("64.4, 64.4, 64.4, 68.8, 76.9", \ + "77.0, 77.0, 77.0, 81.4, 89.8", \ + "95.6, 95.6, 95.6, 100.2, 108.8", \ + "127.1, 127.1, 127.1, 131.8, 140.8", \ + "185.5, 185.5, 185.5, 190.1, 199.2"); + } + rise_transition (inslew_load_5x5__39) { + values ("44.2, 44.2, 44.2, 49.8, 60.9", \ + "58.4, 58.4, 58.4, 64.1, 75.3", \ + "84.9, 84.9, 84.9, 90.6, 101.9", \ + "136.3, 136.3, 136.3, 141.9, 153.2", \ + "237.1, 237.1, 237.1, 243.0, 254.4"); + } + cell_fall (inslew_load_5x5__39) { + values ("130.6, 130.6, 130.6, 135.2, 143.9", \ + "133.2, 133.2, 133.2, 137.8, 146.6", \ + "136.4, 136.4, 136.4, 141.0, 149.9", \ + "143.6, 143.6, 143.6, 147.9, 157.0", \ + "159.5, 159.5, 159.5, 163.6, 171.7"); + } + fall_transition (inslew_load_5x5__39) { + values ("84.7, 84.7, 84.7, 87.4, 92.8", \ + "98.9, 98.9, 98.9, 101.6, 107.0", \ + "125.6, 125.6, 125.6, 128.4, 133.7", \ + "178.6, 178.6, 178.6, 181.4, 186.8", \ + "284.6, 284.6, 284.6, 287.5, 293.5"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__39) { + values ("49.8, 49.8, 49.8, 54.1, 62.1", \ + "46.4, 46.4, 46.4, 50.9, 59.0", \ + "33.4, 33.4, 33.4, 37.8, 46.2", \ + "-1.3, -1.3, -1.3, 3.2, 11.8", \ + "-80.7, -80.7, -80.7, -76.1, -67.1"); + } + rise_transition (inslew_load_5x5__39) { + values ("37.8, 37.8, 37.8, 43.4, 54.5", \ + "44.6, 44.6, 44.6, 50.2, 61.3", \ + "56.9, 56.9, 56.9, 62.6, 73.8", \ + "79.7, 79.7, 79.7, 85.4, 96.7", \ + "123.0, 123.0, 123.0, 128.6, 139.9"); + } + cell_fall (inslew_load_5x5__39) { + values ("105.1, 105.1, 105.1, 109.6, 117.9", \ + "130.2, 130.2, 130.2, 134.8, 143.4", \ + "173.1, 173.1, 173.1, 177.7, 186.6", \ + "252.4, 252.4, 252.4, 256.6, 265.7", \ + "407.7, 407.7, 407.7, 411.8, 419.8"); + } + fall_transition (inslew_load_5x5__39) { + values ("62.8, 62.8, 62.8, 65.5, 70.9", \ + "83.4, 83.4, 83.4, 86.1, 91.5", \ + "121.6, 121.6, 121.6, 124.3, 129.7", \ + "194.8, 194.8, 194.8, 197.8, 203.2", \ + "340.3, 340.3, 340.3, 343.3, 349.2"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__39) { + values ("56.5, 56.5, 56.5, 60.9, 68.9", \ + "56.6, 56.6, 56.6, 61.0, 69.3", \ + "51.0, 51.0, 51.0, 55.4, 63.9", \ + "32.3, 32.3, 32.3, 36.9, 45.6", \ + "-12.7, -12.7, -12.7, -8.0, 1.0"); + } + rise_transition (inslew_load_5x5__39) { + values ("42.3, 42.3, 42.3, 48.0, 59.1", \ + "50.7, 50.7, 50.7, 56.3, 67.5", \ + "66.4, 66.4, 66.4, 72.1, 83.3", \ + "96.3, 96.3, 96.3, 102.0, 113.3", \ + "154.4, 154.4, 154.4, 160.0, 171.3"); + } + cell_fall (inslew_load_5x5__39) { + values ("126.9, 126.9, 126.9, 131.5, 140.1", \ + "145.5, 145.5, 145.5, 150.1, 158.9", \ + "178.1, 178.1, 178.1, 182.6, 191.6", \ + "240.1, 240.1, 240.1, 244.2, 253.2", \ + "363.4, 363.4, 363.4, 367.5, 375.5"); + } + fall_transition (inslew_load_5x5__39) { + values ("79.2, 79.2, 79.2, 81.9, 87.3", \ + "99.0, 99.0, 99.0, 101.7, 107.1", \ + "136.0, 136.0, 136.0, 138.7, 144.1", \ + "209.0, 209.0, 209.0, 211.9, 217.4", \ + "354.7, 354.7, 354.7, 357.6, 363.5"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__39) { + values ("49.0, 49.0, 49.0, 53.4, 61.2", \ + "52.9, 52.9, 52.9, 57.4, 65.5", \ + "54.2, 54.2, 54.2, 58.7, 67.1", \ + "50.1, 50.1, 50.1, 54.7, 63.5", \ + "36.3, 36.3, 36.3, 40.9, 50.0"); + } + rise_transition (inslew_load_5x5__39) { + values ("34.2, 34.2, 34.2, 39.8, 50.9", \ + "44.6, 44.6, 44.6, 50.2, 61.3", \ + "63.0, 63.0, 63.0, 68.7, 79.9", \ + "97.9, 97.9, 97.9, 103.6, 114.9", \ + "166.0, 166.0, 166.0, 171.7, 182.9"); + } + cell_fall (inslew_load_5x5__39) { + values ("65.8, 65.8, 65.8, 70.1, 77.8", \ + "76.8, 76.8, 76.8, 81.2, 89.2", \ + "93.3, 93.3, 93.3, 97.8, 106.4", \ + "120.9, 120.9, 120.9, 125.5, 134.4", \ + "172.8, 172.8, 172.8, 176.8, 185.8"); + } + fall_transition (inslew_load_5x5__39) { + values ("39.3, 39.3, 39.3, 42.0, 47.3", \ + "51.9, 51.9, 51.9, 54.7, 60.0", \ + "76.0, 76.0, 76.0, 78.7, 84.1", \ + "123.0, 123.0, 123.0, 125.7, 131.1", \ + "215.9, 215.9, 215.9, 218.9, 224.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__39) { + values ("721.0, 721.0, 721.0, 775.1, 883.3", \ + "873.3, 873.3, 873.3, 927.4, 1035.5", \ + "1174.1, 1174.1, 1174.1, 1228.2, 1336.3", \ + "1771.5, 1771.5, 1771.5, 1825.6, 1933.7", \ + "2961.3, 2961.3, 2961.3, 3015.4, 3123.6"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("1334.9, 1334.9, 1334.9, 1389.0, 1497.1", \ + "1591.6, 1591.6, 1591.6, 1645.7, 1753.8", \ + "2088.2, 2088.2, 2088.2, 2142.3, 2250.5", \ + "3071.9, 3071.9, 3071.9, 3126.0, 3234.2", \ + "5042.0, 5042.0, 5042.0, 5096.0, 5204.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__39) { + values ("659.0, 659.0, 659.0, 713.0, 821.2", \ + "829.7, 829.7, 829.7, 883.7, 991.9", \ + "1161.5, 1161.5, 1161.5, 1215.6, 1323.7", \ + "1816.7, 1816.7, 1816.7, 1870.8, 1979.0", \ + "3120.6, 3120.6, 3120.6, 3174.7, 3282.8"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("1201.4, 1201.4, 1201.4, 1255.5, 1363.6", \ + "1392.2, 1392.2, 1392.2, 1446.3, 1554.4", \ + "1759.4, 1759.4, 1759.4, 1813.5, 1921.6", \ + "2489.6, 2489.6, 2489.6, 2543.7, 2651.9", \ + "3955.1, 3955.1, 3955.1, 4009.2, 4117.3"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__39) { + values ("551.6, 551.6, 551.6, 605.7, 713.8", \ + "618.5, 618.5, 618.5, 672.6, 780.7", \ + "746.8, 746.8, 746.8, 800.9, 909.1", \ + "993.1, 993.1, 993.1, 1047.2, 1155.4", \ + "1474.0, 1474.0, 1474.0, 1528.1, 1636.2"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("912.0, 912.0, 912.0, 966.1, 1074.3", \ + "1173.2, 1173.2, 1173.2, 1227.3, 1335.4", \ + "1670.1, 1670.1, 1670.1, 1724.2, 1832.3", \ + "2638.1, 2638.1, 2638.1, 2692.1, 2800.3", \ + "4569.1, 4569.1, 4569.1, 4623.2, 4731.3"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__39) { + values ("627.2, 627.2, 627.2, 681.2, 789.4", \ + "719.5, 719.5, 719.5, 773.6, 881.7", \ + "900.5, 900.5, 900.5, 954.6, 1062.7", \ + "1254.9, 1254.9, 1254.9, 1309.0, 1417.2", \ + "1954.6, 1954.6, 1954.6, 2008.7, 2116.9"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("1132.4, 1132.4, 1132.4, 1186.5, 1294.6", \ + "1392.9, 1392.9, 1392.9, 1447.0, 1555.1", \ + "1891.4, 1891.4, 1891.4, 1945.5, 2053.6", \ + "2881.7, 2881.7, 2881.7, 2935.8, 3044.0", \ + "4863.0, 4863.0, 4863.0, 4917.0, 5025.2"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__39) { + values ("492.5, 492.5, 492.5, 546.6, 654.8", \ + "600.8, 600.8, 600.8, 654.9, 763.1", \ + "807.4, 807.4, 807.4, 861.4, 969.6", \ + "1211.2, 1211.2, 1211.2, 1265.3, 1373.5", \ + "2011.9, 2011.9, 2011.9, 2066.0, 2174.1"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("658.6, 658.6, 658.6, 712.7, 820.9", \ + "837.5, 837.5, 837.5, 891.6, 999.8", \ + "1184.3, 1184.3, 1184.3, 1238.4, 1346.6", \ + "1869.3, 1869.3, 1869.3, 1923.3, 2031.5", \ + "3232.1, 3232.1, 3232.1, 3286.2, 3394.4"); + } + } + } + } + + cell (oa3ao322_x2) { + area : 0.0 ; + cell_leakage_power : 7.7 ; + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 4.6 ; + } + leakage_power () { + when : "(i6 & !(i5) & !(i4) & !(i3) & i2 & i1 & i0)" ; + value : 7.6 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & i2 & i1 & i0)" ; + value : 4.3 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & i4 & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & i4 & !(i5) & i6))" ; + value : 9.1 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & !(i4) & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & !(i4) & !(i5) & i6))" ; + value : 9 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & !(i5) & i6) | (!(i0) & (i1 ^ i2) & i3 & !(i5) & i6))" ; + value : 10 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & (i5 ^ i6)) | (!(i4) & i5 & i6))) | (!(i3) & i4 & i5 & i6))) | ((i3 ^ i4) & i5 & i6))) | (!(i1) & ((i2 & (i3 ^ i4) & i5 & i6) | (!(i2) & !(i3) & i4 & !(i5) & i6))))) | (!(i0) & ((i1 & ((i2 & (i3 ^ i4) & i5 & i6) | (!(i2) & !(i3) & i4 & !(i5) & i6))) | (!(i1) & i2 & !(i3) & i4 & !(i5) & i6))))" ; + value : 7.9 ; + } + leakage_power () { + when : "((i0 & ((i1 & i2 & ((i3 & !(i4) & !(i5) & i6) | (!(i3) & (i4 ^ i5) & i6))) | (!(i3) & !(i4) & i5 & i6))) | ((i1 | i2) & !(i3) & !(i4) & i5 & i6))" ; + value : 7.7 ; + } + leakage_power () { + when : "((!((i0 | i1 | i2)) & i3 & (i4 | !(i5)) & i6) | (i3 & i4 & i5 & i6))" ; + value : 11 ; + } + leakage_power () { + when : "((!(i0) & ((!(i1) & ((!(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))) | ((i3 ^ i4) & i5 & i6))) | (!(i2) & (i3 ^ i4) & i5 & i6))) | (!(i1) & !(i2) & (i3 ^ i4) & i5 & i6))" ; + value : 8 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3) & i4 & !(i5) & i6) | (!(i0) & ((i1 & i2 & !(i3) & i4 & !(i5) & i6) | (!(i1) & !(i2) & !(i3) & !(i4) & i5 & i6))))" ; + value : 7.8 ; + } + leakage_power () { + when : "((!((i0 & i1 & i2)) & (!((i3 | i4 | i5)) | !(i6))) | (i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))" ; + value : 4.4 ; + } + pin (i6) { + direction : input ; + capacitance : 5.93 ; + } + pin (i5) { + direction : input ; + capacitance : 5.60 ; + } + pin (i4) { + direction : input ; + capacitance : 5.60 ; + } + pin (i3) { + direction : input ; + capacitance : 5.60 ; + } + pin (i2) { + direction : input ; + capacitance : 5.34 ; + } + pin (i1) { + direction : input ; + capacitance : 5.49 ; + } + pin (i0) { + direction : input ; + capacitance : 5.51 ; + } + pin (q) { + function : "((i6 & ((i2 & i1 & i0) | i5 | i4 | i3)) | (i2 & i1 & i0))" ; + direction : output ; + capacitance : 2.87 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("75.0, 75.0, 75.0, 80.6, 90.9", \ + "77.9, 77.9, 77.9, 83.5, 94.0", \ + "80.3, 80.3, 80.3, 85.9, 96.6", \ + "80.5, 80.5, 80.5, 86.3, 97.3", \ + "76.1, 76.1, 76.1, 82.0, 93.4"); + } + rise_transition (inslew_load_5x5__48) { + values ("65.3, 65.3, 65.3, 72.8, 87.4", \ + "77.3, 77.3, 77.3, 84.7, 99.4", \ + "100.4, 100.4, 100.4, 107.9, 122.7", \ + "146.2, 146.2, 146.2, 153.7, 168.6", \ + "236.8, 236.8, 236.8, 244.3, 259.2"); + } + cell_fall (inslew_load_5x5__48) { + values ("235.2, 235.2, 235.2, 240.5, 250.4", \ + "263.0, 263.0, 263.0, 268.2, 278.4", \ + "309.8, 309.8, 309.8, 315.1, 325.5", \ + "400.7, 400.7, 400.7, 406.1, 416.6", \ + "583.0, 583.0, 583.0, 588.3, 599.0"); + } + fall_transition (inslew_load_5x5__48) { + values ("129.8, 129.8, 129.8, 133.3, 139.7", \ + "157.1, 157.1, 157.1, 160.6, 167.3", \ + "207.3, 207.3, 207.3, 210.9, 217.9", \ + "305.6, 305.6, 305.6, 309.4, 316.4", \ + "500.8, 500.8, 500.8, 504.4, 511.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("72.9, 72.9, 72.9, 78.5, 88.6", \ + "81.6, 81.6, 81.6, 87.2, 97.7", \ + "94.1, 94.1, 94.1, 99.6, 110.4", \ + "113.0, 113.0, 113.0, 118.7, 129.7", \ + "145.7, 145.7, 145.7, 151.6, 163.1"); + } + rise_transition (inslew_load_5x5__48) { + values ("59.6, 59.6, 59.6, 67.0, 81.6", \ + "73.9, 73.9, 73.9, 81.3, 96.0", \ + "101.0, 101.0, 101.0, 108.5, 123.2", \ + "153.5, 153.5, 153.5, 161.0, 175.9", \ + "257.1, 257.1, 257.1, 264.7, 279.6"); + } + cell_fall (inslew_load_5x5__48) { + values ("215.4, 215.4, 215.4, 220.7, 230.7", \ + "230.9, 230.9, 230.9, 236.1, 246.1", \ + "255.1, 255.1, 255.1, 260.4, 270.7", \ + "301.7, 301.7, 301.7, 307.0, 317.5", \ + "396.3, 396.3, 396.3, 401.6, 412.2"); + } + fall_transition (inslew_load_5x5__48) { + values ("118.9, 118.9, 118.9, 122.4, 128.6", \ + "139.6, 139.6, 139.6, 143.2, 149.7", \ + "177.9, 177.9, 177.9, 181.5, 188.3", \ + "252.3, 252.3, 252.3, 256.0, 262.9", \ + "399.6, 399.6, 399.6, 403.3, 410.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("68.7, 68.7, 68.7, 74.2, 84.3", \ + "82.1, 82.1, 82.1, 87.7, 98.1", \ + "102.4, 102.4, 102.4, 108.0, 118.8", \ + "136.6, 136.6, 136.6, 142.4, 153.4", \ + "199.6, 199.6, 199.6, 205.5, 217.0"); + } + rise_transition (inslew_load_5x5__48) { + values ("53.2, 53.2, 53.2, 60.6, 75.2", \ + "69.5, 69.5, 69.5, 76.9, 91.6", \ + "99.4, 99.4, 99.4, 106.9, 121.6", \ + "157.0, 157.0, 157.0, 164.5, 179.4", \ + "270.3, 270.3, 270.3, 277.8, 292.8"); + } + cell_fall (inslew_load_5x5__48) { + values ("195.3, 195.3, 195.3, 200.6, 210.8", \ + "202.9, 202.9, 202.9, 208.1, 218.1", \ + "212.1, 212.1, 212.1, 217.4, 227.5", \ + "229.6, 229.6, 229.6, 234.9, 245.3", \ + "267.0, 267.0, 267.0, 272.3, 282.9"); + } + fall_transition (inslew_load_5x5__48) { + values ("107.9, 107.9, 107.9, 111.5, 117.4", \ + "124.5, 124.5, 124.5, 128.0, 134.3", \ + "154.9, 154.9, 154.9, 158.4, 165.1", \ + "213.6, 213.6, 213.6, 217.2, 224.2", \ + "329.8, 329.8, 329.8, 333.5, 340.5"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("41.5, 41.5, 41.5, 46.9, 56.4", \ + "35.5, 35.5, 35.5, 40.9, 50.7", \ + "15.4, 15.4, 15.4, 20.8, 30.8", \ + "-36.4, -36.4, -36.4, -30.8, -20.6", \ + "-153.7, -153.7, -153.7, -148.2, -137.4"); + } + rise_transition (inslew_load_5x5__48) { + values ("32.8, 32.8, 32.8, 40.2, 54.6", \ + "39.0, 39.0, 39.0, 46.4, 60.9", \ + "49.0, 49.0, 49.0, 56.4, 70.9", \ + "65.9, 65.9, 65.9, 73.3, 88.0", \ + "95.8, 95.8, 95.8, 103.3, 118.0"); + } + cell_fall (inslew_load_5x5__48) { + values ("128.6, 128.6, 128.6, 134.2, 144.2", \ + "168.1, 168.1, 168.1, 173.3, 183.7", \ + "232.3, 232.3, 232.3, 237.6, 247.6", \ + "349.6, 349.6, 349.6, 354.9, 365.3", \ + "577.6, 577.6, 577.6, 582.9, 593.5"); + } + fall_transition (inslew_load_5x5__48) { + values ("67.1, 67.1, 67.1, 69.9, 76.0", \ + "93.9, 93.9, 93.9, 97.3, 103.1", \ + "139.0, 139.0, 139.0, 142.5, 149.0", \ + "224.0, 224.0, 224.0, 227.6, 234.5", \ + "391.4, 391.4, 391.4, 395.0, 402.2"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("46.0, 46.0, 46.0, 51.4, 61.0", \ + "41.7, 41.7, 41.7, 47.1, 56.9", \ + "25.1, 25.1, 25.1, 30.6, 40.6", \ + "-18.8, -18.8, -18.8, -13.2, -2.7", \ + "-119.1, -119.1, -119.1, -113.5, -102.7"); + } + rise_transition (inslew_load_5x5__48) { + values ("35.9, 35.9, 35.9, 43.3, 57.8", \ + "42.6, 42.6, 42.6, 50.0, 64.5", \ + "54.1, 54.1, 54.1, 61.5, 76.1", \ + "74.0, 74.0, 74.0, 81.5, 96.1", \ + "110.4, 110.4, 110.4, 117.9, 132.7"); + } + cell_fall (inslew_load_5x5__48) { + values ("164.3, 164.3, 164.3, 169.5, 179.9", \ + "203.1, 203.1, 203.1, 208.4, 218.4", \ + "263.4, 263.4, 263.4, 268.6, 278.8", \ + "375.5, 375.5, 375.5, 380.9, 391.3", \ + "595.4, 595.4, 595.4, 600.8, 611.4"); + } + fall_transition (inslew_load_5x5__48) { + values ("87.7, 87.7, 87.7, 91.0, 96.8", \ + "116.0, 116.0, 116.0, 119.6, 125.7", \ + "163.3, 163.3, 163.3, 166.9, 173.6", \ + "252.9, 252.9, 252.9, 256.6, 263.5", \ + "429.8, 429.8, 429.8, 433.4, 440.7"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("48.3, 48.3, 48.3, 53.7, 63.4", \ + "46.3, 46.3, 46.3, 51.7, 61.6", \ + "34.7, 34.7, 34.7, 40.3, 50.4", \ + "2.6, 2.6, 2.6, 8.2, 18.8", \ + "-71.1, -71.1, -71.1, -65.4, -54.5"); + } + rise_transition (inslew_load_5x5__48) { + values ("37.5, 37.5, 37.5, 44.9, 59.4", \ + "45.4, 45.4, 45.4, 52.8, 67.3", \ + "59.2, 59.2, 59.2, 66.7, 81.3", \ + "84.4, 84.4, 84.4, 91.8, 106.5", \ + "131.6, 131.6, 131.6, 139.1, 154.0"); + } + cell_fall (inslew_load_5x5__48) { + values ("199.9, 199.9, 199.9, 205.2, 215.4", \ + "237.1, 237.1, 237.1, 242.3, 252.3", \ + "294.0, 294.0, 294.0, 299.3, 309.7", \ + "401.2, 401.2, 401.2, 406.5, 417.0", \ + "613.8, 613.8, 613.8, 619.1, 629.8"); + } + fall_transition (inslew_load_5x5__48) { + values ("108.3, 108.3, 108.3, 111.9, 117.8", \ + "138.0, 138.0, 138.0, 141.6, 148.1", \ + "188.4, 188.4, 188.4, 192.0, 199.0", \ + "284.9, 284.9, 284.9, 288.7, 295.7", \ + "475.9, 475.9, 475.9, 479.6, 487.0"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("32.4, 32.4, 32.4, 37.7, 47.0", \ + "29.5, 29.5, 29.5, 34.9, 44.5", \ + "17.7, 17.7, 17.7, 23.1, 33.1", \ + "-12.8, -12.8, -12.8, -7.2, 3.3", \ + "-79.0, -79.0, -79.0, -73.3, -62.5"); + } + rise_transition (inslew_load_5x5__48) { + values ("25.7, 25.7, 25.7, 33.2, 47.6", \ + "34.4, 34.4, 34.4, 41.8, 56.3", \ + "49.1, 49.1, 49.1, 56.5, 71.1", \ + "75.6, 75.6, 75.6, 83.0, 97.7", \ + "126.1, 126.1, 126.1, 133.6, 148.4"); + } + cell_fall (inslew_load_5x5__48) { + values ("61.4, 61.4, 61.4, 66.4, 75.1", \ + "79.2, 79.2, 79.2, 84.4, 94.0", \ + "108.4, 108.4, 108.4, 113.8, 124.0", \ + "163.2, 163.2, 163.2, 168.5, 178.4", \ + "269.3, 269.3, 269.3, 274.7, 285.1"); + } + fall_transition (inslew_load_5x5__48) { + values ("32.2, 32.2, 32.2, 35.4, 41.3", \ + "47.6, 47.6, 47.6, 50.6, 56.7", \ + "75.8, 75.8, 75.8, 78.8, 84.8", \ + "129.4, 129.4, 129.4, 132.9, 139.3", \ + "235.6, 235.6, 235.6, 239.3, 246.2"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__48) { + values ("540.6, 540.6, 540.6, 576.4, 648.1", \ + "628.5, 628.5, 628.5, 664.4, 736.0", \ + "802.9, 802.9, 802.9, 838.8, 910.4", \ + "1151.5, 1151.5, 1151.5, 1187.3, 1259.0", \ + "1846.7, 1846.7, 1846.7, 1882.5, 1954.2"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("1050.9, 1050.9, 1050.9, 1086.7, 1158.4", \ + "1258.2, 1258.2, 1258.2, 1294.0, 1365.7", \ + "1652.9, 1652.9, 1652.9, 1688.7, 1760.4", \ + "2432.4, 2432.4, 2432.4, 2468.2, 2539.9", \ + "3983.8, 3983.8, 3983.8, 4019.6, 4091.3"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__48) { + values ("490.0, 490.0, 490.0, 525.8, 597.5", \ + "590.1, 590.1, 590.1, 625.9, 697.6", \ + "786.5, 786.5, 786.5, 822.4, 894.0", \ + "1175.5, 1175.5, 1175.5, 1211.3, 1283.0", \ + "1950.7, 1950.7, 1950.7, 1986.5, 2058.2"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("960.0, 960.0, 960.0, 995.8, 1067.5", \ + "1117.1, 1117.1, 1117.1, 1152.9, 1224.6", \ + "1416.4, 1416.4, 1416.4, 1452.3, 1523.9", \ + "2005.5, 2005.5, 2005.5, 2041.3, 2112.9", \ + "3176.2, 3176.2, 3176.2, 3212.0, 3283.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__48) { + values ("435.6, 435.6, 435.6, 471.4, 543.0", \ + "543.9, 543.9, 543.9, 579.8, 651.4", \ + "754.3, 754.3, 754.3, 790.1, 861.8", \ + "1169.5, 1169.5, 1169.5, 1205.4, 1277.0", \ + "1995.6, 1995.6, 1995.6, 2031.4, 2103.1"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("870.2, 870.2, 870.2, 906.0, 977.7", \ + "994.9, 994.9, 994.9, 1030.7, 1102.4", \ + "1232.0, 1232.0, 1232.0, 1267.8, 1339.5", \ + "1696.3, 1696.3, 1696.3, 1732.2, 1803.8", \ + "2619.1, 2619.1, 2619.1, 2654.9, 2726.6"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__48) { + values ("341.8, 341.8, 341.8, 377.7, 449.3", \ + "370.5, 370.5, 370.5, 406.4, 478.0", \ + "422.3, 422.3, 422.3, 458.1, 529.8", \ + "517.8, 517.8, 517.8, 553.6, 625.3", \ + "697.9, 697.9, 697.9, 733.8, 805.4"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("582.2, 582.2, 582.2, 618.0, 689.7", \ + "769.9, 769.9, 769.9, 805.7, 877.4", \ + "1105.9, 1105.9, 1105.9, 1141.7, 1213.4", \ + "1754.1, 1754.1, 1754.1, 1789.9, 1861.5", \ + "3038.0, 3038.0, 3038.0, 3073.8, 3145.5"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__48) { + values ("377.6, 377.6, 377.6, 413.5, 485.1", \ + "413.3, 413.3, 413.3, 449.2, 520.8", \ + "480.0, 480.0, 480.0, 515.8, 587.5", \ + "605.2, 605.2, 605.2, 641.0, 712.7", \ + "846.4, 846.4, 846.4, 882.3, 953.9"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("739.4, 739.4, 739.4, 775.2, 846.8", \ + "941.0, 941.0, 941.0, 976.8, 1048.5", \ + "1300.2, 1300.2, 1300.2, 1336.1, 1407.7", \ + "1996.1, 1996.1, 1996.1, 2031.9, 2103.6", \ + "3376.8, 3376.8, 3376.8, 3412.6, 3484.3"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__48) { + values ("398.4, 398.4, 398.4, 434.3, 505.9", \ + "447.3, 447.3, 447.3, 483.1, 554.8", \ + "540.5, 540.5, 540.5, 576.4, 648.0", \ + "720.9, 720.9, 720.9, 756.7, 828.4", \ + "1074.4, 1074.4, 1074.4, 1110.2, 1181.9"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("896.0, 896.0, 896.0, 931.8, 1003.5", \ + "1111.7, 1111.7, 1111.7, 1147.5, 1219.2", \ + "1500.9, 1500.9, 1500.9, 1536.7, 1608.4", \ + "2260.3, 2260.3, 2260.3, 2296.1, 2367.8", \ + "3768.8, 3768.8, 3768.8, 3804.6, 3876.3"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__48) { + values ("265.1, 265.1, 265.1, 300.9, 372.6", \ + "315.9, 315.9, 315.9, 351.7, 423.4", \ + "413.1, 413.1, 413.1, 448.9, 520.6", \ + "603.0, 603.0, 603.0, 638.9, 710.5", \ + "979.2, 979.2, 979.2, 1015.0, 1086.7"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("380.3, 380.3, 380.3, 416.1, 487.8", \ + "522.1, 522.1, 522.1, 557.9, 629.5", \ + "793.8, 793.8, 793.8, 829.7, 901.3", \ + "1329.9, 1329.9, 1329.9, 1365.7, 1437.4", \ + "2397.5, 2397.5, 2397.5, 2433.3, 2505.0"); + } + } + } + } + + cell (oa3ao322_x4) { + area : 0.0 ; + cell_leakage_power : 7.5 ; + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 4.6 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 4.4 ; + } + leakage_power () { + when : "(i6 & !(i5) & !(i4) & !(i3) & i2 & i1 & i0)" ; + value : 7.6 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & i2 & i1 & i0)" ; + value : 4.3 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & i4 & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & i4 & !(i5) & i6))" ; + value : 9.1 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & !(i4) & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & !(i4) & !(i5) & i6))" ; + value : 9 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & !(i5) & i6) | (!(i0) & (i1 ^ i2) & i3 & !(i5) & i6))" ; + value : 10 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & (i5 ^ i6)) | (!(i4) & i5 & i6))) | (!(i3) & i4 & i5 & i6))) | ((i3 ^ i4) & i5 & i6))) | (!(i1) & ((i2 & (i3 ^ i4) & i5 & i6) | (!(i2) & !(i3) & i4 & !(i5) & i6))))) | (!(i0) & ((i1 & ((i2 & (i3 ^ i4) & i5 & i6) | (!(i2) & !(i3) & i4 & !(i5) & i6))) | (!(i1) & i2 & !(i3) & i4 & !(i5) & i6))))" ; + value : 7.9 ; + } + leakage_power () { + when : "((i0 & ((i1 & i2 & ((i3 & !(i4) & !(i5) & i6) | (!(i3) & (i4 ^ i5) & i6))) | (!(i3) & !(i4) & i5 & i6))) | ((i1 | i2) & !(i3) & !(i4) & i5 & i6))" ; + value : 7.7 ; + } + leakage_power () { + when : "((!((i0 | i1 | i2)) & i3 & (i4 | !(i5)) & i6) | (i3 & i4 & i5 & i6))" ; + value : 11 ; + } + leakage_power () { + when : "((!(i0) & ((!(i1) & ((!(i2) & ((i3 & !(i4) & i5 & i6) | (!(i3) & i4 & i6))) | ((i3 ^ i4) & i5 & i6))) | (!(i2) & (i3 ^ i4) & i5 & i6))) | (!(i1) & !(i2) & (i3 ^ i4) & i5 & i6))" ; + value : 8 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & !(i3) & i4 & !(i5) & i6) | (!(i0) & ((i1 & i2 & !(i3) & i4 & !(i5) & i6) | (!(i1) & !(i2) & !(i3) & !(i4) & i5 & i6))))" ; + value : 7.8 ; + } + leakage_power () { + when : "(!((i0 & i1 & i2)) & (!((i3 | i4 | i5)) | !(i6)))" ; + value : 5.4 ; + } + pin (i6) { + direction : input ; + capacitance : 5.16 ; + } + pin (i5) { + direction : input ; + capacitance : 4.94 ; + } + pin (i4) { + direction : input ; + capacitance : 4.93 ; + } + pin (i3) { + direction : input ; + capacitance : 5.38 ; + } + pin (i2) { + direction : input ; + capacitance : 5.47 ; + } + pin (i1) { + direction : input ; + capacitance : 5.67 ; + } + pin (i0) { + direction : input ; + capacitance : 5.68 ; + } + pin (q) { + function : "((i6 & ((i0 & i1 & i2) | i5 | i4 | i3)) | (i0 & i1 & i2))" ; + direction : output ; + capacitance : 4.30 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("82.7, 82.7, 82.7, 87.2, 95.5", \ + "84.9, 84.9, 84.9, 89.4, 97.9", \ + "86.2, 86.2, 86.2, 90.8, 99.5", \ + "83.5, 83.5, 83.5, 88.2, 97.1", \ + "72.6, 72.6, 72.6, 77.2, 86.2"); + } + rise_transition (inslew_load_5x5__49) { + values ("68.7, 68.7, 68.7, 74.4, 85.6", \ + "79.0, 79.0, 79.0, 84.7, 95.9", \ + "99.6, 99.6, 99.6, 105.2, 116.5", \ + "140.6, 140.6, 140.6, 146.1, 157.3", \ + "221.2, 221.2, 221.2, 227.1, 238.3"); + } + cell_fall (inslew_load_5x5__49) { + values ("304.0, 304.0, 304.0, 308.2, 317.2", \ + "337.4, 337.4, 337.4, 341.3, 350.3", \ + "394.9, 394.9, 394.9, 398.9, 407.2", \ + "506.7, 506.7, 506.7, 510.8, 518.7", \ + "729.7, 729.7, 729.7, 733.8, 742.0"); + } + fall_transition (inslew_load_5x5__49) { + values ("178.7, 178.7, 178.7, 181.5, 186.9", \ + "211.0, 211.0, 211.0, 214.0, 219.4", \ + "270.8, 270.8, 270.8, 273.7, 279.5", \ + "387.7, 387.7, 387.7, 390.6, 396.5", \ + "619.8, 619.8, 619.8, 622.7, 628.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("81.4, 81.4, 81.4, 85.9, 94.2", \ + "89.9, 89.9, 89.9, 94.4, 102.8", \ + "101.2, 101.2, 101.2, 105.7, 114.5", \ + "116.9, 116.9, 116.9, 121.5, 130.5", \ + "142.1, 142.1, 142.1, 146.7, 155.7"); + } + rise_transition (inslew_load_5x5__49) { + values ("63.7, 63.7, 63.7, 69.4, 80.5", \ + "76.2, 76.2, 76.2, 81.8, 93.0", \ + "100.3, 100.3, 100.3, 106.0, 117.2", \ + "147.4, 147.4, 147.4, 152.9, 164.1", \ + "239.7, 239.7, 239.7, 245.6, 256.9"); + } + cell_fall (inslew_load_5x5__49) { + values ("281.7, 281.7, 281.7, 286.2, 295.1", \ + "301.8, 301.8, 301.8, 305.9, 314.9", \ + "334.2, 334.2, 334.2, 338.1, 346.8", \ + "396.6, 396.6, 396.6, 400.7, 408.6", \ + "522.0, 522.0, 522.0, 526.1, 534.2"); + } + fall_transition (inslew_load_5x5__49) { + values ("165.8, 165.8, 165.8, 168.5, 173.9", \ + "190.3, 190.3, 190.3, 193.1, 198.5", \ + "235.7, 235.7, 235.7, 238.6, 244.2", \ + "324.3, 324.3, 324.3, 327.1, 333.1", \ + "499.4, 499.4, 499.4, 502.3, 508.2"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("78.5, 78.5, 78.5, 82.9, 91.2", \ + "91.8, 91.8, 91.8, 96.2, 104.6", \ + "111.1, 111.1, 111.1, 115.6, 124.3", \ + "141.6, 141.6, 141.6, 146.3, 155.3", \ + "196.4, 196.4, 196.4, 201.0, 210.0"); + } + rise_transition (inslew_load_5x5__49) { + values ("58.4, 58.4, 58.4, 64.0, 75.1", \ + "72.5, 72.5, 72.5, 78.2, 89.4", \ + "99.3, 99.3, 99.3, 104.9, 116.1", \ + "150.9, 150.9, 150.9, 156.5, 167.6", \ + "251.8, 251.8, 251.8, 257.6, 269.0"); + } + cell_fall (inslew_load_5x5__49) { + values ("259.6, 259.6, 259.6, 264.1, 273.0", \ + "270.6, 270.6, 270.6, 275.0, 283.9", \ + "286.6, 286.6, 286.6, 290.5, 299.6", \ + "316.6, 316.6, 316.6, 320.7, 328.8", \ + "378.3, 378.3, 378.3, 382.4, 390.3"); + } + fall_transition (inslew_load_5x5__49) { + values ("152.7, 152.7, 152.7, 155.4, 160.7", \ + "172.2, 172.2, 172.2, 175.0, 180.3", \ + "208.3, 208.3, 208.3, 211.3, 216.7", \ + "278.3, 278.3, 278.3, 281.2, 287.1", \ + "416.5, 416.5, 416.5, 419.4, 425.2"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("56.2, 56.2, 56.2, 60.5, 68.5", \ + "52.1, 52.1, 52.1, 56.5, 64.6", \ + "36.2, 36.2, 36.2, 40.6, 48.9", \ + "-7.4, -7.4, -7.4, -2.9, 5.5", \ + "-110.2, -110.2, -110.2, -105.6, -96.8"); + } + rise_transition (inslew_load_5x5__49) { + values ("41.7, 41.7, 41.7, 47.3, 58.4", \ + "47.3, 47.3, 47.3, 52.8, 63.9", \ + "57.4, 57.4, 57.4, 63.1, 74.2", \ + "75.3, 75.3, 75.3, 81.0, 92.2", \ + "107.8, 107.8, 107.8, 113.4, 124.7"); + } + cell_fall (inslew_load_5x5__49) { + values ("175.7, 175.7, 175.7, 180.3, 189.0", \ + "212.8, 212.8, 212.8, 217.4, 226.3", \ + "276.2, 276.2, 276.2, 280.5, 289.5", \ + "393.6, 393.6, 393.6, 397.6, 405.9", \ + "621.8, 621.8, 621.8, 625.9, 633.9"); + } + fall_transition (inslew_load_5x5__49) { + values ("99.8, 99.8, 99.8, 102.5, 107.9", \ + "127.0, 127.0, 127.0, 129.7, 135.1", \ + "174.6, 174.6, 174.6, 177.4, 182.8", \ + "265.5, 265.5, 265.5, 268.4, 274.2", \ + "445.5, 445.5, 445.5, 448.4, 454.2"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("78.0, 78.0, 78.0, 82.4, 90.7", \ + "81.2, 81.2, 81.2, 85.6, 93.9", \ + "78.6, 78.6, 78.6, 83.1, 91.5", \ + "60.7, 60.7, 60.7, 65.3, 74.1", \ + "10.3, 10.3, 10.3, 15.0, 23.9"); + } + rise_transition (inslew_load_5x5__49) { + values ("54.2, 54.2, 54.2, 59.8, 70.9", \ + "61.9, 61.9, 61.9, 67.6, 78.7", \ + "76.4, 76.4, 76.4, 82.0, 93.2", \ + "103.2, 103.2, 103.2, 108.8, 120.1", \ + "153.7, 153.7, 153.7, 159.3, 170.5"); + } + cell_fall (inslew_load_5x5__49) { + values ("210.7, 210.7, 210.7, 215.3, 224.2", \ + "233.5, 233.5, 233.5, 238.0, 246.9", \ + "272.3, 272.3, 272.3, 276.5, 285.5", \ + "345.8, 345.8, 345.8, 349.8, 358.2", \ + "488.0, 488.0, 488.0, 492.1, 500.1"); + } + fall_transition (inslew_load_5x5__49) { + values ("122.9, 122.9, 122.9, 125.6, 131.0", \ + "143.8, 143.8, 143.8, 146.5, 151.8", \ + "181.6, 181.6, 181.6, 184.4, 189.8", \ + "255.4, 255.4, 255.4, 258.3, 264.0", \ + "402.5, 402.5, 402.5, 405.4, 411.3"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("81.8, 81.8, 81.8, 86.1, 94.5", \ + "88.0, 88.0, 88.0, 92.4, 100.8", \ + "92.5, 92.5, 92.5, 97.0, 105.6", \ + "90.8, 90.8, 90.8, 95.4, 104.3", \ + "76.2, 76.2, 76.2, 80.7, 89.8"); + } + rise_transition (inslew_load_5x5__49) { + values ("56.8, 56.8, 56.8, 62.4, 73.5", \ + "66.2, 66.2, 66.2, 71.9, 83.0", \ + "84.2, 84.2, 84.2, 89.8, 101.0", \ + "118.4, 118.4, 118.4, 124.0, 135.2", \ + "184.3, 184.3, 184.3, 190.1, 201.2"); + } + cell_fall (inslew_load_5x5__49) { + values ("243.7, 243.7, 243.7, 248.2, 257.1", \ + "262.4, 262.4, 262.4, 266.8, 275.8", \ + "292.4, 292.4, 292.4, 296.4, 305.4", \ + "349.1, 349.1, 349.1, 353.1, 361.3", \ + "462.2, 462.2, 462.2, 466.3, 474.2"); + } + fall_transition (inslew_load_5x5__49) { + values ("143.6, 143.6, 143.6, 146.3, 151.6", \ + "164.5, 164.5, 164.5, 167.2, 172.5", \ + "202.3, 202.3, 202.3, 205.3, 210.7", \ + "276.0, 276.0, 276.0, 278.9, 284.8", \ + "422.8, 422.8, 422.8, 425.7, 431.6"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__49) { + values ("63.1, 63.1, 63.1, 67.5, 75.5", \ + "68.3, 68.3, 68.3, 72.6, 80.9", \ + "71.3, 71.3, 71.3, 75.8, 84.1", \ + "68.6, 68.6, 68.6, 73.1, 81.9", \ + "54.9, 54.9, 54.9, 59.5, 68.5"); + } + rise_transition (inslew_load_5x5__49) { + values ("43.8, 43.8, 43.8, 49.4, 60.4", \ + "53.5, 53.5, 53.5, 59.2, 70.3", \ + "71.7, 71.7, 71.7, 77.3, 88.5", \ + "105.9, 105.9, 105.9, 111.4, 122.7", \ + "172.1, 172.1, 172.1, 177.8, 188.9"); + } + cell_fall (inslew_load_5x5__49) { + values ("85.5, 85.5, 85.5, 89.9, 97.8", \ + "99.8, 99.8, 99.8, 104.3, 112.5", \ + "122.3, 122.3, 122.3, 126.9, 135.6", \ + "161.4, 161.4, 161.4, 166.0, 174.9", \ + "235.1, 235.1, 235.1, 239.1, 247.7"); + } + fall_transition (inslew_load_5x5__49) { + values ("49.5, 49.5, 49.5, 52.2, 57.6", \ + "63.3, 63.3, 63.3, 66.0, 71.3", \ + "89.1, 89.1, 89.1, 91.8, 97.1", \ + "140.0, 140.0, 140.0, 142.7, 148.0", \ + "240.3, 240.3, 240.3, 243.2, 248.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__49) { + values ("838.3, 838.3, 838.3, 892.0, 999.3", \ + "953.1, 953.1, 953.1, 1006.8, 1114.1", \ + "1183.1, 1183.1, 1183.1, 1236.8, 1344.1", \ + "1642.3, 1642.3, 1642.3, 1696.0, 1803.3", \ + "2557.3, 2557.3, 2557.3, 2611.0, 2718.4"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("2073.8, 2073.8, 2073.8, 2127.4, 2234.8", \ + "2433.8, 2433.8, 2433.8, 2487.5, 2594.8", \ + "3111.5, 3111.5, 3111.5, 3165.2, 3272.6", \ + "4446.5, 4446.5, 4446.5, 4500.2, 4607.6", \ + "7099.9, 7099.9, 7099.9, 7153.6, 7261.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__49) { + values ("774.2, 774.2, 774.2, 827.9, 935.3", \ + "907.5, 907.5, 907.5, 961.2, 1068.5", \ + "1169.3, 1169.3, 1169.3, 1223.0, 1330.4", \ + "1685.9, 1685.9, 1685.9, 1739.6, 1847.0", \ + "2713.2, 2713.2, 2713.2, 2766.9, 2874.3"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("1921.3, 1921.3, 1921.3, 1975.0, 2082.4", \ + "2194.0, 2194.0, 2194.0, 2247.7, 2355.1", \ + "2708.4, 2708.4, 2708.4, 2762.1, 2869.4", \ + "3718.3, 3718.3, 3718.3, 3772.0, 3879.3", \ + "5720.7, 5720.7, 5720.7, 5774.4, 5881.8"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__49) { + values ("706.4, 706.4, 706.4, 760.1, 867.5", \ + "852.2, 852.2, 852.2, 905.9, 1013.2", \ + "1135.4, 1135.4, 1135.4, 1189.1, 1296.5", \ + "1690.9, 1690.9, 1690.9, 1744.6, 1852.0", \ + "2792.4, 2792.4, 2792.4, 2846.1, 2953.5"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("1769.2, 1769.2, 1769.2, 1822.9, 1930.3", \ + "1985.8, 1985.8, 1985.8, 2039.5, 2146.9", \ + "2394.1, 2394.1, 2394.1, 2447.8, 2555.1", \ + "3191.2, 3191.2, 3191.2, 3244.9, 3352.2", \ + "4770.0, 4770.0, 4770.0, 4823.7, 4931.1"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__49) { + values ("549.7, 549.7, 549.7, 603.4, 710.8", \ + "595.5, 595.5, 595.5, 649.2, 756.5", \ + "682.4, 682.4, 682.4, 736.1, 843.4", \ + "842.4, 842.4, 842.4, 896.1, 1003.5", \ + "1141.6, 1141.6, 1141.6, 1195.3, 1302.7"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("1190.5, 1190.5, 1190.5, 1244.1, 1351.5", \ + "1481.0, 1481.0, 1481.0, 1534.7, 1642.1", \ + "2004.6, 2004.6, 2004.6, 2058.3, 2165.7", \ + "3017.8, 3017.8, 3017.8, 3071.5, 3178.9", \ + "5028.9, 5028.9, 5028.9, 5082.6, 5190.0"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__49) { + values ("661.0, 661.0, 661.0, 714.7, 822.0", \ + "730.1, 730.1, 730.1, 783.8, 891.2", \ + "862.9, 862.9, 862.9, 916.6, 1023.9", \ + "1115.5, 1115.5, 1115.5, 1169.2, 1276.6", \ + "1602.0, 1602.0, 1602.0, 1655.6, 1763.0"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("1435.2, 1435.2, 1435.2, 1488.9, 1596.2", \ + "1662.3, 1662.3, 1662.3, 1716.0, 1823.3", \ + "2084.1, 2084.1, 2084.1, 2137.7, 2245.1", \ + "2912.6, 2912.6, 2912.6, 2966.2, 3073.6", \ + "4567.8, 4567.8, 4567.8, 4621.5, 4728.9"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__49) { + values ("697.3, 697.3, 697.3, 751.0, 858.3", \ + "788.3, 788.3, 788.3, 842.0, 949.3", \ + "965.7, 965.7, 965.7, 1019.4, 1126.8", \ + "1310.1, 1310.1, 1310.1, 1363.8, 1471.2", \ + "1985.1, 1985.1, 1985.1, 2038.8, 2146.2"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("1667.4, 1667.4, 1667.4, 1721.1, 1828.5", \ + "1897.1, 1897.1, 1897.1, 1950.8, 2058.1", \ + "2324.2, 2324.2, 2324.2, 2377.9, 2485.2", \ + "3159.9, 3159.9, 3159.9, 3213.6, 3320.9", \ + "4827.5, 4827.5, 4827.5, 4881.2, 4988.5"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__49) { + values ("532.9, 532.9, 532.9, 586.6, 694.0", \ + "625.3, 625.3, 625.3, 678.9, 786.3", \ + "802.9, 802.9, 802.9, 856.6, 964.0", \ + "1146.9, 1146.9, 1146.9, 1200.6, 1308.0", \ + "1824.5, 1824.5, 1824.5, 1878.2, 1985.6"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("722.6, 722.6, 722.6, 776.3, 883.7", \ + "894.7, 894.7, 894.7, 948.3, 1055.7", \ + "1223.4, 1223.4, 1223.4, 1277.1, 1384.5", \ + "1876.4, 1876.4, 1876.4, 1930.1, 2037.5", \ + "3173.6, 3173.6, 3173.6, 3227.3, 3334.6"); + } + } + } + } + + cell (on12_x1) { + area : 0.0 ; + cell_leakage_power : 1.5 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 2.9 ; + } + leakage_power () { + when : "i1" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 0.00022 ; + } + pin (i1) { + direction : input ; + capacitance : 5.91 ; + } + pin (i0) { + direction : input ; + capacitance : 5.92 ; + } + pin (q) { + function : "(!(i0) | i1)" ; + direction : output ; + capacitance : 3.04 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__50) { + values ("29.0, 29.0, 29.0, 36.1, 49.1", \ + "25.3, 25.3, 25.3, 32.7, 46.4", \ + "16.7, 16.7, 16.7, 24.5, 39.0", \ + "-6.2, -6.2, -6.2, 2.1, 17.6", \ + "-56.1, -56.1, -56.1, -47.5, -31.1"); + } + rise_transition (inslew_load_5x5__50) { + values ("29.6, 29.6, 29.6, 41.3, 64.6", \ + "38.9, 38.9, 38.9, 50.6, 73.8", \ + "59.1, 59.1, 59.1, 70.8, 94.0", \ + "94.0, 94.0, 94.0, 105.8, 129.2", \ + "159.7, 159.7, 159.7, 171.6, 195.3"); + } + cell_fall (inslew_load_5x5__50) { + values ("45.6, 45.6, 45.6, 51.1, 61.2", \ + "56.9, 56.9, 56.9, 63.1, 74.4", \ + "75.6, 75.6, 75.6, 82.3, 95.1", \ + "110.0, 110.0, 110.0, 117.6, 131.4", \ + "176.7, 176.7, 176.7, 184.5, 199.7"); + } + fall_transition (inslew_load_5x5__50) { + values ("27.1, 27.1, 27.1, 32.6, 43.3", \ + "36.7, 36.7, 36.7, 42.4, 53.4", \ + "54.7, 54.7, 54.7, 60.7, 71.9", \ + "89.4, 89.4, 89.4, 95.6, 107.4", \ + "158.1, 158.1, 158.1, 164.4, 176.7"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__50) { + values ("20.9, 20.9, 20.9, 29.5, 44.9", \ + "31.0, 31.0, 31.0, 40.2, 57.1", \ + "48.8, 48.8, 48.8, 58.4, 76.6", \ + "82.8, 82.8, 82.8, 92.7, 111.8", \ + "150.1, 150.1, 150.1, 160.1, 179.8"); + } + rise_transition (inslew_load_5x5__50) { + values ("41.5, 41.5, 41.5, 53.6, 77.1", \ + "76.4, 76.4, 76.4, 88.6, 112.5", \ + "142.6, 142.6, 142.6, 154.9, 179.3", \ + "273.0, 273.0, 273.0, 285.4, 310.1", \ + "532.8, 532.8, 532.8, 545.3, 570.1"); + } + cell_fall (inslew_load_5x5__50) { + values ("5.3, 5.3, 5.3, 12.4, 24.0", \ + "0.3, 0.3, 0.3, 8.4, 22.1", \ + "-10.6, -10.6, -10.6, -1.7, 14.0", \ + "-33.1, -33.1, -33.1, -23.8, -6.4", \ + "-78.5, -78.5, -78.5, -68.9, -50.4"); + } + fall_transition (inslew_load_5x5__50) { + values ("17.6, 17.6, 17.6, 23.6, 34.8", \ + "30.1, 30.1, 30.1, 36.4, 48.2", \ + "54.3, 54.3, 54.3, 60.9, 73.4", \ + "102.3, 102.3, 102.3, 109.1, 122.1", \ + "198.1, 198.1, 198.1, 204.9, 218.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__50) { + values ("236.2, 236.2, 236.2, 274.2, 350.2", \ + "294.1, 294.1, 294.1, 332.0, 408.0", \ + "407.2, 407.2, 407.2, 445.2, 521.1", \ + "631.7, 631.7, 631.7, 669.7, 745.7", \ + "1079.4, 1079.4, 1079.4, 1117.4, 1193.4"); + } + fall_power (energy_inslew_load_5x5__50) { + values ("318.8, 318.8, 318.8, 356.8, 432.8", \ + "446.3, 446.3, 446.3, 484.2, 560.2", \ + "697.9, 697.9, 697.9, 735.9, 811.8", \ + "1199.2, 1199.2, 1199.2, 1237.2, 1313.1", \ + "2200.8, 2200.8, 2200.8, 2238.7, 2314.7"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__50) { + values ("116.0, 116.0, 116.0, 154.0, 229.9", \ + "192.0, 192.0, 192.0, 229.9, 305.9", \ + "343.9, 343.9, 343.9, 381.9, 457.8", \ + "647.7, 647.7, 647.7, 685.7, 761.7", \ + "1255.4, 1255.4, 1255.4, 1293.4, 1369.3"); + } + fall_power (energy_inslew_load_5x5__50) { + values ("77.4, 77.4, 77.4, 115.3, 191.3", \ + "118.8, 118.8, 118.8, 156.8, 232.7", \ + "201.7, 201.7, 201.7, 239.7, 315.6", \ + "367.5, 367.5, 367.5, 405.4, 481.4", \ + "699.0, 699.0, 699.0, 737.0, 812.9"); + } + } + } + } + + cell (on12_x4) { + area : 0.0 ; + cell_leakage_power : 3.1 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 1.4 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 6.1 ; + } + leakage_power () { + when : "!(i0)" ; + value : 1.9 ; + } + pin (i1) { + direction : input ; + capacitance : 6.27 ; + } + pin (i0) { + direction : input ; + capacitance : 5.04 ; + } + pin (q) { + function : "(i1 | !(i0))" ; + direction : output ; + capacitance : 4.20 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("34.7, 34.7, 34.7, 38.9, 46.3", \ + "34.3, 34.3, 34.3, 38.5, 46.2", \ + "27.3, 27.3, 27.3, 31.6, 39.8", \ + "7.0, 7.0, 7.0, 11.5, 20.0", \ + "-39.0, -39.0, -39.0, -34.4, -25.5"); + } + rise_transition (inslew_load_5x5__21) { + values ("23.6, 23.6, 23.6, 29.1, 39.8", \ + "32.5, 32.5, 32.5, 38.0, 48.8", \ + "47.9, 47.9, 47.9, 53.5, 64.3", \ + "76.3, 76.3, 76.3, 81.8, 92.8", \ + "131.2, 131.2, 131.2, 136.9, 147.8"); + } + cell_fall (inslew_load_5x5__21) { + values ("108.6, 108.6, 108.6, 113.1, 121.3", \ + "127.5, 127.5, 127.5, 132.1, 140.6", \ + "161.5, 161.5, 161.5, 166.1, 175.0", \ + "226.7, 226.7, 226.7, 231.3, 240.4", \ + "356.7, 356.7, 356.7, 361.3, 370.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("67.0, 67.0, 67.0, 69.8, 75.3", \ + "87.3, 87.3, 87.3, 90.1, 95.6", \ + "125.7, 125.7, 125.7, 128.5, 134.1", \ + "201.9, 201.9, 201.9, 204.6, 210.1", \ + "354.2, 354.2, 354.2, 356.9, 362.4"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("72.7, 72.7, 72.7, 76.9, 84.4", \ + "88.5, 88.5, 88.5, 92.8, 100.6", \ + "111.9, 111.9, 111.9, 116.3, 124.4", \ + "153.2, 153.2, 153.2, 157.7, 166.1", \ + "225.9, 225.9, 225.9, 230.5, 239.4"); + } + rise_transition (inslew_load_5x5__21) { + values ("26.7, 26.7, 26.7, 32.2, 42.9", \ + "34.5, 34.5, 34.5, 40.0, 50.8", \ + "47.9, 47.9, 47.9, 53.4, 64.2", \ + "71.7, 71.7, 71.7, 77.2, 88.2", \ + "119.2, 119.2, 119.2, 124.7, 135.6"); + } + cell_fall (inslew_load_5x5__21) { + values ("86.3, 86.3, 86.3, 90.5, 98.5", \ + "77.2, 77.2, 77.2, 81.4, 89.4", \ + "68.4, 68.4, 68.4, 72.7, 80.6", \ + "44.1, 44.1, 44.1, 48.6, 56.8", \ + "-13.9, -13.9, -13.9, -9.3, -0.7"); + } + fall_transition (inslew_load_5x5__21) { + values ("41.8, 41.8, 41.8, 44.7, 50.1", \ + "42.2, 42.2, 42.2, 45.0, 50.4", \ + "50.9, 50.9, 50.9, 53.6, 59.2", \ + "66.6, 66.6, 66.6, 69.3, 74.8", \ + "94.4, 94.4, 94.4, 97.2, 102.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("432.1, 432.1, 432.1, 484.6, 589.7", \ + "528.4, 528.4, 528.4, 580.9, 686.0", \ + "712.8, 712.8, 712.8, 765.3, 870.3", \ + "1072.0, 1072.0, 1072.0, 1124.5, 1229.5", \ + "1783.7, 1783.7, 1783.7, 1836.3, 1941.3"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("950.3, 950.3, 950.3, 1002.9, 1107.9", \ + "1215.8, 1215.8, 1215.8, 1268.3, 1373.4", \ + "1728.5, 1728.5, 1728.5, 1781.0, 1886.1", \ + "2748.4, 2748.4, 2748.4, 2800.9, 2905.9", \ + "4787.8, 4787.8, 4787.8, 4840.3, 4945.3"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("594.2, 594.2, 594.2, 646.7, 751.8", \ + "748.2, 748.2, 748.2, 800.7, 905.8", \ + "1043.8, 1043.8, 1043.8, 1096.3, 1201.3", \ + "1619.7, 1619.7, 1619.7, 1672.2, 1777.3", \ + "2774.0, 2774.0, 2774.0, 2826.5, 2931.5"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("731.1, 731.1, 731.1, 783.7, 888.7", \ + "776.0, 776.0, 776.0, 828.5, 933.5", \ + "929.9, 929.9, 929.9, 982.4, 1087.5", \ + "1222.8, 1222.8, 1222.8, 1275.3, 1380.4", \ + "1777.2, 1777.2, 1777.2, 1829.7, 1934.8"); + } + } + } + } + + cell (one_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + pin (q) { + function : "1" ; + direction : output ; + capacitance : 1.34 ; + } + } + + cell (powmid_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + } + + cell (rowend_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + } + + cell (sff1r_x4) { + area : 0.0 ; + cell_leakage_power : 6 ; + leakage_power () { + when : "(ck & i & (!(nrst) | !(q)))" ; + value : 8.1 ; + } + leakage_power () { + when : "(q & nrst & !(i) & ck)" ; + value : 4.3 ; + } + leakage_power () { + when : "(q & nrst & i & !(ck))" ; + value : 8.4 ; + } + leakage_power () { + when : "((ck & i & nrst & q) | (!(ck) & i & nrst & !(q)))" ; + value : 4.9 ; + } + leakage_power () { + when : "(q & !(nrst) & i & !(ck))" ; + value : 7.1 ; + } + leakage_power () { + when : "(!(q) & !(nrst) & i & !(ck))" ; + value : 4.2 ; + } + leakage_power () { + when : "(!(q) & nrst & !(i) & !(ck))" ; + value : 4.5 ; + } + leakage_power () { + when : "((ck & !(i) & (!(nrst) | !(q))) | (!(ck) & !(i) & q))" ; + value : 7.4 ; + } + leakage_power () { + when : "(!(q) & !(nrst) & !(i) & !(ck))" ; + value : 5.1 ; + } + ff(iq,iq_neg) { + clocked_on : "ck" ; + next_state : "i" ; + clear : "!(nrst)" ; + + } + pin (nrst) { + direction : input ; + capacitance : 3.91 ; + internal_power (energy_nrst) { + rise_power (energy_inslew_5__0) { + values ("354.7, 390.8, 462.8, 606.8, 894.8"); + } + fall_power (energy_inslew_5__0) { + values ("392.9, 428.4, 499.4, 641.4, 925.3"); + } + } + } + pin (i) { + direction : input ; + capacitance : 4.23 ; + timing (i_ck_setup_rising) { + timing_type : setup_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("-182.2, -189.2, -195.4, -199.3, -199.2", \ + "-177.8, -184.8, -191.0, -194.9, -194.8", \ + "-175.2, -182.2, -188.4, -192.3, -192.2", \ + "-173.9, -180.9, -187.1, -191.0, -190.9", \ + "-173.8, -180.8, -187.0, -190.9, -190.8"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("-41.8, -45.5, -46.8, -43.4, -31.6", \ + "-33.5, -37.2, -38.5, -35.1, -23.3", \ + "-21.4, -25.1, -26.4, -23.0, -11.2", \ + "-1.1, -4.8, -6.1, -2.7, 9.1", \ + "35.6, 31.9, 30.6, 34.0, 45.8"); + } + } + timing (i_ck_hold_rising) { + timing_type : hold_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("215.8, 222.8, 229.0, 232.9, 232.8", \ + "211.4, 218.4, 224.6, 228.5, 228.4", \ + "208.8, 215.8, 222.0, 225.9, 225.8", \ + "207.5, 214.5, 220.7, 224.6, 224.5", \ + "207.4, 214.4, 220.6, 224.5, 224.4"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("86.0, 89.7, 91.0, 87.6, 75.8", \ + "77.7, 81.4, 82.7, 79.3, 67.5", \ + "65.6, 69.3, 70.6, 67.2, 55.4", \ + "45.3, 49.0, 50.3, 46.9, 35.1", \ + "8.6, 12.3, 13.6, 10.2, -1.6"); + } + } + internal_power (energy_i) { + rise_power (energy_inslew_5__0) { + values ("254.6, 302.8, 398.0, 587.6, 966.2"); + } + fall_power (energy_inslew_5__0) { + values ("265.3, 333.2, 467.7, 735.9, 1271.6"); + } + } + } + pin (ck) { + direction : input ; + capacitance : 4.20 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("577.7, 630.8, 735.1, 941.2, 1351.5"); + } + fall_power (energy_inslew_5__0) { + values ("639.2, 709.0, 846.5, 1119.7, 1664.9"); + } + } + } + pin (q) { + function : "iq" ; + direction : output ; + capacitance : 8.51 ; + timing (maxd_q_ck_rising_edge) { + timing_type : rising_edge ; + related_pin : "ck" ; + cell_fall (inslew_load_5x5__51) { + values ("105.7, 105.7, 105.7, 113.8, 127.8", \ + "108.2, 108.2, 108.2, 116.3, 130.4", \ + "104.8, 104.8, 104.8, 112.8, 127.2", \ + "90.2, 90.2, 90.2, 98.3, 112.9", \ + "47.3, 47.3, 47.3, 55.3, 70.3"); + } + fall_transition (inslew_load_5x5__51) { + values ("42.8, 42.8, 42.8, 48.2, 58.6", \ + "44.3, 44.3, 44.3, 49.7, 60.1", \ + "46.2, 46.2, 46.2, 51.7, 62.0", \ + "49.8, 49.8, 49.8, 55.4, 65.8", \ + "56.2, 56.2, 56.2, 61.9, 72.3"); + } + cell_rise (inslew_load_5x5__51) { + values ("140.6, 140.6, 140.6, 148.9, 163.7", \ + "147.2, 147.2, 147.2, 155.4, 170.3", \ + "152.0, 152.0, 152.0, 160.3, 175.3", \ + "151.6, 151.6, 151.6, 159.9, 175.1", \ + "139.5, 139.5, 139.5, 147.8, 163.2"); + } + rise_transition (inslew_load_5x5__51) { + values ("57.0, 57.0, 57.0, 68.0, 89.6", \ + "58.1, 58.1, 58.1, 69.1, 90.6", \ + "59.8, 59.8, 59.8, 70.8, 92.3", \ + "62.6, 62.6, 62.6, 73.6, 95.2", \ + "67.2, 67.2, 67.2, 78.2, 99.9"); + } + } + internal_power (energy_nun_q_ck) { + related_pin : "ck" ; + rise_power (energy_inslew_load_5x5__51) { + values ("584.1, 584.1, 584.1, 690.5, 903.1", \ + "590.8, 590.8, 590.8, 697.1, 909.8", \ + "601.4, 601.4, 601.4, 707.8, 920.4", \ + "619.1, 619.1, 619.1, 725.4, 938.1", \ + "648.6, 648.6, 648.6, 754.9, 967.6"); + } + fall_power (energy_inslew_load_5x5__51) { + values ("614.6, 614.6, 614.6, 720.9, 933.5", \ + "626.9, 626.9, 626.9, 733.2, 945.8", \ + "642.8, 642.8, 642.8, 749.1, 961.7", \ + "673.3, 673.3, 673.3, 779.6, 992.3", \ + "726.5, 726.5, 726.5, 832.8, 1045.5"); + } + } + } + } + + cell (sff1_x4) { + area : 0.0 ; + cell_leakage_power : 5.8 ; + leakage_power () { + when : "(q & i & ck)" ; + value : 3.8 ; + } + leakage_power () { + when : "(!(q) & i & ck)" ; + value : 8.5 ; + } + leakage_power () { + when : "(q & !(i) & ck)" ; + value : 3.1 ; + } + leakage_power () { + when : "(!(q) & !(i) & ck)" ; + value : 7.9 ; + } + ff(iq,iq_neg) { + clocked_on : "ck" ; + next_state : "i" ; + + } + pin (i) { + direction : input ; + capacitance : 5.25 ; + timing (i_ck_setup_rising) { + timing_type : setup_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("-149.9, -154.0, -155.0, -149.5, -132.2", \ + "-158.6, -162.7, -163.7, -158.2, -140.9", \ + "-163.0, -167.1, -168.1, -162.6, -145.3", \ + "-184.5, -188.6, -189.6, -184.1, -166.8", \ + "-234.9, -239.0, -240.0, -234.5, -217.2"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("-28.7, -28.8, -23.8, -8.8, 25.1", \ + "-16.8, -16.9, -11.9, 3.1, 37.0", \ + "3.0, 2.9, 7.9, 22.9, 56.8", \ + "38.7, 38.6, 43.6, 58.6, 92.5", \ + "107.4, 107.3, 112.3, 127.3, 161.2"); + } + } + timing (i_ck_hold_rising) { + timing_type : hold_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("169.9, 174.0, 175.0, 169.5, 152.2", \ + "178.6, 182.7, 183.7, 178.2, 160.9", \ + "183.0, 187.1, 188.1, 182.6, 165.3", \ + "204.5, 208.6, 209.6, 204.1, 186.8", \ + "254.9, 259.0, 260.0, 254.5, 237.2"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("63.7, 63.8, 58.8, 43.8, 9.9", \ + "51.8, 51.9, 46.9, 31.9, -2.0", \ + "32.0, 32.1, 27.1, 12.1, -21.8", \ + "-3.7, -3.6, -8.6, -23.6, -57.5", \ + "-72.4, -72.3, -77.3, -92.3, -126.2"); + } + } + internal_power (energy_i) { + rise_power (energy_inslew_5__0) { + values ("267.1, 310.0, 393.8, 559.8, 890.3"); + } + fall_power (energy_inslew_5__0) { + values ("309.9, 416.8, 627.7, 1048.2, 1888.1"); + } + } + } + pin (ck) { + direction : input ; + capacitance : 5.36 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("601.0, 663.4, 785.3, 1026.0, 1505.0"); + } + fall_power (energy_inslew_5__0) { + values ("691.5, 789.0, 981.3, 1363.8, 2127.7"); + } + } + } + pin (q) { + function : "iq" ; + direction : output ; + capacitance : 7.86 ; + timing (maxd_q_ck_rising_edge) { + timing_type : rising_edge ; + related_pin : "ck" ; + cell_fall (inslew_load_5x5__52) { + values ("95.7, 95.7, 95.7, 103.3, 116.6", \ + "95.4, 95.4, 95.4, 102.9, 116.3", \ + "87.5, 87.5, 87.5, 95.0, 108.5", \ + "64.9, 64.9, 64.9, 72.3, 86.1", \ + "7.8, 7.8, 7.8, 15.3, 29.3"); + } + fall_transition (inslew_load_5x5__52) { + values ("43.3, 43.3, 43.3, 48.4, 58.0", \ + "44.6, 44.6, 44.6, 49.7, 59.3", \ + "46.2, 46.2, 46.2, 51.4, 61.0", \ + "49.5, 49.5, 49.5, 54.7, 64.3", \ + "55.3, 55.3, 55.3, 60.6, 70.3"); + } + cell_rise (inslew_load_5x5__52) { + values ("112.4, 112.4, 112.4, 119.7, 132.9", \ + "115.8, 115.8, 115.8, 123.2, 136.4", \ + "115.1, 115.1, 115.1, 122.5, 135.8", \ + "104.5, 104.5, 104.5, 112.0, 125.5", \ + "73.5, 73.5, 73.5, 81.2, 94.9"); + } + rise_transition (inslew_load_5x5__52) { + values ("41.3, 41.3, 41.3, 51.5, 71.2", \ + "42.4, 42.4, 42.4, 52.6, 72.3", \ + "44.2, 44.2, 44.2, 54.3, 74.1", \ + "47.1, 47.1, 47.1, 57.2, 77.1", \ + "51.9, 51.9, 51.9, 62.0, 81.9"); + } + } + internal_power (energy_nun_q_ck) { + related_pin : "ck" ; + rise_power (energy_inslew_load_5x5__52) { + values ("480.5, 480.5, 480.5, 578.8, 775.3", \ + "487.2, 487.2, 487.2, 585.4, 781.9", \ + "497.8, 497.8, 497.8, 596.0, 792.6", \ + "515.9, 515.9, 515.9, 614.1, 810.6", \ + "545.7, 545.7, 545.7, 644.0, 840.5"); + } + fall_power (energy_inslew_load_5x5__52) { + values ("610.7, 610.7, 610.7, 709.0, 905.5", \ + "621.6, 621.6, 621.6, 719.8, 916.4", \ + "635.1, 635.1, 635.1, 733.4, 929.9", \ + "662.4, 662.4, 662.4, 760.7, 957.2", \ + "710.9, 710.9, 710.9, 809.2, 1005.7"); + } + } + } + } + + cell (sff2_x4) { + area : 0.0 ; + cell_leakage_power : 6.4 ; + leakage_power () { + when : "(ck & cmd & i1 & q)" ; + value : 5.1 ; + } + leakage_power () { + when : "(ck & cmd & i1 & !(q))" ; + value : 10 ; + } + leakage_power () { + when : "(ck & cmd & !(i1) & q)" ; + value : 3.7 ; + } + leakage_power () { + when : "(ck & cmd & !(i1) & !(q))" ; + value : 8.4 ; + } + leakage_power () { + when : "(ck & !(cmd) & i0 & q)" ; + value : 4.1 ; + } + leakage_power () { + when : "(ck & !(cmd) & i0 & !(q))" ; + value : 9.2 ; + } + leakage_power () { + when : "(ck & !(cmd) & !(i0) & q)" ; + value : 2.7 ; + } + leakage_power () { + when : "(ck & !(cmd) & !(i0) & !(q))" ; + value : 7.4 ; + } + ff(iq,iq_neg) { + clocked_on : "ck" ; + next_state : "((cmd & i1) | (!(cmd) & i0))" ; + + } + pin (i1) { + direction : input ; + capacitance : 3.99 ; + timing (i1_ck_setup_rising) { + timing_type : setup_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("-168.6, -175.2, -180.8, -184.2, -183.6", \ + "-162.8, -169.4, -175.0, -178.4, -177.8", \ + "-155.3, -161.9, -167.5, -170.9, -170.3", \ + "-145.4, -152.0, -157.6, -161.0, -160.4", \ + "-128.8, -135.4, -141.0, -144.4, -143.8"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("-0.7, -4.1, -5.0, -1.3, 10.8", \ + "8.0, 4.6, 3.7, 7.4, 19.5", \ + "22.6, 19.2, 18.3, 22.0, 34.1", \ + "49.1, 45.7, 44.8, 48.5, 60.6", \ + "99.4, 96.0, 95.1, 98.8, 110.9"); + } + } + timing (i1_ck_hold_rising) { + timing_type : hold_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("190.9, 197.5, 203.1, 206.5, 205.9", \ + "185.1, 191.7, 197.3, 200.7, 200.1", \ + "177.6, 184.2, 189.8, 193.2, 192.6", \ + "167.7, 174.3, 179.9, 183.3, 182.7", \ + "151.1, 157.7, 163.3, 166.7, 166.1"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("39.4, 42.8, 43.7, 40.0, 27.9", \ + "30.7, 34.1, 35.0, 31.3, 19.2", \ + "16.1, 19.5, 20.4, 16.7, 4.6", \ + "-10.4, -7.0, -6.1, -9.8, -21.9", \ + "-60.7, -57.3, -56.4, -60.1, -72.2"); + } + } + internal_power (energy_i1) { + rise_power (energy_inslew_5__0) { + values ("333.7, 387.5, 494.2, 706.6, 1130.4"); + } + fall_power (energy_inslew_5__0) { + values ("389.2, 465.3, 616.5, 918.8, 1520.1"); + } + } + } + pin (i0) { + direction : input ; + capacitance : 4.08 ; + timing (i0_ck_setup_rising) { + timing_type : setup_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("-168.6, -175.2, -180.8, -184.2, -183.6", \ + "-162.8, -169.4, -175.0, -178.4, -177.8", \ + "-155.3, -161.9, -167.5, -170.9, -170.3", \ + "-145.4, -152.0, -157.6, -161.0, -160.4", \ + "-128.8, -135.4, -141.0, -144.4, -143.8"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("-0.7, -4.1, -5.0, -1.3, 10.8", \ + "8.0, 4.6, 3.7, 7.4, 19.5", \ + "22.6, 19.2, 18.3, 22.0, 34.1", \ + "49.1, 45.7, 44.8, 48.5, 60.6", \ + "99.4, 96.0, 95.1, 98.8, 110.9"); + } + } + timing (i0_ck_hold_rising) { + timing_type : hold_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("190.9, 197.5, 203.1, 206.5, 205.9", \ + "185.1, 191.7, 197.3, 200.7, 200.1", \ + "177.6, 184.2, 189.8, 193.2, 192.6", \ + "167.7, 174.3, 179.9, 183.3, 182.7", \ + "151.1, 157.7, 163.3, 166.7, 166.1"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("39.4, 42.8, 43.7, 40.0, 27.9", \ + "30.7, 34.1, 35.0, 31.3, 19.2", \ + "16.1, 19.5, 20.4, 16.7, 4.6", \ + "-10.4, -7.0, -6.1, -9.8, -21.9", \ + "-60.7, -57.3, -56.4, -60.1, -72.2"); + } + } + internal_power (energy_i0) { + rise_power (energy_inslew_5__0) { + values ("333.7, 387.5, 494.2, 706.6, 1130.4"); + } + fall_power (energy_inslew_5__0) { + values ("389.2, 465.3, 616.5, 918.8, 1520.1"); + } + } + } + pin (cmd) { + direction : input ; + capacitance : 7.58 ; + timing (cmd_ck_setup_rising) { + timing_type : setup_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("-10.3, -13.7, -14.6, -10.9, 1.2", \ + "-3.1, -6.5, -7.4, -3.7, 8.4", \ + "4.2, 0.8, -0.1, 3.6, 15.7", \ + "12.5, 9.1, 8.2, 11.9, 24.0", \ + "23.0, 19.6, 18.7, 22.4, 34.5"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("-20.7, -24.1, -25.0, -21.3, -9.2", \ + "-8.1, -11.5, -12.4, -8.7, 3.4", \ + "11.0, 7.6, 6.7, 10.4, 22.5", \ + "44.0, 40.6, 39.7, 43.4, 55.5", \ + "105.3, 101.9, 101.0, 104.7, 116.8"); + } + } + timing (cmd_ck_hold_rising) { + timing_type : hold_rising ; + related_pin : "ck" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("203.0, 209.6, 215.2, 218.6, 218.0", \ + "200.1, 206.7, 212.3, 215.7, 215.1", \ + "200.2, 206.8, 212.4, 215.8, 215.2", \ + "206.6, 213.2, 218.8, 222.2, 221.6", \ + "223.4, 230.0, 235.6, 239.0, 238.4"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("173.5, 180.1, 185.7, 189.1, 188.5", \ + "165.2, 171.8, 177.4, 180.8, 180.2", \ + "153.9, 160.5, 166.1, 169.5, 168.9", \ + "136.8, 143.4, 149.0, 152.4, 151.8", \ + "108.4, 115.0, 120.6, 124.0, 123.4"); + } + } + internal_power (energy_cmd) { + rise_power (energy_inslew_5__0) { + values ("624.7, 683.5, 795.9, 1017.2, 1456.8"); + } + fall_power (energy_inslew_5__0) { + values ("675.7, 744.7, 880.4, 1149.8, 1687.6"); + } + } + } + pin (ck) { + direction : input ; + capacitance : 4.13 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("543.9, 596.9, 701.1, 907.2, 1317.3"); + } + fall_power (energy_inslew_5__0) { + values ("602.3, 672.1, 809.4, 1082.6, 1627.6"); + } + } + } + pin (q) { + function : "iq" ; + direction : output ; + capacitance : 7.76 ; + timing (maxd_q_ck_rising_edge) { + timing_type : rising_edge ; + related_pin : "ck" ; + cell_fall (inslew_load_5x5__53) { + values ("104.0, 104.0, 104.0, 111.4, 124.7", \ + "106.5, 106.5, 106.5, 113.9, 127.3", \ + "102.2, 102.2, 102.2, 109.6, 123.0", \ + "89.9, 89.9, 89.9, 97.2, 111.0", \ + "48.4, 48.4, 48.4, 55.8, 69.7"); + } + fall_transition (inslew_load_5x5__53) { + values ("44.1, 44.1, 44.1, 49.2, 58.6", \ + "45.5, 45.5, 45.5, 50.5, 60.0", \ + "46.4, 46.4, 46.4, 51.5, 61.0", \ + "51.0, 51.0, 51.0, 56.2, 65.7", \ + "57.4, 57.4, 57.4, 62.5, 72.2"); + } + cell_rise (inslew_load_5x5__53) { + values ("125.5, 125.5, 125.5, 132.8, 145.9", \ + "131.1, 131.1, 131.1, 138.4, 151.6", \ + "134.4, 134.4, 134.4, 141.8, 155.1", \ + "132.1, 132.1, 132.1, 139.7, 153.1", \ + "117.1, 117.1, 117.1, 124.7, 138.3"); + } + rise_transition (inslew_load_5x5__53) { + values ("43.4, 43.4, 43.4, 53.5, 73.0", \ + "44.4, 44.4, 44.4, 54.4, 74.0", \ + "46.0, 46.0, 46.0, 56.1, 75.7", \ + "48.9, 48.9, 48.9, 58.9, 78.5", \ + "53.6, 53.6, 53.6, 63.6, 83.3"); + } + } + internal_power (energy_nun_q_ck) { + related_pin : "ck" ; + rise_power (energy_inslew_load_5x5__53) { + values ("493.8, 493.8, 493.8, 590.8, 784.9", \ + "499.7, 499.7, 499.7, 596.7, 790.8", \ + "509.9, 509.9, 509.9, 606.9, 801.0", \ + "527.2, 527.2, 527.2, 624.2, 818.3", \ + "556.7, 556.7, 556.7, 653.7, 847.8"); + } + fall_power (energy_inslew_load_5x5__53) { + values ("617.9, 617.9, 617.9, 714.9, 909.0", \ + "629.1, 629.1, 629.1, 726.1, 920.2", \ + "637.0, 637.0, 637.0, 734.0, 928.1", \ + "675.2, 675.2, 675.2, 772.2, 966.3", \ + "728.1, 728.1, 728.1, 825.1, 1019.2"); + } + } + } + } + + cell (tie_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + } + + cell (xr2_x1) { + area : 0.0 ; + cell_leakage_power : 9.6 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 9.4 ; + } + leakage_power () { + when : "(i0 ^ i1)" ; + value : 1.7 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 18 ; + } + pin (i1) { + direction : input ; + capacitance : 12.39 ; + } + pin (i0) { + direction : input ; + capacitance : 11.05 ; + } + pin (q) { + function : "(i1 ^ i0)" ; + direction : output ; + capacitance : 4.16 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__54) { + values ("50.0, 50.0, 50.0, 62.3, 85.2", \ + "60.8, 60.8, 60.8, 73.1, 96.8", \ + "75.8, 75.8, 75.8, 88.9, 113.4", \ + "100.7, 100.7, 100.7, 114.4, 140.2", \ + "146.7, 146.7, 146.7, 160.9, 188.0"); + } + rise_transition (inslew_load_5x5__54) { + values ("39.5, 39.5, 39.5, 59.5, 99.2", \ + "57.0, 57.0, 57.0, 76.3, 116.0", \ + "86.4, 86.4, 86.4, 106.1, 145.2", \ + "140.9, 140.9, 140.9, 160.8, 200.1", \ + "246.8, 246.8, 246.8, 266.9, 306.7"); + } + cell_fall (inslew_load_5x5__54) { + values ("39.0, 39.0, 39.0, 48.6, 64.2", \ + "40.8, 40.8, 40.8, 50.9, 67.9", \ + "40.2, 40.2, 40.2, 51.1, 69.9", \ + "35.4, 35.4, 35.4, 47.4, 67.9", \ + "23.2, 23.2, 23.2, 35.6, 59.0"); + } + fall_transition (inslew_load_5x5__54) { + values ("23.3, 23.3, 23.3, 31.6, 47.4", \ + "30.7, 30.7, 30.7, 39.2, 55.3", \ + "44.4, 44.4, 44.4, 53.2, 69.7", \ + "71.1, 71.1, 71.1, 79.8, 97.1", \ + "123.7, 123.7, 123.7, 132.6, 150.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__54) { + values ("37.2, 37.2, 37.2, 48.7, 70.6", \ + "36.9, 36.9, 36.9, 48.7, 71.1", \ + "32.2, 32.2, 32.2, 44.3, 67.4", \ + "17.1, 17.1, 17.1, 29.5, 53.4", \ + "-18.5, -18.5, -18.5, -5.6, 19.3"); + } + rise_transition (inslew_load_5x5__54) { + values ("40.1, 40.1, 40.1, 60.0, 100.3", \ + "53.9, 53.9, 53.9, 73.6, 113.6", \ + "77.6, 77.6, 77.6, 97.8, 137.2", \ + "120.3, 120.3, 120.3, 139.9, 179.9", \ + "199.9, 199.9, 199.9, 219.6, 258.6"); + } + cell_fall (inslew_load_5x5__54) { + values ("50.5, 50.5, 50.5, 58.3, 72.3", \ + "61.1, 61.1, 61.1, 69.6, 85.0", \ + "77.6, 77.6, 77.6, 87.2, 104.3", \ + "107.9, 107.9, 107.9, 118.0, 137.0", \ + "165.6, 165.6, 165.6, 176.8, 197.6"); + } + fall_transition (inslew_load_5x5__54) { + values ("30.8, 30.8, 30.8, 38.8, 54.3", \ + "40.3, 40.3, 40.3, 48.4, 64.2", \ + "57.9, 57.9, 57.9, 66.2, 82.6", \ + "92.0, 92.0, 92.0, 100.7, 117.6", \ + "159.4, 159.4, 159.4, 168.4, 185.8"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__54) { + values ("52.2, 52.2, 52.2, 63.2, 84.9", \ + "60.0, 60.0, 60.0, 71.3, 93.4", \ + "74.0, 74.0, 74.0, 85.4, 108.0", \ + "101.1, 101.1, 101.1, 112.7, 135.8", \ + "154.6, 154.6, 154.6, 166.4, 190.0"); + } + rise_transition (inslew_load_5x5__54) { + values ("109.2, 109.2, 109.2, 128.6, 167.6", \ + "151.9, 151.9, 151.9, 171.1, 209.7", \ + "235.3, 235.3, 235.3, 254.1, 292.1", \ + "401.4, 401.4, 401.4, 420.1, 457.6", \ + "728.5, 728.5, 728.5, 747.4, 785.2"); + } + cell_fall (inslew_load_5x5__54) { + values ("25.6, 25.6, 25.6, 32.1, 44.7", \ + "26.6, 26.6, 26.6, 33.9, 47.7", \ + "26.0, 26.0, 26.0, 34.1, 49.6", \ + "22.9, 22.9, 22.9, 31.7, 48.6", \ + "15.4, 15.4, 15.4, 24.6, 42.6"); + } + fall_transition (inslew_load_5x5__54) { + values ("39.3, 39.3, 39.3, 47.1, 62.5", \ + "56.8, 56.8, 56.8, 64.7, 80.1", \ + "90.8, 90.8, 90.8, 98.8, 114.6", \ + "158.1, 158.1, 158.1, 166.2, 182.3", \ + "291.9, 291.9, 291.9, 300.2, 316.5"); + } + } + timing (maxd_q_i1_negative_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__54) { + values ("40.9, 40.9, 40.9, 52.1, 74.0", \ + "42.4, 42.4, 42.4, 53.9, 76.6", \ + "44.4, 44.4, 44.4, 56.3, 79.5", \ + "47.1, 47.1, 47.1, 59.4, 83.5", \ + "51.8, 51.8, 51.8, 64.4, 89.3"); + } + rise_transition (inslew_load_5x5__54) { + values ("89.7, 89.7, 89.7, 109.0, 147.8", \ + "122.9, 122.9, 122.9, 141.9, 180.2", \ + "186.8, 186.8, 186.8, 206.8, 244.4", \ + "314.6, 314.6, 314.6, 333.6, 371.4", \ + "569.8, 569.8, 569.8, 588.8, 626.7"); + } + cell_fall (inslew_load_5x5__54) { + values ("24.3, 24.3, 24.3, 31.8, 45.5", \ + "29.8, 29.8, 29.8, 38.2, 53.7", \ + "37.9, 37.9, 37.9, 47.2, 64.6", \ + "52.5, 52.5, 52.5, 62.4, 81.3", \ + "80.7, 80.7, 80.7, 91.0, 110.9"); + } + fall_transition (inslew_load_5x5__54) { + values ("33.7, 33.7, 33.7, 41.7, 57.3", \ + "54.1, 54.1, 54.1, 62.3, 78.2", \ + "93.0, 93.0, 93.0, 101.4, 117.9", \ + "169.9, 169.9, 169.9, 178.4, 195.3", \ + "322.8, 322.8, 322.8, 331.5, 348.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__54) { + values ("250.1, 250.1, 250.1, 302.1, 406.1", \ + "327.2, 327.2, 327.2, 379.2, 483.2", \ + "478.4, 478.4, 478.4, 530.4, 634.4", \ + "778.7, 778.7, 778.7, 830.7, 934.7", \ + "1378.1, 1378.1, 1378.1, 1430.1, 1534.1"); + } + fall_power (energy_inslew_load_5x5__54) { + values ("244.4, 244.4, 244.4, 296.4, 400.4", \ + "312.4, 312.4, 312.4, 364.4, 468.4", \ + "446.6, 446.6, 446.6, 498.6, 602.6", \ + "713.8, 713.8, 713.8, 765.8, 869.8", \ + "1247.5, 1247.5, 1247.5, 1299.5, 1403.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__54) { + values ("269.4, 269.4, 269.4, 321.4, 425.4", \ + "332.2, 332.2, 332.2, 384.2, 488.2", \ + "455.6, 455.6, 455.6, 507.6, 611.6", \ + "700.3, 700.3, 700.3, 752.3, 856.3", \ + "1188.1, 1188.1, 1188.1, 1240.1, 1344.1"); + } + fall_power (energy_inslew_load_5x5__54) { + values ("344.6, 344.6, 344.6, 396.6, 500.6", \ + "466.0, 466.0, 466.0, 518.0, 622.0", \ + "706.0, 706.0, 706.0, 758.0, 862.0", \ + "1184.2, 1184.2, 1184.2, 1236.2, 1340.2", \ + "2139.8, 2139.8, 2139.8, 2191.8, 2295.8"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__54) { + values ("279.0, 279.0, 279.0, 331.0, 435.0", \ + "377.2, 377.2, 377.2, 429.2, 533.2", \ + "573.8, 573.8, 573.8, 625.8, 729.8", \ + "966.8, 966.8, 966.8, 1018.8, 1122.8", \ + "1753.0, 1753.0, 1753.0, 1805.0, 1909.0"); + } + fall_power (energy_inslew_load_5x5__54) { + values ("226.1, 226.1, 226.1, 278.1, 382.1", \ + "299.6, 299.6, 299.6, 351.6, 455.6", \ + "446.5, 446.5, 446.5, 498.5, 602.5", \ + "740.4, 740.4, 740.4, 792.4, 896.4", \ + "1328.0, 1328.0, 1328.0, 1380.0, 1484.0"); + } + } + internal_power (energy_neg_q_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__54) { + values ("223.4, 223.4, 223.4, 275.4, 379.4", \ + "296.3, 296.3, 296.3, 348.3, 452.3", \ + "441.9, 441.9, 441.9, 493.9, 597.9", \ + "733.3, 733.3, 733.3, 785.3, 889.3", \ + "1316.0, 1316.0, 1316.0, 1368.0, 1472.0"); + } + fall_power (energy_inslew_load_5x5__54) { + values ("185.2, 185.2, 185.2, 237.2, 341.2", \ + "263.4, 263.4, 263.4, 315.4, 419.4", \ + "419.9, 419.9, 419.9, 471.9, 575.9", \ + "732.8, 732.8, 732.8, 784.8, 888.8", \ + "1358.7, 1358.7, 1358.7, 1410.7, 1514.7"); + } + } + } + } + + cell (xr2_x4) { + area : 0.0 ; + cell_leakage_power : 9.7 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 7.5 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 7.1 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 19 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 5.4 ; + } + pin (i1) { + direction : input ; + capacitance : 10.07 ; + } + pin (i0) { + direction : input ; + capacitance : 10.09 ; + } + pin (q) { + function : "(i0 ^ i1)" ; + direction : output ; + capacitance : 4.20 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("58.4, 58.4, 58.4, 62.7, 70.7", \ + "63.4, 63.4, 63.4, 67.8, 76.1", \ + "69.0, 69.0, 69.0, 73.4, 81.9", \ + "74.6, 74.6, 74.6, 79.3, 88.2", \ + "82.2, 82.2, 82.2, 86.7, 95.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("42.9, 42.9, 42.9, 48.4, 59.3", \ + "53.8, 53.8, 53.8, 59.4, 70.3", \ + "74.9, 74.9, 74.9, 80.4, 91.4", \ + "115.7, 115.7, 115.7, 121.3, 132.2", \ + "195.9, 195.9, 195.9, 201.6, 212.9"); + } + cell_fall (inslew_load_5x5__21) { + values ("92.5, 92.5, 92.5, 97.0, 105.1", \ + "101.1, 101.1, 101.1, 105.6, 114.0", \ + "116.0, 116.0, 116.0, 120.6, 129.3", \ + "144.0, 144.0, 144.0, 148.6, 157.7", \ + "198.6, 198.6, 198.6, 203.3, 212.4"); + } + fall_transition (inslew_load_5x5__21) { + values ("59.9, 59.9, 59.9, 62.7, 68.3", \ + "74.5, 74.5, 74.5, 77.3, 82.8", \ + "102.9, 102.9, 102.9, 105.7, 111.3", \ + "160.1, 160.1, 160.1, 162.9, 168.5", \ + "273.2, 273.2, 273.2, 275.9, 281.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("46.2, 46.2, 46.2, 50.5, 58.2", \ + "44.4, 44.4, 44.4, 48.7, 56.7", \ + "35.5, 35.5, 35.5, 39.9, 48.1", \ + "11.0, 11.0, 11.0, 15.6, 24.2", \ + "-44.4, -44.4, -44.4, -39.8, -30.8"); + } + rise_transition (inslew_load_5x5__21) { + values ("34.8, 34.8, 34.8, 40.3, 51.1", \ + "42.5, 42.5, 42.5, 48.0, 58.8", \ + "56.7, 56.7, 56.7, 62.3, 73.2", \ + "83.6, 83.6, 83.6, 89.1, 100.1", \ + "135.6, 135.6, 135.6, 141.3, 152.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("78.9, 78.9, 78.9, 83.3, 91.2", \ + "97.6, 97.6, 97.6, 102.1, 110.3", \ + "128.7, 128.7, 128.7, 133.3, 142.0", \ + "186.4, 186.4, 186.4, 191.0, 200.1", \ + "297.9, 297.9, 297.9, 302.5, 311.6"); + } + fall_transition (inslew_load_5x5__21) { + values ("47.0, 47.0, 47.0, 49.8, 55.4", \ + "63.9, 63.9, 63.9, 66.7, 72.2", \ + "94.9, 94.9, 94.9, 97.7, 103.3", \ + "156.5, 156.5, 156.5, 159.4, 164.9", \ + "278.9, 278.9, 278.9, 281.6, 287.2"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("84.2, 84.2, 84.2, 88.5, 96.3", \ + "93.0, 93.0, 93.0, 97.4, 105.4", \ + "104.7, 104.7, 104.7, 109.1, 117.3", \ + "121.5, 121.5, 121.5, 125.9, 134.4", \ + "149.1, 149.1, 149.1, 153.8, 162.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("36.0, 36.0, 36.0, 41.5, 52.3", \ + "41.9, 41.9, 41.9, 47.4, 58.3", \ + "52.6, 52.6, 52.6, 58.1, 69.0", \ + "72.5, 72.5, 72.5, 78.1, 89.1", \ + "111.4, 111.4, 111.4, 116.9, 127.9"); + } + cell_fall (inslew_load_5x5__21) { + values ("88.6, 88.6, 88.6, 92.8, 100.9", \ + "96.0, 96.0, 96.0, 100.2, 108.2", \ + "104.3, 104.3, 104.3, 108.6, 116.5", \ + "113.8, 113.8, 113.8, 118.3, 126.5", \ + "127.0, 127.0, 127.0, 131.6, 140.3"); + } + fall_transition (inslew_load_5x5__21) { + values ("35.7, 35.7, 35.7, 38.5, 43.9", \ + "40.7, 40.7, 40.7, 43.5, 49.0", \ + "49.5, 49.5, 49.5, 52.3, 57.9", \ + "65.7, 65.7, 65.7, 68.5, 74.0", \ + "96.9, 96.9, 96.9, 99.7, 105.3"); + } + } + timing (maxd_q_i1_negative_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("100.1, 100.1, 100.1, 104.5, 112.6", \ + "113.5, 113.5, 113.5, 117.9, 126.1", \ + "133.8, 133.8, 133.8, 138.3, 146.6", \ + "168.0, 168.0, 168.0, 172.6, 181.3", \ + "230.7, 230.7, 230.7, 235.3, 244.3"); + } + rise_transition (inslew_load_5x5__21) { + values ("45.3, 45.3, 45.3, 50.8, 61.7", \ + "53.1, 53.1, 53.1, 58.7, 69.6", \ + "67.6, 67.6, 67.6, 73.1, 84.1", \ + "95.3, 95.3, 95.3, 100.8, 111.8", \ + "149.3, 149.3, 149.3, 155.0, 166.0"); + } + cell_fall (inslew_load_5x5__21) { + values ("105.9, 105.9, 105.9, 110.2, 118.1", \ + "109.2, 109.2, 109.2, 113.5, 121.5", \ + "110.6, 110.6, 110.6, 115.1, 123.2", \ + "109.0, 109.0, 109.0, 113.5, 121.9", \ + "102.1, 102.1, 102.1, 106.7, 115.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("48.9, 48.9, 48.9, 51.7, 57.3", \ + "52.8, 52.8, 52.8, 55.6, 61.2", \ + "59.8, 59.8, 59.8, 62.6, 68.2", \ + "73.1, 73.1, 73.1, 75.9, 81.4", \ + "99.6, 99.6, 99.6, 102.4, 107.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__21) { + values ("676.5, 676.5, 676.5, 729.0, 834.0", \ + "819.5, 819.5, 819.5, 872.0, 977.1", \ + "1101.7, 1101.7, 1101.7, 1154.2, 1259.2", \ + "1661.6, 1661.6, 1661.6, 1714.1, 1819.1", \ + "2776.8, 2776.8, 2776.8, 2829.3, 2934.3"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("984.1, 984.1, 984.1, 1036.6, 1141.7", \ + "1205.8, 1205.8, 1205.8, 1258.3, 1363.4", \ + "1644.5, 1644.5, 1644.5, 1697.0, 1802.0", \ + "2523.8, 2523.8, 2523.8, 2576.3, 2681.4", \ + "4272.5, 4272.5, 4272.5, 4325.1, 4430.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__21) { + values ("532.2, 532.2, 532.2, 584.7, 689.7", \ + "617.8, 617.8, 617.8, 670.4, 775.4", \ + "784.5, 784.5, 784.5, 837.0, 942.1", \ + "1110.8, 1110.8, 1110.8, 1163.3, 1268.3", \ + "1755.8, 1755.8, 1755.8, 1808.3, 1913.3"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("774.9, 774.9, 774.9, 827.4, 932.5", \ + "1012.2, 1012.2, 1012.2, 1064.7, 1169.7", \ + "1464.4, 1464.4, 1464.4, 1517.0, 1622.0", \ + "2365.7, 2365.7, 2365.7, 2418.2, 2523.2", \ + "4160.3, 4160.3, 4160.3, 4212.8, 4317.8"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("659.8, 659.8, 659.8, 712.3, 817.3", \ + "768.9, 768.9, 768.9, 821.5, 926.5", \ + "979.8, 979.8, 979.8, 1032.4, 1137.4", \ + "1393.5, 1393.5, 1393.5, 1446.0, 1551.1", \ + "2215.7, 2215.7, 2215.7, 2268.2, 2373.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("732.9, 732.9, 732.9, 785.4, 890.4", \ + "835.9, 835.9, 835.9, 888.4, 993.4", \ + "1028.9, 1028.9, 1028.9, 1081.4, 1186.5", \ + "1402.2, 1402.2, 1402.2, 1454.8, 1559.8", \ + "2138.2, 2138.2, 2138.2, 2190.7, 2295.7"); + } + } + internal_power (energy_neg_q_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("826.5, 826.5, 826.5, 879.0, 984.0", \ + "969.3, 969.3, 969.3, 1021.8, 1126.9", \ + "1244.7, 1244.7, 1244.7, 1297.2, 1402.3", \ + "1786.2, 1786.2, 1786.2, 1838.7, 1943.7", \ + "2862.2, 2862.2, 2862.2, 2914.7, 3019.7"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("941.8, 941.8, 941.8, 994.3, 1099.3", \ + "1035.2, 1035.2, 1035.2, 1087.7, 1192.7", \ + "1212.9, 1212.9, 1212.9, 1265.4, 1370.4", \ + "1560.7, 1560.7, 1560.7, 1613.2, 1718.2", \ + "2253.5, 2253.5, 2253.5, 2306.0, 2411.0"); + } + } + } + } + + cell (zero_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + pin (nq) { + function : "0" ; + direction : output ; + capacitance : 1.37 ; + } + } + +} diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/nsxlib2.py b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/nsxlib2.py new file mode 100644 index 000000000..7eb5279fb --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/nsxlib2.py @@ -0,0 +1,217 @@ + +import sys +import os.path +from coriolis import Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, \ + BasicLayer, Cell, Net, Horizontal, Vertical, \ + Rectilinear, Box, Point, Instance, Transformation, \ + NetExternalComponents, Pad +import coriolis.Viewer +from coriolis.CRL import AllianceFramework, Environment, Gds, LefImport, \ + CellGauge, RoutingGauge, RoutingLayerGauge +from coriolis.helpers import l, u, n, overlay, io, ndaTopDir +from coriolis.helpers.overlay import CfgCache, UpdateSession +from coriolis.Anabatic import StyleFlags + + +__all__ = [ "setup" ] + + +def _routing (): + """ + Define the routing gauge along with the various P&R tool parameters. + """ + af = AllianceFramework.get() + db = DataBase.getDB() + tech = db.getTechnology() + rg = RoutingGauge.create('nsxlib2') + rg.setSymbolic( True ) + dirM1 = RoutingLayerGauge.Vertical + dirM2 = RoutingLayerGauge.Horizontal + netBuilderStyle = 'HV,3RL+' + routingStyle = StyleFlags.HV + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL1' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.PinOnly # layer usage + , 0 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 7.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL2' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 1 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL3' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 2 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(10.0) # track pitch + , l( 3.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL4' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 3 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(20.0) # track pitch + , l( 4.0) # wire width + , l( 4.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL5' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 4 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(20.0) # track pitch + , l( 4.0) # wire width + , l( 4.0) # perpandicular wire width + , l( 4.0) # VIA side + , l( 8.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL6' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.PowerSupply # layer usage + , 5 # depth + , 0.0 # density (deprecated) + , l( 0.0) # track offset from AB + , l(15.0) # track pitch + , l(12.0) # wire width + , l(12.0) # perpandicular wire width + , l( 4.0) # VIA side + , l( 8.0 ) )) # obstacle dW + af.addRoutingGauge( rg ) + af.setRoutingGauge( 'nsxlib2' ) + + cg = CellGauge.create( 'nsxlib2' + , 'METAL1' # pin layer name. + , l( 10.0) # pitch. + , l(100.0) # cell slice height. + , l( 10.0) # cell slice step. + ) + af.addCellGauge( cg ) + af.setCellGauge( 'nsxlib2' ) + + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + # Place & Route setup + cfg.viewer.minimumSize = 500 + cfg.viewer.pixelThreshold = 2 + cfg.lefImport.minTerminalWidth = 0.0 + cfg.crlcore.groundName = 'vss' + cfg.crlcore.powerName = 'vdd' + cfg.etesian.bloat = 'disabled' + cfg.etesian.aspectRatio = 1.00 + cfg.etesian.aspectRatio = [10, 1000] + cfg.etesian.spaceMargin = 0.10 + cfg.etesian.densityVariation = 0.05 + cfg.etesian.routingDriven = False + cfg.etesian.latchUpDistance = l(2000.0) + #cfg.etesian.diodeName = 'diode' + #cfg.etesian.antennaInsertThreshold = 0.50 + #cfg.etesian.antennaMaxWL = u(250.0) + cfg.etesian.feedNames = 'tie_x0,rowend_x0' + cfg.etesian.defaultFeed = 'tie_x0' + cfg.etesian.cell.zero = 'zero_x0' + cfg.etesian.cell.one = 'one_x0' + cfg.etesian.effort = 2 + cfg.etesian.effort = ( ('Fast' , 1) + , ('Standard', 2) + , ('High' , 3) + , ('Extreme' , 4) + ) + cfg.etesian.graphics = 2 + cfg.etesian.graphics = ( ('Show every step' , 1) + , ('Show lower bound', 2) + , ('Show result only', 3) + ) + cfg.anabatic.routingGauge = 'nsxlib2' + cfg.anabatic.cellGauge = 'nsxlib2' + cfg.anabatic.globalLengthThreshold = 30*l(100.0) + cfg.anabatic.saturateRatio = 0.90 + cfg.anabatic.saturateRp = 10 + cfg.anabatic.topRoutingLayer = 'METAL5' + cfg.anabatic.edgeLength = 192 + cfg.anabatic.edgeWidth = 32 + cfg.anabatic.edgeCostH = 9.0 + cfg.anabatic.edgeCostK = -10.0 + cfg.anabatic.edgeHInc = 1.0 + cfg.anabatic.edgeHScaling = 1.0 + cfg.anabatic.globalIterations = 10 + cfg.anabatic.globalIterations = [ 1, 100 ] + cfg.anabatic.gcell.displayMode = 1 + cfg.anabatic.gcell.displayMode = (("Boundary", 1), ("Density", 2)) + cfg.anabatic.netBuilderStyle = netBuilderStyle + cfg.anabatic.routingStyle = routingStyle + cfg.katana.disableStackedVias = False + cfg.katana.hTracksReservedLocal = 4 + cfg.katana.hTracksReservedLocal = [0, 20] + cfg.katana.vTracksReservedLocal = 3 + cfg.katana.vTracksReservedLocal = [0, 20] + cfg.katana.termSatReservedLocal = 8 + cfg.katana.termSatThreshold = 9 + cfg.katana.eventsLimit = 4000002 + cfg.katana.ripupCost = 3 + cfg.katana.ripupCost = [0, None] + cfg.katana.strapRipupLimit = 16 + cfg.katana.strapRipupLimit = [1, None] + cfg.katana.localRipupLimit = 9 + cfg.katana.localRipupLimit = [1, None] + cfg.katana.globalRipupLimit = 5 + cfg.katana.globalRipupLimit = [1, None] + cfg.katana.longGlobalRipupLimit = 5 + cfg.chip.padCoreSide = 'North' + # Plugins setup + cfg.clockTree.minimumSide = l(100.0) * 6 + cfg.clockTree.buffer = 'buf_x8' + cfg.clockTree.placerEngine = 'Etesian' + cfg.block.spareSide = 10*l(100.0) + cfg.spares.buffer = 'buf_x8' + cfg.spares.maxSinks = 31 + + +def _loadNsxlib2 ( cellsTop ): + """ + Setup for NSXLIB2 Alliance library. It is an symbolic library + from which cells are loaded on demand, so we only setup pathes. + + :param cellsTop: The top directory containing the cells views. + """ + af = AllianceFramework.get() + env = af.getEnvironment() + env.setSCALE_X ( 100 ) + env.setCATALOG ( 'CATAL' ) + env.setPOWER ( 'vdd' ) + env.setGROUND ( 'vss' ) + env.setCLOCK ( '^ck$|m_clock|^clk$' ) + env.setBLOCKAGE( 'blockage[Nn]et.*' ) + env.setPad ( '.*_mpx$' ) + env.setRegister( 'sff.*' ) + env.setWORKING_LIBRARY( '.' ) + env.addSYSTEM_LIBRARY ( library=(cellsTop / 'nsxlib2').as_posix(), mode=Environment.Append ) + + +def setup ( cellsTop ): + _routing() + _loadNsxlib2( cellsTop ) diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/sky130_nsx3.rds b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/sky130_nsx3.rds new file mode 100644 index 000000000..f8ac837bb --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/sky130_nsx3.rds @@ -0,0 +1,854 @@ +# 20230301 +# --------------------------------------------------------------------------- +# For SkyWater130 +# --------------------------------------------------------------------------- + + + + +# ------------------------------------------------------------------- +# globals define +# ------------------------------------------------------------------- + +define physical_grid 0.005 +define lambda 0.075 + +table cif_layer +# ------------------------------------------------------------------- +# rds_name cif_name +# ------------------------------------------------------------------- + rds_nwell nwell +# rds_pwell pwel + rds_activ diff + rds_ntie tap + rds_ptie tap + rds_ndif nsdm + rds_pdif psdm + rds_nimp nsdm + rds_pimp psdm + rds_poly poly + rds_alu1 li1 + rds_alu2 met1 + rds_alu3 met2 + rds_alu4 met3 + rds_alu5 met4 + rds_alu6 met5 + rds_cont licon1 + rds_via1 mcon + rds_via2 via + rds_via3 via2 + rds_via4 via3 + rds_via5 via4 + rds_poly2 npc + rds_cpas pad +end + +table gds_layer +# ------------------------------------------------------------------- +# rds_name gds_number gds_datatype gds_pin_layer gds_pin_datatype +# This version is incompatible with oriinal Alliance for 2nd number +# ------------------------------------------------------------------- + rds_nwell 64 20 + rds_pwell 64 44 + rds_activ 65 20 + rds_ptie 65 44 + rds_ntie 65 44 + rds_pdif 94 20 + rds_ndif 93 44 + rds_pimp 94 20 + rds_nimp 93 44 + rds_poly 66 20 + rds_alu1 67 20 67 16 + rds_alu2 68 20 68 16 + rds_alu3 69 20 69 16 + rds_alu4 70 20 70 16 + rds_alu5 71 20 71 16 + rds_alu6 72 20 72 16 + rds_cont 66 44 + rds_via1 67 44 + rds_via2 68 44 + rds_via3 69 44 + rds_via4 70 44 + rds_via5 71 44 + rds_poly2 95 20 + rds_cpas 76 20 +end + +table lynx_resistor +# ------------------------------------------------------------------- +# rds_name square_resistor(ohm/square) # typical values +# ------------------------------------------------------------------- + rds_poly 48 + rds_alu1 13 + rds_alu2 0.125 + rds_alu3 0.125 + rds_alu4 0.047 + rds_alu5 0.047 + rds_alu6 0.029 + rds_cont 15 + rds_via1 152 + rds_via2 4.5 + rds_via3 3.4 + rds_via4 3.4 + rds_via5 0.38 +end + +table lynx_capa +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- + rds_poly 106.2e-6 55.3e-6 # Ca max POLY_NWELL 2Cf0 max POLY_NWELL + rds_alu1 37.9e-6 40.7e-6 # Ca max M1_NWELL 2Cf0 max M1_NWELL + rds_alu2 25.8e-6 40.6e-6 # Ca max M2_NWELL 2Cf0 max M2_NWELL + rds_alu3 16.9e-6 37.8e-6 # Ca max M3_NWELL 2Cf0 max M3_NWELL + rds_alu4 12.4e-6 41.0e-6 # Ca max M4_NWELL 2Cf0 max M4_NWELL + rds_alu5 8.4e-6 36.7e-6 # hyp + rds_alu6 6.3e-6 38.9e-6 +end + +table lynx_capa_poly +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_poly2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu1 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu3 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu4 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu5 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end +table mbk_to_rds_segment +# ---------------------------------------------------------------------------------- +# mbk_name rds_name1 dlr dwr offset mode rds_name2 dlr dwr offset mode +# ---------------------------------------------------------------------------------- + + nwell rds_nwell vw 0.460 0.280 .0 all\ + rds_pimp vw 0.0 -0.80 .275 all \ + rds_nimp vw 0.0 -1.68 3.90 all +# rds_nimp vw 0.225 0.170 .0 all + +# pwell rds_pwell vw 0.460 0.280 .0 all +# rds_nimp vw 0.225 0.170 .0 all + + ndif rds_activ vw 0.0 0.0 .0 all\ + rds_nimp vw 0.0 0.0 .0 all\ + rds_ndif vw 0.0 0.0 .0 all + + pdif rds_activ vw 0.0 0.0 .0 all\ + rds_pimp vw 0.0 0.0 .0 all\ + rds_pdif vw 0.0 0.0 .0 all + + ntie rds_ntie vw 0.145 -0.100 .0 all\ + rds_nimp vw 0.270 0.200 .0 all\ + rds_nwell vw 0.460 0.490 .0 all + + ptie rds_ptie vw 0.145 -0.100 .0 all\ + rds_pimp vw 0.270 0.200 .0 all +# rds_pwell vw 0.460 0.510 .0 all + + + ntrans rds_poly vw 0.13 0.00 .0 all\ + rds_activ vw 0.0 0.50 .0 drc\ + rds_ndif lcw 0.0 0.26 0.0 ext\ + rds_ndif rcw 0.0 0.26 0.0 ext + + ptrans rds_poly vw 0.13 0.00 .0 all\ + rds_activ vw 0.0 0.50 .0 drc\ + rds_pdif lcw 0.0 0.26 0.0 ext\ + rds_pdif rcw 0.0 0.26 0.0 ext + + poly rds_poly vw 0.0 0.00 .0 all + + alu1 rds_alu1 vw 0.01 0.03 .0 all + calu1 rds_alu1 vw 0.01 0.03 .0 all + talu1 rds_talu1 vw 0.01 0.03 .0 all + + alu2 rds_alu2 vw 0.11 0.0 .0 all + calu2 rds_alu2 vw 0.11 0.0 .0 all + talu2 rds_talu2 vw 0.11 0.0 .0 all + + alu3 rds_alu3 vw 0.11 0.0 .0 all + calu3 rds_alu3 vw 0.11 0.0 .0 all + talu3 rds_talu3 vw 0.11 0.0 .0 all + + alu4 rds_alu4 vw 0.15 0.0 .0 all + calu4 rds_alu4 vw 0.15 0.0 .0 all + talu4 rds_talu4 vw 0.15 0.0 .0 all + + alu5 rds_alu5 vw 0.15 0.0 .0 all + calu5 rds_alu5 vw 0.15 0.0 .0 all + talu5 rds_talu5 vw 0.15 0.0 .0 all +end + +table mbk_to_rds_connector +# ------------------------------------------------------------------- +# mbk_name rds_name der dwr +# ------------------------------------------------------------------- +end + +table mbk_to_rds_reference +# ------------------------------------------------------------------- +# mbk_name rds_name width +# ------------------------------------------------------------------- + ref_ref rds_ref 0.330 + ref_con rds_ref 0.330 +end + +table mbk_to_rds_via +# ------------------------------------------------------------------- +# mbk_name rds_name1 width mode rds_name2 width mode ... +## ------------------------------------------------------------------ +# difftap.5 +# licon.7 0.170+0.120*2 + cont_body_n \ + rds_cont 0.170 all\ + rds_alu1 0.410 all\ + rds_nimp 0.430 all\ + rds_ntie 0.400 ext + +# licon.7 0.170+0.120*2 +# difftap.5 + cont_body_p \ + rds_cont 0.170 all\ + rds_alu1 0.410 all\ + rds_pimp 0.430 all\ + rds_ptie 0.400 ext + +# licon.5c + cont_dif_n \ + rds_cont 0.170 all\ + rds_alu1 0.330 all\ + rds_activ 0.290 drc\ + rds_ndif 0.420 ext + +# licon.5c + cont_dif_p \ + rds_cont 0.170 all\ + rds_alu1 0.330 all\ + rds_activ 0.290 drc\ + rds_pdif 0.420 ext + +# licon.8a +# NPC --> poly2 + cont_poly \ + rds_cont 0.170 all\ + rds_poly 0.330 all\ + rds_poly2 0.270 ext\ + rds_alu1 0.330 all + +# m1.4 +# NPC --> poly2 +# m1.5 + cont_via \ + rds_via1 0.170 all\ + rds_alu1 0.330 all\ + rds_poly2 0.270 ext\ + rds_alu2 0.330 all + +# via.1b +# via.5b +# m2.5 + cont_via2 \ + rds_via2 0.150 all\ + rds_alu2 0.370 all\ + rds_alu3 0.370 all + +# via.1b +# via.5b +# m2.5 + cont_via3 \ + rds_via3 0.200 all\ + rds_alu3 0.370 all\ + rds_alu4 0.370 all + + cont_via4 \ + rds_via4 0.200 all\ + rds_alu4 0.490 all\ + rds_alu5 0.380 all +end + +table mbk_to_rds_bigvia_hole +# ------------------------------------------------------------------- +# mbk_via_name rds_hole_name side step mode +# ------------------------------------------------------------------- +CONT_VIA RDS_VIA1 0.17 0.34 ALL +CONT_VIA2 RDS_VIA2 0.15 0.32 ALL +CONT_VIA3 RDS_VIA3 0.20 0.40 ALL +CONT_VIA4 RDS_VIA4 0.20 0.40 ALL # should be more than 4 +CONT_VIA5 RDS_VIA5 0.80 1.60 ALL # should be more than 4 +end + +table mbk_to_rds_bigvia_metal +# ------------------------------------------------------------------- +# mbk_via_name rds_name dwr overlap mode +# ------------------------------------------------------------------- +CONT_VIA RDS_ALU1 0.0 0.330 ALL RDS_ALU2 0.0 0.330 ALL +CONT_VIA2 RDS_ALU2 0.0 0.370 ALL RDS_ALU3 0.0 0.370 ALL +CONT_VIA3 RDS_ALU3 0.0 0.370 ALL RDS_ALU4 0.0 0.370 ALL +CONT_VIA4 RDS_ALU4 0.0 0.5 ALL RDS_ALU5 0.0 0.380 ALL +CONT_VIA5 RDS_ALU5 0.0 0.5 ALL RDS_ALU6 0.0 0.8 ALL +end + +table mbk_to_rds_turnvia +# ------------------------------------------------------------------- +# mbk_name rds_name dwr mode +# ------------------------------------------------------------------- + cont_turn1 rds_alu1 0.105 all + cont_turn2 rds_alu2 0.075 all + cont_turn3 rds_alu3 0.075 all + cont_turn4 rds_alu4 0.075 all + cont_turn5 rds_alu5 0.075 all +end + +table lynx_bulk_implicit +# ------------------------------------------------------------------- +# rds_name type[explicit|implicit] +# ------------------------------------------------------------------- +end + +table lynx_transistor +# ------------------------------------------------------------------- +# mbk_name trans_name compostion +# ------------------------------------------------------------------- + ntrans ntrans c_x_n rds_poly rds_ndif rds_ndif rds_pwell + ptrans ptrans c_x_p rds_poly rds_pdif rds_pdif rds_nwell +end + +table lynx_diffusion +# ------------------------------------------------------------------- +# rds_name compostion +# ------------------------------------------------------------------- + rds_ndif rds_activ 1 rds_nimp 1 rds_nwell 0 + rds_pdif rds_activ 1 rds_pimp 1 rds_nwell 1 + rds_ntie rds_activ 1 rds_nimp 1 rds_nwell 1 + rds_ptie rds_activ 1 rds_pimp 1 rds_nwell 0 +end + +table lynx_graph +# ------------------------------------------------------------------- +# rds_name in_contact_with rds_name1 rds_name2 ... +# ------------------------------------------------------------------- + rds_ndif rds_cont rds_ndif + rds_pdif rds_cont rds_pdif + rds_poly rds_cont rds_poly + rds_cont rds_pdif rds_ndif rds_poly rds_alu1 rds_cont + rds_alu1 rds_cont rds_via1 rds_ref rds_alu1 + rds_ref rds_cont rds_via1 rds_alu1 rds_ref + rds_alu2 rds_via1 rds_via2 rds_alu2 + rds_alu3 rds_via2 rds_via3 rds_alu3 + rds_alu4 rds_via3 rds_via4 rds_alu4 + rds_alu5 rds_via4 rds_via5 rds_alu5 + RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 + RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 + RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 + RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 + RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 +end + +table s2r_oversize_denotch +# ------------------------------------------------------------------- +# rds_name oversized_value_for_denotching +# ------------------------------------------------------------------- + rds_nwell 0.635 +# rds_pwell 0.635 + rds_poly 0.100 + rds_alu1 0.080 + rds_alu2 0.080 + rds_alu3 0.080 + rds_alu4 0.080 + rds_alu5 0.080 + rds_activ 0.130 + rds_ntie 0.190 + rds_ptie 0.190 + rds_nimp 0.190 + rds_pimp 0.190 +end + +table s2r_bloc_ring_width +# ------------------------------------------------------------------- +# rds_name ring_width_to_copy_up +# ------------------------------------------------------------------- + rds_nwell 0. # [ RD_NWEL ] +# rds_pwell 0. # [ RD_PWEL ] + rds_poly 0. # [ RD_POLY ] + rds_alu1 0. # [ RD_ALU1 ] + rds_alu2 0. # [ RD_ALU2 ] + rds_alu3 0. # [ RD_ALU3 ] + rds_alu4 0. # [ RD_ALU3 ] + rds_alu5 0. # [ RD_ALU3 ] + rds_activ 0. # [ RD_ACTI ] + rds_ntie 0. # [ RD_NIMP ] + rds_ptie 0. # [ RD_PIMP ] + rds_nimp 0. # [ RD_NIMP ] + rds_pimp 0. # [ RD_PIMP ] +end + +table s2r_minimum_layer_width +# ------------------------------------------------------------------- +# rds_name min_layer_width_to_keep +# ------------------------------------------------------------------- + rds_nwell 0.840 +# rds_pwell 0.840 + rds_poly 0.150 + rds_gate 0.150 + rds_alu1 0.170 + rds_alu2 0.170 + rds_alu3 0.170 + rds_alu4 0.300 + rds_alu5 0.300 + rds_activ 0.420 + rds_ntie 0.380 + rds_ptie 0.380 + rds_nimp 0.380 + rds_pimp 0.380 +end + +table s2r_post_treat +# ------------------------------------------------------------------- +# rds_name s2r_must_treat_or_not second_layer_whenever_scotch +# ------------------------------------------------------------------- + rds_nwell treat null +# rds_pwell treat null + rds_poly treat null + rds_activ treat null + rds_ntie treat rds_pimp + rds_ptie treat rds_nimp + rds_nimp treat rds_ptie + rds_pimp treat rds_ntie + rds_alu1 treat null + rds_alu2 treat null + rds_alu3 treat null + rds_alu4 treat null + rds_alu5 treat null + rds_cont notreat null +end + +DRC_RULES + +layer RDS_NWELL 0.840 ; +layer RDS_NTIE 0.380 ; +layer RDS_PTIE 0.380 ; +layer RDS_NIMP 0.380 ; +layer RDS_PIMP 0.380 ; +layer RDS_ACTIV 0.420 ; +layer RDS_CONT 0.170 ; +layer RDS_POLY 0.150 ; +layer RDS_VIA1 0.170 ; +layer RDS_VIA2 0.170 ; +layer RDS_VIA3 0.170 ; +layer RDS_VIA4 0.170 ; +layer RDS_VIA5 0.170 ; +layer RDS_ALU1 0.170 ; +layer RDS_ALU2 0.170 ; +layer RDS_ALU3 0.170 ; +layer RDS_ALU4 0.300 ; +layer RDS_ALU5 0.300 ; +layer RDS_ALU6 0.300 ; +layer RDS_USER0 0.005 ; +layer RDS_USER1 0.005 ; +layer RDS_USER2 0.005 ; + +regles + +# note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# there is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# ---------------------------------------------------------- + +# check the nwell shapes +# ---------------------- +characterize RDS_NWELL ( + rule 1 : width >= 0.840 ; + rule 2 : intersection_length min 0.840 ; + rule 3 : notch >= 1.270 ; +); +relation RDS_NWELL , RDS_NWELL ( + rule 4 : spacing axial min 1.270 ; +); +relation RDS_NWELL , RDS_ACTI ( + rule 5 : spacing axial min 0.340 ; +); + +# check the RDS_PIMP shapes +# ------------------------- +characterize RDS_PIMP ( + rule 6 : surface min 0.265 ; + rule 7 : width >= 0.380 ; + rule 8 : intersection_length min 0.380 ; + rule 9 : notch >= 0.380 ; +); +relation RDS_PIMP , RDS_PIMP ( + rule 10 : spacing axial min 0.380 ; +); + +# check the RDS_NIMP shapes +# ------------------------- +characterize RDS_NIMP ( + rule 11 : surface min 0.265 ; + rule 12 : width >= 0.380 ; + rule 13 : intersection_length min 0.380 ; + rule 14 : notch >= 0.380 ; +); +relation RDS_NIMP , RDS_NIMP ( + rule 15 : spacing axial min 0.380 ; +); + +# check the RDS_PTIE shapes +# ------------------------- +characterize RDS_PTIE ( +# rule 16 : surface min 0.255 ; + rule 17 : width >= 0.150 ; + rule 18 : intersection_length min 0.150 ; + rule 19 : notch >= 0.270 ; +); +relation RDS_PTIE , RDS_PTIE ( + rule 20 : spacing axial min 0.270 ; +); + +# check the RDS_NTIE shapes +# ------------------------- +characterize RDS_NTIE ( +# rule 21 : surface min 0.265 ; + rule 22 : width >= 0.150 ; + rule 23 : intersection_length min 0.150 ; + rule 24 : notch >= 0.270 ; +); +relation RDS_NTIE , RDS_NTIE ( + rule 25 : spacing axial min 0.270 ; +); + +# check the RDS_ACTI shapes +# ------------------------- +characterize RDS_ACTI ( + rule 26 : surface min 0.000 ; + rule 27 : width >= 0.420 ; + rule 28 : intersection_length min 0.420 ; + rule 29 : notch >= 0.270 ; +); +relation RDS_ACTI, RDS_ACTI ( + rule 30 : spacing axial min 0.270 ; +); + +# check the RDS_NIMP RDS_PTIE exclusion +# ------------------------------------- +define RDS_NIMP , RDS_PTIE intersection -> NPIMP; +characterize NPIMP ( + rule 31 : width = 0. ; +); +undefine NPIMP; + +# check the RDS_NTIE RDS_PIMP exclusion +# ------------------------------------- +define RDS_NTIE , RDS_PIMP intersection -> NPIMP; +characterize NPIMP ( + rule 32 : width = 0. ; +); +undefine NPIMP; + +# check the RDS_POLY shapes +# ------------------------- +characterize RDS_POLY ( + rule 33 : width >= 0.150 ; + rule 34 : intersection_length min 0.150 ; + rule 35 : notch >= 0.210 ; +); +relation RDS_POLY , RDS_POLY ( + rule 36 : spacing axial min 0.210 ; +); + +define RDS_ACTI , RDS_POLY intersection -> channel; + + # check the channel shapes + # ------------------------- + characterize channel ( + rule 37 : notch >= 0.210 ; + ); + relation channel , channel ( + rule 38 : spacing axial min 0.210 ; + ); + +undefine channel; + +define RDS_ACTI , RDS_CONT intersection -> cont_diff; + + relation RDS_POLY , cont_diff ( + rule 39 : spacing axial >= 0.055 ; + ); + +undefine cont_diff; + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_CONT , RDS_CONT ( + rule 40 : spacing axial >= 0.170 ; +); + +characterize RDS_CONT ( + rule 41 : width = 0.170 ; + rule 42 : length = 0.170 ; +); + +# check RDS_POLY is distant from activ zone of transistor +# ------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + rule 43 : spacing axial >= 0.075 ; +); + +# check RDS_ALU1 shapes +# --------------------- +characterize RDS_ALU1 ( + rule 44 : surface min 0.060 ; + rule 45 : width >= 0.170 ; + rule 46 : intersection_length min 0.170 ; + rule 47 : notch >= 0.170 ; +); +relation RDS_ALU1 , RDS_ALU1 ( + rule 48 : spacing axial min 0.170 ; +); + +# check mcon layers, stacking are free +# --------------------------------------- +relation RDS_VIA1 , RDS_VIA1 ( + rule 49 : spacing axial >= 0.190 ; +); + +characterize RDS_VIA1 ( + rule 50 : width = 0.170 ; + rule 51 : length = 0.170 ; +); + + +# check RDS_ALU2 shapes +# --------------------- +characterize RDS_ALU2 ( +# rule 52 : surface min 0.085 ; + rule 53 : width >= 0.140 ; + rule 54 : intersection_length min 0.140 ; + rule 55 : notch >= 0.140 ; +); +relation RDS_ALU2 , RDS_ALU2 ( + rule 56 : spacing axial min 0.140 ; +); + + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_VIA2 , RDS_VIA2 ( + rule 57 : spacing axial >= 0.170 ; +); + +characterize RDS_VIA2 ( + rule 58 : width = 0.150 ; + rule 59 : length = 0.150 ; +); + + +# check RDS_ALU3 shapes +# --------------------- +characterize RDS_ALU3 ( +# rule 60 : surface min 0.070 ; + rule 61 : width >= 0.140 ; + rule 62 : intersection_length min 0.140 ; + rule 63 : notch >= 0.140 ; +); +relation RDS_ALU3 , RDS_ALU3 ( + rule 64 : spacing axial min 0.140 ; +); + + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_VIA3 , RDS_VIA3 ( + rule 65 : spacing axial >= 0.200 ; +); + +characterize RDS_VIA3 ( + rule 66 : width = 0.200 ; + rule 67 : length = 0.200 ; +); +# check RDS_ALU4 shapes +# --------------------- +characterize RDS_ALU4 ( +# rule 68 : surface min 0.240 ; + rule 69 : width >= 0.300 ; + rule 70 : intersection_length min 0.300 ; + rule 71 : notch >= 0.300 ; +); +relation RDS_ALU4 , RDS_ALU4 ( + rule 72 : spacing axial min 0.300 ; +); + + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_VIA4 , RDS_VIA4 ( + rule 73 : spacing axial >= 0.200 ; +); + +characterize RDS_VIA4 ( + rule 74 : width = 0.200 ; + rule 75 : length = 0.200 ; +); + +# check RDS_ALU5 shapes +# --------------------- +characterize RDS_ALU5 ( +# rule 76 : surface min 0.240 ; + rule 77 : width >= 0.300 ; + rule 78 : intersection_length min 0.300 ; + rule 79 : notch >= 0.300 ; +); +relation RDS_ALU5 , RDS_ALU5 ( + rule 80 : spacing axial min 0.300 ; +); + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_VIA5 , RDS_VIA5 ( + rule 81 : spacing axial >= 0.200 ; +); + +characterize RDS_VIA5 ( + rule 82 : width = 0.200 ; + rule 83 : length = 0.200 ; +); + + +# check RDS_ALU6 shapes +# --------------------- +characterize RDS_ALU6 ( +# rule 84 : surface min 0.240 ; + rule 85 : width >= 0.300 ; + rule 86 : intersection_length min 0.300 ; + rule 87 : notch >= 0.300 ; +); +relation RDS_ALU6 , RDS_ALU6 ( + rule 88 : spacing axial min 0.300 ; +); + +end rules +DRC_COMMENT +1 (RDS_NWELL) Minimum width 0.840 +2 (RDS_NWELL) Intersection length 0.840 +3 (RDS_NWELL) Notch 1.270 +4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 1.270 +5 (RDS_NWELL,RDS_ACTI) Manhatan distance min 0.340 +6 (RDS_PIMP) Minimum area 0.265 +7 (RDS_PIMP) Minimum width 0.380 +8 (RDS_PIMP) Intersection length 0.380 +9 (RDS_PIMP) Notch 0.380 +10 (RDS_PIMP,RDS_PIMP) Manhatan distance min 0.380 +11 (RDS_NIMP) Minimum area 0.265 +12 (RDS_NIMP) Minimum width 0.380 +13 (RDS_NIMP) Intersection length 0.380 +14 (RDS_NIMP) Notch 0.380 +15 (RDS_NIMP,RDS_NIMP) Manhatan distance min 0.380 +16 (RDS_PTIE) Minimum area 0.255 +17 (RDS_PTIE) Minimum width 0.150 +18 (RDS_PTIE) Intersection length 0.150 +19 (RDS_PTIE) Notch 0.270 +20 (RDS_PTIE,RDS_PTIE) Manhatan distance min 0.270 +21 (RDS_NTIE) Minimum area 0.265 +22 (RDS_NTIE) Minimum width 0.150 +23 (RDS_NTIE) Intersection length 0.150 +24 (RDS_NTIE) Notch 0.270 +25 (RDS_NTIE,RDS_NTIE) Manhatan distance min 0.270 +26 (RDS_ACTI) Minimum area 0.0 +27 (RDS_ACTI) Minimum width 0.420 +28 (RDS_ACTI) Intersection length 0.420 +29 (RDS_ACTI) Notch 0.270 +30 (RDS_ACTI,RDS_ACTI) Manhatan distance min 0.270 +31 (RDS_NIMP,RDS_PTIE) intersection width 0. +32 (RDS_PIMP,RDS_NTIE) intersection width 0. +33 (RDS_POLY) Minimum width 0.150 +34 (RDS_POLY) Intersection length 0.150 +35 (RDS_POLY) Notch 0.210 +36 (RDS_POLY,RDS_POLY) Manhatan distance min 0.210 +37 (channel) Notch 0.210 +38 (channel) Manhatan distance min 0.210 +39 (cont_diff) Manhatan distance min 0.055 +40 (RDS_CONT,RDS_CONT) Manhatan distance min 0.170 +41 (RDS_CONT) Width 0.170 +42 (RDS_CONT) Length 0.170 +43 (RDS_POLY,RDS_ACTIV) Manhatan distance min 0.075 +44 (RDS_ALU1) Minimum area 0.060 +45 (RDS_ALU1) Minimum width 0.170 +46 (RDS_ALU1) Intersection length 0.170 +47 (RDS_ALU1) Notch 0.170 +48 (RDS_ALU1,RDS_ALU1) Manhatan distance min 0.170 +49 (RDS_VIA1,RDS_VIA1) Manhatan distance mcon min 0.190 +50 (RDS_VIA1) mcon width 0.170 +51 (RDS_VIA1) mcon length 0.170 +52 (RDS_ALU2) Minimum area 0.083 +53 (RDS_ALU2) Minimum width 0.140 +54 (RDS_ALU2) Intersection length 0.140 +55 (RDS_ALU2) Notch 0.140 +56 (RDS_ALU2,RDS_ALU2) Manhatan distance min 0.140 +57 (RDS_VIA2,RDS_VIA2) Manhatan distance via min 0.170 +58 (RDS_VIA2) via width 0.150 +59 (RDS_VIA2) via length 0.150 +60 (RDS_ALU3) Minimum area 0.0676 +61 (RDS_ALU3) Minimum width 0.140 +62 (RDS_ALU3) Intersection length 0.140 +63 (RDS_ALU3) Notch 0.140 +64 (RDS_ALU3,RDS_ALU3) Manhatan distance min 0.140 +65 (RDS_VIA3,RDS_VIA3) Manhatan distance via min 0.200 +66 (RDS_VIA3) via width 0.200 +67 (RDS_VIA3) via length 0.200 +68 (RDS_ALU4) Minimum area 0.240 +69 (RDS_ALU4) Minimum width 0.300 +70 (RDS_ALU4) Intersection length 0.300 +71 (RDS_ALU4) Notch 0.300 +72 (RDS_ALU4,RDS_ALU4) Manhatan distance min 0.300 +73 (RDS_VIA4,RDS_VIA4) Manhatan distance via min 0.200 +74 (RDS_VIA4) via width 0.200 +75 (RDS_VIA4) via length 0.200 +76 (RDS_ALU5) Minimum area 0.240 +77 (RDS_ALU5) Minimum width 0.300 +78 (RDS_ALU5) Intersection length 0.300 +79 (RDS_ALU5) Notch 0.300 +80 (RDS_ALU5,RDS_ALU5) Manhatan distance min 0.300 +81 (RDS_VIA5,RDS_VIA5) Manhatan distance via min 0.200 +82 (RDS_VIA5) via width 0.200 +83 (RDS_VIA5) via length 0.200 +84 (RDS_ALU6) Minimum area 0.240 +85 (RDS_ALU6) Minimum width 0.300 +86 (RDS_ALU6) Intersection length 0.300 +87 (RDS_ALU6) Notch 0.300 +88 (RDS_ALU6,RDS_ALU6) Manhatan distance min 0.300 +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/spimodel.cfg b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/spimodel.cfg new file mode 100644 index 000000000..0baf5c491 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/spimodel.cfg @@ -0,0 +1,5 @@ +# MBK_SPI_MODEL +# configure the transistor models of spi parser/driver +# +sky130_fd_pr__nfet_01v8 N SUBCKT +sky130_fd_pr__pfet_01v8 P SUBCKT diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/symbolic.dreal b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/symbolic.dreal new file mode 100644 index 000000000..3c39bd85c --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/symbolic.dreal @@ -0,0 +1,127 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Dreal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 02/08/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +dEFINE DREAL_LOWER_FIGURE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_INSTANCE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_CONNECTOR_STEP 0.5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_SEGMENT_STEP 0.7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_REFERENCE_STEP 1.0 + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TAbLE DREAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/symbolic.graal b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/symbolic.graal new file mode 100644 index 000000000..cae4dcf0b --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/symbolic.graal @@ -0,0 +1,386 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Graal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 27/06/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Graal Peek Bound in lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_PEEK_BOUND 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_FIGURE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_INSTANCE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_CONNECTOR_STEP 5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_SEGMENT_STEP 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_REFERENCE_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | Segment Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_NAME + + NWELL Nwell tan Black + PWELL Pwell light_yellow Black + NDIF Ndif lawn_green Black + PDIF Pdif yellow Black + NTIE Ntie spring_green Black + PTIE Ptie light_goldenrod Black + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 GReen Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + TPOLY Tpoly hot_pink Black + TALU1 Talu1 royal_blue Black + TALU2 Talu2 turquoise Black + TALU3 Talu3 light_pink Black + TALU4 Talu4 green Black + TALU5 Talu5 yellow Black + TALU6 Talu6 violet Black + TALU7 Talu7 red Black + TALU8 Talu8 blue Black + CALU1 CAlu1 royal_blue Black + CALU2 CAlu2 Cyan Black + CALU3 CAlu3 light_pink Black + CALU4 CAlu4 green Black + CALU5 CAlu5 yellow Black + CALU6 CAlu6 violet Black + CALU7 CAlu7 red Black + CALU8 CAlu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Transistor Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_TRANSISTOR_NAME + + NTRANS Ntrans lawn_green Black + PTRANS Ptrans yellow Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Connector Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_CONNECTOR_NAME + + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 green Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Length and Width for a symbolic Segment | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_VALUE + + NWELL 4 4 + PWELL 4 4 + NDIF 3 2 # LSX 2 -> 3 + PDIF 3 2 # LSX 2 -> 3 + NTIE 3 1 # LSX 2 -> 3 + PTIE 3 1 # LSX 2 -> 3 + NTRANS 1 5 # LSX 4 -> 5 + PTRANS 1 5 # LSX 4 -> 5 + POLY 1 1 + POLY2 1 1 + ALU1 2 1 # LSX 1 -> 2 + ALU2 2 1 + ALU3 2 1 + ALU4 2 1 + ALU5 2 1 + ALU6 2 1 + ALU7 2 1 + ALU8 2 1 + TPOLY 1 1 + TALU1 2 1 # LSX 1 -> 2 + TALU2 2 1 # LSX 2 -> 1 + TALU3 2 1 # LSX 2 -> 1 + TALU4 2 1 # LSX 2 -> 1 + TALU5 2 1 # LSX 2 -> 1 + TALU6 2 1 # LSX 2 -> 1 + TALU7 2 1 # LSX 2 -> 1 + TALU8 2 1 # LSX 2 -> 1 + CALU1 2 0 + CALU2 2 0 + CALU3 2 0 + CALU4 2 0 + CALU5 2 0 + CALU6 2 0 + CALU7 2 0 + CALU8 2 0 + +END + +# /*------------------------------------------------------------\ +# | | +# | Reference Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_REFERENCE_NAME + + REF_REF Ref_Ref red Black + REF_CON Ref_Con Cyan Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_VIA_NAME + + CONT_DIF_N Cont_NDif lawn_green Black + CONT_DIF_P Cont_PDif yellow Black + CONT_BODY_N Cont_NTie spring_green Black + CONT_BODY_P Cont_PTie light_goldenrod Black + CONT_POLY Cont_Poly red Black + CONT_POLY2 Cont_Poly2 orange Black + CONT_VIA Via_1-2 cyan Black + CONT_VIA2 Via_2-3 light_pink Black + CONT_VIA3 Via_3-4 green Black + CONT_VIA4 Via_4-5 yellow Black + CONT_VIA5 Via_5-6 violet Black + CONT_VIA6 Via_6-7 red Black + CONT_VIA7 Via_7-8 blue Black + C_X_N Cont_CxN orange Black + C_X_P Cont_CxP orange Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Big Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_NAME + + CONT_VIA Big_Via_1-2 cyan Black + CONT_VIA2 Big_Via_2-3 light_pink Black + CONT_VIA3 Big_Via_3-4 green Black + CONT_VIA4 Big_Via_4-5 yellow Black + CONT_VIA5 Big_Via_5-6 violet Black + CONT_VIA6 Big_Via_6-7 red Black + CONT_VIA7 Big_Via_7-8 blue Black + + CONT_TURN1 Turn_Via_1 royal_blue Black + CONT_TURN2 Turn_Via_2 Cyan Black + CONT_TURN3 Turn_Via_3 light_pink Black + CONT_TURN4 Turn_Via_4 green Black + CONT_TURN5 Turn_Via_5 yellow Black + CONT_TURN6 Turn_Via_6 violet Black + CONT_TURN7 Turn_Via_7 red Black + CONT_TURN8 Turn_Via_7 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Size for a symbolic Big Via | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_VALUE + + CONT_VIA 2 + CONT_VIA2 2 + CONT_VIA3 2 + CONT_VIA4 2 + CONT_VIA5 2 + CONT_VIA6 2 + CONT_VIA7 2 + + CONT_TURN1 2 + CONT_TURN2 2 + CONT_TURN3 2 + CONT_TURN4 2 + CONT_TURN5 2 + CONT_TURN6 2 + CONT_TURN7 2 + CONT_TURN8 2 + +END + +# /*------------------------------------------------------------\ +# | | +# | Orient Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_ORIENT_NAME + + NORTH North lawn_green Black + SOUTH South yellow Black + EAST East tan Black + WEST West red Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Symmetry Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SYMMETRY_NAME + + NOSYM No_Sym LightBlue Black + SYM_X Sym_X turquoise Black + SYM_Y Sym_Y cyan Black + SYMXY Sym_XY lightCyan Black + ROT_P Rot_P MediumAquamarine Black + ROT_M Rot_M aquamarine Black + SY_RP Sym_RP green Black + SY_RM Sym_RM MediumSpringGreen Black + +END + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/symbolic.rds b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/symbolic.rds new file mode 100644 index 000000000..ed3608dfe --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/symbolic.rds @@ -0,0 +1,948 @@ +#===================================================================== +# +# ALLIANCE VLSI CAD +# (R)eal (D)ata (S)tructure parameter file +# (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI +# all rights reserved +# e-mail : cao-vlsi@masi.ibp.fr +# +# file : cmos.rds +# version : 12 +# last modif : Apr 4, 2002, Feb 24, 2023 +# +##------------------------------------------------------------------- +# Symbolic to micron on a 'one lambda equals one micron' basis +##------------------------------------------------------------------- +# Refer to the documentation for more precise information. +#===================================================================== +# 1/05/23 +# . no more CXN and CXP +# +# 01/11/09 ALU5/6 pitch 10 +# +# 99/11/3 ALU5/6 rules +# . theses rules are preliminary rules, we hope that they wil change +# in future. For now, ALU5/6 are dedicated to supplies an clock. +# +# 99/3/22 new symbolics rules +# . ALU1 width remains 1, ALU2/3/4 is 2 +# . ALU1/2/3/4 distance (edge to edge) is now 3 for all +# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2 +# . All via stacking are allowed +# +# 98/12/1 drc rules were updated +# distance VIA to POLY or gate is one rather 2 +# VIA2 and ALU3 appeared +# . ALU3 width is 3 +# . ALU2/VIA2/ALU3 is resp. 3/1/3 +# . ALU3 edge distance is 2 +# . stacked VIA/VIA2 is allowed +# . if they are not stacked they must distant of 2 +# . CONT/VIA2 is free +# note +# . stacked CONT/VIA is always not allowed +# NWELL is automatically drawn with the DIFN and NTIE layers +#===================================================================== + +##------------------------------------------------------------------- +# PHYSICAL_GRID : +##------------------------------------------------------------------- + +DEFINE PHYSICAL_GRID .5 + +##------------------------------------------------------------------- +# LAMBDA : +##------------------------------------------------------------------- + +DEFINE LAMBDA 1 + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_SEGMENT : +# +# MBK RDS layer 1 RDS layer 2 +# name name TRANS DLR DWR OFFSET name TRANS DLR DWR OFFSET ... +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_SEGMENT + + PWELL RDS_PWELL VW 2.0 0.0 0.0 EXT + NWELL RDS_NWELL VW 2.0 0.0 0.0 ALL + NDIF RDS_NDIF VW 0.5 0.0 0.0 ALL + PDIF RDS_PDIF VW 0.5 0.0 0.0 ALL + NTIE RDS_NTIE VW 1.5 0.0 0.0 ALL\ + RDS_NWELL VW 2.0 5.0 0.0 ALL + PTIE RDS_PTIE VW 1.5 0.0 0.0 ALL\ + RDS_PWELL VW 2.0 5.0 0.0 ALL # LSX DLR 0.5 -> 1.5 + NTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \ + RDS_NDIF LCW -1.5 2.5 0.0 EXT \ + RDS_NDIF RCW -1.5 2.5 0.0 EXT \ + RDS_NDIF VW -1.5 6.0 0.0 DRC \ + RDS_ACTIV VW -1.5 6.0 0.0 ALL + PTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \ + RDS_PDIF LCW -1.5 2.5 0.0 EXT \ + RDS_PDIF RCW -1.5 2.5 0.0 EXT \ + RDS_PDIF VW -1.5 6.0 0.0 DRC \ + RDS_ACTIV VW -1.5 6.0 0.0 ALL + POLY RDS_POLY VW 0.5 0.0 0.0 ALL + POLY2 RDS_POLY2 VW 0.5 0.0 0.0 ALL + ALU1 RDS_ALU1 VW 1.0 0.0 0.0 ALL # LSX DLR 0.5 -> 1.0 + ALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL + ALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL + ALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL + ALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL + ALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL + CALU1 RDS_ALU1 VW 1.0 0.0 0.0 ALL + CALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL + CALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL + CALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL + CALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL + CALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL + TPOLY RDS_TPOLY VW 0.5 0.0 0.0 ALL + TALU1 RDS_TALU1 VW 1.0 0.0 0.0 ALL # SX DLR 0.5 -> 1.0 + TALU2 RDS_TALU2 VW 1.0 0.0 0.0 ALL + TALU3 RDS_TALU3 VW 1.0 0.0 0.0 ALL + TALU4 RDS_TALU4 VW 1.0 0.0 0.0 ALL + TALU5 RDS_TALU5 VW 1.0 0.0 0.0 ALL + TALU6 RDS_TALU6 VW 1.0 0.0 0.0 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_CONNECTOR : +# +# MBK RDS layer +# name name DER DWR +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_CONNECTOR + + POLY RDS_POLY .5 0 + POLY2 RDS_POLY2 .5 0 + ALU1 RDS_ALU1 1.0 0 # LSX DER 0.5 -> 1.0 + ALU2 RDS_ALU2 1.0 0 + ALU3 RDS_ALU3 1.0 0 + ALU4 RDS_ALU4 1.0 0 + ALU5 RDS_ALU5 1.0 0 + ALU6 RDS_ALU6 1.0 0 + CALU1 RDS_ALU1 1.0 0 # LSX DER 0.5 -> 1.0 + CALU2 RDS_ALU2 1.0 0 + CALU3 RDS_ALU3 1.0 0 + CALU4 RDS_ALU4 1.0 0 + CALU5 RDS_ALU5 1.0 0 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_REFERENCE : +# +# MBK ref RDS layer +# name name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_REFERENCE + + REF_REF RDS_REF 1 + REF_CON RDS_VALU1 2 RDS_TVIA1 1 RDS_TALU2 2 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_VIA1 : +# +# MBK via RDS layer 1 RDS layer 2 RDS layer 3 RDS layer 4 +# name name width name width name width name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_VIA + + CONT_BODY_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PTIE 3 ALL + CONT_BODY_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NTIE 3 ALL + CONT_DIF_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NDIF 3 ALL + CONT_DIF_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PDIF 3 ALL + CONT_POLY RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY 2 ALL # LSX POLY=3 -> POLY=2 + CONT_POLY2 RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY2 2 ALL # LSX POLY2=3 -> POLY2=2 + CONT_VIA RDS_ALU1 2 ALL RDS_VIA1 1 ALL RDS_ALU2 2 ALL + CONT_VIA2 RDS_ALU2 2 ALL RDS_VIA2 1 ALL RDS_ALU3 2 ALL + CONT_VIA3 RDS_ALU3 2 ALL RDS_VIA3 1 ALL RDS_ALU4 2 ALL + CONT_VIA4 RDS_ALU4 2 ALL RDS_VIA4 1 ALL RDS_ALU5 2 ALL + CONT_VIA5 RDS_ALU5 2 ALL RDS_VIA5 1 ALL RDS_ALU6 2 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_HOLE : +# +# MBK via RDS Hole +# name name side step mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_HOLE + +CONT_VIA RDS_VIA1 1 4 ALL +CONT_VIA2 RDS_VIA2 1 4 ALL +CONT_VIA3 RDS_VIA3 1 4 ALL +CONT_VIA4 RDS_VIA4 1 4 ALL # should be more than 4 +CONT_VIA5 RDS_VIA5 1 4 ALL # should be more than 4 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_METAL : +# +# MBK via RDS layer 1 ... +# name name delta-width overlap mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_METAL + +CONT_VIA RDS_ALU1 0.0 0.5 ALL RDS_ALU2 0.0 0.5 ALL +CONT_VIA2 RDS_ALU2 0.0 0.5 ALL RDS_ALU3 0.0 0.5 ALL +CONT_VIA3 RDS_ALU3 0.0 0.5 ALL RDS_ALU4 0.0 0.5 ALL +CONT_VIA4 RDS_ALU4 0.0 0.5 ALL RDS_ALU5 0.0 0.5 ALL +CONT_VIA5 RDS_ALU5 0.0 0.5 ALL RDS_ALU6 0.0 0.5 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_TURNVIA : +# +# MBK via RDS layer 1 ... +# name name DWR MODE +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_TURNVIA + +CONT_TURN1 RDS_ALU1 0 ALL +CONT_TURN2 RDS_ALU2 0 ALL +CONT_TURN3 RDS_ALU3 0 ALL +CONT_TURN4 RDS_ALU4 0 ALL +CONT_TURN5 RDS_ALU5 0 ALL +CONT_TURN6 RDS_ALU6 0 ALL + +END + + +##------------------------------------------------------------------- +# TABLE LYNX_GRAPH : +# +# RDS layer Rds layer 1 Rds layer 2 ... +# name name name ... +##------------------------------------------------------------------- + +TABLE LYNX_GRAPH + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# RDS_NWELL RDS_NTIE RDS_NWELL +# RDS_PWELL RDS_PTIE RDS_PWELL +# RDS_NDIF RDS_CONT RDS_NDIF +# RDS_PDIF RDS_CONT RDS_PDIF +# RDS_NTIE RDS_CONT RDS_NTIE RDS_NWELL +# RDS_PTIE RDS_CONT RDS_PTIE RDS_PWELL + + RDS_NDIF RDS_CONT RDS_NDIF + RDS_PDIF RDS_CONT RDS_PDIF + RDS_NTIE RDS_CONT RDS_NTIE + RDS_PTIE RDS_CONT RDS_PTIE + + RDS_POLY RDS_CONT RDS_POLY + RDS_POLY2 RDS_CONT RDS_POLY2 + RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT + RDS_ALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1 + RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 + RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 + RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 + RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 + RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 + RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 + RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2 + RDS_ALU3 RDS_VIA2 RDS_VIA3 RDS_ALU3 + RDS_ALU4 RDS_VIA3 RDS_VIA4 RDS_ALU4 + RDS_ALU5 RDS_VIA4 RDS_VIA5 RDS_ALU5 + RDS_ALU6 RDS_VIA5 RDS_ALU6 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_CAPA : +# +# RDS layer Surface capacitance Perimetric capacitance +# name piF / Micron^2 piF / Micron +##------------------------------------------------------------------- + +TABLE LYNX_CAPA + + RDS_POLY 1.00e-04 1.00e-04 + RDS_POLY2 1.00e-04 1.00e-04 + RDS_ALU1 0.50e-04 0.90e-04 + RDS_ALU2 0.25e-04 0.95e-04 + RDS_ALU3 0.25e-04 0.95e-04 + RDS_ALU4 0.25e-04 0.95e-04 + RDS_ALU5 0.25e-04 0.95e-04 + RDS_ALU6 0.25e-04 0.95e-04 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_RESISTOR : +# +# RDS layer Surface resistor +# name Ohm / Micron^2 +##------------------------------------------------------------------- + +TABLE LYNX_RESISTOR + + RDS_POLY 50.0 + RDS_POLY2 50.0 + RDS_ALU1 12.0 # LSX .1 -> 12 + RDS_ALU2 0.05 + RDS_ALU3 0.05 + RDS_ALU4 0.05 + RDS_ALU5 0.05 + RDS_ALU6 0.05 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_TRANSISTOR : +# +# MBK layer Transistor Type MBK via +# name name name +##------------------------------------------------------------------- + +TABLE LYNX_TRANSISTOR + + NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL + PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL + +END + +##------------------------------------------------------------------- +# TABLE LYNX_DIFFUSION : +# +# RDS layer RDS layer +# name name +##------------------------------------------------------------------- + +TABLE LYNX_DIFFUSION +END + +##------------------------------------------------------------------- +# TABLE LYNX_BULK_IMPLICIT : +# +# RDS layer Bulk type +# name EXPLICIT/IMPLICIT +##------------------------------------------------------------------- + +TABLE LYNX_BULK_IMPLICIT + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# NWELL EXPLICIT +# PWELL IMPLICIT + +END + + + +##------------------------------------------------------------------- +# TABLE S2R_OVERSIZE_DENOTCH : +##------------------------------------------------------------------- + +TABLE S2R_OVERSIZE_DENOTCH +END + +##------------------------------------------------------------------- +# TABLE S2R_BLOC_RING_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_BLOC_RING_WIDTH +END + +##------------------------------------------------------------------- +# TABLE S2R_MINIMUM_LAYER_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_MINIMUM_LAYER_WIDTH + + RDS_NWELL 4 + RDS_NDIF 3 # LSX 2 -> 3 + RDS_PDIF 3 # LSX 2 -> 3 + RDS_NTIE 3 # LSX 2 -> 3 + RDS_PTIE 3 # LSX 2 -> 3 + RDS_POLY 1 + RDS_POLY2 1 + RDS_TPOLY 1 + RDS_CONT 1 + RDS_ALU1 2 # LSX 1 -> 2 + RDS_TALU1 2 # LSX 1 -> 2 + RDS_VIA1 1 + RDS_ALU2 2 + RDS_TALU2 2 + RDS_VIA2 1 + RDS_ALU3 2 + RDS_TALU3 2 + RDS_VIA3 1 + RDS_ALU4 2 + RDS_TALU4 2 + RDS_VIA4 1 + RDS_ALU5 2 + RDS_TALU5 2 + RDS_VIA5 1 + RDS_ALU6 2 + RDS_TALU6 2 + +END + +##------------------------------------------------------------------- +# TABLE MBK_WIRESETTING : +##------------------------------------------------------------------- +# +# This table is used by ocp, nero & ring. It supplies *symbolic* +# information about the routing grid, the cell gauge and the power +# wires. + + +TABLE MBK_WIRESETTING + + X_GRID 5 + Y_GRID 5 + Y_SLICE 50 + WIDTH_VDD 4 # LSX 6 -> 4 + WIDTH_VSS 4 # LSX 6 -> 4 + TRACK_WIDTH_ALU8 0 + TRACK_WIDTH_ALU7 2 + TRACK_WIDTH_ALU6 2 + TRACK_WIDTH_ALU5 2 + TRACK_WIDTH_ALU4 2 + TRACK_WIDTH_ALU3 2 + TRACK_WIDTH_ALU2 2 + TRACK_WIDTH_ALU1 2 + TRACK_SPACING_ALU8 0 + TRACK_SPACING_ALU7 8 + TRACK_SPACING_ALU6 8 + TRACK_SPACING_ALU5 3 + TRACK_SPACING_ALU4 3 + TRACK_SPACING_ALU3 3 + TRACK_SPACING_ALU2 3 + TRACK_SPACING_ALU1 3 + +END + + +##------------------------------------------------------------------- +# TABLE CIF_LAYER : +##------------------------------------------------------------------- + +TABLE CIF_LAYER + + RDS_NWELL LNWELL + RDS_NDIF LNDIF + RDS_PDIF LPDIF + RDS_NTIE LNTIE + RDS_PTIE LPTIE + RDS_POLY LPOLY + RDS_POLY2 LPOLY2 + RDS_TPOLY LTPOLY + RDS_CONT LCONT + RDS_ALU1 LALU1 + RDS_VALU1 LVALU1 + RDS_TALU1 LTALU1 + RDS_VIA1 LVIA + RDS_TVIA1 LTVIA1 + RDS_ALU2 LALU2 + RDS_TALU2 LTALU2 + RDS_VIA2 LVIA2 + RDS_ALU3 LALU3 + RDS_TALU3 LTALU3 + RDS_VIA3 LVIA3 + RDS_ALU4 LALU4 + RDS_TALU4 LTALU4 + RDS_VIA4 LVIA4 + RDS_ALU5 LALU5 + RDS_TALU5 LTALU5 + RDS_VIA5 LVIA5 + RDS_ALU6 LALU6 + RDS_TALU6 LTALU6 + RDS_REF LREF + +END + +##------------------------------------------------------------------- +# TABLE GDS_LAYER : +##------------------------------------------------------------------- + +TABLE GDS_LAYER + + RDS_NWELL 1 + RDS_NDIF 3 + RDS_PDIF 4 + RDS_NTIE 5 + RDS_PTIE 6 + RDS_POLY 7 + RDS_POLY2 8 + RDS_TPOLY 9 + RDS_CONT 10 + RDS_ALU1 11 11 + RDS_VALU1 12 + RDS_TALU1 13 + RDS_VIA1 14 + RDS_TVIA1 15 + RDS_ALU2 16 16 + RDS_TALU2 17 + RDS_VIA2 18 + RDS_ALU3 19 19 + RDS_TALU3 20 + RDS_VIA3 21 + RDS_ALU4 22 22 + RDS_TALU4 23 + RDS_VIA4 25 + RDS_ALU5 26 26 + RDS_TALU5 27 + RDS_VIA5 28 + RDS_ALU6 29 29 + RDS_TALU6 30 + RDS_REF 24 + +END + +##------------------------------------------------------------------- +# TABLE S2R_POST_TREAT : +##------------------------------------------------------------------- + +TABLE S2R_POST_TREAT + +END +DRC_RULES + +layer RDS_NWELL 4.; +layer RDS_NTIE 3.; # LSX 2 -> 3 +layer RDS_PTIE 3.; # LSX 2 -> 3 +layer RDS_NDIF 3.; # LSX 2 -> 3 +layer RDS_PDIF 3.; # LSX 2 -> 3 +layer RDS_ACTIV 2.; +layer RDS_CONT 1.; +layer RDS_VIA1 1.; +layer RDS_VIA2 1.; +layer RDS_VIA3 1.; +layer RDS_VIA4 1.; +layer RDS_VIA5 1.; +layer RDS_POLY 1.; +layer RDS_POLY2 1.; +layer RDS_ALU1 2.; # LSX 1 -> 2 +layer RDS_ALU2 2.; +layer RDS_ALU3 2.; +layer RDS_ALU4 2.; +layer RDS_ALU5 2.; +layer RDS_ALU6 2.; +layer RDS_USER0 1.; +layer RDS_USER1 1.; +layer RDS_USER2 1.; + +regles + +# Note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# There is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# There is no rule to check NTIE and PDIF are included in NWELL +# since this is necessarily true +#----------------------------------------------------------- + +# Check the NWELL shapes +#----------------------- +caracterise RDS_NWELL ( + regle 1 : largeur >= 4. ; + regle 2 : longueur_inter min 4. ; + regle 3 : notch >= 12. ; +); +relation RDS_NWELL , RDS_NWELL ( + regle 4 : distance axiale min 12. ; +); + +# Check RDS_PTIE is really excluded outside NWELL +#------------------------------------------------ +relation RDS_PTIE , RDS_NWELL ( + regle 5 : distance axiale >= 7.5; + regle 6 : enveloppe longueur_inter < 0. ; + regle 7 : marge longueur_inter < 0. ; + regle 8 : croix longueur_inter < 0. ; + regle 9 : intersection longueur_inter < 0. ; + regle 10 : extension longueur_inter < 0. ; + regle 11 : inclusion longueur_inter < 0. ; +); + +# Check RDS_NDIF is really excluded outside NWELL +#------------------------------------------------ +relation RDS_NDIF , RDS_NWELL ( + regle 12 : distance axiale >= 7.5; + regle 13 : enveloppe longueur_inter < 0. ; + regle 14 : marge longueur_inter < 0. ; + regle 15 : croix longueur_inter < 0. ; + regle 16 : intersection longueur_inter < 0. ; + regle 17 : extension longueur_inter < 0. ; + regle 18 : inclusion longueur_inter < 0. ; +); + +# Check the RDS_PDIF shapes +#-------------------------- +caracterise RDS_PDIF ( + regle 19 : largeur >= 3. ; # LSX 2 -> 3 + regle 20 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 21 : notch >= 3. ; +); +relation RDS_PDIF , RDS_PDIF ( + regle 22 : distance axiale min 3. ; +); + +# Check the RDS_NDIF shapes +#-------------------------- +caracterise RDS_NDIF ( + regle 23 : largeur >= 3. ; # LSX 2 -> 3 + regle 24 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 25 : notch >= 3. ; +); +relation RDS_NDIF , RDS_NDIF ( + regle 26 : distance axiale min 3. ; +); + +# Check the RDS_PTIE shapes +#-------------------------- +caracterise RDS_PTIE ( + regle 27 : largeur >= 3. ; # LSX 2 -> 3 + regle 28 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 29 : notch >= 3. ; +); +relation RDS_PTIE , RDS_PTIE ( + regle 30 : distance axiale min 3. ; +); + +# Check the RDS_NTIE shapes +#-------------------------- +caracterise RDS_NTIE ( + regle 31 : largeur >= 3. ; # LSX 2 -> 3 + regle 32 : longueur_inter min 3. ; # LSX 2 -> 3 + regle 33 : notch >= 3. ; +); +relation RDS_NTIE , RDS_NTIE ( + regle 34 : distance axiale min 3. ; +); + +define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF; +define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF; + +# Check the ANY_N_DIF ANY_P_DIFF exclusion +#-------------------------------------- +relation ANY_N_DIF , ANY_P_DIF ( + regle 35 : distance axiale >= 3. ; + regle 36 : enveloppe longueur_inter < 0. ; + regle 37 : marge longueur_inter < 0. ; + regle 38 : croix longueur_inter < 0. ; + regle 39 : intersection longueur_inter < 0. ; + regle 40 : extension longueur_inter < 0. ; + regle 41 : inclusion longueur_inter < 0. ; +); + +undefine ANY_P_DIF; +undefine ANY_N_DIF; + +define RDS_NDIF , RDS_PDIF union -> NP_DIF; + +# Check RDS_POLY related to NP_DIF +#--------------------------------- +relation RDS_POLY , NP_DIF ( + regle 42 : distance axiale >= 1. ; + regle 43 : intersection longueur_inter < 0. ; +); + +define NP_DIF , RDS_POLY intersection -> CHANNEL; + +# Check the RDS_POLY shapes +#-------------------------- +caracterise RDS_POLY ( + regle 44 : largeur >= 1. ; + regle 45 : longueur_inter min 1. ; + regle 46 : notch >= 2.5 ; # LSX 2 -> 2.5 +); +relation RDS_POLY , RDS_POLY ( + regle 47 : distance axiale min 2.5; # LSX 2 -> 2.5 +); + +define NP_DIF , RDS_CONT intersection -> CONT_DIFF; +# Check the CHANNEL shapes +#-------------------------- +caracterise CHANNEL ( + regle 48 : notch >= 3. ; +); +relation CHANNEL , CHANNEL ( + regle 49 : distance axiale min 3.; +); + +undefine CHANNEL; + +# Check RDS_POLY is distant from ACTIV ZONE of TRANSISTOR +#-------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + regle 79 : distance axiale >= 1. ; +); + +relation RDS_POLY , CONT_DIFF ( + regle 50 : distance axiale >= 2. ; +); + +undefine CONT_DIFF; +undefine NP_DIF; + + +# Check RDS_ALU1 shapes +#---------------------- +caracterise RDS_ALU1 ( + regle 51 : largeur >= 2. ; # LSX 1 -> 2 + regle 52 : longueur_inter min 2. ; # LSX 1 -> 2 + regle 53 : notch >= 3. ; +); +relation RDS_ALU1 , RDS_ALU1 ( + regle 54 : distance axiale min 3. ; +); + +# Check RDS_ALU2 shapes +#---------------------- +caracterise RDS_ALU2 ( + regle 55 : largeur >= 2. ; + regle 56 : longueur_inter min 2. ; + regle 57 : notch >= 3. ; +); +relation RDS_ALU2 , RDS_ALU2 ( + regle 58 : distance axiale min 3. ; +); + +# Check RDS_ALU3 shapes +#---------------------- +caracterise RDS_ALU3 ( + regle 59 : largeur >= 2. ; + regle 60 : longueur_inter min 2. ; + regle 61 : notch >= 3. ; +); +relation RDS_ALU3 , RDS_ALU3 ( + regle 62 : distance axiale min 3. ; +); + +# Check RDS_ALU4 shapes +#---------------------- +caracterise RDS_ALU4 ( + regle 63 : largeur >= 2. ; + regle 64 : longueur_inter min 2. ; + regle 65 : notch >= 3. ; +); +relation RDS_ALU4 , RDS_ALU4 ( + regle 66 : distance axiale min 3. ; +); + +# Check RDS_ALU5 shapes +#---------------------- +caracterise RDS_ALU5 ( + regle 80 : largeur >= 2. ; + regle 81 : longueur_inter min 2. ; + regle 82 : notch >= 3. ; +); +relation RDS_ALU5 , RDS_ALU5 ( + regle 83 : distance axiale min 3. ; +); + +# Check RDS_ALU6 shapes +#---------------------- +caracterise RDS_ALU6 ( + regle 84 : largeur >= 2. ; + regle 85 : longueur_inter min 2. ; + regle 86 : notch >= 3. ; +); +relation RDS_ALU6 , RDS_ALU6 ( + regle 87 : distance axiale min 3. ; +); + +# Check ANY_VIA layers, stacking are free +#---------------------------------------- +relation RDS_CONT , RDS_CONT ( + regle 67 : distance axiale >= 3. ; +); +relation RDS_VIA , RDS_VIA ( + regle 68 : distance axiale >= 4. ; +); +relation RDS_VIA2 , RDS_VIA2 ( + regle 69 : distance axiale >= 4. ; +); +relation RDS_VIA3 , RDS_VIA3 ( + regle 70 : distance axiale >= 4. ; +); +relation RDS_VIA4 , RDS_VIA4 ( + regle 88 : distance axiale >= 4. ; +); +relation RDS_VIA5 , RDS_VIA5 ( + regle 89 : distance axiale >= 4. ; +); +caracterise RDS_CONT ( + regle 71 : largeur >= 1. ; + regle 72 : longueur <= 1. ; +); +caracterise RDS_VIA ( + regle 73 : largeur >= 1. ; + regle 74 : longueur <= 1. ; +); +caracterise RDS_VIA2 ( + regle 75 : largeur >= 1. ; + regle 76 : longueur <= 1. ; +); +caracterise RDS_VIA3 ( + regle 77 : largeur >= 1. ; + regle 78 : longueur <= 1. ; +); +caracterise RDS_VIA4 ( + regle 90 : largeur >= 1. ; + regle 91 : longueur <= 1. ; +); +caracterise RDS_VIA5 ( + regle 92 : largeur >= 1. ; + regle 93 : longueur <= 1. ; +); + +# Check the POLY2 shapes +#----------------------- +caracterise RDS_POLY2 ( + regle 94 : largeur >= 1. ; + regle 95 : longueur_inter min 1. ; + regle 96 : notch >= 5. ; +); +relation RDS_POLY2 , RDS_POLY2 ( + regle 97 : distance axiale min 5. ; +); + +# Check RDS_POLY2 is really included inside RDS_POLY1 +#---------------------------------------------------- +relation RDS_POLY , RDS_POLY2 ( + regle 98 : distance axiale < 0.; + regle 99 : enveloppe inferieure min 5. ; + regle 100 : marge longueur_inter < 0. ; + regle 101 : croix longueur_inter < 0. ; + regle 102 : intersection longueur_inter < 0. ; + regle 103 : extension longueur_inter < 0. ; + regle 104 : inclusion longueur_inter < 0. ; +); + + +fin regles +DRC_COMMENT +1 (RDS_NWELL) minimum width 4. +2 (RDS_NWELL) minimum width 4. +3 (RDS_NWELL) Manhatan distance min 12. +4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12. +5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5 +6 (RDS_PTIE,RDS_NWELL) must never been in contact +7 (RDS_PTIE,RDS_NWELL) must never been in contact +8 (RDS_PTIE,RDS_NWELL) must never been in contact +9 (RDS_PTIE,RDS_NWELL) must never been in contact +10 (RDS_PTIE,RDS_NWELL) must never been in contact +11 (RDS_PTIE,RDS_NWELL) must never been in contact +12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5 +13 (RDS_NDIF,RDS_NWELL) must never been in contact +14 (RDS_NDIF,RDS_NWELL) must never been in contact +15 (RDS_NDIF,RDS_NWELL) must never been in contact +16 (RDS_NDIF,RDS_NWELL) must never been in contact +17 (RDS_NDIF,RDS_NWELL) must never been in contact +18 (RDS_NDIF,RDS_NWELL) must never been in contact +19 (RDS_PDIF) minimum width 3. # LSX 2 -> 3 +20 (RDS_PDIF) minimum width 3. # LSX 2 -> 3 +21 (RDS_PDIF) Manhatan distance min 3. +22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3. +23 (RDS_NDIF) minimum width 3. # LSX 2 -> 3 +24 (RDS_NDIF) minimum width 3. # LSX 2 -> 3 +25 (RDS_NDIF) Manhatan distance min 3. +26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3. +27 (RDS_PTIE) minimum width 3. # LSX 2 -> 3 +28 (RDS_PTIE) minimum width 3. # LSX 2 -> 3 +29 (RDS_PTIE) Manhatan distance min 3. +30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3. +31 (RDS_NTIE) minimum width 3. # LSX 2 -> 3 +32 (RDS_NTIE) minimum width 3. # LSX 2 -> 3 +33 (RDS_NTIE) Manhatan distance min 3. +34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3. +35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3. +36 (ANY_N_DIF,ANY_P_DIF) must never been in contact +37 (ANY_N_DIF,ANY_P_DIF) must never been in contact +38 (ANY_N_DIF,ANY_P_DIF) must never been in contact +39 (ANY_N_DIF,ANY_P_DIF) must never been in contact +40 (ANY_N_DIF,ANY_P_DIF) must never been in contact +41 (ANY_N_DIF,ANY_P_DIF) must never been in contact +42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1. +43 (RDS_POLY,NP_DIF) bad intersection +44 (RDS_POLY) minimum width 1. +45 (RDS_POLY) minimum width 1. +46 (RDS_POLY) Manhatan distance min 2. +47 (RDS_POLY,RDS_POLY) Manhatan distance min 2. +48 (CHANNEL) Manhatan distance min 3. +49 (CHANNEL,CHANNEL) Manhatan distance min 3. +50 (RDS_POLY,CONT_DIFF) Manhatan distance min 2. +51 (RDS_ALU1) minimum width 2. # LSX 1 -> 2 +52 (RDS_ALU1) minimum width 2. # LSX 1 -> 2 +53 (RDS_ALU1) Manhatan distance min 3. +54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 3. +55 (RDS_ALU2) minimum width 2. +56 (RDS_ALU2) minimum width 2. +57 (RDS_ALU2) Manhatan distance min 3. +58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 3. +59 (RDS_ALU3) minimum width 2. +60 (RDS_ALU3) minimum width 2. +61 (RDS_ALU3) Manhatan distance min 3. +62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3. +63 (RDS_ALU4) minimum width 2. +64 (RDS_ALU4) minimum width 2. +65 (RDS_ALU4) Manhatan distance min 3. +66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3. +67 (RDS_CONT,RDS_CONT) Manhatan distance min 3. +68 (RDS_VIA,RDS_VIA) Manhatan distance min 4. +69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 4. +70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 4. +71 (RDS_CONT) minimum width 1. +72 (RDS_CONT) maximum length 1. +73 (RDS_VIA) minimum width 1. +74 (RDS_VIA) maximum length 1. +75 (RDS_VIA2) minimum width 1. +76 (RDS_VIA2) maximum length 1. +77 (RDS_VIA3) minimum width 1. +78 (RDS_VIA3) maximum length 1. +79 (RDS_POLY,RDS_ACTIV) Manhatan distance min 1. +80 (RDS_ALU5) minimum width 2. +81 (RDS_ALU5) minimum width 2. +82 (RDS_ALU5) Manhatan distance min 4. +83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 4. +84 (RDS_ALU6) minimum width 2. +85 (RDS_ALU6) minimum width 2. +86 (RDS_ALU6) Manhatan distance min 4. +87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 4. +88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 4. +89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 4. +90 (RDS_VIA4) minimum width 1. +91 (RDS_VIA4) maximum length 1. +92 (RDS_VIA5) minimum width 1. +93 (RDS_VIA5) maximum length 1. +94 (RDS_POLY2) minimum width 1. +95 (RDS_POLY2) minimum width 1. +96 (RDS_POLY2) Manhatan distance min 5. +97 (RDS_POLY2,POLY2) Manhatan distance min 5. +98 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +99 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +100 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +101 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +102 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +103 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +104 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/techno.py b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/techno.py new file mode 100644 index 000000000..c12718518 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/techno.py @@ -0,0 +1,663 @@ + +from coriolis import CRL, Hurricane, Viewer, Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, BasicLayer, \ + RegularLayer, Cell, Net, Horizontal, Vertical, Rectilinear, \ + Box, Point, NetExternalComponents +from coriolis.technos.common.colors import toRGB +from coriolis.technos.common.patterns import toHexa +from coriolis.helpers import u +from coriolis.helpers.technology import createBL, createVia +from coriolis.helpers.overlay import CfgCache +from coriolis.helpers.analogtechno import Length, Area, Unit, Asymmetric, loadAnalogTechno, addDevice +from coriolis.designflow.task import ShellEnv + + +__all__ = [ "setup" ] + + +""" +Coriolis Design Technological Rules (DTR) for SkyWater 130nm CMOS General Purpose +================================================================================= + +:Version: rev.LIP6-1 +:Date: December 21, 2022 +:Date: February 2, 2023 +:Date: April 20, 2023 +:Authors: Marie-Minerve Louerat + +Reference documents: + https://skywater-pdk.readthedocs.io/en/main/rules/masks.html + https://skywater-pdk.readthedosc.io/en/main/rules/periphery.html#x + +Beware of the existence of li1 local interconnect using licon to connect to +difftap or to poly and mcon ton connect to metal1 + +Beware that some rules are context dependent (via spacing at end of line or at +one side, wide metal3) + +Beware different description exist of MIM capacitors +here met2, capm, met3 and via2 connects met2/capm to met3 + +===================== ======= ========== ==================================== +SkyWater130 mask Acronym Layer name Coriolis original +purpose for rule layer name +===================== ======= ========== ==================================== +N-Well NWM nwm nwell +Low Vt Nch LVTNM lvtn +active diffusion difftap active +Poly 1 P1M poly poly +P+ Implant PSDM psdm pImplant +N+ Implant NSDM nsdm nImplant +Local Intr Cont. 1 LICM1 licon cut0 contact between difftap and li1, + poly and li1 +Local Intrcnct 1 LI1M li metal metal between poly and metal1 + for local interconnect +Contact CTM1 mcon cut1 contact between li1 and metal1 +Metal 1 MM1 m1 metal1 +Via VIM via cut2 +Metal 2 MM2 m2 metal2 +Via 2-PLM VIM2 via2 cut3 +Metal 3-PLM MM3 m3 metal3 +Via 2-PLM VIM3 via3 cut4 +Metal 4 MM4 m4 metal4 +Via 4 VIM4 via4 cut5 +Metal 5 MM5 m5 metal5 + +capm CAPM capm metcap +Metal 2 MM2 bottom_plate metbot +===================== ======= ============ ==================================== + +""" + + +analogTechnologyTable = \ + ( ('Header', 'Sky130', DbU.UnitPowerMicro, 'rev.LIP6-1') + # ------------------------------------------------------------------------------------ + # ( Rule name , [Layer1] , [Layer2] , Value , Rule flags , Reference ) + , ('physicalGrid' , 0.005 , Length , 'GSF') + , ('transistorMinL' , 0.15 , Length , 'poly.1 and device details') + #, ('transistorMinL' , 0.38 , Length , 'lvtn.1a') + , ('transistorMaxL' , 38 , Length , 'rule0002') + , ('transistorMinW' , 0.42 , Length , 'difftap.2') + #, ('transistorMinW' , 0.36 , Length , 'difftap.2b') + , ('transistorMaxW' , 4000 , Length , 'rule0004') + + # N-WELL (nwm) + , ('minWidth' , 'nwm' , 0.84 , Length , 'nwell.1') + , ('minSpacing' , 'nwm' , 1.27 , Length , 'nwell.2a') + , ('minArea' , 'nwm' , 0 , Area , 'N/A') + + # LVTN (lvtn) + , ('minWidth' , 'lvtn' , 0.38 , Length , 'lvtn.1a') + , ('minSpacing' , 'lvtn' , 0.38 , Length , 'lvtn.2') + , ('minArea' , 'lvtn' , 0.265 , Area , 'lvtn.13') + , ('minEnclosure' , 'nwm' , 'lvtn' , 0.38 , Length|Asymmetric, 'lvtn.10') + + # DIFF (difftap) + , ('minWidth' , 'difftap' , 0.15 , Length , 'difftap.1') + , ('minSpacing' , 'difftap' , 0.27 , Length , 'difftap.3') + , ('minArea' , 'difftap' , 0 , Area , 'N/A') + , ('minEnclosure' , 'nwm' , 'difftap' , 0.18 , Length|Asymmetric, 'difftap.10') + + # Poly1 (poly) + , ('minWidth' , 'poly' , 0.15 , Length , 'poly.1a') + , ('minSpacing' , 'poly' , 0.21 , Length , 'poly.2') + , ('minGateSpacing' , 'poly' , 0.21 , Length , 'poly.2') + , ('minArea' , 'poly' , 0 , Area , 'N/A') + , ('minSpacing' , 'poly' , 'difftap' , 0.075 , Length , 'poly.4') + , ('minExtension' , 'poly' , 'difftap' , 0.130 , Length|Asymmetric, 'poly.8') + , ('minGateExtension' , 'difftap' , 'poly' , 0.25 , Length|Asymmetric, 'poly.7') + , ('minExtension' , 'difftap' , 'poly' , 0.25 , Length|Asymmetric, 'poly.7') + + # 4.1.6 PPLUS (psdm) + , ('minWidth' , 'psdm' , 0.38 , Length , 'psd.1') + , ('minSpacing' , 'psdm' , 0.38 , Length , 'psd.2') + , ('minArea' , 'psdm' , 0.255 , Area , 'psd.10b') + , ('minSpacing' , 'psdm' , 'difftap' , 0.130 , Length , 'psd.7') + , ('minGateExtension' , 'psdm' , 'poly' , 0.00 , Length|Asymmetric, 'N/A') + , ('minOverlap' , 'psdm' , 'difftap' , 0.00 , Length , 'N/A') + , ('minEnclosure' , 'psdm' , 'difftap' , 0.125 , Length|Asymmetric, 'psd.5a') + , ('minStrapEnclosure' , 'psdm' , 'difftap' , 0.125 , Length , 'psd.5b') + , ('minSpacing' , 'nsdm' , 'psdm' , 0.00 , Length , 'N/A') + , ('minEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minLengthEnclosure', 'psdm' , 'difftap' , 0 , Length|Asymmetric, 'N/A') + , ('minWidthEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'psdm' , 'difftap' , 0.125 , Length|Asymmetric, 'dup. psd.5a') + , ('minStrapEnclosure' , 'psdm' , 0.125 , Length , 'dup. psd.5b') + + # NPLUS (nsdm) + , ('minWidth' , 'nsdm' , 0.38 , Length , 'nsd.1') + , ('minSpacing' , 'nsdm' , 0.38 , Length , 'nsd.2') + , ('minArea' , 'nsdm' , 0.265 , Area , 'nsd.10a') + , ('minSpacing' , 'nsdm' , 'difftap' , 0.130 , Length , 'nsd.7') + , ('minGateExtension' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minOverlap' , 'nsdm' , 'difftap' , 0 , Length , 'N/A') + , ('minEnclosure' , 'nsdm' , 'difftap' , 0.125 , Length|Asymmetric, 'nsd.5a') + , ('minStrapEnclosure' , 'nsdm' , 'difftap' , 0.125 , Length , 'nsd.5b') + , ('minEnclosure' , 'nsdm' , 'nwm' , 0 , Length|Asymmetric, 'N/A') + , ('minEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minLengthEnclosure', 'nsdm' , 'difftap' , 0 , Length|Asymmetric, 'N/A') + , ('minWidthEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minGateEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'nsdm' , 'difftap' , 0.125 , Length|Asymmetric, 'dup. nsd.5a') + , ('minStrapEnclosure' , 'nsdm' , 0.215 , Length , 'dup. nsd.5b') + + # LICM1 (licon) + , ('minWidth' , 'licon' , 0.17 , Length , 'licon.1') + , ('minSpacing' , 'licon' , 0.17 , Length , 'licon.2') + , ('minGateSpacing' , 'licon' , 'poly' , 0.25 , Length|Asymmetric, 'licon.10') + , ('minSpacing' , 'licon' , 'poly' , 0.25 , Length|Asymmetric, 'licon.10') + , ('minSpacing' , 'licon' , 'difftap' , 0.19 , Length , 'licon.14') + #, ('minSpacing' , 'licon' , 'difftap' , 0.06 , Length , 'licon.5b') + , ('minEnclosure' , 'difftap' , 'licon' , 0.04 , Length|Asymmetric, 'licon.5a and licon.7 : 0.12 isolated tap') + , ('minEnclosure' , 'poly' , 'licon' , 0.05 , Length|Asymmetric, 'licon.8 and licon.8a : 0.08') + , ('minEnclosure' , 'psdm' , 'licon' , 0 , Length|Asymmetric, 'N/A') + , ('minEnclosure' , 'nsdm' , 'licon' , 0 , Length|Asymmetric, 'N/A') + , ('minGateEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'poly' , 'licon' , 0.05 , Length|Asymmetric, 'dup. licon.8 and licon.8a') + , ('minExtension' , 'psdm' , 'licon' , 0.25 , Length|Asymmetric, 'dup.') + , ('minExtension' , 'nsdm' , 'licon' , 0.25 , Length|Asymmetric, 'dup.') + + # LI1M (li) + , ('minWidth' , 'li' , 0.17 , Length , 'li.1') + , ('minSpacing' , 'li' , 0.17 , Length , 'li.3') + , ('minArea' , 'li' , 0.0561, Area , 'li.6') + , ('minEnclosure' , 'li' , 'licon' , 0.08 , Length|Asymmetric, 'li.5') + , ('minEnclosure' , 'li' , 'mcon' , 0.00 , Length|Asymmetric, 'ct.4') + + # CTM1 (mcon) + , ('minWidth' , 'mcon' , 0.17 , Length , 'ct.1') + , ('minSpacing' , 'mcon' , 0.19 , Length , 'ct.2') + + + # MM1 (m1) + , ('minWidth' , 'm1' , 0.14 , Length , 'm1.1') + , ('minSpacing' , 'm1' , 0.14 , Length , 'm1.2') + , ('minArea' , 'm1' , 0.083 , Area , 'm1.6') + , ('minEnclosure' , 'm1' , 'mcon' , 0.03 , Length|Asymmetric, 'm1.4 and m1.5 : 0.06 one side') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm1' , 'mcon' , 0.03 , Length|Asymmetric, 'm1.4 and m1.5') + + # VIM (via) + , ('minWidth' , 'via' , 0.15 , Length , 'via.1a') + , ('minSpacing' , 'via' , 0.17 , Length , 'via.2') + , ('minEnclosure' , 'm1' , 'via' , 0.55 , Length|Asymmetric, 'via.4a and via.5a : 0.085 on one side') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'm1' , 'via' , 0.55 , Length|Asymmetric, 'dup. via.a4 and via.5a : 0.085 on one side') + + # MM2 (m2) + , ('minWidth' , 'm2' , 0.14 , Length , 'm2.1') + , ('minSpacing' , 'm2' , 0.14 , Length , 'm2.2') + , ('minArea' , 'm2' , 0.0676, Area , 'm2.6') + , ('minEnclosure' , 'm2' , 'via' , 0.055 , Length|Asymmetric, 'm2.4 and m2.5 : 0.085 end of line') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm2' , 'via' , 0.055 , Length|Asymmetric, 'dup. m2.4 and m2.5 : 0.085 end of line') + + # VIM2 (via2) + , ('minWidth' , 'via2' , 0.20 , Length , 'via2.1a') + , ('minSpacing' , 'via2' , 0.20 , Length , 'via2.2') + , ('minEnclosure' , 'm2' , 'via2' , 0.04 , Length|Asymmetric, 'via2.4 via2.5 : 0.085 and via2.14') + + # MM3 (m3) + , ('minWidth' , 'm3' , 0.30 , Length , 'm3.1') + , ('minSpacing' , 'm3' , 0.30 , Length , 'm3.2') + , ('minSpacing' , 'widem3' , 0.40 , Length , 'm3.3d') + , ('minArea' , 'm3' , 0.24 , Area , 'm3.6' ) + , ('minEnclosure' , 'm3' , 'via2' , 0.065 , Length|Asymmetric, 'm3.4') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm3' , 'via2' , 0.065 , Length|Asymmetric, 'dup. m3.4') + + # VIM3 (via3) + , ('minWidth' , 'via3' , 0.20 , Length , 'via3.1') + , ('minSpacing' , 'via3' , 0.20 , Length , 'via3.2') + , ('minEnclosure' , 'm3' , 'via3' , 0.060 , Length|Asymmetric, 'via3.4 and via3.5 end of line : 0.090') + + # MM4 (m4) + , ('minWidth' , 'm4' , 0.30 , Length , 'm4.1') + , ('minSpacing' , 'm4' , 0.30 , Length , 'm4.2') + , ('minArea' , 'm4' , 0.24 , Area , 'm4.4a') + , ('minEnclosure' , 'm4' , 'via3' , 0.065 , Length|Asymmetric, 'm4.3') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm4' , 'via3' , 0.065 , Length|Asymmetric, 'dup. m4.3 ') + + # VIM4 (via4) + , ('minWidth' , 'via4' , 0.80 , Length , 'via4.1') + , ('minSpacing' , 'via4' , 0.80 , Length , 'via4.2') + , ('minEnclosure' , 'm4' , 'via4' , 0.19 , Length|Asymmetric, 'via4.4') + + # MM5 (m5) + , ('minWidth' , 'm5' , 1.6 , Length , 'm5.1') + , ('minSpacing' , 'm5' , 1.6 , Length , 'm5.2') + , ('minArea' , 'm5' , 4.00 , Area , 'm5.4') + , ('minEnclosure' , 'm5' , 'via4' , 0.310 , Length|Asymmetric, 'm5.3') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm5' , 'via4' , 0.310 , Length|Asymmetric, 'dup. m5.3 ') + + + #capm + #, ('minWidth' , 'metcap' , 1.0 , Length , 'capm.1') + #, ('minWidth' , 'metcapdum' , 0.5 , Length , '') + #, ('maxWidth' , 'metcap' , 300.0 , Length , '') + #, ('maxWidth' , 'metbot' , 350.0 , Length , '') + #, ('minSpacing' , 'metcap' , 0.84 , Length , 'capm.2a') + #, ('minSpacing' , 'metbot' , 0.8 , Length , 'metcap.2b') + #, ('minSpacing' , 'cut1' , 'metcap' , 0.50 , Length , '') + #, ('minSpacing' , 'cut2' , 'metcap' , 0.50 , Length , 'capm.5') + #, ('minSpacingOnMetbot', 'cut2' , 0.2 , Length , 'via2.2') + #, ('minSpacingOnMetbot', 'via2' , 0.2 , Length , 'via2.2') + #, ('minSpacingOnMetcap', 'cut2' , 0.2 , Length , 'via2.2') + #, ('minEnclosure' , 'm2' , 'metcap' , 0.14 , Length|Asymmetric, 'capm.3') + #, ('minEnclosure' , 'metbot' , 'cut1' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'metbot' , 'cut2' , 0.04 , Length|Asymmetric, 'via2.14') + #, ('minEnclosure' , 'metcap' , 'cut2' , 0.14 , Length|Asymmetric, 'capm.4') + #, ('minArea' , 'metcap' , 0 , Area , 'na') + #, ('minAreaInMetcap' , 'cut2' , 0 , Area , 'na') + #, ('MIMCap' , 1.25 , Unit , 'na') + #, ('MIMPerimeterCap' , 0.17 , Unit , 'na') + + + #capm + , ('minWidth' , 'capm' , 1.0 , Length , 'capm.1') + , ('minWidth' , 'capmdum' , 0.5 , Length , '') + , ('maxWidth' , 'capm' , 30.0 , Length , '') + , ('maxWidth' , 'metbot' , 35.0 , Length , '') + , ('minSpacing' , 'capm' , 0.84 , Length , 'capm.2a') + #, ('minSpacing' , 'm3' , 0.8 , Length , 'capm.2b') + , ('minSpacingWide1' , 'm2' , 0.8 , Length , 'capm.2b') + , ('minSpacing' , 'via' , 'capm' , 0.50 , Length , 'fake') + , ('minSpacing' , 'via2' , 'capm' , 0.50 , Length , 'capm.5') + , ('minSpacingOnMetBot', 'via2' , 0.2 , Length , 'via2.2') + , ('minSpacingOnMetCap', 'via2' , 0.2 , Length , 'via2.2') + , ('minSpacingOnMetBot', 'via' , 0.2 , Length , 'via2.2 fake') + , ('minSpacingOnMetCap', 'via' , 0.2 , Length , 'via2.2 fake') + , ('minEnclosure' , 'm2' , 'capm' , 0.14 , Length|Asymmetric, 'capm.3') + , ('minEnclosure' , 'm3' , 'via' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'm3' , 'via2' , 0.04 , Length|Asymmetric, 'via2.14') + , ('minEnclosure' , 'capm' , 'via' , 0.14 , Length|Asymmetric, 'capm.4 fake') + , ('minEnclosure' , 'capm' , 'via2' , 0.14 , Length|Asymmetric, 'capm.4') + , ('minArea' , 'capm' , 0 , Area , 'na') + , ('minAreaInMetcap' , 'via2' , 0 , Area , 'na') + , ('MIMCap' , 1.25 , Unit , 'na') + , ('MIMPerimeterCap' , 0.17 , Unit , 'na') + , ('PIPCap' , 1.25 , Unit , 'na') + , ('PIPPerimeterCap' , 0.17 , Unit , 'na') + + ) + + +def _loadDtr (): + """ + Load design kit physical rules for SkyWater 130nm. + """ + loadAnalogTechno( analogTechnologyTable, __file__ ) + + +def _loadDevices (): + addDevice( name = 'DifferentialPairBulkConnected' + #, spice = spiceDir+'DiffPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'DifferentialPairBulkUnconnected' + #, spice = spiceDir+'DiffPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'LevelShifterBulkUnconnected' + #, spice = spiceDir+'LevelShifterBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S1', 'S2', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.LS_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.LS_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.LS_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.LS_interdigitated.py' ) + ) + ) + addDevice( name = 'TransistorBulkConnected' + #, spice = spiceDir+'TransistorBulkConnected.spi' + , connectors = ( 'D', 'G', 'S' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'TransistorBulkUnconnected' + #, spice = spiceDir+'TransistorBulkUnconnected.spi' + , connectors = ( 'D', 'G', 'S', 'B' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkConnected' + #, spice = spiceDir+'CCPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkUnconnected' + #, spice = spiceDir+'CCPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkConnected' + #, spice = spiceDir+'CommonSourcePairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkUnconnected' + #, spice = spiceDir+'CommonSourcePairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkConnected' + #, spice = spiceDir+'CurrMirBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkUnconnected' + #, spice = spiceDir+'CurrMirBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'MultiCapacitor' + #, spice = spiceDir+'MIM_OneCapacitor.spi' + , connectors = ( 'T1', 'B1' ) + , layouts = ( ('Matrix', 'coriolis.oroshi.multicapacitor.py' ), + ) + ) + #addDevice( name = 'Resistor' + # #, spice = spiceDir+'MIM_OneCapacitor.spi' + # , connectors = ( 'PIN1', 'PIN2' ) + # , layouts = ( ('Snake', 'coriolis.oroshi.resistorsnake.py' ), + # ) + # ) + + +def _setup_techno ( coriolisTechDir ): + ShellEnv.RDS_TECHNO_NAME = (coriolisTechDir / 'sky130_nsx2' / 'sky130_nsx3.rds').as_posix() + ShellEnv.GRAAL_TECHNO_NAME = (coriolisTechDir / 'sky130_nsx2' / 'symbolic.graal' ).as_posix() + ShellEnv.DREAL_TECHNO_NAME = (coriolisTechDir / 'sky130_nsx2' / 'symbolic.dreal' ).as_posix() + + db = DataBase.getDB() + CRL.System.get() + + tech = Technology.create(db, 'Sky130_nsx2') + + DbU.setPrecision( 2 ) + DbU.setPhysicalsPerGrid( 0.0025, DbU.UnitPowerMicro ) + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + cfg.gdsDriver.metricDbu = 1e-09 + cfg.gdsDriver.dbuPerUu = 0.001 + DbU.setGridsPerLambda ( 30 ) + DbU.setSymbolicSnapGridStep( DbU.fromGrid( 1.0 )) + DbU.setPolygonStep ( DbU.fromGrid( 1.0 )) + DbU.setStringMode ( DbU.StringModePhysical, DbU.UnitPowerMicro ) + + createBL( tech, 'nwm' , BasicLayer.Material.nWell , size=u(0.84), spacing=u(1.27), gds2Layer= 64, gds2DataType= 20 ) + createBL( tech, 'nsdm' , BasicLayer.Material.nImplant, size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 93, gds2DataType= 44 ) + createBL( tech, 'psdm' , BasicLayer.Material.pImplant, size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 94, gds2DataType= 20 ) + createBL( tech, 'hvi' , BasicLayer.Material.other , gds2Layer= 75, gds2DataType= 20 ) + createBL( tech, 'difftap.pin' , BasicLayer.Material.other , gds2Layer= 65, gds2DataType= 16 ) + createBL( tech, 'difftap.block', BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 10 ) + createBL( tech, 'poly.pin' , BasicLayer.Material.other , gds2Layer= 66, gds2DataType= 16 ) + createBL( tech, 'poly.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 20 ) + createBL( tech, 'li.pin' , BasicLayer.Material.other , gds2Layer= 67, gds2DataType= 16 ) + createBL( tech, 'li.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 40 ) + createBL( tech, 'm1.pin' , BasicLayer.Material.other , gds2Layer= 68, gds2DataType= 16 ) + createBL( tech, 'm1.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 60 ) + createBL( tech, 'm2.pin' , BasicLayer.Material.other , gds2Layer= 69, gds2DataType= 16 ) + createBL( tech, 'm2.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 80 ) + createBL( tech, 'm3.pin' , BasicLayer.Material.other , gds2Layer= 70, gds2DataType= 16 ) + createBL( tech, 'm3.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=100 ) + createBL( tech, 'm4.pin' , BasicLayer.Material.other , gds2Layer= 71, gds2DataType= 16 ) + createBL( tech, 'm4.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=120 ) + createBL( tech, 'm5.pin' , BasicLayer.Material.other , gds2Layer= 72, gds2DataType= 16 ) + createBL( tech, 'm5.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=140 ) + createBL( tech, 'licon.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 30 ) + createBL( tech, 'mcon.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 50 ) + createBL( tech, 'via.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 70 ) + createBL( tech, 'via2.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 90 ) + createBL( tech, 'via3.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=110 ) + createBL( tech, 'via4.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=130 ) + createBL( tech, 'difftap' , BasicLayer.Material.active , size=u(0.15), spacing=u(0.27), gds2Layer= 65, gds2DataType= 20 ) + createBL( tech, 'poly' , BasicLayer.Material.poly , size=u(0.15), spacing=u(0.21), gds2Layer= 66, gds2DataType= 20 ) + createBL( tech, 'licon' , BasicLayer.Material.cut , size=u(0.17), spacing=u(0.17), gds2Layer= 66, gds2DataType= 44 ) + createBL( tech, 'li' , BasicLayer.Material.metal , size=u(0.17), spacing=u(0.17), gds2Layer= 67, gds2DataType= 20 ) + createBL( tech, 'mcon' , BasicLayer.Material.cut , size=u(0.17), spacing=u(0.19), gds2Layer= 67, gds2DataType= 44 ) + createBL( tech, 'm1' , BasicLayer.Material.metal , size=u(0.14), spacing=u(0.14), area=0.083, gds2Layer= 68, gds2DataType= 20 ) + createBL( tech, 'via' , BasicLayer.Material.cut , size=u(0.15), spacing=u(0.17), gds2Layer= 68, gds2DataType= 44 ) + createBL( tech, 'm2' , BasicLayer.Material.metal , size=u(0.14), spacing=u(0.14), area=0.0676, gds2Layer= 69, gds2DataType= 20 ) + createBL( tech, 'capm' , BasicLayer.Material.metal ) + createBL( tech, 'via2' , BasicLayer.Material.cut , size=u(0.2 ), spacing=u(0.2 ), gds2Layer= 69, gds2DataType= 44 ) + createBL( tech, 'm3' , BasicLayer.Material.metal , size=u(0.3 ), spacing=u(0.3 ), area=0.24, gds2Layer= 70, gds2DataType= 20 ) + createBL( tech, 'via3' , BasicLayer.Material.cut , size=u(0.2 ), spacing=u(0.2 ), gds2Layer= 70, gds2DataType= 44 ) + createBL( tech, 'm4' , BasicLayer.Material.metal , size=u(0.3 ), spacing=u(0.3 ), area=0.24, gds2Layer= 71, gds2DataType= 20 ) + createBL( tech, 'via4' , BasicLayer.Material.cut , size=u(0.8 ), spacing=u(0.8 ), gds2Layer= 71, gds2DataType= 44 ) + createBL( tech, 'm5' , BasicLayer.Material.metal , size=u(1.6 ), spacing=u(1.6 ), area=4.0, gds2Layer= 72, gds2DataType= 20 ) + createBL( tech, 'hvtp' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 78, gds2DataType= 44 ) + createBL( tech, 'lvtn' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer=125, gds2DataType= 44 ) + createBL( tech, 'areaid_sc' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 4 ) + createBL( tech, 'pad' , BasicLayer.Material.cut , size=u(40.0), spacing=u(1.27), gds2Layer= 76, gds2DataType= 20 ) + createBL( tech, 'areaid_diode' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 23 ) + createBL( tech, 'pnp' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 44 ) + createBL( tech, 'diffres' , BasicLayer.Material.other , gds2Layer= 65, gds2DataType= 13 ) + createBL( tech, 'npn' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 20 ) + createBL( tech, 'polyres' , BasicLayer.Material.other , gds2Layer= 66, gds2DataType= 13 ) + createBL( tech, 'prBoundary' , BasicLayer.Material.other , gds2Layer=235, gds2DataType= 4 ) + + tech.addLayerAlias( 'm1', 'met1' ) + tech.addLayerAlias( 'm2', 'met2' ) + tech.addLayerAlias( 'm3', 'met3' ) + tech.addLayerAlias( 'm4', 'met4' ) + tech.addLayerAlias( 'm5', 'met5' ) + + # ViaLayers + createVia( tech, 'li_mcon_m1' , 'li' , 'mcon', 'm1', u(0.17) ) + createVia( tech, 'm1_via_m2' , 'm1' , 'via' , 'm2', u(0.15) ) + createVia( tech, 'm2_via2_m3' , 'm2' , 'via2', 'm3', u(0.2 ) ) + createVia( tech, 'capm_via2_m3', 'capm', 'via2', 'm3', u(0.2 ) ) + createVia( tech, 'm3_via3_m4' , 'm3' , 'via3', 'm4', u(0.2 ) ) + createVia( tech, 'm4_via4_m5' , 'm4' , 'via4', 'm5', u(0.8 ) ) + + # Blockages + tech.getLayer('difftap').setBlockageLayer( tech.getLayer('difftap.block') ) + tech.getLayer('poly') .setBlockageLayer( tech.getLayer('poly.block') ) + tech.getLayer('li') .setBlockageLayer( tech.getLayer('li.block') ) + tech.getLayer('m1') .setBlockageLayer( tech.getLayer('m1.block') ) + tech.getLayer('m2') .setBlockageLayer( tech.getLayer('m2.block') ) + tech.getLayer('m3') .setBlockageLayer( tech.getLayer('m3.block') ) + tech.getLayer('m4') .setBlockageLayer( tech.getLayer('m4.block') ) + tech.getLayer('m5') .setBlockageLayer( tech.getLayer('m5.block') ) + tech.getLayer('licon') .setBlockageLayer( tech.getLayer('licon.block') ) + tech.getLayer('mcon') .setBlockageLayer( tech.getLayer('mcon.block') ) + tech.getLayer('via') .setBlockageLayer( tech.getLayer('via.block') ) + tech.getLayer('via2') .setBlockageLayer( tech.getLayer('via2.block') ) + tech.getLayer('via3') .setBlockageLayer( tech.getLayer('via3.block') ) + tech.getLayer('via4') .setBlockageLayer( tech.getLayer('via4.block') ) + + # Coriolis internal layers + createBL( tech, 'text.cell' , BasicLayer.Material.other, ) + createBL( tech, 'text.instance', BasicLayer.Material.other, ) + createBL( tech, 'SPL1' , BasicLayer.Material.other, ) + createBL( tech, 'AutoLayer' , BasicLayer.Material.other, ) + createBL( tech, 'gmetalh' , BasicLayer.Material.metal, ) + createBL( tech, 'gcontact' , BasicLayer.Material.cut, ) + createBL( tech, 'gmetalv' , BasicLayer.Material.metal, ) + + # Resistors + # ResistorLayer.create(tech, 'poly_res', 'poly', 'polyres') + # ResistorLayer.create(tech, 'active_res', 'difftap', 'diffres') + + # Transistors + # GateLayer.create(tech, 'hvmosgate' , 'difftap', 'poly', 'hvi') + # GateLayer.create(tech, 'mosgate' , 'difftap', 'poly') + # GateLayer.create(tech, 'mosgate_sc', 'difftap', 'poly') + # TransistorLayer.create(tech, 'nfet_01v8' , 'mosgate' , 'nsdm') + # TransistorLayer.create(tech, 'nfet_01v8_lvt' , 'mosgate' , ('nsdm', 'lvtn')) + # TransistorLayer.create(tech, 'nfet_01v8_sc' , 'mosgate_sc', 'nsdm') + # TransistorLayer.create(tech, 'nfet_g5v0d10v5', 'hvmosgate' , 'nsdm') + # TransistorLayer.create(tech, 'pfet_01v8' , 'mosgate' , 'psdm', 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_hvt' , 'mosgate' , ('psdm', 'hvtp'), 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_lvt' , 'mosgate' , ('psdm', 'lvtn'), 'nwm') + # TransistorLayer.create(tech, 'pfet_g5v0d10v5', 'hvmosgate' , 'psdm', 'nwm') + + # Bipolars + # Not implemented: Bipolar 'pnp_05v5_w0u68l0u68' + # Not implemented: Bipolar 'npn_05v5_w1u00l2u00' + # Not implemented: Bipolar 'pnp_05v5_w3u40l3u40' + # Not implemented: Bipolar 'npn_05v5_w1u00l1u00' + + +def _setup_display (): + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [black] + + threshold = 0.2 if Viewer.Graphics.isHighDpi() else 0.1 + + style = Viewer.DisplayStyle( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - black background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + # Viewer. + style.addDrawingStyle( group='Viewer', name='fallback' , color=toRGB('Gray238' ), border=1, pattern='55AA55AA55AA55AA' ) + style.addDrawingStyle( group='Viewer', name='background' , color=toRGB('Gray50' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='rubber' , color=toRGB('192,0,192' ), border=4, threshold=0.02 ) + style.addDrawingStyle( group='Viewer', name='phantom' , color=toRGB('Seashell4' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries' , color=toRGB('wheat1' ), border=2, pattern='0000000000000000', threshold=0 ) + style.addDrawingStyle( group='Viewer', name='marker' , color=toRGB('80,250,80' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionDraw' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionFill' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='grid' , color=toRGB('White' ), border=1, threshold=2.0 ) + style.addDrawingStyle( group='Viewer', name='spot' , color=toRGB('White' ), border=2, threshold=6.0 ) + style.addDrawingStyle( group='Viewer', name='ghost' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='text.ruler' , color=toRGB('White' ), border=1, threshold= 0.0 ) + style.addDrawingStyle( group='Viewer', name='text.instance' , color=toRGB('White' ), border=1, threshold=400.0 ) + style.addDrawingStyle( group='Viewer', name='text.reference', color=toRGB('White' ), border=1, threshold=200.0 ) + style.addDrawingStyle( group='Viewer', name='undef' , color=toRGB('Violet' ), border=0, pattern='2244118822441188' ) + + # Active Layers. + style.addDrawingStyle(group='Active Layers', name='nwm' , color=toRGB('Tan' ), pattern=toHexa('urgo.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='nsdm' , color=toRGB('LawnGreen'), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='psdm' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='hvtp' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='lvtn' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='difftap' , color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='difftap.pin', color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly.pin' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + + # Routing Layers. + style.addDrawingStyle(group='Routing Layers', name='li' , color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='li.pin', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m1' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m1.pin', color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m2' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m2.pin', color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m3' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m3.pin', color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m4' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m4.pin', color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m5' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m5.pin', color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + + # Cuts (VIA holes). + style.addDrawingStyle(group='Cuts (VIA holes', name='licon', color=toRGB('0,150,150'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='mcon' , color=toRGB('Aqua' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via' , color=toRGB('LightPink'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via2' , color=toRGB('Green' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via3' , color=toRGB('Yellow' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via4' , color=toRGB('Violet' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='pad' , color=toRGB('Red' ), threshold=threshold) + + # Blockages. + style.addDrawingStyle(group='Blockages', name='difftap.block', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='poly.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='li.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m1.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m2.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m3.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m4.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m5.block' , color=toRGB('Blue' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='licon.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='mcon.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via2.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via3.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via4.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + + # Knick & Kite. + style.addDrawingStyle( group='Knik & Kite', name='SPL1' , color=toRGB('Red' ) ) + style.addDrawingStyle( group='Knik & Kite', name='AutoLayer' , color=toRGB('Magenta' ) ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalh' , color=toRGB('128,255,200'), pattern=toHexa('antislash2.32' ), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalv' , color=toRGB('200,200,255'), pattern=toHexa('light_antihash1.8'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gcontact' , color=toRGB('255,255,190'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::Edge' , color=toRGB('255,255,190'), pattern='0000000000000000' , border=4, threshold=0.02 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::GCell', color=toRGB('255,255,190'), pattern='0000000000000000' , border=2, threshold=threshold ) + + Viewer.Graphics.addStyle( style ) + + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [white]. + + style = Viewer.DisplayStyle( 'Alliance.Classic [white]' ) + style.inheritFrom( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - white background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + style.addDrawingStyle( group='Viewer', name='background', color=toRGB('White'), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground', color=toRGB('Black'), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries', color=toRGB('Black'), border=1, pattern='0000000000000000' ) + Viewer.Graphics.addStyle( style ) + + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + +def setup ( coriolisTechDir ): + _setup_techno( coriolisTechDir ) + _setup_display() + try: + from .techno_symb import setup as setupSymbolic + except: + pass + else: + setupSymbolic() + _loadDtr() + _loadDevices() + diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/techno_symb.py b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/techno_symb.py new file mode 100644 index 000000000..3196a87e3 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/coriolis/sky130_nsx2/techno_symb.py @@ -0,0 +1,284 @@ + +from coriolis.helpers import l, u, n +from coriolis.Hurricane import DataBase, Technology, Layer, BasicLayer, DiffusionLayer, \ + TransistorLayer, RegularLayer, ContactLayer, ViaLayer + +__all__ = [ 'setup' ] + + +def setup (): + tech = DataBase.getDB().getTechnology() + tech.addLayerAlias( 'nwm' , 'nWell' ) + tech.addLayerAlias( 'difftap' , 'active' ) + #tech.addLayerAlias( 'poly' , 'poly' ) + tech.addLayerAlias( 'psdm' , 'pImplant' ) + tech.addLayerAlias( 'nsdm' , 'nImplant' ) + tech.addLayerAlias( 'licon' , 'cut0' ) + tech.addLayerAlias( 'li' , 'metal1' ) + tech.addLayerAlias( 'mcon' , 'cut1' ) + tech.addLayerAlias( 'm1' , 'metal2' ) + tech.addLayerAlias( 'via' , 'cut2' ) + tech.addLayerAlias( 'm2' , 'metal3' ) + tech.addLayerAlias( 'via2' , 'cut3' ) + tech.addLayerAlias( 'm3' , 'metal4' ) + tech.addLayerAlias( 'via3' , 'cut4' ) + tech.addLayerAlias( 'm4' , 'metla5' ) + tech.addLayerAlias( 'via4' , 'cut5' ) + tech.addLayerAlias( 'm5' , 'metal6' ) + tech.addLayerAlias( 'li.block', 'blockage1' ) + tech.addLayerAlias( 'm1.block', 'blockage2' ) + tech.addLayerAlias( 'm2.block', 'blockage3' ) + tech.addLayerAlias( 'm3.block', 'blockage4' ) + tech.addLayerAlias( 'm4.block', 'blockage5' ) + tech.addLayerAlias( 'm5.block', 'blockage6' ) + tech.addLayerAlias( 'capm' , 'metcap' ) + tech.addLayerAlias( 'capm' , 'metcapdum' ) + tech.addLayerAlias( 'm3' , 'metbot' ) + + nWell = tech.getBasicLayer( 'nwm' ) + active = tech.getBasicLayer( 'difftap' ) + poly = tech.getBasicLayer( 'poly' ) + pImplant = tech.getBasicLayer( 'psdm' ) + nImplant = tech.getBasicLayer( 'nsdm' ) + cut0 = tech.getBasicLayer( 'licon' ) + metal1 = tech.getBasicLayer( 'li' ) + cut1 = tech.getBasicLayer( 'mcon' ) + metal2 = tech.getBasicLayer( 'm1' ) + cut2 = tech.getBasicLayer( 'via' ) + metal3 = tech.getBasicLayer( 'm2' ) + cut3 = tech.getBasicLayer( 'via2' ) + metal4 = tech.getBasicLayer( 'm3' ) + cut4 = tech.getBasicLayer( 'via3' ) + metal5 = tech.getBasicLayer( 'm4' ) + cut5 = tech.getBasicLayer( 'via4' ) + metal6 = tech.getBasicLayer( 'm5' ) + blockage1 = tech.getBasicLayer( 'blockage1' ) + blockage2 = tech.getBasicLayer( 'blockage1' ) + blockage3 = tech.getBasicLayer( 'blockage2' ) + blockage4 = tech.getBasicLayer( 'blockage3' ) + blockage5 = tech.getBasicLayer( 'blockage4' ) + blockage6 = tech.getBasicLayer( 'blockage5' ) + + # Composite/Symbolic layers. + NWELL = RegularLayer .create( tech, 'NWELL' , nWell ) + #PWELL = RegularLayer .create( tech, 'PWELL' , pWell ) + NTIE = DiffusionLayer .create( tech, 'NTIE' , nImplant , active, nWell) + PTIE = DiffusionLayer .create( tech, 'PTIE' , pImplant , active, None) + NDIF = DiffusionLayer .create( tech, 'NDIF' , nImplant , active, None ) + PDIF = DiffusionLayer .create( tech, 'PDIF' , pImplant , active, None ) + GATE = DiffusionLayer .create( tech, 'GATE' , poly , active, None ) + NTRANS = TransistorLayer.create( tech, 'NTRANS' , nImplant , active, poly, None ) + PTRANS = TransistorLayer.create( tech, 'PTRANS' , pImplant , active, poly, nWell ) + POLY = RegularLayer .create( tech, 'POLY' , poly ) + METAL1 = RegularLayer .create( tech, 'METAL1' , metal1 ) + METAL2 = RegularLayer .create( tech, 'METAL2' , metal2 ) + METAL3 = RegularLayer .create( tech, 'METAL3' , metal3 ) + METAL4 = RegularLayer .create( tech, 'METAL4' , metal4 ) + METAL5 = RegularLayer .create( tech, 'METAL5' , metal5 ) + METAL6 = RegularLayer .create( tech, 'METAL6' , metal6 ) + CONT_BODY_N = ContactLayer .create( tech, 'CONT_BODY_N', nImplant , active, cut0, metal1, None ) + CONT_BODY_P = ContactLayer .create( tech, 'CONT_BODY_P', pImplant , active, cut0, metal1, None ) + CONT_DIF_N = ContactLayer .create( tech, 'CONT_DIF_N' , nImplant , active, cut0, metal1, None ) + CONT_DIF_P = ContactLayer .create( tech, 'CONT_DIF_P' , pImplant , active, cut0, metal1, None ) + CONT_POLY = ViaLayer .create( tech, 'CONT_POLY' , poly, cut0, metal1 ) + + # VIAs for symbolic technologies. + VIA12 = ViaLayer .create( tech, 'VIA12' , metal1, cut1, metal2 ) + VIA23 = ViaLayer .create( tech, 'VIA23' , metal2, cut2, metal3 ) + #VIA23cap = ViaLayer .create( tech, 'VIA23cap' , metcap, cut2, metal3 ) + VIA34 = ViaLayer .create( tech, 'VIA34' , metal3, cut3, metal4 ) + VIA45 = ViaLayer .create( tech, 'VIA45' , metal4, cut4, metal5 ) + VIA56 = ViaLayer .create( tech, 'VIA56' , metal5, cut5, metal6 ) + BLOCKAGE1 = RegularLayer.create( tech, 'BLOCKAGE1' , blockage1 ) + BLOCKAGE2 = RegularLayer.create( tech, 'BLOCKAGE2' , blockage2 ) + BLOCKAGE3 = RegularLayer.create( tech, 'BLOCKAGE3' , blockage3 ) + BLOCKAGE4 = RegularLayer.create( tech, 'BLOCKAGE4' , blockage4 ) + BLOCKAGE5 = RegularLayer.create( tech, 'BLOCKAGE5' , blockage5 ) + BLOCKAGE6 = RegularLayer.create( tech, 'BLOCKAGE6' , blockage6 ) + + tech.setSymbolicLayer( CONT_BODY_N.getName() ) + tech.setSymbolicLayer( CONT_BODY_P.getName() ) + tech.setSymbolicLayer( CONT_DIF_N .getName() ) + tech.setSymbolicLayer( CONT_DIF_P .getName() ) + tech.setSymbolicLayer( CONT_POLY .getName() ) + tech.setSymbolicLayer( POLY .getName() ) + tech.setSymbolicLayer( METAL1 .getName() ) + tech.setSymbolicLayer( METAL2 .getName() ) + tech.setSymbolicLayer( METAL3 .getName() ) + tech.setSymbolicLayer( METAL4 .getName() ) + tech.setSymbolicLayer( METAL5 .getName() ) + tech.setSymbolicLayer( METAL6 .getName() ) + tech.setSymbolicLayer( BLOCKAGE1 .getName() ) + tech.setSymbolicLayer( BLOCKAGE2 .getName() ) + tech.setSymbolicLayer( BLOCKAGE3 .getName() ) + tech.setSymbolicLayer( BLOCKAGE4 .getName() ) + tech.setSymbolicLayer( BLOCKAGE5 .getName() ) + tech.setSymbolicLayer( BLOCKAGE6 .getName() ) + tech.setSymbolicLayer( VIA12 .getName() ) + tech.setSymbolicLayer( VIA23 .getName() ) + tech.setSymbolicLayer( VIA34 .getName() ) + tech.setSymbolicLayer( VIA45 .getName() ) + tech.setSymbolicLayer( VIA56 .getName() ) + + NWELL.setExtentionCap( nWell, l(0.0) ) + #PWELL.setExtentionCap( pWell, l(0.0) ) + + NTIE.setMinimalSize ( l(3.0) ) + NTIE.setExtentionCap ( nWell , l(1.5) ) + NTIE.setExtentionWidth( nWell , l(0.5) ) + NTIE.setExtentionCap ( nImplant, l(1.0) ) + NTIE.setExtentionWidth( nImplant, l(0.5) ) + NTIE.setExtentionCap ( active , l(0.5) ) + NTIE.setExtentionWidth( active , l(0.0) ) + + PTIE.setMinimalSize ( l(3.0) ) + PTIE.setExtentionCap ( nWell , l(1.5) ) + PTIE.setExtentionWidth( nWell , l(0.5) ) + PTIE.setExtentionCap ( nImplant, l(1.0) ) + PTIE.setExtentionWidth( nImplant, l(0.5) ) + PTIE.setExtentionCap ( active , l(0.5) ) + PTIE.setExtentionWidth( active , l(0.0) ) + + NDIF.setMinimalSize ( l(3.0) ) + NDIF.setExtentionCap ( nImplant, l(1.0) ) + NDIF.setExtentionWidth( nImplant, l(0.5) ) + NDIF.setExtentionCap ( active , l(0.5) ) + NDIF.setExtentionWidth( active , l(0.0) ) + + PDIF.setMinimalSize ( l(3.0) ) + PDIF.setExtentionCap ( pImplant, l(1.0) ) + PDIF.setExtentionWidth( pImplant, l(0.5) ) + PDIF.setExtentionCap ( active , l(0.5) ) + PDIF.setExtentionWidth( active , l(0.0) ) + + GATE.setMinimalSize ( l(1.0) ) + GATE.setExtentionCap ( poly , l(1.5) ) + + NTRANS.setMinimalSize ( l( 1.0) ) + NTRANS.setExtentionCap ( nImplant, l(-1.0) ) + NTRANS.setExtentionWidth( nImplant, l( 2.5) ) + NTRANS.setExtentionCap ( active , l(-1.5) ) + NTRANS.setExtentionWidth( active , l( 2.0) ) + + PTRANS.setMinimalSize ( l( 1.0) ) + PTRANS.setExtentionCap ( nWell , l(-1.0) ) + PTRANS.setExtentionWidth( nWell , l( 4.5) ) + PTRANS.setExtentionCap ( pImplant, l(-1.0) ) + PTRANS.setExtentionWidth( pImplant, l( 4.0) ) + PTRANS.setExtentionCap ( active , l(-1.5) ) + PTRANS.setExtentionWidth( active , l( 3.0) ) + + POLY .setMinimalSize ( l(1.0) ) + POLY .setExtentionCap ( poly , l(0.5) ) + #POLY2.setMinimalSize ( l(1.0) ) + #POLY2.setExtentionCap ( poly , l(0.5) ) + + METAL1 .setMinimalSize ( l(1.0) ) + METAL1 .setExtentionCap ( metal1 , l(0.5) ) + METAL2 .setMinimalSize ( l(1.0) ) + METAL2 .setExtentionCap ( metal2 , l(1.0) ) + METAL3 .setMinimalSize ( l(1.0) ) + METAL3 .setExtentionCap ( metal3 , l(1.0) ) + METAL4 .setMinimalSize ( l(1.0) ) + METAL4 .setExtentionCap ( metal4 , l(1.0) ) + METAL4 .setMinimalSpacing( l(3.0) ) + METAL5 .setMinimalSize ( l(2.0) ) + METAL5 .setExtentionCap ( metal5 , l(1.0) ) + #METAL6 .setMinimalSize ( l(2.0) ) + #METAL6 .setExtentionCap ( metal6 , l(1.0) ) + #METAL7 .setMinimalSize ( l(2.0) ) + #METAL7 .setExtentionCap ( metal7 , l(1.0) ) + #METAL8 .setMinimalSize ( l(2.0) ) + #METAL8 .setExtentionCap ( metal8 , l(1.0) ) + #METAL9 .setMinimalSize ( l(2.0) ) + #METAL9 .setExtentionCap ( metal9 , l(1.0) ) + #METAL10.setMinimalSize ( l(2.0) ) + #METAL10.setExtentionCap ( metal10 , l(1.0) ) + + # Contacts (i.e. Active <--> Metal) (symbolic). + CONT_BODY_N.setMinimalSize( l( 1.0) ) + CONT_BODY_N.setEnclosure ( nWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( nImplant, l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( active , l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_BODY_P.setMinimalSize( l( 1.0) ) + #CONT_BODY_P.setEnclosure ( pWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( pImplant, l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( active , l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_N.setMinimalSize( l( 1.0) ) + CONT_DIF_N.setEnclosure ( nImplant, l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_P.setMinimalSize( l( 1.0) ) + CONT_DIF_P.setEnclosure ( pImplant, l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_POLY.setMinimalSize( l( 1.0) ) + CONT_POLY.setEnclosure ( poly , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_POLY.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + # VIAs (i.e. Metal <--> Metal) (symbolic). + VIA12 .setMinimalSize ( l( 1.0) ) + VIA12 .setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setEnclosure ( metal2 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setMinimalSpacing( l( 4.0) ) + VIA23 .setMinimalSize ( l( 1.0) ) + VIA23 .setEnclosure ( metal2 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setEnclosure ( metal3 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setMinimalSpacing( l( 4.0) ) + VIA34 .setMinimalSize ( l( 1.0) ) + VIA34 .setEnclosure ( metal3 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setEnclosure ( metal4 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setMinimalSpacing( l( 4.0) ) + VIA45 .setMinimalSize ( l( 1.0) ) + VIA45 .setEnclosure ( metal4 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setMinimalSpacing( l( 4.0) ) + #VIA56 .setMinimalSize ( l( 1.0) ) + #VIA56 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setMinimalSpacing( l( 4.0) ) + #VIA67 .setMinimalSize ( l( 1.0) ) + #VIA67 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSize ( l( 1.0) ) + #VIA78 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA89 .setMinimalSize ( l( 1.0) ) + #VIA89 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setMinimalSpacing( l( 4.0) ) + #VIA910.setMinimalSize ( l( 1.0) ) + #VIA910.setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setEnclosure ( metal10 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setMinimalSpacing( l( 4.0) ) + + # Blockages (symbolic). + BLOCKAGE1 .setMinimalSize ( l( 1.0) ) + BLOCKAGE1 .setExtentionCap( blockage1 , l( 0.5) ) + BLOCKAGE2 .setMinimalSize ( l( 2.0) ) + BLOCKAGE2 .setExtentionCap( blockage2 , l( 0.5) ) + BLOCKAGE3 .setMinimalSize ( l( 2.0) ) + BLOCKAGE3 .setExtentionCap( blockage3 , l( 0.5) ) + BLOCKAGE4 .setMinimalSize ( l( 2.0) ) + BLOCKAGE4 .setExtentionCap( blockage4 , l( 0.5) ) + BLOCKAGE5 .setMinimalSize ( l( 2.0) ) + BLOCKAGE5 .setExtentionCap( blockage5 , l( 1.0) ) + #BLOCKAGE6 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE6 .setExtentionCap( blockage6 , l( 1.0) ) + #BLOCKAGE7 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE7 .setExtentionCap( blockage7 , l( 1.0) ) + #BLOCKAGE8 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE8 .setExtentionCap( blockage8 , l( 1.0) ) + #BLOCKAGE9 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE9 .setExtentionCap( blockage9 , l( 1.0) ) + #BLOCKAGE10.setMinimalSize ( l( 2.0) ) + #BLOCKAGE10.setExtentionCap( blockage10, l( 1.0) ) diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/core/sky130A_mr.drc b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/core/sky130A_mr.drc new file mode 100644 index 000000000..46c9b1fd1 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/core/sky130A_mr.drc @@ -0,0 +1,800 @@ +# DRC for SKY130 according to : +# https://skywater-pdk.readthedocs.io/en/latest/rules/periphery.html +# https://skywater-pdk.readthedocs.io/en/latest/rules/layers.html +# +# Distributed under GNU GPLv3: https://www.gnu.org/licenses/ +# +# History : +# 2022-6-22 : 2022.6.30_01.07 release +# +# 2023-6-14 : 2023.6.14_01.08 release +# +########################################################################################## +release = "2023.6.14_01.08" + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{msg} +" +end +# optionnal for a batch launch : klayout -b -rd input=my_layout.gds -rd report=sky130_drc.txt -r drc_sky130.drc +if $input + source($input, $top_cell) +end + +if $report == "" + report("SKY130 DRC runset") +elsif $report + report("SKY130 DRC runset", $report) +else + report("SKY130 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "sky130_drc.txt")) +end + +AL = true # do not change +CU = false # do not change +# choose betwen only one of AL or CU back-end flow here : +backend_flow = AL + +option_FEOL = false +option_BEOL = false +option_OFFGRID = false +option_SEAL = false +option_FLOATING_MET = false + +# enable / disable rule groups +if $feol == "1" || $feol == "true" + option_FEOL = true # front-end-of-line checks +else + option_FEOL = false +end + +if $beol == "1" || $beol == "true" + option_BEOL = true # back-end-of-line checks +else + option_BEOL = false +end + +if $offgrid == "1" || $offgrid == "true" + option_OFFGRID = true # manufacturing grid/angle checks +else + option_OFFGRID = false +end + +if $seal == "1" || $seal == "true" + option_SEAL = true # option_SEAL RING checks +else + option_SEAL = false +end + +if $floating_met == "1" || $floating_met == "true" + option_FLOATING_MET = true # back-end-of-line checks +else + option_FLOATING_MET = false +end + +# klayout setup +######################## +# use a tile size of 1mm - not used in deep mode- +# tiles(1000.um) +# use a tile border of 10 micron: +# tile_borders(1.um) +#no_borders + +# hierachical +deep + +if $thr + threads($thr) +else + threads(4) +end + +# if more inof is needed, set true +# verbose(true) +verbose(true) + +# layers definitions +######################## + +# all except purpose (datatype) 5 -- label and 44 -- via +li_wildcard = "67/20" +mcon_wildcard = "67/44" + +m1_wildcard = "68/20" +via_wildcard = "68/44" + +m2_wildcard = "69/20" +via2_wildcard = "69/44" + +m3_wildcard = "70/20" +via3_wildcard = "70/44" + +m4_wildcard = "71/20" +via4_wildcard = "71/44" + +m5_wildcard = "72/20" + +nsdm_wildcard = "93/44" + +psdm_wildcard = "94/20" +nwell_wildcard = "64/20" + +diff = input(65, 20) +tap = polygons(65, 44) +nwell = polygons(nwell_wildcard) +dnwell = polygons(64, 18) +pwbm = polygons(19, 44) +pwde = polygons(124, 20) +natfet = polygons(124, 21) +hvtr = polygons(18, 20) +hvtp = polygons(78, 44) +ldntm = polygons(11, 44) +hvi = polygons(75, 20) +tunm = polygons(80, 20) +lvtn = polygons(125, 44) +poly = polygons(66, 20) +hvntm = polygons(125, 20) +nsdm = polygons(nsdm_wildcard) +psdm = polygons(psdm_wildcard) +rpm = polygons(86, 20) +urpm = polygons(79, 20) +npc = polygons(95, 20) +licon = polygons(66, 44) + +li = polygons(li_wildcard) +mcon = polygons(mcon_wildcard) + +m1 = polygons(m1_wildcard) +via = polygons(via_wildcard) + +m2 = polygons(m2_wildcard) +via2 = polygons(via2_wildcard) + +m3 = polygons(m3_wildcard) +via3 = polygons(via3_wildcard) + +m4 = polygons(m4_wildcard) +via4 = polygons(via4_wildcard) + +m5 = polygons(m5_wildcard) + +pad = polygons(76, 20) +nsm = polygons(61, 20) +capm = polygons(89, 44) +cap2m = polygons(97, 44) +vhvi = polygons(74, 21) +uhvi = polygons(74, 22) +npn = polygons(82, 20) +inductor = polygons(82, 24) +vpp = polygons(82, 64) +pnp = polygons(82, 44) +lvs_prune = polygons(84, 44) +ncm = polygons(92, 44) +padcenter = polygons(81, 20) +mf = polygons(76, 44) +areaid_sl = polygons(81, 1) +areaid_ce = polygons(81, 2) +areaid_fe = polygons(81, 3) +areaid_sc = polygons(81, 4) +areaid_sf = polygons(81, 6) +areaid_sw = polygons(81, 7) +areaid_sr = polygons(81, 8) +areaid_mt = polygons(81, 10) +areaid_dt = polygons(81, 11) +areaid_ft = polygons(81, 12) +areaid_ww = polygons(81, 13) +areaid_ld = polygons(81, 14) +areaid_ns = polygons(81, 15) +areaid_ij = polygons(81, 17) +areaid_zr = polygons(81, 18) +areaid_ed = polygons(81, 19) +areaid_de = polygons(81, 23) +areaid_rd = polygons(81, 24) +areaid_dn = polygons(81, 50) +areaid_cr = polygons(81, 51) +areaid_cd = polygons(81, 52) +areaid_st = polygons(81, 53) +areaid_op = polygons(81, 54) +areaid_en = polygons(81, 57) +areaid_en20 = polygons(81, 58) +areaid_le = polygons(81, 60) +areaid_hl = polygons(81, 63) +areaid_sd = polygons(81, 70) +areaid_po = polygons(81, 81) +areaid_it = polygons(81, 84) +areaid_et = polygons(81, 101) +areaid_lvt = polygons(81, 108) +areaid_re = polygons(81, 125) +areaid_ag = polygons(81, 79) +poly_rs = polygons(66, 13) +diff_rs = polygons(65, 13) +pwell_rs = polygons(64, 13) +li_rs = polygons(67, 13) +cfom = polygons(22, 20) + + +# Define a new custom function that selects polygons by their number of holes: +# It will return a new layer containing those polygons with min to max holes. +# max can be nil to omit the upper limit. +class DRC::DRCLayer + def with_holes(min, max) + new_data = RBA::Region::new + self.data.each do |p| + if p.holes >= (min || 0) && (!max || p.holes <= max) + new_data.insert(p) + end + end + DRC::DRCLayer::new(@engine, new_data) + end +end + +# DRC section +######################## +log("DRC section") + +if option_FEOL +log("option_FEOL section") +# dnwell +log("START: 64/18 (dnwell)") +dnwell.width(3.0, euclidian).output("dnwell.2", "dnwell.2 : min. dnwell width : 3.0um") +log("END: 64/18 (dnwell)") + +not_sram = layout(source.cell_obj).select("-*sky130_sram_*kbyte_*") +not_sram_nsdm = not_sram.input(nsdm_wildcard) +not_sram_psdm = not_sram.input(psdm_wildcard) +not_sram_nwell = not_sram.input(nwell_wildcard) + +# This is a hack, should be reverted + +not_io = layout(source.cell_obj).select("-*sky130_fd_io__gpiov2_amux", "-*sky130_fd_io__simple_pad_and_busses") +not_io_nwell = not_io.input(nwell_wildcard) + +# nwell +log("START: 64/20 (nwell)") +nwell.width(0.84, euclidian).output("nwell.1", "nwell.1 : min. nwell width : 0.84um") +nwell.space(1.27, euclidian).output("nwell.2a", "nwell.2a : min. nwell spacing (merged if less) : 1.27um") +nwell_interact = not_sram_nwell.and(not_io_nwell).merge +dnwell.enclosing(nwell_interact.holes, 1.03, euclidian).output("nwell.6", "nwell.6 : min enclosure of nwellHole by dnwell : 1.03um") +log("END: 64/20 (nwell)") + +# hvtp +log("START: 78/44 (hvtp)") +hvtp.width(0.38, euclidian).output("hvtp.1", "hvtp.1 : min. hvtp width : 0.38um") +hvtp.space(0.38, euclidian).output("hvtp.2", "hvtp.2 : min. hvtp spacing : 0.38um") +log("END: 78/44 (hvtp)") + +# hvtr +log("START: 18/20 (htvr)") +hvtr.width(0.38, euclidian).output("hvtr.1", "hvtr.1 : min. hvtr width : 0.38um") +hvtr.separation(hvtp, 0.38, euclidian).output("hvtr.2", "hvtr.2 : min. hvtr spacing : 0.38um") +hvtr.and(hvtp).output("hvtr.2_a", "hvtr.2_a : hvtr must not overlap hvtp") +log("END: 18/20 (htvr)") + +# lvtn +log("START: 25/44 (lvtn)") +lvtn.width(0.38, euclidian).output("lvtn.1a", "lvtn.1a : min. lvtn width : 0.38um") +lvtn.space(0.38, euclidian).output("lvtn.2", "lvtn.2 : min. lvtn spacing : 0.38um") +log("END: 25/44 (lvtn)") + +# ncm +log("START: 92/44 (ncm)") +ncm.width(0.38, euclidian).output("ncm.1", "ncm.1 : min. ncm width : 0.38um") +ncm.space(0.38, euclidian).output("ncm.2a", "ncm.2a : min. ncm spacing : 0.38um") +log("END: 92/44 (ncm)") + +# diff-tap +log("START: 65/20 (diff)") +difftap = diff.or(tap) +diff_width = diff.rectangles.width(0.15, euclidian).polygons +diff_cross_areaid_ce = diff_width.edges.outside_part(areaid_ce).not(diff_width.outside(areaid_ce).edges) +diff_cross_areaid_ce.output("difftap.1", "difftap.1 : min. diff width across areaid:ce : 0.15um") +diff.outside(areaid_ce).width(0.15, euclidian).output("difftap.1_a", "difftap.1_a : min. diff width in periphery : 0.15um") +log("END: 65/20 (diff)") + +log("START: 65/44 (tap)") +tap_width = tap.rectangles.width(0.15, euclidian).polygons +tap_cross_areaid_ce = tap_width.edges.outside_part(areaid_ce).not(tap_width.outside(areaid_ce).edges) +tap_cross_areaid_ce.output("difftap.1_b", "difftap.1_b : min. tap width across areaid:ce : 0.15um") +tap.not(areaid_ce).width(0.15, euclidian).output("difftap.1_c", "difftap.1_c : min. tap width in periphery : 0.15um") +log("END: 65/44 (tap)") + +difftap.space(0.27, euclidian).output("difftap.3", "difftap.3 : min. difftap spacing : 0.27um") + +# tunm +log("START: 80/20 (tunm)") +tunm.width(0.41, euclidian).output("tunm.1", "tunm.1 : min. tunm width : 0.41um") +tunm.space(0.5, euclidian).output("tunm.2", "tunm.2 : min. tunm spacing : 0.5um") +log("END: 80/20 (tunm)") + +# poly +log("START: 66/20 (poly)") +poly.width(0.15, euclidian).output("poly.1a", "poly.1a : min. poly width : 0.15um") +poly.not(areaid_ce).space(0.21, euclidian).output("poly.2", "poly.2 : min. poly spacing : 0.21um") + + +# rpm +log("START: 86/20 (rpm)") +rpm.width(1.27, euclidian).output("rpm.1a", "rpm.1a : min. rpm width : 1.27um") +rpm.space(0.84, euclidian).output("rpm.2", "rpm.2 : min. rpm spacing : 0.84um") +log("END: 86/20 (rpm)") + +# urpm +log("START: 79/20 (urpm)") +urpm.width(1.27, euclidian).output("urpm.1a", "urpm.1a : min. rpm width : 1.27um") +urpm.space(0.84, euclidian).output("urpm.2", "urpm.2 : min. rpm spacing : 0.84um") +log("END: 79/20 (urpm)") + +# npc +log("START: 95/20 (npc)") +npc.width(0.27, euclidian).output("npc.1", "npc.1 : min. npc width : 0.27um") +npc.space(0.27, euclidian).output("npc.2", "npc.2 : min. npc spacing, should be manually merged if less than : 0.27um") +log("END: 95/20 (npc)") + +# nsdm +log("START: 93/44 (nsdm)") +not_sram_nsdm.outside(areaid_ce).width(0.38, euclidian).output("nsd.1", "nsd.1 : min. nsdm width : 0.38um") +not_sram_nsdm.not(areaid_ce).space(0.38, euclidian).output("nsd.2", "nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um") +log("END: 93/44 (nsdm)") + +# psdm +log("START: 94/20 (psdm)") +not_sram_psdm.outside(areaid_ce).width(0.38, euclidian).output("psd.1", "psd.1 : min. psdm width : 0.38um") +not_sram_psdm.not(areaid_ce).space(0.38, euclidian).output("psd.2", "psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um") +log("END: 94/20 (psdm)") + +# licon +log("START: 66/44 (licon)") +if option_SEAL + ringLICON = licon.drc(with_holes > 0) + rectLICON = licon.not(ringLICON) +else + rectLICON = licon +end +xfom = difftap.not(poly) +licon1ToXfom = licon.interacting(licon.and(xfom)) +licon1ToXfom_PERI = licon1ToXfom.not(areaid_ce) +rectLICON.non_rectangles.output("licon.1", "licon.1 : licon should be rectangle") +rectLICON.not(rpm.or(urpm)).edges.without_length(0.17).output("licon.1_a/b", "licon.1_a/b : minimum/maximum width of licon : 0.17um") +licon1ToXfom_PERI.separation(npc, 0.09, euclidian).output("licon.13", "licon.13 : min. difftap licon spacing to npc : 0.09um") +licon1ToXfom_PERI.and(npc).output("licon.13_a", "licon.13_a : licon of diffTap in periphery must not overlap npc") +licon.interacting(poly).and(licon.interacting(difftap)).output("licon.17", "licon.17 : Licons may not overlap both poly and (diff or tap)") +log("END: 66/44 (licon)") + +# CAPM +log("START: 89/44 (capm)") +capm.width(1.0, euclidian).output("capm.1", "capm.1 : min. capm width : 1.0um") +capm.space(0.84, euclidian).output("capm.2a", "capm.2a : min. capm spacing : 0.84um") +m3.interacting(capm).isolated(1.2, euclidian).output("capm.2b", "capm.2b : min. capm spacing : 1.2um") +(m3.interacting(capm)).isolated(1.2, euclidian).output("capm.2b_a", "capm.2b_a : min. spacing of m3_bot_plate : 1.2um") +capm.and(m3).enclosing(m3, 0.14, euclidian).output("capm.3", "capm.3 : min. capm and m3 enclosure of m3 : 0.14um") +m3.enclosing(capm, 0.14, euclidian).output("capm.3_a", "capm.3_a : min. m3 enclosure of capm : 0.14um") +capm.enclosing(via3, 0.14, euclidian).output("capm.4", "capm.4 : min. capm enclosure of via3 : 0.14um") +capm.separation(via3, 0.14, euclidian).output("capm.5", "capm.5 : min. capm spacing to via3 : 0.14um") +(m3.not_interacting(capm)).separation(capm, 0.5, euclidian).output("capm.11", "capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um") +log("END: 89/44 (capm)") + +# CAP2M +log("START: 97/44 (cap2m)") +cap2m.width(1.0, euclidian).output("cap2m.1", "cap2m.1 : min. cap2m width : 1.0um") +cap2m.space(0.84, euclidian).output("cap2m.2a", "cap2m.2a : min. cap2m spacing : 0.84um") +m4.interacting(cap2m).isolated(1.2, euclidian).output("cap2m.2b", "cap2m.2b : min. cap2m spacing : 1.2um") +(m4.interacting(cap2m)).isolated(1.2, euclidian).output("cap2m.2b_a", "cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um") +cap2m.and(m4).enclosing(m4, 0.14, euclidian).output("cap2m.3", "cap2m.3 : min. m4 enclosure of cap2m : 0.14um") +m4.enclosing(cap2m, 0.14, euclidian).output("cap2m.3_a", "cap2m.3_a : min. m4 enclosure of cap2m : 0.14um") +cap2m.enclosing(via4, 0.2, euclidian).output("cap2m.4", "cap2m.4 : min. cap2m enclosure of via4 : 0.14um") +cap2m.separation(via4, 0.2, euclidian).output("cap2m.5", "cap2m.5 : min. cap2m spacing to via4 : 0.14um") +(m4.not_interacting(cap2m)).separation(cap2m, 0.5, euclidian).output("cap2m.11", "cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um") +log("END: 97/44 (cap2m)") +end #option_FEOL + +if option_BEOL +log("option_BEOL section") + +# li +log("START: 67/20 (li)") +linotace = li.not(li.interacting(areaid_ce)) +linotace.width(0.17, euclidian).output("li.1", "li.1 : min. li width : 0.17um") +# This rule is taking a long time in some slots +linotace.edges.space(0.17, euclidian).output("li.3", "li.3 : min. li spacing : 0.17um") +licon_peri = licon.not(areaid_ce) +li_edges_with_less_enclosure = li.enclosing(licon_peri, 0.08, projection).second_edges +error_corners = li_edges_with_less_enclosure.width(angle_limit(100.0), 1.dbu) +li_interact = licon_peri.interacting(error_corners.polygons(1.dbu)) +li_interact.output("li.5", "li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um") +linotace.with_area(nil, 0.0561).output("li.6", "li.6 : min. li area : 0.0561um²") +log("END: 67/20 (li)") + +# ct +log("START: 67/44 (mcon)") +mconnotace = mcon.not(areaid_ce) +if option_SEAL + ringMCON = mcon.drc(with_holes > 0) + rectMCON = mcon.not(ringMCON) +else + rectMCON = mcon +end +rectMCON_peri = rectMCON.not(areaid_ce) +rectMCON.non_rectangles.output("ct.1", "ct.1: non-ring mcon should be rectangular") +# rectMCON_peri.edges.without_length(0.17).output("ct.1_a/b", "ct.1_a/b : minimum/maximum width of mcon : 0.17um") +rectMCON_peri.drc(width < 0.17).output("ct.1_a", "ct.1_a : minimum width of mcon : 0.17um") +rectMCON_peri.drc(length > 0.17).output("ct.1_b", "ct.1_b : maximum length of mcon : 0.17um") +mcon.space(0.19, euclidian).output("ct.2", "ct.2 : min. mcon spacing : 0.19um") +if option_SEAL + ringMCON.width(0.17, euclidian).output("ct.3", "ct.3 : min. width of ring-shaped mcon : 0.17um") + ringMCON.drc(width >= 0.175).output("ct.3_a", "ct.3_a : max. width of ring-shaped mcon : 0.175um") + ringMCON.not(areaid_sl).output("ct.3_b", "ct.3_b: ring-shaped mcon must be enclosed by areaid_sl") +end +mconnotace.not(li).output("ct.4", "ct.4 : mcon should covered by li") +log("END: 67/44 (mcon)") + +# m1 +log("START: 68/20 (m1)") +m1.width(0.14, euclidian).output("m1.1", "m1.1 : min. m1 width : 0.14um") +huge_m1 = m1.sized(-1.5).sized(1.5).snap(0.005) & m1 +non_huge_m1 = m1.edges - huge_m1 +huge_m1 = huge_m1.edges.outside_part(m1.merged) + +non_huge_m1.space(0.14, euclidian).output("m1.2", "m1.2 : min. m1 spacing : 0.14um") + +(huge_m1.separation(non_huge_m1, 0.28, euclidian) + huge_m1.space(0.28, euclidian)).output("m1.3ab", "m1.3ab : min. 3um.m1 spacing m1 : 0.28um") + +#not_in_cell6 = layout(source.cell_obj).select("-s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b", "-s8fpls_pl8", "-s8fs_cmux4_fm") +not_in_cell6 = layout(source.cell_obj).select("-s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b", "-s8fs_cmux4_fm") +not_in_cell6_m1 = not_in_cell6.input(m1_wildcard) + +not_in_cell6_m1.enclosing(mconnotace, 0.03, euclidian).output("791_m1.4", "791_m1.4 : min. m1 enclosure of mcon : 0.03um") +mconnotace.not(m1).output("m1.4", "m1.4 : mcon periphery must be enclosed by m1") +in_cell6 = layout(source.cell_obj).select("-*", "+s8cell_ee_plus_sseln_a", "+s8cell_ee_plus_sseln_b", "+s8cell_ee_plus_sselp_a", "+s8cell_ee_plus_sselp_b", "+s8fpls_pl8", "+s8fs_cmux4_fm") +in_cell6_m1 = in_cell6.input(m1_wildcard) +in_cell6_m1.enclosing(mcon, 0.005, euclidian).output("m1.4a", "m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um") + +in_cell6_m1.not(m1).output('m1.4a_a', 'm1.4a_a : mcon periph must be enclosed by met1 for specific cells') + +m1.with_area(0..0.083).output("m1.6", "m1.6 : min. m1 area : 0.083um²") + +m1.holes.with_area(0..0.14).output("m1.7", "m1.7 : min. m1 with holes area : 0.14um²") +if option_FLOATING_MET + m1.not_interacting(via.or(mcon)).output("m1.x", "floating met1, must interact with via1") +end + +if backend_flow = AL + #Could flag false positive, fix would be to add .rectangles for m1 + mconnotace_edges_with_less_enclosure_m1 = m1.enclosing(mconnotace, 0.06, projection).second_edges + error_corners_m1 = mconnotace_edges_with_less_enclosure_m1.width(angle_limit(100.0), 1.dbu) + mconnotace_interact_m1 = mconnotace.interacting(error_corners_m1.polygons(1.dbu)) + mconnotace_interact_m1.output("m1.5", "m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um") +end +log("END: 68/20 (m1)") + +# via +log("START: 68/44 (via)") +if backend_flow = AL + if option_SEAL + ringVIA = via.drc(with_holes > 0) + rectVIA = via.not(ringVIA) + else + rectVIA = via + end + + via_not_mt = rectVIA.not(areaid_mt) + + via_not_mt.non_rectangles.output("via.1a", "via.1a : via outside of moduleCut should be rectangular") + via_not_mt.width(0.15, euclidian).output("via.1a_a", "via.1a_a : min. width of via outside of moduleCut : 0.15um") + # via_not_mt.edges.without_length(nil, 0.15 + 1.dbu).output("via.1a_b", "via.1a_b : maximum length of via : 0.15um") + via_not_mt.drc(length > 0.15).output("via.1a_b", "via.1a_b : maximum length of via : 0.15um") + + via.space(0.17, euclidian).output("via.2", "via.2 : min. via spacing : 0.17um") + + if option_SEAL + ringVIA.width(0.2, euclidian).output("via.3", "via.3 : min. width of ring-shaped via : 0.2um") + ringVIA.drc(width >= 0.205).output("via.3_a", "via.3_a : max. width of ring-shaped via : 0.205um") + ringVIA.not(areaid_sl).output("via.3_b", "via.3_b: ring-shaped via must be enclosed by areaid_sl") + end + + m1.edges.enclosing(rectVIA.drc(width == 0.15), 0.055, euclidian).output("via.4a", "via.4a : min. m1 enclosure of 0.15um via : 0.055um") + rectVIA.squares.drc(width == 0.15).not(m1).output("via.4a_a", "via.4a_a : 0.15um via must be enclosed by met1") + + via1_edges_with_less_enclosure_m1 = m1.edges.enclosing(rectVIA.drc(width == 0.15), 0.085, projection).second_edges + error_corners_via1 = via1_edges_with_less_enclosure_m1.width(angle_limit(100.0), 1.dbu) + via2_interact = via.interacting(error_corners_via1.polygons(1.dbu)) + via2_interact.output("via.5a", "via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um") + +end +log("END: 68/44 (via)") + +# m2 +log("START: 69/20 (m2)") +m2.width(0.14, euclidian).output("m2.1", "m2.1 : min. m2 width : 0.14um") + +huge_m2 = m2.sized(-1.5).sized(1.5).snap(0.005) & m2 +non_huge_m2 = m2.edges - huge_m2 +huge_m2 = huge_m2.edges.outside_part(m2.merged) +via_outside_periphery = via.not(areaid_ce) + +non_huge_m2.space(0.14, euclidian).output("m2.2", "m2.2 : min. m2 spacing : 0.14um") + +(huge_m2.separation(non_huge_m2, 0.28, euclidian) + huge_m2.space(0.28, euclidian)).output("m2.3ab", "m2.3ab : min. 3um.m2 spacing m2 : 0.28um") + +m2.with_area(0..0.0676).output("m2.6", "m2.6 : min. m2 area : 0.0676um²") +m2.holes.with_area(0..0.14).output("m2.7", "m2.7 : min. m2 holes area : 0.14um²") +if option_FLOATING_MET + m2.not_interacting(via.or(via2)).output("m2.x", "floating met2, must interact with via1 or via2") +end +if backend_flow = AL + m2.enclosing(via_outside_periphery, 0.055, euclidian).output("m2.4", "m2.4 : min. m2 enclosure of via : 0.055um") + via_outside_periphery.not(m2).output("m2.4_a", "m2.4_a : via in periphery must be enclosed by met2") + via_edges_with_less_enclosure_m2 = m2.enclosing(via, 0.085, projection).second_edges + error_corners = via_edges_with_less_enclosure_m2.width(angle_limit(100.0), 1.dbu) + via_interact = via.interacting(error_corners.polygons(1.dbu)) + via_interact.output("m2.5", "m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um") + +end +log("END: 69/20 (m2)") + +# via2 +log("START: 69/44 (via2)") +if backend_flow = AL + if option_SEAL + ringVIA2 = via2.drc(with_holes > 0) + rectVIA2 = via2.not(ringVIA2) + else + rectVIA2 = via2 + end + + via2_not_mt = rectVIA2.not(areaid_mt) + via2_not_mt.non_rectangles.output("via2.1a", "via2.1a : via2 outside of moduleCut should be rectangular") + via2_not_mt.width(0.2, euclidian).output("via2.1a_a", "via2.1a_a : min. width of via2 outside of moduleCut : 0.2um") + via2_not_mt.edges.without_length(nil, 0.2 + 1.dbu).output("via2.1a_b", "via2.1a_b : maximum length of via2 : 0.2um") + via2.space(0.2, euclidian).output("via2.2", "via2.2 : min. via2 spacing : 0.2um") + + if option_SEAL + ringVIA2.width(0.2, euclidian).output("via2.3", "via2.3 : min. width of ring-shaped via2 : 0.2um") + ringVIA2.drc(width >= 0.205).output("via2.3_a", "via2.3_a : max. width of ring-shaped via2 : 0.205um") + ringVIA2.not(areaid_sl).output("via2.3_b", "via2.3_b: ring-shaped via2 must be enclosed by areaid_sl") + end + + m2.enclosing(via2, 0.04, euclidian).output("via2.4", "via2.4 : min. m2 enclosure of via2 : 0.04um") + via2.not(m2).output("via2.4_a", "via2.4_a : via must be enclosed by met2") + + via2_edges_with_less_enclosure = m2.enclosing(via2, 0.085, projection).second_edges + error_corners = via2_edges_with_less_enclosure.width(angle_limit(100.0), 1.dbu) + via2_interact = via2.interacting(error_corners.polygons(1.dbu)) + via2_interact.output("via2.5", "via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um") +end +log("END: 69/44 (via2)") + +# m3 +log("START: 70/20 (m3)") +m3.width(0.3, euclidian).output("m3.1", "m3.1 : min. m3 width : 0.3um") + +huge_m3 = m3.sized(-1.5).sized(1.5).snap(0.005) & m3 +non_huge_m3 = m3.edges - huge_m3 +huge_m3 = huge_m3.edges.outside_part(m3.merged) + +non_huge_m3.space(0.3, euclidian).output("m3.2", "m3.2 : min. m3 spacing : 0.3um") + +m3.with_area(0..0.240).output("m3.6", "m3.6 : min. m3 area : 0.240um²") + +(huge_m3.separation(non_huge_m3, 0.4, euclidian) + huge_m3.space(0.4, euclidian)).output("m3.3cd", "m3.3cd : min. 3um.m3 spacing m3 : 0.4um") +if option_FLOATING_MET + m3.not_interacting(via2.or(via3)).output("m3.x", "floating met3, must interact with via2 or via3") +end +if backend_flow = AL + m3.enclosing(via2, 0.065, euclidian).output("m3.4", "m3.4 : min. m3 enclosure of via2 : 0.065um") + via2.not(m3).output("m3.4_a", "m3.4_a : via2 must be enclosed by met3") +end +log("END: 70/20 (m3)") + +# via3 +log("START: 70/44 (via3)") +if backend_flow = AL + if option_SEAL + ringVIA3 = via3.drc(with_holes > 0) + rectVIA3 = via3.not(ringVIA3) + else + rectVIA3 = via3 + end + + via3_not_mt = rectVIA3.not(areaid_mt) + via3_not_mt.non_rectangles.output("via3.1", "via3.1 : via3 outside of moduleCut should be rectangular") + via3_not_mt.width(0.2, euclidian).output("via3.1_a", "via3.1_a : min. width of via3 outside of moduleCut : 0.2um") + via3_not_mt.edges.without_length(nil, 0.2 + 1.dbu).output("via3.1_b", "via3.1_b : maximum length of via3 : 0.2um") + + via3.space(0.2, euclidian).output("via3.2", "via3.2 : min. via3 spacing : 0.2um") + m3.enclosing(via3, 0.06, euclidian).output("via3.4", "via3.4 : min. m3 enclosure of via3 : 0.06um") + rectVIA3.not(m3).output("via3.4_a", "via3.4_a : non-ring via3 must be enclosed by met3") + + via_edges_with_less_enclosure = m3.enclosing(via3, 0.09, projection).second_edges + error_corners = via_edges_with_less_enclosure.width(angle_limit(100.0), 1.dbu) + via3_interact = via3.interacting(error_corners.polygons(1.dbu)) + via3_interact.output("via3.5", "via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um") +end +log("END: 70/44 (via3)") + +# m4 +log("START: 71/20 (m4)") +m4.width(0.3, euclidian).output("m4.1", "m4.1 : min. m4 width : 0.3um") + +huge_m4 = m4.sized(-1.5).sized(1.5).snap(0.005) & m4 +non_huge_m4 = m4.edges - huge_m4 +huge_m4 = huge_m4.edges.outside_part(m4.merged) + +non_huge_m4.space(0.3, euclidian).output("m4.2", "m4.2 : min. m4 spacing : 0.3um") + +m4.with_area(0..0.240).output("m4.4a", "m4.4a : min. m4 area : 0.240um²") + +(huge_m4.separation(non_huge_m4, 0.4, euclidian) + huge_m4.space(0.4, euclidian)).output("m4.5ab", "m4.5ab : min. 3um.m4 spacing m4 : 0.4um") +if option_FLOATING_MET + m4.not_interacting(via3.or(via4)).output("m4.x", "floating met3, must interact with via3 or via4") +end +if backend_flow = AL + m4.enclosing(via3, 0.065, euclidian).output("m4.3", "m4.3 : min. m4 enclosure of via3 : 0.065um") + via3.not(m4).output("m4.3_a", "m4.3_a : via3 must be enclosed by met4") +end +log("END: 71/20 (m4)") + +# via4 +log("START: 71/44 (via4)") +if option_SEAL + ringVIA4 = via4.drc(with_holes > 0) + rectVIA4 = via4.not(ringVIA4) +else + rectVIA4 = via4 +end + +via4_not_mt = rectVIA4.not(areaid_mt) +via4_not_mt.non_rectangles.output("via4.1", "via4.1 : via4 outside of moduleCut should be rectangular") +rectVIA4.width(0.8, euclidian).output("via4.1_a", "via4.1_a : min. width of via4 outside of moduleCut : 0.8um") +rectVIA4.drc(length > 0.8).output("via4.1_b", "via4.1_b : maximum length of via4 : 0.8um") + +via4.space(0.8, euclidian).polygons.output("via4.2", "via4.2 : min. via4 spacing : 0.8um") + +if option_SEAL + ringVIA4.width(0.8, euclidian).output("via4.3", "via4.3 : min. width of ring-shaped via4 : 0.8um") + ringVIA4.drc(width >= 0.805).output("via4.3_a", "via4.3_a : max. width of ring-shaped via4 : 0.805um") + ringVIA4.not(areaid_sl).output("via4.3_b", "via4.3_b: ring-shaped via4 must be enclosed by areaid_sl") +end + +m4.enclosing(via4, 0.19, euclidian).output("via4.4", "via4.4 : min. m4 enclosure of via4 : 0.19um") +rectVIA4.not(m4).output("via4.4_a", "via4.4_a : m4 must enclose all via4") +log("END: 71/44 (via4)") + +# m5 +log("START: 72/20 (m5)") +m5.width(1.6, euclidian).output("m5.1", "m5.1 : min. m5 width : 1.6um") + +m5.space(1.6, euclidian).output("m5.2", "m5.2 : min. m5 spacing : 1.6um") + +m5.enclosing(via4, 0.31, euclidian).output("m5.3", "m5.3 : min. m5 enclosure of via4 : 0.31um") +via4.not(m5).output("m5.3_a", "m5.3_a : via must be enclosed by m5") +if option_FLOATING_MET + m5.not_interacting(via4).output("m5.x", "floating met5, must interact with via4") +end +m5.with_area(0..4.0).output("m5.4", "m5.4 : min. m5 area : 4.0um²") +log("END: 72/20 (m5)") + +# pad +log("START: 76/20 (pad)") +pad.space(1.27, euclidian).output("pad.2", "pad.2 : min. pad spacing : 1.27um") +log("END: 76/20 (pad)") + +end #option_BEOL + +if option_FEOL +log("option_FEOL section") + +# hvi +log("START: 75/20 (hvi)") +hvi_peri = hvi.not(areaid_ce) +hvi_peri.width(0.6, euclidian).output("hvi.1", "hvi.1 : min. hvi width : 0.6um") +hvi_peri.space(0.7, euclidian).output("hvi.2a", "hvi.2a : min. hvi spacing : 0.7um") +log("END: 75/20 (hvi)") + +# hvntm +log("START: 125/20 (hvntm)") +hvntm_peri = hvntm.not(areaid_ce) +hvntm_peri.width(0.7, euclidian).output("hvntm.1", "hvntm.1 : min. hvntm width : 0.7um") +hvntm_peri.space(0.7, euclidian).output("hvntm.2", "hvntm.2 : min. hvntm spacing : 0.7um") +log("END: 125/20 (hvntm)") + +end #option_FEOL + + +if option_OFFGRID +log("option_OFFGRID-ANGLES section") + +dnwell.ongrid(0.005).output("dnwell_option_OFFGRID", "x.1b : option_OFFGRID vertex on dnwell") +dnwell.with_angle(0 .. 45).output("dnwell_angle", "x.3a : non 45 degree angle dnwell") +nwell.ongrid(0.005).output("nwell_option_OFFGRID", "x.1b : option_OFFGRID vertex on nwell") +nwell.with_angle(0 .. 45).output("nwell_angle", "x.3a : non 45 degree angle nwell") +pwbm.ongrid(0.005).output("pwbm_option_OFFGRID", "x.1b : option_OFFGRID vertex on pwbm") +pwbm.with_angle(0 .. 45).output("pwbm_angle", "x.3a : non 45 degree angle pwbm") +pwde.ongrid(0.005).output("pwde_option_OFFGRID", "x.1b : option_OFFGRID vertex on pwde") +pwde.with_angle(0 .. 45).output("pwde_angle", "x.3a : non 45 degree angle pwde") +hvtp.ongrid(0.005).output("hvtp_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvtp") +hvtp.with_angle(0 .. 45).output("hvtp_angle", "x.3a : non 45 degree angle hvtp") +hvtr.ongrid(0.005).output("hvtr_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvtr") +hvtr.with_angle(0 .. 45).output("hvtr_angle", "x.3a : non 45 degree angle hvtr") +lvtn.ongrid(0.005).output("lvtn_option_OFFGRID", "x.1b : option_OFFGRID vertex on lvtn") +lvtn.with_angle(0 .. 45).output("lvtn_angle", "x.3a : non 45 degree angle lvtn") +ncm.ongrid(0.005).output("ncm_option_OFFGRID", "x.1b : option_OFFGRID vertex on ncm") +ncm.with_angle(0 .. 45).output("ncm_angle", "x.3a : non 45 degree angle ncm") +diff.ongrid(0.005).output("diff_option_OFFGRID", "x.1b : option_OFFGRID vertex on diff") +tap.ongrid(0.005).output("tap_option_OFFGRID", "x.1b : option_OFFGRID vertex on tap") +diff.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("diff_angle", "x.2 : non 90 degree angle diff") +diff.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("diff_angle", "x.2c : non 45 degree angle diff") +tap.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("tap_angle", "x.2 : non 90 degree angle tap") +tap.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("tap_angle", "x.2c : non 45 degree angle tap") +tunm.ongrid(0.005).output("tunm_option_OFFGRID", "x.1b : option_OFFGRID vertex on tunm") +tunm.with_angle(0 .. 45).output("tunm_angle", "x.3a : non 45 degree angle tunm") +poly.ongrid(0.005).output("poly_option_OFFGRID", "x.1b : option_OFFGRID vertex on poly") +poly.with_angle(0 .. 90).output("poly_angle", "x.2 : non 90 degree angle poly") +rpm.ongrid(0.005).output("rpm_option_OFFGRID", "x.1b : option_OFFGRID vertex on rpm") +rpm.with_angle(0 .. 45).output("rpm_angle", "x.3a : non 45 degree angle rpm") +npc.ongrid(0.005).output("npc_option_OFFGRID", "x.1b : option_OFFGRID vertex on npc") +npc.with_angle(0 .. 45).output("npc_angle", "x.3a : non 45 degree angle npc") +nsdm.ongrid(0.005).output("nsdm_option_OFFGRID", "x.1b : option_OFFGRID vertex on nsdm") +nsdm.with_angle(0 .. 45).output("nsdm_angle", "x.3a : non 45 degree angle nsdm") +psdm.ongrid(0.005).output("psdm_option_OFFGRID", "x.1b : option_OFFGRID vertex on psdm") +psdm.with_angle(0 .. 45).output("psdm_angle", "x.3a : non 45 degree angle psdm") +licon.ongrid(0.005).output("licon_option_OFFGRID", "x.1b : option_OFFGRID vertex on licon") +licon.with_angle(0 .. 90).output("licon_angle", "x.2 : non 90 degree angle licon") +li.ongrid(0.005).output("li_option_OFFGRID", "x.1b : option_OFFGRID vertex on li") +li.with_angle(0 .. 45).output("li_angle", "x.3a : non 45 degree angle li") +mcon.ongrid(0.005).output("ct_option_OFFGRID", "x.1b : option_OFFGRID vertex on mcon") +mcon.with_angle(0 .. 90).output("ct_angle", "x.2 : non 90 degree angle mcon") +vpp.ongrid(0.005).output("vpp_option_OFFGRID", "x.1b : option_OFFGRID vertex on vpp") +vpp.with_angle(0 .. 45).output("vpp_angle", "x.3a : non 45 degree angle vpp") +m1.ongrid(0.005).output("m1_option_OFFGRID", "x.1b : option_OFFGRID vertex on m1") +m1.with_angle(0 .. 45).output("m1_angle", "x.3a : non 45 degree angle m1") +via.ongrid(0.005).output("via_option_OFFGRID", "x.1b : option_OFFGRID vertex on via") +via.with_angle(0 .. 90).output("via_angle", "x.2 : non 90 degree angle via") +m2.ongrid(0.005).output("m2_option_OFFGRID", "x.1b : option_OFFGRID vertex on m2") +m2.with_angle(0 .. 45).output("m2_angle", "x.3a : non 45 degree angle m2") +via2.ongrid(0.005).output("via2_option_OFFGRID", "x.1b : option_OFFGRID vertex on via2") +via2.with_angle(0 .. 90).output("via2_angle", "x.2 : non 90 degree angle via2") +m3.ongrid(0.005).output("m3_option_OFFGRID", "x.1b : option_OFFGRID vertex on m3") +m3.with_angle(0 .. 45).output("m3_angle", "x.3a : non 45 degree angle m3") +via3.ongrid(0.005).output("via3_option_OFFGRID", "x.1b : option_OFFGRID vertex on via3") +via3.with_angle(0 .. 90).output("via3_angle", "x.2 : non 90 degree angle via3") +nsm.ongrid(0.005).output("nsm_option_OFFGRID", "x.1b : option_OFFGRID vertex on nsm") +nsm.with_angle(0 .. 45).output("nsm_angle", "x.3a : non 45 degree angle nsm") +m4.ongrid(0.005).output("m4_option_OFFGRID", "x.1b : option_OFFGRID vertex on m4") +m4.with_angle(0 .. 45).output("m4_angle", "x.3a : non 45 degree angle m4") +via4.ongrid(0.005).output("via4_option_OFFGRID", "x.1b : option_OFFGRID vertex on via4") +via4.with_angle(0 .. 90).output("via4_angle", "x.2 : non 90 degree angle via4") +m5.ongrid(0.005).output("m5_option_OFFGRID", "x.1b : option_OFFGRID vertex on m5") +m5.with_angle(0 .. 45).output("m5_angle", "x.3a : non 45 degree angle m5") +pad.ongrid(0.005).output("pad_option_OFFGRID", "x.1b : option_OFFGRID vertex on pad") +pad.with_angle(0 .. 45).output("pad_angle", "x.3a : non 45 degree angle pad") +mf.ongrid(0.005).output("mf_option_OFFGRID", "x.1b : option_OFFGRID vertex on mf") +mf.with_angle(0 .. 90).output("mf_angle", "x.2 : non 90 degree angle mf") +hvi.ongrid(0.005).output("hvi_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvi") +hvi.with_angle(0 .. 45).output("hvi_angle", "x.3a : non 45 degree angle hvi") +hvntm.ongrid(0.005).output("hvntm_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvntm") +hvntm.with_angle(0 .. 45).output("hvntm_angle", "x.3a : non 45 degree angle hvntm") +vhvi.ongrid(0.005).output("vhvi_option_OFFGRID", "x.1b : option_OFFGRID vertex on vhvi") +vhvi.with_angle(0 .. 45).output("vhvi_angle", "x.3a : non 45 degree angle vhvi") +uhvi.ongrid(0.005).output("uhvi_option_OFFGRID", "x.1b : option_OFFGRID vertex on uhvi") +uhvi.with_angle(0 .. 45).output("uhvi_angle", "x.3a : non 45 degree angle uhvi") +pwell_rs.ongrid(0.005).output("pwell_rs_option_OFFGRID", "x.1b : option_OFFGRID vertex on pwell_rs") +pwell_rs.with_angle(0 .. 45).output("pwell_rs_angle", "x.3a : non 45 degree angle pwell_rs") +areaid_re.ongrid(0.005).output("areaid_re_option_OFFGRID", "x.1b : option_OFFGRID vertex on areaid.re") + +end #option_OFFGRID +logger.info(" ") +logger.info("Cell exclusion list:") +logger.info(" rule | cell") +logger.info(" nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram") +logger.info(" nsd.1 | sram") +logger.info(" nsd.2 | sram") +logger.info(" psd.1 | sram") +logger.info(" psd.2 | sram") +logger.info(" ") +logger.info("release #{release}") diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/drc_sky130.lydrc b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/drc_sky130.lydrc new file mode 100755 index 000000000..68a49f4bc --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/drc_sky130.lydrc @@ -0,0 +1,878 @@ + + + + + drc + + + + false + false + + true + drc_scripts + tools_menu.drc.end + dsl + drc-dsl-xml + # +# DRC for SKY130 according to : +# https://skywater-pdk.readthedocs.io/en/latest/rules/periphery.html +# https://skywater-pdk.readthedocs.io/en/latest/rules/layers.html +# +# Distributed under GNU GPLv3: https://www.gnu.org/licenses/ +# +# History : +# 2020-10-04 : v1.0 : initial release +# +########################################################################################## +tstart = Time.now + +# optionnal for a batch launch : klayout -b -rd input=my_layout.gds -rd report=sky130_drc.txt -r drc_sky130.drc +if $input + source($input) +end + +if $report +# report($report) + report("SKY130 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), $report)) +else + report("SKY130 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "sky130_drc.txt")) +end + +AL = true # do not change +CU = false # do not change +# choose betwen only one of AL or CU back-end flow here : +backend_flow = AL + +# enable / disable rule groups +FEOL = true # front-end-of-line checks +BEOL = true # back-end-of-line checks +OFFGRID = true # manufacturing grid/angle checks + +# klayout setup +######################## +# use a tile size of 1mm - not used in deep mode- +tiles(1000.um) +# use a tile border of 10 micron: +tile_borders(1.um) +#no_borders + +# hierachical +deep + +# use 4 cpu cores +threads(4) +# if more inof is needed, set true +verbose(false) + +# layers definitions +######################## +diff = input(65, 20) +tap = polygons(65, 44) +nwell = polygons(64, 20) +dnwell = polygons(64, 18) +pwbm = polygons(19, 44) +pwde = polygons(124, 20) +natfet = polygons(124, 21) +hvtr = polygons(18, 20) +hvtp = polygons(78, 44) +ldntm = polygons(11, 44) +hvi = polygons(75, 20) +tunm = polygons(80, 20) +lvtn = polygons(125, 44) +poly = polygons(66, 20) +hvntm = polygons(125, 20) +nsdm = polygons(93, 44) +psdm = polygons(94, 20) +rpm = polygons(86, 20) +urpm = polygons(79, 20) +npc = polygons(95, 20) +licon = polygons(66, 44) +li = input(67, 20) +mcon = polygons(67, 44) +m1 = polygons(68, 20) +via = polygons(68, 44) +m2 = polygons(69, 20) +via2 = polygons(69, 44) +m3 = polygons(70, 20) +via3 = polygons(70, 44) +m4 = polygons(71, 20) +via4 = polygons(71, 44) +m5 = polygons(72, 20) +pad = polygons(76, 20) +nsm = polygons(61, 20) +capm = polygons(89, 44) +cap2m = polygons(97, 44) +vhvi = polygons(74, 21) +uhvi = polygons(74, 22) +npn = polygons(82, 20) +inductor = polygons(82, 24) +vpp = polygons(82, 64) +pnp = polygons(82, 44) +lvs_prune = polygons(84, 44) +ncm = polygons(92, 44) +padcenter = polygons(81, 20) +mf = polygons(76, 44) +areaid_sl = polygons(81, 1) +areaid_ce = polygons(81, 2) +areaid_fe = polygons(81, 3) +areaid_sc = polygons(81, 4) +areaid_sf = polygons(81, 6) +areaid_sw = polygons(81, 7) +areaid_sr = polygons(81, 8) +areaid_mt = polygons(81, 10) +areaid_dt = polygons(81, 11) +areaid_ft = polygons(81, 12) +areaid_ww = polygons(81, 13) +areaid_ld = polygons(81, 14) +areaid_ns = polygons(81, 15) +areaid_ij = polygons(81, 17) +areaid_zr = polygons(81, 18) +areaid_ed = polygons(81, 19) +areaid_de = polygons(81, 23) +areaid_rd = polygons(81, 24) +areaid_dn = polygons(81, 50) +areaid_cr = polygons(81, 51) +areaid_cd = polygons(81, 52) +areaid_st = polygons(81, 53) +areaid_op = polygons(81, 54) +areaid_en = polygons(81, 57) +areaid_en20 = polygons(81, 58) +areaid_le = polygons(81, 60) +areaid_hl = polygons(81, 63) +areaid_sd = polygons(81, 70) +areaid_po = polygons(81, 81) +areaid_it = polygons(81, 84) +areaid_et = polygons(81, 101) +areaid_lvt = polygons(81, 108) +areaid_re = polygons(81, 125) +areaid_ag = polygons(81, 79) +poly_rs = polygons(66, 13) +diff_rs = polygons(65, 13) +pwell_rs = polygons(64, 13) +li_rs = polygons(67, 13) +cfom = polygons(22, 20) + + +# Define a new custom function that selects polygons by their number of holes: +# It will return a new layer containing those polygons with min to max holes. +# max can be nil to omit the upper limit. +class DRC::DRCLayer + def with_holes(min, max) + new_data = RBA::Region::new + self.data.each do |p| + if p.holes >= (min || 0) && (!max || p.holes <= max) + new_data.insert(p) + end + end + DRC::DRCLayer::new(@engine, new_data) + end +end + +# DRC section +######################## +info("DRC section") + +if FEOL +info("FEOL section") +gate = diff & poly + +# dnwell +dnwell.width(3.0, euclidian).output("dnwell.2", "dnwell.2 : min. dnwell width : 3.0um") +dnwell.not(uhvi).not(areaid_po).isolated(6.3, euclidian).output("dnwell.3", "dnwell.3 : min. dnwell spacing : 6.3um") +dnwell.and(pnp).output("dnwell.4", "dnwell.4 : dnwell must not overlap pnp") +dnwell.and(psdm).edges.not(psdm.edges).output("dnwell.5", "p+ must not straddle dnwell") +# dnwell.6 rue not coded + +# nwell +nwell.width(0.84, euclidian).output("nwell.1", "nwell.1 : min. nwell width : 0.84um") +nwell.space(1.27, euclidian).output("nwell.2a", "nwell.2a : min. nwell spacing (merged if less) : 1.27um") +# rule nwell.4 is suitable for digital cells +#nwell.not(uhvi).not(areaid_en20).not_interacting(tap.and(licon).and(li)).output("nwell.4", "nwell4 : all nwell exempt inside uhvi must contain a n+tap") +nwell.enclosing(dnwell.not(uhvi).not(areaid_po), 0.4, euclidian).output("nwell.5", "nwell.5 : min. nwell enclosing dnwell exempt unside uhvi : 0.4um") +dnwell.enclosing(nwell.not(uhvi), 1.03, euclidian).output("nwell.6", "nwell.6 : min. dnwell enclosing nwell exempt unside uhvi : 1.03um") +dnwell.separation(nwell, 4.5, euclidian).output("nwell.7", "nwell.7 : min. dnwell separation nwell : 4.5um") + +# pwbm +pwbm.not(uhvi).output("pwbm", "pwbm must be inside uhvi") +dnwell.and(uhvi).edges.not(pwbm).output("pwbm.4", "pwbm.4 : dnwell inside uhvi must be enclosed by pwbm") + +# pwde +pwde.not(pwbm).output("pwdem.3", "pwdem.3 : pwde must be inside pwbm") +pwde.not(uhvi).output("pwdem.4", "pwdem.4 : pwde must be inside uhvi") +pwde.not(dnwell).output("pwdem.5", "pwdem.5 : pwde must be inside dnwell") + +# hvtp +#hvtp.not(nwell).output("hvtp", "hvtp must inside nwell") +hvtp.width(0.38, euclidian).output("hvtp.1", "hvtp.1 : min. hvtp width : 0.38um") +hvtp.space(0.38, euclidian).output("hvtp.2", "hvtp.2 : min. hvtp spacing : 0.38um") +hvtp.enclosing(gate.and(psdm), 0.18, euclidian).output("hvtp.3", "hvtp.3 : min. hvtp enclosure of pfet gate : 0.18um") +hvtp.separation(gate.and(psdm), 0.18, euclidian).output("hvtp.4", "hvtp.4 : min. hvtp spacing pfet gate: 0.18um") +hvtp.with_area(0..0.265).output("hvtp.5", "hvtp.5 : min. hvtp area : 0.265um²") + +# hvtr +hvtr.width(0.38, euclidian).output("hvtr.1", "hvtr.1 : min. hvtr width : 0.38um") +hvtr.isolated(0.38, euclidian).output("hvtr.2", "hvtr.2 : min. hvtr spacing : 0.38um") + +# lvtn +lvtn.width(0.38, euclidian).output("lvtn.1", "lvtn.1 : min. lvtn width : 0.38um") +lvtn.space(0.38, euclidian).output("lvtn.2", "lvtn.2 : min. lvtn spacing : 0.38um") +lvtn.separation(diff.and(poly).not(uhvi), 0.18, euclidian).output("lvtn.3a", "lvtn.3a : min. lvtn spacing to gate : 0.18um") +lvtn.separation(diff.and(nwell).not(poly), 0.235, projection).output("lvtn.3b", "lvtn.3b : min. lvtn spacing to pfet s/d : 0.18um") +lvtn.enclosing(gate.not(uhvi), 0.18, euclidian).output("lvtn.4b", "lvtn.4b : min. lvtn enclosing to gate : 0.18um") +lvtn.separation(hvtp, 0.38, euclidian).output("lvtn.9", "lvtn.9 : min. lvtn spacing hvtp : 0.38um") +nwell.not_interacting(gate.and(nwell.not(hvi).not(areaid_ce))).enclosing(lvtn.not(uhvi), 0.18, euclidian).polygons.without_area(0).output("lvtn.4b", "lvtn.4b : min. lvtn enclosure of gate : 0.18um") +lvtn.separation(nwell.inside(areaid_ce), 0.38, euclidian).output("lvtn.12", "lvtn.12 : min. lvtn spacing nwell inside areaid.ce : 0.38um") +lvtn.with_area(0..0.265).output("lvtn.13", "lvtn.13 : min. lvtn area : 0.265um²") + +# ncm +ncm.and(tap.and(nwell).or(diff.not(nwell))).output("ncm.x.3", "ncm.x.3 : ncm must not overlap n+diff") +ncm.width(0.38, euclidian).output("ncm.1", "ncm.1 : min. ncm width : 0.38um") +ncm.space(0.38, euclidian).output("ncm.2", "ncm.2 : min. ncm spacing manual merge if smaller : 0.38um") +ncm.enclosing(diff.and(nwell), 0.18, euclidian).output("ncm.3", "ncm.3 : min. ncm enclosure of p+diff : 0.18um") +ncm.separation(lvtn.and(diff), 0.23, euclidian).output("ncm.5", "ncm.5 : min. ncm spacing lvtn diff : 0.23um") +ncm.separation(diff.not(nwell), 0.2, euclidian).output("ncm.6", "ncm.6 : min. ncm spacing nfet : 0.2um") +ncm.with_area(0..0.265).output("ncm.7", "ncm.13 : min. ncm area : 0.265um²") + +# diff-tap +difftap = diff + tap +difftap.width(0.15, euclidian).output("difftap.1", "difftap.1 : min. difftap width : 0.15um") +not_in_cell1 = layout(source.cell_obj).select("s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b" , "-s8fpls_pl8", "-s8fpls_rdrv4" , "-s8fpls_rdrv4f", "-s8fpls_rdrv8") +not_in_cell1_diff = not_in_cell1.input(65, 20) +not_in_cell1_diff.not(areaid_sc).not(poly).edges.and(gate.edges).with_length(0,0.42).output("difftap.2", "difftap.2: min. gate (exempt areaid.sc) width : 0.42um") +diff.and(areaid_sc).not(poly).edges.and(gate.edges).with_length(0,0.36).output("difftap.2", "difftap.2: min. gate inside areaid.sc width : 0.36um") +difftap.space(0.27, euclidian).output("difftap.3", "difftap.3 : min. difftap spacing : 0.27um") +tap.edges.and(diff.edges).with_length(0,0.29).output("difftap.4", "difftap.4 : min. tap bound by diffusion : 0.29um") +tap.edges.and(diff.edges).space(0.4, projection).output("difftap.5", "difftap.5 : min. tap bound by 2 diffusions : 0.4um") +(tap.edges.and(diff.edges)).extended(0.01, 0.01, 0, 0, false).not(tap.and(diff)).and(diff.or(tap)).output("difftap.6", "difftap.6 : diff and tap not allowed to extend beyong their abutting ege") +tap.edges.not_interacting(diff.edges).separation(diff.edges, 0.13, euclidian).output("difftap.7", "difftap.7 : min. diff/tap spacing to non-coincident diff edge : 0.13um") +diff.edges.not_interacting(tap.edges).separation(tap.edges, 0.13, euclidian).output("difftap.7", "difftap.7 : min. diff/tap spacing to non-coincident tap edge : 0.13um") +nwell.enclosing(diff.not(uhvi).and(psdm), 0.18, euclidian).output("difftap.8", "difftap.8 : min. p+diff enclosure by nwell : 0.18um") +diff.not(uhvi).and(nsdm).separation(nwell, 0.34, euclidian).output("difftap.9", "difftap.9 : min. n+diff spacing to nwell : 0.34um") +nwell.enclosing(tap.not(uhvi).and(nsdm), 0.18, euclidian).output("difftap.10", "difftap.10 : min. n+tap enclosure by nwell : 0.18um") +tap.not(uhvi).and(psdm).separation(nwell, 0.13, euclidian).output("difftap.11", "difftap.11 : min. p+tap spacing to nwell : 0.13um") + +# tunm +tunm.width(0.41, euclidian).output("tunm.1", "tunm.1 : min. tunm width : 0.41um") +tunm.isolated(0.5, euclidian).output("tunm.2", "tunm.2 : min. tunm spacing : 0.5um") +tunm.enclosing(gate, 0.095, euclidian).output("tunm.3", "tunm.3 : min. tunm beyond gate : 0.095um") +tunm.separation(gate.not_interacting(tunm), 0.095, euclidian).output("tunm.4", "tunm.4 : min. tunm spacing to gate outside tunm: 0.095um") +gate.and(tunm).edges.not(gate.edges).output("tunm.5", "tunm.5 : gate must not straddle tunm") +tunm.not(dnwell).output("tunm.6a", "tunm.6a : tunm not allowed outside dnwell") +tunm.with_area(0..0.672).output("tunm.7", "tunm.7 : min. tunm area : 0.672um²") + +# poly +poly.width(0.15, euclidian).output("poly.1a", "poly.1a : min. poly width : 0.15um") +poly.not(diff).edges.and(gate.and(lvtn).edges).space(0.35, euclidian).output("poly.1b", "poly.1b: min. lvtn gate width : 0.35um") +poly.space(0.21, euclidian).output("poly.2", "poly.2 : min. poly spacing : 0.21um") +poly.and(rpm.or(urpm).or(poly_rs)).width(0.33, euclidian).output("poly.3", "poly.3 : min. poly resistor width : 0.33um") +poly.not(gate).separation(diff, 0.075, projection).polygons.without_area(0).output("poly.4", "poly.4 : min. poly on field spacing to diff : 0.075um") +poly.not(gate).separation(tap, 0.055, euclidian).output("poly.5", "poly.5 : min. poly on field spacing to tap : 0.055um") +gate.separation(tap, 0.3, projection).polygons.and(diff).output("poly.6", "poly.6 : min. gate spacing to tap : 0.3um") +diff.enclosing(gate, 0.25, projection).polygons.without_area(0).output("poly.7", "poly.7 : min. source/drain length : 0.25um") +poly.enclosing(gate, 0.13, projection).polygons.without_area(0).output("poly.8", "poly.8 : min. poly extention gate (endcap) : 0.13um") +poly.and(rpm.or(urpm).or(poly_rs)).separation(poly.or(difftap), 0.48, euclidian).polygons.without_area(0).output("poly.9", "poly.9 : min. poly resistor space to poly or diff/tap : 0.48um") +diff.merged.edges.end_segments(0.01).and(poly).output("poly.10", "poly.10 : poly must not overlap diff corner") +gate.with_angle(0 .. 90).output("poly.11", "poly.11 : non 90 degree angle gate") +not_in_cell3 = layout(source.cell_obj).select("s8fgvr_n_fg2") +not_in_cell3_poly = not_in_cell3.input(66, 20) +not_in_cell3_poly.not(hvi).not(nwell.not(hvi)).and(tap).output("poly.12", "poly.12 : poly must not overlap tap") +poly.and(diff_rs).output("poly.15", "poly.15 : poly must not overlap diff resistor") + +# rpm +rpm.width(1.27, euclidian).output("rpm.1a", "rpm.1a : min. rpm width : 1.27um") +rpm.space(0.84, euclidian).output("rpm.2", "rpm.2 : min. rpm spacing : 0.84um") +rpm.enclosing(poly.and(poly_rs).and(psdm), 0.2, euclidian).output("rpm.3", "rpm.3 : min. rpm enclosure of poly resistor : 0.2um") +psdm.enclosing(poly.and(poly_rs).and(rpm), 0.11, euclidian).output("rpm.4", "rpm.4 : min. psdm enclosure of poly resistor : 0.11um") +npc.enclosing(poly.and(poly_rs).and(rpm), 0.095, euclidian).output("rpm.5", "rpm.5 : min. npc enclosure of poly resistor : 0.095um") +rpm.separation(nsdm, 0.2, euclidian).output("rpm.6", "rpm.6 : min. rpm spacing nsdm: 0.2um") +rpm.separation(poly, 0.2, euclidian).output("rpm.7", "rpm.7 : min. rpm spacing poly: 0.2um") +rpm.and(poly).edges.not(poly.edges).output("rpm.8", "rpm.8 : poly must not straddle rpm") +poly.and(poly_rs).and(rpm).separation(hvntm, 0.185, euclidian).output("rpm.9", "rpm.9 : min. poly resistor spacing hvntm: 0.185um") +rpm.and(pwbm).output("rpm.10", "rpm.107 : min. rpm spacing pwbm: na") + +# varac +varac = poly & tap & (nwell - hvi) - areaid_ce +tap.not(poly).edges.and(varac.edges).space(0.18, euclidian).output("varac.1", "varac.1: min. varac channel length : 0.18um") +tap.and(poly).edges.and(varac.edges).space(1.0, euclidian).output("varac.2", "varac.2: min. varac channel wdth : 1.0um") +varac.separation(hvtp, 0.18, euclidian).output("varac.3", "varac.3: min. varac channel space to hvtp : 0.18um") +varac.separation(licon.and(tap), 0.25, euclidian).output("varac.4", "varac.4: min. varac channel space to licon on tap : 0.25um") +nwell.enclosing(poly.overlapping(varac), 0.15, euclidian).output("varac.5", "varac.5: min. nwell enclosure of poly overlapping varac channel : 0.15um") +tap.overlapping(varac).separation(difftap, 0.27, euclidian).polygons.without_area(0).output("varac.6", "varac.6: min. varac channel tap space to difftap : 0.27um") +nwell.overlapping(varac).and(diff.and(nwell)).output("varac.7", "varac.7: nwell overlapping varac channel must not overlap p+diff") + +# photo +photodiode = dnwell & areaid_po +photodiode.edges.without_length(3.0).output("photo.2", "photo.2 : minimum/maximum width of photodiode : 3.0um") +photodiode.space(5.0, euclidian).output("photo.3", "photo.3 : mini. photodiode spacing : 5.0um") +photodiode.separation(dnwell, 5.3, euclidian).output("photo.4", "photo.4 : mini. photodiode spacing to dnwell : 5.3um") +areaid_po.not(dnwell).output("photo.5.6", "photo.5.6 : photodiode edges must coincide areaid.po and enclosed by dnwell") +photodiode.not(tap.not(nwell).holes).output("photo.7", "photo.7 : photodiode must be enclosed by p+tap ring") +photodiode.and(nwell).edges.without_length(0.84).output("photo.8", "photo.8 : minimum/maximum width of nwell inside photodiode : 0.84um") +areaid_po.edges.and(photodiode.and(nwell).sized(1.08)).without_length(12.0).output("photo.9", "photo.9 : minimum/maximum enclosure of nwell by photodiode : 1.08um") +photodiode.and(tap).edges.without_length(0.41).output("photo.10", "photo.10 : minimum/maximum width of tap inside photodiode : 0.41um") + +# npc +npc.width(0.27, euclidian).output("npc.1", "npc.1 : min. npc width : 0.27um") +npc.space(0.27, euclidian).output("npc.2", "npc.2 : min. npc spacing, should be mnually merge if less : 0.27um") +npc.separation(gate, 0.09, euclidian).output("npc.4", "npc.4 : min. npc spacing to gate : 0.09um") + +# nsdm/psdm +npsdm = nsdm + psdm +nsdm.width(0.38, euclidian).output("nsdm.1", "nsdm.1 : min. nsdm width : 0.38um") +psdm.width(0.38, euclidian).output("psdm.1", "psdm.1 : min. psdm width : 0.38um") +nsdm.space(0.38, euclidian).output("n/psdm.1", "n/psdm.1 : min. nsdm spacing, should be mnually merge if less : 0.38um") +psdm.space(0.38, euclidian).output("n/psdm.1", "n/psdm.1 : min. psdm spacing, should be mnually merge if less : 0.38um") +npsdm.enclosing(diff, 0.125, euclidian).polygons.not(tap.sized(0.125)).output("n/psdm.5a", "n/psdm.5a : min. n/psdm enclosure diff except butting edge : 0.125um") +npsdm.enclosing(tap, 0.125, euclidian).polygons.not(diff.sized(0.125)).output("n/psdm.5b", "n/psdm.5b : min. n/psdm enclosure tap except butting edge : 0.125um") +tap.edges.and(diff.edges).not(npsdm).output("n/psdm.6", "n/psdm.6 : min. n/psdm enclosure of butting edge : 0.0um") +nsdm.and(difftap).separation(psdm.and(difftap), 0.13, euclidian).polygons.without_area(0).output("n/psdm.7", "n/psdm.7 : min. nsdm diff spacing to psdm diff except butting edge : 0.13um") +diff.and((nsdm.and(nwell)).or(psdm.not(nwell))).output("n/psdm.8", "n/psdm.8 : diff should be the opposite type of well/substrate underneath") +tap.and((nsdm.not(nwell)).or(psdm.and(nwell))).output("n/psdm.8", "n/psdm.8 : tap should be the same type of well/substrate underneath") +tap.and(diff).without_area(0).output("tap and diff", "tap and diff must not overlap") +nsdm.with_area(0..0.265).output("n/psdm.10a", "n/psdm.10a : min. nsdm area : 0.265um²") +psdm.with_area(0..0.265).output("n/psdm.10b", "n/psdm.10b : min. psdm area : 0.265um²") + +# licon +licon.not(poly.interacting(poly_rs)).edges.without_length(0.17).output("licon.1", "licon.1 : minimum/maximum width of licon : 0.17um") +licon.and(poly.interacting(poly_rs)).not_interacting((licon.and(poly.interacting(poly_rs)).edges.with_length(0.19)).or(licon.and(poly.interacting(poly_rs)).edges.with_length(2.0))).output("licon.1b/c", "licon.1b/c : minimum/maximum width/length of licon inside poly resistor : 2.0/0.19um") +licon.space(0.17, euclidian).output("licon.2", "licon.2 : min. licon spacing : 0.17um") +licon.and(poly.interacting(poly_rs)).edges.with_length(0.19).space(0.35, euclidian).output("licon.2b", "licon.2b : min. licon 0.19um edge on resistor spacing : 0.35um") +licon.interacting(licon.and(poly.interacting(poly_rs)).edges.with_length(2.0)).separation(licon.and(poly.interacting(poly_rs)), 0.51, euclidian).output("licon.2c", "licon.2c : min. licon 2.0um edge on resistor spacing : 0.51um") +licon.and(poly.interacting(poly_rs)).separation(licon.not(poly.interacting(poly_rs)), 0.51, euclidian).output("licon.2d", "licon.2d : min. licon on resistor spacing other licon : 0.51um") +# rule licon.3 not coded +licon.not(li).not(poly.or(diff).or(tap)).output("licon.4", "licon.4 : min. licon must overlap li and (poly or tap or diff) ") +diff.enclosing(licon, 0.04, euclidian).output("licon.5", "licon.5 : min. diff enclosure of licon : 0.04um") +tap.edges.and(diff.edges).separation(licon.and(tap).edges, 0.06, euclidian).output("licon.6", "licon.6 : min. abutting edge spacing to licon tap : 0.06um") +licon_edges_with_less_enclosure_tap = tap.enclosing(licon, 0.12, projection).second_edges +opposite1 = (licon.edges - licon_edges_with_less_enclosure_tap).width(0.17 + 1.dbu, projection).polygons +licon.not_interacting(opposite1).output("licon.7", "licon.7 : min. tap enclosure of licon by one of 2 opposite edges : 0.12um") +poly.enclosing(licon, 0.05, euclidian).output("licon.8", "licon.8 : min. poly enclosure of licon : 0.05um") +licon008 = licon.interacting(poly.enclosing(licon, 0.08, euclidian).polygons) +licon_edges_with_less_enclosure_poly = poly.enclosing(licon, 0.08, projection).second_edges +opposite2 = (licon.edges - licon_edges_with_less_enclosure_poly).width(0.17 + 1.dbu, projection).polygons +licon008.not_interacting(opposite2).output("licon.8a", "licon.8a : min. poly enclosure of licon by one of 2 opposite edges : 0.08um") +# rule licon.9 not coded +licon.and(tap.and(nwell.not(hvi))).separation(varac, 0.25, euclidian).output("licon.10", "licon.10 : min. licon spacing to varac channel : 0.25um") +not_in_cell4 = layout(source.cell_obj).select("-s8fs_gwdlvx4", "-s8fs_gwdlvx8", "-s8fs_hvrsw_x4", "-s8fs_hvrsw8", "-s8fs_hvrsw264", "-s8fs_hvrsw520", "-s8fs_rdecdrv", "-s8fs_rdec8”, “s8fs_rdec32", "-s8fs_rdec264", "-s8fs_rdec520") +not_in_cell4_licon = not_in_cell4.input(66, 44) +not_in_cell4_licon.and(diff.or(tap)).separation(gate.not(areaid_sc), 0.055, euclidian).output("licon.11", "licon.11 : min. licon spacing to gate : 0.055um") +licon.and(diff.or(tap)).separation(gate.and(areaid_sc), 0.05, euclidian).output("licon.11a", "licon.11a : min. licon spacing to gate inside areaid.sc : 0.05um") +in_cell4 = layout(source.cell_obj).select("+s8fs_gwdlvx4", "+s8fs_gwdlvx8", "+s8fs_hvrsw_x4", "+s8fs_hvrsw8", "+s8fs_hvrsw264", "+s8fs_hvrsw520") +in_cell4_licon = in_cell4.input(66, 44) +in_cell4_licon.and(diff.or(tap)).separation(gate, 0.04, euclidian).output("licon.11c", "licon.11c : min. licon spacing to gate for specific cells: 0.04um") +# rules 11.b , 11.d not coded +diff.interacting(gate).not(diff.interacting(gate).width(5.7, euclidian).polygons).output("licon.12", "licon.12 : max. sd width without licon : 5.7um") +licon.and(diff.or(tap)).separation(npc, 0.09, euclidian).output("licon.13", "licon.13 : min. difftap licon spacing to npc : 0.09um") +licon.and(poly).separation(diff.or(tap), 0.19, euclidian).output("licon.14", "licon.14 : min. poly licon spacing to difftap : 0.19um") +npc.enclosing(licon.and(poly), 0.1, euclidian).output("licon.15", "licon.15 : min. npc enclosure of poly-licon : 0.1um") +# rule licon.16 not applicable for the diff for the nmos of a nand gates or the pmos of a nor gates +#diff.not(gate).not_interacting(licon).output("licon.16", "licon.16 : diff must enclose one licon") +tap.not(uhvi).not_interacting(licon).output("licon.16", "licon.16 : tap must enclose one licon") +poly.and(tap).edges.not(tap.edges).output("licon.17", "licon.17 : tap must not straddle poly") +npc.not_interacting(licon.and(poly)).output("licon.18", "licon.18 : npc mut enclosed one poly-licon") + +# li +not_in_cell5 = layout(source.cell_obj).select("-s8rf2_xcmvpp_hd5_*") +not_in_cell5_li = not_in_cell5.input(67, 20) +not_in_cell5_li.width(0.17, euclidian).output("li.1", "li.1 : min. li width : 0.17um") +in_cell5 = layout(source.cell_obj).select("+s8rf2_xcmvpp_hd5_*") +in_cell5_li = in_cell5.input(67, 20) +in_cell5_li.width(0.14, euclidian).output("li.1a", "li.1a : min. li width for the cells s8rf2_xcmvpp_hd5_* : 0.14um") +# rule li.2 not coded +not_in_cell5_li.isolated(0.17, euclidian).output("li.3", "li.3 : min. li spacing : 0.17um") +in_cell5_li.space(0.14, euclidian).output("li.3a", "li.3a : min. li spacing for the cells s8rf2_xcmvpp_hd5_* : 0.14um") +licon08 = licon.interacting(li.enclosing(licon, 0.08, euclidian).polygons) +licon_edges_with_less_enclosure_li = li.enclosing(licon, 0.08, projection).second_edges +opposite3 = (licon.edges - licon_edges_with_less_enclosure_li).width(0.17 + 1.dbu, projection).polygons +licon08.not_interacting(opposite3).output("li.5", "li.5 : min. li enclosure of licon of 2 opposite edges : 0.08um") +li.with_area(0..0.0561).output("li.6", "li.6 : min. li area : 0.0561um²") + +# vpp +vpp.width(1.43, euclidian).output("vpp.1", "vpp.1 : min. vpp width : 1.43um") +# rules 1.b, 1.c not coded +vpp.and(poly.or(difftap)).output("vpp.3", "vpp.3 : vpp must not overlapp poly or diff or tap") +vpp.and(nwell).edges.not(vpp.edges).output("vpp.4", "vpp.4 : vpp must not straddle nwell") +vpp.and(dnwell).edges.not(vpp.edges).output("vpp.4", "vpp.4 : vpp must not straddle dnwell") +vpp.and(poly.or(li).or(m1).or(m2)).separation(poly.or(li).or(m1).or(m2), 1.5, euclidian).polygons.with_area(2.25,nil).output("vpp.5", "vpp.5 : min. vpp spacing to poly or li or m1 or m2 : 1.5um") +vpp.with_area(0..area(vpp.and(m3))*0.25).output("vpp.5a", "vpp.5a : max. m3 density in vpp : 0.25") +vpp.with_area(0..area(vpp.and(m4))*0.3).output("vpp.5b", "vpp.5b : max. m4 density in vpp : 0.3") +vpp.with_area(0..area(vpp.and(m5))*0.4).output("vpp.5c", "vpp.5c : max. m5 density in vpp : 0.4") +nwell.enclosing(vpp, 1.5, euclidian).output("vpp.8", "vpp.8 : nwell enclosure of vpp : 1.5") +vpp.separation(nwell, 1.5, euclidian).polygons.without_area(0).output("vpp.9", "vpp.9 : vpp spacing to nwell : 1.5") +# rule vpp.10 not coded +# rule vpp.11 not coded because moscap is not defined properly by any gds layer +# rules vpp.12a, 12b, 12c not coded because specific to one cell +if backend_flow = CU + m1.separation(vpp.and(m1), 0.16, euclidian).polygons.without_area(0).output("vpp.13", "vpp.13 : m1 spacing to m1inside vpp : 0.16") +end + +# CAPM +capm.width(1.0, euclidian).output("capm.1", "capm.1 : min. capm width : 1.0um") +capm.space(0.84, euclidian).output("capm.2a", "capm.2a : min. capm spacing : 0.84um") +m2.interacting(capm).isolated(1.2, euclidian).output("capm.2b", "capm.2b : min. capm spacing : 1.2um") +m2.enclosing(capm, 0.14, euclidian).output("capm.3", "capm.3 : min. m2 enclosure of capm : 0.14um") +capm.enclosing(via2, 0.14, euclidian).output("capm.4", "capm.4 : min. capm enclosure of via2 : 0.14um") +capm.separation(via2, 0.14, euclidian).output("capm.5", "capm.5 : min. capm spacing to via2 : 0.14um") +capm.sized(-20.0).sized(20.0).output("capm.6", "capm.6 : max. capm lenght/width : 20um") +capm.with_angle(0 .. 90).output("capm.7", "capm.7 : capm not rectangle") +capm.separation(via, 0.14, euclidian).polygons.without_area(0).output("capm.8", "capm.8 : min. capm spacing to via : 0.14um") +capm.and(nwell).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle nwell") +capm.and(diff).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle diff") +capm.and(tap).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle tap") +capm.and(poly).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle poly") +capm.and(li).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle li") +capm.and(m1).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle m1") +capm.separation(m2.not_interacting(capm), 0.14, euclidian).output("capm.11", "capm.11 : min. capm spacing to m2 not overlapping capm : 0.5um") + +end #FEOL + +if BEOL +info("BEOL section") + +# ct +mcon.edges.without_length(0.17).output("ct.1", "ct.1 : minimum/maximum width of mcon : 0.17um") +mcon.space(0.19, euclidian).output("ct.2", "ct.2 : min. mcon spacing : 0.19um") +# rule ct.3 not coded +mcon.not(li).output("ct.4", "ct.4 : mcon should covered by li") +if backend_flow = CU + li.interacting(li.and(m1).not(mcon).with_holes(1,10)).enclosing(mcon, 0.2, euclidian).output("ct.irdrop.1", "ct.irdrop.1 : min. li enclsoure of 1..10 mcon : 0.2um") + li.interacting(li.and(m1).not(mcon).with_holes(11,100)).enclosing(mcon, 0.3, euclidian).output("ct.irdrop.2", "ct.irdrop.2 : min. li enclsoure of 11..100 mcon : 0.3um") +end + +# m1 +huge_m1 = m1.sized(-1.5).sized(1.5) +m1.width(0.14, euclidian).output("m1.1", "m1.1 : min. m1 width : 0.14um") +m1.space(0.14, euclidian).output("m1.2", "m1.2 : min. m1 spacing : 0.14um") +huge_m1.separation(m1, 0.28, euclidian).output("m1.3ab", "m1.3ab : min. 3um.m1 spacing m1 : 0.28um") +not_in_cell6 = layout(source.cell_obj).select("-s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b", "-s8fpls_pl8", "-s8fs_cmux4_fm") +not_in_cell6_m1 = not_in_cell6.input(68, 20) +not_in_cell6_m1.enclosing(mcon, 0.03, euclidian).output("m1.4", "m1.4 : min. m1 enclosure of mcon : 0.03um") +in_cell6 = layout(source.cell_obj).select("+s8cell_ee_plus_sseln_a", "+s8cell_ee_plus_sseln_b", "+s8cell_ee_plus_sselp_a", "+s8cell_ee_plus_sselp_b", "+s8fpls_pl8", "+s8fs_cmux4_fm") +in_cell6_m1 = in_cell6.input(68, 20) +in_cell6_m1.enclosing(mcon, 0.005, euclidian).output("m1.4a", "m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um") +m1.with_area(0..0.083).output("m1.6", "m1.6 : min. m1 area : 0.083um²") +m1.holes.with_area(0..0.14).output("m1.7", "m1.7 : min. m1 holes area : 0.14um²") +if backend_flow = AL + mcon06 = mcon.interacting(poly.enclosing(m1, 0.06, euclidian).polygons) + mcon_edges_with_less_enclosure_m1 = m1.enclosing(mcon, 0.06, projection).second_edges + opposite4 = (mcon.edges - mcon_edges_with_less_enclosure_m1).width(0.17 + 1.dbu, projection).polygons + mcon06.not_interacting(opposite4).output("m1.5", "m1.5 : min. m1 enclosure of mcon of 2 opposite edges : 0.06um") + # rule m1.pd.1, rule m1.pd.2a, rule m1.pd.2b not coded +end +if bakend_flow = CU + m1.sized(-2.0).sized(2.0).output("m1.11", "m1.11 : max. m1 width after slotting : 4.0um") + # rule m1.12 not coded because inconsistent with m1.11 + # rule m1.13, m1.14, m1.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 +end + +# via +#rule via.3 not coded +via.not(m1).output("via.4c.5c", "via.4c.5c : m1 must enclose all via") +if backend_flow = AL + via.not(areaid_mt).edges.without_length(0.15).output("via.1a", "via.1a : minimum/maximum width of via : 0.15um") + via.and(areaid_mt).not_interacting((via.and(areaid_mt).edges.without_length(0.15)).or(via.and(areaid_mt).edges.without_length(0.23)).or(via.and(areaid_mt).edges.without_length(0.28))).output("via.1b", "via.1b : minimum/maximum width of via in areaid.mt: 0.15um or 0.23um or 0.28um") + via.space(0.17, euclidian).output("via.2", "via.2 : min. via spacing : 0.17um") + m1.enclosing(via.not_interacting(via.edges.without_length(0.15)), 0.055, euclidian).output("via.4a", "via.4a : min. m1 enclosure of 0.15um via : 0.055um") + m1.enclosing(via.not_interacting(via.edges.without_length(0.23)), 0.03, euclidian).output("via.4b", "via.4b : min. m1 enclosure of 0.23um via : 0.03um") + via1_edges_with_less_enclosure_m1 = m1.enclosing(via.not_interacting(via.edges.without_length(0.15)), 0.085, projection).second_edges + opposite5 = (via.not_interacting(via.edges.without_length(0.15)).edges - via1_edges_with_less_enclosure_m1).width(0.15 + 1.dbu, projection).polygons + via.not_interacting(via.edges.without_length(0.15)).not_interacting(opposite5).output("via1.5a", "via1.5a : min. m1 enclosure of 0.15um via of 2 opposite edges : 0.085um") + via2_edges_with_less_enclosure_m1 = m1.enclosing(via.not_interacting(via.edges.without_length(0.23)), 0.06, projection).second_edges + opposite6 = (via.not_interacting(via.edges.without_length(0.23)).edges - via2_edges_with_less_enclosure_m1).width(0.23 + 1.dbu, projection).polygons + via.not_interacting(via.edges.without_length(0.23)).not_interacting(opposite6).output("via1.5b", "via1.5b : min. m1 enclosure of 0.23um via of 2 opposite edges : 0.06um") +end +if backend_flow = CU + via.not(areaid_mt).edges.without_length(0.18).output("via.11", "via.11 : minimum/maximum width of via : 0.18um") + via.space(0.13, euclidian).output("via.12", "via.12 : min. via spacing : 0.13um") + # rule via.13 not coded because not understandable + via1_edges_with_less_enclosure_m1 = m1.enclosing(via, 0.04, projection).second_edges + opposite5 = (via.edges - via1_edges_with_less_enclosure_m1).width(0.18 + 1.dbu, projection).polygons + via.not_interacting(opposite5).output("via1.14", "via1.14 : min. m1 enclosure of 0.04um via of 2 opposite edges : 0.04um") + # rules via.irdrop.1, via.irdrop.2, via.irdrop.3, via.irdrop.4 not coded because not understandable +end + +# m2 +huge_m2 = m2.sized(-1.5).sized(1.5) +m2.width(0.14, euclidian).output("m2.1", "m2.1 : min. m2 width : 0.14um") +m2.space(0.14, euclidian).output("m2.2", "m2.2 : min. m2 spacing : 0.14um") +huge_m2.separation(m2, 0.28, euclidian).output("m2.3ab", "m2.3ab : min. 3um.m2 spacing m2 : 0.28um") +# rule m2.3c not coded +m2.with_area(0..0.0676).output("m2.6", "m2.6 : min. m2 area : 0.0676um²") +m2.holes.with_area(0..0.14).output("m2.7", "m2.7 : min. m2 holes area : 0.14um²") +via.not(m2).output("m2.via", "m2.via : m2 must enclose via") +if backend_flow = AL + m2.enclosing(via, 0.055, euclidian).output("m2.4", "m2.4 : min. m2 enclosure of via : 0.055um") + via_edges_with_less_enclosure_m2 = m2.enclosing(via, 0.085, projection).second_edges + error_corners = via_edges_with_less_enclosure_m2.width(angle_limit(100.0), 1.dbu) + via_interact = via.interacting(error_corners.polygons(1.dbu)) + via_interact.output("m2.5", "m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um") + # opposite7 = (via.edges - via_edges_with_less_enclosure_m2).width(0.14 + 1.dbu, projection).polygons + # via.not_interacting(opposite7).output("m2.5", "m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um") + # rule m2.pd.1, rule m2.pd.2a, rule m2.pd.2b not coded +end +if bakend_flow = CU + m2.sized(-2.0).sized(2.0).output("m2.11", "m2.11 : max. m2 width after slotting : 4.0um") + # rule m2.12 not coded because inconsistent with m2.11 + # rule m2.13, m2.14, m2.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 +end + +# via2 +#rule via233 not coded +via2.not(m2).output("via2", "via2 : m2 must enclose all via2") +if backend_flow = AL + via2.not(areaid_mt).edges.without_length(0.2).output("via2.1a", "via2.1a : minimum/maximum width of via2 : 0.2um") + via2.and(areaid_mt).not_interacting((via2.and(areaid_mt).edges.without_length(0.2)).or(via2.and(areaid_mt).edges.without_length(1.2)).or(via2.and(areaid_mt).edges.without_length(1.5))).output("via2.1b", "via2.1b : minimum/maximum width of via2 in areaid.mt: 0.2um or 1.2um or 1.5um") + via2.space(0.2, euclidian).output("via2.2", "via2.2 : min. via2 spacing : 0.2um") + m2.enclosing(via2, 0.04, euclidian).output("via2.4", "via2.4 : min. m2 enclosure of via2 : 0.04um") + m2.enclosing(via2.not_interacting(via2.edges.without_length(1.5)), 0.14, euclidian).output("via2.4a", "via2.4a : min. m2 enclosure of 1.5um via2 : 0.14um") + via2_edges_with_less_enclosure_m2 = m2.enclosing(via2, 0.085, projection).second_edges + opposite8 = (via2.edges - via2_edges_with_less_enclosure_m2).width(0.2 + 1.dbu, projection).polygons + via2.not_interacting(opposite8).output("via2.5", "via2.5 : min. m2 enclosure of via2 of 2 opposite edges : 0.085um") +end +if backend_flow = CU + via2.edges.without_length(0.21).output("via2.11", "via2.11 : minimum/maximum width of via2 : 0.21um") + via2.isolated(0.18, euclidian).output("via2.12", "via2.12 : min. via2 spacing : 0.18um") + # rule via2.13 not coded because not understandable, or not clear + m2.enclosing(via2, 0.035, euclidian).output("via2.14", "via2.14 : min. m2 enclosure of via2 : 0.035um") + # rules via2.irdrop.1, via2.irdrop.2, via2.irdrop.3, via2.irdrop.4 not coded because not understandable +end + +# m3 +huge_m3 = m3.sized(-1.5).sized(1.5) +m3.width(0.3, euclidian).output("m3.1", "m3.1 : min. m3 width : 0.3um") +m3.space(0.3, euclidian).output("m3.2", "m3.2 : min. m3 spacing : 0.3um") +huge_m3.separation(m3, 0.4, euclidian).output("m3.3ab", "m3.3ab : min. 3um.m3 spacing m3 : 0.4um") +# rule m3.3c not coded +m3.with_area(0..0.24).output("m3.6", "m3.6 : min. m2 area : 0.24um²") +via2.not(m3).output("m3.via2", "m3.via2 : m3 must enclose via2") +if backend_flow = AL + m3.enclosing(via2, 0.065, euclidian).output("m3.4", "m3.4 : min. m3 enclosure of via2 : 0.065um") + via2_edges_with_less_enclosure_m3 = m3.enclosing(via2, 0.085, projection).second_edges + opposite9 = (via2.edges - via2_edges_with_less_enclosure_m3).width(0.3 + 1.dbu, projection).polygons + via2.not_interacting(opposite9).output("m3.5", "m3.5 : min. m3 enclosure of via2 of 2 opposite edges : 0.085um") + # rule m3.pd.1, rule m3.pd.2a, rule m3.pd.2b not coded +end +if bakend_flow = CU + m3.holes.with_area(0..0.2).output("m3.7", "m3.7 : min. m2 holes area : 0.2um²") + m3.sized(-2.0).sized(2.0).output("m3.11", "m3.11 : max. m3 width after slotting : 4.0um") + # rule m3.12 not coded because inconsistent with m3.11 + # rule m3.13, m3.14, m3.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 +end + +# via3 +#rule via3.3 not coded +via3.not(m3).output("via3", "via3 : m3 must enclose all via3") +if backend_flow = AL + via3.not(areaid_mt).edges.without_length(0.2).output("via3.1a", "via3.1a : minimum/maximum width of via3 : 0.2um") + via3.and(areaid_mt).not_interacting((via3.and(areaid_mt).edges.without_length(0.2)).or(via3.and(areaid_mt).edges.without_length(0.8))).output("via3.1a", "via3.1a : minimum/maximum width of via3 in areaid.mt: 0.2um or 0.8um") + via3.space(0.2, euclidian).output("via3.2", "via3.2 : min. via3 spacing : 0.2um") + m3.enclosing(via3, 0.06, euclidian).output("via3.4", "via3.4 : min. m3 enclosure of via3 : 0.06um") + via3_edges_with_less_enclosure_m3 = m3.enclosing(via3, 0.09, projection).second_edges + opposite10 = (via3.edges - via3_edges_with_less_enclosure_m3).width(0.2 + 1.dbu, projection).polygons + via3.not_interacting(opposite10).output("via3.5", "via3.5 : min. m2 enclosure of via3 of 2 opposite edges : 0.09um") +end +if backend_flow = CU + via3.edges.without_length(0.21).output("via3.11", "via3.11 : minimum/maximum width of via3 : 0.21um") + via3.space(0.18, euclidian).output("via3.12", "via3.12 : min. via3 spacing : 0.18um") + m3.enclosing(via3, 0.055, euclidian).output("via3.13", "via3.13 : min. m3 enclosure of via3 : 0.055um") + # rule via3.14 not coded because not understandable, or not clear + # rules via3.irdrop.1, via3.irdrop.2, via3.irdrop.3, via3.irdrop.4 not coded because not understandable +end + +# nsm +nsm.width(3.0, euclidian).output("nsm.1", "nsm.1 : min. nsm width : 3.0um") +nsm.space(4.0, euclidian).output("nsm.2", "nsm.2 : min. nsm spacing : 4.0um") +nsm.enclosing(diff, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of diff : 3.0um") +nsm.enclosing(tap, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of tap : 3.0um") +nsm.enclosing(poly, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of poly : 3.0um") +nsm.enclosing(li, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of li : 3.0um") +nsm.enclosing(m1, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m1 : 3.0um") +nsm.enclosing(m2, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m2 : 3.0um") +nsm.enclosing(m3, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m3 : 3.0um") +nsm.enclosing(m4, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m4 : 3.0um") +nsm.enclosing(m5, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m5 : 3.0um") +nsm.enclosing(cfom, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of cfom : 3.0um") +if backend_flow = AL + nsm.separation(diff, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to diff : 1.0um") + nsm.separation(tap, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to tap : 1.0um") + nsm.separation(poly, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to poly : 1.0um") + nsm.separation(li, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to li : 1.0um") + nsm.separation(m1, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m1 : 1.0um") + nsm.separation(m2, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m2 : 1.0um") + nsm.separation(m3, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m3 : 1.0um") + nsm.separation(m4, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m4 : 1.0um") + nsm.separation(m5, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m5 : 1.0um") + nsm.separation(cfom, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to cfom : 1.0um") +end + +# m4 +huge_m4 = m4.sized(-1.5).sized(1.5) +m4.width(0.3, euclidian).output("m4.1", "m4.1 : min. m4 width : 0.3um") +m4.space(0.3, euclidian).output("m4.2", "m4.2 : min. m4 spacing : 0.3um") +m4.with_area(0..0.24).output("m4.4", "m4.4 : min. m2 area : 0.24um²") +huge_m4.separation(m4, 0.4, euclidian).output("m4.5ab", "m4.5ab : min. 3um.m4 spacing m4 : 0.4um") +via3.not(m4).output("m4.via3", "m4.via3 : m4 must enclose via3") +if backend_flow = AL + m4.enclosing(via3, 0.065, euclidian).output("m4.3", "m4.3 : min. m4 enclosure of via3 : 0.065um") + via3_edges_with_less_enclosure_m4 = m4.enclosing(via2, 0.085, projection).second_edges + opposite9 = (via3.edges - via3_edges_with_less_enclosure_m4).width(0.3 + 1.dbu, projection).polygons + via3.not_interacting(opposite9).output("m4.5", "m4.5 : min. m4 enclosure of via3 of 2 opposite edges : 0.085um") + # rule m4.pd.1, rule m4.pd.2a, rule m4.pd.2b not coded +end +if bakend_flow = CU + m4.holes.with_area(0..0.2).output("m4.7", "m4.7 : min. m2 holes area : 0.2um²") + m4.sized(-5.0).sized(5.0).output("m4.11", "m4.11 : max. m4 width after slotting : 10.0um") + # rule m4.12 not coded because inconsistent with m4.11 + # rule m4.13, m4.14, m4.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 + m4.enclosing(via3, 0.06, euclidian).output("m4.15", "m4.15 : min. m4 enclosure of via3 : 0.06um") +end + +# via4 +via4.edges.without_length(0.8).output("via4.1a", "via4.1a : minimum/maximum width of via4 : 0.8um") +via4.space(0.8, euclidian).output("via4.2", "via4.2 : min. via4 spacing : 0.8um") +#rule via4.3 not coded +m4.enclosing(via4, 0.19, euclidian).output("via4.4", "via4.4 : min. m4 enclosure of via4 : 0.19um") +via4.not(m4).output("via4", "via4 : m4 must enclose all via4") +if backend_flow = CU + # rules via4.irdrop.1, via4.irdrop.2, via4.irdrop.3, via4.irdrop.4 not coded because not understandable +end + +# m5 +m5.width(1.6, euclidian).output("m5.1", "m5.1 : min. m5 width : 1.6um") +m5.space(1.6, euclidian).output("m5.2", "m5.2 : min. m5 spacing : 1.6um") +via4.not(m5).output("m5.via4", "m5.via4 : m5 must enclose via4") +m5.enclosing(via4, 0.31, euclidian).output("m5.3", "m4.3 : min. m5 enclosure of via4 : 0.31um") + +# pad +pad.isolated(1.27, euclidian).output("pad.2", "pad.2 : min. pad spacing : 1.27um") + +end #BEOL + +if FEOL +info("FEOL section") + +# mf +mf.not_interacting(mf.edges.without_length(0.8)).output("mf.1", "mf.1 : minimum/maximum width of fuse : 0.8um") +mf.not_interacting(mf.edges.without_length(7.2)).output("mf.2", "mf.2 : minimum/maximum length of fuse : 7.2um") +mf.space(1.96, euclidian).output("mf.3", "mf.3 : min. fuse center spacing : 2.76um") +# fuses need more clarification on fuse_shield, fuse layers ... + +# hvi +hvi.width(0.6, euclidian).output("hvi.1", "hvi.1 : min. hvi width : 0.6um") +hvi.space(0.7, euclidian).output("hvi.2", "hvi.2 : min. hvi spacing, merge if less : 0.7um") +hvi.and(tunm).output("hvi.4", "hvi.4 : hvi must not overlapp tunm") +hvi.and(nwell).separation(nwell, 2.0, euclidian).output("hvnwell.8", "hvnwelli.8 : min. hvnwel spacing to nwell : 2.0") +areaid_hl.not(hvi).output("hvnwel.9", "hvnwell.9 : hvi must overlapp hvnwell") +# rule hvnell.10 not coded +diff.not(psdm.and(diff_rs)).and(hvi).width(0.29, euclidian).output("hvdifftap.14", "hvdifftap.14 : min. diff inside hvi width : 0.29um") +diff.and(psdm.and(diff_rs)).and(hvi).width(0.15, euclidian).output("hvdifftap.14a", "hvdifftap.14a : min. p+diff resistor inside hvi width : 0.15um") +diff.and(hvi).isolated(0.3, euclidian).output("hvdifftap.15a", "hvdifftap.15a : min. diff inside hvi spacing : 0.3um") +diff.and(hvi).and(nsdm).separation(diff.and(hvi).and(psdm), 0.37, euclidian).polygons.without_area(0).output("hvdifftap.15b", "hvdifftap.15b : min. n+diff inside hvi spacing to p+diff inside hvi except abutting: 0.37um") +tap.and(hvi).edges.and(diff).without_length(0.7).output("hvdifftap.16", "hvdifftap.16 : min. tap inside hvi abuttng diff : 0.7um") +hvi.and(nwell).enclosing(diff, 0.33, euclidian).output("hvdifftap.17", "hvdifftap.17 : min. hvnwell enclosure of p+diff : 0.33um") +hvi.and(nwell).separation(diff, 0.43, euclidian).output("hvdifftap.18", "hvdifftap.18 : min. hvnwell spacing to n+diff : 0.43um") +hvi.and(nwell).enclosing(tap, 0.33, euclidian).output("hvdifftap.19", "hvdifftap.19 : min. hvnwell enclosure of n+tap : 0.33um") +hvi.and(nwell).separation(tap, 0.43, euclidian).output("hvdifftap.20", "hvdifftap.20 : min. hvnwell spacing to p+tap : 0.43um") +hvi.and(diff).edges.not(diff.edges).output("hvdifftap.21", "hvdifftap.21 : diff must not straddle hvi") +hvi.and(tap).edges.not(tap.edges).output("hvdifftap.21", "hvdifftap.21 : tap must not straddle hvi") +hvi.enclosing(difftap, 0.18, euclidian).output("hvdifftap.22", "hvdifftap.22 : min. hvi enclosure of diff or tap : 0.18um") +hvi.separation(difftap, 0.18, euclidian).output("hvdifftap.23", "hvdifftap.23 : min. hvi spacing to diff or tap : 0.18um") +hvi.and(diff).not(nwell).separation(nwell, 0.43, euclidian).output("hvdifftap.24", "hvdifftap.24 : min. hv n+diff spacing to nwell : 0.43um") +diff.and(hvi).not(nwell).isolated(1.07, euclidian).polygons.and(tap).output("hvdifftap.25", "hvdifftap.25 : min. n+diff inside hvi spacing accros p+tap : 1.07um") +diff.not(poly).edges.and(gate.and(hvi).edges).space(0.35, euclidian).output("hvpoly.13", "hvpoly.13: min. hvi gate length : 0.5um") +hvi.and(poly).edges.not(poly.edges).output("hvpoly.14", "hvpoly.14 : poly must not straddle hvi") + +# hvntm +hvntm.width(0.7, euclidian).output("hvntm.1", "hvntm.1 : min. hvntm width : 0.7um") +hvntm.space(0.7, euclidian).output("hvntm.2", "hvntm.2 : min. hvntm spacing : 0.7um") +hvntm.enclosing(diff.and(nwell).and(hvi), 0.185, euclidian).output("hvntm.3", "hvntm.3 : min. hvntm enclosure of hv n+diff : 0.185um") +hvntm.separation(diff.not(nwell).not(hvi), 0.185, euclidian).output("hvntm.4", "hvntm.4 : min. hvntm spacing to n+diff : 0.185um") +hvntm.separation(diff.and(nwell).not(hvi), 0.185, euclidian).output("hvntm.5", "hvntm.5 : min. hvntm spacing to p+diff : 0.185um") +hvntm.separation(tap.not(nwell).not(hvi), 0.185, euclidian).polygons.without_area(0).output("hvntm.6a", "hvntm.6a : min. hvntm spacing to p+tap : 0.185um") +hvntm.and(areaid_ce).output("hvntm.9", "hvntm.9 : hvntm must not overlapp areaid.ce") + +# denmos +poly.not_interacting(pwde).interacting(areaid_en).width(1.055, projection).output("denmos.1", "denmos.1 : min. de_nfet gate width : 1.055um") +diff.not_interacting(pwde).enclosing(poly.interacting(areaid_en), 0.28, projection).polygons.without_area(0).output("denmos.2", "denmos.2 : min. de_nfet source ouside poly width : 0.28um") +diff.not_interacting(pwde).and(poly.interacting(areaid_en)).width(0.925, projection).output("denmos.3", "denmos.3 : min. de_nfet source inside poly width : 0.925um") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).width(0.17, euclidian).output("denmos.4", "denmos.4 : min. de_nfet drain width : 0.17um") +nwell.not_interacting(pwde).and(poly.interacting(areaid_en)).width(0.225, projection).polygons.or(nwell.and(poly.interacting(areaid_en)).sized(-0.1125).sized(0.1125)).output("denmos.5", "denmos.5 : min. de_nfet source inside nwell width : 0.225m") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).separation(diff.interacting(poly.interacting(areaid_en)), 1.585, projection).output("denmos.6", "denmos.6 : min. de_nfet source spacing to drain : 1.585um") +nwell.not_interacting(pwde).and(poly.and(diff).interacting(areaid_en)).edges.without_length(5.0, nil).output("denmos.7", "denmos.7 : min. de_nfet channel width : 5.0um") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("denmos.8", "denmos.8 : 90deg. not allowed for de_nfet drain") +nwell.not_interacting(pwde).interacting(areaid_en).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("denmos.9a", "denmos.9a : 90deg. not allowed for de_nfet nwell") +nwell.not_interacting(pwde).interacting(areaid_en).edges.with_angle(45).without_length(0.607..0.609).output("denmos.9a", "denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners") +nwell.not_interacting(pwde).interacting(areaid_en).edges.with_angle(135).without_length(0.607..0.609).output("denmos.9a", "denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(45).without_length(0.7..0.71).output("denmos.9b", "denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(135).without_length(0.7..0.71).output("denmos.9b", "denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners") +nwell.not_interacting(pwde).enclosing(diff.interacting(areaid_en).not_interacting(poly), 0.66, euclidian).output("denmos.10", "denmos.10 : min. nwell enclosure of de_nfet drain : 0.66um") +nwell.not_interacting(pwde).interacting(areaid_en).separation(tap.not(nwell), 0.86, euclidian).output("denmos.11", "denmos.11 : min. de_nfet nwell spacing to tap : 0.86um") +nwell.not_interacting(pwde).interacting(areaid_en).isolated(2.4, euclidian).output("denmos.12", "denmos.12 : min. de_nfet nwell : 2.4um") +nsdm.not_interacting(pwde).enclosing(diff.interacting(areaid_en).interacting(poly), 0.13, euclidian).output("denmos.13", "denmos.13 : min. nsdm enclosure of de_nfet source : 0.13um") + +# depmos +poly.interacting(pwde).interacting(areaid_en).width(1.05, projection).output("depmos.1", "depmos.1 : min. de_pfet gate width : 1.05um") +diff.interacting(pwde).enclosing(poly.interacting(areaid_en), 0.28, projection).polygons.without_area(0).output("depmos.2", "depmos.2 : min. de_pfet source ouside poly width : 0.28um") +diff.interacting(pwde).and(poly.interacting(areaid_en)).width(0.92, projection).output("depmos.3", "depmos.3 : min. de_pfet source inside poly width : 0.92um") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).width(0.17, euclidian).output("depmos.4", "depmos.4 : min. de_pfet drain width : 0.17um") +pwde.not(nwell).and(poly.interacting(areaid_en)).width(0.26, projection).polygons.or(pwde.not(nwell).and(poly.interacting(areaid_en)).sized(-0.13).sized(0.13)).output("depmos.5", "depmos.5 : min. de_pfet source inside nwell width : 0.26m") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).separation(diff.interacting(poly.interacting(areaid_en)), 1.19, projection).output("depmos.6", "depmos.6 : min. de_pfet source spacing to drain : 1.19um") +nwell.interacting(pwde).and(poly.and(diff).interacting(areaid_en)).edges.without_length(5.0, nil).output("depmos.7", "depmos.7 : min. de_pfet channel width : 5.0um") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("depmos.8", "depmos.8 : 90deg. not allowed for de_pfet drain") +pwde.not(nwell).interacting(areaid_en).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("depmos.9a", "depmos.9a : 90deg. not allowed for de_pfet pwell") +pwde.not(nwell).interacting(areaid_en).edges.with_angle(45).without_length(0.607..0.609).output("depmos.9a", "depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners") +pwde.not(nwell).interacting(areaid_en).edges.with_angle(135).without_length(0.607..0.609).output("depmos.9a", "depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(45).without_length(0.7..0.71).output("depmos.9b", "depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(135).without_length(0.7..0.71).output("depmos.9b", "depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners") +nwell.interacting(pwde).separation(diff.interacting(areaid_en).not_interacting(poly), 0.86, euclidian).output("depmos.10", "depmos.10 : min. pwell enclosure of de_pfet drain : 0.86um") +pwde.not(nwell).interacting(areaid_en).separation(tap.and(nwell), 0.66, euclidian).output("depmos.11", "depmos.11 : min. de_pfet pwell spacing to tap : 0.66um") +psdm.interacting(pwde).enclosing(diff.interacting(areaid_en).interacting(poly), 0.13, euclidian).output("depmos.12", "depmos.12 : min. psdm enclosure of de_pfet source : 0.13um") + +# extd +areaid_en.and(difftap).edges.not(difftap.edges).output("extd.1", "extd.1 : difftap must not straddle areaid.en") +difftap.interacting(areaid_en).not(poly).with_area(0).output("extd.2", "extd.2 : poly must not overlapp entirely difftap in areaid.en") +# rules extd.4, extd.5, extd.6, extd.7 not coded because specific to some cells + +# vhvi +# rules vhvi.vhv.1, vhvi.vhv.2, vhvi.vhv.3, vhvi.vhv.4, vhvi.vhv.5, vhvi.vhv.6 not coded +vhvi.width(0.02, euclidian).output("vhvi.1", "vhvi.1 : min. vhvi width : 0.02um") +vhvi.and(areaid_ce).output("vhvi.2", "vhvi.2 : vhvi must not overlap areaid.ce") +vhvi.and(hvi).output("vhvi.3", "vhvi.3 : vhvi must not overlap hvi") +# rules vhvi.4, vhvi.6 not coded +vhvi.and(diff).edges.not(diff.edges).output("vhvi.5", "vhvi.5 : vhvi must not straddle diff") +vhvi.and(tap).edges.not(tap.edges).output("vhvi.5", "vhvi.5 : vhvi must not straddle tap") +vhvi.and(poly).edges.not(poly.edges).output("vhvi.7", "vhvi.7 : vhvi must not straddle poly") + +nwell.and(vhvi).separation(nwell, 2.5, euclidian).output("hv.nwell.1", "hv.nwell.1 : min. vhvi nwell spacing to nwell : 2.5um") +diff.and(vhvi).space(0.3, euclidian).output("hv.diff.1", "hv.diff.1 : min. vhvi diff spacing : 0.3um") +nwell.interacting(diff.and(vhvi)).separation(diff.not(nwell), 0.43, euclidian).output("hv.diff.2", "hv.diff.2 : min. vhvi nwell spacing n+diff : 0.43um") +diff.and(vhvi).not(nwell).separation(nwell, 0.55, euclidian).output("hv.diff.3a", "hv.diff.3a : min. vhvi n+diff spacing nwell : 0.55um") +# rule hv.diff.3b not coded +poly.and(vhvi).not(diff).separation(diff, 0.3, euclidian).polygons.without_area(0).output("hv.poly.2", "hv.poly.2 : min. vhvi poly spacing to diff : 0.3um") +poly.and(vhvi).not(diff).separation(nwell, 0.55, euclidian).polygons.without_area(0).output("hv.poly.3", "hv.poly.3 : min. vhvi poly spacing to nwell : 0.55um") +nwell.enclosing(poly.and(vhvi).not(diff), 0.3, euclidian).polygons.without_area(0).output("hv.poly.4", "hv.poly.4 : min. nwell enclosure of vhvi poly : 0.3um") +#poly.and(vhvi).enclosing(diff.interacting(areaid_en), 0.16, projection).polygons.without_area(0).output("hv.poly.6", "hv.poly.6 : min. poly enclosure of hvfet gate : 0.16um") +# rule hv.poly.7 not coded + +# uhvi +uhvi.and(diff).edges.not(diff.edges).output("uhvi.1", "uhvi.1 : diff must not straddle uhvi") +uhvi.and(tap).edges.not(tap.edges).output("uhvi.1", "uhvi.1 : tap must not straddle uhvi") +uhvi.and(poly).edges.not(poly.edges).output("uhvi.2", "uhvi.2 : poly must not straddle uhvi") +pwbm.not(uhvi).output("uhvi.3", "uhvi.3 : uhvi must not enclose pwbm") +uhvi.and(dnwell).edges.not(dnwell.edges).output("uhvi.4", "uhvi.4 : dnwell must not straddle uhvi") +areaid_en20.not(uhvi).output("uhvi.5", "uhvi.5 : uhvi must not enclose areaid.en20") +#dnwell.not(uhvi).output("uhvi.6", "uhvi.6 : uhvi must not enclose dnwell") +natfet.not(uhvi).output("uhvi.7", "uhvi.7 : uhvi must not enclose natfet") + +# pwell_res +pwell_rs.width(2.65).output("pwres.2", "pwres.2 : min. pwell resistor width : 2.65um") +pwell_rs.sized(-2.65).sized(2.65).output("pwres.2", "pwres.2 : max. pwell resistor width : 2.65um") +pwell_rs.interacting(pwell_rs.edges.with_length(2.651,26.499)).output("pwres.3", "pwres.3 : min. pwell resistor length : 26.5um") +pwell_rs.interacting(pwell_rs.edges.with_length(265.0, nil)).output("pwres.4", "pwres.4 : max. pwell resistor length : 265um") +tap.interacting(pwell_rs).separation(nwell, 0.22, euclidian).output("pwres.5", "pwres.5 : min. pwell resistor tap spacing to nwell : 0.22um") +tap.interacting(pwell_rs).and(tap.sized(0.22).and(nwell)).output("pwres.5", "pwres.5 : max. pwell resistor tap spacing to nwell : 0.22um") +tap.interacting(pwell_rs).width(0.53).output("pwres.6", "pwres.6 : min. width of tap inside pwell resistor : 0.53um") +tap.interacting(pwell_rs).sized(-0.265).sized(0.265).output("pwres.6", "pwres.6 : max. width of tap inside pwell resistor : 0.53um") +# rules pwres.7a, pwres.7b not coded +pwell_rs.and(diff).output("pwres.8", "pwres.8 : diff not allowed inside pwell resistor") +pwell_rs.and(poly).output("pwres.8", "pwres.8 : poly not allowed inside pwell resistor") +# rules pwres.9, pwres.10 not coded + +# rf_diode +areaid_re.with_angle(0 .. 90).output("rfdiode.1", "rfdiode.1 : non 90 degree angle areaid.re") +areaid_re.not(nwell).or(nwell.interacting(areaid_re).not(areaid_re)).output("rfdiode.2", "rfdiode.2 : areaid.re must coincide rf nwell diode") +# rule rfdiode.3 not coded + +end #FEOL + +if OFFGRID +info("OFFGRID-ANGLES section") + +dnwell.ongrid(0.005).output("dnwell_OFFGRID", "x.1b : OFFGRID vertex on dnwell") +dnwell.with_angle(0 .. 45).output("dnwell_angle", "x.3a : non 45 degree angle dnwell") +nwell.ongrid(0.005).output("nwell_OFFGRID", "x.1b : OFFGRID vertex on nwell") +nwell.with_angle(0 .. 45).output("nwell_angle", "x.3a : non 45 degree angle nwell") +pwbm.ongrid(0.005).output("pwbm_OFFGRID", "x.1b : OFFGRID vertex on pwbm") +pwbm.with_angle(0 .. 45).output("pwbm_angle", "x.3a : non 45 degree angle pwbm") +pwde.ongrid(0.005).output("pwde_OFFGRID", "x.1b : OFFGRID vertex on pwde") +pwde.with_angle(0 .. 45).output("pwde_angle", "x.3a : non 45 degree angle pwde") +hvtp.ongrid(0.005).output("hvtp_OFFGRID", "x.1b : OFFGRID vertex on hvtp") +hvtp.with_angle(0 .. 45).output("hvtp_angle", "x.3a : non 45 degree angle hvtp") +hvtr.ongrid(0.005).output("hvtr_OFFGRID", "x.1b : OFFGRID vertex on hvtr") +hvtr.with_angle(0 .. 45).output("hvtr_angle", "x.3a : non 45 degree angle hvtr") +lvtn.ongrid(0.005).output("lvtn_OFFGRID", "x.1b : OFFGRID vertex on lvtn") +lvtn.with_angle(0 .. 45).output("lvtn_angle", "x.3a : non 45 degree angle lvtn") +ncm.ongrid(0.005).output("ncm_OFFGRID", "x.1b : OFFGRID vertex on ncm") +ncm.with_angle(0 .. 45).output("ncm_angle", "x.3a : non 45 degree angle ncm") +diff.ongrid(0.005).output("diff_OFFGRID", "x.1b : OFFGRID vertex on diff") +tap.ongrid(0.005).output("tap_OFFGRID", "x.1b : OFFGRID vertex on tap") +diff.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("diff_angle", "x.2 : non 90 degree angle diff") +diff.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("diff_angle", "x.2c : non 45 degree angle diff") +tap.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("tap_angle", "x.2 : non 90 degree angle tap") +tap.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("tap_angle", "x.2c : non 45 degree angle tap") +tunm.ongrid(0.005).output("tunm_OFFGRID", "x.1b : OFFGRID vertex on tunm") +tunm.with_angle(0 .. 45).output("tunm_angle", "x.3a : non 45 degree angle tunm") +poly.ongrid(0.005).output("poly_OFFGRID", "x.1b : OFFGRID vertex on poly") +poly.with_angle(0 .. 90).output("poly_angle", "x.2 : non 90 degree angle poly") +rpm.ongrid(0.005).output("rpm_OFFGRID", "x.1b : OFFGRID vertex on rpm") +rpm.with_angle(0 .. 45).output("rpm_angle", "x.3a : non 45 degree angle rpm") +npc.ongrid(0.005).output("npc_OFFGRID", "x.1b : OFFGRID vertex on npc") +npc.with_angle(0 .. 45).output("npc_angle", "x.3a : non 45 degree angle npc") +nsdm.ongrid(0.005).output("nsdm_OFFGRID", "x.1b : OFFGRID vertex on nsdm") +nsdm.with_angle(0 .. 45).output("nsdm_angle", "x.3a : non 45 degree angle nsdm") +psdm.ongrid(0.005).output("psdm_OFFGRID", "x.1b : OFFGRID vertex on psdm") +psdm.with_angle(0 .. 45).output("psdm_angle", "x.3a : non 45 degree angle psdm") +licon.ongrid(0.005).output("licon_OFFGRID", "x.1b : OFFGRID vertex on licon") +licon.with_angle(0 .. 90).output("licon_angle", "x.2 : non 90 degree angle licon") +li.ongrid(0.005).output("li_OFFGRID", "x.1b : OFFGRID vertex on li") +li.with_angle(0 .. 45).output("li_angle", "x.3a : non 45 degree angle li") +mcon.ongrid(0.005).output("ct_OFFGRID", "x.1b : OFFGRID vertex on mcon") +mcon.with_angle(0 .. 90).output("ct_angle", "x.2 : non 90 degree angle mcon") +vpp.ongrid(0.005).output("vpp_OFFGRID", "x.1b : OFFGRID vertex on vpp") +vpp.with_angle(0 .. 45).output("vpp_angle", "x.3a : non 45 degree angle vpp") +m1.ongrid(0.005).output("m1_OFFGRID", "x.1b : OFFGRID vertex on m1") +m1.with_angle(0 .. 45).output("m1_angle", "x.3a : non 45 degree angle m1") +via.ongrid(0.005).output("via_OFFGRID", "x.1b : OFFGRID vertex on via") +via.with_angle(0 .. 90).output("via_angle", "x.2 : non 90 degree angle via") +m2.ongrid(0.005).output("m2_OFFGRID", "x.1b : OFFGRID vertex on m2") +m2.with_angle(0 .. 45).output("m2_angle", "x.3a : non 45 degree angle m2") +via2.ongrid(0.005).output("via2_OFFGRID", "x.1b : OFFGRID vertex on via2") +via2.with_angle(0 .. 90).output("via2_angle", "x.2 : non 90 degree angle via2") +m3.ongrid(0.005).output("m3_OFFGRID", "x.1b : OFFGRID vertex on m3") +m3.with_angle(0 .. 45).output("m3_angle", "x.3a : non 45 degree angle m3") +via3.ongrid(0.005).output("via3_OFFGRID", "x.1b : OFFGRID vertex on via3") +via3.with_angle(0 .. 90).output("via3_angle", "x.2 : non 90 degree angle via3") +nsm.ongrid(0.005).output("nsm_OFFGRID", "x.1b : OFFGRID vertex on nsm") +nsm.with_angle(0 .. 45).output("nsm_angle", "x.3a : non 45 degree angle nsm") +m4.ongrid(0.005).output("m4_OFFGRID", "x.1b : OFFGRID vertex on m4") +m4.with_angle(0 .. 45).output("m4_angle", "x.3a : non 45 degree angle m4") +via4.ongrid(0.005).output("via4_OFFGRID", "x.1b : OFFGRID vertex on via4") +via4.with_angle(0 .. 90).output("via4_angle", "x.2 : non 90 degree angle via4") +m5.ongrid(0.005).output("m5_OFFGRID", "x.1b : OFFGRID vertex on m5") +m5.with_angle(0 .. 45).output("m5_angle", "x.3a : non 45 degree angle m5") +pad.ongrid(0.005).output("pad_OFFGRID", "x.1b : OFFGRID vertex on pad") +pad.with_angle(0 .. 45).output("pad_angle", "x.3a : non 45 degree angle pad") +mf.ongrid(0.005).output("mf_OFFGRID", "x.1b : OFFGRID vertex on mf") +mf.with_angle(0 .. 90).output("mf_angle", "x.2 : non 90 degree angle mf") +hvi.ongrid(0.005).output("hvi_OFFGRID", "x.1b : OFFGRID vertex on hvi") +hvi.with_angle(0 .. 45).output("hvi_angle", "x.3a : non 45 degree angle hvi") +hvntm.ongrid(0.005).output("hvntm_OFFGRID", "x.1b : OFFGRID vertex on hvntm") +hvntm.with_angle(0 .. 45).output("hvntm_angle", "x.3a : non 45 degree angle hvntm") +vhvi.ongrid(0.005).output("vhvi_OFFGRID", "x.1b : OFFGRID vertex on vhvi") +vhvi.with_angle(0 .. 45).output("vhvi_angle", "x.3a : non 45 degree angle vhvi") +uhvi.ongrid(0.005).output("uhvi_OFFGRID", "x.1b : OFFGRID vertex on uhvi") +uhvi.with_angle(0 .. 45).output("uhvi_angle", "x.3a : non 45 degree angle uhvi") +pwell_rs.ongrid(0.005).output("pwell_rs_OFFGRID", "x.1b : OFFGRID vertex on pwell_rs") +pwell_rs.with_angle(0 .. 45).output("pwell_rs_angle", "x.3a : non 45 degree angle pwell_rs") +areaid_re.ongrid(0.005).output("areaid_re_OFFGRID", "x.1b : OFFGRID vertex on areaid.re") + +end #OFFGRID + +# time spent for the DRC +time = Time.now +hours = ((time - tstart)/3600).to_i +minutes = ((time - tstart)/60 - hours * 60).to_i +seconds = ((time - tstart) - (minutes * 60 + hours * 3600)).to_i +$stdout.write "DRC finished at : #{time.hour}:#{time.min}:#{time.sec} - DRC duration = #{hours} hrs. #{minutes} min. #{seconds} sec.\n" + diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/sky130A.lydrc b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/sky130A.lydrc new file mode 100644 index 000000000..67ec2a5cf --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/sky130A.lydrc @@ -0,0 +1,39 @@ + + + DRC + + drc + + + + false + false + 0 + + true + sky130a + tools_menu.sky130a>lvs("Sky130A").end + dsl + drc-dsl-xml + +# Take input from layout window +# $input = nil + +# Interactive report +# $report = "" + +# Enable all parts +$feol = "true" +$beol = "true" +$offgrid = "true" + +# Disabled for now +$seal = "false" +$floating_met = "false" + +# Default threads +$thr = nil + +# %include ./core/sky130A_mr.drc + + diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/sky130A.lyp b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/sky130A.lyp new file mode 100755 index 000000000..cf7ec0b5d --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/sky130A.lyp @@ -0,0 +1,8241 @@ + + + + #ccccd9 + #ccccd9 + 0 + 0 + C7 + C0 + true + true + false + 1 + false + false + 0 + prBoundary.boundary - 235/4 + 235/4@1 + + + #00ffff + #00ffff + 0 + 0 + C21 + C0 + true + true + false + 1 + false + false + 0 + pwell.drawing - 64/44 + 64/44@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + C39 + C0 + true + true + false + 1 + false + false + 0 + pwell.pin - 122/16 + 122/16@1 + + + #9900e6 + #9900e6 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + pwell.label - 64/59 + 64/59@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + pwell.res - 64/13 + 64/13@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + pwell.cut - 64/14 + 64/14@1 + + + #ffffff + #96c8ff + 0 + 0 + C39 + C0 + true + true + false + 1 + false + false + 0 + pwelliso.pin - 44/16 + 44/16@1 + + + #9900e6 + #9900e6 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + pwelliso.label - 44/5 + 44/5@1 + + + #00cc66 + #00cc66 + 0 + 0 + C21 + C0 + true + true + false + 1 + false + false + 0 + nwell.drawing - 64/20 + 64/20@1 + + + #ff00ff + #ff00ff + 0 + 0 + C2 + C0 + true + true + false + 1 + false + false + 0 + nwell.net - 84/23 + 84/23@1 + + + #268c6b + #268c6b + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + nwell.pin - 64/16 + 64/16@1 + + + #333399 + #333399 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + nwell.label - 64/5 + 64/5@1 + + + #c8ffc8 + #c8ffc8 + 0 + 0 + C48 + C0 + true + true + false + 1 + false + false + 0 + dnwell.drawing - 64/18 + 64/18@1 + + + #00ffff + #00ffff + 0 + 0 + C6 + C0 + true + true + false + 1 + false + false + 0 + vhvi.drawing - 74/21 + 74/21@1 + + + #00ff00 + #00ff00 + 0 + 0 + C35 + C0 + true + true + false + 1 + false + false + 0 + diff.drawing - 65/20 + 65/20@1 + + + #00ff00 + #00ff00 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + diff.res - 65/13 + 65/13@1 + + + #00ff00 + #00ff00 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + diff.cut - 65/14 + 65/14@1 + + + #268c6b + #268c6b + 0 + 0 + C37 + C0 + false + true + false + 1 + false + false + 0 + diff.pin - 65/16 + 65/16@1 + + + #c8ffc8 + #c8ffc8 + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + diff.label - 65/6 + 65/6@1 + + + #00ff00 + #00ff00 + 0 + 0 + C5 + C0 + false + true + false + 1 + false + false + 0 + diff.net - 65/23 + 65/23@1 + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + false + 0 + diff.boundary - 65/4 + 65/4@1 + + + #9900e6 + #9900e6 + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + diff.hv - 65/8 + 65/8@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C35 + C0 + true + true + false + 1 + false + false + 0 + tap.drawing - 65/44 + 65/44@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + tap.pin - 65/48 + 65/48@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C5 + C0 + false + true + false + 1 + false + false + 0 + tap.net - 65/41 + 65/41@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + false + 0 + tap.boundary - 65/60 + 65/60@1 + + + #fff464 + #fff464 + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + tap.label - 65/5 + 65/5@1 + + + #9900e6 + #9900e6 + 0 + 0 + C23 + C0 + true + true + false + 1 + false + false + 0 + psdm.drawing - 94/20 + 94/20@1 + + + #e61f0d + #e61f0d + 0 + 0 + C22 + C0 + true + true + false + 1 + false + false + 0 + nsdm.drawing - 93/44 + 93/44@1 + + + #ff0000 + #ff0000 + 0 + 0 + C42 + C0 + true + true + false + 1 + false + false + 0 + poly.drawing - 66/20 + 66/20@1 + + + #ff8000 + #ff8000 + 0 + 0 + C39 + C0 + true + true + false + 1 + false + false + 0 + poly.pin - 66/16 + 66/16@1 + + + #ff0000 + #ff0000 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + poly.res - 66/13 + 66/13@1 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.cut - 66/14 + 66/14@1 + + + #ff0000 + #ff0000 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + poly.gate - 66/9 + 66/9@1 + + + #ffafaf + #ffafaf + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.label - 66/5 + 66/5@1 + + + #ff0000 + #ff0000 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + poly.boundary - 66/4 + 66/4@1 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.probe - 66/25 + 66/25@1 + + + #ff0000 + #ff0000 + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + poly.short - 66/15 + 66/15@1 + + + #ff0000 + #ff0000 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + poly.net - 66/23 + 66/23@1 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.model - 66/83 + 66/83@1 + + + #00cc66 + #00cc66 + 0 + 0 + C51 + C0 + true + true + false + 1 + false + false + 0 + ldntm.drawing - 11/44 + 11/44@1 + + + #96c8ff + #ffffff + 0 + 0 + C15 + C0 + true + true + false + 1 + false + false + 0 + lvtn.drawing - 125/44 + 125/44@1 + + + #ff8000 + #ffffff + 0 + 0 + C14 + C0 + true + true + false + 1 + false + false + 0 + hvtp.drawing - 78/44 + 78/44@1 + + + #ff0000 + #e61f0d + 0 + 0 + C14 + C0 + false + true + false + 1 + false + false + 0 + hvtr.drawing - 18/20 + 18/20@1 + + + #9900e6 + #9900e6 + 0 + 0 + C42 + C0 + true + true + false + 1 + false + false + 0 + tunm.drawing - 80/20 + 80/20@1 + + + #ffffcc + #ffffcc + 0 + 0 + C24 + C0 + true + true + false + 1 + false + false + 0 + licon1.drawing - 66/44 + 66/44@1 + + + #ffffcc + #ffffcc + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + licon1.boundary - 66/60 + 66/60@1 + + + #ffe6bf + #c8ffff + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + licon1.pin - 66/58 + 66/58@1 + + + #ffffcc + #ffffcc + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + licon1.net - 66/41 + 66/41@1 + + + #bf4026 + #bf4026 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + npc.drawing - 95/20 + 95/20@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + li1.drawing - 67/20 + 67/20@1 + + + #bf4026 + #bf4026 + 0 + 0 + C47 + C0 + true + true + false + 1 + false + false + 0 + li1.pin - 67/16 + 67/16@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + I1 + C0 + false + true + false + 1 + false + false + 0 + li1.res - 67/13 + 67/13@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + li1.cut - 67/14 + 67/14@1 + + + #bf4026 + #bf4026 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + li1.label - 67/5 + 67/5@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C54 + C0 + true + true + false + 1 + false + false + 0 + li1.net - 67/23 + 67/23@1 + + + #d9e6ff + #d9e6ff + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + li1.boundary - 67/4 + 67/4@1 + + + #bf4026 + #bf4026 + 0 + 0 + C54 + C0 + true + true + false + 1 + false + false + 0 + li1.blockage - 67/10 + 67/10@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + li1.short - 67/15 + 67/15@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + li1.probe - 67/25 + 67/25@1 + + + #ccccd9 + #ccccd9 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + mcon.drawing - 67/44 + 67/44@1 + + + #ccccd9 + #ccccd9 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + mcon.boundary - 67/60 + 67/60@1 + + + #ffffcc + #d9e6ff + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + mcon.pin - 67/48 + 67/48@1 + + + #ccccd9 + #ccccd9 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + mcon.net - 67/41 + 67/41@1 + + + #0000ff + #0000ff + 0 + 0 + C7 + C0 + true + true + false + 1 + false + false + 0 + met1.drawing - 68/20 + 68/20@1 + + + #0000ff + #0000ff + 0 + 0 + I1 + C0 + false + true + false + 1 + false + false + 0 + met1.res - 68/13 + 68/13@1 + + + #0000ff + #0000ff + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + met1.cut - 68/14 + 68/14@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C6 + C0 + true + true + false + 1 + false + false + 0 + met1.pin - 68/16 + 68/16@1 + + + #96c8ff + #96c8ff + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + met1.label - 68/5 + 68/5@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + met1.net - 68/23 + 68/23@1 + + + #0000ff + #0000ff + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + met1.boundary - 68/4 + 68/4@1 + + + #0000ff + #0000ff + 0 + 0 + C54 + C0 + true + true + false + 1 + false + false + 0 + met1.blockage - 68/10 + 68/10@1 + + + #0000ff + #0000ff + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + met1.short - 68/15 + 68/15@1 + + + #0000ff + #0000ff + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + met1.probe - 68/25 + 68/25@1 + + + #0000ff + #0000ff + 0 + 0 + C26 + C0 + false + true + false + 1 + false + false + 0 + met1.option1 - 68/32 + 68/32@1 + + + #0000ff + #0000ff + 0 + 0 + C27 + C0 + false + true + false + 1 + false + false + 0 + met1.option2 - 68/33 + 68/33@1 + + + #0000ff + #0000ff + 0 + 0 + C28 + C0 + false + true + false + 1 + false + false + 0 + met1.option3 - 68/34 + 68/34@1 + + + #0000ff + #0000ff + 0 + 0 + C29 + C0 + false + true + false + 1 + false + false + 0 + met1.option4 - 68/35 + 68/35@1 + + + #0000ff + #0000ff + 0 + 0 + C30 + C0 + false + true + false + 1 + false + false + 0 + met1.option5 - 68/36 + 68/36@1 + + + #0000ff + #0000ff + 0 + 0 + C31 + C0 + false + true + false + 1 + false + false + 0 + met1.option6 - 68/37 + 68/37@1 + + + #0000ff + #0000ff + 0 + 0 + C32 + C0 + false + true + false + 1 + false + false + 0 + met1.option7 - 68/38 + 68/38@1 + + + #0000ff + #0000ff + 0 + 0 + C33 + C0 + false + true + false + 1 + false + false + 0 + met1.option8 - 68/39 + 68/39@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + via.drawing - 68/44 + 68/44@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + via.boundary - 68/60 + 68/60@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + via.net - 68/41 + 68/41@1 + + + #ae7dff + #ae7dff + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + via.pin - 68/58 + 68/58@1 + + + #ff00ff + #ff00ff + 0 + 0 + C38 + C0 + true + true + false + 1 + false + false + 0 + met2.drawing - 69/20 + 69/20@1 + + + #ff00ff + #ff00ff + 0 + 0 + I1 + C0 + false + true + false + 1 + false + false + 0 + met2.res - 69/13 + 69/13@1 + + + #ff00ff + #ff00ff + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + met2.cut - 69/14 + 69/14@1 + + + #ff00ff + #ff00ff + 0 + 0 + C46 + C0 + true + true + false + 1 + false + false + 0 + met2.pin - 69/16 + 69/16@1 + + + #ffc8ff + #ffc8ff + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + met2.label - 69/5 + 69/5@1 + + + #ff00ff + #ff00ff + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + met2.net - 69/23 + 69/23@1 + + + #ff00ff + #ff00ff + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + met2.boundary - 69/4 + 69/4@1 + + + #ff00ff + #ff00ff + 0 + 0 + C54 + C0 + true + true + false + 1 + false + false + 0 + met2.blockage - 69/10 + 69/10@1 + + + #ff00ff + #ff00ff + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + met2.short - 69/15 + 69/15@1 + + + #ff00ff + #ff00ff + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + met2.probe - 69/25 + 69/25@1 + + + #ff00ff + #ff00ff + 0 + 0 + C26 + C0 + false + true + false + 1 + false + false + 0 + met2.option1 - 69/32 + 69/32@1 + + + #ff00ff + #ff00ff + 0 + 0 + C27 + C0 + false + true + false + 1 + false + false + 0 + met2.option2 - 69/33 + 69/33@1 + + + #ff00ff + #ff00ff + 0 + 0 + C28 + C0 + false + true + false + 1 + false + false + 0 + met2.option3 - 69/34 + 69/34@1 + + + #ff00ff + #ff00ff + 0 + 0 + C29 + C0 + false + true + false + 1 + false + false + 0 + met2.option4 - 69/35 + 69/35@1 + + + #ff00ff + #ff00ff + 0 + 0 + C30 + C0 + false + true + false + 1 + false + false + 0 + met2.option5 - 69/36 + 69/36@1 + + + #ff00ff + #ff00ff + 0 + 0 + C31 + C0 + false + true + false + 1 + false + false + 0 + met2.option6 - 69/37 + 69/37@1 + + + #ff00ff + #ff00ff + 0 + 0 + C32 + C0 + false + true + false + 1 + false + false + 0 + met2.option7 - 69/38 + 69/38@1 + + + #ff00ff + #ff00ff + 0 + 0 + C33 + C0 + false + true + false + 1 + false + false + 0 + met2.option8 - 69/39 + 69/39@1 + + + #ff8000 + #ff8000 + 0 + 0 + I1 + C7 + true + true + false + 3 + false + false + 0 + via2.drawing - 69/44 + 69/44@1 + + + #ff8000 + #ff8000 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + via2.boundary - 69/60 + 69/60@1 + + + #ff8000 + #ff8000 + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + via2.pin - 69/58 + 69/58@1 + + + #ff8000 + #ff8000 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + via2.net - 69/41 + 69/41@1 + + + #00ffff + #00ffff + 0 + 0 + C50 + C0 + true + true + false + 1 + false + false + 0 + met3.drawing - 70/20 + 70/20@1 + + + #00ffff + #00ffff + 0 + 0 + I1 + C0 + false + true + false + 1 + false + false + 0 + met3.res - 70/13 + 70/13@1 + + + #00ffff + #00ffff + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + met3.cut - 70/14 + 70/14@1 + + + #00ffff + #00ffff + 0 + 0 + C35 + C0 + true + true + false + 1 + false + false + 0 + met3.pin - 70/16 + 70/16@1 + + + #c8ffff + #c8ffff + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + met3.label - 70/5 + 70/5@1 + + + #00ffff + #00ffff + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + met3.net - 70/23 + 70/23@1 + + + #00ffff + #00ffff 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40/0 + 40/0@1 + + + #ffffcc + #ffffcc + 0 + 0 + C14 + C0 + false + true + false + 1 + false + false + 0 + cviam.maskAdd - 105/21 + 105/21@1 + + + #ffffcc + #ffffcc + 0 + 0 + C3 + C0 + false + true + false + 1 + false + false + 0 + cviam.maskDrop - 105/22 + 105/22@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + C21 + C0 + false + true + false + 1 + false + false + 0 + cmm2.drawing - 105/44 + 105/44@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + C13 + C0 + true + true + false + 1 + false + false + 0 + cmm2.mask - 41/0 + 41/0@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + C14 + C0 + false + true + false + 1 + false + false + 0 + cmm2.maskAdd - 105/43 + 105/43@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + C11 + C0 + false + true + false + 1 + false + false + 0 + cmm2.maskDrop - 105/42 + 105/42@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + cmm2.waffleDrop - 105/52 + 105/52@1 + + + #333399 + #333399 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + false + 0 + cviam2.drawing - 108/20 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areaid.lowTapDensity - 81/14 + 81/14@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + C0 + C7 + true + true + false + 3 + false + false + 0 + areaid.notCritSide - 81/15 + 81/15@1 + + + #adff2f + #adff2f + 0 + 0 + C2 + C7 + true + true + false + 3 + false + false + 0 + areaid.injection - 81/17 + 81/17@1 + + + #bebed8 + #bebed8 + 0 + 0 + C2 + C7 + true + true + false + 3 + false + false + 0 + areaid.rfdiode - 81/125 + 81/125@1 + + + #ffffff + #ffffff + 0 + 0 + C0 + C7 + true + true + false + 3 + false + false + 0 + areaid.seal - 81/1 + 81/1@1 + + + #d9e6ff + #d9e6ff + 0 + 0 + C0 + C7 + true + true + false + 3 + false + false + 0 + areaid.core - 81/2 + 81/2@1 + + + #ffffcc + #ffffcc + 0 + 0 + C0 + C7 + true + true + false + 3 + false + false + 0 + areaid.frame - 81/3 + 81/3@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C0 + C7 + true + true + false + 3 + false + false + 0 + areaid.esd - 81/19 + 81/19@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C0 + C7 + true + true + false + 3 + false + false + 0 + areaid.dieCut - 81/11 + 81/11@1 + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C7 + true + true + false + 3 + false + false + 0 + areaid.moduleCut - 81/10 + 81/10@1 + + + #00ffff + #00ffff + 0 + 0 + C0 + C7 + true + true + false + 3 + false + false + 0 + areaid.frameRect - 81/12 + 81/12@1 + + + #333399 + #ccccd9 + 0 + 0 + C23 + C0 + true + true + false + 1 + false + false + 0 + areaid.substrateCut - 81/53 + 81/53@1 + + + #ffff00 + #ffff00 + 0 + 0 + C0 + C7 + true + true + false + 3 + false + false + 0 + areaid.diode - 81/23 + 81/23@1 + + + #ff00ff + #ff00ff + 0 + 0 + C0 + C7 + true + true + false + 3 + false + false + 0 + areaid.standardc - 81/4 + 81/4@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C0 + C5 + true + true + false + 1 + false + false + 0 + areaid.deadZon - 81/50 + 81/50@1 + + + #ff8000 + #ff8000 + 0 + 0 + C0 + C5 + true + true + false + 1 + false + false + 0 + areaid.critCorner - 81/51 + 81/51@1 + + + #ffffcc + #ffffcc + 0 + 0 + C0 + C5 + true + true + false + 1 + false + false + 0 + areaid.critSid - 81/52 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+ .*.............. + *............... + .......*.......* + ..............*. + .............*.. + ................ + ................ + ................ + .........*...... + ........*....... + + 55 + rain + + + *** + 1 + solid + + + ****.. + 2 + dashed + + + *.. + 3 + dots + + + ***..*.. + 4 + dashDot + + + **.. + 5 + shortDash + + + ****..**.. + 6 + doubleDash + + + *... + 7 + hidden + + + *** + 8 + thickLine + + diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/sky130A.lyt b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/sky130A.lyt new file mode 100755 index 000000000..9a48d2c10 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/libs.tech/klayout/sky130A.lyt @@ -0,0 +1,200 @@ + + + sky130A_el + sky130A Elements + + 0.001 + + sky130A.lyp + true + + + 1 + true + true + + + true + layer_map('66/15 : PY_SHORT';'72/15 : M5_SHORT';'81/14 : LDID';'122/16 : PWELL_PIN';'64/5 : NWELLLABEL';'64/16 : NWELLPT';'64/59 : PWELLLABEL';'64/20 : NWELL';'64/18 : DNWELL';'65/20 : DIFF';'65/44 : TAP';'125/44 : LVTN';'78/44 : HVTP';'75/20 : HVI';'80/20 : TUNM';'66/20 : POLY';'95/20 : NPC';'94/20 : PSDM';'93/44 : NSDM';'66/44 : LICON1';'67/20 : LI1';'67/16 : LI1T';'67/5 : LI1P';'67/44 : MCON';'68/20 : MET1';'68/16 : MET1T';'68/5 : MET1P';'68/44 : VIA1';'69/20 : MET2';'69/16 : MET2T';'69/5 : MET2P';'69/44 : VIA2';'70/20 : MET3';'70/16 : MET3T';'70/5 : MET3P';'70/44 : VIA3';'71/20 : MET4';'71/16 : MET4T';'71/5 : MET4P';'71/44 : VIA4';'72/20 : MET5';'72/16 : MET5T';'72/5 : MET5P';'76/20 : PAD';'76/16 : PADT';'76/5 : PADP';'81/4 : BOUND';'83/44 : TEXT';'18/20 : HVTR';'92/44 : NCM';'86/20 : RPM';'61/20 : NSM';'74/20 : RDL';'74/21 : VHVI';'11/44 : LDNTM';'125/20 : HVNTM';'85/44 : PMM';'82/44 : PNP';'82/64 : CAP';'82/24 : IND';'64/13 : PWRES';'66/13 : POLYRES';'65/13 : DIFFRES';'81/23 : DIODE') + true + true + + + true + layer_map('met1 : met1.drawing (68/20)';'met1.LABEL : met1.label (68/5)';'met1.PIN : met1.pin (68/16)';'via : via.drawing (68/44)';'met2 : met2.drawing (69/20)';'met2.LABEL : met2.label (69/5)';'met2.PIN : met2.pin (69/16)';'via2 : via2.drawing (69/44)';'met3 : met3.drawing (70/20)';'met3.LABEL : met3.label (70/5)';'met3.PIN : met3.pin (70/16)';'via3 : via3.drawing (70/44)';'met4 : met4.drawing (71/20)';'met4.LABEL : met4.label (71/5)';'met4.PIN : met4.pin (71/16)';'via4 : via4.drawing (71/44)';'met5 : met5.drawing (72/20)';'met5.LABEL : met5.label (72/5)';'met5.PIN : met5.pin (72/16)') + 0.001 + true + #1 + true + #1 + false + #1 + true + OUTLINE + true + PLACEMENT_BLK + true + REGIONS + true + + 0 + true + .PIN + 2 + true + .PIN + 2 + true + .FILL + 5 + true + .OBS + 3 + true + .BLK + 4 + true + .LABEL + 1 + true + .LABEL + 1 + true + + 0 + true + + 0 + VIA_ + true + default + false + false + + + + false + true + true + 64 + 0 + 1 + 0 + DATA + 0 + 0 + BORDER + layer_map() + true + + + 0.001 + 1 + 100 + 100 + 0 + 0 + 0 + false + false + false + true + layer_map() + + + 0 + 0.001 + layer_map() + true + false + + + 1 + 0.001 + layer_map() + true + false + true + + + + + + GDS2 + + true + false + false + false + false + false + 8000 + 32000 + LIB + + + 2 + false + false + 1 + * + false + + + 0 + + + false + false + + + 0 + + true + + + + + + + MET4,VIA4,MET5 + MET3,VIA3,MET4 + MET2,VIA2,MET3 + MET1,VIA1,MET2 + LI,MCON,MET1 + POLY,LICON,LI + POLY='66/20' + LICON='66/44' + LI='67/20' + MCON='67/44' + MET1='68/20' + VIA1='68/44' + MET2='69/20' + VIA2='69/44' + MET3='70/20' + VIA3='70/44' + MET4='71/20' + VIA4='71/44' + META5='72/20' + + MET4,VIA4,MET5 + MET3,VIA3,MET4 + MET2,VIA2,MET3 + MET1,VIA1,MET2 + LI,MCON,MET1 + POLY,LICON,LI + POLY='66/20' + LICON='66/44' + LI='67/20' + MCON='67/44' + MET1='68/20' + VIA1='68/44' + MET2='69/20' + VIA2='69/44' + MET3='70/20' + VIA3='70/44' + MET4='71/20' + VIA4='71/44' + META5='72/20' + + diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/meson.build b/pdks/symbolic/nsxlib2/sky130_nsx2/meson.build new file mode 100644 index 000000000..40914f8b4 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/meson.build @@ -0,0 +1,27 @@ + +project( + 'pdk_sky130_nsx2', + version: '0.1.0', + meson_version: '>= 1.2.0', + default_options: ['warning_level=3'] +) + +python = import('python') +py = python.find_installation('python3') +py_deps = py.dependency() + +pdks_dir = py.get_install_dir() / 'pdks' / 'sky130_nsx2' + +find_py = 'find libs.tech/coriolis -type f -name "*.py"' +res = run_command('sh', '-c', find_py, check:true) +py_files = res.stdout().strip().split('\n') + +find_data = 'find libs.tech/coriolis -type f ! -name "*.py"' +res = run_command('sh', '-c', find_data, check:true) +data_files = res.stdout().strip().split('\n') + +py.install_sources( files(py_files) , subdir: 'pdks/sky130_nsx2' ) +py.install_sources( files(data_files) , subdir: 'pdks/sky130_nsx2' ) + +install_subdir( 'libs.tech/klayout' , install_dir: pdks_dir ) + diff --git a/pdks/symbolic/nsxlib2/sky130_nsx2/pyproject.toml b/pdks/symbolic/nsxlib2/sky130_nsx2/pyproject.toml new file mode 100644 index 000000000..d05bdb963 --- /dev/null +++ b/pdks/symbolic/nsxlib2/sky130_nsx2/pyproject.toml @@ -0,0 +1,25 @@ +[project] +name = "pdk_sky130_nsx2" +version = "0.1.0" +description = "Sky130 nsxlib2 PDK for Coriolis EDA" +authors = [ { name = "Coriolis EDA Contributers" } ] +requires-python = ">= 3.8" + +[build-system] +requires = [ + "meson", + "meson-python", + "ninja", + "setuptools", + "cibuildwheel", + "build", + "pdm-backend" +] +build-backend = "mesonpy" + +[tool.meson] +build-dir = "build" + +[tool.cibuildwheel] +build = "cp310-*" +skip = ["cp36-*", "cp37-*", "pp*"] diff --git a/pdks/symbolic/phlib/cells/CATAL b/pdks/symbolic/phlib/cells/CATAL new file mode 100644 index 000000000..2dac959f8 --- /dev/null +++ b/pdks/symbolic/phlib/cells/CATAL @@ -0,0 +1,18 @@ +padreal G +padreal C +padline C +padall C +pck_sp C +pi_sp C +po_sp C +pvddck2_sp C +pvssck2_sp C +ck_buf C +i_buf C +pbuf_c C +pbuf_e C +supplyck_buf C +vssck_con C +vddck_con C +corner_sp C +cornar_sp C diff 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3400,16200,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,8800,CONT_DIF_P,* +V 7000,9600,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,9600,CONT_VIA,* +V 7000,10400,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,9600,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,4800,CONT_DIF_P,* +V 10600,14400,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,14400,CONT_BODY_N,* +V 10600,9600,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 2200,15400,CONT_VIA,* +V 9400,27200,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,24000,CONT_DIF_N,* +V 10600,27200,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 7000,22800,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 10600,30000,CONT_BODY_P,* +V 10600,24800,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 9400,15400,CONT_VIA,* +V 10600,6900,CONT_BODY_N,* +V 9400,6900,CONT_DIF_P,* +V 1000,17800,CONT_BODY_N,* +V 1000,16200,CONT_BODY_N,* +V 1000,19400,CONT_BODY_N,* +V 10600,16100,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/phlib/cells/frame_temp_x1.ap b/pdks/symbolic/phlib/cells/frame_temp_x1.ap new file mode 100644 index 000000000..1f6cad3c1 --- /dev/null +++ b/pdks/symbolic/phlib/cells/frame_temp_x1.ap @@ -0,0 +1,12 @@ +V ALLIANCE : 6 +H frame_temp_x1,P,16/11/2016,100 +A 0,0,12400,31200 +C 6200,31200,6000,pad,0,NORTH,ALU1 +C 6200,31200,6000,pad,1,NORTH,ALU2 +C 12400,8600,9000,vdd,1,EAST,ALU1 +C 12400,19400,4800,vss,1,EAST,ALU1 +C 0,19400,4800,vss,0,WEST,ALU1 +C 0,8600,9000,vdd,0,WEST,ALU1 +C 0,1400,900,ck,0,WEST,ALU1 +C 12400,1400,900,ck,1,EAST,ALU1 +EOF diff --git a/pdks/symbolic/phlib/cells/frame_temp_x2.ap b/pdks/symbolic/phlib/cells/frame_temp_x2.ap new file mode 100644 index 000000000..222bc25f9 --- /dev/null +++ b/pdks/symbolic/phlib/cells/frame_temp_x2.ap @@ -0,0 +1,12 @@ +V ALLIANCE : 6 +H frame_temp_x2,P,16/11/2016,100 +A 0,0,24800,31200 +C 18600,31200,6000,pad,2,NORTH,ALU1 +C 18600,31200,6000,pad,3,NORTH,ALU2 +C 24800,1400,900,ck,2,EAST,ALU1 +C 24800,19400,4800,vss,2,EAST,ALU1 +C 24800,8600,9000,vdd,2,EAST,ALU1 +C 0,19400,4800,vss,0,WEST,ALU1 +C 0,8600,9000,vdd,0,WEST,ALU1 +C 0,1400,900,ck,0,WEST,ALU1 +EOF diff --git a/pdks/symbolic/phlib/cells/i_buf.ap b/pdks/symbolic/phlib/cells/i_buf.ap new file mode 100644 index 000000000..467702528 --- /dev/null +++ b/pdks/symbolic/phlib/cells/i_buf.ap @@ -0,0 +1,423 @@ +V ALLIANCE : 6 +H i_buf,P,30/ 5/2017,100 +A -200,0,12600,31200 +C 7600,31200,1000,pad,0,NORTH,ALU1 +C -200,26400,7600,vss,0,WEST,ALU2 +C -200,11800,18400,vdd,0,WEST,ALU2 +C -200,1400,900,ck,0,WEST,ALU2 +C 12600,1400,900,ck,1,EAST,ALU2 +C 12600,11800,18400,vdd,1,EAST,ALU2 +C 12600,26400,7600,vss,1,EAST,ALU2 +C 3400,0,300,t,0,SOUTH,ALU1 +S 7600,29100,7600,31100,600,*,UP,ALU1 +S 1000,30000,2200,30000,400,*,LEFT,ALU1 +S 1000,28000,2200,28000,400,*,RIGHT,ALU1 +S 1000,27200,2200,27200,400,*,LEFT,ALU1 +S 1000,26400,2200,26400,400,*,RIGHT,ALU1 +S 1000,25600,2200,25600,400,*,LEFT,ALU1 +S 1000,24800,2200,24800,400,*,RIGHT,ALU1 +S 1000,24800,2200,24800,400,*,LEFT,ALU1 +S 1000,24000,2200,24000,400,*,RIGHT,ALU1 +S 1000,22800,2200,22800,400,*,LEFT,ALU1 +S 1000,20800,2200,20800,400,*,RIGHT,ALU1 +S 1000,19400,2200,19400,400,*,LEFT,ALU1 +S 1000,18600,2200,18600,400,*,RIGHT,ALU1 +S 1000,17800,2300,17800,400,*,LEFT,ALU1 +S 1000,17000,2200,17000,400,*,RIGHT,ALU1 +S 1000,16200,2200,16200,400,*,LEFT,ALU1 +S 1000,15400,2200,15400,400,*,RIGHT,ALU1 +S 1000,14400,2200,14400,400,*,LEFT,ALU1 +S 1000,13600,2200,13600,400,*,RIGHT,ALU1 +S 1000,12800,2200,12800,400,*,LEFT,ALU1 +S 1000,12000,2200,12000,400,*,RIGHT,ALU1 +S 1000,11200,2200,11200,400,*,LEFT,ALU1 +S 1000,10400,2200,10400,400,*,RIGHT,ALU1 +S 1000,9600,2200,9600,400,*,LEFT,ALU1 +S 1000,8800,2200,8800,400,*,RIGHT,ALU1 +S 1000,8000,2200,8000,400,*,LEFT,ALU1 +S 1000,7200,2200,7200,400,*,RIGHT,ALU1 +S 1000,6400,2200,6400,400,*,LEFT,ALU1 +S 1000,5600,2200,5600,400,*,RIGHT,ALU1 +S 1000,4800,2200,4800,400,*,LEFT,ALU1 +S 1000,2800,2200,2800,400,*,RIGHT,ALU1 +S 9400,2800,10600,2800,400,*,LEFT,ALU1 +S 9400,4800,10600,4800,400,*,RIGHT,ALU1 +S 9400,5600,10600,5600,400,*,LEFT,ALU1 +S 9400,6400,10600,6400,400,*,RIGHT,ALU1 +S 9400,7200,10600,7200,400,*,LEFT,ALU1 +S 9400,8000,10600,8000,400,*,RIGHT,ALU1 +S 9400,8800,10600,8800,400,*,LEFT,ALU1 +S 9400,9600,10600,9600,400,*,RIGHT,ALU1 +S 9400,10400,10600,10400,400,*,LEFT,ALU1 +S 9400,11200,10600,11200,400,*,RIGHT,ALU1 +S 9400,12000,10600,12000,400,*,LEFT,ALU1 +S 9400,12800,10600,12800,400,*,RIGHT,ALU1 +S 9400,13600,10600,13600,400,*,LEFT,ALU1 +S 9400,14400,10600,14400,400,*,RIGHT,ALU1 +S 9400,17000,10600,17000,400,*,LEFT,ALU1 +S 9400,17800,10600,17800,400,*,RIGHT,ALU1 +S 9400,18600,10600,18600,400,*,LEFT,ALU1 +S 9400,19400,10600,19400,400,*,RIGHT,ALU1 +S 9400,20800,10600,20800,400,*,LEFT,ALU1 +S 9400,22800,10600,22800,400,*,RIGHT,ALU1 +S 9400,24000,10600,24000,400,*,LEFT,ALU1 +S 9400,24800,10600,24800,400,*,RIGHT,ALU1 +S 9400,25600,10600,25600,400,*,LEFT,ALU1 +S 9400,26400,10600,26400,400,*,RIGHT,ALU1 +S 9400,27200,10600,27200,400,*,LEFT,ALU1 +S 9400,28000,10600,28000,400,*,RIGHT,ALU1 +S -350,1400,12650,1400,1300,*,RIGHT,ALU2 +S 3400,100,3400,27900,400,*,UP,ALU1 +S 6400,15400,7000,15400,600,*,RIGHT,POLY +S 6200,1600,6200,21600,12800,*,UP,NWELL +S 6200,21600,6200,31200,12800,*,DOWN,PWELL +S 9500,20800,10500,20800,400,*,LEFT,ALU1 +S 10600,16500,10600,20700,400,*,DOWN,ALU1 +S 9400,16500,9400,20700,400,*,UP,ALU1 +S 1000,2900,1000,20700,400,*,UP,ALU1 +S 1100,20800,2100,20800,400,*,RIGHT,ALU1 +S 2200,2900,2200,20700,400,*,UP,ALU1 +S 700,20800,10900,20800,600,*,LEFT,NTIE +S 8800,28800,8800,29200,200,*,DOWN,POLY +S 9500,22800,10500,22800,400,*,LEFT,ALU1 +S 7000,22900,7000,27900,400,*,UP,ALU1 +S 7100,29000,8100,29000,400,*,LEFT,ALU1 +S 7000,23900,7000,28300,600,*,UP,NDIF +S 2200,23900,2200,28300,600,*,UP,NDIF +S 2800,23700,2800,28500,200,*,UP,NTRANS +S 4000,23700,4000,28500,200,*,UP,NTRANS +S 6400,23700,6400,28500,200,*,UP,NTRANS +S 9400,23900,9400,28300,600,*,UP,NDIF +S 8200,23900,8200,28300,600,*,UP,NDIF +S 8800,23700,8800,28500,200,*,UP,NTRANS +S 8200,3900,8200,28900,400,*,DOWN,ALU1 +S 7100,3800,8100,3800,400,*,LEFT,ALU1 +S 7000,4500,7000,8900,600,*,UP,PDIF +S 2200,4500,2200,8900,600,*,UP,PDIF +S 2800,4300,2800,9100,200,*,UP,PTRANS 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4600,4500,4600,8900,600,*,UP,PDIF +S 6400,4000,7200,4000,200,*,RIGHT,POLY +S 4600,22900,4600,27900,400,*,UP,ALU1 +S 2800,28800,4800,28800,200,*,RIGHT,POLY +S 4700,29000,5700,29000,400,*,LEFT,ALU1 +S 2800,15400,5800,15400,200,*,RIGHT,POLY +S 4600,4900,4600,20700,400,*,UP,ALU1 +S 2800,4000,4800,4000,200,*,RIGHT,POLY +S 5800,3900,5800,28900,400,*,UP,ALU1 +S 4700,3800,5700,3800,400,*,LEFT,ALU1 +S 4700,2800,10500,2800,400,*,LEFT,ALU1 +S 8800,15400,9400,15400,600,*,RIGHT,POLY +S -300,30000,12700,30000,500,*,RIGHT,ALU2 +S -300,28000,12700,28000,500,*,LEFT,ALU2 +S -300,26400,12700,26400,500,*,RIGHT,ALU2 +S -300,24800,12700,24800,500,*,LEFT,ALU2 +S -300,22800,12700,22800,500,*,RIGHT,ALU2 +S -300,20800,12700,20800,500,*,LEFT,ALU2 +S -300,18600,12700,18600,500,*,RIGHT,ALU2 +S -300,17000,12700,17000,500,*,LEFT,ALU2 +S -300,15400,12700,15400,500,*,RIGHT,ALU2 +S -300,13600,12700,13600,500,*,LEFT,ALU2 +S -300,11200,12700,11200,500,*,RIGHT,ALU2 +S -300,9600,12700,9600,500,*,LEFT,ALU2 +S -300,8000,12700,8000,500,*,RIGHT,ALU2 +S -300,5600,12700,5600,500,*,LEFT,ALU2 +S -300,2800,12700,2800,500,*,RIGHT,ALU2 +V 3400,0,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 10600,24800,CONT_VIA,* +V 10600,30000,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 7000,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,27200,CONT_BODY_P,* +V 2200,24000,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,27200,CONT_DIF_N,* +V 2200,15400,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,9600,CONT_VIA,* +V 1000,14400,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,14400,CONT_BODY_N,* +V 9400,4800,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,9600,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,10400,CONT_DIF_P,* +V 2200,9600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,9600,CONT_VIA,* +V 7000,8800,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 5800,17800,CONT_DIF_P,* +V 10600,17000,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 10600,18600,CONT_VIA,* +V 10600,17800,CONT_BODY_N,* +V 10600,19400,CONT_BODY_N,* +V 5800,17000,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 9400,17800,CONT_DIF_P,* +V 9400,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 4600,17000,CONT_VIA,* +V 8200,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 5800,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 7000,20800,CONT_BODY_N,* +V 7000,17000,CONT_VIA,* +V 7000,18600,CONT_VIA,* +V 7000,16200,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 9400,14400,CONT_DIF_P,* +V 9400,22800,CONT_VIA,* +V 7000,29000,CONT_POLY,* +V 7000,3800,CONT_POLY,* +V 10600,22800,CONT_BODY_P,* +V 7000,15400,CONT_POLY,* +V 8200,19400,CONT_DIF_P,* +V 9400,19400,CONT_DIF_P,* +V 10600,2800,CONT_BODY_N,* +V 1000,9600,CONT_VIA,* +V 9400,29000,CONT_POLY,* +V 9400,30000,CONT_BODY_P,* +V 5800,30000,CONT_BODY_P,* +V 1000,30000,CONT_BODY_P,* +V 2200,30000,CONT_BODY_P,* +V 3400,30000,CONT_BODY_P,* +V 4600,29000,CONT_POLY,* +V 5800,15400,CONT_POLY,* +V 4600,3800,CONT_POLY,* +V 9400,15400,CONT_POLY,* +V 9400,15400,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib/cells/i_buf2.ap b/pdks/symbolic/phlib/cells/i_buf2.ap new file mode 100644 index 000000000..2b97c1e91 --- /dev/null +++ b/pdks/symbolic/phlib/cells/i_buf2.ap @@ -0,0 +1,417 @@ +V ALLIANCE : 6 +H i_buf2,P,30/ 5/2017,100 +A -200,0,12600,31200 +C 7600,31200,1000,pad,0,NORTH,ALU1 +C -200,26400,7600,vss,0,WEST,ALU2 +C -200,11800,18400,vdd,0,WEST,ALU2 +C -200,1400,900,ck,0,WEST,ALU2 +C 12600,1400,900,ck,1,EAST,ALU2 +C 12600,11800,18400,vdd,1,EAST,ALU2 +C 12600,26400,7600,vss,1,EAST,ALU2 +S 1000,24000,2200,24000,400,*,LEFT,ALU1 +S 1000,25600,2200,25600,400,*,LEFT,ALU1 +S 1000,28800,2200,28800,400,*,LEFT,ALU1 +S 1000,27200,2200,27200,400,*,LEFT,ALU1 +S 2200,22900,2200,29900,400,*,DOWN,ALU1 +S 7600,29100,7600,31100,600,*,UP,ALU1 +S 1000,20800,2200,20800,400,*,RIGHT,ALU1 +S 1000,19400,2200,19400,400,*,LEFT,ALU1 +S 1000,18600,2200,18600,400,*,RIGHT,ALU1 +S 1000,17800,2200,17800,400,*,LEFT,ALU1 +S 1000,17000,2200,17000,400,*,RIGHT,ALU1 +S 1000,16200,2200,16200,400,*,LEFT,ALU1 +S 1000,15400,2200,15400,400,*,LEFT,ALU1 +S 1000,14400,2200,14400,400,*,RIGHT,ALU1 +S 1000,13600,2200,13600,400,*,LEFT,ALU1 +S 1000,12800,2200,12800,400,*,RIGHT,ALU1 +S 1000,12000,2200,12000,400,*,LEFT,ALU1 +S 1000,11200,2200,11200,400,*,RIGHT,ALU1 +S 1000,10400,2200,10400,400,*,LEFT,ALU1 +S 1000,9600,2200,9600,400,*,RIGHT,ALU1 +S 1000,8800,2200,8800,400,*,LEFT,ALU1 +S 1000,8000,2200,8000,400,*,RIGHT,ALU1 +S 1000,7200,2200,7200,400,*,LEFT,ALU1 +S 1000,6400,2200,6400,400,*,LEFT,ALU1 +S 1000,5600,2200,5600,400,*,RIGHT,ALU1 +S 1000,4800,2200,4800,400,*,LEFT,ALU1 +S 1000,2800,2200,2800,400,*,RIGHT,ALU1 +S 9400,2800,10600,2800,400,*,LEFT,ALU1 +S 9400,4800,10600,4800,400,*,LEFT,ALU1 +S 9400,5600,10600,5600,400,*,RIGHT,ALU1 +S 9400,6400,10600,6400,400,*,LEFT,ALU1 +S 9400,7200,10600,7200,400,*,RIGHT,ALU1 +S 9400,8000,10600,8000,400,*,LEFT,ALU1 +S 9400,8800,10600,8800,400,*,RIGHT,ALU1 +S 9400,9600,10600,9600,400,*,LEFT,ALU1 +S 9400,10400,10600,10400,400,*,RIGHT,ALU1 +S 9400,11200,10600,11200,400,*,LEFT,ALU1 +S 9400,12000,10600,12000,400,*,RIGHT,ALU1 +S 9400,12800,10600,12800,400,*,LEFT,ALU1 +S 9400,13600,10600,13600,400,*,LEFT,ALU1 +S 9400,14400,10600,14400,400,*,RIGHT,ALU1 +S 9400,17000,10600,17000,400,*,LEFT,ALU1 +S 9400,17800,10600,17800,400,*,RIGHT,ALU1 +S 9400,18600,10600,18600,400,*,LEFT,ALU1 +S 9400,19400,10600,19400,400,*,RIGHT,ALU1 +S 9400,20800,10600,20800,400,*,LEFT,ALU1 +S 9400,22800,10600,22800,400,*,RIGHT,ALU1 +S 9400,24000,10600,24000,400,*,LEFT,ALU1 +S 9400,24800,10600,24800,400,*,RIGHT,ALU1 +S 9400,25600,10600,25600,400,*,LEFT,ALU1 +S 9400,26400,10600,26400,400,*,RIGHT,ALU1 +S 9400,27200,10600,27200,400,*,LEFT,ALU1 +S 9400,28000,10600,28000,400,*,RIGHT,ALU1 +S -350,1400,12650,1400,1300,*,RIGHT,ALU2 +S 8800,15400,9400,15400,600,*,RIGHT,POLY +S 4700,2800,10500,2800,400,*,LEFT,ALU1 +S 4700,3800,5700,3800,400,*,LEFT,ALU1 +S 5800,3900,5800,28900,400,*,UP,ALU1 +S 2800,4000,4800,4000,200,*,RIGHT,POLY +S 4600,4900,4600,20700,400,*,UP,ALU1 +S 2800,15400,5800,15400,200,*,RIGHT,POLY +S 4700,29000,5700,29000,400,*,LEFT,ALU1 +S 2800,28800,4800,28800,200,*,RIGHT,POLY +S 4600,22900,4600,27900,400,*,UP,ALU1 +S 6400,4000,7200,4000,200,*,RIGHT,POLY +S 4600,4500,4600,8900,600,*,UP,PDIF +S 5800,4500,5800,8900,600,*,DOWN,PDIF +S 4600,10300,4600,14700,600,*,DOWN,PDIF +S 5800,10300,5800,14700,600,*,DOWN,PDIF +S 4600,16100,4600,19500,600,*,DOWN,PDIF +S 5800,16100,5800,19500,600,*,DOWN,PDIF +S 4600,23900,4600,28300,600,*,UP,NDIF +S 5800,23900,5800,28300,600,*,UP,NDIF +S 6400,28800,7000,28800,200,*,LEFT,POLY +S 1100,30000,5700,30000,400,*,RIGHT,ALU1 +S 1000,22900,1000,29900,400,*,UP,ALU1 +S 9500,30000,10500,30000,400,*,LEFT,ALU1 +S 10600,22900,10600,29900,400,*,UP,ALU1 +S 9400,22900,9400,28900,400,*,UP,ALU1 +S 8800,29000,9400,29000,600,*,RIGHT,POLY +S 2200,22900,2200,28700,400,*,UP,ALU1 +S 7000,4900,7000,14300,400,*,DOWN,ALU1 +S 7000,16300,7000,20700,400,*,UP,ALU1 +S 8800,4100,8800,14900,200,*,UP,PTRANS +S 9400,4300,9400,14700,600,*,DOWN,PDIF +S 8200,4300,8200,14700,600,*,UP,PDIF +S 1000,2500,1000,20900,600,*,UP,NTIE +S 2200,16100,2200,19500,600,*,UP,PDIF +S 700,2800,10900,2800,600,*,LEFT,NTIE +S 2800,15900,2800,19700,200,*,UP,PTRANS +S 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+S 2800,4300,2800,9100,200,*,UP,PTRANS +S 2200,4500,2200,8900,600,*,UP,PDIF +S 7000,4500,7000,8900,600,*,UP,PDIF +S 7100,3800,8100,3800,400,*,LEFT,ALU1 +S 8200,3900,8200,28900,400,*,DOWN,ALU1 +S 8800,23700,8800,28500,200,*,UP,NTRANS +S 8200,23900,8200,28300,600,*,UP,NDIF +S 9400,23900,9400,28300,600,*,UP,NDIF +S 6400,23700,6400,28500,200,*,UP,NTRANS +S 4000,23700,4000,28500,200,*,UP,NTRANS +S 2800,23700,2800,28500,200,*,UP,NTRANS +S 2200,23900,2200,28300,600,*,UP,NDIF +S 7000,23900,7000,28300,600,*,UP,NDIF +S 7100,29000,8100,29000,400,*,LEFT,ALU1 +S 7000,22900,7000,27900,400,*,UP,ALU1 +S 9500,22800,10500,22800,400,*,LEFT,ALU1 +S 8800,28800,8800,29200,200,*,DOWN,POLY +S 700,20800,10900,20800,600,*,LEFT,NTIE +S 2200,2900,2200,20700,400,*,UP,ALU1 +S 1100,20800,2100,20800,400,*,RIGHT,ALU1 +S 1000,2900,1000,20700,400,*,UP,ALU1 +S 9400,16500,9400,20700,400,*,UP,ALU1 +S 10600,16500,10600,20700,400,*,DOWN,ALU1 +S 9500,20800,10500,20800,400,*,LEFT,ALU1 +S 6200,21600,6200,31200,12800,*,DOWN,PWELL +S 6200,1600,6200,21600,12800,*,UP,NWELL +S 6400,15400,7000,15400,600,*,RIGHT,POLY +S 3400,4600,3400,27900,400,*,UP,ALU1 +S -300,30000,12700,30000,500,*,RIGHT,ALU2 +S -300,28000,12700,28000,500,*,LEFT,ALU2 +S -300,26400,12700,26400,500,*,RIGHT,ALU2 +S -300,24800,12700,24800,500,*,LEFT,ALU2 +S -300,22800,12700,22800,500,*,RIGHT,ALU2 +S -300,20800,12700,20800,500,*,LEFT,ALU2 +S -300,18600,12700,18600,500,*,RIGHT,ALU2 +S -300,17000,12700,17000,500,*,LEFT,ALU2 +S -300,15400,12700,15400,500,*,RIGHT,ALU2 +S -300,13600,12700,13600,500,*,LEFT,ALU2 +S -300,11200,12700,11200,500,*,RIGHT,ALU2 +S -300,9600,12700,9600,500,*,LEFT,ALU2 +S -300,8000,12700,8000,500,*,RIGHT,ALU2 +S -300,5600,12700,5600,500,*,LEFT,ALU2 +S -300,2800,12700,2800,500,*,RIGHT,ALU2 +V 9400,15400,CONT_POLY,* +V 4600,3800,CONT_POLY,* +V 5800,15400,CONT_POLY,* +V 4600,29000,CONT_POLY,* +V 3400,30000,CONT_BODY_P,* +V 2200,30000,CONT_BODY_P,* +V 1000,30000,CONT_BODY_P,* +V 5800,30000,CONT_BODY_P,* +V 9400,30000,CONT_BODY_P,* +V 9400,29000,CONT_POLY,* +V 1000,9600,CONT_VIA,* +V 10600,2800,CONT_BODY_N,* +V 9400,19400,CONT_DIF_P,* +V 8200,19400,CONT_DIF_P,* +V 7000,15400,CONT_POLY,* +V 10600,22800,CONT_BODY_P,* +V 7000,3800,CONT_POLY,* +V 7000,29000,CONT_POLY,* +V 9400,22800,CONT_VIA,* +V 9400,14400,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 7000,16200,CONT_DIF_P,* +V 7000,18600,CONT_VIA,* +V 7000,17000,CONT_VIA,* +V 7000,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 5800,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 8200,2800,CONT_BODY_N,* +V 4600,17000,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 9400,17000,CONT_VIA,* +V 9400,17800,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 5800,17000,CONT_DIF_P,* +V 10600,19400,CONT_BODY_N,* +V 10600,17800,CONT_BODY_N,* +V 10600,18600,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 10600,17000,CONT_VIA,* +V 5800,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,8800,CONT_DIF_P,* +V 7000,9600,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,9600,CONT_VIA,* +V 7000,10400,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,9600,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,4800,CONT_DIF_P,* +V 10600,14400,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,14400,CONT_BODY_N,* +V 10600,9600,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 2200,15400,CONT_VIA,* +V 9400,27200,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,24000,CONT_DIF_N,* +V 10600,27200,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 7000,22800,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 10600,30000,CONT_BODY_P,* +V 10600,24800,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 9400,15400,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib/cells/padall.ap b/pdks/symbolic/phlib/cells/padall.ap new file mode 100644 index 000000000..3b777d1ed --- /dev/null +++ b/pdks/symbolic/phlib/cells/padall.ap @@ -0,0 +1,8 @@ +V ALLIANCE : 6 +H padall,P,25/11/2016,100 +A -64000,-128000,128000,0 +I 105600,-230400,padline,east,ROT_M +I -118400,-230400,padline,west,ROT_P +I -102400,-246400,padline,south,SYMXY +I -102400,-22400,padline,north,NOSYM +EOF diff --git a/pdks/symbolic/phlib/cells/padline.ap b/pdks/symbolic/phlib/cells/padline.ap new file mode 100644 index 000000000..7af99baba --- /dev/null +++ b/pdks/symbolic/phlib/cells/padline.ap @@ -0,0 +1,20 @@ +V ALLIANCE : 6 +H padline,P,25/11/2016,100 +A 0,0,204800,12800 +I 0,0,padreal,pad0,NOSYM +I 12800,0,padreal,pad1,NOSYM +I 25600,0,padreal,pad2,NOSYM +I 38400,0,padreal,pad3,NOSYM +I 51200,0,padreal,pad4,NOSYM +I 64000,0,padreal,pad5,NOSYM +I 76800,0,padreal,pad6,NOSYM +I 89600,0,padreal,pad7,NOSYM +I 102400,0,padreal,pad8,NOSYM +I 115200,0,padreal,pad9,NOSYM +I 128000,0,padreal,pad10,NOSYM +I 140800,0,padreal,pad11,NOSYM +I 153600,0,padreal,pad12,NOSYM +I 166400,0,padreal,pad13,NOSYM +I 179200,0,padreal,pad14,NOSYM +I 192000,0,padreal,pad15,NOSYM +EOF diff --git a/pdks/symbolic/phlib/cells/padreal.ap b/pdks/symbolic/phlib/cells/padreal.ap new file mode 100644 index 000000000..394d6f226 --- /dev/null +++ b/pdks/symbolic/phlib/cells/padreal.ap @@ -0,0 +1,4 @@ +V ALLIANCE : 6 +H padreal,P,10/12/2016,100 +A -800,-1300,11200,10200 +EOF diff --git a/pdks/symbolic/phlib/cells/pbuf_c.ap b/pdks/symbolic/phlib/cells/pbuf_c.ap new file mode 100644 index 000000000..e63f1f95c --- /dev/null +++ b/pdks/symbolic/phlib/cells/pbuf_c.ap @@ -0,0 +1,421 @@ +V ALLIANCE : 6 +H pbuf_c,P,15/10/2017,100 +A 0,0,12800,31200 +C 12800,1400,900,ck,1,EAST,ALU2 +C 0,1400,900,ck,0,WEST,ALU1 +C 12000,0,300,i,1,SOUTH,ALU2 +C 12000,0,300,i,0,SOUTH,ALU1 +C 12800,26400,7600,vss,1,EAST,ALU2 +C 12800,11800,18400,vdd,1,EAST,ALU2 +C 0,11800,18400,vdd,0,WEST,ALU1 +C 0,26400,7600,vss,0,WEST,ALU2 +C 3400,31200,1000,pad,0,NORTH,ALU1 +C 5800,31200,1000,pad,1,NORTH,ALU1 +S 3400,30900,5700,30900,400,*,RIGHT,ALU1 +S 900,30000,2200,30000,400,*,RIGHT,ALU1 +S 2200,22900,2200,29800,400,*,UP,ALU1 +S 1000,22800,2200,22800,400,*,LEFT,ALU1 +S 1000,24000,2200,24000,400,*,LEFT,ALU1 +S 1000,25600,2200,25600,400,*,LEFT,ALU1 +S 1000,27200,2200,27200,400,*,LEFT,ALU1 +S 1000,28800,2200,28800,400,*,LEFT,ALU1 +S -100,2800,12900,2800,500,*,RIGHT,ALU2 +S -100,5600,12900,5600,500,*,LEFT,ALU2 +S -100,8000,12900,8000,500,*,RIGHT,ALU2 +S -100,9600,12900,9600,500,*,LEFT,ALU2 +S -100,11200,12900,11200,500,*,RIGHT,ALU2 +S -100,13600,12900,13600,500,*,LEFT,ALU2 +S -100,15400,12900,15400,500,*,RIGHT,ALU2 +S -200,17000,12900,17000,500,*,LEFT,ALU2 +S -100,18600,12900,18600,500,*,RIGHT,ALU2 +S -100,20800,12900,20800,500,*,LEFT,ALU2 +S -100,22800,12900,22800,500,*,RIGHT,ALU2 +S -100,24800,12900,24800,500,*,LEFT,ALU2 +S -100,26400,12900,26400,500,*,RIGHT,ALU2 +S 0,28000,12900,28000,500,*,LEFT,ALU2 +S -100,30000,12900,30000,500,*,RIGHT,ALU2 +S 5800,4900,5800,31300,400,*,UP,ALU1 +S 0,1400,12700,1400,1300,*,RIGHT,ALU2 +S 6400,15400,7000,15400,600,*,RIGHT,POLY +S 2800,15400,6400,15400,200,*,RIGHT,POLY +S 7100,30000,10500,30000,400,*,LEFT,ALU1 +S 6400,1600,6400,21600,12800,*,UP,NWELL +S 6400,21600,6400,31200,12800,*,DOWN,PWELL +S 3400,4900,3400,31300,400,*,UP,ALU1 +S 9500,20800,10500,20800,400,*,LEFT,ALU1 +S 10600,16500,10600,20700,400,*,DOWN,ALU1 +S 9400,16500,9400,20700,400,*,UP,ALU1 +S 4600,2900,4600,20700,400,*,UP,ALU1 +S 1000,2900,1000,20700,400,*,UP,ALU1 +S 1100,20800,2100,20800,400,*,RIGHT,ALU1 +S 2200,2900,2200,20700,400,*,UP,ALU1 +S 700,20800,10900,20800,600,*,LEFT,NTIE +S 8800,28800,8800,29200,200,*,DOWN,POLY +S 8800,29000,9200,29000,600,*,RIGHT,POLY +S 9300,29000,11500,29000,400,*,LEFT,ALU1 +S 9500,22800,10500,22800,400,*,LEFT,ALU1 +S 7000,22900,7000,27900,400,*,UP,ALU1 +S 9400,22900,9400,27900,400,*,UP,ALU1 +S 10600,22900,10600,27900,400,*,UP,ALU1 +S 7100,29000,8100,29000,400,*,LEFT,ALU1 +S 2800,28800,7000,28800,200,*,LEFT,POLY +S 7000,23900,7000,28300,600,*,UP,NDIF +S 2200,23900,2200,28300,600,*,UP,NDIF +S 2800,23700,2800,28500,200,*,UP,NTRANS +S 4000,23700,4000,28500,200,*,UP,NTRANS +S 5200,23700,5200,28500,200,*,UP,NTRANS +S 6400,23700,6400,28500,200,*,UP,NTRANS +S 9400,23900,9400,28300,600,*,UP,NDIF +S 8200,23900,8200,28300,600,*,UP,NDIF +S 8800,23700,8800,28500,200,*,UP,NTRANS +S 8200,3900,8200,28900,400,*,DOWN,ALU1 +S 7100,3800,8100,3800,400,*,LEFT,ALU1 +S 7000,4500,7000,8900,600,*,UP,PDIF +S 2200,4500,2200,8900,600,*,UP,PDIF +S 2800,4300,2800,9100,200,*,UP,PTRANS +S 4000,4300,4000,9100,200,*,UP,PTRANS +S 5200,4300,5200,9100,200,*,UP,PTRANS +S 6400,4300,6400,9100,200,*,UP,PTRANS +S 10600,22500,10600,30300,600,*,DOWN,PTIE +S 1000,22500,1000,30300,600,*,DOWN,PTIE +S 700,22800,10900,22800,600,*,LEFT,PTIE +S 700,30000,10900,30000,600,*,LEFT,PTIE +S 9400,2900,9400,14300,400,*,UP,ALU1 +S 1100,2800,10500,2800,400,*,LEFT,ALU1 +S 7100,15400,8100,15400,400,*,LEFT,ALU1 +S 2200,10300,2200,14700,600,*,UP,PDIF +S 2800,10100,2800,14900,200,*,UP,PTRANS +S 4000,10100,4000,14900,200,*,UP,PTRANS +S 5200,10100,5200,14900,200,*,DOWN,PTRANS +S 7000,10300,7000,14700,600,*,UP,PDIF +S 6400,10100,6400,14900,200,*,UP,PTRANS +S 2800,15000,2800,15800,200,*,UP,POLY +S 4000,15000,4000,15800,200,*,UP,POLY +S 5200,15000,5200,15800,200,*,UP,POLY +S 6400,15000,6400,15800,200,*,UP,POLY +S 8800,15400,9200,15400,600,*,RIGHT,POLY +S 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2200,24000,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,27200,CONT_DIF_N,* +V 2200,15400,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,9600,CONT_VIA,* +V 1000,14400,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,14400,CONT_BODY_N,* +V 9400,4800,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,9600,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,10400,CONT_DIF_P,* +V 2200,9600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,9600,CONT_VIA,* +V 7000,8800,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 5800,17800,CONT_DIF_P,* +V 10600,17000,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 10600,18600,CONT_VIA,* +V 10600,17800,CONT_BODY_N,* +V 10600,19400,CONT_BODY_N,* +V 5800,17000,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 9400,17800,CONT_DIF_P,* +V 9400,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 4600,17000,CONT_VIA,* +V 8200,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 5800,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 3400,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 7000,20800,CONT_BODY_N,* +V 7000,17000,CONT_VIA,* +V 7000,18600,CONT_VIA,* +V 7000,16200,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 9400,14400,CONT_DIF_P,* +V 9200,29000,CONT_POLY,* +V 9400,22800,CONT_VIA,* +V 7000,29000,CONT_POLY,* +V 7000,3800,CONT_POLY,* +V 10600,22800,CONT_BODY_P,* +V 7000,15400,CONT_POLY,* +V 9200,15400,CONT_POLY,* +V 8200,19400,CONT_DIF_P,* +V 9400,19400,CONT_DIF_P,* +V 10600,2800,CONT_BODY_N,* +V 8200,21800,CONT_VIA,* +V 1000,9600,CONT_VIA,* +V 12000,0,CONT_VIA,* +V 1000,19400,CONT_BODY_N,* +V 1000,17800,CONT_BODY_N,* +V 1000,16200,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/phlib/cells/pbuf_e.ap b/pdks/symbolic/phlib/cells/pbuf_e.ap new file mode 100644 index 000000000..16b14f9ed --- /dev/null +++ b/pdks/symbolic/phlib/cells/pbuf_e.ap @@ -0,0 +1,415 @@ +V ALLIANCE : 6 +H pbuf_e,P,30/ 5/2017,100 +A -200,0,12600,31200 +C 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2800,23700,2800,28500,200,*,UP,NTRANS +S 4000,23700,4000,28500,200,*,UP,NTRANS +S 5200,23700,5200,28500,200,*,UP,NTRANS +S 6400,23700,6400,28500,200,*,UP,NTRANS +S 9400,23900,9400,28300,600,*,UP,NDIF +S 8200,23900,8200,28300,600,*,UP,NDIF +S 8800,23700,8800,28500,200,*,UP,NTRANS +S 2200,4500,2200,8900,600,*,UP,PDIF +S 2800,4300,2800,9100,200,*,UP,PTRANS +S 4000,4300,4000,9100,200,*,UP,PTRANS +S 5200,4300,5200,9100,200,*,UP,PTRANS +S 6400,4300,6400,9100,200,*,UP,PTRANS +S 1000,22900,1000,29900,400,*,UP,ALU1 +S 10600,22500,10600,30300,600,*,DOWN,PTIE +S 1000,22500,1000,30300,600,*,DOWN,PTIE +S 700,22800,10900,22800,600,*,LEFT,PTIE +S 700,30000,10900,30000,600,*,LEFT,PTIE +S 9400,2900,9400,14300,400,*,UP,ALU1 +S 2200,10300,2200,14700,600,*,UP,PDIF +S 2800,10100,2800,14900,200,*,UP,PTRANS +S 4000,10100,4000,14900,200,*,UP,PTRANS +S 5200,10100,5200,14900,200,*,DOWN,PTRANS +S 6400,10100,6400,14900,200,*,UP,PTRANS +S 2800,15000,2800,15800,200,*,UP,POLY +S 4000,15000,4000,15800,200,*,UP,POLY +S 5200,15000,5200,15800,200,*,UP,POLY +S 6400,15000,6400,15800,200,*,UP,POLY +S 8800,15400,9200,15400,600,*,RIGHT,POLY +S 9300,15400,11500,15400,400,*,RIGHT,ALU1 +S 8800,15200,8800,15600,200,*,UP,POLY +S 10600,2900,10600,14300,400,*,DOWN,ALU1 +S 10600,2500,10600,20900,600,*,UP,NTIE +S 8800,15900,8800,19700,200,*,UP,PTRANS +S 8200,16100,8200,19500,600,*,UP,PDIF +S 9400,16100,9400,19500,600,*,UP,PDIF +S 6400,15900,6400,19700,200,*,UP,PTRANS +S 5200,15900,5200,19700,200,*,UP,PTRANS +S 4000,15900,4000,19700,200,*,UP,PTRANS +S 2800,15900,2800,19700,200,*,UP,PTRANS +S 700,2800,10900,2800,600,*,LEFT,NTIE +S 2200,16100,2200,19500,600,*,UP,PDIF +S 1000,2500,1000,20900,600,*,UP,NTIE +S 7000,16300,7000,20700,400,*,UP,ALU1 +S 7000,4900,7000,14300,400,*,DOWN,ALU1 +S 11450,21800,12550,21800,600,*,LEFT,ALU2 +S 7600,15900,7600,19700,200,*,DOWN,PTRANS +S 7600,10100,7600,14900,200,*,DOWN,PTRANS +S 7600,4300,7600,9100,200,*,DOWN,PTRANS +S 8800,10100,8800,14900,200,*,UP,PTRANS +S 8800,4300,8800,9100,200,*,DOWN,PTRANS +S 7600,23700,7600,28500,200,*,DOWN,NTRANS +S 2800,4000,8800,4000,200,*,RIGHT,POLY +S 9400,10300,9400,14700,600,*,DOWN,PDIF +S 9400,4500,9400,8900,600,*,UP,PDIF +S 7100,2800,10500,2800,400,*,LEFT,ALU1 +S 1100,2800,4500,2800,400,*,RIGHT,ALU1 +S 5800,3600,5800,4000,600,*,DOWN,POLY +S 2800,15400,8800,15400,200,*,RIGHT,POLY +S 7600,15000,7600,15800,200,*,UP,POLY +S 2800,28800,8800,28800,200,*,LEFT,POLY +S 8200,4900,8200,29900,400,*,DOWN,ALU1 +S 7000,22900,7000,27900,400,*,UP,ALU1 +S 4600,22900,4600,27900,400,*,UP,ALU1 +S 3500,29000,8100,29000,400,*,LEFT,ALU1 +S 5800,4900,5800,28900,400,*,UP,ALU1 +S 3400,4900,3400,28900,400,*,UP,ALU1 +S 1100,30000,6900,30000,400,*,RIGHT,ALU1 +S 9400,28000,10600,28000,400,*,RIGHT,ALU1 +S 9400,27200,10600,27200,400,*,LEFT,ALU1 +S 9400,26400,10600,26400,400,*,RIGHT,ALU1 +S 9400,25600,10600,25600,400,*,LEFT,ALU1 +S 9400,24800,10600,24800,400,*,RIGHT,ALU1 +S 9400,24000,10600,24000,400,*,LEFT,ALU1 +S 9400,22800,10600,22800,400,*,RIGHT,ALU1 +S 9400,20800,10600,20800,400,*,LEFT,ALU1 +S 9400,19400,10600,19400,400,*,RIGHT,ALU1 +S 9400,18600,10600,18600,400,*,LEFT,ALU1 +S 9400,17800,10600,17800,400,*,RIGHT,ALU1 +S 9400,17000,10600,17000,400,*,LEFT,ALU1 +S 9400,14400,10600,14400,400,*,RIGHT,ALU1 +S 9400,13600,10600,13600,400,*,LEFT,ALU1 +S 9400,12800,10600,12800,400,*,RIGHT,ALU1 +S 9400,12000,10600,12000,400,*,LEFT,ALU1 +S 9400,11200,10600,11200,400,*,RIGHT,ALU1 +S 9400,10400,10600,10400,400,*,LEFT,ALU1 +S 9400,9600,10600,9600,400,*,RIGHT,ALU1 +S 9400,8800,10600,8800,400,*,LEFT,ALU1 +S 9400,8000,10600,8000,400,*,RIGHT,ALU1 +S 9400,7200,10600,7200,400,*,LEFT,ALU1 +S 9400,6400,10600,6400,400,*,RIGHT,ALU1 +S 9400,5600,10600,5600,400,*,LEFT,ALU1 +S 9400,4800,10600,4800,400,*,RIGHT,ALU1 +S 9400,2800,10600,2800,400,*,LEFT,ALU1 +S 1000,2800,2200,2800,400,*,RIGHT,ALU1 +S 1000,4800,2200,4800,400,*,LEFT,ALU1 +S 1000,5600,2200,5600,400,*,RIGHT,ALU1 +S 1000,6400,2200,6400,400,*,LEFT,ALU1 +S 1000,7200,2200,7200,400,*,RIGHT,ALU1 +S 1000,8000,2200,8000,400,*,LEFT,ALU1 +S 1000,8800,2200,8800,400,*,RIGHT,ALU1 +S 1000,9600,2200,9600,400,*,LEFT,ALU1 +S 1000,10400,2200,10400,400,*,RIGHT,ALU1 +S 1000,11200,2200,11200,400,*,LEFT,ALU1 +S 1000,12000,2200,12000,400,*,RIGHT,ALU1 +S 1000,12800,2200,12800,400,*,LEFT,ALU1 +S 1000,13600,2200,13600,400,*,RIGHT,ALU1 +S 1000,14400,2200,14400,400,*,LEFT,ALU1 +S 1000,15400,2200,15400,400,*,RIGHT,ALU1 +S 1000,16200,2200,16200,400,*,LEFT,ALU1 +S 1000,17000,2200,17000,400,*,RIGHT,ALU1 +S 1000,17800,2200,17800,400,*,LEFT,ALU1 +S 1000,18600,2200,18600,400,*,RIGHT,ALU1 +S 1000,19400,2200,19400,400,*,LEFT,ALU1 +S 1000,20800,2200,20800,400,*,RIGHT,ALU1 +V 1000,30000,CONT_VIA,* +V 2200,30000,CONT_VIA,* +V 4600,30000,CONT_VIA,* +V 7000,30000,CONT_VIA,* +V 11600,21800,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 10600,24800,CONT_VIA,* +V 7000,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 2200,30000,CONT_BODY_P,* +V 1000,30000,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,27200,CONT_BODY_P,* +V 2200,24000,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,27200,CONT_DIF_N,* +V 2200,15400,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,9600,CONT_VIA,* +V 1000,14400,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,14400,CONT_BODY_N,* +V 9400,4800,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,10400,CONT_DIF_P,* +V 2200,9600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,9600,CONT_VIA,* +V 7000,8800,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 5800,17800,CONT_DIF_P,* +V 10600,17000,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 10600,18600,CONT_VIA,* +V 10600,17800,CONT_BODY_N,* +V 10600,19400,CONT_BODY_N,* +V 5800,17000,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 9400,17800,CONT_DIF_P,* +V 9400,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 4600,17000,CONT_VIA,* +V 8200,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 3400,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 7000,20800,CONT_BODY_N,* +V 7000,17000,CONT_VIA,* +V 7000,18600,CONT_VIA,* +V 7000,16200,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 9400,14400,CONT_DIF_P,* +V 9200,29000,CONT_POLY,* +V 9400,22800,CONT_VIA,* +V 10600,22800,CONT_BODY_P,* +V 9200,15400,CONT_POLY,* +V 8200,19400,CONT_DIF_P,* +V 9400,19400,CONT_DIF_P,* +V 10600,2800,CONT_BODY_N,* +V 5800,3600,CONT_POLY,* +V 7000,30000,CONT_BODY_P,* +V 5800,30000,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 3400,30000,CONT_BODY_P,* +V 1000,9600,CONT_VIA,* +V 1000,19400,CONT_BODY_N,* +V 1000,17800,CONT_BODY_N,* +V 1000,16200,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/phlib/cells/pck_sp.ap b/pdks/symbolic/phlib/cells/pck_sp.ap new file mode 100644 index 000000000..af476f321 --- /dev/null +++ b/pdks/symbolic/phlib/cells/pck_sp.ap @@ -0,0 +1,15 @@ +V ALLIANCE : 6 +H pck_sp,P,18/10/2017,100 +A 0,0,25600,31200 +C 14100,31200,13000,pad,1,NORTH,ALU1 +C 0,1400,1200,ck,0,WEST,ALU2 +C 0,11800,18400,vdd,0,WEST,ALU2 +C 0,26400,7600,vss,0,WEST,ALU2 +C 25600,26400,7600,vss,1,EAST,ALU2 +C 25600,11800,18400,vdd,1,EAST,ALU2 +C 25600,1400,1200,ck,1,EAST,ALU2 +C 25600,19100,200,vdd,2,EAST,ALU2 +S 7900,31100,20300,31100,300,*,RIGHT,ALU1 +I 0,0,ck_buf,ck,NOSYM +I 12800,0,ck_buf,ckbuf_r,NOSYM +EOF diff --git a/pdks/symbolic/phlib/cells/pck_sp.vbe b/pdks/symbolic/phlib/cells/pck_sp.vbe new file mode 100644 index 000000000..ea3ae4ff0 --- /dev/null +++ b/pdks/symbolic/phlib/cells/pck_sp.vbe @@ -0,0 +1,40 @@ +-- VHDL data flow description generated from `pck_sp` +-- date : Thu Feb 23 17:05:59 1995 + + +-- Entity Declaration + +ENTITY pck_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_pad : NATURAL := 1326; -- cin_pad + CONSTANT tpll_pad : NATURAL := 1443; -- tpll_pad + CONSTANT rdown_pad : NATURAL := 58; -- rdown_pad + CONSTANT tphh_pad : NATURAL := 228; -- tphh_pad + CONSTANT rup_pad : NATURAL := 68 -- rup_pad + ); + PORT ( + pad : in BIT; -- pad + ck : out BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vsi + --vdde : in BIT; -- vdde + --vddi : in BIT; -- vddi + --vsse : in BIT; -- vsse + --vssi : in BIT -- vssi + ); +END pck_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pck_sp IS + +BEGIN + ASSERT ((((vdd and vdd)and not (vss)) and not (vss)) = '1') + REPORT "power supply is missing on pck_sp" + SEVERITY WARNING; + + +ck <= pad; +END; diff --git a/pdks/symbolic/phlib/cells/pi_sp.ap b/pdks/symbolic/phlib/cells/pi_sp.ap new file mode 100644 index 000000000..301d0455b --- /dev/null +++ b/pdks/symbolic/phlib/cells/pi_sp.ap @@ -0,0 +1,18 @@ +V ALLIANCE : 6 +H pi_sp,P,18/10/2017,100 +A 0,0,25600,31200 +C 14200,31200,13000,pad,1,NORTH,ALU1 +C 0,26500,7600,vss,1,WEST,ALU2 +C 0,1400,1200,ck,1,WEST,ALU2 +C 0,11900,18400,vdd,1,WEST,ALU2 +C 25600,1300,1200,ck,0,EAST,ALU2 +C 25600,11800,18400,vdd,0,EAST,ALU2 +C 25600,26400,7600,vss,0,EAST,ALU2 +C 3800,0,300,t,0,SOUTH,ALU1 +S 7800,30900,20400,30900,300,*,RIGHT,ALU1 +S 3500,21900,16500,21900,400,*,LEFT,ALU2 +I 0,0,i_buf,ibuf,NOSYM +I 12800,0,i_buf2,ibuf_r,NOSYM +V 3600,21900,CONT_VIA,* +V 16400,21900,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib/cells/pi_sp.vbe b/pdks/symbolic/phlib/cells/pi_sp.vbe new file mode 100644 index 000000000..22d6de503 --- /dev/null +++ b/pdks/symbolic/phlib/cells/pi_sp.vbe @@ -0,0 +1,37 @@ +-- VHDL data flow description generated from `pi_sp` +-- date : Thu Feb 23 17:06:23 1995 + + +-- Entity Declaration + +ENTITY pi_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_pad : NATURAL := 654; -- cin_pad + CONSTANT tpll_pad : NATURAL := 1487; -- tpll_pad + CONSTANT rdown_pad : NATURAL := 234; -- rdown_pad + CONSTANT tphh_pad : NATURAL := 233; -- tphh_pad + CONSTANT rup_pad : NATURAL := 273 -- rup_pad + ); + PORT ( + pad : in BIT; -- pad + t : out BIT; -- t + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + ); +END pi_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pi_sp IS + +BEGIN + ASSERT ((((vdd and vdd) and not (vss)) and not (vss)) = '1') + REPORT "power supply is missing on pi_sp" + SEVERITY WARNING; + + +t <= pad; +END; diff --git a/pdks/symbolic/phlib/cells/po_sp.ap b/pdks/symbolic/phlib/cells/po_sp.ap new file mode 100644 index 000000000..233dc1dd3 --- /dev/null +++ b/pdks/symbolic/phlib/cells/po_sp.ap @@ -0,0 +1,17 @@ +V ALLIANCE : 6 +H po_sp,P,18/10/2017,100 +A 0,0,25600,31200 +C 15800,31200,8000,pad,1,NORTH,ALU1 +C 25600,12000,18400,vdd,1,EAST,ALU2 +C 25600,26400,7600,vss,0,EAST,ALU2 +C 0,11800,18400,vdd,0,WEST,ALU2 +C 0,26600,7600,vss,1,WEST,ALU2 +C 25600,1400,900,ck,2,EAST,ALU2 +C 0,1400,900,ck,1,WEST,ALU2 +C 24800,0,100,i,0,SOUTH,ALU1 +C 25600,1200,200,ck,0,EAST,ALU2 +S 12800,30900,18600,30900,300,*,RIGHT,ALU1 +S 12800,30000,12800,31300,400,*,UP,ALU1 +I 12800,0,pbuf_c,con,NOSYM +I 0,0,pbuf_e,ext,NOSYM +EOF diff --git a/pdks/symbolic/phlib/cells/po_sp.vbe b/pdks/symbolic/phlib/cells/po_sp.vbe new file mode 100644 index 000000000..df9f47c42 --- /dev/null +++ b/pdks/symbolic/phlib/cells/po_sp.vbe @@ -0,0 +1,41 @@ +-- VHDL data flow description generated from `po_sp` +-- date : Thu Feb 23 17:08:20 1995 + + +-- Entity Declaration + +ENTITY po_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_i : NATURAL := 191; -- cin_i + CONSTANT tpll_i : NATURAL := 2176; -- tpll_i + CONSTANT rdown_i : NATURAL := 15; -- rdown_i + CONSTANT tphh_i : NATURAL := 2032; -- tphh_i + CONSTANT rup_i : NATURAL := 16 -- rup_i + ); + PORT ( + i : in BIT; -- i + pad : out BIT; -- pad + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + -- vdde : in BIT; -- vdde + -- vddi : in BIT; -- vddi + -- vsse : in BIT; -- vsse + -- vssi : in BIT -- vssi + ); +END po_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF po_sp IS + +BEGIN + ASSERT ((((vdd and vdd) and not (vss)) and not (vss)) = '1') + REPORT "power supply is missing on po_sp" + SEVERITY WARNING; + + +pad <= i; +END; diff --git a/pdks/symbolic/phlib/cells/pvddck2_sp.ap b/pdks/symbolic/phlib/cells/pvddck2_sp.ap new file mode 100644 index 000000000..21f676ea0 --- /dev/null +++ b/pdks/symbolic/phlib/cells/pvddck2_sp.ap @@ -0,0 +1,16 @@ +V ALLIANCE : 6 +H pvddck2_sp,P,18/10/2017,100 +A 0,0,25600,31200 +C 6200,31200,8000,vdd,4,NORTH,ALU1 +C 11800,0,300,cko,0,SOUTH,ALU1 +C 11800,0,300,cko,1,SOUTH,ALU2 +C 6400,0,3000,vdd,0,SOUTH,ALU1 +C 0,1400,1200,ck,0,WEST,ALU2 +C 0,11800,18400,vdd,1,WEST,ALU2 +C 0,26400,7600,vss,0,WEST,ALU2 +C 25600,1400,1200,ck,1,EAST,ALU2 +C 25600,11800,18400,vdd,2,EAST,ALU2 +C 25600,26400,7600,vss,1,EAST,ALU2 +I 0,0,vddck_con,con,NOSYM +I 12800,0,supplyck_buf,buf,NOSYM +EOF diff --git a/pdks/symbolic/phlib/cells/pvddck2_sp.vbe b/pdks/symbolic/phlib/cells/pvddck2_sp.vbe new file mode 100644 index 000000000..ea0afc33d --- /dev/null +++ b/pdks/symbolic/phlib/cells/pvddck2_sp.vbe @@ -0,0 +1,42 @@ +-- VHDL data flow description generated from `pvddck2_sp` +-- date : Thu Feb 23 17:11:45 1995 + + +-- Entity Declaration + +ENTITY pvddck2_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_ck : NATURAL := 127; -- cin_ck + CONSTANT tpll_ck : NATURAL := 1055; -- tpll_ck + CONSTANT rdown_ck : NATURAL := 126; -- rdown_ck + CONSTANT tphh_ck : NATURAL := 963; -- tphh_ck + CONSTANT rup_ck : NATURAL := 183 -- rup_ck + ); + PORT ( + cko : out WOR_BIT BUS; -- cko + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + -- vdde : in BIT; -- vdde + -- vddi : in BIT; -- vddi + -- vsse : in BIT; -- vsse + -- vssi : in BIT -- vssi + ); +END pvddck2_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvddck2_sp IS + +BEGIN + ASSERT ((((not (vss) and not (vss)) and vdd) and vdd) = '1') + REPORT "power supply is missing on pvddck2_sp" + SEVERITY WARNING; + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; +END; diff --git a/pdks/symbolic/phlib/cells/pvssck2_sp.ap b/pdks/symbolic/phlib/cells/pvssck2_sp.ap new file mode 100644 index 000000000..df75f8f74 --- /dev/null +++ b/pdks/symbolic/phlib/cells/pvssck2_sp.ap @@ -0,0 +1,19 @@ +V ALLIANCE : 6 +H pvssck2_sp,P,18/10/2017,100 +A 0,0,25600,31200 +C 6200,31200,8000,vss,5,NORTH,ALU1 +C 6400,0,3000,vss,1,SOUTH,ALU2 +C 6400,0,3000,vss,0,SOUTH,ALU1 +C 11800,0,300,cko,0,SOUTH,ALU1 +C 11800,0,300,cko,1,SOUTH,ALU2 +C 25600,1500,1200,ck,1,EAST,ALU2 +C 25600,11800,18400,vdd,1,EAST,ALU2 +C 25600,26400,7600,vss,3,EAST,ALU2 +C 0,1400,1200,ck,0,WEST,ALU2 +C 0,11600,18400,vdd,0,WEST,ALU2 +C 0,26400,7600,vss,2,WEST,ALU2 +C 12700,26700,200,vss,4,EAST,ALU2 +C 12700,16200,200,vdd,2,EAST,ALU2 +I 0,0,vssck_con,con,NOSYM +I 12800,0,supplyck_buf,buf,NOSYM +EOF diff --git a/pdks/symbolic/phlib/cells/pvssck2_sp.vbe b/pdks/symbolic/phlib/cells/pvssck2_sp.vbe new file mode 100644 index 000000000..1aadc0998 --- /dev/null +++ b/pdks/symbolic/phlib/cells/pvssck2_sp.vbe @@ -0,0 +1,42 @@ +-- VHDL data flow description generated from `pvssck2_sp` +-- date : Thu Feb 23 17:11:45 1995 + + +-- Entity Declaration + +ENTITY pvssck2_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_ck : NATURAL := 127; -- cin_ck + CONSTANT tpll_ck : NATURAL := 1055; -- tpll_ck + CONSTANT rdown_ck : NATURAL := 126; -- rdown_ck + CONSTANT tphh_ck : NATURAL := 963; -- tphh_ck + CONSTANT rup_ck : NATURAL := 183 -- rup_ck + ); + PORT ( + cko : out WOR_BIT BUS; -- cko + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + -- vdde : in BIT; -- vdde + -- vddi : in BIT; -- vddi + -- vsse : in BIT; -- vsse + -- vssi : in BIT -- vssi + ); +END pvssck2_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvssck2_sp IS + +BEGIN + ASSERT ((((not (vss) and not (vss)) and vdd) and vdd) = '1') + REPORT "power supply is missing on pvssck2_sp" + SEVERITY WARNING; + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; +END; diff --git a/pdks/symbolic/phlib/cells/supplyck_buf.ap b/pdks/symbolic/phlib/cells/supplyck_buf.ap new file mode 100644 index 000000000..78538f00c --- /dev/null +++ b/pdks/symbolic/phlib/cells/supplyck_buf.ap @@ -0,0 +1,383 @@ +V ALLIANCE : 6 +H supplyck_buf,P,31/ 5/2017,100 +A 0,0,12800,31200 +C 12800,26400,7600,vss,1,EAST,ALU2 +C 12800,11800,18400,vdd,1,EAST,ALU2 +C 12800,1400,900,ck,1,EAST,ALU2 +C 0,1400,900,ck,0,WEST,ALU2 +C 0,11800,18400,vdd,0,WEST,ALU2 +C 0,26400,7600,vss,0,WEST,ALU2 +S 1000,20800,2200,20800,400,*,LEFT,ALU1 +S 1000,18600,2200,18600,400,*,LEFT,ALU1 +S 1000,17000,2200,17000,400,*,LEFT,ALU1 +S 1000,15400,2200,15400,400,*,LEFT,ALU1 +S 1000,13600,2200,13600,400,*,LEFT,ALU1 +S 1000,11200,2200,11200,400,*,RIGHT,ALU1 +S 1000,9600,2200,9600,400,*,RIGHT,ALU1 +S 1000,8000,2200,8000,400,*,RIGHT,ALU1 +S 1000,5600,2200,5600,400,*,LEFT,ALU1 +S 9400,5600,10600,5600,400,*,RIGHT,ALU1 +S 9400,8000,10600,8000,400,*,LEFT,ALU1 +S 9400,9600,10600,9600,400,*,LEFT,ALU1 +S 9400,11200,10600,11200,400,*,LEFT,ALU1 +S 9400,13600,10600,13600,400,*,RIGHT,ALU1 +S 9400,17000,10600,17000,400,*,RIGHT,ALU1 +S 9400,18600,10600,18600,400,*,RIGHT,ALU1 +S 9400,20800,10600,20800,400,*,RIGHT,ALU1 +S 1000,24800,2200,24800,400,*,RIGHT,ALU1 +S 1000,26400,2200,26400,400,*,RIGHT,ALU1 +S 1000,28000,2200,28000,400,*,RIGHT,ALU1 +S 9400,28000,10600,28000,400,*,LEFT,ALU1 +S 9400,26400,10600,26400,400,*,LEFT,ALU1 +S 9400,24800,10600,24800,400,*,LEFT,ALU1 +S 6400,21600,6400,31200,13200,*,DOWN,PWELL +S 6400,1600,6400,21600,13200,*,UP,NWELL +S 11700,1400,11700,29000,400,*,DOWN,ALU1 +S 2800,4000,7200,4000,200,*,RIGHT,POLY +S 1000,22900,1000,28700,400,*,UP,ALU1 +S 2200,22900,2200,28700,400,*,UP,ALU1 +S 4600,22900,4600,29900,400,*,UP,ALU1 +S 7000,4900,7000,14300,400,*,DOWN,ALU1 +S 7000,16300,7000,20700,400,*,UP,ALU1 +S 8800,4100,8800,14900,200,*,UP,PTRANS +S 9400,4300,9400,14700,600,*,DOWN,PDIF +S 8200,4300,8200,14700,600,*,UP,PDIF +S 1000,2500,1000,20900,600,*,UP,NTIE +S 2200,16100,2200,19500,600,*,UP,PDIF +S 700,2800,10900,2800,600,*,LEFT,NTIE +S 2800,15900,2800,19700,200,*,UP,PTRANS +S 4000,15900,4000,19700,200,*,UP,PTRANS +S 5200,15900,5200,19700,200,*,UP,PTRANS +S 7000,16100,7000,19500,600,*,UP,PDIF +S 6400,15900,6400,19700,200,*,UP,PTRANS +S 9400,16100,9400,19500,600,*,UP,PDIF +S 8200,16100,8200,19500,600,*,UP,PDIF +S 8800,15900,8800,19700,200,*,UP,PTRANS +S 10600,2500,10600,20900,600,*,UP,NTIE +S 10600,2900,10600,14300,400,*,DOWN,ALU1 +S 8800,15200,8800,15600,200,*,UP,POLY +S 9300,15400,11500,15400,400,*,RIGHT,ALU1 +S 8800,15400,9200,15400,600,*,RIGHT,POLY +S 6400,15000,6400,15800,200,*,UP,POLY +S 5200,15000,5200,15800,200,*,UP,POLY +S 4000,15000,4000,15800,200,*,UP,POLY +S 2800,15000,2800,15800,200,*,UP,POLY +S 6400,10100,6400,14900,200,*,UP,PTRANS +S 7000,10300,7000,14700,600,*,UP,PDIF +S 5200,10100,5200,14900,200,*,DOWN,PTRANS +S 4000,10100,4000,14900,200,*,UP,PTRANS +S 2800,10100,2800,14900,200,*,UP,PTRANS +S 2200,10300,2200,14700,600,*,UP,PDIF +S 7100,15400,8100,15400,400,*,LEFT,ALU1 +S 1100,2800,10500,2800,400,*,LEFT,ALU1 +S 9400,2900,9400,14300,400,*,UP,ALU1 +S 700,30000,10900,30000,600,*,LEFT,PTIE +S 700,22800,10900,22800,600,*,LEFT,PTIE +S 1000,22500,1000,30300,600,*,DOWN,PTIE +S 10600,22500,10600,30300,600,*,DOWN,PTIE +S 6400,4300,6400,9100,200,*,UP,PTRANS +S 5200,4300,5200,9100,200,*,UP,PTRANS +S 4000,4300,4000,9100,200,*,UP,PTRANS +S 2800,4300,2800,9100,200,*,UP,PTRANS +S 2200,4500,2200,8900,600,*,UP,PDIF +S 7000,4500,7000,8900,600,*,UP,PDIF +S 7100,3800,8100,3800,400,*,LEFT,ALU1 +S 8800,23700,8800,28500,200,*,UP,NTRANS +S 8200,23900,8200,28300,600,*,UP,NDIF +S 9400,23900,9400,28300,600,*,UP,NDIF +S 6400,23700,6400,28500,200,*,UP,NTRANS +S 5200,23700,5200,28500,200,*,UP,NTRANS +S 4000,23700,4000,28500,200,*,UP,NTRANS +S 2800,23700,2800,28500,200,*,UP,NTRANS +S 2200,23900,2200,28300,600,*,UP,NDIF +S 7000,23900,7000,28300,600,*,UP,NDIF +S 2800,28800,7000,28800,200,*,LEFT,POLY +S 7100,29000,8100,29000,400,*,LEFT,ALU1 +S 10600,22900,10600,27900,400,*,UP,ALU1 +S 9400,22900,9400,27900,400,*,UP,ALU1 +S 7000,22900,7000,27900,400,*,UP,ALU1 +S 9500,22800,10500,22800,400,*,LEFT,ALU1 +S 9300,29000,11500,29000,400,*,LEFT,ALU1 +S 8800,29000,9200,29000,600,*,RIGHT,POLY +S 8800,28800,8800,29200,200,*,DOWN,POLY +S 700,20800,10900,20800,600,*,LEFT,NTIE +S 2200,2900,2200,20700,400,*,UP,ALU1 +S 1100,20800,2100,20800,400,*,RIGHT,ALU1 +S 1000,2900,1000,20700,400,*,UP,ALU1 +S 4600,2900,4600,20700,400,*,UP,ALU1 +S 9400,16500,9400,20700,400,*,UP,ALU1 +S 10600,16500,10600,20700,400,*,DOWN,ALU1 +S 9500,20800,10500,20800,400,*,LEFT,ALU1 +S 7100,30000,10500,30000,400,*,LEFT,ALU1 +S 2800,15400,6400,15400,200,*,RIGHT,POLY +S 6400,15400,7000,15400,600,*,RIGHT,POLY +S 5800,4900,5800,28100,400,*,UP,ALU1 +S 3400,4900,3400,28100,400,*,UP,ALU1 +S -150,21800,5950,21800,600,*,LEFT,ALU2 +S 50,1400,12750,1400,1300,*,LEFT,ALU2 +S 8200,3800,8200,28900,400,*,DOWN,ALU1 +S -100,26400,12900,26400,500,*,LEFT,ALU2 +S -100,24800,12900,24800,500,*,RIGHT,ALU2 +S -100,28000,12900,28000,500,*,RIGHT,ALU2 +S -100,30000,12900,30000,500,*,LEFT,ALU2 +S 900,22800,10700,22800,500,*,LEFT,ALU2 +S -200,20800,12900,20800,500,*,RIGHT,ALU2 +S -100,18600,12900,18600,500,*,RIGHT,ALU2 +S -100,17000,12900,17000,500,*,LEFT,ALU2 +S -100,15400,12900,15400,500,*,RIGHT,ALU2 +S -100,13600,12900,13600,500,*,LEFT,ALU2 +S -100,11200,12900,11200,500,*,RIGHT,ALU2 +S -100,9600,12900,9600,500,*,LEFT,ALU2 +S -100,8000,12900,8000,500,*,RIGHT,ALU2 +S -100,5600,12900,5600,500,*,LEFT,ALU2 +S -100,2800,12900,2800,500,*,RIGHT,ALU2 +V 1000,16200,CONT_BODY_N,* +V 1000,17800,CONT_BODY_N,* +V 1000,19400,CONT_BODY_N,* +V 11700,1400,CONT_VIA,* +V 1000,9600,CONT_VIA,* +V 10600,2800,CONT_BODY_N,* +V 9400,19400,CONT_DIF_P,* +V 8200,19400,CONT_DIF_P,* +V 9200,15400,CONT_POLY,* +V 7000,15400,CONT_POLY,* +V 10600,22800,CONT_BODY_P,* +V 7000,3800,CONT_POLY,* +V 7000,29000,CONT_POLY,* +V 9400,22800,CONT_VIA,* +V 9200,29000,CONT_POLY,* +V 9400,14400,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 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10600,17000,CONT_VIA,* +V 5800,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,8800,CONT_DIF_P,* +V 7000,9600,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,9600,CONT_VIA,* +V 7000,10400,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,9600,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,4800,CONT_DIF_P,* +V 10600,14400,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,14400,CONT_BODY_N,* +V 10600,9600,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 2200,15400,CONT_VIA,* +V 9400,27200,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,24000,CONT_DIF_N,* +V 10600,27200,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 7000,22800,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 10600,30000,CONT_BODY_P,* +V 7000,30000,CONT_BODY_P,* +V 9400,30000,CONT_VIA,* +V 8200,30000,CONT_VIA,* +V 10600,24800,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 5800,21800,CONT_VIA,* +V 3400,21800,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib/cells/vddck_con.ap b/pdks/symbolic/phlib/cells/vddck_con.ap new file mode 100644 index 000000000..a6a26344d --- /dev/null +++ b/pdks/symbolic/phlib/cells/vddck_con.ap @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H vddck_con,P,13/10/2017,100 +A -200,0,12600,31200 +C 5400,31200,6000,pad,0,NORTH,ALU1 +C 12600,26400,7600,vss,1,EAST,ALU2 +C 12600,11700,18400,vdd,1,EAST,ALU2 +C 12600,1400,900,ck,1,EAST,ALU2 +C 11400,0,300,cko,1,NORTH,ALU2 +C 11400,0,300,cko,0,SOUTH,ALU1 +C 6000,0,3000,vdd,0,SOUTH,ALU1 +C -200,1400,900,ck,0,WEST,ALU2 +C -200,11800,18400,vdd,2,WEST,ALU2 +C -200,26400,7600,vss,0,WEST,ALU2 +S 2200,8600,9800,8600,12000,*,RIGHT,ALU1 +S 6000,-100,6000,2500,8000,*,DOWN,ALU1 +S 11400,-200,11400,21900,500,*,DOWN,ALU1 +S -500,1400,12500,1400,1300,*,RIGHT,ALU2 +S 6000,2650,6000,14550,8000,*,UP,ALU2 +S -300,26400,12500,26400,7600,*,RIGHT,ALU2 +S -400,11800,1900,11800,18400,*,LEFT,ALU2 +S 6000,2650,6000,20850,8000,*,UP,ALU2 +S 6000,14900,6000,31000,8000,*,DOWN,ALU1 +S 11250,21800,12550,21800,600,*,LEFT,ALU2 +S 10000,11700,12500,11700,18400,*,RIGHT,ALU2 +B 6000,11800,7800,18200,CONT_VIA,* +V 11400,21800,CONT_VIA,* +V 11400,0,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib/cells/vssck_con.ap b/pdks/symbolic/phlib/cells/vssck_con.ap new file mode 100644 index 000000000..927820971 --- /dev/null +++ b/pdks/symbolic/phlib/cells/vssck_con.ap @@ -0,0 +1,25 @@ +V ALLIANCE : 6 +H vssck_con,P,13/10/2017,100 +A -200,0,12600,31200 +C 6000,31200,6000,pad,0,NORTH,ALU1 +C 6000,31200,6000,pad,1,NORTH,ALU2 +C 12600,26400,7600,vss,2,EAST,ALU2 +C 12600,11600,18000,vdd,1,EAST,ALU2 +C 12600,1400,900,ck,1,EAST,ALU2 +C 6000,0,3000,vss,0,SOUTH,ALU1 +C 11400,0,300,cko,1,NORTH,ALU2 +C 11400,0,300,cko,0,SOUTH,ALU1 +C -200,1400,900,ck,0,WEST,ALU2 +C -200,11600,18000,vdd,0,WEST,ALU2 +C -200,26400,7600,vss,1,WEST,ALU2 +S -300,1400,12600,1400,1300,*,RIGHT,ALU2 +S -300,11800,12600,11800,18400,*,RIGHT,ALU2 +S 11250,21800,12550,21800,600,*,LEFT,ALU2 +S -200,26400,12600,26400,7600,*,RIGHT,ALU2 +S 11400,-100,11400,21800,500,*,UP,ALU1 +S 6000,22950,6000,31050,8000,*,UP,ALU2 +S 6000,-100,6000,31100,8000,*,DOWN,ALU1 +B 6050,26400,8100,7600,CONT_VIA,* +V 11400,0,CONT_VIA,* +V 11400,21800,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib80/cells/CATAL b/pdks/symbolic/phlib80/cells/CATAL new file mode 100644 index 000000000..35312bbfd --- /dev/null +++ b/pdks/symbolic/phlib80/cells/CATAL @@ -0,0 +1,21 @@ +padreal G +padreal C +padline C +padall C +pck_sp C +pi_sp C +po_sp C +pod_sp C +pvddck2_sp C +pvssck2_sp C +ck_buf C +i_buf C +pbuf_c C +pbuf_e C +pbuf_oc C +pbuf_oe C +supplyck_buf C +vssck_con C +vddck_con C +corner_sp C +cornar_sp C diff --git a/pdks/symbolic/phlib80/cells/ck_buf.ap b/pdks/symbolic/phlib80/cells/ck_buf.ap new file mode 100644 index 000000000..a222871cb --- /dev/null +++ b/pdks/symbolic/phlib80/cells/ck_buf.ap @@ -0,0 +1,415 @@ +V ALLIANCE : 6 +H ck_buf,P,15/ 8/2019,100 +A 0,0,12300,31200 +C 12300,26400,7600,vss,2,EAST,ALU2 +C 12300,11800,18400,vdd,2,EAST,ALU2 +C 12300,1400,900,ck,2,EAST,ALU2 +C 0,26400,7600,vss,1,WEST,ALU2 +C 0,11800,18400,vdd,1,WEST,ALU2 +C 0,1400,900,ck,1,WEST,ALU2 +C 7800,31200,1000,pad,1,NORTH,ALU1 +S 0,1400,12300,1400,1300,ck,RIGHT,CALU2 +S 0,2800,12300,2800,500,vdd,LEFT,CALU2 +S 0,5600,12300,5600,500,vdd,RIGHT,CALU2 +S 0,8000,12300,8000,500,vdd,LEFT,CALU2 +S 0,9600,12300,9600,500,vdd,RIGHT,CALU2 +S 0,11200,12300,11200,500,vdd,LEFT,CALU2 +S 0,13600,12300,13600,500,vdd,RIGHT,CALU2 +S 0,15400,12300,15400,500,vdd,LEFT,CALU2 +S 0,17000,12300,17000,500,vdd,RIGHT,CALU2 +S 0,18600,12300,18600,500,vdd,LEFT,CALU2 +S 0,20800,12300,20800,500,vdd,RIGHT,CALU2 +S 0,22800,12300,22800,500,vss,LEFT,CALU2 +S 0,24800,12300,24800,500,vss,RIGHT,CALU2 +S 0,26400,12300,26400,500,vss,LEFT,CALU2 +S 0,28000,12300,28000,500,vss,RIGHT,CALU2 +S 0,30000,12300,30000,500,vss,RIGHT,CALU2 +S 9400,22800,9400,29100,400,*,UP,ALU1 +S 7000,29100,8200,29100,400,*,LEFT,ALU1 +S 5800,3800,5800,29100,400,*,UP,ALU1 +S 4600,29100,5800,29100,400,*,LEFT,ALU1 +S 9400,16500,9400,20900,400,*,UP,ALU1 +S 10600,16000,10600,20900,400,*,DOWN,ALU1 +S 10600,2800,10600,14400,400,*,DOWN,ALU1 +S 9400,2800,9400,14400,400,*,UP,ALU1 +S 4600,4800,4600,20800,400,*,UP,ALU1 +S 9400,30000,10600,30000,400,*,LEFT,ALU1 +S 4600,22800,4600,28000,400,*,UP,ALU1 +S 3400,1000,3400,28000,400,*,UP,ALU1 +S 7000,16200,7000,20800,400,*,UP,ALU1 +S 8200,3800,8200,29200,400,*,DOWN,ALU1 +S 7000,3800,8200,3800,400,*,LEFT,ALU1 +S 4600,2800,10600,2800,400,*,LEFT,ALU1 +S 4600,3800,5800,3800,400,*,LEFT,ALU1 +S 7000,4800,7000,14400,400,*,DOWN,ALU1 +S 7000,15400,8100,15400,400,*,LEFT,ALU1 +S 7000,22800,7000,28000,400,*,UP,ALU1 +S 1000,30000,5800,30000,400,*,RIGHT,ALU1 +S 1000,20800,2200,20800,400,*,RIGHT,ALU1 +S 2200,2800,2200,20800,400,*,UP,ALU1 +S 1000,2800,1000,20800,400,*,UP,ALU1 +S 10600,22800,10600,29900,400,*,UP,ALU1 +S 2200,22800,2200,28700,400,*,UP,ALU1 +S 1000,22800,1000,30000,400,*,UP,ALU1 +S 2800,29000,4700,29000,200,*,RIGHT,POLY +S 1000,2800,1000,19400,400,*,DOWN,ALU1 +S 1000,18600,2200,18600,400,*,RIGHT,ALU1 +S 1000,17000,2200,17000,400,*,RIGHT,ALU1 +S 1000,15400,2200,15400,400,*,RIGHT,ALU1 +S 1000,13600,2200,13600,400,*,RIGHT,ALU1 +S 1000,11200,2200,11200,400,*,LEFT,ALU1 +S 1000,9600,2200,9600,400,*,LEFT,ALU1 +S 1000,8000,2200,8000,400,*,LEFT,ALU1 +S 1000,5600,2200,5600,400,*,RIGHT,ALU1 +S 1000,2800,2200,2800,400,*,RIGHT,ALU1 +S 9400,5600,10600,5600,400,*,RIGHT,ALU1 +S 9400,8000,10600,8000,400,*,LEFT,ALU1 +S 9400,9600,10600,9600,400,*,LEFT,ALU1 +S 9400,9600,10600,9600,400,*,RIGHT,ALU1 +S 9400,11200,10600,11200,400,*,RIGHT,ALU1 +S 9400,13600,10600,13600,400,*,LEFT,ALU1 +S 9400,17000,10600,17000,400,*,LEFT,ALU1 +S 9400,18600,10600,18600,400,*,LEFT,ALU1 +S 9400,20800,10600,20800,400,*,LEFT,ALU1 +S 9400,22800,10600,22800,400,*,RIGHT,ALU1 +S 9400,24800,10600,24800,400,*,RIGHT,ALU1 +S 9400,26400,10600,26400,400,*,RIGHT,ALU1 +S 9400,28000,10600,28000,400,*,RIGHT,ALU1 +S -300,2800,12700,2800,500,*,RIGHT,ALU2 +S -300,5600,12700,5600,500,*,LEFT,ALU2 +S -300,8000,12700,8000,500,*,RIGHT,ALU2 +S -300,9600,12700,9600,500,*,LEFT,ALU2 +S -300,11200,12700,11200,500,*,RIGHT,ALU2 +S -300,13600,12700,13600,500,*,LEFT,ALU2 +S -300,15400,12700,15400,500,*,RIGHT,ALU2 +S -300,17000,12700,17000,500,*,LEFT,ALU2 +S -300,18600,12700,18600,500,*,RIGHT,ALU2 +S -300,20800,12700,20800,500,*,LEFT,ALU2 +S -300,22800,12700,22800,500,*,RIGHT,ALU2 +S -300,24800,12700,24800,500,*,LEFT,ALU2 +S -300,26400,12700,26400,500,*,RIGHT,ALU2 +S -300,28000,12700,28000,500,*,LEFT,ALU2 +S -300,30000,12700,30000,500,*,RIGHT,ALU2 +S 6400,15400,7000,15400,600,*,RIGHT,POLY +S 6200,1600,6200,21600,12800,*,UP,NWELL +S 6200,21600,6200,31200,12800,*,DOWN,PWELL +S 9500,20800,10500,20800,400,*,LEFT,ALU1 +S 700,20800,10900,20800,600,*,LEFT,NTIE +S 9500,22800,10500,22800,400,*,LEFT,ALU1 +S 7000,23900,7000,28300,600,*,UP,NDIF +S 2200,23900,2200,28300,600,*,UP,NDIF +S 2800,23700,2800,28500,200,*,UP,NTRANS +S 4000,23700,4000,28500,200,*,UP,NTRANS +S 6400,23700,6400,28500,200,*,UP,NTRANS +S 9400,23900,9400,28300,600,*,UP,NDIF +S 8200,23900,8200,28300,600,*,UP,NDIF +S 8800,23700,8800,28500,200,*,UP,NTRANS +S 7000,4500,7000,8900,600,*,UP,PDIF +S 2200,4500,2200,8900,600,*,UP,PDIF +S 2800,4300,2800,9100,200,*,UP,PTRANS +S 4000,4300,4000,9100,200,*,UP,PTRANS +S 6400,4300,6400,9100,200,*,UP,PTRANS +S 10600,22500,10600,30300,600,*,DOWN,PTIE +S 1000,22500,1000,30300,600,*,DOWN,PTIE +S 700,22800,10900,22800,600,*,LEFT,PTIE +S 700,30000,10900,30000,600,*,LEFT,PTIE +S 2200,10300,2200,14700,600,*,UP,PDIF +S 2800,10100,2800,14900,200,*,UP,PTRANS +S 4000,10100,4000,14900,200,*,UP,PTRANS +S 7000,10300,7000,14700,600,*,UP,PDIF +S 6400,10100,6400,14900,200,*,UP,PTRANS +S 2800,15000,2800,15800,200,*,UP,POLY +S 4000,15000,4000,15800,200,*,UP,POLY +S 6400,15000,6400,15800,200,*,UP,POLY +S 8800,15200,8800,15600,200,*,UP,POLY +S 10600,2500,10600,20900,600,*,UP,NTIE +S 8800,15900,8800,19700,200,*,UP,PTRANS +S 8200,16100,8200,19500,600,*,UP,PDIF +S 9400,16100,9400,19500,600,*,UP,PDIF +S 6400,15900,6400,19700,200,*,UP,PTRANS +S 7000,16100,7000,19500,600,*,UP,PDIF +S 4000,15900,4000,19700,200,*,UP,PTRANS +S 2800,15900,2800,19700,200,*,UP,PTRANS +S 700,2800,10900,2800,600,*,LEFT,NTIE +S 2200,16100,2200,19500,600,*,UP,PDIF +S 1000,2500,1000,20900,600,*,UP,NTIE +S 8200,4300,8200,14700,600,*,UP,PDIF +S 9400,4300,9400,14700,600,*,DOWN,PDIF +S 8800,4100,8800,14900,200,*,UP,PTRANS +S 5800,23900,5800,28300,600,*,UP,NDIF +S 4600,23900,4600,28300,600,*,UP,NDIF +S 5800,16100,5800,19500,600,*,DOWN,PDIF +S 4600,16100,4600,19500,600,*,DOWN,PDIF +S 5800,10300,5800,14700,600,*,DOWN,PDIF +S 4600,10300,4600,14700,600,*,DOWN,PDIF +S 5800,4500,5800,8900,600,*,DOWN,PDIF +S 4600,4500,4600,8900,600,*,UP,PDIF +S 6400,4000,7200,4000,200,*,RIGHT,POLY +S 2800,15400,5800,15400,200,*,RIGHT,POLY +S 2800,4000,4800,4000,200,*,RIGHT,POLY +S 8800,15400,9400,15400,600,*,RIGHT,POLY +S -400,1400,12700,1400,1400,*,LEFT,ALU2 +S 8800,29000,9300,29000,200,*,RIGHT,POLY +S 6400,29000,6900,29000,200,*,LEFT,POLY +S 2800,28700,2800,29000,200,*,UP,POLY +S 4000,28700,4000,29000,200,*,UP,POLY +S 6400,28700,6400,29000,200,*,UP,POLY +S 8800,28700,8800,29000,200,*,UP,POLY +S 7600,29500,7600,31100,600,*,UP,ALU1 +S 3400,10300,3400,14700,300,*,DOWN,PDIF +S 3400,4500,3400,8900,300,*,DOWN,PDIF +S 3400,16100,3400,19500,600,*,DOWN,PDIF +S 3400,23900,3400,28300,600,*,UP,NDIF +V 9400,29100,CONT_POLY,* +V 4600,29100,CONT_POLY,* +V 7000,29100,CONT_POLY,* +V 10600,16100,CONT_BODY_N,* +V 1000,19400,CONT_BODY_N,* +V 1000,16200,CONT_BODY_N,* +V 1000,17800,CONT_BODY_N,* +V 9400,6900,CONT_DIF_P,* +V 10600,6900,CONT_BODY_N,* +V 9400,15400,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 10600,24800,CONT_VIA,* +V 10600,30000,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 7000,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,27200,CONT_BODY_P,* +V 2200,24000,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,27200,CONT_DIF_N,* +V 2200,15400,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,9600,CONT_VIA,* +V 1000,14400,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,14400,CONT_BODY_N,* +V 9400,4800,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,9600,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,10400,CONT_DIF_P,* +V 2200,9600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,9600,CONT_VIA,* +V 7000,8800,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 5800,17800,CONT_DIF_P,* +V 10600,17000,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 10600,18600,CONT_VIA,* +V 10600,17800,CONT_BODY_N,* +V 10600,19400,CONT_BODY_N,* +V 5800,17000,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 9400,17800,CONT_DIF_P,* +V 9400,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 4600,17000,CONT_VIA,* +V 8200,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 5800,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 7000,20800,CONT_BODY_N,* +V 7000,17000,CONT_VIA,* +V 7000,18600,CONT_VIA,* +V 7000,16200,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 9400,14400,CONT_DIF_P,* +V 9400,22800,CONT_VIA,* +V 7000,3800,CONT_POLY,* +V 10600,22800,CONT_BODY_P,* +V 7000,15400,CONT_POLY,* +V 8200,19400,CONT_DIF_P,* +V 9400,19400,CONT_DIF_P,* +V 10600,2800,CONT_BODY_N,* +V 1000,9600,CONT_VIA,* +V 9400,30000,CONT_BODY_P,* +V 5800,30000,CONT_BODY_P,* +V 1000,30000,CONT_BODY_P,* +V 2200,30000,CONT_BODY_P,* +V 3400,30000,CONT_BODY_P,* +V 5800,15400,CONT_POLY,* +V 4600,3800,CONT_POLY,* +V 9400,15400,CONT_POLY,* +V 3400,1000,CONT_VIA,* +V 3400,1800,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib80/cells/frame_temp_x1.ap b/pdks/symbolic/phlib80/cells/frame_temp_x1.ap new file mode 100644 index 000000000..1f6cad3c1 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/frame_temp_x1.ap @@ -0,0 +1,12 @@ +V ALLIANCE : 6 +H frame_temp_x1,P,16/11/2016,100 +A 0,0,12400,31200 +C 6200,31200,6000,pad,0,NORTH,ALU1 +C 6200,31200,6000,pad,1,NORTH,ALU2 +C 12400,8600,9000,vdd,1,EAST,ALU1 +C 12400,19400,4800,vss,1,EAST,ALU1 +C 0,19400,4800,vss,0,WEST,ALU1 +C 0,8600,9000,vdd,0,WEST,ALU1 +C 0,1400,900,ck,0,WEST,ALU1 +C 12400,1400,900,ck,1,EAST,ALU1 +EOF diff --git a/pdks/symbolic/phlib80/cells/frame_temp_x2.ap b/pdks/symbolic/phlib80/cells/frame_temp_x2.ap new file mode 100644 index 000000000..222bc25f9 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/frame_temp_x2.ap @@ -0,0 +1,12 @@ +V ALLIANCE : 6 +H frame_temp_x2,P,16/11/2016,100 +A 0,0,24800,31200 +C 18600,31200,6000,pad,2,NORTH,ALU1 +C 18600,31200,6000,pad,3,NORTH,ALU2 +C 24800,1400,900,ck,2,EAST,ALU1 +C 24800,19400,4800,vss,2,EAST,ALU1 +C 24800,8600,9000,vdd,2,EAST,ALU1 +C 0,19400,4800,vss,0,WEST,ALU1 +C 0,8600,9000,vdd,0,WEST,ALU1 +C 0,1400,900,ck,0,WEST,ALU1 +EOF diff --git a/pdks/symbolic/phlib80/cells/i_buf.ap b/pdks/symbolic/phlib80/cells/i_buf.ap new file mode 100644 index 000000000..2bb231fd0 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/i_buf.ap @@ -0,0 +1,442 @@ +V ALLIANCE : 6 +H i_buf,P,15/ 8/2019,100 +A 0,0,12300,31200 +C 0,1400,900,ck,1,WEST,ALU2 +C 0,11800,18400,vdd,1,WEST,ALU2 +C 0,26400,7600,vss,1,WEST,ALU2 +C 12300,26400,7600,vss,2,EAST,ALU2 +C 12300,11800,18400,vdd,2,EAST,ALU2 +C 12300,1400,900,ck,2,EAST,ALU2 +C 3400,0,300,t,1,SOUTH,ALU1 +C 7600,31200,1000,pad,0,NORTH,ALU1 +S 0,1400,12300,1400,1300,ck,RIGHT,CALU2 +S 0,2800,12300,2800,500,vdd,LEFT,CALU2 +S 0,5600,12300,5600,500,vdd,RIGHT,CALU2 +S 0,8000,12300,8000,500,vdd,LEFT,CALU2 +S 0,9600,12300,9600,500,vdd,RIGHT,CALU2 +S 0,11200,12300,11200,500,vdd,LEFT,CALU2 +S 0,13600,12300,13600,500,vdd,RIGHT,CALU2 +S 0,15400,12300,15400,500,vdd,LEFT,CALU2 +S 0,17000,12300,17000,500,vdd,RIGHT,CALU2 +S 0,18600,12300,18600,500,vdd,LEFT,CALU2 +S 0,20800,12300,20800,500,vdd,RIGHT,CALU2 +S 0,22800,12300,22800,500,vss,LEFT,CALU2 +S 0,24800,12300,24800,500,vss,RIGHT,CALU2 +S 0,26400,12300,26400,500,vss,LEFT,CALU2 +S 0,28000,12300,28000,500,vss,RIGHT,CALU2 +S 0,30000,12300,30000,500,vss,RIGHT,CALU2 +S 9400,4800,10600,4800,300,*,RIGHT,ALU1 +S 9400,5600,10600,5600,300,*,LEFT,ALU1 +S 9400,6400,10600,6400,300,*,RIGHT,ALU1 +S 9400,7200,10600,7200,300,*,LEFT,ALU1 +S 9400,8000,10600,8000,300,*,RIGHT,ALU1 +S 9400,8800,10600,8800,300,*,LEFT,ALU1 +S 9400,9600,10600,9600,300,*,RIGHT,ALU1 +S 9400,10400,10600,10400,300,*,LEFT,ALU1 +S 9400,11200,10600,11200,300,*,RIGHT,ALU1 +S 9400,12000,10600,12000,300,*,LEFT,ALU1 +S 9400,12800,10600,12800,300,*,RIGHT,ALU1 +S 9400,13600,10600,13600,300,*,LEFT,ALU1 +S 9400,14400,10600,14400,300,*,RIGHT,ALU1 +S 9400,17000,10600,17000,300,*,LEFT,ALU1 +S 9400,17800,10600,17800,300,*,RIGHT,ALU1 +S 9400,18600,10600,18600,300,*,LEFT,ALU1 +S 9400,19400,10600,19400,300,*,RIGHT,ALU1 +S 9400,24000,10600,24000,300,*,LEFT,ALU1 +S 9400,24800,10600,24800,300,*,RIGHT,ALU1 +S 9400,25600,10600,25600,300,*,LEFT,ALU1 +S 9400,26400,10600,26400,300,*,RIGHT,ALU1 +S 9400,27200,10600,27200,300,*,LEFT,ALU1 +S 9400,28000,10600,28000,300,*,RIGHT,ALU1 +S 1000,4800,2200,4800,300,*,LEFT,ALU1 +S 1000,5600,2200,5600,300,*,RIGHT,ALU1 +S 1000,6400,2200,6400,300,*,LEFT,ALU1 +S 1000,7200,2200,7200,300,*,RIGHT,ALU1 +S 1000,8000,2200,8000,300,*,LEFT,ALU1 +S 1000,8800,2200,8800,300,*,RIGHT,ALU1 +S 1000,9600,2200,9600,300,*,LEFT,ALU1 +S 1000,10400,2200,10400,300,*,RIGHT,ALU1 +S 1000,11200,2200,11200,300,*,LEFT,ALU1 +S 1000,12000,2200,12000,300,*,RIGHT,ALU1 +S 1000,12800,2200,12800,300,*,LEFT,ALU1 +S 1000,13600,2200,13600,300,*,RIGHT,ALU1 +S 1000,14400,2200,14400,300,*,LEFT,ALU1 +S 1000,15400,2200,15400,300,*,RIGHT,ALU1 +S 1000,16200,2200,16200,300,*,LEFT,ALU1 +S 1000,17000,2200,17000,300,*,RIGHT,ALU1 +S 1000,17800,2300,17800,300,*,LEFT,ALU1 +S 1000,18600,2200,18600,300,*,RIGHT,ALU1 +S 1000,19400,2200,19400,300,*,LEFT,ALU1 +S 1000,22800,2200,22800,300,*,LEFT,ALU1 +S 1000,24000,2200,24000,300,*,RIGHT,ALU1 +S 1000,24800,2200,24800,300,*,RIGHT,ALU1 +S 1000,25600,2200,25600,300,*,LEFT,ALU1 +S 1000,26400,2200,26400,300,*,RIGHT,ALU1 +S 1000,27200,2200,27200,300,*,LEFT,ALU1 +S 1000,28000,2200,28000,300,*,RIGHT,ALU1 +S -300,2800,12700,2800,500,*,RIGHT,ALU2 +S -300,5600,12700,5600,500,*,LEFT,ALU2 +S -300,8000,12700,8000,500,*,RIGHT,ALU2 +S -300,9600,12700,9600,500,*,LEFT,ALU2 +S -300,11200,12700,11200,500,*,RIGHT,ALU2 +S -300,13600,12700,13600,500,*,LEFT,ALU2 +S -300,15400,12700,15400,500,*,RIGHT,ALU2 +S -300,17000,12700,17000,500,*,LEFT,ALU2 +S -300,18600,12700,18600,500,*,RIGHT,ALU2 +S -300,20800,12700,20800,500,*,LEFT,ALU2 +S -300,22800,12700,22800,500,*,RIGHT,ALU2 +S -300,24800,12700,24800,500,*,LEFT,ALU2 +S -300,26400,12700,26400,500,*,RIGHT,ALU2 +S -300,28000,12700,28000,500,*,LEFT,ALU2 +S -300,30000,12700,30000,500,*,RIGHT,ALU2 +S 8800,15400,9400,15400,600,*,RIGHT,POLY +S 4700,2800,10500,2800,400,*,LEFT,ALU1 +S 4700,3800,5700,3800,400,*,LEFT,ALU1 +S 5800,3900,5800,28900,400,*,UP,ALU1 +S 2800,4000,4800,4000,200,*,RIGHT,POLY +S 4600,4900,4600,20700,400,*,UP,ALU1 +S 2800,15400,5800,15400,200,*,RIGHT,POLY +S 4700,29000,5700,29000,400,*,LEFT,ALU1 +S 2800,28800,4800,28800,200,*,RIGHT,POLY +S 4600,22900,4600,27900,400,*,UP,ALU1 +S 6400,4000,7200,4000,200,*,RIGHT,POLY +S 4600,4500,4600,8900,600,*,UP,PDIF +S 5800,4500,5800,8900,600,*,DOWN,PDIF +S 4600,10300,4600,14700,600,*,DOWN,PDIF +S 5800,10300,5800,14700,600,*,DOWN,PDIF +S 4600,16100,4600,19500,600,*,DOWN,PDIF +S 5800,16100,5800,19500,600,*,DOWN,PDIF +S 4600,23900,4600,28300,600,*,UP,NDIF +S 5800,23900,5800,28300,600,*,UP,NDIF +S 6400,28800,7000,28800,200,*,LEFT,POLY +S 1100,30000,5700,30000,400,*,RIGHT,ALU1 +S 1000,22900,1000,29900,400,*,UP,ALU1 +S 9500,30000,10500,30000,400,*,LEFT,ALU1 +S 10600,22900,10600,29900,400,*,UP,ALU1 +S 9400,22900,9400,28900,400,*,UP,ALU1 +S 8800,29000,9400,29000,600,*,RIGHT,POLY +S 2200,22900,2200,28700,400,*,UP,ALU1 +S 7000,4900,7000,14300,400,*,DOWN,ALU1 +S 7000,16300,7000,20700,400,*,UP,ALU1 +S 8800,4100,8800,14900,200,*,UP,PTRANS +S 9400,4300,9400,14700,600,*,DOWN,PDIF +S 8200,4300,8200,14700,600,*,UP,PDIF +S 1000,2500,1000,20900,600,*,UP,NTIE +S 2200,16100,2200,19500,600,*,UP,PDIF +S 700,2800,10900,2800,600,*,LEFT,NTIE +S 2800,15900,2800,19700,200,*,UP,PTRANS +S 4000,15900,4000,19700,200,*,UP,PTRANS +S 7000,16100,7000,19500,600,*,UP,PDIF +S 6400,15900,6400,19700,200,*,UP,PTRANS +S 9400,16100,9400,19500,600,*,UP,PDIF +S 8200,16100,8200,19500,600,*,UP,PDIF +S 8800,15900,8800,19700,200,*,UP,PTRANS +S 10600,2500,10600,20900,600,*,UP,NTIE +S 10600,2900,10600,14300,400,*,DOWN,ALU1 +S 8800,15200,8800,15600,200,*,UP,POLY +S 6400,15000,6400,15800,200,*,UP,POLY +S 4000,15000,4000,15800,200,*,UP,POLY +S 2800,15000,2800,15800,200,*,UP,POLY +S 6400,10100,6400,14900,200,*,UP,PTRANS +S 7000,10300,7000,14700,600,*,UP,PDIF +S 4000,10100,4000,14900,200,*,UP,PTRANS +S 2800,10100,2800,14900,200,*,UP,PTRANS +S 2200,10300,2200,14700,600,*,UP,PDIF +S 7100,15400,8100,15400,400,*,LEFT,ALU1 +S 9400,2900,9400,14300,400,*,UP,ALU1 +S 700,30000,10900,30000,600,*,LEFT,PTIE +S 700,22800,10900,22800,600,*,LEFT,PTIE +S 1000,22500,1000,30300,600,*,DOWN,PTIE +S 10600,22500,10600,30300,600,*,DOWN,PTIE +S 6400,4300,6400,9100,200,*,UP,PTRANS +S 4000,4300,4000,9100,200,*,UP,PTRANS +S 2800,4300,2800,9100,200,*,UP,PTRANS +S 2200,4500,2200,8900,600,*,UP,PDIF +S 7000,4500,7000,8900,600,*,UP,PDIF +S 7100,3800,8100,3800,400,*,LEFT,ALU1 +S 8200,3900,8200,28900,400,*,DOWN,ALU1 +S 8800,23700,8800,28500,200,*,UP,NTRANS +S 8200,23900,8200,28300,600,*,UP,NDIF +S 9400,23900,9400,28300,600,*,UP,NDIF +S 6400,23700,6400,28500,200,*,UP,NTRANS +S 4000,23700,4000,28500,200,*,UP,NTRANS +S 2800,23700,2800,28500,200,*,UP,NTRANS +S 2200,23900,2200,28300,600,*,UP,NDIF +S 7000,23900,7000,28300,600,*,UP,NDIF +S 7100,29000,8100,29000,400,*,LEFT,ALU1 +S 7000,22900,7000,27900,400,*,UP,ALU1 +S 9500,22800,10500,22800,400,*,LEFT,ALU1 +S 8800,28800,8800,29200,200,*,DOWN,POLY +S 700,20800,10900,20800,600,*,LEFT,NTIE +S 2200,2900,2200,20700,400,*,UP,ALU1 +S 1100,20800,2100,20800,400,*,RIGHT,ALU1 +S 1000,2900,1000,20700,400,*,UP,ALU1 +S 9400,16500,9400,20700,400,*,UP,ALU1 +S 10600,16500,10600,20700,400,*,DOWN,ALU1 +S 9500,20800,10500,20800,400,*,LEFT,ALU1 +S 6200,21600,6200,31200,12800,*,DOWN,PWELL +S 6200,1600,6200,21600,12800,*,UP,NWELL +S 6400,15400,7000,15400,600,*,RIGHT,POLY +S 3400,100,3400,27900,400,*,UP,ALU1 +S -350,1400,12650,1400,1300,*,RIGHT,ALU2 +S 9400,22800,10600,22800,400,*,RIGHT,ALU1 +S 9400,20800,10600,20800,400,*,LEFT,ALU1 +S 9400,2800,10600,2800,400,*,LEFT,ALU1 +S 1000,2800,2200,2800,400,*,RIGHT,ALU1 +S 1000,20800,2200,20800,400,*,RIGHT,ALU1 +S 1000,30000,2200,30000,400,*,LEFT,ALU1 +S 7600,29100,7600,31100,600,*,UP,ALU1 +S 3400,23900,3400,28300,600,*,UP,NDIF +S 3500,16100,3500,19500,600,*,DOWN,PDIF +S 3400,10300,3400,14700,600,*,DOWN,PDIF +S 3400,4500,3400,8900,600,*,UP,PDIF +V 9400,15400,CONT_VIA,* +V 9400,15400,CONT_POLY,* +V 4600,3800,CONT_POLY,* +V 5800,15400,CONT_POLY,* +V 4600,29000,CONT_POLY,* +V 3400,30000,CONT_BODY_P,* +V 2200,30000,CONT_BODY_P,* +V 1000,30000,CONT_BODY_P,* +V 5800,30000,CONT_BODY_P,* +V 9400,30000,CONT_BODY_P,* +V 9400,29000,CONT_POLY,* +V 1000,9600,CONT_VIA,* +V 10600,2800,CONT_BODY_N,* +V 9400,19400,CONT_DIF_P,* +V 8200,19400,CONT_DIF_P,* +V 7000,15400,CONT_POLY,* +V 10600,22800,CONT_BODY_P,* +V 7000,3800,CONT_POLY,* +V 7000,29000,CONT_POLY,* +V 9400,22800,CONT_VIA,* +V 9400,14400,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 7000,16200,CONT_DIF_P,* +V 7000,18600,CONT_VIA,* +V 7000,17000,CONT_VIA,* +V 7000,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 5800,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 8200,2800,CONT_BODY_N,* +V 4600,17000,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 9400,17000,CONT_VIA,* +V 9400,17800,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 5800,17000,CONT_DIF_P,* +V 10600,19400,CONT_BODY_N,* +V 10600,17800,CONT_BODY_N,* +V 10600,18600,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 10600,17000,CONT_VIA,* +V 5800,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,8800,CONT_DIF_P,* +V 7000,9600,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,9600,CONT_VIA,* +V 7000,10400,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,9600,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,4800,CONT_DIF_P,* +V 10600,14400,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,14400,CONT_BODY_N,* +V 10600,9600,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 2200,15400,CONT_VIA,* +V 9400,27200,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,24000,CONT_DIF_N,* +V 10600,27200,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 7000,22800,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 10600,30000,CONT_BODY_P,* +V 10600,24800,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 3400,0,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib80/cells/i_buf2.ap b/pdks/symbolic/phlib80/cells/i_buf2.ap new file mode 100644 index 000000000..2cc63aa6d --- /dev/null +++ b/pdks/symbolic/phlib80/cells/i_buf2.ap @@ -0,0 +1,437 @@ +V ALLIANCE : 6 +H i_buf2,P,30/ 8/2019,100 +A 0,0,12300,31200 +C 7300,31200,1000,pad,0,NORTH,ALU1 +C 12300,1400,900,ck,1,EAST,ALU2 +C 12300,11800,18400,vdd,1,EAST,ALU2 +C 12300,26400,7600,vss,1,EAST,ALU2 +C 0,26400,7600,vss,0,WEST,ALU2 +C 0,11800,18400,vdd,0,WEST,ALU2 +C 0,1400,900,ck,0,WEST,ALU2 +S 0,1400,12300,1400,1300,ck,RIGHT,CALU2 +S 0,2800,12300,2800,500,vdd,LEFT,CALU2 +S 0,5600,12300,5600,500,vdd,RIGHT,CALU2 +S 0,8000,12300,8000,500,vdd,LEFT,CALU2 +S 0,9600,12300,9600,500,vdd,RIGHT,CALU2 +S 0,11200,12300,11200,500,vdd,LEFT,CALU2 +S 0,13600,12300,13600,500,vdd,RIGHT,CALU2 +S 0,15400,12300,15400,500,vdd,LEFT,CALU2 +S 0,17000,12300,17000,500,vdd,RIGHT,CALU2 +S 0,18600,12300,18600,500,vdd,LEFT,CALU2 +S 0,20800,12300,20800,500,vdd,RIGHT,CALU2 +S 0,22800,12300,22800,500,vss,LEFT,CALU2 +S 0,24800,12300,24800,500,vss,RIGHT,CALU2 +S 0,26400,12300,26400,500,vss,LEFT,CALU2 +S 0,28000,12300,28000,500,vss,RIGHT,CALU2 +S 0,30000,12300,30000,500,vss,RIGHT,CALU2 +S 3400,4500,3400,8900,600,*,UP,PDIF +S 3400,10300,3400,14700,600,*,DOWN,PDIF +S 3500,16100,3500,19500,600,*,DOWN,PDIF +S 3500,23900,3500,28300,600,*,UP,NDIF +S -300,2800,12700,2800,500,*,RIGHT,ALU2 +S -300,5600,12700,5600,500,*,LEFT,ALU2 +S -300,8000,12700,8000,500,*,RIGHT,ALU2 +S -300,9600,12700,9600,500,*,LEFT,ALU2 +S -300,11200,12700,11200,500,*,RIGHT,ALU2 +S -300,13600,12700,13600,500,*,LEFT,ALU2 +S -300,15400,12700,15400,500,*,RIGHT,ALU2 +S -300,17000,12700,17000,500,*,LEFT,ALU2 +S -300,18600,12700,18600,500,*,RIGHT,ALU2 +S -300,20800,12700,20800,500,*,LEFT,ALU2 +S -300,22800,12700,22800,500,*,RIGHT,ALU2 +S -300,24800,12700,24800,500,*,LEFT,ALU2 +S -300,26400,12700,26400,500,*,RIGHT,ALU2 +S -300,28000,12700,28000,500,*,LEFT,ALU2 +S -300,30000,12700,30000,500,*,RIGHT,ALU2 +S 3400,4600,3400,27900,400,*,UP,ALU1 +S 6400,15400,7000,15400,600,*,RIGHT,POLY +S 6200,1600,6200,21600,12800,*,UP,NWELL +S 6200,21600,6200,31200,12800,*,DOWN,PWELL +S 9500,20800,10500,20800,300,*,LEFT,ALU1 +S 10600,16500,10600,20700,400,*,DOWN,ALU1 +S 9400,16500,9400,20700,400,*,UP,ALU1 +S 1000,2900,1000,20700,400,*,UP,ALU1 +S 1100,20800,2100,20800,400,*,RIGHT,ALU1 +S 2200,2900,2200,20700,400,*,UP,ALU1 +S 700,20800,10900,20800,600,*,LEFT,NTIE +S 8800,28800,8800,29200,200,*,DOWN,POLY +S 9500,22800,10500,22800,300,*,LEFT,ALU1 +S 7000,22900,7000,27900,400,*,UP,ALU1 +S 7100,29000,8100,29000,300,*,LEFT,ALU1 +S 7000,23900,7000,28300,600,*,UP,NDIF +S 2200,23900,2200,28300,600,*,UP,NDIF +S 2800,23700,2800,28500,200,*,UP,NTRANS +S 4000,23700,4000,28500,200,*,UP,NTRANS +S 6400,23700,6400,28500,200,*,UP,NTRANS +S 9400,23900,9400,28300,600,*,UP,NDIF +S 8200,23900,8200,28300,600,*,UP,NDIF +S 8800,23700,8800,28500,200,*,UP,NTRANS +S 8200,3900,8200,28900,400,*,DOWN,ALU1 +S 7100,3800,8100,3800,300,*,LEFT,ALU1 +S 7000,4500,7000,8900,600,*,UP,PDIF +S 2200,4500,2200,8900,600,*,UP,PDIF +S 2800,4300,2800,9100,200,*,UP,PTRANS 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9400,17000,10600,17000,300,*,LEFT,ALU1 +S 9400,14400,10600,14400,400,*,RIGHT,ALU1 +S 9400,13600,10600,13600,300,*,LEFT,ALU1 +S 9400,12800,10600,12800,300,*,LEFT,ALU1 +S 9400,12000,10600,12000,400,*,RIGHT,ALU1 +S 9400,11200,10600,11200,300,*,LEFT,ALU1 +S 9400,10400,10600,10400,400,*,RIGHT,ALU1 +S 9400,9600,10600,9600,300,*,LEFT,ALU1 +S 9400,8800,10600,8800,400,*,RIGHT,ALU1 +S 9400,8000,10600,8000,300,*,LEFT,ALU1 +S 9400,7200,10600,7200,400,*,RIGHT,ALU1 +S 9400,6400,10600,6400,300,*,LEFT,ALU1 +S 9400,5600,10600,5600,400,*,RIGHT,ALU1 +S 9400,4800,10600,4800,300,*,LEFT,ALU1 +S 9400,2800,10600,2800,300,*,LEFT,ALU1 +S 1000,2800,2200,2800,400,*,RIGHT,ALU1 +S 1000,4800,2200,4800,300,*,LEFT,ALU1 +S 1000,5600,2200,5600,400,*,RIGHT,ALU1 +S 1000,6400,2200,6400,300,*,LEFT,ALU1 +S 1000,7200,2200,7200,300,*,LEFT,ALU1 +S 1000,8000,2200,8000,400,*,RIGHT,ALU1 +S 1000,8800,2200,8800,300,*,LEFT,ALU1 +S 1000,9600,2200,9600,400,*,RIGHT,ALU1 +S 1000,10400,2200,10400,300,*,LEFT,ALU1 +S 1000,11200,2200,11200,400,*,RIGHT,ALU1 +S 1000,12000,2200,12000,300,*,LEFT,ALU1 +S 1000,12800,2200,12800,400,*,RIGHT,ALU1 +S 1000,13600,2200,13600,300,*,LEFT,ALU1 +S 1000,14400,2200,14400,400,*,RIGHT,ALU1 +S 1000,15400,2200,15400,300,*,LEFT,ALU1 +S 1000,16200,2200,16200,300,*,LEFT,ALU1 +S 1000,17000,2200,17000,400,*,RIGHT,ALU1 +S 1000,17800,2200,17800,300,*,LEFT,ALU1 +S 1000,18600,2200,18600,400,*,RIGHT,ALU1 +S 1000,19400,2200,19400,300,*,LEFT,ALU1 +S 1000,20800,2200,20800,400,*,RIGHT,ALU1 +S 7600,29100,7600,31100,600,*,UP,ALU1 +S 2200,22900,2200,29900,400,*,DOWN,ALU1 +S 1000,27200,2200,27200,300,*,LEFT,ALU1 +S 1000,28800,2200,28800,300,*,LEFT,ALU1 +S 1000,25600,2200,25600,300,*,LEFT,ALU1 +S 1000,24000,2200,24000,300,*,LEFT,ALU1 +V 9400,15400,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 10600,24800,CONT_VIA,* +V 10600,30000,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 7000,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,27200,CONT_BODY_P,* +V 2200,24000,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,27200,CONT_DIF_N,* +V 2200,15400,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,9600,CONT_VIA,* +V 1000,14400,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,14400,CONT_BODY_N,* +V 9400,4800,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,9600,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,10400,CONT_DIF_P,* +V 2200,9600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,9600,CONT_VIA,* +V 7000,8800,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 5800,17800,CONT_DIF_P,* +V 10600,17000,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 10600,18600,CONT_VIA,* +V 10600,17800,CONT_BODY_N,* +V 10600,19400,CONT_BODY_N,* +V 5800,17000,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 9400,17800,CONT_DIF_P,* +V 9400,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 4600,17000,CONT_VIA,* +V 8200,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 5800,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 7000,20800,CONT_BODY_N,* +V 7000,17000,CONT_VIA,* +V 7000,18600,CONT_VIA,* +V 7000,16200,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 9400,14400,CONT_DIF_P,* +V 9400,22800,CONT_VIA,* +V 7000,29000,CONT_POLY,* +V 7000,3800,CONT_POLY,* +V 10600,22800,CONT_BODY_P,* +V 7000,15400,CONT_POLY,* +V 8200,19400,CONT_DIF_P,* +V 9400,19400,CONT_DIF_P,* +V 10600,2800,CONT_BODY_N,* +V 1000,9600,CONT_VIA,* +V 9400,29000,CONT_POLY,* +V 9400,30000,CONT_BODY_P,* +V 5800,30000,CONT_BODY_P,* +V 1000,30000,CONT_BODY_P,* +V 2200,30000,CONT_BODY_P,* +V 3400,30000,CONT_BODY_P,* +V 4600,29000,CONT_POLY,* +V 5800,15400,CONT_POLY,* +V 4600,3800,CONT_POLY,* +V 9400,15400,CONT_POLY,* +EOF diff --git a/pdks/symbolic/phlib80/cells/padall.ap b/pdks/symbolic/phlib80/cells/padall.ap new file mode 100644 index 000000000..a206a351c --- /dev/null +++ b/pdks/symbolic/phlib80/cells/padall.ap @@ -0,0 +1,8 @@ +V ALLIANCE : 6 +H padall,P,25/ 9/2019,100 +A 0,0,600000,600000 +I 56300,18700,padline,south,SYM_Y +I 56300,561300,padline,north,NOSYM +I 18700,56300,padline,west,ROT_P +I 561300,56300,padline,east,ROT_M +EOF diff --git a/pdks/symbolic/phlib80/cells/padline.ap b/pdks/symbolic/phlib80/cells/padline.ap new file mode 100644 index 000000000..77b0b6415 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/padline.ap @@ -0,0 +1,24 @@ +V ALLIANCE : 6 +H padline,P,25/11/2016,100 +A 0,0,487400,20000 +I 0,0,padreal,pad0,NOSYM +I 24600,0,padreal,pad1,NOSYM +I 49200,0,padreal,pad2,NOSYM +I 73800,0,padreal,pad3,NOSYM +I 98400,0,padreal,pad4,NOSYM +I 123000,0,padreal,pad5,NOSYM +I 147600,0,padreal,pad6,NOSYM +I 172200,0,padreal,pad7,NOSYM +I 196800,0,padreal,pad8,NOSYM +I 221400,0,padreal,pad9,NOSYM +I 246000,0,padreal,pad10,NOSYM +I 270600,0,padreal,pad11,NOSYM +I 295200,0,padreal,pad12,NOSYM +I 319800,0,padreal,pad13,NOSYM +I 344400,0,padreal,pad14,NOSYM +I 369000,0,padreal,pad15,NOSYM +I 393600,0,padreal,pad16,NOSYM +I 418200,0,padreal,pad17,NOSYM +I 442800,0,padreal,pad18,NOSYM +I 467400,0,padreal,pad19,NOSYM +EOF diff --git a/pdks/symbolic/phlib80/cells/padreal.ap b/pdks/symbolic/phlib80/cells/padreal.ap new file mode 100644 index 000000000..1effe41a1 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/padreal.ap @@ -0,0 +1,6 @@ +V ALLIANCE : 6 +H padreal,P,25/ 9/2019,100 +A 0,0,20000,20000 +S 10000,-2400,10000,0,18000,*,DOWN,ALU1 +S 0,10000,20000,10000,20000,pad,RIGHT,ALU1 +EOF diff --git a/pdks/symbolic/phlib80/cells/pbuf_c.ap b/pdks/symbolic/phlib80/cells/pbuf_c.ap new file mode 100644 index 000000000..5d179476b --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pbuf_c.ap @@ -0,0 +1,448 @@ +V ALLIANCE : 6 +H pbuf_c,P,16/ 8/2019,100 +A 0,0,12300,31200 +C 5800,31200,1000,pad,1,NORTH,ALU1 +C 3400,31200,1000,pad,0,NORTH,ALU1 +C 0,26400,7600,vss,0,WEST,ALU2 +C 0,11800,18400,vdd,0,WEST,ALU1 +C 12000,0,300,i,0,SOUTH,ALU1 +C 12000,0,300,i,1,SOUTH,ALU2 +C 0,1400,900,ck,0,WEST,ALU1 +C 12300,11800,18400,vdd,1,EAST,ALU2 +C 12300,26400,7600,vss,1,EAST,ALU2 +C 12300,1400,900,ck,1,EAST,ALU2 +S 0,1400,12300,1400,1300,ck,RIGHT,CALU2 +S 0,2800,12300,2800,500,vdd,LEFT,CALU2 +S 0,5600,12300,5600,500,vdd,RIGHT,CALU2 +S 0,8000,12300,8000,500,vdd,LEFT,CALU2 +S 0,9600,12300,9600,500,vdd,RIGHT,CALU2 +S 0,11200,12300,11200,500,vdd,LEFT,CALU2 +S 0,13600,12300,13600,500,vdd,RIGHT,CALU2 +S 0,15400,12300,15400,500,vdd,LEFT,CALU2 +S 0,17000,12300,17000,500,vdd,RIGHT,CALU2 +S 0,18600,12300,18600,500,vdd,LEFT,CALU2 +S 0,20800,12300,20800,500,vdd,RIGHT,CALU2 +S 0,22800,12300,22800,500,vss,LEFT,CALU2 +S 0,24800,12300,24800,500,vss,RIGHT,CALU2 +S 0,26400,12300,26400,500,vss,LEFT,CALU2 +S 0,28000,12300,28000,500,vss,RIGHT,CALU2 +S 0,30000,12300,30000,500,vss,RIGHT,CALU2 +S 9300,29000,12000,29000,300,*,LEFT,ALU1 +S 9300,15400,12000,15400,400,*,RIGHT,ALU1 +S 5800,4500,5800,8900,600,*,UP,PDIF +S 4600,4500,4600,8900,600,*,UP,PDIF +S 3400,4500,3400,8900,600,*,UP,PDIF +S 5900,10300,5900,14700,600,*,UP,PDIF +S 4600,10300,4600,14700,600,*,UP,PDIF +S 3300,10300,3300,14700,600,*,UP,PDIF +S 5800,16100,5800,19500,600,*,UP,PDIF +S 4500,16100,4500,19500,600,*,UP,PDIF +S 3300,16100,3300,19500,600,*,UP,PDIF +S 5800,23900,5800,28300,600,*,UP,NDIF +S 4600,23900,4600,28300,600,*,UP,NDIF +S 3200,23900,3200,28300,600,*,UP,NDIF +S 1000,20800,2200,20800,400,*,RIGHT,ALU1 +S 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1000,27200,2200,27200,300,*,LEFT,ALU1 +S 1000,25600,2200,25600,300,*,LEFT,ALU1 +S 1000,24000,2200,24000,300,*,LEFT,ALU1 +S 1000,22800,2200,22800,300,*,LEFT,ALU1 +S 2200,22900,2200,29800,400,*,UP,ALU1 +S 900,30000,2200,30000,400,*,RIGHT,ALU1 +V 1000,16200,CONT_BODY_N,* +V 1000,17800,CONT_BODY_N,* +V 1000,19400,CONT_BODY_N,* +V 12000,0,CONT_VIA,* +V 1000,9600,CONT_VIA,* +V 8200,21800,CONT_VIA,* +V 10600,2800,CONT_BODY_N,* +V 9400,19400,CONT_DIF_P,* +V 8200,19400,CONT_DIF_P,* +V 9200,15400,CONT_POLY,* +V 7000,15400,CONT_POLY,* +V 10600,22800,CONT_BODY_P,* +V 7000,3800,CONT_POLY,* +V 7000,29000,CONT_POLY,* +V 9400,22800,CONT_VIA,* +V 9200,29000,CONT_POLY,* +V 9400,14400,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 7000,16200,CONT_DIF_P,* +V 7000,18600,CONT_VIA,* +V 7000,17000,CONT_VIA,* +V 7000,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 3400,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 5800,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 8200,2800,CONT_BODY_N,* +V 4600,17000,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 9400,17000,CONT_VIA,* +V 9400,17800,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 5800,17000,CONT_DIF_P,* +V 10600,19400,CONT_BODY_N,* +V 10600,17800,CONT_BODY_N,* +V 10600,18600,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 10600,17000,CONT_VIA,* +V 5800,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,8800,CONT_DIF_P,* +V 7000,9600,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,9600,CONT_VIA,* +V 7000,10400,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,9600,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,4800,CONT_DIF_P,* +V 10600,14400,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,14400,CONT_BODY_N,* +V 10600,9600,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 2200,15400,CONT_VIA,* +V 9400,27200,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,24000,CONT_DIF_N,* +V 10600,27200,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 7000,22800,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 10600,30000,CONT_BODY_P,* +V 7000,30000,CONT_BODY_P,* +V 9400,30000,CONT_VIA,* +V 8200,30000,CONT_VIA,* +V 10600,24800,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 2200,30000,CONT_BODY_P,* +V 1000,30000,CONT_BODY_P,* +V 2200,30000,CONT_VIA,* +V 1000,30000,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib80/cells/pbuf_e.ap b/pdks/symbolic/phlib80/cells/pbuf_e.ap new file mode 100644 index 000000000..3c4838c49 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pbuf_e.ap @@ -0,0 +1,448 @@ +V ALLIANCE : 6 +H pbuf_e,P,16/ 8/2019,100 +A 0,0,12300,31200 +C 0,26400,7600,vss,0,WEST,ALU2 +C 0,11800,18400,vdd,0,WEST,ALU2 +C 0,1400,900,ck,0,WEST,ALU2 +C 12300,26400,7600,vss,1,EAST,ALU2 +C 12300,11800,18400,vdd,1,EAST,ALU2 +C 12300,1400,900,ck,1,EAST,ALU2 +S 0,1400,12300,1400,1300,ck,RIGHT,CALU2 +S 0,2800,12300,2800,500,vdd,LEFT,CALU2 +S 0,5600,12300,5600,500,vdd,RIGHT,CALU2 +S 0,8000,12300,8000,500,vdd,LEFT,CALU2 +S 0,9600,12300,9600,500,vdd,RIGHT,CALU2 +S 0,11200,12300,11200,500,vdd,LEFT,CALU2 +S 0,13600,12300,13600,500,vdd,RIGHT,CALU2 +S 0,15400,12300,15400,500,vdd,LEFT,CALU2 +S 0,17000,12300,17000,500,vdd,RIGHT,CALU2 +S 0,18600,12300,18600,500,vdd,LEFT,CALU2 +S 0,20800,12300,20800,500,vdd,RIGHT,CALU2 +S 0,22800,12300,22800,500,vss,LEFT,CALU2 +S 0,24800,12300,24800,500,vss,RIGHT,CALU2 +S 0,26400,12300,26400,500,vss,LEFT,CALU2 +S 0,28000,12300,28000,500,vss,RIGHT,CALU2 +S 0,30000,12300,30000,500,vss,RIGHT,CALU2 +S 11400,21800,12100,21800,600,*,LEFT,ALU2 +S 8200,4900,8200,31300,400,*,DOWN,ALU1 +S 8200,4500,8200,8900,600,*,UP,PDIF +S 7000,4500,7000,8900,600,*,UP,PDIF +S 5800,4500,5800,8900,600,*,UP,PDIF +S 4600,4500,4600,8900,600,*,UP,PDIF +S 3400,4500,3400,8900,600,*,UP,PDIF +S 3400,10300,3400,14700,600,*,DOWN,PDIF +S 4600,10300,4600,14700,600,*,DOWN,PDIF +S 5800,10300,5800,14700,600,*,DOWN,PDIF +S 7000,10300,7000,14700,600,*,DOWN,PDIF +S 8200,10300,8200,14700,600,*,DOWN,PDIF +S 7000,16100,7000,19500,600,*,UP,PDIF +S 5800,16100,5800,19500,600,*,UP,PDIF +S 4500,16100,4500,19500,600,*,UP,PDIF +S 3400,16100,3400,19500,600,*,UP,PDIF +S 6900,23900,6900,28300,600,*,UP,NDIF +S 5700,23900,5700,28300,600,*,UP,NDIF +S 4500,23900,4500,28300,600,*,UP,NDIF +S 3400,23900,3400,28300,600,*,UP,NDIF +S 1000,20800,2200,20800,400,*,RIGHT,ALU1 +S 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3400,4900,3400,28900,400,*,UP,ALU1 +S 5800,4900,5800,28900,400,*,UP,ALU1 +S 3500,29000,8100,29000,300,*,LEFT,ALU1 +S 4600,22900,4600,27900,400,*,UP,ALU1 +S 7000,22900,7000,27900,400,*,UP,ALU1 +S 2800,28800,8800,28800,200,*,LEFT,POLY +S 7600,15000,7600,15800,200,*,UP,POLY +S 2800,15400,8800,15400,200,*,RIGHT,POLY +S 5800,3600,5800,4000,600,*,DOWN,POLY +S 1100,2800,4500,2800,400,*,RIGHT,ALU1 +S 7100,2800,10500,2800,300,*,LEFT,ALU1 +S 9400,4500,9400,8900,600,*,UP,PDIF +S 9400,10300,9400,14700,600,*,DOWN,PDIF +S 2800,4000,8800,4000,200,*,RIGHT,POLY +S 7600,23700,7600,28500,200,*,DOWN,NTRANS +S 8800,4300,8800,9100,200,*,DOWN,PTRANS +S 8800,10100,8800,14900,200,*,UP,PTRANS +S 7600,4300,7600,9100,200,*,DOWN,PTRANS +S 7600,10100,7600,14900,200,*,DOWN,PTRANS +S 7600,15900,7600,19700,200,*,DOWN,PTRANS +S 7000,4900,7000,14300,400,*,DOWN,ALU1 +S 7000,16300,7000,20700,400,*,UP,ALU1 +S 1000,2500,1000,20900,600,*,UP,NTIE +S 2200,16100,2200,19500,600,*,UP,PDIF +S 700,2800,10900,2800,600,*,LEFT,NTIE +S 2800,15900,2800,19700,200,*,UP,PTRANS +S 4000,15900,4000,19700,200,*,UP,PTRANS +S 5200,15900,5200,19700,200,*,UP,PTRANS +S 6400,15900,6400,19700,200,*,UP,PTRANS +S 9400,16100,9400,19500,600,*,UP,PDIF +S 8200,16100,8200,19500,600,*,UP,PDIF +S 8800,15900,8800,19700,200,*,UP,PTRANS +S 10600,2500,10600,20900,600,*,UP,NTIE +S 10600,2900,10600,14300,400,*,DOWN,ALU1 +S 8800,15200,8800,15600,200,*,UP,POLY +S 9300,15400,11500,15400,400,*,RIGHT,ALU1 +S 8800,15400,9200,15400,600,*,RIGHT,POLY +S 6400,15000,6400,15800,200,*,UP,POLY +S 5200,15000,5200,15800,200,*,UP,POLY +S 4000,15000,4000,15800,200,*,UP,POLY +S 2800,15000,2800,15800,200,*,UP,POLY +S 6400,10100,6400,14900,200,*,UP,PTRANS +S 5200,10100,5200,14900,200,*,DOWN,PTRANS +S 4000,10100,4000,14900,200,*,UP,PTRANS +S 2800,10100,2800,14900,200,*,UP,PTRANS +S 2200,10300,2200,14700,600,*,UP,PDIF +S 9400,2900,9400,14300,400,*,UP,ALU1 +S 700,30000,10900,30000,600,*,LEFT,PTIE +S 700,22800,10900,22800,600,*,LEFT,PTIE +S 1000,22500,1000,30300,600,*,DOWN,PTIE +S 10600,22500,10600,30300,600,*,DOWN,PTIE +S 1000,22900,1000,29900,400,*,UP,ALU1 +S 6400,4300,6400,9100,200,*,UP,PTRANS +S 5200,4300,5200,9100,200,*,UP,PTRANS +S 4000,4300,4000,9100,200,*,UP,PTRANS +S 2800,4300,2800,9100,200,*,UP,PTRANS +S 2200,4500,2200,8900,600,*,UP,PDIF +S 8800,23700,8800,28500,200,*,UP,NTRANS +S 8200,23900,8200,28300,600,*,UP,NDIF +S 9400,23900,9400,28300,600,*,UP,NDIF +S 6400,23700,6400,28500,200,*,UP,NTRANS +S 5200,23700,5200,28500,200,*,UP,NTRANS +S 4000,23700,4000,28500,200,*,UP,NTRANS +S 2800,23700,2800,28500,200,*,UP,NTRANS +S 2200,23900,2200,28300,600,*,UP,NDIF +S 10600,22900,10600,27900,400,*,UP,ALU1 +S 9400,22900,9400,27900,400,*,UP,ALU1 +S 2200,22900,2200,29900,400,*,UP,ALU1 +S 9500,22800,10500,22800,300,*,LEFT,ALU1 +S 9300,29000,11500,29000,300,*,LEFT,ALU1 +S 8800,29000,9200,29000,600,*,RIGHT,POLY +S 8800,28800,8800,29200,200,*,DOWN,POLY +S 700,20800,10900,20800,600,*,LEFT,NTIE +S 2200,2900,2200,20700,400,*,UP,ALU1 +S 1100,20800,2100,20800,400,*,RIGHT,ALU1 +S 1000,2900,1000,20700,400,*,UP,ALU1 +S 4600,2900,4600,20700,400,*,UP,ALU1 +S 9400,16500,9400,20700,400,*,UP,ALU1 +S 10600,16500,10600,20700,400,*,DOWN,ALU1 +S 9500,20800,10500,20800,300,*,LEFT,ALU1 +S 6200,21600,6200,31200,12800,*,DOWN,PWELL +S 6200,1600,6200,21600,12800,*,UP,NWELL +S 11600,1600,11600,29000,500,*,UP,ALU1 +S 5800,1700,5800,3500,400,*,UP,ALU1 +S 5800,1600,11700,1600,500,*,LEFT,ALU1 +S 6200,1600,6200,21600,12800,*,UP,NWELL +S 1000,28800,2200,28800,300,*,LEFT,ALU1 +S 1000,27200,2200,27200,300,*,LEFT,ALU1 +S 1000,25600,2200,25600,300,*,LEFT,ALU1 +S 1000,24000,2200,24000,300,*,LEFT,ALU1 +S 1000,22800,2200,22800,300,*,LEFT,ALU1 +S -300,30000,12100,30000,500,*,RIGHT,ALU2 +S -300,28000,12100,28000,500,*,LEFT,ALU2 +S -300,26400,12100,26400,500,*,RIGHT,ALU2 +S -300,24800,12100,24800,500,*,LEFT,ALU2 +S -300,22800,12100,22800,500,*,RIGHT,ALU2 +S -300,20800,12100,20800,500,*,LEFT,ALU2 +S -300,18600,12100,18600,500,*,RIGHT,ALU2 +S -300,17000,12100,17000,500,*,RIGHT,ALU2 +S -300,13600,12100,13600,500,*,RIGHT,ALU2 +S -300,11200,12100,11200,500,*,RIGHT,ALU2 +S -300,9600,12100,9600,500,*,RIGHT,ALU2 +S -300,8000,12100,8000,500,*,RIGHT,ALU2 +S -300,5600,12100,5600,500,*,RIGHT,ALU2 +S -300,2800,12100,2800,500,*,RIGHT,ALU2 +S -500,1400,12100,1400,1300,*,RIGHT,ALU2 +V 1000,16200,CONT_BODY_N,* +V 1000,17800,CONT_BODY_N,* +V 1000,19400,CONT_BODY_N,* +V 1000,9600,CONT_VIA,* +V 3400,30000,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 5800,30000,CONT_BODY_P,* +V 7000,30000,CONT_BODY_P,* +V 5800,3600,CONT_POLY,* +V 10600,2800,CONT_BODY_N,* +V 9400,19400,CONT_DIF_P,* +V 8200,19400,CONT_DIF_P,* +V 9200,15400,CONT_POLY,* +V 10600,22800,CONT_BODY_P,* +V 9400,22800,CONT_VIA,* +V 9200,29000,CONT_POLY,* +V 9400,14400,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 7000,16200,CONT_DIF_P,* +V 7000,18600,CONT_VIA,* +V 7000,17000,CONT_VIA,* +V 7000,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 3400,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 8200,2800,CONT_BODY_N,* +V 4600,17000,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 9400,17000,CONT_VIA,* +V 9400,17800,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 5800,17000,CONT_DIF_P,* +V 10600,19400,CONT_BODY_N,* +V 10600,17800,CONT_BODY_N,* +V 10600,18600,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 10600,17000,CONT_VIA,* +V 5800,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,8800,CONT_DIF_P,* +V 7000,9600,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,9600,CONT_VIA,* +V 7000,10400,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,4800,CONT_DIF_P,* +V 10600,14400,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,14400,CONT_BODY_N,* +V 10600,9600,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 2200,15400,CONT_VIA,* +V 9400,27200,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,24000,CONT_DIF_N,* +V 10600,27200,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,30000,CONT_BODY_P,* +V 2200,30000,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 7000,22800,CONT_BODY_P,* +V 10600,24800,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 11600,21800,CONT_VIA,* +V 7000,30000,CONT_VIA,* +V 4600,30000,CONT_VIA,* +V 2200,30000,CONT_VIA,* +V 1000,30000,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib80/cells/pbuf_oc.ap b/pdks/symbolic/phlib80/cells/pbuf_oc.ap new file mode 100644 index 000000000..103a2b057 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pbuf_oc.ap @@ -0,0 +1,449 @@ +V ALLIANCE : 6 +H pbuf_oc,P,17/ 8/2019,100 +A 0,0,12300,31200 +C 12300,1400,900,ck,1,EAST,ALU2 +C 12300,26400,7600,vss,1,EAST,ALU2 +C 12300,11800,18400,vdd,1,EAST,ALU2 +C 0,1400,900,ck,0,WEST,ALU1 +C 12000,0,300,i,1,SOUTH,ALU2 +C 12000,0,300,i,0,SOUTH,ALU1 +C 0,11800,18400,vdd,0,WEST,ALU1 +C 0,26400,7600,vss,0,WEST,ALU2 +C 3400,31200,1000,pad,0,NORTH,ALU1 +C 5800,31200,1000,pad,1,NORTH,ALU1 +S 0,1400,12300,1400,1300,ck,RIGHT,CALU2 +S 0,2800,12300,2800,500,vdd,LEFT,CALU2 +S 0,5600,12300,5600,500,vdd,RIGHT,CALU2 +S 0,8000,12300,8000,500,vdd,LEFT,CALU2 +S 0,9600,12300,9600,500,vdd,RIGHT,CALU2 +S 0,11200,12300,11200,500,vdd,LEFT,CALU2 +S 0,13600,12300,13600,500,vdd,RIGHT,CALU2 +S 0,15400,12300,15400,500,vdd,LEFT,CALU2 +S 0,17000,12300,17000,500,vdd,RIGHT,CALU2 +S 0,18600,12300,18600,500,vdd,LEFT,CALU2 +S 0,20800,12300,20800,500,vdd,RIGHT,CALU2 +S 0,22800,12300,22800,500,vss,LEFT,CALU2 +S 0,24800,12300,24800,500,vss,RIGHT,CALU2 +S 0,26400,12300,26400,500,vss,LEFT,CALU2 +S 0,28000,12300,28000,500,vss,RIGHT,CALU2 +S 0,30000,12300,30000,500,vss,RIGHT,CALU2 +S 7000,22000,7000,22800,400,*,UP,ALU1 +S 6400,19900,6400,22000,200,*,UP,POLY +S 6400,22000,7000,22000,600,*,RIGHT,POLY +S 900,30000,2200,30000,400,*,RIGHT,ALU1 +S 2200,22900,2200,29800,400,*,UP,ALU1 +S 1000,22800,2200,22800,300,*,LEFT,ALU1 +S 1000,24000,2200,24000,300,*,LEFT,ALU1 +S 1000,25600,2200,25600,300,*,LEFT,ALU1 +S 1000,27200,2200,27200,300,*,LEFT,ALU1 +S 1000,28800,2200,28800,300,*,LEFT,ALU1 +S -100,2800,12900,2800,500,*,RIGHT,ALU2 +S -100,5600,12900,5600,500,*,LEFT,ALU2 +S -100,8000,12900,8000,500,*,RIGHT,ALU2 +S -100,9600,12900,9600,500,*,LEFT,ALU2 +S -100,11200,12900,11200,500,*,RIGHT,ALU2 +S -100,13600,12900,13600,500,*,LEFT,ALU2 +S -100,15400,12900,15400,500,*,RIGHT,ALU2 +S -200,17000,12900,17000,500,*,LEFT,ALU2 +S -100,18600,12900,18600,500,*,RIGHT,ALU2 +S -100,20800,12900,20800,500,*,LEFT,ALU2 +S -100,22800,12900,22800,500,*,RIGHT,ALU2 +S -100,24800,12900,24800,500,*,LEFT,ALU2 +S -100,26400,12900,26400,500,*,RIGHT,ALU2 +S 0,28000,12900,28000,500,*,LEFT,ALU2 +S -100,30000,12900,30000,500,*,RIGHT,ALU2 +S 5800,4900,5800,31300,400,*,UP,ALU1 +S 0,1400,12700,1400,1300,*,RIGHT,ALU2 +S 2800,15400,6400,15400,200,*,RIGHT,POLY +S 7100,30000,10500,30000,300,*,LEFT,ALU1 +S 6400,1600,6400,21600,12800,*,UP,NWELL +S 6400,21600,6400,31200,12800,*,DOWN,PWELL +S 3400,4900,3400,31300,400,*,UP,ALU1 +S 9500,20800,10500,20800,300,*,LEFT,ALU1 +S 10600,16500,10600,20700,400,*,DOWN,ALU1 +S 9400,16500,9400,20700,400,*,UP,ALU1 +S 4600,2900,4600,20700,400,*,UP,ALU1 +S 1000,2900,1000,20700,400,*,UP,ALU1 +S 1100,20800,2100,20800,400,*,RIGHT,ALU1 +S 2200,2900,2200,20700,400,*,UP,ALU1 +S 700,20800,10900,20800,600,*,LEFT,NTIE +S 8800,28800,8800,29200,200,*,DOWN,POLY +S 8800,29000,9200,29000,600,*,RIGHT,POLY +S 9500,22800,10500,22800,300,*,LEFT,ALU1 +S 7000,22900,7000,27900,400,*,UP,ALU1 +S 9400,22900,9400,27900,400,*,UP,ALU1 +S 10600,22900,10600,27900,400,*,UP,ALU1 +S 7100,29000,8100,29000,300,*,LEFT,ALU1 +S 2800,28800,7000,28800,200,*,LEFT,POLY +S 7000,23900,7000,28300,600,*,UP,NDIF +S 2200,23900,2200,28300,600,*,UP,NDIF +S 2800,23700,2800,28500,200,*,UP,NTRANS +S 4000,23700,4000,28500,200,*,UP,NTRANS +S 5200,23700,5200,28500,200,*,UP,NTRANS +S 6400,23700,6400,28500,200,*,UP,NTRANS +S 9400,23900,9400,28300,600,*,UP,NDIF +S 8200,23900,8200,28300,600,*,UP,NDIF +S 8800,23700,8800,28500,200,*,UP,NTRANS +S 8200,3900,8200,28900,400,*,DOWN,ALU1 +S 7100,3800,8100,3800,300,*,LEFT,ALU1 +S 7000,4500,7000,8900,600,*,UP,PDIF +S 2200,4500,2200,8900,600,*,UP,PDIF +S 2800,4300,2800,9100,200,*,UP,PTRANS +S 4000,4300,4000,9100,200,*,UP,PTRANS +S 5200,4300,5200,9100,200,*,UP,PTRANS +S 6400,4300,6400,9100,200,*,UP,PTRANS +S 10600,22500,10600,30300,600,*,DOWN,PTIE +S 1000,22500,1000,30300,600,*,DOWN,PTIE +S 700,22800,10900,22800,600,*,LEFT,PTIE +S 700,30000,10900,30000,600,*,LEFT,PTIE +S 9400,2900,9400,14300,400,*,UP,ALU1 +S 1100,2800,10500,2800,300,*,LEFT,ALU1 +S 2200,10300,2200,14700,600,*,UP,PDIF +S 2800,10100,2800,14900,200,*,UP,PTRANS +S 4000,10100,4000,14900,200,*,UP,PTRANS +S 5200,10100,5200,14900,200,*,DOWN,PTRANS +S 7000,10300,7000,14700,600,*,UP,PDIF +S 6400,10100,6400,14900,200,*,UP,PTRANS +S 2800,15000,2800,15800,200,*,UP,POLY +S 4000,15000,4000,15800,200,*,UP,POLY +S 5200,15000,5200,15800,200,*,UP,POLY +S 6400,15000,6400,15800,200,*,UP,POLY +S 8800,15400,9200,15400,600,*,RIGHT,POLY +S 8800,15200,8800,15600,200,*,UP,POLY +S 10600,2900,10600,14300,400,*,DOWN,ALU1 +S 10600,2500,10600,20900,600,*,UP,NTIE +S 8800,15900,8800,19700,200,*,UP,PTRANS +S 8200,16100,8200,19500,600,*,UP,PDIF +S 9400,16100,9400,19500,600,*,UP,PDIF +S 6400,15900,6400,19700,200,*,UP,PTRANS +S 7000,16100,7000,19500,600,*,UP,PDIF +S 5200,15900,5200,19700,200,*,UP,PTRANS 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9400,18600,10600,18600,300,*,LEFT,ALU1 +S 9400,17800,10600,17800,400,*,RIGHT,ALU1 +S 9400,17000,10600,17000,300,*,LEFT,ALU1 +S 9400,14400,10600,14400,300,*,LEFT,ALU1 +S 9400,13600,10600,13600,400,*,RIGHT,ALU1 +S 9400,12800,10600,12800,300,*,LEFT,ALU1 +S 9400,12000,10600,12000,400,*,RIGHT,ALU1 +S 9400,11200,10600,11200,300,*,LEFT,ALU1 +S 9400,10400,10600,10400,400,*,RIGHT,ALU1 +S 9400,9600,10600,9600,300,*,LEFT,ALU1 +S 9400,8800,10600,8800,400,*,RIGHT,ALU1 +S 9400,8000,10600,8000,300,*,LEFT,ALU1 +S 9400,7200,10600,7200,400,*,RIGHT,ALU1 +S 9400,6400,10600,6400,300,*,LEFT,ALU1 +S 9400,5600,10600,5600,400,*,RIGHT,ALU1 +S 9400,4800,10600,4800,300,*,LEFT,ALU1 +S 9400,2800,10700,2800,400,*,RIGHT,ALU1 +S 1000,2800,2200,2800,400,*,RIGHT,ALU1 +S 1000,4800,2200,4800,300,*,LEFT,ALU1 +S 1000,5600,2200,5600,400,*,RIGHT,ALU1 +S 1000,6400,2200,6400,300,*,LEFT,ALU1 +S 1000,7200,2200,7200,400,*,RIGHT,ALU1 +S 1000,8000,2200,8000,300,*,LEFT,ALU1 +S 1000,8800,2200,8800,400,*,RIGHT,ALU1 +S 1000,9600,2200,9600,300,*,LEFT,ALU1 +S 1000,10400,2200,10400,400,*,RIGHT,ALU1 +S 1000,11200,2200,11200,300,*,LEFT,ALU1 +S 1000,12000,2200,12000,400,*,RIGHT,ALU1 +S 1000,12800,2200,12800,300,*,LEFT,ALU1 +S 1000,13600,2200,13600,400,*,RIGHT,ALU1 +S 1000,14400,2200,14400,300,*,LEFT,ALU1 +S 1000,15400,2200,15400,400,*,RIGHT,ALU1 +S 1000,16200,2200,16200,300,*,LEFT,ALU1 +S 1000,17000,2200,17000,400,*,RIGHT,ALU1 +S 1000,17800,2200,17800,300,*,LEFT,ALU1 +S 1000,18600,2200,18600,400,*,RIGHT,ALU1 +S 1000,19400,2200,19400,300,*,LEFT,ALU1 +S 1000,20800,2200,20800,400,*,RIGHT,ALU1 +S 3200,23900,3200,28300,600,*,UP,NDIF +S 4600,23900,4600,28300,600,*,UP,NDIF +S 5800,23900,5800,28300,600,*,UP,NDIF +S 3300,16100,3300,19500,600,*,UP,PDIF +S 4500,16100,4500,19500,600,*,UP,PDIF +S 5800,16100,5800,19500,600,*,UP,PDIF +S 3300,10300,3300,14700,600,*,UP,PDIF +S 4600,10300,4600,14700,600,*,UP,PDIF +S 5900,10300,5900,14700,600,*,UP,PDIF +S 3400,4500,3400,8900,600,*,UP,PDIF +S 4600,4500,4600,8900,600,*,UP,PDIF +S 5800,4500,5800,8900,600,*,UP,PDIF +S 9300,15400,12000,15400,400,*,RIGHT,ALU1 +S 9300,29000,12000,29000,300,*,LEFT,ALU1 +V 7000,22000,CONT_POLY,* +V 1000,30000,CONT_VIA,* +V 2200,30000,CONT_VIA,* +V 1000,30000,CONT_BODY_P,* +V 2200,30000,CONT_BODY_P,* +V 1000,28000,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 10600,24800,CONT_VIA,* +V 8200,30000,CONT_VIA,* +V 9400,30000,CONT_VIA,* +V 7000,30000,CONT_BODY_P,* +V 10600,30000,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 7000,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,27200,CONT_BODY_P,* +V 2200,24000,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,27200,CONT_DIF_N,* +V 2200,15400,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,9600,CONT_VIA,* +V 1000,14400,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,14400,CONT_BODY_N,* +V 9400,4800,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,9600,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,10400,CONT_DIF_P,* +V 2200,9600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,9600,CONT_VIA,* +V 7000,8800,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 5800,17800,CONT_DIF_P,* +V 10600,17000,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 10600,18600,CONT_VIA,* +V 10600,17800,CONT_BODY_N,* +V 10600,19400,CONT_BODY_N,* +V 5800,17000,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 9400,17800,CONT_DIF_P,* +V 9400,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 4600,17000,CONT_VIA,* +V 8200,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 5800,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 3400,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 7000,20800,CONT_BODY_N,* +V 7000,17000,CONT_VIA,* +V 7000,18600,CONT_VIA,* +V 7000,16200,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 9400,14400,CONT_DIF_P,* +V 9200,29000,CONT_POLY,* +V 9400,22800,CONT_VIA,* +V 7000,29000,CONT_POLY,* +V 7000,3800,CONT_POLY,* +V 10600,22800,CONT_BODY_P,* +V 9200,15400,CONT_POLY,* +V 8200,19400,CONT_DIF_P,* +V 9400,19400,CONT_DIF_P,* +V 10600,2800,CONT_BODY_N,* +V 8200,21800,CONT_VIA,* +V 1000,9600,CONT_VIA,* +V 12000,0,CONT_VIA,* +V 1000,19400,CONT_BODY_N,* +V 1000,17800,CONT_BODY_N,* +V 1000,16200,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/phlib80/cells/pbuf_oe.ap b/pdks/symbolic/phlib80/cells/pbuf_oe.ap new file mode 100644 index 000000000..10dc648ba --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pbuf_oe.ap @@ -0,0 +1,453 @@ +V ALLIANCE : 6 +H pbuf_oe,P,17/ 8/2019,100 +A 0,0,12300,31200 +C 12300,1400,900,ck,1,EAST,ALU2 +C 12300,11800,18400,vdd,1,EAST,ALU2 +C 12300,26400,7600,vss,1,EAST,ALU2 +C 0,1400,900,ck,0,WEST,ALU2 +C 0,11800,18400,vdd,0,WEST,ALU2 +C 0,26400,7600,vss,0,WEST,ALU2 +S 0,1400,12300,1400,1300,ck,RIGHT,CALU2 +S 0,2800,12300,2800,500,vdd,LEFT,CALU2 +S 0,5600,12300,5600,500,vdd,RIGHT,CALU2 +S 0,8000,12300,8000,500,vdd,LEFT,CALU2 +S 0,9600,12300,9600,500,vdd,RIGHT,CALU2 +S 0,11200,12300,11200,500,vdd,LEFT,CALU2 +S 0,13600,12300,13600,500,vdd,RIGHT,CALU2 +S 0,15400,12300,15400,500,vdd,LEFT,CALU2 +S 0,17000,12300,17000,500,vdd,RIGHT,CALU2 +S 0,18600,12300,18600,500,vdd,LEFT,CALU2 +S 0,20800,12300,20800,500,vdd,RIGHT,CALU2 +S 0,22800,12300,22800,500,vss,LEFT,CALU2 +S 0,24800,12300,24800,500,vss,RIGHT,CALU2 +S 0,26400,12300,26400,500,vss,LEFT,CALU2 +S 0,28000,12300,28000,500,vss,RIGHT,CALU2 +S 0,30000,12300,30000,500,vss,RIGHT,CALU2 +S 8800,19800,8800,22100,200,*,UP,POLY +S 9400,22000,9400,22800,400,*,DOWN,ALU1 +S 8800,22000,9200,22000,600,*,RIGHT,POLY +S 11700,1600,11700,15400,400,*,UP,ALU1 +S 11600,21600,11600,29000,500,*,UP,ALU1 +S -500,1400,12100,1400,1300,*,RIGHT,ALU2 +S -300,2800,12100,2800,500,*,RIGHT,ALU2 +S -300,5600,12100,5600,500,*,RIGHT,ALU2 +S -300,8000,12100,8000,500,*,RIGHT,ALU2 +S -300,9600,12100,9600,500,*,RIGHT,ALU2 +S -300,11200,12100,11200,500,*,RIGHT,ALU2 +S -300,13600,12100,13600,500,*,RIGHT,ALU2 +S -300,17000,12100,17000,500,*,RIGHT,ALU2 +S -300,18600,12100,18600,500,*,RIGHT,ALU2 +S -300,20800,12100,20800,500,*,LEFT,ALU2 +S -300,22800,12100,22800,500,*,RIGHT,ALU2 +S -300,24800,12100,24800,500,*,LEFT,ALU2 +S -300,26400,12100,26400,500,*,RIGHT,ALU2 +S -300,28000,12100,28000,500,*,LEFT,ALU2 +S -300,30000,12100,30000,500,*,RIGHT,ALU2 +S 1000,22800,2200,22800,300,*,LEFT,ALU1 +S 1000,24000,2200,24000,300,*,LEFT,ALU1 +S 1000,25600,2200,25600,300,*,LEFT,ALU1 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9400,18600,10600,18600,300,*,LEFT,ALU1 +S 9400,17800,10600,17800,400,*,RIGHT,ALU1 +S 9400,17000,10600,17000,300,*,LEFT,ALU1 +S 9400,14400,10600,14400,400,*,RIGHT,ALU1 +S 9400,13600,10600,13600,300,*,LEFT,ALU1 +S 9400,12800,10600,12800,400,*,RIGHT,ALU1 +S 9400,12000,10600,12000,300,*,LEFT,ALU1 +S 9400,11200,10600,11200,400,*,RIGHT,ALU1 +S 9400,10400,10600,10400,300,*,LEFT,ALU1 +S 9400,9600,10600,9600,400,*,RIGHT,ALU1 +S 9400,8800,10600,8800,300,*,LEFT,ALU1 +S 9400,8000,10600,8000,400,*,RIGHT,ALU1 +S 9400,7200,10600,7200,300,*,LEFT,ALU1 +S 9400,6400,10600,6400,400,*,RIGHT,ALU1 +S 9400,5600,10600,5600,300,*,LEFT,ALU1 +S 9400,4800,10600,4800,400,*,RIGHT,ALU1 +S 9400,2800,10600,2800,300,*,LEFT,ALU1 +S 1000,2800,2200,2800,400,*,RIGHT,ALU1 +S 1000,4800,2200,4800,300,*,LEFT,ALU1 +S 1000,5600,2200,5600,400,*,RIGHT,ALU1 +S 1000,6400,2200,6400,300,*,LEFT,ALU1 +S 1000,7200,2200,7200,400,*,RIGHT,ALU1 +S 1000,8000,2200,8000,300,*,LEFT,ALU1 +S 1000,8800,2200,8800,400,*,RIGHT,ALU1 +S 1000,9600,2200,9600,300,*,LEFT,ALU1 +S 1000,10400,2200,10400,400,*,RIGHT,ALU1 +S 1000,11200,2200,11200,300,*,LEFT,ALU1 +S 1000,12000,2200,12000,400,*,RIGHT,ALU1 +S 1000,12800,2200,12800,300,*,LEFT,ALU1 +S 1000,13600,2200,13600,400,*,RIGHT,ALU1 +S 1000,14400,2200,14400,300,*,LEFT,ALU1 +S 1000,15400,2200,15400,400,*,RIGHT,ALU1 +S 1000,16200,2200,16200,300,*,LEFT,ALU1 +S 1000,17000,2200,17000,400,*,RIGHT,ALU1 +S 1000,17800,2200,17800,300,*,LEFT,ALU1 +S 1000,18600,2200,18600,400,*,RIGHT,ALU1 +S 1000,19400,2200,19400,300,*,LEFT,ALU1 +S 1000,20800,2200,20800,400,*,RIGHT,ALU1 +S 3400,23900,3400,28300,600,*,UP,NDIF +S 4500,23900,4500,28300,600,*,UP,NDIF +S 5700,23900,5700,28300,600,*,UP,NDIF +S 6900,23900,6900,28300,600,*,UP,NDIF +S 3400,16100,3400,19500,600,*,UP,PDIF +S 4500,16100,4500,19500,600,*,UP,PDIF +S 5800,16100,5800,19500,600,*,UP,PDIF +S 7000,16100,7000,19500,600,*,UP,PDIF +S 8200,10300,8200,14700,600,*,DOWN,PDIF +S 7000,10300,7000,14700,600,*,DOWN,PDIF +S 5800,10300,5800,14700,600,*,DOWN,PDIF +S 4600,10300,4600,14700,600,*,DOWN,PDIF +S 3400,10300,3400,14700,600,*,DOWN,PDIF +S 3400,4500,3400,8900,600,*,UP,PDIF +S 4600,4500,4600,8900,600,*,UP,PDIF +S 5800,4500,5800,8900,600,*,UP,PDIF +S 7000,4500,7000,8900,600,*,UP,PDIF +S 8200,4500,8200,8900,600,*,UP,PDIF +S 8200,4900,8200,31300,400,*,DOWN,ALU1 +S 11400,21800,12100,21800,600,*,LEFT,ALU2 +V 9200,22000,CONT_POLY,* +V 1000,30000,CONT_VIA,* +V 2200,30000,CONT_VIA,* +V 4600,30000,CONT_VIA,* +V 7000,30000,CONT_VIA,* +V 11600,21800,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 10600,24800,CONT_VIA,* +V 7000,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 2200,30000,CONT_BODY_P,* +V 1000,30000,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,27200,CONT_BODY_P,* +V 2200,24000,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,27200,CONT_DIF_N,* +V 2200,15400,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,9600,CONT_VIA,* +V 1000,14400,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,14400,CONT_BODY_N,* +V 9400,4800,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,10400,CONT_DIF_P,* +V 2200,9600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,9600,CONT_VIA,* +V 7000,8800,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 5800,17800,CONT_DIF_P,* +V 10600,17000,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 10600,18600,CONT_VIA,* +V 10600,17800,CONT_BODY_N,* +V 10600,19400,CONT_BODY_N,* +V 5800,17000,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 9400,17800,CONT_DIF_P,* +V 9400,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 4600,17000,CONT_VIA,* +V 8200,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 3400,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 7000,20800,CONT_BODY_N,* +V 7000,17000,CONT_VIA,* +V 7000,18600,CONT_VIA,* +V 7000,16200,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 9400,14400,CONT_DIF_P,* +V 9200,29000,CONT_POLY,* +V 9400,22800,CONT_VIA,* +V 10600,22800,CONT_BODY_P,* +V 9200,15400,CONT_POLY,* +V 8200,19400,CONT_DIF_P,* +V 9400,19400,CONT_DIF_P,* +V 10600,2800,CONT_BODY_N,* +V 5800,3600,CONT_POLY,* +V 7000,30000,CONT_BODY_P,* +V 5800,30000,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 3400,30000,CONT_BODY_P,* +V 1000,9600,CONT_VIA,* +V 1000,19400,CONT_BODY_N,* +V 1000,17800,CONT_BODY_N,* +V 1000,16200,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/phlib80/cells/pck_sp.ap b/pdks/symbolic/phlib80/cells/pck_sp.ap new file mode 100644 index 000000000..1ebb7b7ce --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pck_sp.ap @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H pck_sp,P,19/ 2/2020,100 +A 0,0,24600,31200 +C 24600,19100,200,vdd,2,EAST,ALU2 +C 24600,1400,1200,ck,1,EAST,ALU2 +C 24600,11800,18400,vdd,1,EAST,ALU2 +C 24600,26400,7600,vss,1,EAST,ALU2 +C 0,26400,7600,vss,0,WEST,ALU2 +C 0,11800,18400,vdd,0,WEST,ALU2 +C 0,1400,1200,ck,0,WEST,ALU2 +C 14100,31200,13000,pad,0,NORTH,ALU1 +S 14100,31200,14100,33800,600,pad,UP,CALU1 +S 14100,31200,14100,33800,600,*,UP,ALU1 +S 7900,31100,20100,31100,400,pad,RIGHT,CALU1 +S -200,1400,24800,1400,1300,ck,RIGHT,CALU2 +S -200,2800,24800,2800,500,vdd,LEFT,CALU2 +S -200,5600,24800,5600,500,vdd,RIGHT,CALU2 +S -200,8000,24800,8000,500,vdd,LEFT,CALU2 +S -200,9600,24800,9600,500,vdd,RIGHT,CALU2 +S -200,11200,24800,11200,500,vdd,LEFT,CALU2 +S -200,13600,24800,13600,500,vdd,RIGHT,CALU2 +S -200,15400,24800,15400,500,vdd,LEFT,CALU2 +S -200,17000,24800,17000,500,vdd,RIGHT,CALU2 +S -200,18600,24800,18600,500,vdd,LEFT,CALU2 +S -200,20800,24800,20800,500,vdd,RIGHT,CALU2 +S -200,22800,24800,22800,500,vss,LEFT,CALU2 +S -200,24800,24800,24800,500,vss,RIGHT,CALU2 +S -200,26400,24800,26400,500,vss,LEFT,CALU2 +S -200,28000,24800,28000,500,vss,RIGHT,CALU2 +S -200,30000,24800,30000,500,vss,RIGHT,CALU2 +S 7900,31100,20100,31100,300,*,RIGHT,ALU1 +I 12300,0,ck_buf,ckbuf_r,NOSYM +I 0,0,ck_buf,ck,NOSYM +EOF diff --git a/pdks/symbolic/phlib80/cells/pck_sp.vbe b/pdks/symbolic/phlib80/cells/pck_sp.vbe new file mode 100644 index 000000000..ea3ae4ff0 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pck_sp.vbe @@ -0,0 +1,40 @@ +-- VHDL data flow description generated from `pck_sp` +-- date : Thu Feb 23 17:05:59 1995 + + +-- Entity Declaration + +ENTITY pck_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_pad : NATURAL := 1326; -- cin_pad + CONSTANT tpll_pad : NATURAL := 1443; -- tpll_pad + CONSTANT rdown_pad : NATURAL := 58; -- rdown_pad + CONSTANT tphh_pad : NATURAL := 228; -- tphh_pad + CONSTANT rup_pad : NATURAL := 68 -- rup_pad + ); + PORT ( + pad : in BIT; -- pad + ck : out BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vsi + --vdde : in BIT; -- vdde + --vddi : in BIT; -- vddi + --vsse : in BIT; -- vsse + --vssi : in BIT -- vssi + ); +END pck_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pck_sp IS + +BEGIN + ASSERT ((((vdd and vdd)and not (vss)) and not (vss)) = '1') + REPORT "power supply is missing on pck_sp" + SEVERITY WARNING; + + +ck <= pad; +END; diff --git a/pdks/symbolic/phlib80/cells/pi_sp.ap b/pdks/symbolic/phlib80/cells/pi_sp.ap new file mode 100644 index 000000000..7a42a8ffb --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pi_sp.ap @@ -0,0 +1,40 @@ +V ALLIANCE : 6 +H pi_sp,P,27/ 9/2019,100 +A 0,0,24600,31200 +C 19900,34400,1000,pad,2,NORTH,ALU1 +C 7600,34000,1000,pad,1,NORTH,ALU1 +C 24600,26400,7600,vss,0,EAST,ALU2 +C 24600,11800,18400,vdd,0,EAST,ALU2 +C 24600,1300,1200,ck,0,EAST,ALU2 +C 14200,31200,13000,pad,0,NORTH,ALU1 +C 0,26500,7600,vss,1,WEST,ALU2 +C 0,1400,1200,ck,1,WEST,ALU2 +C 0,11900,18400,vdd,1,WEST,ALU2 +C 3400,0,300,t,0,SOUTH,ALU1 +C 3400,0,300,t,1,SOUTH,ALU2 +S -200,30000,24800,30000,500,vss,RIGHT,CALU2 +S -200,28000,24800,28000,500,vss,RIGHT,CALU2 +S -200,26400,24800,26400,500,vss,LEFT,CALU2 +S -200,24800,24800,24800,500,vss,RIGHT,CALU2 +S -200,22800,24800,22800,500,vss,LEFT,CALU2 +S -200,20800,24800,20800,500,vdd,RIGHT,CALU2 +S -200,18600,24800,18600,500,vdd,LEFT,CALU2 +S -200,17000,24800,17000,500,vdd,RIGHT,CALU2 +S -200,15400,24800,15400,500,vdd,LEFT,CALU2 +S -200,13600,24800,13600,500,vdd,RIGHT,CALU2 +S -200,11200,24800,11200,500,vdd,LEFT,CALU2 +S -200,9600,24800,9600,500,vdd,RIGHT,CALU2 +S -200,8000,24800,8000,500,vdd,LEFT,CALU2 +S -200,5600,24800,5600,500,vdd,RIGHT,CALU2 +S -200,2800,24800,2800,500,vdd,LEFT,CALU2 +S -200,1400,24800,1400,1300,ck,RIGHT,CALU2 +S 3500,21900,16200,21900,400,*,LEFT,ALU2 +S 19900,31400,19900,34200,800,pad,UP,CALU1 +S 19900,31400,19900,34200,800,pad,UP,ALU1 +S 7600,31300,7600,33800,800,pad,DOWN,CALU1 +S 7600,31300,7600,33800,800,pad,DOWN,ALU1 +I 0,0,i_buf,ibuf,NOSYM +I 12300,0,i_buf2,ibuf_r,NOSYM +V 3600,21900,CONT_VIA,* +V 16200,21900,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib80/cells/pi_sp.vbe b/pdks/symbolic/phlib80/cells/pi_sp.vbe new file mode 100644 index 000000000..22d6de503 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pi_sp.vbe @@ -0,0 +1,37 @@ +-- VHDL data flow description generated from `pi_sp` +-- date : Thu Feb 23 17:06:23 1995 + + +-- Entity Declaration + +ENTITY pi_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_pad : NATURAL := 654; -- cin_pad + CONSTANT tpll_pad : NATURAL := 1487; -- tpll_pad + CONSTANT rdown_pad : NATURAL := 234; -- rdown_pad + CONSTANT tphh_pad : NATURAL := 233; -- tphh_pad + CONSTANT rup_pad : NATURAL := 273 -- rup_pad + ); + PORT ( + pad : in BIT; -- pad + t : out BIT; -- t + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + ); +END pi_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pi_sp IS + +BEGIN + ASSERT ((((vdd and vdd) and not (vss)) and not (vss)) = '1') + REPORT "power supply is missing on pi_sp" + SEVERITY WARNING; + + +t <= pad; +END; diff --git a/pdks/symbolic/phlib80/cells/po_sp.ap b/pdks/symbolic/phlib80/cells/po_sp.ap new file mode 100644 index 000000000..9b6d858fc --- /dev/null +++ b/pdks/symbolic/phlib80/cells/po_sp.ap @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H po_sp,P,27/ 9/2019,100 +A 0,0,24600,31200 +C 13100,32500,10000,pad,2,NORTH,ALU1 +C 15800,31200,8000,pad,1,NORTH,CALU1 +C 0,11800,18400,vdd,0,WEST,ALU2 +C 0,26600,7600,vss,1,WEST,ALU2 +C 0,1400,900,ck,1,WEST,ALU2 +C 24600,12000,18400,vdd,1,EAST,ALU2 +C 24600,26400,7600,vss,0,EAST,ALU2 +C 24600,1400,900,ck,2,EAST,ALU2 +C 24300,0,100,i,0,SOUTH,ALU1 +C 24300,0,100,i,1,SOUTH,ALU2 +C 24600,1200,200,ck,0,EAST,ALU2 +S -200,30000,24800,30000,500,vss,RIGHT,CALU2 +S -200,28000,24800,28000,500,vss,RIGHT,CALU2 +S -200,26400,24800,26400,500,vss,LEFT,CALU2 +S -200,24800,24800,24800,500,vss,RIGHT,CALU2 +S -200,22800,24800,22800,500,vss,LEFT,CALU2 +S -200,20800,24800,20800,500,vdd,RIGHT,CALU2 +S -200,18600,24800,18600,500,vdd,LEFT,CALU2 +S -200,17000,24800,17000,500,vdd,RIGHT,CALU2 +S -200,15400,24800,15400,500,vdd,LEFT,CALU2 +S -200,13600,24800,13600,500,vdd,RIGHT,CALU2 +S -200,11200,24800,11200,500,vdd,LEFT,CALU2 +S -200,9600,24800,9600,500,vdd,RIGHT,CALU2 +S -200,8000,24800,8000,500,vdd,LEFT,CALU2 +S -200,5600,24800,5600,500,vdd,RIGHT,CALU2 +S -200,2800,24800,2800,500,vdd,LEFT,CALU2 +S -200,1400,24800,1400,1300,ck,RIGHT,CALU2 +S 8200,32000,18300,32000,800,*,RIGHT,ALU1 +I 0,0,pbuf_e,ext,NOSYM +I 12300,0,pbuf_c,con,NOSYM +EOF diff --git a/pdks/symbolic/phlib80/cells/po_sp.vbe b/pdks/symbolic/phlib80/cells/po_sp.vbe new file mode 100644 index 000000000..df9f47c42 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/po_sp.vbe @@ -0,0 +1,41 @@ +-- VHDL data flow description generated from `po_sp` +-- date : Thu Feb 23 17:08:20 1995 + + +-- Entity Declaration + +ENTITY po_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_i : NATURAL := 191; -- cin_i + CONSTANT tpll_i : NATURAL := 2176; -- tpll_i + CONSTANT rdown_i : NATURAL := 15; -- rdown_i + CONSTANT tphh_i : NATURAL := 2032; -- tphh_i + CONSTANT rup_i : NATURAL := 16 -- rup_i + ); + PORT ( + i : in BIT; -- i + pad : out BIT; -- pad + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + -- vdde : in BIT; -- vdde + -- vddi : in BIT; -- vddi + -- vsse : in BIT; -- vsse + -- vssi : in BIT -- vssi + ); +END po_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF po_sp IS + +BEGIN + ASSERT ((((vdd and vdd) and not (vss)) and not (vss)) = '1') + REPORT "power supply is missing on po_sp" + SEVERITY WARNING; + + +pad <= i; +END; diff --git a/pdks/symbolic/phlib80/cells/pod_sp.ap b/pdks/symbolic/phlib80/cells/pod_sp.ap new file mode 100644 index 000000000..b1a706edd --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pod_sp.ap @@ -0,0 +1,35 @@ +V ALLIANCE : 6 +H pod_sp,P,27/ 9/2019,100 +A 0,0,24600,31200 +C 13000,32500,10000,pad,2,NORTH,ALU1 +C 15800,31200,8000,pad,1,NORTH,CALU1 +C 0,11800,18400,vdd,0,WEST,ALU2 +C 0,26600,7600,vss,1,WEST,ALU2 +C 0,1400,900,ck,1,WEST,ALU2 +C 24600,12000,18400,vdd,1,EAST,ALU2 +C 24600,26400,7600,vss,0,EAST,ALU2 +C 24600,1400,900,ck,2,EAST,ALU2 +C 24300,0,100,i,0,SOUTH,ALU1 +C 24300,0,100,i,1,SOUTH,ALU2 +C 24600,1200,200,ck,0,EAST,ALU2 +S 8300,32300,18300,32300,200,pad,RIGHT,CALU1 +S -200,30000,24800,30000,500,vss,RIGHT,CALU2 +S -200,28000,24800,28000,500,vss,RIGHT,CALU2 +S -200,26400,24800,26400,500,vss,LEFT,CALU2 +S -200,24800,24800,24800,500,vss,RIGHT,CALU2 +S -200,22800,24800,22800,500,vss,LEFT,CALU2 +S -200,20800,24800,20800,500,vdd,RIGHT,CALU2 +S -200,18600,24800,18600,500,vdd,LEFT,CALU2 +S -200,17000,24800,17000,500,vdd,RIGHT,CALU2 +S -200,15400,24800,15400,500,vdd,LEFT,CALU2 +S -200,13600,24800,13600,500,vdd,RIGHT,CALU2 +S -200,11200,24800,11200,500,vdd,LEFT,CALU2 +S -200,9600,24800,9600,500,vdd,RIGHT,CALU2 +S -200,8000,24800,8000,500,vdd,LEFT,CALU2 +S -200,5600,24800,5600,500,vdd,RIGHT,CALU2 +S -200,2800,24800,2800,500,vdd,LEFT,CALU2 +S -200,1400,24800,1400,1300,ck,RIGHT,CALU2 +S 8200,32000,18300,32000,800,*,RIGHT,ALU1 +I 0,0,pbuf_oe,ext,NOSYM +I 12300,0,pbuf_oc,con,NOSYM +EOF diff --git a/pdks/symbolic/phlib80/cells/pod_sp.vbe b/pdks/symbolic/phlib80/cells/pod_sp.vbe new file mode 100644 index 000000000..d1273f605 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pod_sp.vbe @@ -0,0 +1,27 @@ +ENTITY pod_sp IS + GENERIC ( + CONSTANT area : NATURAL := 80000; + CONSTANT rup : NATURAL := 684404; + CONSTANT rdown : NATURAL := 24 + ); + PORT ( + i : in BIT; + pad : out MUX_BIT BUS; + ck : in BIT; + vdd : in BIT; + vss : in BIT + ); +END pod_sp; + +ARCHITECTURE behaviour_data_flow OF pod_sp IS + +BEGIN + label0 : BLOCK (i = '0') + BEGIN + pad <= guarded '0'; + END BLOCK label0; + + ASSERT ((vdd and not vss ) = '1') + REPORT "power supply is missing on pod_sp" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/phlib80/cells/prow_sp.ap b/pdks/symbolic/phlib80/cells/prow_sp.ap new file mode 100644 index 000000000..7b861f95e --- /dev/null +++ b/pdks/symbolic/phlib80/cells/prow_sp.ap @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H prow_sp,P,23/ 9/2019,100 +A 0,0,24600,31200 +C 24600,26400,7600,vss,3,EAST,ALU2 +C 24600,11800,18400,vdd,1,EAST,ALU2 +C 24600,1500,1200,ck,1,EAST,ALU2 +C 12700,16200,200,vdd,2,EAST,ALU2 +C 12700,26700,200,vss,4,EAST,ALU2 +C 0,26400,7600,vss,2,WEST,ALU2 +C 0,11600,18400,vdd,0,WEST,ALU2 +C 0,1400,1200,ck,0,WEST,ALU2 +C 6400,0,3000,vss,0,SOUTH,ALU1 +C 6200,31200,8000,vss,5,NORTH,ALU1 +C 11400,0,300,cko,0,SOUTH,ALU1 +S -200,30000,24800,30000,500,vss,RIGHT,CALU2 +S -200,28000,24800,28000,500,vss,RIGHT,CALU2 +S -200,26400,24800,26400,500,vss,LEFT,CALU2 +S -200,24800,24800,24800,500,vss,RIGHT,CALU2 +S -200,22800,24800,22800,500,vss,LEFT,CALU2 +S -200,20800,24800,20800,500,vdd,RIGHT,CALU2 +S -200,18600,24800,18600,500,vdd,LEFT,CALU2 +S -200,17000,24800,17000,500,vdd,RIGHT,CALU2 +S -200,15400,24800,15400,500,vdd,LEFT,CALU2 +S -200,13600,24800,13600,500,vdd,RIGHT,CALU2 +S -200,11200,24800,11200,500,vdd,LEFT,CALU2 +S -200,9600,24800,9600,500,vdd,RIGHT,CALU2 +S -200,8000,24800,8000,500,vdd,LEFT,CALU2 +S -200,5600,24800,5600,500,vdd,RIGHT,CALU2 +S -200,2800,24800,2800,500,vdd,LEFT,CALU2 +S -200,1400,24800,1400,1300,ck,RIGHT,CALU2 +EOF diff --git a/pdks/symbolic/phlib80/cells/pvdd_sp.ap b/pdks/symbolic/phlib80/cells/pvdd_sp.ap new file mode 100644 index 000000000..f05eac2bf --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pvdd_sp.ap @@ -0,0 +1,33 @@ +V ALLIANCE : 6 +H pvdd_sp,P,27/ 9/2019,100 +A 0,0,24600,31200 +C 12300,32400,22000,vdd,0,NORTH,ALU1 +C 6200,31200,8000,vss,4,NORTH,ALU1 +C 12300,0,20000,vss,0,SOUTH,ALU1 +C 0,1400,1200,ck,0,WEST,ALU2 +C 0,11600,18400,vdd,0,WEST,ALU2 +C 0,26400,7600,vss,1,WEST,ALU2 +C 12700,26700,200,vss,3,EAST,ALU2 +C 12700,16200,200,vdd,2,EAST,ALU2 +C 24600,1500,1200,ck,1,EAST,ALU2 +C 24600,11800,18400,vdd,1,EAST,ALU2 +C 24600,26400,7600,vss,2,EAST,ALU2 +S 12200,2700,12200,32200,22000,vss,DOWN,ALU1 +S -200,1400,24800,1400,1300,ck,RIGHT,CALU2 +S -200,2800,24800,2800,500,vdd,LEFT,CALU2 +S -200,5600,24800,5600,500,vdd,RIGHT,CALU2 +S -200,8000,24800,8000,500,vdd,LEFT,CALU2 +S -200,9600,24800,9600,500,vdd,RIGHT,CALU2 +S -200,11200,24800,11200,500,vdd,LEFT,CALU2 +S -200,13600,24800,13600,500,vdd,RIGHT,CALU2 +S -200,15400,24800,15400,500,vdd,LEFT,CALU2 +S -200,17000,24800,17000,500,vdd,RIGHT,CALU2 +S -200,18600,24800,18600,500,vdd,LEFT,CALU2 +S -200,20800,24800,20800,500,vdd,RIGHT,CALU2 +S -200,22800,24800,22800,500,vss,LEFT,CALU2 +S -200,24800,24800,24800,500,vss,RIGHT,CALU2 +S -200,26400,24800,26400,500,vss,LEFT,CALU2 +S -200,28000,24800,28000,500,vss,RIGHT,CALU2 +S -200,30000,24800,30000,500,vss,RIGHT,CALU2 +B 12200,11750,22000,18500,CONT_VIA,vdd +EOF diff --git a/pdks/symbolic/phlib80/cells/pvddck2_sp.ap b/pdks/symbolic/phlib80/cells/pvddck2_sp.ap new file mode 100644 index 000000000..dccb2d1e3 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pvddck2_sp.ap @@ -0,0 +1,32 @@ +V ALLIANCE : 6 +H pvddck2_sp,P,27/ 9/2019,100 +A 0,0,24600,31200 +C 6000,31200,7600,vdd,3,NORTH,ALU1 +C 0,26400,7600,vss,0,WEST,ALU2 +C 0,11800,18400,vdd,1,WEST,ALU2 +C 0,1400,1200,ck,0,WEST,ALU2 +C 6200,0,7600,vdd,0,SOUTH,ALU1 +C 24600,26400,7600,vss,1,EAST,ALU2 +C 24600,11800,18400,vdd,2,EAST,ALU2 +C 24600,1400,1200,ck,1,EAST,ALU2 +C 11400,0,600,cko,0,NORTH,ALU1 +C 11400,0,600,cko,1,NORTH,ALU2 +S -200,30000,24800,30000,500,vss,RIGHT,CALU2 +S -200,28000,24800,28000,500,vss,RIGHT,CALU2 +S -200,26400,24800,26400,500,vss,LEFT,CALU2 +S -200,24800,24800,24800,500,vss,RIGHT,CALU2 +S -200,22800,24800,22800,500,vss,LEFT,CALU2 +S -200,20800,24800,20800,500,vdd,RIGHT,CALU2 +S -200,18600,24800,18600,500,vdd,LEFT,CALU2 +S -200,17000,24800,17000,500,vdd,RIGHT,CALU2 +S -200,15400,24800,15400,500,vdd,LEFT,CALU2 +S -200,13600,24800,13600,500,vdd,RIGHT,CALU2 +S -200,11200,24800,11200,500,vdd,LEFT,CALU2 +S -200,9600,24800,9600,500,vdd,RIGHT,CALU2 +S -200,8000,24800,8000,500,vdd,LEFT,CALU2 +S -200,5600,24800,5600,500,vdd,RIGHT,CALU2 +S -200,2800,24800,2800,500,vdd,LEFT,CALU2 +S -200,1400,24800,1400,1300,ck,RIGHT,CALU2 +I 12300,0,supplyck_buf,buf,NOSYM +I 0,0,vddck_con,con,NOSYM +EOF diff --git a/pdks/symbolic/phlib80/cells/pvddck2_sp.vbe b/pdks/symbolic/phlib80/cells/pvddck2_sp.vbe new file mode 100644 index 000000000..ea0afc33d --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pvddck2_sp.vbe @@ -0,0 +1,42 @@ +-- VHDL data flow description generated from `pvddck2_sp` +-- date : Thu Feb 23 17:11:45 1995 + + +-- Entity Declaration + +ENTITY pvddck2_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_ck : NATURAL := 127; -- cin_ck + CONSTANT tpll_ck : NATURAL := 1055; -- tpll_ck + CONSTANT rdown_ck : NATURAL := 126; -- rdown_ck + CONSTANT tphh_ck : NATURAL := 963; -- tphh_ck + CONSTANT rup_ck : NATURAL := 183 -- rup_ck + ); + PORT ( + cko : out WOR_BIT BUS; -- cko + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + -- vdde : in BIT; -- vdde + -- vddi : in BIT; -- vddi + -- vsse : in BIT; -- vsse + -- vssi : in BIT -- vssi + ); +END pvddck2_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvddck2_sp IS + +BEGIN + ASSERT ((((not (vss) and not (vss)) and vdd) and vdd) = '1') + REPORT "power supply is missing on pvddck2_sp" + SEVERITY WARNING; + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; +END; diff --git a/pdks/symbolic/phlib80/cells/pvss_sp.ap b/pdks/symbolic/phlib80/cells/pvss_sp.ap new file mode 100644 index 000000000..97dd5aee9 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pvss_sp.ap @@ -0,0 +1,32 @@ +V ALLIANCE : 6 +H pvss_sp,P,27/ 9/2019,100 +A 0,0,24600,31200 +C 12300,0,20000,vss,0,SOUTH,ALU1 +C 12300,31200,20000,vss,4,NORTH,ALU1 +C 0,1400,1200,ck,0,WEST,ALU2 +C 0,11600,18400,vdd,0,WEST,ALU2 +C 0,26400,7600,vss,1,WEST,ALU2 +C 12700,26700,200,vss,3,EAST,ALU2 +C 12700,16200,200,vdd,2,EAST,ALU2 +C 24600,1500,1200,ck,1,EAST,ALU2 +C 24600,11800,18400,vdd,1,EAST,ALU2 +C 24600,26400,7600,vss,2,EAST,ALU2 +S -200,1400,24800,1400,1300,ck,RIGHT,CALU2 +S -200,2800,24800,2800,500,vdd,LEFT,CALU2 +S -200,5600,24800,5600,500,vdd,RIGHT,CALU2 +S -200,8000,24800,8000,500,vdd,LEFT,CALU2 +S -200,9600,24800,9600,500,vdd,RIGHT,CALU2 +S -200,11200,24800,11200,500,vdd,LEFT,CALU2 +S -200,13600,24800,13600,500,vdd,RIGHT,CALU2 +S -200,15400,24800,15400,500,vdd,LEFT,CALU2 +S -200,17000,24800,17000,500,vdd,RIGHT,CALU2 +S -200,18600,24800,18600,500,vdd,LEFT,CALU2 +S -200,20800,24800,20800,500,vdd,RIGHT,CALU2 +S -200,22800,24800,22800,500,vss,LEFT,CALU2 +S -200,24800,24800,24800,500,vss,RIGHT,CALU2 +S -200,26400,24800,26400,500,vss,LEFT,CALU2 +S -200,28000,24800,28000,500,vss,RIGHT,CALU2 +S -200,30000,24800,30000,500,vss,RIGHT,CALU2 +S 12200,-700,12200,32200,22000,vss,DOWN,ALU1 +B 12200,26300,22200,7800,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib80/cells/pvssc_sp.ap b/pdks/symbolic/phlib80/cells/pvssc_sp.ap new file mode 100644 index 000000000..68cd7d360 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pvssc_sp.ap @@ -0,0 +1,16 @@ +V ALLIANCE : 6 +H pvssc_sp,P,27/ 9/2019,100 +A 0,0,24600,31200 +C 12300,32400,22000,vss,0,NORTH,ALU1 +C 24600,26400,7600,vss,1,EAST,ALU2 +C 12700,26700,200,vss,2,EAST,ALU2 +C 0,26400,7600,vss,0,WEST,ALU2 +C 12300,31200,20000,vss,3,NORTH,ALU1 +S -200,30000,24800,30000,500,vss,RIGHT,CALU2 +S -200,28000,24800,28000,500,vss,RIGHT,CALU2 +S -200,26400,24800,26400,500,vss,LEFT,CALU2 +S -200,24800,24800,24800,500,vss,RIGHT,CALU2 +S -200,22800,24800,22800,500,vss,LEFT,CALU2 +S 12200,21800,12200,32200,22000,vss,DOWN,ALU1 +B 12200,26300,22200,7800,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib80/cells/pvssck2_sp.ap b/pdks/symbolic/phlib80/cells/pvssck2_sp.ap new file mode 100644 index 000000000..abaae0a6a --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pvssck2_sp.ap @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H pvssck2_sp,P,27/ 9/2019,100 +A 0,0,24600,31200 +C 6000,31200,7600,vss,4,NORTH,ALU1 +C 24600,26400,7600,vss,2,EAST,ALU2 +C 24600,11800,18400,vdd,1,EAST,ALU2 +C 24600,1500,1200,ck,1,EAST,ALU2 +C 12700,16200,200,vdd,2,EAST,ALU2 +C 12700,26700,200,vss,3,EAST,ALU2 +C 0,26400,7600,vss,1,WEST,ALU2 +C 0,11600,18400,vdd,0,WEST,ALU2 +C 0,1400,1200,ck,0,WEST,ALU2 +C 6200,0,7600,vss,0,SOUTH,ALU1 +C 11400,0,300,cko,0,SOUTH,ALU1 +C 11400,0,300,cko,1,SOUTH,ALU2 +S -200,30000,24800,30000,500,vss,RIGHT,CALU2 +S -200,28000,24800,28000,500,vss,RIGHT,CALU2 +S -200,26400,24800,26400,500,vss,LEFT,CALU2 +S -200,24800,24800,24800,500,vss,RIGHT,CALU2 +S -200,22800,24800,22800,500,vss,LEFT,CALU2 +S -200,20800,24800,20800,500,vdd,RIGHT,CALU2 +S -200,18600,24800,18600,500,vdd,LEFT,CALU2 +S -200,17000,24800,17000,500,vdd,RIGHT,CALU2 +S -200,15400,24800,15400,500,vdd,LEFT,CALU2 +S -200,13600,24800,13600,500,vdd,RIGHT,CALU2 +S -200,11200,24800,11200,500,vdd,LEFT,CALU2 +S -200,9600,24800,9600,500,vdd,RIGHT,CALU2 +S -200,8000,24800,8000,500,vdd,LEFT,CALU2 +S -200,5600,24800,5600,500,vdd,RIGHT,CALU2 +S -200,2800,24800,2800,500,vdd,LEFT,CALU2 +S -200,1400,24800,1400,1300,ck,RIGHT,CALU2 +I 12300,0,supplyck_buf,buf,NOSYM +I 0,0,vssck_con,con,NOSYM +EOF diff --git a/pdks/symbolic/phlib80/cells/pvssck2_sp.vbe b/pdks/symbolic/phlib80/cells/pvssck2_sp.vbe new file mode 100644 index 000000000..1aadc0998 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/pvssck2_sp.vbe @@ -0,0 +1,42 @@ +-- VHDL data flow description generated from `pvssck2_sp` +-- date : Thu Feb 23 17:11:45 1995 + + +-- Entity Declaration + +ENTITY pvssck2_sp IS + GENERIC ( + CONSTANT area : NATURAL := 86000; -- area + CONSTANT cin_ck : NATURAL := 127; -- cin_ck + CONSTANT tpll_ck : NATURAL := 1055; -- tpll_ck + CONSTANT rdown_ck : NATURAL := 126; -- rdown_ck + CONSTANT tphh_ck : NATURAL := 963; -- tphh_ck + CONSTANT rup_ck : NATURAL := 183 -- rup_ck + ); + PORT ( + cko : out WOR_BIT BUS; -- cko + ck : in BIT; -- ck + vdd : in BIT; -- vdd + vss : in BIT -- vss + -- vdde : in BIT; -- vdde + -- vddi : in BIT; -- vddi + -- vsse : in BIT; -- vsse + -- vssi : in BIT -- vssi + ); +END pvssck2_sp; + + +-- Architecture Declaration + +ARCHITECTURE behaviour_data_flow OF pvssck2_sp IS + +BEGIN + ASSERT ((((not (vss) and not (vss)) and vdd) and vdd) = '1') + REPORT "power supply is missing on pvssck2_sp" + SEVERITY WARNING; + + label0 : BLOCK ('1' = '1') + BEGIN + cko <= GUARDED ck; + END BLOCK label0; +END; diff --git a/pdks/symbolic/phlib80/cells/supplyck_buf.ap b/pdks/symbolic/phlib80/cells/supplyck_buf.ap new file mode 100644 index 000000000..d30ddd666 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/supplyck_buf.ap @@ -0,0 +1,411 @@ +V ALLIANCE : 6 +H supplyck_buf,P,17/ 8/2019,100 +A 0,0,12300,31200 +C 12300,26400,7600,vss,1,EAST,ALU2 +C 12300,11800,18400,vdd,1,EAST,ALU2 +C 12300,1400,900,ck,1,EAST,ALU2 +C 0,1400,900,ck,0,WEST,ALU2 +C 0,11800,18400,vdd,0,WEST,ALU2 +C 0,26400,7600,vss,0,WEST,ALU2 +S 0,1400,12300,1400,1300,ck,RIGHT,CALU2 +S 0,2800,12300,2800,500,vdd,LEFT,CALU2 +S 0,5600,12300,5600,500,vdd,RIGHT,CALU2 +S 0,8000,12300,8000,500,vdd,LEFT,CALU2 +S 0,9600,12300,9600,500,vdd,RIGHT,CALU2 +S 0,11200,12300,11200,500,vdd,LEFT,CALU2 +S 0,13600,12300,13600,500,vdd,RIGHT,CALU2 +S 0,15400,12300,15400,500,vdd,LEFT,CALU2 +S 0,17000,12300,17000,500,vdd,RIGHT,CALU2 +S 0,18600,12300,18600,500,vdd,LEFT,CALU2 +S 0,20800,12300,20800,500,vdd,RIGHT,CALU2 +S 0,22800,12300,22800,500,vss,LEFT,CALU2 +S 0,24800,12300,24800,500,vss,RIGHT,CALU2 +S 0,26400,12300,26400,500,vss,LEFT,CALU2 +S 0,28000,12300,28000,500,vss,RIGHT,CALU2 +S 0,30000,12300,30000,500,vss,RIGHT,CALU2 +S 6200,1600,6200,21600,12400,*,UP,NWELL +S 6200,21600,6200,31200,12400,*,DOWN,PWELL +S 200,30000,12100,30000,500,*,LEFT,ALU2 +S 200,28000,12100,28000,500,*,RIGHT,ALU2 +S 200,26400,12100,26400,500,*,LEFT,ALU2 +S 200,24800,12100,24800,500,*,RIGHT,ALU2 +S 200,18600,12100,18600,500,*,RIGHT,ALU2 +S 200,17000,12100,17000,500,*,LEFT,ALU2 +S 200,15400,12100,15400,500,*,RIGHT,ALU2 +S 200,13600,12100,13600,500,*,LEFT,ALU2 +S 200,11200,12100,11200,500,*,RIGHT,ALU2 +S 200,9600,12100,9600,500,*,LEFT,ALU2 +S 200,2800,12100,2800,500,*,RIGHT,ALU2 +S 150,1400,12150,1400,1300,*,LEFT,ALU2 +S 150,21800,5950,21800,600,*,LEFT,ALU2 +S 200,20800,12900,20800,500,*,RIGHT,ALU2 +S 200,8000,12900,8000,500,*,RIGHT,ALU2 +S 200,5600,12900,5600,500,*,LEFT,ALU2 +S 1000,20800,2200,20800,400,*,LEFT,ALU1 +S 1000,18600,2200,18600,400,*,LEFT,ALU1 +S 1000,17000,2200,17000,400,*,LEFT,ALU1 +S 1000,15400,2200,15400,400,*,LEFT,ALU1 +S 1000,13600,2200,13600,400,*,LEFT,ALU1 +S 1000,11200,2200,11200,400,*,RIGHT,ALU1 +S 1000,9600,2200,9600,400,*,RIGHT,ALU1 +S 1000,8000,2200,8000,400,*,RIGHT,ALU1 +S 1000,5600,2200,5600,400,*,LEFT,ALU1 +S 9400,5600,10600,5600,400,*,RIGHT,ALU1 +S 9400,8000,10600,8000,400,*,LEFT,ALU1 +S 9400,9600,10600,9600,400,*,LEFT,ALU1 +S 9400,11200,10600,11200,400,*,LEFT,ALU1 +S 9400,13600,10600,13600,400,*,RIGHT,ALU1 +S 9400,17000,10600,17000,400,*,RIGHT,ALU1 +S 9400,18600,10600,18600,400,*,RIGHT,ALU1 +S 9400,20800,10600,20800,400,*,RIGHT,ALU1 +S 1000,24800,2200,24800,400,*,RIGHT,ALU1 +S 1000,26400,2200,26400,400,*,RIGHT,ALU1 +S 1000,28000,2200,28000,400,*,RIGHT,ALU1 +S 9400,28000,10600,28000,400,*,LEFT,ALU1 +S 9400,26400,10600,26400,400,*,LEFT,ALU1 +S 9400,24800,10600,24800,400,*,LEFT,ALU1 +S 11700,1400,11700,29000,400,*,DOWN,ALU1 +S 2800,4000,7200,4000,200,*,RIGHT,POLY +S 1000,22900,1000,28700,400,*,UP,ALU1 +S 2200,22900,2200,28700,400,*,UP,ALU1 +S 4600,22900,4600,29900,400,*,UP,ALU1 +S 7000,4900,7000,14300,400,*,DOWN,ALU1 +S 7000,16300,7000,20700,400,*,UP,ALU1 +S 8800,4100,8800,14900,200,*,UP,PTRANS +S 9400,4300,9400,14700,600,*,DOWN,PDIF +S 8200,4300,8200,14700,600,*,UP,PDIF +S 1000,2500,1000,20900,600,*,UP,NTIE +S 2200,16100,2200,19500,600,*,UP,PDIF +S 700,2800,10900,2800,600,*,LEFT,NTIE +S 2800,15900,2800,19700,200,*,UP,PTRANS +S 4000,15900,4000,19700,200,*,UP,PTRANS +S 5200,15900,5200,19700,200,*,UP,PTRANS +S 7000,16100,7000,19500,600,*,UP,PDIF +S 6400,15900,6400,19700,200,*,UP,PTRANS +S 9400,16100,9400,19500,600,*,UP,PDIF +S 8200,16100,8200,19500,600,*,UP,PDIF +S 8800,15900,8800,19700,200,*,UP,PTRANS +S 10600,2500,10600,20900,600,*,UP,NTIE +S 10600,2900,10600,14300,400,*,DOWN,ALU1 +S 8800,15200,8800,15600,200,*,UP,POLY +S 9300,15400,11500,15400,400,*,RIGHT,ALU1 +S 8800,15400,9200,15400,600,*,RIGHT,POLY +S 6400,15000,6400,15800,200,*,UP,POLY +S 5200,15000,5200,15800,200,*,UP,POLY +S 4000,15000,4000,15800,200,*,UP,POLY +S 2800,15000,2800,15800,200,*,UP,POLY +S 6400,10100,6400,14900,200,*,UP,PTRANS +S 7000,10300,7000,14700,600,*,UP,PDIF +S 5200,10100,5200,14900,200,*,DOWN,PTRANS +S 4000,10100,4000,14900,200,*,UP,PTRANS +S 2800,10100,2800,14900,200,*,UP,PTRANS +S 2200,10300,2200,14700,600,*,UP,PDIF +S 7100,15400,8100,15400,400,*,LEFT,ALU1 +S 1100,2800,10500,2800,400,*,LEFT,ALU1 +S 9400,2900,9400,14300,400,*,UP,ALU1 +S 700,30000,10900,30000,600,*,LEFT,PTIE +S 700,22800,10900,22800,600,*,LEFT,PTIE +S 1000,22500,1000,30300,600,*,DOWN,PTIE +S 10600,22500,10600,30300,600,*,DOWN,PTIE +S 6400,4300,6400,9100,200,*,UP,PTRANS +S 5200,4300,5200,9100,200,*,UP,PTRANS +S 4000,4300,4000,9100,200,*,UP,PTRANS +S 2800,4300,2800,9100,200,*,UP,PTRANS +S 2200,4500,2200,8900,600,*,UP,PDIF +S 7000,4500,7000,8900,600,*,UP,PDIF +S 7100,3800,8100,3800,400,*,LEFT,ALU1 +S 8800,23700,8800,28500,200,*,UP,NTRANS +S 8200,23900,8200,28300,600,*,UP,NDIF +S 9400,23900,9400,28300,600,*,UP,NDIF +S 6400,23700,6400,28500,200,*,UP,NTRANS +S 5200,23700,5200,28500,200,*,UP,NTRANS +S 4000,23700,4000,28500,200,*,UP,NTRANS +S 2800,23700,2800,28500,200,*,UP,NTRANS +S 2200,23900,2200,28300,600,*,UP,NDIF +S 7000,23900,7000,28300,600,*,UP,NDIF +S 2800,28800,7000,28800,200,*,LEFT,POLY +S 7100,29000,8100,29000,400,*,LEFT,ALU1 +S 10600,22900,10600,27900,400,*,UP,ALU1 +S 9400,22900,9400,27900,400,*,UP,ALU1 +S 7000,22900,7000,27900,400,*,UP,ALU1 +S 9500,22800,10500,22800,400,*,LEFT,ALU1 +S 9300,29000,11500,29000,400,*,LEFT,ALU1 +S 8800,29000,9200,29000,600,*,RIGHT,POLY +S 8800,28800,8800,29200,200,*,DOWN,POLY +S 700,20800,10900,20800,600,*,LEFT,NTIE +S 2200,2900,2200,20700,400,*,UP,ALU1 +S 1100,20800,2100,20800,400,*,RIGHT,ALU1 +S 1000,2900,1000,20700,400,*,UP,ALU1 +S 4600,2900,4600,20700,400,*,UP,ALU1 +S 9400,16500,9400,20700,400,*,UP,ALU1 +S 10600,16500,10600,20700,400,*,DOWN,ALU1 +S 9500,20800,10500,20800,400,*,LEFT,ALU1 +S 7100,30000,10500,30000,400,*,LEFT,ALU1 +S 2800,15400,6400,15400,200,*,RIGHT,POLY +S 6400,15400,7000,15400,600,*,RIGHT,POLY +S 5800,4900,5800,28100,400,*,UP,ALU1 +S 3400,4900,3400,28100,400,*,UP,ALU1 +S 8200,3800,8200,28900,400,*,DOWN,ALU1 +S 900,22800,10700,22800,500,*,LEFT,ALU2 +S 5900,23900,5900,28300,600,*,UP,NDIF +S 4700,23900,4700,28300,600,*,UP,NDIF +S 3500,23900,3500,28300,600,*,UP,NDIF +S 5900,16100,5900,19500,600,*,UP,PDIF +S 4500,16100,4500,19500,600,*,UP,PDIF +S 3400,16100,3400,19500,600,*,UP,PDIF +S 5800,10300,5800,14700,600,*,UP,PDIF +S 4600,10300,4600,14700,600,*,UP,PDIF +S 3400,10300,3400,14700,600,*,UP,PDIF +S 5800,4500,5800,8900,600,*,UP,PDIF +S 4500,4500,4500,8900,600,*,UP,PDIF +S 3400,4500,3400,8900,600,*,UP,PDIF +V 1000,16200,CONT_BODY_N,* +V 1000,17800,CONT_BODY_N,* +V 1000,19400,CONT_BODY_N,* +V 11700,1400,CONT_VIA,* +V 1000,9600,CONT_VIA,* +V 10600,2800,CONT_BODY_N,* +V 9400,19400,CONT_DIF_P,* +V 8200,19400,CONT_DIF_P,* +V 9200,15400,CONT_POLY,* +V 7000,15400,CONT_POLY,* +V 10600,22800,CONT_BODY_P,* +V 7000,3800,CONT_POLY,* +V 7000,29000,CONT_POLY,* +V 9400,22800,CONT_VIA,* +V 9200,29000,CONT_POLY,* +V 9400,14400,CONT_DIF_P,* +V 8200,14400,CONT_DIF_P,* +V 7000,4800,CONT_DIF_P,* +V 5800,4800,CONT_DIF_P,* +V 4600,4800,CONT_DIF_P,* +V 3400,4800,CONT_DIF_P,* +V 2200,4800,CONT_DIF_P,* +V 7000,19400,CONT_DIF_P,* +V 5800,19400,CONT_DIF_P,* +V 4600,19400,CONT_DIF_P,* +V 3400,19400,CONT_DIF_P,* +V 2200,19400,CONT_DIF_P,* +V 7000,17800,CONT_DIF_P,* +V 7000,16200,CONT_DIF_P,* +V 7000,18600,CONT_VIA,* +V 7000,17000,CONT_VIA,* +V 7000,20800,CONT_BODY_N,* +V 4600,20800,CONT_BODY_N,* +V 2200,20800,CONT_BODY_N,* +V 1000,20800,CONT_BODY_N,* +V 9400,20800,CONT_BODY_N,* +V 10600,20800,CONT_BODY_N,* +V 9400,2800,CONT_BODY_N,* +V 1000,2800,CONT_BODY_N,* +V 2200,2800,CONT_BODY_N,* +V 3400,2800,CONT_BODY_N,* +V 4600,2800,CONT_BODY_N,* +V 5800,2800,CONT_BODY_N,* +V 7000,2800,CONT_BODY_N,* +V 8200,2800,CONT_BODY_N,* +V 4600,17000,CONT_VIA,* +V 4600,18600,CONT_VIA,* +V 2200,18600,CONT_VIA,* +V 2200,17000,CONT_VIA,* +V 9400,18600,CONT_VIA,* +V 9400,17000,CONT_VIA,* +V 9400,17800,CONT_DIF_P,* +V 8200,17800,CONT_DIF_P,* +V 8200,16200,CONT_DIF_P,* +V 8200,17000,CONT_DIF_P,* +V 8200,18600,CONT_DIF_P,* +V 5800,18600,CONT_DIF_P,* +V 3400,18600,CONT_DIF_P,* +V 3400,17000,CONT_DIF_P,* +V 5800,17000,CONT_DIF_P,* +V 10600,19400,CONT_BODY_N,* +V 10600,17800,CONT_BODY_N,* +V 10600,18600,CONT_VIA,* +V 1000,18600,CONT_VIA,* +V 1000,17000,CONT_VIA,* +V 10600,17000,CONT_VIA,* +V 5800,17800,CONT_DIF_P,* +V 4600,17800,CONT_DIF_P,* +V 3400,17800,CONT_DIF_P,* +V 2200,17800,CONT_DIF_P,* +V 5800,16200,CONT_DIF_P,* +V 4600,16200,CONT_DIF_P,* +V 3400,16200,CONT_DIF_P,* +V 2200,16200,CONT_DIF_P,* +V 7000,6400,CONT_DIF_P,* +V 7000,7200,CONT_DIF_P,* +V 7000,8800,CONT_DIF_P,* +V 7000,9600,CONT_VIA,* +V 4600,9600,CONT_VIA,* +V 7000,8000,CONT_VIA,* +V 7000,5600,CONT_VIA,* +V 4600,8000,CONT_VIA,* +V 4600,5600,CONT_VIA,* +V 2200,5600,CONT_VIA,* +V 2200,8000,CONT_VIA,* +V 2200,9600,CONT_VIA,* +V 7000,10400,CONT_DIF_P,* +V 7000,12000,CONT_DIF_P,* +V 7000,12800,CONT_DIF_P,* +V 7000,14400,CONT_DIF_P,* +V 5800,10400,CONT_DIF_P,* +V 4600,10400,CONT_DIF_P,* +V 3400,10400,CONT_DIF_P,* +V 2200,10400,CONT_DIF_P,* +V 5800,11200,CONT_DIF_P,* +V 5800,12000,CONT_DIF_P,* +V 5800,12800,CONT_DIF_P,* +V 5800,13600,CONT_DIF_P,* +V 5800,14400,CONT_DIF_P,* +V 4600,12000,CONT_DIF_P,* +V 4600,12800,CONT_DIF_P,* +V 4600,14400,CONT_DIF_P,* +V 3400,11200,CONT_DIF_P,* +V 3400,12000,CONT_DIF_P,* +V 3400,12800,CONT_DIF_P,* +V 3400,13600,CONT_DIF_P,* +V 3400,14400,CONT_DIF_P,* +V 2200,12000,CONT_DIF_P,* +V 2200,12800,CONT_DIF_P,* +V 2200,14400,CONT_DIF_P,* +V 4600,8800,CONT_DIF_P,* +V 5800,8800,CONT_DIF_P,* +V 5800,8000,CONT_DIF_P,* +V 5800,7200,CONT_DIF_P,* +V 5800,6400,CONT_DIF_P,* +V 5800,5600,CONT_DIF_P,* +V 4600,6400,CONT_DIF_P,* +V 4600,7200,CONT_DIF_P,* +V 3400,8800,CONT_DIF_P,* +V 3400,8000,CONT_DIF_P,* +V 3400,7200,CONT_DIF_P,* +V 3400,6400,CONT_DIF_P,* +V 3400,5600,CONT_DIF_P,* +V 2200,6400,CONT_DIF_P,* +V 2200,7200,CONT_DIF_P,* +V 2200,8800,CONT_DIF_P,* +V 8200,4800,CONT_DIF_P,* +V 8200,5600,CONT_DIF_P,* +V 8200,6400,CONT_DIF_P,* +V 8200,7200,CONT_DIF_P,* +V 8200,8000,CONT_DIF_P,* +V 8200,8800,CONT_DIF_P,* +V 8200,9600,CONT_DIF_P,* +V 8200,10400,CONT_DIF_P,* +V 8200,11200,CONT_DIF_P,* +V 8200,12000,CONT_DIF_P,* +V 8200,12800,CONT_DIF_P,* +V 8200,13600,CONT_DIF_P,* +V 9400,12800,CONT_DIF_P,* +V 9400,12000,CONT_DIF_P,* +V 9400,10400,CONT_DIF_P,* +V 9400,8800,CONT_DIF_P,* +V 9400,7200,CONT_DIF_P,* +V 9400,6400,CONT_DIF_P,* +V 9400,4800,CONT_DIF_P,* +V 10600,14400,CONT_BODY_N,* +V 10600,12800,CONT_BODY_N,* +V 10600,12000,CONT_BODY_N,* +V 10600,10400,CONT_BODY_N,* +V 10600,8800,CONT_BODY_N,* +V 10600,7200,CONT_BODY_N,* +V 10600,6400,CONT_BODY_N,* +V 10600,4800,CONT_BODY_N,* +V 1000,4800,CONT_BODY_N,* +V 1000,6400,CONT_BODY_N,* +V 1000,7200,CONT_BODY_N,* +V 1000,8800,CONT_BODY_N,* +V 1000,10400,CONT_BODY_N,* +V 1000,12000,CONT_BODY_N,* +V 1000,12800,CONT_BODY_N,* +V 1000,14400,CONT_BODY_N,* +V 10600,9600,CONT_VIA,* +V 9400,9600,CONT_VIA,* +V 10600,11200,CONT_VIA,* +V 9400,11200,CONT_VIA,* +V 10600,13600,CONT_VIA,* +V 9400,13600,CONT_VIA,* +V 7000,13600,CONT_VIA,* +V 7000,11200,CONT_VIA,* +V 4600,11200,CONT_VIA,* +V 4600,13600,CONT_VIA,* +V 2200,13600,CONT_VIA,* +V 1000,13600,CONT_VIA,* +V 1000,11200,CONT_VIA,* +V 2200,11200,CONT_VIA,* +V 1000,8000,CONT_VIA,* +V 1000,5600,CONT_VIA,* +V 9400,5600,CONT_VIA,* +V 10600,5600,CONT_VIA,* +V 9400,8000,CONT_VIA,* +V 10600,8000,CONT_VIA,* +V 1000,15400,CONT_VIA,* +V 2200,15400,CONT_VIA,* +V 9400,27200,CONT_DIF_N,* +V 9400,25600,CONT_DIF_N,* +V 9400,24000,CONT_DIF_N,* +V 8200,24000,CONT_DIF_N,* +V 8200,24800,CONT_DIF_N,* +V 8200,25600,CONT_DIF_N,* +V 8200,26400,CONT_DIF_N,* +V 8200,27200,CONT_DIF_N,* +V 8200,28000,CONT_DIF_N,* +V 7000,27200,CONT_DIF_N,* +V 7000,25600,CONT_DIF_N,* +V 7000,24000,CONT_DIF_N,* +V 5800,24000,CONT_DIF_N,* +V 5800,24800,CONT_DIF_N,* +V 5800,25600,CONT_DIF_N,* +V 5800,26400,CONT_DIF_N,* +V 5800,27200,CONT_DIF_N,* +V 5800,28000,CONT_DIF_N,* +V 4600,27200,CONT_DIF_N,* +V 4600,25600,CONT_DIF_N,* +V 4600,24000,CONT_DIF_N,* +V 3400,24000,CONT_DIF_N,* +V 3400,24800,CONT_DIF_N,* +V 3400,25600,CONT_DIF_N,* +V 3400,26400,CONT_DIF_N,* +V 3400,27200,CONT_DIF_N,* +V 3400,28000,CONT_DIF_N,* +V 2200,27200,CONT_DIF_N,* +V 2200,25600,CONT_DIF_N,* +V 2200,24000,CONT_DIF_N,* +V 10600,27200,CONT_BODY_P,* +V 10600,25600,CONT_BODY_P,* +V 10600,24000,CONT_BODY_P,* +V 1000,24000,CONT_BODY_P,* +V 1000,25600,CONT_BODY_P,* +V 1000,27200,CONT_BODY_P,* +V 1000,28800,CONT_BODY_P,* +V 1000,22800,CONT_BODY_P,* +V 2200,22800,CONT_BODY_P,* +V 4600,22800,CONT_BODY_P,* +V 7000,22800,CONT_BODY_P,* +V 4600,30000,CONT_BODY_P,* +V 10600,30000,CONT_BODY_P,* +V 7000,30000,CONT_BODY_P,* +V 9400,30000,CONT_VIA,* +V 8200,30000,CONT_VIA,* +V 10600,24800,CONT_VIA,* +V 9400,24800,CONT_VIA,* +V 9400,26400,CONT_VIA,* +V 10600,26400,CONT_VIA,* +V 10600,28000,CONT_VIA,* +V 9400,28000,CONT_VIA,* +V 7000,24800,CONT_VIA,* +V 7000,26400,CONT_VIA,* +V 7000,28000,CONT_VIA,* +V 4600,28000,CONT_VIA,* +V 4600,26400,CONT_VIA,* +V 4600,24800,CONT_VIA,* +V 2200,24800,CONT_VIA,* +V 1000,24800,CONT_VIA,* +V 1000,26400,CONT_VIA,* +V 2200,26400,CONT_VIA,* +V 2200,28000,CONT_VIA,* +V 1000,28000,CONT_VIA,* +V 5800,21800,CONT_VIA,* +V 3400,21800,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib80/cells/vddck_con.ap b/pdks/symbolic/phlib80/cells/vddck_con.ap new file mode 100644 index 000000000..b20c3b074 --- /dev/null +++ b/pdks/symbolic/phlib80/cells/vddck_con.ap @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H vddck_con,P,17/ 8/2019,100 +A 0,0,12300,31200 +C 12300,26400,7600,vss,2,EAST,ALU2 +C 12300,11700,18400,vdd,1,EAST,ALU2 +C 12300,1400,900,ck,2,EAST,ALU2 +C 0,1400,900,ck,1,WEST,ALU2 +C 0,11800,18400,vdd,4,WEST,ALU2 +C 0,26400,7600,vss,1,WEST,ALU2 +C 5400,31200,6000,pad,0,NORTH,ALU1 +C 11400,0,300,cko,1,NORTH,ALU2 +C 11400,0,300,cko,0,SOUTH,ALU1 +C 6000,0,3000,vdd,0,SOUTH,ALU1 +S -200,1400,12500,1400,1300,ck,RIGHT,CALU2 +S -200,26400,12500,26400,7600,vss,RIGHT,CALU2 +S -200,11800,12500,11800,18400,vdd,RIGHT,CALU2 +S 11250,21800,12500,21800,600,*,LEFT,ALU2 +S 200,26400,12100,26400,7600,*,RIGHT,ALU2 +S 10000,11700,12100,11700,18400,*,RIGHT,ALU2 +S 200,1400,12100,1400,1300,*,RIGHT,ALU2 +S 200,11800,1900,11800,18400,*,LEFT,ALU2 +S 2200,8600,9800,8600,12000,*,RIGHT,ALU1 +S 6000,-100,6000,2500,8000,*,DOWN,ALU1 +S 11400,-200,11400,21900,500,*,DOWN,ALU1 +S 6000,2650,6000,14550,8000,*,UP,ALU2 +S 6000,2650,6000,20850,8000,*,UP,ALU2 +S 6000,14800,6000,31000,8000,*,DOWN,ALU1 +B 6000,11800,7800,18200,CONT_VIA,* +V 11400,21800,CONT_VIA,* +V 11400,0,CONT_VIA,* +EOF diff --git a/pdks/symbolic/phlib80/cells/vssck_con.ap b/pdks/symbolic/phlib80/cells/vssck_con.ap new file mode 100644 index 000000000..582f07a1a --- /dev/null +++ b/pdks/symbolic/phlib80/cells/vssck_con.ap @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H vssck_con,P,17/ 8/2019,100 +A 0,0,12300,31200 +C 12300,1400,900,ck,2,EAST,ALU2 +C 12300,11600,18000,vdd,2,EAST,ALU2 +C 12300,26400,7600,vss,3,EAST,ALU2 +C 0,26400,7600,vss,2,WEST,ALU2 +C 0,11600,18000,vdd,1,WEST,ALU2 +C 0,1400,900,ck,1,WEST,ALU2 +C 11400,0,300,cko,0,SOUTH,ALU1 +C 11400,0,300,cko,1,NORTH,ALU2 +C 6000,0,3000,vss,0,SOUTH,ALU1 +C 6000,31200,6000,pad,1,NORTH,ALU2 +C 6000,31200,6000,pad,0,NORTH,ALU1 +S -200,1400,12500,1400,1300,ck,RIGHT,CALU2 +S -200,26400,12500,26400,7600,vss,RIGHT,CALU2 +S -200,11800,12500,11800,18400,vdd,RIGHT,CALU2 +S 200,1400,12100,1400,1300,*,RIGHT,ALU2 +S 11250,21800,12150,21800,600,*,LEFT,ALU2 +S 200,11800,12100,11800,18400,*,RIGHT,ALU2 +S 200,26400,12100,26400,7600,*,RIGHT,ALU2 +S 6000,-100,6000,31100,8000,*,DOWN,ALU1 +S 6000,22950,6000,31050,8000,*,UP,ALU2 +S 11400,-100,11400,21800,500,*,UP,ALU1 +V 11400,21800,CONT_VIA,* +V 11400,0,CONT_VIA,* +B 6050,26400,8100,7600,CONT_VIA,* +EOF diff --git a/pdks/symbolic/pyproject.toml b/pdks/symbolic/pyproject.toml new file mode 100644 index 000000000..cb1f14346 --- /dev/null +++ b/pdks/symbolic/pyproject.toml @@ -0,0 +1,25 @@ +[project] +name = "pdk_symbolic_cells" +version = "0.1.0" +description = "Collection of symbolic cells for Coriolis EDA PDKs." +authors = [ { name = "Coriolis EDA Contributers" } ] +requires-python = ">= 3.8" + +[build-system] +requires = [ + "meson", + "meson-python", + "ninja", + "setuptools", + "cibuildwheel", + "build", + "pdm-backend" +] +build-backend = "mesonpy" + +[tool.meson] +build-dir = "build" + +[tool.cibuildwheel] +build = "cp310-*" +skip = ["cp36-*", "cp37-*", "pp*"] diff --git a/pdks/symbolic/sxlib/cells/CATAL b/pdks/symbolic/sxlib/cells/CATAL new file mode 100644 index 000000000..8b40a9293 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/CATAL @@ -0,0 +1,98 @@ +a2_x2 C +a2_x4 C +a3_x2 C +a3_x4 C +a4_x2 C +a4_x4 C +an12_x1 C +an12_x4 C +ao22_x2 C +ao22_x4 C +ao2o22_x2 C +ao2o22_x4 C +buf_x2 C +buf_x4 C +buf_x8 C +fulladder_x2 C +fulladder_x4 C +halfadder_x2 C +halfadder_x4 C +inv_x1 C +inv_x2 C +inv_x4 C +inv_x8 C +mx2_x2 C +mx2_x4 C +mx3_x2 C +mx3_x4 C +na2_x1 C +na2_x4 C +na3_x1 C +na3_x4 C +na4_x1 C +na4_x4 C +nao22_x1 C +nao22_x4 C +nao2o22_x1 C +nao2o22_x4 C +nmx2_x1 C +nmx2_x4 C +nmx3_x1 C +nmx3_x4 C +no2_x1 C +no2_x4 C +no3_x1 C +no3_x4 C +no4_x1 C +no4_x4 C +noa22_x1 C +noa22_x4 C +noa2a22_x1 C +noa2a22_x4 C +noa2a2a23_x1 C +noa2a2a23_x4 C +noa2a2a2a24_x1 C +noa2a2a2a24_x4 C +noa2ao222_x1 C +noa2ao222_x4 C +noa3ao322_x1 C +noa3ao322_x4 C +nts_x1 C +nts_x2 C +nxr2_x1 C +nxr2_x4 C +o2_x2 C +o2_x4 C +o3_x2 C +o3_x4 C +o4_x2 C +o4_x4 C +oa22_x2 C +oa22_x4 C +oa2a22_x2 C +oa2a22_x4 C +oa2a2a23_x2 C +oa2a2a23_x4 C +oa2a2a2a24_x2 C +oa2a2a2a24_x4 C +oa2ao222_x2 C +oa2ao222_x4 C +oa3ao322_x2 C +oa3ao322_x4 C +on12_x1 C +on12_x4 C +one_x0 C +powmid_x0 C +powmid_x0 F +rowend_x0 C +rowend_x0 F +sff1_x4 C +sff2_x4 C +sff3_x4 C +tie_x0 C +tie_x0 F +ts_x4 C +ts_x8 C +xr2_x1 C +xr2_x4 C +zero_x0 C diff --git a/pdks/symbolic/sxlib/cells/a2_x2.al b/pdks/symbolic/sxlib/cells/a2_x2.al new file mode 100644 index 000000000..561353695 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a2_x2.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H a2_x2,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,1,2,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,2.9,5,6,2,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00005 +T P,0.35,2.9,2,7,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00004 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00003 +T N,0.35,2.9,4,2,1,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00002 +T N,0.35,2.9,3,6,4,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00001 +S 7,EXTERNAL,i0 +Q 0.00214738 +S 6,EXTERNAL,i1 +Q 0.00400776 +S 5,EXTERNAL,vdd +Q 0.00374949 +S 4,EXTERNAL,vss +Q 0.00298567 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00463918 +S 1,EXTERNAL,q +Q 0.00258522 +EOF diff --git a/pdks/symbolic/sxlib/cells/a2_x2.ap b/pdks/symbolic/sxlib/cells/a2_x2.ap new file mode 100644 index 000000000..786d041a2 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a2_x2.ap @@ -0,0 +1,71 @@ +V ALLIANCE : 6 +H a2_x2,P,18/ 5/2002,100 +A 0,0,2500,5000 +R 1500,4000,ref_ref,i1_40 +R 1500,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i1_25 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 1500,1000,ref_ref,i1_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 2000,2500,ref_ref,q_25 +R 2000,3000,ref_ref,q_30 +R 2000,3500,ref_ref,q_35 +R 2000,4000,ref_ref,q_40 +R 2000,1000,ref_ref,q_10 +R 2000,1500,ref_ref,q_15 +R 2000,2000,ref_ref,q_20 +S 1500,1000,1500,4000,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 2000,1000,2000,4000,200,q,DOWN,CALU1 +S 900,300,900,1700,300,*,UP,NDIF +S 300,800,300,1700,300,*,UP,NDIF +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1000,2000,1800,2000,100,*,RIGHT,POLY +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,ALU1 +S 0,300,2500,300,600,vss,RIGHT,ALU1 +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 1800,1400,1800,2600,100,*,UP,POLY +S 1500,1000,1500,4000,100,*,DOWN,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1200,2400,1200,3100,100,*,DOWN,POLY +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 950,1000,950,4000,100,*,DOWN,ALU1 +S 300,1000,950,1000,100,*,RIGHT,ALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +S 2000,1000,2000,4000,200,*,DOWN,ALU1 +V 500,2000,CONT_POLY,* +V 1400,2500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 300,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 1400,1500,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 500,3000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/a2_x2.sym b/pdks/symbolic/sxlib/cells/a2_x2.sym new file mode 100644 index 000000000..4ef52f4a5 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/a2_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/a2_x2.vbe b/pdks/symbolic/sxlib/cells/a2_x2.vbe new file mode 100644 index 000000000..8e6db7cd8 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i1_q : NATURAL := 203; + CONSTANT tphh_i0_q : NATURAL := 261; + CONSTANT tpll_i0_q : NATURAL := 388; + CONSTANT tpll_i1_q : NATURAL := 434; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x2; + +ARCHITECTURE behaviour_data_flow OF a2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x2" + SEVERITY WARNING; + q <= (i0 and i1) after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/a2_x2.vhd b/pdks/symbolic/sxlib/cells/a2_x2.vhd new file mode 100644 index 000000000..9c04bc77f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a2_x2.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a2_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a2_x2; + +ARCHITECTURE RTL OF a2_x2 IS +BEGIN + q <= (i0 AND i1); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/a2_x4.al b/pdks/symbolic/sxlib/cells/a2_x4.al new file mode 100644 index 000000000..70f58873c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a2_x4.al @@ -0,0 +1,30 @@ +V ALLIANCE : 6 +H a2_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,4,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00008 +T P,0.35,5.9,5,4,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00007 +T P,0.35,2.9,5,6,4,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00006 +T P,0.35,2.9,4,7,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00005 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00004 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,3,6,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 7,EXTERNAL,i0 +Q 0.00214738 +S 6,EXTERNAL,i1 +Q 0.00400776 +S 5,EXTERNAL,vdd +Q 0.00579486 +S 4,INTERNAL +Q 0.00596944 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,q +Q 0.00258522 +S 1,EXTERNAL,vss +Q 0.00450225 +EOF diff --git a/pdks/symbolic/sxlib/cells/a2_x4.ap b/pdks/symbolic/sxlib/cells/a2_x4.ap new file mode 100644 index 000000000..88a4e3b04 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a2_x4.ap @@ -0,0 +1,82 @@ +V ALLIANCE : 6 +H a2_x4,P,18/ 5/2002,100 +A 0,0,3000,5000 +R 2000,2000,ref_ref,q_20 +R 2000,1500,ref_ref,q_15 +R 2000,1000,ref_ref,q_10 +R 2000,4000,ref_ref,q_40 +R 2000,3500,ref_ref,q_35 +R 2000,3000,ref_ref,q_30 +R 2000,2500,ref_ref,q_25 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 1500,1000,ref_ref,i1_10 +R 1500,1500,ref_ref,i1_15 +R 1500,2000,ref_ref,i1_20 +R 1500,2500,ref_ref,i1_25 +R 1500,3000,ref_ref,i1_30 +R 1500,3500,ref_ref,i1_35 +R 1500,4000,ref_ref,i1_40 +S 2700,500,2700,1000,200,*,DOWN,ALU1 +S 2000,1000,2000,4000,200,*,DOWN,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1200,2400,1200,3100,100,*,DOWN,POLY +S 600,100,600,1400,100,*,DOWN,NTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,1000,1500,4000,100,*,DOWN,ALU1 +S 1000,2000,2400,2000,100,*,RIGHT,POLY +S 1800,1400,1800,2600,100,*,UP,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 2700,3000,2700,4500,200,*,DOWN,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 950,1000,950,4000,100,*,DOWN,ALU1 +S 300,1000,950,1000,100,*,RIGHT,ALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +S 2000,1000,2000,4000,200,q,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1500,1000,1500,4000,200,i1,DOWN,CALU1 +V 500,3000,CONT_POLY,* +V 2700,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1400,1500,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 2100,1000,CONT_DIF_N,* +V 2100,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1000,2000,CONT_POLY,* +V 1400,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/a2_x4.sym b/pdks/symbolic/sxlib/cells/a2_x4.sym new file mode 100644 index 000000000..db1efc873 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/a2_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/a2_x4.vbe b/pdks/symbolic/sxlib/cells/a2_x4.vbe new file mode 100644 index 000000000..f6955d6e9 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY a2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphh_i0_q : NATURAL := 338; + CONSTANT tpll_i0_q : NATURAL := 476; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x4; + +ARCHITECTURE behaviour_data_flow OF a2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a2_x4" + SEVERITY WARNING; + q <= (i0 and i1) after 1100 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/a2_x4.vhd b/pdks/symbolic/sxlib/cells/a2_x4.vhd new file mode 100644 index 000000000..577cea82a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a2_x4; + +ARCHITECTURE RTL OF a2_x4 IS +BEGIN + q <= (i0 AND i1); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/a3_x2.al b/pdks/symbolic/sxlib/cells/a3_x2.al new file mode 100644 index 000000000..87820e7b2 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a3_x2.al @@ -0,0 +1,35 @@ +V ALLIANCE : 6 +H a3_x2,L,30/10/99 +C i0,IN,EXTERNAL,9 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,5 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,4 +T P,0.35,2.9,3,8,6,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,2.9,6,9,3,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T P,0.35,5.9,5,3,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00006 +T P,0.35,2.9,6,7,3,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00005 +T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00004 +T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,3,3.75,tr_00003 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,4.2,3.75,tr_00002 +T N,0.35,2.9,4,3,5,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00001 +S 9,EXTERNAL,i0 +Q 0.00260759 +S 8,EXTERNAL,i1 +Q 0.00282737 +S 7,EXTERNAL,i2 +Q 0.00304715 +S 6,EXTERNAL,vdd +Q 0.00350341 +S 5,EXTERNAL,q +Q 0.00364281 +S 4,EXTERNAL,vss +Q 0.00332715 +S 3,INTERNAL +Q 0.00629467 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/a3_x2.ap b/pdks/symbolic/sxlib/cells/a3_x2.ap new file mode 100644 index 000000000..ba4d77660 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a3_x2.ap @@ -0,0 +1,88 @@ +V ALLIANCE : 6 +H a3_x2,P,18/ 5/2002,100 +A 0,0,3000,5000 +R 2500,1000,ref_ref,q_10 +R 2500,1500,ref_ref,q_15 +R 2500,4000,ref_ref,q_40 +R 2500,3500,ref_ref,q_35 +R 2500,3000,ref_ref,q_30 +R 2500,2500,ref_ref,q_25 +R 2500,2000,ref_ref,q_20 +R 1500,3500,ref_ref,i2_35 +R 1500,3000,ref_ref,i2_30 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 1000,1500,ref_ref,i1_15 +R 500,1500,ref_ref,i0_15 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1500,2500,ref_ref,i2_25 +S 1700,300,1700,1700,300,*,UP,NDIF +S 2000,300,2000,1200,400,*,UP,NDIF +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1500,1500,1500,3500,200,i2,DOWN,CALU1 +S 2450,1000,2700,1000,200,*,LEFT,ALU1 +S 2450,4000,2700,4000,200,*,LEFT,ALU1 +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2400,1400,2400,2600,100,*,UP,POLY +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2100,2800,2100,4700,300,*,UP,PDIF +S 300,4000,2000,4000,100,*,RIGHT,ALU1 +S 1000,1500,1000,3500,100,*,DOWN,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 1000,3100,1200,3100,100,*,LEFT,POLY +S 600,1900,600,3100,100,*,UP,POLY +S 1000,1900,1000,3100,100,*,UP,POLY +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 600,600,600,1900,100,*,DOWN,NTRANS +S 300,800,300,1700,300,*,UP,NDIF +S 300,1000,2000,1000,100,*,RIGHT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,DOWN,ALU1 +S 1400,2600,1800,2600,100,*,RIGHT,POLY +S 1400,1900,1400,2600,100,*,UP,POLY +S 1800,2600,1800,3100,100,*,UP,POLY +S 2500,3500,2700,3500,200,*,LEFT,ALU1 +S 2500,3000,2700,3000,200,*,LEFT,ALU1 +S 300,300,1100,300,300,*,RIGHT,PTIE +S 1900,2000,2400,2000,300,*,RIGHT,POLY +V 1700,500,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 2100,4500,CONT_DIF_P,* +V 2700,1000,CONT_DIF_N,* +V 2700,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1000,2500,CONT_POLY,* +V 900,4500,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 1500,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,300,CONT_BODY_P,* +V 700,300,CONT_BODY_P,* +V 1100,300,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/a3_x2.sym b/pdks/symbolic/sxlib/cells/a3_x2.sym new file mode 100644 index 000000000..64f0ad54a Binary files /dev/null and b/pdks/symbolic/sxlib/cells/a3_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/a3_x2.vbe b/pdks/symbolic/sxlib/cells/a3_x2.vbe new file mode 100644 index 000000000..7a7b521b3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 290; + CONSTANT tphh_i1_q : NATURAL := 353; + CONSTANT tphh_i0_q : NATURAL := 395; + CONSTANT tpll_i0_q : NATURAL := 435; + CONSTANT tpll_i1_q : NATURAL := 479; + CONSTANT tpll_i2_q : NATURAL := 521; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x2; + +ARCHITECTURE behaviour_data_flow OF a3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x2" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1100 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/a3_x2.vhd b/pdks/symbolic/sxlib/cells/a3_x2.vhd new file mode 100644 index 000000000..08ae66625 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a3_x2.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a3_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a3_x2; + +ARCHITECTURE RTL OF a3_x2 IS +BEGIN + q <= ((i0 AND i1) AND i2); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/a3_x4.al b/pdks/symbolic/sxlib/cells/a3_x4.al new file mode 100644 index 000000000..a0b7376e5 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a3_x4.al @@ -0,0 +1,37 @@ +V ALLIANCE : 6 +H a3_x4,L,30/10/99 +C i0,IN,EXTERNAL,9 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,6,4,3,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00010 +T P,0.35,5.9,3,4,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00009 +T P,0.35,2.9,6,7,4,0,0.75,0.75,7.3,7.3,5.4,10.65,tr_00008 +T P,0.35,2.9,4,8,6,0,0.75,0.75,7.3,7.3,3.6,10.65,tr_00007 +T P,0.35,2.9,6,9,4,0,0.75,0.75,7.3,7.3,1.8,10.65,tr_00006 +T N,0.35,2.9,4,9,5,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00005 +T N,0.35,2.9,3,4,2,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00004 +T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00003 +T N,0.35,2.9,5,8,1,0,0.75,0.75,7.3,7.3,3,2.25,tr_00002 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,4.2,2.25,tr_00001 +S 9,EXTERNAL,i0 +Q 0.0028158 +S 8,EXTERNAL,i1 +Q 0.00331294 +S 7,EXTERNAL,i2 +Q 0.00325537 +S 6,EXTERNAL,vdd +Q 0.00554878 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00773401 +S 3,EXTERNAL,q +Q 0.00264397 +S 2,EXTERNAL,vss +Q 0.00484372 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/a3_x4.ap b/pdks/symbolic/sxlib/cells/a3_x4.ap new file mode 100644 index 000000000..468eeccfe --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a3_x4.ap @@ -0,0 +1,94 @@ +V ALLIANCE : 6 +H a3_x4,P,18/ 5/2002,100 +A 0,0,3500,5000 +R 2500,1500,ref_ref,q_15 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1500,2500,ref_ref,i2_25 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 2500,4000,ref_ref,q_40 +R 2500,3500,ref_ref,q_35 +R 2500,3000,ref_ref,q_30 +R 2500,2500,ref_ref,q_25 +R 2500,2000,ref_ref,q_20 +R 2500,1000,ref_ref,q_10 +S 3200,500,3200,1000,200,*,DOWN,ALU1 +S 2000,4500,2000,4700,300,*,UP,PDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 3200,300,3200,1200,300,*,UP,NDIF +S 2900,100,2900,1400,100,*,DOWN,NTRANS +S 2600,300,2600,1200,300,*,UP,NDIF +S 2300,100,2300,1400,100,*,DOWN,NTRANS +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 2900,1400,2900,2600,100,*,UP,POLY +S 2300,1400,2300,2600,100,*,UP,POLY +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1000,1500,1000,3500,100,*,DOWN,ALU1 +S 1500,1500,1500,3500,100,*,DOWN,ALU1 +S 1800,2900,1800,4200,100,*,UP,PTRANS +S 300,1000,2000,1000,100,*,RIGHT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 300,4000,2000,4000,100,*,RIGHT,ALU1 +S 1000,2500,1200,2500,300,*,RIGHT,POLY +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1000,1400,1000,2600,100,*,UP,POLY +S 1400,1400,1400,2100,100,*,UP,POLY +S 1600,2900,1800,2900,100,*,RIGHT,POLY +S 1600,1900,1600,2900,100,*,DOWN,POLY +S 1900,2000,2900,2000,300,*,RIGHT,POLY +S 2100,2800,2100,4700,300,*,UP,PDIF +S 300,3100,300,4000,300,*,DOWN,PDIF +S 1200,2900,1200,4200,100,*,UP,PTRANS +S 600,2900,600,4200,100,*,UP,PTRANS +S 1500,3100,1500,4000,300,*,DOWN,PDIF +S 900,3100,900,4600,300,*,DOWN,PDIF +S 1900,300,1900,1200,300,*,UP,NDIF +S 1700,300,1700,1200,300,*,UP,NDIF +S 3200,3000,3200,4500,200,*,DOWN,ALU1 +S 1200,2400,1200,2900,100,*,DOWN,POLY +S 600,1400,600,2900,100,*,UP,POLY +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i2,DOWN,CALU1 +V 2000,4600,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 3200,500,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2000,500,CONT_DIF_N,* +V 2600,1000,CONT_DIF_N,* +V 2600,3000,CONT_DIF_P,* +V 2600,4000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 3200,4500,CONT_DIF_P,* +V 2600,3500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 1000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/a3_x4.sym b/pdks/symbolic/sxlib/cells/a3_x4.sym new file mode 100644 index 000000000..3f536421c Binary files /dev/null and b/pdks/symbolic/sxlib/cells/a3_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/a3_x4.vbe b/pdks/symbolic/sxlib/cells/a3_x4.vbe new file mode 100644 index 000000000..556b6b0fc --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY a3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 356; + CONSTANT tphh_i1_q : NATURAL := 428; + CONSTANT tphh_i0_q : NATURAL := 478; + CONSTANT tpll_i0_q : NATURAL := 514; + CONSTANT tpll_i1_q : NATURAL := 554; + CONSTANT tpll_i2_q : NATURAL := 592; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x4; + +ARCHITECTURE behaviour_data_flow OF a3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a3_x4" + SEVERITY WARNING; + q <= ((i0 and i1) and i2) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/a3_x4.vhd b/pdks/symbolic/sxlib/cells/a3_x4.vhd new file mode 100644 index 000000000..751f7ee5f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a3_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a3_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a3_x4; + +ARCHITECTURE RTL OF a3_x4 IS +BEGIN + q <= ((i0 AND i1) AND i2); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/a4_x2.al b/pdks/symbolic/sxlib/cells/a4_x2.al new file mode 100644 index 000000000..bd8536a8c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a4_x2.al @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H a4_x2,L,30/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,11,1,6,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00010 +T P,0.35,2.9,1,10,6,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009 +T P,0.35,2.9,6,9,1,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,2.9,1,8,6,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00007 +T P,0.35,2.9,6,7,1,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00006 +T N,0.35,2.9,4,8,5,0,0.75,0.75,7.3,7.3,4.2,3.75,tr_00005 +T N,0.35,2.9,2,10,3,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00004 +T N,0.35,2.9,5,7,1,0,0.75,0.75,7.3,7.3,5.4,3.75,tr_00003 +T N,0.35,2.9,3,9,4,0,0.75,0.75,7.3,7.3,3,3.75,tr_00002 +T N,0.35,2.9,2,1,11,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00001 +S 11,EXTERNAL,q +Q 0.00364281 +S 10,EXTERNAL,i0 +Q 0.00288944 +S 9,EXTERNAL,i1 +Q 0.00310922 +S 8,EXTERNAL,i2 +Q 0.00332901 +S 7,EXTERNAL,i3 +Q 0.00318596 +S 6,EXTERNAL,vdd +Q 0.0046087 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.00402115 +S 1,INTERNAL +Q 0.00564944 +EOF diff --git a/pdks/symbolic/sxlib/cells/a4_x2.ap b/pdks/symbolic/sxlib/cells/a4_x2.ap new file mode 100644 index 000000000..6817d90a4 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a4_x2.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 6 +H a4_x2,P,18/ 5/2002,100 +A 0,0,3500,5000 +R 1500,1000,ref_ref,i2_10 +R 1000,1000,ref_ref,i1_10 +R 500,1000,ref_ref,i0_10 +R 3000,1000,ref_ref,q_10 +R 3000,1500,ref_ref,q_15 +R 3000,2000,ref_ref,q_20 +R 3000,2500,ref_ref,q_25 +R 3000,3000,ref_ref,q_30 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1000,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 2000,3500,ref_ref,i3_35 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,2000,ref_ref,i3_20 +R 2000,1500,ref_ref,i3_15 +R 1000,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i2_25 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +S 900,300,1900,300,300,*,RIGHT,PTIE +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 2000,1500,2000,3500,200,i3,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 3000,3000,3200,3000,200,*,RIGHT,ALU1 +S 3000,3500,3200,3500,200,*,RIGHT,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 2000,800,2000,1700,300,*,UP,NDIF +S 300,400,300,1700,300,*,UP,NDIF +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1800,600,1800,1900,100,*,DOWN,NTRANS +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 600,1900,600,3100,100,*,DOWN,POLY +S 1000,1900,1000,3100,100,*,UP,POLY +S 1400,1900,1400,2600,100,*,UP,POLY +S 2100,1900,2100,3100,100,*,DOWN,POLY +S 1600,2400,1600,3100,100,*,UP,POLY +S 1800,1900,2100,1900,100,*,RIGHT,POLY +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 3200,300,3200,1200,300,*,UP,NDIF +S 2400,2500,2900,2500,300,*,RIGHT,POLY +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 2900,100,2900,1400,100,*,DOWN,NTRANS +S 2900,1400,2900,2600,100,*,UP,POLY +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 2100,3100,2400,3100,100,*,LEFT,POLY +S 1600,3100,1800,3100,100,*,RIGHT,POLY +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 300,3300,300,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 1500,3300,1500,4600,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 2100,1000,2550,1000,100,*,RIGHT,ALU1 +S 900,4000,2550,4000,100,*,RIGHT,ALU1 +S 3000,950,3000,4050,200,*,DOWN,ALU1 +S 2950,1000,3200,1000,200,*,LEFT,ALU1 +S 2950,4000,3200,4000,200,*,RIGHT,ALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +V 1800,300,CONT_BODY_P,* +V 1000,300,CONT_BODY_P,* +V 1500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2600,400,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 3200,3000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 2500,2500,CONT_POLY,* +V 2600,4700,CONT_DIF_P,* +V 1000,2500,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/a4_x2.sym b/pdks/symbolic/sxlib/cells/a4_x2.sym new file mode 100644 index 000000000..716d5421e Binary files /dev/null and b/pdks/symbolic/sxlib/cells/a4_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/a4_x2.vbe b/pdks/symbolic/sxlib/cells/a4_x2.vbe new file mode 100644 index 000000000..3a6353969 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 374; + CONSTANT tphh_i1_q : NATURAL := 441; + CONSTANT tpll_i3_q : NATURAL := 455; + CONSTANT tphh_i2_q : NATURAL := 482; + CONSTANT tpll_i2_q : NATURAL := 498; + CONSTANT tphh_i3_q : NATURAL := 506; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x2; + +ARCHITECTURE behaviour_data_flow OF a4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/a4_x2.vhd b/pdks/symbolic/sxlib/cells/a4_x2.vhd new file mode 100644 index 000000000..5819d66ab --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a4_x2.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a4_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a4_x2; + +ARCHITECTURE RTL OF a4_x2 IS +BEGIN + q <= (((i0 AND i1) AND i2) AND i3); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/a4_x4.al b/pdks/symbolic/sxlib/cells/a4_x4.al new file mode 100644 index 000000000..7ce759937 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a4_x4.al @@ -0,0 +1,45 @@ +V ALLIANCE : 6 +H a4_x4,L,30/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,5 +T P,0.35,5.9,11,3,6,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00013 +T P,0.35,5.9,11,3,6,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00012 +T P,0.35,2.9,6,7,3,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00011 +T P,0.35,2.9,3,8,6,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010 +T P,0.35,2.9,6,9,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00009 +T P,0.35,2.9,3,10,6,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00008 +T N,0.35,2.9,11,3,5,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00007 +T N,0.35,2.9,11,3,5,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00006 +T N,0.35,2.9,5,3,11,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00005 +T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,3,3.75,tr_00004 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,5.4,3.75,tr_00003 +T N,0.35,2.9,5,10,1,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00002 +T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,4.2,3.75,tr_00001 +S 11,EXTERNAL,q +Q 0.00264397 +S 10,EXTERNAL,i0 +Q 0.00288944 +S 9,EXTERNAL,i1 +Q 0.00310922 +S 8,EXTERNAL,i2 +Q 0.00332901 +S 7,EXTERNAL,i3 +Q 0.00318597 +S 6,EXTERNAL,vdd +Q 0.00665407 +S 5,EXTERNAL,vss +Q 0.00571399 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.0070012 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/a4_x4.ap b/pdks/symbolic/sxlib/cells/a4_x4.ap new file mode 100644 index 000000000..81cb020ff --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a4_x4.ap @@ -0,0 +1,115 @@ +V ALLIANCE : 6 +H a4_x4,P,18/ 5/2002,100 +A 0,0,4000,5000 +R 1500,1000,ref_ref,i2_10 +R 1000,1000,ref_ref,i1_10 +R 500,1000,ref_ref,i0_10 +R 3000,1000,ref_ref,q_10 +R 3000,1500,ref_ref,q_15 +R 3000,2000,ref_ref,q_20 +R 3000,2500,ref_ref,q_25 +R 3000,3000,ref_ref,q_30 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1000,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 2000,3500,ref_ref,i3_35 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,2000,ref_ref,i3_20 +R 2000,1500,ref_ref,i3_15 +R 1000,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i2_25 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +S 3700,500,3700,1000,200,*,DOWN,ALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 2000,1500,2000,3500,200,i3,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +S 3000,950,3000,4050,200,*,DOWN,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 2000,900,2000,1700,300,*,UP,NDIF +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 900,4000,2550,4000,100,*,RIGHT,ALU1 +S 2100,1000,2550,1000,100,*,RIGHT,ALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 300,400,300,1700,300,*,UP,NDIF +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1800,600,1800,1900,100,*,DOWN,NTRANS +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 600,1900,600,3100,100,*,DOWN,POLY +S 1000,1900,1000,3100,100,*,UP,POLY +S 1400,1900,1400,2600,100,*,UP,POLY +S 2100,1900,2100,3100,100,*,DOWN,POLY +S 1600,2400,1600,3100,100,*,UP,POLY +S 1800,1900,2100,1900,100,*,RIGHT,POLY +S 3200,300,3200,1200,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 300,3300,300,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 900,3300,900,4200,300,*,DOWN,PDIF +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 2800,1400,2800,2600,100,*,UP,POLY +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 3400,2600,3400,4900,100,*,DOWN,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 3700,3000,3700,4500,200,*,UP,ALU1 +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2400,2500,3400,2500,300,*,RIGHT,POLY +S 1450,3300,1450,4600,200,*,DOWN,PDIF +S 1700,3100,1700,4400,100,*,UP,PTRANS +S 2300,3100,2300,4400,100,*,UP,PTRANS +S 2100,3100,2300,3100,100,*,LEFT,POLY +S 1600,3100,1700,3100,100,*,RIGHT,POLY +S 2550,2800,2550,4700,200,*,DOWN,PDIF +S 900,300,1900,300,300,*,RIGHT,PTIE +V 300,4000,CONT_DIF_P,* +V 1800,300,CONT_BODY_P,* +V 1000,300,CONT_BODY_P,* +V 1500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2100,1000,CONT_DIF_N,* +V 2500,2500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 2500,400,CONT_DIF_N,* +V 3100,1000,CONT_DIF_N,* +V 3100,4000,CONT_DIF_P,* +V 3100,3000,CONT_DIF_P,* +V 3100,3500,CONT_DIF_P,* +V 2500,4700,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 3700,500,CONT_DIF_N,* +V 3700,4500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 1500,4700,CONT_DIF_P,* +V 2000,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/a4_x4.sym b/pdks/symbolic/sxlib/cells/a4_x4.sym new file mode 100644 index 000000000..d6f59e2ba Binary files /dev/null and b/pdks/symbolic/sxlib/cells/a4_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/a4_x4.vbe b/pdks/symbolic/sxlib/cells/a4_x4.vbe new file mode 100644 index 000000000..4f96afa4c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY a4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 540; + CONSTANT rdown_i1_q : NATURAL := 540; + CONSTANT rdown_i2_q : NATURAL := 540; + CONSTANT rdown_i3_q : NATURAL := 540; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 505; + CONSTANT tpll_i3_q : NATURAL := 538; + CONSTANT tpll_i2_q : NATURAL := 576; + CONSTANT tphh_i1_q : NATURAL := 578; + CONSTANT tpll_i1_q : NATURAL := 614; + CONSTANT tphh_i2_q : NATURAL := 627; + CONSTANT tpll_i0_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 661; + CONSTANT transistors : NATURAL := 13 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x4; + +ARCHITECTURE behaviour_data_flow OF a4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on a4_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) and i3) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/a4_x4.vhd b/pdks/symbolic/sxlib/cells/a4_x4.vhd new file mode 100644 index 000000000..93ffcf82e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/a4_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY a4_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END a4_x4; + +ARCHITECTURE RTL OF a4_x4 IS +BEGIN + q <= (((i0 AND i1) AND i2) AND i3); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/an12_x1.al b/pdks/symbolic/sxlib/cells/an12_x1.al new file mode 100644 index 000000000..fd4692132 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/an12_x1.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H an12_x1,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,4,7,1,0,0.75,0.75,13.3,13.3,2.7,11.25,tr_00006 +T P,0.35,5.9,5,3,4,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00005 +T P,0.35,2.9,3,6,5,0,0.75,0.75,7.3,7.3,5.7,9.75,tr_00004 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,2.1,3,tr_00003 +T N,0.35,1.4,1,3,2,0,0.75,0.75,4.3,4.3,3.9,3,tr_00002 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,5.7,3,tr_00001 +S 7,EXTERNAL,i0 +Q 0.00319019 +S 6,EXTERNAL,i1 +Q 0.00362068 +S 5,EXTERNAL,vdd +Q 0.00298567 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00417012 +S 2,EXTERNAL,vss +Q 0.00351447 +S 1,EXTERNAL,q +Q 0.00384845 +EOF diff --git a/pdks/symbolic/sxlib/cells/an12_x1.ap b/pdks/symbolic/sxlib/cells/an12_x1.ap new file mode 100644 index 000000000..a17cb8f30 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/an12_x1.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H an12_x1,P, 7/ 6/2002,100 +A 0,0,2500,5000 +R 1500,1000,ref_ref,i1_10 +R 500,1000,ref_ref,q_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2500,ref_ref,i0_25 +R 500,4000,ref_ref,q_40 +R 500,3500,ref_ref,q_35 +R 1500,2500,ref_ref,i1_25 +R 1500,3000,ref_ref,i1_30 +R 1500,3500,ref_ref,i1_35 +R 1500,4000,ref_ref,i1_40 +R 500,3000,ref_ref,q_30 +R 500,2500,ref_ref,q_25 +R 500,1500,ref_ref,q_15 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1500,1500,ref_ref,i1_15 +R 1500,2000,ref_ref,i1_20 +S 2200,4300,2200,4800,300,*,DOWN,NTIE +S 700,2000,900,2000,300,*,LEFT,POLY +S 1700,1500,1900,1500,300,*,RIGHT,POLY +S 1700,2500,1900,2500,300,*,RIGHT,POLY +S 500,1000,500,1550,200,*,DOWN,ALU1 +S 250,2500,400,2500,200,*,LEFT,ALU1 +S 250,1500,500,1500,200,*,RIGHT,ALU1 +S 300,1450,300,2550,200,*,DOWN,ALU1 +S 900,2000,900,2600,100,*,UP,POLY +S 700,2000,900,2000,100,*,RIGHT,POLY +S 700,1400,700,2000,100,*,UP,POLY +S 1900,2400,1900,2600,100,*,UP,POLY +S 1900,1400,1900,1600,100,*,UP,POLY +S 1500,1500,1700,1500,200,*,LEFT,ALU1 +S 1500,2500,1700,2500,200,*,LEFT,ALU1 +S 2200,1000,2200,3500,100,*,UP,ALU1 +S 1300,2000,2200,2000,100,*,RIGHT,POLY +S 2200,2800,2200,3700,300,*,UP,PDIF +S 2200,800,2200,1200,300,*,DOWN,NDIF +S 1300,2050,1300,2600,100,*,DOWN,POLY +S 400,2800,400,4200,300,*,DOWN,PDIF +S 1900,2600,1900,3900,100,*,UP,PTRANS +S 600,2800,600,4200,300,*,DOWN,PDIF +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,UP,PDIF +S 900,2600,900,4900,100,*,UP,PTRANS +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1600,400,1600,1200,300,*,UP,NDIF +S 400,400,400,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 1300,1400,1300,2000,100,*,UP,POLY +S 450,1000,1000,1000,200,*,LEFT,ALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 1500,1000,1500,4000,200,i1,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 500,2500,500,4000,200,q,DOWN,CALU1 +S 500,1000,500,1500,200,q,DOWN,CALU1 +S 500,2450,500,4000,200,*,DOWN,ALU1 +V 900,2000,CONT_POLY,* +V 1700,1500,CONT_POLY,* +V 1700,2500,CONT_POLY,* +V 2200,2000,CONT_POLY,* +V 2200,1000,CONT_DIF_N,* +V 2200,3500,CONT_DIF_P,* +V 2200,4700,CONT_BODY_N,* +V 400,4000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 2200,3000,CONT_DIF_P,* +V 1600,500,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/an12_x1.sym b/pdks/symbolic/sxlib/cells/an12_x1.sym new file mode 100644 index 000000000..eafa148f0 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/an12_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/an12_x1.vbe b/pdks/symbolic/sxlib/cells/an12_x1.vbe new file mode 100644 index 000000000..10267b443 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/an12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 3640; + CONSTANT rdown_i1_q : NATURAL := 3640; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i0_q : NATURAL := 168; + CONSTANT tphl_i0_q : NATURAL := 200; + CONSTANT tphh_i1_q : NATURAL := 285; + CONSTANT tpll_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x1; + +ARCHITECTURE behaviour_data_flow OF an12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x1" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/an12_x1.vhd b/pdks/symbolic/sxlib/cells/an12_x1.vhd new file mode 100644 index 000000000..6779ed375 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/an12_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY an12_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END an12_x1; + +ARCHITECTURE RTL OF an12_x1 IS +BEGIN + q <= (NOT(i0) AND i1); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/an12_x4.al b/pdks/symbolic/sxlib/cells/an12_x4.al new file mode 100644 index 000000000..95b23dae1 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/an12_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H an12_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,5,6,4,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00010 +T P,0.35,2.9,1,4,5,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00009 +T P,0.35,5.9,8,1,5,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00008 +T P,0.35,5.9,5,1,8,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00007 +T P,0.35,2.9,5,7,1,0,0.75,0.75,7.3,7.3,6.6,11.25,tr_00006 +T N,0.35,1.4,3,6,4,0,0.75,0.75,4.3,4.3,1.8,2.1,tr_00005 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00004 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,3,1,8,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00002 +T N,0.35,2.9,8,1,3,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00001 +S 8,EXTERNAL,q +Q 0.00258522 +S 7,EXTERNAL,i1 +Q 0.00400776 +S 6,EXTERNAL,i0 +Q 0.00372902 +S 5,EXTERNAL,vdd +Q 0.00606652 +S 4,INTERNAL +Q 0.00525013 +S 3,EXTERNAL,vss +Q 0.00536146 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00603296 +EOF diff --git a/pdks/symbolic/sxlib/cells/an12_x4.ap b/pdks/symbolic/sxlib/cells/an12_x4.ap new file mode 100644 index 000000000..9a5d2e5f0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/an12_x4.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H an12_x4,P,18/ 5/2002,100 +A 0,0,4000,5000 +R 2500,1500,ref_ref,i1_15 +R 2500,2000,ref_ref,i1_20 +R 2500,2500,ref_ref,i1_25 +R 2500,3000,ref_ref,i1_30 +R 2500,3500,ref_ref,i1_35 +R 2500,4000,ref_ref,i1_40 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 3000,3000,ref_ref,q_30 +R 3000,2500,ref_ref,q_25 +R 3000,2000,ref_ref,q_20 +R 3000,1500,ref_ref,q_15 +R 3000,1000,ref_ref,q_10 +R 2500,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i0_15 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,1000,ref_ref,i0_10 +R 1000,4000,ref_ref,i0_40 +S 3700,500,3700,1000,200,*,DOWN,ALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3700,3000,3700,4500,200,*,DOWN,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 2500,1000,2500,4000,100,*,DOWN,ALU1 +S 1950,1000,1950,4000,100,*,DOWN,ALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 2000,2000,3400,2000,100,*,RIGHT,POLY +S 2800,1400,2800,2600,100,*,UP,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2200,2500,2500,2500,300,*,RIGHT,POLY +S 2200,1500,2500,1500,300,*,RIGHT,POLY +S 2200,2400,2200,3100,100,*,DOWN,POLY +S 3700,300,3700,1200,300,*,UP,NDIF +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 3100,300,3100,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 2200,100,2200,1400,100,*,DOWN,NTRANS +S 2200,3100,2200,4400,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,DOWN,PDIF +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 3700,2800,3700,4700,300,*,DOWN,PDIF +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 1900,3300,1900,4200,300,*,DOWN,PDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1600,3100,1600,4400,100,*,UP,PTRANS +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,1000,1950,1000,100,*,RIGHT,ALU1 +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 600,300,600,1100,100,*,UP,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1100,3300,1100,4600,700,*,DOWN,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,2500,1600,2500,100,*,RIGHT,POLY +S 1600,1400,1600,3100,100,*,DOWN,POLY +S 1600,1400,1800,1400,100,*,RIGHT,POLY +S 600,3100,1000,3100,100,*,RIGHT,POLY +S 1000,3000,1000,3100,100,*,DOWN,POLY +S 600,1100,1000,1100,100,*,RIGHT,POLY +S 1000,1100,1000,1200,100,*,UP,POLY +S 2500,1000,2500,4000,200,i1,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +V 1900,3500,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 2400,2500,CONT_POLY,* +V 2400,1500,CONT_POLY,* +V 2500,500,CONT_DIF_N,* +V 3100,1000,CONT_DIF_N,* +V 3700,500,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 2500,4500,CONT_DIF_P,* +V 3700,4500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 1900,4000,CONT_DIF_P,* +V 3100,3000,CONT_DIF_P,* +V 3100,3500,CONT_DIF_P,* +V 3100,4000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 1300,4500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1000,3000,CONT_POLY,* +V 900,4500,CONT_DIF_P,* +V 300,2500,CONT_POLY,* +V 1000,1200,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/an12_x4.sym b/pdks/symbolic/sxlib/cells/an12_x4.sym new file mode 100644 index 000000000..4b6274ced Binary files /dev/null and b/pdks/symbolic/sxlib/cells/an12_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/an12_x4.vbe b/pdks/symbolic/sxlib/cells/an12_x4.vbe new file mode 100644 index 000000000..0d030a6cb --- /dev/null +++ b/pdks/symbolic/sxlib/cells/an12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY an12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphl_i0_q : NATURAL := 461; + CONSTANT tplh_i0_q : NATURAL := 471; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x4; + +ARCHITECTURE behaviour_data_flow OF an12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an12_x4" + SEVERITY WARNING; + q <= (not (i0) and i1) after 1100 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/an12_x4.vhd b/pdks/symbolic/sxlib/cells/an12_x4.vhd new file mode 100644 index 000000000..cc1252a13 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/an12_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY an12_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END an12_x4; + +ARCHITECTURE RTL OF an12_x4 IS +BEGIN + q <= (NOT(i0) AND i1); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/ao22_x2.al b/pdks/symbolic/sxlib/cells/ao22_x2.al new file mode 100644 index 000000000..7a3497ad6 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao22_x2.al @@ -0,0 +1,35 @@ +V ALLIANCE : 6 +H ao22_x2,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,6 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,9,6,2,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,2.9,5,8,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T P,0.35,2.9,2,7,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00006 +T P,0.35,5.9,5,2,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005 +T N,0.35,2.9,4,2,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,1.4,1,7,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003 +T N,0.35,1.4,3,6,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002 +T N,0.35,1.4,2,8,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 9,INTERNAL +Q 0 +S 8,EXTERNAL,i0 +Q 0.00295462 +S 7,EXTERNAL,i2 +Q 0.00371745 +S 6,EXTERNAL,i1 +Q 0.00344928 +S 5,EXTERNAL,vdd +Q 0.00367968 +S 4,EXTERNAL,q +Q 0.00358405 +S 3,INTERNAL +Q 0.00114171 +S 2,INTERNAL +Q 0.00464422 +S 1,EXTERNAL,vss +Q 0.00367968 +EOF diff --git a/pdks/symbolic/sxlib/cells/ao22_x2.ap b/pdks/symbolic/sxlib/cells/ao22_x2.ap new file mode 100644 index 000000000..d940d9870 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao22_x2.ap @@ -0,0 +1,99 @@ +V ALLIANCE : 6 +H ao22_x2,P,18/ 5/2002,100 +A 0,0,3000,5000 +R 2000,1000,ref_ref,i2_10 +R 2500,1000,ref_ref,q_10 +R 2500,1500,ref_ref,q_15 +R 2500,2000,ref_ref,q_20 +R 2500,2500,ref_ref,q_25 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,4000,ref_ref,i2_40 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +S 200,300,1600,300,300,*,RIGHT,PTIE +S 800,4700,1600,4700,300,*,RIGHT,NTIE +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 2500,3000,2700,3000,200,*,RIGHT,ALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 900,1500,1500,1500,100,*,RIGHT,ALU1 +S 1500,1500,1500,4000,100,*,DOWN,ALU1 +S 300,1000,1500,1000,100,*,RIGHT,ALU1 +S 1000,2000,1000,4000,100,*,UP,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 2500,1000,2700,1000,200,*,RIGHT,ALU1 +S 2500,4000,2700,4000,200,*,RIGHT,ALU1 +S 2500,3500,2700,3500,200,*,RIGHT,ALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2400,1400,2400,2600,100,*,UP,POLY +S 600,1400,600,3100,100,*,UP,POLY +S 1200,1400,1200,1800,100,*,DOWN,POLY +S 900,1800,1200,1800,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 1800,2600,1800,3100,100,*,DOWN,POLY +S 1800,2600,2100,2600,100,*,LEFT,POLY +S 1000,1800,1000,2100,300,*,UP,POLY +S 1400,2100,2400,2100,100,*,RIGHT,POLY +S 600,600,600,1400,100,*,UP,NTRANS +S 1200,600,1200,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 300,800,300,1200,300,*,DOWN,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 900,800,900,1600,300,*,DOWN,NDIF +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 2400,2600,2400,4900,100,*,DOWN,PTRANS +S 1500,3300,1500,4200,300,*,UP,PDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 300,3300,300,4600,300,*,UP,PDIF +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +V 1000,3000,CONT_POLY,* +V 1500,2200,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 900,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 2100,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 900,1500,CONT_DIF_N,* +V 1500,4700,CONT_BODY_N,* +V 2100,4500,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/ao22_x2.sym b/pdks/symbolic/sxlib/cells/ao22_x2.sym new file mode 100644 index 000000000..ce180b7b2 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/ao22_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/ao22_x2.vbe b/pdks/symbolic/sxlib/cells/ao22_x2.vbe new file mode 100644 index 000000000..7cfca61f3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 420; + CONSTANT tpll_i2_q : NATURAL := 425; + CONSTANT tpll_i0_q : NATURAL := 447; + CONSTANT tphh_i1_q : NATURAL := 493; + CONSTANT tpll_i1_q : NATURAL := 526; + CONSTANT tphh_i0_q : NATURAL := 558; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x2; + +ARCHITECTURE behaviour_data_flow OF ao22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/ao22_x2.vhd b/pdks/symbolic/sxlib/cells/ao22_x2.vhd new file mode 100644 index 000000000..e0a0dd3e5 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao22_x2.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ao22_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ao22_x2; + +ARCHITECTURE RTL OF ao22_x2 IS +BEGIN + q <= ((i0 OR i1) AND i2); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/ao22_x4.al b/pdks/symbolic/sxlib/cells/ao22_x4.al new file mode 100644 index 000000000..97b82f3d8 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao22_x4.al @@ -0,0 +1,37 @@ +V ALLIANCE : 6 +H ao22_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,2.9,3,6,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010 +T P,0.35,2.9,5,8,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009 +T P,0.35,2.9,9,7,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,5.9,5,3,4,0,0.75,0.75,13.3,13.3,8.1,11.25,tr_00007 +T P,0.35,5.9,4,3,5,0,0.75,0.75,13.3,13.3,9.9,11.25,tr_00006 +T N,0.35,1.4,3,8,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005 +T N,0.35,1.4,1,7,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004 +T N,0.35,1.4,2,6,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003 +T N,0.35,2.9,2,3,4,0,0.75,0.75,7.3,7.3,9.9,2.25,tr_00002 +T N,0.35,2.9,4,3,2,0,0.75,0.75,7.3,7.3,8.1,2.25,tr_00001 +S 9,INTERNAL +Q 0 +S 8,EXTERNAL,i0 +Q 0.00295461 +S 7,EXTERNAL,i1 +Q 0.00344928 +S 6,EXTERNAL,i2 +Q 0.00371745 +S 5,EXTERNAL,vdd +Q 0.00606652 +S 4,EXTERNAL,q +Q 0.00258522 +S 3,INTERNAL +Q 0.00618269 +S 2,EXTERNAL,vss +Q 0.00512644 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/pdks/symbolic/sxlib/cells/ao22_x4.ap b/pdks/symbolic/sxlib/cells/ao22_x4.ap new file mode 100644 index 000000000..2cb869ec6 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao22_x4.ap @@ -0,0 +1,110 @@ +V ALLIANCE : 6 +H ao22_x4,P,18/ 5/2002,100 +A 0,0,4000,5000 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 500,4000,ref_ref,i0_40 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 2000,4000,ref_ref,i2_40 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 3000,1000,ref_ref,q_10 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 3000,3000,ref_ref,q_30 +R 3000,2500,ref_ref,q_25 +R 3000,2000,ref_ref,q_20 +R 3000,1500,ref_ref,q_15 +R 2000,1000,ref_ref,i2_10 +S 200,300,1600,300,300,*,RIGHT,PTIE +S 800,4700,1600,4700,300,*,RIGHT,NTIE +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 3600,2800,3600,4700,300,*,UP,PDIF +S 3300,2600,3300,4900,100,*,DOWN,PTRANS +S 3000,2800,3000,4700,300,*,UP,PDIF +S 2700,2600,2700,4900,100,*,DOWN,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 300,3300,300,4600,300,*,UP,PDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 1500,3300,1500,4200,300,*,UP,PDIF +S 2400,2800,2400,4700,400,*,UP,PDIF +S 2400,300,2400,1200,400,*,DOWN,NDIF +S 3600,300,3600,1200,300,*,DOWN,NDIF +S 3000,300,3000,1200,300,*,DOWN,NDIF +S 2700,100,2700,1400,100,*,UP,NTRANS +S 900,800,900,1600,300,*,DOWN,NDIF +S 3300,100,3300,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 300,800,300,1200,300,*,DOWN,NDIF +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,UP,NTRANS +S 600,600,600,1400,100,*,UP,NTRANS +S 3300,1400,3300,2600,100,*,UP,POLY +S 1000,1800,1000,2100,300,*,UP,POLY +S 1400,2100,3300,2100,100,*,RIGHT,POLY +S 2700,1400,2700,2600,100,*,UP,POLY +S 1800,2600,2100,2600,100,*,LEFT,POLY +S 1800,2600,1800,3100,100,*,DOWN,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 900,1800,1200,1800,100,*,RIGHT,POLY +S 1200,1400,1200,1800,100,*,DOWN,POLY +S 600,1400,600,3100,100,*,UP,POLY +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3600,3000,3600,4500,200,*,UP,ALU1 +S 3600,500,3600,1000,200,*,DOWN,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 1000,2000,1000,4000,100,*,UP,ALU1 +S 300,1000,1500,1000,100,*,RIGHT,ALU1 +S 1500,1500,1500,4000,100,*,DOWN,ALU1 +S 900,1500,1500,1500,100,*,RIGHT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +V 3000,3500,CONT_DIF_P,* +V 3000,3000,CONT_DIF_P,* +V 3600,3500,CONT_DIF_P,* +V 3600,4000,CONT_DIF_P,* +V 2300,4500,CONT_DIF_P,* +V 3600,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 3000,4000,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 3600,3000,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 3600,500,CONT_DIF_N,* +V 2300,500,CONT_DIF_N,* +V 3000,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3600,1000,CONT_DIF_N,* +V 1500,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 1500,2200,CONT_POLY,* +V 1000,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/ao22_x4.sym b/pdks/symbolic/sxlib/cells/ao22_x4.sym new file mode 100644 index 000000000..a74c52373 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/ao22_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/ao22_x4.vbe b/pdks/symbolic/sxlib/cells/ao22_x4.vbe new file mode 100644 index 000000000..2995c9cca --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY ao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tpll_i2_q : NATURAL := 505; + CONSTANT tphh_i2_q : NATURAL := 526; + CONSTANT tpll_i0_q : NATURAL := 552; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 647; + CONSTANT tphh_i0_q : NATURAL := 674; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao22_x4; + +ARCHITECTURE behaviour_data_flow OF ao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and i2) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/ao22_x4.vhd b/pdks/symbolic/sxlib/cells/ao22_x4.vhd new file mode 100644 index 000000000..9edee9dd3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao22_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ao22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ao22_x4; + +ARCHITECTURE RTL OF ao22_x4 IS +BEGIN + q <= ((i0 OR i1) AND i2); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/ao2o22_x2.al b/pdks/symbolic/sxlib/cells/ao2o22_x2.al new file mode 100644 index 000000000..c9435003a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao2o22_x2.al @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H ao2o22_x2,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,4 +C i2,IN,EXTERNAL,5 +C i3,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,9 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,10,6,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00010 +T P,0.35,2.9,11,5,3,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00009 +T P,0.35,2.9,9,7,11,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00008 +T P,0.35,2.9,3,4,10,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00007 +T P,0.35,5.9,8,3,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00006 +T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00005 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00004 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,3,4,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002 +T N,0.35,2.9,1,3,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00001 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,EXTERNAL,vdd +Q 0.00505663 +S 8,EXTERNAL,q +Q 0.00258522 +S 7,EXTERNAL,i3 +Q 0.00295462 +S 6,EXTERNAL,i0 +Q 0.00295462 +S 5,EXTERNAL,i2 +Q 0.00323197 +S 4,EXTERNAL,i1 +Q 0.00323197 +S 3,INTERNAL +Q 0.00640584 +S 2,INTERNAL +Q 0.00199441 +S 1,EXTERNAL,vss +Q 0.00564418 +EOF diff --git a/pdks/symbolic/sxlib/cells/ao2o22_x2.ap b/pdks/symbolic/sxlib/cells/ao2o22_x2.ap new file mode 100644 index 000000000..212547d2d --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao2o22_x2.ap @@ -0,0 +1,112 @@ +V ALLIANCE : 6 +H ao2o22_x2,P,18/ 5/2002,100 +A 0,0,4500,5000 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2500,3000,ref_ref,i3_30 +R 2500,2500,ref_ref,i3_25 +R 2500,2000,ref_ref,i3_20 +R 2500,1500,ref_ref,i3_15 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 2000,3500,ref_ref,i2_35 +R 2500,3500,ref_ref,i3_35 +R 4000,4000,ref_ref,q_40 +R 4000,2000,ref_ref,q_20 +R 4000,3000,ref_ref,q_30 +R 4000,3500,ref_ref,q_35 +R 4000,2500,ref_ref,q_25 +R 4000,1500,ref_ref,q_15 +R 4000,1000,ref_ref,q_10 +S 800,4700,2200,4700,300,*,RIGHT,NTIE +S 200,300,1600,300,300,*,RIGHT,PTIE +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 2000,1500,2000,3500,200,i2,DOWN,CALU1 +S 2500,1500,2500,3500,200,i3,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 2700,800,2700,1200,300,*,UP,NDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 300,1000,2700,1000,100,*,RIGHT,ALU1 +S 900,800,900,1600,300,*,UP,NDIF +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 900,1500,1500,1500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 300,800,300,1200,300,*,UP,NDIF +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 4000,300,4000,1200,300,*,UP,NDIF +S 3400,300,3400,1200,300,*,UP,NDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 1600,4000,3000,4000,100,*,LEFT,ALU1 +S 3000,2000,3000,4000,100,*,DOWN,ALU1 +S 3000,2000,3500,2000,100,*,RIGHT,ALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 3500,2000,3700,2000,300,*,RIGHT,POLY +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 1500,300,CONT_BODY_P,* +V 1500,4700,CONT_BODY_N,* +V 2700,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 2100,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 900,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 3500,2000,CONT_POLY,* +V 3400,500,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 3400,4500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/ao2o22_x2.sym b/pdks/symbolic/sxlib/cells/ao2o22_x2.sym new file mode 100644 index 000000000..e11d7a606 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/ao2o22_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/ao2o22_x2.vbe b/pdks/symbolic/sxlib/cells/ao2o22_x2.vbe new file mode 100644 index 000000000..c503d1b97 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao2o22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 432; + CONSTANT tpll_i0_q : NATURAL := 451; + CONSTANT tphh_i3_q : NATURAL := 488; + CONSTANT tphh_i1_q : NATURAL := 508; + CONSTANT tpll_i3_q : NATURAL := 526; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tphh_i0_q : NATURAL := 572; + CONSTANT tpll_i2_q : NATURAL := 627; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x2; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x2" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/ao2o22_x2.vhd b/pdks/symbolic/sxlib/cells/ao2o22_x2.vhd new file mode 100644 index 000000000..1e6a58e72 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao2o22_x2.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ao2o22_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ao2o22_x2; + +ARCHITECTURE RTL OF ao2o22_x2 IS +BEGIN + q <= ((i0 OR i1) AND (i2 OR i3)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/ao2o22_x4.al b/pdks/symbolic/sxlib/cells/ao2o22_x4.al new file mode 100644 index 000000000..b54bd5fcb --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao2o22_x4.al @@ -0,0 +1,44 @@ +V ALLIANCE : 6 +H ao2o22_x4,L,30/10/99 +C i0,IN,EXTERNAL,5 +C i1,IN,EXTERNAL,4 +C i2,IN,EXTERNAL,6 +C i3,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,9 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,8,1,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00012 +T P,0.35,5.9,9,1,8,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00011 +T P,0.35,2.9,1,4,11,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00010 +T P,0.35,2.9,9,7,10,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00009 +T P,0.35,2.9,10,6,1,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00008 +T P,0.35,2.9,11,5,9,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T N,0.35,2.9,8,1,3,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00006 +T N,0.35,2.9,3,1,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00005 +T N,0.35,1.4,1,4,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004 +T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,3,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00002 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00001 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,EXTERNAL,vdd +Q 0.007102 +S 8,EXTERNAL,q +Q 0.00258522 +S 7,EXTERNAL,i3 +Q 0.00295462 +S 6,EXTERNAL,i2 +Q 0.00323197 +S 5,EXTERNAL,i0 +Q 0.00295461 +S 4,EXTERNAL,i1 +Q 0.00323197 +S 3,EXTERNAL,vss +Q 0.00674947 +S 2,INTERNAL +Q 0.00199441 +S 1,INTERNAL +Q 0.00812254 +EOF diff --git a/pdks/symbolic/sxlib/cells/ao2o22_x4.ap b/pdks/symbolic/sxlib/cells/ao2o22_x4.ap new file mode 100644 index 000000000..f5c2137ef --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao2o22_x4.ap @@ -0,0 +1,125 @@ +V ALLIANCE : 6 +H ao2o22_x4,P,18/ 5/2002,100 +A 0,0,5000,5000 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2500,3000,ref_ref,i3_30 +R 2500,2500,ref_ref,i3_25 +R 2500,2000,ref_ref,i3_20 +R 2500,1500,ref_ref,i3_15 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 2000,3500,ref_ref,i2_35 +R 2500,3500,ref_ref,i3_35 +R 4000,4000,ref_ref,q_40 +R 4000,2000,ref_ref,q_20 +R 4000,3000,ref_ref,q_30 +R 4000,3500,ref_ref,q_35 +R 4000,2500,ref_ref,q_25 +R 4000,1500,ref_ref,q_15 +R 4000,1000,ref_ref,q_10 +S 200,300,1600,300,300,*,RIGHT,PTIE +S 800,4700,2200,4700,300,*,RIGHT,NTIE +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 2700,800,2700,1200,300,*,UP,NDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 300,1000,2700,1000,100,*,RIGHT,ALU1 +S 900,800,900,1600,300,*,UP,NDIF +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 900,1500,1500,1500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 300,800,300,1200,300,*,UP,NDIF +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 3500,2000,4300,2000,300,*,RIGHT,POLY +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 4600,300,4600,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 3400,300,3400,1200,300,*,UP,NDIF +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 1600,4000,3000,4000,100,*,LEFT,ALU1 +S 3000,2000,3000,4000,100,*,DOWN,ALU1 +S 3000,2000,3500,2000,100,*,RIGHT,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 2000,1500,2000,3500,200,i2,DOWN,CALU1 +S 2500,1500,2500,3500,200,i3,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 1500,300,CONT_BODY_P,* +V 1500,4700,CONT_BODY_N,* +V 2700,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 2100,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 900,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 3500,2000,CONT_POLY,* +V 3400,500,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 4600,500,CONT_DIF_N,* +V 3400,4500,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/ao2o22_x4.sym b/pdks/symbolic/sxlib/cells/ao2o22_x4.sym new file mode 100644 index 000000000..b81d17b33 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/ao2o22_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/ao2o22_x4.vbe b/pdks/symbolic/sxlib/cells/ao2o22_x4.vbe new file mode 100644 index 000000000..61a5bff61 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY ao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 554; + CONSTANT tpll_i0_q : NATURAL := 569; + CONSTANT tphh_i3_q : NATURAL := 606; + CONSTANT tphh_i1_q : NATURAL := 637; + CONSTANT tpll_i3_q : NATURAL := 639; + CONSTANT tpll_i1_q : NATURAL := 666; + CONSTANT tphh_i0_q : NATURAL := 696; + CONSTANT tpll_i2_q : NATURAL := 744; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END ao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF ao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ao2o22_x4" + SEVERITY WARNING; + q <= ((i0 or i1) and (i2 or i3)) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/ao2o22_x4.vhd b/pdks/symbolic/sxlib/cells/ao2o22_x4.vhd new file mode 100644 index 000000000..e056132e3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ao2o22_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ao2o22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ao2o22_x4; + +ARCHITECTURE RTL OF ao2o22_x4 IS +BEGIN + q <= ((i0 OR i1) AND (i2 OR i3)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/buf_x2.al b/pdks/symbolic/sxlib/cells/buf_x2.al new file mode 100644 index 000000000..1fcb2f7a1 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x2.al @@ -0,0 +1,21 @@ +V ALLIANCE : 6 +H buf_x2,L,30/10/99 +C i,IN,EXTERNAL,5 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,3,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00004 +T P,0.35,1.7,4,5,3,0,0.75,0.75,4.9,4.9,1.8,9.15,tr_00003 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,0.8,3,5,1,0,0.75,0.75,3.1,3.1,1.8,3.3,tr_00001 +S 5,EXTERNAL,i +Q 0.00373582 +S 4,EXTERNAL,vdd +Q 0.00323175 +S 3,INTERNAL +Q 0.00370178 +S 2,EXTERNAL,q +Q 0.00258522 +S 1,EXTERNAL,vss +Q 0.0026442 +EOF diff --git a/pdks/symbolic/sxlib/cells/buf_x2.ap b/pdks/symbolic/sxlib/cells/buf_x2.ap new file mode 100644 index 000000000..a65c8b119 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x2.ap @@ -0,0 +1,57 @@ +V ALLIANCE : 6 +H buf_x2,P, 8/ 6/2002,100 +A 0,0,2000,5000 +R 1000,1000,ref_ref,i_10 +R 1000,1500,ref_ref,i_15 +R 1500,1000,ref_ref,q_10 +R 1500,2500,ref_ref,q_25 +R 1500,1500,ref_ref,q_15 +R 1500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,q_35 +R 1500,3000,ref_ref,q_30 +R 1500,2000,ref_ref,q_20 +R 1000,4000,ref_ref,i_40 +R 1000,3500,ref_ref,i_35 +R 1000,3000,ref_ref,i_30 +R 1000,2500,ref_ref,i_25 +R 1000,2000,ref_ref,i_20 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 300,4200,300,4700,200,*,DOWN,ALU1 +S 600,2500,800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 300,4200,300,4700,300,*,DOWN,NTIE +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 600,800,600,1400,100,*,DOWN,NTRANS +S 600,2600,600,3500,100,*,UP,PTRANS +S 300,2800,300,3300,300,*,DOWN,PDIF +S 300,1000,300,1200,300,*,UP,NDIF +S 300,1100,300,3000,100,*,DOWN,ALU1 +S 300,2000,1200,2000,200,*,RIGHT,POLY +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 800,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 800,2500,CONT_POLY,* +V 300,4200,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 300,3000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1100,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/buf_x2.sym b/pdks/symbolic/sxlib/cells/buf_x2.sym new file mode 100644 index 000000000..9fb82c89a Binary files /dev/null and b/pdks/symbolic/sxlib/cells/buf_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/buf_x2.vbe b/pdks/symbolic/sxlib/cells/buf_x2.vbe new file mode 100644 index 000000000..e2e4c344e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x2.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 6; + CONSTANT rdown_i_q : NATURAL := 1620; + CONSTANT rup_i_q : NATURAL := 1790; + CONSTANT tpll_i_q : NATURAL := 391; + CONSTANT tphh_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x2; + +ARCHITECTURE behaviour_data_flow OF buf_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x2" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/buf_x2.vhd b/pdks/symbolic/sxlib/cells/buf_x2.vhd new file mode 100644 index 000000000..e5c84422a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x2.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY buf_x2 IS +PORT( + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END buf_x2; + +ARCHITECTURE RTL OF buf_x2 IS +BEGIN + q <= i; +END RTL; diff --git a/pdks/symbolic/sxlib/cells/buf_x4.al b/pdks/symbolic/sxlib/cells/buf_x4.al new file mode 100644 index 000000000..f72dee408 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x4.al @@ -0,0 +1,23 @@ +V ALLIANCE : 6 +H buf_x4,L,30/10/99 +C i,IN,EXTERNAL,5 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,3,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00006 +T P,0.35,5.9,4,3,2,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00005 +T P,0.35,2.9,4,5,3,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00004 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,1.4,3,5,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 5,EXTERNAL,i +Q 0.00373582 +S 4,EXTERNAL,vdd +Q 0.00527712 +S 3,INTERNAL +Q 0.00574803 +S 2,EXTERNAL,q +Q 0.00258522 +S 1,EXTERNAL,vss +Q 0.00374949 +EOF diff --git a/pdks/symbolic/sxlib/cells/buf_x4.ap b/pdks/symbolic/sxlib/cells/buf_x4.ap new file mode 100644 index 000000000..a2d669f43 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x4.ap @@ -0,0 +1,71 @@ +V ALLIANCE : 6 +H buf_x4,P,18/ 5/2002,100 +A 0,0,2500,5000 +R 1000,1000,ref_ref,i_10 +R 1000,1500,ref_ref,i_15 +R 1500,1000,ref_ref,q_10 +R 1500,2500,ref_ref,q_25 +R 1500,1500,ref_ref,q_15 +R 1500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,q_35 +R 1500,3000,ref_ref,q_30 +R 1500,2000,ref_ref,q_20 +R 1000,4000,ref_ref,i_40 +R 1000,3500,ref_ref,i_35 +R 1000,3000,ref_ref,i_30 +R 1000,2500,ref_ref,i_25 +R 1000,2000,ref_ref,i_20 +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 300,2000,1800,2000,300,*,RIGHT,POLY +S 2100,500,2100,1000,200,*,DOWN,ALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 2100,3000,2100,4500,200,*,DOWN,ALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 300,4200,300,4700,200,*,DOWN,ALU1 +S 600,2500,800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 300,4200,300,4700,300,*,DOWN,NTIE +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,2600,600,3900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,DOWN,PDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +V 300,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 800,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 800,2500,CONT_POLY,* +V 300,4200,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 2100,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/buf_x4.sym b/pdks/symbolic/sxlib/cells/buf_x4.sym new file mode 100644 index 000000000..d4472e27d Binary files /dev/null and b/pdks/symbolic/sxlib/cells/buf_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/buf_x4.vbe b/pdks/symbolic/sxlib/cells/buf_x4.vbe new file mode 100644 index 000000000..0b7726ef9 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x4.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i : NATURAL := 9; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphh_i_q : NATURAL := 379; + CONSTANT tpll_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x4; + +ARCHITECTURE behaviour_data_flow OF buf_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x4" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/buf_x4.vhd b/pdks/symbolic/sxlib/cells/buf_x4.vhd new file mode 100644 index 000000000..208df74a1 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x4.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY buf_x4 IS +PORT( + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END buf_x4; + +ARCHITECTURE RTL OF buf_x4 IS +BEGIN + q <= i; +END RTL; diff --git a/pdks/symbolic/sxlib/cells/buf_x8.al b/pdks/symbolic/sxlib/cells/buf_x8.al new file mode 100644 index 000000000..55ee04cfd --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x8.al @@ -0,0 +1,27 @@ +V ALLIANCE : 6 +H buf_x8,L,30/10/99 +C i,IN,EXTERNAL,5 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T P,0.35,5.9,4,3,1,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,5.9,4,3,1,0,0.75,0.75,13.3,13.3,9,11.25,tr_00007 +T P,0.35,5.9,4,5,3,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00006 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00005 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00004 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,9,2.25,tr_00002 +T N,0.35,2.9,3,5,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 5,EXTERNAL,i +Q 0.00373582 +S 4,EXTERNAL,vdd +Q 0.00782917 +S 3,INTERNAL +Q 0.00908482 +S 2,EXTERNAL,vss +Q 0.00647781 +S 1,EXTERNAL,q +Q 0.00599301 +EOF diff --git a/pdks/symbolic/sxlib/cells/buf_x8.ap b/pdks/symbolic/sxlib/cells/buf_x8.ap new file mode 100644 index 000000000..048946336 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x8.ap @@ -0,0 +1,99 @@ +V ALLIANCE : 6 +H buf_x8,P,18/ 5/2002,100 +A 0,0,4000,5000 +R 1500,2000,ref_ref,q_20 +R 1500,3000,ref_ref,q_30 +R 1500,3500,ref_ref,q_35 +R 1500,4000,ref_ref,q_40 +R 1500,1000,ref_ref,q_10 +R 1500,2500,ref_ref,q_25 +R 1500,1500,ref_ref,q_15 +R 1000,1000,ref_ref,i_10 +R 1000,1500,ref_ref,i_15 +R 1000,4000,ref_ref,i_40 +R 1000,3500,ref_ref,i_35 +R 1000,3000,ref_ref,i_30 +R 1000,2500,ref_ref,i_25 +R 1000,2000,ref_ref,i_20 +S 3300,3350,3300,4500,200,*,DOWN,ALU1 +S 3250,3400,3700,3400,200,*,RIGHT,ALU1 +S 3700,2900,3700,3400,200,*,DOWN,ALU1 +S 3300,1700,3700,1700,200,*,RIGHT,ALU1 +S 3300,500,3300,1700,200,*,UP,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 600,2500,800,2500,300,*,RIGHT,POLY +S 300,2000,3000,2000,300,*,RIGHT,POLY +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 3200,1700,3800,1700,300,*,RIGHT,PTIE +S 300,300,300,1200,300,*,UP,NDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 3700,2900,3700,3400,300,*,DOWN,NTIE +S 3300,4000,3300,4700,300,*,DOWN,PDIF +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,500,2100,1000,200,*,DOWN,ALU1 +S 2100,3000,2100,4500,200,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1500,2000,2700,2000,200,*,RIGHT,ALU1 +S 2700,1000,2700,4000,200,*,UP,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 2700,1000,CONT_DIF_N,* +V 2700,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 800,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3700,1700,CONT_BODY_P,* +V 3300,1700,CONT_BODY_P,* +V 3700,3400,CONT_BODY_N,* +V 3700,2900,CONT_BODY_N,* +V 3300,4500,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 3300,1000,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 800,2500,CONT_POLY,* +V 2100,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/buf_x8.sym b/pdks/symbolic/sxlib/cells/buf_x8.sym new file mode 100644 index 000000000..21c53cae7 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/buf_x8.sym differ diff --git a/pdks/symbolic/sxlib/cells/buf_x8.vbe b/pdks/symbolic/sxlib/cells/buf_x8.vbe new file mode 100644 index 000000000..3b2ecc3bb --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x8.vbe @@ -0,0 +1,26 @@ +ENTITY buf_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i : NATURAL := 15; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphh_i_q : NATURAL := 343; + CONSTANT tpll_i_q : NATURAL := 396; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x8; + +ARCHITECTURE behaviour_data_flow OF buf_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on buf_x8" + SEVERITY WARNING; + q <= i after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/buf_x8.vhd b/pdks/symbolic/sxlib/cells/buf_x8.vhd new file mode 100644 index 000000000..cf5f0e48f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/buf_x8.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY buf_x8 IS +PORT( + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END buf_x8; + +ARCHITECTURE RTL OF buf_x8 IS +BEGIN + q <= i; +END RTL; diff --git a/pdks/symbolic/sxlib/cells/fulladder_x2.al b/pdks/symbolic/sxlib/cells/fulladder_x2.al new file mode 100644 index 000000000..10a81b4eb --- /dev/null +++ b/pdks/symbolic/sxlib/cells/fulladder_x2.al @@ -0,0 +1,100 @@ +V ALLIANCE : 6 +H fulladder_x2,L,30/10/99 +C a1,UNKNOWN,EXTERNAL,9 +C a2,UNKNOWN,EXTERNAL,10 +C a3,UNKNOWN,EXTERNAL,16 +C a4,UNKNOWN,EXTERNAL,21 +C b1,UNKNOWN,EXTERNAL,7 +C b2,UNKNOWN,EXTERNAL,6 +C b3,UNKNOWN,EXTERNAL,23 +C b4,UNKNOWN,EXTERNAL,24 +C cin1,IN,EXTERNAL,8 +C cin2,IN,EXTERNAL,22 +C cin3,IN,EXTERNAL,20 +C cout,OUT,EXTERNAL,11 +C sout,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,1 +T P,0.35,2,27,24,25,0,0.75,0.75,5.5,5.5,28.2,10.8,tr_00028 +T P,0.35,2,25,21,26,0,0.75,0.75,5.5,5.5,26.7,10.8,tr_00027 +T P,0.35,2,26,20,15,0,0.75,0.75,5.5,5.5,25.2,10.8,tr_00026 +T P,0.35,2.6,15,2,27,0,0.75,0.75,6.7,6.7,23.4,11.1,tr_00025 +T P,0.35,2,27,22,14,0,0.75,0.75,5.5,5.5,21.6,11.4,tr_00024 +T P,0.35,2,14,23,27,0,0.75,0.75,5.5,5.5,20.1,11.4,tr_00023 +T P,0.35,2,27,16,14,0,0.75,0.75,5.5,5.5,18.3,11.4,tr_00022 +T P,0.35,2.6,14,9,13,0,0.75,0.75,6.7,6.7,1.8,11.1,tr_00021 +T P,0.35,3.8,13,6,5,0,0.75,0.75,9.1,9.1,8.7,10.5,tr_00020 +T P,0.35,3.8,5,10,2,0,0.75,0.75,9.1,9.1,7.2,10.5,tr_00019 +T P,0.35,2.6,2,8,13,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00018 +T P,0.35,2.6,13,7,14,0,0.75,0.75,6.7,6.7,3.6,11.1,tr_00017 +T P,0.35,5.9,14,2,11,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00016 +T P,0.35,5.9,12,15,14,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00015 +T N,0.35,1.4,17,2,15,0,0.75,0.75,4.3,4.3,23.1,3.3,tr_00014 +T N,0.35,1.1,1,24,17,0,0.75,0.75,3.7,3.7,28.2,3.15,tr_00013 +T N,0.35,1.1,1,20,17,0,0.75,0.75,3.7,3.7,24.9,3.15,tr_00012 +T N,0.35,1.1,17,21,1,0,0.75,0.75,3.7,3.7,26.4,3.15,tr_00011 +T N,0.35,1.1,18,23,19,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00010 +T N,0.35,1.1,19,16,1,0,0.75,0.75,3.7,3.7,18.3,3.15,tr_00009 +T N,0.35,1.1,15,22,18,0,0.75,0.75,3.7,3.7,21.3,3.15,tr_00008 +T N,0.35,1.7,2,7,3,0,0.75,0.75,4.9,4.9,3.3,3.45,tr_00007 +T N,0.35,1.4,3,9,1,0,0.75,0.75,4.3,4.3,1.8,3.3,tr_00006 +T N,0.35,1.1,4,8,2,0,0.75,0.75,3.7,3.7,5.1,3.15,tr_00005 +T N,0.35,1.1,1,10,4,0,0.75,0.75,3.7,3.7,6.9,3.15,tr_00004 +T N,0.35,1.1,4,6,1,0,0.75,0.75,3.7,3.7,8.7,3.15,tr_00003 +T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00002 +T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00001 +S 27,INTERNAL +Q 0.00250174 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0 +S 24,EXTERNAL,b4 +Q 0.00295462 +S 23,EXTERNAL,b3 +Q 0.00296195 +S 22,EXTERNAL,cin2 +Q 0.00296195 +S 21,EXTERNAL,a4 +Q 0.00310499 +S 20,EXTERNAL,cin3 +Q 0.00283471 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00108534 +S 16,EXTERNAL,a3 +Q 0.00281157 +S 15,INTERNAL +Q 0.00630209 +S 14,EXTERNAL,vdd +Q 0.0105755 +S 13,INTERNAL +Q 0.00227626 +S 12,EXTERNAL,sout +Q 0.00211518 +S 11,EXTERNAL,cout +Q 0.00276149 +S 10,EXTERNAL,a2 +Q 0.00262649 +S 9,EXTERNAL,a1 +Q 0.00316706 +S 8,EXTERNAL,cin1 +Q 0.00311233 +S 7,EXTERNAL,b1 +Q 0.00311656 +S 6,EXTERNAL,b2 +Q 0.00239514 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00114171 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.0112381 +S 1,EXTERNAL,vss +Q 0.0111043 +EOF diff --git a/pdks/symbolic/sxlib/cells/fulladder_x2.ap b/pdks/symbolic/sxlib/cells/fulladder_x2.ap new file mode 100644 index 000000000..f4fa6ba46 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/fulladder_x2.ap @@ -0,0 +1,272 @@ +V ALLIANCE : 6 +H fulladder_x2,P,18/ 5/2002,100 +A 0,0,10000,5000 +R 500,1500,ref_ref,a1_15 +R 500,2000,ref_ref,a1_20 +R 500,2500,ref_ref,a1_25 +R 500,3000,ref_ref,a1_30 +R 1000,1500,ref_ref,b1_15 +R 1000,2000,ref_ref,b1_20 +R 1000,2500,ref_ref,b1_25 +R 1000,3000,ref_ref,b1_30 +R 2000,1500,ref_ref,cin1_15 +R 2000,2000,ref_ref,cin1_20 +R 2000,2500,ref_ref,cin1_25 +R 2000,3000,ref_ref,cin1_30 +R 2500,1500,ref_ref,a2_15 +R 2500,2000,ref_ref,a2_20 +R 2500,2500,ref_ref,a2_25 +R 2500,3000,ref_ref,a2_30 +R 3000,1500,ref_ref,b2_15 +R 3000,2000,ref_ref,b2_20 +R 3000,2500,ref_ref,b2_25 +R 3000,3000,ref_ref,b2_30 +R 3500,1500,ref_ref,cout_15 +R 3500,2000,ref_ref,cout_20 +R 3500,2500,ref_ref,cout_25 +R 3500,3000,ref_ref,cout_30 +R 4000,1000,ref_ref,cout_10 +R 5000,1000,ref_ref,sout_10 +R 5000,1500,ref_ref,sout_15 +R 5000,2000,ref_ref,sout_20 +R 5000,2500,ref_ref,sout_25 +R 5000,3000,ref_ref,sout_30 +R 5000,3500,ref_ref,sout_35 +R 6000,1500,ref_ref,a3_15 +R 6000,2000,ref_ref,a3_20 +R 6000,2500,ref_ref,a3_25 +R 6000,3000,ref_ref,a3_30 +R 6500,1500,ref_ref,b3_15 +R 6500,2000,ref_ref,b3_20 +R 6500,2500,ref_ref,b3_25 +R 6500,3000,ref_ref,b3_30 +R 7000,1500,ref_ref,cin2_15 +R 7000,2000,ref_ref,cin2_20 +R 7000,2500,ref_ref,cin2_25 +R 7000,3000,ref_ref,cin2_30 +R 8500,1500,ref_ref,cin3_15 +R 8500,2000,ref_ref,cin3_20 +R 8500,2500,ref_ref,cin3_25 +R 8500,3000,ref_ref,cin3_30 +R 9000,1500,ref_ref,a4_15 +R 9000,2000,ref_ref,a4_20 +R 9000,2500,ref_ref,a4_25 +R 9000,3000,ref_ref,a4_30 +R 9500,1500,ref_ref,b4_15 +R 9500,2000,ref_ref,b4_20 +R 9500,2500,ref_ref,b4_25 +R 9500,3000,ref_ref,b4_30 +R 500,1000,ref_ref,a1_10 +R 500,3500,ref_ref,a1_35 +R 1000,3500,ref_ref,b1_35 +R 9000,3500,ref_ref,a4_35 +R 9500,3500,ref_ref,b4_35 +S 7500,2000,7700,2000,300,*,RIGHT,POLY +S 4100,2500,4300,2500,300,*,LEFT,POLY +S 1700,2500,2000,2500,300,*,LEFT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 3450,1500,4050,1500,200,*,RIGHT,ALU1 +S 4000,1000,4000,1550,200,*,DOWN,ALU1 +S 4000,1000,4000,1500,200,cout,DOWN,CALU1 +S 3500,1500,3500,3000,200,cout,DOWN,CALU1 +S 2000,1500,2000,3000,200,cin1,DOWN,CALU1 +S 2500,1500,2500,3000,200,a2,DOWN,CALU1 +S 3000,1500,3000,3000,200,b2,DOWN,CALU1 +S 5000,1000,5000,3500,200,sout,DOWN,CALU1 +S 6000,1500,6000,3000,200,a3,DOWN,CALU1 +S 6500,1500,6500,3000,200,b3,DOWN,CALU1 +S 7000,1500,7000,3000,200,cin2,DOWN,CALU1 +S 8500,1500,8500,3000,200,cin3,DOWN,CALU1 +S 500,1000,500,3500,200,a1,DOWN,CALU1 +S 1000,1500,1000,3500,200,b1,DOWN,CALU1 +S 9000,1500,9000,3500,200,a4,DOWN,CALU1 +S 9500,1500,9500,3500,200,b4,DOWN,CALU1 +S 5000,1000,5000,3500,200,*,UP,ALU1 +S 1500,3500,4400,3500,100,*,LEFT,ALU1 +S 5600,3500,7500,3500,100,*,RIGHT,ALU1 +S 5600,3500,5600,4000,100,*,DOWN,ALU1 +S 4400,4000,5600,4000,100,*,RIGHT,ALU1 +S 4400,2500,4400,4000,100,*,UP,ALU1 +S 4300,2500,4400,2500,100,*,RIGHT,ALU1 +S 5500,1000,5500,2000,100,*,DOWN,ALU1 +S 8500,1500,8500,3000,100,*,UP,ALU1 +S 7000,1500,7000,3000,100,*,UP,ALU1 +S 6500,1500,6500,3000,100,*,DOWN,ALU1 +S 6000,1500,6000,3000,100,*,DOWN,ALU1 +S 3800,1000,4000,1000,200,*,LEFT,ALU1 +S 3500,1450,3500,3050,200,*,DOWN,ALU1 +S 3450,3000,3800,3000,200,*,LEFT,ALU1 +S 4700,2000,5500,2000,100,*,LEFT,POLY +S 4700,1400,4700,2600,100,*,UP,POLY +S 4100,1400,4100,2600,100,*,UP,POLY +S 5500,1000,7400,1000,100,*,RIGHT,ALU1 +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 5000,300,5000,1200,300,*,UP,NDIF +S 4700,100,4700,1400,100,*,DOWN,NTRANS +S 4100,100,4100,1400,100,*,DOWN,NTRANS +S 4400,300,4400,1200,300,*,UP,NDIF +S 3800,300,3800,1200,300,*,UP,NDIF +S 7500,1500,8000,1500,100,*,RIGHT,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 6400,4000,9700,4000,100,*,RIGHT,ALU1 +S 8000,1000,9100,1000,100,*,RIGHT,ALU1 +S 7500,2000,7500,3500,100,*,UP,ALU1 +S 9700,300,9700,1000,200,*,DOWN,ALU1 +S 8300,2400,8400,2400,100,*,RIGHT,POLY +S 9200,400,9600,400,300,*,RIGHT,PTIE +S 7500,950,7500,1500,100,*,UP,ALU1 +S 8000,1500,8000,3550,100,*,UP,ALU1 +S 0,4700,10000,4700,600,vdd,RIGHT,CALU1 +S 0,300,10000,300,600,vss,RIGHT,CALU1 +S 2900,700,2900,1400,100,*,UP,NTRANS +S 2300,700,2300,1400,100,*,UP,NTRANS +S 1700,700,1700,1400,100,*,UP,NTRANS +S 600,700,600,1500,100,*,UP,NTRANS +S 1400,900,1400,1400,300,*,UP,NDIF +S 2000,900,2000,1200,300,*,UP,NDIF +S 2600,500,2600,1200,300,*,UP,NDIF +S 3200,900,3200,1200,300,*,UP,NDIF +S 2300,1400,2300,1900,100,*,UP,POLY +S 1200,3100,1200,4300,100,*,UP,PTRANS +S 1800,3100,1800,4300,100,*,UP,PTRANS +S 2400,2700,2400,4300,100,*,UP,PTRANS +S 2900,2700,2900,4300,100,*,UP,PTRANS +S 2700,2900,2700,4100,200,*,UP,PDIF +S 3200,2900,3200,4100,300,*,UP,PDIF +S 600,3100,600,4300,100,*,UP,PTRANS +S 900,3300,900,4450,300,*,UP,PDIF +S 2400,1900,2400,2700,100,*,UP,POLY +S 2900,1400,2900,2700,100,*,UP,POLY +S 2100,2900,2100,4100,200,*,UP,PDIF +S 1200,2000,1200,3100,100,*,UP,POLY +S 1100,1600,1100,2000,100,*,UP,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1700,1400,1700,2500,100,*,UP,POLY +S 1700,2500,2000,2500,100,*,RIGHT,POLY +S 1000,2000,1200,2000,100,*,LEFT,POLY +S 600,1500,600,3100,100,*,UP,POLY +S 1100,700,1100,1600,100,*,UP,NTRANS +S 8800,1400,8900,1400,100,*,RIGHT,POLY +S 7100,700,7100,1400,100,*,UP,NTRANS +S 6100,700,6100,1400,100,*,UP,NTRANS +S 6600,700,6600,1400,100,*,UP,NTRANS +S 8800,700,8800,1400,100,*,UP,NTRANS +S 8300,700,8300,1400,100,*,UP,NTRANS +S 9400,700,9400,1400,100,*,UP,NTRANS +S 9700,1000,9700,1200,300,*,UP,NDIF +S 5800,500,5800,1200,300,*,UP,NDIF +S 8300,1400,8300,2400,100,*,UP,POLY +S 6100,3300,6100,4300,100,*,UP,PTRANS +S 6700,3300,6700,4300,100,*,UP,PTRANS +S 7200,3300,7200,4300,100,*,UP,PTRANS +S 5700,3500,5700,4600,400,*,UP,PDIF +S 7800,3100,7800,4300,100,*,UP,PTRANS +S 8400,3100,8400,4100,100,*,UP,PTRANS +S 8900,3100,8900,4100,100,*,UP,PTRANS +S 9400,3100,9400,4100,100,*,UP,PTRANS +S 8700,3300,8700,3900,200,*,UP,PDIF +S 8100,3300,8100,4100,200,*,UP,PDIF +S 7500,3300,7500,4100,300,*,UP,PDIF +S 9700,3300,9700,4000,300,*,UP,PDIF +S 7700,3100,7800,3100,100,*,RIGHT,POLY +S 7100,3300,7200,3300,100,*,RIGHT,POLY +S 6600,3300,6700,3300,100,*,RIGHT,POLY +S 9400,1400,9400,3100,100,*,DOWN,POLY +S 8900,1400,8900,3100,100,*,UP,POLY +S 7100,1400,7100,3300,100,*,UP,POLY +S 6600,1400,6600,3300,100,*,UP,POLY +S 6100,1400,6100,3300,100,*,UP,POLY +S 8400,2500,8400,3100,100,*,DOWN,POLY +S 6400,400,7900,400,300,*,RIGHT,PTIE +S 7600,4700,9200,4700,300,*,RIGHT,NTIE +S 1600,4700,3200,4700,300,*,RIGHT,NTIE +S 0,3900,10000,3900,2400,*,RIGHT,NWELL +S 7700,1500,7700,3100,100,*,UP,POLY +S 7700,700,7700,1500,100,*,UP,NTRANS +S 7400,900,7400,1200,300,*,UP,NDIF +S 300,500,300,1300,300,*,UP,NDIF +S 900,400,2000,400,300,*,RIGHT,PTIE +S 9500,1500,9500,3500,100,*,DOWN,ALU1 +S 9000,1500,9000,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 8550,450,8550,1200,200,*,UP,NDIF +S 6950,3600,6950,4650,200,*,UP,PDIF +S 1500,3300,1500,4100,300,*,UP,PDIF +S 300,3300,300,4100,300,*,UP,PDIF +S 6400,3500,6400,4100,300,*,UP,PDIF +S 8000,900,8000,1200,300,*,UP,NDIF +S 9100,900,9100,1200,300,*,UP,NDIF +V 5700,4500,CONT_DIF_P,* +V 5000,3500,CONT_DIF_P,* +V 4300,2500,CONT_POLY,* +V 5500,2000,CONT_POLY,* +V 5000,3000,CONT_DIF_P,* +V 3800,3000,CONT_DIF_P,* +V 4400,4500,CONT_DIF_P,* +V 4400,500,CONT_DIF_N,* +V 5000,1000,CONT_DIF_N,* +V 3800,1000,CONT_DIF_N,* +V 1400,1000,CONT_DIF_N,* +V 2000,2500,CONT_POLY,* +V 2000,400,CONT_BODY_P,* +V 2500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3200,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 2000,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2600,500,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +V 9000,2500,CONT_POLY,* +V 9500,2000,CONT_POLY,* +V 7500,2000,CONT_POLY,* +V 7000,2000,CONT_POLY,* +V 6500,2000,CONT_POLY,* +V 6000,2000,CONT_POLY,* +V 8500,2500,CONT_POLY,* +V 9200,400,CONT_BODY_P,* +V 9600,400,CONT_BODY_P,* +V 7950,400,CONT_BODY_P,* +V 7400,1000,CONT_DIF_N,* +V 8000,1000,CONT_DIF_N,* +V 9100,1000,CONT_DIF_N,* +V 9700,1000,CONT_DIF_N,* +V 5800,500,CONT_DIF_N,* +V 8100,3500,CONT_DIF_P,* +V 9700,4000,CONT_DIF_P,* +V 6400,4000,CONT_DIF_P,* +V 7500,4000,CONT_DIF_P,* +V 3000,2500,CONT_POLY,* +V 6400,400,CONT_BODY_P,* +V 6900,400,CONT_BODY_P,* +V 7400,400,CONT_BODY_P,* +V 7600,4700,CONT_BODY_N,* +V 8000,4700,CONT_BODY_N,* +V 8400,4700,CONT_BODY_N,* +V 8800,4700,CONT_BODY_N,* +V 9200,4700,CONT_BODY_N,* +V 3200,4700,CONT_BODY_N,* +V 2800,4700,CONT_BODY_N,* +V 2400,4700,CONT_BODY_N,* +V 2000,4700,CONT_BODY_N,* +V 1600,4700,CONT_BODY_N,* +V 300,500,CONT_DIF_N,* +V 1000,400,CONT_BODY_P,* +V 1500,400,CONT_BODY_P,* +V 8550,400,CONT_DIF_N,* +V 6950,4600,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/fulladder_x2.vbe b/pdks/symbolic/sxlib/cells/fulladder_x2.vbe new file mode 100644 index 000000000..1df49a55b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/fulladder_x2.vbe @@ -0,0 +1,121 @@ +ENTITY fulladder_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a1 : NATURAL := 8; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT cin_a3 : NATURAL := 6; + CONSTANT cin_a4 : NATURAL := 6; + CONSTANT cin_b1 : NATURAL := 8; + CONSTANT cin_b2 : NATURAL := 8; + CONSTANT cin_b3 : NATURAL := 6; + CONSTANT cin_b4 : NATURAL := 6; + CONSTANT cin_cin1 : NATURAL := 7; + CONSTANT cin_cin2 : NATURAL := 6; + CONSTANT cin_cin3 : NATURAL := 6; + CONSTANT rdown_a1_cout : NATURAL := 1620; + CONSTANT rdown_a1_sout : NATURAL := 1620; + CONSTANT rdown_a2_cout : NATURAL := 1620; + CONSTANT rdown_a2_sout : NATURAL := 1620; + CONSTANT rdown_a3_sout : NATURAL := 1620; + CONSTANT rdown_a4_sout : NATURAL := 1620; + CONSTANT rdown_b1_cout : NATURAL := 1620; + CONSTANT rdown_b1_sout : NATURAL := 1620; + CONSTANT rdown_b2_cout : NATURAL := 1620; + CONSTANT rdown_b2_sout : NATURAL := 1620; + CONSTANT rdown_b3_sout : NATURAL := 1620; + CONSTANT rdown_b4_sout : NATURAL := 1620; + CONSTANT rdown_cin1_cout : NATURAL := 1620; + CONSTANT rdown_cin1_sout : NATURAL := 1620; + CONSTANT rdown_cin2_sout : NATURAL := 1620; + CONSTANT rdown_cin3_sout : NATURAL := 1620; + CONSTANT rup_a1_cout : NATURAL := 1790; + CONSTANT rup_a1_sout : NATURAL := 1790; + CONSTANT rup_a2_cout : NATURAL := 1790; + CONSTANT rup_a2_sout : NATURAL := 1790; + CONSTANT rup_a3_sout : NATURAL := 1790; + CONSTANT rup_a4_sout : NATURAL := 1790; + CONSTANT rup_b1_cout : NATURAL := 1790; + CONSTANT rup_b1_sout : NATURAL := 1790; + CONSTANT rup_b2_cout : NATURAL := 1790; + CONSTANT rup_b2_sout : NATURAL := 1790; + CONSTANT rup_b3_sout : NATURAL := 1790; + CONSTANT rup_b4_sout : NATURAL := 1790; + CONSTANT rup_cin1_cout : NATURAL := 1790; + CONSTANT rup_cin1_sout : NATURAL := 1790; + CONSTANT rup_cin2_sout : NATURAL := 1790; + CONSTANT rup_cin3_sout : NATURAL := 1790; + CONSTANT tphh_cin3_sout : NATURAL := 489; + CONSTANT tphh_a4_sout : NATURAL := 536; + CONSTANT tphh_b4_sout : NATURAL := 581; + CONSTANT tphh_a2_cout : NATURAL := 658; + CONSTANT tpll_cin1_cout : NATURAL := 694; + CONSTANT tphh_a1_cout : NATURAL := 699; + CONSTANT tpll_b1_cout : NATURAL := 709; + CONSTANT tpll_a1_cout : NATURAL := 736; + CONSTANT tphh_cin1_cout : NATURAL := 742; + CONSTANT tpll_b2_cout : NATURAL := 748; + CONSTANT tphh_b2_cout : NATURAL := 751; + CONSTANT tphh_b1_cout : NATURAL := 777; + CONSTANT tpll_a2_cout : NATURAL := 782; + CONSTANT tpll_cin2_sout : NATURAL := 893; + CONSTANT tphh_a3_sout : NATURAL := 902; + CONSTANT tpll_b3_sout : NATURAL := 951; + CONSTANT tpll_a3_sout : NATURAL := 1008; + CONSTANT tphh_b3_sout : NATURAL := 1014; + CONSTANT tpll_b4_sout : NATURAL := 1071; + CONSTANT tpll_a4_sout : NATURAL := 1114; + CONSTANT tphh_cin2_sout : NATURAL := 1116; + CONSTANT tphl_a2_sout : NATURAL := 1128; + CONSTANT tpll_cin3_sout : NATURAL := 1149; + CONSTANT tplh_cin1_sout : NATURAL := 1163; + CONSTANT tphl_a1_sout : NATURAL := 1169; + CONSTANT tplh_b1_sout : NATURAL := 1178; + CONSTANT tplh_a1_sout : NATURAL := 1205; + CONSTANT tphl_cin1_sout : NATURAL := 1212; + CONSTANT tplh_b2_sout : NATURAL := 1217; + CONSTANT tphl_b2_sout : NATURAL := 1221; + CONSTANT tphl_b1_sout : NATURAL := 1247; + CONSTANT tplh_a2_sout : NATURAL := 1251; + CONSTANT transistors : NATURAL := 28 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + a3 : in BIT; + a4 : in BIT; + b1 : in BIT; + b2 : in BIT; + b3 : in BIT; + b4 : in BIT; + cin1 : in BIT; + cin2 : in BIT; + cin3 : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END fulladder_x2; + +ARCHITECTURE behaviour_data_flow OF fulladder_x2 IS + SIGNAL ncout : BIT; + +BEGIN + ASSERT ((((cin1 and cin2) and cin3) or not (((cin1 or cin2) or cin3))) = '1') + REPORT "cin1, cin2, cin3 must be connected together on fulladder_x2" + SEVERITY WARNING; + ASSERT (((((b1 and b2) and b3) and b4) or not ((((b1 or b2) or b3) or + b4))) = '1') + REPORT "b1, b2, b3, b4 must be connected together on fulladder_x2" + SEVERITY WARNING; + ASSERT (((((a1 and a2) and a3) and a4) or not ((((a1 or a2) or a3) or + a4))) = '1') + REPORT "a1, a2, a3, a4 must be connected together on fulladder_x2" + SEVERITY WARNING; + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on fulladder_x2" + SEVERITY WARNING; + ncout <= not (((a1 and b1) or ((a2 or b2) and cin1))); + sout <= (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) after 1900 ps; + cout <= not (ncout) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/fulladder_x2.vhd b/pdks/symbolic/sxlib/cells/fulladder_x2.vhd new file mode 100644 index 000000000..d9d8f757e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/fulladder_x2.vhd @@ -0,0 +1,34 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY fulladder_x2 IS +PORT( + a1 : IN STD_LOGIC; + a2 : IN STD_LOGIC; + a3 : IN STD_LOGIC; + a4 : IN STD_LOGIC; + b1 : IN STD_LOGIC; + b2 : IN STD_LOGIC; + b3 : IN STD_LOGIC; + b4 : IN STD_LOGIC; + cin1 : IN STD_LOGIC; + cin2 : IN STD_LOGIC; + cin3 : IN STD_LOGIC; + cout : OUT STD_LOGIC; + sout : OUT STD_LOGIC +); +END fulladder_x2; + +ARCHITECTURE RTL OF fulladder_x2 IS + SIGNAL ncout : STD_LOGIC; + +BEGIN + cout <= NOT(ncout); + sout <= (((a3 AND b3) AND cin2) OR (((a4 OR b4) OR cin3) AND ncout)); + ncout <= NOT(((a1 AND b1) OR ((a2 OR b2) AND cin1))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/fulladder_x4.al b/pdks/symbolic/sxlib/cells/fulladder_x4.al new file mode 100644 index 000000000..777242dea --- /dev/null +++ b/pdks/symbolic/sxlib/cells/fulladder_x4.al @@ -0,0 +1,104 @@ +V ALLIANCE : 6 +H fulladder_x4,L,30/10/99 +C a1,UNKNOWN,EXTERNAL,10 +C a2,UNKNOWN,EXTERNAL,9 +C a3,UNKNOWN,EXTERNAL,20 +C a4,UNKNOWN,EXTERNAL,24 +C b1,UNKNOWN,EXTERNAL,7 +C b2,UNKNOWN,EXTERNAL,8 +C b3,UNKNOWN,EXTERNAL,21 +C b4,UNKNOWN,EXTERNAL,23 +C cin1,IN,EXTERNAL,6 +C cin2,IN,EXTERNAL,22 +C cin3,IN,EXTERNAL,19 +C cout,OUT,EXTERNAL,11 +C sout,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,11,3,13,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00032 +T P,0.35,2.6,14,7,13,0,0.75,0.75,6.7,6.7,3.6,11.1,tr_00031 +T P,0.35,2.6,3,6,14,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00030 +T P,0.35,3.8,5,9,3,0,0.75,0.75,9.1,9.1,7.2,10.5,tr_00029 +T P,0.35,3.8,14,8,5,0,0.75,0.75,9.1,9.1,8.7,10.5,tr_00028 +T P,0.35,2.6,13,10,14,0,0.75,0.75,6.7,6.7,1.8,11.1,tr_00027 +T P,0.35,5.9,13,3,11,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00026 +T P,0.35,5.9,13,15,12,0,0.75,0.75,13.3,13.3,17.7,11.25,tr_00025 +T P,0.35,5.9,12,15,13,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00024 +T P,0.35,2,13,21,25,0,0.75,0.75,5.5,5.5,21.6,11.4,tr_00023 +T P,0.35,2,25,22,13,0,0.75,0.75,5.5,5.5,23.1,11.4,tr_00022 +T P,0.35,2,25,23,27,0,0.75,0.75,5.5,5.5,29.7,10.8,tr_00021 +T P,0.35,2,27,24,26,0,0.75,0.75,5.5,5.5,28.2,10.8,tr_00020 +T P,0.35,2,25,20,13,0,0.75,0.75,5.5,5.5,19.8,11.4,tr_00019 +T P,0.35,2.6,15,3,25,0,0.75,0.75,6.7,6.7,24.9,11.1,tr_00018 +T P,0.35,2,26,19,15,0,0.75,0.75,5.5,5.5,26.7,10.8,tr_00017 +T N,0.35,2.9,1,3,11,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00016 +T N,0.35,1.1,2,8,1,0,0.75,0.75,3.7,3.7,8.7,3.15,tr_00015 +T N,0.35,1.1,1,9,2,0,0.75,0.75,3.7,3.7,6.9,3.15,tr_00014 +T N,0.35,1.1,2,6,3,0,0.75,0.75,3.7,3.7,5.1,3.15,tr_00013 +T N,0.35,1.4,4,10,1,0,0.75,0.75,4.3,4.3,1.8,3.3,tr_00012 +T N,0.35,1.7,3,7,4,0,0.75,0.75,4.9,4.9,3.3,3.45,tr_00011 +T N,0.35,2.9,11,3,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00010 +T N,0.35,2.9,12,15,1,0,0.75,0.75,7.3,7.3,17.7,2.25,tr_00009 +T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00008 +T N,0.35,1.4,16,3,15,0,0.75,0.75,4.3,4.3,24.6,3.3,tr_00007 +T N,0.35,1.1,1,23,16,0,0.75,0.75,3.7,3.7,29.7,3.15,tr_00006 +T N,0.35,1.1,15,22,17,0,0.75,0.75,3.7,3.7,22.8,3.15,tr_00005 +T N,0.35,1.1,17,21,18,0,0.75,0.75,3.7,3.7,21.3,3.15,tr_00004 +T N,0.35,1.1,16,24,1,0,0.75,0.75,3.7,3.7,27.9,3.15,tr_00003 +T N,0.35,1.1,1,19,16,0,0.75,0.75,3.7,3.7,26.4,3.15,tr_00002 +T N,0.35,1.1,18,20,1,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00001 +S 27,INTERNAL +Q 0 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0.00250174 +S 24,EXTERNAL,a4 +Q 0.00310499 +S 23,EXTERNAL,b4 +Q 0.00295462 +S 22,EXTERNAL,cin2 +Q 0.00296195 +S 21,EXTERNAL,b3 +Q 0.00296195 +S 20,EXTERNAL,a3 +Q 0.00252972 +S 19,EXTERNAL,cin3 +Q 0.00283471 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0 +S 16,INTERNAL +Q 0.00108534 +S 15,INTERNAL +Q 0.00752047 +S 14,INTERNAL +Q 0.00227626 +S 13,EXTERNAL,vdd +Q 0.010917 +S 12,EXTERNAL,sout +Q 0.00217394 +S 11,EXTERNAL,cout +Q 0.00217394 +S 10,EXTERNAL,a1 +Q 0.00316706 +S 9,EXTERNAL,a2 +Q 0.00262649 +S 8,EXTERNAL,b2 +Q 0.00239514 +S 7,EXTERNAL,b1 +Q 0.00311656 +S 6,EXTERNAL,cin1 +Q 0.00311233 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.0135185 +S 2,INTERNAL +Q 0.00114171 +S 1,EXTERNAL,vss +Q 0.0122096 +EOF diff --git a/pdks/symbolic/sxlib/cells/fulladder_x4.ap b/pdks/symbolic/sxlib/cells/fulladder_x4.ap new file mode 100644 index 000000000..726d5d340 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/fulladder_x4.ap @@ -0,0 +1,284 @@ +V ALLIANCE : 6 +H fulladder_x4,P,18/ 5/2002,100 +A 0,0,10500,5000 +R 500,1500,ref_ref,a1_15 +R 500,2000,ref_ref,a1_20 +R 500,2500,ref_ref,a1_25 +R 500,3000,ref_ref,a1_30 +R 1000,1500,ref_ref,b1_15 +R 1000,2000,ref_ref,b1_20 +R 1000,2500,ref_ref,b1_25 +R 1000,3000,ref_ref,b1_30 +R 2000,1500,ref_ref,cin1_15 +R 2000,2000,ref_ref,cin1_20 +R 2000,2500,ref_ref,cin1_25 +R 2000,3000,ref_ref,cin1_30 +R 2500,1500,ref_ref,a2_15 +R 2500,2000,ref_ref,a2_20 +R 2500,2500,ref_ref,a2_25 +R 2500,3000,ref_ref,a2_30 +R 3000,1500,ref_ref,b2_15 +R 3000,2000,ref_ref,b2_20 +R 3000,2500,ref_ref,b2_25 +R 3000,3000,ref_ref,b2_30 +R 500,1000,ref_ref,a1_10 +R 500,3500,ref_ref,a1_35 +R 1000,3500,ref_ref,b1_35 +R 5500,1500,ref_ref,sout_15 +R 5500,1000,ref_ref,sout_10 +R 5500,3500,ref_ref,sout_35 +R 5500,3000,ref_ref,sout_30 +R 5500,2500,ref_ref,sout_25 +R 5500,2000,ref_ref,sout_20 +R 10000,3000,ref_ref,b4_30 +R 9500,3500,ref_ref,a4_35 +R 9000,2500,ref_ref,cin3_25 +R 9000,3000,ref_ref,cin3_30 +R 9500,1500,ref_ref,a4_15 +R 9500,2000,ref_ref,a4_20 +R 9500,2500,ref_ref,a4_25 +R 9500,3000,ref_ref,a4_30 +R 10000,2000,ref_ref,b4_20 +R 10000,2500,ref_ref,b4_25 +R 7000,2500,ref_ref,b3_25 +R 7000,3000,ref_ref,b3_30 +R 7500,1500,ref_ref,cin2_15 +R 7500,2000,ref_ref,cin2_20 +R 7500,2500,ref_ref,cin2_25 +R 7500,3000,ref_ref,cin2_30 +R 10000,3500,ref_ref,b4_35 +R 9000,2000,ref_ref,cin3_20 +R 7000,1500,ref_ref,b3_15 +R 9000,1500,ref_ref,cin3_15 +R 6500,2000,ref_ref,a3_20 +R 6500,2500,ref_ref,a3_25 +R 6500,3000,ref_ref,a3_30 +R 10000,1500,ref_ref,b4_15 +R 7000,2000,ref_ref,b3_20 +R 4500,1500,ref_ref,cout_15 +R 4500,2000,ref_ref,cout_20 +R 4500,2500,ref_ref,cout_25 +R 4500,3000,ref_ref,cout_30 +R 4500,1000,ref_ref,cout_10 +R 4500,3500,ref_ref,cout_35 +S 8000,2000,8200,2000,300,*,RIGHT,POLY +S 1700,2500,2000,2500,300,*,LEFT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 9050,400,9050,1200,200,*,UP,NDIF +S 7450,3600,7450,4650,200,*,UP,PDIF +S 4100,1400,4100,2600,100,*,UP,POLY +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 4100,100,4100,1400,100,*,DOWN,NTRANS +S 4400,300,4400,1200,300,*,UP,NDIF +S 3800,300,3800,1200,300,*,UP,NDIF +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 2900,700,2900,1400,100,*,UP,NTRANS +S 2300,700,2300,1400,100,*,UP,NTRANS +S 1700,700,1700,1400,100,*,UP,NTRANS +S 600,700,600,1500,100,*,UP,NTRANS +S 1400,900,1400,1400,300,*,UP,NDIF +S 2000,900,2000,1200,300,*,UP,NDIF +S 2600,500,2600,1200,300,*,UP,NDIF +S 3200,900,3200,1200,300,*,UP,NDIF +S 2300,1400,2300,1900,100,*,UP,POLY +S 1200,3100,1200,4300,100,*,UP,PTRANS +S 1800,3100,1800,4300,100,*,UP,PTRANS +S 2400,2700,2400,4300,100,*,UP,PTRANS +S 2900,2700,2900,4300,100,*,UP,PTRANS +S 2700,2900,2700,4100,200,*,UP,PDIF +S 3200,2900,3200,4100,300,*,UP,PDIF +S 600,3100,600,4300,100,*,UP,PTRANS +S 900,3300,900,4450,300,*,UP,PDIF +S 300,3300,300,4050,300,*,UP,PDIF +S 2400,1900,2400,2700,100,*,UP,POLY +S 2900,1400,2900,2700,100,*,UP,POLY +S 2100,2900,2100,4100,200,*,UP,PDIF +S 1200,2000,1200,3100,100,*,UP,POLY +S 1100,1600,1100,2000,100,*,UP,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1700,1400,1700,2500,100,*,UP,POLY +S 1700,2500,2000,2500,100,*,RIGHT,POLY +S 1000,2000,1200,2000,100,*,LEFT,POLY +S 600,1500,600,3100,100,*,UP,POLY +S 1100,700,1100,1600,100,*,UP,NTRANS +S 1600,4700,3200,4700,300,*,RIGHT,NTIE +S 300,500,300,1300,300,*,UP,NDIF +S 900,400,2000,400,300,*,RIGHT,PTIE +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 4700,1400,4700,2600,100,*,UP,POLY +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4700,100,4700,1400,100,*,DOWN,NTRANS +S 5000,300,5000,1200,300,*,UP,NDIF +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 5900,1400,5900,2600,100,*,UP,POLY +S 5300,1400,5300,2600,100,*,UP,POLY +S 5900,100,5900,1400,100,*,DOWN,NTRANS +S 5600,300,5600,1200,300,*,UP,NDIF +S 5300,100,5300,1400,100,*,DOWN,NTRANS +S 6200,300,6200,1200,300,*,UP,NDIF +S 5900,2600,5900,4900,100,*,UP,PTRANS +S 5600,2800,5600,4700,300,*,DOWN,PDIF +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 6200,2800,6200,4700,300,*,DOWN,PDIF +S 10200,300,10200,1000,200,*,DOWN,ALU1 +S 8000,1500,8500,1500,100,*,RIGHT,ALU1 +S 8000,950,8000,1500,100,*,UP,ALU1 +S 8500,1500,8500,3550,100,*,UP,ALU1 +S 6100,3500,8000,3500,100,*,RIGHT,ALU1 +S 6100,3500,6100,4000,100,*,DOWN,ALU1 +S 10000,1500,10000,3500,100,*,DOWN,ALU1 +S 9500,1500,9500,3500,100,*,UP,ALU1 +S 6900,4000,10200,4000,100,*,RIGHT,ALU1 +S 8500,1000,9600,1000,100,*,RIGHT,ALU1 +S 8000,2000,8000,3500,100,*,UP,ALU1 +S 9000,1500,9000,3000,100,*,UP,ALU1 +S 7500,1500,7500,3000,100,*,UP,ALU1 +S 7000,1500,7000,3000,100,*,DOWN,ALU1 +S 7100,3300,7200,3300,100,*,RIGHT,POLY +S 8800,1400,8800,2400,100,*,UP,POLY +S 9900,1400,9900,3100,100,*,DOWN,POLY +S 9400,1400,9400,3100,100,*,UP,POLY +S 7600,1400,7600,3300,100,*,UP,POLY +S 7100,1400,7100,3300,100,*,UP,POLY +S 6600,1400,6600,3300,100,*,UP,POLY +S 8900,2500,8900,3100,100,*,DOWN,POLY +S 8200,1500,8200,3100,100,*,UP,POLY +S 8200,3100,8300,3100,100,*,RIGHT,POLY +S 7600,3300,7700,3300,100,*,RIGHT,POLY +S 9300,1400,9400,1400,100,*,RIGHT,POLY +S 8800,2400,8900,2400,100,*,RIGHT,POLY +S 9700,400,10100,400,300,*,RIGHT,PTIE +S 6900,400,8400,400,300,*,RIGHT,PTIE +S 8200,700,8200,1500,100,*,UP,NTRANS +S 7900,900,7900,1200,300,*,UP,NDIF +S 9900,700,9900,1400,100,*,UP,NTRANS +S 7600,700,7600,1400,100,*,UP,NTRANS +S 10200,1000,10200,1200,300,*,UP,NDIF +S 7100,700,7100,1400,100,*,UP,NTRANS +S 9300,700,9300,1400,100,*,UP,NTRANS +S 8800,700,8800,1400,100,*,UP,NTRANS +S 6600,700,6600,1400,100,*,UP,NTRANS +S 7200,3300,7200,4300,100,*,UP,PTRANS +S 7700,3300,7700,4300,100,*,UP,PTRANS +S 9900,3100,9900,4100,100,*,UP,PTRANS +S 9200,3300,9200,3900,200,*,UP,PDIF +S 9400,3100,9400,4100,100,*,UP,PTRANS +S 6600,3300,6600,4300,100,*,UP,PTRANS +S 8600,3300,8600,4100,200,*,UP,PDIF +S 8000,3300,8000,4100,300,*,UP,PDIF +S 10200,3300,10200,4000,300,*,UP,PDIF +S 8100,4700,9700,4700,300,*,RIGHT,NTIE +S 8300,3100,8300,4300,100,*,UP,PTRANS +S 8900,3100,8900,4100,100,*,UP,PTRANS +S 6300,300,6300,1200,300,*,UP,NDIF +S 6300,3500,6300,4700,300,*,UP,PDIF +S 6500,2000,6500,3000,100,*,DOWN,ALU1 +S 6000,1500,6000,2000,100,*,DOWN,ALU1 +S 6500,1000,7900,1000,100,*,RIGHT,ALU1 +S 6000,1500,6500,1500,100,*,RIGHT,ALU1 +S 6500,1000,6500,1500,100,*,DOWN,ALU1 +S 5500,950,5500,3550,200,*,UP,ALU1 +S 1500,3500,3800,3500,100,*,LEFT,ALU1 +S 3800,2000,3800,4000,100,*,UP,ALU1 +S 3800,2000,3900,2000,100,*,RIGHT,ALU1 +S 4500,950,4500,3550,200,*,UP,ALU1 +S 3800,4000,6100,4000,100,*,RIGHT,ALU1 +S 3800,500,3800,1000,200,*,UP,ALU1 +S 0,300,10500,300,600,vss,RIGHT,CALU1 +S 0,3900,10500,3900,2400,*,RIGHT,NWELL +S 0,4700,10500,4700,600,vdd,RIGHT,CALU1 +S 3900,2000,4700,2000,300,*,RIGHT,POLY +S 5300,2000,6000,2000,300,*,LEFT,POLY +S 500,1000,500,3500,200,a1,DOWN,CALU1 +S 1000,1500,1000,3500,200,b1,DOWN,CALU1 +S 2000,1500,2000,3000,200,cin1,DOWN,CALU1 +S 2500,1500,2500,3000,200,a2,DOWN,CALU1 +S 3000,1500,3000,3000,200,b2,DOWN,CALU1 +S 5500,1000,5500,3500,200,sout,DOWN,CALU1 +S 10000,1500,10000,3500,200,b4,DOWN,CALU1 +S 9500,1500,9500,3500,200,a4,DOWN,CALU1 +S 9000,1500,9000,3000,200,cin3,DOWN,CALU1 +S 7000,1500,7000,3000,200,b3,DOWN,CALU1 +S 7500,1500,7500,3000,200,cin2,DOWN,CALU1 +S 6500,2000,6500,3000,200,a3,DOWN,CALU1 +S 4500,1000,4500,3500,200,cout,DOWN,CALU1 +S 1500,3300,1500,4100,300,*,UP,PDIF +S 6900,3500,6900,4100,300,*,UP,PDIF +S 8500,900,8500,1200,300,*,UP,NDIF +S 9600,900,9600,1200,300,*,UP,NDIF +V 9050,400,CONT_DIF_N,* +V 7450,4600,CONT_DIF_P,* +V 1400,1000,CONT_DIF_N,* +V 2000,2500,CONT_POLY,* +V 2000,400,CONT_BODY_P,* +V 2500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3200,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 2000,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2600,500,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +V 3000,2500,CONT_POLY,* +V 3200,4700,CONT_BODY_N,* +V 2800,4700,CONT_BODY_N,* +V 2400,4700,CONT_BODY_N,* +V 2000,4700,CONT_BODY_N,* +V 1600,4700,CONT_BODY_N,* +V 300,500,CONT_DIF_N,* +V 1000,400,CONT_BODY_P,* +V 1500,400,CONT_BODY_P,* +V 3800,4500,CONT_DIF_P,* +V 5000,4500,CONT_DIF_P,* +V 6200,4500,CONT_DIF_P,* +V 3800,500,CONT_DIF_N,* +V 5000,500,CONT_DIF_N,* +V 6200,500,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +V 5600,3500,CONT_DIF_P,* +V 5600,3000,CONT_DIF_P,* +V 6000,2000,CONT_POLY,* +V 8000,2000,CONT_POLY,* +V 7500,2000,CONT_POLY,* +V 7000,2000,CONT_POLY,* +V 6500,2000,CONT_POLY,* +V 9000,2500,CONT_POLY,* +V 9500,2500,CONT_POLY,* +V 10000,2000,CONT_POLY,* +V 7400,400,CONT_BODY_P,* +V 7900,400,CONT_BODY_P,* +V 9700,400,CONT_BODY_P,* +V 10100,400,CONT_BODY_P,* +V 8450,400,CONT_BODY_P,* +V 6900,400,CONT_BODY_P,* +V 8500,1000,CONT_DIF_N,* +V 9600,1000,CONT_DIF_N,* +V 10200,1000,CONT_DIF_N,* +V 7900,1000,CONT_DIF_N,* +V 9700,4700,CONT_BODY_N,* +V 6900,4000,CONT_DIF_P,* +V 8000,4000,CONT_DIF_P,* +V 8100,4700,CONT_BODY_N,* +V 8500,4700,CONT_BODY_N,* +V 8900,4700,CONT_BODY_N,* +V 9300,4700,CONT_BODY_N,* +V 8600,3500,CONT_DIF_P,* +V 10200,4000,CONT_DIF_P,* +V 3900,2000,CONT_POLY,* +V 4400,1000,CONT_DIF_N,* +V 4400,3000,CONT_DIF_P,* +V 4400,3500,CONT_DIF_P,* +V 3800,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/fulladder_x4.vbe b/pdks/symbolic/sxlib/cells/fulladder_x4.vbe new file mode 100644 index 000000000..8c5b56589 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/fulladder_x4.vbe @@ -0,0 +1,121 @@ +ENTITY fulladder_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 5250; + CONSTANT cin_a1 : NATURAL := 8; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT cin_a3 : NATURAL := 6; + CONSTANT cin_a4 : NATURAL := 6; + CONSTANT cin_b1 : NATURAL := 8; + CONSTANT cin_b2 : NATURAL := 8; + CONSTANT cin_b3 : NATURAL := 6; + CONSTANT cin_b4 : NATURAL := 6; + CONSTANT cin_cin1 : NATURAL := 7; + CONSTANT cin_cin2 : NATURAL := 6; + CONSTANT cin_cin3 : NATURAL := 6; + CONSTANT rdown_a1_cout : NATURAL := 810; + CONSTANT rdown_a1_sout : NATURAL := 810; + CONSTANT rdown_a2_cout : NATURAL := 810; + CONSTANT rdown_a2_sout : NATURAL := 810; + CONSTANT rdown_a3_sout : NATURAL := 810; + CONSTANT rdown_a4_sout : NATURAL := 810; + CONSTANT rdown_b1_cout : NATURAL := 810; + CONSTANT rdown_b1_sout : NATURAL := 810; + CONSTANT rdown_b2_cout : NATURAL := 810; + CONSTANT rdown_b2_sout : NATURAL := 810; + CONSTANT rdown_b3_sout : NATURAL := 810; + CONSTANT rdown_b4_sout : NATURAL := 810; + CONSTANT rdown_cin1_cout : NATURAL := 810; + CONSTANT rdown_cin1_sout : NATURAL := 810; + CONSTANT rdown_cin2_sout : NATURAL := 810; + CONSTANT rdown_cin3_sout : NATURAL := 810; + CONSTANT rup_a1_cout : NATURAL := 890; + CONSTANT rup_a1_sout : NATURAL := 890; + CONSTANT rup_a2_cout : NATURAL := 890; + CONSTANT rup_a2_sout : NATURAL := 890; + CONSTANT rup_a3_sout : NATURAL := 890; + CONSTANT rup_a4_sout : NATURAL := 890; + CONSTANT rup_b1_cout : NATURAL := 890; + CONSTANT rup_b1_sout : NATURAL := 890; + CONSTANT rup_b2_cout : NATURAL := 890; + CONSTANT rup_b2_sout : NATURAL := 890; + CONSTANT rup_b3_sout : NATURAL := 890; + CONSTANT rup_b4_sout : NATURAL := 890; + CONSTANT rup_cin1_cout : NATURAL := 890; + CONSTANT rup_cin1_sout : NATURAL := 890; + CONSTANT rup_cin2_sout : NATURAL := 890; + CONSTANT rup_cin3_sout : NATURAL := 890; + CONSTANT tphh_cin3_sout : NATURAL := 630; + CONSTANT tphh_a4_sout : NATURAL := 673; + CONSTANT tphh_b4_sout : NATURAL := 715; + CONSTANT tphh_a1_cout : NATURAL := 800; + CONSTANT tphh_a2_cout : NATURAL := 801; + CONSTANT tpll_cin1_cout : NATURAL := 830; + CONSTANT tpll_b1_cout : NATURAL := 839; + CONSTANT tpll_a1_cout : NATURAL := 866; + CONSTANT tpll_b2_cout : NATURAL := 883; + CONSTANT tphh_b1_cout : NATURAL := 884; + CONSTANT tphh_b2_cout : NATURAL := 892; + CONSTANT tphh_cin1_cout : NATURAL := 899; + CONSTANT tpll_a2_cout : NATURAL := 924; + CONSTANT tphh_a3_sout : NATURAL := 1086; + CONSTANT tpll_cin2_sout : NATURAL := 1150; + CONSTANT tphh_b3_sout : NATURAL := 1202; + CONSTANT tpll_b3_sout : NATURAL := 1208; + CONSTANT tpll_a3_sout : NATURAL := 1265; + CONSTANT tphh_cin2_sout : NATURAL := 1308; + CONSTANT tpll_b4_sout : NATURAL := 1329; + CONSTANT tpll_a4_sout : NATURAL := 1377; + CONSTANT tpll_cin3_sout : NATURAL := 1417; + CONSTANT tphl_a1_sout : NATURAL := 1471; + CONSTANT tphl_a2_sout : NATURAL := 1472; + CONSTANT tplh_cin1_sout : NATURAL := 1492; + CONSTANT tplh_b1_sout : NATURAL := 1501; + CONSTANT tplh_a1_sout : NATURAL := 1528; + CONSTANT tplh_b2_sout : NATURAL := 1545; + CONSTANT tphl_b1_sout : NATURAL := 1555; + CONSTANT tphl_b2_sout : NATURAL := 1563; + CONSTANT tphl_cin1_sout : NATURAL := 1570; + CONSTANT tplh_a2_sout : NATURAL := 1586; + CONSTANT transistors : NATURAL := 32 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + a3 : in BIT; + a4 : in BIT; + b1 : in BIT; + b2 : in BIT; + b3 : in BIT; + b4 : in BIT; + cin1 : in BIT; + cin2 : in BIT; + cin3 : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END fulladder_x4; + +ARCHITECTURE behaviour_data_flow OF fulladder_x4 IS + SIGNAL ncout : BIT; + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on fulladder_x4" + SEVERITY WARNING; + ASSERT (((((a1 and a2) and a3) and a4) or not ((((a1 or a2) or a3) or + a4))) = '1') + REPORT "a1, a2, a3, a4 must be connected together on fulladder_x4" + SEVERITY WARNING; + ASSERT (((((b1 and b2) and b3) and b4) or not ((((b1 or b2) or b3) or + b4))) = '1') + REPORT "b1, b2, b3, b4 must be connected together on fulladder_x4" + SEVERITY WARNING; + ASSERT ((((cin1 and cin2) and cin3) or not (((cin1 or cin2) or cin3))) = '1') + REPORT "cin1, cin2, cin3 must be connected together on fulladder_x4" + SEVERITY WARNING; + ncout <= not (((a1 and b1) or ((a2 or b2) and cin1))); + sout <= (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) after 2200 ps; + cout <= not (ncout) after 1500 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/fulladder_x4.vhd b/pdks/symbolic/sxlib/cells/fulladder_x4.vhd new file mode 100644 index 000000000..73aa48a2f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/fulladder_x4.vhd @@ -0,0 +1,34 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY fulladder_x4 IS +PORT( + a1 : IN STD_LOGIC; + a2 : IN STD_LOGIC; + a3 : IN STD_LOGIC; + a4 : IN STD_LOGIC; + b1 : IN STD_LOGIC; + b2 : IN STD_LOGIC; + b3 : IN STD_LOGIC; + b4 : IN STD_LOGIC; + cin1 : IN STD_LOGIC; + cin2 : IN STD_LOGIC; + cin3 : IN STD_LOGIC; + cout : OUT STD_LOGIC; + sout : OUT STD_LOGIC +); +END fulladder_x4; + +ARCHITECTURE RTL OF fulladder_x4 IS + SIGNAL ncout : STD_LOGIC; + +BEGIN + cout <= NOT(ncout); + sout <= (((a3 AND b3) AND cin2) OR (((a4 OR b4) OR cin3) AND ncout)); + ncout <= NOT(((a1 AND b1) OR ((a2 OR b2) AND cin1))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/halfadder_x2.al b/pdks/symbolic/sxlib/cells/halfadder_x2.al new file mode 100644 index 000000000..fab1b2635 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/halfadder_x2.al @@ -0,0 +1,57 @@ +V ALLIANCE : 6 +H halfadder_x2,L,30/10/99 +C a,UNKNOWN,EXTERNAL,7 +C b,UNKNOWN,EXTERNAL,8 +C cout,OUT,EXTERNAL,4 +C sout,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,3 +T P,0.35,2.6,6,7,1,0,0.75,0.75,6.7,6.7,3.9,11.1,tr_00020 +T P,0.35,5.9,14,9,6,0,0.75,0.75,13.3,13.3,21.9,11.25,tr_00019 +T P,0.35,5.9,4,1,6,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00018 +T P,0.35,3.2,12,8,6,0,0.75,0.75,7.9,7.9,11.1,9.9,tr_00017 +T P,0.35,3.2,6,13,12,0,0.75,0.75,7.9,7.9,16.5,9.9,tr_00016 +T P,0.35,3.2,12,5,9,0,0.75,0.75,7.9,7.9,14.7,9.9,tr_00015 +T P,0.35,3.2,9,7,12,0,0.75,0.75,7.9,7.9,12.9,9.9,tr_00014 +T P,0.35,2.6,1,8,6,0,0.75,0.75,6.7,6.7,5.7,11.1,tr_00013 +T P,0.35,2.3,6,8,5,0,0.75,0.75,6.1,6.1,9.3,9.45,tr_00012 +T P,0.35,3.2,13,7,6,0,0.75,0.75,7.9,7.9,18.3,9.9,tr_00011 +T N,0.35,2.9,3,9,14,0,0.75,0.75,7.3,7.3,21.9,2.25,tr_00010 +T N,0.35,2.9,3,1,4,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00009 +T N,0.35,1.4,3,8,11,0,0.75,0.75,4.3,4.3,11.1,3,tr_00008 +T N,0.35,2,1,8,2,0,0.75,0.75,5.5,5.5,5.7,3.3,tr_00007 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,3.9,3,tr_00006 +T N,0.35,1.7,9,5,10,0,0.75,0.75,4.9,4.9,14.7,3.15,tr_00005 +T N,0.35,1.4,10,7,3,0,0.75,0.75,4.3,4.3,16.5,3,tr_00004 +T N,0.35,1.1,3,7,13,0,0.75,0.75,3.7,3.7,18.3,3.15,tr_00003 +T N,0.35,1.7,11,13,9,0,0.75,0.75,4.9,4.9,12.9,3.15,tr_00002 +T N,0.35,1.1,5,8,3,0,0.75,0.75,3.7,3.7,9.3,3.15,tr_00001 +S 14,EXTERNAL,sout +Q 0.00258522 +S 13,INTERNAL +Q 0.00530432 +S 12,INTERNAL +Q 0.00171257 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.0062563 +S 8,EXTERNAL,b +Q 0.0069823 +S 7,EXTERNAL,a +Q 0.0115667 +S 6,EXTERNAL,vdd +Q 0.00938587 +S 5,INTERNAL +Q 0.00442919 +S 4,EXTERNAL,cout +Q 0.00258522 +S 3,EXTERNAL,vss +Q 0.00832828 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00435733 +EOF diff --git a/pdks/symbolic/sxlib/cells/halfadder_x2.ap b/pdks/symbolic/sxlib/cells/halfadder_x2.ap new file mode 100644 index 000000000..209681eb8 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/halfadder_x2.ap @@ -0,0 +1,188 @@ +V ALLIANCE : 6 +H halfadder_x2,P, 8/ 6/2002,100 +A 0,0,8000,5000 +R 7500,2500,ref_ref,sout_25 +R 7500,2000,ref_ref,sout_20 +R 7500,1500,ref_ref,sout_15 +R 3500,1500,ref_ref,b_15 +R 3500,2000,ref_ref,b_20 +R 3500,2500,ref_ref,b_25 +R 3500,3000,ref_ref,b_30 +R 7500,4000,ref_ref,sout_40 +R 7500,1000,ref_ref,sout_10 +R 7500,3000,ref_ref,sout_30 +R 7500,3500,ref_ref,sout_35 +R 1000,3500,ref_ref,a_35 +R 1000,4000,ref_ref,a_40 +R 1000,1000,ref_ref,a_10 +R 1000,1500,ref_ref,a_15 +R 1000,2500,ref_ref,a_25 +R 1000,2000,ref_ref,a_20 +R 3500,3500,ref_ref,b_35 +R 3500,1000,ref_ref,b_10 +R 500,4000,ref_ref,cout_40 +R 500,1000,ref_ref,cout_10 +R 500,3000,ref_ref,cout_30 +R 500,3500,ref_ref,cout_35 +R 500,2500,ref_ref,cout_25 +R 500,2000,ref_ref,cout_20 +R 500,1500,ref_ref,cout_15 +R 1000,3000,ref_ref,a_30 +S 6400,4300,6400,4800,300,*,DOWN,NTIE +S 2800,4300,2800,4800,300,*,DOWN,NTIE +S 7500,1000,7500,4000,200,*,DOWN,ALU1 +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 5200,2800,5200,3800,300,*,DOWN,PDIF +S 3400,2800,3400,4500,300,*,DOWN,PDIF +S 5800,2800,5800,4500,300,*,DOWN,PDIF +S 2800,2800,2800,3500,300,*,UP,PDIF +S 6400,2800,6400,3800,300,*,DOWN,PDIF +S 6100,2600,6100,4000,100,*,UP,PTRANS +S 3100,2600,3100,3700,100,*,UP,PTRANS +S 0,3900,8000,3900,2400,*,LEFT,NWELL +S 1900,3100,1900,4300,100,*,DOWN,PTRANS +S 1600,3300,1600,4100,300,*,UP,PDIF +S 4300,2600,4300,4000,100,*,UP,PTRANS +S 4900,2600,4900,4000,100,*,UP,PTRANS +S 5500,2600,5500,4000,100,*,UP,PTRANS +S 3700,2600,3700,4000,100,*,UP,PTRANS +S 4000,2800,4000,3800,300,*,DOWN,PDIF +S 4600,2800,4600,3800,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,DOWN,PTRANS +S 2200,3300,2200,4600,300,*,UP,PDIF +S 400,2800,400,4700,300,*,UP,PDIF +S 1000,2800,1000,4700,300,*,UP,PDIF +S 7000,3400,7000,4700,300,*,DOWN,PDIF +S 7600,2800,7600,4700,300,*,DOWN,PDIF +S 7300,2600,7300,4900,100,*,UP,PTRANS +S 1300,3100,1300,4300,100,*,DOWN,PTRANS +S 3100,700,3100,1400,100,*,DOWN,NTRANS +S 4300,600,4300,1500,100,*,DOWN,NTRANS +S 4600,800,4600,1300,300,*,UP,NDIF +S 4000,800,4000,1300,300,*,UP,NDIF +S 5200,800,5200,1300,300,*,UP,NDIF +S 6100,700,6100,1400,100,*,DOWN,NTRANS +S 6400,900,6400,1600,300,*,UP,NDIF +S 5500,600,5500,1400,100,*,DOWN,NTRANS +S 2800,1000,2800,1200,300,*,UP,NDIF +S 3400,400,3400,1200,300,*,UP,NDIF +S 5800,400,5800,1200,300,*,UP,NDIF +S 4900,600,4900,1500,100,*,DOWN,NTRANS +S 1300,600,1300,1400,100,*,UP,NTRANS +S 1900,600,1900,1600,100,*,UP,NTRANS +S 2200,800,2200,1400,300,*,DOWN,NDIF +S 1600,800,1600,1400,300,*,DOWN,NDIF +S 3700,600,3700,1400,100,*,DOWN,NTRANS +S 1000,300,1000,1200,300,*,DOWN,NDIF +S 400,300,400,1200,300,*,DOWN,NDIF +S 700,100,700,1400,100,*,UP,NTRANS +S 7000,300,7000,1000,300,*,UP,NDIF +S 7600,300,7600,1200,300,*,UP,NDIF +S 7300,100,7300,1400,100,*,DOWN,NTRANS +S 4900,1500,4900,2600,100,*,DOWN,POLY +S 7000,2000,7300,2000,300,*,RIGHT,POLY +S 4300,1500,4600,1500,100,*,RIGHT,POLY +S 7300,1400,7300,2600,100,*,DOWN,POLY +S 1900,2000,2000,2000,100,*,RIGHT,POLY +S 1900,1600,1900,2000,100,*,UP,POLY +S 1000,2500,1300,2500,300,*,RIGHT,POLY +S 3100,2600,3700,2600,100,*,RIGHT,POLY +S 3100,1400,3700,1400,100,*,RIGHT,POLY +S 2800,2000,4900,2000,100,*,RIGHT,POLY +S 5500,1400,6100,1400,100,*,RIGHT,POLY +S 5500,2000,5500,2600,100,*,DOWN,POLY +S 5500,2000,6500,2000,100,*,RIGHT,POLY +S 4300,2600,4600,2600,100,*,RIGHT,POLY +S 1000,1500,1300,1500,300,*,RIGHT,POLY +S 700,2000,1500,2000,100,*,RIGHT,POLY +S 1300,2400,1300,3100,100,*,UP,POLY +S 700,1400,700,2600,100,*,DOWN,POLY +S 0,300,8000,300,600,vss,RIGHT,CALU1 +S 5000,1600,5000,2000,100,*,DOWN,ALU1 +S 0,4700,8000,4700,600,vdd,RIGHT,CALU1 +S 7000,1000,7000,2000,100,*,DOWN,ALU1 +S 7000,3500,7000,4500,200,*,DOWN,ALU1 +S 6000,1500,6000,4000,100,*,DOWN,ALU1 +S 6500,1500,6500,2900,100,*,DOWN,ALU1 +S 2100,3500,3500,3500,100,*,RIGHT,ALU1 +S 2100,3000,2100,3500,100,*,DOWN,ALU1 +S 2000,3000,2100,3000,100,*,LEFT,ALU1 +S 4500,1600,5000,1600,100,*,RIGHT,ALU1 +S 5200,3000,5200,3500,100,*,DOWN,ALU1 +S 2800,1000,2800,3000,100,*,DOWN,ALU1 +S 4000,3000,4600,3000,100,*,LEFT,ALU1 +S 4000,1000,4000,3000,100,*,UP,ALU1 +S 5000,2000,5500,2000,100,*,RIGHT,ALU1 +S 4500,2500,6000,2500,100,*,RIGHT,ALU1 +S 4000,1000,7000,1000,100,*,RIGHT,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1550,1000,1550,3500,100,*,UP,ALU1 +S 1000,4000,6000,4000,100,*,RIGHT,ALU1 +S 1550,1000,2200,1000,100,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 3500,1000,3500,3500,100,*,UP,ALU1 +S 4000,3500,5200,3500,100,*,RIGHT,ALU1 +S 7500,1000,7500,4000,200,sout,DOWN,CALU1 +S 3500,1000,3500,3500,200,b,DOWN,CALU1 +S 1000,1000,1000,4000,200,a,DOWN,CALU1 +S 500,1000,500,4000,200,cout,DOWN,CALU1 +S 3900,4700,5300,4700,300,*,RIGHT,NTIE +S 1500,300,2900,300,300,*,RIGHT,PTIE +S 3900,300,5300,300,300,*,RIGHT,PTIE +V 4000,4700,CONT_BODY_N,* +V 5200,4700,CONT_BODY_N,* +V 7000,3500,CONT_DIF_P,* +V 2800,3000,CONT_DIF_P,* +V 6500,2900,CONT_DIF_P,* +V 7600,3000,CONT_DIF_P,* +V 7600,3500,CONT_DIF_P,* +V 7600,4000,CONT_DIF_P,* +V 7000,4500,CONT_DIF_P,* +V 4600,4700,CONT_BODY_N,* +V 4600,3000,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 5800,4500,CONT_DIF_P,* +V 2800,4700,CONT_BODY_N,* +V 6400,4700,CONT_BODY_N,* +V 4000,3500,CONT_DIF_P,* +V 5200,3500,CONT_DIF_P,* +V 7000,4000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +V 2200,4500,CONT_DIF_P,* +V 1600,3500,CONT_DIF_P,* +V 400,4000,CONT_DIF_P,* +V 1000,4500,CONT_DIF_P,* +V 5200,3000,CONT_DIF_P,* +V 7600,1000,CONT_DIF_N,* +V 7000,500,CONT_DIF_N,* +V 4600,1100,CONT_DIF_N,* +V 1000,500,CONT_DIF_N,* +V 2200,1000,CONT_DIF_N,* +V 400,1000,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 5800,500,CONT_DIF_N,* +V 6500,1500,CONT_DIF_N,* +V 2200,300,CONT_BODY_P,* +V 2800,300,CONT_BODY_P,* +V 4600,300,CONT_BODY_P,* +V 5200,300,CONT_BODY_P,* +V 4000,300,CONT_BODY_P,* +V 1600,300,CONT_BODY_P,* +V 7000,2000,CONT_POLY,* +V 5500,2000,CONT_POLY,* +V 6500,2000,CONT_POLY,* +V 6000,2500,CONT_POLY,* +V 4500,1600,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1100,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 6000,1500,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2800,2000,CONT_POLY,* +V 2000,3000,CONT_POLY,* +V 1100,1500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/halfadder_x2.vbe b/pdks/symbolic/sxlib/cells/halfadder_x2.vbe new file mode 100644 index 000000000..da1482b2e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/halfadder_x2.vbe @@ -0,0 +1,46 @@ +ENTITY halfadder_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 27; + CONSTANT cin_b : NATURAL := 22; + CONSTANT rdown_a_cout : NATURAL := 1620; + CONSTANT rdown_a_sout : NATURAL := 1620; + CONSTANT rdown_b_cout : NATURAL := 1620; + CONSTANT rdown_b_sout : NATURAL := 1620; + CONSTANT rup_a_cout : NATURAL := 1790; + CONSTANT rup_a_sout : NATURAL := 1790; + CONSTANT rup_b_cout : NATURAL := 1790; + CONSTANT rup_b_sout : NATURAL := 1790; + CONSTANT tphh_a_cout : NATURAL := 361; + CONSTANT tpll_b_cout : NATURAL := 383; + CONSTANT tphh_b_cout : NATURAL := 386; + CONSTANT tpll_a_cout : NATURAL := 398; + CONSTANT tphh_a_sout : NATURAL := 421; + CONSTANT tpll_b_sout : NATURAL := 497; + CONSTANT tphl_b_sout : NATURAL := 531; + CONSTANT tplh_b_sout : NATURAL := 556; + CONSTANT tphh_b_sout : NATURAL := 558; + CONSTANT tpll_a_sout : NATURAL := 562; + CONSTANT tphl_a_sout : NATURAL := 575; + CONSTANT tplh_a_sout : NATURAL := 607; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + a : in BIT; + b : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END halfadder_x2; + +ARCHITECTURE behaviour_data_flow OF halfadder_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on halfadder_x2" + SEVERITY WARNING; + sout <= (a xor b) after 1200 ps; + cout <= (a and b) after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/halfadder_x2.vhd b/pdks/symbolic/sxlib/cells/halfadder_x2.vhd new file mode 100644 index 000000000..9ca385304 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/halfadder_x2.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY halfadder_x2 IS +PORT( + a : IN STD_LOGIC; + b : IN STD_LOGIC; + cout : OUT STD_LOGIC; + sout : OUT STD_LOGIC +); +END halfadder_x2; + +ARCHITECTURE RTL OF halfadder_x2 IS +BEGIN + cout <= (a AND b); + sout <= (a XOR b); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/halfadder_x4.al b/pdks/symbolic/sxlib/cells/halfadder_x4.al new file mode 100644 index 000000000..4d1b8f272 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/halfadder_x4.al @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H halfadder_x4,L,30/10/99 +C a,UNKNOWN,EXTERNAL,6 +C b,UNKNOWN,EXTERNAL,7 +C cout,OUT,EXTERNAL,1 +C sout,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,4,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00024 +T P,0.35,5.9,1,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00023 +T P,0.35,5.9,5,9,14,0,0.75,0.75,13.3,13.3,25.2,11.25,tr_00022 +T P,0.35,5.9,14,9,5,0,0.75,0.75,13.3,13.3,23.4,11.25,tr_00021 +T P,0.35,2.6,5,6,4,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00020 +T P,0.35,2.6,4,7,5,0,0.75,0.75,6.7,6.7,7.2,11.1,tr_00019 +T P,0.35,3.2,9,6,12,0,0.75,0.75,7.9,7.9,14.4,9.9,tr_00018 +T P,0.35,3.2,12,11,9,0,0.75,0.75,7.9,7.9,16.2,9.9,tr_00017 +T P,0.35,3.2,5,13,12,0,0.75,0.75,7.9,7.9,18,9.9,tr_00016 +T P,0.35,3.2,12,7,5,0,0.75,0.75,7.9,7.9,12.6,9.9,tr_00015 +T P,0.35,3.2,13,6,5,0,0.75,0.75,7.9,7.9,19.8,9.9,tr_00014 +T P,0.35,2.3,5,7,11,0,0.75,0.75,6.1,6.1,10.8,9.45,tr_00013 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00012 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00011 +T N,0.35,2.9,14,9,2,0,0.75,0.75,7.3,7.3,25.2,2.25,tr_00010 +T N,0.35,2.9,2,9,14,0,0.75,0.75,7.3,7.3,23.4,2.25,tr_00009 +T N,0.35,1.4,3,6,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00008 +T N,0.35,2,4,7,3,0,0.75,0.75,5.5,5.5,7.2,3.3,tr_00007 +T N,0.35,1.4,2,7,8,0,0.75,0.75,4.3,4.3,12.6,3,tr_00006 +T N,0.35,1.4,10,6,2,0,0.75,0.75,4.3,4.3,18,3,tr_00005 +T N,0.35,1.7,9,11,10,0,0.75,0.75,4.9,4.9,16.2,3.15,tr_00004 +T N,0.35,1.7,8,13,9,0,0.75,0.75,4.9,4.9,14.4,3.15,tr_00003 +T N,0.35,1.1,2,6,13,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00002 +T N,0.35,1.1,11,7,2,0,0.75,0.75,3.7,3.7,10.8,3.15,tr_00001 +S 14,EXTERNAL,sout +Q 0.00258522 +S 13,INTERNAL +Q 0.00530431 +S 12,INTERNAL +Q 0.00171257 +S 11,INTERNAL +Q 0.00442919 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.00752047 +S 8,INTERNAL +Q 0 +S 7,EXTERNAL,b +Q 0.0069823 +S 6,EXTERNAL,a +Q 0.0115667 +S 5,EXTERNAL,vdd +Q 0.0134766 +S 4,INTERNAL +Q 0.00589885 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.011949 +S 1,EXTERNAL,cout +Q 0.00258522 +EOF diff --git a/pdks/symbolic/sxlib/cells/halfadder_x4.ap b/pdks/symbolic/sxlib/cells/halfadder_x4.ap new file mode 100644 index 000000000..c43b84c43 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/halfadder_x4.ap @@ -0,0 +1,215 @@ +V ALLIANCE : 6 +H halfadder_x4,P, 8/ 6/2002,100 +A 0,0,9000,5000 +R 8000,1500,ref_ref,sout_15 +R 8000,2000,ref_ref,sout_20 +R 8000,2500,ref_ref,sout_25 +R 8000,3500,ref_ref,sout_35 +R 8000,3000,ref_ref,sout_30 +R 8000,1000,ref_ref,sout_10 +R 8000,4000,ref_ref,sout_40 +R 4000,3000,ref_ref,b_30 +R 4000,2500,ref_ref,b_25 +R 4000,2000,ref_ref,b_20 +R 4000,1500,ref_ref,b_15 +R 4000,1000,ref_ref,b_10 +R 4000,3500,ref_ref,b_35 +R 1500,2000,ref_ref,a_20 +R 1500,2500,ref_ref,a_25 +R 1500,1500,ref_ref,a_15 +R 1500,1000,ref_ref,a_10 +R 1500,4000,ref_ref,a_40 +R 1500,3500,ref_ref,a_35 +R 1500,3000,ref_ref,a_30 +R 1000,1500,ref_ref,cout_15 +R 1000,2000,ref_ref,cout_20 +R 1000,2500,ref_ref,cout_25 +R 1000,3500,ref_ref,cout_35 +R 1000,3000,ref_ref,cout_30 +R 1000,1000,ref_ref,cout_10 +R 1000,4000,ref_ref,cout_40 +S 6900,4300,6900,4800,300,*,DOWN,NTIE +S 3300,4300,3300,4800,300,*,DOWN,NTIE +S 4400,300,5800,300,300,*,RIGHT,PTIE +S 2000,300,3400,300,300,*,RIGHT,PTIE +S 4400,4700,5800,4700,300,*,RIGHT,NTIE +S 8000,1000,8000,4000,200,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 3600,2600,3600,3700,100,*,UP,PTRANS +S 3600,700,3600,1400,100,*,DOWN,NTRANS +S 6600,2600,6600,4000,100,*,UP,PTRANS +S 6900,2800,6900,3800,300,*,DOWN,PDIF +S 3300,2800,3300,3500,300,*,UP,PDIF +S 6900,900,6900,1600,300,*,UP,NDIF +S 6600,700,6600,1400,100,*,DOWN,NTRANS +S 5400,1500,5400,2600,100,*,DOWN,POLY +S 0,3900,9000,3900,2400,*,LEFT,NWELL +S 6300,2800,6300,4500,300,*,DOWN,PDIF +S 3900,2800,3900,4500,300,*,DOWN,PDIF +S 5700,2800,5700,3800,300,*,DOWN,PDIF +S 5100,2800,5100,3800,300,*,DOWN,PDIF +S 4500,2800,4500,3800,300,*,DOWN,PDIF +S 5500,1600,5500,2000,100,*,DOWN,ALU1 +S 5700,800,5700,1300,300,*,UP,NDIF +S 4500,800,4500,1300,300,*,UP,NDIF +S 5100,800,5100,1300,300,*,UP,NDIF +S 4800,600,4800,1500,100,*,DOWN,NTRANS +S 5400,600,5400,1500,100,*,DOWN,NTRANS +S 4800,1500,5100,1500,100,*,RIGHT,POLY +S 5000,1600,5500,1600,100,*,RIGHT,ALU1 +S 6300,400,6300,1200,300,*,UP,NDIF +S 3900,400,3900,1200,300,*,UP,NDIF +S 3300,1000,3300,1200,300,*,UP,NDIF +S 4200,2600,4200,4000,100,*,UP,PTRANS +S 6000,2600,6000,4000,100,*,UP,PTRANS +S 5400,2600,5400,4000,100,*,UP,PTRANS +S 4800,2600,4800,4000,100,*,UP,PTRANS +S 6000,600,6000,1400,100,*,DOWN,NTRANS +S 4200,600,4200,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1400,300,*,DOWN,NDIF +S 2700,800,2700,1400,300,*,DOWN,NDIF +S 2400,600,2400,1600,100,*,UP,NTRANS +S 2400,1600,2400,2000,100,*,UP,POLY +S 2100,3300,2100,4100,300,*,UP,PDIF +S 2400,3100,2400,4300,100,*,DOWN,PTRANS +S 1800,3100,1800,4300,100,*,DOWN,PTRANS +S 1800,600,1800,1400,100,*,UP,NTRANS +S 2400,2000,2500,2000,100,*,RIGHT,POLY +S 600,2000,1200,2000,300,*,LEFT,POLY +S 2500,3000,2600,3000,100,*,LEFT,ALU1 +S 2600,3000,2600,3500,100,*,DOWN,ALU1 +S 2600,3500,4000,3500,100,*,RIGHT,ALU1 +S 7000,1500,7000,2900,100,*,DOWN,ALU1 +S 6500,1500,6500,4000,100,*,DOWN,ALU1 +S 7500,3500,7500,4500,200,*,DOWN,ALU1 +S 8700,3000,8700,4500,200,*,DOWN,ALU1 +S 8700,500,8700,1000,200,*,DOWN,ALU1 +S 7500,1000,7500,2000,100,*,DOWN,ALU1 +S 4500,1000,7500,1000,100,*,RIGHT,ALU1 +S 5000,2500,6500,2500,100,*,RIGHT,ALU1 +S 5500,2000,6000,2000,100,*,RIGHT,ALU1 +S 4500,1000,4500,3000,100,*,UP,ALU1 +S 4500,3000,5100,3000,100,*,LEFT,ALU1 +S 3300,1000,3300,3000,100,*,DOWN,ALU1 +S 5700,3000,5700,3500,100,*,DOWN,ALU1 +S 4500,3500,5700,3500,100,*,RIGHT,ALU1 +S 4000,1000,4000,3500,100,*,UP,ALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 2050,1000,2700,1000,100,*,RIGHT,ALU1 +S 1500,4000,6500,4000,100,*,RIGHT,ALU1 +S 2050,1000,2050,3500,100,*,UP,ALU1 +S 2500,2000,2500,3000,100,*,UP,ALU1 +S 0,4700,9000,4700,600,vdd,RIGHT,CALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 300,3000,300,4500,200,*,DOWN,ALU1 +S 0,300,9000,300,600,vss,RIGHT,CALU1 +S 8400,1400,8400,2600,100,*,DOWN,POLY +S 7800,1400,7800,2600,100,*,DOWN,POLY +S 4800,2600,5100,2600,100,*,RIGHT,POLY +S 6000,2000,7000,2000,100,*,RIGHT,POLY +S 6000,2000,6000,2600,100,*,DOWN,POLY +S 6000,1400,6600,1400,100,*,RIGHT,POLY +S 3300,2000,5400,2000,100,*,RIGHT,POLY +S 3600,1400,4200,1400,100,*,RIGHT,POLY +S 3600,2600,4200,2600,100,*,RIGHT,POLY +S 1500,2500,1800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1200,2000,2000,2000,100,*,RIGHT,POLY +S 1500,1500,1800,1500,300,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 7800,100,7800,1400,100,*,DOWN,NTRANS +S 8400,100,8400,1400,100,*,DOWN,NTRANS +S 8100,300,8100,1200,300,*,UP,NDIF +S 8700,300,8700,1200,300,*,UP,NDIF +S 7500,300,7500,1000,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 7800,2600,7800,4900,100,*,UP,PTRANS +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 7500,3400,7500,4700,300,*,DOWN,PDIF +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 8400,2600,8400,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2700,3300,2700,4600,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 8000,1000,8000,4000,200,sout,DOWN,CALU1 +S 4000,1000,4000,3500,200,b,DOWN,CALU1 +S 1500,1000,1500,4000,200,a,DOWN,CALU1 +S 1000,1000,1000,4000,200,cout,DOWN,CALU1 +S 7500,2000,8400,2000,300,*,RIGHT,POLY +V 5700,4700,CONT_BODY_N,* +V 4500,4700,CONT_BODY_N,* +V 5100,4700,CONT_BODY_N,* +V 2100,300,CONT_BODY_P,* +V 4500,300,CONT_BODY_P,* +V 5700,300,CONT_BODY_P,* +V 5100,300,CONT_BODY_P,* +V 5100,1100,CONT_DIF_N,* +V 5000,1600,CONT_POLY,* +V 6500,2500,CONT_POLY,* +V 7000,2000,CONT_POLY,* +V 6000,2000,CONT_POLY,* +V 7500,2000,CONT_POLY,* +V 3300,2000,CONT_POLY,* +V 4000,1500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 5000,2500,CONT_POLY,* +V 6500,1500,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 1600,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 1600,1500,CONT_POLY,* +V 2500,3000,CONT_POLY,* +V 3300,300,CONT_BODY_P,* +V 2700,300,CONT_BODY_P,* +V 7500,500,CONT_DIF_N,* +V 8700,500,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 8100,1000,CONT_DIF_N,* +V 7000,1500,CONT_DIF_N,* +V 6300,500,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 7500,4500,CONT_DIF_P,* +V 8100,4000,CONT_DIF_P,* +V 8100,3500,CONT_DIF_P,* +V 8100,3000,CONT_DIF_P,* +V 7000,2900,CONT_DIF_P,* +V 3300,3000,CONT_DIF_P,* +V 8700,4500,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 8700,3500,CONT_DIF_P,* +V 8700,3000,CONT_DIF_P,* +V 7500,3500,CONT_DIF_P,* +V 7500,4000,CONT_DIF_P,* +V 5700,3500,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 6900,4700,CONT_BODY_N,* +V 3300,4700,CONT_BODY_N,* +V 6300,4500,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 5700,3000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 900,3000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/halfadder_x4.vbe b/pdks/symbolic/sxlib/cells/halfadder_x4.vbe new file mode 100644 index 000000000..7743ad3e8 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/halfadder_x4.vbe @@ -0,0 +1,46 @@ +ENTITY halfadder_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_a : NATURAL := 27; + CONSTANT cin_b : NATURAL := 22; + CONSTANT rdown_a_cout : NATURAL := 810; + CONSTANT rdown_a_sout : NATURAL := 810; + CONSTANT rdown_b_cout : NATURAL := 810; + CONSTANT rdown_b_sout : NATURAL := 810; + CONSTANT rup_a_cout : NATURAL := 890; + CONSTANT rup_a_sout : NATURAL := 890; + CONSTANT rup_b_cout : NATURAL := 890; + CONSTANT rup_b_sout : NATURAL := 890; + CONSTANT tphh_a_cout : NATURAL := 467; + CONSTANT tpll_b_cout : NATURAL := 480; + CONSTANT tpll_a_cout : NATURAL := 494; + CONSTANT tphh_b_cout : NATURAL := 500; + CONSTANT tphh_a_sout : NATURAL := 527; + CONSTANT tpll_b_sout : NATURAL := 594; + CONSTANT tphl_b_sout : NATURAL := 607; + CONSTANT tplh_b_sout : NATURAL := 642; + CONSTANT tphh_b_sout : NATURAL := 655; + CONSTANT tphl_a_sout : NATURAL := 656; + CONSTANT tpll_a_sout : NATURAL := 665; + CONSTANT tplh_a_sout : NATURAL := 692; + CONSTANT transistors : NATURAL := 24 +); +PORT ( + a : in BIT; + b : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END halfadder_x4; + +ARCHITECTURE behaviour_data_flow OF halfadder_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on halfadder_x4" + SEVERITY WARNING; + sout <= (a xor b) after 1300 ps; + cout <= (a and b) after 1100 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/halfadder_x4.vhd b/pdks/symbolic/sxlib/cells/halfadder_x4.vhd new file mode 100644 index 000000000..f253a47b3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/halfadder_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY halfadder_x4 IS +PORT( + a : IN STD_LOGIC; + b : IN STD_LOGIC; + cout : OUT STD_LOGIC; + sout : OUT STD_LOGIC +); +END halfadder_x4; + +ARCHITECTURE RTL OF halfadder_x4 IS +BEGIN + cout <= (a AND b); + sout <= (a XOR b); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/inv_x1.al b/pdks/symbolic/sxlib/cells/inv_x1.al new file mode 100644 index 000000000..5ae39942f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x1.al @@ -0,0 +1,17 @@ +V ALLIANCE : 6 +H inv_x1,L,30/10/99 +C i,IN,EXTERNAL,4 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,2.1,9.75,tr_00002 +T N,0.35,1.4,1,4,2,0,0.75,0.75,4.3,4.3,2.1,3,tr_00001 +S 4,EXTERNAL,i +Q 0.00353623 +S 3,EXTERNAL,vdd +Q 0.00230273 +S 2,EXTERNAL,nq +Q 0.00240895 +S 1,EXTERNAL,vss +Q 0.00230273 +EOF diff --git a/pdks/symbolic/sxlib/cells/inv_x1.ap b/pdks/symbolic/sxlib/cells/inv_x1.ap new file mode 100644 index 000000000..813025e8e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x1.ap @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H inv_x1,P, 8/ 6/2002,100 +A 0,0,1500,5000 +R 1000,4000,ref_ref,nq_40 +R 1000,3500,ref_ref,nq_35 +R 1000,3000,ref_ref,nq_30 +R 1000,2500,ref_ref,nq_25 +R 1000,2000,ref_ref,nq_20 +R 1000,1500,ref_ref,nq_15 +R 1000,1000,ref_ref,nq_10 +R 500,1000,ref_ref,i_10 +R 500,1500,ref_ref,i_15 +R 500,2000,ref_ref,i_20 +R 500,2500,ref_ref,i_25 +R 500,3000,ref_ref,i_30 +R 500,3500,ref_ref,i_35 +R 500,4000,ref_ref,i_40 +S 1000,4300,1000,4800,300,*,DOWN,NTIE +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 1000,2800,1000,3700,300,*,DOWN,PDIF +S 700,2600,700,3900,100,*,UP,PTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 0,300,1500,300,600,vss,RIGHT,CALU1 +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 400,2000,700,2000,300,*,RIGHT,POLY +S 700,1400,700,2600,100,*,UP,POLY +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 350,400,350,1200,400,*,UP,NDIF +S 350,2800,350,4600,400,*,DOWN,PDIF +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +V 1000,3000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 400,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 1000,4700,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/inv_x1.sym b/pdks/symbolic/sxlib/cells/inv_x1.sym new file mode 100644 index 000000000..dc735e9d6 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/inv_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/inv_x1.vbe b/pdks/symbolic/sxlib/cells/inv_x1.vbe new file mode 100644 index 000000000..67e85e029 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x1.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_i_nq : NATURAL := 3640; + CONSTANT rup_i_nq : NATURAL := 3720; + CONSTANT tphl_i_nq : NATURAL := 101; + CONSTANT tplh_i_nq : NATURAL := 139; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x1; + +ARCHITECTURE behaviour_data_flow OF inv_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x1" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/inv_x1.vhd b/pdks/symbolic/sxlib/cells/inv_x1.vhd new file mode 100644 index 000000000..92c2d59ab --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x1.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY inv_x1 IS +PORT( + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END inv_x1; + +ARCHITECTURE RTL OF inv_x1 IS +BEGIN + nq <= NOT(i); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/inv_x2.al b/pdks/symbolic/sxlib/cells/inv_x2.al new file mode 100644 index 000000000..c02fcb01a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x2.al @@ -0,0 +1,17 @@ +V ALLIANCE : 6 +H inv_x2,L,30/10/99 +C i,IN,EXTERNAL,4 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,2 +T P,0.35,4.4,1,4,3,0,0.75,0.75,10.3,10.3,2.1,10.5,tr_00002 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00001 +S 4,EXTERNAL,i +Q 0.0031892 +S 3,EXTERNAL,vdd +Q 0.00230273 +S 2,EXTERNAL,vss +Q 0.00230273 +S 1,EXTERNAL,nq +Q 0.00276148 +EOF diff --git a/pdks/symbolic/sxlib/cells/inv_x2.ap b/pdks/symbolic/sxlib/cells/inv_x2.ap new file mode 100644 index 000000000..d44069e63 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x2.ap @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H inv_x2,P,18/ 5/2002,100 +A 0,0,1500,5000 +R 1000,4000,ref_ref,nq_40 +R 1000,3500,ref_ref,nq_35 +R 1000,3000,ref_ref,nq_30 +R 1000,2500,ref_ref,nq_25 +R 1000,2000,ref_ref,nq_20 +R 1000,1500,ref_ref,nq_15 +R 1000,1000,ref_ref,nq_10 +R 500,1000,ref_ref,i_10 +R 500,1500,ref_ref,i_15 +R 500,2000,ref_ref,i_20 +R 500,2500,ref_ref,i_25 +R 500,3000,ref_ref,i_30 +R 500,3500,ref_ref,i_35 +R 500,4000,ref_ref,i_40 +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 350,2800,350,4600,400,*,DOWN,PDIF +S 350,400,350,1700,400,*,UP,NDIF +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 1000,800,1000,1700,300,*,UP,NDIF +S 700,600,700,1900,100,*,DOWN,NTRANS +S 700,1900,700,2600,100,*,UP,POLY +S 1000,2800,1000,4200,300,*,DOWN,PDIF +S 700,2600,700,4400,100,*,UP,PTRANS +S 400,2000,700,2000,300,*,RIGHT,POLY +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 0,300,1500,300,600,vss,RIGHT,CALU1 +V 1000,1500,CONT_DIF_N,* +V 1000,3000,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 400,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/inv_x2.sym b/pdks/symbolic/sxlib/cells/inv_x2.sym new file mode 100644 index 000000000..93f40e69c Binary files /dev/null and b/pdks/symbolic/sxlib/cells/inv_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/inv_x2.vbe b/pdks/symbolic/sxlib/cells/inv_x2.vbe new file mode 100644 index 000000000..9df0116d3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x2.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT cin_i : NATURAL := 12; + CONSTANT rdown_i_nq : NATURAL := 1620; + CONSTANT rup_i_nq : NATURAL := 2420; + CONSTANT tphl_i_nq : NATURAL := 69; + CONSTANT tplh_i_nq : NATURAL := 163; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x2; + +ARCHITECTURE behaviour_data_flow OF inv_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x2" + SEVERITY WARNING; + nq <= not (i) after 800 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/inv_x2.vhd b/pdks/symbolic/sxlib/cells/inv_x2.vhd new file mode 100644 index 000000000..d4b14dd67 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x2.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY inv_x2 IS +PORT( + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END inv_x2; + +ARCHITECTURE RTL OF inv_x2 IS +BEGIN + nq <= NOT(i); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/inv_x4.al b/pdks/symbolic/sxlib/cells/inv_x4.al new file mode 100644 index 000000000..bb87114c7 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x4.al @@ -0,0 +1,19 @@ +V ALLIANCE : 6 +H inv_x4,L,30/10/99 +C i,IN,EXTERNAL,4 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,2 +T P,0.35,4.1,3,4,1,0,0.75,0.75,9.7,9.7,3.9,12.15,tr_00004 +T P,0.35,5.9,1,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00003 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00002 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00001 +S 4,EXTERNAL,i +Q 0.00530442 +S 3,EXTERNAL,vdd +Q 0.00423058 +S 2,EXTERNAL,vss +Q 0.0038193 +S 1,EXTERNAL,nq +Q 0.00258522 +EOF diff --git a/pdks/symbolic/sxlib/cells/inv_x4.ap b/pdks/symbolic/sxlib/cells/inv_x4.ap new file mode 100644 index 000000000..cdec25600 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x4.ap @@ -0,0 +1,52 @@ +V ALLIANCE : 6 +H inv_x4,P,10/ 6/2002,100 +A 0,0,2000,5000 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1000,4000,ref_ref,nq_40 +R 500,4000,ref_ref,i_40 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +R 500,2500,ref_ref,i_25 +R 500,2000,ref_ref,i_20 +R 500,1500,ref_ref,i_15 +R 500,1000,ref_ref,i_10 +S 1600,3500,1600,4500,200,*,DOWN,ALU1 +S 1600,500,1600,1000,200,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 0,3900,2000,3900,2400,*,LEFT,NWELL +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 1600,3400,1600,4700,300,*,DOWN,PDIF +S 1300,1400,1300,3200,100,*,UP,POLY +S 1300,3200,1300,4900,100,*,UP,PTRANS +S 400,300,400,1200,300,*,UP,NDIF +S 1000,300,1000,1200,300,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 1300,100,1300,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,300,*,UP,NDIF +S 500,1500,1300,1500,300,*,RIGHT,POLY +S 400,2800,400,4700,300,*,DOWN,PDIF +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 700,1400,700,2600,100,*,UP,POLY +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +V 400,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 1600,1000,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 1600,4000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 1600,3500,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/inv_x4.sym b/pdks/symbolic/sxlib/cells/inv_x4.sym new file mode 100644 index 000000000..2a1da33c5 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/inv_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/inv_x4.vbe b/pdks/symbolic/sxlib/cells/inv_x4.vbe new file mode 100644 index 000000000..3091ae3f7 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x4.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i : NATURAL := 26; + CONSTANT rdown_i_nq : NATURAL := 810; + CONSTANT rup_i_nq : NATURAL := 1060; + CONSTANT tphl_i_nq : NATURAL := 71; + CONSTANT tplh_i_nq : NATURAL := 143; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x4; + +ARCHITECTURE behaviour_data_flow OF inv_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x4" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/inv_x4.vhd b/pdks/symbolic/sxlib/cells/inv_x4.vhd new file mode 100644 index 000000000..2263c327f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x4.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY inv_x4 IS +PORT( + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END inv_x4; + +ARCHITECTURE RTL OF inv_x4 IS +BEGIN + nq <= NOT(i); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/inv_x8.al b/pdks/symbolic/sxlib/cells/inv_x8.al new file mode 100644 index 000000000..f3b8f6acc --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x8.al @@ -0,0 +1,23 @@ +V ALLIANCE : 6 +H inv_x8,L,30/10/99 +C i,IN,EXTERNAL,4 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00008 +T P,0.35,5.9,3,4,2,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00007 +T P,0.35,5.9,3,4,2,0,0.75,0.75,13.3,13.3,7.5,11.25,tr_00006 +T P,0.35,5.9,2,4,3,0,0.75,0.75,13.3,13.3,5.7,11.25,tr_00005 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00004 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00003 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,7.5,2.25,tr_00002 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.7,2.25,tr_00001 +S 4,EXTERNAL,i +Q 0.00785425 +S 3,EXTERNAL,vdd +Q 0.0074877 +S 2,EXTERNAL,nq +Q 0.00599301 +S 1,EXTERNAL,vss +Q 0.00613633 +EOF diff --git a/pdks/symbolic/sxlib/cells/inv_x8.ap b/pdks/symbolic/sxlib/cells/inv_x8.ap new file mode 100644 index 000000000..7f1ac2163 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x8.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 6 +H inv_x8,P,18/ 5/2002,100 +A 0,0,3500,5000 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1000,4000,ref_ref,nq_40 +R 500,1000,ref_ref,i_10 +R 500,1500,ref_ref,i_15 +R 500,2000,ref_ref,i_20 +R 500,2500,ref_ref,i_25 +R 500,3000,ref_ref,i_30 +R 500,3500,ref_ref,i_35 +R 500,4000,ref_ref,i_40 +S 2800,3350,2800,4500,200,*,UP,ALU1 +S 2750,3400,3200,3400,200,*,LEFT,ALU1 +S 3200,2900,3200,3400,200,*,UP,ALU1 +S 2800,500,2800,1700,200,*,DOWN,ALU1 +S 2800,1700,3200,1700,200,*,LEFT,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 1000,2000,2200,2000,200,*,LEFT,ALU1 +S 2200,1000,2200,4000,200,*,DOWN,ALU1 +S 3200,2800,3200,3500,300,*,UP,NTIE +S 2800,3900,2800,4700,300,*,DOWN,PDIF +S 2700,1700,3300,1700,300,*,RIGHT,PTIE +S 400,1500,2500,1500,300,*,RIGHT,POLY +S 1600,3000,1600,4500,200,*,UP,ALU1 +S 1600,500,1600,1000,200,*,DOWN,ALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1900,100,1900,1400,100,*,DOWN,NTRANS +S 2500,100,2500,1400,100,*,DOWN,NTRANS +S 2200,300,2200,1200,300,*,UP,NDIF +S 400,300,400,1200,300,*,UP,NDIF +S 1000,300,1000,1200,300,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,300,*,UP,NDIF +S 1300,100,1300,1400,100,*,DOWN,NTRANS +S 1900,2600,1900,4900,100,*,UP,PTRANS +S 2200,2800,2200,4700,300,*,DOWN,PDIF +S 2500,2600,2500,4900,100,*,UP,PTRANS +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 400,2800,400,4700,300,*,DOWN,PDIF +S 700,1400,700,2600,100,*,UP,POLY +S 1300,1400,1300,2600,100,*,UP,POLY +S 1900,1400,1900,2600,100,*,UP,POLY +S 2500,1400,2500,2600,100,*,UP,POLY +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 2800,300,2800,1200,300,*,UP,NDIF +S 0,3900,3500,3900,2400,*,LEFT,NWELL +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +V 3200,3400,CONT_BODY_N,* +V 2800,4000,CONT_DIF_P,* +V 2800,4500,CONT_DIF_P,* +V 3200,2900,CONT_BODY_N,* +V 3200,1700,CONT_BODY_P,* +V 2800,1700,CONT_BODY_P,* +V 500,1500,CONT_POLY,* +V 1600,1000,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 2200,1000,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 2200,3000,CONT_DIF_P,* +V 2200,3500,CONT_DIF_P,* +V 2200,4000,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 1600,3000,CONT_DIF_P,* +V 1600,3500,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 1600,4000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 2800,500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/inv_x8.sym b/pdks/symbolic/sxlib/cells/inv_x8.sym new file mode 100644 index 000000000..c0564bf14 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/inv_x8.sym differ diff --git a/pdks/symbolic/sxlib/cells/inv_x8.vbe b/pdks/symbolic/sxlib/cells/inv_x8.vbe new file mode 100644 index 000000000..4e6fa0639 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x8.vbe @@ -0,0 +1,26 @@ +ENTITY inv_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i : NATURAL := 54; + CONSTANT rdown_i_nq : NATURAL := 400; + CONSTANT rup_i_nq : NATURAL := 450; + CONSTANT tphl_i_nq : NATURAL := 86; + CONSTANT tplh_i_nq : NATURAL := 133; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x8; + +ARCHITECTURE behaviour_data_flow OF inv_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on inv_x8" + SEVERITY WARNING; + nq <= not (i) after 700 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/inv_x8.vhd b/pdks/symbolic/sxlib/cells/inv_x8.vhd new file mode 100644 index 000000000..9d32ed3c7 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/inv_x8.vhd @@ -0,0 +1,19 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY inv_x8 IS +PORT( + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END inv_x8; + +ARCHITECTURE RTL OF inv_x8 IS +BEGIN + nq <= NOT(i); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/mx2_x2.al b/pdks/symbolic/sxlib/cells/mx2_x2.al new file mode 100644 index 000000000..719679f70 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx2_x2.al @@ -0,0 +1,45 @@ +V ALLIANCE : 6 +H mx2_x2,L,30/10/99 +C cmd,IN,EXTERNAL,6 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,9 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,10,7,11,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00012 +T P,0.35,2.9,2,3,12,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00011 +T P,0.35,2.9,11,6,2,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00010 +T P,0.35,2.9,3,6,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009 +T P,0.35,2.9,12,8,10,0,0.75,0.75,7.3,7.3,8.4,11.25,tr_00008 +T P,0.35,5.9,10,2,9,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00007 +T N,0.35,2.9,9,2,1,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00006 +T N,0.35,1.4,4,7,1,0,0.75,0.75,4.3,4.3,3.6,1.5,tr_00005 +T N,0.35,1.4,2,3,4,0,0.75,0.75,4.3,4.3,4.8,1.5,tr_00004 +T N,0.35,1.4,1,6,3,0,0.75,0.75,4.3,4.3,1.8,1.5,tr_00003 +T N,0.35,1.4,5,6,2,0,0.75,0.75,4.3,4.3,7.2,1.5,tr_00002 +T N,0.35,1.4,1,8,5,0,0.75,0.75,4.3,4.3,8.4,1.5,tr_00001 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,vdd +Q 0.00658426 +S 9,EXTERNAL,q +Q 0.00264397 +S 8,EXTERNAL,i1 +Q 0.00371745 +S 7,EXTERNAL,i0 +Q 0.00336619 +S 6,EXTERNAL,cmd +Q 0.00660261 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00595297 +S 2,INTERNAL +Q 0.0047485 +S 1,EXTERNAL,vss +Q 0.00552667 +EOF diff --git a/pdks/symbolic/sxlib/cells/mx2_x2.ap b/pdks/symbolic/sxlib/cells/mx2_x2.ap new file mode 100644 index 000000000..88250b0b5 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx2_x2.ap @@ -0,0 +1,115 @@ +V ALLIANCE : 6 +H mx2_x2,P, 8/ 6/2002,100 +A 0,0,4500,5000 +R 1500,1500,ref_ref,cmd_15 +R 1500,2000,ref_ref,cmd_20 +R 1500,2500,ref_ref,cmd_25 +R 1500,3000,ref_ref,cmd_30 +R 1500,3500,ref_ref,cmd_35 +R 1500,4000,ref_ref,cmd_40 +R 4000,2500,ref_ref,q_25 +R 4000,3500,ref_ref,q_35 +R 4000,4000,ref_ref,q_40 +R 4000,1500,ref_ref,q_15 +R 4000,2000,ref_ref,q_20 +R 4000,3000,ref_ref,q_30 +R 4000,1000,ref_ref,q_10 +R 1000,1500,ref_ref,i0_15 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 1000,4000,ref_ref,i0_40 +R 3000,1000,ref_ref,i1_10 +R 3000,1500,ref_ref,i1_15 +R 3000,2000,ref_ref,i1_20 +R 3000,2500,ref_ref,i1_25 +R 3000,3000,ref_ref,i1_30 +R 3000,3500,ref_ref,i1_35 +R 3000,4000,ref_ref,i1_40 +S 3500,2800,3500,3300,300,*,DOWN,PDIF +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 3800,1400,3800,2600,100,*,DOWN,POLY +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,100,2400,900,100,*,UP,NTRANS +S 600,900,600,3100,100,*,DOWN,POLY +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,700,300,*,UP,NDIF +S 600,100,600,900,100,*,UP,NTRANS +S 1600,100,1600,900,100,*,UP,NTRANS +S 1200,100,1200,900,100,*,UP,NTRANS +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 2400,2800,2400,3100,100,*,UP,POLY +S 2500,1000,2500,2700,100,*,UP,ALU1 +S 2000,2300,3800,2300,100,*,RIGHT,POLY +S 3500,3000,3500,4500,200,*,UP,ALU1 +S 3300,3300,3300,4700,700,*,UP,PDIF +S 3300,300,3300,1200,700,*,DOWN,NDIF +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 3800,100,3800,1400,100,*,UP,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 1600,2000,1600,3100,100,*,UP,POLY +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 4000,950,4000,4050,200,*,DOWN,ALU1 +S 1500,1500,1500,4000,200,cmd,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 3500,500,3500,1000,200,*,DOWN,ALU1 +V 2500,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 1600,1000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2400,CONT_POLY,* +V 2500,2700,CONT_POLY,* +V 3500,3000,CONT_DIF_P,* +V 3500,1000,CONT_DIF_N,* +V 3500,4500,CONT_DIF_P,* +V 3500,500,CONT_DIF_N,* +V 4100,1000,CONT_DIF_N,* +V 4100,3000,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,3500,CONT_DIF_P,* +V 3500,4000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 2000,4000,CONT_DIF_P,* +V 2000,4700,CONT_BODY_N,* +V 2000,3500,CONT_DIF_P,* +V 2000,1500,CONT_DIF_N,* +V 3000,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 900,4500,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 3000,1500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/mx2_x2.sym b/pdks/symbolic/sxlib/cells/mx2_x2.sym new file mode 100644 index 000000000..572a87c6b Binary files /dev/null and b/pdks/symbolic/sxlib/cells/mx2_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/mx2_x2.vbe b/pdks/symbolic/sxlib/cells/mx2_x2.vbe new file mode 100644 index 000000000..401686e9e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx2_x2.vbe @@ -0,0 +1,40 @@ +ENTITY mx2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_cmd_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 451; + CONSTANT tphh_i1_q : NATURAL := 451; + CONSTANT tpll_i0_q : NATURAL := 469; + CONSTANT tpll_i1_q : NATURAL := 469; + CONSTANT tphh_cmd_q : NATURAL := 484; + CONSTANT tphl_cmd_q : NATURAL := 485; + CONSTANT tpll_cmd_q : NATURAL := 522; + CONSTANT tplh_cmd_q : NATURAL := 534; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x2; + +ARCHITECTURE behaviour_data_flow OF mx2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x2" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1100 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/mx2_x2.vhd b/pdks/symbolic/sxlib/cells/mx2_x2.vhd new file mode 100644 index 000000000..c115df14b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx2_x2.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY mx2_x2 IS +PORT( + cmd : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END mx2_x2; + +ARCHITECTURE RTL OF mx2_x2 IS +BEGIN + q <= ((i1 AND cmd) OR (NOT(cmd) AND i0)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/mx2_x4.al b/pdks/symbolic/sxlib/cells/mx2_x4.al new file mode 100644 index 000000000..be51afcd5 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx2_x4.al @@ -0,0 +1,47 @@ +V ALLIANCE : 6 +H mx2_x4,L,30/10/99 +C cmd,IN,EXTERNAL,6 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,9 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,11,7,10,0,0.75,0.75,7.3,7.3,8.4,11.25,tr_00014 +T P,0.35,2.9,2,6,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00013 +T P,0.35,2.9,12,6,1,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00012 +T P,0.35,2.9,1,2,11,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00011 +T P,0.35,2.9,10,8,12,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00010 +T P,0.35,5.9,9,1,10,0,0.75,0.75,13.3,13.3,13.2,11.25,tr_00009 +T P,0.35,5.9,10,1,9,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00008 +T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,8.4,1.5,tr_00007 +T N,0.35,1.4,4,6,1,0,0.75,0.75,4.3,4.3,7.2,1.5,tr_00006 +T N,0.35,1.4,3,6,2,0,0.75,0.75,4.3,4.3,1.8,1.5,tr_00005 +T N,0.35,1.4,1,2,5,0,0.75,0.75,4.3,4.3,4.8,1.5,tr_00004 +T N,0.35,1.4,5,8,3,0,0.75,0.75,4.3,4.3,3.6,1.5,tr_00003 +T N,0.35,2.9,9,1,3,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00002 +T N,0.35,2.9,3,1,9,0,0.75,0.75,7.3,7.3,13.2,2.25,tr_00001 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,vdd +Q 0.00862963 +S 9,EXTERNAL,q +Q 0.00264397 +S 8,EXTERNAL,i0 +Q 0.00336619 +S 7,EXTERNAL,i1 +Q 0.00371745 +S 6,EXTERNAL,cmd +Q 0.00660261 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00721951 +S 2,INTERNAL +Q 0.00595297 +S 1,INTERNAL +Q 0.00607876 +EOF diff --git a/pdks/symbolic/sxlib/cells/mx2_x4.ap b/pdks/symbolic/sxlib/cells/mx2_x4.ap new file mode 100644 index 000000000..c71a78b69 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx2_x4.ap @@ -0,0 +1,129 @@ +V ALLIANCE : 6 +H mx2_x4,P,18/ 5/2002,100 +A 0,0,5000,5000 +R 1500,1500,ref_ref,cmd_15 +R 1500,2000,ref_ref,cmd_20 +R 1500,2500,ref_ref,cmd_25 +R 1500,3000,ref_ref,cmd_30 +R 1500,3500,ref_ref,cmd_35 +R 1500,4000,ref_ref,cmd_40 +R 4000,2500,ref_ref,q_25 +R 4000,3500,ref_ref,q_35 +R 4000,4000,ref_ref,q_40 +R 4000,1500,ref_ref,q_15 +R 4000,2000,ref_ref,q_20 +R 4000,3000,ref_ref,q_30 +R 4000,1000,ref_ref,q_10 +R 1000,1500,ref_ref,i0_15 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 1000,4000,ref_ref,i0_40 +R 3000,1000,ref_ref,i1_10 +R 3000,1500,ref_ref,i1_15 +R 3000,2000,ref_ref,i1_20 +R 3000,2500,ref_ref,i1_25 +R 3000,3000,ref_ref,i1_30 +R 3000,3500,ref_ref,i1_35 +R 3000,4000,ref_ref,i1_40 +S 3500,500,3500,1000,200,*,DOWN,ALU1 +S 4700,500,4700,1000,200,*,DOWN,ALU1 +S 1500,1500,1500,4000,200,cmd,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 4000,950,4000,4050,200,*,DOWN,ALU1 +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,100,2400,900,100,*,UP,NTRANS +S 600,900,600,3100,100,*,DOWN,POLY +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,700,300,*,UP,NDIF +S 600,100,600,900,100,*,UP,NTRANS +S 1600,100,1600,900,100,*,UP,NTRANS +S 1200,100,1200,900,100,*,UP,NTRANS +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 2400,2800,2400,3100,100,*,UP,POLY +S 2500,1000,2500,2700,100,*,UP,ALU1 +S 3500,3000,3500,4500,200,*,UP,ALU1 +S 3300,3300,3300,4700,700,*,UP,PDIF +S 3300,300,3300,1200,700,*,DOWN,NDIF +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 3800,100,3800,1400,100,*,UP,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 1600,2000,1600,3100,100,*,UP,POLY +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 4400,100,4400,1400,100,*,UP,NTRANS +S 4700,300,4700,1200,300,*,DOWN,NDIF +S 2000,2300,4400,2300,100,*,RIGHT,POLY +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 4700,3000,4700,4500,200,*,UP,ALU1 +S 4400,2600,4400,4900,100,*,DOWN,PTRANS +S 4700,2800,4700,4700,300,*,UP,PDIF +S 4700,2800,4700,3300,300,*,DOWN,PDIF +S 3500,2800,3500,3300,300,*,DOWN,PDIF +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 3800,1400,3800,2600,100,*,DOWN,POLY +S 4400,1400,4400,2600,100,*,DOWN,POLY +V 2500,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 1600,1000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2400,CONT_POLY,* +V 2500,2700,CONT_POLY,* +V 3500,3000,CONT_DIF_P,* +V 3500,1000,CONT_DIF_N,* +V 3500,4500,CONT_DIF_P,* +V 3500,500,CONT_DIF_N,* +V 4100,1000,CONT_DIF_N,* +V 4100,3000,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 4100,3500,CONT_DIF_P,* +V 3500,4000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 2000,4000,CONT_DIF_P,* +V 2000,4700,CONT_BODY_N,* +V 2000,3500,CONT_DIF_P,* +V 2000,1500,CONT_DIF_N,* +V 3000,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 900,4500,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 3000,1500,CONT_POLY,* +V 4700,3500,CONT_DIF_P,* +V 4700,3000,CONT_DIF_P,* +V 4700,4500,CONT_DIF_P,* +V 4700,4000,CONT_DIF_P,* +V 4700,500,CONT_DIF_N,* +V 4700,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/mx2_x4.sym b/pdks/symbolic/sxlib/cells/mx2_x4.sym new file mode 100644 index 000000000..8224e1782 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/mx2_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/mx2_x4.vbe b/pdks/symbolic/sxlib/cells/mx2_x4.vbe new file mode 100644 index 000000000..ddb1f3ca7 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY mx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 564; + CONSTANT tphh_i1_q : NATURAL := 564; + CONSTANT tphl_cmd_q : NATURAL := 574; + CONSTANT tpll_i0_q : NATURAL := 576; + CONSTANT tpll_i1_q : NATURAL := 576; + CONSTANT tphh_cmd_q : NATURAL := 615; + CONSTANT tplh_cmd_q : NATURAL := 631; + CONSTANT tpll_cmd_q : NATURAL := 647; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x4; + +ARCHITECTURE behaviour_data_flow OF mx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx2_x4" + SEVERITY WARNING; + q <= ((i1 and cmd) or (not (cmd) and i0)) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/mx2_x4.vhd b/pdks/symbolic/sxlib/cells/mx2_x4.vhd new file mode 100644 index 000000000..2da047b55 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx2_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY mx2_x4 IS +PORT( + cmd : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END mx2_x4; + +ARCHITECTURE RTL OF mx2_x4 IS +BEGIN + q <= ((i1 AND cmd) OR (NOT(cmd) AND i0)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/mx3_x2.al b/pdks/symbolic/sxlib/cells/mx3_x2.al new file mode 100644 index 000000000..6b49a8232 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx3_x2.al @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H mx3_x2,L,30/10/99 +C cmd0,IN,EXTERNAL,15 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,16,6,1,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00020 +T P,0.35,2.9,7,13,18,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00019 +T P,0.35,2.9,19,15,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00018 +T P,0.35,2.9,1,14,19,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00017 +T P,0.35,2.9,18,8,16,0,0.75,0.75,7.3,7.3,9,12.75,tr_00016 +T P,0.35,2.9,17,10,18,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00015 +T P,0.35,2.9,1,9,17,0,0.75,0.75,7.3,7.3,6,12.75,tr_00014 +T P,0.35,5.9,12,1,7,0,0.75,0.75,13.3,13.3,17.4,11.25,tr_00013 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00012 +T P,0.35,2,7,15,13,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00011 +T N,0.35,1.7,4,8,2,0,0.75,0.75,4.9,4.9,9,2.55,tr_00010 +T N,0.35,1.7,2,9,1,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00009 +T N,0.35,1.7,1,6,5,0,0.75,0.75,4.9,4.9,6,2.55,tr_00008 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00007 +T N,0.35,1.7,3,15,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00006 +T N,0.35,1.7,11,13,3,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00005 +T N,0.35,1.7,1,14,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00004 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00003 +T N,0.35,1.1,13,15,3,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00002 +T N,0.35,2.9,3,1,12,0,0.75,0.75,7.3,7.3,17.4,3.75,tr_00001 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0.00170541 +S 17,INTERNAL +Q 0 +S 16,INTERNAL +Q 0 +S 15,EXTERNAL,cmd0 +Q 0.00553121 +S 14,EXTERNAL,i0 +Q 0.00386191 +S 13,INTERNAL +Q 0.0057783 +S 12,EXTERNAL,q +Q 0.00361343 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00654004 +S 6,INTERNAL +Q 0.00547335 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00671631 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00814817 +EOF diff --git a/pdks/symbolic/sxlib/cells/mx3_x2.ap b/pdks/symbolic/sxlib/cells/mx3_x2.ap new file mode 100644 index 000000000..03aebe1e0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx3_x2.ap @@ -0,0 +1,175 @@ +V ALLIANCE : 6 +H mx3_x2,P,13/ 6/2002,100 +A 0,0,6500,5000 +R 500,1500,ref_ref,cmd1_15 +R 500,2000,ref_ref,cmd1_20 +R 500,2500,ref_ref,cmd1_25 +R 500,3000,ref_ref,cmd1_30 +R 500,3500,ref_ref,cmd1_35 +R 1500,2500,ref_ref,i2_25 +R 2500,2500,ref_ref,i1_25 +R 3500,2000,ref_ref,cmd0_20 +R 3500,2500,ref_ref,cmd0_25 +R 3500,3000,ref_ref,cmd0_30 +R 4000,2000,ref_ref,i0_20 +R 4000,3000,ref_ref,i0_30 +R 4500,2500,ref_ref,i0_25 +R 6000,1000,ref_ref,q_10 +R 6000,1500,ref_ref,q_15 +R 6000,2500,ref_ref,q_25 +R 6000,3000,ref_ref,q_30 +R 6000,3500,ref_ref,q_35 +R 6000,4000,ref_ref,q_40 +S 1100,1000,3300,1000,200,*,RIGHT,ALU1 +S 4900,1000,5500,1000,200,*,RIGHT,ALU1 +S 5500,1000,5500,3500,200,*,DOWN,ALU1 +S 4400,2000,4400,3000,200,*,UP,ALU1 +S 4900,3500,4900,4000,200,*,DOWN,ALU1 +S 5000,1500,5000,3000,200,*,DOWN,ALU1 +S 3400,1500,5000,1500,200,*,RIGHT,ALU1 +S 1100,4000,3300,4000,200,*,RIGHT,ALU1 +S 2300,3500,5500,3500,200,*,RIGHT,ALU1 +S 3000,2000,3000,3500,200,*,UP,ALU1 +S 2800,2000,3000,2000,200,*,RIGHT,ALU1 +S 2800,1500,2800,2000,200,*,UP,ALU1 +S 2300,1500,2800,1500,200,*,RIGHT,ALU1 +S 1100,3000,2500,3000,200,*,LEFT,ALU1 +S 1000,1600,1000,3000,200,*,UP,ALU1 +S 2000,2500,2500,2500,200,*,LEFT,ALU1 +S 1500,2100,1500,2500,200,*,DOWN,ALU1 +S 1100,1500,1800,1500,200,*,LEFT,ALU1 +S 800,2000,800,2600,100,*,DOWN,POLY +S 500,900,500,1800,300,*,DOWN,NDIF +S 800,1300,800,2000,100,*,DOWN,NTRANS +S 1100,1500,1100,1800,300,*,UP,NDIF +S 5200,1300,5200,1900,100,*,DOWN,NTRANS +S 5200,1900,5200,2600,100,*,DOWN,POLY +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 500,3500,1800,3500,100,*,LEFT,ALU1 +S 500,400,500,1000,200,*,DOWN,ALU1 +S 2600,3000,2600,3600,100,*,UP,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 500,2500,800,2500,300,*,RIGHT,POLY +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 3900,3800,3900,4700,200,*,UP,PDIF +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 4900,3800,4900,4700,300,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 3300,3800,3300,4700,200,*,UP,PDIF +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 1100,3800,1100,4700,300,*,UP,PDIF +S 1400,3600,1400,4900,100,*,UP,PTRANS +S 1700,3800,1700,4700,200,*,DOWN,PDIF +S 2300,3500,2300,4700,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 500,2800,500,4000,300,*,UP,PDIF +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 4000,3300,4000,3600,100,*,UP,POLY +S 5800,2600,5800,4900,100,*,UP,PTRANS +S 5500,2800,5500,4600,300,*,DOWN,PDIF +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 5800,2000,5800,2600,100,*,DOWN,POLY +S 6100,2800,6100,4700,300,*,UP,PDIF +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 4900,2800,4900,3400,300,*,UP,PDIF +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 4200,1100,4200,1500,100,*,UP,POLY +S 3900,400,3900,900,200,*,DOWN,NDIF +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 800,2600,800,3600,100,*,UP,PTRANS +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 3000,400,3000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 1400,400,1400,1300,100,*,UP,NTRANS +S 3600,200,3600,1100,100,*,UP,NTRANS +S 4200,200,4200,1100,100,*,UP,NTRANS +S 4600,200,4600,1100,100,*,UP,NTRANS +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 3500,1500,3500,3600,100,*,UP,POLY +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 4900,1500,4900,1700,300,*,DOWN,NDIF +S 5800,600,5800,1900,100,*,DOWN,NTRANS +S 6100,800,6100,1700,300,*,UP,NDIF +S 5500,500,5500,1700,300,*,DOWN,NDIF +S 6050,2500,6250,2500,200,*,RIGHT,ALU1 +S 6200,1450,6200,2550,200,*,DOWN,ALU1 +S 6050,1500,6250,1500,200,*,LEFT,ALU1 +S 5500,2000,5700,2000,200,*,LEFT,ALU1 +S 4900,400,4900,1000,300,*,UP,NDIF +S 500,1500,500,3500,200,cmd1,DOWN,CALU1 +S 1500,2500,1500,2500,200,i2,LEFT,CALU1 +S 2500,2500,2500,2500,200,i1,LEFT,CALU1 +S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1 +S 6000,2450,6000,4000,200,*,DOWN,ALU1 +S 6000,950,6000,1550,200,*,DOWN,ALU1 +S 6000,2500,6000,4000,200,q,DOWN,CALU1 +S 6000,1000,6000,1500,200,q,DOWN,CALU1 +S 4000,3000,4000,3000,200,i0,LEFT,CALU1 +S 4500,2500,4500,2500,200,i0,LEFT,CALU1 +S 4000,2000,4000,2000,200,i0,LEFT,CALU1 +S 1800,3500,2000,3500,300,*,RIGHT,POLY +S 4400,2000,4600,2000,300,*,RIGHT,POLY +S 4400,3000,4600,3000,300,*,LEFT,POLY +S 1800,1500,2000,1500,300,*,RIGHT,POLY +V 1100,1600,CONT_DIF_N,* +V 4900,1600,CONT_DIF_N,* +V 1800,3500,CONT_POLY,* +V 4200,1500,CONT_POLY,* +V 3400,1500,CONT_POLY,* +V 1800,1500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2300,1500,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 4900,1000,CONT_DIF_N,* +V 1100,1000,CONT_DIF_N,* +V 500,1000,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 3300,4000,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 2300,3500,CONT_DIF_P,* +V 1100,4000,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 1100,3000,CONT_DIF_P,* +V 4900,3000,CONT_DIF_P,* +V 2500,3000,CONT_POLY,* +V 4400,3000,CONT_POLY,* +V 4400,2000,CONT_POLY,* +V 5500,4600,CONT_DIF_P,* +V 5500,500,CONT_DIF_N,* +V 6100,3500,CONT_DIF_P,* +V 6100,4000,CONT_DIF_P,* +V 6100,3000,CONT_DIF_P,* +V 6100,1500,CONT_DIF_N,* +V 6100,1000,CONT_DIF_N,* +V 3900,2500,CONT_POLY,* +V 5700,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/mx3_x2.vbe b/pdks/symbolic/sxlib/cells/mx3_x2.vbe new file mode 100644 index 000000000..ddc531ad5 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx3_x2.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 1620; + CONSTANT rdown_cmd1_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_cmd0_q : NATURAL := 1790; + CONSTANT rup_cmd1_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 538; + CONSTANT tphh_cmd0_q : NATURAL := 573; + CONSTANT tphh_i1_q : NATURAL := 654; + CONSTANT tphh_i2_q : NATURAL := 654; + CONSTANT tpll_i0_q : NATURAL := 658; + CONSTANT tphh_cmd1_q : NATURAL := 664; + CONSTANT tpll_cmd0_q : NATURAL := 680; + CONSTANT tplh_cmd1_q : NATURAL := 738; + CONSTANT tphl_cmd1_q : NATURAL := 739; + CONSTANT tplh_cmd0_q : NATURAL := 768; + CONSTANT tphl_cmd0_q : NATURAL := 792; + CONSTANT tpll_i1_q : NATURAL := 808; + CONSTANT tpll_i2_q : NATURAL := 808; + CONSTANT tpll_cmd1_q : NATURAL := 817; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x2; + +ARCHITECTURE behaviour_data_flow OF mx3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx3_x2" + SEVERITY WARNING; + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) + and i2)))) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/mx3_x2.vhd b/pdks/symbolic/sxlib/cells/mx3_x2.vhd new file mode 100644 index 000000000..9fc27c51f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx3_x2.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY mx3_x2 IS +PORT( + cmd0 : IN STD_LOGIC; + cmd1 : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END mx3_x2; + +ARCHITECTURE RTL OF mx3_x2 IS +BEGIN + q <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2)))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/mx3_x4.al b/pdks/symbolic/sxlib/cells/mx3_x4.al new file mode 100644 index 000000000..a852eb315 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx3_x4.al @@ -0,0 +1,71 @@ +V ALLIANCE : 6 +H mx3_x4,L,30/10/99 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,15 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,7,2,11,0,0.75,0.75,13.3,13.3,18.9,11.25,tr_00022 +T P,0.35,2.9,18,6,2,0,0.75,0.75,7.3,7.3,7.5,12.75,tr_00021 +T P,0.35,2.9,7,13,17,0,0.75,0.75,7.3,7.3,10.5,12.75,tr_00020 +T P,0.35,2.9,19,14,7,0,0.75,0.75,7.3,7.3,12.3,12.75,tr_00019 +T P,0.35,2.9,2,15,19,0,0.75,0.75,7.3,7.3,13.5,12.75,tr_00018 +T P,0.35,2.9,17,8,18,0,0.75,0.75,7.3,7.3,8.7,12.75,tr_00017 +T P,0.35,2.9,16,10,17,0,0.75,0.75,7.3,7.3,3.9,12.75,tr_00016 +T P,0.35,2.9,2,9,16,0,0.75,0.75,7.3,7.3,5.7,12.75,tr_00015 +T P,0.35,5.9,11,2,7,0,0.75,0.75,13.3,13.3,17.1,11.25,tr_00014 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.1,9.3,tr_00013 +T P,0.35,2,7,14,13,0,0.75,0.75,5.5,5.5,15.3,9.3,tr_00012 +T N,0.35,2.9,11,2,3,0,0.75,0.75,7.3,7.3,18.9,3.75,tr_00011 +T N,0.35,1.7,1,9,2,0,0.75,0.75,4.9,4.9,7.5,2.55,tr_00010 +T N,0.35,1.7,2,6,5,0,0.75,0.75,4.9,4.9,5.7,2.55,tr_00009 +T N,0.35,1.7,12,13,3,0,0.75,0.75,4.9,4.9,12.3,1.95,tr_00008 +T N,0.35,1.7,2,15,12,0,0.75,0.75,4.9,4.9,13.5,1.95,tr_00007 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,8.7,2.55,tr_00006 +T N,0.35,2.9,3,2,11,0,0.75,0.75,7.3,7.3,17.1,3.75,tr_00005 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,3.9,2.55,tr_00004 +T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.5,1.95,tr_00003 +T N,0.35,1.1,13,14,3,0,0.75,0.75,3.7,3.7,15.3,4.95,tr_00002 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.1,5.25,tr_00001 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00170541 +S 16,INTERNAL +Q 0 +S 15,EXTERNAL,i0 +Q 0.00397942 +S 14,EXTERNAL,cmd0 +Q 0.00547246 +S 13,INTERNAL +Q 0.00589104 +S 12,INTERNAL +Q 0 +S 11,EXTERNAL,q +Q 0.00396596 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00864417 +S 6,INTERNAL +Q 0.00586794 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00823288 +S 2,INTERNAL +Q 0.00946154 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/mx3_x4.ap b/pdks/symbolic/sxlib/cells/mx3_x4.ap new file mode 100644 index 000000000..ae08a7ac0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx3_x4.ap @@ -0,0 +1,198 @@ +V ALLIANCE : 6 +H mx3_x4,P,13/ 6/2002,100 +A 0,0,7000,5000 +R 6000,4000,ref_ref,q_40 +R 6000,3500,ref_ref,q_35 +R 6000,3000,ref_ref,q_30 +R 6000,2500,ref_ref,q_25 +R 6000,1500,ref_ref,q_15 +R 6000,1000,ref_ref,q_10 +R 4500,2500,ref_ref,i0_25 +R 4000,3000,ref_ref,i0_30 +R 4000,2000,ref_ref,i0_20 +R 3500,3000,ref_ref,cmd0_30 +R 3500,2500,ref_ref,cmd0_25 +R 3500,2000,ref_ref,cmd0_20 +R 2500,2500,ref_ref,i1_25 +R 1500,2500,ref_ref,i2_25 +R 500,3500,ref_ref,cmd1_35 +R 500,3000,ref_ref,cmd1_30 +R 500,2500,ref_ref,cmd1_25 +R 500,2000,ref_ref,cmd1_20 +R 500,1500,ref_ref,cmd1_15 +R 6500,2000,ref_ref,q_20 +S 4800,3000,5000,3000,200,*,RIGHT,ALU1 +S 1000,1000,3200,1000,200,*,RIGHT,ALU1 +S 4800,1000,5500,1000,200,*,RIGHT,ALU1 +S 5500,1000,5500,3500,200,*,DOWN,ALU1 +S 4800,1500,4800,1700,200,*,DOWN,ALU1 +S 3300,1500,4800,1500,200,*,RIGHT,ALU1 +S 4800,1700,5000,1700,200,*,LEFT,ALU1 +S 5000,1700,5000,2950,200,*,DOWN,ALU1 +S 4300,2000,4300,3000,200,*,UP,ALU1 +S 4800,3500,4800,4000,200,*,DOWN,ALU1 +S 2200,3500,5500,3500,200,*,RIGHT,ALU1 +S 2700,2000,3000,2000,200,*,RIGHT,ALU1 +S 3000,2000,3000,3500,200,*,UP,ALU1 +S 2700,1500,2700,2000,200,*,UP,ALU1 +S 2200,1500,2700,1500,200,*,RIGHT,ALU1 +S 1000,4000,3200,4000,200,*,RIGHT,ALU1 +S 500,3500,1700,3500,200,*,LEFT,ALU1 +S 1000,3000,2400,3000,200,*,LEFT,ALU1 +S 1000,1600,1000,3000,200,*,UP,ALU1 +S 2000,2500,2500,2500,200,*,LEFT,ALU1 +S 1500,2100,1500,2500,200,*,DOWN,ALU1 +S 1000,1500,1700,1500,200,*,LEFT,ALU1 +S 700,2000,700,2600,100,*,DOWN,POLY +S 400,900,400,1800,300,*,DOWN,NDIF +S 700,1300,700,2000,100,*,DOWN,NTRANS +S 1000,1500,1000,1800,300,*,UP,NDIF +S 5100,1900,5100,2600,100,*,DOWN,POLY +S 5100,1300,5100,1900,100,*,DOWN,NTRANS +S 3500,2500,3800,2500,200,*,RIGHT,ALU1 +S 6100,2000,6500,2000,200,*,RIGHT,ALU1 +S 5500,2000,5600,2000,200,*,LEFT,ALU1 +S 4300,2500,4500,2500,200,*,LEFT,ALU1 +S 4000,2000,4300,2000,200,*,RIGHT,ALU1 +S 4000,3000,4300,3000,200,*,RIGHT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 400,2800,400,4000,300,*,UP,PDIF +S 6600,2800,6600,4700,300,*,UP,PDIF +S 6300,2600,6300,4900,100,*,UP,PTRANS +S 2500,3600,2500,4900,100,*,UP,PTRANS +S 3800,3800,3800,4700,200,*,UP,PDIF +S 3500,3600,3500,4900,100,*,UP,PTRANS +S 4100,3600,4100,4900,100,*,UP,PTRANS +S 4800,3800,4800,4700,300,*,UP,PDIF +S 4500,3600,4500,4900,100,*,UP,PTRANS +S 3200,3800,3200,4700,200,*,UP,PDIF +S 2900,3600,2900,4900,100,*,UP,PTRANS +S 1000,3800,1000,4700,300,*,UP,PDIF +S 1300,3600,1300,4900,100,*,UP,PTRANS +S 1600,3800,1600,4700,200,*,DOWN,PDIF +S 2200,3500,2200,4700,300,*,UP,PDIF +S 1900,3600,1900,4900,100,*,UP,PTRANS +S 5700,2600,5700,4900,100,*,UP,PTRANS +S 5400,2800,5400,4600,300,*,DOWN,PDIF +S 6000,2800,6000,4700,300,*,UP,PDIF +S 4800,2800,4800,3400,300,*,UP,PDIF +S 700,2600,700,3600,100,*,UP,PTRANS +S 5100,2600,5100,3600,100,*,UP,PTRANS +S 1000,2800,1000,3400,300,*,UP,PDIF +S 6600,800,6600,1700,300,*,DOWN,NDIF +S 6300,600,6300,1900,100,*,DOWN,NTRANS +S 2500,400,2500,1300,100,*,UP,NTRANS +S 1900,400,1900,1300,100,*,UP,NTRANS +S 4100,200,4100,1100,100,*,UP,NTRANS +S 4500,200,4500,1100,100,*,UP,NTRANS +S 3800,400,3800,900,200,*,DOWN,NDIF +S 2900,400,2900,1300,100,*,UP,NTRANS +S 5700,600,5700,1900,100,*,DOWN,NTRANS +S 6000,800,6000,1700,300,*,UP,NDIF +S 5400,500,5400,1700,300,*,DOWN,NDIF +S 1300,400,1300,1300,100,*,UP,NTRANS +S 3500,200,3500,1100,100,*,UP,NTRANS +S 3200,400,3200,1100,300,*,DOWN,NDIF +S 2200,600,2200,1600,300,*,UP,NDIF +S 1600,600,1600,1100,200,*,DOWN,NDIF +S 1000,600,1000,1000,300,*,DOWN,NDIF +S 5700,1900,5700,2600,100,*,DOWN,POLY +S 6300,1900,6300,2600,100,*,DOWN,POLY +S 1700,1500,1900,1500,100,*,RIGHT,POLY +S 400,2500,700,2500,300,*,RIGHT,POLY +S 5600,2000,6300,2000,100,*,RIGHT,POLY +S 3700,1900,3900,1900,100,*,LEFT,POLY +S 3700,1100,3700,1900,100,*,DOWN,POLY +S 3900,2500,5100,2500,100,*,RIGHT,POLY +S 1900,2000,1900,3600,100,*,DOWN,POLY +S 1900,2000,2500,2000,100,*,RIGHT,POLY +S 2500,3000,2500,3600,100,*,UP,POLY +S 3200,1500,3300,1500,100,*,LEFT,POLY +S 3500,1100,3700,1100,100,*,RIGHT,POLY +S 2500,1300,2500,2000,100,*,UP,POLY +S 2900,1300,2900,3600,100,*,DOWN,POLY +S 4100,1100,4100,1500,100,*,UP,POLY +S 2400,2500,2900,2500,100,*,RIGHT,POLY +S 4300,3000,4500,3000,100,*,RIGHT,POLY +S 4500,3000,4500,3600,100,*,UP,POLY +S 4400,2000,4500,2000,100,*,RIGHT,POLY +S 3900,1900,3900,3300,100,*,DOWN,POLY +S 3400,1500,3400,3600,100,*,UP,POLY +S 3400,3600,3500,3600,100,*,RIGHT,POLY +S 4500,1100,4500,2000,100,*,DOWN,POLY +S 3900,3600,4100,3600,100,*,LEFT,POLY +S 3900,3300,3900,3600,100,*,UP,POLY +S 1300,1300,1300,3600,100,*,DOWN,POLY +S 1900,1300,1900,1500,100,*,DOWN,POLY +S 6600,300,6600,1500,200,*,DOWN,ALU1 +S 400,400,400,1000,200,*,DOWN,ALU1 +S 6000,950,6000,1550,200,*,DOWN,ALU1 +S 6600,3000,6600,4600,200,*,UP,ALU1 +S 400,4000,400,4600,200,*,UP,ALU1 +S 6000,2450,6000,4000,200,*,DOWN,ALU1 +S 5950,2500,6150,2500,200,*,RIGHT,ALU1 +S 6100,1450,6100,2550,200,*,DOWN,ALU1 +S 5950,1500,6150,1500,200,*,LEFT,ALU1 +S 0,300,7000,300,600,vss,RIGHT,CALU1 +S 0,3900,7000,3900,2400,*,RIGHT,NWELL +S 0,4700,7000,4700,600,vdd,RIGHT,CALU1 +S 4800,400,4800,1000,300,*,UP,NDIF +S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1 +S 2500,2500,2500,2500,200,i1,LEFT,CALU1 +S 1500,2500,1500,2500,200,i2,LEFT,CALU1 +S 500,1500,500,3500,200,cmd1,DOWN,CALU1 +S 4500,2500,4500,2500,200,i0,LEFT,CALU1 +S 4000,3000,4000,3000,200,i0,LEFT,CALU1 +S 4000,2000,4000,2000,200,i0,LEFT,CALU1 +S 6000,2500,6000,4000,200,q,DOWN,CALU1 +S 6000,1000,6000,1500,200,q,DOWN,CALU1 +S 6500,2000,6500,2000,200,q,LEFT,CALU1 +S 1300,2500,1500,2500,300,*,LEFT,POLY +S 1700,3500,1900,3500,300,*,RIGHT,POLY +S 1700,1500,1900,1500,300,*,RIGHT,POLY +S 4300,2000,4500,2000,300,*,RIGHT,POLY +S 4300,3000,4500,3000,300,*,RIGHT,POLY +S 5900,300,6400,300,300,*,RIGHT,PTIE +V 1000,1600,CONT_DIF_N,* +V 4800,1600,CONT_DIF_N,* +V 2500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 400,4000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 3800,4500,CONT_DIF_P,* +V 2200,3500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 4800,4000,CONT_DIF_P,* +V 6600,4600,CONT_DIF_P,* +V 4800,3000,CONT_DIF_P,* +V 5400,4600,CONT_DIF_P,* +V 6000,3500,CONT_DIF_P,* +V 6000,4000,CONT_DIF_P,* +V 6000,3000,CONT_DIF_P,* +V 6600,4000,CONT_DIF_P,* +V 6600,3500,CONT_DIF_P,* +V 6600,3000,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 400,1000,CONT_DIF_N,* +V 6600,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 4800,1000,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 3800,500,CONT_DIF_N,* +V 5400,500,CONT_DIF_N,* +V 6000,1000,CONT_DIF_N,* +V 2200,1500,CONT_DIF_N,* +V 6000,1500,CONT_DIF_N,* +V 6600,1500,CONT_DIF_N,* +V 6000,300,CONT_BODY_P,* +V 400,2500,CONT_POLY,* +V 2400,3000,CONT_POLY,* +V 1700,3500,CONT_POLY,* +V 4100,1500,CONT_POLY,* +V 3300,1500,CONT_POLY,* +V 1700,1500,CONT_POLY,* +V 4300,3000,CONT_POLY,* +V 4300,2000,CONT_POLY,* +V 3800,2500,CONT_POLY,* +V 5600,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/mx3_x4.vbe b/pdks/symbolic/sxlib/cells/mx3_x4.vbe new file mode 100644 index 000000000..77baa4489 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx3_x4.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 810; + CONSTANT rdown_cmd1_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_cmd0_q : NATURAL := 890; + CONSTANT rup_cmd1_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 640; + CONSTANT tphh_cmd0_q : NATURAL := 683; + CONSTANT tphh_i1_q : NATURAL := 770; + CONSTANT tphh_i2_q : NATURAL := 770; + CONSTANT tpll_i0_q : NATURAL := 774; + CONSTANT tpll_cmd0_q : NATURAL := 779; + CONSTANT tphh_cmd1_q : NATURAL := 792; + CONSTANT tplh_cmd0_q : NATURAL := 844; + CONSTANT tplh_cmd1_q : NATURAL := 846; + CONSTANT tphl_cmd1_q : NATURAL := 872; + CONSTANT tphl_cmd0_q : NATURAL := 922; + CONSTANT tpll_i1_q : NATURAL := 948; + CONSTANT tpll_i2_q : NATURAL := 948; + CONSTANT tpll_cmd1_q : NATURAL := 967; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x4; + +ARCHITECTURE behaviour_data_flow OF mx3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mx3_x4" + SEVERITY WARNING; + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) + and i2)))) after 1600 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/mx3_x4.vhd b/pdks/symbolic/sxlib/cells/mx3_x4.vhd new file mode 100644 index 000000000..281c341ec --- /dev/null +++ b/pdks/symbolic/sxlib/cells/mx3_x4.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY mx3_x4 IS +PORT( + cmd0 : IN STD_LOGIC; + cmd1 : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END mx3_x4; + +ARCHITECTURE RTL OF mx3_x4 IS +BEGIN + q <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2)))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/na2_x1.al b/pdks/symbolic/sxlib/cells/na2_x1.al new file mode 100644 index 000000000..e9556bd68 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na2_x1.al @@ -0,0 +1,24 @@ +V ALLIANCE : 6 +H na2_x1,L,30/10/99 +C i0,IN,EXTERNAL,5 +C i1,IN,EXTERNAL,4 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,2 +T P,0.35,2.9,1,5,6,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00004 +T P,0.35,2.9,6,4,1,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00003 +T N,0.35,2.9,2,5,3,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00002 +T N,0.35,2.9,3,4,1,0,0.75,0.75,7.3,7.3,3.3,3.75,tr_00001 +S 6,EXTERNAL,vdd +Q 0.00282047 +S 5,EXTERNAL,i0 +Q 0.00353623 +S 4,EXTERNAL,i1 +Q 0.00368237 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.0026442 +S 1,EXTERNAL,nq +Q 0.00279086 +EOF diff --git a/pdks/symbolic/sxlib/cells/na2_x1.ap b/pdks/symbolic/sxlib/cells/na2_x1.ap new file mode 100644 index 000000000..072191685 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na2_x1.ap @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H na2_x1,P, 8/ 6/2002,100 +A 0,0,2000,5000 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1000,4000,ref_ref,nq_40 +R 1500,4000,ref_ref,i1_40 +R 1500,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i1_25 +R 1500,2000,ref_ref,i1_20 +R 1500,1500,ref_ref,i1_15 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +S 1200,300,1700,300,300,*,RIGHT,PTIE +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +S 1500,1500,1500,4000,200,i1,DOWN,CALU1 +S 500,1000,500,4000,200,i0,DOWN,CALU1 +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +S 400,3000,700,3000,300,*,RIGHT,POLY +S 1500,1500,1500,4000,100,*,DOWN,ALU1 +S 1600,3300,1600,4600,300,*,DOWN,PDIF +S 400,3300,400,4600,300,*,DOWN,PDIF +S 700,3100,700,4400,100,*,UP,PTRANS +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 1300,2000,1600,2000,300,*,RIGHT,POLY +S 1300,1900,1300,3100,100,*,DOWN,POLY +S 700,600,700,1900,100,*,DOWN,NTRANS +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 700,1900,700,3100,100,*,UP,POLY +S 1100,1900,1600,1900,100,*,RIGHT,POLY +S 1000,1000,1400,1000,200,*,RIGHT,ALU1 +S 1400,800,1400,1700,300,*,UP,NDIF +S 400,400,400,1700,300,*,UP,NDIF +S 1000,950,1000,4000,200,*,UP,ALU1 +V 500,3000,CONT_POLY,* +V 1600,4500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1500,2000,CONT_POLY,* +V 400,500,CONT_DIF_N,* +V 1400,1000,CONT_DIF_N,* +V 1250,300,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/na2_x1.sym b/pdks/symbolic/sxlib/cells/na2_x1.sym new file mode 100644 index 000000000..0ef443c8a Binary files /dev/null and b/pdks/symbolic/sxlib/cells/na2_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/na2_x1.vbe b/pdks/symbolic/sxlib/cells/na2_x1.vbe new file mode 100644 index 000000000..486b6aaf0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 59; + CONSTANT tphl_i1_nq : NATURAL := 111; + CONSTANT tplh_i1_nq : NATURAL := 234; + CONSTANT tplh_i0_nq : NATURAL := 288; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x1; + +ARCHITECTURE behaviour_data_flow OF na2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x1" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 900 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/na2_x1.vhd b/pdks/symbolic/sxlib/cells/na2_x1.vhd new file mode 100644 index 000000000..23b74f776 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na2_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na2_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na2_x1; + +ARCHITECTURE RTL OF na2_x1 IS +BEGIN + nq <= NOT((i0 AND i1)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/na2_x4.al b/pdks/symbolic/sxlib/cells/na2_x4.al new file mode 100644 index 000000000..49769d581 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na2_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H na2_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,6,3,5,0,0.75,0.75,7.3,7.3,8.7,9.75,tr_00010 +T P,0.35,5.9,2,6,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,5,6,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,2.9,3,8,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T P,0.35,2.9,5,7,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00006 +T N,0.35,2.9,1,6,2,0,0.75,0.75,7.3,7.3,5.1,2.25,tr_00005 +T N,0.35,2.9,2,6,1,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00004 +T N,0.35,1.4,1,3,6,0,0.75,0.75,4.3,4.3,8.7,3,tr_00003 +T N,0.35,2.9,4,7,1,0,0.75,0.75,7.3,7.3,3.3,3.75,tr_00002 +T N,0.35,2.9,3,8,4,0,0.75,0.75,7.3,7.3,1.8,3.75,tr_00001 +S 8,EXTERNAL,i0 +Q 0.00260759 +S 7,EXTERNAL,i1 +Q 0.00297253 +S 6,INTERNAL +Q 0.0060306 +S 5,EXTERNAL,vdd +Q 0.0046087 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00560951 +S 2,EXTERNAL,nq +Q 0.00214456 +S 1,EXTERNAL,vss +Q 0.00419742 +EOF diff --git a/pdks/symbolic/sxlib/cells/na2_x4.ap b/pdks/symbolic/sxlib/cells/na2_x4.ap new file mode 100644 index 000000000..fbbbb6386 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na2_x4.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H na2_x4,P,18/ 5/2002,100 +A 0,0,3500,5000 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 2000,3500,ref_ref,nq_35 +R 2000,3000,ref_ref,nq_30 +R 2000,2500,ref_ref,nq_25 +R 2000,2000,ref_ref,nq_20 +R 2000,1500,ref_ref,nq_15 +R 2000,1000,ref_ref,nq_10 +S 300,4000,300,4500,200,*,UP,ALU1 +S 2000,1000,2000,3550,200,*,DOWN,ALU1 +S 1400,300,1400,1700,300,*,UP,NDIF +S 600,1900,600,3100,100,*,DOWN,POLY +S 600,600,600,1900,100,*,DOWN,NTRANS +S 900,800,900,1700,300,*,UP,NDIF +S 300,800,300,1700,300,*,UP,NDIF +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 2400,1900,2400,2600,100,*,DOWN,POLY +S 1800,1900,1800,2600,100,*,DOWN,POLY +S 2300,1400,2300,1900,100,*,DOWN,POLY +S 1700,1400,1700,2100,100,*,UP,POLY +S 1700,2000,2600,2000,300,*,RIGHT,POLY +S 2500,2000,3200,2000,100,*,LEFT,ALU1 +S 900,2000,1200,2000,300,*,RIGHT,POLY +S 1200,1900,1200,3100,100,*,UP,POLY +S 2700,4300,2700,4700,300,*,UP,PDIF +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 300,3300,300,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 850,3700,850,4200,200,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 3200,1000,3200,3500,100,*,DOWN,ALU1 +S 900,4000,3000,4000,100,*,RIGHT,ALU1 +S 500,1500,500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 300,1000,1500,1000,100,*,RIGHT,ALU1 +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 3200,2800,3200,3700,300,*,UP,PDIF +S 2900,2600,2900,3900,100,*,UP,PTRANS +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 3200,800,3200,1200,300,*,DOWN,NDIF +S 2900,600,2900,1400,100,*,DOWN,NTRANS +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 2600,300,2600,1200,300,*,UP,NDIF +S 2300,100,2300,1400,100,*,DOWN,NTRANS +S 2000,300,2000,1200,300,*,UP,NDIF +S 1700,100,1700,1400,100,*,DOWN,NTRANS +S 300,300,900,300,300,*,LEFT,PTIE +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +S 2000,1000,2000,3500,200,nq,DOWN,CALU1 +V 300,4000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 2500,2000,CONT_POLY,* +V 900,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 3200,3500,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 800,300,CONT_BODY_P,* +V 3200,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 2600,500,CONT_DIF_N,* +V 1400,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 300,300,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/na2_x4.sym b/pdks/symbolic/sxlib/cells/na2_x4.sym new file mode 100644 index 000000000..be1b6080d Binary files /dev/null and b/pdks/symbolic/sxlib/cells/na2_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/na2_x4.vbe b/pdks/symbolic/sxlib/cells/na2_x4.vbe new file mode 100644 index 000000000..c73eca058 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY na2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 353; + CONSTANT tphl_i0_nq : NATURAL := 412; + CONSTANT tplh_i0_nq : NATURAL := 552; + CONSTANT tplh_i1_nq : NATURAL := 601; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x4; + +ARCHITECTURE behaviour_data_flow OF na2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na2_x4" + SEVERITY WARNING; + nq <= not ((i0 and i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/na2_x4.vhd b/pdks/symbolic/sxlib/cells/na2_x4.vhd new file mode 100644 index 000000000..ef555cb4b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na2_x4; + +ARCHITECTURE RTL OF na2_x4 IS +BEGIN + nq <= NOT((i0 AND i1)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/na3_x1.al b/pdks/symbolic/sxlib/cells/na3_x1.al new file mode 100644 index 000000000..e2da070ad --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na3_x1.al @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H na3_x1,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,5 +C i2,IN,EXTERNAL,6 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,8 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,2,7,8,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00006 +T P,0.35,2.9,2,6,8,0,0.75,0.75,7.3,7.3,5.7,11.25,tr_00005 +T P,0.35,2.9,8,5,2,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00004 +T N,0.35,2.9,1,6,2,0,0.75,0.75,7.3,7.3,4.2,2.25,tr_00003 +T N,0.35,2.9,4,5,1,0,0.75,0.75,7.3,7.3,3,2.25,tr_00002 +T N,0.35,2.9,3,7,4,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 8,EXTERNAL,vdd +Q 0.0033382 +S 7,EXTERNAL,i0 +Q 0.00388325 +S 6,EXTERNAL,i2 +Q 0.00352565 +S 5,EXTERNAL,i1 +Q 0.00390877 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00298567 +S 2,EXTERNAL,nq +Q 0.00346654 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/na3_x1.ap b/pdks/symbolic/sxlib/cells/na3_x1.ap new file mode 100644 index 000000000..d36ff7952 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na3_x1.ap @@ -0,0 +1,74 @@ +V ALLIANCE : 6 +H na3_x1,P,18/ 5/2002,100 +A 0,0,2500,5000 +R 2000,4000,ref_ref,nq_40 +R 2000,3500,ref_ref,nq_35 +R 2000,2500,ref_ref,nq_25 +R 2000,3000,ref_ref,nq_30 +R 2000,2000,ref_ref,nq_20 +R 2000,1500,ref_ref,nq_15 +R 2000,1000,ref_ref,nq_10 +R 500,4000,ref_ref,i0_40 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 1500,3500,ref_ref,i2_35 +R 1500,3000,ref_ref,i2_30 +R 1500,2500,ref_ref,i2_25 +R 1500,2000,ref_ref,i2_20 +R 1500,1500,ref_ref,i2_15 +R 1500,1000,ref_ref,i2_10 +S 1000,4000,2200,4000,200,*,RIGHT,ALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 1700,900,1700,1200,300,*,DOWN,NDIF +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 800,300,800,1200,300,*,UP,NDIF +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,UP,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,200,*,UP,NDIF +S 1900,800,1900,1200,500,*,UP,NDIF +S 2200,3300,2200,4200,300,*,DOWN,PDIF +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 400,3300,400,4600,300,*,DOWN,PDIF +S 1600,3300,1600,4600,300,*,DOWN,PDIF +S 1900,3100,1900,4400,100,*,UP,PTRANS +S 700,3100,700,4400,100,*,UP,PTRANS +S 1900,1600,1900,3100,100,*,DOWN,POLY +S 1400,1600,1900,1600,100,*,LEFT,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 400,3000,700,3000,300,*,RIGHT,POLY +S 900,2000,1300,2000,300,*,RIGHT,POLY +S 1300,1900,1300,3100,100,*,DOWN,POLY +S 1000,1400,1000,2100,100,*,UP,POLY +S 2000,4000,2200,4000,200,*,RIGHT,ALU1 +S 2000,1000,2000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,4000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +V 300,500,CONT_DIF_N,* +V 1500,1500,CONT_POLY,* +V 2000,1000,CONT_DIF_N,* +V 2200,4000,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 500,3000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/na3_x1.sym b/pdks/symbolic/sxlib/cells/na3_x1.sym new file mode 100644 index 000000000..f2d1f56c5 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/na3_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/na3_x1.vbe b/pdks/symbolic/sxlib/cells/na3_x1.vbe new file mode 100644 index 000000000..d51e12075 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 4120; + CONSTANT rdown_i1_nq : NATURAL := 4120; + CONSTANT rdown_i2_nq : NATURAL := 4120; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 119; + CONSTANT tphl_i1_nq : NATURAL := 171; + CONSTANT tphl_i2_nq : NATURAL := 193; + CONSTANT tplh_i2_nq : NATURAL := 265; + CONSTANT tplh_i1_nq : NATURAL := 316; + CONSTANT tplh_i0_nq : NATURAL := 363; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x1; + +ARCHITECTURE behaviour_data_flow OF na3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/na3_x1.vhd b/pdks/symbolic/sxlib/cells/na3_x1.vhd new file mode 100644 index 000000000..278daf099 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na3_x1.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na3_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na3_x1; + +ARCHITECTURE RTL OF na3_x1 IS +BEGIN + nq <= NOT(((i0 AND i1) AND i2)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/na3_x4.al b/pdks/symbolic/sxlib/cells/na3_x4.al new file mode 100644 index 000000000..caa069a8e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na3_x4.al @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H na3_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,5 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,4 +T P,0.35,2.9,6,9,3,0,0.75,0.75,7.3,7.3,5.4,10.95,tr_00012 +T P,0.35,2.9,3,10,6,0,0.75,0.75,7.3,7.3,3.6,10.95,tr_00011 +T P,0.35,2.9,6,8,3,0,0.75,0.75,7.3,7.3,1.8,10.95,tr_00010 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00009 +T P,0.35,2.9,7,3,6,0,0.75,0.75,7.3,7.3,10.2,9.75,tr_00008 +T P,0.35,5.9,5,7,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00007 +T N,0.35,2.9,2,9,4,0,0.75,0.75,7.3,7.3,4.5,3.75,tr_00006 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00005 +T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,3.3,3.75,tr_00004 +T N,0.35,2.9,4,7,5,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,5,7,4,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00002 +T N,0.35,1.4,4,3,7,0,0.75,0.75,4.3,4.3,10.2,3,tr_00001 +S 10,EXTERNAL,i2 +Q 0.00312291 +S 9,EXTERNAL,i1 +Q 0.00275797 +S 8,EXTERNAL,i0 +Q 0.00290312 +S 7,INTERNAL +Q 0.0060306 +S 6,EXTERNAL,vdd +Q 0.00436263 +S 5,EXTERNAL,nq +Q 0.00214456 +S 4,EXTERNAL,vss +Q 0.00436263 +S 3,INTERNAL +Q 0.00663132 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/na3_x4.ap b/pdks/symbolic/sxlib/cells/na3_x4.ap new file mode 100644 index 000000000..1c7f61c46 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na3_x4.ap @@ -0,0 +1,102 @@ +V ALLIANCE : 6 +H na3_x4,P,18/ 5/2002,100 +A 0,0,4000,5000 +R 1000,1500,ref_ref,i2_15 +R 1000,2000,ref_ref,i2_20 +R 1000,2500,ref_ref,i2_25 +R 1000,3000,ref_ref,i2_30 +R 1000,3500,ref_ref,i2_35 +R 2500,3500,ref_ref,nq_35 +R 2500,3000,ref_ref,nq_30 +R 2500,2500,ref_ref,nq_25 +R 2500,2000,ref_ref,nq_20 +R 2500,1500,ref_ref,nq_15 +R 2500,1000,ref_ref,nq_10 +R 1500,1500,ref_ref,i1_15 +R 1500,2000,ref_ref,i1_20 +R 1500,2500,ref_ref,i1_25 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i1_35 +R 1500,3000,ref_ref,i1_30 +S 200,300,1200,300,300,*,RIGHT,PTIE +S 2500,1000,2500,3550,200,*,DOWN,ALU1 +S 3700,1000,3700,3500,100,*,DOWN,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 3000,2000,3700,2000,100,*,LEFT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 2900,1900,2900,2600,100,*,DOWN,POLY +S 2300,1900,2300,2600,100,*,DOWN,POLY +S 2800,1400,2800,1900,100,*,DOWN,POLY +S 2200,1400,2200,2100,100,*,UP,POLY +S 2200,2000,3100,2000,300,*,RIGHT,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 3700,2800,3700,3700,300,*,UP,PDIF +S 3400,2600,3400,3900,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 3400,600,3400,1400,100,*,DOWN,NTRANS +S 3100,300,3100,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 2200,100,2200,1400,100,*,DOWN,NTRANS +S 1900,300,1900,1700,300,*,UP,NDIF +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 3700,800,3700,1200,300,*,DOWN,NDIF +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 700,600,700,1900,100,*,DOWN,NTRANS +S 1500,600,1500,1900,100,*,DOWN,NTRANS +S 1800,300,1800,1700,300,*,UP,NDIF +S 400,800,400,1700,300,*,UP,NDIF +S 400,1000,2000,1000,100,*,RIGHT,ALU1 +S 300,4000,3500,4000,100,*,RIGHT,ALU1 +S 400,2000,700,2000,300,*,RIGHT,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1400,2100,1800,2100,100,*,RIGHT,POLY +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,3000,600,4300,100,*,UP,PTRANS +S 1200,3000,1200,4300,100,*,UP,PTRANS +S 1500,3200,1500,4100,300,*,DOWN,PDIF +S 1800,3000,1800,4300,100,*,UP,PTRANS +S 300,3200,300,4100,300,*,DOWN,PDIF +S 900,3200,900,4600,300,*,DOWN,PDIF +S 1800,2100,1800,3000,100,*,DOWN,POLY +S 1200,2400,1200,3000,100,*,DOWN,POLY +S 600,1900,600,3000,100,*,DOWN,POLY +S 900,2500,1200,2500,300,*,RIGHT,POLY +S 1100,1900,1100,2600,100,*,UP,POLY +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1000,1500,1000,3500,200,i2,DOWN,CALU1 +S 2500,1000,2500,3500,200,nq,DOWN,CALU1 +S 1500,1500,1500,3500,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i0,DOWN,CALU1 +V 1100,300,CONT_BODY_P,* +V 700,300,CONT_BODY_P,* +V 2000,4600,CONT_DIF_P,* +V 1000,2500,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3500,4000,CONT_POLY,* +V 2600,3500,CONT_DIF_P,* +V 2600,3000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 2500,1000,CONT_DIF_N,* +V 3100,500,CONT_DIF_N,* +V 1900,500,CONT_DIF_N,* +V 400,1000,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 3200,4600,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 300,300,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/na3_x4.sym b/pdks/symbolic/sxlib/cells/na3_x4.sym new file mode 100644 index 000000000..951469080 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/na3_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/na3_x4.vbe b/pdks/symbolic/sxlib/cells/na3_x4.vbe new file mode 100644 index 000000000..160a97f61 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY na3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 460; + CONSTANT tphl_i2_nq : NATURAL := 519; + CONSTANT tphl_i0_nq : NATURAL := 556; + CONSTANT tplh_i0_nq : NATURAL := 601; + CONSTANT tplh_i2_nq : NATURAL := 647; + CONSTANT tplh_i1_nq : NATURAL := 691; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x4; + +ARCHITECTURE behaviour_data_flow OF na3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na3_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) and i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/na3_x4.vhd b/pdks/symbolic/sxlib/cells/na3_x4.vhd new file mode 100644 index 000000000..ccf28ce79 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na3_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na3_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na3_x4; + +ARCHITECTURE RTL OF na3_x4 IS +BEGIN + nq <= NOT(((i0 AND i1) AND i2)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/na4_x1.al b/pdks/symbolic/sxlib/cells/na4_x1.al new file mode 100644 index 000000000..3287ed3c4 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na4_x1.al @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H na4_x1,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,6 +C i3,IN,EXTERNAL,9 +C nq,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,10,7,4,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,2.9,4,6,10,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00007 +T P,0.35,2.9,10,9,4,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00006 +T P,0.35,2.9,4,8,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00005 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00004 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3,2.25,tr_00003 +T N,0.35,2.9,2,6,5,0,0.75,0.75,7.3,7.3,4.2,2.25,tr_00002 +T N,0.35,2.9,5,9,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 10,EXTERNAL,vdd +Q 0.00444349 +S 9,EXTERNAL,i3 +Q 0.00381484 +S 8,EXTERNAL,i0 +Q 0.00323647 +S 7,EXTERNAL,i1 +Q 0.00345625 +S 6,EXTERNAL,i2 +Q 0.00367603 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,nq +Q 0.0035253 +S 3,EXTERNAL,vss +Q 0.00332715 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/na4_x1.ap b/pdks/symbolic/sxlib/cells/na4_x1.ap new file mode 100644 index 000000000..89ba4fc98 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na4_x1.ap @@ -0,0 +1,87 @@ +V ALLIANCE : 6 +H na4_x1,P,18/ 5/2002,100 +A 0,0,3000,5000 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 500,1000,ref_ref,i0_10 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1500,3500,ref_ref,i2_35 +R 1500,3000,ref_ref,i2_30 +R 1500,2500,ref_ref,i2_25 +R 1500,2000,ref_ref,i2_20 +R 1500,1500,ref_ref,i2_15 +R 1500,1000,ref_ref,i2_10 +R 2000,1000,ref_ref,i3_10 +R 2000,1500,ref_ref,i3_15 +R 2000,2000,ref_ref,i3_20 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2000,3500,ref_ref,i3_35 +R 2500,3500,ref_ref,nq_35 +R 2500,3000,ref_ref,nq_30 +R 2500,2500,ref_ref,nq_25 +R 2500,2000,ref_ref,nq_20 +R 2500,1500,ref_ref,nq_15 +R 2500,1000,ref_ref,nq_10 +R 2500,4000,ref_ref,nq_40 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 1500,1000,1500,3500,200,i2,DOWN,CALU1 +S 2000,1000,2000,3500,200,i3,DOWN,CALU1 +S 2500,1000,2500,4000,200,nq,DOWN,CALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 900,3300,900,4200,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 600,3100,600,4400,100,*,UP,PTRANS +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 1500,3300,1500,4600,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 2000,1000,2000,3500,100,*,DOWN,ALU1 +S 2300,800,2300,1200,700,*,UP,NDIF +S 1000,1400,1000,3100,100,*,UP,POLY +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1400,2600,1800,2600,100,*,RIGHT,POLY +S 1800,2600,1800,3100,100,*,UP,POLY +S 1800,1400,1800,1900,100,*,UP,POLY +S 1800,1900,2400,1900,100,*,RIGHT,POLY +S 2400,1900,2400,3100,100,*,UP,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 2500,1000,2500,4050,200,*,UP,ALU1 +S 900,4000,2550,4000,200,*,LEFT,ALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +V 300,500,CONT_DIF_N,* +V 1500,4500,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2500,1000,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/na4_x1.sym b/pdks/symbolic/sxlib/cells/na4_x1.sym new file mode 100644 index 000000000..17cafb1e0 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/na4_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/na4_x1.vbe b/pdks/symbolic/sxlib/cells/na4_x1.vbe new file mode 100644 index 000000000..07f51ce0b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 5400; + CONSTANT rdown_i1_nq : NATURAL := 5400; + CONSTANT rdown_i2_nq : NATURAL := 5400; + CONSTANT rdown_i3_nq : NATURAL := 5400; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT rup_i3_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 179; + CONSTANT tphl_i1_nq : NATURAL := 237; + CONSTANT tphl_i2_nq : NATURAL := 269; + CONSTANT tphl_i3_nq : NATURAL := 282; + CONSTANT tplh_i3_nq : NATURAL := 302; + CONSTANT tplh_i2_nq : NATURAL := 350; + CONSTANT tplh_i1_nq : NATURAL := 395; + CONSTANT tplh_i0_nq : NATURAL := 438; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x1; + +ARCHITECTURE behaviour_data_flow OF na4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/na4_x1.vhd b/pdks/symbolic/sxlib/cells/na4_x1.vhd new file mode 100644 index 000000000..cedcb1c0f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na4_x1.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na4_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na4_x1; + +ARCHITECTURE RTL OF na4_x1 IS +BEGIN + nq <= NOT((((i0 AND i1) AND i2) AND i3)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/na4_x4.al b/pdks/symbolic/sxlib/cells/na4_x4.al new file mode 100644 index 000000000..111fa2f3e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na4_x4.al @@ -0,0 +1,48 @@ +V ALLIANCE : 6 +H na4_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,11 +C i3,IN,EXTERNAL,12 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,5,12,7,0,0.75,0.75,7.3,7.3,13.2,11.25,tr_00014 +T P,0.35,2.9,7,11,5,0,0.75,0.75,7.3,7.3,11.4,11.25,tr_00013 +T P,0.35,2.9,5,8,7,0,0.75,0.75,7.3,7.3,9.6,11.25,tr_00012 +T P,0.35,2.9,7,6,5,0,0.75,0.75,7.3,7.3,7.8,11.25,tr_00011 +T P,0.35,5.9,2,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T P,0.35,5.9,5,4,2,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,2.9,5,7,4,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00008 +T N,0.35,2.9,9,11,10,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00007 +T N,0.35,2.9,1,8,9,0,0.75,0.75,7.3,7.3,9,2.25,tr_00006 +T N,0.35,2.9,3,6,1,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00005 +T N,0.35,2.9,10,12,7,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00004 +T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003 +T N,0.35,2.9,3,4,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,1.4,4,7,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 12,EXTERNAL,i3 +Q 0.00381484 +S 11,EXTERNAL,i2 +Q 0.00367603 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0 +S 8,EXTERNAL,i1 +Q 0.00345625 +S 7,INTERNAL +Q 0.00793105 +S 6,EXTERNAL,i0 +Q 0.00323647 +S 5,EXTERNAL,vdd +Q 0.00557437 +S 4,INTERNAL +Q 0.00589179 +S 3,EXTERNAL,vss +Q 0.00504558 +S 2,EXTERNAL,nq +Q 0.00211518 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/na4_x4.ap b/pdks/symbolic/sxlib/cells/na4_x4.ap new file mode 100644 index 000000000..9923b6d9f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na4_x4.ap @@ -0,0 +1,123 @@ +V ALLIANCE : 6 +H na4_x4,P, 8/ 6/2002,100 +A 0,0,5000,5000 +R 1500,1000,ref_ref,nq_10 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 3500,1500,ref_ref,i2_15 +R 3500,1000,ref_ref,i2_10 +R 4000,1000,ref_ref,i3_10 +R 4000,1500,ref_ref,i3_15 +R 4000,2000,ref_ref,i3_20 +R 4000,2500,ref_ref,i3_25 +R 4000,3000,ref_ref,i3_30 +R 4000,3500,ref_ref,i3_35 +R 3000,2000,ref_ref,i1_20 +R 3000,2500,ref_ref,i1_25 +R 3000,3000,ref_ref,i1_30 +R 3000,3500,ref_ref,i1_35 +R 3500,3500,ref_ref,i2_35 +R 3500,3000,ref_ref,i2_30 +R 3500,2500,ref_ref,i2_25 +R 3500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i0_15 +R 2500,2000,ref_ref,i0_20 +R 2500,2500,ref_ref,i0_25 +R 2500,3000,ref_ref,i0_30 +R 2500,3500,ref_ref,i0_35 +R 2500,1000,ref_ref,i0_10 +R 3000,1000,ref_ref,i1_10 +R 3000,1500,ref_ref,i1_15 +S 300,4300,300,4800,300,*,DOWN,NTIE +S 300,3000,300,3500,100,*,DOWN,ALU1 +S 4550,1000,4550,4000,100,*,UP,ALU1 +S 4400,1900,4400,3100,100,*,UP,POLY +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 2300,3300,2300,4700,300,*,DOWN,PDIF +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 300,1000,300,3000,100,*,DOWN,ALU1 +S 600,2500,800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,2600,600,3900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,DOWN,PDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 3800,100,3800,1400,100,*,DOWN,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 4300,800,4300,1200,700,*,UP,NDIF +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2600,100,2600,1400,100,*,DOWN,NTRANS +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2600,3100,2600,4400,100,*,UP,PTRANS +S 4700,3300,4700,4600,300,*,DOWN,PDIF +S 3500,3300,3500,4600,300,*,DOWN,PDIF +S 4100,3300,4100,4200,300,*,DOWN,PDIF +S 2900,3300,2900,4200,300,*,DOWN,PDIF +S 3200,3100,3200,4400,100,*,UP,PTRANS +S 3800,3100,3800,4400,100,*,UP,PTRANS +S 4400,3100,4400,4400,100,*,UP,PTRANS +S 2600,1400,2600,3100,100,*,DOWN,POLY +S 3000,1400,3000,3100,100,*,UP,POLY +S 3000,3100,3200,3100,100,*,RIGHT,POLY +S 3400,1400,3400,2600,100,*,UP,POLY +S 3400,2600,3800,2600,100,*,RIGHT,POLY +S 3800,2600,3800,3100,100,*,UP,POLY +S 3800,1400,3800,1900,100,*,UP,POLY +S 3800,1900,4400,1900,100,*,RIGHT,POLY +S 2500,1000,2500,3500,100,*,DOWN,ALU1 +S 3000,1000,3000,3500,100,*,DOWN,ALU1 +S 3500,1000,3500,3500,100,*,DOWN,ALU1 +S 4000,1000,4000,3500,100,*,DOWN,ALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 1500,1000,1500,3500,200,*,UP,ALU1 +S 1050,1500,1050,4000,100,*,DOWN,ALU1 +S 800,2500,1050,2500,200,*,RIGHT,ALU1 +S 800,1500,1050,1500,200,*,RIGHT,ALU1 +S 600,2000,1800,2000,300,*,RIGHT,POLY +S 300,2000,600,2000,200,*,LEFT,ALU1 +S 1050,4000,4550,4000,100,*,LEFT,ALU1 +S 1500,1000,1500,3500,200,nq,DOWN,CALU1 +S 3500,1000,3500,3500,200,i2,DOWN,CALU1 +S 4000,1000,4000,3500,200,i3,DOWN,CALU1 +S 3000,1000,3000,3500,200,i1,DOWN,CALU1 +S 2500,1000,2500,3500,200,i0,DOWN,CALU1 +V 300,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 2200,500,CONT_DIF_N,* +V 2200,4500,CONT_DIF_P,* +V 800,1500,CONT_POLY,* +V 800,2500,CONT_POLY,* +V 300,4700,CONT_BODY_N,* +V 300,3000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 4500,1000,CONT_DIF_N,* +V 2900,4000,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 3500,4500,CONT_DIF_P,* +V 4700,4500,CONT_DIF_P,* +V 3000,2000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 600,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/na4_x4.sym b/pdks/symbolic/sxlib/cells/na4_x4.sym new file mode 100644 index 000000000..9b5c878b4 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/na4_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/na4_x4.vbe b/pdks/symbolic/sxlib/cells/na4_x4.vbe new file mode 100644 index 000000000..a67d18901 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY na4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 578; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i3_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 681; + CONSTANT tplh_i2_nq : NATURAL := 689; + CONSTANT tphl_i3_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 731; + CONSTANT tplh_i0_nq : NATURAL := 771; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x4; + +ARCHITECTURE behaviour_data_flow OF na4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on na4_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) and i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/na4_x4.vhd b/pdks/symbolic/sxlib/cells/na4_x4.vhd new file mode 100644 index 000000000..5593da222 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/na4_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY na4_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END na4_x4; + +ARCHITECTURE RTL OF na4_x4 IS +BEGIN + nq <= NOT((((i0 AND i1) AND i2) AND i3)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nao22_x1.al b/pdks/symbolic/sxlib/cells/nao22_x1.al new file mode 100644 index 000000000..22bbb6dcc --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao22_x1.al @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H nao22_x1,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,4,8,1,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,5.9,5,6,4,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00005 +T P,0.35,5.9,1,7,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00004 +T N,0.35,2.9,2,6,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00003 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 8,EXTERNAL,i2 +Q 0.00344864 +S 7,EXTERNAL,i1 +Q 0.00288494 +S 6,EXTERNAL,i0 +Q 0.00260759 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00473727 +S 3,EXTERNAL,vss +Q 0.00432598 +S 2,INTERNAL +Q 0.00114171 +S 1,EXTERNAL,nq +Q 0.00282024 +EOF diff --git a/pdks/symbolic/sxlib/cells/nao22_x1.ap b/pdks/symbolic/sxlib/cells/nao22_x1.ap new file mode 100644 index 000000000..f23afedb0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao22_x1.ap @@ -0,0 +1,81 @@ +V ALLIANCE : 6 +H nao22_x1,P, 8/ 6/2002,100 +A 0,0,3000,5000 +R 2000,1000,ref_ref,i2_10 +R 2000,4000,ref_ref,i2_40 +R 1500,4000,ref_ref,nq_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 1500,1500,ref_ref,nq_15 +R 1500,2000,ref_ref,nq_20 +R 1500,2500,ref_ref,nq_25 +R 1500,3000,ref_ref,nq_30 +R 1500,3500,ref_ref,nq_35 +S 2700,200,2700,700,300,*,UP,PTIE +S 2700,1300,2700,1800,300,*,DOWN,PTIE +S 2700,2800,2700,3300,300,*,UP,NTIE +S 2700,4300,2700,4800,300,*,DOWN,NTIE +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 1500,1500,1500,4000,200,nq,DOWN,CALU1 +S 2000,1000,2000,4000,100,*,DOWN,ALU1 +S 2700,500,2700,1700,200,*,DOWN,ALU1 +S 2700,2900,2700,4500,200,*,DOWN,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 300,1000,1500,1000,100,*,RIGHT,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 900,300,900,1600,300,*,UP,NDIF +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1500,1450,1500,4000,200,*,UP,ALU1 +S 900,1500,1550,1500,200,*,RIGHT,ALU1 +V 2700,300,CONT_BODY_P,* +V 2700,4700,CONT_BODY_N,* +V 2700,2900,CONT_BODY_N,* +V 2700,1700,CONT_BODY_P,* +V 2100,4500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 300,4500,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nao22_x1.sym b/pdks/symbolic/sxlib/cells/nao22_x1.sym new file mode 100644 index 000000000..865b45a34 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/nao22_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/nao22_x1.vbe b/pdks/symbolic/sxlib/cells/nao22_x1.vbe new file mode 100644 index 000000000..13c4e6dec --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 1790; + CONSTANT tphl_i2_nq : NATURAL := 165; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tplh_i2_nq : NATURAL := 238; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x1; + +ARCHITECTURE behaviour_data_flow OF nao22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 900 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/nao22_x1.vhd b/pdks/symbolic/sxlib/cells/nao22_x1.vhd new file mode 100644 index 000000000..7873413cf --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao22_x1.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nao22_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nao22_x1; + +ARCHITECTURE RTL OF nao22_x1 IS +BEGIN + nq <= NOT(((i0 OR i1) AND i2)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nao22_x4.al b/pdks/symbolic/sxlib/cells/nao22_x4.al new file mode 100644 index 000000000..1be1c88ac --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao22_x4.al @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H nao22_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C i2,IN,EXTERNAL,5 +C nq,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,9 +C vss,IN,EXTERNAL,4 +T P,0.35,2.9,10,6,3,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00012 +T P,0.35,2.9,9,7,10,0,0.75,0.75,7.3,7.3,5.7,11.25,tr_00011 +T P,0.35,2.9,3,5,9,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00010 +T P,0.35,2.9,9,3,2,0,0.75,0.75,7.3,7.3,9.3,9.75,tr_00009 +T P,0.35,5.9,9,2,8,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00008 +T P,0.35,5.9,8,2,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00007 +T N,0.35,1.4,4,5,1,0,0.75,0.75,4.3,4.3,2.1,3,tr_00006 +T N,0.35,2.9,4,2,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00005 +T N,0.35,1.4,1,6,3,0,0.75,0.75,4.3,4.3,3.9,3,tr_00004 +T N,0.35,1.4,3,7,1,0,0.75,0.75,4.3,4.3,5.7,3,tr_00003 +T N,0.35,1.4,2,3,4,0,0.75,0.75,4.3,4.3,9.3,3,tr_00002 +T N,0.35,2.9,8,2,4,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00001 +S 10,INTERNAL +Q 0 +S 9,EXTERNAL,vdd +Q 0.00768955 +S 8,EXTERNAL,nq +Q 0.00258522 +S 7,EXTERNAL,i0 +Q 0.00358899 +S 6,EXTERNAL,i1 +Q 0.00295012 +S 5,EXTERNAL,i2 +Q 0.00379567 +S 4,EXTERNAL,vss +Q 0.00616192 +S 3,INTERNAL +Q 0.0066832 +S 2,INTERNAL +Q 0.00580421 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/pdks/symbolic/sxlib/cells/nao22_x4.ap b/pdks/symbolic/sxlib/cells/nao22_x4.ap new file mode 100644 index 000000000..2d1683ce7 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao22_x4.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H nao22_x4,P, 8/ 6/2002,100 +A 0,0,5000,5000 +R 500,1000,ref_ref,i2_10 +R 500,1500,ref_ref,i2_15 +R 500,2500,ref_ref,i2_25 +R 500,3000,ref_ref,i2_30 +R 4000,3500,ref_ref,nq_35 +R 4000,3000,ref_ref,nq_30 +R 4000,2000,ref_ref,nq_20 +R 4000,1000,ref_ref,nq_10 +R 4000,1500,ref_ref,nq_15 +R 4000,2500,ref_ref,nq_25 +R 2000,2000,ref_ref,i0_20 +R 2000,2500,ref_ref,i0_25 +R 2000,3000,ref_ref,i0_30 +R 1500,3000,ref_ref,i1_30 +R 1500,2500,ref_ref,i1_25 +R 1500,2000,ref_ref,i1_20 +R 500,2000,ref_ref,i2_20 +R 2000,3500,ref_ref,i0_35 +R 1500,3500,ref_ref,i1_35 +R 500,3500,ref_ref,i2_35 +R 500,4000,ref_ref,i2_40 +R 4000,4000,ref_ref,nq_40 +R 2500,1500,ref_ref,i0_15 +S 2800,4300,2800,4800,300,*,DOWN,NTIE +S 2000,2000,2400,2000,200,*,RIGHT,ALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 2000,2000,2000,3500,100,*,DOWN,ALU1 +S 1000,1500,1600,1500,100,*,RIGHT,ALU1 +S 1500,2000,1500,3500,100,*,DOWN,ALU1 +S 1600,800,1600,1600,300,*,UP,NDIF +S 400,400,400,1200,300,*,UP,NDIF +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 2800,2000,3500,2000,100,*,RIGHT,ALU1 +S 3300,2500,3300,3500,100,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 1100,4000,2800,4000,100,*,LEFT,ALU1 +S 2800,3500,2800,4000,100,*,UP,ALU1 +S 2800,3500,3300,3500,100,*,LEFT,ALU1 +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 1000,1000,2200,1000,100,*,RIGHT,ALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 500,2000,700,2000,300,*,RIGHT,POLY +S 1300,2000,1500,2000,300,*,RIGHT,POLY +S 3500,2000,4300,2000,300,*,RIGHT,POLY +S 3100,2500,3300,2500,300,*,RIGHT,POLY +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 3100,1400,3100,2600,100,*,DOWN,POLY +S 700,1400,700,3100,100,*,DOWN,POLY +S 1300,1400,1300,3100,100,*,DOWN,POLY +S 1900,1400,1900,3100,100,*,DOWN,POLY +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 3400,300,3400,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 4600,300,4600,1200,300,*,UP,NDIF +S 3100,600,3100,1400,100,*,DOWN,NTRANS +S 2800,800,2800,1200,300,*,UP,NDIF +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 2200,800,2200,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 3100,2600,3100,3900,100,*,UP,PTRANS +S 2800,2800,2800,3700,300,*,DOWN,PDIF +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 400,3300,400,4600,300,*,DOWN,PDIF +S 1600,3300,1600,4200,300,*,DOWN,PDIF +S 2200,3300,2200,4600,300,*,DOWN,PDIF +S 700,3100,700,4400,100,*,UP,PTRANS +S 1900,3100,1900,4400,100,*,UP,PTRANS +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 2400,1500,2400,2000,100,*,DOWN,ALU1 +S 2400,1500,2500,1500,100,*,RIGHT,ALU1 +S 3500,1000,3500,2000,100,*,DOWN,ALU1 +S 2800,1000,3500,1000,100,*,LEFT,ALU1 +S 2800,2000,2800,3000,100,*,UP,ALU1 +S 500,1000,500,4000,200,i2,DOWN,CALU1 +S 4000,1000,4000,4000,200,nq,DOWN,CALU1 +S 1500,2000,1500,3500,200,i1,DOWN,CALU1 +S 2000,2000,2000,3500,200,i0,DOWN,CALU1 +S 2500,1500,2500,1500,200,i0,LEFT,CALU1 +S 900,4700,1700,4700,300,*,RIGHT,NTIE +S 900,300,2900,300,300,*,RIGHT,PTIE +V 1600,1500,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1600,300,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3500,2000,CONT_POLY,* +V 3300,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2200,300,CONT_BODY_P,* +V 1000,300,CONT_BODY_P,* +V 2800,300,CONT_BODY_P,* +V 2800,1000,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 4600,500,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 2200,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 3400,4000,CONT_DIF_P,* +V 1000,4700,CONT_BODY_N,* +V 2800,4700,CONT_BODY_N,* +V 2800,3000,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1600,4700,CONT_BODY_N,* +V 1000,3500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 2200,4500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nao22_x4.sym b/pdks/symbolic/sxlib/cells/nao22_x4.sym new file mode 100644 index 000000000..a7c777bd5 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/nao22_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/nao22_x4.vbe b/pdks/symbolic/sxlib/cells/nao22_x4.vbe new file mode 100644 index 000000000..ebdcfc515 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY nao22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 596; + CONSTANT tplh_i2_nq : NATURAL := 636; + CONSTANT tplh_i0_nq : NATURAL := 650; + CONSTANT tphl_i1_nq : NATURAL := 664; + CONSTANT tplh_i1_nq : NATURAL := 723; + CONSTANT tphl_i0_nq : NATURAL := 732; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao22_x4; + +ARCHITECTURE behaviour_data_flow OF nao22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/nao22_x4.vhd b/pdks/symbolic/sxlib/cells/nao22_x4.vhd new file mode 100644 index 000000000..e45a87a3d --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao22_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nao22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nao22_x4; + +ARCHITECTURE RTL OF nao22_x4 IS +BEGIN + nq <= NOT(((i0 OR i1) AND i2)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nao2o22_x1.al b/pdks/symbolic/sxlib/cells/nao2o22_x1.al new file mode 100644 index 000000000..ebf99d479 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao2o22_x1.al @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H nao2o22_x1,L,30/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,2,8,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00008 +T P,0.35,5.9,5,10,4,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00007 +T P,0.35,5.9,6,7,2,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,5.9,4,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005 +T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,2.9,1,7,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003 +T N,0.35,2.9,2,8,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 10,EXTERNAL,i0 +Q 0.00260759 +S 9,EXTERNAL,i2 +Q 0.00288944 +S 8,EXTERNAL,i1 +Q 0.00288494 +S 7,EXTERNAL,i3 +Q 0.00316679 +S 6,INTERNAL +Q 0 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00490248 +S 3,EXTERNAL,vss +Q 0.00449119 +S 2,EXTERNAL,nq +Q 0.00282024 +S 1,INTERNAL +Q 0.00199441 +EOF diff --git a/pdks/symbolic/sxlib/cells/nao2o22_x1.ap b/pdks/symbolic/sxlib/cells/nao2o22_x1.ap new file mode 100644 index 000000000..ac8c342bd --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao2o22_x1.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H nao2o22_x1,P,10/ 6/2002,100 +A 0,0,3500,5000 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2500,3500,ref_ref,i2_35 +R 2000,3500,ref_ref,i3_35 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,2000,ref_ref,i3_20 +R 2000,1500,ref_ref,i3_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,4000,ref_ref,i0_40 +R 500,3500,ref_ref,i0_35 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 1500,4000,ref_ref,nq_40 +R 2000,4000,ref_ref,i3_40 +R 2500,4000,ref_ref,i2_40 +S 3200,2800,3200,3300,300,*,DOWN,NTIE +S 2600,2800,2600,3700,300,*,UP,PDIF +S 2700,3700,2700,4700,300,*,DOWN,PDIF +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 1500,1500,1500,4000,200,nq,DOWN,CALU1 +S 2000,1500,2000,4000,200,i3,DOWN,CALU1 +S 2500,1500,2500,4000,200,i2,DOWN,CALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 3200,2900,3200,4500,200,*,DOWN,ALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,1400,600,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 900,300,900,1600,300,*,UP,NDIF +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 300,1000,2700,1000,100,*,RIGHT,ALU1 +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 2500,1500,2500,4000,100,*,DOWN,ALU1 +S 1500,1450,1500,4000,200,*,UP,ALU1 +S 900,1500,1550,1500,200,*,RIGHT,ALU1 +V 3200,2900,CONT_BODY_N,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 2700,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nao2o22_x1.sym b/pdks/symbolic/sxlib/cells/nao2o22_x1.sym new file mode 100644 index 000000000..7030a68e6 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/nao2o22_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/nao2o22_x1.vbe b/pdks/symbolic/sxlib/cells/nao2o22_x1.vbe new file mode 100644 index 000000000..327e99763 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao2o22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i3_nq : NATURAL := 174; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 226; + CONSTANT tphl_i2_nq : NATURAL := 237; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT tplh_i2_nq : NATURAL := 307; + CONSTANT tplh_i3_nq : NATURAL := 382; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x1; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/nao2o22_x1.vhd b/pdks/symbolic/sxlib/cells/nao2o22_x1.vhd new file mode 100644 index 000000000..9ddd0b031 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao2o22_x1.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nao2o22_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nao2o22_x1; + +ARCHITECTURE RTL OF nao2o22_x1 IS +BEGIN + nq <= NOT(((i0 OR i1) AND (i2 OR i3))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nao2o22_x4.al b/pdks/symbolic/sxlib/cells/nao2o22_x4.al new file mode 100644 index 000000000..ff51e2b93 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao2o22_x4.al @@ -0,0 +1,48 @@ +V ALLIANCE : 6 +H nao2o22_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,4 +C i2,IN,EXTERNAL,7 +C i3,IN,EXTERNAL,5 +C nq,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,10,3,9,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00014 +T P,0.35,5.9,10,9,8,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00013 +T P,0.35,5.9,8,9,10,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00012 +T P,0.35,2.9,11,6,10,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00011 +T P,0.35,2.9,12,5,3,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010 +T P,0.35,2.9,10,7,12,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00009 +T P,0.35,2.9,3,4,11,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T N,0.35,1.4,9,3,1,0,0.75,0.75,4.3,4.3,10.8,3,tr_00007 +T N,0.35,2.9,8,9,1,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00006 +T N,0.35,2.9,1,9,8,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005 +T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00003 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,1.8,3,tr_00002 +T N,0.35,1.4,3,4,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,vdd +Q 0.00820729 +S 9,INTERNAL +Q 0.00518414 +S 8,EXTERNAL,nq +Q 0.00258522 +S 7,EXTERNAL,i2 +Q 0.00295462 +S 6,EXTERNAL,i0 +Q 0.00295462 +S 5,EXTERNAL,i3 +Q 0.00323197 +S 4,EXTERNAL,i1 +Q 0.00323197 +S 3,INTERNAL +Q 0.0066832 +S 2,INTERNAL +Q 0.00199441 +S 1,EXTERNAL,vss +Q 0.00726721 +EOF diff --git a/pdks/symbolic/sxlib/cells/nao2o22_x4.ap b/pdks/symbolic/sxlib/cells/nao2o22_x4.ap new file mode 100644 index 000000000..056f13cce --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao2o22_x4.ap @@ -0,0 +1,144 @@ +V ALLIANCE : 6 +H nao2o22_x4,P, 8/ 6/2002,100 +A 0,0,5500,5000 +R 4500,2500,ref_ref,nq_25 +R 4500,1500,ref_ref,nq_15 +R 4500,1000,ref_ref,nq_10 +R 4500,2000,ref_ref,nq_20 +R 4500,3000,ref_ref,nq_30 +R 4500,3500,ref_ref,nq_35 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 2000,1500,ref_ref,i3_15 +R 2000,2000,ref_ref,i3_20 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 4500,4000,ref_ref,nq_40 +R 500,3500,ref_ref,i0_35 +R 500,4000,ref_ref,i0_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 2000,3500,ref_ref,i3_35 +R 2500,3500,ref_ref,i2_35 +S 3300,4300,3300,4800,300,*,DOWN,NTIE +S 4500,1000,4500,4000,200,nq,DOWN,CALU1 +S 500,2000,500,4000,200,i0,DOWN,CALU1 +S 1000,2000,1000,4000,200,i1,DOWN,CALU1 +S 2000,1500,2000,3500,200,i3,DOWN,CALU1 +S 2500,1500,2500,3500,200,i2,DOWN,CALU1 +S 4500,1000,4500,4000,200,*,UP,ALU1 +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 3300,1000,3300,3000,100,*,DOWN,ALU1 +S 3300,800,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,3700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 5100,300,5100,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 3900,300,3900,1200,300,*,UP,NDIF +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 3800,2500,3800,3500,100,*,DOWN,ALU1 +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 3300,2000,4000,2000,100,*,RIGHT,ALU1 +S 3600,2500,3800,2500,300,*,RIGHT,POLY +S 3900,4000,3900,4500,200,*,DOWN,ALU1 +S 5100,3000,5100,4500,200,*,DOWN,ALU1 +S 5100,500,5100,1000,200,*,DOWN,ALU1 +S 3900,500,3900,1000,200,*,DOWN,ALU1 +S 4000,2000,4800,2000,300,*,RIGHT,POLY +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 2700,800,2700,1200,300,*,UP,NDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 300,1000,2700,1000,100,*,RIGHT,ALU1 +S 900,800,900,1600,300,*,UP,NDIF +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 900,1500,1500,1500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 3300,3500,3800,3500,100,*,LEFT,ALU1 +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 1600,4000,3300,4000,100,*,LEFT,ALU1 +S 300,800,300,1200,300,*,UP,NDIF +S 900,4700,2100,4700,300,*,RIGHT,NTIE +S 300,300,1500,300,300,*,RIGHT,PTIE +S 2700,300,3300,300,300,*,RIGHT,PTIE +V 4500,1000,CONT_DIF_N,* +V 3300,300,CONT_BODY_P,* +V 5100,500,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3800,2500,CONT_POLY,* +V 3900,4000,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 3300,3000,CONT_DIF_P,* +V 3300,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 4000,2000,CONT_POLY,* +V 3300,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 1500,4700,CONT_BODY_N,* +V 2700,4500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +V 2100,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 2700,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 4500,3000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nao2o22_x4.sym b/pdks/symbolic/sxlib/cells/nao2o22_x4.sym new file mode 100644 index 000000000..886aab256 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/nao2o22_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/nao2o22_x4.vbe b/pdks/symbolic/sxlib/cells/nao2o22_x4.vbe new file mode 100644 index 000000000..b5c506fee --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao2o22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY nao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i3_nq : NATURAL := 607; + CONSTANT tplh_i0_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 664; + CONSTANT tphl_i1_nq : NATURAL := 666; + CONSTANT tplh_i1_nq : NATURAL := 717; + CONSTANT tplh_i2_nq : NATURAL := 721; + CONSTANT tphl_i0_nq : NATURAL := 734; + CONSTANT tplh_i3_nq : NATURAL := 807; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x4; + +ARCHITECTURE behaviour_data_flow OF nao2o22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nao2o22_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) and (i2 or i3))) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/nao2o22_x4.vhd b/pdks/symbolic/sxlib/cells/nao2o22_x4.vhd new file mode 100644 index 000000000..4bc6cef65 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nao2o22_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nao2o22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nao2o22_x4; + +ARCHITECTURE RTL OF nao2o22_x4 IS +BEGIN + nq <= NOT(((i0 OR i1) AND (i2 OR i3))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nmx2_x1.al b/pdks/symbolic/sxlib/cells/nmx2_x1.al new file mode 100644 index 000000000..92138ed13 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx2_x1.al @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H nmx2_x1,L,30/10/99 +C cmd,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,11 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,3,5,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00010 +T P,0.35,5.9,8,9,3,0,0.75,0.75,13.3,13.3,5.1,11.25,tr_00009 +T P,0.35,5.9,6,11,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00008 +T P,0.35,5.9,7,10,8,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00007 +T P,0.35,2.9,5,9,7,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00006 +T N,0.35,2.9,2,9,3,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00005 +T N,0.35,2.9,3,5,4,0,0.75,0.75,7.3,7.3,5.1,2.25,tr_00004 +T N,0.35,2.9,1,11,2,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00003 +T N,0.35,2.9,4,10,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,1.4,1,9,5,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 11,EXTERNAL,i1 +Q 0.00271107 +S 10,EXTERNAL,i0 +Q 0.00265635 +S 9,EXTERNAL,cmd +Q 0.00492843 +S 8,INTERNAL +Q 0 +S 7,EXTERNAL,vdd +Q 0.00384489 +S 6,INTERNAL +Q 0 +S 5,INTERNAL +Q 0.00698278 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,nq +Q 0.00270273 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00384489 +EOF diff --git a/pdks/symbolic/sxlib/cells/nmx2_x1.ap b/pdks/symbolic/sxlib/cells/nmx2_x1.ap new file mode 100644 index 000000000..0d120bf58 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx2_x1.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H nmx2_x1,P,18/ 5/2002,100 +A 0,0,3500,5000 +R 2000,1000,ref_ref,nq_10 +R 2000,2000,ref_ref,nq_20 +R 2500,1500,ref_ref,nq_15 +R 2000,2500,ref_ref,nq_25 +R 2000,3000,ref_ref,nq_30 +R 2000,3500,ref_ref,nq_35 +R 3000,4000,ref_ref,i1_40 +R 3000,3500,ref_ref,i1_35 +R 3000,3000,ref_ref,i1_30 +R 3000,2500,ref_ref,i1_25 +R 3000,2000,ref_ref,i1_20 +R 3000,1500,ref_ref,i1_15 +R 3000,1000,ref_ref,i1_10 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1500,3500,ref_ref,cmd_35 +R 1500,3000,ref_ref,cmd_30 +R 1500,2500,ref_ref,cmd_25 +R 1500,2000,ref_ref,cmd_20 +S 2500,1500,2500,1500,200,nq,LEFT,CALU1 +S 2000,1000,2000,1000,200,nq,LEFT,CALU1 +S 2000,2000,2000,3500,200,nq,DOWN,CALU1 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 1000,1500,1000,3500,200,i0,DOWN,CALU1 +S 1500,2000,1500,3500,200,cmd,DOWN,CALU1 +S 2000,1950,2000,3500,200,*,DOWN,ALU1 +S 2600,300,2600,1200,200,*,DOWN,NDIF +S 2600,2800,2600,4700,200,*,UP,PDIF +S 2300,2600,2500,2600,100,*,RIGHT,POLY +S 2300,2600,2300,4900,100,*,DOWN,PTRANS +S 600,2000,2300,2000,100,*,RIGHT,POLY +S 2300,1400,2300,2000,100,*,DOWN,POLY +S 2300,100,2300,1400,100,*,UP,NTRANS +S 1700,100,1700,1400,100,*,UP,NTRANS +S 1700,2000,1700,2600,100,*,UP,POLY +S 1700,2600,1700,4900,100,*,DOWN,PTRANS +S 300,1000,1550,1000,100,*,RIGHT,ALU1 +S 1550,1000,1550,1500,100,*,UP,ALU1 +S 2000,300,2000,1200,500,*,DOWN,NDIF +S 2500,2500,2500,4000,100,*,DOWN,ALU1 +S 300,4000,2500,4000,100,*,RIGHT,ALU1 +S 3200,300,3200,1200,300,*,UP,NDIF +S 2900,100,2900,1400,100,*,UP,NTRANS +S 2900,2600,2900,4900,100,*,DOWN,PTRANS +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 1000,1500,1000,3500,100,*,DOWN,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 2000,2800,2000,4700,500,*,DOWN,PDIF +S 900,2600,1200,2600,100,*,RIGHT,POLY +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 300,800,300,1200,300,*,UP,NDIF +S 600,1400,600,3100,100,*,DOWN,POLY +S 600,600,600,1400,100,*,UP,NTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 2050,1500,2500,1500,200,*,LEFT,ALU1 +S 2100,950,2100,2050,200,*,UP,ALU1 +V 2000,1000,CONT_DIF_N,* +V 3200,500,CONT_DIF_N,* +V 2500,2500,CONT_POLY,* +V 3200,4500,CONT_DIF_P,* +V 2000,3000,CONT_DIF_P,* +V 3000,2500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 900,500,CONT_DIF_N,* +V 1600,1500,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 300,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 2000,3500,CONT_DIF_P,* +V 1500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nmx2_x1.sym b/pdks/symbolic/sxlib/cells/nmx2_x1.sym new file mode 100644 index 000000000..b7abb9199 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/nmx2_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/nmx2_x1.vbe b/pdks/symbolic/sxlib/cells/nmx2_x1.vbe new file mode 100644 index 000000000..3f0ab6425 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx2_x1.vbe @@ -0,0 +1,40 @@ +ENTITY nmx2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_cmd : NATURAL := 21; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 217; + CONSTANT tphl_i1_nq : NATURAL := 217; + CONSTANT tphl_cmd_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 256; + CONSTANT tplh_i1_nq : NATURAL := 256; + CONSTANT tplh_cmd_nq : NATURAL := 287; + CONSTANT tphh_cmd_nq : NATURAL := 379; + CONSTANT tpll_cmd_nq : NATURAL := 410; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x1; + +ARCHITECTURE behaviour_data_flow OF nmx2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x1" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/nmx2_x1.vhd b/pdks/symbolic/sxlib/cells/nmx2_x1.vhd new file mode 100644 index 000000000..463098937 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx2_x1.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nmx2_x1 IS +PORT( + cmd : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nmx2_x1; + +ARCHITECTURE RTL OF nmx2_x1 IS +BEGIN + nq <= NOT(((i0 AND NOT(cmd)) OR (i1 AND cmd))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nmx2_x4.al b/pdks/symbolic/sxlib/cells/nmx2_x4.al new file mode 100644 index 000000000..1af7115fe --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx2_x4.al @@ -0,0 +1,51 @@ +V ALLIANCE : 6 +H nmx2_x4,L,30/10/99 +C cmd,IN,EXTERNAL,7 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,6 +C nq,OUT,EXTERNAL,10 +C vdd,IN,EXTERNAL,11 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,11,8,12,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00016 +T P,0.35,2.9,3,4,13,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00015 +T P,0.35,2.9,12,7,3,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00014 +T P,0.35,2.9,4,7,11,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00013 +T P,0.35,2.9,13,6,11,0,0.75,0.75,7.3,7.3,8.4,11.25,tr_00012 +T P,0.35,2.9,11,3,9,0,0.75,0.75,7.3,7.3,10.2,11.25,tr_00011 +T P,0.35,5.9,11,9,10,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00010 +T P,0.35,5.9,10,9,11,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00009 +T N,0.35,1.4,5,8,1,0,0.75,0.75,4.3,4.3,3.6,1.5,tr_00008 +T N,0.35,1.4,3,4,5,0,0.75,0.75,4.3,4.3,4.8,1.5,tr_00007 +T N,0.35,1.4,1,7,4,0,0.75,0.75,4.3,4.3,1.8,1.5,tr_00006 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,7.2,1.5,tr_00005 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,8.4,1.5,tr_00004 +T N,0.35,1.4,9,3,1,0,0.75,0.75,4.3,4.3,10.2,1.5,tr_00003 +T N,0.35,2.9,10,9,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00002 +T N,0.35,2.9,1,9,10,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00001 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0 +S 11,EXTERNAL,vdd +Q 0.00966511 +S 10,EXTERNAL,nq +Q 0.00258522 +S 9,INTERNAL +Q 0.00573596 +S 8,EXTERNAL,i0 +Q 0.00336619 +S 7,EXTERNAL,cmd +Q 0.00660261 +S 6,EXTERNAL,i1 +Q 0.00371745 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00595297 +S 3,INTERNAL +Q 0.00516493 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00807873 +EOF diff --git a/pdks/symbolic/sxlib/cells/nmx2_x4.ap b/pdks/symbolic/sxlib/cells/nmx2_x4.ap new file mode 100644 index 000000000..8c79f782e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx2_x4.ap @@ -0,0 +1,143 @@ +V ALLIANCE : 6 +H nmx2_x4,P,18/ 5/2002,100 +A 0,0,6000,5000 +R 3000,4000,ref_ref,i1_40 +R 3000,3500,ref_ref,i1_35 +R 3000,3000,ref_ref,i1_30 +R 3000,2500,ref_ref,i1_25 +R 3000,2000,ref_ref,i1_20 +R 3000,1500,ref_ref,i1_15 +R 3000,1000,ref_ref,i1_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 1500,4000,ref_ref,cmd_40 +R 1500,3500,ref_ref,cmd_35 +R 1500,3000,ref_ref,cmd_30 +R 1500,2500,ref_ref,cmd_25 +R 1500,2000,ref_ref,cmd_20 +R 1500,1500,ref_ref,cmd_15 +R 5000,4000,ref_ref,nq_40 +R 5000,3500,ref_ref,nq_35 +R 5000,2500,ref_ref,nq_25 +R 5000,1000,ref_ref,nq_10 +R 5000,3000,ref_ref,nq_30 +R 5000,2000,ref_ref,nq_20 +R 5000,1500,ref_ref,nq_15 +S 4400,500,4400,1000,200,*,DOWN,ALU1 +S 5600,500,5600,1000,200,*,DOWN,ALU1 +S 3000,1000,3000,4000,200,i1,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 1500,1500,1500,4000,200,cmd,DOWN,CALU1 +S 5000,1000,5000,4000,200,nq,DOWN,CALU1 +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 1600,2000,1600,3100,100,*,UP,POLY +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 2500,1000,2500,2700,100,*,UP,ALU1 +S 2400,2800,2400,3100,100,*,UP,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 1200,100,1200,900,100,*,UP,NTRANS +S 1600,100,1600,900,100,*,UP,NTRANS +S 600,100,600,900,100,*,UP,NTRANS +S 900,300,900,700,300,*,UP,NDIF +S 600,900,600,3100,100,*,DOWN,POLY +S 2400,100,2400,900,100,*,UP,NTRANS +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 3400,100,3400,900,100,*,UP,NTRANS +S 3100,300,3100,700,300,*,DOWN,NDIF +S 3700,300,3700,1100,300,*,DOWN,NDIF +S 300,300,300,1100,300,*,UP,NDIF +S 3400,3100,3400,4400,100,*,DOWN,PTRANS +S 3700,3300,3700,4200,300,*,DOWN,PDIF +S 3100,3300,3100,4600,300,*,DOWN,PDIF +S 3700,1000,3700,4000,100,*,DOWN,ALU1 +S 3400,900,3400,3100,100,*,DOWN,POLY +S 2000,2300,3400,2300,100,*,RIGHT,POLY +S 5600,3000,5600,4500,200,*,UP,ALU1 +S 4400,3000,4400,4500,200,*,UP,ALU1 +S 5600,2900,5600,3300,300,*,DOWN,PDIF +S 4700,100,4700,1400,100,*,UP,NTRANS +S 5000,300,5000,1200,300,*,DOWN,NDIF +S 5300,100,5300,1400,100,*,UP,NTRANS +S 5600,300,5600,1200,300,*,DOWN,NDIF +S 4400,300,4400,1200,300,*,DOWN,NDIF +S 3800,2500,5300,2500,100,*,LEFT,POLY +S 4700,1400,4700,2600,100,*,DOWN,POLY +S 4700,2600,4700,4900,100,*,DOWN,PTRANS +S 5300,1400,5300,2600,100,*,DOWN,POLY +S 5300,2600,5300,4900,100,*,DOWN,PTRANS +S 4400,2800,4400,4700,300,*,UP,PDIF +S 5600,2800,5600,4700,300,*,UP,PDIF +S 5000,2800,5000,4700,300,*,UP,PDIF +V 3000,1500,CONT_POLY,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1000,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1000,3000,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 2000,1500,CONT_DIF_N,* +V 2000,3500,CONT_DIF_P,* +V 2000,4700,CONT_BODY_N,* +V 2000,4000,CONT_DIF_P,* +V 2500,2700,CONT_POLY,* +V 2000,2400,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1600,1000,CONT_POLY,* +V 1500,4700,CONT_BODY_N,* +V 2500,4700,CONT_BODY_N,* +V 3100,500,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 3100,4500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,3400,CONT_DIF_P,* +V 3800,2500,CONT_POLY,* +V 4400,3000,CONT_DIF_P,* +V 4400,4500,CONT_DIF_P,* +V 5600,3000,CONT_DIF_P,* +V 5600,4500,CONT_DIF_P,* +V 5600,4000,CONT_DIF_P,* +V 5000,3000,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 5000,3500,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 4400,3500,CONT_DIF_P,* +V 5600,3500,CONT_DIF_P,* +V 4400,1000,CONT_DIF_N,* +V 4400,500,CONT_DIF_N,* +V 5600,500,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +V 5000,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nmx2_x4.sym b/pdks/symbolic/sxlib/cells/nmx2_x4.sym new file mode 100644 index 000000000..2f3c726de Binary files /dev/null and b/pdks/symbolic/sxlib/cells/nmx2_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/nmx2_x4.vbe b/pdks/symbolic/sxlib/cells/nmx2_x4.vbe new file mode 100644 index 000000000..436a6b355 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx2_x4.vbe @@ -0,0 +1,40 @@ +ENTITY nmx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_cmd_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_cmd_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 610; + CONSTANT tphl_cmd_nq : NATURAL := 632; + CONSTANT tplh_i0_nq : NATURAL := 653; + CONSTANT tplh_i1_nq : NATURAL := 653; + CONSTANT tphh_cmd_nq : NATURAL := 688; + CONSTANT tpll_cmd_nq : NATURAL := 703; + CONSTANT tplh_cmd_nq : NATURAL := 708; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x4; + +ARCHITECTURE behaviour_data_flow OF nmx2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx2_x4" + SEVERITY WARNING; + nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/nmx2_x4.vhd b/pdks/symbolic/sxlib/cells/nmx2_x4.vhd new file mode 100644 index 000000000..d8d2a999e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx2_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nmx2_x4 IS +PORT( + cmd : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nmx2_x4; + +ARCHITECTURE RTL OF nmx2_x4 IS +BEGIN + nq <= NOT(((i0 AND NOT(cmd)) OR (i1 AND cmd))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nmx3_x1.al b/pdks/symbolic/sxlib/cells/nmx3_x1.al new file mode 100644 index 000000000..d88bd5589 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx3_x1.al @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H nmx3_x1,L,30/10/99 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,15,6,1,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00018 +T P,0.35,2.9,7,12,17,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00017 +T P,0.35,2.9,18,14,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00016 +T P,0.35,2.9,1,13,18,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00015 +T P,0.35,2.9,17,8,15,0,0.75,0.75,7.3,7.3,9,12.75,tr_00014 +T P,0.35,2.9,16,10,17,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00013 +T P,0.35,2.9,1,9,16,0,0.75,0.75,7.3,7.3,6,12.75,tr_00012 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00011 +T P,0.35,2,7,14,12,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00010 +T N,0.35,1.7,4,8,2,0,0.75,0.75,4.9,4.9,9,2.55,tr_00009 +T N,0.35,1.7,2,9,1,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00008 +T N,0.35,1.7,1,6,5,0,0.75,0.75,4.9,4.9,6,2.55,tr_00007 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00006 +T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00005 +T N,0.35,1.7,11,12,3,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00004 +T N,0.35,1.7,1,13,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00003 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00002 +T N,0.35,1.1,12,14,3,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00001 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00170541 +S 16,INTERNAL +Q 0 +S 15,INTERNAL +Q 0 +S 14,EXTERNAL,cmd0 +Q 0.00553121 +S 13,EXTERNAL,i0 +Q 0.00386192 +S 12,INTERNAL +Q 0.0057783 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00690363 +S 6,INTERNAL +Q 0.00547335 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00619857 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,nq +Q 0.00696213 +EOF diff --git a/pdks/symbolic/sxlib/cells/nmx3_x1.ap b/pdks/symbolic/sxlib/cells/nmx3_x1.ap new file mode 100644 index 000000000..b7f864420 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx3_x1.ap @@ -0,0 +1,156 @@ +V ALLIANCE : 6 +H nmx3_x1,P,12/ 6/2002,100 +A 0,0,6000,5000 +R 5500,1000,ref_ref,nq_10 +R 5500,3000,ref_ref,nq_30 +R 5500,2500,ref_ref,nq_25 +R 5500,2000,ref_ref,nq_20 +R 5500,1500,ref_ref,nq_15 +R 5500,3500,ref_ref,nq_35 +R 500,1500,ref_ref,cmd1_15 +R 500,2000,ref_ref,cmd1_20 +R 500,2500,ref_ref,cmd1_25 +R 500,3000,ref_ref,cmd1_30 +R 500,3500,ref_ref,cmd1_35 +R 1500,2500,ref_ref,i2_25 +R 2500,2500,ref_ref,i1_25 +R 3500,2000,ref_ref,cmd0_20 +R 3500,2500,ref_ref,cmd0_25 +R 3500,3000,ref_ref,cmd0_30 +R 4000,2000,ref_ref,i0_20 +R 4000,3000,ref_ref,i0_30 +R 4500,2500,ref_ref,i0_25 +S 4900,1000,5500,1000,200,*,RIGHT,ALU1 +S 3000,2000,3000,3500,200,*,UP,ALU1 +S 2300,2000,3000,2000,200,*,RIGHT,ALU1 +S 2300,1500,2300,2000,200,*,UP,ALU1 +S 500,3500,1800,3500,200,*,LEFT,ALU1 +S 1000,3000,2500,3000,200,*,LEFT,ALU1 +S 1000,1500,1800,1500,200,*,RIGHT,ALU1 +S 1000,1500,1000,3000,200,*,UP,ALU1 +S 4900,1500,4900,1800,300,*,DOWN,NDIF +S 3400,1500,5000,1500,200,*,RIGHT,ALU1 +S 5000,1500,5000,3000,200,*,DOWN,ALU1 +S 4400,2000,4400,3000,200,*,UP,ALU1 +S 4900,3500,4900,4000,200,*,DOWN,ALU1 +S 2300,3500,5500,3500,200,*,RIGHT,ALU1 +S 1100,4000,3300,4000,200,*,RIGHT,ALU1 +S 2000,2500,2500,2500,200,*,RIGHT,ALU1 +S 1500,2100,1500,2500,200,*,DOWN,ALU1 +S 1100,1000,3300,1000,200,*,RIGHT,ALU1 +S 800,2000,800,2600,100,*,DOWN,POLY +S 500,1000,500,1800,300,*,DOWN,NDIF +S 800,1300,800,2000,100,*,DOWN,NTRANS +S 1100,1500,1100,1800,300,*,UP,NDIF +S 1800,1500,2000,1500,300,*,RIGHT,POLY +S 4400,2000,4600,2000,300,*,RIGHT,POLY +S 4400,3000,4600,3000,300,*,RIGHT,POLY +S 1800,3500,2000,3500,300,*,RIGHT,POLY +S 4000,2000,4000,2000,200,i0,LEFT,CALU1 +S 4500,2500,4500,2500,200,i0,LEFT,CALU1 +S 4000,3000,4000,3000,200,i0,LEFT,CALU1 +S 5500,1000,5500,3500,200,nq,DOWN,CALU1 +S 500,1500,500,3500,200,cmd1,DOWN,CALU1 +S 1500,2500,1500,2500,200,i2,LEFT,CALU1 +S 2500,2500,2500,2500,200,i1,LEFT,CALU1 +S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1 +S 5500,4000,5500,4700,200,*,UP,ALU1 +S 5500,2800,5500,4000,300,*,DOWN,PDIF +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 5500,500,5500,1800,300,*,DOWN,NDIF +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 500,400,500,1000,200,*,DOWN,ALU1 +S 2600,3000,2600,3600,100,*,UP,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 500,2500,800,2500,300,*,RIGHT,POLY +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 3900,3800,3900,4700,200,*,UP,PDIF +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 4900,3800,4900,4700,300,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 3300,3800,3300,4700,200,*,UP,PDIF +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 1100,3800,1100,4700,300,*,UP,PDIF +S 1400,3600,1400,4900,100,*,UP,PTRANS +S 1700,3800,1700,4700,200,*,DOWN,PDIF +S 2300,3500,2300,4700,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 500,2800,500,4000,300,*,UP,PDIF +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 4000,3300,4000,3600,100,*,UP,POLY +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 4900,2800,4900,3400,300,*,UP,PDIF +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 4200,1100,4200,1500,100,*,UP,POLY +S 3900,400,3900,900,200,*,DOWN,NDIF +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 800,2600,800,3600,100,*,UP,PTRANS +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 3000,400,3000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 1400,400,1400,1300,100,*,UP,NTRANS +S 3600,200,3600,1100,100,*,UP,NTRANS +S 4200,200,4200,1100,100,*,UP,NTRANS +S 4600,200,4600,1100,100,*,UP,NTRANS +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 3500,1500,3500,3600,100,*,UP,POLY +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 5200,1300,5200,2000,100,*,DOWN,NTRANS +S 5200,2000,5200,2600,100,*,DOWN,POLY +S 4900,400,4900,1000,300,*,UP,NDIF +V 4900,1600,CONT_DIF_N,* +V 1100,1600,CONT_DIF_N,* +V 5500,4000,CONT_DIF_P,* +V 1800,3500,CONT_POLY,* +V 4200,1500,CONT_POLY,* +V 3400,1500,CONT_POLY,* +V 1800,1500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2300,1500,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 4900,1000,CONT_DIF_N,* +V 1100,1000,CONT_DIF_N,* +V 500,1000,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 3300,4000,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 2300,3500,CONT_DIF_P,* +V 1100,4000,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 1100,3000,CONT_DIF_P,* +V 4900,3000,CONT_DIF_P,* +V 2500,3000,CONT_POLY,* +V 4400,3000,CONT_POLY,* +V 4400,2000,CONT_POLY,* +V 5500,500,CONT_DIF_N,* +V 3900,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nmx3_x1.vbe b/pdks/symbolic/sxlib/cells/nmx3_x1.vbe new file mode 100644 index 000000000..1853919ce --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx3_x1.vbe @@ -0,0 +1,55 @@ +ENTITY nmx3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 7420; + CONSTANT rdown_cmd1_nq : NATURAL := 7420; + CONSTANT rdown_i0_nq : NATURAL := 5140; + CONSTANT rdown_i1_nq : NATURAL := 7420; + CONSTANT rdown_i2_nq : NATURAL := 7420; + CONSTANT rup_cmd0_nq : NATURAL := 9760; + CONSTANT rup_cmd1_nq : NATURAL := 9760; + CONSTANT rup_i0_nq : NATURAL := 6680; + CONSTANT rup_i1_nq : NATURAL := 9760; + CONSTANT rup_i2_nq : NATURAL := 9760; + CONSTANT tphl_i0_nq : NATURAL := 315; + CONSTANT tphl_cmd0_nq : NATURAL := 356; + CONSTANT tphl_cmd1_nq : NATURAL := 414; + CONSTANT tphl_i1_nq : NATURAL := 429; + CONSTANT tphl_i2_nq : NATURAL := 429; + CONSTANT tplh_i0_nq : NATURAL := 441; + CONSTANT tplh_cmd0_nq : NATURAL := 495; + CONSTANT tphh_cmd1_nq : NATURAL := 519; + CONSTANT tpll_cmd1_nq : NATURAL := 520; + CONSTANT tplh_cmd1_nq : NATURAL := 566; + CONSTANT tphh_cmd0_nq : NATURAL := 582; + CONSTANT tplh_i1_nq : NATURAL := 582; + CONSTANT tplh_i2_nq : NATURAL := 582; + CONSTANT tpll_cmd0_nq : NATURAL := 586; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x1; + +ARCHITECTURE behaviour_data_flow OF nmx3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx3_x1" + SEVERITY WARNING; + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not + (cmd1) and i2))))) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/nmx3_x1.vhd b/pdks/symbolic/sxlib/cells/nmx3_x1.vhd new file mode 100644 index 000000000..7fe6277fe --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx3_x1.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nmx3_x1 IS +PORT( + cmd0 : IN STD_LOGIC; + cmd1 : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nmx3_x1; + +ARCHITECTURE RTL OF nmx3_x1 IS +BEGIN + nq <= NOT(((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2))))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nmx3_x4.al b/pdks/symbolic/sxlib/cells/nmx3_x4.al new file mode 100644 index 000000000..eec6d89ff --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx3_x4.al @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H nmx3_x4,L,30/10/99 +C cmd0,IN,EXTERNAL,15 +C cmd1,IN,EXTERNAL,8 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,2,7,15,11,0,0.75,0.75,5.5,5.5,15.3,9.3,tr_00024 +T P,0.35,2,2,8,7,0,0.75,0.75,5.5,5.5,2.1,9.3,tr_00023 +T P,0.35,5.9,12,16,7,0,0.75,0.75,13.3,13.3,17.1,11.25,tr_00022 +T P,0.35,2.9,3,8,18,0,0.75,0.75,7.3,7.3,5.7,12.75,tr_00021 +T P,0.35,2.9,18,10,17,0,0.75,0.75,7.3,7.3,3.9,12.75,tr_00020 +T P,0.35,2.9,17,9,19,0,0.75,0.75,7.3,7.3,8.7,12.75,tr_00019 +T P,0.35,2.9,3,14,20,0,0.75,0.75,7.3,7.3,13.5,12.75,tr_00018 +T P,0.35,2.9,20,15,7,0,0.75,0.75,7.3,7.3,12.3,12.75,tr_00017 +T P,0.35,2.9,7,11,17,0,0.75,0.75,7.3,7.3,10.5,12.75,tr_00016 +T P,0.35,2.9,19,2,3,0,0.75,0.75,7.3,7.3,7.5,12.75,tr_00015 +T P,0.35,5.9,7,16,12,0,0.75,0.75,13.3,13.3,18.9,11.25,tr_00014 +T P,0.35,2.9,16,3,7,0,0.75,0.75,7.3,7.3,20.7,9.75,tr_00013 +T N,0.35,1.1,1,8,2,0,0.75,0.75,3.7,3.7,2.1,5.25,tr_00012 +T N,0.35,1.1,11,15,1,0,0.75,0.75,3.7,3.7,15.3,4.95,tr_00011 +T N,0.35,1.7,1,15,6,0,0.75,0.75,4.9,4.9,10.5,1.95,tr_00010 +T N,0.35,1.7,4,10,6,0,0.75,0.75,4.9,4.9,3.9,2.55,tr_00009 +T N,0.35,1.7,6,9,5,0,0.75,0.75,4.9,4.9,8.7,2.55,tr_00008 +T N,0.35,1.7,3,14,13,0,0.75,0.75,4.9,4.9,13.5,1.95,tr_00007 +T N,0.35,1.7,13,11,1,0,0.75,0.75,4.9,4.9,12.3,1.95,tr_00006 +T N,0.35,1.7,3,2,4,0,0.75,0.75,4.9,4.9,5.7,2.55,tr_00005 +T N,0.35,1.7,5,8,3,0,0.75,0.75,4.9,4.9,7.5,2.55,tr_00004 +T N,0.35,2.9,12,16,1,0,0.75,0.75,7.3,7.3,18.9,2.55,tr_00003 +T N,0.35,1.4,1,3,16,0,0.75,0.75,4.3,4.3,20.7,3.3,tr_00002 +T N,0.35,2.9,1,16,12,0,0.75,0.75,7.3,7.3,17.1,2.55,tr_00001 +S 20,INTERNAL +Q 0 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00170541 +S 16,INTERNAL +Q 0.00532834 +S 15,EXTERNAL,cmd0 +Q 0.00547246 +S 14,EXTERNAL,i0 +Q 0.00397942 +S 13,INTERNAL +Q 0 +S 12,EXTERNAL,nq +Q 0.00232082 +S 11,INTERNAL +Q 0.00589104 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,i1 +Q 0.0025589 +S 8,EXTERNAL,cmd1 +Q 0.00604152 +S 7,EXTERNAL,vdd +Q 0.00916191 +S 6,INTERNAL +Q 0.00170541 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.0105263 +S 2,INTERNAL +Q 0.00586794 +S 1,EXTERNAL,vss +Q 0.00757552 +EOF diff --git a/pdks/symbolic/sxlib/cells/nmx3_x4.ap b/pdks/symbolic/sxlib/cells/nmx3_x4.ap new file mode 100644 index 000000000..69b1136dc --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx3_x4.ap @@ -0,0 +1,201 @@ +V ALLIANCE : 6 +H nmx3_x4,P,13/ 6/2002,100 +A 0,0,7500,5000 +R 6000,2000,ref_ref,nq_20 +R 6000,4000,ref_ref,nq_40 +R 6000,3500,ref_ref,nq_35 +R 6000,3000,ref_ref,nq_30 +R 6000,2500,ref_ref,nq_25 +R 6000,1500,ref_ref,nq_15 +R 4500,2500,ref_ref,i0_25 +R 4000,3000,ref_ref,i0_30 +R 4000,2000,ref_ref,i0_20 +R 3500,3000,ref_ref,cmd0_30 +R 3500,2500,ref_ref,cmd0_25 +R 3500,2000,ref_ref,cmd0_20 +R 2500,2500,ref_ref,i1_25 +R 1500,2500,ref_ref,i2_25 +R 500,3500,ref_ref,cmd1_35 +R 500,3000,ref_ref,cmd1_30 +R 500,2500,ref_ref,cmd1_25 +R 500,2000,ref_ref,cmd1_20 +R 500,1500,ref_ref,cmd1_15 +S 5000,1750,5000,3000,200,*,DOWN,ALU1 +S 4800,3000,5000,3000,200,*,RIGHT,ALU1 +S 7200,1100,7200,3500,200,*,DOWN,ALU1 +S 6700,1000,6700,2500,200,*,UP,ALU1 +S 4800,1750,5000,1750,200,*,LEFT,ALU1 +S 4800,1000,6700,1000,200,*,RIGHT,ALU1 +S 5500,1000,5500,3500,200,*,DOWN,ALU1 +S 4800,3500,4800,4000,200,*,DOWN,ALU1 +S 4300,2000,4300,3000,200,*,UP,ALU1 +S 2200,3500,5500,3500,200,*,RIGHT,ALU1 +S 1000,4000,3200,4000,200,*,RIGHT,ALU1 +S 3300,1500,4800,1500,200,*,RIGHT,ALU1 +S 1000,1000,3200,1000,200,*,RIGHT,ALU1 +S 2700,2000,3000,2000,200,*,RIGHT,ALU1 +S 3000,2000,3000,3500,200,*,UP,ALU1 +S 2700,1500,2700,2000,200,*,UP,ALU1 +S 2200,1500,2700,1500,200,*,RIGHT,ALU1 +S 1000,3000,2400,3000,200,*,LEFT,ALU1 +S 1000,1600,1000,3000,200,*,UP,ALU1 +S 2000,2500,2500,2500,200,*,LEFT,ALU1 +S 1500,2100,1500,2500,200,*,DOWN,ALU1 +S 1000,1500,1700,1500,200,*,LEFT,ALU1 +S 700,2000,700,2600,100,*,DOWN,POLY +S 400,900,400,1800,300,*,DOWN,NDIF +S 700,1300,700,2000,100,*,DOWN,NTRANS +S 1000,1500,1000,1800,300,*,UP,NDIF +S 6000,400,6000,1500,300,*,UP,NDIF +S 5700,2100,7200,2100,100,*,RIGHT,POLY +S 5700,1500,5700,2600,100,*,DOWN,POLY +S 6000,1450,6000,4000,200,*,DOWN,ALU1 +S 5400,500,5400,1800,300,*,DOWN,NDIF +S 5700,200,5700,1500,100,*,DOWN,NTRANS +S 6900,700,6900,1500,100,*,DOWN,NTRANS +S 6600,400,6600,1300,300,*,DOWN,NDIF +S 6300,200,6300,1500,100,*,DOWN,NTRANS +S 7200,900,7200,1300,300,*,DOWN,NDIF +S 6700,1500,6900,1500,100,*,LEFT,POLY +S 6700,1500,6700,1600,100,*,UP,POLY +S 6300,1400,6300,2600,100,*,DOWN,POLY +S 6700,2600,6900,2600,100,*,RIGHT,POLY +S 6700,2500,6700,2600,100,*,UP,POLY +S 7200,2800,7200,3700,300,*,DOWN,PDIF +S 6900,2600,6900,3900,100,*,UP,PTRANS +S 0,4700,7500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,7500,3900,2400,*,RIGHT,NWELL +S 0,300,7500,300,600,vss,RIGHT,CALU1 +S 3500,2500,3800,2500,200,*,RIGHT,ALU1 +S 4300,2500,4500,2500,200,*,LEFT,ALU1 +S 4000,2000,4300,2000,200,*,RIGHT,ALU1 +S 4000,3000,4300,3000,200,*,RIGHT,ALU1 +S 400,2800,400,4000,300,*,UP,PDIF +S 6600,2800,6600,4700,300,*,UP,PDIF +S 6300,2600,6300,4900,100,*,UP,PTRANS +S 2500,3600,2500,4900,100,*,UP,PTRANS +S 3800,3800,3800,4700,200,*,UP,PDIF +S 3500,3600,3500,4900,100,*,UP,PTRANS +S 4100,3600,4100,4900,100,*,UP,PTRANS +S 4800,3800,4800,4700,300,*,UP,PDIF +S 4500,3600,4500,4900,100,*,UP,PTRANS +S 3200,3800,3200,4700,200,*,UP,PDIF +S 2900,3600,2900,4900,100,*,UP,PTRANS +S 1000,3800,1000,4700,300,*,UP,PDIF +S 1300,3600,1300,4900,100,*,UP,PTRANS +S 1600,3800,1600,4700,200,*,DOWN,PDIF +S 2200,3500,2200,4700,300,*,UP,PDIF +S 1900,3600,1900,4900,100,*,UP,PTRANS +S 5700,2600,5700,4900,100,*,UP,PTRANS +S 5400,2800,5400,4600,300,*,DOWN,PDIF +S 6000,2800,6000,4700,300,*,UP,PDIF +S 4800,2800,4800,3400,300,*,UP,PDIF +S 700,2600,700,3600,100,*,UP,PTRANS +S 5100,2600,5100,3600,100,*,UP,PTRANS +S 1000,2800,1000,3400,300,*,UP,PDIF +S 2500,400,2500,1300,100,*,UP,NTRANS +S 1900,400,1900,1300,100,*,UP,NTRANS +S 4100,200,4100,1100,100,*,UP,NTRANS +S 4500,200,4500,1100,100,*,UP,NTRANS +S 3800,400,3800,900,200,*,DOWN,NDIF +S 2900,400,2900,1300,100,*,UP,NTRANS +S 1300,400,1300,1300,100,*,UP,NTRANS +S 3500,200,3500,1100,100,*,UP,NTRANS +S 3200,400,3200,1100,300,*,DOWN,NDIF +S 2200,600,2200,1600,300,*,UP,NDIF +S 1600,600,1600,1100,200,*,DOWN,NDIF +S 1000,600,1000,1000,300,*,DOWN,NDIF +S 5100,1300,5100,2000,100,*,DOWN,NTRANS +S 4800,1500,4800,1700,300,*,DOWN,NDIF +S 1700,1500,1900,1500,100,*,RIGHT,POLY +S 400,2500,700,2500,300,*,RIGHT,POLY +S 3700,1900,3900,1900,100,*,LEFT,POLY +S 3700,1100,3700,1900,100,*,DOWN,POLY +S 3900,2500,5100,2500,100,*,RIGHT,POLY +S 1900,2000,1900,3600,100,*,DOWN,POLY +S 1900,2000,2500,2000,100,*,RIGHT,POLY +S 2500,3000,2500,3600,100,*,UP,POLY +S 3200,1500,3300,1500,100,*,LEFT,POLY +S 3500,1100,3700,1100,100,*,RIGHT,POLY +S 2500,1300,2500,2000,100,*,UP,POLY +S 2900,1300,2900,3600,100,*,DOWN,POLY +S 4100,1100,4100,1500,100,*,UP,POLY +S 2400,2500,2900,2500,100,*,RIGHT,POLY +S 4300,3000,4500,3000,100,*,RIGHT,POLY +S 4500,3000,4500,3600,100,*,UP,POLY +S 4400,2000,4500,2000,100,*,RIGHT,POLY +S 3900,1900,3900,3300,100,*,DOWN,POLY +S 3400,1500,3400,3600,100,*,UP,POLY +S 3400,3600,3500,3600,100,*,RIGHT,POLY +S 5100,2000,5100,2600,100,*,DOWN,POLY +S 4500,1100,4500,2000,100,*,DOWN,POLY +S 3900,3600,4100,3600,100,*,LEFT,POLY +S 3900,3300,3900,3600,100,*,UP,POLY +S 1300,1300,1300,3600,100,*,DOWN,POLY +S 1900,1300,1900,1500,100,*,DOWN,POLY +S 400,400,400,1000,200,*,DOWN,ALU1 +S 6600,3000,6600,4600,200,*,UP,ALU1 +S 400,4000,400,4600,200,*,UP,ALU1 +S 4800,1500,4800,1700,200,*,DOWN,ALU1 +S 4800,400,4800,1000,300,*,UP,NDIF +S 6000,1500,6000,4000,200,nq,DOWN,CALU1 +S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1 +S 2500,2500,2500,2500,200,i1,LEFT,CALU1 +S 1500,2500,1500,2500,200,i2,LEFT,CALU1 +S 500,1500,500,3500,200,cmd1,DOWN,CALU1 +S 4500,2500,4500,2500,200,i0,LEFT,CALU1 +S 4000,3000,4000,3000,200,i0,LEFT,CALU1 +S 4000,2000,4000,2000,200,i0,LEFT,CALU1 +S 500,3500,1700,3500,100,*,LEFT,ALU1 +S 1700,3500,1900,3500,300,*,RIGHT,POLY +S 1700,1500,1900,1500,300,*,RIGHT,POLY +S 1300,2500,1500,2500,300,*,RIGHT,POLY +S 4300,3000,4500,3000,300,*,RIGHT,POLY +S 4300,2000,4500,2000,300,*,RIGHT,POLY +S 7200,4300,7200,4800,300,*,DOWN,NTIE +V 1000,1600,CONT_DIF_N,* +V 6000,1500,CONT_DIF_N,* +V 6600,500,CONT_DIF_N,* +V 7200,1100,CONT_DIF_N,* +V 6700,1600,CONT_POLY,* +V 7200,2100,CONT_POLY,* +V 6700,2500,CONT_POLY,* +V 7200,3500,CONT_DIF_P,* +V 7200,3000,CONT_DIF_P,* +V 2500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 400,4000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 3800,4500,CONT_DIF_P,* +V 2200,3500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 4800,4000,CONT_DIF_P,* +V 6600,4600,CONT_DIF_P,* +V 4800,3000,CONT_DIF_P,* +V 5400,4600,CONT_DIF_P,* +V 6000,3500,CONT_DIF_P,* +V 6000,4000,CONT_DIF_P,* +V 6000,3000,CONT_DIF_P,* +V 6600,4000,CONT_DIF_P,* +V 6600,3500,CONT_DIF_P,* +V 6600,3000,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 400,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 4800,1000,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 3800,500,CONT_DIF_N,* +V 5400,500,CONT_DIF_N,* +V 2200,1500,CONT_DIF_N,* +V 4800,1700,CONT_DIF_N,* +V 400,2500,CONT_POLY,* +V 2400,3000,CONT_POLY,* +V 1700,3500,CONT_POLY,* +V 4100,1500,CONT_POLY,* +V 3300,1500,CONT_POLY,* +V 1700,1500,CONT_POLY,* +V 4300,3000,CONT_POLY,* +V 4300,2000,CONT_POLY,* +V 3800,2500,CONT_POLY,* +V 7200,4700,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nmx3_x4.vbe b/pdks/symbolic/sxlib/cells/nmx3_x4.vbe new file mode 100644 index 000000000..b6b54b2a0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx3_x4.vbe @@ -0,0 +1,55 @@ +ENTITY nmx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 810; + CONSTANT rdown_cmd1_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_cmd0_nq : NATURAL := 890; + CONSTANT rup_cmd1_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 748; + CONSTANT tphl_cmd0_nq : NATURAL := 790; + CONSTANT tphl_cmd1_nq : NATURAL := 866; + CONSTANT tphl_i1_nq : NATURAL := 869; + CONSTANT tphl_i2_nq : NATURAL := 869; + CONSTANT tplh_i0_nq : NATURAL := 900; + CONSTANT tplh_cmd0_nq : NATURAL := 936; + CONSTANT tpll_cmd1_nq : NATURAL := 952; + CONSTANT tphh_cmd1_nq : NATURAL := 981; + CONSTANT tpll_cmd0_nq : NATURAL := 993; + CONSTANT tphh_cmd0_nq : NATURAL := 1041; + CONSTANT tplh_cmd1_nq : NATURAL := 1048; + CONSTANT tplh_i1_nq : NATURAL := 1053; + CONSTANT tplh_i2_nq : NATURAL := 1053; + CONSTANT transistors : NATURAL := 24 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x4; + +ARCHITECTURE behaviour_data_flow OF nmx3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nmx3_x4" + SEVERITY WARNING; + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not + (cmd1) and i2))))) after 1700 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/nmx3_x4.vhd b/pdks/symbolic/sxlib/cells/nmx3_x4.vhd new file mode 100644 index 000000000..ae619ddab --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nmx3_x4.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nmx3_x4 IS +PORT( + cmd0 : IN STD_LOGIC; + cmd1 : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nmx3_x4; + +ARCHITECTURE RTL OF nmx3_x4 IS +BEGIN + nq <= NOT(((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2))))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/no2_x1.al b/pdks/symbolic/sxlib/cells/no2_x1.al new file mode 100644 index 000000000..827dc1ee2 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no2_x1.al @@ -0,0 +1,24 @@ +V ALLIANCE : 6 +H no2_x1,L,30/10/99 +C i0,IN,EXTERNAL,5 +C i1,IN,EXTERNAL,6 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,4,6,2,0,0.75,0.75,13.3,13.3,3,11.25,tr_00004 +T P,0.35,5.9,3,5,4,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00003 +T N,0.35,1.4,2,5,1,0,0.75,0.75,4.3,4.3,3.9,3,tr_00002 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,2.1,3,tr_00001 +S 6,EXTERNAL,i1 +Q 0.00303982 +S 5,EXTERNAL,i0 +Q 0.00343734 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vdd +Q 0.0026442 +S 2,EXTERNAL,nq +Q 0.00305526 +S 1,EXTERNAL,vss +Q 0.00299673 +EOF diff --git a/pdks/symbolic/sxlib/cells/no2_x1.ap b/pdks/symbolic/sxlib/cells/no2_x1.ap new file mode 100644 index 000000000..f273ea5ac --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no2_x1.ap @@ -0,0 +1,59 @@ +V ALLIANCE : 6 +H no2_x1,P, 5/12/2005,100 +A 0,0,2000,5000 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 500,1500,ref_ref,nq_15 +R 500,2000,ref_ref,nq_20 +R 500,2500,ref_ref,nq_25 +R 500,3000,ref_ref,nq_30 +R 500,3500,ref_ref,nq_35 +R 500,4000,ref_ref,nq_40 +R 500,1000,ref_ref,nq_10 +R 1500,1000,ref_ref,i0_10 +S 500,1000,1000,1000,200,*,LEFT,ALU1 +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 500,1000,500,4000,200,nq,DOWN,CALU1 +S 1500,1000,1500,4000,200,i0,DOWN,CALU1 +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 0,4700,2000,4700,600,vdd,RIGHT,CALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 0,300,2000,300,600,vss,RIGHT,CALU1 +S 1700,2800,1700,4700,300,*,UP,PDIF +S 700,2400,1000,2400,100,*,LEFT,POLY +S 1300,1900,1500,1900,100,*,LEFT,POLY +S 700,1400,700,2400,100,*,DOWN,POLY +S 400,400,400,1200,300,*,UP,NDIF +S 1600,400,1600,1200,300,*,UP,NDIF +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 1400,2050,1400,2600,100,*,DOWN,POLY +S 1300,1400,1300,2000,100,*,UP,POLY +V 500,4000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 1700,4500,CONT_DIF_P,* +V 1000,1000,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 1000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/no2_x1.sym b/pdks/symbolic/sxlib/cells/no2_x1.sym new file mode 100644 index 000000000..0736b807d Binary files /dev/null and b/pdks/symbolic/sxlib/cells/no2_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/no2_x1.vbe b/pdks/symbolic/sxlib/cells/no2_x1.vbe new file mode 100644 index 000000000..37a91f3f6 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no2_x1.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tplh_i0_nq : NATURAL := 121; + CONSTANT tplh_i1_nq : NATURAL := 161; + CONSTANT tphl_i1_nq : NATURAL := 193; + CONSTANT tphl_i0_nq : NATURAL := 298; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x1; + +ARCHITECTURE behaviour_data_flow OF no2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x1" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 900 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/no2_x1.vhd b/pdks/symbolic/sxlib/cells/no2_x1.vhd new file mode 100644 index 000000000..095b74bf5 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no2_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no2_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no2_x1; + +ARCHITECTURE RTL OF no2_x1 IS +BEGIN + nq <= NOT((i0 OR i1)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/no2_x4.al b/pdks/symbolic/sxlib/cells/no2_x4.al new file mode 100644 index 000000000..368b93808 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no2_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H no2_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,3,11.25,tr_00010 +T P,0.35,5.9,5,7,1,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00009 +T P,0.35,5.9,3,6,4,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00008 +T P,0.35,5.9,4,6,3,0,0.75,0.75,13.3,13.3,5.1,11.25,tr_00007 +T P,0.35,2.9,4,1,6,0,0.75,0.75,7.3,7.3,8.7,9.75,tr_00006 +T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00005 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004 +T N,0.35,1.4,6,1,2,0,0.75,0.75,4.3,4.3,8.7,3,tr_00003 +T N,0.35,2.9,2,6,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00002 +T N,0.35,2.9,3,6,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 8,EXTERNAL,i0 +Q 0.00275797 +S 7,EXTERNAL,i1 +Q 0.00260759 +S 6,INTERNAL +Q 0.00628215 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00384489 +S 3,EXTERNAL,nq +Q 0.00214456 +S 2,EXTERNAL,vss +Q 0.0046087 +S 1,INTERNAL +Q 0.00676363 +EOF diff --git a/pdks/symbolic/sxlib/cells/no2_x4.ap b/pdks/symbolic/sxlib/cells/no2_x4.ap new file mode 100644 index 000000000..9f0045ab3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no2_x4.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H no2_x4,P, 8/ 6/2002,100 +A 0,0,3500,5000 +R 2000,1500,ref_ref,nq_15 +R 2000,2000,ref_ref,nq_20 +R 2000,2500,ref_ref,nq_25 +R 2000,3000,ref_ref,nq_30 +R 2000,3500,ref_ref,nq_35 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 500,1500,ref_ref,i1_15 +R 500,2000,ref_ref,i1_20 +R 500,2500,ref_ref,i1_25 +R 500,3000,ref_ref,i1_30 +R 500,3500,ref_ref,i1_35 +R 2000,1000,ref_ref,nq_10 +S 3200,4300,3200,4800,300,*,DOWN,NTIE +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,100,2400,1400,100,*,UP,NTRANS +S 3200,1000,3200,3000,100,*,UP,ALU1 +S 1400,2800,1400,4700,300,*,UP,PDIF +S 2900,2600,2900,3900,100,*,DOWN,PTRANS +S 2600,2800,2600,4700,300,*,UP,PDIF +S 2000,2800,2000,4700,300,*,UP,PDIF +S 1700,2600,1700,4900,100,*,DOWN,PTRANS +S 2300,2600,2300,4900,100,*,DOWN,PTRANS +S 3200,2800,3200,3700,300,*,UP,PDIF +S 3200,800,3200,1200,300,*,DOWN,NDIF +S 2900,600,2900,1400,100,*,UP,NTRANS +S 2600,300,2600,1200,300,*,DOWN,NDIF +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,UP,ALU1 +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 2700,2500,2700,4000,100,*,DOWN,ALU1 +S 2400,1400,2400,2100,100,*,UP,POLY +S 2300,1900,2300,2600,100,*,DOWN,POLY +S 1700,1900,1700,2600,100,*,UP,POLY +S 1800,1400,1800,2100,100,*,DOWN,POLY +S 1700,2000,2600,2000,300,*,RIGHT,POLY +S 2600,2500,2900,2500,300,*,RIGHT,POLY +S 2500,2000,3200,2000,100,*,RIGHT,ALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 300,2800,300,4700,300,*,DOWN,PDIF +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 600,2600,600,4900,100,*,UP,PTRANS +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 1300,2800,1300,4700,300,*,DOWN,PDIF +S 600,1400,600,2600,100,*,DOWN,POLY +S 300,400,300,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,1000,1500,1000,100,*,LEFT,ALU1 +S 1500,300,1500,1200,300,*,UP,NDIF +S 1200,1400,1200,2400,100,*,UP,POLY +S 900,2400,1200,2400,100,*,LEFT,POLY +S 3200,3000,3200,3500,100,*,DOWN,ALU1 +S 2000,950,2000,3500,200,*,DOWN,ALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 2000,1000,2000,3500,200,nq,DOWN,CALU1 +S 1000,1500,1000,3500,200,i0,DOWN,CALU1 +S 500,1500,500,3500,200,i1,DOWN,CALU1 +V 2000,3500,CONT_DIF_P,* +V 2000,3000,CONT_DIF_P,* +V 2700,300,CONT_DIF_N,* +V 2700,2500,CONT_POLY,* +V 3200,4700,CONT_BODY_N,* +V 3200,3000,CONT_DIF_P,* +V 2600,4500,CONT_DIF_P,* +V 1400,4500,CONT_DIF_P,* +V 3200,1000,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 2100,1000,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 1500,400,CONT_DIF_N,* +V 3200,3500,CONT_DIF_P,* +V 300,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/no2_x4.sym b/pdks/symbolic/sxlib/cells/no2_x4.sym new file mode 100644 index 000000000..dfc6d7106 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/no2_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/no2_x4.vbe b/pdks/symbolic/sxlib/cells/no2_x4.vbe new file mode 100644 index 000000000..5060db0e8 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY no2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tplh_i0_nq : NATURAL := 447; + CONSTANT tplh_i1_nq : NATURAL := 504; + CONSTANT tphl_i1_nq : NATURAL := 522; + CONSTANT tphl_i0_nq : NATURAL := 618; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x4; + +ARCHITECTURE behaviour_data_flow OF no2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no2_x4" + SEVERITY WARNING; + nq <= not ((i0 or i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/no2_x4.vhd b/pdks/symbolic/sxlib/cells/no2_x4.vhd new file mode 100644 index 000000000..43e59322b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no2_x4; + +ARCHITECTURE RTL OF no2_x4 IS +BEGIN + nq <= NOT((i0 OR i1)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/no3_x1.al b/pdks/symbolic/sxlib/cells/no3_x1.al new file mode 100644 index 000000000..ff99b0b41 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no3_x1.al @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H no3_x1,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,5,6,3,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00006 +T P,0.35,5.9,3,7,1,0,0.75,0.75,13.3,13.3,3,11.25,tr_00005 +T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00004 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,1.4,2,6,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001 +S 8,EXTERNAL,i2 +Q 0.00361086 +S 7,EXTERNAL,i1 +Q 0.00317863 +S 6,EXTERNAL,i0 +Q 0.0032596 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00298567 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.0033382 +S 1,EXTERNAL,nq +Q 0.00381907 +EOF diff --git a/pdks/symbolic/sxlib/cells/no3_x1.ap b/pdks/symbolic/sxlib/cells/no3_x1.ap new file mode 100644 index 000000000..bab70751a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no3_x1.ap @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H no3_x1,P,18/ 5/2002,100 +A 0,0,2500,5000 +R 500,1000,ref_ref,nq_10 +R 2000,4000,ref_ref,i2_40 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 1500,4000,ref_ref,i0_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1000,4000,ref_ref,i1_40 +R 500,1500,ref_ref,nq_15 +R 500,2000,ref_ref,nq_20 +R 500,2500,ref_ref,nq_25 +R 500,3000,ref_ref,nq_30 +R 500,3500,ref_ref,nq_35 +R 500,4000,ref_ref,nq_40 +R 2000,1000,ref_ref,i2_10 +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 300,1000,1500,1000,200,*,LEFT,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 600,2400,1100,2400,100,*,LEFT,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,400,900,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 300,1000,500,1000,200,*,RIGHT,ALU1 +S 500,1000,500,4000,200,nq,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +V 1500,2000,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 500,4000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/no3_x1.sym b/pdks/symbolic/sxlib/cells/no3_x1.sym new file mode 100644 index 000000000..ca5f63b10 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/no3_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/no3_x1.vbe b/pdks/symbolic/sxlib/cells/no3_x1.vbe new file mode 100644 index 000000000..6711f8b1f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no3_x1.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT tplh_i2_nq : NATURAL := 192; + CONSTANT tphl_i1_nq : NATURAL := 215; + CONSTANT tplh_i1_nq : NATURAL := 243; + CONSTANT tplh_i0_nq : NATURAL := 246; + CONSTANT tphl_i0_nq : NATURAL := 318; + CONSTANT tphl_i2_nq : NATURAL := 407; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x1; + +ARCHITECTURE behaviour_data_flow OF no3_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x1" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/no3_x1.vhd b/pdks/symbolic/sxlib/cells/no3_x1.vhd new file mode 100644 index 000000000..9ba7168a4 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no3_x1.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no3_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no3_x1; + +ARCHITECTURE RTL OF no3_x1 IS +BEGIN + nq <= NOT(((i0 OR i1) OR i2)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/no3_x4.al b/pdks/symbolic/sxlib/cells/no3_x4.al new file mode 100644 index 000000000..1ec48c9cc --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no3_x4.al @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H no3_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,2.9,4,3,7,0,0.75,0.75,7.3,7.3,10.2,9.75,tr_00012 +T P,0.35,5.9,4,7,1,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00011 +T P,0.35,5.9,1,7,4,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00010 +T P,0.35,5.9,6,10,3,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00009 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,3,11.25,tr_00008 +T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00007 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00006 +T N,0.35,2.9,2,7,1,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00005 +T N,0.35,1.4,7,3,2,0,0.75,0.75,4.3,4.3,10.2,3,tr_00004 +T N,0.35,1.4,2,9,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003 +T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,1.4,3,10,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 10,EXTERNAL,i2 +Q 0.00260759 +S 9,EXTERNAL,i1 +Q 0.00282737 +S 8,EXTERNAL,i0 +Q 0.00282737 +S 7,INTERNAL +Q 0.00571129 +S 6,INTERNAL +Q 0 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00418636 +S 3,INTERNAL +Q 0.00784181 +S 2,EXTERNAL,vss +Q 0.00436263 +S 1,EXTERNAL,nq +Q 0.00214456 +EOF diff --git a/pdks/symbolic/sxlib/cells/no3_x4.ap b/pdks/symbolic/sxlib/cells/no3_x4.ap new file mode 100644 index 000000000..66f612c1d --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no3_x4.ap @@ -0,0 +1,99 @@ +V ALLIANCE : 6 +H no3_x4,P, 8/ 6/2002,100 +A 0,0,4000,5000 +R 2500,1000,ref_ref,nq_10 +R 500,3500,ref_ref,i2_35 +R 500,1500,ref_ref,i2_15 +R 500,2000,ref_ref,i2_20 +R 500,2500,ref_ref,i2_25 +R 500,3000,ref_ref,i2_30 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 2500,3500,ref_ref,nq_35 +R 2500,3000,ref_ref,nq_30 +R 2500,2500,ref_ref,nq_25 +R 2500,2000,ref_ref,nq_20 +R 2500,1500,ref_ref,nq_15 +S 3700,4300,3700,4800,300,*,DOWN,NTIE +S 2500,950,2500,3500,200,*,DOWN,ALU1 +S 3000,2000,3700,2000,100,*,RIGHT,ALU1 +S 3100,2500,3400,2500,300,*,RIGHT,POLY +S 2200,2000,3100,2000,300,*,RIGHT,POLY +S 2300,1400,2300,2100,100,*,DOWN,POLY +S 2200,1900,2200,2600,100,*,UP,POLY +S 2800,1900,2800,2600,100,*,DOWN,POLY +S 2900,1400,2900,2100,100,*,UP,POLY +S 3200,2500,3200,4000,100,*,DOWN,ALU1 +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2600,300,2600,1200,300,*,DOWN,NDIF +S 300,1000,2000,1000,100,*,LEFT,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 1400,2400,1800,2400,100,*,LEFT,POLY +S 1800,1400,1800,2400,100,*,UP,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1000,1400,1000,2600,100,*,DOWN,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 600,1400,600,2600,100,*,DOWN,POLY +S 1700,2800,1700,4700,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 900,400,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 3100,300,3100,1200,300,*,DOWN,NDIF +S 3400,600,3400,1400,100,*,UP,NTRANS +S 3700,800,3700,1200,300,*,DOWN,NDIF +S 3700,2800,3700,3700,300,*,UP,PDIF +S 2800,2600,2800,4900,100,*,DOWN,PTRANS +S 2200,2600,2200,4900,100,*,DOWN,PTRANS +S 2500,2800,2500,4700,300,*,UP,PDIF +S 3100,2800,3100,4700,300,*,UP,PDIF +S 3400,2600,3400,3900,100,*,DOWN,PTRANS +S 1900,2800,1900,4700,300,*,UP,PDIF +S 3700,1000,3700,3000,100,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 2900,100,2900,1400,100,*,UP,NTRANS +S 2300,100,2300,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 2500,1000,2500,3500,200,nq,DOWN,CALU1 +S 500,1500,500,3500,200,i2,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +V 3000,2000,CONT_POLY,* +V 2600,1000,CONT_DIF_N,* +V 1500,2500,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 1900,4500,CONT_DIF_P,* +V 3100,4500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 3700,4700,CONT_BODY_N,* +V 3200,2500,CONT_POLY,* +V 3200,300,CONT_DIF_N,* +V 2000,300,CONT_DIF_N,* +V 2500,3000,CONT_DIF_P,* +V 2500,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/no3_x4.sym b/pdks/symbolic/sxlib/cells/no3_x4.sym new file mode 100644 index 000000000..bfea318a2 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/no3_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/no3_x4.vbe b/pdks/symbolic/sxlib/cells/no3_x4.vbe new file mode 100644 index 000000000..52e3d602b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY no3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 545; + CONSTANT tplh_i0_nq : NATURAL := 561; + CONSTANT tplh_i1_nq : NATURAL := 623; + CONSTANT tphl_i1_nq : NATURAL := 638; + CONSTANT tplh_i2_nq : NATURAL := 640; + CONSTANT tphl_i0_nq : NATURAL := 722; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x4; + +ARCHITECTURE behaviour_data_flow OF no3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no3_x4" + SEVERITY WARNING; + nq <= not (((i0 or i1) or i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/no3_x4.vhd b/pdks/symbolic/sxlib/cells/no3_x4.vhd new file mode 100644 index 000000000..1d621496e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no3_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no3_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no3_x4; + +ARCHITECTURE RTL OF no3_x4 IS +BEGIN + nq <= NOT(((i0 OR i1) OR i2)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/no4_x1.al b/pdks/symbolic/sxlib/cells/no4_x1.al new file mode 100644 index 000000000..315b53be7 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no4_x1.al @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H no4_x1,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,10 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,3,8,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00008 +T P,0.35,5.9,6,10,2,0,0.75,0.75,13.3,13.3,3,11.25,tr_00007 +T P,0.35,5.9,4,7,6,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00006 +T P,0.35,5.9,5,9,3,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00005 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004 +T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003 +T N,0.35,1.4,1,10,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00002 +T N,0.35,1.4,2,9,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00001 +S 10,EXTERNAL,i1 +Q 0.00317863 +S 9,EXTERNAL,i3 +Q 0.00310922 +S 8,EXTERNAL,i2 +Q 0.00332901 +S 7,EXTERNAL,i0 +Q 0.0032596 +S 6,INTERNAL +Q 0 +S 5,EXTERNAL,vdd +Q 0.00332715 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,nq +Q 0.00399534 +S 1,EXTERNAL,vss +Q 0.00403221 +EOF diff --git a/pdks/symbolic/sxlib/cells/no4_x1.ap b/pdks/symbolic/sxlib/cells/no4_x1.ap new file mode 100644 index 000000000..8640dd0f9 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no4_x1.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H no4_x1,P,18/ 5/2002,100 +A 0,0,3000,5000 +R 500,1000,ref_ref,nq_10 +R 500,3500,ref_ref,nq_35 +R 500,3000,ref_ref,nq_30 +R 500,2500,ref_ref,nq_25 +R 500,2000,ref_ref,nq_20 +R 500,1500,ref_ref,nq_15 +R 500,4000,ref_ref,nq_40 +R 2500,1500,ref_ref,i3_15 +R 2500,2000,ref_ref,i3_20 +R 2500,2500,ref_ref,i3_25 +R 2500,3000,ref_ref,i3_30 +R 2500,3500,ref_ref,i3_35 +R 2500,4000,ref_ref,i3_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 1500,4000,ref_ref,i0_40 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 2000,4000,ref_ref,i2_40 +S 450,1000,850,1000,200,*,LEFT,ALU1 +S 500,950,500,4000,200,*,DOWN,ALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 2500,1500,2500,4000,100,*,UP,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 1500,400,1500,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2000,1500,2000,4000,100,*,UP,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,2400,1100,2400,100,*,LEFT,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 850,1000,2100,1000,200,*,LEFT,ALU1 +S 500,1000,500,4000,200,nq,DOWN,CALU1 +S 2500,1500,2500,4000,200,i3,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 2000,1500,2000,4000,200,i2,DOWN,CALU1 +V 2700,500,CONT_DIF_N,* +V 2500,4500,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 2500,2000,CONT_POLY,* +V 1500,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/no4_x1.sym b/pdks/symbolic/sxlib/cells/no4_x1.sym new file mode 100644 index 000000000..b45e14775 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/no4_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/no4_x1.vbe b/pdks/symbolic/sxlib/cells/no4_x1.vbe new file mode 100644 index 000000000..5d15a3cd4 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no4_x1.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rdown_i3_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT tphl_i1_nq : NATURAL := 230; + CONSTANT tplh_i3_nq : NATURAL := 271; + CONSTANT tplh_i1_nq : NATURAL := 320; + CONSTANT tphl_i0_nq : NATURAL := 330; + CONSTANT tplh_i2_nq : NATURAL := 333; + CONSTANT tplh_i0_nq : NATURAL := 340; + CONSTANT tphl_i2_nq : NATURAL := 419; + CONSTANT tphl_i3_nq : NATURAL := 499; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x1; + +ARCHITECTURE behaviour_data_flow OF no4_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x1" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1100 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/no4_x1.vhd b/pdks/symbolic/sxlib/cells/no4_x1.vhd new file mode 100644 index 000000000..651a0b4f8 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no4_x1.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no4_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no4_x1; + +ARCHITECTURE RTL OF no4_x1 IS +BEGIN + nq <= NOT((((i0 OR i1) OR i2) OR i3)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/no4_x4.al b/pdks/symbolic/sxlib/cells/no4_x4.al new file mode 100644 index 000000000..df49bccfd --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no4_x4.al @@ -0,0 +1,48 @@ +V ALLIANCE : 6 +H no4_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,10 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C nq,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,4,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00014 +T P,0.35,5.9,3,10,1,0,0.75,0.75,13.3,13.3,3,11.25,tr_00013 +T P,0.35,5.9,5,7,3,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00012 +T P,0.35,5.9,6,9,4,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00011 +T P,0.35,5.9,11,12,6,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00010 +T P,0.35,5.9,6,12,11,0,0.75,0.75,13.3,13.3,9.6,11.25,tr_00009 +T P,0.35,2.9,6,1,12,0,0.75,0.75,7.3,7.3,13.2,9.75,tr_00008 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00007 +T N,0.35,1.4,2,8,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00006 +T N,0.35,1.4,2,10,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005 +T N,0.35,1.4,1,9,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00004 +T N,0.35,2.9,11,12,2,0,0.75,0.75,7.3,7.3,9.6,2.25,tr_00003 +T N,0.35,2.9,2,12,11,0,0.75,0.75,7.3,7.3,11.4,2.25,tr_00002 +T N,0.35,1.4,12,1,2,0,0.75,0.75,4.3,4.3,13.2,3,tr_00001 +S 12,INTERNAL +Q 0.00586076 +S 11,EXTERNAL,nq +Q 0.00229144 +S 10,EXTERNAL,i1 +Q 0.00317863 +S 9,EXTERNAL,i3 +Q 0.00310922 +S 8,EXTERNAL,i2 +Q 0.00332901 +S 7,EXTERNAL,i0 +Q 0.0032596 +S 6,EXTERNAL,vdd +Q 0.00674947 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.00575064 +S 1,INTERNAL +Q 0.00812639 +EOF diff --git a/pdks/symbolic/sxlib/cells/no4_x4.ap b/pdks/symbolic/sxlib/cells/no4_x4.ap new file mode 100644 index 000000000..9d97393e5 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no4_x4.ap @@ -0,0 +1,135 @@ +V ALLIANCE : 6 +H no4_x4,P, 8/ 6/2002,100 +A 0,0,5000,5000 +R 3500,3000,ref_ref,nq_30 +R 3500,2500,ref_ref,nq_25 +R 3500,2000,ref_ref,nq_20 +R 3500,1500,ref_ref,nq_15 +R 3500,4000,ref_ref,nq_40 +R 3500,3500,ref_ref,nq_35 +R 2500,1500,ref_ref,i3_15 +R 2500,2000,ref_ref,i3_20 +R 2500,2500,ref_ref,i3_25 +R 2500,3000,ref_ref,i3_30 +R 2500,3500,ref_ref,i3_35 +R 2500,4000,ref_ref,i3_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 1500,4000,ref_ref,i0_40 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 2000,4000,ref_ref,i2_40 +S 4700,4300,4700,4800,300,*,DOWN,NTIE +S 4700,3000,4700,3500,100,*,DOWN,ALU1 +S 500,1000,900,1000,200,*,LEFT,ALU1 +S 500,1000,4000,1000,100,*,LEFT,ALU1 +S 500,3000,500,4000,100,*,UP,ALU1 +S 500,1000,500,3000,100,*,DOWN,ALU1 +S 4100,3000,4100,4500,200,*,DOWN,ALU1 +S 3500,300,3500,1600,300,*,DOWN,NDIF +S 4000,1000,4000,2500,100,*,UP,ALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 2800,2800,2800,4700,400,*,UP,PDIF +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 4000,1500,4200,1500,200,*,RIGHT,ALU1 +S 4200,1500,4400,1500,300,*,RIGHT,POLY +S 3200,2000,4700,2000,300,*,RIGHT,POLY +S 4700,1000,4700,3000,100,*,UP,ALU1 +S 4200,2500,4400,2500,300,*,RIGHT,POLY +S 3800,1400,3800,2600,100,*,UP,POLY +S 3200,1400,3200,2600,100,*,UP,POLY +S 2900,2800,2900,4700,300,*,UP,PDIF +S 4400,2600,4400,3900,100,*,DOWN,PTRANS +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3500,2800,3500,4700,300,*,UP,PDIF +S 3200,2600,3200,4900,100,*,DOWN,PTRANS +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 4700,2800,4700,3700,300,*,UP,PDIF +S 4700,800,4700,1200,300,*,DOWN,NDIF +S 4400,600,4400,1400,100,*,UP,NTRANS +S 3800,100,3800,1400,100,*,UP,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 3200,100,3200,1400,100,*,UP,NTRANS +S 2900,300,2900,1200,300,*,DOWN,NDIF +S 4000,2500,4200,2500,200,*,RIGHT,ALU1 +S 2500,1500,2500,4000,100,*,UP,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 1500,400,1500,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2000,1500,2000,4000,100,*,UP,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,2400,1100,2400,100,*,LEFT,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 3500,1500,3500,4000,200,*,DOWN,ALU1 +S 3500,1500,3500,4000,200,nq,DOWN,CALU1 +S 2500,1500,2500,4000,200,i3,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 2000,1500,2000,4000,200,i2,DOWN,CALU1 +V 4700,3500,CONT_DIF_P,* +V 2900,4500,CONT_DIF_P,* +V 2500,4500,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 4100,3000,CONT_DIF_P,* +V 4100,3500,CONT_DIF_P,* +V 4100,4000,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 3500,1500,CONT_DIF_N,* +V 3500,3000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 3500,4000,CONT_DIF_P,* +V 2800,500,CONT_DIF_N,* +V 4200,1500,CONT_POLY,* +V 4700,2000,CONT_POLY,* +V 4200,2500,CONT_POLY,* +V 4700,4700,CONT_BODY_N,* +V 4700,3000,CONT_DIF_P,* +V 4100,4500,CONT_DIF_P,* +V 4100,500,CONT_DIF_N,* +V 4700,1000,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 1500,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/no4_x4.sym b/pdks/symbolic/sxlib/cells/no4_x4.sym new file mode 100644 index 000000000..ca15cbb22 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/no4_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/no4_x4.vbe b/pdks/symbolic/sxlib/cells/no4_x4.vbe new file mode 100644 index 000000000..cffb179c4 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY no4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 564; + CONSTANT tphl_i0_nq : NATURAL := 656; + CONSTANT tplh_i3_nq : NATURAL := 693; + CONSTANT tphl_i2_nq : NATURAL := 739; + CONSTANT tplh_i2_nq : NATURAL := 761; + CONSTANT tplh_i1_nq : NATURAL := 768; + CONSTANT tplh_i0_nq : NATURAL := 777; + CONSTANT tphl_i3_nq : NATURAL := 816; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x4; + +ARCHITECTURE behaviour_data_flow OF no4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on no4_x4" + SEVERITY WARNING; + nq <= not ((((i0 or i1) or i2) or i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/no4_x4.vhd b/pdks/symbolic/sxlib/cells/no4_x4.vhd new file mode 100644 index 000000000..855a29a7a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/no4_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY no4_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END no4_x4; + +ARCHITECTURE RTL OF no4_x4 IS +BEGIN + nq <= NOT((((i0 OR i1) OR i2) OR i3)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa22_x1.al b/pdks/symbolic/sxlib/cells/noa22_x1.al new file mode 100644 index 000000000..fe536c466 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa22_x1.al @@ -0,0 +1,31 @@ +V ALLIANCE : 6 +H noa22_x1,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,5,8,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,5.9,2,6,4,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00005 +T P,0.35,5.9,4,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00004 +T N,0.35,2.9,3,6,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00003 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 8,EXTERNAL,i2 +Q 0.00344864 +S 7,EXTERNAL,i1 +Q 0.00288494 +S 6,EXTERNAL,i0 +Q 0.00260759 +S 5,EXTERNAL,vdd +Q 0.004561 +S 4,INTERNAL +Q 0.00171257 +S 3,EXTERNAL,vss +Q 0.00450225 +S 2,EXTERNAL,nq +Q 0.0026146 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa22_x1.ap b/pdks/symbolic/sxlib/cells/noa22_x1.ap new file mode 100644 index 000000000..9ccee5a96 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa22_x1.ap @@ -0,0 +1,82 @@ +V ALLIANCE : 6 +H noa22_x1,P, 8/ 6/2002,100 +A 0,0,3000,5000 +R 2000,4000,ref_ref,i2_40 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 2000,1000,ref_ref,i2_10 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 1500,1000,ref_ref,nq_10 +R 1500,1500,ref_ref,nq_15 +R 1500,2000,ref_ref,nq_20 +R 1500,2500,ref_ref,nq_25 +R 1500,3000,ref_ref,nq_30 +R 1500,3500,ref_ref,nq_35 +S 2700,200,2700,700,300,*,UP,PTIE +S 2700,1300,2700,1800,300,*,DOWN,PTIE +S 2700,2800,2700,3300,300,*,UP,NTIE +S 2700,4300,2700,4800,300,*,DOWN,NTIE +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 1500,1000,1500,3500,200,nq,DOWN,CALU1 +S 0,3900,3000,3900,2400,*,LEFT,NWELL +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2700,500,2700,1700,200,*,DOWN,ALU1 +S 2700,2900,2700,4500,200,*,DOWN,ALU1 +S 2000,1000,2000,4000,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 500,1000,500,3000,100,*,UP,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 900,3500,1500,3500,200,*,RIGHT,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 1500,1000,1500,3550,200,*,UP,ALU1 +V 2700,300,CONT_BODY_P,* +V 2700,4700,CONT_BODY_N,* +V 2700,2900,CONT_BODY_N,* +V 2700,1700,CONT_BODY_P,* +V 2100,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 300,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa22_x1.sym b/pdks/symbolic/sxlib/cells/noa22_x1.sym new file mode 100644 index 000000000..feab16976 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/noa22_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/noa22_x1.vbe b/pdks/symbolic/sxlib/cells/noa22_x1.vbe new file mode 100644 index 000000000..5c13864f3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa22_x1.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 1620; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tphl_i2_nq : NATURAL := 218; + CONSTANT tplh_i2_nq : NATURAL := 241; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x1; + +ARCHITECTURE behaviour_data_flow OF noa22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 900 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa22_x1.vhd b/pdks/symbolic/sxlib/cells/noa22_x1.vhd new file mode 100644 index 000000000..504470193 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa22_x1.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa22_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa22_x1; + +ARCHITECTURE RTL OF noa22_x1 IS +BEGIN + nq <= NOT(((i0 AND i1) OR i2)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa22_x4.al b/pdks/symbolic/sxlib/cells/noa22_x4.al new file mode 100644 index 000000000..8157586a6 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa22_x4.al @@ -0,0 +1,41 @@ +V ALLIANCE : 6 +H noa22_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,5 +C i2,IN,EXTERNAL,6 +C nq,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,9 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,8,4,9,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00012 +T P,0.35,5.9,9,4,8,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00011 +T P,0.35,2.9,9,1,4,0,0.75,0.75,7.3,7.3,9.3,9.75,tr_00010 +T P,0.35,2.9,10,6,9,0,0.75,0.75,7.3,7.3,2.1,11.25,tr_00009 +T P,0.35,2.9,10,7,1,0,0.75,0.75,7.3,7.3,5.7,11.25,tr_00008 +T P,0.35,2.9,1,5,10,0,0.75,0.75,7.3,7.3,3.9,11.25,tr_00007 +T N,0.35,2.9,8,4,3,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00006 +T N,0.35,1.4,4,1,3,0,0.75,0.75,4.3,4.3,9.3,3,tr_00005 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,5.7,3,tr_00004 +T N,0.35,1.4,1,5,2,0,0.75,0.75,4.3,4.3,3.9,3,tr_00003 +T N,0.35,2.9,3,4,8,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00002 +T N,0.35,1.4,3,6,1,0,0.75,0.75,4.3,4.3,2.1,3,tr_00001 +S 10,INTERNAL +Q 0.00114171 +S 9,EXTERNAL,vdd +Q 0.00768955 +S 8,EXTERNAL,nq +Q 0.00258522 +S 7,EXTERNAL,i0 +Q 0.00295462 +S 6,EXTERNAL,i2 +Q 0.00379567 +S 5,EXTERNAL,i1 +Q 0.00323197 +S 4,INTERNAL +Q 0.00518414 +S 3,EXTERNAL,vss +Q 0.00674947 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00560501 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa22_x4.ap b/pdks/symbolic/sxlib/cells/noa22_x4.ap new file mode 100644 index 000000000..34a631f37 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa22_x4.ap @@ -0,0 +1,123 @@ +V ALLIANCE : 6 +H noa22_x4,P,18/ 5/2002,100 +A 0,0,5000,5000 +R 2000,1500,ref_ref,i0_15 +R 2000,1000,ref_ref,i0_10 +R 4000,4000,ref_ref,nq_40 +R 1500,1000,ref_ref,i1_10 +R 1500,1500,ref_ref,i1_15 +R 1500,2000,ref_ref,i1_20 +R 1500,2500,ref_ref,i1_25 +R 1500,3000,ref_ref,i1_30 +R 2000,3000,ref_ref,i0_30 +R 2000,2500,ref_ref,i0_25 +R 2000,2000,ref_ref,i0_20 +R 500,3000,ref_ref,i2_30 +R 500,2500,ref_ref,i2_25 +R 500,2000,ref_ref,i2_20 +R 500,1500,ref_ref,i2_15 +R 500,1000,ref_ref,i2_10 +R 4000,2500,ref_ref,nq_25 +R 4000,1500,ref_ref,nq_15 +R 4000,1000,ref_ref,nq_10 +R 4000,2000,ref_ref,nq_20 +R 4000,3000,ref_ref,nq_30 +R 4000,3500,ref_ref,nq_35 +R 500,3500,ref_ref,i2_35 +R 500,4000,ref_ref,i2_40 +S 900,300,1700,300,300,*,RIGHT,PTIE +S 900,4700,2900,4700,300,*,RIGHT,NTIE +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 2200,3300,2200,4200,300,*,DOWN,PDIF +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 1900,3100,1900,4400,100,*,UP,PTRANS +S 700,3100,700,4400,100,*,UP,PTRANS +S 2800,2800,2800,3700,300,*,DOWN,PDIF +S 3100,2600,3100,3900,100,*,UP,PTRANS +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 400,400,400,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 2200,400,2200,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1600,800,1600,1200,300,*,UP,NDIF +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 2800,800,2800,1200,300,*,UP,NDIF +S 3100,600,3100,1400,100,*,DOWN,NTRANS +S 4600,300,4600,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 3400,300,3400,1200,300,*,UP,NDIF +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 1900,1400,1900,3100,100,*,DOWN,POLY +S 1300,1400,1300,3100,100,*,DOWN,POLY +S 700,1400,700,3100,100,*,DOWN,POLY +S 3100,1400,3100,2600,100,*,DOWN,POLY +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 3100,2500,3300,2500,300,*,RIGHT,POLY +S 3500,2000,4300,2000,300,*,RIGHT,POLY +S 1300,2000,1500,2000,300,*,RIGHT,POLY +S 500,2000,700,2000,300,*,RIGHT,POLY +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 1000,4000,2200,4000,100,*,RIGHT,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 2000,1000,2000,3000,100,*,DOWN,ALU1 +S 3300,2500,3300,3500,100,*,DOWN,ALU1 +S 2800,2000,3500,2000,100,*,RIGHT,ALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,UP,ALU1 +S 2800,1000,2800,3000,100,*,DOWN,ALU1 +S 1500,1000,1500,3000,100,*,DOWN,ALU1 +S 1000,3500,3300,3500,100,*,RIGHT,ALU1 +S 1600,3300,1600,4200,300,*,DOWN,PDIF +S 400,3300,400,4600,300,*,DOWN,PDIF +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 2000,1000,2000,3000,200,i0,DOWN,CALU1 +S 4000,1000,4000,4000,200,nq,DOWN,CALU1 +S 1500,1000,1500,3000,200,i1,DOWN,CALU1 +S 500,1000,500,4000,200,i2,DOWN,CALU1 +V 4000,4000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 2200,4700,CONT_BODY_N,* +V 4600,4500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 2800,3000,CONT_DIF_P,* +V 2800,4700,CONT_BODY_N,* +V 1000,4700,CONT_BODY_N,* +V 2200,4000,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 3400,4000,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 400,500,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 4600,500,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 2200,500,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 1000,300,CONT_BODY_P,* +V 1600,300,CONT_BODY_P,* +V 1500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 3300,2500,CONT_POLY,* +V 3500,2000,CONT_POLY,* +V 1600,3500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1600,4700,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa22_x4.sym b/pdks/symbolic/sxlib/cells/noa22_x4.sym new file mode 100644 index 000000000..cbc2e448b Binary files /dev/null and b/pdks/symbolic/sxlib/cells/noa22_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/noa22_x4.vbe b/pdks/symbolic/sxlib/cells/noa22_x4.vbe new file mode 100644 index 000000000..6288a32e6 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY noa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 550; + CONSTANT tphl_i2_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i2_nq : NATURAL := 646; + CONSTANT tplh_i1_nq : NATURAL := 709; + CONSTANT tplh_i0_nq : NATURAL := 740; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa22_x4; + +ARCHITECTURE behaviour_data_flow OF noa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or i2)) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa22_x4.vhd b/pdks/symbolic/sxlib/cells/noa22_x4.vhd new file mode 100644 index 000000000..8723b6636 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa22_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa22_x4; + +ARCHITECTURE RTL OF noa22_x4 IS +BEGIN + nq <= NOT(((i0 AND i1) OR i2)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa2a22_x1.al b/pdks/symbolic/sxlib/cells/noa2a22_x1.al new file mode 100644 index 000000000..3e8dac59b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a22_x1.al @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H noa2a22_x1,L,30/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,5,8,3,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00008 +T P,0.35,5.9,3,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00007 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005 +T N,0.35,2.9,4,9,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,2.9,3,7,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00003 +T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 10,EXTERNAL,i0 +Q 0.00260759 +S 9,EXTERNAL,i2 +Q 0.00288944 +S 8,EXTERNAL,i1 +Q 0.00288494 +S 7,EXTERNAL,i3 +Q 0.00316679 +S 6,EXTERNAL,vdd +Q 0.00472621 +S 5,INTERNAL +Q 0.00199441 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,nq +Q 0.00264397 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00466746 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a22_x1.ap b/pdks/symbolic/sxlib/cells/noa2a22_x1.ap new file mode 100644 index 000000000..3d740ab37 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a22_x1.ap @@ -0,0 +1,88 @@ +V ALLIANCE : 6 +H noa2a22_x1,P,10/ 6/2002,100 +A 0,0,3500,5000 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 1500,1000,ref_ref,nq_10 +R 2500,1000,ref_ref,i2_10 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2500,3500,ref_ref,i2_35 +R 2000,3500,ref_ref,i3_35 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,2000,ref_ref,i3_20 +R 2000,1500,ref_ref,i3_15 +R 2000,1000,ref_ref,i3_10 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +S 3200,2900,3200,3300,300,*,DOWN,NTIE +S 2600,2800,2600,3700,300,*,UP,PDIF +S 2700,3700,2700,4700,300,*,DOWN,PDIF +S 1500,1000,1500,3500,200,nq,DOWN,CALU1 +S 2500,1000,2500,3500,200,i2,DOWN,CALU1 +S 2000,1000,2000,3500,200,i3,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 0,3900,3500,3900,2400,*,LEFT,NWELL +S 3200,2900,3200,4500,200,*,DOWN,ALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,1400,600,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 2000,1000,2000,3500,100,*,DOWN,ALU1 +S 2500,1000,2500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1500,1000,1500,3550,200,*,UP,ALU1 +S 900,3500,1550,3500,200,*,RIGHT,ALU1 +V 3200,2900,CONT_BODY_N,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a22_x1.sym b/pdks/symbolic/sxlib/cells/noa2a22_x1.sym new file mode 100644 index 000000000..8a5d4d5c9 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/noa2a22_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/noa2a22_x1.vbe b/pdks/symbolic/sxlib/cells/noa2a22_x1.vbe new file mode 100644 index 000000000..d63481981 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a22_x1.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i3_nq : NATURAL := 256; + CONSTANT tphl_i2_nq : NATURAL := 284; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i2_nq : NATURAL := 289; + CONSTANT tplh_i0_nq : NATURAL := 327; + CONSTANT tphl_i3_nq : NATURAL := 372; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa2a22_x1.vhd b/pdks/symbolic/sxlib/cells/noa2a22_x1.vhd new file mode 100644 index 000000000..acb4a088c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a22_x1.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a22_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a22_x1; + +ARCHITECTURE RTL OF noa2a22_x1 IS +BEGIN + nq <= NOT(((i0 AND i1) OR (i2 AND i3))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa2a22_x4.al b/pdks/symbolic/sxlib/cells/noa2a22_x4.al new file mode 100644 index 000000000..d5b7bc86c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a22_x4.al @@ -0,0 +1,48 @@ +V ALLIANCE : 6 +H noa2a22_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,5 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,9 +C vdd,IN,EXTERNAL,11 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,12,5,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00014 +T P,0.35,2.9,12,8,11,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00013 +T P,0.35,2.9,11,7,12,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00012 +T P,0.35,2.9,3,6,12,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00011 +T P,0.35,5.9,9,10,11,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00010 +T P,0.35,5.9,11,10,9,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00009 +T P,0.35,2.9,11,3,10,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00008 +T N,0.35,1.4,2,5,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00007 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006 +T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00005 +T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004 +T N,0.35,2.9,1,10,9,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00003 +T N,0.35,2.9,9,10,1,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00002 +T N,0.35,1.4,10,3,1,0,0.75,0.75,4.3,4.3,10.8,3,tr_00001 +S 12,INTERNAL +Q 0.00199441 +S 11,EXTERNAL,vdd +Q 0.00803103 +S 10,INTERNAL +Q 0.00518414 +S 9,EXTERNAL,nq +Q 0.00258522 +S 8,EXTERNAL,i2 +Q 0.00295462 +S 7,EXTERNAL,i3 +Q 0.00323197 +S 6,EXTERNAL,i0 +Q 0.00295462 +S 5,EXTERNAL,i1 +Q 0.00323197 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00594323 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00726721 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a22_x4.ap b/pdks/symbolic/sxlib/cells/noa2a22_x4.ap new file mode 100644 index 000000000..9032c64da --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a22_x4.ap @@ -0,0 +1,138 @@ +V ALLIANCE : 6 +H noa2a22_x4,P,18/ 5/2002,100 +A 0,0,5500,5000 +R 4500,2500,ref_ref,nq_25 +R 4500,1500,ref_ref,nq_15 +R 4500,1000,ref_ref,nq_10 +R 4500,2000,ref_ref,nq_20 +R 4500,3000,ref_ref,nq_30 +R 4500,3500,ref_ref,nq_35 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 2000,1000,ref_ref,i3_10 +R 2000,1500,ref_ref,i3_15 +R 2000,2000,ref_ref,i3_20 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 2500,1000,ref_ref,i2_10 +R 4500,4000,ref_ref,nq_40 +S 2600,4700,3400,4700,300,*,RIGHT,NTIE +S 900,300,2100,300,300,*,LEFT,PTIE +S 300,4700,1500,4700,300,*,RIGHT,NTIE +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 3300,1000,3300,3000,100,*,DOWN,ALU1 +S 3300,800,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,3700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 5100,300,5100,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 3900,300,3900,1200,300,*,UP,NDIF +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 2000,1000,2000,3000,100,*,DOWN,ALU1 +S 2500,1000,2500,3000,100,*,DOWN,ALU1 +S 900,3500,3800,3500,100,*,RIGHT,ALU1 +S 3800,2500,3800,3500,100,*,DOWN,ALU1 +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 3300,2000,4000,2000,100,*,RIGHT,ALU1 +S 3600,2500,3800,2500,300,*,RIGHT,POLY +S 3900,4000,3900,4500,200,*,DOWN,ALU1 +S 5100,3000,5100,4500,200,*,DOWN,ALU1 +S 5100,500,5100,1000,200,*,DOWN,ALU1 +S 3900,500,3900,1000,200,*,DOWN,ALU1 +S 4000,2000,4800,2000,300,*,RIGHT,POLY +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 2700,3300,2700,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 300,400,300,1200,300,*,UP,NDIF +S 2700,400,2700,1200,300,*,UP,NDIF +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 4500,1000,4500,4000,200,*,UP,ALU1 +S 4500,1000,4500,4000,200,nq,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 2000,1000,2000,3000,200,i3,DOWN,CALU1 +S 2500,1000,2500,3000,200,i2,DOWN,CALU1 +V 2700,4700,CONT_BODY_N,* +V 4500,4000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 4500,3000,CONT_DIF_P,* +V 2100,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 900,4700,CONT_BODY_N,* +V 1500,1000,CONT_DIF_N,* +V 4500,1000,CONT_DIF_N,* +V 5100,500,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2700,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3800,2500,CONT_POLY,* +V 3900,4000,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 3300,3000,CONT_DIF_P,* +V 3300,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 4000,2000,CONT_POLY,* +V 3300,4700,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a22_x4.sym b/pdks/symbolic/sxlib/cells/noa2a22_x4.sym new file mode 100644 index 000000000..aac4b28cc Binary files /dev/null and b/pdks/symbolic/sxlib/cells/noa2a22_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/noa2a22_x4.vbe b/pdks/symbolic/sxlib/cells/noa2a22_x4.vbe new file mode 100644 index 000000000..93e31d341 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY noa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 562; + CONSTANT tphl_i1_nq : NATURAL := 646; + CONSTANT tplh_i3_nq : NATURAL := 677; + CONSTANT tphl_i2_nq : NATURAL := 701; + CONSTANT tplh_i2_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 714; + CONSTANT tplh_i0_nq : NATURAL := 745; + CONSTANT tphl_i3_nq : NATURAL := 805; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a22_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or (i2 and i3))) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa2a22_x4.vhd b/pdks/symbolic/sxlib/cells/noa2a22_x4.vhd new file mode 100644 index 000000000..73870fd0c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a22_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a22_x4; + +ARCHITECTURE RTL OF noa2a22_x4 IS +BEGIN + nq <= NOT(((i0 AND i1) OR (i2 AND i3))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa2a2a23_x1.al b/pdks/symbolic/sxlib/cells/noa2a2a23_x1.al new file mode 100644 index 000000000..c68647d74 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a23_x1.al @@ -0,0 +1,52 @@ +V ALLIANCE : 6 +H noa2a2a23_x1,L,30/10/99 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,14 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,12 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,5,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00012 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,12,13,6,0,0.75,0.75,13.3,13.3,13.2,11.25,tr_00008 +T P,0.35,5.9,6,14,12,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00007 +T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00006 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,2.9,1,13,11,0,0.75,0.75,7.3,7.3,13.2,2.25,tr_00004 +T N,0.35,2.9,11,14,2,0,0.75,0.75,7.3,7.3,12,2.25,tr_00003 +T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00002 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00001 +S 14,EXTERNAL,i1 +Q 0.0026959 +S 13,EXTERNAL,i0 +Q 0.00232574 +S 12,EXTERNAL,vdd +Q 0.00651445 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i5 +Q 0.00276531 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i3 +Q 0.00262649 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00198726 +S 5,INTERNAL +Q 0.00199441 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,nq +Q 0.00458289 +S 1,EXTERNAL,vss +Q 0.00575064 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a2a23_x1.ap b/pdks/symbolic/sxlib/cells/noa2a2a23_x1.ap new file mode 100644 index 000000000..5d95cf93d --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a23_x1.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H noa2a2a23_x1,P, 8/ 6/2002,100 +A 0,0,5000,5000 +R 1000,2000,ref_ref,i5_20 +R 1000,2500,ref_ref,i5_25 +R 1000,3000,ref_ref,i5_30 +R 1000,1500,ref_ref,i5_15 +R 2000,1500,ref_ref,i3_15 +R 2000,2500,ref_ref,i3_25 +R 2000,3000,ref_ref,i3_30 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2000,2000,ref_ref,i3_20 +R 1500,1500,ref_ref,i4_15 +R 1500,2000,ref_ref,i4_20 +R 1500,2500,ref_ref,i4_25 +R 500,2500,ref_ref,nq_25 +R 500,2000,ref_ref,nq_20 +R 500,1500,ref_ref,nq_15 +R 500,3500,ref_ref,nq_35 +R 500,3000,ref_ref,nq_30 +R 4000,2000,ref_ref,i1_20 +R 4500,2500,ref_ref,i0_25 +R 4500,2000,ref_ref,i0_20 +R 4500,1500,ref_ref,i0_15 +R 4500,3000,ref_ref,i0_30 +R 4000,3000,ref_ref,i1_30 +R 4000,2500,ref_ref,i1_25 +R 4000,1500,ref_ref,i1_15 +R 500,1000,ref_ref,nq_10 +R 1500,3000,ref_ref,i4_30 +R 1500,3500,ref_ref,i4_35 +S 3100,300,3100,800,300,*,UP,PTIE +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 4500,1500,4500,3000,200,i0,DOWN,CALU1 +S 4000,1500,4000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3500,200,nq,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 4700,300,4700,1000,200,*,DOWN,ALU1 +S 4400,1400,4400,2600,100,*,DOWN,POLY +S 4400,100,4400,1400,100,*,UP,NTRANS +S 4400,2600,4400,4900,100,*,UP,PTRANS +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3800,2600,3800,4900,100,*,UP,PTRANS +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 900,1400,900,2600,100,*,DOWN,POLY +S 500,950,500,3550,200,*,DOWN,ALU1 +S 450,3500,900,3500,200,*,RIGHT,ALU1 +S 3500,4000,3500,4700,200,*,UP,ALU1 +S 2100,3500,4100,3500,100,*,RIGHT,ALU1 +S 4100,3500,4100,4000,100,*,UP,ALU1 +S 4700,2800,4700,4700,300,*,UP,PDIF +S 4700,3500,4700,4600,200,*,DOWN,ALU1 +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 4700,300,4700,1200,300,*,DOWN,NDIF +S 4000,1400,4000,2500,100,*,UP,POLY +S 3800,2500,4000,2500,100,*,LEFT,POLY +S 3800,2500,3800,2700,100,*,UP,POLY +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 800,100,800,1400,100,*,UP,NTRANS +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,1400,900,1400,100,*,LEFT,POLY +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 450,1000,3700,1000,200,*,LEFT,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3500,2800,3500,4700,300,*,UP,PDIF +V 1500,1000,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 3900,2500,CONT_POLY,* +V 4700,1000,CONT_DIF_N,* +V 4100,4000,CONT_DIF_P,* +V 4700,4000,CONT_DIF_P,* +V 2500,2500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 3500,4000,CONT_DIF_P,* +V 4700,4500,CONT_DIF_P,* +V 4700,3500,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 4700,500,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 3100,400,CONT_BODY_P,* +V 4500,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a2a23_x1.sym b/pdks/symbolic/sxlib/cells/noa2a2a23_x1.sym new file mode 100644 index 000000000..87e8c14f3 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/noa2a2a23_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/noa2a2a23_x1.vbe b/pdks/symbolic/sxlib/cells/noa2a2a23_x1.vbe new file mode 100644 index 000000000..2d90886a0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a23_x1.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT rup_i3_nq : NATURAL := 4690; + CONSTANT rup_i4_nq : NATURAL := 4690; + CONSTANT rup_i5_nq : NATURAL := 4690; + CONSTANT tphl_i5_nq : NATURAL := 178; + CONSTANT tphl_i4_nq : NATURAL := 250; + CONSTANT tphl_i2_nq : NATURAL := 307; + CONSTANT tplh_i1_nq : NATURAL := 388; + CONSTANT tphl_i3_nq : NATURAL := 398; + CONSTANT tplh_i4_nq : NATURAL := 416; + CONSTANT tplh_i0_nq : NATURAL := 425; + CONSTANT tplh_i3_nq : NATURAL := 438; + CONSTANT tplh_i5_nq : NATURAL := 464; + CONSTANT tplh_i2_nq : NATURAL := 479; + CONSTANT tphl_i0_nq : NATURAL := 525; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa2a2a23_x1.vhd b/pdks/symbolic/sxlib/cells/noa2a2a23_x1.vhd new file mode 100644 index 000000000..13c08812d --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a23_x1.vhd @@ -0,0 +1,24 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a2a23_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a2a23_x1; + +ARCHITECTURE RTL OF noa2a2a23_x1 IS +BEGIN + nq <= NOT((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa2a2a23_x4.al b/pdks/symbolic/sxlib/cells/noa2a2a23_x4.al new file mode 100644 index 000000000..5bd111a20 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a23_x4.al @@ -0,0 +1,62 @@ +V ALLIANCE : 6 +H noa2a2a23_x4,L,30/10/99 +C i0,IN,EXTERNAL,15 +C i1,IN,EXTERNAL,16 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,10 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,11,4,14,0,0.75,0.75,7.3,7.3,17.7,9.75,tr_00018 +T P,0.35,5.9,5,16,14,0,0.75,0.75,13.3,13.3,10.5,11.25,tr_00017 +T P,0.35,5.9,13,11,14,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00016 +T P,0.35,5.9,14,11,13,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00015 +T P,0.35,5.9,14,15,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00014 +T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00013 +T P,0.35,5.9,6,9,5,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00012 +T P,0.35,5.9,4,8,6,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011 +T P,0.35,5.9,6,7,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T N,0.35,1.4,1,4,11,0,0.75,0.75,4.3,4.3,17.7,3,tr_00009 +T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00008 +T N,0.35,2.9,12,16,4,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00007 +T N,0.35,2.9,13,11,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00006 +T N,0.35,2.9,13,11,1,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00005 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,10,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 16,EXTERNAL,i1 +Q 0.00247612 +S 15,EXTERNAL,i0 +Q 0.00232574 +S 14,EXTERNAL,vdd +Q 0.00830269 +S 13,EXTERNAL,nq +Q 0.0023502 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0.0053368 +S 10,EXTERNAL,i3 +Q 0.00262649 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i5 +Q 0.0027653 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00199441 +S 5,INTERNAL +Q 0.00181815 +S 4,INTERNAL +Q 0.00716684 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00624627 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a2a23_x4.ap b/pdks/symbolic/sxlib/cells/noa2a2a23_x4.ap new file mode 100644 index 000000000..575cb6d8a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a23_x4.ap @@ -0,0 +1,156 @@ +V ALLIANCE : 6 +H noa2a2a23_x4,P, 8/ 6/2002,100 +A 0,0,6500,5000 +R 5000,4000,ref_ref,nq_40 +R 5000,1500,ref_ref,nq_15 +R 5000,3500,ref_ref,nq_35 +R 5000,3000,ref_ref,nq_30 +R 5000,2500,ref_ref,nq_25 +R 5000,2000,ref_ref,nq_20 +R 4000,1500,ref_ref,i0_15 +R 4000,3000,ref_ref,i0_30 +R 3500,3000,ref_ref,i1_30 +R 3500,2500,ref_ref,i1_25 +R 3500,1500,ref_ref,i1_15 +R 3500,2000,ref_ref,i1_20 +R 4000,2500,ref_ref,i0_25 +R 4000,2000,ref_ref,i0_20 +R 1500,3500,ref_ref,i4_35 +R 1500,3000,ref_ref,i4_30 +R 1500,2500,ref_ref,i4_25 +R 1500,2000,ref_ref,i4_20 +R 1500,1500,ref_ref,i4_15 +R 2000,2000,ref_ref,i3_20 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,1500,ref_ref,i3_15 +R 1000,1500,ref_ref,i5_15 +R 1000,3000,ref_ref,i5_30 +R 1000,2500,ref_ref,i5_25 +R 1000,2000,ref_ref,i5_20 +S 6200,4200,6200,4700,300,*,DOWN,NTIE +S 5000,1500,5000,4000,200,nq,DOWN,CALU1 +S 3500,1500,3500,3000,200,i1,DOWN,CALU1 +S 4000,1500,4000,3000,200,i0,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +S 2100,3500,3800,3500,100,*,RIGHT,ALU1 +S 6200,1000,6200,3500,100,*,DOWN,ALU1 +S 5500,2000,6200,2000,100,*,RIGHT,ALU1 +S 5700,1000,5700,1500,100,*,UP,ALU1 +S 500,1000,5700,1000,100,*,RIGHT,ALU1 +S 4700,2000,5300,2000,100,*,RIGHT,POLY +S 5900,1400,5900,2600,100,*,UP,POLY +S 5000,1450,5000,4050,200,*,DOWN,ALU1 +S 3250,2800,3250,4600,200,*,DOWN,PDIF +S 2700,2800,2700,4000,300,*,UP,PDIF +S 6200,2800,6200,3700,300,*,UP,PDIF +S 6200,800,6200,1200,300,*,DOWN,NDIF +S 5900,2600,5900,3900,100,*,UP,PTRANS +S 5900,600,5900,1400,100,*,DOWN,NTRANS +S 3500,2600,3500,4900,100,*,UP,PTRANS +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 5000,2800,5000,4700,300,*,UP,PDIF +S 5600,2800,5600,4700,300,*,UP,PDIF +S 4400,2800,4400,4700,300,*,UP,PDIF +S 3800,2800,3800,4700,300,*,UP,PDIF +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 4100,100,4100,1400,100,*,UP,NTRANS +S 3700,100,3700,1400,100,*,UP,NTRANS +S 3400,300,3400,1200,300,*,DOWN,NDIF +S 4400,300,4400,1200,300,*,DOWN,NDIF +S 5600,300,5600,1200,300,*,DOWN,NDIF +S 4700,100,4700,1400,100,*,UP,NTRANS +S 5300,100,5300,1400,100,*,DOWN,NTRANS +S 5300,1400,5300,2600,100,*,DOWN,POLY +S 4700,1400,4700,2600,100,*,DOWN,POLY +S 3500,1400,3700,1400,100,*,LEFT,POLY +S 4100,1400,4100,2600,100,*,DOWN,POLY +S 3500,1400,3500,2500,100,*,UP,POLY +S 5600,3500,5600,4600,200,*,DOWN,ALU1 +S 3800,3500,3800,4000,100,*,UP,ALU1 +S 4400,3500,4400,4600,200,*,DOWN,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 800,1400,900,1400,100,*,LEFT,POLY +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,100,800,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 900,1400,900,2600,100,*,DOWN,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 5000,300,5000,1500,300,*,DOWN,NDIF +S 5300,2000,5500,2000,300,*,LEFT,POLY +S 5700,1500,5900,1500,300,*,RIGHT,POLY +V 5700,1500,CONT_POLY,* +V 5500,2000,CONT_POLY,* +V 3200,4600,CONT_DIF_P,* +V 6200,4600,CONT_BODY_N,* +V 6200,3500,CONT_DIF_P,* +V 6200,3000,CONT_DIF_P,* +V 6200,1000,CONT_DIF_N,* +V 5000,3500,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 4400,4500,CONT_DIF_P,* +V 4400,3500,CONT_DIF_P,* +V 3800,4000,CONT_DIF_P,* +V 5600,3500,CONT_DIF_P,* +V 5600,4500,CONT_DIF_P,* +V 5600,4000,CONT_DIF_P,* +V 5000,3000,CONT_DIF_P,* +V 4400,500,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 5600,500,CONT_DIF_N,* +V 3500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 500,500,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 5000,1500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a2a23_x4.sym b/pdks/symbolic/sxlib/cells/noa2a2a23_x4.sym new file mode 100644 index 000000000..2fd94d259 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/noa2a2a23_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/noa2a2a23_x4.vbe b/pdks/symbolic/sxlib/cells/noa2a2a23_x4.vbe new file mode 100644 index 000000000..328209403 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY noa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT tphl_i5_nq : NATURAL := 496; + CONSTANT tphl_i4_nq : NATURAL := 574; + CONSTANT tphl_i2_nq : NATURAL := 620; + CONSTANT tphl_i3_nq : NATURAL := 716; + CONSTANT tplh_i1_nq : NATURAL := 778; + CONSTANT tplh_i0_nq : NATURAL := 814; + CONSTANT tplh_i4_nq : NATURAL := 819; + CONSTANT tplh_i3_nq : NATURAL := 833; + CONSTANT tphl_i0_nq : NATURAL := 834; + CONSTANT tplh_i5_nq : NATURAL := 865; + CONSTANT tplh_i2_nq : NATURAL := 873; + CONSTANT tphl_i1_nq : NATURAL := 955; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a23_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1600 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa2a2a23_x4.vhd b/pdks/symbolic/sxlib/cells/noa2a2a23_x4.vhd new file mode 100644 index 000000000..c7141298b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a23_x4.vhd @@ -0,0 +1,24 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a2a23_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a2a23_x4; + +ARCHITECTURE RTL OF noa2a2a23_x4 IS +BEGIN + nq <= NOT((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.al b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.al new file mode 100644 index 000000000..2221c84bb --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.al @@ -0,0 +1,66 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x1,L,30/10/99 +C i0,IN,EXTERNAL,18 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,16 +C i3,IN,EXTERNAL,15 +C i4,IN,EXTERNAL,10 +C i5,IN,EXTERNAL,9 +C i6,IN,EXTERNAL,8 +C i7,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,13,15,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00016 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.2,11.25,tr_00015 +T P,0.35,5.9,3,7,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00014 +T P,0.35,5.9,14,18,13,0,0.75,0.75,13.3,13.3,18,11.25,tr_00013 +T P,0.35,5.9,6,16,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00012 +T P,0.35,5.9,6,10,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00011 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,5,8,3,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,9,2.25,tr_00008 +T N,0.35,2.9,11,15,3,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00007 +T N,0.35,2.9,3,8,4,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,2,16,11,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005 +T N,0.35,2.9,2,18,12,0,0.75,0.75,7.3,7.3,18,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,12,17,3,0,0.75,0.75,7.3,7.3,16.2,2.25,tr_00002 +T N,0.35,2.9,4,7,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 18,EXTERNAL,i0 +Q 0.00260759 +S 17,EXTERNAL,i1 +Q 0.00260759 +S 16,EXTERNAL,i2 +Q 0.00232574 +S 15,EXTERNAL,i3 +Q 0.00232574 +S 14,EXTERNAL,vdd +Q 0.00670525 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i4 +Q 0.00232574 +S 9,EXTERNAL,i5 +Q 0.00232574 +S 8,EXTERNAL,i6 +Q 0.00269068 +S 7,EXTERNAL,i7 +Q 0.00260759 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,nq +Q 0.00490604 +S 2,EXTERNAL,vss +Q 0.00711654 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.ap b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.ap new file mode 100644 index 000000000..ef0a006b0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.ap @@ -0,0 +1,155 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x1,P, 8/ 6/2002,100 +A 0,0,7000,5000 +R 6000,3500,ref_ref,i0_35 +R 6000,3000,ref_ref,i0_30 +R 6000,2500,ref_ref,i0_25 +R 6000,2000,ref_ref,i0_20 +R 6000,1500,ref_ref,i0_15 +R 5500,3500,ref_ref,i1_35 +R 5500,3000,ref_ref,i1_30 +R 5500,2500,ref_ref,i1_25 +R 5500,2000,ref_ref,i1_20 +R 5500,1500,ref_ref,i1_15 +R 4000,3000,ref_ref,i2_30 +R 4000,2500,ref_ref,i2_25 +R 4000,2000,ref_ref,i2_20 +R 4000,1500,ref_ref,i2_15 +R 3500,3000,ref_ref,i3_30 +R 3500,2500,ref_ref,i3_25 +R 3500,2000,ref_ref,i3_20 +R 3500,1500,ref_ref,i3_15 +R 3000,3000,ref_ref,i4_30 +R 3000,2500,ref_ref,i4_25 +R 3000,2000,ref_ref,i4_20 +R 3000,1500,ref_ref,i4_15 +R 2500,3000,ref_ref,i5_30 +R 2500,2500,ref_ref,i5_25 +R 2500,2000,ref_ref,i5_20 +R 2500,1500,ref_ref,i5_15 +R 1500,3000,ref_ref,i6_30 +R 1500,2500,ref_ref,i6_25 +R 1500,2000,ref_ref,i6_20 +R 1500,1500,ref_ref,i6_15 +R 1000,3500,ref_ref,nq_35 +R 1000,3000,ref_ref,nq_30 +R 1000,2500,ref_ref,nq_25 +R 1000,2000,ref_ref,nq_20 +R 1000,1500,ref_ref,nq_15 +R 1000,1000,ref_ref,nq_10 +R 500,3000,ref_ref,i7_30 +R 500,2500,ref_ref,i7_25 +R 500,2000,ref_ref,i7_20 +R 500,1500,ref_ref,i7_15 +R 500,1000,ref_ref,i7_10 +S 6300,300,6300,1200,300,*,DOWN,NDIF +S 6300,2800,6300,4700,300,*,UP,PDIF +S 4000,2500,4200,2500,300,*,RIGHT,POLY +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 5400,100,5400,1400,100,*,UP,NTRANS +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 6000,100,6000,1400,100,*,UP,NTRANS +S 4200,100,4200,1400,100,*,UP,NTRANS +S 5700,300,5700,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 4500,300,4500,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 5100,300,5100,1200,300,*,DOWN,NDIF +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 6000,1400,6000,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 5400,1400,5400,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 6300,300,6300,1000,200,*,DOWN,ALU1 +S 0,3900,7000,3900,2400,*,RIGHT,NWELL +S 0,300,7000,300,600,vss,RIGHT,CALU1 +S 0,4700,7000,4700,600,vdd,RIGHT,CALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 4500,2800,4500,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 6000,2600,6000,4900,100,*,UP,PTRANS +S 5700,2800,5700,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,UP,PDIF +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 6300,4000,6300,4600,200,*,DOWN,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 6000,1500,6000,3500,100,*,UP,ALU1 +S 5500,1500,5500,3500,100,*,UP,ALU1 +S 5000,4000,5700,4000,100,*,LEFT,ALU1 +S 5000,3500,5000,4000,100,*,DOWN,ALU1 +S 3900,3500,5000,3500,100,*,LEFT,ALU1 +S 950,1000,5100,1000,200,*,LEFT,ALU1 +S 1000,950,1000,3550,200,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 6000,1500,6000,3500,200,i0,DOWN,CALU1 +S 5500,1500,5500,3500,200,i1,DOWN,CALU1 +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 1000,1000,1000,3500,200,nq,DOWN,CALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +V 3300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 6300,4000,CONT_DIF_P,* +V 6300,1000,CONT_DIF_N,* +V 500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 5500,2500,CONT_POLY,* +V 6000,2500,CONT_POLY,* +V 3300,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.sym b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.sym new file mode 100644 index 000000000..85b0df929 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.vbe b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.vbe new file mode 100644 index 000000000..ed253ca47 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rdown_i6_nq : NATURAL := 2850; + CONSTANT rdown_i7_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT rup_i4_nq : NATURAL := 6190; + CONSTANT rup_i5_nq : NATURAL := 6190; + CONSTANT rup_i6_nq : NATURAL := 6190; + CONSTANT rup_i7_nq : NATURAL := 6190; + CONSTANT tphl_i7_nq : NATURAL := 200; + CONSTANT tphl_i6_nq : NATURAL := 270; + CONSTANT tphl_i5_nq : NATURAL := 329; + CONSTANT tphl_i4_nq : NATURAL := 419; + CONSTANT tplh_i6_nq : NATURAL := 535; + CONSTANT tphl_i2_nq : NATURAL := 550; + CONSTANT tplh_i1_nq : NATURAL := 562; + CONSTANT tplh_i7_nq : NATURAL := 591; + CONSTANT tplh_i0_nq : NATURAL := 606; + CONSTANT tplh_i4_nq : NATURAL := 613; + CONSTANT tplh_i3_nq : NATURAL := 616; + CONSTANT tphl_i0_nq : NATURAL := 649; + CONSTANT tplh_i2_nq : NATURAL := 662; + CONSTANT tplh_i5_nq : NATURAL := 662; + CONSTANT tphl_i3_nq : NATURAL := 667; + CONSTANT tphl_i1_nq : NATURAL := 775; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x1" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.vhd b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.vhd new file mode 100644 index 000000000..dbac8f6e9 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x1.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a2a2a24_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + i7 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a2a2a24_x1; + +ARCHITECTURE RTL OF noa2a2a2a24_x1 IS +BEGIN + nq <= NOT(((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.al b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.al new file mode 100644 index 000000000..63a60e344 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.al @@ -0,0 +1,76 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x4,L,30/10/99 +C i0,IN,EXTERNAL,20 +C i1,IN,EXTERNAL,15 +C i2,IN,EXTERNAL,16 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C i6,IN,EXTERNAL,9 +C i7,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,19 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,18,2,14,0,0.75,0.75,7.3,7.3,23.7,9.75,tr_00022 +T P,0.35,5.9,13,15,14,0,0.75,0.75,13.3,13.3,16.5,11.25,tr_00021 +T P,0.35,5.9,14,18,19,0,0.75,0.75,13.3,13.3,21.9,11.25,tr_00020 +T P,0.35,5.9,19,18,14,0,0.75,0.75,13.3,13.3,20.1,11.25,tr_00019 +T P,0.35,5.9,14,20,13,0,0.75,0.75,13.3,13.3,18.3,11.25,tr_00018 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00017 +T P,0.35,5.9,5,8,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00016 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00015 +T P,0.35,5.9,6,16,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00014 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00013 +T P,0.35,5.9,13,17,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00012 +T N,0.35,1.4,3,2,18,0,0.75,0.75,4.3,4.3,23.7,3,tr_00011 +T N,0.35,2.9,3,20,12,0,0.75,0.75,7.3,7.3,18.3,2.25,tr_00010 +T N,0.35,2.9,19,18,3,0,0.75,0.75,7.3,7.3,21.9,2.25,tr_00009 +T N,0.35,2.9,12,15,2,0,0.75,0.75,7.3,7.3,17.1,2.25,tr_00008 +T N,0.35,2.9,19,18,3,0,0.75,0.75,7.3,7.3,20.1,2.25,tr_00007 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00006 +T N,0.35,2.9,2,9,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,2.9,11,17,2,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00004 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00003 +T N,0.35,2.9,3,16,11,0,0.75,0.75,7.3,7.3,12,2.25,tr_00002 +T N,0.35,2.9,4,8,3,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00001 +S 20,EXTERNAL,i0 +Q 0.00284261 +S 19,EXTERNAL,nq +Q 0.0023502 +S 18,INTERNAL +Q 0.00547561 +S 17,EXTERNAL,i3 +Q 0.00232574 +S 16,EXTERNAL,i2 +Q 0.00254552 +S 15,EXTERNAL,i1 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00984486 +S 13,INTERNAL +Q 0.00193089 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i7 +Q 0.00260759 +S 9,EXTERNAL,i6 +Q 0.00269068 +S 8,EXTERNAL,i5 +Q 0.00232574 +S 7,EXTERNAL,i4 +Q 0.00232574 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00778843 +S 2,INTERNAL +Q 0.00816047 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.ap b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.ap new file mode 100644 index 000000000..1a79a7907 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.ap @@ -0,0 +1,194 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x4,P, 8/ 6/2002,100 +A 0,0,8500,5000 +R 4000,3000,ref_ref,i2_30 +R 4000,2500,ref_ref,i2_25 +R 4000,2000,ref_ref,i2_20 +R 4000,1500,ref_ref,i2_15 +R 3500,3000,ref_ref,i3_30 +R 3500,2500,ref_ref,i3_25 +R 3500,2000,ref_ref,i3_20 +R 3500,1500,ref_ref,i3_15 +R 3000,3000,ref_ref,i4_30 +R 3000,2500,ref_ref,i4_25 +R 3000,2000,ref_ref,i4_20 +R 3000,1500,ref_ref,i4_15 +R 2500,3000,ref_ref,i5_30 +R 2500,2500,ref_ref,i5_25 +R 2500,2000,ref_ref,i5_20 +R 2500,1500,ref_ref,i5_15 +R 1500,3000,ref_ref,i6_30 +R 1500,2500,ref_ref,i6_25 +R 1500,2000,ref_ref,i6_20 +R 1500,1500,ref_ref,i6_15 +R 500,3000,ref_ref,i7_30 +R 500,2500,ref_ref,i7_25 +R 500,2000,ref_ref,i7_20 +R 500,1500,ref_ref,i7_15 +R 500,1000,ref_ref,i7_10 +R 7000,2500,ref_ref,nq_25 +R 7000,3000,ref_ref,nq_30 +R 7000,3500,ref_ref,nq_35 +R 7000,1500,ref_ref,nq_15 +R 7000,2000,ref_ref,nq_20 +R 7000,4000,ref_ref,nq_40 +R 6500,3000,ref_ref,i0_30 +R 6500,2500,ref_ref,i0_25 +R 6500,2000,ref_ref,i0_20 +R 6500,1500,ref_ref,i0_15 +R 5500,1500,ref_ref,i1_15 +R 5500,3000,ref_ref,i1_30 +R 5500,2500,ref_ref,i1_25 +R 5500,2000,ref_ref,i1_20 +R 6500,3500,ref_ref,i0_35 +S 8200,4200,8200,4700,300,*,DOWN,NTIE +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +S 7000,1500,7000,4000,200,nq,DOWN,CALU1 +S 5500,1500,5500,3000,200,i1,DOWN,CALU1 +S 6500,1500,6500,3500,200,i0,DOWN,CALU1 +S 6100,1400,6100,2600,100,*,DOWN,POLY +S 5500,1400,5500,2600,100,*,UP,POLY +S 5500,1400,5700,1400,100,*,LEFT,POLY +S 6700,2000,7500,2000,100,*,LEFT,POLY +S 6200,2000,6400,2000,200,*,RIGHT,ALU1 +S 7500,2000,8200,2000,100,*,RIGHT,ALU1 +S 3900,3500,5800,3500,100,*,RIGHT,ALU1 +S 7700,1000,7700,1500,100,*,UP,ALU1 +S 5400,1000,7700,1000,100,*,RIGHT,ALU1 +S 7900,1400,7900,2600,100,*,UP,POLY +S 7000,1450,7000,4050,200,*,DOWN,ALU1 +S 8200,1000,8200,3500,100,*,UP,ALU1 +S 8200,2800,8200,3700,300,*,UP,PDIF +S 8200,800,8200,1200,300,*,UP,NDIF +S 7900,2600,7900,3900,100,*,UP,PTRANS +S 7900,600,7900,1400,100,*,DOWN,NTRANS +S 1000,1000,5400,1000,100,*,RIGHT,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 6500,1500,6500,3500,100,*,UP,ALU1 +S 5200,2800,5200,4700,300,*,UP,PDIF +S 5500,2600,5500,4900,100,*,UP,PTRANS +S 7300,2600,7300,4900,100,*,UP,PTRANS +S 6400,2800,6400,4700,300,*,UP,PDIF +S 6700,2600,6700,4900,100,*,UP,PTRANS +S 7600,2800,7600,4700,300,*,UP,PDIF +S 7000,2800,7000,4700,300,*,UP,PDIF +S 5800,2800,5800,4700,300,*,UP,PDIF +S 6100,2600,6100,4900,100,*,UP,PTRANS +S 6100,100,6100,1400,100,*,UP,NTRANS +S 7600,300,7600,1200,300,*,DOWN,NDIF +S 6400,300,6400,1200,300,*,DOWN,NDIF +S 7300,100,7300,1400,100,*,DOWN,NTRANS +S 5400,300,5400,1200,300,*,DOWN,NDIF +S 5700,100,5700,1400,100,*,UP,NTRANS +S 6700,100,6700,1400,100,*,UP,NTRANS +S 6700,1400,6700,2600,100,*,DOWN,POLY +S 7300,1400,7300,2600,100,*,DOWN,POLY +S 5800,3500,5800,4000,100,*,UP,ALU1 +S 6400,4000,6400,4600,200,*,DOWN,ALU1 +S 5200,4000,5200,4600,200,*,DOWN,ALU1 +S 7600,3500,7600,4600,200,*,DOWN,ALU1 +S 4500,2800,4500,4700,300,*,UP,PDIF +S 0,4700,8500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,8500,3900,2400,*,RIGHT,NWELL +S 0,300,8500,300,600,vss,RIGHT,CALU1 +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 7000,300,7000,1500,300,*,DOWN,NDIF +S 7300,2000,7500,2000,300,*,LEFT,POLY +S 7700,1500,7900,1500,300,*,RIGHT,POLY +V 5500,2000,CONT_POLY,* +V 6200,2000,CONT_POLY,* +V 7500,2000,CONT_POLY,* +V 7700,1500,CONT_POLY,* +V 8200,1000,CONT_DIF_N,* +V 8200,3500,CONT_DIF_P,* +V 8200,2900,CONT_DIF_P,* +V 5200,4500,CONT_DIF_P,* +V 7000,3000,CONT_DIF_P,* +V 7600,4000,CONT_DIF_P,* +V 5800,4000,CONT_DIF_P,* +V 5200,4000,CONT_DIF_P,* +V 7600,4500,CONT_DIF_P,* +V 7600,3500,CONT_DIF_P,* +V 6400,4000,CONT_DIF_P,* +V 7000,4000,CONT_DIF_P,* +V 6400,4500,CONT_DIF_P,* +V 7000,3500,CONT_DIF_P,* +V 7600,500,CONT_DIF_N,* +V 6400,500,CONT_DIF_N,* +V 5400,1000,CONT_DIF_N,* +V 8200,4600,CONT_BODY_N,* +V 3300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 900,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 3300,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 4300,500,CONT_DIF_N,* +V 2300,500,CONT_DIF_N,* +V 7000,1500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.sym b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.sym new file mode 100644 index 000000000..7df574ee6 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.vbe b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.vbe new file mode 100644 index 000000000..2499cd710 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.vbe @@ -0,0 +1,69 @@ +ENTITY noa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4250; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rdown_i7_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT rup_i7_nq : NATURAL := 890; + CONSTANT tphl_i7_nq : NATURAL := 525; + CONSTANT tphl_i6_nq : NATURAL := 606; + CONSTANT tphl_i5_nq : NATURAL := 649; + CONSTANT tphl_i4_nq : NATURAL := 748; + CONSTANT tphl_i2_nq : NATURAL := 867; + CONSTANT tphl_i0_nq : NATURAL := 966; + CONSTANT tphl_i3_nq : NATURAL := 990; + CONSTANT tplh_i6_nq : NATURAL := 999; + CONSTANT tplh_i1_nq : NATURAL := 1005; + CONSTANT tplh_i0_nq : NATURAL := 1049; + CONSTANT tplh_i7_nq : NATURAL := 1052; + CONSTANT tplh_i3_nq : NATURAL := 1061; + CONSTANT tplh_i4_nq : NATURAL := 1061; + CONSTANT tphl_i1_nq : NATURAL := 1097; + CONSTANT tplh_i2_nq : NATURAL := 1106; + CONSTANT tplh_i5_nq : NATURAL := 1109; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2a2a2a24_x4" + SEVERITY WARNING; + nq <= not (((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and + i7))) after 1700 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.vhd b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.vhd new file mode 100644 index 000000000..e349c824e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2a2a2a24_x4.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2a2a2a24_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + i7 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2a2a2a24_x4; + +ARCHITECTURE RTL OF noa2a2a2a24_x4 IS +BEGIN + nq <= NOT(((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa2ao222_x1.al b/pdks/symbolic/sxlib/cells/noa2ao222_x1.al new file mode 100644 index 000000000..a39f8b03c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2ao222_x1.al @@ -0,0 +1,45 @@ +V ALLIANCE : 6 +H noa2ao222_x1,L,30/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00010 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00009 +T P,0.35,4.25,7,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00008 +T P,0.35,4.25,6,11,7,0,0.75,0.75,10,10,3.6,10.42,tr_00007 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00006 +T N,0.35,2.6,3,8,1,0,0.75,0.75,6.7,6.7,8.7,3.9,tr_00005 +T N,0.35,2.6,4,12,1,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00004 +T N,0.35,2.6,1,9,3,0,0.75,0.75,6.7,6.7,6.9,3.9,tr_00003 +T N,0.35,2.6,3,10,2,0,0.75,0.75,6.7,6.7,5.1,3.9,tr_00002 +T N,0.35,2.6,2,11,4,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00001 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL +Q 0.00212909 +S 8,EXTERNAL +Q 0.00226057 +S 7,EXTERNAL,vdd +Q 0.00366862 +S 6,INTERNAL +Q 0.00227626 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00114171 +S 2,EXTERNAL,nq +Q 0.0026146 +S 1,EXTERNAL,vss +Q 0.00419742 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2ao222_x1.ap b/pdks/symbolic/sxlib/cells/noa2ao222_x1.ap new file mode 100644 index 000000000..86a97a022 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2ao222_x1.ap @@ -0,0 +1,103 @@ +V ALLIANCE : 6 +H noa2ao222_x1,P,20/ 6/2002,100 +A 0,0,3500,5000 +R 3000,3500,ref_ref,i3_35 +R 3000,3000,ref_ref,i3_30 +R 3000,2500,ref_ref,i3_25 +R 3000,2000,ref_ref,i3_20 +R 3000,1500,ref_ref,i3_15 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 1500,1000,ref_ref,nq_10 +R 2000,1500,ref_ref,nq_15 +R 2000,2000,ref_ref,nq_20 +R 2000,2500,ref_ref,nq_25 +R 2000,3000,ref_ref,nq_30 +R 2000,3500,ref_ref,nq_35 +R 1500,2000,ref_ref,i4_20 +R 1500,2500,ref_ref,i4_25 +R 1500,3000,ref_ref,i4_30 +R 1500,3500,ref_ref,i4_35 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +S 2900,1900,2900,2600,100,*,UP,POLY +S 2400,1900,2400,2600,100,*,UP,POLY +S 1700,1900,1700,2600,100,*,UP,POLY +S 1100,1900,1100,2600,100,*,UP,POLY +S 600,1900,600,2600,100,*,UP,POLY +S 1500,2000,1700,2000,300,*,RIGHT,POLY +S 1500,1000,1500,1500,200,nq,DOWN,CALU1 +S 2000,1500,2000,3500,200,nq,DOWN,CALU1 +S 3000,1500,3000,3500,200,i3,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 1500,2000,1500,3500,200,i4,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 2000,1450,2000,3550,200,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 1500,2800,1500,4150,200,*,UP,PDIF +S 600,2600,600,4350,100,*,UP,PTRANS +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1450,1500,2050,1500,200,*,RIGHT,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 3000,1500,3000,3500,100,*,UP,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 2600,500,2600,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 300,500,300,1700,300,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1500,950,1500,1500,200,*,UP,ALU1 +S 1400,900,1400,1700,200,*,UP,NDIF +S 2900,700,2900,1900,100,*,UP,NTRANS +S 3200,900,3200,1700,300,*,UP,NDIF +S 600,700,600,1900,100,*,UP,NTRANS +S 2300,700,2300,1900,100,*,UP,NTRANS +S 1700,700,1700,1900,100,*,UP,NTRANS +S 2000,900,2000,1700,200,*,UP,NDIF +S 1100,700,1100,1900,100,*,UP,NTRANS +S 1200,400,2000,400,300,*,RIGHT,PTIE +V 2100,3500,CONT_DIF_P,* +V 2600,500,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 1400,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 2000,400,CONT_BODY_P,* +V 1600,400,CONT_BODY_P,* +V 1200,400,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2ao222_x1.vbe b/pdks/symbolic/sxlib/cells/noa2ao222_x1.vbe new file mode 100644 index 000000000..034393fea --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2ao222_x1.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3210; + CONSTANT rdown_i1_nq : NATURAL := 3210; + CONSTANT rdown_i2_nq : NATURAL := 3210; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 5260; + CONSTANT rup_i1_nq : NATURAL := 5260; + CONSTANT rup_i2_nq : NATURAL := 5260; + CONSTANT rup_i3_nq : NATURAL := 5260; + CONSTANT rup_i4_nq : NATURAL := 3750; + CONSTANT tphl_i2_nq : NATURAL := 186; + CONSTANT tphl_i4_nq : NATURAL := 240; + CONSTANT tphl_i3_nq : NATURAL := 256; + CONSTANT tplh_i4_nq : NATURAL := 309; + CONSTANT tphl_i0_nq : NATURAL := 348; + CONSTANT tplh_i1_nq : NATURAL := 378; + CONSTANT tplh_i0_nq : NATURAL := 422; + CONSTANT tphl_i1_nq : NATURAL := 440; + CONSTANT tplh_i3_nq : NATURAL := 459; + CONSTANT tplh_i2_nq : NATURAL := 473; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x1; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1100 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa2ao222_x1.vhd b/pdks/symbolic/sxlib/cells/noa2ao222_x1.vhd new file mode 100644 index 000000000..065e8073c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2ao222_x1.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2ao222_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2ao222_x1; + +ARCHITECTURE RTL OF noa2ao222_x1 IS +BEGIN + nq <= NOT(((i0 AND i1) OR ((i2 OR i3) AND i4))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa2ao222_x2.sym b/pdks/symbolic/sxlib/cells/noa2ao222_x2.sym new file mode 100644 index 000000000..0f226fcc5 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/noa2ao222_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/noa2ao222_x4.al b/pdks/symbolic/sxlib/cells/noa2ao222_x4.al new file mode 100644 index 000000000..3af0440ff --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2ao222_x4.al @@ -0,0 +1,55 @@ +V ALLIANCE : 6 +H noa2ao222_x4,L,30/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00016 +T P,0.35,5.9,5,9,1,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00015 +T P,0.35,4.25,7,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00014 +T P,0.35,4.25,6,11,7,0,0.75,0.75,10,10,3.6,10.42,tr_00013 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00012 +T P,0.35,5.9,14,13,7,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00011 +T P,0.35,2.9,7,1,13,0,0.75,0.75,7.3,7.3,12.3,9.75,tr_00010 +T P,0.35,5.9,7,13,14,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00009 +T N,0.35,1.7,3,10,1,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00008 +T N,0.35,2.6,4,12,2,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00007 +T N,0.35,2.6,1,11,4,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00006 +T N,0.35,1.7,3,8,2,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00005 +T N,0.35,1.7,2,9,3,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00004 +T N,0.35,1.4,13,1,2,0,0.75,0.75,4.3,4.3,12.3,4.5,tr_00003 +T N,0.35,2.9,14,13,2,0,0.75,0.75,7.3,7.3,15.9,3.75,tr_00002 +T N,0.35,2.9,2,13,14,0,0.75,0.75,7.3,7.3,14.1,3.75,tr_00001 +S 14,EXTERNAL,nq +Q 0.00276148 +S 13,INTERNAL +Q 0.00420824 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL +Q 0.00212909 +S 8,EXTERNAL +Q 0.00197871 +S 7,EXTERNAL,vdd +Q 0.00825499 +S 6,INTERNAL +Q 0.00227626 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00114171 +S 2,EXTERNAL,vss +Q 0.00913632 +S 1,INTERNAL +Q 0.00576981 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2ao222_x4.ap b/pdks/symbolic/sxlib/cells/noa2ao222_x4.ap new file mode 100644 index 000000000..7f92a464e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2ao222_x4.ap @@ -0,0 +1,159 @@ +V ALLIANCE : 6 +H noa2ao222_x4,P,20/ 6/2002,100 +A 0,0,6000,5000 +R 5000,4000,ref_ref,nq_40 +R 5000,2000,ref_ref,nq_20 +R 5000,2500,ref_ref,nq_25 +R 5000,3000,ref_ref,nq_30 +R 5000,1000,ref_ref,nq_10 +R 5000,3500,ref_ref,nq_35 +R 5000,1500,ref_ref,nq_15 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,3500,ref_ref,i4_35 +R 1500,3000,ref_ref,i4_30 +R 1500,2500,ref_ref,i4_25 +R 1500,2000,ref_ref,i4_20 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 3000,1500,ref_ref,i3_15 +R 3000,2000,ref_ref,i3_20 +R 3000,2500,ref_ref,i3_25 +R 3000,3000,ref_ref,i3_30 +S 2900,1900,2900,2600,100,*,UP,POLY +S 2400,1900,2400,2600,100,*,UP,POLY +S 1700,1900,1700,2600,100,*,UP,POLY +S 1100,1900,1100,2600,100,*,UP,POLY +S 600,1900,600,2600,100,*,UP,POLY +S 4100,2500,4300,2500,300,*,LEFT,POLY +S 1500,2000,1700,2000,300,*,RIGHT,POLY +S 2100,3500,4300,3500,100,*,LEFT,ALU1 +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 4100,2600,4100,3900,100,*,UP,PTRANS +S 3800,2800,3800,3700,300,*,UP,PDIF +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 5600,2800,5600,4700,300,*,DOWN,PDIF +S 3800,1300,3800,1700,300,*,UP,NDIF +S 4700,600,4700,1900,100,*,DOWN,NTRANS +S 5000,800,5000,1700,300,*,UP,NDIF +S 4400,800,4400,1700,300,*,UP,NDIF +S 5300,600,5300,1900,100,*,DOWN,NTRANS +S 5600,800,5600,1700,300,*,UP,NDIF +S 4100,1100,4100,1900,100,*,DOWN,NTRANS +S 4100,1900,4100,2600,100,*,DOWN,POLY +S 4500,2000,5300,2000,300,*,RIGHT,POLY +S 4700,1900,4700,2600,100,*,UP,POLY +S 5300,1900,5300,2600,100,*,UP,POLY +S 4400,300,4400,1500,200,*,DOWN,ALU1 +S 4400,4000,4400,4700,200,*,UP,ALU1 +S 5600,3000,5600,4700,200,*,UP,ALU1 +S 3800,1500,3800,3000,100,*,UP,ALU1 +S 3800,2000,4500,2000,100,*,LEFT,ALU1 +S 4300,2500,4300,3500,100,*,UP,ALU1 +S 5600,300,5600,1500,200,*,DOWN,ALU1 +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 2000,900,2000,1700,300,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 1400,900,1400,1700,300,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 300,500,300,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 2600,500,2600,1700,300,*,UP,NDIF +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 600,2600,600,4350,100,*,UP,PTRANS +S 1500,2800,1500,4150,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 2700,2800,2700,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 5000,1000,5000,4000,200,nq,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,2000,1500,3500,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 3000,1500,3000,3000,200,i3,DOWN,CALU1 +S 3100,300,5700,300,300,*,RIGHT,PTIE +S 3800,4200,3800,4700,300,*,DOWN,NTIE +V 5000,3000,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 3800,3000,CONT_DIF_P,* +V 3800,4600,CONT_BODY_N,* +V 5600,3000,CONT_DIF_P,* +V 5000,3500,CONT_DIF_P,* +V 4400,4500,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 5600,3500,CONT_DIF_P,* +V 5600,4000,CONT_DIF_P,* +V 5600,4500,CONT_DIF_P,* +V 5000,1500,CONT_DIF_N,* +V 4400,1000,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +V 5600,1500,CONT_DIF_N,* +V 3800,1500,CONT_DIF_N,* +V 4400,1500,CONT_DIF_N,* +V 5000,1000,CONT_DIF_N,* +V 3800,300,CONT_BODY_P,* +V 5600,300,CONT_BODY_P,* +V 4400,300,CONT_BODY_P,* +V 5000,300,CONT_BODY_P,* +V 4500,2000,CONT_POLY,* +V 4300,2500,CONT_POLY,* +V 1200,400,CONT_BODY_P,* +V 1600,400,CONT_BODY_P,* +V 2000,400,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3200,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 1400,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2600,500,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +V 3200,300,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa2ao222_x4.sym b/pdks/symbolic/sxlib/cells/noa2ao222_x4.sym new file mode 100644 index 000000000..7315791ae Binary files /dev/null and b/pdks/symbolic/sxlib/cells/noa2ao222_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/noa2ao222_x4.vbe b/pdks/symbolic/sxlib/cells/noa2ao222_x4.vbe new file mode 100644 index 000000000..89b9f12c5 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 638; + CONSTANT tplh_i4_nq : NATURAL := 664; + CONSTANT tphl_i0_nq : NATURAL := 684; + CONSTANT tphl_i4_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 732; + CONSTANT tplh_i1_nq : NATURAL := 758; + CONSTANT tphl_i1_nq : NATURAL := 780; + CONSTANT tplh_i3_nq : NATURAL := 795; + CONSTANT tplh_i0_nq : NATURAL := 801; + CONSTANT tplh_i2_nq : NATURAL := 809; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa2ao222_x4.vhd b/pdks/symbolic/sxlib/cells/noa2ao222_x4.vhd new file mode 100644 index 000000000..b2e57b155 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa2ao222_x4.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa2ao222_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa2ao222_x4; + +ARCHITECTURE RTL OF noa2ao222_x4 IS +BEGIN + nq <= NOT(((i0 AND i1) OR ((i2 OR i3) AND i4))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa3ao322_x1.al b/pdks/symbolic/sxlib/cells/noa3ao322_x1.al new file mode 100644 index 000000000..181eded8f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa3ao322_x1.al @@ -0,0 +1,59 @@ +V ALLIANCE : 6 +H noa3ao322_x1,L,30/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C i3,IN,EXTERNAL,11 +C i4,IN,EXTERNAL,15 +C i5,IN,EXTERNAL,16 +C i6,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,4 +T P,0.35,4.4,6,12,7,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00014 +T P,0.35,4.4,7,9,6,0,0.75,0.75,10.3,10.3,3.6,10.5,tr_00013 +T P,0.35,4.4,6,10,7,0,0.75,0.75,10.3,10.3,5.1,10.5,tr_00012 +T P,0.35,5.9,6,16,14,0,0.75,0.75,13.3,13.3,11.7,11.25,tr_00011 +T P,0.35,5.9,14,15,13,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00010 +T P,0.35,5.9,1,8,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00009 +T P,0.35,5.9,13,11,1,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00008 +T N,0.35,2.6,4,16,3,0,0.75,0.75,6.7,6.7,11.7,3.9,tr_00007 +T N,0.35,2.6,3,15,4,0,0.75,0.75,6.7,6.7,9.9,3.9,tr_00006 +T N,0.35,2.6,4,11,3,0,0.75,0.75,6.7,6.7,8.4,3.9,tr_00005 +T N,0.35,2.6,3,8,1,0,0.75,0.75,6.7,6.7,6.6,3.9,tr_00004 +T N,0.35,3.5,1,10,2,0,0.75,0.75,8.5,8.5,4.8,3.45,tr_00003 +T N,0.35,3.5,2,9,5,0,0.75,0.75,8.5,8.5,3.3,3.45,tr_00002 +T N,0.35,3.5,5,12,4,0,0.75,0.75,8.5,8.5,1.8,3.45,tr_00001 +S 16,EXTERNAL,i5 +Q 0.00226056 +S 15,EXTERNAL,i4 +Q 0.00241094 +S 14,INTERNAL +Q 0 +S 13,INTERNAL +Q 0 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i3 +Q 0.00199028 +S 10,EXTERNAL,i2 +Q 0.00241094 +S 9,EXTERNAL,i1 +Q 0.00269279 +S 8,EXTERNAL,i6 +Q 0.00212909 +S 7,EXTERNAL,vdd +Q 0.0052329 +S 6,INTERNAL +Q 0.00250174 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vss +Q 0.00558543 +S 3,INTERNAL +Q 0.00108534 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,nq +Q 0.0026146 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa3ao322_x1.ap b/pdks/symbolic/sxlib/cells/noa3ao322_x1.ap new file mode 100644 index 000000000..e4d59e767 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa3ao322_x1.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H noa3ao322_x1,P,18/ 5/2002,100 +A 0,0,4500,5000 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 1500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i2_20 +R 1500,2500,ref_ref,i2_25 +R 1500,3000,ref_ref,i2_30 +R 1500,3500,ref_ref,i2_35 +R 2000,1000,ref_ref,nq_10 +R 2000,2000,ref_ref,i6_20 +R 2000,2500,ref_ref,i6_25 +R 2000,3000,ref_ref,i6_30 +R 2000,3500,ref_ref,i6_35 +R 2500,1500,ref_ref,nq_15 +R 2500,2000,ref_ref,nq_20 +R 2500,2500,ref_ref,nq_25 +R 2500,3000,ref_ref,nq_30 +R 2500,3500,ref_ref,nq_35 +R 3000,1500,ref_ref,i3_15 +R 3000,2000,ref_ref,i3_20 +R 3000,2500,ref_ref,i3_25 +R 3000,3000,ref_ref,i3_30 +R 3500,1500,ref_ref,i4_15 +R 3500,2000,ref_ref,i4_20 +R 3500,2500,ref_ref,i4_25 +R 3500,3000,ref_ref,i4_30 +R 3500,3500,ref_ref,i4_35 +R 4000,1500,ref_ref,i5_15 +R 4000,2000,ref_ref,i5_20 +R 4000,2500,ref_ref,i5_25 +R 4000,3000,ref_ref,i5_30 +R 4000,3500,ref_ref,i5_35 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +S 3050,350,3050,1700,200,*,UP,NDIF +S 1450,2800,1450,4650,200,*,UP,PDIF +S 300,2800,300,4200,300,*,UP,PDIF +S 600,2600,600,4400,100,*,UP,PTRANS +S 900,2800,900,4200,300,*,UP,PDIF +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 1700,2600,1700,4400,100,*,UP,PTRANS +S 2000,2800,2000,4200,200,*,UP,PDIF +S 4200,300,4200,1000,200,*,DOWN,ALU1 +S 4200,900,4200,1700,300,*,UP,NDIF +S 4000,1500,4000,3500,100,*,DOWN,ALU1 +S 3300,1900,3400,1900,100,*,RIGHT,POLY +S 2500,1000,3600,1000,100,*,RIGHT,ALU1 +S 3900,700,3900,1900,100,*,UP,NTRANS +S 3600,900,3600,1700,300,*,UP,NDIF +S 3300,700,3300,1900,100,*,UP,NTRANS +S 2800,1900,2800,2400,100,i3,UP,POLY +S 2800,2400,2900,2400,100,*,RIGHT,POLY +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 3900,2600,3900,4900,100,*,UP,PTRANS +S 4200,2800,4200,4700,300,*,UP,PDIF +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 2600,2800,2600,4700,200,*,UP,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 3200,2800,3200,4700,200,*,UP,PDIF +S 300,500,300,1700,300,*,UP,NDIF +S 2800,700,2800,1900,100,*,UP,NTRANS +S 2200,700,2200,1900,100,*,UP,NTRANS +S 2500,900,2500,1700,200,*,UP,NDIF +S 1100,1900,1100,2600,100,i1,UP,POLY +S 1600,1900,1600,2600,100,i2,UP,POLY +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 3900,1900,3900,2600,100,i5,DOWN,POLY +S 2200,1900,2200,2600,100,i6,UP,POLY +S 600,1900,600,2600,100,i0,UP,POLY +S 3400,1900,3400,2600,100,i4,UP,POLY +S 1600,2600,1700,2600,100,*,RIGHT,POLY +S 2200,2600,2300,2600,100,*,RIGHT,POLY +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 300,4000,300,4700,200,*,UP,ALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 900,4000,4200,4000,100,*,RIGHT,ALU1 +S 3500,1500,3500,3500,100,*,UP,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 2000,950,2000,1500,200,*,UP,ALU1 +S 2500,1450,2500,3550,200,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 1950,1500,2550,1500,200,*,RIGHT,ALU1 +S 2000,2000,2000,3500,100,*,UP,ALU1 +S 450,4700,850,4700,300,*,RIGHT,NTIE +S 1600,400,1600,1900,100,*,UP,NTRANS +S 1100,400,1100,1900,100,*,UP,NTRANS +S 600,400,600,1900,100,*,UP,NTRANS +S 1900,600,1900,1700,200,*,UP,NDIF +S 3700,400,4100,400,300,*,RIGHT,PTIE +S 1000,1000,1000,3500,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i2,DOWN,CALU1 +S 2000,2000,2000,3500,200,i6,DOWN,CALU1 +S 3000,1500,3000,3000,200,i3,DOWN,CALU1 +S 3500,1500,3500,3500,200,i4,DOWN,CALU1 +S 4000,1500,4000,3500,200,i5,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 2500,1500,2500,3500,200,nq,DOWN,CALU1 +S 2000,1000,2000,1500,200,nq,DOWN,CALU1 +S 2000,2000,2200,2000,300,*,RIGHT,POLY +V 1450,4700,CONT_DIF_P,* +V 3050,400,CONT_DIF_N,* +V 4200,1000,CONT_DIF_N,* +V 4000,2000,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 3600,1000,CONT_DIF_N,* +V 3500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 850,4700,CONT_BODY_N,* +V 900,4000,CONT_DIF_P,* +V 4200,4000,CONT_DIF_P,* +V 2600,3500,CONT_DIF_P,* +V 2000,4000,CONT_DIF_P,* +V 2500,1000,CONT_DIF_N,* +V 1900,1000,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 450,4700,CONT_BODY_N,* +V 4100,400,CONT_BODY_P,* +V 3700,400,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa3ao322_x1.vbe b/pdks/symbolic/sxlib/cells/noa3ao322_x1.vbe new file mode 100644 index 000000000..ff0227769 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa3ao322_x1.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3370; + CONSTANT rdown_i1_nq : NATURAL := 3370; + CONSTANT rdown_i2_nq : NATURAL := 3370; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rdown_i5_nq : NATURAL := 3210; + CONSTANT rdown_i6_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 6700; + CONSTANT rup_i1_nq : NATURAL := 6700; + CONSTANT rup_i2_nq : NATURAL := 6700; + CONSTANT rup_i3_nq : NATURAL := 6700; + CONSTANT rup_i4_nq : NATURAL := 6700; + CONSTANT rup_i5_nq : NATURAL := 6700; + CONSTANT rup_i6_nq : NATURAL := 3690; + CONSTANT tphl_i3_nq : NATURAL := 196; + CONSTANT tphl_i6_nq : NATURAL := 246; + CONSTANT tphl_i4_nq : NATURAL := 264; + CONSTANT tplh_i6_nq : NATURAL := 311; + CONSTANT tphl_i5_nq : NATURAL := 328; + CONSTANT tphl_i0_nq : NATURAL := 396; + CONSTANT tphl_i1_nq : NATURAL := 486; + CONSTANT tplh_i2_nq : NATURAL := 488; + CONSTANT tphl_i2_nq : NATURAL := 546; + CONSTANT tplh_i1_nq : NATURAL := 552; + CONSTANT tplh_i5_nq : NATURAL := 581; + CONSTANT tplh_i3_nq : NATURAL := 599; + CONSTANT tplh_i4_nq : NATURAL := 608; + CONSTANT tplh_i0_nq : NATURAL := 616; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x1; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa3ao322_x1.vhd b/pdks/symbolic/sxlib/cells/noa3ao322_x1.vhd new file mode 100644 index 000000000..56c06273b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa3ao322_x1.vhd @@ -0,0 +1,25 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa3ao322_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa3ao322_x1; + +ARCHITECTURE RTL OF noa3ao322_x1 IS +BEGIN + nq <= NOT((((i0 AND i1) AND i2) OR (((i3 OR i4) OR i5) AND i6))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/noa3ao322_x4.al b/pdks/symbolic/sxlib/cells/noa3ao322_x4.al new file mode 100644 index 000000000..b2d65294e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa3ao322_x4.al @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H noa3ao322_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,18 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,14 +C i5,IN,EXTERNAL,15 +C i6,IN,EXTERNAL,16 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,4.4,11,17,6,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00020 +T P,0.35,5.9,5,4,3,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00019 +T P,0.35,3.5,6,16,12,0,0.75,0.75,8.5,8.5,12.6,10.95,tr_00018 +T P,0.35,3.2,12,18,5,0,0.75,0.75,7.9,7.9,10.8,11.1,tr_00017 +T P,0.35,5.9,3,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00016 +T P,0.35,3.2,12,7,5,0,0.75,0.75,7.9,7.9,7.2,11.1,tr_00015 +T P,0.35,4.4,13,14,11,0,0.75,0.75,10.3,10.3,16.2,10.5,tr_00014 +T P,0.35,4.4,12,15,13,0,0.75,0.75,10.3,10.3,17.7,10.5,tr_00013 +T P,0.35,3.2,5,8,12,0,0.75,0.75,7.9,7.9,9,11.1,tr_00012 +T P,0.35,3.5,5,6,4,0,0.75,0.75,8.5,8.5,1.8,10.05,tr_00011 +T N,0.35,1.7,9,16,6,0,0.75,0.75,4.9,4.9,12.3,3.45,tr_00010 +T N,0.35,2.3,10,8,2,0,0.75,0.75,6.1,6.1,9,3.75,tr_00009 +T N,0.35,1.1,9,14,1,0,0.75,0.75,3.7,3.7,15.9,3.15,tr_00008 +T N,0.35,2.3,6,18,10,0,0.75,0.75,6.1,6.1,10.5,3.75,tr_00007 +T N,0.35,2.3,2,7,1,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00006 +T N,0.35,1.1,1,17,9,0,0.75,0.75,3.7,3.7,14.1,3.15,tr_00005 +T N,0.35,1.1,1,15,9,0,0.75,0.75,3.7,3.7,17.7,3.15,tr_00004 +T N,0.35,2,4,6,1,0,0.75,0.75,5.5,5.5,1.8,3.3,tr_00003 +T N,0.35,2.9,3,4,1,0,0.75,0.75,7.3,7.3,5.4,2.85,tr_00002 +T N,0.35,2.9,1,4,3,0,0.75,0.75,7.3,7.3,3.6,2.85,tr_00001 +S 18,EXTERNAL,i2 +Q 0.00247612 +S 17,EXTERNAL,i3 +Q 0.00290834 +S 16,EXTERNAL,i6 +Q 0.00262649 +S 15,EXTERNAL,i5 +Q 0.00275797 +S 14,EXTERNAL,i4 +Q 0.00283894 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0.00261448 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.00114171 +S 8,EXTERNAL,i1 +Q 0.00275797 +S 7,EXTERNAL,i0 +Q 0.00290834 +S 6,INTERNAL +Q 0.00675598 +S 5,EXTERNAL,vdd +Q 0.00900775 +S 4,INTERNAL +Q 0.00543312 +S 3,EXTERNAL,nq +Q 0.00258522 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00847896 +EOF diff --git a/pdks/symbolic/sxlib/cells/noa3ao322_x4.ap b/pdks/symbolic/sxlib/cells/noa3ao322_x4.ap new file mode 100644 index 000000000..bc0115c1f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa3ao322_x4.ap @@ -0,0 +1,191 @@ +V ALLIANCE : 6 +H noa3ao322_x4,P, 8/ 6/2002,100 +A 0,0,6500,5000 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 1500,1000,ref_ref,nq_10 +R 1500,4000,ref_ref,nq_40 +R 2500,3500,ref_ref,i0_35 +R 5000,3500,ref_ref,i3_35 +R 6000,2500,ref_ref,i5_25 +R 6000,3000,ref_ref,i5_30 +R 6000,3500,ref_ref,i5_35 +R 2500,1500,ref_ref,i0_15 +R 2500,2000,ref_ref,i0_20 +R 2500,2500,ref_ref,i0_25 +R 2500,3000,ref_ref,i0_30 +R 5000,3000,ref_ref,i3_30 +R 5500,1500,ref_ref,i4_15 +R 5500,2000,ref_ref,i4_20 +R 5500,2500,ref_ref,i4_25 +R 5500,3000,ref_ref,i4_30 +R 5500,3500,ref_ref,i4_35 +R 6000,1500,ref_ref,i5_15 +R 6000,2000,ref_ref,i5_20 +R 5000,1500,ref_ref,i3_15 +R 5000,2000,ref_ref,i3_20 +R 5000,2500,ref_ref,i3_25 +R 3500,2500,ref_ref,i2_25 +R 3500,3000,ref_ref,i2_30 +R 3500,3500,ref_ref,i2_35 +R 4000,2000,ref_ref,i6_20 +R 4000,2500,ref_ref,i6_25 +R 4000,3000,ref_ref,i6_30 +R 4000,3500,ref_ref,i6_35 +R 3000,1500,ref_ref,i1_15 +R 3000,2000,ref_ref,i1_20 +R 3000,2500,ref_ref,i1_25 +R 3000,3000,ref_ref,i1_30 +R 3000,3500,ref_ref,i1_35 +R 1500,3500,ref_ref,nq_35 +R 3500,2000,ref_ref,i2_20 +S 300,4300,300,4800,300,*,DOWN,NTIE +S 4500,2800,4500,4200,300,*,DOWN,PDIF +S 4000,2000,4200,2000,300,*,RIGHT,POLY +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 600,2600,600,4100,100,*,UP,PTRANS +S 300,2800,300,3900,300,*,UP,PDIF +S 2100,2800,2100,4700,200,*,DOWN,PDIF +S 3000,3000,3000,4400,100,*,UP,PTRANS +S 3300,3200,3300,4500,300,*,DOWN,PDIF +S 3900,3100,3900,4200,200,*,UP,PDIF +S 5900,2600,5900,4400,100,*,UP,PTRANS +S 5400,2600,5400,4400,100,*,UP,PTRANS +S 2400,3000,2400,4400,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 6200,2800,6200,4200,300,*,UP,PDIF +S 3600,3000,3600,4400,100,*,UP,PTRANS +S 4200,2900,4200,4400,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2700,3200,2700,4200,300,*,UP,PDIF +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 5000,400,5000,1200,300,*,DOWN,NDIF +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 1500,500,1500,1400,300,*,UP,NDIF +S 2200,400,2200,1600,300,*,UP,NDIF +S 900,500,900,1400,300,*,DOWN,NDIF +S 600,600,600,1600,100,*,DOWN,NTRANS +S 300,800,300,1400,300,*,DOWN,NDIF +S 5900,700,5900,1400,100,*,UP,NTRANS +S 6200,900,6200,1200,300,*,UP,NDIF +S 4700,700,4700,1400,100,*,UP,NTRANS +S 2500,700,2500,1800,100,*,UP,NTRANS +S 3500,700,3500,1800,100,*,UP,NTRANS +S 5300,700,5300,1400,100,*,UP,NTRANS +S 3800,900,3800,1400,200,*,UP,NDIF +S 3000,700,3000,1800,100,*,UP,NTRANS +S 5600,900,5600,1200,300,*,UP,NDIF +S 4100,700,4100,1600,100,*,UP,NTRANS +S 4400,900,4400,1400,200,*,UP,NDIF +S 2800,400,4300,400,300,*,RIGHT,PTIE +S 5700,400,6100,400,300,*,RIGHT,PTIE +S 600,1600,600,2600,100,*,DOWN,POLY +S 1000,1600,1000,1700,100,*,DOWN,POLY +S 1000,1600,1800,1600,100,*,RIGHT,POLY +S 1000,2600,1800,2600,100,*,LEFT,POLY +S 1000,2500,1000,2600,100,*,DOWN,POLY +S 600,2100,2000,2100,100,*,LEFT,POLY +S 5300,1400,5300,1900,100,*,UP,POLY +S 4100,1600,4100,1900,100,*,UP,POLY +S 4700,1900,4900,1900,100,*,RIGHT,POLY +S 3600,1900,3600,3000,100,i2,UP,POLY +S 3500,1800,3500,2000,100,*,UP,POLY +S 4700,1400,4700,1900,100,*,UP,POLY +S 4100,1900,4200,1900,100,*,LEFT,POLY +S 2400,1900,2500,1900,100,*,RIGHT,POLY +S 3000,1900,3000,3000,100,*,DOWN,POLY +S 2500,1800,2500,2000,100,*,DOWN,POLY +S 5900,1900,5900,2600,100,i5,DOWN,POLY +S 5400,1900,5400,2600,100,i4,UP,POLY +S 2400,1900,2400,3000,100,*,DOWN,POLY +S 5300,1900,5400,1900,100,*,RIGHT,POLY +S 3000,1800,3000,2000,100,*,UP,POLY +S 5900,1400,5900,2000,100,*,UP,POLY +S 4200,1900,4200,2900,100,i6,UP,POLY +S 4900,1900,4900,2600,100,*,UP,POLY +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 6200,300,6200,1000,200,*,DOWN,ALU1 +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 300,2500,1000,2500,100,*,LEFT,ALU1 +S 300,1700,1000,1700,100,*,LEFT,ALU1 +S 300,1200,300,3500,100,*,DOWN,ALU1 +S 3500,2000,3500,3500,100,*,UP,ALU1 +S 900,3000,900,4500,200,*,UP,ALU1 +S 900,600,900,1200,200,*,DOWN,ALU1 +S 4400,1000,5600,1000,100,*,RIGHT,ALU1 +S 5000,1500,5000,3500,100,*,UP,ALU1 +S 4500,1500,4500,3500,100,*,DOWN,ALU1 +S 2000,1000,3800,1000,100,*,LEFT,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 2100,4000,2100,4700,200,*,UP,ALU1 +S 3800,1500,4500,1500,100,*,RIGHT,ALU1 +S 3800,1000,3800,1500,100,*,UP,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 3000,1500,3000,3500,100,*,DOWN,ALU1 +S 5500,1500,5500,3500,100,*,UP,ALU1 +S 4000,2000,4000,3500,100,*,UP,ALU1 +S 6000,1500,6000,3500,100,*,DOWN,ALU1 +S 2700,4000,6200,4000,100,*,RIGHT,ALU1 +S 2000,1000,2000,2000,100,*,UP,ALU1 +S 1500,1000,1500,4000,200,nq,DOWN,CALU1 +S 2500,1500,2500,3500,200,i0,DOWN,CALU1 +S 5000,1500,5000,3500,200,i3,DOWN,CALU1 +S 6000,1500,6000,3500,200,i5,DOWN,CALU1 +S 5500,1500,5500,3500,200,i4,DOWN,CALU1 +S 3500,2000,3500,3500,200,i2,DOWN,CALU1 +S 4000,2000,4000,3500,200,i6,DOWN,CALU1 +S 3000,1500,3000,3500,200,i1,DOWN,CALU1 +S 3800,4700,5800,4700,300,*,RIGHT,NTIE +V 300,4700,CONT_BODY_N,* +V 300,3000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 6200,4000,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,3000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 4500,4700,CONT_BODY_N,* +V 3900,4700,CONT_BODY_N,* +V 2100,4000,CONT_DIF_P,* +V 5700,4700,CONT_BODY_N,* +V 4500,3000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 3900,4000,CONT_DIF_P,* +V 5100,4700,CONT_BODY_N,* +V 1500,3500,CONT_DIF_P,* +V 2200,500,CONT_DIF_N,* +V 5000,500,CONT_DIF_N,* +V 300,1200,CONT_DIF_N,* +V 4400,1000,CONT_DIF_N,* +V 900,1200,CONT_DIF_N,* +V 900,700,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3800,1000,CONT_DIF_N,* +V 6200,1000,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +V 2800,400,CONT_BODY_P,* +V 4350,400,CONT_BODY_P,* +V 3300,400,CONT_BODY_P,* +V 3800,400,CONT_BODY_P,* +V 6100,400,CONT_BODY_P,* +V 5700,400,CONT_BODY_P,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 3500,2000,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 1000,1700,CONT_POLY,* +V 5000,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 5500,2500,CONT_POLY,* +V 6000,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/noa3ao322_x4.sym b/pdks/symbolic/sxlib/cells/noa3ao322_x4.sym new file mode 100644 index 000000000..25b1ee2e5 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/noa3ao322_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/noa3ao322_x4.vbe b/pdks/symbolic/sxlib/cells/noa3ao322_x4.vbe new file mode 100644 index 000000000..1fc4b8a6f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT tplh_i6_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 729; + CONSTANT tphl_i6_nq : NATURAL := 738; + CONSTANT tphl_i0_nq : NATURAL := 819; + CONSTANT tphl_i4_nq : NATURAL := 821; + CONSTANT tplh_i2_nq : NATURAL := 874; + CONSTANT tplh_i5_nq : NATURAL := 900; + CONSTANT tphl_i5_nq : NATURAL := 907; + CONSTANT tphl_i1_nq : NATURAL := 914; + CONSTANT tplh_i4_nq : NATURAL := 924; + CONSTANT tplh_i3_nq : NATURAL := 926; + CONSTANT tplh_i1_nq : NATURAL := 931; + CONSTANT tplh_i0_nq : NATURAL := 987; + CONSTANT tphl_i2_nq : NATURAL := 990; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1600 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/noa3ao322_x4.vhd b/pdks/symbolic/sxlib/cells/noa3ao322_x4.vhd new file mode 100644 index 000000000..610f1dffb --- /dev/null +++ b/pdks/symbolic/sxlib/cells/noa3ao322_x4.vhd @@ -0,0 +1,25 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY noa3ao322_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END noa3ao322_x4; + +ARCHITECTURE RTL OF noa3ao322_x4 IS +BEGIN + nq <= NOT((((i0 AND i1) AND i2) OR (((i3 OR i4) OR i5) AND i6))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nts_x1.al b/pdks/symbolic/sxlib/cells/nts_x1.al new file mode 100644 index 000000000..69a2f5ec2 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nts_x1.al @@ -0,0 +1,30 @@ +V ALLIANCE : 6 +H nts_x1,L,30/10/99 +C cmd,IN,EXTERNAL,7 +C i,IN,EXTERNAL,8 +C nq,TRISTATE,EXTERNAL,1 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00006 +T P,0.35,5.9,5,4,1,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00005 +T P,0.35,2.9,4,7,6,0,0.75,0.75,7.3,7.3,7.2,9.75,tr_00004 +T N,0.35,2.9,2,8,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00003 +T N,0.35,2.9,1,7,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,7.2,3,tr_00001 +S 8,EXTERNAL,i +Q 0.00317129 +S 7,EXTERNAL,cmd +Q 0.00472134 +S 6,EXTERNAL,vdd +Q 0.00497229 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00329099 +S 3,EXTERNAL,vss +Q 0.00420847 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,nq +Q 0.00258522 +EOF diff --git a/pdks/symbolic/sxlib/cells/nts_x1.ap b/pdks/symbolic/sxlib/cells/nts_x1.ap new file mode 100644 index 000000000..e7755e5cf --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nts_x1.ap @@ -0,0 +1,80 @@ +V ALLIANCE : 6 +H nts_x1,P,18/ 5/2002,100 +A 0,0,3000,5000 +R 1000,4000,ref_ref,cmd_40 +R 1000,3500,ref_ref,cmd_35 +R 1000,3000,ref_ref,cmd_30 +R 1000,2500,ref_ref,cmd_25 +R 500,4000,ref_ref,i_40 +R 1500,2500,ref_ref,nq_25 +R 500,2500,ref_ref,i_25 +R 500,2000,ref_ref,i_20 +R 500,1500,ref_ref,i_15 +R 500,1000,ref_ref,i_10 +R 1000,2000,ref_ref,cmd_20 +R 1000,1500,ref_ref,cmd_15 +R 1000,1000,ref_ref,cmd_10 +R 1500,1000,ref_ref,nq_10 +R 1500,4000,ref_ref,nq_40 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 500,3500,ref_ref,i_35 +R 500,3000,ref_ref,i_30 +S 2000,300,2800,300,300,*,RIGHT,PTIE +S 2000,4700,2800,4700,300,*,RIGHT,NTIE +S 2700,3000,2700,4700,200,*,UP,ALU1 +S 2700,300,2700,1000,200,*,DOWN,ALU1 +S 1000,2000,2400,2000,100,*,RIGHT,POLY +S 1200,1400,1200,2000,100,*,UP,POLY +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1500,1000,1500,4000,200,*,DOWN,ALU1 +S 600,1400,600,2600,100,*,UP,POLY +S 500,1000,500,4000,100,*,UP,ALU1 +S 2400,2600,2400,3900,100,*,DOWN,PTRANS +S 2100,2800,2100,3700,300,*,DOWN,PDIF +S 2700,2800,2700,3700,300,*,DOWN,PDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 600,2600,600,4900,100,*,DOWN,PTRANS +S 2400,600,2400,1400,100,*,UP,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 2700,800,2700,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2000,2500,2000,2600,100,*,DOWN,POLY +S 1200,2600,2000,2600,100,*,RIGHT,POLY +S 2100,1000,2100,3500,100,*,DOWN,ALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 1000,1000,1000,4000,200,cmd,DOWN,CALU1 +S 500,1000,500,4000,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,nq,DOWN,CALU1 +V 2100,4700,CONT_BODY_N,* +V 2100,300,CONT_BODY_P,* +V 2700,4700,CONT_BODY_N,* +V 2700,300,CONT_BODY_P,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 300,4500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 2000,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nts_x1.sym b/pdks/symbolic/sxlib/cells/nts_x1.sym new file mode 100644 index 000000000..f4ed35b46 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/nts_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/nts_x1.vbe b/pdks/symbolic/sxlib/cells/nts_x1.vbe new file mode 100644 index 000000000..f6cada4ad --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nts_x1.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_cmd : NATURAL := 14; + CONSTANT cin_i : NATURAL := 14; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i_nq : NATURAL := 3210; + CONSTANT tphl_cmd_nq : NATURAL := 41; + CONSTANT tphl_i_nq : NATURAL := 169; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 249; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x1; + +ARCHITECTURE behaviour_data_flow OF nts_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x1" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 800 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/sxlib/cells/nts_x1.vhd b/pdks/symbolic/sxlib/cells/nts_x1.vhd new file mode 100644 index 000000000..e1177332c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nts_x1.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nts_x1 IS +PORT( + cmd : IN STD_LOGIC; + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nts_x1; + +ARCHITECTURE RTL OF nts_x1 IS +BEGIN + PROCESS ( i, cmd ) + BEGIN + IF (cmd = '1') + THEN nq <= NOT(i); + ELSE nq <= 'Z'; + END IF; + END PROCESS; +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nts_x2.al b/pdks/symbolic/sxlib/cells/nts_x2.al new file mode 100644 index 000000000..c5f008586 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nts_x2.al @@ -0,0 +1,38 @@ +V ALLIANCE : 6 +H nts_x2,L,30/10/99 +C cmd,IN,EXTERNAL,9 +C i,IN,EXTERNAL,10 +C nq,TRISTATE,EXTERNAL,2 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,6,10,7,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00010 +T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009 +T P,0.35,5.9,2,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00008 +T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00007 +T P,0.35,2.9,6,9,8,0,0.75,0.75,7.3,7.3,10.2,9.75,tr_00006 +T N,0.35,2.9,2,9,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00004 +T N,0.35,2.9,4,10,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,3,10,4,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00002 +T N,0.35,1.4,8,9,4,0,0.75,0.75,4.3,4.3,10.2,3,tr_00001 +S 10,EXTERNAL,i +Q 0.00541538 +S 9,EXTERNAL,cmd +Q 0.00510823 +S 8,INTERNAL +Q 0.00545178 +S 7,INTERNAL +Q 0 +S 6,EXTERNAL,vdd +Q 0.00589026 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vss +Q 0.00495018 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,nq +Q 0.00258522 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/nts_x2.ap b/pdks/symbolic/sxlib/cells/nts_x2.ap new file mode 100644 index 000000000..d19c0eb83 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nts_x2.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H nts_x2,P, 8/ 6/2002,100 +A 0,0,4000,5000 +R 1000,4000,ref_ref,i_40 +R 1000,3500,ref_ref,i_35 +R 1000,3000,ref_ref,i_30 +R 1000,2500,ref_ref,i_25 +R 1000,2000,ref_ref,i_20 +R 1000,1500,ref_ref,i_15 +R 1000,1000,ref_ref,i_10 +R 1500,4000,ref_ref,nq_40 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 1500,1000,ref_ref,nq_10 +R 3000,2000,ref_ref,cmd_20 +R 3000,1500,ref_ref,cmd_15 +R 3000,1000,ref_ref,cmd_10 +R 3000,2500,ref_ref,cmd_25 +R 3000,3000,ref_ref,cmd_30 +R 3000,3500,ref_ref,cmd_35 +S 3700,4300,3700,4800,300,*,DOWN,NTIE +S 1000,1000,1000,4000,200,i,DOWN,CALU1 +S 1500,1000,1500,4000,200,nq,DOWN,CALU1 +S 3000,1000,3000,3500,200,cmd,DOWN,CALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1200,2600,2000,2600,100,*,RIGHT,POLY +S 1200,1400,2000,1400,100,*,RIGHT,POLY +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,100,2400,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,2600,600,4900,100,*,DOWN,PTRANS +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 1800,2600,1800,4900,100,*,DOWN,PTRANS +S 2400,2600,2400,4900,100,*,DOWN,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 600,1400,600,2600,100,*,UP,POLY +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 3400,2600,3400,3900,100,*,DOWN,PTRANS +S 3700,2800,3700,3700,300,*,DOWN,PDIF +S 300,3000,300,4500,200,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 3400,600,3400,1400,100,*,UP,NTRANS +S 3700,800,3700,1200,300,*,UP,NDIF +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2000,1500,3000,1500,100,*,RIGHT,ALU1 +S 3000,2000,3400,2000,300,*,RIGHT,POLY +S 2000,4000,3700,4000,100,*,RIGHT,ALU1 +S 3700,1000,3700,4000,100,*,DOWN,ALU1 +S 2000,2500,2000,4000,100,*,DOWN,ALU1 +S 3000,1000,3000,3500,100,*,UP,ALU1 +S 2900,300,2900,1200,700,*,DOWN,NDIF +S 2900,2800,2900,4700,700,*,UP,PDIF +S 1500,1000,1500,4000,200,*,DOWN,ALU1 +V 3700,3500,CONT_DIF_P,* +V 3700,1000,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2000,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 3700,4700,CONT_BODY_N,* +V 300,4500,CONT_DIF_P,* +V 2000,1500,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 2700,4500,CONT_DIF_P,* +V 2700,500,CONT_DIF_N,* +V 3100,4500,CONT_DIF_P,* +V 3100,500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nts_x2.sym b/pdks/symbolic/sxlib/cells/nts_x2.sym new file mode 100644 index 000000000..c821e1e9c Binary files /dev/null and b/pdks/symbolic/sxlib/cells/nts_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/nts_x2.vbe b/pdks/symbolic/sxlib/cells/nts_x2.vbe new file mode 100644 index 000000000..4bb47086f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nts_x2.vbe @@ -0,0 +1,37 @@ +ENTITY nts_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_cmd : NATURAL := 18; + CONSTANT cin_i : NATURAL := 28; + CONSTANT rdown_cmd_nq : NATURAL := 1430; + CONSTANT rdown_i_nq : NATURAL := 1430; + CONSTANT rup_cmd_nq : NATURAL := 1600; + CONSTANT rup_i_nq : NATURAL := 1600; + CONSTANT tphl_cmd_nq : NATURAL := 33; + CONSTANT tphl_i_nq : NATURAL := 167; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 330; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x2; + +ARCHITECTURE behaviour_data_flow OF nts_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nts_x2" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i) after 900 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/sxlib/cells/nts_x2.vhd b/pdks/symbolic/sxlib/cells/nts_x2.vhd new file mode 100644 index 000000000..b982932da --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nts_x2.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nts_x2 IS +PORT( + cmd : IN STD_LOGIC; + i : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nts_x2; + +ARCHITECTURE RTL OF nts_x2 IS +BEGIN + PROCESS ( i, cmd ) + BEGIN + IF (cmd = '1') + THEN nq <= NOT(i); + ELSE nq <= 'Z'; + END IF; + END PROCESS; +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nxr2_x1.al b/pdks/symbolic/sxlib/cells/nxr2_x1.al new file mode 100644 index 000000000..be155f9df --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nxr2_x1.al @@ -0,0 +1,40 @@ +V ALLIANCE : 6 +H nxr2_x1,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,7,9,6,0,0.75,0.75,13.3,13.3,9,11.25,tr_00012 +T P,0.35,5.9,6,5,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,6,8,7,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,2.9,7,8,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00008 +T P,0.35,2.9,9,10,7,0,0.75,0.75,7.3,7.3,10.8,11.25,tr_00007 +T N,0.35,2.9,4,8,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00005 +T N,0.35,2.9,2,5,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,2.9,3,10,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00003 +T N,0.35,1.4,4,10,9,0,0.75,0.75,4.3,4.3,10.8,3,tr_00002 +T N,0.35,1.4,5,8,4,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 10,EXTERNAL,i1 +Q 0.00533757 +S 9,INTERNAL +Q 0.00655161 +S 8,EXTERNAL,i0 +Q 0.00413388 +S 7,EXTERNAL,vdd +Q 0.0047041 +S 6,INTERNAL +Q 0.00217068 +S 5,INTERNAL +Q 0.0053513 +S 4,EXTERNAL,vss +Q 0.0047041 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,nq +Q 0.00299651 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/nxr2_x1.ap b/pdks/symbolic/sxlib/cells/nxr2_x1.ap new file mode 100644 index 000000000..bf9e07cca --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nxr2_x1.ap @@ -0,0 +1,111 @@ +V ALLIANCE : 6 +H nxr2_x1,P, 8/ 6/2002,100 +A 0,0,4500,5000 +R 1500,2500,ref_ref,nq_25 +R 1500,2000,ref_ref,nq_20 +R 1500,1500,ref_ref,nq_15 +R 1500,1000,ref_ref,nq_10 +R 1500,3500,ref_ref,nq_35 +R 1500,3000,ref_ref,nq_30 +R 1000,1000,ref_ref,i0_10 +R 1000,1500,ref_ref,i0_15 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 1000,4000,ref_ref,i0_40 +R 3500,1000,ref_ref,i1_10 +R 3500,1500,ref_ref,i1_15 +R 3500,2000,ref_ref,i1_20 +R 3500,2500,ref_ref,i1_25 +R 3500,3000,ref_ref,i1_30 +R 3500,3500,ref_ref,i1_35 +R 3500,4000,ref_ref,i1_40 +S 3800,300,4300,300,300,*,RIGHT,PTIE +S 3800,4700,4300,4700,300,*,RIGHT,NTIE +S 1500,1000,1500,3500,200,nq,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 3500,1000,3500,4000,200,i1,DOWN,CALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 1500,4000,2700,4000,100,*,RIGHT,ALU1 +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 600,2600,600,3100,100,*,DOWN,POLY +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 3600,3100,3600,4400,100,*,UP,PTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,2600,3600,3100,100,*,DOWN,POLY +S 3500,1000,3500,4000,100,*,DOWN,ALU1 +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 4000,1000,4000,3500,100,*,DOWN,ALU1 +S 4000,3300,4000,4200,300,*,DOWN,PDIF +S 4000,800,4000,1200,300,*,UP,NDIF +S 3000,2000,3000,2600,100,*,DOWN,POLY +S 2000,2500,3500,2500,100,*,RIGHT,ALU1 +S 3000,1400,3600,1400,100,*,RIGHT,POLY +S 2000,1500,2500,1500,100,*,RIGHT,ALU1 +S 2500,1500,2500,2000,100,*,DOWN,ALU1 +S 2500,2000,3000,2000,100,*,RIGHT,ALU1 +S 1450,3500,2100,3500,200,*,RIGHT,ALU1 +S 1500,950,1500,3550,200,*,UP,ALU1 +S 1450,1000,2100,1000,200,*,RIGHT,ALU1 +S 300,3500,300,4000,100,*,DOWN,ALU1 +S 4000,3500,4000,4000,100,*,UP,ALU1 +S 2700,3000,2700,4000,100,*,UP,ALU1 +V 300,2000,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 3900,300,CONT_BODY_P,* +V 3900,4700,CONT_BODY_N,* +V 3300,4500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 3300,500,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +V 2000,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 4000,3500,CONT_DIF_P,* +V 4000,1000,CONT_DIF_N,* +V 3000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nxr2_x1.sym b/pdks/symbolic/sxlib/cells/nxr2_x1.sym new file mode 100644 index 000000000..94e1c85df Binary files /dev/null and b/pdks/symbolic/sxlib/cells/nxr2_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/nxr2_x1.vbe b/pdks/symbolic/sxlib/cells/nxr2_x1.vbe new file mode 100644 index 000000000..1c89dd228 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nxr2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY nxr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i1_nq : NATURAL := 156; + CONSTANT tphl_i0_nq : NATURAL := 288; + CONSTANT tplh_i0_nq : NATURAL := 293; + CONSTANT tplh_i1_nq : NATURAL := 327; + CONSTANT tphh_i0_nq : NATURAL := 366; + CONSTANT tpll_i0_nq : NATURAL := 389; + CONSTANT tphh_i1_nq : NATURAL := 395; + CONSTANT tpll_i1_nq : NATURAL := 503; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x1; + +ARCHITECTURE behaviour_data_flow OF nxr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x1" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1100 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/nxr2_x1.vhd b/pdks/symbolic/sxlib/cells/nxr2_x1.vhd new file mode 100644 index 000000000..9ad239caa --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nxr2_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nxr2_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nxr2_x1; + +ARCHITECTURE RTL OF nxr2_x1 IS +BEGIN + nq <= NOT((i0 XOR i1)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/nxr2_x4.al b/pdks/symbolic/sxlib/cells/nxr2_x4.al new file mode 100644 index 000000000..eec8e7309 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nxr2_x4.al @@ -0,0 +1,46 @@ +V ALLIANCE : 6 +H nxr2_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,9,10,6,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00016 +T P,0.35,2.9,6,8,4,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00015 +T P,0.35,5.9,11,2,6,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00014 +T P,0.35,5.9,6,2,11,0,0.75,0.75,13.3,13.3,16.2,11.25,tr_00013 +T P,0.35,5.9,2,9,7,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00012 +T P,0.35,5.9,7,8,6,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00011 +T P,0.35,5.9,7,4,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,6,10,7,0,0.75,0.75,13.3,13.3,9,11.25,tr_00009 +T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,16.2,2.25,tr_00008 +T N,0.35,2.9,1,2,11,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00007 +T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006 +T N,0.35,1.4,1,10,9,0,0.75,0.75,4.3,4.3,10.8,3,tr_00005 +T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004 +T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,5,10,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00002 +T N,0.35,2.9,1,8,5,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00001 +S 11,EXTERNAL,nq +Q 0.00258522 +S 10,EXTERNAL,i1 +Q 0.00462772 +S 9,INTERNAL +Q 0.00536068 +S 8,EXTERNAL,i0 +Q 0.00370588 +S 7,INTERNAL +Q 0.00114171 +S 6,EXTERNAL,vdd +Q 0.00866628 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.0044986 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00780232 +S 1,EXTERNAL,vss +Q 0.00666861 +EOF diff --git a/pdks/symbolic/sxlib/cells/nxr2_x4.ap b/pdks/symbolic/sxlib/cells/nxr2_x4.ap new file mode 100644 index 000000000..c0b67af01 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nxr2_x4.ap @@ -0,0 +1,135 @@ +V ALLIANCE : 6 +H nxr2_x4,P, 8/ 6/2002,100 +A 0,0,6000,5000 +R 1000,1000,ref_ref,i0_10 +R 1000,1500,ref_ref,i0_15 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 1000,4000,ref_ref,i0_40 +R 3500,1500,ref_ref,i1_15 +R 3500,2000,ref_ref,i1_20 +R 3500,2500,ref_ref,i1_25 +R 3500,3000,ref_ref,i1_30 +R 3500,3500,ref_ref,i1_35 +R 3500,4000,ref_ref,i1_40 +R 5000,1500,ref_ref,nq_15 +R 5000,2000,ref_ref,nq_20 +R 5000,2500,ref_ref,nq_25 +R 5000,3500,ref_ref,nq_35 +R 5000,3000,ref_ref,nq_30 +R 5000,1000,ref_ref,nq_10 +R 5000,4000,ref_ref,nq_40 +S 300,4300,300,4800,300,*,DOWN,NTIE +S 3900,4300,3900,4800,300,*,DOWN,NTIE +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +S 0,3900,6000,3900,2400,*,LEFT,NWELL +S 1500,4000,2700,4000,100,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 1500,3500,2100,3500,100,*,RIGHT,ALU1 +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 2500,2000,3000,2000,100,*,RIGHT,ALU1 +S 5700,2800,5700,4700,300,*,DOWN,PDIF +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,UP,PDIF +S 600,2600,600,3900,100,*,UP,PTRANS +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 4500,3400,4500,4700,300,*,DOWN,PDIF +S 3900,2800,3900,3700,300,*,DOWN,PDIF +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 5400,100,5400,1400,100,*,DOWN,NTRANS +S 5100,300,5100,1200,300,*,UP,NDIF +S 5700,300,5700,1200,300,*,UP,NDIF +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 4000,1500,4000,2900,100,*,DOWN,ALU1 +S 3500,1500,3500,4000,100,*,DOWN,ALU1 +S 4500,3500,4500,4500,200,*,DOWN,ALU1 +S 5700,3000,5700,4500,200,*,DOWN,ALU1 +S 5700,500,5700,1000,200,*,DOWN,ALU1 +S 5400,1400,5400,2600,100,*,DOWN,POLY +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 4500,1000,4500,2000,100,*,DOWN,ALU1 +S 1500,1000,4500,1000,100,*,RIGHT,ALU1 +S 3900,800,3900,1600,300,*,UP,NDIF +S 4500,300,4500,1000,300,*,UP,NDIF +S 2000,2500,2500,2500,100,*,RIGHT,ALU1 +S 2500,2000,2500,2500,100,*,DOWN,ALU1 +S 2000,1500,3500,1500,100,*,RIGHT,ALU1 +S 3000,1400,3000,2000,100,*,DOWN,POLY +S 3000,2600,3600,2600,100,*,RIGHT,POLY +S 300,1000,300,3000,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 3500,1500,3500,4000,200,i1,DOWN,CALU1 +S 5000,1000,5000,4000,200,nq,DOWN,CALU1 +S 4500,2000,5400,2000,300,*,RIGHT,POLY +V 300,2000,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 3900,4700,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 3300,4500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 3300,500,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +V 2000,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 300,3000,CONT_DIF_P,* +V 4500,500,CONT_DIF_N,* +V 5700,500,CONT_DIF_N,* +V 5700,1000,CONT_DIF_N,* +V 5700,4500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 5700,3500,CONT_DIF_P,* +V 5700,3000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 5100,1000,CONT_DIF_N,* +V 4000,1500,CONT_DIF_N,* +V 4000,2900,CONT_DIF_P,* +V 4500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/nxr2_x4.sym b/pdks/symbolic/sxlib/cells/nxr2_x4.sym new file mode 100644 index 000000000..4e7a0cde4 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/nxr2_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/nxr2_x4.vbe b/pdks/symbolic/sxlib/cells/nxr2_x4.vbe new file mode 100644 index 000000000..aa5ea7108 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nxr2_x4.vbe @@ -0,0 +1,36 @@ +ENTITY nxr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tpll_i1_nq : NATURAL := 453; + CONSTANT tphh_i0_nq : NATURAL := 469; + CONSTANT tpll_i0_nq : NATURAL := 481; + CONSTANT tphl_i0_nq : NATURAL := 522; + CONSTANT tplh_i1_nq : NATURAL := 542; + CONSTANT tphl_i1_nq : NATURAL := 553; + CONSTANT tplh_i0_nq : NATURAL := 553; + CONSTANT tphh_i1_nq : NATURAL := 568; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x4; + +ARCHITECTURE behaviour_data_flow OF nxr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nxr2_x4" + SEVERITY WARNING; + nq <= not ((i0 xor i1)) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/nxr2_x4.vhd b/pdks/symbolic/sxlib/cells/nxr2_x4.vhd new file mode 100644 index 000000000..929c679a3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/nxr2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY nxr2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + nq : OUT STD_LOGIC +); +END nxr2_x4; + +ARCHITECTURE RTL OF nxr2_x4 IS +BEGIN + nq <= NOT((i0 XOR i1)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/o2_x2.al b/pdks/symbolic/sxlib/cells/o2_x2.al new file mode 100644 index 000000000..e01963606 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o2_x2.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H o2_x2,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,3,2,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00006 +T P,0.35,4.4,4,6,5,0,0.75,0.75,10.3,10.3,3.6,10.5,tr_00005 +T P,0.35,4.4,5,7,2,0,0.75,0.75,10.3,10.3,2.4,10.5,tr_00004 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,2,6,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002 +T N,0.35,2.9,3,2,1,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 7,EXTERNAL,i1 +Q 0.00282737 +S 6,EXTERNAL,i0 +Q 0.00344095 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00298567 +S 3,EXTERNAL,q +Q 0.00264397 +S 2,INTERNAL +Q 0.00463918 +S 1,EXTERNAL,vss +Q 0.0033382 +EOF diff --git a/pdks/symbolic/sxlib/cells/o2_x2.ap b/pdks/symbolic/sxlib/cells/o2_x2.ap new file mode 100644 index 000000000..edcbb5b52 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o2_x2.ap @@ -0,0 +1,71 @@ +V ALLIANCE : 6 +H o2_x2,P,18/ 5/2002,100 +A 0,0,2500,5000 +R 500,3000,ref_ref,i1_30 +R 500,3500,ref_ref,i1_35 +R 500,1500,ref_ref,i1_15 +R 500,2000,ref_ref,i1_20 +R 500,2500,ref_ref,i1_25 +R 1500,1000,ref_ref,i0_10 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 1500,4000,ref_ref,i0_40 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 2000,1500,ref_ref,q_15 +R 2000,2000,ref_ref,q_20 +R 2000,2500,ref_ref,q_25 +R 2000,3000,ref_ref,q_30 +R 2000,3500,ref_ref,q_35 +R 2000,4000,ref_ref,q_40 +R 2000,1000,ref_ref,q_10 +S 200,4700,1000,4700,300,*,RIGHT,NTIE +S 300,4000,950,4000,100,*,LEFT,ALU1 +S 950,1000,950,4000,100,*,UP,ALU1 +S 0,3900,2500,3900,2400,*,LEFT,NWELL +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 800,2600,800,4400,100,*,UP,PTRANS +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 300,2800,300,4200,300,*,DOWN,PDIF +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 600,2600,800,2600,100,*,RIGHT,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1000,2000,1800,2000,100,*,RIGHT,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2000,950,2000,4050,200,*,UP,ALU1 +S 500,1500,500,3500,200,i1,DOWN,CALU1 +S 1500,1000,1500,4000,200,i0,DOWN,CALU1 +S 2000,1000,2000,4000,200,q,DOWN,CALU1 +V 900,4700,CONT_BODY_N,* +V 300,4000,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 1500,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 1400,1500,CONT_POLY,* +V 1400,2500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 2100,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/o2_x2.sym b/pdks/symbolic/sxlib/cells/o2_x2.sym new file mode 100644 index 000000000..d70269b2d Binary files /dev/null and b/pdks/symbolic/sxlib/cells/o2_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/o2_x2.vbe b/pdks/symbolic/sxlib/cells/o2_x2.vbe new file mode 100644 index 000000000..9e115a06f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o2_x2.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tpll_i0_q : NATURAL := 310; + CONSTANT tphh_i1_q : NATURAL := 335; + CONSTANT tpll_i1_q : NATURAL := 364; + CONSTANT tphh_i0_q : NATURAL := 406; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x2; + +ARCHITECTURE behaviour_data_flow OF o2_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x2" + SEVERITY WARNING; + q <= (i0 or i1) after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/o2_x2.vhd b/pdks/symbolic/sxlib/cells/o2_x2.vhd new file mode 100644 index 000000000..6ff6bde5b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o2_x2.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o2_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o2_x2; + +ARCHITECTURE RTL OF o2_x2 IS +BEGIN + q <= (i0 OR i1); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/o2_x4.al b/pdks/symbolic/sxlib/cells/o2_x4.al new file mode 100644 index 000000000..396b7653f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o2_x4.al @@ -0,0 +1,30 @@ +V ALLIANCE : 6 +H o2_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,4,1,3,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,5.9,3,1,4,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00007 +T P,0.35,4.4,4,6,5,0,0.75,0.75,10.3,10.3,3.6,10.5,tr_00006 +T P,0.35,4.4,5,7,1,0,0.75,0.75,10.3,10.3,2.4,10.5,tr_00005 +T N,0.35,2.9,2,1,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002 +T N,0.35,2.9,3,1,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 7,EXTERNAL,i1 +Q 0.00282737 +S 6,EXTERNAL,i0 +Q 0.00344095 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00503104 +S 3,EXTERNAL,q +Q 0.00264397 +S 2,EXTERNAL,vss +Q 0.00444349 +S 1,INTERNAL +Q 0.00596944 +EOF diff --git a/pdks/symbolic/sxlib/cells/o2_x4.ap b/pdks/symbolic/sxlib/cells/o2_x4.ap new file mode 100644 index 000000000..b4120dd07 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o2_x4.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 6 +H o2_x4,P,18/ 5/2002,100 +A 0,0,3000,5000 +R 500,3000,ref_ref,i1_30 +R 500,3500,ref_ref,i1_35 +R 500,1500,ref_ref,i1_15 +R 500,2000,ref_ref,i1_20 +R 500,2500,ref_ref,i1_25 +R 1500,1000,ref_ref,i0_10 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 1500,4000,ref_ref,i0_40 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 2000,1500,ref_ref,q_15 +R 2000,2000,ref_ref,q_20 +R 2000,2500,ref_ref,q_25 +R 2000,3000,ref_ref,q_30 +R 2000,3500,ref_ref,q_35 +R 2000,4000,ref_ref,q_40 +R 2000,1000,ref_ref,q_10 +S 200,4700,1000,4700,300,*,RIGHT,NTIE +S 300,4000,950,4000,100,*,LEFT,ALU1 +S 950,1000,950,4000,100,*,UP,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 800,2600,800,4400,100,*,UP,PTRANS +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 300,2800,300,4200,300,*,DOWN,PDIF +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 600,2600,800,2600,100,*,RIGHT,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2400,100,2400,1400,100,*,UP,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1000,2000,2400,2000,100,*,RIGHT,POLY +S 2700,500,2700,1000,200,*,DOWN,ALU1 +S 2700,3000,2700,4500,200,*,UP,ALU1 +S 2000,950,2000,4050,200,*,UP,ALU1 +S 500,1500,500,3500,200,i1,DOWN,CALU1 +S 1500,1000,1500,4000,200,i0,DOWN,CALU1 +S 2000,1000,2000,4000,200,q,DOWN,CALU1 +V 900,4700,CONT_BODY_N,* +V 300,4000,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 1500,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 1400,1500,CONT_POLY,* +V 1400,2500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 2100,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2700,4500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 2700,1000,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/o2_x4.sym b/pdks/symbolic/sxlib/cells/o2_x4.sym new file mode 100644 index 000000000..fe8d315fb Binary files /dev/null and b/pdks/symbolic/sxlib/cells/o2_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/o2_x4.vbe b/pdks/symbolic/sxlib/cells/o2_x4.vbe new file mode 100644 index 000000000..e22a93618 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o2_x4.vbe @@ -0,0 +1,32 @@ +ENTITY o2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 394; + CONSTANT tphh_i1_q : NATURAL := 427; + CONSTANT tpll_i1_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 491; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x4; + +ARCHITECTURE behaviour_data_flow OF o2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o2_x4" + SEVERITY WARNING; + q <= (i0 or i1) after 1100 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/o2_x4.vhd b/pdks/symbolic/sxlib/cells/o2_x4.vhd new file mode 100644 index 000000000..c4dbf96e0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o2_x4; + +ARCHITECTURE RTL OF o2_x4 IS +BEGIN + q <= (i0 OR i1); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/o3_x2.al b/pdks/symbolic/sxlib/cells/o3_x2.al new file mode 100644 index 000000000..d476fb88e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o3_x2.al @@ -0,0 +1,35 @@ +V ALLIANCE : 6 +H o3_x2,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,4.4,6,7,3,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00007 +T P,0.35,4.4,5,9,6,0,0.75,0.75,10.3,10.3,3,10.5,tr_00006 +T P,0.35,4.4,4,8,5,0,0.75,0.75,10.3,10.3,4.2,10.5,tr_00005 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,1.4,2,9,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003 +T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,1.4,3,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 9,EXTERNAL,i1 +Q 0.00282737 +S 8,EXTERNAL,i0 +Q 0.00282737 +S 7,EXTERNAL,i2 +Q 0.00260759 +S 6,INTERNAL +Q 0 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00350341 +S 3,INTERNAL +Q 0.00620074 +S 2,EXTERNAL,vss +Q 0.00367968 +S 1,EXTERNAL,q +Q 0.00358405 +EOF diff --git a/pdks/symbolic/sxlib/cells/o3_x2.ap b/pdks/symbolic/sxlib/cells/o3_x2.ap new file mode 100644 index 000000000..c04d6db6c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o3_x2.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 6 +H o3_x2,P,18/ 5/2002,100 +A 0,0,3000,5000 +R 500,3000,ref_ref,i2_30 +R 500,3500,ref_ref,i2_35 +R 500,1500,ref_ref,i2_15 +R 500,2000,ref_ref,i2_20 +R 500,2500,ref_ref,i2_25 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 2500,4000,ref_ref,q_40 +R 2500,3500,ref_ref,q_35 +R 2500,3000,ref_ref,q_30 +R 2500,2500,ref_ref,q_25 +R 2500,2000,ref_ref,q_20 +R 2500,1500,ref_ref,q_15 +R 2500,1000,ref_ref,q_10 +S 200,4700,1200,4700,300,*,RIGHT,NTIE +S 2500,1000,2700,1000,200,*,LEFT,ALU1 +S 2500,3000,2700,3000,200,*,LEFT,ALU1 +S 2500,3500,2700,3500,200,*,LEFT,ALU1 +S 2500,4000,2700,4000,200,*,RIGHT,ALU1 +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 1800,2800,1800,4700,500,*,DOWN,PDIF +S 1600,1400,1600,2600,100,*,UP,POLY +S 1600,1400,1800,1400,100,*,LEFT,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1000,1400,1000,2600,100,*,DOWN,POLY +S 1400,2600,1400,4400,100,*,UP,PTRANS +S 1000,2600,1000,4400,100,*,UP,PTRANS +S 600,2600,600,4400,100,*,UP,PTRANS +S 300,4000,2000,4000,100,*,LEFT,ALU1 +S 300,2800,300,4200,300,*,DOWN,PDIF +S 2000,2000,2400,2000,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 300,1000,2000,1000,100,*,RIGHT,ALU1 +S 600,1400,600,2600,100,*,DOWN,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 900,400,900,1200,300,*,UP,NDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 0,3900,3000,3900,2400,*,LEFT,NWELL +S 500,1500,500,3500,200,i2,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +V 1100,4700,CONT_BODY_N,* +V 1700,4500,CONT_DIF_P,* +V 1500,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 2000,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,1500,CONT_POLY,* +V 2100,500,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 2100,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 2700,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 2700,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/o3_x2.sym b/pdks/symbolic/sxlib/cells/o3_x2.sym new file mode 100644 index 000000000..10ad4b429 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/o3_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/o3_x2.vbe b/pdks/symbolic/sxlib/cells/o3_x2.vbe new file mode 100644 index 000000000..5aad7aba9 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o3_x2.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 360; + CONSTANT tpll_i0_q : NATURAL := 407; + CONSTANT tphh_i1_q : NATURAL := 430; + CONSTANT tpll_i1_q : NATURAL := 482; + CONSTANT tphh_i0_q : NATURAL := 494; + CONSTANT tpll_i2_q : NATURAL := 506; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x2; + +ARCHITECTURE behaviour_data_flow OF o3_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x2" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1100 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/o3_x2.vhd b/pdks/symbolic/sxlib/cells/o3_x2.vhd new file mode 100644 index 000000000..020e53784 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o3_x2.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o3_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o3_x2; + +ARCHITECTURE RTL OF o3_x2 IS +BEGIN + q <= ((i0 OR i1) OR i2); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/o3_x4.al b/pdks/symbolic/sxlib/cells/o3_x4.al new file mode 100644 index 000000000..c0ae14bde --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o3_x4.al @@ -0,0 +1,37 @@ +V ALLIANCE : 6 +H o3_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,3,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00010 +T P,0.35,5.9,1,3,5,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00009 +T P,0.35,4.4,5,7,4,0,0.75,0.75,10.3,10.3,4.2,10.5,tr_00008 +T P,0.35,4.4,4,9,6,0,0.75,0.75,10.3,10.3,3,10.5,tr_00007 +T P,0.35,4.4,6,8,3,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00006 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00005 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,6.9,2.25,tr_00004 +T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,3,7,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,1.4,2,9,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001 +S 9,EXTERNAL,i1 +Q 0.00282737 +S 8,EXTERNAL,i2 +Q 0.00260759 +S 7,EXTERNAL,i0 +Q 0.00282737 +S 6,INTERNAL +Q 0 +S 5,EXTERNAL,vdd +Q 0.00537252 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00773401 +S 2,EXTERNAL,vss +Q 0.00519625 +S 1,EXTERNAL,q +Q 0.00258522 +EOF diff --git a/pdks/symbolic/sxlib/cells/o3_x4.ap b/pdks/symbolic/sxlib/cells/o3_x4.ap new file mode 100644 index 000000000..065737081 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o3_x4.ap @@ -0,0 +1,94 @@ +V ALLIANCE : 6 +H o3_x4,P,18/ 5/2002,100 +A 0,0,3500,5000 +R 2500,1000,ref_ref,q_10 +R 2500,1500,ref_ref,q_15 +R 2500,2000,ref_ref,q_20 +R 2500,2500,ref_ref,q_25 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,i0_35 +R 1500,3000,ref_ref,i0_30 +R 1500,2500,ref_ref,i0_25 +R 1500,2000,ref_ref,i0_20 +R 1500,1500,ref_ref,i0_15 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,2500,ref_ref,i2_25 +R 500,2000,ref_ref,i2_20 +R 500,1500,ref_ref,i2_15 +R 500,3500,ref_ref,i2_35 +R 500,3000,ref_ref,i2_30 +S 3200,500,3200,1000,200,*,UP,ALU1 +S 2500,1000,2500,4000,200,*,DOWN,ALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,400,900,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,UP,ALU1 +S 600,1400,600,2600,100,*,DOWN,POLY +S 300,1000,2000,1000,100,*,RIGHT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 300,2800,300,4200,300,*,DOWN,PDIF +S 300,4000,2000,4000,100,*,LEFT,ALU1 +S 600,2600,600,4400,100,*,UP,PTRANS +S 1000,2600,1000,4400,100,*,UP,PTRANS +S 1400,2600,1400,4400,100,*,UP,PTRANS +S 1000,1400,1000,2600,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1600,1400,1800,1400,100,*,LEFT,POLY +S 1600,1400,1600,2600,100,*,UP,POLY +S 1800,2800,1800,4700,500,*,DOWN,PDIF +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 2300,100,2300,1400,100,*,DOWN,NTRANS +S 2300,1400,2300,2600,100,*,DOWN,POLY +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 2600,300,2600,1200,300,*,DOWN,NDIF +S 2600,2800,2600,4700,300,*,UP,PDIF +S 2900,100,2900,1400,100,*,DOWN,NTRANS +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 3200,300,3200,1200,300,*,DOWN,NDIF +S 2900,2600,2900,4900,100,*,DOWN,PTRANS +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 1900,2000,2900,2000,300,*,RIGHT,POLY +S 3200,2800,3200,4700,300,*,UP,PDIF +S 3200,3000,3200,4500,200,*,UP,ALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 500,1500,500,3500,200,i2,DOWN,CALU1 +S 200,4700,1200,4700,300,*,RIGHT,NTIE +V 300,4700,CONT_BODY_N,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 500,1500,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,2500,CONT_POLY,* +V 2000,300,CONT_DIF_N,* +V 2000,4500,CONT_DIF_P,* +V 2600,1000,CONT_DIF_N,* +V 2600,3000,CONT_DIF_P,* +V 2600,3500,CONT_DIF_P,* +V 2600,4000,CONT_DIF_P,* +V 3200,500,CONT_DIF_N,* +V 3200,4500,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 3200,1000,CONT_DIF_N,* +V 1100,4700,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/o3_x4.sym b/pdks/symbolic/sxlib/cells/o3_x4.sym new file mode 100644 index 000000000..6453b5590 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/o3_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/o3_x4.vbe b/pdks/symbolic/sxlib/cells/o3_x4.vbe new file mode 100644 index 000000000..1e7ea94f8 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o3_x4.vbe @@ -0,0 +1,38 @@ +ENTITY o3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 447; + CONSTANT tpll_i0_q : NATURAL := 501; + CONSTANT tphh_i1_q : NATURAL := 510; + CONSTANT tphh_i0_q : NATURAL := 569; + CONSTANT tpll_i1_q : NATURAL := 585; + CONSTANT tpll_i2_q : NATURAL := 622; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x4; + +ARCHITECTURE behaviour_data_flow OF o3_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o3_x4" + SEVERITY WARNING; + q <= ((i0 or i1) or i2) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/o3_x4.vhd b/pdks/symbolic/sxlib/cells/o3_x4.vhd new file mode 100644 index 000000000..76e4c9ba0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o3_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o3_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o3_x4; + +ARCHITECTURE RTL OF o3_x4 IS +BEGIN + q <= ((i0 OR i1) OR i2); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/o4_x2.al b/pdks/symbolic/sxlib/cells/o4_x2.al new file mode 100644 index 000000000..7be3125b1 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o4_x2.al @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H o4_x2,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,1 +T P,0.35,4.4,3,10,2,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00010 +T P,0.35,4.4,6,8,3,0,0.75,0.75,10.3,10.3,3,10.5,tr_00009 +T P,0.35,4.4,5,7,6,0,0.75,0.75,10.3,10.3,4.2,10.5,tr_00008 +T P,0.35,4.4,4,9,5,0,0.75,0.75,10.3,10.3,5.4,10.5,tr_00007 +T P,0.35,5.9,4,2,11,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00006 +T N,0.35,1.4,2,9,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00005 +T N,0.35,1.4,1,10,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00003 +T N,0.35,1.4,2,8,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00002 +T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,8.7,2.25,tr_00001 +S 11,EXTERNAL,q +Q 0.00258522 +S 10,EXTERNAL,i3 +Q 0.00260759 +S 9,EXTERNAL,i2 +Q 0.00318597 +S 8,EXTERNAL,i1 +Q 0.00282737 +S 7,EXTERNAL,i0 +Q 0.00319753 +S 6,INTERNAL +Q 0 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00384489 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.0066641 +S 1,EXTERNAL,vss +Q 0.00419742 +EOF diff --git a/pdks/symbolic/sxlib/cells/o4_x2.ap b/pdks/symbolic/sxlib/cells/o4_x2.ap new file mode 100644 index 000000000..4c8656a48 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o4_x2.ap @@ -0,0 +1,105 @@ +V ALLIANCE : 6 +H o4_x2,P,18/ 5/2002,100 +A 0,0,3500,5000 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 3000,3000,ref_ref,q_30 +R 3000,2500,ref_ref,q_25 +R 3000,2000,ref_ref,q_20 +R 3000,1000,ref_ref,q_10 +R 3000,1500,ref_ref,q_15 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 500,2000,ref_ref,i3_20 +R 500,2500,ref_ref,i3_25 +R 500,3000,ref_ref,i3_30 +R 500,3500,ref_ref,i3_35 +R 500,1500,ref_ref,i3_15 +S 200,4700,1600,4700,300,*,RIGHT,NTIE +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 2000,1500,2000,3500,200,i2,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 500,1500,500,3500,200,i3,DOWN,CALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1500,400,1500,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 1400,2000,1400,2100,100,*,DOWN,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 600,1400,600,2600,100,*,DOWN,POLY +S 300,2800,300,4200,300,*,DOWN,PDIF +S 600,2600,600,4400,100,*,UP,PTRANS +S 1000,2600,1000,4400,100,*,UP,PTRANS +S 1400,2600,1400,4400,100,*,UP,PTRANS +S 2100,1400,2400,1400,100,*,RIGHT,POLY +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 2200,2800,2200,4700,500,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,DOWN,PTRANS +S 3200,2800,3200,4700,300,*,UP,PDIF +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 2400,2000,2900,2000,300,*,RIGHT,POLY +S 3200,300,3200,1200,300,*,DOWN,NDIF +S 2900,100,2900,1400,100,*,UP,NTRANS +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 1000,1400,1000,2600,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1400,1900,1400,2600,100,*,DOWN,POLY +S 1600,1400,1600,2100,100,*,DOWN,POLY +S 1600,1400,1800,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 2100,1400,2100,2600,100,*,DOWN,POLY +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 300,4000,2550,4000,100,*,RIGHT,ALU1 +S 900,1000,2550,1000,100,*,LEFT,ALU1 +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3000,4000,3200,4000,200,*,LEFT,ALU1 +S 3000,3500,3200,3500,200,*,LEFT,ALU1 +S 3000,3000,3200,3000,200,*,LEFT,ALU1 +S 3000,1000,3200,1000,200,*,LEFT,ALU1 +V 900,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 1500,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 300,4700,CONT_BODY_N,* +V 1500,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1500,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 3200,1000,CONT_DIF_N,* +V 3200,4000,CONT_DIF_P,* +V 3200,3000,CONT_DIF_P,* +V 3200,3500,CONT_DIF_P,* +V 2600,300,CONT_DIF_N,* +V 2600,4500,CONT_DIF_P,* +V 2200,4500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/o4_x2.sym b/pdks/symbolic/sxlib/cells/o4_x2.sym new file mode 100644 index 000000000..4e5ebc9a6 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/o4_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/o4_x2.vbe b/pdks/symbolic/sxlib/cells/o4_x2.vbe new file mode 100644 index 000000000..09652e62b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o4_x2.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i3_q : NATURAL := 378; + CONSTANT tphh_i1_q : NATURAL := 446; + CONSTANT tphh_i0_q : NATURAL := 508; + CONSTANT tpll_i2_q : NATURAL := 531; + CONSTANT tphh_i2_q : NATURAL := 567; + CONSTANT tpll_i0_q : NATURAL := 601; + CONSTANT tpll_i3_q : NATURAL := 626; + CONSTANT tpll_i1_q : NATURAL := 631; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x2; + +ARCHITECTURE behaviour_data_flow OF o4_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x2" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/o4_x2.vhd b/pdks/symbolic/sxlib/cells/o4_x2.vhd new file mode 100644 index 000000000..b7b15c9df --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o4_x2.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o4_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o4_x2; + +ARCHITECTURE RTL OF o4_x2 IS +BEGIN + q <= (((i0 OR i1) OR i2) OR i3); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/o4_x4.al b/pdks/symbolic/sxlib/cells/o4_x4.al new file mode 100644 index 000000000..9b33d0a12 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o4_x4.al @@ -0,0 +1,44 @@ +V ALLIANCE : 6 +H o4_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,10 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,5,7,6,0,0.75,0.75,13.3,13.3,6.6,11.25,tr_00012 +T P,0.35,5.9,3,8,4,0,0.75,0.75,13.3,13.3,4.2,11.25,tr_00011 +T P,0.35,5.9,4,10,1,0,0.75,0.75,13.3,13.3,3,11.25,tr_00010 +T P,0.35,5.9,6,9,3,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,5,1,11,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00008 +T P,0.35,5.9,11,1,5,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00007 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,7.2,3,tr_00006 +T N,0.35,1.4,2,10,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005 +T N,0.35,1.4,2,9,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004 +T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003 +T N,0.35,2.9,11,1,2,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00002 +T N,0.35,2.9,2,1,11,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00001 +S 11,EXTERNAL,q +Q 0.00343717 +S 10,EXTERNAL,i1 +Q 0.00317863 +S 9,EXTERNAL,i2 +Q 0.00332901 +S 8,EXTERNAL,i0 +Q 0.0032596 +S 7,EXTERNAL,i3 +Q 0.00282737 +S 6,INTERNAL +Q 0 +S 5,EXTERNAL,vdd +Q 0.00524395 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.00471516 +S 1,INTERNAL +Q 0.00811076 +EOF diff --git a/pdks/symbolic/sxlib/cells/o4_x4.ap b/pdks/symbolic/sxlib/cells/o4_x4.ap new file mode 100644 index 000000000..39105c8e5 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o4_x4.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H o4_x4,P, 8/ 6/2002,100 +A 0,0,4000,5000 +R 2500,2000,ref_ref,i3_20 +R 2500,2500,ref_ref,i3_25 +R 2500,3000,ref_ref,i3_30 +R 2500,3500,ref_ref,i3_35 +R 2500,4000,ref_ref,i3_40 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 1500,3500,ref_ref,i0_35 +R 1500,4000,ref_ref,i0_40 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 2000,4000,ref_ref,i2_40 +R 3500,2500,ref_ref,q_25 +R 3500,2000,ref_ref,q_20 +R 3500,1500,ref_ref,q_15 +R 3500,1000,ref_ref,q_10 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 3000,3000,ref_ref,q_30 +S 700,2800,700,4700,300,*,DOWN,PDIF +S 2550,300,2550,1200,200,*,UP,NDIF +S 2300,1400,2400,1400,100,*,RIGHT,POLY +S 1700,1400,1900,1400,100,*,RIGHT,POLY +S 2300,600,2300,1400,100,*,DOWN,NTRANS +S 2000,1000,2500,1000,200,*,RIGHT,ALU1 +S 1700,600,1700,1400,100,*,DOWN,NTRANS +S 1450,250,1450,1200,200,*,UP,NDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 500,1000,500,3000,100,*,DOWN,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 300,400,300,1200,300,*,UP,NDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2000,1500,2000,4000,100,*,UP,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,2400,1100,2400,100,*,LEFT,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 2800,2600,2800,4900,100,*,DOWN,PTRANS +S 3400,2600,3400,4900,100,*,DOWN,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3100,2800,3100,4700,300,*,UP,PDIF +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 2800,100,2800,1400,100,*,UP,NTRANS +S 3400,100,3400,1400,100,*,UP,NTRANS +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 3100,300,3100,1200,300,*,DOWN,NDIF +S 2500,1500,3000,1500,100,*,LEFT,ALU1 +S 2500,1000,2500,1500,100,*,DOWN,ALU1 +S 500,1000,2500,1000,100,*,LEFT,ALU1 +S 2500,2000,2500,4000,100,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 2800,2600,3400,2600,100,*,RIGHT,POLY +S 2800,1400,3400,1400,100,*,RIGHT,POLY +S 3000,1500,3000,2500,100,*,DOWN,ALU1 +S 3100,1000,3500,1000,200,*,RIGHT,ALU1 +S 500,3000,500,4000,100,*,UP,ALU1 +S 3500,1000,3500,3050,200,*,DOWN,ALU1 +S 3100,3000,3500,3000,200,*,LEFT,ALU1 +S 3700,3500,3700,4500,200,*,UP,ALU1 +S 500,1000,900,1000,200,*,LEFT,ALU1 +S 2500,2000,2500,4000,200,i3,DOWN,CALU1 +S 1000,1500,1000,4000,200,i1,DOWN,CALU1 +S 1500,1500,1500,4000,200,i0,DOWN,CALU1 +S 2000,1500,2000,4000,200,i2,DOWN,CALU1 +S 3000,3000,3000,4000,200,*,UP,ALU1 +S 3500,1000,3500,3000,200,q,DOWN,CALU1 +S 3000,3000,3000,4000,200,q,DOWN,CALU1 +V 2000,2000,CONT_POLY,* +V 2000,1000,CONT_DIF_N,* +V 1500,300,CONT_DIF_N,* +V 500,3000,CONT_DIF_P,* +V 2500,2000,CONT_POLY,* +V 900,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 1000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3700,4500,CONT_DIF_P,* +V 3700,500,CONT_DIF_N,* +V 3000,1500,CONT_POLY,* +V 2500,4500,CONT_DIF_P,* +V 2500,300,CONT_DIF_N,* +V 3000,2500,CONT_POLY,* +V 3100,1000,CONT_DIF_N,* +V 3100,3000,CONT_DIF_P,* +V 3100,3500,CONT_DIF_P,* +V 3100,4000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/o4_x4.sym b/pdks/symbolic/sxlib/cells/o4_x4.sym new file mode 100644 index 000000000..390104b35 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/o4_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/o4_x4.vbe b/pdks/symbolic/sxlib/cells/o4_x4.vbe new file mode 100644 index 000000000..bc869a8fb --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o4_x4.vbe @@ -0,0 +1,44 @@ +ENTITY o4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 492; + CONSTANT tpll_i3_q : NATURAL := 536; + CONSTANT tphh_i0_q : NATURAL := 574; + CONSTANT tpll_i2_q : NATURAL := 611; + CONSTANT tpll_i0_q : NATURAL := 638; + CONSTANT tphh_i2_q : NATURAL := 649; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 721; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x4; + +ARCHITECTURE behaviour_data_flow OF o4_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on o4_x4" + SEVERITY WARNING; + q <= (((i0 or i1) or i2) or i3) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/o4_x4.vhd b/pdks/symbolic/sxlib/cells/o4_x4.vhd new file mode 100644 index 000000000..240d21761 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/o4_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY o4_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END o4_x4; + +ARCHITECTURE RTL OF o4_x4 IS +BEGIN + q <= (((i0 OR i1) OR i2) OR i3); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa22_x2.al b/pdks/symbolic/sxlib/cells/oa22_x2.al new file mode 100644 index 000000000..fea0e23c0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa22_x2.al @@ -0,0 +1,35 @@ +V ALLIANCE : 6 +H oa22_x2,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,6 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,2.9,1,6,9,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,2.9,9,8,1,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T P,0.35,2.9,9,7,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00006 +T P,0.35,5.9,5,1,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00005 +T N,0.35,1.4,1,6,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00004 +T N,0.35,1.4,3,8,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00003 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,2.9,4,1,2,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00001 +S 9,INTERNAL +Q 0.00171257 +S 8,EXTERNAL,i0 +Q 0.00295461 +S 7,EXTERNAL,i2 +Q 0.00383259 +S 6,EXTERNAL,i1 +Q 0.00270208 +S 5,EXTERNAL,vdd +Q 0.00367968 +S 4,EXTERNAL,q +Q 0.00358405 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.00367968 +S 1,INTERNAL +Q 0.00439855 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa22_x2.ap b/pdks/symbolic/sxlib/cells/oa22_x2.ap new file mode 100644 index 000000000..0c43bb2b3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa22_x2.ap @@ -0,0 +1,98 @@ +V ALLIANCE : 6 +H oa22_x2,P,18/ 5/2002,100 +A 0,0,3000,5000 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1000,1000,ref_ref,i1_10 +R 2000,4000,ref_ref,i2_40 +R 2000,3500,ref_ref,i2_35 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 2000,1000,ref_ref,i2_10 +R 2500,1000,ref_ref,q_10 +R 2500,1500,ref_ref,q_15 +R 2500,2000,ref_ref,q_20 +R 2500,2500,ref_ref,q_25 +R 2500,3000,ref_ref,q_30 +R 2500,3500,ref_ref,q_35 +R 2500,4000,ref_ref,q_40 +S 800,300,1600,300,300,*,RIGHT,PTIE +S 200,4700,1600,4700,300,*,RIGHT,NTIE +S 300,3500,300,4000,100,*,UP,ALU1 +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 1500,2000,2400,2000,100,*,RIGHT,POLY +S 1000,3000,1200,3000,300,*,RIGHT,POLY +S 1000,1500,1200,1500,300,*,RIGHT,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1800,1500,2000,1500,300,*,RIGHT,POLY +S 1800,2500,2000,2500,300,*,RIGHT,POLY +S 2500,1000,2700,1000,200,*,RIGHT,ALU1 +S 2500,3000,2700,3000,200,*,LEFT,ALU1 +S 2500,3500,2700,3500,200,*,RIGHT,ALU1 +S 2500,4000,2700,4000,200,*,RIGHT,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 2100,2800,2100,4700,300,*,UP,PDIF +S 2400,2600,2400,4900,100,*,DOWN,PTRANS +S 2700,2800,2700,4700,300,*,UP,PDIF +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 1500,3300,1500,4200,300,*,UP,PDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 300,400,300,1200,300,*,DOWN,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 600,600,600,1400,100,*,UP,NTRANS +S 900,800,900,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 2400,1400,2400,2600,100,*,UP,POLY +S 600,1400,600,3100,100,*,UP,POLY +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 900,3500,1500,3500,100,*,RIGHT,ALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 1000,1000,1000,3000,100,*,UP,ALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +V 300,3500,CONT_DIF_P,* +V 1500,2000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 2100,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 900,4700,CONT_BODY_N,* +V 2100,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 900,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa22_x2.sym b/pdks/symbolic/sxlib/cells/oa22_x2.sym new file mode 100644 index 000000000..803280dea Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa22_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa22_x2.vbe b/pdks/symbolic/sxlib/cells/oa22_x2.vbe new file mode 100644 index 000000000..d2d267604 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa22_x2.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 1500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 390; + CONSTANT tphh_i2_q : NATURAL := 438; + CONSTANT tpll_i2_q : NATURAL := 454; + CONSTANT tphh_i1_q : NATURAL := 488; + CONSTANT tpll_i1_q : NATURAL := 525; + CONSTANT tpll_i0_q : NATURAL := 555; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x2; + +ARCHITECTURE behaviour_data_flow OF oa22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa22_x2.vhd b/pdks/symbolic/sxlib/cells/oa22_x2.vhd new file mode 100644 index 000000000..882c5eac9 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa22_x2.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa22_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa22_x2; + +ARCHITECTURE RTL OF oa22_x2 IS +BEGIN + q <= ((i0 AND i1) OR i2); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa22_x4.al b/pdks/symbolic/sxlib/cells/oa22_x4.al new file mode 100644 index 000000000..63de95c1e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa22_x4.al @@ -0,0 +1,37 @@ +V ALLIANCE : 6 +H oa22_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,2.9,9,7,5,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00010 +T P,0.35,2.9,9,6,3,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00009 +T P,0.35,2.9,3,8,9,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00008 +T P,0.35,5.9,5,3,4,0,0.75,0.75,13.3,13.3,8.1,11.25,tr_00007 +T P,0.35,5.9,4,3,5,0,0.75,0.75,13.3,13.3,9.9,11.25,tr_00006 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00005 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004 +T N,0.35,1.4,3,8,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00003 +T N,0.35,2.9,2,3,4,0,0.75,0.75,7.3,7.3,9.9,2.25,tr_00002 +T N,0.35,2.9,4,3,2,0,0.75,0.75,7.3,7.3,8.1,2.25,tr_00001 +S 9,INTERNAL +Q 0.00114171 +S 8,EXTERNAL,i1 +Q 0.00270208 +S 7,EXTERNAL,i2 +Q 0.00383259 +S 6,EXTERNAL,i0 +Q 0.00295461 +S 5,EXTERNAL,vdd +Q 0.00606652 +S 4,EXTERNAL,q +Q 0.00258522 +S 3,INTERNAL +Q 0.00611125 +S 2,EXTERNAL,vss +Q 0.00512644 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa22_x4.ap b/pdks/symbolic/sxlib/cells/oa22_x4.ap new file mode 100644 index 000000000..8830c307d --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa22_x4.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 6 +H oa22_x4,P,18/ 5/2002,100 +A 0,0,4000,5000 +R 3000,1000,ref_ref,q_10 +R 3000,1500,ref_ref,q_15 +R 3000,2000,ref_ref,q_20 +R 3000,2500,ref_ref,q_25 +R 3000,3000,ref_ref,q_30 +R 3000,3500,ref_ref,q_35 +R 3000,4000,ref_ref,q_40 +R 2000,1000,ref_ref,i2_10 +R 2000,1500,ref_ref,i2_15 +R 2000,2000,ref_ref,i2_20 +R 2000,2500,ref_ref,i2_25 +R 2000,3000,ref_ref,i2_30 +R 2000,3500,ref_ref,i2_35 +R 2000,4000,ref_ref,i2_40 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +S 800,300,1600,300,300,*,RIGHT,PTIE +S 200,4700,1600,4700,300,*,RIGHT,NTIE +S 1500,2000,3300,2000,200,*,RIGHT,POLY +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2300,2800,2300,4700,300,*,UP,PDIF +S 3300,2600,3300,4900,100,*,DOWN,PTRANS +S 3600,2800,3600,4700,300,*,UP,PDIF +S 3000,2800,3000,4700,300,*,UP,PDIF +S 2700,2600,2700,4900,100,*,DOWN,PTRANS +S 2700,100,2700,1400,100,*,UP,NTRANS +S 3000,300,3000,1200,300,*,DOWN,NDIF +S 3300,100,3300,1400,100,*,UP,NTRANS +S 3600,300,3600,1200,300,*,DOWN,NDIF +S 2700,1400,2700,2600,100,*,UP,POLY +S 3300,1400,3300,2600,100,*,DOWN,POLY +S 3000,1000,3000,4000,200,*,DOWN,ALU1 +S 3600,500,3600,1000,200,*,DOWN,ALU1 +S 3600,3000,3600,4500,200,*,UP,ALU1 +S 1000,1000,1000,3000,100,*,UP,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 900,3500,1500,3500,100,*,RIGHT,ALU1 +S 600,1400,600,3100,100,*,UP,POLY +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,UP,NTRANS +S 900,800,900,1200,300,*,DOWN,NDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1800,600,1800,1400,100,*,UP,NTRANS +S 300,400,300,1200,300,*,DOWN,NDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 900,3300,900,4200,300,*,UP,PDIF +S 1500,3300,1500,4200,300,*,UP,PDIF +S 300,3300,300,4200,300,*,UP,PDIF +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1800,3100,1800,4400,100,*,DOWN,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1800,2500,2000,2500,300,*,RIGHT,POLY +S 1800,1500,2000,1500,300,*,RIGHT,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1000,1500,1200,1500,300,*,RIGHT,POLY +S 1000,3000,1200,3000,300,*,RIGHT,POLY +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 2000,1000,2000,4000,200,i2,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +V 3600,3500,CONT_DIF_P,* +V 3600,3000,CONT_DIF_P,* +V 3000,4000,CONT_DIF_P,* +V 3000,3500,CONT_DIF_P,* +V 3000,3000,CONT_DIF_P,* +V 3600,4500,CONT_DIF_P,* +V 3600,4000,CONT_DIF_P,* +V 3000,1000,CONT_DIF_N,* +V 3600,1000,CONT_DIF_N,* +V 3600,500,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 1500,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 900,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 2000,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2300,4500,CONT_DIF_P,* +V 2300,500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa22_x4.sym b/pdks/symbolic/sxlib/cells/oa22_x4.sym new file mode 100644 index 000000000..50b52fb72 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa22_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa22_x4.vbe b/pdks/symbolic/sxlib/cells/oa22_x4.vbe new file mode 100644 index 000000000..fa425e333 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa22_x4.vbe @@ -0,0 +1,38 @@ +ENTITY oa22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 511; + CONSTANT tphh_i2_q : NATURAL := 523; + CONSTANT tpll_i2_q : NATURAL := 571; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tpll_i0_q : NATURAL := 677; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa22_x4; + +ARCHITECTURE behaviour_data_flow OF oa22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or i2) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa22_x4.vhd b/pdks/symbolic/sxlib/cells/oa22_x4.vhd new file mode 100644 index 000000000..3c61d8080 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa22_x4.vhd @@ -0,0 +1,21 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa22_x4; + +ARCHITECTURE RTL OF oa22_x4 IS +BEGIN + q <= ((i0 AND i1) OR i2); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa2a22_x2.al b/pdks/symbolic/sxlib/cells/oa2a22_x2.al new file mode 100644 index 000000000..e82135ab9 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a22_x2.al @@ -0,0 +1,42 @@ +V ALLIANCE : 6 +H oa2a22_x2,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,5 +C i2,IN,EXTERNAL,7 +C i3,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,9 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,11,5,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00010 +T P,0.35,2.9,11,8,10,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00009 +T P,0.35,2.9,10,7,11,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00008 +T P,0.35,2.9,3,6,11,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00007 +T P,0.35,5.9,9,3,10,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00006 +T N,0.35,1.4,2,5,3,0,0.75,0.75,4.3,4.3,3.6,3,tr_00005 +T N,0.35,1.4,1,6,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00004 +T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00003 +T N,0.35,1.4,3,7,4,0,0.75,0.75,4.3,4.3,5.4,3,tr_00002 +T N,0.35,2.9,1,3,9,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00001 +S 11,INTERNAL +Q 0.00199441 +S 10,EXTERNAL,vdd +Q 0.00564418 +S 9,EXTERNAL,q +Q 0.00258522 +S 8,EXTERNAL,i3 +Q 0.00295462 +S 7,EXTERNAL,i2 +Q 0.00323197 +S 6,EXTERNAL,i0 +Q 0.00295462 +S 5,EXTERNAL,i1 +Q 0.00323197 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00577862 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00564418 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a22_x2.ap b/pdks/symbolic/sxlib/cells/oa2a22_x2.ap new file mode 100644 index 000000000..50f6bcb80 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a22_x2.ap @@ -0,0 +1,111 @@ +V ALLIANCE : 6 +H oa2a22_x2,P,18/ 5/2002,100 +A 0,0,4500,5000 +R 2500,1000,ref_ref,i3_10 +R 2500,1500,ref_ref,i3_15 +R 2500,2000,ref_ref,i3_20 +R 2500,2500,ref_ref,i3_25 +R 2500,3000,ref_ref,i3_30 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 2000,1000,ref_ref,i2_10 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +R 4000,4000,ref_ref,q_40 +R 4000,3500,ref_ref,q_35 +R 4000,3000,ref_ref,q_30 +R 4000,2000,ref_ref,q_20 +R 4000,1000,ref_ref,q_10 +R 4000,1500,ref_ref,q_15 +R 4000,2500,ref_ref,q_25 +S 800,300,2200,300,300,*,RIGHT,PTIE +S 200,4700,1600,4700,300,*,RIGHT,NTIE +S 2500,1000,2500,3000,200,i3,DOWN,CALU1 +S 2000,1000,2000,3000,200,i2,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +S 2700,400,2700,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 600,1400,600,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2700,3300,2700,4200,300,*,DOWN,PDIF +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 2500,1000,2500,3000,100,*,DOWN,ALU1 +S 2000,1000,2000,3000,100,*,DOWN,ALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 3400,300,3400,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 900,3500,3500,3500,100,*,RIGHT,ALU1 +S 3500,2000,3500,3500,100,*,DOWN,ALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 3500,2000,3700,2000,300,*,RIGHT,POLY +V 4000,4000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 3500,2000,CONT_POLY,* +V 4000,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 3400,4500,CONT_DIF_P,* +V 3400,4000,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 900,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a22_x2.sym b/pdks/symbolic/sxlib/cells/oa2a22_x2.sym new file mode 100644 index 000000000..447371381 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa2a22_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa2a22_x2.vbe b/pdks/symbolic/sxlib/cells/oa2a22_x2.vbe new file mode 100644 index 000000000..1c5c40883 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a22_x2.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 403; + CONSTANT tpll_i2_q : NATURAL := 487; + CONSTANT tphh_i1_q : NATURAL := 495; + CONSTANT tpll_i3_q : NATURAL := 512; + CONSTANT tpll_i1_q : NATURAL := 534; + CONSTANT tphh_i3_q : NATURAL := 537; + CONSTANT tpll_i0_q : NATURAL := 564; + CONSTANT tphh_i2_q : NATURAL := 646; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa2a22_x2.vhd b/pdks/symbolic/sxlib/cells/oa2a22_x2.vhd new file mode 100644 index 000000000..fc749b4f0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a22_x2.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a22_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a22_x2; + +ARCHITECTURE RTL OF oa2a22_x2 IS +BEGIN + q <= ((i0 AND i1) OR (i2 AND i3)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa2a22_x4.al b/pdks/symbolic/sxlib/cells/oa2a22_x4.al new file mode 100644 index 000000000..1d11346de --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a22_x4.al @@ -0,0 +1,44 @@ +V ALLIANCE : 6 +H oa2a22_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,5 +C i2,IN,EXTERNAL,6 +C i3,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,9 +C vdd,IN,EXTERNAL,10 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,9,4,10,0,0.75,0.75,13.3,13.3,11.1,11.25,tr_00012 +T P,0.35,5.9,10,4,9,0,0.75,0.75,13.3,13.3,12.9,11.25,tr_00011 +T P,0.35,2.9,4,7,11,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00010 +T P,0.35,2.9,10,6,11,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00009 +T P,0.35,2.9,11,8,10,0,0.75,0.75,7.3,7.3,7.2,11.25,tr_00008 +T P,0.35,2.9,11,5,4,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00007 +T N,0.35,2.9,1,4,9,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00006 +T N,0.35,2.9,9,4,1,0,0.75,0.75,7.3,7.3,12.9,2.25,tr_00005 +T N,0.35,1.4,4,6,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004 +T N,0.35,1.4,3,8,1,0,0.75,0.75,4.3,4.3,7.2,3,tr_00003 +T N,0.35,1.4,1,7,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00002 +T N,0.35,1.4,2,5,4,0,0.75,0.75,4.3,4.3,3.6,3,tr_00001 +S 11,INTERNAL +Q 0.00199441 +S 10,EXTERNAL,vdd +Q 0.00768955 +S 9,EXTERNAL,q +Q 0.00258522 +S 8,EXTERNAL,i3 +Q 0.00295462 +S 7,EXTERNAL,i0 +Q 0.00295462 +S 6,EXTERNAL,i2 +Q 0.00323197 +S 5,EXTERNAL,i1 +Q 0.00323197 +S 4,INTERNAL +Q 0.00732866 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00674947 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a22_x4.ap b/pdks/symbolic/sxlib/cells/oa2a22_x4.ap new file mode 100644 index 000000000..1143c431c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a22_x4.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H oa2a22_x4,P,18/ 5/2002,100 +A 0,0,5000,5000 +R 2500,1000,ref_ref,i3_10 +R 2500,1500,ref_ref,i3_15 +R 2500,2000,ref_ref,i3_20 +R 2500,2500,ref_ref,i3_25 +R 2500,3000,ref_ref,i3_30 +R 2000,3000,ref_ref,i2_30 +R 2000,2500,ref_ref,i2_25 +R 2000,2000,ref_ref,i2_20 +R 2000,1500,ref_ref,i2_15 +R 2000,1000,ref_ref,i2_10 +R 1000,1000,ref_ref,i1_10 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +R 4000,4000,ref_ref,q_40 +R 4000,3500,ref_ref,q_35 +R 4000,3000,ref_ref,q_30 +R 4000,2000,ref_ref,q_20 +R 4000,1000,ref_ref,q_10 +R 4000,1500,ref_ref,q_15 +R 4000,2500,ref_ref,q_25 +S 800,300,2200,300,300,*,RIGHT,PTIE +S 200,4700,1600,4700,300,*,RIGHT,NTIE +S 2700,400,2700,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 600,1400,600,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2700,3300,2700,4200,300,*,DOWN,PDIF +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 2500,1000,2500,3000,100,*,DOWN,ALU1 +S 2000,1000,2000,3000,100,*,DOWN,ALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 3400,4000,3400,4500,200,*,DOWN,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 4600,500,4600,1000,200,*,DOWN,ALU1 +S 3400,500,3400,1000,200,*,DOWN,ALU1 +S 4600,3000,4600,4500,200,*,DOWN,ALU1 +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 3700,1400,3700,2600,100,*,DOWN,POLY +S 4300,100,4300,1400,100,*,DOWN,NTRANS +S 3400,300,3400,1200,300,*,UP,NDIF +S 4000,300,4000,1200,300,*,UP,NDIF +S 3700,100,3700,1400,100,*,DOWN,NTRANS +S 4600,300,4600,1200,300,*,UP,NDIF +S 3400,2800,3400,4700,300,*,DOWN,PDIF +S 4600,2800,4600,4700,300,*,DOWN,PDIF +S 4300,2600,4300,4900,100,*,UP,PTRANS +S 3700,2600,3700,4900,100,*,UP,PTRANS +S 4000,2800,4000,4700,300,*,DOWN,PDIF +S 900,3500,3500,3500,100,*,RIGHT,ALU1 +S 3500,2000,3500,3500,100,*,DOWN,ALU1 +S 3500,2000,4300,2000,100,*,RIGHT,POLY +S 2500,1000,2500,3000,200,i3,DOWN,CALU1 +S 2000,1000,2000,3000,200,i2,DOWN,CALU1 +S 1000,1000,1000,3000,200,i1,DOWN,CALU1 +S 500,1000,500,3000,200,i0,DOWN,CALU1 +S 4000,1000,4000,4000,200,q,DOWN,CALU1 +V 4000,4000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 1500,300,CONT_BODY_P,* +V 500,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 3500,2000,CONT_POLY,* +V 4000,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 3400,500,CONT_DIF_N,* +V 4600,500,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 3400,4500,CONT_DIF_P,* +V 3400,4000,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 4600,4000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 900,4700,CONT_BODY_N,* +V 900,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a22_x4.sym b/pdks/symbolic/sxlib/cells/oa2a22_x4.sym new file mode 100644 index 000000000..cc180c209 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa2a22_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa2a22_x4.vbe b/pdks/symbolic/sxlib/cells/oa2a22_x4.vbe new file mode 100644 index 000000000..a233499c0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a22_x4.vbe @@ -0,0 +1,44 @@ +ENTITY oa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 519; + CONSTANT tpll_i2_q : NATURAL := 596; + CONSTANT tpll_i3_q : NATURAL := 619; + CONSTANT tphh_i1_q : NATURAL := 624; + CONSTANT tphh_i3_q : NATURAL := 644; + CONSTANT tpll_i1_q : NATURAL := 669; + CONSTANT tpll_i0_q : NATURAL := 696; + CONSTANT tphh_i2_q : NATURAL := 763; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a22_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a22_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a22_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i2 and i3)) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa2a22_x4.vhd b/pdks/symbolic/sxlib/cells/oa2a22_x4.vhd new file mode 100644 index 000000000..9cf43446a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a22_x4.vhd @@ -0,0 +1,22 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a22_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a22_x4; + +ARCHITECTURE RTL OF oa2a22_x4 IS +BEGIN + q <= ((i0 AND i1) OR (i2 AND i3)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa2a2a23_x2.al b/pdks/symbolic/sxlib/cells/oa2a2a23_x2.al new file mode 100644 index 000000000..bcf6fd25d --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a23_x2.al @@ -0,0 +1,56 @@ +V ALLIANCE : 6 +H oa2a2a23_x2,L,30/10/99 +C i0,IN,EXTERNAL,15 +C i1,IN,EXTERNAL,14 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,5,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00014 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00013 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00012 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00011 +T P,0.35,5.9,6,14,13,0,0.75,0.75,13.3,13.3,12,11.25,tr_00010 +T P,0.35,5.9,13,15,6,0,0.75,0.75,13.3,13.3,13.8,11.25,tr_00009 +T P,0.35,5.9,12,2,13,0,0.75,0.75,13.3,13.3,15.6,11.25,tr_00008 +T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00007 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00005 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,11,14,2,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00003 +T N,0.35,2.9,1,15,11,0,0.75,0.75,7.3,7.3,13.8,2.25,tr_00002 +T N,0.35,2.9,12,2,1,0,0.75,0.75,7.3,7.3,15.6,2.25,tr_00001 +S 15,EXTERNAL,i0 +Q 0.00232574 +S 14,EXTERNAL,i1 +Q 0.00247612 +S 13,EXTERNAL,vdd +Q 0.0071974 +S 12,EXTERNAL,q +Q 0.00264397 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i5 +Q 0.00276531 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i3 +Q 0.00262649 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.0021 +S 5,INTERNAL +Q 0.00199441 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.0070541 +S 1,EXTERNAL,vss +Q 0.00572853 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a2a23_x2.ap b/pdks/symbolic/sxlib/cells/oa2a2a23_x2.ap new file mode 100644 index 000000000..e906a48d3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a23_x2.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H oa2a2a23_x2,P, 8/ 6/2002,100 +A 0,0,6000,5000 +R 4500,1500,ref_ref,i0_15 +R 4500,3000,ref_ref,i0_30 +R 4000,3000,ref_ref,i1_30 +R 4000,2500,ref_ref,i1_25 +R 4000,1500,ref_ref,i1_15 +R 4000,2000,ref_ref,i1_20 +R 4500,2500,ref_ref,i0_25 +R 4500,2000,ref_ref,i0_20 +R 5500,1000,ref_ref,q_10 +R 5500,1500,ref_ref,q_15 +R 5500,3500,ref_ref,q_35 +R 5500,3000,ref_ref,q_30 +R 5500,2500,ref_ref,q_25 +R 5500,2000,ref_ref,q_20 +R 1500,3500,ref_ref,i4_35 +R 1500,3000,ref_ref,i4_30 +R 1500,2500,ref_ref,i4_25 +R 1500,2000,ref_ref,i4_20 +R 1500,1500,ref_ref,i4_15 +R 2000,2000,ref_ref,i3_20 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,1500,ref_ref,i3_15 +R 1000,1500,ref_ref,i5_15 +R 1000,3000,ref_ref,i5_30 +R 1000,2500,ref_ref,i5_25 +R 1000,2000,ref_ref,i5_20 +R 5500,4000,ref_ref,q_40 +S 3700,4000,3700,4600,200,*,DOWN,ALU1 +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3200,300,3200,800,300,*,UP,PTIE +S 5000,2000,5200,2000,300,*,RIGHT,POLY +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 5200,1400,5200,2600,100,*,DOWN,POLY +S 5000,1000,5000,2000,100,*,UP,ALU1 +S 500,1000,5000,1000,100,*,RIGHT,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2100,3500,4300,3500,100,*,RIGHT,ALU1 +S 4000,1400,4200,1400,100,*,LEFT,POLY +S 4600,1400,4600,2600,100,*,DOWN,POLY +S 4000,1400,4000,2500,100,*,UP,POLY +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 5200,2600,5200,4900,100,*,UP,PTRANS +S 5500,2800,5500,4700,300,*,UP,PDIF +S 4900,2800,4900,4700,300,*,UP,PDIF +S 4300,2800,4300,4700,300,*,UP,PDIF +S 4600,2600,4600,4900,100,*,UP,PTRANS +S 4000,2600,4000,4900,100,*,UP,PTRANS +S 4900,300,4900,1200,300,*,DOWN,NDIF +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5200,100,5200,1400,100,*,UP,NTRANS +S 4600,100,4600,1400,100,*,UP,NTRANS +S 4200,100,4200,1400,100,*,UP,NTRANS +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 5500,950,5500,4050,200,*,DOWN,ALU1 +S 4300,3500,4300,4000,100,*,UP,ALU1 +S 4900,3500,4900,4600,200,*,DOWN,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 800,1400,900,1400,100,*,LEFT,POLY +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,100,800,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 900,1400,900,2600,100,*,DOWN,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 4500,1500,4500,3000,200,i0,DOWN,CALU1 +S 4000,1500,4000,3000,200,i1,DOWN,CALU1 +S 5500,1000,5500,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +V 3700,4000,CONT_DIF_P,* +V 3700,4500,CONT_DIF_P,* +V 5000,2000,CONT_POLY,* +V 3200,400,CONT_BODY_P,* +V 4000,2500,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 5500,3000,CONT_DIF_P,* +V 5500,3500,CONT_DIF_P,* +V 5500,4000,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 4900,4500,CONT_DIF_P,* +V 4900,3500,CONT_DIF_P,* +V 4300,4000,CONT_DIF_P,* +V 5500,1000,CONT_DIF_N,* +V 4900,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a2a23_x2.sym b/pdks/symbolic/sxlib/cells/oa2a2a23_x2.sym new file mode 100644 index 000000000..5bd6e7878 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa2a2a23_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa2a2a23_x2.vbe b/pdks/symbolic/sxlib/cells/oa2a2a23_x2.vbe new file mode 100644 index 000000000..189ed7159 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a23_x2.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT tphh_i5_q : NATURAL := 321; + CONSTANT tphh_i4_q : NATURAL := 402; + CONSTANT tphh_i2_q : NATURAL := 441; + CONSTANT tphh_i3_q : NATURAL := 540; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT tpll_i4_q : NATURAL := 591; + CONSTANT tpll_i3_q : NATURAL := 600; + CONSTANT tpll_i5_q : NATURAL := 636; + CONSTANT tpll_i2_q : NATURAL := 639; + CONSTANT tphh_i0_q : NATURAL := 653; + CONSTANT tphh_i1_q : NATURAL := 775; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x2" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa2a2a23_x2.vhd b/pdks/symbolic/sxlib/cells/oa2a2a23_x2.vhd new file mode 100644 index 000000000..fc4cca2e0 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a23_x2.vhd @@ -0,0 +1,24 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a2a23_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a2a23_x2; + +ARCHITECTURE RTL OF oa2a2a23_x2 IS +BEGIN + q <= (((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa2a2a23_x4.al b/pdks/symbolic/sxlib/cells/oa2a2a23_x4.al new file mode 100644 index 000000000..5b4789254 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a23_x4.al @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H oa2a2a23_x4,L,30/10/99 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,15 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,10 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,12,4,13,0,0.75,0.75,13.3,13.3,15.6,11.25,tr_00016 +T P,0.35,5.9,13,4,12,0,0.75,0.75,13.3,13.3,17.4,11.25,tr_00015 +T P,0.35,5.9,13,14,5,0,0.75,0.75,13.3,13.3,13.8,11.25,tr_00014 +T P,0.35,5.9,5,15,13,0,0.75,0.75,13.3,13.3,12,11.25,tr_00013 +T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00012 +T P,0.35,5.9,6,9,5,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,4,8,6,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00010 +T P,0.35,5.9,6,7,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009 +T N,0.35,2.9,12,4,1,0,0.75,0.75,7.3,7.3,15.6,2.25,tr_00008 +T N,0.35,2.9,12,4,1,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00007 +T N,0.35,2.9,1,14,11,0,0.75,0.75,7.3,7.3,13.8,2.25,tr_00006 +T N,0.35,2.9,11,15,4,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,10,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 15,EXTERNAL,i1 +Q 0.00247612 +S 14,EXTERNAL,i0 +Q 0.00232574 +S 13,EXTERNAL,vdd +Q 0.00883149 +S 12,EXTERNAL,q +Q 0.00264397 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i3 +Q 0.00262649 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i5 +Q 0.0027653 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00199441 +S 5,INTERNAL +Q 0.0021 +S 4,INTERNAL +Q 0.00860414 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00695133 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a2a23_x4.ap b/pdks/symbolic/sxlib/cells/oa2a2a23_x4.ap new file mode 100644 index 000000000..615fe9612 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a23_x4.ap @@ -0,0 +1,148 @@ +V ALLIANCE : 6 +H oa2a2a23_x4,P, 8/ 6/2002,100 +A 0,0,6500,5000 +R 4500,1500,ref_ref,i0_15 +R 4500,3000,ref_ref,i0_30 +R 4000,3000,ref_ref,i1_30 +R 4000,2500,ref_ref,i1_25 +R 4000,1500,ref_ref,i1_15 +R 4000,2000,ref_ref,i1_20 +R 4500,2500,ref_ref,i0_25 +R 4500,2000,ref_ref,i0_20 +R 5500,1000,ref_ref,q_10 +R 5500,1500,ref_ref,q_15 +R 5500,3500,ref_ref,q_35 +R 5500,3000,ref_ref,q_30 +R 5500,2500,ref_ref,q_25 +R 5500,2000,ref_ref,q_20 +R 1500,3500,ref_ref,i4_35 +R 1500,3000,ref_ref,i4_30 +R 1500,2500,ref_ref,i4_25 +R 1500,2000,ref_ref,i4_20 +R 1500,1500,ref_ref,i4_15 +R 2000,2000,ref_ref,i3_20 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 2000,3000,ref_ref,i3_30 +R 2000,2500,ref_ref,i3_25 +R 2000,1500,ref_ref,i3_15 +R 1000,1500,ref_ref,i5_15 +R 1000,3000,ref_ref,i5_30 +R 1000,2500,ref_ref,i5_25 +R 1000,2000,ref_ref,i5_20 +R 5500,4000,ref_ref,q_40 +S 3200,300,3200,800,300,*,UP,PTIE +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3700,4000,3700,4600,200,*,UP,ALU1 +S 4000,1500,4000,3000,200,i1,DOWN,CALU1 +S 4500,1500,4500,3000,200,i0,DOWN,CALU1 +S 1500,1500,1500,3500,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 2000,1500,2000,3000,200,i3,DOWN,CALU1 +S 1000,1500,1000,3000,200,i5,DOWN,CALU1 +S 5500,1000,5500,4000,200,q,DOWN,CALU1 +S 5000,2000,5800,2000,100,*,RIGHT,POLY +S 5800,1400,5800,2600,100,*,DOWN,POLY +S 5200,1400,5200,2600,100,*,DOWN,POLY +S 5000,1000,5000,2000,100,*,UP,ALU1 +S 500,1000,5000,1000,100,*,RIGHT,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2100,3500,4300,3500,100,*,RIGHT,ALU1 +S 4000,1400,4200,1400,100,*,LEFT,POLY +S 4600,1400,4600,2600,100,*,DOWN,POLY +S 4000,1400,4000,2500,100,*,UP,POLY +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 5200,2600,5200,4900,100,*,UP,PTRANS +S 5800,2600,5800,4900,100,*,UP,PTRANS +S 5500,2800,5500,4700,300,*,UP,PDIF +S 6100,2800,6100,4700,300,*,UP,PDIF +S 4900,2800,4900,4700,300,*,UP,PDIF +S 4300,2800,4300,4700,300,*,UP,PDIF +S 4600,2600,4600,4900,100,*,UP,PTRANS +S 4000,2600,4000,4900,100,*,UP,PTRANS +S 4900,300,4900,1200,300,*,DOWN,NDIF +S 6100,300,6100,1200,300,*,DOWN,NDIF +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5200,100,5200,1400,100,*,UP,NTRANS +S 5800,100,5800,1400,100,*,DOWN,NTRANS +S 4600,100,4600,1400,100,*,UP,NTRANS +S 4200,100,4200,1400,100,*,UP,NTRANS +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 5500,950,5500,4050,200,*,DOWN,ALU1 +S 6100,300,6100,1000,200,*,DOWN,ALU1 +S 6100,3500,6100,4600,200,*,DOWN,ALU1 +S 4300,3500,4300,4000,100,*,UP,ALU1 +S 4900,3500,4900,4600,200,*,DOWN,ALU1 +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 800,1400,900,1400,100,*,LEFT,POLY +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,100,800,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 900,1400,900,2600,100,*,DOWN,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +V 3700,4500,CONT_DIF_P,* +V 5000,2000,CONT_POLY,* +V 3200,400,CONT_BODY_P,* +V 4000,2500,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 6100,3500,CONT_DIF_P,* +V 6100,4500,CONT_DIF_P,* +V 6100,4000,CONT_DIF_P,* +V 5500,3000,CONT_DIF_P,* +V 5500,3500,CONT_DIF_P,* +V 5500,4000,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 4900,4500,CONT_DIF_P,* +V 4900,3500,CONT_DIF_P,* +V 4300,4000,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 6100,500,CONT_DIF_N,* +V 6100,1000,CONT_DIF_N,* +V 5500,1000,CONT_DIF_N,* +V 4900,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a2a23_x4.sym b/pdks/symbolic/sxlib/cells/oa2a2a23_x4.sym new file mode 100644 index 000000000..19dec265d Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa2a2a23_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa2a2a23_x4.vbe b/pdks/symbolic/sxlib/cells/oa2a2a23_x4.vbe new file mode 100644 index 000000000..c39f56f93 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a23_x4.vbe @@ -0,0 +1,56 @@ +ENTITY oa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT tphh_i5_q : NATURAL := 379; + CONSTANT tphh_i4_q : NATURAL := 464; + CONSTANT tphh_i2_q : NATURAL := 493; + CONSTANT tphh_i3_q : NATURAL := 594; + CONSTANT tpll_i1_q : NATURAL := 613; + CONSTANT tpll_i0_q : NATURAL := 648; + CONSTANT tpll_i4_q : NATURAL := 673; + CONSTANT tpll_i3_q : NATURAL := 677; + CONSTANT tphh_i0_q : NATURAL := 699; + CONSTANT tpll_i5_q : NATURAL := 714; + CONSTANT tpll_i2_q : NATURAL := 715; + CONSTANT tphh_i1_q : NATURAL := 822; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a23_x4" + SEVERITY WARNING; + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa2a2a23_x4.vhd b/pdks/symbolic/sxlib/cells/oa2a2a23_x4.vhd new file mode 100644 index 000000000..61d3a82ab --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a23_x4.vhd @@ -0,0 +1,24 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a2a23_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a2a23_x4; + +ARCHITECTURE RTL OF oa2a2a23_x4 IS +BEGIN + q <= (((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.al b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.al new file mode 100644 index 000000000..56c387c7a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.al @@ -0,0 +1,70 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x2,L,30/10/99 +C i0,IN,EXTERNAL,19 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,15 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,10 +C i5,IN,EXTERNAL,9 +C i6,IN,EXTERNAL,8 +C i7,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,18 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,18,1,14,0,0.75,0.75,13.3,13.3,20.4,11.25,tr_00018 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.8,11.25,tr_00017 +T P,0.35,5.9,14,19,13,0,0.75,0.75,13.3,13.3,18.6,11.25,tr_00016 +T P,0.35,5.9,13,16,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00015 +T P,0.35,5.9,1,7,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00014 +T P,0.35,5.9,6,15,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00013 +T P,0.35,5.9,6,10,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00012 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,5,8,1,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T N,0.35,2.9,3,9,4,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00009 +T N,0.35,2.9,4,15,12,0,0.75,0.75,7.3,7.3,12,2.25,tr_00008 +T N,0.35,2.9,11,17,1,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00007 +T N,0.35,2.9,4,19,11,0,0.75,0.75,7.3,7.3,18.6,2.25,tr_00006 +T N,0.35,2.9,18,1,4,0,0.75,0.75,7.3,7.3,20.4,2.25,tr_00005 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004 +T N,0.35,2.9,12,16,1,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00003 +T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 19,EXTERNAL,i0 +Q 0.00261741 +S 18,EXTERNAL,q +Q 0.00264397 +S 17,EXTERNAL,i1 +Q 0.00210054 +S 16,EXTERNAL,i3 +Q 0.00232574 +S 15,EXTERNAL,i2 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00769303 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i4 +Q 0.00232574 +S 9,EXTERNAL,i5 +Q 0.00232574 +S 8,EXTERNAL,i6 +Q 0.00269068 +S 7,EXTERNAL,i7 +Q 0.00260759 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,EXTERNAL,vss +Q 0.00692922 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00855851 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.ap b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.ap new file mode 100644 index 000000000..b35581754 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.ap @@ -0,0 +1,172 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x2,P, 3/12/2003,100 +A 0,0,7500,5000 +R 6500,3500,ref_ref,i0_35 +R 5500,2000,ref_ref,i1_20 +R 5500,2500,ref_ref,i1_25 +R 5500,3000,ref_ref,i1_30 +R 5500,1500,ref_ref,i1_15 +R 6500,1500,ref_ref,i0_15 +R 6500,2000,ref_ref,i0_20 +R 6500,2500,ref_ref,i0_25 +R 6500,3000,ref_ref,i0_30 +R 7000,1000,ref_ref,q_10 +R 7000,4000,ref_ref,q_40 +R 7000,2000,ref_ref,q_20 +R 7000,1500,ref_ref,q_15 +R 7000,3500,ref_ref,q_35 +R 7000,3000,ref_ref,q_30 +R 7000,2500,ref_ref,q_25 +R 500,1000,ref_ref,i7_10 +R 500,1500,ref_ref,i7_15 +R 500,2000,ref_ref,i7_20 +R 500,2500,ref_ref,i7_25 +R 500,3000,ref_ref,i7_30 +R 1500,1500,ref_ref,i6_15 +R 1500,2000,ref_ref,i6_20 +R 1500,2500,ref_ref,i6_25 +R 1500,3000,ref_ref,i6_30 +R 2500,1500,ref_ref,i5_15 +R 2500,2000,ref_ref,i5_20 +R 2500,2500,ref_ref,i5_25 +R 2500,3000,ref_ref,i5_30 +R 3000,1500,ref_ref,i4_15 +R 3000,2000,ref_ref,i4_20 +R 3000,2500,ref_ref,i4_25 +R 3000,3000,ref_ref,i4_30 +R 3500,1500,ref_ref,i3_15 +R 3500,2000,ref_ref,i3_20 +R 3500,2500,ref_ref,i3_25 +R 3500,3000,ref_ref,i3_30 +R 4000,1500,ref_ref,i2_15 +R 4000,2000,ref_ref,i2_20 +R 4000,2500,ref_ref,i2_25 +R 4000,3000,ref_ref,i2_30 +S 5300,2800,5300,4700,300,*,UP,PDIF +S 4500,2800,4500,4700,300,*,UP,PDIF +S 4900,300,4900,800,300,*,UP,PTIE +S 5500,1500,5500,3000,200,i1,DOWN,CALU1 +S 6500,1500,6500,3500,200,i0,DOWN,CALU1 +S 7000,1000,7000,4000,200,q,DOWN,CALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +S 6500,1500,6500,3500,100,*,UP,ALU1 +S 5500,1500,5700,1500,200,*,RIGHT,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 4800,1000,4800,2000,100,*,UP,ALU1 +S 6300,1500,6500,1500,200,*,RIGHT,ALU1 +S 6300,2500,6500,2500,200,*,RIGHT,ALU1 +S 7000,950,7000,4050,200,*,DOWN,ALU1 +S 1000,1000,5500,1000,100,*,RIGHT,ALU1 +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 5800,100,5800,1400,100,*,UP,NTRANS +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5300,4000,5300,4600,200,*,DOWN,ALU1 +S 6500,4000,6500,4600,200,*,DOWN,ALU1 +S 5900,3500,5900,4000,100,*,UP,ALU1 +S 3900,3500,5900,3500,100,*,RIGHT,ALU1 +S 7100,2800,7100,4700,300,*,UP,PDIF +S 6800,2600,6800,4900,100,*,UP,PTRANS +S 6500,2800,6500,4700,300,*,UP,PDIF +S 5600,2600,5600,4900,100,*,UP,PTRANS +S 6200,2600,6200,4900,100,*,UP,PTRANS +S 5900,2800,5900,4700,300,*,UP,PDIF +S 6500,300,6500,1200,300,*,DOWN,NDIF +S 6200,100,6200,1400,100,*,UP,NTRANS +S 7100,300,7100,1200,300,*,DOWN,NDIF +S 6800,100,6800,1400,100,*,UP,NTRANS +S 6800,1400,6800,2600,100,*,DOWN,POLY +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 500,1000,500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3900,2800,3900,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3300,2800,3300,4700,300,*,UP,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +S 4800,2000,6800,2000,100,*,RIGHT,POLY +S 0,300,7500,300,600,vss,RIGHT,CALU1 +S 0,3900,7500,3900,2400,*,RIGHT,NWELL +S 0,4700,7500,4700,600,vdd,RIGHT,CALU1 +V 5300,4500,CONT_DIF_P,* +V 5700,1500,CONT_POLY,* +V 5500,2500,CONT_POLY,* +V 4800,2000,CONT_POLY,* +V 6300,2500,CONT_POLY,* +V 6300,1500,CONT_POLY,* +V 4900,400,CONT_BODY_P,* +V 2300,500,CONT_DIF_N,* +V 4300,500,CONT_DIF_N,* +V 5500,1000,CONT_DIF_N,* +V 5300,4000,CONT_DIF_P,* +V 5900,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 7100,3000,CONT_DIF_P,* +V 7100,3500,CONT_DIF_P,* +V 6500,4500,CONT_DIF_P,* +V 7100,4000,CONT_DIF_P,* +V 6500,4000,CONT_DIF_P,* +V 6500,500,CONT_DIF_N,* +V 7100,1000,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3300,3500,CONT_DIF_P,* +V 4000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 300,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.sym b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.sym new file mode 100644 index 000000000..f3db5d904 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.vbe b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.vbe new file mode 100644 index 000000000..39a24492c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rdown_i7_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT rup_i7_q : NATURAL := 1790; + CONSTANT tphh_i7_q : NATURAL := 346; + CONSTANT tphh_i6_q : NATURAL := 426; + CONSTANT tphh_i5_q : NATURAL := 467; + CONSTANT tphh_i4_q : NATURAL := 565; + CONSTANT tphh_i2_q : NATURAL := 682; + CONSTANT tpll_i6_q : NATURAL := 748; + CONSTANT tpll_i1_q : NATURAL := 753; + CONSTANT tphh_i0_q : NATURAL := 780; + CONSTANT tpll_i0_q : NATURAL := 797; + CONSTANT tpll_i7_q : NATURAL := 800; + CONSTANT tphh_i3_q : NATURAL := 803; + CONSTANT tpll_i3_q : NATURAL := 810; + CONSTANT tpll_i4_q : NATURAL := 813; + CONSTANT tpll_i2_q : NATURAL := 856; + CONSTANT tpll_i5_q : NATURAL := 861; + CONSTANT tphh_i1_q : NATURAL := 909; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x2" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1500 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.vhd b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.vhd new file mode 100644 index 000000000..3615b8070 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x2.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a2a2a24_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + i7 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a2a2a24_x2; + +ARCHITECTURE RTL OF oa2a2a2a24_x2 IS +BEGIN + q <= ((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.al b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.al new file mode 100644 index 000000000..08c8f70f3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.al @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x4,L,30/10/99 +C i0,IN,EXTERNAL,19 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,15 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C i6,IN,EXTERNAL,9 +C i7,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,18 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00020 +T P,0.35,5.9,5,8,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00019 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00018 +T P,0.35,5.9,6,15,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00017 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00016 +T P,0.35,5.9,13,16,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00015 +T P,0.35,5.9,14,19,13,0,0.75,0.75,13.3,13.3,18.6,11.25,tr_00014 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.8,11.25,tr_00013 +T P,0.35,5.9,14,2,18,0,0.75,0.75,13.3,13.3,22.2,11.25,tr_00012 +T P,0.35,5.9,18,2,14,0,0.75,0.75,13.3,13.3,20.4,11.25,tr_00011 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00010 +T N,0.35,2.9,2,9,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00009 +T N,0.35,2.9,12,16,2,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00008 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00007 +T N,0.35,2.9,18,2,3,0,0.75,0.75,7.3,7.3,20.4,2.25,tr_00006 +T N,0.35,2.9,3,19,11,0,0.75,0.75,7.3,7.3,18.6,2.25,tr_00005 +T N,0.35,2.9,18,2,3,0,0.75,0.75,7.3,7.3,22.2,2.25,tr_00004 +T N,0.35,2.9,11,17,2,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00003 +T N,0.35,2.9,3,15,12,0,0.75,0.75,7.3,7.3,12,2.25,tr_00002 +T N,0.35,2.9,4,8,3,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00001 +S 19,EXTERNAL,i0 +Q 0.00261741 +S 18,EXTERNAL,q +Q 0.00264397 +S 17,EXTERNAL,i1 +Q 0.00210054 +S 16,EXTERNAL,i3 +Q 0.00232574 +S 15,EXTERNAL,i2 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00932712 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i7 +Q 0.00260759 +S 9,EXTERNAL,i6 +Q 0.00269068 +S 8,EXTERNAL,i5 +Q 0.00232574 +S 7,EXTERNAL,i4 +Q 0.00232574 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00815202 +S 2,INTERNAL +Q 0.00988877 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.ap b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.ap new file mode 100644 index 000000000..30e7e03fb --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.ap @@ -0,0 +1,184 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x4,P, 3/12/2003,100 +A 0,0,8000,5000 +R 6500,3500,ref_ref,i0_35 +R 5500,2000,ref_ref,i1_20 +R 5500,2500,ref_ref,i1_25 +R 5500,3000,ref_ref,i1_30 +R 5500,1500,ref_ref,i1_15 +R 6500,1500,ref_ref,i0_15 +R 6500,2000,ref_ref,i0_20 +R 6500,2500,ref_ref,i0_25 +R 6500,3000,ref_ref,i0_30 +R 7000,1000,ref_ref,q_10 +R 7000,4000,ref_ref,q_40 +R 7000,2000,ref_ref,q_20 +R 7000,1500,ref_ref,q_15 +R 7000,3500,ref_ref,q_35 +R 7000,3000,ref_ref,q_30 +R 7000,2500,ref_ref,q_25 +R 500,1000,ref_ref,i7_10 +R 500,1500,ref_ref,i7_15 +R 500,2000,ref_ref,i7_20 +R 500,2500,ref_ref,i7_25 +R 500,3000,ref_ref,i7_30 +R 1500,1500,ref_ref,i6_15 +R 1500,2000,ref_ref,i6_20 +R 1500,2500,ref_ref,i6_25 +R 1500,3000,ref_ref,i6_30 +R 2500,1500,ref_ref,i5_15 +R 2500,2000,ref_ref,i5_20 +R 2500,2500,ref_ref,i5_25 +R 2500,3000,ref_ref,i5_30 +R 3000,1500,ref_ref,i4_15 +R 3000,2000,ref_ref,i4_20 +R 3000,2500,ref_ref,i4_25 +R 3000,3000,ref_ref,i4_30 +R 3500,1500,ref_ref,i3_15 +R 3500,2000,ref_ref,i3_20 +R 3500,2500,ref_ref,i3_25 +R 3500,3000,ref_ref,i3_30 +R 4000,1500,ref_ref,i2_15 +R 4000,2000,ref_ref,i2_20 +R 4000,2500,ref_ref,i2_25 +R 4000,3000,ref_ref,i2_30 +S 6500,1500,6500,3500,100,*,UP,ALU1 +S 4800,2000,7400,2000,100,*,RIGHT,POLY +S 5500,1500,5700,1500,200,*,RIGHT,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 4800,1000,4800,2000,100,*,UP,ALU1 +S 6300,1500,6500,1500,200,*,RIGHT,ALU1 +S 6300,2500,6500,2500,200,*,RIGHT,ALU1 +S 7000,950,7000,4050,200,*,DOWN,ALU1 +S 1000,1000,5500,1000,100,*,RIGHT,ALU1 +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 5800,100,5800,1400,100,*,UP,NTRANS +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5300,4000,5300,4600,200,*,DOWN,ALU1 +S 6500,4000,6500,4600,200,*,DOWN,ALU1 +S 5900,3500,5900,4000,100,*,UP,ALU1 +S 3900,3500,5900,3500,100,*,RIGHT,ALU1 +S 7100,2800,7100,4700,300,*,UP,PDIF +S 7700,2800,7700,4700,300,*,UP,PDIF +S 6800,2600,6800,4900,100,*,UP,PTRANS +S 6500,2800,6500,4700,300,*,UP,PDIF +S 7400,2600,7400,4900,100,*,UP,PTRANS +S 5600,2600,5600,4900,100,*,UP,PTRANS +S 6200,2600,6200,4900,100,*,UP,PTRANS +S 5900,2800,5900,4700,300,*,UP,PDIF +S 7400,100,7400,1400,100,*,DOWN,NTRANS +S 6500,300,6500,1200,300,*,DOWN,NDIF +S 7700,300,7700,1200,300,*,DOWN,NDIF +S 6200,100,6200,1400,100,*,UP,NTRANS +S 7100,300,7100,1200,300,*,DOWN,NDIF +S 6800,100,6800,1400,100,*,UP,NTRANS +S 6800,1400,6800,2600,100,*,DOWN,POLY +S 7400,1400,7400,2600,100,*,DOWN,POLY +S 7700,300,7700,1000,200,*,DOWN,ALU1 +S 7700,3500,7700,4600,200,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 0,4700,8000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,8000,3900,2400,*,RIGHT,NWELL +S 0,300,8000,300,600,vss,RIGHT,CALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 500,1000,500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3900,2800,3900,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3300,2800,3300,4700,300,*,UP,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +S 6500,1500,6500,3500,200,i0,DOWN,CALU1 +S 5500,1500,5500,3000,200,i1,DOWN,CALU1 +S 7000,1000,7000,4000,200,q,DOWN,CALU1 +S 500,1000,500,3000,200,i7,DOWN,CALU1 +S 1500,1500,1500,3000,200,i6,DOWN,CALU1 +S 2500,1500,2500,3000,200,i5,DOWN,CALU1 +S 3000,1500,3000,3000,200,i4,DOWN,CALU1 +S 3500,1500,3500,3000,200,i3,DOWN,CALU1 +S 4000,1500,4000,3000,200,i2,DOWN,CALU1 +S 5300,2800,5300,4700,300,*,UP,PDIF +S 4500,2800,4500,4700,300,*,UP,PDIF +S 4900,300,4900,800,300,*,UP,PTIE +V 5700,1500,CONT_POLY,* +V 5500,2500,CONT_POLY,* +V 4800,2000,CONT_POLY,* +V 6300,2500,CONT_POLY,* +V 6300,1500,CONT_POLY,* +V 4900,400,CONT_BODY_P,* +V 2300,500,CONT_DIF_N,* +V 4300,500,CONT_DIF_N,* +V 5500,1000,CONT_DIF_N,* +V 5300,4000,CONT_DIF_P,* +V 5900,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 7700,4000,CONT_DIF_P,* +V 7100,3000,CONT_DIF_P,* +V 7100,3500,CONT_DIF_P,* +V 6500,4500,CONT_DIF_P,* +V 7100,4000,CONT_DIF_P,* +V 6500,4000,CONT_DIF_P,* +V 7700,3500,CONT_DIF_P,* +V 7700,4500,CONT_DIF_P,* +V 7700,1000,CONT_DIF_N,* +V 6500,500,CONT_DIF_N,* +V 7100,1000,CONT_DIF_N,* +V 7700,500,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3300,3500,CONT_DIF_P,* +V 4000,2500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3000,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 300,500,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 5300,4500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.sym b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.sym new file mode 100644 index 000000000..90d920643 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.vbe b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.vbe new file mode 100644 index 000000000..33d168440 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.vbe @@ -0,0 +1,68 @@ +ENTITY oa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rdown_i7_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT rup_i7_q : NATURAL := 890; + CONSTANT tphh_i7_q : NATURAL := 399; + CONSTANT tphh_i6_q : NATURAL := 487; + CONSTANT tphh_i5_q : NATURAL := 515; + CONSTANT tphh_i4_q : NATURAL := 619; + CONSTANT tphh_i2_q : NATURAL := 726; + CONSTANT tphh_i0_q : NATURAL := 823; + CONSTANT tpll_i1_q : NATURAL := 835; + CONSTANT tpll_i6_q : NATURAL := 845; + CONSTANT tphh_i3_q : NATURAL := 851; + CONSTANT tpll_i0_q : NATURAL := 879; + CONSTANT tpll_i3_q : NATURAL := 895; + CONSTANT tpll_i7_q : NATURAL := 895; + CONSTANT tpll_i4_q : NATURAL := 902; + CONSTANT tpll_i2_q : NATURAL := 940; + CONSTANT tpll_i5_q : NATURAL := 949; + CONSTANT tphh_i1_q : NATURAL := 955; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2a2a2a24_x4" + SEVERITY WARNING; + q <= ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) after 1600 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.vhd b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.vhd new file mode 100644 index 000000000..480fb8b86 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2a2a2a24_x4.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2a2a2a24_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + i7 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2a2a2a24_x4; + +ARCHITECTURE RTL OF oa2a2a2a24_x4 IS +BEGIN + q <= ((((i0 AND i1) OR (i2 AND i3)) OR (i4 AND i5)) OR (i6 AND i7)); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa2ao222_x2.al b/pdks/symbolic/sxlib/cells/oa2ao222_x2.al new file mode 100644 index 000000000..4491d1517 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2ao222_x2.al @@ -0,0 +1,49 @@ +V ALLIANCE : 6 +H oa2ao222_x2,L,30/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C i4,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,13,2,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00012 +T P,0.35,5.9,6,9,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00011 +T P,0.35,4.25,6,11,5,0,0.75,0.75,10,10,3.6,10.42,tr_00010 +T P,0.35,4.25,5,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00009 +T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00007 +T N,0.35,2.9,4,2,13,0,0.75,0.75,7.3,7.3,12.3,3.75,tr_00006 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00005 +T N,0.35,1.7,1,9,4,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00004 +T N,0.35,2.6,2,11,3,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00003 +T N,0.35,2.6,3,12,4,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00002 +T N,0.35,1.7,1,10,2,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00001 +S 13,EXTERNAL,q +Q 0.00276148 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL,i3 +Q 0.00197871 +S 8,EXTERNAL +Q 0.00212909 +S 7,INTERNAL +Q 0 +S 6,INTERNAL +Q 0.00227626 +S 5,EXTERNAL,vdd +Q 0.00557437 +S 4,EXTERNAL,vss +Q 0.00657321 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00590927 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2ao222_x2.ap b/pdks/symbolic/sxlib/cells/oa2ao222_x2.ap new file mode 100644 index 000000000..a33bfd196 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2ao222_x2.ap @@ -0,0 +1,130 @@ +V ALLIANCE : 6 +H oa2ao222_x2,P,20/ 6/2002,100 +A 0,0,5000,5000 +R 4500,4000,ref_ref,q_40 +R 4500,2000,ref_ref,q_20 +R 4500,2500,ref_ref,q_25 +R 4500,3000,ref_ref,q_30 +R 4500,1000,ref_ref,q_10 +R 4500,3500,ref_ref,q_35 +R 4500,1500,ref_ref,q_15 +R 500,1000,ref_ref,i0_10 +R 500,1500,ref_ref,i0_15 +R 500,2000,ref_ref,i0_20 +R 500,2500,ref_ref,i0_25 +R 500,3000,ref_ref,i0_30 +R 500,3500,ref_ref,i0_35 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 1500,3500,ref_ref,i4_35 +R 1500,3000,ref_ref,i4_30 +R 1500,2500,ref_ref,i4_25 +R 1500,2000,ref_ref,i4_20 +R 2500,1500,ref_ref,i2_15 +R 2500,2000,ref_ref,i2_20 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 3000,1500,ref_ref,i3_15 +R 3000,2000,ref_ref,i3_20 +R 3000,2500,ref_ref,i3_25 +R 3000,3000,ref_ref,i3_30 +S 2900,1900,2900,2600,100,*,UP,POLY +S 2400,1900,2400,2600,100,*,UP,POLY +S 1700,1900,1700,2600,100,*,UP,POLY +S 1100,1900,1100,2600,100,*,UP,POLY +S 600,1900,600,2600,100,*,UP,POLY +S 4200,300,4800,300,300,*,RIGHT,PTIE +S 1500,2000,1700,2000,300,*,RIGHT,POLY +S 4500,1000,4500,4000,200,q,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 1500,2000,1500,3500,200,i4,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 3000,1500,3000,3000,200,i3,DOWN,CALU1 +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 2100,3500,3900,3500,100,*,RIGHT,ALU1 +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 3800,800,3800,1700,300,*,UP,NDIF +S 4100,600,4100,1900,100,*,DOWN,NTRANS +S 4400,800,4400,1700,300,*,UP,NDIF +S 3800,2500,4100,2500,300,*,RIGHT,POLY +S 4100,1900,4100,2600,100,*,UP,POLY +S 3800,300,3800,1500,200,*,DOWN,ALU1 +S 3800,4000,3800,4700,200,*,UP,ALU1 +S 3900,2500,3900,3500,100,*,DOWN,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 2000,900,2000,1700,300,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 1400,900,1400,1700,300,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 300,500,300,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 2600,500,2600,1700,300,*,UP,NDIF +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 600,2600,600,4350,100,*,UP,PTRANS +S 300,2800,300,4150,300,*,UP,PDIF +S 2700,2800,2700,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 4500,1000,4500,4000,200,*,DOWN,ALU1 +S 1500,2800,1500,4700,200,*,UP,PDIF +V 4700,300,CONT_BODY_P,* +V 4300,300,CONT_BODY_P,* +V 4400,3000,CONT_DIF_P,* +V 3800,4000,CONT_DIF_P,* +V 4400,3500,CONT_DIF_P,* +V 3800,4500,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 3800,1500,CONT_DIF_N,* +V 4400,1000,CONT_DIF_N,* +V 4400,1500,CONT_DIF_N,* +V 3800,1000,CONT_DIF_N,* +V 3900,2500,CONT_POLY,* +V 1200,400,CONT_BODY_P,* +V 1600,400,CONT_BODY_P,* +V 2000,400,CONT_BODY_P,* +V 300,500,CONT_DIF_N,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 500,2000,CONT_POLY,* +V 3200,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 1400,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2600,500,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2ao222_x2.sym b/pdks/symbolic/sxlib/cells/oa2ao222_x2.sym new file mode 100644 index 000000000..1e610a786 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa2ao222_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa2ao222_x2.vbe b/pdks/symbolic/sxlib/cells/oa2ao222_x2.vbe new file mode 100644 index 000000000..2a96b29e2 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2ao222_x2.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT tpll_i4_q : NATURAL := 453; + CONSTANT tphh_i2_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 495; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphh_i3_q : NATURAL := 556; + CONSTANT tphh_i4_q : NATURAL := 558; + CONSTANT tpll_i3_q : NATURAL := 578; + CONSTANT tpll_i0_q : NATURAL := 581; + CONSTANT tphh_i1_q : NATURAL := 598; + CONSTANT tpll_i2_q : NATURAL := 604; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x2; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1200 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa2ao222_x2.vhd b/pdks/symbolic/sxlib/cells/oa2ao222_x2.vhd new file mode 100644 index 000000000..5ef47e621 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2ao222_x2.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2ao222_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2ao222_x2; + +ARCHITECTURE RTL OF oa2ao222_x2 IS +BEGIN + q <= ((i0 AND i1) OR (i4 AND (i2 OR i3))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa2ao222_x4.al b/pdks/symbolic/sxlib/cells/oa2ao222_x4.al new file mode 100644 index 000000000..3aafc2a22 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2ao222_x4.al @@ -0,0 +1,51 @@ +V ALLIANCE : 6 +H oa2ao222_x4,L,30/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C i4,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,13,2,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00014 +T P,0.35,5.9,6,9,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00013 +T P,0.35,4.25,6,11,5,0,0.75,0.75,10,10,3.6,10.42,tr_00012 +T P,0.35,4.25,5,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00011 +T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,5,2,13,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00008 +T N,0.35,2.9,4,2,13,0,0.75,0.75,7.3,7.3,12.3,3.75,tr_00007 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00006 +T N,0.35,1.7,1,9,4,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00005 +T N,0.35,2.6,2,11,3,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00004 +T N,0.35,2.6,3,12,4,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00003 +T N,0.35,1.7,1,10,2,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00002 +T N,0.35,2.9,13,2,4,0,0.75,0.75,7.3,7.3,14.1,3.75,tr_00001 +S 13,EXTERNAL,q +Q 0.00276148 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL,i3 +Q 0.00197871 +S 8,EXTERNAL +Q 0.00212909 +S 7,INTERNAL +Q 0 +S 6,INTERNAL +Q 0.00227626 +S 5,EXTERNAL,vdd +Q 0.00773725 +S 4,EXTERNAL,vss +Q 0.00861858 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00727894 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2ao222_x4.ap b/pdks/symbolic/sxlib/cells/oa2ao222_x4.ap new file mode 100644 index 000000000..22c69c2e7 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2ao222_x4.ap @@ -0,0 +1,146 @@ +V ALLIANCE : 6 +H oa2ao222_x4,P,20/ 6/2002,100 +A 0,0,5500,5000 +R 3000,3000,ref_ref,i3_30 +R 3000,2500,ref_ref,i3_25 +R 3000,2000,ref_ref,i3_20 +R 3000,1500,ref_ref,i3_15 +R 2500,3000,ref_ref,i2_30 +R 2500,2500,ref_ref,i2_25 +R 2500,2000,ref_ref,i2_20 +R 2500,1500,ref_ref,i2_15 +R 1500,2000,ref_ref,i4_20 +R 1500,2500,ref_ref,i4_25 +R 1500,3000,ref_ref,i4_30 +R 1500,3500,ref_ref,i4_35 +R 1000,1500,ref_ref,i1_15 +R 1000,2000,ref_ref,i1_20 +R 1000,2500,ref_ref,i1_25 +R 1000,3000,ref_ref,i1_30 +R 1000,3500,ref_ref,i1_35 +R 500,3500,ref_ref,i0_35 +R 500,3000,ref_ref,i0_30 +R 500,2500,ref_ref,i0_25 +R 500,2000,ref_ref,i0_20 +R 500,1500,ref_ref,i0_15 +R 500,1000,ref_ref,i0_10 +R 4500,1500,ref_ref,q_15 +R 4500,3500,ref_ref,q_35 +R 4500,1000,ref_ref,q_10 +R 4500,3000,ref_ref,q_30 +R 4500,2500,ref_ref,q_25 +R 4500,2000,ref_ref,q_20 +R 4500,4000,ref_ref,q_40 +S 2900,1900,2900,2600,100,*,UP,POLY +S 2400,1900,2400,2600,100,*,UP,POLY +S 1700,1900,1700,2600,100,*,UP,POLY +S 1100,1900,1100,2600,100,*,UP,POLY +S 600,1900,600,2600,100,*,UP,POLY +S 3100,300,5100,300,300,*,RIGHT,PTIE +S 4500,1000,4500,4000,200,*,DOWN,ALU1 +S 3900,2500,4700,2500,300,*,RIGHT,POLY +S 5000,3000,5000,4700,200,*,UP,ALU1 +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 5000,800,5000,1700,300,*,UP,NDIF +S 5000,300,5000,1500,200,*,DOWN,ALU1 +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4700,1900,4700,2600,100,*,UP,POLY +S 4700,600,4700,1900,100,*,DOWN,NTRANS +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 600,2600,600,4350,100,*,UP,PTRANS +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 2600,500,2600,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 300,500,300,1700,300,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1400,900,1400,1700,300,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 2000,900,2000,1700,300,*,UP,NDIF +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3900,2500,3900,3500,100,*,DOWN,ALU1 +S 3800,4000,3800,4700,200,*,UP,ALU1 +S 3800,300,3800,1500,200,*,DOWN,ALU1 +S 4100,1900,4100,2600,100,*,UP,POLY +S 3800,2500,4100,2500,300,*,RIGHT,POLY +S 4400,800,4400,1700,300,*,UP,NDIF +S 4100,600,4100,1900,100,*,DOWN,NTRANS +S 3800,800,3800,1700,300,*,UP,NDIF +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 2100,3500,3900,3500,100,*,RIGHT,ALU1 +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 3000,1500,3000,3000,200,i3,DOWN,CALU1 +S 2500,1500,2500,3000,200,i2,DOWN,CALU1 +S 1500,2000,1500,3500,200,i4,DOWN,CALU1 +S 1000,1500,1000,3500,200,i1,DOWN,CALU1 +S 500,1000,500,3500,200,i0,DOWN,CALU1 +S 4500,1000,4500,4000,200,q,DOWN,CALU1 +S 1500,2000,1700,2000,300,*,RIGHT,POLY +S 1500,2800,1500,4700,200,*,UP,PDIF +V 3200,300,CONT_BODY_P,* +V 5000,300,CONT_BODY_P,* +V 3800,300,CONT_BODY_P,* +V 5000,3000,CONT_DIF_P,* +V 5000,3500,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 5000,4500,CONT_DIF_P,* +V 5000,1000,CONT_DIF_N,* +V 5000,1500,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +V 2600,500,CONT_DIF_N,* +V 3200,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 1400,1000,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 3200,4000,CONT_DIF_P,* +V 500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 300,500,CONT_DIF_N,* +V 2000,400,CONT_BODY_P,* +V 1600,400,CONT_BODY_P,* +V 1200,400,CONT_BODY_P,* +V 3900,2500,CONT_POLY,* +V 4400,300,CONT_BODY_P,* +V 3800,1000,CONT_DIF_N,* +V 4400,1500,CONT_DIF_N,* +V 4400,1000,CONT_DIF_N,* +V 3800,1500,CONT_DIF_N,* +V 4400,4000,CONT_DIF_P,* +V 3800,4500,CONT_DIF_P,* +V 4400,3500,CONT_DIF_P,* +V 3800,4000,CONT_DIF_P,* +V 4400,3000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa2ao222_x4.sym b/pdks/symbolic/sxlib/cells/oa2ao222_x4.sym new file mode 100644 index 000000000..d47162842 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa2ao222_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa2ao222_x4.vbe b/pdks/symbolic/sxlib/cells/oa2ao222_x4.vbe new file mode 100644 index 000000000..d8e7b2abf --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT tpll_i4_q : NATURAL := 529; + CONSTANT tphh_i2_q : NATURAL := 552; + CONSTANT tphh_i0_q : NATURAL := 553; + CONSTANT tpll_i1_q : NATURAL := 616; + CONSTANT tphh_i3_q : NATURAL := 640; + CONSTANT tphh_i4_q : NATURAL := 656; + CONSTANT tpll_i0_q : NATURAL := 657; + CONSTANT tpll_i3_q : NATURAL := 660; + CONSTANT tphh_i1_q : NATURAL := 662; + CONSTANT tpll_i2_q : NATURAL := 693; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa2ao222_x4.vhd b/pdks/symbolic/sxlib/cells/oa2ao222_x4.vhd new file mode 100644 index 000000000..11ed1fc9a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa2ao222_x4.vhd @@ -0,0 +1,23 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa2ao222_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa2ao222_x4; + +ARCHITECTURE RTL OF oa2ao222_x4 IS +BEGIN + q <= ((i0 AND i1) OR (i4 AND (i2 OR i3))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa3ao322_x1.sym b/pdks/symbolic/sxlib/cells/oa3ao322_x1.sym new file mode 100644 index 000000000..3b587ba74 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa3ao322_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa3ao322_x2.al b/pdks/symbolic/sxlib/cells/oa3ao322_x2.al new file mode 100644 index 000000000..6f7a09546 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa3ao322_x2.al @@ -0,0 +1,63 @@ +V ALLIANCE : 6 +H oa3ao322_x2,L,30/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,15 +C i5,IN,EXTERNAL,16 +C i6,IN,EXTERNAL,11 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,7,2,4,0,0.75,0.75,13.3,13.3,2.4,11.25,tr_00016 +T P,0.35,4.4,14,17,2,0,0.75,0.75,10.3,10.3,11.7,10.5,tr_00015 +T P,0.35,4.4,13,15,14,0,0.75,0.75,10.3,10.3,13.2,10.5,tr_00014 +T P,0.35,4.4,6,16,13,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00013 +T P,0.35,3.2,6,10,7,0,0.75,0.75,7.9,7.9,4.2,11.1,tr_00012 +T P,0.35,3.2,7,9,6,0,0.75,0.75,7.9,7.9,6,11.1,tr_00011 +T P,0.35,3.2,6,8,7,0,0.75,0.75,7.9,7.9,7.8,11.1,tr_00010 +T P,0.35,3.5,2,11,6,0,0.75,0.75,8.5,8.5,9.6,10.95,tr_00009 +T N,0.35,2.9,4,2,3,0,0.75,0.75,7.3,7.3,2.4,3.75,tr_00008 +T N,0.35,1.7,12,11,2,0,0.75,0.75,4.9,4.9,9.3,3.45,tr_00007 +T N,0.35,1.1,3,17,12,0,0.75,0.75,3.7,3.7,11.1,3.15,tr_00006 +T N,0.35,1.1,12,15,3,0,0.75,0.75,3.7,3.7,12.9,3.15,tr_00005 +T N,0.35,1.1,3,16,12,0,0.75,0.75,3.7,3.7,14.7,3.15,tr_00004 +T N,0.35,2.3,2,8,1,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00003 +T N,0.35,2.3,1,9,5,0,0.75,0.75,6.1,6.1,6,3.75,tr_00002 +T N,0.35,2.3,5,10,3,0,0.75,0.75,6.1,6.1,4.5,3.75,tr_00001 +S 17,EXTERNAL,i3 +Q 0.00290834 +S 16,EXTERNAL,i5 +Q 0.00275797 +S 15,EXTERNAL,i4 +Q 0.00283894 +S 14,INTERNAL +Q 0 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0.00114171 +S 11,EXTERNAL,i6 +Q 0.00262649 +S 10,EXTERNAL,i0 +Q 0.00290834 +S 9,EXTERNAL,i1 +Q 0.00275797 +S 8,EXTERNAL,i2 +Q 0.00247612 +S 7,EXTERNAL,vdd +Q 0.00644464 +S 6,INTERNAL +Q 0.00261448 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,q +Q 0.00258522 +S 3,EXTERNAL,vss +Q 0.00679717 +S 2,INTERNAL +Q 0.00549512 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa3ao322_x2.ap b/pdks/symbolic/sxlib/cells/oa3ao322_x2.ap new file mode 100644 index 000000000..a04575bc2 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa3ao322_x2.ap @@ -0,0 +1,161 @@ +V ALLIANCE : 6 +H oa3ao322_x2,P, 8/ 6/2002,100 +A 0,0,5500,5000 +R 500,3500,ref_ref,q_35 +R 500,3000,ref_ref,q_30 +R 500,2500,ref_ref,q_25 +R 500,2000,ref_ref,q_20 +R 500,1500,ref_ref,q_15 +R 500,1000,ref_ref,q_10 +R 500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,i0_35 +R 4000,3500,ref_ref,i3_35 +R 5000,2500,ref_ref,i5_25 +R 5000,3000,ref_ref,i5_30 +R 5000,3500,ref_ref,i5_35 +R 1500,1500,ref_ref,i0_15 +R 1500,2000,ref_ref,i0_20 +R 1500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i0_30 +R 4000,3000,ref_ref,i3_30 +R 4500,1500,ref_ref,i4_15 +R 4500,2000,ref_ref,i4_20 +R 4500,2500,ref_ref,i4_25 +R 4500,3000,ref_ref,i4_30 +R 4500,3500,ref_ref,i4_35 +R 5000,1500,ref_ref,i5_15 +R 5000,2000,ref_ref,i5_20 +R 4000,1500,ref_ref,i3_15 +R 4000,2000,ref_ref,i3_20 +R 4000,2500,ref_ref,i3_25 +R 2500,2500,ref_ref,i2_25 +R 2500,3000,ref_ref,i2_30 +R 2500,3500,ref_ref,i2_35 +R 3000,2000,ref_ref,i6_20 +R 3000,2500,ref_ref,i6_25 +R 3000,3000,ref_ref,i6_30 +R 3000,3500,ref_ref,i6_35 +R 2000,1500,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_20 +R 2000,2500,ref_ref,i1_25 +R 2000,3000,ref_ref,i1_30 +R 2000,3500,ref_ref,i1_35 +R 2500,2000,ref_ref,i2_20 +S 1100,2800,1100,4700,200,*,DOWN,PDIF +S 3000,2000,3200,2000,300,*,RIGHT,POLY +S 800,2000,1000,2000,300,*,LEFT,POLY +S 500,1000,500,4000,200,q,DOWN,CALU1 +S 1500,1500,1500,3500,200,i0,DOWN,CALU1 +S 4500,1500,4500,3500,200,i4,DOWN,CALU1 +S 5000,1500,5000,3500,200,i5,DOWN,CALU1 +S 4000,1500,4000,3500,200,i3,DOWN,CALU1 +S 3000,2000,3000,3500,200,i6,DOWN,CALU1 +S 2000,1500,2000,3500,200,i1,DOWN,CALU1 +S 2500,2000,2500,3500,200,i2,DOWN,CALU1 +S 3100,1900,3200,1900,100,*,LEFT,POLY +S 1400,1900,1500,1900,100,*,RIGHT,POLY +S 3900,1900,3900,2600,100,*,UP,POLY +S 3700,1900,3900,1900,100,*,RIGHT,POLY +S 800,2600,800,4900,100,*,UP,PTRANS +S 500,2800,500,4700,300,*,DOWN,PDIF +S 500,800,500,1700,300,*,UP,NDIF +S 800,600,800,1900,100,*,DOWN,NTRANS +S 1200,500,1200,1700,300,*,UP,NDIF +S 4700,400,5100,400,300,*,RIGHT,PTIE +S 800,1900,800,2600,100,*,DOWN,POLY +S 4900,1900,4900,2600,100,i5,DOWN,POLY +S 4400,1900,4400,2600,100,i4,UP,POLY +S 4300,1900,4400,1900,100,*,RIGHT,POLY +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 500,1000,500,4000,200,*,UP,ALU1 +S 1100,4000,1100,4700,200,*,UP,ALU1 +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 1000,1000,1000,2000,100,*,UP,ALU1 +S 3400,1000,4600,1000,100,*,RIGHT,ALU1 +S 4000,1500,4000,3500,100,*,UP,ALU1 +S 3500,1500,3500,3500,100,*,DOWN,ALU1 +S 1500,1500,1500,3500,100,*,DOWN,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 4500,1500,4500,3500,100,*,UP,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 5200,300,5200,1000,200,*,DOWN,ALU1 +S 5000,1500,5000,3500,100,*,DOWN,ALU1 +S 2500,2000,2500,3500,100,*,UP,ALU1 +S 2800,1000,2800,1500,100,*,UP,ALU1 +S 2800,1500,3500,1500,100,*,RIGHT,ALU1 +S 1000,1000,2800,1000,100,*,LEFT,ALU1 +S 1700,4000,5200,4000,100,*,RIGHT,ALU1 +S 3900,2600,3900,4400,100,*,UP,PTRANS +S 4400,2600,4400,4400,100,*,UP,PTRANS +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 3100,700,3100,1600,100,*,UP,NTRANS +S 3700,700,3700,1400,100,*,UP,NTRANS +S 4300,700,4300,1400,100,*,UP,NTRANS +S 4900,700,4900,1400,100,*,UP,NTRANS +S 5200,900,5200,1200,300,*,UP,NDIF +S 4600,900,4600,1200,300,*,UP,NDIF +S 4000,400,4000,1200,300,*,DOWN,NDIF +S 3400,900,3400,1400,200,*,UP,NDIF +S 2800,900,2800,1400,200,*,UP,NDIF +S 3100,1600,3100,1900,100,*,UP,POLY +S 3700,1400,3700,1900,100,*,UP,POLY +S 4300,1400,4300,1900,100,*,UP,POLY +S 1400,3000,1400,4400,100,*,UP,PTRANS +S 2000,3000,2000,4400,100,*,UP,PTRANS +S 2600,3000,2600,4400,100,*,UP,PTRANS +S 3200,2900,3200,4400,100,*,UP,PTRANS +S 5200,2800,5200,4200,300,*,UP,PDIF +S 1700,3200,1700,4200,300,*,UP,PDIF +S 2300,3200,2300,4500,300,*,DOWN,PDIF +S 2900,3100,2900,4200,200,*,UP,PDIF +S 3500,3100,3500,4200,400,*,DOWN,PDIF +S 1400,1900,1400,3000,100,*,DOWN,POLY +S 2000,1900,2000,3000,100,*,DOWN,POLY +S 2600,1900,2600,3000,100,i2,UP,POLY +S 3200,1900,3200,2900,100,i6,UP,POLY +S 2500,700,2500,1800,100,*,UP,NTRANS +S 2000,700,2000,1800,100,*,UP,NTRANS +S 1500,700,1500,1800,100,*,UP,NTRANS +S 1800,400,3300,400,300,*,RIGHT,PTIE +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 1500,1800,1500,2000,100,*,DOWN,POLY +S 2000,1800,2000,2000,100,*,UP,POLY +S 2500,1800,2500,2000,100,*,UP,POLY +S 4900,1400,4900,2000,100,*,UP,POLY +S 2800,4700,4800,4700,300,*,RIGHT,NTIE +V 500,3500,CONT_DIF_P,* +V 1100,4000,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 3500,3000,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 2300,4500,CONT_DIF_P,* +V 5200,4000,CONT_DIF_P,* +V 500,1500,CONT_DIF_N,* +V 4000,500,CONT_DIF_N,* +V 2800,1000,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 1200,500,CONT_DIF_N,* +V 5200,1000,CONT_DIF_N,* +V 4600,1000,CONT_DIF_N,* +V 5100,400,CONT_BODY_P,* +V 4700,400,CONT_BODY_P,* +V 1000,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 5000,2000,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 4000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 2900,4000,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 2900,4700,CONT_BODY_N,* +V 3500,4700,CONT_BODY_N,* +V 4100,4700,CONT_BODY_N,* +V 4700,4700,CONT_BODY_N,* +V 2800,400,CONT_BODY_P,* +V 2300,400,CONT_BODY_P,* +V 1800,400,CONT_BODY_P,* +V 3350,400,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa3ao322_x2.sym b/pdks/symbolic/sxlib/cells/oa3ao322_x2.sym new file mode 100644 index 000000000..5fbf4f56b Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa3ao322_x2.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa3ao322_x2.vbe b/pdks/symbolic/sxlib/cells/oa3ao322_x2.vbe new file mode 100644 index 000000000..dc2a71887 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa3ao322_x2.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT tpll_i6_q : NATURAL := 540; + CONSTANT tphh_i3_q : NATURAL := 560; + CONSTANT tphh_i6_q : NATURAL := 563; + CONSTANT tphh_i0_q : NATURAL := 638; + CONSTANT tphh_i4_q : NATURAL := 649; + CONSTANT tpll_i2_q : NATURAL := 707; + CONSTANT tphh_i5_q : NATURAL := 734; + CONSTANT tpll_i5_q : NATURAL := 734; + CONSTANT tphh_i1_q : NATURAL := 735; + CONSTANT tpll_i4_q : NATURAL := 760; + CONSTANT tpll_i1_q : NATURAL := 764; + CONSTANT tpll_i3_q : NATURAL := 765; + CONSTANT tphh_i2_q : NATURAL := 806; + CONSTANT tpll_i0_q : NATURAL := 820; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x2; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa3ao322_x2.vhd b/pdks/symbolic/sxlib/cells/oa3ao322_x2.vhd new file mode 100644 index 000000000..23b695b4a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa3ao322_x2.vhd @@ -0,0 +1,25 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa3ao322_x2 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa3ao322_x2; + +ARCHITECTURE RTL OF oa3ao322_x2 IS +BEGIN + q <= (((i0 AND i1) AND i2) OR (i6 AND ((i3 OR i4) OR i5))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/oa3ao322_x4.al b/pdks/symbolic/sxlib/cells/oa3ao322_x4.al new file mode 100644 index 000000000..eacaab987 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa3ao322_x4.al @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H oa3ao322_x4,L,30/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,14 +C i5,IN,EXTERNAL,15 +C i6,IN,EXTERNAL,17 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,3.2,11,9,5,0,0.75,0.75,7.9,7.9,9.3,11.1,tr_00018 +T P,0.35,3.5,8,17,11,0,0.75,0.75,8.5,8.5,11.1,10.95,tr_00017 +T P,0.35,5.9,5,8,2,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00016 +T P,0.35,4.4,13,16,8,0,0.75,0.75,10.3,10.3,13.2,10.5,tr_00015 +T P,0.35,3.2,5,7,11,0,0.75,0.75,7.9,7.9,7.5,11.1,tr_00014 +T P,0.35,4.4,11,15,12,0,0.75,0.75,10.3,10.3,16.2,10.5,tr_00013 +T P,0.35,4.4,12,14,13,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00012 +T P,0.35,3.2,11,6,5,0,0.75,0.75,7.9,7.9,5.7,11.1,tr_00011 +T P,0.35,5.9,2,8,5,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00010 +T N,0.35,2.3,3,7,4,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00009 +T N,0.35,1.7,10,17,8,0,0.75,0.75,4.9,4.9,10.8,3.45,tr_00008 +T N,0.35,1.1,1,16,10,0,0.75,0.75,3.7,3.7,12.6,3.15,tr_00007 +T N,0.35,2.3,4,6,1,0,0.75,0.75,6.1,6.1,6,3.75,tr_00006 +T N,0.35,2.3,8,9,3,0,0.75,0.75,6.1,6.1,9,3.75,tr_00005 +T N,0.35,2.9,2,8,1,0,0.75,0.75,7.3,7.3,3.9,3.75,tr_00004 +T N,0.35,1.1,10,14,1,0,0.75,0.75,3.7,3.7,14.4,3.15,tr_00003 +T N,0.35,1.1,1,15,10,0,0.75,0.75,3.7,3.7,16.2,3.15,tr_00002 +T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00001 +S 17,EXTERNAL,i6 +Q 0.00262649 +S 16,EXTERNAL,i3 +Q 0.00290835 +S 15,EXTERNAL,i5 +Q 0.00275797 +S 14,EXTERNAL,i4 +Q 0.00283894 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0.00261448 +S 10,INTERNAL +Q 0.00114171 +S 9,EXTERNAL,i2 +Q 0.00247612 +S 8,INTERNAL +Q 0.00668962 +S 7,EXTERNAL,i1 +Q 0.00275797 +S 6,EXTERNAL,i0 +Q 0.00290834 +S 5,EXTERNAL,vdd +Q 0.00849001 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,q +Q 0.00258522 +S 1,EXTERNAL,vss +Q 0.00825499 +EOF diff --git a/pdks/symbolic/sxlib/cells/oa3ao322_x4.ap b/pdks/symbolic/sxlib/cells/oa3ao322_x4.ap new file mode 100644 index 000000000..173d7d6c2 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa3ao322_x4.ap @@ -0,0 +1,174 @@ +V ALLIANCE : 6 +H oa3ao322_x4,P, 8/ 6/2002,100 +A 0,0,6000,5000 +R 3500,3500,ref_ref,i6_35 +R 2500,1500,ref_ref,i1_15 +R 2500,2000,ref_ref,i1_20 +R 2500,2500,ref_ref,i1_25 +R 2500,3000,ref_ref,i1_30 +R 2500,3500,ref_ref,i1_35 +R 1000,3500,ref_ref,q_35 +R 3000,2000,ref_ref,i2_20 +R 4500,2000,ref_ref,i3_20 +R 4500,2500,ref_ref,i3_25 +R 3000,2500,ref_ref,i2_25 +R 3000,3000,ref_ref,i2_30 +R 3000,3500,ref_ref,i2_35 +R 3500,2000,ref_ref,i6_20 +R 3500,2500,ref_ref,i6_25 +R 3500,3000,ref_ref,i6_30 +R 5000,1500,ref_ref,i4_15 +R 5000,2000,ref_ref,i4_20 +R 5000,2500,ref_ref,i4_25 +R 5000,3000,ref_ref,i4_30 +R 5000,3500,ref_ref,i4_35 +R 5500,1500,ref_ref,i5_15 +R 5500,2000,ref_ref,i5_20 +R 4500,1500,ref_ref,i3_15 +R 5500,2500,ref_ref,i5_25 +R 5500,3000,ref_ref,i5_30 +R 5500,3500,ref_ref,i5_35 +R 2000,1500,ref_ref,i0_15 +R 2000,2000,ref_ref,i0_20 +R 2000,2500,ref_ref,i0_25 +R 2000,3000,ref_ref,i0_30 +R 4500,3000,ref_ref,i3_30 +R 1000,3000,ref_ref,q_30 +R 1000,2500,ref_ref,q_25 +R 1000,2000,ref_ref,q_20 +R 1000,1500,ref_ref,q_15 +R 1000,1000,ref_ref,q_10 +R 1000,4000,ref_ref,q_40 +R 2000,3500,ref_ref,i0_35 +R 4500,3500,ref_ref,i3_35 +S 1600,2800,1600,4700,200,*,DOWN,PDIF +S 4000,2800,4000,4200,300,*,DOWN,PDIF +S 700,2000,1500,2000,300,*,LEFT,POLY +S 3500,2000,3700,2000,300,*,RIGHT,POLY +S 2500,1500,2500,3500,200,i1,DOWN,CALU1 +S 3000,2000,3000,3500,200,i2,DOWN,CALU1 +S 3500,2000,3500,3500,200,i6,DOWN,CALU1 +S 5000,1500,5000,3500,200,i4,DOWN,CALU1 +S 5500,1500,5500,3500,200,i5,DOWN,CALU1 +S 1000,1000,1000,4000,200,q,DOWN,CALU1 +S 2000,1500,2000,3500,200,i0,DOWN,CALU1 +S 4500,1500,4500,3500,200,i3,DOWN,CALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 5000,1500,5000,3500,100,*,UP,ALU1 +S 3500,2000,3500,3500,100,*,UP,ALU1 +S 5700,300,5700,1000,200,*,DOWN,ALU1 +S 5500,1500,5500,3500,100,*,DOWN,ALU1 +S 2200,4000,5700,4000,100,*,RIGHT,ALU1 +S 1500,1000,1500,2000,100,*,UP,ALU1 +S 3900,1000,5100,1000,100,*,RIGHT,ALU1 +S 4500,1500,4500,3500,100,*,UP,ALU1 +S 4000,1500,4000,3500,100,*,DOWN,ALU1 +S 1500,1000,3300,1000,100,*,LEFT,ALU1 +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 1600,4000,1600,4700,200,*,UP,ALU1 +S 3300,1500,4000,1500,100,*,RIGHT,ALU1 +S 3300,1000,3300,1500,100,*,UP,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 400,400,400,1500,200,*,DOWN,ALU1 +S 400,3000,400,4500,200,*,UP,ALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 1300,1900,1300,2600,100,*,DOWN,POLY +S 5400,1900,5400,2600,100,i5,DOWN,POLY +S 4900,1900,4900,2600,100,i4,UP,POLY +S 1900,1900,1900,3000,100,*,DOWN,POLY +S 4800,1900,4900,1900,100,*,RIGHT,POLY +S 2500,1800,2500,2000,100,*,UP,POLY +S 5400,1400,5400,2000,100,*,UP,POLY +S 3700,1900,3700,2900,100,i6,UP,POLY +S 4400,1900,4400,2600,100,*,UP,POLY +S 4200,1900,4400,1900,100,*,RIGHT,POLY +S 3100,1900,3100,3000,100,i2,UP,POLY +S 3000,1800,3000,2000,100,*,UP,POLY +S 4200,1400,4200,1900,100,*,UP,POLY +S 3600,1900,3700,1900,100,*,LEFT,POLY +S 1900,1900,2000,1900,100,*,RIGHT,POLY +S 2500,1900,2500,3000,100,*,DOWN,POLY +S 2000,1800,2000,2000,100,*,DOWN,POLY +S 4800,1400,4800,1900,100,*,UP,POLY +S 3600,1600,3600,1900,100,*,UP,POLY +S 700,1900,700,2600,100,*,DOWN,POLY +S 2300,400,3800,400,300,*,RIGHT,PTIE +S 5200,400,5600,400,300,*,RIGHT,PTIE +S 2500,700,2500,1800,100,*,UP,NTRANS +S 5100,900,5100,1200,300,*,UP,NDIF +S 4500,400,4500,1200,300,*,DOWN,NDIF +S 3600,700,3600,1600,100,*,UP,NTRANS +S 1700,500,1700,1700,300,*,UP,NDIF +S 3900,900,3900,1400,200,*,UP,NDIF +S 4200,700,4200,1400,100,*,UP,NTRANS +S 2000,700,2000,1800,100,*,UP,NTRANS +S 3000,700,3000,1800,100,*,UP,NTRANS +S 1000,800,1000,1700,300,*,UP,NDIF +S 1300,600,1300,1900,100,*,DOWN,NTRANS +S 4800,700,4800,1400,100,*,UP,NTRANS +S 3300,900,3300,1400,200,*,UP,NDIF +S 5400,700,5400,1400,100,*,UP,NTRANS +S 5700,900,5700,1200,300,*,UP,NDIF +S 400,800,400,1700,300,*,DOWN,NDIF +S 700,600,700,1900,100,*,DOWN,NTRANS +S 5700,2800,5700,4200,300,*,UP,PDIF +S 3100,3000,3100,4400,100,*,UP,PTRANS +S 3700,2900,3700,4400,100,*,UP,PTRANS +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 2200,3200,2200,4200,300,*,UP,PDIF +S 4400,2600,4400,4400,100,*,UP,PTRANS +S 2500,3000,2500,4400,100,*,UP,PTRANS +S 2800,3200,2800,4500,300,*,DOWN,PDIF +S 3400,3100,3400,4200,200,*,UP,PDIF +S 5400,2600,5400,4400,100,*,UP,PTRANS +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 1900,3000,1900,4400,100,*,UP,PTRANS +S 400,2800,400,4700,300,*,UP,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 3300,4700,5300,4700,300,*,RIGHT,NTIE +V 1500,2000,CONT_POLY,* +V 3500,2000,CONT_POLY,* +V 5000,2500,CONT_POLY,* +V 5500,2000,CONT_POLY,* +V 4500,2500,CONT_POLY,* +V 2000,2000,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 2300,400,CONT_BODY_P,* +V 3850,400,CONT_BODY_P,* +V 2800,400,CONT_BODY_P,* +V 3300,400,CONT_BODY_P,* +V 5600,400,CONT_BODY_P,* +V 5200,400,CONT_BODY_P,* +V 5700,1000,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 1700,500,CONT_DIF_N,* +V 1000,1500,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 400,1500,CONT_DIF_N,* +V 400,1000,CONT_DIF_N,* +V 3400,4000,CONT_DIF_P,* +V 4600,4700,CONT_BODY_N,* +V 1000,3500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 4000,4700,CONT_BODY_N,* +V 3400,4700,CONT_BODY_N,* +V 1600,4000,CONT_DIF_P,* +V 5200,4700,CONT_BODY_N,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 2800,4500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 2200,4000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 400,4000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/oa3ao322_x4.sym b/pdks/symbolic/sxlib/cells/oa3ao322_x4.sym new file mode 100644 index 000000000..a6afb4722 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/oa3ao322_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/oa3ao322_x4.vbe b/pdks/symbolic/sxlib/cells/oa3ao322_x4.vbe new file mode 100644 index 000000000..6f1ad9762 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT tpll_i6_q : NATURAL := 651; + CONSTANT tphh_i3_q : NATURAL := 673; + CONSTANT tphh_i6_q : NATURAL := 684; + CONSTANT tphh_i0_q : NATURAL := 717; + CONSTANT tphh_i4_q : NATURAL := 758; + CONSTANT tphh_i1_q : NATURAL := 818; + CONSTANT tpll_i2_q : NATURAL := 834; + CONSTANT tphh_i5_q : NATURAL := 839; + CONSTANT tpll_i5_q : NATURAL := 865; + CONSTANT tpll_i1_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 894; + CONSTANT tpll_i4_q : NATURAL := 896; + CONSTANT tpll_i3_q : NATURAL := 898; + CONSTANT tpll_i0_q : NATURAL := 946; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1500 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/oa3ao322_x4.vhd b/pdks/symbolic/sxlib/cells/oa3ao322_x4.vhd new file mode 100644 index 000000000..24b29df7c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/oa3ao322_x4.vhd @@ -0,0 +1,25 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY oa3ao322_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + i3 : IN STD_LOGIC; + i4 : IN STD_LOGIC; + i5 : IN STD_LOGIC; + i6 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END oa3ao322_x4; + +ARCHITECTURE RTL OF oa3ao322_x4 IS +BEGIN + q <= (((i0 AND i1) AND i2) OR (i6 AND ((i3 OR i4) OR i5))); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/on12_x1.al b/pdks/symbolic/sxlib/cells/on12_x1.al new file mode 100644 index 000000000..209fc17ff --- /dev/null +++ b/pdks/symbolic/sxlib/cells/on12_x1.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H on12_x1,L,30/10/99 +C i0,IN,EXTERNAL,5 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,7,5,1,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00006 +T P,0.35,2.9,1,2,7,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00005 +T P,0.35,2.9,7,6,2,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00004 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,1.8,4.5,tr_00003 +T N,0.35,2.9,4,5,1,0,0.75,0.75,7.3,7.3,4.8,3.75,tr_00002 +T N,0.35,2.9,3,2,4,0,0.75,0.75,7.3,7.3,3.6,3.75,tr_00001 +S 7,EXTERNAL,vdd +Q 0.0033382 +S 6,EXTERNAL,i1 +Q 0.00373582 +S 5,EXTERNAL,i0 +Q 0.00368237 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00316194 +S 2,INTERNAL +Q 0.00412385 +S 1,EXTERNAL,q +Q 0.00279086 +EOF diff --git a/pdks/symbolic/sxlib/cells/on12_x1.ap b/pdks/symbolic/sxlib/cells/on12_x1.ap new file mode 100644 index 000000000..5655762e7 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/on12_x1.ap @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H on12_x1,P, 8/ 6/2002,100 +A 0,0,2500,5000 +R 2000,4000,ref_ref,i0_40 +R 1500,4000,ref_ref,q_40 +R 1500,3500,ref_ref,q_35 +R 1500,3000,ref_ref,q_30 +R 1500,2500,ref_ref,q_25 +R 1500,2000,ref_ref,q_20 +R 1500,1500,ref_ref,q_15 +R 1000,2000,ref_ref,i1_20 +R 1000,1500,ref_ref,i1_15 +R 2000,1500,ref_ref,i0_15 +R 2000,2000,ref_ref,i0_20 +R 2000,2500,ref_ref,i0_25 +R 2000,3000,ref_ref,i0_30 +R 2000,3500,ref_ref,i0_35 +R 1000,4000,ref_ref,i1_40 +R 1000,3500,ref_ref,i1_35 +R 1000,3000,ref_ref,i1_30 +R 1000,2500,ref_ref,i1_25 +R 1000,1000,ref_ref,i1_10 +R 1500,1000,ref_ref,q_10 +S 300,200,300,700,300,*,UP,PTIE +S 1400,300,2300,300,300,*,RIGHT,PTIE +S 2000,1500,2000,4000,200,i0,DOWN,CALU1 +S 1000,1000,1000,4000,200,i1,DOWN,CALU1 +S 1500,1000,1500,4000,200,q,DOWN,CALU1 +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 800,2000,1000,2000,200,*,RIGHT,ALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 800,3000,1000,3000,200,*,RIGHT,ALU1 +S 300,1500,300,4000,100,*,UP,ALU1 +S 1500,950,1500,4000,200,*,UP,ALU1 +S 1500,1000,1900,1000,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 1800,1900,1800,3100,100,*,DOWN,POLY +S 1800,2000,2100,2000,300,*,RIGHT,POLY +S 1600,1900,2100,1900,100,*,RIGHT,POLY +S 1200,1900,1200,3100,100,*,UP,POLY +S 600,3000,800,3000,300,*,LEFT,POLY +S 600,2000,800,2000,300,*,LEFT,POLY +S 300,2500,1200,2500,100,*,RIGHT,POLY +S 600,1100,600,1900,100,*,DOWN,NTRANS +S 300,1300,300,1700,300,*,DOWN,NDIF +S 1900,800,1900,1700,300,*,UP,NDIF +S 1600,600,1600,1900,100,*,DOWN,NTRANS +S 1200,600,1200,1900,100,*,DOWN,NTRANS +S 900,400,900,1700,300,*,UP,NDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 900,3300,900,4600,300,*,DOWN,PDIF +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +V 2200,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 2000,2000,CONT_POLY,* +V 800,3000,CONT_POLY,* +V 800,2000,CONT_POLY,* +V 300,2500,CONT_POLY,* +V 300,300,CONT_BODY_P,* +V 300,1500,CONT_DIF_N,* +V 1900,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 2100,4500,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/on12_x1.sym b/pdks/symbolic/sxlib/cells/on12_x1.sym new file mode 100644 index 000000000..6b8b5019c Binary files /dev/null and b/pdks/symbolic/sxlib/cells/on12_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/on12_x1.vbe b/pdks/symbolic/sxlib/cells/on12_x1.vbe new file mode 100644 index 000000000..32688f423 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/on12_x1.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3720; + CONSTANT rup_i1_q : NATURAL := 3720; + CONSTANT tphl_i0_q : NATURAL := 111; + CONSTANT tplh_i0_q : NATURAL := 234; + CONSTANT tpll_i1_q : NATURAL := 291; + CONSTANT tphh_i1_q : NATURAL := 314; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x1; + +ARCHITECTURE behaviour_data_flow OF on12_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x1" + SEVERITY WARNING; + q <= (not (i0) or i1) after 900 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/on12_x1.vhd b/pdks/symbolic/sxlib/cells/on12_x1.vhd new file mode 100644 index 000000000..8e0928f32 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/on12_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY on12_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END on12_x1; + +ARCHITECTURE RTL OF on12_x1 IS +BEGIN + q <= (NOT(i0) OR i1); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/on12_x4.al b/pdks/symbolic/sxlib/cells/on12_x4.al new file mode 100644 index 000000000..3f58d0ad2 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/on12_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H on12_x4,L,30/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,4,7,1,0,0.75,0.75,7.3,7.3,1.8,12.75,tr_00010 +T P,0.35,4.4,5,1,2,0,0.75,0.75,10.3,10.3,5.4,10.5,tr_00009 +T P,0.35,5.9,4,2,8,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00008 +T P,0.35,5.9,8,2,4,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00007 +T P,0.35,4.4,4,6,5,0,0.75,0.75,10.3,10.3,6.6,10.5,tr_00006 +T N,0.35,1.4,3,7,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005 +T N,0.35,2.9,8,2,3,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00004 +T N,0.35,2.9,3,2,8,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00003 +T N,0.35,1.4,3,1,2,0,0.75,0.75,4.3,4.3,4.8,3,tr_00002 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,6.6,3,tr_00001 +S 8,EXTERNAL,q +Q 0.00264397 +S 7,EXTERNAL,i0 +Q 0.00406025 +S 6,EXTERNAL,i1 +Q 0.00344095 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00589026 +S 3,EXTERNAL,vss +Q 0.00547897 +S 2,INTERNAL +Q 0.00629378 +S 1,INTERNAL +Q 0.00472684 +EOF diff --git a/pdks/symbolic/sxlib/cells/on12_x4.ap b/pdks/symbolic/sxlib/cells/on12_x4.ap new file mode 100644 index 000000000..5c4ccc93d --- /dev/null +++ b/pdks/symbolic/sxlib/cells/on12_x4.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 6 +H on12_x4,P,18/ 5/2002,100 +A 0,0,4000,5000 +R 1000,1000,ref_ref,i0_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 1000,1500,ref_ref,i0_15 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 3000,1000,ref_ref,q_10 +R 2500,1000,ref_ref,i1_10 +R 2500,1500,ref_ref,i1_15 +R 2500,4000,ref_ref,i1_40 +R 2500,3500,ref_ref,i1_35 +R 2500,3000,ref_ref,i1_30 +R 2500,2500,ref_ref,i1_25 +R 3000,4000,ref_ref,q_40 +R 3000,3500,ref_ref,q_35 +R 3000,3000,ref_ref,q_30 +R 3000,2500,ref_ref,q_25 +R 3000,2000,ref_ref,q_20 +R 3000,1500,ref_ref,q_15 +R 2500,2000,ref_ref,i1_20 +S 1400,4700,2000,4700,300,*,RIGHT,NTIE +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 3000,1000,3000,4000,200,q,DOWN,CALU1 +S 2500,1000,2500,4000,200,i1,DOWN,CALU1 +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,3800,300,4700,300,*,UP,PDIF +S 600,3600,600,4900,100,*,UP,PTRANS +S 900,3800,900,4700,300,*,UP,PDIF +S 600,3400,600,3600,100,*,DOWN,POLY +S 600,3500,800,3500,100,*,RIGHT,POLY +S 800,3500,1000,3500,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 300,2000,1600,2000,100,*,RIGHT,POLY +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 600,1500,800,1500,100,*,RIGHT,POLY +S 600,1400,600,1600,100,*,UP,POLY +S 300,800,300,1200,300,*,UP,NDIF +S 1100,400,1100,1200,700,*,UP,NDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1500,2800,1500,4200,300,*,DOWN,PDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 2500,2800,2500,4700,300,*,UP,PDIF +S 3100,2800,3100,4700,300,*,UP,PDIF +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 2200,2600,2200,4400,100,*,UP,PTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,UP,NTRANS +S 3100,300,3100,1200,300,*,UP,NDIF +S 3700,300,3700,1200,300,*,UP,NDIF +S 3400,100,3400,1400,100,*,UP,NTRANS +S 1600,600,1600,1400,100,*,DOWN,NTRANS +S 1900,800,1900,1200,300,*,UP,NDIF +S 2200,600,2200,1400,100,*,DOWN,NTRANS +S 2200,1500,2500,1500,300,*,RIGHT,POLY +S 2000,2000,3400,2000,100,*,RIGHT,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2800,1400,2800,2600,100,*,DOWN,POLY +S 1600,2600,1800,2600,100,*,RIGHT,POLY +S 1600,1400,1600,2600,100,*,DOWN,POLY +S 2200,2500,2500,2500,300,*,RIGHT,POLY +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 3000,950,3000,4050,200,*,UP,ALU1 +S 3700,500,3700,1000,200,*,DOWN,ALU1 +S 2500,1000,2500,4000,100,*,UP,ALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 3700,3000,3700,4500,200,*,UP,ALU1 +S 1500,2900,1900,2900,100,*,RIGHT,ALU1 +S 1900,1000,1900,2900,100,*,DOWN,ALU1 +S 1500,2900,1500,4000,100,*,DOWN,ALU1 +V 1900,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 900,4500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 800,3500,CONT_POLY,* +V 1500,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 300,2000,CONT_POLY,* +V 800,1500,CONT_POLY,* +V 1500,4000,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 3100,3000,CONT_DIF_P,* +V 2500,4500,CONT_DIF_P,* +V 3700,3000,CONT_DIF_P,* +V 3700,3500,CONT_DIF_P,* +V 3700,4000,CONT_DIF_P,* +V 3700,4500,CONT_DIF_P,* +V 3100,4000,CONT_DIF_P,* +V 3100,3500,CONT_DIF_P,* +V 1300,500,CONT_DIF_N,* +V 1900,1000,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 3100,1000,CONT_DIF_N,* +V 3700,500,CONT_DIF_N,* +V 3700,1000,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 2000,2000,CONT_POLY,* +V 2400,2500,CONT_POLY,* +V 2400,1500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/on12_x4.sym b/pdks/symbolic/sxlib/cells/on12_x4.sym new file mode 100644 index 000000000..6142c6ce3 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/on12_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/on12_x4.vbe b/pdks/symbolic/sxlib/cells/on12_x4.vbe new file mode 100644 index 000000000..c5f990c6c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/on12_x4.vbe @@ -0,0 +1,32 @@ +ENTITY on12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 394; + CONSTANT tphl_i0_q : NATURAL := 474; + CONSTANT tphh_i1_q : NATURAL := 491; + CONSTANT tplh_i0_q : NATURAL := 499; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x4; + +ARCHITECTURE behaviour_data_flow OF on12_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on on12_x4" + SEVERITY WARNING; + q <= (not (i0) or i1) after 1100 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/on12_x4.vhd b/pdks/symbolic/sxlib/cells/on12_x4.vhd new file mode 100644 index 000000000..2e6b4193d --- /dev/null +++ b/pdks/symbolic/sxlib/cells/on12_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY on12_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END on12_x4; + +ARCHITECTURE RTL OF on12_x4 IS +BEGIN + q <= (NOT(i0) OR i1); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/one_x0.al b/pdks/symbolic/sxlib/cells/one_x0.al new file mode 100644 index 000000000..b41db8928 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/one_x0.al @@ -0,0 +1,13 @@ +V ALLIANCE : 6 +H one_x0,L,30/10/99 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,1 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,2.1,9.75,tr_00001 +S 3,EXTERNAL,vss +Q 0.00473877 +S 2,EXTERNAL,q +Q 0.00223269 +S 1,EXTERNAL,vdd +Q 0.0037716 +EOF diff --git a/pdks/symbolic/sxlib/cells/one_x0.ap b/pdks/symbolic/sxlib/cells/one_x0.ap new file mode 100644 index 000000000..98257c102 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/one_x0.ap @@ -0,0 +1,37 @@ +V ALLIANCE : 6 +H one_x0,P,18/ 5/2002,100 +A 0,0,1500,5000 +R 1000,4000,ref_ref,q_40 +R 1000,3500,ref_ref,q_35 +R 1000,3000,ref_ref,q_30 +R 1000,2500,ref_ref,q_25 +R 1000,2000,ref_ref,q_20 +R 1000,1500,ref_ref,q_15 +R 1000,1000,ref_ref,q_10 +S 1000,1000,1000,4000,200,q,DOWN,CALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 1000,2800,1000,3700,300,*,DOWN,PDIF +S 700,2600,700,3900,100,*,UP,PTRANS +S 0,300,1500,300,600,vss,RIGHT,CALU1 +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 350,2800,350,3700,400,*,DOWN,PDIF +S 400,3000,400,4700,200,*,UP,ALU1 +S 700,2400,700,2600,100,*,DOWN,POLY +S 500,300,500,2500,200,*,DOWN,ALU1 +S 400,4500,1000,4500,300,*,RIGHT,NTIE +S 500,500,500,1500,300,*,DOWN,PTIE +S 500,500,1000,500,300,*,RIGHT,PTIE +S 500,2500,700,2500,300,*,RIGHT,POLY +V 1000,3000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +V 500,2500,CONT_POLY,* +V 500,500,CONT_BODY_P,* +V 500,1000,CONT_BODY_P,* +V 500,1500,CONT_BODY_P,* +V 1000,500,CONT_BODY_P,* +V 1000,4500,CONT_BODY_N,* +V 400,4500,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/one_x0.sym b/pdks/symbolic/sxlib/cells/one_x0.sym new file mode 100644 index 000000000..9f9e2854b Binary files /dev/null and b/pdks/symbolic/sxlib/cells/one_x0.sym differ diff --git a/pdks/symbolic/sxlib/cells/one_x0.vbe b/pdks/symbolic/sxlib/cells/one_x0.vbe new file mode 100644 index 000000000..e7439c597 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/one_x0.vbe @@ -0,0 +1,20 @@ +ENTITY one_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END one_x0; + +ARCHITECTURE behaviour_data_flow OF one_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on one_x0" + SEVERITY WARNING; + q <= '1'; +END; diff --git a/pdks/symbolic/sxlib/cells/one_x0.vhd b/pdks/symbolic/sxlib/cells/one_x0.vhd new file mode 100644 index 000000000..492070cb7 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/one_x0.vhd @@ -0,0 +1,18 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY one_x0 IS +PORT( + q : OUT STD_LOGIC +); +END one_x0; + +ARCHITECTURE RTL OF one_x0 IS +BEGIN + q <= '1'; +END RTL; diff --git a/pdks/symbolic/sxlib/cells/powmid_x0.al b/pdks/symbolic/sxlib/cells/powmid_x0.al new file mode 100644 index 000000000..a96fa128c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/powmid_x0.al @@ -0,0 +1,9 @@ +V ALLIANCE : 6 +H powmid_x0,L,02/08/2004 +C vdd,UNKNOWN,EXTERNAL,2 +C vss,UNKNOWN,EXTERNAL,1 +S 2,EXTERNAL,vdd +Q 0.0026439 +S 1,EXTERNAL,vss +Q 0.00371008 +EOF diff --git a/pdks/symbolic/sxlib/cells/powmid_x0.ap b/pdks/symbolic/sxlib/cells/powmid_x0.ap new file mode 100644 index 000000000..c375d0d13 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/powmid_x0.ap @@ -0,0 +1,14 @@ +V ALLIANCE : 6 +H powmid_x0,P, 6/ 6/2003,100 +A 0,0,3500,5000 +S 2000,0,3000,0,200,*,RIGHT,TALU2 +S 500,5000,1500,5000,200,*,RIGHT,TALU2 +S 0,300,3500,300,600,vss,RIGHT,CALU1 +S 0,4700,3500,4700,600,vdd,RIGHT,CALU1 +S 1000,0,1000,5000,1200,vdd,DOWN,CALU3 +S 2500,0,2500,5000,1200,vss,DOWN,CALU3 +B 2500,0,1200,200,CONT_VIA,* +B 2500,0,1200,200,CONT_VIA2,* +B 1000,5000,1200,200,CONT_VIA,* +B 1000,5000,1200,200,CONT_VIA2,* +EOF diff --git a/pdks/symbolic/sxlib/cells/powmid_x0.vbe b/pdks/symbolic/sxlib/cells/powmid_x0.vbe new file mode 100644 index 000000000..52f4c8149 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/powmid_x0.vbe @@ -0,0 +1,18 @@ +ENTITY powmid_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END powmid_x0; + +ARCHITECTURE behaviour_data_flow OF powmid_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on powmid_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/sxlib/cells/powmid_x0.vhd b/pdks/symbolic/sxlib/cells/powmid_x0.vhd new file mode 100644 index 000000000..e6b0b9d01 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/powmid_x0.vhd @@ -0,0 +1,16 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY powmid_x0 IS +PORT( +); +END powmid_x0; + +ARCHITECTURE RTL OF powmid_x0 IS +BEGIN +END RTL; diff --git a/pdks/symbolic/sxlib/cells/rowend_x0.al b/pdks/symbolic/sxlib/cells/rowend_x0.al new file mode 100644 index 000000000..a54f5a21d --- /dev/null +++ b/pdks/symbolic/sxlib/cells/rowend_x0.al @@ -0,0 +1,9 @@ +V ALLIANCE : 6 +H rowend_x0,L,30/10/99 +C vdd,IN,EXTERNAL,2 +C vss,IN,EXTERNAL,1 +S 2,EXTERNAL,vdd +Q 0.00126725 +S 1,EXTERNAL,vss +Q 0.00126725 +EOF diff --git a/pdks/symbolic/sxlib/cells/rowend_x0.ap b/pdks/symbolic/sxlib/cells/rowend_x0.ap new file mode 100644 index 000000000..d48764b74 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/rowend_x0.ap @@ -0,0 +1,7 @@ +V ALLIANCE : 6 +H rowend_x0,P,24/ 7/2002,100 +A 0,0,500,5000 +S 0,3900,500,3900,2400,*,RIGHT,NWELL +S 0,300,500,300,600,vss,RIGHT,CALU1 +S 0,4700,500,4700,600,vdd,RIGHT,CALU1 +EOF diff --git a/pdks/symbolic/sxlib/cells/rowend_x0.vbe b/pdks/symbolic/sxlib/cells/rowend_x0.vbe new file mode 100644 index 000000000..dfe3de719 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/rowend_x0.vbe @@ -0,0 +1,18 @@ +ENTITY rowend_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 250; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END rowend_x0; + +ARCHITECTURE behaviour_data_flow OF rowend_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rowend_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/sxlib/cells/rowend_x0.vhd b/pdks/symbolic/sxlib/cells/rowend_x0.vhd new file mode 100644 index 000000000..b21c2701e --- /dev/null +++ b/pdks/symbolic/sxlib/cells/rowend_x0.vhd @@ -0,0 +1,16 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY rowend_x0 IS +PORT( +); +END rowend_x0; + +ARCHITECTURE RTL OF rowend_x0 IS +BEGIN +END RTL; diff --git a/pdks/symbolic/sxlib/cells/sff1_x4.al b/pdks/symbolic/sxlib/cells/sff1_x4.al new file mode 100644 index 000000000..ea46bf2ac --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff1_x4.al @@ -0,0 +1,68 @@ +V ALLIANCE : 6 +H sff1_x4,L,30/10/99 +C ck,IN,EXTERNAL,5 +C i,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,17,13,14,0,0.75,0.75,7.3,7.3,21.6,12.75,tr_00026 +T P,0.35,2.9,12,3,17,0,0.75,0.75,7.3,7.3,19.8,12.75,tr_00025 +T P,0.35,2.9,9,2,12,0,0.75,0.75,7.3,7.3,18,12.75,tr_00024 +T P,0.35,2.9,7,2,15,0,0.75,0.75,7.3,7.3,12.6,11.25,tr_00023 +T P,0.35,2.9,15,9,14,0,0.75,0.75,7.3,7.3,14.4,12.75,tr_00022 +T P,0.35,2.9,16,3,7,0,0.75,0.75,7.3,7.3,10.8,11.25,tr_00021 +T P,0.35,2.9,2,5,14,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00020 +T P,0.35,2.9,14,2,3,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00019 +T P,0.35,2.9,4,6,14,0,0.75,0.75,7.3,7.3,7.2,12.75,tr_00018 +T P,0.35,2.9,14,4,16,0,0.75,0.75,7.3,7.3,9,12.75,tr_00017 +T P,0.35,5.9,14,12,13,0,0.75,0.75,13.3,13.3,23.4,11.25,tr_00016 +T P,0.35,5.9,13,12,14,0,0.75,0.75,13.3,13.3,25.2,11.25,tr_00015 +T P,0.35,2.9,9,7,14,0,0.75,0.75,7.3,7.3,16.2,12.75,tr_00014 +T N,0.35,1.4,11,2,12,0,0.75,0.75,4.3,4.3,19.8,3,tr_00013 +T N,0.35,1.4,1,13,11,0,0.75,0.75,4.3,4.3,21.6,3,tr_00012 +T N,0.35,1.4,12,3,9,0,0.75,0.75,4.3,4.3,18,3,tr_00011 +T N,0.35,1.4,1,9,8,0,0.75,0.75,4.3,4.3,14.4,1.5,tr_00010 +T N,0.35,1.4,8,3,7,0,0.75,0.75,4.3,4.3,12.6,3,tr_00009 +T N,0.35,1.4,7,2,10,0,0.75,0.75,4.3,4.3,10.8,3,tr_00008 +T N,0.35,1.4,3,2,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00007 +T N,0.35,1.4,1,5,2,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006 +T N,0.35,1.4,10,4,1,0,0.75,0.75,4.3,4.3,9,3,tr_00005 +T N,0.35,1.4,1,6,4,0,0.75,0.75,4.3,4.3,7.2,3,tr_00004 +T N,0.35,2.9,13,12,1,0,0.75,0.75,7.3,7.3,23.4,2.25,tr_00003 +T N,0.35,2.9,1,12,13,0,0.75,0.75,7.3,7.3,25.2,2.25,tr_00002 +T N,0.35,1.4,9,7,1,0,0.75,0.75,4.3,4.3,16.2,1.5,tr_00001 +S 17,INTERNAL +Q 0 +S 16,INTERNAL +Q 0 +S 15,INTERNAL +Q 0 +S 14,EXTERNAL,vdd +Q 0.0115377 +S 13,EXTERNAL,q +Q 0.00615082 +S 12,INTERNAL,sff_s +Q 0.00679978 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,INTERNAL,y +Q 0.00480814 +S 8,INTERNAL +Q 0 +S 7,INTERNAL,sff_m +Q 0.00642301 +S 6,EXTERNAL,i +Q 0.00344388 +S 5,EXTERNAL,ck +Q 0.00344095 +S 4,INTERNAL,u +Q 0.00567853 +S 3,INTERNAL,ckr +Q 0.0113963 +S 2,INTERNAL,nckr +Q 0.0123833 +S 1,EXTERNAL,vss +Q 0.0103626 +EOF diff --git a/pdks/symbolic/sxlib/cells/sff1_x4.ap b/pdks/symbolic/sxlib/cells/sff1_x4.ap new file mode 100644 index 000000000..83ff56fbe --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff1_x4.ap @@ -0,0 +1,217 @@ +V ALLIANCE : 6 +H sff1_x4,P,18/ 5/2002,100 +A 0,0,9000,5000 +R 3000,4000,ref_ref,i_40 +R 8000,1000,ref_ref,q_10 +R 8000,1500,ref_ref,q_15 +R 8000,2500,ref_ref,q_25 +R 8000,3000,ref_ref,q_30 +R 8000,3500,ref_ref,q_35 +R 8000,4000,ref_ref,q_40 +R 3000,1000,ref_ref,i_10 +R 2500,1500,ref_ref,i_15 +R 2500,2000,ref_ref,i_20 +R 2500,2500,ref_ref,i_25 +R 2500,3000,ref_ref,i_30 +R 2500,3500,ref_ref,i_35 +R 1000,1000,ref_ref,ck_10 +R 1000,1500,ref_ref,ck_15 +R 1000,2000,ref_ref,ck_20 +R 1000,2500,ref_ref,ck_25 +R 1000,3000,ref_ref,ck_30 +R 1000,3500,ref_ref,ck_35 +R 1000,4000,ref_ref,ck_40 +R 8000,2000,ref_ref,q_20 +S 8000,1000,8000,4000,200,*,DOWN,ALU1 +S 3000,1000,3000,1000,200,i,LEFT,CALU1 +S 3000,4000,3000,4000,200,i,LEFT,CALU1 +S 2500,1500,2500,3500,200,i,DOWN,CALU1 +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 800,3000,1000,3000,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,ck,DOWN,CALU1 +S 8000,1000,8000,4000,200,q,DOWN,CALU1 +S 6300,4000,6900,4000,100,*,RIGHT,ALU1 +S 6300,1000,6900,1000,100,*,RIGHT,ALU1 +S 6300,800,6300,1200,300,*,DOWN,NDIF +S 6300,3800,6300,4700,300,*,DOWN,PDIF +S 6600,600,6600,1400,100,*,UP,NTRANS +S 7200,600,7200,1400,100,*,UP,NTRANS +S 7200,3600,7200,4900,100,*,DOWN,PTRANS +S 6600,3600,6600,4900,100,*,DOWN,PTRANS +S 6000,3600,6000,4900,100,*,DOWN,PTRANS +S 6000,600,6000,1400,100,*,UP,NTRANS +S 4800,100,4800,900,100,*,UP,NTRANS +S 4200,600,4200,1400,100,*,UP,NTRANS +S 4200,3100,4200,4400,100,*,DOWN,PTRANS +S 4800,3600,4800,4900,100,*,DOWN,PTRANS +S 3600,3100,3600,4400,100,*,DOWN,PTRANS +S 3600,600,3600,1400,100,*,UP,NTRANS +S 3300,800,3300,1200,300,*,DOWN,NDIF +S 3300,3300,3300,4700,300,*,UP,PDIF +S 4500,1000,4500,3500,100,sff_m,DOWN,ALU1 +S 6900,1000,6900,4000,100,*,DOWN,ALU1 +S 3900,3500,4500,3500,100,*,RIGHT,ALU1 +S 3000,1500,3000,3000,100,u,DOWN,ALU1 +S 3000,3100,3000,3600,100,*,UP,POLY +S 4500,3300,4500,4700,300,*,UP,PDIF +S 4000,2000,4000,3000,100,*,UP,ALU1 +S 4200,2500,4200,3100,100,*,DOWN,POLY +S 3900,3300,3900,4200,300,*,UP,PDIF +S 3500,3000,4000,3000,100,*,RIGHT,ALU1 +S 1600,2000,6000,2000,100,ckr,RIGHT,POLY +S 300,2500,6600,2500,100,nckr,RIGHT,POLY +S 1500,3300,1500,4200,300,*,UP,PDIF +S 600,1500,900,1500,300,*,RIGHT,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 900,400,900,1200,300,*,DOWN,NDIF +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 1200,600,1200,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 300,800,300,1200,300,*,DOWN,NDIF +S 2000,3000,3000,3000,100,*,RIGHT,POLY +S 4800,1000,5100,1000,300,*,RIGHT,POLY +S 5100,1500,5400,1500,300,*,RIGHT,POLY +S 4800,3500,5100,3500,300,*,RIGHT,POLY +S 6300,3500,6600,3500,300,*,RIGHT,POLY +S 5100,3000,5400,3000,300,*,RIGHT,POLY +S 3900,2000,4200,2000,300,*,RIGHT,POLY +S 6000,2000,6300,2000,300,*,RIGHT,POLY +S 600,3000,900,3000,300,*,RIGHT,POLY +S 3500,1500,3500,2500,100,*,DOWN,ALU1 +S 900,3300,900,4600,300,*,UP,PDIF +S 300,3300,300,4200,300,*,UP,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 0,3900,9000,3900,2400,*,RIGHT,NWELL +S 2700,400,2700,1200,300,*,DOWN,NDIF +S 3000,600,3000,1400,100,*,UP,NTRANS +S 2400,600,2400,1400,100,*,UP,NTRANS +S 2100,800,2100,1200,300,*,DOWN,NDIF +S 4500,300,4500,1200,300,*,DOWN,NDIF +S 3900,800,3900,1200,300,*,DOWN,NDIF +S 7800,100,7800,1400,100,*,UP,NTRANS +S 6900,800,6900,1200,300,*,DOWN,NDIF +S 8700,300,8700,1200,300,*,DOWN,NDIF +S 8400,100,8400,1400,100,*,UP,NTRANS +S 8100,300,8100,1200,300,*,DOWN,NDIF +S 7500,300,7500,1200,300,*,DOWN,NDIF +S 5700,300,5700,1200,300,*,DOWN,NDIF +S 5100,300,5100,700,300,*,DOWN,NDIF +S 5700,300,5700,700,300,*,DOWN,NDIF +S 5400,100,5400,900,100,*,UP,NTRANS +S 2100,3800,2100,4700,300,*,UP,PDIF +S 2700,3800,2700,4700,300,*,UP,PDIF +S 2400,3600,2400,4900,100,*,DOWN,PTRANS +S 6900,3800,6900,4700,300,*,UP,PDIF +S 3000,3600,3000,4900,100,*,DOWN,PTRANS +S 7500,2800,7500,4700,300,*,DOWN,PDIF +S 7800,2600,7800,4900,100,*,DOWN,PTRANS +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 8400,2600,8400,4900,100,*,DOWN,PTRANS +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 5400,3600,5400,4900,100,*,UP,PTRANS +S 5000,3800,5000,4700,300,*,DOWN,PDIF +S 5600,3800,5600,4700,300,*,DOWN,PDIF +S 4200,1400,4200,2000,100,*,DOWN,POLY +S 6000,2500,6000,3600,100,*,DOWN,POLY +S 5400,3000,5400,3600,100,*,DOWN,POLY +S 5400,900,5400,1500,100,*,UP,POLY +S 6000,1400,6000,2000,100,*,DOWN,POLY +S 8400,1400,8400,2600,100,*,DOWN,POLY +S 7200,2500,7500,2500,300,*,RIGHT,POLY +S 7200,1500,7500,1500,300,*,RIGHT,POLY +S 7800,1400,7800,2600,100,*,DOWN,POLY +S 6600,1400,6600,2500,100,*,DOWN,POLY +S 0,300,9000,300,600,vss,RIGHT,CALU1 +S 0,4700,9000,4700,600,vdd,RIGHT,CALU1 +S 4500,3000,5200,3000,100,*,RIGHT,ALU1 +S 6300,2000,6300,3500,100,*,DOWN,ALU1 +S 5000,1000,5700,1000,100,*,RIGHT,ALU1 +S 3900,1000,4500,1000,100,*,RIGHT,ALU1 +S 4500,1500,5200,1500,100,*,LEFT,ALU1 +S 8700,3000,8700,4500,200,*,DOWN,ALU1 +S 7500,3000,7500,4500,200,*,DOWN,ALU1 +S 8700,500,8700,1000,200,*,DOWN,ALU1 +S 7500,500,7500,1000,200,*,DOWN,ALU1 +S 7400,2500,8100,2500,100,*,RIGHT,ALU1 +S 7400,1500,8100,1500,100,*,RIGHT,ALU1 +S 5700,1000,5700,4000,100,y,DOWN,ALU1 +S 5000,3500,5700,3500,100,*,LEFT,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 300,3500,300,4000,100,*,DOWN,ALU1 +S 1500,300,2100,300,300,*,RIGHT,PTIE +S 3300,300,3900,300,300,*,RIGHT,PTIE +S 6300,300,6900,300,300,*,RIGHT,PTIE +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 2550,1000,3000,1000,100,*,RIGHT,ALU1 +S 2550,4000,3000,4000,100,*,RIGHT,ALU1 +S 2050,1000,2050,4000,100,*,DOWN,ALU1 +S 7200,2400,7200,3600,100,*,UP,POLY +S 6900,2000,7400,2000,100,*,RIGHT,ALU1 +S 7300,2000,8400,2000,300,sff_s,RIGHT,POLY +V 3900,3500,CONT_DIF_P,* +V 3500,3000,CONT_POLY,* +V 2100,4000,CONT_DIF_P,* +V 6900,300,CONT_BODY_P,* +V 6300,300,CONT_BODY_P,* +V 8100,3500,CONT_DIF_P,* +V 8100,4000,CONT_DIF_P,* +V 800,1500,CONT_POLY,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 3500,1500,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 2500,3500,CONT_POLY,* +V 3900,300,CONT_BODY_P,* +V 3300,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 2000,3000,CONT_POLY,* +V 1600,2000,CONT_POLY,* +V 300,2500,CONT_POLY,* +V 800,3000,CONT_POLY,* +V 900,4500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 2700,500,CONT_DIF_N,* +V 8100,1000,CONT_DIF_N,* +V 7500,1000,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 7500,500,CONT_DIF_N,* +V 8700,500,CONT_DIF_N,* +V 5700,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 5100,500,CONT_DIF_N,* +V 6300,1000,CONT_DIF_N,* +V 2700,4500,CONT_DIF_P,* +V 8700,3500,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 7500,4500,CONT_DIF_P,* +V 8700,4500,CONT_DIF_P,* +V 7500,4000,CONT_DIF_P,* +V 7500,3500,CONT_DIF_P,* +V 7500,3000,CONT_DIF_P,* +V 8100,3000,CONT_DIF_P,* +V 8700,3000,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 6300,4000,CONT_DIF_P,* +V 6400,3500,CONT_POLY,* +V 5000,1000,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 5200,3000,CONT_POLY,* +V 6200,2000,CONT_POLY,* +V 5200,1500,CONT_POLY,* +V 7400,1500,CONT_POLY,* +V 7400,2500,CONT_POLY,* +V 5000,3500,CONT_POLY,* +V 1500,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 7400,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/sff1_x4.sym b/pdks/symbolic/sxlib/cells/sff1_x4.sym new file mode 100644 index 000000000..6702478b6 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/sff1_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/sff1_x4.vbe b/pdks/symbolic/sxlib/cells/sff1_x4.vbe new file mode 100644 index 000000000..4756bfddd --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff1_x4.vbe @@ -0,0 +1,39 @@ +ENTITY sff1_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tsr_i_ck : NATURAL := 476; + CONSTANT transistors : NATURAL := 26 +); +PORT ( + ck : in BIT; + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff1_x4; + +ARCHITECTURE VBE OF sff1_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff1_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED i; + END BLOCK label0; + + q <= sff_m after 1700 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/sff1_x4.vhd b/pdks/symbolic/sxlib/cells/sff1_x4.vhd new file mode 100644 index 000000000..b274aa53b --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff1_x4.vhd @@ -0,0 +1,27 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY sff1_x4 IS +PORT( + ck : IN STD_LOGIC; + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END sff1_x4; + +ARCHITECTURE RTL OF sff1_x4 IS + SIGNAL sff_m : STD_LOGIC; +BEGIN + q <= sff_m; + PROCESS ( ck ) + BEGIN + IF ((ck = '1') AND ck'EVENT) + THEN sff_m <= i; + END IF; + END PROCESS; +END RTL; diff --git a/pdks/symbolic/sxlib/cells/sff2_x4.al b/pdks/symbolic/sxlib/cells/sff2_x4.al new file mode 100644 index 000000000..fe6cd3d35 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff2_x4.al @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H sff2_x4,L,30/10/99 +C ck,IN,EXTERNAL,11 +C cmd,IN,EXTERNAL,6 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,17 +C vdd,IN,EXTERNAL,19 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,19,16,17,0,0.75,0.75,13.3,13.3,32.4,11.25,tr_00034 +T P,0.35,2.9,19,3,23,0,0.75,0.75,7.3,7.3,18,12.75,tr_00033 +T P,0.35,2.9,15,14,19,0,0.75,0.75,7.3,7.3,25.2,12.75,tr_00032 +T P,0.35,5.9,17,16,19,0,0.75,0.75,13.3,13.3,34.2,11.25,tr_00031 +T P,0.35,2.9,10,11,19,0,0.75,0.75,7.3,7.3,12.6,11.25,tr_00030 +T P,0.35,2.9,19,10,9,0,0.75,0.75,7.3,7.3,14.4,11.25,tr_00029 +T P,0.35,2.9,3,5,20,0,0.75,0.75,7.3,7.3,7.5,11.25,tr_00028 +T P,0.35,2.9,21,6,3,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00027 +T P,0.35,2.9,20,8,19,0,0.75,0.75,7.3,7.3,8.7,11.25,tr_00026 +T P,0.35,2.9,5,6,19,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00025 +T P,0.35,2.9,19,7,21,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00024 +T P,0.35,2.9,23,9,14,0,0.75,0.75,7.3,7.3,19.8,11.25,tr_00023 +T P,0.35,2.9,14,10,22,0,0.75,0.75,7.3,7.3,21.6,11.25,tr_00022 +T P,0.35,2.9,22,15,19,0,0.75,0.75,7.3,7.3,23.4,12.75,tr_00021 +T P,0.35,2.9,15,10,16,0,0.75,0.75,7.3,7.3,27,12.75,tr_00020 +T P,0.35,2.9,16,9,24,0,0.75,0.75,7.3,7.3,28.8,12.75,tr_00019 +T P,0.35,2.9,24,17,19,0,0.75,0.75,7.3,7.3,30.6,12.75,tr_00018 +T N,0.35,1.4,12,3,1,0,0.75,0.75,4.3,4.3,18,3,tr_00017 +T N,0.35,2.9,17,16,1,0,0.75,0.75,7.3,7.3,32.4,2.25,tr_00016 +T N,0.35,2.9,1,16,17,0,0.75,0.75,7.3,7.3,34.2,2.25,tr_00015 +T N,0.35,1.4,15,14,1,0,0.75,0.75,4.3,4.3,25.2,1.5,tr_00014 +T N,0.35,1.4,1,11,10,0,0.75,0.75,4.3,4.3,12.6,3,tr_00013 +T N,0.35,1.4,9,10,1,0,0.75,0.75,4.3,4.3,14.4,3,tr_00012 +T N,0.35,1.4,1,8,2,0,0.75,0.75,4.3,4.3,8.7,3,tr_00011 +T N,0.35,1.4,3,5,4,0,0.75,0.75,4.3,4.3,4.8,3,tr_00010 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,7.5,3,tr_00009 +T N,0.35,1.4,4,7,1,0,0.75,0.75,4.3,4.3,3.6,3,tr_00008 +T N,0.35,1.4,1,6,5,0,0.75,0.75,4.3,4.3,1.8,3,tr_00007 +T N,0.35,1.4,14,10,12,0,0.75,0.75,4.3,4.3,19.8,3,tr_00006 +T N,0.35,1.4,13,9,14,0,0.75,0.75,4.3,4.3,21.6,3,tr_00005 +T N,0.35,1.4,1,15,13,0,0.75,0.75,4.3,4.3,23.4,1.5,tr_00004 +T N,0.35,1.4,16,9,15,0,0.75,0.75,4.3,4.3,27,3,tr_00003 +T N,0.35,1.4,18,10,16,0,0.75,0.75,4.3,4.3,28.8,3,tr_00002 +T N,0.35,1.4,1,17,18,0,0.75,0.75,4.3,4.3,30.6,3,tr_00001 +S 24,INTERNAL +Q 0 +S 23,INTERNAL +Q 0 +S 22,INTERNAL +Q 0 +S 21,INTERNAL +Q 0 +S 20,INTERNAL +Q 0 +S 19,EXTERNAL,vdd +Q 0.0144679 +S 18,INTERNAL +Q 0 +S 17,EXTERNAL,q +Q 0.00615082 +S 16,INTERNAL,sff_s +Q 0.0067122 +S 15,INTERNAL,y +Q 0.00480814 +S 14,INTERNAL,sff_m +Q 0.00642301 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0 +S 11,EXTERNAL,ck +Q 0.0031591 +S 10,INTERNAL,nckr +Q 0.011396 +S 9,INTERNAL,ckr +Q 0.0110493 +S 8,EXTERNAL,i1 +Q 0.00242923 +S 7,EXTERNAL,i0 +Q 0.0031591 +S 6,EXTERNAL,cmd +Q 0.00541426 +S 5,INTERNAL +Q 0.00654862 +S 4,INTERNAL +Q 0 +S 3,INTERNAL,u +Q 0.00667128 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.0131165 +EOF diff --git a/pdks/symbolic/sxlib/cells/sff2_x4.ap b/pdks/symbolic/sxlib/cells/sff2_x4.ap new file mode 100644 index 000000000..b4ff1761f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff2_x4.ap @@ -0,0 +1,259 @@ +V ALLIANCE : 6 +H sff2_x4,P,18/ 5/2002,100 +A 0,0,12000,5000 +R 11000,2000,ref_ref,q_20 +R 11000,4000,ref_ref,q_40 +R 11000,3500,ref_ref,q_35 +R 11000,3000,ref_ref,q_30 +R 11000,2500,ref_ref,q_25 +R 11000,1500,ref_ref,q_15 +R 11000,1000,ref_ref,q_10 +R 1500,4000,ref_ref,cmd_40 +R 1500,3500,ref_ref,cmd_35 +R 1500,3000,ref_ref,cmd_30 +R 1500,2500,ref_ref,cmd_25 +R 3000,3500,ref_ref,i1_35 +R 3000,3000,ref_ref,i1_30 +R 3000,2500,ref_ref,i1_25 +R 3000,2000,ref_ref,i1_20 +R 3000,1500,ref_ref,i1_15 +R 3000,1000,ref_ref,i1_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3000,ref_ref,i0_30 +R 1000,3500,ref_ref,i0_35 +R 1000,2500,ref_ref,i0_25 +R 1000,2000,ref_ref,i0_20 +R 1000,1500,ref_ref,i0_15 +R 4500,1500,ref_ref,ck_15 +R 4500,2000,ref_ref,ck_20 +R 4500,2500,ref_ref,ck_25 +R 4500,3000,ref_ref,ck_30 +R 4500,3500,ref_ref,ck_35 +R 4500,1000,ref_ref,ck_10 +S 11000,1000,11000,4000,200,q,DOWN,CALU1 +S 1500,2500,1500,4000,200,cmd,DOWN,CALU1 +S 3000,1000,3000,3500,200,i1,DOWN,CALU1 +S 1000,1500,1000,4000,200,i0,DOWN,CALU1 +S 4500,1000,4500,3500,200,ck,DOWN,CALU1 +S 10400,2000,11400,2000,300,*,RIGHT,POLY +S 9900,2000,10400,2000,100,*,RIGHT,ALU1 +S 10200,2400,10200,3600,100,*,DOWN,POLY +S 9900,1000,9900,4000,100,sff_s,DOWN,ALU1 +S 7500,1000,7500,3500,100,sff_m,DOWN,ALU1 +S 6500,1500,6500,2500,100,*,DOWN,ALU1 +S 6500,3000,7000,3000,100,*,RIGHT,ALU1 +S 7000,2000,7000,3000,100,*,UP,ALU1 +S 6000,1500,6000,4000,100,u,DOWN,ALU1 +S 6900,3500,7500,3500,100,*,RIGHT,ALU1 +S 9300,4000,9900,4000,100,*,RIGHT,ALU1 +S 7500,1500,8200,1500,100,*,LEFT,ALU1 +S 9300,2000,9300,3500,100,*,DOWN,ALU1 +S 7500,3000,8200,3000,100,*,RIGHT,ALU1 +S 10400,1500,11100,1500,100,*,RIGHT,ALU1 +S 10400,2500,11100,2500,100,*,RIGHT,ALU1 +S 10500,3000,10500,4500,200,*,DOWN,ALU1 +S 11700,3000,11700,4500,200,*,DOWN,ALU1 +S 8000,3500,8700,3500,100,*,LEFT,ALU1 +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 1500,2500,1500,4000,100,*,DOWN,ALU1 +S 2000,4000,6000,4000,100,*,RIGHT,ALU1 +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 0,4700,12000,4700,600,vdd,RIGHT,CALU1 +S 10500,500,10500,1000,200,*,DOWN,ALU1 +S 11700,500,11700,1000,200,*,DOWN,ALU1 +S 9300,1000,9900,1000,100,*,RIGHT,ALU1 +S 6900,1000,7500,1000,100,*,RIGHT,ALU1 +S 8000,1000,8700,1000,100,*,RIGHT,ALU1 +S 3900,1000,3900,3500,100,*,DOWN,ALU1 +S 3000,1000,3000,3500,100,*,DOWN,ALU1 +S 8700,1000,8700,4000,100,y,DOWN,ALU1 +S 1500,1000,1500,2000,100,*,UP,ALU1 +S 2500,1000,2500,3000,100,*,DOWN,ALU1 +S 5100,1000,5100,3500,100,*,DOWN,ALU1 +S 4500,1000,4500,3500,100,*,DOWN,ALU1 +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 0,300,12000,300,600,vss,RIGHT,CALU1 +S 8100,3000,8400,3000,300,*,RIGHT,POLY +S 9300,3500,9600,3500,300,*,RIGHT,POLY +S 7800,3500,8100,3500,300,*,RIGHT,POLY +S 8100,1500,8400,1500,300,*,RIGHT,POLY +S 7200,2500,7200,3100,100,*,DOWN,POLY +S 11400,1400,11400,2600,100,*,DOWN,POLY +S 9000,1400,9000,2000,100,*,DOWN,POLY +S 8400,3000,8400,3600,100,*,DOWN,POLY +S 9000,2500,9000,3600,100,*,DOWN,POLY +S 7200,1400,7200,2000,100,*,DOWN,POLY +S 9000,2000,9300,2000,300,*,RIGHT,POLY +S 6900,2000,7200,2000,300,*,RIGHT,POLY +S 4200,1500,4500,1500,300,*,RIGHT,POLY +S 4800,1400,4800,3100,100,*,DOWN,POLY +S 9600,1400,9600,2500,100,*,DOWN,POLY +S 10800,1400,10800,2600,100,*,DOWN,POLY +S 10200,1500,10500,1500,300,*,RIGHT,POLY +S 10200,2500,10500,2500,300,*,RIGHT,POLY +S 3900,2500,9600,2500,100,nckr,RIGHT,POLY +S 5100,2000,9000,2000,100,ckr,RIGHT,POLY +S 4200,3000,4500,3000,300,*,RIGHT,POLY +S 1600,2500,1600,3100,100,*,DOWN,POLY +S 1600,1400,1600,2000,100,*,DOWN,POLY +S 2500,1400,2500,2500,100,*,DOWN,POLY +S 900,3000,1200,3000,300,*,RIGHT,POLY +S 900,1500,1200,1500,300,*,RIGHT,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 600,2500,2500,2500,100,*,RIGHT,POLY +S 8400,900,8400,1500,100,*,UP,POLY +S 7800,1000,8100,1000,300,*,RIGHT,POLY +S 5700,3800,5700,4700,300,*,UP,PDIF +S 6300,3300,6300,4700,300,*,UP,PDIF +S 6900,3300,6900,4200,300,*,UP,PDIF +S 7500,3300,7500,4700,300,*,UP,PDIF +S 10800,2600,10800,4900,100,*,DOWN,PTRANS +S 10500,2800,10500,4700,300,*,DOWN,PDIF +S 6000,3600,6000,4900,100,*,DOWN,PTRANS +S 9900,3800,9900,4700,300,*,UP,PDIF +S 8400,3600,8400,4900,100,*,UP,PTRANS +S 11100,2800,11100,4700,300,*,DOWN,PDIF +S 11400,2600,11400,4900,100,*,DOWN,PTRANS +S 11700,2800,11700,4700,300,*,DOWN,PDIF +S 4500,3300,4500,4600,300,*,UP,PDIF +S 8600,3800,8600,4700,300,*,DOWN,PDIF +S 9300,3800,9300,4700,300,*,DOWN,PDIF +S 8000,3800,8000,4700,300,*,DOWN,PDIF +S 3900,3300,3900,4200,300,*,UP,PDIF +S 4200,3100,4200,4400,100,*,DOWN,PTRANS +S 4800,3100,4800,4400,100,*,DOWN,PTRANS +S 5100,3300,5100,4200,300,*,UP,PDIF +S 2500,3100,2500,4400,100,*,DOWN,PTRANS +S 3200,3300,3200,4600,300,*,DOWN,PDIF +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 2900,3100,2900,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 900,3300,900,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 6900,800,6900,1200,300,*,DOWN,NDIF +S 7500,300,7500,1200,300,*,DOWN,NDIF +S 6300,800,6300,1200,300,*,DOWN,NDIF +S 6000,600,6000,1400,100,*,UP,NTRANS +S 5700,400,5700,1200,300,*,DOWN,NDIF +S 9900,800,9900,1200,300,*,DOWN,NDIF +S 10800,100,10800,1400,100,*,UP,NTRANS +S 9300,800,9300,1200,300,*,DOWN,NDIF +S 8700,300,8700,1200,300,*,DOWN,NDIF +S 10500,300,10500,1200,300,*,DOWN,NDIF +S 11100,300,11100,1200,300,*,DOWN,NDIF +S 11400,100,11400,1400,100,*,UP,NTRANS +S 11700,300,11700,1200,300,*,DOWN,NDIF +S 8400,100,8400,900,100,*,UP,NTRANS +S 8700,300,8700,700,300,*,DOWN,NDIF +S 8100,300,8100,700,300,*,DOWN,NDIF +S 5100,800,5100,1200,300,*,DOWN,NDIF +S 4200,600,4200,1400,100,*,UP,NTRANS +S 3900,800,3900,1200,300,*,DOWN,NDIF +S 4500,400,4500,1200,300,*,DOWN,NDIF +S 4800,600,4800,1400,100,*,UP,NTRANS +S 2100,800,2100,1600,500,*,DOWN,NDIF +S 2900,600,2900,1400,100,*,UP,NTRANS +S 3200,400,3200,1200,300,*,UP,NDIF +S 1600,600,1600,1400,100,*,UP,NTRANS +S 1900,800,1900,1200,300,*,UP,NDIF +S 2500,600,2500,1400,100,*,UP,NTRANS +S 1200,600,1200,1400,100,*,UP,NTRANS +S 600,600,600,1400,100,*,UP,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 900,400,900,1200,300,*,UP,NDIF +S 0,3900,12000,3900,2400,*,RIGHT,NWELL +S 1500,300,2500,300,300,*,RIGHT,PTIE +S 6300,300,6900,300,300,*,RIGHT,PTIE +S 9300,300,9900,300,300,*,RIGHT,PTIE +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 6600,600,6600,1400,100,*,UP,NTRANS +S 6600,3100,6600,4400,100,*,DOWN,PTRANS +S 7200,3100,7200,4400,100,*,DOWN,PTRANS +S 7800,3600,7800,4900,100,*,DOWN,PTRANS +S 7200,600,7200,1400,100,*,UP,NTRANS +S 7800,100,7800,900,100,*,UP,NTRANS +S 9000,600,9000,1400,100,*,UP,NTRANS +S 9000,3600,9000,4900,100,*,DOWN,PTRANS +S 9600,3600,9600,4900,100,*,DOWN,PTRANS +S 10200,3600,10200,4900,100,*,DOWN,PTRANS +S 9600,600,9600,1400,100,*,UP,NTRANS +S 10200,600,10200,1400,100,*,UP,NTRANS +S 11000,1000,11000,4000,200,*,DOWN,ALU1 +V 10400,2000,CONT_POLY,* +V 3000,3000,CONT_POLY,* +V 6000,1500,CONT_POLY,* +V 6500,2500,CONT_POLY,* +V 6500,1500,CONT_POLY,* +V 6500,3000,CONT_POLY,* +V 10400,2500,CONT_POLY,* +V 10400,1500,CONT_POLY,* +V 8200,1500,CONT_POLY,* +V 9200,2000,CONT_POLY,* +V 8200,3000,CONT_POLY,* +V 7000,2000,CONT_POLY,* +V 9400,3500,CONT_POLY,* +V 5900,3500,CONT_POLY,* +V 5200,2000,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 4400,3000,CONT_POLY,* +V 4400,1500,CONT_POLY,* +V 8000,3500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,3000,CONT_POLY,* +V 1000,3000,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 8000,1000,CONT_POLY,* +V 2500,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 6300,300,CONT_BODY_P,* +V 6900,300,CONT_BODY_P,* +V 9300,300,CONT_BODY_P,* +V 9900,300,CONT_BODY_P,* +V 1500,4700,CONT_BODY_N,* +V 2500,4700,CONT_BODY_N,* +V 11100,3500,CONT_DIF_P,* +V 6900,3500,CONT_DIF_P,* +V 10500,3500,CONT_DIF_P,* +V 10500,4000,CONT_DIF_P,* +V 11700,4500,CONT_DIF_P,* +V 10500,4500,CONT_DIF_P,* +V 11700,4000,CONT_DIF_P,* +V 11700,3500,CONT_DIF_P,* +V 5700,4500,CONT_DIF_P,* +V 11100,4000,CONT_DIF_P,* +V 2000,3500,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 9300,4000,CONT_DIF_P,* +V 8100,4500,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 11700,3000,CONT_DIF_P,* +V 11100,3000,CONT_DIF_P,* +V 10500,3000,CONT_DIF_P,* +V 3200,4500,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 2000,1500,CONT_DIF_N,* +V 5700,500,CONT_DIF_N,* +V 8100,500,CONT_DIF_N,* +V 6900,1000,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 11700,500,CONT_DIF_N,* +V 10500,500,CONT_DIF_N,* +V 11700,1000,CONT_DIF_N,* +V 10500,1000,CONT_DIF_N,* +V 11100,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 9300,1000,CONT_DIF_N,* +V 3200,500,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 4000,2500,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/sff2_x4.sym b/pdks/symbolic/sxlib/cells/sff2_x4.sym new file mode 100644 index 000000000..343c26257 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/sff2_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/sff2_x4.vbe b/pdks/symbolic/sxlib/cells/sff2_x4.vbe new file mode 100644 index 000000000..59eaa6446 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff2_x4.vbe @@ -0,0 +1,51 @@ +ENTITY sff2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 6000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd : NATURAL := 16; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 7; + CONSTANT rdown_ck_q : NATURAL := 800; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_cmd_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thr_cmd_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT tsf_cmd_ck : NATURAL := 833; + CONSTANT tsf_i0_ck : NATURAL := 764; + CONSTANT tsf_i1_ck : NATURAL := 764; + CONSTANT tsr_cmd_ck : NATURAL := 770; + CONSTANT tsr_i0_ck : NATURAL := 666; + CONSTANT tsr_i1_ck : NATURAL := 666; + CONSTANT transistors : NATURAL := 34 +); +PORT ( + ck : in BIT; + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff2_x4; + +ARCHITECTURE VBE OF sff2_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff2_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd))); + END BLOCK label0; + + q <= sff_m after 2000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/sff2_x4.vhd b/pdks/symbolic/sxlib/cells/sff2_x4.vhd new file mode 100644 index 000000000..f49ef60e7 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff2_x4.vhd @@ -0,0 +1,29 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY sff2_x4 IS +PORT( + ck : IN STD_LOGIC; + cmd : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END sff2_x4; + +ARCHITECTURE RTL OF sff2_x4 IS + SIGNAL sff_m : STD_LOGIC; +BEGIN + q <= sff_m; + PROCESS ( ck ) + BEGIN + IF ((ck = '1') AND ck'EVENT) + THEN sff_m <= ((i1 AND cmd) OR (i0 AND NOT(cmd))); + END IF; + END PROCESS; +END RTL; diff --git a/pdks/symbolic/sxlib/cells/sff3_x4.al b/pdks/symbolic/sxlib/cells/sff3_x4.al new file mode 100644 index 000000000..fbf02fa2c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff3_x4.al @@ -0,0 +1,116 @@ +V ALLIANCE : 6 +H sff3_x4,L,30/10/99 +C ck,IN,EXTERNAL,15 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,8 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,24 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,6,13,28,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00042 +T P,0.35,2,7,14,12,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00041 +T P,0.35,2.9,28,14,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00040 +T P,0.35,2.9,7,12,27,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00039 +T P,0.35,2.9,27,9,25,0,0.75,0.75,7.3,7.3,9,12.75,tr_00038 +T P,0.35,2.9,25,2,6,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00037 +T P,0.35,2,2,8,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00036 +T P,0.35,2.9,6,8,26,0,0.75,0.75,7.3,7.3,6,12.75,tr_00035 +T P,0.35,2.9,26,10,27,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00034 +T P,0.35,2.9,22,19,21,0,0.75,0.75,7.3,7.3,33,12.75,tr_00033 +T P,0.35,2.9,31,22,7,0,0.75,0.75,7.3,7.3,29.4,12.75,tr_00032 +T P,0.35,2.9,16,19,31,0,0.75,0.75,7.3,7.3,27.6,11.25,tr_00031 +T P,0.35,2.9,30,24,7,0,0.75,0.75,7.3,7.3,36.6,12.75,tr_00030 +T P,0.35,2.9,21,18,30,0,0.75,0.75,7.3,7.3,34.8,12.75,tr_00029 +T P,0.35,5.9,24,21,7,0,0.75,0.75,13.3,13.3,40.2,11.25,tr_00028 +T P,0.35,2.9,22,16,7,0,0.75,0.75,7.3,7.3,31.2,12.75,tr_00027 +T P,0.35,2.9,29,18,16,0,0.75,0.75,7.3,7.3,25.8,11.25,tr_00026 +T P,0.35,5.9,7,21,24,0,0.75,0.75,13.3,13.3,38.4,11.25,tr_00025 +T P,0.35,2.9,7,6,29,0,0.75,0.75,7.3,7.3,24,11.25,tr_00024 +T P,0.35,2.9,18,19,7,0,0.75,0.75,7.3,7.3,22.2,11.25,tr_00023 +T P,0.35,2.9,7,15,19,0,0.75,0.75,7.3,7.3,18.3,11.25,tr_00022 +T N,0.35,1.1,12,14,1,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00021 +T N,0.35,1.1,1,8,2,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00020 +T N,0.35,1.7,6,13,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00019 +T N,0.35,1.7,1,14,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00018 +T N,0.35,1.7,11,12,1,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00017 +T N,0.35,1.7,6,2,3,0,0.75,0.75,4.9,4.9,6,2.55,tr_00016 +T N,0.35,1.7,5,8,6,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00015 +T N,0.35,1.7,4,9,5,0,0.75,0.75,4.9,4.9,9,2.55,tr_00014 +T N,0.35,1.7,3,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00013 +T N,0.35,1.4,16,19,17,0,0.75,0.75,4.3,4.3,25.8,3,tr_00012 +T N,0.35,1.4,1,24,20,0,0.75,0.75,4.3,4.3,36.6,3,tr_00011 +T N,0.35,1.4,20,19,21,0,0.75,0.75,4.3,4.3,34.8,3,tr_00010 +T N,0.35,1.4,21,18,22,0,0.75,0.75,4.3,4.3,33,3,tr_00009 +T N,0.35,1.4,1,22,23,0,0.75,0.75,4.3,4.3,29.4,1.5,tr_00008 +T N,0.35,1.4,23,18,16,0,0.75,0.75,4.3,4.3,27.6,3,tr_00007 +T N,0.35,1.4,22,16,1,0,0.75,0.75,4.3,4.3,31.2,1.5,tr_00006 +T N,0.35,2.9,24,21,1,0,0.75,0.75,7.3,7.3,38.4,2.25,tr_00005 +T N,0.35,2.9,1,21,24,0,0.75,0.75,7.3,7.3,40.2,2.25,tr_00004 +T N,0.35,1.4,17,6,1,0,0.75,0.75,4.3,4.3,24,3,tr_00003 +T N,0.35,1.4,1,19,18,0,0.75,0.75,4.3,4.3,22.2,3,tr_00002 +T N,0.35,1.4,19,15,1,0,0.75,0.75,4.3,4.3,18.3,3,tr_00001 +S 31,INTERNAL +Q 0 +S 30,INTERNAL +Q 0 +S 29,INTERNAL +Q 0 +S 28,INTERNAL +Q 0 +S 27,INTERNAL +Q 0.00170541 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0 +S 24,EXTERNAL,q +Q 0.00615082 +S 23,INTERNAL +Q 0 +S 22,INTERNAL,y +Q 0.00480814 +S 21,INTERNAL,sff_s +Q 0.00671219 +S 20,INTERNAL +Q 0 +S 19,INTERNAL,nckr +Q 0.0114885 +S 18,INTERNAL,ckr +Q 0.0113072 +S 17,INTERNAL +Q 0 +S 16,INTERNAL,sff_m +Q 0.00642301 +S 15,EXTERNAL,ck +Q 0.00323647 +S 14,EXTERNAL,cmd0 +Q 0.00553121 +S 13,EXTERNAL,i0 +Q 0.00386191 +S 12,INTERNAL +Q 0.0057783 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,i1 +Q 0.0025589 +S 8,EXTERNAL,cmd1 +Q 0.00604152 +S 7,EXTERNAL,vdd +Q 0.0159513 +S 6,INTERNAL,u +Q 0.0112516 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00547335 +S 1,EXTERNAL,vss +Q 0.0145999 +EOF diff --git a/pdks/symbolic/sxlib/cells/sff3_x4.ap b/pdks/symbolic/sxlib/cells/sff3_x4.ap new file mode 100644 index 000000000..2fe227d42 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff3_x4.ap @@ -0,0 +1,337 @@ +V ALLIANCE : 6 +H sff3_x4,P,13/ 6/2002,100 +A 0,0,14000,5000 +R 6000,1000,ref_ref,ck_10 +R 6000,3500,ref_ref,ck_35 +R 6000,3000,ref_ref,ck_30 +R 6000,2500,ref_ref,ck_25 +R 6000,1500,ref_ref,ck_15 +R 6000,2000,ref_ref,ck_20 +R 13000,1000,ref_ref,q_10 +R 13000,3000,ref_ref,q_30 +R 13000,2500,ref_ref,q_25 +R 13000,1500,ref_ref,q_15 +R 13000,2000,ref_ref,q_20 +R 13000,4000,ref_ref,q_40 +R 13000,3500,ref_ref,q_35 +R 500,1500,ref_ref,cmd1_15 +R 500,2000,ref_ref,cmd1_20 +R 500,2500,ref_ref,cmd1_25 +R 500,3000,ref_ref,cmd1_30 +R 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2300,3500,2300,4700,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 500,2800,500,4000,300,*,UP,PDIF +S 800,2600,800,3600,100,*,UP,PTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 4900,2800,4900,3400,300,*,UP,PDIF +S 3300,3800,3300,4700,200,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 3900,3800,3900,4700,200,*,UP,PDIF +S 4900,3800,4900,4700,300,*,UP,PDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 1400,400,1400,1300,100,*,UP,NTRANS +S 3000,400,3000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 4200,200,4200,1100,100,*,UP,NTRANS +S 3900,400,3900,900,200,*,DOWN,NDIF +S 3600,200,3600,1100,100,*,UP,NTRANS +S 4900,500,4900,1000,300,*,UP,NDIF +S 4600,200,4600,1100,100,*,UP,NTRANS +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 5200,1300,5200,2000,100,*,DOWN,NTRANS +S 4900,1500,4900,1700,300,*,DOWN,NDIF +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 2600,3000,2600,3600,100,*,UP,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 500,2500,800,2500,300,*,RIGHT,POLY +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 4000,3300,4000,3600,100,*,UP,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 5200,2000,5200,2600,100,*,DOWN,POLY +S 4200,1100,4200,1500,100,*,UP,POLY +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 3500,1500,3500,3600,100,*,UP,POLY +S 1100,1000,3300,1000,100,*,RIGHT,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 4400,2000,4400,3000,100,*,UP,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 4900,1500,4900,1700,200,*,DOWN,ALU1 +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 6000,1000,6000,3500,200,ck,DOWN,CALU1 +S 13000,1000,13000,4000,200,q,DOWN,CALU1 +S 500,1500,500,3500,200,cmd1,DOWN,CALU1 +S 1500,2500,1500,2500,200,i2,LEFT,CALU1 +S 2500,2500,2500,2500,200,i1,LEFT,CALU1 +S 3500,2000,3500,3000,200,cmd0,DOWN,CALU1 +S 4500,2500,4500,2500,200,i0,LEFT,CALU1 +S 4000,3000,4000,3000,200,i0,LEFT,CALU1 +S 4000,2000,4000,2000,200,i0,LEFT,CALU1 +S 13000,1000,13000,4000,200,*,DOWN,ALU1 +S 1800,1500,2000,1500,300,*,RIGHT,POLY +S 1800,3500,2000,3500,300,*,RIGHT,POLY +S 4400,2000,4600,2000,300,*,RIGHT,POLY +S 4400,3000,4600,3000,300,*,RIGHT,POLY +V 1100,1600,CONT_DIF_N,* +V 8300,4700,CONT_BODY_N,* +V 6400,300,CONT_BODY_P,* +V 6400,4700,CONT_BODY_N,* +V 6500,3500,CONT_DIF_P,* +V 6500,1000,CONT_DIF_N,* +V 6600,2500,CONT_POLY,* +V 6000,2500,CONT_POLY,* +V 7700,4600,CONT_DIF_P,* +V 7100,4700,CONT_BODY_N,* +V 11300,4000,CONT_DIF_P,* +V 8900,4700,CONT_BODY_N,* +V 13100,3500,CONT_DIF_P,* +V 8900,3500,CONT_DIF_P,* +V 12500,3500,CONT_DIF_P,* +V 12500,4000,CONT_DIF_P,* +V 13700,4500,CONT_DIF_P,* +V 7100,3500,CONT_DIF_P,* +V 12500,4500,CONT_DIF_P,* +V 13700,4000,CONT_DIF_P,* +V 13700,3500,CONT_DIF_P,* +V 13100,4000,CONT_DIF_P,* +V 10100,4500,CONT_DIF_P,* +V 10700,4000,CONT_DIF_P,* +V 13700,3000,CONT_DIF_P,* +V 13100,3000,CONT_DIF_P,* +V 12500,3000,CONT_DIF_P,* +V 7700,500,CONT_DIF_N,* +V 10100,500,CONT_DIF_N,* +V 11300,1000,CONT_DIF_N,* +V 8900,1000,CONT_DIF_N,* +V 10700,1000,CONT_DIF_N,* +V 13700,500,CONT_DIF_N,* +V 12500,500,CONT_DIF_N,* +V 13700,1000,CONT_DIF_N,* +V 12500,1000,CONT_DIF_N,* +V 13100,1000,CONT_DIF_N,* +V 7100,1000,CONT_DIF_N,* +V 8300,300,CONT_BODY_P,* +V 11900,300,CONT_BODY_P,* +V 11300,300,CONT_BODY_P,* +V 8900,300,CONT_BODY_P,* +V 7100,300,CONT_BODY_P,* +V 10000,1000,CONT_POLY,* +V 8000,1500,CONT_POLY,* +V 8600,1500,CONT_POLY,* +V 8000,3000,CONT_POLY,* +V 8600,3000,CONT_POLY,* +V 7500,2000,CONT_POLY,* +V 12400,2000,CONT_POLY,* +V 8500,2500,CONT_POLY,* +V 12400,2500,CONT_POLY,* +V 12400,1500,CONT_POLY,* +V 10200,1500,CONT_POLY,* +V 11200,2000,CONT_POLY,* +V 10200,3000,CONT_POLY,* +V 9000,2000,CONT_POLY,* +V 11400,3500,CONT_POLY,* +V 10000,3500,CONT_POLY,* +V 500,4000,CONT_DIF_P,* +V 1100,3000,CONT_DIF_P,* +V 1100,4000,CONT_DIF_P,* +V 2300,3500,CONT_DIF_P,* +V 4900,3000,CONT_DIF_P,* +V 4900,4000,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 1100,1000,CONT_DIF_N,* +V 500,1000,CONT_DIF_N,* +V 5500,500,CONT_DIF_N,* +V 4900,1000,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 2300,1500,CONT_DIF_N,* +V 4900,1700,CONT_DIF_N,* +V 1800,3500,CONT_POLY,* +V 1800,1500,CONT_POLY,* +V 500,2500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 1500,2500,CONT_POLY,* +V 2500,3000,CONT_POLY,* +V 3400,1500,CONT_POLY,* +V 4200,1500,CONT_POLY,* +V 3900,2500,CONT_POLY,* +V 4400,2000,CONT_POLY,* +V 4400,3000,CONT_POLY,* +V 5500,4500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/sff3_x4.vbe b/pdks/symbolic/sxlib/cells/sff3_x4.vbe new file mode 100644 index 000000000..a1953ab9f --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff3_x4.vbe @@ -0,0 +1,65 @@ +ENTITY sff3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 890; + CONSTANT rup_ck_q : NATURAL := 810; + CONSTANT taf_ck_q : NATURAL := 600; + CONSTANT tar_ck_q : NATURAL := 600; + CONSTANT thf_ck_q : NATURAL := 0; + CONSTANT thf_cmd0_ck : NATURAL := 0; + CONSTANT thf_cmd1_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thf_i2_ck : NATURAL := 0; + CONSTANT thr_ck_q : NATURAL := 0; + CONSTANT thr_cmd0_ck : NATURAL := 0; + CONSTANT thr_cmd1_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT thr_i2_ck : NATURAL := 0; + CONSTANT tsf_cmd0_ck : NATURAL := 1200; + CONSTANT tsf_cmd1_ck : NATURAL := 1200; + CONSTANT tsf_i0_ck : NATURAL := 1200; + CONSTANT tsf_i1_ck : NATURAL := 1200; + CONSTANT tsf_i2_ck : NATURAL := 1200; + CONSTANT tsr_cmd0_ck : NATURAL := 1100; + CONSTANT tsr_cmd1_ck : NATURAL := 1100; + CONSTANT tsr_i0_ck : NATURAL := 850; + CONSTANT tsr_i1_ck : NATURAL := 950; + CONSTANT tsr_i2_ck : NATURAL := 950; + CONSTANT transistors : NATURAL := 42 +); +PORT ( + ck : in BIT; + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff3_x4; + +ARCHITECTURE behaviour_data_flow OF sff3_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on sff3_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2)))); + END BLOCK label0; + + q <= sff_m after 2400 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/sff3_x4.vhd b/pdks/symbolic/sxlib/cells/sff3_x4.vhd new file mode 100644 index 000000000..a99d02f2c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sff3_x4.vhd @@ -0,0 +1,31 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY sff3_x4 IS +PORT( + ck : IN STD_LOGIC; + cmd0 : IN STD_LOGIC; + cmd1 : IN STD_LOGIC; + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + i2 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END sff3_x4; + +ARCHITECTURE RTL OF sff3_x4 IS + SIGNAL sff_m : STD_LOGIC; +BEGIN + q <= sff_m; + PROCESS ( ck ) + BEGIN + IF ((ck = '1') AND ck'EVENT) + THEN sff_m <= ((NOT(cmd0) AND i0) OR (cmd0 AND ((cmd1 AND i1) OR (NOT(cmd1) AND i2)))); + END IF; + END PROCESS; +END RTL; diff --git a/pdks/symbolic/sxlib/cells/sxlib.cct b/pdks/symbolic/sxlib/cells/sxlib.cct new file mode 100644 index 000000000..c13bceff9 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sxlib.cct @@ -0,0 +1,1018 @@ +Circuit a2_x2 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 and i1) ; +EndCircuit +Circuit a2_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 and i1) ; +EndCircuit +Circuit a3_x2 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) and i2) ; +EndCircuit +Circuit a3_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) and i2) ; +EndCircuit +Circuit a4_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) and i3) ; +EndCircuit +Circuit a4_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) and i3) ; +EndCircuit +Circuit an12_x1 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 and i1) ; +EndCircuit +Circuit an12_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 and i1) ; +EndCircuit +Circuit ao22_x2 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) and i2) ; +EndCircuit +Circuit ao22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) and i2) ; +EndCircuit +Circuit ao2o22_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) and (i2 or i3)) ; +EndCircuit +Circuit ao2o22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) and (i2 or i3)) ; +EndCircuit +Circuit buf_x2 ( + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := i ; +EndCircuit +Circuit buf_x4 ( + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := i ; +EndCircuit +Circuit buf_x8 ( + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := i ; +EndCircuit +Circuit fulladder_x2 ( + Input a1 , + Input a2 , + Input a3 , + Input a4 , + Input b1 , + Input b2 , + Input b3 , + Input b4 , + Input cin1 , + Input cin2 , + Input cin3 , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE ncout := not ((a1 and b1) or ((a2 or b2) and cin1)) ; +WIRE sout := (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) ; +WIRE cout := not ncout ; +EndCircuit +Circuit fulladder_x4 ( + Input a1 , + Input a2 , + Input a3 , + Input a4 , + Input b1 , + Input b2 , + Input b3 , + Input b4 , + Input cin1 , + Input cin2 , + Input cin3 , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE ncout := not ((a1 and b1) or ((a2 or b2) and cin1)) ; +WIRE sout := (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) ; +WIRE cout := not ncout ; +EndCircuit +Circuit halfadder_x2 ( + Input a , + Input b , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE sout := (a xor b) ; +WIRE cout := (a and b) ; +EndCircuit +Circuit halfadder_x4 ( + Input a , + Input b , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE sout := (a xor b) ; +WIRE cout := (a and b) ; +EndCircuit +Circuit inv_x1 ( + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not i ; +EndCircuit +Circuit inv_x2 ( + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not i ; +EndCircuit +Circuit inv_x4 ( + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not i ; +EndCircuit +Circuit inv_x8 ( + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not i ; +EndCircuit +Circuit mx2_x2 ( + Input cmd , + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i1 and cmd) or (not cmd and i0)) ; +EndCircuit +Circuit mx2_x4 ( + Input cmd , + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i1 and cmd) or (not cmd and i0)) ; +EndCircuit +Circuit mx3_x2 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit mx3_x4 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit na2_x1 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 and i1) ; +EndCircuit +Circuit na2_x4 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 and i1) ; +EndCircuit +Circuit na3_x1 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) and i2) ; +EndCircuit +Circuit na3_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) and i2) ; +EndCircuit +Circuit na4_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) and i3) ; +EndCircuit +Circuit na4_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) and i3) ; +EndCircuit +Circuit nao22_x1 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) and i2) ; +EndCircuit +Circuit nao22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) and i2) ; +EndCircuit +Circuit nao2o22_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) and (i2 or i3)) ; +EndCircuit +Circuit nao2o22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) and (i2 or i3)) ; +EndCircuit +Circuit nmx2_x1 ( + Input cmd , + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and not cmd) or (i1 and cmd)) ; +EndCircuit +Circuit nmx2_x4 ( + Input cmd , + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and not cmd) or (i1 and cmd)) ; +EndCircuit +Circuit nmx3_x1 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit nmx3_x4 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit no2_x1 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 or i1) ; +EndCircuit +Circuit no2_x4 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 or i1) ; +EndCircuit +Circuit no3_x1 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) or i2) ; +EndCircuit +Circuit no3_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 or i1) or i2) ; +EndCircuit +Circuit no4_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 or i1) or i2) or i3) ; +EndCircuit +Circuit no4_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 or i1) or i2) or i3) ; +EndCircuit +Circuit noa22_x1 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or i2) ; +EndCircuit +Circuit noa22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or i2) ; +EndCircuit +Circuit noa2a22_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or (i2 and i3)) ; +EndCircuit +Circuit noa2a22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or (i2 and i3)) ; +EndCircuit +Circuit noa2a2a23_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit noa2a2a23_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit noa2a2a2a24_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit noa2a2a2a24_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit noa2ao222_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or ((i2 or i3) and i4)) ; +EndCircuit +Circuit noa2ao222_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or ((i2 or i3) and i4)) ; +EndCircuit +Circuit noa3ao322_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) or (((i3 or i4) or i5) and i6)) ; +EndCircuit +Circuit noa3ao322_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) or (((i3 or i4) or i5) and i6)) ; +EndCircuit +Circuit nts_x1 ( + Input cmd , + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE commande_0_nq := cmd ; +WIRE data_0_nq := not i ; +TRI1 nq ; + BUFIF1 tri_0_nq (nq,data_0_nq,commande_0_nq) ; +EndCircuit +Circuit nts_x2 ( + Input cmd , + Input i , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE commande_0_nq := cmd ; +WIRE data_0_nq := not i ; +TRI1 nq ; + BUFIF1 tri_0_nq (nq,data_0_nq,commande_0_nq) ; +EndCircuit +Circuit nxr2_x1 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 xor i1) ; +EndCircuit +Circuit nxr2_x4 ( + Input i0 , + Input i1 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (i0 xor i1) ; +EndCircuit +Circuit o2_x2 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 or i1) ; +EndCircuit +Circuit o2_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 or i1) ; +EndCircuit +Circuit o3_x2 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) or i2) ; +EndCircuit +Circuit o3_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 or i1) or i2) ; +EndCircuit +Circuit o4_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 or i1) or i2) or i3) ; +EndCircuit +Circuit o4_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 or i1) or i2) or i3) ; +EndCircuit +Circuit oa22_x2 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or i2) ; +EndCircuit +Circuit oa22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or i2) ; +EndCircuit +Circuit oa2a22_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i2 and i3)) ; +EndCircuit +Circuit oa2a22_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i2 and i3)) ; +EndCircuit +Circuit oa2a2a23_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit oa2a2a23_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit oa2a2a2a24_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit oa2a2a2a24_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit oa2ao222_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i4 and (i2 or i3))) ; +EndCircuit +Circuit oa2ao222_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i4 and (i2 or i3))) ; +EndCircuit +Circuit oa3ao322_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) ; +EndCircuit +Circuit oa3ao322_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) ; +EndCircuit +Circuit on12_x1 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 or i1) ; +EndCircuit +Circuit on12_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 or i1) ; +EndCircuit +Circuit one_x0 ( + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := 1 ; +EndCircuit +Circuit rowend_x0 ( + Supply1 vdd , + Supply0 vss + ); +EndCircuit +Circuit sff1_x4 ( + Input ck , + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE sff_m_bcond_0 := ck ; +REGISTER (1,1) sff_m ; +WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := i ; +WIRE q := sff_m ; +EndCircuit +Circuit sff2_x4 ( + Input ck , + Input cmd , + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE sff_m_bcond_0 := ck ; +REGISTER (1,1) sff_m ; +WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := ((i1 and cmd) or (i0 and not cmd)) ; +WIRE q := sff_m ; +EndCircuit +Circuit sff3_x4 ( + Input ck , + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE sff_m_bcond_0 := ck ; +REGISTER (1,1) sff_m ; +WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +WIRE q := sff_m ; +EndCircuit +Circuit tie_x0 ( + Supply1 vdd , + Supply0 vss + ); +EndCircuit +Circuit ts_x4 ( + Input cmd , + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE commande_0_q := cmd ; +WIRE data_0_q := i ; +TRI1 q ; + BUFIF1 tri_0_q (q,data_0_q,commande_0_q) ; +EndCircuit +Circuit ts_x8 ( + Input cmd , + Input i , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE commande_0_q := cmd ; +WIRE data_0_q := i ; +TRI1 q ; + BUFIF1 tri_0_q (q,data_0_q,commande_0_q) ; +EndCircuit +Circuit xr2_x1 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 xor i1) ; +EndCircuit +Circuit xr2_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (i0 xor i1) ; +EndCircuit +Circuit zero_x0 ( + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := 0 ; +EndCircuit diff --git a/pdks/symbolic/sxlib/cells/sxlib.db b/pdks/symbolic/sxlib/cells/sxlib.db new file mode 100644 index 000000000..c7915a1b0 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/sxlib.db differ diff --git a/pdks/symbolic/sxlib/cells/sxlib.lef b/pdks/symbolic/sxlib/cells/sxlib.lef new file mode 100644 index 000000000..2fd72b8c5 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sxlib.lef @@ -0,0 +1,8085 @@ + +VERSION 5.2 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "()" ; +DIVIDERCHAR "." ; + + +MACRO a2_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END a2_x2 + + +MACRO a2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END a2_x4 + + +MACRO a3_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END a3_x2 + + +MACRO a3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END a3_x4 + + +MACRO a4_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END a4_x2 + + +MACRO a4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END a4_x4 + + +MACRO an12_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END an12_x1 + + +MACRO an12_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END an12_x4 + + +MACRO ao22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END ao22_x2 + + +MACRO ao22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END ao22_x4 + + +MACRO ao2o22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END ao2o22_x2 + + +MACRO ao2o22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END ao2o22_x4 + + +MACRO buf_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END buf_x2 + + +MACRO buf_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END buf_x4 + + +MACRO buf_x8 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END buf_x8 + + +MACRO fulladder_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 100.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + LAYER ALU1 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END cout + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END sout + PIN cin1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END cin1 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END a2 + PIN b2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END b2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END a3 + PIN b3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END b3 + PIN cin2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + END + END cin2 + PIN cin3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 84.00 29.00 86.00 31.00 ; + RECT 84.00 24.00 86.00 26.00 ; + RECT 84.00 19.00 86.00 21.00 ; + RECT 84.00 14.00 86.00 16.00 ; + END + END cin3 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a1 + PIN b1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END b1 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + END + END a4 + PIN b4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + END + END b4 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 97.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 97.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 98.50 41.00 ; + END +END fulladder_x2 + + +MACRO fulladder_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 105.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END sout + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END cout + PIN a1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a1 + PIN b1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END b1 + PIN cin1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END cin1 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END a2 + PIN b2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END b2 + PIN b4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + END + END b4 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + END + END a4 + PIN cin3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + END + END cin3 + PIN b3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + END + END b3 + PIN cin2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 74.00 14.00 76.00 16.00 ; + END + END cin2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + END + END a3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 102.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 102.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 103.50 41.00 ; + END +END fulladder_x4 + + +MACRO halfadder_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 80.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 74.00 39.00 76.00 41.00 ; + RECT 74.00 34.00 76.00 36.00 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 74.00 9.00 76.00 11.00 ; + END + END sout + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END cout + PIN b + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END b + PIN a + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END a + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 77.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 77.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 78.50 41.00 ; + END +END halfadder_x2 + + +MACRO halfadder_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 90.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN sout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END sout + PIN cout + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END cout + PIN b + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END b + PIN a + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END a + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 87.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 87.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 88.50 41.00 ; + END +END halfadder_x4 + + +MACRO inv_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END inv_x1 + + +MACRO inv_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END inv_x2 + + +MACRO inv_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END inv_x4 + + +MACRO inv_x8 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END inv_x8 + + +MACRO mx2_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END cmd + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END mx2_x2 + + +MACRO mx2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END cmd + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END mx2_x4 + + +MACRO mx3_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + LAYER ALU1 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + END + END q + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + LAYER ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END mx3_x2 + + +MACRO mx3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 70.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 19.00 66.00 21.00 ; + LAYER ALU1 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + LAYER ALU1 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + END + END q + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 67.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 67.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 68.50 41.00 ; + END +END mx3_x4 + + +MACRO na2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END na2_x1 + + +MACRO na2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END na2_x4 + + +MACRO na3_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END na3_x1 + + +MACRO na3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END na3_x4 + + +MACRO na4_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END na4_x1 + + +MACRO na4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END na4_x4 + + +MACRO nao22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END nao22_x1 + + +MACRO nao22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 14.00 26.00 16.00 ; + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END nao22_x4 + + +MACRO nao2o22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END nao2o22_x1 + + +MACRO nao2o22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END nao2o22_x4 + + +MACRO nmx2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + LAYER ALU1 ; + RECT 19.00 9.00 21.00 11.00 ; + LAYER ALU1 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END cmd + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END nmx2_x1 + + +MACRO nmx2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END cmd + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END nmx2_x4 + + +MACRO nmx3_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + LAYER ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i0 + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END nmx3_x1 + + +MACRO nmx3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 75.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END nq + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 72.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 72.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 73.50 41.00 ; + END +END nmx3_x4 + + +MACRO no2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 20.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 17.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 17.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 18.50 41.00 ; + END +END no2_x1 + + +MACRO no2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END no2_x4 + + +MACRO no3_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END no3_x1 + + +MACRO no3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END no3_x4 + + +MACRO no4_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END no4_x1 + + +MACRO no4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END nq + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END no4_x4 + + +MACRO noa22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END noa22_x1 + + +MACRO noa22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END noa22_x4 + + +MACRO noa2a22_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END noa2a22_x1 + + +MACRO noa2a22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END noa2a22_x4 + + +MACRO noa2a2a23_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nq + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END noa2a2a23_x1 + + +MACRO noa2a2a23_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i0 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END noa2a2a23_x4 + + +MACRO noa2a2a2a24_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 70.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 67.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 67.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 68.50 41.00 ; + END +END noa2a2a2a24_x1 + + +MACRO noa2a2a2a24_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 85.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + END + END nq + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 82.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 82.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 83.50 41.00 ; + END +END noa2a2a2a24_x4 + + +MACRO noa2ao222_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + LAYER ALU1 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END noa2ao222_x1 + + +MACRO noa2ao222_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END noa2ao222_x4 + + +MACRO noa3ao322_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i2 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i6 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i5 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END noa3ao322_x1 + + +MACRO noa3ao322_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i0 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END i3 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + END + END i5 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END i2 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i6 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END noa3ao322_x4 + + +MACRO nts_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END cmd + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END nts_x1 + + +MACRO nts_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END cmd + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END nts_x2 + + +MACRO nxr2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END nxr2_x1 + + +MACRO nxr2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END nxr2_x4 + + +MACRO o2_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END o2_x2 + + +MACRO o2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END o2_x4 + + +MACRO o3_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END o3_x2 + + +MACRO o3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END o3_x4 + + +MACRO o4_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + END +END o4_x2 + + +MACRO o4_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i3 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END o4_x4 + + +MACRO oa22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + END +END oa22_x2 + + +MACRO oa22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END oa22_x4 + + +MACRO oa2a22_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END oa2a22_x2 + + +MACRO oa2a22_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END oa2a22_x4 + + +MACRO oa2a2a23_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END oa2a2a23_x2 + + +MACRO oa2a2a23_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 54.00 9.00 56.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i0 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i3 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i5 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END oa2a2a23_x4 + + +MACRO oa2a2a2a24_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 75.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END i0 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 72.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 72.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 73.50 41.00 ; + END +END oa2a2a2a24_x2 + + +MACRO oa2a2a2a24_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 80.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 64.00 14.00 66.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i1 + PIN i7 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i7 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i6 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i5 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i4 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 77.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 77.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 78.50 41.00 ; + END +END oa2a2a2a24_x4 + + +MACRO oa2ao222_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END oa2ao222_x2 + + +MACRO oa2ao222_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i2 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i4 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END oa2ao222_x4 + + +MACRO oa3ao322_x2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 55.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END i0 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END i5 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i3 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END i6 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i2 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 52.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 52.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 53.50 41.00 ; + END +END oa3ao322_x2 + + +MACRO oa3ao322_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END i2 + PIN i6 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END i6 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + END + END i4 + PIN i5 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i5 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i0 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END i3 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END oa3ao322_x4 + + +MACRO on12_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + END +END on12_x1 + + +MACRO on12_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 40.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END i1 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 37.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 37.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 38.50 41.00 ; + END +END on12_x4 + + +MACRO one_x0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END one_x0 + + +MACRO powmid_x0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + LAYER ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 44.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + LAYER ALU3 ; + WIDTH 12.00 ; + PATH 25.00 6.00 25.00 44.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 33.50 41.00 ; + LAYER ALU2 ; + RECT 4.00 49.00 16.00 51.00 ; + RECT 19.00 -1.00 31.00 1.00 ; + END +END powmid_x0 + + +MACRO rowend_x0 + CLASS CORE FEEDTHRU ; + ORIGIN 0.00 0.00 ; + SIZE 5.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 2.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 2.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 3.50 41.00 ; + END +END rowend_x0 + + +MACRO sff1_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 90.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + LAYER ALU1 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 87.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 87.00 3.00 ; + END + END vss + PIN ck + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END ck + OBS + LAYER ALU1 ; + RECT 1.50 9.00 88.50 41.00 ; + END +END sff1_x4 + + +MACRO sff2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + RECT 109.00 24.00 111.00 26.00 ; + RECT 109.00 19.00 111.00 21.00 ; + RECT 109.00 14.00 111.00 16.00 ; + RECT 109.00 9.00 111.00 11.00 ; + END + END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END cmd + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 117.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 117.00 3.00 ; + END + END vss + PIN ck + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER ALU1 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 44.00 9.00 46.00 11.00 ; + END + END ck + OBS + LAYER ALU1 ; + RECT 1.50 9.00 118.50 41.00 ; + END +END sff2_x4 + + +MACRO sff3_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 140.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 129.00 39.00 131.00 41.00 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 129.00 29.00 131.00 31.00 ; + RECT 129.00 24.00 131.00 26.00 ; + RECT 129.00 19.00 131.00 21.00 ; + RECT 129.00 14.00 131.00 16.00 ; + RECT 129.00 9.00 131.00 11.00 ; + END + END q + PIN cmd1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END cmd1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END i1 + PIN cmd0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END cmd0 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 19.00 41.00 21.00 ; + LAYER ALU1 ; + RECT 39.00 29.00 41.00 31.00 ; + LAYER ALU1 ; + RECT 44.00 24.00 46.00 26.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 137.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 137.00 3.00 ; + END + END vss + PIN ck + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER ALU1 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END ck + OBS + LAYER ALU1 ; + RECT 1.50 9.00 138.50 41.00 ; + END +END sff3_x4 + + +MACRO tie_x0 + CLASS CORE FEEDTHRU ; + ORIGIN 0.00 0.00 ; + SIZE 10.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 7.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 7.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 8.50 41.00 ; + END +END tie_x0 + + +MACRO ts_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END cmd + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 48.50 41.00 ; + END +END ts_x4 + + +MACRO ts_x8 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 65.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER ALU1 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END q + PIN cmd + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END cmd + PIN i + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 54.00 14.00 56.00 16.00 ; + END + END i + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 62.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 62.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 63.50 41.00 ; + END +END ts_x8 + + +MACRO xr2_x1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 19.00 9.00 21.00 11.00 ; + LAYER ALU1 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 14.00 9.00 16.00 11.00 ; + LAYER ALU1 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 43.50 41.00 ; + END +END xr2_x1 + + +MACRO xr2_x4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 60.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END i0 + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 57.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 57.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 58.50 41.00 ; + END +END xr2_x4 + + +MACRO zero_x0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 15.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN vdd + DIRECTION INPUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 12.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INPUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 12.00 3.00 ; + END + END vss + OBS + LAYER ALU1 ; + RECT 1.50 9.00 13.50 41.00 ; + END +END zero_x0 + + +END LIBRARY diff --git a/pdks/symbolic/sxlib/cells/sxlib.lib b/pdks/symbolic/sxlib/cells/sxlib.lib new file mode 100644 index 000000000..686cce72c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sxlib.lib @@ -0,0 +1,22662 @@ +/************************************************************************/ +/* */ +/* Avertec Release v3.4p5 (64 bits on Linux 4.4.70-1.el7.elrepo.x86_64)*/ +/* [AVT_only] host: lepka */ +/* [AVT_only] arch: x86_64 */ +/* [AVT_only] path: /dsk/l1/tasyag/Linux.el7_64/install/bin/avt_shell */ +/* argv: /dsk/l1/jpc/coriolis-2.x/src/alliance-check-toolkit/benchs/bin/buildLib.tcl /dsk/l1/jpc/coriolis-2.x/src/alliance-check-toolkit/benchs/etc/bsim4_dummy.hsp sxlib */ +/* */ +/* User: jpc */ +/* Generation date Wed Jun 13 14:09:48 2018 */ +/* */ +/* liberty data flow `sxlib.lib` */ +/* */ +/************************************************************************/ + + + +library (sxlib.lib) { + + technology (cmos) ; + date : "Wed Jun 13 14:09:48 2018" ; + delay_model : table_lookup ; + nom_voltage : 5.00 ; + nom_temperature : 70.0 ; + nom_process : 1.0 ; + slew_derate_from_library : 1.0 ; + default_fanout_load : 1000.0 ; + default_inout_pin_cap : 1000.0 ; + default_input_pin_cap : 1000.0 ; + default_output_pin_cap : 0.0 ; + voltage_unit : "1V" ; + time_unit : "1ps" ; + capacitive_load_unit (1,ff) ; + pulling_resistance_unit : "1ohm" ; + current_unit : "1mA" ; + leakage_power_unit : "1uW" ; + default_cell_leakage_power : 0.0 ; + input_threshold_pct_rise : 50.0 ; + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_rise : 50.0 ; + output_threshold_pct_fall : 50.0 ; + slew_lower_threshold_pct_fall : 20.0 ; + slew_upper_threshold_pct_fall : 80.0 ; + slew_lower_threshold_pct_rise : 20.0 ; + slew_upper_threshold_pct_rise : 80.0 ; + + lu_table_template (inslew_load_5x5__39) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("34.11, 68.23, 136.46, 272.91, 545.83"); + } + lu_table_template (inslew_load_5x5__38) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("29.20, 58.40, 116.80, 233.60, 467.21"); + } + lu_table_template (inslew_load_5x5__37) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.29, 74.57, 149.15, 298.29, 596.59"); + } + lu_table_template (inslew_load_5x5__36) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("38.27, 76.53, 153.07, 306.13, 612.27"); + } + lu_table_template (inslew_load_5x5__35) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("21.76, 43.52, 87.03, 174.07, 348.13"); + } + lu_table_template (inslew_load_5x5__34) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.20, 44.41, 88.82, 177.64, 355.27"); + } + lu_table_template (inslew_load_5x5__33) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.28, 44.57, 89.13, 178.27, 356.53"); + } + lu_table_template (inslew_load_5x5__32) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("35.08, 70.16, 140.33, 280.66, 561.32"); + } + lu_table_template (inslew_load_5x5__31) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("45.48, 90.96, 181.93, 363.85, 727.70"); + } + lu_table_template (inslew_load_5x5__30) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.60, 75.20, 150.41, 300.81, 601.63"); + } + lu_table_template (inslew_load_5x5__29) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.38, 44.76, 89.52, 179.04, 358.07"); + } + lu_table_template (inslew_load_5x5__28) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("34.76, 69.52, 139.03, 278.07, 556.14"); + } + lu_table_template (inslew_load_5x5__27) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("28.37, 56.74, 113.48, 226.95, 453.91"); + } + lu_table_template (inslew_load_5x5__26) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("21.09, 42.19, 84.37, 168.75, 337.49"); + } + lu_table_template (inslew_load_5x5__25) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("20.60, 41.21, 82.41, 164.83, 329.65"); + } + lu_table_template (inslew_load_5x5__24) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("13.41, 26.82, 53.63, 107.26, 214.53"); + } + lu_table_template (inslew_load_5x5__23) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.42, 44.85, 89.69, 179.39, 358.77"); + } + lu_table_template (inslew_load_5x5__22) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("21.58, 43.17, 86.33, 172.67, 345.33"); + } + lu_table_template (inslew_load_5x5__21) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("38.72, 77.44, 154.89, 309.77, 619.55"); + } + lu_table_template (inslew_load_5x5__20) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.64, 75.27, 150.55, 301.09, 602.19"); + } + lu_table_template (inslew_load_5x5__19) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("18.95, 37.90, 75.81, 151.61, 303.22"); + } + lu_table_template (inslew_load_5x5__18) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("21.51, 43.03, 86.05, 172.11, 344.21"); + } + lu_table_template (inslew_load_5x5__17) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.03, 44.06, 88.12, 176.24, 352.47"); + } + lu_table_template (inslew_load_5x5__16) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("51.47, 102.94, 205.89, 411.77, 823.54"); + } + lu_table_template (inslew_load_5x5__15) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.25, 74.50, 149.01, 298.01, 596.03"); + } + lu_table_template (inslew_load_5x5__14) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.99, 75.97, 151.95, 303.89, 607.79"); + } + lu_table_template (inslew_load_5x5__13) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.11, 74.22, 148.45, 296.89, 593.79"); + } + lu_table_template (inslew_load_5x5__12) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("38.27, 76.54, 153.07, 306.14, 612.29"); + } + lu_table_template (inslew_load_5x5__11) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.78, 75.55, 151.11, 302.21, 604.43"); + } + lu_table_template (inslew_load_5x5__10) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("36.69, 73.38, 146.76, 293.51, 587.02"); + } + lu_table_template (inslew_5__0) { + variable_1 : input_net_transition; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + lu_table_template (inslew_load_5x5__9) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.35, 44.71, 89.41, 178.83, 357.65"); + } + lu_table_template (inslew_load_5x5__8) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("26.02, 52.03, 104.07, 208.14, 416.28"); + } + lu_table_template (inslew_load_5x5__7) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.22, 74.43, 148.87, 297.73, 595.47"); + } + lu_table_template (inslew_load_5x5__6) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("38.06, 76.11, 152.23, 304.45, 608.91"); + } + lu_table_template (inslew_load_5x5__5) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.08, 74.15, 148.31, 296.61, 593.23"); + } + lu_table_template (inslew_load_5x5__4) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("38.86, 77.72, 155.45, 310.89, 621.79"); + } + lu_table_template (inslew_load_5x5__3) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.92, 75.83, 151.67, 303.33, 606.67"); + } + lu_table_template (inslew_load_5x5__2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.15, 74.29, 148.59, 297.17, 594.35"); + } + lu_table_template (inslew_load_5x5__1) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("74.50, 149.01, 298.01, 596.03, 1192.05"); + } + lu_table_template (inslew_load_5x5__0) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("21.44, 42.89, 85.77, 171.55, 343.09"); + } + power_lut_template (energy_inslew_load_5x5__39) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("34.11, 68.23, 136.46, 272.91, 545.83"); + } + power_lut_template (energy_inslew_load_5x5__38) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("29.20, 58.40, 116.80, 233.60, 467.21"); + } + power_lut_template (energy_inslew_load_5x5__37) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.29, 74.57, 149.15, 298.29, 596.59"); + } + power_lut_template (energy_inslew_load_5x5__36) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("38.27, 76.53, 153.07, 306.13, 612.27"); + } + power_lut_template (energy_inslew_load_5x5__35) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("21.76, 43.52, 87.03, 174.07, 348.13"); + } + power_lut_template (energy_inslew_load_5x5__34) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.20, 44.41, 88.82, 177.64, 355.27"); + } + power_lut_template (energy_inslew_load_5x5__33) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.28, 44.57, 89.13, 178.27, 356.53"); + } + power_lut_template (energy_inslew_load_5x5__32) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("35.08, 70.16, 140.33, 280.66, 561.32"); + } + power_lut_template (energy_inslew_load_5x5__31) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("45.48, 90.96, 181.93, 363.85, 727.70"); + } + power_lut_template (energy_inslew_load_5x5__30) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.60, 75.20, 150.41, 300.81, 601.63"); + } + power_lut_template (energy_inslew_load_5x5__29) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.38, 44.76, 89.52, 179.04, 358.07"); + } + power_lut_template (energy_inslew_load_5x5__28) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("34.76, 69.52, 139.03, 278.07, 556.14"); + } + power_lut_template (energy_inslew_load_5x5__27) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("28.37, 56.74, 113.48, 226.95, 453.91"); + } + power_lut_template (energy_inslew_load_5x5__26) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("21.09, 42.19, 84.37, 168.75, 337.49"); + } + power_lut_template (energy_inslew_load_5x5__25) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("20.60, 41.21, 82.41, 164.83, 329.65"); + } + power_lut_template (energy_inslew_load_5x5__24) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("13.41, 26.82, 53.63, 107.26, 214.53"); + } + power_lut_template (energy_inslew_load_5x5__23) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.42, 44.85, 89.69, 179.39, 358.77"); + } + power_lut_template (energy_inslew_load_5x5__22) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("21.58, 43.17, 86.33, 172.67, 345.33"); + } + power_lut_template (energy_inslew_load_5x5__21) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("38.72, 77.44, 154.89, 309.77, 619.55"); + } + power_lut_template (energy_inslew_load_5x5__20) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.64, 75.27, 150.55, 301.09, 602.19"); + } + power_lut_template (energy_inslew_load_5x5__19) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("18.95, 37.90, 75.81, 151.61, 303.22"); + } + power_lut_template (energy_inslew_load_5x5__18) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("21.51, 43.03, 86.05, 172.11, 344.21"); + } + power_lut_template (energy_inslew_load_5x5__17) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.03, 44.06, 88.12, 176.24, 352.47"); + } + power_lut_template (energy_inslew_load_5x5__16) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("51.47, 102.94, 205.89, 411.77, 823.54"); + } + power_lut_template (energy_inslew_load_5x5__15) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.25, 74.50, 149.01, 298.01, 596.03"); + } + power_lut_template (energy_inslew_load_5x5__14) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.99, 75.97, 151.95, 303.89, 607.79"); + } + power_lut_template (energy_inslew_load_5x5__13) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.11, 74.22, 148.45, 296.89, 593.79"); + } + power_lut_template (energy_inslew_load_5x5__12) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("38.27, 76.54, 153.07, 306.14, 612.29"); + } + power_lut_template (energy_inslew_load_5x5__11) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.78, 75.55, 151.11, 302.21, 604.43"); + } + power_lut_template (energy_inslew_load_5x5__10) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("36.69, 73.38, 146.76, 293.51, 587.02"); + } + power_lut_template (energy_inslew_5__0) { + variable_1 : input_transition_time; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + power_lut_template (energy_inslew_load_5x5__9) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("22.35, 44.71, 89.41, 178.83, 357.65"); + } + power_lut_template (energy_inslew_load_5x5__8) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("26.02, 52.03, 104.07, 208.14, 416.28"); + } + power_lut_template (energy_inslew_load_5x5__7) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.22, 74.43, 148.87, 297.73, 595.47"); + } + power_lut_template (energy_inslew_load_5x5__6) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("38.06, 76.11, 152.23, 304.45, 608.91"); + } + power_lut_template (energy_inslew_load_5x5__5) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.08, 74.15, 148.31, 296.61, 593.23"); + } + power_lut_template (energy_inslew_load_5x5__4) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("38.86, 77.72, 155.45, 310.89, 621.79"); + } + power_lut_template (energy_inslew_load_5x5__3) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.92, 75.83, 151.67, 303.33, 606.67"); + } + power_lut_template (energy_inslew_load_5x5__2) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("37.15, 74.29, 148.59, 297.17, 594.35"); + } + power_lut_template (energy_inslew_load_5x5__1) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("74.50, 149.01, 298.01, 596.03, 1192.05"); + } + power_lut_template (energy_inslew_load_5x5__0) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("21.44, 42.89, 85.77, 171.55, 343.09"); + } + + + + + cell (ao2o22_x2) { + area : 32.40 ; + cell_leakage_power : 5.3 ; + leakage_power () { + when : "(!(i3) & !(i2) & i1 & i0)" ; + value : 6.4 ; + } + leakage_power () { + when : "(i3 & !(i2) & !(i1) & i0)" ; + value : 4.2 ; + } + leakage_power () { + when : "((!(i0) & i1 & i2) | (i1 & i2 & !(i3)))" ; + value : 4.5 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & i3) | (!(i1) & i2))) | (i1 & !(i2) & i3))" ; + value : 4.3 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & !(i3))" ; + value : 5.4 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 7.2 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3))" ; + value : 5.8 ; + } + leakage_power () { + when : "((i0 & i1 & i2 & i3) | (!(i0) & !(i1) & !(i2) & !(i3)))" ; + value : 4.4 ; + } + pin (i3) { + direction : input ; + capacitance : 432.96 ; + } + pin (i2) { + direction : input ; + capacitance : 434.46 ; + } + pin (i1) { + direction : input ; + capacitance : 434.46 ; + } + pin (i0) { + direction : input ; + capacitance : 432.96 ; + } + pin (q) { + function : "((i0 | i1) & (i3 | i2))" ; + direction : output ; + capacitance : 85.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("7129.9, 7129.9, 7129.9, 7423.9, 7966.1", \ + "7141.3, 7141.3, 7141.3, 7435.2, 7977.0", \ + "7153.1, 7153.1, 7153.1, 7446.9, 7988.4", \ + "7167.1, 7167.1, 7167.1, 7460.9, 8002.4", \ + "7199.4, 7199.4, 7199.4, 7493.2, 8034.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("3194.3, 3194.3, 3194.3, 3437.0, 3904.6", \ + "3203.1, 3203.1, 3203.1, 3445.7, 3913.0", \ + "3210.4, 3210.4, 3210.4, 3452.9, 3920.1", \ + "3212.7, 3212.7, 3212.7, 3455.2, 3922.3", \ + "3213.7, 3213.7, 3213.7, 3456.1, 3923.3"); + } + cell_fall (inslew_load_5x5__0) { + values ("9764.2, 9764.2, 9764.2, 10013.6, 10481.4", \ + "9758.8, 9758.8, 9758.8, 10008.2, 10476.0", \ + "9748.1, 9748.1, 9748.1, 9997.5, 10465.3", \ + "9726.7, 9726.7, 9726.7, 9976.1, 10443.9", \ + "9683.8, 9683.8, 9683.8, 9933.2, 10401.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("4559.8, 4559.8, 4559.8, 4687.0, 4978.7", \ + "4559.8, 4559.8, 4559.8, 4687.0, 4978.7", \ + "4559.8, 4559.8, 4559.8, 4687.0, 4978.7", \ + "4559.8, 4559.8, 4559.8, 4687.0, 4978.7", \ + "4559.8, 4559.8, 4559.8, 4687.0, 4978.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("5844.5, 5844.5, 5844.5, 6160.4, 6731.0", \ + "5856.4, 5856.4, 5856.4, 6172.2, 6742.6", \ + "5868.2, 5868.2, 5868.2, 6183.9, 6754.2", \ + "5882.4, 5882.4, 5882.4, 6198.1, 6768.4", \ + "5915.4, 5915.4, 5915.4, 6231.0, 6801.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("2281.3, 2281.3, 2281.3, 2549.3, 3041.3", \ + "2290.9, 2290.9, 2290.9, 2558.7, 3050.4", \ + "2298.6, 2298.6, 2298.6, 2566.3, 3057.7", \ + "2301.2, 2301.2, 2301.2, 2568.9, 3060.2", \ + "2302.9, 2302.9, 2302.9, 2570.5, 3061.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("7265.0, 7265.0, 7265.0, 7503.9, 7972.1", \ + "7267.9, 7267.9, 7267.9, 7506.8, 7974.4", \ + "7276.8, 7276.8, 7276.8, 7515.7, 7982.1", \ + "7288.9, 7288.9, 7288.9, 7527.8, 7993.5", \ + "7317.5, 7317.5, 7317.5, 7556.4, 8022.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("3081.6, 3081.6, 3081.6, 3260.9, 3614.2", \ + "3084.5, 3084.5, 3084.5, 3263.5, 3616.9", \ + "3090.2, 3090.2, 3090.2, 3268.9, 3622.4", \ + "3093.3, 3093.3, 3093.3, 3271.9, 3625.4", \ + "3094.0, 3094.0, 3094.0, 3272.6, 3626.1"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("7341.1, 7341.1, 7341.1, 7634.2, 8174.8", \ + "7335.9, 7335.9, 7335.9, 7629.0, 8169.6", \ + "7325.6, 7325.6, 7325.6, 7618.7, 8159.3", \ + "7305.0, 7305.0, 7305.0, 7598.1, 8138.7", \ + "7263.7, 7263.7, 7263.7, 7556.9, 8097.4"); + } + rise_transition (inslew_load_5x5__0) { + values ("3310.0, 3310.0, 3310.0, 3551.5, 4015.4", \ + "3310.0, 3310.0, 3310.0, 3551.5, 4015.4", \ + "3310.0, 3310.0, 3310.0, 3551.5, 4015.4", \ + "3310.0, 3310.0, 3310.0, 3551.5, 4015.4", \ + "3310.1, 3310.1, 3310.1, 3551.7, 4015.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("8487.5, 8487.5, 8487.5, 8731.9, 9186.6", \ + "8490.1, 8490.1, 8490.1, 8734.5, 9189.3", \ + "8498.9, 8498.9, 8498.9, 8743.3, 9198.3", \ + "8511.1, 8511.1, 8511.1, 8755.5, 9210.6", \ + "8539.4, 8539.4, 8539.4, 8783.8, 9238.9"); + } + fall_transition (inslew_load_5x5__0) { + values ("3847.1, 3847.1, 3847.1, 3990.0, 4302.6", \ + "3850.0, 3850.0, 3850.0, 3992.8, 4305.3", \ + "3855.8, 3855.8, 3855.8, 3998.5, 4310.9", \ + "3859.0, 3859.0, 3859.0, 4001.6, 4313.9", \ + "3859.7, 3859.7, 3859.7, 4002.2, 4314.5"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("8534.0, 8534.0, 8534.0, 8821.2, 9360.3", \ + "8528.8, 8528.8, 8528.8, 8816.0, 9355.1", \ + "8518.5, 8518.5, 8518.5, 8805.7, 9344.8", \ + "8497.9, 8497.9, 8497.9, 8785.1, 9324.2", \ + "8456.6, 8456.6, 8456.6, 8743.8, 9283.0"); + } + rise_transition (inslew_load_5x5__0) { + values ("4118.8, 4118.8, 4118.8, 4349.8, 4797.3", \ + "4118.8, 4118.8, 4118.8, 4349.8, 4797.3", \ + "4118.8, 4118.8, 4118.8, 4349.8, 4797.3", \ + "4118.8, 4118.8, 4118.8, 4349.8, 4797.3", \ + "4118.9, 4118.9, 4118.9, 4349.9, 4797.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("10765.8, 10765.8, 10765.8, 11112.0, 11587.7", \ + "10760.4, 10760.4, 10760.4, 11106.6, 11582.3", \ + "10749.7, 10749.7, 10749.7, 11095.9, 11571.6", \ + "10728.3, 10728.3, 10728.3, 11074.5, 11550.2", \ + "10685.4, 10685.4, 10685.4, 11031.6, 11507.3"); + } + fall_transition (inslew_load_5x5__0) { + values ("5183.1, 5183.1, 5183.1, 5339.9, 5607.5", \ + "5183.1, 5183.1, 5183.1, 5339.9, 5607.5", \ + "5183.1, 5183.1, 5183.1, 5339.9, 5607.5", \ + "5183.1, 5183.1, 5183.1, 5339.9, 5607.5", \ + "5183.1, 5183.1, 5183.1, 5339.9, 5607.5"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("26635.3, 26635.3, 26635.3, 27707.5, 29851.8", \ + "26682.4, 26682.4, 26682.4, 27754.6, 29898.9", \ + "26751.0, 26751.0, 26751.0, 27823.2, 29967.5", \ + "26857.5, 26857.5, 26857.5, 27929.7, 30074.0", \ + "27061.4, 27061.4, 27061.4, 28133.6, 30277.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("32109.6, 32109.6, 32109.6, 33181.8, 35326.1", \ + "35357.7, 35357.7, 35357.7, 35357.7, 35357.7", \ + "35420.8, 35420.8, 35420.8, 35420.8, 35420.8", \ + "35547.0, 35547.0, 35547.0, 35547.0, 35547.0", \ + "35799.5, 35799.5, 35799.5, 35799.5, 35799.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("21800.7, 21800.7, 21800.7, 22872.9, 25017.2", \ + "21833.6, 21833.6, 21833.6, 22905.8, 25050.1", \ + "21873.3, 21873.3, 21873.3, 22945.5, 25089.8", \ + "21923.6, 21923.6, 21923.6, 22995.8, 25140.1", \ + "22016.4, 22016.4, 22016.4, 23088.6, 25232.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("22327.8, 22327.8, 22327.8, 23399.9, 25544.3", \ + "22377.0, 22377.0, 22377.0, 23449.1, 25593.5", \ + "22475.3, 22475.3, 22475.3, 23547.5, 25691.9", \ + "22648.2, 22648.2, 22648.2, 23720.3, 25864.7", \ + "22978.1, 22978.1, 22978.1, 24050.2, 26194.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("27463.8, 27463.8, 27463.8, 28535.9, 30680.3", \ + "30694.6, 30694.6, 30694.6, 30694.6, 30694.6", \ + "30723.4, 30723.4, 30723.4, 30723.4, 30723.4", \ + "30780.8, 30780.8, 30780.8, 30780.8, 30780.8", \ + "27679.5, 27679.5, 27679.5, 28751.7, 30896.0"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("26952.7, 26952.7, 26952.7, 28024.9, 30169.2", \ + "27003.6, 27003.6, 27003.6, 28075.7, 30220.1", \ + "27105.4, 27105.4, 27105.4, 28177.6, 30321.9", \ + "27285.1, 27285.1, 27285.1, 28357.2, 30501.6", \ + "27627.9, 27627.9, 27627.9, 28700.1, 30844.5"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("32256.8, 32256.8, 32256.8, 33328.9, 35473.3", \ + "35496.2, 35496.2, 35496.2, 35496.2, 35496.2", \ + "35542.0, 35542.0, 35542.0, 35542.0, 35542.0", \ + "35633.5, 35633.5, 35633.5, 35633.5, 35633.5", \ + "32600.4, 32600.4, 32600.4, 33672.6, 35816.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("36710.1, 36710.1, 36710.1, 37782.3, 39926.6", \ + "39970.7, 39970.7, 39970.7, 39970.7, 39970.7", \ + "40058.9, 40058.9, 40058.9, 40058.9, 40058.9", \ + "40235.2, 40235.2, 40235.2, 40235.2, 40235.2", \ + "40587.9, 40587.9, 40587.9, 40587.9, 40587.9"); + } + } + } + } + + cell (buf_x8) { + area : 28.80 ; + cell_leakage_power : 11 ; + leakage_power () { + when : "i" ; + value : 13 ; + } + leakage_power () { + when : "!(i)" ; + value : 9.4 ; + } + pin (i) { + direction : input ; + capacitance : 854.46 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 298.01 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("5654.5, 5654.5, 5654.5, 5938.7, 6455.0", \ + "5663.3, 5663.3, 5663.3, 5947.5, 6463.8", \ + "5680.9, 5680.9, 5680.9, 5965.1, 6481.4", \ + "5716.1, 5716.1, 5716.1, 6000.3, 6516.6", \ + "5786.9, 5786.9, 5786.9, 6071.0, 6587.3"); + } + rise_transition (inslew_load_5x5__1) { + values ("1936.0, 1936.0, 1936.0, 2180.1, 2628.6", \ + "1936.0, 1936.0, 1936.0, 2180.1, 2628.6", \ + "1936.0, 1936.0, 1936.0, 2180.1, 2628.6", \ + "1936.0, 1936.0, 1936.0, 2180.1, 2628.6", \ + "1936.6, 1936.6, 1936.6, 2180.8, 2629.2"); + } + cell_fall (inslew_load_5x5__1) { + values ("7543.5, 7543.5, 7543.5, 7751.2, 8190.8", \ + "7552.3, 7552.3, 7552.3, 7760.0, 8199.6", \ + "7569.9, 7569.9, 7569.9, 7777.6, 8217.2", \ + "7605.1, 7605.1, 7605.1, 7812.8, 8252.4", \ + "7675.5, 7675.5, 7675.5, 7883.2, 8322.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("2905.0, 2905.0, 2905.0, 3067.3, 3385.1", \ + "2905.0, 2905.0, 2905.0, 3067.3, 3385.1", \ + "2905.0, 2905.0, 2905.0, 3067.3, 3385.1", \ + "2905.0, 2905.0, 2905.0, 3067.3, 3385.1", \ + "2905.0, 2905.0, 2905.0, 3067.3, 3385.1"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__1) { + values ("80386.4, 80386.4, 80386.4, 84111.6, 91561.9", \ + "91607.6, 91607.6, 91607.6, 91607.6, 91607.6", \ + "91699.1, 91699.1, 91699.1, 91699.1, 91699.1", \ + "91881.9, 91881.9, 91881.9, 91881.9, 91881.9", \ + "81077.8, 81077.8, 81077.8, 84802.9, 92253.3"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("82971.9, 82971.9, 82971.9, 86697.1, 94147.4", \ + "94235.8, 94235.8, 94235.8, 94235.8, 94235.8", \ + "94412.6, 94412.6, 94412.6, 94412.6, 94412.6", \ + "94766.2, 94766.2, 94766.2, 94766.2, 94766.2", \ + "95473.4, 95473.4, 95473.4, 95473.4, 95473.4"); + } + } + } + } + + cell (fulladder_x4) { + area : 75.60 ; + cell_leakage_power : 15 ; + leakage_power () { + when : "((!(a1) & ((a2 & ((a3 & ((a4 & ((!(b1) & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))) | (b4 & cin1 & cin2 & cin3))) | (b3 & b4 & cin1 & cin2 & cin3))) | (!(b1) & b3 & cin1 & cin2))) | (a4 & !(b1) & b3 & b4 & cin1 & cin2 & cin3))) | (a3 & a4 & !(b1) & b2 & b3 & b4 & cin1 & cin2 & cin3))) | (a2 & a3 & a4 & !(b1) & b3 & b4 & cin1 & cin2 & cin3))" ; + value : 18 ; + } + leakage_power () { + when : "((a1 & ((a2 & ((a3 & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & (cin2 | cin3)) | cin2)) | (b4 & (cin1 | cin2) & cin3))) | (b3 & ((b4 & (cin2 | cin3)) | cin2)) | (b4 & cin2 & cin3))) | (!(b1) & ((b2 & ((b3 & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & ((cin1 & (cin2 | cin3)) | (!(cin2) & cin3))) | (!((cin1 ^ cin2)) & cin3))))) | (b3 & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & b4 & cin1 & cin3))))) | (!(a4) & ((b1 & b3 & cin2) | (!(b1) & ((b2 & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))) | (!(b3) & ((b4 & cin1 & cin2 & cin3) | (!(b4) & !(cin1) & !(cin2) & cin3))))) | (b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & b4 & (cin1 | cin2) & cin3) | (b4 & cin1 & cin2 & cin3))) | (b3 & b4 & cin2 & cin3))) | (!(b1) & ((b2 & ((b3 & ((b4 & ((cin1 & (cin2 | cin3)) | (!(cin2) & cin3))) | (!((cin1 ^ cin2)) & cin3))) | (!(b3) & ((b4 & cin3) | (!(b4) & !(cin1) & (!(cin2) | cin3)))))) | (b3 & b4 & cin1 & cin3) | (b4 & cin1 & cin2 & cin3))))) | (!(b1) & b2 & ((b3 & ((b4 & cin1 & cin2 & cin3) | (!(b4) & !(cin1) & !(cin2) & cin3))) | (!(b3) & !(b4) & !(cin1) & cin3))))))) | (!(a2) & ((a3 & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & (cin2 | cin3)) | cin2)) | (b4 & cin2 & cin3))) | (b3 & ((b4 & (cin2 | cin3)) | cin2)) | (b4 & cin1 & cin2 & cin3))) | (!(b1) & b2 & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))) | (b4 & cin1 & cin3))))) | (b1 & b3 & cin2) | (b2 & b3 & cin1 & cin2))) | (a4 & ((b1 & ((b2 & b3 & b4 & cin2 & cin3) | (b3 & b4 & cin1 & cin2 & cin3))) | (!(b1) & b2 & ((b3 & b4 & cin1 & cin3) | (b4 & cin1 & cin2 & cin3))))))))) | (!(a1) & ((a2 & ((a3 & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2 & cin3))))) | (b3 & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & b4 & cin1 & cin3))) | (!(b1) & ((!(b2) & ((!(b3) & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & cin3))) | (b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & cin1 & !(cin2) & cin3))) | (b3 & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & cin1 & !(cin2) & cin3))) | (!(b3) & ((b4 & cin1 & (cin2 ^ cin3)) | (!(b4) & cin1 & cin2 & cin3))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))) | (b4 & cin1 & cin2 & cin3))) | (b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))))) | (!(b1) & ((!(b2) & ((!(b3) & b4 & cin1 & cin3) | (b4 & cin1 & !(cin2) & cin3))) | (b3 & b4 & cin1 & !(cin2) & cin3) | (!(b3) & b4 & cin1 & cin2 & cin3))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2 & cin3))) | (b4 & cin1 & cin3))) | (b3 & b4 & cin1 & cin3) | (b4 & cin1 & cin2 & cin3))) | (!(b1) & ((!(b2) & ((b3 & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & cin3))) | (!(b3) & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2 & cin3))))) | (b3 & ((b4 & cin1 & (cin2 ^ cin3)) | (!(b4) & cin1 & cin2 & cin3))) | (!(b3) & b4 & cin1 & cin3))))) | (!(a4) & ((!(b1) & ((!(b2) & ((b3 & b4 & cin1 & cin3) | (b4 & cin1 & cin2 & cin3))) | (b3 & b4 & cin1 & cin2 & cin3))) | (b2 & b3 & b4 & cin1 & cin2 & cin3))))))) | (!(a2) & ((a3 & ((a4 & ((b1 & b2 & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))) | (b4 & cin1 & cin3))) | (!(b1) & b2 & ((b3 & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2 & cin3))))))) | (!(a4) & ((!(b1) & b2 & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))) | (b4 & cin1 & cin2 & cin3))) | (b2 & b3 & cin1 & cin2))))) | (!(a3) & ((a4 & ((!(b1) & b2 & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2 & cin3))) | (b4 & cin1 & cin3))) | (b2 & ((b3 & b4 & cin1 & cin3) | (b4 & cin1 & cin2 & cin3))))) | (!(b1) & b2 & b3 & b4 & cin1 & cin2 & cin3))))))))" ; + value : 17 ; + } + leakage_power () { + when : "((a1 & ((a2 & ((a3 & !(a4) & ((b1 & ((!(b2) & ((!(b3) & !(b4) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b3) & !(b4) & !((cin1 & cin2)) & !(cin3)))) | (!(b1) & ((b2 & ((!(b3) & !(b4) & !(cin1) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))))) | (!(a3) & ((a4 & b1 & ((!(b2) & !(b3) & !(b4) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(a4) & ((b1 & ((b2 & ((!(b3) & ((!(b4) & (!((cin1 | cin2)) | !(cin3))) | (!(cin1) & !(cin2) & !(cin3)))) | (!(b4) & !((cin1 & cin2)) & !(cin3)))) | (!(b2) & ((b3 & !(b4) & !(cin3)) | (!(b3) & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))))))))) | (b2 & ((!(b3) & !(b4) & !((cin1 & cin2)) & !(cin3)) | (!(b4) & !(cin1) & !(cin3)))) | (b3 & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))))))) | (!(a2) & ((a3 & !(a4) & ((b1 & ((!(b3) & !(b4) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b1) & ((b2 & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & (cin1 ^ cin2) & !(cin3)))) | (!(b2) & ((!(b3) & !(b4) & cin1 & !(cin3)) | (!(b4) & cin1 & !(cin2) & !(cin3)))))))) | (!(a3) & ((a4 & b1 & !(b3) & !(b4) & !(cin2) & !(cin3)) | (!(a4) & ((b1 & ((b3 & !(b4) & !(cin3)) | (!(b3) & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))))))) | (b2 & ((b3 & !(b4) & (cin1 ^ cin2) & !(cin3)) | (!(b3) & !(b4) & cin1 & !(cin3)))) | (!(b2) & ((b3 & !(b4) & cin1 & !(cin3)) | (!(b4) & cin1 & cin2 & !(cin3)))))))))))) | (!(a1) & ((a2 & ((a3 & !(a4) & ((b1 & b2 & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))) | (b2 & b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(a3) & !(a4) & b1 & ((b2 & ((b3 & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))))) | (!(a2) & ((a3 & ((a4 & ((!(b1) & !(b2) & ((b3 & !(cin1)) | (!(cin1) & (cin2 | !(cin3))))) | (!(b2) & b3 & ((!(b4) & !(cin1) & cin2) | (!(cin1) & cin2 & !(cin3)))))) | (!(a4) & ((b1 & ((b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b2) & ((b3 & ((!(b4) & ((cin1 & !(cin2) & !(cin3)) | (!(cin1) & cin2))) | (!(cin1) & cin2))) | (!(b3) & !(b4) & cin1 & cin2 & !(cin3)))))) | (!(b1) & !(b2) & ((b3 & ((b4 & !(cin1)) | (!(cin1) & (cin2 | cin3)))) | (b4 & !(cin1)) | (!(cin1) & cin2 & cin3))))))) | (!(a3) & ((a4 & !(b1) & !(b2) & ((b3 & !(cin1) & (cin2 | !(cin3))) | (!(cin1) & cin2 & !(cin3)))) | (!(a4) & ((b1 & ((b2 & ((!(b3) & !(b4) & cin1 & !(cin3)) | (!(b4) & cin1 & !(cin2) & !(cin3)))) | (!(b2) & b3 & !(b4) & cin1 & cin2 & !(cin3)))) | (!(b1) & ((b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b2) & ((b3 & ((b4 & !(cin1)) | (!(cin1) & cin2 & cin3))) | (b4 & !(cin1) & cin2))))))))))))))" ; + value : 14 ; + } + leakage_power () { + when : "((a1 & ((a2 & ((!(a3) & !(a4) & ((!(b1) & !(b2) & ((!(b3) & !(b4) & !(cin1) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(a4) & !(b1) & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(a2) & ((a3 & !(a4) & !(b1) & ((!(b2) & ((!(b3) & !(b4) & !(cin1) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(a3) & !(a4) & ((b1 & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b1) & ((b2 & ((!(b3) & !(b4) & !(cin1) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b2) & ((b3 & !(b4) & !(cin1) & !(cin3)) | (!(b3) & !(b4) & (cin1 ^ cin2) & !(cin3)))))))))))) | (!(a1) & ((a2 & ((a3 & !(a4) & ((b1 & ((!(b2) & ((!(b3) & !(b4) & !(cin1) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b1) & ((b2 & !(b3) & !(b4) & !(cin1) & !(cin3)) | (!(b2) & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))))))) | (!(a3) & !(a4) & ((b1 & ((!((b2 & b3)) & !(b4) & !(cin1) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b1) & ((b2 & !(b4) & !(cin1) & !(cin3)) | (b3 & !(b4) & !(cin1) & cin2 & !(cin3)))))))) | (!(a2) & ((a3 & !(a4) & ((b1 & ((b2 & ((!(b3) & !(b4) & !(cin1) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b2) & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & (cin1 ^ cin2) & !(cin3)))))) | (!(b1) & ((b2 & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))) | (!(b2) & ((!(b3) & !(b4) & cin1 & !(cin3)) | (!(b4) & cin1 & !(cin2) & !(cin3)))))))) | (!(a3) & !(a4) & ((b1 & ((b2 & !(b4) & !(cin1) & !(cin3)) | (!(b2) & ((b3 & !(b4) & (cin1 ^ cin2) & !(cin3)) | (!(b3) & !(b4) & cin1 & !(cin3)))))) | (!(b1) & ((b2 & b3 & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(b2) & ((b3 & !(b4) & cin1 & !(cin3)) | (!(b4) & cin1 & cin2 & !(cin3)))))))))))))" ; + value : 13 ; + } + leakage_power () { + when : "((a1 & ((a2 & ((a3 & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & !(cin2)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & (!((cin1 | cin2)) | !(cin3))) | (!(b4) & cin3))))) | (!(b2) & ((b3 & ((b4 & !(cin2) & !(cin3)) | (!(b4) & !(cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))) | (!(b4) & (cin1 | cin2) & cin3))))))) | (!(b1) & ((b2 & ((b3 & ((!(b4) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (!(b3) & ((b4 & ((!(cin1) & (cin2 | !(cin3))) | (!(cin2) & !(cin3)))) | (!(b4) & ((cin1 & (cin2 ^ cin3)) | (!(cin1) & (cin2 | !(cin3))))))))) | (!(b2) & ((b3 & ((b4 & !(cin1) & (!(cin2) | cin3)) | (!(b4) & ((!(cin1) & !(cin2)) | (!(cin2) & !(cin3)))))) | (!(b3) & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & (!(cin1) | cin2 | cin3)))))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & ((cin1 & !(cin2)) | (!(cin2) & cin3))) | (cin1 & !(cin2) & cin3))) | (!(b3) & b4 & cin3))) | (b3 & b4 & !(cin2) & cin3) | (!(b3) & b4 & (cin1 | cin2) & cin3))) | (!(b1) & ((b2 & ((b3 & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & ((!(cin1) & (cin2 | cin3)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & (!(cin1) | (cin2 ^ cin3))) | (!(b4) & cin2 & cin3))))) | (!(b2) & ((b3 & ((b4 & ((!(cin1) & !(cin2)) | (!(cin2) & !(cin3)))) | (!(b4) & !(cin2) & cin3))) | (!(b3) & ((b4 & (!(cin1) | cin2 | cin3)) | (!((cin1 & !(cin2))) & cin3))))))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & (!((cin1 | cin2)) | !(cin3))) | (!(b4) & cin3))) | (!(b3) & ((b4 & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))) | (!(b4) & cin2 & cin3))))) | (!(b2) & ((b3 & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))) | (!(b4) & (cin1 | cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & cin2) | cin3)) | (cin1 & cin2 & cin3))))))) | (!(b1) & ((!(b2) & ((b3 & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & (!(cin1) | cin2 | cin3)))) | (!(b3) & ((b4 & (!(cin1) | !(cin2) | !(cin3))) | (!(b4) & (!(cin1) | cin3)))))) | (b3 & ((b4 & ((!(cin1) & (cin2 | !(cin3))) | (!(cin2) & !(cin3)))) | (!(b4) & ((cin1 & (cin2 ^ cin3)) | (!(cin1) & (cin2 | !(cin3))))))) | (!(b3) & ((b4 & !(cin3)) | (!(b4) & ((cin1 & cin3) | (!(cin1) & cin2 & !(cin3)))))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & b4 & cin3) | (b4 & cin2 & cin3))) | (b3 & b4 & (cin1 | cin2) & cin3) | (b4 & cin1 & cin2 & cin3))) | (!(b1) & ((!(b2) & ((b3 & ((b4 & (!(cin1) | cin2 | cin3)) | (!((cin1 & !(cin2))) & cin3))) | (b4 & (!(cin1) | cin3)) | (!(cin1) & cin3))) | (b3 & ((b4 & (!(cin1) | (cin2 ^ cin3))) | (!(b4) & cin2 & cin3))) | (!(b3) & b4 & (!(cin1) | cin3)))))))))) | (!(a2) & ((a3 & ((a4 & ((b1 & ((!(b2) & ((b3 & ((b4 & !(cin2) & !(cin3)) | (!(b4) & !(cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (!(cin1) & (cin2 | cin3)))) | (!(b4) & (cin1 | cin2) & cin3))))) | (b3 & ((b4 & !(cin2) & !(cin3)) | (!(b4) & !(cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))) | (!(b4) & (cin1 | cin2) & cin3))))) | (!(b1) & ((b2 & ((b3 & ((b4 & ((!(cin1) & (!(cin2) | cin3)) | (!(cin2) & !(cin3)))) | (!(b4) & !(cin2)))) | (!(b3) & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & (!(cin1) | cin2 | cin3)))))) | (!(b2) & cin1))))) | (!(a4) & ((b1 & ((b3 & b4 & !(cin2) & cin3) | (!(b3) & b4 & (cin1 | cin2) & cin3))) | (!(b1) & ((b2 & ((b3 & ((b4 & !(cin2)) | (!(cin2) & cin3))) | (!(b3) & ((b4 & (!(cin1) | cin2 | cin3)) | (!((cin1 & !(cin2))) & cin3))))) | (!(b2) & ((b3 & ((b4 & cin1) | (cin1 & (cin2 | cin3)))) | (b4 & cin1) | (cin1 & cin3))))))))) | (!(a3) & ((a4 & ((b1 & ((!(b2) & ((b3 & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (!(cin1) & (cin2 | cin3)))) | (!(b4) & (cin1 | cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & cin2) | cin3)) | (cin1 & cin2 & cin3))))) | (b3 & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))) | (!(b4) & (cin1 | cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & cin2) | cin3)) | (cin1 & cin2 & cin3))))) | (!(b1) & ((b2 & ((b3 & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & (!(cin1) | cin2 | cin3)))) | (!(b3) & ((b4 & (!(cin1) | !(cin2) | !(cin3))) | (!(b4) & (!(cin1) | cin3)))))) | (!(b2) & ((!(b3) & (cin1 | (!(cin2) & cin3))) | cin1)))))) | (!(a4) & ((b1 & ((b3 & b4 & (cin1 | cin2) & cin3) | (b4 & cin1 & cin2 & cin3))) | (!(b1) & ((b2 & ((b3 & ((b4 & (!(cin1) | cin2 | cin3)) | (!((cin1 & !(cin2))) & cin3))) | (b4 & (!(cin1) | cin3)) | (!(cin1) & cin3))) | (!(b2) & ((!(b3) & ((b4 & cin1) | (!(b4) & (cin1 | !(cin2)) & cin3))) | (b4 & cin1) | (cin1 & cin3))))))))))))) | (!(a1) & ((a2 & ((a3 & ((a4 & ((b1 & ((b2 & ((b3 & ((!(b4) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (!(b3) & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & (!(cin1) | (cin2 ^ cin3))))))) | (!(b2) & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & ((b4 & ((cin1 & !(cin3)) | (!(cin1) & !(cin2) & cin3))) | (!(b4) & ((cin1 & (cin2 | cin3)) | (!(cin2) & cin3))))))))) | (!(b1) & ((b2 & ((!(b3) & ((b4 & ((cin1 & !(cin2) & !(cin3)) | (!(cin1) & cin3))) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (!(cin2) & cin3))))) | (b4 & !(cin1) & !(cin2) & cin3) | (!(b4) & cin1 & !(cin2) & !(cin3)))) | (!(b3) & !(b4) & cin1 & !(cin3)) | (!(b4) & cin1 & !(cin2) & !(cin3)))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & !((cin1 & cin2)) & cin3))) | (!(b3) & ((b4 & (!(cin1) | (cin2 ^ cin3))) | (!(b4) & !((cin1 & !(cin2))) & cin3))))) | (!(b2) & ((b3 & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & cin1 & !(cin2) & cin3))) | (!(b3) & ((b4 & cin1 & (cin2 | cin3)) | (!(b4) & !((cin1 ^ cin2)) & cin3))))))) | (!(b1) & ((b2 & ((b3 & ((!(b4) & cin1 & !(cin2)) | (cin1 & !(cin2) & !(cin3)))) | (!(b3) & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & (cin1 | !(cin2)) & cin3))))) | (b3 & ((!(b4) & cin1 & !(cin2)) | (cin1 & !(cin2) & !(cin3)))) | (!(b3) & ((b4 & cin1 & !(cin3)) | (!(b4) & cin1 & cin3))))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & (!(cin1) | (cin2 ^ cin3))))) | (!(b3) & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & (!(cin1) | cin3)))))) | (!(b2) & ((b3 & ((b4 & ((cin1 & !(cin3)) | (!(cin1) & !(cin2) & cin3))) | (!(b4) & ((cin1 & (cin2 | cin3)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (!(cin1) & cin3))) | (!(b4) & (!((cin1 | cin2)) | cin3)))))))) | (!(b1) & ((b2 & ((b3 & ((b4 & ((cin1 & !(cin2) & !(cin3)) | (!(cin1) & cin3))) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & ((cin1 & !(cin3)) | (!(cin1) & (!(cin2) | cin3)))) | (!(b4) & (!((cin1 ^ cin2)) | cin3)))))) | (b3 & !(b4) & cin1 & !(cin3)) | (!(b3) & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & cin1 & (cin2 ^ cin3)))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & (!(cin1) | (cin2 ^ cin3))) | (!(b4) & !((cin1 & !(cin2))) & cin3))) | (!(b3) & ((b4 & (!(cin1) | cin3)) | (!(cin1) & cin3))))) | (!(b2) & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (!(b4) & !((cin1 ^ cin2)) & cin3))) | (!(b3) & !((b4 ^ cin1)) & cin3))))) | (!(b1) & ((b2 & ((b3 & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & (cin1 | !(cin2)) & cin3))) | (!(b3) & ((b4 & ((cin1 & (cin2 | cin3)) | (!(cin1) & !(cin2)))) | (!(b4) & !((cin1 & !(cin2))) & cin3))))) | (b3 & ((b4 & cin1 & !(cin3)) | (!(b4) & cin1 & cin3))) | (!(b3) & ((b4 & cin1 & (cin2 ^ cin3)) | (!(b4) & cin1 & cin2 & cin3))))))))))) | (!(a2) & ((a3 & ((a4 & ((b1 & ((b2 & ((b3 & ((!(b4) & cin1 & !(cin2)) | (cin1 & !(cin2) & !(cin3)))) | (!(b3) & ((b4 & ((cin1 & !(cin3)) | (!(cin1) & !(cin2) & cin3))) | (!(b4) & ((cin1 & (cin2 | cin3)) | (!(cin2) & cin3))))))) | (!(b2) & ((!(b3) & ((b4 & cin1 & (!(cin2) | cin3)) | (cin1 & !(cin2)))) | (b4 & cin1 & !(cin2) & cin3))))) | (b2 & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & cin1 & (cin2 ^ cin3)))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & cin1 & !(cin2)) | (cin1 & !(cin2) & cin3))) | (!(b3) & ((b4 & cin1 & (cin2 | cin3)) | (!(b4) & !((cin1 ^ cin2)) & cin3))))) | (!(b2) & !(b3) & ((b4 & cin1 & !(cin2)) | (cin1 & !(cin2) & cin3))))) | (b2 & ((b3 & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & cin1 & !(cin2) & cin3))) | (!(b3) & ((b4 & cin1 & (cin2 ^ cin3)) | (!(b4) & cin1 & cin2 & cin3))))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & ((cin1 & !(cin3)) | (!(cin1) & !(cin2) & cin3))) | (!(b4) & ((cin1 & (cin2 | cin3)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (!(cin1) & cin3))) | (!(b4) & (!((cin1 | cin2)) | cin3)))))) | (!(b2) & ((!(b3) & cin1) | (b4 & cin1 & (!(cin2) | cin3)) | (cin1 & !(cin2)))))) | (b2 & ((b3 & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & cin1 & (cin2 ^ cin3)))) | (!(b3) & ((b4 & cin1 & !(cin3)) | (!(b4) & cin1 & cin3))))) | (!(b2) & !(b3) & cin1 & !(cin2) & cin3))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (!(b4) & !((cin1 ^ cin2)) & cin3))) | (!(b3) & !((b4 ^ cin1)) & cin3))) | (!(b2) & ((!(b3) & ((b4 & cin1) | (cin1 & cin3))) | (b4 & cin1 & !(cin2)) | (cin1 & !(cin2) & cin3))))) | (b2 & ((b3 & ((b4 & cin1 & (cin2 ^ cin3)) | (!(b4) & cin1 & cin2 & cin3))) | (!(b3) & b4 & cin1 & cin3))) | (!(b2) & !(b3) & !(b4) & cin1 & !(cin2) & cin3))))))))))" ; + value : 16 ; + } + leakage_power () { + when : "((a1 & ((a2 & ((a3 & ((a4 & ((b1 & ((!(b2) & ((!(b3) & ((!(b4) & (!((cin1 | cin2)) | !(cin3))) | (!(cin1) & !(cin2) & !(cin3)))) | (!(b4) & !(cin2) & !(cin3)))) | (!(b3) & !(b4) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b1) & ((!(b2) & ((b3 & ((!(b4) & !(cin1) & cin2) | (!(cin1) & cin2 & !(cin3)))) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((!(b4) & ((!(cin1) & !(cin2)) | (!(cin2) & !(cin3)))) | (!(cin1) & !(cin2) & !(cin3)))) | (!(b3) & ((b4 & !(cin3)) | (!(b4) & ((cin1 & cin2) | cin3)))))) | (!(b2) & ((b3 & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & !(cin2)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & (!((cin1 | cin2)) | !(cin3))) | (!(b4) & cin3))))))) | (!(b1) & ((!(b2) & ((b3 & ((!(b4) & ((cin1 & !(cin2) & !(cin3)) | (!(cin1) & cin2))) | (!(cin1) & cin2))) | (!(b3) & ((!(b4) & cin1 & (!(cin2) | !(cin3))) | (cin1 & !(cin2) & !(cin3)))))) | (!(b3) & ((!(b4) & cin1 & (!(cin2) | !(cin3))) | (cin1 & !(cin2) & !(cin3)))) | (!(b4) & cin1 & !(cin2) & !(cin3)))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & !(b4) & !(cin3)) | (!(b3) & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))))))) | (!(b2) & ((b3 & ((!(b4) & (!((cin1 | cin2)) | !(cin3))) | (!(cin1) & !(cin2) & !(cin3)))) | (!(b3) & ((b4 & !((cin1 & cin2)) & !(cin3)) | (!(b4) & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))))))))) | (!(b1) & ((!(b3) & !(b4) & cin1 & !(cin3)) | (!(b4) & cin1 & !(cin2) & !(cin3)))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & !(cin3)) | (!(b4) & ((cin1 & cin2) | cin3)))) | (!(b3) & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))) | (!(b4) & (cin1 | cin2) & cin3))))) | (!(b2) & ((b3 & ((b4 & (!((cin1 | cin2)) | !(cin3))) | (!(b4) & cin3))) | (!(b3) & ((b4 & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))) | (!(b4) & cin2 & cin3))))))) | (!(b1) & ((b3 & ((!(b4) & cin1 & (!(cin2) | !(cin3))) | (cin1 & !(cin2) & !(cin3)))) | (!(b3) & ((b4 & cin1 & !(cin3)) | (!(b4) & cin1 & (cin2 | cin3)))))))))))) | (!(a2) & ((a3 & ((a4 & ((b1 & ((!(b3) & ((!(b4) & (!((cin1 | cin2)) | !(cin3))) | (!(cin1) & !(cin2) & !(cin3)))) | (!(b4) & !(cin2) & !(cin3)))) | (!(b1) & ((b2 & ((b3 & ((!(b4) & !(cin1) & cin2) | (!(cin1) & cin2 & !(cin3)))) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(b2) & !(cin1)))))) | (!(a4) & ((b1 & ((b3 & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & !(cin2)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & (!((cin1 | cin2)) | !(cin3))) | (!(b4) & cin3))))) | (!(b1) & ((b2 & ((b3 & ((!(b4) & ((cin1 & !(cin2) & !(cin3)) | (!(cin1) & cin2))) | (!(cin1) & cin2))) | (!(b3) & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & cin1 & (cin2 ^ cin3)))))) | (!(b2) & ((b3 & ((b4 & !(cin1)) | (!(cin1) & (cin2 | cin3)))) | (b4 & !(cin1)) | (!(cin1) & cin3))))))))) | (!(a3) & ((a4 & ((b1 & ((b3 & ((!(b4) & (!((cin1 | cin2)) | !(cin3))) | (!(cin1) & !(cin2) & !(cin3)))) | (!(b3) & ((b4 & !((cin1 & cin2)) & !(cin3)) | (!(b4) & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))))))) | (!(b1) & ((b2 & ((!(b3) & !(b4) & cin1 & !(cin3)) | (!(b4) & cin1 & !(cin2) & !(cin3)))) | (!(b2) & ((b3 & !(cin1)) | (!(cin1) & (cin2 | !(cin3))))))))) | (!(a4) & ((b1 & ((b3 & ((b4 & (!((cin1 | cin2)) | !(cin3))) | (!(b4) & cin3))) | (!(b3) & ((b4 & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))) | (!(b4) & cin2 & cin3))))) | (!(b1) & ((b2 & ((b3 & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & cin1 & (cin2 ^ cin3)))) | (!(b3) & ((b4 & cin1 & !(cin3)) | (!(b4) & cin1 & cin3))))) | (!(b2) & ((b3 & ((b4 & !(cin1)) | (!(cin1) & cin3))) | (b4 & !(cin1)) | (!(cin1) & cin2 & cin3))))))))))))) | (!(a1) & ((a2 & ((a3 & ((a4 & ((b1 & ((!(b2) & ((b3 & !(cin1)) | (!(b3) & ((!(b4) & ((!(cin1) & (cin2 | !(cin3))) | (!(cin2) & !(cin3)))) | (!(cin1) & (cin2 | !(cin3))))))) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(b1) & ((!(b2) & !(cin1)) | (b3 & ((!(b4) & !(cin1)) | (!(cin1) & (cin2 | !(cin3))))) | (!(b4) & !(cin1) & (cin2 | !(cin3))) | (!(cin1) & !(cin3)))))) | (!(a4) & ((b1 & ((!(b2) & ((b3 & ((b4 & !(cin1)) | (!(b4) & (cin1 ^ (cin2 | cin3))))) | (!(b3) & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & (cin1 ^ (cin2 & cin3))))))) | (b3 & !(b4) & (cin1 ^ cin2) & !(cin3)) | (!(b3) & ((!(b4) & cin1 & (!(cin2) | !(cin3))) | (cin1 & !(cin2) & !(cin3)))))) | (!(b1) & ((!(b2) & ((b3 & ((b4 & !(cin1)) | (!(cin1) & (cin2 | cin3)))) | (!(b3) & ((b4 & !(cin1)) | (!(b4) & (cin1 ^ cin3)))))) | (b3 & ((b4 & !(cin1)) | (!(cin1) & (cin2 | cin3)))) | (!(b3) & ((b4 & !(cin1)) | (!(b4) & ((cin1 & !(cin3)) | (!(cin1) & cin2 & cin3))))))))))) | (!(a3) & ((a4 & ((b1 & ((!(b2) & ((b3 & ((!(b4) & ((!(cin1) & (cin2 | !(cin3))) | (!(cin2) & !(cin3)))) | (!(cin1) & (cin2 | !(cin3))))) | (!(b3) & ((b4 & !(cin1) & !(cin3)) | (!(b4) & (cin1 | cin2) & !(cin3)))))) | (!(b3) & !(b4) & cin1 & !(cin3)) | (!(b4) & cin1 & !(cin2) & !(cin3)))) | (!(b1) & ((!(b2) & ((!((b3 | b4)) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (b3 & ((!(b4) & !(cin1) & (cin2 | !(cin3))) | (!(cin1) & !(cin3)))) | (!(b3) & ((!(b4) & (cin1 ^ cin2) & !(cin3)) | (!(cin1) & cin2 & !(cin3)))))))) | (!(a4) & ((b1 & ((!(b2) & ((b3 & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & (cin1 ^ (cin2 & cin3))))) | (!(b3) & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))))) | (b3 & ((!(b4) & cin1 & (!(cin2) | !(cin3))) | (cin1 & !(cin2) & !(cin3)))) | (!(b3) & ((b4 & cin1 & !(cin3)) | (!(b4) & cin1 & (cin2 | cin3)))))) | (!(b1) & ((!(b2) & ((!(b3) & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (!(cin1) & cin3))))) | (b4 & !(cin1)) | (!(b4) & (cin1 ^ cin3)))) | (b3 & ((b4 & !(cin1)) | (!(b4) & ((cin1 & !(cin3)) | (!(cin1) & cin2 & cin3))))) | (!(b3) & ((b4 & ((cin1 & !(cin2) & !(cin3)) | (!(cin1) & cin2))) | (!(b4) & cin1 & (!(cin2) | !(cin3))))))))))))) | (!(a2) & ((a3 & ((a4 & ((b1 & ((b2 & ((b3 & !(cin1)) | (!(b3) & ((!(b4) & ((!(cin1) & (cin2 | !(cin3))) | (!(cin2) & !(cin3)))) | (!(cin1) & (cin2 | !(cin3))))))) | (!(b2) & ((b3 & ((b4 & ((cin1 & (cin2 | !(cin3))) | (!(cin1) & (!(cin2) | cin3)))) | (!(b4) & (cin1 | !(cin2))))) | (!(b3) & ((!(b4) & (!(cin1) | cin2)) | !(cin1) | (cin2 & !(cin3)))))))) | (!(b1) & ((b2 & ((!((b3 | b4)) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (!(b2) & ((!(b3) & (cin1 | (!(cin2) & cin3))) | cin1)))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & !(cin1)) | (!(b4) & (cin1 ^ (cin2 | cin3))))) | (!(b3) & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & ((cin1 & (cin2 ^ cin3)) | (!(cin1) & cin2 & cin3))))))) | (!(b2) & ((b3 & ((b4 & (cin1 | !(cin2))) | (cin1 & (cin2 | cin3)) | (!(cin2) & cin3))) | (!(b3) & ((b4 & (!(cin1) | cin2)) | (!((cin1 & !(cin2))) & cin3))))))) | (!(b1) & ((b2 & ((b3 & ((b4 & !(cin1)) | (!(b4) & (cin1 ^ (cin2 | cin3))))) | (!(b3) & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (!(cin1) & cin3))))))) | (!(b2) & ((b3 & ((b4 & cin1) | (cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & cin1) | (!(b4) & (cin1 | !(cin2)) & cin3))))))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & ((!(b4) & ((!(cin1) & (cin2 | !(cin3))) | (!(cin2) & !(cin3)))) | (!(cin1) & (cin2 | !(cin3))))) | (!(b3) & ((b4 & !(cin1) & !(cin3)) | (!(b4) & (cin1 | cin2) & !(cin3)))))) | (!(b2) & ((b3 & ((!(b4) & (!(cin1) | cin2)) | !(cin1) | (cin2 & !(cin3)))) | !(cin1))))) | (!(b1) & ((b2 & ((!(b3) & ((!(b4) & (!(cin1) | !(cin3))) | !(cin1))) | (!(b4) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (!(b2) & ((b3 & (cin1 | (!(cin2) & cin3))) | (!(b3) & ((cin1 & (cin2 | !(cin3))) | (!(cin1) & (!(cin2) | cin3)))))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & ((cin1 & (cin2 ^ cin3)) | (!(cin1) & cin2 & cin3))))) | (!(b3) & (b4 ^ (cin1 & cin3))))) | (!(b2) & ((b3 & ((b4 & (!(cin1) | cin2)) | (!((cin1 & !(cin2))) & cin3))) | (b4 & !(cin1)) | (!(cin1) & cin3))))) | (!(b1) & ((b2 & ((b3 & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (!(cin1) & cin3))))) | (!(b3) & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & ((cin1 & cin2) | cin3)))))) | (!(b2) & ((b3 & ((b4 & cin1) | (!(b4) & (cin1 | !(cin2)) & cin3))) | (!(b3) & ((b4 & (cin1 | !(cin2))) | (!(b4) & !((cin1 & !(cin2))) & cin3))))))))))))))))" ; + value : 15 ; + } + leakage_power () { + when : "((!(a1) & ((!(a2) & ((!(a3) & !(a4) & ((!(b1) & ((!(b2) & ((!(b3) & !(b4) & !((cin1 & cin2)) & !(cin3)) | (!(b4) & !(cin1) & !(cin3)))) | (!(b3) & !(b4) & !(cin1) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b2) & ((!(b3) & !(b4) & !(cin1) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))))) | (!(a4) & ((!(b1) & ((!(b2) & ((!(b3) & !(b4) & !(cin1) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))))) | (!(a3) & !(a4) & !(b1) & !(b2) & ((!(b3) & !(b4) & !(cin1) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(a4) & !(b1) & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(a2) & !(a3) & !(a4) & !(b1) & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))" ; + value : 12 ; + } + pin (cin3) { + direction : input ; + capacitance : 320.01 ; + } + pin (cin2) { + direction : input ; + capacitance : 320.61 ; + } + pin (cin1) { + direction : input ; + capacitance : 379.19 ; + } + pin (b4) { + direction : input ; + capacitance : 321.96 ; + } + pin (b3) { + direction : input ; + capacitance : 320.61 ; + } + pin (b2) { + direction : input ; + capacitance : 486.14 ; + } + pin (b1) { + direction : input ; + capacitance : 434.11 ; + } + pin (a4) { + direction : input ; + capacitance : 322.56 ; + } + pin (a3) { + direction : input ; + capacitance : 317.46 ; + } + pin (a2) { + direction : input ; + capacitance : 487.04 ; + } + pin (a1) { + direction : input ; + capacitance : 407.22 ; + } + pin (sout) { + function : "(((b4 | a4 | cin3) & ((a3 & cin2 & b3) | (!((b2 | a2)) & (!(a1) | !(b1))) | (!((a1 & b1)) & !(cin1)))) | (a3 & cin2 & b3))" ; + direction : output ; + capacitance : 148.59 ; + timing (maxd_sout_a3_positive_unate) { + related_pin : "a3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("22731.1, 22731.1, 22731.1, 22952.1, 23386.7", \ + "22720.0, 22720.0, 22720.0, 22941.0, 23375.6", \ + "22697.9, 22697.9, 22697.9, 22918.9, 23353.5", \ + "22653.6, 22653.6, 22653.6, 22874.6, 23309.2", \ + "22565.0, 22565.0, 22565.0, 22786.0, 23220.6"); + } + rise_transition (inslew_load_5x5__2) { + values ("14038.1, 14038.1, 14038.1, 14225.0, 14600.8", \ + "14038.1, 14038.1, 14038.1, 14225.0, 14600.8", \ + "14038.1, 14038.1, 14038.1, 14225.0, 14600.8", \ + "14038.1, 14038.1, 14038.1, 14225.0, 14600.8", \ + "14038.1, 14038.1, 14038.1, 14225.0, 14600.8"); + } + cell_fall (inslew_load_5x5__2) { + values ("37709.1, 37709.1, 37709.1, 37901.8, 38306.1", \ + "37694.3, 37694.3, 37694.3, 37887.0, 38291.3", \ + "37664.8, 37664.8, 37664.8, 37857.5, 38261.8", \ + "37605.7, 37605.7, 37605.7, 37798.4, 38202.7", \ + "37487.6, 37487.6, 37487.6, 37680.3, 38084.6"); + } + fall_transition (inslew_load_5x5__2) { + values ("24081.8, 24081.8, 24081.8, 24215.1, 24485.1", \ + "24081.8, 24081.8, 24081.8, 24215.1, 24485.1", \ + "24081.8, 24081.8, 24081.8, 24215.1, 24485.1", \ + "24081.8, 24081.8, 24081.8, 24215.1, 24485.1", \ + "24081.8, 24081.8, 24081.8, 24215.1, 24485.1"); + } + } + timing (maxd_sout_a4_positive_unate) { + related_pin : "a4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("13115.9, 13115.9, 13115.9, 13351.2, 13805.3", \ + "13114.0, 13114.0, 13114.0, 13349.3, 13803.4", \ + "13110.2, 13110.2, 13110.2, 13345.5, 13799.6", \ + "13102.5, 13102.5, 13102.5, 13337.8, 13791.9", \ + "13087.3, 13087.3, 13087.3, 13322.6, 13776.7"); + } + rise_transition (inslew_load_5x5__2) { + values ("7349.9, 7349.9, 7349.9, 7539.1, 7911.6", \ + "7349.9, 7349.9, 7349.9, 7539.1, 7911.6", \ + "7349.9, 7349.9, 7349.9, 7539.1, 7911.6", \ + "7349.9, 7349.9, 7349.9, 7539.1, 7911.6", \ + "7349.9, 7349.9, 7349.9, 7539.1, 7911.6"); + } + cell_fall (inslew_load_5x5__2) { + values ("29965.7, 29965.7, 29965.7, 30160.4, 30563.5", \ + "29974.1, 29974.1, 29974.1, 30168.8, 30571.8", \ + "29981.0, 29981.0, 29981.0, 30175.7, 30578.8", \ + "29961.6, 29961.6, 29961.6, 30156.3, 30559.4", \ + "29947.8, 29947.8, 29947.8, 30142.5, 30545.6"); + } + fall_transition (inslew_load_5x5__2) { + values ("19195.1, 19195.1, 19195.1, 19331.5, 19610.7", \ + "19209.4, 19209.4, 19209.4, 19345.6, 19624.9", \ + "19229.8, 19229.8, 19229.8, 19366.2, 19645.2", \ + "19244.3, 19244.3, 19244.3, 19380.5, 19659.6", \ + "19279.9, 19279.9, 19279.9, 19416.1, 19695.0"); + } + } + timing (maxd_sout_b3_positive_unate) { + related_pin : "b3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("21371.1, 21371.1, 21371.1, 21591.8, 22028.9", \ + "21369.0, 21369.0, 21369.0, 21589.8, 22026.8", \ + "21360.0, 21360.0, 21360.0, 21580.7, 22017.8", \ + "21343.5, 21343.5, 21343.5, 21564.2, 22001.3", \ + "21311.6, 21311.6, 21311.6, 21532.3, 21969.4"); + } + rise_transition (inslew_load_5x5__2) { + values ("13206.9, 13206.9, 13206.9, 13394.5, 13770.6", \ + "13209.8, 13209.8, 13209.8, 13397.4, 13773.5", \ + "13210.4, 13210.4, 13210.4, 13398.0, 13774.0", \ + "13210.4, 13210.4, 13210.4, 13398.0, 13774.1", \ + "13210.4, 13210.4, 13210.4, 13398.0, 13774.0"); + } + cell_fall (inslew_load_5x5__2) { + values ("36855.2, 36855.2, 36855.2, 37048.1, 37452.4", \ + "36840.4, 36840.4, 36840.4, 37033.3, 37437.6", \ + "36810.9, 36810.9, 36810.9, 37003.8, 37408.1", \ + "36751.9, 36751.9, 36751.9, 36944.8, 37349.1", \ + "36633.7, 36633.7, 36633.7, 36826.6, 37230.9"); + } + fall_transition (inslew_load_5x5__2) { + values ("23500.0, 23500.0, 23500.0, 23633.4, 23904.5", \ + "23500.0, 23500.0, 23500.0, 23633.4, 23904.5", \ + "23500.0, 23500.0, 23500.0, 23633.4, 23904.5", \ + "23500.0, 23500.0, 23500.0, 23633.4, 23904.5", \ + "23500.0, 23500.0, 23500.0, 23633.4, 23904.5"); + } + } + timing (maxd_sout_b4_positive_unate) { + related_pin : "b4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("13414.7, 13414.7, 13414.7, 13649.9, 14104.9", \ + "13412.8, 13412.8, 13412.8, 13648.0, 14103.0", \ + "13409.0, 13409.0, 13409.0, 13644.2, 14099.2", \ + "13401.4, 13401.4, 13401.4, 13636.6, 14091.6", \ + "13386.2, 13386.2, 13386.2, 13621.4, 14076.4"); + } + rise_transition (inslew_load_5x5__2) { + values ("7543.8, 7543.8, 7543.8, 7733.3, 8105.6", \ + "7543.8, 7543.8, 7543.8, 7733.3, 8105.6", \ + "7543.8, 7543.8, 7543.8, 7733.3, 8105.6", \ + "7543.8, 7543.8, 7543.8, 7733.3, 8105.6", \ + "7543.8, 7543.8, 7543.8, 7733.3, 8105.6"); + } + cell_fall (inslew_load_5x5__2) { + values ("33454.0, 33454.0, 33454.0, 33647.8, 34050.9", \ + "33447.2, 33447.2, 33447.2, 33641.0, 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144343.2, 144343.2, 146200.5, 149915.2", \ + "144809.7, 144809.7, 144809.7, 146667.1, 150381.7"); + } + } + internal_power (energy_pos_sout_b3) { + related_pin : "b3" ; + rise_power (energy_inslew_load_5x5__2) { + values ("112765.5, 112765.5, 112765.5, 114622.8, 118337.5", \ + "112800.5, 112800.5, 112800.5, 114657.9, 118372.6", \ + "112838.1, 112838.1, 112838.1, 114695.4, 118410.1", \ + "112906.4, 112906.4, 112906.4, 114763.8, 118478.4", \ + "118614.4, 118614.4, 118614.4, 118614.4, 118614.4"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("177238.0, 177238.0, 177238.0, 179095.3, 182810.0", \ + "182835.5, 182835.5, 182835.5, 182835.5, 182835.5", \ + "182886.5, 182886.5, 182886.5, 182886.5, 182886.5", \ + "182988.5, 182988.5, 182988.5, 182988.5, 182988.5", \ + "183192.4, 183192.4, 183192.4, 183192.4, 183192.4"); + } + } + internal_power (energy_pos_sout_b4) { + related_pin : "b4" ; + rise_power (energy_inslew_load_5x5__2) { + values ("76353.4, 76353.4, 76353.4, 78210.8, 81925.5", \ + "81934.9, 81934.9, 81934.9, 81934.9, 81934.9", \ + "81953.7, 81953.7, 81953.7, 81953.7, 81953.7", \ + "81991.4, 81991.4, 81991.4, 81991.4, 81991.4", \ + "82066.7, 82066.7, 82066.7, 82066.7, 82066.7"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("160760.3, 160760.3, 160760.3, 162617.7, 166332.4", \ + "160821.8, 160821.8, 160821.8, 162679.1, 166393.8", \ + "160891.2, 160891.2, 160891.2, 162748.6, 166463.3", \ + "161089.0, 161089.0, 161089.0, 162946.4, 166661.1", \ + "161428.0, 161428.0, 161428.0, 163285.3, 167000.0"); + } + } + internal_power (energy_pos_sout_cin2) { + related_pin : "cin2" ; + rise_power (energy_inslew_load_5x5__2) { + values ("105812.9, 105812.9, 105812.9, 107670.2, 111384.9", \ + "105892.4, 105892.4, 105892.4, 107749.7, 111464.4", \ + "106054.2, 106054.2, 106054.2, 107911.5, 111626.2", \ + "106163.8, 106163.8, 106163.8, 108021.2, 111735.8", \ + "106309.9, 106309.9, 106309.9, 108167.3, 111882.0"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("170909.5, 170909.5, 170909.5, 172766.9, 176481.6", \ + "176501.1, 176501.1, 176501.1, 176501.1, 176501.1", \ + "176540.3, 176540.3, 176540.3, 176540.3, 176540.3", \ + "176618.6, 176618.6, 176618.6, 176618.6, 176618.6", \ + "176775.3, 176775.3, 176775.3, 176775.3, 176775.3"); + } + } + internal_power (energy_pos_sout_cin3) { + related_pin : "cin3" ; + rise_power (energy_inslew_load_5x5__2) { + values ("69662.2, 69662.2, 69662.2, 71519.6, 75234.3", \ + "75238.7, 75238.7, 75238.7, 75238.7, 75238.7", \ + "75247.6, 75247.6, 75247.6, 75247.6, 75247.6", \ + "75265.5, 75265.5, 75265.5, 75265.5, 75265.5", \ + "75301.1, 75301.1, 75301.1, 75301.1, 75301.1"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("127514.9, 127514.9, 127514.9, 129372.2, 133086.9", \ + "127400.2, 127400.2, 127400.2, 129257.5, 132972.2", \ + "127757.6, 127757.6, 127757.6, 129615.0, 133329.6", \ + "128294.4, 128294.4, 128294.4, 130151.8, 133866.5", \ + "128875.3, 128875.3, 128875.3, 130732.6, 134447.3"); + } + } + internal_power (energy_neg_sout_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__2) { + values ("160023.4, 160023.4, 160023.4, 161880.7, 165595.4", \ + "165639.2, 165639.2, 165639.2, 165639.2, 165639.2", \ + "165726.8, 165726.8, 165726.8, 165726.8, 165726.8", \ + "165902.1, 165902.1, 165902.1, 165902.1, 165902.1", \ + "166252.6, 166252.6, 166252.6, 166252.6, 166252.6"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("128251.7, 128251.7, 128251.7, 130109.1, 133823.8", \ + "133843.6, 133843.6, 133843.6, 133843.6, 133843.6", \ + "133883.3, 133883.3, 133883.3, 133883.3, 133883.3", \ + "133962.6, 133962.6, 133962.6, 133962.6, 133962.6", \ + "134121.2, 134121.2, 134121.2, 134121.2, 134121.2"); + } + } + internal_power (energy_neg_sout_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__2) { + values ("127901.7, 127901.7, 127901.7, 129759.1, 133473.7", \ + "128023.0, 128023.0, 128023.0, 129880.4, 133595.0", \ + "128217.4, 128217.4, 128217.4, 130074.7, 133789.4", \ + "128448.0, 128448.0, 128448.0, 130305.3, 134020.0", \ + "128936.3, 128936.3, 128936.3, 130793.6, 134508.3"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("123156.1, 123156.1, 123156.1, 125013.4, 128728.1", \ + "128742.2, 128742.2, 128742.2, 128742.2, 128742.2", \ + "128770.3, 128770.3, 128770.3, 128770.3, 128770.3", \ + "128826.7, 128826.7, 128826.7, 128826.7, 128826.7", \ + "128939.4, 128939.4, 128939.4, 128939.4, 128939.4"); + } + } + internal_power (energy_neg_sout_b1) { + related_pin : "b1" ; + rise_power (energy_inslew_load_5x5__2) { + values ("156068.8, 156068.8, 156068.8, 157926.1, 161640.8", \ + "161677.1, 161677.1, 161677.1, 161677.1, 161677.1", \ + "161749.7, 161749.7, 161749.7, 161749.7, 161749.7", \ + "161895.0, 161895.0, 161895.0, 161895.0, 161895.0", \ + "162185.5, 162185.5, 162185.5, 162185.5, 162185.5"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("122544.6, 122544.6, 122544.6, 124402.0, 128116.6", \ + "122578.4, 122578.4, 122578.4, 124435.7, 128150.4", \ + "122622.9, 122622.9, 122622.9, 124480.2, 128194.9", \ + "122709.8, 122709.8, 122709.8, 124567.2, 128281.9", \ + "122880.4, 122880.4, 122880.4, 124737.7, 128452.4"); + } + } + internal_power (energy_neg_sout_b2) { + related_pin : "b2" ; + rise_power (energy_inslew_load_5x5__2) { + values ("142320.8, 142320.8, 142320.8, 144178.2, 147892.8", \ + "142352.0, 142352.0, 142352.0, 144209.3, 147924.0", \ + "142466.6, 142466.6, 142466.6, 144324.0, 148038.6", \ + "142642.3, 142642.3, 142642.3, 144499.7, 148214.3", \ + "142992.2, 142992.2, 142992.2, 144849.5, 148564.2"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("131342.0, 131342.0, 131342.0, 133199.3, 136914.0", \ + "136933.3, 136933.3, 136933.3, 136933.3, 136933.3", \ + "136971.8, 136971.8, 136971.8, 136971.8, 136971.8", \ + "137048.9, 137048.9, 137048.9, 137048.9, 137048.9", \ + "137203.1, 137203.1, 137203.1, 137203.1, 137203.1"); + } + } + internal_power (energy_neg_sout_cin1) { + related_pin : "cin1" ; + rise_power (energy_inslew_load_5x5__2) { + values ("119842.9, 119842.9, 119842.9, 121700.3, 125414.9", \ + "119898.9, 119898.9, 119898.9, 121756.2, 125470.9", \ + "119970.2, 119970.2, 119970.2, 121827.6, 125542.2", \ + "120128.4, 120128.4, 120128.4, 121985.7, 125700.4", \ + "120374.4, 120374.4, 120374.4, 122231.8, 125946.4"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("117988.8, 117988.8, 117988.8, 119846.1, 123560.8", \ + "118018.2, 118018.2, 118018.2, 119875.6, 123590.2", \ + "118064.0, 118064.0, 118064.0, 119921.4, 123636.0", \ + "118126.9, 118126.9, 118126.9, 119984.2, 123698.9", \ + "118251.7, 118251.7, 118251.7, 120109.0, 123823.7"); + } + } + } + pin (cout) { + function : "(((b2 | a2) & ((a1 & b1) | cin1)) | (a1 & b1))" ; + direction : output ; + capacitance : 148.59 ; + timing (maxd_cout_a1_positive_unate) { + related_pin : "a1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("14845.6, 14845.6, 14845.6, 15079.9, 15535.8", \ + "14843.1, 14843.1, 14843.1, 15077.4, 15533.3", \ + "14838.1, 14838.1, 14838.1, 15072.4, 15528.3", \ + "14828.1, 14828.1, 14828.1, 15062.4, 15518.3", \ + "14808.0, 14808.0, 14808.0, 15042.3, 15498.2"); + } + rise_transition (inslew_load_5x5__2) { + values ("8355.7, 8355.7, 8355.7, 8545.9, 8919.6", \ + "8355.7, 8355.7, 8355.7, 8545.9, 8919.6", \ + "8355.7, 8355.7, 8355.7, 8545.9, 8919.6", \ + "8355.7, 8355.7, 8355.7, 8545.9, 8919.6", \ + "8355.7, 8355.7, 8355.7, 8545.9, 8919.6"); + } + cell_fall (inslew_load_5x5__2) { + values ("22819.9, 22819.9, 22819.9, 23028.5, 23444.2", \ + "22813.5, 22813.5, 22813.5, 23022.1, 23437.8", \ + "22800.6, 22800.6, 22800.6, 23009.2, 23424.9", \ + "22774.9, 22774.9, 22774.9, 22983.5, 23399.2", \ + "22723.6, 22723.6, 22723.6, 22932.2, 23347.9"); + } + fall_transition (inslew_load_5x5__2) { + values ("13294.0, 13294.0, 13294.0, 13437.6, 13729.6", \ + "13294.0, 13294.0, 13294.0, 13437.6, 13729.6", \ + "13294.0, 13294.0, 13294.0, 13437.6, 13729.6", \ + "13294.0, 13294.0, 13294.0, 13437.6, 13729.6", \ + "13294.0, 13294.0, 13294.0, 13437.6, 13729.6"); + } + } + timing (maxd_cout_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("16804.3, 16804.3, 16804.3, 17038.0, 17494.6", \ + "16799.1, 16799.1, 16799.1, 17032.8, 17489.4", \ + "16788.8, 16788.8, 16788.8, 17022.5, 17479.1", \ + "16768.2, 16768.2, 16768.2, 17001.9, 17458.5", \ + "16727.0, 16727.0, 16727.0, 16960.7, 17417.3"); + } + rise_transition (inslew_load_5x5__2) { + values ("9093.5, 9093.5, 9093.5, 9282.3, 9656.4", \ + "9093.5, 9093.5, 9093.5, 9282.3, 9656.4", \ + "9093.5, 9093.5, 9093.5, 9282.3, 9656.4", \ + "9093.5, 9093.5, 9093.5, 9282.3, 9656.4", \ + "9093.5, 9093.5, 9093.5, 9282.3, 9656.4"); + } + cell_fall (inslew_load_5x5__2) { + values ("16127.5, 16127.5, 16127.5, 16326.4, 16722.0", \ + "16150.2, 16150.2, 16150.2, 16349.1, 16744.7", \ + "16179.3, 16179.3, 16179.3, 16378.2, 16773.8", \ + "16184.2, 16184.2, 16184.2, 16383.1, 16778.7", \ + "16222.4, 16222.4, 16222.4, 16421.7, 16817.3"); + } + fall_transition (inslew_load_5x5__2) { + values ("9132.0, 9132.0, 9132.0, 9276.5, 9553.5", \ + "9152.6, 9152.6, 9152.6, 9297.0, 9574.1", \ + "9182.2, 9182.2, 9182.2, 9326.6, 9603.6", \ + "9204.0, 9204.0, 9204.0, 9348.2, 9625.3", \ + "9253.6, 9253.6, 9253.6, 9397.9, 9675.0"); + } + } + timing (maxd_cout_b1_positive_unate) { + related_pin : "b1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("13762.9, 13762.9, 13762.9, 13997.8, 14453.2", \ + "13767.9, 13767.9, 13767.9, 14002.8, 14458.2", \ + "13772.5, 13772.5, 13772.5, 14007.4, 14462.8", \ + "13785.5, 13785.5, 13785.5, 14020.4, 14475.8", \ + "13812.5, 13812.5, 13812.5, 14047.4, 14502.8"); + } + rise_transition (inslew_load_5x5__2) { + values ("7678.5, 7678.5, 7678.5, 7869.5, 8243.8", \ + "7682.0, 7682.0, 7682.0, 7873.0, 8247.3", \ + "7682.6, 7682.6, 7682.6, 7873.6, 8247.9", \ + "7683.1, 7683.1, 7683.1, 7874.2, 8248.5", \ + "7683.4, 7683.4, 7683.4, 7874.4, 8248.7"); + } + cell_fall (inslew_load_5x5__2) { + values ("22151.1, 22151.1, 22151.1, 22359.7, 22771.7", \ + "22144.7, 22144.7, 22144.7, 22353.3, 22765.3", \ + "22131.8, 22131.8, 22131.8, 22340.4, 22752.4", \ + "22106.2, 22106.2, 22106.2, 22314.8, 22726.8", \ + "22054.8, 22054.8, 22054.8, 22263.4, 22675.4"); + } + fall_transition (inslew_load_5x5__2) { + values ("12789.5, 12789.5, 12789.5, 12933.6, 13224.7", \ + "12789.5, 12789.5, 12789.5, 12933.6, 13224.7", \ + "12789.5, 12789.5, 12789.5, 12933.6, 13224.7", \ + "12789.5, 12789.5, 12789.5, 12933.6, 13224.7", \ + "12789.5, 12789.5, 12789.5, 12933.6, 13224.7"); + } + } + timing (maxd_cout_b2_positive_unate) { + related_pin : "b2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("18724.8, 18724.8, 18724.8, 18957.9, 19415.2", \ + "18719.6, 18719.6, 18719.6, 18952.7, 19410.0", \ + "18709.3, 18709.3, 18709.3, 18942.4, 19399.7", \ + "18688.7, 18688.7, 18688.7, 18921.8, 19379.1", \ + "18647.5, 18647.5, 18647.5, 18880.6, 19337.9"); + } + rise_transition (inslew_load_5x5__2) { + values ("10308.9, 10308.9, 10308.9, 10496.0, 10870.6", \ + "10308.9, 10308.9, 10308.9, 10496.0, 10870.6", \ + "10308.9, 10308.9, 10308.9, 10496.0, 10870.6", \ + "10308.9, 10308.9, 10308.9, 10496.0, 10870.6", \ + "10308.9, 10308.9, 10308.9, 10496.0, 10870.6"); + } + cell_fall (inslew_load_5x5__2) { + values ("19284.5, 19284.5, 19284.5, 19493.3, 19892.0", \ + "19271.7, 19271.7, 19271.7, 19480.5, 19879.2", \ + "19267.4, 19267.4, 19267.4, 19476.2, 19875.0", \ + "19244.0, 19244.0, 19244.0, 19452.8, 19851.6", \ + "19211.1, 19211.1, 19211.1, 19419.9, 19818.8"); + } + fall_transition (inslew_load_5x5__2) { + values ("11002.6, 11002.6, 11002.6, 11149.5, 11430.2", \ + "11001.7, 11001.7, 11001.7, 11148.5, 11429.2", \ + "11012.2, 11012.2, 11012.2, 11159.1, 11439.8", \ + "11020.7, 11020.7, 11020.7, 11167.6, 11448.4", \ + "11037.2, 11037.2, 11037.2, 11184.0, 11464.8"); + } + } + timing (maxd_cout_cin1_positive_unate) { + related_pin : "cin1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("15123.2, 15123.2, 15123.2, 15357.5, 15813.4", \ + "15128.8, 15128.8, 15128.8, 15363.1, 15818.9", \ + "15138.4, 15138.4, 15138.4, 15372.7, 15828.5", \ + "15152.3, 15152.3, 15152.3, 15386.6, 15842.4", \ + "15185.8, 15185.8, 15185.8, 15420.1, 15876.0"); + } + rise_transition (inslew_load_5x5__2) { + values ("8334.5, 8334.5, 8334.5, 8524.7, 8898.4", \ + "8338.4, 8338.4, 8338.4, 8528.6, 8902.3", \ + "8342.6, 8342.6, 8342.6, 8532.8, 8906.5", \ + "8343.1, 8343.1, 8343.1, 8533.3, 8907.0", \ + "8343.7, 8343.7, 8343.7, 8533.9, 8907.6"); + } + cell_fall (inslew_load_5x5__2) { + values ("14853.0, 14853.0, 14853.0, 15053.1, 15468.1", \ + "14862.4, 14862.4, 14862.4, 15062.6, 15477.1", \ + "14866.3, 14866.3, 14866.3, 15066.5, 15480.6", \ + "14886.0, 14886.0, 14886.0, 15086.2, 15499.4", \ + "14912.5, 14912.5, 14912.5, 15112.7, 15525.1"); + } + fall_transition (inslew_load_5x5__2) { + values ("7527.4, 7527.4, 7527.4, 7670.7, 7943.4", \ + "7534.5, 7534.5, 7534.5, 7677.9, 7950.7", \ + "7539.3, 7539.3, 7539.3, 7682.7, 7955.6", \ + "7552.4, 7552.4, 7552.4, 7695.7, 7969.1", \ + "7562.4, 7562.4, 7562.4, 7705.7, 7979.3"); + } + } + internal_power (energy_pos_cout_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__2) { + values ("92058.8, 92058.8, 92058.8, 93916.1, 97630.8", \ + "97650.6, 97650.6, 97650.6, 97650.6, 97650.6", \ + "97690.3, 97690.3, 97690.3, 97690.3, 97690.3", \ + "97769.6, 97769.6, 97769.6, 97769.6, 97769.6", \ + "97928.2, 97928.2, 97928.2, 97928.2, 97928.2"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("128732.3, 128732.3, 128732.3, 130589.7, 134304.3", \ + "134348.1, 134348.1, 134348.1, 134348.1, 134348.1", \ + "134435.8, 134435.8, 134435.8, 134435.8, 134435.8", \ + "134611.0, 134611.0, 134611.0, 134611.0, 134611.0", \ + "134961.5, 134961.5, 134961.5, 134961.5, 134961.5"); + } + } + internal_power (energy_pos_cout_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__2) { + values ("88898.0, 88898.0, 88898.0, 90755.4, 94470.0", \ + "94484.1, 94484.1, 94484.1, 94484.1, 94484.1", \ + "94512.3, 94512.3, 94512.3, 94512.3, 94512.3", \ + "94568.7, 94568.7, 94568.7, 94568.7, 94568.7", \ + "94681.3, 94681.3, 94681.3, 94681.3, 94681.3"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("87472.0, 87472.0, 87472.0, 89329.3, 93044.0", \ + "87637.2, 87637.2, 87637.2, 89494.5, 93209.2", \ + "87894.5, 87894.5, 87894.5, 89751.9, 93466.6", \ + "88171.4, 88171.4, 88171.4, 90028.8, 93743.5", \ + "88765.6, 88765.6, 88765.6, 90623.0, 94337.6"); + } + } + internal_power (energy_pos_cout_b1) { + related_pin : "b1" ; + rise_power (energy_inslew_load_5x5__2) { + values ("84605.0, 84605.0, 84605.0, 86462.3, 90177.0", \ + "84647.8, 84647.8, 84647.8, 86505.1, 90219.8", \ + "84693.7, 84693.7, 84693.7, 86551.1, 90265.8", \ + "84782.2, 84782.2, 84782.2, 86639.5, 90354.2", \ + "84953.3, 84953.3, 84953.3, 86810.7, 90525.3"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("123649.3, 123649.3, 123649.3, 125506.7, 129221.4", \ + "129257.7, 129257.7, 129257.7, 129257.7, 129257.7", \ + "129330.3, 129330.3, 129330.3, 129330.3, 129330.3", \ + "129475.6, 129475.6, 129475.6, 129475.6, 129475.6", \ + "129766.1, 129766.1, 129766.1, 129766.1, 129766.1"); + } + } + internal_power (energy_pos_cout_b2) { + related_pin : "b2" ; + rise_power (energy_inslew_load_5x5__2) { + values ("100326.9, 100326.9, 100326.9, 102184.2, 105898.9", \ + "105918.2, 105918.2, 105918.2, 105918.2, 105918.2", \ + "105956.7, 105956.7, 105956.7, 105956.7, 105956.7", \ + "106033.8, 106033.8, 106033.8, 106033.8, 106033.8", \ + "106188.0, 106188.0, 106188.0, 106188.0, 106188.0"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("105959.6, 105959.6, 105959.6, 107816.9, 111531.6", \ + "105988.7, 105988.7, 105988.7, 107846.1, 111560.7", \ + "106126.4, 106126.4, 106126.4, 107983.7, 111698.4", \ + "106321.1, 106321.1, 106321.1, 108178.4, 111893.1", \ + "106707.3, 106707.3, 106707.3, 108564.6, 112279.3"); + } + } + internal_power (energy_pos_cout_cin1) { + related_pin : "cin1" ; + rise_power (energy_inslew_load_5x5__2) { + values ("81740.6, 81740.6, 81740.6, 83597.9, 87312.6", \ + "81780.3, 81780.3, 81780.3, 83637.6, 87352.3", \ + "81837.1, 81837.1, 81837.1, 83694.4, 87409.1", \ + "81901.2, 81901.2, 81901.2, 83758.5, 87473.2", \ + "82027.3, 82027.3, 82027.3, 83884.6, 87599.3"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("76035.7, 76035.7, 76035.7, 77893.0, 81607.7", \ + "76106.2, 76106.2, 76106.2, 77963.5, 81678.2", \ + "76187.8, 76187.8, 76187.8, 78045.1, 81759.8", \ + "76373.1, 76373.1, 76373.1, 78230.4, 81945.1", \ + "76640.0, 76640.0, 76640.0, 78497.3, 82212.0"); + } + } + } + } + + cell (nmx2_x4) { + area : 43.20 ; + cell_leakage_power : 8.9 ; + leakage_power () { + when : "(!(i1) & i0 & cmd)" ; + value : 9.8 ; + } + leakage_power () { + when : "(cmd & i1)" ; + value : 7.1 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & cmd)" ; + value : 9.1 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 7.6 ; + } + leakage_power () { + when : "(i1 & !(i0) & !(cmd))" ; + value : 10 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & !(cmd))" ; + value : 9.7 ; + } + pin (i1) { + direction : input ; + capacitance : 438.92 ; + } + pin (i0) { + direction : input ; + capacitance : 436.07 ; + } + pin (cmd) { + direction : input ; + capacitance : 864.42 ; + } + pin (nq) { + function : "((!(i0) & (!(i1) | !(cmd))) | (!(i1) & cmd))" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_nq_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("14300.1, 14300.1, 14300.1, 14564.6, 15054.8", \ + "14308.9, 14308.9, 14308.9, 14573.4, 15063.6", \ + "14326.5, 14326.5, 14326.5, 14591.0, 15081.2", \ + "14361.7, 14361.7, 14361.7, 14626.2, 15116.4", \ + "14425.2, 14425.2, 14425.2, 14689.7, 15179.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("3066.8, 3066.8, 3066.8, 3285.9, 3706.3", \ + "3066.8, 3066.8, 3066.8, 3285.9, 3706.3", \ + "3066.8, 3066.8, 3066.8, 3285.9, 3706.3", \ + "3066.8, 3066.8, 3066.8, 3285.9, 3706.3", \ + "3067.4, 3067.4, 3067.4, 3286.6, 3706.9"); + } + cell_fall (inslew_load_5x5__3) { + values ("14388.3, 14388.3, 14388.3, 14599.4, 15027.0", \ + "14397.1, 14397.1, 14397.1, 14608.2, 15035.8", \ + "14414.7, 14414.7, 14414.7, 14625.8, 15053.4", \ + "14449.8, 14449.8, 14449.8, 14660.9, 15088.5", \ + "14519.0, 14519.0, 14519.0, 14730.1, 15157.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("2990.8, 2990.8, 2990.8, 3152.4, 3475.3", \ + "2990.8, 2990.8, 2990.8, 3152.4, 3475.3", \ + "2990.8, 2990.8, 2990.8, 3152.4, 3475.3", \ + "2990.8, 2990.8, 2990.8, 3152.4, 3475.3", \ + "2990.8, 2990.8, 2990.8, 3152.5, 3475.3"); + } + } + timing (maxd_nq_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("12264.6, 12264.6, 12264.6, 12529.3, 13020.6", \ + "12270.9, 12270.9, 12270.9, 12535.5, 13026.7", \ + "12285.0, 12285.0, 12285.0, 12549.7, 13040.7", \ + "12299.6, 12299.6, 12299.6, 12564.2, 13055.0", \ + "12330.6, 12330.6, 12330.6, 12595.2, 13086.1"); + } + rise_transition (inslew_load_5x5__3) { + values ("3042.7, 3042.7, 3042.7, 3262.3, 3683.4", \ + "3045.2, 3045.2, 3045.2, 3264.8, 3685.8", \ + "3049.7, 3049.7, 3049.7, 3269.2, 3690.1", \ + "3052.0, 3052.0, 3052.0, 3271.4, 3692.2", \ + "3053.2, 3053.2, 3053.2, 3272.6, 3693.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("11229.4, 11229.4, 11229.4, 11440.5, 11871.8", \ + "11232.9, 11232.9, 11232.9, 11444.1, 11875.4", \ + "11240.5, 11240.5, 11240.5, 11451.6, 11882.9", \ + "11256.7, 11256.7, 11256.7, 11467.8, 11899.1", \ + "11289.6, 11289.6, 11289.6, 11500.8, 11932.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("2976.0, 2976.0, 2976.0, 3138.3, 3461.0", \ + "2976.2, 2976.2, 2976.2, 3138.4, 3461.1", \ + "2976.2, 2976.2, 2976.2, 3138.5, 3461.2", \ + "2976.2, 2976.2, 2976.2, 3138.5, 3461.2", \ + "2976.4, 2976.4, 2976.4, 3138.7, 3461.4"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("16849.9, 16849.9, 16849.9, 17105.2, 17589.8", \ + "16844.6, 16844.6, 16844.6, 17099.9, 17584.5", \ + "16833.8, 16833.8, 16833.8, 17089.1, 17573.7", \ + "16812.4, 16812.4, 16812.4, 17067.7, 17552.3", \ + "16769.4, 16769.4, 16769.4, 17024.7, 17509.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("4364.8, 4364.8, 4364.8, 4565.9, 4961.8", \ + "4364.8, 4364.8, 4364.8, 4565.9, 4961.8", \ + "4364.8, 4364.8, 4364.8, 4565.9, 4961.8", \ + "4364.8, 4364.8, 4364.8, 4565.9, 4961.8", \ + "4364.8, 4364.8, 4364.8, 4565.9, 4961.8"); + } + cell_fall (inslew_load_5x5__3) { + values ("13968.3, 13968.3, 13968.3, 14082.1, 14492.4", \ + "13963.2, 13963.2, 13963.2, 14077.0, 14487.3", \ + "13952.8, 13952.8, 13952.8, 14066.6, 14476.9", \ + "13932.2, 13932.2, 13932.2, 14046.0, 14456.3", \ + "13891.4, 13891.4, 13891.4, 14005.1, 14415.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("3556.1, 3556.1, 3556.1, 3589.3, 3901.4", \ + "3556.1, 3556.1, 3556.1, 3589.3, 3901.4", \ + "3556.1, 3556.1, 3556.1, 3589.3, 3901.4", \ + "3556.1, 3556.1, 3556.1, 3589.3, 3901.4", \ + "3556.1, 3556.1, 3556.1, 3589.5, 3901.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("16849.9, 16849.9, 16849.9, 17105.2, 17589.8", \ + "16844.6, 16844.6, 16844.6, 17099.9, 17584.5", \ + "16833.8, 16833.8, 16833.8, 17089.1, 17573.7", \ + "16812.4, 16812.4, 16812.4, 17067.7, 17552.3", \ + "16769.4, 16769.4, 16769.4, 17024.7, 17509.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("4364.8, 4364.8, 4364.8, 4565.9, 4961.8", \ + "4364.8, 4364.8, 4364.8, 4565.9, 4961.8", \ + "4364.8, 4364.8, 4364.8, 4565.9, 4961.8", \ + "4364.8, 4364.8, 4364.8, 4565.9, 4961.8", \ + "4364.8, 4364.8, 4364.8, 4565.9, 4961.8"); + } + cell_fall (inslew_load_5x5__3) { + values ("13968.3, 13968.3, 13968.3, 14082.1, 14492.4", \ + "13963.2, 13963.2, 13963.2, 14077.0, 14487.3", \ + "13952.8, 13952.8, 13952.8, 14066.6, 14476.9", \ + "13932.2, 13932.2, 13932.2, 14046.0, 14456.3", \ + "13891.4, 13891.4, 13891.4, 14005.1, 14415.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("3556.1, 3556.1, 3556.1, 3589.3, 3901.4", \ + "3556.1, 3556.1, 3556.1, 3589.3, 3901.4", \ + "3556.1, 3556.1, 3556.1, 3589.3, 3901.4", \ + "3556.1, 3556.1, 3556.1, 3589.3, 3901.4", \ + "3556.1, 3556.1, 3556.1, 3589.5, 3901.5"); + } + } + internal_power (energy_pos_nq_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__3) { + values ("61498.4, 61498.4, 61498.4, 63394.3, 67186.0", \ + "67208.8, 67208.8, 67208.8, 67208.8, 67208.8", \ + "67254.6, 67254.6, 67254.6, 67254.6, 67254.6", \ + "67347.0, 67347.0, 67347.0, 67347.0, 67347.0", \ + "61866.9, 61866.9, 61866.9, 63762.7, 67554.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("58012.9, 58012.9, 58012.9, 59908.8, 63700.4", \ + "63744.5, 63744.5, 63744.5, 63744.5, 63744.5", \ + "63832.7, 63832.7, 63832.7, 63832.7, 63832.7", \ + "64009.1, 64009.1, 64009.1, 64009.1, 64009.1", \ + "58676.7, 58676.7, 58676.7, 60572.5, 64364.2"); + } + } + internal_power (energy_neg_nq_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("54450.8, 54450.8, 54450.8, 56346.6, 60138.3", \ + "54508.1, 54508.1, 54508.1, 56403.9, 60195.6", \ + "54619.4, 54619.4, 54619.4, 56515.2, 60306.9", \ + "54798.6, 54798.6, 54798.6, 56694.4, 60486.1", \ + "55134.0, 55134.0, 55134.0, 57029.9, 60821.5"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("50853.5, 50853.5, 50853.5, 52749.3, 56541.0", \ + "50868.2, 50868.2, 50868.2, 52764.0, 56555.7", \ + "50892.8, 50892.8, 50892.8, 52788.6, 56580.3", \ + "56624.9, 56624.9, 56624.9, 56624.9, 56624.9", \ + "51031.1, 51031.1, 51031.1, 52926.9, 56718.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("71287.2, 71287.2, 71287.2, 73183.0, 76974.7", \ + "77018.8, 77018.8, 77018.8, 77018.8, 77018.8", \ + "77107.0, 77107.0, 77107.0, 77107.0, 77107.0", \ + "77283.3, 77283.3, 77283.3, 77283.3, 77283.3", \ + "77636.0, 77636.0, 77636.0, 77636.0, 77636.0"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("61190.0, 61190.0, 61190.0, 63085.8, 66877.5", \ + "66900.4, 66900.4, 66900.4, 66900.4, 66900.4", \ + "66946.2, 66946.2, 66946.2, 66946.2, 66946.2", \ + "67037.8, 67037.8, 67037.8, 67037.8, 67037.8", \ + "61535.0, 61535.0, 61535.0, 63430.8, 67222.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("71287.2, 71287.2, 71287.2, 73183.0, 76974.7", \ + "77018.8, 77018.8, 77018.8, 77018.8, 77018.8", \ + "77107.0, 77107.0, 77107.0, 77107.0, 77107.0", \ + "77283.3, 77283.3, 77283.3, 77283.3, 77283.3", \ + "77636.0, 77636.0, 77636.0, 77636.0, 77636.0"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("61190.0, 61190.0, 61190.0, 63085.8, 66877.5", \ + "66900.4, 66900.4, 66900.4, 66900.4, 66900.4", \ + "66946.2, 66946.2, 66946.2, 66946.2, 66946.2", \ + "67037.8, 67037.8, 67037.8, 67037.8, 67037.8", \ + "61535.0, 61535.0, 61535.0, 63430.8, 67222.5"); + } + } + } + } + + cell (o4_x4) { + area : 28.80 ; + cell_leakage_power : 7.6 ; + leakage_power () { + when : "(i0 & i1 & i2)" ; + value : 7.2 ; + } + leakage_power () { + when : "(i1 & !(i2) & !(i3))" ; + value : 7.3 ; + } + leakage_power () { + when : "((i0 & (!(i1) | (!(i2) & i3))) | (!(i0) & (i2 | i3)))" ; + value : 7 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 8.9 ; + } + pin (i3) { + direction : input ; + capacitance : 712.85 ; + } + pin (i2) { + direction : input ; + capacitance : 715.40 ; + } + pin (i1) { + direction : input ; + capacitance : 715.10 ; + } + pin (i0) { + direction : input ; + capacitance : 715.40 ; + } + pin (q) { + function : "(i3 | i2 | i0 | i1)" ; + direction : output ; + capacitance : 155.45 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("8364.6, 8364.6, 8364.6, 8632.4, 9129.7", \ + "8373.4, 8373.4, 8373.4, 8641.2, 9138.5", \ + "8391.0, 8391.0, 8391.0, 8658.8, 9156.1", \ + "8426.2, 8426.2, 8426.2, 8694.0, 9191.3", \ + "8496.6, 8496.6, 8496.6, 8764.4, 9261.7"); + } + rise_transition (inslew_load_5x5__4) { + values ("3352.2, 3352.2, 3352.2, 3571.6, 3992.6", \ + "3352.2, 3352.2, 3352.2, 3571.6, 3992.6", \ + "3352.2, 3352.2, 3352.2, 3571.6, 3992.6", \ + "3352.2, 3352.2, 3352.2, 3571.6, 3992.6", \ + "3352.3, 3352.3, 3352.3, 3571.6, 3992.7"); + } + cell_fall (inslew_load_5x5__4) { + values ("13307.0, 13307.0, 13307.0, 13530.4, 13981.3", \ + "13312.6, 13312.6, 13312.6, 13536.0, 13985.4", \ + "13315.7, 13315.7, 13315.7, 13539.1, 13986.2", \ + "13299.3, 13299.3, 13299.3, 13522.7, 13968.0", \ + "13280.4, 13280.4, 13280.4, 13503.8, 13945.8"); + } + fall_transition (inslew_load_5x5__4) { + values ("8065.5, 8065.5, 8065.5, 8240.2, 8570.8", \ + "8077.3, 8077.3, 8077.3, 8251.9, 8582.7", \ + "8093.8, 8093.8, 8093.8, 8268.6, 8599.5", \ + "8107.3, 8107.3, 8107.3, 8282.1, 8613.1", \ + "8131.5, 8131.5, 8131.5, 8306.4, 8637.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("6632.2, 6632.2, 6632.2, 6923.0, 7450.7", \ + "6641.0, 6641.0, 6641.0, 6931.8, 7459.5", \ + "6658.6, 6658.6, 6658.6, 6949.4, 7477.1", \ + "6693.8, 6693.8, 6693.8, 6984.6, 7512.3", \ + "6764.3, 6764.3, 6764.3, 7055.1, 7582.8"); + } + rise_transition (inslew_load_5x5__4) { + values ("2236.6, 2236.6, 2236.6, 2483.9, 2937.1", \ + "2236.6, 2236.6, 2236.6, 2483.9, 2937.1", \ + "2236.6, 2236.6, 2236.6, 2483.9, 2937.1", \ + "2236.6, 2236.6, 2236.6, 2483.9, 2937.1", \ + "2236.9, 2236.9, 2236.9, 2484.1, 2937.4"); + } + cell_fall (inslew_load_5x5__4) { + values ("9989.0, 9989.0, 9989.0, 10292.4, 10840.5", \ + "9959.2, 9959.2, 9959.2, 10262.0, 10808.7", \ + "9999.9, 9999.9, 9999.9, 10304.5, 10855.5", \ + "10008.5, 10008.5, 10008.5, 10314.3, 10868.2", \ + "10069.8, 10069.8, 10069.8, 10376.2, 10940.3"); + } + fall_transition (inslew_load_5x5__4) { + values ("5819.5, 5819.5, 5819.5, 5978.5, 6232.7", \ + "5804.1, 5804.1, 5804.1, 5962.5, 6216.4", \ + "5850.2, 5850.2, 5850.2, 6010.5, 6265.4", \ + "5881.5, 5881.5, 5881.5, 6043.0, 6298.6", \ + "5963.8, 5963.8, 5963.8, 6126.4, 6386.3"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("9351.2, 9351.2, 9351.2, 9614.5, 10110.0", \ + "9360.0, 9360.0, 9360.0, 9623.3, 10118.8", \ + "9377.6, 9377.6, 9377.6, 9640.9, 10136.4", \ + "9412.8, 9412.8, 9412.8, 9676.1, 10171.6", \ + "9483.2, 9483.2, 9483.2, 9746.5, 10242.0"); + } + rise_transition (inslew_load_5x5__4) { + values ("3962.3, 3962.3, 3962.3, 4173.3, 4582.5", \ + "3962.3, 3962.3, 3962.3, 4173.3, 4582.5", \ + "3962.3, 3962.3, 3962.3, 4173.3, 4582.5", \ + "3962.3, 3962.3, 3962.3, 4173.3, 4582.5", \ + "3962.3, 3962.3, 3962.3, 4173.3, 4582.5"); + } + cell_fall (inslew_load_5x5__4) { + values ("16784.5, 16784.5, 16784.5, 17004.8, 17443.1", \ + "16775.9, 16775.9, 16775.9, 16996.2, 17434.5", \ + "16755.6, 16755.6, 16755.6, 16975.9, 17414.2", \ + "16719.4, 16719.4, 16719.4, 16939.6, 17377.9", \ + "16645.3, 16645.3, 16645.3, 16865.6, 17303.9"); + } + fall_transition (inslew_load_5x5__4) { + values ("10321.1, 10321.1, 10321.1, 10496.2, 10828.6", \ + "10323.9, 10323.9, 10323.9, 10499.0, 10831.4", \ + "10326.0, 10326.0, 10326.0, 10501.1, 10833.5", \ + "10329.6, 10329.6, 10329.6, 10504.7, 10837.2", \ + "10330.3, 10330.3, 10330.3, 10505.3, 10837.8"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("10045.8, 10045.8, 10045.8, 10306.9, 10801.4", \ + "10054.6, 10054.6, 10054.6, 10315.7, 10810.2", \ + "10072.2, 10072.2, 10072.2, 10333.3, 10827.8", \ + "10107.4, 10107.4, 10107.4, 10368.5, 10863.0", \ + "10177.8, 10177.8, 10177.8, 10438.9, 10933.4"); + } + rise_transition (inslew_load_5x5__4) { + values ("4385.6, 4385.6, 4385.6, 4591.8, 4996.6", \ + "4385.6, 4385.6, 4385.6, 4591.8, 4996.6", \ + "4385.6, 4385.6, 4385.6, 4591.8, 4996.6", \ + "4385.6, 4385.6, 4385.6, 4591.8, 4996.6", \ + "4385.6, 4385.6, 4385.6, 4591.8, 4996.6"); + } + cell_fall (inslew_load_5x5__4) { + values ("20599.4, 20599.4, 20599.4, 20811.9, 21219.2", \ + "20584.6, 20584.6, 20584.6, 20797.1, 21204.4", \ + "20555.1, 20555.1, 20555.1, 20767.6, 21174.9", \ + "20495.9, 20495.9, 20495.9, 20708.4, 21115.7", \ + "20377.7, 20377.7, 20377.7, 20590.2, 20997.5"); + } + fall_transition (inslew_load_5x5__4) { + values ("12781.3, 12781.3, 12781.3, 12933.0, 13230.0", \ + "12781.3, 12781.3, 12781.3, 12933.0, 13230.0", \ + "12781.3, 12781.3, 12781.3, 12933.0, 13230.0", \ + "12781.3, 12781.3, 12781.3, 12933.0, 13230.0", \ + "12781.3, 12781.3, 12781.3, 12933.0, 13230.0"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__4) { + values ("53790.2, 53790.2, 53790.2, 55733.3, 59619.5", \ + "59645.9, 59645.9, 59645.9, 59645.9, 59645.9", \ + "59698.9, 59698.9, 59698.9, 59698.9, 59698.9", \ + "59804.8, 59804.8, 59804.8, 59804.8, 59804.8", \ + "54187.8, 54187.8, 54187.8, 56130.9, 60017.1"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("82820.5, 82820.5, 82820.5, 84763.6, 88649.8", \ + "82938.0, 82938.0, 82938.0, 84881.0, 88767.2", \ + "83129.9, 83129.9, 83129.9, 85072.9, 88959.1", \ + "83391.1, 83391.1, 83391.1, 85334.2, 89220.4", \ + "83896.5, 83896.5, 83896.5, 85839.6, 89725.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__4) { + values ("42395.8, 42395.8, 42395.8, 44338.9, 48225.1", \ + "48245.3, 48245.3, 48245.3, 48245.3, 48245.3", \ + "48285.9, 48285.9, 48285.9, 48285.9, 48285.9", \ + "48367.0, 48367.0, 48367.0, 48367.0, 48367.0", \ + "42701.0, 42701.0, 42701.0, 44644.0, 48530.2"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("59013.7, 59013.7, 59013.7, 60956.8, 64843.0", \ + "58963.3, 58963.3, 58963.3, 60906.4, 64792.6", \ + "59335.1, 59335.1, 59335.1, 61278.1, 65164.3", \ + "59703.5, 59703.5, 59703.5, 61646.6, 65532.8", \ + "60563.5, 60563.5, 60563.5, 62506.5, 66392.7"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__4) { + values ("60637.3, 60637.3, 60637.3, 62580.4, 66466.5", \ + "66502.8, 66502.8, 66502.8, 66502.8, 66502.8", \ + "66575.3, 66575.3, 66575.3, 66575.3, 66575.3", \ + "66720.2, 66720.2, 66720.2, 66720.2, 66720.2", \ + "67010.2, 67010.2, 67010.2, 67010.2, 67010.2"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("107451.8, 107451.8, 107451.8, 109394.9, 113281.1", \ + "107512.7, 107512.7, 107512.7, 109455.8, 113341.9", \ + "107613.5, 107613.5, 107613.5, 109556.6, 113442.7", \ + "107811.1, 107811.1, 107811.1, 109754.1, 113640.3", \ + "108164.7, 108164.7, 108164.7, 110107.8, 113993.9"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__4) { + values ("65583.4, 65583.4, 65583.4, 67526.5, 71412.7", \ + "71467.5, 71467.5, 71467.5, 71467.5, 71467.5", \ + "71577.1, 71577.1, 71577.1, 71577.1, 71577.1", \ + "71796.2, 71796.2, 71796.2, 71796.2, 71796.2", \ + "72234.6, 72234.6, 72234.6, 72234.6, 72234.6"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("131701.7, 131701.7, 131701.7, 133644.8, 137530.9", \ + "137570.8, 137570.8, 137570.8, 137570.8, 137570.8", \ + "137650.6, 137650.6, 137650.6, 137650.6, 137650.6", \ + "137810.2, 137810.2, 137810.2, 137810.2, 137810.2", \ + "138129.4, 138129.4, 138129.4, 138129.4, 138129.4"); + } + } + } + } + + cell (na4_x4) { + area : 36.00 ; + cell_leakage_power : 8 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 8 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & i0)" ; + value : 9.1 ; + } + leakage_power () { + when : "(i0 & (i1 ^ i2) & i3)" ; + value : 8.7 ; + } + leakage_power () { + when : "(i3 & i2 & i1 & !(i0))" ; + value : 8.8 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))) | (!(i0) & ((i1 & (i2 ^ i3)) | (!(i1) & i2 & i3))))" ; + value : 7.8 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))))" ; + value : 6.9 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 6.6 ; + } + pin (i3) { + direction : input ; + capacitance : 573.08 ; + } + pin (i2) { + direction : input ; + capacitance : 572.48 ; + } + pin (i1) { + direction : input ; + capacitance : 571.58 ; + } + pin (i0) { + direction : input ; + capacitance : 570.68 ; + } + pin (nq) { + function : "(!(i3) | !(i2) | !(i1) | !(i0))" ; + direction : output ; + capacitance : 148.31 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__5) { + values ("13944.8, 13944.8, 13944.8, 14202.0, 14680.3", \ + "13953.6, 13953.6, 13953.6, 14210.8, 14689.1", \ + "13971.2, 13971.2, 13971.2, 14228.4, 14706.7", \ + "14006.3, 14006.3, 14006.3, 14263.5, 14741.8", \ + "14076.6, 14076.6, 14076.6, 14333.8, 14812.1"); + } + rise_transition (inslew_load_5x5__5) { + values ("3295.5, 3295.5, 3295.5, 3506.7, 3910.7", \ + "3295.5, 3295.5, 3295.5, 3506.7, 3910.7", \ + "3295.5, 3295.5, 3295.5, 3506.7, 3910.7", \ + "3295.5, 3295.5, 3295.5, 3506.7, 3910.7", \ + "3295.5, 3295.5, 3295.5, 3506.7, 3910.7"); + } + cell_fall (inslew_load_5x5__5) { + values ("17385.1, 17385.1, 17385.1, 17599.8, 18004.7", \ + "17370.5, 17370.5, 17370.5, 17585.2, 17990.1", \ + "17341.5, 17341.5, 17341.5, 17556.2, 17961.1", \ + "17283.3, 17283.3, 17283.3, 17498.0, 17902.9", \ + "17167.0, 17167.0, 17167.0, 17381.7, 17786.6"); + } + fall_transition (inslew_load_5x5__5) { + values ("4463.0, 4463.0, 4463.0, 4568.2, 4814.0", \ + "4463.0, 4463.0, 4463.0, 4568.2, 4814.0", \ + "4463.0, 4463.0, 4463.0, 4568.2, 4814.0", \ + "4463.0, 4463.0, 4463.0, 4568.2, 4814.0", \ + "4463.0, 4463.0, 4463.0, 4568.2, 4814.0"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__5) { + values ("13032.4, 13032.4, 13032.4, 13291.5, 13771.7", \ + "13041.2, 13041.2, 13041.2, 13300.3, 13780.5", \ + "13058.8, 13058.8, 13058.8, 13317.9, 13798.1", \ + "13094.0, 13094.0, 13094.0, 13353.1, 13833.3", \ + "13164.3, 13164.3, 13164.3, 13423.4, 13903.6"); + } + rise_transition (inslew_load_5x5__5) { + values ("3059.2, 3059.2, 3059.2, 3273.8, 3685.4", \ + "3059.2, 3059.2, 3059.2, 3273.8, 3685.4", \ + "3059.2, 3059.2, 3059.2, 3273.8, 3685.4", \ + "3059.2, 3059.2, 3059.2, 3273.8, 3685.4", \ + "3059.2, 3059.2, 3059.2, 3273.8, 3685.4"); + } + cell_fall (inslew_load_5x5__5) { + values ("15466.2, 15466.2, 15466.2, 15678.3, 16079.0", \ + "15458.7, 15458.7, 15458.7, 15670.9, 16071.5", \ + "15440.9, 15440.9, 15440.9, 15653.1, 16053.7", \ + "15405.6, 15405.6, 15405.6, 15617.8, 16018.4", \ + "15335.5, 15335.5, 15335.5, 15547.7, 15948.3"); + } + fall_transition (inslew_load_5x5__5) { + values ("4034.1, 4034.1, 4034.1, 4148.6, 4413.4", \ + "4034.8, 4034.8, 4034.8, 4149.3, 4413.8", \ + "4035.1, 4035.1, 4035.1, 4149.6, 4414.2", \ + "4035.1, 4035.1, 4035.1, 4149.6, 4414.2", \ + "4035.2, 4035.2, 4035.2, 4149.7, 4414.4"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__5) { + values ("11881.8, 11881.8, 11881.8, 12143.5, 12638.8", \ + "11890.6, 11890.6, 11890.6, 12152.3, 12647.6", \ + "11908.2, 11908.2, 11908.2, 12169.9, 12665.2", \ + "11943.4, 11943.4, 11943.4, 12205.1, 12700.4", \ + "12013.9, 12013.9, 12013.9, 12275.5, 12770.9"); + } + rise_transition (inslew_load_5x5__5) { + values ("2758.6, 2758.6, 2758.6, 2978.6, 3399.6", \ + "2758.6, 2758.6, 2758.6, 2978.6, 3399.6", \ + "2758.6, 2758.6, 2758.6, 2978.6, 3399.6", \ + "2758.6, 2758.6, 2758.6, 2978.6, 3399.6", \ + "2758.7, 2758.7, 2758.7, 2978.7, 3399.7"); + } + cell_fall (inslew_load_5x5__5) { + values ("13378.2, 13378.2, 13378.2, 13487.8, 13889.7", \ + "13380.3, 13380.3, 13380.3, 13489.8, 13891.7", \ + "13385.0, 13385.0, 13385.0, 13494.5, 13896.4", \ + "13374.2, 13374.2, 13374.2, 13483.7, 13885.6", \ + "13347.6, 13347.6, 13347.6, 13457.1, 13859.0"); + } + fall_transition (inslew_load_5x5__5) { + values ("3576.5, 3576.5, 3576.5, 3605.3, 3909.2", \ + "3579.3, 3579.3, 3579.3, 3607.7, 3911.6", \ + "3583.5, 3583.5, 3583.5, 3611.8, 3915.5", \ + "3585.6, 3585.6, 3585.6, 3613.7, 3917.4", \ + "3586.0, 3586.0, 3586.0, 3614.2, 3917.8"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__5) { + values ("10324.8, 10324.8, 10324.8, 10602.8, 11110.0", \ + "10333.6, 10333.6, 10333.6, 10611.6, 11118.8", \ + "10351.2, 10351.2, 10351.2, 10629.2, 11136.4", \ + "10386.4, 10386.4, 10386.4, 10664.4, 11171.6", \ + "10457.0, 10457.0, 10457.0, 10735.0, 11242.2"); + } + rise_transition (inslew_load_5x5__5) { + values ("2349.8, 2349.8, 2349.8, 2585.8, 3018.4", \ + "2349.8, 2349.8, 2349.8, 2585.8, 3018.4", \ + "2349.8, 2349.8, 2349.8, 2585.8, 3018.4", \ + "2349.8, 2349.8, 2349.8, 2585.8, 3018.4", \ + "2350.3, 2350.3, 2350.3, 2586.3, 3018.8"); + } + cell_fall (inslew_load_5x5__5) { + values ("11007.7, 11007.7, 11007.7, 11214.3, 11629.6", \ + "11018.8, 11018.8, 11018.8, 11225.4, 11640.4", \ + "11061.8, 11061.8, 11061.8, 11268.4, 11682.4", \ + "11102.7, 11102.7, 11102.7, 11309.3, 11721.2", \ + "11125.4, 11125.4, 11125.4, 11332.0, 11742.4"); + } + fall_transition (inslew_load_5x5__5) { + values ("2986.5, 2986.5, 2986.5, 3144.2, 3461.8", \ + "2987.8, 2987.8, 2987.8, 3145.5, 3463.1", \ + "2991.8, 2991.8, 2991.8, 3149.3, 3466.9", \ + "2999.5, 2999.5, 2999.5, 3156.6, 3474.3", \ + "3005.5, 3005.5, 3005.5, 3162.3, 3480.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__5) { + values ("65427.3, 65427.3, 65427.3, 67281.1, 70988.8", \ + "71067.6, 71067.6, 71067.6, 71067.6, 71067.6", \ + "71225.2, 71225.2, 71225.2, 71225.2, 71225.2", \ + "71540.4, 71540.4, 71540.4, 71540.4, 71540.4", \ + "72170.9, 72170.9, 72170.9, 72170.9, 72170.9"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("80489.1, 80489.1, 80489.1, 82342.9, 86050.6", \ + "86067.2, 86067.2, 86067.2, 86067.2, 86067.2", \ + "86100.4, 86100.4, 86100.4, 86100.4, 86100.4", \ + "86166.7, 86166.7, 86166.7, 86166.7, 86166.7", \ + "86299.6, 86299.6, 86299.6, 86299.6, 86299.6"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__5) { + values ("61510.6, 61510.6, 61510.6, 63364.4, 67072.1", \ + "67133.6, 67133.6, 67133.6, 67133.6, 67133.6", \ + "67256.6, 67256.6, 67256.6, 67256.6, 67256.6", \ + "67502.6, 67502.6, 67502.6, 67502.6, 67502.6", \ + "67994.7, 67994.7, 67994.7, 67994.7, 67994.7"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("71045.5, 71045.5, 71045.5, 72899.4, 76607.1", \ + "71072.0, 71072.0, 71072.0, 72925.9, 76633.6", \ + "71114.0, 71114.0, 71114.0, 72967.8, 76675.5", \ + "76753.8, 76753.8, 76753.8, 76753.8, 76753.8", \ + "71349.8, 71349.8, 71349.8, 73203.6, 76911.3"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__5) { + values ("56770.3, 56770.3, 56770.3, 58624.1, 62331.8", \ + "62381.4, 62381.4, 62381.4, 62381.4, 62381.4", \ + "62480.5, 62480.5, 62480.5, 62480.5, 62480.5", \ + "62678.7, 62678.7, 62678.7, 62678.7, 62678.7", \ + "57514.5, 57514.5, 57514.5, 59368.4, 63076.0"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("61428.6, 61428.6, 61428.6, 63282.5, 66990.1", \ + "61475.1, 61475.1, 61475.1, 63328.9, 67036.6", \ + "61560.8, 61560.8, 61560.8, 63414.6, 67122.3", \ + "61667.8, 61667.8, 61667.8, 63521.6, 67229.3", \ + "61847.2, 61847.2, 61847.2, 63701.1, 67408.7"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__5) { + values ("50768.5, 50768.5, 50768.5, 52622.4, 56330.0", \ + "56371.1, 56371.1, 56371.1, 56371.1, 56371.1", \ + "56453.2, 56453.2, 56453.2, 56453.2, 56453.2", \ + "56617.4, 56617.4, 56617.4, 56617.4, 56617.4", \ + "51387.2, 51387.2, 51387.2, 53241.1, 56948.7"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("51964.1, 51964.1, 51964.1, 53818.0, 57525.7", \ + "52021.2, 52021.2, 52021.2, 53875.0, 57582.7", \ + "52164.4, 52164.4, 52164.4, 54018.3, 57725.9", \ + "52360.7, 52360.7, 52360.7, 54214.6, 57922.2", \ + "52604.2, 52604.2, 52604.2, 54458.1, 58165.8"); + } + } + } + } + + cell (nxr2_x1) { + area : 32.40 ; + cell_leakage_power : 7.9 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 7.2 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 7.9 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 8.9 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 7.5 ; + } + pin (i1) { + direction : input ; + capacitance : 1275.14 ; + } + pin (i0) { + direction : input ; + capacitance : 1270.30 ; + } + pin (nq) { + function : "!((i1 ^ i0))" ; + direction : output ; + capacitance : 152.23 ; + timing (maxd_nq_i0_positive_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("4645.5, 4645.5, 4645.5, 5313.9, 6430.3", \ + "4654.3, 4654.3, 4654.3, 5322.7, 6439.1", \ + "4671.9, 4671.9, 4671.9, 5340.3, 6456.7", \ + "4707.0, 4707.0, 4707.0, 5375.5, 6491.9", \ + "4773.1, 4773.1, 4773.1, 5442.6, 6560.2"); + } + rise_transition (inslew_load_5x5__6) { + values ("1618.2, 1618.2, 1618.2, 2431.1, 3919.3", \ + "1618.2, 1618.2, 1618.2, 2431.1, 3919.3", \ + "1618.2, 1618.2, 1618.2, 2431.1, 3919.3", \ + "1618.2, 1618.2, 1618.2, 2431.1, 3919.3", \ + "1618.6, 1618.6, 1618.6, 2432.2, 3920.8"); + } + cell_fall (inslew_load_5x5__6) { + values ("5285.3, 5285.3, 5285.3, 5915.1, 6851.6", \ + "5294.1, 5294.1, 5294.1, 5923.9, 6860.4", \ + "5311.7, 5311.7, 5311.7, 5941.5, 6878.0", \ + "5346.9, 5346.9, 5346.9, 5976.7, 6913.2", \ + "5417.1, 5417.1, 5417.1, 6047.0, 6983.5"); + } + fall_transition (inslew_load_5x5__6) { + values ("1807.7, 1807.7, 1807.7, 2374.2, 3290.4", \ + "1807.7, 1807.7, 1807.7, 2374.2, 3290.4", \ + "1807.7, 1807.7, 1807.7, 2374.2, 3290.4", \ + "1807.7, 1807.7, 1807.7, 2374.2, 3290.4", \ + "1807.9, 1807.9, 1807.9, 2374.5, 3290.7"); + } + } + timing (maxd_nq_i1_positive_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("7885.0, 7885.0, 7885.0, 8343.5, 9260.7", \ + "7893.8, 7893.8, 7893.8, 8352.3, 9269.5", \ + "7911.4, 7911.4, 7911.4, 8369.9, 9287.1", \ + "7946.6, 7946.6, 7946.6, 8405.0, 9322.3", \ + "8014.5, 8014.5, 8014.5, 8473.1, 9390.5"); + } + rise_transition (inslew_load_5x5__6) { + values ("6448.6, 6448.6, 6448.6, 7164.0, 8586.3", \ + "6448.6, 6448.6, 6448.6, 7164.0, 8586.3", \ + "6448.6, 6448.6, 6448.6, 7164.0, 8586.3", \ + "6448.6, 6448.6, 6448.6, 7164.0, 8586.3", \ + "6449.6, 6449.6, 6449.6, 7165.0, 8587.1"); + } + cell_fall (inslew_load_5x5__6) { + values ("7775.8, 7775.8, 7775.8, 8128.9, 8812.0", \ + "7784.5, 7784.5, 7784.5, 8137.6, 8820.7", \ + "7802.1, 7802.1, 7802.1, 8155.2, 8838.3", \ + "7837.3, 7837.3, 7837.3, 8190.4, 8873.5", \ + "7907.7, 7907.7, 7907.7, 8260.8, 8944.0"); + } + fall_transition (inslew_load_5x5__6) { + values ("4264.8, 4264.8, 4264.8, 4690.1, 5530.6", \ + "4264.8, 4264.8, 4264.8, 4690.1, 5530.6", \ + "4264.8, 4264.8, 4264.8, 4690.1, 5530.6", \ + "4264.8, 4264.8, 4264.8, 4690.1, 5530.6", \ + "4265.2, 4265.2, 4265.2, 4690.5, 5531.0"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__6) { + values ("6167.4, 6167.4, 6167.4, 6606.7, 7505.1", \ + "6161.9, 6161.9, 6161.9, 6601.2, 7499.7", \ + "6151.0, 6151.0, 6151.0, 6590.4, 7489.0", \ + "6129.2, 6129.2, 6129.2, 6568.8, 7467.4", \ + "6085.7, 6085.7, 6085.7, 6525.5, 7424.4"); + } + rise_transition (inslew_load_5x5__6) { + values ("7505.5, 7505.5, 7505.5, 8231.1, 9682.3", \ + "7505.5, 7505.5, 7505.5, 8231.1, 9682.3", \ + "7505.5, 7505.5, 7505.5, 8231.1, 9682.3", \ + "7505.5, 7505.5, 7505.5, 8231.1, 9682.3", \ + "7505.6, 7505.6, 7505.6, 8231.2, 9682.3"); + } + cell_fall (inslew_load_5x5__6) { + values ("3782.5, 3782.5, 3782.5, 4047.1, 4585.0", \ + "3777.3, 3777.3, 3777.3, 4041.9, 4579.9", \ + "3766.9, 3766.9, 3766.9, 4031.6, 4569.5", \ + "3746.2, 3746.2, 3746.2, 4010.9, 4548.9", \ + "3704.6, 3704.6, 3704.6, 3969.4, 4507.6"); + } + fall_transition (inslew_load_5x5__6) { + values ("4313.4, 4313.4, 4313.4, 4740.2, 5594.0", \ + "4313.4, 4313.4, 4313.4, 4740.2, 5594.0", \ + "4313.4, 4313.4, 4313.4, 4740.2, 5594.0", \ + "4313.4, 4313.4, 4313.4, 4740.2, 5594.0", \ + "4315.6, 4315.6, 4315.6, 4741.8, 5594.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__6) { + values ("2960.7, 2960.7, 2960.7, 3421.0, 4342.4", \ + "2970.8, 2970.8, 2970.8, 3431.2, 4352.9", \ + "2979.0, 2979.0, 2979.0, 3439.0, 4360.2", \ + "2995.8, 2995.8, 2995.8, 3456.6, 4379.0", \ + "3015.9, 3015.9, 3015.9, 3478.5, 4402.6"); + } + rise_transition (inslew_load_5x5__6) { + values ("2593.5, 2593.5, 2593.5, 3327.5, 4799.0", \ + "2614.7, 2614.7, 2614.7, 3348.9, 4820.8", \ + "2634.4, 2634.4, 2634.4, 3368.1, 4839.3", \ + "2664.5, 2664.5, 2664.5, 3399.3, 4872.4", \ + "2682.1, 2682.1, 2682.1, 3416.6, 4890.0"); + } + cell_fall (inslew_load_5x5__6) { + values ("2396.3, 2396.3, 2396.3, 2669.5, 3216.8", \ + "2391.1, 2391.1, 2391.1, 2664.3, 3211.6", \ + "2380.8, 2380.8, 2380.8, 2654.0, 3201.3", \ + "2360.1, 2360.1, 2360.1, 2633.4, 3180.7", \ + "2314.1, 2314.1, 2314.1, 2589.5, 3138.7"); + } + fall_transition (inslew_load_5x5__6) { + values ("2215.2, 2215.2, 2215.2, 2642.1, 3495.8", \ + "2215.2, 2215.2, 2215.2, 2642.1, 3495.8", \ + "2215.2, 2215.2, 2215.2, 2642.1, 3495.8", \ + "2215.4, 2215.4, 2215.4, 2642.2, 3495.8", \ + "2227.5, 2227.5, 2227.5, 2651.2, 3500.5"); + } + } + internal_power (energy_pos_nq_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__6) { + values ("15882.0, 15882.0, 15882.0, 17784.8, 21590.5", \ + "21613.4, 21613.4, 21613.4, 21613.4, 21613.4", \ + "21659.2, 21659.2, 21659.2, 21659.2, 21659.2", \ + "16042.4, 16042.4, 16042.4, 17945.2, 21750.9", \ + "16236.5, 16236.5, 16236.5, 18139.4, 21945.0"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("16805.8, 16805.8, 16805.8, 18708.6, 22514.3", \ + "22558.4, 22558.4, 22558.4, 22558.4, 22558.4", \ + "22646.5, 22646.5, 22646.5, 22646.5, 22646.5", \ + "22822.9, 22822.9, 22822.9, 22822.9, 22822.9", \ + "17467.5, 17467.5, 17467.5, 19370.4, 23176.1"); + } + } + internal_power (energy_pos_nq_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__6) { + values ("28687.5, 28687.5, 28687.5, 30590.4, 34396.1", \ + "34419.0, 34419.0, 34419.0, 34419.0, 34419.0", \ + "34464.7, 34464.7, 34464.7, 34464.7, 34464.7", \ + "28848.0, 28848.0, 28848.0, 30750.8, 34556.5", \ + "29041.9, 29041.9, 29041.9, 30944.7, 34750.4"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("27994.1, 27994.1, 27994.1, 29897.0, 33702.6", \ + "33746.7, 33746.7, 33746.7, 33746.7, 33746.7", \ + "33834.9, 33834.9, 33834.9, 33834.9, 33834.9", \ + "34011.3, 34011.3, 34011.3, 34011.3, 34011.3", \ + "28656.2, 28656.2, 28656.2, 30559.0, 34364.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__6) { + values ("17879.3, 17879.3, 17879.3, 19782.1, 23587.8", \ + "17967.7, 17967.7, 17967.7, 19870.5, 23676.2", \ + "18144.5, 18144.5, 18144.5, 20047.3, 23853.0", \ + "18498.1, 18498.1, 18498.1, 20400.9, 24206.6", \ + "19205.2, 19205.2, 19205.2, 21108.1, 24913.7"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("17012.8, 17012.8, 17012.8, 18915.7, 22721.3", \ + "17058.5, 17058.5, 17058.5, 18961.4, 22767.0", \ + "17150.0, 17150.0, 17150.0, 19052.8, 22858.5", \ + "17332.8, 17332.8, 17332.8, 19235.6, 23041.3", \ + "17698.5, 17698.5, 17698.5, 19601.3, 23407.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__6) { + values ("5107.2, 5107.2, 5107.2, 7010.0, 10815.7", \ + "5192.5, 5192.5, 5192.5, 7095.3, 10901.0", \ + "5363.1, 5363.1, 5363.1, 7266.0, 11071.6", \ + "5704.4, 5704.4, 5704.4, 7607.2, 11412.9", \ + "6386.8, 6386.8, 6386.8, 8289.7, 12095.3"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("7642.9, 7642.9, 7642.9, 9545.7, 13351.4", \ + "7671.7, 7671.7, 7671.7, 9574.5, 13380.2", \ + "7729.2, 7729.2, 7729.2, 9632.0, 13437.7", \ + "7844.2, 7844.2, 7844.2, 9747.0, 13552.7", \ + "8074.2, 8074.2, 8074.2, 9977.0, 13782.7"); + } + } + } + } + + cell (no4_x4) { + area : 36.00 ; + cell_leakage_power : 8.2 ; + leakage_power () { + when : "((i0 & i1 & (i2 | !(i3))) | (i1 & !(i2) & !(i3)))" ; + value : 6.4 ; + } + leakage_power () { + when : "((i0 & (!(i1) | (!(i2) & i3))) | (!(i0) & (i2 | i3)))" ; + value : 6.1 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 12 ; + } + pin (i3) { + direction : input ; + capacitance : 714.80 ; + } + pin (i2) { + direction : input ; + capacitance : 715.70 ; + } + pin (i1) { + direction : input ; + capacitance : 715.10 ; + } + pin (i0) { + direction : input ; + capacitance : 715.40 ; + } + pin (nq) { + function : "(!(i3) & !(i2) & !(i0) & !(i1))" ; + direction : output ; + capacitance : 148.87 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__7) { + values ("17425.8, 17425.8, 17425.8, 17665.2, 18139.7", \ + "17438.3, 17438.3, 17438.3, 17677.4, 18151.9", \ + "17450.9, 17450.9, 17450.9, 17689.5, 18163.9", \ + "17442.6, 17442.6, 17442.6, 17680.9, 18155.3", \ + "17435.0, 17435.0, 17435.0, 17672.7, 18147.0"); + } + rise_transition (inslew_load_5x5__7) { + values ("4848.3, 4848.3, 4848.3, 5044.3, 5428.4", \ + "4856.1, 4856.1, 4856.1, 5052.2, 5436.2", \ + "4867.2, 4867.2, 4867.2, 5063.2, 5447.2", \ + "4876.2, 4876.2, 4876.2, 5072.3, 5456.2", \ + "4891.5, 4891.5, 4891.5, 5087.7, 5471.4"); + } + cell_fall (inslew_load_5x5__7) { + values ("11968.2, 11968.2, 11968.2, 12175.5, 12594.7", \ + "11977.0, 11977.0, 11977.0, 12184.3, 12603.5", \ + "11994.6, 11994.6, 11994.6, 12201.9, 12621.1", \ + "12029.9, 12029.9, 12029.9, 12237.2, 12656.4", \ + "12100.2, 12100.2, 12100.2, 12307.6, 12726.8"); + } + fall_transition (inslew_load_5x5__7) { + values ("2979.9, 2979.9, 2979.9, 3138.5, 3457.0", \ + "2979.9, 2979.9, 2979.9, 3138.5, 3457.0", \ + "2979.9, 2979.9, 2979.9, 3138.5, 3457.0", \ + "2979.9, 2979.9, 2979.9, 3138.5, 3457.0", \ + "2980.0, 2980.0, 2980.0, 3138.6, 3457.0"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__7) { + values ("11996.2, 11996.2, 11996.2, 12256.1, 12737.4", \ + "11952.3, 11952.3, 11952.3, 12212.3, 12694.2", \ + "12065.3, 12065.3, 12065.3, 12325.0, 12805.9", \ + "12131.0, 12131.0, 12131.0, 12390.4, 12871.2", \ + "12303.0, 12303.0, 12303.0, 12562.0, 13042.2"); + } + rise_transition (inslew_load_5x5__7) { + values ("3070.4, 3070.4, 3070.4, 3285.6, 3698.4", \ + "3059.1, 3059.1, 3059.1, 3274.5, 3687.6", \ + "3103.1, 3103.1, 3103.1, 3317.9, 3729.4", \ + "3135.6, 3135.6, 3135.6, 3350.0, 3760.4", \ + "3208.3, 3208.3, 3208.3, 3421.8, 3829.6"); + } + cell_fall (inslew_load_5x5__7) { + values ("10577.3, 10577.3, 10577.3, 10784.8, 11216.6", \ + "10586.1, 10586.1, 10586.1, 10793.6, 11225.4", \ + "10603.7, 10603.7, 10603.7, 10811.2, 11243.0", \ + "10638.9, 10638.9, 10638.9, 10846.4, 11278.2", \ + "10708.3, 10708.3, 10708.3, 10915.8, 11347.6"); + } + fall_transition (inslew_load_5x5__7) { + values ("2930.2, 2930.2, 2930.2, 3091.1, 3409.0", \ + "2930.2, 2930.2, 2930.2, 3091.1, 3409.0", \ + "2930.2, 2930.2, 2930.2, 3091.1, 3409.0", \ + "2930.2, 2930.2, 2930.2, 3091.1, 3409.0", \ + "2930.2, 2930.2, 2930.2, 3091.1, 3409.1"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__7) { + values ("22210.8, 22210.8, 22210.8, 22447.4, 22898.2", \ + "22203.2, 22203.2, 22203.2, 22439.7, 22890.6", \ + "22183.6, 22183.6, 22183.6, 22420.2, 22871.1", \ + "22148.6, 22148.6, 22148.6, 22385.1, 22836.0", \ + "22074.4, 22074.4, 22074.4, 22310.9, 22761.8"); + } + rise_transition (inslew_load_5x5__7) { + values ("6368.1, 6368.1, 6368.1, 6558.4, 6933.5", \ + "6369.8, 6369.8, 6369.8, 6560.1, 6935.2", \ + "6371.1, 6371.1, 6371.1, 6561.4, 6936.5", \ + "6373.3, 6373.3, 6373.3, 6563.6, 6938.6", \ + "6373.7, 6373.7, 6373.7, 6563.9, 6939.0"); + } + cell_fall (inslew_load_5x5__7) { + values ("12988.0, 12988.0, 12988.0, 13195.3, 13600.6", \ + "12996.8, 12996.8, 12996.8, 13204.1, 13609.4", \ + "13014.4, 13014.4, 13014.4, 13221.7, 13627.0", \ + "13049.5, 13049.5, 13049.5, 13256.8, 13662.1", \ + "13120.3, 13120.3, 13120.3, 13327.6, 13732.8"); + } + fall_transition (inslew_load_5x5__7) { + values ("3127.1, 3127.1, 3127.1, 3279.5, 3597.0", \ + "3127.1, 3127.1, 3127.1, 3279.5, 3597.0", \ + "3127.1, 3127.1, 3127.1, 3279.5, 3597.0", \ + "3127.1, 3127.1, 3127.1, 3279.5, 3597.0", \ + "3127.3, 3127.3, 3127.3, 3279.7, 3597.2"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__7) { + values ("26569.4, 26569.4, 26569.4, 26805.6, 27261.6", \ + "26554.6, 26554.6, 26554.6, 26790.8, 27246.8", \ + "26524.9, 26524.9, 26524.9, 26761.1, 27217.1", \ + "26465.5, 26465.5, 26465.5, 26701.7, 27157.7", \ + "26346.8, 26346.8, 26346.8, 26583.0, 27039.0"); + } + rise_transition (inslew_load_5x5__7) { + values ("7745.0, 7745.0, 7745.0, 7935.1, 8307.5", \ + "7745.0, 7745.0, 7745.0, 7935.1, 8307.5", \ + "7745.0, 7745.0, 7745.0, 7935.1, 8307.5", \ + "7745.0, 7745.0, 7745.0, 7935.1, 8307.5", \ + "7745.0, 7745.0, 7745.0, 7935.1, 8307.5"); + } + cell_fall (inslew_load_5x5__7) { + values ("13802.9, 13802.9, 13802.9, 14010.3, 14414.9", \ + "13811.7, 13811.7, 13811.7, 14019.1, 14423.7", \ + "13829.3, 13829.3, 13829.3, 14036.7, 14441.3", \ + "13864.5, 13864.5, 13864.5, 14071.9, 14476.5", \ + "13935.1, 13935.1, 13935.1, 14142.4, 14547.1"); + } + fall_transition (inslew_load_5x5__7) { + values ("3275.3, 3275.3, 3275.3, 3422.1, 3734.0", \ + "3275.3, 3275.3, 3275.3, 3422.1, 3734.0", \ + "3275.3, 3275.3, 3275.3, 3422.1, 3734.0", \ + "3275.3, 3275.3, 3275.3, 3422.1, 3734.0", \ + "3275.4, 3275.4, 3275.4, 3422.2, 3734.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__7) { + values ("77953.8, 77953.8, 77953.8, 79814.6, 83536.3", \ + "78059.7, 78059.7, 78059.7, 79920.6, 83642.3", \ + "78235.2, 78235.2, 78235.2, 80096.1, 83817.8", \ + "78484.1, 78484.1, 78484.1, 80344.9, 84066.6", \ + "78958.7, 78958.7, 78958.7, 80819.6, 84541.2"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("57532.6, 57532.6, 57532.6, 59393.4, 63115.1", \ + "63141.6, 63141.6, 63141.6, 63141.6, 63141.6", \ + "63194.6, 63194.6, 63194.6, 63194.6, 63194.6", \ + "63300.6, 63300.6, 63300.6, 63300.6, 63300.6", \ + "57931.9, 57931.9, 57931.9, 59792.7, 63514.4"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__7) { + values ("55121.9, 55121.9, 55121.9, 56982.7, 60704.4", \ + "55091.1, 55091.1, 55091.1, 56952.0, 60673.6", \ + "55471.6, 55471.6, 55471.6, 57332.4, 61054.1", \ + "55865.3, 55865.3, 55865.3, 57726.1, 61447.8", \ + "56706.8, 56706.8, 56706.8, 58567.6, 62289.3"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("49809.8, 49809.8, 49809.8, 51670.6, 55392.3", \ + "55412.6, 55412.6, 55412.6, 55412.6, 55412.6", \ + "55453.1, 55453.1, 55453.1, 55453.1, 55453.1", \ + "55534.3, 55534.3, 55534.3, 55534.3, 55534.3", \ + "50120.8, 50120.8, 50120.8, 51981.7, 55703.4"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__7) { + values ("100872.4, 100872.4, 100872.4, 102733.2, 106454.9", \ + "100930.2, 100930.2, 100930.2, 102791.0, 106512.7", \ + "101028.6, 101028.6, 101028.6, 102889.5, 106611.2", \ + "101221.7, 101221.7, 101221.7, 103082.5, 106804.2", \ + "101574.4, 101574.4, 101574.4, 103435.3, 107156.9"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("62842.1, 62842.1, 62842.1, 64703.0, 68424.6", \ + "68460.9, 68460.9, 68460.9, 68460.9, 68460.9", \ + "68533.4, 68533.4, 68533.4, 68533.4, 68533.4", \ + "68678.3, 68678.3, 68678.3, 68678.3, 68678.3", \ + "63387.5, 63387.5, 63387.5, 65248.3, 68970.0"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__7) { + values ("123218.5, 123218.5, 123218.5, 125079.4, 128801.1", \ + "128841.0, 128841.0, 128841.0, 128841.0, 128841.0", \ + "128920.7, 128920.7, 128920.7, 128920.7, 128920.7", \ + "129080.3, 129080.3, 129080.3, 129080.3, 129080.3", \ + "129399.5, 129399.5, 129399.5, 129399.5, 129399.5"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("66920.8, 66920.8, 66920.8, 68781.6, 72503.3", \ + "72558.1, 72558.1, 72558.1, 72558.1, 72558.1", \ + "72667.7, 72667.7, 72667.7, 72667.7, 72667.7", \ + "72886.8, 72886.8, 72886.8, 72886.8, 72886.8", \ + "67743.5, 67743.5, 67743.5, 69604.4, 73326.0"); + } + } + } + } + + cell (no3_x1) { + area : 18.00 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "((i0 & i1) | (i1 & !(i2)))" ; + value : 1.7 ; + } + leakage_power () { + when : "((i0 & !(i1)) | (!(i0) & i2))" ; + value : 1.4 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 4.2 ; + } + pin (i2) { + direction : input ; + capacitance : 718.25 ; + } + pin (i1) { + direction : input ; + capacitance : 715.10 ; + } + pin (i0) { + direction : input ; + capacitance : 715.40 ; + } + pin (nq) { + function : "((!(i1) & !(i0)) & !(i2))" ; + direction : output ; + capacitance : 104.07 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__8) { + values ("5702.3, 5702.3, 5702.3, 6106.3, 6929.5", \ + "5696.3, 5696.3, 5696.3, 6100.3, 6923.6", \ + "5687.6, 5687.6, 5687.6, 6091.9, 6915.5", \ + "5667.7, 5667.7, 5667.7, 6072.4, 6896.5", \ + "5630.1, 5630.1, 5630.1, 6035.0, 6859.4"); + } + rise_transition (inslew_load_5x5__8) { + values ("7574.3, 7574.3, 7574.3, 8306.3, 9770.7", \ + "7579.4, 7579.4, 7579.4, 8311.4, 9775.8", \ + "7590.9, 7590.9, 7590.9, 8323.3, 9788.2", \ + "7598.5, 7598.5, 7598.5, 8331.2, 9796.8", \ + "7599.9, 7599.9, 7599.9, 8332.5, 9798.0"); + } + cell_fall (inslew_load_5x5__8) { + values ("2841.4, 2841.4, 2841.4, 3074.7, 3543.1", \ + "2850.2, 2850.2, 2850.2, 3083.5, 3551.9", \ + "2867.7, 2867.7, 2867.7, 3101.1, 3569.5", \ + "2902.9, 2902.9, 2902.9, 3136.2, 3604.7", \ + "2971.6, 2971.6, 2971.6, 3205.7, 3674.7"); + } + fall_transition (inslew_load_5x5__8) { + values ("2151.8, 2151.8, 2151.8, 2468.4, 3101.7", \ + "2151.8, 2151.8, 2151.8, 2468.4, 3101.7", \ + "2151.8, 2151.8, 2151.8, 2468.4, 3101.7", \ + "2151.8, 2151.8, 2151.8, 2468.4, 3101.7", \ + "2157.6, 2157.6, 2157.6, 2472.8, 3104.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__8) { + values ("2086.8, 2086.8, 2086.8, 2514.3, 3360.5", \ + "2111.0, 2111.0, 2111.0, 2538.2, 3383.6", \ + "2126.4, 2126.4, 2126.4, 2552.4, 3395.0", \ + "2163.4, 2163.4, 2163.4, 2588.8, 3431.2", \ + "2174.7, 2174.7, 2174.7, 2605.8, 3454.1"); + } + rise_transition (inslew_load_5x5__8) { + values ("1440.6, 1440.6, 1440.6, 2183.6, 3664.6", \ + "1496.4, 1496.4, 1496.4, 2238.8, 3718.4", \ + "1545.6, 1545.6, 1545.6, 2285.9, 3760.5", \ + "1641.4, 1641.4, 1641.4, 2380.4, 3854.7", \ + "1705.7, 1705.7, 1705.7, 2443.9, 3920.0"); + } + cell_fall (inslew_load_5x5__8) { + values ("1698.7, 1698.7, 1698.7, 1938.7, 2415.0", \ + "1707.5, 1707.5, 1707.5, 1947.5, 2423.8", \ + "1725.1, 1725.1, 1725.1, 1965.1, 2441.4", \ + "1759.9, 1759.9, 1759.9, 2000.2, 2476.5", \ + "1808.8, 1808.8, 1808.8, 2058.3, 2542.8"); + } + fall_transition (inslew_load_5x5__8) { + values ("662.0, 662.0, 662.0, 978.6, 1611.9", \ + "662.0, 662.0, 662.0, 978.6, 1611.9", \ + "662.0, 662.0, 662.0, 978.6, 1611.9", \ + "662.4, 662.4, 662.4, 978.9, 1612.0", \ + "672.9, 672.9, 672.9, 991.5, 1621.4"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__8) { + values ("9408.7, 9408.7, 9408.7, 9787.1, 10581.5", \ + "9397.1, 9397.1, 9397.1, 9775.6, 10570.1", \ + "9374.1, 9374.1, 9374.1, 9752.7, 10547.3", \ + "9327.9, 9327.9, 9327.9, 9706.8, 10501.8", \ + "9235.5, 9235.5, 9235.5, 9615.1, 10410.6"); + } + rise_transition (inslew_load_5x5__8) { + values ("13739.1, 13739.1, 13739.1, 14461.2, 15905.2", \ + "13739.1, 13739.1, 13739.1, 14461.2, 15905.2", \ + "13739.1, 13739.1, 13739.1, 14461.2, 15905.2", \ + "13739.1, 13739.1, 13739.1, 14461.2, 15905.2", \ + "13739.1, 13739.1, 13739.1, 14461.2, 15905.2"); + } + cell_fall (inslew_load_5x5__8) { + values ("3527.4, 3527.4, 3527.4, 3756.7, 4220.4", \ + "3536.2, 3536.2, 3536.2, 3765.5, 4229.2", \ + "3553.7, 3553.7, 3553.7, 3783.1, 4246.8", \ + "3588.9, 3588.9, 3588.9, 3818.2, 4282.0", \ + "3658.8, 3658.8, 3658.8, 3888.3, 4352.2"); + } + fall_transition (inslew_load_5x5__8) { + values ("3046.2, 3046.2, 3046.2, 3362.8, 3996.1", \ + "3046.2, 3046.2, 3046.2, 3362.8, 3996.1", \ + "3046.2, 3046.2, 3046.2, 3362.8, 3996.1", \ + "3046.2, 3046.2, 3046.2, 3362.8, 3996.1", \ + "3048.6, 3048.6, 3048.6, 3364.6, 3997.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__8) { + values ("11853.9, 11853.9, 11853.9, 13154.7, 15756.5", \ + "11897.6, 11897.6, 11897.6, 13198.5, 15800.2", \ + "11985.0, 11985.0, 11985.0, 13285.9, 15887.7", \ + "12159.9, 12159.9, 12159.9, 13460.8, 16062.5", \ + "12509.7, 12509.7, 12509.7, 13810.6, 16412.3"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("7465.2, 7465.2, 7465.2, 8766.1, 11367.8", \ + "7501.4, 7501.4, 7501.4, 8802.3, 11404.0", \ + "7573.9, 7573.9, 7573.9, 8874.8, 11476.5", \ + "7718.9, 7718.9, 7718.9, 9019.8, 11621.5", \ + "8008.8, 8008.8, 8008.8, 9309.7, 11911.4"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__8) { + values ("1337.6, 1337.6, 1337.6, 2638.5, 5240.2", \ + "1381.9, 1381.9, 1381.9, 2682.8, 5284.5", \ + "1470.5, 1470.5, 1470.5, 2771.3, 5373.1", \ + "1647.6, 1647.6, 1647.6, 2948.5, 5550.3", \ + "2002.0, 2002.0, 2002.0, 3302.8, 5904.6"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("1334.9, 1334.9, 1334.9, 2635.8, 5237.6", \ + "1361.4, 1361.4, 1361.4, 2662.3, 5264.0", \ + "1414.4, 1414.4, 1414.4, 2715.3, 5317.0", \ + "1520.3, 1520.3, 1520.3, 2821.2, 5422.9", \ + "1732.2, 1732.2, 1732.2, 3033.0, 5634.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__8) { + values ("23089.7, 23089.7, 23089.7, 24390.6, 26992.4", \ + "23129.6, 23129.6, 23129.6, 24430.5, 27032.3", \ + "23209.4, 23209.4, 23209.4, 24510.3, 27112.1", \ + "23369.0, 23369.0, 23369.0, 24669.9, 27271.6", \ + "23688.2, 23688.2, 23688.2, 24989.1, 27590.8"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("11158.2, 11158.2, 11158.2, 12459.1, 15060.8", \ + "11213.0, 11213.0, 11213.0, 12513.9, 15115.6", \ + "11322.6, 11322.6, 11322.6, 12623.5, 15225.2", \ + "11541.7, 11541.7, 11541.7, 12842.6, 15444.4", \ + "11980.1, 11980.1, 11980.1, 13280.9, 15882.7"); + } + } + } + } + + cell (ao22_x2) { + area : 21.60 ; + cell_leakage_power : 4 ; + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 4 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 4.3 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0))" ; + value : 4.5 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 3.5 ; + } + leakage_power () { + when : "(!((i0 ^ i1)) & i2)" ; + value : 4.4 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 3.1 ; + } + pin (i2) { + direction : input ; + capacitance : 438.92 ; + } + pin (i1) { + direction : input ; + capacitance : 435.52 ; + } + pin (i0) { + direction : input ; + capacitance : 432.96 ; + } + pin (q) { + function : "((i0 | i1) & i2)" ; + direction : output ; + capacitance : 89.41 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("7110.7, 7110.7, 7110.7, 7416.3, 7980.7", \ + "7119.0, 7119.0, 7119.0, 7424.5, 7988.7", \ + "7127.1, 7127.1, 7127.1, 7432.6, 7996.6", \ + "7142.3, 7142.3, 7142.3, 7447.8, 8011.8", \ + "7175.6, 7175.6, 7175.6, 7481.0, 8045.0"); + } + rise_transition (inslew_load_5x5__9) { + values ("3183.5, 3183.5, 3183.5, 3436.5, 3922.9", \ + "3189.6, 3189.6, 3189.6, 3442.5, 3928.8", \ + "3193.0, 3193.0, 3193.0, 3445.8, 3932.1", \ + "3194.1, 3194.1, 3194.1, 3446.9, 3933.1", \ + "3194.5, 3194.5, 3194.5, 3447.3, 3933.5"); + } + cell_fall (inslew_load_5x5__9) { + values ("9743.3, 9743.3, 9743.3, 10001.9, 10486.9", \ + "9738.0, 9738.0, 9738.0, 9996.6, 10481.6", \ + "9727.2, 9727.2, 9727.2, 9985.8, 10470.8", \ + "9705.8, 9705.8, 9705.8, 9964.4, 10449.4", \ + "9662.9, 9662.9, 9662.9, 9921.5, 10406.5"); + } + fall_transition (inslew_load_5x5__9) { + values ("4550.7, 4550.7, 4550.7, 4684.2, 4991.8", \ + "4550.7, 4550.7, 4550.7, 4684.2, 4991.8", \ + "4550.7, 4550.7, 4550.7, 4684.2, 4991.8", \ + "4550.7, 4550.7, 4550.7, 4684.2, 4991.8", \ + "4550.7, 4550.7, 4550.7, 4684.2, 4991.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("5823.7, 5823.7, 5823.7, 6151.9, 6743.0", \ + "5832.3, 5832.3, 5832.3, 6160.5, 6751.3", \ + "5840.5, 5840.5, 5840.5, 6168.6, 6759.4", \ + "5855.9, 5855.9, 5855.9, 6184.0, 6774.8", \ + "5889.3, 5889.3, 5889.3, 6217.4, 6808.1"); + } + rise_transition (inslew_load_5x5__9) { + values ("2268.0, 2268.0, 2268.0, 2546.9, 3058.3", \ + "2274.7, 2274.7, 2274.7, 2553.4, 3064.6", \ + "2278.3, 2278.3, 2278.3, 2557.0, 3068.1", \ + "2279.7, 2279.7, 2279.7, 2558.4, 3069.4", \ + "2280.5, 2280.5, 2280.5, 2559.1, 3070.1"); + } + cell_fall (inslew_load_5x5__9) { + values ("7237.1, 7237.1, 7237.1, 7485.6, 7983.5", \ + "7240.0, 7240.0, 7240.0, 7488.5, 7985.7", \ + "7249.0, 7249.0, 7249.0, 7497.5, 7993.5", \ + "7261.1, 7261.1, 7261.1, 7509.6, 8005.0", \ + "7289.7, 7289.7, 7289.7, 7538.2, 8033.4"); + } + fall_transition (inslew_load_5x5__9) { + values ("3070.9, 3070.9, 3070.9, 3259.6, 3622.8", \ + "3073.8, 3073.8, 3073.8, 3262.3, 3625.6", \ + "3079.4, 3079.4, 3079.4, 3267.7, 3631.1", \ + "3082.4, 3082.4, 3082.4, 3270.6, 3634.1", \ + "3083.2, 3083.2, 3083.2, 3271.4, 3634.8"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("7226.8, 7226.8, 7226.8, 7532.0, 8094.2", \ + "7221.6, 7221.6, 7221.6, 7526.8, 8089.0", \ + "7211.3, 7211.3, 7211.3, 7516.5, 8078.7", \ + "7190.7, 7190.7, 7190.7, 7495.9, 8058.1", \ + "7149.6, 7149.6, 7149.6, 7454.7, 8016.9"); + } + rise_transition (inslew_load_5x5__9) { + values ("3234.5, 3234.5, 3234.5, 3486.6, 3972.0", \ + "3234.5, 3234.5, 3234.5, 3486.6, 3972.0", \ + "3234.5, 3234.5, 3234.5, 3486.6, 3972.0", \ + "3234.5, 3234.5, 3234.5, 3486.6, 3972.0", \ + "3234.8, 3234.8, 3234.8, 3486.8, 3972.2"); + } + cell_fall (inslew_load_5x5__9) { + values ("5538.4, 5538.4, 5538.4, 5791.3, 6250.7", \ + "5547.2, 5547.2, 5547.2, 5800.1, 6259.5", \ + "5564.8, 5564.8, 5564.8, 5817.7, 6277.1", \ + "5599.9, 5599.9, 5599.9, 5852.8, 6312.2", \ + "5670.3, 5670.3, 5670.3, 5923.2, 6382.6"); + } + fall_transition (inslew_load_5x5__9) { + values ("1839.5, 1839.5, 1839.5, 2021.2, 2387.8", \ + "1839.5, 1839.5, 1839.5, 2021.2, 2387.8", \ + "1839.5, 1839.5, 1839.5, 2021.2, 2387.8", \ + "1839.5, 1839.5, 1839.5, 2021.2, 2387.8", \ + "1839.5, 1839.5, 1839.5, 2021.2, 2387.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__9) { + values ("26524.4, 26524.4, 26524.4, 27642.1, 29877.4", \ + "26564.8, 26564.8, 26564.8, 27682.5, 29917.8", \ + "26623.6, 26623.6, 26623.6, 27741.3, 29976.6", \ + "26727.0, 26727.0, 26727.0, 27844.7, 30080.0", \ + "26929.5, 26929.5, 26929.5, 28047.1, 30282.5"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("31988.4, 31988.4, 31988.4, 33106.0, 35341.4", \ + "35372.9, 35372.9, 35372.9, 35372.9, 35372.9", \ + "35436.0, 35436.0, 35436.0, 35436.0, 35436.0", \ + "35562.3, 35562.3, 35562.3, 35562.3, 35562.3", \ + "35814.8, 35814.8, 35814.8, 35814.8, 35814.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__9) { + values ("21689.3, 21689.3, 21689.3, 22807.0, 25042.3", \ + "21715.3, 21715.3, 21715.3, 22832.9, 25068.3", \ + "21745.8, 21745.8, 21745.8, 22863.5, 25098.8", \ + "21793.4, 21793.4, 21793.4, 22911.1, 25146.4", \ + "21883.9, 21883.9, 21883.9, 23001.6, 25237.0"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("22205.2, 22205.2, 22205.2, 23322.8, 25558.2", \ + "22254.5, 22254.5, 22254.5, 23372.1, 25607.5", \ + "22352.8, 22352.8, 22352.8, 23470.4, 25705.8", \ + "22525.6, 22525.6, 22525.6, 23643.2, 25878.6", \ + "22855.5, 22855.5, 22855.5, 23973.1, 26208.5"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__9) { + values ("27017.0, 27017.0, 27017.0, 28134.6, 30370.0", \ + "30392.9, 30392.9, 30392.9, 30392.9, 30392.9", \ + "30438.7, 30438.7, 30438.7, 30438.7, 30438.7", \ + "30530.3, 30530.3, 30530.3, 30530.3, 30530.3", \ + "27361.0, 27361.0, 27361.0, 28478.6, 30714.0"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("21348.8, 21348.8, 21348.8, 22466.4, 24701.8", \ + "24745.9, 24745.9, 24745.9, 24745.9, 24745.9", \ + "24834.0, 24834.0, 24834.0, 24834.0, 24834.0", \ + "25010.4, 25010.4, 25010.4, 25010.4, 25010.4", \ + "22010.3, 22010.3, 22010.3, 23127.9, 25363.3"); + } + } + } + } + + cell (buf_x2) { + area : 14.40 ; + cell_leakage_power : 2.9 ; + leakage_power () { + when : "i" ; + value : 3.3 ; + } + leakage_power () { + when : "!(i)" ; + value : 2.5 ; + } + pin (i) { + direction : input ; + capacitance : 273.38 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 85.77 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("4748.3, 4748.3, 4748.3, 5082.3, 5687.6", \ + "4757.1, 4757.1, 4757.1, 5091.1, 5696.4", \ + "4774.7, 4774.7, 4774.7, 5108.7, 5714.0", \ + "4809.9, 4809.9, 4809.9, 5143.9, 5749.2", \ + "4881.1, 4881.1, 4881.1, 5215.1, 5820.4"); + } + rise_transition (inslew_load_5x5__0) { + values ("1309.7, 1309.7, 1309.7, 1596.2, 2140.4", \ + "1309.7, 1309.7, 1309.7, 1596.2, 2140.4", \ + "1309.7, 1309.7, 1309.7, 1596.2, 2140.4", \ + "1309.7, 1309.7, 1309.7, 1596.2, 2140.4", \ + "1311.2, 1311.2, 1311.2, 1597.7, 2141.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("6612.2, 6612.2, 6612.2, 6935.7, 7454.3", \ + "6621.0, 6621.0, 6621.0, 6944.5, 7463.1", \ + "6638.5, 6638.5, 6638.5, 6962.0, 7480.6", \ + "6673.7, 6673.7, 6673.7, 6997.2, 7515.8", \ + "6744.1, 6744.1, 6744.1, 7067.6, 7586.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("2469.6, 2469.6, 2469.6, 2690.3, 3000.5", \ + "2469.6, 2469.6, 2469.6, 2690.3, 3000.5", \ + "2469.6, 2469.6, 2469.6, 2690.3, 3000.5", \ + "2469.6, 2469.6, 2469.6, 2690.3, 3000.5", \ + "2469.6, 2469.6, 2469.6, 2690.3, 3000.5"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__0) { + values ("19035.9, 19035.9, 19035.9, 20108.1, 22252.4", \ + "22266.1, 22266.1, 22266.1, 22266.1, 22266.1", \ + "22293.6, 22293.6, 22293.6, 22293.6, 22293.6", \ + "22348.5, 22348.5, 22348.5, 22348.5, 22348.5", \ + "19244.9, 19244.9, 19244.9, 20317.0, 22461.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("19723.2, 19723.2, 19723.2, 20795.4, 22939.7", \ + "22966.1, 22966.1, 22966.1, 22966.1, 22966.1", \ + "23019.0, 23019.0, 23019.0, 23019.0, 23019.0", \ + "23124.7, 23124.7, 23124.7, 23124.7, 23124.7", \ + "23336.0, 23336.0, 23336.0, 23336.0, 23336.0"); + } + } + } + } + + cell (sff2_x4) { + area : 86.40 ; + cell_leakage_power : 16 ; + pin (i1) { + direction : input ; + capacitance : 432.17 ; + internal_power (energy_i1) { + rise_power (energy_inslew_5__0) { + values ("30711.0, 30733.9, 30779.7, 30871.3, 31055.1"); + } + fall_power (energy_inslew_5__0) { + values ("30915.3, 30959.4, 31047.5, 31223.9, 31576.6"); + } + } + } + pin (i0) { + direction : input ; + capacitance : 436.17 ; + internal_power (energy_i0) { + rise_power (energy_inslew_5__0) { + values ("30711.0, 30733.9, 30779.7, 30871.3, 31055.1"); + } + fall_power (energy_inslew_5__0) { + values ("30915.3, 30959.4, 31047.5, 31223.9, 31576.6"); + } + } + } + pin (cmd) { + direction : input ; + capacitance : 856.62 ; + internal_power (energy_cmd) { + rise_power (energy_inslew_5__0) { + values ("50919.2, 50942.1, 50987.9, 51080.3, 51284.8"); + } + fall_power (energy_inslew_5__0) { + values ("51061.2, 51105.3, 51193.4, 51369.9, 51724.8"); + } + } + } + pin (ck) { + direction : input ; + clock : true ; + capacitance : 436.17 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("46872.3, 46895.2, 46941.0, 47032.6, 47218.0"); + } + fall_power (energy_inslew_5__0) { + values ("48838.2, 48882.3, 48970.5, 49146.8, 49499.6"); + } + } + } + pin (q) { + direction : output ; + function : "IQ" ; + capacitance : 581.88 ; + } + ff(IQ,IQN) { + next_state : "(cmd * i1) + (cmd' * i0)" ; + clocked_on : "ck" ; + } + } + + cell (noa2ao222_x1) { + area : 25.20 ; + cell_leakage_power : 5.6 ; + leakage_power () { + when : "(i4 & i3 & i2 & i1 & i0)" ; + value : 4.8 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & i3) ^ i4))" ; + value : 4.5 ; + } + leakage_power () { + when : "(i0 & i1 & !((i2 & i3)) & !(i4))" ; + value : 4.1 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & !(i1) & i0)" ; + value : 7.4 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & i0)" ; + value : 6.8 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3 & i4)" ; + value : 5.8 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & i1 & !(i0))" ; + value : 7.1 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & i4)" ; + value : 5.6 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & i3 & i4)" ; + value : 5.3 ; + } + leakage_power () { + when : "(!(i0) & i1 & (i2 ^ i3) & !(i4))" ; + value : 5.9 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & !(i0))" ; + value : 6.4 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & !(i0))" ; + value : 4.6 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & i2 & i4)" ; + value : 6.7 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & !(i4)) | (!(i0) & !(i1) & ((i2 & i3 & !(i4)) | (!(i2) & i3 & i4))))" ; + value : 6.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4)) | (!(i0) & !(i1) & (i2 ^ i3) & !(i4)))" ; + value : 5 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.5 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 3.8 ; + } + pin (i4) { + direction : input ; + capacitance : 817.54 ; + } + pin (i3) { + direction : input ; + capacitance : 817.99 ; + } + pin (i2) { + direction : input ; + capacitance : 816.04 ; + } + pin (i1) { + direction : input ; + capacitance : 664.65 ; + } + pin (i0) { + direction : input ; + capacitance : 666.60 ; + } + pin (nq) { + function : "((((!(i4) & !(i0)) | (!(i4) & !(i1))) | ((!(i2) & !(i3)) & !(i0))) | ((!(i2) & !(i3)) & !(i1)))" ; + direction : output ; + capacitance : 146.76 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("11925.7, 11925.7, 11925.7, 12533.5, 13806.8", \ + "11918.4, 11918.4, 11918.4, 12526.3, 13799.7", \ + "11903.9, 11903.9, 11903.9, 12512.0, 13785.5", \ + "11874.8, 11874.8, 11874.8, 12483.3, 13757.0", \ + "11816.7, 11816.7, 11816.7, 12425.8, 13700.1"); + } + rise_transition (inslew_load_5x5__10) { + values ("17869.3, 17869.3, 17869.3, 19027.6, 21344.4", \ + "17869.3, 17869.3, 17869.3, 19027.6, 21344.4", \ + "17869.3, 17869.3, 17869.3, 19027.6, 21344.4", \ + "17869.3, 17869.3, 17869.3, 19027.6, 21344.4", \ + "17869.3, 17869.3, 17869.3, 19027.6, 21344.4"); + } + cell_fall (inslew_load_5x5__10) { + values ("4166.0, 4166.0, 4166.0, 4445.3, 5018.3", \ + "4160.8, 4160.8, 4160.8, 4440.1, 5013.2", \ + "4150.4, 4150.4, 4150.4, 4429.8, 5002.8", \ + "4129.7, 4129.7, 4129.7, 4409.1, 4982.2", \ + "4088.1, 4088.1, 4088.1, 4367.7, 4940.9"); + } + fall_transition (inslew_load_5x5__10) { + values ("5119.5, 5119.5, 5119.5, 5576.8, 6491.4", \ + "5119.5, 5119.5, 5119.5, 5576.8, 6491.4", \ + "5119.5, 5119.5, 5119.5, 5576.8, 6491.4", \ + "5119.5, 5119.5, 5119.5, 5576.8, 6491.4", \ + "5120.8, 5120.8, 5120.8, 5577.7, 6491.9"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("10887.5, 10887.5, 10887.5, 11502.4, 12782.4", \ + "10880.3, 10880.3, 10880.3, 11495.2, 12775.3", \ + "10865.8, 10865.8, 10865.8, 11480.9, 12761.0", \ + "10836.8, 10836.8, 10836.8, 11452.2, 12732.6", \ + "10778.8, 10778.8, 10778.8, 11394.9, 12675.7"); + } + rise_transition (inslew_load_5x5__10) { + values ("16099.4, 16099.4, 16099.4, 17257.8, 19574.5", \ + "16099.4, 16099.4, 16099.4, 17257.8, 19574.5", \ + "16099.4, 16099.4, 16099.4, 17257.8, 19574.5", \ + "16099.4, 16099.4, 16099.4, 17257.8, 19574.5", \ + "16099.4, 16099.4, 16099.4, 17257.8, 19574.5"); + } + cell_fall (inslew_load_5x5__10) { + values ("3343.0, 3343.0, 3343.0, 3629.5, 4211.5", \ + "3346.3, 3346.3, 3346.3, 3632.9, 4215.1", \ + "3353.4, 3353.4, 3353.4, 3640.0, 4222.0", \ + "3369.7, 3369.7, 3369.7, 3656.3, 4238.4", \ + "3402.5, 3402.5, 3402.5, 3689.5, 4271.8"); + } + fall_transition (inslew_load_5x5__10) { + values ("3905.2, 3905.2, 3905.2, 4370.4, 5300.9", \ + "3908.6, 3908.6, 3908.6, 4373.9, 5304.5", \ + "3909.9, 3909.9, 3909.9, 4375.1, 5305.5", \ + "3910.2, 3910.2, 3910.2, 4375.4, 5305.9", \ + "3913.1, 3913.1, 3913.1, 4377.3, 5306.7"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("4030.3, 4030.3, 4030.3, 4694.3, 6024.3", \ + "4014.9, 4014.9, 4014.9, 4677.3, 6005.2", \ + "4058.5, 4058.5, 4058.5, 4720.2, 6047.4", \ + "4083.6, 4083.6, 4083.6, 4743.0, 6067.5", \ + "4133.2, 4133.2, 4133.2, 4793.9, 6120.7"); + } + rise_transition (inslew_load_5x5__10) { + values ("3978.8, 3978.8, 3978.8, 5153.5, 7509.6", \ + "3968.2, 3968.2, 3968.2, 5139.9, 7492.2", \ + "4075.8, 4075.8, 4075.8, 5246.3, 7597.3", \ + "4170.3, 4170.3, 4170.3, 5336.6, 7682.8", \ + "4325.7, 4325.7, 4325.7, 5493.7, 7843.4"); + } + cell_fall (inslew_load_5x5__10) { + values ("2577.3, 2577.3, 2577.3, 2870.2, 3456.6", \ + "2572.2, 2572.2, 2572.2, 2865.0, 3451.5", \ + "2561.9, 2561.9, 2561.9, 2854.7, 3441.2", \ + "2541.2, 2541.2, 2541.2, 2834.1, 3420.5", \ + "2496.5, 2496.5, 2496.5, 2791.0, 3378.8"); + } + fall_transition (inslew_load_5x5__10) { + values ("2365.5, 2365.5, 2365.5, 2822.8, 3737.4", \ + "2365.5, 2365.5, 2365.5, 2822.8, 3737.4", \ + "2365.5, 2365.5, 2365.5, 2822.8, 3737.4", \ + "2365.6, 2365.6, 2365.6, 2822.8, 3737.4", \ + "2375.1, 2375.1, 2375.1, 2829.7, 3740.8"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("7972.2, 7972.2, 7972.2, 8611.0, 9912.7", \ + "7960.5, 7960.5, 7960.5, 8599.1, 9900.5", \ + "7957.0, 7957.0, 7957.0, 8596.1, 9898.1", \ + "7935.0, 7935.0, 7935.0, 8574.4, 9876.9", \ + "7899.8, 7899.8, 7899.8, 8540.5, 9844.8"); + } + rise_transition (inslew_load_5x5__10) { + values ("10697.2, 10697.2, 10697.2, 11859.2, 14185.0", \ + "10696.2, 10696.2, 10696.2, 11858.0, 14183.2", \ + "10727.0, 10727.0, 10727.0, 11889.3, 14215.5", \ + "10752.8, 10752.8, 10752.8, 11915.5, 14242.2", \ + "10794.8, 10794.8, 10794.8, 11959.1, 14288.5"); + } + cell_fall (inslew_load_5x5__10) { + values ("3473.3, 3473.3, 3473.3, 3760.6, 4341.1", \ + "3468.2, 3468.2, 3468.2, 3755.5, 4335.9", \ + "3457.8, 3457.8, 3457.8, 3745.1, 4325.6", \ + "3437.2, 3437.2, 3437.2, 3724.5, 4304.9", \ + "3395.4, 3395.4, 3395.4, 3683.0, 4263.6"); + } + fall_transition (inslew_load_5x5__10) { + values ("3721.6, 3721.6, 3721.6, 4178.9, 5093.5", \ + "3721.6, 3721.6, 3721.6, 4178.9, 5093.5", \ + "3721.6, 3721.6, 3721.6, 4178.9, 5093.5", \ + "3721.6, 3721.6, 3721.6, 4178.9, 5093.5", \ + "3724.8, 3724.8, 3724.8, 4181.1, 5094.5"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("2366.9, 2366.9, 2366.9, 2890.4, 3928.0", \ + "2381.9, 2381.9, 2381.9, 2905.3, 3943.0", \ + "2400.4, 2400.4, 2400.4, 2923.7, 3961.6", \ + "2414.0, 2414.0, 2414.0, 2936.3, 3973.4", \ + "2421.4, 2421.4, 2421.4, 2948.5, 3990.5"); + } + rise_transition (inslew_load_5x5__10) { + values ("1491.5, 1491.5, 1491.5, 2338.0, 4027.3", \ + "1525.8, 1525.8, 1525.8, 2372.2, 4061.6", \ + "1572.4, 1572.4, 1572.4, 2418.5, 4108.4", \ + "1616.5, 1616.5, 1616.5, 2461.1, 4149.5", \ + "1657.0, 1657.0, 1657.0, 2501.2, 4192.3"); + } + cell_fall (inslew_load_5x5__10) { + values ("1690.8, 1690.8, 1690.8, 1990.6, 2585.1", \ + "1694.6, 1694.6, 1694.6, 1994.6, 2589.7", \ + "1700.2, 1700.2, 1700.2, 2000.1, 2595.4", \ + "1718.2, 1718.2, 1718.2, 2017.9, 2612.1", \ + "1729.6, 1729.6, 1729.6, 2039.6, 2641.8"); + } + fall_transition (inslew_load_5x5__10) { + values ("1025.1, 1025.1, 1025.1, 1489.8, 2418.0", \ + "1031.3, 1031.3, 1031.3, 1496.3, 2425.5", \ + "1034.0, 1034.0, 1034.0, 1498.9, 2428.3", \ + "1041.1, 1041.1, 1041.1, 1505.1, 2432.5", \ + "1052.3, 1052.3, 1052.3, 1516.4, 2439.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__10) { + values ("26615.4, 26615.4, 26615.4, 28449.8, 32118.7", \ + "26693.4, 26693.4, 26693.4, 28527.8, 32196.7", \ + "26849.3, 26849.3, 26849.3, 28683.8, 32352.7", \ + "27161.2, 27161.2, 27161.2, 28995.7, 32664.6", \ + "27785.0, 27785.0, 27785.0, 29619.5, 33288.4"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("18842.7, 18842.7, 18842.7, 20677.1, 24346.0", \ + "18873.3, 18873.3, 18873.3, 20707.7, 24376.6", \ + "18934.5, 18934.5, 18934.5, 20769.0, 24437.9", \ + "19057.0, 19057.0, 19057.0, 20891.4, 24560.3", \ + "19301.9, 19301.9, 19301.9, 21136.4, 24805.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__10) { + values ("23792.7, 23792.7, 23792.7, 25627.1, 29296.0", \ + "23850.7, 23850.7, 23850.7, 25685.1, 29354.0", \ + "23966.7, 23966.7, 23966.7, 25801.1, 29470.0", \ + "24198.7, 24198.7, 24198.7, 26033.1, 29702.0", \ + "24662.7, 24662.7, 24662.7, 26497.1, 30166.0"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("13748.3, 13748.3, 13748.3, 15582.7, 19251.6", \ + "13782.3, 13782.3, 13782.3, 15616.7, 19285.6", \ + "13850.3, 13850.3, 13850.3, 15684.8, 19353.7", \ + "13986.4, 13986.4, 13986.4, 15820.9, 19489.8", \ + "14258.6, 14258.6, 14258.6, 16093.1, 19762.0"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__10) { + values ("4840.3, 4840.3, 4840.3, 6674.8, 10343.7", \ + "4913.9, 4913.9, 4913.9, 6748.3, 10417.2", \ + "5061.0, 5061.0, 5061.0, 6895.5, 10564.4", \ + "5355.4, 5355.4, 5355.4, 7189.8, 10858.7", \ + "5944.0, 5944.0, 5944.0, 7778.4, 11447.3"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("7296.3, 7296.3, 7296.3, 9130.7, 12799.6", \ + "7314.7, 7314.7, 7314.7, 9149.2, 12818.1", \ + "7351.6, 7351.6, 7351.6, 9186.0, 12854.9", \ + "7425.3, 7425.3, 7425.3, 9259.7, 12928.6", \ + "7572.7, 7572.7, 7572.7, 9407.2, 13076.1"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__10) { + values ("15011.8, 15011.8, 15011.8, 16846.3, 20515.2", \ + "15088.7, 15088.7, 15088.7, 16923.1, 20592.0", \ + "15242.4, 15242.4, 15242.4, 17076.8, 20745.7", \ + "15549.8, 15549.8, 15549.8, 17384.3, 21053.1", \ + "16164.6, 16164.6, 16164.6, 17999.1, 21668.0"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("12743.6, 12743.6, 12743.6, 14578.1, 18247.0", \ + "12769.6, 12769.6, 12769.6, 14604.1, 18273.0", \ + "12821.6, 12821.6, 12821.6, 14656.0, 18324.9", \ + "12925.5, 12925.5, 12925.5, 14760.0, 18428.9", \ + "13133.4, 13133.4, 13133.4, 14967.8, 18636.7"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__10) { + values ("1836.7, 1836.7, 1836.7, 3671.1, 7340.0", \ + "1894.0, 1894.0, 1894.0, 3728.5, 7397.4", \ + "2008.8, 2008.8, 2008.8, 3843.2, 7512.1", \ + "2238.2, 2238.2, 2238.2, 4072.7, 7741.6", \ + "2697.2, 2697.2, 2697.2, 4531.7, 8200.6"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("1919.3, 1919.3, 1919.3, 3753.7, 7422.6", \ + "1948.9, 1948.9, 1948.9, 3783.3, 7452.2", \ + "2008.2, 2008.2, 2008.2, 3842.6, 7511.5", \ + "2126.8, 2126.8, 2126.8, 3961.2, 7630.1", \ + "2363.9, 2363.9, 2363.9, 4198.4, 7867.3"); + } + } + } + } + + cell (nao22_x1) { + area : 21.60 ; + cell_leakage_power : 3.9 ; + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 4.7 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 3.1 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 3.3 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 3.8 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 5.5 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 2.8 ; + } + pin (i2) { + direction : input ; + capacitance : 853.12 ; + } + pin (i1) { + direction : input ; + capacitance : 848.02 ; + } + pin (i0) { + direction : input ; + capacitance : 846.52 ; + } + pin (nq) { + function : "(!(i2) | (!(i1) & !(i0)))" ; + direction : output ; + capacitance : 151.11 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("5101.8, 5101.8, 5101.8, 5544.8, 6443.6", \ + "5096.3, 5096.3, 5096.3, 5539.4, 6438.2", \ + "5085.5, 5085.5, 5085.5, 5528.6, 6427.5", \ + "5063.8, 5063.8, 5063.8, 5507.0, 6406.0", \ + "5020.4, 5020.4, 5020.4, 5463.8, 6363.0"); + } + rise_transition (inslew_load_5x5__11) { + values ("5866.8, 5866.8, 5866.8, 6587.0, 8027.6", \ + "5866.8, 5866.8, 5866.8, 6587.0, 8027.6", \ + "5866.8, 5866.8, 5866.8, 6587.0, 8027.6", \ + "5866.8, 5866.8, 5866.8, 6587.0, 8027.6", \ + "5867.1, 5867.1, 5867.1, 6587.2, 8027.6"); + } + cell_fall (inslew_load_5x5__11) { + values ("2348.1, 2348.1, 2348.1, 2620.7, 3166.7", \ + "2352.6, 2352.6, 2352.6, 2625.5, 3172.0", \ + "2358.3, 2358.3, 2358.3, 2631.2, 3177.7", \ + "2375.1, 2375.1, 2375.1, 2647.6, 3193.6", \ + "2402.3, 2402.3, 2402.3, 2677.2, 3225.3"); + } + fall_transition (inslew_load_5x5__11) { + values ("2156.6, 2156.6, 2156.6, 2586.8, 3447.6", \ + "2164.0, 2164.0, 2164.0, 2594.6, 3456.1", \ + "2166.7, 2166.7, 2166.7, 2597.4, 3459.0", \ + "2170.9, 2170.9, 2170.9, 2600.8, 3461.6", \ + "2179.0, 2179.0, 2179.0, 2606.8, 3464.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("2200.8, 2200.8, 2200.8, 2665.1, 3586.3", \ + "2205.6, 2205.6, 2205.6, 2669.7, 3590.6", \ + "2213.8, 2213.8, 2213.8, 2678.1, 3599.8", \ + "2224.5, 2224.5, 2224.5, 2689.0, 3611.5", \ + "2252.8, 2252.8, 2252.8, 2720.6, 3642.9"); + } + rise_transition (inslew_load_5x5__11) { + values ("1411.5, 1411.5, 1411.5, 2143.6, 3606.4", \ + "1422.4, 1422.4, 1422.4, 2154.2, 3616.4", \ + "1436.6, 1436.6, 1436.6, 2168.7, 3632.2", \ + "1442.5, 1442.5, 1442.5, 2174.9, 3639.6", \ + "1463.0, 1463.0, 1463.0, 2191.0, 3648.1"); + } + cell_fall (inslew_load_5x5__11) { + values ("1556.1, 1556.1, 1556.1, 1833.9, 2384.6", \ + "1559.9, 1559.9, 1559.9, 1837.8, 2389.2", \ + "1565.5, 1565.5, 1565.5, 1843.4, 2394.8", \ + "1583.2, 1583.2, 1583.2, 1861.1, 2411.6", \ + "1587.5, 1587.5, 1587.5, 1878.2, 2439.3"); + } + fall_transition (inslew_load_5x5__11) { + values ("944.4, 944.4, 944.4, 1374.9, 2234.8", \ + "950.6, 950.6, 950.6, 1381.3, 2242.2", \ + "953.1, 953.1, 953.1, 1383.9, 2244.9", \ + "960.5, 960.5, 960.5, 1390.2, 2249.0", \ + "971.7, 971.7, 971.7, 1402.6, 2257.0"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("2189.5, 2189.5, 2189.5, 2471.1, 3035.5", \ + "2198.3, 2198.3, 2198.3, 2479.9, 3044.3", \ + "2215.9, 2215.9, 2215.9, 2497.5, 3061.9", \ + "2250.9, 2250.9, 2250.9, 2532.6, 3097.0", \ + "2315.5, 2315.5, 2315.5, 2599.9, 3166.5"); + } + rise_transition (inslew_load_5x5__11) { + values ("1698.1, 1698.1, 1698.1, 2082.1, 2850.2", \ + "1698.1, 1698.1, 1698.1, 2082.1, 2850.2", \ + "1698.1, 1698.1, 1698.1, 2082.1, 2850.2", \ + "1698.3, 1698.3, 1698.3, 2082.2, 2850.2", \ + "1712.8, 1712.8, 1712.8, 2092.9, 2855.5"); + } + cell_fall (inslew_load_5x5__11) { + values ("2441.0, 2441.0, 2441.0, 2711.9, 3254.9", \ + "2435.8, 2435.8, 2435.8, 2706.8, 3249.7", \ + "2425.5, 2425.5, 2425.5, 2696.4, 3239.4", \ + "2404.7, 2404.7, 2404.7, 2675.7, 3218.7", \ + "2359.0, 2359.0, 2359.0, 2632.0, 3176.7"); + } + fall_transition (inslew_load_5x5__11) { + values ("2282.8, 2282.8, 2282.8, 2706.6, 3554.0", \ + "2282.8, 2282.8, 2282.8, 2706.6, 3554.0", \ + "2282.8, 2282.8, 2282.8, 2706.6, 3554.0", \ + "2283.0, 2283.0, 2283.0, 2706.6, 3554.0", \ + "2294.6, 2294.6, 2294.6, 2715.3, 3558.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__11) { + values ("13556.5, 13556.5, 13556.5, 15445.4, 19223.0", \ + "13619.7, 13619.7, 13619.7, 15508.5, 19286.2", \ + "13746.0, 13746.0, 13746.0, 15634.8, 19412.5", \ + "13998.6, 13998.6, 13998.6, 15887.4, 19665.1", \ + "14503.8, 14503.8, 14503.8, 16392.6, 20170.3"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("7312.7, 7312.7, 7312.7, 9201.5, 12979.2", \ + "7363.1, 7363.1, 7363.1, 9251.9, 13029.6", \ + "7463.9, 7463.9, 7463.9, 9352.7, 13130.4", \ + "7665.5, 7665.5, 7665.5, 9554.3, 13332.0", \ + "8068.7, 8068.7, 8068.7, 9957.5, 13735.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__11) { + values ("1902.5, 1902.5, 1902.5, 3791.3, 7569.0", \ + "1966.2, 1966.2, 1966.2, 3855.1, 7632.8", \ + "2093.8, 2093.8, 2093.8, 3982.6, 7760.3", \ + "2348.9, 2348.9, 2348.9, 4237.8, 8015.4", \ + "2859.2, 2859.2, 2859.2, 4748.0, 8525.7"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("1971.7, 1971.7, 1971.7, 3860.6, 7638.2", \ + "2004.5, 2004.5, 2004.5, 3893.3, 7671.0", \ + "2070.0, 2070.0, 2070.0, 3958.8, 7736.5", \ + "2201.0, 2201.0, 2201.0, 4089.9, 7867.5", \ + "2463.1, 2463.1, 2463.1, 4351.9, 8129.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__11) { + values ("7033.1, 7033.1, 7033.1, 8921.9, 12699.6", \ + "7121.5, 7121.5, 7121.5, 9010.3, 12788.0", \ + "7298.3, 7298.3, 7298.3, 9187.1, 12964.8", \ + "7651.9, 7651.9, 7651.9, 9540.7, 13318.4", \ + "8359.0, 8359.0, 8359.0, 10247.9, 14025.5"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("7961.3, 7961.3, 7961.3, 9850.2, 13627.8", \ + "8007.0, 8007.0, 8007.0, 9895.9, 13673.6", \ + "8098.5, 8098.5, 8098.5, 9987.3, 13765.0", \ + "8281.3, 8281.3, 8281.3, 10170.2, 13947.8", \ + "8647.0, 8647.0, 8647.0, 10535.9, 14313.5"); + } + } + } + } + + cell (zero_x0) { + area : 10.80 ; + cell_leakage_power : 0 ; + pin (nq) { + function : "0" ; + direction : output ; + capacitance : 30.09 ; + } + } + + cell (nxr2_x4) { + area : 43.20 ; + cell_leakage_power : 12 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 13 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 11 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 10 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 15 ; + } + pin (i1) { + direction : input ; + capacitance : 1270.79 ; + } + pin (i0) { + direction : input ; + capacitance : 1268.50 ; + } + pin (nq) { + function : "!((i1 ^ i0))" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_nq_i0_positive_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("9129.2, 9129.2, 9129.2, 9383.4, 9865.9", \ + "9124.1, 9124.1, 9124.1, 9378.3, 9860.8", \ + "9113.8, 9113.8, 9113.8, 9368.0, 9850.5", \ + "9093.2, 9093.2, 9093.2, 9347.4, 9829.9", \ + "9051.9, 9051.9, 9051.9, 9306.1, 9788.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("4517.6, 4517.6, 4517.6, 4717.4, 5111.3", \ + "4517.6, 4517.6, 4517.6, 4717.4, 5111.3", \ + "4517.6, 4517.6, 4517.6, 4717.4, 5111.3", \ + "4517.6, 4517.6, 4517.6, 4717.4, 5111.3", \ + "4517.6, 4517.6, 4517.6, 4717.4, 5111.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("10452.8, 10452.8, 10452.8, 10760.6, 11183.7", \ + "10447.4, 10447.4, 10447.4, 10755.2, 11178.3", \ + "10436.7, 10436.7, 10436.7, 10744.5, 11167.6", \ + "10415.2, 10415.2, 10415.2, 10723.0, 11146.1", \ + "10372.4, 10372.4, 10372.4, 10680.2, 11103.3"); + } + fall_transition (inslew_load_5x5__3) { + values ("5006.8, 5006.8, 5006.8, 5143.5, 5378.0", \ + "5006.8, 5006.8, 5006.8, 5143.5, 5378.0", \ + "5006.8, 5006.8, 5006.8, 5143.5, 5378.0", \ + "5006.8, 5006.8, 5006.8, 5143.5, 5378.0", \ + "5006.8, 5006.8, 5006.8, 5143.5, 5378.0"); + } + } + timing (maxd_nq_i1_positive_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("7958.2, 7958.2, 7958.2, 8216.4, 8701.2", \ + "7963.0, 7963.0, 7963.0, 8221.2, 8706.0", \ + "7970.2, 7970.2, 7970.2, 8228.4, 8713.2", \ + "7986.9, 7986.9, 7986.9, 8245.1, 8729.9", \ + "8020.5, 8020.5, 8020.5, 8278.7, 8763.5"); + } + rise_transition (inslew_load_5x5__3) { + values ("3761.6, 3761.6, 3761.6, 3970.1, 4372.2", \ + "3764.0, 3764.0, 3764.0, 3972.5, 4374.6", \ + "3764.6, 3764.6, 3764.6, 3973.1, 4375.1", \ + "3765.0, 3765.0, 3765.0, 3973.5, 4375.5", \ + "3765.0, 3765.0, 3765.0, 3973.5, 4375.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("9893.5, 9893.5, 9893.5, 10116.3, 10534.8", \ + "9888.1, 9888.1, 9888.1, 10110.9, 10529.4", \ + "9877.4, 9877.4, 9877.4, 10100.2, 10518.7", \ + "9856.0, 9856.0, 9856.0, 10078.8, 10497.3", \ + "9813.1, 9813.1, 9813.1, 10035.9, 10454.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("4650.1, 4650.1, 4650.1, 4758.0, 5005.2", \ + "4650.1, 4650.1, 4650.1, 4758.0, 5005.2", \ + "4650.1, 4650.1, 4650.1, 4758.0, 5005.2", \ + "4650.1, 4650.1, 4650.1, 4758.0, 5005.2", \ + "4650.1, 4650.1, 4650.1, 4758.0, 5005.2"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("11169.1, 11169.1, 11169.1, 11433.9, 11928.7", \ + "11177.9, 11177.9, 11177.9, 11442.7, 11937.5", \ + "11195.5, 11195.5, 11195.5, 11460.3, 11955.1", \ + "11230.7, 11230.7, 11230.7, 11495.5, 11990.3", \ + "11301.2, 11301.2, 11301.2, 11566.0, 12060.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("2929.7, 2929.7, 2929.7, 3149.8, 3573.0", \ + "2929.7, 2929.7, 2929.7, 3149.8, 3573.0", \ + "2929.7, 2929.7, 2929.7, 3149.8, 3573.0", \ + "2929.7, 2929.7, 2929.7, 3149.8, 3573.0", \ + "2929.9, 2929.9, 2929.9, 3150.0, 3573.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("10148.6, 10148.6, 10148.6, 10360.7, 10773.4", \ + "10157.4, 10157.4, 10157.4, 10369.5, 10782.2", \ + "10175.0, 10175.0, 10175.0, 10387.1, 10799.8", \ + "10210.2, 10210.2, 10210.2, 10422.3, 10835.0", \ + "10279.9, 10279.9, 10279.9, 10492.0, 10904.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("3079.5, 3079.5, 3079.5, 3236.0, 3559.0", \ + "3079.5, 3079.5, 3079.5, 3236.0, 3559.0", \ + "3079.5, 3079.5, 3079.5, 3236.0, 3559.0", \ + "3079.5, 3079.5, 3079.5, 3236.0, 3559.0", \ + "3079.8, 3079.8, 3079.8, 3236.3, 3559.3"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("11740.8, 11740.8, 11740.8, 11999.6, 12484.6", \ + "11749.6, 11749.6, 11749.6, 12008.4, 12493.4", \ + "11767.2, 11767.2, 11767.2, 12026.0, 12511.0", \ + "11802.4, 11802.4, 11802.4, 12061.2, 12546.2", \ + "11872.8, 11872.8, 11872.8, 12131.5, 12616.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("3684.0, 3684.0, 3684.0, 3893.3, 4297.2", \ + "3684.0, 3684.0, 3684.0, 3893.3, 4297.2", \ + "3684.0, 3684.0, 3684.0, 3893.3, 4297.2", \ + "3684.0, 3684.0, 3684.0, 3893.3, 4297.2", \ + "3684.1, 3684.1, 3684.1, 3893.5, 4297.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("10921.0, 10921.0, 10921.0, 11137.2, 11456.9", \ + "10929.8, 10929.8, 10929.8, 11146.0, 11465.7", \ + "10947.4, 10947.4, 10947.4, 11163.6, 11483.3", \ + "10982.6, 10982.6, 10982.6, 11198.8, 11518.5", \ + "11052.4, 11052.4, 11052.4, 11268.5, 11588.2"); + } + fall_transition (inslew_load_5x5__3) { + values ("3569.4, 3569.4, 3569.4, 3700.4, 3917.2", \ + "3569.4, 3569.4, 3569.4, 3700.4, 3917.2", \ + "3569.4, 3569.4, 3569.4, 3700.4, 3917.2", \ + "3569.4, 3569.4, 3569.4, 3700.4, 3917.2", \ + "3569.6, 3569.6, 3569.6, 3700.6, 3917.4"); + } + } + internal_power (energy_pos_nq_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("69473.4, 69473.4, 69473.4, 71369.2, 75160.9", \ + "75206.6, 75206.6, 75206.6, 75206.6, 75206.6", \ + "75298.0, 75298.0, 75298.0, 75298.0, 75298.0", \ + "75480.9, 75480.9, 75480.9, 75480.9, 75480.9", \ + "75846.6, 75846.6, 75846.6, 75846.6, 75846.6"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("70605.1, 70605.1, 70605.1, 72500.9, 76292.6", \ + "76381.0, 76381.0, 76381.0, 76381.0, 76381.0", \ + "76557.8, 76557.8, 76557.8, 76557.8, 76557.8", \ + "76911.4, 76911.4, 76911.4, 76911.4, 76911.4", \ + "77618.5, 77618.5, 77618.5, 77618.5, 77618.5"); + } + } + internal_power (energy_pos_nq_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("59745.4, 59745.4, 59745.4, 61641.2, 65432.9", \ + "59808.5, 59808.5, 59808.5, 61704.3, 65496.0", \ + "59912.5, 59912.5, 59912.5, 61808.3, 65600.0", \ + "60115.9, 60115.9, 60115.9, 62011.7, 65803.4", \ + "66206.6, 66206.6, 66206.6, 66206.6, 66206.6"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("65200.9, 65200.9, 65200.9, 67096.7, 70888.4", \ + "70951.6, 70951.6, 70951.6, 70951.6, 70951.6", \ + "71077.9, 71077.9, 71077.9, 71077.9, 71077.9", \ + "71330.5, 71330.5, 71330.5, 71330.5, 71330.5", \ + "71835.6, 71835.6, 71835.6, 71835.6, 71835.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("60956.2, 60956.2, 60956.2, 62852.0, 66643.7", \ + "66687.8, 66687.8, 66687.8, 66687.8, 66687.8", \ + "66776.0, 66776.0, 66776.0, 66776.0, 66776.0", \ + "66952.3, 66952.3, 66952.3, 66952.3, 66952.3", \ + "61619.0, 61619.0, 61619.0, 63514.9, 67306.5"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("58041.1, 58041.1, 58041.1, 59936.9, 63728.6", \ + "63751.5, 63751.5, 63751.5, 63751.5, 63751.5", \ + "63797.3, 63797.3, 63797.3, 63797.3, 63797.3", \ + "63889.0, 63889.0, 63889.0, 63889.0, 63889.0", \ + "58397.2, 58397.2, 58397.2, 60293.1, 64084.8"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("70066.1, 70066.1, 70066.1, 71962.0, 75753.6", \ + "75797.7, 75797.7, 75797.7, 75797.7, 75797.7", \ + "75885.9, 75885.9, 75885.9, 75885.9, 75885.9", \ + "76062.2, 76062.2, 76062.2, 76062.2, 76062.2", \ + "70728.5, 70728.5, 70728.5, 72624.4, 76416.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("64670.8, 64670.8, 64670.8, 66566.6, 70358.3", \ + "70381.2, 70381.2, 70381.2, 70381.2, 70381.2", \ + "70427.0, 70427.0, 70427.0, 70427.0, 70427.0", \ + "70518.7, 70518.7, 70518.7, 70518.7, 70518.7", \ + "65030.3, 65030.3, 65030.3, 66926.2, 70717.8"); + } + } + } + } + + cell (noa3ao322_x1) { + area : 32.40 ; + cell_leakage_power : 7.8 ; + leakage_power () { + when : "(i6 & i5 & i4 & i3 & i2 & i1 & i0)" ; + value : 7.5 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & i4 & i5) ^ i6))" ; + value : 6.9 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & !((i3 & i4 & i5)) & !(i6))" ; + value : 6.4 ; + } + leakage_power () { + when : "(!(i6) & i5 & i4 & i3 & !(i2) & i1 & i0)" ; + value : 11 ; + } + leakage_power () { + when : "(i0 & i1 & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 9.5 ; + } + leakage_power () { + when : "(i6 & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 9.7 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & ((i3 & ((i4 & i5 & i6) | (!(i4) & !(i5) & !(i6)))) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!(i1) & i2 & i3 & i4 & i5 & i6))) | (!(i0) & i1 & i2 & i3 & i4 & i5 & i6))" ; + value : 8.3 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))) | (!(i0) & i1 & i2 & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))))" ; + value : 7.7 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 7.8 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & !(i4) & !(i5) & !(i6))" ; + value : 6.6 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & i6) | (!(i2) & i3 & i4 & i5 & i6))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5) & i6) | (!(i2) & i3 & i4 & i5 & i6))) | (!(i1) & i2 & i3 & i4 & i5 & i6))))" ; + value : 9.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i2) & i3 & i4 & !(i5) & i6))) | (!(i0) & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i2) & i3 & i4 & !(i5) & i6))) | (!(i1) & i2 & i3 & i4 & !(i5) & i6))))" ; + value : 9 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & ((i4 & i5 & !(i6)) | (!(i4) & !(i5) & i6))) | (!(i0) & (i1 ^ i2) & i3 & ((i4 & i5 & !(i6)) | (!(i4) & !(i5) & i6))))" ; + value : 9.1 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i0) & (i1 ^ i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))" ; + value : 7.9 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))) | (!(i0) & (i1 ^ i2) & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))))" ; + value : 8.5 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!(i0) & (i1 ^ i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))" ; + value : 6.7 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & i6))" ; + value : 8.1 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & !(i6)))" ; + value : 5.4 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & !(i5) & i6) | (!(i0) & ((i1 & i2 & i3 & !(i5) & i6) | (!(i1) & !(i2) & i3 & i4 & i5 & !(i6)))))" ; + value : 8 ; + } + leakage_power () { + when : "((i0 & !(i1) & i2 & i3 & i4 & i5 & !(i6)) | (!(i0) & ((i1 & i2 & i3 & i4 & i5 & !(i6)) | (!(i1) & !(i2) & i3 & (i4 | !(i5)) & i6))))" ; + value : 10 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 6.8 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6)))" ; + value : 9.3 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 5.5 ; + } + leakage_power () { + when : "((i0 & i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i0) & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6))" ; + value : 7 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 4.3 ; + } + pin (i6) { + direction : input ; + capacitance : 817.54 ; + } + pin (i5) { + direction : input ; + capacitance : 817.99 ; + } + pin (i4) { + direction : input ; + capacitance : 818.59 ; + } + pin (i3) { + direction : input ; + capacitance : 815.44 ; + } + pin (i2) { + direction : input ; + capacitance : 759.75 ; + } + pin (i1) { + direction : input ; + capacitance : 762.30 ; + } + pin (i0) { + direction : input ; + capacitance : 761.70 ; + } + pin (nq) { + function : "((((((!(i6) & !(i0)) | (!(i6) & !(i1))) | (!(i6) & !(i2))) | (((!(i3) & !(i4)) & !(i5)) & !(i0))) | (((!(i3) & !(i4)) & !(i5)) & !(i1))) | (((!(i3) & !(i4)) & !(i5)) & !(i2)))" ; + direction : output ; + capacitance : 153.07 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("20732.9, 20732.9, 20732.9, 21450.1, 22988.0", \ + "20721.4, 20721.4, 20721.4, 21438.7, 22976.8", \ + "20698.5, 20698.5, 20698.5, 21416.0, 22954.3", \ + "20652.6, 20652.6, 20652.6, 21370.6, 22909.2", \ + "20560.7, 20560.7, 20560.7, 21279.8, 22819.1"); + } + rise_transition (inslew_load_5x5__12) { + values ("34177.1, 34177.1, 34177.1, 35707.7, 38768.9", \ + "34177.1, 34177.1, 34177.1, 35707.7, 38768.9", \ + "34177.1, 34177.1, 34177.1, 35707.7, 38768.9", \ + "34177.1, 34177.1, 34177.1, 35707.7, 38768.9", \ + "34177.1, 34177.1, 34177.1, 35707.7, 38768.9"); + } + cell_fall (inslew_load_5x5__12) { + values ("5583.6, 5583.6, 5583.6, 5865.5, 6451.2", \ + "5572.5, 5572.5, 5572.5, 5854.4, 6440.1", \ + "5550.3, 5550.3, 5550.3, 5832.2, 6417.9", \ + "5505.8, 5505.8, 5505.8, 5787.8, 6373.5", \ + "5416.8, 5416.8, 5416.8, 5699.0, 6284.8"); + } + fall_transition (inslew_load_5x5__12) { + values ("7937.9, 7937.9, 7937.9, 8456.9, 9495.0", \ + "7937.9, 7937.9, 7937.9, 8456.9, 9495.0", \ + "7937.9, 7937.9, 7937.9, 8456.9, 9495.0", \ + "7937.9, 7937.9, 7937.9, 8456.9, 9495.0", \ + "7938.1, 7938.1, 7938.1, 8457.1, 9495.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("19512.2, 19512.2, 19512.2, 20237.5, 21783.5", \ + "19500.7, 19500.7, 19500.7, 20226.1, 21772.2", \ + "19477.8, 19477.8, 19477.8, 20203.5, 21749.7", \ + "19432.0, 19432.0, 19432.0, 20158.1, 21704.7", \ + "19340.3, 19340.3, 19340.3, 20067.4, 21614.6"); + } + rise_transition (inslew_load_5x5__12) { + values ("31956.4, 31956.4, 31956.4, 33487.0, 36548.2", \ + "31956.4, 31956.4, 31956.4, 33487.0, 36548.2", \ + "31956.4, 31956.4, 31956.4, 33487.0, 36548.2", \ + "31956.4, 31956.4, 31956.4, 33487.0, 36548.2", \ + "31956.4, 31956.4, 31956.4, 33487.0, 36548.2"); + } + cell_fall (inslew_load_5x5__12) { + values ("4532.7, 4532.7, 4532.7, 4823.1, 5418.8", \ + "4528.2, 4528.2, 4528.2, 4818.6, 5414.4", \ + "4519.0, 4519.0, 4519.0, 4809.4, 5405.3", \ + "4502.5, 4502.5, 4502.5, 4793.0, 5388.9", \ + "4470.2, 4470.2, 4470.2, 4760.8, 5356.9"); + } + fall_transition (inslew_load_5x5__12) { + values ("6238.5, 6238.5, 6238.5, 6764.8, 7817.5", \ + "6241.4, 6241.4, 6241.4, 6767.8, 7820.6", \ + "6242.1, 6242.1, 6242.1, 6768.5, 7821.4", \ + "6242.1, 6242.1, 6242.1, 6768.6, 7821.4", \ + "6242.7, 6242.7, 6242.7, 6768.9, 7821.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("17791.5, 17791.5, 17791.5, 18528.3, 20085.6", \ + "17780.1, 17780.1, 17780.1, 18517.0, 20074.4", \ + "17757.2, 17757.2, 17757.2, 18494.4, 20051.9", \ + "17711.5, 17711.5, 17711.5, 18449.1, 20006.9", \ + "17620.1, 17620.1, 17620.1, 18358.5, 19916.9"); + } + rise_transition (inslew_load_5x5__12) { + values ("28826.3, 28826.3, 28826.3, 30356.9, 33418.1", \ + "28826.3, 28826.3, 28826.3, 30356.9, 33418.1", \ + "28826.3, 28826.3, 28826.3, 30356.9, 33418.1", \ + "28826.3, 28826.3, 28826.3, 30356.9, 33418.1", \ + "28826.3, 28826.3, 28826.3, 30356.9, 33418.1"); + } + cell_fall (inslew_load_5x5__12) { + values ("3519.7, 3519.7, 3519.7, 3818.2, 4424.1", \ + "3524.4, 3524.4, 3524.4, 3822.9, 4428.7", \ + "3533.2, 3533.2, 3533.2, 3831.8, 4437.9", \ + "3540.2, 3540.2, 3540.2, 3838.5, 4444.1", \ + "3562.6, 3562.6, 3562.6, 3861.3, 4467.3"); + } + fall_transition (inslew_load_5x5__12) { + values ("4581.2, 4581.2, 4581.2, 5116.4, 6187.2", \ + "4597.8, 4597.8, 4597.8, 5132.8, 6203.4", \ + "4620.7, 4620.7, 4620.7, 5156.0, 6227.0", \ + "4627.9, 4627.9, 4627.9, 5162.7, 6232.9", \ + "4634.7, 4634.7, 4634.7, 5168.9, 6238.6"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("4520.0, 4520.0, 4520.0, 5358.6, 7030.6", \ + "4579.1, 4579.1, 4579.1, 5415.4, 7084.5", \ + "4559.4, 4559.4, 4559.4, 5392.3, 7056.8", \ + "4688.2, 4688.2, 4688.2, 5515.8, 7173.5", \ + "4772.6, 4772.6, 4772.6, 5593.1, 7242.5"); + } + rise_transition (inslew_load_5x5__12) { + values ("4726.1, 4726.1, 4726.1, 6326.9, 9522.1", \ + "4860.2, 4860.2, 4860.2, 6456.8, 9646.4", \ + "4862.6, 4862.6, 4862.6, 6452.5, 9633.2", \ + "5180.3, 5180.3, 5180.3, 6760.0, 9927.6", \ + "5454.9, 5454.9, 5454.9, 7020.6, 10172.2"); + } + cell_fall (inslew_load_5x5__12) { + values ("2628.1, 2628.1, 2628.1, 2933.3, 3544.7", \ + "2622.9, 2622.9, 2622.9, 2928.1, 3539.6", \ + "2612.6, 2612.6, 2612.6, 2917.8, 3529.3", \ + "2591.9, 2591.9, 2591.9, 2897.2, 3508.6", \ + "2547.6, 2547.6, 2547.6, 2854.4, 3467.0"); + } + fall_transition (inslew_load_5x5__12) { + values ("2442.8, 2442.8, 2442.8, 2919.8, 3873.8", \ + "2442.8, 2442.8, 2442.8, 2919.8, 3873.8", \ + "2442.8, 2442.8, 2442.8, 2919.8, 3873.8", \ + "2442.9, 2442.9, 2442.9, 2919.9, 3873.8", \ + "2451.9, 2451.9, 2451.9, 2926.3, 3876.8"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("9241.9, 9241.9, 9241.9, 10037.7, 11658.1", \ + "9216.2, 9216.2, 9216.2, 10011.6, 11631.3", \ + "9234.4, 9234.4, 9234.4, 10030.1, 11650.4", \ + "9248.3, 9248.3, 9248.3, 10044.8, 11666.1", \ + "9224.4, 9224.4, 9224.4, 10021.6, 11643.7"); + } + rise_transition (inslew_load_5x5__12) { + values ("13422.1, 13422.1, 13422.1, 14978.3, 18094.3", \ + "13397.5, 13397.5, 13397.5, 14952.8, 18067.5", \ + "13477.3, 13477.3, 13477.3, 15033.3, 18149.0", \ + "13586.0, 13586.0, 13586.0, 15143.1, 18260.3", \ + "13675.9, 13675.9, 13675.9, 15233.7, 18351.9"); + } + cell_fall (inslew_load_5x5__12) { + values ("3523.8, 3523.8, 3523.8, 3823.4, 4428.8", \ + "3518.6, 3518.6, 3518.6, 3818.2, 4423.7", \ + "3508.3, 3508.3, 3508.3, 3807.9, 4413.4", \ + "3487.6, 3487.6, 3487.6, 3787.3, 4392.7", \ + "3445.9, 3445.9, 3445.9, 3745.8, 4351.4"); + } + fall_transition (inslew_load_5x5__12) { + values ("3798.9, 3798.9, 3798.9, 4275.9, 5229.9", \ + "3798.9, 3798.9, 3798.9, 4275.9, 5229.9", \ + "3798.9, 3798.9, 3798.9, 4275.9, 5229.9", \ + "3798.9, 3798.9, 3798.9, 4275.9, 5229.9", \ + "3801.9, 3801.9, 3801.9, 4278.0, 5230.8"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("13936.5, 13936.5, 13936.5, 14699.7, 16284.6", \ + "13932.3, 13932.3, 13932.3, 14695.6, 16280.7", \ + "13906.6, 13906.6, 13906.6, 14670.1, 16255.3", \ + "13877.9, 13877.9, 13877.9, 14642.0, 16227.7", \ + "13810.6, 13810.6, 13810.6, 14575.7, 16162.4"); + } + rise_transition (inslew_load_5x5__12) { + values ("21898.6, 21898.6, 21898.6, 23437.3, 26515.3", \ + "21917.6, 21917.6, 21917.6, 23456.5, 26534.7", \ + "21921.3, 21921.3, 21921.3, 23460.1, 26538.3", \ + "21964.2, 21964.2, 21964.2, 23503.4, 26582.2", \ + "22010.5, 22010.5, 22010.5, 23550.2, 26629.9"); + } + cell_fall (inslew_load_5x5__12) { + values ("3947.1, 3947.1, 3947.1, 4244.0, 4846.6", \ + "3941.9, 3941.9, 3941.9, 4238.9, 4841.5", \ + "3931.6, 3931.6, 3931.6, 4228.5, 4831.2", \ + "3910.9, 3910.9, 3910.9, 4207.9, 4810.5", \ + "3869.4, 3869.4, 3869.4, 4166.5, 4769.2"); + } + fall_transition (inslew_load_5x5__12) { + values ("4439.8, 4439.8, 4439.8, 4916.7, 5870.7", \ + "4439.8, 4439.8, 4439.8, 4916.7, 5870.7", \ + "4439.8, 4439.8, 4439.8, 4916.7, 5870.7", \ + "4439.8, 4439.8, 4439.8, 4916.7, 5870.7", \ + "4441.5, 4441.5, 4441.5, 4917.9, 5871.2"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("2350.9, 2350.9, 2350.9, 2886.7, 3949.3", \ + "2348.6, 2348.6, 2348.6, 2883.4, 3944.1", \ + "2369.5, 2369.5, 2369.5, 2904.1, 3965.1", \ + "2385.6, 2385.6, 2385.6, 2918.8, 3978.4", \ + "2397.9, 2397.9, 2397.9, 2937.2, 4004.3"); + } + rise_transition (inslew_load_5x5__12) { + values ("1502.2, 1502.2, 1502.2, 2366.2, 4091.6", \ + "1507.9, 1507.9, 1507.9, 2370.4, 4092.6", \ + "1558.4, 1558.4, 1558.4, 2420.6, 4143.3", \ + "1608.0, 1608.0, 1608.0, 2467.8, 4188.2", \ + "1661.9, 1661.9, 1661.9, 2523.2, 4250.2"); + } + cell_fall (inslew_load_5x5__12) { + values ("1699.4, 1699.4, 1699.4, 2011.8, 2631.3", \ + "1704.0, 1704.0, 1704.0, 2016.5, 2636.3", \ + "1708.8, 1708.8, 1708.8, 2021.5, 2642.0", \ + "1726.1, 1726.1, 1726.1, 2038.4, 2657.4", \ + "1737.5, 1737.5, 1737.5, 2060.0, 2686.8"); + } + fall_transition (inslew_load_5x5__12) { + values ("1038.8, 1038.8, 1038.8, 1523.2, 2490.8", \ + "1047.4, 1047.4, 1047.4, 1532.0, 2500.1", \ + "1051.5, 1051.5, 1051.5, 1536.4, 2505.6", \ + "1060.7, 1060.7, 1060.7, 1544.3, 2510.8", \ + "1072.9, 1072.9, 1072.9, 1556.1, 2517.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__12) { + values ("40560.5, 40560.5, 40560.5, 42473.9, 46300.7", \ + "40660.4, 40660.4, 40660.4, 42573.8, 46400.6", \ + "40860.1, 40860.1, 40860.1, 42773.5, 46600.3", \ + "41259.6, 41259.6, 41259.6, 43173.0, 46999.8", \ + "42058.5, 42058.5, 42058.5, 43971.9, 47798.7"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("27024.4, 27024.4, 27024.4, 28937.8, 32764.6", \ + "27052.5, 27052.5, 27052.5, 28965.9, 32792.7", \ + "27108.7, 27108.7, 27108.7, 29022.1, 32848.9", \ + "27221.1, 27221.1, 27221.1, 29134.5, 32961.3", \ + "27445.8, 27445.8, 27445.8, 29359.2, 33186.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__12) { + values ("37760.4, 37760.4, 37760.4, 39673.8, 43500.6", \ + "37836.2, 37836.2, 37836.2, 39749.6, 43576.4", \ + "37987.9, 37987.9, 37987.9, 39901.3, 43728.1", \ + "38291.2, 38291.2, 38291.2, 40204.6, 44031.4", \ + "38897.9, 38897.9, 38897.9, 40811.3, 44638.1"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("20485.5, 20485.5, 20485.5, 22398.9, 26225.7", \ + "20518.1, 20518.1, 20518.1, 22431.5, 26258.3", \ + "20583.1, 20583.1, 20583.1, 22496.5, 26323.3", \ + "20713.2, 20713.2, 20713.2, 22626.6, 26453.4", \ + "20973.5, 20973.5, 20973.5, 22886.9, 26713.7"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__12) { + values ("33831.7, 33831.7, 33831.7, 35745.1, 39571.9", \ + "33891.8, 33891.8, 33891.8, 35805.2, 39632.0", \ + "34011.9, 34011.9, 34011.9, 35925.3, 39752.1", \ + "34252.2, 34252.2, 34252.2, 36165.6, 39992.4", \ + "34732.7, 34732.7, 34732.7, 36646.1, 40472.9"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("14371.3, 14371.3, 14371.3, 16284.7, 20111.5", \ + "14406.7, 14406.7, 14406.7, 16320.1, 20146.9", \ + "14477.7, 14477.7, 14477.7, 16391.1, 20217.9", \ + "14619.6, 14619.6, 14619.6, 16533.0, 20359.8", \ + "14903.4, 14903.4, 14903.4, 16816.8, 20643.6"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__12) { + values ("5075.3, 5075.3, 5075.3, 6988.7, 10815.5", \ + "5145.5, 5145.5, 5145.5, 7058.9, 10885.7", \ + "5285.9, 5285.9, 5285.9, 7199.3, 11026.1", \ + "5566.6, 5566.6, 5566.6, 7480.0, 11306.8", \ + "6128.2, 6128.2, 6128.2, 8041.6, 11868.4"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("7602.1, 7602.1, 7602.1, 9515.5, 13342.3", \ + "7616.0, 7616.0, 7616.0, 9529.4, 13356.2", \ + "7644.0, 7644.0, 7644.0, 9557.4, 13384.2", \ + "7699.9, 7699.9, 7699.9, 9613.3, 13440.1", \ + "7811.7, 7811.7, 7811.7, 9725.1, 13551.9"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__12) { + values ("14768.7, 14768.7, 14768.7, 16682.1, 20508.9", \ + "14842.4, 14842.4, 14842.4, 16755.7, 20582.5", \ + "14989.7, 14989.7, 14989.7, 16903.1, 20729.9", \ + "15284.5, 15284.5, 15284.5, 17197.9, 21024.7", \ + "15874.1, 15874.1, 15874.1, 17787.5, 21614.3"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("13046.6, 13046.6, 13046.6, 14960.0, 18786.8", \ + "13065.3, 13065.3, 13065.3, 14978.7, 18805.5", \ + "13102.8, 13102.8, 13102.8, 15016.2, 18843.0", \ + "13177.7, 13177.7, 13177.7, 15091.1, 18917.9", \ + "13327.4, 13327.4, 13327.4, 15240.8, 19067.6"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__12) { + values ("25222.8, 25222.8, 25222.8, 27136.2, 30963.0", \ + "25299.9, 25299.9, 25299.9, 27213.3, 31040.1", \ + "25454.2, 25454.2, 25454.2, 27367.6, 31194.4", \ + "25762.7, 25762.7, 25762.7, 27676.1, 31502.9", \ + "26379.7, 26379.7, 26379.7, 28293.1, 32119.9"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("15625.0, 15625.0, 15625.0, 17538.4, 21365.2", \ + "15651.3, 15651.3, 15651.3, 17564.7, 21391.5", \ + "15704.1, 15704.1, 15704.1, 17617.4, 21444.2", \ + "15809.5, 15809.5, 15809.5, 17722.9, 21549.7", \ + "16020.3, 16020.3, 16020.3, 17933.7, 21760.5"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__12) { + values ("1923.2, 1923.2, 1923.2, 3836.6, 7663.4", \ + "1980.7, 1980.7, 1980.7, 3894.1, 7720.9", \ + "2095.7, 2095.7, 2095.7, 4009.1, 7835.9", \ + "2325.6, 2325.6, 2325.6, 4239.0, 8065.8", \ + "2785.4, 2785.4, 2785.4, 4698.8, 8525.6"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("1991.1, 1991.1, 1991.1, 3904.5, 7731.3", \ + "2021.2, 2021.2, 2021.2, 3934.6, 7761.4", \ + "2081.3, 2081.3, 2081.3, 3994.7, 7821.5", \ + "2201.5, 2201.5, 2201.5, 4114.9, 7941.7", \ + "2442.0, 2442.0, 2442.0, 4355.4, 8182.2"); + } + } + } + } + + cell (one_x0) { + area : 10.80 ; + cell_leakage_power : 0 ; + pin (q) { + function : "1" ; + direction : output ; + capacitance : 41.18 ; + } + } + + cell (na3_x4) { + area : 28.80 ; + cell_leakage_power : 8 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 7.2 ; + } + leakage_power () { + when : "(i0 & (i1 ^ i2))" ; + value : 8.8 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0))" ; + value : 9.1 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2)) | (!(i0) & (i1 ^ i2)))" ; + value : 7.8 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 6.9 ; + } + pin (i2) { + direction : input ; + capacitance : 569.23 ; + } + pin (i1) { + direction : input ; + capacitance : 567.23 ; + } + pin (i0) { + direction : input ; + capacitance : 568.33 ; + } + pin (nq) { + function : "(!(i1) | !(i2) | !(i0))" ; + direction : output ; + capacitance : 148.45 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("10182.6, 10182.6, 10182.6, 10461.3, 10969.3", \ + "10191.4, 10191.4, 10191.4, 10470.1, 10978.1", \ + "10209.0, 10209.0, 10209.0, 10487.7, 10995.7", \ + "10244.2, 10244.2, 10244.2, 10522.9, 11030.9", \ + "10315.1, 10315.1, 10315.1, 10593.8, 11101.7"); + } + rise_transition (inslew_load_5x5__13) { + values ("2314.2, 2314.2, 2314.2, 2550.8, 2984.7", \ + "2314.2, 2314.2, 2314.2, 2550.8, 2984.7", \ + "2314.2, 2314.2, 2314.2, 2550.8, 2984.7", \ + "2314.2, 2314.2, 2314.2, 2550.8, 2984.7", \ + "2314.8, 2314.8, 2314.8, 2551.4, 2985.2"); + } + cell_fall (inslew_load_5x5__13) { + values ("10311.4, 10311.4, 10311.4, 10518.3, 10943.5", \ + "10327.1, 10327.1, 10327.1, 10534.0, 10959.0", \ + "10339.2, 10339.2, 10339.2, 10546.0, 10970.8", \ + "10348.9, 10348.9, 10348.9, 10555.7, 10980.4", \ + "10369.3, 10369.3, 10369.3, 10576.1, 11000.7"); + } + fall_transition (inslew_load_5x5__13) { + values ("2949.9, 2949.9, 2949.9, 3109.4, 3427.0", \ + "2950.8, 2950.8, 2950.8, 3110.2, 3427.8", \ + "2951.5, 2951.5, 2951.5, 3110.9, 3428.5", \ + "2951.8, 2951.8, 2951.8, 3111.2, 3428.8", \ + "2952.3, 2952.3, 2952.3, 3111.7, 3429.3"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("12915.1, 12915.1, 12915.1, 13174.7, 13656.6", \ + "12923.9, 12923.9, 12923.9, 13183.5, 13665.4", \ + "12941.5, 12941.5, 12941.5, 13201.1, 13683.0", \ + "12976.6, 12976.6, 12976.6, 13236.2, 13718.1", \ + "13046.9, 13046.9, 13046.9, 13306.5, 13788.4"); + } + rise_transition (inslew_load_5x5__13) { + values ("3032.0, 3032.0, 3032.0, 3247.3, 3660.1", \ + "3032.0, 3032.0, 3032.0, 3247.3, 3660.1", \ + "3032.0, 3032.0, 3032.0, 3247.3, 3660.1", \ + "3032.0, 3032.0, 3032.0, 3247.3, 3660.1", \ + "3032.0, 3032.0, 3032.0, 3247.3, 3660.1"); + } + cell_fall (inslew_load_5x5__13) { + values ("13764.8, 13764.8, 13764.8, 13874.5, 14276.6", \ + "13753.7, 13753.7, 13753.7, 13863.4, 14265.5", \ + "13731.5, 13731.5, 13731.5, 13841.2, 14243.3", \ + "13687.2, 13687.2, 13687.2, 13796.9, 14199.0", \ + "13599.0, 13599.0, 13599.0, 13708.7, 14110.8"); + } + fall_transition (inslew_load_5x5__13) { + values ("3629.9, 3629.9, 3629.9, 3656.2, 3958.5", \ + "3629.9, 3629.9, 3629.9, 3656.2, 3958.5", \ + "3629.9, 3629.9, 3629.9, 3656.2, 3958.5", \ + "3629.9, 3629.9, 3629.9, 3656.2, 3958.5", \ + "3630.2, 3630.2, 3630.2, 3656.5, 3958.8"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("11754.1, 11754.1, 11754.1, 12016.3, 12513.8", \ + "11762.9, 11762.9, 11762.9, 12025.1, 12522.6", \ + "11780.5, 11780.5, 11780.5, 12042.7, 12540.2", \ + "11815.6, 11815.6, 11815.6, 12077.8, 12575.3", \ + "11886.1, 11886.1, 11886.1, 12148.3, 12645.8"); + } + rise_transition (inslew_load_5x5__13) { + values ("2728.0, 2728.0, 2728.0, 2948.8, 3371.2", \ + "2728.0, 2728.0, 2728.0, 2948.8, 3371.2", \ + "2728.0, 2728.0, 2728.0, 2948.8, 3371.2", \ + "2728.0, 2728.0, 2728.0, 2948.8, 3371.2", \ + "2728.1, 2728.1, 2728.1, 2948.9, 3371.4"); + } + cell_fall (inslew_load_5x5__13) { + values ("11810.2, 11810.2, 11810.2, 12016.9, 12421.1", \ + "11807.0, 11807.0, 11807.0, 12013.7, 12417.8", \ + "11798.2, 11798.2, 11798.2, 12004.9, 12409.1", \ + "11781.7, 11781.7, 11781.7, 11988.4, 12392.6", \ + "11751.5, 11751.5, 11751.5, 11958.2, 12362.4"); + } + fall_transition (inslew_load_5x5__13) { + values ("3133.9, 3133.9, 3133.9, 3285.7, 3602.5", \ + "3134.6, 3134.6, 3134.6, 3286.3, 3603.1", \ + "3134.7, 3134.7, 3134.7, 3286.4, 3603.2", \ + "3134.7, 3134.7, 3134.7, 3286.4, 3603.2", \ + "3135.8, 3135.8, 3135.8, 3287.4, 3604.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__13) { + values ("50231.6, 50231.6, 50231.6, 52087.1, 55798.3", \ + "55847.9, 55847.9, 55847.9, 55847.9, 55847.9", \ + "55947.0, 55947.0, 55947.0, 55947.0, 55947.0", \ + "56145.2, 56145.2, 56145.2, 56145.2, 56145.2", \ + "50978.2, 50978.2, 50978.2, 52833.8, 56545.0"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("50519.1, 50519.1, 50519.1, 52374.7, 56085.9", \ + "50569.7, 50569.7, 50569.7, 52425.3, 56136.5", \ + "50637.0, 50637.0, 50637.0, 52492.6, 56203.8", \ + "50734.9, 50734.9, 50734.9, 52590.4, 56301.6", \ + "50926.6, 50926.6, 50926.6, 52782.2, 56493.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__13) { + values ("61012.5, 61012.5, 61012.5, 62868.0, 66579.2", \ + "66658.0, 66658.0, 66658.0, 66658.0, 66658.0", \ + "66815.7, 66815.7, 66815.7, 66815.7, 66815.7", \ + "67130.9, 67130.9, 67130.9, 67130.9, 67130.9", \ + "67761.4, 67761.4, 67761.4, 67761.4, 67761.4"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("67324.2, 67324.2, 67324.2, 69179.7, 72890.9", \ + "72907.5, 72907.5, 72907.5, 72907.5, 72907.5", \ + "72940.7, 72940.7, 72940.7, 72940.7, 72940.7", \ + "73007.1, 73007.1, 73007.1, 73007.1, 73007.1", \ + "67576.2, 67576.2, 67576.2, 69431.8, 73142.9"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__13) { + values ("56255.8, 56255.8, 56255.8, 58111.4, 61822.6", \ + "61884.1, 61884.1, 61884.1, 61884.1, 61884.1", \ + "62007.1, 62007.1, 62007.1, 62007.1, 62007.1", \ + "62253.1, 62253.1, 62253.1, 62253.1, 62253.1", \ + "57179.4, 57179.4, 57179.4, 59034.9, 62746.1"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("58164.1, 58164.1, 58164.1, 60019.7, 63730.9", \ + "58189.7, 58189.7, 58189.7, 60045.3, 63756.5", \ + "58230.4, 58230.4, 58230.4, 60086.0, 63797.2", \ + "63875.4, 63875.4, 63875.4, 63875.4, 63875.4", \ + "58474.8, 58474.8, 58474.8, 60330.4, 64041.6"); + } + } + } + } + + cell (nao2o22_x4) { + area : 39.60 ; + cell_leakage_power : 8.7 ; + leakage_power () { + when : "(!(i3) & i2 & !(i1) & i0)" ; + value : 6.1 ; + } + leakage_power () { + when : "((i0 & ((i1 & i2 & !(i3)) | (!(i1) & i3))) | (i1 & i2 & !(i3)))" ; + value : 6.3 ; + } + leakage_power () { + when : "(i1 & i3)" ; + value : 6.4 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & !(i3))" ; + value : 10 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 12 ; + } + leakage_power () { + when : "((i0 & i1 & !(i2) & !(i3)) | (!(i0) & !(i1) & (i2 ^ i3)))" ; + value : 11 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 9.2 ; + } + pin (i3) { + direction : input ; + capacitance : 434.46 ; + } + pin (i2) { + direction : input ; + capacitance : 432.96 ; + } + pin (i1) { + direction : input ; + capacitance : 434.46 ; + } + pin (i0) { + direction : input ; + capacitance : 432.96 ; + } + pin (nq) { + function : "(!((i0 | i1)) | (!(i2) & !(i3)))" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("15950.7, 15950.7, 15950.7, 16207.4, 16692.8", \ + "15945.4, 15945.4, 15945.4, 16202.1, 16687.5", \ + "15934.6, 15934.6, 15934.6, 16191.3, 16676.7", \ + "15913.2, 15913.2, 15913.2, 16169.9, 16655.3", \ + "15870.2, 15870.2, 15870.2, 16126.9, 16612.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("4103.1, 4103.1, 4103.1, 4307.2, 4706.1", \ + "4103.1, 4103.1, 4103.1, 4307.2, 4706.1", \ + "4103.1, 4103.1, 4103.1, 4307.2, 4706.1", \ + "4103.1, 4103.1, 4103.1, 4307.2, 4706.1", \ + "4103.1, 4103.1, 4103.1, 4307.2, 4706.1"); + } + cell_fall (inslew_load_5x5__3) { + values ("12480.2, 12480.2, 12480.2, 12691.2, 13103.8", \ + "12493.0, 12493.0, 12493.0, 12704.0, 13116.7", \ + "12505.3, 12505.3, 12505.3, 12716.3, 13128.9", \ + "12519.8, 12519.8, 12519.8, 12730.8, 13143.5", \ + "12553.7, 12553.7, 12553.7, 12764.7, 13177.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("3174.1, 3174.1, 3174.1, 3328.0, 3649.8", \ + "3177.0, 3177.0, 3177.0, 3330.8, 3652.4", \ + "3179.2, 3179.2, 3179.2, 3332.9, 3654.4", \ + "3180.0, 3180.0, 3180.0, 3333.6, 3655.2", \ + "3180.8, 3180.8, 3180.8, 3334.4, 3655.9"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("12300.2, 12300.2, 12300.2, 12564.8, 13055.7", \ + "12306.4, 12306.4, 12306.4, 12571.0, 13061.8", \ + "12320.5, 12320.5, 12320.5, 12585.1, 13075.7", \ + "12334.9, 12334.9, 12334.9, 12599.5, 13090.0", \ + "12365.9, 12365.9, 12365.9, 12630.5, 13120.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("3051.5, 3051.5, 3051.5, 3271.0, 3691.8", \ + "3054.0, 3054.0, 3054.0, 3273.4, 3694.2", \ + "3058.5, 3058.5, 3058.5, 3277.8, 3698.5", \ + "3060.8, 3060.8, 3060.8, 3280.1, 3700.7", \ + "3062.0, 3062.0, 3062.0, 3281.3, 3701.8"); + } + cell_fall (inslew_load_5x5__3) { + values ("11230.7, 11230.7, 11230.7, 11441.8, 11873.7", \ + "11238.7, 11238.7, 11238.7, 11449.8, 11881.5", \ + "11247.0, 11247.0, 11247.0, 11458.1, 11889.7", \ + "11260.4, 11260.4, 11260.4, 11471.5, 11903.1", \ + "11293.3, 11293.3, 11293.3, 11504.4, 11935.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("2974.6, 2974.6, 2974.6, 3136.9, 3459.6", \ + "2975.1, 2975.1, 2975.1, 3137.4, 3460.1", \ + "2975.5, 2975.5, 2975.5, 3137.8, 3460.5", \ + "2975.7, 2975.7, 2975.7, 3138.0, 3460.6", \ + "2976.0, 2976.0, 2976.0, 3138.3, 3460.9"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("17505.7, 17505.7, 17505.7, 17760.3, 18243.9", \ + "17500.4, 17500.4, 17500.4, 17755.0, 18238.6", \ + "17489.6, 17489.6, 17489.6, 17744.2, 18227.8", \ + "17468.1, 17468.1, 17468.1, 17722.7, 18206.3", \ + "17425.2, 17425.2, 17425.2, 17679.8, 18163.4"); + } + rise_transition (inslew_load_5x5__3) { + values ("4550.7, 4550.7, 4550.7, 4750.2, 5144.0", \ + "4550.7, 4550.7, 4550.7, 4750.2, 5144.0", \ + "4550.7, 4550.7, 4550.7, 4750.2, 5144.0", \ + "4550.7, 4550.7, 4550.7, 4750.2, 5144.0", \ + "4550.7, 4550.7, 4550.7, 4750.2, 5144.0"); + } + cell_fall (inslew_load_5x5__3) { + values ("14174.4, 14174.4, 14174.4, 14288.0, 14698.1", \ + "14169.2, 14169.2, 14169.2, 14282.8, 14692.9", \ + "14158.9, 14158.9, 14158.9, 14272.5, 14682.6", \ + "14138.3, 14138.3, 14138.3, 14251.9, 14662.0", \ + "14097.3, 14097.3, 14097.3, 14210.8, 14621.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("3596.7, 3596.7, 3596.7, 3628.2, 3938.6", \ + "3596.7, 3596.7, 3596.7, 3628.2, 3938.6", \ + "3596.7, 3596.7, 3596.7, 3628.2, 3938.6", \ + "3596.7, 3596.7, 3596.7, 3628.2, 3938.6", \ + "3596.8, 3596.8, 3596.8, 3628.3, 3938.8"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("14075.3, 14075.3, 14075.3, 14335.8, 14822.3", \ + "14080.6, 14080.6, 14080.6, 14341.1, 14827.5", \ + "14094.0, 14094.0, 14094.0, 14354.4, 14840.9", \ + "14108.3, 14108.3, 14108.3, 14368.7, 14855.1", \ + "14138.0, 14138.0, 14138.0, 14398.5, 14884.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("3574.3, 3574.3, 3574.3, 3785.6, 4192.2", \ + "3576.5, 3576.5, 3576.5, 3787.7, 4194.3", \ + "3580.6, 3580.6, 3580.6, 3791.8, 4198.3", \ + "3582.9, 3582.9, 3582.9, 3794.1, 4200.5", \ + "3583.6, 3583.6, 3583.6, 3794.8, 4201.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("12740.8, 12740.8, 12740.8, 12951.8, 13364.4", \ + "12735.6, 12735.6, 12735.6, 12946.6, 13359.2", \ + "12725.3, 12725.3, 12725.3, 12936.3, 13348.9", \ + "12704.7, 12704.7, 12704.7, 12915.7, 13328.3", \ + "12664.1, 12664.1, 12664.1, 12875.1, 13287.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("3220.6, 3220.6, 3220.6, 3372.7, 3693.3", \ + "3220.6, 3220.6, 3220.6, 3372.7, 3693.3", \ + "3220.6, 3220.6, 3220.6, 3372.7, 3693.3", \ + "3220.6, 3220.6, 3220.6, 3372.7, 3693.3", \ + "3221.0, 3221.0, 3221.0, 3373.1, 3693.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("67784.4, 67784.4, 67784.4, 69680.3, 73472.0", \ + "73503.5, 73503.5, 73503.5, 73503.5, 73503.5", \ + "73566.6, 73566.6, 73566.6, 73566.6, 73566.6", \ + "73692.9, 73692.9, 73692.9, 73692.9, 73692.9", \ + "73945.3, 73945.3, 73945.3, 73945.3, 73945.3"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("55786.0, 55786.0, 55786.0, 57681.8, 61473.5", \ + "55837.9, 55837.9, 55837.9, 57733.7, 61525.4", \ + "55909.3, 55909.3, 55909.3, 57805.2, 61596.9", \ + "56017.3, 56017.3, 56017.3, 57913.2, 61704.9", \ + "56226.6, 56226.6, 56226.6, 58122.4, 61914.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("54561.4, 54561.4, 54561.4, 56457.3, 60248.9", \ + "54618.7, 54618.7, 54618.7, 56514.5, 60306.2", \ + "54730.0, 54730.0, 54730.0, 56625.9, 60417.5", \ + "54909.3, 54909.3, 54909.3, 56805.1, 60596.8", \ + "55244.7, 55244.7, 55244.7, 57140.5, 60932.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("50897.2, 50897.2, 50897.2, 52793.1, 56584.7", \ + "50921.6, 50921.6, 50921.6, 52817.4, 56609.1", \ + "50953.9, 50953.9, 50953.9, 52849.8, 56641.5", \ + "51002.2, 51002.2, 51002.2, 52898.1, 56689.7", \ + "51099.4, 51099.4, 51099.4, 52995.2, 56786.9"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("73863.5, 73863.5, 73863.5, 75759.4, 79551.1", \ + "79595.1, 79595.1, 79595.1, 79595.1, 79595.1", \ + "79683.3, 79683.3, 79683.3, 79683.3, 79683.3", \ + "79859.7, 79859.7, 79859.7, 79859.7, 79859.7", \ + "80212.4, 80212.4, 80212.4, 80212.4, 80212.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("62004.2, 62004.2, 62004.2, 63900.0, 67691.7", \ + "67714.6, 67714.6, 67714.6, 67714.6, 67714.6", \ + "67760.4, 67760.4, 67760.4, 67760.4, 67760.4", \ + "67852.0, 67852.0, 67852.0, 67852.0, 67852.0", \ + "62348.9, 62348.9, 62348.9, 64244.7, 68036.4"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__3) { + values ("60839.1, 60839.1, 60839.1, 62735.0, 66526.7", \ + "60897.3, 60897.3, 60897.3, 62793.1, 66584.8", \ + "61011.8, 61011.8, 61011.8, 62907.7, 66699.4", \ + "61198.3, 61198.3, 61198.3, 63094.2, 66885.9", \ + "61544.7, 61544.7, 61544.7, 63440.6, 67232.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("56765.8, 56765.8, 56765.8, 58661.6, 62453.3", \ + "62467.6, 62467.6, 62467.6, 62467.6, 62467.6", \ + "62496.4, 62496.4, 62496.4, 62496.4, 62496.4", \ + "62553.8, 62553.8, 62553.8, 62553.8, 62553.8", \ + "56984.9, 56984.9, 56984.9, 58880.7, 62672.4"); + } + } + } + } + + cell (oa2a2a23_x4) { + area : 46.80 ; + cell_leakage_power : 12 ; + leakage_power () { + when : "(i5 & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 12 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & (i4 ^ i5)))) | (!(i0) & i1 & ((i2 & !(i3) & (i4 ^ i5)) | (!(i2) & i3 & !(i4) & i5))))" ; + value : 11 ; + } + leakage_power () { + when : "((i0 & ((!(i1) & ((i2 & i3 & (i4 ^ i5)) | (!((i2 & i3)) & i4 & i5))) | (i2 & ((i3 & (i4 ^ i5)) | (!(i3) & i4 & i5))) | (!(i2) & i3 & i4 & i5))) | (!(i0) & ((i1 & ((i2 & i3 & (i4 ^ i5)) | (!((i2 & i3)) & i4 & i5))) | (i2 & i3 & (i4 ^ i5)))))" ; + value : 18 ; + } + leakage_power () { + when : "((i0 & i1 & ((!(i2) & (!(i3) | !(i4) | !(i5))) | (!(i3) & (!(i4) | !(i5))) | (!(i4) & !(i5)))) | (i2 & i3 & !(i4) & !(i5)))" ; + value : 17 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i0) & ((i1 & !(i2) & i3 & i4 & !(i5)) | (!(i1) & i2 & !(i3) & !(i4) & i5))))" ; + value : 10 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & (i3 ^ i4) & !(i5)) | (!(i1) & !(i2) & i3 & i4 & !(i5))))" ; + value : 9.5 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & (i3 ^ i4) & !(i5)) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))))))" ; + value : 9.8 ; + } + leakage_power () { + when : "((!((i0 | i1)) & i4 & i5) | (i2 & i3 & i4 & i5))" ; + value : 19 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i1) & !(i2) & (i3 ^ i4) & !(i5))))" ; + value : 8.5 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))))" ; + value : 8.9 ; + } + leakage_power () { + when : "(!(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 7.5 ; + } + pin (i5) { + direction : input ; + capacitance : 845.77 ; + } + pin (i4) { + direction : input ; + capacitance : 848.32 ; + } + pin (i3) { + direction : input ; + capacitance : 845.17 ; + } + pin (i2) { + direction : input ; + capacitance : 844.87 ; + } + pin (i1) { + direction : input ; + capacitance : 844.57 ; + } + pin (i0) { + direction : input ; + capacitance : 843.97 ; + } + pin (q) { + function : "((i4 & ((i2 & ((i1 & i0) | i3 | i5)) | (i1 & i0) | i5)) | (i2 & ((i1 & i0) | i3)) | (i1 & i0))" ; + direction : output ; + capacitance : 151.95 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("10521.4, 10521.4, 10521.4, 10761.8, 11226.6", \ + "10516.2, 10516.2, 10516.2, 10756.6, 11221.4", \ + "10505.9, 10505.9, 10505.9, 10746.3, 11211.1", \ + "10485.3, 10485.3, 10485.3, 10725.7, 11190.5", \ + "10444.0, 10444.0, 10444.0, 10684.4, 11149.2"); + } + rise_transition (inslew_load_5x5__14) { + values ("5415.2, 5415.2, 5415.2, 5611.6, 6003.0", \ + "5415.2, 5415.2, 5415.2, 5611.6, 6003.0", \ + "5415.2, 5415.2, 5415.2, 5611.6, 6003.0", \ + "5415.2, 5415.2, 5415.2, 5611.6, 6003.0", \ + "5415.3, 5415.3, 5415.3, 5611.7, 6003.1"); + } + cell_fall (inslew_load_5x5__14) { + values ("16274.5, 16274.5, 16274.5, 16492.2, 16923.6", \ + "16263.2, 16263.2, 16263.2, 16480.9, 16912.3", \ + "16240.5, 16240.5, 16240.5, 16458.2, 16889.6", \ + "16195.1, 16195.1, 16195.1, 16412.8, 16844.2", \ + "16104.4, 16104.4, 16104.4, 16322.1, 16753.5"); + } + fall_transition (inslew_load_5x5__14) { + values ("9010.6, 9010.6, 9010.6, 9184.5, 9506.5", \ + "9010.6, 9010.6, 9010.6, 9184.5, 9506.5", \ + "9010.6, 9010.6, 9010.6, 9184.5, 9506.5", \ + "9010.6, 9010.6, 9010.6, 9184.5, 9506.5", \ + "9010.6, 9010.6, 9010.6, 9184.5, 9506.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("9378.4, 9378.4, 9378.4, 9627.2, 10109.6", \ + "9383.4, 9383.4, 9383.4, 9632.0, 10114.4", \ + "9390.3, 9390.3, 9390.3, 9639.0, 10121.3", \ + "9407.0, 9407.0, 9407.0, 9655.7, 10138.1", \ + "9440.6, 9440.6, 9440.6, 9689.3, 10171.7"); + } + rise_transition (inslew_load_5x5__14) { + values ("4715.7, 4715.7, 4715.7, 4915.6, 5308.4", \ + "4718.0, 4718.0, 4718.0, 4917.9, 5310.7", \ + "4718.5, 4718.5, 4718.5, 4918.4, 5311.2", \ + "4718.8, 4718.8, 4718.8, 4918.7, 5311.5", \ + "4718.8, 4718.8, 4718.8, 4918.7, 5311.5"); + } + cell_fall (inslew_load_5x5__14) { + values ("15437.2, 15437.2, 15437.2, 15655.5, 16082.6", \ + "15425.9, 15425.9, 15425.9, 15644.2, 16071.3", \ + "15403.2, 15403.2, 15403.2, 15621.5, 16048.6", \ + "15357.8, 15357.8, 15357.8, 15576.1, 16003.2", \ + "15267.1, 15267.1, 15267.1, 15485.4, 15912.5"); + } + fall_transition (inslew_load_5x5__14) { + values ("8498.6, 8498.6, 8498.6, 8671.0, 8994.9", \ + "8498.6, 8498.6, 8498.6, 8671.0, 8994.9", \ + "8498.6, 8498.6, 8498.6, 8671.0, 8994.9", \ + "8498.6, 8498.6, 8498.6, 8671.0, 8994.9", \ + "8498.6, 8498.6, 8498.6, 8671.0, 8994.9"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("9187.5, 9187.5, 9187.5, 9441.8, 9924.7", \ + "9182.4, 9182.4, 9182.4, 9436.7, 9919.6", \ + "9172.1, 9172.1, 9172.1, 9426.4, 9909.3", \ + "9151.4, 9151.4, 9151.4, 9405.7, 9888.6", \ + "9110.2, 9110.2, 9110.2, 9364.5, 9847.5"); + } + rise_transition (inslew_load_5x5__14) { + values ("4553.9, 4553.9, 4553.9, 4753.8, 5148.1", \ + "4553.9, 4553.9, 4553.9, 4753.8, 5148.1", \ + "4553.9, 4553.9, 4553.9, 4753.8, 5148.1", \ + "4553.9, 4553.9, 4553.9, 4753.8, 5148.1", \ + "4554.0, 4554.0, 4554.0, 4753.9, 5148.2"); + } + cell_fall (inslew_load_5x5__14) { + values ("13049.9, 13049.9, 13049.9, 13266.5, 13807.8", \ + "13047.2, 13047.2, 13047.2, 13263.7, 13804.6", \ + "13034.1, 13034.1, 13034.1, 13250.7, 13791.2", \ + "13016.4, 13016.4, 13016.4, 13233.0, 13772.7", \ + "12976.3, 12976.3, 12976.3, 13192.8, 13732.0"); + } + fall_transition (inslew_load_5x5__14) { + values ("7118.1, 7118.1, 7118.1, 7284.6, 7586.7", \ + "7122.4, 7122.4, 7122.4, 7288.9, 7591.2", \ + "7125.2, 7125.2, 7125.2, 7291.8, 7594.2", \ + "7133.3, 7133.3, 7133.3, 7299.7, 7602.6", \ + "7138.4, 7138.4, 7138.4, 7304.8, 7607.9"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("8019.8, 8019.8, 8019.8, 8278.0, 8763.3", \ + "8024.6, 8024.6, 8024.6, 8282.8, 8768.1", \ + "8031.8, 8031.8, 8031.8, 8290.0, 8775.3", \ + "8048.5, 8048.5, 8048.5, 8306.6, 8791.9", \ + "8082.1, 8082.1, 8082.1, 8340.2, 8825.5"); + } + rise_transition (inslew_load_5x5__14) { + values ("3801.6, 3801.6, 3801.6, 4009.8, 4412.1", \ + "3804.0, 3804.0, 3804.0, 4012.3, 4414.5", \ + "3804.5, 3804.5, 3804.5, 4012.8, 4415.0", \ + "3804.9, 3804.9, 3804.9, 4013.1, 4415.3", \ + "3804.9, 3804.9, 3804.9, 4013.1, 4415.3"); + } + cell_fall (inslew_load_5x5__14) { + values ("12198.6, 12198.6, 12198.6, 12478.2, 13113.2", \ + "12196.0, 12196.0, 12196.0, 12474.9, 13110.4", \ + "12182.9, 12182.9, 12182.9, 12461.4, 13097.2", \ + "12165.2, 12165.2, 12165.2, 12442.5, 13079.2", \ + "12124.9, 12124.9, 12124.9, 12401.4, 13038.7"); + } + fall_transition (inslew_load_5x5__14) { + values ("6596.2, 6596.2, 6596.2, 6763.0, 7068.2", \ + "6600.5, 6600.5, 6600.5, 6767.4, 7072.8", \ + "6603.4, 6603.4, 6603.4, 6770.2, 7075.9", \ + "6611.3, 6611.3, 6611.3, 6778.2, 7084.5", \ + "6616.4, 6616.4, 6616.4, 6783.3, 7089.9"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("5813.8, 5813.8, 5813.8, 6097.7, 6614.1", \ + "5818.9, 5818.9, 5818.9, 6102.7, 6619.0", \ + "5826.3, 5826.3, 5826.3, 6110.2, 6626.5", \ + "5843.0, 5843.0, 5843.0, 6126.8, 6643.1", \ + "5876.6, 5876.6, 5876.6, 6160.4, 6676.7"); + } + rise_transition (inslew_load_5x5__14) { + values ("2254.3, 2254.3, 2254.3, 2494.9, 2937.1", \ + "2257.0, 2257.0, 2257.0, 2497.6, 2939.7", \ + "2257.9, 2257.9, 2257.9, 2498.5, 2940.5", \ + "2258.2, 2258.2, 2258.2, 2498.8, 2940.8", \ + "2258.6, 2258.6, 2258.6, 2499.2, 2941.2"); + } + cell_fall (inslew_load_5x5__14) { + values ("9133.2, 9133.2, 9133.2, 9356.3, 9775.3", \ + "9157.6, 9157.6, 9157.6, 9380.9, 9800.2", \ + "9189.8, 9189.8, 9189.8, 9413.3, 9833.0", \ + "9194.7, 9194.7, 9194.7, 9418.4, 9838.3", \ + "9247.8, 9247.8, 9247.8, 9471.9, 9892.5"); + } + fall_transition (inslew_load_5x5__14) { + values ("4557.4, 4557.4, 4557.4, 4667.7, 4919.2", \ + "4580.1, 4580.1, 4580.1, 4690.0, 4940.7", \ + "4612.8, 4612.8, 4612.8, 4722.3, 4971.8", \ + "4633.9, 4633.9, 4633.9, 4743.1, 4991.8", \ + "4695.7, 4695.7, 4695.7, 4803.9, 5050.6"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("7112.1, 7112.1, 7112.1, 7375.3, 7863.2", \ + "7107.0, 7107.0, 7107.0, 7370.2, 7858.1", \ + "7096.7, 7096.7, 7096.7, 7359.9, 7847.8", \ + "7076.0, 7076.0, 7076.0, 7339.2, 7827.1", \ + "7034.9, 7034.9, 7034.9, 7298.1, 7786.0"); + } + rise_transition (inslew_load_5x5__14) { + values ("3148.7, 3148.7, 3148.7, 3365.7, 3782.8", \ + "3148.7, 3148.7, 3148.7, 3365.7, 3782.8", \ + "3148.7, 3148.7, 3148.7, 3365.7, 3782.8", \ + "3148.7, 3148.7, 3148.7, 3365.7, 3782.8", \ + "3148.9, 3148.9, 3148.9, 3365.9, 3783.0"); + } + cell_fall (inslew_load_5x5__14) { + values ("9881.8, 9881.8, 9881.8, 10202.2, 10628.1", \ + "9903.6, 9903.6, 9903.6, 10226.5, 10652.7", \ + "9931.7, 9931.7, 9931.7, 10258.2, 10684.8", \ + "9933.9, 9933.9, 9933.9, 10262.8, 10689.6", \ + "9980.0, 9980.0, 9980.0, 10315.6, 10743.2"); + } + fall_transition (inslew_load_5x5__14) { + values ("5100.1, 5100.1, 5100.1, 5245.2, 5478.0", \ + "5121.0, 5121.0, 5121.0, 5267.6, 5499.8", \ + "5151.3, 5151.3, 5151.3, 5300.0, 5531.2", \ + "5170.6, 5170.6, 5170.6, 5320.7, 5551.4", \ + "5227.8, 5227.8, 5227.8, 5382.0, 5611.0"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__14) { + values ("81027.8, 81027.8, 81027.8, 82927.1, 86725.8", \ + "86771.5, 86771.5, 86771.5, 86771.5, 86771.5", \ + "86862.9, 86862.9, 86862.9, 86862.9, 86862.9", \ + "87045.8, 87045.8, 87045.8, 87045.8, 87045.8", \ + "81713.8, 81713.8, 81713.8, 83613.1, 87411.8"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("107201.7, 107201.7, 107201.7, 109101.0, 112899.7", \ + "112988.0, 112988.0, 112988.0, 112988.0, 112988.0", \ + "107466.6, 107466.6, 107466.6, 109366.0, 113164.7", \ + "113518.2, 113518.2, 113518.2, 113518.2, 113518.2", \ + "114225.4, 114225.4, 114225.4, 114225.4, 114225.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__14) { + values ("71389.6, 71389.6, 71389.6, 73288.9, 77087.6", \ + "71453.0, 71453.0, 71453.0, 73352.4, 77151.0", \ + "71556.7, 71556.7, 71556.7, 73456.0, 77254.7", \ + "71760.1, 71760.1, 71760.1, 73659.4, 77458.1", \ + "77861.3, 77861.3, 77861.3, 77861.3, 77861.3"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("100790.7, 100790.7, 100790.7, 102690.0, 106488.7", \ + "106551.9, 106551.9, 106551.9, 106551.9, 106551.9", \ + "106678.2, 106678.2, 106678.2, 106678.2, 106678.2", \ + "106930.8, 106930.8, 106930.8, 106930.8, 106930.8", \ + "107435.9, 107435.9, 107435.9, 107435.9, 107435.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__14) { + values ("69966.0, 69966.0, 69966.0, 71865.4, 75664.1", \ + "75692.8, 75692.8, 75692.8, 75692.8, 75692.8", \ + "75750.3, 75750.3, 75750.3, 75750.3, 75750.3", \ + "75865.3, 75865.3, 75865.3, 75865.3, 75865.3", \ + "70397.7, 70397.7, 70397.7, 72297.0, 76095.7"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("83131.5, 83131.5, 83131.5, 85030.9, 88829.5", \ + "83244.1, 83244.1, 83244.1, 85143.4, 88942.1", \ + "83432.4, 83432.4, 83432.4, 85331.8, 89130.4", \ + "83823.9, 83823.9, 83823.9, 85723.3, 89522.0", \ + "84538.4, 84538.4, 84538.4, 86437.7, 90236.4"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__14) { + values ("60241.2, 60241.2, 60241.2, 62140.6, 65939.2", \ + "60287.1, 60287.1, 60287.1, 62186.4, 65985.1", \ + "60355.4, 60355.4, 60355.4, 62254.7, 66053.4", \ + "60488.2, 60488.2, 60488.2, 62387.5, 66186.2", \ + "66448.3, 66448.3, 66448.3, 66448.3, 66448.3"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("76677.3, 76677.3, 76677.3, 78576.6, 82375.3", \ + "76768.2, 76768.2, 76768.2, 78667.5, 82466.2", \ + "76913.4, 76913.4, 76913.4, 78812.8, 82611.5", \ + "77218.3, 77218.3, 77218.3, 79117.6, 82916.3", \ + "77760.2, 77760.2, 77760.2, 79659.5, 83458.2"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__14) { + values ("43333.1, 43333.1, 43333.1, 45232.4, 49031.1", \ + "43368.7, 43368.7, 43368.7, 45268.1, 49066.7", \ + "43419.2, 43419.2, 43419.2, 45318.5, 49117.2", \ + "43513.8, 43513.8, 43513.8, 45413.1, 49211.8", \ + "43701.9, 43701.9, 43701.9, 45601.2, 49399.9"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("52368.2, 52368.2, 52368.2, 54267.5, 58066.2", \ + "52559.0, 52559.0, 52559.0, 54458.4, 58257.1", \ + "52869.4, 52869.4, 52869.4, 54768.7, 58567.4", \ + "53237.8, 53237.8, 53237.8, 55137.2, 58935.9", \ + "54086.0, 54086.0, 54086.0, 55985.3, 59784.0"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__14) { + values ("53188.1, 53188.1, 53188.1, 55087.5, 58886.1", \ + "58905.9, 58905.9, 58905.9, 58905.9, 58905.9", \ + "58945.4, 58945.4, 58945.4, 58945.4, 58945.4", \ + "59024.5, 59024.5, 59024.5, 59024.5, 59024.5", \ + "53485.6, 53485.6, 53485.6, 55384.9, 59183.6"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("58879.2, 58879.2, 58879.2, 60778.6, 64577.2", \ + "59088.9, 59088.9, 59088.9, 60988.3, 64787.0", \ + "59436.8, 59436.8, 59436.8, 61336.2, 65134.9", \ + "59880.1, 59880.1, 59880.1, 61779.5, 65578.1", \ + "60880.8, 60880.8, 60880.8, 62780.1, 66578.8"); + } + } + } + } + + cell (nmx3_x4) { + area : 54.00 ; + cell_leakage_power : 9.6 ; + leakage_power () { + when : "(i2 & i1 & i0 & cmd1 & cmd0)" ; + value : 8.2 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0 & cmd1 & cmd0)" ; + value : 8.3 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i0) & i1)" ; + value : 8.1 ; + } + leakage_power () { + when : "((cmd0 ^ cmd1) & i0 & i2)" ; + value : 8.8 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i0) & i2) | (!(cmd0) & cmd1 & i0 & !(i2)))" ; + value : 8.7 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & i1)" ; + value : 9.3 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & !(i1))" ; + value : 9.2 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & i0 & i1 & !(i2)) | (!(cmd0) & !(cmd1) & !(i0) & i1 & i2))" ; + value : 13 ; + } + leakage_power () { + when : "((cmd0 & ((cmd1 & i0 & !(i1) & i2) | (!(cmd1) & (i0 ^ i1) & !(i2)))) | (!(cmd0) & ((cmd1 & !(i0) & i1 & i2) | (!(cmd1) & !(i0) & (i1 ^ i2)))))" ; + value : 12 ; + } + leakage_power () { + when : "((cmd0 & ((cmd1 & ((!(i0) & !(i1)) | (!(i1) & !(i2)))) | (!(i0) & !(i1) & !(i2)))) | (!(cmd0) & ((cmd1 & !(i0) & (!(i1) | !(i2))) | (!(i0) & !(i1) & !(i2)))))" ; + value : 11 ; + } + pin (i2) { + direction : input ; + capacitance : 454.27 ; + } + pin (i1) { + direction : input ; + capacitance : 454.85 ; + } + pin (i0) { + direction : input ; + capacitance : 463.11 ; + } + pin (cmd1) { + direction : input ; + capacitance : 773.53 ; + } + pin (cmd0) { + direction : input ; + capacitance : 768.70 ; + } + pin (nq) { + function : "((!(i2) & ((!(i0) & (!(cmd0) | !(i1) | !(cmd1))) | (cmd0 & (!(i1) | !(cmd1))))) | (!(i0) & (!(cmd0) | (!(i1) & cmd1))) | (cmd0 & !(i1) & cmd1))" ; + direction : output ; + capacitance : 149.01 ; + timing (maxd_nq_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__15) { + values ("26428.9, 26428.9, 26428.9, 26665.6, 27117.9", \ + "26437.7, 26437.7, 26437.7, 26674.4, 27126.7", \ + "26455.3, 26455.3, 26455.3, 26692.0, 27144.3", \ + "26490.3, 26490.3, 26490.3, 26727.0, 27179.3", \ + "26563.7, 26563.7, 26563.7, 26800.4, 27252.7"); + } + rise_transition (inslew_load_5x5__15) { + values ("6780.2, 6780.2, 6780.2, 6968.9, 7343.5", \ + "6780.2, 6780.2, 6780.2, 6968.9, 7343.5", \ + "6780.2, 6780.2, 6780.2, 6968.9, 7343.5", \ + "6780.2, 6780.2, 6780.2, 6968.9, 7343.5", \ + "6780.2, 6780.2, 6780.2, 6968.9, 7343.5"); + } + cell_fall (inslew_load_5x5__15) { + values ("19129.4, 19129.4, 19129.4, 19341.8, 19642.9", \ + "19138.2, 19138.2, 19138.2, 19350.6, 19651.7", \ + "19155.7, 19155.7, 19155.7, 19368.1, 19669.2", \ + "19190.9, 19190.9, 19190.9, 19403.3, 19704.4", \ + "19261.3, 19261.3, 19261.3, 19473.7, 19774.8"); + } + fall_transition (inslew_load_5x5__15) { + values ("3925.6, 3925.6, 3925.6, 4043.4, 4231.2", \ + "3925.6, 3925.6, 3925.6, 4043.4, 4231.2", \ + "3925.6, 3925.6, 3925.6, 4043.4, 4231.2", \ + "3925.6, 3925.6, 3925.6, 4043.4, 4231.2", \ + "3925.7, 3925.7, 3925.7, 4043.4, 4231.3"); + } + } + timing (maxd_nq_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__15) { + values ("17516.5, 17516.5, 17516.5, 17769.5, 18247.6", \ + "17525.3, 17525.3, 17525.3, 17778.3, 18256.4", \ + "17542.9, 17542.9, 17542.9, 17795.9, 18274.0", \ + "17578.0, 17578.0, 17578.0, 17831.0, 18309.1", \ + "17645.8, 17645.8, 17645.8, 17898.9, 18377.0"); + } + rise_transition (inslew_load_5x5__15) { + values ("3986.2, 3986.2, 3986.2, 4188.3, 4581.8", \ + "3986.2, 3986.2, 3986.2, 4188.3, 4581.8", \ + "3986.2, 3986.2, 3986.2, 4188.3, 4581.8", \ + "3986.2, 3986.2, 3986.2, 4188.3, 4581.8", \ + "3987.0, 3987.0, 3987.0, 4189.1, 4582.5"); + } + cell_fall (inslew_load_5x5__15) { + values ("16535.6, 16535.6, 16535.6, 16743.1, 17148.0", \ + "16544.4, 16544.4, 16544.4, 16751.9, 17156.8", \ + "16562.0, 16562.0, 16562.0, 16769.5, 17174.4", \ + "16597.1, 16597.1, 16597.1, 16804.6, 17209.5", \ + "16667.3, 16667.3, 16667.3, 16874.8, 17279.7"); + } + fall_transition (inslew_load_5x5__15) { + values ("3296.4, 3296.4, 3296.4, 3442.6, 3754.1", \ + "3296.4, 3296.4, 3296.4, 3442.6, 3754.1", \ + "3296.4, 3296.4, 3296.4, 3442.6, 3754.1", \ + "3296.4, 3296.4, 3296.4, 3442.6, 3754.1", \ + "3296.4, 3296.4, 3296.4, 3442.6, 3754.1"); + } + } + timing (maxd_nq_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("19934.6, 19934.6, 19934.6, 20170.3, 20635.8", \ + "19929.2, 19929.2, 19929.2, 20164.9, 20630.4", \ + "19918.5, 19918.5, 19918.5, 20154.2, 20619.7", \ + "19897.0, 19897.0, 19897.0, 20132.7, 20598.2", \ + "19854.1, 19854.1, 19854.1, 20089.8, 20555.3"); + } + rise_transition (inslew_load_5x5__15) { + values ("5176.8, 5176.8, 5176.8, 5371.1, 5755.2", \ + "5176.8, 5176.8, 5176.8, 5371.1, 5755.2", \ + "5176.8, 5176.8, 5176.8, 5371.1, 5755.2", \ + "5176.8, 5176.8, 5176.8, 5371.1, 5755.2", \ + "5176.8, 5176.8, 5176.8, 5371.1, 5755.2"); + } + cell_fall (inslew_load_5x5__15) { + values ("17297.7, 17297.7, 17297.7, 17512.3, 17917.0", \ + "17286.6, 17286.6, 17286.6, 17501.2, 17905.9", \ + "17264.4, 17264.4, 17264.4, 17479.0, 17883.7", \ + "17220.1, 17220.1, 17220.1, 17434.7, 17839.4", \ + "17131.5, 17131.5, 17131.5, 17346.1, 17750.8"); + } + fall_transition (inslew_load_5x5__15) { + values ("4320.0, 4320.0, 4320.0, 4428.7, 4681.8", \ + "4320.0, 4320.0, 4320.0, 4428.7, 4681.8", \ + "4320.0, 4320.0, 4320.0, 4428.7, 4681.8", \ + "4320.0, 4320.0, 4320.0, 4428.7, 4681.8", \ + "4320.0, 4320.0, 4320.0, 4428.7, 4681.8"); + } + } + timing (maxd_nq_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("15158.8, 15158.8, 15158.8, 15412.4, 15890.6", \ + "15191.9, 15191.9, 15191.9, 15445.5, 15923.7", \ + "15235.7, 15235.7, 15235.7, 15489.1, 15967.2", \ + "15265.3, 15265.3, 15265.3, 15518.6, 15996.7", \ + "15320.9, 15320.9, 15320.9, 15574.1, 16052.2"); + } + rise_transition (inslew_load_5x5__15) { + values ("3902.4, 3902.4, 3902.4, 4105.7, 4500.0", \ + "3915.3, 3915.3, 3915.3, 4118.4, 4512.6", \ + "3933.4, 3933.4, 3933.4, 4136.2, 4530.2", \ + "3948.9, 3948.9, 3948.9, 4151.5, 4545.3", \ + "3972.0, 3972.0, 3972.0, 4174.4, 4567.9"); + } + cell_fall (inslew_load_5x5__15) { + values ("12322.1, 12322.1, 12322.1, 12529.6, 12935.3", \ + "12336.3, 12336.3, 12336.3, 12543.7, 12949.5", \ + "12362.6, 12362.6, 12362.6, 12570.0, 12975.8", \ + "12377.8, 12377.8, 12377.8, 12585.2, 12991.0", \ + "12403.8, 12403.8, 12403.8, 12611.2, 13017.0"); + } + fall_transition (inslew_load_5x5__15) { + values ("3181.3, 3181.3, 3181.3, 3331.8, 3648.2", \ + "3185.4, 3185.4, 3185.4, 3335.8, 3652.0", \ + "3192.3, 3192.3, 3192.3, 3342.3, 3658.3", \ + "3195.5, 3195.5, 3195.5, 3345.5, 3661.3", \ + "3197.6, 3197.6, 3197.6, 3347.5, 3663.2"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("12958.2, 12958.2, 12958.2, 13217.5, 13698.2", \ + "12964.0, 12964.0, 12964.0, 13223.2, 13703.9", \ + "12977.7, 12977.7, 12977.7, 13236.9, 13717.6", \ + "12992.0, 12992.0, 12992.0, 13251.2, 13731.8", \ + "13022.9, 13022.9, 13022.9, 13282.1, 13762.7"); + } + rise_transition (inslew_load_5x5__15) { + values ("3200.7, 3200.7, 3200.7, 3414.5, 3823.0", \ + "3203.0, 3203.0, 3203.0, 3416.8, 3825.2", \ + "3207.4, 3207.4, 3207.4, 3421.1, 3829.3", \ + "3209.6, 3209.6, 3209.6, 3423.3, 3831.5", \ + "3210.7, 3210.7, 3210.7, 3424.4, 3832.5"); + } + cell_fall (inslew_load_5x5__15) { + values ("10921.7, 10921.7, 10921.7, 11129.3, 11554.1", \ + "10925.4, 10925.4, 10925.4, 11132.9, 11557.8", \ + "10933.0, 10933.0, 10933.0, 11140.5, 11565.3", \ + "10949.3, 10949.3, 10949.3, 11156.8, 11581.6", \ + "10982.2, 10982.2, 10982.2, 11189.8, 11614.5"); + } + fall_transition (inslew_load_5x5__15) { + values ("2961.0, 2961.0, 2961.0, 3120.7, 3439.3", \ + "2961.1, 2961.1, 2961.1, 3120.8, 3439.4", \ + "2961.2, 2961.2, 2961.2, 3120.9, 3439.5", \ + "2961.2, 2961.2, 2961.2, 3120.9, 3439.5", \ + "2961.4, 2961.4, 2961.4, 3121.1, 3439.7"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("20723.5, 20723.5, 20723.5, 20958.6, 21409.9", \ + "20722.0, 20722.0, 20722.0, 20957.1, 21408.4", \ + "20711.1, 20711.1, 20711.1, 20946.2, 21397.5", \ + "20695.4, 20695.4, 20695.4, 20930.5, 21381.8", \ + "20657.5, 20657.5, 20657.5, 20892.6, 21343.9"); + } + rise_transition (inslew_load_5x5__15) { + values ("5600.9, 5600.9, 5600.9, 5792.2, 6175.8", \ + "5603.4, 5603.4, 5603.4, 5794.7, 6178.2", \ + "5605.4, 5605.4, 5605.4, 5796.7, 6180.2", \ + "5609.4, 5609.4, 5609.4, 5800.7, 6184.1", \ + "5611.6, 5611.6, 5611.6, 5802.9, 6186.3"); + } + cell_fall (inslew_load_5x5__15) { + values ("15572.7, 15572.7, 15572.7, 15785.3, 16086.3", \ + "15569.4, 15569.4, 15569.4, 15781.9, 16082.9", \ + "15562.5, 15562.5, 15562.5, 15775.0, 16076.0", \ + "15545.0, 15545.0, 15545.0, 15757.5, 16058.6", \ + "15512.5, 15512.5, 15512.5, 15725.0, 16026.1"); + } + fall_transition (inslew_load_5x5__15) { + values ("3954.1, 3954.1, 3954.1, 4071.2, 4257.4", \ + "3955.0, 3955.0, 3955.0, 4072.1, 4258.2", \ + "3956.1, 3956.1, 3956.1, 4073.1, 4259.2", \ + "3956.4, 3956.4, 3956.4, 4073.4, 4259.5", \ + "3956.5, 3956.5, 3956.5, 4073.4, 4259.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("20723.5, 20723.5, 20723.5, 20958.6, 21409.9", \ + "20722.0, 20722.0, 20722.0, 20957.1, 21408.4", \ + "20711.1, 20711.1, 20711.1, 20946.2, 21397.5", \ + "20695.4, 20695.4, 20695.4, 20930.5, 21381.8", \ + "20657.5, 20657.5, 20657.5, 20892.6, 21343.9"); + } + rise_transition (inslew_load_5x5__15) { + values ("5600.9, 5600.9, 5600.9, 5792.2, 6175.8", \ + "5603.4, 5603.4, 5603.4, 5794.7, 6178.2", \ + "5605.4, 5605.4, 5605.4, 5796.7, 6180.2", \ + "5609.4, 5609.4, 5609.4, 5800.7, 6184.1", \ + "5611.6, 5611.6, 5611.6, 5802.9, 6186.3"); + } + cell_fall (inslew_load_5x5__15) { + values ("15572.7, 15572.7, 15572.7, 15785.3, 16086.3", \ + "15569.4, 15569.4, 15569.4, 15781.9, 16082.9", \ + "15562.5, 15562.5, 15562.5, 15775.0, 16076.0", \ + "15545.0, 15545.0, 15545.0, 15757.5, 16058.6", \ + "15512.5, 15512.5, 15512.5, 15725.0, 16026.1"); + } + fall_transition (inslew_load_5x5__15) { + values ("3954.1, 3954.1, 3954.1, 4071.2, 4257.4", \ + "3955.0, 3955.0, 3955.0, 4072.1, 4258.2", \ + "3956.1, 3956.1, 3956.1, 4073.1, 4259.2", \ + "3956.4, 3956.4, 3956.4, 4073.4, 4259.5", \ + "3956.5, 3956.5, 3956.5, 4073.4, 4259.5"); + } + } + internal_power (energy_pos_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__15) { + values ("105465.5, 105465.5, 105465.5, 107328.0, 111053.2", \ + "111068.6, 111068.6, 111068.6, 111068.6, 111068.6", \ + "111099.2, 111099.2, 111099.2, 111099.2, 111099.2", \ + "111161.0, 111161.0, 111161.0, 111161.0, 111161.0", \ + "111304.2, 111304.2, 111304.2, 111304.2, 111304.2"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("78466.6, 78466.6, 78466.6, 80329.2, 84054.3", \ + "84089.2, 84089.2, 84089.2, 84089.2, 84089.2", \ + "84158.9, 84158.9, 84158.9, 84158.9, 84158.9", \ + "84298.3, 84298.3, 84298.3, 84298.3, 84298.3", \ + "78991.0, 78991.0, 78991.0, 80853.6, 84578.7"); + } + } + internal_power (energy_pos_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__15) { + values ("68909.6, 68909.6, 68909.6, 70772.2, 74497.4", \ + "74512.7, 74512.7, 74512.7, 74512.7, 74512.7", \ + "74543.4, 74543.4, 74543.4, 74543.4, 74543.4", \ + "74604.9, 74604.9, 74604.9, 74604.9, 74604.9", \ + "69157.4, 69157.4, 69157.4, 71020.0, 74745.2"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("62338.5, 62338.5, 62338.5, 64201.1, 67926.3", \ + "67961.1, 67961.1, 67961.1, 67961.1, 67961.1", \ + "68030.8, 68030.8, 68030.8, 68030.8, 68030.8", \ + "68170.2, 68170.2, 68170.2, 68170.2, 68170.2", \ + "62861.9, 62861.9, 62861.9, 64724.5, 68449.7"); + } + } + internal_power (energy_neg_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__15) { + values ("83097.8, 83097.8, 83097.8, 84960.3, 88685.5", \ + "88737.8, 88737.8, 88737.8, 88737.8, 88737.8", \ + "88842.4, 88842.4, 88842.4, 88842.4, 88842.4", \ + "89051.7, 89051.7, 89051.7, 89051.7, 89051.7", \ + "89470.1, 89470.1, 89470.1, 89470.1, 89470.1"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("73195.7, 73195.7, 73195.7, 75058.3, 78783.5", \ + "78804.8, 78804.8, 78804.8, 78804.8, 78804.8", \ + "78847.4, 78847.4, 78847.4, 78847.4, 78847.4", \ + "78932.7, 78932.7, 78932.7, 78932.7, 78932.7", \ + "79103.3, 79103.3, 79103.3, 79103.3, 79103.3"); + } + } + internal_power (energy_neg_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__15) { + values ("61287.5, 61287.5, 61287.5, 63150.1, 66875.2", \ + "61411.0, 61411.0, 61411.0, 63273.6, 66998.8", \ + "61601.7, 61601.7, 61601.7, 63464.3, 67189.5", \ + "61832.3, 61832.3, 61832.3, 63694.9, 67420.1", \ + "62237.2, 62237.2, 62237.2, 64099.8, 67825.0"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("53964.0, 53964.0, 53964.0, 55826.5, 59551.7", \ + "54015.2, 54015.2, 54015.2, 55877.7, 59602.9", \ + "54104.2, 54104.2, 54104.2, 55966.7, 59691.9", \ + "54183.4, 54183.4, 54183.4, 56046.0, 59771.2", \ + "54299.5, 54299.5, 54299.5, 56162.1, 59887.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__15) { + values ("56349.9, 56349.9, 56349.9, 58212.5, 61937.7", \ + "56403.2, 56403.2, 56403.2, 58265.8, 61991.0", \ + "56507.6, 56507.6, 56507.6, 58370.1, 62095.3", \ + "56673.6, 56673.6, 56673.6, 58536.2, 62261.4", \ + "56982.2, 56982.2, 56982.2, 58844.8, 62570.0"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("51398.9, 51398.9, 51398.9, 53261.5, 56986.7", \ + "51417.8, 51417.8, 51417.8, 53280.3, 57005.5", \ + "51450.4, 51450.4, 51450.4, 53313.0, 57038.2", \ + "51512.0, 51512.0, 51512.0, 53374.6, 57099.8", \ + "51641.4, 51641.4, 51641.4, 53504.0, 57229.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__15) { + values ("81739.0, 81739.0, 81739.0, 83601.6, 87326.7", \ + "81797.2, 81797.2, 81797.2, 83659.8, 87385.0", \ + "81888.5, 81888.5, 81888.5, 83751.1, 87476.2", \ + "82072.2, 82072.2, 82072.2, 83934.8, 87660.0", \ + "82391.6, 82391.6, 82391.6, 84254.1, 87979.3"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("66058.1, 66058.1, 66058.1, 67920.7, 71645.9", \ + "66082.4, 66082.4, 66082.4, 67945.0, 71670.2", \ + "66124.1, 66124.1, 66124.1, 67986.7, 71711.9", \ + "66188.0, 66188.0, 66188.0, 68050.5, 71775.7", \ + "66311.0, 66311.0, 66311.0, 68173.5, 71898.7"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__15) { + values ("81739.0, 81739.0, 81739.0, 83601.6, 87326.7", \ + "81797.2, 81797.2, 81797.2, 83659.8, 87385.0", \ + "81888.5, 81888.5, 81888.5, 83751.1, 87476.2", \ + "82072.2, 82072.2, 82072.2, 83934.8, 87660.0", \ + "82391.6, 82391.6, 82391.6, 84254.1, 87979.3"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("66058.1, 66058.1, 66058.1, 67920.7, 71645.9", \ + "66082.4, 66082.4, 66082.4, 67945.0, 71670.2", \ + "66124.1, 66124.1, 66124.1, 67986.7, 71711.9", \ + "66188.0, 66188.0, 66188.0, 68050.5, 71775.7", \ + "66311.0, 66311.0, 66311.0, 68173.5, 71898.7"); + } + } + } + } + + cell (o3_x2) { + area : 21.60 ; + cell_leakage_power : 4.4 ; + leakage_power () { + when : "(i0 & (!(i1) | !(i2)))" ; + value : 3.8 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0))" ; + value : 3.9 ; + } + leakage_power () { + when : "(!((i0 & !(i1))) & i2)" ; + value : 4 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 5.8 ; + } + pin (i2) { + direction : input ; + capacitance : 571.41 ; + } + pin (i1) { + direction : input ; + capacitance : 572.31 ; + } + pin (i0) { + direction : input ; + capacitance : 572.31 ; + } + pin (q) { + function : "(i0 | i1 | i2)" ; + direction : output ; + capacitance : 89.41 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("5294.4, 5294.4, 5294.4, 5633.6, 6250.8", \ + "5303.2, 5303.2, 5303.2, 5642.4, 6259.6", \ + "5320.8, 5320.8, 5320.8, 5660.0, 6277.2", \ + "5356.0, 5356.0, 5356.0, 5695.2, 6312.4", \ + "5426.9, 5426.9, 5426.9, 5766.1, 6383.3"); + } + rise_transition (inslew_load_5x5__9) { + values ("1499.7, 1499.7, 1499.7, 1792.9, 2342.9", \ + "1499.7, 1499.7, 1499.7, 1792.9, 2342.9", \ + "1499.7, 1499.7, 1499.7, 1792.9, 2342.9", \ + "1499.7, 1499.7, 1499.7, 1792.9, 2342.9", \ + "1500.6, 1500.6, 1500.6, 1793.8, 2343.7"); + } + cell_fall (inslew_load_5x5__9) { + values ("12472.5, 12472.5, 12472.5, 12784.0, 13491.8", \ + "12461.1, 12461.1, 12461.1, 12772.6, 13480.4", \ + "12438.4, 12438.4, 12438.4, 12749.9, 13457.7", \ + "12393.0, 12393.0, 12393.0, 12704.5, 13412.3", \ + "12302.2, 12302.2, 12302.2, 12613.7, 13321.5"); + } + fall_transition (inslew_load_5x5__9) { + values ("6843.1, 6843.1, 6843.1, 7037.0, 7377.9", \ + "6843.1, 6843.1, 6843.1, 7037.0, 7377.9", \ + "6843.1, 6843.1, 6843.1, 7037.0, 7377.9", \ + "6843.1, 6843.1, 6843.1, 7037.0, 7377.9", \ + "6843.1, 6843.1, 6843.1, 7037.0, 7377.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("4530.7, 4530.7, 4530.7, 4904.1, 5540.0", \ + "4539.5, 4539.5, 4539.5, 4912.9, 5548.8", \ + "4557.1, 4557.1, 4557.1, 4930.5, 5566.4", \ + "4592.3, 4592.3, 4592.3, 4965.7, 5601.6", \ + "4663.6, 4663.6, 4663.6, 5036.9, 5672.7"); + } + rise_transition (inslew_load_5x5__9) { + values ("974.8, 974.8, 974.8, 1286.2, 1855.7", \ + "974.8, 974.8, 974.8, 1286.2, 1855.7", \ + "974.8, 974.8, 974.8, 1286.2, 1855.7", \ + "974.8, 974.8, 974.8, 1286.2, 1855.7", \ + "976.3, 976.3, 976.3, 1287.7, 1857.1"); + } + cell_fall (inslew_load_5x5__9) { + values ("9770.6, 9770.6, 9770.6, 10033.9, 10525.7", \ + "9764.1, 9764.1, 9764.1, 10027.5, 10519.3", \ + "9755.1, 9755.1, 9755.1, 10018.5, 10510.5", \ + "9735.6, 9735.6, 9735.6, 9999.1, 10491.1", \ + "9698.5, 9698.5, 9698.5, 9962.0, 10454.0"); + } + fall_transition (inslew_load_5x5__9) { + values ("5087.3, 5087.3, 5087.3, 5211.8, 5498.5", \ + "5088.7, 5088.7, 5088.7, 5213.4, 5500.1", \ + "5093.2, 5093.2, 5093.2, 5217.6, 5504.1", \ + "5096.1, 5096.1, 5096.1, 5220.7, 5507.2", \ + "5096.5, 5096.5, 5096.5, 5221.0, 5507.6"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("3916.4, 3916.4, 3916.4, 4260.5, 4836.9", \ + "3925.2, 3925.2, 3925.2, 4269.3, 4845.7", \ + "3942.8, 3942.8, 3942.8, 4286.9, 4863.3", \ + "3978.0, 3978.0, 3978.0, 4322.1, 4898.5", \ + "4045.8, 4045.8, 4045.8, 4390.3, 4967.0"); + } + rise_transition (inslew_load_5x5__9) { + values ("673.9, 673.9, 673.9, 982.1, 1538.2", \ + "673.9, 673.9, 673.9, 982.1, 1538.2", \ + "673.9, 673.9, 673.9, 982.1, 1538.2", \ + "673.9, 673.9, 673.9, 982.1, 1538.2", \ + "674.3, 674.3, 674.3, 982.6, 1538.8"); + } + cell_fall (inslew_load_5x5__9) { + values ("6737.2, 6737.2, 6737.2, 6985.8, 7482.8", \ + "6755.1, 6755.1, 6755.1, 7003.7, 7497.3", \ + "6759.8, 6759.8, 6759.8, 7008.4, 7499.6", \ + "6789.2, 6789.2, 6789.2, 7037.8, 7522.7", \ + "6812.0, 6812.0, 6812.0, 7060.7, 7540.7"); + } + fall_transition (inslew_load_5x5__9) { + values ("3068.3, 3068.3, 3068.3, 3256.9, 3620.2", \ + "3084.7, 3084.7, 3084.7, 3272.4, 3636.1", \ + "3095.8, 3095.8, 3095.8, 3283.1, 3647.0", \ + "3125.9, 3125.9, 3125.9, 3311.8, 3676.8", \ + "3148.7, 3148.7, 3148.7, 3333.7, 3699.0"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__9) { + values ("26820.5, 26820.5, 26820.5, 27938.2, 30173.5", \ + "30211.8, 30211.8, 30211.8, 30211.8, 30211.8", \ + "30288.3, 30288.3, 30288.3, 30288.3, 30288.3", \ + "30441.3, 30441.3, 30441.3, 30441.3, 30441.3", \ + "27396.1, 27396.1, 27396.1, 28513.8, 30749.1"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("49683.3, 49683.3, 49683.3, 50800.9, 53036.3", \ + "53079.8, 53079.8, 53079.8, 53079.8, 53079.8", \ + "53166.8, 53166.8, 53166.8, 53166.8, 53166.8", \ + "53340.7, 53340.7, 53340.7, 53340.7, 53340.7", \ + "53688.6, 53688.6, 53688.6, 53688.6, 53688.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__9) { + values ("23461.9, 23461.9, 23461.9, 24579.6, 26814.9", \ + "26840.1, 26840.1, 26840.1, 26840.1, 26840.1", \ + "26890.5, 26890.5, 26890.5, 26890.5, 26890.5", \ + "26991.3, 26991.3, 26991.3, 26991.3, 26991.3", \ + "23842.8, 23842.8, 23842.8, 24960.5, 27195.8"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("35716.7, 35716.7, 35716.7, 36834.4, 39069.7", \ + "35765.5, 35765.5, 35765.5, 36883.2, 39118.5", \ + "35866.2, 35866.2, 35866.2, 36983.9, 39219.3", \ + "36052.1, 36052.1, 36052.1, 37169.8, 39405.1", \ + "36407.0, 36407.0, 36407.0, 37524.6, 39760.0"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__9) { + values ("17244.6, 17244.6, 17244.6, 18362.3, 20597.6", \ + "20615.6, 20615.6, 20615.6, 20615.6, 20615.6", \ + "20651.5, 20651.5, 20651.5, 20651.5, 20651.5", \ + "20723.3, 20723.3, 20723.3, 20723.3, 20723.3", \ + "17522.2, 17522.2, 17522.2, 18639.8, 20875.2"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("22323.6, 22323.6, 22323.6, 23441.3, 25676.6", \ + "22414.7, 22414.7, 22414.7, 23532.4, 25767.7", \ + "22534.4, 22534.4, 22534.4, 23652.1, 25887.4", \ + "22796.7, 22796.7, 22796.7, 23914.4, 26149.7", \ + "23211.9, 23211.9, 23211.9, 24329.6, 26564.9"); + } + } + } + } + + cell (no2_x4) { + area : 25.20 ; + cell_leakage_power : 7.2 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 6.1 ; + } + leakage_power () { + when : "i1" ; + value : 6.4 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 9.2 ; + } + pin (i1) { + direction : input ; + capacitance : 711.35 ; + } + pin (i0) { + direction : input ; + capacitance : 711.95 ; + } + pin (nq) { + function : "(!(i0) & !(i1))" ; + direction : output ; + capacitance : 148.45 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("13532.9, 13532.9, 13532.9, 13788.9, 14266.7", \ + "13527.5, 13527.5, 13527.5, 13783.5, 14261.3", \ + "13516.8, 13516.8, 13516.8, 13772.8, 14250.6", \ + "13495.2, 13495.2, 13495.2, 13751.2, 14229.0", \ + "13452.2, 13452.2, 13452.2, 13708.2, 14186.0"); + } + rise_transition (inslew_load_5x5__13) { + values ("3482.9, 3482.9, 3482.9, 3691.0, 4091.2", \ + "3482.9, 3482.9, 3482.9, 3691.0, 4091.2", \ + "3482.9, 3482.9, 3482.9, 3691.0, 4091.2", \ + "3482.9, 3482.9, 3482.9, 3691.0, 4091.2", \ + "3482.9, 3482.9, 3482.9, 3691.0, 4091.2"); + } + cell_fall (inslew_load_5x5__13) { + values ("11902.3, 11902.3, 11902.3, 12109.1, 12527.0", \ + "11911.1, 11911.1, 11911.1, 12117.9, 12535.8", \ + "11928.7, 11928.7, 11928.7, 12135.5, 12553.4", \ + "11963.9, 11963.9, 11963.9, 12170.7, 12588.6", \ + "12034.3, 12034.3, 12034.3, 12241.1, 12659.0"); + } + fall_transition (inslew_load_5x5__13) { + values ("2978.2, 2978.2, 2978.2, 3136.4, 3454.2", \ + "2978.2, 2978.2, 2978.2, 3136.4, 3454.2", \ + "2978.2, 2978.2, 2978.2, 3136.4, 3454.2", \ + "2978.2, 2978.2, 2978.2, 3136.4, 3454.2", \ + "2978.2, 2978.2, 2978.2, 3136.4, 3454.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("9405.9, 9405.9, 9405.9, 9684.8, 10193.1", \ + "9414.1, 9414.1, 9414.1, 9693.0, 10201.3", \ + "9430.0, 9430.0, 9430.0, 9708.9, 10217.0", \ + "9444.9, 9444.9, 9444.9, 9723.8, 10231.9", \ + "9478.8, 9478.8, 9478.8, 9757.6, 10265.7"); + } + rise_transition (inslew_load_5x5__13) { + values ("2285.6, 2285.6, 2285.6, 2522.6, 2957.3", \ + "2288.7, 2288.7, 2288.7, 2525.7, 2960.3", \ + "2293.6, 2293.6, 2293.6, 2530.5, 2964.9", \ + "2295.9, 2295.9, 2295.9, 2532.8, 2967.2", \ + "2299.1, 2299.1, 2299.1, 2535.9, 2970.2"); + } + cell_fall (inslew_load_5x5__13) { + values ("10505.5, 10505.5, 10505.5, 10712.4, 11142.4", \ + "10514.3, 10514.3, 10514.3, 10721.2, 11151.2", \ + "10531.9, 10531.9, 10531.9, 10738.8, 11168.8", \ + "10567.1, 10567.1, 10567.1, 10774.0, 11204.0", \ + "10636.2, 10636.2, 10636.2, 10843.1, 11273.1"); + } + fall_transition (inslew_load_5x5__13) { + values ("2930.5, 2930.5, 2930.5, 3090.8, 3408.2", \ + "2930.5, 2930.5, 2930.5, 3090.8, 3408.2", \ + "2930.5, 2930.5, 2930.5, 3090.8, 3408.2", \ + "2930.5, 2930.5, 2930.5, 3090.8, 3408.2", \ + "2930.6, 2930.6, 2930.6, 3090.9, 3408.3"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__13) { + values ("69180.6, 69180.6, 69180.6, 71036.1, 74747.3", \ + "74787.2, 74787.2, 74787.2, 74787.2, 74787.2", \ + "74867.0, 74867.0, 74867.0, 74867.0, 74867.0", \ + "75026.6, 75026.6, 75026.6, 75026.6, 75026.6", \ + "75345.8, 75345.8, 75345.8, 75345.8, 75345.8"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("57156.3, 57156.3, 57156.3, 59011.9, 62723.0", \ + "62777.8, 62777.8, 62777.8, 62777.8, 62777.8", \ + "62887.4, 62887.4, 62887.4, 62887.4, 62887.4", \ + "63106.6, 63106.6, 63106.6, 63106.6, 63106.6", \ + "57980.2, 57980.2, 57980.2, 59835.8, 63546.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__13) { + values ("49822.5, 49822.5, 49822.5, 51678.1, 55389.3", \ + "49884.6, 49884.6, 49884.6, 51740.2, 55451.3", \ + "50001.3, 50001.3, 50001.3, 51856.9, 55568.0", \ + "50190.3, 50190.3, 50190.3, 52045.8, 55757.0", \ + "50558.9, 50558.9, 50558.9, 52414.4, 56125.6"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("49432.8, 49432.8, 49432.8, 51288.4, 54999.6", \ + "55035.8, 55035.8, 55035.8, 55035.8, 55035.8", \ + "55108.3, 55108.3, 55108.3, 55108.3, 55108.3", \ + "55253.3, 55253.3, 55253.3, 55253.3, 55253.3", \ + "49984.1, 49984.1, 49984.1, 51839.6, 55550.8"); + } + } + } + } + + cell (oa3ao322_x2) { + area : 39.60 ; + cell_leakage_power : 7.2 ; + leakage_power () { + when : "(i6 & i5 & i4 & i3 & i2 & i1 & i0)" ; + value : 8.3 ; + } + leakage_power () { + when : "(i0 & i1 & i2 & ((i3 & ((i4 & (i5 ^ i6)) | (!(i4) & i5 & i6))) | (!(i3) & i4 & i5 & i6)))" ; + value : 7.9 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & i2 & i1 & i0)" ; + value : 7.4 ; + } + leakage_power () { + when : "(!(i6) & i5 & i4 & i3 & !(i2) & i1 & i0)" ; + value : 8.8 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & ((!(i3) & !((i4 & i5)) & i6) | (!(i4) & !(i5) & i6))) | (!(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))))" ; + value : 7.8 ; + } + leakage_power () { + when : "(i0 & i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 6.8 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & i4 & i5 & i6) | (!(i0) & i1 & i2 & i3 & i4 & i5 & i6))" ; + value : 8.7 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3 & i4 & i5 & !(i6))" ; + value : 8.5 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3 & !(i5) & i6) | (!(i0) & i1 & i2 & i3 & !(i5) & i6))" ; + value : 8.4 ; + } + leakage_power () { + when : "((i0 & ((i1 & i2 & ((i3 & !((i4 & i5)) & !(i6)) | (!(i3) & (i4 | i5) & !(i6)))) | (i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))) | (i1 & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))" ; + value : 7.5 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))) | (!(i0) & i1 & i2 & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))))" ; + value : 8.2 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 6.5 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & !(i4) & !(i5) & i6)" ; + value : 6.4 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & !(i4) & !(i5) & !(i6))" ; + value : 5.5 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & i5 & i6) | (!(i0) & (i1 ^ i2) & i3 & i4 & i5 & i6))" ; + value : 9.1 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & i5 & !(i6)) | (!(i0) & (i1 ^ i2) & i3 & i4 & i5 & !(i6)))" ; + value : 7.7 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & i6) | (!(i1) & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))) | (!(i0) & (i1 ^ i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))" ; + value : 6.7 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))) | (!(i0) & (i1 ^ i2) & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))))" ; + value : 8.6 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))) | (!(i0) & (i1 ^ i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))" ; + value : 5.8 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & i6))" ; + value : 5.6 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & !(i6)))" ; + value : 4.8 ; + } + leakage_power () { + when : "(!(i6) & i5 & i4 & i3 & !(i2) & !(i1) & !(i0))" ; + value : 7 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & i3 & (i4 | !(i5)) & i6)" ; + value : 9.6 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 6 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & !(i5) & i6) | (!(i0) & ((i1 & !(i2) & i3 & !(i5) & i6) | (!(i1) & ((i2 & i3 & !(i5) & i6) | (!(i2) & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))))))))" ; + value : 9 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 5 ; + } + leakage_power () { + when : "(i6 & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 4.9 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 4 ; + } + pin (i6) { + direction : input ; + capacitance : 514.62 ; + } + pin (i5) { + direction : input ; + capacitance : 544.97 ; + } + pin (i4) { + direction : input ; + capacitance : 545.27 ; + } + pin (i3) { + direction : input ; + capacitance : 545.57 ; + } + pin (i2) { + direction : input ; + capacitance : 538.60 ; + } + pin (i1) { + direction : input ; + capacitance : 541.15 ; + } + pin (i0) { + direction : input ; + capacitance : 541.75 ; + } + pin (q) { + function : "((i6 & ((i2 & i1 & i0) | i5 | i4 | i3)) | (i2 & i1 & i0))" ; + direction : output ; + capacitance : 85.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("11839.5, 11839.5, 11839.5, 12110.2, 12625.9", \ + "11828.4, 11828.4, 11828.4, 12099.1, 12614.8", \ + "11806.2, 11806.2, 11806.2, 12076.9, 12592.6", \ + "11761.9, 11761.9, 11761.9, 12032.6, 12548.3", \ + "11673.3, 11673.3, 11673.3, 11944.0, 12459.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("6748.6, 6748.6, 6748.6, 6966.9, 7398.9", \ + "6748.6, 6748.6, 6748.6, 6966.9, 7398.9", \ + "6748.6, 6748.6, 6748.6, 6966.9, 7398.9", \ + "6748.6, 6748.6, 6748.6, 6966.9, 7398.9", \ + "6748.6, 6748.6, 6748.6, 6966.9, 7398.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("22334.1, 22334.1, 22334.1, 22570.9, 23031.7", \ + "22323.2, 22323.2, 22323.2, 22560.0, 23020.8", \ + "22301.4, 22301.4, 22301.4, 22538.2, 22999.0", \ + "22257.7, 22257.7, 22257.7, 22494.5, 22955.3", \ + "22170.4, 22170.4, 22170.4, 22407.2, 22868.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("13807.8, 13807.8, 13807.8, 13971.7, 14305.7", \ + "13807.8, 13807.8, 13807.8, 13971.6, 14305.6", \ + "13807.8, 13807.8, 13807.8, 13971.6, 14305.6", \ + "13807.8, 13807.8, 13807.8, 13971.7, 14305.7", \ + "13807.8, 13807.8, 13807.8, 13971.7, 14305.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("10350.5, 10350.5, 10350.5, 10619.9, 11134.5", \ + "10347.1, 10347.1, 10347.1, 10616.6, 11131.1", \ + "10338.2, 10338.2, 10338.2, 10607.6, 11122.2", \ + "10321.8, 10321.8, 10321.8, 10591.3, 11105.8", \ + "10289.8, 10289.8, 10289.8, 10559.2, 11073.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("5768.7, 5768.7, 5768.7, 5988.8, 6429.1", \ + "5770.6, 5770.6, 5770.6, 5990.8, 6431.0", \ + "5771.2, 5771.2, 5771.2, 5991.3, 6431.5", \ + "5771.2, 5771.2, 5771.2, 5991.4, 6431.6", \ + "5771.2, 5771.2, 5771.2, 5991.3, 6431.5"); + } + cell_fall (inslew_load_5x5__0) { + values ("21507.9, 21507.9, 21507.9, 21744.8, 22200.8", \ + "21497.0, 21497.0, 21497.0, 21733.9, 22189.9", \ + "21475.1, 21475.1, 21475.1, 21712.0, 22168.0", \ + "21431.5, 21431.5, 21431.5, 21668.4, 22124.4", \ + "21344.1, 21344.1, 21344.1, 21581.0, 22037.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("13244.9, 13244.9, 13244.9, 13409.8, 13739.0", \ + "13244.9, 13244.9, 13244.9, 13409.8, 13739.0", \ + "13244.9, 13244.9, 13244.9, 13409.8, 13739.0", \ + "13244.9, 13244.9, 13244.9, 13409.8, 13739.0", \ + "13244.9, 13244.9, 13244.9, 13409.8, 13739.0"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("8868.9, 8868.9, 8868.9, 9147.6, 9685.4", \ + "8888.6, 8888.6, 8888.6, 9166.8, 9704.5", \ + "8906.0, 8906.0, 8906.0, 9183.6, 9721.3", \ + "8912.9, 8912.9, 8912.9, 9190.4, 9728.0", \ + "8938.5, 8938.5, 8938.5, 9215.8, 9753.4"); + } + rise_transition (inslew_load_5x5__0) { + values ("4786.8, 4786.8, 4786.8, 5011.8, 5453.0", \ + "4803.9, 4803.9, 4803.9, 5029.0, 5470.0", \ + "4819.2, 4819.2, 4819.2, 5044.2, 5485.2", \ + "4822.2, 4822.2, 4822.2, 5047.3, 5488.2", \ + "4826.0, 4826.0, 4826.0, 5051.1, 5491.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("20305.7, 20305.7, 20305.7, 20541.2, 20991.7", \ + "20294.8, 20294.8, 20294.8, 20530.3, 20980.8", \ + "20273.0, 20273.0, 20273.0, 20508.5, 20959.0", \ + "20229.3, 20229.3, 20229.3, 20464.8, 20915.3", \ + "20142.0, 20142.0, 20142.0, 20377.5, 20828.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("12426.4, 12426.4, 12426.4, 12593.0, 12916.1", \ + "12426.4, 12426.4, 12426.4, 12593.0, 12916.1", \ + "12426.4, 12426.4, 12426.4, 12593.0, 12916.1", \ + "12426.4, 12426.4, 12426.4, 12593.0, 12916.1", \ + "12426.4, 12426.4, 12426.4, 12593.0, 12916.1"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("8355.4, 8355.4, 8355.4, 8644.0, 9182.6", \ + "8356.0, 8356.0, 8356.0, 8644.6, 9183.2", \ + "8357.0, 8357.0, 8357.0, 8645.6, 9184.2", \ + "8359.1, 8359.1, 8359.1, 8647.7, 9186.3", \ + "8363.3, 8363.3, 8363.3, 8651.8, 9190.5"); + } + rise_transition (inslew_load_5x5__0) { + values ("3854.6, 3854.6, 3854.6, 4088.4, 4539.5", \ + "3854.6, 3854.6, 3854.6, 4088.4, 4539.5", \ + "3854.6, 3854.6, 3854.6, 4088.4, 4539.5", \ + "3854.6, 3854.6, 3854.6, 4088.4, 4539.5", \ + "3854.6, 3854.6, 3854.6, 4088.5, 4539.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("9282.5, 9282.5, 9282.5, 9538.9, 10015.2", \ + "9319.2, 9319.2, 9319.2, 9575.8, 10052.6", \ + "9286.5, 9286.5, 9286.5, 9543.6, 10020.3", \ + "9361.7, 9361.7, 9361.7, 9620.9, 10098.1", \ + "9295.9, 9295.9, 9295.9, 9653.0, 10131.2"); + } + fall_transition (inslew_load_5x5__0) { + values ("5119.1, 5119.1, 5119.1, 5241.2, 5513.2", \ + "5155.3, 5155.3, 5155.3, 5277.7, 5548.5", \ + "5146.8, 5146.8, 5146.8, 5269.2, 5540.3", \ + "5233.1, 5233.1, 5233.1, 5356.3, 5624.5", \ + "5261.4, 5261.4, 5261.4, 5426.4, 5692.5"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("10244.5, 10244.5, 10244.5, 10514.7, 11048.4", \ + "10245.0, 10245.0, 10245.0, 10515.2, 11048.9", \ + "10246.0, 10246.0, 10246.0, 10516.2, 11049.9", \ + "10248.1, 10248.1, 10248.1, 10518.3, 11052.0", \ + "10252.3, 10252.3, 10252.3, 10522.5, 11056.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("5126.6, 5126.6, 5126.6, 5351.1, 5790.7", \ + "5126.6, 5126.6, 5126.6, 5351.1, 5790.7", \ + "5126.6, 5126.6, 5126.6, 5351.1, 5790.7", \ + "5126.6, 5126.6, 5126.6, 5351.1, 5790.7", \ + "5126.6, 5126.6, 5126.6, 5351.1, 5790.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("12712.6, 12712.6, 12712.6, 12958.2, 13670.8", \ + "12687.1, 12687.1, 12687.1, 12932.7, 13645.6", \ + "12698.3, 12698.3, 12698.3, 12944.0, 13656.0", \ + "12677.7, 12677.7, 12677.7, 12923.4, 13635.0", \ + "12671.2, 12671.2, 12671.2, 12917.1, 13627.1"); + } + fall_transition (inslew_load_5x5__0) { + values ("7561.6, 7561.6, 7561.6, 7749.3, 8146.4", \ + "7552.9, 7552.9, 7552.9, 7740.5, 8136.5", \ + "7576.9, 7576.9, 7576.9, 7764.6, 8162.7", \ + "7592.5, 7592.5, 7592.5, 7780.3, 8180.1", \ + "7636.9, 7636.9, 7636.9, 7824.8, 8229.2"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("11169.1, 11169.1, 11169.1, 11438.4, 11953.5", \ + "11169.6, 11169.6, 11169.6, 11438.9, 11954.0", \ + "11170.6, 11170.6, 11170.6, 11439.9, 11955.0", \ + "11172.7, 11172.7, 11172.7, 11442.0, 11957.1", \ + "11176.9, 11176.9, 11176.9, 11446.2, 11961.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("5733.6, 5733.6, 5733.6, 5953.8, 6394.3", \ + "5733.6, 5733.6, 5733.6, 5953.8, 6394.3", \ + "5733.6, 5733.6, 5733.6, 5953.8, 6394.3", \ + "5733.6, 5733.6, 5733.6, 5953.8, 6394.3", \ + "5733.6, 5733.6, 5733.6, 5953.8, 6394.3"); + } + cell_fall (inslew_load_5x5__0) { + values ("16748.6, 16748.6, 16748.6, 16974.1, 17415.5", \ + "16743.2, 16743.2, 16743.2, 16968.8, 17410.2", \ + "16717.4, 16717.4, 16717.4, 16942.9, 17384.3", \ + "16686.5, 16686.5, 16686.5, 16912.2, 17353.5", \ + "16617.8, 16617.8, 16617.8, 16843.7, 17285.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("10201.1, 10201.1, 10201.1, 10367.5, 10679.1", \ + "10206.9, 10206.9, 10206.9, 10373.8, 10685.1", \ + "10208.0, 10208.0, 10208.0, 10374.7, 10686.2", \ + "10221.8, 10221.8, 10221.8, 10388.3, 10699.8", \ + "10236.9, 10236.9, 10236.9, 10403.3, 10714.6"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("6446.7, 6446.7, 6446.7, 6748.5, 7313.8", \ + "6460.9, 6460.9, 6460.9, 6762.0, 7327.2", \ + "6472.6, 6472.6, 6472.6, 6773.0, 7338.2", \ + "6478.9, 6478.9, 6478.9, 6779.0, 7344.1", \ + "6493.2, 6493.2, 6493.2, 6793.2, 7358.3"); + } + rise_transition (inslew_load_5x5__0) { + values ("2627.5, 2627.5, 2627.5, 2883.0, 3364.5", \ + "2641.3, 2641.3, 2641.3, 2896.2, 3377.4", \ + "2653.6, 2653.6, 2653.6, 2908.0, 3388.9", \ + "2658.5, 2658.5, 2658.5, 2912.8, 3393.5", \ + "2660.5, 2660.5, 2660.5, 2914.7, 3395.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("6646.9, 6646.9, 6646.9, 6885.7, 7449.2", \ + "6657.9, 6657.9, 6657.9, 6896.8, 7459.2", \ + "6660.4, 6660.4, 6660.4, 6899.4, 7461.1", \ + "6682.4, 6682.4, 6682.4, 6921.6, 7481.2", \ + "6707.1, 6707.1, 6707.1, 6946.3, 7504.3"); + } + fall_transition (inslew_load_5x5__0) { + values ("2713.3, 2713.3, 2713.3, 2907.5, 3259.5", \ + "2722.0, 2722.0, 2722.0, 2915.9, 3268.6", \ + "2727.2, 2727.2, 2727.2, 2920.9, 3274.1", \ + "2744.3, 2744.3, 2744.3, 2937.4, 3292.2", \ + "2758.5, 2758.5, 2758.5, 2951.1, 3307.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("51756.1, 51756.1, 51756.1, 52828.2, 54972.6", \ + "54994.1, 54994.1, 54994.1, 54994.1, 54994.1", \ + "55037.2, 55037.2, 55037.2, 55037.2, 55037.2", \ + "55123.4, 55123.4, 55123.4, 55123.4, 55123.4", \ + "52079.4, 52079.4, 52079.4, 53151.5, 55295.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("82964.8, 82964.8, 82964.8, 84037.0, 86181.3", \ + "83032.6, 83032.6, 83032.6, 84104.8, 86249.1", \ + "86384.8, 86384.8, 86384.8, 86384.8, 86384.8", \ + "86656.3, 86656.3, 86656.3, 86656.3, 86656.3", \ + "87199.2, 87199.2, 87199.2, 87199.2, 87199.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("44488.7, 44488.7, 44488.7, 45560.9, 47705.2", \ + "44519.3, 44519.3, 44519.3, 45591.5, 47735.8", \ + "44570.2, 44570.2, 44570.2, 45642.4, 47786.7", \ + "44669.4, 44669.4, 44669.4, 45741.6, 47885.9", \ + "48083.9, 48083.9, 48083.9, 48083.9, 48083.9"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("79448.9, 79448.9, 79448.9, 80521.0, 82665.4", \ + "82716.3, 82716.3, 82716.3, 82716.3, 82716.3", \ + "82818.0, 82818.0, 82818.0, 82818.0, 82818.0", \ + "83021.5, 83021.5, 83021.5, 83021.5, 83021.5", \ + "83428.5, 83428.5, 83428.5, 83428.5, 83428.5"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("37579.9, 37579.9, 37579.9, 38652.1, 40796.4", \ + "37655.1, 37655.1, 37655.1, 38727.3, 40871.6", \ + "37751.7, 37751.7, 37751.7, 38823.8, 40968.2", \ + "37867.2, 37867.2, 37867.2, 38939.3, 41083.7", \ + "38091.5, 38091.5, 38091.5, 39163.7, 41308.0"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("74350.1, 74350.1, 74350.1, 75422.2, 77566.6", \ + "77606.5, 77606.5, 77606.5, 77606.5, 77606.5", \ + "77686.6, 77686.6, 77686.6, 77686.6, 77686.6", \ + "77846.5, 77846.5, 77846.5, 77846.5, 77846.5", \ + "78166.5, 78166.5, 78166.5, 78166.5, 78166.5"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("29370.3, 29370.3, 29370.3, 30442.5, 32586.8", \ + "32600.5, 32600.5, 32600.5, 32600.5, 32600.5", \ + "32627.7, 32627.7, 32627.7, 32627.7, 32627.7", \ + "32682.1, 32682.1, 32682.1, 32682.1, 32682.1", \ + "29574.7, 29574.7, 29574.7, 30646.8, 32791.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("30154.0, 30154.0, 30154.0, 31226.1, 33370.5", \ + "30294.4, 30294.4, 30294.4, 31366.6, 33510.9", \ + "30339.1, 30339.1, 30339.1, 31411.3, 33555.6", \ + "30729.5, 30729.5, 30729.5, 31801.7, 33946.0", \ + "31209.6, 31209.6, 31209.6, 32281.8, 34426.2"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__0) { + values ("37074.1, 37074.1, 37074.1, 38146.3, 40290.6", \ + "40308.2, 40308.2, 40308.2, 40308.2, 40308.2", \ + "40343.4, 40343.4, 40343.4, 40343.4, 40343.4", \ + "40413.8, 40413.8, 40413.8, 40413.8, 40413.8", \ + "40554.6, 40554.6, 40554.6, 40554.6, 40554.6"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("45156.8, 45156.8, 45156.8, 46229.0, 48373.3", \ + "45164.3, 45164.3, 45164.3, 46236.5, 48380.8", \ + "45310.6, 45310.6, 45310.6, 46382.8, 48527.1", \ + "45500.8, 45500.8, 45500.8, 46572.9, 48717.3", \ + "45922.9, 45922.9, 45922.9, 46995.1, 49139.4"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__0) { + values ("40920.2, 40920.2, 40920.2, 41992.4, 44136.7", \ + "44160.4, 44160.4, 44160.4, 44160.4, 44160.4", \ + "44207.8, 44207.8, 44207.8, 44207.8, 44207.8", \ + "44302.6, 44302.6, 44302.6, 44302.6, 44302.6", \ + "44492.2, 44492.2, 44492.2, 44492.2, 44492.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("60660.5, 60660.5, 60660.5, 61732.6, 63877.0", \ + "60714.5, 60714.5, 60714.5, 61786.7, 63931.0", \ + "60788.4, 60788.4, 60788.4, 61860.6, 64004.9", \ + "60972.2, 60972.2, 60972.2, 62044.3, 64188.7", \ + "61301.2, 61301.2, 61301.2, 62373.4, 64517.7"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__0) { + values ("22855.5, 22855.5, 22855.5, 23927.6, 26072.0", \ + "22907.1, 22907.1, 22907.1, 23979.3, 26123.6", \ + "22975.5, 22975.5, 22975.5, 24047.6, 26192.0", \ + "23066.3, 23066.3, 23066.3, 24138.5, 26282.9", \ + "23229.9, 23229.9, 23229.9, 24302.1, 26446.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("21516.6, 21516.6, 21516.6, 22588.8, 24733.1", \ + "21575.4, 21575.4, 21575.4, 22647.5, 24791.9", \ + "21658.0, 21658.0, 21658.0, 22730.2, 24874.5", \ + "21842.5, 21842.5, 21842.5, 22914.7, 25059.0", \ + "22153.0, 22153.0, 22153.0, 23225.1, 25369.5"); + } + } + } + } + + cell (oa2ao222_x4) { + area : 39.60 ; + cell_leakage_power : 8.7 ; + leakage_power () { + when : "(i0 & i1 & ((i2 & i3) | i4))" ; + value : 10 ; + } + leakage_power () { + when : "(i0 & i1 & !((i2 & i3)) & !(i4))" ; + value : 9.7 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & !(i1) & i0)" ; + value : 9.1 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & i0)" ; + value : 8.6 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & !(i1) & i0)" ; + value : 7.5 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & i1 & !(i0))" ; + value : 8.8 ; + } + leakage_power () { + when : "((i0 ^ i1) & (i2 | i3) & i4)" ; + value : 11 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & !(i4)) | (!(i0) & i1 & !(i2) & !(i3) & i4))" ; + value : 8.3 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & (i2 ^ i3) & !(i4)) | (!(i1) & i2 & i3 & !(i4))))" ; + value : 7.9 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 | i3) & i4)" ; + value : 12 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4)) | (!(i1) & (i2 ^ i3) & !(i4))))" ; + value : 7.1 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 7.4 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 6.2 ; + } + pin (i4) { + direction : input ; + capacitance : 736.44 ; + } + pin (i3) { + direction : input ; + capacitance : 734.34 ; + } + pin (i2) { + direction : input ; + capacitance : 734.94 ; + } + pin (i1) { + direction : input ; + capacitance : 664.65 ; + } + pin (i0) { + direction : input ; + capacitance : 666.60 ; + } + pin (q) { + function : "(((i3 | i2) & ((i1 & i0) | i4)) | (i1 & i0))" ; + direction : output ; + capacitance : 152.23 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("10216.6, 10216.6, 10216.6, 10457.1, 10926.2", \ + "10211.4, 10211.4, 10211.4, 10451.9, 10921.0", \ + "10201.1, 10201.1, 10201.1, 10441.6, 10910.7", \ + "10180.5, 10180.5, 10180.5, 10421.0, 10890.1", \ + "10139.2, 10139.2, 10139.2, 10379.7, 10848.8"); + } + rise_transition (inslew_load_5x5__6) { + values ("5321.8, 5321.8, 5321.8, 5519.2, 5911.2", \ + "5321.8, 5321.8, 5321.8, 5519.2, 5911.2", \ + "5321.8, 5321.8, 5321.8, 5519.2, 5911.2", \ + "5321.8, 5321.8, 5321.8, 5519.2, 5911.2", \ + "5321.8, 5321.8, 5321.8, 5519.2, 5911.3"); + } + cell_fall (inslew_load_5x5__6) { + values ("16886.8, 16886.8, 16886.8, 17102.1, 17533.5", \ + "16879.7, 16879.7, 16879.7, 17095.0, 17526.4", \ + "16865.5, 16865.5, 16865.5, 17080.8, 17512.2", \ + "16837.2, 16837.2, 16837.2, 17052.5, 17483.9", \ + "16780.7, 16780.7, 16780.7, 16996.0, 17427.4"); + } + fall_transition (inslew_load_5x5__6) { + values ("9655.5, 9655.5, 9655.5, 9828.7, 10152.6", \ + "9655.5, 9655.5, 9655.5, 9828.7, 10152.6", \ + "9655.5, 9655.5, 9655.5, 9828.7, 10152.6", \ + "9655.5, 9655.5, 9655.5, 9828.7, 10152.6", \ + "9655.5, 9655.5, 9655.5, 9828.7, 10152.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("9067.2, 9067.2, 9067.2, 9320.8, 9804.7", \ + "9072.2, 9072.2, 9072.2, 9325.7, 9809.5", \ + "9079.1, 9079.1, 9079.1, 9332.5, 9816.4", \ + "9095.8, 9095.8, 9095.8, 9349.2, 9833.1", \ + "9129.5, 9129.5, 9129.5, 9382.9, 9866.8"); + } + rise_transition (inslew_load_5x5__6) { + values ("4616.6, 4616.6, 4616.6, 4816.7, 5211.0", \ + "4619.1, 4619.1, 4619.1, 4819.1, 5213.4", \ + "4619.4, 4619.4, 4619.4, 4819.5, 5213.7", \ + "4619.8, 4619.8, 4619.8, 4819.8, 5214.1", \ + "4619.8, 4619.8, 4619.8, 4819.8, 5214.1"); + } + cell_fall (inslew_load_5x5__6) { + values ("16055.8, 16055.8, 16055.8, 16272.4, 16703.9", \ + "16048.7, 16048.7, 16048.7, 16265.3, 16696.8", \ + "16034.6, 16034.6, 16034.6, 16251.2, 16682.7", \ + "16006.3, 16006.3, 16006.3, 16222.9, 16654.4", \ + "15949.7, 15949.7, 15949.7, 16166.3, 16597.8"); + } + fall_transition (inslew_load_5x5__6) { + values ("9137.8, 9137.8, 9137.8, 9313.0, 9634.7", \ + "9137.8, 9137.8, 9137.8, 9313.0, 9634.7", \ + "9137.8, 9137.8, 9137.8, 9313.0, 9634.7", \ + "9137.8, 9137.8, 9137.8, 9313.0, 9634.7", \ + "9137.8, 9137.8, 9137.8, 9313.0, 9634.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("11019.8, 11019.8, 11019.8, 11260.1, 11725.8", \ + "11014.7, 11014.7, 11014.7, 11255.0, 11720.7", \ + "11004.4, 11004.4, 11004.4, 11244.7, 11710.4", \ + "10983.7, 10983.7, 10983.7, 11224.0, 11689.7", \ + "10942.5, 10942.5, 10942.5, 11182.8, 11648.5"); + } + rise_transition (inslew_load_5x5__6) { + values ("5424.7, 5424.7, 5424.7, 5621.4, 6013.3", \ + "5424.7, 5424.7, 5424.7, 5621.4, 6013.3", \ + "5424.7, 5424.7, 5424.7, 5621.4, 6013.3", \ + "5424.7, 5424.7, 5424.7, 5621.4, 6013.3", \ + "5424.7, 5424.7, 5424.7, 5621.4, 6013.3"); + } + cell_fall (inslew_load_5x5__6) { + values ("10067.8, 10067.8, 10067.8, 10422.4, 10852.2", \ + "10048.6, 10048.6, 10048.6, 10402.4, 10832.1", \ + "10075.2, 10075.2, 10075.2, 10432.7, 10862.8", \ + "10080.2, 10080.2, 10080.2, 10440.5, 10870.9", \ + "10113.4, 10113.4, 10113.4, 10479.7, 10910.8"); + } + fall_transition (inslew_load_5x5__6) { + values ("5388.9, 5388.9, 5388.9, 5551.8, 5775.0", \ + "5381.9, 5381.9, 5381.9, 5544.3, 5767.7", \ + "5412.7, 5412.7, 5412.7, 5577.6, 5800.1", \ + "5436.2, 5436.2, 5436.2, 5602.9, 5824.7", \ + "5486.1, 5486.1, 5486.1, 5656.7, 5877.1"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("13093.0, 13093.0, 13093.0, 13334.0, 13796.0", \ + "13087.8, 13087.8, 13087.8, 13328.8, 13790.8", \ + "13077.5, 13077.5, 13077.5, 13318.5, 13780.5", \ + "13056.9, 13056.9, 13056.9, 13297.9, 13759.9", \ + "13015.6, 13015.6, 13015.6, 13256.6, 13718.6"); + } + rise_transition (inslew_load_5x5__6) { + values ("6755.8, 6755.8, 6755.8, 6949.0, 7332.0", \ + "6755.8, 6755.8, 6755.8, 6949.0, 7332.0", \ + "6755.8, 6755.8, 6755.8, 6949.0, 7332.0", \ + "6755.8, 6755.8, 6755.8, 6949.0, 7332.0", \ + "6755.8, 6755.8, 6755.8, 6949.0, 7332.0"); + } + cell_fall (inslew_load_5x5__6) { + values ("13081.6, 13081.6, 13081.6, 13297.5, 13825.2", \ + "13069.1, 13069.1, 13069.1, 13285.0, 13812.8", \ + "13064.5, 13064.5, 13064.5, 13280.5, 13807.2", \ + "13041.2, 13041.2, 13041.2, 13257.3, 13783.0", \ + "13007.7, 13007.7, 13007.7, 13223.8, 13747.8"); + } + fall_transition (inslew_load_5x5__6) { + values ("7310.8, 7310.8, 7310.8, 7479.0, 7786.8", \ + "7310.0, 7310.0, 7310.0, 7478.1, 7785.9", \ + "7320.1, 7320.1, 7320.1, 7488.3, 7796.5", \ + "7328.1, 7328.1, 7328.1, 7496.4, 7805.0", \ + "7343.6, 7343.6, 7343.6, 7511.9, 7821.1"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("9778.6, 9778.6, 9778.6, 10030.5, 10514.2", \ + "9786.5, 9786.5, 9786.5, 10038.2, 10521.9", \ + "9794.3, 9794.3, 9794.3, 10045.8, 10529.6", \ + "9809.9, 9809.9, 9809.9, 10061.4, 10545.1", \ + "9843.1, 9843.1, 9843.1, 10094.6, 10578.3"); + } + rise_transition (inslew_load_5x5__6) { + values ("4660.3, 4660.3, 4660.3, 4860.4, 5254.3", \ + "4665.6, 4665.6, 4665.6, 4865.7, 5259.6", \ + "4668.5, 4668.5, 4668.5, 4868.6, 5262.4", \ + "4669.6, 4669.6, 4669.6, 4869.7, 5263.6", \ + "4669.8, 4669.8, 4669.8, 4869.9, 5263.7"); + } + cell_fall (inslew_load_5x5__6) { + values ("7854.1, 7854.1, 7854.1, 8071.0, 8390.5", \ + "7866.3, 7866.3, 7866.3, 8083.3, 8402.7", \ + "7881.5, 7881.5, 7881.5, 8098.5, 8417.9", \ + "7889.2, 7889.2, 7889.2, 8106.4, 8425.6", \ + "7907.7, 7907.7, 7907.7, 8125.0, 8444.3"); + } + fall_transition (inslew_load_5x5__6) { + values ("3631.6, 3631.6, 3631.6, 3761.3, 3975.5", \ + "3642.8, 3642.8, 3642.8, 3772.2, 3985.8", \ + "3658.3, 3658.3, 3658.3, 3787.3, 4000.1", \ + "3671.4, 3671.4, 3671.4, 3800.1, 4012.1", \ + "3687.8, 3687.8, 3687.8, 3816.1, 4027.1"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__6) { + values ("75748.9, 75748.9, 75748.9, 77651.7, 81457.4", \ + "81488.0, 81488.0, 81488.0, 81488.0, 81488.0", \ + "81549.3, 81549.3, 81549.3, 81549.3, 81549.3", \ + "81671.7, 81671.7, 81671.7, 81671.7, 81671.7", \ + "76208.5, 76208.5, 76208.5, 78111.3, 81917.0"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("108133.7, 108133.7, 108133.7, 110036.5, 113842.2", \ + "113920.2, 113920.2, 113920.2, 113920.2, 113920.2", \ + "114076.1, 114076.1, 114076.1, 114076.1, 114076.1", \ + "114388.0, 114388.0, 114388.0, 114388.0, 114388.0", \ + "115011.8, 115011.8, 115011.8, 115011.8, 115011.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__6) { + values ("66663.6, 66663.6, 66663.6, 68566.4, 72372.1", \ + "66711.1, 66711.1, 66711.1, 68613.9, 72419.6", \ + "66781.2, 66781.2, 66781.2, 68684.1, 72489.7", \ + "66919.4, 66919.4, 66919.4, 68822.3, 72627.9", \ + "72900.1, 72900.1, 72900.1, 72900.1, 72900.1"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("102074.9, 102074.9, 102074.9, 103977.7, 107783.4", \ + "107841.4, 107841.4, 107841.4, 107841.4, 107841.4", \ + "107957.4, 107957.4, 107957.4, 107957.4, 107957.4", \ + "108189.4, 108189.4, 108189.4, 108189.4, 108189.4", \ + "108653.4, 108653.4, 108653.4, 108653.4, 108653.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__6) { + values ("63032.5, 63032.5, 63032.5, 64935.3, 68741.0", \ + "68763.4, 68763.4, 68763.4, 68763.4, 68763.4", \ + "68808.3, 68808.3, 68808.3, 68808.3, 68808.3", \ + "68898.2, 68898.2, 68898.2, 68898.2, 68898.2", \ + "69077.8, 69077.8, 69077.8, 69077.8, 69077.8"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("58608.9, 58608.9, 58608.9, 60511.7, 64317.4", \ + "58618.2, 58618.2, 58618.2, 60521.0, 64326.7", \ + "58912.1, 58912.1, 58912.1, 60814.9, 64620.6", \ + "59264.7, 59264.7, 59264.7, 61167.5, 64973.2", \ + "59988.8, 59988.8, 59988.8, 61891.7, 65697.4"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__6) { + values ("76762.6, 76762.6, 76762.6, 78665.4, 82471.1", \ + "82501.8, 82501.8, 82501.8, 82501.8, 82501.8", \ + "82563.2, 82563.2, 82563.2, 82563.2, 82563.2", \ + "82686.1, 82686.1, 82686.1, 82686.1, 82686.1", \ + "82931.7, 82931.7, 82931.7, 82931.7, 82931.7"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("80702.3, 80702.3, 80702.3, 82605.1, 86410.8", \ + "80749.7, 80749.7, 80749.7, 82652.5, 86458.2", \ + "80918.3, 80918.3, 80918.3, 82821.1, 86626.8", \ + "81179.8, 81179.8, 81179.8, 83082.7, 86888.3", \ + "81697.8, 81697.8, 81697.8, 83600.6, 87406.3"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__6) { + values ("55081.6, 55081.6, 55081.6, 56984.4, 60790.1", \ + "55144.3, 55144.3, 55144.3, 57047.1, 60852.8", \ + "55226.6, 55226.6, 55226.6, 57129.5, 60935.1", \ + "55365.1, 55365.1, 55365.1, 57267.9, 61073.6", \ + "55630.4, 55630.4, 55630.4, 57533.2, 61338.9"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("46456.9, 46456.9, 46456.9, 48359.7, 52165.4", \ + "46558.4, 46558.4, 46558.4, 48461.2, 52266.9", \ + "46722.0, 46722.0, 46722.0, 48624.8, 52430.5", \ + "46946.8, 46946.8, 46946.8, 48849.6, 52655.3", \ + "47341.9, 47341.9, 47341.9, 49244.7, 53050.4"); + } + } + } + } + + cell (noa2a2a2a24_x1) { + area : 50.40 ; + cell_leakage_power : 13 ; + leakage_power () { + when : "(i0 & i1 & ((!(i2) & ((!(i3) & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!(i4) & !(i5) & !(i6) & !(i7)))) | (!(i3) & !(i4) & !(i5) & !(i6) & !(i7))))" ; + value : 22 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5 & !(i6) & i7))" ; + value : 11 ; + } + leakage_power () { + when : "(!(i7) & i6 & !(i5) & i4 & i3 & !(i2) & i1 & !(i0))" ; + value : 9.5 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & !(i5) & i6 & !(i7)) | (!(i0) & i1 & ((i2 & !(i3) & i4 & !(i5) & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))" ; + value : 9.9 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & !(i5) & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))) | (!(i0) & i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))))" ; + value : 10 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i2) & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))) | (!(i1) & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))) | (i2 & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 24 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7))) | (!(i0) & !(i1) & i2 & !(i3) & !(i4) & i5 & !(i6) & i7))" ; + value : 9.7 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7)))) | (!(i1) & !(i2) & i3 & i4 & !(i5) & i6 & !(i7))))" ; + value : 8.5 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i1) & (i2 ^ i3) & (i4 ^ i5) & i6 & i7))))" ; + value : 26 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7)))) | (!(i0) & ((i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))) | (!(i1) & ((i2 & !(i3) & i4 & !(i5) & i6 & !(i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))))" ; + value : 8.9 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))))))" ; + value : 9.3 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | ((i4 ^ i5) & i6 & i7))) | (!(i2) & ((!(i3) & i6 & i7) | ((i4 ^ i5) & i6 & i7))))) | (!(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))))" ; + value : 25 ; + } + leakage_power () { + when : "((i0 & i1 & ((i2 & ((i3 & (!((i4 | i5)) | (!(i6) & !(i7)))) | (!(i3) & ((i4 & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i4) & ((i5 & (!(i6) | !(i7))) | (!(i5) & (i6 | i7)))))))) | (!(i2) & ((i3 & ((i4 & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i4) & ((i5 & (!(i6) | !(i7))) | (!(i5) & (i6 | i7)))))) | (!(i3) & ((i4 & (i5 | i6 | i7)) | (i5 & (i6 | i7)) | (i6 & i7))))))) | (i2 & i3 & (!((i4 | i5)) | (!(i6) & !(i7)))) | (i4 & i5 & !(i6) & !(i7)))" ; + value : 23 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i1) & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7))))))" ; + value : 7.5 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))))))" ; + value : 7.9 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & !(i3) & !(i4) & i5 & !(i6) & i7))))" ; + value : 8.3 ; + } + leakage_power () { + when : "((!((i0 | i1)) & ((!((i2 | i3)) & i6 & i7) | (i4 & i5 & i6 & i7))) | (i2 & i3 & i4 & i5 & i6 & i7))" ; + value : 27 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7))))))))" ; + value : 6.6 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))))" ; + value : 6.9 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.6 ; + } + pin (i7) { + direction : input ; + capacitance : 846.52 ; + } + pin (i6) { + direction : input ; + capacitance : 845.97 ; + } + pin (i5) { + direction : input ; + capacitance : 843.97 ; + } + pin (i4) { + direction : input ; + capacitance : 843.97 ; + } + pin (i3) { + direction : input ; + capacitance : 843.97 ; + } + pin (i2) { + direction : input ; + capacitance : 845.47 ; + } + pin (i1) { + direction : input ; + capacitance : 846.52 ; + } + pin (i0) { + direction : input ; + capacitance : 846.52 ; + } + pin (nq) { + function : "((((((((((((((((((!(i6) & !(i5)) & !(i2)) & !(i0)) | (((!(i6) & !(i5)) & !(i2)) & !(i1))) | (((!(i6) & !(i5)) & !(i3)) & !(i0))) | (((!(i6) & !(i5)) & !(i3)) & !(i1))) | (((!(i6) & !(i4)) & !(i2)) & !(i0))) | (((!(i6) & !(i4)) & !(i2)) & !(i1))) | (((!(i6) & !(i4)) & !(i3)) & !(i0))) | (((!(i6) & !(i4)) & !(i3)) & !(i1))) | (((!(i7) & !(i5)) & !(i2)) & !(i0))) | (((!(i7) & !(i5)) & !(i2)) & !(i1))) | (((!(i7) & !(i5)) & !(i3)) & !(i0))) | (((!(i7) & !(i5)) & !(i3)) & !(i1))) | (((!(i7) & !(i4)) & !(i2)) & !(i0))) | (((!(i7) & !(i4)) & !(i2)) & !(i1))) | (((!(i7) & !(i4)) & !(i3)) & !(i0))) | (((!(i7) & !(i4)) & !(i3)) & !(i1)))" ; + direction : output ; + capacitance : 205.89 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("19117.0, 19117.0, 19117.0, 20048.1, 22010.2", \ + "19102.0, 19102.0, 19102.0, 20033.2, 21995.4", \ + "19071.9, 19071.9, 19071.9, 20003.4, 21965.7", \ + "19011.8, 19011.8, 19011.8, 19943.7, 21906.4", \ + "18891.6, 18891.6, 18891.6, 19824.5, 21787.8"); + } + rise_transition (inslew_load_5x5__16) { + values ("31018.9, 31018.9, 31018.9, 32906.9, 36682.9", \ + "31018.9, 31018.9, 31018.9, 32906.9, 36682.9", \ + "31018.9, 31018.9, 31018.9, 32906.9, 36682.9", \ + "31018.9, 31018.9, 31018.9, 32906.9, 36682.9", \ + "31018.9, 31018.9, 31018.9, 32906.9, 36682.9"); + } + cell_fall (inslew_load_5x5__16) { + values ("4844.9, 4844.9, 4844.9, 5198.8, 5923.9", \ + "4839.7, 4839.7, 4839.7, 5193.6, 5918.7", \ + "4829.4, 4829.4, 4829.4, 5183.3, 5908.4", \ + "4808.7, 4808.7, 4808.7, 5162.6, 5887.8", \ + "4767.3, 4767.3, 4767.3, 5121.3, 5846.5"); + } + fall_transition (inslew_load_5x5__16) { + values ("5934.3, 5934.3, 5934.3, 6511.6, 7666.3", \ + "5934.3, 5934.3, 5934.3, 6511.6, 7666.3", \ + "5934.3, 5934.3, 5934.3, 6511.6, 7666.3", \ + "5934.3, 5934.3, 5934.3, 6511.6, 7666.3", \ + "5934.8, 5934.8, 5934.8, 6511.9, 7666.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("17826.6, 17826.6, 17826.6, 18766.4, 20736.5", \ + "17811.6, 17811.6, 17811.6, 18751.5, 20721.6", \ + "17781.6, 17781.6, 17781.6, 18721.7, 20692.0", \ + "17721.5, 17721.5, 17721.5, 18662.1, 20632.7", \ + "17601.5, 17601.5, 17601.5, 18542.9, 20514.1"); + } + rise_transition (inslew_load_5x5__16) { + values ("28693.9, 28693.9, 28693.9, 30581.9, 34358.0", \ + "28693.9, 28693.9, 28693.9, 30581.9, 34357.9", \ + "28693.9, 28693.9, 28693.9, 30581.9, 34358.0", \ + "28693.9, 28693.9, 28693.9, 30581.9, 34357.9", \ + "28693.9, 28693.9, 28693.9, 30581.9, 34357.9"); + } + cell_fall (inslew_load_5x5__16) { + values ("4025.7, 4025.7, 4025.7, 4387.5, 5122.6", \ + "4029.1, 4029.1, 4029.1, 4390.9, 5126.2", \ + "4036.3, 4036.3, 4036.3, 4398.0, 5133.1", \ + "4052.6, 4052.6, 4052.6, 4414.4, 5149.5", \ + "4085.9, 4085.9, 4085.9, 4447.8, 5183.1"); + } + fall_transition (inslew_load_5x5__16) { + values ("4733.9, 4733.9, 4733.9, 5321.2, 6496.0", \ + "4737.2, 4737.2, 4737.2, 5324.7, 6499.6", \ + "4738.6, 4738.6, 4738.6, 5325.9, 6500.6", \ + "4738.9, 4738.9, 4738.9, 5326.2, 6501.0", \ + "4739.8, 4739.8, 4739.8, 5326.7, 6501.1"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("14474.9, 14474.9, 14474.9, 15442.0, 17442.2", \ + "14467.9, 14467.9, 14467.9, 15435.2, 17435.6", \ + "14445.2, 14445.2, 14445.2, 15412.6, 17413.1", \ + "14410.9, 14410.9, 14410.9, 15378.9, 17379.8", \ + "14338.2, 14338.2, 14338.2, 15307.0, 17308.6"); + } + rise_transition (inslew_load_5x5__16) { + values ("22821.8, 22821.8, 22821.8, 24733.5, 28557.2", \ + "22834.2, 22834.2, 22834.2, 24746.0, 28569.9", \ + "22840.1, 22840.1, 22840.1, 24752.0, 28575.9", \ + "22865.3, 22865.3, 22865.3, 24777.4, 28601.9", \ + "22888.7, 22888.7, 22888.7, 24801.1, 28626.0"); + } + cell_fall (inslew_load_5x5__16) { + values ("4784.3, 4784.3, 4784.3, 5138.6, 5864.2", \ + "4779.2, 4779.2, 4779.2, 5133.5, 5859.0", \ + "4768.8, 4768.8, 4768.8, 5123.1, 5848.7", \ + "4748.1, 4748.1, 4748.1, 5102.5, 5828.1", \ + "4706.8, 4706.8, 4706.8, 5061.2, 5786.8"); + } + fall_transition (inslew_load_5x5__16) { + values ("5842.4, 5842.4, 5842.4, 6419.7, 7574.4", \ + "5842.4, 5842.4, 5842.4, 6419.7, 7574.4", \ + "5842.4, 5842.4, 5842.4, 6419.7, 7574.4", \ + "5842.4, 5842.4, 5842.4, 6419.7, 7574.4", \ + "5843.0, 5843.0, 5843.0, 6420.1, 7574.5"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("13178.9, 13178.9, 13178.9, 14154.6, 16162.6", \ + "13171.9, 13171.9, 13171.9, 14147.8, 16156.0", \ + "13149.2, 13149.2, 13149.2, 14125.2, 16133.5", \ + "13114.8, 13114.8, 13114.8, 14091.3, 16100.1", \ + "13042.0, 13042.0, 13042.0, 14019.3, 16028.8"); + } + rise_transition (inslew_load_5x5__16) { + values ("20467.9, 20467.9, 20467.9, 22379.4, 26202.8", \ + "20480.1, 20480.1, 20480.1, 22391.8, 26215.4", \ + "20486.0, 20486.0, 20486.0, 22397.6, 26221.4", \ + "20510.8, 20510.8, 20510.8, 22422.8, 26247.1", \ + "20533.7, 20533.7, 20533.7, 22446.1, 26270.9"); + } + cell_fall (inslew_load_5x5__16) { + values ("3964.8, 3964.8, 3964.8, 4327.0, 5062.5", \ + "3968.2, 3968.2, 3968.2, 4330.4, 5066.0", \ + "3975.4, 3975.4, 3975.4, 4337.5, 5073.0", \ + "3991.7, 3991.7, 3991.7, 4353.9, 5089.4", \ + "4024.9, 4024.9, 4024.9, 4387.3, 5123.0"); + } + fall_transition (inslew_load_5x5__16) { + values ("4640.4, 4640.4, 4640.4, 5227.7, 6402.5", \ + "4643.8, 4643.8, 4643.8, 5231.2, 6406.1", \ + "4645.1, 4645.1, 4645.1, 5232.4, 6407.1", \ + "4645.4, 4645.4, 4645.4, 5232.7, 6407.5", \ + "4646.4, 4646.4, 4646.4, 5233.3, 6407.6"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("8219.4, 8219.4, 8219.4, 9226.3, 11266.4", \ + "8234.0, 8234.0, 8234.0, 9241.4, 11282.1", \ + "8249.4, 8249.4, 8249.4, 9257.4, 11298.9", \ + "8228.2, 8228.2, 8228.2, 9235.9, 11277.1", \ + "8232.1, 8232.1, 8232.1, 9241.8, 11285.5"); + } + rise_transition (inslew_load_5x5__16) { + values ("11541.6, 11541.6, 11541.6, 13469.7, 17335.2", \ + "11591.9, 11591.9, 11591.9, 13520.9, 17387.4", \ + "11664.8, 11664.8, 11664.8, 13594.8, 17462.9", \ + "11706.1, 11706.1, 11706.1, 13635.4, 17502.5", \ + "11852.7, 11852.7, 11852.7, 13785.2, 17656.6"); + } + cell_fall (inslew_load_5x5__16) { + values ("3045.5, 3045.5, 3045.5, 3413.7, 4155.0", \ + "3048.6, 3048.6, 3048.6, 3416.9, 4158.4", \ + "3056.2, 3056.2, 3056.2, 3424.3, 4165.6", \ + "3072.4, 3072.4, 3072.4, 3440.6, 4181.9", \ + "3104.7, 3104.7, 3104.7, 3473.5, 4215.3"); + } + fall_transition (inslew_load_5x5__16) { + values ("3229.7, 3229.7, 3229.7, 3816.8, 4991.4", \ + "3232.7, 3232.7, 3232.7, 3820.0, 4994.8", \ + "3234.7, 3234.7, 3234.7, 3821.7, 4996.1", \ + "3234.7, 3234.7, 3234.7, 3821.8, 4996.4", \ + "3238.8, 3238.8, 3238.8, 3824.3, 4997.1"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("9514.6, 9514.6, 9514.6, 10514.9, 12549.6", \ + "9529.6, 9529.6, 9529.6, 10530.3, 12565.5", \ + "9545.6, 9545.6, 9545.6, 10546.8, 12582.7", \ + "9523.9, 9523.9, 9523.9, 10525.0, 12560.6", \ + "9529.6, 9529.6, 9529.6, 10532.3, 12570.0"); + } + rise_transition (inslew_load_5x5__16) { + values ("13916.5, 13916.5, 13916.5, 15848.7, 19719.0", \ + "13967.8, 13967.8, 13967.8, 15900.6, 19771.7", \ + "14041.9, 14041.9, 14041.9, 15975.5, 19847.7", \ + "14082.4, 14082.4, 14082.4, 16015.5, 19887.1", \ + "14232.8, 14232.8, 14232.8, 16168.1, 20043.0"); + } + cell_fall (inslew_load_5x5__16) { + values ("3870.1, 3870.1, 3870.1, 4230.6, 4962.1", \ + "3865.0, 3865.0, 3865.0, 4225.4, 4956.9", \ + "3854.6, 3854.6, 3854.6, 4215.1, 4946.6", \ + "3834.0, 3834.0, 3834.0, 4194.5, 4926.0", \ + "3792.5, 3792.5, 3792.5, 4153.1, 4884.7"); + } + fall_transition (inslew_load_5x5__16) { + values ("4455.4, 4455.4, 4455.4, 5032.7, 6187.4", \ + "4455.4, 4455.4, 4455.4, 5032.7, 6187.4", \ + "4455.4, 4455.4, 4455.4, 5032.7, 6187.4", \ + "4455.4, 4455.4, 4455.4, 5032.7, 6187.4", \ + "4457.4, 4457.4, 4457.4, 5034.0, 6187.9"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("3935.0, 3935.0, 3935.0, 3866.0, 5979.3", \ + "2893.3, 2893.3, 2893.3, 3946.0, 6054.5", \ + "3005.6, 3005.6, 3005.6, 4053.6, 6154.1", \ + "3160.1, 3160.1, 3160.1, 4200.3, 6288.4", \ + "3257.4, 3257.4, 3257.4, 4277.5, 6343.7"); + } + rise_transition (inslew_load_5x5__16) { + values ("3715.5, 3715.5, 3715.5, 3564.0, 7560.9", \ + "1756.3, 1756.3, 1756.3, 3736.0, 7723.8", \ + "2008.3, 2008.3, 2008.3, 3979.2, 7951.5", \ + "2373.5, 2373.5, 2373.5, 4329.6, 8278.3", \ + "2685.1, 2685.1, 2685.1, 4600.1, 8506.6"); + } + cell_fall (inslew_load_5x5__16) { + values ("1653.0, 1653.0, 1653.0, 2030.3, 2780.1", \ + "1655.5, 1655.5, 1655.5, 2033.0, 2783.1", \ + "1664.4, 1664.4, 1664.4, 2041.5, 2790.9", \ + "1679.9, 1679.9, 1679.9, 2057.3, 2807.0", \ + "1691.5, 1691.5, 1691.5, 2081.5, 2838.6"); + } + fall_transition (inslew_load_5x5__16) { + values ("1093.0, 1093.0, 1093.0, 1679.8, 2853.4", \ + "1095.0, 1095.0, 1095.0, 1682.0, 2856.2", \ + "1099.1, 1099.1, 1099.1, 1685.5, 2858.5", \ + "1099.4, 1099.4, 1099.4, 1685.4, 2858.5", \ + "1114.1, 1114.1, 1114.1, 1698.6, 2864.4"); + } + } + timing (maxd_nq_i7_negative_unate) { + related_pin : "i7" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("4129.3, 4129.3, 4129.3, 5184.0, 7284.0", \ + "4208.5, 4208.5, 4208.5, 5260.9, 7357.2", \ + "4315.1, 4315.1, 4315.1, 5363.2, 7453.6", \ + "4460.4, 4460.4, 4460.4, 5501.3, 7583.5", \ + "4532.8, 4532.8, 4532.8, 5562.0, 7632.8"); + } + rise_transition (inslew_load_5x5__16) { + values ("4026.4, 4026.4, 4026.4, 6026.6, 10013.2", \ + "4197.1, 4197.1, 4197.1, 6192.8, 10172.3", \ + "4438.2, 4438.2, 4438.2, 6425.7, 10394.1", \ + "4786.1, 4786.1, 4786.1, 6760.0, 10712.7", \ + "5047.8, 5047.8, 5047.8, 6998.8, 10929.6"); + } + cell_fall (inslew_load_5x5__16) { + values ("2484.6, 2484.6, 2484.6, 2854.4, 3594.9", \ + "2479.5, 2479.5, 2479.5, 2849.3, 3589.8", \ + "2469.2, 2469.2, 2469.2, 2838.9, 3579.5", \ + "2448.5, 2448.5, 2448.5, 2818.3, 3558.9", \ + "2403.4, 2403.4, 2403.4, 2775.4, 3517.3"); + } + fall_transition (inslew_load_5x5__16) { + values ("2353.3, 2353.3, 2353.3, 2930.6, 4085.3", \ + "2353.3, 2353.3, 2353.3, 2930.6, 4085.3", \ + "2353.3, 2353.3, 2353.3, 2930.6, 4085.3", \ + "2353.4, 2353.4, 2353.4, 2930.7, 4085.3", \ + "2364.5, 2364.5, 2364.5, 2938.0, 4088.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__16) { + values ("40009.7, 40009.7, 40009.7, 42583.2, 47730.4", \ + "40098.1, 40098.1, 40098.1, 42671.6, 47818.8", \ + "40274.9, 40274.9, 40274.9, 42848.4, 47995.5", \ + "40628.4, 40628.4, 40628.4, 43202.0, 48349.1", \ + "41335.6, 41335.6, 41335.6, 43909.2, 49056.3"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("24238.3, 24238.3, 24238.3, 26811.8, 31958.9", \ + "24284.0, 24284.0, 24284.0, 26857.5, 32004.6", \ + "24375.4, 24375.4, 24375.4, 26949.0, 32096.1", \ + "24558.2, 24558.2, 24558.2, 27131.8, 32278.9", \ + "24923.9, 24923.9, 24923.9, 27497.5, 32644.6"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__16) { + values ("36815.2, 36815.2, 36815.2, 39388.8, 44535.9", \ + "36878.4, 36878.4, 36878.4, 39451.9, 44599.1", \ + "37004.7, 37004.7, 37004.7, 39578.2, 44725.4", \ + "37257.3, 37257.3, 37257.3, 39830.8, 44978.0", \ + "37762.5, 37762.5, 37762.5, 40336.0, 45483.2"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("18581.8, 18581.8, 18581.8, 21155.3, 26302.4", \ + "18632.2, 18632.2, 18632.2, 21205.7, 26352.9", \ + "18733.0, 18733.0, 18733.0, 21306.5, 26453.7", \ + "18934.6, 18934.6, 18934.6, 21508.1, 26655.3", \ + "19337.8, 19337.8, 19337.8, 21911.4, 27058.5"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__16) { + values ("28570.7, 28570.7, 28570.7, 31144.2, 36291.4", \ + "28656.0, 28656.0, 28656.0, 31229.5, 36376.7", \ + "28826.6, 28826.6, 28826.6, 31400.2, 36547.3", \ + "29167.8, 29167.8, 29167.8, 31741.4, 36888.5", \ + "29850.3, 29850.3, 29850.3, 32423.9, 37571.0"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("23811.8, 23811.8, 23811.8, 26385.3, 31532.5", \ + "23840.5, 23840.5, 23840.5, 26414.1, 31561.2", \ + "23898.0, 23898.0, 23898.0, 26471.6, 31618.7", \ + "24013.0, 24013.0, 24013.0, 26586.6, 31733.7", \ + "24243.0, 24243.0, 24243.0, 26816.6, 31963.7"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__16) { + values ("25379.9, 25379.9, 25379.9, 27953.5, 33100.6", \ + "25443.7, 25443.7, 25443.7, 28017.3, 33164.4", \ + "25571.3, 25571.3, 25571.3, 28144.9, 33292.0", \ + "25826.4, 25826.4, 25826.4, 28400.0, 33547.1", \ + "26336.7, 26336.7, 26336.7, 28910.2, 34057.3"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("18154.6, 18154.6, 18154.6, 20728.2, 25875.3", \ + "18187.3, 18187.3, 18187.3, 20760.9, 25908.0", \ + "18252.9, 18252.9, 18252.9, 20826.4, 25973.5", \ + "18383.9, 18383.9, 18383.9, 20957.4, 26104.6", \ + "18645.9, 18645.9, 18645.9, 21219.5, 26366.6"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__16) { + values ("13722.6, 13722.6, 13722.6, 16296.2, 21443.3", \ + "13784.8, 13784.8, 13784.8, 16358.4, 21505.5", \ + "13909.2, 13909.2, 13909.2, 16482.7, 21629.9", \ + "14157.9, 14157.9, 14157.9, 16731.4, 21878.6", \ + "14655.3, 14655.3, 14655.3, 17228.9, 22376.0"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("11962.3, 11962.3, 11962.3, 14535.9, 19683.0", \ + "11985.6, 11985.6, 11985.6, 14559.2, 19706.3", \ + "12032.2, 12032.2, 12032.2, 14605.8, 19752.9", \ + "12125.4, 12125.4, 12125.4, 14698.9, 19846.0", \ + "12311.7, 12311.7, 12311.7, 14885.2, 20032.4"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__16) { + values ("16910.8, 16910.8, 16910.8, 19484.4, 24631.5", \ + "16992.0, 16992.0, 16992.0, 19565.5, 24712.7", \ + "17154.3, 17154.3, 17154.3, 19727.8, 24875.0", \ + "17478.9, 17478.9, 17478.9, 20052.5, 25199.6", \ + "18128.1, 18128.1, 18128.1, 20701.7, 25848.8"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("17620.0, 17620.0, 17620.0, 20193.5, 25340.7", \ + "17639.7, 17639.7, 17639.7, 20213.3, 25360.4", \ + "17679.3, 17679.3, 17679.3, 20252.8, 25400.0", \ + "17758.3, 17758.3, 17758.3, 20331.9, 25479.0", \ + "17916.4, 17916.4, 17916.4, 20490.0, 25637.1"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__16) { + values ("2638.8, 2638.8, 2638.8, 5212.4, 10359.5", \ + "2699.1, 2699.1, 2699.1, 5272.7, 10419.8", \ + "2819.7, 2819.7, 2819.7, 5393.3, 10540.4", \ + "3061.0, 3061.0, 3061.0, 5634.5, 10781.6", \ + "3543.4, 3543.4, 3543.4, 6116.9, 11264.1"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("2585.9, 2585.9, 2585.9, 5159.5, 10306.6", \ + "2603.2, 2603.2, 2603.2, 5176.8, 10323.9", \ + "2637.8, 2637.8, 2637.8, 5211.4, 10358.5", \ + "2707.0, 2707.0, 2707.0, 5280.6, 10427.7", \ + "2845.4, 2845.4, 2845.4, 5418.9, 10566.1"); + } + } + internal_power (energy_neg_nq_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__16) { + values ("5824.4, 5824.4, 5824.4, 8397.9, 13545.0", \ + "5901.0, 5901.0, 5901.0, 8474.5, 13621.7", \ + "6054.2, 6054.2, 6054.2, 8627.8, 13774.9", \ + "6360.7, 6360.7, 6360.7, 8934.2, 14081.3", \ + "6973.6, 6973.6, 6973.6, 9547.1, 14694.3"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("8244.3, 8244.3, 8244.3, 10817.9, 15965.0", \ + "8258.9, 8258.9, 8258.9, 10832.4, 15979.6", \ + "8288.0, 8288.0, 8288.0, 10861.5, 16008.6", \ + "8346.1, 8346.1, 8346.1, 10919.7, 16066.8", \ + "8462.5, 8462.5, 8462.5, 11036.0, 16183.2"); + } + } + } + } + + cell (xr2_x4) { + area : 43.20 ; + cell_leakage_power : 12 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 10 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 13 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 14 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 11 ; + } + pin (i1) { + direction : input ; + capacitance : 1270.79 ; + } + pin (i0) { + direction : input ; + capacitance : 1268.49 ; + } + pin (q) { + function : "(i0 ^ i1)" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("9135.4, 9135.4, 9135.4, 9389.6, 9872.1", \ + "9130.3, 9130.3, 9130.3, 9384.5, 9867.0", \ + "9119.9, 9119.9, 9119.9, 9374.1, 9856.6", \ + "9099.3, 9099.3, 9099.3, 9353.5, 9836.0", \ + "9058.2, 9058.2, 9058.2, 9312.4, 9794.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("4521.6, 4521.6, 4521.6, 4721.4, 5115.3", \ + "4521.6, 4521.6, 4521.6, 4721.4, 5115.3", \ + "4521.6, 4521.6, 4521.6, 4721.4, 5115.3", \ + "4521.6, 4521.6, 4521.6, 4721.4, 5115.3", \ + "4521.7, 4521.7, 4521.7, 4721.5, 5115.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("10465.6, 10465.6, 10465.6, 10774.4, 11197.6", \ + "10460.3, 10460.3, 10460.3, 10769.1, 11192.3", \ + "10449.4, 10449.4, 10449.4, 10758.3, 11181.4", \ + "10428.0, 10428.0, 10428.0, 10736.9, 11160.0", \ + "10385.2, 10385.2, 10385.2, 10694.0, 11117.2"); + } + fall_transition (inslew_load_5x5__3) { + values ("5014.4, 5014.4, 5014.4, 5151.7, 5386.0", \ + "5014.4, 5014.4, 5014.4, 5151.7, 5386.0", \ + "5014.5, 5014.5, 5014.5, 5151.8, 5386.0", \ + "5014.5, 5014.5, 5014.5, 5151.8, 5386.0", \ + "5014.4, 5014.4, 5014.4, 5151.7, 5386.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("7052.0, 7052.0, 7052.0, 7315.3, 7802.8", \ + "7046.8, 7046.8, 7046.8, 7310.1, 7797.6", \ + "7036.5, 7036.5, 7036.5, 7299.8, 7787.3", \ + "7015.9, 7015.9, 7015.9, 7279.2, 7766.7", \ + "6974.7, 6974.7, 6974.7, 7238.0, 7725.5"); + } + rise_transition (inslew_load_5x5__3) { + values ("3108.7, 3108.7, 3108.7, 3326.1, 3743.9", \ + "3108.7, 3108.7, 3108.7, 3326.1, 3743.9", \ + "3108.7, 3108.7, 3108.7, 3326.1, 3743.9", \ + "3108.7, 3108.7, 3108.7, 3326.1, 3743.9", \ + "3109.0, 3109.0, 3109.0, 3326.3, 3744.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("7899.9, 7899.9, 7899.9, 8115.7, 8435.9", \ + "7908.7, 7908.7, 7908.7, 8124.6, 8444.7", \ + "7913.9, 7913.9, 7913.9, 8129.8, 8449.9", \ + "7931.4, 7931.4, 7931.4, 8147.3, 8467.4", \ + "7955.0, 7955.0, 7955.0, 8171.0, 8491.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("3503.9, 3503.9, 3503.9, 3636.7, 3857.2", \ + "3511.1, 3511.1, 3511.1, 3643.7, 3863.7", \ + "3516.7, 3516.7, 3516.7, 3649.2, 3869.0", \ + "3528.4, 3528.4, 3528.4, 3660.4, 3879.6", \ + "3534.8, 3534.8, 3534.8, 3666.7, 3885.5"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("11179.3, 11179.3, 11179.3, 11444.1, 11938.7", \ + "11188.1, 11188.1, 11188.1, 11452.9, 11947.5", \ + "11205.7, 11205.7, 11205.7, 11470.5, 11965.1", \ + "11240.9, 11240.9, 11240.9, 11505.7, 12000.3", \ + "11311.4, 11311.4, 11311.4, 11576.2, 12070.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("2932.9, 2932.9, 2932.9, 3152.9, 3576.0", \ + "2932.9, 2932.9, 2932.9, 3152.9, 3576.0", \ + "2932.9, 2932.9, 2932.9, 3152.9, 3576.0", \ + "2932.9, 2932.9, 2932.9, 3152.9, 3576.0", \ + "2933.1, 2933.1, 2933.1, 3153.1, 3576.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("10151.3, 10151.3, 10151.3, 10363.4, 10776.1", \ + "10160.1, 10160.1, 10160.1, 10372.2, 10784.9", \ + "10177.7, 10177.7, 10177.7, 10389.8, 10802.5", \ + "10212.9, 10212.9, 10212.9, 10425.0, 10837.7", \ + "10282.6, 10282.6, 10282.6, 10494.7, 10907.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("3079.8, 3079.8, 3079.8, 3236.3, 3559.3", \ + "3079.8, 3079.8, 3079.8, 3236.3, 3559.3", \ + "3079.8, 3079.8, 3079.8, 3236.3, 3559.3", \ + "3079.8, 3079.8, 3079.8, 3236.3, 3559.3", \ + "3080.0, 3080.0, 3080.0, 3236.5, 3559.5"); + } + } + timing (maxd_q_i1_negative_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("13584.9, 13584.9, 13584.9, 13839.4, 14322.3", \ + "13593.7, 13593.7, 13593.7, 13848.2, 14331.1", \ + "13611.3, 13611.3, 13611.3, 13865.8, 14348.7", \ + "13646.5, 13646.5, 13646.5, 13901.0, 14383.9", \ + "13717.1, 13717.1, 13717.1, 13971.7, 14454.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("4430.4, 4430.4, 4430.4, 4631.0, 5025.9", \ + "4430.4, 4430.4, 4430.4, 4631.0, 5025.9", \ + "4430.4, 4430.4, 4430.4, 4631.0, 5025.9", \ + "4430.4, 4430.4, 4430.4, 4631.0, 5025.9", \ + "4430.7, 4430.7, 4430.7, 4631.3, 5026.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("12441.8, 12441.8, 12441.8, 12664.9, 13083.8", \ + "12450.6, 12450.6, 12450.6, 12673.7, 13092.6", \ + "12468.2, 12468.2, 12468.2, 12691.3, 13110.2", \ + "12503.4, 12503.4, 12503.4, 12726.5, 13145.4", \ + "12571.6, 12571.6, 12571.6, 12794.7, 13213.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("4680.0, 4680.0, 4680.0, 4787.3, 5033.4", \ + "4680.0, 4680.0, 4680.0, 4787.3, 5033.4", \ + "4680.0, 4680.0, 4680.0, 4787.3, 5033.4", \ + "4680.0, 4680.0, 4680.0, 4787.3, 5033.4", \ + "4680.0, 4680.0, 4680.0, 4787.4, 5033.5"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("69524.8, 69524.8, 69524.8, 71420.6, 75212.3", \ + "75258.0, 75258.0, 75258.0, 75258.0, 75258.0", \ + "75349.4, 75349.4, 75349.4, 75349.4, 75349.4", \ + "75532.3, 75532.3, 75532.3, 75532.3, 75532.3", \ + "70210.8, 70210.8, 70210.8, 72106.6, 75898.3"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("70721.4, 70721.4, 70721.4, 72617.3, 76408.9", \ + "76497.4, 76497.4, 76497.4, 76497.4, 76497.4", \ + "70986.8, 70986.8, 70986.8, 72882.6, 76674.3", \ + "77027.9, 77027.9, 77027.9, 77027.9, 77027.9", \ + "77735.1, 77735.1, 77735.1, 77735.1, 77735.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("52719.9, 52719.9, 52719.9, 54615.7, 58407.4", \ + "58436.1, 58436.1, 58436.1, 58436.1, 58436.1", \ + "58493.6, 58493.6, 58493.6, 58493.6, 58493.6", \ + "58608.7, 58608.7, 58608.7, 58608.7, 58608.7", \ + "53152.6, 53152.6, 53152.6, 55048.4, 58840.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("49176.8, 49176.8, 49176.8, 51072.7, 54864.3", \ + "49302.9, 49302.9, 49302.9, 51198.8, 54990.4", \ + "49505.7, 49505.7, 49505.7, 51401.6, 55193.2", \ + "49913.0, 49913.0, 49913.0, 51808.8, 55600.5", \ + "50632.2, 50632.2, 50632.2, 52528.0, 56319.7"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("61005.4, 61005.4, 61005.4, 62901.2, 66692.9", \ + "66737.0, 66737.0, 66737.0, 66737.0, 66737.0", \ + "66825.1, 66825.1, 66825.1, 66825.1, 66825.1", \ + "67001.5, 67001.5, 67001.5, 67001.5, 67001.5", \ + "61668.2, 61668.2, 61668.2, 63564.0, 67355.7"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("58077.8, 58077.8, 58077.8, 59973.6, 63765.3", \ + "63788.2, 63788.2, 63788.2, 63788.2, 63788.2", \ + "63834.0, 63834.0, 63834.0, 63834.0, 63834.0", \ + "63925.7, 63925.7, 63925.7, 63925.7, 63925.7", \ + "58433.9, 58433.9, 58433.9, 60329.7, 64121.4"); + } + } + internal_power (energy_neg_q_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("79926.6, 79926.6, 79926.6, 81822.5, 85614.1", \ + "85658.2, 85658.2, 85658.2, 85658.2, 85658.2", \ + "85746.4, 85746.4, 85746.4, 85746.4, 85746.4", \ + "85922.8, 85922.8, 85922.8, 85922.8, 85922.8", \ + "80590.1, 80590.1, 80590.1, 82485.9, 86277.6"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("79368.1, 79368.1, 79368.1, 81264.0, 85055.7", \ + "85078.6, 85078.6, 85078.6, 85078.6, 85078.6", \ + "85124.4, 85124.4, 85124.4, 85124.4, 85124.4", \ + "85216.1, 85216.1, 85216.1, 85216.1, 85216.1", \ + "79723.0, 79723.0, 79723.0, 81618.8, 85410.5"); + } + } + } + } + + cell (na2_x4) { + area : 25.20 ; + cell_leakage_power : 8 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 6.4 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 8.8 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 9.2 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 7.8 ; + } + pin (i1) { + direction : input ; + capacitance : 568.63 ; + } + pin (i0) { + direction : input ; + capacitance : 566.63 ; + } + pin (nq) { + function : "(!(i0) | !(i1))" ; + direction : output ; + capacitance : 148.45 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("10048.5, 10048.5, 10048.5, 10327.5, 10835.9", \ + "10057.3, 10057.3, 10057.3, 10336.3, 10844.7", \ + "10074.9, 10074.9, 10074.9, 10353.9, 10862.3", \ + "10110.1, 10110.1, 10110.1, 10389.1, 10897.5", \ + "10181.0, 10181.0, 10181.0, 10460.0, 10968.3"); + } + rise_transition (inslew_load_5x5__13) { + values ("2280.1, 2280.1, 2280.1, 2517.3, 2952.1", \ + "2280.1, 2280.1, 2280.1, 2517.3, 2952.1", \ + "2280.1, 2280.1, 2280.1, 2517.3, 2952.1", \ + "2280.1, 2280.1, 2280.1, 2517.3, 2952.1", \ + "2280.8, 2280.8, 2280.8, 2518.0, 2952.8"); + } + cell_fall (inslew_load_5x5__13) { + values ("9556.8, 9556.8, 9556.8, 9763.6, 10194.3", \ + "9560.4, 9560.4, 9560.4, 9767.2, 10197.9", \ + "9568.3, 9568.3, 9568.3, 9775.2, 10205.9", \ + "9584.4, 9584.4, 9584.4, 9791.3, 10222.0", \ + "9609.2, 9609.2, 9609.2, 9816.1, 10246.7"); + } + fall_transition (inslew_load_5x5__13) { + values ("2928.5, 2928.5, 2928.5, 3088.9, 3406.3", \ + "2928.5, 2928.5, 2928.5, 3088.9, 3406.3", \ + "2928.5, 2928.5, 2928.5, 3089.0, 3406.3", \ + "2928.5, 2928.5, 2928.5, 3089.0, 3406.3", \ + "2928.7, 2928.7, 2928.7, 3089.2, 3406.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("11634.2, 11634.2, 11634.2, 11896.6, 12395.7", \ + "11643.0, 11643.0, 11643.0, 11905.4, 12404.5", \ + "11660.6, 11660.6, 11660.6, 11923.0, 12422.1", \ + "11695.7, 11695.7, 11695.7, 11958.1, 12457.2", \ + "11766.0, 11766.0, 11766.0, 12028.5, 12527.6"); + } + rise_transition (inslew_load_5x5__13) { + values ("2699.0, 2699.0, 2699.0, 2920.4, 3343.9", \ + "2699.0, 2699.0, 2699.0, 2920.4, 3343.9", \ + "2699.0, 2699.0, 2699.0, 2920.4, 3343.9", \ + "2699.0, 2699.0, 2699.0, 2920.4, 3343.9", \ + "2699.1, 2699.1, 2699.1, 2920.6, 3344.0"); + } + cell_fall (inslew_load_5x5__13) { + values ("10613.4, 10613.4, 10613.4, 10820.2, 11242.3", \ + "10608.2, 10608.2, 10608.2, 10815.0, 11237.1", \ + "10597.9, 10597.9, 10597.9, 10804.7, 11226.8", \ + "10577.2, 10577.2, 10577.2, 10784.0, 11206.1", \ + "10535.7, 10535.7, 10535.7, 10742.5, 11164.5"); + } + fall_transition (inslew_load_5x5__13) { + values ("2961.9, 2961.9, 2961.9, 3120.7, 3438.5", \ + "2961.9, 2961.9, 2961.9, 3120.7, 3438.5", \ + "2961.9, 2961.9, 2961.9, 3120.7, 3438.5", \ + "2961.9, 2961.9, 2961.9, 3120.7, 3438.5", \ + "2962.3, 2962.3, 2962.3, 3121.2, 3439.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__13) { + values ("49731.2, 49731.2, 49731.2, 51586.8, 55297.9", \ + "55359.4, 55359.4, 55359.4, 55359.4, 55359.4", \ + "55482.4, 55482.4, 55482.4, 55482.4, 55482.4", \ + "55728.5, 55728.5, 55728.5, 55728.5, 55728.5", \ + "50657.9, 50657.9, 50657.9, 52513.5, 56224.6"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("49209.1, 49209.1, 49209.1, 51064.7, 54775.9", \ + "54797.9, 54797.9, 54797.9, 54797.9, 54797.9", \ + "49272.3, 49272.3, 49272.3, 51127.9, 54839.1", \ + "54918.5, 54918.5, 54918.5, 54918.5, 54918.5", \ + "49533.3, 49533.3, 49533.3, 51388.9, 55100.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__13) { + values ("55779.2, 55779.2, 55779.2, 57634.8, 61346.0", \ + "61424.8, 61424.8, 61424.8, 61424.8, 61424.8", \ + "61582.4, 61582.4, 61582.4, 61582.4, 61582.4", \ + "61897.6, 61897.6, 61897.6, 61897.6, 61897.6", \ + "56962.3, 56962.3, 56962.3, 58817.9, 62529.1"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("56157.8, 56157.8, 56157.8, 58013.4, 61724.6", \ + "61741.1, 61741.1, 61741.1, 61741.1, 61741.1", \ + "61774.3, 61774.3, 61774.3, 61774.3, 61774.3", \ + "61840.9, 61840.9, 61840.9, 61840.9, 61840.9", \ + "56420.2, 56420.2, 56420.2, 58275.7, 61986.9"); + } + } + } + } + + cell (tie_x0) { + area : 7.20 ; + cell_leakage_power : 0 ; + } + + cell (on12_x1) { + area : 18.00 ; + cell_leakage_power : 3.2 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 3.2 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 3.1 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 2.2 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 4.1 ; + } + pin (i1) { + direction : input ; + capacitance : 439.40 ; + } + pin (i0) { + direction : input ; + capacitance : 572.98 ; + } + pin (q) { + function : "(i1 | !(i0))" ; + direction : output ; + capacitance : 88.12 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__17) { + values ("5490.8, 5490.8, 5490.8, 5860.1, 6560.7", \ + "5499.6, 5499.6, 5499.6, 5868.9, 6569.5", \ + "5517.1, 5517.1, 5517.1, 5886.4, 6587.0", \ + "5552.3, 5552.3, 5552.3, 5921.6, 6622.2", \ + "5618.3, 5618.3, 5618.3, 5988.2, 6689.7"); + } + rise_transition (inslew_load_5x5__17) { + values ("2443.4, 2443.4, 2443.4, 2891.2, 3767.6", \ + "2443.4, 2443.4, 2443.4, 2891.2, 3767.6", \ + "2443.4, 2443.4, 2443.4, 2891.2, 3767.6", \ + "2443.5, 2443.5, 2443.5, 2891.3, 3767.7", \ + "2446.2, 2446.2, 2446.2, 2894.1, 3770.4"); + } + cell_fall (inslew_load_5x5__17) { + values ("4696.0, 4696.0, 4696.0, 4894.2, 5274.5", \ + "4704.8, 4704.8, 4704.8, 4903.0, 5283.3", \ + "4722.4, 4722.4, 4722.4, 4920.6, 5300.9", \ + "4757.6, 4757.6, 4757.6, 4955.8, 5336.1", \ + "4826.9, 4826.9, 4826.9, 5025.1, 5405.5"); + } + fall_transition (inslew_load_5x5__17) { + values ("2345.8, 2345.8, 2345.8, 2592.4, 3079.1", \ + "2345.8, 2345.8, 2345.8, 2592.4, 3079.1", \ + "2345.8, 2345.8, 2345.8, 2592.4, 3079.1", \ + "2345.8, 2345.8, 2345.8, 2592.4, 3079.1", \ + "2346.5, 2346.5, 2346.5, 2593.1, 3079.8"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("1959.4, 1959.4, 1959.4, 2295.0, 2961.2", \ + "1968.2, 1968.2, 1968.2, 2303.8, 2970.0", \ + "1985.8, 1985.8, 1985.8, 2321.4, 2987.5", \ + "2020.8, 2020.8, 2020.8, 2356.5, 3022.7", \ + "2078.3, 2078.3, 2078.3, 2420.9, 3091.7"); + } + rise_transition (inslew_load_5x5__17) { + values ("853.6, 853.6, 853.6, 1301.8, 2198.0", \ + "853.6, 853.6, 853.6, 1301.8, 2198.0", \ + "853.6, 853.6, 853.6, 1301.8, 2198.0", \ + "853.8, 853.8, 853.8, 1301.9, 2198.0", \ + "862.3, 862.3, 862.3, 1310.3, 2202.6"); + } + cell_fall (inslew_load_5x5__17) { + values ("941.0, 941.0, 941.0, 1103.1, 1424.5", \ + "943.5, 943.5, 943.5, 1105.7, 1427.4", \ + "952.3, 952.3, 952.3, 1114.3, 1435.4", \ + "960.8, 960.8, 960.8, 1126.6, 1450.5", \ + "916.2, 916.2, 916.2, 1107.4, 1459.2"); + } + fall_transition (inslew_load_5x5__17) { + values ("565.9, 565.9, 565.9, 817.1, 1318.8", \ + "567.8, 567.8, 567.8, 819.1, 1321.3", \ + "572.1, 572.1, 572.1, 822.9, 1323.9", \ + "576.5, 576.5, 576.5, 827.1, 1326.2", \ + "600.1, 600.1, 600.1, 858.5, 1358.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__17) { + values ("15222.5, 15222.5, 15222.5, 16324.0, 18526.9", \ + "18549.8, 18549.8, 18549.8, 18549.8, 18549.8", \ + "18595.6, 18595.6, 18595.6, 18595.6, 18595.6", \ + "15383.4, 15383.4, 15383.4, 16484.9, 18687.9", \ + "15593.9, 15593.9, 15593.9, 16695.3, 18898.3"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("15432.0, 15432.0, 15432.0, 16533.5, 18736.4", \ + "18780.5, 18780.5, 18780.5, 18780.5, 18780.5", \ + "18868.7, 18868.7, 18868.7, 18868.7, 18868.7", \ + "19045.0, 19045.0, 19045.0, 19045.0, 19045.0", \ + "16094.5, 16094.5, 16094.5, 17195.9, 19398.9"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__17) { + values ("1135.4, 1135.4, 1135.4, 2236.9, 4439.9", \ + "1196.9, 1196.9, 1196.9, 2298.4, 4501.4", \ + "1319.9, 1319.9, 1319.9, 2421.4, 4624.4", \ + "1566.0, 1566.0, 1566.0, 2667.4, 4870.4", \ + "2058.0, 2058.0, 2058.0, 3159.5, 5362.4"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("1148.6, 1148.6, 1148.6, 2250.1, 4453.0", \ + "1168.2, 1168.2, 1168.2, 2269.6, 4472.6", \ + "1207.3, 1207.3, 1207.3, 2308.8, 4511.7", \ + "1285.6, 1285.6, 1285.6, 2387.1, 4590.0", \ + "1442.1, 1442.1, 1442.1, 2543.6, 4746.5"); + } + } + } + } + + cell (on12_x4) { + area : 28.80 ; + cell_leakage_power : 7.5 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 7.5 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 6.9 ; + } + leakage_power () { + when : "!(i0)" ; + value : 8.2 ; + } + pin (i1) { + direction : input ; + capacitance : 578.67 ; + } + pin (i0) { + direction : input ; + capacitance : 440.00 ; + } + pin (q) { + function : "(i1 | !(i0))" ; + direction : output ; + capacitance : 151.95 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("7378.9, 7378.9, 7378.9, 7645.1, 8143.7", \ + "7387.7, 7387.7, 7387.7, 7653.9, 8152.5", \ + "7405.3, 7405.3, 7405.3, 7671.5, 8170.1", \ + "7440.5, 7440.5, 7440.5, 7706.7, 8205.3", \ + "7511.0, 7511.0, 7511.0, 7777.2, 8275.7"); + } + rise_transition (inslew_load_5x5__14) { + values ("2900.8, 2900.8, 2900.8, 3123.0, 3548.6", \ + "2900.8, 2900.8, 2900.8, 3123.0, 3548.6", \ + "2900.8, 2900.8, 2900.8, 3123.0, 3548.6", \ + "2900.8, 2900.8, 2900.8, 3123.0, 3548.6", \ + "2900.9, 2900.9, 2900.9, 3123.1, 3548.8"); + } + cell_fall (inslew_load_5x5__14) { + values ("10670.2, 10670.2, 10670.2, 11013.1, 11438.2", \ + "10664.8, 10664.8, 10664.8, 11007.7, 11432.8", \ + "10654.1, 10654.1, 10654.1, 10997.0, 11422.1", \ + "10632.7, 10632.7, 10632.7, 10975.6, 11400.7", \ + "10589.8, 10589.8, 10589.8, 10932.7, 11357.8"); + } + fall_transition (inslew_load_5x5__14) { + values ("5306.5, 5306.5, 5306.5, 5457.3, 5679.7", \ + "5306.5, 5306.5, 5306.5, 5457.3, 5679.7", \ + "5306.5, 5306.5, 5306.5, 5457.3, 5679.7", \ + "5306.5, 5306.5, 5306.5, 5457.3, 5679.7", \ + "5306.5, 5306.5, 5306.5, 5457.3, 5679.7"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__14) { + values ("10480.2, 10480.2, 10480.2, 10759.9, 11276.2", \ + "10489.0, 10489.0, 10489.0, 10768.7, 11285.0", \ + "10506.6, 10506.6, 10506.6, 10786.3, 11302.6", \ + "10541.7, 10541.7, 10541.7, 10821.5, 11337.8", \ + "10612.4, 10612.4, 10612.4, 10892.1, 11408.4"); + } + rise_transition (inslew_load_5x5__14) { + values ("2428.3, 2428.3, 2428.3, 2665.7, 3105.3", \ + "2428.3, 2428.3, 2428.3, 2665.7, 3105.3", \ + "2428.3, 2428.3, 2428.3, 2665.7, 3105.3", \ + "2428.3, 2428.3, 2428.3, 2665.8, 3105.4", \ + "2428.9, 2428.9, 2428.9, 2666.3, 3105.9"); + } + cell_fall (inslew_load_5x5__14) { + values ("10727.7, 10727.7, 10727.7, 10944.9, 11355.0", \ + "10736.5, 10736.5, 10736.5, 10953.7, 11363.8", \ + "10754.1, 10754.1, 10754.1, 10971.3, 11381.4", \ + "10789.3, 10789.3, 10789.3, 11006.5, 11416.6", \ + "10856.3, 10856.3, 10856.3, 11073.6, 11483.7"); + } + fall_transition (inslew_load_5x5__14) { + values ("3990.4, 3990.4, 3990.4, 4109.9, 4383.6", \ + "3990.4, 3990.4, 3990.4, 4109.9, 4383.6", \ + "3990.4, 3990.4, 3990.4, 4109.9, 4383.6", \ + "3990.4, 3990.4, 3990.4, 4109.9, 4383.6", \ + "3990.6, 3990.6, 3990.6, 4110.0, 4383.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__14) { + values ("49263.6, 49263.6, 49263.6, 51163.0, 54961.6", \ + "54999.9, 54999.9, 54999.9, 54999.9, 54999.9", \ + "55076.4, 55076.4, 55076.4, 55076.4, 55076.4", \ + "55229.4, 55229.4, 55229.4, 55229.4, 55229.4", \ + "49838.2, 49838.2, 49838.2, 51737.5, 55536.2"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("63855.5, 63855.5, 63855.5, 65754.9, 69553.5", \ + "69597.0, 69597.0, 69597.0, 69597.0, 69597.0", \ + "69684.0, 69684.0, 69684.0, 69684.0, 69684.0", \ + "69858.0, 69858.0, 69858.0, 69858.0, 69858.0", \ + "70205.9, 70205.9, 70205.9, 70205.9, 70205.9"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__14) { + values ("52631.6, 52631.6, 52631.6, 54530.9, 58329.6", \ + "58373.7, 58373.7, 58373.7, 58373.7, 58373.7", \ + "58461.9, 58461.9, 58461.9, 58461.9, 58461.9", \ + "52940.6, 52940.6, 52940.6, 54839.9, 58638.6", \ + "53296.8, 53296.8, 53296.8, 55196.1, 58994.8"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("56190.9, 56190.9, 56190.9, 58090.2, 61888.9", \ + "61911.8, 61911.8, 61911.8, 61911.8, 61911.8", \ + "61957.6, 61957.6, 61957.6, 61957.6, 61957.6", \ + "62049.6, 62049.6, 62049.6, 62049.6, 62049.6", \ + "56552.5, 56552.5, 56552.5, 58451.8, 62250.5"); + } + } + } + } + + cell (a3_x4) { + area : 25.20 ; + cell_leakage_power : 5.7 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 8.1 ; + } + leakage_power () { + when : "(i0 & (i1 ^ i2))" ; + value : 5.7 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0))" ; + value : 6 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2)) | (!(i0) & (i1 ^ i2)))" ; + value : 4.7 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 3.8 ; + } + pin (i2) { + direction : input ; + capacitance : 569.33 ; + } + pin (i1) { + direction : input ; + capacitance : 569.93 ; + } + pin (i0) { + direction : input ; + capacitance : 567.53 ; + } + pin (q) { + function : "(i0 & i1 & i2)" ; + direction : output ; + capacitance : 151.95 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("7244.4, 7244.4, 7244.4, 7503.4, 7989.4", \ + "7264.9, 7264.9, 7264.9, 7523.7, 8009.7", \ + "7282.8, 7282.8, 7282.8, 7541.5, 8027.5", \ + "7289.9, 7289.9, 7289.9, 7548.6, 8034.5", \ + "7315.4, 7315.4, 7315.4, 7574.1, 8060.0"); + } + rise_transition (inslew_load_5x5__14) { + values ("3764.6, 3764.6, 3764.6, 3973.7, 4377.0", \ + "3783.1, 3783.1, 3783.1, 3992.0, 4394.9", \ + "3799.5, 3799.5, 3799.5, 4008.1, 4410.8", \ + "3802.7, 3802.7, 3802.7, 4011.3, 4413.9", \ + "3806.6, 3806.6, 3806.6, 4015.1, 4417.7"); + } + cell_fall (inslew_load_5x5__14) { + values ("8264.0, 8264.0, 8264.0, 8476.0, 8888.2", \ + "8272.8, 8272.8, 8272.8, 8484.8, 8897.0", \ + "8290.4, 8290.4, 8290.4, 8502.4, 8914.6", \ + "8325.6, 8325.6, 8325.6, 8537.6, 8949.8", \ + "8396.0, 8396.0, 8396.0, 8608.0, 9020.2"); + } + fall_transition (inslew_load_5x5__14) { + values ("3031.2, 3031.2, 3031.2, 3190.5, 3513.8", \ + "3031.2, 3031.2, 3031.2, 3190.5, 3513.8", \ + "3031.2, 3031.2, 3031.2, 3190.5, 3513.8", \ + "3031.2, 3031.2, 3031.2, 3190.5, 3513.8", \ + "3031.2, 3031.2, 3031.2, 3190.5, 3513.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("8767.0, 8767.0, 8767.0, 9012.1, 9494.9", \ + "8763.9, 8763.9, 8763.9, 9009.0, 9491.7", \ + "8755.1, 8755.1, 8755.1, 9000.1, 9482.8", \ + "8738.7, 8738.7, 8738.7, 8983.7, 9466.5", \ + "8706.7, 8706.7, 8706.7, 8951.7, 9434.4"); + } + rise_transition (inslew_load_5x5__14) { + values ("4819.5, 4819.5, 4819.5, 5019.5, 5411.3", \ + "4821.6, 4821.6, 4821.6, 5021.6, 5413.3", \ + "4822.1, 4822.1, 4822.1, 5022.1, 5413.8", \ + "4822.2, 4822.2, 4822.2, 5022.2, 5413.9", \ + "4822.1, 4822.1, 4822.1, 5022.1, 5413.8"); + } + cell_fall (inslew_load_5x5__14) { + values ("9292.7, 9292.7, 9292.7, 9508.1, 9824.7", \ + "9301.4, 9301.4, 9301.4, 9516.8, 9833.4", \ + "9319.0, 9319.0, 9319.0, 9534.4, 9851.0", \ + "9354.2, 9354.2, 9354.2, 9569.6, 9886.2", \ + "9424.6, 9424.6, 9424.6, 9640.0, 9956.6"); + } + fall_transition (inslew_load_5x5__14) { + values ("3591.3, 3591.3, 3591.3, 3721.6, 3936.6", \ + "3591.3, 3591.3, 3591.3, 3721.6, 3936.6", \ + "3591.3, 3591.3, 3591.3, 3721.6, 3936.6", \ + "3591.3, 3591.3, 3591.3, 3721.6, 3936.6", \ + "3591.3, 3591.3, 3591.3, 3721.6, 3936.6"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("10302.5, 10302.5, 10302.5, 10542.6, 11002.2", \ + "10291.5, 10291.5, 10291.5, 10531.6, 10991.2", \ + "10269.3, 10269.3, 10269.3, 10509.4, 10969.1", \ + "10225.0, 10225.0, 10225.0, 10465.1, 10924.7", \ + "10136.4, 10136.4, 10136.4, 10376.5, 10836.2"); + } + rise_transition (inslew_load_5x5__14) { + values ("5843.5, 5843.5, 5843.5, 6038.4, 6426.5", \ + "5843.5, 5843.5, 5843.5, 6038.4, 6426.5", \ + "5843.5, 5843.5, 5843.5, 6038.4, 6426.6", \ + "5843.5, 5843.5, 5843.5, 6038.4, 6426.5", \ + "5843.5, 5843.5, 5843.5, 6038.4, 6426.6"); + } + cell_fall (inslew_load_5x5__14) { + values ("10026.5, 10026.5, 10026.5, 10244.4, 10655.3", \ + "10035.3, 10035.3, 10035.3, 10253.2, 10664.1", \ + "10052.9, 10052.9, 10052.9, 10270.8, 10681.7", \ + "10088.1, 10088.1, 10088.1, 10306.0, 10716.9", \ + "10158.5, 10158.5, 10158.5, 10376.4, 10787.3"); + } + fall_transition (inslew_load_5x5__14) { + values ("3957.8, 3957.8, 3957.8, 4078.6, 4352.8", \ + "3957.8, 3957.8, 3957.8, 4078.6, 4352.8", \ + "3957.8, 3957.8, 3957.8, 4078.6, 4352.8", \ + "3957.8, 3957.8, 3957.8, 4078.6, 4352.8", \ + "3957.8, 3957.8, 3957.8, 4078.6, 4352.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__14) { + values ("49827.3, 49827.3, 49827.3, 51726.7, 55525.3", \ + "49946.4, 49946.4, 49946.4, 51845.8, 55644.4", \ + "50075.7, 50075.7, 50075.7, 51975.1, 55773.8", \ + "50179.8, 50179.8, 50179.8, 52079.2, 55877.8", \ + "50375.3, 50375.3, 50375.3, 52274.6, 56073.3"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("43197.7, 43197.7, 43197.7, 45097.0, 48895.7", \ + "48945.3, 48945.3, 48945.3, 48945.3, 48945.3", \ + "49044.4, 49044.4, 49044.4, 49044.4, 49044.4", \ + "49242.6, 49242.6, 49242.6, 49242.6, 49242.6", \ + "49639.1, 49639.1, 49639.1, 49639.1, 49639.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__14) { + values ("60652.2, 60652.2, 60652.2, 62551.6, 66350.2", \ + "60683.5, 60683.5, 60683.5, 62582.8, 66381.5", \ + "60725.4, 60725.4, 60725.4, 62624.8, 66423.4", \ + "60804.0, 60804.0, 60804.0, 62703.4, 66502.1", \ + "66658.6, 66658.6, 66658.6, 66658.6, 66658.6"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("49307.6, 49307.6, 49307.6, 51207.0, 55005.6", \ + "55067.1, 55067.1, 55067.1, 55067.1, 55067.1", \ + "55190.2, 55190.2, 55190.2, 55190.2, 55190.2", \ + "55436.2, 55436.2, 55436.2, 55436.2, 55436.2", \ + "55928.2, 55928.2, 55928.2, 55928.2, 55928.2"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__14) { + values ("71970.2, 71970.2, 71970.2, 73869.6, 77668.2", \ + "77684.8, 77684.8, 77684.8, 77684.8, 77684.8", \ + "72020.4, 72020.4, 72020.4, 73919.7, 77718.4", \ + "77784.7, 77784.7, 77784.7, 77784.7, 77784.7", \ + "77917.5, 77917.5, 77917.5, 77917.5, 77917.5"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("54168.1, 54168.1, 54168.1, 56067.4, 59866.1", \ + "59944.9, 59944.9, 59944.9, 59944.9, 59944.9", \ + "60102.5, 60102.5, 60102.5, 60102.5, 60102.5", \ + "60417.8, 60417.8, 60417.8, 60417.8, 60417.8", \ + "61048.2, 61048.2, 61048.2, 61048.2, 61048.2"); + } + } + } + } + + cell (oa2a2a2a24_x2) { + area : 54.00 ; + cell_leakage_power : 17 ; + leakage_power () { + when : "(i7 & !(i6) & i5 & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 13 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))) | (!(i2) & i3 & (i4 ^ i5) & (i6 ^ i7)))) | (!(i0) & i1 & ((i2 & !(i3) & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))))" ; + value : 12 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))) | (!(i1) & i2 & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 27 ; + } + leakage_power () { + when : "((i0 & ((i1 & (!((i2 | i3)) | !((i4 | i5)) | (!(i6) & !(i7)))) | (i2 & i3 & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!((i2 & i3)) & i4 & i5 & !(i6) & !(i7)))) | (i1 & ((i2 & i3 & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))) | (!((i2 & i3)) & i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & ((!(i4) & ((!(i5) & (!(i6) | !(i7))) | (!(i6) & !(i7)))) | (!(i5) & !(i6) & !(i7)))))" ; + value : 25 ; + } + leakage_power () { + when : "(((i0 | i1) & i2 & i3 & i4 & i5 & i6 & i7) | (!((i0 | i1)) & (i2 ^ i3) & (i4 ^ i5) & i6 & i7))" ; + value : 29 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & (i4 ^ i5) & (i6 ^ i7)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))))) | (!(i1) & ((i2 & !(i3) & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))))))" ; + value : 11 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((!(i2) & !((i3 & !(i4) & !(i5))) & i6 & i7) | (!(i3) & (i4 | i5) & i6 & i7))) | (!(i0) & ((i1 & ((!(i2) & !((i3 & !(i4) & !(i5))) & i6 & i7) | (!(i3) & (i4 | i5) & i6 & i7))) | (!(i1) & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))))) | (!(i2) & ((i3 & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))))" ; + value : 28 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((!(i3) & ((i4 & ((!(i5) & (i6 | i7)) | (i6 ^ i7))) | (!(i4) & i5 & (i6 | i7)))) | ((i4 ^ i5) & (i6 ^ i7)))) | (!(i2) & i3 & ((i4 & ((!(i5) & (i6 | i7)) | (i6 ^ i7))) | (!(i4) & i5 & (i6 | i7)))))) | (!(i1) & i2 & i3 & ((i4 & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))) | (!(i4) & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))))))) | (!(i0) & ((i1 & i2 & i3 & ((i4 & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))) | (!(i4) & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))))) | (!(i1) & ((i2 & i3 & ((i4 & i5 & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & !(i6) & !(i7)))))))" ; + value : 26 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i1) & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7))))))" ; + value : 9.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & i6 & !(i7)))))))))))" ; + value : 9.6 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i0) & ((i1 & !(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & i4 & !(i5) & i6 & !(i7)))) | (!(i1) & ((i2 & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))) | (!(i2) & ((i3 & i4 & !(i5) & i6 & !(i7)) | (!(i3) & !(i4) & i5 & !(i6) & i7))))))))" ; + value : 10 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((!((i2 | i3)) & i6 & i7) | (i4 & i5 & i6 & i7)))" ; + value : 30 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7))))))))" ; + value : 8.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))))" ; + value : 8.6 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 7.2 ; + } + pin (i7) { + direction : input ; + capacitance : 846.52 ; + } + pin (i6) { + direction : input ; + capacitance : 845.97 ; + } + pin (i5) { + direction : input ; + capacitance : 843.97 ; + } + pin (i4) { + direction : input ; + capacitance : 843.97 ; + } + pin (i3) { + direction : input ; + capacitance : 843.97 ; + } + pin (i2) { + direction : input ; + capacitance : 844.87 ; + } + pin (i1) { + direction : input ; + capacitance : 842.97 ; + } + pin (i0) { + direction : input ; + capacitance : 846.36 ; + } + pin (q) { + function : "((i6 & ((i5 & ((i2 & ((i0 & i1) | i3 | i4 | i7)) | (i0 & i1) | i4 | i7)) | (i2 & ((i0 & i1) | i3 | i7)) | (i0 & i1) | i7)) | (i5 & ((i2 & ((i0 & i1) | i3 | i4)) | (i0 & i1) | i4)) | (i2 & ((i0 & i1) | i3)) | (i0 & i1))" ; + direction : output ; + capacitance : 86.05 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("8585.5, 8585.5, 8585.5, 8871.9, 9410.4", \ + "8580.4, 8580.4, 8580.4, 8866.8, 9405.3", \ + "8570.1, 8570.1, 8570.1, 8856.5, 9395.0", \ + "8549.4, 8549.4, 8549.4, 8835.8, 9374.3", \ + "8508.2, 8508.2, 8508.2, 8794.6, 9333.2"); + } + rise_transition (inslew_load_5x5__18) { + values ("4117.3, 4117.3, 4117.3, 4348.4, 4797.4", \ + "4117.3, 4117.3, 4117.3, 4348.4, 4797.4", \ + "4117.3, 4117.3, 4117.3, 4348.4, 4797.4", \ + "4117.3, 4117.3, 4117.3, 4348.4, 4797.4", \ + "4117.4, 4117.4, 4117.4, 4348.4, 4797.5"); + } + cell_fall (inslew_load_5x5__18) { + values ("19781.7, 19781.7, 19781.7, 20023.1, 20479.0", \ + "19766.9, 19766.9, 19766.9, 20008.3, 20464.2", \ + "19737.2, 19737.2, 19737.2, 19978.6, 20434.5", \ + "19678.0, 19678.0, 19678.0, 19919.4, 20375.3", \ + "19559.6, 19559.6, 19559.6, 19801.0, 20256.9"); + } + fall_transition (inslew_load_5x5__18) { + values ("11703.1, 11703.1, 11703.1, 11873.0, 12195.1", \ + "11703.1, 11703.1, 11703.1, 11873.0, 12195.1", \ + "11703.1, 11703.1, 11703.1, 11873.0, 12195.1", \ + "11703.1, 11703.1, 11703.1, 11873.0, 12195.1", \ + "11703.1, 11703.1, 11703.1, 11873.0, 12195.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("7391.6, 7391.6, 7391.6, 7683.7, 8224.1", \ + "7396.5, 7396.5, 7396.5, 7688.6, 8229.0", \ + "7403.7, 7403.7, 7403.7, 7695.8, 8236.2", \ + "7420.4, 7420.4, 7420.4, 7712.5, 8252.9", \ + "7454.0, 7454.0, 7454.0, 7746.1, 8286.5"); + } + rise_transition (inslew_load_5x5__18) { + values ("3344.9, 3344.9, 3344.9, 3585.1, 4047.8", \ + "3347.3, 3347.3, 3347.3, 3587.6, 4050.1", \ + "3347.9, 3347.9, 3347.9, 3588.2, 4050.7", \ + "3348.3, 3348.3, 3348.3, 3588.5, 4051.0", \ + "3348.3, 3348.3, 3348.3, 3588.5, 4051.0"); + } + cell_fall (inslew_load_5x5__18) { + values ("18765.2, 18765.2, 18765.2, 19005.2, 19457.1", \ + "18750.4, 18750.4, 18750.4, 18990.4, 19442.3", \ + "18720.8, 18720.8, 18720.8, 18960.8, 19412.7", \ + "18661.6, 18661.6, 18661.6, 18901.6, 19353.5", \ + "18543.1, 18543.1, 18543.1, 18783.1, 19235.0"); + } + fall_transition (inslew_load_5x5__18) { + values ("11028.3, 11028.3, 11028.3, 11198.8, 11517.7", \ + "11028.3, 11028.3, 11028.3, 11198.8, 11517.7", \ + "11028.3, 11028.3, 11028.3, 11198.8, 11517.7", \ + "11028.3, 11028.3, 11028.3, 11198.8, 11517.7", \ + "11028.3, 11028.3, 11028.3, 11198.8, 11517.7"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("8496.1, 8496.1, 8496.1, 8782.8, 9321.4", \ + "8491.0, 8491.0, 8491.0, 8777.7, 9316.3", \ + "8480.7, 8480.7, 8480.7, 8767.4, 9306.0", \ + "8460.0, 8460.0, 8460.0, 8746.7, 9285.3", \ + "8418.8, 8418.8, 8418.8, 8705.6, 9244.1"); + } + rise_transition (inslew_load_5x5__18) { + values ("4057.7, 4057.7, 4057.7, 4289.5, 4739.1", \ + "4057.7, 4057.7, 4057.7, 4289.5, 4739.1", \ + "4057.7, 4057.7, 4057.7, 4289.5, 4739.1", \ + "4057.7, 4057.7, 4057.7, 4289.5, 4739.1", \ + "4057.7, 4057.7, 4057.7, 4289.6, 4739.2"); + } + cell_fall (inslew_load_5x5__18) { + values ("16108.5, 16108.5, 16108.5, 16337.6, 16788.3", \ + "16100.7, 16100.7, 16100.7, 16329.7, 16780.4", \ + "16077.6, 16077.6, 16077.6, 16306.7, 16757.4", \ + "16041.7, 16041.7, 16041.7, 16270.7, 16721.4", \ + "15968.2, 15968.2, 15968.2, 16197.2, 16648.0"); + } + fall_transition (inslew_load_5x5__18) { + values ("9353.1, 9353.1, 9353.1, 9520.0, 9837.6", \ + "9356.8, 9356.8, 9356.8, 9523.7, 9841.3", \ + "9358.5, 9358.5, 9358.5, 9525.5, 9843.0", \ + "9366.1, 9366.1, 9366.1, 9533.2, 9850.7", \ + "9373.3, 9373.3, 9373.3, 9540.3, 9857.7"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("7297.4, 7297.4, 7297.4, 7590.0, 8130.8", \ + "7302.2, 7302.2, 7302.2, 7594.8, 8135.6", \ + "7309.4, 7309.4, 7309.4, 7602.0, 8142.8", \ + "7326.2, 7326.2, 7326.2, 7618.8, 8159.6", \ + "7359.8, 7359.8, 7359.8, 7652.4, 8193.2"); + } + rise_transition (inslew_load_5x5__18) { + values ("3280.4, 3280.4, 3280.4, 3521.4, 3986.0", \ + "3282.9, 3282.9, 3282.9, 3523.8, 3988.4", \ + "3283.5, 3283.5, 3283.5, 3524.4, 3988.9", \ + "3283.9, 3283.9, 3283.9, 3524.8, 3989.3", \ + "3283.9, 3283.9, 3283.9, 3524.8, 3989.3"); + } + cell_fall (inslew_load_5x5__18) { + values ("15079.6, 15079.6, 15079.6, 15307.7, 15757.1", \ + "15071.6, 15071.6, 15071.6, 15299.8, 15749.2", \ + "15048.6, 15048.6, 15048.6, 15276.7, 15726.2", \ + "15012.6, 15012.6, 15012.6, 15241.8, 15690.2", \ + "14939.1, 14939.1, 14939.1, 15168.2, 15616.7"); + } + fall_transition (inslew_load_5x5__18) { + values ("8667.1, 8667.1, 8667.1, 8832.7, 9154.1", \ + "8670.7, 8670.7, 8670.7, 8836.4, 9157.7", \ + "8672.5, 8672.5, 8672.5, 8838.1, 9159.5", \ + "8680.1, 8680.1, 8680.1, 8845.7, 9167.0", \ + "8687.1, 8687.1, 8687.1, 8852.8, 9174.1"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("5820.1, 5820.1, 5820.1, 6135.2, 6704.7", \ + "5825.1, 5825.1, 5825.1, 6140.2, 6709.6", \ + "5832.7, 5832.7, 5832.7, 6147.8, 6717.2", \ + "5849.3, 5849.3, 5849.3, 6164.3, 6733.7", \ + "5882.8, 5882.8, 5882.8, 6197.9, 6767.3"); + } + rise_transition (inslew_load_5x5__18) { + values ("2244.0, 2244.0, 2244.0, 2509.8, 3000.9", \ + "2246.7, 2246.7, 2246.7, 2512.4, 3003.5", \ + "2247.6, 2247.6, 2247.6, 2513.3, 3004.3", \ + "2247.9, 2247.9, 2247.9, 2513.6, 3004.6", \ + "2248.2, 2248.2, 2248.2, 2513.9, 3004.9"); + } + cell_fall (inslew_load_5x5__18) { + values ("11131.4, 11131.4, 11131.4, 11409.3, 11907.7", \ + "10986.7, 10986.7, 10986.7, 11418.7, 11917.6", \ + "10992.8, 10992.8, 10992.8, 11426.5, 11926.0", \ + "10965.0, 10965.0, 10965.0, 11399.7, 11899.5", \ + "10951.6, 10951.6, 10951.6, 11389.8, 11890.9"); + } + fall_transition (inslew_load_5x5__18) { + values ("6080.7, 6080.7, 6080.7, 6222.2, 6482.1", \ + "6008.5, 6008.5, 6008.5, 6238.1, 6498.1", \ + "6030.3, 6030.3, 6030.3, 6261.1, 6521.2", \ + "6041.5, 6041.5, 6041.5, 6273.0, 6533.0", \ + "6086.0, 6086.0, 6086.0, 6320.1, 6580.3"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("7112.0, 7112.0, 7112.0, 7405.9, 7950.1", \ + "7106.8, 7106.8, 7106.8, 7400.7, 7944.9", \ + "7096.5, 7096.5, 7096.5, 7390.4, 7934.6", \ + "7075.9, 7075.9, 7075.9, 7369.8, 7914.0", \ + "7034.7, 7034.7, 7034.7, 7328.6, 7872.8"); + } + rise_transition (inslew_load_5x5__18) { + values ("3124.7, 3124.7, 3124.7, 3367.8, 3836.2", \ + "3124.7, 3124.7, 3124.7, 3367.8, 3836.2", \ + "3124.7, 3124.7, 3124.7, 3367.8, 3836.2", \ + "3124.7, 3124.7, 3124.7, 3367.8, 3836.2", \ + "3124.9, 3124.9, 3124.9, 3368.0, 3836.4"); + } + cell_fall (inslew_load_5x5__18) { + values ("11951.4, 11951.4, 11951.4, 12394.8, 12911.5", \ + "11961.9, 11961.9, 11961.9, 12404.4, 12921.5", \ + "11971.0, 11971.0, 11971.0, 12412.3, 12929.9", \ + "11944.6, 11944.6, 11944.6, 12385.2, 12903.1", \ + "11937.7, 11937.7, 11937.7, 12375.8, 12894.7"); + } + fall_transition (inslew_load_5x5__18) { + values ("6674.0, 6674.0, 6674.0, 6942.2, 7208.3", \ + "6689.2, 6689.2, 6689.2, 6958.1, 7224.6", \ + "6711.0, 6711.0, 6711.0, 6981.1, 7247.9", \ + "6722.1, 6722.1, 6722.1, 6992.9, 7259.8", \ + "6767.0, 6767.0, 6767.0, 7040.5, 7307.8"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("3683.7, 3683.7, 3683.7, 4046.5, 4640.8", \ + "3685.6, 3685.6, 3685.6, 4048.6, 4643.1", \ + "3692.2, 3692.2, 3692.2, 4055.4, 4650.1", \ + "3708.4, 3708.4, 3708.4, 4071.6, 4666.3", \ + "3739.2, 3739.2, 3739.2, 4102.6, 4697.7"); + } + rise_transition (inslew_load_5x5__18) { + values ("688.8, 688.8, 688.8, 1001.8, 1544.3", \ + "689.0, 689.0, 689.0, 1002.1, 1544.6", \ + "689.2, 689.2, 689.2, 1002.3, 1544.9", \ + "689.2, 689.2, 689.2, 1002.3, 1544.9", \ + "689.4, 689.4, 689.4, 1002.6, 1545.3"); + } + cell_fall (inslew_load_5x5__18) { + values ("6965.2, 6965.2, 6965.2, 7209.1, 7653.9", \ + "7023.9, 7023.9, 7023.9, 7268.4, 7708.2", \ + "7099.8, 7099.8, 7099.8, 7344.6, 7788.2", \ + "7199.6, 7199.6, 7199.6, 7444.8, 7892.9", \ + "7227.9, 7227.9, 7227.9, 7473.6, 7923.5"); + } + fall_transition (inslew_load_5x5__18) { + values ("3091.2, 3091.2, 3091.2, 3258.3, 3574.6", \ + "3140.5, 3140.5, 3140.5, 3306.1, 3625.6", \ + "3209.2, 3209.2, 3209.2, 3372.7, 3693.6", \ + "3307.9, 3307.9, 3307.9, 3468.4, 3790.2", \ + "3375.0, 3375.0, 3375.0, 3533.6, 3854.6"); + } + } + timing (maxd_q_i7_positive_unate) { + related_pin : "i7" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("4825.5, 4825.5, 4825.5, 5153.4, 5748.2", \ + "4820.3, 4820.3, 4820.3, 5148.2, 5743.0", \ + "4810.0, 4810.0, 4810.0, 5137.9, 5732.7", \ + "4789.4, 4789.4, 4789.4, 5117.3, 5712.1", \ + "4749.1, 4749.1, 4749.1, 5076.9, 5671.6"); + } + rise_transition (inslew_load_5x5__18) { + values ("1488.7, 1488.7, 1488.7, 1769.2, 2295.1", \ + "1488.7, 1488.7, 1488.7, 1769.2, 2295.1", \ + "1488.7, 1488.7, 1488.7, 1769.2, 2295.1", \ + "1488.7, 1488.7, 1488.7, 1769.2, 2295.1", \ + "1490.5, 1490.5, 1490.5, 1770.9, 2296.7"); + } + cell_fall (inslew_load_5x5__18) { + values ("8023.1, 8023.1, 8023.1, 8272.1, 8736.4", \ + "8078.4, 8078.4, 8078.4, 8327.8, 8793.7", \ + "8149.5, 8149.5, 8149.5, 8399.4, 8867.5", \ + "8242.8, 8242.8, 8242.8, 8493.4, 8962.6", \ + "8265.6, 8265.6, 8265.6, 8516.6, 8986.6"); + } + fall_transition (inslew_load_5x5__18) { + values ("3850.2, 3850.2, 3850.2, 3997.2, 4313.1", \ + "3898.8, 3898.8, 3898.8, 4044.8, 4360.2", \ + "3966.4, 3966.4, 3966.4, 4111.0, 4425.7", \ + "4063.7, 4063.7, 4063.7, 4206.3, 4518.3", \ + "4128.7, 4128.7, 4128.7, 4270.0, 4580.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__18) { + values ("49535.7, 49535.7, 49535.7, 50611.4, 52762.7", \ + "52808.4, 52808.4, 52808.4, 52808.4, 52808.4", \ + "52899.8, 52899.8, 52899.8, 52899.8, 52899.8", \ + "53082.7, 53082.7, 53082.7, 53082.7, 53082.7", \ + "50221.6, 50221.6, 50221.6, 51297.2, 53448.6"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("87712.9, 87712.9, 87712.9, 88788.6, 90940.0", \ + "91028.4, 91028.4, 91028.4, 91028.4, 91028.4", \ + "91205.1, 91205.1, 91205.1, 91205.1, 91205.1", \ + "91558.7, 91558.7, 91558.7, 91558.7, 91558.7", \ + "92265.9, 92265.9, 92265.9, 92265.9, 92265.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__18) { + values ("41825.1, 41825.1, 41825.1, 42900.7, 45052.1", \ + "41881.8, 41881.8, 41881.8, 42957.5, 45108.8", \ + "41984.2, 41984.2, 41984.2, 43059.9, 45211.2", \ + "42186.7, 42186.7, 42186.7, 43262.4, 45413.7", \ + "45817.0, 45817.0, 45817.0, 45817.0, 45817.0"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("82392.9, 82392.9, 82392.9, 83468.6, 85619.9", \ + "85683.0, 85683.0, 85683.0, 85683.0, 85683.0", \ + "85809.3, 85809.3, 85809.3, 85809.3, 85809.3", \ + "86061.9, 86061.9, 86061.9, 86061.9, 86061.9", \ + "86567.1, 86567.1, 86567.1, 86567.1, 86567.1"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__18) { + values ("48946.1, 48946.1, 48946.1, 50021.8, 52173.1", \ + "52201.9, 52201.9, 52201.9, 52201.9, 52201.9", \ + "52259.4, 52259.4, 52259.4, 52259.4, 52259.4", \ + "52374.4, 52374.4, 52374.4, 52374.4, 52374.4", \ + "49377.5, 49377.5, 49377.5, 50453.2, 52604.5"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("68869.1, 68869.1, 68869.1, 69944.8, 72096.1", \ + "68966.1, 68966.1, 68966.1, 70041.8, 72193.1", \ + "69142.2, 69142.2, 69142.2, 70217.9, 72369.2", \ + "69507.4, 69507.4, 69507.4, 70583.1, 72734.4", \ + "70212.2, 70212.2, 70212.2, 71287.9, 73439.2"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__18) { + values ("41231.9, 41231.9, 41231.9, 42307.6, 44459.0", \ + "41271.1, 41271.1, 41271.1, 42346.7, 44498.1", \ + "41338.2, 41338.2, 41338.2, 42413.8, 44565.2", \ + "41470.1, 41470.1, 41470.1, 42545.7, 44697.1", \ + "44959.1, 44959.1, 44959.1, 44959.1, 44959.1"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("63525.8, 63525.8, 63525.8, 64601.5, 66752.8", \ + "63601.2, 63601.2, 63601.2, 64676.9, 66828.2", \ + "63734.2, 63734.2, 63734.2, 64809.9, 66961.3", \ + "64013.1, 64013.1, 64013.1, 65088.7, 67240.1", \ + "64545.4, 64545.4, 64545.4, 65621.1, 67772.4"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__18) { + values ("32544.8, 32544.8, 32544.8, 33620.5, 35771.8", \ + "32574.1, 32574.1, 32574.1, 33649.8, 35801.1", \ + "32622.8, 32622.8, 32622.8, 33698.5, 35849.8", \ + "32716.7, 32716.7, 32716.7, 33792.3, 35943.7", \ + "32903.7, 32903.7, 32903.7, 33979.4, 36130.7"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("43788.4, 43788.4, 43788.4, 44864.1, 47015.4", \ + "43898.8, 43898.8, 43898.8, 44974.4, 47125.8", \ + "44092.7, 44092.7, 44092.7, 45168.4, 47319.7", \ + "44377.3, 44377.3, 44377.3, 45453.0, 47604.3", \ + "45017.3, 45017.3, 45017.3, 46092.9, 48244.3"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__18) { + values ("40302.2, 40302.2, 40302.2, 41377.9, 43529.2", \ + "43549.0, 43549.0, 43549.0, 43549.0, 43549.0", \ + "43588.5, 43588.5, 43588.5, 43588.5, 43588.5", \ + "43667.5, 43667.5, 43667.5, 43667.5, 43667.5", \ + "40599.2, 40599.2, 40599.2, 41674.8, 43826.2"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("49157.6, 49157.6, 49157.6, 50233.3, 52384.6", \ + "49287.3, 49287.3, 49287.3, 50363.0, 52514.3", \ + "49519.6, 49519.6, 49519.6, 50595.2, 52746.6", \ + "49879.8, 49879.8, 49879.8, 50955.5, 53106.8", \ + "50673.0, 50673.0, 50673.0, 51748.6, 53900.0"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__18) { + values ("19388.0, 19388.0, 19388.0, 20463.7, 22615.0", \ + "19410.6, 19410.6, 19410.6, 20486.3, 22637.6", \ + "19448.7, 19448.7, 19448.7, 20524.4, 22675.8", \ + "22744.9, 22744.9, 22744.9, 22744.9, 22744.9", \ + "19663.4, 19663.4, 19663.4, 20739.1, 22890.4"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("23831.7, 23831.7, 23831.7, 24907.4, 27058.7", \ + "24037.4, 24037.4, 24037.4, 25113.1, 27264.4", \ + "24360.8, 24360.8, 24360.8, 25436.5, 27587.8", \ + "24893.1, 24893.1, 24893.1, 25968.8, 28120.1", \ + "25573.8, 25573.8, 25573.8, 26649.4, 28800.8"); + } + } + internal_power (energy_pos_q_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__18) { + values ("27210.2, 27210.2, 27210.2, 28285.9, 30437.2", \ + "30451.7, 30451.7, 30451.7, 30451.7, 30451.7", \ + "30480.8, 30480.8, 30480.8, 30480.8, 30480.8", \ + "30539.0, 30539.0, 30539.0, 30539.0, 30539.0", \ + "27431.9, 27431.9, 27431.9, 28507.6, 30658.9"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("29254.9, 29254.9, 29254.9, 30330.6, 32481.9", \ + "29474.6, 29474.6, 29474.6, 30550.3, 32701.6", \ + "29826.9, 29826.9, 29826.9, 30902.6, 33053.9", \ + "30419.5, 30419.5, 30419.5, 31495.1, 33646.5", \ + "31223.8, 31223.8, 31223.8, 32299.4, 34450.8"); + } + } + } + } + + cell (ao22_x4) { + area : 28.80 ; + cell_leakage_power : 6 ; + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 5.7 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 7.1 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 7.2 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 5.2 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 6.1 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 4.7 ; + } + pin (i2) { + direction : input ; + capacitance : 438.92 ; + } + pin (i1) { + direction : input ; + capacitance : 435.52 ; + } + pin (i0) { + direction : input ; + capacitance : 432.96 ; + } + pin (q) { + function : "(i2 & (i0 | i1))" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("11412.9, 11412.9, 11412.9, 11653.0, 12111.8", \ + "11420.7, 11420.7, 11420.7, 11660.8, 12119.7", \ + "11428.6, 11428.6, 11428.6, 11668.8, 12127.7", \ + "11443.1, 11443.1, 11443.1, 11683.3, 12142.1", \ + "11476.6, 11476.6, 11476.6, 11716.8, 12175.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("6064.1, 6064.1, 6064.1, 6258.3, 6643.3", \ + "6069.4, 6069.4, 6069.4, 6263.6, 6648.6", \ + "6072.5, 6072.5, 6072.5, 6266.7, 6651.7", \ + "6073.0, 6073.0, 6073.0, 6267.3, 6652.2", \ + "6073.4, 6073.4, 6073.4, 6267.7, 6652.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("13892.9, 13892.9, 13892.9, 14110.8, 14668.7", \ + "13887.5, 13887.5, 13887.5, 14105.4, 14663.3", \ + "13876.8, 13876.8, 13876.8, 14094.7, 14652.6", \ + "13855.4, 13855.4, 13855.4, 14073.3, 14631.2", \ + "13812.6, 13812.6, 13812.6, 14030.5, 14588.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("7084.4, 7084.4, 7084.4, 7250.9, 7543.5", \ + "7084.4, 7084.4, 7084.4, 7250.9, 7543.5", \ + "7084.4, 7084.4, 7084.4, 7250.9, 7543.5", \ + "7084.4, 7084.4, 7084.4, 7250.9, 7543.5", \ + "7084.4, 7084.4, 7084.4, 7250.9, 7543.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("10267.6, 10267.6, 10267.6, 10507.2, 10975.3", \ + "10275.6, 10275.6, 10275.6, 10515.2, 10983.0", \ + "10283.5, 10283.5, 10283.5, 10523.1, 10990.9", \ + "10298.1, 10298.1, 10298.1, 10537.7, 11005.4", \ + "10331.6, 10331.6, 10331.6, 10571.2, 11038.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("5319.8, 5319.8, 5319.8, 5516.5, 5906.8", \ + "5325.2, 5325.2, 5325.2, 5521.9, 5912.2", \ + "5328.3, 5328.3, 5328.3, 5524.9, 5915.3", \ + "5329.0, 5329.0, 5329.0, 5525.6, 5916.0", \ + "5329.4, 5329.4, 5329.4, 5526.0, 5916.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("11626.5, 11626.5, 11626.5, 11926.8, 12468.6", \ + "11628.7, 11628.7, 11628.7, 11929.2, 12471.2", \ + "11636.8, 11636.8, 11636.8, 11937.4, 12480.0", \ + "11648.6, 11648.6, 11648.6, 11949.4, 12492.2", \ + "11676.5, 11676.5, 11676.5, 11977.3, 12520.2"); + } + fall_transition (inslew_load_5x5__3) { + values ("5848.8, 5848.8, 5848.8, 6005.1, 6252.2", \ + "5851.4, 5851.4, 5851.4, 6007.9, 6255.0", \ + "5856.9, 5856.9, 5856.9, 6013.6, 6260.8", \ + "5860.0, 5860.0, 5860.0, 6016.9, 6264.1", \ + "5860.4, 5860.4, 5860.4, 6017.3, 6264.5"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("11482.2, 11482.2, 11482.2, 11722.3, 12181.2", \ + "11477.1, 11477.1, 11477.1, 11717.2, 12176.1", \ + "11466.8, 11466.8, 11466.8, 11706.9, 12165.8", \ + "11446.1, 11446.1, 11446.1, 11686.2, 12145.1", \ + "11404.9, 11404.9, 11404.9, 11645.0, 12103.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("6060.8, 6060.8, 6060.8, 6255.0, 6640.1", \ + "6060.8, 6060.8, 6060.8, 6255.0, 6640.1", \ + "6060.8, 6060.8, 6060.8, 6255.0, 6640.1", \ + "6060.8, 6060.8, 6060.8, 6255.0, 6640.1", \ + "6060.9, 6060.9, 6060.9, 6255.1, 6640.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("8370.9, 8370.9, 8370.9, 8582.5, 8994.5", \ + "8379.7, 8379.7, 8379.7, 8591.3, 9003.3", \ + "8397.3, 8397.3, 8397.3, 8608.9, 9020.9", \ + "8432.5, 8432.5, 8432.5, 8644.1, 9056.1", \ + "8502.9, 8502.9, 8502.9, 8714.5, 9126.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("3293.3, 3293.3, 3293.3, 3442.5, 3759.0", \ + "3293.3, 3293.3, 3293.3, 3442.5, 3759.0", \ + "3293.3, 3293.3, 3293.3, 3442.5, 3759.0", \ + "3293.3, 3293.3, 3293.3, 3442.5, 3759.0", \ + "3293.3, 3293.3, 3293.3, 3442.5, 3759.0"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("64934.3, 64934.3, 64934.3, 66830.1, 70621.8", \ + "64990.6, 64990.6, 64990.6, 66886.4, 70678.1", \ + "65059.0, 65059.0, 65059.0, 66954.8, 70746.5", \ + "65162.8, 65162.8, 65162.8, 67058.7, 70850.4", \ + "65366.7, 65366.7, 65366.7, 67262.6, 71054.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("72047.1, 72047.1, 72047.1, 73942.9, 77734.6", \ + "77766.2, 77766.2, 77766.2, 77766.2, 77766.2", \ + "77829.3, 77829.3, 77829.3, 77829.3, 77829.3", \ + "77955.5, 77955.5, 77955.5, 77955.5, 77955.5", \ + "78208.0, 78208.0, 78208.0, 78208.0, 78208.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("57943.7, 57943.7, 57943.7, 59839.5, 63631.2", \ + "57985.9, 57985.9, 57985.9, 59881.8, 63673.5", \ + "58025.9, 58025.9, 58025.9, 59921.7, 63713.4", \ + "58074.2, 58074.2, 58074.2, 59970.0, 63761.7", \ + "58165.2, 58165.2, 58165.2, 60061.1, 63852.7"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("58600.1, 58600.1, 58600.1, 60495.9, 64287.6", \ + "58657.3, 58657.3, 58657.3, 60553.2, 64344.8", \ + "58773.1, 58773.1, 58773.1, 60668.9, 64460.6", \ + "58955.9, 58955.9, 58955.9, 60851.8, 64643.5", \ + "59286.0, 59286.0, 59286.0, 61181.9, 64973.5"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("65280.5, 65280.5, 65280.5, 67176.3, 70968.0", \ + "70990.9, 70990.9, 70990.9, 70990.9, 70990.9", \ + "71036.7, 71036.7, 71036.7, 71036.7, 71036.7", \ + "71128.2, 71128.2, 71128.2, 71128.2, 71128.2", \ + "65624.3, 65624.3, 65624.3, 67520.1, 71311.8"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("46888.0, 46888.0, 46888.0, 48783.9, 52575.5", \ + "52619.6, 52619.6, 52619.6, 52619.6, 52619.6", \ + "52707.8, 52707.8, 52707.8, 52707.8, 52707.8", \ + "52884.2, 52884.2, 52884.2, 52884.2, 52884.2", \ + "53236.9, 53236.9, 53236.9, 53236.9, 53236.9"); + } + } + } + } + + cell (inv_x2) { + area : 10.80 ; + cell_leakage_power : 2 ; + leakage_power () { + when : "i" ; + value : 1.2 ; + } + leakage_power () { + when : "!(i)" ; + value : 2.8 ; + } + pin (i) { + direction : input ; + capacitance : 712.18 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 75.81 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("1482.3, 1482.3, 1482.3, 1675.4, 2058.6", \ + "1491.1, 1491.1, 1491.1, 1684.2, 2067.4", \ + "1508.6, 1508.6, 1508.6, 1701.8, 2084.9", \ + "1542.8, 1542.8, 1542.8, 1736.5, 2120.0", \ + "1580.8, 1580.8, 1580.8, 1786.1, 2181.8"); + } + rise_transition (inslew_load_5x5__19) { + values ("583.1, 583.1, 583.1, 840.1, 1353.9", \ + "583.1, 583.1, 583.1, 840.1, 1353.9", \ + "583.1, 583.1, 583.1, 840.1, 1353.9", \ + "583.9, 583.9, 583.9, 840.7, 1354.2", \ + "595.9, 595.9, 595.9, 856.8, 1368.7"); + } + cell_fall (inslew_load_5x5__19) { + values ("750.2, 750.2, 750.2, 837.7, 1011.4", \ + "759.0, 759.0, 759.0, 846.5, 1020.2", \ + "776.1, 776.1, 776.1, 863.9, 1037.7", \ + "795.3, 795.3, 795.3, 888.4, 1068.1", \ + "750.1, 750.1, 750.1, 867.0, 1078.4"); + } + fall_transition (inslew_load_5x5__19) { + values ("271.6, 271.6, 271.6, 386.8, 617.2", \ + "271.6, 271.6, 271.6, 386.8, 617.2", \ + "271.9, 271.9, 271.9, 387.1, 617.4", \ + "277.6, 277.6, 277.6, 394.9, 624.8", \ + "301.2, 301.2, 301.2, 430.3, 669.5"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__19) { + values ("1021.0, 1021.0, 1021.0, 1968.6, 3863.8", \ + "1107.0, 1107.0, 1107.0, 2054.6, 3949.7", \ + "1279.0, 1279.0, 1279.0, 2226.6, 4121.7", \ + "1623.0, 1623.0, 1623.0, 2570.6, 4465.7", \ + "2310.9, 2310.9, 2310.9, 3258.5, 5153.7"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("990.7, 990.7, 990.7, 1938.3, 3833.4", \ + "1021.3, 1021.3, 1021.3, 1968.9, 3864.1", \ + "1082.6, 1082.6, 1082.6, 2030.1, 3925.3", \ + "1205.0, 1205.0, 1205.0, 2152.6, 4047.7", \ + "1449.9, 1449.9, 1449.9, 2397.5, 4292.6"); + } + } + } + } + + cell (nao2o22_x1) { + area : 25.20 ; + cell_leakage_power : 6.4 ; + leakage_power () { + when : "(!(i3) & !(i2) & i1 & i0)" ; + value : 9.5 ; + } + leakage_power () { + when : "(!(i3) & i2 & !(i1) & i0)" ; + value : 2.8 ; + } + leakage_power () { + when : "((i0 & ((i1 & i2 & !(i3)) | (!(i1) & i3))) | (i1 & i2 & !(i3)))" ; + value : 3.1 ; + } + leakage_power () { + when : "(i1 & i3)" ; + value : 3.3 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & !(i3))" ; + value : 7.5 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 11 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3))" ; + value : 8.3 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.6 ; + } + pin (i3) { + direction : input ; + capacitance : 850.57 ; + } + pin (i2) { + direction : input ; + capacitance : 849.07 ; + } + pin (i1) { + direction : input ; + capacitance : 848.02 ; + } + pin (i0) { + direction : input ; + capacitance : 846.52 ; + } + pin (nq) { + function : "((!(i1) & !(i0)) | (!(i3) & !(i2)))" ; + direction : output ; + capacitance : 151.11 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("5101.8, 5101.8, 5101.8, 5544.8, 6443.6", \ + "5096.3, 5096.3, 5096.3, 5539.4, 6438.2", \ + "5085.5, 5085.5, 5085.5, 5528.6, 6427.5", \ + "5063.8, 5063.8, 5063.8, 5507.0, 6406.0", \ + "5020.4, 5020.4, 5020.4, 5463.8, 6363.0"); + } + rise_transition (inslew_load_5x5__11) { + values ("5866.8, 5866.8, 5866.8, 6587.0, 8027.6", \ + "5866.8, 5866.8, 5866.8, 6587.0, 8027.6", \ + "5866.8, 5866.8, 5866.8, 6587.0, 8027.6", \ + "5866.8, 5866.8, 5866.8, 6587.0, 8027.6", \ + "5867.1, 5867.1, 5867.1, 6587.2, 8027.6"); + } + cell_fall (inslew_load_5x5__11) { + values ("2344.2, 2344.2, 2344.2, 2616.6, 3162.4", \ + "2348.3, 2348.3, 2348.3, 2620.7, 3166.5", \ + "2354.6, 2354.6, 2354.6, 2627.4, 3173.9", \ + "2369.9, 2369.9, 2369.9, 2642.2, 3188.0", \ + "2397.1, 2397.1, 2397.1, 2671.6, 3219.4"); + } + fall_transition (inslew_load_5x5__11) { + values ("2151.0, 2151.0, 2151.0, 2580.9, 3441.4", \ + "2159.0, 2159.0, 2159.0, 2588.9, 3449.4", \ + "2165.7, 2165.7, 2165.7, 2596.3, 3457.9", \ + "2171.4, 2171.4, 2171.4, 2601.0, 3461.3", \ + "2181.3, 2181.3, 2181.3, 2608.5, 3465.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("2200.8, 2200.8, 2200.8, 2665.1, 3586.3", \ + "2205.6, 2205.6, 2205.6, 2669.7, 3590.6", \ + "2213.8, 2213.8, 2213.8, 2678.1, 3599.8", \ + "2224.5, 2224.5, 2224.5, 2689.0, 3611.5", \ + "2252.8, 2252.8, 2252.8, 2720.6, 3642.9"); + } + rise_transition (inslew_load_5x5__11) { + values ("1411.5, 1411.5, 1411.5, 2143.6, 3606.4", \ + "1422.4, 1422.4, 1422.4, 2154.2, 3616.4", \ + "1436.6, 1436.6, 1436.6, 2168.7, 3632.2", \ + "1442.5, 1442.5, 1442.5, 2174.9, 3639.6", \ + "1463.0, 1463.0, 1463.0, 2191.0, 3648.1"); + } + cell_fall (inslew_load_5x5__11) { + values ("1552.7, 1552.7, 1552.7, 1830.3, 2380.6", \ + "1556.9, 1556.9, 1556.9, 1834.5, 2384.7", \ + "1562.0, 1562.0, 1562.0, 1839.8, 2391.1", \ + "1578.8, 1578.8, 1578.8, 1856.5, 2406.4", \ + "1584.0, 1584.0, 1584.0, 1873.9, 2434.1"); + } + fall_transition (inslew_load_5x5__11) { + values ("939.5, 939.5, 939.5, 1369.8, 2229.1", \ + "947.7, 947.7, 947.7, 1378.0, 2237.1", \ + "952.5, 952.5, 952.5, 1383.2, 2244.0", \ + "962.2, 962.2, 962.2, 1391.5, 2249.4", \ + "976.7, 976.7, 976.7, 1406.4, 2259.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("6418.4, 6418.4, 6418.4, 6852.7, 7742.7", \ + "6413.0, 6413.0, 6413.0, 6847.3, 7737.3", \ + "6402.1, 6402.1, 6402.1, 6836.4, 7726.5", \ + "6380.3, 6380.3, 6380.3, 6814.8, 7705.0", \ + "6336.7, 6336.7, 6336.7, 6771.5, 7661.9"); + } + rise_transition (inslew_load_5x5__11) { + values ("7891.1, 7891.1, 7891.1, 8611.4, 10051.9", \ + "7891.1, 7891.1, 7891.1, 8611.4, 10051.9", \ + "7891.1, 7891.1, 7891.1, 8611.4, 10051.9", \ + "7891.1, 7891.1, 7891.1, 8611.4, 10051.9", \ + "7891.2, 7891.2, 7891.2, 8611.4, 10051.9"); + } + cell_fall (inslew_load_5x5__11) { + values ("3275.4, 3275.4, 3275.4, 3541.1, 4078.5", \ + "3270.2, 3270.2, 3270.2, 3536.0, 4073.3", \ + "3259.9, 3259.9, 3259.9, 3525.6, 4063.0", \ + "3239.2, 3239.2, 3239.2, 3505.0, 4042.3", \ + "3197.1, 3197.1, 3197.1, 3463.3, 4000.9"); + } + fall_transition (inslew_load_5x5__11) { + values ("3545.7, 3545.7, 3545.7, 3969.4, 4816.9", \ + "3545.7, 3545.7, 3545.7, 3969.4, 4816.9", \ + "3545.7, 3545.7, 3545.7, 3969.4, 4816.9", \ + "3545.7, 3545.7, 3545.7, 3969.4, 4816.9", \ + "3550.0, 3550.0, 3550.0, 3972.5, 4818.4"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("3522.1, 3522.1, 3522.1, 3977.6, 4891.7", \ + "3526.4, 3526.4, 3526.4, 3981.7, 4895.7", \ + "3535.5, 3535.5, 3535.5, 3991.2, 4905.5", \ + "3547.0, 3547.0, 3547.0, 4003.1, 4917.9", \ + "3578.3, 3578.3, 3578.3, 4034.0, 4948.1"); + } + rise_transition (inslew_load_5x5__11) { + values ("3467.7, 3467.7, 3467.7, 4199.8, 5665.3", \ + "3477.8, 3477.8, 3477.8, 4209.7, 5674.9", \ + "3493.5, 3493.5, 3493.5, 4225.9, 5691.7", \ + "3500.8, 3500.8, 3500.8, 4233.7, 5700.3", \ + "3509.6, 3509.6, 3509.6, 4240.4, 5704.7"); + } + cell_fall (inslew_load_5x5__11) { + values ("2486.4, 2486.4, 2486.4, 2757.0, 3299.7", \ + "2481.2, 2481.2, 2481.2, 2751.9, 3294.5", \ + "2470.9, 2470.9, 2470.9, 2741.6, 3284.2", \ + "2450.2, 2450.2, 2450.2, 2720.9, 3263.5", \ + "2405.0, 2405.0, 2405.0, 2677.5, 3221.7"); + } + fall_transition (inslew_load_5x5__11) { + values ("2351.5, 2351.5, 2351.5, 2775.2, 3622.7", \ + "2351.5, 2351.5, 2351.5, 2775.2, 3622.7", \ + "2351.5, 2351.5, 2351.5, 2775.2, 3622.7", \ + "2351.6, 2351.6, 2351.6, 2775.3, 3622.7", \ + "2362.6, 2362.6, 2362.6, 2783.5, 3626.9"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__11) { + values ("13556.5, 13556.5, 13556.5, 15445.4, 19223.0", \ + "13619.7, 13619.7, 13619.7, 15508.5, 19286.2", \ + "13746.0, 13746.0, 13746.0, 15634.8, 19412.5", \ + "13998.6, 13998.6, 13998.6, 15887.4, 19665.1", \ + "14503.8, 14503.8, 14503.8, 16392.6, 20170.3"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("7312.7, 7312.7, 7312.7, 9201.5, 12979.2", \ + "7363.1, 7363.1, 7363.1, 9251.9, 13029.6", \ + "7463.9, 7463.9, 7463.9, 9352.7, 13130.4", \ + "7665.5, 7665.5, 7665.5, 9554.3, 13332.0", \ + "8068.7, 8068.7, 8068.7, 9957.5, 13735.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__11) { + values ("1902.5, 1902.5, 1902.5, 3791.3, 7569.0", \ + "1966.2, 1966.2, 1966.2, 3855.1, 7632.8", \ + "2093.8, 2093.8, 2093.8, 3982.6, 7760.3", \ + "2348.9, 2348.9, 2348.9, 4237.8, 8015.4", \ + "2859.2, 2859.2, 2859.2, 4748.0, 8525.7"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("1971.7, 1971.7, 1971.7, 3860.6, 7638.2", \ + "2004.5, 2004.5, 2004.5, 3893.3, 7671.0", \ + "2070.0, 2070.0, 2070.0, 3958.8, 7736.5", \ + "2201.0, 2201.0, 2201.0, 4089.9, 7867.5", \ + "2463.1, 2463.1, 2463.1, 4351.9, 8129.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__11) { + values ("18890.4, 18890.4, 18890.4, 20779.2, 24556.9", \ + "18978.8, 18978.8, 18978.8, 20867.6, 24645.3", \ + "19155.6, 19155.6, 19155.6, 21044.4, 24822.1", \ + "19509.2, 19509.2, 19509.2, 21398.0, 25175.7", \ + "20216.3, 20216.3, 20216.3, 22105.2, 25882.9"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("13590.7, 13590.7, 13590.7, 15479.5, 19257.2", \ + "13636.4, 13636.4, 13636.4, 15525.2, 19302.9", \ + "13727.8, 13727.8, 13727.8, 15616.7, 19394.3", \ + "13910.7, 13910.7, 13910.7, 15799.5, 19577.2", \ + "14276.4, 14276.4, 14276.4, 16165.2, 19942.9"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__11) { + values ("7232.6, 7232.6, 7232.6, 9121.5, 12899.1", \ + "7317.9, 7317.9, 7317.9, 9206.8, 12984.4", \ + "7488.6, 7488.6, 7488.6, 9377.4, 13155.1", \ + "7829.8, 7829.8, 7829.8, 9718.6, 13496.3", \ + "8512.3, 8512.3, 8512.3, 10401.1, 14178.8"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("8250.4, 8250.4, 8250.4, 10139.3, 13917.0", \ + "8279.2, 8279.2, 8279.2, 10168.0, 13945.7", \ + "8336.7, 8336.7, 8336.7, 10225.5, 14003.2", \ + "8451.7, 8451.7, 8451.7, 10340.5, 14118.2", \ + "8681.7, 8681.7, 8681.7, 10570.5, 14348.2"); + } + } + } + } + + cell (oa22_x2) { + area : 21.60 ; + cell_leakage_power : 4.2 ; + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 4.5 ; + } + leakage_power () { + when : "(i0 & !((i1 ^ i2)))" ; + value : 4.4 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 4.3 ; + } + leakage_power () { + when : "(!(i0) & (i1 ^ i2))" ; + value : 4.2 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 3.7 ; + } + pin (i2) { + direction : input ; + capacitance : 440.12 ; + } + pin (i1) { + direction : input ; + capacitance : 432.62 ; + } + pin (i0) { + direction : input ; + capacitance : 432.96 ; + } + pin (q) { + function : "((i1 & (i2 | i0)) | i2)" ; + direction : output ; + capacitance : 89.41 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("7134.1, 7134.1, 7134.1, 7439.8, 8004.8", \ + "7129.0, 7129.0, 7129.0, 7434.7, 7999.7", \ + "7118.7, 7118.7, 7118.7, 7424.4, 7989.4", \ + "7098.0, 7098.0, 7098.0, 7403.7, 7968.7", \ + "7056.9, 7056.9, 7056.9, 7362.6, 7927.6"); + } + rise_transition (inslew_load_5x5__9) { + values ("3170.7, 3170.7, 3170.7, 3423.9, 3910.7", \ + "3170.7, 3170.7, 3170.7, 3423.9, 3910.7", \ + "3170.7, 3170.7, 3170.7, 3423.9, 3910.7", \ + "3170.7, 3170.7, 3170.7, 3423.9, 3910.7", \ + "3170.9, 3170.9, 3170.9, 3424.1, 3910.9"); + } + cell_fall (inslew_load_5x5__9) { + values ("7973.9, 7973.9, 7973.9, 8225.3, 8616.8", \ + "7982.2, 7982.2, 7982.2, 8233.7, 8625.1", \ + "7988.3, 7988.3, 7988.3, 8239.8, 8631.1", \ + "8006.0, 8006.0, 8006.0, 8257.6, 8648.8", \ + "8028.4, 8028.4, 8028.4, 8280.0, 8671.1"); + } + fall_transition (inslew_load_5x5__9) { + values ("3545.0, 3545.0, 3545.0, 3704.6, 3985.3", \ + "3551.7, 3551.7, 3551.7, 3711.1, 3991.5", \ + "3557.4, 3557.4, 3557.4, 3716.5, 3996.6", \ + "3567.5, 3567.5, 3567.5, 3726.3, 4005.9", \ + "3570.0, 3570.0, 3570.0, 3728.7, 4008.2"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("5829.5, 5829.5, 5829.5, 6157.7, 6748.7", \ + "5834.5, 5834.5, 5834.5, 6162.7, 6753.6", \ + "5841.9, 5841.9, 5841.9, 6170.1, 6761.0", \ + "5858.4, 5858.4, 5858.4, 6186.6, 6777.5", \ + "5892.1, 5892.1, 5892.1, 6220.3, 6811.2"); + } + rise_transition (inslew_load_5x5__9) { + values ("2271.9, 2271.9, 2271.9, 2550.7, 3062.0", \ + "2274.8, 2274.8, 2274.8, 2553.6, 3064.8", \ + "2275.7, 2275.7, 2275.7, 2554.5, 3065.7", \ + "2276.0, 2276.0, 2276.0, 2554.8, 3066.0", \ + "2276.4, 2276.4, 2276.4, 2555.2, 3066.3"); + } + cell_fall (inslew_load_5x5__9) { + values ("7210.0, 7210.0, 7210.0, 7458.5, 7959.7", \ + "7218.5, 7218.5, 7218.5, 7466.9, 7966.8", \ + "7224.8, 7224.8, 7224.8, 7473.3, 7971.9", \ + "7242.6, 7242.6, 7242.6, 7491.1, 7987.7", \ + "7265.0, 7265.0, 7265.0, 7513.5, 8009.5"); + } + fall_transition (inslew_load_5x5__9) { + values ("3055.9, 3055.9, 3055.9, 3245.3, 3608.1", \ + "3062.4, 3062.4, 3062.4, 3251.6, 3614.5", \ + "3068.0, 3068.0, 3068.0, 3256.8, 3619.9", \ + "3077.8, 3077.8, 3077.8, 3266.2, 3629.5", \ + "3080.2, 3080.2, 3080.2, 3268.5, 3631.9"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__9) { + values ("4224.1, 4224.1, 4224.1, 4600.2, 5237.5", \ + "4232.9, 4232.9, 4232.9, 4609.0, 5246.3", \ + "4250.5, 4250.5, 4250.5, 4626.6, 5263.9", \ + "4285.7, 4285.7, 4285.7, 4661.8, 5299.1", \ + "4357.8, 4357.8, 4357.8, 4733.7, 5370.8"); + } + rise_transition (inslew_load_5x5__9) { + values ("947.4, 947.4, 947.4, 1260.4, 1831.0", \ + "947.4, 947.4, 947.4, 1260.4, 1831.0", \ + "947.4, 947.4, 947.4, 1260.4, 1831.0", \ + "947.4, 947.4, 947.4, 1260.4, 1831.0", \ + "950.1, 950.1, 950.1, 1262.9, 1833.5"); + } + cell_fall (inslew_load_5x5__9) { + values ("9876.6, 9876.6, 9876.6, 10135.3, 10621.2", \ + "9871.3, 9871.3, 9871.3, 10130.0, 10615.9", \ + "9860.5, 9860.5, 9860.5, 10119.2, 10605.1", \ + "9839.1, 9839.1, 9839.1, 10097.8, 10583.7", \ + "9796.1, 9796.1, 9796.1, 10054.8, 10540.7"); + } + fall_transition (inslew_load_5x5__9) { + values ("4631.5, 4631.5, 4631.5, 4763.3, 5067.4", \ + "4631.5, 4631.5, 4631.5, 4763.3, 5067.4", \ + "4631.5, 4631.5, 4631.5, 4763.3, 5067.4", \ + "4631.5, 4631.5, 4631.5, 4763.3, 5067.4", \ + "4631.5, 4631.5, 4631.5, 4763.3, 5067.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__9) { + values ("26647.8, 26647.8, 26647.8, 27765.4, 30000.8", \ + "30015.1, 30015.1, 30015.1, 30015.1, 30015.1", \ + "30043.8, 30043.8, 30043.8, 30043.8, 30043.8", \ + "30101.3, 30101.3, 30101.3, 30101.3, 30101.3", \ + "26863.7, 26863.7, 26863.7, 27981.4, 30216.7"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("24876.6, 24876.6, 24876.6, 25994.3, 28229.6", \ + "24938.3, 24938.3, 24938.3, 26056.0, 28291.3", \ + "25039.7, 25039.7, 25039.7, 26157.3, 28392.7", \ + "25239.2, 25239.2, 25239.2, 26356.9, 28592.2", \ + "25587.4, 25587.4, 25587.4, 26705.1, 28940.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__9) { + values ("21686.9, 21686.9, 21686.9, 22804.5, 25039.9", \ + "21704.5, 21704.5, 21704.5, 22822.2, 25057.5", \ + "21728.9, 21728.9, 21728.9, 22846.5, 25081.9", \ + "21774.0, 21774.0, 21774.0, 22891.7, 25127.0", \ + "21863.8, 21863.8, 21863.8, 22981.5, 25216.8"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("22148.8, 22148.8, 22148.8, 23266.5, 25501.8", \ + "22208.9, 22208.9, 22208.9, 23326.5, 25561.9", \ + "22306.8, 22306.8, 22306.8, 23424.5, 25659.8", \ + "22499.4, 22499.4, 22499.4, 23617.0, 25852.4", \ + "22834.1, 22834.1, 22834.1, 23951.8, 26187.1"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__9) { + values ("23606.4, 23606.4, 23606.4, 24724.1, 26959.4", \ + "26982.3, 26982.3, 26982.3, 26982.3, 26982.3", \ + "27028.1, 27028.1, 27028.1, 27028.1, 27028.1", \ + "27119.7, 27119.7, 27119.7, 27119.7, 27119.7", \ + "23954.6, 23954.6, 23954.6, 25072.3, 27307.6"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("32551.2, 32551.2, 32551.2, 33668.9, 35904.2", \ + "35948.3, 35948.3, 35948.3, 35948.3, 35948.3", \ + "36036.5, 36036.5, 36036.5, 36036.5, 36036.5", \ + "36212.8, 36212.8, 36212.8, 36212.8, 36212.8", \ + "36565.5, 36565.5, 36565.5, 36565.5, 36565.5"); + } + } + } + } + + cell (o3_x4) { + area : 25.20 ; + cell_leakage_power : 7 ; + leakage_power () { + when : "((i0 & (!(i1) | !(i2))) | (i1 & !(i2)))" ; + value : 6.6 ; + } + leakage_power () { + when : "(!((i0 & !(i1))) & i2)" ; + value : 6.8 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 7.5 ; + } + pin (i2) { + direction : input ; + capacitance : 571.41 ; + } + pin (i1) { + direction : input ; + capacitance : 572.31 ; + } + pin (i0) { + direction : input ; + capacitance : 572.31 ; + } + pin (q) { + function : "(i0 | i1 | i2)" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("8087.6, 8087.6, 8087.6, 8349.5, 8836.5", \ + "8096.4, 8096.4, 8096.4, 8358.3, 8845.3", \ + "8114.0, 8114.0, 8114.0, 8375.9, 8862.9", \ + "8149.2, 8149.2, 8149.2, 8411.1, 8898.1", \ + "8219.6, 8219.6, 8219.6, 8481.5, 8968.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("3347.1, 3347.1, 3347.1, 3561.5, 3973.0", \ + "3347.1, 3347.1, 3347.1, 3561.5, 3973.0", \ + "3347.1, 3347.1, 3347.1, 3561.5, 3973.0", \ + "3347.1, 3347.1, 3347.1, 3561.5, 3973.0", \ + "3347.2, 3347.2, 3347.2, 3561.5, 3973.1"); + } + cell_fall (inslew_load_5x5__3) { + values ("16347.6, 16347.6, 16347.6, 16564.0, 16991.7", \ + "16336.3, 16336.3, 16336.3, 16552.7, 16980.4", \ + "16313.6, 16313.6, 16313.6, 16530.0, 16957.7", \ + "16268.3, 16268.3, 16268.3, 16484.7, 16912.4", \ + "16177.6, 16177.6, 16177.6, 16394.0, 16821.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("9282.5, 9282.5, 9282.5, 9457.6, 9777.8", \ + "9282.5, 9282.5, 9282.5, 9457.6, 9777.8", \ + "9282.5, 9282.5, 9282.5, 9457.6, 9777.8", \ + "9282.5, 9282.5, 9282.5, 9457.6, 9777.8", \ + "9282.5, 9282.5, 9282.5, 9457.6, 9777.8"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("7440.5, 7440.5, 7440.5, 7705.8, 8201.2", \ + "7449.3, 7449.3, 7449.3, 7714.6, 8210.0", \ + "7466.9, 7466.9, 7466.9, 7732.1, 8227.6", \ + "7502.1, 7502.1, 7502.1, 7767.4, 8262.8", \ + "7572.6, 7572.6, 7572.6, 7837.8, 8333.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("2938.5, 2938.5, 2938.5, 3159.5, 3583.0", \ + "2938.5, 2938.5, 2938.5, 3159.5, 3583.0", \ + "2938.4, 2938.4, 2938.4, 3159.4, 3582.9", \ + "2938.5, 2938.5, 2938.5, 3159.5, 3583.0", \ + "2938.6, 2938.6, 2938.6, 3159.5, 3583.1"); + } + cell_fall (inslew_load_5x5__3) { + values ("13380.4, 13380.4, 13380.4, 13596.7, 14103.5", \ + "13374.0, 13374.0, 13374.0, 13590.4, 14096.9", \ + "13365.4, 13365.4, 13365.4, 13581.9, 14087.9", \ + "13346.5, 13346.5, 13346.5, 13562.9, 14068.6", \ + "13309.4, 13309.4, 13309.4, 13525.8, 14031.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("7539.5, 7539.5, 7539.5, 7707.9, 8021.4", \ + "7541.0, 7541.0, 7541.0, 7709.4, 8023.0", \ + "7545.1, 7545.1, 7545.1, 7713.5, 8027.3", \ + "7548.2, 7548.2, 7548.2, 7716.7, 8030.5", \ + "7548.6, 7548.6, 7548.6, 7716.9, 8030.8"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("6192.0, 6192.0, 6192.0, 6478.1, 6997.4", \ + "6200.8, 6200.8, 6200.8, 6486.9, 7006.2", \ + "6218.4, 6218.4, 6218.4, 6504.5, 7023.8", \ + "6253.6, 6253.6, 6253.6, 6539.7, 7059.0", \ + "6324.3, 6324.3, 6324.3, 6610.3, 7129.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("2119.2, 2119.2, 2119.2, 2363.4, 2811.0", \ + "2119.2, 2119.2, 2119.2, 2363.4, 2811.0", \ + "2119.2, 2119.2, 2119.2, 2363.4, 2811.0", \ + "2119.2, 2119.2, 2119.2, 2363.4, 2811.0", \ + "2119.6, 2119.6, 2119.6, 2363.8, 2811.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("10575.1, 10575.1, 10575.1, 10873.0, 11411.9", \ + "10589.6, 10589.6, 10589.6, 10888.0, 11428.4", \ + "10591.2, 10591.2, 10591.2, 10890.1, 11431.4", \ + "10615.1, 10615.1, 10615.1, 10914.9, 11459.1", \ + "10634.9, 10634.9, 10634.9, 10934.8, 11481.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("5807.0, 5807.0, 5807.0, 5962.2, 6209.2", \ + "5822.3, 5822.3, 5822.3, 5978.1, 6225.4", \ + "5832.2, 5832.2, 5832.2, 5988.5, 6236.1", \ + "5861.1, 5861.1, 5861.1, 6018.4, 6266.8", \ + "5883.7, 5883.7, 5883.7, 6041.3, 6290.9"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("54031.7, 54031.7, 54031.7, 55927.5, 59719.2", \ + "59757.4, 59757.4, 59757.4, 59757.4, 59757.4", \ + "59833.9, 59833.9, 59833.9, 59833.9, 59833.9", \ + "59987.0, 59987.0, 59987.0, 59987.0, 59987.0", \ + "54605.8, 54605.8, 54605.8, 56501.7, 60293.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("96411.2, 96411.2, 96411.2, 98307.0, 102098.7", \ + "102142.2, 102142.2, 102142.2, 102142.2, 102142.2", \ + "102229.2, 102229.2, 102229.2, 102229.2, 102229.2", \ + "102403.1, 102403.1, 102403.1, 102403.1, 102403.1", \ + "102751.0, 102751.0, 102751.0, 102751.0, 102751.0"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("49666.6, 49666.6, 49666.6, 51562.4, 55354.1", \ + "55379.3, 55379.3, 55379.3, 55379.3, 55379.3", \ + "49741.8, 49741.8, 49741.8, 51637.7, 55429.3", \ + "55530.2, 55530.2, 55530.2, 55530.2, 55530.2", \ + "50045.0, 50045.0, 50045.0, 51940.9, 55732.5"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("77133.8, 77133.8, 77133.8, 79029.6, 82821.3", \ + "77187.4, 77187.4, 77187.4, 79083.2, 82874.9", \ + "77301.4, 77301.4, 77301.4, 79197.2, 82988.9", \ + "77497.7, 77497.7, 77497.7, 79393.5, 83185.2", \ + "77853.4, 77853.4, 77853.4, 79749.2, 83540.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("41580.6, 41580.6, 41580.6, 43476.4, 47268.1", \ + "47286.1, 47286.1, 47286.1, 47286.1, 47286.1", \ + "47322.0, 47322.0, 47322.0, 47322.0, 47322.0", \ + "47393.8, 47393.8, 47393.8, 47393.8, 47393.8", \ + "41851.6, 41851.6, 41851.6, 43747.4, 47539.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("58521.8, 58521.8, 58521.8, 60417.6, 64209.3", \ + "58659.5, 58659.5, 58659.5, 60555.4, 64347.0", \ + "58808.0, 58808.0, 58808.0, 60703.8, 64495.5", \ + "59159.8, 59159.8, 59159.8, 61055.7, 64847.3", \ + "59647.6, 59647.6, 59647.6, 61543.5, 65335.2"); + } + } + } + } + + cell (o2_x4) { + area : 21.60 ; + cell_leakage_power : 6.5 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 6.6 ; + } + leakage_power () { + when : "i1" ; + value : 6.8 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 6.1 ; + } + pin (i1) { + direction : input ; + capacitance : 572.31 ; + } + pin (i0) { + direction : input ; + capacitance : 578.67 ; + } + pin (q) { + function : "(i0 | i1)" ; + direction : output ; + capacitance : 151.95 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("7376.1, 7376.1, 7376.1, 7642.3, 8141.0", \ + "7384.9, 7384.9, 7384.9, 7651.1, 8149.8", \ + "7402.5, 7402.5, 7402.5, 7668.7, 8167.4", \ + "7437.7, 7437.7, 7437.7, 7703.9, 8202.6", \ + "7508.2, 7508.2, 7508.2, 7774.4, 8273.1"); + } + rise_transition (inslew_load_5x5__14) { + values ("2899.1, 2899.1, 2899.1, 3121.3, 3547.0", \ + "2899.1, 2899.1, 2899.1, 3121.3, 3547.0", \ + "2899.1, 2899.1, 2899.1, 3121.3, 3547.0", \ + "2899.1, 2899.1, 2899.1, 3121.3, 3547.0", \ + "2899.2, 2899.2, 2899.2, 3121.5, 3547.2"); + } + cell_fall (inslew_load_5x5__14) { + values ("10668.3, 10668.3, 10668.3, 11011.0, 11436.1", \ + "10662.9, 10662.9, 10662.9, 11005.6, 11430.7", \ + "10652.2, 10652.2, 10652.2, 10994.9, 11420.0", \ + "10630.8, 10630.8, 10630.8, 10973.5, 11398.6", \ + "10587.9, 10587.9, 10587.9, 10930.6, 11355.7"); + } + fall_transition (inslew_load_5x5__14) { + values ("5305.7, 5305.7, 5305.7, 5456.3, 5678.7", \ + "5305.7, 5305.7, 5305.7, 5456.3, 5678.7", \ + "5305.7, 5305.7, 5305.7, 5456.3, 5678.7", \ + "5305.7, 5305.7, 5305.7, 5456.3, 5678.7", \ + "5305.7, 5305.7, 5305.7, 5456.3, 5678.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("6124.6, 6124.6, 6124.6, 6411.8, 6933.1", \ + "6133.4, 6133.4, 6133.4, 6420.6, 6941.9", \ + "6151.0, 6151.0, 6151.0, 6438.2, 6959.5", \ + "6186.2, 6186.2, 6186.2, 6473.4, 6994.7", \ + "6256.8, 6256.8, 6256.8, 6544.0, 7065.4"); + } + rise_transition (inslew_load_5x5__14) { + values ("2074.6, 2074.6, 2074.6, 2320.2, 2770.6", \ + "2074.6, 2074.6, 2074.6, 2320.2, 2770.6", \ + "2074.6, 2074.6, 2074.6, 2320.2, 2770.6", \ + "2074.6, 2074.6, 2074.6, 2320.2, 2770.6", \ + "2075.0, 2075.0, 2075.0, 2320.6, 2770.9"); + } + cell_fall (inslew_load_5x5__14) { + values ("8409.8, 8409.8, 8409.8, 8626.9, 9036.7", \ + "8412.6, 8412.6, 8412.6, 8629.6, 9039.5", \ + "8421.6, 8421.6, 8421.6, 8638.7, 9048.7", \ + "8434.0, 8434.0, 8434.0, 8651.1, 9061.1", \ + "8462.4, 8462.4, 8462.4, 8679.5, 9089.4"); + } + fall_transition (inslew_load_5x5__14) { + values ("3961.5, 3961.5, 3961.5, 4081.6, 4356.3", \ + "3964.4, 3964.4, 3964.4, 4084.5, 4359.1", \ + "3970.4, 3970.4, 3970.4, 4090.3, 4364.9", \ + "3973.7, 3973.7, 3973.7, 4093.4, 4367.7", \ + "3974.2, 3974.2, 3974.2, 4093.9, 4368.1"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__14) { + values ("49245.5, 49245.5, 49245.5, 51144.8, 54943.5", \ + "54981.7, 54981.7, 54981.7, 54981.7, 54981.7", \ + "55058.2, 55058.2, 55058.2, 55058.2, 55058.2", \ + "55211.3, 55211.3, 55211.3, 55211.3, 55211.3", \ + "49820.0, 49820.0, 49820.0, 51719.3, 55518.0"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("63836.9, 63836.9, 63836.9, 65736.2, 69534.9", \ + "69578.4, 69578.4, 69578.4, 69578.4, 69578.4", \ + "69665.4, 69665.4, 69665.4, 69665.4, 69665.4", \ + "69839.3, 69839.3, 69839.3, 69839.3, 69839.3", \ + "70187.2, 70187.2, 70187.2, 70187.2, 70187.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__14) { + values ("41154.1, 41154.1, 41154.1, 43053.4, 46852.1", \ + "46877.3, 46877.3, 46877.3, 46877.3, 46877.3", \ + "46927.7, 46927.7, 46927.7, 46927.7, 46927.7", \ + "47028.5, 47028.5, 47028.5, 47028.5, 47028.5", \ + "41533.9, 41533.9, 41533.9, 43433.3, 47231.9"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("47285.2, 47285.2, 47285.2, 49184.5, 52983.2", \ + "47346.0, 47346.0, 47346.0, 49245.4, 53044.1", \ + "47467.8, 47467.8, 47467.8, 49367.1, 53165.8", \ + "47663.0, 47663.0, 47663.0, 49562.3, 53361.0", \ + "48019.6, 48019.6, 48019.6, 49918.9, 53717.6"); + } + } + } + } + + cell (a2_x4) { + area : 21.60 ; + cell_leakage_power : 5.9 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 7.2 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 5.7 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 6.1 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 4.7 ; + } + pin (i1) { + direction : input ; + capacitance : 576.29 ; + } + pin (i0) { + direction : input ; + capacitance : 564.79 ; + } + pin (q) { + function : "(i1 & i0)" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("4917.7, 4917.7, 4917.7, 5206.8, 5731.9", \ + "4923.2, 4923.2, 4923.2, 5212.3, 5737.3", \ + "4930.2, 4930.2, 4930.2, 5219.3, 5744.3", \ + "4947.0, 4947.0, 4947.0, 5236.1, 5761.0", \ + "4981.3, 4981.3, 4981.3, 5270.4, 5795.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("1873.5, 1873.5, 1873.5, 2122.0, 2579.3", \ + "1876.7, 1876.7, 1876.7, 2125.1, 2582.3", \ + "1877.2, 1877.2, 1877.2, 2125.7, 2582.8", \ + "1877.7, 1877.7, 1877.7, 2126.1, 2583.2", \ + "1879.2, 1879.2, 1879.2, 2127.6, 2584.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("8174.8, 8174.8, 8174.8, 8386.3, 8808.8", \ + "8183.6, 8183.6, 8183.6, 8395.1, 8817.6", \ + "8201.1, 8201.1, 8201.1, 8412.6, 8835.1", \ + "8236.3, 8236.3, 8236.3, 8447.8, 8870.3", \ + "8306.7, 8306.7, 8306.7, 8518.2, 8940.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("2996.3, 2996.3, 2996.3, 3157.2, 3480.1", \ + "2996.3, 2996.3, 2996.3, 3157.2, 3480.1", \ + "2996.3, 2996.3, 2996.3, 3157.2, 3480.1", \ + "2996.3, 2996.3, 2996.3, 3157.2, 3480.1", \ + "2996.3, 2996.3, 2996.3, 3157.2, 3480.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("6247.6, 6247.6, 6247.6, 6514.0, 7015.7", \ + "6242.4, 6242.4, 6242.4, 6508.8, 7010.6", \ + "6232.1, 6232.1, 6232.1, 6498.5, 7000.3", \ + "6211.5, 6211.5, 6211.5, 6477.9, 6979.7", \ + "6170.5, 6170.5, 6170.5, 6436.9, 6938.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("2818.4, 2818.4, 2818.4, 3041.6, 3468.9", \ + "2818.5, 2818.5, 2818.5, 3041.7, 3468.9", \ + "2818.5, 2818.5, 2818.5, 3041.7, 3468.9", \ + "2818.5, 2818.5, 2818.5, 3041.7, 3468.9", \ + "2819.0, 2819.0, 2819.0, 3042.2, 3469.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("9210.1, 9210.1, 9210.1, 9327.0, 9737.9", \ + "9218.9, 9218.9, 9218.9, 9335.8, 9746.7", \ + "9236.5, 9236.5, 9236.5, 9353.4, 9764.3", \ + "9271.6, 9271.6, 9271.6, 9388.5, 9799.4", \ + "9342.0, 9342.0, 9342.0, 9458.9, 9869.8"); + } + fall_transition (inslew_load_5x5__3) { + values ("3559.7, 3559.7, 3559.7, 3595.1, 3905.6", \ + "3559.7, 3559.7, 3559.7, 3595.1, 3905.6", \ + "3559.7, 3559.7, 3559.7, 3595.1, 3905.6", \ + "3559.7, 3559.7, 3559.7, 3595.1, 3905.6", \ + "3559.7, 3559.7, 3559.7, 3595.1, 3905.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("40440.1, 40440.1, 40440.1, 42336.0, 46127.6", \ + "40472.8, 40472.8, 40472.8, 42368.6, 46160.3", \ + "40514.4, 40514.4, 40514.4, 42410.2, 46201.9", \ + "40594.4, 40594.4, 40594.4, 42490.3, 46281.9", \ + "40757.3, 40757.3, 40757.3, 42653.2, 46444.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("42588.8, 42588.8, 42588.8, 44484.6, 48276.3", \ + "48337.8, 48337.8, 48337.8, 48337.8, 48337.8", \ + "48460.8, 48460.8, 48460.8, 48460.8, 48460.8", \ + "48706.8, 48706.8, 48706.8, 48706.8, 48706.8", \ + "49198.9, 49198.9, 49198.9, 49198.9, 49198.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("50314.5, 50314.5, 50314.5, 52210.3, 56002.0", \ + "50331.4, 50331.4, 50331.4, 52227.3, 56018.9", \ + "56052.1, 56052.1, 56052.1, 56052.1, 56052.1", \ + "56118.5, 56118.5, 56118.5, 56118.5, 56118.5", \ + "50566.2, 50566.2, 50566.2, 52462.0, 56253.7"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("48704.1, 48704.1, 48704.1, 50599.9, 54391.6", \ + "54470.4, 54470.4, 54470.4, 54470.4, 54470.4", \ + "54628.0, 54628.0, 54628.0, 54628.0, 54628.0", \ + "54943.3, 54943.3, 54943.3, 54943.3, 54943.3", \ + "55573.7, 55573.7, 55573.7, 55573.7, 55573.7"); + } + } + } + } + + cell (noa2a22_x1) { + area : 25.20 ; + cell_leakage_power : 5.1 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 6.6 ; + } + leakage_power () { + when : "(i0 & i1 & (!(i2) | !(i3)))" ; + value : 6.7 ; + } + leakage_power () { + when : "(!(i3) & i2 & !(i1) & i0)" ; + value : 5.5 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3)" ; + value : 6.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3) | (!(i0) & i1 & i2 & !(i3)))" ; + value : 5.1 ; + } + leakage_power () { + when : "(i3 & !(i2) & i1 & !(i0))" ; + value : 4.7 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 5.7 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & !(i1) & i2 & !(i3)))" ; + value : 4.1 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & !(i2) & i3)))" ; + value : 3.8 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 2.8 ; + } + pin (i3) { + direction : input ; + capacitance : 850.57 ; + } + pin (i2) { + direction : input ; + capacitance : 849.07 ; + } + pin (i1) { + direction : input ; + capacitance : 848.02 ; + } + pin (i0) { + direction : input ; + capacitance : 846.52 ; + } + pin (nq) { + function : "((((!(i1) & !(i3)) | (!(i1) & !(i2))) | (!(i0) & !(i3))) | (!(i0) & !(i2)))" ; + direction : output ; + capacitance : 150.55 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("2955.7, 2955.7, 2955.7, 3410.8, 4322.0", \ + "2965.8, 2965.8, 2965.8, 3421.1, 4332.5", \ + "2973.9, 2973.9, 2973.9, 3428.9, 4339.9", \ + "2990.8, 2990.8, 2990.8, 3446.5, 4358.7", \ + "3010.9, 3010.9, 3010.9, 3468.3, 4382.3"); + } + rise_transition (inslew_load_5x5__20) { + values ("2585.4, 2585.4, 2585.4, 3311.3, 4766.5", \ + "2606.6, 2606.6, 2606.6, 3332.7, 4788.3", \ + "2626.4, 2626.4, 2626.4, 3351.9, 4806.8", \ + "2656.4, 2656.4, 2656.4, 3383.1, 4839.9", \ + "2674.0, 2674.0, 2674.0, 3400.4, 4857.4"); + } + cell_fall (inslew_load_5x5__20) { + values ("2393.3, 2393.3, 2393.3, 2663.5, 3204.7", \ + "2388.1, 2388.1, 2388.1, 2658.3, 3199.5", \ + "2377.8, 2377.8, 2377.8, 2648.0, 3189.2", \ + "2357.1, 2357.1, 2357.1, 2627.3, 3168.6", \ + "2311.0, 2311.0, 2311.0, 2583.5, 3126.6"); + } + fall_transition (inslew_load_5x5__20) { + values ("2210.5, 2210.5, 2210.5, 2632.6, 3477.0", \ + "2210.5, 2210.5, 2210.5, 2632.6, 3477.0", \ + "2210.5, 2210.5, 2210.5, 2632.6, 3477.0", \ + "2210.7, 2210.7, 2210.7, 2632.7, 3477.0", \ + "2222.8, 2222.8, 2222.8, 2641.9, 3481.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("2169.4, 2169.4, 2169.4, 2630.6, 3544.9", \ + "2179.5, 2179.5, 2179.5, 2640.7, 3555.2", \ + "2188.6, 2188.6, 2188.6, 2649.2, 3562.9", \ + "2204.7, 2204.7, 2204.7, 2665.7, 3580.8", \ + "2217.3, 2217.3, 2217.3, 2683.8, 3603.1"); + } + rise_transition (inslew_load_5x5__20) { + values ("1362.0, 1362.0, 1362.0, 2089.2, 3540.9", \ + "1383.1, 1383.1, 1383.1, 2110.3, 3562.4", \ + "1404.3, 1404.3, 1404.3, 2130.7, 3581.4", \ + "1433.2, 1433.2, 1433.2, 2160.0, 3613.0", \ + "1452.9, 1452.9, 1452.9, 2178.3, 3630.2"); + } + cell_fall (inslew_load_5x5__20) { + values ("1559.0, 1559.0, 1559.0, 1836.0, 2385.5", \ + "1561.5, 1561.5, 1561.5, 1838.5, 2388.3", \ + "1570.5, 1570.5, 1570.5, 1847.2, 2396.4", \ + "1585.7, 1585.7, 1585.7, 1862.9, 2412.4", \ + "1592.1, 1592.1, 1592.1, 1882.0, 2441.6"); + } + fall_transition (inslew_load_5x5__20) { + values ("947.8, 947.8, 947.8, 1377.0, 2235.0", \ + "949.6, 949.6, 949.6, 1379.1, 2237.6", \ + "953.8, 953.8, 953.8, 1382.9, 2240.3", \ + "954.2, 954.2, 954.2, 1383.0, 2240.2", \ + "967.8, 967.8, 967.8, 1397.6, 2249.7"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("6161.6, 6161.6, 6161.6, 6595.9, 7484.2", \ + "6156.2, 6156.2, 6156.2, 6590.5, 7478.8", \ + "6145.3, 6145.3, 6145.3, 6579.7, 7468.1", \ + "6123.5, 6123.5, 6123.5, 6558.0, 7446.5", \ + "6079.9, 6079.9, 6079.9, 6514.7, 7403.5"); + } + rise_transition (inslew_load_5x5__20) { + values ("7496.0, 7496.0, 7496.0, 8213.6, 9648.8", \ + "7496.0, 7496.0, 7496.0, 8213.6, 9648.8", \ + "7496.0, 7496.0, 7496.0, 8213.6, 9648.8", \ + "7496.0, 7496.0, 7496.0, 8213.6, 9648.8", \ + "7496.1, 7496.1, 7496.1, 8213.7, 9648.8"); + } + cell_fall (inslew_load_5x5__20) { + values ("3779.4, 3779.4, 3779.4, 4041.0, 4572.9", \ + "3774.2, 3774.2, 3774.2, 4035.8, 4567.7", \ + "3763.8, 3763.8, 3763.8, 4025.4, 4557.4", \ + "3743.1, 3743.1, 3743.1, 4004.8, 4536.7", \ + "3701.5, 3701.5, 3701.5, 3963.3, 4495.4"); + } + fall_transition (inslew_load_5x5__20) { + values ("4308.3, 4308.3, 4308.3, 4730.5, 5574.8", \ + "4308.3, 4308.3, 4308.3, 4730.5, 5574.8", \ + "4308.3, 4308.3, 4308.3, 4730.5, 5574.8", \ + "4308.3, 4308.3, 4308.3, 4730.5, 5574.8", \ + "4310.5, 4310.5, 4310.5, 4732.1, 5575.6"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("5375.6, 5375.6, 5375.6, 5815.1, 6708.7", \ + "5370.1, 5370.1, 5370.1, 5809.7, 6703.3", \ + "5359.3, 5359.3, 5359.3, 5798.9, 6692.5", \ + "5337.6, 5337.6, 5337.6, 5777.3, 6671.0", \ + "5294.1, 5294.1, 5294.1, 5734.1, 6628.0"); + } + rise_transition (inslew_load_5x5__20) { + values ("6287.5, 6287.5, 6287.5, 7005.1, 8440.3", \ + "6287.5, 6287.5, 6287.5, 7005.1, 8440.3", \ + "6287.5, 6287.5, 6287.5, 7005.1, 8440.3", \ + "6287.5, 6287.5, 6287.5, 7005.1, 8440.3", \ + "6287.8, 6287.8, 6287.8, 7005.3, 8440.4"); + } + cell_fall (inslew_load_5x5__20) { + values ("2952.1, 2952.1, 2952.1, 3220.4, 3761.1", \ + "2955.2, 2955.2, 2955.2, 3223.6, 3764.5", \ + "2962.8, 2962.8, 2962.8, 3231.1, 3771.7", \ + "2978.9, 2978.9, 2978.9, 3247.3, 3788.0", \ + "3011.0, 3011.0, 3011.0, 3279.9, 3821.2"); + } + fall_transition (inslew_load_5x5__20) { + values ("3080.1, 3080.1, 3080.1, 3509.4, 4368.2", \ + "3083.1, 3083.1, 3083.1, 3512.5, 4371.5", \ + "3085.1, 3085.1, 3085.1, 3514.3, 4372.9", \ + "3085.2, 3085.2, 3085.2, 3514.4, 4373.2", \ + "3089.7, 3089.7, 3089.7, 3517.6, 4374.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__20) { + values ("5086.2, 5086.2, 5086.2, 6968.0, 10731.7", \ + "5171.5, 5171.5, 5171.5, 7053.3, 10817.0", \ + "5342.1, 5342.1, 5342.1, 7224.0, 10987.6", \ + "5683.4, 5683.4, 5683.4, 7565.2, 11328.9", \ + "6365.8, 6365.8, 6365.8, 8247.7, 12011.3"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("7621.9, 7621.9, 7621.9, 9503.7, 13267.4", \ + "7650.7, 7650.7, 7650.7, 9532.5, 13296.2", \ + "7708.2, 7708.2, 7708.2, 9590.0, 13353.7", \ + "7823.2, 7823.2, 7823.2, 9705.0, 13468.7", \ + "8053.2, 8053.2, 8053.2, 9935.0, 13698.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__20) { + values ("1895.5, 1895.5, 1895.5, 3777.3, 7541.0", \ + "1959.2, 1959.2, 1959.2, 3841.1, 7604.8", \ + "2086.8, 2086.8, 2086.8, 3968.6, 7732.3", \ + "2341.9, 2341.9, 2341.9, 4223.8, 7987.5", \ + "2852.2, 2852.2, 2852.2, 4734.0, 8497.7"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("1964.7, 1964.7, 1964.7, 3846.6, 7610.2", \ + "1997.5, 1997.5, 1997.5, 3879.3, 7643.0", \ + "2063.0, 2063.0, 2063.0, 3944.8, 7708.5", \ + "2194.0, 2194.0, 2194.0, 4075.9, 7839.5", \ + "2456.1, 2456.1, 2456.1, 4337.9, 8101.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__20) { + values ("17854.4, 17854.4, 17854.4, 19736.2, 23499.9", \ + "17942.8, 17942.8, 17942.8, 19824.6, 23588.3", \ + "18119.6, 18119.6, 18119.6, 20001.4, 23765.1", \ + "18473.2, 18473.2, 18473.2, 20355.0, 24118.7", \ + "19180.3, 19180.3, 19180.3, 21062.2, 24825.9"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("16990.3, 16990.3, 16990.3, 18872.1, 22635.8", \ + "17036.0, 17036.0, 17036.0, 18917.8, 22681.5", \ + "17127.4, 17127.4, 17127.4, 19009.3, 22772.9", \ + "17310.3, 17310.3, 17310.3, 19192.1, 22955.8", \ + "17676.0, 17676.0, 17676.0, 19557.8, 23321.5"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__20) { + values ("14660.0, 14660.0, 14660.0, 16541.8, 20305.5", \ + "14723.1, 14723.1, 14723.1, 16604.9, 20368.6", \ + "14849.4, 14849.4, 14849.4, 16731.2, 20494.9", \ + "15102.0, 15102.0, 15102.0, 16983.8, 20747.5", \ + "15607.2, 15607.2, 15607.2, 17489.0, 21252.7"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("11333.8, 11333.8, 11333.8, 13215.6, 16979.3", \ + "11384.2, 11384.2, 11384.2, 13266.0, 17029.7", \ + "11485.0, 11485.0, 11485.0, 13366.8, 17130.5", \ + "11686.6, 11686.6, 11686.6, 13568.5, 17332.1", \ + "12089.8, 12089.8, 12089.8, 13971.7, 17735.4"); + } + } + } + } + + cell (buf_x4) { + area : 18.00 ; + cell_leakage_power : 5.6 ; + leakage_power () { + when : "i" ; + value : 6.4 ; + } + leakage_power () { + when : "!(i)" ; + value : 4.7 ; + } + pin (i) { + direction : input ; + capacitance : 439.40 ; + } + pin (q) { + function : "i" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_q_i_positive_unate) { + related_pin : "i" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("5689.5, 5689.5, 5689.5, 5977.9, 6501.3", \ + "5698.3, 5698.3, 5698.3, 5986.7, 6510.1", \ + "5715.9, 5715.9, 5715.9, 6004.3, 6527.7", \ + "5751.1, 5751.1, 5751.1, 6039.5, 6562.9", \ + "5821.9, 5821.9, 5821.9, 6110.3, 6633.7"); + } + rise_transition (inslew_load_5x5__3) { + values ("1960.5, 1960.5, 1960.5, 2208.1, 2662.6", \ + "1960.5, 1960.5, 1960.5, 2208.1, 2662.6", \ + "1960.5, 1960.5, 1960.5, 2208.1, 2662.6", \ + "1960.5, 1960.5, 1960.5, 2208.1, 2662.6", \ + "1961.1, 1961.1, 1961.1, 2208.7, 2663.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("7570.4, 7570.4, 7570.4, 7781.7, 8227.6", \ + "7579.2, 7579.2, 7579.2, 7790.5, 8236.4", \ + "7596.8, 7596.8, 7596.8, 7808.1, 8254.0", \ + "7632.0, 7632.0, 7632.0, 7843.3, 8289.2", \ + "7702.3, 7702.3, 7702.3, 7913.6, 8359.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("2917.0, 2917.0, 2917.0, 3082.0, 3403.8", \ + "2917.0, 2917.0, 2917.0, 3082.0, 3403.8", \ + "2917.0, 2917.0, 2917.0, 3082.0, 3403.8", \ + "2917.0, 2917.0, 2917.0, 3082.0, 3403.8", \ + "2917.0, 2917.0, 2917.0, 3082.0, 3403.8"); + } + } + internal_power (energy_pos_q_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__3) { + values ("40392.4, 40392.4, 40392.4, 42288.2, 46079.9", \ + "46102.8, 46102.8, 46102.8, 46102.8, 46102.8", \ + "46148.6, 46148.6, 46148.6, 46148.6, 46148.6", \ + "46240.2, 46240.2, 46240.2, 46240.2, 46240.2", \ + "40738.7, 40738.7, 40738.7, 42634.5, 46426.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("41666.0, 41666.0, 41666.0, 43561.8, 47353.5", \ + "47397.6, 47397.6, 47397.6, 47397.6, 47397.6", \ + "47485.8, 47485.8, 47485.8, 47485.8, 47485.8", \ + "47662.1, 47662.1, 47662.1, 47662.1, 47662.1", \ + "48014.8, 48014.8, 48014.8, 48014.8, 48014.8"); + } + } + } + } + + cell (an12_x4) { + area : 28.80 ; + cell_leakage_power : 7 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 6.9 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 5.5 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 8.6 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 7.1 ; + } + pin (i1) { + direction : input ; + capacitance : 576.29 ; + } + pin (i0) { + direction : input ; + capacitance : 438.92 ; + } + pin (q) { + function : "(!(i0) & i1)" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("6247.9, 6247.9, 6247.9, 6514.3, 7016.0", \ + "6242.7, 6242.7, 6242.7, 6509.1, 7010.8", \ + "6232.4, 6232.4, 6232.4, 6498.8, 7000.5", \ + "6211.8, 6211.8, 6211.8, 6478.2, 6979.9", \ + "6170.8, 6170.8, 6170.8, 6437.2, 6938.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("2818.6, 2818.6, 2818.6, 3041.8, 3469.1", \ + "2818.6, 2818.6, 2818.6, 3041.8, 3469.1", \ + "2818.6, 2818.6, 2818.6, 3041.8, 3469.1", \ + "2818.6, 2818.6, 2818.6, 3041.8, 3469.1", \ + "2819.2, 2819.2, 2819.2, 3042.4, 3469.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("9210.4, 9210.4, 9210.4, 9327.3, 9738.2", \ + "9219.1, 9219.1, 9219.1, 9336.0, 9746.9", \ + "9236.7, 9236.7, 9236.7, 9353.6, 9764.5", \ + "9271.9, 9271.9, 9271.9, 9388.8, 9799.7", \ + "9342.3, 9342.3, 9342.3, 9459.2, 9870.1"); + } + fall_transition (inslew_load_5x5__3) { + values ("3559.8, 3559.8, 3559.8, 3595.2, 3905.7", \ + "3559.8, 3559.8, 3559.8, 3595.2, 3905.7", \ + "3559.8, 3559.8, 3559.8, 3595.2, 3905.7", \ + "3559.8, 3559.8, 3559.8, 3595.2, 3905.7", \ + "3559.8, 3559.8, 3559.8, 3595.2, 3905.7"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("8916.1, 8916.1, 8916.1, 9199.8, 9716.3", \ + "8924.9, 8924.9, 8924.9, 9208.6, 9725.1", \ + "8942.4, 8942.4, 8942.4, 9226.1, 9742.6", \ + "8977.6, 8977.6, 8977.6, 9261.3, 9777.8", \ + "9048.4, 9048.4, 9048.4, 9332.0, 9848.5"); + } + rise_transition (inslew_load_5x5__3) { + values ("2312.0, 2312.0, 2312.0, 2553.0, 2994.6", \ + "2312.0, 2312.0, 2312.0, 2553.0, 2994.6", \ + "2312.0, 2312.0, 2312.0, 2553.0, 2994.6", \ + "2312.0, 2312.0, 2312.0, 2553.0, 2994.6", \ + "2312.8, 2312.8, 2312.8, 2553.8, 2995.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("10781.7, 10781.7, 10781.7, 10993.1, 11409.9", \ + "10790.5, 10790.5, 10790.5, 11001.9, 11418.7", \ + "10808.1, 10808.1, 10808.1, 11019.5, 11436.3", \ + "10843.4, 10843.4, 10843.4, 11054.8, 11471.6", \ + "10912.7, 10912.7, 10912.7, 11124.1, 11540.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("3019.7, 3019.7, 3019.7, 3179.6, 3502.5", \ + "3019.7, 3019.7, 3019.7, 3179.6, 3502.5", \ + "3019.7, 3019.7, 3019.7, 3179.6, 3502.5", \ + "3019.7, 3019.7, 3019.7, 3179.6, 3502.5", \ + "3020.0, 3020.0, 3020.0, 3179.9, 3502.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("50316.8, 50316.8, 50316.8, 52212.6, 56004.3", \ + "56020.9, 56020.9, 56020.9, 56020.9, 56020.9", \ + "56054.1, 56054.1, 56054.1, 56054.1, 56054.1", \ + "56120.5, 56120.5, 56120.5, 56120.5, 56120.5", \ + "50568.5, 50568.5, 50568.5, 52464.3, 56256.0"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("48706.2, 48706.2, 48706.2, 50602.1, 54393.7", \ + "54472.6, 54472.6, 54472.6, 54472.6, 54472.6", \ + "54630.2, 54630.2, 54630.2, 54630.2, 54630.2", \ + "54945.4, 54945.4, 54945.4, 54945.4, 54945.4", \ + "55575.9, 55575.9, 55575.9, 55575.9, 55575.9"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("51241.7, 51241.7, 51241.7, 53137.5, 56929.2", \ + "56973.3, 56973.3, 56973.3, 56973.3, 56973.3", \ + "57061.4, 57061.4, 57061.4, 57061.4, 57061.4", \ + "57237.8, 57237.8, 57237.8, 57237.8, 57237.8", \ + "51908.2, 51908.2, 51908.2, 53804.0, 57595.7"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("52696.3, 52696.3, 52696.3, 54592.1, 58383.8", \ + "58406.7, 58406.7, 58406.7, 58406.7, 58406.7", \ + "58452.5, 58452.5, 58452.5, 58452.5, 58452.5", \ + "58544.6, 58544.6, 58544.6, 58544.6, 58544.6", \ + "53062.9, 53062.9, 53062.9, 54958.7, 58750.4"); + } + } + } + } + + cell (mx3_x4) { + area : 50.40 ; + cell_leakage_power : 8.8 ; + leakage_power () { + when : "(cmd0 & cmd1 & i0 & i1)" ; + value : 9.1 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0 & cmd1 & cmd0)" ; + value : 8.2 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i0) & i1)" ; + value : 9 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0) & cmd1 & cmd0)" ; + value : 8.4 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & cmd1 & cmd0)" ; + value : 7.6 ; + } + leakage_power () { + when : "(i2 & i1 & i0 & !(cmd1) & cmd0)" ; + value : 9.6 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0 & !(cmd1) & cmd0)" ; + value : 9.7 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0 & !(cmd1) & cmd0)" ; + value : 8.7 ; + } + leakage_power () { + when : "(cmd0 & ((cmd1 & i0 & !(i1) & i2) | (!(cmd1) & !(i0) & i1 & !(i2))))" ; + value : 8.9 ; + } + leakage_power () { + when : "(cmd0 & !(cmd1) & ((i0 & i1 & !(i2)) | (!(i0) & i2)))" ; + value : 9.5 ; + } + leakage_power () { + when : "(!(cmd0) & cmd1 & i0 & i2)" ; + value : 9.4 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i0) & !(i1) & !(i2)) | (!(cmd0) & cmd1 & !(i0) & (i1 ^ i2)))" ; + value : 8.1 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & cmd1 & !(cmd0))" ; + value : 7.5 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & i1)" ; + value : 9.9 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & !(i1))" ; + value : 9.8 ; + } + leakage_power () { + when : "(!(cmd0) & ((cmd1 & i0 & !(i2)) | (!(cmd1) & !(i0) & i1 & i2)))" ; + value : 9.2 ; + } + leakage_power () { + when : "(!(cmd0) & ((cmd1 & !(i0) & i1 & i2) | (!(cmd1) & !(i0) & (i1 ^ i2))))" ; + value : 8.6 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & !(cmd1) & !(cmd0))" ; + value : 8 ; + } + pin (i2) { + direction : input ; + capacitance : 454.27 ; + } + pin (i1) { + direction : input ; + capacitance : 454.85 ; + } + pin (i0) { + direction : input ; + capacitance : 463.11 ; + } + pin (cmd1) { + direction : input ; + capacitance : 774.18 ; + } + pin (cmd0) { + direction : input ; + capacitance : 744.49 ; + } + pin (q) { + function : "((i2 & ((i0 & (!(cmd0) | i1 | !(cmd1))) | (cmd0 & (i1 | !(cmd1))))) | (i0 & (!(cmd0) | (i1 & cmd1))) | (cmd0 & i1 & cmd1))" ; + direction : output ; + capacitance : 154.89 ; + timing (maxd_q_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("16219.1, 16219.1, 16219.1, 16462.1, 16938.8", \ + "16208.0, 16208.0, 16208.0, 16451.0, 16927.7", \ + "16185.8, 16185.8, 16185.8, 16428.8, 16905.5", \ + "16141.5, 16141.5, 16141.5, 16384.5, 16861.2", \ + "16052.9, 16052.9, 16052.9, 16295.9, 16772.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("9664.0, 9664.0, 9664.0, 9858.9, 10247.2", \ + "9664.0, 9664.0, 9664.0, 9858.9, 10247.2", \ + "9664.0, 9664.0, 9664.0, 9858.9, 10247.2", \ + "9664.0, 9664.0, 9664.0, 9858.9, 10247.2", \ + "9664.0, 9664.0, 9664.0, 9858.9, 10247.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("16807.0, 16807.0, 16807.0, 17028.2, 17463.3", \ + "16801.6, 16801.6, 16801.6, 17022.8, 17457.9", \ + "16790.9, 16790.9, 16790.9, 17012.1, 17447.2", \ + "16769.5, 16769.5, 16769.5, 16990.7, 17425.8", \ + "16726.7, 16726.7, 16726.7, 16947.9, 17383.0"); + } + fall_transition (inslew_load_5x5__21) { + values ("8579.1, 8579.1, 8579.1, 8754.9, 9084.4", \ + "8579.1, 8579.1, 8579.1, 8754.9, 9084.4", \ + "8579.1, 8579.1, 8579.1, 8754.9, 9084.4", \ + "8579.1, 8579.1, 8579.1, 8754.9, 9084.4", \ + "8579.1, 8579.1, 8579.1, 8754.9, 9084.4"); + } + } + timing (maxd_q_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("12111.8, 12111.8, 12111.8, 12356.6, 12826.9", \ + "12120.6, 12120.6, 12120.6, 12365.4, 12835.7", \ + "12141.4, 12141.4, 12141.4, 12386.3, 12856.7", \ + "12155.3, 12155.3, 12155.3, 12400.1, 12870.5", \ + "12173.4, 12173.4, 12173.4, 12418.2, 12888.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("6964.6, 6964.6, 6964.6, 7161.1, 7550.1", \ + "6974.4, 6974.4, 6974.4, 7170.9, 7559.8", \ + "6992.8, 6992.8, 6992.8, 7189.4, 7578.3", \ + "7002.5, 7002.5, 7002.5, 7199.0, 7587.9", \ + "7002.8, 7002.8, 7002.8, 7199.3, 7588.2"); + } + cell_fall (inslew_load_5x5__21) { + values ("15381.4, 15381.4, 15381.4, 15602.5, 16037.8", \ + "15400.0, 15400.0, 15400.0, 15621.0, 16056.4", \ + "15423.6, 15423.6, 15423.6, 15644.7, 16080.2", \ + "15435.0, 15435.0, 15435.0, 15656.0, 16091.7", \ + "15470.4, 15470.4, 15470.4, 15691.3, 16127.1"); + } + fall_transition (inslew_load_5x5__21) { + values ("8617.8, 8617.8, 8617.8, 8793.8, 9123.2", \ + "8634.4, 8634.4, 8634.4, 8810.3, 9139.7", \ + "8657.6, 8657.6, 8657.6, 8833.7, 9163.0", \ + "8677.0, 8677.0, 8677.0, 8853.1, 9182.3", \ + "8710.3, 8710.3, 8710.3, 8886.6, 9215.7"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("8829.2, 8829.2, 8829.2, 9088.9, 9581.2", \ + "8834.1, 8834.1, 8834.1, 9093.8, 9586.0", \ + "8840.8, 8840.8, 8840.8, 9100.5, 9592.7", \ + "8857.6, 8857.6, 8857.6, 9117.3, 9609.5", \ + "8891.2, 8891.2, 8891.2, 9150.9, 9643.1"); + } + rise_transition (inslew_load_5x5__21) { + values ("4449.7, 4449.7, 4449.7, 4654.4, 5057.2", \ + "4452.3, 4452.3, 4452.3, 4657.0, 5059.7", \ + "4452.7, 4452.7, 4452.7, 4657.4, 5060.1", \ + "4453.1, 4453.1, 4453.1, 4657.8, 5060.5", \ + "4453.1, 4453.1, 4453.1, 4657.8, 5060.5"); + } + cell_fall (inslew_load_5x5__21) { + values ("12021.0, 12021.0, 12021.0, 12325.6, 12892.5", \ + "12023.2, 12023.2, 12023.2, 12327.8, 12895.0", \ + "12031.3, 12031.3, 12031.3, 12335.9, 12903.8", \ + "12043.0, 12043.0, 12043.0, 12347.6, 12915.9", \ + "12071.0, 12071.0, 12071.0, 12375.7, 12944.0"); + } + fall_transition (inslew_load_5x5__21) { + values ("5985.1, 5985.1, 5985.1, 6148.0, 6411.4", \ + "5987.8, 5987.8, 5987.8, 6150.6, 6414.2", \ + "5993.2, 5993.2, 5993.2, 6156.1, 6420.0", \ + "5996.3, 5996.3, 5996.3, 6159.2, 6423.2", \ + "5996.7, 5996.7, 5996.7, 6159.7, 6423.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("14700.7, 14700.7, 14700.7, 14944.5, 15419.8", \ + "14697.0, 14697.0, 14697.0, 14940.8, 15416.1", \ + "14690.5, 14690.5, 14690.5, 14934.3, 15409.6", \ + "14673.1, 14673.1, 14673.1, 14916.9, 15392.2", \ + "14640.6, 14640.6, 14640.6, 14884.5, 15359.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("8684.2, 8684.2, 8684.2, 8881.1, 9268.5", \ + "8686.9, 8686.9, 8686.9, 8883.8, 9271.2", \ + "8690.6, 8690.6, 8690.6, 8887.5, 9275.0", \ + "8691.5, 8691.5, 8691.5, 8888.4, 9275.8", \ + "8691.6, 8691.6, 8691.6, 8888.4, 9275.9"); + } + cell_fall (inslew_load_5x5__21) { + values ("19659.3, 19659.3, 19659.3, 19508.9, 19947.0", \ + "19656.6, 19656.6, 19656.6, 19506.1, 19944.2", \ + "19644.4, 19644.4, 19644.4, 19493.7, 19931.9", \ + "19626.6, 19626.6, 19626.6, 19475.7, 19913.9", \ + "19587.9, 19587.9, 19587.9, 19436.9, 19875.1"); + } + fall_transition (inslew_load_5x5__21) { + values ("11181.2, 11181.2, 11181.2, 11114.4, 11448.0", \ + "11185.2, 11185.2, 11185.2, 11118.5, 11452.1", \ + "11188.4, 11188.4, 11188.4, 11121.6, 11455.1", \ + "11195.6, 11195.6, 11195.6, 11128.4, 11462.0", \ + "11199.6, 11199.6, 11199.6, 11132.3, 11465.9"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__21) { + values ("14700.7, 14700.7, 14700.7, 14944.5, 15419.8", \ + "14697.0, 14697.0, 14697.0, 14940.8, 15416.1", \ + "14690.5, 14690.5, 14690.5, 14934.3, 15409.6", \ + "14673.1, 14673.1, 14673.1, 14916.9, 15392.2", \ + "14640.6, 14640.6, 14640.6, 14884.5, 15359.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("8684.2, 8684.2, 8684.2, 8881.1, 9268.5", \ + "8686.9, 8686.9, 8686.9, 8883.8, 9271.2", \ + "8690.6, 8690.6, 8690.6, 8887.5, 9275.0", \ + "8691.5, 8691.5, 8691.5, 8888.4, 9275.8", \ + "8691.6, 8691.6, 8691.6, 8888.4, 9275.9"); + } + cell_fall (inslew_load_5x5__21) { + values ("19659.3, 19659.3, 19659.3, 19508.9, 19947.0", \ + "19656.6, 19656.6, 19656.6, 19506.1, 19944.2", \ + "19644.4, 19644.4, 19644.4, 19493.7, 19931.9", \ + "19626.6, 19626.6, 19626.6, 19475.7, 19913.9", \ + "19587.9, 19587.9, 19587.9, 19436.9, 19875.1"); + } + fall_transition (inslew_load_5x5__21) { + values ("11181.2, 11181.2, 11181.2, 11114.4, 11448.0", \ + "11185.2, 11185.2, 11185.2, 11118.5, 11452.1", \ + "11188.4, 11188.4, 11188.4, 11121.6, 11455.1", \ + "11195.6, 11195.6, 11195.6, 11128.4, 11462.0", \ + "11199.6, 11199.6, 11199.6, 11132.3, 11465.9"); + } + } + timing (maxd_q_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("16285.6, 16285.6, 16285.6, 16530.5, 17001.0", \ + "16294.4, 16294.4, 16294.4, 16539.3, 17009.8", \ + "16312.0, 16312.0, 16312.0, 16556.9, 17027.4", \ + "16347.2, 16347.2, 16347.2, 16592.1, 17062.6", \ + "16417.8, 16417.8, 16417.8, 16662.6, 17133.1"); + } + rise_transition (inslew_load_5x5__21) { + values ("7028.9, 7028.9, 7028.9, 7225.5, 7614.3", \ + "7028.9, 7028.9, 7028.9, 7225.5, 7614.3", \ + "7028.9, 7028.9, 7028.9, 7225.5, 7614.3", \ + "7028.9, 7028.9, 7028.9, 7225.5, 7614.3", \ + "7029.3, 7029.3, 7029.3, 7225.8, 7614.7"); + } + cell_fall (inslew_load_5x5__21) { + values ("24938.8, 24938.8, 24938.8, 25151.3, 25561.1", \ + "24947.6, 24947.6, 24947.6, 25160.1, 25569.9", \ + "24965.2, 24965.2, 24965.2, 25177.7, 25587.5", \ + "25000.4, 25000.4, 25000.4, 25212.9, 25622.7", \ + "25067.2, 25067.2, 25067.2, 25279.7, 25689.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("13016.1, 13016.1, 13016.1, 13164.7, 13465.3", \ + "13016.1, 13016.1, 13016.1, 13164.7, 13465.3", \ + "13016.1, 13016.1, 13016.1, 13164.7, 13465.3", \ + "13016.1, 13016.1, 13016.1, 13164.7, 13465.3", \ + "13016.1, 13016.1, 13016.1, 13164.7, 13465.3"); + } + } + timing (maxd_q_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("16467.0, 16467.0, 16467.0, 16711.8, 17182.8", \ + "16475.8, 16475.8, 16475.8, 16720.6, 17191.6", \ + "16493.4, 16493.4, 16493.4, 16738.2, 17209.2", \ + "16528.5, 16528.5, 16528.5, 16773.3, 17244.3", \ + "16599.0, 16599.0, 16599.0, 16843.8, 17314.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("7136.8, 7136.8, 7136.8, 7333.5, 7722.7", \ + "7136.8, 7136.8, 7136.8, 7333.5, 7722.7", \ + "7136.8, 7136.8, 7136.8, 7333.5, 7722.7", \ + "7136.8, 7136.8, 7136.8, 7333.5, 7722.7", \ + "7136.9, 7136.9, 7136.9, 7333.7, 7722.8"); + } + cell_fall (inslew_load_5x5__21) { + values ("17581.8, 17581.8, 17581.8, 17802.8, 18238.6", \ + "17590.6, 17590.6, 17590.6, 17811.6, 18247.4", \ + "17608.2, 17608.2, 17608.2, 17829.2, 18265.0", \ + "17643.3, 17643.3, 17643.3, 17864.3, 18300.1", \ + "17709.3, 17709.3, 17709.3, 17930.3, 18366.1"); + } + fall_transition (inslew_load_5x5__21) { + values ("8712.7, 8712.7, 8712.7, 8888.9, 9218.0", \ + "8712.7, 8712.7, 8712.7, 8888.9, 9218.0", \ + "8712.7, 8712.7, 8712.7, 8888.9, 9218.0", \ + "8712.7, 8712.7, 8712.7, 8888.9, 9218.0", \ + "8712.7, 8712.7, 8712.7, 8889.0, 9218.1"); + } + } + internal_power (energy_pos_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__21) { + values ("94034.7, 94034.7, 94034.7, 95970.8, 99842.9", \ + "99864.3, 99864.3, 99864.3, 99864.3, 99864.3", \ + "99906.9, 99906.9, 99906.9, 99906.9, 99906.9", \ + "99992.1, 99992.1, 99992.1, 99992.1, 99992.1", \ + "100162.6, 100162.6, 100162.6, 100162.6, 100162.6"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("88683.9, 88683.9, 88683.9, 90620.0, 94492.1", \ + "94544.4, 94544.4, 94544.4, 94544.4, 94544.4", \ + "94649.1, 94649.1, 94649.1, 94649.1, 94649.1", \ + "94858.3, 94858.3, 94858.3, 94858.3, 94858.3", \ + "95276.7, 95276.7, 95276.7, 95276.7, 95276.7"); + } + } + internal_power (energy_pos_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__21) { + values ("68436.0, 68436.0, 68436.0, 70372.1, 74244.3", \ + "68506.4, 68506.4, 68506.4, 70442.5, 74314.7", \ + "68641.5, 68641.5, 68641.5, 70577.6, 74449.7", \ + "68747.5, 68747.5, 68747.5, 70683.6, 74555.8", \ + "68845.5, 68845.5, 68845.5, 70781.6, 74653.7"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("76902.9, 76902.9, 76902.9, 78839.0, 82711.2", \ + "77035.5, 77035.5, 77035.5, 78971.6, 82843.8", \ + "77239.9, 77239.9, 77239.9, 79175.9, 83048.1", \ + "77477.9, 77477.9, 77477.9, 79414.0, 83286.2", \ + "77921.2, 77921.2, 77921.2, 79857.3, 83729.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__21) { + values ("53876.2, 53876.2, 53876.2, 55812.3, 59684.5", \ + "53905.7, 53905.7, 53905.7, 55841.8, 59713.9", \ + "53938.4, 53938.4, 53938.4, 55874.5, 59746.7", \ + "54002.1, 54002.1, 54002.1, 55938.2, 59810.4", \ + "59932.8, 59932.8, 59932.8, 59932.8, 59932.8"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("60478.6, 60478.6, 60478.6, 62414.7, 66286.9", \ + "60532.6, 60532.6, 60532.6, 62468.7, 66340.8", \ + "60641.5, 60641.5, 60641.5, 62577.6, 66449.8", \ + "60811.2, 60811.2, 60811.2, 62747.3, 66619.5", \ + "61115.2, 61115.2, 61115.2, 63051.3, 66923.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("84514.6, 84514.6, 84514.6, 86450.7, 90322.8", \ + "84546.5, 84546.5, 84546.5, 86482.6, 90354.8", \ + "84600.1, 84600.1, 84600.1, 86536.2, 90408.4", \ + "84666.6, 84666.6, 84666.6, 86602.7, 90474.9", \ + "84789.5, 84789.5, 84789.5, 86725.6, 90597.7"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("98681.3, 98681.3, 98681.3, 100617.4, 104489.6", \ + "98744.8, 98744.8, 98744.8, 100680.9, 104553.0", \ + "98839.1, 98839.1, 98839.1, 100775.2, 104647.4", \ + "99032.6, 99032.6, 99032.6, 100968.7, 104840.8", \ + "99358.2, 99358.2, 99358.2, 101294.3, 105166.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("84514.6, 84514.6, 84514.6, 86450.7, 90322.8", \ + "84546.5, 84546.5, 84546.5, 86482.6, 90354.8", \ + "84600.1, 84600.1, 84600.1, 86536.2, 90408.4", \ + "84666.6, 84666.6, 84666.6, 86602.7, 90474.9", \ + "84789.5, 84789.5, 84789.5, 86725.6, 90597.7"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("98681.3, 98681.3, 98681.3, 100617.4, 104489.6", \ + "98744.8, 98744.8, 98744.8, 100680.9, 104553.0", \ + "98839.1, 98839.1, 98839.1, 100775.2, 104647.4", \ + "99032.6, 99032.6, 99032.6, 100968.7, 104840.8", \ + "99358.2, 99358.2, 99358.2, 101294.3, 105166.4"); + } + } + internal_power (energy_neg_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__21) { + values ("87097.8, 87097.8, 87097.8, 89033.9, 92906.0", \ + "92932.6, 92932.6, 92932.6, 92932.6, 92932.6", \ + "92985.6, 92985.6, 92985.6, 92985.6, 92985.6", \ + "93091.6, 93091.6, 93091.6, 93091.6, 93091.6", \ + "87498.4, 87498.4, 87498.4, 89434.5, 93306.7"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("124424.9, 124424.9, 124424.9, 126361.0, 130233.2", \ + "130250.0, 130250.0, 130250.0, 130250.0, 130250.0", \ + "130283.6, 130283.6, 130283.6, 130283.6, 130283.6", \ + "130350.8, 130350.8, 130350.8, 130350.8, 130350.8", \ + "130494.1, 130494.1, 130494.1, 130494.1, 130494.1"); + } + } + internal_power (energy_neg_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__21) { + values ("76743.3, 76743.3, 76743.3, 78679.4, 82551.5", \ + "82586.4, 82586.4, 82586.4, 82586.4, 82586.4", \ + "82656.1, 82656.1, 82656.1, 82656.1, 82656.1", \ + "82795.4, 82795.4, 82795.4, 82795.4, 82795.4", \ + "77267.1, 77267.1, 77267.1, 79203.1, 83075.3"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("84504.4, 84504.4, 84504.4, 86440.5, 90312.7", \ + "90328.0, 90328.0, 90328.0, 90328.0, 90328.0", \ + "90358.7, 90358.7, 90358.7, 90358.7, 90358.7", \ + "90420.2, 90420.2, 90420.2, 90420.2, 90420.2", \ + "84746.8, 84746.8, 84746.8, 86682.9, 90555.1"); + } + } + } + } + + cell (no3_x4) { + area : 28.80 ; + cell_leakage_power : 7.7 ; + leakage_power () { + when : "((i0 & (!(i1) | !(i2))) | (i1 & !(i2)))" ; + value : 6.1 ; + } + leakage_power () { + when : "(!((i0 & !(i1))) & i2)" ; + value : 6.4 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 11 ; + } + pin (i2) { + direction : input ; + capacitance : 711.35 ; + } + pin (i1) { + direction : input ; + capacitance : 712.25 ; + } + pin (i0) { + direction : input ; + capacitance : 712.25 ; + } + pin (nq) { + function : "(!(i0) & !(i1) & !(i2))" ; + direction : output ; + capacitance : 148.45 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("19812.4, 19812.4, 19812.4, 20046.9, 20500.6", \ + "19801.0, 19801.0, 19801.0, 20035.5, 20489.2", \ + "19778.2, 19778.2, 19778.2, 20012.7, 20466.4", \ + "19732.7, 19732.7, 19732.7, 19967.2, 20420.9", \ + "19641.7, 19641.7, 19641.7, 19876.2, 20329.9"); + } + rise_transition (inslew_load_5x5__13) { + values ("5456.8, 5456.8, 5456.8, 5648.2, 6030.6", \ + "5456.8, 5456.8, 5456.8, 5648.2, 6030.6", \ + "5456.8, 5456.8, 5456.8, 5648.2, 6030.6", \ + "5456.8, 5456.8, 5456.8, 5648.2, 6030.6", \ + "5456.8, 5456.8, 5456.8, 5648.2, 6030.6"); + } + cell_fall (inslew_load_5x5__13) { + values ("12940.8, 12940.8, 12940.8, 13147.5, 13551.6", \ + "12949.6, 12949.6, 12949.6, 13156.3, 13560.4", \ + "12967.2, 12967.2, 12967.2, 13173.9, 13578.0", \ + "13002.4, 13002.4, 13002.4, 13209.1, 13613.2", \ + "13073.0, 13073.0, 13073.0, 13279.7, 13683.9"); + } + fall_transition (inslew_load_5x5__13) { + values ("3117.7, 3117.7, 3117.7, 3270.1, 3587.0", \ + "3117.7, 3117.7, 3117.7, 3270.1, 3587.0", \ + "3117.7, 3117.7, 3117.7, 3270.1, 3587.0", \ + "3117.7, 3117.7, 3117.7, 3270.1, 3587.0", \ + "3117.9, 3117.9, 3117.9, 3270.2, 3587.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("15627.7, 15627.7, 15627.7, 15878.7, 16354.7", \ + "15622.3, 15622.3, 15622.3, 15873.3, 16349.4", \ + "15616.0, 15616.0, 15616.0, 15867.0, 16343.0", \ + "15598.3, 15598.3, 15598.3, 15849.3, 16325.3", \ + "15561.4, 15561.4, 15561.4, 15812.4, 16288.4"); + } + rise_transition (inslew_load_5x5__13) { + values ("4197.9, 4197.9, 4197.9, 4396.5, 4786.4", \ + "4199.0, 4199.0, 4199.0, 4397.6, 4787.6", \ + "4201.8, 4201.8, 4201.8, 4400.3, 4790.2", \ + "4203.7, 4203.7, 4203.7, 4402.3, 4792.1", \ + "4203.9, 4203.9, 4203.9, 4402.4, 4792.3"); + } + cell_fall (inslew_load_5x5__13) { + values ("11934.1, 11934.1, 11934.1, 12140.9, 12559.3", \ + "11942.9, 11942.9, 11942.9, 12149.7, 12568.1", \ + "11960.5, 11960.5, 11960.5, 12167.3, 12585.7", \ + "11995.7, 11995.7, 11995.7, 12202.5, 12620.9", \ + "12066.1, 12066.1, 12066.1, 12272.9, 12691.3"); + } + fall_transition (inslew_load_5x5__13) { + values ("2977.1, 2977.1, 2977.1, 3135.3, 3453.1", \ + "2977.1, 2977.1, 2977.1, 3135.3, 3453.1", \ + "2977.1, 2977.1, 2977.1, 3135.3, 3453.1", \ + "2977.1, 2977.1, 2977.1, 3135.3, 3453.1", \ + "2977.1, 2977.1, 2977.1, 3135.4, 3453.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("10865.3, 10865.3, 10865.3, 11127.5, 11625.7", \ + "10904.8, 10904.8, 10904.8, 11166.9, 11664.3", \ + "10927.5, 10927.5, 10927.5, 11189.5, 11686.2", \ + "10992.9, 10992.9, 10992.9, 11254.7, 11749.9", \ + "11037.9, 11037.9, 11037.9, 11299.6, 11794.1"); + } + rise_transition (inslew_load_5x5__13) { + values ("2716.7, 2716.7, 2716.7, 2937.7, 3360.6", \ + "2731.5, 2731.5, 2731.5, 2952.3, 3374.6", \ + "2742.7, 2742.7, 2742.7, 2963.2, 3385.1", \ + "2768.8, 2768.8, 2768.8, 2988.7, 3409.8", \ + "2787.1, 2787.1, 2787.1, 3006.7, 3427.2"); + } + cell_fall (inslew_load_5x5__13) { + values ("10540.7, 10540.7, 10540.7, 10747.6, 11178.5", \ + "10549.5, 10549.5, 10549.5, 10756.4, 11187.3", \ + "10567.1, 10567.1, 10567.1, 10774.0, 11204.9", \ + "10602.3, 10602.3, 10602.3, 10809.2, 11240.1", \ + "10671.6, 10671.6, 10671.6, 10878.5, 11309.3"); + } + fall_transition (inslew_load_5x5__13) { + values ("2928.1, 2928.1, 2928.1, 3088.6, 3405.9", \ + "2928.1, 2928.1, 2928.1, 3088.6, 3405.9", \ + "2928.1, 2928.1, 2928.1, 3088.6, 3405.9", \ + "2928.1, 2928.1, 2928.1, 3088.6, 3405.9", \ + "2928.2, 2928.2, 2928.2, 3088.7, 3406.0"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__13) { + values ("94478.0, 94478.0, 94478.0, 96333.6, 100044.8", \ + "100084.7, 100084.7, 100084.7, 100084.7, 100084.7", \ + "100164.5, 100164.5, 100164.5, 100164.5, 100164.5", \ + "100324.1, 100324.1, 100324.1, 100324.1, 100324.1", \ + "100643.2, 100643.2, 100643.2, 100643.2, 100643.2"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("62610.1, 62610.1, 62610.1, 64465.7, 68176.9", \ + "68231.7, 68231.7, 68231.7, 68231.7, 68231.7", \ + "68341.2, 68341.2, 68341.2, 68341.2, 68341.2", \ + "68560.4, 68560.4, 68560.4, 68560.4, 68560.4", \ + "63433.8, 63433.8, 63433.8, 65289.3, 69000.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__13) { + values ("73425.8, 73425.8, 73425.8, 75281.3, 78992.5", \ + "73477.8, 73477.8, 73477.8, 75333.4, 79044.6", \ + "73585.9, 73585.9, 73585.9, 75441.5, 79152.6", \ + "73775.5, 73775.5, 73775.5, 75631.0, 79342.2", \ + "74126.8, 74126.8, 74126.8, 75982.4, 79693.6"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("57329.0, 57329.0, 57329.0, 59184.6, 62895.8", \ + "62932.0, 62932.0, 62932.0, 62932.0, 62932.0", \ + "63004.5, 63004.5, 63004.5, 63004.5, 63004.5", \ + "63149.5, 63149.5, 63149.5, 63149.5, 63149.5", \ + "57874.9, 57874.9, 57874.9, 59730.5, 63441.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__13) { + values ("52640.7, 52640.7, 52640.7, 54496.3, 58207.5", \ + "52778.4, 52778.4, 52778.4, 54634.0, 58345.2", \ + "52937.3, 52937.3, 52937.3, 54792.9, 58504.1", \ + "53279.8, 53279.8, 53279.8, 55135.4, 58846.6", \ + "53750.6, 53750.6, 53750.6, 55606.2, 59317.4"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("49607.4, 49607.4, 49607.4, 51463.0, 55174.1", \ + "55200.6, 55200.6, 55200.6, 55200.6, 55200.6", \ + "55253.6, 55253.6, 55253.6, 55253.6, 55253.6", \ + "55359.6, 55359.6, 55359.6, 55359.6, 55359.6", \ + "50011.8, 50011.8, 50011.8, 51867.4, 55578.5"); + } + } + } + } + + cell (ao2o22_x4) { + area : 36.00 ; + cell_leakage_power : 7.4 ; + leakage_power () { + when : "(!(i3) & !(i2) & i1 & i0)" ; + value : 8.1 ; + } + leakage_power () { + when : "(i3 & !(i2) & !(i1) & i0)" ; + value : 7 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 7.2 ; + } + leakage_power () { + when : "((i0 & (i1 ^ (i2 | !(i3)))) | (!(i0) & i1 & !(i2)))" ; + value : 7.1 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 8.8 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3))" ; + value : 7.5 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 6.1 ; + } + pin (i3) { + direction : input ; + capacitance : 432.96 ; + } + pin (i2) { + direction : input ; + capacitance : 434.46 ; + } + pin (i1) { + direction : input ; + capacitance : 434.46 ; + } + pin (i0) { + direction : input ; + capacitance : 432.96 ; + } + pin (q) { + function : "((i0 | i1) & (i3 | i2))" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("11442.3, 11442.3, 11442.3, 11682.4, 12141.3", \ + "11452.8, 11452.8, 11452.8, 11693.0, 12151.9", \ + "11464.0, 11464.0, 11464.0, 11704.2, 12163.1", \ + "11478.0, 11478.0, 11478.0, 11718.2, 12177.1", \ + "11509.6, 11509.6, 11509.6, 11749.8, 12208.7"); + } + rise_transition (inslew_load_5x5__3) { + values ("6082.0, 6082.0, 6082.0, 6276.2, 6661.2", \ + "6089.7, 6089.7, 6089.7, 6284.0, 6668.8", \ + "6096.2, 6096.2, 6096.2, 6290.4, 6675.2", \ + "6098.2, 6098.2, 6098.2, 6292.5, 6677.2", \ + "6098.6, 6098.6, 6098.6, 6292.8, 6677.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("13928.8, 13928.8, 13928.8, 14144.2, 14701.5", \ + "13923.5, 13923.5, 13923.5, 14138.9, 14696.2", \ + "13912.7, 13912.7, 13912.7, 14128.1, 14685.4", \ + "13891.3, 13891.3, 13891.3, 14106.7, 14664.0", \ + "13848.5, 13848.5, 13848.5, 14063.9, 14621.2"); + } + fall_transition (inslew_load_5x5__3) { + values ("7098.6, 7098.6, 7098.6, 7265.1, 7559.1", \ + "7098.6, 7098.6, 7098.6, 7265.1, 7559.1", \ + "7098.6, 7098.6, 7098.6, 7265.1, 7559.1", \ + "7098.6, 7098.6, 7098.6, 7265.1, 7559.1", \ + "7098.6, 7098.6, 7098.6, 7265.1, 7559.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("10298.0, 10298.0, 10298.0, 10537.6, 11004.9", \ + "10308.9, 10308.9, 10308.9, 10548.5, 11015.5", \ + "10320.2, 10320.2, 10320.2, 10559.8, 11026.6", \ + "10334.0, 10334.0, 10334.0, 10573.6, 11040.4", \ + "10366.0, 10366.0, 10366.0, 10605.6, 11072.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("5338.6, 5338.6, 5338.6, 5535.1, 5925.5", \ + "5346.5, 5346.5, 5346.5, 5542.9, 5933.3", \ + "5353.1, 5353.1, 5353.1, 5549.5, 5939.9", \ + "5355.1, 5355.1, 5355.1, 5551.5, 5941.9", \ + "5355.6, 5355.6, 5355.6, 5552.0, 5942.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("11659.9, 11659.9, 11659.9, 11959.8, 12504.4", \ + "11662.1, 11662.1, 11662.1, 11962.0, 12506.9", \ + "11670.2, 11670.2, 11670.2, 11970.1, 12515.7", \ + "11682.0, 11682.0, 11682.0, 11981.9, 12527.9", \ + "11709.9, 11709.9, 11709.9, 12009.8, 12555.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("5864.9, 5864.9, 5864.9, 6022.2, 6270.6", \ + "5867.6, 5867.6, 5867.6, 6024.8, 6273.4", \ + "5873.1, 5873.1, 5873.1, 6030.4, 6279.3", \ + "5876.2, 5876.2, 5876.2, 6033.6, 6282.5", \ + "5876.6, 5876.6, 5876.6, 6033.9, 6283.0"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("11599.3, 11599.3, 11599.3, 11839.6, 12298.5", \ + "11594.2, 11594.2, 11594.2, 11834.5, 12293.4", \ + "11583.9, 11583.9, 11583.9, 11824.2, 12283.1", \ + "11563.2, 11563.2, 11563.2, 11803.5, 12262.4", \ + "11522.0, 11522.0, 11522.0, 11762.3, 12221.2"); + } + rise_transition (inslew_load_5x5__3) { + values ("6134.9, 6134.9, 6134.9, 6329.1, 6713.5", \ + "6134.9, 6134.9, 6134.9, 6329.1, 6713.5", \ + "6134.9, 6134.9, 6134.9, 6329.1, 6713.5", \ + "6134.9, 6134.9, 6134.9, 6329.1, 6713.5", \ + "6134.9, 6134.9, 6134.9, 6329.1, 6713.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("12676.2, 12676.2, 12676.2, 12980.1, 13601.5", \ + "12678.3, 12678.3, 12678.3, 12982.2, 13603.9", \ + "12686.4, 12686.4, 12686.4, 12990.3, 13612.7", \ + "12698.2, 12698.2, 12698.2, 13002.2, 13624.9", \ + "12726.1, 12726.1, 12726.1, 13030.1, 13652.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("6488.0, 6488.0, 6488.0, 6652.8, 6939.5", \ + "6490.6, 6490.6, 6490.6, 6655.4, 6942.3", \ + "6496.1, 6496.1, 6496.1, 6661.0, 6948.3", \ + "6499.2, 6499.2, 6499.2, 6664.1, 6951.6", \ + "6499.5, 6499.5, 6499.5, 6664.4, 6952.0"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("12714.1, 12714.1, 12714.1, 12954.2, 13414.9", \ + "12709.0, 12709.0, 12709.0, 12949.1, 13409.8", \ + "12698.7, 12698.7, 12698.7, 12938.8, 13399.5", \ + "12678.1, 12678.1, 12678.1, 12918.2, 13378.9", \ + "12636.8, 12636.8, 12636.8, 12876.9, 13337.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("6851.6, 6851.6, 6851.6, 7043.7, 7425.1", \ + "6851.6, 6851.6, 6851.6, 7043.7, 7425.1", \ + "6851.6, 6851.6, 6851.6, 7043.7, 7425.1", \ + "6851.6, 6851.6, 6851.6, 7043.7, 7425.1", \ + "6851.6, 6851.6, 6851.6, 7043.7, 7425.1"); + } + cell_fall (inslew_load_5x5__3) { + values ("15033.9, 15033.9, 15033.9, 15251.1, 15738.2", \ + "15028.6, 15028.6, 15028.6, 15245.8, 15732.9", \ + "15017.9, 15017.9, 15017.9, 15235.1, 15722.2", \ + "14996.5, 14996.5, 14996.5, 15213.7, 15700.8", \ + "14953.6, 14953.6, 14953.6, 15170.8, 15657.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("7704.3, 7704.3, 7704.3, 7873.4, 8192.6", \ + "7704.3, 7704.3, 7704.3, 7873.4, 8192.6", \ + "7704.3, 7704.3, 7704.3, 7873.4, 8192.6", \ + "7704.3, 7704.3, 7704.3, 7873.4, 8192.6", \ + "7704.3, 7704.3, 7704.3, 7873.4, 8192.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("65156.5, 65156.5, 65156.5, 67052.3, 70844.0", \ + "65226.9, 65226.9, 65226.9, 67122.8, 70914.4", \ + "65315.1, 65315.1, 65315.1, 67211.0, 71002.6", \ + "65427.8, 65427.8, 65427.8, 67323.7, 71115.4", \ + "65631.4, 65631.4, 65631.4, 67527.2, 71318.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("72291.4, 72291.4, 72291.4, 74187.2, 77978.9", \ + "78010.4, 78010.4, 78010.4, 78010.4, 78010.4", \ + "78073.5, 78073.5, 78073.5, 78073.5, 78073.5", \ + "78199.8, 78199.8, 78199.8, 78199.8, 78199.8", \ + "78452.3, 78452.3, 78452.3, 78452.3, 78452.3"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("58166.3, 58166.3, 58166.3, 60062.1, 63853.8", \ + "58222.3, 58222.3, 58222.3, 60118.1, 63909.8", \ + "58282.4, 58282.4, 58282.4, 60178.2, 63969.9", \ + "58338.5, 58338.5, 58338.5, 60234.3, 64026.0", \ + "58430.2, 58430.2, 58430.2, 60326.1, 64117.8"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("58847.1, 58847.1, 58847.1, 60742.9, 64534.6", \ + "58904.3, 58904.3, 58904.3, 60800.1, 64591.8", \ + "59020.1, 59020.1, 59020.1, 60915.9, 64707.6", \ + "59202.9, 59202.9, 59202.9, 61098.8, 64890.4", \ + "59533.0, 59533.0, 59533.0, 61428.8, 65220.5"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("66004.2, 66004.2, 66004.2, 67900.1, 71691.7", \ + "71706.1, 71706.1, 71706.1, 71706.1, 71706.1", \ + "71734.8, 71734.8, 71734.8, 71734.8, 71734.8", \ + "71792.3, 71792.3, 71792.3, 71792.3, 71792.3", \ + "71907.1, 71907.1, 71907.1, 71907.1, 71907.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("65393.7, 65393.7, 65393.7, 67289.6, 71081.3", \ + "65452.5, 65452.5, 65452.5, 67348.3, 71140.0", \ + "65571.8, 65571.8, 65571.8, 67467.6, 71259.3", \ + "65761.5, 65761.5, 65761.5, 67657.3, 71449.0", \ + "66104.7, 66104.7, 66104.7, 68000.6, 71792.3"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__3) { + values ("72915.0, 72915.0, 72915.0, 74810.8, 78602.5", \ + "78625.4, 78625.4, 78625.4, 78625.4, 78625.4", \ + "78671.2, 78671.2, 78671.2, 78671.2, 78671.2", \ + "78762.8, 78762.8, 78762.8, 78762.8, 78762.8", \ + "78946.0, 78946.0, 78946.0, 78946.0, 78946.0"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("78777.2, 78777.2, 78777.2, 80673.1, 84464.7", \ + "84508.8, 84508.8, 84508.8, 84508.8, 84508.8", \ + "84597.0, 84597.0, 84597.0, 84597.0, 84597.0", \ + "84773.3, 84773.3, 84773.3, 84773.3, 84773.3", \ + "85126.0, 85126.0, 85126.0, 85126.0, 85126.0"); + } + } + } + } + + cell (oa2ao222_x2) { + area : 36.00 ; + cell_leakage_power : 7.1 ; + leakage_power () { + when : "(i4 & i3 & i2 & i1 & i0)" ; + value : 7.6 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & (i3 ^ i4)) | (!(i2) & i3 & i4)))" ; + value : 7.3 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & i1 & i0)" ; + value : 7.2 ; + } + leakage_power () { + when : "(i0 & i1 & !((i2 & i3)) & !(i4))" ; + value : 6.9 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & !(i1) & i0)" ; + value : 7.4 ; + } + leakage_power () { + when : "(i4 & !(i3) & !(i2) & !(i1) & i0)" ; + value : 7 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3 & i4)" ; + value : 8.5 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & i1 & !(i0))" ; + value : 7.1 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & i4)" ; + value : 8.4 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2) & i3 & i4)" ; + value : 8.1 ; + } + leakage_power () { + when : "(!(i0) & i1 & (i2 ^ i3) & !(i4))" ; + value : 6.3 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & !(i4)) | (!(i0) & i1 & !(i2) & !(i3) & i4))" ; + value : 6.6 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & i1 & !(i0))" ; + value : 5.5 ; + } + leakage_power () { + when : "(!(i4) & i3 & i2 & !(i1) & !(i0))" ; + value : 6.2 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & i2 & i4)" ; + value : 9.5 ; + } + leakage_power () { + when : "(i4 & i3 & !(i2) & !(i1) & !(i0))" ; + value : 9 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & (i2 ^ i3) & !(i4))" ; + value : 5.4 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4)) | (!(i0) & !(i1) & !(i2) & !(i3) & i4))" ; + value : 5.8 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 4.6 ; + } + pin (i4) { + direction : input ; + capacitance : 736.44 ; + } + pin (i3) { + direction : input ; + capacitance : 734.34 ; + } + pin (i2) { + direction : input ; + capacitance : 734.94 ; + } + pin (i1) { + direction : input ; + capacitance : 664.65 ; + } + pin (i0) { + direction : input ; + capacitance : 666.60 ; + } + pin (q) { + function : "((i4 & ((i0 & i1) | i3 | i2)) | (i0 & i1))" ; + direction : output ; + capacitance : 86.33 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__22) { + values ("7866.3, 7866.3, 7866.3, 8156.9, 8698.3", \ + "7861.1, 7861.1, 7861.1, 8151.7, 8693.1", \ + "7850.8, 7850.8, 7850.8, 8141.4, 8682.8", \ + "7830.1, 7830.1, 7830.1, 8120.7, 8662.1", \ + "7789.0, 7789.0, 7789.0, 8079.5, 8620.9"); + } + rise_transition (inslew_load_5x5__22) { + values ("3747.9, 3747.9, 3747.9, 3984.6, 4440.3", \ + "3747.9, 3747.9, 3747.9, 3984.6, 4440.3", \ + "3747.9, 3747.9, 3747.9, 3984.6, 4440.3", \ + "3747.9, 3747.9, 3747.9, 3984.6, 4440.3", \ + "3748.1, 3748.1, 3748.1, 3984.7, 4440.5"); + } + cell_fall (inslew_load_5x5__22) { + values ("13620.8, 13620.8, 13620.8, 13868.4, 14576.7", \ + "13613.7, 13613.7, 13613.7, 13861.3, 14569.6", \ + "13599.5, 13599.5, 13599.5, 13847.1, 14555.4", \ + "13571.1, 13571.1, 13571.1, 13818.7, 14527.0", \ + "13514.4, 13514.4, 13514.4, 13762.0, 14470.3"); + } + fall_transition (inslew_load_5x5__22) { + values ("7528.0, 7528.0, 7528.0, 7716.7, 8115.9", \ + "7528.0, 7528.0, 7528.0, 7716.7, 8115.9", \ + "7528.0, 7528.0, 7528.0, 7716.7, 8115.9", \ + "7528.0, 7528.0, 7528.0, 7716.7, 8115.9", \ + "7528.0, 7528.0, 7528.0, 7716.7, 8115.9"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__22) { + values ("6635.8, 6635.8, 6635.8, 6933.0, 7488.6", \ + "6640.9, 6640.9, 6640.9, 6938.1, 7493.6", \ + "6648.0, 6648.0, 6648.0, 6945.2, 7500.6", \ + "6664.7, 6664.7, 6664.7, 6961.9, 7517.3", \ + "6698.4, 6698.4, 6698.4, 6995.6, 7551.0"); + } + rise_transition (inslew_load_5x5__22) { + values ("2936.0, 2936.0, 2936.0, 3184.0, 3659.3", \ + "2938.7, 2938.7, 2938.7, 3186.7, 3661.9", \ + "2939.2, 2939.2, 2939.2, 3187.2, 3662.5", \ + "2939.6, 2939.6, 2939.6, 3187.6, 3662.8", \ + "2939.8, 2939.8, 2939.8, 3187.8, 3663.0"); + } + cell_fall (inslew_load_5x5__22) { + values ("12788.3, 12788.3, 12788.3, 13045.5, 13760.2", \ + "12781.2, 12781.2, 12781.2, 13038.4, 13753.1", \ + "12767.0, 12767.0, 12767.0, 13024.2, 13738.9", \ + "12738.7, 12738.7, 12738.7, 12995.9, 13710.6", \ + "12682.0, 12682.0, 12682.0, 12939.2, 13653.9"); + } + fall_transition (inslew_load_5x5__22) { + values ("7017.6, 7017.6, 7017.6, 7206.2, 7565.0", \ + "7017.6, 7017.6, 7017.6, 7206.2, 7565.0", \ + "7017.6, 7017.6, 7017.6, 7206.2, 7565.0", \ + "7017.6, 7017.6, 7017.6, 7206.2, 7565.0", \ + "7017.6, 7017.6, 7017.6, 7206.2, 7565.0"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__22) { + values ("7428.4, 7428.4, 7428.4, 7724.9, 8277.1", \ + "7423.2, 7423.2, 7423.2, 7719.7, 8271.9", \ + "7412.9, 7412.9, 7412.9, 7709.4, 8261.6", \ + "7392.3, 7392.3, 7392.3, 7688.8, 8241.0", \ + "7351.1, 7351.1, 7351.1, 7647.6, 8199.7"); + } + rise_transition (inslew_load_5x5__22) { + values ("3012.5, 3012.5, 3012.5, 3259.1, 3732.5", \ + "3012.5, 3012.5, 3012.5, 3259.1, 3732.5", \ + "3012.5, 3012.5, 3012.5, 3259.1, 3732.5", \ + "3012.5, 3012.5, 3012.5, 3259.1, 3732.5", \ + "3012.6, 3012.6, 3012.6, 3259.2, 3732.7"); + } + cell_fall (inslew_load_5x5__22) { + values ("6891.4, 6891.4, 6891.4, 7053.1, 7526.3", \ + "6871.9, 6871.9, 6871.9, 7033.6, 7508.2", \ + "6904.9, 6904.9, 6904.9, 7066.5, 7534.4", \ + "6915.6, 6915.6, 6915.6, 7077.3, 7540.0", \ + "6956.8, 6956.8, 6956.8, 7118.4, 7581.5"); + } + fall_transition (inslew_load_5x5__22) { + values ("3132.8, 3132.8, 3132.8, 3225.0, 3579.4", \ + "3126.2, 3126.2, 3126.2, 3218.8, 3573.1", \ + "3159.0, 3159.0, 3159.0, 3249.8, 3604.4", \ + "3184.5, 3184.5, 3184.5, 3273.9, 3628.9", \ + "3236.2, 3236.2, 3236.2, 3322.8, 3679.1"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__22) { + values ("9625.2, 9625.2, 9625.2, 9911.5, 10452.7", \ + "9620.0, 9620.0, 9620.0, 9906.3, 10447.5", \ + "9609.7, 9609.7, 9609.7, 9896.0, 10437.2", \ + "9589.1, 9589.1, 9589.1, 9875.4, 10416.6", \ + "9547.9, 9547.9, 9547.9, 9834.1, 10375.3"); + } + rise_transition (inslew_load_5x5__22) { + values ("4494.3, 4494.3, 4494.3, 4722.0, 5169.2", \ + "4494.3, 4494.3, 4494.3, 4722.0, 5169.2", \ + "4494.3, 4494.3, 4494.3, 4722.0, 5169.2", \ + "4494.3, 4494.3, 4494.3, 4722.0, 5169.2", \ + "4494.3, 4494.3, 4494.3, 4722.1, 5169.3"); + } + cell_fall (inslew_load_5x5__22) { + values ("10071.9, 10071.9, 10071.9, 10333.7, 10816.1", \ + "10059.7, 10059.7, 10059.7, 10321.5, 10803.8", \ + "10054.1, 10054.1, 10054.1, 10316.1, 10798.6", \ + "10030.0, 10030.0, 10030.0, 10292.3, 10774.9", \ + "9994.4, 9994.4, 9994.4, 10257.0, 10739.8"); + } + fall_transition (inslew_load_5x5__22) { + values ("5227.0, 5227.0, 5227.0, 5354.1, 5626.3", \ + "5226.4, 5226.4, 5226.4, 5353.3, 5625.6", \ + "5236.7, 5236.7, 5236.7, 5363.8, 5635.8", \ + "5245.1, 5245.1, 5245.1, 5372.4, 5644.1", \ + "5260.6, 5260.6, 5260.6, 5388.0, 5659.2"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__22) { + values ("6013.6, 6013.6, 6013.6, 6334.1, 6911.9", \ + "6022.0, 6022.0, 6022.0, 6342.2, 6919.8", \ + "6030.0, 6030.0, 6030.0, 6350.1, 6927.6", \ + "6047.2, 6047.2, 6047.2, 6367.2, 6944.7", \ + "6079.8, 6079.8, 6079.8, 6399.8, 6977.3"); + } + rise_transition (inslew_load_5x5__22) { + values ("2029.1, 2029.1, 2029.1, 2302.0, 2804.3", \ + "2035.5, 2035.5, 2035.5, 2308.2, 2810.3", \ + "2038.8, 2038.8, 2038.8, 2311.4, 2813.4", \ + "2041.3, 2041.3, 2041.3, 2313.9, 2815.7", \ + "2041.3, 2041.3, 2041.3, 2313.9, 2815.7"); + } + cell_fall (inslew_load_5x5__22) { + values ("5177.7, 5177.7, 5177.7, 5439.4, 5856.1", \ + "5190.0, 5190.0, 5190.0, 5452.2, 5869.5", \ + "5205.1, 5205.1, 5205.1, 5467.7, 5886.1", \ + "5213.1, 5213.1, 5213.1, 5476.0, 5895.3", \ + "5229.8, 5229.8, 5229.8, 5493.1, 5943.6"); + } + fall_transition (inslew_load_5x5__22) { + values ("1933.6, 1933.6, 1933.6, 2098.1, 2402.3", \ + "1946.4, 1946.4, 1946.4, 2110.0, 2413.6", \ + "1964.0, 1964.0, 1964.0, 2126.4, 2429.1", \ + "1979.0, 1979.0, 1979.0, 2140.3, 2442.4", \ + "1996.5, 1996.5, 1996.5, 2156.8, 2483.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__22) { + values ("43016.4, 43016.4, 43016.4, 44095.6, 46253.9", \ + "46284.5, 46284.5, 46284.5, 46284.5, 46284.5", \ + "46345.7, 46345.7, 46345.7, 46345.7, 46345.7", \ + "46468.2, 46468.2, 46468.2, 46468.2, 46468.2", \ + "43476.0, 43476.0, 43476.0, 44555.2, 46713.5"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("61121.6, 61121.6, 61121.6, 62200.7, 64359.1", \ + "64437.0, 64437.0, 64437.0, 64437.0, 64437.0", \ + "64593.0, 64593.0, 64593.0, 64593.0, 64593.0", \ + "64904.9, 64904.9, 64904.9, 64904.9, 64904.9", \ + "65528.7, 65528.7, 65528.7, 65528.7, 65528.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__22) { + values ("35850.0, 35850.0, 35850.0, 36929.2, 39087.5", \ + "35890.6, 35890.6, 35890.6, 36969.7, 39128.1", \ + "35960.0, 35960.0, 35960.0, 37039.2, 39197.5", \ + "36097.0, 36097.0, 36097.0, 37176.2, 39334.5", \ + "36369.7, 36369.7, 36369.7, 37448.9, 39607.2"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("56680.8, 56680.8, 56680.8, 57760.0, 59918.3", \ + "59976.3, 59976.3, 59976.3, 59976.3, 59976.3", \ + "60092.3, 60092.3, 60092.3, 60092.3, 60092.3", \ + "60324.3, 60324.3, 60324.3, 60324.3, 60324.3", \ + "60788.3, 60788.3, 60788.3, 60788.3, 60788.3"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__22) { + values ("27824.5, 27824.5, 27824.5, 28903.7, 31062.0", \ + "31084.5, 31084.5, 31084.5, 31084.5, 31084.5", \ + "31129.4, 31129.4, 31129.4, 31129.4, 31129.4", \ + "31219.2, 31219.2, 31219.2, 31219.2, 31219.2", \ + "28161.7, 28161.7, 28161.7, 29240.8, 31399.2"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("24754.1, 24754.1, 24754.1, 25833.3, 27991.7", \ + "24787.3, 24787.3, 24787.3, 25866.4, 28024.8", \ + "24986.9, 24986.9, 24986.9, 26066.1, 28224.4", \ + "25270.1, 25270.1, 25270.1, 26349.2, 28507.6", \ + "25837.9, 25837.9, 25837.9, 26917.0, 29075.4"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__22) { + values ("37647.3, 37647.3, 37647.3, 38726.5, 40884.8", \ + "40915.6, 40915.6, 40915.6, 40915.6, 40915.6", \ + "40977.0, 40977.0, 40977.0, 40977.0, 40977.0", \ + "41099.8, 41099.8, 41099.8, 41099.8, 41099.8", \ + "38108.1, 38108.1, 38108.1, 39187.3, 41345.6"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("40989.9, 40989.9, 40989.9, 42069.0, 44227.4", \ + "41040.4, 41040.4, 41040.4, 42119.5, 44277.9", \ + "41176.3, 41176.3, 41176.3, 42255.5, 44413.8", \ + "41412.0, 41412.0, 41412.0, 42491.2, 44649.5", \ + "41879.0, 41879.0, 41879.0, 42958.2, 45116.5"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__22) { + values ("21931.3, 21931.3, 21931.3, 23010.5, 25168.8", \ + "21978.3, 21978.3, 21978.3, 23057.5, 25215.8", \ + "22051.4, 22051.4, 22051.4, 23130.6, 25288.9", \ + "22189.0, 22189.0, 22189.0, 23268.2, 25426.5", \ + "25690.7, 25690.7, 25690.7, 25690.7, 25690.7"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("19560.0, 19560.0, 19560.0, 20639.1, 22797.5", \ + "19629.3, 19629.3, 19629.3, 20708.5, 22866.8", \ + "19748.2, 19748.2, 19748.2, 20827.4, 22985.7", \ + "19936.2, 19936.2, 19936.2, 21015.3, 23173.7", \ + "20281.6, 20281.6, 20281.6, 21360.8, 23519.1"); + } + } + } + } + + cell (oa2a22_x2) { + area : 32.40 ; + cell_leakage_power : 4.5 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 6.1 ; + } + leakage_power () { + when : "(i3 & !(i2) & !(i1) & i0)" ; + value : 4.4 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3)" ; + value : 5.9 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & !(i0))" ; + value : 4 ; + } + leakage_power () { + when : "((i0 & !(i1) & i2 & !(i3)) | (!(i0) & i1 & !(i2) & i3))" ; + value : 4.2 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 5.6 ; + } + leakage_power () { + when : "(!(i0) & (i1 ^ i2) & !(i3))" ; + value : 3.5 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & !(i1) & !(i2) & i3))" ; + value : 3.7 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 3.1 ; + } + pin (i3) { + direction : input ; + capacitance : 432.96 ; + } + pin (i2) { + direction : input ; + capacitance : 434.46 ; + } + pin (i1) { + direction : input ; + capacitance : 434.46 ; + } + pin (i0) { + direction : input ; + capacitance : 432.96 ; + } + pin (q) { + function : "((i0 & ((i2 & i3) | i1)) | (i2 & i3))" ; + direction : output ; + capacitance : 85.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("7159.5, 7159.5, 7159.5, 7453.5, 7996.2", \ + "7154.3, 7154.3, 7154.3, 7448.3, 7991.0", \ + "7144.0, 7144.0, 7144.0, 7438.0, 7980.7", \ + "7123.4, 7123.4, 7123.4, 7417.4, 7960.1", \ + "7082.2, 7082.2, 7082.2, 7376.2, 7918.9"); + } + rise_transition (inslew_load_5x5__0) { + values ("3185.5, 3185.5, 3185.5, 3428.5, 3896.2", \ + "3185.5, 3185.5, 3185.5, 3428.5, 3896.2", \ + "3185.5, 3185.5, 3185.5, 3428.5, 3896.2", \ + "3185.5, 3185.5, 3185.5, 3428.5, 3896.2", \ + "3185.7, 3185.7, 3185.7, 3428.7, 3896.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("7981.6, 7981.6, 7981.6, 8223.8, 8597.2", \ + "7980.5, 7980.5, 7980.5, 8222.8, 8596.1", \ + "7994.5, 7994.5, 7994.5, 8236.9, 8610.1", \ + "8011.5, 8011.5, 8011.5, 8253.9, 8627.0", \ + "8034.3, 8034.3, 8034.3, 8276.7, 8649.8"); + } + fall_transition (inslew_load_5x5__0) { + values ("3546.2, 3546.2, 3546.2, 3698.2, 3962.9", \ + "3547.4, 3547.4, 3547.4, 3699.4, 3964.0", \ + "3558.4, 3558.4, 3558.4, 3710.1, 3974.1", \ + "3570.1, 3570.1, 3570.1, 3721.3, 3984.7", \ + "3576.9, 3576.9, 3576.9, 3727.9, 3991.0"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("5856.7, 5856.7, 5856.7, 6172.5, 6743.1", \ + "5861.6, 5861.6, 5861.6, 6177.5, 6747.9", \ + "5868.9, 5868.9, 5868.9, 6184.7, 6755.2", \ + "5885.5, 5885.5, 5885.5, 6201.3, 6771.8", \ + "5919.2, 5919.2, 5919.2, 6235.0, 6805.4"); + } + rise_transition (inslew_load_5x5__0) { + values ("2289.6, 2289.6, 2289.6, 2557.5, 3049.5", \ + "2292.4, 2292.4, 2292.4, 2560.3, 3052.2", \ + "2293.3, 2293.3, 2293.3, 2561.2, 3053.1", \ + "2293.8, 2293.8, 2293.8, 2561.6, 3053.5", \ + "2294.1, 2294.1, 2294.1, 2561.9, 3053.8"); + } + cell_fall (inslew_load_5x5__0) { + values ("7220.4, 7220.4, 7220.4, 7459.2, 7933.1", \ + "7219.4, 7219.4, 7219.4, 7458.3, 7931.9", \ + "7233.7, 7233.7, 7233.7, 7472.6, 7943.8", \ + "7250.9, 7250.9, 7250.9, 7489.8, 7958.6", \ + "7273.7, 7273.7, 7273.7, 7513.0, 7979.9"); + } + fall_transition (inslew_load_5x5__0) { + values ("3057.1, 3057.1, 3057.1, 3237.4, 3590.4", \ + "3058.4, 3058.4, 3058.4, 3238.7, 3591.6", \ + "3069.2, 3069.2, 3069.2, 3248.9, 3602.1", \ + "3080.5, 3080.5, 3080.5, 3259.8, 3613.2", \ + "3087.1, 3087.1, 3087.1, 3266.1, 3619.5"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("8072.8, 8072.8, 8072.8, 8361.8, 8901.2", \ + "8077.7, 8077.7, 8077.7, 8366.7, 8906.0", \ + "8084.7, 8084.7, 8084.7, 8373.6, 8913.0", \ + "8101.3, 8101.3, 8101.3, 8390.2, 8929.6", \ + "8134.9, 8134.9, 8134.9, 8423.8, 8963.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("3841.3, 3841.3, 3841.3, 4075.5, 4526.9", \ + "3843.8, 3843.8, 3843.8, 4078.0, 4529.4", \ + "3844.5, 3844.5, 3844.5, 4078.6, 4530.0", \ + "3844.9, 3844.9, 3844.9, 4079.0, 4530.4", \ + "3844.9, 3844.9, 3844.9, 4079.0, 4530.4"); + } + cell_fall (inslew_load_5x5__0) { + values ("10006.6, 10006.6, 10006.6, 10256.5, 10726.0", \ + "10001.2, 10001.2, 10001.2, 10251.1, 10720.6", \ + "9990.5, 9990.5, 9990.5, 10240.4, 10709.9", \ + "9969.1, 9969.1, 9969.1, 10219.0, 10688.5", \ + "9926.2, 9926.2, 9926.2, 10176.1, 10645.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("4707.3, 4707.3, 4707.3, 4831.7, 5117.4", \ + "4707.3, 4707.3, 4707.3, 4831.7, 5117.4", \ + "4707.3, 4707.3, 4707.3, 4831.7, 5117.4", \ + "4707.3, 4707.3, 4707.3, 4831.7, 5117.4", \ + "4707.3, 4707.3, 4707.3, 4831.7, 5117.4"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("9246.8, 9246.8, 9246.8, 9531.7, 10070.5", \ + "9241.6, 9241.6, 9241.6, 9526.5, 10065.3", \ + "9231.3, 9231.3, 9231.3, 9516.2, 10055.0", \ + "9210.7, 9210.7, 9210.7, 9495.6, 10034.4", \ + "9169.4, 9169.4, 9169.4, 9454.3, 9993.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("4596.9, 4596.9, 4596.9, 4822.2, 5265.2", \ + "4596.9, 4596.9, 4596.9, 4822.2, 5265.2", \ + "4596.9, 4596.9, 4596.9, 4822.2, 5265.2", \ + "4596.9, 4596.9, 4596.9, 4822.2, 5265.2", \ + "4596.9, 4596.9, 4596.9, 4822.2, 5265.2"); + } + cell_fall (inslew_load_5x5__0) { + values ("10650.1, 10650.1, 10650.1, 10904.5, 11378.5", \ + "10644.7, 10644.7, 10644.7, 10899.1, 11373.1", \ + "10634.0, 10634.0, 10634.0, 10888.4, 11362.4", \ + "10612.5, 10612.5, 10612.5, 10866.9, 11340.9", \ + "10569.7, 10569.7, 10569.7, 10824.1, 11298.1"); + } + fall_transition (inslew_load_5x5__0) { + values ("5097.6, 5097.6, 5097.6, 5217.0, 5488.6", \ + "5097.6, 5097.6, 5097.6, 5217.0, 5488.6", \ + "5097.6, 5097.6, 5097.6, 5217.0, 5488.6", \ + "5097.6, 5097.6, 5097.6, 5217.0, 5488.6", \ + "5097.6, 5097.6, 5097.6, 5217.0, 5488.6"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("26754.4, 26754.4, 26754.4, 27826.5, 29970.9", \ + "29985.2, 29985.2, 29985.2, 29985.2, 29985.2", \ + "30013.9, 30013.9, 30013.9, 30013.9, 30013.9", \ + "30071.4, 30071.4, 30071.4, 30071.4, 30071.4", \ + "26970.3, 26970.3, 26970.3, 28042.5, 30186.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("24955.5, 24955.5, 24955.5, 26027.7, 28172.0", \ + "25001.8, 25001.8, 25001.8, 26074.0, 28218.3", \ + "25118.5, 25118.5, 25118.5, 26190.7, 28335.0", \ + "25322.4, 25322.4, 25322.4, 26394.6, 28538.9", \ + "25682.9, 25682.9, 25682.9, 26755.0, 28899.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("21794.5, 21794.5, 21794.5, 22866.7, 25011.0", \ + "21812.2, 21812.2, 21812.2, 22884.3, 25028.7", \ + "21836.5, 21836.5, 21836.5, 22908.7, 25053.0", \ + "21881.9, 21881.9, 21881.9, 22954.0, 25098.4", \ + "21971.5, 21971.5, 21971.5, 23043.7, 25188.0"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("22227.9, 22227.9, 22227.9, 23300.1, 25444.4", \ + "22272.6, 22272.6, 22272.6, 23344.8, 25489.1", \ + "22385.9, 22385.9, 22385.9, 23458.1, 25602.4", \ + "22582.9, 22582.9, 22582.9, 23655.0, 25799.4", \ + "22929.7, 22929.7, 22929.7, 24001.8, 26146.2"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__0) { + values ("30312.5, 30312.5, 30312.5, 31384.7, 33529.0", \ + "30344.4, 30344.4, 30344.4, 31416.6, 33560.9", \ + "30396.3, 30396.3, 30396.3, 31468.5, 33612.8", \ + "30498.1, 30498.1, 30498.1, 31570.3, 33714.6", \ + "33916.0, 33916.0, 33916.0, 33916.0, 33916.0"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("33112.5, 33112.5, 33112.5, 34184.6, 36329.0", \ + "36360.5, 36360.5, 36360.5, 36360.5, 36360.5", \ + "36423.6, 36423.6, 36423.6, 36423.6, 36423.6", \ + "36549.9, 36549.9, 36549.9, 36549.9, 36549.9", \ + "36802.4, 36802.4, 36802.4, 36802.4, 36802.4"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__0) { + values ("35201.4, 35201.4, 35201.4, 36273.6, 38417.9", \ + "38440.8, 38440.8, 38440.8, 38440.8, 38440.8", \ + "38486.6, 38486.6, 38486.6, 38486.6, 38486.6", \ + "38578.2, 38578.2, 38578.2, 38578.2, 38578.2", \ + "38761.4, 38761.4, 38761.4, 38761.4, 38761.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("35830.6, 35830.6, 35830.6, 36902.8, 39047.1", \ + "39091.2, 39091.2, 39091.2, 39091.2, 39091.2", \ + "39179.4, 39179.4, 39179.4, 39179.4, 39179.4", \ + "39355.7, 39355.7, 39355.7, 39355.7, 39355.7", \ + "39708.4, 39708.4, 39708.4, 39708.4, 39708.4"); + } + } + } + } + + cell (noa2a22_x4) { + area : 39.60 ; + cell_leakage_power : 8.3 ; + leakage_power () { + when : "(i0 & i1 & (i2 | i3))" ; + value : 8 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & i1 & i0)" ; + value : 8.1 ; + } + leakage_power () { + when : "(!(i3) & i2 & !(i1) & i0)" ; + value : 9.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3) | (!(i0) & i1 & i2 & !(i3)))" ; + value : 9 ; + } + leakage_power () { + when : "(i3 & !(i2) & i1 & !(i0))" ; + value : 8.8 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 7.5 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & !(i1) & i2 & !(i3)))" ; + value : 8.5 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & !(i2) & i3)))" ; + value : 8.3 ; + } + leakage_power () { + when : "((i0 & !(i1) & i2 & i3) | (!(i0) & ((i1 & i2 & i3) | (!(i1) & !(i2) & !(i3)))))" ; + value : 7.8 ; + } + pin (i3) { + direction : input ; + capacitance : 434.46 ; + } + pin (i2) { + direction : input ; + capacitance : 432.96 ; + } + pin (i1) { + direction : input ; + capacitance : 434.46 ; + } + pin (i0) { + direction : input ; + capacitance : 432.96 ; + } + pin (nq) { + function : "((!(i1) & (!(i2) | !(i3))) | (!((i2 & i3)) & !(i0)))" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("13296.6, 13296.6, 13296.6, 13558.9, 14046.4", \ + "13297.4, 13297.4, 13297.4, 13559.7, 14047.1", \ + "13321.1, 13321.1, 13321.1, 13583.3, 14070.8", \ + "13347.7, 13347.7, 13347.7, 13609.8, 14097.2", \ + "13375.6, 13375.6, 13375.6, 13637.7, 14125.1"); + } + rise_transition (inslew_load_5x5__3) { + values ("3345.6, 3345.6, 3345.6, 3560.6, 3972.2", \ + "3346.7, 3346.7, 3346.7, 3561.7, 3973.3", \ + "3355.1, 3355.1, 3355.1, 3569.7, 3981.3", \ + "3363.8, 3363.8, 3363.8, 3578.2, 3989.6", \ + "3368.7, 3368.7, 3368.7, 3583.0, 3994.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("12533.8, 12533.8, 12533.8, 12744.8, 13157.4", \ + "12528.7, 12528.7, 12528.7, 12739.7, 13152.3", \ + "12518.3, 12518.3, 12518.3, 12729.3, 13141.9", \ + "12497.7, 12497.7, 12497.7, 12708.7, 13121.3", \ + "12457.4, 12457.4, 12457.4, 12668.4, 13081.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("3179.6, 3179.6, 3179.6, 3333.2, 3654.8", \ + "3179.6, 3179.6, 3179.6, 3333.2, 3654.8", \ + "3179.6, 3179.6, 3179.6, 3333.2, 3654.8", \ + "3179.6, 3179.6, 3179.6, 3333.2, 3654.8", \ + "3180.1, 3180.1, 3180.1, 3333.7, 3655.3"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("12229.4, 12229.4, 12229.4, 12494.2, 12986.1", \ + "12230.7, 12230.7, 12230.7, 12495.5, 12987.3", \ + "12255.6, 12255.6, 12255.6, 12520.3, 13011.7", \ + "12283.4, 12283.4, 12283.4, 12548.0, 13039.0", \ + "12311.5, 12311.5, 12311.5, 12576.1, 13066.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("3031.0, 3031.0, 3031.0, 3250.8, 3672.3", \ + "3032.3, 3032.3, 3032.3, 3252.1, 3673.5", \ + "3041.1, 3041.1, 3041.1, 3260.7, 3681.9", \ + "3050.0, 3050.0, 3050.0, 3269.5, 3690.4", \ + "3055.0, 3055.0, 3055.0, 3274.4, 3695.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("11237.5, 11237.5, 11237.5, 11448.6, 11880.4", \ + "11241.1, 11241.1, 11241.1, 11452.2, 11883.9", \ + "11248.8, 11248.8, 11248.8, 11459.9, 11891.6", \ + "11264.8, 11264.8, 11264.8, 11476.0, 11907.7", \ + "11297.9, 11297.9, 11297.9, 11509.0, 11940.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("2975.0, 2975.0, 2975.0, 3137.3, 3460.0", \ + "2975.2, 2975.2, 2975.2, 3137.5, 3460.2", \ + "2975.2, 2975.2, 2975.2, 3137.6, 3460.2", \ + "2975.3, 2975.3, 2975.3, 3137.6, 3460.3", \ + "2975.4, 2975.4, 2975.4, 3137.7, 3460.4"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("17212.5, 17212.5, 17212.5, 17467.4, 17951.5", \ + "17207.1, 17207.1, 17207.1, 17462.0, 17946.1", \ + "17196.4, 17196.4, 17196.4, 17451.3, 17935.4", \ + "17174.9, 17174.9, 17174.9, 17429.8, 17913.9", \ + "17132.0, 17132.0, 17132.0, 17386.9, 17871.0"); + } + rise_transition (inslew_load_5x5__3) { + values ("4468.0, 4468.0, 4468.0, 4667.9, 5062.6", \ + "4468.0, 4468.0, 4468.0, 4667.9, 5062.6", \ + "4468.0, 4468.0, 4468.0, 4667.9, 5062.6", \ + "4468.0, 4468.0, 4468.0, 4667.9, 5062.6", \ + "4468.0, 4468.0, 4468.0, 4667.9, 5062.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("14959.2, 14959.2, 14959.2, 15174.1, 15483.0", \ + "14954.0, 14954.0, 14954.0, 15168.9, 15477.8", \ + "14943.7, 14943.7, 14943.7, 15158.6, 15467.5", \ + "14923.1, 14923.1, 14923.1, 15138.0, 15446.9", \ + "14881.9, 14881.9, 14881.9, 15096.9, 15405.8"); + } + fall_transition (inslew_load_5x5__3) { + values ("3755.8, 3755.8, 3755.8, 3880.5, 4084.1", \ + "3755.8, 3755.8, 3755.8, 3880.5, 4084.1", \ + "3755.8, 3755.8, 3755.8, 3880.5, 4084.1", \ + "3755.8, 3755.8, 3755.8, 3880.5, 4084.1", \ + "3755.9, 3755.9, 3755.9, 3880.6, 4084.2"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("16296.4, 16296.4, 16296.4, 16552.5, 17037.9", \ + "16291.1, 16291.1, 16291.1, 16547.2, 17032.6", \ + "16280.3, 16280.3, 16280.3, 16536.4, 17021.8", \ + "16258.9, 16258.9, 16258.9, 16515.0, 17000.4", \ + "16215.9, 16215.9, 16215.9, 16472.0, 16957.4"); + } + rise_transition (inslew_load_5x5__3) { + values ("4203.5, 4203.5, 4203.5, 4406.4, 4804.4", \ + "4203.5, 4203.5, 4203.5, 4406.4, 4804.4", \ + "4203.5, 4203.5, 4203.5, 4406.4, 4804.4", \ + "4203.5, 4203.5, 4203.5, 4406.4, 4804.4", \ + "4203.5, 4203.5, 4203.5, 4406.4, 4804.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("13540.9, 13540.9, 13540.9, 13752.4, 14163.5", \ + "13546.0, 13546.0, 13546.0, 13757.5, 14168.6", \ + "13553.4, 13553.4, 13553.4, 13764.8, 14175.9", \ + "13569.9, 13569.9, 13569.9, 13781.4, 14192.5", \ + "13603.5, 13603.5, 13603.5, 13814.9, 14226.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("3385.9, 3385.9, 3385.9, 3531.9, 3845.6", \ + "3386.7, 3386.7, 3386.7, 3532.7, 3846.3", \ + "3387.0, 3387.0, 3387.0, 3532.9, 3846.6", \ + "3387.1, 3387.1, 3387.1, 3533.0, 3846.7", \ + "3387.2, 3387.2, 3387.2, 3533.1, 3846.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("58111.0, 58111.0, 58111.0, 60006.8, 63798.5", \ + "58161.5, 58161.5, 58161.5, 60057.3, 63849.0", \ + "58304.3, 58304.3, 58304.3, 60200.1, 63991.8", \ + "58534.4, 58534.4, 58534.4, 60430.2, 64221.9", \ + "58909.3, 58909.3, 58909.3, 60805.1, 64596.8"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("55976.1, 55976.1, 55976.1, 57871.9, 61663.6", \ + "61677.9, 61677.9, 61677.9, 61677.9, 61677.9", \ + "61706.6, 61706.6, 61706.6, 61706.6, 61706.6", \ + "61764.1, 61764.1, 61764.1, 61764.1, 61764.1", \ + "56196.1, 56196.1, 56196.1, 58091.9, 61883.6"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("54397.4, 54397.4, 54397.4, 56293.2, 60084.9", \ + "54447.1, 54447.1, 54447.1, 56342.9, 60134.6", \ + "54586.7, 54586.7, 54586.7, 56482.5, 60274.2", \ + "54809.8, 54809.8, 54809.8, 56705.6, 60497.3", \ + "55170.7, 55170.7, 55170.7, 57066.6, 60858.3"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("50878.4, 50878.4, 50878.4, 52774.2, 56565.9", \ + "50893.2, 50893.2, 50893.2, 52789.1, 56580.7", \ + "50917.6, 50917.6, 50917.6, 52813.4, 56605.1", \ + "50962.4, 50962.4, 50962.4, 52858.2, 56649.9", \ + "51055.9, 51055.9, 51055.9, 52951.7, 56743.4"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("72707.3, 72707.3, 72707.3, 74603.1, 78394.8", \ + "78438.9, 78438.9, 78438.9, 78438.9, 78438.9", \ + "78527.0, 78527.0, 78527.0, 78527.0, 78527.0", \ + "78703.4, 78703.4, 78703.4, 78703.4, 78703.4", \ + "79056.1, 79056.1, 79056.1, 79056.1, 79056.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("65180.4, 65180.4, 65180.4, 67076.3, 70868.0", \ + "70890.8, 70890.8, 70890.8, 70890.8, 70890.8", \ + "70936.6, 70936.6, 70936.6, 70936.6, 70936.6", \ + "71028.2, 71028.2, 71028.2, 71028.2, 71028.2", \ + "65524.6, 65524.6, 65524.6, 67420.5, 71212.1"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__3) { + values ("69114.8, 69114.8, 69114.8, 71010.7, 74802.3", \ + "74833.9, 74833.9, 74833.9, 74833.9, 74833.9", \ + "74897.0, 74897.0, 74897.0, 74897.0, 74897.0", \ + "75023.3, 75023.3, 75023.3, 75023.3, 75023.3", \ + "75275.7, 75275.7, 75275.7, 75275.7, 75275.7"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("59827.7, 59827.7, 59827.7, 61723.6, 65515.3", \ + "59860.8, 59860.8, 59860.8, 61756.6, 65548.3", \ + "59913.6, 59913.6, 59913.6, 61809.5, 65601.1", \ + "60015.3, 60015.3, 60015.3, 61911.2, 65702.8", \ + "60217.6, 60217.6, 60217.6, 62113.5, 65905.1"); + } + } + } + } + + cell (a4_x2) { + area : 25.20 ; + cell_leakage_power : 3.6 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 6.1 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & i0)" ; + value : 4.4 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3) | (!(i0) & i1 & i2 & i3))" ; + value : 4 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))) | (!(i0) & ((i1 & (i2 ^ i3)) | (!(i1) & i2 & i3))))" ; + value : 3.1 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))))" ; + value : 2.1 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 1.9 ; + } + pin (i3) { + direction : input ; + capacitance : 569.03 ; + } + pin (i2) { + direction : input ; + capacitance : 570.98 ; + } + pin (i1) { + direction : input ; + capacitance : 570.08 ; + } + pin (i0) { + direction : input ; + capacitance : 569.18 ; + } + pin (q) { + function : "(i3 & i2 & i1 & i0)" ; + direction : output ; + capacitance : 89.69 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__23) { + values ("11184.8, 11184.8, 11184.8, 11467.5, 12004.4", \ + "11170.2, 11170.2, 11170.2, 11452.9, 11989.8", \ + "11141.2, 11141.2, 11141.2, 11423.9, 11960.8", \ + "11083.0, 11083.0, 11083.0, 11365.7, 11902.6", \ + "10966.8, 10966.8, 10966.8, 11249.4, 11786.4"); + } + rise_transition (inslew_load_5x5__23) { + values ("6649.1, 6649.1, 6649.1, 6878.1, 7330.5", \ + "6649.1, 6649.1, 6649.1, 6878.1, 7330.5", \ + "6649.1, 6649.1, 6649.1, 6878.1, 7330.5", \ + "6649.1, 6649.1, 6649.1, 6878.1, 7330.5", \ + "6649.2, 6649.2, 6649.2, 6878.1, 7330.5"); + } + cell_fall (inslew_load_5x5__23) { + values ("7714.0, 7714.0, 7714.0, 7963.9, 8542.2", \ + "7722.8, 7722.8, 7722.8, 7972.7, 8551.0", \ + "7740.4, 7740.4, 7740.4, 7990.3, 8568.6", \ + "7775.6, 7775.6, 7775.6, 8025.5, 8603.8", \ + "7845.9, 7845.9, 7845.9, 8095.8, 8674.1"); + } + fall_transition (inslew_load_5x5__23) { + values ("2738.1, 2738.1, 2738.1, 2940.3, 3301.5", \ + "2738.1, 2738.1, 2738.1, 2940.3, 3301.5", \ + "2738.1, 2738.1, 2738.1, 2940.3, 3301.5", \ + "2738.1, 2738.1, 2738.1, 2940.3, 3301.5", \ + "2738.1, 2738.1, 2738.1, 2940.3, 3301.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__23) { + values ("9366.0, 9366.0, 9366.0, 9647.5, 10196.2", \ + "9358.5, 9358.5, 9358.5, 9640.0, 10188.6", \ + "9340.8, 9340.8, 9340.8, 9622.3, 10170.9", \ + "9305.4, 9305.4, 9305.4, 9586.9, 10135.5", \ + "9235.3, 9235.3, 9235.3, 9516.8, 10065.4"); + } + rise_transition (inslew_load_5x5__23) { + values ("5379.3, 5379.3, 5379.3, 5612.0, 6071.9", \ + "5381.5, 5381.5, 5381.5, 5614.2, 6074.1", \ + "5382.4, 5382.4, 5382.4, 5615.0, 6074.9", \ + "5382.4, 5382.4, 5382.4, 5615.0, 6074.9", \ + "5382.4, 5382.4, 5382.4, 5615.1, 6075.0"); + } + cell_fall (inslew_load_5x5__23) { + values ("7081.9, 7081.9, 7081.9, 7407.7, 7938.4", \ + "7090.7, 7090.7, 7090.7, 7416.5, 7947.2", \ + "7108.3, 7108.3, 7108.3, 7434.1, 7964.8", \ + "7143.5, 7143.5, 7143.5, 7469.3, 8000.0", \ + "7213.8, 7213.8, 7213.8, 7539.6, 8070.3"); + } + fall_transition (inslew_load_5x5__23) { + values ("2447.6, 2447.6, 2447.6, 2670.8, 2998.4", \ + "2447.6, 2447.6, 2447.6, 2670.8, 2998.4", \ + "2447.6, 2447.6, 2447.6, 2670.8, 2998.4", \ + "2447.6, 2447.6, 2447.6, 2670.8, 2998.4", \ + "2447.6, 2447.6, 2447.6, 2670.8, 2998.4"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__23) { + values ("7457.5, 7457.5, 7457.5, 7756.8, 8316.3", \ + "7458.2, 7458.2, 7458.2, 7757.6, 8317.0", \ + "7461.9, 7461.9, 7461.9, 7761.1, 8320.5", \ + "7451.0, 7451.0, 7451.0, 7750.2, 8309.6", \ + "7423.1, 7423.1, 7423.1, 7722.3, 8281.7"); + } + rise_transition (inslew_load_5x5__23) { + values ("4010.9, 4010.9, 4010.9, 4253.6, 4721.9", \ + "4018.5, 4018.5, 4018.5, 4261.2, 4729.4", \ + "4032.4, 4032.4, 4032.4, 4274.9, 4742.9", \ + "4039.1, 4039.1, 4039.1, 4281.7, 4749.5", \ + "4039.1, 4039.1, 4039.1, 4281.6, 4749.4"); + } + cell_fall (inslew_load_5x5__23) { + values ("6441.9, 6441.9, 6441.9, 6717.7, 7190.1", \ + "6450.7, 6450.7, 6450.7, 6726.5, 7198.9", \ + "6468.3, 6468.3, 6468.3, 6744.1, 7216.5", \ + "6503.5, 6503.5, 6503.5, 6779.3, 7251.7", \ + "6573.8, 6573.8, 6573.8, 6849.6, 7322.0"); + } + fall_transition (inslew_load_5x5__23) { + values ("2142.5, 2142.5, 2142.5, 2304.8, 2635.1", \ + "2142.5, 2142.5, 2142.5, 2304.8, 2635.1", \ + "2142.5, 2142.5, 2142.5, 2304.8, 2635.1", \ + "2142.5, 2142.5, 2142.5, 2304.8, 2635.1", \ + "2142.4, 2142.4, 2142.4, 2304.8, 2635.1"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__23) { + values ("5421.7, 5421.7, 5421.7, 5745.2, 6332.5", \ + "5438.4, 5438.4, 5438.4, 5760.8, 6347.8", \ + "5505.0, 5505.0, 5505.0, 5823.9, 6410.2", \ + "5557.3, 5557.3, 5557.3, 5873.4, 6459.0", \ + "5571.3, 5571.3, 5571.3, 5886.8, 6472.4"); + } + rise_transition (inslew_load_5x5__23) { + values ("2474.3, 2474.3, 2474.3, 2747.2, 3251.7", \ + "2494.2, 2494.2, 2494.2, 2766.2, 3270.1", \ + "2557.1, 2557.1, 2557.1, 2826.4, 3328.7", \ + "2608.7, 2608.7, 2608.7, 2876.0, 3376.9", \ + "2619.9, 2619.9, 2619.9, 2886.8, 3387.4"); + } + cell_fall (inslew_load_5x5__23) { + values ("5469.2, 5469.2, 5469.2, 5717.8, 6240.6", \ + "5478.0, 5478.0, 5478.0, 5726.6, 6249.4", \ + "5495.6, 5495.6, 5495.6, 5744.2, 6267.0", \ + "5530.8, 5530.8, 5530.8, 5779.4, 6302.2", \ + "5601.2, 5601.2, 5601.2, 5849.8, 6372.6"); + } + fall_transition (inslew_load_5x5__23) { + values ("1557.9, 1557.9, 1557.9, 1770.2, 2152.6", \ + "1557.9, 1557.9, 1557.9, 1770.2, 2152.6", \ + "1557.9, 1557.9, 1557.9, 1770.2, 2152.6", \ + "1557.9, 1557.9, 1557.9, 1770.2, 2152.6", \ + "1558.0, 1558.0, 1558.0, 1770.3, 2152.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__23) { + values ("49360.0, 49360.0, 49360.0, 50481.1, 52723.5", \ + "52740.1, 52740.1, 52740.1, 52740.1, 52740.1", \ + "52773.2, 52773.2, 52773.2, 52773.2, 52773.2", \ + "52839.6, 52839.6, 52839.6, 52839.6, 52839.6", \ + "49609.0, 49609.0, 49609.0, 50730.2, 52972.5"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("30476.9, 30476.9, 30476.9, 31598.0, 33840.4", \ + "33919.2, 33919.2, 33919.2, 33919.2, 33919.2", \ + "34076.8, 34076.8, 34076.8, 34076.8, 34076.8", \ + "34392.0, 34392.0, 34392.0, 34392.0, 34392.0", \ + "35022.5, 35022.5, 35022.5, 35022.5, 35022.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__23) { + values ("40447.6, 40447.6, 40447.6, 41568.8, 43811.1", \ + "40473.5, 40473.5, 40473.5, 41594.7, 43837.1", \ + "40515.2, 40515.2, 40515.2, 41636.3, 43878.7", \ + "43956.9, 43956.9, 43956.9, 43956.9, 43956.9", \ + "40750.2, 40750.2, 40750.2, 41871.3, 44113.7"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("27297.4, 27297.4, 27297.4, 28418.5, 30660.9", \ + "30722.4, 30722.4, 30722.4, 30722.4, 30722.4", \ + "30845.4, 30845.4, 30845.4, 30845.4, 30845.4", \ + "31091.4, 31091.4, 31091.4, 31091.4, 31091.4", \ + "31583.4, 31583.4, 31583.4, 31583.4, 31583.4"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__23) { + values ("31486.3, 31486.3, 31486.3, 32607.5, 34849.8", \ + "31528.9, 31528.9, 31528.9, 32650.0, 34892.4", \ + "31609.9, 31609.9, 31609.9, 32731.1, 34973.4", \ + "31715.6, 31715.6, 31715.6, 32836.7, 35079.1", \ + "31890.4, 31890.4, 31890.4, 33011.5, 35253.9"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("23475.3, 23475.3, 23475.3, 24596.4, 26838.8", \ + "26888.3, 26888.3, 26888.3, 26888.3, 26888.3", \ + "26987.5, 26987.5, 26987.5, 26987.5, 26987.5", \ + "27185.7, 27185.7, 27185.7, 27185.7, 27185.7", \ + "24218.7, 24218.7, 24218.7, 25339.9, 27582.2"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__23) { + values ("22847.6, 22847.6, 22847.6, 23968.8, 26211.1", \ + "22916.3, 22916.3, 22916.3, 24037.5, 26279.8", \ + "23107.6, 23107.6, 23107.6, 24228.7, 26471.1", \ + "23320.9, 23320.9, 23320.9, 24442.0, 26684.4", \ + "23534.9, 23534.9, 23534.9, 24656.1, 26898.4"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("18669.4, 18669.4, 18669.4, 19790.6, 22032.9", \ + "22074.0, 22074.0, 22074.0, 22074.0, 22074.0", \ + "22156.1, 22156.1, 22156.1, 22156.1, 22156.1", \ + "22320.3, 22320.3, 22320.3, 22320.3, 22320.3", \ + "19285.4, 19285.4, 19285.4, 20406.6, 22648.9"); + } + } + } + } + + cell (a3_x2) { + area : 21.60 ; + cell_leakage_power : 3.8 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 5.3 ; + } + leakage_power () { + when : "(i0 & (i1 ^ i2))" ; + value : 4 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0))" ; + value : 4.4 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2)) | (!(i0) & (i1 ^ i2)))" ; + value : 3.1 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 2.1 ; + } + pin (i2) { + direction : input ; + capacitance : 568.43 ; + } + pin (i1) { + direction : input ; + capacitance : 567.53 ; + } + pin (i0) { + direction : input ; + capacitance : 566.63 ; + } + pin (q) { + function : "(i1 & i0 & i2)" ; + direction : output ; + capacitance : 89.69 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__23) { + values ("3950.7, 3950.7, 3950.7, 4304.0, 4930.9", \ + "3977.5, 3977.5, 3977.5, 4329.1, 4955.3", \ + "3999.8, 3999.8, 3999.8, 4349.9, 4975.6", \ + "4010.1, 4010.1, 4010.1, 4359.7, 4985.3", \ + "4037.3, 4037.3, 4037.3, 4386.6, 5011.9"); + } + rise_transition (inslew_load_5x5__23) { + values ("1232.5, 1232.5, 1232.5, 1535.1, 2096.7", \ + "1257.7, 1257.7, 1257.7, 1558.9, 2119.9", \ + "1279.0, 1279.0, 1279.0, 1579.2, 2139.6", \ + "1285.0, 1285.0, 1285.0, 1584.9, 2145.2", \ + "1292.9, 1292.9, 1292.9, 1592.3, 2152.4"); + } + cell_fall (inslew_load_5x5__23) { + values ("5409.4, 5409.4, 5409.4, 5659.9, 6186.5", \ + "5418.2, 5418.2, 5418.2, 5668.7, 6195.3", \ + "5435.8, 5435.8, 5435.8, 5686.3, 6212.9", \ + "5471.0, 5471.0, 5471.0, 5721.5, 6248.1", \ + "5541.3, 5541.3, 5541.3, 5791.8, 6318.4"); + } + fall_transition (inslew_load_5x5__23) { + values ("1528.3, 1528.3, 1528.3, 1746.8, 2127.5", \ + "1528.3, 1528.3, 1528.3, 1746.8, 2127.5", \ + "1528.3, 1528.3, 1528.3, 1746.8, 2127.5", \ + "1528.3, 1528.3, 1528.3, 1746.8, 2127.5", \ + "1528.4, 1528.4, 1528.4, 1746.8, 2127.6"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__23) { + values ("5754.9, 5754.9, 5754.9, 6070.8, 6657.0", \ + "5751.8, 5751.8, 5751.8, 6067.6, 6653.8", \ + "5742.9, 5742.9, 5742.9, 6058.6, 6644.8", \ + "5726.6, 5726.6, 5726.6, 6042.3, 6628.5", \ + "5694.9, 5694.9, 5694.9, 6010.6, 6596.8"); + } + rise_transition (inslew_load_5x5__23) { + values ("2622.6, 2622.6, 2622.6, 2890.0, 3391.1", \ + "2625.0, 2625.0, 2625.0, 2892.2, 3393.3", \ + "2625.5, 2625.5, 2625.5, 2892.7, 3393.8", \ + "2625.6, 2625.6, 2625.6, 2892.8, 3393.9", \ + "2626.4, 2626.4, 2626.4, 2893.6, 3394.6"); + } + cell_fall (inslew_load_5x5__23) { + values ("6390.8, 6390.8, 6390.8, 6665.8, 7136.1", \ + "6399.6, 6399.6, 6399.6, 6674.6, 7144.9", \ + "6417.2, 6417.2, 6417.2, 6692.2, 7162.5", \ + "6452.4, 6452.4, 6452.4, 6727.4, 7197.7", \ + "6522.7, 6522.7, 6522.7, 6797.7, 7268.0"); + } + fall_transition (inslew_load_5x5__23) { + values ("2121.3, 2121.3, 2121.3, 2282.6, 2614.6", \ + "2121.3, 2121.3, 2121.3, 2282.6, 2614.6", \ + "2121.3, 2121.3, 2121.3, 2282.6, 2614.6", \ + "2121.3, 2121.3, 2121.3, 2282.6, 2614.6", \ + "2121.3, 2121.3, 2121.3, 2282.7, 2614.6"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__23) { + values ("7434.5, 7434.5, 7434.5, 7735.4, 8295.4", \ + "7423.4, 7423.4, 7423.4, 7724.3, 8284.3", \ + "7401.3, 7401.3, 7401.3, 7702.2, 8262.2", \ + "7356.9, 7356.9, 7356.9, 7657.8, 8217.8", \ + "7268.4, 7268.4, 7268.4, 7569.4, 8129.3"); + } + rise_transition (inslew_load_5x5__23) { + values ("3825.8, 3825.8, 3825.8, 4070.8, 4542.4", \ + "3825.8, 3825.8, 3825.8, 4070.8, 4542.4", \ + "3825.8, 3825.8, 3825.8, 4070.8, 4542.4", \ + "3825.8, 3825.8, 3825.8, 4070.8, 4542.4", \ + "3826.1, 3826.1, 3826.1, 4071.1, 4542.8"); + } + cell_fall (inslew_load_5x5__23) { + values ("7035.1, 7035.1, 7035.1, 7361.6, 7888.4", \ + "7043.9, 7043.9, 7043.9, 7370.4, 7897.2", \ + "7061.5, 7061.5, 7061.5, 7388.0, 7914.8", \ + "7096.6, 7096.6, 7096.6, 7423.1, 7949.9", \ + "7167.0, 7167.0, 7167.0, 7493.5, 8020.3"); + } + fall_transition (inslew_load_5x5__23) { + values ("2432.6, 2432.6, 2432.6, 2653.3, 2979.5", \ + "2432.6, 2432.6, 2432.6, 2653.3, 2979.5", \ + "2432.6, 2432.6, 2432.6, 2653.3, 2979.5", \ + "2432.6, 2432.6, 2432.6, 2653.3, 2979.5", \ + "2432.6, 2432.6, 2432.6, 2653.3, 2979.5"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__23) { + values ("19947.9, 19947.9, 19947.9, 21069.0, 23311.4", \ + "20017.8, 20017.8, 20017.8, 21139.0, 23381.3", \ + "20102.6, 20102.6, 20102.6, 21223.7, 23466.1", \ + "20201.7, 20201.7, 20201.7, 21322.9, 23565.2", \ + "20391.7, 20391.7, 20391.7, 21512.9, 23755.2"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("18382.5, 18382.5, 18382.5, 19503.7, 21746.0", \ + "21795.6, 21795.6, 21795.6, 21795.6, 21795.6", \ + "21894.7, 21894.7, 21894.7, 21894.7, 21894.7", \ + "22092.9, 22092.9, 22092.9, 22092.9, 22092.9", \ + "19126.0, 19126.0, 19126.0, 20247.2, 22489.5"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__23) { + values ("28008.8, 28008.8, 28008.8, 29130.0, 31372.3", \ + "28033.7, 28033.7, 28033.7, 29154.8, 31397.2", \ + "28074.0, 28074.0, 28074.0, 29195.2, 31437.5", \ + "28152.5, 28152.5, 28152.5, 29273.6, 31516.0", \ + "28311.0, 28311.0, 28311.0, 29432.1, 31674.5"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("23191.8, 23191.8, 23191.8, 24313.0, 26555.3", \ + "26616.8, 26616.8, 26616.8, 26616.8, 26616.8", \ + "26739.8, 26739.8, 26739.8, 26739.8, 26739.8", \ + "26985.9, 26985.9, 26985.9, 26985.9, 26985.9", \ + "24114.5, 24114.5, 24114.5, 25235.7, 27478.0"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__23) { + values ("36475.0, 36475.0, 36475.0, 37596.1, 39838.5", \ + "39855.1, 39855.1, 39855.1, 39855.1, 39855.1", \ + "39888.2, 39888.2, 39888.2, 39888.2, 39888.2", \ + "39954.6, 39954.6, 39954.6, 39954.6, 39954.6", \ + "36724.7, 36724.7, 36724.7, 37845.9, 40088.2"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("27019.3, 27019.3, 27019.3, 28140.4, 30382.8", \ + "30461.6, 30461.6, 30461.6, 30461.6, 30461.6", \ + "30619.2, 30619.2, 30619.2, 30619.2, 30619.2", \ + "30934.4, 30934.4, 30934.4, 30934.4, 30934.4", \ + "31564.9, 31564.9, 31564.9, 31564.9, 31564.9"); + } + } + } + } + + cell (inv_x1) { + area : 10.80 ; + cell_leakage_power : 1.1 ; + leakage_power () { + when : "i" ; + value : 0.83 ; + } + leakage_power () { + when : "!(i)" ; + value : 1.4 ; + } + pin (i) { + direction : input ; + capacitance : 438.56 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 53.63 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("1323.3, 1323.3, 1323.3, 1527.9, 1933.8", \ + "1332.1, 1332.1, 1332.1, 1536.7, 1942.6", \ + "1349.7, 1349.7, 1349.7, 1554.3, 1960.2", \ + "1383.1, 1383.1, 1383.1, 1588.7, 1995.2", \ + "1411.4, 1411.4, 1411.4, 1632.9, 2055.3"); + } + rise_transition (inslew_load_5x5__24) { + values ("553.7, 553.7, 553.7, 826.4, 1371.9", \ + "553.7, 553.7, 553.7, 826.4, 1371.9", \ + "553.7, 553.7, 553.7, 826.4, 1371.9", \ + "555.1, 555.1, 555.1, 827.7, 1372.4", \ + "571.9, 571.9, 571.9, 849.5, 1391.0"); + } + cell_fall (inslew_load_5x5__24) { + values ("947.0, 947.0, 947.0, 1070.8, 1316.4", \ + "955.8, 955.8, 955.8, 1079.6, 1325.2", \ + "973.3, 973.3, 973.3, 1097.1, 1342.8", \ + "1000.9, 1000.9, 1000.9, 1128.0, 1376.6", \ + "989.0, 989.0, 989.0, 1137.8, 1412.9"); + } + fall_transition (inslew_load_5x5__24) { + values ("358.8, 358.8, 358.8, 522.0, 848.4", \ + "358.8, 358.8, 358.8, 522.0, 848.4", \ + "358.9, 358.9, 358.9, 522.1, 848.4", \ + "362.9, 362.9, 362.9, 526.6, 851.7", \ + "385.1, 385.1, 385.1, 558.4, 887.6"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__24) { + values ("701.9, 701.9, 701.9, 1372.3, 2713.1", \ + "746.0, 746.0, 746.0, 1416.4, 2757.2", \ + "834.2, 834.2, 834.2, 1504.6, 2845.4", \ + "1010.6, 1010.6, 1010.6, 1681.0, 3021.7", \ + "1363.3, 1363.3, 1363.3, 2033.7, 3374.4"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("705.8, 705.8, 705.8, 1376.2, 2717.0", \ + "728.7, 728.7, 728.7, 1399.1, 2739.9", \ + "774.5, 774.5, 774.5, 1444.9, 2785.7", \ + "866.1, 866.1, 866.1, 1536.5, 2877.3", \ + "1049.3, 1049.3, 1049.3, 1719.7, 3060.5"); + } + } + } + } + + cell (sff3_x4) { + area : 100.80 ; + cell_leakage_power : 18 ; + pin (i2) { + direction : input ; + capacitance : 452.77 ; + internal_power (energy_i2) { + rise_power (energy_inslew_5__0) { + values ("33407.3, 33426.6, 33462.0, 33524.3, 33646.9"); + } + fall_power (energy_inslew_5__0) { + values ("34475.6, 34519.4, 34599.3, 34759.8, 35066.4"); + } + } + } + pin (i1) { + direction : input ; + capacitance : 454.85 ; + internal_power (energy_i1) { + rise_power (energy_inslew_5__0) { + values ("33407.3, 33426.6, 33462.0, 33524.3, 33646.9"); + } + fall_power (energy_inslew_5__0) { + values ("34475.6, 34519.4, 34599.3, 34759.8, 35066.4"); + } + } + } + pin (i0) { + direction : input ; + capacitance : 462.28 ; + internal_power (energy_i0) { + rise_power (energy_inslew_5__0) { + values ("23714.2, 23732.3, 23764.5, 23826.0, 23954.1"); + } + fall_power (energy_inslew_5__0) { + values ("22071.3, 22113.3, 22196.5, 22351.2, 22654.5"); + } + } + } + pin (cmd1) { + direction : input ; + capacitance : 774.46 ; + internal_power (energy_cmd1) { + rise_power (energy_inslew_5__0) { + values ("55649.9, 55665.2, 55695.9, 55757.4, 55892.4"); + } + fall_power (energy_inslew_5__0) { + values ("56189.8, 56224.6, 56294.3, 56433.7, 56713.0"); + } + } + } + pin (cmd0) { + direction : input ; + capacitance : 771.51 ; + internal_power (energy_cmd0) { + rise_power (energy_inslew_5__0) { + values ("89764.2, 89779.5, 89810.2, 89872.0, 90015.4"); + } + fall_power (energy_inslew_5__0) { + values ("84175.2, 84210.0, 84279.7, 84419.1, 84699.1"); + } + } + } + pin (ck) { + direction : input ; + capacitance : 429.53 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("46981.8, 47004.7, 47050.4, 47142.0, 47327.4"); + } + fall_power (energy_inslew_5__0) { + values ("48946.8, 48990.9, 49079.1, 49255.5, 49608.2"); + } + } + } + pin (q) { + direction : output ; + capacitance : 582.68 ; + } + } + + cell (noa22_x4) { + area : 36.00 ; + cell_leakage_power : 7.6 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 6.4 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 9.2 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 6.3 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0))" ; + value : 9 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 6.1 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 8.5 ; + } + pin (i2) { + direction : input ; + capacitance : 439.56 ; + } + pin (i1) { + direction : input ; + capacitance : 434.46 ; + } + pin (i0) { + direction : input ; + capacitance : 432.96 ; + } + pin (nq) { + function : "((!(i0) & !(i2)) | (!(i2) & !(i1)))" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("13304.9, 13304.9, 13304.9, 13567.2, 14054.6", \ + "13319.4, 13319.4, 13319.4, 13581.7, 14069.1", \ + "13331.2, 13331.2, 13331.2, 13593.4, 14080.8", \ + "13356.6, 13356.6, 13356.6, 13618.7, 14106.1", \ + "13381.6, 13381.6, 13381.6, 13643.8, 14131.2"); + } + rise_transition (inslew_load_5x5__3) { + values ("3348.2, 3348.2, 3348.2, 3563.2, 3974.7", \ + "3353.3, 3353.3, 3353.3, 3567.9, 3979.6", \ + "3357.8, 3357.8, 3357.8, 3572.3, 3983.9", \ + "3365.1, 3365.1, 3365.1, 3579.4, 3990.9", \ + "3366.9, 3366.9, 3366.9, 3581.3, 3992.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("12525.1, 12525.1, 12525.1, 12736.1, 13148.7", \ + "12520.0, 12520.0, 12520.0, 12731.0, 13143.6", \ + "12509.7, 12509.7, 12509.7, 12720.7, 13133.3", \ + "12489.0, 12489.0, 12489.0, 12700.0, 13112.6", \ + "12448.6, 12448.6, 12448.6, 12659.6, 13072.2"); + } + fall_transition (inslew_load_5x5__3) { + values ("3177.9, 3177.9, 3177.9, 3331.6, 3653.3", \ + "3177.9, 3177.9, 3177.9, 3331.6, 3653.3", \ + "3177.9, 3177.9, 3177.9, 3331.6, 3653.3", \ + "3177.9, 3177.9, 3177.9, 3331.6, 3653.3", \ + "3178.4, 3178.4, 3178.4, 3332.1, 3653.7"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("12237.4, 12237.4, 12237.4, 12502.2, 12994.0", \ + "12252.9, 12252.9, 12252.9, 12517.7, 13009.2", \ + "12265.6, 12265.6, 12265.6, 12530.3, 13021.6", \ + "12291.3, 12291.3, 12291.3, 12556.0, 13046.9", \ + "12316.7, 12316.7, 12316.7, 12581.4, 13072.2"); + } + rise_transition (inslew_load_5x5__3) { + values ("3033.4, 3033.4, 3033.4, 3253.2, 3674.6", \ + "3038.9, 3038.9, 3038.9, 3258.6, 3679.8", \ + "3043.7, 3043.7, 3043.7, 3263.3, 3684.4", \ + "3051.0, 3051.0, 3051.0, 3270.5, 3691.4", \ + "3053.0, 3053.0, 3053.0, 3272.4, 3693.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("11231.5, 11231.5, 11231.5, 11442.6, 11874.4", \ + "11235.1, 11235.1, 11235.1, 11446.3, 11878.0", \ + "11242.8, 11242.8, 11242.8, 11453.9, 11885.7", \ + "11258.9, 11258.9, 11258.9, 11470.0, 11901.8", \ + "11292.0, 11292.0, 11292.0, 11503.1, 11934.8"); + } + fall_transition (inslew_load_5x5__3) { + values ("2974.8, 2974.8, 2974.8, 3137.1, 3459.8", \ + "2974.9, 2974.9, 2974.9, 3137.2, 3459.9", \ + "2975.0, 2975.0, 2975.0, 3137.3, 3460.0", \ + "2975.0, 2975.0, 2975.0, 3137.3, 3460.0", \ + "2975.2, 2975.2, 2975.2, 3137.5, 3460.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("16111.2, 16111.2, 16111.2, 16367.6, 16853.0", \ + "16105.8, 16105.8, 16105.8, 16362.2, 16847.6", \ + "16095.1, 16095.1, 16095.1, 16351.5, 16836.9", \ + "16073.5, 16073.5, 16073.5, 16329.9, 16815.3", \ + "16030.5, 16030.5, 16030.5, 16286.9, 16772.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("4150.3, 4150.3, 4150.3, 4353.8, 4752.3", \ + "4150.3, 4150.3, 4150.3, 4353.8, 4752.3", \ + "4150.3, 4150.3, 4150.3, 4353.8, 4752.3", \ + "4150.3, 4150.3, 4150.3, 4353.8, 4752.3", \ + "4150.3, 4150.3, 4150.3, 4353.8, 4752.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("10871.7, 10871.7, 10871.7, 11082.9, 11519.5", \ + "10880.5, 10880.5, 10880.5, 11091.7, 11528.3", \ + "10898.1, 10898.1, 10898.1, 11109.3, 11545.9", \ + "10933.3, 10933.3, 10933.3, 11144.5, 11581.1", \ + "11003.8, 11003.8, 11003.8, 11214.9, 11651.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("2955.8, 2955.8, 2955.8, 3119.0, 3441.4", \ + "2955.8, 2955.8, 2955.8, 3119.0, 3441.4", \ + "2955.8, 2955.8, 2955.8, 3119.0, 3441.4", \ + "2955.8, 2955.8, 2955.8, 3119.0, 3441.4", \ + "2956.1, 2956.1, 2956.1, 3119.3, 3441.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("58110.8, 58110.8, 58110.8, 60006.7, 63798.3", \ + "58188.8, 58188.8, 58188.8, 60084.6, 63876.3", \ + "58304.6, 58304.6, 58304.6, 60200.4, 63992.1", \ + "58525.0, 58525.0, 58525.0, 60420.8, 64212.5", \ + "58879.0, 58879.0, 58879.0, 60774.9, 64566.6"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("55942.5, 55942.5, 55942.5, 57838.3, 61630.0", \ + "61644.4, 61644.4, 61644.4, 61644.4, 61644.4", \ + "61673.1, 61673.1, 61673.1, 61673.1, 61673.1", \ + "61730.5, 61730.5, 61730.5, 61730.5, 61730.5", \ + "56162.2, 56162.2, 56162.2, 58058.1, 61849.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("54395.9, 54395.9, 54395.9, 56291.8, 60083.4", \ + "54472.9, 54472.9, 54472.9, 56368.7, 60160.4", \ + "54586.1, 54586.1, 54586.1, 56481.9, 60273.6", \ + "54798.6, 54798.6, 54798.6, 56694.4, 60486.1", \ + "55139.3, 55139.3, 55139.3, 57035.2, 60826.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("50852.7, 50852.7, 50852.7, 52748.5, 56540.2", \ + "50867.4, 50867.4, 50867.4, 52763.2, 56554.9", \ + "50892.0, 50892.0, 50892.0, 52787.8, 56579.5", \ + "56624.1, 56624.1, 56624.1, 56624.1, 56624.1", \ + "51030.3, 51030.3, 51030.3, 52926.1, 56717.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("68410.4, 68410.4, 68410.4, 70306.2, 74097.9", \ + "74142.0, 74142.0, 74142.0, 74142.0, 74142.0", \ + "74230.2, 74230.2, 74230.2, 74230.2, 74230.2", \ + "74406.5, 74406.5, 74406.5, 74406.5, 74406.5", \ + "74759.2, 74759.2, 74759.2, 74759.2, 74759.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("54910.1, 54910.1, 54910.1, 56805.9, 60597.6", \ + "60620.5, 60620.5, 60620.5, 60620.5, 60620.5", \ + "60666.3, 60666.3, 60666.3, 60666.3, 60666.3", \ + "60757.9, 60757.9, 60757.9, 60757.9, 60757.9", \ + "55262.5, 55262.5, 55262.5, 57158.3, 60950.0"); + } + } + } + } + + cell (halfadder_x2) { + area : 57.60 ; + cell_leakage_power : 10 ; + leakage_power () { + when : "(!(b) & a)" ; + value : 12 ; + } + leakage_power () { + when : "b" ; + value : 11 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 8.7 ; + } + pin (b) { + direction : input ; + capacitance : 1250.49 ; + } + pin (a) { + direction : input ; + capacitance : 1301.97 ; + } + pin (sout) { + function : "(b ^ a)" ; + direction : output ; + capacitance : 85.77 ; + timing (maxd_sout_a_positive_unate) { + related_pin : "a" ; + when : "!(b)" ; + sdf_cond : "!(b)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("6794.8, 6794.8, 6794.8, 7090.3, 7641.3", \ + "6792.3, 6792.3, 6792.3, 7087.8, 7638.8", \ + "6787.3, 6787.3, 6787.3, 7082.8, 7633.8", \ + "6777.2, 6777.2, 6777.2, 7072.8, 7623.7", \ + "6757.3, 6757.3, 6757.3, 7052.8, 7603.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("2995.6, 2995.6, 2995.6, 3241.7, 3713.7", \ + "2995.6, 2995.6, 2995.6, 3241.7, 3713.7", \ + "2995.6, 2995.6, 2995.6, 3241.7, 3713.7", \ + "2995.6, 2995.6, 2995.6, 3241.8, 3713.7", \ + "2995.9, 2995.9, 2995.9, 3242.0, 3714.0"); + } + cell_fall (inslew_load_5x5__0) { + values ("7554.1, 7554.1, 7554.1, 7707.9, 8171.0", \ + "7553.3, 7553.3, 7553.3, 7707.2, 8170.3", \ + "7567.7, 7567.7, 7567.7, 7721.5, 8185.2", \ + "7585.0, 7585.0, 7585.0, 7738.8, 8203.0", \ + "7608.2, 7608.2, 7608.2, 7762.0, 8226.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("3320.9, 3320.9, 3320.9, 3398.5, 3754.6", \ + "3322.5, 3322.5, 3322.5, 3399.9, 3756.0", \ + "3333.5, 3333.5, 3333.5, 3410.4, 3766.6", \ + "3345.0, 3345.0, 3345.0, 3421.3, 3777.8", \ + "3351.5, 3351.5, 3351.5, 3427.5, 3784.1"); + } + } + timing (maxd_sout_b_positive_unate) { + related_pin : "b" ; + when : "!(a)" ; + sdf_cond : "!(a)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("8876.1, 8876.1, 8876.1, 9161.6, 9700.7", \ + "8873.6, 8873.6, 8873.6, 9159.1, 9698.2", \ + "8868.6, 8868.6, 8868.6, 9154.1, 9693.2", \ + "8858.5, 8858.5, 8858.5, 9144.0, 9683.1", \ + "8838.5, 8838.5, 8838.5, 9124.0, 9663.1"); + } + rise_transition (inslew_load_5x5__0) { + values ("4423.4, 4423.4, 4423.4, 4650.5, 5095.6", \ + "4423.4, 4423.4, 4423.4, 4650.5, 5095.6", \ + "4423.4, 4423.4, 4423.4, 4650.5, 5095.6", \ + "4423.4, 4423.4, 4423.4, 4650.5, 5095.6", \ + "4423.4, 4423.4, 4423.4, 4650.5, 5095.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("10224.2, 10224.2, 10224.2, 10475.7, 10947.9", \ + "10218.8, 10218.8, 10218.8, 10470.3, 10942.5", \ + "10208.1, 10208.1, 10208.1, 10459.6, 10931.8", \ + "10186.6, 10186.6, 10186.6, 10438.1, 10910.3", \ + "10143.8, 10143.8, 10143.8, 10395.3, 10867.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("4864.3, 4864.3, 4864.3, 4986.7, 5266.8", \ + "4864.3, 4864.3, 4864.3, 4986.7, 5266.8", \ + "4864.3, 4864.3, 4864.3, 4986.7, 5266.8", \ + "4864.3, 4864.3, 4864.3, 4986.7, 5266.8", \ + "4864.3, 4864.3, 4864.3, 4986.7, 5266.8"); + } + } + timing (maxd_sout_a_negative_unate) { + related_pin : "a" ; + when : "b" ; + sdf_cond : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__0) { + values ("10823.8, 10823.8, 10823.8, 11113.5, 11652.6", \ + "10832.6, 10832.6, 10832.6, 11122.3, 11661.4", \ + "10850.2, 10850.2, 10850.2, 11139.9, 11679.0", \ + "10885.4, 10885.4, 10885.4, 11175.1, 11714.2", \ + "10955.4, 10955.4, 10955.4, 11245.1, 11784.2"); + } + rise_transition (inslew_load_5x5__0) { + values ("3717.8, 3717.8, 3717.8, 3953.4, 4407.2", \ + "3717.8, 3717.8, 3717.8, 3953.4, 4407.2", \ + "3717.8, 3717.8, 3717.8, 3953.4, 4407.2", \ + "3717.8, 3717.8, 3717.8, 3953.4, 4407.2", \ + "3718.5, 3718.5, 3718.5, 3954.1, 4407.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("11990.6, 11990.6, 11990.6, 12239.6, 12706.7", \ + "11999.4, 11999.4, 11999.4, 12248.4, 12715.5", \ + "12016.9, 12016.9, 12016.9, 12265.9, 12733.0", \ + "12052.1, 12052.1, 12052.1, 12301.1, 12768.2", \ + "12118.7, 12118.7, 12118.7, 12367.7, 12834.8"); + } + fall_transition (inslew_load_5x5__0) { + values ("4465.0, 4465.0, 4465.0, 4594.5, 4890.1", \ + "4465.0, 4465.0, 4465.0, 4594.5, 4890.1", \ + "4465.0, 4465.0, 4465.0, 4594.5, 4890.1", \ + "4465.0, 4465.0, 4465.0, 4594.5, 4890.1", \ + "4465.0, 4465.0, 4465.0, 4594.5, 4890.1"); + } + } + timing (maxd_sout_b_negative_unate) { + related_pin : "b" ; + when : "a" ; + sdf_cond : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__0) { + values ("9452.5, 9452.5, 9452.5, 9767.4, 10336.7", \ + "9461.3, 9461.3, 9461.3, 9776.2, 10345.5", \ + "9478.9, 9478.9, 9478.9, 9793.8, 10363.1", \ + "9514.1, 9514.1, 9514.1, 9829.0, 10398.3", \ + "9584.3, 9584.3, 9584.3, 9899.2, 10468.5"); + } + rise_transition (inslew_load_5x5__0) { + values ("2342.5, 2342.5, 2342.5, 2609.1, 3098.7", \ + "2342.5, 2342.5, 2342.5, 2609.1, 3098.7", \ + "2342.5, 2342.5, 2342.5, 2609.1, 3098.7", \ + "2342.5, 2342.5, 2342.5, 2609.1, 3098.7", \ + "2342.9, 2342.9, 2342.9, 2609.5, 3099.1"); + } + cell_fall (inslew_load_5x5__0) { + values ("9305.1, 9305.1, 9305.1, 9544.4, 10091.9", \ + "9313.9, 9313.9, 9313.9, 9553.2, 10100.7", \ + "9331.5, 9331.5, 9331.5, 9570.8, 10118.3", \ + "9366.7, 9366.7, 9366.7, 9606.0, 10153.5", \ + "9434.5, 9434.5, 9434.5, 9673.8, 10221.3"); + } + fall_transition (inslew_load_5x5__0) { + values ("2870.3, 2870.3, 2870.3, 3059.0, 3425.7", \ + "2870.3, 2870.3, 2870.3, 3059.0, 3425.7", \ + "2870.3, 2870.3, 2870.3, 3059.0, 3425.7", \ + "2870.3, 2870.3, 2870.3, 3059.0, 3425.7", \ + "2870.6, 2870.6, 2870.6, 3059.3, 3426.1"); + } + } + internal_power (energy_pos_sout_a) { + related_pin : "a" ; + when : "!(b)" ; + rise_power (energy_inslew_load_5x5__0) { + values ("26840.4, 26840.4, 26840.4, 27912.6, 30056.9", \ + "30073.4, 30073.4, 30073.4, 30073.4, 30073.4", \ + "30106.4, 30106.4, 30106.4, 30106.4, 30106.4", \ + "26956.0, 26956.0, 26956.0, 28028.2, 30172.5", \ + "27088.7, 27088.7, 27088.7, 28160.8, 30305.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("24774.8, 24774.8, 24774.8, 25846.9, 27991.3", \ + "24822.1, 24822.1, 24822.1, 25894.3, 28038.6", \ + "24940.2, 24940.2, 24940.2, 26012.3, 28156.7", \ + "25146.2, 25146.2, 25146.2, 26218.4, 28362.7", \ + "25510.7, 25510.7, 25510.7, 26582.9, 28727.2"); + } + } + internal_power (energy_pos_sout_b) { + related_pin : "b" ; + when : "!(a)" ; + rise_power (energy_inslew_load_5x5__0) { + values ("35676.7, 35676.7, 35676.7, 36748.9, 38893.2", \ + "38919.2, 38919.2, 38919.2, 38919.2, 38919.2", \ + "38971.1, 38971.1, 38971.1, 38971.1, 38971.1", \ + "39074.8, 39074.8, 39074.8, 39074.8, 39074.8", \ + "39282.4, 39282.4, 39282.4, 39282.4, 39282.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("36254.8, 36254.8, 36254.8, 37327.0, 39471.3", \ + "39515.6, 39515.6, 39515.6, 39515.6, 39515.6", \ + "39604.0, 39604.0, 39604.0, 39604.0, 39604.0", \ + "39781.0, 39781.0, 39781.0, 39781.0, 39781.0", \ + "40134.9, 40134.9, 40134.9, 40134.9, 40134.9"); + } + } + internal_power (energy_neg_sout_a) { + related_pin : "a" ; + when : "b" ; + rise_power (energy_inslew_load_5x5__0) { + values ("38808.8, 38808.8, 38808.8, 39881.0, 42025.3", \ + "42060.4, 42060.4, 42060.4, 42060.4, 42060.4", \ + "42130.5, 42130.5, 42130.5, 42130.5, 42130.5", \ + "42270.7, 42270.7, 42270.7, 42270.7, 42270.7", \ + "39340.3, 39340.3, 39340.3, 40412.5, 42556.8"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("41032.9, 41032.9, 41032.9, 42105.1, 44249.4", \ + "44277.0, 44277.0, 44277.0, 44277.0, 44277.0", \ + "44332.1, 44332.1, 44332.1, 44332.1, 44332.1", \ + "44442.4, 44442.4, 44442.4, 44442.4, 44442.4", \ + "44670.8, 44670.8, 44670.8, 44670.8, 44670.8"); + } + } + internal_power (energy_neg_sout_b) { + related_pin : "b" ; + when : "a" ; + rise_power (energy_inslew_load_5x5__0) { + values ("30019.0, 30019.0, 30019.0, 31091.2, 33235.5", \ + "33270.8, 33270.8, 33270.8, 33270.8, 33270.8", \ + "33341.3, 33341.3, 33341.3, 33341.3, 33341.3", \ + "33482.3, 33482.3, 33482.3, 33482.3, 33482.3", \ + "30549.7, 30549.7, 30549.7, 31621.8, 33766.2"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("29473.9, 29473.9, 29473.9, 30546.1, 32690.4", \ + "32708.7, 32708.7, 32708.7, 32708.7, 32708.7", \ + "32745.3, 32745.3, 32745.3, 32745.3, 32745.3", \ + "32818.8, 32818.8, 32818.8, 32818.8, 32818.8", \ + "29761.9, 29761.9, 29761.9, 30834.0, 32978.4"); + } + } + } + pin (cout) { + function : "(a & b)" ; + direction : output ; + capacitance : 85.77 ; + timing (maxd_cout_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("6113.2, 6113.2, 6113.2, 6412.4, 6978.5", \ + "6112.9, 6112.9, 6112.9, 6412.1, 6978.2", \ + "6112.4, 6112.4, 6112.4, 6411.6, 6977.7", \ + "6111.2, 6111.2, 6111.2, 6410.4, 6976.5", \ + "6109.3, 6109.3, 6109.3, 6408.5, 6974.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("2693.7, 2693.7, 2693.7, 2947.7, 3429.1", \ + "2693.7, 2693.7, 2693.7, 2947.7, 3429.1", \ + "2693.7, 2693.7, 2693.7, 2947.7, 3429.1", \ + "2693.7, 2693.7, 2693.7, 2947.7, 3429.1", \ + "2694.3, 2694.3, 2694.3, 2948.2, 3429.7"); + } + cell_fall (inslew_load_5x5__0) { + values ("5916.9, 5916.9, 5916.9, 6180.9, 6597.7", \ + "5925.7, 5925.7, 5925.7, 6189.7, 6606.5", \ + "5943.3, 5943.3, 5943.3, 6207.3, 6624.1", \ + "5978.5, 5978.5, 5978.5, 6242.5, 6659.3", \ + "6048.8, 6048.8, 6048.8, 6312.9, 6729.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("2081.5, 2081.5, 2081.5, 2235.7, 2525.3", \ + "2081.5, 2081.5, 2081.5, 2235.7, 2525.3", \ + "2081.5, 2081.5, 2081.5, 2235.7, 2525.3", \ + "2081.5, 2081.5, 2081.5, 2235.7, 2525.3", \ + "2081.7, 2081.7, 2081.7, 2235.8, 2525.3"); + } + } + timing (maxd_cout_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("4661.8, 4661.8, 4661.8, 4988.0, 5581.5", \ + "4670.0, 4670.0, 4670.0, 4996.1, 5589.2", \ + "4673.8, 4673.8, 4673.8, 4999.8, 5592.8", \ + "4683.6, 4683.6, 4683.6, 5009.6, 5602.7", \ + "4704.6, 4704.6, 4704.6, 5030.5, 5623.5"); + } + rise_transition (inslew_load_5x5__0) { + values ("1566.8, 1566.8, 1566.8, 1848.8, 2375.2", \ + "1574.5, 1574.5, 1574.5, 1856.4, 2382.3", \ + "1576.5, 1576.5, 1576.5, 1858.3, 2384.1", \ + "1577.4, 1577.4, 1577.4, 1859.2, 2385.0", \ + "1579.2, 1579.2, 1579.2, 1861.0, 2386.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("5408.2, 5408.2, 5408.2, 5648.3, 6146.7", \ + "5417.0, 5417.0, 5417.0, 5657.1, 6155.5", \ + "5434.6, 5434.6, 5434.6, 5674.7, 6173.1", \ + "5469.7, 5469.7, 5469.7, 5709.8, 6208.2", \ + "5540.1, 5540.1, 5540.1, 5780.2, 6278.6"); + } + fall_transition (inslew_load_5x5__0) { + values ("1637.8, 1637.8, 1637.8, 1832.7, 2210.2", \ + "1637.8, 1637.8, 1637.8, 1832.7, 2210.2", \ + "1637.8, 1637.8, 1637.8, 1832.7, 2210.2", \ + "1637.8, 1637.8, 1637.8, 1832.7, 2210.2", \ + "1637.9, 1637.9, 1637.9, 1832.8, 2210.3"); + } + } + internal_power (energy_pos_cout_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__0) { + values ("26183.0, 26183.0, 26183.0, 27255.2, 29399.5", \ + "29419.4, 29419.4, 29419.4, 29419.4, 29419.4", \ + "29459.0, 29459.0, 29459.0, 29459.0, 29459.0", \ + "29538.3, 29538.3, 29538.3, 29538.3, 29538.3", \ + "26481.9, 26481.9, 26481.9, 27554.1, 29698.4"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("21338.4, 21338.4, 21338.4, 22410.6, 24554.9", \ + "24598.7, 24598.7, 24598.7, 24598.7, 24598.7", \ + "24686.3, 24686.3, 24686.3, 24686.3, 24686.3", \ + "24861.6, 24861.6, 24861.6, 24861.6, 24861.6", \ + "21995.7, 21995.7, 21995.7, 23067.8, 25212.2"); + } + } + internal_power (energy_pos_cout_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__0) { + values ("20031.9, 20031.9, 20031.9, 21104.1, 23248.4", \ + "20067.8, 20067.8, 20067.8, 21140.0, 23284.3", \ + "20112.7, 20112.7, 20112.7, 21184.8, 23329.2", \ + "20196.6, 20196.6, 20196.6, 21268.8, 23413.1", \ + "20364.1, 20364.1, 20364.1, 21436.3, 23580.6"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("18079.9, 18079.9, 18079.9, 19152.0, 21296.4", \ + "21336.5, 21336.5, 21336.5, 21336.5, 21336.5", \ + "21416.9, 21416.9, 21416.9, 21416.9, 21416.9", \ + "21577.6, 21577.6, 21577.6, 21577.6, 21577.6", \ + "18682.6, 18682.6, 18682.6, 19754.8, 21899.1"); + } + } + } + } + + cell (fulladder_x2) { + area : 72.00 ; + cell_leakage_power : 9.7 ; + leakage_power () { + when : "((a1 & ((a2 & !(a3) & !(a4) & b1 & ((b2 & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b2) & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(a2) & !(a3) & !(a4) & b1 & b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(a1) & a2 & !(a3) & !(a4) & !(b1) & b2 & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))" ; + value : 9.3 ; + } + leakage_power () { + when : "((!(a1) & ((a2 & ((a3 & ((a4 & ((!(b1) & ((b3 & ((b4 & cin1 & !(cin2)) | (cin1 & !(cin2) & cin3))) | (!(b3) & b4 & cin1 & cin3))) | (b3 & b4 & cin1 & !(cin2) & cin3) | (!(b3) & b4 & cin1 & cin2 & cin3))) | (!(b1) & b3 & b4 & cin1 & !(cin2) & cin3))) | (!(a3) & a4 & ((!(b1) & ((b3 & b4 & cin1 & cin3) | (b4 & cin1 & cin2 & cin3))) | (b3 & b4 & cin1 & cin2 & cin3))))) | (a3 & a4 & b2 & ((b3 & b4 & cin1 & !(cin2) & cin3) | (!(b3) & b4 & cin1 & cin2 & cin3))) | (!(a3) & a4 & b2 & b3 & b4 & cin1 & cin2 & cin3))) | (a2 & ((a3 & a4 & ((!(b1) & ((b3 & b4 & cin1 & !(cin2) & cin3) | (!(b3) & b4 & cin1 & cin2 & cin3))) | (b2 & b3 & b4 & cin1 & !(cin2) & cin3))) | (!(a3) & a4 & !(b1) & b3 & b4 & cin1 & cin2 & cin3))) | (a3 & a4 & !(b1) & b2 & ((b3 & b4 & cin1 & !(cin2) & cin3) | (!(b3) & b4 & cin1 & cin2 & cin3))) | (!(a3) & a4 & !(b1) & b2 & b3 & b4 & cin1 & cin2 & cin3))" ; + value : 13 ; + } + leakage_power () { + when : "((a1 & ((a2 & ((a3 & !(a4) & b1 & ((b2 & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b2) & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(a3) & !(a4) & b1 & ((b2 & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))) | (!(b2) & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & !(b4) & cin1 & cin2 & !(cin3)))))))) | (!(a2) & ((a3 & !(a4) & b1 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(a3) & !(a4) & ((b1 & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & !(b4) & cin1 & cin2 & !(cin3)))) | (!(b1) & b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))))))) | (!(a1) & ((a2 & ((a3 & !(a4) & b1 & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a3) & !(a4) & b1 & !(b2) & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))))) | (!(a2) & ((a3 & !(a4) & b1 & (b2 ^ b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a3) & !(a4) & b1 & b2 & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & (cin1 ^ cin2) & !(cin3)))))))))" ; + value : 9.6 ; + } + leakage_power () { + when : "((a1 & !(a2) & !(a3) & !(a4) & b1 & !(b2) & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(a1) & ((a2 & !(a3) & !(a4) & b1 & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a2) & !(a3) & !(a4) & b1 & b2 & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))))" ; + value : 9.2 ; + } + leakage_power () { + when : "(!(cin3) & !(cin2) & !(cin1) & !(b4) & !(b3) & !(b2) & b1 & !(a4) & !(a3) & !(a2) & !(a1))" ; + value : 8.7 ; + } + leakage_power () { + when : "((a1 & ((a2 & !(a3) & !(a4) & b1 & b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(a2) & ((a3 & !(a4) & !(b1) & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a3) & !(a4) & !(b1) & !(b2) & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))))))) | (!(a1) & ((a2 & ((a3 & !(a4) & !(b1) & !(b2) & !(b3) & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(a3) & !(a4) & !(b1) & !(b2) & b3 & !(b4) & !(cin1) & cin2 & !(cin3)))) | (!(a2) & ((a3 & ((!(a4) & !(b1) & ((b2 & !(b3) & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(b2) & b3 & !(cin1) & cin2))) | (!(b1) & !(b2) & b3 & ((!(b4) & !(cin1) & cin2) | (!(cin1) & cin2 & !(cin3)))))) | (!(a3) & !(a4) & !(b1) & b2 & b3 & !(b4) & !(cin1) & cin2 & !(cin3)))))))" ; + value : 9.5 ; + } + leakage_power () { + when : "((a1 & ((a2 & ((a3 & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & ((cin1 & (cin2 | !(cin3))) | (!(cin1) & (!(cin2) | cin3)))) | (!(b4) & ((cin1 & (cin2 | cin3)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & (cin2 | cin3)) | (cin2 & cin3))))) | (!(b2) & ((b3 & ((b4 & ((cin1 & (!(cin2) | cin3)) | (!(cin2) & cin3))) | (cin1 & !(cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & cin2) | cin3)) | (cin1 & cin2 & cin3))))))) | (!(b1) & ((b2 & ((b3 & ((b4 & (!(cin1) | cin2 | !(cin3))) | (!(b4) & (!(cin1) | cin2 | cin3)))) | (!(b3) & ((b4 & (!(cin1) | !(cin2) | !(cin3))) | (!(b4) & (!(cin1) | cin3)))))) | (b3 & ((b4 & cin1 & (cin2 | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (!(cin2) & cin3))) | (!(b4) & (cin1 | !(cin2)) & cin3))))))) | (!(a4) & ((!(b1) & ((b2 & ((b3 & ((b4 & (!(cin1) | cin2 | cin3)) | (!(cin1) & (cin2 | cin3)) | cin2)) | (b4 & (!(cin1) | cin3)) | (!(cin1) & cin3))) | (b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))) | (!(b3) & ((b4 & cin1 & cin3) | (!(b4) & !(cin1) & !(cin2) & cin3))))) | (b2 & ((b3 & ((b4 & ((cin1 & (cin2 | cin3)) | (!(cin2) & cin3))) | (cin1 & cin2))) | (!(b3) & b4 & cin2 & cin3))) | (b3 & b4 & cin1 & !(cin2) & cin3) | (!(b3) & b4 & cin1 & cin2 & cin3))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & (cin2 | cin3)) | (cin2 & cin3))) | (b4 & cin3))) | (b3 & ((b4 & ((cin1 & cin2) | cin3)) | (cin1 & cin2 & cin3))) | (b4 & (cin1 | cin2) & cin3))) | (!(b1) & ((b2 & ((b3 & ((b4 & (!(cin1) | !(cin2) | !(cin3))) | (!(b4) & (!(cin1) | cin3)))) | (!(b3) & ((b4 & (!(cin1) | cin2 | cin3)) | !(cin1) | (cin2 & cin3))))) | (b3 & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (!(cin2) & cin3))) | (!(b4) & (cin1 | !(cin2)) & cin3))) | (!(b3) & ((b4 & (!((cin1 ^ cin2)) | cin3)) | (!(cin1) & (!(cin2) | cin3)) | (cin2 & cin3))))))) | (!(a4) & ((!(b1) & ((b2 & ((b3 & ((b4 & (!(cin1) | cin3)) | (!(cin1) & cin3))) | (b4 & (!(cin1) | (cin2 & cin3))) | (!(cin1) & cin3))) | (b3 & ((b4 & cin1 & cin3) | (!(b4) & !(cin1) & !(cin2) & cin3))) | (!(b3) & ((b4 & !((cin1 ^ cin2)) & cin3) | (!(b4) & !(cin1) & cin3))))) | (b2 & b3 & b4 & cin2 & cin3) | (b3 & b4 & cin1 & cin2 & cin3))))))) | (!(a2) & ((a3 & ((a4 & ((b1 & ((b3 & ((b4 & ((cin1 & (!(cin2) | cin3)) | (!(cin2) & cin3))) | (cin1 & !(cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & cin2) | cin3)) | (cin1 & cin2 & cin3))))) | (!(b1) & ((b2 & ((b3 & ((b4 & cin1 & (cin2 | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & ((cin1 & (cin2 ^ cin3)) | (!(cin2) & cin3))) | (!(b4) & !((cin1 ^ cin2)) & cin3))))) | (!(b2) & ((!(b3) & ((b4 & cin1 & (!(cin2) | cin3)) | (cin1 & !(cin2)))) | (b4 & cin1 & !(cin2) & cin3))))))) | (!(a4) & ((b1 & ((b3 & b4 & cin1 & !(cin2) & cin3) | (!(b3) & b4 & cin1 & cin2 & cin3))) | (!(b1) & ((b2 & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))) | (!(b3) & ((b4 & cin1 & cin2 & cin3) | (!(b4) & !(cin1) & !(cin2) & cin3))))) | (!(b2) & !(b3) & ((b4 & cin1 & !(cin2)) | (cin1 & !(cin2) & cin3))))))))) | (!(a3) & ((a4 & ((b1 & ((b3 & ((b4 & ((cin1 & cin2) | cin3)) | (cin1 & cin2 & cin3))) | (b4 & (cin1 | cin2) & cin3))) | (!(b1) & ((b2 & ((b3 & ((b4 & ((cin1 & (cin2 ^ cin3)) | (!(cin2) & cin3))) | (!(b4) & !((cin1 ^ cin2)) & cin3))) | (!(b3) & ((b4 & (!((cin1 | cin2)) | cin3)) | (!(cin1) & (!(cin2) | cin3)))))) | (!(b2) & ((!(b3) & cin1) | (b4 & cin1 & (!(cin2) | cin3)) | (cin1 & !(cin2)))))))) | (!(a4) & ((b1 & b3 & b4 & cin1 & cin2 & cin3) | (!(b1) & ((b2 & ((b3 & ((b4 & cin1 & cin2 & cin3) | (!(b4) & !(cin1) & !(cin2) & cin3))) | (!(b3) & ((!(b4) & !(cin1) & cin3) | (!(cin1) & !(cin2) & cin3))))) | (!(b2) & ((!(b3) & ((b4 & cin1) | (cin1 & cin3))) | (b4 & cin1 & !(cin2)) | (cin1 & !(cin2) & cin3))))))))))))) | (!(a1) & ((a2 & ((a3 & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & cin1 & (cin2 | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (!(cin2) & cin3))) | (!(b4) & (cin1 | !(cin2)) & cin3))))) | (b3 & ((b4 & cin1 & (cin2 | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & cin3))))) | (!(b1) & ((b3 & ((!(b4) & cin1 & (cin2 | !(cin3))) | (cin1 & cin2))) | (!(b3) & ((b4 & cin1 & !(cin3)) | (!(b4) & cin1 & (cin2 | cin3)))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))) | (!(b3) & ((b4 & cin1 & cin3) | (!(b4) & !(cin1) & !(cin2) & cin3))))) | (b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))) | (b4 & cin1 & cin3))) | (!(b1) & ((b3 & ((b4 & cin1 & (cin2 | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2 & cin3))))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (!(cin2) & cin3))) | (!(b4) & (cin1 | !(cin2)) & cin3))) | (!(b3) & ((b4 & (!((cin1 ^ cin2)) | cin3)) | (!(cin1) & (!(cin2) | cin3)) | (cin2 & cin3))))) | (b3 & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & cin3))) | (!(b3) & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2 & cin3))))) | (!(b1) & ((b3 & ((b4 & cin1 & !(cin3)) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & cin3))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & cin1 & cin3) | (!(b4) & !(cin1) & !(cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & cin2 & cin3) | (!(cin1) & !(cin2)))) | (!(b4) & !(cin1) & cin3))))) | (b3 & b4 & cin1 & cin3) | (b4 & cin1 & cin2 & cin3))) | (!(b1) & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2 & cin3))) | (b4 & cin1 & cin3))))))))) | (!(a2) & ((a3 & ((a4 & ((!(b1) & b2 & ((b3 & ((!(b4) & cin1) | (cin1 & (cin2 | !(cin3))))) | (!(b3) & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & cin3))))) | (b2 & ((b3 & ((b4 & cin1 & (cin2 | !(cin3))) | (!(b4) & cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & cin1 & (cin2 ^ cin3)) | (!(b4) & cin1 & cin2 & cin3))))))) | (!(a4) & ((!(b1) & b2 & ((b3 & ((b4 & cin1) | (cin1 & (cin2 | cin3)))) | (b4 & cin1 & cin3))) | (b2 & ((b3 & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2))) | (b4 & cin1 & cin2 & cin3))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & cin1 & (cin2 ^ cin3)) | (!(b4) & cin1 & cin2 & cin3))) | (!(b3) & b4 & cin1 & cin3))) | (!(b2) & !(b3) & cin1 & !(cin2) & cin3))) | (!(b1) & b2 & ((b3 & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & cin1 & cin3))) | (!(b3) & ((b4 & cin1 & (cin2 | cin3)) | (cin1 & cin2 & cin3))))))) | (!(a4) & ((b1 & ((b2 & b3 & b4 & cin1 & cin2 & cin3) | (!(b2) & !(b3) & !(b4) & cin1 & !(cin2) & cin3))) | (!(b1) & b2 & ((b3 & b4 & cin1 & cin3) | (b4 & cin1 & cin2 & cin3))))))))))))" ; + value : 12 ; + } + leakage_power () { + when : "((a1 & !(a2) & !(a3) & !(a4) & !(b1) & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a1) & ((a2 & ((a3 & !(a4) & !(b1) & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a3) & !(a4) & !(b1) & !(b2) & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))))) | (!(a2) & ((a3 & !(a4) & !(b1) & (b2 ^ b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a3) & !(a4) & !(b1) & b2 & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))))))))" ; + value : 9.1 ; + } + leakage_power () { + when : "(!(a1) & ((a2 & !(a3) & !(a4) & !(b1) & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a2) & !(a3) & !(a4) & !(b1) & b2 & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3))))" ; + value : 8.8 ; + } + leakage_power () { + when : "((a1 & ((a2 & !(a3) & !(a4) & !(b1) & !(b2) & !(b3) & !(b4) & !(cin2) & !(cin3)) | (!(a2) & !(a3) & !(a4) & !(b1) & b2 & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(a1) & ((a2 & ((a3 & !(a4) & !(b1) & (b2 ^ b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a3) & !(a4) & ((b1 & ((b2 & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b2) & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(b1) & b2 & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))))))) | (!(a2) & ((a3 & ((a4 & !(b1) & !(b2) & ((b3 & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(cin1) & cin2 & !(cin3)))) | (!(a4) & !(b1) & ((b2 & b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b2) & ((b3 & b4 & !(cin1) & !(cin2)) | (!(b3) & b4 & !(cin1) & cin2))))))) | (!(a3) & ((a4 & !(b1) & !(b2) & b3 & !(cin1) & cin2 & !(cin3)) | (!(a4) & !(b1) & !(b2) & b3 & b4 & !(cin1) & cin2))))))))" ; + value : 9.7 ; + } + leakage_power () { + when : "((a1 & ((a2 & ((a3 & !(a4) & b1 & ((b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b2) & !(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))) | (!(a3) & ((a4 & b1 & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a4) & ((b1 & ((b2 & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & !(b4) & cin1 & cin2 & !(cin3)))) | (!(b2) & ((b3 & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(b3) & ((b4 & !(cin1) & !(cin2) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & cin3))))))) | (!(b1) & b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))))))) | (!(a2) & ((a3 & !(a4) & b1 & !(b3) & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(a3) & ((a4 & b1 & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a4) & b1 & ((b3 & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(b3) & ((b4 & !(cin1) & !(cin2) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & cin3))))))))))) | (!(a1) & ((a2 & !(a3) & !(a4) & b1 & b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(a2) & ((a3 & ((a4 & !(b1) & !(b2) & ((b3 & ((b4 & !(cin1) & cin2 & cin3) | (!(b4) & !(cin1) & !(cin2) & cin3))) | (!(b3) & !(b4) & !(cin1) & cin2 & cin3))) | (!(a4) & ((b1 & !(b2) & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b1) & !(b2) & ((b3 & !(b4) & !(cin1) & !(cin2) & cin3) | (!(b3) & !(b4) & ((cin1 & cin2 & !(cin3)) | (!(cin1) & cin2 & cin3))))))))) | (!(a3) & ((!(a4) & ((b1 & !(b2) & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & !(b4) & cin1 & cin2 & !(cin3)))) | (!(b1) & ((b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b2) & b3 & !(b4) & ((cin1 & cin2 & !(cin3)) | (!(cin1) & cin2 & cin3))))))) | (!(b1) & !(b2) & b3 & !(b4) & !(cin1) & cin2 & cin3))))))))" ; + value : 9.8 ; + } + leakage_power () { + when : "((a1 & ((!(a2) & ((a3 & !(a4) & ((b1 & b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b1) & ((b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b2) & !(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))))) | (!(a3) & !(a4) & !(b1) & ((b2 & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & !(b4) & cin1 & cin2 & !(cin3)))) | (!(b2) & ((b3 & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))))))) | (a3 & !(a4) & b1 & !(b2) & b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(a1) & !(a2) & ((a3 & ((a4 & !(b1) & !(b2) & !(b3) & !(cin1) & !(cin2) & !(cin3)) | (!(a4) & ((b1 & b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b1) & !(b2) & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & b4 & !(cin1) & !(cin2)))))))) | (!(a3) & ((a4 & !(b1) & !(b2) & ((b3 & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(cin1) & cin2 & !(cin3)))) | (!(a4) & ((b1 & b2 & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & !(b4) & cin1 & cin2 & !(cin3)))) | (!(b1) & !(b2) & ((b3 & b4 & !(cin1) & !(cin2)) | (!(b3) & b4 & !(cin1) & cin2))))))))))" ; + value : 9.9 ; + } + leakage_power () { + when : "((a1 & ((!(a2) & ((a3 & !(a4) & b1 & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a3) & !(a4) & b1 & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))))) | (a3 & !(a4) & b1 & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a3) & !(a4) & b1 & !(b2) & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))))) | (!(a1) & !(a2) & ((a3 & !(a4) & ((b1 & !(b2) & !(b3) & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(b1) & !(b2) & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(a3) & !(a4) & ((b1 & !(b2) & ((b3 & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(b1) & !(b2) & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & !(b4) & cin1 & cin2 & !(cin3)))))))))" ; + value : 9.4 ; + } + leakage_power () { + when : "((a1 & ((a2 & ((a3 & ((a4 & ((b1 & ((b2 & ((b3 & ((!(b4) & ((!(cin1) & (cin2 | !(cin3))) | (!(cin2) & !(cin3)))) | (!(cin1) & cin2 & !(cin3)))) | (!(b3) & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))))))) | (!(b2) & ((b3 & ((!(b4) & (!(cin1) | cin2 | !(cin3))) | (!(cin1) & (cin2 | !(cin3))) | (cin2 & !(cin3)))) | (!(b3) & ((b4 & !((cin1 & cin2)) & !(cin3)) | (!(b4) & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))))))))) | (!(b1) & ((!(b2) & ((b3 & ((!(b4) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (!(b3) & ((!(b4) & (!((cin1 | !(cin2))) | !(cin3))) | (!(cin1) & (cin2 | !(cin3))))))) | (!(b3) & !(b4) & cin1 & !(cin3)) | (!(b4) & cin1 & !(cin2) & !(cin3)))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & ((!(cin1) & (cin2 | !(cin3))) | (!(cin2) & !(cin3)))) | (!(b4) & ((!(cin1) & (cin2 | cin3)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))) | (!(b4) & (cin1 | cin2) & cin3))))) | (!(b2) & ((b3 & ((b4 & (!(cin1) | cin2 | !(cin3))) | (!(b4) & (cin2 | cin3)))) | (!(b3) & ((b4 & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))) | (!(b4) & cin2 & cin3))))))) | (!(b1) & ((b2 & ((b3 & ((!(b4) & ((cin1 & !(cin2)) | (!(cin2) & !(cin3)))) | (cin1 & !(cin2) & !(cin3)))) | (!(b3) & ((b4 & cin1 & !(cin3)) | (!(b4) & ((cin1 & (cin2 | cin3)) | (!(cin1) & !(cin3)))))))) | (!(b2) & ((b3 & ((!(b4) & (!(cin1) | !(cin2))) | !(cin1) | (!(cin2) & !(cin3)))) | (!(b3) & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & (cin1 | cin2) & cin3))))))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))))) | (!(b3) & ((b4 & !(cin3)) | (!(b4) & ((cin1 & cin2) | cin3)))))) | (!(b2) & ((b3 & ((b4 & !((cin1 & cin2)) & !(cin3)) | (!(b4) & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))))) | (!(b3) & ((b4 & (!((cin1 | cin2)) | !(cin3))) | (!(b4) & cin3))))))) | (!(b1) & ((b2 & ((!(b3) & ((!(b4) & cin1 & (!(cin2) | !(cin3))) | (cin1 & !(cin2) & !(cin3)))) | (!(b4) & cin1 & !(cin3)))) | (!(b2) & ((b3 & ((!(b4) & (!((cin1 | !(cin2))) | !(cin3))) | (!(cin1) & (cin2 | !(cin3))))) | (!(b3) & ((b4 & (cin1 ^ cin2) & !(cin3)) | (!(b4) & ((cin1 & (cin2 ^ cin3)) | (cin2 & !(cin3)))))))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (cin2 ^ cin3))) | (!(b4) & (cin1 | cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & cin2) | cin3)) | (cin1 & cin2 & cin3))))) | (!(b2) & ((b3 & ((b4 & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))) | (!(b4) & cin2 & cin3))) | (!(b3) & b4 & cin3))))) | (!(b1) & ((b2 & ((b3 & ((b4 & cin1 & !(cin3)) | (!(b4) & ((cin1 & (cin2 | cin3)) | (!(cin1) & !(cin3)))))) | (!(b3) & ((b4 & cin1 & (!(cin2) | !(cin3))) | (!(b4) & ((cin1 & cin3) | (!(cin1) & cin2 & !(cin3)))))))) | (!(b2) & ((b3 & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & (cin1 | cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & (cin2 ^ cin3)) | (!(cin1) & (cin2 | !(cin3))))) | (!(b4) & cin1 & cin2 & cin3))))))))))))) | (!(a2) & ((a3 & ((a4 & ((b1 & ((b3 & ((!(b4) & (!(cin1) | cin2 | !(cin3))) | (!(cin1) & (cin2 | !(cin3))) | (cin2 & !(cin3)))) | (!(b3) & ((b4 & !((cin1 & cin2)) & !(cin3)) | (!(b4) & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))))))) | (!(b1) & ((b2 & ((b3 & ((!(b4) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (!(b3) & ((!(b4) & ((cin1 ^ cin2) | !(cin3))) | (!(cin1) & (cin2 | !(cin3))) | (!(cin2) & !(cin3)))))) | (!(b2) & ((b3 & ((b4 & ((cin1 & (cin2 | !(cin3))) | (!(cin1) & (!(cin2) | cin3)))) | (!(b4) & (cin1 | !(cin2))))) | (!(b3) & ((!(b4) & (!(cin1) | cin2)) | !(cin1) | (cin2 & !(cin3)))))))))) | (!(a4) & ((b1 & ((b3 & ((b4 & (!(cin1) | cin2 | !(cin3))) | (!(b4) & (cin2 | cin3)))) | (!(b3) & ((b4 & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))) | (!(b4) & cin2 & cin3))))) | (!(b1) & ((b2 & ((b3 & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & (!(cin1) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & (!(cin1) | !(cin2) | !(cin3))) | (!(b4) & (cin1 | cin2) & cin3))))) | (!(b2) & ((b3 & ((b4 & (cin1 | !(cin2))) | cin1 | (!(cin2) & cin3))) | (!(b3) & ((b4 & (!(cin1) | cin2)) | (cin1 & cin2) | (!(cin1) & cin3))))))))))) | (!(a3) & ((a4 & ((b1 & ((b3 & ((b4 & !((cin1 & cin2)) & !(cin3)) | (!(b4) & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))))) | (!(b3) & ((b4 & (!((cin1 | cin2)) | !(cin3))) | (!(b4) & cin3))))) | (!(b1) & ((b2 & ((b3 & ((!(b4) & ((cin1 ^ cin2) | !(cin3))) | (!(cin1) & (cin2 | !(cin3))) | (!(cin2) & !(cin3)))) | (!(b3) & ((b4 & (cin1 | cin2) & !(cin3)) | (!(b4) & ((cin1 & (cin2 | cin3)) | (cin2 & !(cin3)))))))) | (!(b2) & ((b3 & ((!(b4) & (!(cin1) | cin2)) | !(cin1) | (cin2 & !(cin3)))) | !(cin1))))))) | (!(a4) & ((b1 & ((b3 & ((b4 & ((!(cin1) & (cin2 | cin3)) | (cin2 ^ cin3))) | (!(b4) & cin2 & cin3))) | (!(b3) & b4 & cin3))) | (!(b1) & ((b2 & ((b3 & ((b4 & (!(cin1) | !(cin2) | !(cin3))) | (!(b4) & (cin1 | cin2) & cin3))) | (!(b3) & ((b4 & ((cin1 & (cin2 | cin3)) | (!(cin1) & (cin2 | !(cin3))))) | (cin1 & cin2 & cin3))))) | (!(b2) & ((b3 & ((b4 & (!(cin1) | cin2)) | (cin1 & cin2) | (!(cin1) & cin3))) | (b4 & !(cin1)) | (!(cin1) & cin3))))))))))))) | (!(a1) & ((a2 & ((a3 & ((a4 & ((b1 & ((!(b2) & ((!(b3) & ((!(b4) & (!(cin1) | !(cin3))) | !(cin1))) | (!(b4) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (b3 & ((!(b4) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (!(b3) & ((!(b4) & (!((cin1 | !(cin2))) | !(cin3))) | (!(cin1) & (cin2 | !(cin3))))))) | (!(b1) & ((b2 & ((!((b3 | b4)) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (!(b3) & ((b4 & !(cin1) & cin3) | (!(b4) & ((cin1 & !(cin2) & !(cin3)) | (!(cin1) & !(cin2) & cin3))))) | (b4 & !(cin1) & !(cin2) & cin3))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((!(b4) & (!(cin1) | !(cin2))) | !(cin1) | (!(cin2) & !(cin3)))) | (!(b3) & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & ((cin1 & (cin2 | cin3)) | cin2)))))) | (!(b2) & ((b3 & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & ((cin1 & !(cin2)) | (!(cin1) & (cin2 | cin3)))))) | (!(b3) & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & cin3))))))) | (!(b1) & ((b2 & ((b3 & ((b4 & !(cin1)) | (!(b4) & (cin1 ^ (cin2 | cin3))))) | (!(b3) & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (!(cin1) & cin3))))))) | (!(b3) & ((!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (!(cin2) & cin3))) | (cin1 & !(cin2) & !(cin3)))) | (!(b4) & cin1 & !(cin2) & !(cin3)))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & ((!(b4) & (!((cin1 | !(cin2))) | !(cin3))) | (!(cin1) & (cin2 | !(cin3))))) | (!(b3) & ((!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (cin2 & !(cin3)))) | ((cin1 ^ cin2) & !(cin3)))))) | (!(b2) & ((b3 & ((!(b4) & (!(cin1) | !(cin3))) | !(cin1))) | (!(b3) & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & (!(cin1) | (cin2 ^ cin3))))))))) | (!(b1) & ((b2 & ((!(b3) & ((!(b4) & (!(cin1) | !(cin3))) | !(cin1))) | (!(b4) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (!(b3) & ((!(b4) & ((cin1 & !(cin3)) | (!(cin1) & (!(cin2) | cin3)))) | (!(cin1) & (!(cin2) | cin3)))) | (b4 & !(cin1) & cin3) | (!(b4) & ((cin1 & !(cin2) & !(cin3)) | (!(cin1) & !(cin2) & cin3))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & ((cin1 & (cin2 | cin3)) | cin2)))) | (!(b3) & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | (!(cin1) & cin2))) | (!(b4) & cin1 & cin3))))) | (!(b2) & ((b3 & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & cin3))) | (!(b3) & ((b4 & (!(cin1) | (cin2 ^ cin3))) | (!(b4) & !((cin1 & !(cin2))) & cin3))))))) | (!(b1) & ((b2 & ((b3 & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (!(cin1) & cin3))))) | (!(b3) & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & ((cin1 & cin2) | cin3)))))) | (b3 & ((!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (!(cin2) & cin3))) | (cin1 & !(cin2) & !(cin3)))) | (!(b3) & ((b4 & ((cin1 & !(cin3)) | (!(cin1) & !(cin2)))) | (!(b4) & ((cin1 & cin2) | cin3)))))))))))) | (!(a2) & ((a3 & ((a4 & ((b1 & ((b2 & ((!(b3) & ((!(b4) & (!(cin1) | !(cin2) | !(cin3))) | !(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & (!(cin1) | (!(cin2) & !(cin3)))) | !(cin1))) | (!(b2) & ((!(b3) & (cin1 | (!(cin2) & cin3))) | cin1)))) | (b2 & ((!(b3) & ((b4 & !(cin1) & cin3) | (!(b4) & ((cin1 & !(cin3)) | (!(cin1) & !(cin2) & cin3))))) | (b4 & !(cin1) & !(cin2) & cin3))) | (!(b2) & ((!(b3) & ((b4 & cin1) | (cin1 & (!(cin2) | cin3)))) | (b4 & cin1 & (!(cin2) | cin3)) | (cin1 & !(cin2) & cin3))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & (!(cin1) | (!(cin2) & !(cin3)))) | (!(b4) & ((!(cin1) & (cin2 | cin3)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & (!(cin1) | !(cin2) | !(cin3))) | (!(b4) & cin3))))) | (!(b2) & ((b3 & ((b4 & cin1) | (cin1 & (cin2 | cin3)))) | (!(b3) & ((b4 & cin1) | (!(b4) & (cin1 | !(cin2)) & cin3))))))) | (!(b1) & ((b2 & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & ((b4 & cin1 & !(cin3)) | (!(b4) & ((cin1 & (cin2 | cin3)) | (!(cin2) & cin3))))))) | (!(b2) & ((!(b3) & ((b4 & cin1 & (!(cin2) | cin3)) | (cin1 & cin3))) | (cin1 & !(cin2) & cin3))))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((b3 & ((!(b4) & (!(cin1) | !(cin2) | !(cin3))) | !(cin1) | (!(cin2) & !(cin3)))) | (!(b3) & ((b4 & (!(cin1) | !(cin3))) | (!(b4) & (!(cin1) | cin2 | cin3)))))) | (!(b2) & ((b3 & (cin1 | (!(cin2) & cin3))) | (!(b3) & ((cin1 & (cin2 | !(cin3))) | (!(cin1) & (!(cin2) | cin3)))))))) | (!(b1) & ((b2 & ((!(b3) & ((!(b4) & ((cin1 & (!(cin2) | !(cin3))) | (!(cin1) & (!(cin2) | cin3)))) | (!(cin1) & (!(cin2) | cin3)) | (!(cin2) & !(cin3)))) | (b4 & !(cin1) & cin3) | (!(b4) & ((cin1 & !(cin3)) | (!(cin1) & !(cin2) & cin3))))) | (!(b2) & ((!((b3 & !(b4))) & cin1) | (cin1 & (!(cin2) | cin3)))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & (!(cin1) | !(cin2) | !(cin3))) | (!(b4) & cin3))) | (!(b3) & ((b4 & (!(cin1) | cin2 | cin3)) | (!((cin1 & !(cin2))) & cin3))))) | (!(b2) & ((b3 & ((b4 & cin1) | (!(b4) & (cin1 | !(cin2)) & cin3))) | (!(b3) & ((b4 & (cin1 | (!(cin2) & cin3))) | (!(b4) & !((cin1 & !(cin2))) & cin3))))))) | (!(b1) & ((b2 & ((b3 & ((b4 & cin1 & !(cin3)) | (!(b4) & ((cin1 & (cin2 | cin3)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & ((cin1 & (!(cin2) | !(cin3))) | !(cin2))) | (!(b4) & cin3))))) | (!(b2) & ((!(b3) & ((b4 & cin1) | (cin1 & cin3))) | (b4 & cin1 & (!(cin2) | cin3)) | (cin1 & cin3))))))))))))))" ; + value : 11 ; + } + leakage_power () { + when : "((a1 & ((!(a2) & !(a3) & !(a4) & b1 & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a3) & !(a4) & b1 & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(a1) & !(a2) & ((a3 & !(a4) & ((b1 & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b1) & !(b2) & !(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))) | (!(a3) & !(a4) & ((b1 & !(b2) & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))) | (!(b1) & !(b2) & ((b3 & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))))))))" ; + value : 9 ; + } + leakage_power () { + when : "(!(a1) & !(a2) & ((a3 & !(a4) & !(b1) & !(b2) & !(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(a3) & !(a4) & !(b1) & !(b2) & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3))))))" ; + value : 8.6 ; + } + leakage_power () { + when : "((a1 & ((a2 & ((a3 & ((a4 & b1 & ((!(b2) & !(b3) & !(b4) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(a4) & ((b1 & ((b2 & ((b3 & !(b4) & !(cin2) & !(cin3)) | (!(b3) & ((b4 & !(cin1) & !(cin2) & !(cin3)) | (!(b4) & ((!(cin1) & (cin2 ^ cin3)) | (cin2 & !(cin3)))))))) | (!(b2) & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & (cin2 ^ cin3)) | (!(cin2) & cin3))))))))) | (!(b1) & ((!(b2) & !(b3) & !(b4) & !(cin3)) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & ((!(b3) & !(b4) & !((cin1 & cin2)) & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & !(cin3)))) | (!(b2) & ((b3 & !(b4) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & (cin1 | cin2) & !(cin3)))))) | (!(b2) & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(a4) & ((b1 & ((b2 & ((b3 & ((b4 & !(cin1) & !(cin2) & !(cin3)) | (!(b4) & ((!(cin1) & (cin2 ^ cin3)) | (cin2 & !(cin3)))))) | (!(b3) & ((b4 & !((cin1 & cin2)) & !(cin3)) | (!(b4) & !((cin1 & cin2)) & cin3))))) | (!(b2) & ((b3 & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & (cin2 ^ cin3)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & (cin1 | cin2) & !(cin3)) | (!(b4) & (cin1 | cin2) & cin3))))))) | (!(b1) & ((b2 & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !((cin1 ^ cin2)) & !(cin3)))) | (!(b2) & ((b3 & !(b4) & !(cin3)) | (!(b3) & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & (cin2 ^ cin3)) | (cin2 & !(cin3)))))))))))))))) | (!(a2) & ((a3 & ((a4 & ((b1 & !(b3) & !(b4) & !(cin2) & !(cin3)) | (!(b1) & !(b2) & b3 & ((!(b4) & !(cin1) & cin2) | (!(cin1) & cin2 & !(cin3)))))) | (!(a4) & ((b1 & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & (cin2 ^ cin3)) | (!(cin2) & cin3))))))) | (!(b1) & ((b2 & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !((cin1 & !(cin2))) & !(cin3)))) | (!(b2) & ((b3 & ((!(b4) & !(cin1) & (cin2 | !(cin3))) | (!(cin1) & cin2))) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))))))))) | (!(a3) & ((a4 & ((b1 & ((b3 & !(b4) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & (cin1 | cin2) & !(cin3)))) | (b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(a4) & ((b1 & ((b3 & ((b4 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & (cin2 ^ cin3)) | (!(cin2) & cin3))))) | (!(b3) & ((b4 & (cin1 | cin2) & !(cin3)) | (!(b4) & (cin1 | cin2) & cin3))))) | (!(b1) & ((b2 & ((b3 & !(b4) & !((cin1 & !(cin2))) & !(cin3)) | (!(b3) & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & ((cin1 & !(cin2) & cin3) | (!(cin1) & cin2 & !(cin3)))))))) | (!(b2) & ((b3 & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b3) & !(b4) & cin1 & cin2 & !(cin3)))))))))))))) | (!(a1) & ((a2 & ((a3 & ((a4 & !(b1) & !(b2) & ((b3 & ((!(b4) & !(cin1)) | (!(cin1) & (cin2 | !(cin3))))) | (!(b4) & !(cin1) & (cin2 | !(cin3))) | (!(cin1) & !(cin3)))) | (!(a4) & ((b1 & ((b2 & !(b3) & !(b4) & !(cin2) & !(cin3)) | (!(b2) & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & (cin1 | cin2) & !(cin3)))))) | (!(b1) & ((b2 & ((b3 & !(b4) & !(cin1) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & !(cin1) & cin2 & !(cin3)))) | (!(b2) & ((b3 & ((b4 & !(cin1)) | (!(cin1) & (cin2 | cin3)))) | (b4 & !(cin1)) | (!(cin1) & cin2 & cin3))))))))) | (!(a3) & ((a4 & ((b1 & !(b2) & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b1) & !(b2) & ((b3 & ((!(b4) & !(cin1) & (cin2 | !(cin3))) | (!(cin1) & !(cin3)))) | (!(cin1) & cin2 & !(cin3)))))) | (!(a4) & ((b1 & ((b2 & ((b3 & !(b4) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & cin2 & !(cin3)))) | (!(b2) & ((b3 & !(b4) & (cin1 | cin2) & !(cin3)) | (!(b3) & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & cin1 & (cin2 ^ cin3)))))))) | (!(b1) & ((b2 & ((b3 & !(b4) & !(cin1) & cin2 & !(cin3)) | (!(b3) & !(b4) & cin1 & !(cin2) & !(cin3)))) | (!(b2) & ((b3 & ((b4 & !(cin1)) | (!(cin1) & cin2 & cin3))) | (!(b3) & ((b4 & !(cin1) & cin2) | (!(b4) & cin1 & !(cin2) & !(cin3)))))))))))))) | (!(a2) & ((a3 & ((a4 & ((b1 & !(b2) & ((b3 & !(cin1)) | (!(cin1) & (cin2 | !(cin3))))) | (!(b1) & ((b2 & ((b3 & ((!(b4) & !(cin1)) | (!(cin1) & (cin2 | !(cin3))))) | (!(b4) & !(cin1) & (cin2 | !(cin3))) | (!(cin1) & !(cin3)))) | (!(b2) & ((b3 & ((b4 & ((cin1 & cin2 & !(cin3)) | (!(cin1) & !(cin2) & cin3))) | (!(b4) & cin1 & (cin2 | !(cin3))))) | (!(b3) & ((b4 & !(cin1) & cin3) | (!(b4) & ((cin1 & cin2 & !(cin3)) | (!(cin1) & !(cin2) & cin3))))))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & !(b4) & !(cin2) & !(cin3)) | (!(b3) & !(b4) & cin2 & !(cin3)))) | (!(b2) & ((b3 & ((b4 & !(cin1)) | (!(b4) & (cin1 ^ (cin2 | cin3))))) | (!(b3) & ((b4 & !(cin1)) | (!(b4) & ((cin1 & cin2 & !(cin3)) | (!(cin1) & cin2 & cin3))))))))) | (!(b1) & ((b2 & ((b3 & ((b4 & !(cin1)) | (!(cin1) & (cin2 | cin3)))) | (!(b3) & ((b4 & !(cin1)) | (!(b4) & ((cin1 & !(cin2) & !(cin3)) | (!(cin1) & cin2 & cin3))))))) | (!(b2) & ((b3 & ((b4 & cin1 & (cin2 | !(cin3))) | (cin1 & cin2))) | (!(b3) & ((b4 & cin1 & cin2 & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & cin3))))))))))) | (!(a3) & ((a4 & ((b1 & ((b2 & !(b3) & !(b4) & cin1 & !(cin2) & !(cin3)) | (!(b2) & ((b3 & !(cin1) & (cin2 | !(cin3))) | (!(cin1) & cin2 & !(cin3)))))) | (!(b1) & ((b2 & ((b3 & ((!(b4) & !(cin1) & (cin2 | !(cin3))) | (!(cin1) & !(cin3)))) | (!(cin1) & cin2 & !(cin3)))) | (!(b2) & ((b3 & ((b4 & !(cin1) & cin3) | (!(b4) & ((cin1 & cin2 & !(cin3)) | (!(cin1) & !(cin2) & cin3))))) | (!(b3) & !(cin1) & (!(cin2) | cin3)))))))) | (!(a4) & ((b1 & ((b2 & ((b3 & !(b4) & cin2 & !(cin3)) | (!(b3) & ((b4 & cin1 & !(cin2) & !(cin3)) | (!(b4) & cin1 & !(cin2) & cin3))))) | (!(b2) & ((b3 & ((b4 & !(cin1)) | (!(b4) & ((cin1 & cin2 & !(cin3)) | (!(cin1) & cin2 & cin3))))) | (b4 & !(cin1) & (cin2 | !(cin3))))))) | (!(b1) & ((b2 & ((b3 & ((b4 & !(cin1)) | (!(b4) & ((cin1 & !(cin2) & !(cin3)) | (!(cin1) & cin2 & cin3))))) | (!(b3) & ((b4 & !(cin1) & cin2) | (!(b4) & cin1 & cin2 & !(cin3)))))) | (!(b2) & ((b3 & ((b4 & cin1 & cin2 & !(cin3)) | (!(b4) & !(cin1) & !(cin2) & cin3))) | (!(b3) & ((b4 & !(cin1) & !(cin2)) | (!(b4) & !(cin1) & cin3))))))))))))))))" ; + value : 10 ; + } + leakage_power () { + when : "(!(cin3) & !(cin2) & !(cin1) & !(b4) & !(b3) & !(b2) & !(b1) & !(a4) & !(a3) & !(a2) & !(a1))" ; + value : 8.2 ; + } + pin (cin3) { + direction : input ; + capacitance : 320.01 ; + } + pin (cin2) { + direction : input ; + capacitance : 320.61 ; + } + pin (cin1) { + direction : input ; + capacitance : 379.19 ; + } + pin (b4) { + direction : input ; + capacitance : 321.96 ; + } + pin (b3) { + direction : input ; + capacitance : 320.61 ; + } + pin (b2) { + direction : input ; + capacitance : 486.14 ; + } + pin (b1) { + direction : input ; + capacitance : 434.11 ; + } + pin (a4) { + direction : input ; + capacitance : 322.56 ; + } + pin (a3) { + direction : input ; + capacitance : 320.01 ; + } + pin (a2) { + direction : input ; + capacitance : 487.04 ; + } + pin (a1) { + direction : input ; + capacitance : 407.22 ; + } + pin (sout) { + function : "(((b4 | a4 | cin3) & ((cin2 & b3 & a3) | (!((b2 | a2)) & (!(a1) | !(b1))) | (!((a1 & b1)) & !(cin1)))) | (cin2 & b3 & a3))" ; + direction : output ; + capacitance : 82.41 ; + timing (maxd_sout_a3_positive_unate) { + related_pin : "a3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__25) { + values ("15962.3, 15962.3, 15962.3, 16221.4, 16726.5", \ + "15951.2, 15951.2, 15951.2, 16210.3, 16715.4", \ + "15929.1, 15929.1, 15929.1, 16188.2, 16693.3", \ + "15884.8, 15884.8, 15884.8, 16143.9, 16649.0", \ + "15796.1, 15796.1, 15796.1, 16055.2, 16560.3"); + } + rise_transition (inslew_load_5x5__25) { + values ("9453.9, 9453.9, 9453.9, 9661.9, 10074.3", \ + "9453.9, 9453.9, 9453.9, 9661.9, 10074.3", \ + "9453.9, 9453.9, 9453.9, 9661.9, 10074.3", \ + "9453.9, 9453.9, 9453.9, 9661.9, 10074.3", \ + "9453.9, 9453.9, 9453.9, 9661.9, 10074.3"); + } + cell_fall (inslew_load_5x5__25) { + values ("27408.9, 27408.9, 27408.9, 27635.9, 28085.8", \ + "27394.1, 27394.1, 27394.1, 27621.1, 28071.0", \ + "27364.6, 27364.6, 27364.6, 27591.6, 28041.5", \ + "27305.5, 27305.5, 27305.5, 27532.5, 27982.4", \ + "27187.3, 27187.3, 27187.3, 27414.3, 27864.2"); + } + fall_transition (inslew_load_5x5__25) { + values ("16974.9, 16974.9, 16974.9, 17126.8, 17447.2", \ + "16974.9, 16974.9, 16974.9, 17126.8, 17447.2", \ + "16974.9, 16974.9, 16974.9, 17126.8, 17447.2", \ + "16974.9, 16974.9, 16974.9, 17126.8, 17447.2", \ + "16974.9, 16974.9, 16974.9, 17126.8, 17447.2"); + } + } + timing (maxd_sout_a4_positive_unate) { + related_pin : "a4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__25) { + values ("8469.3, 8469.3, 8469.3, 8745.2, 9266.1", \ + "8467.4, 8467.4, 8467.4, 8743.3, 9264.2", \ + "8463.6, 8463.6, 8463.6, 8739.5, 9260.4", \ + "8456.0, 8456.0, 8456.0, 8731.9, 9252.8", \ + "8440.7, 8440.7, 8440.7, 8716.7, 9237.6"); + } + rise_transition (inslew_load_5x5__25) { + values ("4284.8, 4284.8, 4284.8, 4504.6, 4934.1", \ + "4284.8, 4284.8, 4284.8, 4504.6, 4934.1", \ + "4284.8, 4284.8, 4284.8, 4504.6, 4934.1", \ + "4284.8, 4284.8, 4284.8, 4504.6, 4934.1", \ + "4284.8, 4284.8, 4284.8, 4504.6, 4934.1"); + } + cell_fall (inslew_load_5x5__25) { + values ("19618.9, 19618.9, 19618.9, 19845.3, 20270.0", \ + "19627.0, 19627.0, 19627.0, 19853.4, 20278.1", \ + "19633.5, 19633.5, 19633.5, 19859.9, 20284.8", \ + "19613.9, 19613.9, 19613.9, 19840.3, 20265.4", \ + "19598.9, 19598.9, 19598.9, 19825.3, 20250.7"); + } + fall_transition (inslew_load_5x5__25) { + values ("11949.1, 11949.1, 11949.1, 12110.1, 12416.8", \ + "11962.9, 11962.9, 11962.9, 12123.7, 12430.7", \ + "11982.8, 11982.8, 11982.8, 12144.1, 12450.9", \ + "11997.2, 11997.2, 11997.2, 12158.3, 12465.1", \ + "12031.7, 12031.7, 12031.7, 12192.5, 12500.1"); + } + } + timing (maxd_sout_b3_positive_unate) { + related_pin : "b3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__25) { + values ("14539.2, 14539.2, 14539.2, 14798.5, 15302.0", \ + "14537.0, 14537.0, 14537.0, 14796.3, 15299.8", \ + "14527.8, 14527.8, 14527.8, 14787.1, 15290.6", \ + "14511.4, 14511.4, 14511.4, 14770.7, 15274.2", \ + "14479.3, 14479.3, 14479.3, 14738.6, 15242.1"); + } + rise_transition (inslew_load_5x5__25) { + values ("8538.2, 8538.2, 8538.2, 8748.3, 9160.1", \ + "8541.1, 8541.1, 8541.1, 8751.1, 9163.0", \ + "8541.6, 8541.6, 8541.6, 8751.6, 9163.5", \ + "8541.7, 8541.7, 8541.7, 8751.7, 9163.6", \ + "8541.6, 8541.6, 8541.6, 8751.6, 9163.5"); + } + cell_fall (inslew_load_5x5__25) { + values ("26558.1, 26558.1, 26558.1, 26785.1, 27232.9", \ + "26543.4, 26543.4, 26543.4, 26770.4, 27218.2", \ + "26513.8, 26513.8, 26513.8, 26740.8, 27188.6", \ + "26454.7, 26454.7, 26454.7, 26681.7, 27129.5", \ + "26336.6, 26336.6, 26336.6, 26563.6, 27011.4"); + } + fall_transition (inslew_load_5x5__25) { + values ("16399.4, 16399.4, 16399.4, 16552.2, 16874.3", \ + "16399.4, 16399.4, 16399.4, 16552.2, 16874.3", \ + "16399.4, 16399.4, 16399.4, 16552.2, 16874.3", \ + "16399.4, 16399.4, 16399.4, 16552.2, 16874.3", \ + "16399.4, 16399.4, 16399.4, 16552.2, 16874.3"); + } + } + timing (maxd_sout_b4_positive_unate) { + related_pin : "b4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__25) { + values ("8783.6, 8783.6, 8783.6, 9058.5, 9578.9", \ + "8781.7, 8781.7, 8781.7, 9056.6, 9577.0", \ + "8777.8, 8777.8, 8777.8, 9052.7, 9573.1", \ + "8770.2, 8770.2, 8770.2, 9045.1, 9565.5", \ + "8755.0, 8755.0, 8755.0, 9030.0, 9550.3"); + } + rise_transition (inslew_load_5x5__25) { + values ("4498.6, 4498.6, 4498.6, 4716.0, 5143.2", \ + "4498.6, 4498.6, 4498.6, 4716.0, 5143.2", \ + "4498.6, 4498.6, 4498.6, 4716.0, 5143.2", \ + "4498.6, 4498.6, 4498.6, 4716.0, 5143.2", \ + "4498.6, 4498.6, 4498.6, 4716.0, 5143.3"); + } + cell_fall (inslew_load_5x5__25) { + values ("23136.7, 23136.7, 23136.7, 23363.0, 23807.4", \ + "23129.6, 23129.6, 23129.6, 23355.8, 23800.4", \ + "23104.0, 23104.0, 23104.0, 23330.3, 23774.8", \ + "23069.5, 23069.5, 23069.5, 23295.8, 23740.4", \ + "22996.5, 22996.5, 22996.5, 23222.8, 23667.6"); + } + fall_transition (inslew_load_5x5__25) { + values ("14216.9, 14216.9, 14216.9, 14373.2, 14699.0", \ + "14221.5, 14221.5, 14221.5, 14377.8, 14703.6", \ + "14221.9, 14221.9, 14221.9, 14378.2, 14704.2", \ + "14232.3, 14232.3, 14232.3, 14388.6, 14714.6", \ + "14244.0, 14244.0, 14244.0, 14400.3, 14726.2"); + } + } + timing (maxd_sout_cin2_positive_unate) { + related_pin : "cin2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__25) { + values ("13155.5, 13155.5, 13155.5, 13415.3, 13916.1", \ + "13165.4, 13165.4, 13165.4, 13425.2, 13926.0", \ + "13189.7, 13189.7, 13189.7, 13449.4, 13950.4", \ + "13199.9, 13199.9, 13199.9, 13459.7, 13960.7", \ + "13220.2, 13220.2, 13220.2, 13479.9, 13980.9"); + } + rise_transition (inslew_load_5x5__25) { + values ("7649.9, 7649.9, 7649.9, 7859.7, 8272.1", \ + "7660.2, 7660.2, 7660.2, 7870.1, 8282.4", \ + "7680.5, 7680.5, 7680.5, 7890.5, 8302.7", \ + "7686.8, 7686.8, 7686.8, 7896.7, 8308.9", \ + "7687.5, 7687.5, 7687.5, 7897.4, 8309.7"); + } + cell_fall (inslew_load_5x5__25) { + values ("25344.0, 25344.0, 25344.0, 25571.0, 26018.8", \ + "25329.3, 25329.3, 25329.3, 25556.3, 26004.1", \ + "25299.7, 25299.7, 25299.7, 25526.7, 25974.5", \ + "25240.6, 25240.6, 25240.6, 25467.6, 25915.4", \ + "25122.5, 25122.5, 25122.5, 25349.5, 25797.3"); + } + fall_transition (inslew_load_5x5__25) { + values ("15578.7, 15578.7, 15578.7, 15732.4, 16057.3", \ + "15578.7, 15578.7, 15578.7, 15732.4, 16057.3", \ + "15578.7, 15578.7, 15578.7, 15732.4, 16057.3", \ + "15578.7, 15578.7, 15578.7, 15732.4, 16057.3", \ + "15578.7, 15578.7, 15578.7, 15732.4, 16057.3"); + } + } + timing (maxd_sout_cin3_positive_unate) { + related_pin : "cin3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__25) { + values ("7612.3, 7612.3, 7612.3, 7891.8, 8413.3", \ + "7610.4, 7610.4, 7610.4, 7889.9, 8411.4", \ + "7606.5, 7606.5, 7606.5, 7886.0, 8407.5", \ + "7598.9, 7598.9, 7598.9, 7878.4, 8399.9", \ + "7583.7, 7583.7, 7583.7, 7863.3, 8384.7"); + } + rise_transition (inslew_load_5x5__25) { + values ("3698.2, 3698.2, 3698.2, 3925.2, 4362.2", \ + "3698.2, 3698.2, 3698.2, 3925.2, 4362.2", \ + "3698.2, 3698.2, 3698.2, 3925.2, 4362.2", \ + "3698.2, 3698.2, 3698.2, 3925.2, 4362.2", \ + "3698.4, 3698.4, 3698.4, 3925.3, 4362.4"); + } + cell_fall (inslew_load_5x5__25) { + values ("15855.6, 15855.6, 15855.6, 16089.8, 16556.3", \ + "15812.7, 15812.7, 15812.7, 16047.0, 16513.5", \ + "15863.3, 15863.3, 15863.3, 16097.5, 16564.0", \ + "15927.0, 15927.0, 15927.0, 16161.1, 16627.6", \ + "15956.3, 15956.3, 15956.3, 16190.4, 16656.8"); + } + fall_transition (inslew_load_5x5__25) { + values ("9509.2, 9509.2, 9509.2, 9697.6, 10045.0", \ + "9486.4, 9486.4, 9486.4, 9674.9, 10022.3", \ + "9534.9, 9534.9, 9534.9, 9723.3, 10070.8", \ + "9602.7, 9602.7, 9602.7, 9790.7, 10138.5", \ + "9658.4, 9658.4, 9658.4, 9846.2, 10194.2"); + } + } + timing (maxd_sout_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("27489.6, 27489.6, 27489.6, 27749.1, 28252.2", \ + "27483.1, 27483.1, 27483.1, 27742.6, 28245.7", \ + "27470.3, 27470.3, 27470.3, 27729.8, 28232.9", \ + "27444.6, 27444.6, 27444.6, 27704.1, 28207.2", \ + "27393.2, 27393.2, 27393.2, 27652.7, 28155.8"); + } + rise_transition (inslew_load_5x5__25) { + values ("8347.5, 8347.5, 8347.5, 8558.0, 8969.8", \ + "8347.5, 8347.5, 8347.5, 8558.0, 8969.8", \ + "8347.5, 8347.5, 8347.5, 8558.0, 8969.8", \ + "8347.5, 8347.5, 8347.5, 8558.0, 8969.8", \ + "8347.5, 8347.5, 8347.5, 8558.0, 8969.8"); + } + cell_fall (inslew_load_5x5__25) { + values ("18944.9, 18944.9, 18944.9, 19351.9, 19818.7", \ + "18942.4, 18942.4, 18942.4, 19349.4, 19816.2", \ + "18937.3, 18937.3, 18937.3, 19344.3, 19811.1", \ + "18927.3, 18927.3, 18927.3, 19334.3, 19801.1", \ + "18907.2, 18907.2, 18907.2, 19314.2, 19781.0"); + } + fall_transition (inslew_load_5x5__25) { + values ("5743.9, 5743.9, 5743.9, 5940.2, 6176.2", \ + "5743.9, 5743.9, 5743.9, 5940.2, 6176.2", \ + "5743.9, 5743.9, 5743.9, 5940.2, 6176.2", \ + "5743.9, 5743.9, 5743.9, 5940.2, 6176.2", \ + "5743.9, 5743.9, 5743.9, 5940.2, 6176.2"); + } + } + timing (maxd_sout_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("19984.1, 19984.1, 19984.1, 20243.6, 20739.4", \ + "20012.2, 20012.2, 20012.2, 20271.8, 20767.5", \ + "20049.0, 20049.0, 20049.0, 20308.6, 20804.4", \ + "20059.9, 20059.9, 20059.9, 20319.6, 20815.3", \ + "20110.0, 20110.0, 20110.0, 20369.7, 20865.5"); + } + rise_transition (inslew_load_5x5__25) { + values ("6046.7, 6046.7, 6046.7, 6257.7, 6677.4", \ + "6058.4, 6058.4, 6058.4, 6269.4, 6688.9", \ + "6075.5, 6075.5, 6075.5, 6286.5, 6705.8", \ + "6088.0, 6088.0, 6088.0, 6298.9, 6718.2", \ + "6115.7, 6115.7, 6115.7, 6326.6, 6745.5"); + } + cell_fall (inslew_load_5x5__25) { + values ("19535.9, 19535.9, 19535.9, 19937.8, 20404.1", \ + "19530.7, 19530.7, 19530.7, 19932.6, 20398.9", \ + "19520.4, 19520.4, 19520.4, 19922.3, 20388.6", \ + "19499.8, 19499.8, 19499.8, 19901.7, 20368.0", \ + "19458.6, 19458.6, 19458.6, 19860.5, 20326.8"); + } + fall_transition (inslew_load_5x5__25) { + values ("5700.7, 5700.7, 5700.7, 5892.5, 6130.6", \ + "5700.7, 5700.7, 5700.7, 5892.5, 6130.6", \ + "5700.7, 5700.7, 5700.7, 5892.5, 6130.6", \ + "5700.7, 5700.7, 5700.7, 5892.5, 6130.6", \ + "5700.7, 5700.7, 5700.7, 5892.5, 6130.6"); + } + } + timing (maxd_sout_b1_negative_unate) { + related_pin : "b1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("26749.3, 26749.3, 26749.3, 27009.1, 27511.8", \ + "26742.9, 26742.9, 26742.9, 27002.7, 27505.4", \ + "26730.1, 26730.1, 26730.1, 26989.9, 27492.6", \ + "26704.4, 26704.4, 26704.4, 26964.2, 27466.9", \ + "26653.0, 26653.0, 26653.0, 26912.8, 27415.5"); + } + rise_transition (inslew_load_5x5__25) { + values ("8081.2, 8081.2, 8081.2, 8291.9, 8703.5", \ + "8081.2, 8081.2, 8081.2, 8291.9, 8703.5", \ + "8081.2, 8081.2, 8081.2, 8291.9, 8703.5", \ + "8081.2, 8081.2, 8081.2, 8291.9, 8703.5", \ + "8081.2, 8081.2, 8081.2, 8291.9, 8703.5"); + } + cell_fall (inslew_load_5x5__25) { + values ("17760.1, 17760.1, 17760.1, 18128.8, 18590.3", \ + "17765.4, 17765.4, 17765.4, 18134.2, 18595.7", \ + "17770.1, 17770.1, 17770.1, 18139.0, 18600.5", \ + "17783.3, 17783.3, 17783.3, 18152.2, 18613.7", \ + "17810.1, 17810.1, 17810.1, 18179.1, 18640.6"); + } + fall_transition (inslew_load_5x5__25) { + values ("5419.7, 5419.7, 5419.7, 5589.3, 5835.9", \ + "5421.3, 5421.3, 5421.3, 5591.0, 5837.6", \ + "5421.6, 5421.6, 5421.6, 5591.3, 5837.9", \ + "5421.9, 5421.9, 5421.9, 5591.6, 5838.2", \ + "5422.0, 5422.0, 5422.0, 5591.7, 5838.3"); + } + } + timing (maxd_sout_b2_negative_unate) { + related_pin : "b2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("23585.0, 23585.0, 23585.0, 23844.9, 24343.4", \ + "23572.2, 23572.2, 23572.2, 23832.0, 24330.5", \ + "23569.3, 23569.3, 23569.3, 23829.1, 24327.7", \ + "23547.0, 23547.0, 23547.0, 23806.9, 24305.4", \ + "23515.9, 23515.9, 23515.9, 23775.8, 24274.3"); + } + rise_transition (inslew_load_5x5__25) { + values ("7120.2, 7120.2, 7120.2, 7329.3, 7742.8", \ + "7119.8, 7119.8, 7119.8, 7328.8, 7742.3", \ + "7125.3, 7125.3, 7125.3, 7334.4, 7747.9", \ + "7129.9, 7129.9, 7129.9, 7338.9, 7752.4", \ + "7138.4, 7138.4, 7138.4, 7347.5, 7761.0"); + } + cell_fall (inslew_load_5x5__25) { + values ("21571.3, 21571.3, 21571.3, 21894.7, 22506.7", \ + "21566.1, 21566.1, 21566.1, 21889.5, 22501.5", \ + "21555.8, 21555.8, 21555.8, 21879.2, 22491.2", \ + "21535.2, 21535.2, 21535.2, 21858.6, 22470.6", \ + "21494.0, 21494.0, 21494.0, 21817.4, 22429.4"); + } + fall_transition (inslew_load_5x5__25) { + values ("6223.7, 6223.7, 6223.7, 6398.6, 6686.1", \ + "6223.7, 6223.7, 6223.7, 6398.6, 6686.1", \ + "6223.7, 6223.7, 6223.7, 6398.6, 6686.1", \ + "6223.7, 6223.7, 6223.7, 6398.6, 6686.1", \ + "6223.7, 6223.7, 6223.7, 6398.6, 6686.1"); + } + } + timing (maxd_sout_cin1_negative_unate) { + related_pin : "cin1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("18534.1, 18534.1, 18534.1, 18793.8, 19299.3", \ + "18545.7, 18545.7, 18545.7, 18805.4, 19310.8", \ + "18551.1, 18551.1, 18551.1, 18810.9, 19316.1", \ + "18574.8, 18574.8, 18574.8, 18834.5, 19339.5", \ + "18603.8, 18603.8, 18603.8, 18863.5, 19368.3"); + } + rise_transition (inslew_load_5x5__25) { + values ("5389.7, 5389.7, 5389.7, 5603.2, 6027.0", \ + "5394.0, 5394.0, 5394.0, 5607.4, 6031.2", \ + "5396.8, 5396.8, 5396.8, 5610.2, 6034.0", \ + "5404.7, 5404.7, 5404.7, 5618.0, 6041.8", \ + "5410.4, 5410.4, 5410.4, 5623.6, 6047.4"); + } + cell_fall (inslew_load_5x5__25) { + values ("17703.3, 17703.3, 17703.3, 18060.0, 18520.1", \ + "17709.3, 17709.3, 17709.3, 18066.3, 18526.4", \ + "17719.2, 17719.2, 17719.2, 18076.4, 18536.6", \ + "17733.5, 17733.5, 17733.5, 18090.8, 18551.0", \ + "17766.9, 17766.9, 17766.9, 18124.2, 18584.4"); + } + fall_transition (inslew_load_5x5__25) { + values ("5320.5, 5320.5, 5320.5, 5482.8, 5732.6", \ + "5322.4, 5322.4, 5322.4, 5484.9, 5734.6", \ + "5324.4, 5324.4, 5324.4, 5486.9, 5736.6", \ + "5324.7, 5324.7, 5324.7, 5487.3, 5736.9", \ + "5324.9, 5324.9, 5324.9, 5487.6, 5737.1"); + } + } + internal_power (energy_pos_sout_a3) { + related_pin : "a3" ; + rise_power (energy_inslew_load_5x5__25) { + values ("51012.8, 51012.8, 51012.8, 52042.9, 54103.3", \ + "54118.6, 54118.6, 54118.6, 54118.6, 54118.6", \ + "54149.2, 54149.2, 54149.2, 54149.2, 54149.2", \ + "54210.5, 54210.5, 54210.5, 54210.5, 54210.5", \ + "54333.1, 54333.1, 54333.1, 54333.1, 54333.1"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("77301.2, 77301.2, 77301.2, 78331.3, 80391.7", \ + "80426.5, 80426.5, 80426.5, 80426.5, 80426.5", \ + "80496.2, 80496.2, 80496.2, 80496.2, 80496.2", \ + "80635.6, 80635.6, 80635.6, 80635.6, 80635.6", \ + "80914.3, 80914.3, 80914.3, 80914.3, 80914.3"); + } + } + internal_power (energy_pos_sout_a4) { + related_pin : "a4" ; + rise_power (energy_inslew_load_5x5__25) { + values ("31365.9, 31365.9, 31365.9, 32396.1, 34456.4", \ + "34462.8, 34462.8, 34462.8, 34462.8, 34462.8", \ + "34475.5, 34475.5, 34475.5, 34475.5, 34475.5", \ + "34500.9, 34500.9, 34500.9, 34500.9, 34500.9", \ + "31461.5, 31461.5, 31461.5, 32491.6, 34552.0"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("53616.3, 53616.3, 53616.3, 54646.5, 56706.8", \ + "53690.0, 53690.0, 53690.0, 54720.2, 56780.5", \ + "53814.0, 53814.0, 53814.0, 54844.2, 56904.5", \ + "53983.2, 53983.2, 53983.2, 55013.4, 57073.7", \ + "54340.1, 54340.1, 54340.1, 55370.2, 57430.6"); + } + } + internal_power (energy_pos_sout_b3) { + related_pin : "b3" ; + rise_power (energy_inslew_load_5x5__25) { + values ("46008.3, 46008.3, 46008.3, 47038.4, 49098.8", \ + "46033.9, 46033.9, 46033.9, 47064.1, 49124.4", \ + "46069.5, 46069.5, 46069.5, 47099.7, 49160.0", \ + "46137.9, 46137.9, 46137.9, 47168.0, 49228.4", \ + "49364.3, 49364.3, 49364.3, 49364.3, 49364.3"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("74617.9, 74617.9, 74617.9, 75648.1, 77708.4", \ + "77733.9, 77733.9, 77733.9, 77733.9, 77733.9", \ + "77784.9, 77784.9, 77784.9, 77784.9, 77784.9", \ + "77886.9, 77886.9, 77886.9, 77886.9, 77886.9", \ + "78090.8, 78090.8, 78090.8, 78090.8, 78090.8"); + } + } + internal_power (energy_pos_sout_b4) { + related_pin : "b4" ; + rise_power (energy_inslew_load_5x5__25) { + values ("32602.2, 32602.2, 32602.2, 33632.4, 35692.7", \ + "35702.1, 35702.1, 35702.1, 35702.1, 35702.1", \ + "35721.0, 35721.0, 35721.0, 35721.0, 35721.0", \ + "35758.6, 35758.6, 35758.6, 35758.6, 35758.6", \ + "32743.7, 32743.7, 32743.7, 33773.8, 35834.2"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("64268.7, 64268.7, 64268.7, 65298.9, 67359.2", \ + "64315.8, 64315.8, 64315.8, 65346.0, 67406.3", \ + "64383.9, 64383.9, 64383.9, 65414.1, 67474.4", \ + "64548.6, 64548.6, 64548.6, 65578.8, 67639.1", \ + "64850.3, 64850.3, 64850.3, 65880.5, 67940.8"); + } + } + internal_power (energy_pos_sout_cin2) { + related_pin : "cin2" ; + rise_power (energy_inslew_load_5x5__25) { + values ("41244.9, 41244.9, 41244.9, 42275.1, 44335.4", \ + "41294.1, 41294.1, 41294.1, 42324.3, 44384.6", \ + "41391.8, 41391.8, 41391.8, 42421.9, 44482.3", \ + "41482.3, 41482.3, 41482.3, 42512.5, 44572.8", \ + "41628.3, 41628.3, 41628.3, 42658.4, 44718.8"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("70797.1, 70797.1, 70797.1, 71827.2, 73887.6", \ + "73907.2, 73907.2, 73907.2, 73907.2, 73907.2", \ + "73946.3, 73946.3, 73946.3, 73946.3, 73946.3", \ + "74024.6, 74024.6, 74024.6, 74024.6, 74024.6", \ + "74181.3, 74181.3, 74181.3, 74181.3, 74181.3"); + } + } + internal_power (energy_pos_sout_cin3) { + related_pin : "cin3" ; + rise_power (energy_inslew_load_5x5__25) { + values ("28059.8, 28059.8, 28059.8, 29089.9, 31150.3", \ + "31154.7, 31154.7, 31154.7, 31154.7, 31154.7", \ + "31163.6, 31163.6, 31163.6, 31163.6, 31163.6", \ + "31181.5, 31181.5, 31181.5, 31181.5, 31181.5", \ + "28127.0, 28127.0, 28127.0, 29157.2, 31217.5"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("43301.8, 43301.8, 43301.8, 44331.9, 46392.3", \ + "43260.6, 43260.6, 43260.6, 44290.8, 46351.1", \ + "43472.2, 43472.2, 43472.2, 44502.3, 46562.7", \ + "43803.8, 43803.8, 43803.8, 44833.9, 46894.3", \ + "44217.3, 44217.3, 44217.3, 45247.5, 47307.8"); + } + } + internal_power (energy_neg_sout_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__25) { + values ("80886.4, 80886.4, 80886.4, 81916.6, 83976.9", \ + "84020.7, 84020.7, 84020.7, 84020.7, 84020.7", \ + "84108.4, 84108.4, 84108.4, 84108.4, 84108.4", \ + "84283.6, 84283.6, 84283.6, 84283.6, 84283.6", \ + "84634.1, 84634.1, 84634.1, 84634.1, 84634.1"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("62397.9, 62397.9, 62397.9, 63428.1, 65488.4", \ + "65508.2, 65508.2, 65508.2, 65508.2, 65508.2", \ + "65547.9, 65547.9, 65547.9, 65547.9, 65547.9", \ + "65627.2, 65627.2, 65627.2, 65627.2, 65627.2", \ + "65785.9, 65785.9, 65785.9, 65785.9, 65785.9"); + } + } + internal_power (energy_neg_sout_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__25) { + values ("55351.8, 55351.8, 55351.8, 56382.0, 58442.3", \ + "55439.6, 55439.6, 55439.6, 56469.7, 58530.1", \ + "55586.4, 55586.4, 55586.4, 56616.6, 58676.9", \ + "55782.2, 55782.2, 55782.2, 56812.4, 58872.7", \ + "56186.8, 56186.8, 56186.8, 57216.9, 59277.3"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("54424.3, 54424.3, 54424.3, 55454.4, 57514.8", \ + "57528.8, 57528.8, 57528.8, 57528.8, 57528.8", \ + "57557.0, 57557.0, 57557.0, 57557.0, 57557.0", \ + "57613.4, 57613.4, 57613.4, 57613.4, 57613.4", \ + "57726.1, 57726.1, 57726.1, 57726.1, 57726.1"); + } + } + internal_power (energy_neg_sout_b1) { + related_pin : "b1" ; + rise_power (energy_inslew_load_5x5__25) { + values ("77742.4, 77742.4, 77742.4, 78772.6, 80832.9", \ + "80869.2, 80869.2, 80869.2, 80869.2, 80869.2", \ + "80941.9, 80941.9, 80941.9, 80941.9, 80941.9", \ + "81087.1, 81087.1, 81087.1, 81087.1, 81087.1", \ + "81377.7, 81377.7, 81377.7, 81377.7, 81377.7"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("57395.1, 57395.1, 57395.1, 58425.3, 60485.6", \ + "57424.8, 57424.8, 57424.8, 58455.0, 60515.3", \ + "57468.8, 57468.8, 57468.8, 58499.0, 60559.3", \ + "57555.2, 57555.2, 57555.2, 58585.4, 60645.7", \ + "57725.3, 57725.3, 57725.3, 58755.5, 60815.8"); + } + } + internal_power (energy_neg_sout_b2) { + related_pin : "b2" ; + rise_power (energy_inslew_load_5x5__25) { + values ("66873.3, 66873.3, 66873.3, 67903.5, 69963.8", \ + "66906.3, 66906.3, 66906.3, 67936.5, 69996.8", \ + "67002.9, 67002.9, 67002.9, 68033.1, 70093.4", \ + "67164.9, 67164.9, 67164.9, 68195.1, 70255.4", \ + "67486.7, 67486.7, 67486.7, 68516.9, 70577.2"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("61148.1, 61148.1, 61148.1, 62178.3, 64238.6", \ + "64257.9, 64257.9, 64257.9, 64257.9, 64257.9", \ + "64296.4, 64296.4, 64296.4, 64296.4, 64296.4", \ + "64373.5, 64373.5, 64373.5, 64373.5, 64373.5", \ + "64527.7, 64527.7, 64527.7, 64527.7, 64527.7"); + } + } + internal_power (energy_neg_sout_cin1) { + related_pin : "cin1" ; + rise_power (energy_inslew_load_5x5__25) { + values ("51153.0, 51153.0, 51153.0, 52183.1, 54243.5", \ + "51197.1, 51197.1, 51197.1, 52227.3, 54287.6", \ + "51260.9, 51260.9, 51260.9, 52291.0, 54351.4", \ + "51397.1, 51397.1, 51397.1, 52427.3, 54487.6", \ + "51626.4, 51626.4, 51626.4, 52656.6, 54716.9"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("49962.6, 49962.6, 49962.6, 50992.8, 53053.1", \ + "49987.9, 49987.9, 49987.9, 51018.0, 53078.4", \ + "50028.7, 50028.7, 50028.7, 51058.8, 53119.2", \ + "50091.7, 50091.7, 50091.7, 51121.8, 53182.2", \ + "50215.3, 50215.3, 50215.3, 51245.5, 53305.8"); + } + } + } + pin (cout) { + function : "(((b2 | a2) & ((a1 & b1) | cin1)) | (a1 & b1))" ; + direction : output ; + capacitance : 84.37 ; + timing (maxd_cout_a1_positive_unate) { + related_pin : "a1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__26) { + values ("11142.4, 11142.4, 11142.4, 11408.1, 11915.9", \ + "11139.9, 11139.9, 11139.9, 11405.6, 11913.4", \ + "11134.8, 11134.8, 11134.8, 11400.5, 11908.3", \ + "11124.8, 11124.8, 11124.8, 11390.5, 11898.3", \ + "11104.7, 11104.7, 11104.7, 11370.4, 11878.2"); + } + rise_transition (inslew_load_5x5__26) { + values ("5925.6, 5925.6, 5925.6, 6142.4, 6575.6", \ + "5925.6, 5925.6, 5925.6, 6142.4, 6575.6", \ + "5925.6, 5925.6, 5925.6, 6142.4, 6575.6", \ + "5925.6, 5925.6, 5925.6, 6142.4, 6575.6", \ + "5925.6, 5925.6, 5925.6, 6142.4, 6575.6"); + } + cell_fall (inslew_load_5x5__26) { + values ("17541.1, 17541.1, 17541.1, 17779.2, 18238.6", \ + "17534.6, 17534.6, 17534.6, 17772.7, 18232.1", \ + "17521.8, 17521.8, 17521.8, 17759.9, 18219.3", \ + "17496.1, 17496.1, 17496.1, 17734.2, 18193.6", \ + "17444.7, 17444.7, 17444.7, 17682.8, 18142.2"); + } + fall_transition (inslew_load_5x5__26) { + values ("9792.4, 9792.4, 9792.4, 9958.3, 10278.2", \ + "9792.4, 9792.4, 9792.4, 9958.3, 10278.2", \ + "9792.4, 9792.4, 9792.4, 9958.3, 10278.2", \ + "9792.4, 9792.4, 9792.4, 9958.3, 10278.2", \ + "9792.4, 9792.4, 9792.4, 9958.3, 10278.2"); + } + } + timing (maxd_cout_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__26) { + values ("11739.4, 11739.4, 11739.4, 12004.9, 12512.8", \ + "11734.2, 11734.2, 11734.2, 11999.7, 12507.6", \ + "11723.9, 11723.9, 11723.9, 11989.4, 12497.3", \ + "11703.3, 11703.3, 11703.3, 11968.8, 12476.7", \ + "11662.1, 11662.1, 11662.1, 11927.6, 12435.5"); + } + rise_transition (inslew_load_5x5__26) { + values ("5827.8, 5827.8, 5827.8, 6044.8, 6478.8", \ + "5827.8, 5827.8, 5827.8, 6044.8, 6478.8", \ + "5827.8, 5827.8, 5827.8, 6044.8, 6478.8", \ + "5827.8, 5827.8, 5827.8, 6044.8, 6478.8", \ + "5827.8, 5827.8, 5827.8, 6044.8, 6478.8"); + } + cell_fall (inslew_load_5x5__26) { + values ("10939.2, 10939.2, 10939.2, 11207.9, 11700.2", \ + "10960.3, 10960.3, 10960.3, 11229.1, 11721.9", \ + "10987.0, 10987.0, 10987.0, 11255.8, 11749.2", \ + "10990.6, 10990.6, 10990.6, 11259.4, 11753.3", \ + "11024.3, 11024.3, 11024.3, 11293.1, 11788.1"); + } + fall_transition (inslew_load_5x5__26) { + values ("5690.8, 5690.8, 5690.8, 5843.2, 6123.1", \ + "5711.3, 5711.3, 5711.3, 5863.6, 6143.7", \ + "5740.8, 5740.8, 5740.8, 5893.1, 6173.3", \ + "5762.7, 5762.7, 5762.7, 5914.9, 6195.3", \ + "5811.7, 5811.7, 5811.7, 5963.7, 6244.5"); + } + } + timing (maxd_cout_b1_positive_unate) { + related_pin : "b1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__26) { + values ("10004.8, 10004.8, 10004.8, 10270.5, 10787.4", \ + "10009.9, 10009.9, 10009.9, 10275.6, 10792.4", \ + "10014.6, 10014.6, 10014.6, 10280.3, 10797.1", \ + "10027.7, 10027.7, 10027.7, 10293.4, 10810.2", \ + "10054.6, 10054.6, 10054.6, 10320.3, 10837.0"); + } + rise_transition (inslew_load_5x5__26) { + values ("5196.4, 5196.4, 5196.4, 5415.7, 5852.0", \ + "5200.0, 5200.0, 5200.0, 5419.3, 5855.6", \ + "5200.7, 5200.7, 5200.7, 5420.0, 5856.3", \ + "5201.4, 5201.4, 5201.4, 5420.6, 5856.9", \ + "5201.5, 5201.5, 5201.5, 5420.8, 5857.1"); + } + cell_fall (inslew_load_5x5__26) { + values ("16887.4, 16887.4, 16887.4, 17122.9, 17582.0", \ + "16881.0, 16881.0, 16881.0, 17116.5, 17575.6", \ + "16868.2, 16868.2, 16868.2, 17103.7, 17562.8", \ + "16842.5, 16842.5, 16842.5, 17078.0, 17537.1", \ + "16791.1, 16791.1, 16791.1, 17026.6, 17485.7"); + } + fall_transition (inslew_load_5x5__26) { + values ("9306.3, 9306.3, 9306.3, 9471.2, 9791.3", \ + "9306.3, 9306.3, 9306.3, 9471.2, 9791.3", \ + "9306.3, 9306.3, 9306.3, 9471.2, 9791.3", \ + "9306.3, 9306.3, 9306.3, 9471.2, 9791.3", \ + "9306.3, 9306.3, 9306.3, 9471.2, 9791.3"); + } + } + timing (maxd_cout_b2_positive_unate) { + related_pin : "b2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__26) { + values ("13702.5, 13702.5, 13702.5, 13967.7, 14477.4", \ + "13697.3, 13697.3, 13697.3, 13962.5, 14472.2", \ + "13687.0, 13687.0, 13687.0, 13952.2, 14461.9", \ + "13666.4, 13666.4, 13666.4, 13931.6, 14441.3", \ + "13625.2, 13625.2, 13625.2, 13890.4, 14400.1"); + } + rise_transition (inslew_load_5x5__26) { + values ("7073.1, 7073.1, 7073.1, 7288.2, 7716.8", \ + "7073.1, 7073.1, 7073.1, 7288.2, 7716.8", \ + "7073.1, 7073.1, 7073.1, 7288.2, 7716.8", \ + "7073.1, 7073.1, 7073.1, 7288.2, 7716.8", \ + "7073.1, 7073.1, 7073.1, 7288.2, 7716.8"); + } + cell_fall (inslew_load_5x5__26) { + values ("14058.0, 14058.0, 14058.0, 14291.8, 14763.0", \ + "14045.4, 14045.4, 14045.4, 14279.1, 14750.4", \ + "14040.6, 14040.6, 14040.6, 14274.3, 14745.1", \ + "14016.7, 14016.7, 14016.7, 14250.5, 14720.8", \ + "13982.6, 13982.6, 13982.6, 14216.4, 14685.8"); + } + fall_transition (inslew_load_5x5__26) { + values ("7565.5, 7565.5, 7565.5, 7729.6, 8049.3", \ + "7564.6, 7564.6, 7564.6, 7728.8, 8048.5", \ + "7574.7, 7574.7, 7574.7, 7738.8, 8058.7", \ + "7582.8, 7582.8, 7582.8, 7746.9, 8067.0", \ + "7598.2, 7598.2, 7598.2, 7762.3, 8082.7"); + } + } + timing (maxd_cout_cin1_positive_unate) { + related_pin : "cin1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__26) { + values ("9963.8, 9963.8, 9963.8, 10230.0, 10752.0", \ + "9969.7, 9969.7, 9969.7, 10235.8, 10757.8", \ + "9979.2, 9979.2, 9979.2, 10245.3, 10767.2", \ + "9993.6, 9993.6, 9993.6, 10259.7, 10781.5", \ + "10026.9, 10026.9, 10026.9, 10293.0, 10814.8"); + } + rise_transition (inslew_load_5x5__26) { + values ("4976.0, 4976.0, 4976.0, 5196.8, 5632.5", \ + "4980.2, 4980.2, 4980.2, 5200.9, 5636.7", \ + "4984.5, 4984.5, 4984.5, 5205.2, 5640.9", \ + "4985.2, 4985.2, 4985.2, 5205.9, 5641.7", \ + "4985.7, 4985.7, 4985.7, 5206.4, 5642.1"); + } + cell_fall (inslew_load_5x5__26) { + values ("9916.4, 9916.4, 9916.4, 10171.0, 10647.3", \ + "9925.3, 9925.3, 9925.3, 10180.0, 10656.3", \ + "9928.8, 9928.8, 9928.8, 10183.5, 10660.0", \ + "9947.3, 9947.3, 9947.3, 10202.1, 10678.8", \ + "9972.6, 9972.6, 9972.6, 10227.5, 10704.2"); + } + fall_transition (inslew_load_5x5__26) { + values ("4565.1, 4565.1, 4565.1, 4706.7, 5002.7", \ + "4572.3, 4572.3, 4572.3, 4713.8, 5009.6", \ + "4577.2, 4577.2, 4577.2, 4718.7, 5014.4", \ + "4590.4, 4590.4, 4590.4, 4731.8, 5027.2", \ + "4600.1, 4600.1, 4600.1, 4741.4, 5036.7"); + } + } + internal_power (energy_pos_cout_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__26) { + values ("47013.4, 47013.4, 47013.4, 48068.1, 50177.4", \ + "50197.3, 50197.3, 50197.3, 50197.3, 50197.3", \ + "50236.9, 50236.9, 50236.9, 50236.9, 50236.9", \ + "50316.3, 50316.3, 50316.3, 50316.3, 50316.3", \ + "50474.9, 50474.9, 50474.9, 50474.9, 50474.9"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("65760.8, 65760.8, 65760.8, 66815.4, 68924.8", \ + "68968.6, 68968.6, 68968.6, 68968.6, 68968.6", \ + "69056.2, 69056.2, 69056.2, 69056.2, 69056.2", \ + "69231.4, 69231.4, 69231.4, 69231.4, 69231.4", \ + "69581.9, 69581.9, 69581.9, 69581.9, 69581.9"); + } + } + internal_power (energy_pos_cout_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__26) { + values ("38977.1, 38977.1, 38977.1, 40031.8, 42141.1", \ + "42155.2, 42155.2, 42155.2, 42155.2, 42155.2", \ + "42183.4, 42183.4, 42183.4, 42183.4, 42183.4", \ + "42239.8, 42239.8, 42239.8, 42239.8, 42239.8", \ + "42352.4, 42352.4, 42352.4, 42352.4, 42352.4"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("37528.6, 37528.6, 37528.6, 38583.3, 40692.6", \ + "37628.8, 37628.8, 37628.8, 38683.4, 40792.8", \ + "37792.5, 37792.5, 37792.5, 38847.2, 40956.5", \ + "38001.8, 38001.8, 38001.8, 39056.4, 41165.8", \ + "38436.5, 38436.5, 38436.5, 39491.2, 41600.5"); + } + } + internal_power (energy_pos_cout_b1) { + related_pin : "b1" ; + rise_power (energy_inslew_load_5x5__26) { + values ("41561.8, 41561.8, 41561.8, 42616.5, 44725.8", \ + "41593.7, 41593.7, 41593.7, 42648.3, 44757.7", \ + "41638.1, 41638.1, 41638.1, 42692.7, 44802.1", \ + "41724.9, 41724.9, 41724.9, 42779.5, 44888.9", \ + "41895.0, 41895.0, 41895.0, 42949.7, 45059.0"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("62282.2, 62282.2, 62282.2, 63336.9, 65446.2", \ + "65482.5, 65482.5, 65482.5, 65482.5, 65482.5", \ + "65555.1, 65555.1, 65555.1, 65555.1, 65555.1", \ + "65700.4, 65700.4, 65700.4, 65700.4, 65700.4", \ + "65990.9, 65990.9, 65990.9, 65990.9, 65990.9"); + } + } + internal_power (energy_pos_cout_b2) { + related_pin : "b2" ; + rise_power (energy_inslew_load_5x5__26) { + values ("46607.1, 46607.1, 46607.1, 47661.7, 49771.1", \ + "49790.3, 49790.3, 49790.3, 49790.3, 49790.3", \ + "49828.9, 49828.9, 49828.9, 49828.9, 49828.9", \ + "49906.0, 49906.0, 49906.0, 49906.0, 49906.0", \ + "50060.1, 50060.1, 50060.1, 50060.1, 50060.1"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("50232.2, 50232.2, 50232.2, 51286.9, 53396.2", \ + "50264.6, 50264.6, 50264.6, 51319.3, 53428.6", \ + "50368.1, 50368.1, 50368.1, 51422.8, 53532.1", \ + "50535.5, 50535.5, 50535.5, 51590.2, 53699.5", \ + "50867.6, 50867.6, 50867.6, 51922.3, 54031.6"); + } + } + internal_power (energy_pos_cout_cin1) { + related_pin : "cin1" ; + rise_power (energy_inslew_load_5x5__26) { + values ("34003.2, 34003.2, 34003.2, 35057.9, 37167.2", \ + "34030.7, 34030.7, 34030.7, 35085.4, 37194.7", \ + "34073.9, 34073.9, 34073.9, 35128.6, 37237.9", \ + "34137.3, 34137.3, 34137.3, 35192.0, 37301.3", \ + "34261.3, 34261.3, 34261.3, 35316.0, 37425.3"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("32683.0, 32683.0, 32683.0, 33737.7, 35847.0", \ + "32730.9, 32730.9, 32730.9, 33785.6, 35894.9", \ + "32797.4, 32797.4, 32797.4, 33852.1, 35961.4", \ + "32940.6, 32940.6, 32940.6, 33995.2, 36104.6", \ + "33175.1, 33175.1, 33175.1, 34229.8, 36339.1"); + } + } + } + } + + cell (noa3ao322_x4) { + area : 46.80 ; + cell_leakage_power : 11 ; + leakage_power () { + when : "(!(i6) & i5 & i4 & i3 & !(i2) & i1 & i0)" ; + value : 14 ; + } + leakage_power () { + when : "((i0 & ((i1 & i2 & ((i3 & ((i4 & (!(i5) | !(i6))) | (!(i4) & (i5 | i6)))) | (!(i3) & ((i4 & i5) | i6)))) | (!(i1) & i2 & !(i3) & !(i4) & !(i5) & !(i6)))) | (!(i0) & i1 & i2 & !(i3) & !(i4) & !(i5) & !(i6)))" ; + value : 10 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i1) & i3 & i4 & i5 & !(i6)))) | (!(i0) & (i1 | i2) & i3 & i4 & i5 & !(i6)))" ; + value : 13 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & !(i6)))" ; + value : 9.7 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & ((i4 & !(i5) & !(i6)) | (!(i4) & (i5 ^ i6)))))) | (!(i1) & ((!(i2) & ((i3 & (i4 ^ i5 ^ i6)) | (!(i3) & i4 & i5 & !(i6)))) | (i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))) | (!(i0) & ((i1 & ((!(i2) & ((i3 & (i4 ^ i5 ^ i6)) | (!(i3) & i4 & i5 & !(i6)))) | (i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i1) & ((i2 & ((i3 & (i4 ^ i5 ^ i6)) | (!(i3) & i4 & i5 & !(i6)))) | (!(i2) & ((i3 & ((i4 & (i5 | i6)) | (!(i5) & i6))) | (i4 & !(i5) & i6))))))))" ; + value : 12 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((!(i2) & ((i3 | i4 | i5) ^ !(i6))) | (i3 & i4 & i5 & i6))) | (!(i1) & ((i2 & ((i3 & (!((i4 | i5)) | i6)) | (!(i3) & ((i4 ^ i5) | i6)))) | (i3 & ((i4 & !(i5) & i6) | (!(i4) & !((i5 ^ i6))))) | (!(i3) & ((i4 ^ i5) | i6)))))) | (!(i0) & ((i1 & ((i2 & ((i3 & (!((i4 | i5)) | i6)) | (!(i3) & ((i4 ^ i5) | i6)))) | (i3 & ((i4 & !(i5) & i6) | (!(i4) & !((i5 ^ i6))))) | (!(i3) & ((i4 ^ i5) | i6)))) | (!(i1) & ((i2 & ((i3 & ((i4 & !(i5) & i6) | (!(i4) & !((i5 ^ i6))))) | (!(i3) & ((i4 ^ i5) | i6)))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6)) | (!(i4) & i5))) | (!(i3) & ((i4 & i5) | (i5 & i6))))))))))" ; + value : 11 ; + } + leakage_power () { + when : "((i0 & i1 & i2 & ((!(i3) & !((i4 & i5)) & !(i6)) | (!(i4) & !(i5) & !(i6)))) | (!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))" ; + value : 9.9 ; + } + leakage_power () { + when : "(i6 & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 9.8 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 8.9 ; + } + pin (i6) { + direction : input ; + capacitance : 514.62 ; + } + pin (i5) { + direction : input ; + capacitance : 544.97 ; + } + pin (i4) { + direction : input ; + capacitance : 545.27 ; + } + pin (i3) { + direction : input ; + capacitance : 545.57 ; + } + pin (i2) { + direction : input ; + capacitance : 538.60 ; + } + pin (i1) { + direction : input ; + capacitance : 541.15 ; + } + pin (i0) { + direction : input ; + capacitance : 541.75 ; + } + pin (nq) { + function : "((!((i5 | i4 | i3)) & (!(i2) | !(i0) | !(i1))) | (!((i2 & i0 & i1)) & !(i6)))" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("28959.5, 28959.5, 28959.5, 29199.5, 29664.6", \ + "28948.6, 28948.6, 28948.6, 29188.6, 29653.7", \ + "28926.7, 28926.7, 28926.7, 29166.7, 29631.8", \ + "28882.9, 28882.9, 28882.9, 29122.9, 29588.0", \ + "28795.5, 28795.5, 28795.5, 29035.5, 29500.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("8410.6, 8410.6, 8410.6, 8603.8, 8982.3", \ + "8410.6, 8410.6, 8410.6, 8603.8, 8982.3", \ + "8410.6, 8410.6, 8410.6, 8603.8, 8982.3", \ + "8410.6, 8410.6, 8410.6, 8603.8, 8982.3", \ + "8410.6, 8410.6, 8410.6, 8603.8, 8982.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("17841.6, 17841.6, 17841.6, 18059.9, 18471.3", \ + "17830.5, 17830.5, 17830.5, 18048.8, 18460.2", \ + "17808.4, 17808.4, 17808.4, 18026.7, 18438.1", \ + "17764.0, 17764.0, 17764.0, 17982.3, 18393.7", \ + "17675.4, 17675.4, 17675.4, 17893.7, 18305.1"); + } + fall_transition (inslew_load_5x5__3) { + values ("4307.5, 4307.5, 4307.5, 4418.9, 4678.4", \ + "4307.5, 4307.5, 4307.5, 4418.9, 4678.4", \ + "4307.5, 4307.5, 4307.5, 4418.9, 4678.4", \ + "4307.5, 4307.5, 4307.5, 4418.9, 4678.4", \ + "4307.5, 4307.5, 4307.5, 4418.9, 4678.4"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("28068.1, 28068.1, 28068.1, 28308.6, 28773.1", \ + "28057.2, 28057.2, 28057.2, 28297.7, 28762.2", \ + "28035.3, 28035.3, 28035.3, 28275.8, 28740.3", \ + "27991.6, 27991.6, 27991.6, 28232.1, 28696.6", \ + "27904.1, 27904.1, 27904.1, 28144.6, 28609.1"); + } + rise_transition (inslew_load_5x5__3) { + values ("8106.8, 8106.8, 8106.8, 8300.8, 8679.1", \ + "8106.8, 8106.8, 8106.8, 8300.8, 8679.1", \ + "8106.8, 8106.8, 8106.8, 8300.8, 8679.1", \ + "8106.8, 8106.8, 8106.8, 8300.8, 8679.1", \ + "8106.8, 8106.8, 8106.8, 8300.8, 8679.1"); + } + cell_fall (inslew_load_5x5__3) { + values ("16219.3, 16219.3, 16219.3, 16435.4, 16744.1", \ + "16216.1, 16216.1, 16216.1, 16432.2, 16740.9", \ + "16207.1, 16207.1, 16207.1, 16423.3, 16731.9", \ + "16190.8, 16190.8, 16190.8, 16407.0, 16715.6", \ + "16158.7, 16158.7, 16158.7, 16374.9, 16683.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("3942.2, 3942.2, 3942.2, 4062.2, 4255.5", \ + "3942.9, 3942.9, 3942.9, 4062.9, 4256.1", \ + "3943.1, 3943.1, 3943.1, 4063.0, 4256.3", \ + "3943.1, 3943.1, 3943.1, 4063.0, 4256.3", \ + "3943.1, 3943.1, 3943.1, 4063.0, 4256.3"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("26767.4, 26767.4, 26767.4, 27007.9, 27471.4", \ + "26756.4, 26756.4, 26756.4, 26996.9, 27460.4", \ + "26734.6, 26734.6, 26734.6, 26975.1, 27438.6", \ + "26690.8, 26690.8, 26690.8, 26931.3, 27394.8", \ + "26603.4, 26603.4, 26603.4, 26843.9, 27307.4"); + } + rise_transition (inslew_load_5x5__3) { + values ("7668.3, 7668.3, 7668.3, 7861.8, 8241.2", \ + "7668.3, 7668.3, 7668.3, 7861.8, 8241.2", \ + "7668.3, 7668.3, 7668.3, 7861.8, 8241.2", \ + "7668.3, 7668.3, 7668.3, 7861.8, 8241.2", \ + "7668.3, 7668.3, 7668.3, 7861.8, 8241.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("14590.9, 14590.9, 14590.9, 14705.3, 15115.6", \ + "14613.1, 14613.1, 14613.1, 14727.5, 15137.8", \ + "14632.2, 14632.2, 14632.2, 14746.7, 15156.9", \ + "14640.0, 14640.0, 14640.0, 14754.5, 15164.7", \ + "14665.9, 14665.9, 14665.9, 14780.3, 15190.6"); + } + fall_transition (inslew_load_5x5__3) { + values ("3574.2, 3574.2, 3574.2, 3607.2, 3918.4", \ + "3580.4, 3580.4, 3580.4, 3613.2, 3924.1", \ + "3586.0, 3586.0, 3586.0, 3618.5, 3929.2", \ + "3587.2, 3587.2, 3587.2, 3619.7, 3930.3", \ + "3588.6, 3588.6, 3588.6, 3621.0, 3931.6"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("13741.4, 13741.4, 13741.4, 14003.5, 14490.8", \ + "13796.2, 13796.2, 13796.2, 14058.0, 14545.2", \ + "13762.3, 13762.3, 13762.3, 14024.2, 14511.4", \ + "13880.7, 13880.7, 13880.7, 14142.2, 14629.1", \ + "13946.8, 13946.8, 13946.8, 14207.9, 14694.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("3366.5, 3366.5, 3366.5, 3580.8, 3992.1", \ + "3390.9, 3390.9, 3390.9, 3604.8, 4015.5", \ + "3386.1, 3386.1, 3386.1, 3600.1, 4011.0", \ + "3444.2, 3444.2, 3444.2, 3657.2, 4066.7", \ + "3491.1, 3491.1, 3491.1, 3703.5, 4111.9"); + } + cell_fall (inslew_load_5x5__3) { + values ("13529.5, 13529.5, 13529.5, 13740.6, 14152.1", \ + "13530.0, 13530.0, 13530.0, 13741.1, 14152.6", \ + "13531.0, 13531.0, 13531.0, 13742.1, 14153.6", \ + "13533.1, 13533.1, 13533.1, 13744.2, 14155.7", \ + "13537.4, 13537.4, 13537.4, 13748.5, 14159.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("3079.5, 3079.5, 3079.5, 3237.1, 3560.9", \ + "3079.5, 3079.5, 3079.5, 3237.1, 3560.9", \ + "3079.5, 3079.5, 3079.5, 3237.1, 3560.9", \ + "3079.5, 3079.5, 3079.5, 3237.1, 3560.9", \ + "3079.5, 3079.5, 3079.5, 3237.2, 3560.9"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("18426.5, 18426.5, 18426.5, 18666.6, 19146.8", \ + "18398.9, 18398.9, 18398.9, 18639.0, 19119.4", \ + "18416.8, 18416.8, 18416.8, 18656.9, 19136.7", \ + "18401.0, 18401.0, 18401.0, 18641.1, 19120.5", \ + "18406.6, 18406.6, 18406.6, 18646.6, 19125.0"); + } + rise_transition (inslew_load_5x5__3) { + values ("5001.2, 5001.2, 5001.2, 5200.5, 5591.0", \ + "4995.8, 4995.8, 4995.8, 5195.2, 5585.7", \ + "5010.9, 5010.9, 5010.9, 5210.1, 5600.7", \ + "5020.8, 5020.8, 5020.8, 5220.0, 5610.6", \ + "5048.6, 5048.6, 5048.6, 5247.5, 5638.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("15745.2, 15745.2, 15745.2, 15859.6, 16269.6", \ + "15745.7, 15745.7, 15745.7, 15860.1, 16270.1", \ + "15746.8, 15746.8, 15746.8, 15861.2, 16271.2", \ + "15748.8, 15748.8, 15748.8, 15863.2, 16273.2", \ + "15753.0, 15753.0, 15753.0, 15867.4, 16277.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("3655.6, 3655.6, 3655.6, 3684.8, 3992.9", \ + "3655.6, 3655.6, 3655.6, 3684.8, 3992.9", \ + "3655.6, 3655.6, 3655.6, 3684.8, 3992.9", \ + "3655.6, 3655.6, 3655.6, 3684.8, 3992.9", \ + "3655.6, 3655.6, 3655.6, 3684.8, 3992.9"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("22804.1, 22804.1, 22804.1, 23044.8, 23503.7", \ + "22799.8, 22799.8, 22799.8, 23040.5, 23499.4", \ + "22774.2, 22774.2, 22774.2, 23014.9, 23473.8", \ + "22745.8, 22745.8, 22745.8, 22986.5, 23445.4", \ + "22680.0, 22680.0, 22680.0, 22920.7, 23379.7"); + } + rise_transition (inslew_load_5x5__3) { + values ("6433.6, 6433.6, 6433.6, 6627.2, 7009.1", \ + "6437.0, 6437.0, 6437.0, 6630.5, 7012.5", \ + "6437.5, 6437.5, 6437.5, 6631.1, 7013.0", \ + "6445.2, 6445.2, 6445.2, 6638.7, 7020.6", \ + "6453.5, 6453.5, 6453.5, 6647.0, 7028.9"); + } + cell_fall (inslew_load_5x5__3) { + values ("16754.5, 16754.5, 16754.5, 16970.2, 17279.2", \ + "16755.0, 16755.0, 16755.0, 16970.7, 17279.7", \ + "16756.0, 16756.0, 16756.0, 16971.7, 17280.7", \ + "16758.1, 16758.1, 16758.1, 16973.8, 17282.8", \ + "16762.2, 16762.2, 16762.2, 16977.9, 17286.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("3880.4, 3880.4, 3880.4, 4002.0, 4198.8", \ + "3880.4, 3880.4, 3880.4, 4002.0, 4198.8", \ + "3880.4, 3880.4, 3880.4, 4002.0, 4198.8", \ + "3880.4, 3880.4, 3880.4, 4002.0, 4198.8", \ + "3880.4, 3880.4, 3880.4, 4002.0, 4198.8"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("10594.8, 10594.8, 10594.8, 10881.7, 11402.5", \ + "10611.9, 10611.9, 10611.9, 10898.7, 11419.4", \ + "10619.0, 10619.0, 10619.0, 10905.8, 11426.4", \ + "10652.7, 10652.7, 10652.7, 10939.3, 11459.6", \ + "10686.0, 10686.0, 10686.0, 10972.5, 11492.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("2076.7, 2076.7, 2076.7, 2322.1, 2772.0", \ + "2083.7, 2083.7, 2083.7, 2329.0, 2778.7", \ + "2088.4, 2088.4, 2088.4, 2333.6, 2783.2", \ + "2102.4, 2102.4, 2102.4, 2347.3, 2796.4", \ + "2113.6, 2113.6, 2113.6, 2358.4, 2807.0"); + } + cell_fall (inslew_load_5x5__3) { + values ("11332.8, 11332.8, 11332.8, 11553.7, 12083.3", \ + "11349.9, 11349.9, 11349.9, 11569.1, 12099.7", \ + "11363.6, 11363.6, 11363.6, 11581.2, 12112.7", \ + "11370.5, 11370.5, 11370.5, 11587.5, 12119.4", \ + "11387.6, 11387.6, 11387.6, 11604.2, 12136.3"); + } + fall_transition (inslew_load_5x5__3) { + values ("2628.2, 2628.2, 2628.2, 2808.7, 3128.3", \ + "2633.2, 2633.2, 2633.2, 2813.1, 3133.6", \ + "2637.5, 2637.5, 2637.5, 2816.8, 3138.2", \ + "2639.2, 2639.2, 2639.2, 2818.3, 3139.9", \ + "2640.6, 2640.6, 2640.6, 2819.6, 3141.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("133575.9, 133575.9, 133575.9, 135471.8, 139263.4", \ + "139331.3, 139331.3, 139331.3, 139331.3, 139331.3", \ + "139467.0, 139467.0, 139467.0, 139467.0, 139467.0", \ + "139738.5, 139738.5, 139738.5, 139738.5, 139738.5", \ + "140281.3, 140281.3, 140281.3, 140281.3, 140281.3"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("87635.4, 87635.4, 87635.4, 89531.3, 93322.9", \ + "93344.5, 93344.5, 93344.5, 93344.5, 93344.5", \ + "93387.6, 93387.6, 93387.6, 93387.6, 93387.6", \ + "93473.7, 93473.7, 93473.7, 93473.7, 93473.7", \ + "93646.1, 93646.1, 93646.1, 93646.1, 93646.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("128966.7, 128966.7, 128966.7, 130862.6, 134654.2", \ + "134705.1, 134705.1, 134705.1, 134705.1, 134705.1", \ + "134806.9, 134806.9, 134806.9, 134806.9, 134806.9", \ + "135010.4, 135010.4, 135010.4, 135010.4, 135010.4", \ + "135417.4, 135417.4, 135417.4, 135417.4, 135417.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("79202.3, 79202.3, 79202.3, 81098.1, 84889.8", \ + "79235.0, 79235.0, 79235.0, 81130.8, 84922.5", \ + "79286.4, 79286.4, 79286.4, 81182.2, 84973.9", \ + "85073.0, 85073.0, 85073.0, 85073.0, 85073.0", \ + "85271.1, 85271.1, 85271.1, 85271.1, 85271.1"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("122309.0, 122309.0, 122309.0, 124204.8, 127996.5", \ + "128036.5, 128036.5, 128036.5, 128036.5, 128036.5", \ + "128116.5, 128116.5, 128116.5, 128116.5, 128116.5", \ + "128276.5, 128276.5, 128276.5, 128276.5, 128276.5", \ + "128596.5, 128596.5, 128596.5, 128596.5, 128596.5"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("71075.4, 71075.4, 71075.4, 72971.2, 76762.9", \ + "71171.0, 71171.0, 71171.0, 73066.9, 76858.6", \ + "71285.2, 71285.2, 71285.2, 73181.1, 76972.7", \ + "71405.4, 71405.4, 71405.4, 73301.3, 77093.0", \ + "71634.0, 71634.0, 71634.0, 73529.9, 77321.5"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__3) { + values ("63260.8, 63260.8, 63260.8, 65156.6, 68948.3", \ + "63479.8, 63479.8, 63479.8, 65375.7, 69167.3", \ + "63513.2, 63513.2, 63513.2, 65409.0, 69200.7", \ + "64090.5, 64090.5, 64090.5, 65986.3, 69778.0", \ + "64724.5, 64724.5, 64724.5, 66620.3, 70412.0"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("61226.8, 61226.8, 61226.8, 63122.7, 66914.4", \ + "66928.0, 66928.0, 66928.0, 66928.0, 66928.0", \ + "66955.2, 66955.2, 66955.2, 66955.2, 66955.2", \ + "67009.6, 67009.6, 67009.6, 67009.6, 67009.6", \ + "61431.7, 61431.7, 61431.7, 63327.6, 67119.2"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__3) { + values ("83717.7, 83717.7, 83717.7, 85613.5, 89405.2", \ + "83707.3, 83707.3, 83707.3, 85603.1, 89394.8", \ + "83905.6, 83905.6, 83905.6, 85801.4, 89593.1", \ + "84130.3, 84130.3, 84130.3, 86026.2, 89817.8", \ + "84647.6, 84647.6, 84647.6, 86543.4, 90335.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("70491.7, 70491.7, 70491.7, 72387.5, 76179.2", \ + "76196.8, 76196.8, 76196.8, 76196.8, 76196.8", \ + "76232.0, 76232.0, 76232.0, 76232.0, 76232.0", \ + "76302.4, 76302.4, 76302.4, 76302.4, 76302.4", \ + "76443.3, 76443.3, 76443.3, 76443.3, 76443.3"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__3) { + values ("104207.1, 104207.1, 104207.1, 106102.9, 109894.6", \ + "104272.7, 104272.7, 104272.7, 106168.5, 109960.2", \ + "104348.8, 104348.8, 104348.8, 106244.6, 110036.3", \ + "104558.8, 104558.8, 104558.8, 106454.6, 110246.3", \ + "104916.6, 104916.6, 104916.6, 106812.4, 110604.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("75053.6, 75053.6, 75053.6, 76949.4, 80741.1", \ + "80764.8, 80764.8, 80764.8, 80764.8, 80764.8", \ + "80812.2, 80812.2, 80812.2, 80812.2, 80812.2", \ + "80907.0, 80907.0, 80907.0, 80907.0, 80907.0", \ + "81096.6, 81096.6, 81096.6, 81096.6, 81096.6"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__3) { + values ("52411.8, 52411.8, 52411.8, 54307.6, 58099.3", \ + "52490.2, 52490.2, 52490.2, 54386.1, 58177.7", \ + "52586.8, 52586.8, 52586.8, 54482.6, 58274.3", \ + "52809.7, 52809.7, 52809.7, 54705.6, 58497.2", \ + "53149.8, 53149.8, 53149.8, 55045.7, 58837.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("53094.9, 53094.9, 53094.9, 54990.8, 58782.5", \ + "53164.5, 53164.5, 53164.5, 55060.3, 58852.0", \ + "53247.0, 53247.0, 53247.0, 55142.8, 58934.5", \ + "53343.6, 53343.6, 53343.6, 55239.4, 59031.1", \ + "53516.9, 53516.9, 53516.9, 55412.8, 59204.5"); + } + } + } + } + + cell (halfadder_x4) { + area : 64.80 ; + cell_leakage_power : 15 ; + leakage_power () { + when : "(!(b) & a)" ; + value : 17 ; + } + leakage_power () { + when : "b" ; + value : 15 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 12 ; + } + pin (b) { + direction : input ; + capacitance : 1250.49 ; + } + pin (a) { + direction : input ; + capacitance : 1301.97 ; + } + pin (sout) { + function : "(a ^ b)" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_sout_a_positive_unate) { + related_pin : "a" ; + when : "!(b)" ; + sdf_cond : "!(b)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("10722.3, 10722.3, 10722.3, 10961.6, 11420.4", \ + "10719.8, 10719.8, 10719.8, 10959.1, 11417.9", \ + "10714.8, 10714.8, 10714.8, 10954.1, 11412.9", \ + "10704.8, 10704.8, 10704.8, 10944.1, 11402.9", \ + "10684.7, 10684.7, 10684.7, 10924.0, 11382.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("5656.4, 5656.4, 5656.4, 5851.2, 6240.6", \ + "5656.4, 5656.4, 5656.4, 5851.2, 6240.6", \ + "5656.4, 5656.4, 5656.4, 5851.2, 6240.6", \ + "5656.4, 5656.4, 5656.4, 5851.2, 6240.6", \ + "5656.4, 5656.4, 5656.4, 5851.2, 6240.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("11457.5, 11457.5, 11457.5, 11753.9, 12289.3", \ + "11456.2, 11456.2, 11456.2, 11752.7, 12288.2", \ + "11468.8, 11468.8, 11468.8, 11765.6, 12302.2", \ + "11484.6, 11484.6, 11484.6, 11781.8, 12319.4", \ + "11507.2, 11507.2, 11507.2, 11804.7, 12342.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("5769.1, 5769.1, 5769.1, 5923.1, 6169.7", \ + "5770.3, 5770.3, 5770.3, 5924.3, 6171.0", \ + "5780.7, 5780.7, 5780.7, 5935.2, 6182.1", \ + "5791.9, 5791.9, 5791.9, 5946.8, 6193.9", \ + "5798.3, 5798.3, 5798.3, 5953.5, 6200.7"); + } + } + timing (maxd_sout_b_positive_unate) { + related_pin : "b" ; + when : "!(a)" ; + sdf_cond : "!(a)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("12670.8, 12670.8, 12670.8, 12910.9, 13371.9", \ + "12668.3, 12668.3, 12668.3, 12908.4, 13369.4", \ + "12663.3, 12663.3, 12663.3, 12903.3, 13364.3", \ + "12653.3, 12653.3, 12653.3, 12893.4, 13354.4", \ + "12633.2, 12633.2, 12633.2, 12873.3, 13334.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("6923.7, 6923.7, 6923.7, 7116.0, 7497.3", \ + "6923.7, 6923.7, 6923.7, 7116.0, 7497.3", \ + "6923.7, 6923.7, 6923.7, 7115.9, 7497.2", \ + "6923.7, 6923.7, 6923.7, 7116.0, 7497.3", \ + "6923.7, 6923.7, 6923.7, 7116.0, 7497.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("13988.5, 13988.5, 13988.5, 14203.9, 14752.6", \ + "13983.2, 13983.2, 13983.2, 14198.6, 14747.3", \ + "13972.4, 13972.4, 13972.4, 14187.8, 14736.5", \ + "13951.0, 13951.0, 13951.0, 14166.4, 14715.1", \ + "13908.2, 13908.2, 13908.2, 14123.6, 14672.3"); + } + fall_transition (inslew_load_5x5__3) { + values ("7154.6, 7154.6, 7154.6, 7321.3, 7618.5", \ + "7154.6, 7154.6, 7154.6, 7321.3, 7618.5", \ + "7154.6, 7154.6, 7154.6, 7321.3, 7618.5", \ + "7154.6, 7154.6, 7154.6, 7321.3, 7618.5", \ + "7154.6, 7154.6, 7154.6, 7321.3, 7618.5"); + } + } + timing (maxd_sout_a_negative_unate) { + related_pin : "a" ; + when : "b" ; + sdf_cond : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("14705.8, 14705.8, 14705.8, 14946.4, 15405.2", \ + "14714.6, 14714.6, 14714.6, 14955.2, 15414.0", \ + "14732.2, 14732.2, 14732.2, 14972.8, 15431.6", \ + "14767.4, 14767.4, 14767.4, 15008.0, 15466.8", \ + "14837.4, 14837.4, 14837.4, 15078.0, 15536.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("6271.0, 6271.0, 6271.0, 6465.2, 6848.4", \ + "6271.0, 6271.0, 6271.0, 6465.2, 6848.4", \ + "6271.0, 6271.0, 6271.0, 6465.2, 6848.4", \ + "6271.0, 6271.0, 6271.0, 6465.2, 6848.4", \ + "6271.4, 6271.4, 6271.4, 6465.5, 6848.8"); + } + cell_fall (inslew_load_5x5__3) { + values ("15704.4, 15704.4, 15704.4, 15968.7, 16511.7", \ + "15713.2, 15713.2, 15713.2, 15977.5, 16520.5", \ + "15730.7, 15730.7, 15730.7, 15995.0, 16538.0", \ + "15765.9, 15765.9, 15765.9, 16030.2, 16573.2", \ + "15832.5, 15832.5, 15832.5, 16096.8, 16639.8"); + } + fall_transition (inslew_load_5x5__3) { + values ("6779.0, 6779.0, 6779.0, 6945.4, 7225.4", \ + "6779.0, 6779.0, 6779.0, 6945.4, 7225.4", \ + "6779.0, 6779.0, 6779.0, 6945.4, 7225.4", \ + "6779.0, 6779.0, 6779.0, 6945.4, 7225.4", \ + "6779.0, 6779.0, 6779.0, 6945.4, 7225.4"); + } + } + timing (maxd_sout_b_negative_unate) { + related_pin : "b" ; + when : "a" ; + sdf_cond : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("13609.6, 13609.6, 13609.6, 13849.7, 14326.7", \ + "13618.4, 13618.4, 13618.4, 13858.5, 14335.5", \ + "13636.0, 13636.0, 13636.0, 13876.1, 14353.1", \ + "13671.2, 13671.2, 13671.2, 13911.3, 14388.3", \ + "13741.6, 13741.6, 13741.6, 13981.7, 14458.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("5061.2, 5061.2, 5061.2, 5260.0, 5650.7", \ + "5061.2, 5061.2, 5061.2, 5260.0, 5650.7", \ + "5061.2, 5061.2, 5061.2, 5260.0, 5650.7", \ + "5061.2, 5061.2, 5061.2, 5260.0, 5650.7", \ + "5061.4, 5061.4, 5061.4, 5260.2, 5650.9"); + } + cell_fall (inslew_load_5x5__3) { + values ("13348.3, 13348.3, 13348.3, 13705.0, 14132.2", \ + "13357.1, 13357.1, 13357.1, 13713.8, 14141.0", \ + "13374.7, 13374.7, 13374.7, 13731.4, 14158.6", \ + "13409.8, 13409.8, 13409.8, 13766.5, 14193.7", \ + "13477.5, 13477.5, 13477.5, 13834.2, 14261.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("5414.3, 5414.3, 5414.3, 5576.0, 5795.5", \ + "5414.3, 5414.3, 5414.3, 5576.0, 5795.5", \ + "5414.3, 5414.3, 5414.3, 5576.0, 5795.5", \ + "5414.3, 5414.3, 5414.3, 5576.0, 5795.5", \ + "5414.4, 5414.4, 5414.4, 5575.7, 5795.5"); + } + } + internal_power (energy_pos_sout_a) { + related_pin : "a" ; + when : "!(b)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("63379.0, 63379.0, 63379.0, 65274.9, 69066.6", \ + "69083.0, 69083.0, 69083.0, 69083.0, 69083.0", \ + "69116.0, 69116.0, 69116.0, 69116.0, 69116.0", \ + "69182.0, 69182.0, 69182.0, 69182.0, 69182.0", \ + "69313.9, 69313.9, 69313.9, 69313.9, 69313.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("60310.3, 60310.3, 60310.3, 62206.2, 65997.8", \ + "60360.8, 60360.8, 60360.8, 62256.7, 66048.4", \ + "60511.5, 60511.5, 60511.5, 62407.3, 66199.0", \ + "60752.5, 60752.5, 60752.5, 62648.3, 66440.0", \ + "61137.7, 61137.7, 61137.7, 63033.5, 66825.2"); + } + } + internal_power (energy_pos_sout_b) { + related_pin : "b" ; + when : "!(a)" ; + rise_power (energy_inslew_load_5x5__3) { + values ("75945.8, 75945.8, 75945.8, 77841.7, 81633.4", \ + "81659.3, 81659.3, 81659.3, 81659.3, 81659.3", \ + "76023.3, 76023.3, 76023.3, 77919.1, 81710.8", \ + "81814.6, 81814.6, 81814.6, 81814.6, 81814.6", \ + "82022.1, 82022.1, 82022.1, 82022.1, 82022.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("75940.2, 75940.2, 75940.2, 77836.1, 81627.7", \ + "81672.0, 81672.0, 81672.0, 81672.0, 81672.0", \ + "81760.4, 81760.4, 81760.4, 81760.4, 81760.4", \ + "81937.4, 81937.4, 81937.4, 81937.4, 81937.4", \ + "82291.3, 82291.3, 82291.3, 82291.3, 82291.3"); + } + } + internal_power (energy_neg_sout_a) { + related_pin : "a" ; + when : "b" ; + rise_power (energy_inslew_load_5x5__3) { + values ("77106.1, 77106.1, 77106.1, 79002.0, 82793.6", \ + "82828.7, 82828.7, 82828.7, 82828.7, 82828.7", \ + "82898.8, 82898.8, 82898.8, 82898.8, 82898.8", \ + "83039.1, 83039.1, 83039.1, 83039.1, 83039.1", \ + "77638.0, 77638.0, 77638.0, 79533.9, 83325.5"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("79532.1, 79532.1, 79532.1, 81427.9, 85219.6", \ + "85247.1, 85247.1, 85247.1, 85247.1, 85247.1", \ + "85302.3, 85302.3, 85302.3, 85302.3, 85302.3", \ + "85412.6, 85412.6, 85412.6, 85412.6, 85412.6", \ + "85641.0, 85641.0, 85641.0, 85641.0, 85641.0"); + } + } + internal_power (energy_neg_sout_b) { + related_pin : "b" ; + when : "a" ; + rise_power (energy_inslew_load_5x5__3) { + values ("64675.6, 64675.6, 64675.6, 66571.5, 70363.2", \ + "70398.4, 70398.4, 70398.4, 70398.4, 70398.4", \ + "70468.9, 70468.9, 70468.9, 70468.9, 70468.9", \ + "70610.0, 70610.0, 70610.0, 70610.0, 70610.0", \ + "65206.8, 65206.8, 65206.8, 67102.7, 70894.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("63875.5, 63875.5, 63875.5, 65771.3, 69563.0", \ + "69581.3, 69581.3, 69581.3, 69581.3, 69581.3", \ + "69617.9, 69617.9, 69617.9, 69617.9, 69617.9", \ + "69691.5, 69691.5, 69691.5, 69691.5, 69691.5", \ + "64162.7, 64162.7, 64162.7, 66058.5, 69850.2"); + } + } + } + pin (cout) { + function : "(a & b)" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_cout_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("9830.8, 9830.8, 9830.8, 10070.5, 10540.7", \ + "9830.5, 9830.5, 9830.5, 10070.2, 10540.4", \ + "9829.9, 9829.9, 9829.9, 10069.6, 10539.8", \ + "9828.8, 9828.8, 9828.8, 10068.5, 10538.7", \ + "9826.6, 9826.6, 9826.6, 10066.3, 10536.5"); + } + rise_transition (inslew_load_5x5__3) { + values ("5264.9, 5264.9, 5264.9, 5462.0, 5852.4", \ + "5264.9, 5264.9, 5264.9, 5462.0, 5852.4", \ + "5264.9, 5264.9, 5264.9, 5462.0, 5852.4", \ + "5264.9, 5264.9, 5264.9, 5462.0, 5852.4", \ + "5264.9, 5264.9, 5264.9, 5462.0, 5852.4"); + } + cell_fall (inslew_load_5x5__3) { + values ("9160.5, 9160.5, 9160.5, 9375.8, 9686.9", \ + "9169.3, 9169.3, 9169.3, 9384.6, 9695.7", \ + "9186.9, 9186.9, 9186.9, 9402.2, 9713.3", \ + "9222.1, 9222.1, 9222.1, 9437.4, 9748.5", \ + "9292.5, 9292.5, 9292.5, 9507.8, 9818.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("3726.6, 3726.6, 3726.6, 3852.4, 4058.5", \ + "3726.6, 3726.6, 3726.6, 3852.4, 4058.5", \ + "3726.6, 3726.6, 3726.6, 3852.4, 4058.5", \ + "3726.6, 3726.6, 3726.6, 3852.4, 4058.5", \ + "3726.6, 3726.6, 3726.6, 3852.4, 4058.5"); + } + } + timing (maxd_cout_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("8581.1, 8581.1, 8581.1, 8836.0, 9320.1", \ + "8588.1, 8588.1, 8588.1, 8843.1, 9327.1", \ + "8591.6, 8591.6, 8591.6, 8846.5, 9330.5", \ + "8600.5, 8600.5, 8600.5, 8855.4, 9339.4", \ + "8621.1, 8621.1, 8621.1, 8876.0, 9360.0"); + } + rise_transition (inslew_load_5x5__3) { + values ("4401.3, 4401.3, 4401.3, 4601.9, 4997.4", \ + "4407.4, 4407.4, 4407.4, 4607.9, 5003.3", \ + "4408.8, 4408.8, 4408.8, 4609.3, 5004.8", \ + "4409.1, 4409.1, 4409.1, 4609.6, 5005.0", \ + "4409.3, 4409.3, 4409.3, 4609.8, 5005.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("8596.7, 8596.7, 8596.7, 8808.1, 9220.0", \ + "8605.5, 8605.5, 8605.5, 8816.9, 9228.8", \ + "8623.1, 8623.1, 8623.1, 8834.5, 9246.4", \ + "8658.3, 8658.3, 8658.3, 8869.7, 9281.6", \ + "8728.7, 8728.7, 8728.7, 8940.1, 9352.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("3294.4, 3294.4, 3294.4, 3443.6, 3760.4", \ + "3294.4, 3294.4, 3294.4, 3443.6, 3760.4", \ + "3294.4, 3294.4, 3294.4, 3443.6, 3760.4", \ + "3294.4, 3294.4, 3294.4, 3443.6, 3760.4", \ + "3294.4, 3294.4, 3294.4, 3443.6, 3760.4"); + } + } + internal_power (energy_pos_cout_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__3) { + values ("61169.9, 61169.9, 61169.9, 63065.7, 66857.4", \ + "66877.2, 66877.2, 66877.2, 66877.2, 66877.2", \ + "66916.9, 66916.9, 66916.9, 66916.9, 66916.9", \ + "66996.2, 66996.2, 66996.2, 66996.2, 66996.2", \ + "67154.8, 67154.8, 67154.8, 67154.8, 67154.8"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("48290.9, 48290.9, 48290.9, 50186.7, 53978.4", \ + "54022.2, 54022.2, 54022.2, 54022.2, 54022.2", \ + "54109.8, 54109.8, 54109.8, 54109.8, 54109.8", \ + "54285.1, 54285.1, 54285.1, 54285.1, 54285.1", \ + "54635.6, 54635.6, 54635.6, 54635.6, 54635.6"); + } + } + internal_power (energy_pos_cout_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__3) { + values ("52645.1, 52645.1, 52645.1, 54541.0, 58332.6", \ + "52698.9, 52698.9, 52698.9, 54594.7, 58386.4", \ + "52747.6, 52747.6, 52747.6, 54643.5, 58435.2", \ + "52831.0, 52831.0, 52831.0, 54726.9, 58518.6", \ + "52996.4, 52996.4, 52996.4, 54892.3, 58683.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("44118.2, 44118.2, 44118.2, 46014.0, 49805.7", \ + "49845.9, 49845.9, 49845.9, 49845.9, 49845.9", \ + "49926.2, 49926.2, 49926.2, 49926.2, 49926.2", \ + "50086.9, 50086.9, 50086.9, 50086.9, 50086.9", \ + "50408.3, 50408.3, 50408.3, 50408.3, 50408.3"); + } + } + } + } + + cell (a2_x2) { + area : 18.00 ; + cell_leakage_power : 3.8 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 4 ; + } + leakage_power () { + when : "i1" ; + value : 4.4 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 3.1 ; + } + pin (i1) { + direction : input ; + capacitance : 576.29 ; + } + pin (i0) { + direction : input ; + capacitance : 564.79 ; + } + pin (q) { + function : "(i0 & i1)" ; + direction : output ; + capacitance : 85.77 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("3183.9, 3183.9, 3183.9, 3507.1, 4054.3", \ + "3185.9, 3185.9, 3185.9, 3509.3, 4056.8", \ + "3192.5, 3192.5, 3192.5, 3516.1, 4063.7", \ + "3208.7, 3208.7, 3208.7, 3532.3, 4079.9", \ + "3234.4, 3234.4, 3234.4, 3558.9, 4107.6"); + } + rise_transition (inslew_load_5x5__0) { + values ("650.5, 650.5, 650.5, 944.7, 1478.3", \ + "650.7, 650.7, 650.7, 945.0, 1478.7", \ + "650.8, 650.8, 650.8, 945.1, 1479.0", \ + "650.8, 650.8, 650.8, 945.1, 1479.1", \ + "651.7, 651.7, 651.7, 946.2, 1480.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("5300.8, 5300.8, 5300.8, 5555.1, 6059.9", \ + "5309.6, 5309.6, 5309.6, 5563.9, 6068.7", \ + "5327.1, 5327.1, 5327.1, 5581.4, 6086.2", \ + "5362.3, 5362.3, 5362.3, 5616.6, 6121.4", \ + "5432.6, 5432.6, 5432.6, 5686.9, 6191.7"); + } + fall_transition (inslew_load_5x5__0) { + values ("1470.6, 1470.6, 1470.6, 1695.5, 2059.0", \ + "1470.6, 1470.6, 1470.6, 1695.5, 2059.0", \ + "1470.6, 1470.6, 1470.6, 1695.5, 2059.0", \ + "1470.6, 1470.6, 1470.6, 1695.5, 2059.0", \ + "1470.6, 1470.6, 1470.6, 1695.6, 2059.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("3778.8, 3778.8, 3778.8, 4137.5, 4751.6", \ + "3773.7, 3773.7, 3773.7, 4132.4, 4746.5", \ + "3763.3, 3763.3, 3763.3, 4122.0, 4736.1", \ + "3742.7, 3742.7, 3742.7, 4101.4, 4715.5", \ + "3704.5, 3704.5, 3704.5, 4062.5, 4676.5"); + } + rise_transition (inslew_load_5x5__0) { + values ("992.3, 992.3, 992.3, 1291.1, 1839.5", \ + "992.3, 992.3, 992.3, 1291.1, 1839.5", \ + "992.3, 992.3, 992.3, 1291.1, 1839.5", \ + "992.3, 992.3, 992.3, 1291.1, 1839.5", \ + "997.1, 997.1, 997.1, 1295.7, 1843.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("6295.6, 6295.6, 6295.6, 6559.6, 6977.2", \ + "6304.3, 6304.3, 6304.3, 6568.3, 6985.9", \ + "6321.9, 6321.9, 6321.9, 6585.9, 7003.5", \ + "6357.1, 6357.1, 6357.1, 6621.1, 7038.7", \ + "6427.4, 6427.4, 6427.4, 6691.4, 7109.0"); + } + fall_transition (inslew_load_5x5__0) { + values ("2078.2, 2078.2, 2078.2, 2232.8, 2522.8", \ + "2078.2, 2078.2, 2078.2, 2232.8, 2522.8", \ + "2078.2, 2078.2, 2078.2, 2232.8, 2522.8", \ + "2078.2, 2078.2, 2078.2, 2232.8, 2522.8", \ + "2078.2, 2078.2, 2078.2, 2232.9, 2522.8"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__0) { + values ("16890.9, 16890.9, 16890.9, 17963.0, 20107.4", \ + "16916.3, 16916.3, 16916.3, 17988.4, 20132.8", \ + "16957.7, 16957.7, 16957.7, 18029.9, 20174.2", \ + "17036.7, 17036.7, 17036.7, 18108.9, 20253.2", \ + "17215.2, 17215.2, 17215.2, 18287.3, 20431.7"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("17871.6, 17871.6, 17871.6, 18943.8, 21088.1", \ + "21149.6, 21149.6, 21149.6, 21149.6, 21149.6", \ + "21272.6, 21272.6, 21272.6, 21272.6, 21272.6", \ + "21518.7, 21518.7, 21518.7, 21518.7, 21518.7", \ + "18794.4, 18794.4, 18794.4, 19866.5, 22010.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__0) { + values ("24724.9, 24724.9, 24724.9, 25797.0, 27941.4", \ + "27958.0, 27958.0, 27958.0, 27958.0, 27958.0", \ + "27991.1, 27991.1, 27991.1, 27991.1, 27991.1", \ + "28057.5, 28057.5, 28057.5, 28057.5, 28057.5", \ + "24982.6, 24982.6, 24982.6, 26054.7, 28199.1"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("22686.3, 22686.3, 22686.3, 23758.5, 25902.8", \ + "25981.6, 25981.6, 25981.6, 25981.6, 25981.6", \ + "26139.2, 26139.2, 26139.2, 26139.2, 26139.2", \ + "26454.5, 26454.5, 26454.5, 26454.5, 26454.5", \ + "23868.5, 23868.5, 23868.5, 24940.7, 27085.0"); + } + } + } + } + + cell (na3_x1) { + area : 18.00 ; + cell_leakage_power : 1.9 ; + leakage_power () { + when : "(i2 & i1 & i0)" ; + value : 2.5 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 2.7 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 2.4 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2)) | (!(i0) & (i1 ^ i2)))" ; + value : 1.4 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 0.46 ; + } + pin (i2) { + direction : input ; + capacitance : 571.88 ; + } + pin (i1) { + direction : input ; + capacitance : 574.08 ; + } + pin (i0) { + direction : input ; + capacitance : 575.23 ; + } + pin (nq) { + function : "((!(i1) | !(i2)) | !(i0))" ; + direction : output ; + capacitance : 113.48 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__27) { + values ("3980.3, 3980.3, 3980.3, 4398.0, 5240.8", \ + "3989.1, 3989.1, 3989.1, 4406.8, 5249.6", \ + "4006.6, 4006.6, 4006.6, 4424.4, 5267.2", \ + "4041.6, 4041.6, 4041.6, 4459.4, 5302.3", \ + "4111.5, 4111.5, 4111.5, 4529.6, 5372.6"); + } + rise_transition (inslew_load_5x5__27) { + values ("3523.9, 3523.9, 3523.9, 4100.9, 5255.1", \ + "3523.9, 3523.9, 3523.9, 4100.9, 5255.1", \ + "3523.9, 3523.9, 3523.9, 4100.9, 5255.1", \ + "3523.9, 3523.9, 3523.9, 4100.9, 5255.1", \ + "3525.1, 3525.1, 3525.1, 4101.7, 5255.4"); + } + cell_fall (inslew_load_5x5__27) { + values ("3368.3, 3368.3, 3368.3, 3629.2, 4160.6", \ + "3357.2, 3357.2, 3357.2, 3618.1, 4149.5", \ + "3335.0, 3335.0, 3335.0, 3595.9, 4127.3", \ + "3290.5, 3290.5, 3290.5, 3551.5, 4083.0", \ + "3201.1, 3201.1, 3201.1, 3462.4, 3994.2"); + } + fall_transition (inslew_load_5x5__27) { + values ("4447.1, 4447.1, 4447.1, 4908.9, 5832.5", \ + "4447.1, 4447.1, 4447.1, 4908.9, 5832.5", \ + "4447.1, 4447.1, 4447.1, 4908.9, 5832.5", \ + "4447.1, 4447.1, 4447.1, 4908.9, 5832.5", \ + "4451.8, 4451.8, 4451.8, 4912.3, 5834.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__27) { + values ("3124.9, 3124.9, 3124.9, 3548.5, 4397.2", \ + "3133.7, 3133.7, 3133.7, 3557.3, 4405.9", \ + "3151.2, 3151.2, 3151.2, 3574.9, 4423.5", \ + "3186.3, 3186.3, 3186.3, 3610.0, 4458.7", \ + "3255.6, 3255.6, 3255.6, 3679.9, 4528.9"); + } + rise_transition (inslew_load_5x5__27) { + values ("2394.0, 2394.0, 2394.0, 2971.1, 4125.3", \ + "2394.0, 2394.0, 2394.0, 2971.1, 4125.3", \ + "2394.0, 2394.0, 2394.0, 2971.1, 4125.3", \ + "2394.0, 2394.0, 2394.0, 2971.1, 4125.3", \ + "2397.7, 2397.7, 2397.7, 2973.3, 4126.0"); + } + cell_fall (inslew_load_5x5__27) { + values ("2307.4, 2307.4, 2307.4, 2576.3, 3117.1", \ + "2302.3, 2302.3, 2302.3, 2571.4, 3112.4", \ + "2293.0, 2293.0, 2293.0, 2562.1, 3103.2", \ + "2276.5, 2276.5, 2276.5, 2545.7, 3086.7", \ + "2239.7, 2239.7, 2239.7, 2511.0, 3053.9"); + } + fall_transition (inslew_load_5x5__27) { + values ("2699.1, 2699.1, 2699.1, 3167.0, 4103.2", \ + "2701.1, 2701.1, 2701.1, 3169.2, 4105.8", \ + "2701.6, 2701.6, 2701.6, 3169.8, 4106.4", \ + "2701.9, 2701.9, 2701.9, 3170.0, 4106.5", \ + "2715.1, 2715.1, 2715.1, 3179.7, 4111.5"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__27) { + values ("2047.9, 2047.9, 2047.9, 2478.9, 3334.9", \ + "2056.7, 2056.7, 2056.7, 2487.7, 3343.7", \ + "2074.3, 2074.3, 2074.3, 2505.3, 3361.2", \ + "2109.3, 2109.3, 2109.3, 2540.4, 3396.4", \ + "2169.2, 2169.2, 2169.2, 2606.8, 3466.2"); + } + rise_transition (inslew_load_5x5__27) { + values ("971.4, 971.4, 971.4, 1548.5, 2702.6", \ + "971.4, 971.4, 971.4, 1548.5, 2702.7", \ + "971.4, 971.4, 971.4, 1548.5, 2702.7", \ + "971.6, 971.6, 971.6, 1548.5, 2702.7", \ + "980.5, 980.5, 980.5, 1556.0, 2705.6"); + } + cell_fall (inslew_load_5x5__27) { + values ("1281.2, 1281.2, 1281.2, 1557.1, 2104.7", \ + "1291.9, 1291.9, 1291.9, 1567.7, 2115.4", \ + "1298.9, 1298.9, 1298.9, 1574.9, 2123.4", \ + "1310.4, 1310.4, 1310.4, 1585.7, 2131.9", \ + "1291.9, 1291.9, 1291.9, 1585.6, 2147.6"); + } + fall_transition (inslew_load_5x5__27) { + values ("979.6, 979.6, 979.6, 1453.6, 2400.9", \ + "1006.5, 1006.5, 1006.5, 1480.4, 2427.8", \ + "1026.3, 1026.3, 1026.3, 1500.7, 2449.4", \ + "1047.0, 1047.0, 1047.0, 1517.1, 2459.9", \ + "1070.7, 1070.7, 1070.7, 1540.5, 2477.2"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__27) { + values ("7716.1, 7716.1, 7716.1, 9134.5, 11971.5", \ + "7794.9, 7794.9, 7794.9, 9213.3, 12050.3", \ + "7952.5, 7952.5, 7952.5, 9371.0, 12207.9", \ + "8267.7, 8267.7, 8267.7, 9686.2, 12523.1", \ + "8898.2, 8898.2, 8898.2, 10316.7, 13153.6"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("12049.2, 12049.2, 12049.2, 13467.7, 16304.6", \ + "12065.8, 12065.8, 12065.8, 13484.3, 16321.2", \ + "12099.0, 12099.0, 12099.0, 13517.5, 16354.4", \ + "12165.4, 12165.4, 12165.4, 13583.9, 16420.8", \ + "12298.1, 12298.1, 12298.1, 13716.6, 16553.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__27) { + values ("4921.6, 4921.6, 4921.6, 6340.1, 9177.0", \ + "4983.1, 4983.1, 4983.1, 6401.6, 9238.5", \ + "5106.1, 5106.1, 5106.1, 6524.6, 9361.5", \ + "5352.2, 5352.2, 5352.2, 6770.6, 9607.6", \ + "5844.2, 5844.2, 5844.2, 7262.7, 10099.6"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("6595.8, 6595.8, 6595.8, 8014.3, 10851.2", \ + "6615.4, 6615.4, 6615.4, 8033.8, 10870.8", \ + "6654.5, 6654.5, 6654.5, 8073.0, 10909.9", \ + "6732.8, 6732.8, 6732.8, 8151.2, 10988.2", \ + "6889.3, 6889.3, 6889.3, 8307.8, 11144.7"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__27) { + values ("1412.9, 1412.9, 1412.9, 2831.4, 5668.3", \ + "1462.5, 1462.5, 1462.5, 2880.9, 5717.9", \ + "1561.6, 1561.6, 1561.6, 2980.0, 5817.0", \ + "1759.8, 1759.8, 1759.8, 3178.3, 6015.2", \ + "2156.3, 2156.3, 2156.3, 3574.7, 6411.6"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("1495.4, 1495.4, 1495.4, 2913.9, 5750.8", \ + "1517.3, 1517.3, 1517.3, 2935.8, 5772.7", \ + "1561.0, 1561.0, 1561.0, 2979.5, 5816.4", \ + "1648.5, 1648.5, 1648.5, 3067.0, 5903.9", \ + "1823.5, 1823.5, 1823.5, 3241.9, 6078.9"); + } + } + } + } + + cell (inv_x8) { + area : 25.20 ; + cell_leakage_power : 8.9 ; + leakage_power () { + when : "i" ; + value : 6.6 ; + } + leakage_power () { + when : "!(i)" ; + value : 11 ; + } + pin (i) { + direction : input ; + capacitance : 3363.04 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 298.01 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__1) { + values ("1260.6, 1260.6, 1260.6, 1403.3, 1686.2", \ + "1269.4, 1269.4, 1269.4, 1412.1, 1695.0", \ + "1287.0, 1287.0, 1287.0, 1429.6, 1712.6", \ + "1319.8, 1319.8, 1319.8, 1463.5, 1747.4", \ + "1341.3, 1341.3, 1341.3, 1499.0, 1799.5"); + } + rise_transition (inslew_load_5x5__1) { + values ("470.3, 470.3, 470.3, 659.7, 1038.4", \ + "470.3, 470.3, 470.3, 659.7, 1038.4", \ + "470.3, 470.3, 470.3, 659.7, 1038.4", \ + "471.6, 471.6, 471.6, 661.1, 1039.3", \ + "485.0, 485.0, 485.0, 680.6, 1060.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("908.5, 908.5, 908.5, 994.8, 1165.9", \ + "917.3, 917.3, 917.3, 1003.6, 1174.7", \ + "934.8, 934.8, 934.8, 1021.1, 1192.3", \ + "960.9, 960.9, 960.9, 1050.2, 1224.7", \ + "940.6, 940.6, 940.6, 1047.6, 1246.8"); + } + fall_transition (inslew_load_5x5__1) { + values ("308.8, 308.8, 308.8, 422.0, 648.5", \ + "308.8, 308.8, 308.8, 422.0, 648.5", \ + "308.9, 308.9, 308.9, 422.1, 648.5", \ + "312.2, 312.2, 312.2, 426.5, 652.8", \ + "329.5, 329.5, 329.5, 453.4, 687.8"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__1) { + values ("3978.5, 3978.5, 3978.5, 7703.6, 15153.9", \ + "4332.0, 4332.0, 4332.0, 8057.2, 15507.5", \ + "5039.2, 5039.2, 5039.2, 8764.4, 16214.7", \ + "6453.6, 6453.6, 6453.6, 10178.7, 17629.0", \ + "9282.2, 9282.2, 9282.2, 13007.4, 20457.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("4008.3, 4008.3, 4008.3, 7733.5, 15183.8", \ + "4191.2, 4191.2, 4191.2, 7916.3, 15366.6", \ + "4556.9, 4556.9, 4556.9, 8282.0, 15732.3", \ + "5288.3, 5288.3, 5288.3, 9013.4, 16463.7", \ + "6751.0, 6751.0, 6751.0, 10476.2, 17926.5"); + } + } + } + } + + cell (inv_x4) { + area : 14.40 ; + cell_leakage_power : 4.2 ; + leakage_power () { + when : "i" ; + value : 2.8 ; + } + leakage_power () { + when : "!(i)" ; + value : 5.6 ; + } + pin (i) { + direction : input ; + capacitance : 1523.46 ; + } + pin (nq) { + function : "!(i)" ; + direction : output ; + capacitance : 139.03 ; + timing (maxd_nq_i_negative_unate) { + related_pin : "i" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__28) { + values ("1270.3, 1270.3, 1270.3, 1426.7, 1737.0", \ + "1279.1, 1279.1, 1279.1, 1435.5, 1745.8", \ + "1296.7, 1296.7, 1296.7, 1453.1, 1763.4", \ + "1329.6, 1329.6, 1329.6, 1487.1, 1798.2", \ + "1352.4, 1352.4, 1352.4, 1524.6, 1852.4"); + } + rise_transition (inslew_load_5x5__28) { + values ("488.5, 488.5, 488.5, 696.4, 1112.1", \ + "488.5, 488.5, 488.5, 696.4, 1112.1", \ + "488.5, 488.5, 488.5, 696.4, 1112.1", \ + "489.9, 489.9, 489.9, 697.8, 1112.9", \ + "504.3, 504.3, 504.3, 718.1, 1134.2"); + } + cell_fall (inslew_load_5x5__28) { + values ("717.9, 717.9, 717.9, 798.2, 957.5", \ + "726.7, 726.7, 726.7, 807.0, 966.3", \ + "743.6, 743.6, 743.6, 824.3, 983.8", \ + "760.8, 760.8, 760.8, 847.0, 1013.1", \ + "709.0, 709.0, 709.0, 818.8, 1016.9"); + } + fall_transition (inslew_load_5x5__28) { + values ("256.6, 256.6, 256.6, 362.2, 573.5", \ + "256.6, 256.6, 256.6, 362.2, 573.5", \ + "257.0, 257.0, 257.0, 362.6, 573.8", \ + "262.9, 262.9, 262.9, 371.0, 582.2", \ + "286.3, 286.3, 286.3, 406.3, 627.9"); + } + } + internal_power (energy_neg_nq_i) { + related_pin : "i" ; + rise_power (energy_inslew_load_5x5__28) { + values ("1877.5, 1877.5, 1877.5, 3615.4, 7091.2", \ + "2052.1, 2052.1, 2052.1, 3790.0, 7265.9", \ + "2401.3, 2401.3, 2401.3, 4139.3, 7615.1", \ + "3099.9, 3099.9, 3099.9, 4837.8, 8313.6", \ + "4496.9, 4496.9, 4496.9, 6234.8, 9710.7"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("1846.2, 1846.2, 1846.2, 3584.1, 7060.0", \ + "1919.4, 1919.4, 1919.4, 3657.3, 7133.2", \ + "2065.8, 2065.8, 2065.8, 3803.7, 7279.6", \ + "2358.6, 2358.6, 2358.6, 4096.5, 7572.4", \ + "2944.2, 2944.2, 2944.2, 4682.1, 8158.0"); + } + } + } + } + + cell (an12_x1) { + area : 18.00 ; + cell_leakage_power : 3 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 2.5 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 3.1 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 3.6 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 2.8 ; + } + pin (i1) { + direction : input ; + capacitance : 441.20 ; + } + pin (i0) { + direction : input ; + capacitance : 716.60 ; + } + pin (q) { + function : "(i1 & !(i0))" ; + direction : output ; + capacitance : 89.52 ; + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__29) { + values ("6704.1, 6704.1, 6704.1, 6968.4, 7502.8", \ + "6712.9, 6712.9, 6712.9, 6977.2, 7511.6", \ + "6730.5, 6730.5, 6730.5, 6994.8, 7529.2", \ + "6765.6, 6765.6, 6765.6, 7030.0, 7564.4", \ + "6831.2, 6831.2, 6831.2, 7095.7, 7630.3"); + } + rise_transition (inslew_load_5x5__29) { + values ("5534.1, 5534.1, 5534.1, 5953.2, 6793.9", \ + "5534.1, 5534.1, 5534.1, 5953.2, 6793.9", \ + "5534.1, 5534.1, 5534.1, 5953.2, 6793.9", \ + "5534.2, 5534.2, 5534.2, 5953.2, 6793.9", \ + "5535.7, 5535.7, 5535.7, 5954.7, 6795.5"); + } + cell_fall (inslew_load_5x5__29) { + values ("6989.2, 6989.2, 6989.2, 7283.5, 7830.8", \ + "6998.0, 6998.0, 6998.0, 7292.3, 7839.6", \ + "7015.6, 7015.6, 7015.6, 7309.9, 7857.2", \ + "7050.8, 7050.8, 7050.8, 7345.1, 7892.4", \ + "7120.7, 7120.7, 7120.7, 7415.1, 7962.5"); + } + fall_transition (inslew_load_5x5__29) { + values ("2762.5, 2762.5, 2762.5, 3053.4, 3609.4", \ + "2762.5, 2762.5, 2762.5, 3053.4, 3609.4", \ + "2762.5, 2762.5, 2762.5, 3053.4, 3609.4", \ + "2762.5, 2762.5, 2762.5, 3053.4, 3609.4", \ + "2762.8, 2762.8, 2762.8, 3053.7, 3609.6"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__29) { + values ("1614.2, 1614.2, 1614.2, 1890.2, 2436.5", \ + "1619.0, 1619.0, 1619.0, 1894.9, 2440.9", \ + "1627.2, 1627.2, 1627.2, 1903.1, 2449.7", \ + "1637.3, 1637.3, 1637.3, 1913.7, 2461.0", \ + "1649.8, 1649.8, 1649.8, 1935.9, 2489.5"); + } + rise_transition (inslew_load_5x5__29) { + values ("958.4, 958.4, 958.4, 1392.3, 2257.8", \ + "969.4, 969.4, 969.4, 1403.1, 2268.0", \ + "983.6, 983.6, 983.6, 1417.4, 2283.2", \ + "989.9, 989.9, 989.9, 1423.7, 2290.1", \ + "1016.6, 1016.6, 1016.6, 1448.9, 2306.4"); + } + cell_fall (inslew_load_5x5__29) { + values ("1667.8, 1667.8, 1667.8, 1874.6, 2284.8", \ + "1676.6, 1676.6, 1676.6, 1883.4, 2293.6", \ + "1694.2, 1694.2, 1694.2, 1901.0, 2311.2", \ + "1728.9, 1728.9, 1728.9, 1936.0, 2346.4", \ + "1776.2, 1776.2, 1776.2, 1992.1, 2411.2"); + } + fall_transition (inslew_load_5x5__29) { + values ("621.3, 621.3, 621.3, 893.7, 1438.5", \ + "621.3, 621.3, 621.3, 893.7, 1438.5", \ + "621.3, 621.3, 621.3, 893.7, 1438.5", \ + "621.8, 621.8, 621.8, 894.1, 1438.6", \ + "631.6, 631.6, 631.6, 906.6, 1449.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__29) { + values ("23099.8, 23099.8, 23099.8, 24218.8, 26456.7", \ + "26479.6, 26479.6, 26479.6, 26479.6, 26479.6", \ + "26525.4, 26525.4, 26525.4, 26525.4, 26525.4", \ + "23260.3, 23260.3, 23260.3, 24379.3, 26617.2", \ + "23454.3, 23454.3, 23454.3, 24573.3, 26811.3"); + } + fall_power (energy_inslew_load_5x5__29) { + values ("22138.7, 22138.7, 22138.7, 23257.7, 25495.7", \ + "25539.7, 25539.7, 25539.7, 25539.7, 25539.7", \ + "25627.9, 25627.9, 25627.9, 25627.9, 25627.9", \ + "25804.3, 25804.3, 25804.3, 25804.3, 25804.3", \ + "22801.5, 22801.5, 22801.5, 23920.5, 26158.4"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__29) { + values ("1140.1, 1140.1, 1140.1, 2259.1, 4497.0", \ + "1183.8, 1183.8, 1183.8, 2302.8, 4540.8", \ + "1271.3, 1271.3, 1271.3, 2390.3, 4628.2", \ + "1446.2, 1446.2, 1446.2, 2565.1, 4803.1", \ + "1795.9, 1795.9, 1795.9, 2914.9, 5152.9"); + } + fall_power (energy_inslew_load_5x5__29) { + values ("1177.8, 1177.8, 1177.8, 2296.8, 4534.7", \ + "1214.1, 1214.1, 1214.1, 2333.0, 4571.0", \ + "1286.5, 1286.5, 1286.5, 2405.5, 4643.5", \ + "1431.5, 1431.5, 1431.5, 2550.5, 4788.4", \ + "1721.4, 1721.4, 1721.4, 2840.4, 5078.4"); + } + } + } + } + + cell (mx2_x2) { + area : 32.40 ; + cell_leakage_power : 5.1 ; + leakage_power () { + when : "(!(i1) & i0 & cmd)" ; + value : 5.1 ; + } + leakage_power () { + when : "(cmd & i1)" ; + value : 5.2 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & cmd)" ; + value : 4.4 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 5.7 ; + } + leakage_power () { + when : "(i1 & !(i0) & !(cmd))" ; + value : 5.6 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & !(cmd))" ; + value : 4.9 ; + } + pin (i1) { + direction : input ; + capacitance : 438.92 ; + } + pin (i0) { + direction : input ; + capacitance : 436.07 ; + } + pin (cmd) { + direction : input ; + capacitance : 864.42 ; + } + pin (q) { + function : "((i1 & (i0 | cmd)) | (i0 & !(cmd)))" ; + direction : output ; + capacitance : 86.05 ; + timing (maxd_q_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("5826.6, 5826.6, 5826.6, 6143.8, 6716.4", \ + "5831.6, 5831.6, 5831.6, 6148.8, 6721.4", \ + "5839.0, 5839.0, 5839.0, 6156.2, 6728.7", \ + "5855.5, 5855.5, 5855.5, 6172.7, 6745.2", \ + "5889.1, 5889.1, 5889.1, 6206.2, 6778.8"); + } + rise_transition (inslew_load_5x5__18) { + values ("2268.1, 2268.1, 2268.1, 2537.4, 3031.8", \ + "2271.0, 2271.0, 2271.0, 2540.3, 3034.6", \ + "2272.0, 2272.0, 2272.0, 2541.2, 3035.5", \ + "2272.4, 2272.4, 2272.4, 2541.6, 3035.8", \ + "2272.7, 2272.7, 2272.7, 2541.9, 3036.1"); + } + cell_fall (inslew_load_5x5__18) { + values ("7231.5, 7231.5, 7231.5, 7471.4, 7945.9", \ + "7234.3, 7234.3, 7234.3, 7474.2, 7948.1", \ + "7243.3, 7243.3, 7243.3, 7483.2, 7955.8", \ + "7255.4, 7255.4, 7255.4, 7495.3, 7967.3", \ + "7284.0, 7284.0, 7284.0, 7523.9, 7995.7"); + } + fall_transition (inslew_load_5x5__18) { + values ("3065.8, 3065.8, 3065.8, 3247.1, 3600.5", \ + "3068.6, 3068.6, 3068.6, 3249.8, 3603.2", \ + "3074.4, 3074.4, 3074.4, 3255.2, 3608.7", \ + "3077.5, 3077.5, 3077.5, 3258.2, 3611.7", \ + "3078.2, 3078.2, 3078.2, 3258.9, 3612.5"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("8334.6, 8334.6, 8334.6, 8623.6, 9164.4", \ + "8329.4, 8329.4, 8329.4, 8618.4, 9159.2", \ + "8319.1, 8319.1, 8319.1, 8608.1, 9148.9", \ + "8298.5, 8298.5, 8298.5, 8587.5, 9128.3", \ + "8257.4, 8257.4, 8257.4, 8546.3, 9087.1"); + } + rise_transition (inslew_load_5x5__18) { + values ("3986.5, 3986.5, 3986.5, 4220.0, 4670.2", \ + "3986.5, 3986.5, 3986.5, 4220.0, 4670.2", \ + "3986.5, 3986.5, 3986.5, 4220.0, 4670.2", \ + "3986.5, 3986.5, 3986.5, 4220.0, 4670.2", \ + "3986.6, 3986.6, 3986.6, 4220.1, 4670.3"); + } + cell_fall (inslew_load_5x5__18) { + values ("10383.6, 10383.6, 10383.6, 10636.4, 11109.3", \ + "10378.2, 10378.2, 10378.2, 10631.0, 11103.9", \ + "10367.5, 10367.5, 10367.5, 10620.3, 11093.2", \ + "10346.1, 10346.1, 10346.1, 10598.9, 11071.8", \ + "10303.2, 10303.2, 10303.2, 10556.0, 11028.9"); + } + fall_transition (inslew_load_5x5__18) { + values ("4939.5, 4939.5, 4939.5, 5060.0, 5338.1", \ + "4939.5, 4939.5, 4939.5, 5060.0, 5338.1", \ + "4939.5, 4939.5, 4939.5, 5060.0, 5338.1", \ + "4939.5, 4939.5, 4939.5, 5060.0, 5338.1", \ + "4939.5, 4939.5, 4939.5, 5060.0, 5338.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("8334.6, 8334.6, 8334.6, 8623.6, 9164.4", \ + "8329.4, 8329.4, 8329.4, 8618.4, 9159.2", \ + "8319.1, 8319.1, 8319.1, 8608.1, 9148.9", \ + "8298.5, 8298.5, 8298.5, 8587.5, 9128.3", \ + "8257.4, 8257.4, 8257.4, 8546.3, 9087.1"); + } + rise_transition (inslew_load_5x5__18) { + values ("3986.5, 3986.5, 3986.5, 4220.0, 4670.2", \ + "3986.5, 3986.5, 3986.5, 4220.0, 4670.2", \ + "3986.5, 3986.5, 3986.5, 4220.0, 4670.2", \ + "3986.5, 3986.5, 3986.5, 4220.0, 4670.2", \ + "3986.6, 3986.6, 3986.6, 4220.1, 4670.3"); + } + cell_fall (inslew_load_5x5__18) { + values ("10383.6, 10383.6, 10383.6, 10636.4, 11109.3", \ + "10378.2, 10378.2, 10378.2, 10631.0, 11103.9", \ + "10367.5, 10367.5, 10367.5, 10620.3, 11093.2", \ + "10346.1, 10346.1, 10346.1, 10598.9, 11071.8", \ + "10303.2, 10303.2, 10303.2, 10556.0, 11028.9"); + } + fall_transition (inslew_load_5x5__18) { + values ("4939.5, 4939.5, 4939.5, 5060.0, 5338.1", \ + "4939.5, 4939.5, 4939.5, 5060.0, 5338.1", \ + "4939.5, 4939.5, 4939.5, 5060.0, 5338.1", \ + "4939.5, 4939.5, 4939.5, 5060.0, 5338.1", \ + "4939.5, 4939.5, 4939.5, 5060.0, 5338.1"); + } + } + timing (maxd_q_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("9174.3, 9174.3, 9174.3, 9487.1, 10056.7", \ + "9183.1, 9183.1, 9183.1, 9495.9, 10065.5", \ + "9200.7, 9200.7, 9200.7, 9513.5, 10083.1", \ + "9235.8, 9235.8, 9235.8, 9548.6, 10118.2", \ + "9305.8, 9305.8, 9305.8, 9618.6, 10188.1"); + } + rise_transition (inslew_load_5x5__18) { + values ("2463.6, 2463.6, 2463.6, 2728.1, 3216.0", \ + "2463.6, 2463.6, 2463.6, 2728.1, 3216.0", \ + "2463.6, 2463.6, 2463.6, 2728.1, 3216.0", \ + "2463.6, 2463.6, 2463.6, 2728.1, 3216.0", \ + "2464.4, 2464.4, 2464.4, 2728.9, 3216.7"); + } + cell_fall (inslew_load_5x5__18) { + values ("9251.0, 9251.0, 9251.0, 9490.9, 9959.6", \ + "9259.8, 9259.8, 9259.8, 9499.7, 9968.4", \ + "9277.4, 9277.4, 9277.4, 9517.3, 9986.0", \ + "9312.6, 9312.6, 9312.6, 9552.5, 10021.2", \ + "9375.7, 9375.7, 9375.7, 9615.6, 10084.2"); + } + fall_transition (inslew_load_5x5__18) { + values ("3092.4, 3092.4, 3092.4, 3272.5, 3626.3", \ + "3092.4, 3092.4, 3092.4, 3272.5, 3626.3", \ + "3092.4, 3092.4, 3092.4, 3272.5, 3626.3", \ + "3092.4, 3092.4, 3092.4, 3272.5, 3626.3", \ + "3092.6, 3092.6, 3092.6, 3272.7, 3626.5"); + } + } + internal_power (energy_pos_q_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__18) { + values ("21682.1, 21682.1, 21682.1, 22757.8, 24909.1", \ + "21699.8, 21699.8, 21699.8, 22775.4, 24926.8", \ + "21724.1, 21724.1, 21724.1, 22799.8, 24951.1", \ + "21769.4, 21769.4, 21769.4, 22845.1, 24996.5", \ + "21859.1, 21859.1, 21859.1, 22934.7, 25086.1"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("22180.1, 22180.1, 22180.1, 23255.8, 25407.1", \ + "22229.3, 22229.3, 22229.3, 23305.0, 25456.3", \ + "22327.7, 22327.7, 22327.7, 23403.3, 25554.7", \ + "22500.5, 22500.5, 22500.5, 23576.1, 25727.5", \ + "22830.4, 22830.4, 22830.4, 23906.0, 26057.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__18) { + values ("31436.0, 31436.0, 31436.0, 32511.7, 34663.0", \ + "34685.9, 34685.9, 34685.9, 34685.9, 34685.9", \ + "34731.7, 34731.7, 34731.7, 34731.7, 34731.7", \ + "34823.3, 34823.3, 34823.3, 34823.3, 34823.3", \ + "31779.6, 31779.6, 31779.6, 32855.3, 35006.6"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("34681.3, 34681.3, 34681.3, 35756.9, 37908.3", \ + "37952.3, 37952.3, 37952.3, 37952.3, 37952.3", \ + "38040.5, 38040.5, 38040.5, 38040.5, 38040.5", \ + "38216.9, 38216.9, 38216.9, 38216.9, 38216.9", \ + "38569.6, 38569.6, 38569.6, 38569.6, 38569.6"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__18) { + values ("31436.0, 31436.0, 31436.0, 32511.7, 34663.0", \ + "34685.9, 34685.9, 34685.9, 34685.9, 34685.9", \ + "34731.7, 34731.7, 34731.7, 34731.7, 34731.7", \ + "34823.3, 34823.3, 34823.3, 34823.3, 34823.3", \ + "31779.6, 31779.6, 31779.6, 32855.3, 35006.6"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("34681.3, 34681.3, 34681.3, 35756.9, 37908.3", \ + "37952.3, 37952.3, 37952.3, 37952.3, 37952.3", \ + "38040.5, 38040.5, 38040.5, 38040.5, 38040.5", \ + "38216.9, 38216.9, 38216.9, 38216.9, 38216.9", \ + "38569.6, 38569.6, 38569.6, 38569.6, 38569.6"); + } + } + internal_power (energy_neg_q_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__18) { + values ("28913.6, 28913.6, 28913.6, 29989.3, 32140.6", \ + "32184.7, 32184.7, 32184.7, 32184.7, 32184.7", \ + "32272.9, 32272.9, 32272.9, 32272.9, 32272.9", \ + "32449.2, 32449.2, 32449.2, 32449.2, 32449.2", \ + "29578.0, 29578.0, 29578.0, 30653.7, 32805.0"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("29146.3, 29146.3, 29146.3, 30221.9, 32373.3", \ + "32396.2, 32396.2, 32396.2, 32396.2, 32396.2", \ + "32442.0, 32442.0, 32442.0, 32442.0, 32442.0", \ + "32534.3, 32534.3, 32534.3, 32534.3, 32534.3", \ + "29511.5, 29511.5, 29511.5, 30587.2, 32738.5"); + } + } + } + } + + cell (oa3ao322_x4) { + area : 43.20 ; + cell_leakage_power : 8.3 ; + leakage_power () { + when : "(i0 & i1 & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 9.5 ; + } + leakage_power () { + when : "(i0 & i1 & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 8.5 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & i1 & i0)" ; + value : 7.5 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & !((i3 & i4 & i5)) & !(i6)) | (!(i2) & i3 & i4 & i5 & !(i6)))) | (!(i1) & i2 & i3 & i4 & i5 & !(i6)))) | (!(i0) & i1 & i2 & i3 & i4 & i5 & !(i6)))" ; + value : 10 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 9.2 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 8.2 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & !(i4) & !(i5) & i6)" ; + value : 8.1 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & !(i3) & !(i4) & !(i5) & !(i6))" ; + value : 7.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & i5 & !(i6)) | (!(i0) & (i1 ^ i2) & i3 & i4 & i5 & !(i6)))" ; + value : 9.4 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & i6) | (!(i1) & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))) | (!(i0) & (i1 ^ i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6)))))" ; + value : 8.4 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & i4 & i5) | i6)) | ((i3 | i4 | i5) & i6))) | (i2 & (i3 | i4 | i5) & i6) | (!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))) | (i1 & ((i2 & (i3 | i4 | i5) & i6) | (!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))) | (i2 & ((!(i3) & (i4 | i5) & i6) | (!(i4) & i5 & i6))))" ; + value : 11 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))) | (!(i0) & (i1 ^ i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6)))))" ; + value : 7.4 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & i6) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & i6))" ; + value : 7.3 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6)) | (!(i0) & (i1 ^ i2) & !(i3) & !(i4) & !(i5) & !(i6)))" ; + value : 6.4 ; + } + leakage_power () { + when : "(!(i6) & i5 & i4 & i3 & !(i2) & !(i1) & !(i0))" ; + value : 8.6 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & (i4 ^ i5) & !(i6)) | (!(i3) & i4 & i5 & !(i6))))" ; + value : 7.6 ; + } + leakage_power () { + when : "((!(i0) & ((!(i1) & ((!(i2) & (i3 | i4 | i5) & i6) | (i3 & (i4 | !(i5)) & i6))) | (!(i2) & i3 & (i4 | !(i5)) & i6))) | (!(i1) & !(i2) & i3 & (i4 | !(i5)) & i6))" ; + value : 12 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6)) | (!(i3) & (i4 ^ i5) & !(i6))))" ; + value : 6.7 ; + } + leakage_power () { + when : "(i6 & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 6.5 ; + } + leakage_power () { + when : "(!(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.7 ; + } + pin (i6) { + direction : input ; + capacitance : 514.62 ; + } + pin (i5) { + direction : input ; + capacitance : 544.97 ; + } + pin (i4) { + direction : input ; + capacitance : 545.27 ; + } + pin (i3) { + direction : input ; + capacitance : 545.57 ; + } + pin (i2) { + direction : input ; + capacitance : 538.60 ; + } + pin (i1) { + direction : input ; + capacitance : 541.15 ; + } + pin (i0) { + direction : input ; + capacitance : 541.75 ; + } + pin (q) { + function : "(((i5 | i4 | i3) & ((i0 & i1 & i2) | i6)) | (i0 & i1 & i2))" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("15252.9, 15252.9, 15252.9, 15491.4, 15958.0", \ + "15241.8, 15241.8, 15241.8, 15480.3, 15946.9", \ + "15219.7, 15219.7, 15219.7, 15458.2, 15924.8", \ + "15175.3, 15175.3, 15175.3, 15413.8, 15880.4", \ + "15086.7, 15086.7, 15086.7, 15325.2, 15791.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("9099.8, 9099.8, 9099.8, 9291.6, 9671.2", \ + "9099.8, 9099.8, 9099.8, 9291.6, 9671.2", \ + "9099.8, 9099.8, 9099.8, 9291.6, 9671.2", \ + "9099.8, 9099.8, 9099.8, 9291.6, 9671.2", \ + "9099.8, 9099.8, 9099.8, 9291.6, 9671.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("27571.7, 27571.7, 27571.7, 27779.7, 28192.1", \ + "27560.8, 27560.8, 27560.8, 27768.8, 28181.2", \ + "27539.0, 27539.0, 27539.0, 27747.0, 28159.4", \ + "27495.4, 27495.4, 27495.4, 27703.4, 28115.8", \ + "27408.2, 27408.2, 27408.2, 27616.2, 28028.6"); + } + fall_transition (inslew_load_5x5__3) { + values ("17526.4, 17526.4, 17526.4, 17667.2, 17956.7", \ + "17526.4, 17526.4, 17526.4, 17667.2, 17956.7", \ + "17526.4, 17526.4, 17526.4, 17667.2, 17956.7", \ + "17526.4, 17526.4, 17526.4, 17667.2, 17956.7", \ + "17526.4, 17526.4, 17526.4, 17667.2, 17956.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("13832.1, 13832.1, 13832.1, 14071.6, 14536.8", \ + "13828.8, 13828.8, 13828.8, 14068.3, 14533.5", \ + "13819.9, 13819.9, 13819.9, 14059.4, 14524.6", \ + "13803.6, 13803.6, 13803.6, 14043.1, 14508.3", \ + "13771.5, 13771.5, 13771.5, 14011.0, 14476.2"); + } + rise_transition (inslew_load_5x5__3) { + values ("8182.8, 8182.8, 8182.8, 8376.8, 8755.8", \ + "8184.9, 8184.9, 8184.9, 8378.8, 8757.8", \ + "8185.3, 8185.3, 8185.3, 8379.2, 8758.3", \ + "8185.4, 8185.4, 8185.4, 8379.4, 8758.4", \ + "8185.3, 8185.3, 8185.3, 8379.2, 8758.3"); + } + cell_fall (inslew_load_5x5__3) { + values ("26741.6, 26741.6, 26741.6, 26949.7, 27362.0", \ + "26730.7, 26730.7, 26730.7, 26938.8, 27351.1", \ + "26708.9, 26708.9, 26708.9, 26917.0, 27329.3", \ + "26665.3, 26665.3, 26665.3, 26873.4, 27285.7", \ + "26578.1, 26578.1, 26578.1, 26786.2, 27198.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("16955.1, 16955.1, 16955.1, 17096.6, 17387.6", \ + "16955.1, 16955.1, 16955.1, 17096.6, 17387.6", \ + "16955.1, 16955.1, 16955.1, 17096.6, 17387.6", \ + "16955.1, 16955.1, 16955.1, 17096.6, 17387.6", \ + "16955.1, 16955.1, 16955.1, 17096.6, 17387.6"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("12450.5, 12450.5, 12450.5, 12690.4, 13152.9", \ + "12469.0, 12469.0, 12469.0, 12708.9, 13171.5", \ + "12485.5, 12485.5, 12485.5, 12725.4, 13188.1", \ + "12491.5, 12491.5, 12491.5, 12731.4, 13194.1", \ + "12517.1, 12517.1, 12517.1, 12757.0, 13219.7"); + } + rise_transition (inslew_load_5x5__3) { + values ("7292.4, 7292.4, 7292.4, 7485.4, 7866.0", \ + "7308.6, 7308.6, 7308.6, 7501.6, 7882.1", \ + "7323.1, 7323.1, 7323.1, 7516.1, 7896.6", \ + "7325.5, 7325.5, 7325.5, 7518.5, 7899.0", \ + "7329.3, 7329.3, 7329.3, 7522.3, 7902.8"); + } + cell_fall (inslew_load_5x5__3) { + values ("25534.2, 25534.2, 25534.2, 25742.2, 26154.5", \ + "25523.3, 25523.3, 25523.3, 25731.3, 26143.6", \ + "25501.5, 25501.5, 25501.5, 25709.5, 26121.8", \ + "25457.9, 25457.9, 25457.9, 25665.9, 26078.2", \ + "25370.7, 25370.7, 25370.7, 25578.7, 25991.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("16124.6, 16124.6, 16124.6, 16266.9, 16560.4", \ + "16124.6, 16124.6, 16124.6, 16266.9, 16560.4", \ + "16124.6, 16124.6, 16124.6, 16266.9, 16560.4", \ + "16124.6, 16124.6, 16124.6, 16266.9, 16560.4", \ + "16124.6, 16124.6, 16124.6, 16266.9, 16560.4"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("12696.5, 12696.5, 12696.5, 12936.6, 13397.0", \ + "12697.0, 12697.0, 12697.0, 12937.1, 13397.5", \ + "12698.1, 12698.1, 12698.1, 12938.2, 13398.6", \ + "12700.1, 12700.1, 12700.1, 12940.2, 13400.6", \ + "12704.3, 12704.3, 12704.3, 12944.4, 13404.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("6763.3, 6763.3, 6763.3, 6955.7, 7337.0", \ + "6763.3, 6763.3, 6763.3, 6955.7, 7337.0", \ + "6763.3, 6763.3, 6763.3, 6955.7, 7337.0", \ + "6763.3, 6763.3, 6763.3, 6955.7, 7337.0", \ + "6763.3, 6763.3, 6763.3, 6955.7, 7337.0"); + } + cell_fall (inslew_load_5x5__3) { + values ("14176.7, 14176.7, 14176.7, 14393.9, 14819.2", \ + "14212.9, 14212.9, 14212.9, 14430.0, 14856.2", \ + "14178.6, 14178.6, 14178.6, 14395.8, 14821.9", \ + "14254.0, 14254.0, 14254.0, 14471.0, 14897.6", \ + "14284.4, 14284.4, 14284.4, 14501.3, 14928.3"); + } + fall_transition (inslew_load_5x5__3) { + values ("8745.2, 8745.2, 8745.2, 8918.8, 9240.4", \ + "8778.2, 8778.2, 8778.2, 8952.0, 9273.3", \ + "8769.0, 8769.0, 8769.0, 8942.6, 9264.1", \ + "8848.0, 8848.0, 8848.0, 9021.9, 9343.2", \ + "8911.2, 8911.2, 8911.2, 9085.4, 9406.3"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("14485.3, 14485.3, 14485.3, 14725.2, 15190.1", \ + "14485.8, 14485.8, 14485.8, 14725.7, 15190.6", \ + "14486.8, 14486.8, 14486.8, 14726.7, 15191.6", \ + "14488.9, 14488.9, 14488.9, 14728.8, 15193.7", \ + "14493.1, 14493.1, 14493.1, 14733.0, 15197.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("7931.1, 7931.1, 7931.1, 8125.3, 8504.7", \ + "7931.1, 7931.1, 7931.1, 8125.3, 8504.7", \ + "7931.1, 7931.1, 7931.1, 8125.3, 8504.7", \ + "7931.1, 7931.1, 7931.1, 8125.3, 8504.7", \ + "7931.1, 7931.1, 7931.1, 8125.3, 8504.7"); + } + cell_fall (inslew_load_5x5__3) { + values ("18216.2, 18216.2, 18216.2, 18047.0, 18474.1", \ + "17806.8, 17806.8, 17806.8, 18021.0, 18448.1", \ + "18202.0, 18202.0, 18202.0, 18032.5, 18459.6", \ + "18181.3, 18181.3, 18181.3, 18011.8, 18438.9", \ + "18177.3, 18177.3, 18177.3, 18006.5, 18433.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("11422.0, 11422.0, 11422.0, 11332.1, 11660.2", \ + "11154.7, 11154.7, 11154.7, 11322.8, 11650.9", \ + "11427.7, 11427.7, 11427.7, 11347.5, 11675.6", \ + "11448.9, 11448.9, 11448.9, 11363.2, 11691.5", \ + "11492.8, 11492.8, 11492.8, 11409.1, 11737.4"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("15369.5, 15369.5, 15369.5, 15608.7, 16074.4", \ + "15370.0, 15370.0, 15370.0, 15609.2, 16074.9", \ + "15371.0, 15371.0, 15371.0, 15610.2, 16075.9", \ + "15373.1, 15373.1, 15373.1, 15612.3, 16078.0", \ + "15377.3, 15377.3, 15377.3, 15616.5, 16082.2"); + } + rise_transition (inslew_load_5x5__3) { + values ("8507.6, 8507.6, 8507.6, 8700.7, 9079.9", \ + "8507.6, 8507.6, 8507.6, 8700.7, 9079.9", \ + "8507.6, 8507.6, 8507.6, 8700.7, 9079.9", \ + "8507.6, 8507.6, 8507.6, 8700.7, 9079.9", \ + "8507.6, 8507.6, 8507.6, 8700.7, 9079.9"); + } + cell_fall (inslew_load_5x5__3) { + values ("21973.6, 21973.6, 21973.6, 22180.9, 22590.3", \ + "21968.4, 21968.4, 21968.4, 22175.7, 22585.2", \ + "21942.6, 21942.6, 21942.6, 22149.9, 22559.4", \ + "21912.2, 21912.2, 21912.2, 22119.5, 22529.1", \ + "21844.1, 21844.1, 21844.1, 22051.4, 22461.2"); + } + fall_transition (inslew_load_5x5__3) { + values ("13883.9, 13883.9, 13883.9, 14029.5, 14328.7", \ + "13890.0, 13890.0, 13890.0, 14035.8, 14334.9", \ + "13891.2, 13891.2, 13891.2, 14036.9, 14336.4", \ + "13905.3, 13905.3, 13905.3, 14050.9, 14350.2", \ + "13920.9, 13920.9, 13920.9, 14066.6, 14366.2"); + } + } + timing (maxd_q_i6_positive_unate) { + related_pin : "i6" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("10949.9, 10949.9, 10949.9, 11189.3, 11648.2", \ + "10962.2, 10962.2, 10962.2, 11201.7, 11660.6", \ + "10972.9, 10972.9, 10972.9, 11212.3, 11671.2", \ + "10978.6, 10978.6, 10978.6, 11218.1, 11677.0", \ + "10991.5, 10991.5, 10991.5, 11230.9, 11689.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("5724.8, 5724.8, 5724.8, 5919.6, 6308.3", \ + "5736.2, 5736.2, 5736.2, 5930.9, 6319.4", \ + "5746.6, 5746.6, 5746.6, 5941.3, 6329.8", \ + "5750.8, 5750.8, 5750.8, 5945.5, 6333.9", \ + "5751.4, 5751.4, 5751.4, 5946.1, 6334.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("10551.1, 10551.1, 10551.1, 10878.5, 11302.8", \ + "10560.3, 10560.3, 10560.3, 10888.8, 11313.2", \ + "10561.2, 10561.2, 10561.2, 10890.3, 11314.8", \ + "10580.0, 10580.0, 10580.0, 10911.2, 11335.8", \ + "10602.7, 10602.7, 10602.7, 10935.6, 11360.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("5176.9, 5176.9, 5176.9, 5321.6, 5549.1", \ + "5185.3, 5185.3, 5185.3, 5330.6, 5557.8", \ + "5190.2, 5190.2, 5190.2, 5335.8, 5562.8", \ + "5207.1, 5207.1, 5207.1, 5353.9, 5580.4", \ + "5221.5, 5221.5, 5221.5, 5369.4, 5595.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("98485.5, 98485.5, 98485.5, 100381.3, 104173.0", \ + "104194.6, 104194.6, 104194.6, 104194.6, 104194.6", \ + "104237.6, 104237.6, 104237.6, 104237.6, 104237.6", \ + "104323.8, 104323.8, 104323.8, 104323.8, 104323.8", \ + "104496.1, 104496.1, 104496.1, 104496.1, 104496.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("157525.3, 157525.3, 157525.3, 159421.2, 163212.8", \ + "163280.7, 163280.7, 163280.7, 163280.7, 163280.7", \ + "163416.4, 163416.4, 163416.4, 163416.4, 163416.4", \ + "163687.9, 163687.9, 163687.9, 163687.9, 163687.9", \ + "164230.7, 164230.7, 164230.7, 164230.7, 164230.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("88519.4, 88519.4, 88519.4, 90415.2, 94206.9", \ + "88556.5, 88556.5, 88556.5, 90452.4, 94244.0", \ + "88608.9, 88608.9, 88608.9, 90504.7, 94296.4", \ + "88708.6, 88708.6, 88708.6, 90604.4, 94396.1", \ + "94594.1, 94594.1, 94594.1, 94594.1, 94594.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("152275.3, 152275.3, 152275.3, 154171.1, 157962.8", \ + "158013.7, 158013.7, 158013.7, 158013.7, 158013.7", \ + "158115.5, 158115.5, 158115.5, 158115.5, 158115.5", \ + "158319.0, 158319.0, 158319.0, 158319.0, 158319.0", \ + "158725.9, 158725.9, 158725.9, 158725.9, 158725.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("79043.3, 79043.3, 79043.3, 80939.1, 84730.8", \ + "79167.2, 79167.2, 79167.2, 81063.1, 84854.7", \ + "79308.0, 79308.0, 79308.0, 81203.8, 84995.5", \ + "79429.3, 79429.3, 79429.3, 81325.2, 85116.8", \ + "79666.0, 79666.0, 79666.0, 81561.9, 85353.5"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("144655.2, 144655.2, 144655.2, 146551.0, 150342.7", \ + "150382.7, 150382.7, 150382.7, 150382.7, 150382.7", \ + "150462.7, 150462.7, 150462.7, 150462.7, 150462.7", \ + "150622.7, 150622.7, 150622.7, 150622.7, 150622.7", \ + "150942.7, 150942.7, 150942.7, 150942.7, 150942.7"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__3) { + values ("70211.5, 70211.5, 70211.5, 72107.4, 75899.0", \ + "75912.6, 75912.6, 75912.6, 75912.6, 75912.6", \ + "75939.9, 75939.9, 75939.9, 75939.9, 75939.9", \ + "75994.3, 75994.3, 75994.3, 75994.3, 75994.3", \ + "76103.2, 76103.2, 76103.2, 76103.2, 76103.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("79027.7, 79027.7, 79027.7, 80923.5, 84715.2", \ + "79268.4, 79268.4, 79268.4, 81164.2, 84955.9", \ + "79280.1, 79280.1, 79280.1, 81175.9, 84967.6", \ + "79910.9, 79910.9, 79910.9, 81806.7, 85598.4", \ + "80581.5, 80581.5, 80581.5, 82477.4, 86269.0"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__3) { + values ("81432.1, 81432.1, 81432.1, 83327.9, 87119.6", \ + "87137.2, 87137.2, 87137.2, 87137.2, 87137.2", \ + "87172.4, 87172.4, 87172.4, 87172.4, 87172.4", \ + "87242.8, 87242.8, 87242.8, 87242.8, 87242.8", \ + "87383.6, 87383.6, 87383.6, 87383.6, 87383.6"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("101350.3, 101350.3, 101350.3, 103246.2, 107037.8", \ + "101327.8, 101327.8, 101327.8, 103223.6, 107015.3", \ + "101552.0, 101552.0, 101552.0, 103447.8, 107239.5", \ + "101790.8, 101790.8, 101790.8, 103686.7, 107478.3", \ + "102358.8, 102358.8, 102358.8, 104254.7, 108046.3"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__3) { + values ("87031.9, 87031.9, 87031.9, 88927.8, 92719.4", \ + "92743.1, 92743.1, 92743.1, 92743.1, 92743.1", \ + "92790.5, 92790.5, 92790.5, 92790.5, 92790.5", \ + "92885.4, 92885.4, 92885.4, 92885.4, 92885.4", \ + "93075.0, 93075.0, 93075.0, 93075.0, 93075.0"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("124218.5, 124218.5, 124218.5, 126114.3, 129906.0", \ + "124291.9, 124291.9, 124291.9, 126187.7, 129979.4", \ + "124368.9, 124368.9, 124368.9, 126264.8, 130056.4", \ + "124596.7, 124596.7, 124596.7, 126492.6, 130284.3", \ + "124974.1, 124974.1, 124974.1, 126870.0, 130661.6"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__3) { + values ("60663.1, 60663.1, 60663.1, 62558.9, 66350.6", \ + "60748.7, 60748.7, 60748.7, 62644.5, 66436.2", \ + "60849.2, 60849.2, 60849.2, 62745.0, 66536.7", \ + "60953.0, 60953.0, 60953.0, 62848.8, 66640.5", \ + "61115.3, 61115.3, 61115.3, 63011.1, 66802.8"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("54941.2, 54941.2, 54941.2, 56837.0, 60628.7", \ + "55025.8, 55025.8, 55025.8, 56921.7, 60713.4", \ + "55122.5, 55122.5, 55122.5, 57018.4, 60810.1", \ + "55359.6, 55359.6, 55359.6, 57255.5, 61047.2", \ + "55716.4, 55716.4, 55716.4, 57612.3, 61404.0"); + } + } + } + } + + cell (oa2a2a2a24_x4) { + area : 57.60 ; + cell_leakage_power : 20 ; + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))) | (!(i0) & i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))))" ; + value : 14 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((!(i3) & ((i4 & ((!(i5) & (i6 | i7)) | (i6 ^ i7))) | (!(i4) & i5 & (i6 | i7)))) | ((i4 ^ i5) & (i6 ^ i7)))) | (!(i2) & i3 & ((i4 & ((!(i5) & (i6 | i7)) | (i6 ^ i7))) | (!(i4) & i5 & (i6 | i7)))))) | (!(i1) & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))) | (i2 & i3 & (i4 ^ i5) & (i6 ^ i7)))))" ; + value : 29 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & !(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i2) & ((i3 & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))) | (!(i3) & !(i4) & i5 & !(i6) & i7))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))))))" ; + value : 13 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i0) & ((i1 & (i2 ^ i3) & i4 & i5 & i6 & i7) | (!(i1) & (i2 ^ i3) & !((i4 & i5)) & i6 & i7))))" ; + value : 31 ; + } + leakage_power () { + when : "((!((i0 | i1)) & i4 & i5 & i6 & i7) | (i2 & i3 & i4 & i5 & i6 & i7))" ; + value : 32 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & (((i2 | i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!((i2 | i3)) & i6 & i7))))) | (!(i0) & ((i1 & (((i2 | i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!((i2 | i3)) & i6 & i7))) | (!(i1) & ((i2 & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))" ; + value : 30 ; + } + leakage_power () { + when : "((i0 & i1 & (!((i2 | i3)) | !((i4 | i5)) | (!(i6) & !(i7)))) | (i2 & i3 & (!((i4 | i5)) | (!(i6) & !(i7)))) | (i4 & i5 & !(i6) & !(i7)))" ; + value : 28 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))))))))))" ; + value : 11 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))))))) | (!(i0) & ((i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i2) & ((i3 & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))) | (!(i3) & !(i4) & i5 & !(i6) & i7))))))))" ; + value : 12 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & !(i2) & !(i3) & !((i4 & i5)) & i6 & i7)" ; + value : 33 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7))))))))" ; + value : 9.9 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & !(i3) & !(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))))" ; + value : 10 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 8.9 ; + } + pin (i7) { + direction : input ; + capacitance : 846.52 ; + } + pin (i6) { + direction : input ; + capacitance : 845.97 ; + } + pin (i5) { + direction : input ; + capacitance : 843.97 ; + } + pin (i4) { + direction : input ; + capacitance : 843.97 ; + } + pin (i3) { + direction : input ; + capacitance : 843.97 ; + } + pin (i2) { + direction : input ; + capacitance : 844.87 ; + } + pin (i1) { + direction : input ; + capacitance : 842.97 ; + } + pin (i0) { + direction : input ; + capacitance : 846.36 ; + } + pin (q) { + function : "((i6 & ((i5 & ((i2 & ((i0 & i1) | i3 | i4 | i7)) | (i0 & i1) | i4 | i7)) | (i2 & ((i0 & i1) | i3 | i7)) | (i0 & i1) | i7)) | (i5 & ((i2 & ((i0 & i1) | i3 | i4)) | (i0 & i1) | i4)) | (i2 & ((i0 & i1) | i3)) | (i0 & i1))" ; + direction : output ; + capacitance : 151.95 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("10681.3, 10681.3, 10681.3, 10921.4, 11383.0", \ + "10676.2, 10676.2, 10676.2, 10916.3, 11377.9", \ + "10665.9, 10665.9, 10665.9, 10906.0, 11367.6", \ + "10645.2, 10645.2, 10645.2, 10885.3, 11346.9", \ + "10604.0, 10604.0, 10604.0, 10844.1, 11305.7"); + } + rise_transition (inslew_load_5x5__14) { + values ("5514.8, 5514.8, 5514.8, 5710.7, 6102.0", \ + "5514.8, 5514.8, 5514.8, 5710.7, 6102.0", \ + "5514.8, 5514.8, 5514.8, 5710.7, 6102.0", \ + "5514.8, 5514.8, 5514.8, 5710.7, 6102.0", \ + "5514.8, 5514.8, 5514.8, 5710.7, 6102.0"); + } + cell_fall (inslew_load_5x5__14) { + values ("23486.2, 23486.2, 23486.2, 23696.7, 24112.0", \ + "23471.4, 23471.4, 23471.4, 23681.9, 24097.2", \ + "23441.9, 23441.9, 23441.9, 23652.4, 24067.7", \ + "23382.7, 23382.7, 23382.7, 23593.2, 24008.5", \ + "23264.5, 23264.5, 23264.5, 23475.0, 23890.3"); + } + fall_transition (inslew_load_5x5__14) { + values ("14352.2, 14352.2, 14352.2, 14495.2, 14796.3", \ + "14352.2, 14352.2, 14352.2, 14495.2, 14796.3", \ + "14352.2, 14352.2, 14352.2, 14495.2, 14796.3", \ + "14352.2, 14352.2, 14352.2, 14495.2, 14796.3", \ + "14352.2, 14352.2, 14352.2, 14495.2, 14796.3"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("9544.7, 9544.7, 9544.7, 9789.3, 10271.1", \ + "9549.6, 9549.6, 9549.6, 9794.1, 10275.9", \ + "9556.7, 9556.7, 9556.7, 9801.2, 10282.9", \ + "9573.3, 9573.3, 9573.3, 9817.8, 10299.6", \ + "9607.0, 9607.0, 9607.0, 9851.5, 10333.3"); + } + rise_transition (inslew_load_5x5__14) { + values ("4820.7, 4820.7, 4820.7, 5020.9, 5412.9", \ + "4823.1, 4823.1, 4823.1, 5023.2, 5415.2", \ + "4823.5, 4823.5, 4823.5, 5023.7, 5415.7", \ + "4823.8, 4823.8, 4823.8, 5024.0, 5416.0", \ + "4823.8, 4823.8, 4823.8, 5024.0, 5416.0"); + } + cell_fall (inslew_load_5x5__14) { + values ("22459.6, 22459.6, 22459.6, 22669.4, 23082.1", \ + "22444.8, 22444.8, 22444.8, 22654.6, 23067.3", \ + "22415.3, 22415.3, 22415.3, 22625.1, 23037.8", \ + "22356.2, 22356.2, 22356.2, 22566.0, 22978.7", \ + "22237.9, 22237.9, 22237.9, 22447.7, 22860.4"); + } + fall_transition (inslew_load_5x5__14) { + values ("13661.3, 13661.3, 13661.3, 13805.7, 14107.1", \ + "13661.3, 13661.3, 13661.3, 13805.7, 14107.1", \ + "13661.3, 13661.3, 13661.3, 13805.7, 14107.1", \ + "13661.3, 13661.3, 13661.3, 13805.7, 14107.1", \ + "13661.3, 13661.3, 13661.3, 13805.7, 14107.1"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + 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(energy_inslew_load_5x5__14) { + values ("81661.1, 81661.1, 81661.1, 83560.4, 87359.1", \ + "87387.8, 87387.8, 87387.8, 87387.8, 87387.8", \ + "87445.3, 87445.3, 87445.3, 87445.3, 87445.3", \ + "87560.4, 87560.4, 87560.4, 87560.4, 87560.4", \ + "87790.4, 87790.4, 87790.4, 87790.4, 87790.4"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("123775.4, 123775.4, 123775.4, 125674.7, 129473.4", \ + "123884.6, 123884.6, 123884.6, 125784.0, 129582.6", \ + "124066.2, 124066.2, 124066.2, 125965.6, 129764.2", \ + "124456.3, 124456.3, 124456.3, 126355.6, 130154.3", \ + "125184.4, 125184.4, 125184.4, 127083.8, 130882.5"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__14) { + values ("72026.8, 72026.8, 72026.8, 73926.1, 77724.8", \ + "72073.0, 72073.0, 72073.0, 73972.3, 77771.0", \ + "72141.0, 72141.0, 72141.0, 74040.3, 77839.0", \ + "72273.8, 72273.8, 72273.8, 74173.1, 77971.8", \ + "78233.8, 78233.8, 78233.8, 78233.8, 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90200.4, 92099.8, 95898.4"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__14) { + values ("70564.7, 70564.7, 70564.7, 72464.1, 76262.7", \ + "76282.5, 76282.5, 76282.5, 76282.5, 76282.5", \ + "76322.0, 76322.0, 76322.0, 76322.0, 76322.0", \ + "76401.1, 76401.1, 76401.1, 76401.1, 76401.1", \ + "70861.5, 70861.5, 70861.5, 72760.8, 76559.5"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("96220.8, 96220.8, 96220.8, 98120.2, 101918.8", \ + "96400.7, 96400.7, 96400.7, 98300.0, 102098.7", \ + "96704.9, 96704.9, 96704.9, 98604.2, 102402.9", \ + "97099.7, 97099.7, 97099.7, 98999.1, 102797.7", \ + "98042.8, 98042.8, 98042.8, 99942.2, 103740.8"); + } + } + internal_power (energy_pos_q_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__14) { + values ("43905.1, 43905.1, 43905.1, 45804.5, 49603.1", \ + "43934.8, 43934.8, 43934.8, 45834.1, 49632.8", \ + "43973.7, 43973.7, 43973.7, 45873.0, 49671.7", \ + "44043.9, 44043.9, 44043.9, 45943.2, 49741.9", \ + "44183.7, 44183.7, 44183.7, 46083.1, 49881.7"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("60200.2, 60200.2, 60200.2, 62099.6, 65898.2", \ + "60539.7, 60539.7, 60539.7, 62439.1, 66237.8", \ + "61048.0, 61048.0, 61048.0, 62947.3, 66746.0", \ + "61846.7, 61846.7, 61846.7, 63746.0, 67544.7", \ + "62692.4, 62692.4, 62692.4, 64591.8, 68390.5"); + } + } + internal_power (energy_pos_q_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__14) { + values ("53756.7, 53756.7, 53756.7, 55656.1, 59454.7", \ + "59469.3, 59469.3, 59469.3, 59469.3, 59469.3", \ + "59498.4, 59498.4, 59498.4, 59498.4, 59498.4", \ + "59556.5, 59556.5, 59556.5, 59556.5, 59556.5", \ + "53975.9, 53975.9, 53975.9, 55875.3, 59673.9"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("67849.8, 67849.8, 67849.8, 69749.2, 73547.8", \ + "68204.0, 68204.0, 68204.0, 70103.3, 73902.0", \ + "68742.1, 68742.1, 68742.1, 70641.5, 74440.1", \ + "69602.3, 69602.3, 69602.3, 71501.6, 75300.3", \ + "70573.7, 70573.7, 70573.7, 72473.1, 76271.8"); + } + } + } + } + + cell (mx2_x4) { + area : 36.00 ; + cell_leakage_power : 7.2 ; + leakage_power () { + when : "(!(i1) & i0 & cmd)" ; + value : 6.7 ; + } + leakage_power () { + when : "(cmd & i1)" ; + value : 7.9 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & cmd)" ; + value : 6 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 8.5 ; + } + leakage_power () { + when : "(i1 & !(i0) & !(cmd))" ; + value : 7.3 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & !(cmd))" ; + value : 6.6 ; + } + pin (i1) { + direction : input ; + capacitance : 438.92 ; + } + pin (i0) { + direction : input ; + capacitance : 436.07 ; + } + pin (cmd) { + direction : input ; + capacitance : 864.42 ; + } + pin (q) { + function : "((i1 & (i0 | cmd)) | (i0 & !(cmd)))" ; + direction : output ; + capacitance : 151.95 ; + timing (maxd_q_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("10278.1, 10278.1, 10278.1, 10518.1, 10986.8", \ + "10282.9, 10282.9, 10282.9, 10523.0, 10991.6", \ + "10289.7, 10289.7, 10289.7, 10529.7, 10998.3", \ + "10306.4, 10306.4, 10306.4, 10546.4, 11015.0", \ + "10340.0, 10340.0, 10340.0, 10580.0, 11048.6"); + } + rise_transition (inslew_load_5x5__14) { + values ("5326.2, 5326.2, 5326.2, 5523.2, 5914.2", \ + "5328.7, 5328.7, 5328.7, 5525.6, 5916.7", \ + "5329.1, 5329.1, 5329.1, 5526.1, 5917.2", \ + "5329.6, 5329.6, 5329.6, 5526.5, 5917.6", \ + "5329.6, 5329.6, 5329.6, 5526.5, 5917.6"); + } + cell_fall (inslew_load_5x5__14) { + values ("11626.6, 11626.6, 11626.6, 11927.3, 12469.7", \ + "11628.8, 11628.8, 11628.8, 11929.6, 12472.3", \ + "11636.9, 11636.9, 11636.9, 11937.9, 12481.0", \ + "11648.7, 11648.7, 11648.7, 11949.9, 12493.3", \ + "11676.7, 11676.7, 11676.7, 11977.9, 12521.3"); + } + fall_transition (inslew_load_5x5__14) { + values ("5848.9, 5848.9, 5848.9, 6005.4, 6252.8", \ + "5851.5, 5851.5, 5851.5, 6008.1, 6255.6", \ + "5857.0, 5857.0, 5857.0, 6013.8, 6261.4", \ + "5860.1, 5860.1, 5860.1, 6017.1, 6264.7", \ + "5860.5, 5860.5, 5860.5, 6017.5, 6265.1"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("12519.6, 12519.6, 12519.6, 12760.2, 13221.2", \ + "12514.4, 12514.4, 12514.4, 12755.0, 13216.0", \ + "12504.1, 12504.1, 12504.1, 12744.7, 13205.7", \ + "12483.5, 12483.5, 12483.5, 12724.1, 13185.1", \ + "12442.2, 12442.2, 12442.2, 12682.8, 13143.8"); + } + rise_transition (inslew_load_5x5__14) { + values ("6728.2, 6728.2, 6728.2, 6921.0, 7302.8", \ + "6728.2, 6728.2, 6728.2, 6921.0, 7302.8", \ + "6728.2, 6728.2, 6728.2, 6921.0, 7302.8", \ + "6728.2, 6728.2, 6728.2, 6921.0, 7302.8", \ + "6728.2, 6728.2, 6728.2, 6921.0, 7302.8"); + } + cell_fall (inslew_load_5x5__14) { + values ("14546.2, 14546.2, 14546.2, 14762.3, 15282.9", \ + "14540.8, 14540.8, 14540.8, 14756.9, 15277.5", \ + "14530.1, 14530.1, 14530.1, 14746.2, 15266.8", \ + "14508.7, 14508.7, 14508.7, 14724.8, 15245.4", \ + "14465.8, 14465.8, 14465.8, 14681.9, 15202.5"); + } + fall_transition (inslew_load_5x5__14) { + values ("7442.3, 7442.3, 7442.3, 7610.5, 7919.4", \ + "7442.3, 7442.3, 7442.3, 7610.5, 7919.4", \ + "7442.3, 7442.3, 7442.3, 7610.5, 7919.4", \ + "7442.3, 7442.3, 7442.3, 7610.5, 7919.4", \ + "7442.3, 7442.3, 7442.3, 7610.5, 7919.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("12519.6, 12519.6, 12519.6, 12760.2, 13221.2", \ + "12514.4, 12514.4, 12514.4, 12755.0, 13216.0", \ + "12504.1, 12504.1, 12504.1, 12744.7, 13205.7", \ + "12483.5, 12483.5, 12483.5, 12724.1, 13185.1", \ + "12442.2, 12442.2, 12442.2, 12682.8, 13143.8"); + } + rise_transition (inslew_load_5x5__14) { + values ("6728.2, 6728.2, 6728.2, 6921.0, 7302.8", \ + "6728.2, 6728.2, 6728.2, 6921.0, 7302.8", \ + "6728.2, 6728.2, 6728.2, 6921.0, 7302.8", \ + "6728.2, 6728.2, 6728.2, 6921.0, 7302.8", \ + "6728.2, 6728.2, 6728.2, 6921.0, 7302.8"); + } + cell_fall (inslew_load_5x5__14) { + values ("14546.2, 14546.2, 14546.2, 14762.3, 15282.9", \ + "14540.8, 14540.8, 14540.8, 14756.9, 15277.5", \ + "14530.1, 14530.1, 14530.1, 14746.2, 15266.8", \ + "14508.7, 14508.7, 14508.7, 14724.8, 15245.4", \ + "14465.8, 14465.8, 14465.8, 14681.9, 15202.5"); + } + fall_transition (inslew_load_5x5__14) { + values ("7442.3, 7442.3, 7442.3, 7610.5, 7919.4", \ + "7442.3, 7442.3, 7442.3, 7610.5, 7919.4", \ + "7442.3, 7442.3, 7442.3, 7610.5, 7919.4", \ + "7442.3, 7442.3, 7442.3, 7610.5, 7919.4", \ + "7442.3, 7442.3, 7442.3, 7610.5, 7919.4"); + } + } + timing (maxd_q_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__14) { + values ("13622.2, 13622.2, 13622.2, 13862.1, 14327.8", \ + "13631.0, 13631.0, 13631.0, 13870.9, 14336.6", \ + "13648.6, 13648.6, 13648.6, 13888.5, 14354.2", \ + "13683.7, 13683.7, 13683.7, 13923.6, 14389.3", \ + "13753.8, 13753.8, 13753.8, 13993.8, 14459.5"); + } + rise_transition (inslew_load_5x5__14) { + values ("5412.8, 5412.8, 5412.8, 5609.1, 6000.1", \ + "5412.8, 5412.8, 5412.8, 5609.1, 6000.1", \ + "5412.8, 5412.8, 5412.8, 5609.1, 6000.1", \ + "5412.8, 5412.8, 5412.8, 5609.1, 6000.1", \ + "5413.2, 5413.2, 5413.2, 5609.5, 6000.5"); + } + cell_fall (inslew_load_5x5__14) { + values ("13589.7, 13589.7, 13589.7, 13890.9, 14434.4", \ + "13598.5, 13598.5, 13598.5, 13899.7, 14443.2", \ + "13616.1, 13616.1, 13616.1, 13917.3, 14460.8", \ + "13651.3, 13651.3, 13651.3, 13952.5, 14496.0", \ + "13713.8, 13713.8, 13713.8, 14015.0, 14558.5"); + } + fall_transition (inslew_load_5x5__14) { + values ("5861.0, 5861.0, 5861.0, 6018.0, 6265.6", \ + "5861.0, 5861.0, 5861.0, 6018.0, 6265.6", \ + "5861.0, 5861.0, 5861.0, 6018.0, 6265.6", \ + "5861.0, 5861.0, 5861.0, 6018.0, 6265.6", \ + "5861.0, 5861.0, 5861.0, 6018.0, 6265.6"); + } + } + internal_power (energy_pos_q_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__14) { + values ("57980.1, 57980.1, 57980.1, 59879.5, 63678.1", \ + "58005.4, 58005.4, 58005.4, 59904.7, 63703.4", \ + "58030.1, 58030.1, 58030.1, 59929.4, 63728.1", \ + "58077.0, 58077.0, 58077.0, 59976.4, 63775.0", \ + "63864.0, 63864.0, 63864.0, 63864.0, 63864.0"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("58600.4, 58600.4, 58600.4, 60499.7, 64298.4", \ + "58657.4, 58657.4, 58657.4, 60556.8, 64355.4", \ + "58773.2, 58773.2, 58773.2, 60672.5, 64471.2", \ + "58956.0, 58956.0, 58956.0, 60855.4, 64654.1", \ + "59286.3, 59286.3, 59286.3, 61185.7, 64984.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__14) { + values ("71690.5, 71690.5, 71690.5, 73589.8, 77388.5", \ + "77411.4, 77411.4, 77411.4, 77411.4, 77411.4", \ + "77457.2, 77457.2, 77457.2, 77457.2, 77457.2", \ + "77548.8, 77548.8, 77548.8, 77548.8, 77548.8", \ + "77731.9, 77731.9, 77731.9, 77731.9, 77731.9"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("75877.4, 75877.4, 75877.4, 77776.7, 81575.4", \ + "81619.5, 81619.5, 81619.5, 81619.5, 81619.5", \ + "81707.6, 81707.6, 81707.6, 81707.6, 81707.6", \ + "81884.0, 81884.0, 81884.0, 81884.0, 81884.0", \ + "82236.7, 82236.7, 82236.7, 82236.7, 82236.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__14) { + values ("71690.5, 71690.5, 71690.5, 73589.8, 77388.5", \ + "77411.4, 77411.4, 77411.4, 77411.4, 77411.4", \ + "77457.2, 77457.2, 77457.2, 77457.2, 77457.2", \ + "77548.8, 77548.8, 77548.8, 77548.8, 77548.8", \ + "77731.9, 77731.9, 77731.9, 77731.9, 77731.9"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("75877.4, 75877.4, 75877.4, 77776.7, 81575.4", \ + "81619.5, 81619.5, 81619.5, 81619.5, 81619.5", \ + "81707.6, 81707.6, 81707.6, 81707.6, 81707.6", \ + "81884.0, 81884.0, 81884.0, 81884.0, 81884.0", \ + "82236.7, 82236.7, 82236.7, 82236.7, 82236.7"); + } + } + internal_power (energy_neg_q_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__14) { + values ("65263.5, 65263.5, 65263.5, 67162.8, 70961.5", \ + "71005.6, 71005.6, 71005.6, 71005.6, 71005.6", \ + "71093.7, 71093.7, 71093.7, 71093.7, 71093.7", \ + "71270.1, 71270.1, 71270.1, 71270.1, 71270.1", \ + "65928.2, 65928.2, 65928.2, 67827.5, 71626.2"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("65563.3, 65563.3, 65563.3, 67462.6, 71261.3", \ + "71284.2, 71284.2, 71284.2, 71284.2, 71284.2", \ + "71330.0, 71330.0, 71330.0, 71330.0, 71330.0", \ + "71422.3, 71422.3, 71422.3, 71422.3, 71422.3", \ + "71625.9, 71625.9, 71625.9, 71625.9, 71625.9"); + } + } + } + } + + cell (rowend_x0) { + area : 3.60 ; + cell_leakage_power : 0 ; + } + + cell (noa22_x1) { + area : 21.60 ; + cell_leakage_power : 4 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 3.3 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 5.5 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 3.1 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0))" ; + value : 5.2 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 2.8 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 4.2 ; + } + pin (i2) { + direction : input ; + capacitance : 853.12 ; + } + pin (i1) { + direction : input ; + capacitance : 848.02 ; + } + pin (i0) { + direction : input ; + capacitance : 846.52 ; + } + pin (nq) { + function : "((!(i0) & !(i2)) | (!(i1) & !(i2)))" ; + direction : output ; + capacitance : 150.41 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__30) { + values ("2973.6, 2973.6, 2973.6, 3429.4, 4341.2", \ + "2976.9, 2976.9, 2976.9, 3432.3, 4343.7", \ + "2986.0, 2986.0, 2986.0, 3441.2, 4352.4", \ + "3000.6, 3000.6, 3000.6, 3457.2, 4370.2", \ + "3023.4, 3023.4, 3023.4, 3480.8, 4394.2"); + } + rise_transition (inslew_load_5x5__30) { + values ("2613.9, 2613.9, 2613.9, 3340.8, 4797.0", \ + "2623.6, 2623.6, 2623.6, 3350.0, 4805.4", \ + "2643.0, 2643.0, 2643.0, 3369.0, 4824.1", \ + "2664.1, 2664.1, 2664.1, 3392.2, 4850.1", \ + "2675.4, 2675.4, 2675.4, 3401.6, 4857.9"); + } + cell_fall (inslew_load_5x5__30) { + values ("2393.0, 2393.0, 2393.0, 2663.0, 3203.7", \ + "2387.9, 2387.9, 2387.9, 2657.8, 3198.5", \ + "2377.5, 2377.5, 2377.5, 2647.5, 3188.2", \ + "2356.8, 2356.8, 2356.8, 2626.8, 3167.6", \ + "2310.8, 2310.8, 2310.8, 2583.0, 3125.5"); + } + fall_transition (inslew_load_5x5__30) { + values ("2210.1, 2210.1, 2210.1, 2631.9, 3475.4", \ + "2210.1, 2210.1, 2210.1, 2631.9, 3475.4", \ + "2210.1, 2210.1, 2210.1, 2631.9, 3475.4", \ + "2210.3, 2210.3, 2210.3, 2632.0, 3475.4", \ + "2222.4, 2222.4, 2222.4, 2641.1, 3480.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__30) { + values ("2185.8, 2185.8, 2185.8, 2647.4, 3562.9", \ + "2189.7, 2189.7, 2189.7, 2651.0, 3565.8", \ + "2199.4, 2199.4, 2199.4, 2660.3, 3574.6", \ + "2212.2, 2212.2, 2212.2, 2674.0, 3591.0", \ + "2229.2, 2229.2, 2229.2, 2695.7, 3614.8"); + } + rise_transition (inslew_load_5x5__30) { + values ("1388.0, 1388.0, 1388.0, 2115.8, 3569.5", \ + "1398.7, 1398.7, 1398.7, 2126.0, 3578.5", \ + "1419.0, 1419.0, 1419.0, 2145.7, 3597.4", \ + "1437.2, 1437.2, 1437.2, 2165.3, 3621.2", \ + "1453.1, 1453.1, 1453.1, 2178.6, 3630.3"); + } + cell_fall (inslew_load_5x5__30) { + values ("1558.8, 1558.8, 1558.8, 1835.4, 2384.4", \ + "1561.2, 1561.2, 1561.2, 1838.0, 2387.3", \ + "1570.2, 1570.2, 1570.2, 1846.7, 2395.4", \ + "1585.4, 1585.4, 1585.4, 1862.4, 2411.4", \ + "1591.8, 1591.8, 1591.8, 1881.5, 2440.6"); + } + fall_transition (inslew_load_5x5__30) { + values ("947.4, 947.4, 947.4, 1376.2, 2233.4", \ + "949.2, 949.2, 949.2, 1378.3, 2236.0", \ + "953.4, 953.4, 953.4, 1382.1, 2238.7", \ + "953.8, 953.8, 953.8, 1382.2, 2238.6", \ + "967.4, 967.4, 967.4, 1396.8, 2248.1"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__30) { + values ("5244.2, 5244.2, 5244.2, 5684.2, 6577.8", \ + "5238.7, 5238.7, 5238.7, 5678.7, 6572.4", \ + "5227.7, 5227.7, 5227.7, 5667.8, 6561.6", \ + "5205.7, 5205.7, 5205.7, 5646.1, 6540.0", \ + "5161.7, 5161.7, 5161.7, 5602.5, 6496.8"); + } + rise_transition (inslew_load_5x5__30) { + values ("6085.6, 6085.6, 6085.6, 6802.6, 8236.4", \ + "6085.6, 6085.6, 6085.6, 6802.6, 8236.4", \ + "6085.6, 6085.6, 6085.6, 6802.6, 8236.4", \ + "6085.6, 6085.6, 6085.6, 6802.6, 8236.4", \ + "6085.9, 6085.9, 6085.9, 6802.7, 8236.5"); + } + cell_fall (inslew_load_5x5__30) { + values ("1849.6, 1849.6, 1849.6, 2017.0, 2354.1", \ + "1858.4, 1858.4, 1858.4, 2025.8, 2362.9", \ + "1876.0, 1876.0, 1876.0, 2043.3, 2380.5", \ + "1911.0, 1911.0, 1911.0, 2078.5, 2415.6", \ + "1971.4, 1971.4, 1971.4, 2142.0, 2482.8"); + } + fall_transition (inslew_load_5x5__30) { + values ("1539.0, 1539.0, 1539.0, 1767.6, 2224.7", \ + "1539.0, 1539.0, 1539.0, 1767.6, 2224.7", \ + "1539.0, 1539.0, 1539.0, 1767.6, 2224.7", \ + "1539.9, 1539.9, 1539.9, 1768.1, 2225.0", \ + "1564.4, 1564.4, 1564.4, 1788.8, 2238.8"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__30) { + values ("5084.4, 5084.4, 5084.4, 6964.5, 10724.7", \ + "5169.8, 5169.8, 5169.8, 7049.8, 10810.0", \ + "5340.4, 5340.4, 5340.4, 7220.5, 10980.6", \ + "5681.6, 5681.6, 5681.6, 7561.7, 11321.9", \ + "6364.1, 6364.1, 6364.1, 8244.2, 12004.3"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("7620.2, 7620.2, 7620.2, 9500.2, 13260.4", \ + "7648.9, 7648.9, 7648.9, 9529.0, 13289.2", \ + "7706.4, 7706.4, 7706.4, 9586.5, 13346.7", \ + "7821.4, 7821.4, 7821.4, 9701.5, 13461.7", \ + "8051.4, 8051.4, 8051.4, 9931.5, 13691.7"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__30) { + values ("1893.7, 1893.7, 1893.7, 3773.8, 7534.0", \ + "1957.5, 1957.5, 1957.5, 3837.6, 7597.8", \ + "2085.1, 2085.1, 2085.1, 3965.1, 7725.3", \ + "2340.2, 2340.2, 2340.2, 4220.3, 7980.4", \ + "2850.4, 2850.4, 2850.4, 4730.5, 8490.7"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("1963.0, 1963.0, 1963.0, 3843.1, 7603.2", \ + "1995.7, 1995.7, 1995.7, 3875.8, 7636.0", \ + "2061.3, 2061.3, 2061.3, 3941.3, 7701.5", \ + "2192.3, 2192.3, 2192.3, 4072.4, 7832.5", \ + "2454.3, 2454.3, 2454.3, 4334.4, 8094.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__30) { + values ("14155.7, 14155.7, 14155.7, 16035.8, 19796.0", \ + "14244.1, 14244.1, 14244.1, 16124.2, 19884.4", \ + "14420.9, 14420.9, 14420.9, 16301.0, 20061.2", \ + "14774.5, 14774.5, 14774.5, 16654.6, 20414.7", \ + "15481.7, 15481.7, 15481.7, 17361.7, 21121.9"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("11119.8, 11119.8, 11119.8, 12999.9, 16760.1", \ + "11165.5, 11165.5, 11165.5, 13045.6, 16805.8", \ + "11256.9, 11256.9, 11256.9, 13137.0, 16897.2", \ + "11439.8, 11439.8, 11439.8, 13319.9, 17080.0", \ + "11805.5, 11805.5, 11805.5, 13685.6, 17445.7"); + } + } + } + } + + cell (noa2a2a23_x1) { + area : 36.00 ; + cell_leakage_power : 7.9 ; + leakage_power () { + when : "(i5 & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 8.3 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5))" ; + value : 7.9 ; + } + leakage_power () { + when : "(!(i5) & i4 & i3 & !(i2) & i1 & !(i0))" ; + value : 7.1 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & !(i5)) | (!(i0) & i1 & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))))" ; + value : 7.5 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((!(i3) & (i4 | i5)) | (i4 ^ i5))) | (!(i2) & i3 & (i4 | i5)))) | (!(i1) & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))))) | (!(i0) & ((i1 & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))) | (i2 & i3 & (i4 ^ i5)))))" ; + value : 12 ; + } + leakage_power () { + when : "((i0 & i1 & (!((i2 | i3)) | (!(i4) & !(i5)))) | (i2 & i3 & !(i4) & !(i5)))" ; + value : 11 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i0) & !(i1) & i2 & !(i3) & !(i4) & i5))" ; + value : 6.9 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & (i3 ^ i4) & !(i5)) | (!(i1) & !(i2) & i3 & i4 & !(i5))))" ; + value : 6.1 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & (i3 ^ i4) & !(i5)) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))))))" ; + value : 6.5 ; + } + leakage_power () { + when : "((!(i0) & !((i1 & !(i2) & !(i3))) & i4 & i5) | (!(i1) & (i2 | i3) & i4 & i5) | (i2 & i3 & i4 & i5))" ; + value : 13 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i1) & !(i2) & (i3 ^ i4) & !(i5))))" ; + value : 5.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))))" ; + value : 5.5 ; + } + leakage_power () { + when : "(!(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 4.2 ; + } + pin (i5) { + direction : input ; + capacitance : 845.77 ; + } + pin (i4) { + direction : input ; + capacitance : 848.32 ; + } + pin (i3) { + direction : input ; + capacitance : 845.17 ; + } + pin (i2) { + direction : input ; + capacitance : 844.87 ; + } + pin (i1) { + direction : input ; + capacitance : 845.47 ; + } + pin (i0) { + direction : input ; + capacitance : 843.97 ; + } + pin (nq) { + function : "(((((((((!(i4) & !(i2)) & !(i0)) | ((!(i4) & !(i2)) & !(i1))) | ((!(i4) & !(i3)) & !(i0))) | ((!(i4) & !(i3)) & !(i1))) | ((!(i5) & !(i2)) & !(i0))) | ((!(i5) & !(i2)) & !(i1))) | ((!(i5) & !(i3)) & !(i0))) | ((!(i5) & !(i3)) & !(i1)))" ; + direction : output ; + capacitance : 181.93 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("11975.3, 11975.3, 11975.3, 12654.5, 14067.1", \ + "11963.8, 11963.8, 11963.8, 12643.1, 14055.8", \ + "11940.8, 11940.8, 11940.8, 12620.2, 14033.0", \ + "11894.8, 11894.8, 11894.8, 12574.5, 13987.5", \ + "11802.8, 11802.8, 11802.8, 12483.1, 13896.5"); + } + rise_transition (inslew_load_5x5__31) { + values ("17475.8, 17475.8, 17475.8, 18738.0, 21262.3", \ + "17475.8, 17475.8, 17475.8, 18738.0, 21262.3", \ + "17475.8, 17475.8, 17475.8, 18738.0, 21262.3", \ + "17475.8, 17475.8, 17475.8, 18738.0, 21262.3", \ + "17475.8, 17475.8, 17475.8, 18738.0, 21262.3"); + } + cell_fall (inslew_load_5x5__31) { + values ("4741.1, 4741.1, 4741.1, 5052.7, 5691.7", \ + "4735.9, 4735.9, 4735.9, 5047.6, 5686.6", \ + "4725.6, 4725.6, 4725.6, 5037.2, 5676.3", \ + "4704.9, 4704.9, 4704.9, 5016.6, 5655.6", \ + "4663.4, 4663.4, 4663.4, 4975.2, 5614.3"); + } + fall_transition (inslew_load_5x5__31) { + values ("5771.6, 5771.6, 5771.6, 6281.7, 7302.0", \ + "5771.6, 5771.6, 5771.6, 6281.7, 7302.0", \ + "5771.6, 5771.6, 5771.6, 6281.7, 7302.0", \ + "5771.6, 5771.6, 5771.6, 6281.7, 7302.0", \ + "5772.2, 5772.2, 5772.2, 6282.1, 7302.2"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("10930.7, 10930.7, 10930.7, 11617.0, 13036.3", \ + "10919.2, 10919.2, 10919.2, 11605.5, 13024.9", \ + "10896.3, 10896.3, 10896.3, 11582.7, 13002.2", \ + "10850.3, 10850.3, 10850.3, 11537.0, 12956.7", \ + "10758.5, 10758.5, 10758.5, 11445.7, 12865.7"); + } + rise_transition (inslew_load_5x5__31) { + values ("15716.8, 15716.8, 15716.8, 16979.0, 19503.3", \ + "15716.8, 15716.8, 15716.8, 16979.0, 19503.3", \ + "15716.8, 15716.8, 15716.8, 16979.0, 19503.3", \ + "15716.8, 15716.8, 15716.8, 16979.0, 19503.3", \ + "15716.8, 15716.8, 15716.8, 16979.0, 19503.3"); + } + cell_fall (inslew_load_5x5__31) { + values ("3920.5, 3920.5, 3920.5, 4239.6, 4888.1", \ + "3923.8, 3923.8, 3923.8, 4243.0, 4891.6", \ + "3931.0, 3931.0, 3931.0, 4250.1, 4898.6", \ + "3947.3, 3947.3, 3947.3, 4266.4, 4915.0", \ + "3980.5, 3980.5, 3980.5, 4299.8, 4948.5"); + } + fall_transition (inslew_load_5x5__31) { + values ("4568.4, 4568.4, 4568.4, 5087.3, 6125.4", \ + "4571.7, 4571.7, 4571.7, 5090.8, 6128.9", \ + "4573.1, 4573.1, 4573.1, 5092.0, 6130.0", \ + "4573.3, 4573.3, 4573.3, 5092.3, 6130.4", \ + "4574.4, 4574.4, 4574.4, 5093.0, 6130.6"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("7958.9, 7958.9, 7958.9, 8667.9, 10112.4", \ + "7956.8, 7956.8, 7956.8, 8666.0, 10110.8", \ + "7944.3, 7944.3, 7944.3, 8653.7, 10098.6", \ + "7927.0, 7927.0, 7927.0, 8637.0, 10082.6", \ + "7887.4, 7887.4, 7887.4, 8598.1, 10044.8"); + } + rise_transition (inslew_load_5x5__31) { + values ("10800.2, 10800.2, 10800.2, 12079.1, 14638.1", \ + "10813.5, 10813.5, 10813.5, 12092.7, 14652.1", \ + "10823.1, 10823.1, 10823.1, 12102.3, 14661.8", \ + "10846.9, 10846.9, 10846.9, 12126.8, 14687.4", \ + "10863.6, 10863.6, 10863.6, 12144.3, 14706.2"); + } + cell_fall (inslew_load_5x5__31) { + values ("3829.7, 3829.7, 3829.7, 4147.3, 4792.3", \ + "3824.5, 3824.5, 3824.5, 4142.1, 4787.2", \ + "3814.2, 3814.2, 3814.2, 4131.8, 4776.8", \ + "3793.5, 3793.5, 3793.5, 4111.1, 4756.2", \ + "3751.9, 3751.9, 3751.9, 4069.7, 4714.9"); + } + fall_transition (inslew_load_5x5__31) { + values ("4390.1, 4390.1, 4390.1, 4900.3, 5920.6", \ + "4390.1, 4390.1, 4390.1, 4900.3, 5920.6", \ + "4390.1, 4390.1, 4390.1, 4900.3, 5920.6", \ + "4390.1, 4390.1, 4390.1, 4900.3, 5920.6", \ + "4392.2, 4392.2, 4392.2, 4901.7, 5921.2"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("6911.1, 6911.1, 6911.1, 7626.7, 9077.2", \ + "6908.7, 6908.7, 6908.7, 7624.5, 9075.4", \ + "6896.3, 6896.3, 6896.3, 7612.2, 9063.2", \ + "6878.3, 6878.3, 6878.3, 7594.9, 9046.8", \ + "6837.9, 6837.9, 6837.9, 7555.5, 9008.5"); + } + rise_transition (inslew_load_5x5__31) { + values ("9019.1, 9019.1, 9019.1, 10297.0, 12854.8", \ + "9031.9, 9031.9, 9031.9, 10310.2, 12868.6", \ + "9041.4, 9041.4, 9041.4, 10319.7, 12878.2", \ + "9063.9, 9063.9, 9063.9, 10343.2, 12903.1", \ + "9078.9, 9078.9, 9078.9, 10359.5, 12921.0"); + } + cell_fall (inslew_load_5x5__31) { + values ("3003.9, 3003.9, 3003.9, 3328.9, 3983.3", \ + "3007.1, 3007.1, 3007.1, 3332.1, 3986.7", \ + "3014.6, 3014.6, 3014.6, 3339.5, 3993.9", \ + "3030.8, 3030.8, 3030.8, 3355.8, 4010.2", \ + "3063.0, 3063.0, 3063.0, 3388.6, 4043.6"); + } + fall_transition (inslew_load_5x5__31) { + values ("3163.3, 3163.3, 3163.3, 3682.1, 4719.9", \ + "3166.3, 3166.3, 3166.3, 3685.3, 4723.3", \ + "3168.3, 3168.3, 3168.3, 3687.0, 4724.7", \ + "3168.4, 3168.4, 3168.4, 3687.1, 4724.9", \ + "3172.6, 3172.6, 3172.6, 3689.9, 4726.0"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("2752.8, 2752.8, 2752.8, 3493.3, 4966.0", \ + "2786.9, 2786.9, 2786.9, 3526.8, 4998.6", \ + "2833.7, 2833.7, 2833.7, 3572.3, 5042.5", \ + "2861.2, 2861.2, 2861.2, 3595.0, 5059.4", \ + "2931.2, 2931.2, 2931.2, 3664.2, 5129.8"); + } + rise_transition (inslew_load_5x5__31) { + values ("1942.8, 1942.8, 1942.8, 3233.9, 5817.4", \ + "2017.3, 2017.3, 2017.3, 3307.2, 5889.1", \ + "2126.2, 2126.2, 2126.2, 3413.8, 5992.9", \ + "2219.5, 2219.5, 2219.5, 3498.6, 6067.3", \ + "2411.9, 2411.9, 2411.9, 3685.5, 6254.4"); + } + cell_fall (inslew_load_5x5__31) { + values ("1612.9, 1612.9, 1612.9, 1946.8, 2609.8", \ + "1615.4, 1615.4, 1615.4, 1949.4, 2612.8", \ + "1624.3, 1624.3, 1624.3, 1958.0, 2620.7", \ + "1639.7, 1639.7, 1639.7, 1973.8, 2636.8", \ + "1649.3, 1649.3, 1649.3, 1996.0, 2667.6"); + } + fall_transition (inslew_load_5x5__31) { + values ("1031.0, 1031.0, 1031.0, 1549.6, 2586.5", \ + "1032.9, 1032.9, 1032.9, 1551.7, 2589.2", \ + "1037.0, 1037.0, 1037.0, 1555.3, 2591.6", \ + "1037.4, 1037.4, 1037.4, 1555.3, 2591.6", \ + "1051.8, 1051.8, 1051.8, 1569.2, 2598.9"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__31) { + values ("3798.4, 3798.4, 3798.4, 4531.9, 6003.5", \ + "3831.6, 3831.6, 3831.6, 4564.7, 6035.8", \ + "3876.6, 3876.6, 3876.6, 4608.9, 6079.2", \ + "3897.6, 3897.6, 3897.6, 4627.0, 6094.1", \ + "3966.8, 3966.8, 3966.8, 4696.8, 6165.4"); + } + rise_transition (inslew_load_5x5__31) { + values ("3741.2, 3741.2, 3741.2, 5032.4, 7625.8", \ + "3814.0, 3814.0, 3814.0, 5104.5, 7696.9", \ + "3919.8, 3919.8, 3919.8, 5208.8, 7799.9", \ + "4001.8, 4001.8, 4001.8, 5285.5, 7870.8", \ + "4188.0, 4188.0, 4188.0, 5471.9, 8059.3"); + } + cell_fall (inslew_load_5x5__31) { + values ("2445.6, 2445.6, 2445.6, 2772.3, 3426.5", \ + "2440.4, 2440.4, 2440.4, 2767.1, 3421.3", \ + "2430.1, 2430.1, 2430.1, 2756.8, 3411.0", \ + "2409.5, 2409.5, 2409.5, 2736.2, 3390.4", \ + "2364.0, 2364.0, 2364.0, 2692.9, 3348.7"); + } + fall_transition (inslew_load_5x5__31) { + values ("2292.3, 2292.3, 2292.3, 2802.5, 3822.7", \ + "2292.3, 2292.3, 2292.3, 2802.5, 3822.7", \ + "2292.3, 2292.3, 2292.3, 2802.5, 3822.7", \ + "2292.5, 2292.5, 2292.5, 2802.5, 3822.8", \ + "2304.0, 2304.0, 2304.0, 2810.6, 3826.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__31) { + values ("29366.4, 29366.4, 29366.4, 31640.5, 36188.6", \ + "29454.8, 29454.8, 29454.8, 31728.9, 36277.0", \ + "29631.6, 29631.6, 29631.6, 31905.7, 36453.8", \ + "29985.2, 29985.2, 29985.2, 32259.3, 36807.4", \ + "30692.4, 30692.4, 30692.4, 32966.4, 37514.6"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("23513.0, 23513.0, 23513.0, 25787.0, 30335.2", \ + "23558.7, 23558.7, 23558.7, 25832.7, 30380.9", \ + "23650.1, 23650.1, 23650.1, 25924.2, 30472.3", \ + "23832.9, 23832.9, 23832.9, 26107.0, 30655.2", \ + "24198.6, 24198.6, 24198.6, 26472.7, 31020.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__31) { + values ("26172.0, 26172.0, 26172.0, 28446.1, 32994.2", \ + "26235.1, 26235.1, 26235.1, 28509.2, 33057.4", \ + "26361.4, 26361.4, 26361.4, 28635.5, 33183.7", \ + "26614.0, 26614.0, 26614.0, 28888.1, 33436.3", \ + "27119.2, 27119.2, 27119.2, 29393.3, 33941.5"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("17856.5, 17856.5, 17856.5, 20130.5, 24678.7", \ + "17906.9, 17906.9, 17906.9, 20180.9, 24729.1", \ + "18007.7, 18007.7, 18007.7, 20281.8, 24829.9", \ + "18209.3, 18209.3, 18209.3, 20483.4, 25031.5", \ + "18612.5, 18612.5, 18612.5, 20886.6, 25434.7"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__31) { + values ("17198.8, 17198.8, 17198.8, 19472.9, 24021.0", \ + "17284.1, 17284.1, 17284.1, 19558.2, 24106.3", \ + "17454.7, 17454.7, 17454.7, 19728.8, 24277.0", \ + "17796.0, 17796.0, 17796.0, 20070.0, 24618.2", \ + "18478.4, 18478.4, 18478.4, 20752.5, 25300.7"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("17338.0, 17338.0, 17338.0, 19612.1, 24160.2", \ + "17366.8, 17366.8, 17366.8, 19640.8, 24189.0", \ + "17424.3, 17424.3, 17424.3, 19698.3, 24246.5", \ + "17539.3, 17539.3, 17539.3, 19813.3, 24361.5", \ + "17769.3, 17769.3, 17769.3, 20043.3, 24591.5"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__31) { + values ("14008.1, 14008.1, 14008.1, 16282.2, 20830.3", \ + "14071.9, 14071.9, 14071.9, 16345.9, 20894.1", \ + "14199.4, 14199.4, 14199.4, 16473.5, 21021.6", \ + "14454.5, 14454.5, 14454.5, 16728.6, 21276.8", \ + "14964.8, 14964.8, 14964.8, 17238.9, 21787.0"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("11680.8, 11680.8, 11680.8, 13954.9, 18503.1", \ + "11713.6, 11713.6, 11713.6, 13987.7, 18535.8", \ + "11779.1, 11779.1, 11779.1, 14053.2, 18601.3", \ + "11910.1, 11910.1, 11910.1, 14184.2, 18732.4", \ + "12172.2, 12172.2, 12172.2, 14446.3, 18994.4"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__31) { + values ("2313.7, 2313.7, 2313.7, 4587.7, 9135.9", \ + "2375.8, 2375.8, 2375.8, 4649.9, 9198.1", \ + "2500.2, 2500.2, 2500.2, 4774.3, 9322.4", \ + "2748.9, 2748.9, 2748.9, 5023.0, 9571.1", \ + "3246.3, 3246.3, 3246.3, 5520.4, 10068.6"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("2320.0, 2320.0, 2320.0, 4594.0, 9142.2", \ + "2343.2, 2343.2, 2343.2, 4617.3, 9165.5", \ + "2389.8, 2389.8, 2389.8, 4663.9, 9212.0", \ + "2483.0, 2483.0, 2483.0, 4757.1, 9305.2", \ + "2669.3, 2669.3, 2669.3, 4943.4, 9491.5"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__31) { + values ("5501.8, 5501.8, 5501.8, 7775.9, 12324.1", \ + "5583.0, 5583.0, 5583.0, 7857.1, 12405.2", \ + "5745.3, 5745.3, 5745.3, 8019.4, 12567.5", \ + "6069.9, 6069.9, 6069.9, 8344.0, 12892.2", \ + "6719.2, 6719.2, 6719.2, 8993.2, 13541.4"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("7977.6, 7977.6, 7977.6, 10251.7, 14799.8", \ + "7997.4, 7997.4, 7997.4, 10271.4, 14819.6", \ + "8036.9, 8036.9, 8036.9, 10311.0, 14859.1", \ + "8115.9, 8115.9, 8115.9, 10390.0, 14938.2", \ + "8274.0, 8274.0, 8274.0, 10548.1, 15096.3"); + } + } + } + } + + cell (oa2a22_x4) { + area : 36.00 ; + cell_leakage_power : 6.5 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 8.9 ; + } + leakage_power () { + when : "(i3 & !(i2) & !(i1) & i0)" ; + value : 6.1 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2 & i3)" ; + value : 8.6 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & !(i0))" ; + value : 5.7 ; + } + leakage_power () { + when : "((i0 & !(i1) & i2 & !(i3)) | (!(i0) & i1 & !(i2) & i3))" ; + value : 5.9 ; + } + leakage_power () { + when : "(i3 & i2 & !(i1) & !(i0))" ; + value : 8.4 ; + } + leakage_power () { + when : "(!(i0) & (i1 ^ i2) & !(i3))" ; + value : 5.2 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & !(i1) & !(i2) & i3))" ; + value : 5.4 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 4.7 ; + } + pin (i3) { + direction : input ; + capacitance : 432.96 ; + } + pin (i2) { + direction : input ; + capacitance : 434.46 ; + } + pin (i1) { + direction : input ; + capacitance : 434.46 ; + } + pin (i0) { + direction : input ; + capacitance : 432.96 ; + } + pin (q) { + function : "((i0 & ((i2 & i3) | i1)) | (i2 & i3))" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("11424.3, 11424.3, 11424.3, 11664.3, 12123.2", \ + "11419.1, 11419.1, 11419.1, 11659.1, 12118.0", \ + "11408.8, 11408.8, 11408.8, 11648.8, 12107.7", \ + "11388.2, 11388.2, 11388.2, 11628.2, 12087.1", \ + "11346.9, 11346.9, 11346.9, 11586.9, 12045.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("6022.8, 6022.8, 6022.8, 6217.1, 6602.6", \ + "6022.8, 6022.8, 6022.8, 6217.1, 6602.6", \ + "6022.8, 6022.8, 6022.8, 6217.1, 6602.6", \ + "6022.8, 6022.8, 6022.8, 6217.1, 6602.6", \ + "6022.8, 6022.8, 6022.8, 6217.1, 6602.6"); + } + cell_fall (inslew_load_5x5__3) { + values ("12211.7, 12211.7, 12211.7, 12514.5, 13101.1", \ + "12210.2, 12210.2, 12210.2, 12513.0, 13099.7", \ + "12222.6, 12222.6, 12222.6, 12525.4, 13113.4", \ + "12238.1, 12238.1, 12238.1, 12541.0, 13130.4", \ + "12260.3, 12260.3, 12260.3, 12563.2, 13153.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("6206.3, 6206.3, 6206.3, 6368.0, 6635.0", \ + "6207.3, 6207.3, 6207.3, 6369.1, 6636.1", \ + "6217.7, 6217.7, 6217.7, 6379.5, 6647.2", \ + "6228.7, 6228.7, 6228.7, 6390.8, 6659.2", \ + "6235.3, 6235.3, 6235.3, 6397.4, 6666.3"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("10301.3, 10301.3, 10301.3, 10540.9, 11008.2", \ + "10306.1, 10306.1, 10306.1, 10545.8, 11012.9", \ + "10312.8, 10312.8, 10312.8, 10552.4, 11019.6", \ + "10329.5, 10329.5, 10329.5, 10569.1, 11036.3", \ + "10363.2, 10363.2, 10363.2, 10602.8, 11070.0"); + } + rise_transition (inslew_load_5x5__3) { + values ("5340.6, 5340.6, 5340.6, 5537.1, 5927.5", \ + "5343.1, 5343.1, 5343.1, 5539.5, 5929.9", \ + "5343.4, 5343.4, 5343.4, 5539.9, 5930.3", \ + "5343.8, 5343.8, 5343.8, 5540.3, 5930.7", \ + "5343.8, 5343.8, 5343.8, 5540.3, 5930.7"); + } + cell_fall (inslew_load_5x5__3) { + values ("11612.3, 11612.3, 11612.3, 11911.4, 12453.1", \ + "11610.8, 11610.8, 11610.8, 11910.0, 12451.7", \ + "11623.2, 11623.2, 11623.2, 11922.8, 12465.5", \ + "11638.6, 11638.6, 11638.6, 11938.6, 12482.4", \ + "11660.9, 11660.9, 11660.9, 11960.9, 12505.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("5837.8, 5837.8, 5837.8, 5994.0, 6241.2", \ + "5838.9, 5838.9, 5838.9, 5995.1, 6242.3", \ + "5849.2, 5849.2, 5849.2, 6005.9, 6253.4", \ + "5860.3, 5860.3, 5860.3, 6017.4, 6265.2", \ + "5866.9, 5866.9, 5866.9, 6024.1, 6272.2"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("12307.5, 12307.5, 12307.5, 12547.9, 13007.7", \ + "12312.4, 12312.4, 12312.4, 12552.7, 13012.6", \ + "12318.9, 12318.9, 12318.9, 12559.3, 13019.1", \ + "12335.6, 12335.6, 12335.6, 12576.0, 13035.8", \ + "12369.3, 12369.3, 12369.3, 12609.7, 13069.5"); + } + rise_transition (inslew_load_5x5__3) { + values ("6642.8, 6642.8, 6642.8, 6835.6, 7217.0", \ + "6645.2, 6645.2, 6645.2, 6838.0, 7219.5", \ + "6645.5, 6645.5, 6645.5, 6838.3, 7219.8", \ + "6646.0, 6646.0, 6646.0, 6838.8, 7220.2", \ + "6646.0, 6646.0, 6646.0, 6838.8, 7220.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("14165.0, 14165.0, 14165.0, 14380.0, 14923.0", \ + "14159.6, 14159.6, 14159.6, 14374.6, 14917.6", \ + "14148.9, 14148.9, 14148.9, 14363.9, 14906.9", \ + "14127.5, 14127.5, 14127.5, 14342.5, 14885.5", \ + "14084.7, 14084.7, 14084.7, 14299.7, 14842.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("7230.1, 7230.1, 7230.1, 7397.1, 7696.7", \ + "7230.1, 7230.1, 7230.1, 7397.1, 7696.7", \ + "7230.1, 7230.1, 7230.1, 7397.1, 7696.7", \ + "7230.1, 7230.1, 7230.1, 7397.1, 7696.7", \ + "7230.1, 7230.1, 7230.1, 7397.1, 7696.7"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("13385.9, 13385.9, 13385.9, 13625.9, 14088.3", \ + "13380.7, 13380.7, 13380.7, 13620.7, 14083.1", \ + "13370.4, 13370.4, 13370.4, 13610.4, 14072.8", \ + "13349.8, 13349.8, 13349.8, 13589.8, 14052.2", \ + "13308.6, 13308.6, 13308.6, 13548.6, 14011.0"); + } + rise_transition (inslew_load_5x5__3) { + values ("7281.7, 7281.7, 7281.7, 7474.5, 7854.9", \ + "7281.7, 7281.7, 7281.7, 7474.5, 7854.9", \ + "7281.7, 7281.7, 7281.7, 7474.5, 7854.9", \ + "7281.7, 7281.7, 7281.7, 7474.5, 7854.9", \ + "7281.7, 7281.7, 7281.7, 7474.5, 7854.9"); + } + cell_fall (inslew_load_5x5__3) { + values ("14816.4, 14816.4, 14816.4, 15033.0, 15535.0", \ + "14811.1, 14811.1, 14811.1, 15027.7, 15529.7", \ + "14800.4, 14800.4, 14800.4, 15017.0, 15519.0", \ + "14779.0, 14779.0, 14779.0, 14995.6, 15497.6", \ + "14736.1, 14736.1, 14736.1, 14952.7, 15454.7"); + } + fall_transition (inslew_load_5x5__3) { + values ("7587.4, 7587.4, 7587.4, 7756.0, 8071.0", \ + "7587.4, 7587.4, 7587.4, 7756.0, 8071.0", \ + "7587.4, 7587.4, 7587.4, 7756.0, 8071.0", \ + "7587.4, 7587.4, 7587.4, 7756.0, 8071.0", \ + "7587.4, 7587.4, 7587.4, 7756.0, 8071.0"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("64922.6, 64922.6, 64922.6, 66818.5, 70610.1", \ + "70624.5, 70624.5, 70624.5, 70624.5, 70624.5", \ + "70653.2, 70653.2, 70653.2, 70653.2, 70653.2", \ + "70710.7, 70710.7, 70710.7, 70710.7, 70710.7", \ + "70825.5, 70825.5, 70825.5, 70825.5, 70825.5"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("62474.1, 62474.1, 62474.1, 64369.9, 68161.6", \ + "62523.1, 62523.1, 62523.1, 64418.9, 68210.6", \ + "62672.2, 62672.2, 62672.2, 64568.0, 68359.7", \ + "62911.3, 62911.3, 62911.3, 64807.1, 68598.8", \ + "63292.9, 63292.9, 63292.9, 65188.8, 68980.4"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("58124.8, 58124.8, 58124.8, 60020.7, 63812.3", \ + "58150.1, 58150.1, 58150.1, 60045.9, 63837.6", \ + "58174.5, 58174.5, 58174.5, 60070.3, 63862.0", \ + "58221.4, 58221.4, 58221.4, 60117.2, 63908.9", \ + "63997.8, 63997.8, 63997.8, 63997.8, 63997.8"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("58612.9, 58612.9, 58612.9, 60508.7, 64300.4", \ + "58660.5, 58660.5, 58660.5, 60556.3, 64348.0", \ + "58806.2, 58806.2, 58806.2, 60702.0, 64493.7", \ + "59038.4, 59038.4, 59038.4, 60934.3, 64725.9", \ + "59406.4, 59406.4, 59406.4, 61302.2, 65093.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("70443.7, 70443.7, 70443.7, 72339.5, 76131.2", \ + "70483.4, 70483.4, 70483.4, 72379.2, 76170.9", \ + "70535.5, 70535.5, 70535.5, 72431.3, 76223.0", \ + "70639.0, 70639.0, 70639.0, 72534.8, 76326.5", \ + "76527.9, 76527.9, 76527.9, 76527.9, 76527.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("73652.4, 73652.4, 73652.4, 75548.2, 79339.9", \ + "79371.5, 79371.5, 79371.5, 79371.5, 79371.5", \ + "79434.6, 79434.6, 79434.6, 79434.6, 79434.6", \ + "79560.8, 79560.8, 79560.8, 79560.8, 79560.8", \ + "79813.3, 79813.3, 79813.3, 79813.3, 79813.3"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__3) { + values ("77104.4, 77104.4, 77104.4, 79000.2, 82791.9", \ + "82814.8, 82814.8, 82814.8, 82814.8, 82814.8", \ + "82860.6, 82860.6, 82860.6, 82860.6, 82860.6", \ + "82952.2, 82952.2, 82952.2, 82952.2, 82952.2", \ + "83135.4, 83135.4, 83135.4, 83135.4, 83135.4"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("77482.4, 77482.4, 77482.4, 79378.2, 83169.9", \ + "83214.0, 83214.0, 83214.0, 83214.0, 83214.0", \ + "83302.2, 83302.2, 83302.2, 83302.2, 83302.2", \ + "83478.5, 83478.5, 83478.5, 83478.5, 83478.5", \ + "83831.2, 83831.2, 83831.2, 83831.2, 83831.2"); + } + } + } + } + + cell (nmx3_x1) { + area : 43.20 ; + cell_leakage_power : 4.7 ; + leakage_power () { + when : "(cmd0 & cmd1 & i0 & i1)" ; + value : 3.5 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i0) & i1)" ; + value : 3.4 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & cmd1 & cmd0)" ; + value : 4.2 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0 & !(cmd1) & cmd0)" ; + value : 6.2 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0 & !(cmd1) & cmd0)" ; + value : 5.4 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0) & !(cmd1) & cmd0)" ; + value : 4 ; + } + leakage_power () { + when : "(cmd0 & !((cmd1 ^ i0)) & !(i1) & !(i2))" ; + value : 4.8 ; + } + leakage_power () { + when : "((cmd0 ^ cmd1) & i0 & i2)" ; + value : 4.1 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & !(i0) & i1 & i2) | (!(cmd0) & cmd1 & i0 & !(i2)))" ; + value : 3.9 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & i1)" ; + value : 4.6 ; + } + leakage_power () { + when : "(!(cmd0) & ((cmd1 & !(i0) & !(i1) & !(i2)) | (!(cmd1) & i0 & !(i1))))" ; + value : 4.5 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0) & !(cmd1) & !(cmd0))" ; + value : 6.1 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0) & !(cmd1) & !(cmd0))" ; + value : 5.5 ; + } + leakage_power () { + when : "((cmd0 & ((cmd1 & i0 & !(i1) & i2) | (!(cmd1) & !(i0) & i1 & !(i2)))) | (!(cmd0) & ((cmd1 & !(i0) & i1 & i2) | (!(cmd1) & !(i0) & !(i1) & i2))))" ; + value : 5.6 ; + } + leakage_power () { + when : "((!(cmd0) & ((cmd1 & !(i0) & (i1 ^ i2)) | (!(cmd1) & !(i0) & !(i1) & !(i2)))) | (cmd1 & !(i0) & !(i1) & i2))" ; + value : 5 ; + } + pin (i2) { + direction : input ; + capacitance : 452.77 ; + } + pin (i1) { + direction : input ; + capacitance : 454.85 ; + } + pin (i0) { + direction : input ; + capacitance : 462.83 ; + } + pin (cmd1) { + direction : input ; + capacitance : 774.46 ; + } + pin (cmd0) { + direction : input ; + capacitance : 771.51 ; + } + pin (nq) { + function : "((!(i2) & ((!(i0) & (!(cmd0) | !(i1) | !(cmd1))) | (cmd0 & (!(i1) | !(cmd1))))) | (!(i0) & (!(cmd0) | (!(i1) & cmd1))) | (cmd0 & !(i1) & cmd1))" ; + direction : output ; + capacitance : 140.33 ; + timing (maxd_nq_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__32) { + values ("13999.4, 13999.4, 13999.4, 15063.3, 17282.6", \ + "14008.2, 14008.2, 14008.2, 15072.1, 17291.4", \ + "14025.8, 14025.8, 14025.8, 15089.7, 17309.0", \ + "14060.8, 14060.8, 14060.8, 15124.7, 17344.0", \ + "14121.0, 14121.0, 14121.0, 15185.2, 17404.6"); + } + rise_transition (inslew_load_5x5__32) { + values ("17874.6, 17874.6, 17874.6, 19821.3, 23717.1", \ + "17874.6, 17874.6, 17874.6, 19821.3, 23717.1", \ + "17874.6, 17874.6, 17874.6, 19821.3, 23717.1", \ + "17874.6, 17874.6, 17874.6, 19821.3, 23717.1", \ + "17874.7, 17874.7, 17874.7, 19821.4, 23717.1"); + } + cell_fall (inslew_load_5x5__32) { + values ("7817.4, 7817.4, 7817.4, 8254.0, 9132.9", \ + "7826.2, 7826.2, 7826.2, 8262.8, 9141.7", \ + "7843.8, 7843.8, 7843.8, 8280.4, 9159.3", \ + "7878.9, 7878.9, 7878.9, 8315.5, 9194.4", \ + "7949.2, 7949.2, 7949.2, 8385.8, 9264.7"); + } + fall_transition (inslew_load_5x5__32) { + values ("5653.8, 5653.8, 5653.8, 6289.6, 7558.5", \ + "5653.8, 5653.8, 5653.8, 6289.6, 7558.5", \ + "5653.8, 5653.8, 5653.8, 6289.6, 7558.5", \ + "5653.8, 5653.8, 5653.8, 6289.6, 7558.5", \ + "5654.4, 5654.4, 5654.4, 6290.2, 7559.1"); + } + } + timing (maxd_nq_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__32) { + values ("5772.7, 5772.7, 5772.7, 6951.0, 9248.1", \ + "5781.5, 5781.5, 5781.5, 6959.8, 9256.9", \ + "5799.1, 5799.1, 5799.1, 6977.4, 9274.5", \ + "5834.2, 5834.2, 5834.2, 7012.5, 9309.6", \ + "5898.1, 5898.1, 5898.1, 7077.9, 9375.9"); + } + rise_transition (inslew_load_5x5__32) { + values ("3464.4, 3464.4, 3464.4, 5428.7, 9404.5", \ + "3464.4, 3464.4, 3464.4, 5428.7, 9404.5", \ + "3464.4, 3464.4, 3464.4, 5428.7, 9404.5", \ + "3464.4, 3464.4, 3464.4, 5428.8, 9404.5", \ + "3466.6, 3466.6, 3466.6, 5430.8, 9405.9"); + } + cell_fall (inslew_load_5x5__32) { + values ("5324.0, 5324.0, 5324.0, 6251.0, 7685.9", \ + "5332.8, 5332.8, 5332.8, 6259.8, 7694.7", \ + "5350.4, 5350.4, 5350.4, 6277.4, 7712.3", \ + "5385.5, 5385.5, 5385.5, 6312.5, 7747.4", \ + "5455.3, 5455.3, 5455.3, 6382.5, 7817.5"); + } + fall_transition (inslew_load_5x5__32) { + values ("2156.6, 2156.6, 2156.6, 3201.1, 5151.5", \ + "2156.6, 2156.6, 2156.6, 3201.1, 5151.5", \ + "2156.6, 2156.6, 2156.6, 3201.1, 5151.5", \ + "2156.6, 2156.6, 2156.6, 3201.1, 5151.5", \ + "2156.7, 2156.7, 2156.7, 3201.4, 5151.8"); + } + } + timing (maxd_nq_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__32) { + values ("8692.6, 8692.6, 8692.6, 9506.1, 11172.0", \ + "8687.2, 8687.2, 8687.2, 9500.7, 11166.6", \ + "8676.3, 8676.3, 8676.3, 9490.0, 11155.9", \ + "8654.6, 8654.6, 8654.6, 9468.4, 11134.4", \ + "8611.3, 8611.3, 8611.3, 9425.3, 11091.5"); + } + rise_transition (inslew_load_5x5__32) { + values ("11259.4, 11259.4, 11259.4, 12597.8, 15274.7", \ + "11259.4, 11259.4, 11259.4, 12597.8, 15274.7", \ + "11259.4, 11259.4, 11259.4, 12597.8, 15274.7", \ + "11259.4, 11259.4, 11259.4, 12597.8, 15274.7", \ + "11259.4, 11259.4, 11259.4, 12597.8, 15274.7"); + } + cell_fall (inslew_load_5x5__32) { + values ("5007.4, 5007.4, 5007.4, 5550.8, 6653.9", \ + "4996.3, 4996.3, 4996.3, 5539.7, 6642.8", \ + "4974.1, 4974.1, 4974.1, 5517.5, 6620.6", \ + "4929.7, 4929.7, 4929.7, 5473.2, 6576.3", \ + "4840.9, 4840.9, 4840.9, 5384.5, 6487.6"); + } + fall_transition (inslew_load_5x5__32) { + values ("6688.4, 6688.4, 6688.4, 7640.9, 9545.8", \ + "6688.4, 6688.4, 6688.4, 7640.9, 9545.8", \ + "6688.4, 6688.4, 6688.4, 7640.9, 9545.8", \ + "6688.4, 6688.4, 6688.4, 7640.9, 9545.8", \ + "6688.9, 6688.9, 6688.9, 7641.1, 9545.8"); + } + } + timing (maxd_nq_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__32) { + values ("3512.3, 3512.3, 3512.3, 4656.1, 6939.4", \ + "3539.0, 3539.0, 3539.0, 4682.1, 6964.5", \ + "3573.5, 3573.5, 3573.5, 4715.5, 6997.2", \ + "3598.9, 3598.9, 3598.9, 4738.1, 7017.4", \ + "3628.9, 3628.9, 3628.9, 4773.3, 7058.7"); + } + rise_transition (inslew_load_5x5__32) { + values ("3007.5, 3007.5, 3007.5, 5008.5, 9022.2", \ + "3068.1, 3068.1, 3068.1, 5067.6, 9079.9", \ + "3152.1, 3152.1, 3152.1, 5149.8, 9160.7", \ + "3230.8, 3230.8, 3230.8, 5223.5, 9230.2", \ + "3316.7, 3316.7, 3316.7, 5316.9, 9333.9"); + } + cell_fall (inslew_load_5x5__32) { + values ("2011.8, 2011.8, 2011.8, 2579.3, 3709.8", \ + "2018.3, 2018.3, 2018.3, 2585.0, 3714.8", \ + "2028.2, 2028.2, 2028.2, 2595.4, 3726.0", \ + "2034.3, 2034.3, 2034.3, 2602.3, 3734.0", \ + "2055.4, 2055.4, 2055.4, 2625.5, 3755.4"); + } + fall_transition (inslew_load_5x5__32) { + values ("1705.4, 1705.4, 1705.4, 2684.1, 4644.4", \ + "1725.9, 1725.9, 1725.9, 2703.3, 4662.3", \ + "1753.3, 1753.3, 1753.3, 2731.6, 4692.0", \ + "1764.7, 1764.7, 1764.7, 2744.0, 4706.3", \ + "1799.4, 1799.4, 1799.4, 2765.8, 4715.0"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__32) { + values ("2758.2, 2758.2, 2758.2, 3615.5, 5324.2", \ + "2762.7, 2762.7, 2762.7, 3619.7, 5328.0", \ + "2771.0, 2771.0, 2771.0, 3628.6, 5337.8", \ + "2781.6, 2781.6, 2781.6, 3639.9, 5350.1", \ + "2814.1, 2814.1, 2814.1, 3671.8, 5380.1"); + } + rise_transition (inslew_load_5x5__32) { + values ("2101.7, 2101.7, 2101.7, 3461.1, 6183.7", \ + "2112.3, 2112.3, 2112.3, 3471.1, 6193.1", \ + "2126.9, 2126.9, 2126.9, 3486.7, 6210.1", \ + "2133.2, 2133.2, 2133.2, 3494.1, 6219.0", \ + "2149.7, 2149.7, 2149.7, 3503.8, 6223.5"); + } + cell_fall (inslew_load_5x5__32) { + values ("1546.2, 1546.2, 1546.2, 1973.6, 2824.5", \ + "1548.7, 1548.7, 1548.7, 1976.4, 2827.7", \ + "1557.4, 1557.4, 1557.4, 1984.5, 2835.0", \ + "1572.6, 1572.6, 1572.6, 2000.3, 2851.2", \ + "1581.2, 1581.2, 1581.2, 2024.4, 2883.2"); + } + fall_transition (inslew_load_5x5__32) { + values ("1119.5, 1119.5, 1119.5, 1786.2, 3120.5", \ + "1121.6, 1121.6, 1121.6, 1788.8, 3123.7", \ + "1125.7, 1125.7, 1125.7, 1791.8, 3125.5", \ + "1126.5, 1126.5, 1126.5, 1792.1, 3125.7", \ + "1146.7, 1146.7, 1146.7, 1808.2, 3131.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__32) { + values ("8433.5, 8433.5, 8433.5, 9543.0, 11790.0", \ + "8431.0, 8431.0, 8431.0, 9540.8, 11788.1", \ + "8419.3, 8419.3, 8419.3, 9529.3, 11776.7", \ + "8401.2, 8401.2, 8401.2, 9511.8, 11760.0", \ + "8361.4, 8361.4, 8361.4, 9472.6, 11721.5"); + } + rise_transition (inslew_load_5x5__32) { + values ("11389.4, 11389.4, 11389.4, 13364.2, 17315.8", \ + "11401.7, 11401.7, 11401.7, 13376.9, 17329.0", \ + "11411.6, 11411.6, 11411.6, 13386.9, 17339.1", \ + "11430.7, 11430.7, 11430.7, 13406.9, 17360.4", \ + "11440.5, 11440.5, 11440.5, 13417.4, 17371.9"); + } + cell_fall (inslew_load_5x5__32) { + values ("3877.5, 3877.5, 3877.5, 4430.8, 5545.8", \ + "3872.2, 3872.2, 3872.2, 4425.7, 5540.8", \ + "3862.7, 3862.7, 3862.7, 4416.5, 5532.0", \ + "3844.6, 3844.6, 3844.6, 4398.5, 5514.1", \ + "3811.7, 3811.7, 3811.7, 4365.8, 5481.5"); + } + fall_transition (inslew_load_5x5__32) { + values ("4837.9, 4837.9, 4837.9, 5802.9, 7733.7", \ + "4842.0, 4842.0, 4842.0, 5807.1, 7738.1", \ + "4846.4, 4846.4, 4846.4, 5812.0, 7743.7", \ + "4847.4, 4847.4, 4847.4, 5813.1, 7744.9", \ + "4849.1, 4849.1, 4849.1, 5814.0, 7745.1"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__32) { + values ("8433.5, 8433.5, 8433.5, 9543.0, 11790.0", \ + "8431.0, 8431.0, 8431.0, 9540.8, 11788.1", \ + "8419.3, 8419.3, 8419.3, 9529.3, 11776.7", \ + "8401.2, 8401.2, 8401.2, 9511.8, 11760.0", \ + "8361.4, 8361.4, 8361.4, 9472.6, 11721.5"); + } + rise_transition (inslew_load_5x5__32) { + values ("11389.4, 11389.4, 11389.4, 13364.2, 17315.8", \ + "11401.7, 11401.7, 11401.7, 13376.9, 17329.0", \ + "11411.6, 11411.6, 11411.6, 13386.9, 17339.1", \ + "11430.7, 11430.7, 11430.7, 13406.9, 17360.4", \ + "11440.5, 11440.5, 11440.5, 13417.4, 17371.9"); + } + cell_fall (inslew_load_5x5__32) { + values ("3877.5, 3877.5, 3877.5, 4430.8, 5545.8", \ + "3872.2, 3872.2, 3872.2, 4425.7, 5540.8", \ + "3862.7, 3862.7, 3862.7, 4416.5, 5532.0", \ + "3844.6, 3844.6, 3844.6, 4398.5, 5514.1", \ + "3811.7, 3811.7, 3811.7, 4365.8, 5481.5"); + } + fall_transition (inslew_load_5x5__32) { + values ("4837.9, 4837.9, 4837.9, 5802.9, 7733.7", \ + "4842.0, 4842.0, 4842.0, 5807.1, 7738.1", \ + "4846.4, 4846.4, 4846.4, 5812.0, 7743.7", \ + "4847.4, 4847.4, 4847.4, 5813.1, 7744.9", \ + "4849.1, 4849.1, 4849.1, 5814.0, 7745.1"); + } + } + internal_power (energy_pos_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__32) { + values ("22869.3, 22869.3, 22869.3, 24623.4, 28131.7", \ + "28147.0, 28147.0, 28147.0, 28147.0, 28147.0", \ + "28177.7, 28177.7, 28177.7, 28177.7, 28177.7", \ + "22977.1, 22977.1, 22977.1, 24731.2, 28239.5", \ + "23120.5, 23120.5, 23120.5, 24874.6, 28382.9"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("20108.1, 20108.1, 20108.1, 21862.2, 25370.4", \ + "25405.3, 25405.3, 25405.3, 25405.3, 25405.3", \ + "25475.0, 25475.0, 25475.0, 25475.0, 25475.0", \ + "25614.4, 25614.4, 25614.4, 25614.4, 25614.4", \ + "20631.5, 20631.5, 20631.5, 22385.6, 25893.9"); + } + } + internal_power (energy_pos_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__32) { + values ("8773.9, 8773.9, 8773.9, 10528.0, 14036.3", \ + "14051.6, 14051.6, 14051.6, 14051.6, 14051.6", \ + "14082.2, 14082.2, 14082.2, 14082.2, 14082.2", \ + "8881.4, 8881.4, 8881.4, 10635.6, 14143.8", \ + "9015.7, 9015.7, 9015.7, 10769.9, 14278.1"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("9080.5, 9080.5, 9080.5, 10834.6, 14342.9", \ + "14377.7, 14377.7, 14377.7, 14377.7, 14377.7", \ + "14447.4, 14447.4, 14447.4, 14447.4, 14447.4", \ + "14586.8, 14586.8, 14586.8, 14586.8, 14586.8", \ + "9603.6, 9603.6, 9603.6, 11357.7, 14865.9"); + } + } + internal_power (energy_neg_nq_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__32) { + values ("13776.8, 13776.8, 13776.8, 15530.9, 19039.2", \ + "13829.1, 13829.1, 13829.1, 15583.2, 19091.5", \ + "13933.7, 13933.7, 13933.7, 15687.8, 19196.1", \ + "14142.9, 14142.9, 14142.9, 15897.0, 19405.3", \ + "14561.4, 14561.4, 14561.4, 16315.5, 19823.7"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("10945.4, 10945.4, 10945.4, 12699.5, 16207.8", \ + "10966.7, 10966.7, 10966.7, 12720.9, 16229.1", \ + "11009.4, 11009.4, 11009.4, 12763.5, 16271.7", \ + "11094.6, 11094.6, 11094.6, 12848.7, 16357.0", \ + "11265.1, 11265.1, 11265.1, 13019.2, 16527.5"); + } + } + internal_power (energy_neg_nq_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__32) { + values ("1753.3, 1753.3, 1753.3, 3507.5, 7015.7", \ + "1782.6, 1782.6, 1782.6, 3536.8, 7045.0", \ + "1841.2, 1841.2, 1841.2, 3595.4, 7103.6", \ + "1958.5, 1958.5, 1958.5, 3712.6, 7220.8", \ + "2192.9, 2192.9, 2192.9, 3947.0, 7455.3"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("1796.2, 1796.2, 1796.2, 3550.4, 7058.6", \ + "1808.3, 1808.3, 1808.3, 3562.4, 7070.6", \ + "1832.3, 1832.3, 1832.3, 3586.4, 7094.7", \ + "1880.4, 1880.4, 1880.4, 3634.5, 7142.8", \ + "1976.6, 1976.6, 1976.6, 3730.7, 7238.9"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__32) { + values ("1761.7, 1761.7, 1761.7, 3515.8, 7024.1", \ + "1799.4, 1799.4, 1799.4, 3553.5, 7061.7", \ + "1874.7, 1874.7, 1874.7, 3628.8, 7137.1", \ + "2025.3, 2025.3, 2025.3, 3779.5, 7287.7", \ + "2326.6, 2326.6, 2326.6, 4080.8, 7589.0"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("1799.5, 1799.5, 1799.5, 3553.6, 7061.9", \ + "1814.8, 1814.8, 1814.8, 3569.0, 7077.2", \ + "1845.4, 1845.4, 1845.4, 3599.6, 7107.8", \ + "1906.7, 1906.7, 1906.7, 3660.8, 7169.0", \ + "2029.1, 2029.1, 2029.1, 3783.3, 7291.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__32) { + values ("9001.1, 9001.1, 9001.1, 10755.3, 14263.5", \ + "9038.8, 9038.8, 9038.8, 10792.9, 14301.2", \ + "9114.1, 9114.1, 9114.1, 10868.2, 14376.5", \ + "9264.8, 9264.8, 9264.8, 11018.9, 14527.1", \ + "9566.1, 9566.1, 9566.1, 11320.2, 14828.4"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("7442.3, 7442.3, 7442.3, 9196.4, 12704.7", \ + "7457.6, 7457.6, 7457.6, 9211.7, 12720.0", \ + "7488.2, 7488.2, 7488.2, 9242.3, 12750.6", \ + "7549.4, 7549.4, 7549.4, 9303.6, 12811.8", \ + "7671.9, 7671.9, 7671.9, 9426.0, 12934.3"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__32) { + values ("9001.1, 9001.1, 9001.1, 10755.3, 14263.5", \ + "9038.8, 9038.8, 9038.8, 10792.9, 14301.2", \ + "9114.1, 9114.1, 9114.1, 10868.2, 14376.5", \ + "9264.8, 9264.8, 9264.8, 11018.9, 14527.1", \ + "9566.1, 9566.1, 9566.1, 11320.2, 14828.4"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("7442.3, 7442.3, 7442.3, 9196.4, 12704.7", \ + "7457.6, 7457.6, 7457.6, 9211.7, 12720.0", \ + "7488.2, 7488.2, 7488.2, 9242.3, 12750.6", \ + "7549.4, 7549.4, 7549.4, 9303.6, 12811.8", \ + "7671.9, 7671.9, 7671.9, 9426.0, 12934.3"); + } + } + } + } + + cell (o4_x2) { + area : 25.20 ; + cell_leakage_power : 4.6 ; + leakage_power () { + when : "((i0 & i1 & i3) | (i1 & !(i2) & i3))" ; + value : 4 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3)) | (!(i1) & !(i2) & i3))) | (i1 & !(i2) & !(i3)))" ; + value : 3.9 ; + } + leakage_power () { + when : "((i0 & ((!(i1) & (i2 | !(i3))) | (i2 & !(i3)))) | (!(i0) & i2))" ; + value : 3.8 ; + } + leakage_power () { + when : "(i3 & !(i2) & !(i1) & !(i0))" ; + value : 4.1 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 7.2 ; + } + pin (i3) { + direction : input ; + capacitance : 571.41 ; + } + pin (i2) { + direction : input ; + capacitance : 573.81 ; + } + pin (i1) { + direction : input ; + capacitance : 572.31 ; + } + pin (i0) { + direction : input ; + capacitance : 573.81 ; + } + pin (q) { + function : "(i2 | i0 | i1 | i3)" ; + direction : output ; + capacitance : 89.13 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__33) { + values ("5344.8, 5344.8, 5344.8, 5682.5, 6295.8", \ + "5353.6, 5353.6, 5353.6, 5691.3, 6304.6", \ + "5371.2, 5371.2, 5371.2, 5708.9, 6322.2", \ + "5406.4, 5406.4, 5406.4, 5744.1, 6357.4", \ + "5477.3, 5477.3, 5477.3, 5815.0, 6428.2"); + } + rise_transition (inslew_load_5x5__33) { + values ("1534.4, 1534.4, 1534.4, 1826.1, 2371.4", \ + "1534.4, 1534.4, 1534.4, 1826.1, 2371.4", \ + "1534.4, 1534.4, 1534.4, 1826.1, 2371.4", \ + "1534.4, 1534.4, 1534.4, 1826.1, 2371.4", \ + "1535.2, 1535.2, 1535.2, 1826.8, 2372.1"); + } + cell_fall (inslew_load_5x5__33) { + values ("14727.3, 14727.3, 14727.3, 14983.0, 15482.1", \ + "14718.5, 14718.5, 14718.5, 14974.2, 15473.3", \ + "14698.1, 14698.1, 14698.1, 14953.8, 15453.0", \ + "14661.5, 14661.5, 14661.5, 14917.2, 15416.4", \ + "14587.2, 14587.2, 14587.2, 14842.9, 15342.1"); + } + fall_transition (inslew_load_5x5__33) { + values ("8761.3, 8761.3, 8761.3, 8959.1, 9337.7", \ + "8764.0, 8764.0, 8764.0, 8961.8, 9340.3", \ + "8766.1, 8766.1, 8766.1, 8963.9, 9342.4", \ + "8769.6, 8769.6, 8769.6, 8967.4, 9345.9", \ + "8770.2, 8770.2, 8770.2, 8968.0, 9346.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__33) { + values ("4586.6, 4586.6, 4586.6, 4955.3, 5587.5", \ + "4595.4, 4595.4, 4595.4, 4964.1, 5596.3", \ + "4613.0, 4613.0, 4613.0, 4981.7, 5613.9", \ + "4648.2, 4648.2, 4648.2, 5016.9, 5649.1", \ + "4719.5, 4719.5, 4719.5, 5088.1, 5720.2"); + } + rise_transition (inslew_load_5x5__33) { + values ("1013.0, 1013.0, 1013.0, 1321.6, 1887.5", \ + "1013.0, 1013.0, 1013.0, 1321.6, 1887.5", \ + "1013.0, 1013.0, 1013.0, 1321.6, 1887.5", \ + "1013.0, 1013.0, 1013.0, 1321.6, 1887.5", \ + "1014.5, 1014.5, 1014.5, 1323.1, 1889.0"); + } + cell_fall (inslew_load_5x5__33) { + values ("11242.7, 11242.7, 11242.7, 11589.9, 12257.9", \ + "11246.4, 11246.4, 11246.4, 11593.7, 12262.9", \ + "11246.5, 11246.5, 11246.5, 11593.9, 12265.0", \ + "11227.8, 11227.8, 11227.8, 11575.2, 12247.9", \ + "11201.5, 11201.5, 11201.5, 11547.8, 12222.8"); + } + fall_transition (inslew_load_5x5__33) { + values ("6504.9, 6504.9, 6504.9, 6696.5, 7018.4", \ + "6516.4, 6516.4, 6516.4, 6708.1, 7030.6", \ + "6532.5, 6532.5, 6532.5, 6724.5, 7047.9", \ + "6545.8, 6545.8, 6545.8, 6737.8, 7062.1", \ + "6566.2, 6566.2, 6566.2, 6758.4, 7084.0"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__33) { + values ("5838.8, 5838.8, 5838.8, 6171.3, 6771.1", \ + "5847.6, 5847.6, 5847.6, 6180.1, 6779.9", \ + "5865.2, 5865.2, 5865.2, 6197.7, 6797.5", \ + "5900.4, 5900.4, 5900.4, 6232.9, 6832.7", \ + "5971.0, 5971.0, 5971.0, 6303.5, 6903.2"); + } + rise_transition (inslew_load_5x5__33) { + values ("1874.7, 1874.7, 1874.7, 2160.3, 2686.3", \ + "1874.7, 1874.7, 1874.7, 2160.3, 2686.3", \ + "1874.7, 1874.7, 1874.7, 2160.3, 2686.3", \ + "1874.7, 1874.7, 1874.7, 2160.3, 2686.3", \ + "1875.2, 1875.2, 1875.2, 2160.8, 2686.7"); + } + cell_fall (inslew_load_5x5__33) { + values ("18476.2, 18476.2, 18476.2, 18717.1, 19175.6", \ + "18461.4, 18461.4, 18461.4, 18702.3, 19160.8", \ + "18431.8, 18431.8, 18431.8, 18672.7, 19131.2", \ + "18372.6, 18372.6, 18372.6, 18613.5, 19072.0", \ + "18254.3, 18254.3, 18254.3, 18495.2, 18953.7"); + } + fall_transition (inslew_load_5x5__33) { + values ("11168.0, 11168.0, 11168.0, 11342.8, 11668.0", \ + "11168.0, 11168.0, 11168.0, 11342.8, 11668.0", \ + "11168.0, 11168.0, 11168.0, 11342.8, 11668.0", \ + "11168.0, 11168.0, 11168.0, 11342.8, 11668.0", \ + "11168.0, 11168.0, 11168.0, 11342.8, 11668.0"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__33) { + values ("3928.9, 3928.9, 3928.9, 4275.3, 4853.6", \ + "3937.7, 3937.7, 3937.7, 4284.1, 4862.4", \ + "3955.3, 3955.3, 3955.3, 4301.7, 4880.0", \ + "3990.4, 3990.4, 3990.4, 4336.9, 4915.1", \ + "4058.4, 4058.4, 4058.4, 4405.2, 4983.8"); + } + rise_transition (inslew_load_5x5__33) { + values ("675.7, 675.7, 675.7, 984.9, 1539.5", \ + "675.7, 675.7, 675.7, 984.9, 1539.5", \ + "675.7, 675.7, 675.7, 984.9, 1539.5", \ + "675.7, 675.7, 675.7, 984.9, 1539.5", \ + "676.0, 676.0, 676.0, 985.4, 1540.2"); + } + cell_fall (inslew_load_5x5__33) { + values ("8033.5, 8033.5, 8033.5, 8289.4, 8769.3", \ + "8070.3, 8070.3, 8070.3, 8326.5, 8806.7", \ + "8119.0, 8119.0, 8119.0, 8375.6, 8856.3", \ + "8133.9, 8133.9, 8133.9, 8390.7, 8871.8", \ + "8207.8, 8207.8, 8207.8, 8465.2, 8947.2"); + } + fall_transition (inslew_load_5x5__33) { + values ("4130.8, 4130.8, 4130.8, 4274.2, 4595.6", \ + "4165.9, 4165.9, 4165.9, 4308.6, 4628.9", \ + "4216.6, 4216.6, 4216.6, 4358.1, 4677.0", \ + "4251.8, 4251.8, 4251.8, 4392.4, 4710.3", \ + "4341.5, 4341.5, 4341.5, 4480.1, 4795.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__33) { + values ("27042.5, 27042.5, 27042.5, 28156.7, 30385.0", \ + "30410.2, 30410.2, 30410.2, 30410.2, 30410.2", \ + "30460.6, 30460.6, 30460.6, 30460.6, 30460.6", \ + "30561.4, 30561.4, 30561.4, 30561.4, 30561.4", \ + "27422.2, 27422.2, 27422.2, 28536.4, 30764.7"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("55016.4, 55016.4, 55016.4, 56130.5, 58358.9", \ + "55069.0, 55069.0, 55069.0, 56183.2, 58411.5", \ + "55164.0, 55164.0, 55164.0, 56278.2, 58506.5", \ + "55352.0, 55352.0, 55352.0, 56466.2, 58694.5", \ + "55707.8, 55707.8, 55707.8, 56821.9, 59050.3"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__33) { + values ("23689.7, 23689.7, 23689.7, 24803.8, 27032.2", \ + "27050.1, 27050.1, 27050.1, 27050.1, 27050.1", \ + "27086.0, 27086.0, 27086.0, 27086.0, 27086.0", \ + "27157.8, 27157.8, 27157.8, 27157.8, 27157.8", \ + "23961.7, 23961.7, 23961.7, 25075.9, 27304.2"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("39974.7, 39974.7, 39974.7, 41088.9, 43317.2", \ + "40054.3, 40054.3, 40054.3, 41168.5, 43396.8", \ + "40192.3, 40192.3, 40192.3, 41306.5, 43534.8", \ + "40408.3, 40408.3, 40408.3, 41522.4, 43750.8", \ + "40821.0, 40821.0, 40821.0, 41935.2, 44163.5"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__33) { + values ("29378.2, 29378.2, 29378.2, 30492.4, 32720.7", \ + "32759.0, 32759.0, 32759.0, 32759.0, 32759.0", \ + "32835.5, 32835.5, 32835.5, 32835.5, 32835.5", \ + "32988.5, 32988.5, 32988.5, 32988.5, 32988.5", \ + "29953.1, 29953.1, 29953.1, 31067.3, 33295.6"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("69876.0, 69876.0, 69876.0, 70990.2, 73218.5", \ + "73262.0, 73262.0, 73262.0, 73262.0, 73262.0", \ + "73349.0, 73349.0, 73349.0, 73349.0, 73349.0", \ + "73522.9, 73522.9, 73522.9, 73522.9, 73522.9", \ + "73870.8, 73870.8, 73870.8, 73870.8, 73870.8"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__33) { + values ("17475.0, 17475.0, 17475.0, 18589.2, 20817.5", \ + "20831.0, 20831.0, 20831.0, 20831.0, 20831.0", \ + "20858.0, 20858.0, 20858.0, 20858.0, 20858.0", \ + "17569.7, 17569.7, 17569.7, 18683.9, 20912.2", \ + "17685.7, 17685.7, 17685.7, 18799.8, 21028.2"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("25343.3, 25343.3, 25343.3, 26457.5, 28685.8", \ + "25486.5, 25486.5, 25486.5, 26600.6, 28829.0", \ + "25716.2, 25716.2, 25716.2, 26830.4, 29058.7", \ + "25986.2, 25986.2, 25986.2, 27100.4, 29328.7", \ + "26581.5, 26581.5, 26581.5, 27695.7, 29924.0"); + } + } + } + } + + cell (no2_x1) { + area : 14.40 ; + cell_leakage_power : 2 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 1.4 ; + } + leakage_power () { + when : "i1" ; + value : 1.7 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 2.8 ; + } + pin (i1) { + direction : input ; + capacitance : 714.50 ; + } + pin (i0) { + direction : input ; + capacitance : 717.50 ; + } + pin (nq) { + function : "(!(i1) & !(i0))" ; + direction : output ; + capacitance : 88.82 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("4520.4, 4520.4, 4520.4, 4775.1, 5296.3", \ + "4515.0, 4515.0, 4515.0, 4769.7, 5290.9", \ + "4504.1, 4504.1, 4504.1, 4758.8, 5280.1", \ + "4482.3, 4482.3, 4482.3, 4737.1, 5258.6", \ + "4438.6, 4438.6, 4438.6, 4693.8, 5215.4"); + } + rise_transition (inslew_load_5x5__34) { + values ("5415.7, 5415.7, 5415.7, 5839.0, 6685.7", \ + "5415.7, 5415.7, 5415.7, 5839.0, 6685.7", \ + "5415.7, 5415.7, 5415.7, 5839.0, 6685.7", \ + "5415.7, 5415.7, 5415.7, 5839.0, 6685.7", \ + "5416.5, 5416.5, 5416.5, 5839.6, 6686.1"); + } + cell_fall (inslew_load_5x5__34) { + values ("2809.9, 2809.9, 2809.9, 3008.9, 3408.4", \ + "2818.7, 2818.7, 2818.7, 3017.7, 3417.2", \ + "2836.3, 2836.3, 2836.3, 3035.3, 3434.7", \ + "2871.4, 2871.4, 2871.4, 3070.4, 3469.9", \ + "2940.0, 2940.0, 2940.0, 3139.6, 3539.8"); + } + fall_transition (inslew_load_5x5__34) { + values ("2109.0, 2109.0, 2109.0, 2379.3, 2919.7", \ + "2109.0, 2109.0, 2109.0, 2379.3, 2919.7", \ + "2109.0, 2109.0, 2109.0, 2379.3, 2919.7", \ + "2109.1, 2109.1, 2109.1, 2379.3, 2919.8", \ + "2115.0, 2115.0, 2115.0, 2384.0, 2922.6"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__34) { + values ("1612.0, 1612.0, 1612.0, 1885.9, 2428.0", \ + "1616.8, 1616.8, 1616.8, 1890.6, 2432.3", \ + "1625.0, 1625.0, 1625.0, 1898.8, 2441.2", \ + "1635.2, 1635.2, 1635.2, 1909.4, 2452.5", \ + "1647.5, 1647.5, 1647.5, 1931.5, 2480.9"); + } + rise_transition (inslew_load_5x5__34) { + values ("955.0, 955.0, 955.0, 1385.6, 2244.3", \ + "966.0, 966.0, 966.0, 1396.3, 2254.5", \ + "980.2, 980.2, 980.2, 1410.6, 2269.7", \ + "986.5, 986.5, 986.5, 1416.9, 2276.5", \ + "1013.2, 1013.2, 1013.2, 1442.2, 2293.0"); + } + cell_fall (inslew_load_5x5__34) { + values ("1666.1, 1666.1, 1666.1, 1871.3, 2278.4", \ + "1674.9, 1674.9, 1674.9, 1880.1, 2287.2", \ + "1692.5, 1692.5, 1692.5, 1897.7, 2304.8", \ + "1727.3, 1727.3, 1727.3, 1932.7, 2340.0", \ + "1774.5, 1774.5, 1774.5, 1988.7, 2404.8"); + } + fall_transition (inslew_load_5x5__34) { + values ("619.2, 619.2, 619.2, 889.5, 1429.9", \ + "619.2, 619.2, 619.2, 889.5, 1429.9", \ + "619.2, 619.2, 619.2, 889.5, 1429.9", \ + "619.6, 619.6, 619.6, 889.8, 1430.1", \ + "629.5, 629.5, 629.5, 902.3, 1440.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__34) { + values ("12782.2, 12782.2, 12782.2, 13892.4, 16112.9", \ + "12822.1, 12822.1, 12822.1, 13932.3, 16152.8", \ + "12901.9, 12901.9, 12901.9, 14012.1, 16232.6", \ + "13061.5, 13061.5, 13061.5, 14171.7, 16392.2", \ + "13380.6, 13380.6, 13380.6, 14490.9, 16711.3"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("7308.1, 7308.1, 7308.1, 8418.3, 10638.8", \ + "7362.9, 7362.9, 7362.9, 8473.1, 10693.6", \ + "7472.5, 7472.5, 7472.5, 8582.7, 10803.1", \ + "7691.6, 7691.6, 7691.6, 8801.8, 11022.3", \ + "8129.9, 8129.9, 8129.9, 9240.2, 11460.6"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__34) { + values ("1131.4, 1131.4, 1131.4, 2241.6, 4462.0", \ + "1175.1, 1175.1, 1175.1, 2285.3, 4505.8", \ + "1262.5, 1262.5, 1262.5, 2372.8, 4593.2", \ + "1437.4, 1437.4, 1437.4, 2547.6, 4768.1", \ + "1787.2, 1787.2, 1787.2, 2897.4, 5117.9"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("1169.1, 1169.1, 1169.1, 2279.3, 4499.7", \ + "1205.3, 1205.3, 1205.3, 2315.5, 4536.0", \ + "1277.8, 1277.8, 1277.8, 2388.0, 4608.5", \ + "1422.8, 1422.8, 1422.8, 2533.0, 4753.4", \ + "1712.7, 1712.7, 1712.7, 2822.9, 5043.4"); + } + } + } + } + + cell (oa22_x4) { + area : 28.80 ; + cell_leakage_power : 6.5 ; + leakage_power () { + when : "(i0 & i1)" ; + value : 7.2 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & i0)" ; + value : 6.1 ; + } + leakage_power () { + when : "((i0 ^ i1) & i2)" ; + value : 7.1 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0))" ; + value : 5.9 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 7 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 5.4 ; + } + pin (i2) { + direction : input ; + capacitance : 440.12 ; + } + pin (i1) { + direction : input ; + capacitance : 432.62 ; + } + pin (i0) { + direction : input ; + capacitance : 432.96 ; + } + pin (q) { + function : "((i0 & (i2 | i1)) | i2)" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("11407.3, 11407.3, 11407.3, 11647.3, 12106.1", \ + "11402.1, 11402.1, 11402.1, 11642.1, 12100.9", \ + "11391.8, 11391.8, 11391.8, 11631.8, 12090.6", \ + "11371.2, 11371.2, 11371.2, 11611.2, 12070.0", \ + "11330.0, 11330.0, 11330.0, 11570.0, 12028.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("6012.4, 6012.4, 6012.4, 6206.7, 6592.2", \ + "6012.4, 6012.4, 6012.4, 6206.7, 6592.2", \ + "6012.4, 6012.4, 6012.4, 6206.7, 6592.2", \ + "6012.4, 6012.4, 6012.4, 6206.7, 6592.2", \ + "6012.4, 6012.4, 6012.4, 6206.7, 6592.2"); + } + cell_fall (inslew_load_5x5__3) { + values ("12209.4, 12209.4, 12209.4, 12512.3, 13098.8", \ + "12216.8, 12216.8, 12216.8, 12519.8, 13107.1", \ + "12222.2, 12222.2, 12222.2, 12525.2, 13113.1", \ + "12239.0, 12239.0, 12239.0, 12542.0, 13131.2", \ + "12261.5, 12261.5, 12261.5, 12564.5, 13154.0"); + } + fall_transition (inslew_load_5x5__3) { + values ("6206.8, 6206.8, 6206.8, 6368.4, 6635.0", \ + "6213.1, 6213.1, 6213.1, 6374.8, 6641.9", \ + "6218.3, 6218.3, 6218.3, 6380.1, 6647.5", \ + "6228.0, 6228.0, 6228.0, 6389.9, 6658.0", \ + "6230.3, 6230.3, 6230.3, 6392.2, 6660.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("10283.7, 10283.7, 10283.7, 10523.3, 10991.0", \ + "10288.5, 10288.5, 10288.5, 10528.2, 10995.8", \ + "10295.1, 10295.1, 10295.1, 10534.7, 11002.3", \ + "10311.9, 10311.9, 10311.9, 10551.5, 11019.1", \ + "10345.6, 10345.6, 10345.6, 10585.2, 11052.8"); + } + rise_transition (inslew_load_5x5__3) { + values ("5329.6, 5329.6, 5329.6, 5526.2, 5916.5", \ + "5332.1, 5332.1, 5332.1, 5528.6, 5919.0", \ + "5332.4, 5332.4, 5332.4, 5529.0, 5919.4", \ + "5332.9, 5332.9, 5332.9, 5529.4, 5919.8", \ + "5332.9, 5332.9, 5332.9, 5529.4, 5919.8"); + } + cell_fall (inslew_load_5x5__3) { + values ("11610.0, 11610.0, 11610.0, 11909.1, 12450.7", \ + "11617.4, 11617.4, 11617.4, 11917.5, 12459.0", \ + "11622.8, 11622.8, 11622.8, 11923.1, 12465.0", \ + "11639.5, 11639.5, 11639.5, 11940.2, 12483.1", \ + "11662.0, 11662.0, 11662.0, 11962.8, 12505.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("5838.1, 5838.1, 5838.1, 5994.1, 6240.9", \ + "5844.4, 5844.4, 5844.4, 6000.7, 6247.8", \ + "5849.7, 5849.7, 5849.7, 6006.2, 6253.4", \ + "5859.5, 5859.5, 5859.5, 6016.4, 6263.7", \ + "5861.7, 5861.7, 5861.7, 6018.7, 6266.1"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("7140.6, 7140.6, 7140.6, 7406.1, 7902.6", \ + "7149.4, 7149.4, 7149.4, 7414.9, 7911.4", \ + "7167.0, 7167.0, 7167.0, 7432.5, 7929.0", \ + "7202.2, 7202.2, 7202.2, 7467.7, 7964.2", \ + "7272.7, 7272.7, 7272.7, 7538.2, 8034.7"); + } + rise_transition (inslew_load_5x5__3) { + values ("2918.3, 2918.3, 2918.3, 3139.6, 3563.8", \ + "2918.3, 2918.3, 2918.3, 3139.6, 3563.8", \ + "2918.3, 2918.3, 2918.3, 3139.6, 3563.8", \ + "2918.3, 2918.3, 2918.3, 3139.6, 3563.8", \ + "2918.5, 2918.5, 2918.5, 3139.8, 3564.0"); + } + cell_fall (inslew_load_5x5__3) { + values ("14025.8, 14025.8, 14025.8, 14240.9, 14793.0", \ + "14020.4, 14020.4, 14020.4, 14235.5, 14787.6", \ + "14009.7, 14009.7, 14009.7, 14224.8, 14776.9", \ + "13988.3, 13988.3, 13988.3, 14203.4, 14755.5", \ + "13945.4, 13945.4, 13945.4, 14160.5, 14712.6"); + } + fall_transition (inslew_load_5x5__3) { + values ("7156.6, 7156.6, 7156.6, 7323.0, 7619.0", \ + "7156.6, 7156.6, 7156.6, 7323.0, 7619.0", \ + "7156.6, 7156.6, 7156.6, 7323.0, 7619.0", \ + "7156.6, 7156.6, 7156.6, 7323.0, 7619.0", \ + "7156.6, 7156.6, 7156.6, 7323.0, 7619.0"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("64813.2, 64813.2, 64813.2, 66709.0, 70500.7", \ + "70515.1, 70515.1, 70515.1, 70515.1, 70515.1", \ + "70543.8, 70543.8, 70543.8, 70543.8, 70543.8", \ + "70601.2, 70601.2, 70601.2, 70601.2, 70601.2", \ + "70716.1, 70716.1, 70716.1, 70716.1, 70716.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("62414.8, 62414.8, 62414.8, 64310.7, 68102.3", \ + "62496.6, 62496.6, 62496.6, 64392.4, 68184.1", \ + "62614.2, 62614.2, 62614.2, 64510.0, 68301.7", \ + "62844.5, 62844.5, 62844.5, 64740.4, 68532.0", \ + "63199.7, 63199.7, 63199.7, 65095.5, 68887.2"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("58014.4, 58014.4, 58014.4, 59910.2, 63701.9", \ + "58039.6, 58039.6, 58039.6, 59935.4, 63727.1", \ + "58064.0, 58064.0, 58064.0, 59959.8, 63751.5", \ + "58110.9, 58110.9, 58110.9, 60006.7, 63798.4", \ + "63887.3, 63887.3, 63887.3, 63887.3, 63887.3"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("58553.7, 58553.7, 58553.7, 60449.5, 64241.2", \ + "58633.6, 58633.6, 58633.6, 60529.4, 64321.1", \ + "58747.8, 58747.8, 58747.8, 60643.7, 64435.4", \ + "58971.5, 58971.5, 58971.5, 60867.3, 64659.0", \ + "59313.1, 59313.1, 59313.1, 61208.9, 65000.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("49759.0, 49759.0, 49759.0, 51654.8, 55446.5", \ + "55469.4, 55469.4, 55469.4, 55469.4, 55469.4", \ + "55515.2, 55515.2, 55515.2, 55515.2, 55515.2", \ + "55606.8, 55606.8, 55606.8, 55606.8, 55606.8", \ + "50103.5, 50103.5, 50103.5, 51999.4, 55791.0"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("72838.4, 72838.4, 72838.4, 74734.3, 78525.9", \ + "78570.0, 78570.0, 78570.0, 78570.0, 78570.0", \ + "78658.2, 78658.2, 78658.2, 78658.2, 78658.2", \ + "78834.5, 78834.5, 78834.5, 78834.5, 78834.5", \ + "79187.2, 79187.2, 79187.2, 79187.2, 79187.2"); + } + } + } + } + + cell (nao22_x4) { + area : 36.00 ; + cell_leakage_power : 7.8 ; + leakage_power () { + when : "(!(i2) & i1 & i0)" ; + value : 8.8 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0)" ; + value : 6.3 ; + } + leakage_power () { + when : "(i1 & i2)" ; + value : 6.4 ; + } + leakage_power () { + when : "((i0 ^ i1) & !(i2))" ; + value : 8.3 ; + } + leakage_power () { + when : "(i2 & !(i1) & !(i0))" ; + value : 9.2 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0))" ; + value : 7.8 ; + } + pin (i2) { + direction : input ; + capacitance : 439.56 ; + } + pin (i1) { + direction : input ; + capacitance : 431.91 ; + } + pin (i0) { + direction : input ; + capacitance : 434.21 ; + } + pin (nq) { + function : "(!((i0 | i1)) | !(i2))" ; + direction : output ; + capacitance : 151.67 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("15958.7, 15958.7, 15958.7, 16215.3, 16700.7", \ + "15953.4, 15953.4, 15953.4, 16210.0, 16695.4", \ + "15942.6, 15942.6, 15942.6, 16199.2, 16684.6", \ + "15921.2, 15921.2, 15921.2, 16177.8, 16663.2", \ + "15878.2, 15878.2, 15878.2, 16134.8, 16620.2"); + } + rise_transition (inslew_load_5x5__3) { + values ("4106.5, 4106.5, 4106.5, 4310.6, 4709.5", \ + "4106.5, 4106.5, 4106.5, 4310.6, 4709.5", \ + "4106.5, 4106.5, 4106.5, 4310.6, 4709.5", \ + "4106.5, 4106.5, 4106.5, 4310.6, 4709.5", \ + "4106.5, 4106.5, 4106.5, 4310.6, 4709.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("12500.3, 12500.3, 12500.3, 12711.3, 13124.0", \ + "12509.2, 12509.2, 12509.2, 12720.3, 13132.9", \ + "12517.8, 12517.8, 12517.8, 12728.8, 13141.5", \ + "12534.0, 12534.0, 12534.0, 12745.0, 13157.7", \ + "12567.4, 12567.4, 12567.4, 12778.4, 13191.1"); + } + fall_transition (inslew_load_5x5__3) { + values ("3179.1, 3179.1, 3179.1, 3332.8, 3654.3", \ + "3181.0, 3181.0, 3181.0, 3334.6, 3656.0", \ + "3182.0, 3182.0, 3182.0, 3335.6, 3657.0", \ + "3182.6, 3182.6, 3182.6, 3336.1, 3657.5", \ + "3182.9, 3182.9, 3182.9, 3336.4, 3657.8"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("12308.0, 12308.0, 12308.0, 12572.5, 13063.2", \ + "12314.1, 12314.1, 12314.1, 12578.7, 13069.2", \ + "12328.2, 12328.2, 12328.2, 12592.7, 13083.1", \ + "12342.8, 12342.8, 12342.8, 12607.3, 13097.5", \ + "12373.7, 12373.7, 12373.7, 12638.2, 13128.3"); + } + rise_transition (inslew_load_5x5__3) { + values ("3055.6, 3055.6, 3055.6, 3274.9, 3695.6", \ + "3058.0, 3058.0, 3058.0, 3277.4, 3698.0", \ + "3062.5, 3062.5, 3062.5, 3281.7, 3702.2", \ + "3064.8, 3064.8, 3064.8, 3284.0, 3704.4", \ + "3065.9, 3065.9, 3065.9, 3285.1, 3705.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("11246.1, 11246.1, 11246.1, 11457.2, 11888.1", \ + "11251.9, 11251.9, 11251.9, 11463.0, 11893.8", \ + "11258.4, 11258.4, 11258.4, 11469.5, 11900.3", \ + "11274.3, 11274.3, 11274.3, 11485.5, 11916.2", \ + "11306.6, 11306.6, 11306.6, 11517.7, 11948.4"); + } + fall_transition (inslew_load_5x5__3) { + values ("2977.5, 2977.5, 2977.5, 3139.6, 3462.4", \ + "2977.8, 2977.8, 2977.8, 3140.0, 3462.7", \ + "2978.0, 2978.0, 2978.0, 3140.1, 3462.8", \ + "2978.1, 2978.1, 2978.1, 3140.3, 3463.0", \ + "2978.3, 2978.3, 2978.3, 3140.4, 3463.2"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__3) { + values ("10699.5, 10699.5, 10699.5, 10971.0, 11485.3", \ + "10708.3, 10708.3, 10708.3, 10979.8, 11494.1", \ + "10725.9, 10725.9, 10725.9, 10997.4, 11511.7", \ + "10761.1, 10761.1, 10761.1, 11032.6, 11546.9", \ + "10831.8, 10831.8, 10831.8, 11103.4, 11617.6"); + } + rise_transition (inslew_load_5x5__3) { + values ("2563.1, 2563.1, 2563.1, 2793.8, 3230.0", \ + "2563.1, 2563.1, 2563.1, 2793.8, 3230.0", \ + "2563.1, 2563.1, 2563.1, 2793.8, 3230.0", \ + "2563.1, 2563.1, 2563.1, 2793.8, 3230.0", \ + "2563.5, 2563.5, 2563.5, 2794.2, 3230.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("12653.2, 12653.2, 12653.2, 12864.3, 13277.0", \ + "12648.1, 12648.1, 12648.1, 12859.2, 13271.9", \ + "12637.7, 12637.7, 12637.7, 12848.8, 13261.5", \ + "12617.1, 12617.1, 12617.1, 12828.2, 13240.9", \ + "12576.7, 12576.7, 12576.7, 12787.8, 13200.5"); + } + fall_transition (inslew_load_5x5__3) { + values ("3204.2, 3204.2, 3204.2, 3356.9, 3677.5", \ + "3204.2, 3204.2, 3204.2, 3356.9, 3677.5", \ + "3204.2, 3204.2, 3204.2, 3356.9, 3677.5", \ + "3204.2, 3204.2, 3204.2, 3356.9, 3677.5", \ + "3204.7, 3204.7, 3204.7, 3357.3, 3677.9"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__3) { + values ("67831.2, 67831.2, 67831.2, 69727.0, 73518.7", \ + "73550.2, 73550.2, 73550.2, 73550.2, 73550.2", \ + "73613.4, 73613.4, 73613.4, 73613.4, 73613.4", \ + "73739.6, 73739.6, 73739.6, 73739.6, 73739.6", \ + "73992.1, 73992.1, 73992.1, 73992.1, 73992.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("55855.5, 55855.5, 55855.5, 57751.3, 61543.0", \ + "55898.5, 55898.5, 55898.5, 57794.3, 61586.0", \ + "55958.8, 55958.8, 55958.8, 57854.7, 61646.3", \ + "56064.7, 56064.7, 56064.7, 57960.5, 61752.2", \ + "56269.5, 56269.5, 56269.5, 58165.3, 61957.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__3) { + values ("54608.2, 54608.2, 54608.2, 56504.0, 60295.7", \ + "54665.4, 54665.4, 54665.4, 56561.3, 60353.0", \ + "54776.8, 54776.8, 54776.8, 56672.6, 60464.3", \ + "54956.0, 54956.0, 54956.0, 56851.8, 60643.5", \ + "55291.0, 55291.0, 55291.0, 57186.9, 60978.5"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("50953.8, 50953.8, 50953.8, 52849.7, 56641.4", \ + "50973.9, 50973.9, 50973.9, 52869.8, 56661.4", \ + "51000.7, 51000.7, 51000.7, 52896.5, 56688.2", \ + "51048.8, 51048.8, 51048.8, 52944.6, 56736.3", \ + "51142.3, 51142.3, 51142.3, 53038.2, 56829.8"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__3) { + values ("54061.5, 54061.5, 54061.5, 55957.3, 59749.0", \ + "59793.1, 59793.1, 59793.1, 59793.1, 59793.1", \ + "59881.2, 59881.2, 59881.2, 59881.2, 59881.2", \ + "60057.6, 60057.6, 60057.6, 60057.6, 60057.6", \ + "54725.7, 54725.7, 54725.7, 56621.5, 60413.2"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("56459.6, 56459.6, 56459.6, 58355.5, 62147.2", \ + "62170.1, 62170.1, 62170.1, 62170.1, 62170.1", \ + "62215.9, 62215.9, 62215.9, 62215.9, 62215.9", \ + "62307.5, 62307.5, 62307.5, 62307.5, 62307.5", \ + "56807.4, 56807.4, 56807.4, 58703.2, 62494.9"); + } + } + } + } + + cell (oa2a2a23_x2) { + area : 43.20 ; + cell_leakage_power : 9.8 ; + leakage_power () { + when : "(i5 & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 9.9 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))) | (!(i0) & i1 & i2 & !(i3) & !(i4) & i5))" ; + value : 9.5 ; + } + leakage_power () { + when : "(!(i5) & i4 & i3 & !(i2) & i1 & !(i0))" ; + value : 8.8 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & i3 & i4 & !(i5)) | (!(i0) & i1 & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))))" ; + value : 9.2 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((!(i3) & (i4 | i5)) | (i4 ^ i5))) | (!(i2) & i3 & (i4 | i5)))) | (!(i1) & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))))) | (!(i0) & ((i1 & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))) | (i2 & i3 & (i4 ^ i5)))))" ; + value : 15 ; + } + leakage_power () { + when : "((i0 & i1 & (!((i2 | i3)) | (!(i4) & !(i5)))) | (i2 & i3 & !(i4) & !(i5)))" ; + value : 14 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i0) & !(i1) & i2 & !(i3) & !(i4) & i5))" ; + value : 8.6 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & (i3 ^ i4) & !(i5)) | (!(i1) & !(i2) & i3 & i4 & !(i5))))" ; + value : 7.8 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & (i3 ^ i4) & !(i5)) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))) | (!(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & !(i4) & i5))))))" ; + value : 8.2 ; + } + leakage_power () { + when : "((!(i0) & !((i1 & !(i2) & !(i3))) & i4 & i5) | (!(i1) & (i2 | i3) & i4 & i5) | (i2 & i3 & i4 & i5))" ; + value : 16 ; + } + leakage_power () { + when : "(!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i1) & !(i2) & (i3 ^ i4) & !(i5))))" ; + value : 6.8 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i0) & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & !(i3) & !(i4) & i5))))" ; + value : 7.2 ; + } + leakage_power () { + when : "(!(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.8 ; + } + pin (i5) { + direction : input ; + capacitance : 845.77 ; + } + pin (i4) { + direction : input ; + capacitance : 848.32 ; + } + pin (i3) { + direction : input ; + capacitance : 845.17 ; + } + pin (i2) { + direction : input ; + capacitance : 844.87 ; + } + pin (i1) { + direction : input ; + capacitance : 844.57 ; + } + pin (i0) { + direction : input ; + capacitance : 843.97 ; + } + pin (q) { + function : "((i4 & ((i2 & ((i1 & i0) | i3 | i5)) | (i1 & i0) | i5)) | (i2 & ((i1 & i0) | i3)) | (i1 & i0))" ; + direction : output ; + capacitance : 86.05 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("8423.4, 8423.4, 8423.4, 8710.8, 9249.7", \ + "8418.2, 8418.2, 8418.2, 8705.6, 9244.5", \ + "8407.9, 8407.9, 8407.9, 8695.3, 9234.2", \ + "8387.3, 8387.3, 8387.3, 8674.7, 9213.6", \ + "8346.1, 8346.1, 8346.1, 8633.4, 9172.4"); + } + rise_transition (inslew_load_5x5__18) { + values ("4013.0, 4013.0, 4013.0, 4245.6, 4695.6", \ + "4013.0, 4013.0, 4013.0, 4245.6, 4695.6", \ + "4013.0, 4013.0, 4013.0, 4245.6, 4695.6", \ + "4013.0, 4013.0, 4013.0, 4245.6, 4695.6", \ + "4013.1, 4013.1, 4013.1, 4245.7, 4695.7"); + } + cell_fall (inslew_load_5x5__18) { + values ("13356.2, 13356.2, 13356.2, 13602.4, 14309.7", \ + "13344.9, 13344.9, 13344.9, 13591.1, 14298.4", \ + "13322.2, 13322.2, 13322.2, 13568.4, 14275.7", \ + "13276.7, 13276.7, 13276.7, 13522.9, 14230.2", \ + "13185.9, 13185.9, 13185.9, 13432.1, 14139.4"); + } + fall_transition (inslew_load_5x5__18) { + values ("7114.9, 7114.9, 7114.9, 7303.5, 7676.4", \ + "7114.9, 7114.9, 7114.9, 7303.5, 7676.4", \ + "7114.9, 7114.9, 7114.9, 7303.5, 7676.4", \ + "7114.9, 7114.9, 7114.9, 7303.5, 7676.4", \ + "7114.9, 7114.9, 7114.9, 7303.5, 7676.4"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("7218.9, 7218.9, 7218.9, 7512.2, 8053.6", \ + "7223.8, 7223.8, 7223.8, 7517.1, 8058.5", \ + "7231.1, 7231.1, 7231.1, 7524.4, 8065.7", \ + "7247.7, 7247.7, 7247.7, 7541.0, 8082.4", \ + "7281.2, 7281.2, 7281.2, 7574.5, 8115.9"); + } + rise_transition (inslew_load_5x5__18) { + values ("3229.6, 3229.6, 3229.6, 3471.5, 3937.9", \ + "3232.1, 3232.1, 3232.1, 3473.9, 3940.3", \ + "3232.8, 3232.8, 3232.8, 3474.6, 3941.0", \ + "3233.0, 3233.0, 3233.0, 3474.9, 3941.2", \ + "3233.1, 3233.1, 3233.1, 3474.9, 3941.3"); + } + cell_fall (inslew_load_5x5__18) { + values ("12516.4, 12516.4, 12516.4, 12973.3, 13487.0", \ + "12505.1, 12505.1, 12505.1, 12962.0, 13475.7", \ + "12482.4, 12482.4, 12482.4, 12939.3, 13453.0", \ + "12437.0, 12437.0, 12437.0, 12893.9, 13407.6", \ + "12346.1, 12346.1, 12346.1, 12803.0, 13316.7"); + } + fall_transition (inslew_load_5x5__18) { + values ("6610.3, 6610.3, 6610.3, 6874.6, 7135.8", \ + "6610.3, 6610.3, 6610.3, 6874.6, 7135.8", \ + "6610.3, 6610.3, 6610.3, 6874.6, 7135.8", \ + "6610.3, 6610.3, 6610.3, 6874.6, 7135.8", \ + "6610.3, 6610.3, 6610.3, 6874.6, 7135.8"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("7038.6, 7038.6, 7038.6, 7333.2, 7880.0", \ + "7033.4, 7033.4, 7033.4, 7328.0, 7874.8", \ + "7023.1, 7023.1, 7023.1, 7317.7, 7864.5", \ + "7002.5, 7002.5, 7002.5, 7297.1, 7843.9", \ + "6961.4, 6961.4, 6961.4, 7255.9, 7802.7"); + } + rise_transition (inslew_load_5x5__18) { + values ("3077.2, 3077.2, 3077.2, 3321.4, 3791.3", \ + "3077.2, 3077.2, 3077.2, 3321.4, 3791.3", \ + "3077.2, 3077.2, 3077.2, 3321.4, 3791.3", \ + "3077.2, 3077.2, 3077.2, 3321.4, 3791.3", \ + "3077.5, 3077.5, 3077.5, 3321.7, 3791.5"); + } + cell_fall (inslew_load_5x5__18) { + values ("10373.8, 10373.8, 10373.8, 10637.4, 11121.2", \ + "10370.6, 10370.6, 10370.6, 10634.4, 11118.2", \ + "10357.3, 10357.3, 10357.3, 10621.1, 11105.0", \ + "10338.5, 10338.5, 10338.5, 10602.5, 11086.5", \ + "10297.5, 10297.5, 10297.5, 10561.6, 11045.7"); + } + fall_transition (inslew_load_5x5__18) { + values ("5257.1, 5257.1, 5257.1, 5388.3, 5661.9", \ + "5261.5, 5261.5, 5261.5, 5392.7, 5666.2", \ + "5264.5, 5264.5, 5264.5, 5395.8, 5669.1", \ + "5272.5, 5272.5, 5272.5, 5403.8, 5677.1", \ + "5277.7, 5277.7, 5277.7, 5409.0, 5682.1"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("5740.2, 5740.2, 5740.2, 6056.6, 6628.0", \ + "5745.2, 5745.2, 5745.2, 6061.6, 6632.9", \ + "5752.7, 5752.7, 5752.7, 6069.1, 6640.3", \ + "5769.3, 5769.3, 5769.3, 6085.6, 6656.8", \ + "5803.0, 5803.0, 5803.0, 6119.3, 6690.5"); + } + rise_transition (inslew_load_5x5__18) { + values ("2187.4, 2187.4, 2187.4, 2454.9, 2948.8", \ + "2190.1, 2190.1, 2190.1, 2457.5, 2951.4", \ + "2191.0, 2191.0, 2191.0, 2458.5, 2952.2", \ + "2191.2, 2191.2, 2191.2, 2458.7, 2952.5", \ + "2191.6, 2191.6, 2191.6, 2459.1, 2952.8"); + } + cell_fall (inslew_load_5x5__18) { + values ("9549.5, 9549.5, 9549.5, 9804.1, 10279.7", \ + "9546.3, 9546.3, 9546.3, 9800.9, 10276.6", \ + "9533.0, 9533.0, 9533.0, 9787.7, 10263.3", \ + "9514.3, 9514.3, 9514.3, 9769.0, 10244.8", \ + "9473.2, 9473.2, 9473.2, 9728.0, 10203.8"); + } + fall_transition (inslew_load_5x5__18) { + values ("4705.9, 4705.9, 4705.9, 4836.2, 5126.2", \ + "4710.4, 4710.4, 4710.4, 4840.6, 5130.6", \ + "4713.3, 4713.3, 4713.3, 4843.5, 5133.4", \ + "4721.5, 4721.5, 4721.5, 4851.5, 5141.1", \ + "4726.5, 4726.5, 4726.5, 4856.5, 5145.9"); + } + } + timing (maxd_q_i4_positive_unate) { + related_pin : "i4" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("3668.8, 3668.8, 3668.8, 4026.8, 4615.0", \ + "3670.7, 3670.7, 3670.7, 4028.9, 4617.4", \ + "3677.4, 3677.4, 3677.4, 4035.7, 4624.4", \ + "3693.6, 3693.6, 3693.6, 4051.9, 4640.6", \ + "3724.2, 3724.2, 3724.2, 4082.8, 4671.8"); + } + rise_transition (inslew_load_5x5__18) { + values ("684.0, 684.0, 684.0, 995.0, 1536.6", \ + "684.2, 684.2, 684.2, 995.3, 1537.0", \ + "684.3, 684.3, 684.3, 995.5, 1537.2", \ + "684.3, 684.3, 684.3, 995.5, 1537.2", \ + "684.6, 684.6, 684.6, 995.9, 1537.7"); + } + cell_fall (inslew_load_5x5__18) { + values ("6046.0, 6046.0, 6046.0, 6349.4, 6869.8", \ + "6074.0, 6074.0, 6074.0, 6370.1, 6895.0", \ + "6111.4, 6111.4, 6111.4, 6396.7, 6928.0", \ + "6121.6, 6121.6, 6121.6, 6399.5, 6935.5", \ + "6180.4, 6180.4, 6180.4, 6440.7, 6987.8"); + } + fall_transition (inslew_load_5x5__18) { + values ("2439.4, 2439.4, 2439.4, 2653.8, 2975.1", \ + "2461.5, 2461.5, 2461.5, 2674.0, 2997.7", \ + "2493.4, 2493.4, 2493.4, 2703.0, 3030.6", \ + "2515.3, 2515.3, 2515.3, 2722.8, 3053.0", \ + "2573.6, 2573.6, 2573.6, 2775.8, 3113.8"); + } + } + timing (maxd_q_i5_positive_unate) { + related_pin : "i5" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("4742.7, 4742.7, 4742.7, 5072.9, 5670.9", \ + "4737.5, 4737.5, 4737.5, 5067.7, 5665.7", \ + "4727.2, 4727.2, 4727.2, 5057.4, 5655.4", \ + "4706.6, 4706.6, 4706.6, 5036.8, 5634.8", \ + "4666.4, 4666.4, 4666.4, 4996.5, 5594.4"); + } + rise_transition (inslew_load_5x5__18) { + values ("1426.9, 1426.9, 1426.9, 1708.6, 2239.7", \ + "1426.9, 1426.9, 1426.9, 1708.6, 2239.7", \ + "1426.9, 1426.9, 1426.9, 1708.6, 2239.7", \ + "1426.9, 1426.9, 1426.9, 1708.6, 2239.7", \ + "1428.8, 1428.8, 1428.8, 1710.5, 2241.4"); + } + cell_fall (inslew_load_5x5__18) { + values ("7020.7, 7020.7, 7020.7, 7187.6, 7710.6", \ + "7046.6, 7046.6, 7046.6, 7289.8, 7734.3", \ + "7080.6, 7080.6, 7080.6, 7324.4, 7765.1", \ + "7087.9, 7087.9, 7087.9, 7331.8, 7770.3", \ + "7143.0, 7143.0, 7143.0, 7387.2, 7828.9"); + } + fall_transition (inslew_load_5x5__18) { + values ("3082.5, 3082.5, 3082.5, 3179.5, 3563.2", \ + "3104.5, 3104.5, 3104.5, 3271.3, 3586.2", \ + "3136.4, 3136.4, 3136.4, 3302.6, 3619.5", \ + "3157.8, 3157.8, 3157.8, 3323.0, 3641.8", \ + "3216.9, 3216.9, 3216.9, 3380.3, 3700.1"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__18) { + values ("48467.3, 48467.3, 48467.3, 49543.0, 51694.3", \ + "51740.0, 51740.0, 51740.0, 51740.0, 51740.0", \ + "51831.5, 51831.5, 51831.5, 51831.5, 51831.5", \ + "52014.3, 52014.3, 52014.3, 52014.3, 52014.3", \ + "49153.2, 49153.2, 49153.2, 50228.8, 52380.2"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("62847.9, 62847.9, 62847.9, 63923.6, 66074.9", \ + "66163.3, 66163.3, 66163.3, 66163.3, 66163.3", \ + "66340.1, 66340.1, 66340.1, 66340.1, 66340.1", \ + "66693.7, 66693.7, 66693.7, 66693.7, 66693.7", \ + "67400.9, 67400.9, 67400.9, 67400.9, 67400.9"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__18) { + values ("40751.2, 40751.2, 40751.2, 41826.9, 43978.2", \ + "40808.0, 40808.0, 40808.0, 41883.6, 44035.0", \ + "40910.5, 40910.5, 40910.5, 41986.2, 44137.5", \ + "41112.9, 41112.9, 41112.9, 42188.5, 44339.9", \ + "41516.3, 41516.3, 41516.3, 42591.9, 44743.3"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("58045.3, 58045.3, 58045.3, 59121.0, 61272.3", \ + "61335.5, 61335.5, 61335.5, 61335.5, 61335.5", \ + "61461.8, 61461.8, 61461.8, 61461.8, 61461.8", \ + "61714.4, 61714.4, 61714.4, 61714.4, 61714.4", \ + "62219.6, 62219.6, 62219.6, 62219.6, 62219.6"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__18) { + values ("39848.1, 39848.1, 39848.1, 40923.8, 43075.1", \ + "43103.9, 43103.9, 43103.9, 43103.9, 43103.9", \ + "43161.4, 43161.4, 43161.4, 43161.4, 43161.4", \ + "43276.4, 43276.4, 43276.4, 43276.4, 43276.4", \ + "40280.1, 40280.1, 40280.1, 41355.8, 43507.1"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("44646.4, 44646.4, 44646.4, 45722.1, 47873.4", \ + "44744.8, 44744.8, 44744.8, 45820.5, 47971.8", \ + "44924.3, 44924.3, 44924.3, 46000.0, 48151.3", \ + "45289.6, 45289.6, 45289.6, 46365.3, 48516.6", \ + "45987.2, 45987.2, 45987.2, 47062.9, 49214.2"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__18) { + values ("32088.9, 32088.9, 32088.9, 33164.6, 35315.9", \ + "32127.8, 32127.8, 32127.8, 33203.5, 35354.9", \ + "32195.5, 32195.5, 32195.5, 33271.2, 35422.5", \ + "32327.0, 32327.0, 32327.0, 33402.7, 35554.0", \ + "32590.0, 32590.0, 32590.0, 33665.6, 35817.0"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("39824.7, 39824.7, 39824.7, 40900.4, 43051.7", \ + "39901.5, 39901.5, 39901.5, 40977.1, 43128.5", \ + "40037.8, 40037.8, 40037.8, 41113.5, 43264.8", \ + "40316.5, 40316.5, 40316.5, 41392.2, 43543.5", \ + "40841.6, 40841.6, 40841.6, 41917.2, 44068.6"); + } + } + internal_power (energy_pos_q_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__18) { + values ("18955.5, 18955.5, 18955.5, 20031.1, 22182.5", \ + "18984.0, 18984.0, 18984.0, 20059.7, 22211.0", \ + "19034.2, 19034.2, 19034.2, 20109.8, 22261.2", \ + "22354.3, 22354.3, 22354.3, 22354.3, 22354.3", \ + "19321.1, 19321.1, 19321.1, 20396.7, 22548.1"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("21726.4, 21726.4, 21726.4, 22802.0, 24953.4", \ + "21853.6, 21853.6, 21853.6, 22929.2, 25080.6", \ + "22071.8, 22071.8, 22071.8, 23147.5, 25298.8", \ + "22384.7, 22384.7, 22384.7, 23460.4, 25611.7", \ + "23054.8, 23054.8, 23054.8, 24130.5, 26281.8"); + } + } + internal_power (energy_pos_q_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__18) { + values ("26779.0, 26779.0, 26779.0, 27854.7, 30006.0", \ + "30025.8, 30025.8, 30025.8, 30025.8, 30025.8", \ + "30065.3, 30065.3, 30065.3, 30065.3, 30065.3", \ + "30144.3, 30144.3, 30144.3, 30144.3, 30144.3", \ + "27079.1, 27079.1, 27079.1, 28154.8, 30306.1"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("26572.0, 26572.0, 26572.0, 27647.7, 29799.0", \ + "26717.9, 26717.9, 26717.9, 27793.5, 29944.9", \ + "26973.7, 26973.7, 26973.7, 28049.4, 30200.7", \ + "27360.8, 27360.8, 27360.8, 28436.4, 30587.8", \ + "28183.6, 28183.6, 28183.6, 29259.3, 31410.6"); + } + } + } + } + + cell (mx3_x2) { + area : 46.80 ; + cell_leakage_power : 6.7 ; + leakage_power () { + when : "(cmd0 & cmd1 & i0 & i1)" ; + value : 6.3 ; + } + leakage_power () { + when : "(i2 & !(i1) & i0 & cmd1 & cmd0)" ; + value : 7.3 ; + } + leakage_power () { + when : "(cmd0 & cmd1 & !(i0) & i1)" ; + value : 6.2 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & cmd1 & cmd0)" ; + value : 5.9 ; + } + leakage_power () { + when : "(!(i2) & i1 & i0 & !(cmd1) & cmd0)" ; + value : 7.8 ; + } + leakage_power () { + when : "(!(i2) & i1 & !(i0) & !(cmd1) & cmd0)" ; + value : 7.2 ; + } + leakage_power () { + when : "(cmd0 & ((!(cmd1) & !(i0) & i2) | (!(i0) & !(i1) & i2)))" ; + value : 6.7 ; + } + leakage_power () { + when : "((cmd0 & cmd1 & i0 & !(i1) & !(i2)) | (!(cmd0) & cmd1 & i0 & i1 & !(i2)))" ; + value : 6.5 ; + } + leakage_power () { + when : "(!(cmd0) & cmd1 & i0 & i2)" ; + value : 6.6 ; + } + leakage_power () { + when : "(!(i2) & !(i1) & !(i0) & cmd1 & !(cmd0))" ; + value : 5.8 ; + } + leakage_power () { + when : "(!(cmd0) & !(cmd1) & i0 & i1)" ; + value : 7.1 ; + } + leakage_power () { + when : "(i2 & i1 & !(i0) & !(cmd1) & !(cmd0))" ; + value : 7.5 ; + } + leakage_power () { + when : "((cmd0 & !(cmd1) & i0 & i2) | (!(cmd0) & !(cmd1) & !(i0) & i1 & !(i2)))" ; + value : 6.9 ; + } + leakage_power () { + when : "((!(cmd0) & ((cmd1 & !(i0) & i1 & i2) | (!(cmd1) & ((i0 & !(i1)) | (!(i1) & i2))))) | (!(cmd1) & i0 & !(i1) & !(i2)))" ; + value : 7 ; + } + leakage_power () { + when : "((!(cmd0) & ((cmd1 & ((i0 & !(i1) & !(i2)) | (!(i0) & (i1 ^ i2)))) | (!(cmd1) & !(i0) & !(i1) & !(i2)))) | (!(cmd1) & !(i0) & !(i1) & !(i2)))" ; + value : 6.4 ; + } + pin (i2) { + direction : input ; + capacitance : 452.77 ; + } + pin (i1) { + direction : input ; + capacitance : 454.85 ; + } + pin (i0) { + direction : input ; + capacitance : 462.83 ; + } + pin (cmd1) { + direction : input ; + capacitance : 773.76 ; + } + pin (cmd0) { + direction : input ; + capacitance : 744.77 ; + } + pin (q) { + function : "((i2 & ((i0 & (!(cmd0) | i1 | !(cmd1))) | (cmd0 & (i1 | !(cmd1))))) | (i0 & (!(cmd0) | (i1 & cmd1))) | (cmd0 & i1 & cmd1))" ; + direction : output ; + capacitance : 87.03 ; + timing (maxd_q_cmd0_positive_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + sdf_cond : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__35) { + values ("11658.1, 11658.1, 11658.1, 11932.8, 12454.8", \ + "11647.0, 11647.0, 11647.0, 11921.7, 12443.7", \ + "11624.8, 11624.8, 11624.8, 11899.5, 12421.5", \ + "11580.5, 11580.5, 11580.5, 11855.2, 12377.2", \ + "11491.9, 11491.9, 11491.9, 11766.6, 12288.6"); + } + rise_transition (inslew_load_5x5__35) { + values ("6531.2, 6531.2, 6531.2, 6753.8, 7193.4", \ + "6531.2, 6531.2, 6531.2, 6753.8, 7193.4", \ + "6531.2, 6531.2, 6531.2, 6753.8, 7193.4", \ + "6531.2, 6531.2, 6531.2, 6753.8, 7193.4", \ + "6531.2, 6531.2, 6531.2, 6753.8, 7193.4"); + } + cell_fall (inslew_load_5x5__35) { + values ("12408.3, 12408.3, 12408.3, 12853.3, 13352.2", \ + "12403.0, 12403.0, 12403.0, 12848.0, 13346.9", \ + "12392.3, 12392.3, 12392.3, 12837.3, 13336.2", \ + "12370.8, 12370.8, 12370.8, 12815.8, 13314.7", \ + "12327.9, 12327.9, 12327.9, 12772.9, 13271.8"); + } + fall_transition (inslew_load_5x5__35) { + values ("6046.8, 6046.8, 6046.8, 6275.1, 6529.8", \ + "6046.8, 6046.8, 6046.8, 6275.1, 6529.8", \ + "6046.8, 6046.8, 6046.8, 6275.1, 6529.8", \ + "6046.8, 6046.8, 6046.8, 6275.1, 6529.8", \ + "6046.8, 6046.8, 6046.8, 6275.1, 6529.8"); + } + } + timing (maxd_q_cmd1_positive_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + sdf_cond : "(cmd0 & i1 & !(i2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__35) { + values ("7245.5, 7245.5, 7245.5, 7540.1, 8085.9", \ + "7256.1, 7256.1, 7256.1, 7550.6, 8096.4", \ + "7278.7, 7278.7, 7278.7, 7572.9, 8118.7", \ + "7292.9, 7292.9, 7292.9, 7587.1, 8132.8", \ + "7313.6, 7313.6, 7313.6, 7607.7, 8153.5"); + } + rise_transition (inslew_load_5x5__35) { + values ("3521.2, 3521.2, 3521.2, 3762.1, 4226.5", \ + "3532.9, 3532.9, 3532.9, 3773.6, 4237.8", \ + "3553.7, 3553.7, 3553.7, 3794.1, 4257.8", \ + "3564.2, 3564.2, 3564.2, 3804.5, 4267.9", \ + "3566.5, 3566.5, 3566.5, 3806.7, 4270.2"); + } + cell_fall (inslew_load_5x5__35) { + values ("9789.4, 9789.4, 9789.4, 10046.6, 10527.7", \ + "9807.9, 9807.9, 9807.9, 10065.2, 10546.6", \ + "9831.2, 9831.2, 9831.2, 10088.8, 10570.4", \ + "9842.7, 9842.7, 9842.7, 10100.5, 10582.4", \ + "9875.5, 9875.5, 9875.5, 10133.5, 10615.9"); + } + fall_transition (inslew_load_5x5__35) { + values ("4870.2, 4870.2, 4870.2, 4997.4, 5284.9", \ + "4888.2, 4888.2, 4888.2, 5015.2, 5302.0", \ + "4913.4, 4913.4, 4913.4, 5040.2, 5326.2", \ + "4934.8, 4934.8, 4934.8, 5061.2, 5346.5", \ + "4969.6, 4969.6, 4969.6, 5095.6, 5379.8"); + } + } + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__35) { + values ("5019.4, 5019.4, 5019.4, 5345.6, 5936.3", \ + "5024.6, 5024.6, 5024.6, 5350.8, 5941.5", \ + "5032.0, 5032.0, 5032.0, 5358.2, 5948.7", \ + "5048.5, 5048.5, 5048.5, 5374.7, 5965.3", \ + "5082.6, 5082.6, 5082.6, 5408.7, 5999.3"); + } + rise_transition (inslew_load_5x5__35) { + values ("1757.0, 1757.0, 1757.0, 2037.7, 2556.5", \ + "1760.1, 1760.1, 1760.1, 2040.8, 2559.3", \ + "1761.1, 1761.1, 1761.1, 2041.7, 2560.2", \ + "1761.4, 1761.4, 1761.4, 2042.0, 2560.5", \ + "1762.5, 1762.5, 1762.5, 2043.1, 2561.5"); + } + cell_fall (inslew_load_5x5__35) { + values ("7746.0, 7746.0, 7746.0, 7992.1, 8379.6", \ + "7748.8, 7748.8, 7748.8, 7994.9, 8382.5", \ + "7757.6, 7757.6, 7757.6, 8003.7, 8391.6", \ + "7769.5, 7769.5, 7769.5, 8015.6, 8464.7", \ + "7798.2, 7798.2, 7798.2, 8044.4, 8492.7"); + } + fall_transition (inslew_load_5x5__35) { + values ("3311.6, 3311.6, 3311.6, 3474.0, 3756.2", \ + "3314.4, 3314.4, 3314.4, 3476.8, 3758.9", \ + "3320.0, 3320.0, 3320.0, 3482.1, 3764.4", \ + "3323.1, 3323.1, 3323.1, 3485.1, 3811.7", \ + "3323.9, 3323.9, 3323.9, 3485.9, 3809.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__35) { + values ("10047.4, 10047.4, 10047.4, 10320.9, 10850.9", \ + "10043.9, 10043.9, 10043.9, 10317.4, 10847.3", \ + "10037.1, 10037.1, 10037.1, 10310.6, 10840.4", \ + "10019.8, 10019.8, 10019.8, 10293.3, 10823.0", \ + "9987.2, 9987.2, 9987.2, 10260.7, 10790.4"); + } + rise_transition (inslew_load_5x5__35) { + values ("5466.0, 5466.0, 5466.0, 5691.1, 6138.5", \ + "5468.8, 5468.8, 5468.8, 5693.8, 6141.3", \ + "5472.5, 5472.5, 5472.5, 5697.5, 6144.9", \ + "5473.3, 5473.3, 5473.3, 5698.3, 6145.8", \ + "5473.3, 5473.3, 5473.3, 5698.3, 6145.8"); + } + cell_fall (inslew_load_5x5__35) { + values ("13467.3, 13467.3, 13467.3, 13715.8, 14436.7", \ + "13464.2, 13464.2, 13464.2, 13712.7, 14433.6", \ + "13451.8, 13451.8, 13451.8, 13700.3, 14421.1", \ + "13433.3, 13433.3, 13433.3, 13681.9, 14402.4", \ + "13394.1, 13394.1, 13394.1, 13642.7, 14363.1"); + } + fall_transition (inslew_load_5x5__35) { + values ("7232.8, 7232.8, 7232.8, 7422.3, 7799.3", \ + "7236.7, 7236.7, 7236.7, 7426.3, 7803.6", \ + "7239.7, 7239.7, 7239.7, 7429.2, 7806.8", \ + "7246.1, 7246.1, 7246.1, 7435.7, 7813.7", \ + "7249.8, 7249.8, 7249.8, 7439.3, 7817.6"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__35) { + values ("10047.4, 10047.4, 10047.4, 10320.9, 10850.9", \ + "10043.9, 10043.9, 10043.9, 10317.4, 10847.3", \ + "10037.1, 10037.1, 10037.1, 10310.6, 10840.4", \ + "10019.8, 10019.8, 10019.8, 10293.3, 10823.0", \ + "9987.2, 9987.2, 9987.2, 10260.7, 10790.4"); + } + rise_transition (inslew_load_5x5__35) { + values ("5466.0, 5466.0, 5466.0, 5691.1, 6138.5", \ + "5468.8, 5468.8, 5468.8, 5693.8, 6141.3", \ + "5472.5, 5472.5, 5472.5, 5697.5, 6144.9", \ + "5473.3, 5473.3, 5473.3, 5698.3, 6145.8", \ + "5473.3, 5473.3, 5473.3, 5698.3, 6145.8"); + } + cell_fall (inslew_load_5x5__35) { + values ("13467.3, 13467.3, 13467.3, 13715.8, 14436.7", \ + "13464.2, 13464.2, 13464.2, 13712.7, 14433.6", \ + "13451.8, 13451.8, 13451.8, 13700.3, 14421.1", \ + "13433.3, 13433.3, 13433.3, 13681.9, 14402.4", \ + "13394.1, 13394.1, 13394.1, 13642.7, 14363.1"); + } + fall_transition (inslew_load_5x5__35) { + values ("7232.8, 7232.8, 7232.8, 7422.3, 7799.3", \ + "7236.7, 7236.7, 7236.7, 7426.3, 7803.6", \ + "7239.7, 7239.7, 7239.7, 7429.2, 7806.8", \ + "7246.1, 7246.1, 7246.1, 7435.7, 7813.7", \ + "7249.8, 7249.8, 7249.8, 7439.3, 7817.6"); + } + } + timing (maxd_q_cmd0_negative_unate) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + sdf_cond : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("12810.3, 12810.3, 12810.3, 13091.5, 13635.7", \ + "12819.1, 12819.1, 12819.1, 13100.3, 13644.5", \ + "12836.6, 12836.6, 12836.6, 13117.8, 13662.0", \ + "12871.8, 12871.8, 12871.8, 13153.0, 13697.2", \ + "12942.4, 12942.4, 12942.4, 13223.5, 13767.7"); + } + rise_transition (inslew_load_5x5__35) { + values ("4819.3, 4819.3, 4819.3, 5047.7, 5495.1", \ + "4819.3, 4819.3, 4819.3, 5047.7, 5495.1", \ + "4819.3, 4819.3, 4819.3, 5047.7, 5495.1", \ + "4819.3, 4819.3, 4819.3, 5047.7, 5495.1", \ + "4819.8, 4819.8, 4819.8, 5048.1, 5495.5"); + } + cell_fall (inslew_load_5x5__35) { + values ("19015.7, 19015.7, 19015.7, 19244.1, 19692.1", \ + "19024.5, 19024.5, 19024.5, 19252.9, 19700.9", \ + "19042.1, 19042.1, 19042.1, 19270.5, 19718.5", \ + "19077.2, 19077.2, 19077.2, 19305.6, 19753.6", \ + "19144.1, 19144.1, 19144.1, 19372.5, 19820.5"); + } + fall_transition (inslew_load_5x5__35) { + values ("9227.3, 9227.3, 9227.3, 9395.5, 9713.7", \ + "9227.3, 9227.3, 9227.3, 9395.5, 9713.7", \ + "9227.3, 9227.3, 9227.3, 9395.5, 9713.7", \ + "9227.3, 9227.3, 9227.3, 9395.5, 9713.7", \ + "9227.3, 9227.3, 9227.3, 9395.5, 9713.7"); + } + } + timing (maxd_q_cmd1_negative_unate) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + sdf_cond : "(cmd0 & !(i1) & i2)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__35) { + values ("11552.8, 11552.8, 11552.8, 11845.1, 12390.2", \ + "11561.6, 11561.6, 11561.6, 11853.9, 12399.0", \ + "11579.2, 11579.2, 11579.2, 11871.5, 12416.6", \ + "11614.3, 11614.3, 11614.3, 11906.6, 12451.7", \ + "11684.6, 11684.6, 11684.6, 11976.8, 12521.9"); + } + rise_transition (inslew_load_5x5__35) { + values ("3820.8, 3820.8, 3820.8, 4058.5, 4516.5", \ + "3820.8, 3820.8, 3820.8, 4058.5, 4516.5", \ + "3820.8, 3820.8, 3820.8, 4058.5, 4516.5", \ + "3820.8, 3820.8, 3820.8, 4058.5, 4516.5", \ + "3820.9, 3820.9, 3820.9, 4058.6, 4516.6"); + } + cell_fall (inslew_load_5x5__35) { + values ("12064.4, 12064.4, 12064.4, 12322.6, 12805.3", \ + "12073.2, 12073.2, 12073.2, 12331.4, 12814.1", \ + "12090.8, 12090.8, 12090.8, 12349.0, 12831.7", \ + "12125.9, 12125.9, 12125.9, 12384.1, 12866.8", \ + "12192.7, 12192.7, 12192.7, 12450.9, 12933.6"); + } + fall_transition (inslew_load_5x5__35) { + values ("4989.6, 4989.6, 4989.6, 5116.1, 5398.8", \ + "4989.6, 4989.6, 4989.6, 5116.1, 5398.8", \ + "4989.6, 4989.6, 4989.6, 5116.1, 5398.8", \ + "4989.6, 4989.6, 4989.6, 5116.1, 5398.8", \ + "4989.9, 4989.9, 4989.9, 5116.4, 5399.1"); + } + } + internal_power (energy_pos_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & !(i0) & i1) | (!(cmd1) & !(i0) & i2))" ; + rise_power (energy_inslew_load_5x5__35) { + values ("43141.0, 43141.0, 43141.0, 44229.0, 46404.8", \ + "46426.1, 46426.1, 46426.1, 46426.1, 46426.1", \ + "46468.7, 46468.7, 46468.7, 46468.7, 46468.7", \ + "46554.0, 46554.0, 46554.0, 46554.0, 46554.0", \ + "46724.5, 46724.5, 46724.5, 46724.5, 46724.5"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("43722.2, 43722.2, 43722.2, 44810.1, 46985.9", \ + "47038.2, 47038.2, 47038.2, 47038.2, 47038.2", \ + "47142.9, 47142.9, 47142.9, 47142.9, 47142.9", \ + "47352.1, 47352.1, 47352.1, 47352.1, 47352.1", \ + "47770.5, 47770.5, 47770.5, 47770.5, 47770.5"); + } + } + internal_power (energy_pos_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & i1 & !(i2))" ; + rise_power (energy_inslew_load_5x5__35) { + values ("25463.6, 25463.6, 25463.6, 26551.5, 28727.3", \ + "25506.0, 25506.0, 25506.0, 26593.9, 28769.8", \ + "25584.1, 25584.1, 25584.1, 26672.1, 28847.9", \ + "25659.6, 25659.6, 25659.6, 26747.6, 28923.4", \ + "25761.8, 25761.8, 25761.8, 26849.7, 29025.6"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("27969.5, 27969.5, 27969.5, 29057.5, 31233.3", \ + "28051.0, 28051.0, 28051.0, 29138.9, 31314.7", \ + "28182.7, 28182.7, 28182.7, 29270.6, 31446.5", \ + "28361.5, 28361.5, 28361.5, 29449.5, 31625.3", \ + "28696.6, 28696.6, 28696.6, 29784.5, 31960.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__35) { + values ("21317.9, 21317.9, 21317.9, 22405.8, 24581.6", \ + "21339.7, 21339.7, 21339.7, 22427.7, 24603.5", \ + "21372.3, 21372.3, 21372.3, 22460.2, 24636.1", \ + "21434.2, 21434.2, 21434.2, 22522.2, 24698.0", \ + "21559.0, 21559.0, 21559.0, 22646.9, 24822.7"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("23468.2, 23468.2, 23468.2, 24556.1, 26732.0", \ + "23514.1, 23514.1, 23514.1, 24602.0, 26777.9", \ + "23605.8, 23605.8, 23605.8, 24693.7, 26869.5", \ + "23765.4, 23765.4, 23765.4, 24853.3, 27029.1", \ + "24069.1, 24069.1, 24069.1, 25157.0, 27332.8"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__35) { + values ("36495.6, 36495.6, 36495.6, 37583.5, 39759.3", \ + "36519.0, 36519.0, 36519.0, 37607.0, 39782.8", \ + "36560.3, 36560.3, 36560.3, 37648.2, 39824.0", \ + "36624.0, 36624.0, 36624.0, 37711.9, 39887.7", \ + "40010.2, 40010.2, 40010.2, 40010.2, 40010.2"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("42694.7, 42694.7, 42694.7, 43782.6, 45958.4", \ + "42744.9, 42744.9, 42744.9, 43832.8, 46008.6", \ + "42829.6, 42829.6, 42829.6, 43917.5, 46093.4", \ + "43000.6, 43000.6, 43000.6, 44088.6, 46264.4", \ + "43313.4, 43313.4, 43313.4, 44401.3, 46577.1"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__35) { + values ("36495.6, 36495.6, 36495.6, 37583.5, 39759.3", \ + "36519.0, 36519.0, 36519.0, 37607.0, 39782.8", \ + "36560.3, 36560.3, 36560.3, 37648.2, 39824.0", \ + "36624.0, 36624.0, 36624.0, 37711.9, 39887.7", \ + "40010.2, 40010.2, 40010.2, 40010.2, 40010.2"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("42694.7, 42694.7, 42694.7, 43782.6, 45958.4", \ + "42744.9, 42744.9, 42744.9, 43832.8, 46008.6", \ + "42829.6, 42829.6, 42829.6, 43917.5, 46093.4", \ + "43000.6, 43000.6, 43000.6, 44088.6, 46264.4", \ + "43313.4, 43313.4, 43313.4, 44401.3, 46577.1"); + } + } + internal_power (energy_neg_q_cmd0) { + related_pin : "cmd0" ; + when : "((cmd1 & i0 & !(i1)) | (!(cmd1) & i0 & !(i2)))" ; + rise_power (energy_inslew_load_5x5__35) { + values ("47244.9, 47244.9, 47244.9, 48332.8, 50508.6", \ + "50535.1, 50535.1, 50535.1, 50535.1, 50535.1", \ + "50588.1, 50588.1, 50588.1, 50588.1, 50588.1", \ + "50694.2, 50694.2, 50694.2, 50694.2, 50694.2", \ + "47644.6, 47644.6, 47644.6, 48732.5, 50908.4"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("62974.0, 62974.0, 62974.0, 64062.0, 66237.8", \ + "66254.6, 66254.6, 66254.6, 66254.6, 66254.6", \ + "66288.1, 66288.1, 66288.1, 66288.1, 66288.1", \ + "66355.4, 66355.4, 66355.4, 66355.4, 66355.4", \ + "66498.7, 66498.7, 66498.7, 66498.7, 66498.7"); + } + } + internal_power (energy_neg_q_cmd1) { + related_pin : "cmd1" ; + when : "(cmd0 & !(i1) & i2)" ; + rise_power (energy_inslew_load_5x5__35) { + values ("33524.2, 33524.2, 33524.2, 34612.1, 36787.9", \ + "36822.8, 36822.8, 36822.8, 36822.8, 36822.8", \ + "36892.5, 36892.5, 36892.5, 36892.5, 36892.5", \ + "37031.9, 37031.9, 37031.9, 37031.9, 37031.9", \ + "34047.6, 34047.6, 34047.6, 35135.5, 37311.4"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("35322.8, 35322.8, 35322.8, 36410.8, 38586.6", \ + "38601.9, 38601.9, 38601.9, 38601.9, 38601.9", \ + "38632.6, 38632.6, 38632.6, 38632.6, 38632.6", \ + "38694.1, 38694.1, 38694.1, 38694.1, 38694.1", \ + "35565.7, 35565.7, 35565.7, 36653.6, 38829.4"); + } + } + } + } + + cell (o2_x2) { + area : 18.00 ; + cell_leakage_power : 4.1 ; + leakage_power () { + when : "(!(i1) & i0)" ; + value : 3.8 ; + } + leakage_power () { + when : "i1" ; + value : 4 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 4.4 ; + } + pin (i1) { + direction : input ; + capacitance : 572.31 ; + } + pin (i0) { + direction : input ; + capacitance : 578.67 ; + } + pin (q) { + function : "(i0 | i1)" ; + direction : output ; + capacitance : 86.05 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("4443.1, 4443.1, 4443.1, 4810.8, 5430.6", \ + "4451.9, 4451.9, 4451.9, 4819.6, 5439.4", \ + "4469.5, 4469.5, 4469.5, 4837.2, 5457.0", \ + "4504.8, 4504.8, 4504.8, 4872.4, 5492.3", \ + "4576.2, 4576.2, 4576.2, 4943.7, 5563.5"); + } + rise_transition (inslew_load_5x5__18) { + values ("912.1, 912.1, 912.1, 1216.6, 1769.6", \ + "912.1, 912.1, 912.1, 1216.6, 1769.6", \ + "912.1, 912.1, 912.1, 1216.6, 1769.6", \ + "912.2, 912.2, 912.2, 1216.6, 1769.6", \ + "913.9, 913.9, 913.9, 1218.2, 1771.2"); + } + cell_fall (inslew_load_5x5__18) { + values ("7812.7, 7812.7, 7812.7, 7962.5, 8427.6", \ + "7807.4, 7807.4, 7807.4, 7957.2, 8422.3", \ + "7796.6, 7796.6, 7796.6, 7946.4, 8411.5", \ + "7775.2, 7775.2, 7775.2, 7925.0, 8390.1", \ + "7732.2, 7732.2, 7732.2, 7882.0, 8347.1"); + } + fall_transition (inslew_load_5x5__18) { + values ("3521.8, 3521.8, 3521.8, 3587.2, 3941.1", \ + "3521.8, 3521.8, 3521.8, 3587.2, 3941.1", \ + "3521.8, 3521.8, 3521.8, 3587.2, 3941.1", \ + "3521.8, 3521.8, 3521.8, 3587.2, 3941.1", \ + "3521.8, 3521.8, 3521.8, 3587.2, 3941.1"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__18) { + values ("3885.1, 3885.1, 3885.1, 4215.7, 4772.4", \ + "3893.9, 3893.9, 3893.9, 4224.5, 4781.2", \ + "3911.5, 3911.5, 3911.5, 4242.1, 4798.8", \ + "3946.7, 3946.7, 3946.7, 4277.3, 4833.9", \ + "4014.4, 4014.4, 4014.4, 4345.4, 4902.4"); + } + rise_transition (inslew_load_5x5__18) { + values ("657.8, 657.8, 657.8, 955.8, 1493.7", \ + "657.8, 657.8, 657.8, 955.8, 1493.7", \ + "657.8, 657.8, 657.8, 955.8, 1493.7", \ + "657.8, 657.8, 657.8, 955.7, 1493.7", \ + "658.2, 658.2, 658.2, 955.2, 1494.3"); + } + cell_fall (inslew_load_5x5__18) { + values ("5332.6, 5332.6, 5332.6, 5597.4, 6015.7", \ + "5335.5, 5335.5, 5335.5, 5600.5, 6018.8", \ + "5333.1, 5333.1, 5333.1, 5609.3, 6027.9", \ + "5344.6, 5344.6, 5344.6, 5621.4, 6040.0", \ + "5373.4, 5373.4, 5373.4, 5650.3, 6069.0"); + } + fall_transition (inslew_load_5x5__18) { + values ("2084.4, 2084.4, 2084.4, 2238.9, 2529.4", \ + "2087.9, 2087.9, 2087.9, 2242.2, 2532.3", \ + "2085.6, 2085.6, 2085.6, 2248.4, 2537.7", \ + "2088.6, 2088.6, 2088.6, 2251.6, 2540.5", \ + "2089.5, 2089.5, 2089.5, 2252.7, 2541.4"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__18) { + values ("23135.9, 23135.9, 23135.9, 24211.6, 26362.9", \ + "26401.2, 26401.2, 26401.2, 26401.2, 26401.2", \ + "26477.7, 26477.7, 26477.7, 26477.7, 26477.7", \ + "23403.9, 23403.9, 23403.9, 24479.6, 26630.9", \ + "23712.9, 23712.9, 23712.9, 24788.6, 26939.9"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("31789.3, 31789.3, 31789.3, 32865.0, 35016.3", \ + "35059.8, 35059.8, 35059.8, 35059.8, 35059.8", \ + "35146.8, 35146.8, 35146.8, 35146.8, 35146.8", \ + "35320.8, 35320.8, 35320.8, 35320.8, 35320.8", \ + "35668.7, 35668.7, 35668.7, 35668.7, 35668.7"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__18) { + values ("16912.9, 16912.9, 16912.9, 17988.5, 20139.9", \ + "20165.1, 20165.1, 20165.1, 20165.1, 20165.1", \ + "20215.5, 20215.5, 20215.5, 20215.5, 20215.5", \ + "17089.5, 17089.5, 17089.5, 18165.2, 20316.5", \ + "17299.8, 17299.8, 17299.8, 18375.5, 20526.8"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("19045.3, 19045.3, 19045.3, 20120.9, 22272.3", \ + "19098.0, 19098.0, 19098.0, 20173.7, 22325.0", \ + "19202.5, 19202.5, 19202.5, 20278.1, 22429.5", \ + "19387.8, 19387.8, 19387.8, 20463.5, 22614.8", \ + "19744.3, 19744.3, 19744.3, 20819.9, 22971.3"); + } + } + } + } + + cell (nmx2_x1) { + area : 25.20 ; + cell_leakage_power : 5.1 ; + leakage_power () { + when : "(!(i1) & i0 & cmd)" ; + value : 6 ; + } + leakage_power () { + when : "(cmd & i1)" ; + value : 3.9 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & cmd)" ; + value : 4.6 ; + } + leakage_power () { + when : "(!(cmd) & i0)" ; + value : 4.5 ; + } + leakage_power () { + when : "(i1 & !(i0) & !(cmd))" ; + value : 6.5 ; + } + leakage_power () { + when : "(!(i1) & !(i0) & !(cmd))" ; + value : 5.2 ; + } + pin (i1) { + direction : input ; + capacitance : 849.78 ; + } + pin (i0) { + direction : input ; + capacitance : 846.78 ; + } + pin (cmd) { + direction : input ; + capacitance : 1269.59 ; + } + pin (nq) { + function : "((!(i0) & (!(i1) | !(cmd))) | (!(i1) & cmd))" ; + direction : output ; + capacitance : 148.87 ; + timing (maxd_nq_cmd_positive_unate) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + sdf_cond : "(i0 & !(i1))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__7) { + values ("4682.6, 4682.6, 4682.6, 5338.6, 6434.5", \ + "4691.4, 4691.4, 4691.4, 5347.4, 6443.3", \ + "4709.0, 4709.0, 4709.0, 5365.0, 6460.9", \ + "4744.1, 4744.1, 4744.1, 5400.2, 6496.1", \ + "4810.5, 4810.5, 4810.5, 5467.5, 6564.6"); + } + rise_transition (inslew_load_5x5__7) { + values ("1609.5, 1609.5, 1609.5, 2408.5, 3858.4", \ + "1609.5, 1609.5, 1609.5, 2408.5, 3858.4", \ + "1609.5, 1609.5, 1609.5, 2408.5, 3858.4", \ + "1609.5, 1609.5, 1609.5, 2408.5, 3858.4", \ + "1610.0, 1610.0, 1610.0, 2409.6, 3859.8"); + } + cell_fall (inslew_load_5x5__7) { + values ("5286.8, 5286.8, 5286.8, 5910.8, 6833.9", \ + "5295.6, 5295.6, 5295.6, 5919.6, 6842.7", \ + "5313.2, 5313.2, 5313.2, 5937.2, 6860.3", \ + "5348.4, 5348.4, 5348.4, 5972.4, 6895.5", \ + "5418.6, 5418.6, 5418.6, 6042.7, 6965.8"); + } + fall_transition (inslew_load_5x5__7) { + values ("1802.9, 1802.9, 1802.9, 2361.9, 3261.9", \ + "1802.9, 1802.9, 1802.9, 2361.9, 3261.9", \ + "1802.9, 1802.9, 1802.9, 2361.9, 3261.9", \ + "1802.9, 1802.9, 1802.9, 2361.9, 3261.9", \ + "1803.2, 1803.2, 1803.2, 2362.1, 3262.1"); + } + } + timing (maxd_nq_cmd_negative_unate) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + sdf_cond : "(!(i0) & i1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__7) { + values ("2193.9, 2193.9, 2193.9, 2651.4, 3559.1", \ + "2198.7, 2198.7, 2198.7, 2656.0, 3563.3", \ + "2206.9, 2206.9, 2206.9, 2664.4, 3572.5", \ + "2217.6, 2217.6, 2217.6, 2675.3, 3584.2", \ + "2245.8, 2245.8, 2245.8, 2706.9, 3615.7"); + } + rise_transition (inslew_load_5x5__7) { + values ("1400.6, 1400.6, 1400.6, 2121.9, 3563.0", \ + "1411.6, 1411.6, 1411.6, 2132.5, 3573.0", \ + "1425.8, 1425.8, 1425.8, 2147.1, 3588.8", \ + "1431.6, 1431.6, 1431.6, 2153.2, 3596.2", \ + "1452.2, 1452.2, 1452.2, 2169.5, 3604.8"); + } + cell_fall (inslew_load_5x5__7) { + values ("1555.9, 1555.9, 1555.9, 1829.8, 2373.2", \ + "1558.4, 1558.4, 1558.4, 1832.3, 2376.1", \ + "1567.3, 1567.3, 1567.3, 1841.1, 2384.2", \ + "1582.6, 1582.6, 1582.6, 1856.8, 2400.2", \ + "1588.8, 1588.8, 1588.8, 1875.6, 2429.2"); + } + fall_transition (inslew_load_5x5__7) { + values ("943.0, 943.0, 943.0, 1367.5, 2215.9", \ + "944.9, 944.9, 944.9, 1369.5, 2218.4", \ + "949.0, 949.0, 949.0, 1373.3, 2221.2", \ + "949.4, 949.4, 949.4, 1373.4, 2221.1", \ + "963.0, 963.0, 963.0, 1388.1, 2230.6"); + } + } + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__7) { + values ("5881.4, 5881.4, 5881.4, 6312.5, 7192.5", \ + "5876.0, 5876.0, 5876.0, 6307.1, 7187.1", \ + "5865.1, 5865.1, 5865.1, 6296.3, 7176.3", \ + "5843.3, 5843.3, 5843.3, 6274.6, 7154.8", \ + "5799.8, 5799.8, 5799.8, 6231.4, 7111.7"); + } + rise_transition (inslew_load_5x5__7) { + values ("7064.6, 7064.6, 7064.6, 7774.2, 9193.3", \ + "7064.6, 7064.6, 7064.6, 7774.2, 9193.3", \ + "7064.6, 7064.6, 7064.6, 7774.2, 9193.3", \ + "7064.6, 7064.6, 7064.6, 7774.2, 9193.3", \ + "7064.7, 7064.7, 7064.7, 7774.2, 9193.4"); + } + cell_fall (inslew_load_5x5__7) { + values ("3179.4, 3179.4, 3179.4, 3441.7, 3971.5", \ + "3174.2, 3174.2, 3174.2, 3436.5, 3966.4", \ + "3163.8, 3163.8, 3163.8, 3426.2, 3956.0", \ + "3143.1, 3143.1, 3143.1, 3405.5, 3935.4", \ + "3100.9, 3100.9, 3100.9, 3363.7, 3894.0"); + } + fall_transition (inslew_load_5x5__7) { + values ("3400.0, 3400.0, 3400.0, 3817.4, 4652.3", \ + "3400.0, 3400.0, 3400.0, 3817.4, 4652.3", \ + "3400.0, 3400.0, 3400.0, 3817.4, 4652.3", \ + "3400.0, 3400.0, 3400.0, 3817.4, 4652.3", \ + "3404.8, 3404.8, 3404.8, 3820.9, 4654.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__7) { + values ("5881.4, 5881.4, 5881.4, 6312.5, 7192.5", \ + "5876.0, 5876.0, 5876.0, 6307.1, 7187.1", \ + "5865.1, 5865.1, 5865.1, 6296.3, 7176.3", \ + "5843.3, 5843.3, 5843.3, 6274.6, 7154.8", \ + "5799.8, 5799.8, 5799.8, 6231.4, 7111.7"); + } + rise_transition (inslew_load_5x5__7) { + values ("7064.6, 7064.6, 7064.6, 7774.2, 9193.3", \ + "7064.6, 7064.6, 7064.6, 7774.2, 9193.3", \ + "7064.6, 7064.6, 7064.6, 7774.2, 9193.3", \ + "7064.6, 7064.6, 7064.6, 7774.2, 9193.3", \ + "7064.7, 7064.7, 7064.7, 7774.2, 9193.4"); + } + cell_fall (inslew_load_5x5__7) { + values ("3179.4, 3179.4, 3179.4, 3441.7, 3971.5", \ + "3174.2, 3174.2, 3174.2, 3436.5, 3966.4", \ + "3163.8, 3163.8, 3163.8, 3426.2, 3956.0", \ + "3143.1, 3143.1, 3143.1, 3405.5, 3935.4", \ + "3100.9, 3100.9, 3100.9, 3363.7, 3894.0"); + } + fall_transition (inslew_load_5x5__7) { + values ("3400.0, 3400.0, 3400.0, 3817.4, 4652.3", \ + "3400.0, 3400.0, 3400.0, 3817.4, 4652.3", \ + "3400.0, 3400.0, 3400.0, 3817.4, 4652.3", \ + "3400.0, 3400.0, 3400.0, 3817.4, 4652.3", \ + "3404.8, 3404.8, 3404.8, 3820.9, 4654.1"); + } + } + internal_power (energy_pos_nq_cmd) { + related_pin : "cmd" ; + when : "(i0 & !(i1))" ; + rise_power (energy_inslew_load_5x5__7) { + values ("15933.1, 15933.1, 15933.1, 17793.9, 21515.6", \ + "21538.5, 21538.5, 21538.5, 21538.5, 21538.5", \ + "21584.3, 21584.3, 21584.3, 21584.3, 21584.3", \ + "16093.5, 16093.5, 16093.5, 17954.3, 21676.0", \ + "16287.5, 16287.5, 16287.5, 18148.4, 21870.0"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("16853.8, 16853.8, 16853.8, 18714.7, 22436.3", \ + "22480.4, 22480.4, 22480.4, 22480.4, 22480.4", \ + "22568.6, 22568.6, 22568.6, 22568.6, 22568.6", \ + "22745.0, 22745.0, 22745.0, 22745.0, 22745.0", \ + "17515.5, 17515.5, 17515.5, 19376.4, 23098.1"); + } + } + internal_power (energy_neg_nq_cmd) { + related_pin : "cmd" ; + when : "(!(i0) & i1)" ; + rise_power (energy_inslew_load_5x5__7) { + values ("1874.5, 1874.5, 1874.5, 3735.3, 7457.0", \ + "1938.2, 1938.2, 1938.2, 3799.1, 7520.8", \ + "2065.8, 2065.8, 2065.8, 3926.6, 7648.3", \ + "2320.9, 2320.9, 2320.9, 4181.8, 7903.4", \ + "2831.2, 2831.2, 2831.2, 4692.0, 8413.7"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("1943.7, 1943.7, 1943.7, 3804.6, 7526.2", \ + "1976.5, 1976.5, 1976.5, 3837.3, 7559.0", \ + "2042.0, 2042.0, 2042.0, 3902.8, 7624.5", \ + "2173.0, 2173.0, 2173.0, 4033.9, 7755.5", \ + "2435.1, 2435.1, 2435.1, 4295.9, 8017.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__7) { + values ("16723.0, 16723.0, 16723.0, 18583.8, 22305.5", \ + "16811.4, 16811.4, 16811.4, 18672.2, 22393.9", \ + "16988.2, 16988.2, 16988.2, 18849.0, 22570.7", \ + "17341.7, 17341.7, 17341.7, 19202.6, 22924.3", \ + "18048.9, 18048.9, 18048.9, 19909.8, 23631.4"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("12941.2, 12941.2, 12941.2, 14802.0, 18523.7", \ + "12986.9, 12986.9, 12986.9, 14847.7, 18569.4", \ + "13078.3, 13078.3, 13078.3, 14939.1, 18660.8", \ + "13261.1, 13261.1, 13261.1, 15122.0, 18843.7", \ + "13626.8, 13626.8, 13626.8, 15487.7, 19209.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__7) { + values ("16723.0, 16723.0, 16723.0, 18583.8, 22305.5", \ + "16811.4, 16811.4, 16811.4, 18672.2, 22393.9", \ + "16988.2, 16988.2, 16988.2, 18849.0, 22570.7", \ + "17341.7, 17341.7, 17341.7, 19202.6, 22924.3", \ + "18048.9, 18048.9, 18048.9, 19909.8, 23631.4"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("12941.2, 12941.2, 12941.2, 14802.0, 18523.7", \ + "12986.9, 12986.9, 12986.9, 14847.7, 18569.4", \ + "13078.3, 13078.3, 13078.3, 14939.1, 18660.8", \ + "13261.1, 13261.1, 13261.1, 15122.0, 18843.7", \ + "13626.8, 13626.8, 13626.8, 15487.7, 19209.3"); + } + } + } + } + + cell (xr2_x1) { + area : 32.40 ; + cell_leakage_power : 7.9 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 7.3 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 7.7 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 7 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 9.5 ; + } + pin (i1) { + direction : input ; + capacitance : 1275.13 ; + } + pin (i0) { + direction : input ; + capacitance : 1270.29 ; + } + pin (q) { + function : "(i0 ^ i1)" ; + direction : output ; + capacitance : 153.07 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + when : "!(i1)" ; + sdf_cond : "!(i1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__36) { + values ("4648.7, 4648.7, 4648.7, 5319.8, 6441.2", \ + "4657.5, 4657.5, 4657.5, 5328.6, 6450.0", \ + "4675.1, 4675.1, 4675.1, 5346.2, 6467.6", \ + "4710.2, 4710.2, 4710.2, 5381.4, 6502.8", \ + "4776.4, 4776.4, 4776.4, 5448.5, 6571.1"); + } + rise_transition (inslew_load_5x5__36) { + values ("1622.8, 1622.8, 1622.8, 2439.4, 3935.0", \ + "1622.8, 1622.8, 1622.8, 2439.4, 3935.0", \ + "1622.8, 1622.8, 1622.8, 2439.4, 3935.0", \ + "1622.8, 1622.8, 1622.8, 2439.4, 3935.1", \ + "1623.3, 1623.3, 1623.3, 2440.5, 3936.5"); + } + cell_fall (inslew_load_5x5__36) { + values ("5289.3, 5289.3, 5289.3, 5920.7, 6860.9", \ + "5298.1, 5298.1, 5298.1, 5929.5, 6869.7", \ + "5315.7, 5315.7, 5315.7, 5947.1, 6887.3", \ + "5350.9, 5350.9, 5350.9, 5982.3, 6922.5", \ + "5421.1, 5421.1, 5421.1, 6052.6, 6992.8"); + } + fall_transition (inslew_load_5x5__36) { + values ("1811.2, 1811.2, 1811.2, 2379.6, 3300.2", \ + "1811.2, 1811.2, 1811.2, 2379.6, 3300.2", \ + "1811.2, 1811.2, 1811.2, 2379.6, 3300.2", \ + "1811.2, 1811.2, 1811.2, 2379.6, 3300.2", \ + "1811.5, 1811.5, 1811.5, 2379.9, 3300.5"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + when : "!(i0)" ; + sdf_cond : "!(i0)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__36) { + values ("5717.9, 5717.9, 5717.9, 6269.8, 7296.6", \ + "5726.7, 5726.7, 5726.7, 6278.6, 7305.4", \ + "5744.3, 5744.3, 5744.3, 6296.2, 7323.0", \ + "5779.5, 5779.5, 5779.5, 6331.4, 7358.2", \ + "5847.2, 5847.2, 5847.2, 6399.6, 7427.2"); + } + rise_transition (inslew_load_5x5__36) { + values ("2932.9, 2932.9, 2932.9, 3674.4, 5130.8", \ + "2932.9, 2932.9, 2932.9, 3674.4, 5130.8", \ + "2932.9, 2932.9, 2932.9, 3674.4, 5130.8", \ + "2932.9, 2932.9, 2932.9, 3674.4, 5130.8", \ + "2934.0, 2934.0, 2934.0, 3675.7, 5132.2"); + } + cell_fall (inslew_load_5x5__36) { + values ("6336.6, 6336.6, 6336.6, 6697.5, 7377.0", \ + "6345.3, 6345.3, 6345.3, 6706.2, 7385.7", \ + "6362.9, 6362.9, 6362.9, 6723.8, 7403.3", \ + "6398.1, 6398.1, 6398.1, 6759.0, 7438.5", \ + "6468.3, 6468.3, 6468.3, 6829.2, 7508.7"); + } + fall_transition (inslew_load_5x5__36) { + values ("3150.0, 3150.0, 3150.0, 3584.0, 4434.5", \ + "3150.0, 3150.0, 3150.0, 3584.0, 4434.5", \ + "3150.0, 3150.0, 3150.0, 3584.0, 4434.5", \ + "3150.0, 3150.0, 3150.0, 3584.0, 4434.5", \ + "3150.2, 3150.2, 3150.2, 3584.2, 4434.7"); + } + } + timing (maxd_q_i0_negative_unate) { + related_pin : "i0" ; + when : "i1" ; + sdf_cond : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("6175.4, 6175.4, 6175.4, 6617.2, 7520.7", \ + "6170.0, 6170.0, 6170.0, 6611.8, 7515.3", \ + "6159.1, 6159.1, 6159.1, 6601.0, 7504.6", \ + "6137.3, 6137.3, 6137.3, 6579.3, 7483.0", \ + "6093.7, 6093.7, 6093.7, 6536.0, 7440.0"); + } + rise_transition (inslew_load_5x5__36) { + values ("7518.2, 7518.2, 7518.2, 8247.8, 9707.0", \ + "7518.2, 7518.2, 7518.2, 8247.8, 9707.0", \ + "7518.2, 7518.2, 7518.2, 8247.8, 9707.0", \ + "7518.2, 7518.2, 7518.2, 8247.8, 9707.0", \ + "7518.3, 7518.3, 7518.3, 8247.9, 9707.1"); + } + cell_fall (inslew_load_5x5__36) { + values ("3785.3, 3785.3, 3785.3, 4051.3, 4592.3", \ + "3780.1, 3780.1, 3780.1, 4046.2, 4587.2", \ + "3769.7, 3769.7, 3769.7, 4035.8, 4576.8", \ + "3749.0, 3749.0, 3749.0, 4015.1, 4556.2", \ + "3707.3, 3707.3, 3707.3, 3973.7, 4514.8"); + } + fall_transition (inslew_load_5x5__36) { + values ("4317.7, 4317.7, 4317.7, 4747.0, 5605.4", \ + "4317.7, 4317.7, 4317.7, 4747.0, 5605.4", \ + "4317.7, 4317.7, 4317.7, 4747.0, 5605.4", \ + "4317.7, 4317.7, 4317.7, 4747.0, 5605.4", \ + "4319.9, 4319.9, 4319.9, 4748.5, 5606.2"); + } + } + timing (maxd_q_i1_negative_unate) { + related_pin : "i1" ; + when : "i0" ; + sdf_cond : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__36) { + values ("5389.5, 5389.5, 5389.5, 5836.5, 6745.3", \ + "5384.0, 5384.0, 5384.0, 5831.1, 6739.9", \ + "5373.2, 5373.2, 5373.2, 5820.3, 6729.1", \ + "5351.5, 5351.5, 5351.5, 5798.7, 6707.6", \ + "5308.0, 5308.0, 5308.0, 5755.5, 6664.6"); + } + rise_transition (inslew_load_5x5__36) { + values ("6309.7, 6309.7, 6309.7, 7039.3, 8498.5", \ + "6309.7, 6309.7, 6309.7, 7039.3, 8498.5", \ + "6309.7, 6309.7, 6309.7, 7039.3, 8498.5", \ + "6309.7, 6309.7, 6309.7, 7039.3, 8498.5", \ + "6310.0, 6310.0, 6310.0, 7039.5, 8498.6"); + } + cell_fall (inslew_load_5x5__36) { + values ("2958.1, 2958.1, 2958.1, 3231.0, 3780.8", \ + "2961.3, 2961.3, 2961.3, 3234.2, 3784.2", \ + "2968.8, 2968.8, 2968.8, 3241.7, 3791.4", \ + "2985.0, 2985.0, 2985.0, 3257.9, 3807.7", \ + "3017.0, 3017.0, 3017.0, 3290.5, 3840.9"); + } + fall_transition (inslew_load_5x5__36) { + values ("3089.7, 3089.7, 3089.7, 3526.2, 4399.3", \ + "3092.7, 3092.7, 3092.7, 3529.3, 4402.6", \ + "3094.7, 3094.7, 3094.7, 3531.1, 4404.1", \ + "3094.7, 3094.7, 3094.7, 3531.2, 4404.3", \ + "3099.3, 3099.3, 3099.3, 3534.3, 4405.7"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + when : "!(i1)" ; + rise_power (energy_inslew_load_5x5__36) { + values ("15892.5, 15892.5, 15892.5, 17805.8, 21632.5", \ + "21655.4, 21655.4, 21655.4, 21655.4, 21655.4", \ + "21701.2, 21701.2, 21701.2, 21701.2, 21701.2", \ + "16052.9, 16052.9, 16052.9, 17966.2, 21792.9", \ + "16247.0, 16247.0, 16247.0, 18160.4, 21987.0"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("16816.3, 16816.3, 16816.3, 18729.6, 22556.3", \ + "22600.4, 22600.4, 22600.4, 22600.4, 22600.4", \ + "22688.5, 22688.5, 22688.5, 22688.5, 22688.5", \ + "22864.9, 22864.9, 22864.9, 22864.9, 22864.9", \ + "17478.0, 17478.0, 17478.0, 19391.4, 23218.1"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + when : "!(i0)" ; + rise_power (energy_inslew_load_5x5__36) { + values ("20322.2, 20322.2, 20322.2, 22235.5, 26062.2", \ + "26085.1, 26085.1, 26085.1, 26085.1, 26085.1", \ + "26130.9, 26130.9, 26130.9, 26130.9, 26130.9", \ + "20482.7, 20482.7, 20482.7, 22396.0, 26222.7", \ + "20680.3, 20680.3, 20680.3, 22593.7, 26420.3"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("22145.5, 22145.5, 22145.5, 24058.9, 27885.5", \ + "27929.6, 27929.6, 27929.6, 27929.6, 27929.6", \ + "28017.8, 28017.8, 28017.8, 28017.8, 28017.8", \ + "28194.2, 28194.2, 28194.2, 28194.2, 28194.2", \ + "22807.2, 22807.2, 22807.2, 24720.6, 28547.3"); + } + } + internal_power (energy_neg_q_i0) { + related_pin : "i0" ; + when : "i1" ; + rise_power (energy_inslew_load_5x5__36) { + values ("17912.6, 17912.6, 17912.6, 19825.9, 23652.6", \ + "18001.0, 18001.0, 18001.0, 19914.3, 23741.0", \ + "18177.8, 18177.8, 18177.8, 20091.1, 23917.8", \ + "18531.4, 18531.4, 18531.4, 20444.7, 24271.4", \ + "19238.5, 19238.5, 19238.5, 21151.9, 24978.6"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("17032.3, 17032.3, 17032.3, 18945.6, 22772.3", \ + "17078.0, 17078.0, 17078.0, 18991.3, 22818.0", \ + "17169.4, 17169.4, 17169.4, 19082.8, 22909.4", \ + "17352.3, 17352.3, 17352.3, 19265.6, 23092.3", \ + "17718.0, 17718.0, 17718.0, 19631.3, 23458.0"); + } + } + internal_power (energy_neg_q_i1) { + related_pin : "i1" ; + when : "i0" ; + rise_power (energy_inslew_load_5x5__36) { + values ("14718.2, 14718.2, 14718.2, 16631.5, 20458.2", \ + "14781.3, 14781.3, 14781.3, 16694.6, 20521.3", \ + "14907.6, 14907.6, 14907.6, 16820.9, 20647.6", \ + "15160.2, 15160.2, 15160.2, 17073.5, 20900.2", \ + "15665.4, 15665.4, 15665.4, 17578.7, 21405.4"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("11375.8, 11375.8, 11375.8, 13289.1, 17115.8", \ + "11426.2, 11426.2, 11426.2, 13339.5, 17166.2", \ + "11527.0, 11527.0, 11527.0, 13440.3, 17267.0", \ + "11728.6, 11728.6, 11728.6, 13642.0, 17468.6", \ + "12131.8, 12131.8, 12131.8, 14045.2, 17871.9"); + } + } + } + } + + cell (noa2ao222_x4) { + area : 43.20 ; + cell_leakage_power : 9.9 ; + leakage_power () { + when : "(i4 & i3 & i2 & i1 & i0)" ; + value : 9.5 ; + } + leakage_power () { + when : "(i0 & i1 & ((i2 & i3) ^ i4))" ; + value : 9.2 ; + } + leakage_power () { + when : "(i0 & i1 & !((i2 & i3)) & !(i4))" ; + value : 8.8 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & i3 & !(i4)) | (!(i2) & !(i3) & i4))) | (!(i0) & i1 & i2 & i3 & !(i4)))" ; + value : 12 ; + } + leakage_power () { + when : "((i0 & !(i1) & (i2 | i3) & i4) | (!(i0) & ((i1 & ((i2 | i3) ^ !(i4))) | (!(i1) & (i2 ^ i3) & !(i4)))))" ; + value : 10 ; + } + leakage_power () { + when : "((i0 & !(i1) & !((i2 & i3)) & !(i4)) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4)) | (!(i2) & (i3 ^ i4)))) | (!(i1) & ((i2 & i3) | i4)))))" ; + value : 11 ; + } + leakage_power () { + when : "(!(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 9.3 ; + } + pin (i4) { + direction : input ; + capacitance : 736.44 ; + } + pin (i3) { + direction : input ; + capacitance : 734.34 ; + } + pin (i2) { + direction : input ; + capacitance : 734.94 ; + } + pin (i1) { + direction : input ; + capacitance : 664.65 ; + } + pin (i0) { + direction : input ; + capacitance : 666.60 ; + } + pin (nq) { + function : "((!(i4) & (!(i0) | !(i1))) | (!((i0 & i1)) & !(i3) & !(i2)))" ; + direction : output ; + capacitance : 152.23 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__6) { + values ("22641.7, 22641.7, 22641.7, 22883.1, 23343.4", \ + "22634.6, 22634.6, 22634.6, 22876.0, 23336.3", \ + "22620.4, 22620.4, 22620.4, 22861.8, 23322.1", \ + "22591.9, 22591.9, 22591.9, 22833.3, 23293.6", \ + "22535.0, 22535.0, 22535.0, 22776.4, 23236.7"); + } + rise_transition (inslew_load_5x5__6) { + values ("6273.0, 6273.0, 6273.0, 6467.6, 6851.9", \ + "6273.0, 6273.0, 6273.0, 6467.6, 6851.9", \ + "6273.0, 6273.0, 6273.0, 6467.6, 6851.9", \ + "6273.0, 6273.0, 6273.0, 6467.6, 6851.9", \ + "6273.0, 6273.0, 6273.0, 6467.6, 6851.9"); + } + cell_fall (inslew_load_5x5__6) { + values ("14489.9, 14489.9, 14489.9, 14603.6, 15015.4", \ + "14484.7, 14484.7, 14484.7, 14598.4, 15010.2", \ + "14474.4, 14474.4, 14474.4, 14588.1, 14999.9", \ + "14453.7, 14453.7, 14453.7, 14567.4, 14979.2", \ + "14412.6, 14412.6, 14412.6, 14526.3, 14938.0"); + } + fall_transition (inslew_load_5x5__6) { + values ("3683.8, 3683.8, 3683.8, 3711.4, 4020.0", \ + "3683.8, 3683.8, 3683.8, 3711.4, 4020.0", \ + "3683.8, 3683.8, 3683.8, 3711.4, 4020.0", \ + "3683.8, 3683.8, 3683.8, 3711.4, 4020.0", \ + "3683.9, 3683.9, 3683.9, 3711.5, 4020.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__6) { + values ("21543.1, 21543.1, 21543.1, 21783.7, 22243.9", \ + "21536.0, 21536.0, 21536.0, 21776.6, 22236.8", \ + "21521.8, 21521.8, 21521.8, 21762.4, 22222.6", \ + "21493.4, 21493.4, 21493.4, 21734.0, 22194.2", \ + "21436.5, 21436.5, 21436.5, 21677.1, 22137.3"); + } + rise_transition (inslew_load_5x5__6) { + values ("5942.4, 5942.4, 5942.4, 6137.3, 6524.9", \ + "5942.4, 5942.4, 5942.4, 6137.3, 6524.9", \ + "5942.4, 5942.4, 5942.4, 6137.3, 6524.9", \ + "5942.4, 5942.4, 5942.4, 6137.3, 6524.9", \ + "5942.4, 5942.4, 5942.4, 6137.3, 6524.9"); + } + cell_fall (inslew_load_5x5__6) { + values ("13060.5, 13060.5, 13060.5, 13272.3, 13685.6", \ + "13065.6, 13065.6, 13065.6, 13277.4, 13690.7", \ + "13073.1, 13073.1, 13073.1, 13284.9, 13698.2", \ + "13089.7, 13089.7, 13089.7, 13301.5, 13714.8", \ + "13123.4, 13123.4, 13123.4, 13335.2, 13748.5"); + } + fall_transition (inslew_load_5x5__6) { + values ("3313.6, 3313.6, 3313.6, 3462.9, 3780.7", \ + "3314.4, 3314.4, 3314.4, 3463.6, 3781.4", \ + "3314.6, 3314.6, 3314.6, 3463.9, 3781.6", \ + "3314.7, 3314.7, 3314.7, 3463.9, 3781.7", \ + "3314.9, 3314.9, 3314.9, 3464.1, 3781.9"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__6) { + values ("12663.7, 12663.7, 12663.7, 12928.1, 13417.7", \ + "12640.6, 12640.6, 12640.6, 12905.0, 13394.6", \ + "12705.7, 12705.7, 12705.7, 12969.9, 13459.4", \ + "12743.5, 12743.5, 12743.5, 13007.6, 13497.0", \ + "12830.5, 12830.5, 12830.5, 13094.2, 13583.4"); + } + rise_transition (inslew_load_5x5__6) { + values ("3211.9, 3211.9, 3211.9, 3429.9, 3846.8", \ + "3207.5, 3207.5, 3207.5, 3425.6, 3842.6", \ + "3233.6, 3233.6, 3233.6, 3451.5, 3867.5", \ + "3254.7, 3254.7, 3254.7, 3472.1, 3887.6", \ + "3294.5, 3294.5, 3294.5, 3511.2, 3925.6"); + } + cell_fall (inslew_load_5x5__6) { + values ("13181.8, 13181.8, 13181.8, 13393.5, 13807.7", \ + "13176.7, 13176.7, 13176.7, 13388.4, 13802.6", \ + "13166.4, 13166.4, 13166.4, 13378.1, 13792.3", \ + "13145.7, 13145.7, 13145.7, 13357.4, 13771.6", \ + "13104.9, 13104.9, 13104.9, 13316.6, 13730.7"); + } + fall_transition (inslew_load_5x5__6) { + values ("3204.8, 3204.8, 3204.8, 3358.1, 3680.1", \ + "3204.8, 3204.8, 3204.8, 3358.1, 3680.1", \ + "3204.8, 3204.8, 3204.8, 3358.1, 3680.1", \ + "3204.8, 3204.8, 3204.8, 3358.1, 3680.1", \ + "3205.0, 3205.0, 3205.0, 3358.3, 3680.2"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__6) { + values ("17491.4, 17491.4, 17491.4, 17742.3, 18227.1", \ + "17478.9, 17478.9, 17478.9, 17729.8, 18214.6", \ + "17479.7, 17479.7, 17479.7, 17730.3, 18215.0", \ + "17461.0, 17461.0, 17461.0, 17711.4, 18196.2", \ + "17433.8, 17433.8, 17433.8, 17683.9, 18168.5"); + } + rise_transition (inslew_load_5x5__6) { + values ("4711.1, 4711.1, 4711.1, 4911.0, 5304.6", \ + "4710.7, 4710.7, 4710.7, 4910.6, 5304.2", \ + "4717.2, 4717.2, 4717.2, 4917.2, 5310.7", \ + "4722.6, 4722.6, 4722.6, 4922.6, 5316.0", \ + "4732.1, 4732.1, 4732.1, 4932.1, 5325.5"); + } + cell_fall (inslew_load_5x5__6) { + values ("15692.8, 15692.8, 15692.8, 15908.5, 16218.2", \ + "15687.6, 15687.6, 15687.6, 15903.3, 16213.0", \ + "15677.3, 15677.3, 15677.3, 15893.0, 16202.7", \ + "15656.6, 15656.6, 15656.6, 15872.3, 16182.0", \ + "15615.3, 15615.3, 15615.3, 15831.0, 16140.7"); + } + fall_transition (inslew_load_5x5__6) { + values ("3797.3, 3797.3, 3797.3, 3921.3, 4123.8", \ + "3797.3, 3797.3, 3797.3, 3921.3, 4123.8", \ + "3797.3, 3797.3, 3797.3, 3921.3, 4123.8", \ + "3797.3, 3797.3, 3797.3, 3921.3, 4123.8", \ + "3797.3, 3797.3, 3797.3, 3921.3, 4123.8"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__6) { + values ("10322.9, 10322.9, 10322.9, 10599.9, 11116.6", \ + "10350.3, 10350.3, 10350.3, 10626.7, 11143.3", \ + "10385.6, 10385.6, 10385.6, 10661.2, 11177.7", \ + "10411.7, 10411.7, 10411.7, 10686.6, 11202.9", \ + "10445.4, 10445.4, 10445.4, 10719.2, 11235.4"); + } + rise_transition (inslew_load_5x5__6) { + values ("2494.6, 2494.6, 2494.6, 2729.5, 3169.0", \ + "2504.6, 2504.6, 2504.6, 2739.1, 3178.3", \ + "2518.4, 2518.4, 2518.4, 2752.2, 3191.1", \ + "2530.3, 2530.3, 2530.3, 2763.6, 3202.1", \ + "2543.4, 2543.4, 2543.4, 2776.0, 3214.3"); + } + cell_fall (inslew_load_5x5__6) { + values ("11763.1, 11763.1, 11763.1, 11974.9, 12410.6", \ + "11768.4, 11768.4, 11768.4, 11980.3, 12415.8", \ + "11774.7, 11774.7, 11774.7, 11986.6, 12422.0", \ + "11792.1, 11792.1, 11792.1, 12003.9, 12439.3", \ + "11824.1, 11824.1, 11824.1, 12035.9, 12471.3"); + } + fall_transition (inslew_load_5x5__6) { + values ("2970.3, 2970.3, 2970.3, 3133.7, 3457.0", \ + "2970.6, 2970.6, 2970.6, 3134.0, 3457.3", \ + "2970.7, 2970.7, 2970.7, 3134.1, 3457.5", \ + "2971.0, 2971.0, 2971.0, 3134.3, 3457.7", \ + "2971.0, 2971.0, 2971.0, 3134.3, 3457.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__6) { + values ("104604.7, 104604.7, 104604.7, 106507.6, 110313.2", \ + "110391.2, 110391.2, 110391.2, 110391.2, 110391.2", \ + "110547.2, 110547.2, 110547.2, 110547.2, 110547.2", \ + "110859.1, 110859.1, 110859.1, 110859.1, 110859.1", \ + "111482.9, 111482.9, 111482.9, 111482.9, 111482.9"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("74531.5, 74531.5, 74531.5, 76434.3, 80240.0", \ + "80270.6, 80270.6, 80270.6, 80270.6, 80270.6", \ + "80331.9, 80331.9, 80331.9, 80331.9, 80331.9", \ + "80454.3, 80454.3, 80454.3, 80454.3, 80454.3", \ + "74991.7, 74991.7, 74991.7, 76894.6, 80700.2"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__6) { + values ("99039.5, 99039.5, 99039.5, 100942.4, 104748.0", \ + "104806.0, 104806.0, 104806.0, 104806.0, 104806.0", \ + "104922.0, 104922.0, 104922.0, 104922.0, 104922.0", \ + "105154.1, 105154.1, 105154.1, 105154.1, 105154.1", \ + "105618.1, 105618.1, 105618.1, 105618.1, 105618.1"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("66922.0, 66922.0, 66922.0, 68824.8, 72630.5", \ + "66963.5, 66963.5, 66963.5, 68866.3, 72672.0", \ + "67034.0, 67034.0, 67034.0, 68936.8, 72742.5", \ + "67170.8, 67170.8, 67170.8, 69073.6, 72879.3", \ + "67445.0, 67445.0, 67445.0, 69347.9, 73153.5"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__6) { + values ("58066.4, 58066.4, 58066.4, 59969.3, 63774.9", \ + "58088.6, 58088.6, 58088.6, 59991.5, 63797.1", \ + "58370.9, 58370.9, 58370.9, 60273.7, 64079.4", \ + "58722.9, 58722.9, 58722.9, 60625.7, 64431.4", \ + "59412.1, 59412.1, 59412.1, 61314.9, 65120.6"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("57663.6, 57663.6, 57663.6, 59566.4, 63372.1", \ + "63394.6, 63394.6, 63394.6, 63394.6, 63394.6", \ + "63439.5, 63439.5, 63439.5, 63439.5, 63439.5", \ + "63529.3, 63529.3, 63529.3, 63529.3, 63529.3", \ + "58002.2, 58002.2, 58002.2, 59905.0, 63710.7"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__6) { + values ("79192.9, 79192.9, 79192.9, 81095.7, 84901.4", \ + "79242.6, 79242.6, 79242.6, 81145.4, 84951.1", \ + "79399.3, 79399.3, 79399.3, 81302.1, 85107.8", \ + "79651.9, 79651.9, 79651.9, 81554.7, 85360.4", \ + "80148.1, 80148.1, 80148.1, 82050.9, 85856.6"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("68242.8, 68242.8, 68242.8, 70145.7, 73951.3", \ + "73982.1, 73982.1, 73982.1, 73982.1, 73982.1", \ + "74043.5, 74043.5, 74043.5, 74043.5, 74043.5", \ + "74166.3, 74166.3, 74166.3, 74166.3, 74166.3", \ + "68703.7, 68703.7, 68703.7, 70606.6, 74412.3"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__6) { + values ("51599.8, 51599.8, 51599.8, 53502.6, 57308.3", \ + "51698.1, 51698.1, 51698.1, 53601.0, 57406.6", \ + "51856.6, 51856.6, 51856.6, 53759.4, 57565.1", \ + "52079.5, 52079.5, 52079.5, 53982.3, 57788.0", \ + "52460.5, 52460.5, 52460.5, 54363.4, 58169.0"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("51554.5, 51554.5, 51554.5, 53457.3, 57263.0", \ + "51595.8, 51595.8, 51595.8, 53498.6, 57304.3", \ + "51665.6, 51665.6, 51665.6, 53568.5, 57374.1", \ + "51803.1, 51803.1, 51803.1, 53705.9, 57511.6", \ + "52068.2, 52068.2, 52068.2, 53971.0, 57776.7"); + } + } + } + } + + cell (noa2a2a23_x4) { + area : 46.80 ; + cell_leakage_power : 14 ; + leakage_power () { + when : "(i5 & !(i4) & !(i3) & i2 & !(i1) & i0)" ; + value : 15 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & !(i5)) | (!(i2) & i3 & (i4 ^ i5)))) | (!(i0) & i1 & (i2 ^ i3) & (i4 ^ i5)))" ; + value : 14 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((!(i3) & (i4 | i5)) | (i4 ^ i5))) | (!(i2) & i3 & (i4 | i5)))) | (!(i1) & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))))) | (!(i0) & ((i1 & ((i2 & i3 & (i4 ^ i5)) | (!(i2) & !(i3) & i4 & i5))) | (i2 & i3 & (i4 ^ i5)))))" ; + value : 17 ; + } + leakage_power () { + when : "((i0 & i1 & (!((i2 | i3)) | (!(i4) & !(i5)))) | (i2 & i3 & !(i4) & !(i5)))" ; + value : 16 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & ((i3 & !(i4) & !(i5)) | (!(i3) & (i4 ^ i5)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & ((i3 & !(i4) & !(i5)) | (!(i3) & (i4 ^ i5)))))) | (!(i1) & (i2 ^ i3) & (i4 ^ i5)))))" ; + value : 13 ; + } + leakage_power () { + when : "((!(i0) & !((i1 & !(i2) & !(i3))) & i4 & i5) | (!(i1) & (i2 | i3) & i4 & i5) | (i2 & i3 & i4 & i5))" ; + value : 18 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5)) | (!(i1) & ((i2 & !(i3) & !(i4) & !(i5)) | (!(i2) & ((i3 & !(i4) & !(i5)) | (!(i3) & (i4 ^ i5)))))))))" ; + value : 12 ; + } + leakage_power () { + when : "(!(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 11 ; + } + pin (i5) { + direction : input ; + capacitance : 845.77 ; + } + pin (i4) { + direction : input ; + capacitance : 848.32 ; + } + pin (i3) { + direction : input ; + capacitance : 845.17 ; + } + pin (i2) { + direction : input ; + capacitance : 844.87 ; + } + pin (i1) { + direction : input ; + capacitance : 844.57 ; + } + pin (i0) { + direction : input ; + capacitance : 843.97 ; + } + pin (nq) { + function : "((!(i4) & ((!(i2) & (!(i0) | !(i1))) | (!((i0 & i1)) & !(i3)))) | (!(i2) & !((i0 & i1)) & !(i5)) | (!((i0 & i1)) & !(i3) & !(i5)))" ; + direction : output ; + capacitance : 149.15 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("22427.2, 22427.2, 22427.2, 22663.6, 23115.3", \ + "22415.8, 22415.8, 22415.8, 22652.2, 23103.9", \ + "22393.0, 22393.0, 22393.0, 22629.4, 23081.1", \ + "22347.5, 22347.5, 22347.5, 22583.9, 23035.6", \ + "22256.4, 22256.4, 22256.4, 22492.8, 22944.5"); + } + rise_transition (inslew_load_5x5__37) { + values ("6097.0, 6097.0, 6097.0, 6287.9, 6665.9", \ + "6097.0, 6097.0, 6097.0, 6287.9, 6665.9", \ + "6097.0, 6097.0, 6097.0, 6287.9, 6665.9", \ + "6097.0, 6097.0, 6097.0, 6287.9, 6665.9", \ + "6097.0, 6097.0, 6097.0, 6287.9, 6665.9"); + } + cell_fall (inslew_load_5x5__37) { + values ("15209.1, 15209.1, 15209.1, 15420.9, 15723.1", \ + "15204.0, 15204.0, 15204.0, 15415.8, 15718.0", \ + "15193.7, 15193.7, 15193.7, 15405.5, 15707.7", \ + "15173.0, 15173.0, 15173.0, 15384.8, 15687.0", \ + "15131.8, 15131.8, 15131.8, 15343.6, 15645.8"); + } + fall_transition (inslew_load_5x5__37) { + values ("3797.4, 3797.4, 3797.4, 3918.5, 4114.0", \ + "3797.4, 3797.4, 3797.4, 3918.5, 4114.0", \ + "3797.4, 3797.4, 3797.4, 3918.5, 4114.0", \ + "3797.4, 3797.4, 3797.4, 3918.5, 4114.0", \ + "3797.5, 3797.5, 3797.5, 3918.6, 4114.0"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("21318.4, 21318.4, 21318.4, 21554.1, 22005.7", \ + "21307.0, 21307.0, 21307.0, 21542.7, 21994.3", \ + "21284.2, 21284.2, 21284.2, 21519.9, 21971.5", \ + "21238.7, 21238.7, 21238.7, 21474.4, 21926.0", \ + "21147.7, 21147.7, 21147.7, 21383.4, 21835.0"); + } + rise_transition (inslew_load_5x5__37) { + values ("5769.9, 5769.9, 5769.9, 5961.1, 6343.1", \ + "5769.9, 5769.9, 5769.9, 5961.1, 6343.1", \ + "5769.9, 5769.9, 5769.9, 5961.1, 6343.1", \ + "5769.9, 5769.9, 5769.9, 5961.1, 6343.1", \ + "5769.9, 5769.9, 5769.9, 5961.1, 6343.1"); + } + cell_fall (inslew_load_5x5__37) { + values ("13915.6, 13915.6, 13915.6, 14025.8, 14429.6", \ + "13920.3, 13920.3, 13920.3, 14030.8, 14434.6", \ + "13927.9, 13927.9, 13927.9, 14038.2, 14442.0", \ + "13944.3, 13944.3, 13944.3, 14054.8, 14458.6", \ + "13978.0, 13978.0, 13978.0, 14088.5, 14492.3"); + } + fall_transition (inslew_load_5x5__37) { + values ("3544.9, 3544.9, 3544.9, 3574.9, 3881.9", \ + "3545.2, 3545.2, 3545.2, 3575.6, 3882.6", \ + "3545.0, 3545.0, 3545.0, 3575.8, 3882.8", \ + "3545.2, 3545.2, 3545.2, 3575.9, 3882.9", \ + "3545.8, 3545.8, 3545.8, 3576.0, 3882.9"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("18108.5, 18108.5, 18108.5, 18349.3, 18824.7", \ + "18108.0, 18108.0, 18108.0, 18348.8, 18824.2", \ + "18096.5, 18096.5, 18096.5, 18337.2, 18812.6", \ + "18082.5, 18082.5, 18082.5, 18323.0, 18798.4", \ + "18046.0, 18046.0, 18046.0, 18286.3, 18761.7"); + } + rise_transition (inslew_load_5x5__37) { + values ("4825.4, 4825.4, 4825.4, 5021.7, 5406.7", \ + "4828.2, 4828.2, 4828.2, 5024.5, 5409.4", \ + "4830.1, 4830.1, 4830.1, 5026.4, 5411.3", \ + "4835.1, 4835.1, 4835.1, 5031.5, 5416.3", \ + "4838.8, 4838.8, 4838.8, 5035.2, 5420.0"); + } + cell_fall (inslew_load_5x5__37) { + values ("13636.1, 13636.1, 13636.1, 13844.6, 14248.6", \ + "13631.0, 13631.0, 13631.0, 13839.5, 14243.5", \ + "13620.7, 13620.7, 13620.7, 13829.2, 14233.2", \ + "13600.0, 13600.0, 13600.0, 13808.5, 14212.5", \ + "13559.0, 13559.0, 13559.0, 13767.6, 14171.5"); + } + fall_transition (inslew_load_5x5__37) { + values ("3390.7, 3390.7, 3390.7, 3533.7, 3842.4", \ + "3390.7, 3390.7, 3390.7, 3533.7, 3842.4", \ + "3390.7, 3390.7, 3390.7, 3533.7, 3842.4", \ + "3390.7, 3390.7, 3390.7, 3533.7, 3842.4", \ + "3390.8, 3390.8, 3390.8, 3533.9, 3842.6"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("16908.2, 16908.2, 16908.2, 17159.1, 17635.9", \ + "16907.8, 16907.8, 16907.8, 17158.6, 17635.4", \ + "16896.3, 16896.3, 16896.3, 17147.2, 17624.0", \ + "16882.1, 16882.1, 16882.1, 17133.0, 17609.7", \ + "16845.4, 16845.4, 16845.4, 17096.2, 17572.9"); + } + rise_transition (inslew_load_5x5__37) { + values ("4463.9, 4463.9, 4463.9, 4660.5, 5049.0", \ + "4466.8, 4466.8, 4466.8, 4663.4, 5051.8", \ + "4468.8, 4468.8, 4468.8, 4665.4, 5053.8", \ + "4473.9, 4473.9, 4473.9, 4670.4, 5058.7", \ + "4477.4, 4477.4, 4477.4, 4674.0, 5062.2"); + } + cell_fall (inslew_load_5x5__37) { + values ("12235.7, 12235.7, 12235.7, 12443.3, 12849.3", \ + "12240.7, 12240.7, 12240.7, 12448.3, 12854.3", \ + "12248.8, 12248.8, 12248.8, 12456.4, 12862.4", \ + "12265.2, 12265.2, 12265.2, 12472.8, 12878.8", \ + "12299.3, 12299.3, 12299.3, 12506.9, 12912.9"); + } + fall_transition (inslew_load_5x5__37) { + values ("3118.7, 3118.7, 3118.7, 3271.8, 3590.3", \ + "3119.4, 3119.4, 3119.4, 3272.6, 3591.0", \ + "3119.8, 3119.8, 3119.8, 3272.9, 3591.3", \ + "3119.8, 3119.8, 3119.8, 3273.0, 3591.4", \ + "3120.2, 3120.2, 3120.2, 3273.3, 3591.7"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("11611.0, 11611.0, 11611.0, 11873.5, 12368.1", \ + "11664.2, 11664.2, 11664.2, 11926.6, 12420.1", \ + "11737.4, 11737.4, 11737.4, 11999.5, 12491.7", \ + "11776.4, 11776.4, 11776.4, 12038.3, 12529.4", \ + "11895.8, 11895.8, 11895.8, 12157.3, 12645.9"); + } + rise_transition (inslew_load_5x5__37) { + values ("2825.1, 2825.1, 2825.1, 3045.0, 3466.1", \ + "2844.4, 2844.4, 2844.4, 3063.9, 3484.4", \ + "2872.3, 2872.3, 2872.3, 3091.3, 3510.9", \ + "2892.6, 2892.6, 2892.6, 3111.2, 3530.2", \ + "2941.6, 2941.6, 2941.6, 3159.4, 3576.9"); + } + cell_fall (inslew_load_5x5__37) { + values ("10308.1, 10308.1, 10308.1, 10515.9, 10948.8", \ + "10311.5, 10311.5, 10311.5, 10519.3, 10952.2", \ + "10320.2, 10320.2, 10320.2, 10528.0, 10960.8", \ + "10336.2, 10336.2, 10336.2, 10544.0, 10976.8", \ + "10366.7, 10366.7, 10366.7, 10574.5, 11007.4"); + } + fall_transition (inslew_load_5x5__37) { + values ("2931.7, 2931.7, 2931.7, 3092.9, 3411.3", \ + "2931.7, 2931.7, 2931.7, 3092.9, 3411.3", \ + "2931.8, 2931.8, 2931.8, 3093.0, 3411.4", \ + "2931.8, 2931.8, 2931.8, 3093.0, 3411.4", \ + "2932.0, 2932.0, 2932.0, 3093.2, 3411.5"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("13085.4, 13085.4, 13085.4, 13344.2, 13824.9", \ + "13132.6, 13132.6, 13132.6, 13391.2, 13871.8", \ + "13197.0, 13197.0, 13197.0, 13455.4, 13935.9", \ + "13227.0, 13227.0, 13227.0, 13485.3, 13965.7", \ + "13334.6, 13334.6, 13334.6, 13592.4, 14072.6"); + } + rise_transition (inslew_load_5x5__37) { + values ("3287.3, 3287.3, 3287.3, 3499.8, 3906.2", \ + "3304.9, 3304.9, 3304.9, 3517.0, 3923.1", \ + "3330.0, 3330.0, 3330.0, 3541.7, 3947.1", \ + "3347.5, 3347.5, 3347.5, 3559.0, 3963.9", \ + "3392.8, 3392.8, 3392.8, 3603.5, 4007.4"); + } + cell_fall (inslew_load_5x5__37) { + values ("11340.4, 11340.4, 11340.4, 11548.1, 11970.3", \ + "11335.3, 11335.3, 11335.3, 11543.0, 11965.2", \ + "11325.0, 11325.0, 11325.0, 11532.7, 11954.9", \ + "11304.3, 11304.3, 11304.3, 11512.0, 11934.2", \ + "11262.9, 11262.9, 11262.9, 11470.6, 11892.7"); + } + fall_transition (inslew_load_5x5__37) { + values ("2973.7, 2973.7, 2973.7, 3133.1, 3451.9", \ + "2973.7, 2973.7, 2973.7, 3133.1, 3451.9", \ + "2973.7, 2973.7, 2973.7, 3133.1, 3451.9", \ + "2973.7, 2973.7, 2973.7, 3133.1, 3451.9", \ + "2973.9, 2973.9, 2973.9, 3133.3, 3452.1"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__37) { + values ("106078.0, 106078.0, 106078.0, 107942.3, 111671.0", \ + "111759.4, 111759.4, 111759.4, 111759.4, 111759.4", \ + "111936.2, 111936.2, 111936.2, 111936.2, 111936.2", \ + "112289.8, 112289.8, 112289.8, 112289.8, 112289.8", \ + "112997.0, 112997.0, 112997.0, 112997.0, 112997.0"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("80406.9, 80406.9, 80406.9, 82271.3, 85999.9", \ + "86045.7, 86045.7, 86045.7, 86045.7, 86045.7", \ + "86137.1, 86137.1, 86137.1, 86137.1, 86137.1", \ + "86319.9, 86319.9, 86319.9, 86319.9, 86319.9", \ + "81093.0, 81093.0, 81093.0, 82957.3, 86686.0"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__37) { + values ("100173.3, 100173.3, 100173.3, 102037.6, 105766.3", \ + "105829.4, 105829.4, 105829.4, 105829.4, 105829.4", \ + "105955.7, 105955.7, 105955.7, 105955.7, 105955.7", \ + "106208.3, 106208.3, 106208.3, 106208.3, 106208.3", \ + "106713.5, 106713.5, 106713.5, 106713.5, 106713.5"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("72289.4, 72289.4, 72289.4, 74153.8, 77882.5", \ + "72347.1, 72347.1, 72347.1, 74211.5, 77940.2", \ + "72450.4, 72450.4, 72450.4, 74314.7, 78043.4", \ + "72652.7, 72652.7, 72652.7, 74517.0, 78245.7", \ + "73056.6, 73056.6, 73056.6, 74920.9, 78649.6"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__37) { + values ("83596.6, 83596.6, 83596.6, 85461.0, 89189.6", \ + "83703.9, 83703.9, 83703.9, 85568.2, 89296.9", \ + "83889.6, 83889.6, 83889.6, 85753.9, 89482.6", \ + "84270.7, 84270.7, 84270.7, 86135.0, 89863.7", \ + "84982.1, 84982.1, 84982.1, 86846.4, 90575.1"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("71357.4, 71357.4, 71357.4, 73221.8, 76950.4", \ + "76979.2, 76979.2, 76979.2, 76979.2, 76979.2", \ + "77036.7, 77036.7, 77036.7, 77036.7, 77036.7", \ + "77151.7, 77151.7, 77151.7, 77151.7, 77151.7", \ + "71790.3, 71790.3, 71790.3, 73654.6, 77383.3"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__37) { + values ("77588.4, 77588.4, 77588.4, 79452.8, 83181.4", \ + "77674.4, 77674.4, 77674.4, 79538.7, 83267.4", \ + "77817.4, 77817.4, 77817.4, 79681.7, 83410.4", \ + "78111.3, 78111.3, 78111.3, 79975.6, 83704.3", \ + "78649.0, 78649.0, 78649.0, 80513.3, 84242.0"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("63088.5, 63088.5, 63088.5, 64952.9, 68681.6", \ + "63128.3, 63128.3, 63128.3, 64992.7, 68721.3", \ + "63197.2, 63197.2, 63197.2, 65061.5, 68790.2", \ + "63328.8, 63328.8, 63328.8, 65193.2, 68921.9", \ + "63594.4, 63594.4, 63594.4, 65458.7, 69187.4"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__37) { + values ("54260.6, 54260.6, 54260.6, 56125.0, 59853.6", \ + "54447.0, 54447.0, 54447.0, 56311.3, 60040.0", \ + "54751.1, 54751.1, 54751.1, 56615.4, 60344.1", \ + "55131.4, 55131.4, 55131.4, 56995.8, 60724.4", \ + "55948.7, 55948.7, 55948.7, 57813.0, 61541.7"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("50784.2, 50784.2, 50784.2, 52648.6, 56377.3", \ + "50809.9, 50809.9, 50809.9, 52674.3, 56402.9", \ + "50859.3, 50859.3, 50859.3, 52723.7, 56452.4", \ + "56545.4, 56545.4, 56545.4, 56545.4, 56545.4", \ + "51148.6, 51148.6, 51148.6, 53013.0, 56741.7"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__37) { + values ("60520.4, 60520.4, 60520.4, 62384.7, 66113.4", \ + "60721.9, 60721.9, 60721.9, 62586.2, 66314.9", \ + "61057.4, 61057.4, 61057.4, 62921.7, 66650.4", \ + "61502.8, 61502.8, 61502.8, 63367.1, 67095.8", \ + "62465.8, 62465.8, 62465.8, 64330.1, 68058.8"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("57777.1, 57777.1, 57777.1, 59641.4, 63370.1", \ + "63389.9, 63389.9, 63389.9, 63389.9, 63389.9", \ + "63429.4, 63429.4, 63429.4, 63429.4, 63429.4", \ + "63508.5, 63508.5, 63508.5, 63508.5, 63508.5", \ + "58079.4, 58079.4, 58079.4, 59943.7, 63672.4"); + } + } + } + } + + cell (a4_x4) { + area : 28.80 ; + cell_leakage_power : 5.4 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 8.9 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & i0)" ; + value : 6 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3) | (!(i0) & i1 & i2 & i3))" ; + value : 5.7 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))) | (!(i0) & ((i1 & (i2 ^ i3)) | (!(i1) & i2 & i3))))" ; + value : 4.7 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))))" ; + value : 3.8 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 3.5 ; + } + pin (i3) { + direction : input ; + capacitance : 568.73 ; + } + pin (i2) { + direction : input ; + capacitance : 570.68 ; + } + pin (i1) { + direction : input ; + capacitance : 570.08 ; + } + pin (i0) { + direction : input ; + capacitance : 569.18 ; + } + pin (q) { + function : "(i3 & i2 & i1 & i0)" ; + direction : output ; + capacitance : 151.95 ; + timing (maxd_q_i0_positive_unate) { + related_pin : "i0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("14629.3, 14629.3, 14629.3, 14868.2, 15335.6", \ + "14614.8, 14614.8, 14614.8, 14853.8, 15321.1", \ + "14585.7, 14585.7, 14585.7, 14824.7, 15292.0", \ + "14527.6, 14527.6, 14527.6, 14766.6, 15233.9", \ + "14411.3, 14411.3, 14411.3, 14650.3, 15117.6"); + } + rise_transition (inslew_load_5x5__14) { + values ("9132.4, 9132.4, 9132.4, 9324.6, 9705.2", \ + "9132.5, 9132.5, 9132.5, 9324.6, 9705.2", \ + "9132.5, 9132.5, 9132.5, 9324.6, 9705.2", \ + "9132.5, 9132.5, 9132.5, 9324.6, 9705.2", \ + "9132.5, 9132.5, 9132.5, 9324.6, 9705.2"); + } + cell_fall (inslew_load_5x5__14) { + values ("10678.0, 10678.0, 10678.0, 10898.2, 11312.5", \ + "10686.8, 10686.8, 10686.8, 10907.0, 11321.3", \ + "10704.4, 10704.4, 10704.4, 10924.6, 11338.9", \ + "10739.6, 10739.6, 10739.6, 10959.8, 11374.1", \ + "10810.0, 10810.0, 10810.0, 11030.2, 11444.5"); + } + fall_transition (inslew_load_5x5__14) { + values ("4280.2, 4280.2, 4280.2, 4394.3, 4655.7", \ + "4280.2, 4280.2, 4280.2, 4394.3, 4655.7", \ + "4280.2, 4280.2, 4280.2, 4394.3, 4655.7", \ + "4280.2, 4280.2, 4280.2, 4394.3, 4655.7", \ + "4280.2, 4280.2, 4280.2, 4394.3, 4655.7"); + } + } + timing (maxd_q_i1_positive_unate) { + related_pin : "i1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("12895.0, 12895.0, 12895.0, 13135.2, 13600.9", \ + "12887.6, 12887.6, 12887.6, 13127.8, 13593.4", \ + "12869.9, 12869.9, 12869.9, 13110.1, 13575.8", \ + "12834.6, 12834.6, 12834.6, 13074.8, 13540.4", \ + "12764.5, 12764.5, 12764.5, 13004.7, 13470.3"); + } + rise_transition (inslew_load_5x5__14) { + values ("7937.5, 7937.5, 7937.5, 8132.1, 8512.4", \ + "7939.7, 7939.7, 7939.7, 8134.4, 8514.6", \ + "7940.5, 7940.5, 7940.5, 8135.2, 8515.4", \ + "7940.6, 7940.6, 7940.6, 8135.3, 8515.5", \ + "7940.6, 7940.6, 7940.6, 8135.3, 8515.5"); + } + cell_fall (inslew_load_5x5__14) { + values ("10074.9, 10074.9, 10074.9, 10292.8, 10704.9", \ + "10083.7, 10083.7, 10083.7, 10301.6, 10713.7", \ + "10101.3, 10101.3, 10101.3, 10319.2, 10731.3", \ + "10136.5, 10136.5, 10136.5, 10354.4, 10766.5", \ + "10206.9, 10206.9, 10206.9, 10424.8, 10836.9"); + } + fall_transition (inslew_load_5x5__14) { + values ("3976.1, 3976.1, 3976.1, 4096.8, 4370.5", \ + "3976.1, 3976.1, 3976.1, 4096.8, 4370.5", \ + "3976.1, 3976.1, 3976.1, 4096.8, 4370.5", \ + "3976.1, 3976.1, 3976.1, 4096.8, 4370.5", \ + "3976.1, 3976.1, 3976.1, 4096.8, 4370.5"); + } + } + timing (maxd_q_i2_positive_unate) { + related_pin : "i2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("11112.0, 11112.0, 11112.0, 11352.7, 11813.7", \ + "11112.2, 11112.2, 11112.2, 11352.8, 11813.9", \ + "11115.8, 11115.8, 11115.8, 11356.4, 11817.5", \ + "11105.1, 11105.1, 11105.1, 11345.7, 11806.9", \ + "11076.3, 11076.3, 11076.3, 11316.9, 11778.1"); + } + rise_transition (inslew_load_5x5__14) { + values ("6701.2, 6701.2, 6701.2, 6894.3, 7276.7", \ + "6708.2, 6708.2, 6708.2, 6901.2, 7283.6", \ + "6721.4, 6721.4, 6721.4, 6914.4, 7296.7", \ + "6728.1, 6728.1, 6728.1, 6921.0, 7303.3", \ + "6727.2, 6727.2, 6727.2, 6920.2, 7302.5"); + } + cell_fall (inslew_load_5x5__14) { + values ("9342.2, 9342.2, 9342.2, 9558.5, 9876.4", \ + "9351.0, 9351.0, 9351.0, 9567.3, 9885.2", \ + "9368.6, 9368.6, 9368.6, 9584.9, 9902.8", \ + "9403.8, 9403.8, 9403.8, 9620.1, 9938.0", \ + "9474.1, 9474.1, 9474.1, 9690.4, 10008.3"); + } + fall_transition (inslew_load_5x5__14) { + values ("3610.6, 3610.6, 3610.6, 3740.4, 3954.9", \ + "3610.6, 3610.6, 3610.6, 3740.4, 3954.9", \ + "3610.6, 3610.6, 3610.6, 3740.4, 3954.9", \ + "3610.6, 3610.6, 3610.6, 3740.4, 3954.9", \ + "3610.6, 3610.6, 3610.6, 3740.4, 3954.9"); + } + } + timing (maxd_q_i3_positive_unate) { + related_pin : "i3" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("9307.2, 9307.2, 9307.2, 9547.1, 10011.7", \ + "9318.3, 9318.3, 9318.3, 9558.2, 10022.3", \ + "9373.0, 9373.0, 9373.0, 9612.7, 10075.2", \ + "9417.5, 9417.5, 9417.5, 9657.2, 10118.4", \ + "9426.7, 9426.7, 9426.7, 9666.4, 10127.4"); + } + rise_transition (inslew_load_5x5__14) { + values ("5434.8, 5434.8, 5434.8, 5631.0, 6022.2", \ + "5449.0, 5449.0, 5449.0, 5645.2, 6036.3", \ + "5498.2, 5498.2, 5498.2, 5694.0, 6085.1", \ + "5540.2, 5540.2, 5540.2, 5735.8, 6126.9", \ + "5546.3, 5546.3, 5546.3, 5741.9, 6132.9"); + } + cell_fall (inslew_load_5x5__14) { + values ("8317.8, 8317.8, 8317.8, 8530.0, 8942.4", \ + "8326.6, 8326.6, 8326.6, 8538.8, 8951.2", \ + "8344.2, 8344.2, 8344.2, 8556.4, 8968.8", \ + "8379.3, 8379.3, 8379.3, 8591.5, 9003.9", \ + "8449.7, 8449.7, 8449.7, 8661.9, 9074.3"); + } + fall_transition (inslew_load_5x5__14) { + values ("3052.4, 3052.4, 3052.4, 3210.5, 3534.3", \ + "3052.4, 3052.4, 3052.4, 3210.5, 3534.3", \ + "3052.4, 3052.4, 3052.4, 3210.5, 3534.3", \ + "3052.4, 3052.4, 3052.4, 3210.5, 3534.3", \ + "3052.4, 3052.4, 3052.4, 3210.5, 3534.3"); + } + } + internal_power (energy_pos_q_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__14) { + values ("96609.7, 96609.7, 96609.7, 98509.1, 102307.8", \ + "96626.7, 96626.7, 96626.7, 98526.0, 102324.7", \ + "102357.9, 102357.9, 102357.9, 102357.9, 102357.9", \ + "102424.2, 102424.2, 102424.2, 102424.2, 102424.2", \ + "102557.0, 102557.0, 102557.0, 102557.0, 102557.0"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("58563.1, 58563.1, 58563.1, 60462.4, 64261.1", \ + "64339.9, 64339.9, 64339.9, 64339.9, 64339.9", \ + "64497.5, 64497.5, 64497.5, 64497.5, 64497.5", \ + "64812.8, 64812.8, 64812.8, 64812.8, 64812.8", \ + "65443.3, 65443.3, 65443.3, 65443.3, 65443.3"); + } + } + internal_power (energy_pos_q_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__14) { + values ("84141.1, 84141.1, 84141.1, 86040.4, 89839.1", \ + "84174.1, 84174.1, 84174.1, 86073.4, 89872.1", \ + "84218.1, 84218.1, 84218.1, 86117.5, 89916.2", \ + "84296.8, 84296.8, 84296.8, 86196.1, 89994.8", \ + "90151.3, 90151.3, 90151.3, 90151.3, 90151.3"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("54526.3, 54526.3, 54526.3, 56425.7, 60224.3", \ + "60285.8, 60285.8, 60285.8, 60285.8, 60285.8", \ + "60408.9, 60408.9, 60408.9, 60408.9, 60408.9", \ + "60654.9, 60654.9, 60654.9, 60654.9, 60654.9", \ + "61146.9, 61146.9, 61146.9, 61146.9, 61146.9"); + } + } + internal_power (energy_pos_q_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__14) { + values ("71563.8, 71563.8, 71563.8, 73463.2, 77261.8", \ + "71627.1, 71627.1, 71627.1, 73526.4, 77325.1", \ + "71749.3, 71749.3, 71749.3, 73648.6, 77447.3", \ + "71876.4, 71876.4, 71876.4, 73775.7, 77574.4", \ + "72046.4, 72046.4, 72046.4, 73945.7, 77744.4"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("49671.4, 49671.4, 49671.4, 51570.8, 55369.4", \ + "55419.0, 55419.0, 55419.0, 55419.0, 55419.0", \ + "55518.1, 55518.1, 55518.1, 55518.1, 55518.1", \ + "55716.3, 55716.3, 55716.3, 55716.3, 55716.3", \ + "56112.8, 56112.8, 56112.8, 56112.8, 56112.8"); + } + } + internal_power (energy_pos_q_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__14) { + values ("59354.8, 59354.8, 59354.8, 61254.1, 65052.8", \ + "59459.9, 59459.9, 59459.9, 61359.3, 65157.9", \ + "59790.1, 59790.1, 59790.1, 61689.5, 65488.1", \ + "60126.3, 60126.3, 60126.3, 62025.6, 65824.3", \ + "60349.5, 60349.5, 60349.5, 62248.9, 66047.6"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("43564.8, 43564.8, 43564.8, 45464.1, 49262.8", \ + "49303.8, 49303.8, 49303.8, 49303.8, 49303.8", \ + "49385.9, 49385.9, 49385.9, 49385.9, 49385.9", \ + "49550.2, 49550.2, 49550.2, 49550.2, 49550.2", \ + "49878.6, 49878.6, 49878.6, 49878.6, 49878.6"); + } + } + } + } + + cell (noa2a2a2a24_x4) { + area : 61.20 ; + cell_leakage_power : 22 ; + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & (i4 ^ i5) & (i6 ^ i7)) | (!(i2) & i3 & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))) | (!(i0) & i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))))" ; + value : 17 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7))) | (!(i2) & i3 & i4 & i5 & i6 & i7))) | (!(i1) & (((i2 | i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!((i2 | i3)) & i4 & i5 & i6 & i7))))) | (!(i0) & ((i1 & (((i2 | i3) & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))) | (!((i2 | i3)) & i4 & i5 & i6 & i7))) | (i2 & i3 & ((i4 & ((i5 & (i6 ^ i7)) | (!(i5) & i6 & i7))) | (!(i4) & i5 & i6 & i7))))))" ; + value : 29 ; + } + leakage_power () { + when : "((i0 & ((i1 & (!((i2 | i3)) | !((i4 | i5)) | (!(i6) & !(i7)))) | (i2 & i3 & (!((i4 | i5)) | (!(i6) & !(i7)))) | (i4 & i5 & !(i6) & !(i7)))) | (i1 & ((i2 & i3 & (!((i4 | i5)) | (!(i6) & !(i7)))) | (i4 & i5 & !(i6) & !(i7)))) | (i2 & i3 & (!((i4 | i5)) | (!(i6) & !(i7)))))" ; + value : 27 ; + } + leakage_power () { + when : "((!((i0 | i1)) & ((i2 & ((i3 & i4 & i5 & i6 & i7) | (!(i3) & (i4 ^ i5) & i6 & i7))) | (!(i2) & i3 & (i4 ^ i5) & i6 & i7))) | (i2 & i3 & i4 & i5 & i6 & i7))" ; + value : 31 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i2) & ((i3 & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & !(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i2) & ((i3 & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))) | (!(i3) & !(i4) & i5 & !(i6) & i7))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & i7) | (!(i4) & i5 & (i6 ^ i7)))) | (!(i2) & i3 & !(i4) & i5 & !(i6) & i7))))))" ; + value : 16 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & i4 & i5 & i6 & i7) | (!(i2) & ((i3 & i4 & i5 & i6 & i7) | (!(i3) & !((i4 & i5)) & i6 & i7))))) | (!(i0) & ((i1 & ((i2 & !(i3) & i4 & i5 & i6 & i7) | (!(i2) & ((i3 & i4 & i5 & i6 & i7) | (!(i3) & !((i4 & i5)) & i6 & i7))))) | (!(i1) & ((i2 & !(i3) & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & ((i4 & i5 & (i6 ^ i7)) | (!(i4) & !(i5) & i6 & i7))) | (i4 & i5 & (i6 ^ i7)))))))))" ; + value : 30 ; + } + leakage_power () { + when : "((i0 & ((i1 & ((i2 & ((!(i3) & ((i4 & ((!(i5) & (i6 | i7)) | (i6 ^ i7))) | (!(i4) & i5 & (i6 | i7)))) | ((i4 ^ i5) & (i6 ^ i7)))) | (!(i2) & i3 & ((i4 & ((!(i5) & (i6 | i7)) | (i6 ^ i7))) | (!(i4) & i5 & (i6 | i7)))))) | (!(i1) & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))))) | (!(i0) & ((i1 & ((i2 & ((i3 & (i4 ^ i5) & (i6 ^ i7)) | (!(i3) & !(i4) & !(i5) & i6 & i7))) | (!(i2) & ((i3 & !(i4) & !(i5) & i6 & i7) | (!(i3) & i4 & i5 & (i6 ^ i7)))))) | (!(i1) & ((i2 & i3 & (i4 ^ i5) & (i6 ^ i7)) | (!((i2 & i3)) & i4 & i5 & !(i6) & !(i7)))))))" ; + value : 28 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))))) | (!(i0) & ((i1 & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))))))))))" ; + value : 14 ; + } + leakage_power () { + when : "((i0 & !(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))))))) | (!(i0) & ((i1 & ((i2 & !(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & !(i5) & i6 & !(i7)))) | (!(i2) & ((i3 & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))) | (!(i3) & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))))))) | (!(i1) & ((i2 & !(i3) & ((i4 & !(i5) & i6 & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & !(i6) & i7))))) | (!(i2) & ((i3 & ((i4 & !(i5) & (i6 ^ i7)) | (!(i4) & i5 & i6 & !(i7)))) | (!(i3) & !(i4) & i5 & !(i6) & i7))))))))" ; + value : 15 ; + } + leakage_power () { + when : "(!(i0) & !(i1) & ((!(i2) & ((!(i3) & i6 & i7) | (i4 & i5 & i6 & i7))) | (!(i3) & i4 & i5 & i6 & i7)))" ; + value : 32 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i0) & ((i1 & !(i2) & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i1) & ((i2 & !(i3) & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i2) & ((i3 & !(i4) & !(i5) & !(i6) & !(i7)) | (!(i3) & ((i4 & !(i5) & !(i6) & !(i7)) | (!(i4) & ((i5 & !(i6) & !(i7)) | (!(i5) & (i6 ^ i7)))))))))))))" ; + value : 13 ; + } + leakage_power () { + when : "(!(i7) & !(i6) & !(i5) & !(i4) & !(i3) & !(i2) & !(i1) & !(i0))" ; + value : 12 ; + } + pin (i7) { + direction : input ; + capacitance : 846.52 ; + } + pin (i6) { + direction : input ; + capacitance : 845.97 ; + } + pin (i5) { + direction : input ; + capacitance : 843.97 ; + } + pin (i4) { + direction : input ; + capacitance : 843.97 ; + } + pin (i3) { + direction : input ; + capacitance : 843.97 ; + } + pin (i2) { + direction : input ; + capacitance : 844.87 ; + } + pin (i1) { + direction : input ; + capacitance : 844.87 ; + } + pin (i0) { + direction : input ; + capacitance : 847.36 ; + } + pin (nq) { + function : "((!(i7) & ((!(i4) & ((!(i3) & (!(i0) | !(i1))) | (!((i0 & i1)) & !(i2)))) | (!(i3) & !((i0 & i1)) & !(i5)) | (!((i0 & i1)) & !(i2) & !(i5)))) | (!(i4) & ((!(i3) & !((i0 & i1)) & !(i6)) | (!((i0 & i1)) & !(i2) & !(i6)))) | (!(i3) & !((i0 & i1)) & !(i5) & !(i6)) | (!((i0 & i1)) & !(i2) & !(i5) & !(i6)))" ; + direction : output ; + capacitance : 149.15 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("29929.9, 29929.9, 29929.9, 30165.8, 30623.9", \ + "29915.0, 29915.0, 29915.0, 30150.9, 30609.0", \ + "29885.3, 29885.3, 29885.3, 30121.2, 30579.3", \ + "29825.9, 29825.9, 29825.9, 30061.8, 30519.9", \ + "29707.2, 29707.2, 29707.2, 29943.1, 30401.2"); + } + rise_transition (inslew_load_5x5__37) { + values ("8628.8, 8628.8, 8628.8, 8818.2, 9190.6", \ + "8628.8, 8628.8, 8628.8, 8818.2, 9190.6", \ + "8628.8, 8628.8, 8628.8, 8818.2, 9190.6", \ + "8628.8, 8628.8, 8628.8, 8818.2, 9190.6", \ + "8628.8, 8628.8, 8628.8, 8818.2, 9190.6"); + } + cell_fall (inslew_load_5x5__37) { + values ("15378.5, 15378.5, 15378.5, 15590.5, 15892.6", \ + "15373.4, 15373.4, 15373.4, 15585.4, 15887.5", \ + "15363.0, 15363.0, 15363.0, 15575.0, 15877.1", \ + "15342.4, 15342.4, 15342.4, 15554.4, 15856.5", \ + "15301.2, 15301.2, 15301.2, 15513.2, 15815.3"); + } + fall_transition (inslew_load_5x5__37) { + values ("3831.2, 3831.2, 3831.2, 3951.5, 4145.0", \ + "3831.2, 3831.2, 3831.2, 3951.5, 4145.0", \ + "3831.2, 3831.2, 3831.2, 3951.5, 4145.0", \ + "3831.2, 3831.2, 3831.2, 3951.5, 4145.0", \ + "3831.3, 3831.3, 3831.3, 3951.6, 4145.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("28679.3, 28679.3, 28679.3, 28915.6, 29373.1", \ + "28664.5, 28664.5, 28664.5, 28900.8, 29358.3", \ + "28634.8, 28634.8, 28634.8, 28871.1, 29328.6", \ + "28575.4, 28575.4, 28575.4, 28811.7, 29269.2", \ + "28456.7, 28456.7, 28456.7, 28693.0, 29150.5"); + } + rise_transition (inslew_load_5x5__37) { + values ("8241.7, 8241.7, 8241.7, 8432.1, 8804.3", \ + "8241.7, 8241.7, 8241.7, 8432.1, 8804.3", \ + "8241.7, 8241.7, 8241.7, 8432.1, 8804.3", \ + "8241.7, 8241.7, 8241.7, 8432.1, 8804.3", \ + "8241.7, 8241.7, 8241.7, 8432.1, 8804.3"); + } + cell_fall (inslew_load_5x5__37) { + values ("14096.6, 14096.6, 14096.6, 14207.1, 14611.1", \ + "14101.6, 14101.6, 14101.6, 14212.1, 14616.1", \ + "14109.1, 14109.1, 14109.1, 14219.5, 14623.6", \ + "14125.7, 14125.7, 14125.7, 14236.1, 14640.2", \ + "14159.3, 14159.3, 14159.3, 14269.8, 14673.8"); + } + fall_transition (inslew_load_5x5__37) { + values ("3580.1, 3580.1, 3580.1, 3609.4, 3915.1", \ + "3580.9, 3580.9, 3580.9, 3610.2, 3915.8", \ + "3581.1, 3581.1, 3581.1, 3610.4, 3916.0", \ + "3581.0, 3581.0, 3581.0, 3610.5, 3916.1", \ + "3581.2, 3581.2, 3581.2, 3610.5, 3916.1"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("25407.8, 25407.8, 25407.8, 25644.6, 26099.1", \ + "25401.2, 25401.2, 25401.2, 25637.9, 26092.5", \ + "25378.6, 25378.6, 25378.6, 25615.4, 26069.9", \ + "25345.3, 25345.3, 25345.3, 25582.0, 26036.6", \ + "25273.8, 25273.8, 25273.8, 25510.5, 25965.1"); + } + rise_transition (inslew_load_5x5__37) { + values ("7219.3, 7219.3, 7219.3, 7408.7, 7782.6", \ + "7221.6, 7221.6, 7221.6, 7411.0, 7784.9", \ + "7222.5, 7222.5, 7222.5, 7412.0, 7785.8", \ + "7227.1, 7227.1, 7227.1, 7416.6, 7790.5", \ + "7231.3, 7231.3, 7231.3, 7420.8, 7794.7"); + } + cell_fall (inslew_load_5x5__37) { + values ("15283.5, 15283.5, 15283.5, 15495.4, 15797.6", \ + "15278.3, 15278.3, 15278.3, 15490.2, 15792.4", \ + "15268.0, 15268.0, 15268.0, 15479.9, 15782.1", \ + "15247.4, 15247.4, 15247.4, 15459.3, 15761.5", \ + "15206.2, 15206.2, 15206.2, 15418.1, 15720.3"); + } + fall_transition (inslew_load_5x5__37) { + values ("3812.0, 3812.0, 3812.0, 3932.8, 4127.4", \ + "3812.0, 3812.0, 3812.0, 3932.8, 4127.4", \ + "3812.0, 3812.0, 3812.0, 3932.8, 4127.4", \ + "3812.0, 3812.0, 3812.0, 3932.8, 4127.4", \ + "3812.0, 3812.0, 3812.0, 3932.8, 4127.4"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("24113.4, 24113.4, 24113.4, 24350.2, 24803.0", \ + "24106.6, 24106.6, 24106.6, 24343.4, 24796.3", \ + "24084.4, 24084.4, 24084.4, 24321.2, 24774.0", \ + "24051.0, 24051.0, 24051.0, 24287.8, 24740.6", \ + "23979.6, 23979.6, 23979.6, 24216.4, 24669.2"); + } + rise_transition (inslew_load_5x5__37) { + values ("6803.6, 6803.6, 6803.6, 6992.4, 7367.3", \ + "6805.8, 6805.8, 6805.8, 6994.6, 7369.4", \ + "6806.9, 6806.9, 6806.9, 6995.6, 7370.5", \ + "6811.4, 6811.4, 6811.4, 7000.1, 7375.0", \ + "6815.6, 6815.6, 6815.6, 7004.3, 7379.1"); + } + cell_fall (inslew_load_5x5__37) { + values ("13995.9, 13995.9, 13995.9, 14106.4, 14510.6", \ + "14001.1, 14001.1, 14001.1, 14111.5, 14515.7", \ + "14008.5, 14008.5, 14008.5, 14118.9, 14523.1", \ + "14025.0, 14025.0, 14025.0, 14135.5, 14539.7", \ + "14058.6, 14058.6, 14058.6, 14169.1, 14573.3"); + } + fall_transition (inslew_load_5x5__37) { + values ("3560.0, 3560.0, 3560.0, 3590.1, 3896.6", \ + "3560.6, 3560.6, 3560.6, 3590.9, 3897.3", \ + "3560.7, 3560.7, 3560.7, 3591.1, 3897.5", \ + "3560.8, 3560.8, 3560.8, 3591.2, 3897.6", \ + "3561.0, 3561.0, 3561.0, 3591.2, 3897.6"); + } + } + timing (maxd_nq_i4_negative_unate) { + related_pin : "i4" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("18910.2, 18910.2, 18910.2, 19146.3, 19612.6", \ + "18928.7, 18928.7, 18928.7, 19164.7, 19630.7", \ + "18949.5, 18949.5, 18949.5, 19185.4, 19650.9", \ + "18930.0, 18930.0, 18930.0, 19166.0, 19631.1", \ + "18946.1, 18946.1, 18946.1, 19182.0, 19646.0"); + } + rise_transition (inslew_load_5x5__37) { + values ("5164.6, 5164.6, 5164.6, 5359.1, 5743.7", \ + "5174.7, 5174.7, 5174.7, 5369.2, 5753.7", \ + "5189.3, 5189.3, 5189.3, 5383.7, 5768.2", \ + "5197.1, 5197.1, 5197.1, 5391.4, 5775.9", \ + "5226.8, 5226.8, 5226.8, 5420.9, 5805.3"); + } + cell_fall (inslew_load_5x5__37) { + values ("12318.2, 12318.2, 12318.2, 12525.8, 12931.8", \ + "12323.2, 12323.2, 12323.2, 12530.8, 12936.8", \ + "12331.3, 12331.3, 12331.3, 12538.9, 12944.9", \ + "12347.7, 12347.7, 12347.7, 12555.3, 12961.3", \ + "12381.7, 12381.7, 12381.7, 12589.4, 12995.4"); + } + fall_transition (inslew_load_5x5__37) { + values ("3135.0, 3135.0, 3135.0, 3287.6, 3605.4", \ + "3135.8, 3135.8, 3135.8, 3288.3, 3606.1", \ + "3136.1, 3136.1, 3136.1, 3288.6, 3606.4", \ + "3136.2, 3136.2, 3136.2, 3288.7, 3606.4", \ + "3136.5, 3136.5, 3136.5, 3289.0, 3606.8"); + } + } + timing (maxd_nq_i5_negative_unate) { + related_pin : "i5" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("20307.7, 20307.7, 20307.7, 20543.0, 20994.7", \ + "20326.0, 20326.0, 20326.0, 20561.3, 21013.0", \ + "20346.7, 20346.7, 20346.7, 20582.1, 21033.7", \ + "20326.6, 20326.6, 20326.6, 20562.1, 21013.7", \ + "20343.0, 20343.0, 20343.0, 20578.5, 21030.1"); + } + rise_transition (inslew_load_5x5__37) { + values ("5621.0, 5621.0, 5621.0, 5812.5, 6196.1", \ + "5630.7, 5630.7, 5630.7, 5822.1, 6205.7", \ + "5644.6, 5644.6, 5644.6, 5836.0, 6219.4", \ + "5651.9, 5651.9, 5651.9, 5843.3, 6226.6", \ + "5680.9, 5680.9, 5680.9, 5872.3, 6255.3"); + } + cell_fall (inslew_load_5x5__37) { + values ("13710.2, 13710.2, 13710.2, 13918.8, 14322.7", \ + "13705.1, 13705.1, 13705.1, 13913.7, 14317.6", \ + "13694.8, 13694.8, 13694.8, 13903.4, 14307.3", \ + "13674.1, 13674.1, 13674.1, 13882.7, 14286.6", \ + "13633.2, 13633.2, 13633.2, 13841.8, 14245.6"); + } + fall_transition (inslew_load_5x5__37) { + values ("3405.1, 3405.1, 3405.1, 3547.7, 3855.7", \ + "3405.1, 3405.1, 3405.1, 3547.7, 3855.7", \ + "3405.1, 3405.1, 3405.1, 3547.7, 3855.7", \ + "3405.1, 3405.1, 3405.1, 3547.7, 3855.7", \ + "3405.3, 3405.3, 3405.3, 3547.8, 3855.9"); + } + } + timing (maxd_nq_i6_negative_unate) { + related_pin : "i6" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("12348.0, 12348.0, 12348.0, 12608.8, 13093.1", \ + "12465.3, 12465.3, 12465.3, 12725.7, 13207.9", \ + "12622.2, 12622.2, 12622.2, 12882.2, 13363.8", \ + "12835.1, 12835.1, 12835.1, 13094.5, 13575.5", \ + "12947.3, 12947.3, 12947.3, 13206.1, 13686.9"); + } + rise_transition (inslew_load_5x5__37) { + values ("3026.4, 3026.4, 3026.4, 3242.8, 3657.7", \ + "3069.0, 3069.0, 3069.0, 3284.7, 3698.2", \ + "3128.0, 3128.0, 3128.0, 3342.9, 3754.3", \ + "3211.4, 3211.4, 3211.4, 3425.3, 3833.8", \ + "3270.5, 3270.5, 3270.5, 3483.3, 3890.2"); + } + cell_fall (inslew_load_5x5__37) { + values ("10364.4, 10364.4, 10364.4, 10572.2, 11004.6", \ + "10367.8, 10367.8, 10367.8, 10575.6, 11008.0", \ + "10376.5, 10376.5, 10376.5, 10584.3, 11016.7", \ + "10392.4, 10392.4, 10392.4, 10600.2, 11032.6", \ + "10423.3, 10423.3, 10423.3, 10631.1, 11063.5"); + } + fall_transition (inslew_load_5x5__37) { + values ("2933.1, 2933.1, 2933.1, 3094.3, 3412.7", \ + "2933.2, 2933.2, 2933.2, 3094.4, 3412.8", \ + "2933.3, 2933.3, 2933.3, 3094.4, 3412.8", \ + "2933.3, 2933.3, 2933.3, 3094.4, 3412.8", \ + "2933.5, 2933.5, 2933.5, 3094.6, 3413.0"); + } + } + timing (maxd_nq_i7_negative_unate) { + related_pin : "i7" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__37) { + values ("14148.4, 14148.4, 14148.4, 14404.4, 14883.7", \ + "14248.8, 14248.8, 14248.8, 14504.6, 14983.8", \ + "14382.4, 14382.4, 14382.4, 14637.8, 15116.8", \ + "14563.8, 14563.8, 14563.8, 14818.4, 15297.2", \ + "14649.2, 14649.2, 14649.2, 14903.4, 15382.1"); + } + rise_transition (inslew_load_5x5__37) { + values ("3621.9, 3621.9, 3621.9, 3829.1, 4228.2", \ + "3659.0, 3659.0, 3659.0, 3865.8, 4264.2", \ + "3710.6, 3710.6, 3710.6, 3916.8, 4314.1", \ + "3783.8, 3783.8, 3783.8, 3989.2, 4385.2", \ + "3834.3, 3834.3, 3834.3, 4038.8, 4434.2"); + } + cell_fall (inslew_load_5x5__37) { + values ("11392.0, 11392.0, 11392.0, 11599.7, 12021.2", \ + "11386.8, 11386.8, 11386.8, 11594.5, 12016.0", \ + "11376.5, 11376.5, 11376.5, 11584.2, 12005.7", \ + "11355.9, 11355.9, 11355.9, 11563.6, 11985.1", \ + "11314.7, 11314.7, 11314.7, 11522.4, 11943.8"); + } + fall_transition (inslew_load_5x5__37) { + values ("2976.4, 2976.4, 2976.4, 3135.6, 3454.4", \ + "2976.4, 2976.4, 2976.4, 3135.6, 3454.4", \ + "2976.4, 2976.4, 2976.4, 3135.6, 3454.4", \ + "2976.4, 2976.4, 2976.4, 3135.6, 3454.4", \ + "2976.5, 2976.5, 2976.5, 3135.8, 3454.6"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__37) { + values ("138584.7, 138584.7, 138584.7, 140449.1, 144177.7", \ + "144266.1, 144266.1, 144266.1, 144266.1, 144266.1", \ + "144442.9, 144442.9, 144442.9, 144442.9, 144442.9", \ + "144796.5, 144796.5, 144796.5, 144796.5, 144796.5", \ + "145503.7, 145503.7, 145503.7, 145503.7, 145503.7"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("81508.1, 81508.1, 81508.1, 83372.4, 87101.1", \ + "87146.8, 87146.8, 87146.8, 87146.8, 87146.8", \ + "87238.2, 87238.2, 87238.2, 87238.2, 87238.2", \ + "87421.1, 87421.1, 87421.1, 87421.1, 87421.1", \ + "82194.3, 82194.3, 82194.3, 84058.6, 87787.3"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__37) { + values ("131973.8, 131973.8, 131973.8, 133838.2, 137566.9", \ + "137630.0, 137630.0, 137630.0, 137630.0, 137630.0", \ + "137756.3, 137756.3, 137756.3, 137756.3, 137756.3", \ + "138008.9, 138008.9, 138008.9, 138008.9, 138008.9", \ + "138514.1, 138514.1, 138514.1, 138514.1, 138514.1"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("73407.2, 73407.2, 73407.2, 75271.6, 79000.2", \ + "73465.1, 73465.1, 73465.1, 75329.4, 79058.1", \ + "73568.1, 73568.1, 73568.1, 75432.5, 79161.2", \ + "73770.7, 73770.7, 73770.7, 75635.0, 79363.7", \ + "74174.5, 74174.5, 74174.5, 76038.9, 79767.5"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__37) { + values ("114896.5, 114896.5, 114896.5, 116760.8, 120489.5", \ + "115001.0, 115001.0, 115001.0, 116865.3, 120594.0", \ + "115180.3, 115180.3, 115180.3, 117044.7, 120773.3", \ + "115561.0, 115561.0, 115561.0, 117425.3, 121154.0", \ + "116279.5, 116279.5, 116279.5, 118143.8, 121872.5"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("80893.4, 80893.4, 80893.4, 82757.7, 86486.4", \ + "86515.2, 86515.2, 86515.2, 86515.2, 86515.2", \ + "86572.7, 86572.7, 86572.7, 86572.7, 86572.7", \ + "86687.7, 86687.7, 86687.7, 86687.7, 86687.7", \ + "81325.0, 81325.0, 81325.0, 83189.3, 86918.0"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__37) { + values ("108143.3, 108143.3, 108143.3, 110007.6, 113736.3", \ + "108225.9, 108225.9, 108225.9, 110090.3, 113818.9", \ + "108362.5, 108362.5, 108362.5, 110226.9, 113955.6", \ + "108656.2, 108656.2, 108656.2, 110520.5, 114249.2", \ + "109202.0, 109202.0, 109202.0, 111066.4, 114795.0"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("72784.0, 72784.0, 72784.0, 74648.4, 78377.1", \ + "72824.4, 72824.4, 72824.4, 74688.7, 78417.4", \ + "72892.3, 72892.3, 72892.3, 74756.7, 78485.3", \ + "73024.0, 73024.0, 73024.0, 74888.3, 78617.0", \ + "73286.7, 73286.7, 73286.7, 75151.0, 78879.7"); + } + } + internal_power (energy_neg_nq_i4) { + related_pin : "i4" ; + rise_power (energy_inslew_load_5x5__37) { + values ("82881.8, 82881.8, 82881.8, 84746.1, 88474.8", \ + "83025.3, 83025.3, 83025.3, 84889.7, 88618.3", \ + "83266.7, 83266.7, 83266.7, 85131.1, 88859.7", \ + "83578.0, 83578.0, 83578.0, 85442.3, 89171.0", \ + "84314.2, 84314.2, 84314.2, 86178.6, 89907.2"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("63562.5, 63562.5, 63562.5, 65426.8, 69155.5", \ + "63593.1, 63593.1, 63593.1, 65457.4, 69186.1", \ + "63643.0, 63643.0, 63643.0, 65507.3, 69236.0", \ + "63736.5, 63736.5, 63736.5, 65600.8, 69329.5", \ + "63926.1, 63926.1, 63926.1, 65790.5, 69519.2"); + } + } + internal_power (energy_neg_nq_i5) { + related_pin : "i5" ; + rise_power (energy_inslew_load_5x5__37) { + values ("89768.5, 89768.5, 89768.5, 91632.9, 95361.6", \ + "89929.6, 89929.6, 89929.6, 91793.9, 95522.6", \ + "90207.1, 90207.1, 90207.1, 92071.4, 95800.1", \ + "90591.9, 90591.9, 90591.9, 92456.2, 96184.9", \ + "91479.9, 91479.9, 91479.9, 93344.3, 97072.9"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("71819.8, 71819.8, 71819.8, 73684.1, 77412.8", \ + "77432.6, 77432.6, 77432.6, 77432.6, 77432.6", \ + "77472.1, 77472.1, 77472.1, 77472.1, 77472.1", \ + "77551.1, 77551.1, 77551.1, 77551.1, 77551.1", \ + "72117.8, 72117.8, 72117.8, 73982.2, 77710.9"); + } + } + internal_power (energy_neg_nq_i6) { + related_pin : "i6" ; + rise_power (energy_inslew_load_5x5__37) { + values ("55941.5, 55941.5, 55941.5, 57805.9, 61534.5", \ + "56284.7, 56284.7, 56284.7, 58149.0, 61877.7", \ + "56800.5, 56800.5, 56800.5, 58664.8, 62393.5", \ + "57606.2, 57606.2, 57606.2, 59470.5, 63199.2", \ + "58491.8, 58491.8, 58491.8, 60356.2, 64084.9"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("51154.1, 51154.1, 51154.1, 53018.4, 56747.1", \ + "51174.0, 51174.0, 51174.0, 53038.3, 56767.0", \ + "51211.4, 51211.4, 51211.4, 53075.7, 56804.4", \ + "56873.5, 56873.5, 56873.5, 56873.5, 56873.5", \ + "51428.5, 51428.5, 51428.5, 53292.8, 57021.5"); + } + } + internal_power (energy_neg_nq_i7) { + related_pin : "i7" ; + rise_power (energy_inslew_load_5x5__37) { + values ("63230.7, 63230.7, 63230.7, 65095.1, 68823.7", \ + "63573.0, 63573.0, 63573.0, 65437.3, 69166.0", \ + "64096.2, 64096.2, 64096.2, 65960.5, 69689.2", \ + "64931.8, 64931.8, 64931.8, 66796.2, 70524.8", \ + "65910.6, 65910.6, 65910.6, 67774.9, 71503.6"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("58153.4, 58153.4, 58153.4, 60017.7, 63746.4", \ + "63761.0, 63761.0, 63761.0, 63761.0, 63761.0", \ + "63790.0, 63790.0, 63790.0, 63790.0, 63790.0", \ + "63848.2, 63848.2, 63848.2, 63848.2, 63848.2", \ + "58377.0, 58377.0, 58377.0, 60241.3, 63970.0"); + } + } + } + } + + cell (no4_x1) { + area : 21.60 ; + cell_leakage_power : 2.9 ; + leakage_power () { + when : "((i0 & i1 & (i2 | !(i3))) | (i1 & !(i2) & !(i3)))" ; + value : 1.7 ; + } + leakage_power () { + when : "((i0 & (!(i1) | (!(i2) & i3))) | (!(i0) & (i2 | i3)))" ; + value : 1.4 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 5.6 ; + } + pin (i3) { + direction : input ; + capacitance : 714.80 ; + } + pin (i2) { + direction : input ; + capacitance : 715.70 ; + } + pin (i1) { + direction : input ; + capacitance : 715.10 ; + } + pin (i0) { + direction : input ; + capacitance : 715.40 ; + } + pin (nq) { + function : "(((!(i1) & !(i0)) & !(i2)) & !(i3))" ; + direction : output ; + capacitance : 116.80 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("6758.7, 6758.7, 6758.7, 7324.8, 8476.2", \ + "6767.1, 6767.1, 6767.1, 7333.4, 8485.1", \ + "6773.8, 6773.8, 6773.8, 7340.6, 8492.8", \ + "6761.0, 6761.0, 6761.0, 7328.0, 8480.5", \ + "6742.9, 6742.9, 6742.9, 7311.4, 8465.8"); + } + rise_transition (inslew_load_5x5__38) { + values ("9654.4, 9654.4, 9654.4, 10751.7, 12948.7", \ + "9692.2, 9692.2, 9692.2, 10789.9, 12987.4", \ + "9745.2, 9745.2, 9745.2, 10843.5, 13041.9", \ + "9790.0, 9790.0, 9790.0, 10888.4, 13087.1", \ + "9859.8, 9859.8, 9859.8, 10960.3, 13162.1"); + } + cell_fall (inslew_load_5x5__38) { + values ("2867.2, 2867.2, 2867.2, 3129.2, 3655.2", \ + "2876.0, 2876.0, 2876.0, 3138.0, 3664.0", \ + "2893.6, 2893.6, 2893.6, 3155.6, 3681.6", \ + "2928.7, 2928.7, 2928.7, 3190.8, 3716.8", \ + "2997.6, 2997.6, 2997.6, 3260.3, 3786.9"); + } + fall_transition (inslew_load_5x5__38) { + values ("2186.9, 2186.9, 2186.9, 2542.2, 3253.0", \ + "2186.9, 2186.9, 2186.9, 2542.2, 3253.0", \ + "2186.9, 2186.9, 2186.9, 2542.2, 3253.0", \ + "2186.9, 2186.9, 2186.9, 2542.3, 3253.0", \ + "2192.5, 2192.5, 2192.5, 2546.3, 3255.1"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("2387.4, 2387.4, 2387.4, 2988.9, 4185.3", \ + "2359.4, 2359.4, 2359.4, 2959.7, 4153.1", \ + "2441.4, 2441.4, 2441.4, 3039.0, 4226.0", \ + "2494.4, 2494.4, 2494.4, 3087.0, 4263.8", \ + "2609.6, 2609.6, 2609.6, 3199.6, 4370.9"); + } + rise_transition (inslew_load_5x5__38) { + values ("1644.6, 1644.6, 1644.6, 2772.2, 5030.1", \ + "1610.6, 1610.6, 1610.6, 2736.0, 4988.1", \ + "1801.8, 1801.8, 1801.8, 2922.3, 5162.2", \ + "1963.0, 1963.0, 1963.0, 3073.8, 5294.4", \ + "2279.1, 2279.1, 2279.1, 3378.1, 5584.4"); + } + cell_fall (inslew_load_5x5__38) { + values ("1725.4, 1725.4, 1725.4, 1994.4, 2528.3", \ + "1734.2, 1734.2, 1734.2, 2003.2, 2537.1", \ + "1751.8, 1751.8, 1751.8, 2020.8, 2554.7", \ + "1786.6, 1786.6, 1786.6, 2055.9, 2589.9", \ + "1836.9, 1836.9, 1836.9, 2115.5, 2657.1"); + } + fall_transition (inslew_load_5x5__38) { + values ("697.1, 697.1, 697.1, 1052.4, 1763.2", \ + "697.1, 697.1, 697.1, 1052.4, 1763.2", \ + "697.1, 697.1, 697.1, 1052.4, 1763.2", \ + "697.5, 697.5, 697.5, 1052.7, 1763.3", \ + "708.6, 708.6, 708.6, 1065.2, 1771.6"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("11169.5, 11169.5, 11169.5, 11706.4, 12825.9", \ + "11161.3, 11161.3, 11161.3, 11698.3, 12818.0", \ + "11141.2, 11141.2, 11141.2, 11678.4, 12798.2", \ + "11104.8, 11104.8, 11104.8, 11642.4, 12762.6", \ + "11029.0, 11029.0, 11029.0, 11567.4, 12688.2"); + } + rise_transition (inslew_load_5x5__38) { + values ("17571.5, 17571.5, 17571.5, 18656.2, 20825.8", \ + "17580.4, 17580.4, 17580.4, 18665.2, 20834.9", \ + "17587.2, 17587.2, 17587.2, 18672.1, 20841.8", \ + "17598.7, 17598.7, 17598.7, 18683.6, 20853.6", \ + "17600.5, 17600.5, 17600.5, 18685.5, 20855.5"); + } + cell_fall (inslew_load_5x5__38) { + values ("3552.7, 3552.7, 3552.7, 3810.5, 4331.7", \ + "3561.5, 3561.5, 3561.5, 3819.3, 4340.5", \ + "3579.0, 3579.0, 3579.0, 3836.9, 4358.1", \ + "3614.2, 3614.2, 3614.2, 3872.0, 4393.3", \ + "3684.2, 3684.2, 3684.2, 3942.2, 4463.6"); + } + fall_transition (inslew_load_5x5__38) { + values ("3081.3, 3081.3, 3081.3, 3436.7, 4147.4", \ + "3081.3, 3081.3, 3081.3, 3436.7, 4147.4", \ + "3081.3, 3081.3, 3081.3, 3436.7, 4147.4", \ + "3081.3, 3081.3, 3081.3, 3436.7, 4147.4", \ + "3083.6, 3083.6, 3083.6, 3438.3, 4148.3"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__38) { + values ("15494.1, 15494.1, 15494.1, 16000.0, 17085.4", \ + "15479.0, 15479.0, 15479.0, 15985.0, 17070.6", \ + "15448.8, 15448.8, 15448.8, 15955.1, 17040.8", \ + "15388.3, 15388.3, 15388.3, 15895.2, 16981.4", \ + "15267.4, 15267.4, 15267.4, 15775.4, 16862.5"); + } + rise_transition (inslew_load_5x5__38) { + values ("25213.4, 25213.4, 25213.4, 26284.5, 28426.7", \ + "25213.4, 25213.4, 25213.4, 26284.5, 28426.7", \ + "25213.4, 25213.4, 25213.4, 26284.5, 28426.7", \ + "25213.4, 25213.4, 25213.4, 26284.5, 28426.7", \ + "25213.4, 25213.4, 25213.4, 26284.5, 28426.7"); + } + cell_fall (inslew_load_5x5__38) { + values ("4046.7, 4046.7, 4046.7, 4301.5, 4819.4", \ + "4055.5, 4055.5, 4055.5, 4310.3, 4828.2", \ + "4073.1, 4073.1, 4073.1, 4327.9, 4845.7", \ + "4108.2, 4108.2, 4108.2, 4363.0, 4880.9", \ + "4178.4, 4178.4, 4178.4, 4433.3, 4951.3"); + } + fall_transition (inslew_load_5x5__38) { + values ("3725.9, 3725.9, 3725.9, 4081.3, 4792.1", \ + "3725.9, 3725.9, 3725.9, 4081.3, 4792.1", \ + "3725.9, 3725.9, 3725.9, 4081.3, 4792.1", \ + "3725.9, 3725.9, 3725.9, 4081.3, 4792.1", \ + "3727.1, 3727.1, 3727.1, 4082.2, 4792.5"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__38) { + values ("11364.7, 11364.7, 11364.7, 12824.7, 15744.8", \ + "11409.0, 11409.0, 11409.0, 12869.0, 15789.1", \ + "11497.6, 11497.6, 11497.6, 12957.6, 15877.7", \ + "11674.8, 11674.8, 11674.8, 13134.8, 16054.8", \ + "12029.1, 12029.1, 12029.1, 13489.1, 16409.2"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("7599.5, 7599.5, 7599.5, 9059.6, 11979.6", \ + "7626.0, 7626.0, 7626.0, 9086.1, 12006.1", \ + "7679.0, 7679.0, 7679.0, 9139.0, 12059.1", \ + "7784.9, 7784.9, 7784.9, 9245.0, 12165.0", \ + "7996.8, 7996.8, 7996.8, 9456.8, 12376.9"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__38) { + values ("1511.5, 1511.5, 1511.5, 2971.5, 5891.5", \ + "1555.4, 1555.4, 1555.4, 3015.5, 5935.5", \ + "1643.4, 1643.4, 1643.4, 3103.4, 6023.5", \ + "1819.3, 1819.3, 1819.3, 3279.3, 6199.4", \ + "2171.1, 2171.1, 2171.1, 3631.1, 6551.2"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("1472.9, 1472.9, 1472.9, 2932.9, 5852.9", \ + "1493.1, 1493.1, 1493.1, 2953.2, 5873.2", \ + "1533.7, 1533.7, 1533.7, 2993.7, 5913.7", \ + "1614.8, 1614.8, 1614.8, 3074.8, 5994.8", \ + "1776.9, 1776.9, 1776.9, 3237.0, 6157.0"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__38) { + values ("21934.2, 21934.2, 21934.2, 23394.2, 26314.2", \ + "21977.9, 21977.9, 21977.9, 23437.9, 26357.9", \ + "22065.3, 22065.3, 22065.3, 23525.3, 26445.4", \ + "22240.2, 22240.2, 22240.2, 23700.2, 26620.3", \ + "22590.0, 22590.0, 22590.0, 24050.0, 26970.1"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("11283.8, 11283.8, 11283.8, 12743.8, 15663.9", \ + "11320.0, 11320.0, 11320.0, 12780.1, 15700.1", \ + "11392.5, 11392.5, 11392.5, 12852.6, 15772.6", \ + "11537.5, 11537.5, 11537.5, 12997.5, 15917.6", \ + "11827.4, 11827.4, 11827.4, 13287.5, 16207.5"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__38) { + values ("32586.7, 32586.7, 32586.7, 34046.7, 36966.7", \ + "32626.6, 32626.6, 32626.6, 34086.6, 37006.6", \ + "32706.4, 32706.4, 32706.4, 34166.4, 37086.4", \ + "32865.9, 32865.9, 32865.9, 34326.0, 37246.0", \ + "33185.1, 33185.1, 33185.1, 34645.1, 37565.2"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("13950.8, 13950.8, 13950.8, 15410.8, 18330.8", \ + "14005.6, 14005.6, 14005.6, 15465.6, 18385.6", \ + "14115.1, 14115.1, 14115.1, 15575.2, 18495.2", \ + "14334.3, 14334.3, 14334.3, 15794.3, 18714.4", \ + "14772.6, 14772.6, 14772.6, 16232.6, 19152.7"); + } + } + } + } + + cell (sff1_x4) { + area : 64.80 ; + cell_leakage_power : 14 ; + pin (i) { + direction : input ; + capacitance : 435.57 ; + internal_power (energy_i) { + rise_power (energy_inslew_5__0) { + values ("21044.0, 21066.9, 21112.6, 21205.0, 21410.3"); + } + fall_power (energy_inslew_5__0) { + values ("19063.8, 19107.9, 19196.1, 19372.4, 19727.8"); + } + } + } + pin (ck) { + direction : input ; + clock : true ; + capacitance : 440.40 ; + internal_power (energy_ck) { + rise_power (energy_inslew_5__0) { + values ("46994.6, 47017.5, 47063.3, 47154.9, 47340.3"); + } + fall_power (energy_inslew_5__0) { + values ("48959.2, 49003.3, 49091.4, 49267.8, 49620.5"); + } + } + } + pin (q) { + direction : output ; + function : "IQ" ; + capacitance : 581.88 ; + } + ff(IQ,IQN) { + next_state : "i" ; + clocked_on : "ck" ; + } + } + + cell (na2_x1) { + area : 14.40 ; + cell_leakage_power : 2 ; + leakage_power () { + when : "(i1 & i0)" ; + value : 1.7 ; + } + leakage_power () { + when : "(!(i1) & i0)" ; + value : 2.8 ; + } + leakage_power () { + when : "(i1 & !(i0))" ; + value : 2.4 ; + } + leakage_power () { + when : "(!(i1) & !(i0))" ; + value : 1.4 ; + } + pin (i1) { + direction : input ; + capacitance : 572.98 ; + } + pin (i0) { + direction : input ; + capacitance : 573.73 ; + } + pin (nq) { + function : "(!(i0) | !(i1))" ; + direction : output ; + capacitance : 88.12 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("3038.6, 3038.6, 3038.6, 3367.3, 4026.0", \ + "3047.3, 3047.3, 3047.3, 3376.1, 4034.7", \ + "3064.9, 3064.9, 3064.9, 3393.6, 4052.3", \ + "3099.9, 3099.9, 3099.9, 3428.7, 4087.4", \ + "3168.8, 3168.8, 3168.8, 3498.3, 4157.5"); + } + rise_transition (inslew_load_5x5__17) { + values ("2276.3, 2276.3, 2276.3, 2724.4, 3620.6", \ + "2276.3, 2276.3, 2276.3, 2724.4, 3620.6", \ + "2276.3, 2276.3, 2276.3, 2724.4, 3620.6", \ + "2276.3, 2276.3, 2276.3, 2724.4, 3620.6", \ + "2280.4, 2280.4, 2280.4, 2727.1, 3621.8"); + } + cell_fall (inslew_load_5x5__17) { + values ("1776.3, 1776.3, 1776.3, 1932.4, 2247.0", \ + "1771.1, 1771.1, 1771.1, 1927.2, 2241.8", \ + "1760.8, 1760.8, 1760.8, 1916.9, 2231.5", \ + "1739.9, 1739.9, 1739.9, 1896.1, 2210.8", \ + "1686.7, 1686.7, 1686.7, 1846.6, 2165.5"); + } + fall_transition (inslew_load_5x5__17) { + values ("1831.9, 1831.9, 1831.9, 2079.0, 2573.1", \ + "1831.9, 1831.9, 1831.9, 2079.0, 2573.1", \ + "1831.9, 1831.9, 1831.9, 2079.0, 2573.1", \ + "1833.2, 1833.2, 1833.2, 2079.9, 2573.6", \ + "1859.6, 1859.6, 1859.6, 2102.5, 2589.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("1959.4, 1959.4, 1959.4, 2295.0, 2961.2", \ + "1968.2, 1968.2, 1968.2, 2303.8, 2970.0", \ + "1985.8, 1985.8, 1985.8, 2321.4, 2987.5", \ + "2020.8, 2020.8, 2020.8, 2356.5, 3022.7", \ + "2078.3, 2078.3, 2078.3, 2420.9, 3091.7"); + } + rise_transition (inslew_load_5x5__17) { + values ("853.6, 853.6, 853.6, 1301.8, 2198.0", \ + "853.6, 853.6, 853.6, 1301.8, 2198.0", \ + "853.6, 853.6, 853.6, 1301.8, 2198.0", \ + "853.8, 853.8, 853.8, 1301.9, 2198.0", \ + "862.3, 862.3, 862.3, 1310.3, 2202.6"); + } + cell_fall (inslew_load_5x5__17) { + values ("941.0, 941.0, 941.0, 1103.1, 1424.5", \ + "943.5, 943.5, 943.5, 1105.7, 1427.4", \ + "952.3, 952.3, 952.3, 1114.3, 1435.4", \ + "960.8, 960.8, 960.8, 1126.6, 1450.5", \ + "916.2, 916.2, 916.2, 1107.4, 1459.2"); + } + fall_transition (inslew_load_5x5__17) { + values ("565.9, 565.9, 565.9, 817.1, 1318.8", \ + "567.8, 567.8, 567.8, 819.1, 1321.3", \ + "572.1, 572.1, 572.1, 822.9, 1323.9", \ + "576.5, 576.5, 576.5, 827.1, 1326.2", \ + "600.1, 600.1, 600.1, 858.5, 1358.4"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__17) { + values ("4649.5, 4649.5, 4649.5, 5751.0, 7953.9", \ + "4728.3, 4728.3, 4728.3, 5829.8, 8032.7", \ + "4885.9, 4885.9, 4885.9, 5987.4, 8190.4", \ + "5201.2, 5201.2, 5201.2, 6302.6, 8505.6", \ + "5831.7, 5831.7, 5831.7, 6933.1, 9136.1"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("6806.8, 6806.8, 6806.8, 7908.3, 10111.2", \ + "6823.4, 6823.4, 6823.4, 7924.9, 10127.8", \ + "6856.6, 6856.6, 6856.6, 7958.1, 10161.0", \ + "6922.9, 6922.9, 6922.9, 8024.4, 10227.4", \ + "7055.7, 7055.7, 7055.7, 8157.2, 10360.1"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__17) { + values ("1135.4, 1135.4, 1135.4, 2236.9, 4439.9", \ + "1196.9, 1196.9, 1196.9, 2298.4, 4501.4", \ + "1319.9, 1319.9, 1319.9, 2421.4, 4624.4", \ + "1566.0, 1566.0, 1566.0, 2667.4, 4870.4", \ + "2058.0, 2058.0, 2058.0, 3159.5, 5362.4"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("1148.6, 1148.6, 1148.6, 2250.1, 4453.0", \ + "1168.2, 1168.2, 1168.2, 2269.6, 4472.6", \ + "1207.3, 1207.3, 1207.3, 2308.8, 4511.7", \ + "1285.6, 1285.6, 1285.6, 2387.1, 4590.0", \ + "1442.1, 1442.1, 1442.1, 2543.6, 4746.5"); + } + } + } + } + + cell (powmid_x0) { + area : 25.20 ; + cell_leakage_power : 0 ; + } + + cell (na4_x1) { + area : 21.60 ; + cell_leakage_power : 1.7 ; + leakage_power () { + when : "(i3 & i2 & i1 & i0)" ; + value : 3.3 ; + } + leakage_power () { + when : "(!(i3) & i2 & i1 & i0)" ; + value : 2.7 ; + } + leakage_power () { + when : "((i0 & (i1 ^ i2) & i3) | (!(i0) & i1 & i2 & i3))" ; + value : 2.3 ; + } + leakage_power () { + when : "((i0 & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))) | (!(i0) & ((i1 & (i2 ^ i3)) | (!(i1) & i2 & i3))))" ; + value : 1.4 ; + } + leakage_power () { + when : "((i0 & !(i1) & !(i2) & !(i3)) | (!(i0) & ((i1 & !(i2) & !(i3)) | (!(i1) & (i2 ^ i3)))))" ; + value : 0.46 ; + } + leakage_power () { + when : "(!(i3) & !(i2) & !(i1) & !(i0))" ; + value : 0.2 ; + } + pin (i3) { + direction : input ; + capacitance : 573.08 ; + } + pin (i2) { + direction : input ; + capacitance : 572.48 ; + } + pin (i1) { + direction : input ; + capacitance : 571.58 ; + } + pin (i0) { + direction : input ; + capacitance : 570.68 ; + } + pin (nq) { + function : "(((!(i1) | !(i2)) | !(i3)) | !(i0))" ; + direction : output ; + capacitance : 136.46 ; + timing (maxd_nq_i0_negative_unate) { + related_pin : "i0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("4765.3, 4765.3, 4765.3, 5263.8, 6274.3", \ + "4774.0, 4774.0, 4774.0, 5272.6, 6283.0", \ + "4791.5, 4791.5, 4791.5, 5290.1, 6300.6", \ + "4826.6, 4826.6, 4826.6, 5325.2, 6335.8", \ + "4896.6, 4896.6, 4896.6, 5395.4, 6406.1"); + } + rise_transition (inslew_load_5x5__39) { + values ("4567.2, 4567.2, 4567.2, 5261.2, 6649.1", \ + "4567.2, 4567.2, 4567.2, 5261.2, 6649.1", \ + "4567.2, 4567.2, 4567.2, 5261.2, 6649.1", \ + "4567.2, 4567.2, 4567.2, 5261.2, 6649.1", \ + "4567.7, 4567.7, 4567.7, 5261.4, 6649.2"); + } + cell_fall (inslew_load_5x5__39) { + values ("5317.1, 5317.1, 5317.1, 5699.9, 6485.5", \ + "5302.5, 5302.5, 5302.5, 5685.3, 6470.9", \ + "5273.4, 5273.4, 5273.4, 5656.2, 6441.8", \ + "5215.0, 5215.0, 5215.0, 5597.9, 6383.7", \ + "5098.4, 5098.4, 5098.4, 5481.4, 6267.3"); + } + fall_transition (inslew_load_5x5__39) { + values ("8012.2, 8012.2, 8012.2, 8746.6, 10215.4", \ + "8012.2, 8012.2, 8012.2, 8746.6, 10215.4", \ + "8012.2, 8012.2, 8012.2, 8746.6, 10215.4", \ + "8012.2, 8012.2, 8012.2, 8746.6, 10215.4", \ + "8012.6, 8012.6, 8012.6, 8746.8, 10215.5"); + } + } + timing (maxd_nq_i1_negative_unate) { + related_pin : "i1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("4056.5, 4056.5, 4056.5, 4560.0, 5575.2", \ + "4065.2, 4065.2, 4065.2, 4568.8, 5584.0", \ + "4082.8, 4082.8, 4082.8, 4586.4, 5601.5", \ + "4117.8, 4117.8, 4117.8, 4621.5, 5636.7", \ + "4187.9, 4187.9, 4187.9, 4691.7, 5707.0"); + } + rise_transition (inslew_load_5x5__39) { + values ("3629.5, 3629.5, 3629.5, 4323.5, 5711.4", \ + "3629.5, 3629.5, 3629.5, 4323.5, 5711.4", \ + "3629.5, 3629.5, 3629.5, 4323.5, 5711.4", \ + "3629.5, 3629.5, 3629.5, 4323.5, 5711.4", \ + "3630.6, 3630.6, 3630.6, 4324.0, 5711.5"); + } + cell_fall (inslew_load_5x5__39) { + values ("4079.9, 4079.9, 4079.9, 4472.6, 5269.7", \ + "4071.1, 4071.1, 4071.1, 4463.8, 5261.0", \ + "4052.8, 4052.8, 4052.8, 4445.6, 5242.9", \ + "4017.2, 4017.2, 4017.2, 4410.1, 5207.4", \ + "3946.8, 3946.8, 3946.8, 4339.9, 5137.2"); + } + fall_transition (inslew_load_5x5__39) { + values ("5842.6, 5842.6, 5842.6, 6586.1, 8073.0", \ + "5845.9, 5845.9, 5845.9, 6589.5, 8076.6", \ + "5847.1, 5847.1, 5847.1, 6590.7, 8077.8", \ + "5847.1, 5847.1, 5847.1, 6590.7, 8077.9", \ + "5848.8, 5848.8, 5848.8, 6591.8, 8078.3"); + } + } + timing (maxd_nq_i2_negative_unate) { + related_pin : "i2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("3202.4, 3202.4, 3202.4, 3712.1, 4732.9", \ + "3211.2, 3211.2, 3211.2, 3720.8, 4741.6", \ + "3228.8, 3228.8, 3228.8, 3738.4, 4759.2", \ + "3263.9, 3263.9, 3263.9, 3773.6, 4794.4", \ + "3333.4, 3333.4, 3333.4, 3843.6, 4864.7"); + } + rise_transition (inslew_load_5x5__39) { + values ("2499.7, 2499.7, 2499.7, 3193.6, 4581.5", \ + "2499.7, 2499.7, 2499.7, 3193.6, 4581.5", \ + "2499.7, 2499.7, 2499.7, 3193.6, 4581.5", \ + "2499.7, 2499.7, 2499.7, 3193.6, 4581.5", \ + "2503.0, 2503.0, 2503.0, 3195.4, 4582.0"); + } + cell_fall (inslew_load_5x5__39) { + values ("2828.8, 2828.8, 2828.8, 3230.3, 4037.8", \ + "2825.7, 2825.7, 2825.7, 3227.2, 4034.7", \ + "2820.5, 2820.5, 2820.5, 3222.6, 4030.8", \ + "2804.5, 2804.5, 2804.5, 3207.1, 4016.0", \ + "2776.6, 2776.6, 2776.6, 3179.7, 3988.5"); + } + fall_transition (inslew_load_5x5__39) { + values ("3618.8, 3618.8, 3618.8, 4370.5, 5876.2", \ + "3630.5, 3630.5, 3630.5, 4382.2, 5887.9", \ + "3648.1, 3648.1, 3648.1, 4400.9, 5907.9", \ + "3655.5, 3655.5, 3655.5, 4409.1, 5917.3", \ + "3665.3, 3665.3, 3665.3, 4415.3, 5919.4"); + } + } + timing (maxd_nq_i3_negative_unate) { + related_pin : "i3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("2127.1, 2127.1, 2127.1, 2644.3, 3672.3", \ + "2135.9, 2135.9, 2135.9, 2653.1, 3681.1", \ + "2153.5, 2153.5, 2153.5, 2670.7, 3698.7", \ + "2188.6, 2188.6, 2188.6, 2705.9, 3733.8", \ + "2250.2, 2250.2, 2250.2, 2773.6, 3803.9"); + } + rise_transition (inslew_load_5x5__39) { + values ("1077.0, 1077.0, 1077.0, 1771.0, 3158.9", \ + "1077.0, 1077.0, 1077.0, 1771.0, 3158.9", \ + "1077.0, 1077.0, 1077.0, 1771.0, 3158.9", \ + "1077.2, 1077.2, 1077.2, 1771.0, 3158.9", \ + "1086.2, 1086.2, 1086.2, 1777.5, 3160.8"); + } + cell_fall (inslew_load_5x5__39) { + values ("1579.7, 1579.7, 1579.7, 1992.3, 2813.1", \ + "1591.2, 1591.2, 1591.2, 2002.1, 2820.2", \ + "1626.4, 1626.4, 1626.4, 2035.9, 2852.1", \ + "1648.0, 1648.0, 1648.0, 2057.7, 2874.6", \ + "1648.9, 1648.9, 1648.9, 2064.8, 2883.5"); + } + fall_transition (inslew_load_5x5__39) { + values ("1354.0, 1354.0, 1354.0, 2120.8, 3655.0", \ + "1391.2, 1391.2, 1391.2, 2154.8, 3683.9", \ + "1480.8, 1480.8, 1480.8, 2241.8, 3767.3", \ + "1547.3, 1547.3, 1547.3, 2307.4, 3833.8", \ + "1603.2, 1603.2, 1603.2, 2348.8, 3857.7"); + } + } + internal_power (energy_neg_nq_i0) { + related_pin : "i0" ; + rise_power (energy_inslew_load_5x5__39) { + values ("10280.7, 10280.7, 10280.7, 11986.4, 15397.8", \ + "10359.5, 10359.5, 10359.5, 12065.2, 15476.6", \ + "10517.1, 10517.1, 10517.1, 12222.8, 15634.2", \ + "10832.3, 10832.3, 10832.3, 12538.0, 15949.5", \ + "11462.8, 11462.8, 11462.8, 13168.5, 16579.9"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("16887.5, 16887.5, 16887.5, 18593.2, 22004.7", \ + "16904.1, 16904.1, 16904.1, 18609.8, 22021.3", \ + "16937.3, 16937.3, 16937.3, 18643.0, 22054.4", \ + "17003.7, 17003.7, 17003.7, 18709.4, 22120.8", \ + "17136.4, 17136.4, 17136.4, 18842.1, 22253.5"); + } + } + internal_power (energy_neg_nq_i1) { + related_pin : "i1" ; + rise_power (energy_inslew_load_5x5__39) { + values ("7958.5, 7958.5, 7958.5, 9664.2, 13075.6", \ + "8020.0, 8020.0, 8020.0, 9725.7, 13137.1", \ + "8143.0, 8143.0, 8143.0, 9848.7, 13260.1", \ + "8389.0, 8389.0, 8389.0, 10094.7, 13506.1", \ + "8881.0, 8881.0, 8881.0, 10586.7, 13998.2"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("11718.6, 11718.6, 11718.6, 13424.3, 16835.7", \ + "11738.2, 11738.2, 11738.2, 13443.9, 16855.3", \ + "11777.3, 11777.3, 11777.3, 13483.0, 16894.4", \ + "11855.6, 11855.6, 11855.6, 13561.3, 16972.7", \ + "12012.1, 12012.1, 12012.1, 13717.8, 17129.3"); + } + } + internal_power (energy_neg_nq_i2) { + related_pin : "i2" ; + rise_power (energy_inslew_load_5x5__39) { + values ("5169.4, 5169.4, 5169.4, 6875.1, 10286.5", \ + "5218.9, 5218.9, 5218.9, 6924.6, 10336.1", \ + "5318.0, 5318.0, 5318.0, 7023.8, 10435.2", \ + "5516.3, 5516.3, 5516.3, 7222.0, 10633.4", \ + "5912.7, 5912.7, 5912.7, 7618.4, 11029.9"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("6592.1, 6592.1, 6592.1, 8297.8, 11709.2", \ + "6614.0, 6614.0, 6614.0, 8319.7, 11731.1", \ + "6657.7, 6657.7, 6657.7, 8363.4, 11774.8", \ + "6745.2, 6745.2, 6745.2, 8450.9, 11862.3", \ + "6920.1, 6920.1, 6920.1, 8625.8, 12037.3"); + } + } + internal_power (energy_neg_nq_i3) { + related_pin : "i3" ; + rise_power (energy_inslew_load_5x5__39) { + values ("1664.1, 1664.1, 1664.1, 3369.8, 6781.2", \ + "1705.2, 1705.2, 1705.2, 3410.9, 6822.3", \ + "1787.3, 1787.3, 1787.3, 3493.0, 6904.4", \ + "1951.5, 1951.5, 1951.5, 3657.2, 7068.6", \ + "2279.9, 2279.9, 2279.9, 3985.6, 7397.1"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("1811.9, 1811.9, 1811.9, 3517.6, 6929.0", \ + "1835.4, 1835.4, 1835.4, 3541.1, 6952.5", \ + "1882.3, 1882.3, 1882.3, 3588.0, 6999.5", \ + "1976.3, 1976.3, 1976.3, 3682.0, 7093.4", \ + "2164.2, 2164.2, 2164.2, 3869.9, 7281.3"); + } + } + } + } + +} diff --git a/pdks/symbolic/sxlib/cells/sxlib.sdb b/pdks/symbolic/sxlib/cells/sxlib.sdb new file mode 100644 index 000000000..86798ed26 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/sxlib.sdb differ diff --git a/pdks/symbolic/sxlib/cells/sxlib.slib b/pdks/symbolic/sxlib/cells/sxlib.slib new file mode 100644 index 000000000..6f4d0f4a2 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sxlib.slib @@ -0,0 +1,472 @@ +/****************************************************************************** + ** + ** FILE NAME: sclib.slib + ** + ** Created by Mokhtar HIRECH (MASI laboratory) on 26 October 1995 + ** from $SYNOPSYS/libraries/syn/class.slib + ** + ** Modified September 1, 1999 Franck + ** + ***************************************************************************** +*/ + + +TRUE = 1; +FALSE = 0; + + +library("sxlib.sdb") { + + ROUTE_GRID = 1024; + INCHES_PER_GRID = .1; + DB_PER_GRID = ROUTE_GRID; + + CENTEMETERS_PER_GRID = INCHES_PER_GRID * 2.54; + METERS_PER_GRID = CENTEMETERS_PER_GRID / 100; + METERS_PER_DB = METERS_PER_GRID / DB_PER_GRID; + + set_route_grid(ROUTE_GRID); + set_external_scale(METERS_PER_DB); + set_meter_scale(METERS_PER_DB); + + grid_pins : TRUE ; + + + + /* note: One ROUTE_GRID is equivalent to 13 / 2 "units" of the IEEE / ANSI symbol + * standard (Std 91 - 1984). One ROUTE_GRID is equivalent to .2 MIL standard + * units (inches) (MIL - STD - 8086) + * Dimensions were derrived from these standards. + * + * - *************************** + * | * **** + * | *** - ** + * | * **** | * + * | ******* *** DYNAMIC HEIGHT * **** -------- + * * **** | * * * | + * AND_HEIGHT *** - ** * BUBBLE_DIAMETER + * * ** * | + * | <-------> *. **** -------- + * | * DYNAMIC WIDTH *. + * | ******* * . + * | * ** . + * | * *** . + * - *************************** . + * . . + * . . + * . . + * <-------------- AND_WIDTH ---------> + * + * + * + * XOR_GAP + * <-------> + * . . + * . . + * . . + * . . + * * *********************** - + * * * ******** | + * * * **** | + * * * ** | + * * * ** | + * * * * + * -.............*.......*..........+ * OR_HEIGHT + * | * * * + * | * *. . *. | + * OR_Y_ORIGIN * *. . ** . | + * | * * . . ** . | + * | * * . . **** . | + * | * * . . ******** . | + * -........*.......*********************** . - + * . . + * <- OR_X_ORIGIN -> . + * . . + * . . + * <---------- OR_WIDTH --------------> + * + * + * + * NOTE: + * + * Both OR_HEIGHT and AND_HEIGHT are defined to be four. + * The rest of the parameters are under "user" control. + * + * The radius of the arcs in an OR gate are defined to be equal to the + * height of the OR gate (this seems to be an industry standard). Thus, + * The radius of all three arcs are defined to be four. + * + * Both the MIL standard and the ANSI / IEEE standard have slightly different + * ideas on these dimensions, so choose the dimensions you like best: + * + */ + +/* REQUIRED SIZES: */ + +AND_HEIGHT = 4; +OR_HEIGHT = 4; + +grid_pins : TRUE ; + +/* ANSI Dimensions: + * The ANSI dimensions have been commented out in favor of the MIL dimensions: + * + * ANSI_AND_HEIGHT = 26.0; + * SCALE = AND_HEIGHT / ANSI_AND_HEIGHT; + * + * AND_WIDTH = 32 * SCALE; + * OR_WIDTH = 32 * SCALE; + * INVERTER_HEIGHT = 22.5 * SCALE; + * XOR_GAP = 5 * SCALE; + * BUBBLE_DIAMETER = 4 * SCALE; + * DYNAMIC_HEIGHT = 4 * SCALE; + * DYNAMIC_WIDTH = 6 * SCALE; + * OFF_SHEET_HEIGHT = 8 * SCALE; Not specified by ANSI, + * this value from MIL + * + */ + + +/* MIL Dimensions: */ + +GRIDS_PER_INCH = 1 / INCHES_PER_GRID; +MIL_AND_HEIGHT = .8; +SCALE = AND_HEIGHT / MIL_AND_HEIGHT; + +AND_WIDTH = 1.00 * SCALE; +OR_WIDTH = 1.00 * SCALE; +OR_INTERNAL_WIDTH = 0.50 * GRIDS_PER_INCH; +INVERTER_HEIGHT = .70 * SCALE; +XOR_GAP = (2.0 / 13.0) * SCALE; /* Not specifed by MIL, this value from ANSI */ +BUBBLE_DIAMETER = .16 * SCALE; +DYNAMIC_HEIGHT = .15 * SCALE; +DYNAMIC_WIDTH = .30 * SCALE; +OFF_SHEET_HEIGHT = .25 * SCALE; + + +/* The following values are not specified by MIL or ANSI: */ + +/* Origins are defined as offset from the lower left corner */ +OR_X_ORIGIN = 3; +OR_Y_ORIGIN = 2; +AND_X_ORIGIN = 3; +AND_Y_ORIGIN = 2; +INVERTER_X_ORIGIN = 1; +INVERTER_Y_ORIGIN = INVERTER_HEIGHT / 2.0; + +EXTRA_WING_SPAN = .5; /* ON 3 + GATES, CONTROLS WING SIZE */ +GATE_GAP = 0; /* CONTROLS VERTICAL GAP ON STACKED GATES */ + +/* The following values are deduced from the above values: */ + +BUBBLE_RADIUS = BUBBLE_DIAMETER / 2.0; +DYNAMIC_RADIUS = DYNAMIC_HEIGHT / 2.0; + + + symbol(and_outline) { + AND_LEFT_X = - AND_X_ORIGIN; + AND_BOTTOM_Y = - AND_Y_ORIGIN; + + AND_TOP_Y = AND_BOTTOM_Y + AND_HEIGHT; + X_START_OF_ARC = AND_LEFT_X + AND_WIDTH - AND_HEIGHT / 2.0; + AND_MIDDLE_Y = AND_BOTTOM_Y + AND_HEIGHT / 2.0; + AND_RIGHT_X = AND_LEFT_X + AND_WIDTH; + + line(AND_LEFT_X, AND_TOP_Y, X_START_OF_ARC, AND_TOP_Y); + line(AND_LEFT_X, AND_BOTTOM_Y, X_START_OF_ARC, AND_BOTTOM_Y); + arc(X_START_OF_ARC, AND_TOP_Y, X_START_OF_ARC, AND_BOTTOM_Y, \ + X_START_OF_ARC, AND_MIDDLE_Y); + } + + + symbol(inverter_triangle) { + + /* The origins are defined to be the offset from the lower left corner */ + INVERTER_LEFT_X = - INVERTER_X_ORIGIN; + INVERTER_BOTTOM_Y = - INVERTER_Y_ORIGIN; + + INVERTER_RIGHT_X = INVERTER_LEFT_X + INVERTER_HEIGHT * SQRT(3) / 2.0; + INVERTER_TOP_Y = INVERTER_BOTTOM_Y + INVERTER_HEIGHT; + INVERTER_MIDDLE_Y = INVERTER_BOTTOM_Y + INVERTER_HEIGHT / 2.0; + + line(INVERTER_LEFT_X, INVERTER_TOP_Y, INVERTER_RIGHT_X, INVERTER_MIDDLE_Y); + line(INVERTER_RIGHT_X, INVERTER_MIDDLE_Y, \ + INVERTER_LEFT_X, INVERTER_BOTTOM_Y); + line(INVERTER_LEFT_X, INVERTER_BOTTOM_Y, INVERTER_LEFT_X, INVERTER_TOP_Y); + } + + symbol(solder_dot) { + line( -.25,-.25,.25,-.25); + line(.25,.25,.25,-.25); + line(.25,.25,-.25,.25); + line( -.25,.25,-.25,-.25); + line( -.25,-.25,.25,.25); + line(.25,-.25,-.25,.25); + } + +/****************************************************************************** +** +** New symbols added for SCLIB cells +** +******************************************************************************/ + + symbol(inv_x1) { + sub_symbol(inverter_triangle, 0,0,0); + + circle(INVERTER_RIGHT_X + BUBBLE_RADIUS, INVERTER_MIDDLE_Y, BUBBLE_RADIUS); + pin(nq, INVERTER_RIGHT_X + BUBBLE_DIAMETER, INVERTER_MIDDLE_Y, RIGHT); + pin(i, INVERTER_LEFT_X, INVERTER_MIDDLE_Y, LEFT); + } + + symbol(a2_x1) { + sub_symbol(and_outline, 0,0,0); + + line(AND_LEFT_X, AND_BOTTOM_Y, AND_LEFT_X, AND_TOP_Y); + + pin(i0, AND_LEFT_X, AND_BOTTOM_Y + 3, LEFT); + pin(i1, AND_LEFT_X, AND_BOTTOM_Y + 1, LEFT); + pin(q, AND_RIGHT_X, AND_MIDDLE_Y, RIGHT); + } + + symbol(na2_x1) { + sub_symbol(and_outline, 0,0,0); + + line(AND_LEFT_X, AND_BOTTOM_Y, AND_LEFT_X, AND_TOP_Y); + circle(AND_LEFT_X - BUBBLE_RADIUS, AND_BOTTOM_Y + 1, BUBBLE_RADIUS); + + pin(i0, AND_LEFT_X, AND_BOTTOM_Y + 3, LEFT); + pin(i1, (AND_LEFT_X - BUBBLE_DIAMETER), AND_BOTTOM_Y + 1, LEFT); + pin(nq, AND_RIGHT_X, AND_MIDDLE_Y, RIGHT); + } + + + OR_LEFT_X = - OR_X_ORIGIN; + OR_BOTTOM_Y = - OR_Y_ORIGIN; + + OR_TOP_Y = OR_BOTTOM_Y + OR_HEIGHT; + OR_LEFT_ARC_CENTER_X = OR_LEFT_X - sqrt(.75 * OR_HEIGHT * OR_HEIGHT); + OR_MIDDLE_Y = OR_BOTTOM_Y + OR_HEIGHT / 2.0; + OR_RIGHT_X = OR_LEFT_ARC_CENTER_X + OR_HEIGHT + OR_INTERNAL_WIDTH; + OR_RIGHT_ARCS_X_START = OR_RIGHT_X - sqrt(.75 * OR_HEIGHT * OR_HEIGHT); +/* + OR_WIDTH = OR_RIGHT_X - OR_LEFT_X; +*/ + symbol(left_side_of_or) { + arc(OR_LEFT_X,OR_TOP_Y,OR_LEFT_X, OR_BOTTOM_Y, \ + OR_LEFT_ARC_CENTER_X, OR_MIDDLE_Y); + } + + + symbol(or_outline) { + sub_symbol(left_side_of_or, 0,0,0); + + + arc(OR_RIGHT_ARCS_X_START, OR_TOP_Y, OR_RIGHT_X, OR_MIDDLE_Y, \ + OR_RIGHT_ARCS_X_START, OR_BOTTOM_Y); + arc(OR_RIGHT_X, OR_MIDDLE_Y, OR_RIGHT_ARCS_X_START, OR_BOTTOM_Y, \ + OR_RIGHT_ARCS_X_START, OR_TOP_Y); + + line(OR_LEFT_X, OR_TOP_Y, OR_RIGHT_ARCS_X_START, OR_TOP_Y); + line(OR_LEFT_X, OR_BOTTOM_Y, OR_RIGHT_ARCS_X_START, OR_BOTTOM_Y); + } + + OR_EVEN_LEFT_PIN_X = OR_LEFT_ARC_CENTER_X + sqrt((15.0 / 16.0) * \ + OR_HEIGHT * OR_HEIGHT); + OR_ODD_LEFT_PIN_X = OR_LEFT_ARC_CENTER_X + OR_HEIGHT; + + symbol(o2_x1) { + sub_symbol(or_outline,0,0,0); + + pin(i0, OR_EVEN_LEFT_PIN_X, OR_BOTTOM_Y + 3, LEFT); + pin(i1, OR_EVEN_LEFT_PIN_X, OR_BOTTOM_Y + 1, LEFT); + pin(q, OR_RIGHT_X, 0, RIGHT); + } + + /* height assumed to be radius of or arc */ + OR_NOT_CIRCLE_X = OR_LEFT_ARC_CENTER_X + sqrt(((OR_HEIGHT - BUBBLE_RADIUS) * \ + (OR_HEIGHT - BUBBLE_RADIUS)) - 1); + symbol(no2_x1) { + sub_symbol(or_outline, 0,0,0); + + circle(OR_NOT_CIRCLE_X, OR_BOTTOM_Y + 1, BUBBLE_RADIUS); + + pin(i0, OR_EVEN_LEFT_PIN_X, OR_BOTTOM_Y + 3, LEFT); + pin(i1, OR_NOT_CIRCLE_X - BUBBLE_RADIUS, OR_BOTTOM_Y + 1, LEFT); + pin(nq, OR_RIGHT_X, 0, RIGHT); + } + + + symbol(B2I) { + LEFT_INVERTER_ORIGIN_X = - INVERTER_X_ORIGIN - 2; + sub_symbol(inverter_triangle, LEFT_INVERTER_ORIGIN_X,0,0); + circle(LEFT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_RADIUS, \ + INVERTER_MIDDLE_Y, BUBBLE_RADIUS); + + RIGHT_INVERTER_ORIGIN_X = INVERTER_X_ORIGIN + 2; + sub_symbol(inverter_triangle, RIGHT_INVERTER_ORIGIN_X,0,0); + circle(RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_RADIUS, \ + INVERTER_MIDDLE_Y, BUBBLE_RADIUS); + + line(LEFT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER, \ + INVERTER_MIDDLE_Y, \ + RIGHT_INVERTER_ORIGIN_X + INVERTER_LEFT_X, INVERTER_MIDDLE_Y); + sub_symbol(solder_dot, INVERTER_X_ORIGIN,0,0); + line(INVERTER_X_ORIGIN, INVERTER_MIDDLE_Y, \ + INVERTER_X_ORIGIN, ceil(INVERTER_TOP_Y) + 1); + line(INVERTER_X_ORIGIN, ceil(INVERTER_TOP_Y) + 1, \ + RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER, \ + ceil(INVERTER_TOP_Y) + 1); + pin(Z1, RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER, \ + ceil(INVERTER_TOP_Y) + 1, RIGHT); + pin(Z2, RIGHT_INVERTER_ORIGIN_X + INVERTER_RIGHT_X + BUBBLE_DIAMETER, \ + INVERTER_MIDDLE_Y, RIGHT); + pin(A, LEFT_INVERTER_ORIGIN_X + INVERTER_LEFT_X, INVERTER_MIDDLE_Y, LEFT); + } + symbol(B2IP) { + sub_symbol(B2I, 0,0,0); + } + symbol(B3I) { + sub_symbol(B2I, 0,0,0); + } + symbol(B3IP) { + sub_symbol(B2I, 0,0,0); + } + symbol(mux2) { + MUX_WIDTH = 2.0; + MUX_X_ORIGIN = MUX_WIDTH / 2.0; + MUX_HEIGHT = 4.0; + MUX_Y_ORIGIN = MUX_HEIGHT / 2.0; + + MUX_LEFT = MUX_X_ORIGIN - (MUX_WIDTH / 2.0); + MUX_RIGHT = MUX_X_ORIGIN + (MUX_WIDTH / 2.0); + MUX_TOP = MUX_Y_ORIGIN + (MUX_HEIGHT / 2.0); + MUX_BOTTOM = MUX_Y_ORIGIN - (MUX_HEIGHT / 2.0); + line(MUX_LEFT, MUX_BOTTOM, MUX_RIGHT, MUX_BOTTOM); + line(MUX_LEFT, MUX_BOTTOM, MUX_LEFT, MUX_TOP); + line(MUX_RIGHT, MUX_TOP, MUX_RIGHT, MUX_BOTTOM); + line(MUX_RIGHT, MUX_TOP, MUX_LEFT, MUX_TOP); + pin(A, MUX_LEFT, MUX_Y_ORIGIN + 1, LEFT); + pin(B, MUX_LEFT, MUX_Y_ORIGIN - 1, LEFT); + pin(S, MUX_X_ORIGIN, MUX_BOTTOM , DOWN); + } + symbol(MUX21H) { + sub_symbol(mux2, 0,0,0); + pin(Z, MUX_RIGHT, MUX_Y_ORIGIN, RIGHT); + } + symbol(MUX21HP) { + sub_symbol(MUX21H, 0,0,0); + } + symbol(MUX21L) { + sub_symbol(mux2, 0,0,0); + pin(Z, MUX_RIGHT + BUBBLE_DIAMETER, MUX_Y_ORIGIN, RIGHT); + circle(MUX_RIGHT + BUBBLE_RADIUS, MUX_Y_ORIGIN, BUBBLE_RADIUS); + } + symbol(MUX21LP) { + sub_symbol(MUX21L, 0,0,0); + } + symbol(mux2sel) { + MUX_WIDTH = 3.0; + MUX_X_ORIGIN = MUX_WIDTH / 2.0; + MUX_HEIGHT = 4.0; + MUX_Y_ORIGIN = MUX_HEIGHT / 2.0; + + MUX_LEFT = MUX_X_ORIGIN - (MUX_WIDTH / 2.0); + MUX_RIGHT = MUX_X_ORIGIN + (MUX_WIDTH / 2.0); + MUX_TOP = MUX_Y_ORIGIN + (MUX_HEIGHT / 2.0); + MUX_BOTTOM = MUX_Y_ORIGIN - (MUX_HEIGHT / 2.0); + line(MUX_LEFT, MUX_BOTTOM, MUX_RIGHT, MUX_BOTTOM); + line(MUX_LEFT, MUX_BOTTOM, MUX_LEFT, MUX_TOP); + line(MUX_RIGHT, MUX_TOP, MUX_RIGHT, MUX_BOTTOM); + line(MUX_RIGHT, MUX_TOP, MUX_LEFT, MUX_TOP); + } + symbol(MUX21LA) { + sub_symbol(mux2sel, 0,0,0); + pin(A, MUX_LEFT, MUX_Y_ORIGIN + 1, LEFT); + pin(B, MUX_LEFT, MUX_Y_ORIGIN - 1, LEFT); + pin(SN, MUX_X_ORIGIN - 0.5, MUX_BOTTOM - BUBBLE_DIAMETER , DOWN); + circle(MUX_X_ORIGIN - 0.5, MUX_BOTTOM - BUBBLE_RADIUS, BUBBLE_RADIUS); + pin(S, MUX_X_ORIGIN + 0.5, MUX_BOTTOM , DOWN); + circle(MUX_RIGHT + BUBBLE_RADIUS, MUX_Y_ORIGIN, BUBBLE_RADIUS); + pin(Z, MUX_RIGHT + BUBBLE_DIAMETER, MUX_Y_ORIGIN, RIGHT); + } + symbol(MUX21LAP) { + sub_symbol(MUX21LA, 0,0,0); + } + symbol(MUX31L) { + sub_symbol(mux2sel, 0,0,0); + pin(D0, MUX_LEFT, MUX_Y_ORIGIN + 1, LEFT); + pin(D1, MUX_LEFT, MUX_Y_ORIGIN , LEFT); + pin(D2, MUX_LEFT, MUX_Y_ORIGIN - 1, LEFT); + pin(A, MUX_X_ORIGIN - 0.5, MUX_BOTTOM , DOWN); + pin(B, MUX_X_ORIGIN + 0.5, MUX_BOTTOM , DOWN); + circle(MUX_RIGHT + BUBBLE_RADIUS, MUX_Y_ORIGIN, BUBBLE_RADIUS); + pin(Z, MUX_RIGHT + BUBBLE_DIAMETER, MUX_Y_ORIGIN, RIGHT); + } + symbol(MUX31LP) { + sub_symbol(MUX31L, 0,0,0); + } + +FFBOX_WIDTH = 6.0; +FFBOX_X_ORIGIN = FFBOX_WIDTH / 2.0; +FFBOX_HEIGHT = 10.0; +FFBOX_Y_ORIGIN = FFBOX_HEIGHT / 2.0; + +FFBOX_LEFT = FFBOX_X_ORIGIN - (FFBOX_WIDTH / 2.0); +FFBOX_RIGHT = FFBOX_X_ORIGIN + (FFBOX_WIDTH / 2.0); + + symbol(ff_box) { + FFBOX_TOP = FFBOX_Y_ORIGIN + (FFBOX_HEIGHT / 2.0); + FFBOX_BOTTOM = FFBOX_Y_ORIGIN - (FFBOX_HEIGHT / 2.0); + line(FFBOX_LEFT, FFBOX_BOTTOM, FFBOX_RIGHT, FFBOX_BOTTOM); + line(FFBOX_LEFT, FFBOX_BOTTOM, FFBOX_LEFT, FFBOX_TOP); + line(FFBOX_RIGHT, FFBOX_TOP, FFBOX_RIGHT, FFBOX_BOTTOM); + line(FFBOX_RIGHT, FFBOX_TOP, FFBOX_LEFT, FFBOX_TOP); + pin(Q, FFBOX_RIGHT, FFBOX_Y_ORIGIN + 4 , RIGHT); + pin(QN, FFBOX_RIGHT + BUBBLE_DIAMETER, FFBOX_Y_ORIGIN - 4 , RIGHT); + circle(FFBOX_RIGHT + BUBBLE_RADIUS, FFBOX_Y_ORIGIN - 4, BUBBLE_RADIUS); + } + + symbol(FD1) { + sub_symbol(ff_box, 0,0,0); + pin(D, FFBOX_LEFT, FFBOX_Y_ORIGIN + 4, LEFT); + + CLOCK_Y = FFBOX_Y_ORIGIN - 4; + pin(CP, FFBOX_LEFT, CLOCK_Y , LEFT); + line(FFBOX_LEFT, CLOCK_Y - 0.5, FFBOX_LEFT + 1, CLOCK_Y); + line(FFBOX_LEFT, CLOCK_Y + 0.5, FFBOX_LEFT + 1, CLOCK_Y); + } + + symbol(FD1P) { + sub_symbol(FD1, 0,0,0); + } + symbol(FDW) { + sub_symbol(FD1, 0,0,0); + pin(CD, FFBOX_X_ORIGIN, FFBOX_BOTTOM - BUBBLE_DIAMETER, DOWN); + circle(FFBOX_X_ORIGIN,FFBOX_BOTTOM - BUBBLE_RADIUS, BUBBLE_RADIUS); + } + + symbol(FD4) { + sub_symbol(FD1, 0,0,0); + pin(SD, FFBOX_X_ORIGIN, FFBOX_TOP + BUBBLE_DIAMETER, UP); + circle(FFBOX_X_ORIGIN,FFBOX_TOP + BUBBLE_RADIUS, BUBBLE_RADIUS); + } + symbol(box_3x6) { + BOX_3X6_WIDTH = 3.0; + BOX_3X6_X_ORIGIN = BOX_3X6_WIDTH / 2.0; + BOX_3X6_HEIGHT = 6.0; + BOX_3X6_Y_ORIGIN = BOX_3X6_HEIGHT / 2.0; + + BOX_3X6_LEFT = BOX_3X6_X_ORIGIN - (BOX_3X6_WIDTH / 2.0); + BOX_3X6_RIGHT = BOX_3X6_X_ORIGIN + (BOX_3X6_WIDTH / 2.0); + BOX_3X6_TOP = BOX_3X6_Y_ORIGIN + (BOX_3X6_HEIGHT / 2.0); + BOX_3X6_BOTTOM = BOX_3X6_Y_ORIGIN - (BOX_3X6_HEIGHT / 2.0); + line(BOX_3X6_LEFT, BOX_3X6_BOTTOM, BOX_3X6_RIGHT, BOX_3X6_BOTTOM); + line(BOX_3X6_LEFT, BOX_3X6_BOTTOM, BOX_3X6_LEFT, BOX_3X6_TOP); + line(BOX_3X6_RIGHT, BOX_3X6_TOP, BOX_3X6_RIGHT, BOX_3X6_BOTTOM); + line(BOX_3X6_RIGHT, BOX_3X6_TOP, BOX_3X6_LEFT, BOX_3X6_TOP); + } +} + + + +/*****************************************************************************/ diff --git a/pdks/symbolic/sxlib/cells/sxlib_FTGS.vhd b/pdks/symbolic/sxlib/cells/sxlib_FTGS.vhd new file mode 100644 index 000000000..6bc6ab6fb --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sxlib_FTGS.vhd @@ -0,0 +1,12219 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_FTGS.vhd +-- FILE CONTENTS: Entity, Structural Architecture(FTGS), +-- and Configuration +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : FTGS, Timing_mesg(TRUE), Timing_xgen(FALSE), GLITCH_HANDLE +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a2_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_a2_x2_FTGS of a2_x2 is + for FTGS + end for; +end CFG_a2_x2_FTGS; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_a2_x4_FTGS of a2_x4 is + for FTGS + end for; +end CFG_a2_x4_FTGS; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a3_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_a3_x2_FTGS of a3_x2 is + for FTGS + end for; +end CFG_a3_x2_FTGS; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_a3_x4_FTGS of a3_x4 is + for FTGS + end for; +end CFG_a3_x4_FTGS; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a4_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000000000000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_a4_x2_FTGS of a4_x2 is + for FTGS + end for; +end CFG_a4_x2_FTGS; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000000000000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_a4_x4_FTGS of a4_x4 is + for FTGS + end for; +end CFG_a4_x4_FTGS; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of an12_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_an12_x1_FTGS of an12_x1 is + for FTGS + end for; +end CFG_an12_x1_FTGS; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of an12_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_an12_x4_FTGS of an12_x4 is + for FTGS + end for; +end CFG_an12_x4_FTGS; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao2o22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000011101110111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_ao2o22_x2_FTGS of ao2o22_x2 is + for FTGS + end for; +end CFG_ao2o22_x2_FTGS; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao2o22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000011101110111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_ao2o22_x4_FTGS of ao2o22_x4 is + for FTGS + end for; +end CFG_ao2o22_x4_FTGS; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00010101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_ao22_x2_FTGS of ao22_x2 is + for FTGS + end for; +end CFG_ao22_x2_FTGS; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00010101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_ao22_x4_FTGS of ao22_x4 is + for FTGS + end for; +end CFG_ao22_x4_FTGS; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of buf_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "01", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i q", + delay_param => + ( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_buf_x2_FTGS of buf_x2 is + for FTGS + end for; +end CFG_buf_x2_FTGS; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of buf_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "01", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i q", + delay_param => + ( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_buf_x4_FTGS of buf_x4 is + for FTGS + end for; +end CFG_buf_x4_FTGS; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of buf_x8 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "01", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i q", + delay_param => + ( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_buf_x8_FTGS of buf_x8 is + for FTGS + end for; +end CFG_buf_x8_FTGS; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x1_FTGS of inv_x1 is + for FTGS + end for; +end CFG_inv_x1_FTGS; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x2_FTGS of inv_x2 is + for FTGS + end for; +end CFG_inv_x2_FTGS; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x4_FTGS of inv_x4 is + for FTGS + end for; +end CFG_inv_x4_FTGS; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x8 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x8_FTGS of inv_x8 is + for FTGS + end for; +end CFG_inv_x8_FTGS; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx2_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00110101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 q", + delay_param => + ((tpdcmd_q_R, tpdcmd_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_mx2_x2_FTGS of mx2_x2 is + for FTGS + end for; +end CFG_mx2_x2_FTGS; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00110101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 q", + delay_param => + ((tpdcmd_q_R, tpdcmd_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_mx2_x4_FTGS of mx2_x4 is + for FTGS + end for; +end CFG_mx2_x4_FTGS; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx3_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00001111000011110101010100110011", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 q", + delay_param => + ((tpdcmd0_q_R, tpdcmd0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_q_R, tpdcmd1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_mx3_x2_FTGS of mx3_x2 is + for FTGS + end for; +end CFG_mx3_x2_FTGS; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00001111000011110101010100110011", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 q", + delay_param => + ((tpdcmd0_q_R, tpdcmd0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_q_R, tpdcmd1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_mx3_x4_FTGS of mx3_x4 is + for FTGS + end for; +end CFG_mx3_x4_FTGS; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_na2_x1_FTGS of na2_x1 is + for FTGS + end for; +end CFG_na2_x1_FTGS; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_na2_x4_FTGS of na2_x4 is + for FTGS + end for; +end CFG_na2_x4_FTGS; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na3_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_na3_x1_FTGS of na3_x1 is + for FTGS + end for; +end CFG_na3_x1_FTGS; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_na3_x4_FTGS of na3_x4 is + for FTGS + end for; +end CFG_na3_x4_FTGS; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na4_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111111111111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_na4_x1_FTGS of na4_x1 is + for FTGS + end for; +end CFG_na4_x1_FTGS; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111111111111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_na4_x4_FTGS of na4_x4 is + for FTGS + end for; +end CFG_na4_x4_FTGS; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao2o22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111100010001000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_nao2o22_x1_FTGS of nao2o22_x1 is + for FTGS + end for; +end CFG_nao2o22_x1_FTGS; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao2o22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111100010001000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_nao2o22_x4_FTGS of nao2o22_x4 is + for FTGS + end for; +end CFG_nao2o22_x4_FTGS; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11101010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nao22_x1_FTGS of nao22_x1 is + for FTGS + end for; +end CFG_nao22_x1_FTGS; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11101010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nao22_x4_FTGS of nao22_x4 is + for FTGS + end for; +end CFG_nao22_x4_FTGS; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11001010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 nq", + delay_param => + ((tpdcmd_nq_R, tpdcmd_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nmx2_x1_FTGS of nmx2_x1 is + for FTGS + end for; +end CFG_nmx2_x1_FTGS; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11001010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 nq", + delay_param => + ((tpdcmd_nq_R, tpdcmd_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nmx2_x4_FTGS of nmx2_x4 is + for FTGS + end for; +end CFG_nmx2_x4_FTGS; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx3_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11110000111100001010101011001100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 nq", + delay_param => + ((tpdcmd0_nq_R, tpdcmd0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_nq_R, tpdcmd1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_nmx3_x1_FTGS of nmx3_x1 is + for FTGS + end for; +end CFG_nmx3_x1_FTGS; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11110000111100001010101011001100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 nq", + delay_param => + ((tpdcmd0_nq_R, tpdcmd0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_nq_R, tpdcmd1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_nmx3_x4_FTGS of nmx3_x4 is + for FTGS + end for; +end CFG_nmx3_x4_FTGS; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_no2_x1_FTGS of no2_x1 is + for FTGS + end for; +end CFG_no2_x1_FTGS; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_no2_x4_FTGS of no2_x4 is + for FTGS + end for; +end CFG_no2_x4_FTGS; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no3_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_no3_x1_FTGS of no3_x1 is + for FTGS + end for; +end CFG_no3_x1_FTGS; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_no3_x4_FTGS of no3_x4 is + for FTGS + end for; +end CFG_no3_x4_FTGS; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no4_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1000000000000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_no4_x1_FTGS of no4_x1 is + for FTGS + end for; +end CFG_no4_x1_FTGS; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1000000000000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_no4_x4_FTGS of no4_x4 is + for FTGS + end for; +end CFG_no4_x4_FTGS; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a2a24_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "10101000101010001010100000000000", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i2 i3 i4 i5 i0 i1 i6 i7 nq", + delay_param => + ((tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_nq_R, tpdi7_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(6), + Input(7) => connect(7), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a2a24_x1_FTGS of noa2a2a2a24_x1 is + for FTGS + end for; +end CFG_noa2a2a2a24_x1_FTGS; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a2a24_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "10101000101010001010100000000000", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i2 i3 i4 i5 i0 i1 i6 i7 nq", + delay_param => + ((tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_nq_R, tpdi7_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(6), + Input(7) => connect(7), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a2a24_x4_FTGS of noa2a2a2a24_x4 is + for FTGS + end for; +end CFG_noa2a2a2a24_x4_FTGS; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a23_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "10101000", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i0 i1 i4 i5 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(2), + Input(5) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a23_x1_FTGS of noa2a2a23_x1 is + for FTGS + end for; +end CFG_noa2a2a23_x1_FTGS; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a23_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "10101000", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i0 i1 i4 i5 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(2), + Input(5) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a23_x4_FTGS of noa2a2a23_x4 is + for FTGS + end for; +end CFG_noa2a2a23_x4_FTGS; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1110111011100000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a22_x1_FTGS of noa2a22_x1 is + for FTGS + end for; +end CFG_noa2a22_x1_FTGS; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1110111011100000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a22_x4_FTGS of noa2a22_x4 is + for FTGS + end for; +end CFG_noa2a22_x4_FTGS; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2ao222_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11101010111010101110101000000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_noa2ao222_x1_FTGS of noa2ao222_x1 is + for FTGS + end for; +end CFG_noa2ao222_x1_FTGS; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2ao222_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11101010111010101110101000000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_noa2ao222_x4_FTGS of noa2ao222_x4 is + for FTGS + end for; +end CFG_noa2ao222_x4_FTGS; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa3ao322_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "0001010101010101" & + "1010101010101000", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 nq", + delay_param => + ((tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa3ao322_x1_FTGS of noa3ao322_x1 is + for FTGS + end for; +end CFG_noa3ao322_x1_FTGS; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa3ao322_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "0001010101010101" & + "1010101010101000", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 nq", + delay_param => + ((tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa3ao322_x4_FTGS of noa3ao322_x4 is + for FTGS + end for; +end CFG_noa3ao322_x4_FTGS; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10101000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa22_x1_FTGS of noa22_x1 is + for FTGS + end for; +end CFG_noa22_x1_FTGS; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10101000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa22_x4_FTGS of noa22_x4 is + for FTGS + end for; +end CFG_noa22_x4_FTGS; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nts_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z1Z0", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd nq", + delay_param => + ((tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_nq_R, tpdcmd_nq_F, tpdcmd_nq_LZ, tpdcmd_nq_R, tpdcmd_nq_HZ, tpdcmd_nq_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_nts_x1_FTGS of nts_x1 is + for FTGS + end for; +end CFG_nts_x1_FTGS; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nts_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z1Z0", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd nq", + delay_param => + ((tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_nq_R, tpdcmd_nq_F, tpdcmd_nq_LZ, tpdcmd_nq_R, tpdcmd_nq_HZ, tpdcmd_nq_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_nts_x2_FTGS of nts_x2 is + for FTGS + end for; +end CFG_nts_x2_FTGS; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nxr2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_nxr2_x1_FTGS of nxr2_x1 is + for FTGS + end for; +end CFG_nxr2_x1_FTGS; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nxr2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_nxr2_x4_FTGS of nxr2_x4 is + for FTGS + end for; +end CFG_nxr2_x4_FTGS; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o2_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_o2_x2_FTGS of o2_x2 is + for FTGS + end for; +end CFG_o2_x2_FTGS; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_o2_x4_FTGS of o2_x4 is + for FTGS + end for; +end CFG_o2_x4_FTGS; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o3_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_o3_x2_FTGS of o3_x2 is + for FTGS + end for; +end CFG_o3_x2_FTGS; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_o3_x4_FTGS of o3_x4 is + for FTGS + end for; +end CFG_o3_x4_FTGS; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o4_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0111111111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_o4_x2_FTGS of o4_x2 is + for FTGS + end for; +end CFG_o4_x2_FTGS; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0111111111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_o4_x4_FTGS of o4_x4 is + for FTGS + end for; +end CFG_o4_x4_FTGS; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a2a24_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "01010111010101110101011111111111", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i4 i5 i6 i7 i0 i1 i2 i3 q", + delay_param => + ((tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_q_R, tpdi7_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(4), + Input(1) => connect(5), + Input(2) => connect(6), + Input(3) => connect(7), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Input(7) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a2a24_x2_FTGS of oa2a2a2a24_x2 is + for FTGS + end for; +end CFG_oa2a2a2a24_x2_FTGS; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a2a24_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "01010111010101110101011111111111", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i4 i5 i6 i7 i0 i1 i2 i3 q", + delay_param => + ((tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_q_R, tpdi7_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(4), + Input(1) => connect(5), + Input(2) => connect(6), + Input(3) => connect(7), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Input(7) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a2a24_x4_FTGS of oa2a2a2a24_x4 is + for FTGS + end for; +end CFG_oa2a2a2a24_x4_FTGS; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a23_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "01010111", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i2 i3 i4 i5 i0 i1 q", + delay_param => + ((tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a23_x2_FTGS of oa2a2a23_x2 is + for FTGS + end for; +end CFG_oa2a2a23_x2_FTGS; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a23_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "01010111", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i2 i3 i4 i5 i0 i1 q", + delay_param => + ((tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a23_x4_FTGS of oa2a2a23_x4 is + for FTGS + end for; +end CFG_oa2a2a23_x4_FTGS; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0001000100011111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a22_x2_FTGS of oa2a22_x2 is + for FTGS + end for; +end CFG_oa2a22_x2_FTGS; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0001000100011111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a22_x4_FTGS of oa2a22_x4 is + for FTGS + end for; +end CFG_oa2a22_x4_FTGS; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2ao222_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00010101000101010001010111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_oa2ao222_x2_FTGS of oa2ao222_x2 is + for FTGS + end for; +end CFG_oa2ao222_x2_FTGS; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2ao222_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00010101000101010001010111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_oa2ao222_x4_FTGS of oa2ao222_x4 is + for FTGS + end for; +end CFG_oa2ao222_x4_FTGS; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa3ao322_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "0001010101010101" & + "0101010101010111", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 q", + delay_param => + ((tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa3ao322_x2_FTGS of oa3ao322_x2 is + for FTGS + end for; +end CFG_oa3ao322_x2_FTGS; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa3ao322_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "0001010101010101" & + "0101010101010111", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 q", + delay_param => + ((tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa3ao322_x4_FTGS of oa3ao322_x4 is + for FTGS + end for; +end CFG_oa3ao322_x4_FTGS; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01010111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa22_x2_FTGS of oa22_x2 is + for FTGS + end for; +end CFG_oa22_x2_FTGS; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01010111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa22_x4_FTGS of oa22_x4 is + for FTGS + end for; +end CFG_oa22_x4_FTGS; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of on12_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_on12_x1_FTGS of on12_x1 is + for FTGS + end for; +end CFG_on12_x1_FTGS; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of on12_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_on12_x4_FTGS of on12_x4 is + for FTGS + end for; +end CFG_on12_x4_FTGS; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity one_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + q : out STD_LOGIC := '1'); +end one_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of one_x0 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + + + +begin + + -- Netlist + q <= '1'; + +end FTGS; + +configuration CFG_one_x0_FTGS of one_x0 is + for FTGS + end for; +end CFG_one_x0_FTGS; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff1_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff1_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of sff1_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_i: constant is + "U3/constraint_param(1).Check_time"; + attribute PROPAGATE_VALUE of tsui_ck: constant is + "U3/constraint_param(0).Check_time"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is + "U3/delay_param(0)(TRAN_10), " & + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is + "U3/delay_param(0)(TRAN_01), " & + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdck_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdck_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdck_R, twdck_F, twdck_R, twdck_R, twdck_F, twdck_F)) + port map( Input => ck, Output => connect(1)); + + -- Netlist + U3 : SEQGEN + generic map( + N_enable => 0, + N_clock => 1, + N_clear => 0, + N_preset => 0, + N_data => 1, + N_cond_signal => 0, + lut_enable => "", + lut_clock => "01", + lut_clear => "", + lut_preset => "", + lut_data => "01", + TT_size_data => nil_integer_vector, + Node_Index_data => nil_integer_vector, + lut_next => "NN01NN01", + pin_names => "ck i q", + delay_param => + ((tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + constraint_param => + ((1, 0, setup_rising_ff, tsui_ck), + (0, 1, hold_rising_ff, thck_i)), + InMapZ => "XX", + Q_feedback => FALSE, + Enable_feedback => FALSE, + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + Constraint_mesg => Timing_mesg, + Constraint_xgen => Timing_xgen, + strn => strn_X01) + port map( Input(0) => connect(1), + Input(1) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_sff1_x4_FTGS of sff1_x4 is + for FTGS + end for; +end CFG_sff1_x4_FTGS; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of sff2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_cmd: constant is + "U5/constraint_param(5).Check_time"; + attribute PROPAGATE_VALUE of tsucmd_ck: constant is + "U5/constraint_param(4).Check_time"; + attribute PROPAGATE_VALUE of thck_i1: constant is + "U5/constraint_param(3).Check_time"; + attribute PROPAGATE_VALUE of tsui1_ck: constant is + "U5/constraint_param(2).Check_time"; + attribute PROPAGATE_VALUE of thck_i0: constant is + "U5/constraint_param(1).Check_time"; + attribute PROPAGATE_VALUE of tsui0_ck: constant is + "U5/constraint_param(0).Check_time"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is + "U5/delay_param(0)(TRAN_10), " & + "U5/delay_param(1)(TRAN_10), U5/delay_param(2)(TRAN_10), " & + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is + "U5/delay_param(0)(TRAN_01), " & + "U5/delay_param(1)(TRAN_01), U5/delay_param(2)(TRAN_01), " & + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdck_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdck_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdck_R, twdck_F, twdck_R, twdck_R, twdck_F, twdck_F)) + port map( Input => ck, Output => connect(3)); + + -- Netlist + U5 : SEQGEN + generic map( + N_enable => 0, + N_clock => 1, + N_clear => 0, + N_preset => 0, + N_data => 3, + N_cond_signal => 0, + lut_enable => "", + lut_clock => "01", + lut_clear => "", + lut_preset => "", + lut_data => "00011011", + TT_size_data => nil_integer_vector, + Node_Index_data => nil_integer_vector, + lut_next => "NN01NN01", + pin_names => "ck i0 i1 cmd q", + delay_param => + ((tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + constraint_param => + ((1, 0, setup_rising_ff, tsui0_ck), + (0, 1, hold_rising_ff, thck_i0), + (2, 0, setup_rising_ff, tsui1_ck), + (0, 2, hold_rising_ff, thck_i1), + (3, 0, setup_rising_ff, tsucmd_ck), + (0, 3, hold_rising_ff, thck_cmd)), + InMapZ => "XXXX", + Q_feedback => FALSE, + Enable_feedback => FALSE, + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + Constraint_mesg => Timing_mesg, + Constraint_xgen => Timing_xgen, + strn => strn_X01) + port map( Input(0) => connect(3), + Input(1) => connect(0), + Input(2) => connect(1), + Input(3) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_sff2_x4_FTGS of sff2_x4 is + for FTGS + end for; +end CFG_sff2_x4_FTGS; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ts_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z0Z1", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd q", + delay_param => + ((tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_q_R, tpdcmd_q_F, tpdcmd_q_LZ, tpdcmd_q_R, tpdcmd_q_HZ, tpdcmd_q_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_ts_x4_FTGS of ts_x4 is + for FTGS + end for; +end CFG_ts_x4_FTGS; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ts_x8 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z0Z1", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd q", + delay_param => + ((tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_q_R, tpdcmd_q_F, tpdcmd_q_LZ, tpdcmd_q_R, tpdcmd_q_HZ, tpdcmd_q_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_ts_x8_FTGS of ts_x8 is + for FTGS + end for; +end CFG_ts_x8_FTGS; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of xr2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_xr2_x1_FTGS of xr2_x1 is + for FTGS + end for; +end CFG_xr2_x1_FTGS; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of xr2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_xr2_x4_FTGS of xr2_x4 is + for FTGS + end for; +end CFG_xr2_x4_FTGS; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity zero_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + nq : out STD_LOGIC := '0'); +end zero_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of zero_x0 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + + + +begin + + -- Netlist + nq <= '0'; + +end FTGS; + +configuration CFG_zero_x0_FTGS of zero_x0 is + for FTGS + end for; +end CFG_zero_x0_FTGS; + + +---- end of library ---- diff --git a/pdks/symbolic/sxlib/cells/sxlib_FTSM.vhd b/pdks/symbolic/sxlib/cells/sxlib_FTSM.vhd new file mode 100644 index 000000000..f19acf591 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sxlib_FTSM.vhd @@ -0,0 +1,11368 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_FTSM.vhd +-- FILE CONTENTS: Entity, Structural Architecture(FTSM), +-- and Configuration +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : FTSM, Timing_mesg(TRUE) +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a2_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_a2_x2_FTSM of a2_x2 is + for FTSM + end for; +end CFG_a2_x2_FTSM; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_a2_x4_FTSM of a2_x4 is + for FTSM + end for; +end CFG_a2_x4_FTSM; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a3_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_a3_x2_FTSM of a3_x2 is + for FTSM + end for; +end CFG_a3_x2_FTSM; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_a3_x4_FTSM of a3_x4 is + for FTSM + end for; +end CFG_a3_x4_FTSM; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a4_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND4MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), I3 => + prop_q(3), Y => q); + + +end FTSM; + +configuration CFG_a4_x2_FTSM of a4_x2 is + for FTSM + end for; +end CFG_a4_x2_FTSM; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND4MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), I3 => + prop_q(3), Y => q); + + +end FTSM; + +configuration CFG_a4_x4_FTSM of a4_x4 is + for FTSM + end for; +end CFG_a4_x4_FTSM; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of an12_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(1), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_an12_x1_FTSM of an12_x1 is + for FTSM + end for; +end CFG_an12_x1_FTSM; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of an12_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(1), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_an12_x4_FTSM of an12_x4 is + for FTSM + end for; +end CFG_an12_x4_FTSM; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao2o22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao2o22_x2_FTSM of ao2o22_x2 is + for FTSM + end for; +end CFG_ao2o22_x2_FTSM; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao2o22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao2o22_x4_FTSM of ao2o22_x4 is + for FTSM + end for; +end CFG_ao2o22_x4_FTSM; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND2MAC + port map( I0 => prop_q(2), I1 => n1, Y => q); + + U8 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao22_x2_FTSM of ao22_x2 is + for FTSM + end for; +end CFG_ao22_x2_FTSM; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND2MAC + port map( I0 => prop_q(2), I1 => n1, Y => q); + + U8 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao22_x4_FTSM of ao22_x4 is + for FTSM + end for; +end CFG_ao22_x4_FTSM; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of buf_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Concurrent assignments + U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(0), Output => q); + + +end FTSM; + +configuration CFG_buf_x2_FTSM of buf_x2 is + for FTSM + end for; +end CFG_buf_x2_FTSM; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of buf_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Concurrent assignments + U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(0), Output => q); + + +end FTSM; + +configuration CFG_buf_x4_FTSM of buf_x4 is + for FTSM + end for; +end CFG_buf_x4_FTSM; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of buf_x8 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Concurrent assignments + U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(0), Output => q); + + +end FTSM; + +configuration CFG_buf_x8_FTSM of buf_x8 is + for FTSM + end for; +end CFG_buf_x8_FTSM; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x1_FTSM of inv_x1 is + for FTSM + end for; +end CFG_inv_x1_FTSM; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x2_FTSM of inv_x2 is + for FTSM + end for; +end CFG_inv_x2_FTSM; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x4_FTSM of inv_x4 is + for FTSM + end for; +end CFG_inv_x4_FTSM; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x8 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x8_FTSM of inv_x8 is + for FTSM + end for; +end CFG_inv_x8_FTSM; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx2_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_q(1), I1 => prop_q(2), S0 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_mx2_x2_FTSM of mx2_x2 is + for FTSM + end for; +end CFG_mx2_x2_FTSM; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_q(1), I1 => prop_q(2), S0 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_mx2_x4_FTSM of mx2_x4 is + for FTSM + end for; +end CFG_mx2_x4_FTSM; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx3_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_q_R, tHL => tpdcmd0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_q_R, tHL => tpdcmd1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_q(4), I1 => prop_q(3), S0 => prop_q(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_q(2), I1 => n1, S0 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_mx3_x2_FTSM of mx3_x2 is + for FTSM + end for; +end CFG_mx3_x2_FTSM; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_q_R, tHL => tpdcmd0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_q_R, tHL => tpdcmd1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_q(4), I1 => prop_q(3), S0 => prop_q(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_q(2), I1 => n1, S0 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_mx3_x4_FTSM of mx3_x4 is + for FTSM + end for; +end CFG_mx3_x4_FTSM; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_na2_x1_FTSM of na2_x1 is + for FTSM + end for; +end CFG_na2_x1_FTSM; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_na2_x4_FTSM of na2_x4 is + for FTSM + end for; +end CFG_na2_x4_FTSM; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na3_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND3MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => + nq); + + +end FTSM; + +configuration CFG_na3_x1_FTSM of na3_x1 is + for FTSM + end for; +end CFG_na3_x1_FTSM; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND3MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => + nq); + + +end FTSM; + +configuration CFG_na3_x4_FTSM of na3_x4 is + for FTSM + end for; +end CFG_na3_x4_FTSM; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na4_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_na4_x1_FTSM of na4_x1 is + for FTSM + end for; +end CFG_na4_x1_FTSM; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_na4_x4_FTSM of na4_x4 is + for FTSM + end for; +end CFG_na4_x4_FTSM; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao2o22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : OR2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao2o22_x1_FTSM of nao2o22_x1 is + for FTSM + end for; +end CFG_nao2o22_x1_FTSM; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao2o22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : OR2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao2o22_x4_FTSM of nao2o22_x4 is + for FTSM + end for; +end CFG_nao2o22_x4_FTSM; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao22_x1_FTSM of nao22_x1 is + for FTSM + end for; +end CFG_nao22_x1_FTSM; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao22_x4_FTSM of nao22_x4 is + for FTSM + end for; +end CFG_nao22_x4_FTSM; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_F, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), S0 => prop_nq(0), Y => + n1); + + U8 : INVMAC + port map( I0 => n1, Y => nq); + + +end FTSM; + +configuration CFG_nmx2_x1_FTSM of nmx2_x1 is + for FTSM + end for; +end CFG_nmx2_x1_FTSM; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_F, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), S0 => prop_nq(0), Y => + n1); + + U8 : INVMAC + port map( I0 => n1, Y => nq); + + +end FTSM; + +configuration CFG_nmx2_x4_FTSM of nmx2_x4 is + for FTSM + end for; +end CFG_nmx2_x4_FTSM; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx3_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_nq_F, tHL => tpdcmd0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_nq_F, tHL => tpdcmd1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(3), S0 => prop_nq(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_nq(2), I1 => n1, S0 => prop_nq(0), Y => n2); + + U13 : INVMAC + port map( I0 => n2, Y => nq); + + +end FTSM; + +configuration CFG_nmx3_x1_FTSM of nmx3_x1 is + for FTSM + end for; +end CFG_nmx3_x1_FTSM; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_nq_F, tHL => tpdcmd0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_nq_F, tHL => tpdcmd1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(3), S0 => prop_nq(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_nq(2), I1 => n1, S0 => prop_nq(0), Y => n2); + + U13 : INVMAC + port map( I0 => n2, Y => nq); + + +end FTSM; + +configuration CFG_nmx3_x4_FTSM of nmx3_x4 is + for FTSM + end for; +end CFG_nmx3_x4_FTSM; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NOR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_no2_x1_FTSM of no2_x1 is + for FTSM + end for; +end CFG_no2_x1_FTSM; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NOR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_no2_x4_FTSM of no2_x4 is + for FTSM + end for; +end CFG_no2_x4_FTSM; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no3_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR3MAC + port map( I0 => prop_nq(2), I1 => prop_nq(0), I2 => prop_nq(1), Y => + nq); + + +end FTSM; + +configuration CFG_no3_x1_FTSM of no3_x1 is + for FTSM + end for; +end CFG_no3_x1_FTSM; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR3MAC + port map( I0 => prop_nq(2), I1 => prop_nq(0), I2 => prop_nq(1), Y => + nq); + + +end FTSM; + +configuration CFG_no3_x4_FTSM of no3_x4 is + for FTSM + end for; +end CFG_no3_x4_FTSM; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no4_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NOR4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_no4_x1_FTSM of no4_x1 is + for FTSM + end for; +end CFG_no4_x1_FTSM; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NOR4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_no4_x4_FTSM of no4_x4 is + for FTSM + end for; +end CFG_no4_x4_FTSM; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a2a24_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_nq_F, tHL => tpdi7_nq_R) + port map( Input => connect(7), Output => prop_nq(7)); + + -- Netlist + U17 : AND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U18 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_nq(6), I1 => prop_nq(7), Y => n1); + + +end FTSM; + +configuration CFG_noa2a2a2a24_x1_FTSM of noa2a2a2a24_x1 is + for FTSM + end for; +end CFG_noa2a2a2a24_x1_FTSM; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a2a24_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_nq_F, tHL => tpdi7_nq_R) + port map( Input => connect(7), Output => prop_nq(7)); + + -- Netlist + U17 : AND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U18 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_nq(6), I1 => prop_nq(7), Y => n1); + + +end FTSM; + +configuration CFG_noa2a2a2a24_x4_FTSM of noa2a2a2a24_x4 is + for FTSM + end for; +end CFG_noa2a2a2a24_x4_FTSM; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a23_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + -- Netlist + U13 : AND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U14 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n3); + + +end FTSM; + +configuration CFG_noa2a2a23_x1_FTSM of noa2a2a23_x1 is + for FTSM + end for; +end CFG_noa2a2a23_x1_FTSM; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a23_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + -- Netlist + U13 : AND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U14 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n3); + + +end FTSM; + +configuration CFG_noa2a2a23_x4_FTSM of noa2a2a23_x4 is + for FTSM + end for; +end CFG_noa2a2a23_x4_FTSM; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2a22_x1_FTSM of noa2a22_x1 is + for FTSM + end for; +end CFG_noa2a22_x1_FTSM; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2a22_x4_FTSM of noa2a22_x4 is + for FTSM + end for; +end CFG_noa2a22_x4_FTSM; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2ao222_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U12 : OR2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U13 : NAND2MAC + port map( I0 => prop_nq(4), I1 => n3, Y => n2); + + U14 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2ao222_x1_FTSM of noa2ao222_x1 is + for FTSM + end for; +end CFG_noa2ao222_x1_FTSM; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2ao222_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U12 : OR2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U13 : NAND2MAC + port map( I0 => prop_nq(4), I1 => n3, Y => n2); + + U14 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2ao222_x4_FTSM of noa2ao222_x4 is + for FTSM + end for; +end CFG_noa2ao222_x4_FTSM; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa3ao322_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + -- Netlist + U15 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U16 : NAND3MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => + n2); + + U17 : OR3MAC + port map( I0 => prop_nq(3), I1 => prop_nq(4), I2 => prop_nq(5), Y => + n3); + + U18 : NAND2MAC + port map( I0 => prop_nq(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_noa3ao322_x1_FTSM of noa3ao322_x1 is + for FTSM + end for; +end CFG_noa3ao322_x1_FTSM; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa3ao322_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + -- Netlist + U15 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U16 : NAND3MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => + n2); + + U17 : OR3MAC + port map( I0 => prop_nq(3), I1 => prop_nq(4), I2 => prop_nq(5), Y => + n3); + + U18 : NAND2MAC + port map( I0 => prop_nq(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_noa3ao322_x4_FTSM of noa3ao322_x4 is + for FTSM + end for; +end CFG_noa3ao322_x4_FTSM; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : AND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa22_x1_FTSM of noa22_x1 is + for FTSM + end for; +end CFG_noa22_x1_FTSM; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : AND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa22_x4_FTSM of noa22_x4 is + for FTSM + end for; +end CFG_noa22_x4_FTSM; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nts_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_R, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_nq_F, tHL => tpdi_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : INV3SHEMAC + port map( I0 => prop_nq(1), OE => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nts_x1_FTSM of nts_x1 is + for FTSM + end for; +end CFG_nts_x1_FTSM; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nts_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_R, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_nq_F, tHL => tpdi_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : INV3SHEMAC + port map( I0 => prop_nq(1), OE => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nts_x2_FTSM of nts_x2 is + for FTSM + end for; +end CFG_nts_x2_FTSM; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nxr2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NXOR2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nxr2_x1_FTSM of nxr2_x1 is + for FTSM + end for; +end CFG_nxr2_x1_FTSM; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nxr2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NXOR2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nxr2_x4_FTSM of nxr2_x4 is + for FTSM + end for; +end CFG_nxr2_x4_FTSM; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o2_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_o2_x2_FTSM of o2_x2 is + for FTSM + end for; +end CFG_o2_x2_FTSM; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_o2_x4_FTSM of o2_x4 is + for FTSM + end for; +end CFG_o2_x4_FTSM; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o3_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR3MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), Y => + q); + + +end FTSM; + +configuration CFG_o3_x2_FTSM of o3_x2 is + for FTSM + end for; +end CFG_o3_x2_FTSM; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR3MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), Y => + q); + + +end FTSM; + +configuration CFG_o3_x4_FTSM of o3_x4 is + for FTSM + end for; +end CFG_o3_x4_FTSM; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o4_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : OR4MAC + port map( I0 => prop_q(2), I1 => prop_q(3), I2 => prop_q(0), I3 => + prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_o4_x2_FTSM of o4_x2 is + for FTSM + end for; +end CFG_o4_x2_FTSM; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : OR4MAC + port map( I0 => prop_q(2), I1 => prop_q(3), I2 => prop_q(0), I3 => + prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_o4_x4_FTSM of o4_x4 is + for FTSM + end for; +end CFG_o4_x4_FTSM; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a2a24_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_q_R, tHL => tpdi7_q_F) + port map( Input => connect(7), Output => prop_q(7)); + + -- Netlist + U17 : NAND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => prop_q(7), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a2a2a24_x2_FTSM of oa2a2a2a24_x2 is + for FTSM + end for; +end CFG_oa2a2a2a24_x2_FTSM; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a2a24_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_q_R, tHL => tpdi7_q_F) + port map( Input => connect(7), Output => prop_q(7)); + + -- Netlist + U17 : NAND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => prop_q(7), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a2a2a24_x4_FTSM of oa2a2a2a24_x4 is + for FTSM + end for; +end CFG_oa2a2a2a24_x4_FTSM; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a23_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + -- Netlist + U13 : NAND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U14 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n3); + + +end FTSM; + +configuration CFG_oa2a2a23_x2_FTSM of oa2a2a23_x2 is + for FTSM + end for; +end CFG_oa2a2a23_x2_FTSM; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a23_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + -- Netlist + U13 : NAND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U14 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n3); + + +end FTSM; + +configuration CFG_oa2a2a23_x4_FTSM of oa2a2a23_x4 is + for FTSM + end for; +end CFG_oa2a2a23_x4_FTSM; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a22_x2_FTSM of oa2a22_x2 is + for FTSM + end for; +end CFG_oa2a22_x2_FTSM; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a22_x4_FTSM of oa2a22_x4 is + for FTSM + end for; +end CFG_oa2a22_x4_FTSM; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2ao222_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U12 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n3); + + U13 : NAND2MAC + port map( I0 => prop_q(4), I1 => n3, Y => n2); + + U14 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2ao222_x2_FTSM of oa2ao222_x2 is + for FTSM + end for; +end CFG_oa2ao222_x2_FTSM; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2ao222_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U12 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n3); + + U13 : NAND2MAC + port map( I0 => prop_q(4), I1 => n3, Y => n2); + + U14 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2ao222_x4_FTSM of oa2ao222_x4 is + for FTSM + end for; +end CFG_oa2ao222_x4_FTSM; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa3ao322_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + -- Netlist + U15 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U16 : OR3MAC + port map( I0 => prop_q(3), I1 => prop_q(4), I2 => prop_q(5), Y => + n3); + + U17 : NAND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + n2); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_oa3ao322_x2_FTSM of oa3ao322_x2 is + for FTSM + end for; +end CFG_oa3ao322_x2_FTSM; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa3ao322_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + -- Netlist + U15 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U16 : OR3MAC + port map( I0 => prop_q(3), I1 => prop_q(4), I2 => prop_q(5), Y => + n3); + + U17 : NAND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + n2); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_oa3ao322_x4_FTSM of oa3ao322_x4 is + for FTSM + end for; +end CFG_oa3ao322_x4_FTSM; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR2MAC + port map( I0 => n1, I1 => prop_q(2), Y => q); + + U8 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa22_x2_FTSM of oa22_x2 is + for FTSM + end for; +end CFG_oa22_x2_FTSM; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR2MAC + port map( I0 => n1, I1 => prop_q(2), Y => q); + + U8 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa22_x4_FTSM of oa22_x4 is + for FTSM + end for; +end CFG_oa22_x4_FTSM; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of on12_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_q(0), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_on12_x1_FTSM of on12_x1 is + for FTSM + end for; +end CFG_on12_x1_FTSM; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of on12_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_q(0), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_on12_x4_FTSM of on12_x4 is + for FTSM + end for; +end CFG_on12_x4_FTSM; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity one_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + q : out STD_LOGIC := '1'); +end one_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of one_x0 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + + +begin + + -- Netlist + q <= '1'; + +end FTSM; + +configuration CFG_one_x0_FTSM of one_x0 is + for FTSM + end for; +end CFG_one_x0_FTSM; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff1_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff1_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of sff1_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_i: constant is "FEC/F2/tHold"; + attribute PROPAGATE_VALUE of tsui_ck: constant is "FEC/F1/tSetup"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is "U3/U1/tHL"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is "U3/U1/tLH"; + attribute PROPAGATE_VALUE of twdck_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdck_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdck_R, tHL => twdck_F) + port map( Input => ck, Output => connect(1)); + + -- Netlist + U3 : DFFLMAC + generic map( tpdY_R => tpdck_q_R, tpdY_F => tpdck_q_F ) + port map( D => connect(0), CLK => connect(1), CLR => n1, Q => q); + + n1 <= '1'; + + -- Forbidden Events + FEC : if Timing_mesg generate + + F1 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsui_ck) + port map( Data(1) => connect(0), Clock => connect(1)); + + F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_i) + port map( Data(1) => connect(0), Clock => connect(1)); + + end generate FEC; + +end FTSM; + +configuration CFG_sff1_x4_FTSM of sff1_x4 is + for FTSM + end for; +end CFG_sff1_x4_FTSM; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of sff2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_cmd: constant is "FEC/F6/tHold"; + attribute PROPAGATE_VALUE of tsucmd_ck: constant is "FEC/F5/tSetup"; + attribute PROPAGATE_VALUE of thck_i1: constant is "FEC/F4/tHold"; + attribute PROPAGATE_VALUE of tsui1_ck: constant is "FEC/F3/tSetup"; + attribute PROPAGATE_VALUE of thck_i0: constant is "FEC/F2/tHold"; + attribute PROPAGATE_VALUE of tsui0_ck: constant is "FEC/F1/tSetup"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is "U6/U1/tHL"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is "U6/U1/tLH"; + attribute PROPAGATE_VALUE of twdck_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdck_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdck_R, tHL => twdck_F) + port map( Input => ck, Output => connect(3)); + + -- Netlist + U5 : MUX2MAC + port map( I0 => connect(0), I1 => connect(1), S0 => connect(2), Y => + n1); + + U6 : DFFLMAC + generic map( tpdY_R => tpdck_q_R, tpdY_F => tpdck_q_F ) + port map( D => n1, CLK => connect(3), CLR => n2, Q => q); + + n2 <= '1'; + + -- Forbidden Events + FEC : if Timing_mesg generate + + F1 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsui0_ck) + port map( Data(1) => connect(0), Clock => connect(3)); + + F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_i0) + port map( Data(1) => connect(0), Clock => connect(3)); + + F3 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsui1_ck) + port map( Data(1) => connect(1), Clock => connect(3)); + + F4 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_i1) + port map( Data(1) => connect(1), Clock => connect(3)); + + F5 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsucmd_ck) + port map( Data(1) => connect(2), Clock => connect(3)); + + F6 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_cmd) + port map( Data(1) => connect(2), Clock => connect(3)); + + end generate FEC; + +end FTSM; + +configuration CFG_sff2_x4_FTSM of sff2_x4 is + for FTSM + end for; +end CFG_sff2_x4_FTSM; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ts_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : BUF3SHEMAC + port map( I0 => prop_q(1), OE => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_ts_x4_FTSM of ts_x4 is + for FTSM + end for; +end CFG_ts_x4_FTSM; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ts_x8 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : BUF3SHEMAC + port map( I0 => prop_q(1), OE => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_ts_x8_FTSM of ts_x8 is + for FTSM + end for; +end CFG_ts_x8_FTSM; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of xr2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_F, tHL => tpdi1_q_R) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : XOR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_xr2_x1_FTSM of xr2_x1 is + for FTSM + end for; +end CFG_xr2_x1_FTSM; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of xr2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_F, tHL => tpdi1_q_R) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : XOR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_xr2_x4_FTSM of xr2_x4 is + for FTSM + end for; +end CFG_xr2_x4_FTSM; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity zero_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + nq : out STD_LOGIC := '0'); +end zero_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of zero_x0 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + + +begin + + -- Netlist + nq <= '0'; + +end FTSM; + +configuration CFG_zero_x0_FTSM of zero_x0 is + for FTSM + end for; +end CFG_zero_x0_FTSM; + + +---- end of library ---- diff --git a/pdks/symbolic/sxlib/cells/sxlib_UDSM.vhd b/pdks/symbolic/sxlib/cells/sxlib_UDSM.vhd new file mode 100644 index 000000000..e54da28c2 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sxlib_UDSM.vhd @@ -0,0 +1,7175 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_UDSM.vhd +-- FILE CONTENTS: Entity, Structural Architecture(UDSM), +-- and Configuration +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : UDSM +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a2_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => q); + + +end UDSM; + +configuration CFG_a2_x2_UDSM of a2_x2 is + for UDSM + end for; +end CFG_a2_x2_UDSM; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => q); + + +end UDSM; + +configuration CFG_a2_x4_UDSM of a2_x4 is + for UDSM + end for; +end CFG_a2_x4_UDSM; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a3_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => q); + + +end UDSM; + +configuration CFG_a3_x2_UDSM of a3_x2 is + for UDSM + end for; +end CFG_a3_x2_UDSM; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => q); + + +end UDSM; + +configuration CFG_a3_x4_UDSM of a3_x4 is + for UDSM + end for; +end CFG_a3_x4_UDSM; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a4_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => q); + + +end UDSM; + +configuration CFG_a4_x2_UDSM of a4_x2 is + for UDSM + end for; +end CFG_a4_x2_UDSM; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => q); + + +end UDSM; + +configuration CFG_a4_x4_UDSM of a4_x4 is + for UDSM + end for; +end CFG_a4_x4_UDSM; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of an12_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i0, Y => n1); + + +end UDSM; + +configuration CFG_an12_x1_UDSM of an12_x1 is + for UDSM + end for; +end CFG_an12_x1_UDSM; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of an12_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i0, Y => n1); + + +end UDSM; + +configuration CFG_an12_x4_UDSM of an12_x4 is + for UDSM + end for; +end CFG_an12_x4_UDSM; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao2o22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n2); + + U3 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao2o22_x2_UDSM of ao2o22_x2 is + for UDSM + end for; +end CFG_ao2o22_x2_UDSM; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao2o22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n2); + + U3 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao2o22_x4_UDSM of ao2o22_x4 is + for UDSM + end for; +end CFG_ao2o22_x4_UDSM; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => q); + + U2 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao22_x2_UDSM of ao22_x2 is + for UDSM + end for; +end CFG_ao22_x2_UDSM; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => q); + + U2 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao22_x4_UDSM of ao22_x4 is + for UDSM + end for; +end CFG_ao22_x4_UDSM; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of buf_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Concurrent assignments + U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => 1 ns, tHL => 1 ns) + port map( Input => i, Output => q); + + +end UDSM; + +configuration CFG_buf_x2_UDSM of buf_x2 is + for UDSM + end for; +end CFG_buf_x2_UDSM; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of buf_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Concurrent assignments + U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => 1 ns, tHL => 1 ns) + port map( Input => i, Output => q); + + +end UDSM; + +configuration CFG_buf_x4_UDSM of buf_x4 is + for UDSM + end for; +end CFG_buf_x4_UDSM; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of buf_x8 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Concurrent assignments + U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => 1 ns, tHL => 1 ns) + port map( Input => i, Output => q); + + +end UDSM; + +configuration CFG_buf_x8_UDSM of buf_x8 is + for UDSM + end for; +end CFG_buf_x8_UDSM; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x1_UDSM of inv_x1 is + for UDSM + end for; +end CFG_inv_x1_UDSM; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x2_UDSM of inv_x2 is + for UDSM + end for; +end CFG_inv_x2_UDSM; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x4_UDSM of inv_x4 is + for UDSM + end for; +end CFG_inv_x4_UDSM; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x8 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x8_UDSM of inv_x8 is + for UDSM + end for; +end CFG_inv_x8_UDSM; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx2_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, S0 => cmd, Y => q); + + +end UDSM; + +configuration CFG_mx2_x2_UDSM of mx2_x2 is + for UDSM + end for; +end CFG_mx2_x2_UDSM; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, S0 => cmd, Y => q); + + +end UDSM; + +configuration CFG_mx2_x4_UDSM of mx2_x4 is + for UDSM + end for; +end CFG_mx2_x4_UDSM; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx3_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => q); + + +end UDSM; + +configuration CFG_mx3_x2_UDSM of mx3_x2 is + for UDSM + end for; +end CFG_mx3_x2_UDSM; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => q); + + +end UDSM; + +configuration CFG_mx3_x4_UDSM of mx3_x4 is + for UDSM + end for; +end CFG_mx3_x4_UDSM; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_na2_x1_UDSM of na2_x1 is + for UDSM + end for; +end CFG_na2_x1_UDSM; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_na2_x4_UDSM of na2_x4 is + for UDSM + end for; +end CFG_na2_x4_UDSM; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na3_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => nq); + + +end UDSM; + +configuration CFG_na3_x1_UDSM of na3_x1 is + for UDSM + end for; +end CFG_na3_x1_UDSM; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => nq); + + +end UDSM; + +configuration CFG_na3_x4_UDSM of na3_x4 is + for UDSM + end for; +end CFG_na3_x4_UDSM; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na4_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_na4_x1_UDSM of na4_x1 is + for UDSM + end for; +end CFG_na4_x1_UDSM; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_na4_x4_UDSM of na4_x4 is + for UDSM + end for; +end CFG_na4_x4_UDSM; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao2o22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : OR2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao2o22_x1_UDSM of nao2o22_x1 is + for UDSM + end for; +end CFG_nao2o22_x1_UDSM; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao2o22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : OR2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao2o22_x4_UDSM of nao2o22_x4 is + for UDSM + end for; +end CFG_nao2o22_x4_UDSM; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao22_x1_UDSM of nao22_x1 is + for UDSM + end for; +end CFG_nao22_x1_UDSM; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao22_x4_UDSM of nao22_x4 is + for UDSM + end for; +end CFG_nao22_x4_UDSM; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); + + U2 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, Y => nq); + + +end UDSM; + +configuration CFG_nmx2_x1_UDSM of nmx2_x1 is + for UDSM + end for; +end CFG_nmx2_x1_UDSM; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); + + U2 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, Y => nq); + + +end UDSM; + +configuration CFG_nmx2_x4_UDSM of nmx2_x4 is + for UDSM + end for; +end CFG_nmx2_x4_UDSM; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx3_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => n2); + + U3 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n2, Y => nq); + + +end UDSM; + +configuration CFG_nmx3_x1_UDSM of nmx3_x1 is + for UDSM + end for; +end CFG_nmx3_x1_UDSM; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => n2); + + U3 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n2, Y => nq); + + +end UDSM; + +configuration CFG_nmx3_x4_UDSM of nmx3_x4 is + for UDSM + end for; +end CFG_nmx3_x4_UDSM; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no2_x1_UDSM of no2_x1 is + for UDSM + end for; +end CFG_no2_x1_UDSM; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no2_x4_UDSM of no2_x4 is + for UDSM + end for; +end CFG_no2_x4_UDSM; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no3_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i0, I2 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no3_x1_UDSM of no3_x1 is + for UDSM + end for; +end CFG_no3_x1_UDSM; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i0, I2 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no3_x4_UDSM of no3_x4 is + for UDSM + end for; +end CFG_no3_x4_UDSM; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no4_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_no4_x1_UDSM of no4_x1 is + for UDSM + end for; +end CFG_no4_x1_UDSM; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_no4_x4_UDSM of no4_x4 is + for UDSM + end for; +end CFG_no4_x4_UDSM; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a2a24_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U2 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n4); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U5 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n1); + + +end UDSM; + +configuration CFG_noa2a2a2a24_x1_UDSM of noa2a2a2a24_x1 is + for UDSM + end for; +end CFG_noa2a2a2a24_x1_UDSM; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a2a24_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U2 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n4); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U5 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n1); + + +end UDSM; + +configuration CFG_noa2a2a2a24_x4_UDSM of noa2a2a2a24_x4 is + for UDSM + end for; +end CFG_noa2a2a2a24_x4_UDSM; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a23_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + +end UDSM; + +configuration CFG_noa2a2a23_x1_UDSM of noa2a2a23_x1 is + for UDSM + end for; +end CFG_noa2a2a23_x1_UDSM; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a23_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + +end UDSM; + +configuration CFG_noa2a2a23_x4_UDSM of noa2a2a23_x4 is + for UDSM + end for; +end CFG_noa2a2a23_x4_UDSM; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2a22_x1_UDSM of noa2a22_x1 is + for UDSM + end for; +end CFG_noa2a22_x1_UDSM; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2a22_x4_UDSM of noa2a22_x4 is + for UDSM + end for; +end CFG_noa2a22_x4_UDSM; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2ao222_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : OR2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U3 : NAND2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2ao222_x1_UDSM of noa2ao222_x1 is + for UDSM + end for; +end CFG_noa2ao222_x1_UDSM; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2ao222_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : OR2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U3 : NAND2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2ao222_x4_UDSM of noa2ao222_x4 is + for UDSM + end for; +end CFG_noa2ao222_x4_UDSM; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa3ao322_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : NAND3MAC + port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); + + U3 : OR3MAC + port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); + + U4 : NAND2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_noa3ao322_x1_UDSM of noa3ao322_x1 is + for UDSM + end for; +end CFG_noa3ao322_x1_UDSM; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa3ao322_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : NAND3MAC + port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); + + U3 : OR3MAC + port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); + + U4 : NAND2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_noa3ao322_x4_UDSM of noa3ao322_x4 is + for UDSM + end for; +end CFG_noa3ao322_x4_UDSM; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa22_x1_UDSM of noa22_x1 is + for UDSM + end for; +end CFG_noa22_x1_UDSM; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa22_x4_UDSM of noa22_x4 is + for UDSM + end for; +end CFG_noa22_x4_UDSM; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nts_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INV3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => nq); + + +end UDSM; + +configuration CFG_nts_x1_UDSM of nts_x1 is + for UDSM + end for; +end CFG_nts_x1_UDSM; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nts_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INV3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => nq); + + +end UDSM; + +configuration CFG_nts_x2_UDSM of nts_x2 is + for UDSM + end for; +end CFG_nts_x2_UDSM; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nxr2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NXOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => nq); + + +end UDSM; + +configuration CFG_nxr2_x1_UDSM of nxr2_x1 is + for UDSM + end for; +end CFG_nxr2_x1_UDSM; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nxr2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NXOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => nq); + + +end UDSM; + +configuration CFG_nxr2_x4_UDSM of nxr2_x4 is + for UDSM + end for; +end CFG_nxr2_x4_UDSM; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o2_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_o2_x2_UDSM of o2_x2 is + for UDSM + end for; +end CFG_o2_x2_UDSM; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_o2_x4_UDSM of o2_x4 is + for UDSM + end for; +end CFG_o2_x4_UDSM; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o3_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, Y => q); + + +end UDSM; + +configuration CFG_o3_x2_UDSM of o3_x2 is + for UDSM + end for; +end CFG_o3_x2_UDSM; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, Y => q); + + +end UDSM; + +configuration CFG_o3_x4_UDSM of o3_x4 is + for UDSM + end for; +end CFG_o3_x4_UDSM; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o4_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i3, I2 => i0, I3 => i1, Y => q); + + +end UDSM; + +configuration CFG_o4_x2_UDSM of o4_x2 is + for UDSM + end for; +end CFG_o4_x2_UDSM; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i3, I2 => i0, I3 => i1, Y => q); + + +end UDSM; + +configuration CFG_o4_x4_UDSM of o4_x4 is + for UDSM + end for; +end CFG_o4_x4_UDSM; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a2a24_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U2 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n4); + + U3 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + U4 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U5 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a2a2a24_x2_UDSM of oa2a2a2a24_x2 is + for UDSM + end for; +end CFG_oa2a2a2a24_x2_UDSM; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a2a24_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U2 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n4); + + U3 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + U4 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U5 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a2a2a24_x4_UDSM of oa2a2a2a24_x4 is + for UDSM + end for; +end CFG_oa2a2a2a24_x4_UDSM; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a23_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U2 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n1); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n3); + + +end UDSM; + +configuration CFG_oa2a2a23_x2_UDSM of oa2a2a23_x2 is + for UDSM + end for; +end CFG_oa2a2a23_x2_UDSM; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a23_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U2 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n1); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n3); + + +end UDSM; + +configuration CFG_oa2a2a23_x4_UDSM of oa2a2a23_x4 is + for UDSM + end for; +end CFG_oa2a2a23_x4_UDSM; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a22_x2_UDSM of oa2a22_x2 is + for UDSM + end for; +end CFG_oa2a22_x2_UDSM; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a22_x4_UDSM of oa2a22_x4 is + for UDSM + end for; +end CFG_oa2a22_x4_UDSM; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2ao222_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n3); + + U3 : NAND2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2ao222_x2_UDSM of oa2ao222_x2 is + for UDSM + end for; +end CFG_oa2ao222_x2_UDSM; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2ao222_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n3); + + U3 : NAND2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2ao222_x4_UDSM of oa2ao222_x4 is + for UDSM + end for; +end CFG_oa2ao222_x4_UDSM; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa3ao322_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR3MAC + port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); + + U3 : NAND3MAC + port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); + + U4 : NAND2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_oa3ao322_x2_UDSM of oa3ao322_x2 is + for UDSM + end for; +end CFG_oa3ao322_x2_UDSM; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa3ao322_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR3MAC + port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); + + U3 : NAND3MAC + port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); + + U4 : NAND2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_oa3ao322_x4_UDSM of oa3ao322_x4 is + for UDSM + end for; +end CFG_oa3ao322_x4_UDSM; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => i2, Y => q); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa22_x2_UDSM of oa22_x2 is + for UDSM + end for; +end CFG_oa22_x2_UDSM; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => i2, Y => q); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa22_x4_UDSM of oa22_x4 is + for UDSM + end for; +end CFG_oa22_x4_UDSM; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of on12_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i1, Y => n1); + + +end UDSM; + +configuration CFG_on12_x1_UDSM of on12_x1 is + for UDSM + end for; +end CFG_on12_x1_UDSM; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of on12_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i1, Y => n1); + + +end UDSM; + +configuration CFG_on12_x4_UDSM of on12_x4 is + for UDSM + end for; +end CFG_on12_x4_UDSM; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity one_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + q : out STD_LOGIC := '1'); +end one_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of one_x0 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Netlist + q <= '1'; + +end UDSM; + +configuration CFG_one_x0_UDSM of one_x0 is + for UDSM + end for; +end CFG_one_x0_UDSM; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff1_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff1_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of sff1_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : DFFLMAC + generic map( tpdY_R => 2 ns, tpdY_F => 2 ns) + port map( D => i, CLK => ck, CLR => n1, Q => q); + + n1 <= '1'; + +end UDSM; + +configuration CFG_sff1_x4_UDSM of sff1_x4 is + for UDSM + end for; +end CFG_sff1_x4_UDSM; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of sff2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); + + U2 : DFFLMAC + generic map( tpdY_R => 2 ns, tpdY_F => 2 ns) + port map( D => n1, CLK => ck, CLR => n2, Q => q); + + n2 <= '1'; + +end UDSM; + +configuration CFG_sff2_x4_UDSM of sff2_x4 is + for UDSM + end for; +end CFG_sff2_x4_UDSM; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ts_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : BUF3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => q); + + +end UDSM; + +configuration CFG_ts_x4_UDSM of ts_x4 is + for UDSM + end for; +end CFG_ts_x4_UDSM; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ts_x8 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : BUF3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => q); + + +end UDSM; + +configuration CFG_ts_x8_UDSM of ts_x8 is + for UDSM + end for; +end CFG_ts_x8_UDSM; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of xr2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : XOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_xr2_x1_UDSM of xr2_x1 is + for UDSM + end for; +end CFG_xr2_x1_UDSM; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of xr2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : XOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_xr2_x4_UDSM of xr2_x4 is + for UDSM + end for; +end CFG_xr2_x4_UDSM; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity zero_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + nq : out STD_LOGIC := '0'); +end zero_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of zero_x0 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Netlist + nq <= '0'; + +end UDSM; + +configuration CFG_zero_x0_UDSM of zero_x0 is + for UDSM + end for; +end CFG_zero_x0_UDSM; + + +---- end of library ---- diff --git a/pdks/symbolic/sxlib/cells/sxlib_VITAL.vhd b/pdks/symbolic/sxlib/cells/sxlib_VITAL.vhd new file mode 100644 index 000000000..c6203b0b6 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sxlib_VITAL.vhd @@ -0,0 +1,8941 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_VITAL.vhd +-- FILE CONTENTS: Entity, Structural Architecture(VITAL), +-- and Configuration +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : VITAL, TimingChecksOn(TRUE), XGenerationOn(FALSE), TimingMessage(TRUE), OnDetect +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a2_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.261 ns, 0.388 ns); + tpd_i1_q : VitalDelayType01 := (0.203 ns, 0.434 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a2_x2 : entity is TRUE; +end a2_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a2_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a2_x2_VITAL of a2_x2 is + for VITAL + end for; +end CFG_a2_x2_VITAL; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.338 ns, 0.476 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a2_x4 : entity is TRUE; +end a2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a2_x4_VITAL of a2_x4 is + for VITAL + end for; +end CFG_a2_x4_VITAL; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a3_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.395 ns, 0.435 ns); + tpd_i1_q : VitalDelayType01 := (0.353 ns, 0.479 ns); + tpd_i2_q : VitalDelayType01 := (0.290 ns, 0.521 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a3_x2 : entity is TRUE; +end a3_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a3_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a3_x2_VITAL of a3_x2 is + for VITAL + end for; +end CFG_a3_x2_VITAL; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.478 ns, 0.514 ns); + tpd_i1_q : VitalDelayType01 := (0.428 ns, 0.554 ns); + tpd_i2_q : VitalDelayType01 := (0.356 ns, 0.592 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a3_x4 : entity is TRUE; +end a3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a3_x4_VITAL of a3_x4 is + for VITAL + end for; +end CFG_a3_x4_VITAL; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a4_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.374 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.441 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.482 ns, 0.498 ns); + tpd_i3_q : VitalDelayType01 := (0.506 ns, 0.455 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a4_x2 : entity is TRUE; +end a4_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a4_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd) AND (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a4_x2_VITAL of a4_x2 is + for VITAL + end for; +end CFG_a4_x2_VITAL; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.505 ns, 0.650 ns); + tpd_i1_q : VitalDelayType01 := (0.578 ns, 0.614 ns); + tpd_i2_q : VitalDelayType01 := (0.627 ns, 0.576 ns); + tpd_i3_q : VitalDelayType01 := (0.661 ns, 0.538 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a4_x4 : entity is TRUE; +end a4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd) AND (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a4_x4_VITAL of a4_x4 is + for VITAL + end for; +end CFG_a4_x4_VITAL; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity an12_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.200 ns, 0.168 ns); + tpd_i1_q : VitalDelayType01 := (0.285 ns, 0.405 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of an12_x1 : entity is TRUE; +end an12_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of an12_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_an12_x1_VITAL of an12_x1 is + for VITAL + end for; +end CFG_an12_x1_VITAL; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity an12_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.461 ns, 0.471 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of an12_x4 : entity is TRUE; +end an12_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of an12_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_an12_x4_VITAL of an12_x4 is + for VITAL + end for; +end CFG_an12_x4_VITAL; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao2o22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.572 ns, 0.451 ns); + tpd_i1_q : VitalDelayType01 := (0.508 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.432 ns, 0.627 ns); + tpd_i3_q : VitalDelayType01 := (0.488 ns, 0.526 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao2o22_x2 : entity is TRUE; +end ao2o22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao2o22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) OR (i2_ipd)) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao2o22_x2_VITAL of ao2o22_x2 is + for VITAL + end for; +end CFG_ao2o22_x2_VITAL; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao2o22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.696 ns, 0.569 ns); + tpd_i1_q : VitalDelayType01 := (0.637 ns, 0.666 ns); + tpd_i2_q : VitalDelayType01 := (0.554 ns, 0.744 ns); + tpd_i3_q : VitalDelayType01 := (0.606 ns, 0.639 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao2o22_x4 : entity is TRUE; +end ao2o22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao2o22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) OR (i2_ipd)) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao2o22_x4_VITAL of ao2o22_x4 is + for VITAL + end for; +end CFG_ao2o22_x4_VITAL; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.558 ns, 0.447 ns); + tpd_i1_q : VitalDelayType01 := (0.493 ns, 0.526 ns); + tpd_i2_q : VitalDelayType01 := (0.420 ns, 0.425 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao22_x2 : entity is TRUE; +end ao22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao22_x2_VITAL of ao22_x2 is + for VITAL + end for; +end CFG_ao22_x2_VITAL; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.674 ns, 0.552 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i2_q : VitalDelayType01 := (0.526 ns, 0.505 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao22_x4 : entity is TRUE; +end ao22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao22_x4_VITAL of ao22_x4 is + for VITAL + end for; +end CFG_ao22_x4_VITAL; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity buf_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_q : VitalDelayType01 := (0.409 ns, 0.391 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of buf_x2 : entity is TRUE; +end buf_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of buf_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := TO_X01(i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_buf_x2_VITAL of buf_x2 is + for VITAL + end for; +end CFG_buf_x2_VITAL; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity buf_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_q : VitalDelayType01 := (0.379 ns, 0.409 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of buf_x4 : entity is TRUE; +end buf_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of buf_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := TO_X01(i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_buf_x4_VITAL of buf_x4 is + for VITAL + end for; +end CFG_buf_x4_VITAL; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity buf_x8 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_q : VitalDelayType01 := (0.343 ns, 0.396 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of buf_x8 : entity is TRUE; +end buf_x8; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of buf_x8 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := TO_X01(i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_buf_x8_VITAL of buf_x8 is + for VITAL + end for; +end CFG_buf_x8_VITAL; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.101 ns, 0.139 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x1 : entity is TRUE; +end inv_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x1_VITAL of inv_x1 is + for VITAL + end for; +end CFG_inv_x1_VITAL; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.069 ns, 0.163 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x2 : entity is TRUE; +end inv_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x2_VITAL of inv_x2 is + for VITAL + end for; +end CFG_inv_x2_VITAL; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.071 ns, 0.143 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x4 : entity is TRUE; +end inv_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x4_VITAL of inv_x4 is + for VITAL + end for; +end CFG_inv_x4_VITAL; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x8 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.086 ns, 0.133 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x8 : entity is TRUE; +end inv_x8; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x8 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x8_VITAL of inv_x8 is + for VITAL + end for; +end CFG_inv_x8_VITAL; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx2_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01 := (0.484 ns, 0.522 ns); + tpd_i0_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tpd_i1_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx2_x2 : entity is TRUE; +end mx2_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx2_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_q, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx2_x2_VITAL of mx2_x2 is + for VITAL + end for; +end CFG_mx2_x2_VITAL; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i0_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tpd_i1_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx2_x4 : entity is TRUE; +end mx2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_q, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx2_x4_VITAL of mx2_x4 is + for VITAL + end for; +end CFG_mx2_x4_VITAL; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx3_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_q : VitalDelayType01 := (0.573 ns, 0.680 ns); + tpd_cmd1_q : VitalDelayType01 := (0.664 ns, 0.817 ns); + tpd_i0_q : VitalDelayType01 := (0.538 ns, 0.658 ns); + tpd_i1_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tpd_i2_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx3_x2 : entity is TRUE; +end mx3_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx3_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_q, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_q, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx3_x2_VITAL of mx3_x2 is + for VITAL + end for; +end CFG_mx3_x2_VITAL; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_q : VitalDelayType01 := (0.683 ns, 0.779 ns); + tpd_cmd1_q : VitalDelayType01 := (0.792 ns, 0.967 ns); + tpd_i0_q : VitalDelayType01 := (0.640 ns, 0.774 ns); + tpd_i1_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tpd_i2_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx3_x4 : entity is TRUE; +end mx3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_q, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_q, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx3_x4_VITAL of mx3_x4 is + for VITAL + end for; +end CFG_mx3_x4_VITAL; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.059 ns, 0.288 ns); + tpd_i1_nq : VitalDelayType01 := (0.111 ns, 0.234 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na2_x1 : entity is TRUE; +end na2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na2_x1_VITAL of na2_x1 is + for VITAL + end for; +end CFG_na2_x1_VITAL; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.412 ns, 0.552 ns); + tpd_i1_nq : VitalDelayType01 := (0.353 ns, 0.601 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na2_x4 : entity is TRUE; +end na2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na2_x4_VITAL of na2_x4 is + for VITAL + end for; +end CFG_na2_x4_VITAL; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na3_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.119 ns, 0.363 ns); + tpd_i1_nq : VitalDelayType01 := (0.171 ns, 0.316 ns); + tpd_i2_nq : VitalDelayType01 := (0.193 ns, 0.265 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na3_x1 : entity is TRUE; +end na3_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na3_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na3_x1_VITAL of na3_x1 is + for VITAL + end for; +end CFG_na3_x1_VITAL; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.556 ns, 0.601 ns); + tpd_i1_nq : VitalDelayType01 := (0.460 ns, 0.691 ns); + tpd_i2_nq : VitalDelayType01 := (0.519 ns, 0.647 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na3_x4 : entity is TRUE; +end na3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na3_x4_VITAL of na3_x4 is + for VITAL + end for; +end CFG_na3_x4_VITAL; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na4_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.179 ns, 0.438 ns); + tpd_i1_nq : VitalDelayType01 := (0.237 ns, 0.395 ns); + tpd_i2_nq : VitalDelayType01 := (0.269 ns, 0.350 ns); + tpd_i3_nq : VitalDelayType01 := (0.282 ns, 0.302 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na4_x1 : entity is TRUE; +end na4_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na4_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)) OR ((NOT i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na4_x1_VITAL of na4_x1 is + for VITAL + end for; +end CFG_na4_x1_VITAL; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.578 ns, 0.771 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.731 ns); + tpd_i2_nq : VitalDelayType01 := (0.681 ns, 0.689 ns); + tpd_i3_nq : VitalDelayType01 := (0.703 ns, 0.644 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na4_x4 : entity is TRUE; +end na4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)) OR ((NOT i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na4_x4_VITAL of na4_x4 is + for VITAL + end for; +end CFG_na4_x4_VITAL; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao2o22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.237 ns, 0.307 ns); + tpd_i3_nq : VitalDelayType01 := (0.174 ns, 0.382 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao2o22_x1 : entity is TRUE; +end nao2o22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao2o22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) AND ((NOT i2_ipd))) OR (((NOT i1_ipd)) AND ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao2o22_x1_VITAL of nao2o22_x1 is + for VITAL + end for; +end CFG_nao2o22_x1_VITAL; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao2o22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.734 ns, 0.644 ns); + tpd_i1_nq : VitalDelayType01 := (0.666 ns, 0.717 ns); + tpd_i2_nq : VitalDelayType01 := (0.664 ns, 0.721 ns); + tpd_i3_nq : VitalDelayType01 := (0.607 ns, 0.807 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao2o22_x4 : entity is TRUE; +end nao2o22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao2o22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) AND ((NOT i2_ipd))) OR (((NOT i1_ipd)) AND ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao2o22_x4_VITAL of nao2o22_x4 is + for VITAL + end for; +end CFG_nao2o22_x4_VITAL; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.165 ns, 0.238 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao22_x1 : entity is TRUE; +end nao22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) OR (((NOT i1_ipd)) AND ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao22_x1_VITAL of nao22_x1 is + for VITAL + end for; +end CFG_nao22_x1_VITAL; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.732 ns, 0.650 ns); + tpd_i1_nq : VitalDelayType01 := (0.664 ns, 0.723 ns); + tpd_i2_nq : VitalDelayType01 := (0.596 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao22_x4 : entity is TRUE; +end nao22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) OR (((NOT i1_ipd)) AND ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao22_x4_VITAL of nao22_x4 is + for VITAL + end for; +end CFG_nao22_x4_VITAL; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i0_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tpd_i1_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx2_x1 : entity is TRUE; +end nmx2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_nq, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx2_x1_VITAL of nmx2_x1 is + for VITAL + end for; +end CFG_nmx2_x1_VITAL; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01 := (0.632 ns, 0.708 ns); + tpd_i0_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tpd_i1_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx2_x4 : entity is TRUE; +end nmx2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_nq, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx2_x4_VITAL of nmx2_x4 is + for VITAL + end for; +end CFG_nmx2_x4_VITAL; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx3_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_nq : VitalDelayType01 := (0.356 ns, 0.495 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.414 ns, 0.566 ns); + tpd_i0_nq : VitalDelayType01 := (0.315 ns, 0.441 ns); + tpd_i1_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tpd_i2_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx3_x1 : entity is TRUE; +end nmx3_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx3_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_nq, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_nq, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx3_x1_VITAL of nmx3_x1 is + for VITAL + end for; +end CFG_nmx3_x1_VITAL; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_nq : VitalDelayType01 := (0.790 ns, 0.936 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.866 ns, 1.048 ns); + tpd_i0_nq : VitalDelayType01 := (0.748 ns, 0.900 ns); + tpd_i1_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tpd_i2_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx3_x4 : entity is TRUE; +end nmx3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_nq, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_nq, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx3_x4_VITAL of nmx3_x4 is + for VITAL + end for; +end CFG_nmx3_x4_VITAL; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.298 ns, 0.121 ns); + tpd_i1_nq : VitalDelayType01 := (0.193 ns, 0.161 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no2_x1 : entity is TRUE; +end no2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no2_x1_VITAL of no2_x1 is + for VITAL + end for; +end CFG_no2_x1_VITAL; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.618 ns, 0.447 ns); + tpd_i1_nq : VitalDelayType01 := (0.522 ns, 0.504 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no2_x4 : entity is TRUE; +end no2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no2_x4_VITAL of no2_x4 is + for VITAL + end for; +end CFG_no2_x4_VITAL; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no3_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.318 ns, 0.246 ns); + tpd_i1_nq : VitalDelayType01 := (0.215 ns, 0.243 ns); + tpd_i2_nq : VitalDelayType01 := (0.407 ns, 0.192 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no3_x1 : entity is TRUE; +end no3_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no3_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no3_x1_VITAL of no3_x1 is + for VITAL + end for; +end CFG_no3_x1_VITAL; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.722 ns, 0.561 ns); + tpd_i1_nq : VitalDelayType01 := (0.638 ns, 0.623 ns); + tpd_i2_nq : VitalDelayType01 := (0.545 ns, 0.640 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no3_x4 : entity is TRUE; +end no3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no3_x4_VITAL of no3_x4 is + for VITAL + end for; +end CFG_no3_x4_VITAL; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no4_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.330 ns, 0.340 ns); + tpd_i1_nq : VitalDelayType01 := (0.230 ns, 0.320 ns); + tpd_i2_nq : VitalDelayType01 := (0.419 ns, 0.333 ns); + tpd_i3_nq : VitalDelayType01 := (0.499 ns, 0.271 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no4_x1 : entity is TRUE; +end no4_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no4_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)) AND ((NOT + i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no4_x1_VITAL of no4_x1 is + for VITAL + end for; +end CFG_no4_x1_VITAL; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.656 ns, 0.777 ns); + tpd_i1_nq : VitalDelayType01 := (0.564 ns, 0.768 ns); + tpd_i2_nq : VitalDelayType01 := (0.739 ns, 0.761 ns); + tpd_i3_nq : VitalDelayType01 := (0.816 ns, 0.693 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no4_x4 : entity is TRUE; +end no4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)) AND ((NOT + i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no4_x4_VITAL of no4_x4 is + for VITAL + end for; +end CFG_no4_x4_VITAL; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.649 ns, 0.606 ns); + tpd_i1_nq : VitalDelayType01 := (0.775 ns, 0.562 ns); + tpd_i2_nq : VitalDelayType01 := (0.550 ns, 0.662 ns); + tpd_i3_nq : VitalDelayType01 := (0.667 ns, 0.616 ns); + tpd_i4_nq : VitalDelayType01 := (0.419 ns, 0.613 ns); + tpd_i5_nq : VitalDelayType01 := (0.329 ns, 0.662 ns); + tpd_i6_nq : VitalDelayType01 := (0.270 ns, 0.535 ns); + tpd_i7_nq : VitalDelayType01 := (0.200 ns, 0.591 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a2a24_x1 : entity is TRUE; +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a2a24_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))) AND (((NOT i7_ipd)) + OR ((NOT i6_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a2a24_x1_VITAL of noa2a2a2a24_x1 is + for VITAL + end for; +end CFG_noa2a2a2a24_x1_VITAL; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.966 ns, 1.049 ns); + tpd_i1_nq : VitalDelayType01 := (1.097 ns, 1.005 ns); + tpd_i2_nq : VitalDelayType01 := (0.867 ns, 1.106 ns); + tpd_i3_nq : VitalDelayType01 := (0.990 ns, 1.061 ns); + tpd_i4_nq : VitalDelayType01 := (0.748 ns, 1.061 ns); + tpd_i5_nq : VitalDelayType01 := (0.649 ns, 1.109 ns); + tpd_i6_nq : VitalDelayType01 := (0.606 ns, 0.999 ns); + tpd_i7_nq : VitalDelayType01 := (0.525 ns, 1.052 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a2a24_x4 : entity is TRUE; +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a2a24_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))) AND (((NOT i7_ipd)) + OR ((NOT i6_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a2a24_x4_VITAL of noa2a2a2a24_x4 is + for VITAL + end for; +end CFG_noa2a2a2a24_x4_VITAL; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.525 ns, 0.425 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.388 ns); + tpd_i2_nq : VitalDelayType01 := (0.307 ns, 0.479 ns); + tpd_i3_nq : VitalDelayType01 := (0.398 ns, 0.438 ns); + tpd_i4_nq : VitalDelayType01 := (0.250 ns, 0.416 ns); + tpd_i5_nq : VitalDelayType01 := (0.178 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a23_x1 : entity is TRUE; +end noa2a2a23_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a23_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a23_x1_VITAL of noa2a2a23_x1 is + for VITAL + end for; +end CFG_noa2a2a23_x1_VITAL; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.834 ns, 0.814 ns); + tpd_i1_nq : VitalDelayType01 := (0.955 ns, 0.778 ns); + tpd_i2_nq : VitalDelayType01 := (0.620 ns, 0.873 ns); + tpd_i3_nq : VitalDelayType01 := (0.716 ns, 0.833 ns); + tpd_i4_nq : VitalDelayType01 := (0.574 ns, 0.819 ns); + tpd_i5_nq : VitalDelayType01 := (0.496 ns, 0.865 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a23_x4 : entity is TRUE; +end noa2a2a23_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a23_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a23_x4_VITAL of noa2a2a23_x4 is + for VITAL + end for; +end CFG_noa2a2a23_x4_VITAL; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.284 ns, 0.289 ns); + tpd_i3_nq : VitalDelayType01 := (0.372 ns, 0.256 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a22_x1 : entity is TRUE; +end noa2a22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a22_x1_VITAL of noa2a22_x1 is + for VITAL + end for; +end CFG_noa2a22_x1_VITAL; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.562 ns, 0.745 ns); + tpd_i1_nq : VitalDelayType01 := (0.646 ns, 0.714 ns); + tpd_i2_nq : VitalDelayType01 := (0.701 ns, 0.703 ns); + tpd_i3_nq : VitalDelayType01 := (0.805 ns, 0.677 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a22_x4 : entity is TRUE; +end noa2a22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a22_x4_VITAL of noa2a22_x4 is + for VITAL + end for; +end CFG_noa2a22_x4_VITAL; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.348 ns, 0.422 ns); + tpd_i1_nq : VitalDelayType01 := (0.440 ns, 0.378 ns); + tpd_i2_nq : VitalDelayType01 := (0.186 ns, 0.473 ns); + tpd_i3_nq : VitalDelayType01 := (0.256 ns, 0.459 ns); + tpd_i4_nq : VitalDelayType01 := (0.240 ns, 0.309 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2ao222_x1 : entity is TRUE; +end noa2ao222_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2ao222_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i4_ipd)) OR (((NOT i3_ipd)) AND ((NOT i2_ipd)))) AND (((NOT + i1_ipd)) OR ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2ao222_x1_VITAL of noa2ao222_x1 is + for VITAL + end for; +end CFG_noa2ao222_x1_VITAL; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.684 ns, 0.801 ns); + tpd_i1_nq : VitalDelayType01 := (0.780 ns, 0.758 ns); + tpd_i2_nq : VitalDelayType01 := (0.638 ns, 0.809 ns); + tpd_i3_nq : VitalDelayType01 := (0.732 ns, 0.795 ns); + tpd_i4_nq : VitalDelayType01 := (0.718 ns, 0.664 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2ao222_x4 : entity is TRUE; +end noa2ao222_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2ao222_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i4_ipd)) OR (((NOT i3_ipd)) AND ((NOT i2_ipd)))) AND (((NOT + i1_ipd)) OR ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2ao222_x4_VITAL of noa2ao222_x4 is + for VITAL + end for; +end CFG_noa2ao222_x4_VITAL; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.396 ns, 0.616 ns); + tpd_i1_nq : VitalDelayType01 := (0.486 ns, 0.552 ns); + tpd_i2_nq : VitalDelayType01 := (0.546 ns, 0.488 ns); + tpd_i3_nq : VitalDelayType01 := (0.196 ns, 0.599 ns); + tpd_i4_nq : VitalDelayType01 := (0.264 ns, 0.608 ns); + tpd_i5_nq : VitalDelayType01 := (0.328 ns, 0.581 ns); + tpd_i6_nq : VitalDelayType01 := (0.246 ns, 0.311 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa3ao322_x1 : entity is TRUE; +end noa3ao322_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa3ao322_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i6_ipd)) OR (((NOT i4_ipd)) AND ((NOT i3_ipd)) AND ((NOT + i5_ipd)))) AND (((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa3ao322_x1_VITAL of noa3ao322_x1 is + for VITAL + end for; +end CFG_noa3ao322_x1_VITAL; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.819 ns, 0.987 ns); + tpd_i1_nq : VitalDelayType01 := (0.914 ns, 0.931 ns); + tpd_i2_nq : VitalDelayType01 := (0.990 ns, 0.874 ns); + tpd_i3_nq : VitalDelayType01 := (0.729 ns, 0.926 ns); + tpd_i4_nq : VitalDelayType01 := (0.821 ns, 0.924 ns); + tpd_i5_nq : VitalDelayType01 := (0.907 ns, 0.900 ns); + tpd_i6_nq : VitalDelayType01 := (0.738 ns, 0.718 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa3ao322_x4 : entity is TRUE; +end noa3ao322_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa3ao322_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i6_ipd)) OR (((NOT i4_ipd)) AND ((NOT i3_ipd)) AND ((NOT + i5_ipd)))) AND (((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa3ao322_x4_VITAL of noa3ao322_x4 is + for VITAL + end for; +end CFG_noa3ao322_x4_VITAL; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.218 ns, 0.241 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa22_x1 : entity is TRUE; +end noa22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) AND (((NOT i1_ipd)) OR ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa22_x1_VITAL of noa22_x1 is + for VITAL + end for; +end CFG_noa22_x1_VITAL; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.550 ns, 0.740 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.709 ns); + tpd_i2_nq : VitalDelayType01 := (0.610 ns, 0.646 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa22_x4 : entity is TRUE; +end noa22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) AND (((NOT i1_ipd)) OR ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa22_x4_VITAL of noa22_x4 is + for VITAL + end for; +end CFG_noa22_x4_VITAL; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nts_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01z := + (0.249 ns, 0.041 ns, 0.249 ns, 0.249 ns, 0.041 ns, 0.041 ns); + tpd_i_nq : VitalDelayType01 := (0.169 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nts_x1 : entity is TRUE; +end nts_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nts_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalBUFIF0 (data => (NOT i_ipd), + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_nq), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_nq), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_nts_x1_VITAL of nts_x1 is + for VITAL + end for; +end CFG_nts_x1_VITAL; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nts_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01z := + (0.330 ns, 0.033 ns, 0.330 ns, 0.330 ns, 0.033 ns, 0.033 ns); + tpd_i_nq : VitalDelayType01 := (0.167 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nts_x2 : entity is TRUE; +end nts_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nts_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalBUFIF0 (data => (NOT i_ipd), + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_nq), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_nq), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_nts_x2_VITAL of nts_x2 is + for VITAL + end for; +end CFG_nts_x2_VITAL; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nxr2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.288 ns, 0.293 ns); + tpd_i1_nq : VitalDelayType01 := (0.156 ns, 0.327 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nxr2_x1 : entity is TRUE; +end nxr2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nxr2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (i1_ipd) XOR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nxr2_x1_VITAL of nxr2_x1 is + for VITAL + end for; +end CFG_nxr2_x1_VITAL; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nxr2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.522 ns, 0.553 ns); + tpd_i1_nq : VitalDelayType01 := (0.553 ns, 0.542 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nxr2_x4 : entity is TRUE; +end nxr2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nxr2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (i1_ipd) XOR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nxr2_x4_VITAL of nxr2_x4 is + for VITAL + end for; +end CFG_nxr2_x4_VITAL; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o2_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.406 ns, 0.310 ns); + tpd_i1_q : VitalDelayType01 := (0.335 ns, 0.364 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o2_x2 : entity is TRUE; +end o2_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o2_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o2_x2_VITAL of o2_x2 is + for VITAL + end for; +end CFG_o2_x2_VITAL; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tpd_i1_q : VitalDelayType01 := (0.427 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o2_x4 : entity is TRUE; +end o2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o2_x4_VITAL of o2_x4 is + for VITAL + end for; +end CFG_o2_x4_VITAL; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o3_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.494 ns, 0.407 ns); + tpd_i1_q : VitalDelayType01 := (0.430 ns, 0.482 ns); + tpd_i2_q : VitalDelayType01 := (0.360 ns, 0.506 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o3_x2 : entity is TRUE; +end o3_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o3_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o3_x2_VITAL of o3_x2 is + for VITAL + end for; +end CFG_o3_x2_VITAL; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.569 ns, 0.501 ns); + tpd_i1_q : VitalDelayType01 := (0.510 ns, 0.585 ns); + tpd_i2_q : VitalDelayType01 := (0.447 ns, 0.622 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o3_x4 : entity is TRUE; +end o3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o3_x4_VITAL of o3_x4 is + for VITAL + end for; +end CFG_o3_x4_VITAL; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o4_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.508 ns, 0.601 ns); + tpd_i1_q : VitalDelayType01 := (0.446 ns, 0.631 ns); + tpd_i2_q : VitalDelayType01 := (0.567 ns, 0.531 ns); + tpd_i3_q : VitalDelayType01 := (0.378 ns, 0.626 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o4_x2 : entity is TRUE; +end o4_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o4_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd) OR (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o4_x2_VITAL of o4_x2 is + for VITAL + end for; +end CFG_o4_x2_VITAL; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.574 ns, 0.638 ns); + tpd_i1_q : VitalDelayType01 := (0.492 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.649 ns, 0.611 ns); + tpd_i3_q : VitalDelayType01 := (0.721 ns, 0.536 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o4_x4 : entity is TRUE; +end o4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd) OR (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o4_x4_VITAL of o4_x4 is + for VITAL + end for; +end CFG_o4_x4_VITAL; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.780 ns, 0.797 ns); + tpd_i1_q : VitalDelayType01 := (0.909 ns, 0.753 ns); + tpd_i2_q : VitalDelayType01 := (0.682 ns, 0.856 ns); + tpd_i3_q : VitalDelayType01 := (0.803 ns, 0.810 ns); + tpd_i4_q : VitalDelayType01 := (0.565 ns, 0.813 ns); + tpd_i5_q : VitalDelayType01 := (0.467 ns, 0.861 ns); + tpd_i6_q : VitalDelayType01 := (0.426 ns, 0.748 ns); + tpd_i7_q : VitalDelayType01 := (0.346 ns, 0.800 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a2a24_x2 : entity is TRUE; +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a2a24_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)) OR ((i7_ipd) AND (i6_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a2a24_x2_VITAL of oa2a2a2a24_x2 is + for VITAL + end for; +end CFG_oa2a2a2a24_x2_VITAL; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.823 ns, 0.879 ns); + tpd_i1_q : VitalDelayType01 := (0.955 ns, 0.835 ns); + tpd_i2_q : VitalDelayType01 := (0.726 ns, 0.940 ns); + tpd_i3_q : VitalDelayType01 := (0.851 ns, 0.895 ns); + tpd_i4_q : VitalDelayType01 := (0.619 ns, 0.902 ns); + tpd_i5_q : VitalDelayType01 := (0.515 ns, 0.949 ns); + tpd_i6_q : VitalDelayType01 := (0.487 ns, 0.845 ns); + tpd_i7_q : VitalDelayType01 := (0.399 ns, 0.895 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a2a24_x4 : entity is TRUE; +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a2a24_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)) OR ((i7_ipd) AND (i6_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a2a24_x4_VITAL of oa2a2a2a24_x4 is + for VITAL + end for; +end CFG_oa2a2a2a24_x4_VITAL; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.653 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.775 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.441 ns, 0.639 ns); + tpd_i3_q : VitalDelayType01 := (0.540 ns, 0.600 ns); + tpd_i4_q : VitalDelayType01 := (0.402 ns, 0.591 ns); + tpd_i5_q : VitalDelayType01 := (0.321 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a23_x2 : entity is TRUE; +end oa2a2a23_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a23_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a23_x2_VITAL of oa2a2a23_x2 is + for VITAL + end for; +end CFG_oa2a2a23_x2_VITAL; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.699 ns, 0.648 ns); + tpd_i1_q : VitalDelayType01 := (0.822 ns, 0.613 ns); + tpd_i2_q : VitalDelayType01 := (0.493 ns, 0.715 ns); + tpd_i3_q : VitalDelayType01 := (0.594 ns, 0.677 ns); + tpd_i4_q : VitalDelayType01 := (0.464 ns, 0.673 ns); + tpd_i5_q : VitalDelayType01 := (0.379 ns, 0.714 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a23_x4 : entity is TRUE; +end oa2a2a23_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a23_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a23_x4_VITAL of oa2a2a23_x4 is + for VITAL + end for; +end CFG_oa2a2a23_x4_VITAL; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.403 ns, 0.564 ns); + tpd_i1_q : VitalDelayType01 := (0.495 ns, 0.534 ns); + tpd_i2_q : VitalDelayType01 := (0.646 ns, 0.487 ns); + tpd_i3_q : VitalDelayType01 := (0.537 ns, 0.512 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a22_x2 : entity is TRUE; +end oa2a22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a22_x2_VITAL of oa2a22_x2 is + for VITAL + end for; +end CFG_oa2a22_x2_VITAL; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.519 ns, 0.696 ns); + tpd_i1_q : VitalDelayType01 := (0.624 ns, 0.669 ns); + tpd_i2_q : VitalDelayType01 := (0.763 ns, 0.596 ns); + tpd_i3_q : VitalDelayType01 := (0.644 ns, 0.619 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a22_x4 : entity is TRUE; +end oa2a22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a22_x4_VITAL of oa2a22_x4 is + for VITAL + end for; +end CFG_oa2a22_x4_VITAL; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.495 ns, 0.581 ns); + tpd_i1_q : VitalDelayType01 := (0.598 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.464 ns, 0.604 ns); + tpd_i3_q : VitalDelayType01 := (0.556 ns, 0.578 ns); + tpd_i4_q : VitalDelayType01 := (0.558 ns, 0.453 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2ao222_x2 : entity is TRUE; +end oa2ao222_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2ao222_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i3_ipd) OR (i2_ipd)) AND (i4_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2ao222_x2_VITAL of oa2ao222_x2 is + for VITAL + end for; +end CFG_oa2ao222_x2_VITAL; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.553 ns, 0.657 ns); + tpd_i1_q : VitalDelayType01 := (0.662 ns, 0.616 ns); + tpd_i2_q : VitalDelayType01 := (0.552 ns, 0.693 ns); + tpd_i3_q : VitalDelayType01 := (0.640 ns, 0.660 ns); + tpd_i4_q : VitalDelayType01 := (0.656 ns, 0.529 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2ao222_x4 : entity is TRUE; +end oa2ao222_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2ao222_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i3_ipd) OR (i2_ipd)) AND (i4_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2ao222_x4_VITAL of oa2ao222_x4 is + for VITAL + end for; +end CFG_oa2ao222_x4_VITAL; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.638 ns, 0.820 ns); + tpd_i1_q : VitalDelayType01 := (0.735 ns, 0.764 ns); + tpd_i2_q : VitalDelayType01 := (0.806 ns, 0.707 ns); + tpd_i3_q : VitalDelayType01 := (0.560 ns, 0.765 ns); + tpd_i4_q : VitalDelayType01 := (0.649 ns, 0.760 ns); + tpd_i5_q : VitalDelayType01 := (0.734 ns, 0.734 ns); + tpd_i6_q : VitalDelayType01 := (0.563 ns, 0.540 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa3ao322_x2 : entity is TRUE; +end oa3ao322_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa3ao322_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i4_ipd) OR (i3_ipd) OR (i5_ipd)) AND (i6_ipd)) OR ((i1_ipd) AND + (i0_ipd) AND (i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa3ao322_x2_VITAL of oa3ao322_x2 is + for VITAL + end for; +end CFG_oa3ao322_x2_VITAL; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.717 ns, 0.946 ns); + tpd_i1_q : VitalDelayType01 := (0.818 ns, 0.890 ns); + tpd_i2_q : VitalDelayType01 := (0.894 ns, 0.834 ns); + tpd_i3_q : VitalDelayType01 := (0.673 ns, 0.898 ns); + tpd_i4_q : VitalDelayType01 := (0.758 ns, 0.896 ns); + tpd_i5_q : VitalDelayType01 := (0.839 ns, 0.865 ns); + tpd_i6_q : VitalDelayType01 := (0.684 ns, 0.651 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa3ao322_x4 : entity is TRUE; +end oa3ao322_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa3ao322_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i4_ipd) OR (i3_ipd) OR (i5_ipd)) AND (i6_ipd)) OR ((i1_ipd) AND + (i0_ipd) AND (i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa3ao322_x4_VITAL of oa3ao322_x4 is + for VITAL + end for; +end CFG_oa3ao322_x4_VITAL; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.390 ns, 0.555 ns); + tpd_i1_q : VitalDelayType01 := (0.488 ns, 0.525 ns); + tpd_i2_q : VitalDelayType01 := (0.438 ns, 0.454 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa22_x2 : entity is TRUE; +end oa22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa22_x2_VITAL of oa22_x2 is + for VITAL + end for; +end CFG_oa22_x2_VITAL; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.511 ns, 0.677 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.523 ns, 0.571 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa22_x4 : entity is TRUE; +end oa22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa22_x4_VITAL of oa22_x4 is + for VITAL + end for; +end CFG_oa22_x4_VITAL; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity on12_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.111 ns, 0.234 ns); + tpd_i1_q : VitalDelayType01 := (0.314 ns, 0.291 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of on12_x1 : entity is TRUE; +end on12_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of on12_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_on12_x1_VITAL of on12_x1 is + for VITAL + end for; +end CFG_on12_x1_VITAL; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity on12_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.474 ns, 0.499 ns); + tpd_i1_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of on12_x4 : entity is TRUE; +end on12_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of on12_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_on12_x4_VITAL of on12_x4 is + for VITAL + end for; +end CFG_on12_x4_VITAL; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity one_x0 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True); + + port( + q : out STD_ULOGIC := '1'); +attribute VITAL_LEVEL0 of one_x0 : entity is TRUE; +end one_x0; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of one_x0 is + attribute VITAL_LEVEL0 of VITAL : architecture is TRUE; + + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + -- empty + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + q <= '1'; + + +end VITAL; + +configuration CFG_one_x0_VITAL of one_x0 is + for VITAL + end for; +end CFG_one_x0_VITAL; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity sff1_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i_ck : VitalDelayType := 0.585 ns; + thold_i_ck : VitalDelayType := 0.000 ns; + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of sff1_x4 : entity is TRUE; +end sff1_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of sff1_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL ck_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (ck_ipd, ck, tipd_ck); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, ck_ipd) + + -- timing check results + VARIABLE Tviol_i_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_i_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_q : STD_LOGIC_VECTOR(0 to 2); + VARIABLE i_delayed : STD_ULOGIC := 'X'; + VARIABLE ck_delayed : STD_ULOGIC := 'X'; + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_i_ck_posedge, + TimingData => Tmkr_i_ck_posedge, + TestSignal => i_ipd, + TestSignalName => "i", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_i_ck, + SetupLow => tsetup_i_ck, + HoldHigh => thold_i_ck, + HoldLow => thold_i_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff1_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_i_ck_posedge; + VitalStateTable( + Result => q_zd, + PreviousDataIn => PrevData_q, + StateTable => sff1_x4_q_tab, + DataIn => ( + ck_delayed, i_delayed, ck_ipd)); + q_zd := Violation XOR q_zd; + i_delayed := i_ipd; + ck_delayed := ck_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (ck_ipd'last_event, tpd_ck_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_sff1_x4_VITAL of sff1_x4 is + for VITAL + end for; +end CFG_sff1_x4_VITAL; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity sff2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i0_ck : VitalDelayType := 0.764 ns; + thold_i0_ck : VitalDelayType := 0.000 ns; + tsetup_i1_ck : VitalDelayType := 0.764 ns; + thold_i1_ck : VitalDelayType := 0.000 ns; + tsetup_cmd_ck : VitalDelayType := 0.833 ns; + thold_cmd_ck : VitalDelayType := 0.000 ns; + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + cmd : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of sff2_x4 : entity is TRUE; +end sff2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of sff2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL ck_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (ck_ipd, ck, tipd_ck); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, cmd_ipd, ck_ipd) + + -- timing check results + VARIABLE Tviol_i0_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_i0_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_i1_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_i1_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_cmd_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_cmd_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_q : STD_LOGIC_VECTOR(0 to 4); + VARIABLE i0_delayed : STD_ULOGIC := 'X'; + VARIABLE i1_delayed : STD_ULOGIC := 'X'; + VARIABLE cmd_delayed : STD_ULOGIC := 'X'; + VARIABLE ck_delayed : STD_ULOGIC := 'X'; + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_i0_ck_posedge, + TimingData => Tmkr_i0_ck_posedge, + TestSignal => i0_ipd, + TestSignalName => "i0", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_i0_ck, + SetupLow => tsetup_i0_ck, + HoldHigh => thold_i0_ck, + HoldLow => thold_i0_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff2_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalSetupHoldCheck ( + Violation => Tviol_i1_ck_posedge, + TimingData => Tmkr_i1_ck_posedge, + TestSignal => i1_ipd, + TestSignalName => "i1", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_i1_ck, + SetupLow => tsetup_i1_ck, + HoldHigh => thold_i1_ck, + HoldLow => thold_i1_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff2_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalSetupHoldCheck ( + Violation => Tviol_cmd_ck_posedge, + TimingData => Tmkr_cmd_ck_posedge, + TestSignal => cmd_ipd, + TestSignalName => "cmd", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_cmd_ck, + SetupLow => tsetup_cmd_ck, + HoldHigh => thold_cmd_ck, + HoldLow => thold_cmd_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff2_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_i0_ck_posedge or Tviol_i1_ck_posedge or Tviol_cmd_ck_posedge; + VitalStateTable( + Result => q_zd, + PreviousDataIn => PrevData_q, + StateTable => sff2_x4_q_tab, + DataIn => ( + ck_delayed, i1_delayed, i0_delayed, cmd_delayed, ck_ipd)); + q_zd := Violation XOR q_zd; + i0_delayed := i0_ipd; + i1_delayed := i1_ipd; + cmd_delayed := cmd_ipd; + ck_delayed := ck_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (ck_ipd'last_event, tpd_ck_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_sff2_x4_VITAL of sff2_x4 is + for VITAL + end for; +end CFG_sff2_x4_VITAL; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ts_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01z := + (0.492 ns, 0.409 ns, 0.492 ns, 0.492 ns, 0.409 ns, 0.409 ns); + tpd_i_q : VitalDelayType01 := (0.475 ns, 0.444 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ts_x4 : entity is TRUE; +end ts_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ts_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalBUFIF0 (data => i_ipd, + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_q), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_q), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_ts_x4_VITAL of ts_x4 is + for VITAL + end for; +end CFG_ts_x4_VITAL; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ts_x8 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01z := + (0.626 ns, 0.466 ns, 0.626 ns, 0.626 ns, 0.466 ns, 0.466 ns); + tpd_i_q : VitalDelayType01 := (0.613 ns, 0.569 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ts_x8 : entity is TRUE; +end ts_x8; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ts_x8 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalBUFIF0 (data => i_ipd, + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_q), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_q), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_ts_x8_VITAL of ts_x8 is + for VITAL + end for; +end CFG_ts_x8_VITAL; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity xr2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.292 ns, 0.293 ns); + tpd_i1_q : VitalDelayType01 := (0.377 ns, 0.261 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of xr2_x1 : entity is TRUE; +end xr2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of xr2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) XOR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_xr2_x1_VITAL of xr2_x1 is + for VITAL + end for; +end CFG_xr2_x1_VITAL; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity xr2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.521 ns, 0.560 ns); + tpd_i1_q : VitalDelayType01 := (0.541 ns, 0.657 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of xr2_x4 : entity is TRUE; +end xr2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of xr2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) XOR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_xr2_x4_VITAL of xr2_x4 is + for VITAL + end for; +end CFG_xr2_x4_VITAL; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity zero_x0 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True); + + port( + nq : out STD_ULOGIC := '0'); +attribute VITAL_LEVEL0 of zero_x0 : entity is TRUE; +end zero_x0; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of zero_x0 is + attribute VITAL_LEVEL0 of VITAL : architecture is TRUE; + + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + -- empty + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + nq <= '0'; + + +end VITAL; + +configuration CFG_zero_x0_VITAL of zero_x0 is + for VITAL + end for; +end CFG_zero_x0_VITAL; + + +---- end of library ---- diff --git a/pdks/symbolic/sxlib/cells/sxlib_Vcomponents.vhd b/pdks/symbolic/sxlib/cells/sxlib_Vcomponents.vhd new file mode 100644 index 000000000..5844b9e33 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sxlib_Vcomponents.vhd @@ -0,0 +1,2252 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_Vcomponents.vhd +-- FILE CONTENTS: VITAL Component Package +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : +-- HISTORY : +-- +---------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +-- synopsys translate_off + +library IEEE; +use IEEE.VITAL_Timing.all; +-- synopsys translate_on + +package VCOMPONENTS is + +constant DefaultTimingChecksOn : Boolean := True; +constant DefaultXon : Boolean := False; +constant DefaultMsgOn : Boolean := True; + +----- Component a2_x2 ----- +component a2_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.261 ns, 0.388 ns); + tpd_i1_q : VitalDelayType01 := (0.203 ns, 0.434 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a2_x4 ----- +component a2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.338 ns, 0.476 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a3_x2 ----- +component a3_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.395 ns, 0.435 ns); + tpd_i1_q : VitalDelayType01 := (0.353 ns, 0.479 ns); + tpd_i2_q : VitalDelayType01 := (0.290 ns, 0.521 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a3_x4 ----- +component a3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.478 ns, 0.514 ns); + tpd_i1_q : VitalDelayType01 := (0.428 ns, 0.554 ns); + tpd_i2_q : VitalDelayType01 := (0.356 ns, 0.592 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a4_x2 ----- +component a4_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.374 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.441 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.482 ns, 0.498 ns); + tpd_i3_q : VitalDelayType01 := (0.506 ns, 0.455 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a4_x4 ----- +component a4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.505 ns, 0.650 ns); + tpd_i1_q : VitalDelayType01 := (0.578 ns, 0.614 ns); + tpd_i2_q : VitalDelayType01 := (0.627 ns, 0.576 ns); + tpd_i3_q : VitalDelayType01 := (0.661 ns, 0.538 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component an12_x1 ----- +component an12_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.200 ns, 0.168 ns); + tpd_i1_q : VitalDelayType01 := (0.285 ns, 0.405 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component an12_x4 ----- +component an12_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.461 ns, 0.471 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao2o22_x2 ----- +component ao2o22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.572 ns, 0.451 ns); + tpd_i1_q : VitalDelayType01 := (0.508 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.432 ns, 0.627 ns); + tpd_i3_q : VitalDelayType01 := (0.488 ns, 0.526 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao2o22_x4 ----- +component ao2o22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.696 ns, 0.569 ns); + tpd_i1_q : VitalDelayType01 := (0.637 ns, 0.666 ns); + tpd_i2_q : VitalDelayType01 := (0.554 ns, 0.744 ns); + tpd_i3_q : VitalDelayType01 := (0.606 ns, 0.639 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao22_x2 ----- +component ao22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.558 ns, 0.447 ns); + tpd_i1_q : VitalDelayType01 := (0.493 ns, 0.526 ns); + tpd_i2_q : VitalDelayType01 := (0.420 ns, 0.425 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao22_x4 ----- +component ao22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.674 ns, 0.552 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i2_q : VitalDelayType01 := (0.526 ns, 0.505 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component buf_x2 ----- +component buf_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_q : VitalDelayType01 := (0.409 ns, 0.391 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component buf_x4 ----- +component buf_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_q : VitalDelayType01 := (0.379 ns, 0.409 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component buf_x8 ----- +component buf_x8 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_q : VitalDelayType01 := (0.343 ns, 0.396 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component inv_x1 ----- +component inv_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.101 ns, 0.139 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component inv_x2 ----- +component inv_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.069 ns, 0.163 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component inv_x4 ----- +component inv_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.071 ns, 0.143 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component inv_x8 ----- +component inv_x8 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.086 ns, 0.133 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component mx2_x2 ----- +component mx2_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01 := (0.484 ns, 0.522 ns); + tpd_i0_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tpd_i1_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component mx2_x4 ----- +component mx2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i0_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tpd_i1_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component mx3_x2 ----- +component mx3_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_q : VitalDelayType01 := (0.573 ns, 0.680 ns); + tpd_cmd1_q : VitalDelayType01 := (0.664 ns, 0.817 ns); + tpd_i0_q : VitalDelayType01 := (0.538 ns, 0.658 ns); + tpd_i1_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tpd_i2_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component mx3_x4 ----- +component mx3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_q : VitalDelayType01 := (0.683 ns, 0.779 ns); + tpd_cmd1_q : VitalDelayType01 := (0.792 ns, 0.967 ns); + tpd_i0_q : VitalDelayType01 := (0.640 ns, 0.774 ns); + tpd_i1_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tpd_i2_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component na2_x1 ----- +component na2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.059 ns, 0.288 ns); + tpd_i1_nq : VitalDelayType01 := (0.111 ns, 0.234 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na2_x4 ----- +component na2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.412 ns, 0.552 ns); + tpd_i1_nq : VitalDelayType01 := (0.353 ns, 0.601 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na3_x1 ----- +component na3_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.119 ns, 0.363 ns); + tpd_i1_nq : VitalDelayType01 := (0.171 ns, 0.316 ns); + tpd_i2_nq : VitalDelayType01 := (0.193 ns, 0.265 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na3_x4 ----- +component na3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.556 ns, 0.601 ns); + tpd_i1_nq : VitalDelayType01 := (0.460 ns, 0.691 ns); + tpd_i2_nq : VitalDelayType01 := (0.519 ns, 0.647 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na4_x1 ----- +component na4_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.179 ns, 0.438 ns); + tpd_i1_nq : VitalDelayType01 := (0.237 ns, 0.395 ns); + tpd_i2_nq : VitalDelayType01 := (0.269 ns, 0.350 ns); + tpd_i3_nq : VitalDelayType01 := (0.282 ns, 0.302 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na4_x4 ----- +component na4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.578 ns, 0.771 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.731 ns); + tpd_i2_nq : VitalDelayType01 := (0.681 ns, 0.689 ns); + tpd_i3_nq : VitalDelayType01 := (0.703 ns, 0.644 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao2o22_x1 ----- +component nao2o22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.237 ns, 0.307 ns); + tpd_i3_nq : VitalDelayType01 := (0.174 ns, 0.382 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao2o22_x4 ----- +component nao2o22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.734 ns, 0.644 ns); + tpd_i1_nq : VitalDelayType01 := (0.666 ns, 0.717 ns); + tpd_i2_nq : VitalDelayType01 := (0.664 ns, 0.721 ns); + tpd_i3_nq : VitalDelayType01 := (0.607 ns, 0.807 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao22_x1 ----- +component nao22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.165 ns, 0.238 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao22_x4 ----- +component nao22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.732 ns, 0.650 ns); + tpd_i1_nq : VitalDelayType01 := (0.664 ns, 0.723 ns); + tpd_i2_nq : VitalDelayType01 := (0.596 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx2_x1 ----- +component nmx2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i0_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tpd_i1_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx2_x4 ----- +component nmx2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01 := (0.632 ns, 0.708 ns); + tpd_i0_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tpd_i1_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx3_x1 ----- +component nmx3_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_nq : VitalDelayType01 := (0.356 ns, 0.495 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.414 ns, 0.566 ns); + tpd_i0_nq : VitalDelayType01 := (0.315 ns, 0.441 ns); + tpd_i1_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tpd_i2_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx3_x4 ----- +component nmx3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_nq : VitalDelayType01 := (0.790 ns, 0.936 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.866 ns, 1.048 ns); + tpd_i0_nq : VitalDelayType01 := (0.748 ns, 0.900 ns); + tpd_i1_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tpd_i2_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no2_x1 ----- +component no2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.298 ns, 0.121 ns); + tpd_i1_nq : VitalDelayType01 := (0.193 ns, 0.161 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no2_x4 ----- +component no2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.618 ns, 0.447 ns); + tpd_i1_nq : VitalDelayType01 := (0.522 ns, 0.504 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no3_x1 ----- +component no3_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.318 ns, 0.246 ns); + tpd_i1_nq : VitalDelayType01 := (0.215 ns, 0.243 ns); + tpd_i2_nq : VitalDelayType01 := (0.407 ns, 0.192 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no3_x4 ----- +component no3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.722 ns, 0.561 ns); + tpd_i1_nq : VitalDelayType01 := (0.638 ns, 0.623 ns); + tpd_i2_nq : VitalDelayType01 := (0.545 ns, 0.640 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no4_x1 ----- +component no4_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.330 ns, 0.340 ns); + tpd_i1_nq : VitalDelayType01 := (0.230 ns, 0.320 ns); + tpd_i2_nq : VitalDelayType01 := (0.419 ns, 0.333 ns); + tpd_i3_nq : VitalDelayType01 := (0.499 ns, 0.271 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no4_x4 ----- +component no4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.656 ns, 0.777 ns); + tpd_i1_nq : VitalDelayType01 := (0.564 ns, 0.768 ns); + tpd_i2_nq : VitalDelayType01 := (0.739 ns, 0.761 ns); + tpd_i3_nq : VitalDelayType01 := (0.816 ns, 0.693 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a2a24_x1 ----- +component noa2a2a2a24_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.649 ns, 0.606 ns); + tpd_i1_nq : VitalDelayType01 := (0.775 ns, 0.562 ns); + tpd_i2_nq : VitalDelayType01 := (0.550 ns, 0.662 ns); + tpd_i3_nq : VitalDelayType01 := (0.667 ns, 0.616 ns); + tpd_i4_nq : VitalDelayType01 := (0.419 ns, 0.613 ns); + tpd_i5_nq : VitalDelayType01 := (0.329 ns, 0.662 ns); + tpd_i6_nq : VitalDelayType01 := (0.270 ns, 0.535 ns); + tpd_i7_nq : VitalDelayType01 := (0.200 ns, 0.591 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a2a24_x4 ----- +component noa2a2a2a24_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.966 ns, 1.049 ns); + tpd_i1_nq : VitalDelayType01 := (1.097 ns, 1.005 ns); + tpd_i2_nq : VitalDelayType01 := (0.867 ns, 1.106 ns); + tpd_i3_nq : VitalDelayType01 := (0.990 ns, 1.061 ns); + tpd_i4_nq : VitalDelayType01 := (0.748 ns, 1.061 ns); + tpd_i5_nq : VitalDelayType01 := (0.649 ns, 1.109 ns); + tpd_i6_nq : VitalDelayType01 := (0.606 ns, 0.999 ns); + tpd_i7_nq : VitalDelayType01 := (0.525 ns, 1.052 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a23_x1 ----- +component noa2a2a23_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.525 ns, 0.425 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.388 ns); + tpd_i2_nq : VitalDelayType01 := (0.307 ns, 0.479 ns); + tpd_i3_nq : VitalDelayType01 := (0.398 ns, 0.438 ns); + tpd_i4_nq : VitalDelayType01 := (0.250 ns, 0.416 ns); + tpd_i5_nq : VitalDelayType01 := (0.178 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a23_x4 ----- +component noa2a2a23_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.834 ns, 0.814 ns); + tpd_i1_nq : VitalDelayType01 := (0.955 ns, 0.778 ns); + tpd_i2_nq : VitalDelayType01 := (0.620 ns, 0.873 ns); + tpd_i3_nq : VitalDelayType01 := (0.716 ns, 0.833 ns); + tpd_i4_nq : VitalDelayType01 := (0.574 ns, 0.819 ns); + tpd_i5_nq : VitalDelayType01 := (0.496 ns, 0.865 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a22_x1 ----- +component noa2a22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.284 ns, 0.289 ns); + tpd_i3_nq : VitalDelayType01 := (0.372 ns, 0.256 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a22_x4 ----- +component noa2a22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.562 ns, 0.745 ns); + tpd_i1_nq : VitalDelayType01 := (0.646 ns, 0.714 ns); + tpd_i2_nq : VitalDelayType01 := (0.701 ns, 0.703 ns); + tpd_i3_nq : VitalDelayType01 := (0.805 ns, 0.677 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2ao222_x1 ----- +component noa2ao222_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.348 ns, 0.422 ns); + tpd_i1_nq : VitalDelayType01 := (0.440 ns, 0.378 ns); + tpd_i2_nq : VitalDelayType01 := (0.186 ns, 0.473 ns); + tpd_i3_nq : VitalDelayType01 := (0.256 ns, 0.459 ns); + tpd_i4_nq : VitalDelayType01 := (0.240 ns, 0.309 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2ao222_x4 ----- +component noa2ao222_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.684 ns, 0.801 ns); + tpd_i1_nq : VitalDelayType01 := (0.780 ns, 0.758 ns); + tpd_i2_nq : VitalDelayType01 := (0.638 ns, 0.809 ns); + tpd_i3_nq : VitalDelayType01 := (0.732 ns, 0.795 ns); + tpd_i4_nq : VitalDelayType01 := (0.718 ns, 0.664 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa3ao322_x1 ----- +component noa3ao322_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.396 ns, 0.616 ns); + tpd_i1_nq : VitalDelayType01 := (0.486 ns, 0.552 ns); + tpd_i2_nq : VitalDelayType01 := (0.546 ns, 0.488 ns); + tpd_i3_nq : VitalDelayType01 := (0.196 ns, 0.599 ns); + tpd_i4_nq : VitalDelayType01 := (0.264 ns, 0.608 ns); + tpd_i5_nq : VitalDelayType01 := (0.328 ns, 0.581 ns); + tpd_i6_nq : VitalDelayType01 := (0.246 ns, 0.311 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa3ao322_x4 ----- +component noa3ao322_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.819 ns, 0.987 ns); + tpd_i1_nq : VitalDelayType01 := (0.914 ns, 0.931 ns); + tpd_i2_nq : VitalDelayType01 := (0.990 ns, 0.874 ns); + tpd_i3_nq : VitalDelayType01 := (0.729 ns, 0.926 ns); + tpd_i4_nq : VitalDelayType01 := (0.821 ns, 0.924 ns); + tpd_i5_nq : VitalDelayType01 := (0.907 ns, 0.900 ns); + tpd_i6_nq : VitalDelayType01 := (0.738 ns, 0.718 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa22_x1 ----- +component noa22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.218 ns, 0.241 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa22_x4 ----- +component noa22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.550 ns, 0.740 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.709 ns); + tpd_i2_nq : VitalDelayType01 := (0.610 ns, 0.646 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nts_x1 ----- +component nts_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01z := + (0.249 ns, 0.041 ns, 0.249 ns, 0.249 ns, 0.041 ns, 0.041 ns); + tpd_i_nq : VitalDelayType01 := (0.169 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nts_x2 ----- +component nts_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01z := + (0.330 ns, 0.033 ns, 0.330 ns, 0.330 ns, 0.033 ns, 0.033 ns); + tpd_i_nq : VitalDelayType01 := (0.167 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nxr2_x1 ----- +component nxr2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.288 ns, 0.293 ns); + tpd_i1_nq : VitalDelayType01 := (0.156 ns, 0.327 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nxr2_x4 ----- +component nxr2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.522 ns, 0.553 ns); + tpd_i1_nq : VitalDelayType01 := (0.553 ns, 0.542 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component o2_x2 ----- +component o2_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.406 ns, 0.310 ns); + tpd_i1_q : VitalDelayType01 := (0.335 ns, 0.364 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o2_x4 ----- +component o2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tpd_i1_q : VitalDelayType01 := (0.427 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o3_x2 ----- +component o3_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.494 ns, 0.407 ns); + tpd_i1_q : VitalDelayType01 := (0.430 ns, 0.482 ns); + tpd_i2_q : VitalDelayType01 := (0.360 ns, 0.506 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o3_x4 ----- +component o3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.569 ns, 0.501 ns); + tpd_i1_q : VitalDelayType01 := (0.510 ns, 0.585 ns); + tpd_i2_q : VitalDelayType01 := (0.447 ns, 0.622 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o4_x2 ----- +component o4_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.508 ns, 0.601 ns); + tpd_i1_q : VitalDelayType01 := (0.446 ns, 0.631 ns); + tpd_i2_q : VitalDelayType01 := (0.567 ns, 0.531 ns); + tpd_i3_q : VitalDelayType01 := (0.378 ns, 0.626 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o4_x4 ----- +component o4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.574 ns, 0.638 ns); + tpd_i1_q : VitalDelayType01 := (0.492 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.649 ns, 0.611 ns); + tpd_i3_q : VitalDelayType01 := (0.721 ns, 0.536 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a2a24_x2 ----- +component oa2a2a2a24_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.780 ns, 0.797 ns); + tpd_i1_q : VitalDelayType01 := (0.909 ns, 0.753 ns); + tpd_i2_q : VitalDelayType01 := (0.682 ns, 0.856 ns); + tpd_i3_q : VitalDelayType01 := (0.803 ns, 0.810 ns); + tpd_i4_q : VitalDelayType01 := (0.565 ns, 0.813 ns); + tpd_i5_q : VitalDelayType01 := (0.467 ns, 0.861 ns); + tpd_i6_q : VitalDelayType01 := (0.426 ns, 0.748 ns); + tpd_i7_q : VitalDelayType01 := (0.346 ns, 0.800 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a2a24_x4 ----- +component oa2a2a2a24_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.823 ns, 0.879 ns); + tpd_i1_q : VitalDelayType01 := (0.955 ns, 0.835 ns); + tpd_i2_q : VitalDelayType01 := (0.726 ns, 0.940 ns); + tpd_i3_q : VitalDelayType01 := (0.851 ns, 0.895 ns); + tpd_i4_q : VitalDelayType01 := (0.619 ns, 0.902 ns); + tpd_i5_q : VitalDelayType01 := (0.515 ns, 0.949 ns); + tpd_i6_q : VitalDelayType01 := (0.487 ns, 0.845 ns); + tpd_i7_q : VitalDelayType01 := (0.399 ns, 0.895 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a23_x2 ----- +component oa2a2a23_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.653 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.775 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.441 ns, 0.639 ns); + tpd_i3_q : VitalDelayType01 := (0.540 ns, 0.600 ns); + tpd_i4_q : VitalDelayType01 := (0.402 ns, 0.591 ns); + tpd_i5_q : VitalDelayType01 := (0.321 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a23_x4 ----- +component oa2a2a23_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.699 ns, 0.648 ns); + tpd_i1_q : VitalDelayType01 := (0.822 ns, 0.613 ns); + tpd_i2_q : VitalDelayType01 := (0.493 ns, 0.715 ns); + tpd_i3_q : VitalDelayType01 := (0.594 ns, 0.677 ns); + tpd_i4_q : VitalDelayType01 := (0.464 ns, 0.673 ns); + tpd_i5_q : VitalDelayType01 := (0.379 ns, 0.714 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a22_x2 ----- +component oa2a22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.403 ns, 0.564 ns); + tpd_i1_q : VitalDelayType01 := (0.495 ns, 0.534 ns); + tpd_i2_q : VitalDelayType01 := (0.646 ns, 0.487 ns); + tpd_i3_q : VitalDelayType01 := (0.537 ns, 0.512 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a22_x4 ----- +component oa2a22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.519 ns, 0.696 ns); + tpd_i1_q : VitalDelayType01 := (0.624 ns, 0.669 ns); + tpd_i2_q : VitalDelayType01 := (0.763 ns, 0.596 ns); + tpd_i3_q : VitalDelayType01 := (0.644 ns, 0.619 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2ao222_x2 ----- +component oa2ao222_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.495 ns, 0.581 ns); + tpd_i1_q : VitalDelayType01 := (0.598 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.464 ns, 0.604 ns); + tpd_i3_q : VitalDelayType01 := (0.556 ns, 0.578 ns); + tpd_i4_q : VitalDelayType01 := (0.558 ns, 0.453 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2ao222_x4 ----- +component oa2ao222_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.553 ns, 0.657 ns); + tpd_i1_q : VitalDelayType01 := (0.662 ns, 0.616 ns); + tpd_i2_q : VitalDelayType01 := (0.552 ns, 0.693 ns); + tpd_i3_q : VitalDelayType01 := (0.640 ns, 0.660 ns); + tpd_i4_q : VitalDelayType01 := (0.656 ns, 0.529 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa3ao322_x2 ----- +component oa3ao322_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.638 ns, 0.820 ns); + tpd_i1_q : VitalDelayType01 := (0.735 ns, 0.764 ns); + tpd_i2_q : VitalDelayType01 := (0.806 ns, 0.707 ns); + tpd_i3_q : VitalDelayType01 := (0.560 ns, 0.765 ns); + tpd_i4_q : VitalDelayType01 := (0.649 ns, 0.760 ns); + tpd_i5_q : VitalDelayType01 := (0.734 ns, 0.734 ns); + tpd_i6_q : VitalDelayType01 := (0.563 ns, 0.540 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa3ao322_x4 ----- +component oa3ao322_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.717 ns, 0.946 ns); + tpd_i1_q : VitalDelayType01 := (0.818 ns, 0.890 ns); + tpd_i2_q : VitalDelayType01 := (0.894 ns, 0.834 ns); + tpd_i3_q : VitalDelayType01 := (0.673 ns, 0.898 ns); + tpd_i4_q : VitalDelayType01 := (0.758 ns, 0.896 ns); + tpd_i5_q : VitalDelayType01 := (0.839 ns, 0.865 ns); + tpd_i6_q : VitalDelayType01 := (0.684 ns, 0.651 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa22_x2 ----- +component oa22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.390 ns, 0.555 ns); + tpd_i1_q : VitalDelayType01 := (0.488 ns, 0.525 ns); + tpd_i2_q : VitalDelayType01 := (0.438 ns, 0.454 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa22_x4 ----- +component oa22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.511 ns, 0.677 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.523 ns, 0.571 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component on12_x1 ----- +component on12_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.111 ns, 0.234 ns); + tpd_i1_q : VitalDelayType01 := (0.314 ns, 0.291 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component on12_x4 ----- +component on12_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.474 ns, 0.499 ns); + tpd_i1_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component one_x0 ----- +component one_x0 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn); + +-- synopsys translate_on + port( + q : out STD_ULOGIC := '1'); +end component; + + +----- Component sff1_x4 ----- +component sff1_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i_ck : VitalDelayType := 0.585 ns; + thold_i_ck : VitalDelayType := 0.000 ns; + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component sff2_x4 ----- +component sff2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i0_ck : VitalDelayType := 0.764 ns; + thold_i0_ck : VitalDelayType := 0.000 ns; + tsetup_i1_ck : VitalDelayType := 0.764 ns; + thold_i1_ck : VitalDelayType := 0.000 ns; + tsetup_cmd_ck : VitalDelayType := 0.833 ns; + thold_cmd_ck : VitalDelayType := 0.000 ns; + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + cmd : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ts_x4 ----- +component ts_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01z := + (0.492 ns, 0.409 ns, 0.492 ns, 0.492 ns, 0.409 ns, 0.409 ns); + tpd_i_q : VitalDelayType01 := (0.475 ns, 0.444 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ts_x8 ----- +component ts_x8 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01z := + (0.626 ns, 0.466 ns, 0.626 ns, 0.626 ns, 0.466 ns, 0.466 ns); + tpd_i_q : VitalDelayType01 := (0.613 ns, 0.569 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component xr2_x1 ----- +component xr2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.292 ns, 0.293 ns); + tpd_i1_q : VitalDelayType01 := (0.377 ns, 0.261 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component xr2_x4 ----- +component xr2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.521 ns, 0.560 ns); + tpd_i1_q : VitalDelayType01 := (0.541 ns, 0.657 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component zero_x0 ----- +component zero_x0 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn); + +-- synopsys translate_on + port( + nq : out STD_ULOGIC := '0'); +end component; + + +end VCOMPONENTS; + +---- end of VITAL components library ---- diff --git a/pdks/symbolic/sxlib/cells/sxlib_Vtables.vhd b/pdks/symbolic/sxlib/cells/sxlib_Vtables.vhd new file mode 100644 index 000000000..85db0e88c --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sxlib_Vtables.vhd @@ -0,0 +1,58 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_Vtables.vhd +-- FILE CONTENTS: VITAL Table Package +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : +-- HISTORY : +-- +---------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +-- synopsys translate_off + +library IEEE; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +-- synopsys translate_on + +package VTABLES is + + CONSTANT L : VitalTableSymbolType := '0'; + CONSTANT H : VitalTableSymbolType := '1'; + CONSTANT x : VitalTableSymbolType := '-'; + CONSTANT S : VitalTableSymbolType := 'S'; + CONSTANT R : VitalTableSymbolType := '/'; + CONSTANT U : VitalTableSymbolType := 'X'; + CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) + + CONSTANT sff1_x4_q_tab : VitalStateTableType := ( + ( L, L, H, x, L ), + ( L, H, H, x, H ), + ( H, x, x, x, S ), + ( x, x, L, x, S )); + + CONSTANT sff2_x4_q_tab : VitalStateTableType := ( + ( L, L, L, x, H, x, L ), + ( L, L, x, H, H, x, L ), + ( L, H, H, x, H, x, H ), + ( L, H, x, H, H, x, H ), + ( L, x, L, L, H, x, L ), + ( L, x, H, L, H, x, H ), + ( H, x, x, x, x, x, S ), + ( x, x, x, x, L, x, S )); + + +end VTABLES; + +---- end of VITAL tables library ---- diff --git a/pdks/symbolic/sxlib/cells/sxlib_components.vhd b/pdks/symbolic/sxlib/cells/sxlib_components.vhd new file mode 100644 index 000000000..0978efc26 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/sxlib_components.vhd @@ -0,0 +1,2677 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_components.vhd +-- FILE CONTENTS: Component Package +-- DATE CREATED : Mon May 7 10:19:50 2001 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : +-- HISTORY : +-- +---------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +-- synopsys translate_off +use IEEE.GS_TYPES.sdt_values_t; +-- synopsys translate_on + +package COMPONENTS is + +constant Default_Timing_mesg : Boolean := True; +constant Default_Timing_xgen : Boolean := False; + +----- Component a2_x2 ----- +component a2_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a2_x4 ----- +component a2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a3_x2 ----- +component a3_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a3_x4 ----- +component a3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a4_x2 ----- +component a4_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a4_x4 ----- +component a4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component an12_x1 ----- +component an12_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component an12_x4 ----- +component an12_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao2o22_x2 ----- +component ao2o22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao2o22_x4 ----- +component ao2o22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao22_x2 ----- +component ao22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao22_x4 ----- +component ao22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component buf_x2 ----- +component buf_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component buf_x4 ----- +component buf_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component buf_x8 ----- +component buf_x8 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component inv_x1 ----- +component inv_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component inv_x2 ----- +component inv_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component inv_x4 ----- +component inv_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component inv_x8 ----- +component inv_x8 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component mx2_x2 ----- +component mx2_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component mx2_x4 ----- +component mx2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component mx3_x2 ----- +component mx3_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component mx3_x4 ----- +component mx3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component na2_x1 ----- +component na2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na2_x4 ----- +component na2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na3_x1 ----- +component na3_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na3_x4 ----- +component na3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na4_x1 ----- +component na4_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na4_x4 ----- +component na4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao2o22_x1 ----- +component nao2o22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao2o22_x4 ----- +component nao2o22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao22_x1 ----- +component nao22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao22_x4 ----- +component nao22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx2_x1 ----- +component nmx2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx2_x4 ----- +component nmx2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx3_x1 ----- +component nmx3_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx3_x4 ----- +component nmx3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no2_x1 ----- +component no2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no2_x4 ----- +component no2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no3_x1 ----- +component no3_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no3_x4 ----- +component no3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no4_x1 ----- +component no4_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no4_x4 ----- +component no4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a2a24_x1 ----- +component noa2a2a2a24_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a2a24_x4 ----- +component noa2a2a2a24_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a23_x1 ----- +component noa2a2a23_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a23_x4 ----- +component noa2a2a23_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a22_x1 ----- +component noa2a22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a22_x4 ----- +component noa2a22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2ao222_x1 ----- +component noa2ao222_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2ao222_x4 ----- +component noa2ao222_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa3ao322_x1 ----- +component noa3ao322_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa3ao322_x4 ----- +component noa3ao322_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa22_x1 ----- +component noa22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa22_x4 ----- +component noa22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nts_x1 ----- +component nts_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nts_x2 ----- +component nts_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nxr2_x1 ----- +component nxr2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nxr2_x4 ----- +component nxr2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component o2_x2 ----- +component o2_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o2_x4 ----- +component o2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o3_x2 ----- +component o3_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o3_x4 ----- +component o3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o4_x2 ----- +component o4_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o4_x4 ----- +component o4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a2a24_x2 ----- +component oa2a2a2a24_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a2a24_x4 ----- +component oa2a2a2a24_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a23_x2 ----- +component oa2a2a23_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a23_x4 ----- +component oa2a2a23_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a22_x2 ----- +component oa2a22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a22_x4 ----- +component oa2a22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2ao222_x2 ----- +component oa2ao222_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2ao222_x4 ----- +component oa2ao222_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa3ao322_x2 ----- +component oa3ao322_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa3ao322_x4 ----- +component oa3ao322_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa22_x2 ----- +component oa22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa22_x4 ----- +component oa22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component on12_x1 ----- +component on12_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component on12_x4 ----- +component on12_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component one_x0 ----- +component one_x0 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen); + +-- synopsys translate_on + port( + q : out STD_LOGIC := '1'); +end component; + + +----- Component sff1_x4 ----- +component sff1_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component sff2_x4 ----- +component sff2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ts_x4 ----- +component ts_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ts_x8 ----- +component ts_x8 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component xr2_x1 ----- +component xr2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component xr2_x4 ----- +component xr2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component zero_x0 ----- +component zero_x0 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen); + +-- synopsys translate_on + port( + nq : out STD_LOGIC := '0'); +end component; + + +end COMPONENTS; + +---- end of components library ---- diff --git a/pdks/symbolic/sxlib/cells/tie_x0.al b/pdks/symbolic/sxlib/cells/tie_x0.al new file mode 100644 index 000000000..499292182 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/tie_x0.al @@ -0,0 +1,19 @@ +V ALLIANCE : 6 +H tie_x0,L,30/10/99 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +S 7,INTERNAL +Q 0.000176265 +S 6,INTERNAL +Q 0.000176265 +S 5,EXTERNAL,vdd +Q 0.00178498 +S 4,INTERNAL +Q 0.000176265 +S 3,INTERNAL +Q 0.000176265 +S 2,EXTERNAL,vss +Q 0.00178498 +S 1,INTERNAL +Q 0.000176265 +EOF diff --git a/pdks/symbolic/sxlib/cells/tie_x0.ap b/pdks/symbolic/sxlib/cells/tie_x0.ap new file mode 100644 index 000000000..d32a01967 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/tie_x0.ap @@ -0,0 +1,18 @@ +V ALLIANCE : 6 +H tie_x0,P,24/ 7/2002,100 +A 0,0,1000,5000 +S 500,500,500,1500,200,*,UP,ALU1 +S 500,3000,500,4500,200,*,DOWN,ALU1 +S 500,3000,500,4500,300,*,UP,NTIE +S 500,500,500,1500,300,*,DOWN,PTIE +S 0,4700,1000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,1000,3900,2400,*,RIGHT,NWELL +S 0,300,1000,300,600,vss,RIGHT,CALU1 +V 500,1500,CONT_BODY_P,* +V 500,1000,CONT_BODY_P,* +V 500,500,CONT_BODY_P,* +V 500,3000,CONT_BODY_N,* +V 500,3500,CONT_BODY_N,* +V 500,4000,CONT_BODY_N,* +V 500,4500,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/tie_x0.vbe b/pdks/symbolic/sxlib/cells/tie_x0.vbe new file mode 100644 index 000000000..938a45c77 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/tie_x0.vbe @@ -0,0 +1,18 @@ +ENTITY tie_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 500; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END tie_x0; + +ARCHITECTURE behaviour_data_flow OF tie_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on tie_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/sxlib/cells/tie_x0.vhd b/pdks/symbolic/sxlib/cells/tie_x0.vhd new file mode 100644 index 000000000..0049a9c60 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/tie_x0.vhd @@ -0,0 +1,16 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY tie_x0 IS +PORT( +); +END tie_x0; + +ARCHITECTURE RTL OF tie_x0 IS +BEGIN +END RTL; diff --git a/pdks/symbolic/sxlib/cells/ts_x4.al b/pdks/symbolic/sxlib/cells/ts_x4.al new file mode 100644 index 000000000..a0d92c79a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ts_x4.al @@ -0,0 +1,36 @@ +V ALLIANCE : 6 +H ts_x4,L,30/10/99 +C cmd,IN,EXTERNAL,7 +C i,IN,EXTERNAL,8 +C q,TRISTATE,EXTERNAL,1 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,2,7,5,0,0.75,0.75,7.3,7.3,5.4,12.75,tr_00012 +T P,0.35,5.9,1,6,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011 +T P,0.35,2.9,6,8,5,0,0.75,0.75,7.3,7.3,13.2,11.25,tr_00010 +T P,0.35,2.9,6,2,4,0,0.75,0.75,7.3,7.3,9.6,11.25,tr_00009 +T P,0.35,2.9,5,7,6,0,0.75,0.75,7.3,7.3,11.4,11.25,tr_00008 +T P,0.35,5.9,5,6,1,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00007 +T N,0.35,2.9,1,4,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00006 +T N,0.35,2.9,3,4,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,5.4,3,tr_00004 +T N,0.35,1.4,6,7,4,0,0.75,0.75,4.3,4.3,13.2,3,tr_00003 +T N,0.35,1.4,3,2,4,0,0.75,0.75,4.3,4.3,9.6,3,tr_00002 +T N,0.35,1.4,4,8,3,0,0.75,0.75,4.3,4.3,11.4,3,tr_00001 +S 8,EXTERNAL,i +Q 0.0029371 +S 7,EXTERNAL,cmd +Q 0.00891222 +S 6,INTERNAL +Q 0.00768869 +S 5,EXTERNAL,vdd +Q 0.00692574 +S 4,INTERNAL +Q 0.00628498 +S 3,EXTERNAL,vss +Q 0.00616192 +S 2,INTERNAL +Q 0.00506239 +S 1,EXTERNAL,q +Q 0.00264397 +EOF diff --git a/pdks/symbolic/sxlib/cells/ts_x4.ap b/pdks/symbolic/sxlib/cells/ts_x4.ap new file mode 100644 index 000000000..343602d4a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ts_x4.ap @@ -0,0 +1,135 @@ +V ALLIANCE : 6 +H ts_x4,P,18/ 5/2002,100 +A 0,0,5000,5000 +R 1500,2500,ref_ref,cmd_25 +R 1500,2000,ref_ref,cmd_20 +R 1500,1500,ref_ref,cmd_15 +R 1500,4000,ref_ref,cmd_40 +R 1500,3500,ref_ref,cmd_35 +R 1500,3000,ref_ref,cmd_30 +R 1500,1000,ref_ref,cmd_10 +R 4000,1500,ref_ref,i_15 +R 4000,3500,ref_ref,i_35 +R 4000,3000,ref_ref,i_30 +R 4000,2500,ref_ref,i_25 +R 4000,2000,ref_ref,i_20 +R 1000,4000,ref_ref,q_40 +R 1000,3500,ref_ref,q_35 +R 1000,3000,ref_ref,q_30 +R 1000,2500,ref_ref,q_25 +R 1000,2000,ref_ref,q_20 +R 1000,1500,ref_ref,q_15 +R 1000,1000,ref_ref,q_10 +S 1500,1000,1500,4000,200,cmd,DOWN,CALU1 +S 4000,1500,4000,3500,200,i,DOWN,CALU1 +S 1000,1000,1000,4000,200,q,DOWN,CALU1 +S 2100,1000,2400,1000,200,*,RIGHT,ALU1 +S 2300,1400,3200,1400,100,*,RIGHT,POLY +S 2400,1000,2400,4000,100,*,DOWN,ALU1 +S 1500,1500,1600,1500,100,*,RIGHT,ALU1 +S 1600,1500,1800,1500,300,*,RIGHT,POLY +S 0,300,5000,300,600,vss,RIGHT,CALU1 +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 0,4700,5000,4700,600,vdd,RIGHT,CALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 1800,3600,1800,4900,100,*,UP,PTRANS +S 2100,3800,2100,4700,300,*,UP,PDIF +S 3500,4000,4700,4000,100,*,RIGHT,ALU1 +S 3800,1500,4000,1500,300,*,RIGHT,POLY +S 4700,1000,4700,4000,100,*,DOWN,ALU1 +S 4100,800,4100,1200,300,*,UP,NDIF +S 2900,800,2900,1200,300,*,UP,NDIF +S 4400,600,4400,1400,100,*,UP,NTRANS +S 4700,800,4700,1200,300,*,UP,NDIF +S 3200,600,3200,1400,100,*,UP,NTRANS +S 3800,600,3800,1400,100,*,UP,NTRANS +S 2900,1000,4100,1000,100,*,RIGHT,ALU1 +S 2900,1000,2900,4000,100,*,DOWN,ALU1 +S 3500,400,3500,1200,300,*,UP,NDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 4000,1500,4000,3500,100,*,DOWN,ALU1 +S 2100,300,2900,300,300,*,RIGHT,PTIE +S 4100,300,4700,300,300,*,RIGHT,PTIE +S 4400,3100,4400,4400,100,*,UP,PTRANS +S 4700,3300,4700,4200,300,*,UP,PDIF +S 4100,3300,4100,4700,300,*,UP,PDIF +S 600,1400,600,1900,100,*,DOWN,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 600,1900,2900,1900,100,*,RIGHT,POLY +S 3400,1900,4400,1900,100,*,RIGHT,POLY +S 4400,1400,4400,1900,100,*,DOWN,POLY +S 3200,3100,3200,4400,100,*,UP,PTRANS +S 2900,3300,2900,4200,300,*,UP,PDIF +S 3800,3100,3800,4400,100,*,UP,PTRANS +S 3500,3300,3500,4200,300,*,UP,PDIF +S 0,3900,5000,3900,2400,*,LEFT,NWELL +S 2700,4700,3500,4700,300,*,RIGHT,NTIE +S 4000,3000,4200,3000,200,*,LEFT,ALU1 +S 4200,3000,4400,3000,300,*,RIGHT,POLY +S 3400,1800,3400,2700,100,*,DOWN,ALU1 +S 1800,2800,1800,3600,100,*,DOWN,POLY +S 3800,2800,3800,3100,100,*,DOWN,POLY +S 1800,2800,3800,2800,100,*,RIGHT,POLY +S 600,2300,600,2600,100,*,UP,POLY +S 1500,3000,1900,3000,200,*,RIGHT,ALU1 +S 1900,2800,1900,3000,300,*,UP,POLY +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1200,2300,1200,2600,100,*,DOWN,POLY +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 300,3000,300,4500,200,*,DOWN,ALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 2100,4000,2400,4000,200,*,RIGHT,ALU1 +S 1000,950,1000,4050,200,*,UP,ALU1 +S 3500,3500,3500,4000,100,*,UP,ALU1 +S 2300,3100,3200,3100,100,*,RIGHT,POLY +S 600,2300,4700,2300,100,*,RIGHT,POLY +V 2400,1500,CONT_POLY,* +V 2900,1800,CONT_POLY,* +V 1600,1500,CONT_POLY,* +V 300,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 1500,500,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 2100,4000,CONT_DIF_P,* +V 4700,4000,CONT_DIF_P,* +V 2900,4000,CONT_DIF_P,* +V 4100,4500,CONT_DIF_P,* +V 4000,1500,CONT_POLY,* +V 2900,1000,CONT_DIF_N,* +V 4700,1000,CONT_DIF_N,* +V 3500,500,CONT_DIF_N,* +V 4100,1000,CONT_DIF_N,* +V 3500,4000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2900,300,CONT_BODY_P,* +V 4700,300,CONT_BODY_P,* +V 4100,300,CONT_BODY_P,* +V 2100,300,CONT_BODY_P,* +V 3400,1800,CONT_POLY,* +V 900,3000,CONT_DIF_P,* +V 3400,2700,CONT_POLY,* +V 4700,2300,CONT_POLY,* +V 2700,4700,CONT_BODY_N,* +V 3500,4700,CONT_BODY_N,* +V 4200,3000,CONT_POLY,* +V 1900,3000,CONT_POLY,* +V 3500,3500,CONT_DIF_P,* +V 4700,3500,CONT_DIF_P,* +V 2900,3500,CONT_DIF_P,* +V 2400,3200,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/ts_x4.sym b/pdks/symbolic/sxlib/cells/ts_x4.sym new file mode 100644 index 000000000..a013224e5 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/ts_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/ts_x4.vbe b/pdks/symbolic/sxlib/cells/ts_x4.vbe new file mode 100644 index 000000000..25d28a499 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ts_x4.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i_q : NATURAL := 810; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tphl_cmd_q : NATURAL := 409; + CONSTANT tpll_i_q : NATURAL := 444; + CONSTANT tphh_i_q : NATURAL := 475; + CONSTANT tphh_cmd_q : NATURAL := 492; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x4; + +ARCHITECTURE behaviour_data_flow OF ts_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x4" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1100 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/sxlib/cells/ts_x4.vhd b/pdks/symbolic/sxlib/cells/ts_x4.vhd new file mode 100644 index 000000000..c5c71db96 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ts_x4.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ts_x4 IS +PORT( + cmd : IN STD_LOGIC; + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ts_x4; + +ARCHITECTURE RTL OF ts_x4 IS +BEGIN + PROCESS ( i, cmd ) + BEGIN + IF (cmd = '1') + THEN q <= i; + ELSE q <= 'Z'; + END IF; + END PROCESS; +END RTL; diff --git a/pdks/symbolic/sxlib/cells/ts_x8.al b/pdks/symbolic/sxlib/cells/ts_x8.al new file mode 100644 index 000000000..6dbe03655 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ts_x8.al @@ -0,0 +1,40 @@ +V ALLIANCE : 6 +H ts_x8,L,30/10/99 +C cmd,IN,EXTERNAL,7 +C i,IN,EXTERNAL,8 +C q,TRISTATE,EXTERNAL,2 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,3,5,2,0,0.75,0.75,13.3,13.3,4.5,11.25,tr_00016 +T P,0.35,5.9,2,5,3,0,0.75,0.75,13.3,13.3,2.7,11.25,tr_00015 +T P,0.35,5.9,3,5,2,0,0.75,0.75,13.3,13.3,8.1,11.25,tr_00014 +T P,0.35,2.9,5,6,4,0,0.75,0.75,7.3,7.3,14.1,11.25,tr_00013 +T P,0.35,2.9,3,7,5,0,0.75,0.75,7.3,7.3,15.9,11.25,tr_00012 +T P,0.35,2.9,6,7,3,0,0.75,0.75,7.3,7.3,9.9,12.75,tr_00011 +T P,0.35,5.9,2,5,3,0,0.75,0.75,13.3,13.3,6.3,11.25,tr_00010 +T P,0.35,2.9,5,8,3,0,0.75,0.75,7.3,7.3,17.7,11.25,tr_00009 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,4.5,2.25,tr_00008 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.7,2.25,tr_00007 +T N,0.35,1.4,1,6,4,0,0.75,0.75,4.3,4.3,14.1,3,tr_00006 +T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,15.9,3,tr_00005 +T N,0.35,1.4,6,7,1,0,0.75,0.75,4.3,4.3,9.9,3,tr_00004 +T N,0.35,1.4,5,7,4,0,0.75,0.75,4.3,4.3,17.7,3,tr_00003 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,6.3,2.25,tr_00002 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,8.1,2.25,tr_00001 +S 8,EXTERNAL,i +Q 0.0029371 +S 7,EXTERNAL,cmd +Q 0.00891222 +S 6,INTERNAL +Q 0.00502769 +S 5,INTERNAL +Q 0.00909993 +S 4,INTERNAL +Q 0.00797383 +S 3,EXTERNAL,vdd +Q 0.00965406 +S 2,EXTERNAL,q +Q 0.00611052 +S 1,EXTERNAL,vss +Q 0.00795016 +EOF diff --git a/pdks/symbolic/sxlib/cells/ts_x8.ap b/pdks/symbolic/sxlib/cells/ts_x8.ap new file mode 100644 index 000000000..5c3d4c57a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ts_x8.ap @@ -0,0 +1,161 @@ +V ALLIANCE : 6 +H ts_x8,P,18/ 5/2002,100 +A 0,0,6500,5000 +R 2500,2000,ref_ref,q_20 +R 2500,1500,ref_ref,q_15 +R 2500,1000,ref_ref,q_10 +R 5500,3500,ref_ref,i_35 +R 5500,3000,ref_ref,i_30 +R 5500,2500,ref_ref,i_25 +R 5500,2000,ref_ref,i_20 +R 2500,4000,ref_ref,q_40 +R 2500,3500,ref_ref,q_35 +R 2500,3000,ref_ref,q_30 +R 2500,2500,ref_ref,q_25 +R 3000,2500,ref_ref,cmd_25 +R 3000,2000,ref_ref,cmd_20 +R 3000,1500,ref_ref,cmd_15 +R 3000,4000,ref_ref,cmd_40 +R 3000,3500,ref_ref,cmd_35 +R 3000,3000,ref_ref,cmd_30 +R 3000,1000,ref_ref,cmd_10 +R 5500,1500,ref_ref,i_15 +S 2500,1000,2500,4000,200,q,DOWN,CALU1 +S 3000,1000,3000,4000,200,cmd,DOWN,CALU1 +S 5500,1500,5500,3500,200,i,DOWN,CALU1 +S 5600,3300,5600,4550,300,*,UP,PDIF +S 3850,3100,4700,3100,100,*,RIGHT,POLY +S 5000,3500,5000,4000,100,*,UP,ALU1 +S 2500,950,2500,4050,200,*,UP,ALU1 +S 0,3900,6500,3900,2400,*,LEFT,NWELL +S 1500,100,1500,1400,100,*,UP,NTRANS +S 900,100,900,1400,100,*,UP,NTRANS +S 1200,300,1200,1200,300,*,UP,NDIF +S 600,300,600,1200,300,*,UP,NDIF +S 4700,600,4700,1400,100,*,UP,NTRANS +S 5300,600,5300,1400,100,*,UP,NTRANS +S 5000,400,5000,1200,300,*,UP,NDIF +S 3300,600,3300,1400,100,*,UP,NTRANS +S 3600,800,3600,1200,300,*,UP,NDIF +S 5600,800,5600,1200,300,*,UP,NDIF +S 4400,800,4400,1200,300,*,UP,NDIF +S 5900,600,5900,1400,100,*,UP,NTRANS +S 6200,800,6200,1200,300,*,UP,NDIF +S 2400,300,2400,1200,300,*,UP,NDIF +S 3000,300,3000,1200,300,*,UP,NDIF +S 2100,100,2100,1400,100,*,UP,NTRANS +S 2700,100,2700,1400,100,*,UP,NTRANS +S 1800,300,1800,1200,300,*,UP,NDIF +S 600,2800,600,4700,300,*,UP,PDIF +S 1500,2600,1500,4900,100,*,UP,PTRANS +S 900,2600,900,4900,100,*,UP,PTRANS +S 1200,2800,1200,4700,300,*,UP,PDIF +S 2700,2600,2700,4900,100,*,UP,PTRANS +S 3000,2800,3000,4700,300,*,UP,PDIF +S 2400,2800,2400,4700,300,*,UP,PDIF +S 6200,3300,6200,4200,300,*,UP,PDIF +S 4700,3100,4700,4400,100,*,UP,PTRANS +S 4400,3300,4400,4200,300,*,UP,PDIF +S 5300,3100,5300,4400,100,*,UP,PTRANS +S 5000,3300,5000,4200,300,*,UP,PDIF +S 3300,3600,3300,4900,100,*,UP,PTRANS +S 3600,3800,3600,4700,300,*,UP,PDIF +S 2100,2600,2100,4900,100,*,UP,PTRANS +S 1800,2800,1800,4700,300,*,UP,PDIF +S 5900,3100,5900,4400,100,*,UP,PTRANS +S 4200,4700,5000,4700,300,*,RIGHT,NTIE +S 3600,300,4400,300,300,*,RIGHT,PTIE +S 5600,300,6200,300,300,*,RIGHT,PTIE +S 1500,1400,1500,1900,100,*,DOWN,POLY +S 900,1400,900,1900,100,*,DOWN,POLY +S 1500,2300,1500,2600,100,*,UP,POLY +S 900,2300,900,2600,100,*,DOWN,POLY +S 900,1900,4400,1900,100,*,RIGHT,POLY +S 3800,1400,4700,1400,100,*,RIGHT,POLY +S 2700,2300,2700,2600,100,*,DOWN,POLY +S 5700,3000,5900,3000,300,*,RIGHT,POLY +S 3300,2800,3300,3600,100,*,DOWN,POLY +S 5300,2800,5300,3100,100,*,DOWN,POLY +S 3300,2800,5300,2800,100,*,RIGHT,POLY +S 2100,2300,2100,2600,100,*,UP,POLY +S 3400,2800,3400,3000,300,*,UP,POLY +S 3100,1500,3300,1500,300,*,RIGHT,POLY +S 5300,1500,5500,1500,300,*,RIGHT,POLY +S 2100,1400,2100,1900,100,*,DOWN,POLY +S 2700,1400,2700,1900,100,*,DOWN,POLY +S 4900,1900,5900,1900,100,*,RIGHT,POLY +S 5900,1400,5900,1900,100,*,DOWN,POLY +S 0,4700,6500,4700,600,vdd,RIGHT,CALU1 +S 0,300,6500,300,600,vss,RIGHT,CALU1 +S 600,500,600,1000,200,*,DOWN,ALU1 +S 600,3000,600,4500,200,*,DOWN,ALU1 +S 3600,1000,3900,1000,200,*,RIGHT,ALU1 +S 1800,3000,1800,4500,200,*,DOWN,ALU1 +S 1800,500,1800,1000,200,*,DOWN,ALU1 +S 3600,4000,3900,4000,200,*,RIGHT,ALU1 +S 4400,1000,4400,4000,100,*,DOWN,ALU1 +S 5500,1500,5500,3500,100,*,DOWN,ALU1 +S 5500,3000,5700,3000,200,*,LEFT,ALU1 +S 4900,1800,4900,2700,100,*,DOWN,ALU1 +S 3900,1000,3900,4000,100,*,DOWN,ALU1 +S 3000,3000,3400,3000,200,*,RIGHT,ALU1 +S 3000,1500,3100,1500,100,*,RIGHT,ALU1 +S 3000,1000,3000,4000,100,*,UP,ALU1 +S 5000,4000,6200,4000,100,*,RIGHT,ALU1 +S 6200,1000,6200,4000,100,*,DOWN,ALU1 +S 4400,1000,5600,1000,100,*,RIGHT,ALU1 +S 1200,1000,1200,4000,200,*,DOWN,ALU1 +S 1200,2100,2500,2100,200,*,RIGHT,ALU1 +S 900,2300,6200,2300,100,*,RIGHT,POLY +V 4400,3500,CONT_DIF_P,* +V 3900,3200,CONT_POLY,* +V 6200,3500,CONT_DIF_P,* +V 5000,3500,CONT_DIF_P,* +V 600,500,CONT_DIF_N,* +V 600,1000,CONT_DIF_N,* +V 1200,1000,CONT_DIF_N,* +V 6200,1000,CONT_DIF_N,* +V 5000,500,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +V 2400,1000,CONT_DIF_N,* +V 1800,1000,CONT_DIF_N,* +V 3000,500,CONT_DIF_N,* +V 1800,500,CONT_DIF_N,* +V 3600,1000,CONT_DIF_N,* +V 4400,1000,CONT_DIF_N,* +V 1200,4000,CONT_DIF_P,* +V 1200,3500,CONT_DIF_P,* +V 1200,3000,CONT_DIF_P,* +V 600,4500,CONT_DIF_P,* +V 600,3000,CONT_DIF_P,* +V 600,3500,CONT_DIF_P,* +V 600,4000,CONT_DIF_P,* +V 2400,3000,CONT_DIF_P,* +V 6200,4000,CONT_DIF_P,* +V 4400,4000,CONT_DIF_P,* +V 5600,4500,CONT_DIF_P,* +V 5000,4000,CONT_DIF_P,* +V 3000,4500,CONT_DIF_P,* +V 1800,3000,CONT_DIF_P,* +V 2400,4000,CONT_DIF_P,* +V 2400,3500,CONT_DIF_P,* +V 1800,4000,CONT_DIF_P,* +V 1800,3500,CONT_DIF_P,* +V 1800,4500,CONT_DIF_P,* +V 3600,4000,CONT_DIF_P,* +V 4200,4700,CONT_BODY_N,* +V 5000,4700,CONT_BODY_N,* +V 4400,300,CONT_BODY_P,* +V 6200,300,CONT_BODY_P,* +V 5600,300,CONT_BODY_P,* +V 3600,300,CONT_BODY_P,* +V 4400,1800,CONT_POLY,* +V 3900,1500,CONT_POLY,* +V 3100,1500,CONT_POLY,* +V 5500,1500,CONT_POLY,* +V 5700,3000,CONT_POLY,* +V 4900,1800,CONT_POLY,* +V 4900,2700,CONT_POLY,* +V 6200,2300,CONT_POLY,* +V 3400,3000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/ts_x8.sym b/pdks/symbolic/sxlib/cells/ts_x8.sym new file mode 100644 index 000000000..4f9e57eb8 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/ts_x8.sym differ diff --git a/pdks/symbolic/sxlib/cells/ts_x8.vbe b/pdks/symbolic/sxlib/cells/ts_x8.vbe new file mode 100644 index 000000000..c92f94f59 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ts_x8.vbe @@ -0,0 +1,37 @@ +ENTITY ts_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_cmd_q : NATURAL := 400; + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_cmd_q : NATURAL := 450; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphl_cmd_q : NATURAL := 466; + CONSTANT tpll_i_q : NATURAL := 569; + CONSTANT tphh_i_q : NATURAL := 613; + CONSTANT tphh_cmd_q : NATURAL := 626; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x8; + +ARCHITECTURE behaviour_data_flow OF ts_x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on ts_x8" + SEVERITY WARNING; + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i after 1200 ps; + END BLOCK label0; + +END; diff --git a/pdks/symbolic/sxlib/cells/ts_x8.vhd b/pdks/symbolic/sxlib/cells/ts_x8.vhd new file mode 100644 index 000000000..464e29317 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/ts_x8.vhd @@ -0,0 +1,26 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY ts_x8 IS +PORT( + cmd : IN STD_LOGIC; + i : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END ts_x8; + +ARCHITECTURE RTL OF ts_x8 IS +BEGIN + PROCESS ( i, cmd ) + BEGIN + IF (cmd = '1') + THEN q <= i; + ELSE q <= 'Z'; + END IF; + END PROCESS; +END RTL; diff --git a/pdks/symbolic/sxlib/cells/xr2_x1.al b/pdks/symbolic/sxlib/cells/xr2_x1.al new file mode 100644 index 000000000..dbd8a28b3 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/xr2_x1.al @@ -0,0 +1,40 @@ +V ALLIANCE : 6 +H xr2_x1,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,7,10,6,0,0.75,0.75,13.3,13.3,9,11.25,tr_00012 +T P,0.35,5.9,6,5,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,6,8,7,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T P,0.35,5.9,2,9,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,2.9,7,8,5,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00008 +T P,0.35,2.9,9,10,7,0,0.75,0.75,7.3,7.3,10.8,11.25,tr_00007 +T N,0.35,2.9,4,8,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,1,10,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00005 +T N,0.35,2.9,2,5,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00004 +T N,0.35,2.9,3,9,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00003 +T N,0.35,1.4,4,10,9,0,0.75,0.75,4.3,4.3,10.8,3,tr_00002 +T N,0.35,1.4,5,8,4,0,0.75,0.75,4.3,4.3,1.8,3,tr_00001 +S 10,EXTERNAL,i1 +Q 0.00533757 +S 9,INTERNAL +Q 0.00655161 +S 8,EXTERNAL,i0 +Q 0.00413388 +S 7,EXTERNAL,vdd +Q 0.0047041 +S 6,INTERNAL +Q 0.00274153 +S 5,INTERNAL +Q 0.0053513 +S 4,EXTERNAL,vss +Q 0.0047041 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,q +Q 0.0029965 +S 1,INTERNAL +Q 0 +EOF diff --git a/pdks/symbolic/sxlib/cells/xr2_x1.ap b/pdks/symbolic/sxlib/cells/xr2_x1.ap new file mode 100644 index 000000000..9c3bbb236 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/xr2_x1.ap @@ -0,0 +1,116 @@ +V ALLIANCE : 6 +H xr2_x1,P, 8/ 6/2002,100 +A 0,0,4500,5000 +R 2000,3000,ref_ref,q_30 +R 2000,3500,ref_ref,q_35 +R 3500,4000,ref_ref,i1_40 +R 3500,3500,ref_ref,i1_35 +R 3500,3000,ref_ref,i1_30 +R 3500,2500,ref_ref,i1_25 +R 3500,2000,ref_ref,i1_20 +R 3500,1500,ref_ref,i1_15 +R 3500,1000,ref_ref,i1_10 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,1500,ref_ref,i0_15 +R 1000,1000,ref_ref,i0_10 +R 1500,1000,ref_ref,q_10 +R 1500,1500,ref_ref,q_15 +R 1500,2000,ref_ref,q_20 +R 1500,2500,ref_ref,q_25 +S 3800,300,4300,300,300,*,RIGHT,PTIE +S 3800,4700,4300,4700,300,*,RIGHT,NTIE +S 1500,3500,1500,4000,100,*,UP,ALU1 +S 4000,3500,4000,4000,100,*,DOWN,ALU1 +S 1500,950,1500,3050,200,*,UP,ALU1 +S 1500,3000,2000,3000,200,*,LEFT,ALU1 +S 2000,3000,2000,3500,200,*,DOWN,ALU1 +S 2700,3000,2700,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,DOWN,ALU1 +S 4000,800,4000,1200,300,*,UP,NDIF +S 4000,3300,4000,4200,300,*,DOWN,PDIF +S 4000,1000,4000,3500,100,*,DOWN,ALU1 +S 2000,2500,2500,2500,100,*,RIGHT,ALU1 +S 2500,2000,3000,2000,100,*,RIGHT,ALU1 +S 2500,2000,2500,2500,100,*,DOWN,ALU1 +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 3000,1400,3000,2000,100,*,DOWN,POLY +S 3000,2600,3600,2600,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 2000,1500,3500,1500,100,*,RIGHT,ALU1 +S 3500,1000,3500,4000,100,*,DOWN,ALU1 +S 3600,2600,3600,3100,100,*,DOWN,POLY +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 3600,3100,3600,4400,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 600,2600,600,3100,100,*,DOWN,POLY +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 1500,4000,2700,4000,100,*,RIGHT,ALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 1500,1000,2100,1000,200,*,RIGHT,ALU1 +S 3500,1000,3500,4000,200,i1,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 2000,3000,2000,3500,200,q,DOWN,CALU1 +S 1500,1000,1500,3000,200,q,DOWN,CALU1 +S 2000,1000,2000,1000,200,q,LEFT,CALU1 +V 1500,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 300,4000,CONT_DIF_P,* +V 4000,1000,CONT_DIF_N,* +V 4000,3500,CONT_DIF_P,* +V 4000,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2100,3500,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 3900,4700,CONT_BODY_N,* +V 3900,300,CONT_BODY_P,* +V 1000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/sxlib/cells/xr2_x1.sym b/pdks/symbolic/sxlib/cells/xr2_x1.sym new file mode 100644 index 000000000..2e21e7d45 Binary files /dev/null and b/pdks/symbolic/sxlib/cells/xr2_x1.sym differ diff --git a/pdks/symbolic/sxlib/cells/xr2_x1.vbe b/pdks/symbolic/sxlib/cells/xr2_x1.vbe new file mode 100644 index 000000000..925f29ad5 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/xr2_x1.vbe @@ -0,0 +1,36 @@ +ENTITY xr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i1_q : NATURAL := 261; + CONSTANT tphl_i0_q : NATURAL := 292; + CONSTANT tplh_i0_q : NATURAL := 293; + CONSTANT tphh_i0_q : NATURAL := 366; + CONSTANT tphl_i1_q : NATURAL := 377; + CONSTANT tpll_i1_q : NATURAL := 388; + CONSTANT tpll_i0_q : NATURAL := 389; + CONSTANT tphh_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x1; + +ARCHITECTURE behaviour_data_flow OF xr2_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x1" + SEVERITY WARNING; + q <= (i0 xor i1) after 1000 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/xr2_x1.vhd b/pdks/symbolic/sxlib/cells/xr2_x1.vhd new file mode 100644 index 000000000..dca011498 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/xr2_x1.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY xr2_x1 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END xr2_x1; + +ARCHITECTURE RTL OF xr2_x1 IS +BEGIN + q <= (i0 XOR i1); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/xr2_x4.al b/pdks/symbolic/sxlib/cells/xr2_x4.al new file mode 100644 index 000000000..c22559274 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/xr2_x4.al @@ -0,0 +1,46 @@ +V ALLIANCE : 6 +H xr2_x4,L,30/10/99 +C i0,IN,EXTERNAL,8 +C i1,IN,EXTERNAL,9 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,10,9,7,0,0.75,0.75,7.3,7.3,10.8,9.75,tr_00016 +T P,0.35,2.9,7,8,4,0,0.75,0.75,7.3,7.3,1.8,9.75,tr_00015 +T P,0.35,5.9,11,2,7,0,0.75,0.75,13.3,13.3,14.4,11.25,tr_00014 +T P,0.35,5.9,7,2,11,0,0.75,0.75,13.3,13.3,16.2,11.25,tr_00013 +T P,0.35,5.9,2,9,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00012 +T P,0.35,5.9,6,8,7,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00011 +T P,0.35,5.9,6,4,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,7,10,6,0,0.75,0.75,13.3,13.3,9,11.25,tr_00009 +T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,16.2,2.25,tr_00008 +T N,0.35,2.9,1,2,11,0,0.75,0.75,7.3,7.3,14.4,2.25,tr_00007 +T N,0.35,1.4,4,8,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00006 +T N,0.35,1.4,1,9,10,0,0.75,0.75,4.3,4.3,10.8,3,tr_00005 +T N,0.35,2.9,3,9,1,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004 +T N,0.35,2.9,2,4,3,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,5,10,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00002 +T N,0.35,2.9,1,8,5,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00001 +S 11,EXTERNAL,q +Q 0.00258522 +S 10,INTERNAL +Q 0.00536068 +S 9,EXTERNAL,i1 +Q 0.00462772 +S 8,EXTERNAL,i0 +Q 0.00370588 +S 7,EXTERNAL,vdd +Q 0.00866628 +S 6,INTERNAL +Q 0.00274153 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00506945 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00791506 +S 1,EXTERNAL,vss +Q 0.00737367 +EOF diff --git a/pdks/symbolic/sxlib/cells/xr2_x4.ap b/pdks/symbolic/sxlib/cells/xr2_x4.ap new file mode 100644 index 000000000..98dde6011 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/xr2_x4.ap @@ -0,0 +1,143 @@ +V ALLIANCE : 6 +H xr2_x4,P, 8/ 6/2002,100 +A 0,0,6000,5000 +R 5000,4000,ref_ref,q_40 +R 5000,1000,ref_ref,q_10 +R 5000,3000,ref_ref,q_30 +R 5000,3500,ref_ref,q_35 +R 5000,2500,ref_ref,q_25 +R 5000,2000,ref_ref,q_20 +R 5000,1500,ref_ref,q_15 +R 3500,4000,ref_ref,i1_40 +R 3500,3500,ref_ref,i1_35 +R 3500,3000,ref_ref,i1_30 +R 3500,2500,ref_ref,i1_25 +R 3500,2000,ref_ref,i1_20 +R 3500,1500,ref_ref,i1_15 +R 1000,4000,ref_ref,i0_40 +R 1000,3500,ref_ref,i0_35 +R 1000,3000,ref_ref,i0_30 +R 1000,2000,ref_ref,i0_20 +R 1000,2500,ref_ref,i0_25 +R 1000,1500,ref_ref,i0_15 +R 1000,1000,ref_ref,i0_10 +S 300,4300,300,4800,300,*,DOWN,NTIE +S 3900,4300,3900,4800,300,*,DOWN,NTIE +S 4500,2000,5400,2000,300,*,RIGHT,POLY +S 5000,1000,5000,4000,200,q,DOWN,CALU1 +S 3500,1500,3500,4000,200,i1,DOWN,CALU1 +S 1000,1000,1000,4000,200,i0,DOWN,CALU1 +S 0,3900,6000,3900,2400,*,LEFT,NWELL +S 4500,300,4500,1000,300,*,UP,NDIF +S 3900,800,3900,1600,300,*,UP,NDIF +S 1500,1000,4500,1000,100,*,RIGHT,ALU1 +S 4500,1000,4500,2000,100,*,DOWN,ALU1 +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 5400,1400,5400,2600,100,*,DOWN,POLY +S 5700,500,5700,1000,200,*,DOWN,ALU1 +S 5700,3000,5700,4500,200,*,DOWN,ALU1 +S 4500,3500,4500,4500,200,*,DOWN,ALU1 +S 3500,1500,3500,4000,100,*,DOWN,ALU1 +S 4000,1500,4000,2900,100,*,DOWN,ALU1 +S 0,300,6000,300,600,vss,RIGHT,CALU1 +S 0,4700,6000,4700,600,vdd,RIGHT,CALU1 +S 5700,300,5700,1200,300,*,UP,NDIF +S 5100,300,5100,1200,300,*,UP,NDIF +S 5400,100,5400,1400,100,*,DOWN,NTRANS +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 3900,2800,3900,3700,300,*,DOWN,PDIF +S 4500,3400,4500,4700,300,*,DOWN,PDIF +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 600,2600,600,3900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,UP,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 5700,2800,5700,4700,300,*,DOWN,PDIF +S 2500,2000,3000,2000,100,*,RIGHT,ALU1 +S 2500,1500,2500,2000,100,*,DOWN,ALU1 +S 2000,1500,2500,1500,100,*,RIGHT,ALU1 +S 3000,1400,3600,1400,100,*,RIGHT,POLY +S 2000,2500,3500,2500,100,*,RIGHT,ALU1 +S 3000,2000,3000,2600,100,*,DOWN,POLY +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 1500,4000,2700,4000,100,*,RIGHT,ALU1 +S 300,1000,300,3000,100,*,DOWN,ALU1 +S 2100,3000,2100,3500,100,*,DOWN,ALU1 +S 1500,3000,2100,3000,100,*,LEFT,ALU1 +S 1500,1000,1500,3000,100,*,UP,ALU1 +S 1500,3500,1500,4000,100,*,UP,ALU1 +S 2700,3000,2700,4000,100,*,DOWN,ALU1 +S 300,3000,300,3500,100,*,UP,ALU1 +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +V 4500,2000,CONT_POLY,* +V 4000,2900,CONT_DIF_P,* +V 4000,1500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 5100,3000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 5700,3000,CONT_DIF_P,* +V 5700,3500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 5700,4500,CONT_DIF_P,* +V 5700,1000,CONT_DIF_N,* +V 5700,500,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 300,3000,CONT_DIF_P,* +V 3000,2000,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 3500,2500,CONT_POLY,* +V 3500,1500,CONT_POLY,* +V 2000,2500,CONT_POLY,* +V 2000,1500,CONT_POLY,* +V 2100,3500,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 900,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 300,4700,CONT_BODY_N,* +V 3900,4700,CONT_BODY_N,* +V 1000,2500,CONT_POLY,* +V 1000,1500,CONT_POLY,* +V 300,2000,CONT_POLY,* +V 1500,3500,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/sxlib/cells/xr2_x4.sym b/pdks/symbolic/sxlib/cells/xr2_x4.sym new file mode 100644 index 000000000..8198a29be Binary files /dev/null and b/pdks/symbolic/sxlib/cells/xr2_x4.sym differ diff --git a/pdks/symbolic/sxlib/cells/xr2_x4.vbe b/pdks/symbolic/sxlib/cells/xr2_x4.vbe new file mode 100644 index 000000000..7e2da9edb --- /dev/null +++ b/pdks/symbolic/sxlib/cells/xr2_x4.vbe @@ -0,0 +1,36 @@ +ENTITY xr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 357; + CONSTANT tphh_i0_q : NATURAL := 476; + CONSTANT tpll_i0_q : NATURAL := 480; + CONSTANT tphl_i0_q : NATURAL := 521; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphl_i1_q : NATURAL := 541; + CONSTANT tplh_i0_q : NATURAL := 560; + CONSTANT tplh_i1_q : NATURAL := 657; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x4; + +ARCHITECTURE behaviour_data_flow OF xr2_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xr2_x4" + SEVERITY WARNING; + q <= (i0 xor i1) after 1300 ps; +END; diff --git a/pdks/symbolic/sxlib/cells/xr2_x4.vhd b/pdks/symbolic/sxlib/cells/xr2_x4.vhd new file mode 100644 index 000000000..404a3949d --- /dev/null +++ b/pdks/symbolic/sxlib/cells/xr2_x4.vhd @@ -0,0 +1,20 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY xr2_x4 IS +PORT( + i0 : IN STD_LOGIC; + i1 : IN STD_LOGIC; + q : OUT STD_LOGIC +); +END xr2_x4; + +ARCHITECTURE RTL OF xr2_x4 IS +BEGIN + q <= (i0 XOR i1); +END RTL; diff --git a/pdks/symbolic/sxlib/cells/zero_x0.al b/pdks/symbolic/sxlib/cells/zero_x0.al new file mode 100644 index 000000000..aafb6a73a --- /dev/null +++ b/pdks/symbolic/sxlib/cells/zero_x0.al @@ -0,0 +1,13 @@ +V ALLIANCE : 6 +H zero_x0,L,30/10/99 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,3 +C vss,IN,EXTERNAL,2 +T N,0.35,1.4,2,3,1,0,0.75,0.75,4.3,4.3,2.1,4.5,tr_00001 +S 3,EXTERNAL,vdd +Q 0.00535397 +S 2,EXTERNAL,vss +Q 0.00330156 +S 1,EXTERNAL,nq +Q 0.00205642 +EOF diff --git a/pdks/symbolic/sxlib/cells/zero_x0.ap b/pdks/symbolic/sxlib/cells/zero_x0.ap new file mode 100644 index 000000000..54fd3dc81 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/zero_x0.ap @@ -0,0 +1,35 @@ +V ALLIANCE : 6 +H zero_x0,P,18/ 5/2002,100 +A 0,0,1500,5000 +R 1000,1000,ref_ref,nq_10 +R 1000,1500,ref_ref,nq_15 +R 1000,2000,ref_ref,nq_20 +R 1000,2500,ref_ref,nq_25 +R 1000,3000,ref_ref,nq_30 +R 1000,3500,ref_ref,nq_35 +R 1000,4000,ref_ref,nq_40 +S 400,500,1000,500,300,*,RIGHT,PTIE +S 400,300,400,1500,200,*,DOWN,ALU1 +S 500,2000,500,4700,200,*,DOWN,ALU1 +S 700,1100,700,1900,100,*,DOWN,NTRANS +S 1000,1300,1000,1700,300,*,UP,NDIF +S 350,1300,350,1700,400,*,UP,NDIF +S 400,2000,700,2000,300,*,RIGHT,POLY +S 500,4500,1000,4500,300,*,LEFT,NTIE +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 0,4700,1500,4700,600,vdd,RIGHT,CALU1 +S 0,300,1500,300,600,vss,RIGHT,CALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 500,3000,500,4600,300,*,UP,NTIE +S 1000,1000,1000,4000,200,nq,DOWN,CALU1 +V 400,500,CONT_BODY_P,* +V 1000,500,CONT_BODY_P,* +V 1000,1500,CONT_DIF_N,* +V 400,1500,CONT_DIF_N,* +V 500,2000,CONT_POLY,* +V 500,4500,CONT_BODY_N,* +V 1000,4500,CONT_BODY_N,* +V 500,3000,CONT_BODY_N,* +V 500,3500,CONT_BODY_N,* +V 500,4000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/sxlib/cells/zero_x0.sym b/pdks/symbolic/sxlib/cells/zero_x0.sym new file mode 100644 index 000000000..5452045be Binary files /dev/null and b/pdks/symbolic/sxlib/cells/zero_x0.sym differ diff --git a/pdks/symbolic/sxlib/cells/zero_x0.vbe b/pdks/symbolic/sxlib/cells/zero_x0.vbe new file mode 100644 index 000000000..535efebc9 --- /dev/null +++ b/pdks/symbolic/sxlib/cells/zero_x0.vbe @@ -0,0 +1,20 @@ +ENTITY zero_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 750; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END zero_x0; + +ARCHITECTURE behaviour_data_flow OF zero_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on zero_x0" + SEVERITY WARNING; + nq <= '0'; +END; diff --git a/pdks/symbolic/sxlib/cells/zero_x0.vhd b/pdks/symbolic/sxlib/cells/zero_x0.vhd new file mode 100644 index 000000000..c662155ca --- /dev/null +++ b/pdks/symbolic/sxlib/cells/zero_x0.vhd @@ -0,0 +1,18 @@ + +-- +-- Generated by VASY +-- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY zero_x0 IS +PORT( + nq : OUT STD_LOGIC +); +END zero_x0; + +ARCHITECTURE RTL OF zero_x0 IS +BEGIN + nq <= '0'; +END RTL; diff --git a/pdks/symbolic/sxlib/cmos_sx/libs.tech/coriolis/cmos_sx/__init__.py b/pdks/symbolic/sxlib/cmos_sx/libs.tech/coriolis/cmos_sx/__init__.py new file mode 100644 index 000000000..b87e091fc --- /dev/null +++ b/pdks/symbolic/sxlib/cmos_sx/libs.tech/coriolis/cmos_sx/__init__.py @@ -0,0 +1,5 @@ + +import os +from pathlib import Path + +path = Path( os.path.dirname(os.path.abspath(__file__)) ) diff --git a/pdks/symbolic/sxlib/cmos_sx/libs.tech/coriolis/cmos_sx/cmos.rds b/pdks/symbolic/sxlib/cmos_sx/libs.tech/coriolis/cmos_sx/cmos.rds new file mode 100644 index 000000000..a52f91832 --- /dev/null +++ b/pdks/symbolic/sxlib/cmos_sx/libs.tech/coriolis/cmos_sx/cmos.rds @@ -0,0 +1,948 @@ +#===================================================================== +# +# ALLIANCE VLSI CAD +# (R)eal (D)ata (S)tructure parameter file +# (c) copyright 1992 Laboratory UPMC/MASI/CAO-VLSI +# all rights reserved +# e-mail : cao-vlsi@masi.ibp.fr +# +# file : cmos.rds +# version : 12 +# last modif : Apr 4, 2002 +# +##------------------------------------------------------------------- +# Symbolic to micron on a 'one lambda equals one micron' basis +##------------------------------------------------------------------- +# Refer to the documentation for more precise information. +#===================================================================== +# 01/11/09 ALU5/6 pitch 10 +# +# 99/11/3 ALU5/6 rules +# . theses rules are preliminary rules, we hope that they wil change +# in future. For now, ALU5/6 are dedicated to supplies an clock. +# +# 99/3/22 new symbolics rules +# . ALU1 width remains 1, ALU2/3/4 is 2 +# . ALU1/2/3/4 distance (edge to edge) is now 3 for all +# . GATE to GATE distance is 3 but POLY wire to POLY wire remains 2 +# . All via stacking are allowed +# +# 98/12/1 drc rules were updated +# distance VIA to POLY or gate is one rather 2 +# VIA2 and ALU3 appeared +# . ALU3 width is 3 +# . ALU2/VIA2/ALU3 is resp. 3/1/3 +# . ALU3 edge distance is 2 +# . stacked VIA/VIA2 is allowed +# . if they are not stacked they must distant of 2 +# . CONT/VIA2 is free +# note +# . stacked CONT/VIA is always not allowed +# NWELL is automatically drawn with the DIFN and NTIE layers +#===================================================================== + +##------------------------------------------------------------------- +# PHYSICAL_GRID : +##------------------------------------------------------------------- + +DEFINE PHYSICAL_GRID .5 + +##------------------------------------------------------------------- +# LAMBDA : +##------------------------------------------------------------------- + +DEFINE LAMBDA 1 + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_SEGMENT : +# +# MBK RDS layer 1 RDS layer 2 +# name name TRANS DLR DWR OFFSET name TRANS DLR DWR OFFSET ... +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_SEGMENT + + PWELL RDS_PWELL VW 0.0 0.0 0.0 EXT + NWELL RDS_NWELL VW 0.0 0.0 0.0 ALL + NDIF RDS_NDIF VW 0.5 0.0 0.0 ALL + PDIF RDS_PDIF VW 0.5 0.0 0.0 ALL \ + RDS_NWELL VW 1.0 1.0 0.0 ALL + NTIE RDS_NTIE VW 0.5 0.0 0.0 ALL \ + RDS_NWELL VW 1.0 1.0 0.0 ALL + PTIE RDS_PTIE VW 0.5 0.0 0.0 ALL + NTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \ + RDS_NDIF LCW -1.5 2.0 0.0 EXT \ + RDS_NDIF RCW -1.5 2.0 0.0 EXT \ + RDS_NDIF VW -1.5 4.0 0.0 DRC \ + RDS_ACTIV VW -1.5 5.0 0.0 ALL \ + RDS_PWELL VW -1.5 0.0 0.0 EXT + PTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \ + RDS_PDIF LCW -1.5 2.0 0.0 EXT \ + RDS_PDIF RCW -1.5 2.0 0.0 EXT \ + RDS_PDIF VW -1.5 4.0 0.0 DRC \ + RDS_ACTIV VW -1.5 5.0 0.0 ALL \ + RDS_NWELL VW -1.0 5.0 0.0 ALL + POLY RDS_POLY VW 0.5 0.0 0.0 ALL + POLY2 RDS_POLY2 VW 0.5 0.0 0.0 ALL + ALU1 RDS_ALU1 VW 0.5 0.0 0.0 ALL + ALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL + ALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL + ALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL + ALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL + ALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL + CALU1 RDS_ALU1 VW 1.0 0.0 0.0 ALL + CALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL + CALU3 RDS_ALU3 VW 1.0 0.0 0.0 ALL + CALU4 RDS_ALU4 VW 1.0 0.0 0.0 ALL + CALU5 RDS_ALU5 VW 1.0 0.0 0.0 ALL + CALU6 RDS_ALU6 VW 1.0 0.0 0.0 ALL + TPOLY RDS_TPOLY VW 0.5 0.0 0.0 ALL + TALU1 RDS_TALU1 VW 0.5 0.0 0.0 ALL + TALU2 RDS_TALU2 VW 1.0 0.0 0.0 ALL + TALU3 RDS_TALU3 VW 1.0 0.0 0.0 ALL + TALU4 RDS_TALU4 VW 1.0 0.0 0.0 ALL + TALU5 RDS_TALU5 VW 1.0 0.0 0.0 ALL + TALU6 RDS_TALU6 VW 1.0 0.0 0.0 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_CONNECTOR : +# +# MBK RDS layer +# name name DER DWR +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_CONNECTOR + + POLY RDS_POLY .5 0 + POLY2 RDS_POLY2 .5 0 + ALU1 RDS_ALU1 .5 0 + ALU2 RDS_ALU2 1.0 0 + ALU3 RDS_ALU3 1.0 0 + ALU4 RDS_ALU4 1.0 0 + ALU5 RDS_ALU5 1.0 0 + ALU6 RDS_ALU6 1.0 0 + CALU1 RDS_ALU1 .5 0 + CALU2 RDS_ALU2 1.0 0 + CALU3 RDS_ALU3 1.0 0 + CALU4 RDS_ALU4 1.0 0 + CALU5 RDS_ALU5 1.0 0 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_REFERENCE : +# +# MBK ref RDS layer +# name name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_REFERENCE + + REF_REF RDS_REF 1 + REF_CON RDS_VALU1 2 RDS_TVIA1 1 RDS_TALU2 2 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_VIA1 : +# +# MBK via RDS layer 1 RDS layer 2 RDS layer 3 RDS layer 4 +# name name width name width name width name width +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_VIA + + CONT_BODY_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PTIE 3 ALL + CONT_BODY_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NTIE 3 ALL RDS_NWELL 4 ALL + CONT_DIF_N RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_NDIF 3 ALL + CONT_DIF_P RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_PDIF 3 ALL RDS_NWELL 4 ALL + CONT_POLY RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY 3 ALL + CONT_POLY2 RDS_ALU1 2 ALL RDS_CONT 1 ALL RDS_POLY2 3 ALL + CONT_VIA RDS_ALU1 2 ALL RDS_VIA1 1 ALL RDS_ALU2 2 ALL + CONT_VIA2 RDS_ALU2 2 ALL RDS_VIA2 1 ALL RDS_ALU3 2 ALL + CONT_VIA3 RDS_ALU3 2 ALL RDS_VIA3 1 ALL RDS_ALU4 2 ALL + CONT_VIA4 RDS_ALU4 2 ALL RDS_VIA4 1 ALL RDS_ALU5 2 ALL + CONT_VIA5 RDS_ALU5 2 ALL RDS_VIA5 1 ALL RDS_ALU6 2 ALL + C_X_N RDS_POLY 1 ALL RDS_NDIF 5 ALL RDS_ACTIV 6 ALL + C_X_P RDS_POLY 1 ALL RDS_PDIF 5 ALL RDS_NWELL 6 ALL RDS_ACTIV 6 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_HOLE : +# +# MBK via RDS Hole +# name name side step mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_HOLE + +CONT_VIA RDS_VIA1 1 4 ALL +CONT_VIA2 RDS_VIA2 1 4 ALL +CONT_VIA3 RDS_VIA3 1 4 ALL +CONT_VIA4 RDS_VIA4 1 4 ALL # should be more than 4 +CONT_VIA5 RDS_VIA5 1 4 ALL # should be more than 4 + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_BIGVIA_METAL : +# +# MBK via RDS layer 1 ... +# name name delta-width overlap mode +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_BIGVIA_METAL + +CONT_VIA RDS_ALU1 0.0 0.5 ALL RDS_ALU2 0.0 0.5 ALL +CONT_VIA2 RDS_ALU2 0.0 0.5 ALL RDS_ALU3 0.0 0.5 ALL +CONT_VIA3 RDS_ALU3 0.0 0.5 ALL RDS_ALU4 0.0 0.5 ALL +CONT_VIA4 RDS_ALU4 0.0 0.5 ALL RDS_ALU5 0.0 0.5 ALL +CONT_VIA5 RDS_ALU5 0.0 0.5 ALL RDS_ALU6 0.0 0.5 ALL + +END + +##------------------------------------------------------------------- +# TABLE MBK_TO_RDS_TURNVIA : +# +# MBK via RDS layer 1 ... +# name name DWR MODE +##------------------------------------------------------------------- + +TABLE MBK_TO_RDS_TURNVIA + +CONT_TURN1 RDS_ALU1 0 ALL +CONT_TURN2 RDS_ALU2 0 ALL +CONT_TURN3 RDS_ALU3 0 ALL +CONT_TURN4 RDS_ALU4 0 ALL +CONT_TURN5 RDS_ALU5 0 ALL +CONT_TURN6 RDS_ALU6 0 ALL + +END + + +##------------------------------------------------------------------- +# TABLE LYNX_GRAPH : +# +# RDS layer Rds layer 1 Rds layer 2 ... +# name name name ... +##------------------------------------------------------------------- + +TABLE LYNX_GRAPH + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# RDS_NWELL RDS_NTIE RDS_NWELL +# RDS_PWELL RDS_PTIE RDS_PWELL +# RDS_NDIF RDS_CONT RDS_NDIF +# RDS_PDIF RDS_CONT RDS_PDIF +# RDS_NTIE RDS_CONT RDS_NTIE RDS_NWELL +# RDS_PTIE RDS_CONT RDS_PTIE RDS_PWELL + + RDS_NDIF RDS_CONT RDS_NDIF + RDS_PDIF RDS_CONT RDS_PDIF + RDS_NTIE RDS_CONT RDS_NTIE + RDS_PTIE RDS_CONT RDS_PTIE + + RDS_POLY RDS_CONT RDS_POLY + RDS_POLY2 RDS_CONT RDS_POLY2 + RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_CONT + RDS_ALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 RDS_ALU1 + RDS_VALU1 RDS_CONT RDS_VIA1 RDS_ALU1 RDS_VALU1 + RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 + RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 + RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 + RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 + RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 + RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2 + RDS_ALU3 RDS_VIA2 RDS_VIA3 RDS_ALU3 + RDS_ALU4 RDS_VIA3 RDS_VIA4 RDS_ALU4 + RDS_ALU5 RDS_VIA4 RDS_VIA5 RDS_ALU5 + RDS_ALU6 RDS_VIA5 RDS_ALU6 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_CAPA : +# +# RDS layer Surface capacitance Perimetric capacitance +# name piF / Micron^2 piF / Micron +##------------------------------------------------------------------- + +TABLE LYNX_CAPA + + RDS_POLY 1.00e-04 1.00e-04 + RDS_POLY2 1.00e-04 1.00e-04 + RDS_ALU1 0.50e-04 0.90e-04 + RDS_ALU2 0.25e-04 0.95e-04 + RDS_ALU3 0.25e-04 0.95e-04 + RDS_ALU4 0.25e-04 0.95e-04 + RDS_ALU5 0.25e-04 0.95e-04 + RDS_ALU6 0.25e-04 0.95e-04 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_RESISTOR : +# +# RDS layer Surface resistor +# name Ohm / Micron^2 +##------------------------------------------------------------------- + +TABLE LYNX_RESISTOR + + RDS_POLY 50.0 + RDS_POLY2 50.0 + RDS_ALU1 0.1 + RDS_ALU2 0.05 + RDS_ALU3 0.05 + RDS_ALU4 0.05 + RDS_ALU5 0.05 + RDS_ALU6 0.05 + +END + +##------------------------------------------------------------------- +# TABLE LYNX_TRANSISTOR : +# +# MBK layer Transistor Type MBK via +# name name name +##------------------------------------------------------------------- + +TABLE LYNX_TRANSISTOR + + NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL + PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL + +END + +##------------------------------------------------------------------- +# TABLE LYNX_DIFFUSION : +# +# RDS layer RDS layer +# name name +##------------------------------------------------------------------- + +TABLE LYNX_DIFFUSION +END + +##------------------------------------------------------------------- +# TABLE LYNX_BULK_IMPLICIT : +# +# RDS layer Bulk type +# name EXPLICIT/IMPLICIT +##------------------------------------------------------------------- + +TABLE LYNX_BULK_IMPLICIT + +##--------------------------- +# +# Modifie par L.Jacomme (Pb Bulk/Alim avec Lynx) +# 23.11.99 +# +# NWELL EXPLICIT +# PWELL IMPLICIT + +END + + + +##------------------------------------------------------------------- +# TABLE S2R_OVERSIZE_DENOTCH : +##------------------------------------------------------------------- + +TABLE S2R_OVERSIZE_DENOTCH +END + +##------------------------------------------------------------------- +# TABLE S2R_BLOC_RING_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_BLOC_RING_WIDTH +END + +##------------------------------------------------------------------- +# TABLE S2R_MINIMUM_LAYER_WIDTH : +##------------------------------------------------------------------- + +TABLE S2R_MINIMUM_LAYER_WIDTH + + RDS_NWELL 4 + RDS_PDIF 2 + RDS_NTIE 2 + RDS_PTIE 2 + RDS_POLY 1 + RDS_POLY2 1 + RDS_TPOLY 1 + RDS_CONT 1 + RDS_ALU1 1 + RDS_TALU1 1 + RDS_VIA1 1 + RDS_ALU2 2 + RDS_TALU2 2 + RDS_VIA2 1 + RDS_ALU3 2 + RDS_TALU3 2 + RDS_VIA3 1 + RDS_ALU4 2 + RDS_TALU4 2 + RDS_VIA4 1 + RDS_ALU5 2 + RDS_TALU5 2 + RDS_VIA5 1 + RDS_ALU6 2 + RDS_TALU6 2 + +END + +##------------------------------------------------------------------- +# TABLE MBK_WIRESETTING : +##------------------------------------------------------------------- +# +# This table is used by ocp, nero & ring. It supplies *symbolic* +# information about the routing grid, the cell gauge and the power +# wires. + + +TABLE MBK_WIRESETTING + + X_GRID 5 + Y_GRID 5 + Y_SLICE 50 + WIDTH_VDD 6 + WIDTH_VSS 6 + TRACK_WIDTH_ALU8 0 + TRACK_WIDTH_ALU7 2 + TRACK_WIDTH_ALU6 2 + TRACK_WIDTH_ALU5 2 + TRACK_WIDTH_ALU4 2 + TRACK_WIDTH_ALU3 2 + TRACK_WIDTH_ALU2 2 + TRACK_WIDTH_ALU1 2 + TRACK_SPACING_ALU8 0 + TRACK_SPACING_ALU7 8 + TRACK_SPACING_ALU6 8 + TRACK_SPACING_ALU5 3 + TRACK_SPACING_ALU4 3 + TRACK_SPACING_ALU3 3 + TRACK_SPACING_ALU2 3 + TRACK_SPACING_ALU1 3 + +END + + +##------------------------------------------------------------------- +# TABLE CIF_LAYER : +##------------------------------------------------------------------- + +TABLE CIF_LAYER + + RDS_NWELL LNWELL + RDS_NDIF LNDIF + RDS_PDIF LPDIF + RDS_NTIE LNTIE + RDS_PTIE LPTIE + RDS_POLY LPOLY + RDS_POLY2 LPOLY2 + RDS_TPOLY LTPOLY + RDS_CONT LCONT + RDS_ALU1 LALU1 + RDS_VALU1 LVALU1 + RDS_TALU1 LTALU1 + RDS_VIA1 LVIA + RDS_TVIA1 LTVIA1 + RDS_ALU2 LALU2 + RDS_TALU2 LTALU2 + RDS_VIA2 LVIA2 + RDS_ALU3 LALU3 + RDS_TALU3 LTALU3 + RDS_VIA3 LVIA3 + RDS_ALU4 LALU4 + RDS_TALU4 LTALU4 + RDS_VIA4 LVIA4 + RDS_ALU5 LALU5 + RDS_TALU5 LTALU5 + RDS_VIA5 LVIA5 + RDS_ALU6 LALU6 + RDS_TALU6 LTALU6 + RDS_REF LREF + +END + +##------------------------------------------------------------------- +# TABLE GDS_LAYER : +##------------------------------------------------------------------- + +TABLE GDS_LAYER + + RDS_NWELL 1 + RDS_NDIF 3 + RDS_PDIF 4 + RDS_NTIE 5 + RDS_PTIE 6 + RDS_POLY 7 + RDS_POLY2 8 + RDS_TPOLY 9 + RDS_CONT 10 + RDS_ALU1 11 11 + RDS_VALU1 12 + RDS_TALU1 13 + RDS_VIA1 14 + RDS_TVIA1 15 + RDS_ALU2 16 16 + RDS_TALU2 17 + RDS_VIA2 18 + RDS_ALU3 19 19 + RDS_TALU3 20 + RDS_VIA3 21 + RDS_ALU4 22 22 + RDS_TALU4 23 + RDS_VIA4 25 + RDS_ALU5 26 26 + RDS_TALU5 27 + RDS_VIA5 28 + RDS_ALU6 29 29 + RDS_TALU6 30 + RDS_REF 24 + +END + +##------------------------------------------------------------------- +# TABLE S2R_POST_TREAT : +##------------------------------------------------------------------- + +TABLE S2R_POST_TREAT + +END +DRC_RULES + +layer RDS_NWELL 4.; +layer RDS_NTIE 2.; +layer RDS_PTIE 2.; +layer RDS_NDIF 2.; +layer RDS_PDIF 2.; +layer RDS_ACTIV 2.; +layer RDS_CONT 1.; +layer RDS_VIA1 1.; +layer RDS_VIA2 1.; +layer RDS_VIA3 1.; +layer RDS_VIA4 1.; +layer RDS_VIA5 1.; +layer RDS_POLY 1.; +layer RDS_POLY2 1.; +layer RDS_ALU1 1.; +layer RDS_ALU2 2.; +layer RDS_ALU3 2.; +layer RDS_ALU4 2.; +layer RDS_ALU5 2.; +layer RDS_ALU6 2.; +layer RDS_USER0 1.; +layer RDS_USER1 1.; +layer RDS_USER2 1.; + +regles + +# Note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# There is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# There is no rule to check NTIE and PDIF are included in NWELL +# since this is necessarily true +#----------------------------------------------------------- + +# Check the NWELL shapes +#----------------------- +caracterise RDS_NWELL ( + regle 1 : largeur >= 4. ; + regle 2 : longueur_inter min 4. ; + regle 3 : notch >= 12. ; +); +relation RDS_NWELL , RDS_NWELL ( + regle 4 : distance axiale min 12. ; +); + +# Check RDS_PTIE is really excluded outside NWELL +#------------------------------------------------ +relation RDS_PTIE , RDS_NWELL ( + regle 5 : distance axiale >= 7.5; + regle 6 : enveloppe longueur_inter < 0. ; + regle 7 : marge longueur_inter < 0. ; + regle 8 : croix longueur_inter < 0. ; + regle 9 : intersection longueur_inter < 0. ; + regle 10 : extension longueur_inter < 0. ; + regle 11 : inclusion longueur_inter < 0. ; +); + +# Check RDS_NDIF is really excluded outside NWELL +#------------------------------------------------ +relation RDS_NDIF , RDS_NWELL ( + regle 12 : distance axiale >= 7.5; + regle 13 : enveloppe longueur_inter < 0. ; + regle 14 : marge longueur_inter < 0. ; + regle 15 : croix longueur_inter < 0. ; + regle 16 : intersection longueur_inter < 0. ; + regle 17 : extension longueur_inter < 0. ; + regle 18 : inclusion longueur_inter < 0. ; +); + +# Check the RDS_PDIF shapes +#-------------------------- +caracterise RDS_PDIF ( + regle 19 : largeur >= 2. ; + regle 20 : longueur_inter min 2. ; + regle 21 : notch >= 3. ; +); +relation RDS_PDIF , RDS_PDIF ( + regle 22 : distance axiale min 3. ; +); + +# Check the RDS_NDIF shapes +#-------------------------- +caracterise RDS_NDIF ( + regle 23 : largeur >= 2. ; + regle 24 : longueur_inter min 2. ; + regle 25 : notch >= 3. ; +); +relation RDS_NDIF , RDS_NDIF ( + regle 26 : distance axiale min 3. ; +); + +# Check the RDS_PTIE shapes +#-------------------------- +caracterise RDS_PTIE ( + regle 27 : largeur >= 2. ; + regle 28 : longueur_inter min 2. ; + regle 29 : notch >= 3. ; +); +relation RDS_PTIE , RDS_PTIE ( + regle 30 : distance axiale min 3. ; +); + +# Check the RDS_NTIE shapes +#-------------------------- +caracterise RDS_NTIE ( + regle 31 : largeur >= 2. ; + regle 32 : longueur_inter min 2. ; + regle 33 : notch >= 3. ; +); +relation RDS_NTIE , RDS_NTIE ( + regle 34 : distance axiale min 3. ; +); + +define RDS_PDIF , RDS_PTIE union -> ANY_P_DIF; +define RDS_NDIF , RDS_NTIE union -> ANY_N_DIF; + +# Check the ANY_N_DIF ANY_P_DIFF exclusion +#-------------------------------------- +relation ANY_N_DIF , ANY_P_DIF ( + regle 35 : distance axiale >= 3. ; + regle 36 : enveloppe longueur_inter < 0. ; + regle 37 : marge longueur_inter < 0. ; + regle 38 : croix longueur_inter < 0. ; + regle 39 : intersection longueur_inter < 0. ; + regle 40 : extension longueur_inter < 0. ; + regle 41 : inclusion longueur_inter < 0. ; +); + +undefine ANY_P_DIF; +undefine ANY_N_DIF; + +define RDS_NDIF , RDS_PDIF union -> NP_DIF; + +# Check RDS_POLY related to NP_DIF +#--------------------------------- +relation RDS_POLY , NP_DIF ( + regle 42 : distance axiale >= 1. ; + regle 43 : intersection longueur_inter < 0. ; +); + +define NP_DIF , RDS_POLY intersection -> CHANNEL; + +# Check the RDS_POLY shapes +#-------------------------- +caracterise RDS_POLY ( + regle 44 : largeur >= 1. ; + regle 45 : longueur_inter min 1. ; + regle 46 : notch >= 2. ; +); +relation RDS_POLY , RDS_POLY ( + regle 47 : distance axiale min 2.; +); + +define NP_DIF , RDS_CONT intersection -> CONT_DIFF; +# Check the CHANNEL shapes +#-------------------------- +caracterise CHANNEL ( + regle 48 : notch >= 3. ; +); +relation CHANNEL , CHANNEL ( + regle 49 : distance axiale min 3.; +); + +undefine CHANNEL; + +# Check RDS_POLY is distant from ACTIV ZONE of TRANSISTOR +#-------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + regle 79 : distance axiale >= 1. ; +); + +relation RDS_POLY , CONT_DIFF ( + regle 50 : distance axiale >= 2. ; +); + +undefine CONT_DIFF; +undefine NP_DIF; + + +# Check RDS_ALU1 shapes +#---------------------- +caracterise RDS_ALU1 ( + regle 51 : largeur >= 1. ; + regle 52 : longueur_inter min 1. ; + regle 53 : notch >= 3. ; +); +relation RDS_ALU1 , RDS_ALU1 ( + regle 54 : distance axiale min 3. ; +); + +# Check RDS_ALU2 shapes +#---------------------- +caracterise RDS_ALU2 ( + regle 55 : largeur >= 2. ; + regle 56 : longueur_inter min 2. ; + regle 57 : notch >= 3. ; +); +relation RDS_ALU2 , RDS_ALU2 ( + regle 58 : distance axiale min 3. ; +); + +# Check RDS_ALU3 shapes +#---------------------- +caracterise RDS_ALU3 ( + regle 59 : largeur >= 2. ; + regle 60 : longueur_inter min 2. ; + regle 61 : notch >= 3. ; +); +relation RDS_ALU3 , RDS_ALU3 ( + regle 62 : distance axiale min 3. ; +); + +# Check RDS_ALU4 shapes +#---------------------- +caracterise RDS_ALU4 ( + regle 63 : largeur >= 2. ; + regle 64 : longueur_inter min 2. ; + regle 65 : notch >= 3. ; +); +relation RDS_ALU4 , RDS_ALU4 ( + regle 66 : distance axiale min 3. ; +); + +# Check RDS_ALU5 shapes +#---------------------- +caracterise RDS_ALU5 ( + regle 80 : largeur >= 2. ; + regle 81 : longueur_inter min 2. ; + regle 82 : notch >= 3. ; +); +relation RDS_ALU5 , RDS_ALU5 ( + regle 83 : distance axiale min 3. ; +); + +# Check RDS_ALU6 shapes +#---------------------- +caracterise RDS_ALU6 ( + regle 84 : largeur >= 2. ; + regle 85 : longueur_inter min 2. ; + regle 86 : notch >= 3. ; +); +relation RDS_ALU6 , RDS_ALU6 ( + regle 87 : distance axiale min 3. ; +); + +# Check ANY_VIA layers, stacking are free +#---------------------------------------- +relation RDS_CONT , RDS_CONT ( + regle 67 : distance axiale >= 3. ; +); +relation RDS_VIA , RDS_VIA ( + regle 68 : distance axiale >= 4. ; +); +relation RDS_VIA2 , RDS_VIA2 ( + regle 69 : distance axiale >= 4. ; +); +relation RDS_VIA3 , RDS_VIA3 ( + regle 70 : distance axiale >= 4. ; +); +relation RDS_VIA4 , RDS_VIA4 ( + regle 88 : distance axiale >= 4. ; +); +relation RDS_VIA5 , RDS_VIA5 ( + regle 89 : distance axiale >= 4. ; +); +caracterise RDS_CONT ( + regle 71 : largeur >= 1. ; + regle 72 : longueur <= 1. ; +); +caracterise RDS_VIA ( + regle 73 : largeur >= 1. ; + regle 74 : longueur <= 1. ; +); +caracterise RDS_VIA2 ( + regle 75 : largeur >= 1. ; + regle 76 : longueur <= 1. ; +); +caracterise RDS_VIA3 ( + regle 77 : largeur >= 1. ; + regle 78 : longueur <= 1. ; +); +caracterise RDS_VIA4 ( + regle 90 : largeur >= 1. ; + regle 91 : longueur <= 1. ; +); +caracterise RDS_VIA5 ( + regle 92 : largeur >= 1. ; + regle 93 : longueur <= 1. ; +); + +# Check the POLY2 shapes +#----------------------- +caracterise RDS_POLY2 ( + regle 94 : largeur >= 1. ; + regle 95 : longueur_inter min 1. ; + regle 96 : notch >= 5. ; +); +relation RDS_POLY2 , RDS_POLY2 ( + regle 97 : distance axiale min 5. ; +); + +# Check RDS_POLY2 is really included inside RDS_POLY1 +#---------------------------------------------------- +relation RDS_POLY , RDS_POLY2 ( + regle 98 : distance axiale < 0.; + regle 99 : enveloppe inferieure min 5. ; + regle 100 : marge longueur_inter < 0. ; + regle 101 : croix longueur_inter < 0. ; + regle 102 : intersection longueur_inter < 0. ; + regle 103 : extension longueur_inter < 0. ; + regle 104 : inclusion longueur_inter < 0. ; +); + + +fin regles +DRC_COMMENT +1 (RDS_NWELL) minimum width 4. +2 (RDS_NWELL) minimum width 4. +3 (RDS_NWELL) Manhatan distance min 12. +4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 12. +5 (RDS_PTIE,RDS_NWELL) Manhatan distance min 7.5 +6 (RDS_PTIE,RDS_NWELL) must never been in contact +7 (RDS_PTIE,RDS_NWELL) must never been in contact +8 (RDS_PTIE,RDS_NWELL) must never been in contact +9 (RDS_PTIE,RDS_NWELL) must never been in contact +10 (RDS_PTIE,RDS_NWELL) must never been in contact +11 (RDS_PTIE,RDS_NWELL) must never been in contact +12 (RDS_NDIF,RDS_NWELL) Manhatan distance min 7.5 +13 (RDS_NDIF,RDS_NWELL) must never been in contact +14 (RDS_NDIF,RDS_NWELL) must never been in contact +15 (RDS_NDIF,RDS_NWELL) must never been in contact +16 (RDS_NDIF,RDS_NWELL) must never been in contact +17 (RDS_NDIF,RDS_NWELL) must never been in contact +18 (RDS_NDIF,RDS_NWELL) must never been in contact +19 (RDS_PDIF) minimum width 2. +20 (RDS_PDIF) minimum width 2. +21 (RDS_PDIF) Manhatan distance min 3. +22 (RDS_PDIF,RDS_PDIF) Manhatan distance min 3. +23 (RDS_NDIF) minimum width 2. +24 (RDS_NDIF) minimum width 2. +25 (RDS_NDIF) Manhatan distance min 3. +26 (RDS_NDIF,RDS_NDIF) Manhatan distance min 3. +27 (RDS_PTIE) minimum width 2. +28 (RDS_PTIE) minimum width 2. +29 (RDS_PTIE) Manhatan distance min 3. +30 (RDS_PTIE,RDS_PTIE) Manhatan distance min 3. +31 (RDS_NTIE) minimum width 2. +32 (RDS_NTIE) minimum width 2. +33 (RDS_NTIE) Manhatan distance min 3. +34 (RDS_NTIE,RDS_NTIE) Manhatan distance min 3. +35 (ANY_N_DIF,ANY_P_DIF) Manhatan distance min 3. +36 (ANY_N_DIF,ANY_P_DIF) must never been in contact +37 (ANY_N_DIF,ANY_P_DIF) must never been in contact +38 (ANY_N_DIF,ANY_P_DIF) must never been in contact +39 (ANY_N_DIF,ANY_P_DIF) must never been in contact +40 (ANY_N_DIF,ANY_P_DIF) must never been in contact +41 (ANY_N_DIF,ANY_P_DIF) must never been in contact +42 (RDS_POLY,ANY_N_DIF) Manhatan distance min 1. +43 (RDS_POLY,NP_DIF) bad intersection +44 (RDS_POLY) minimum width 1. +45 (RDS_POLY) minimum width 1. +46 (RDS_POLY) Manhatan distance min 2. +47 (RDS_POLY,RDS_POLY) Manhatan distance min 2. +48 (CHANNEL) Manhatan distance min 3. +49 (CHANNEL,CHANNEL) Manhatan distance min 3. +50 (RDS_POLY,CONT_DIFF) Manhatan distance min 2. +51 (RDS_ALU1) minimum width 1. +52 (RDS_ALU1) minimum width 1. +53 (RDS_ALU1) Manhatan distance min 3. +54 (RDS_ALU1,RDS_ALU1) Manhatan distance min 3. +55 (RDS_ALU2) minimum width 2. +56 (RDS_ALU2) minimum width 2. +57 (RDS_ALU2) Manhatan distance min 3. +58 (RDS_ALU2,RDS_ALU2) Manhatan distance min 3. +59 (RDS_ALU3) minimum width 2. +60 (RDS_ALU3) minimum width 2. +61 (RDS_ALU3) Manhatan distance min 3. +62 (RDS_ALU3,RDS_ALU3) Manhatan distance min 3. +63 (RDS_ALU4) minimum width 2. +64 (RDS_ALU4) minimum width 2. +65 (RDS_ALU4) Manhatan distance min 3. +66 (RDS_ALU4,RDS_ALU4) Manhatan distance min 3. +67 (RDS_CONT,RDS_CONT) Manhatan distance min 3. +68 (RDS_VIA,RDS_VIA) Manhatan distance min 4. +69 (RDS_VIA2,RDS_VIA2) Manhatan distance min 4. +70 (RDS_VIA3,RDS_VIA3) Manhatan distance min 4. +71 (RDS_CONT) minimum width 1. +72 (RDS_CONT) maximum length 1. +73 (RDS_VIA) minimum width 1. +74 (RDS_VIA) maximum length 1. +75 (RDS_VIA2) minimum width 1. +76 (RDS_VIA2) maximum length 1. +77 (RDS_VIA3) minimum width 1. +78 (RDS_VIA3) maximum length 1. +79 (RDS_POLY,RDS_ACTIV) Manhatan distance min 1. +80 (RDS_ALU5) minimum width 2. +81 (RDS_ALU5) minimum width 2. +82 (RDS_ALU5) Manhatan distance min 4. +83 (RDS_ALU5,RDS_ALU5) Manhatan distance min 4. +84 (RDS_ALU6) minimum width 2. +85 (RDS_ALU6) minimum width 2. +86 (RDS_ALU6) Manhatan distance min 4. +87 (RDS_ALU6,RDS_ALU6) Manhatan distance min 4. +88 (RDS_VIA4,RDS_VIA4) Manhatan distance min 4. +89 (RDS_VIA5,RDS_VIA5) Manhatan distance min 4. +90 (RDS_VIA4) minimum width 1. +91 (RDS_VIA4) maximum length 1. +92 (RDS_VIA5) minimum width 1. +93 (RDS_VIA5) maximum length 1. +94 (RDS_POLY2) minimum width 1. +95 (RDS_POLY2) minimum width 1. +96 (RDS_POLY2) Manhatan distance min 5. +97 (RDS_POLY2,POLY2) Manhatan distance min 5. +98 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +99 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +100 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +101 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +102 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +103 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +104 (RDS_POLY,RDS_POLY2) POLY2 must be enclosed by POLY of 5. +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/sxlib/cmos_sx/libs.tech/coriolis/cmos_sx/techno.py b/pdks/symbolic/sxlib/cmos_sx/libs.tech/coriolis/cmos_sx/techno.py new file mode 100644 index 000000000..ae4cb82fa --- /dev/null +++ b/pdks/symbolic/sxlib/cmos_sx/libs.tech/coriolis/cmos_sx/techno.py @@ -0,0 +1,63 @@ +import os + +# Coriolis imports +from coriolis.designflow.technos import Where +from coriolis.designflow.task import ShellEnv +from coriolis.designflow.yosys import Yosys + +# Imports from Coriolis C++ bindings +from coriolis import Cfg +from coriolis import Viewer +from coriolis import CRL +from coriolis.helpers import overlay + +# Imports from PDKs +from pdks import symbolic +from pdks import cmos_sx + + +__all__ = [ "setup" ] + + +def setup( checkToolkit=None ): + Where( checkToolkit ) + ShellEnv().export() + + with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.misc.minTraceLevel = 1900 + cfg.misc.maxTraceLevel = 3000 + cfg.katana.eventsLimit = 1000000 + cfg.katana.termSatReservedLocal = 6 + cfg.katana.termSatThreshold = 9 + + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + af = CRL.AllianceFramework.get() + env = af.getEnvironment() + + env.setCLOCK( '^ck$|m_clock|^clk' ) + + env.addSYSTEM_LIBRARY( library=(symbolic.path / 'cells' / 'niolib' ).as_posix() + , mode=CRL.Environment.Append ) + + env.addSYSTEM_LIBRARY( library=(symbolic.path / 'cells' / 'sxlib' ).as_posix() + , mode=CRL.Environment.Append ) + + alliance_bin = (Where.allianceTop / 'bin').as_posix() + for env_var in ['PATH', 'path']: + if env_var in os.environ: + paths = os.environ[env_var].split(os.pathsep) + if alliance_bin not in paths: + paths.append(alliance_bin) + os.environ[env_var] = os.pathsep.join(paths) + + Yosys.setLiberty( symbolic.path / 'cells' / 'sxlib' / 'sxlib.lib' ) + + ShellEnv.RDS_TECHNO_NAME = cmos_sx.path / 'cmos_sx' / 'cmos.rds' diff --git a/pdks/symbolic/sxlib/cmos_sx/meson.build b/pdks/symbolic/sxlib/cmos_sx/meson.build new file mode 100644 index 000000000..6c897c209 --- /dev/null +++ b/pdks/symbolic/sxlib/cmos_sx/meson.build @@ -0,0 +1,25 @@ + +project( + 'pdk_cmos_sx', + version: '0.1.0', + meson_version: '>= 1.2.0', + default_options: ['warning_level=3'] +) + +python = import('python') +py = python.find_installation('python3') +py_deps = py.dependency() + +pdks_dir = py.get_install_dir() / 'pdks' / 'cmos_sx' + +py_files = [ + 'libs.tech/coriolis/cmos_sx/__init__.py', + 'libs.tech/coriolis/cmos_sx/techno.py' +] + +data_files = [ + 'libs.tech/coriolis/cmos_sx/cmos.rds', +] + +py.install_sources( files(py_files), subdir: 'pdks/cmos_sx' ) +py.install_sources( files(data_files), subdir: 'pdks/cmos_sx' ) diff --git a/pdks/symbolic/sxlib/cmos_sx/pyproject.toml b/pdks/symbolic/sxlib/cmos_sx/pyproject.toml new file mode 100644 index 000000000..ceb5c780f --- /dev/null +++ b/pdks/symbolic/sxlib/cmos_sx/pyproject.toml @@ -0,0 +1,25 @@ +[project] +name = "pdk_cmos_sx" +version = "0.1.0" +description = "CMOS sxlib PDK for Coriolis EDA" +authors = [ { name = "Coriolis EDA Contributers" } ] +requires-python = ">= 3.8" + +[build-system] +requires = [ + "meson", + "meson-python", + "ninja", + "setuptools", + "cibuildwheel", + "build", + "pdm-backend" +] +build-backend = "mesonpy" + +[tool.meson] +build-dir = "build" + +[tool.cibuildwheel] +build = "cp310-*" +skip = ["cp36-*", "cp37-*", "pp*"] diff --git a/pdks/symbolic/vsclib/cells/CATAL b/pdks/symbolic/vsclib/cells/CATAL new file mode 100644 index 000000000..951307301 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/CATAL @@ -0,0 +1,117 @@ +an2v0x05 C +an2v0x1 C +an2v0x4 C +an2v0x8 C +an3v0x05 C +an3v0x1 C +an3v0x2 C +an3v6x05 C +an4v0x05 C +aoi112v0x05 C +aoi211v0x05 C +aoi211v0x1 C +aoi211v0x2 C +aoi211v5x05 C +aoi21a2bv0x05 C +aoi21a2bv5x05 C +aoi21a2v0x05 C +aoi21bv0x05 C +aoi21v0x05 C +aoi22v0x05 C +aoi22v0x1 C +aoi22v5x05 C +aoi31v0x05 C +aoi31v0x1 C +aoi31v0x2 C +aon21bv0x05 C +aon21bv0x1 C +aon21bv0x2 C +aon21v0x05 C +bf1v0x05 C +bf1v0x1 C +bf1v0x12 C +bf1v0x2 C +bf1v0x4 C +bf1v0x8 C +bf1v5x05 C +dfnt1v0x2 C +dly1v0x05 C +dly2v0x05 C +iv1v0x05 C +iv1v1x05 C +lant1v0x05 C +mxi2v0x05 C +mxi2v0x2 C +mxn2v0x05 C +nd2abv0x05 C +nd2av0x05 C +nd2av0x1 C +nd2av0x2 C +nd2av0x4 C +nd2v0x05 C +nd2v0x1 C +nd2v0x2 C +nd2v0x4 C +nd2v3x05 C +nd2v5x05 C +nd3abv0x05 C +nd3av0x05 C +nd3v0x05 C +nd3v0x1 C +nd4v0x05 C +nd4v0x1 C +nd4v0x2 C +nr2av0x1 C +nr2av0x2 C +nr2av0x4 C +nr2av1x05 C +nr2v0x05 C +nr2v0x1 C +nr2v0x4 C +nr2v1x05 C +nr3abv0x05 C +nr3av0x05 C +nr3v0x05 C +nr3v0x1 C +nr3v0x2 C +nr3v0x4 C +nr3v1x05 C +nr4v0x1 C +nr4v0x2 C +nr4v1x05 C +oai211v0x05 C +oai21a2bv0x05 C +oai21a2v0x05 C +oai21bv0x05 C +oai21v0x05 C +oai21v0x1 C +oai21v0x4 C +oai22v0x05 C +oai23av0x05 C +oai31v0x05 C +oai31v0x1 C +oan21bv0x05 C +oan21v0x05 C +or2v0x05 C +or2v0x1 C +or3v0x05 C +or3v0x1 C +or3v0x2 C +or3v4x05 C +or4v0x05 C +or4v4x05 C +rowend_x0 C +rowend_x0 F +tie_x0 C +tie_x0 F +vddtie C +vsstie C +xaon21v0x05 C +xnr2v8x05 C +xnr3v1x05 C +xoon21v0x05 C +xor2v0x05 C +xor2v1x05 C +xor2v2x05 C +xor2v8x05 C +xor3v1x05 C diff --git a/pdks/symbolic/vsclib/cells/an2v0x05.ap b/pdks/symbolic/vsclib/cells/an2v0x05.ap new file mode 100755 index 000000000..e4ac59823 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an2v0x05.ap @@ -0,0 +1,81 @@ +V ALLIANCE : 6 +H an2v0x05,P,22/ 6/2024,100 +A 0,0,4000,7200 +R 2000,4800,ref_ref,a_48 +R 3600,3200,ref_ref,b_32 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 3600,2400,ref_ref,b_24 +R 2800,5600,ref_ref,a_56 +R 2800,2400,ref_ref,b_24 +R 2000,5600,ref_ref,a_56 +R 1200,1600,ref_ref,z_16 +S 400,6400,2200,6400,200,*,RIGHT,ALU1 +S 2900,2200,2900,2600,200,*,DOWN,POLY +S 3000,2400,3000,3800,200,*,UP,POLY +S 1500,4000,1500,4800,400,*,UP,PDIF +S 2000,3300,2200,3300,200,*,LEFT,POLY +S 2000,3400,2200,3400,200,*,LEFT,POLY +S 3000,3800,3000,4800,200,t03,UP,PTRANS +S 3000,4800,3000,5200,200,*,UP,POLY +S 1100,3200,2600,3200,400,*,RIGHT,ALU1 +S 2500,3200,2500,4100,600,*,UP,ALU1 +S 2000,4800,2000,5500,200,*,UP,POLY +S 2000,3800,2000,4800,200,t01,UP,PTRANS +S 2000,3300,2000,3800,200,*,UP,POLY +S 2000,1500,2000,3200,400,*,UP,ALU1 +S 2700,2300,3600,2300,400,*,RIGHT,ALU1 +S 2700,2400,3600,2400,400,*,RIGHT,ALU1 +S 1000,2100,1000,3800,200,*,UP,POLY +S 2200,1800,2200,3400,200,*,UP,POLY +S 600,6600,3400,6600,600,*,RIGHT,NTIE +S 1000,5000,1000,5400,200,*,UP,POLY +S 2000,4800,2000,5700,600,*,DOWN,ALU1 +S 1900,5600,2800,5600,600,*,RIGHT,ALU1 +S 3600,4000,3600,4600,400,*,UP,PDIF +S 3500,4400,3500,6800,400,*,DOWN,ALU1 +S 2000,4800,2000,5600,400,a,UP,CALU1 +S 1200,4100,1200,6800,400,*,UP,ALU1 +S 500,4000,500,4200,400,*,UP,ALU1 +S 1000,3800,1000,5000,200,t05,UP,PTRANS +S 1200,4100,1600,4100,400,*,RIGHT,ALU1 +S 2800,2400,2800,2400,400,b,LEFT,CALU1 +S 3600,2400,3600,3200,400,b,UP,CALU1 +S 3600,2300,3600,3300,400,*,UP,ALU1 +S 500,1500,500,1900,400,*,UP,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,1600,1200,1600,600,*,RIGHT,ALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 2900,900,2900,1800,200,t04,UP,NTRANS +S 2900,500,2900,900,200,*,UP,POLY +S 2800,5600,2800,5600,400,a,LEFT,CALU1 +S 2500,1100,2500,1600,400,n1,UP,NDIF +S 2200,900,2200,1800,200,t02,UP,NTRANS +S 2200,500,2200,900,200,*,UP,POLY +S 2000,1500,3500,1500,400,*,RIGHT,ALU1 +S 1600,500,1600,1900,600,*,UP,NDIF +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1000,1500,1000,2100,200,t06,UP,NTRANS +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 0,6800,4000,6800,800,*,RIGHT,ALU1 +S 0,5400,4000,5400,4400,*,RIGHT,NWELL +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,400,4000,400,800,*,RIGHT,ALU1 +V 2000,6600,CONT_BODY_N,* +V 2500,4100,CONT_DIF_P,zn +V 2200,5600,CONT_POLY,* +V 3400,6600,CONT_BODY_N,* +V 3500,4500,CONT_DIF_P,* +V 500,4100,CONT_DIF_P,* +V 1500,4100,CONT_DIF_P,* +V 600,6600,CONT_BODY_N,* +V 600,600,CONT_BODY_P,* +V 500,1800,CONT_DIF_N,* +V 3400,1500,CONT_DIF_N,zn +V 3100,2400,CONT_POLY,* +V 1600,600,CONT_DIF_N,* +V 1200,3200,CONT_POLY,zn +EOF diff --git a/pdks/symbolic/vsclib/cells/an2v0x05.vbe b/pdks/symbolic/vsclib/cells/an2v0x05.vbe new file mode 100755 index 000000000..6d34f053b --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an2v0x05.vbe @@ -0,0 +1,32 @@ +ENTITY an2v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_b_z : NATURAL := 3860; + CONSTANT rdown_a_z : NATURAL := 3870; + CONSTANT rup_b_z : NATURAL := 4960; + CONSTANT rup_a_z : NATURAL := 4960; + CONSTANT tphh_a_z : NATURAL := 69; + CONSTANT tphh_b_z : NATURAL := 70; + CONSTANT tpll_b_z : NATURAL := 90; + CONSTANT tpll_a_z : NATURAL := 99; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an2v0x05; + +ARCHITECTURE behaviour_data_flow OF an2v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an2v0x05" + SEVERITY WARNING; + z <= (b and a) after 192 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/an2v0x1.ap b/pdks/symbolic/vsclib/cells/an2v0x1.ap new file mode 100755 index 000000000..a8158812a --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an2v0x1.ap @@ -0,0 +1,77 @@ +V ALLIANCE : 6 +H an2v0x1,P,17/ 2/2007,1000 +A 0,0,40000,72000 +R 12000,16000,ref_ref,z_16 +R 20000,32000,ref_ref,a_32 +R 28000,24000,ref_ref,a_24 +R 28000,32000,ref_ref,a_32 +R 28000,40000,ref_ref,b_40 +R 36000,48000,ref_ref,b_48 +R 4000,16000,ref_ref,z_16 +R 4000,24000,ref_ref,z_24 +R 4000,32000,ref_ref,z_32 +R 4000,40000,ref_ref,z_40 +R 4000,48000,ref_ref,z_48 +S 0,4000,40000,4000,8000,*,RIGHT,ALU1 +S 0,4000,40000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,40000,54000,44000,*,RIGHT,NWELL +S 0,68000,40000,68000,8000,*,RIGHT,ALU1 +S 0,68000,40000,68000,8000,vdd,RIGHT,CALU1 +S 10000,15000,10000,24000,2000,t06,UP,NTRANS +S 12000,16000,12000,16000,4000,z,LEFT,CALU1 +S 12000,24000,20000,24000,4000,*,RIGHT,ALU1 +S 16000,5000,16000,22000,6000,*,UP,NDIF +S 17000,5000,17000,22000,6000,*,UP,NDIF +S 19000,32000,29000,32000,4000,*,RIGHT,ALU1 +S 20000,16000,20000,24000,4000,*,UP,ALU1 +S 20000,16000,36000,16000,4000,*,RIGHT,ALU1 +S 20000,32000,20000,32000,4000,a,LEFT,CALU1 +S 23000,13000,23000,24000,2000,t02,UP,NTRANS +S 23000,24000,23000,32000,2000,*,UP,POLY +S 23000,9000,23000,13000,2000,*,UP,POLY +S 26000,15000,26000,22000,4000,n1,UP,NDIF +S 27000,40000,36000,40000,4000,*,RIGHT,ALU1 +S 28000,23000,28000,32000,4000,*,UP,ALU1 +S 28000,24000,28000,32000,4000,a,UP,CALU1 +S 28000,40000,28000,40000,4000,b,LEFT,CALU1 +S 29000,23000,29000,32000,4000,*,UP,ALU1 +S 30000,13000,30000,24000,2000,t04,UP,NTRANS +S 30000,46000,30000,59000,2000,t03,UP,PTRANS +S 30000,59000,30000,63000,2000,*,UP,POLY +S 30000,9000,30000,13000,2000,*,UP,POLY +S 35000,48000,35000,57000,6000,*,UP,PDIF +S 35000,56000,35000,68000,6000,*,UP,ALU1 +S 36000,40000,36000,49000,4000,*,UP,ALU1 +S 36000,48000,36000,48000,4000,b,LEFT,CALU1 +S 4000,16000,12000,16000,6000,*,RIGHT,ALU1 +S 4000,16000,4000,48000,4000,z,UP,CALU1 +S 5000,15000,5000,19000,4000,*,UP,ALU1 +S 20000,59000,20000,63000,2000,*,UP,POLY +S 20000,46000,20000,59000,2000,t01,UP,PTRANS +S 10000,39000,10000,57000,2000,t05,UP,PTRANS +S 15000,41000,15000,57000,4000,*,UP,PDIF +S 12000,24000,12000,47000,4000,*,UP,ALU1 +S 15000,54000,15000,68000,6000,*,UP,ALU1 +S 12000,47000,25000,47000,4000,*,RIGHT,ALU1 +S 25000,47000,25000,57000,4000,*,DOWN,ALU1 +S 5000,41000,5000,50000,6000,*,UP,PDIF +S 5000,41000,5000,50000,4000,*,UP,ALU1 +S 4000,15000,4000,50000,4000,*,UP,ALU1 +S 10000,24000,10000,39000,2000,*,UP,POLY +S 20000,32000,20000,46000,2000,*,UP,POLY +S 30000,24000,30000,46000,2000,*,UP,POLY +V 12000,32000,CONT_POLY,zn +V 16000,6000,CONT_DIF_N,* +V 22000,32000,CONT_POLY,* +V 25000,49000,CONT_DIF_P,zn +V 32000,40000,CONT_POLY,* +V 35000,16000,CONT_DIF_N,zn +V 35000,56000,CONT_DIF_P,* +V 5000,18000,CONT_DIF_N,* +V 6000,6000,CONT_BODY_P,* +V 6000,66000,CONT_BODY_N,* +V 15000,54000,CONT_DIF_P,* +V 25000,56000,CONT_DIF_P,zn +V 5000,42000,CONT_DIF_P,* +V 5000,49000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/an2v0x1.vbe b/pdks/symbolic/vsclib/cells/an2v0x1.vbe new file mode 100755 index 000000000..fd471b7fe --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an2v0x1.vbe @@ -0,0 +1,32 @@ +ENTITY an2v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 2570; + CONSTANT rdown_a_z : NATURAL := 2580; + CONSTANT rup_b_z : NATURAL := 3310; + CONSTANT rup_a_z : NATURAL := 3310; + CONSTANT tphh_a_z : NATURAL := 73; + CONSTANT tphh_b_z : NATURAL := 73; + CONSTANT tpll_b_z : NATURAL := 91; + CONSTANT tpll_a_z : NATURAL := 101; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an2v0x1; + +ARCHITECTURE behaviour_data_flow OF an2v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an2v0x1" + SEVERITY WARNING; + z <= (b and a) after 158 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/an2v0x4.ap b/pdks/symbolic/vsclib/cells/an2v0x4.ap new file mode 100755 index 000000000..ec5f62791 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an2v0x4.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H an2v0x4,P,22/ 6/2024,100 +A 0,0,5600,7200 +R 1200,1600,ref_ref,z_16 +R 1200,4800,ref_ref,z_48 +R 2800,3200,ref_ref,a_32 +R 3600,2400,ref_ref,a_24 +R 3600,4000,ref_ref,b_40 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,2400,ref_ref,a_24 +R 4400,3200,ref_ref,b_32 +R 4400,4000,ref_ref,b_40 +S 3200,3000,3200,3400,400,*,DOWN,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,3200,2100,3200,600,*,RIGHT,POLY +S 1000,3800,1000,6600,200,t06,UP,PTRANS +S 1100,1200,1100,2600,200,t08,UP,NTRANS +S 1100,800,1100,1200,200,*,UP,POLY +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1500,4800,1500,5700,400,*,UP,ALU1 +S 1700,2400,1700,4000,400,*,UP,ALU1 +S 1700,2400,2600,2400,400,*,RIGHT,ALU1 +S 1700,4000,2500,4000,400,*,RIGHT,ALU1 +S 2000,3800,2000,6600,200,t05,UP,PTRANS +S 2100,1200,2100,2600,200,t07,UP,NTRANS +S 2100,800,2100,1200,200,*,UP,POLY +S 2400,4000,2400,6400,600,*,UP,PDIF +S 2500,4000,2500,4800,400,*,UP,ALU1 +S 2500,4800,3500,4800,400,*,RIGHT,ALU1 +S 2500,5900,2500,6800,400,*,UP,ALU1 +S 2600,1600,2600,2400,400,*,UP,ALU1 +S 2600,1600,4600,1600,400,*,RIGHT,ALU1 +S 2700,1400,2700,2400,600,*,UP,NDIF +S 2700,3200,3500,3200,400,*,RIGHT,ALU1 +S 2700,400,2700,900,600,*,UP,ALU1 +S 2700,800,2700,2400,600,*,UP,NDIF +S 2800,3200,2800,3200,400,a,LEFT,CALU1 +S 3000,3300,3000,4500,200,*,UP,POLY +S 3000,3800,3000,6300,200,t01,UP,PTRANS +S 3000,6300,3000,6700,200,*,UP,POLY +S 3300,600,3300,2600,200,t02,UP,NTRANS +S 3500,2400,3500,3200,400,*,UP,ALU1 +S 3500,2400,4500,2400,400,*,RIGHT,ALU1 +S 3500,4000,4500,4000,400,*,RIGHT,ALU1 +S 3500,4800,3500,5700,400,*,UP,ALU1 +S 3600,2400,3600,2400,400,a,LEFT,CALU1 +S 3600,4000,3600,4000,400,b,LEFT,CALU1 +S 3600,800,3600,2400,400,n1,UP,NDIF +S 4000,3200,4500,3200,600,*,RIGHT,POLY +S 4000,3800,4000,6300,200,t03,UP,PTRANS +S 4000,600,4000,2600,200,t04,UP,NTRANS +S 4000,6300,4000,6700,200,*,UP,POLY +S 400,1500,1700,1500,400,*,RIGHT,ALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 400,1600,1700,1600,400,*,RIGHT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,4800,1500,4800,400,*,RIGHT,ALU1 +S 400,4900,1500,4900,400,*,RIGHT,ALU1 +S 4400,2400,4400,2400,400,a,LEFT,CALU1 +S 4400,3200,4400,4000,400,b,UP,CALU1 +S 4400,3200,4400,4000,600,*,UP,ALU1 +S 4500,4000,4500,6100,600,*,UP,PDIF +S 4500,5100,4500,6800,400,*,UP,ALU1 +S 500,4000,500,6400,600,*,UP,PDIF +S 500,500,500,2400,600,*,UP,NDIF +S 500,5600,500,6800,600,*,UP,ALU1 +V 1500,4900,CONT_DIF_P,* +V 1500,5600,CONT_DIF_P,* +V 1600,1600,CONT_DIF_N,* +V 1700,3200,CONT_POLY,zn +V 2500,6000,CONT_DIF_P,* +V 2700,900,CONT_DIF_N,* +V 3100,3200,CONT_POLY,* +V 3500,4900,CONT_DIF_P,zn +V 3500,5600,CONT_DIF_P,zn +V 4400,3200,CONT_POLY,* +V 4500,1600,CONT_DIF_N,zn +V 4500,5200,CONT_DIF_P,* +V 4500,6000,CONT_DIF_P,* +V 500,5600,CONT_DIF_P,* +V 500,600,CONT_DIF_N,* +V 500,6300,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/an2v0x4.vbe b/pdks/symbolic/vsclib/cells/an2v0x4.vbe new file mode 100755 index 000000000..13e6dafd0 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an2v0x4.vbe @@ -0,0 +1,32 @@ +ENTITY an2v0x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_a : NATURAL := 6; + CONSTANT rdown_b_z : NATURAL := 830; + CONSTANT rdown_a_z : NATURAL := 840; + CONSTANT rup_b_z : NATURAL := 1070; + CONSTANT rup_a_z : NATURAL := 1070; + CONSTANT tphh_a_z : NATURAL := 74; + CONSTANT tphh_b_z : NATURAL := 75; + CONSTANT tpll_b_z : NATURAL := 92; + CONSTANT tpll_a_z : NATURAL := 100; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an2v0x4; + +ARCHITECTURE behaviour_data_flow OF an2v0x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an2v0x4" + SEVERITY WARNING; + z <= (b and a) after 109 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/an2v0x8.ap b/pdks/symbolic/vsclib/cells/an2v0x8.ap new file mode 100755 index 000000000..b40784462 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an2v0x8.ap @@ -0,0 +1,140 @@ +V ALLIANCE : 6 +H an2v0x8,P,27/ 5/2006,1000 +A 0,0,96000,72000 +R 12000,24000,ref_ref,z_24 +R 20000,24000,ref_ref,z_24 +R 20000,32000,ref_ref,z_32 +R 20000,40000,ref_ref,z_40 +R 28000,24000,ref_ref,z_24 +R 28000,40000,ref_ref,z_40 +R 36000,16000,ref_ref,z_16 +R 36000,48000,ref_ref,z_48 +R 52000,32000,ref_ref,a_32 +R 60000,24000,ref_ref,a_24 +R 68000,24000,ref_ref,a_24 +R 68000,32000,ref_ref,b_32 +R 68000,40000,ref_ref,b_40 +R 76000,24000,ref_ref,a_24 +R 76000,40000,ref_ref,b_40 +R 84000,24000,ref_ref,a_24 +R 84000,32000,ref_ref,a_32 +S 0,4000,96000,4000,8000,*,RIGHT,ALU1 +S 0,4000,96000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,96000,54000,44000,*,RIGHT,NWELL +S 0,68000,96000,68000,8000,*,RIGHT,ALU1 +S 0,68000,96000,68000,8000,vdd,RIGHT,CALU1 +S 10000,34000,40000,34000,2000,*,RIGHT,POLY +S 10000,38000,10000,66000,2000,t09,UP,PTRANS +S 11000,24000,36000,24000,4000,*,RIGHT,ALU1 +S 12000,24000,12000,24000,4000,z,RIGHT,CALU1 +S 15000,40000,15000,49000,4000,*,UP,ALU1 +S 15000,40000,36000,40000,4000,*,RIGHT,ALU1 +S 16000,23000,16000,24000,6000,*,UP,ALU1 +S 20000,24000,20000,40000,4000,*,UP,ALU1 +S 20000,24000,20000,40000,4000,z,UP,CALU1 +S 20000,38000,20000,66000,2000,t10,UP,PTRANS +S 21000,26000,21000,34000,2000,*,UP,POLY +S 21000,3000,21000,7000,2000,*,UP,POLY +S 21000,7000,21000,26000,2000,t13,UP,NTRANS +S 25000,54000,25000,68000,4000,*,UP,ALU1 +S 26000,4000,26000,11000,4000,*,UP,ALU1 +S 28000,24000,28000,24000,4000,z,RIGHT,CALU1 +S 28000,40000,28000,40000,4000,z,RIGHT,CALU1 +S 30000,38000,30000,66000,2000,t11,UP,PTRANS +S 31000,3000,31000,7000,2000,*,UP,POLY +S 31000,32000,41000,32000,6000,*,RIGHT,POLY +S 31000,7000,31000,26000,2000,t14,UP,NTRANS +S 35000,40000,35000,49000,4000,*,UP,ALU1 +S 36000,15000,36000,24000,4000,*,UP,ALU1 +S 36000,16000,36000,16000,4000,z,RIGHT,CALU1 +S 36000,40000,36000,49000,4000,*,UP,ALU1 +S 36000,48000,36000,48000,4000,z,RIGHT,CALU1 +S 37000,32000,44000,32000,4000,*,RIGHT,ALU1 +S 40000,38000,40000,66000,2000,t12,UP,PTRANS +S 41000,3000,41000,7000,2000,*,UP,POLY +S 41000,7000,41000,26000,2000,t15,UP,NTRANS +S 44000,15000,44000,41000,4000,*,UP,ALU1 +S 44000,15000,66000,15000,4000,*,RIGHT,ALU1 +S 44000,40000,44000,63000,6000,*,UP,PDIF +S 44000,41000,55000,41000,4000,*,RIGHT,ALU1 +S 45000,54000,45000,68000,4000,*,UP,ALU1 +S 47000,5000,47000,24000,6000,*,UP,NDIF +S 50000,32000,50000,40000,2000,*,UP,POLY +S 50000,40000,50000,66000,2000,t01,UP,PTRANS +S 5000,40000,5000,64000,6000,*,UP,PDIF +S 5000,54000,5000,68000,4000,*,UP,ALU1 +S 52000,24000,52000,33000,4000,*,UP,ALU1 +S 52000,24000,85000,24000,4000,*,RIGHT,ALU1 +S 52000,32000,52000,32000,4000,a,RIGHT,CALU1 +S 53000,5000,53000,9000,2000,*,UP,POLY +S 53000,9000,53000,26000,2000,t03,UP,NTRANS +S 55000,41000,55000,52000,4000,*,UP,ALU1 +S 55000,48000,78000,48000,4000,*,RIGHT,ALU1 +S 56000,11000,56000,24000,4000,n1a,UP,NDIF +S 60000,24000,60000,24000,4000,a,RIGHT,CALU1 +S 60000,26000,60000,40000,2000,*,UP,POLY +S 60000,34000,70000,34000,6000,*,RIGHT,POLY +S 60000,36000,72000,36000,2000,*,RIGHT,POLY +S 60000,40000,60000,66000,2000,t05,UP,PTRANS +S 60000,5000,60000,9000,2000,*,UP,POLY +S 60000,9000,60000,26000,2000,t07,UP,NTRANS +S 6000,5000,6000,22000,6000,*,UP,PTIE +S 66000,42000,66000,63000,6000,*,UP,PDIF +S 66000,56000,66000,68000,6000,*,UP,ALU1 +S 67000,40000,77000,40000,4000,*,RIGHT,ALU1 +S 68000,24000,68000,24000,4000,a,RIGHT,CALU1 +S 68000,32000,68000,40000,4000,b,UP,CALU1 +S 68000,32000,68000,40000,6000,*,UP,ALU1 +S 70000,26000,70000,34000,2000,*,UP,POLY +S 70000,5000,70000,9000,2000,*,UP,POLY +S 70000,9000,70000,26000,2000,t08,UP,NTRANS +S 72000,40000,72000,54000,2000,t06,UP,PTRANS +S 72000,54000,72000,58000,2000,*,UP,POLY +S 73000,11000,73000,24000,4000,n1b,UP,NDIF +S 76000,24000,76000,24000,4000,a,RIGHT,CALU1 +S 76000,40000,76000,40000,4000,b,RIGHT,CALU1 +S 77000,30000,85000,30000,2000,*,RIGHT,POLY +S 77000,5000,77000,9000,2000,*,UP,POLY +S 77000,9000,77000,26000,2000,t04,UP,NTRANS +S 78000,66000,86000,66000,6000,*,RIGHT,NTIE +S 82000,30000,82000,40000,2000,*,UP,POLY +S 82000,40000,82000,54000,2000,t02,UP,PTRANS +S 82000,4000,82000,14000,4000,*,UP,ALU1 +S 82000,54000,82000,58000,2000,*,UP,POLY +S 83000,11000,83000,24000,6000,*,UP,NDIF +S 84000,24000,84000,32000,4000,a,UP,CALU1 +S 84000,24000,84000,32000,6000,*,UP,ALU1 +S 87000,42000,87000,52000,6000,*,UP,PDIF +S 87000,42000,87000,68000,4000,*,UP,ALU1 +V 15000,41000,CONT_DIF_P,* +V 15000,48000,CONT_DIF_P,* +V 16000,23000,CONT_DIF_N,* +V 25000,55000,CONT_DIF_P,* +V 25000,63000,CONT_DIF_P,* +V 26000,10000,CONT_DIF_N,* +V 35000,41000,CONT_DIF_P,* +V 35000,48000,CONT_DIF_P,* +V 36000,16000,CONT_DIF_N,* +V 36000,23000,CONT_DIF_N,* +V 38000,32000,CONT_POLY,zn +V 45000,55000,CONT_DIF_P,* +V 45000,63000,CONT_DIF_P,* +V 47000,6000,CONT_DIF_N,* +V 5000,55000,CONT_DIF_P,* +V 5000,63000,CONT_DIF_P,* +V 52000,32000,CONT_POLY,* +V 55000,44000,CONT_DIF_P,zn +V 55000,51000,CONT_DIF_P,zn +V 6000,6000,CONT_BODY_P,* +V 65000,15000,CONT_DIF_N,zn +V 66000,56000,CONT_DIF_P,* +V 66000,63000,CONT_DIF_P,* +V 68000,34000,CONT_POLY,* +V 77000,48000,CONT_DIF_P,zn +V 78000,66000,CONT_BODY_N,* +V 82000,13000,CONT_DIF_N,* +V 84000,32000,CONT_POLY,* +V 86000,66000,CONT_BODY_N,* +V 87000,43000,CONT_DIF_P,* +V 87000,51000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/an2v0x8.vbe b/pdks/symbolic/vsclib/cells/an2v0x8.vbe new file mode 100755 index 000000000..c6a7c75fe --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an2v0x8.vbe @@ -0,0 +1,32 @@ +ENTITY an2v0x8 IS +GENERIC ( + CONSTANT area : NATURAL := 6912; + CONSTANT cin_b : NATURAL := 9; + CONSTANT cin_a : NATURAL := 10; + CONSTANT rdown_b_z : NATURAL := 410; + CONSTANT rdown_a_z : NATURAL := 410; + CONSTANT rup_b_z : NATURAL := 530; + CONSTANT rup_a_z : NATURAL := 530; + CONSTANT tphh_a_z : NATURAL := 76; + CONSTANT tphh_b_z : NATURAL := 77; + CONSTANT tpll_b_z : NATURAL := 97; + CONSTANT tpll_a_z : NATURAL := 106; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an2v0x8; + +ARCHITECTURE behaviour_data_flow OF an2v0x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an2v0x8" + SEVERITY WARNING; + z <= (b and a) after 101 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/an3v0x05.ap b/pdks/symbolic/vsclib/cells/an3v0x05.ap new file mode 100755 index 000000000..e70362bf0 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an3v0x05.ap @@ -0,0 +1,96 @@ +V ALLIANCE : 6 +H an3v0x05,P, 5/ 7/2024,100 +A 0,0,5600,7200 +R 1200,5600,ref_ref,z_56 +R 2000,3200,ref_ref,a_32 +R 2800,2400,ref_ref,a_24 +R 2800,4000,ref_ref,b_40 +R 3600,2400,ref_ref,c_24 +R 3600,4800,ref_ref,b_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +R 4400,3200,ref_ref,c_32 +R 4400,4000,ref_ref,c_40 +R 4400,4800,ref_ref,b_48 +S 1900,5800,1900,7000,200,*,DOWN,TALU8 +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,1600,1000,2000,200,*,UP,POLY +S 1000,2000,1000,2600,200,t08,UP,NTRANS +S 1000,2600,1000,4600,200,*,UP,POLY +S 1000,4600,1000,5800,200,t07,UP,PTRANS +S 1000,5800,1000,6200,200,*,UP,POLY +S 1200,2300,1200,4800,400,*,UP,ALU1 +S 1200,2300,1700,2300,400,*,RIGHT,ALU1 +S 1200,4800,2500,4800,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1500,4800,1500,6700,400,*,UP,PDIF +S 1700,1500,1700,2300,400,*,UP,ALU1 +S 1700,1500,4400,1500,400,*,RIGHT,ALU1 +S 1700,500,1700,2400,800,*,UP,NDIF +S 1800,500,1800,2400,800,*,UP,NDIF +S 1900,3200,2800,3200,400,*,RIGHT,ALU1 +S 2000,3200,2000,3200,400,a,LEFT,CALU1 +S 2000,3200,2000,4600,200,*,UP,POLY +S 2000,4600,2000,5700,200,t01,UP,PTRANS +S 2200,3200,2500,3200,600,*,RIGHT,POLY +S 2500,1100,2500,1500,200,*,UP,POLY +S 2500,1500,2500,2600,200,t02,UP,NTRANS +S 2500,4800,2500,5500,400,*,UP,ALU1 +S 2500,5500,4800,5500,400,*,RIGHT,ALU1 +S 2700,4000,3500,4000,400,*,RIGHT,ALU1 +S 2800,1700,2800,2400,400,n1,UP,NDIF +S 2800,2300,2800,3200,400,*,UP,ALU1 +S 2800,2400,2800,2400,400,a,LEFT,CALU1 +S 2800,4000,2800,4000,400,b,LEFT,CALU1 +S 3000,4100,3400,4100,200,*,RIGHT,POLY +S 3000,4200,3400,4200,200,*,RIGHT,POLY +S 3000,4600,3000,5700,200,t03,UP,PTRANS +S 3200,1100,3200,1500,200,*,UP,POLY +S 3200,1500,3200,2600,200,t04,UP,NTRANS +S 3200,2600,3200,3900,200,*,UP,POLY +S 3500,1700,3500,2400,400,n2,UP,NDIF +S 3500,4000,3500,4800,400,*,UP,ALU1 +S 3500,4800,4500,4800,400,*,RIGHT,ALU1 +S 3600,2300,3600,3200,400,*,UP,ALU1 +S 3600,2400,3600,2400,400,c,LEFT,CALU1 +S 3600,3200,4500,3200,400,*,RIGHT,ALU1 +S 3600,4800,3600,4800,400,b,LEFT,CALU1 +S 3600,4800,3600,6700,600,*,UP,PDIF +S 3800,600,4600,600,600,*,RIGHT,PTIE +S 3900,1500,3900,2600,200,t06,UP,NTRANS +S 3900,3000,4400,3000,200,*,RIGHT,POLY +S 400,1500,400,5700,400,*,UP,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 400,5600,1200,5600,600,*,RIGHT,ALU1 +S 4200,3200,4200,4700,200,*,UP,POLY +S 4200,4700,4200,5800,200,t05,UP,PTRANS +S 4400,1500,4400,1900,400,*,UP,ALU1 +S 4400,3200,4400,4000,400,c,UP,CALU1 +S 4400,3200,4400,4000,600,*,UP,ALU1 +S 4400,4800,4400,4800,400,b,LEFT,CALU1 +S 500,2200,500,2400,400,*,UP,ALU1 +V 1200,3300,CONT_POLY,zn +V 1600,6600,CONT_DIF_P,* +V 1700,600,CONT_DIF_N,* +V 2200,3200,CONT_POLY,* +V 2500,4900,CONT_DIF_P,zn +V 2600,6600,CONT_BODY_N,* +V 3400,4000,CONT_POLY,* +V 3600,6600,CONT_DIF_P,* +V 3800,600,CONT_BODY_P,* +V 4400,1800,CONT_DIF_N,zn +V 4400,3200,CONT_POLY,* +V 4600,600,CONT_BODY_P,* +V 4700,5500,CONT_DIF_P,zn +V 500,2300,CONT_DIF_N,* +V 500,5500,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/an3v0x05.vbe b/pdks/symbolic/vsclib/cells/an3v0x05.vbe new file mode 100755 index 000000000..7e8904c7b --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an3v0x05.vbe @@ -0,0 +1,38 @@ +ENTITY an3v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3950; + CONSTANT rdown_b_z : NATURAL := 3910; + CONSTANT rdown_c_z : NATURAL := 3890; + CONSTANT rup_a_z : NATURAL := 5010; + CONSTANT rup_b_z : NATURAL := 5010; + CONSTANT rup_c_z : NATURAL := 5010; + CONSTANT tphh_c_z : NATURAL := 88; + CONSTANT tphh_b_z : NATURAL := 93; + CONSTANT tphh_a_z : NATURAL := 94; + CONSTANT tpll_a_z : NATURAL := 120; + CONSTANT tpll_b_z : NATURAL := 111; + CONSTANT tpll_c_z : NATURAL := 100; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an3v0x05; + +ARCHITECTURE behaviour_data_flow OF an3v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an3v0x05" + SEVERITY WARNING; + z <= ((a and b) and c) after 213 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/an3v0x1.ap b/pdks/symbolic/vsclib/cells/an3v0x1.ap new file mode 100755 index 000000000..eedff1b72 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an3v0x1.ap @@ -0,0 +1,106 @@ +V ALLIANCE : 6 +H an3v0x1,P,27/ 5/2006,1000 +A 0,0,56000,72000 +R 12000,48000,ref_ref,z_48 +R 20000,32000,ref_ref,a_32 +R 28000,24000,ref_ref,a_24 +R 28000,40000,ref_ref,b_40 +R 36000,24000,ref_ref,c_24 +R 36000,40000,ref_ref,b_40 +R 36000,48000,ref_ref,b_48 +R 4000,16000,ref_ref,z_16 +R 4000,24000,ref_ref,z_24 +R 4000,32000,ref_ref,z_32 +R 4000,40000,ref_ref,z_40 +R 4000,48000,ref_ref,z_48 +R 4000,56000,ref_ref,z_56 +R 44000,24000,ref_ref,c_24 +R 44000,32000,ref_ref,c_32 +R 44000,40000,ref_ref,b_40 +S 0,4000,56000,4000,8000,*,RIGHT,ALU1 +S 0,4000,56000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,56000,54000,44000,*,RIGHT,NWELL +S 0,68000,56000,68000,8000,*,RIGHT,ALU1 +S 0,68000,56000,68000,8000,vdd,RIGHT,CALU1 +S 10000,12000,10000,16000,2000,*,UP,POLY +S 10000,16000,10000,25000,2000,t08,UP,NTRANS +S 10000,21000,10000,40000,2000,*,UP,POLY +S 10000,40000,10000,58000,2000,t07,UP,PTRANS +S 10000,58000,10000,62000,2000,*,UP,POLY +S 12000,23000,12000,40000,4000,*,UP,ALU1 +S 12000,23000,17000,23000,4000,*,RIGHT,ALU1 +S 12000,40000,20000,40000,4000,*,RIGHT,ALU1 +S 12000,48000,12000,48000,4000,z,RIGHT,CALU1 +S 15000,42000,15000,56000,4000,*,UP,PDIF +S 15000,55000,15000,68000,6000,*,UP,ALU1 +S 16000,5000,16000,23000,6000,*,UP,NDIF +S 17000,15000,17000,23000,4000,*,UP,ALU1 +S 17000,15000,43000,15000,4000,*,RIGHT,ALU1 +S 17000,5000,17000,23000,6000,*,UP,NDIF +S 19000,32000,28000,32000,4000,*,RIGHT,ALU1 +S 20000,32000,20000,32000,4000,a,RIGHT,CALU1 +S 20000,32000,20000,45000,2000,*,UP,POLY +S 20000,40000,20000,47000,4000,*,UP,ALU1 +S 20000,45000,20000,58000,2000,t01,UP,PTRANS +S 20000,47000,25000,47000,4000,*,RIGHT,ALU1 +S 20000,58000,20000,62000,2000,*,UP,POLY +S 23000,12000,23000,25000,2000,t02,UP,NTRANS +S 23000,25000,23000,32000,2000,*,UP,POLY +S 23000,8000,23000,12000,2000,*,UP,POLY +S 25000,47000,25000,56000,4000,*,UP,ALU1 +S 25000,56000,48000,56000,4000,*,RIGHT,ALU1 +S 26000,14000,26000,23000,4000,n1,UP,NDIF +S 27000,40000,45000,40000,4000,*,RIGHT,ALU1 +S 28000,23000,28000,32000,4000,*,UP,ALU1 +S 28000,24000,28000,24000,4000,a,RIGHT,CALU1 +S 28000,40000,28000,40000,4000,b,RIGHT,CALU1 +S 30000,12000,30000,25000,2000,t04,UP,NTRANS +S 30000,25000,30000,40000,2000,*,UP,POLY +S 30000,45000,30000,58000,2000,t03,UP,PTRANS +S 30000,58000,30000,62000,2000,*,UP,POLY +S 30000,8000,30000,12000,2000,*,UP,POLY +S 32000,39000,32000,40000,6000,*,UP,ALU1 +S 33000,14000,33000,23000,4000,n2,UP,NDIF +S 36000,24000,36000,24000,4000,c,RIGHT,CALU1 +S 36000,24000,45000,24000,6000,*,RIGHT,ALU1 +S 36000,40000,36000,48000,4000,b,UP,CALU1 +S 36000,40000,36000,48000,6000,*,UP,ALU1 +S 36000,47000,36000,67000,6000,*,UP,PDIF +S 37000,12000,37000,25000,2000,t06,UP,NTRANS +S 37000,25000,37000,30000,2000,*,UP,POLY +S 37000,30000,42000,30000,2000,*,RIGHT,POLY +S 37000,8000,37000,12000,2000,*,UP,POLY +S 4000,15000,4000,57000,4000,*,UP,ALU1 +S 4000,16000,4000,56000,4000,z,UP,CALU1 +S 4000,48000,13000,48000,4000,*,RIGHT,ALU1 +S 42000,32000,42000,45000,2000,*,UP,POLY +S 42000,44000,42000,57000,2000,t05,UP,PTRANS +S 42000,57000,42000,61000,2000,*,UP,POLY +S 44000,23000,44000,32000,6000,*,UP,ALU1 +S 44000,24000,44000,32000,4000,c,UP,CALU1 +S 44000,32000,44000,32000,4000,c,RIGHT,CALU1 +S 44000,40000,44000,40000,4000,b,RIGHT,CALU1 +S 47000,46000,47000,55000,6000,*,UP,PDIF +S 47000,47000,47000,56000,6000,*,UP,ALU1 +S 5000,21000,5000,23000,4000,*,UP,ALU1 +S 5000,42000,5000,57000,4000,*,UP,ALU1 +S 5000,43000,5000,50000,6000,*,UP,PDIF +S 5000,48000,5000,57000,4000,*,UP,ALU1 +V 12000,32000,CONT_POLY,zn +V 15000,55000,CONT_DIF_P,* +V 16000,6000,CONT_DIF_N,* +V 22000,32000,CONT_POLY,* +V 25000,48000,CONT_DIF_P,zn +V 25000,55000,CONT_DIF_P,zn +V 32000,39000,CONT_POLY,* +V 36000,66000,CONT_DIF_P,* +V 42000,15000,CONT_DIF_N,zn +V 44000,32000,CONT_POLY,* +V 47000,47000,CONT_DIF_P,zn +V 47000,54000,CONT_DIF_P,zn +V 50000,66000,CONT_BODY_N,* +V 5000,22000,CONT_DIF_N,* +V 5000,43000,CONT_DIF_P,* +V 5000,50000,CONT_DIF_P,* +V 6000,6000,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/an3v0x1.vbe b/pdks/symbolic/vsclib/cells/an3v0x1.vbe new file mode 100755 index 000000000..c1f777b69 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an3v0x1.vbe @@ -0,0 +1,38 @@ +ENTITY an3v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 2610; + CONSTANT rdown_b_z : NATURAL := 2600; + CONSTANT rdown_c_z : NATURAL := 2580; + CONSTANT rup_a_z : NATURAL := 3330; + CONSTANT rup_b_z : NATURAL := 3330; + CONSTANT rup_c_z : NATURAL := 3330; + CONSTANT tphh_c_z : NATURAL := 89; + CONSTANT tphh_b_z : NATURAL := 93; + CONSTANT tphh_a_z : NATURAL := 94; + CONSTANT tpll_a_z : NATURAL := 121; + CONSTANT tpll_b_z : NATURAL := 112; + CONSTANT tpll_c_z : NATURAL := 101; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an3v0x1; + +ARCHITECTURE behaviour_data_flow OF an3v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an3v0x1" + SEVERITY WARNING; + z <= ((a and b) and c) after 176 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/an3v0x2.ap b/pdks/symbolic/vsclib/cells/an3v0x2.ap new file mode 100755 index 000000000..ca06185b0 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an3v0x2.ap @@ -0,0 +1,96 @@ +V ALLIANCE : 6 +H an3v0x2,P,22/ 6/2024,100 +A 0,0,5600,7200 +R 1200,1600,ref_ref,z_16 +R 2000,4000,ref_ref,a_40 +R 2800,3200,ref_ref,a_32 +R 3600,2400,ref_ref,c_24 +R 3600,4000,ref_ref,b_40 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,2400,ref_ref,c_24 +R 4400,3200,ref_ref,c_32 +R 4400,4800,ref_ref,b_48 +S 3000,3500,3000,4600,200,*,UP,POLY +S 2100,3000,2100,3400,200,*,UP,POLY +S 2300,2700,2300,3400,200,*,UP,POLY +S 1000,2700,1000,3700,200,*,UP,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,1100,1000,2500,200,t08,UP,NTRANS +S 1000,3800,1000,6600,200,t07,UP,PTRANS +S 1000,700,1000,1100,200,*,UP,POLY +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2400,1200,4900,400,*,UP,ALU1 +S 1200,2400,2400,2400,400,*,RIGHT,ALU1 +S 1200,3100,1200,3300,400,*,UP,ALU1 +S 1200,4900,2600,4900,400,*,RIGHT,ALU1 +S 1400,4000,1400,6400,600,*,UP,PDIF +S 1500,5900,1500,6800,400,*,UP,ALU1 +S 1600,500,1600,2300,600,*,UP,NDIF +S 1700,500,1700,2300,600,*,UP,NDIF +S 2000,3200,2000,4100,400,*,UP,ALU1 +S 2000,3200,2000,4600,200,*,UP,POLY +S 2000,3200,2900,3200,400,*,RIGHT,ALU1 +S 2000,4000,2000,4000,400,a,LEFT,CALU1 +S 2000,4600,2000,6300,200,t01,UP,PTRANS +S 2000,6300,2000,6700,200,*,UP,POLY +S 2300,400,2300,800,200,*,UP,POLY +S 2300,800,2300,2500,200,t02,UP,NTRANS +S 2400,1500,2400,2400,400,*,UP,ALU1 +S 2400,1500,4300,1500,400,*,RIGHT,ALU1 +S 2500,4900,2500,5700,400,*,UP,ALU1 +S 2500,5700,4800,5700,400,*,RIGHT,ALU1 +S 2600,1000,2600,2300,400,n1,UP,NDIF +S 2600,4900,2600,5700,400,*,UP,ALU1 +S 2800,3200,2800,3200,400,a,LEFT,CALU1 +S 3000,2500,3000,4000,200,*,UP,POLY +S 3000,400,3000,800,200,*,UP,POLY +S 3000,4600,3000,6300,200,t03,UP,PTRANS +S 3000,6300,3000,6700,200,*,UP,POLY +S 3000,800,3000,2500,200,t04,UP,NTRANS +S 3100,4000,4400,4000,400,*,RIGHT,ALU1 +S 3300,1000,3300,2300,400,n2,UP,NDIF +S 3500,2400,4500,2400,400,*,RIGHT,ALU1 +S 3600,2400,3600,2400,400,c,LEFT,CALU1 +S 3600,4000,3600,4000,400,b,LEFT,CALU1 +S 3600,4800,3600,6700,600,*,UP,PDIF +S 3700,2500,3700,3000,200,*,UP,POLY +S 3700,400,3700,800,200,*,UP,POLY +S 3700,800,3700,2500,200,t06,UP,NTRANS +S 3800,3000,4400,3000,200,*,RIGHT,POLY +S 400,1500,1300,1500,400,*,RIGHT,ALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 400,1600,1300,1600,400,*,RIGHT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,1600,400,4900,400,*,UP,ALU1 +S 4200,3000,4200,4600,200,*,UP,POLY +S 4200,4600,4200,6300,200,t05,UP,PTRANS +S 4200,6300,4200,6700,200,*,UP,POLY +S 4400,2400,4400,3200,400,c,UP,CALU1 +S 4400,2400,4400,3200,600,*,UP,ALU1 +S 4400,4000,4400,4900,400,*,UP,ALU1 +S 4400,4800,4400,4800,400,b,LEFT,CALU1 +S 500,4000,500,4900,400,*,UP,ALU1 +S 500,4100,500,4800,600,*,UP,PDIF +V 1200,3200,CONT_POLY,zn +V 1500,6000,CONT_DIF_P,* +V 1700,600,CONT_DIF_N,* +V 2200,3200,CONT_POLY,* +V 2500,4900,CONT_DIF_P,zn +V 2500,5600,CONT_DIF_P,zn +V 3200,4000,CONT_POLY,* +V 3600,6600,CONT_DIF_P,* +V 4200,1500,CONT_DIF_N,zn +V 4400,3200,CONT_POLY,* +V 4700,5700,CONT_DIF_P,zn +V 500,1600,CONT_DIF_N,* +V 500,4100,CONT_DIF_P,* +V 500,4800,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/an3v0x2.vbe b/pdks/symbolic/vsclib/cells/an3v0x2.vbe new file mode 100755 index 000000000..9160ce23e --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an3v0x2.vbe @@ -0,0 +1,38 @@ +ENTITY an3v0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 1700; + CONSTANT rdown_b_z : NATURAL := 1680; + CONSTANT rdown_c_z : NATURAL := 1670; + CONSTANT rup_a_z : NATURAL := 2150; + CONSTANT rup_b_z : NATURAL := 2150; + CONSTANT rup_c_z : NATURAL := 2150; + CONSTANT tphh_c_z : NATURAL := 86; + CONSTANT tphh_b_z : NATURAL := 89; + CONSTANT tphh_a_z : NATURAL := 91; + CONSTANT tpll_a_z : NATURAL := 118; + CONSTANT tpll_b_z : NATURAL := 109; + CONSTANT tpll_c_z : NATURAL := 98; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an3v0x2; + +ARCHITECTURE behaviour_data_flow OF an3v0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an3v0x2" + SEVERITY WARNING; + z <= ((a and b) and c) after 146 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/an3v6x05.ap b/pdks/symbolic/vsclib/cells/an3v6x05.ap new file mode 100755 index 000000000..967f6dc43 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an3v6x05.ap @@ -0,0 +1,106 @@ +V ALLIANCE : 6 +H an3v6x05,P,22/ 6/2024,100 +A 0,0,5600,7200 +R 5200,4800,ref_ref,z_48 +R 2000,4000,ref_ref,a_40 +R 2800,4000,ref_ref,a_40 +R 1300,3200,ref_ref,b_32 +R 400,4000,ref_ref,b_40 +R 400,1600,ref_ref,c_16 +R 5200,1600,ref_ref,z_16 +R 5200,4000,ref_ref,z_40 +R 5200,2400,ref_ref,z_24 +R 5200,3200,ref_ref,z_32 +R 2800,3200,ref_ref,a_32 +R 4400,4000,ref_ref,z_40 +R 400,2400,ref_ref,c_24 +R 1200,2400,ref_ref,c_24 +S 4600,5100,4600,5800,200,*,UP,POLY +S 4300,2000,4300,2500,200,*,UP,POLY +S 3900,2700,4600,2700,200,*,LEFT,POLY +S 3000,3600,3000,4800,200,*,DOWN,POLY +S 2000,3000,2000,3700,200,*,DOWN,POLY +S 1600,3000,2600,3000,200,*,RIGHT,POLY +S 1000,2300,1000,3100,200,*,UP,POLY +S 700,2300,1800,2300,200,*,LEFT,POLY +S 5200,1500,5200,4900,400,*,DOWN,ALU1 +S 5200,1600,5200,4800,400,z,UP,CALU1 +S 3500,5500,3500,6800,600,*,UP,ALU1 +S 4400,5600,4900,5600,400,*,RIGHT,ALU1 +S 4400,4800,4400,5600,400,*,DOWN,ALU1 +S 500,4800,4400,4800,400,*,RIGHT,ALU1 +S 2800,3200,2800,4000,400,a,DOWN,CALU1 +S 400,3200,1900,3200,400,*,RIGHT,ALU1 +S 400,3200,400,4100,400,*,DOWN,ALU1 +S 400,4000,400,4000,400,b,LEFT,CALU1 +S 2800,1600,2800,2500,400,*,DOWN,ALU1 +S 2800,2500,4200,2500,400,*,LEFT,ALU1 +S 1900,4000,2900,4000,400,*,LEFT,ALU1 +S 2800,3200,2800,4000,600,*,UP,ALU1 +S 4700,1500,5200,1500,400,*,LEFT,ALU1 +S 1000,5800,1000,6200,200,*,UP,POLY +S 2000,5800,2000,6200,200,*,UP,POLY +S 3000,5800,3000,6200,200,*,UP,POLY +S 3000,4000,3000,4700,200,*,UP,POLY +S 2000,3400,2000,4700,200,*,UP,POLY +S 1000,2700,1000,4700,200,*,UP,POLY +S 4300,900,4300,1300,200,*,DOWN,POLY +S 4600,2700,4600,3800,200,*,DOWN,POLY +S 3800,1000,3800,1700,400,*,DOWN,NDIF +S 4700,1600,5200,1600,400,*,LEFT,ALU1 +S 2500,4800,2500,5100,400,*,UP,ALU1 +S 500,4800,500,5100,400,*,UP,ALU1 +S 1500,5500,1500,6800,600,*,UP,ALU1 +S 1000,4700,1000,5800,200,t05,UP,PTRANS +S 3000,4700,3000,5800,200,t01,UP,PTRANS +S 2000,4700,2000,5800,200,t03,UP,PTRANS +S 4000,4000,4000,5600,600,*,DOWN,PDIF +S 3300,1900,3300,3600,200,*,UP,POLY +S 3000,3600,3300,3600,200,*,LEFT,POLY +S 2600,1900,2600,3000,200,*,UP,POLY +S 2000,3000,2600,3000,200,*,LEFT,POLY +S 3800,4200,3800,5600,1000,*,UP,PDIF +S 1900,400,1900,800,200,*,UP,POLY +S 2600,400,2600,800,200,*,UP,POLY +S 3300,400,3300,800,200,*,UP,POLY +S 1000,2300,1900,2300,200,*,LEFT,POLY +S 1300,1600,2800,1600,400,*,LEFT,ALU1 +S 1900,800,1900,1900,200,t06,UP,NTRANS +S 2200,1000,2200,1700,400,n2,UP,NDIF +S 2600,800,2600,1900,200,t04,UP,NTRANS +S 2900,1000,2900,1700,400,n1,UP,NDIF +S 3300,800,3300,1900,200,t02,UP,NTRANS +S 3800,400,3800,1700,400,*,DOWN,ALU1 +S 4300,1300,4300,1900,200,t08,UP,NTRANS +S 700,2500,900,2500,400,*,RIGHT,ALU1 +S 4300,4100,5200,4100,400,*,LEFT,ALU1 +S 4300,4000,5200,4000,400,*,LEFT,ALU1 +S 4600,3800,4600,5000,200,t07,UP,PTRANS +S 4400,4000,4400,4000,400,z,LEFT,CALU1 +S 400,2400,1300,2400,400,*,RIGHT,ALU1 +S 400,1500,400,2400,400,*,UP,ALU1 +S 400,1600,400,1600,400,c,LEFT,CALU1 +S 1300,3200,1300,3200,400,b,LEFT,CALU1 +S 2000,4000,2000,4000,400,a,LEFT,CALU1 +S 1200,2400,1200,2400,400,c,LEFT,CALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,400,5600,400,800,*,RIGHT,ALU1 +V 3500,5500,CONT_DIF_P,* +V 4100,2500,CONT_POLY,zn +V 1500,5500,CONT_DIF_P,* +V 500,5000,CONT_DIF_P,zn +V 2500,5000,CONT_DIF_P,zn +V 2800,3800,CONT_POLY,* +V 1400,1600,CONT_DIF_N,zn +V 3800,1600,CONT_DIF_N,* +V 4800,1600,CONT_DIF_N,* +V 800,2500,CONT_POLY,* +V 4800,5600,CONT_POLY,zn +V 5100,4100,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 1800,3200,CONT_POLY,* +V 4600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/an3v6x05.vbe b/pdks/symbolic/vsclib/cells/an3v6x05.vbe new file mode 100755 index 000000000..1510bea9e --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an3v6x05.vbe @@ -0,0 +1,38 @@ +ENTITY an3v6x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3930; + CONSTANT rdown_b_z : NATURAL := 3910; + CONSTANT rdown_c_z : NATURAL := 3880; + CONSTANT rup_a_z : NATURAL := 4990; + CONSTANT rup_b_z : NATURAL := 5000; + CONSTANT rup_c_z : NATURAL := 5000; + CONSTANT tphh_c_z : NATURAL := 86; + CONSTANT tphh_b_z : NATURAL := 90; + CONSTANT tphh_a_z : NATURAL := 91; + CONSTANT tpll_a_z : NATURAL := 117; + CONSTANT tpll_b_z : NATURAL := 109; + CONSTANT tpll_c_z : NATURAL := 98; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an3v6x05; + +ARCHITECTURE behaviour_data_flow OF an3v6x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an3v6x05" + SEVERITY WARNING; + z <= ((a and b) and c) after 210 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/an4v0x05.ap b/pdks/symbolic/vsclib/cells/an4v0x05.ap new file mode 100755 index 000000000..b88c0e568 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an4v0x05.ap @@ -0,0 +1,125 @@ +V ALLIANCE : 6 +H an4v0x05,P,22/ 6/2024,100 +A 0,0,6400,7200 +R 1200,1600,ref_ref,z_16 +R 2800,3200,ref_ref,a_32 +R 2800,4000,ref_ref,b_40 +R 3600,2400,ref_ref,a_24 +R 3600,4800,ref_ref,b_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +R 4400,3200,ref_ref,d_32 +R 4400,4000,ref_ref,c_40 +R 4400,4800,ref_ref,b_48 +R 5200,3200,ref_ref,d_32 +R 5200,4000,ref_ref,c_40 +R 6000,1600,ref_ref,d_16 +R 6000,2400,ref_ref,d_24 +R 6000,4800,ref_ref,c_48 +S 500,4700,500,5400,400,*,UP,PDIF +S 0,400,6400,400,800,*,RIGHT,ALU1 +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 1000,1400,1000,1800,200,*,UP,POLY +S 1000,1800,1000,2400,200,t10,UP,NTRANS +S 1000,2400,1000,4400,200,*,UP,POLY +S 1000,4400,1000,5600,200,t09,UP,PTRANS +S 1000,5600,1000,6000,200,*,UP,POLY +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,3200,1600,3200,400,*,RIGHT,ALU1 +S 1500,4600,1500,6000,400,*,UP,PDIF +S 1600,2500,1600,4800,400,*,UP,ALU1 +S 1600,2500,2000,2500,400,*,RIGHT,ALU1 +S 1600,4600,1600,6000,400,*,UP,PDIF +S 1600,4800,2500,4800,400,*,RIGHT,ALU1 +S 1600,5600,1600,6800,400,*,UP,ALU1 +S 1800,500,1800,2400,1000,*,UP,NDIF +S 2000,1500,2000,2500,400,*,UP,ALU1 +S 2000,1500,5200,1500,400,*,RIGHT,ALU1 +S 2100,3200,2600,3200,600,*,RIGHT,POLY +S 2100,3300,2100,5200,200,*,UP,POLY +S 2100,5200,2100,6200,200,t01,UP,PTRANS +S 2100,6200,2100,6600,200,*,UP,POLY +S 2400,3200,2900,3200,400,*,RIGHT,ALU1 +S 2500,4800,2500,5700,400,*,UP,ALU1 +S 2500,5700,4900,5700,400,*,RIGHT,ALU1 +S 2600,1000,2600,1400,200,*,UP,POLY +S 2600,1400,2600,2600,200,t02,UP,NTRANS +S 2600,2400,2600,3200,200,*,UP,POLY +S 2700,4000,3500,4000,400,*,RIGHT,ALU1 +S 2800,2400,2800,3200,400,*,UP,ALU1 +S 2800,2400,3700,2400,400,*,RIGHT,ALU1 +S 2800,3200,2800,3200,400,a,LEFT,CALU1 +S 2800,4000,2800,4000,400,b,LEFT,CALU1 +S 2900,1600,2900,2400,400,n1,UP,NDIF +S 2900,2400,2900,3200,400,*,UP,ALU1 +S 3100,4600,3300,4600,600,*,RIGHT,POLY +S 3100,5200,3100,6200,200,t03,UP,PTRANS +S 3100,6200,3100,6600,200,*,UP,POLY +S 3300,1000,3300,1400,200,*,UP,POLY +S 3300,1400,3300,2600,200,t04,UP,NTRANS +S 3300,2400,3300,4600,200,*,UP,POLY +S 3500,4000,3500,4800,400,*,UP,ALU1 +S 3500,4800,4500,4800,400,*,RIGHT,ALU1 +S 3600,1600,3600,2400,400,n2,UP,NDIF +S 3600,2400,3600,2400,400,a,LEFT,CALU1 +S 3600,4800,3600,4800,400,b,LEFT,CALU1 +S 3700,5400,3700,6700,600,*,UP,PDIF +S 4000,1000,4000,1400,200,*,UP,POLY +S 4000,1400,4000,2600,200,t06,UP,NTRANS +S 4000,2400,4000,3800,200,*,UP,POLY +S 4000,3800,4300,3800,200,*,RIGHT,POLY +S 400,1500,400,5700,400,*,UP,ALU1 +S 400,1600,1200,1600,600,*,RIGHT,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 4300,1600,4300,2400,400,n3,UP,NDIF +S 4300,3200,6000,3200,400,*,RIGHT,ALU1 +S 4300,4000,4300,5200,200,*,UP,POLY +S 4300,4000,6000,4000,400,*,RIGHT,ALU1 +S 4300,5200,4300,6200,200,t05,UP,PTRANS +S 4300,6200,4300,6600,200,*,UP,POLY +S 4400,3200,4400,3200,400,d,LEFT,CALU1 +S 4400,4000,4400,4000,400,c,LEFT,CALU1 +S 4400,4800,4400,4800,400,b,LEFT,CALU1 +S 4700,1000,4700,1400,200,*,UP,POLY +S 4700,1400,4700,2600,200,t08,UP,NTRANS +S 4700,2400,4700,3000,200,*,UP,POLY +S 4700,3000,5300,3000,200,*,RIGHT,POLY +S 500,1500,500,2200,400,*,UP,ALU1 +S 500,4600,500,5700,400,*,UP,ALU1 +S 5200,1500,5200,1800,400,*,UP,ALU1 +S 5200,3200,5200,3200,400,d,LEFT,CALU1 +S 5200,4000,5200,4000,400,c,LEFT,CALU1 +S 5300,3000,5300,5200,200,*,UP,POLY +S 5300,5200,5300,6200,200,t07,UP,PTRANS +S 5300,6200,5300,6600,200,*,UP,POLY +S 5800,5400,5800,6000,600,*,UP,PDIF +S 5800,5800,5800,6800,400,*,UP,ALU1 +S 6000,1500,6000,3200,400,*,UP,ALU1 +S 6000,1600,6000,2400,400,d,UP,CALU1 +S 6000,4000,6000,4900,400,*,UP,ALU1 +S 6000,4800,6000,4800,400,c,LEFT,CALU1 +V 1300,3200,CONT_POLY,zn +V 1600,5700,CONT_DIF_P,* +V 1800,600,CONT_DIF_N,* +V 2500,3200,CONT_POLY,* +V 2600,5700,CONT_DIF_P,zn +V 3500,4600,CONT_POLY,* +V 3700,6600,CONT_DIF_P,* +V 4500,4000,CONT_POLY,* +V 4800,5700,CONT_DIF_P,zn +V 500,2100,CONT_DIF_N,* +V 500,4700,CONT_DIF_P,* +V 5200,1700,CONT_DIF_N,zn +V 5500,3200,CONT_POLY,* +V 5800,5900,CONT_DIF_P,* +V 5800,600,CONT_BODY_P,* +V 600,600,CONT_BODY_P,* +V 600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/an4v0x05.vbe b/pdks/symbolic/vsclib/cells/an4v0x05.vbe new file mode 100755 index 000000000..8574b9835 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/an4v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY an4v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 3; + CONSTANT cin_d : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 4040; + CONSTANT rdown_b_z : NATURAL := 3990; + CONSTANT rdown_c_z : NATURAL := 3950; + CONSTANT rdown_d_z : NATURAL := 3920; + CONSTANT rup_a_z : NATURAL := 5060; + CONSTANT rup_b_z : NATURAL := 5060; + CONSTANT rup_c_z : NATURAL := 5060; + CONSTANT rup_d_z : NATURAL := 5060; + CONSTANT tphh_a_z : NATURAL := 114; + CONSTANT tphh_b_z : NATURAL := 110; + CONSTANT tpll_d_z : NATURAL := 107; + CONSTANT tphh_c_z : NATURAL := 104; + CONSTANT tpll_c_z : NATURAL := 119; + CONSTANT tphh_d_z : NATURAL := 97; + CONSTANT tpll_b_z : NATURAL := 131; + CONSTANT tpll_a_z : NATURAL := 140; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END an4v0x05; + +ARCHITECTURE behaviour_data_flow OF an4v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on an4v0x05" + SEVERITY WARNING; + z <= (((a and b) and c) and d) after 228 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi112v0x05.ap b/pdks/symbolic/vsclib/cells/aoi112v0x05.ap new file mode 100755 index 000000000..b544a38c5 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi112v0x05.ap @@ -0,0 +1,98 @@ +V ALLIANCE : 6 +H aoi112v0x05,P,23/ 6/2024,100 +A 0,0,4800,7200 +R 4400,4800,ref_ref,b_48 +R 2800,1600,ref_ref,z_16 +R 400,4800,ref_ref,c2_48 +R 2800,4000,ref_ref,c1_40 +R 4400,4000,ref_ref,b_40 +R 3600,3200,ref_ref,b_32 +R 2800,4800,ref_ref,c1_48 +R 2000,3200,ref_ref,c1_32 +R 4400,1600,ref_ref,a_16 +R 3600,2400,ref_ref,a_24 +R 1200,4800,ref_ref,c2_48 +R 400,4000,ref_ref,c2_40 +R 400,3200,ref_ref,c2_32 +R 1200,3200,ref_ref,z_32 +R 1200,2400,ref_ref,z_24 +R 2000,1600,ref_ref,z_16 +R 1200,1600,ref_ref,z_16 +S 1000,2300,1000,3100,200,*,UP,POLY +S 1700,2600,1700,3200,200,*,UP,POLY +S 2300,700,2300,1900,400,*,DOWN,NDIF +S 2200,700,2200,1900,400,*,DOWN,NDIF +S 400,1800,1200,1800,400,*,RIGHT,ALU1 +S 1400,1400,1400,1900,400,n3,UP,NDIF +S 1000,1200,1000,2100,200,t08,UP,NTRANS +S 1700,1200,1700,2100,200,t06,UP,NTRANS +S 2200,400,2200,800,600,*,DOWN,ALU1 +S 3700,1800,3700,2300,200,*,UP,POLY +S 3800,2200,3800,3800,200,*,DOWN,POLY +S 2700,1800,2700,2300,200,*,UP,POLY +S 2800,2200,2800,3300,200,*,UP,POLY +S 4300,500,4300,1600,600,*,UP,NDIF +S 2000,3200,2000,3200,400,c1,LEFT,CALU1 +S 2800,4000,2800,4800,400,c1,UP,CALU1 +S 3600,3200,3600,3200,400,b,LEFT,CALU1 +S 4400,4000,4400,4800,400,b,UP,CALU1 +S 4300,5600,4300,6800,600,*,UP,ALU1 +S 4400,3200,4400,4900,400,*,UP,ALU1 +S 3600,2400,3600,2400,400,a,LEFT,CALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 1200,4800,1200,4800,400,c2,LEFT,CALU1 +S 400,3200,400,4800,400,c2,UP,CALU1 +S 0,5400,4800,5400,4400,*,RIGHT,NWELL +S 4300,4000,4300,6400,600,*,DOWN,PDIF +S 400,3100,400,4900,400,*,UP,ALU1 +S 400,4900,1300,4900,400,*,RIGHT,ALU1 +S 0,6800,4800,6800,800,vdd,RIGHT,CALU1 +S 0,6800,4800,6800,800,*,RIGHT,ALU1 +S 0,400,4800,400,800,vss,RIGHT,CALU1 +S 0,400,4800,400,800,*,RIGHT,ALU1 +S 2800,4000,2800,4800,600,*,DOWN,ALU1 +S 2300,3100,2300,4000,400,*,UP,ALU1 +S 2300,4000,2900,4000,400,*,RIGHT,ALU1 +S 3000,3300,4400,3300,400,*,RIGHT,ALU1 +S 3500,3200,4400,3200,400,*,RIGHT,ALU1 +S 3000,3200,3500,3200,600,*,RIGHT,ALU1 +S 3500,2400,4400,2400,400,*,RIGHT,ALU1 +S 2000,3200,2300,3200,600,*,LEFT,ALU1 +S 500,3100,500,3300,400,*,DOWN,ALU1 +S 500,3200,1000,3200,600,*,LEFT,POLY +S 3800,3800,3800,6600,200,t03,UP,PTRANS +S 400,5700,2600,5700,400,*,LEFT,ALU1 +S 400,4800,1300,4800,400,*,RIGHT,ALU1 +S 2000,3800,2000,6600,200,t05,UP,PTRANS +S 1000,3800,1000,6600,200,t07,UP,PTRANS +S 3000,3800,3000,6600,200,t01,UP,PTRANS +S 3400,4000,3400,6400,400,n1,UP,PDIF +S 4400,1500,4400,2400,400,*,UP,ALU1 +S 2700,1200,2700,1800,200,t02,UP,NTRANS +S 3700,1200,3700,1800,200,t04,UP,NTRANS +S 1000,1300,1000,1700,200,*,DOWN,POLY +S 2700,800,2700,1200,200,*,DOWN,POLY +S 3700,800,3700,1200,200,*,DOWN,POLY +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 1200,1600,1200,3200,400,z,UP,CALU1 +S 1200,1500,1200,3300,400,*,DOWN,ALU1 +S 1200,1500,3400,1500,400,*,RIGHT,ALU1 +S 1200,1600,3400,1600,400,*,RIGHT,ALU1 +S 1300,4100,1600,4100,400,*,LEFT,ALU1 +S 1300,3300,1300,4100,400,*,DOWN,ALU1 +S 4400,1600,4400,1600,400,a,LEFT,CALU1 +V 500,1800,CONT_DIF_N,* +V 2200,800,CONT_DIF_N,* +V 3200,1500,CONT_DIF_N,* +V 4300,600,CONT_DIF_N,* +V 4300,5600,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 2000,3200,CONT_POLY,* +V 4300,6300,CONT_DIF_P,* +V 3000,3200,CONT_POLY,* +V 500,3200,CONT_POLY,* +V 1500,4100,CONT_DIF_P,* +V 500,5700,CONT_DIF_P,n2 +V 2500,5700,CONT_DIF_P,n2 +V 4000,2400,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi112v0x05.vbe b/pdks/symbolic/vsclib/cells/aoi112v0x05.vbe new file mode 100755 index 000000000..59054caae --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi112v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY aoi112v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 3456; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c1 : NATURAL := 5; + CONSTANT cin_c2 : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 4010; + CONSTANT rdown_b_z : NATURAL := 3920; + CONSTANT rdown_c1_z : NATURAL := 4160; + CONSTANT rdown_c2_z : NATURAL := 4140; + CONSTANT rup_a_z : NATURAL := 5970; + CONSTANT rup_b_z : NATURAL := 5960; + CONSTANT rup_c1_z : NATURAL := 6240; + CONSTANT rup_c2_z : NATURAL := 6270; + CONSTANT tphl_a_z : NATURAL := 84; + CONSTANT tphl_b_z : NATURAL := 77; + CONSTANT tplh_c2_z : NATURAL := 58; + CONSTANT tphl_c1_z : NATURAL := 53; + CONSTANT tplh_b_z : NATURAL := 95; + CONSTANT tplh_c1_z : NATURAL := 64; + CONSTANT tplh_a_z : NATURAL := 103; + CONSTANT tphl_c2_z : NATURAL := 55; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c1 : in BIT; + c2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi112v0x05; + +ARCHITECTURE behaviour_data_flow OF aoi112v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi112v0x05" + SEVERITY WARNING; + z <= not ((a or b) or (c1 and c2)) after 201 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi211v0x05.ap b/pdks/symbolic/vsclib/cells/aoi211v0x05.ap new file mode 100755 index 000000000..3de80cf7b --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi211v0x05.ap @@ -0,0 +1,100 @@ +V ALLIANCE : 6 +H aoi211v0x05,P, 5/ 7/2024,100 +A 0,0,4800,7200 +R 1200,4000,ref_ref,c_40 +R 2000,4000,ref_ref,b_40 +R 2000,4800,ref_ref,b_48 +R 2800,1600,ref_ref,z_16 +R 2800,4800,ref_ref,b_48 +R 3600,1600,ref_ref,z_16 +R 3600,2400,ref_ref,a1_24 +R 3600,4800,ref_ref,a2_48 +R 400,4800,ref_ref,z_48 +R 4400,4000,ref_ref,a2_40 +R 4400,4800,ref_ref,a2_48 +R 400,3200,ref_ref,c_32 +R 1200,2400,ref_ref,z_24 +R 1200,1600,ref_ref,c_16 +R 1200,3200,ref_ref,z_32 +R 400,2400,ref_ref,c_24 +R 2800,3200,ref_ref,a1_32 +R 2000,3200,ref_ref,b_32 +R 400,5600,ref_ref,z_56 +S 2100,500,2100,1800,200,*,UP,TALU7 +S 2800,3200,2800,3700,200,*,DOWN,POLY +S 1800,3100,1800,3600,200,*,DOWN,POLY +S 2600,800,2600,2400,600,*,UP,NDIF +S 2600,400,2600,900,600,*,DOWN,ALU1 +S 2000,4800,2800,4800,600,*,RIGHT,ALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2800,4800,2800,4800,400,b,LEFT,CALU1 +S 3600,1600,3600,1600,400,z,LEFT,CALU1 +S 3600,4800,3600,4800,400,a2,LEFT,CALU1 +S 3600,4800,4400,4800,600,*,RIGHT,ALU1 +S 4400,4000,4400,4800,400,a2,UP,CALU1 +S 400,2400,400,3200,400,c,UP,CALU1 +S 1100,2000,1100,2600,200,t08,UP,NTRANS +S 2100,2000,2100,2600,200,t06,UP,NTRANS +S 1200,2400,1200,4000,400,z,UP,CALU1 +S 400,1600,400,3300,400,*,DOWN,ALU1 +S 400,1600,1300,1600,400,*,RIGHT,ALU1 +S 1100,1600,1100,2000,200,*,UP,POLY +S 500,3200,1100,3200,600,*,RIGHT,POLY +S 600,4100,600,4900,600,*,UP,PDIF +S 400,4100,1200,4100,400,*,LEFT,ALU1 +S 500,4100,500,4900,600,*,UP,ALU1 +S 2000,3100,2000,4900,400,*,DOWN,ALU1 +S 1200,1600,1200,1600,400,c,LEFT,CALU1 +S 1200,2400,1200,4100,400,*,UP,ALU1 +S 2800,3200,2800,3200,400,a1,LEFT,CALU1 +S 2200,1600,2200,2300,400,*,UP,ALU1 +S 2200,1600,4400,1600,400,*,LEFT,ALU1 +S 1200,2400,2200,2400,400,*,LEFT,ALU1 +S 1200,2300,2200,2300,400,*,LEFT,ALU1 +S 3600,2400,3600,2400,400,a1,LEFT,CALU1 +S 4300,3200,4300,4900,600,*,UP,ALU1 +S 2000,3200,2000,4800,400,b,UP,CALU1 +S 400,3200,500,3200,600,*,LEFT,ALU1 +S 0,6800,4800,6800,800,*,RIGHT,ALU1 +S 0,6800,4800,6800,800,vdd,RIGHT,CALU1 +S 0,400,4800,400,800,*,RIGHT,ALU1 +S 0,400,4800,400,800,vss,RIGHT,CALU1 +S 500,800,500,2400,600,*,UP,NDIF +S 500,400,500,900,600,*,DOWN,ALU1 +S 0,5400,4800,5400,4400,*,RIGHT,NWELL +S 1400,4000,1400,6400,400,n2,UP,PDIF +S 1800,3800,1800,6600,200,t05,UP,PTRANS +S 1100,3800,1100,6600,200,t07,UP,PTRANS +S 3800,3800,3800,6600,200,t03,UP,PTRANS +S 2800,3800,2800,6600,200,t01,UP,PTRANS +S 3300,6300,3300,6800,600,*,UP,ALU1 +S 2200,5600,4400,5600,400,*,RIGHT,ALU1 +S 400,4100,400,5700,400,*,UP,ALU1 +S 400,4800,400,5600,400,z,UP,CALU1 +S 3200,2400,3200,3300,400,*,DOWN,ALU1 +S 3200,2400,3700,2400,400,*,RIGHT,ALU1 +S 2800,3200,3200,3200,600,*,RIGHT,ALU1 +S 3800,3200,4400,3200,600,*,LEFT,POLY +S 3400,1200,3400,1700,400,n3,UP,NDIF +S 3800,1000,3800,1900,200,t04,UP,NTRANS +S 3100,1000,3100,1900,200,t02,UP,NTRANS +S 3100,600,3100,1000,200,*,UP,POLY +S 3800,600,3800,1000,200,*,UP,POLY +S 3100,1900,3100,3300,200,*,UP,POLY +S 3800,1900,3800,3000,200,*,UP,POLY +S 2500,800,2500,1200,600,*,UP,NDIF +V 2600,900,CONT_DIF_N,* +V 500,3200,CONT_POLY,* +V 1600,2300,CONT_DIF_N,* +V 1500,600,CONT_BODY_P,* +V 4300,1600,CONT_DIF_N,* +V 600,4100,CONT_DIF_P,* +V 600,4800,CONT_DIF_P,* +V 2000,3200,CONT_POLY,* +V 3000,3200,CONT_POLY,* +V 4300,3200,CONT_POLY,* +V 500,900,CONT_DIF_N,* +V 3300,6300,CONT_DIF_P,* +V 4300,5600,CONT_DIF_P,n1 +V 2300,5600,CONT_DIF_P,n1 +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi211v0x05.vbe b/pdks/symbolic/vsclib/cells/aoi211v0x05.vbe new file mode 100755 index 000000000..3feae8b89 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi211v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY aoi211v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 3456; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT rdown_b_z : NATURAL := 3900; + CONSTANT rdown_c_z : NATURAL := 3910; + CONSTANT rdown_a1_z : NATURAL := 4430; + CONSTANT rdown_a2_z : NATURAL := 4420; + CONSTANT rup_b_z : NATURAL := 5920; + CONSTANT rup_c_z : NATURAL := 5890; + CONSTANT rup_a1_z : NATURAL := 6280; + CONSTANT rup_a2_z : NATURAL := 6310; + CONSTANT tphl_b_z : NATURAL := 65; + CONSTANT tphl_c_z : NATURAL := 52; + CONSTANT tplh_a2_z : NATURAL := 96; + CONSTANT tphl_a1_z : NATURAL := 74; + CONSTANT tplh_c_z : NATURAL := 57; + CONSTANT tplh_a1_z : NATURAL := 104; + CONSTANT tplh_b_z : NATURAL := 76; + CONSTANT tphl_a2_z : NATURAL := 76; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b : in BIT; + c : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi211v0x05; + +ARCHITECTURE behaviour_data_flow OF aoi211v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi211v0x05" + SEVERITY WARNING; + z <= not((b or c) or (a1 and a2)) after 203 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi211v0x1.ap b/pdks/symbolic/vsclib/cells/aoi211v0x1.ap new file mode 100755 index 000000000..19eca1a19 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi211v0x1.ap @@ -0,0 +1,139 @@ +V ALLIANCE : 6 +H aoi211v0x1,P,22/ 6/2024,100 +A 0,0,8800,7200 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,b_32 +R 1200,4000,ref_ref,b_40 +R 2000,1600,ref_ref,z_16 +R 2000,2400,ref_ref,b_24 +R 2000,4800,ref_ref,z_48 +R 2800,1600,ref_ref,z_16 +R 2800,2400,ref_ref,b_24 +R 2800,3200,ref_ref,c_32 +R 3600,1600,ref_ref,z_16 +R 3600,2400,ref_ref,b_24 +R 3600,3200,ref_ref,c_32 +R 3600,4000,ref_ref,c_40 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,1600,ref_ref,z_16 +R 5200,4000,ref_ref,a2_40 +R 6000,3200,ref_ref,a1_32 +R 6000,4000,ref_ref,a2_40 +R 6800,1600,ref_ref,a1_16 +R 6800,2400,ref_ref,a1_24 +R 6800,4000,ref_ref,a2_40 +R 7600,2400,ref_ref,a2_24 +R 7600,3200,ref_ref,a2_32 +S 5400,3100,5400,3600,200,*,DOWN,POLY +S 4800,2700,4800,3300,200,*,UP,POLY +S 4400,3100,4400,3700,200,*,DOWN,POLY +S 0,400,8800,400,800,*,RIGHT,ALU1 +S 0,400,8800,400,800,vss,RIGHT,CALU1 +S 0,5400,8800,5400,4400,*,RIGHT,NWELL +S 0,6800,8800,6800,800,*,RIGHT,ALU1 +S 0,6800,8800,6800,800,vdd,RIGHT,CALU1 +S 1000,2600,1000,3800,200,*,UP,POLY +S 1000,3800,1000,6600,200,t07,UP,PTRANS +S 1100,1000,1100,2000,200,t09,UP,NTRANS +S 1100,600,1100,1000,200,*,UP,POLY +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2400,1200,4100,400,*,UP,ALU1 +S 1200,2400,3700,2400,400,*,RIGHT,ALU1 +S 1200,3200,1200,4000,400,b,UP,CALU1 +S 1300,4000,1300,6400,400,n2a,UP,PDIF +S 1700,3400,2700,3400,200,*,RIGHT,POLY +S 1700,3800,1700,6600,200,t10,UP,PTRANS +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,2400,2000,2400,400,b,LEFT,CALU1 +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2100,1000,2100,2000,200,t12,UP,NTRANS +S 2100,2000,2100,3200,200,*,UP,POLY +S 2100,3200,2500,3200,600,*,RIGHT,POLY +S 2100,600,2100,1000,200,*,UP,POLY +S 2200,4200,2200,4900,600,*,UP,ALU1 +S 2400,3200,3700,3200,400,*,RIGHT,ALU1 +S 2700,3800,2700,6600,200,t11,UP,PTRANS +S 2700,500,2700,1800,600,*,UP,NDIF +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2800,2400,2800,2400,400,b,LEFT,CALU1 +S 2800,3200,2800,3200,400,c,LEFT,CALU1 +S 2800,500,2800,1800,600,*,UP,NDIF +S 3000,4000,3000,6400,400,n2b,UP,PDIF +S 3400,2500,3400,3800,200,*,UP,POLY +S 3400,3800,3400,6600,200,t08,UP,PTRANS +S 3600,1600,3600,1600,400,z,LEFT,CALU1 +S 3600,2400,3600,2400,400,b,LEFT,CALU1 +S 3600,3200,3600,4000,400,c,UP,CALU1 +S 3600,3200,3600,4000,600,*,UP,ALU1 +S 3900,4800,3900,5700,400,*,UP,ALU1 +S 3900,4800,7900,4800,400,*,RIGHT,ALU1 +S 400,1600,400,4900,400,*,UP,ALU1 +S 400,1600,4500,1600,400,*,RIGHT,ALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 400,4800,2300,4800,400,*,RIGHT,ALU1 +S 400,4900,2300,4900,400,*,RIGHT,ALU1 +S 400,5700,3900,5700,400,*,RIGHT,ALU1 +S 4400,1600,4400,1600,400,z,LEFT,CALU1 +S 4400,3800,4400,6600,200,t04,UP,PTRANS +S 4500,4000,7600,4000,400,*,RIGHT,ALU1 +S 4600,3200,4600,4000,600,*,UP,ALU1 +S 4800,500,4800,900,200,*,UP,POLY +S 4800,900,4800,2600,200,t06,UP,NTRANS +S 4900,5600,4900,6800,600,*,UP,ALU1 +S 500,500,500,1800,600,*,UP,NDIF +S 5100,1100,5100,2400,400,n3,UP,NDIF +S 5200,4000,5200,4000,400,a2,LEFT,CALU1 +S 5400,3800,5400,6600,200,t01,UP,PTRANS +S 5500,3200,6800,3200,400,*,RIGHT,ALU1 +S 5500,500,5500,900,200,*,UP,POLY +S 5500,900,5500,2600,200,t03,UP,NTRANS +S 5600,3400,6400,3400,200,*,RIGHT,POLY +S 5900,4800,5900,5600,400,*,UP,ALU1 +S 6000,1100,6000,2400,600,*,UP,NDIF +S 6000,1200,6000,1900,600,*,UP,NDIF +S 6000,3200,6000,3200,400,a1,LEFT,CALU1 +S 6000,4000,6000,4000,400,a2,LEFT,CALU1 +S 6000,400,6000,2000,400,*,UP,ALU1 +S 6400,3800,6400,6600,200,t02,UP,PTRANS +S 6800,1500,6800,3200,400,*,UP,ALU1 +S 6800,1600,6800,2400,400,a1,UP,CALU1 +S 6800,4000,6800,4000,400,a2,LEFT,CALU1 +S 6900,5600,6900,6800,600,*,UP,ALU1 +S 7000,600,7800,600,600,*,RIGHT,PTIE +S 7400,3100,7400,3800,200,*,UP,POLY +S 7400,3800,7400,6600,200,t05,UP,PTRANS +S 7600,2300,7600,4000,400,*,UP,ALU1 +S 7600,2400,7600,3200,400,a2,UP,CALU1 +S 7900,4800,7900,5700,400,*,UP,ALU1 +S 7900,4900,7900,5600,600,*,UP,PDIF +V 1200,2600,CONT_POLY,* +V 1600,1600,CONT_DIF_N,* +V 2200,4200,CONT_DIF_P,* +V 2200,4900,CONT_DIF_P,* +V 2500,3200,CONT_POLY,* +V 2700,600,CONT_DIF_N,* +V 3600,2400,CONT_POLY,* +V 3900,4900,CONT_DIF_P,n1 +V 3900,5600,CONT_DIF_P,n1 +V 4300,1600,CONT_DIF_N,* +V 4600,3200,CONT_POLY,* +V 4900,5600,CONT_DIF_P,* +V 4900,6300,CONT_DIF_P,* +V 500,5700,CONT_DIF_P,n1 +V 500,600,CONT_DIF_N,* +V 5600,3200,CONT_POLY,* +V 5900,4800,CONT_DIF_P,n1 +V 5900,5500,CONT_DIF_P,n1 +V 6000,1200,CONT_DIF_N,* +V 6000,1900,CONT_DIF_N,* +V 6900,5600,CONT_DIF_P,* +V 6900,6300,CONT_DIF_P,* +V 7000,600,CONT_BODY_P,* +V 7600,3200,CONT_POLY,* +V 7800,600,CONT_BODY_P,* +V 7900,4900,CONT_DIF_P,n1 +V 7900,5600,CONT_DIF_P,n1 +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi211v0x1.vbe b/pdks/symbolic/vsclib/cells/aoi211v0x1.vbe new file mode 100755 index 000000000..fd428c8cb --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi211v0x1.vbe @@ -0,0 +1,44 @@ +ENTITY aoi211v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 6336; + CONSTANT cin_b : NATURAL := 8; + CONSTANT cin_c : NATURAL := 8; + CONSTANT cin_a1 : NATURAL := 9; + CONSTANT cin_a2 : NATURAL := 9; + CONSTANT rdown_b_z : NATURAL := 2330; + CONSTANT rdown_c_z : NATURAL := 2330; + CONSTANT rdown_a1_z : NATURAL := 2320; + CONSTANT rdown_a2_z : NATURAL := 2320; + CONSTANT rup_b_z : NATURAL := 2960; + CONSTANT rup_c_z : NATURAL := 2940; + CONSTANT rup_a1_z : NATURAL := 3130; + CONSTANT rup_a2_z : NATURAL := 3140; + CONSTANT tphl_b_z : NATURAL := 67; + CONSTANT tphl_c_z : NATURAL := 50; + CONSTANT tplh_a2_z : NATURAL := 88; + CONSTANT tphl_a1_z : NATURAL := 71; + CONSTANT tplh_c_z : NATURAL := 48; + CONSTANT tplh_a1_z : NATURAL := 95; + CONSTANT tplh_b_z : NATURAL := 68; + CONSTANT tphl_a2_z : NATURAL := 73; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + b : in BIT; + c : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi211v0x1; + +ARCHITECTURE behaviour_data_flow OF aoi211v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi211v0x1" + SEVERITY WARNING; + z <= not((b or c) or (a1 and a2)) after 137 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi211v0x2.ap b/pdks/symbolic/vsclib/cells/aoi211v0x2.ap new file mode 100755 index 000000000..27dd3bf8c --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi211v0x2.ap @@ -0,0 +1,243 @@ +V ALLIANCE : 6 +H aoi211v0x2,P,22/ 6/2024,100 +A 0,0,16800,7200 +R 9200,3200,ref_ref,a2_32 +R 9200,1600,ref_ref,z_16 +R 8400,3200,ref_ref,a2_32 +R 8400,2400,ref_ref,a2_24 +R 8400,1600,ref_ref,z_16 +R 7600,1600,ref_ref,z_16 +R 6800,3200,ref_ref,b_32 +R 6800,2400,ref_ref,b_24 +R 6800,1600,ref_ref,z_16 +R 6000,2400,ref_ref,b_24 +R 6000,1600,ref_ref,z_16 +R 5200,4800,ref_ref,z_48 +R 5200,3200,ref_ref,c_32 +R 5200,2400,ref_ref,b_24 +R 5200,1600,ref_ref,z_16 +R 4400,4800,ref_ref,z_48 +R 4400,3200,ref_ref,c_32 +R 4400,2400,ref_ref,b_24 +R 4400,1600,ref_ref,z_16 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 3600,4800,ref_ref,z_48 +R 3600,3200,ref_ref,c_32 +R 3600,2400,ref_ref,b_24 +R 3600,1600,ref_ref,z_16 +R 2800,4800,ref_ref,z_48 +R 2800,3200,ref_ref,c_32 +R 2800,1600,ref_ref,z_16 +R 2000,4800,ref_ref,z_48 +R 2000,4000,ref_ref,c_40 +R 2000,3200,ref_ref,c_32 +R 2000,2400,ref_ref,c_24 +R 2000,1600,ref_ref,z_16 +R 13200,4000,ref_ref,a1_40 +R 13200,3200,ref_ref,a1_32 +R 13200,2400,ref_ref,a1_24 +R 13200,1600,ref_ref,a1_16 +R 12400,2400,ref_ref,a1_24 +R 1200,4800,ref_ref,z_48 +R 1200,1600,ref_ref,z_16 +R 11600,3200,ref_ref,a2_32 +R 11600,2400,ref_ref,a1_24 +R 11600,1600,ref_ref,z_16 +R 10800,3200,ref_ref,a2_32 +R 10800,2400,ref_ref,a1_24 +R 10800,1600,ref_ref,z_16 +R 10000,3200,ref_ref,a2_32 +R 10000,2400,ref_ref,a1_24 +R 10000,1600,ref_ref,z_16 +S 5100,3100,5100,3800,200,*,DOWN,POLY +S 5500,2800,5500,3300,200,*,UP,POLY +S 9800,5200,9800,5600,200,*,UP,POLY +S 9800,3800,9800,5200,200,t10,UP,PTRANS +S 9400,2400,9400,2800,600,*,UP,POLY +S 9300,6100,9300,6700,600,*,UP,NTIE +S 9300,4100,9300,4900,400,*,UP,ALU1 +S 9300,2400,13200,2400,400,*,RIGHT,ALU1 +S 9200,3200,9200,3200,400,a2,LEFT,CALU1 +S 9200,2800,10800,2800,200,*,RIGHT,POLY +S 9200,1600,9200,1600,400,z,LEFT,CALU1 +S 8800,5200,8800,5600,200,*,UP,POLY +S 8800,3800,8800,5200,200,t11,UP,PTRANS +S 8400,2400,8400,3200,600,*,UP,ALU1 +S 8400,2400,8400,3200,400,a2,UP,CALU1 +S 8400,1600,8400,1600,400,z,LEFT,CALU1 +S 8300,4900,8300,6800,600,*,UP,ALU1 +S 8300,4000,8300,6400,400,*,UP,PDIF +S 8300,3200,11700,3200,400,*,RIGHT,ALU1 +S 8100,500,8100,2200,1200,*,UP,PTIE +S 7800,3800,7800,6600,200,t07,UP,PTRANS +S 7800,3400,11800,3400,200,*,RIGHT,POLY +S 7600,1600,7600,1600,400,z,LEFT,CALU1 +S 7300,4100,7300,5700,400,*,UP,ALU1 +S 7300,4100,11300,4100,400,*,RIGHT,ALU1 +S 6900,2400,6900,3300,400,*,UP,ALU1 +S 6800,3800,6800,6600,200,t17,UP,PTRANS +S 6800,2400,6800,3800,200,*,UP,POLY +S 6800,2400,6800,3300,400,*,UP,ALU1 +S 6800,2400,6800,3200,400,b,UP,CALU1 +S 6800,1600,6800,1600,400,z,LEFT,CALU1 +S 6400,4000,6400,6400,400,n2d,UP,PDIF +S 6100,500,6100,2400,600,*,UP,NDIF +S 6100,3800,6100,6600,200,t22,UP,PTRANS +S 6000,2400,6000,2400,400,b,LEFT,CALU1 +S 6000,1600,6000,1600,400,z,LEFT,CALU1 +S 5600,4100,5600,4800,600,*,UP,ALU1 +S 5500,600,5500,2600,200,t23,UP,NTRANS +S 5200,4800,5200,4800,400,z,LEFT,CALU1 +S 5200,3200,5200,3200,400,c,LEFT,CALU1 +S 5200,2400,5200,2400,400,b,LEFT,CALU1 +S 5200,1600,5200,1600,400,z,LEFT,CALU1 +S 5100,3800,5100,6600,200,t21,UP,PTRANS +S 5100,3400,6100,3400,200,*,RIGHT,POLY +S 4700,4000,4700,6400,400,n2c,UP,PDIF +S 4500,600,4500,2600,200,t18,UP,NTRANS +S 4400,4800,4400,4800,400,z,LEFT,CALU1 +S 4400,3800,4400,6600,200,t16,UP,PTRANS +S 4400,3200,4400,3200,400,c,LEFT,CALU1 +S 4400,3000,4400,3800,200,*,UP,POLY +S 4400,2400,4400,2400,400,b,LEFT,CALU1 +S 4400,1600,4400,1600,400,z,LEFT,CALU1 +S 400,5700,7300,5700,400,*,RIGHT,ALU1 +S 400,4800,5700,4800,400,*,RIGHT,ALU1 +S 400,2400,400,4000,400,z,UP,CALU1 +S 400,1600,400,4800,400,*,UP,ALU1 +S 400,1600,12100,1600,400,*,RIGHT,ALU1 +S 3900,500,3900,2400,600,*,UP,NDIF +S 3600,4800,3600,4800,400,z,LEFT,CALU1 +S 3600,3200,3600,3200,400,c,LEFT,CALU1 +S 3600,2400,3600,2400,400,b,LEFT,CALU1 +S 3600,1600,3600,1600,400,z,LEFT,CALU1 +S 3400,3800,3400,6600,200,t15,UP,PTRANS +S 3400,3000,3400,3800,200,*,UP,POLY +S 3400,3000,3400,3000,200,*,LEFT,POLY +S 3300,3000,4500,3000,200,*,RIGHT,POLY +S 3300,2400,3300,3000,200,*,UP,POLY +S 3000,4000,3000,6400,400,n2b,UP,PDIF +S 3000,2400,6900,2400,400,*,RIGHT,ALU1 +S 2800,4800,2800,4800,400,z,LEFT,CALU1 +S 2800,3200,2800,3200,400,c,LEFT,CALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2700,3800,2700,6600,200,t20,UP,PTRANS +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2000,2400,2000,4000,600,*,UP,ALU1 +S 2000,2400,2000,4000,400,c,UP,CALU1 +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 1900,3200,5400,3200,400,*,RIGHT,ALU1 +S 1700,3800,1700,6600,200,t19,UP,PTRANS +S 1700,3400,2700,3400,200,*,RIGHT,POLY +S 1700,3200,2000,3200,600,*,RIGHT,POLY +S 16300,5500,16300,6800,400,*,UP,ALU1 +S 16300,4000,16300,6400,600,*,UP,PDIF +S 15800,500,15800,2200,1400,*,UP,PTIE +S 15800,3800,15800,6600,200,t04,UP,PTRANS +S 15300,4100,15300,5700,400,*,UP,ALU1 +S 14800,3800,14800,6600,200,t03,UP,PTRANS +S 14300,5600,14300,6800,600,*,UP,ALU1 +S 14200,400,14200,1700,600,*,UP,ALU1 +S 14100,900,14100,2200,1000,*,UP,NDIF +S 13800,3800,13800,6600,200,t02,UP,PTRANS +S 13300,4800,13300,5600,400,*,UP,ALU1 +S 13200,700,13200,2400,200,t06,UP,NTRANS +S 13200,3200,13300,3200,600,*,RIGHT,ALU1 +S 13200,300,13200,700,200,*,UP,POLY +S 13200,2400,13200,3400,200,*,UP,POLY +S 13200,1600,13200,4000,400,a1,UP,CALU1 +S 13200,1500,13200,4100,400,*,UP,ALU1 +S 1300,4000,1300,6400,400,n2a,UP,PDIF +S 12800,900,12800,2200,400,n3b,UP,NDIF +S 12800,3800,12800,6600,200,t01,UP,PTRANS +S 12800,3400,15800,3400,200,*,RIGHT,POLY +S 12500,700,12500,2400,200,t13,UP,NTRANS +S 12500,300,12500,700,200,*,UP,POLY +S 12400,2400,12400,2400,400,a1,LEFT,CALU1 +S 12300,5600,12300,6800,600,*,UP,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 11800,3800,11800,6600,200,t09,UP,PTRANS +S 11600,3200,11600,3200,400,a2,LEFT,CALU1 +S 11600,2800,11600,3400,600,*,UP,POLY +S 11600,2400,11600,2400,400,a1,LEFT,CALU1 +S 11600,1600,11600,1600,400,z,LEFT,CALU1 +S 11500,700,11500,2400,200,t12,UP,NTRANS +S 11500,300,11500,700,200,*,UP,POLY +S 11500,2800,12500,2800,200,*,RIGHT,POLY +S 11300,4800,15300,4800,400,*,RIGHT,ALU1 +S 11300,4100,11300,5700,400,*,UP,ALU1 +S 11100,900,11100,2200,400,n3a,UP,NDIF +S 10800,700,10800,2400,200,t05,UP,NTRANS +S 10800,3800,10800,6600,200,t08,UP,PTRANS +S 10800,3200,10800,3200,400,a2,LEFT,CALU1 +S 10800,300,10800,700,200,*,UP,POLY +S 10800,2400,10800,2400,400,a1,LEFT,CALU1 +S 10800,1600,10800,1600,400,z,LEFT,CALU1 +S 10300,4900,10300,6800,600,*,UP,ALU1 +S 10300,4000,10300,6400,400,*,UP,PDIF +S 10200,500,10200,2200,600,*,UP,NDIF +S 1000,500,1000,1800,1400,*,UP,PTIE +S 1000,3800,1000,6600,200,t14,UP,PTRANS +S 1000,2400,3100,2400,200,*,RIGHT,POLY +S 1000,2400,1000,3800,200,*,UP,POLY +S 10000,3200,10000,3200,400,a2,LEFT,CALU1 +S 10000,2400,10000,2400,400,a1,LEFT,CALU1 +S 10000,1600,10000,1600,400,z,LEFT,CALU1 +S 0,6800,16800,6800,800,vdd,RIGHT,CALU1 +S 0,6800,16800,6800,800,*,RIGHT,ALU1 +S 0,5400,16800,5400,4400,*,RIGHT,NWELL +S 0,400,16800,400,800,vss,RIGHT,CALU1 +S 0,400,16800,400,800,*,RIGHT,ALU1 +V 9400,2400,CONT_POLY,* +V 9300,6600,CONT_BODY_N,* +V 9300,4800,CONT_DIF_P,n1 +V 9300,4100,CONT_DIF_P,n1 +V 8400,3200,CONT_POLY,* +V 8300,6300,CONT_DIF_P,* +V 8300,4900,CONT_DIF_P,* +V 8100,600,CONT_BODY_P,* +V 7300,5600,CONT_DIF_P,n1 +V 7300,4900,CONT_DIF_P,n1 +V 7300,4200,CONT_DIF_P,n1 +V 6900,2500,CONT_POLY,* +V 6100,600,CONT_DIF_N,* +V 600,600,CONT_BODY_P,* +V 5600,4800,CONT_DIF_P,* +V 5600,4100,CONT_DIF_P,* +V 5300,3200,CONT_POLY,* +V 500,5700,CONT_DIF_P,n1 +V 5000,1600,CONT_DIF_N,* +V 3900,600,CONT_DIF_N,* +V 3900,5700,CONT_DIF_P,n1 +V 3100,2400,CONT_POLY,* +V 2200,4800,CONT_DIF_P,* +V 2000,3200,CONT_POLY,* +V 16300,6300,CONT_DIF_P,* +V 16300,5600,CONT_DIF_P,* +V 16200,600,CONT_BODY_P,* +V 15400,600,CONT_BODY_P,* +V 15300,5600,CONT_DIF_P,n1 +V 15300,4900,CONT_DIF_P,n1 +V 15300,4200,CONT_DIF_P,n1 +V 14300,6300,CONT_DIF_P,* +V 14300,5600,CONT_DIF_P,* +V 14200,1700,CONT_DIF_N,* +V 14200,1000,CONT_DIF_N,* +V 1400,600,CONT_BODY_P,* +V 13300,5500,CONT_DIF_P,n1 +V 13300,4800,CONT_DIF_P,n1 +V 13300,3200,CONT_POLY,* +V 12300,6300,CONT_DIF_P,* +V 12300,5600,CONT_DIF_P,* +V 12000,1600,CONT_DIF_N,* +V 11600,3200,CONT_POLY,* +V 11300,5600,CONT_DIF_P,n1 +V 11300,4900,CONT_DIF_P,n1 +V 11300,4200,CONT_DIF_P,n1 +V 10300,6300,CONT_DIF_P,* +V 10300,4900,CONT_DIF_P,* +V 10200,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi211v0x2.vbe b/pdks/symbolic/vsclib/cells/aoi211v0x2.vbe new file mode 100755 index 000000000..d741f7ec3 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi211v0x2.vbe @@ -0,0 +1,44 @@ +ENTITY aoi211v0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 12096; + CONSTANT cin_b : NATURAL := 15; + CONSTANT cin_c : NATURAL := 15; + CONSTANT cin_a1 : NATURAL := 17; + CONSTANT cin_a2 : NATURAL := 16; + CONSTANT rdown_b_z : NATURAL := 1160; + CONSTANT rdown_c_z : NATURAL := 1160; + CONSTANT rdown_a1_z : NATURAL := 1160; + CONSTANT rdown_a2_z : NATURAL := 1160; + CONSTANT rup_b_z : NATURAL := 1480; + CONSTANT rup_c_z : NATURAL := 1470; + CONSTANT rup_a1_z : NATURAL := 1560; + CONSTANT rup_a2_z : NATURAL := 1570; + CONSTANT tphl_b_z : NATURAL := 66; + CONSTANT tphl_c_z : NATURAL := 50; + CONSTANT tplh_a2_z : NATURAL := 85; + CONSTANT tphl_a1_z : NATURAL := 70; + CONSTANT tplh_c_z : NATURAL := 48; + CONSTANT tplh_a1_z : NATURAL := 93; + CONSTANT tplh_b_z : NATURAL := 67; + CONSTANT tphl_a2_z : NATURAL := 72; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + b : in BIT; + c : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi211v0x2; + +ARCHITECTURE behaviour_data_flow OF aoi211v0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi211v0x2" + SEVERITY WARNING; + z <= not((b or c) or (a1 and a2)) after 102 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi211v5x05.ap b/pdks/symbolic/vsclib/cells/aoi211v5x05.ap new file mode 100755 index 000000000..0c121ad50 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi211v5x05.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H aoi211v5x05,P,23/ 6/2024,100 +A 0,0,5600,7200 +R 4400,4800,ref_ref,a2_48 +R 4400,4000,ref_ref,a2_40 +R 4400,2400,ref_ref,a1_24 +R 4400,1600,ref_ref,z_16 +R 400,5600,ref_ref,z_56 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 3600,4800,ref_ref,a2_48 +R 3600,3200,ref_ref,a1_32 +R 3600,2400,ref_ref,a1_24 +R 3600,1600,ref_ref,z_16 +R 2800,4800,ref_ref,b_48 +R 2800,1600,ref_ref,z_16 +R 2000,4800,ref_ref,b_48 +R 2000,4000,ref_ref,b_40 +R 2000,2400,ref_ref,c_24 +R 2000,1600,ref_ref,z_16 +R 1200,4000,ref_ref,c_40 +R 1200,3200,ref_ref,c_32 +R 1200,1600,ref_ref,z_16 +S 3000,3200,3000,3600,200,*,DOWN,POLY +S 2000,3200,2000,3600,200,*,DOWN,POLY +S 800,4900,800,5700,600,*,UP,PDIF +S 500,500,500,1700,600,*,UP,NDIF +S 4400,4000,4400,4800,400,a2,UP,CALU1 +S 4400,3200,4400,4900,400,*,UP,ALU1 +S 4400,2400,4400,2400,400,a1,LEFT,CALU1 +S 4400,1600,4400,1600,400,z,LEFT,CALU1 +S 400,5700,900,5700,400,*,RIGHT,ALU1 +S 400,4900,900,4900,400,*,RIGHT,ALU1 +S 400,2400,400,5600,400,z,UP,CALU1 +S 400,1600,4600,1600,400,*,RIGHT,ALU1 +S 400,1600,400,5700,400,*,UP,ALU1 +S 4000,2200,4000,3500,200,*,UP,POLY +S 3600,4800,4400,4800,600,*,RIGHT,ALU1 +S 3600,4800,3600,4800,400,a2,LEFT,CALU1 +S 3600,4100,3600,6400,600,*,UP,PDIF +S 3600,2400,3600,3300,400,*,UP,ALU1 +S 3600,2400,3600,3200,400,a1,UP,CALU1 +S 3600,1600,3600,1600,400,z,LEFT,CALU1 +S 3500,2400,4500,2400,400,*,RIGHT,ALU1 +S 3500,2400,3500,3300,400,*,UP,ALU1 +S 3300,2200,3300,3300,200,*,UP,POLY +S 3100,3300,3600,3300,400,*,RIGHT,ALU1 +S 3000,3900,3000,6600,200,t01,UP,PTRANS +S 2800,4800,2800,4800,400,b,LEFT,CALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2100,900,2100,1300,200,*,UP,POLY +S 2100,1900,2100,3300,200,*,UP,POLY +S 2100,1300,2100,1900,200,t06,UP,NTRANS +S 2000,4800,2800,4800,600,*,RIGHT,ALU1 +S 2000,4000,2000,4800,400,b,UP,CALU1 +S 2000,3900,2000,6600,200,t05,UP,PTRANS +S 2000,2400,2000,2400,400,c,LEFT,CALU1 +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 1600,4100,1600,6400,400,n2,UP,PDIF +S 1300,3900,1300,6600,200,t07,UP,PTRANS +S 1300,2500,1300,3900,200,*,UP,POLY +S 1200,3200,1200,4000,400,c,UP,CALU1 +S 1200,2400,2100,2400,400,*,RIGHT,ALU1 +S 1200,2400,1200,4100,400,*,UP,ALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1100,900,1100,1300,200,*,UP,POLY +S 1100,1300,1100,1900,200,t08,UP,NTRANS +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 2100,3900,2100,4900,600,*,UP,ALU1 +S 2200,3200,2200,4900,400,*,UP,ALU1 +S 4000,3300,4400,3300,600,*,LEFT,POLY +S 3600,1500,3600,2000,400,n3,UP,NDIF +S 4000,1300,4000,2200,200,t04,UP,NTRANS +S 3300,1300,3300,2200,200,t02,UP,NTRANS +S 2700,500,2700,2000,600,*,UP,NDIF +S 3300,900,3300,1300,200,*,UP,POLY +S 4000,900,4000,1300,200,*,UP,POLY +S 3500,6300,3500,6800,600,*,UP,ALU1 +S 4000,3900,4000,6600,200,t03,UP,PTRANS +S 2400,5600,4600,5600,400,*,RIGHT,ALU1 +V 800,5700,CONT_DIF_P,* +V 800,4900,CONT_DIF_P,* +V 500,600,CONT_DIF_N,* +V 5000,600,CONT_BODY_P,* +V 4400,3300,CONT_POLY,* +V 3200,3300,CONT_POLY,* +V 2700,600,CONT_DIF_N,* +V 2500,5600,CONT_DIF_P,n1 +V 2200,3300,CONT_POLY,* +V 1600,1600,CONT_DIF_N,* +V 1200,2500,CONT_POLY,* +V 4500,1600,CONT_DIF_N,* +V 3500,6300,CONT_DIF_P,* +V 4500,5600,CONT_DIF_P,n1 +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi211v5x05.vbe b/pdks/symbolic/vsclib/cells/aoi211v5x05.vbe new file mode 100755 index 000000000..8c27bb905 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi211v5x05.vbe @@ -0,0 +1,44 @@ +ENTITY aoi211v5x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 4; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT rdown_b_z : NATURAL := 3870; + CONSTANT rdown_c_z : NATURAL := 3880; + CONSTANT rdown_a1_z : NATURAL := 4370; + CONSTANT rdown_a2_z : NATURAL := 4360; + CONSTANT rup_b_z : NATURAL := 6120; + CONSTANT rup_c_z : NATURAL := 6110; + CONSTANT rup_a1_z : NATURAL := 6500; + CONSTANT rup_a2_z : NATURAL := 6520; + CONSTANT tphl_b_z : NATURAL := 63; + CONSTANT tphl_c_z : NATURAL := 52; + CONSTANT tplh_a2_z : NATURAL := 97; + CONSTANT tphl_a1_z : NATURAL := 73; + CONSTANT tplh_c_z : NATURAL := 58; + CONSTANT tplh_a1_z : NATURAL := 106; + CONSTANT tplh_b_z : NATURAL := 76; + CONSTANT tphl_a2_z : NATURAL := 75; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b : in BIT; + c : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi211v5x05; + +ARCHITECTURE behaviour_data_flow OF aoi211v5x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi211v5x05" + SEVERITY WARNING; + z <= not((b or c) or (a1 and a2)) after 205 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi21a2bv0x05.ap b/pdks/symbolic/vsclib/cells/aoi21a2bv0x05.ap new file mode 100755 index 000000000..6183feee4 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi21a2bv0x05.ap @@ -0,0 +1,122 @@ +V ALLIANCE : 6 +H aoi21a2bv0x05,P, 5/ 7/2024,100 +A 0,0,7200,7200 +R 3600,4800,ref_ref,z_48 +R 1200,3200,ref_ref,b_32 +R 1200,2400,ref_ref,b_24 +R 6000,4000,ref_ref,a1_40 +R 6800,4000,ref_ref,a1_40 +R 6800,3200,ref_ref,a1_32 +R 2000,5600,ref_ref,a2_56 +R 1200,5600,ref_ref,a2_56 +R 1200,4800,ref_ref,a2_48 +R 2000,3200,ref_ref,b_32 +R 2000,4000,ref_ref,b_40 +R 4400,2400,ref_ref,z_24 +R 4400,3200,ref_ref,z_32 +R 3600,4000,ref_ref,z_40 +R 4400,4000,ref_ref,a1_40 +S 3300,2400,3300,2800,800,*,UP,TALU7 +S 3100,4400,3100,5700,800,*,DOWN,TALU8 +S 4400,1600,4400,2500,800,*,UP,TALU7 +S 3100,1700,3100,2700,800,*,DOWN,TALU7 +S 5400,2800,5400,3200,200,*,UP,POLY +S 5000,3200,5000,3600,200,*,DOWN,POLY +S 2200,3000,2200,4800,200,*,DOWN,POLY +S 1000,1800,1000,4300,200,*,UP,POLY +S 3500,3900,3500,4900,400,*,UP,ALU1 +S 3500,4000,4400,4000,600,*,LEFT,ALU1 +S 3600,3900,3600,4900,400,*,UP,ALU1 +S 0,5400,7200,5400,4400,*,RIGHT,NWELL +S 1200,2400,1200,3200,400,b,UP,CALU1 +S 1200,2300,1200,3300,400,*,UP,ALU1 +S 1200,3200,2000,3200,600,*,RIGHT,ALU1 +S 2000,3100,2000,4100,400,*,UP,ALU1 +S 5900,4100,6800,4100,400,*,RIGHT,ALU1 +S 5900,4000,6800,4000,400,*,RIGHT,ALU1 +S 6000,4000,6000,4000,400,a1,LEFT,CALU1 +S 6800,3200,6800,4000,400,a1,UP,CALU1 +S 3600,4000,3600,4000,400,z,LEFT,CALU1 +S 4400,2400,4400,4000,400,z,UP,CALU1 +S 2000,3200,2000,4000,400,b,UP,CALU1 +S 2000,5600,2000,5600,400,a2,LEFT,CALU1 +S 1200,4800,1200,5600,400,a2,UP,CALU1 +S 400,5100,500,5100,600,*,LEFT,ALU1 +S 1000,800,1000,1200,200,*,DOWN,POLY +S 2200,1600,2200,2000,200,*,DOWN,POLY +S 4400,1600,4400,2000,200,*,DOWN,POLY +S 5400,1500,5400,1900,200,*,DOWN,POLY +S 6100,1500,6100,1900,200,*,DOWN,POLY +S 6200,6200,6200,6600,200,*,UP,POLY +S 5000,5400,5000,5800,200,*,UP,POLY +S 4000,5400,4000,5800,200,*,UP,POLY +S 2200,6000,2200,6400,200,*,UP,POLY +S 1000,6000,1000,6400,200,*,UP,POLY +S 3800,6600,4600,6600,600,*,RIGHT,NTIE +S 5800,600,6600,600,600,*,LEFT,PTIE +S 3700,500,3700,2400,600,*,UP,NDIF +S 6600,2100,6600,2400,600,*,DOWN,NDIF +S 6700,4900,6700,5600,600,*,DOWN,PDIF +S 6700,4900,6700,5600,600,*,DOWN,ALU1 +S 5600,4000,5600,6000,400,*,DOWN,PDIF +S 4400,4900,6800,4900,400,*,RIGHT,ALU1 +S 5600,5000,5600,6000,600,*,DOWN,PDIF +S 6200,4600,6200,6200,200,t01,UP,PTRANS +S 6800,3100,6800,4100,400,*,DOWN,ALU1 +S 6100,2600,6100,4000,200,*,UP,POLY +S 6600,400,6600,2300,400,*,DOWN,ALU1 +S 3800,500,3800,2400,600,*,UP,NDIF +S 1600,5000,1600,6700,600,*,DOWN,PDIF +S 5600,5800,5600,6800,400,*,UP,ALU1 +S 1200,5600,2000,5600,600,*,RIGHT,ALU1 +S 1200,4100,1200,5700,400,*,UP,ALU1 +S 400,1500,5800,1500,400,*,LEFT,ALU1 +S 1000,1200,1000,1800,200,t10,UP,NTRANS +S 400,1500,400,5200,400,*,UP,ALU1 +S 2200,4800,2200,6000,200,t07,UP,PTRANS +S 1000,4800,1000,6000,200,t08,UP,PTRANS +S 1600,500,1600,2400,600,*,UP,NDIF +S 2200,2000,2200,2600,200,t09,UP,NTRANS +S 2700,3200,3700,3200,400,*,LEFT,ALU1 +S 3600,3200,4000,3200,600,*,RIGHT,POLY +S 4400,2300,4400,4100,400,*,UP,ALU1 +S 4400,2300,5000,2300,400,*,LEFT,ALU1 +S 4400,2000,4400,2600,200,t06,UP,NTRANS +S 4000,3000,4400,3000,200,*,LEFT,POLY +S 2700,2200,2700,5200,400,*,UP,ALU1 +S 5800,1500,5800,3200,400,*,DOWN,ALU1 +S 5100,3200,5800,3200,400,*,RIGHT,ALU1 +S 5400,1900,5400,2600,200,t04,UP,NTRANS +S 5700,2100,5700,2400,400,n2,UP,NDIF +S 6100,1900,6100,2600,200,t02,UP,NTRANS +S 5000,3800,5000,5400,200,t03,UP,PTRANS +S 4000,3800,4000,5400,200,t05,UP,PTRANS +S 0,6800,7200,6800,800,vdd,RIGHT,CALU1 +S 0,6800,7200,6800,800,*,RIGHT,ALU1 +S 0,400,7200,400,800,vss,RIGHT,CALU1 +S 0,400,7200,400,800,*,RIGHT,ALU1 +V 3600,3200,CONT_POLY,bn +V 2700,2300,CONT_DIF_N,bn +V 2700,5100,CONT_DIF_P,bn +V 3800,6600,CONT_BODY_N,* +V 4600,6600,CONT_BODY_N,* +V 2700,600,CONT_BODY_P,* +V 5800,600,CONT_BODY_P,* +V 6700,5600,CONT_DIF_P,n1 +V 4500,4900,CONT_DIF_P,n1 +V 6700,4900,CONT_DIF_P,n1 +V 6300,4000,CONT_POLY,* +V 1600,6600,CONT_DIF_P,* +V 500,1500,CONT_DIF_N,a2n +V 2000,3200,CONT_POLY,* +V 500,5100,CONT_DIF_P,a2n +V 1200,4200,CONT_POLY,* +V 4900,2300,CONT_DIF_N,* +V 3800,600,CONT_DIF_N,* +V 5200,3200,CONT_POLY,a2n +V 6600,2200,CONT_DIF_N,* +V 5600,5900,CONT_DIF_P,* +V 3500,4100,CONT_DIF_P,* +V 1600,600,CONT_DIF_N,* +V 6600,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi21a2bv0x05.vbe b/pdks/symbolic/vsclib/cells/aoi21a2bv0x05.vbe new file mode 100755 index 000000000..82360f453 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi21a2bv0x05.vbe @@ -0,0 +1,38 @@ +ENTITY aoi21a2bv0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5184; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 5400; + CONSTANT rdown_a2_z : NATURAL := 5400; + CONSTANT rdown_b_z : NATURAL := 3890; + CONSTANT rup_a1_z : NATURAL := 7300; + CONSTANT rup_a2_z : NATURAL := 7330; + CONSTANT rup_b_z : NATURAL := 6690; + CONSTANT tphl_a1_z : NATURAL := 58; + CONSTANT tpll_a2_z : NATURAL := 110; + CONSTANT tpll_b_z : NATURAL := 85; + CONSTANT tphh_b_z : NATURAL := 76; + CONSTANT tphh_a2_z : NATURAL := 105; + CONSTANT tplh_a1_z : NATURAL := 78; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi21a2bv0x05; + +ARCHITECTURE behaviour_data_flow OF aoi21a2bv0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi21a2bv0x05" + SEVERITY WARNING; + z <= (not a1 or a2) and b after 235 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi21a2bv5x05.ap b/pdks/symbolic/vsclib/cells/aoi21a2bv5x05.ap new file mode 100755 index 000000000..0926353d6 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi21a2bv5x05.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H aoi21a2bv5x05,P, 5/ 7/2024,100 +A 0,0,7200,7200 +R 3600,4800,ref_ref,z_48 +R 1200,2400,ref_ref,b_24 +R 6000,4000,ref_ref,a1_40 +R 6800,4000,ref_ref,a1_40 +R 6800,3200,ref_ref,a1_32 +R 2000,5600,ref_ref,a2_56 +R 1200,5600,ref_ref,a2_56 +R 1200,4800,ref_ref,a2_48 +R 2000,3200,ref_ref,b_32 +R 2000,4000,ref_ref,b_40 +R 4400,2400,ref_ref,z_24 +R 4400,3200,ref_ref,z_32 +R 4400,4000,ref_ref,a1_40 +R 1200,4000,ref_ref,a2_40 +S 3200,4400,3200,6200,800,*,UP,TALU8 +S 4500,1600,4500,2000,800,*,UP,TALU7 +S 3400,1600,3400,2800,800,*,DOWN,TALU7 +S 4400,2900,4400,3300,200,*,UP,POLY +S 5400,2900,5400,3200,200,*,UP,POLY +S 1000,1800,1000,4500,200,*,UP,POLY +S 0,5400,7200,5400,4400,*,RIGHT,NWELL +S 2000,3100,2000,4100,400,*,UP,ALU1 +S 5900,4100,6800,4100,400,*,RIGHT,ALU1 +S 5900,4000,6800,4000,400,*,RIGHT,ALU1 +S 6000,4000,6000,4000,400,a1,LEFT,CALU1 +S 6800,3200,6800,4000,400,a1,UP,CALU1 +S 4400,2400,4400,4000,400,z,UP,CALU1 +S 2000,3200,2000,4000,400,b,UP,CALU1 +S 2000,5600,2000,5600,400,a2,LEFT,CALU1 +S 1000,800,1000,1200,200,*,DOWN,POLY +S 4400,1600,4400,2000,200,*,DOWN,POLY +S 5400,1500,5400,1900,200,*,DOWN,POLY +S 6100,1500,6100,1900,200,*,DOWN,POLY +S 5800,600,6600,600,600,*,LEFT,PTIE +S 6600,2100,6600,2400,600,*,DOWN,NDIF +S 6700,4900,6700,5600,600,*,DOWN,PDIF +S 6700,4900,6700,5600,600,*,DOWN,ALU1 +S 6800,3100,6800,4100,400,*,DOWN,ALU1 +S 6600,400,6600,2300,400,*,DOWN,ALU1 +S 3800,500,3800,2400,600,*,UP,NDIF +S 1200,5600,2000,5600,600,*,RIGHT,ALU1 +S 400,1500,5800,1500,400,*,LEFT,ALU1 +S 1000,1200,1000,1800,200,t10,UP,NTRANS +S 2700,3200,3700,3200,400,*,LEFT,ALU1 +S 4400,2300,4400,4100,400,*,UP,ALU1 +S 4400,2300,5000,2300,400,*,LEFT,ALU1 +S 4400,2000,4400,2600,200,t06,UP,NTRANS +S 4000,3000,4400,3000,200,*,LEFT,POLY +S 5800,1500,5800,3200,400,*,DOWN,ALU1 +S 5100,3200,5800,3200,400,*,RIGHT,ALU1 +S 5400,1900,5400,2600,200,t04,UP,NTRANS +S 5700,2100,5700,2400,400,n2,UP,NDIF +S 6100,1900,6100,2600,200,t02,UP,NTRANS +S 0,6800,7200,6800,800,vdd,RIGHT,CALU1 +S 0,6800,7200,6800,800,*,RIGHT,ALU1 +S 0,400,7200,400,800,vss,RIGHT,CALU1 +S 0,400,7200,400,800,*,RIGHT,ALU1 +S 4600,4900,6800,4900,400,*,RIGHT,ALU1 +S 6200,4300,6200,5900,200,t01,UP,PTRANS +S 5200,4300,5200,5900,200,t03,UP,PTRANS +S 4200,4300,4200,5900,200,t05,UP,PTRANS +S 5700,5600,5700,6800,600,*,UP,ALU1 +S 6700,3100,6700,4100,400,*,DOWN,ALU1 +S 4700,4900,4700,5600,600,*,DOWN,ALU1 +S 6200,5900,6200,6300,200,*,UP,POLY +S 5200,5900,5200,6300,200,*,UP,POLY +S 4200,5900,4200,6300,200,*,UP,POLY +S 2200,4700,2200,5900,200,t07,UP,PTRANS +S 2800,2200,2800,3200,600,*,UP,ALU1 +S 2300,1500,2300,1900,200,*,DOWN,POLY +S 2300,1900,2300,2500,200,t09,UP,NTRANS +S 1600,500,1600,2300,600,*,UP,NDIF +S 1700,500,1700,2300,600,*,UP,NDIF +S 1900,3100,2300,3100,600,*,RIGHT,POLY +S 1200,3900,1200,5700,400,*,UP,ALU1 +S 1200,3100,2000,3100,400,*,LEFT,ALU1 +S 1200,2300,1200,3100,400,*,UP,ALU1 +S 1200,2400,1200,2400,400,b,LEFT,CALU1 +S 1000,4700,1000,5900,200,t08,UP,PTRANS +S 400,5000,500,5000,600,*,LEFT,ALU1 +S 400,1500,400,5100,400,*,UP,ALU1 +S 2700,3200,2700,5100,400,*,UP,ALU1 +S 1600,4900,1600,6700,600,*,DOWN,PDIF +S 1000,5900,1000,6300,200,*,UP,POLY +S 2200,5900,2200,6300,200,*,UP,POLY +S 2200,3200,2200,4700,200,*,DOWN,POLY +S 6100,2600,6100,3900,200,*,UP,POLY +S 6100,3700,6700,3700,600,*,LEFT,POLY +S 5200,3200,5200,4300,200,*,DOWN,POLY +S 4200,3200,4200,4300,200,*,DOWN,POLY +S 3600,3200,4200,3200,600,*,RIGHT,POLY +S 3600,4100,4400,4100,400,*,LEFT,ALU1 +S 3700,4100,3700,5000,400,*,UP,ALU1 +S 3600,4100,3600,5000,400,*,UP,ALU1 +S 3600,4800,3600,4800,400,z,LEFT,CALU1 +S 1200,4000,1200,5600,400,a2,UP,CALU1 +V 3600,3200,CONT_POLY,bn +V 2700,600,CONT_BODY_P,* +V 5800,600,CONT_BODY_P,* +V 6700,5600,CONT_DIF_P,n1 +V 6700,4900,CONT_DIF_P,n1 +V 1600,6600,CONT_DIF_P,* +V 500,1500,CONT_DIF_N,a2n +V 4900,2300,CONT_DIF_N,* +V 3800,600,CONT_DIF_N,* +V 5200,3200,CONT_POLY,a2n +V 6600,2200,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 6600,600,CONT_BODY_P,* +V 4700,4900,CONT_DIF_P,n1 +V 3200,6600,CONT_BODY_N,* +V 6700,3700,CONT_POLY,* +V 5700,5600,CONT_DIF_P,* +V 4700,5600,CONT_DIF_P,n1 +V 3700,4600,CONT_DIF_P,* +V 2800,2200,CONT_DIF_N,bn +V 1900,3100,CONT_POLY,* +V 1200,4100,CONT_POLY,* +V 500,5000,CONT_DIF_P,a2n +V 2700,5000,CONT_DIF_P,bn +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi21a2bv5x05.vbe b/pdks/symbolic/vsclib/cells/aoi21a2bv5x05.vbe new file mode 100755 index 000000000..bbfdc4536 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi21a2bv5x05.vbe @@ -0,0 +1,38 @@ +ENTITY aoi21a2bv5x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5184; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 5410; + CONSTANT rdown_a2_z : NATURAL := 5400; + CONSTANT rdown_b_z : NATURAL := 3900; + CONSTANT rup_a1_z : NATURAL := 7300; + CONSTANT rup_a2_z : NATURAL := 7330; + CONSTANT rup_b_z : NATURAL := 6690; + CONSTANT tphl_a1_z : NATURAL := 59; + CONSTANT tpll_a2_z : NATURAL := 113; + CONSTANT tpll_b_z : NATURAL := 86; + CONSTANT tphh_b_z : NATURAL := 78; + CONSTANT tphh_a2_z : NATURAL := 108; + CONSTANT tplh_a1_z : NATURAL := 79; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi21a2bv5x05; + +ARCHITECTURE behaviour_data_flow OF aoi21a2bv5x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi21a2bv5x05" + SEVERITY WARNING; + z <= (not a1 or a2) and b after 237 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi21a2v0x05.ap b/pdks/symbolic/vsclib/cells/aoi21a2v0x05.ap new file mode 100755 index 000000000..7dce754c9 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi21a2v0x05.ap @@ -0,0 +1,108 @@ +V ALLIANCE : 6 +H aoi21a2v0x05,P, 5/ 7/2024,100 +A 0,0,5600,7200 +R 3600,3200,ref_ref,a1_32 +R 5200,3200,ref_ref,a2_32 +R 5200,4000,ref_ref,a2_40 +R 5200,4800,ref_ref,a2_48 +R 4400,4800,ref_ref,a2_48 +R 2800,4000,ref_ref,a1_40 +R 1200,3200,ref_ref,b_32 +R 2000,3200,ref_ref,b_32 +R 1200,4000,ref_ref,b_40 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 2800,4800,ref_ref,a1_48 +R 2000,1600,ref_ref,z_16 +R 1200,1600,ref_ref,z_16 +S 3800,4400,3800,6700,600,*,DOWN,TALU8 +S 2000,2500,2000,3800,200,*,UP,POLY +S 1000,3200,1000,3600,200,*,DOWN,POLY +S 2500,5200,2500,6700,600,*,UP,PDIF +S 4400,4800,4400,4800,400,a2,LEFT,CALU1 +S 5200,3200,5200,4800,400,a2,UP,CALU1 +S 2800,4000,2800,4800,400,a1,DOWN,CALU1 +S 2700,4100,3200,4100,400,*,LEFT,ALU1 +S 2700,4000,3200,4000,400,*,LEFT,ALU1 +S 3200,3200,3200,4100,400,*,UP,ALU1 +S 2800,4000,2800,4800,600,*,DOWN,ALU1 +S 3200,3200,3700,3200,400,*,LEFT,ALU1 +S 3600,3200,3600,3200,400,a1,LEFT,CALU1 +S 2000,3200,2000,3200,400,b,LEFT,CALU1 +S 1200,3200,1200,4000,400,b,UP,CALU1 +S 1200,3100,1200,4100,400,*,DOWN,ALU1 +S 1200,3200,2100,3200,400,*,LEFT,ALU1 +S 2100,2500,4400,2500,400,*,RIGHT,ALU1 +S 4000,4100,4400,4100,400,*,RIGHT,ALU1 +S 4400,1800,4400,4100,400,*,UP,ALU1 +S 600,6600,1400,6600,600,*,RIGHT,NTIE +S 500,4100,500,4800,600,*,UP,PDIF +S 500,4000,500,4900,400,*,UP,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,1600,2000,1600,600,*,RIGHT,ALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 2500,4000,2500,6700,400,*,UP,PDIF +S 2000,5400,2000,5800,200,*,UP,POLY +S 2000,3800,2000,5400,200,t03,UP,PTRANS +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 1500,5000,1500,5700,400,*,UP,ALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1000,3800,1000,5400,200,t05,UP,PTRANS +S 1500,5700,3600,5700,400,*,RIGHT,ALU1 +S 3000,4800,3000,6400,200,t01,UP,PTRANS +S 3000,6400,3000,6800,200,*,UP,POLY +S 4600,3800,4600,5000,200,t07,UP,PTRANS +S 4200,1500,4200,2100,200,t08,UP,NTRANS +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 1300,1200,1300,1800,200,t06,UP,NTRANS +S 2300,1200,2300,1900,200,t04,UP,NTRANS +S 3000,1200,3000,1900,200,t02,UP,NTRANS +S 2600,1500,2600,1700,400,n2,UP,NDIF +S 4300,4800,5200,4800,400,*,LEFT,ALU1 +S 5100,3200,5200,3200,600,*,RIGHT,ALU1 +S 4600,3200,4900,3200,600,*,LEFT,POLY +S 4400,1800,4800,1800,400,*,LEFT,ALU1 +S 3600,400,3600,1600,400,*,DOWN,ALU1 +S 4200,1100,4200,1500,200,*,DOWN,POLY +S 5100,5800,5100,6800,400,*,UP,ALU1 +S 5200,4000,5200,6000,400,*,DOWN,PDIF +S 5100,4000,5100,6000,400,*,DOWN,PDIF +S 3000,800,3000,1200,200,*,DOWN,POLY +S 2300,800,2300,1200,200,*,DOWN,POLY +S 1300,800,1300,1200,200,*,DOWN,POLY +S 700,500,700,1600,600,*,UP,NDIF +S 600,500,600,1600,600,*,UP,NDIF +S 3600,1400,3600,1900,600,*,UP,NDIF +S 1000,5400,1000,5800,200,*,UP,POLY +S 3000,1900,3000,4800,200,*,UP,POLY +S 1300,1800,1300,3200,200,*,UP,POLY +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 4200,3000,4600,3000,200,*,RIGHT,POLY +S 4200,2100,4200,3000,200,*,UP,POLY +S 4300,4900,5200,4900,400,*,LEFT,ALU1 +S 5200,3100,5200,4900,400,*,UP,ALU1 +V 2500,6600,CONT_DIF_P,* +V 1200,3200,CONT_POLY,* +V 2200,2500,CONT_POLY,a2n +V 4700,1800,CONT_DIF_N,a2n +V 4100,4100,CONT_DIF_P,a2n +V 700,600,CONT_DIF_N,* +V 600,6600,CONT_BODY_N,* +V 500,4800,CONT_DIF_P,* +V 500,4100,CONT_DIF_P,* +V 3200,4000,CONT_POLY,* +V 1500,5100,CONT_DIF_P,n1 +V 1400,6600,CONT_BODY_N,* +V 3600,1500,CONT_DIF_N,* +V 3500,5700,CONT_DIF_P,n1 +V 5000,600,CONT_BODY_P,* +V 1800,1500,CONT_DIF_N,* +V 5100,3200,CONT_POLY,* +V 5100,5900,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi21a2v0x05.vbe b/pdks/symbolic/vsclib/cells/aoi21a2v0x05.vbe new file mode 100755 index 000000000..21ed01b94 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi21a2v0x05.vbe @@ -0,0 +1,38 @@ +ENTITY aoi21a2v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 5390; + CONSTANT rdown_a2_z : NATURAL := 5380; + CONSTANT rdown_b_z : NATURAL := 3880; + CONSTANT rup_a1_z : NATURAL := 7290; + CONSTANT rup_a2_z : NATURAL := 7310; + CONSTANT rup_b_z : NATURAL := 6650; + CONSTANT tphl_a1_z : NATURAL := 57; + CONSTANT tpll_a2_z : NATURAL := 104; + CONSTANT tphl_b_z : NATURAL := 39; + CONSTANT tplh_b_z : NATURAL := 48; + CONSTANT tphh_a2_z : NATURAL := 98; + CONSTANT tplh_a1_z : NATURAL := 74; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi21a2v0x05; + +ARCHITECTURE behaviour_data_flow OF aoi21a2v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi21a2v0x05" + SEVERITY WARNING; + z <= not ((a1 and not a2) or b) after 220 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi21bv0x05.ap b/pdks/symbolic/vsclib/cells/aoi21bv0x05.ap new file mode 100755 index 000000000..bfb83d686 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi21bv0x05.ap @@ -0,0 +1,106 @@ +V ALLIANCE : 6 +H aoi21bv0x05,P, 5/ 7/2024,100 +A 0,0,5600,7200 +R 1200,2400,ref_ref,z_24 +R 2000,2400,ref_ref,a2_24 +R 3600,2400,ref_ref,a2_24 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 2800,4800,ref_ref,a1_48 +R 2800,2400,ref_ref,a2_24 +R 2800,1600,ref_ref,a2_16 +R 1200,1600,ref_ref,z_16 +R 2000,4000,ref_ref,a1_40 +R 5200,3200,ref_ref,b_32 +R 4400,4800,ref_ref,b_48 +R 5200,4000,ref_ref,b_40 +R 2800,4000,ref_ref,a1_40 +R 5200,4800,ref_ref,b_48 +S 3800,4400,3800,6700,400,*,DOWN,TALU8 +S 2500,4000,2500,6600,400,*,UP,PDIF +S 2500,5500,2500,6600,600,*,UP,PDIF +S 1000,3100,1000,3600,200,*,DOWN,POLY +S 500,4000,500,4900,400,*,UP,ALU1 +S 1200,1600,1200,2400,400,z,UP,CALU1 +S 3600,400,3600,1600,400,*,DOWN,ALU1 +S 400,2400,1200,2400,600,*,RIGHT,ALU1 +S 2000,2400,3600,2400,600,*,LEFT,ALU1 +S 500,400,500,1600,400,*,DOWN,ALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 400,2300,400,4900,400,*,UP,ALU1 +S 1200,1500,1900,1500,400,*,RIGHT,ALU1 +S 1200,1500,1200,2400,400,*,DOWN,ALU1 +S 3000,1800,3000,4800,200,*,UP,POLY +S 2600,1300,2600,1600,400,n2,UP,NDIF +S 3600,1300,3600,1900,600,*,UP,NDIF +S 2000,2400,2000,2400,400,a2,LEFT,CALU1 +S 2800,1500,2800,2400,400,*,UP,ALU1 +S 2000,2400,2000,3800,200,*,UP,POLY +S 2300,700,2300,1100,200,*,DOWN,POLY +S 3000,1100,3000,1800,200,t02,UP,NTRANS +S 3000,700,3000,1100,200,*,DOWN,POLY +S 2300,1100,2300,1800,200,t04,UP,NTRANS +S 600,6600,1400,6600,600,*,RIGHT,NTIE +S 500,4100,500,4800,600,*,UP,PDIF +S 2800,1600,2800,2400,400,a2,UP,CALU1 +S 2000,5400,2000,5800,200,*,UP,POLY +S 2000,3800,2000,5400,200,t03,UP,PTRANS +S 1500,5000,1500,5700,400,*,UP,ALU1 +S 1000,3800,1000,5400,200,t05,UP,PTRANS +S 3600,2400,3600,2400,400,a2,LEFT,CALU1 +S 1500,5700,3600,5700,400,*,RIGHT,ALU1 +S 3000,4800,3000,6400,200,t01,UP,PTRANS +S 3000,6400,3000,6800,200,*,UP,POLY +S 4600,3800,4600,5000,200,t07,UP,PTRANS +S 4200,1500,4200,2100,200,t08,UP,NTRANS +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 1300,1200,1300,1800,200,t06,UP,NTRANS +S 2000,4000,2000,4000,400,a1,LEFT,CALU1 +S 2800,4000,2800,4900,400,*,UP,ALU1 +S 1900,4000,3300,4000,400,*,RIGHT,ALU1 +S 1100,3200,4400,3200,400,*,RIGHT,ALU1 +S 4400,4800,4400,4800,400,b,LEFT,CALU1 +S 4300,4800,5200,4800,400,*,LEFT,ALU1 +S 4100,3200,4100,4100,600,*,DOWN,ALU1 +S 5100,3200,5200,3200,600,*,RIGHT,ALU1 +S 4600,3200,4900,3200,600,*,LEFT,POLY +S 4400,1800,4400,3200,400,*,UP,ALU1 +S 4400,1800,4800,1800,400,*,LEFT,ALU1 +S 4200,1100,4200,1500,200,*,DOWN,POLY +S 5100,5800,5100,6800,400,*,UP,ALU1 +S 5200,4000,5200,6000,400,*,DOWN,PDIF +S 5100,4000,5100,6000,400,*,DOWN,PDIF +S 1300,800,1300,1200,200,*,DOWN,POLY +S 1000,5400,1000,5800,200,*,UP,POLY +S 1300,1800,1300,3200,200,*,UP,POLY +S 2800,4000,2800,4800,400,a1,UP,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 4200,3000,4600,3000,200,*,RIGHT,POLY +S 4200,2100,4200,3000,200,*,UP,POLY +S 4300,4900,5200,4900,400,*,LEFT,ALU1 +S 5200,3100,5200,4900,400,*,UP,ALU1 +S 5200,3200,5200,4800,400,b,UP,CALU1 +V 2500,6400,CONT_DIF_P,* +V 500,1500,CONT_DIF_N,* +V 2200,2400,CONT_POLY,* +V 600,6600,CONT_BODY_N,* +V 500,4800,CONT_DIF_P,* +V 500,4100,CONT_DIF_P,* +V 3200,4000,CONT_POLY,* +V 1500,5100,CONT_DIF_P,n1 +V 1400,6600,CONT_BODY_N,* +V 3600,1500,CONT_DIF_N,* +V 3500,5700,CONT_DIF_P,n1 +V 4100,4100,CONT_DIF_P,bn +V 5000,600,CONT_BODY_P,* +V 1800,1500,CONT_DIF_N,* +V 5100,3200,CONT_POLY,* +V 4700,1800,CONT_DIF_N,bn +V 1200,3200,CONT_POLY,bn +V 5100,5900,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi21bv0x05.vbe b/pdks/symbolic/vsclib/cells/aoi21bv0x05.vbe new file mode 100755 index 000000000..91f26cfe3 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi21bv0x05.vbe @@ -0,0 +1,38 @@ +ENTITY aoi21bv0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_a2 : NATURAL := 4; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 5380; + CONSTANT rdown_a2_z : NATURAL := 5370; + CONSTANT rdown_b_z : NATURAL := 3900; + CONSTANT rup_a1_z : NATURAL := 7290; + CONSTANT rup_a2_z : NATURAL := 7330; + CONSTANT rup_b_z : NATURAL := 6680; + CONSTANT tphl_a1_z : NATURAL := 57; + CONSTANT tphl_a2_z : NATURAL := 59; + CONSTANT tpll_b_z : NATURAL := 88; + CONSTANT tphh_b_z : NATURAL := 79; + CONSTANT tplh_a2_z : NATURAL := 70; + CONSTANT tplh_a1_z : NATURAL := 78; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi21bv0x05; + +ARCHITECTURE behaviour_data_flow OF aoi21bv0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi21bv0x05" + SEVERITY WARNING; + z <= not ((a1 and a2) or not b) after 222 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi21v0x05.ap b/pdks/symbolic/vsclib/cells/aoi21v0x05.ap new file mode 100755 index 000000000..db46c69c1 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi21v0x05.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 6 +H aoi21v0x05,P,23/ 6/2024,100 +A 0,0,4000,7200 +R 1200,4000,ref_ref,b_40 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 3600,4000,ref_ref,a1_40 +R 3600,1600,ref_ref,a2_16 +R 2800,4800,ref_ref,a1_48 +R 2800,4000,ref_ref,a1_40 +R 2800,2400,ref_ref,a2_24 +R 2800,1600,ref_ref,a2_16 +R 2000,4000,ref_ref,b_40 +R 2000,1600,ref_ref,z_16 +R 1200,3200,ref_ref,b_32 +R 1200,1600,ref_ref,z_16 +S 2500,5000,2500,6700,600,*,UP,PDIF +S 1000,3100,1000,3500,200,*,DOWN,POLY +S 3000,2200,3000,4100,200,*,UP,POLY +S 1300,2100,1300,3200,200,*,UP,POLY +S 1200,3200,1200,4000,400,b,UP,CALU1 +S 700,500,700,1900,600,*,UP,NDIF +S 600,6600,1400,6600,600,*,RIGHT,NTIE +S 600,500,600,1900,600,*,UP,NDIF +S 500,4100,500,4800,600,*,UP,PDIF +S 500,4000,500,4900,400,*,UP,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,1600,2000,1600,600,*,RIGHT,ALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 3600,500,3600,2000,400,*,UP,NDIF +S 3600,4000,3600,4000,400,a1,LEFT,CALU1 +S 3600,1600,3600,1600,400,a2,LEFT,CALU1 +S 3500,500,3500,2000,400,*,UP,NDIF +S 3500,4900,3500,5600,600,*,UP,PDIF +S 3500,4800,3500,5700,400,*,UP,ALU1 +S 3000,6200,3000,6600,200,*,UP,POLY +S 3000,4600,3000,6200,200,t01,UP,PTRANS +S 3000,1500,3000,2200,200,t02,UP,NTRANS +S 2800,4000,3600,4000,600,*,RIGHT,ALU1 +S 2800,4000,2800,4800,400,a1,UP,CALU1 +S 2800,3900,2800,4900,400,*,UP,ALU1 +S 2800,1600,3600,1600,600,*,RIGHT,ALU1 +S 2800,1600,2800,2400,400,a2,UP,CALU1 +S 2800,1500,2800,2700,400,*,UP,ALU1 +S 2600,1700,2600,2000,400,n2,UP,NDIF +S 2500,4000,2500,6700,400,*,UP,PDIF +S 2300,1500,2300,2200,200,t04,UP,NTRANS +S 2200,2700,2200,2800,600,*,UP,ALU1 +S 2100,2700,2800,2700,400,*,RIGHT,ALU1 +S 2000,5400,2000,5800,200,*,UP,POLY +S 2000,4000,2000,4000,400,b,LEFT,CALU1 +S 2000,3800,2000,5400,200,t03,UP,PTRANS +S 2000,2900,2000,3800,200,*,UP,POLY +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 1800,1500,1800,1900,400,*,UP,ALU1 +S 1700,600,2500,600,600,*,RIGHT,PTIE +S 1500,5700,3500,5700,400,*,RIGHT,ALU1 +S 1500,5000,1500,5700,400,*,UP,ALU1 +S 1300,1500,1300,2100,200,t06,UP,NTRANS +S 1200,4000,2000,4000,600,*,RIGHT,ALU1 +S 1200,3100,1200,4100,400,*,UP,ALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1000,5400,1000,5800,200,*,UP,POLY +S 1000,3800,1000,5400,200,t05,UP,PTRANS +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 0,6800,4000,6800,800,*,RIGHT,ALU1 +S 0,5400,4000,5400,4400,*,RIGHT,NWELL +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,400,4000,400,800,*,RIGHT,ALU1 +V 2500,6600,CONT_DIF_P,* +V 700,600,CONT_DIF_N,* +V 600,6600,CONT_BODY_N,* +V 500,4800,CONT_DIF_P,* +V 500,4100,CONT_DIF_P,* +V 3500,600,CONT_DIF_N,* +V 3500,5600,CONT_DIF_P,n1 +V 3500,4900,CONT_DIF_P,n1 +V 3200,4000,CONT_POLY,* +V 2500,600,CONT_BODY_P,* +V 2200,2800,CONT_POLY,* +V 1800,1800,CONT_DIF_N,* +V 1700,600,CONT_BODY_P,* +V 1500,5100,CONT_DIF_P,n1 +V 1400,6600,CONT_BODY_N,* +V 1200,3200,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi21v0x05.vbe b/pdks/symbolic/vsclib/cells/aoi21v0x05.vbe new file mode 100755 index 000000000..6e6cfadf8 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi21v0x05.vbe @@ -0,0 +1,38 @@ +ENTITY aoi21v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 5380; + CONSTANT rdown_a2_z : NATURAL := 5370; + CONSTANT rdown_b_z : NATURAL := 3880; + CONSTANT rup_a1_z : NATURAL := 7280; + CONSTANT rup_a2_z : NATURAL := 7320; + CONSTANT rup_b_z : NATURAL := 6640; + CONSTANT tphl_a1_z : NATURAL := 57; + CONSTANT tphl_a2_z : NATURAL := 58; + CONSTANT tphl_b_z : NATURAL := 39; + CONSTANT tplh_b_z : NATURAL := 49; + CONSTANT tplh_a2_z : NATURAL := 69; + CONSTANT tplh_a1_z : NATURAL := 76; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi21v0x05; + +ARCHITECTURE behaviour_data_flow OF aoi21v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi21v0x05" + SEVERITY WARNING; + z <= not (((a1 and a2) or b)) after 207 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi22v0x05.ap b/pdks/symbolic/vsclib/cells/aoi22v0x05.ap new file mode 100755 index 000000000..bc9e6b3aa --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi22v0x05.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 6 +H aoi22v0x05,P, 5/ 7/2024,100 +A 0,0,5600,7200 +R 1200,1600,ref_ref,z_16 +R 1200,4000,ref_ref,b2_40 +R 2000,1600,ref_ref,z_16 +R 2000,2400,ref_ref,b1_24 +R 2000,3200,ref_ref,b2_32 +R 2800,2400,ref_ref,b1_24 +R 2800,4000,ref_ref,a2_40 +R 3600,1600,ref_ref,b1_16 +R 3600,3200,ref_ref,a1_32 +R 3600,4000,ref_ref,a2_40 +R 3600,4800,ref_ref,a2_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,2400,ref_ref,a1_24 +R 4400,3200,ref_ref,a1_32 +R 4400,4000,ref_ref,a2_40 +S 4500,600,5100,600,600,*,RIGHT,PTIE +S 3100,2000,3100,4000,200,*,UP,POLY +S 4200,3200,4200,4100,200,*,UP,POLY +S 3800,2000,3800,3200,200,*,UP,POLY +S 1400,2300,1400,2700,200,*,UP,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,2600,1000,4600,200,*,UP,POLY +S 1000,4600,1000,6200,200,t05,UP,PTRANS +S 1000,6200,1000,6600,200,*,UP,POLY +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2400,1200,2700,400,*,UP,ALU1 +S 1200,2400,3600,2400,400,*,RIGHT,ALU1 +S 1200,4000,1200,4000,400,b2,LEFT,CALU1 +S 1200,4000,1900,4000,600,*,RIGHT,ALU1 +S 1400,1300,1400,2000,200,t06,UP,NTRANS +S 1400,900,1400,1300,200,*,UP,POLY +S 1800,1500,1800,1800,400,n1,UP,NDIF +S 1900,3200,1900,4100,400,*,UP,ALU1 +S 1900,3200,2100,3200,400,*,RIGHT,ALU1 +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,2400,2000,2400,400,b1,LEFT,CALU1 +S 2000,3200,2000,3200,400,b2,LEFT,CALU1 +S 2000,4600,2000,6200,200,t07,UP,PTRANS +S 2000,6200,2000,6600,200,*,UP,POLY +S 2100,1300,2100,2000,200,t08,UP,NTRANS +S 2100,2000,2100,4000,200,*,UP,POLY +S 2100,900,2100,1300,200,*,UP,POLY +S 2500,4900,2500,5700,400,*,UP,ALU1 +S 2700,4000,4500,4000,400,*,RIGHT,ALU1 +S 2800,2400,2800,2400,400,b1,LEFT,CALU1 +S 2800,4000,2800,4000,400,a2,LEFT,CALU1 +S 2900,3200,4500,3200,400,*,RIGHT,ALU1 +S 3000,4600,3000,6200,200,t03,UP,PTRANS +S 3000,6200,3000,6600,200,*,UP,POLY +S 3100,1300,3100,2000,200,t04,UP,NTRANS +S 3100,900,3100,1300,200,*,UP,POLY +S 3400,1500,3400,1800,400,n2,UP,NDIF +S 3600,1500,3600,2400,400,*,UP,ALU1 +S 3600,1600,3600,1600,400,b1,LEFT,CALU1 +S 3600,3200,3600,3200,400,a1,LEFT,CALU1 +S 3600,4000,3600,4800,400,a2,UP,CALU1 +S 3600,4000,3600,4900,400,*,UP,ALU1 +S 3600,4300,3600,6700,400,*,UP,PDIF +S 3600,4800,3600,6700,600,*,UP,PDIF +S 3800,1300,3800,2000,200,t02,UP,NTRANS +S 3800,900,3800,1300,200,*,UP,POLY +S 400,1500,2700,1500,400,*,RIGHT,ALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 400,1600,2700,1600,400,*,RIGHT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,4900,1600,4900,400,*,RIGHT,ALU1 +S 400,5700,4800,5700,400,*,RIGHT,ALU1 +S 4200,4100,4200,5700,200,t01,UP,PTRANS +S 4400,2300,4400,3200,400,*,UP,ALU1 +S 4400,2400,4400,3200,400,a1,UP,CALU1 +S 4400,4000,4400,4000,400,a2,LEFT,CALU1 +S 4400,400,4400,1600,600,*,UP,ALU1 +S 4500,1500,4500,1800,600,*,UP,NDIF +S 4500,2300,4500,3200,400,*,UP,ALU1 +S 4500,6600,5100,6600,600,*,RIGHT,NTIE +S 4700,4700,4700,5400,600,*,UP,PDIF +S 4700,4700,4700,5700,600,*,UP,ALU1 +S 700,500,700,1800,600,*,UP,NDIF +S 800,500,800,1800,600,*,UP,NDIF +V 1200,2600,CONT_POLY,* +V 1500,4900,CONT_DIF_P,* +V 1900,4000,CONT_POLY,* +V 2500,5000,CONT_DIF_P,n3 +V 2500,5700,CONT_DIF_P,n3 +V 2600,1600,CONT_DIF_N,* +V 2900,4000,CONT_POLY,* +V 3600,6600,CONT_DIF_P,* +V 4000,3200,CONT_POLY,* +V 4400,1600,CONT_DIF_N,* +V 4700,4700,CONT_DIF_P,n3 +V 4700,5400,CONT_DIF_P,n3 +V 4800,6600,CONT_BODY_N,* +V 4900,600,CONT_BODY_P,* +V 500,5700,CONT_DIF_P,n3 +V 800,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi22v0x05.vbe b/pdks/symbolic/vsclib/cells/aoi22v0x05.vbe new file mode 100755 index 000000000..7516b0c0e --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi22v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY aoi22v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_b1 : NATURAL := 4; + CONSTANT cin_b2 : NATURAL := 3; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT rdown_b1_z : NATURAL := 5320; + CONSTANT rdown_b2_z : NATURAL := 5290; + CONSTANT rdown_a1_z : NATURAL := 5410; + CONSTANT rdown_a2_z : NATURAL := 5400; + CONSTANT rup_b1_z : NATURAL := 6650; + CONSTANT rup_b2_z : NATURAL := 6660; + CONSTANT rup_a1_z : NATURAL := 6740; + CONSTANT rup_a2_z : NATURAL := 6760; + CONSTANT tphl_b1_z : NATURAL := 48; + CONSTANT tphl_b2_z : NATURAL := 49; + CONSTANT tplh_a2_z : NATURAL := 82; + CONSTANT tphl_a1_z : NATURAL := 69; + CONSTANT tplh_b2_z : NATURAL := 55; + CONSTANT tplh_a1_z : NATURAL := 88; + CONSTANT tplh_b1_z : NATURAL := 62; + CONSTANT tphl_a2_z : NATURAL := 71; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi22v0x05; + +ARCHITECTURE behaviour_data_flow OF aoi22v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi22v0x05" + SEVERITY WARNING; + z <= not (((b1 and b2) or (a1 and a2))) after 216 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi22v0x1.ap b/pdks/symbolic/vsclib/cells/aoi22v0x1.ap new file mode 100755 index 000000000..98bff2514 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi22v0x1.ap @@ -0,0 +1,100 @@ +V ALLIANCE : 6 +H aoi22v0x1,P,22/ 6/2024,100 +A 0,0,5600,7200 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,b1_32 +R 1200,4000,ref_ref,b1_40 +R 2000,2400,ref_ref,b1_24 +R 2000,4000,ref_ref,b2_40 +R 2800,2400,ref_ref,a1_24 +R 2800,4000,ref_ref,b2_40 +R 2800,4800,ref_ref,b2_48 +R 3600,1600,ref_ref,a1_16 +R 3600,3200,ref_ref,a2_32 +R 3600,4000,ref_ref,a2_40 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,2400,ref_ref,a1_24 +R 4400,3200,ref_ref,a1_32 +R 4400,4800,ref_ref,a2_48 +S 1300,2100,1300,2700,200,*,UP,POLY +S 1000,2500,1000,3200,200,*,DOWN,POLY +S 2000,3200,2000,3800,200,*,DOWN,POLY +S 2100,2800,2100,3500,200,*,UP,POLY +S 4200,2300,4200,2900,200,*,DOWN,POLY +S 3900,2300,4600,2300,200,*,RIGHT,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,2500,1000,3900,200,*,UP,POLY +S 1000,3900,1000,6600,200,t05,UP,PTRANS +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2500,1200,4100,400,*,UP,ALU1 +S 1200,2500,2000,2500,400,*,RIGHT,ALU1 +S 1200,3200,1200,4000,400,b1,UP,CALU1 +S 1300,300,1300,700,200,*,UP,POLY +S 1300,700,1300,1900,200,t06,UP,NTRANS +S 1700,900,1700,1700,600,n1,UP,NDIF +S 2000,2300,2000,2500,400,*,UP,ALU1 +S 2000,2400,2000,2400,400,b1,LEFT,CALU1 +S 2000,3900,2000,6600,200,t07,UP,PTRANS +S 2000,4000,2000,4000,400,b2,LEFT,CALU1 +S 2000,4000,2800,4000,600,*,RIGHT,ALU1 +S 2100,1900,2100,3300,200,*,UP,POLY +S 2100,300,2100,700,200,*,UP,POLY +S 2100,700,2100,1900,200,t08,UP,NTRANS +S 2200,3200,2200,4100,400,*,UP,ALU1 +S 2800,2300,2800,2500,400,*,UP,ALU1 +S 2800,2300,4400,2300,400,*,RIGHT,ALU1 +S 2800,2400,2800,2400,400,a1,LEFT,CALU1 +S 2800,3900,2800,4900,400,*,UP,ALU1 +S 2800,4000,2800,4800,400,b2,UP,CALU1 +S 3000,3100,3000,3900,200,*,UP,POLY +S 3000,3900,3000,6600,200,t03,UP,PTRANS +S 3100,1900,3100,3300,200,*,UP,POLY +S 3100,300,3100,700,200,*,UP,POLY +S 3100,3200,3600,3200,400,*,RIGHT,ALU1 +S 3100,700,3100,1900,200,t04,UP,NTRANS +S 3500,900,3500,1700,600,n2,UP,NDIF +S 3600,1500,3600,2300,400,*,UP,ALU1 +S 3600,1600,3600,1600,400,a1,LEFT,CALU1 +S 3600,3100,3600,4800,400,*,UP,ALU1 +S 3600,3200,3600,4000,400,a2,UP,CALU1 +S 3600,4100,3600,6400,600,*,UP,PDIF +S 3600,4800,4500,4800,400,*,RIGHT,ALU1 +S 3600,6300,3600,6800,600,*,UP,ALU1 +S 3900,2300,4100,2300,200,*,RIGHT,POLY +S 3900,300,3900,700,200,*,UP,POLY +S 3900,700,3900,1900,200,t02,UP,NTRANS +S 400,1500,2700,1500,400,*,RIGHT,ALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 400,1600,1200,1600,600,*,RIGHT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,4900,1600,4900,400,*,RIGHT,ALU1 +S 400,5600,4800,5600,400,*,RIGHT,ALU1 +S 4200,2600,4200,3900,200,*,UP,POLY +S 4200,3900,4200,6600,200,t01,UP,PTRANS +S 4400,2300,4400,3300,400,*,UP,ALU1 +S 4400,2400,4400,3200,400,a1,UP,CALU1 +S 4400,400,4400,1100,400,*,UP,ALU1 +S 4400,4800,4400,4800,400,a2,LEFT,CALU1 +S 4500,900,4500,1700,600,*,UP,NDIF +S 600,500,600,1700,600,*,UP,NDIF +V 1200,2600,CONT_POLY,* +V 1500,4900,CONT_DIF_P,* +V 2200,3300,CONT_POLY,* +V 2500,5600,CONT_DIF_P,n3 +V 2600,1500,CONT_DIF_N,* +V 3200,3200,CONT_POLY,* +V 3600,6300,CONT_DIF_P,* +V 4400,1000,CONT_DIF_N,* +V 4400,2500,CONT_POLY,* +V 4700,5600,CONT_DIF_P,n3 +V 500,5600,CONT_DIF_P,n3 +V 700,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi22v0x1.vbe b/pdks/symbolic/vsclib/cells/aoi22v0x1.vbe new file mode 100755 index 000000000..541dcd0e2 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi22v0x1.vbe @@ -0,0 +1,44 @@ +ENTITY aoi22v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_b1 : NATURAL := 5; + CONSTANT cin_b2 : NATURAL := 5; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT rdown_b1_z : NATURAL := 3110; + CONSTANT rdown_b2_z : NATURAL := 3090; + CONSTANT rdown_a1_z : NATURAL := 3150; + CONSTANT rdown_a2_z : NATURAL := 3150; + CONSTANT rup_b1_z : NATURAL := 3940; + CONSTANT rup_b2_z : NATURAL := 3940; + CONSTANT rup_a1_z : NATURAL := 4000; + CONSTANT rup_a2_z : NATURAL := 4010; + CONSTANT tphl_b1_z : NATURAL := 45; + CONSTANT tphl_b2_z : NATURAL := 46; + CONSTANT tplh_a2_z : NATURAL := 77; + CONSTANT tphl_a1_z : NATURAL := 65; + CONSTANT tplh_b2_z : NATURAL := 52; + CONSTANT tplh_a1_z : NATURAL := 84; + CONSTANT tplh_b1_z : NATURAL := 59; + CONSTANT tphl_a2_z : NATURAL := 66; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi22v0x1; + +ARCHITECTURE behaviour_data_flow OF aoi22v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi22v0x1" + SEVERITY WARNING; + z <= not (((b1 and b2) or (a1 and a2))) after 150 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi22v5x05.ap b/pdks/symbolic/vsclib/cells/aoi22v5x05.ap new file mode 100755 index 000000000..df7e97502 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi22v5x05.ap @@ -0,0 +1,111 @@ +V ALLIANCE : 6 +H aoi22v5x05,P,23/ 6/2024,100 +A 0,0,5600,7200 +R 1200,2400,ref_ref,b1_24 +R 1200,4800,ref_ref,z_48 +R 2000,3200,ref_ref,b1_32 +R 2000,4000,ref_ref,a1_40 +R 2000,4800,ref_ref,z_48 +R 2800,2400,ref_ref,b2_24 +R 2800,4000,ref_ref,a1_40 +R 3600,1600,ref_ref,b2_16 +R 3600,3200,ref_ref,a1_32 +R 3600,4800,ref_ref,a2_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 4400,2400,ref_ref,a1_24 +R 4400,4000,ref_ref,a2_40 +R 4400,4800,ref_ref,a2_48 +S 2200,2000,2200,2400,200,*,UP,POLY +S 1000,4000,1000,4400,200,*,DOWN,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,4600,1000,6200,200,t01,UP,PTRANS +S 1000,6200,1000,6600,200,*,UP,POLY +S 1200,2300,1200,3200,400,*,UP,ALU1 +S 1200,2400,1200,2400,400,b1,LEFT,CALU1 +S 1200,2400,1500,2400,600,*,RIGHT,POLY +S 1200,3200,2100,3200,400,*,RIGHT,ALU1 +S 1200,3900,1200,4100,400,*,UP,ALU1 +S 1200,3900,3200,3900,400,*,RIGHT,ALU1 +S 1200,4000,3200,4000,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1300,4000,3200,4000,400,*,RIGHT,ALU1 +S 1400,5700,3600,5700,400,*,RIGHT,ALU1 +S 1500,1100,1500,1800,200,t06,UP,NTRANS +S 1500,2300,1500,3200,200,*,UP,POLY +S 1500,3200,2000,3200,200,*,RIGHT,POLY +S 1500,700,1500,1100,200,*,UP,POLY +S 1900,1300,1900,1600,400,n1,UP,NDIF +S 2000,3200,2000,3200,400,b1,LEFT,CALU1 +S 2000,3200,2000,4600,200,*,UP,POLY +S 2000,4000,2000,4000,400,a1,LEFT,CALU1 +S 2000,4600,2000,6200,200,t05,UP,PTRANS +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2000,6200,2000,6600,200,*,UP,POLY +S 2200,1100,2200,1800,200,t08,UP,NTRANS +S 2200,700,2200,1100,200,*,UP,POLY +S 2300,2400,3600,2400,400,*,RIGHT,ALU1 +S 2400,4900,2600,4900,400,*,RIGHT,ALU1 +S 2500,4800,2500,4900,600,*,UP,ALU1 +S 2600,2400,2600,3900,200,*,UP,POLY +S 2600,3900,3000,3900,200,*,RIGHT,POLY +S 2800,2400,2800,2400,400,b2,LEFT,CALU1 +S 2800,4000,2800,4000,400,a1,LEFT,CALU1 +S 3000,3900,3000,4600,200,*,UP,POLY +S 3000,4600,3000,6200,200,t07,UP,PTRANS +S 3000,6200,3000,6600,200,*,UP,POLY +S 3200,1100,3200,1800,200,t04,UP,NTRANS +S 3200,1800,3200,3200,200,*,UP,POLY +S 3200,3200,3200,4000,400,*,UP,ALU1 +S 3200,3200,4000,3200,200,*,RIGHT,POLY +S 3200,3200,4400,3200,400,*,RIGHT,ALU1 +S 3200,700,3200,1100,200,*,UP,POLY +S 3500,1300,3500,1600,400,n2,UP,NDIF +S 3500,4800,4500,4800,400,*,RIGHT,ALU1 +S 3600,1500,3600,2400,400,*,UP,ALU1 +S 3600,1600,3600,1600,400,b2,LEFT,CALU1 +S 3600,3200,3600,3200,400,a1,LEFT,CALU1 +S 3600,4800,3600,4800,400,a2,LEFT,CALU1 +S 3900,1100,3900,1800,200,t02,UP,NTRANS +S 3900,2400,4400,2400,600,*,RIGHT,POLY +S 3900,700,3900,1100,200,*,UP,POLY +S 4000,3200,4000,4100,200,*,UP,POLY +S 4000,4000,4400,4000,600,*,RIGHT,POLY +S 4000,4600,4000,6200,200,t03,UP,PTRANS +S 4000,6200,4000,6600,200,*,UP,POLY +S 400,1500,2800,1500,400,*,RIGHT,ALU1 +S 400,1500,400,4800,400,*,UP,ALU1 +S 400,1600,400,4000,400,z,UP,CALU1 +S 400,4800,2600,4800,400,*,RIGHT,ALU1 +S 4400,2300,4400,3200,400,*,UP,ALU1 +S 4400,2400,4400,2400,400,a1,LEFT,CALU1 +S 4400,4000,4400,4800,400,a2,UP,CALU1 +S 4400,4000,4400,4800,600,*,UP,ALU1 +S 4500,1300,4500,1600,600,*,UP,NDIF +S 4500,400,4500,1500,400,*,UP,ALU1 +S 4500,5800,4500,6800,400,*,UP,ALU1 +S 4600,4800,4600,6000,600,*,UP,PDIF +S 500,4800,500,6000,600,*,UP,PDIF +S 500,5800,500,6800,400,*,UP,ALU1 +S 800,500,800,1600,600,*,UP,NDIF +S 900,500,900,1600,600,*,UP,NDIF +V 1200,2400,CONT_POLY,* +V 1200,4000,CONT_POLY,* +V 1500,5700,CONT_DIF_P,n3 +V 2400,2400,CONT_POLY,* +V 2500,4900,CONT_DIF_P,* +V 2700,1500,CONT_DIF_N,* +V 3500,5700,CONT_DIF_P,n3 +V 4400,2400,CONT_POLY,* +V 4400,4000,CONT_POLY,* +V 4500,1400,CONT_DIF_N,* +V 4500,5900,CONT_DIF_P,* +V 500,5900,CONT_DIF_P,* +V 900,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi22v5x05.vbe b/pdks/symbolic/vsclib/cells/aoi22v5x05.vbe new file mode 100755 index 000000000..02d7dfab7 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi22v5x05.vbe @@ -0,0 +1,44 @@ +ENTITY aoi22v5x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_b1 : NATURAL := 4; + CONSTANT cin_b2 : NATURAL := 3; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT rdown_b1_z : NATURAL := 5310; + CONSTANT rdown_b2_z : NATURAL := 5290; + CONSTANT rdown_a1_z : NATURAL := 5380; + CONSTANT rdown_a2_z : NATURAL := 5360; + CONSTANT rup_b1_z : NATURAL := 6640; + CONSTANT rup_b2_z : NATURAL := 6650; + CONSTANT rup_a1_z : NATURAL := 6750; + CONSTANT rup_a2_z : NATURAL := 6760; + CONSTANT tphl_b1_z : NATURAL := 49; + CONSTANT tphl_b2_z : NATURAL := 50; + CONSTANT tplh_a2_z : NATURAL := 78; + CONSTANT tphl_a1_z : NATURAL := 69; + CONSTANT tplh_b2_z : NATURAL := 56; + CONSTANT tplh_a1_z : NATURAL := 87; + CONSTANT tplh_b1_z : NATURAL := 63; + CONSTANT tphl_a2_z : NATURAL := 68; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi22v5x05; + +ARCHITECTURE behaviour_data_flow OF aoi22v5x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi22v5x05" + SEVERITY WARNING; + z <= not (((b1 and b2) or (a1 and a2))) after 215 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi31v0x05.ap b/pdks/symbolic/vsclib/cells/aoi31v0x05.ap new file mode 100755 index 000000000..5a67e44cb --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi31v0x05.ap @@ -0,0 +1,115 @@ +V ALLIANCE : 6 +H aoi31v0x05,P, 5/ 7/2024,100 +A 0,0,5600,7200 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,b_32 +R 2000,2400,ref_ref,b_24 +R 2000,4000,ref_ref,a3_40 +R 2800,1600,ref_ref,a1_16 +R 2800,2400,ref_ref,b_24 +R 2800,3200,ref_ref,a3_32 +R 2800,4800,ref_ref,a3_48 +R 3600,1600,ref_ref,a1_16 +R 3600,4000,ref_ref,a2_40 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +R 4400,2400,ref_ref,a1_24 +R 4400,3200,ref_ref,a1_32 +R 4400,4000,ref_ref,a2_40 +R 4400,4800,ref_ref,a2_48 +S 4600,600,5100,600,600,*,RIGHT,PTIE +S 2000,3500,2000,4100,200,*,UP,POLY +S 1000,3200,1000,4100,200,*,UP,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,4100,1000,5700,200,t07,UP,PTRANS +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2400,1200,3300,400,*,UP,ALU1 +S 1200,2400,2900,2400,400,*,RIGHT,ALU1 +S 1200,3200,1200,3200,400,b,LEFT,CALU1 +S 1400,1000,1400,1400,200,*,UP,POLY +S 1400,1400,1400,2000,200,t08,UP,NTRANS +S 1400,2000,1400,3200,200,*,UP,POLY +S 1500,5300,1500,5700,400,*,UP,ALU1 +S 1500,5700,3700,5700,400,*,RIGHT,ALU1 +S 2000,2400,2000,2400,400,b,LEFT,CALU1 +S 2000,4000,2000,4000,400,a3,LEFT,CALU1 +S 2000,4000,2300,4000,600,*,RIGHT,ALU1 +S 2000,4100,2000,5700,200,t05,UP,PTRANS +S 2300,3200,2300,4800,400,*,UP,ALU1 +S 2300,3200,2900,3200,400,*,RIGHT,ALU1 +S 2300,4800,2900,4800,400,*,RIGHT,ALU1 +S 2400,1000,2400,1400,200,*,UP,POLY +S 2400,1400,2400,2400,200,t06,UP,NTRANS +S 2400,2400,2400,3300,200,*,UP,POLY +S 2600,4800,2600,6700,600,*,UP,PDIF +S 2700,1600,3700,1600,400,*,RIGHT,ALU1 +S 2800,1600,2800,1600,400,a1,LEFT,CALU1 +S 2800,1600,2800,2200,400,n2,UP,NDIF +S 2800,2400,2800,2400,400,b,LEFT,CALU1 +S 2800,3200,2800,3200,400,a3,LEFT,CALU1 +S 2800,4800,2800,4800,400,a3,LEFT,CALU1 +S 3100,1000,3100,1400,200,*,UP,POLY +S 3100,1400,3100,2400,200,t04,UP,NTRANS +S 3100,2400,3100,4200,200,*,UP,POLY +S 3200,4600,3200,6200,200,t03,UP,PTRANS +S 3200,6200,3200,6600,200,*,UP,POLY +S 3300,4000,4500,4000,400,*,RIGHT,ALU1 +S 3500,1600,3500,2200,400,n1,UP,NDIF +S 3600,1600,3600,1600,400,a1,LEFT,CALU1 +S 3600,4000,3600,4000,400,a2,LEFT,CALU1 +S 3700,1600,3700,2400,400,*,UP,ALU1 +S 3700,2400,4500,2400,400,*,RIGHT,ALU1 +S 3700,4800,3700,5700,400,*,UP,ALU1 +S 3800,1000,3800,1400,200,*,UP,POLY +S 3800,1400,3800,2400,200,t02,UP,NTRANS +S 3800,2800,4300,2800,200,*,RIGHT,POLY +S 400,1500,1300,1500,400,*,RIGHT,ALU1 +S 400,1500,400,5700,400,*,UP,ALU1 +S 400,1600,1200,1600,600,*,RIGHT,ALU1 +S 400,1600,1300,1600,400,*,RIGHT,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 400,1600,400,5700,400,*,UP,ALU1 +S 400,1700,2000,1700,400,*,RIGHT,ALU1 +S 4200,3000,4200,4600,200,*,UP,POLY +S 4200,4600,4200,6200,200,t01,UP,PTRANS +S 4200,6200,4200,6600,200,*,UP,POLY +S 4400,2400,4400,3200,400,a1,UP,CALU1 +S 4400,2400,4400,3200,600,*,UP,ALU1 +S 4400,4000,4400,4800,400,a2,UP,CALU1 +S 4400,4000,4400,4900,400,*,UP,ALU1 +S 4500,4000,4500,4900,400,*,UP,ALU1 +S 4600,1600,4600,2200,800,*,UP,NDIF +S 4600,400,4600,1700,600,*,UP,ALU1 +S 4700,4800,4700,6000,600,*,UP,PDIF +S 4700,5800,4700,6800,400,*,UP,ALU1 +S 500,4300,500,5200,400,*,UP,ALU1 +S 500,4400,500,5200,600,*,UP,PDIF +S 500,4800,500,5700,400,*,UP,ALU1 +S 600,500,600,1800,600,*,UP,NDIF +S 600,6600,1600,6600,600,*,RIGHT,NTIE +S 700,500,700,1800,600,*,UP,NDIF +V 1200,3200,CONT_POLY,* +V 1500,5400,CONT_DIF_P,n3 +V 1900,1700,CONT_DIF_N,* +V 2300,3500,CONT_POLY,* +V 2600,6600,CONT_DIF_P,* +V 3400,4000,CONT_POLY,* +V 3700,4900,CONT_DIF_P,n3 +V 3700,5600,CONT_DIF_P,n3 +V 4400,3000,CONT_POLY,* +V 4600,1700,CONT_DIF_N,* +V 4700,5900,CONT_DIF_P,* +V 4900,600,CONT_BODY_P,* +V 500,4400,CONT_DIF_P,* +V 500,5100,CONT_DIF_P,* +V 600,6600,CONT_BODY_N,* +V 700,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi31v0x05.vbe b/pdks/symbolic/vsclib/cells/aoi31v0x05.vbe new file mode 100755 index 000000000..55257460f --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi31v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY aoi31v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_a2 : NATURAL := 4; + CONSTANT cin_a3 : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 3890; + CONSTANT rdown_a1_z : NATURAL := 5240; + CONSTANT rdown_a2_z : NATURAL := 5230; + CONSTANT rdown_a3_z : NATURAL := 5230; + CONSTANT rup_b_z : NATURAL := 6120; + CONSTANT rup_a1_z : NATURAL := 7320; + CONSTANT rup_a2_z : NATURAL := 7320; + CONSTANT rup_a3_z : NATURAL := 7350; + CONSTANT tphl_b_z : NATURAL := 41; + CONSTANT tphl_a1_z : NATURAL := 62; + CONSTANT tplh_a3_z : NATURAL := 75; + CONSTANT tphl_a2_z : NATURAL := 60; + CONSTANT tplh_a1_z : NATURAL := 94; + CONSTANT tplh_a2_z : NATURAL := 85; + CONSTANT tplh_b_z : NATURAL := 53; + CONSTANT tphl_a3_z : NATURAL := 58; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b : in BIT; + a1 : in BIT; + a2 : in BIT; + a3 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi31v0x05; + +ARCHITECTURE behaviour_data_flow OF aoi31v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi31v0x05" + SEVERITY WARNING; + z <= not(b or ((a1 and a2) and a3)) after 215 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi31v0x1.ap b/pdks/symbolic/vsclib/cells/aoi31v0x1.ap new file mode 100755 index 000000000..8eb640f83 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi31v0x1.ap @@ -0,0 +1,104 @@ +V ALLIANCE : 6 +H aoi31v0x1,P, 5/ 7/2024,100 +A 0,0,5600,7200 +R 1200,1600,ref_ref,z_16 +R 1200,4000,ref_ref,a3_40 +R 2000,2400,ref_ref,b_24 +R 2000,3200,ref_ref,a3_32 +R 2000,4000,ref_ref,a3_40 +R 2800,1600,ref_ref,b_16 +R 3600,2400,ref_ref,a1_24 +R 3600,4000,ref_ref,a2_40 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +R 4400,2400,ref_ref,a1_24 +R 4400,3200,ref_ref,a1_32 +R 4400,4000,ref_ref,a2_40 +R 4400,4800,ref_ref,a2_48 +S 1500,700,1500,1300,800,*,UP,TALU7 +S 4100,3000,4100,3400,200,*,DOWN,POLY +S 4000,2800,4000,3600,200,*,UP,POLY +S 1400,1900,1400,2700,200,*,UP,POLY +S 1000,2500,1000,3500,200,*,DOWN,POLY +S 2000,3200,2000,4100,200,*,DOWN,POLY +S 3000,3200,3000,3800,200,*,DOWN,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,2800,1000,3900,200,*,UP,POLY +S 1000,3900,1000,6600,200,t05,UP,PTRANS +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2400,1200,2700,400,*,UP,ALU1 +S 1200,2400,2800,2400,400,*,RIGHT,ALU1 +S 1200,4000,1200,4000,400,a3,LEFT,CALU1 +S 1200,4000,2200,4000,600,*,RIGHT,ALU1 +S 1400,1300,1400,2000,200,t06,UP,NTRANS +S 1400,900,1400,1300,200,*,UP,POLY +S 1500,4800,1500,5700,400,*,UP,ALU1 +S 1500,4800,3500,4800,400,*,RIGHT,ALU1 +S 2000,2400,2000,2400,400,b,LEFT,CALU1 +S 2000,3200,2000,4000,400,a3,UP,CALU1 +S 2000,3200,2000,4100,600,*,UP,ALU1 +S 2000,3900,2000,6600,200,t07,UP,PTRANS +S 2100,3200,2100,4100,600,*,UP,ALU1 +S 2400,1000,2400,2600,200,t08,UP,NTRANS +S 2400,2600,2400,3300,200,*,UP,POLY +S 2400,600,2400,1000,200,*,UP,POLY +S 2500,5600,2500,6800,600,*,UP,ALU1 +S 2800,1200,2800,2400,400,n2,UP,NDIF +S 2800,1500,2800,2400,400,*,UP,ALU1 +S 2800,1600,2800,1600,400,b,LEFT,CALU1 +S 3000,3900,3000,6600,200,t03,UP,PTRANS +S 3100,4000,4500,4000,400,*,RIGHT,ALU1 +S 3200,1000,3200,2600,200,t04,UP,NTRANS +S 3200,2600,3200,3300,200,*,UP,POLY +S 3200,3300,3200,4000,600,*,UP,ALU1 +S 3200,600,3200,1000,200,*,UP,POLY +S 3500,4800,3500,5700,400,*,UP,ALU1 +S 3600,1200,3600,2400,400,n1,UP,NDIF +S 3600,2400,3600,2400,400,a1,LEFT,CALU1 +S 3600,2400,4500,2400,600,*,RIGHT,ALU1 +S 3600,4000,3600,4000,400,a2,LEFT,CALU1 +S 4000,1000,4000,2600,200,t02,UP,NTRANS +S 4000,3900,4000,6600,200,t01,UP,PTRANS +S 4000,600,4000,1000,200,*,UP,POLY +S 400,1500,2000,1500,400,*,RIGHT,ALU1 +S 400,1500,400,5700,400,*,UP,ALU1 +S 400,1600,2000,1600,400,*,RIGHT,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 4400,2300,4400,3200,600,*,UP,ALU1 +S 4400,2400,4400,3200,400,a1,UP,CALU1 +S 4400,4000,4400,4800,400,a2,UP,CALU1 +S 4400,4000,4400,4800,600,*,UP,ALU1 +S 4500,1200,4500,2400,600,*,UP,NDIF +S 4500,400,4500,1400,400,*,UP,ALU1 +S 4500,4100,4500,6400,600,*,UP,PDIF +S 4500,5600,4500,6800,600,*,UP,ALU1 +S 500,4900,500,5700,600,*,UP,ALU1 +S 500,4900,500,5700,600,*,UP,PDIF +S 700,500,700,1800,600,*,UP,NDIF +S 800,500,800,1800,600,*,UP,NDIF +V 1200,2600,CONT_POLY,* +V 1500,4900,CONT_DIF_P,n3 +V 1500,5600,CONT_DIF_P,n3 +V 1900,1600,CONT_DIF_N,* +V 2200,3300,CONT_POLY,* +V 2500,5600,CONT_DIF_P,* +V 2500,6300,CONT_DIF_P,* +V 3200,3300,CONT_POLY,* +V 3500,4900,CONT_DIF_P,n3 +V 3500,5600,CONT_DIF_P,n3 +V 4400,3200,CONT_POLY,* +V 4500,1300,CONT_DIF_N,* +V 4500,5600,CONT_DIF_P,* +V 4500,6300,CONT_DIF_P,* +V 500,4900,CONT_DIF_P,* +V 500,5700,CONT_DIF_P,* +V 800,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi31v0x1.vbe b/pdks/symbolic/vsclib/cells/aoi31v0x1.vbe new file mode 100755 index 000000000..6c91d67fe --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi31v0x1.vbe @@ -0,0 +1,44 @@ +ENTITY aoi31v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT cin_a3 : NATURAL := 5; + CONSTANT rdown_b_z : NATURAL := 3310; + CONSTANT rdown_a1_z : NATURAL := 3270; + CONSTANT rdown_a2_z : NATURAL := 3270; + CONSTANT rdown_a3_z : NATURAL := 3270; + CONSTANT rup_b_z : NATURAL := 3630; + CONSTANT rup_a1_z : NATURAL := 4340; + CONSTANT rup_a2_z : NATURAL := 4340; + CONSTANT rup_a3_z : NATURAL := 4360; + CONSTANT tphl_b_z : NATURAL := 47; + CONSTANT tphl_a1_z : NATURAL := 60; + CONSTANT tplh_a3_z : NATURAL := 70; + CONSTANT tphl_a2_z : NATURAL := 60; + CONSTANT tplh_a1_z : NATURAL := 88; + CONSTANT tplh_a2_z : NATURAL := 80; + CONSTANT tplh_b_z : NATURAL := 49; + CONSTANT tphl_a3_z : NATURAL := 57; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b : in BIT; + a1 : in BIT; + a2 : in BIT; + a3 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi31v0x1; + +ARCHITECTURE behaviour_data_flow OF aoi31v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi31v0x1" + SEVERITY WARNING; + z <= not(b or ((a1 and a2) and a3)) after 157 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aoi31v0x2.ap b/pdks/symbolic/vsclib/cells/aoi31v0x2.ap new file mode 100755 index 000000000..1fe1b6988 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi31v0x2.ap @@ -0,0 +1,155 @@ +V ALLIANCE : 6 +H aoi31v0x2,P,22/ 6/2024,100 +A 0,0,9600,7200 +R 1200,3200,ref_ref,b_32 +R 2000,2400,ref_ref,z_24 +R 2000,3200,ref_ref,z_32 +R 2000,4000,ref_ref,z_40 +R 2800,1600,ref_ref,z_16 +R 2800,3200,ref_ref,a1_32 +R 3600,1600,ref_ref,z_16 +R 3600,2400,ref_ref,a1_24 +R 400,3200,ref_ref,b_32 +R 400,4000,ref_ref,b_40 +R 400,4800,ref_ref,b_48 +R 4400,1600,ref_ref,z_16 +R 4400,2400,ref_ref,a1_24 +R 4400,4000,ref_ref,a2_40 +R 5200,1600,ref_ref,z_16 +R 5200,2400,ref_ref,a1_24 +R 5200,3200,ref_ref,a3_32 +R 5200,4000,ref_ref,a2_40 +R 6000,2400,ref_ref,a1_24 +R 6000,3200,ref_ref,a3_32 +R 6000,4000,ref_ref,a2_40 +R 6800,1600,ref_ref,a1_16 +R 6800,2400,ref_ref,a1_24 +R 6800,4000,ref_ref,a2_40 +R 7600,2400,ref_ref,a1_24 +R 7600,3200,ref_ref,a2_32 +R 8400,2400,ref_ref,a1_24 +S 3000,3100,3000,3600,200,*,DOWN,POLY +S 4000,3100,4000,3700,200,*,DOWN,POLY +S 0,400,9600,400,800,*,RIGHT,ALU1 +S 0,400,9600,400,800,vss,RIGHT,CALU1 +S 0,5400,9600,5400,4400,*,RIGHT,NWELL +S 0,6800,9600,6800,800,*,RIGHT,ALU1 +S 0,6800,9600,6800,800,vdd,RIGHT,CALU1 +S 1000,1400,1000,1800,200,*,UP,POLY +S 1000,1800,1000,2600,200,t3b,UP,NTRANS +S 1000,3200,2000,3200,600,*,RIGHT,POLY +S 1000,3800,1000,6600,200,t1b,UP,PTRANS +S 1200,3200,1200,3200,400,b,LEFT,CALU1 +S 1400,2300,2000,2300,400,*,RIGHT,ALU1 +S 1400,4100,2000,4100,400,*,RIGHT,ALU1 +S 1500,4100,1500,4800,600,*,UP,ALU1 +S 2000,1400,2000,1800,200,*,UP,POLY +S 2000,1600,2000,4100,400,*,UP,ALU1 +S 2000,1600,5700,1600,400,*,RIGHT,ALU1 +S 2000,1800,2000,2600,200,t4b,UP,NTRANS +S 2000,2400,2000,4000,400,z,UP,CALU1 +S 2000,3800,2000,6600,200,t2b,UP,PTRANS +S 2500,4800,2500,5700,400,*,UP,ALU1 +S 2500,4800,8600,4800,400,*,RIGHT,ALU1 +S 2700,500,2700,2400,800,*,UP,NDIF +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2800,2400,2800,3300,400,*,UP,ALU1 +S 2800,2400,8500,2400,400,*,RIGHT,ALU1 +S 2800,3000,3400,3000,200,*,RIGHT,POLY +S 2800,3200,2800,3200,400,a1,LEFT,CALU1 +S 3000,3800,3000,6600,200,t1a1,UP,PTRANS +S 3400,400,3400,800,200,*,UP,POLY +S 3400,800,3400,2600,200,t3a1,UP,NTRANS +S 3500,6200,3500,6800,400,*,UP,ALU1 +S 3600,1600,3600,1600,400,z,LEFT,CALU1 +S 3600,2400,3600,2400,400,a1,LEFT,CALU1 +S 3700,1000,3700,2400,400,n1a,UP,NDIF +S 4000,3800,4000,6600,200,t1a2,UP,PTRANS +S 400,3100,400,4900,400,*,UP,ALU1 +S 400,3200,1200,3200,600,*,RIGHT,ALU1 +S 400,3200,400,4800,400,b,UP,CALU1 +S 400,5700,2500,5700,400,*,RIGHT,ALU1 +S 4100,4000,7100,4000,400,*,RIGHT,ALU1 +S 4200,3200,4200,4000,600,*,UP,ALU1 +S 4200,400,4200,800,200,*,UP,POLY +S 4200,800,4200,2600,200,t3a2,UP,NTRANS +S 4400,1600,4400,1600,400,z,LEFT,CALU1 +S 4400,2400,4400,2400,400,a1,LEFT,CALU1 +S 4400,4000,4400,4000,400,a2,LEFT,CALU1 +S 4500,4800,4500,5700,400,*,UP,ALU1 +S 4600,1000,4600,2400,400,n2a,UP,NDIF +S 5000,3200,6200,3200,600,*,RIGHT,POLY +S 5000,3800,5000,6600,200,t1a3,UP,PTRANS +S 5000,400,5000,700,200,*,UP,POLY +S 5000,800,5000,2600,200,t3a3,UP,NTRANS +S 500,2000,500,2400,600,*,UP,NDIF +S 500,400,500,2200,400,*,UP,ALU1 +S 5100,3200,6100,3200,400,*,RIGHT,ALU1 +S 5200,1600,5200,1600,400,z,LEFT,CALU1 +S 5200,2400,5200,2400,400,a1,LEFT,CALU1 +S 5200,3200,5200,3200,400,a3,LEFT,CALU1 +S 5200,4000,5200,4000,400,a2,LEFT,CALU1 +S 5500,5600,5500,6800,600,*,UP,ALU1 +S 5600,1000,5600,2400,600,*,UP,NDIF +S 6000,2400,6000,2400,400,a1,LEFT,CALU1 +S 6000,3200,6000,3200,400,a3,LEFT,CALU1 +S 6000,3800,6000,6600,200,t2a3,UP,PTRANS +S 6000,4000,6000,4000,400,a2,LEFT,CALU1 +S 600,600,1400,600,600,*,RIGHT,PTIE +S 6200,400,6200,700,200,*,UP,POLY +S 6200,800,6200,2600,200,t4a3,UP,NTRANS +S 6500,1000,6500,2400,400,n2b,UP,NDIF +S 6500,4800,6500,5600,400,*,UP,ALU1 +S 6800,1500,6800,2400,400,*,UP,ALU1 +S 6800,1600,6800,2400,400,a1,UP,CALU1 +S 6800,4000,6800,4000,400,a2,LEFT,CALU1 +S 6900,3200,7700,3200,400,*,RIGHT,ALU1 +S 7000,3200,7000,4000,600,*,UP,ALU1 +S 7000,3800,7000,6600,200,t2a2,UP,PTRANS +S 7000,400,7000,700,200,*,UP,POLY +S 7000,800,7000,2600,200,t4a2,UP,NTRANS +S 7400,1000,7400,2400,400,n1b,UP,NDIF +S 7500,5600,7500,6800,600,*,UP,ALU1 +S 7600,2400,7600,2400,400,a1,LEFT,CALU1 +S 7600,3200,7600,3200,400,a2,LEFT,CALU1 +S 7800,3200,8700,3200,600,*,RIGHT,POLY +S 7800,400,7800,800,200,*,UP,POLY +S 7800,800,7800,2600,200,t4a1,UP,NTRANS +S 8000,3800,8000,6600,200,t2a1,UP,PTRANS +S 8300,400,8300,1200,400,*,UP,ALU1 +S 8400,1000,8400,2400,600,*,UP,NDIF +S 8400,2400,8400,2400,400,a1,LEFT,CALU1 +S 8500,2400,8500,3300,400,*,UP,ALU1 +S 8500,4100,8500,4800,600,*,UP,PDIF +S 8500,4100,8500,4800,600,*,UP,ALU1 +V 1200,3200,CONT_POLY,* +V 1400,600,CONT_BODY_P,* +V 1500,2300,CONT_DIF_N,* +V 1500,4100,CONT_DIF_P,* +V 1500,4800,CONT_DIF_P,* +V 2500,4900,CONT_DIF_P,n3 +V 2500,5600,CONT_DIF_P,n3 +V 2700,600,CONT_DIF_N,* +V 2800,3200,CONT_POLY,* +V 3500,6300,CONT_DIF_P,* +V 4200,3200,CONT_POLY,* +V 4500,4900,CONT_DIF_P,n3 +V 4500,5600,CONT_DIF_P,n3 +V 500,2100,CONT_DIF_N,* +V 500,5700,CONT_DIF_P,n3 +V 5200,3200,CONT_POLY,* +V 5500,5600,CONT_DIF_P,* +V 5500,6300,CONT_DIF_P,* +V 5600,1600,CONT_DIF_N,* +V 6000,3200,CONT_POLY,* +V 600,600,CONT_BODY_P,* +V 6500,4800,CONT_DIF_P,n3 +V 6500,5500,CONT_DIF_P,n3 +V 7000,3200,CONT_POLY,* +V 7500,5600,CONT_DIF_P,* +V 7500,6300,CONT_DIF_P,* +V 8300,1100,CONT_DIF_N,* +V 8500,3200,CONT_POLY,* +V 8500,4100,CONT_DIF_P,n3 +V 8500,4800,CONT_DIF_P,n3 +EOF diff --git a/pdks/symbolic/vsclib/cells/aoi31v0x2.vbe b/pdks/symbolic/vsclib/cells/aoi31v0x2.vbe new file mode 100755 index 000000000..f7661f2ef --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aoi31v0x2.vbe @@ -0,0 +1,44 @@ +ENTITY aoi31v0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 6912; + CONSTANT cin_b : NATURAL := 8; + CONSTANT cin_a1 : NATURAL := 12; + CONSTANT cin_a2 : NATURAL := 11; + CONSTANT cin_a3 : NATURAL := 10; + CONSTANT rdown_b_z : NATURAL := 1450; + CONSTANT rdown_a1_z : NATURAL := 1470; + CONSTANT rdown_a2_z : NATURAL := 1460; + CONSTANT rdown_a3_z : NATURAL := 1460; + CONSTANT rup_b_z : NATURAL := 1750; + CONSTANT rup_a1_z : NATURAL := 2100; + CONSTANT rup_a2_z : NATURAL := 2090; + CONSTANT rup_a3_z : NATURAL := 2110; + CONSTANT tphl_b_z : NATURAL := 42; + CONSTANT tphl_a1_z : NATURAL := 57; + CONSTANT tplh_a3_z : NATURAL := 69; + CONSTANT tphl_a2_z : NATURAL := 55; + CONSTANT tplh_a1_z : NATURAL := 90; + CONSTANT tplh_a2_z : NATURAL := 80; + CONSTANT tplh_b_z : NATURAL := 47; + CONSTANT tphl_a3_z : NATURAL := 52; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + b : in BIT; + a1 : in BIT; + a2 : in BIT; + a3 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aoi31v0x2; + +ARCHITECTURE behaviour_data_flow OF aoi31v0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aoi31v0x2" + SEVERITY WARNING; + z <= not(b or ((a1 and a2) and a3)) after 105 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aon21bv0x05.ap b/pdks/symbolic/vsclib/cells/aon21bv0x05.ap new file mode 100755 index 000000000..707713b2a --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aon21bv0x05.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H aon21bv0x05,P,23/ 6/2024,100 +A 0,0,5600,7200 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,b_32 +R 2000,1600,ref_ref,b_16 +R 2000,2400,ref_ref,b_24 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 3600,2400,ref_ref,a1_24 +R 2800,2400,ref_ref,a1_24 +R 2800,3200,ref_ref,a1_32 +R 5200,3200,ref_ref,a2_32 +R 4400,4000,ref_ref,a2_40 +R 5200,4000,ref_ref,a2_40 +R 1200,4800,ref_ref,z_48 +R 5200,2400,ref_ref,a2_24 +S 2000,2000,2000,4300,200,*,UP,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2500,1200,3300,400,*,UP,ALU1 +S 1200,2500,2000,2500,400,*,RIGHT,ALU1 +S 1200,3200,1200,3200,400,b,LEFT,CALU1 +S 2000,1500,2000,2500,400,*,UP,ALU1 +S 2000,1600,2000,2400,400,b,UP,CALU1 +S 400,1500,400,4100,400,*,UP,ALU1 +S 400,1600,1200,1600,600,*,RIGHT,ALU1 +S 400,1600,400,4000,400,z,UP,CALU1 +S 600,6600,1400,6600,600,*,RIGHT,NTIE +S 2800,2400,3600,2400,600,*,LEFT,ALU1 +S 4700,4800,4700,5300,600,*,UP,PDIF +S 4300,4000,5200,4000,400,*,RIGHT,ALU1 +S 400,4100,1200,4100,400,*,RIGHT,ALU1 +S 1200,4900,1500,4900,600,*,LEFT,ALU1 +S 1000,4600,1000,5400,200,t05,UP,PTRANS +S 2000,4600,2000,5400,200,t07,UP,PTRANS +S 500,4800,500,5200,600,*,UP,PDIF +S 2100,4000,3600,4000,400,*,RIGHT,ALU1 +S 2800,2300,2800,3300,400,*,UP,ALU1 +S 1000,5400,1000,5800,200,*,UP,POLY +S 2000,5400,2000,5800,200,*,UP,POLY +S 1200,4100,1200,5000,400,*,UP,ALU1 +S 500,5000,500,6800,400,*,UP,ALU1 +S 4700,5000,4700,6800,400,*,UP,ALU1 +S 3600,1500,3600,1800,400,n1,UP,NDIF +S 2600,1500,2600,1800,600,*,UP,NDIF +S 2800,400,2800,1600,600,*,DOWN,ALU1 +S 4500,1500,4500,1800,600,*,UP,NDIF +S 4000,1300,4000,2000,200,t02,UP,NTRANS +S 4000,900,4000,1300,200,*,UP,POLY +S 3300,1300,3300,2000,200,t04,UP,NTRANS +S 3300,900,3300,1300,200,*,UP,POLY +S 800,1500,800,1800,600,*,UP,NDIF +S 1700,1500,1700,1800,400,n2,UP,NDIF +S 2000,1300,2000,2000,200,t08,UP,NTRANS +S 1300,1300,1300,2000,200,t06,UP,NTRANS +S 1300,900,1300,1300,200,*,UP,POLY +S 2000,900,2000,1300,200,*,UP,POLY +S 2800,2600,3300,2600,600,*,RIGHT,POLY +S 4000,2000,4000,3900,200,*,UP,POLY +S 4000,4000,4400,4000,600,*,LEFT,POLY +S 1000,2600,1000,4600,200,*,UP,POLY +S 4500,1600,4500,3200,400,*,DOWN,ALU1 +S 3600,3200,4500,3200,400,*,RIGHT,ALU1 +S 2600,4800,2600,5300,600,*,UP,PDIF +S 4100,4600,4100,5500,200,t01,UP,PTRANS +S 3100,4600,3100,5500,200,t03,UP,PTRANS +S 3100,2600,3100,4600,200,*,UP,POLY +S 3100,5500,3100,5900,200,*,UP,POLY +S 4100,5500,4100,5900,200,*,UP,POLY +S 3600,3200,3600,5000,400,*,UP,ALU1 +S 2600,5000,2600,6800,400,*,UP,ALU1 +S 4400,4000,4400,4000,400,a2,LEFT,CALU1 +S 3600,2400,3600,2400,400,a1,LEFT,CALU1 +S 2800,2400,2800,3200,400,a1,UP,CALU1 +S 4300,4100,5200,4100,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 5200,2300,5200,4100,400,*,DOWN,ALU1 +S 5200,2400,5200,4000,400,a2,UP,CALU1 +V 1400,6600,CONT_BODY_N,* +V 600,6600,CONT_BODY_N,* +V 4400,4000,CONT_POLY,* +V 4700,5100,CONT_DIF_P,* +V 1500,4900,CONT_DIF_P,* +V 500,5100,CONT_DIF_P,* +V 2200,4000,CONT_POLY,an +V 2800,2600,CONT_POLY,* +V 2800,1600,CONT_DIF_N,* +V 4500,1700,CONT_DIF_N,an +V 800,1700,CONT_DIF_N,* +V 1200,2600,CONT_POLY,* +V 5000,600,CONT_BODY_P,* +V 2600,5100,CONT_DIF_P,* +V 3600,4900,CONT_DIF_P,an +EOF diff --git a/pdks/symbolic/vsclib/cells/aon21bv0x05.vbe b/pdks/symbolic/vsclib/cells/aon21bv0x05.vbe new file mode 100755 index 000000000..256424023 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aon21bv0x05.vbe @@ -0,0 +1,38 @@ +ENTITY aon21bv0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a2_z : NATURAL := 5280; + CONSTANT rdown_a1_z : NATURAL := 5290; + CONSTANT rdown_b_z : NATURAL := 5290; + CONSTANT rup_a2_z : NATURAL := 7430; + CONSTANT rup_a1_z : NATURAL := 7430; + CONSTANT rup_b_z : NATURAL := 7430; + CONSTANT tphh_a2_z : NATURAL := 91; + CONSTANT tphl_b_z : NATURAL := 38; + CONSTANT tplh_b_z : NATURAL := 50; + CONSTANT tphh_a1_z : NATURAL := 91; + CONSTANT tpll_a1_z : NATURAL := 100; + CONSTANT tpll_a2_z : NATURAL := 92; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a2 : in BIT; + a1 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aon21bv0x05; + +ARCHITECTURE behaviour_data_flow OF aon21bv0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aon21bv0x05" + SEVERITY WARNING; + z <= not b or (a1 and a2) after 236 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aon21bv0x1.ap b/pdks/symbolic/vsclib/cells/aon21bv0x1.ap new file mode 100755 index 000000000..da814bc9d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aon21bv0x1.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H aon21bv0x1,P,22/ 6/2024,100 +A 0,0,5600,7200 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,b_32 +R 2000,1600,ref_ref,b_16 +R 2000,2400,ref_ref,b_24 +R 3600,2400,ref_ref,a1_24 +R 3600,4000,ref_ref,a2_40 +R 3600,4800,ref_ref,a2_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 4400,3200,ref_ref,a1_32 +R 4400,4000,ref_ref,a2_40 +S 3500,3600,3500,4200,200,*,UP,POLY +S 3200,4000,3200,4600,200,*,DOWN,POLY +S 2300,2800,2300,3400,200,*,UP,POLY +S 2000,3500,2600,3500,200,*,RIGHT,POLY +S 1000,3000,1000,3800,200,*,DOWN,POLY +S 1000,2900,1600,2900,200,*,RIGHT,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,3200,1000,3900,200,*,UP,POLY +S 1000,3900,1000,5300,200,t05,UP,PTRANS +S 1000,5300,1000,5700,200,*,UP,POLY +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2500,1200,3300,400,*,UP,ALU1 +S 1200,2500,2000,2500,400,*,RIGHT,ALU1 +S 1200,3200,1200,3200,400,b,LEFT,CALU1 +S 1400,2900,1600,2900,200,*,RIGHT,POLY +S 1500,4100,1500,5000,400,*,UP,ALU1 +S 1600,1300,1600,2500,200,t06,UP,NTRANS +S 1600,900,1600,1300,200,*,UP,POLY +S 2000,1500,2000,2300,400,n2,UP,NDIF +S 2000,1500,2000,2500,400,*,UP,ALU1 +S 2000,1600,2000,2400,400,b,UP,CALU1 +S 2000,3500,2200,3500,200,*,RIGHT,POLY +S 2000,3900,2000,5300,200,t07,UP,PTRANS +S 2000,5300,2000,5700,200,*,UP,POLY +S 2100,3300,2800,3300,400,*,RIGHT,ALU1 +S 2300,1300,2300,2500,200,t08,UP,NTRANS +S 2300,2600,2300,3200,200,*,UP,POLY +S 2300,900,2300,1300,200,*,UP,POLY +S 2500,3300,2500,5600,400,*,UP,ALU1 +S 2500,5600,3800,5600,400,*,RIGHT,ALU1 +S 2600,4100,2600,6700,600,*,UP,PDIF +S 2800,1600,2800,3300,400,*,UP,ALU1 +S 2800,1600,4800,1600,400,*,RIGHT,ALU1 +S 2900,500,2900,2400,600,*,UP,NDIF +S 3200,4700,3200,6200,200,t03,UP,PTRANS +S 3200,6200,3200,6600,200,*,UP,POLY +S 3400,4000,4500,4000,400,*,RIGHT,ALU1 +S 3400,4100,3700,4100,600,*,RIGHT,ALU1 +S 3500,1300,3500,2600,200,t04,UP,NTRANS +S 3500,2600,3500,4000,200,*,UP,POLY +S 3500,900,3500,1300,200,*,UP,POLY +S 3600,2300,3600,3200,400,*,UP,ALU1 +S 3600,2400,3600,2400,400,a1,LEFT,CALU1 +S 3600,3200,4500,3200,400,*,RIGHT,ALU1 +S 3600,4000,3600,4800,400,a2,UP,CALU1 +S 3600,4000,3600,4800,600,*,UP,ALU1 +S 3900,1500,3900,2400,400,n1,UP,NDIF +S 400,1500,400,4100,400,*,UP,ALU1 +S 400,1600,1200,1600,600,*,RIGHT,ALU1 +S 400,1600,400,4000,400,z,UP,CALU1 +S 400,4100,1500,4100,400,*,RIGHT,ALU1 +S 4200,1300,4200,2600,200,t02,UP,NTRANS +S 4200,2600,4200,4700,200,*,UP,POLY +S 4200,4700,4200,6200,200,t01,UP,PTRANS +S 4200,6200,4200,6600,200,*,UP,POLY +S 4200,900,4200,1300,200,*,UP,POLY +S 4400,3200,4400,3200,400,a1,LEFT,CALU1 +S 4400,4000,4400,4000,400,a2,LEFT,CALU1 +S 4700,4900,4700,6000,600,*,UP,PDIF +S 4700,5000,4700,6800,400,*,UP,ALU1 +S 500,4100,500,5100,600,*,UP,PDIF +S 500,4900,500,6800,400,*,UP,ALU1 +S 600,6600,1400,6600,600,*,RIGHT,NTIE +V 1100,1600,CONT_DIF_N,* +V 1200,3100,CONT_POLY,* +V 1400,6600,CONT_BODY_N,* +V 1500,4200,CONT_DIF_P,* +V 1500,4900,CONT_DIF_P,* +V 2400,3300,CONT_POLY,an +V 2600,6600,CONT_DIF_P,* +V 2900,600,CONT_DIF_N,* +V 3400,4100,CONT_POLY,* +V 3700,5600,CONT_DIF_P,an +V 4400,3200,CONT_POLY,* +V 4700,1600,CONT_DIF_N,an +V 4700,5100,CONT_DIF_P,* +V 4700,5900,CONT_DIF_P,* +V 500,5000,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aon21bv0x1.vbe b/pdks/symbolic/vsclib/cells/aon21bv0x1.vbe new file mode 100755 index 000000000..00c589b3e --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aon21bv0x1.vbe @@ -0,0 +1,38 @@ +ENTITY aon21bv0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a2 : NATURAL := 4; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a2_z : NATURAL := 3090; + CONSTANT rdown_a1_z : NATURAL := 3080; + CONSTANT rdown_b_z : NATURAL := 3100; + CONSTANT rup_a2_z : NATURAL := 4250; + CONSTANT rup_a1_z : NATURAL := 4250; + CONSTANT rup_b_z : NATURAL := 4240; + CONSTANT tphh_a2_z : NATURAL := 79; + CONSTANT tphl_b_z : NATURAL := 35; + CONSTANT tplh_b_z : NATURAL := 46; + CONSTANT tphh_a1_z : NATURAL := 80; + CONSTANT tpll_a1_z : NATURAL := 86; + CONSTANT tpll_a2_z : NATURAL := 95; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a2 : in BIT; + a1 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aon21bv0x1; + +ARCHITECTURE behaviour_data_flow OF aon21bv0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aon21bv0x1" + SEVERITY WARNING; + z <= not b or (a1 and a2) after 162 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aon21bv0x2.ap b/pdks/symbolic/vsclib/cells/aon21bv0x2.ap new file mode 100755 index 000000000..03357fe25 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aon21bv0x2.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H aon21bv0x2,P,22/ 6/2024,100 +A 0,0,5600,7200 +R 1200,2400,ref_ref,b_24 +R 1200,3200,ref_ref,b_32 +R 1200,4800,ref_ref,z_48 +R 2000,1600,ref_ref,b_16 +R 3600,2400,ref_ref,a2_24 +R 3600,3200,ref_ref,a2_32 +R 3600,4800,ref_ref,a1_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 4400,2400,ref_ref,a2_24 +R 4400,4000,ref_ref,a1_40 +S 4200,3000,4200,4200,200,*,UP,POLY +S 4000,3000,4200,3000,200,*,RIGHT,POLY +S 1000,3100,1000,3700,200,*,DOWN,POLY +S 1400,2700,1400,3300,200,*,UP,POLY +S 3300,3400,3300,4100,200,*,UP,POLY +S 3200,3900,3200,4500,200,*,DOWN,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,3200,1000,4100,200,*,UP,POLY +S 1000,4100,1000,6500,200,t05,UP,PTRANS +S 1000,6500,1000,6900,200,*,UP,POLY +S 1200,2300,1200,3300,400,*,UP,ALU1 +S 1200,2300,2000,2300,400,*,RIGHT,ALU1 +S 1200,2400,1200,3200,400,b,UP,CALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1400,600,1400,2600,200,t06,UP,NTRANS +S 1500,4800,1500,5700,400,*,UP,ALU1 +S 1800,800,1800,2400,400,n2,UP,NDIF +S 2000,1500,2000,2300,400,*,UP,ALU1 +S 2000,1600,2000,1600,400,b,LEFT,CALU1 +S 2000,3200,2000,4100,200,*,UP,POLY +S 2000,4100,2000,6500,200,t07,UP,PTRANS +S 2000,6500,2000,6900,200,*,UP,POLY +S 2100,3200,2800,3200,400,*,RIGHT,ALU1 +S 2100,600,2100,2600,200,t08,UP,NTRANS +S 2500,3200,2500,5600,400,*,UP,ALU1 +S 2500,5600,3800,5600,400,*,RIGHT,ALU1 +S 2600,4300,2600,6400,600,*,UP,PDIF +S 2600,6300,2600,6800,600,*,UP,ALU1 +S 2700,500,2700,2400,600,*,UP,NDIF +S 2800,1500,2800,3200,400,*,UP,ALU1 +S 2800,1500,4600,1500,400,*,RIGHT,ALU1 +S 3200,4600,3200,6600,200,t03,UP,PTRANS +S 3300,2600,3300,4000,200,*,UP,POLY +S 3300,4000,3600,4000,400,*,RIGHT,ALU1 +S 3300,500,3300,900,200,*,UP,POLY +S 3300,900,3300,2600,200,t04,UP,NTRANS +S 3500,4800,4400,4800,400,*,RIGHT,ALU1 +S 3600,2300,3600,4000,400,*,UP,ALU1 +S 3600,2400,3600,3200,400,a2,UP,CALU1 +S 3600,2400,4400,2400,600,*,RIGHT,ALU1 +S 3600,4800,3600,4800,400,a1,LEFT,CALU1 +S 3700,1100,3700,2400,400,n1,UP,NDIF +S 4000,500,4000,900,200,*,UP,POLY +S 4000,900,4000,2600,200,t02,UP,NTRANS +S 400,1500,1000,1500,400,*,RIGHT,ALU1 +S 400,1500,400,4800,400,*,UP,ALU1 +S 400,1600,400,4000,400,z,UP,CALU1 +S 400,4800,1500,4800,400,*,RIGHT,ALU1 +S 4200,4600,4200,6600,200,t01,UP,PTRANS +S 4400,2400,4400,2400,400,a2,LEFT,CALU1 +S 4400,3900,4400,4800,400,*,UP,ALU1 +S 4400,4000,4400,4000,400,a1,LEFT,CALU1 +S 4700,4800,4700,6400,600,*,UP,PDIF +S 4700,5600,4700,6800,600,*,UP,ALU1 +S 500,4300,500,6300,600,*,UP,PDIF +S 500,5500,500,6800,600,*,UP,ALU1 +V 1200,3200,CONT_POLY,* +V 1500,4900,CONT_DIF_P,* +V 1500,5600,CONT_DIF_P,* +V 2200,3200,CONT_POLY,an +V 2600,6300,CONT_DIF_P,* +V 2700,600,CONT_DIF_N,* +V 3400,4000,CONT_POLY,* +V 3700,5600,CONT_DIF_P,an +V 4400,4000,CONT_POLY,* +V 4500,1500,CONT_DIF_N,an +V 4700,5600,CONT_DIF_P,* +V 4700,6300,CONT_DIF_P,* +V 500,5500,CONT_DIF_P,* +V 500,6200,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aon21bv0x2.vbe b/pdks/symbolic/vsclib/cells/aon21bv0x2.vbe new file mode 100755 index 000000000..1a2a3ab40 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aon21bv0x2.vbe @@ -0,0 +1,38 @@ +ENTITY aon21bv0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT cin_b : NATURAL := 6; + CONSTANT rdown_a2_z : NATURAL := 1850; + CONSTANT rdown_a1_z : NATURAL := 1850; + CONSTANT rdown_b_z : NATURAL := 1850; + CONSTANT rup_a2_z : NATURAL := 2470; + CONSTANT rup_a1_z : NATURAL := 2470; + CONSTANT rup_b_z : NATURAL := 2470; + CONSTANT tphh_a2_z : NATURAL := 80; + CONSTANT tphl_b_z : NATURAL := 34; + CONSTANT tplh_b_z : NATURAL := 44; + CONSTANT tphh_a1_z : NATURAL := 80; + CONSTANT tpll_a1_z : NATURAL := 87; + CONSTANT tpll_a2_z : NATURAL := 96; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a2 : in BIT; + a1 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aon21bv0x2; + +ARCHITECTURE behaviour_data_flow OF aon21bv0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aon21bv0x2" + SEVERITY WARNING; + z <= not b or (a1 and a2) after 124 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/aon21v0x05.ap b/pdks/symbolic/vsclib/cells/aon21v0x05.ap new file mode 100755 index 000000000..39edbd8c3 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aon21v0x05.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 6 +H aon21v0x05,P, 5/ 7/2024,100 +A 0,0,6400,7200 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 6000,4000,ref_ref,a1_40 +R 6000,4800,ref_ref,a1_48 +R 5200,4800,ref_ref,a1_48 +R 5200,2400,ref_ref,a2_24 +R 3600,3200,ref_ref,b_32 +R 3600,4000,ref_ref,b_40 +R 3600,4800,ref_ref,b_48 +R 4400,4800,ref_ref,b_48 +R 1200,2400,ref_ref,z_24 +R 4400,3200,ref_ref,a2_32 +S 2100,3700,2100,5300,800,*,UP,TALU8 +S 1400,2900,1400,3300,200,*,UP,POLY +S 400,800,1800,800,200,*,RIGHT,ALU1 +S 300,6400,1600,6400,200,*,RIGHT,ALU1 +S 2000,1600,2800,1600,400,*,LEFT,ALU1 +S 1500,3200,2700,3200,400,*,RIGHT,ALU1 +S 1400,1600,1400,2000,200,*,DOWN,POLY +S 1400,2000,1400,2600,200,t08,UP,NTRANS +S 2000,1600,2700,1600,600,*,LEFT,NDIF +S 2000,400,2000,2400,400,*,DOWN,ALU1 +S 400,2400,1200,2400,600,*,RIGHT,ALU1 +S 2000,1500,2000,2400,600,*,UP,NDIF +S 1000,3400,1700,3400,200,*,RIGHT,POLY +S 600,6600,1400,6600,600,*,RIGHT,NTIE +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 1000,3800,1000,5000,200,t07,UP,PTRANS +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,400,6400,400,800,*,RIGHT,ALU1 +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 3200,1300,3200,1900,200,t06,UP,NTRANS +S 4200,1200,4200,1900,200,t04,UP,NTRANS +S 4900,1200,4900,1900,200,t02,UP,NTRANS +S 3700,1500,3700,2400,400,*,DOWN,ALU1 +S 2700,2400,3700,2400,400,*,RIGHT,ALU1 +S 4400,2400,4400,3300,400,*,DOWN,ALU1 +S 4400,2400,5300,2400,400,*,RIGHT,ALU1 +S 3600,4800,4400,4800,600,*,RIGHT,ALU1 +S 3600,3100,3600,4900,400,*,UP,ALU1 +S 3600,5700,6000,5700,400,*,RIGHT,ALU1 +S 4200,4400,4200,6000,200,t03,UP,PTRANS +S 5400,4400,5400,6000,200,t01,UP,PTRANS +S 3200,4400,3200,6000,200,t05,UP,PTRANS +S 5200,4800,6000,4800,600,*,RIGHT,ALU1 +S 5900,3700,5900,4900,400,*,DOWN,ALU1 +S 6000,3700,6000,4900,400,*,DOWN,ALU1 +S 4800,4600,4800,6700,600,*,DOWN,PDIF +S 3400,3200,3600,3200,600,*,RIGHT,ALU1 +S 600,600,1400,600,600,*,RIGHT,PTIE +S 1500,4600,1500,6800,400,*,UP,ALU1 +S 1500,4000,1500,4800,600,*,DOWN,PDIF +S 5400,400,5400,1600,400,*,DOWN,ALU1 +S 5400,1400,5400,1700,600,*,UP,NDIF +S 3200,1900,3200,4400,200,*,UP,POLY +S 4200,1900,4200,4400,200,*,UP,POLY +S 5400,2300,5400,4400,200,*,DOWN,POLY +S 4900,2300,5400,2300,200,*,LEFT,POLY +S 5400,3800,5900,3800,600,*,RIGHT,POLY +S 400,1500,400,4200,400,*,DOWN,ALU1 +S 400,4100,500,4100,600,*,LEFT,ALU1 +S 1000,5000,1000,5400,200,*,UP,POLY +S 3200,6000,3200,6400,200,*,UP,POLY +S 4200,6000,4200,6400,200,*,UP,POLY +S 5400,6000,5400,6400,200,*,UP,POLY +S 3200,900,3200,1300,200,*,DOWN,POLY +S 4200,800,4200,1200,200,*,DOWN,POLY +S 4900,800,4900,1200,200,*,DOWN,POLY +S 4500,1400,4500,1700,400,n2,UP,NDIF +S 2700,2400,2700,5500,400,*,DOWN,ALU1 +S 2700,4700,2700,5400,600,*,DOWN,PDIF +S 400,1600,400,4000,400,z,UP,CALU1 +S 1200,2400,1200,2400,400,z,LEFT,CALU1 +S 3600,3200,3600,4800,400,b,UP,CALU1 +S 4400,4800,4400,4800,400,b,LEFT,CALU1 +S 5200,4800,5200,4800,400,a1,LEFT,CALU1 +S 6000,4000,6000,4800,400,a1,UP,CALU1 +S 5200,2400,5200,2400,400,a2,LEFT,CALU1 +S 4400,3200,4400,3200,400,a2,LEFT,CALU1 +V 2700,1600,CONT_DIF_N,* +V 1600,3200,CONT_POLY,* +V 900,2300,CONT_DIF_N,* +V 2000,2300,CONT_DIF_N,* +V 2000,1600,CONT_DIF_N,* +V 600,6600,CONT_BODY_N,* +V 500,4100,CONT_DIF_P,* +V 1400,6600,CONT_BODY_N,* +V 3400,3200,CONT_POLY,* +V 4400,3200,CONT_POLY,* +V 3700,1600,CONT_DIF_N,* +V 5400,1500,CONT_DIF_N,* +V 3700,5700,CONT_DIF_P,n1 +V 5900,5700,CONT_DIF_P,n1 +V 2700,4700,CONT_DIF_P,* +V 5900,3800,CONT_POLY,* +V 1500,4700,CONT_DIF_P,* +V 4800,6600,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 1400,600,CONT_BODY_P,* +V 2700,5400,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/aon21v0x05.vbe b/pdks/symbolic/vsclib/cells/aon21v0x05.vbe new file mode 100755 index 000000000..e09371957 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/aon21v0x05.vbe @@ -0,0 +1,38 @@ +ENTITY aon21v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a1_z : NATURAL := 4090; + CONSTANT rdown_a2_z : NATURAL := 4060; + CONSTANT rdown_b_z : NATURAL := 4030; + CONSTANT rup_a1_z : NATURAL := 5090; + CONSTANT rup_a2_z : NATURAL := 5090; + CONSTANT rup_b_z : NATURAL := 4970; + CONSTANT tphh_a1_z : NATURAL := 101; + CONSTANT tphh_b_z : NATURAL := 72; + CONSTANT tpll_b_z : NATURAL := 95; + CONSTANT tphh_a2_z : NATURAL := 102; + CONSTANT tpll_a2_z : NATURAL := 116; + CONSTANT tpll_a1_z : NATURAL := 125; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END aon21v0x05; + +ARCHITECTURE behaviour_data_flow OF aon21v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on aon21v0x05" + SEVERITY WARNING; + z <= (a1 and a2) or b after 216 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/bf1v0x05.ap b/pdks/symbolic/vsclib/cells/bf1v0x05.ap new file mode 100755 index 000000000..462170eab --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x05.ap @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H bf1v0x05,P, 5/ 7/2024,100 +A 0,0,3200,7200 +R 1200,4800,ref_ref,z_48 +R 2000,4800,ref_ref,a_48 +R 2000,5600,ref_ref,a_56 +R 2800,5600,ref_ref,a_56 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +S 600,6100,600,6700,600,*,UP,NTIE +S 2200,5300,2200,5800,200,*,UP,POLY +S 0,400,3200,400,800,*,RIGHT,ALU1 +S 0,400,3200,400,800,vss,RIGHT,CALU1 +S 0,5400,3200,5400,4400,*,RIGHT,NWELL +S 0,6800,3200,6800,800,*,RIGHT,ALU1 +S 0,6800,3200,6800,800,vdd,RIGHT,CALU1 +S 1000,1600,1000,2000,200,*,UP,POLY +S 1000,2000,1000,2600,200,t04,UP,NTRANS +S 1000,3100,1000,4100,200,*,UP,POLY +S 1000,4100,1000,5300,200,t03,UP,PTRANS +S 1000,5300,1000,5700,200,*,UP,POLY +S 1200,3200,2800,3200,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1600,2100,1600,2400,600,*,UP,NDIF +S 1600,400,1600,2300,400,*,UP,ALU1 +S 1600,4300,1600,6700,600,*,UP,PDIF +S 2000,4700,2000,5700,400,*,UP,ALU1 +S 2000,4800,2000,5600,400,a,UP,CALU1 +S 2000,5600,2800,5600,600,*,RIGHT,ALU1 +S 2200,1500,2200,1900,200,*,UP,POLY +S 2200,1900,2200,2600,200,t02,UP,NTRANS +S 2200,2600,2200,4100,200,*,UP,POLY +S 2200,4100,2200,5100,200,t01,UP,PTRANS +S 2700,2100,2700,2400,600,*,UP,NDIF +S 2700,2300,2700,3200,600,*,UP,ALU1 +S 2700,3200,2700,4500,400,*,UP,ALU1 +S 2800,5600,2800,5600,400,a,LEFT,CALU1 +S 400,2300,400,4900,400,*,UP,ALU1 +S 400,2300,600,2300,400,*,RIGHT,ALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 400,4800,1200,4800,600,*,RIGHT,ALU1 +S 500,4300,500,4900,400,*,UP,ALU1 +S 600,600,2600,600,600,*,RIGHT,PTIE +V 1300,3200,CONT_POLY,an +V 1600,2200,CONT_DIF_N,* +V 1600,6600,CONT_DIF_P,* +V 2400,5700,CONT_POLY,* +V 2600,600,CONT_BODY_P,* +V 2600,6600,CONT_BODY_N,* +V 2700,2300,CONT_DIF_N,an +V 2700,4400,CONT_DIF_P,an +V 500,2300,CONT_DIF_N,* +V 500,4400,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/bf1v0x05.vbe b/pdks/symbolic/vsclib/cells/bf1v0x05.vbe new file mode 100755 index 000000000..7b495de2f --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x05.vbe @@ -0,0 +1,26 @@ +ENTITY bf1v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3830; + CONSTANT rup_a_z : NATURAL := 4940; + CONSTANT tpll_a_z : NATURAL := 78; + CONSTANT tphh_a_z : NATURAL := 54; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1v0x05; + +ARCHITECTURE behaviour_data_flow OF bf1v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1v0x05" + SEVERITY WARNING; + z <= a after 176 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/bf1v0x1.ap b/pdks/symbolic/vsclib/cells/bf1v0x1.ap new file mode 100755 index 000000000..5b745fff3 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x1.ap @@ -0,0 +1,59 @@ +V ALLIANCE : 6 +H bf1v0x1,P,22/ 6/2024,100 +A 0,0,3200,7200 +R 1200,4800,ref_ref,z_48 +R 2000,4800,ref_ref,a_48 +R 2000,5600,ref_ref,a_56 +R 2800,5600,ref_ref,a_56 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +S 2200,5200,2200,5900,200,*,UP,POLY +S 0,400,3200,400,800,*,RIGHT,ALU1 +S 0,400,3200,400,800,vss,RIGHT,CALU1 +S 0,5400,3200,5400,4400,*,RIGHT,NWELL +S 0,6800,3200,6800,800,*,RIGHT,ALU1 +S 0,6800,3200,6800,800,vdd,RIGHT,CALU1 +S 1000,1300,1000,1700,200,*,UP,POLY +S 1000,1700,1000,2600,200,t04,UP,NTRANS +S 1000,3100,1000,3800,200,*,UP,POLY +S 1000,3200,1300,3200,600,*,RIGHT,POLY +S 1000,3800,1000,5600,200,t03,UP,PTRANS +S 1000,5600,1000,6000,200,*,UP,POLY +S 1200,3200,2800,3200,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1600,1900,1600,2400,600,*,UP,NDIF +S 1600,4000,1600,6700,600,*,UP,PDIF +S 1600,400,1600,2200,400,*,UP,ALU1 +S 2000,4700,2000,5700,400,*,UP,ALU1 +S 2000,4800,2000,5600,400,a,UP,CALU1 +S 2000,5600,2800,5600,600,*,RIGHT,ALU1 +S 2200,1400,2200,1800,200,*,UP,POLY +S 2200,1800,2200,2600,200,t02,UP,NTRANS +S 2200,2600,2200,3800,200,*,UP,POLY +S 2200,3800,2200,5100,200,t01,UP,PTRANS +S 2700,2300,2700,3200,600,*,UP,ALU1 +S 2700,3200,2700,4200,400,*,UP,ALU1 +S 2800,5600,2800,5600,400,a,LEFT,CALU1 +S 400,2300,400,4900,400,*,UP,ALU1 +S 400,2300,600,2300,400,*,RIGHT,ALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 400,4800,1200,4800,600,*,RIGHT,ALU1 +S 500,4000,500,4900,400,*,UP,ALU1 +S 500,4100,500,4800,600,*,UP,PDIF +S 600,600,2600,600,600,*,RIGHT,PTIE +V 1300,3200,CONT_POLY,an +V 1600,2100,CONT_DIF_N,* +V 1600,6600,CONT_DIF_P,* +V 2400,5700,CONT_POLY,* +V 2600,600,CONT_BODY_P,* +V 2600,6600,CONT_BODY_N,* +V 2700,2300,CONT_DIF_N,an +V 2700,4100,CONT_DIF_P,an +V 500,2300,CONT_DIF_N,* +V 500,4100,CONT_DIF_P,* +V 500,4800,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/bf1v0x1.vbe b/pdks/symbolic/vsclib/cells/bf1v0x1.vbe new file mode 100755 index 000000000..8c25fb491 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x1.vbe @@ -0,0 +1,26 @@ +ENTITY bf1v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 2550; + CONSTANT rup_a_z : NATURAL := 3290; + CONSTANT tpll_a_z : NATURAL := 77; + CONSTANT tphh_a_z : NATURAL := 56; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1v0x1; + +ARCHITECTURE behaviour_data_flow OF bf1v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1v0x1" + SEVERITY WARNING; + z <= a after 140 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/bf1v0x12.ap b/pdks/symbolic/vsclib/cells/bf1v0x12.ap new file mode 100755 index 000000000..b8b334ecb --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x12.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 6 +H bf1v0x12,P,15/12/2007,1000 +A 0,0,104000,72000 +R 92000,32000,ref_ref,a_32 +R 92000,24000,ref_ref,a_24 +R 84000,32000,ref_ref,a_32 +R 52000,40000,ref_ref,z_40 +R 52000,24000,ref_ref,z_24 +R 44000,40000,ref_ref,z_40 +R 44000,24000,ref_ref,z_24 +R 36000,48000,ref_ref,z_48 +R 36000,40000,ref_ref,z_40 +R 36000,24000,ref_ref,z_24 +R 36000,16000,ref_ref,z_16 +R 28000,40000,ref_ref,z_40 +R 28000,32000,ref_ref,z_32 +R 20000,40000,ref_ref,z_40 +R 12000,40000,ref_ref,z_40 +S 75000,15000,75000,40000,4000,*,UP,ALU1 +S 95000,5000,95000,22000,6000,*,UP,PTIE +S 95000,41000,95000,48000,6000,*,UP,PDIF +S 95000,40000,95000,49000,4000,*,UP,ALU1 +S 93000,23000,93000,32000,4000,*,UP,ALU1 +S 92000,24000,92000,32000,4000,a,UP,CALU1 +S 92000,23000,92000,32000,4000,*,UP,ALU1 +S 90000,38000,90000,57000,2000,t03,UP,PTRANS +S 85000,47000,85000,68000,6000,*,UP,ALU1 +S 85000,4000,85000,22000,4000,*,UP,ALU1 +S 85000,12000,85000,24000,6000,*,UP,NDIF +S 84000,32000,84000,32000,4000,a,LEFT,CALU1 +S 83000,32000,93000,32000,4000,*,RIGHT,ALU1 +S 80000,6000,80000,10000,2000,*,UP,POLY +S 80000,38000,80000,57000,2000,t02,UP,PTRANS +S 80000,10000,80000,26000,2000,t05,UP,NTRANS +S 75000,66000,94000,66000,6000,*,RIGHT,NTIE +S 75000,40000,95000,40000,4000,*,RIGHT,ALU1 +S 75000,40000,75000,49000,4000,*,UP,ALU1 +S 70000,6000,70000,10000,2000,*,UP,POLY +S 70000,38000,70000,57000,2000,t01,UP,PTRANS +S 70000,32000,90000,32000,6000,*,RIGHT,POLY +S 70000,10000,70000,26000,2000,t04,UP,NTRANS +S 65000,8000,65000,24000,4000,*,UP,NDIF +S 65000,47000,65000,68000,6000,*,UP,ALU1 +S 65000,4000,65000,23000,4000,*,UP,ALU1 +S 65000,40000,65000,59000,4000,*,UP,PDIF +S 60000,61000,60000,65000,2000,*,UP,POLY +S 60000,6000,60000,26000,2000,t15,UP,NTRANS +S 60000,38000,60000,61000,2000,t11,UP,PTRANS +S 55000,40000,55000,49000,4000,*,UP,ALU1 +S 55000,15000,55000,24000,4000,*,UP,ALU1 +S 52000,40000,52000,40000,4000,z,LEFT,CALU1 +S 52000,24000,52000,24000,4000,z,LEFT,CALU1 +S 5000,48000,5000,68000,4000,*,UP,ALU1 +S 5000,40000,5000,64000,6000,*,UP,PDIF +S 50000,6000,50000,26000,2000,t14,UP,NTRANS +S 50000,38000,50000,66000,2000,t10,UP,PTRANS +S 50000,32000,60000,32000,6000,*,RIGHT,POLY +S 45000,54000,45000,68000,4000,*,UP,ALU1 +S 45000,4000,45000,16000,6000,*,UP,ALU1 +S 44000,40000,44000,40000,4000,z,LEFT,CALU1 +S 44000,24000,44000,24000,4000,z,LEFT,CALU1 +S 40000,6000,40000,26000,2000,t13,UP,NTRANS +S 40000,38000,40000,66000,2000,t09,UP,PTRANS +S 37000,32000,75000,32000,4000,*,RIGHT,ALU1 +S 36000,40000,36000,49000,4000,*,UP,ALU1 +S 36000,40000,36000,48000,4000,z,UP,CALU1 +S 36000,16000,36000,24000,4000,z,UP,CALU1 +S 36000,15000,36000,24000,4000,*,UP,ALU1 +S 35000,40000,35000,49000,4000,*,UP,ALU1 +S 35000,15000,35000,24000,4000,*,UP,ALU1 +S 30000,6000,30000,26000,2000,t12,UP,NTRANS +S 30000,38000,30000,66000,2000,t08,UP,PTRANS +S 30000,32000,40000,32000,6000,*,RIGHT,POLY +S 28000,32000,28000,40000,4000,z,UP,CALU1 +S 28000,24000,55000,24000,4000,*,RIGHT,ALU1 +S 28000,24000,28000,40000,4000,*,UP,ALU1 +S 25000,54000,25000,68000,4000,*,UP,ALU1 +S 25000,4000,25000,16000,6000,*,UP,ALU1 +S 24000,8000,24000,24000,6000,*,UP,NDIF +S 20000,40000,20000,40000,4000,z,LEFT,CALU1 +S 20000,38000,20000,66000,2000,t07,UP,PTRANS +S 15000,40000,15000,49000,4000,*,UP,ALU1 +S 12000,40000,12000,40000,4000,z,LEFT,CALU1 +S 11000,40000,55000,40000,4000,*,RIGHT,ALU1 +S 10000,5000,10000,22000,14000,*,UP,PTIE +S 10000,38000,10000,66000,2000,t06,UP,PTRANS +S 10000,34000,30000,34000,2000,*,RIGHT,POLY +S 0,68000,104000,68000,8000,vdd,RIGHT,CALU1 +S 0,68000,104000,68000,8000,*,RIGHT,ALU1 +S 0,54000,104000,54000,44000,*,RIGHT,NWELL +S 0,4000,104000,4000,8000,vss,RIGHT,CALU1 +S 0,4000,104000,4000,8000,*,RIGHT,ALU1 +V 75000,16000,CONT_DIF_N,an +V 95000,6000,CONT_BODY_P,* +V 95000,48000,CONT_DIF_P,an +V 95000,41000,CONT_DIF_P,an +V 94000,66000,CONT_BODY_N,* +V 85000,54000,CONT_DIF_P,* +V 85000,47000,CONT_DIF_P,* +V 85000,21000,CONT_DIF_N,* +V 85000,13000,CONT_DIF_N,* +V 84000,32000,CONT_POLY,* +V 75000,66000,CONT_BODY_N,* +V 75000,48000,CONT_DIF_P,an +V 75000,41000,CONT_DIF_P,an +V 75000,23000,CONT_DIF_N,an +V 65000,54000,CONT_DIF_P,* +V 65000,47000,CONT_DIF_P,* +V 65000,22000,CONT_DIF_N,* +V 65000,14000,CONT_DIF_N,* +V 6000,6000,CONT_BODY_P,* +V 55000,48000,CONT_DIF_P,* +V 55000,41000,CONT_DIF_P,* +V 55000,32000,CONT_POLY,an +V 55000,23000,CONT_DIF_N,* +V 55000,16000,CONT_DIF_N,* +V 5000,63000,CONT_DIF_P,* +V 5000,56000,CONT_DIF_P,* +V 5000,49000,CONT_DIF_P,* +V 45000,9000,CONT_DIF_N,* +V 45000,63000,CONT_DIF_P,* +V 45000,55000,CONT_DIF_P,* +V 45000,16000,CONT_DIF_N,* +V 38000,32000,CONT_POLY,an +V 35000,48000,CONT_DIF_P,* +V 35000,41000,CONT_DIF_P,* +V 35000,23000,CONT_DIF_N,* +V 35000,16000,CONT_DIF_N,* +V 25000,9000,CONT_DIF_N,* +V 25000,63000,CONT_DIF_P,* +V 25000,55000,CONT_DIF_P,* +V 25000,16000,CONT_DIF_N,* +V 15000,48000,CONT_DIF_P,* +V 15000,41000,CONT_DIF_P,* +V 14000,6000,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/bf1v0x12.vbe b/pdks/symbolic/vsclib/cells/bf1v0x12.vbe new file mode 100755 index 000000000..4c7d9e338 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x12.vbe @@ -0,0 +1,26 @@ +ENTITY bf1v0x12 IS +GENERIC ( + CONSTANT area : NATURAL := 7488; + CONSTANT cin_a : NATURAL := 11; + CONSTANT rdown_a_z : NATURAL := 290; + CONSTANT rup_a_z : NATURAL := 360; + CONSTANT tpll_a_z : NATURAL := 91; + CONSTANT tphh_a_z : NATURAL := 70; + CONSTANT transistors : NATURAL := 15 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1v0x12; + +ARCHITECTURE behaviour_data_flow OF bf1v0x12 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1v0x12" + SEVERITY WARNING; + z <= a after 89 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/bf1v0x2.ap b/pdks/symbolic/vsclib/cells/bf1v0x2.ap new file mode 100755 index 000000000..38b8e0444 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x2.ap @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H bf1v0x2,P,22/ 6/2024,100 +A 0,0,3200,7200 +R 1200,5600,ref_ref,z_56 +R 2000,3200,ref_ref,a_32 +R 2800,3200,ref_ref,a_32 +R 2800,4000,ref_ref,a_40 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +S 2200,2700,2200,3600,200,*,UP,POLY +S 1000,2800,1000,3700,200,*,UP,POLY +S 0,400,3200,400,800,*,RIGHT,ALU1 +S 0,400,3200,400,800,vss,RIGHT,CALU1 +S 0,5400,3200,5400,4400,*,RIGHT,NWELL +S 0,6800,3200,6800,800,*,RIGHT,ALU1 +S 0,6800,3200,6800,800,vdd,RIGHT,CALU1 +S 1000,1200,1000,2600,200,t04,UP,NTRANS +S 1000,3800,1000,6600,200,t03,UP,PTRANS +S 1000,800,1000,1200,200,*,UP,POLY +S 1200,2300,1200,4800,400,*,UP,ALU1 +S 1200,2300,2800,2300,400,*,RIGHT,ALU1 +S 1200,4800,2800,4800,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1600,1400,1600,2400,600,*,UP,NDIF +S 1600,4000,1600,6700,600,*,UP,PDIF +S 1600,400,1600,1500,600,*,UP,ALU1 +S 2000,3200,2000,3200,400,a,LEFT,CALU1 +S 2000,3200,2800,3200,600,*,RIGHT,ALU1 +S 2200,1200,2200,1600,200,*,UP,POLY +S 2200,1600,2200,2600,200,t02,UP,NTRANS +S 2200,3800,2200,5500,200,t01,UP,PTRANS +S 2200,5500,2200,5900,200,*,UP,POLY +S 2800,3100,2800,4100,400,*,UP,ALU1 +S 2800,3200,2800,4000,400,a,UP,CALU1 +S 400,1500,400,4800,400,*,UP,ALU1 +S 400,1500,400,5700,400,*,UP,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 400,4800,400,5700,400,*,UP,ALU1 +S 400,5600,1300,5600,400,*,RIGHT,ALU1 +S 400,5700,1300,5700,400,*,RIGHT,ALU1 +S 500,1400,500,2400,600,*,UP,NDIF +S 500,1500,500,2400,400,*,UP,ALU1 +S 500,4800,500,5700,400,*,UP,ALU1 +S 500,4900,500,5700,600,*,UP,PDIF +V 1200,3200,CONT_POLY,an +V 1600,1500,CONT_DIF_N,* +V 1600,6600,CONT_DIF_P,* +V 2400,3200,CONT_POLY,* +V 2600,600,CONT_BODY_P,* +V 2600,6600,CONT_BODY_N,* +V 2700,2300,CONT_DIF_N,an +V 2700,4800,CONT_DIF_P,an +V 500,1600,CONT_DIF_N,* +V 500,2300,CONT_DIF_N,* +V 500,4900,CONT_DIF_P,* +V 500,5600,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/bf1v0x2.vbe b/pdks/symbolic/vsclib/cells/bf1v0x2.vbe new file mode 100755 index 000000000..b4278ed74 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x2.vbe @@ -0,0 +1,26 @@ +ENTITY bf1v0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 1650; + CONSTANT rup_a_z : NATURAL := 2120; + CONSTANT tpll_a_z : NATURAL := 82; + CONSTANT tphh_a_z : NATURAL := 62; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1v0x2; + +ARCHITECTURE behaviour_data_flow OF bf1v0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1v0x2" + SEVERITY WARNING; + z <= a after 119 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/bf1v0x4.ap b/pdks/symbolic/vsclib/cells/bf1v0x4.ap new file mode 100755 index 000000000..2396b8b7e --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x4.ap @@ -0,0 +1,73 @@ +V ALLIANCE : 6 +H bf1v0x4,P, 7/ 6/2006,1000 +A 0,0,40000,72000 +R 12000,16000,ref_ref,z_16 +R 12000,48000,ref_ref,z_48 +R 20000,40000,ref_ref,a_40 +R 28000,32000,ref_ref,a_32 +R 4000,32000,ref_ref,z_32 +R 4000,40000,ref_ref,z_40 +R 12000,24000,ref_ref,z_24 +R 28000,40000,ref_ref,a_40 +S 19000,24000,36000,24000,4000,*,RIGHT,ALU1 +S 0,4000,40000,4000,8000,*,RIGHT,ALU1 +S 0,4000,40000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,40000,54000,44000,*,RIGHT,NWELL +S 0,68000,40000,68000,8000,*,RIGHT,ALU1 +S 0,68000,40000,68000,8000,vdd,RIGHT,CALU1 +S 10000,32000,18000,32000,6000,*,RIGHT,POLY +S 10000,38000,10000,66000,2000,t03,UP,PTRANS +S 12000,48000,12000,48000,4000,z,LEFT,CALU1 +S 15000,48000,15000,57000,4000,*,UP,ALU1 +S 20000,38000,20000,66000,2000,t04,UP,PTRANS +S 20000,40000,20000,40000,4000,a,LEFT,CALU1 +S 24000,40000,24000,64000,6000,*,UP,PDIF +S 25000,54000,25000,68000,4000,*,UP,ALU1 +S 28000,31000,28000,40000,4000,*,UP,ALU1 +S 30000,11000,30000,26000,2000,t02,UP,NTRANS +S 30000,38000,30000,65000,2000,t01,UP,PTRANS +S 30000,65000,30000,69000,2000,*,UP,POLY +S 30000,7000,30000,11000,2000,*,UP,POLY +S 35000,15000,35000,23000,6000,*,UP,NDIF +S 4000,48000,15000,48000,4000,*,RIGHT,ALU1 +S 5000,40000,5000,64000,6000,*,UP,PDIF +S 5000,56000,5000,68000,6000,*,UP,ALU1 +S 29000,31000,29000,40000,4000,*,UP,ALU1 +S 19000,40000,29000,40000,4000,*,RIGHT,ALU1 +S 35000,48000,35000,55000,6000,*,UP,PDIF +S 35000,47000,35000,56000,4000,*,DOWN,ALU1 +S 36000,24000,36000,56000,4000,*,UP,ALU1 +S 35000,15000,35000,24000,4000,*,DOWN,ALU1 +S 19000,24000,19000,33000,4000,*,UP,ALU1 +S 4000,31000,12000,31000,4000,*,LEFT,ALU1 +S 4000,32000,4000,40000,4000,z,UP,CALU1 +S 4000,31000,4000,48000,4000,*,UP,ALU1 +S 12000,16000,12000,24000,4000,z,UP,CALU1 +S 20000,12000,20000,26000,2000,t05,UP,NTRANS +S 10000,12000,10000,26000,2000,t06,UP,NTRANS +S 12000,15000,12000,31000,4000,*,UP,ALU1 +S 12000,16000,15000,16000,6000,*,RIGHT,ALU1 +S 5000,4000,5000,23000,4000,*,DOWN,ALU1 +S 5000,14000,5000,24000,6000,*,UP,NDIF +S 25000,4000,25000,16000,4000,*,UP,ALU1 +S 25000,13000,25000,24000,4000,*,UP,NDIF +S 20000,8000,20000,12000,2000,*,UP,POLY +S 10000,8000,10000,12000,2000,*,UP,POLY +S 28000,32000,28000,40000,4000,a,UP,CALU1 +V 15000,49000,CONT_DIF_P,* +V 15000,56000,CONT_DIF_P,* +V 25000,55000,CONT_DIF_P,* +V 25000,62000,CONT_DIF_P,* +V 35000,16000,CONT_DIF_N,an +V 35000,23000,CONT_DIF_N,an +V 35000,48000,CONT_DIF_P,an +V 5000,56000,CONT_DIF_P,* +V 5000,63000,CONT_DIF_P,* +V 29000,32000,CONT_POLY,* +V 35000,55000,CONT_DIF_P,an +V 19000,32000,CONT_POLY,an +V 15000,16000,CONT_DIF_N,* +V 5000,15000,CONT_DIF_N,* +V 5000,22000,CONT_DIF_N,* +V 25000,15000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/bf1v0x4.vbe b/pdks/symbolic/vsclib/cells/bf1v0x4.vbe new file mode 100755 index 000000000..d4fae7bc7 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x4.vbe @@ -0,0 +1,26 @@ +ENTITY bf1v0x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_a : NATURAL := 6; + CONSTANT rdown_a_z : NATURAL := 830; + CONSTANT rup_a_z : NATURAL := 1060; + CONSTANT tpll_a_z : NATURAL := 84; + CONSTANT tphh_a_z : NATURAL := 65; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1v0x4; + +ARCHITECTURE behaviour_data_flow OF bf1v0x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1v0x4" + SEVERITY WARNING; + z <= a after 98 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/bf1v0x8.ap b/pdks/symbolic/vsclib/cells/bf1v0x8.ap new file mode 100755 index 000000000..6a5d2fa5f --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x8.ap @@ -0,0 +1,117 @@ +V ALLIANCE : 6 +H bf1v0x8,P,22/ 6/2024,100 +A 0,0,7200,7200 +R 1200,4000,ref_ref,z_40 +R 2000,2400,ref_ref,z_24 +R 2000,3200,ref_ref,z_32 +R 2000,4000,ref_ref,z_40 +R 2800,2400,ref_ref,z_24 +R 2800,4000,ref_ref,z_40 +R 3600,1600,ref_ref,z_16 +R 3600,2400,ref_ref,z_24 +R 3600,4000,ref_ref,z_40 +R 3600,4800,ref_ref,z_48 +R 6000,4000,ref_ref,a_40 +R 6800,3200,ref_ref,a_32 +R 6800,4000,ref_ref,a_40 +S 4000,2700,4000,3700,200,*,UP,POLY +S 0,400,7200,400,800,*,RIGHT,ALU1 +S 0,400,7200,400,800,vss,RIGHT,CALU1 +S 0,5400,7200,5400,4400,*,RIGHT,NWELL +S 0,6800,7200,6800,800,*,RIGHT,ALU1 +S 0,6800,7200,6800,800,vdd,RIGHT,CALU1 +S 1000,1300,1000,2600,200,t12,UP,NTRANS +S 1000,2600,1000,3800,200,*,UP,POLY +S 1000,3400,2000,3400,200,*,RIGHT,POLY +S 1000,3800,1000,6400,200,t08,UP,PTRANS +S 1000,6400,1000,6800,200,*,UP,POLY +S 1000,900,1000,1300,200,*,UP,POLY +S 1100,4000,3600,4000,400,*,RIGHT,ALU1 +S 1100,4000,3700,4000,400,*,RIGHT,ALU1 +S 1200,4000,1200,4000,400,z,LEFT,CALU1 +S 1500,1500,1500,2400,400,*,UP,ALU1 +S 1500,2400,3700,2400,400,*,RIGHT,ALU1 +S 1500,4000,1500,4900,400,*,UP,ALU1 +S 2000,1300,2000,2600,200,t11,UP,NTRANS +S 2000,2400,2000,4000,400,*,UP,ALU1 +S 2000,2400,2000,4000,400,z,UP,CALU1 +S 2000,3200,3800,3200,600,*,RIGHT,POLY +S 2000,3800,2000,6400,200,t07,UP,PTRANS +S 2000,6400,2000,6800,200,*,UP,POLY +S 2000,900,2000,1300,200,*,UP,POLY +S 2500,400,2500,1600,600,*,UP,ALU1 +S 2500,5200,2500,6800,400,*,UP,ALU1 +S 2800,2400,2800,2400,400,z,LEFT,CALU1 +S 2800,4000,2800,4000,400,z,LEFT,CALU1 +S 3000,1300,3000,2600,200,t10,UP,NTRANS +S 3000,3200,5500,3200,400,*,RIGHT,ALU1 +S 3000,3800,3000,6400,200,t06,UP,PTRANS +S 3000,6400,3000,6800,200,*,UP,POLY +S 3000,900,3000,1300,200,*,UP,POLY +S 3600,1500,3600,2400,600,*,UP,ALU1 +S 3600,1600,3600,2400,400,z,UP,CALU1 +S 3600,4000,3600,4800,400,z,UP,CALU1 +S 3600,4000,3600,4900,600,*,UP,ALU1 +S 4000,1300,4000,2600,200,t09,UP,NTRANS +S 4000,3800,4000,6400,200,t05,UP,PTRANS +S 4000,6400,4000,6800,200,*,UP,POLY +S 4000,900,4000,1300,200,*,UP,POLY +S 4400,1500,4400,2400,600,*,UP,NDIF +S 4500,400,4500,2400,400,*,UP,ALU1 +S 4500,5200,4500,6800,400,*,UP,ALU1 +S 5000,1300,5000,2600,200,t04,UP,NTRANS +S 5000,2600,5000,3800,200,*,UP,POLY +S 5000,3400,6000,3400,200,*,RIGHT,POLY +S 5000,3800,5000,6400,200,t02,UP,PTRANS +S 5000,6400,5000,6800,200,*,UP,POLY +S 5000,900,5000,1300,200,*,UP,POLY +S 500,1500,500,2400,600,*,UP,NDIF +S 500,4000,500,6200,600,*,UP,PDIF +S 500,400,500,2400,400,*,UP,ALU1 +S 500,5200,500,6800,400,*,UP,ALU1 +S 5200,3200,5200,4900,400,*,UP,ALU1 +S 5200,4900,5600,4900,400,*,RIGHT,ALU1 +S 5500,2200,5500,3200,400,*,UP,ALU1 +S 6000,1200,6000,1600,200,*,UP,POLY +S 6000,1600,6000,2600,200,t03,UP,NTRANS +S 6000,3200,6500,3200,600,*,RIGHT,POLY +S 6000,3800,6000,5500,200,t01,UP,PTRANS +S 6000,4000,6000,4000,400,a,LEFT,CALU1 +S 6000,4000,6800,4000,600,*,RIGHT,ALU1 +S 6000,5500,6000,5900,200,*,UP,POLY +S 6500,400,6500,2000,400,*,UP,ALU1 +S 6500,5100,6500,6800,400,*,UP,ALU1 +S 6600,1800,6600,2400,600,*,UP,NDIF +S 6600,4000,6600,5300,600,*,UP,PDIF +S 6700,3100,6700,4100,400,*,UP,ALU1 +S 6800,3100,6800,4100,400,*,UP,ALU1 +S 6800,3200,6800,4000,400,a,UP,CALU1 +V 1500,1600,CONT_DIF_N,* +V 1500,2300,CONT_DIF_N,* +V 1500,4100,CONT_DIF_P,* +V 1500,4800,CONT_DIF_P,* +V 2500,1600,CONT_DIF_N,* +V 2500,5300,CONT_DIF_P,* +V 2500,6100,CONT_DIF_P,* +V 3100,3200,CONT_POLY,an +V 3500,1600,CONT_DIF_N,* +V 3500,2300,CONT_DIF_N,* +V 3500,4100,CONT_DIF_P,* +V 3500,4800,CONT_DIF_P,* +V 3800,3200,CONT_POLY,an +V 4500,1600,CONT_DIF_N,* +V 4500,2300,CONT_DIF_N,* +V 4500,5300,CONT_DIF_P,* +V 4500,6100,CONT_DIF_P,* +V 500,1600,CONT_DIF_N,* +V 500,2300,CONT_DIF_N,* +V 500,5300,CONT_DIF_P,* +V 500,6100,CONT_DIF_P,* +V 5500,2300,CONT_DIF_N,an +V 5500,4900,CONT_DIF_P,an +V 6400,600,CONT_BODY_P,* +V 6400,6600,CONT_BODY_N,* +V 6500,1900,CONT_DIF_N,* +V 6500,5200,CONT_DIF_P,* +V 6700,3200,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/bf1v0x8.vbe b/pdks/symbolic/vsclib/cells/bf1v0x8.vbe new file mode 100755 index 000000000..f6b02833a --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v0x8.vbe @@ -0,0 +1,26 @@ +ENTITY bf1v0x8 IS +GENERIC ( + CONSTANT area : NATURAL := 5184; + CONSTANT cin_a : NATURAL := 8; + CONSTANT rdown_a_z : NATURAL := 450; + CONSTANT rup_a_z : NATURAL := 570; + CONSTANT tpll_a_z : NATURAL := 85; + CONSTANT tphh_a_z : NATURAL := 67; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1v0x8; + +ARCHITECTURE behaviour_data_flow OF bf1v0x8 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1v0x8" + SEVERITY WARNING; + z <= a after 89 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/bf1v5x05.ap b/pdks/symbolic/vsclib/cells/bf1v5x05.ap new file mode 100755 index 000000000..587dbd1aa --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v5x05.ap @@ -0,0 +1,56 @@ +V ALLIANCE : 6 +H bf1v5x05,P,23/ 6/2024,100 +A 0,0,3200,7200 +R 1200,4800,ref_ref,z_48 +R 2000,4800,ref_ref,a_48 +R 2000,5600,ref_ref,a_56 +R 2800,5600,ref_ref,a_56 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +S 2200,5200,2200,5600,200,*,UP,POLY +S 1000,2800,1000,3600,200,*,UP,POLY +S 0,400,3200,400,800,*,RIGHT,ALU1 +S 0,400,3200,400,800,vss,RIGHT,CALU1 +S 0,5400,3200,5400,4400,*,RIGHT,NWELL +S 0,6800,3200,6800,800,*,RIGHT,ALU1 +S 0,6800,3200,6800,800,vdd,RIGHT,CALU1 +S 1000,1600,1000,2000,200,*,UP,POLY +S 1000,2000,1000,2600,200,t04,UP,NTRANS +S 1000,3800,1000,5000,200,t03,UP,PTRANS +S 1000,5000,1000,5400,200,*,UP,POLY +S 1100,3200,2700,3200,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1600,2200,1600,2300,600,*,UP,NDIF +S 1600,4000,1600,6700,600,*,UP,PDIF +S 1600,400,1600,2400,400,*,UP,ALU1 +S 2000,4700,2000,5700,400,*,UP,ALU1 +S 2000,4800,2000,5600,400,a,UP,CALU1 +S 2000,5600,2800,5600,600,*,RIGHT,ALU1 +S 2200,1600,2200,2000,200,*,UP,POLY +S 2200,2000,2200,2600,200,t02,UP,NTRANS +S 2200,2500,2200,3800,200,*,UP,POLY +S 2200,3800,2200,5000,200,t01,UP,PTRANS +S 2700,2200,2700,4200,400,*,UP,ALU1 +S 2800,5600,2800,5600,400,a,LEFT,CALU1 +S 400,2300,400,4900,400,*,UP,ALU1 +S 400,2300,600,2300,400,*,RIGHT,ALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 400,4800,1200,4800,600,*,RIGHT,ALU1 +S 500,4000,500,4900,400,*,UP,ALU1 +S 600,5900,600,6700,600,*,UP,NTIE +S 600,600,2600,600,600,*,RIGHT,PTIE +V 1200,3200,CONT_POLY,an +V 1600,2300,CONT_DIF_N,* +V 1600,6600,CONT_DIF_P,* +V 2400,5600,CONT_POLY,* +V 2600,600,CONT_BODY_P,* +V 2600,6600,CONT_BODY_N,* +V 2700,2300,CONT_DIF_N,an +V 2700,4100,CONT_DIF_P,an +V 500,2300,CONT_DIF_N,* +V 500,4100,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/bf1v5x05.vbe b/pdks/symbolic/vsclib/cells/bf1v5x05.vbe new file mode 100755 index 000000000..8010d863f --- /dev/null +++ b/pdks/symbolic/vsclib/cells/bf1v5x05.vbe @@ -0,0 +1,26 @@ +ENTITY bf1v5x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3820; + CONSTANT rup_a_z : NATURAL := 4940; + CONSTANT tpll_a_z : NATURAL := 71; + CONSTANT tphh_a_z : NATURAL := 59; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END bf1v5x05; + +ARCHITECTURE behaviour_data_flow OF bf1v5x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on bf1v5x05" + SEVERITY WARNING; + z <= a after 175 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/dfnt1v0x2.ap b/pdks/symbolic/vsclib/cells/dfnt1v0x2.ap new file mode 100755 index 000000000..acfed3974 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/dfnt1v0x2.ap @@ -0,0 +1,210 @@ +V ALLIANCE : 6 +H dfnt1v0x2,P, 5/ 7/2024,100 +A 0,0,14400,7200 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 12400,4800,ref_ref,cp_48 +R 12400,4000,ref_ref,cp_40 +R 11600,4000,ref_ref,cp_40 +R 10800,3200,ref_ref,d_32 +R 10000,4000,ref_ref,d_40 +R 10000,3200,ref_ref,d_32 +R 400,4800,ref_ref,z_48 +R 1200,4000,ref_ref,z_40 +S 2400,6600,4400,6600,800,*,RIGHT,NTIE +S 11400,600,13900,600,800,*,RIGHT,PTIE +S 12000,4400,12000,6100,800,*,UP,TALU8 +S 2900,3800,2900,5500,800,*,UP,TALU8 +S 11100,1200,11100,2900,800,*,UP,TALU7 +S 1800,1000,1800,2700,800,*,DOWN,TALU7 +S 8800,1500,8800,1700,600,n1,DOWN,NDIF +S 8800,5600,8800,5800,600,n1,DOWN,PDIF +S 7800,1600,7800,3400,400,n1,UP,ALU1 +S 6800,2600,7800,2600,600,*,RIGHT,ALU1 +S 6100,1500,6100,5200,400,*,UP,ALU1 +S 10600,1500,10600,1900,600,*,DOWN,NDIF +S 2700,2800,2700,3400,200,*,UP,POLY +S 2800,3000,2800,3300,200,*,DOWN,POLY +S 3200,1500,3200,2400,400,*,UP,NDIF +S 2700,1900,2700,2600,200,t18,UP,NTRANS +S 2000,3400,3100,3400,200,*,RIGHT,POLY +S 9300,4000,9300,4600,200,*,DOWN,POLY +S 8300,2000,8300,2500,200,*,UP,POLY +S 4600,4000,4600,4600,200,*,DOWN,POLY +S 5600,2000,5600,2600,200,*,UP,POLY +S 8300,2000,8300,2600,200,*,UP,POLY +S 9300,4000,9300,4600,200,*,DOWN,POLY +S 11600,3200,11600,4300,200,*,UP,POLY +S 12000,2800,12000,3300,200,*,UP,POLY +S 5600,2000,5600,2600,200,*,UP,POLY +S 4600,4000,4600,4600,200,*,DOWN,POLY +S 11900,800,13400,800,200,*,RIGHT,ALU1 +S 2700,6400,4100,6400,200,*,RIGHT,ALU1 +S 3900,1900,3900,4800,200,*,UP,POLY +S 3900,5400,3900,5800,200,*,UP,POLY +S 3900,4800,3900,5400,200,t19,UP,PTRANS +S 9900,3200,10900,3200,400,*,RIGHT,ALU1 +S 5600,6900,11000,6900,200,*,RIGHT,POLY +S 5600,300,8300,300,200,*,RIGHT,POLY +S 500,4000,500,5000,600,*,UP,PDIF +S 1500,400,1500,1400,400,*,UP,ALU1 +S 13000,5900,13000,6300,200,*,UP,POLY +S 12500,5600,12500,6800,600,*,UP,ALU1 +S 12500,5100,12500,5700,600,*,UP,PDIF +S 12400,4000,12400,4800,600,*,UP,ALU1 +S 12400,4000,12400,4800,400,cp,UP,CALU1 +S 11600,4000,11600,4000,400,cp,LEFT,CALU1 +S 11500,4000,12500,4000,400,*,RIGHT,ALU1 +S 10800,3200,10800,3200,400,d,LEFT,CALU1 +S 1000,600,3900,600,200,*,RIGHT,POLY +S 1000,2400,1000,3800,200,*,UP,POLY +S 10000,3200,10000,4000,600,*,UP,ALU1 +S 10000,3200,10000,4000,400,d,UP,CALU1 +S 0,6800,14400,6800,800,vdd,RIGHT,CALU1 +S 0,6800,14400,6800,800,*,RIGHT,ALU1 +S 0,5400,14400,5400,4400,*,RIGHT,NWELL +S 0,400,14400,400,800,vss,RIGHT,CALU1 +S 0,400,14400,400,800,*,RIGHT,ALU1 +S 8300,5900,8300,6900,200,*,UP,POLY +S 4600,4300,4600,5300,200,*,UP,POLY +S 5200,2500,5400,2500,600,*,LEFT,ALU1 +S 4600,3300,5600,3300,200,*,RIGHT,POLY +S 4700,4100,5200,4100,400,*,RIGHT,ALU1 +S 5200,2400,5200,4100,400,*,UP,ALU1 +S 3400,1500,3400,2400,400,*,UP,NDIF +S 9300,900,9300,1300,200,*,UP,POLY +S 10000,900,10000,1300,200,*,UP,POLY +S 7100,400,7100,1700,400,*,UP,ALU1 +S 7800,1600,8900,1600,400,*,RIGHT,ALU1 +S 10500,400,10500,1600,600,*,UP,ALU1 +S 3900,600,3900,1300,200,*,UP,POLY +S 4600,1900,4600,3300,200,*,UP,POLY +S 4600,900,4600,1300,200,*,UP,POLY +S 5600,300,5600,1300,200,*,UP,POLY +S 6600,900,6600,1300,200,*,DOWN,POLY +S 7600,900,7600,1300,200,*,DOWN,POLY +S 8300,300,8300,1300,200,*,UP,POLY +S 9600,1500,9600,1700,400,dnn,UP,NDIF +S 8500,2500,9100,2500,600,*,RIGHT,ALU1 +S 9100,2400,11600,2400,400,*,RIGHT,ALU1 +S 8300,3300,9300,3300,200,*,RIGHT,POLY +S 9600,4900,9600,5800,400,dnp,UP,PDIF +S 6100,4100,7500,4100,400,*,RIGHT,ALU1 +S 7900,1500,7900,1700,400,n3n,UP,NDIF +S 4200,1500,4200,1700,400,n5n,UP,NDIF +S 7800,3400,8300,3400,400,*,RIGHT,ALU1 +S 10500,5500,10500,6800,600,*,UP,ALU1 +S 9100,4800,11500,4800,400,*,RIGHT,ALU1 +S 11500,4800,11500,5100,400,*,UP,ALU1 +S 9100,2400,9100,4800,400,*,UP,ALU1 +S 11000,5800,11000,6900,200,*,UP,POLY +S 11000,4300,11600,4300,200,*,RIGHT,POLY +S 10000,1900,10000,4700,200,*,UP,POLY +S 9300,1900,9300,3300,200,*,UP,POLY +S 3000,3200,4200,3200,400,*,RIGHT,ALU1 +S 4200,1600,4200,3200,400,*,UP,ALU1 +S 4200,1600,5200,1600,400,*,RIGHT,ALU1 +S 3400,400,3400,1700,400,*,UP,ALU1 +S 400,4000,1300,4000,400,*,RIGHT,ALU1 +S 1200,4000,1200,4000,400,z,LEFT,CALU1 +S 1500,4800,1500,6800,400,*,UP,ALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 400,2000,400,4900,400,*,UP,ALU1 +S 500,4000,500,4900,400,*,UP,ALU1 +S 400,2100,500,2100,600,*,LEFT,ALU1 +S 2000,5200,2000,5600,200,*,UP,POLY +S 4200,5000,4200,5200,400,n5p,UP,PDIF +S 4600,5400,4600,5800,200,*,UP,POLY +S 3300,5000,3300,6800,400,*,UP,ALU1 +S 4000,3200,4000,5100,400,*,UP,ALU1 +S 4000,5100,5200,5100,400,*,RIGHT,ALU1 +S 2300,2200,2300,4100,400,*,UP,ALU1 +S 2300,4100,2600,4100,400,*,RIGHT,ALU1 +S 1100,3100,2300,3100,400,*,RIGHT,ALU1 +S 11700,3200,13500,3200,400,*,RIGHT,ALU1 +S 12000,1600,12000,2000,200,*,UP,POLY +S 13500,2100,13500,2400,600,*,UP,NDIF +S 12500,2100,12500,2400,400,*,UP,NDIF +S 13000,1500,13000,1900,200,*,UP,POLY +S 13000,2600,13000,4900,200,*,UP,POLY +S 11500,2300,11500,2400,600,*,UP,ALU1 +S 12500,400,12500,2400,400,*,UP,ALU1 +S 13500,2200,13500,5300,400,*,UP,ALU1 +S 12300,4200,13000,4200,600,*,RIGHT,POLY +S 1500,4000,1500,6400,400,*,DOWN,PDIF +S 13000,4900,13000,5900,200,t01,UP,PTRANS +S 13000,1900,13000,2600,200,t02,UP,NTRANS +S 11000,4700,11000,5800,200,t03,UP,PTRANS +S 12000,2000,12000,2600,200,t04,UP,NTRANS +S 10000,4700,10000,6000,200,t05,UP,PTRANS +S 10000,1300,10000,1900,200,t06,UP,NTRANS +S 9300,4700,9300,6000,200,t07,UP,PTRANS +S 9300,1300,9300,1900,200,t08,UP,NTRANS +S 6600,1300,6600,1900,200,t10,UP,NTRANS +S 7600,1300,7600,1900,200,t12,UP,NTRANS +S 8300,1300,8300,1900,200,t14,UP,NTRANS +S 5600,1300,5600,1900,200,t16,UP,NTRANS +S 2000,3800,2000,5200,200,t17,UP,PTRANS +S 3900,1300,3900,1900,200,t20,UP,NTRANS +S 4600,4800,4600,5400,200,t21,UP,PTRANS +S 4600,1300,4600,1900,200,t22,UP,NTRANS +S 1000,3800,1000,6600,200,t23,UP,PTRANS +S 1000,1000,1000,2400,200,t24,UP,NTRANS +S 8300,5700,8900,5700,400,*,RIGHT,ALU1 +S 8300,5400,8300,6000,200,t13,UP,PTRANS +S 7900,5600,7900,5800,400,n3p,UP,PDIF +S 7600,5400,7600,6000,200,t11,UP,PTRANS +S 7100,5000,7100,5800,400,*,UP,PDIF +S 6600,4800,6600,6000,200,t09,UP,PTRANS +S 5600,4800,5600,6000,200,t15,UP,PTRANS +S 5600,3300,5600,4800,200,*,UP,POLY +S 5600,6000,5600,6900,200,*,UP,POLY +S 6600,1900,6600,4800,200,*,UP,POLY +S 7600,1900,7600,5400,200,*,UP,POLY +S 8300,3300,8300,5400,200,*,UP,POLY +S 7100,5600,7100,6800,400,*,UP,ALU1 +S 8300,3400,8300,5700,400,*,UP,ALU1 +V 8800,5700,CONT_DIF_P,n1 +V 8800,1600,CONT_DIF_N,n1 +V 6800,2600,CONT_POLY,* +V 6100,5100,CONT_DIF_P,n3 +V 6100,1600,CONT_DIF_N,n3 +V 2200,2300,CONT_DIF_N,zn +V 500,4800,CONT_DIF_P,* +V 500,4100,CONT_DIF_P,* +V 500,2100,CONT_DIF_N,* +V 1500,6300,CONT_DIF_P,* +V 1500,1300,CONT_DIF_N,* +V 12500,5600,CONT_DIF_P,* +V 7100,1600,CONT_DIF_N,* +V 10500,1600,CONT_DIF_N,* +V 13500,5200,CONT_DIF_P,cn +V 5400,2500,CONT_POLY,ci +V 4800,4100,CONT_POLY,ci +V 8500,2500,CONT_POLY,ci +V 7400,4100,CONT_POLY,n2 +V 5100,1600,CONT_DIF_N,n4 +V 3100,3200,CONT_POLY,n4 +V 11500,5000,CONT_DIF_P,ci +V 10500,5500,CONT_DIF_P,* +V 12000,6600,CONT_BODY_N,* +V 9100,4100,CONT_POLY,ci +V 3400,1600,CONT_DIF_N,* +V 1500,4900,CONT_DIF_P,* +V 2500,4100,CONT_DIF_P,zn +V 3300,5100,CONT_DIF_P,* +V 1200,3100,CONT_POLY,zn +V 5100,5100,CONT_DIF_P,n4 +V 11800,3200,CONT_POLY,cn +V 11500,2300,CONT_DIF_N,ci +V 12500,2300,CONT_DIF_N,* +V 13500,2300,CONT_DIF_N,cn +V 12500,4200,CONT_POLY,* +V 10200,3200,CONT_POLY,* +V 13200,600,CONT_BODY_P,* +V 12100,600,CONT_BODY_P,* +V 7100,5700,CONT_DIF_P,* +V 2900,6600,CONT_BODY_N,* +V 3900,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/dfnt1v0x2.vbe b/pdks/symbolic/vsclib/cells/dfnt1v0x2.vbe new file mode 100755 index 000000000..ef016ef75 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/dfnt1v0x2.vbe @@ -0,0 +1,39 @@ +ENTITY dfnt1v0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 10368; + CONSTANT cin_cp : NATURAL := 3; + CONSTANT cin_d : NATURAL := 3; + CONSTANT rdown_cp_z : NATURAL := 1670; + CONSTANT rup_cp_z : NATURAL := 2130; + CONSTANT taf_cp_z : NATURAL := 222; + CONSTANT tar_cp_z : NATURAL := 193; + CONSTANT thf_d_cp : NATURAL := 36; + CONSTANT thr_d_cp : NATURAL := 204; + CONSTANT tsf_d_cp : NATURAL := 343; + CONSTANT tsr_d_cp : NATURAL := 227; + CONSTANT transistors : NATURAL := 24 +); +PORT ( + cp : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END dfnt1v0x2; + +ARCHITECTURE VBE OF dfnt1v0x2 IS + SIGNAL df_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on dfnt1v0x2" + SEVERITY WARNING; + + label0 : BLOCK (cp and not cp'STABLE) + BEGIN + df_m <= GUARDED d; + END BLOCK label0; + + z <= df_m after 255 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/dly1v0x05.ap b/pdks/symbolic/vsclib/cells/dly1v0x05.ap new file mode 100755 index 000000000..b79e8e59d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/dly1v0x05.ap @@ -0,0 +1,96 @@ +V ALLIANCE : 6 +H dly1v0x05,P, 5/ 7/2024,100 +A 0,0,6400,7200 +R 4400,4800,ref_ref,a_48 +R 4400,4000,ref_ref,a_40 +R 400,5600,ref_ref,z_56 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 3600,4800,ref_ref,a_48 +R 1200,4000,ref_ref,z_40 +S 3000,1500,3000,2700,800,*,UP,TALU7 +S 3000,4800,3000,6100,800,*,UP,TALU8 +S 3500,5200,3500,5600,600,*,DOWN,PDIF +S 5000,5200,5000,5800,200,t01,UP,PTRANS +S 4000,5200,4000,5800,200,t03,UP,PTRANS +S 5500,5600,5500,5700,600,*,DOWN,ALU1 +S 5600,3000,5600,5700,400,*,UP,ALU1 +S 600,6600,1400,6600,600,*,RIGHT,NTIE +S 5500,1500,5500,3200,600,*,UP,ALU1 +S 500,4100,500,4900,600,*,UP,PDIF +S 500,4000,500,5700,600,*,UP,ALU1 +S 500,1500,500,2200,600,*,UP,ALU1 +S 5000,6000,5000,6400,200,*,UP,POLY +S 5000,2400,5000,5400,200,*,UP,POLY +S 5000,1800,5000,2400,200,t02,UP,NTRANS +S 5000,1400,5000,1800,200,*,UP,POLY +S 4500,5600,4500,6800,600,*,UP,ALU1 +S 4500,400,4500,2200,600,*,UP,ALU1 +S 4400,4000,4400,4800,600,*,UP,ALU1 +S 4400,4000,4400,4800,400,a,UP,CALU1 +S 4200,3100,5600,3100,600,*,RIGHT,ALU1 +S 4200,2800,4200,3900,600,*,UP,POLY +S 400,4000,1600,4000,400,*,RIGHT,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 400,1500,400,5700,400,*,UP,ALU1 +S 4000,6000,4000,6900,200,*,UP,POLY +S 4000,300,4000,1800,200,*,UP,POLY +S 4000,2400,4000,5400,200,*,UP,POLY +S 4000,1800,4000,2400,200,t04,UP,NTRANS +S 3600,4800,3600,4800,400,a,LEFT,CALU1 +S 3500,4700,4800,4700,600,*,RIGHT,ALU1 +S 3500,1500,3500,2200,600,*,UP,ALU1 +S 3400,1500,3400,3800,400,*,UP,ALU1 +S 3200,3100,3400,3100,600,*,RIGHT,ALU1 +S 2600,600,3400,600,600,*,RIGHT,PTIE +S 2500,4100,2500,4900,600,*,UP,PDIF +S 2500,4000,2500,4900,600,*,UP,ALU1 +S 2500,1500,2500,2200,600,*,UP,ALU1 +S 2400,5700,3600,5700,400,*,RIGHT,ALU1 +S 2400,1500,2400,4900,400,*,UP,ALU1 +S 2000,5700,2500,5700,600,*,RIGHT,POLY +S 2000,5100,2000,6900,200,*,UP,POLY +S 2000,3900,2000,5100,200,t05,UP,PTRANS +S 2000,3100,3200,3100,600,*,RIGHT,POLY +S 2000,300,2000,1800,200,*,UP,POLY +S 2000,2400,2000,3900,200,*,UP,POLY +S 2000,1800,2000,2400,200,t06,UP,NTRANS +S 1500,4800,1500,6800,600,*,UP,ALU1 +S 1500,400,1500,2200,600,*,UP,ALU1 +S 1200,4000,1200,4000,400,z,LEFT,CALU1 +S 1200,3100,2400,3100,600,*,RIGHT,ALU1 +S 1000,5100,1000,6000,200,*,UP,POLY +S 1000,3900,1000,5100,200,t07,UP,PTRANS +S 1000,300,1000,1800,200,*,UP,POLY +S 1000,2400,1000,3900,200,*,UP,POLY +S 1000,1800,1000,2400,200,t08,UP,NTRANS +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,400,6400,400,800,*,RIGHT,ALU1 +V 4500,5500,CONT_DIF_P,* +V 5500,5500,CONT_DIF_P,n1 +V 3500,5500,CONT_DIF_P,n2 +V 600,6600,CONT_BODY_N,* +V 5500,2100,CONT_DIF_N,n1 +V 500,4800,CONT_DIF_P,* +V 500,2100,CONT_DIF_N,* +V 4800,4700,CONT_POLY,* +V 4500,2100,CONT_DIF_N,* +V 4200,3100,CONT_POLY,n1 +V 3500,2100,CONT_DIF_N,n2 +V 3400,600,CONT_BODY_P,* +V 3200,3100,CONT_POLY,n2 +V 2600,600,CONT_BODY_P,* +V 2500,5700,CONT_POLY,n2 +V 2500,4800,CONT_DIF_P,n3 +V 2500,2100,CONT_DIF_N,n3 +V 1500,4800,CONT_DIF_P,* +V 1500,2100,CONT_DIF_N,* +V 1400,6600,CONT_BODY_N,* +V 1200,3100,CONT_POLY,n3 +EOF diff --git a/pdks/symbolic/vsclib/cells/dly1v0x05.vbe b/pdks/symbolic/vsclib/cells/dly1v0x05.vbe new file mode 100755 index 000000000..dd1d41fd0 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/dly1v0x05.vbe @@ -0,0 +1,26 @@ +ENTITY dly1v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3830; + CONSTANT rup_a_z : NATURAL := 4950; + CONSTANT tpll_a_z : NATURAL := 166; + CONSTANT tphh_a_z : NATURAL := 158; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END dly1v0x05; + +ARCHITECTURE behaviour_data_flow OF dly1v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on dly1v0x05" + SEVERITY WARNING; + z <= a after 272 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/dly2v0x05.ap b/pdks/symbolic/vsclib/cells/dly2v0x05.ap new file mode 100755 index 000000000..a8b814dcc --- /dev/null +++ b/pdks/symbolic/vsclib/cells/dly2v0x05.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H dly2v0x05,P,23/ 6/2024,100 +A 0,0,6400,7200 +R 1200,3200,ref_ref,z_32 +R 2800,3200,ref_ref,a_32 +R 3600,3200,ref_ref,a_32 +R 3600,4000,ref_ref,a_40 +R 3600,4800,ref_ref,a_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +S 4100,800,5500,800,200,*,RIGHT,ALU1 +S 3700,4700,3700,5200,200,*,DOWN,POLY +S 0,400,6400,400,800,*,RIGHT,ALU1 +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 1000,1800,1000,2400,200,t09,UP,NTRANS +S 1000,2800,1700,2800,200,*,RIGHT,POLY +S 1000,300,1000,1800,200,*,UP,POLY +S 1000,4200,1500,4200,200,*,RIGHT,POLY +S 1000,4600,1000,5300,200,t07,UP,PTRANS +S 1000,5300,1000,6000,200,*,UP,POLY +S 1200,3200,1200,3200,400,z,LEFT,CALU1 +S 1300,2000,1300,2200,400,n5,UP,NDIF +S 1400,4000,2600,4000,400,*,RIGHT,ALU1 +S 1500,2800,1500,4200,600,*,UP,POLY +S 1500,4800,1500,5100,600,*,UP,PDIF +S 1500,4800,1500,6800,600,*,UP,ALU1 +S 1700,1800,1700,2400,200,t08,UP,NTRANS +S 1700,300,1700,1800,200,*,UP,POLY +S 2200,400,2200,2200,600,*,UP,ALU1 +S 2300,3900,3600,3900,400,*,RIGHT,POLY +S 2400,3800,2400,6800,400,*,UP,POLY +S 2400,5700,5400,5700,400,*,RIGHT,ALU1 +S 2500,3100,3700,3100,600,*,RIGHT,ALU1 +S 2500,4000,2500,5700,600,*,UP,ALU1 +S 2700,1400,2700,1800,200,*,UP,POLY +S 2700,1800,2700,2400,200,t02,UP,NTRANS +S 2800,3200,2800,3200,400,a,LEFT,CALU1 +S 3000,2000,3000,2200,400,n2,UP,NDIF +S 3100,5600,3100,6700,600,*,UP,PDIF +S 3400,1400,3400,1800,200,*,UP,POLY +S 3400,1800,3400,2400,200,t06,UP,NTRANS +S 3400,2900,4800,2900,400,*,RIGHT,POLY +S 3500,2800,3500,4000,400,*,UP,POLY +S 3600,3000,3600,4900,600,*,UP,ALU1 +S 3600,3200,3600,4800,400,a,UP,CALU1 +S 3600,3200,3600,4900,600,*,UP,ALU1 +S 3700,2000,3700,2200,400,n3,UP,NDIF +S 3700,5400,3700,6200,200,t01,UP,PTRANS +S 3700,6200,3700,6600,200,*,UP,POLY +S 4000,5600,4000,6000,400,n1,UP,PDIF +S 400,1600,400,5600,400,z,UP,CALU1 +S 400,3100,1700,3100,600,*,RIGHT,ALU1 +S 4100,1400,4100,1800,200,*,UP,POLY +S 4100,1800,4100,2400,200,t05,UP,NTRANS +S 4400,2000,4400,2200,400,n4,UP,NDIF +S 4400,5400,4400,6200,200,t03,UP,PTRANS +S 4400,600,5200,600,600,*,RIGHT,PTIE +S 4400,6200,4400,6600,200,*,UP,POLY +S 4500,400,4500,4900,400,*,UP,ALU1 +S 4800,1400,4800,1800,200,*,UP,POLY +S 4800,1800,4800,2400,200,t04,UP,NTRANS +S 500,1500,500,5700,600,*,UP,ALU1 +S 500,4800,500,5100,600,*,UP,PDIF +S 5200,5600,5200,6000,800,*,UP,PDIF +S 5300,1500,5300,5700,600,*,UP,ALU1 +S 600,6600,1400,6600,600,*,RIGHT,NTIE +V 1400,6600,CONT_BODY_N,* +V 1500,4000,CONT_POLY,an +V 1500,4900,CONT_DIF_P,* +V 2200,2100,CONT_DIF_N,* +V 2300,6600,CONT_POLY,* +V 2600,3000,CONT_POLY,* +V 3100,6600,CONT_DIF_P,* +V 3500,4800,CONT_POLY,* +V 4400,600,CONT_BODY_P,* +V 4500,4800,CONT_POLY,* +V 500,2100,CONT_DIF_N,* +V 500,4900,CONT_DIF_P,* +V 5200,600,CONT_BODY_P,* +V 5300,2100,CONT_DIF_N,an +V 5300,5700,CONT_DIF_P,an +V 600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/dly2v0x05.vbe b/pdks/symbolic/vsclib/cells/dly2v0x05.vbe new file mode 100755 index 000000000..481cd7dbe --- /dev/null +++ b/pdks/symbolic/vsclib/cells/dly2v0x05.vbe @@ -0,0 +1,26 @@ +ENTITY dly2v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 7080; + CONSTANT rup_a_z : NATURAL := 8860; + CONSTANT tpll_a_z : NATURAL := 216; + CONSTANT tphh_a_z : NATURAL := 170; + CONSTANT transistors : NATURAL := 9 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END dly2v0x05; + +ARCHITECTURE behaviour_data_flow OF dly2v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on dly2v0x05" + SEVERITY WARNING; + z <= a after 392 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/iv1v0x05.ap b/pdks/symbolic/vsclib/cells/iv1v0x05.ap new file mode 100755 index 000000000..c1d20a32d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/iv1v0x05.ap @@ -0,0 +1,45 @@ +V ALLIANCE : 6 +H iv1v0x05,P, 5/ 7/2024,100 +A 0,0,2400,7200 +R 1200,3200,ref_ref,z_32 +R 1200,4000,ref_ref,z_40 +R 1200,5600,ref_ref,a_56 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4800,ref_ref,a_48 +R 400,5600,ref_ref,a_56 +S 1300,6600,1900,6600,600,*,RIGHT,NTIE +S 1000,5200,1000,5700,200,*,UP,POLY +S 0,400,2400,400,800,*,RIGHT,ALU1 +S 0,400,2400,400,800,vss,RIGHT,CALU1 +S 0,5400,2400,5400,4400,*,RIGHT,NWELL +S 0,6800,2400,6800,800,*,RIGHT,ALU1 +S 0,6800,2400,6800,800,vdd,RIGHT,CALU1 +S 1000,1600,1000,2000,200,*,UP,POLY +S 1000,2000,1000,2600,200,t02,UP,NTRANS +S 1000,2500,1000,3800,200,*,UP,POLY +S 1000,3800,1000,5000,200,t01,UP,PTRANS +S 1000,500,1000,1000,1400,*,UP,PTIE +S 1200,3100,1200,4100,400,*,UP,ALU1 +S 1200,3200,1200,4000,400,z,UP,CALU1 +S 1200,4100,1600,4100,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,a,LEFT,CALU1 +S 1500,400,1500,2300,600,*,UP,ALU1 +S 400,2400,400,3200,400,z,UP,CALU1 +S 400,3200,1200,3200,600,*,RIGHT,ALU1 +S 400,4000,400,6700,400,*,UP,PDIF +S 400,4700,400,5700,400,*,UP,ALU1 +S 400,4800,400,5600,400,a,UP,CALU1 +S 400,5600,1200,5600,600,*,RIGHT,ALU1 +S 500,2300,500,3300,600,*,UP,ALU1 +S 500,4000,500,6700,400,*,UP,PDIF +S 500,6300,500,6700,600,*,UP,PDIF +V 1500,6600,CONT_BODY_N,* +V 1200,5600,CONT_POLY,* +V 1400,600,CONT_BODY_P,* +V 1500,2300,CONT_DIF_N,* +V 1500,4100,CONT_DIF_P,* +V 500,2300,CONT_DIF_N,* +V 500,6600,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/iv1v0x05.vbe b/pdks/symbolic/vsclib/cells/iv1v0x05.vbe new file mode 100755 index 000000000..f950a4ea6 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/iv1v0x05.vbe @@ -0,0 +1,26 @@ +ENTITY iv1v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 1728; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3840; + CONSTANT rup_a_z : NATURAL := 4930; + CONSTANT tphl_a_z : NATURAL := 34; + CONSTANT tplh_a_z : NATURAL := 39; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END iv1v0x05; + +ARCHITECTURE behaviour_data_flow OF iv1v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on iv1v0x05" + SEVERITY WARNING; + z <= not (a) after 146 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/iv1v1x05.ap b/pdks/symbolic/vsclib/cells/iv1v1x05.ap new file mode 100755 index 000000000..c3ecbe38d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/iv1v1x05.ap @@ -0,0 +1,46 @@ +V ALLIANCE : 6 +H iv1v1x05,P, 5/ 7/2024,100 +A 0,0,2400,7200 +R 1200,3200,ref_ref,z_32 +R 1200,4000,ref_ref,z_40 +R 1200,5600,ref_ref,a_56 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4800,ref_ref,a_48 +R 400,5600,ref_ref,a_56 +S 1400,6600,1900,6600,800,*,RIGHT,NTIE +S 1000,5200,1000,5700,200,*,UP,POLY +S 0,400,2400,400,800,*,RIGHT,ALU1 +S 0,400,2400,400,800,vss,RIGHT,CALU1 +S 0,5400,2400,5400,4400,*,RIGHT,NWELL +S 0,6800,2400,6800,800,*,RIGHT,ALU1 +S 0,6800,2400,6800,800,vdd,RIGHT,CALU1 +S 1000,1400,1000,1800,200,*,UP,POLY +S 1000,1800,1000,2600,200,t02,UP,NTRANS +S 1000,2600,1000,3800,200,*,UP,POLY +S 1000,3800,1000,5000,200,t01,UP,PTRANS +S 1200,3100,1200,4100,400,*,UP,ALU1 +S 1200,3200,1200,4000,400,z,UP,CALU1 +S 1200,4100,1600,4100,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,a,LEFT,CALU1 +S 1500,2000,1500,2400,600,*,UP,NDIF +S 1500,400,1500,2200,400,*,UP,ALU1 +S 400,2400,400,3200,400,z,UP,CALU1 +S 400,3200,1200,3200,600,*,RIGHT,ALU1 +S 400,4000,400,6700,400,*,UP,PDIF +S 400,4700,400,5700,400,*,UP,ALU1 +S 400,4800,400,5600,400,a,UP,CALU1 +S 400,5600,1200,5600,600,*,RIGHT,ALU1 +S 500,2300,500,3300,600,*,UP,ALU1 +S 500,4000,500,6700,400,*,UP,PDIF +S 500,6300,500,6700,600,*,UP,PDIF +S 600,600,1400,600,600,*,RIGHT,PTIE +V 1200,5600,CONT_POLY,* +V 1400,600,CONT_BODY_P,* +V 1500,2100,CONT_DIF_N,* +V 1500,4100,CONT_DIF_P,* +V 1500,6600,CONT_BODY_N,* +V 500,2300,CONT_DIF_N,* +V 500,6600,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/iv1v1x05.vbe b/pdks/symbolic/vsclib/cells/iv1v1x05.vbe new file mode 100755 index 000000000..841c6147a --- /dev/null +++ b/pdks/symbolic/vsclib/cells/iv1v1x05.vbe @@ -0,0 +1,26 @@ +ENTITY iv1v1x05 IS +GENERIC ( + CONSTANT area : NATURAL := 1728; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 2920; + CONSTANT rup_a_z : NATURAL := 4930; + CONSTANT tphl_a_z : NATURAL := 30; + CONSTANT tplh_a_z : NATURAL := 40; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END iv1v1x05; + +ARCHITECTURE behaviour_data_flow OF iv1v1x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on iv1v1x05" + SEVERITY WARNING; + z <= not (a) after 133 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/lant1v0x05.ap b/pdks/symbolic/vsclib/cells/lant1v0x05.ap new file mode 100755 index 000000000..66075df47 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/lant1v0x05.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H lant1v0x05,P, 5/ 7/2024,100 +A 0,0,8000,7200 +R 1200,2400,ref_ref,z_24 +R 5200,2400,ref_ref,d_24 +R 6000,4000,ref_ref,d_40 +R 400,1600,ref_ref,z_16 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 6000,1600,ref_ref,e_16 +R 6800,2400,ref_ref,e_24 +R 6000,3200,ref_ref,d_32 +S 6900,300,6900,2500,800,*,UP,TALU7 +S 2400,1200,2400,2100,1000,*,UP,TALU7 +S 2800,4400,2800,6100,800,*,UP,TALU8 +S 3300,5500,3300,5800,600,*,DOWN,PDIF +S 3800,5300,3800,5900,200,t09,UP,PTRANS +S 4300,5300,4300,5900,200,t11,UP,PTRANS +S 1700,2300,1700,2500,600,*,DOWN,NDIF +S 1600,1300,1600,1500,600,*,UP,NDIF +S 1100,1100,1100,1700,200,t14,UP,NTRANS +S 3100,1700,3100,2500,600,*,DOWN,NDIF +S 2500,2100,2500,2700,200,t08,UP,NTRANS +S 3600,2400,3800,2400,200,*,RIGHT,POLY +S 3800,2600,3800,5000,200,*,UP,POLY +S 3300,5600,3300,6800,400,*,UP,ALU1 +S 3800,6000,3800,6400,200,*,UP,POLY +S 5300,4200,5300,4500,200,*,DOWN,POLY +S 7000,2800,7000,4800,200,*,DOWN,POLY +S 6500,500,6500,2200,600,*,UP,NDIF +S 1100,600,1100,1000,200,*,DOWN,POLY +S 1600,400,1600,1400,400,*,DOWN,ALU1 +S 400,2300,400,4200,400,*,DOWN,ALU1 +S 500,4000,500,4200,400,*,DOWN,ALU1 +S 400,1600,400,4000,400,z,UP,CALU1 +S 1000,5000,1000,5400,200,*,UP,POLY +S 1000,3800,1000,5000,200,t13,UP,PTRANS +S 2500,1600,2500,2000,200,*,DOWN,POLY +S 500,1500,500,2500,600,*,UP,ALU1 +S 1200,2400,1200,2400,400,z,LEFT,CALU1 +S 400,2400,1200,2400,600,*,RIGHT,ALU1 +S 6000,1000,6000,1400,200,*,DOWN,POLY +S 6000,2000,6000,4800,200,*,DOWN,POLY +S 5300,2000,5300,3400,200,*,UP,POLY +S 5300,1000,5300,1400,200,*,DOWN,POLY +S 6000,1400,6000,2000,200,t04,UP,NTRANS +S 5300,1400,5300,2000,200,t06,UP,NTRANS +S 3600,1000,3600,1400,200,*,DOWN,POLY +S 4300,1000,4300,1400,200,*,DOWN,POLY +S 3700,1700,3700,4000,400,*,UP,ALU1 +S 3000,1600,3000,2400,400,*,DOWN,NDIF +S 3600,1400,3600,2000,200,t10,UP,NTRANS +S 4300,1400,4300,2000,200,t12,UP,NTRANS +S 3700,1700,4900,1700,400,*,LEFT,ALU1 +S 4400,2500,4400,3200,400,*,UP,ALU1 +S 4300,3400,4300,5400,200,*,DOWN,POLY +S 4300,3400,5300,3400,200,*,RIGHT,POLY +S 5300,4800,5300,6000,200,t05,UP,PTRANS +S 6000,4800,6000,6000,200,t03,UP,PTRANS +S 2500,4000,2500,4800,400,*,UP,ALU1 +S 2500,4800,3500,4800,400,*,LEFT,ALU1 +S 2000,4000,2500,4000,400,*,RIGHT,ALU1 +S 6000,4000,6100,4000,600,*,LEFT,ALU1 +S 6000,2400,6000,4100,400,*,DOWN,ALU1 +S 5200,2400,5200,2400,400,d,LEFT,CALU1 +S 4300,6000,4300,6900,200,*,DOWN,POLY +S 4300,6900,7000,6900,200,*,LEFT,POLY +S 7000,6000,7000,6900,200,*,UP,POLY +S 7500,4800,7500,5200,400,*,DOWN,ALU1 +S 6500,5600,6500,6800,400,*,UP,ALU1 +S 7000,4800,7000,6000,200,t01,UP,PTRANS +S 1000,3400,2500,3400,200,*,RIGHT,POLY +S 4400,3200,5100,3200,400,*,RIGHT,ALU1 +S 5100,2400,6000,2400,400,*,RIGHT,ALU1 +S 5100,3200,5100,4800,400,*,UP,ALU1 +S 4300,4000,4300,5700,400,*,UP,ALU1 +S 3700,4000,4300,4000,400,*,LEFT,ALU1 +S 4300,6000,4300,6400,200,*,UP,POLY +S 2000,5000,2000,5400,200,*,UP,POLY +S 7000,1400,7000,1800,200,*,DOWN,POLY +S 6000,3200,6000,4000,400,d,UP,CALU1 +S 4300,5700,4900,5700,400,*,RIGHT,ALU1 +S 6600,500,6600,900,600,*,UP,NDIF +S 2700,3200,3700,3200,400,*,RIGHT,ALU1 +S 600,6600,1400,6600,600,*,RIGHT,NTIE +S 2500,2600,2500,3400,200,*,UP,POLY +S 2000,3800,2000,5000,200,t07,UP,PTRANS +S 7000,1800,7000,2400,200,t02,UP,NTRANS +S 0,5400,8000,5400,4400,*,RIGHT,NWELL +S 6000,1600,6000,1600,400,e,LEFT,CALU1 +S 6800,2400,6800,2400,400,e,LEFT,CALU1 +S 5900,1600,6800,1600,400,*,RIGHT,ALU1 +S 6800,1600,6800,3100,400,*,UP,ALU1 +S 7500,2000,7500,2200,400,*,UP,ALU1 +S 7600,2000,7600,4800,400,*,DOWN,ALU1 +S 5100,4800,7600,4800,400,*,RIGHT,ALU1 +S 3000,400,3000,2400,400,*,DOWN,ALU1 +S 2000,2200,2000,4000,400,*,UP,ALU1 +S 1500,4700,1500,6800,600,*,UP,ALU1 +S 1100,1600,1100,3400,200,*,UP,POLY +S 0,6800,8000,6800,800,*,RIGHT,ALU1 +S 0,6800,8000,6800,800,vdd,RIGHT,CALU1 +S 0,400,8000,400,800,vss,RIGHT,CALU1 +S 0,400,8000,400,800,*,RIGHT,ALU1 +S 5600,5000,5600,5800,400,dnp,UP,PDIF +S 5600,1600,5600,1800,400,dnn,DOWN,NDIF +S 4000,1600,4000,1800,400,n3n,DOWN,NDIF +V 3300,5600,CONT_DIF_P,* +V 500,1400,CONT_DIF_N,* +V 1600,1400,CONT_DIF_N,* +V 3000,2400,CONT_DIF_N,* +V 2000,2400,CONT_DIF_N,n2 +V 3600,4800,CONT_POLY,n2 +V 6500,600,CONT_DIF_N,* +V 2600,600,CONT_BODY_P,* +V 6100,4000,CONT_POLY,* +V 6500,5700,CONT_DIF_P,* +V 1400,6600,CONT_BODY_N,* +V 600,6600,CONT_BODY_N,* +V 6800,3000,CONT_POLY,* +V 1500,4700,CONT_DIF_P,* +V 500,4100,CONT_DIF_P,* +V 7500,2100,CONT_DIF_N,en +V 7500,5100,CONT_DIF_P,en +V 5100,4200,CONT_POLY,en +V 4400,2600,CONT_POLY,en +V 4800,1700,CONT_DIF_N,n1 +V 2800,3200,CONT_POLY,n1 +V 4800,5700,CONT_DIF_P,n1 +V 2500,4700,CONT_DIF_P,n2 +EOF diff --git a/pdks/symbolic/vsclib/cells/lant1v0x05.vbe b/pdks/symbolic/vsclib/cells/lant1v0x05.vbe new file mode 100755 index 000000000..caea38cd0 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/lant1v0x05.vbe @@ -0,0 +1,43 @@ +ENTITY lant1v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5760; + CONSTANT cin_e : NATURAL := 5; + CONSTANT cin_d : NATURAL := 3; + CONSTANT rdown_e_z : NATURAL := 4260; + CONSTANT rdown_d_z : NATURAL := 4450; + CONSTANT rup_e_z : NATURAL := 5100; + CONSTANT rup_d_z : NATURAL := 5170; + CONSTANT taf_e_z : NATURAL := 185; + CONSTANT taf_d_z : NATURAL := 162; + CONSTANT tar_e_z : NATURAL := 102; + CONSTANT tar_d_z : NATURAL := 117; + CONSTANT thf_d_e : NATURAL := 0; + CONSTANT thr_d_e : NATURAL := 0; + CONSTANT tsf_d_e : NATURAL := 365; + CONSTANT tsr_d_e : NATURAL := 384; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + e : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END lant1v0x05; + +ARCHITECTURE VBE OF lant1v0x05 IS + SIGNAL la_m : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on lant1v0x05" + SEVERITY WARNING; + + label0 : BLOCK (e) + BEGIN + la_m <= GUARDED d; + END BLOCK label0; + + z <= la_m after 260 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/mxi2v0x05.ap b/pdks/symbolic/vsclib/cells/mxi2v0x05.ap new file mode 100755 index 000000000..fb0b1e495 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/mxi2v0x05.ap @@ -0,0 +1,117 @@ +V ALLIANCE : 6 +H mxi2v0x05,P,23/ 6/2024,100 +A 0,0,5600,7200 +R 4400,5600,ref_ref,s_56 +R 400,4800,ref_ref,s_48 +R 400,2400,ref_ref,a0_24 +R 3600,5600,ref_ref,s_56 +R 3600,4000,ref_ref,z_40 +R 3600,3200,ref_ref,z_32 +R 3600,2400,ref_ref,z_24 +R 3600,1600,ref_ref,z_16 +R 2800,5600,ref_ref,s_56 +R 2800,4800,ref_ref,z_48 +R 2800,3200,ref_ref,a1_32 +R 2800,1600,ref_ref,z_16 +R 2000,5600,ref_ref,s_56 +R 2000,2400,ref_ref,a1_24 +R 2000,1600,ref_ref,z_16 +R 1200,4800,ref_ref,s_48 +R 1200,3200,ref_ref,a0_32 +S 4600,5300,4600,5700,200,*,UP,POLY +S 1700,2000,1700,2400,200,*,UP,POLY +S 1500,3200,2700,3200,200,*,RIGHT,POLY +S 3400,3300,4200,3300,600,*,RIGHT,POLY +S 4300,3300,5100,3300,600,*,RIGHT,ALU1 +S 4000,500,4000,1900,600,*,UP,NDIF +S 4600,1500,4600,2100,200,t06,UP,NTRANS +S 4600,2500,5100,2500,200,*,RIGHT,POLY +S 5100,2500,5100,4000,200,*,UP,POLY +S 4600,4100,5100,4100,200,*,RIGHT,POLY +S 4600,4500,4600,5100,200,t05,UP,PTRANS +S 4000,4700,4000,6700,600,*,UP,PDIF +S 5100,1700,5100,4900,400,*,UP,ALU1 +S 4700,5700,4900,5700,400,*,RIGHT,ALU1 +S 700,4200,1000,4200,200,*,RIGHT,POLY +S 1900,1600,3600,1600,400,*,RIGHT,ALU1 +S 700,2200,700,4000,200,*,UP,POLY +S 700,2200,1000,2200,200,*,RIGHT,POLY +S 3400,1100,3400,1800,200,t10,UP,NTRANS +S 3400,4600,3400,6200,200,t09,UP,PTRANS +S 1000,1100,1000,1800,200,t08,UP,NTRANS +S 1000,4600,1000,6200,200,t07,UP,PTRANS +S 1700,1100,1700,1800,200,t04,UP,NTRANS +S 2700,4600,2700,6200,200,t03,UP,PTRANS +S 2700,1100,2700,1800,200,t02,UP,NTRANS +S 1700,4600,1700,6200,200,t01,UP,PTRANS +S 500,5800,500,6800,400,*,UP,ALU1 +S 500,4800,500,6000,600,*,UP,PDIF +S 500,400,500,1500,400,*,UP,ALU1 +S 500,4000,500,4900,600,*,UP,ALU1 +S 500,1300,500,1600,600,*,UP,NDIF +S 4400,5600,4400,5600,400,s,LEFT,CALU1 +S 400,4900,1300,4900,400,*,RIGHT,ALU1 +S 400,4800,400,4800,400,s,LEFT,CALU1 +S 400,4800,1300,4800,400,*,RIGHT,ALU1 +S 400,3200,1600,3200,400,*,RIGHT,ALU1 +S 400,2400,400,2400,400,a0,LEFT,CALU1 +S 400,2300,400,3200,400,*,UP,ALU1 +S 3900,4800,3900,6700,400,*,UP,PDIF +S 3600,5600,3600,5600,400,s,LEFT,CALU1 +S 3600,1600,3600,4000,400,z,UP,CALU1 +S 3600,1500,3600,4800,400,*,UP,ALU1 +S 3400,700,3400,1100,200,*,UP,POLY +S 3400,6200,3400,6600,200,*,UP,POLY +S 3400,1800,3400,4600,200,*,UP,POLY +S 3100,4800,3100,6000,400,n4,UP,PDIF +S 3100,1300,3100,1600,400,n2,UP,NDIF +S 2800,5600,2800,5600,400,s,LEFT,CALU1 +S 2800,4800,2800,4800,400,z,LEFT,CALU1 +S 2800,3200,2800,3200,400,a1,LEFT,CALU1 +S 2800,2400,2800,4000,400,*,UP,ALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2700,700,2700,1100,200,*,UP,POLY +S 2700,6200,2700,6600,200,*,UP,POLY +S 2700,1800,2700,3200,200,*,UP,POLY +S 2500,4000,2800,4000,400,*,RIGHT,ALU1 +S 2200,4800,2200,4900,600,*,UP,ALU1 +S 2100,4800,3600,4800,400,*,RIGHT,ALU1 +S 2000,5600,2000,5600,400,s,LEFT,CALU1 +S 2000,2400,2000,2400,400,a1,LEFT,CALU1 +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 1900,1500,3600,1500,400,*,RIGHT,ALU1 +S 1800,2400,2800,2400,400,*,RIGHT,ALU1 +S 1700,700,1700,1100,200,*,UP,POLY +S 1700,6200,1700,6600,200,*,UP,POLY +S 1700,3400,1700,4600,200,*,UP,POLY +S 1500,3200,1500,3400,600,*,UP,ALU1 +S 1300,5600,4900,5600,400,*,RIGHT,ALU1 +S 1300,4800,1300,6000,400,n3,UP,PDIF +S 1300,4800,1300,5600,400,*,UP,ALU1 +S 1300,1300,1300,1600,400,n1,UP,NDIF +S 1200,4800,1200,4800,400,s,LEFT,CALU1 +S 1200,3200,1200,3200,400,a0,LEFT,CALU1 +S 1000,700,1000,1100,200,*,UP,POLY +S 1000,6200,1000,6600,200,*,UP,POLY +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,400,5600,400,800,*,RIGHT,ALU1 +V 5000,600,CONT_BODY_P,* +V 4300,3300,CONT_POLY,sn +V 5100,1800,CONT_DIF_N,sn +V 5100,4800,CONT_DIF_P,sn +V 4800,5700,CONT_POLY,* +V 500,5900,CONT_DIF_P,* +V 500,4000,CONT_POLY,* +V 500,1400,CONT_DIF_N,* +V 5000,6600,CONT_BODY_N,* +V 4000,6600,CONT_DIF_P,* +V 4000,600,CONT_DIF_N,* +V 2600,4000,CONT_POLY,* +V 2200,4900,CONT_DIF_P,* +V 2200,1500,CONT_DIF_N,* +V 1900,2400,CONT_POLY,* +V 1500,3400,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/mxi2v0x05.vbe b/pdks/symbolic/vsclib/cells/mxi2v0x05.vbe new file mode 100755 index 000000000..3c5bf4da8 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/mxi2v0x05.vbe @@ -0,0 +1,40 @@ +ENTITY mxi2v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_s : NATURAL := 6; + CONSTANT cin_a0 : NATURAL := 3; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT rdown_s_z : NATURAL := 5310; + CONSTANT rdown_a0_z : NATURAL := 5310; + CONSTANT rdown_a1_z : NATURAL := 5320; + CONSTANT rup_s_z : NATURAL := 7260; + CONSTANT rup_a0_z : NATURAL := 7330; + CONSTANT rup_a1_z : NATURAL := 7360; + CONSTANT tphl_a0_z : NATURAL := 56; + CONSTANT tphl_a1_z : NATURAL := 59; + CONSTANT tphl_s_z : NATURAL := 57; + CONSTANT tplh_a0_z : NATURAL := 62; + CONSTANT tplh_a1_z : NATURAL := 65; + CONSTANT tplh_s_z : NATURAL := 73; + CONSTANT tphh_s_z : NATURAL := 99; + CONSTANT tpll_s_z : NATURAL := 132; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + s : in BIT; + a0 : in BIT; + a1 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END mxi2v0x05; + +ARCHITECTURE behaviour_data_flow OF mxi2v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mxi2v0x05" + SEVERITY WARNING; + z <= (not a0 and not s) or (not a1 and s) after 233 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/mxi2v0x2.ap b/pdks/symbolic/vsclib/cells/mxi2v0x2.ap new file mode 100755 index 000000000..9d7513545 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/mxi2v0x2.ap @@ -0,0 +1,164 @@ +V ALLIANCE : 6 +H mxi2v0x2,P, 5/ 7/2024,100 +A 0,0,9600,7200 +R 4400,2400,ref_ref,a1_24 +R 3600,3200,ref_ref,s_32 +R 5200,4000,ref_ref,s_40 +R 4400,4000,ref_ref,s_40 +R 3600,4000,ref_ref,s_40 +R 1200,5600,ref_ref,a0_56 +R 400,3200,ref_ref,a0_32 +R 400,4800,ref_ref,a0_48 +R 400,4000,ref_ref,a0_40 +R 6800,2400,ref_ref,a1_24 +R 1200,2400,ref_ref,z_24 +R 1200,3200,ref_ref,z_32 +R 1200,4000,ref_ref,z_40 +R 6000,5600,ref_ref,z_56 +R 5200,5600,ref_ref,z_56 +R 4400,5600,ref_ref,z_56 +R 3600,5600,ref_ref,z_56 +R 2800,5600,ref_ref,z_56 +R 7600,3200,ref_ref,a1_32 +R 2800,1600,ref_ref,z_16 +R 2000,1600,ref_ref,z_16 +S 4400,2200,6900,2200,400,*,RIGHT,ALU1 +S 6800,2200,6800,2700,600,*,UP,ALU1 +S 4400,2200,4400,3000,400,*,DOWN,ALU1 +S 2100,5600,6300,5600,400,*,LEFT,ALU1 +S 4400,4300,4400,6400,400,*,DOWN,PDIF +S 7800,1400,7800,2100,600,*,DOWN,NDIF +S 8000,4000,8000,6400,600,*,DOWN,PDIF +S 7000,4300,7000,6400,400,n4b,UP,PDIF +S 5300,4300,5300,6400,400,n4a,UP,PDIF +S 4800,3700,5000,3700,200,*,LEFT,POLY +S 4800,2300,4800,3700,200,*,DOWN,POLY +S 4400,6300,4400,6800,600,*,UP,ALU1 +S 5700,3700,6700,3700,200,*,LEFT,POLY +S 7200,2700,7400,2700,200,*,RIGHT,POLY +S 6900,1400,6900,2100,400,n1a,UP,NDIF +S 3400,4300,3400,6400,400,n3b,UP,PDIF +S 1700,4300,1700,6400,400,n3a,UP,PDIF +S 800,4300,800,6400,600,*,DOWN,PDIF +S 900,6300,900,6800,600,*,UP,ALU1 +S 1200,3700,1400,3700,200,*,LEFT,POLY +S 1200,2300,1200,3700,200,*,UP,POLY +S 2100,3700,3100,3700,200,*,RIGHT,POLY +S 3200,1400,3200,2100,400,n2b,UP,NDIF +S 1500,1400,1500,2100,400,n2a,UP,NDIF +S 1200,300,3600,300,200,*,RIGHT,POLY +S 1200,300,1200,1200,200,*,DOWN,POLY +S 1900,2700,2900,2700,200,*,RIGHT,POLY +S 5200,1400,5200,2100,400,n1b,UP,NDIF +S 7400,2700,7400,4100,200,*,UP,POLY +S 8800,2300,9200,2300,400,*,RIGHT,ALU1 +S 2100,4900,2100,5600,400,*,UP,ALU1 +S 6700,2700,7700,2700,400,*,RIGHT,ALU1 +S 5400,2900,5400,4000,400,*,UP,ALU1 +S 3500,4000,5400,4000,400,*,LEFT,ALU1 +S 5400,2900,5700,2900,400,*,LEFT,ALU1 +S 2900,3500,3700,3500,400,*,LEFT,ALU1 +S 1200,2400,1200,4000,400,z,UP,CALU1 +S 1200,1600,1200,4100,400,*,DOWN,ALU1 +S 2900,1500,6200,1500,400,*,LEFT,ALU1 +S 4400,2400,4400,2400,400,a1,LEFT,CALU1 +S 8600,5600,8600,6000,200,*,UP,POLY +S 8400,3000,8600,3000,200,*,RIGHT,POLY +S 8400,3100,8600,3100,200,*,RIGHT,POLY +S 8400,2600,8400,3100,200,*,UP,POLY +S 8600,3000,8600,3800,200,*,DOWN,POLY +S 9100,4100,9100,4800,600,*,UP,PDIF +S 7900,400,7900,2000,600,*,DOWN,ALU1 +S 7600,2700,7600,3200,600,*,DOWN,ALU1 +S 7600,3200,7600,3200,400,a1,LEFT,CALU1 +S 8400,300,8400,1700,200,*,DOWN,POLY +S 300,3500,1200,3500,600,*,RIGHT,POLY +S 3600,3200,3600,4000,400,s,UP,CALU1 +S 3600,3200,3600,4000,600,*,UP,ALU1 +S 500,400,500,1600,400,*,DOWN,ALU1 +S 1300,4100,1300,4900,400,*,UP,ALU1 +S 8000,4300,8000,6400,600,*,DOWN,PDIF +S 500,1400,500,2100,600,*,UP,NDIF +S 400,3100,400,5600,400,*,UP,ALU1 +S 400,3200,400,4800,400,a0,UP,CALU1 +S 400,3500,500,3500,600,*,RIGHT,ALU1 +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 1200,1600,2900,1600,400,*,RIGHT,ALU1 +S 2200,4200,2800,4200,400,*,RIGHT,ALU1 +S 1300,4900,2100,4900,400,*,RIGHT,ALU1 +S 2800,4200,2800,4800,400,*,UP,ALU1 +S 4200,500,4200,2100,600,*,UP,NDIF +S 2800,5600,2800,5600,400,z,LEFT,CALU1 +S 3600,5600,3600,5600,400,z,LEFT,CALU1 +S 4400,5600,4400,5600,400,z,LEFT,CALU1 +S 5200,5600,5200,5600,400,z,LEFT,CALU1 +S 6000,5600,6000,5600,400,z,LEFT,CALU1 +S 4400,4000,4400,4000,400,s,LEFT,CALU1 +S 5200,4000,5200,4000,400,s,LEFT,CALU1 +S 6800,2400,6800,2400,400,a1,LEFT,CALU1 +S 400,5600,1300,5600,400,*,LEFT,ALU1 +S 2200,2900,2200,4200,400,*,UP,ALU1 +S 6600,3400,6600,4800,400,*,UP,ALU1 +S 1900,2900,2200,2900,400,*,RIGHT,ALU1 +S 3600,2700,3800,2700,200,*,LEFT,POLY +S 3800,2700,3800,4100,200,*,UP,POLY +S 3600,300,3600,1200,200,*,UP,POLY +S 1200,5600,1200,5600,400,a0,LEFT,CALU1 +S 0,400,9600,400,800,vss,RIGHT,CALU1 +S 0,400,9600,400,800,*,RIGHT,ALU1 +S 0,6800,9600,6800,800,vdd,RIGHT,CALU1 +S 0,6800,9600,6800,800,*,RIGHT,ALU1 +S 0,5400,9600,5400,4400,*,RIGHT,NWELL +S 2800,4800,6600,4800,400,*,RIGHT,ALU1 +S 6600,4000,9200,4000,400,*,RIGHT,ALU1 +S 9200,2300,9200,4000,400,*,DOWN,ALU1 +S 8000,4800,8000,6800,400,*,UP,ALU1 +S 1400,4100,1400,6600,200,t01,UP,PTRANS +S 3800,4100,3800,6600,200,t02,UP,PTRANS +S 1200,1200,1200,2300,200,t03,UP,NTRANS +S 3600,1200,3600,2300,200,t04,UP,NTRANS +S 5000,4100,5000,6600,200,t05,UP,PTRANS +S 7400,4100,7400,6600,200,t06,UP,PTRANS +S 4800,1200,4800,2300,200,t07,UP,NTRANS +S 7200,1200,7200,2300,200,t08,UP,NTRANS +S 8600,3800,8600,5600,200,t09,UP,PTRANS +S 8400,1700,8400,2600,200,t10,UP,NTRANS +S 3100,4100,3100,6600,200,t12,UP,PTRANS +S 2100,4100,2100,6600,200,t11,UP,PTRANS +S 5500,1200,5500,2300,200,t13,UP,NTRANS +S 6500,1200,6500,2300,200,t14,UP,NTRANS +S 1900,1200,1900,2300,200,t15,UP,NTRANS +S 2900,1200,2900,2300,200,t16,UP,NTRANS +S 5700,4100,5700,6600,200,t17,UP,PTRANS +S 6700,4100,6700,6600,200,t18,UP,PTRANS +S 6500,300,6500,800,200,*,DOWN,POLY +S 6500,300,8400,300,200,*,LEFT,POLY +S 5500,2700,6500,2700,200,*,RIGHT,POLY +S 4800,800,4800,1200,200,*,DOWN,POLY +S 5500,800,5500,1200,200,*,DOWN,POLY +S 9100,4000,9100,4900,400,*,UP,ALU1 +V 4600,2900,CONT_POLY,* +V 4400,6300,CONT_DIF_P,* +V 6200,5600,CONT_DIF_P,* +V 6000,1500,CONT_DIF_N,* +V 900,6300,CONT_DIF_P,* +V 2600,5600,CONT_DIF_P,* +V 2400,1600,CONT_DIF_N,* +V 8900,2300,CONT_DIF_N,sn +V 9100,4800,CONT_DIF_P,sn +V 9100,4100,CONT_DIF_P,sn +V 7900,2000,CONT_DIF_N,* +V 9000,600,CONT_BODY_P,* +V 9000,6600,CONT_BODY_N,* +V 4200,600,CONT_DIF_N,* +V 500,3500,CONT_POLY,* +V 6600,3500,CONT_POLY,sn +V 7600,3200,CONT_POLY,* +V 5600,2900,CONT_POLY,* +V 3000,3500,CONT_POLY,* +V 2000,2900,CONT_POLY,sn +V 500,1500,CONT_DIF_N,* +V 8000,5600,CONT_DIF_P,* +V 8000,4900,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/mxi2v0x2.vbe b/pdks/symbolic/vsclib/cells/mxi2v0x2.vbe new file mode 100755 index 000000000..1be3127ae --- /dev/null +++ b/pdks/symbolic/vsclib/cells/mxi2v0x2.vbe @@ -0,0 +1,40 @@ +ENTITY mxi2v0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 6912; + CONSTANT cin_s : NATURAL := 12; + CONSTANT cin_a0 : NATURAL := 9; + CONSTANT cin_a1 : NATURAL := 9; + CONSTANT rdown_s_z : NATURAL := 1670; + CONSTANT rdown_a0_z : NATURAL := 1700; + CONSTANT rdown_a1_z : NATURAL := 1690; + CONSTANT rup_s_z : NATURAL := 2300; + CONSTANT rup_a0_z : NATURAL := 2340; + CONSTANT rup_a1_z : NATURAL := 2340; + CONSTANT tphl_a0_z : NATURAL := 57; + CONSTANT tphl_a1_z : NATURAL := 54; + CONSTANT tphl_s_z : NATURAL := 40; + CONSTANT tplh_a0_z : NATURAL := 69; + CONSTANT tplh_a1_z : NATURAL := 73; + CONSTANT tplh_s_z : NATURAL := 47; + CONSTANT tphh_s_z : NATURAL := 106; + CONSTANT tpll_s_z : NATURAL := 121; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + s : in BIT; + a0 : in BIT; + a1 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END mxi2v0x2; + +ARCHITECTURE behaviour_data_flow OF mxi2v0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mxi2v0x2" + SEVERITY WARNING; + z <= (not a0 and not s) or (not a1 and s) after 121 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/mxn2v0x05.ap b/pdks/symbolic/vsclib/cells/mxn2v0x05.ap new file mode 100755 index 000000000..bb40dfef1 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/mxn2v0x05.ap @@ -0,0 +1,113 @@ +V ALLIANCE : 6 +H mxn2v0x05,P,23/ 6/2024,100 +A 0,0,6400,7200 +R 2000,3200,ref_ref,a0_32 +R 2800,4000,ref_ref,a0_40 +R 6000,5600,ref_ref,s_56 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,3200,ref_ref,a1_32 +R 4400,2400,ref_ref,a1_24 +R 5200,2400,ref_ref,a1_24 +R 5200,4800,ref_ref,s_48 +R 1200,4800,ref_ref,z_48 +R 2800,3200,ref_ref,a0_32 +S 4900,4000,4900,5600,600,*,UP,PDIF +S 2700,2000,2700,2400,200,*,UP,POLY +S 4000,4800,4000,5600,400,n4,UP,PDIF +S 2300,4800,2300,5600,400,n3,UP,PDIF +S 4000,1400,4000,1600,400,n2,UP,NDIF +S 2300,1400,2300,1600,400,n1,UP,NDIF +S 1000,1200,1000,1800,200,t08,UP,NTRANS +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,400,6400,400,800,*,RIGHT,ALU1 +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 4400,1200,4400,1800,200,t06,UP,NTRANS +S 5400,1200,5400,1800,200,t06,UP,NTRANS +S 3700,1200,3700,1800,200,t10,UP,NTRANS +S 2700,1200,2700,1800,200,t02,UP,NTRANS +S 2000,1200,2000,1800,200,t04,UP,NTRANS +S 4400,4600,4400,5800,200,t09,UP,PTRANS +S 3700,4600,3700,5800,200,t03,UP,PTRANS +S 2700,4600,2700,5800,200,t01,UP,PTRANS +S 2000,4600,2000,5800,200,t07,UP,PTRANS +S 2000,1800,2000,4600,200,*,DOWN,POLY +S 4400,1800,4400,4600,200,*,DOWN,POLY +S 3700,1800,3700,3200,200,*,UP,POLY +S 2700,3200,3700,3200,200,*,LEFT,POLY +S 2700,3200,2700,4600,200,*,UP,POLY +S 2200,1500,2200,2300,400,*,UP,ALU1 +S 1500,400,1500,1600,400,*,DOWN,ALU1 +S 1000,1800,1000,4600,200,*,DOWN,POLY +S 5400,3800,5400,4400,200,t05,UP,PTRANS +S 5400,1800,5400,3800,200,*,DOWN,POLY +S 6000,1500,6000,4100,400,*,DOWN,ALU1 +S 6000,4800,6000,5700,400,*,UP,ALU1 +S 5900,4800,5900,5700,400,*,UP,ALU1 +S 5400,4800,5900,4800,200,*,RIGHT,POLY +S 3700,300,3700,1200,200,*,DOWN,POLY +S 3700,300,5400,300,200,*,RIGHT,POLY +S 5400,300,5400,1200,200,*,UP,POLY +S 3200,4800,3200,4900,600,*,UP,ALU1 +S 400,1500,600,1500,400,*,RIGHT,ALU1 +S 5800,1500,6000,1500,400,*,LEFT,ALU1 +S 4900,400,4900,1500,600,*,DOWN,ALU1 +S 4400,2400,4400,3200,400,a1,UP,CALU1 +S 5200,2400,5200,2400,400,a1,LEFT,CALU1 +S 4400,2400,5200,2400,600,*,LEFT,ALU1 +S 2200,1500,3300,1500,400,*,LEFT,ALU1 +S 4400,5800,4400,6200,200,*,UP,POLY +S 3700,5800,3700,6200,200,*,UP,POLY +S 2700,5800,2700,6200,200,*,UP,POLY +S 1000,800,1000,1200,200,*,DOWN,POLY +S 2000,800,2000,1200,200,*,DOWN,POLY +S 2700,800,2700,1200,200,*,DOWN,POLY +S 5100,4800,6000,4800,400,*,LEFT,ALU1 +S 5200,4800,5200,4800,400,s,LEFT,CALU1 +S 6000,5600,6000,5600,400,s,LEFT,CALU1 +S 4900,5500,4900,6800,600,*,UP,ALU1 +S 4500,2300,4500,3300,600,*,DOWN,ALU1 +S 3600,2300,3600,4100,400,*,UP,ALU1 +S 2900,2400,3600,2400,600,*,RIGHT,ALU1 +S 3600,4100,6000,4100,400,*,RIGHT,ALU1 +S 2000,3200,2000,3200,400,a0,LEFT,CALU1 +S 2800,3200,2800,4000,600,*,DOWN,ALU1 +S 2000,4800,3300,4800,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 400,4800,1300,4800,400,*,RIGHT,ALU1 +S 2000,4100,2000,4800,400,*,UP,ALU1 +S 1000,4600,1000,5800,200,t07,UP,PTRANS +S 400,1500,400,4900,400,*,DOWN,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 500,4800,500,4900,600,*,DOWN,ALU1 +S 1500,5500,1500,6800,600,*,UP,ALU1 +S 2000,5800,2000,6200,200,*,UP,POLY +S 1000,5800,1000,6200,200,*,UP,POLY +S 2800,3200,2800,4000,400,a0,UP,CALU1 +S 1100,2300,1100,4100,400,*,UP,ALU1 +S 1100,4100,2000,4100,400,*,LEFT,ALU1 +S 1100,2300,2200,2300,400,*,LEFT,ALU1 +S 1800,3300,2900,3300,600,*,RIGHT,ALU1 +V 500,1500,CONT_DIF_N,* +V 5900,1500,CONT_DIF_N,sn +V 4900,1500,CONT_DIF_N,* +V 1500,1500,CONT_DIF_N,* +V 2900,2400,CONT_POLY,sn +V 5900,4100,CONT_DIF_P,sn +V 5900,5000,CONT_POLY,* +V 3200,1500,CONT_DIF_N,zn +V 4900,5500,CONT_DIF_P,* +V 4600,3200,CONT_POLY,* +V 3600,4000,CONT_POLY,sn +V 1900,3400,CONT_POLY,* +V 3200,4900,CONT_DIF_P,zn +V 1500,5500,CONT_DIF_P,* +V 500,4900,CONT_DIF_P,* +V 5800,6600,CONT_BODY_N,* +V 1100,2400,CONT_POLY,zn +EOF diff --git a/pdks/symbolic/vsclib/cells/mxn2v0x05.vbe b/pdks/symbolic/vsclib/cells/mxn2v0x05.vbe new file mode 100755 index 000000000..26eeeba74 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/mxn2v0x05.vbe @@ -0,0 +1,40 @@ +ENTITY mxn2v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_s : NATURAL := 5; + CONSTANT cin_a0 : NATURAL := 3; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT rdown_s_z : NATURAL := 4070; + CONSTANT rdown_a0_z : NATURAL := 4080; + CONSTANT rdown_a1_z : NATURAL := 4080; + CONSTANT rup_s_z : NATURAL := 5030; + CONSTANT rup_a0_z : NATURAL := 5030; + CONSTANT rup_a1_z : NATURAL := 5030; + CONSTANT tphh_a0_z : NATURAL := 113; + CONSTANT tphh_a1_z : NATURAL := 108; + CONSTANT tpll_a0_z : NATURAL := 149; + CONSTANT tpll_a1_z : NATURAL := 147; + CONSTANT tphh_s_z : NATURAL := 94; + CONSTANT tphl_s_z : NATURAL := 159; + CONSTANT tpll_s_z : NATURAL := 120; + CONSTANT tplh_s_z : NATURAL := 185; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + s : in BIT; + a0 : in BIT; + a1 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END mxn2v0x05; + +ARCHITECTURE behaviour_data_flow OF mxn2v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on mxn2v0x05" + SEVERITY WARNING; + z <= (a0 and not s) or (a1 and s) after 248 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd2abv0x05.ap b/pdks/symbolic/vsclib/cells/nd2abv0x05.ap new file mode 100755 index 000000000..3b9beed36 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2abv0x05.ap @@ -0,0 +1,98 @@ +V ALLIANCE : 6 +H nd2abv0x05,P, 5/ 7/2024,100 +A 0,0,5600,7200 +R 1200,1600,ref_ref,b_16 +R 1200,2400,ref_ref,b_24 +R 1200,3200,ref_ref,b_32 +R 2000,1600,ref_ref,z_16 +R 2000,3200,ref_ref,b_32 +R 2800,1600,ref_ref,z_16 +R 2800,2400,ref_ref,z_24 +R 2800,3200,ref_ref,z_32 +R 2800,4000,ref_ref,z_40 +R 2800,4800,ref_ref,z_48 +R 2800,5600,ref_ref,z_56 +R 3600,4000,ref_ref,a_40 +R 3600,4800,ref_ref,a_48 +R 4400,4000,ref_ref,a_40 +S 2000,800,2000,2500,800,*,UP,TALU7 +S 4300,800,5300,800,200,*,RIGHT,ALU1 +S 300,800,1800,800,200,*,RIGHT,ALU1 +S 4100,6400,5300,6400,200,*,RIGHT,ALU1 +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,1200,1000,1600,200,*,UP,POLY +S 1000,1600,1000,2200,200,tt04,UP,NTRANS +S 1000,2200,1000,4700,200,*,UP,POLY +S 1000,4700,1000,5900,200,tt03,UP,PTRANS +S 1000,5900,1000,6300,200,*,UP,POLY +S 1200,1500,1200,3300,400,*,UP,ALU1 +S 1200,1600,1200,3200,400,b,UP,CALU1 +S 1200,3200,2000,3200,600,*,RIGHT,ALU1 +S 1500,500,1500,2000,400,*,UP,NDIF +S 1600,4900,1600,5700,600,*,UP,PDIF +S 1600,500,1600,800,600,*,UP,NDIF +S 1700,5500,1700,6800,400,*,UP,ALU1 +S 1800,4000,2300,4000,600,*,RIGHT,POLY +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,1600,2800,1600,600,*,RIGHT,ALU1 +S 2000,3200,2000,3200,400,b,LEFT,CALU1 +S 2300,2600,2300,4700,200,*,UP,POLY +S 2300,2600,2900,2600,200,*,RIGHT,POLY +S 2300,4700,2300,5900,200,tt07,UP,PTRANS +S 2300,5900,2300,6300,200,*,UP,POLY +S 2800,1500,2800,5700,400,*,UP,ALU1 +S 2800,1600,2800,5600,400,z,UP,CALU1 +S 2900,1200,2900,2200,200,tt08,UP,NTRANS +S 2900,800,2900,1200,200,*,UP,POLY +S 3200,1400,3200,2000,400,n1,UP,NDIF +S 3300,3500,3300,4700,200,*,UP,POLY +S 3300,3500,3600,3500,200,*,RIGHT,POLY +S 3300,4700,3300,5900,200,tt05,UP,PTRANS +S 3300,5900,3300,6300,200,*,UP,POLY +S 3600,1200,3600,2200,200,tt06,UP,NTRANS +S 3600,2200,3600,3500,200,*,UP,POLY +S 3600,3900,3600,4900,400,*,UP,ALU1 +S 3600,4000,3600,4800,400,a,UP,CALU1 +S 3600,4000,4500,4000,600,*,RIGHT,ALU1 +S 3600,800,3600,1200,200,*,UP,POLY +S 3700,2900,5200,2900,400,*,RIGHT,ALU1 +S 3800,5600,3800,6800,600,*,UP,ALU1 +S 3900,4700,3900,5700,600,*,UP,PDIF +S 4000,1400,4000,2000,600,*,UP,NDIF +S 400,1800,400,4000,400,*,UP,ALU1 +S 400,4000,2000,4000,400,*,RIGHT,ALU1 +S 4100,400,4100,2000,400,*,UP,ALU1 +S 4300,6600,5000,6600,600,*,RIGHT,NTIE +S 4400,4000,4400,4000,400,a,LEFT,CALU1 +S 4500,4500,4500,5700,200,tt01,UP,PTRANS +S 4600,1200,4600,1600,200,*,UP,POLY +S 4600,1600,4600,2200,200,tt02,UP,NTRANS +S 4600,2200,4600,4100,200,*,UP,POLY +S 4900,4800,5200,4800,400,*,RIGHT,ALU1 +S 500,1800,500,2000,400,*,UP,ALU1 +S 500,4000,500,5100,400,*,UP,ALU1 +S 5100,1800,5100,2000,400,*,UP,ALU1 +S 5200,1800,5200,4800,400,*,UP,ALU1 +V 1200,3000,CONT_POLY,* +V 1600,600,CONT_DIF_N,* +V 1700,5600,CONT_DIF_P,* +V 1900,4000,CONT_POLY,bn +V 2400,1700,CONT_DIF_N,* +V 2800,5100,CONT_DIF_P,* +V 3800,2900,CONT_POLY,an +V 3800,5600,CONT_DIF_P,* +V 4100,1900,CONT_DIF_N,* +V 4300,6600,CONT_BODY_N,* +V 4400,3900,CONT_POLY,* +V 5000,4800,CONT_DIF_P,an +V 5000,600,CONT_BODY_P,* +V 5000,6600,CONT_BODY_N,* +V 500,1900,CONT_DIF_N,bn +V 500,5000,CONT_DIF_P,bn +V 5100,1900,CONT_DIF_N,an +V 600,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd2abv0x05.vbe b/pdks/symbolic/vsclib/cells/nd2abv0x05.vbe new file mode 100755 index 000000000..7dc3f91ea --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2abv0x05.vbe @@ -0,0 +1,32 @@ +ENTITY nd2abv0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3700; + CONSTANT rdown_b_z : NATURAL := 3700; + CONSTANT rup_a_z : NATURAL := 4950; + CONSTANT rup_b_z : NATURAL := 4960; + CONSTANT tpll_a_z : NATURAL := 82; + CONSTANT tphh_b_z : NATURAL := 73; + CONSTANT tpll_b_z : NATURAL := 80; + CONSTANT tphh_a_z : NATURAL := 78; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2abv0x05; + +ARCHITECTURE behaviour_data_flow OF nd2abv0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2abv0x05" + SEVERITY WARNING; + z <= (a or b) after 186 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd2av0x05.ap b/pdks/symbolic/vsclib/cells/nd2av0x05.ap new file mode 100755 index 000000000..f9c725d43 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2av0x05.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 6 +H nd2av0x05,P, 5/ 7/2024,100 +A 0,0,4000,7200 +R 1200,2400,ref_ref,z_24 +R 1200,3200,ref_ref,z_32 +R 1200,4000,ref_ref,z_40 +R 1200,5600,ref_ref,b_56 +R 2000,4000,ref_ref,z_40 +R 2800,2400,ref_ref,a_24 +R 3600,2400,ref_ref,a_24 +R 3600,3200,ref_ref,a_32 +R 3600,4000,ref_ref,a_40 +R 400,2400,ref_ref,z_24 +R 400,4000,ref_ref,b_40 +R 400,4800,ref_ref,b_48 +R 400,5600,ref_ref,b_56 +S 700,4600,700,5500,800,*,UP,TALU8 +S 2500,4000,2500,5600,600,*,UP,PDIF +S 300,800,1600,800,200,*,RIGHT,ALU1 +S 2900,2100,2900,2500,200,*,UP,POLY +S 0,400,4000,400,800,*,RIGHT,ALU1 +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,5400,4000,5400,4400,*,RIGHT,NWELL +S 0,6800,4000,6800,800,*,RIGHT,ALU1 +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 1000,1500,1000,1900,200,*,UP,POLY +S 1000,1900,1000,2600,200,t04,UP,NTRANS +S 1000,2600,1000,3800,200,*,UP,POLY +S 1000,3800,1000,4600,200,t03,UP,PTRANS +S 1000,4600,1000,5100,200,*,UP,POLY +S 1100,5000,1100,5700,200,*,UP,POLY +S 1200,2300,1200,4100,400,*,UP,ALU1 +S 1200,2400,1200,4000,400,z,UP,CALU1 +S 1200,4000,2100,4000,400,*,RIGHT,ALU1 +S 1200,4100,2100,4100,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,b,LEFT,CALU1 +S 1400,2100,1400,2400,400,n1,UP,NDIF +S 1500,6600,3400,6600,600,*,RIGHT,NTIE +S 1700,1500,1700,1900,200,*,UP,POLY +S 1700,1900,1700,2600,200,t06,UP,NTRANS +S 1700,3200,2000,3200,600,*,RIGHT,POLY +S 2000,1500,2000,3300,400,*,UP,ALU1 +S 2000,1500,3500,1500,400,*,RIGHT,ALU1 +S 2000,3300,2800,3300,400,*,RIGHT,ALU1 +S 2000,3800,2000,4600,200,t05,UP,PTRANS +S 2000,4000,2000,4000,400,z,LEFT,CALU1 +S 2300,500,2300,2400,600,*,UP,NDIF +S 2400,5500,2400,6800,600,*,UP,ALU1 +S 2800,2400,2800,2400,400,a,LEFT,CALU1 +S 2800,2400,3600,2400,600,*,RIGHT,ALU1 +S 2800,3300,2800,4800,400,*,UP,ALU1 +S 2800,4800,3600,4800,400,*,RIGHT,ALU1 +S 2900,1200,2900,1800,200,t02,UP,NTRANS +S 2900,800,2900,1200,200,*,UP,POLY +S 3000,2400,3000,4100,200,*,UP,POLY +S 3000,4100,3000,5100,200,t01,UP,PTRANS +S 3000,5100,3000,5500,200,*,UP,POLY +S 3600,2300,3600,4100,400,*,UP,ALU1 +S 3600,2400,3600,4000,400,a,UP,CALU1 +S 400,2400,1200,2400,600,*,RIGHT,ALU1 +S 400,2400,400,2400,400,z,LEFT,CALU1 +S 400,3900,400,5700,400,*,UP,ALU1 +S 400,4000,400,5600,400,b,UP,CALU1 +S 400,4000,400,6700,400,*,UP,PDIF +S 400,5600,1400,5600,600,*,RIGHT,ALU1 +S 500,2100,500,2400,600,*,UP,NDIF +S 500,4000,500,6700,400,*,UP,PDIF +S 500,5600,500,6700,600,*,UP,PDIF +S 500,700,1400,700,800,*,RIGHT,PTIE +V 2500,5500,CONT_DIF_P,* +V 1300,5700,CONT_POLY,* +V 1300,600,CONT_BODY_P,* +V 1500,4100,CONT_DIF_P,* +V 1500,6600,CONT_BODY_N,* +V 2000,3200,CONT_POLY,an +V 2300,600,CONT_DIF_N,* +V 3100,2400,CONT_POLY,* +V 3400,1500,CONT_DIF_N,an +V 3400,6600,CONT_BODY_N,* +V 3500,4800,CONT_DIF_P,an +V 500,2300,CONT_DIF_N,* +V 500,6600,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd2av0x05.vbe b/pdks/symbolic/vsclib/cells/nd2av0x05.vbe new file mode 100755 index 000000000..e6750063f --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2av0x05.vbe @@ -0,0 +1,32 @@ +ENTITY nd2av0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_b : NATURAL := 2; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_b_z : NATURAL := 5290; + CONSTANT rdown_a_z : NATURAL := 5280; + CONSTANT rup_b_z : NATURAL := 7420; + CONSTANT rup_a_z : NATURAL := 7430; + CONSTANT tphl_b_z : NATURAL := 36; + CONSTANT tplh_b_z : NATURAL := 48; + CONSTANT tpll_a_z : NATURAL := 86; + CONSTANT tphh_a_z : NATURAL := 78; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2av0x05; + +ARCHITECTURE behaviour_data_flow OF nd2av0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2av0x05" + SEVERITY WARNING; + z <= (not (b) or a) after 221 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd2av0x1.ap b/pdks/symbolic/vsclib/cells/nd2av0x1.ap new file mode 100755 index 000000000..bd879a73d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2av0x1.ap @@ -0,0 +1,80 @@ +V ALLIANCE : 6 +H nd2av0x1,P,22/ 6/2024,100 +A 0,0,4000,7200 +R 400,3200,ref_ref,b_32 +R 400,5600,ref_ref,b_56 +R 400,4800,ref_ref,b_48 +R 400,4000,ref_ref,b_40 +R 3600,3200,ref_ref,a_32 +R 3600,2400,ref_ref,a_24 +R 2800,2400,ref_ref,a_24 +R 2000,4000,ref_ref,z_40 +R 1200,5600,ref_ref,b_56 +R 1200,4000,ref_ref,z_40 +R 1200,3200,ref_ref,z_32 +R 1200,2400,ref_ref,z_24 +S 2900,2000,2900,2500,200,*,UP,POLY +S 1700,2800,1700,3300,200,*,UP,POLY +S 2600,6600,3400,6600,600,*,LEFT,NTIE +S 3500,4100,3500,4200,600,*,DOWN,ALU1 +S 2800,3300,2800,4100,400,*,UP,ALU1 +S 2800,4100,3600,4100,400,*,RIGHT,ALU1 +S 2500,4900,2500,6800,400,*,UP,ALU1 +S 3600,2400,3600,3200,400,a,UP,CALU1 +S 3600,2300,3600,3300,400,*,UP,ALU1 +S 3000,5300,3000,5700,200,*,UP,POLY +S 3000,3900,3000,5300,200,t01,UP,PTRANS +S 2000,5300,2000,5700,200,*,UP,POLY +S 1000,5300,1000,5700,200,*,UP,POLY +S 700,3300,1000,3300,600,*,LEFT,POLY +S 500,3200,500,3400,400,*,UP,ALU1 +S 400,4100,400,6700,400,*,UP,PDIF +S 500,4100,500,6700,400,*,UP,PDIF +S 1000,3900,1000,5300,200,t03,UP,PTRANS +S 2000,3900,2000,5300,200,t05,UP,PTRANS +S 1500,4200,1500,4900,600,*,UP,ALU1 +S 400,3200,400,5600,400,b,UP,CALU1 +S 400,2300,1200,2300,400,*,LEFT,ALU1 +S 400,3100,400,5700,400,*,UP,ALU1 +S 400,5700,1300,5700,400,*,RIGHT,ALU1 +S 400,5600,1300,5600,400,*,RIGHT,ALU1 +S 3500,1300,3500,1600,600,*,UP,NDIF +S 3000,2400,3000,3800,200,*,UP,POLY +S 2900,700,2900,1100,200,*,UP,POLY +S 2900,1100,2900,1800,200,t02,UP,NTRANS +S 2800,2400,3600,2400,600,*,RIGHT,ALU1 +S 2800,2400,2800,2400,400,a,LEFT,CALU1 +S 2300,500,2300,2400,600,*,UP,NDIF +S 2000,4000,2000,4000,400,z,LEFT,CALU1 +S 2000,3300,2800,3300,400,*,RIGHT,ALU1 +S 2000,1500,3600,1500,400,*,RIGHT,ALU1 +S 2000,1500,2000,3300,400,*,UP,ALU1 +S 1700,3200,2000,3200,600,*,RIGHT,POLY +S 1700,1400,1700,2600,200,t06,UP,NTRANS +S 1400,1600,1400,2400,400,n1,UP,NDIF +S 1200,5600,1200,5600,400,b,LEFT,CALU1 +S 1200,4100,2100,4100,400,*,RIGHT,ALU1 +S 1200,4000,2100,4000,400,*,RIGHT,ALU1 +S 1200,2400,1200,4000,400,z,UP,CALU1 +S 1200,2300,1200,4100,400,*,UP,ALU1 +S 1000,2600,1000,3800,200,*,UP,POLY +S 1000,1400,1000,2600,200,t04,UP,NTRANS +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 0,6800,4000,6800,800,*,RIGHT,ALU1 +S 0,5400,4000,5400,4400,*,RIGHT,NWELL +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,400,4000,400,800,*,RIGHT,ALU1 +V 2600,6600,CONT_BODY_N,* +V 2500,5000,CONT_DIF_P,* +V 3500,4200,CONT_DIF_P,an +V 500,3300,CONT_POLY,* +V 1500,4200,CONT_DIF_P,* +V 1500,4900,CONT_DIF_P,* +V 500,6600,CONT_DIF_P,* +V 500,2300,CONT_DIF_N,* +V 3500,1500,CONT_DIF_N,an +V 3400,6600,CONT_BODY_N,* +V 3100,2400,CONT_POLY,* +V 2300,600,CONT_DIF_N,* +V 2000,3200,CONT_POLY,an +EOF diff --git a/pdks/symbolic/vsclib/cells/nd2av0x1.vbe b/pdks/symbolic/vsclib/cells/nd2av0x1.vbe new file mode 100755 index 000000000..128f9b0d2 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2av0x1.vbe @@ -0,0 +1,32 @@ +ENTITY nd2av0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 3100; + CONSTANT rdown_a_z : NATURAL := 3080; + CONSTANT rup_b_z : NATURAL := 4240; + CONSTANT rup_a_z : NATURAL := 4250; + CONSTANT tphl_b_z : NATURAL := 34; + CONSTANT tplh_b_z : NATURAL := 46; + CONSTANT tpll_a_z : NATURAL := 83; + CONSTANT tphh_a_z : NATURAL := 81; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2av0x1; + +ARCHITECTURE behaviour_data_flow OF nd2av0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2av0x1" + SEVERITY WARNING; + z <= (not (b) or a) after 153 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd2av0x2.ap b/pdks/symbolic/vsclib/cells/nd2av0x2.ap new file mode 100755 index 000000000..1a719111d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2av0x2.ap @@ -0,0 +1,79 @@ +V ALLIANCE : 6 +H nd2av0x2,P,22/ 6/2024,100 +A 0,0,4800,7200 +R 1200,2400,ref_ref,b_24 +R 1200,3200,ref_ref,b_32 +R 1200,4800,ref_ref,z_48 +R 1200,5600,ref_ref,z_56 +R 2000,1600,ref_ref,b_16 +R 2800,4000,ref_ref,a_40 +R 3600,3200,ref_ref,a_32 +R 3600,4000,ref_ref,a_40 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +S 2000,2700,2000,3200,200,*,UP,POLY +S 0,400,4800,400,800,*,RIGHT,ALU1 +S 0,400,4800,400,800,vss,RIGHT,CALU1 +S 0,5400,4800,5400,4400,*,RIGHT,NWELL +S 0,6800,4800,6800,800,*,RIGHT,ALU1 +S 0,6800,4800,6800,800,vdd,RIGHT,CALU1 +S 1100,3100,1100,3800,200,*,UP,POLY +S 1100,3800,1100,6200,200,t03,UP,PTRANS +S 1100,6200,1100,6600,200,*,UP,POLY +S 1200,2300,1200,3300,400,*,UP,ALU1 +S 1200,2300,2000,2300,400,*,RIGHT,ALU1 +S 1200,2400,1200,3200,400,b,UP,CALU1 +S 1200,4700,1200,5700,400,*,UP,ALU1 +S 1200,4800,1200,5600,400,z,UP,CALU1 +S 1200,5700,1700,5700,400,*,RIGHT,ALU1 +S 1300,600,1300,2500,200,t04,UP,NTRANS +S 1700,800,1700,2300,400,n1,UP,NDIF +S 2000,1500,2000,2300,400,*,UP,ALU1 +S 2000,1600,2000,1600,400,b,LEFT,CALU1 +S 2000,3100,2000,4900,400,*,UP,ALU1 +S 2000,3100,2800,3100,400,*,RIGHT,ALU1 +S 2000,4900,3900,4900,400,*,RIGHT,ALU1 +S 2000,600,2000,2500,200,t06,UP,NTRANS +S 2100,3100,2100,3800,200,*,UP,POLY +S 2100,3800,2100,6200,200,t05,UP,PTRANS +S 2100,6200,2100,6600,200,*,UP,POLY +S 2700,4000,2700,6000,600,*,UP,PDIF +S 2700,5700,2700,6800,400,*,UP,ALU1 +S 2800,2300,2800,3100,400,*,UP,ALU1 +S 2800,2300,4000,2300,400,*,RIGHT,ALU1 +S 2800,4000,2800,4000,400,a,LEFT,CALU1 +S 2800,4000,3600,4000,600,*,RIGHT,ALU1 +S 2800,400,2800,1600,600,*,UP,ALU1 +S 2800,800,2800,2300,600,*,UP,NDIF +S 3300,3000,3300,3800,200,*,UP,POLY +S 3300,3800,3300,5600,200,t01,UP,PTRANS +S 3300,5600,3300,6000,200,*,UP,POLY +S 3400,1200,3400,1600,200,*,UP,POLY +S 3400,1600,3400,2500,200,t02,UP,NTRANS +S 3400,2500,3400,3200,200,*,UP,POLY +S 3600,3100,3600,4100,400,*,UP,ALU1 +S 3600,3200,3600,4000,400,a,UP,CALU1 +S 3900,2200,3900,2300,600,*,UP,ALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 400,1500,900,1500,400,*,RIGHT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,4800,1200,4800,600,*,RIGHT,ALU1 +S 500,4000,500,6000,600,*,UP,PDIF +S 500,5700,500,6800,400,*,UP,ALU1 +V 1200,3100,CONT_POLY,* +V 1600,5700,CONT_DIF_P,* +V 2200,3100,CONT_POLY,an +V 2700,5800,CONT_DIF_P,* +V 2800,1600,CONT_DIF_N,* +V 2800,900,CONT_DIF_N,* +V 3600,3200,CONT_POLY,* +V 3700,6600,CONT_BODY_N,* +V 3800,4900,CONT_DIF_P,an +V 3800,600,CONT_BODY_P,* +V 3900,2200,CONT_DIF_N,an +V 500,5800,CONT_DIF_P,* +V 800,1500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd2av0x2.vbe b/pdks/symbolic/vsclib/cells/nd2av0x2.vbe new file mode 100755 index 000000000..065af93ff --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2av0x2.vbe @@ -0,0 +1,32 @@ +ENTITY nd2av0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3456; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 1950; + CONSTANT rdown_a_z : NATURAL := 1940; + CONSTANT rup_b_z : NATURAL := 2470; + CONSTANT rup_a_z : NATURAL := 2470; + CONSTANT tphl_b_z : NATURAL := 34; + CONSTANT tplh_b_z : NATURAL := 44; + CONSTANT tpll_a_z : NATURAL := 83; + CONSTANT tphh_a_z : NATURAL := 79; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2av0x2; + +ARCHITECTURE behaviour_data_flow OF nd2av0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2av0x2" + SEVERITY WARNING; + z <= (not (b) or a) after 115 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd2av0x4.ap b/pdks/symbolic/vsclib/cells/nd2av0x4.ap new file mode 100755 index 000000000..68b82eb9f --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2av0x4.ap @@ -0,0 +1,106 @@ +V ALLIANCE : 6 +H nd2av0x4,P,22/ 6/2024,100 +A 0,0,6400,7200 +R 1200,1600,ref_ref,z_16 +R 1200,4800,ref_ref,z_48 +R 2000,1600,ref_ref,z_16 +R 2000,3200,ref_ref,b_32 +R 2000,4000,ref_ref,b_40 +R 2000,4800,ref_ref,z_48 +R 2800,1600,ref_ref,z_16 +R 2800,3200,ref_ref,b_32 +R 2800,4800,ref_ref,z_48 +R 3600,4000,ref_ref,a_40 +R 3600,5600,ref_ref,z_56 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 4400,4000,ref_ref,a_40 +R 4400,4800,ref_ref,a_48 +S 2000,3200,3000,3200,600,*,LEFT,POLY +S 3000,2800,3000,3900,200,*,UP,POLY +S 2000,2900,2000,3900,200,*,UP,POLY +S 5000,3200,5000,3800,200,*,DOWN,POLY +S 0,400,6400,400,800,*,RIGHT,ALU1 +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 1000,3200,1000,4200,200,*,UP,POLY +S 1000,4200,1000,6600,200,t07,UP,PTRANS +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2400,1200,3300,400,*,UP,ALU1 +S 1200,2400,5500,2400,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1300,600,1300,2600,200,t09,UP,NTRANS +S 1500,4800,1500,5600,400,*,UP,ALU1 +S 1600,800,1600,2400,400,n1a,UP,NDIF +S 1900,3200,2900,3200,400,*,RIGHT,ALU1 +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,3200,2000,4000,400,b,UP,CALU1 +S 2000,3200,2000,4000,600,*,UP,ALU1 +S 2000,4200,2000,6600,200,t03,UP,PTRANS +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2000,600,2000,2600,200,t05,UP,NTRANS +S 2500,5600,2500,6800,600,*,UP,ALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2800,3200,2800,3200,400,b,LEFT,CALU1 +S 2800,4800,2800,4800,400,z,LEFT,CALU1 +S 3000,4200,3000,6600,200,t04,UP,PTRANS +S 3000,600,3000,2600,200,t06,UP,NTRANS +S 3300,800,3300,2400,400,n1b,UP,NDIF +S 3500,4000,4800,4000,400,*,RIGHT,ALU1 +S 3500,4800,3500,5700,400,*,UP,ALU1 +S 3600,4000,3600,4000,400,a,LEFT,CALU1 +S 3600,4800,3600,5700,400,*,UP,ALU1 +S 3600,5600,3600,5600,400,z,LEFT,CALU1 +S 3700,600,3700,2600,200,t10,UP,NTRANS +S 3800,2400,3800,3200,600,*,UP,ALU1 +S 4000,3200,4000,4200,200,*,UP,POLY +S 4000,4200,4000,6600,200,t08,UP,PTRANS +S 400,1600,2900,1600,400,*,RIGHT,ALU1 +S 400,1600,400,4800,400,*,UP,ALU1 +S 400,2400,400,4000,400,z,UP,CALU1 +S 400,4800,3600,4800,400,*,RIGHT,ALU1 +S 4200,400,4200,1600,600,*,UP,ALU1 +S 4300,800,4300,2400,400,*,UP,NDIF +S 4400,4000,4400,4800,400,a,UP,CALU1 +S 4400,4000,4400,4900,400,*,UP,ALU1 +S 4500,4100,4500,6400,400,*,UP,PDIF +S 4500,5600,4500,6800,600,*,UP,ALU1 +S 4800,1200,4800,2600,200,t02,UP,NTRANS +S 4800,2600,4800,3300,200,*,UP,POLY +S 4800,3200,4800,4000,400,*,UP,ALU1 +S 4800,800,4800,1200,200,*,UP,POLY +S 5000,3900,5000,6600,200,t01,UP,PTRANS +S 500,4400,500,6400,600,*,UP,PDIF +S 500,5600,500,6800,600,*,UP,ALU1 +S 5300,1400,5300,2400,600,*,UP,NDIF +S 5300,1500,5300,2400,400,*,UP,ALU1 +S 5500,2400,5500,5000,400,*,UP,ALU1 +S 5500,4200,5500,4900,600,*,UP,PDIF +S 700,800,700,2400,600,*,UP,NDIF +S 800,400,800,900,600,*,UP,ALU1 +V 1200,3200,CONT_POLY,an +V 1500,4800,CONT_DIF_P,* +V 1500,5500,CONT_DIF_P,* +V 2500,1600,CONT_DIF_N,* +V 2500,5600,CONT_DIF_P,* +V 2500,6300,CONT_DIF_P,* +V 2800,3200,CONT_POLY,* +V 3500,4800,CONT_DIF_P,* +V 3500,5500,CONT_DIF_P,* +V 3800,3200,CONT_POLY,an +V 4200,1600,CONT_DIF_N,* +V 4200,900,CONT_DIF_N,* +V 4500,5600,CONT_DIF_P,* +V 4500,6300,CONT_DIF_P,* +V 4800,3300,CONT_POLY,* +V 500,5600,CONT_DIF_P,* +V 500,6300,CONT_DIF_P,* +V 5300,1600,CONT_DIF_N,an +V 5300,2300,CONT_DIF_N,an +V 5500,4200,CONT_DIF_P,an +V 5500,4900,CONT_DIF_P,an +V 800,900,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd2av0x4.vbe b/pdks/symbolic/vsclib/cells/nd2av0x4.vbe new file mode 100755 index 000000000..cda53b30b --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2av0x4.vbe @@ -0,0 +1,32 @@ +ENTITY nd2av0x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_b : NATURAL := 10; + CONSTANT cin_a : NATURAL := 6; + CONSTANT rdown_b_z : NATURAL := 930; + CONSTANT rdown_a_z : NATURAL := 920; + CONSTANT rup_b_z : NATURAL := 1230; + CONSTANT rup_a_z : NATURAL := 1240; + CONSTANT tphl_b_z : NATURAL := 33; + CONSTANT tplh_b_z : NATURAL := 43; + CONSTANT tpll_a_z : NATURAL := 89; + CONSTANT tphh_a_z : NATURAL := 84; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2av0x4; + +ARCHITECTURE behaviour_data_flow OF nd2av0x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2av0x4" + SEVERITY WARNING; + z <= (not (b) or a) after 89 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd2v0x05.ap b/pdks/symbolic/vsclib/cells/nd2v0x05.ap new file mode 100755 index 000000000..c2481d665 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v0x05.ap @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H nd2v0x05,P, 5/ 7/2024,100 +A 0,0,3200,7200 +R 2800,2400,ref_ref,a_24 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 2000,3200,ref_ref,a_32 +R 1200,5600,ref_ref,b_56 +R 1200,4000,ref_ref,z_40 +R 400,4800,ref_ref,b_48 +R 400,5600,ref_ref,b_56 +R 2800,3200,ref_ref,a_32 +S 1800,6600,2700,6600,600,*,RIGHT,NTIE +S 1700,2600,1700,3300,200,*,UP,POLY +S 2100,3100,2100,3800,200,*,DOWN,POLY +S 1100,4600,1100,5800,200,*,UP,POLY +S 400,800,2000,800,200,*,RIGHT,ALU1 +S 1600,6400,2800,6400,200,*,RIGHT,ALU1 +S 2700,4000,2700,4400,600,*,DOWN,PDIF +S 2700,4200,2700,6800,400,*,UP,ALU1 +S 2000,3200,2000,3200,400,a,LEFT,CALU1 +S 400,2300,500,2300,600,*,RIGHT,ALU1 +S 1700,1500,1700,1900,200,*,DOWN,POLY +S 1000,1500,1000,1900,200,*,DOWN,POLY +S 400,2400,400,3200,400,z,UP,CALU1 +S 500,2100,500,2400,600,*,UP,NDIF +S 1000,2600,1000,3400,200,*,UP,POLY +S 1700,1900,1700,2600,200,t02,UP,NTRANS +S 1000,1900,1000,2600,200,t04,UP,NTRANS +S 1400,2100,1400,2400,400,n1,UP,NDIF +S 1100,3300,1100,3800,200,*,DOWN,POLY +S 2100,4600,2100,5000,200,*,UP,POLY +S 1100,3800,1100,4600,200,t03,UP,PTRANS +S 2100,3800,2100,4600,200,t01,UP,PTRANS +S 1200,4000,1200,4000,400,z,LEFT,CALU1 +S 0,6800,3200,6800,800,vdd,RIGHT,CALU1 +S 0,6800,3200,6800,800,*,RIGHT,ALU1 +S 0,5400,3200,5400,4400,*,RIGHT,NWELL +S 0,400,3200,400,800,vss,RIGHT,CALU1 +S 0,400,3200,400,800,*,RIGHT,ALU1 +S 2300,300,2300,1500,600,*,UP,ALU1 +S 2400,1400,2400,2400,600,*,UP,NDIF +S 2300,1400,2300,2400,600,*,UP,NDIF +S 400,4800,400,5600,400,b,UP,CALU1 +S 1200,5600,1200,5600,400,b,LEFT,CALU1 +S 400,4700,400,5700,400,*,UP,ALU1 +S 400,5600,1400,5600,400,*,RIGHT,ALU1 +S 400,5700,1400,5700,400,*,RIGHT,ALU1 +S 500,4000,500,6700,600,*,UP,PDIF +S 1200,3800,1200,4100,400,*,DOWN,ALU1 +S 400,3800,1200,3800,400,*,LEFT,ALU1 +S 400,2200,400,3800,400,*,UP,ALU1 +S 1200,4100,1700,4100,400,*,RIGHT,ALU1 +S 2000,3200,2800,3200,600,*,LEFT,ALU1 +S 2800,2300,2800,3300,400,*,UP,ALU1 +S 2800,2400,2800,3200,400,a,UP,CALU1 +S 600,600,1300,600,600,*,LEFT,PTIE +V 2700,4300,CONT_DIF_P,* +V 2000,3200,CONT_POLY,* +V 500,2300,CONT_DIF_N,* +V 1600,4100,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 2600,6600,CONT_BODY_N,* +V 1800,6600,CONT_BODY_N,* +V 2300,1500,CONT_DIF_N,* +V 1300,5600,CONT_POLY,* +V 500,6600,CONT_DIF_P,* +V 1300,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd2v0x05.vbe b/pdks/symbolic/vsclib/cells/nd2v0x05.vbe new file mode 100755 index 000000000..4f6f759b3 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v0x05.vbe @@ -0,0 +1,32 @@ +ENTITY nd2v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 2; + CONSTANT cin_b : NATURAL := 2; + CONSTANT rdown_a_z : NATURAL := 5290; + CONSTANT rdown_b_z : NATURAL := 5290; + CONSTANT rup_a_z : NATURAL := 7390; + CONSTANT rup_b_z : NATURAL := 7410; + CONSTANT tphl_a_z : NATURAL := 33; + CONSTANT tphl_b_z : NATURAL := 34; + CONSTANT tplh_b_z : NATURAL := 46; + CONSTANT tplh_a_z : NATURAL := 53; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2v0x05; + +ARCHITECTURE behaviour_data_flow OF nd2v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2v0x05" + SEVERITY WARNING; + z <= not ((a and b)) after 200 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd2v0x1.ap b/pdks/symbolic/vsclib/cells/nd2v0x1.ap new file mode 100755 index 000000000..758bddeab --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v0x1.ap @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H nd2v0x1,P,30/ 3/2007,1000 +A 0,0,32000,72000 +R 4000,16000,ref_ref,z_16 +R 12000,48000,ref_ref,z_48 +R 4000,40000,ref_ref,z_40 +R 12000,32000,ref_ref,b_32 +R 20000,40000,ref_ref,b_40 +R 20000,16000,ref_ref,a_16 +R 28000,24000,ref_ref,a_24 +R 20000,24000,ref_ref,a_24 +R 4000,24000,ref_ref,z_24 +R 4000,32000,ref_ref,z_32 +S 27000,47000,27000,68000,6000,*,UP,ALU1 +S 4000,48000,13000,48000,4000,*,RIGHT,ALU1 +S 11000,34000,11000,43000,2000,*,DOWN,POLY +S 21000,25000,21000,43000,2000,*,UP,POLY +S 11000,57000,11000,61000,2000,*,UP,POLY +S 27000,45000,27000,55000,6000,*,DOWN,PDIF +S 5000,45000,5000,57000,6000,*,UP,PDIF +S 4000,47000,17000,47000,4000,*,RIGHT,ALU1 +S 16000,47000,16000,54000,6000,*,DOWN,ALU1 +S 21000,43000,21000,57000,2000,t01,UP,PTRANS +S 11000,43000,11000,57000,2000,t03,UP,PTRANS +S 4000,16000,5000,16000,6000,*,LEFT,ALU1 +S 25000,9000,25000,17000,10000,*,UP,NDIF +S 17000,23000,21000,23000,2000,*,RIGHT,POLY +S 17000,3000,17000,7000,2000,*,DOWN,POLY +S 17000,7000,17000,19000,2000,t02,UP,NTRANS +S 13000,9000,13000,17000,4000,n1,UP,NDIF +S 10000,3000,10000,7000,2000,*,DOWN,POLY +S 10000,19000,10000,32000,2000,*,UP,POLY +S 10000,7000,10000,19000,2000,t04,UP,NTRANS +S 4000,16000,4000,40000,4000,z,UP,CALU1 +S 4000,15000,4000,48000,4000,*,UP,ALU1 +S 27000,4000,27000,11000,4000,*,DOWN,ALU1 +S 18000,66000,26000,66000,6000,*,LEFT,NTIE +S 5000,56000,5000,68000,6000,*,UP,ALU1 +S 12000,32000,12000,32000,4000,b,LEFT,CALU1 +S 20000,40000,20000,40000,4000,b,LEFT,CALU1 +S 12000,48000,12000,48000,4000,z,LEFT,CALU1 +S 20000,24000,28000,24000,6000,*,LEFT,ALU1 +S 20000,15000,20000,25000,4000,*,UP,ALU1 +S 20000,16000,20000,24000,4000,a,UP,CALU1 +S 28000,24000,28000,24000,4000,a,LEFT,CALU1 +S 0,4000,32000,4000,8000,*,RIGHT,ALU1 +S 0,4000,32000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,32000,54000,44000,*,RIGHT,NWELL +S 0,68000,32000,68000,8000,*,RIGHT,ALU1 +S 0,68000,32000,68000,8000,vdd,RIGHT,CALU1 +S 12000,36000,21000,36000,4000,*,RIGHT,ALU1 +S 12000,31000,12000,36000,4000,*,UP,ALU1 +S 20000,36000,20000,40000,6000,*,DOWN,ALU1 +V 27000,47000,CONT_DIF_P,* +V 27000,54000,CONT_DIF_P,* +V 16000,47000,CONT_DIF_P,* +V 16000,54000,CONT_DIF_P,* +V 5000,16000,CONT_DIF_N,* +V 23000,25000,CONT_POLY,* +V 27000,10000,CONT_DIF_N,* +V 18000,66000,CONT_BODY_N,* +V 5000,56000,CONT_DIF_P,* +V 12000,32000,CONT_POLY,* +V 26000,66000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd2v0x1.vbe b/pdks/symbolic/vsclib/cells/nd2v0x1.vbe new file mode 100755 index 000000000..9dbddad59 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v0x1.vbe @@ -0,0 +1,32 @@ +ENTITY nd2v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 3090; + CONSTANT rdown_b_z : NATURAL := 3100; + CONSTANT rup_a_z : NATURAL := 4220; + CONSTANT rup_b_z : NATURAL := 4240; + CONSTANT tphl_a_z : NATURAL := 33; + CONSTANT tphl_b_z : NATURAL := 34; + CONSTANT tplh_b_z : NATURAL := 45; + CONSTANT tplh_a_z : NATURAL := 52; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2v0x1; + +ARCHITECTURE behaviour_data_flow OF nd2v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2v0x1" + SEVERITY WARNING; + z <= not ((a and b)) after 133 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd2v0x2.ap b/pdks/symbolic/vsclib/cells/nd2v0x2.ap new file mode 100755 index 000000000..dce1d3ce4 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v0x2.ap @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H nd2v0x2,P,29/ 3/2007,1000 +A 0,0,32000,72000 +R 4000,48000,ref_ref,z_48 +R 20000,24000,ref_ref,b_24 +R 20000,40000,ref_ref,a_40 +R 12000,24000,ref_ref,b_24 +R 12000,32000,ref_ref,b_32 +R 12000,48000,ref_ref,z_48 +R 28000,32000,ref_ref,a_32 +R 28000,40000,ref_ref,a_40 +R 4000,16000,ref_ref,z_16 +R 4000,24000,ref_ref,z_24 +R 4000,32000,ref_ref,z_32 +R 4000,40000,ref_ref,z_40 +S 4000,16000,4000,48000,4000,z,UP,CALU1 +S 20000,36000,27000,36000,6000,*,LEFT,POLY +S 27000,35000,27000,41000,4000,*,UP,ALU1 +S 20000,24000,20000,24000,4000,b,LEFT,CALU1 +S 12000,24000,20000,24000,6000,*,RIGHT,ALU1 +S 28000,31000,28000,41000,4000,*,DOWN,ALU1 +S 20000,26000,20000,42000,2000,*,DOWN,POLY +S 20000,40000,20000,40000,4000,a,LEFT,CALU1 +S 15000,48000,15000,57000,4000,*,UP,ALU1 +S 4000,15000,4000,49000,4000,*,UP,ALU1 +S 4000,48000,12000,48000,6000,*,RIGHT,ALU1 +S 20000,40000,28000,40000,6000,*,RIGHT,ALU1 +S 28000,32000,28000,40000,4000,a,UP,CALU1 +S 0,4000,32000,4000,8000,*,RIGHT,ALU1 +S 0,4000,32000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,32000,54000,44000,*,RIGHT,NWELL +S 0,68000,32000,68000,8000,*,RIGHT,ALU1 +S 0,68000,32000,68000,8000,vdd,RIGHT,CALU1 +S 12000,23000,12000,33000,4000,*,UP,ALU1 +S 12000,24000,12000,32000,4000,b,UP,CALU1 +S 12000,48000,12000,48000,4000,z,LEFT,CALU1 +S 13000,6000,13000,26000,2000,t04,UP,NTRANS +S 16000,8000,16000,24000,4000,n1,UP,NDIF +S 20000,6000,20000,26000,2000,t02,UP,NTRANS +S 4000,15000,9000,15000,4000,*,RIGHT,ALU1 +S 26000,44000,26000,64000,6000,*,UP,PDIF +S 20000,42000,20000,66000,2000,t01,UP,PTRANS +S 10000,42000,10000,66000,2000,t03,UP,PTRANS +S 5000,44000,5000,64000,6000,*,UP,PDIF +S 25000,56000,25000,68000,6000,*,UP,ALU1 +S 5000,56000,5000,68000,6000,*,UP,ALU1 +S 10000,33000,10000,42000,2000,*,DOWN,POLY +S 27000,4000,27000,17000,4000,*,DOWN,ALU1 +S 27000,8000,27000,24000,6000,*,UP,NDIF +V 27000,36000,CONT_POLY,* +V 12000,32000,CONT_POLY,* +V 15000,49000,CONT_DIF_P,* +V 8000,15000,CONT_DIF_N,* +V 25000,63000,CONT_DIF_P,* +V 5000,63000,CONT_DIF_P,* +V 25000,56000,CONT_DIF_P,* +V 15000,56000,CONT_DIF_P,* +V 5000,56000,CONT_DIF_P,* +V 27000,9000,CONT_DIF_N,* +V 27000,16000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd2v0x2.vbe b/pdks/symbolic/vsclib/cells/nd2v0x2.vbe new file mode 100755 index 000000000..eaff71b3b --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v0x2.vbe @@ -0,0 +1,32 @@ +ENTITY nd2v0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_b : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 1850; + CONSTANT rdown_b_z : NATURAL := 1850; + CONSTANT rup_a_z : NATURAL := 2460; + CONSTANT rup_b_z : NATURAL := 2470; + CONSTANT tphl_a_z : NATURAL := 32; + CONSTANT tphl_b_z : NATURAL := 34; + CONSTANT tplh_b_z : NATURAL := 44; + CONSTANT tplh_a_z : NATURAL := 50; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2v0x2; + +ARCHITECTURE behaviour_data_flow OF nd2v0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2v0x2" + SEVERITY WARNING; + z <= not ((a and b)) after 94 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd2v0x4.ap b/pdks/symbolic/vsclib/cells/nd2v0x4.ap new file mode 100755 index 000000000..f7970748d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v0x4.ap @@ -0,0 +1,98 @@ +V ALLIANCE : 6 +H nd2v0x4,P,22/ 6/2024,100 +A 0,0,5600,7200 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,a_32 +R 2000,1600,ref_ref,z_16 +R 2000,2400,ref_ref,a_24 +R 2000,4800,ref_ref,z_48 +R 2800,1600,ref_ref,z_16 +R 2800,2400,ref_ref,a_24 +R 2800,3200,ref_ref,b_32 +R 2800,4000,ref_ref,b_40 +R 2800,4800,ref_ref,z_48 +R 3600,2400,ref_ref,a_24 +R 3600,4000,ref_ref,b_40 +R 3600,5600,ref_ref,z_56 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 4400,2400,ref_ref,a_24 +S 4500,800,5200,800,200,*,RIGHT,ALU1 +S 4000,3100,4000,3700,200,*,DOWN,POLY +S 3700,2700,3700,3300,200,*,UP,POLY +S 3000,2700,3000,3700,200,*,UP,POLY +S 2000,2800,2000,3700,200,*,UP,POLY +S 1300,2800,1300,3300,200,*,UP,POLY +S 1000,3100,1000,3700,200,*,DOWN,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,3800,1000,6600,200,t01,UP,PTRANS +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2400,1200,3300,400,*,UP,ALU1 +S 1200,2400,4500,2400,400,*,RIGHT,ALU1 +S 1200,3200,1200,3200,400,a,LEFT,CALU1 +S 1300,600,1300,2600,200,t03,UP,NTRANS +S 1400,4800,3600,4800,400,*,RIGHT,ALU1 +S 1500,4100,1500,4800,600,*,UP,ALU1 +S 1700,800,1700,2400,400,n1a,UP,NDIF +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,2400,2000,2400,400,a,LEFT,CALU1 +S 2000,3200,3000,3200,600,*,RIGHT,POLY +S 2000,3800,2000,6600,200,t05,UP,PTRANS +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2000,600,2000,2600,200,t07,UP,NTRANS +S 2500,4000,2500,6400,400,*,UP,PDIF +S 2500,5500,2500,6800,600,*,UP,ALU1 +S 2700,4000,3700,4000,400,*,RIGHT,ALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2800,2400,2800,2400,400,a,LEFT,CALU1 +S 2800,3200,2800,4000,400,b,UP,CALU1 +S 2800,3200,2800,4000,600,*,UP,ALU1 +S 2800,4800,2800,4800,400,z,LEFT,CALU1 +S 3000,3800,3000,5800,200,t06,UP,PTRANS +S 3000,5800,3000,6200,200,*,UP,POLY +S 3000,600,3000,2600,200,t08,UP,NTRANS +S 3300,800,3300,2400,400,n1b,UP,NDIF +S 3500,4800,3500,5700,400,*,UP,ALU1 +S 3600,2400,3600,2400,400,a,LEFT,CALU1 +S 3600,4000,3600,4000,400,b,LEFT,CALU1 +S 3600,4800,3600,5700,400,*,UP,ALU1 +S 3600,5600,3600,5600,400,z,LEFT,CALU1 +S 3700,600,3700,2600,200,t04,UP,NTRANS +S 3900,2400,3900,3200,600,*,UP,ALU1 +S 4000,3800,4000,5800,200,t02,UP,PTRANS +S 4000,5800,4000,6200,200,*,UP,POLY +S 400,1600,2900,1600,400,*,RIGHT,ALU1 +S 400,1600,400,4100,400,*,UP,ALU1 +S 400,2400,400,4000,400,z,UP,CALU1 +S 400,4100,1600,4100,400,*,RIGHT,ALU1 +S 4300,1500,4300,2400,600,*,UP,NDIF +S 4300,400,4300,1600,600,*,UP,ALU1 +S 4400,2400,4400,2400,400,a,LEFT,CALU1 +S 4500,4800,4500,6800,600,*,UP,ALU1 +S 4600,4000,4600,5600,600,*,UP,PDIF +S 500,4000,500,6400,600,*,UP,PDIF +S 500,5600,500,6800,600,*,UP,ALU1 +S 600,500,600,2400,600,*,UP,NDIF +V 1200,3200,CONT_POLY,* +V 1500,4100,CONT_DIF_P,* +V 1500,4800,CONT_DIF_P,* +V 2500,1600,CONT_DIF_N,* +V 2500,5500,CONT_DIF_P,* +V 2800,3200,CONT_POLY,* +V 3500,4800,CONT_DIF_P,* +V 3500,5500,CONT_DIF_P,* +V 3900,3200,CONT_POLY,* +V 4300,1600,CONT_DIF_N,* +V 4500,4800,CONT_DIF_P,* +V 4500,5500,CONT_DIF_P,* +V 5000,600,CONT_BODY_P,* +V 5000,6600,CONT_BODY_N,* +V 500,5600,CONT_DIF_P,* +V 500,6300,CONT_DIF_P,* +V 700,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd2v0x4.vbe b/pdks/symbolic/vsclib/cells/nd2v0x4.vbe new file mode 100755 index 000000000..43084a5ff --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v0x4.vbe @@ -0,0 +1,32 @@ +ENTITY nd2v0x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 11; + CONSTANT cin_b : NATURAL := 10; + CONSTANT rdown_a_z : NATURAL := 920; + CONSTANT rdown_b_z : NATURAL := 930; + CONSTANT rup_a_z : NATURAL := 1230; + CONSTANT rup_b_z : NATURAL := 1230; + CONSTANT tphl_a_z : NATURAL := 32; + CONSTANT tphl_b_z : NATURAL := 33; + CONSTANT tplh_b_z : NATURAL := 43; + CONSTANT tplh_a_z : NATURAL := 49; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2v0x4; + +ARCHITECTURE behaviour_data_flow OF nd2v0x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2v0x4" + SEVERITY WARNING; + z <= not ((a and b)) after 66 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd2v3x05.ap b/pdks/symbolic/vsclib/cells/nd2v3x05.ap new file mode 100755 index 000000000..484c2f7a8 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v3x05.ap @@ -0,0 +1,64 @@ +V ALLIANCE : 6 +H nd2v3x05,P, 5/ 7/2024,100 +A 0,0,3200,7200 +R 400,1600,ref_ref,z_16 +R 2000,5600,ref_ref,b_56 +R 1200,4000,ref_ref,z_40 +R 1200,4800,ref_ref,b_48 +R 1200,5600,ref_ref,b_56 +R 2000,2400,ref_ref,a_24 +R 2000,3200,ref_ref,a_32 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 2800,2400,ref_ref,a_24 +S 1800,6600,2600,6600,600,*,RIGHT,NTIE +S 1100,5000,1100,5400,200,*,UP,POLY +S 1700,2600,1700,3200,200,*,UP,POLY +S 2300,1100,2300,2400,600,*,UP,NDIF +S 2200,400,2200,1300,400,*,UP,ALU1 +S 400,1600,400,3200,400,z,UP,CALU1 +S 500,1500,500,2400,400,*,UP,ALU1 +S 400,1500,400,4000,400,*,UP,ALU1 +S 500,1500,500,2400,600,*,UP,NDIF +S 1000,500,1000,900,200,*,DOWN,POLY +S 1700,500,1700,900,200,*,DOWN,POLY +S 2100,4800,2100,5200,200,*,UP,POLY +S 1000,900,1000,2600,200,t04,UP,NTRANS +S 1700,900,1700,2600,200,t02,UP,NTRANS +S 1400,1100,1400,2400,400,n1,UP,NDIF +S 2100,3800,2100,4800,200,t01,UP,PTRANS +S 1100,3800,1100,4800,200,t03,UP,PTRANS +S 500,6400,500,6800,600,*,UP,ALU1 +S 500,4000,500,6500,600,*,UP,PDIF +S 2000,5600,2000,5600,400,b,LEFT,CALU1 +S 0,400,3200,400,800,*,RIGHT,ALU1 +S 0,400,3200,400,800,vss,RIGHT,CALU1 +S 0,5400,3200,5400,4400,*,RIGHT,NWELL +S 0,6800,3200,6800,800,*,RIGHT,ALU1 +S 0,6800,3200,6800,800,vdd,RIGHT,CALU1 +S 1200,4000,1200,4000,400,z,LEFT,CALU1 +S 1200,4800,1200,5600,400,b,UP,CALU1 +S 2000,2300,2000,3200,600,*,UP,ALU1 +S 2000,2400,2000,3200,400,a,UP,CALU1 +S 1100,3300,1100,3800,200,*,DOWN,POLY +S 1600,4000,1600,4100,600,*,DOWN,ALU1 +S 400,4000,1700,4000,400,*,RIGHT,ALU1 +S 2800,2400,2800,2400,400,a,LEFT,CALU1 +S 1900,2400,2800,2400,600,*,RIGHT,ALU1 +S 1000,2600,1000,3400,200,*,UP,POLY +S 1200,4800,1200,5600,600,*,UP,ALU1 +S 1100,5600,2100,5600,400,*,RIGHT,ALU1 +S 2800,4800,2800,6800,400,*,UP,ALU1 +S 2600,4800,2800,4800,400,*,LEFT,ALU1 +S 2700,4000,2700,4900,600,*,DOWN,PDIF +V 2200,1200,CONT_DIF_N,* +V 500,1600,CONT_DIF_N,* +V 1300,5400,CONT_POLY,* +V 500,6400,CONT_DIF_P,* +V 1800,6600,CONT_BODY_N,* +V 2600,6600,CONT_BODY_N,* +V 1600,4100,CONT_DIF_P,* +V 500,2300,CONT_DIF_N,* +V 2700,4800,CONT_DIF_P,* +V 2000,3200,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd2v3x05.vbe b/pdks/symbolic/vsclib/cells/nd2v3x05.vbe new file mode 100755 index 000000000..c950c3d8a --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v3x05.vbe @@ -0,0 +1,32 @@ +ENTITY nd2v3x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 2250; + CONSTANT rdown_b_z : NATURAL := 2310; + CONSTANT rup_a_z : NATURAL := 5920; + CONSTANT rup_b_z : NATURAL := 5950; + CONSTANT tphl_a_z : NATURAL := 26; + CONSTANT tphl_b_z : NATURAL := 25; + CONSTANT tplh_b_z : NATURAL := 51; + CONSTANT tplh_a_z : NATURAL := 65; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2v3x05; + +ARCHITECTURE behaviour_data_flow OF nd2v3x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2v3x05" + SEVERITY WARNING; + z <= not ((a and b)) after 144 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd2v5x05.ap b/pdks/symbolic/vsclib/cells/nd2v5x05.ap new file mode 100755 index 000000000..a1e7fa0ec --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v5x05.ap @@ -0,0 +1,63 @@ +V ALLIANCE : 6 +H nd2v5x05,P, 5/ 7/2024,100 +A 0,0,3200,7200 +R 2800,2400,ref_ref,a_24 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 2000,3200,ref_ref,a_32 +R 2000,2400,ref_ref,a_24 +R 1200,5600,ref_ref,b_56 +R 1200,4800,ref_ref,b_48 +R 1200,4000,ref_ref,z_40 +R 2000,5600,ref_ref,b_56 +S 1800,6600,2700,6600,600,*,RIGHT,NTIE +S 1100,5200,1100,5600,200,*,UP,POLY +S 1700,2600,1700,3200,200,*,UP,POLY +S 2400,1500,2400,2400,600,*,UP,NDIF +S 400,2300,500,2300,600,*,RIGHT,ALU1 +S 1100,5600,2100,5600,400,*,RIGHT,ALU1 +S 1200,4800,1200,5600,600,*,UP,ALU1 +S 400,2200,400,4000,400,*,UP,ALU1 +S 400,2400,400,3200,400,z,UP,CALU1 +S 1000,2600,1000,3400,200,*,UP,POLY +S 1900,2400,2800,2400,600,*,RIGHT,ALU1 +S 2800,2400,2800,2400,400,a,LEFT,CALU1 +S 400,4000,1700,4000,400,*,RIGHT,ALU1 +S 1600,4000,1600,4100,600,*,DOWN,ALU1 +S 1100,3300,1100,3800,200,*,DOWN,POLY +S 2300,400,2300,1600,600,*,UP,ALU1 +S 2000,2400,2000,3200,400,a,UP,CALU1 +S 2000,2300,2000,3200,600,*,UP,ALU1 +S 1200,4800,1200,5600,400,b,UP,CALU1 +S 1200,4000,1200,4000,400,z,LEFT,CALU1 +S 0,6800,3200,6800,800,vdd,RIGHT,CALU1 +S 0,6800,3200,6800,800,*,RIGHT,ALU1 +S 0,5400,3200,5400,4400,*,RIGHT,NWELL +S 0,400,3200,400,800,vss,RIGHT,CALU1 +S 0,400,3200,400,800,*,RIGHT,ALU1 +S 2000,5600,2000,5600,400,b,LEFT,CALU1 +S 500,4000,500,6500,600,*,UP,PDIF +S 500,6400,500,6800,600,*,UP,ALU1 +S 1400,2000,1400,2400,400,n1,UP,NDIF +S 1700,1800,1700,2600,200,t02,UP,NTRANS +S 1000,1800,1000,2600,200,t04,UP,NTRANS +S 1100,3800,1100,5000,200,t03,UP,PTRANS +S 2100,3800,2100,5000,200,t01,UP,PTRANS +S 2100,5000,2100,5400,200,*,UP,POLY +S 1700,1400,1700,1800,200,*,DOWN,POLY +S 1000,1400,1000,1800,200,*,DOWN,POLY +S 2600,4700,2800,4700,400,*,LEFT,ALU1 +S 2700,4000,2700,4800,600,*,DOWN,PDIF +S 2800,4700,2800,6800,400,*,UP,ALU1 +V 2000,3200,CONT_POLY,* +V 500,2300,CONT_DIF_N,* +V 1600,4100,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 2300,1600,CONT_DIF_N,* +V 2600,600,CONT_BODY_P,* +V 2600,6600,CONT_BODY_N,* +V 1800,6600,CONT_BODY_N,* +V 500,6400,CONT_DIF_P,* +V 1300,5600,CONT_POLY,* +V 2700,4700,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd2v5x05.vbe b/pdks/symbolic/vsclib/cells/nd2v5x05.vbe new file mode 100755 index 000000000..46853038c --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd2v5x05.vbe @@ -0,0 +1,32 @@ +ENTITY nd2v5x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 4610; + CONSTANT rdown_b_z : NATURAL := 4610; + CONSTANT rup_a_z : NATURAL := 4920; + CONSTANT rup_b_z : NATURAL := 4940; + CONSTANT tphl_a_z : NATURAL := 36; + CONSTANT tphl_b_z : NATURAL := 37; + CONSTANT tplh_b_z : NATURAL := 43; + CONSTANT tplh_a_z : NATURAL := 48; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd2v5x05; + +ARCHITECTURE behaviour_data_flow OF nd2v5x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd2v5x05" + SEVERITY WARNING; + z <= not ((a and b)) after 160 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd3abv0x05.ap b/pdks/symbolic/vsclib/cells/nd3abv0x05.ap new file mode 100755 index 000000000..6d747cfe2 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd3abv0x05.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H nd3abv0x05,P,23/ 6/2024,100 +A 0,0,4800,7200 +R 3600,5600,ref_ref,a_56 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,c_32 +R 1200,4000,ref_ref,c_40 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 3600,4800,ref_ref,a_48 +R 2800,4800,ref_ref,a_48 +R 2800,4000,ref_ref,a_40 +R 4400,2400,ref_ref,b_24 +R 4400,3200,ref_ref,b_32 +R 3600,1600,ref_ref,b_16 +R 4400,1600,ref_ref,b_16 +R 2000,4000,ref_ref,c_40 +S 3100,4200,3100,4800,200,*,DOWN,POLY +S 1700,2600,1700,3200,200,*,UP,POLY +S 1300,2100,1300,2400,400,n2,DOWN,NDIF +S 4300,4000,4300,5200,400,*,DOWN,ALU1 +S 1200,3100,1200,4300,400,*,DOWN,ALU1 +S 400,2200,400,5100,400,*,UP,ALU1 +S 2800,2600,2800,4000,200,*,UP,POLY +S 1000,2600,1000,4800,200,*,UP,POLY +S 3800,2600,3800,4800,200,*,DOWN,POLY +S 3800,6300,3800,6700,200,*,UP,POLY +S 3100,6300,3100,6700,200,*,UP,POLY +S 2000,5600,2000,6000,200,*,UP,POLY +S 1000,5600,1000,6000,200,*,UP,POLY +S 400,5000,400,6700,400,*,DOWN,PDIF +S 500,5000,500,6700,400,*,DOWN,PDIF +S 2600,5000,2600,6100,600,*,DOWN,PDIF +S 3100,4800,3100,6300,200,t03,UP,PTRANS +S 3800,4800,3800,6300,200,t01,UP,PTRANS +S 1000,4800,1000,5600,200,t07,UP,PTRANS +S 2000,4800,2000,5600,200,t05,UP,PTRANS +S 400,5100,1600,5100,400,*,RIGHT,ALU1 +S 1000,1500,1000,1900,200,*,DOWN,POLY +S 1700,1500,1700,1900,200,*,DOWN,POLY +S 2200,400,2200,2400,400,*,DOWN,ALU1 +S 2300,2100,2300,2400,400,*,DOWN,NDIF +S 1700,1900,1700,2600,200,t06,UP,NTRANS +S 1200,1500,1200,2200,400,*,DOWN,ALU1 +S 1000,1900,1000,2600,200,t08,UP,NTRANS +S 500,2100,500,2400,600,*,UP,NDIF +S 400,2200,1200,2200,400,*,RIGHT,ALU1 +S 3600,3200,3600,4000,400,*,UP,ALU1 +S 3300,2300,3300,3200,600,*,UP,ALU1 +S 2000,3300,2000,4800,200,*,DOWN,POLY +S 1900,3200,3600,3200,400,*,RIGHT,ALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 4300,500,4300,2400,400,*,UP,NDIF +S 4400,500,4400,2400,400,*,UP,NDIF +S 2300,600,3200,600,600,*,LEFT,PTIE +S 3800,1600,3800,2000,200,*,DOWN,POLY +S 2800,1600,2800,2000,200,*,DOWN,POLY +S 0,5400,4800,5400,4400,*,RIGHT,NWELL +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 0,6800,4800,6800,800,*,RIGHT,ALU1 +S 0,6800,4800,6800,800,vdd,RIGHT,CALU1 +S 0,400,4800,400,800,*,RIGHT,ALU1 +S 0,400,4800,400,800,vss,RIGHT,CALU1 +S 3500,1600,4400,1600,400,*,RIGHT,ALU1 +S 3800,2000,3800,2600,200,t02,UP,NTRANS +S 2800,2000,2800,2600,200,t04,UP,NTRANS +S 1200,4000,2000,4000,600,*,RIGHT,ALU1 +S 2000,4000,2000,4000,400,c,LEFT,CALU1 +S 4300,3200,4400,3200,600,*,RIGHT,ALU1 +S 2800,4800,3600,4800,600,*,RIGHT,ALU1 +S 2800,3900,2800,4900,400,*,UP,ALU1 +S 2600,5600,2600,6800,600,*,UP,ALU1 +S 3600,4000,4300,4000,400,*,RIGHT,ALU1 +S 3600,4700,3600,5700,400,*,UP,ALU1 +S 3600,1600,3600,1600,400,b,LEFT,CALU1 +S 3500,1500,4400,1500,400,*,RIGHT,ALU1 +S 4400,1500,4400,3300,400,*,UP,ALU1 +S 4400,1600,4400,3200,400,b,UP,CALU1 +S 1200,3200,1200,4000,400,c,UP,CALU1 +S 2800,4000,2800,4800,400,a,UP,CALU1 +S 3600,4800,3600,5600,400,a,UP,CALU1 +S 3800,3200,4300,3200,600,*,LEFT,POLY +S 3400,5000,3400,6100,400,n1,UP,PDIF +V 4300,5100,CONT_DIF_P,nd +V 1500,5100,CONT_DIF_P,* +V 2800,4200,CONT_POLY,* +V 1200,4200,CONT_POLY,* +V 2200,2300,CONT_DIF_N,* +V 500,2200,CONT_DIF_N,* +V 2000,3200,CONT_POLY,nd +V 4300,600,CONT_DIF_N,* +V 3200,600,CONT_BODY_P,* +V 2400,600,CONT_BODY_P,* +V 4300,3200,CONT_POLY,* +V 3300,2300,CONT_DIF_N,nd +V 2600,5600,CONT_DIF_P,* +V 500,6600,CONT_DIF_P,* +V 1500,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd3abv0x05.vbe b/pdks/symbolic/vsclib/cells/nd3abv0x05.vbe new file mode 100755 index 000000000..184f80fc5 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd3abv0x05.vbe @@ -0,0 +1,38 @@ +ENTITY nd3abv0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 3456; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_c : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 5320; + CONSTANT rdown_b_z : NATURAL := 5320; + CONSTANT rdown_c_z : NATURAL := 5290; + CONSTANT rup_a_z : NATURAL := 7430; + CONSTANT rup_b_z : NATURAL := 7420; + CONSTANT rup_c_z : NATURAL := 7430; + CONSTANT tpll_a_z : NATURAL := 110; + CONSTANT tpll_b_z : NATURAL := 100; + CONSTANT tphl_c_z : NATURAL := 38; + CONSTANT tplh_c_z : NATURAL := 50; + CONSTANT tphh_b_z : NATURAL := 84; + CONSTANT tphh_a_z : NATURAL := 93; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd3abv0x05; + +ARCHITECTURE behaviour_data_flow OF nd3abv0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd3abv0x05" + SEVERITY WARNING; + z <= not ((not a and not b) and c) after 238 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd3av0x05.ap b/pdks/symbolic/vsclib/cells/nd3av0x05.ap new file mode 100755 index 000000000..0af65e464 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd3av0x05.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H nd3av0x05,P,23/ 6/2024,100 +A 0,0,5600,7200 +R 4400,5600,ref_ref,a_56 +R 4400,4800,ref_ref,a_48 +R 2000,4000,ref_ref,z_40 +R 1200,4000,ref_ref,z_40 +R 3600,4000,ref_ref,a_32 +R 3600,2400,ref_ref,b_24 +R 2800,2400,ref_ref,b_24 +R 2800,3200,ref_ref,b_32 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 2000,1600,ref_ref,c_16 +R 1200,2400,ref_ref,c_24 +S 4600,2600,4600,4400,200,*,UP,POLY +S 4400,4800,4400,5600,400,a,UP,CALU1 +S 4400,4000,4400,5700,400,*,UP,ALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 2000,4000,2000,4000,400,z,LEFT,CALU1 +S 1200,4000,1200,4000,400,z,LEFT,CALU1 +S 3600,2400,3600,2400,400,b,LEFT,CALU1 +S 600,6600,1400,6600,600,*,RIGHT,NTIE +S 4600,1600,4600,2000,200,*,DOWN,POLY +S 3800,400,3800,1500,400,*,DOWN,ALU1 +S 3900,1100,3900,2400,800,*,UP,NDIF +S 1000,5600,1000,6000,200,*,UP,POLY +S 2200,5600,2200,6000,200,*,UP,POLY +S 3200,5600,3200,6000,200,*,UP,POLY +S 4600,6000,4600,6400,200,*,UP,POLY +S 1100,1400,1100,1700,600,*,DOWN,NDIF +S 1600,500,1600,900,200,*,UP,POLY +S 2300,500,2300,900,200,*,UP,POLY +S 3000,500,3000,900,200,*,UP,POLY +S 3200,3200,3800,3200,600,*,LEFT,POLY +S 5100,2200,5100,5200,400,*,DOWN,ALU1 +S 1600,5200,1600,6800,400,*,UP,ALU1 +S 500,4000,500,5000,400,*,DOWN,ALU1 +S 400,1500,400,5000,400,*,UP,ALU1 +S 2700,4000,2700,5000,400,*,UP,ALU1 +S 400,1500,1200,1500,400,*,LEFT,ALU1 +S 3000,2400,3200,2400,200,*,RIGHT,POLY +S 3200,2300,3200,4600,200,*,DOWN,POLY +S 3000,2300,3200,2300,200,*,RIGHT,POLY +S 4600,2000,4600,2600,200,t08,UP,NTRANS +S 3900,5000,3900,5800,800,*,DOWN,PDIF +S 3700,4800,3700,5400,400,*,UP,PDIF +S 4600,4800,4600,6000,200,t07,UP,PTRANS +S 1600,4800,1600,5400,600,*,DOWN,PDIF +S 3200,4600,3200,5600,200,t01,UP,PTRANS +S 1000,4600,1000,5600,200,t05,UP,PTRANS +S 2200,4600,2200,5600,200,t03,UP,PTRANS +S 400,4000,2700,4000,400,*,RIGHT,ALU1 +S 1200,2300,1200,2600,400,*,DOWN,ALU1 +S 1200,2400,1200,2400,400,c,LEFT,CALU1 +S 3700,3200,5100,3200,400,*,RIGHT,ALU1 +S 2100,3200,2900,3200,400,*,RIGHT,ALU1 +S 2900,2300,2900,3200,400,*,DOWN,ALU1 +S 2800,2400,3600,2400,600,*,RIGHT,ALU1 +S 2800,2400,2800,3200,400,b,DOWN,CALU1 +S 2800,2300,2800,3200,400,*,DOWN,ALU1 +S 2000,1500,2000,2300,400,*,UP,ALU1 +S 1200,2300,2000,2300,400,*,RIGHT,ALU1 +S 2000,1600,2000,1600,400,c,LEFT,CALU1 +S 1000,2600,1000,4600,200,*,DOWN,POLY +S 1400,2400,1600,2400,200,*,LEFT,POLY +S 1300,2300,1600,2300,200,*,LEFT,POLY +S 2200,3300,2200,4600,200,*,DOWN,POLY +S 2300,1900,2300,3100,200,*,UP,POLY +S 3700,5200,3700,6800,400,*,UP,ALU1 +S 3600,4000,3600,4000,400,a,LEFT,CALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 3500,4000,4400,4000,400,*,LEFT,ALU1 +S 3000,900,3000,1900,200,t02,UP,NTRANS +S 2600,1100,2600,1700,400,n1,UP,NDIF +S 2300,900,2300,1900,200,t04,UP,NTRANS +S 1600,900,1600,1900,200,t06,UP,NTRANS +S 1900,1100,1900,1700,400,n2,UP,NDIF +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,400,5600,400,800,*,RIGHT,ALU1 +V 3800,3200,CONT_POLY,an +V 5100,2300,CONT_DIF_N,an +V 5100,5100,CONT_DIF_P,an +V 1400,6600,CONT_BODY_N,* +V 600,6600,CONT_BODY_N,* +V 3800,1400,CONT_DIF_N,* +V 1100,1500,CONT_DIF_N,* +V 4400,4200,CONT_POLY,* +V 1600,5300,CONT_DIF_P,* +V 1200,2500,CONT_POLY,* +V 2700,4900,CONT_DIF_P,* +V 3700,5300,CONT_DIF_P,* +V 500,4900,CONT_DIF_P,* +V 2200,3200,CONT_POLY,* +V 5000,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd3av0x05.vbe b/pdks/symbolic/vsclib/cells/nd3av0x05.vbe new file mode 100755 index 000000000..d0a0da087 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd3av0x05.vbe @@ -0,0 +1,38 @@ +ENTITY nd3av0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_c : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 5090; + CONSTANT rdown_b_z : NATURAL := 5110; + CONSTANT rdown_c_z : NATURAL := 5100; + CONSTANT rup_a_z : NATURAL := 5950; + CONSTANT rup_b_z : NATURAL := 5930; + CONSTANT rup_c_z : NATURAL := 5940; + CONSTANT tpll_a_z : NATURAL := 93; + CONSTANT tphl_b_z : NATURAL := 45; + CONSTANT tphl_c_z : NATURAL := 42; + CONSTANT tplh_c_z : NATURAL := 53; + CONSTANT tplh_b_z : NATURAL := 61; + CONSTANT tphh_a_z : NATURAL := 93; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd3av0x05; + +ARCHITECTURE behaviour_data_flow OF nd3av0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd3av0x05" + SEVERITY WARNING; + z <= not ((not a and b) and c) after 203 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd3v0x05.ap b/pdks/symbolic/vsclib/cells/nd3v0x05.ap new file mode 100755 index 000000000..b718e74b7 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd3v0x05.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H nd3v0x05,P,28/ 2/2007,1000 +A 0,0,40000,72000 +R 4000,56000,ref_ref,z_56 +R 4000,48000,ref_ref,z_48 +R 4000,40000,ref_ref,z_40 +R 4000,32000,ref_ref,z_32 +R 4000,24000,ref_ref,z_24 +R 4000,16000,ref_ref,z_16 +R 36000,48000,ref_ref,b_48 +R 36000,24000,ref_ref,a_24 +R 28000,40000,ref_ref,b_40 +R 28000,32000,ref_ref,a_32 +R 20000,48000,ref_ref,z_48 +R 20000,40000,ref_ref,b_40 +R 20000,24000,ref_ref,c_24 +R 20000,16000,ref_ref,c_16 +R 12000,48000,ref_ref,z_48 +R 12000,24000,ref_ref,c_24 +S 10000,31000,10000,49000,2000,*,UP,POLY +S 20000,40000,20000,49000,2000,*,UP,POLY +S 30000,23000,30000,49000,2000,*,UP,POLY +S 25000,48000,25000,53000,4000,*,UP,ALU1 +S 10000,59000,10000,63000,2000,*,UP,POLY +S 20000,59000,20000,63000,2000,*,UP,POLY +S 30000,59000,30000,63000,2000,*,UP,POLY +S 35000,56000,35000,68000,6000,*,UP,ALU1 +S 15000,56000,15000,68000,6000,*,UP,ALU1 +S 5000,48000,5000,57000,4000,*,UP,ALU1 +S 10000,49000,10000,59000,2000,t05,UP,PTRANS +S 20000,49000,20000,59000,2000,t03,UP,PTRANS +S 30000,49000,30000,59000,2000,t01,UP,PTRANS +S 35000,51000,35000,57000,6000,*,UP,PDIF +S 10000,29000,16000,29000,6000,*,RIGHT,POLY +S 4000,48000,25000,48000,4000,*,RIGHT,ALU1 +S 4000,16000,4000,56000,4000,z,UP,CALU1 +S 4000,16000,12000,16000,4000,*,RIGHT,ALU1 +S 4000,15000,4000,57000,4000,*,UP,ALU1 +S 36000,48000,36000,48000,4000,b,LEFT,CALU1 +S 36000,40000,36000,49000,4000,*,UP,ALU1 +S 36000,24000,36000,24000,4000,a,LEFT,CALU1 +S 36000,23000,36000,32000,4000,*,UP,ALU1 +S 35000,4000,35000,16000,6000,*,UP,ALU1 +S 35000,15000,35000,21000,6000,*,UP,NDIF +S 30000,9000,30000,13000,2000,*,UP,POLY +S 30000,13000,30000,23000,2000,t02,UP,NTRANS +S 28000,40000,28000,40000,4000,b,LEFT,CALU1 +S 28000,32000,28000,32000,4000,a,LEFT,CALU1 +S 27000,32000,36000,32000,4000,*,RIGHT,ALU1 +S 26000,15000,26000,21000,4000,n1,UP,NDIF +S 23000,9000,23000,13000,2000,*,UP,POLY +S 23000,23000,23000,40000,2000,*,UP,POLY +S 23000,13000,23000,23000,2000,t04,UP,NTRANS +S 21000,15000,21000,24000,4000,*,UP,ALU1 +S 20000,48000,20000,48000,4000,z,LEFT,CALU1 +S 20000,40000,20000,40000,4000,b,LEFT,CALU1 +S 20000,16000,20000,24000,4000,c,UP,CALU1 +S 20000,15000,20000,24000,4000,*,UP,ALU1 +S 19000,40000,36000,40000,4000,*,RIGHT,ALU1 +S 19000,15000,19000,21000,4000,n2,UP,NDIF +S 16000,9000,16000,13000,2000,*,UP,POLY +S 16000,13000,16000,23000,2000,t06,UP,NTRANS +S 12000,48000,12000,48000,4000,z,LEFT,CALU1 +S 12000,24000,21000,24000,4000,*,RIGHT,ALU1 +S 12000,24000,12000,24000,4000,c,LEFT,CALU1 +S 12000,23000,21000,23000,4000,*,RIGHT,ALU1 +S 12000,23000,12000,30000,4000,*,UP,ALU1 +S 0,68000,40000,68000,8000,vdd,RIGHT,CALU1 +S 0,68000,40000,68000,8000,*,RIGHT,ALU1 +S 0,54000,40000,54000,44000,*,RIGHT,NWELL +S 0,4000,40000,4000,8000,vss,RIGHT,CALU1 +S 0,4000,40000,4000,8000,*,RIGHT,ALU1 +V 5000,52000,CONT_DIF_P,* +V 15000,56000,CONT_DIF_P,* +V 25000,52000,CONT_DIF_P,* +V 35000,56000,CONT_DIF_P,* +V 6000,6000,CONT_BODY_P,* +V 35000,16000,CONT_DIF_N,* +V 32000,32000,CONT_POLY,* +V 22000,40000,CONT_POLY,* +V 12000,29000,CONT_POLY,* +V 11000,16000,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd3v0x05.vbe b/pdks/symbolic/vsclib/cells/nd3v0x05.vbe new file mode 100755 index 000000000..9e1209143 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd3v0x05.vbe @@ -0,0 +1,38 @@ +ENTITY nd3v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_c : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 5100; + CONSTANT rdown_b_z : NATURAL := 5100; + CONSTANT rdown_c_z : NATURAL := 5100; + CONSTANT rup_a_z : NATURAL := 5940; + CONSTANT rup_b_z : NATURAL := 5930; + CONSTANT rup_c_z : NATURAL := 5950; + CONSTANT tphl_a_z : NATURAL := 46; + CONSTANT tphl_b_z : NATURAL := 46; + CONSTANT tphl_c_z : NATURAL := 43; + CONSTANT tplh_c_z : NATURAL := 54; + CONSTANT tplh_b_z : NATURAL := 62; + CONSTANT tplh_a_z : NATURAL := 68; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd3v0x05; + +ARCHITECTURE behaviour_data_flow OF nd3v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd3v0x05" + SEVERITY WARNING; + z <= not (((a and b) and c)) after 191 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd3v0x1.ap b/pdks/symbolic/vsclib/cells/nd3v0x1.ap new file mode 100755 index 000000000..a665d68a4 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd3v0x1.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H nd3v0x1,P,22/ 6/2024,100 +A 0,0,4000,7200 +R 3600,1600,ref_ref,a_16 +R 400,5600,ref_ref,z_56 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 3600,4800,ref_ref,b_48 +R 3600,2400,ref_ref,a_24 +R 2800,4000,ref_ref,b_40 +R 2800,3200,ref_ref,a_32 +R 2000,4800,ref_ref,z_48 +R 2000,2400,ref_ref,c_24 +R 1200,4800,ref_ref,z_48 +R 1200,3200,ref_ref,c_32 +R 1200,2400,ref_ref,c_24 +S 3000,3100,3000,4600,200,*,UP,POLY +S 2700,3000,3300,3000,200,*,RIGHT,POLY +S 2000,3500,2000,4500,200,*,DOWN,POLY +S 3300,600,3300,2400,600,*,UP,NDIF +S 3300,400,3300,800,600,*,UP,ALU1 +S 400,1500,900,1500,400,*,RIGHT,ALU1 +S 2000,2600,2000,4000,200,*,UP,POLY +S 2700,600,2700,2600,200,t02,UP,NTRANS +S 2300,800,2300,2400,400,n1,UP,NDIF +S 2000,600,2000,2600,200,t04,UP,NTRANS +S 1600,800,1600,2400,400,n2,UP,NDIF +S 1300,600,1300,2600,200,t06,UP,NTRANS +S 3600,1600,3600,2400,400,a,UP,CALU1 +S 3600,1500,3600,3200,400,*,UP,ALU1 +S 500,4900,500,5700,600,*,UP,PDIF +S 500,4800,500,5700,400,*,UP,ALU1 +S 400,4800,2500,4800,400,*,RIGHT,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 400,1500,400,5700,400,*,UP,ALU1 +S 3600,4800,3600,4800,400,b,LEFT,CALU1 +S 3600,4000,3600,4900,400,*,UP,ALU1 +S 3500,5600,3500,6800,600,*,UP,ALU1 +S 3500,4800,3500,6400,600,*,UP,PDIF +S 3000,4600,3000,6600,200,t01,UP,PTRANS +S 2800,4000,2800,4000,400,b,LEFT,CALU1 +S 2800,3200,2800,3200,400,a,LEFT,CALU1 +S 2700,3200,3600,3200,400,*,RIGHT,ALU1 +S 2500,4800,2500,5700,400,*,UP,ALU1 +S 2100,4000,3600,4000,400,*,RIGHT,ALU1 +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2000,4600,2000,6600,200,t03,UP,PTRANS +S 1500,5600,1500,6800,600,*,UP,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1200,2400,2100,2400,400,*,RIGHT,ALU1 +S 1200,2400,1200,3200,400,c,UP,CALU1 +S 1200,2300,2100,2300,400,*,RIGHT,ALU1 +S 1200,2300,1200,3300,400,*,UP,ALU1 +S 1000,4600,1000,6600,200,t05,UP,PTRANS +S 1000,3200,1000,4600,200,*,UP,POLY +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 0,6800,4000,6800,800,*,RIGHT,ALU1 +S 0,5400,4000,5400,4400,*,RIGHT,NWELL +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,400,4000,400,800,*,RIGHT,ALU1 +S 2000,2400,2000,2400,400,c,LEFT,CALU1 +V 3300,800,CONT_DIF_N,* +V 800,1500,CONT_DIF_N,* +V 500,5600,CONT_DIF_P,* +V 500,4900,CONT_DIF_P,* +V 3500,6300,CONT_DIF_P,* +V 3500,5600,CONT_DIF_P,* +V 3200,3200,CONT_POLY,* +V 2500,5600,CONT_DIF_P,* +V 2500,4900,CONT_DIF_P,* +V 2200,4000,CONT_POLY,* +V 1500,6300,CONT_DIF_P,* +V 1500,5600,CONT_DIF_P,* +V 1200,3200,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd3v0x1.vbe b/pdks/symbolic/vsclib/cells/nd3v0x1.vbe new file mode 100755 index 000000000..6e216efa9 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd3v0x1.vbe @@ -0,0 +1,38 @@ +ENTITY nd3v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 2550; + CONSTANT rdown_b_z : NATURAL := 2550; + CONSTANT rdown_c_z : NATURAL := 2550; + CONSTANT rup_a_z : NATURAL := 2970; + CONSTANT rup_b_z : NATURAL := 2960; + CONSTANT rup_c_z : NATURAL := 2970; + CONSTANT tphl_a_z : NATURAL := 43; + CONSTANT tphl_b_z : NATURAL := 42; + CONSTANT tphl_c_z : NATURAL := 39; + CONSTANT tplh_c_z : NATURAL := 50; + CONSTANT tplh_b_z : NATURAL := 58; + CONSTANT tplh_a_z : NATURAL := 64; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd3v0x1; + +ARCHITECTURE behaviour_data_flow OF nd3v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd3v0x1" + SEVERITY WARNING; + z <= not (((a and b) and c)) after 118 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd4v0x05.ap b/pdks/symbolic/vsclib/cells/nd4v0x05.ap new file mode 100755 index 000000000..21f0e8430 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd4v0x05.ap @@ -0,0 +1,116 @@ +V ALLIANCE : 6 +H nd4v0x05,P, 5/ 7/2024,100 +A 0,0,5600,7200 +R 1200,2400,ref_ref,d_24 +R 1200,3200,ref_ref,d_32 +R 1200,4800,ref_ref,z_48 +R 2000,1600,ref_ref,d_16 +R 2000,3200,ref_ref,c_32 +R 2000,4800,ref_ref,z_48 +R 2800,1600,ref_ref,c_16 +R 2800,2400,ref_ref,c_24 +R 2800,4000,ref_ref,b_40 +R 2800,4800,ref_ref,z_48 +R 3600,1600,ref_ref,a_16 +R 3600,3200,ref_ref,b_32 +R 3600,5600,ref_ref,z_56 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 4400,2400,ref_ref,a_24 +R 4400,3200,ref_ref,a_32 +R 4400,4800,ref_ref,b_48 +S 4400,600,5100,600,600,*,RIGHT,PTIE +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,3200,1000,4900,200,*,UP,POLY +S 1000,4900,1000,5900,200,t07,UP,PTRANS +S 1000,5900,1000,6300,200,*,UP,POLY +S 1200,2300,1200,3300,400,*,UP,ALU1 +S 1200,2300,2000,2300,400,*,RIGHT,ALU1 +S 1200,2400,1200,3200,400,d,UP,CALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1300,2900,1600,2900,200,*,RIGHT,POLY +S 1500,4800,1500,5400,400,*,UP,ALU1 +S 1600,1300,1600,2500,200,t08,UP,NTRANS +S 1600,900,1600,1300,200,*,UP,POLY +S 1800,4100,2000,4100,400,*,RIGHT,ALU1 +S 1900,1500,1900,2300,400,n3,UP,NDIF +S 2000,1500,2000,2300,400,*,UP,ALU1 +S 2000,1600,2000,1600,400,d,LEFT,CALU1 +S 2000,3100,2000,4100,400,*,UP,ALU1 +S 2000,3100,2800,3100,400,*,RIGHT,ALU1 +S 2000,3200,2000,3200,400,c,LEFT,CALU1 +S 2000,3200,2800,3200,400,*,RIGHT,ALU1 +S 2000,4100,2300,4100,600,*,RIGHT,POLY +S 2000,4200,2000,4900,200,*,UP,POLY +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2000,4900,2000,5900,200,t05,UP,PTRANS +S 2000,5900,2000,6300,200,*,UP,POLY +S 2300,1300,2300,2500,200,t06,UP,NTRANS +S 2300,2500,2300,4300,200,*,UP,POLY +S 2300,900,2300,1300,200,*,UP,POLY +S 2500,5600,2500,6800,600,*,UP,ALU1 +S 2600,1500,2600,2300,400,n2,UP,NDIF +S 2700,4000,3600,4000,400,*,RIGHT,ALU1 +S 2700,4000,4400,4000,400,*,RIGHT,ALU1 +S 2800,1500,2800,3200,400,*,UP,ALU1 +S 2800,1600,2800,2400,400,c,UP,CALU1 +S 2800,4000,2800,4000,400,b,LEFT,CALU1 +S 2800,4800,2800,4800,400,z,LEFT,CALU1 +S 3000,1300,3000,2500,200,t04,UP,NTRANS +S 3000,2500,3000,4900,200,*,UP,POLY +S 3000,4900,3000,5900,200,t03,UP,PTRANS +S 3000,5900,3000,6300,200,*,UP,POLY +S 3000,900,3000,1300,200,*,UP,POLY +S 3300,1500,3300,2300,400,n1,UP,NDIF +S 3500,4800,3500,5700,400,*,UP,ALU1 +S 3600,1500,3600,2300,400,*,UP,ALU1 +S 3600,1600,3600,1600,400,a,LEFT,CALU1 +S 3600,2300,4400,2300,400,*,RIGHT,ALU1 +S 3600,3100,3600,4000,400,*,UP,ALU1 +S 3600,3200,3600,3200,400,b,LEFT,CALU1 +S 3600,4100,4400,4100,400,*,RIGHT,ALU1 +S 3600,4800,3600,5700,400,*,UP,ALU1 +S 3600,5600,3600,5600,400,z,LEFT,CALU1 +S 3700,1300,3700,2500,200,t02,UP,NTRANS +S 3700,2900,4200,2900,200,*,RIGHT,POLY +S 3700,900,3700,1300,200,*,UP,POLY +S 4000,2900,4000,4900,200,*,UP,POLY +S 4000,3100,4200,3100,600,*,RIGHT,POLY +S 4000,4900,4000,5900,200,t01,UP,PTRANS +S 4000,5900,4000,6300,200,*,UP,POLY +S 400,1500,400,4800,400,*,UP,ALU1 +S 400,1600,1200,1600,400,*,RIGHT,ALU1 +S 400,1600,400,4000,400,z,UP,CALU1 +S 400,4800,3600,4800,400,*,RIGHT,ALU1 +S 4400,2300,4400,3300,400,*,UP,ALU1 +S 4400,2400,4400,3200,400,a,UP,CALU1 +S 4400,4000,4400,4900,400,*,UP,ALU1 +S 4400,4300,4400,4900,400,*,UP,ALU1 +S 4400,4800,4400,4800,400,b,LEFT,CALU1 +S 4500,1500,4500,2300,800,*,UP,NDIF +S 4500,400,4500,1600,600,*,UP,ALU1 +S 4600,5100,4600,5700,600,*,UP,PDIF +S 4600,5600,4600,6800,600,*,UP,ALU1 +S 500,5100,500,5700,600,*,UP,PDIF +S 500,5600,500,6800,600,*,UP,ALU1 +V 1100,1600,CONT_DIF_N,* +V 1200,3100,CONT_POLY,* +V 1500,5300,CONT_DIF_P,* +V 1900,4100,CONT_POLY,* +V 2500,5600,CONT_DIF_P,* +V 3200,4000,CONT_POLY,* +V 3500,5300,CONT_DIF_P,* +V 4400,3100,CONT_POLY,* +V 4500,1600,CONT_DIF_N,* +V 4600,5600,CONT_DIF_P,* +V 4900,600,CONT_BODY_P,* +V 5000,6600,CONT_BODY_N,* +V 500,5600,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd4v0x05.vbe b/pdks/symbolic/vsclib/cells/nd4v0x05.vbe new file mode 100755 index 000000000..d6c37f5ab --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd4v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY nd4v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 4; + CONSTANT cin_d : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 5440; + CONSTANT rdown_b_z : NATURAL := 5440; + CONSTANT rdown_c_z : NATURAL := 5440; + CONSTANT rdown_d_z : NATURAL := 5430; + CONSTANT rup_a_z : NATURAL := 5990; + CONSTANT rup_b_z : NATURAL := 5960; + CONSTANT rup_c_z : NATURAL := 5950; + CONSTANT rup_d_z : NATURAL := 5960; + CONSTANT tphl_a_z : NATURAL := 59; + CONSTANT tphl_b_z : NATURAL := 58; + CONSTANT tphl_c_z : NATURAL := 52; + CONSTANT tphl_d_z : NATURAL := 46; + CONSTANT tplh_d_z : NATURAL := 59; + CONSTANT tplh_c_z : NATURAL := 69; + CONSTANT tplh_b_z : NATURAL := 78; + CONSTANT tplh_a_z : NATURAL := 84; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd4v0x05; + +ARCHITECTURE behaviour_data_flow OF nd4v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd4v0x05" + SEVERITY WARNING; + z <= not ((((a and b) and c) and d)) after 206 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd4v0x1.ap b/pdks/symbolic/vsclib/cells/nd4v0x1.ap new file mode 100755 index 000000000..add6ebf02 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd4v0x1.ap @@ -0,0 +1,103 @@ +V ALLIANCE : 6 +H nd4v0x1,P,22/ 6/2024,100 +A 0,0,5600,7200 +R 1200,2400,ref_ref,d_24 +R 1200,3200,ref_ref,d_32 +R 1200,4800,ref_ref,z_48 +R 2000,1600,ref_ref,d_16 +R 2000,3200,ref_ref,c_32 +R 2000,4000,ref_ref,c_40 +R 2800,1600,ref_ref,c_16 +R 2800,2400,ref_ref,c_24 +R 3600,1600,ref_ref,a_16 +R 3600,3200,ref_ref,b_32 +R 3600,4000,ref_ref,b_40 +R 3600,5600,ref_ref,z_56 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,1600,ref_ref,a_16 +R 4400,2400,ref_ref,a_24 +R 4400,3200,ref_ref,a_32 +R 4400,4800,ref_ref,b_48 +R 4400,5600,ref_ref,b_56 +S 4100,3000,4100,3400,200,*,UP,POLY +S 4000,3100,4000,4500,200,*,UP,POLY +S 3700,3000,4500,3000,200,*,RIGHT,POLY +S 2000,3800,2000,4400,200,*,DOWN,POLY +S 1000,3000,1600,3000,200,*,RIGHT,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,3000,1000,4500,200,*,UP,POLY +S 1000,4500,1000,6200,200,t07,UP,PTRANS +S 1000,6200,1000,6600,200,*,UP,POLY +S 1200,2300,1200,3300,400,*,UP,ALU1 +S 1200,2300,2000,2300,400,*,RIGHT,ALU1 +S 1200,2400,1200,3200,400,d,UP,CALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1500,4900,1500,5700,400,*,UP,ALU1 +S 1600,2600,1600,2900,200,*,UP,POLY +S 1600,600,1600,2600,200,t08,UP,NTRANS +S 1900,800,1900,2400,400,n3,UP,NDIF +S 2000,1500,2000,2300,400,*,UP,ALU1 +S 2000,1600,2000,1600,400,d,LEFT,CALU1 +S 2000,3100,2800,3100,400,*,RIGHT,ALU1 +S 2000,3200,2000,4000,400,c,UP,CALU1 +S 2000,4500,2000,6200,200,t05,UP,PTRANS +S 2000,6200,2000,6600,200,*,UP,POLY +S 2100,3100,2100,4100,600,*,UP,ALU1 +S 2300,2600,2300,4000,200,*,UP,POLY +S 2300,600,2300,2600,200,t06,UP,NTRANS +S 2500,5800,2500,6800,400,*,UP,ALU1 +S 2600,800,2600,2400,400,n2,UP,NDIF +S 2800,1500,2800,3100,400,*,UP,ALU1 +S 2800,1600,2800,2400,400,c,UP,CALU1 +S 3000,2600,3000,4500,200,*,UP,POLY +S 3000,4500,3000,6200,200,t03,UP,PTRANS +S 3000,600,3000,2600,200,t04,UP,NTRANS +S 3000,6200,3000,6600,200,*,UP,POLY +S 3100,3900,3600,3900,400,*,RIGHT,ALU1 +S 3300,800,3300,2400,400,n1,UP,NDIF +S 3500,4900,3500,5700,400,*,UP,ALU1 +S 3600,1600,3600,1600,400,a,LEFT,CALU1 +S 3600,1600,4400,1600,600,*,RIGHT,ALU1 +S 3600,3100,3600,4100,400,*,UP,ALU1 +S 3600,3200,3600,4000,400,b,UP,CALU1 +S 3600,4100,4400,4100,400,*,RIGHT,ALU1 +S 3600,4900,3600,5700,400,*,UP,ALU1 +S 3600,5600,3600,5600,400,z,LEFT,CALU1 +S 3700,600,3700,2600,200,t02,UP,NTRANS +S 4000,4500,4000,6200,200,t01,UP,PTRANS +S 4000,6200,4000,6600,200,*,UP,POLY +S 400,1500,1200,1500,400,*,RIGHT,ALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,4800,1200,4800,600,*,RIGHT,ALU1 +S 400,4900,3600,4900,400,*,RIGHT,ALU1 +S 4400,1500,4400,3300,400,*,UP,ALU1 +S 4400,1600,4400,3200,400,a,UP,CALU1 +S 4400,4100,4400,5700,400,*,UP,ALU1 +S 4400,4800,4400,5600,400,b,UP,CALU1 +S 4400,500,4400,2400,600,*,UP,NDIF +S 4600,4700,4600,6700,600,*,UP,PDIF +S 500,4700,500,6000,600,*,UP,PDIF +S 500,5800,500,6800,400,*,UP,ALU1 +V 1100,1500,CONT_DIF_N,* +V 1200,3200,CONT_POLY,* +V 1500,4900,CONT_DIF_P,* +V 1500,5600,CONT_DIF_P,* +V 2200,3900,CONT_POLY,* +V 2500,5900,CONT_DIF_P,* +V 3200,3900,CONT_POLY,* +V 3500,4900,CONT_DIF_P,* +V 3500,5600,CONT_DIF_P,* +V 4300,600,CONT_DIF_N,* +V 4400,3200,CONT_POLY,* +V 4600,6600,CONT_DIF_P,* +V 500,5900,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd4v0x1.vbe b/pdks/symbolic/vsclib/cells/nd4v0x1.vbe new file mode 100755 index 000000000..5e5efc55e --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd4v0x1.vbe @@ -0,0 +1,44 @@ +ENTITY nd4v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT cin_d : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 3260; + CONSTANT rdown_b_z : NATURAL := 3270; + CONSTANT rdown_c_z : NATURAL := 3270; + CONSTANT rdown_d_z : NATURAL := 3260; + CONSTANT rup_a_z : NATURAL := 3520; + CONSTANT rup_b_z : NATURAL := 3500; + CONSTANT rup_c_z : NATURAL := 3500; + CONSTANT rup_d_z : NATURAL := 3500; + CONSTANT tphl_a_z : NATURAL := 56; + CONSTANT tphl_b_z : NATURAL := 54; + CONSTANT tphl_c_z : NATURAL := 49; + CONSTANT tphl_d_z : NATURAL := 42; + CONSTANT tplh_d_z : NATURAL := 55; + CONSTANT tplh_c_z : NATURAL := 64; + CONSTANT tplh_b_z : NATURAL := 73; + CONSTANT tplh_a_z : NATURAL := 79; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd4v0x1; + +ARCHITECTURE behaviour_data_flow OF nd4v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd4v0x1" + SEVERITY WARNING; + z <= not ((((a and b) and c) and d)) after 144 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nd4v0x2.ap b/pdks/symbolic/vsclib/cells/nd4v0x2.ap new file mode 100755 index 000000000..ad7104998 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd4v0x2.ap @@ -0,0 +1,174 @@ +V ALLIANCE : 6 +H nd4v0x2,P,22/ 6/2024,100 +A 0,0,8000,7200 +R 1200,1600,ref_ref,z_16 +R 1200,4800,ref_ref,z_48 +R 2000,1600,ref_ref,z_16 +R 2000,2400,ref_ref,a_24 +R 2000,4000,ref_ref,b_40 +R 2000,5600,ref_ref,z_56 +R 2800,1600,ref_ref,z_16 +R 2800,2400,ref_ref,a_24 +R 2800,4800,ref_ref,b_48 +R 2800,5600,ref_ref,z_56 +R 3600,1600,ref_ref,z_16 +R 3600,2400,ref_ref,a_24 +R 3600,3200,ref_ref,c_32 +R 3600,4000,ref_ref,c_40 +R 3600,4800,ref_ref,b_48 +R 3600,5600,ref_ref,z_56 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 4400,1600,ref_ref,z_16 +R 4400,2400,ref_ref,a_24 +R 4400,4000,ref_ref,c_40 +R 4400,4800,ref_ref,b_48 +R 5200,2400,ref_ref,a_24 +R 5200,3200,ref_ref,d_32 +R 5200,4000,ref_ref,c_40 +R 5200,4800,ref_ref,b_48 +R 6000,1600,ref_ref,a_16 +R 6000,2400,ref_ref,a_24 +R 6000,3200,ref_ref,d_32 +R 6000,4800,ref_ref,b_48 +R 6000,5600,ref_ref,b_56 +R 6800,2400,ref_ref,a_24 +R 6800,4000,ref_ref,d_40 +R 6800,4800,ref_ref,b_48 +R 7600,2400,ref_ref,a_24 +S 3300,3300,3300,4000,200,*,DOWN,POLY +S 6900,2600,7600,2600,200,*,RIGHT,POLY +S 6500,3200,6500,4900,200,*,UP,POLY +S 2000,3300,2000,4000,200,*,DOWN,POLY +S 2300,2800,2300,3500,200,*,UP,POLY +S 0,400,8000,400,800,*,RIGHT,ALU1 +S 0,400,8000,400,800,vss,RIGHT,CALU1 +S 0,5400,8000,5400,4400,*,RIGHT,NWELL +S 0,6800,8000,6800,800,*,RIGHT,ALU1 +S 0,6800,8000,6800,800,vdd,RIGHT,CALU1 +S 1000,2900,1000,4000,200,*,UP,POLY +S 1000,4000,1000,6500,200,t01,UP,PTRANS +S 1000,6500,1000,6900,200,*,UP,POLY +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2400,1200,2900,400,*,UP,ALU1 +S 1200,2400,7600,2400,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1300,2600,1600,2600,200,*,RIGHT,POLY +S 1400,5600,3900,5600,400,*,RIGHT,ALU1 +S 1500,4800,1500,5600,600,*,UP,ALU1 +S 1600,300,1600,700,200,*,UP,POLY +S 1600,700,1600,2200,200,t02,UP,NTRANS +S 1900,4000,2600,4000,400,*,RIGHT,ALU1 +S 1900,900,1900,2000,400,n1,UP,NDIF +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,2400,2000,2400,400,a,LEFT,CALU1 +S 2000,4000,2000,4000,400,b,LEFT,CALU1 +S 2000,4000,2000,6500,200,t04,UP,PTRANS +S 2000,5600,2000,5600,400,z,LEFT,CALU1 +S 2000,6500,2000,6900,200,*,UP,POLY +S 2200,3300,2200,4000,400,*,UP,ALU1 +S 2300,2200,2300,3300,200,*,UP,POLY +S 2300,300,2300,700,200,*,UP,POLY +S 2300,700,2300,2200,200,t05,UP,NTRANS +S 2600,4000,2600,4800,400,*,UP,ALU1 +S 2600,4800,6900,4800,400,*,RIGHT,ALU1 +S 2600,900,2600,2000,400,n2,UP,NDIF +S 2700,4200,2700,6500,600,*,UP,PDIF +S 2700,6300,2700,6800,600,*,UP,ALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2800,2400,2800,2400,400,a,LEFT,CALU1 +S 2800,4800,2800,4800,400,b,LEFT,CALU1 +S 2800,5600,2800,5600,400,z,LEFT,CALU1 +S 3000,2200,3000,3200,200,*,UP,POLY +S 3000,300,3000,700,200,*,UP,POLY +S 3000,3200,3500,3200,200,*,RIGHT,POLY +S 3000,700,3000,2200,200,t08,UP,NTRANS +S 3300,4000,3300,6500,200,t07,UP,PTRANS +S 3300,6500,3300,6900,200,*,UP,POLY +S 3300,900,3300,2000,400,n3,UP,NDIF +S 3500,4000,5800,4000,400,*,RIGHT,ALU1 +S 3600,1600,3600,1600,400,z,LEFT,CALU1 +S 3600,2400,3600,2400,400,a,LEFT,CALU1 +S 3600,3200,3600,4000,400,c,UP,CALU1 +S 3600,3200,3600,4000,600,*,UP,ALU1 +S 3600,4800,3600,4800,400,b,LEFT,CALU1 +S 3600,5600,3600,5600,400,z,LEFT,CALU1 +S 3700,2600,4700,2600,200,*,RIGHT,POLY +S 3700,300,3700,700,200,*,UP,POLY +S 3700,700,3700,2200,200,t11,UP,NTRANS +S 400,1600,400,4800,400,*,UP,ALU1 +S 400,1600,4500,1600,400,*,RIGHT,ALU1 +S 400,2400,400,4000,400,z,UP,CALU1 +S 400,4800,1600,4800,400,*,RIGHT,ALU1 +S 4300,2700,4300,4000,200,*,UP,POLY +S 4300,4000,4300,6500,200,t10,UP,PTRANS +S 4300,6500,4300,6900,200,*,UP,POLY +S 4400,1600,4400,1600,400,z,LEFT,CALU1 +S 4400,2400,4400,2400,400,a,LEFT,CALU1 +S 4400,4000,4400,4000,400,c,LEFT,CALU1 +S 4400,4800,4400,4800,400,b,LEFT,CALU1 +S 4500,2600,4500,3400,600,*,UP,POLY +S 4500,3200,6600,3200,400,*,RIGHT,ALU1 +S 4700,300,4700,700,200,*,UP,POLY +S 4700,700,4700,2200,200,t12,UP,NTRANS +S 4800,5500,4800,6800,600,*,UP,ALU1 +S 4900,4200,4900,6300,600,*,UP,PDIF +S 5000,900,5000,2000,400,n6,UP,NDIF +S 500,4200,500,6300,600,*,UP,PDIF +S 500,5500,500,6800,600,*,UP,ALU1 +S 5200,2400,5200,2400,400,a,LEFT,CALU1 +S 5200,3200,5200,3200,400,d,LEFT,CALU1 +S 5200,4000,5200,4000,400,c,LEFT,CALU1 +S 5200,4800,5200,4800,400,b,LEFT,CALU1 +S 5400,2200,5400,2700,200,*,UP,POLY +S 5400,300,5400,700,200,*,UP,POLY +S 5400,700,5400,2200,200,t09,UP,NTRANS +S 5500,2600,5500,4000,200,*,UP,POLY +S 5700,900,5700,2000,400,n5,UP,NDIF +S 5900,6600,7400,6600,600,*,RIGHT,NTIE +S 6000,1500,6000,2400,400,*,UP,ALU1 +S 6000,1600,6000,2400,400,a,UP,CALU1 +S 6000,2300,7600,2300,400,*,RIGHT,ALU1 +S 6000,3200,6000,3200,400,d,LEFT,CALU1 +S 6000,4800,6000,5600,400,b,UP,CALU1 +S 6000,4800,6000,5700,400,*,UP,ALU1 +S 6100,2200,6100,3200,200,*,UP,POLY +S 6100,300,6100,700,200,*,UP,POLY +S 6100,3200,6500,3200,200,*,RIGHT,POLY +S 6100,700,6100,2200,200,t06,UP,NTRANS +S 6400,900,6400,2000,400,n4,UP,NDIF +S 6600,3200,6600,4000,400,*,UP,ALU1 +S 6600,4000,6900,4000,400,*,RIGHT,ALU1 +S 6800,2400,6800,2400,400,a,LEFT,CALU1 +S 6800,2600,7300,2600,200,*,RIGHT,POLY +S 6800,300,6800,700,200,*,UP,POLY +S 6800,4000,6800,4000,400,d,LEFT,CALU1 +S 6800,4800,6800,4800,400,b,LEFT,CALU1 +S 6800,700,6800,2200,200,t03,UP,NTRANS +S 7300,400,7300,1100,400,*,UP,ALU1 +S 7400,900,7400,2000,600,*,UP,NDIF +S 7500,2300,7500,2900,600,*,UP,ALU1 +S 7600,2400,7600,2400,400,a,LEFT,CALU1 +S 900,500,900,2000,600,*,UP,NDIF +V 1000,600,CONT_DIF_N,* +V 1200,2800,CONT_POLY,* +V 1500,4800,CONT_DIF_P,* +V 1500,5600,CONT_DIF_P,* +V 2200,3400,CONT_POLY,* +V 2700,6300,CONT_DIF_P,* +V 3500,3400,CONT_POLY,* +V 3800,5600,CONT_DIF_P,* +V 4200,1600,CONT_DIF_N,* +V 4600,3200,CONT_POLY,* +V 4800,5500,CONT_DIF_P,* +V 4800,6200,CONT_DIF_P,* +V 500,5500,CONT_DIF_P,* +V 500,6200,CONT_DIF_P,* +V 5700,4000,CONT_POLY,* +V 5900,6600,CONT_BODY_N,* +V 6700,4800,CONT_POLY,* +V 7300,1000,CONT_DIF_N,* +V 7400,6600,CONT_BODY_N,* +V 7500,2800,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nd4v0x2.vbe b/pdks/symbolic/vsclib/cells/nd4v0x2.vbe new file mode 100755 index 000000000..e63339263 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nd4v0x2.vbe @@ -0,0 +1,44 @@ +ENTITY nd4v0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 5760; + CONSTANT cin_a : NATURAL := 8; + CONSTANT cin_b : NATURAL := 8; + CONSTANT cin_c : NATURAL := 7; + CONSTANT cin_d : NATURAL := 7; + CONSTANT rdown_a_z : NATURAL := 2180; + CONSTANT rdown_b_z : NATURAL := 2180; + CONSTANT rdown_c_z : NATURAL := 2180; + CONSTANT rdown_d_z : NATURAL := 2170; + CONSTANT rup_a_z : NATURAL := 2400; + CONSTANT rup_b_z : NATURAL := 2380; + CONSTANT rup_c_z : NATURAL := 2380; + CONSTANT rup_d_z : NATURAL := 2380; + CONSTANT tphl_a_z : NATURAL := 56; + CONSTANT tphl_b_z : NATURAL := 53; + CONSTANT tphl_c_z : NATURAL := 47; + CONSTANT tphl_d_z : NATURAL := 40; + CONSTANT tplh_d_z : NATURAL := 53; + CONSTANT tplh_c_z : NATURAL := 63; + CONSTANT tplh_b_z : NATURAL := 72; + CONSTANT tplh_a_z : NATURAL := 80; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nd4v0x2; + +ARCHITECTURE behaviour_data_flow OF nd4v0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nd4v0x2" + SEVERITY WARNING; + z <= not ((((a and b) and c) and d)) after 115 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr2av0x1.ap b/pdks/symbolic/vsclib/cells/nr2av0x1.ap new file mode 100755 index 000000000..27a79f25e --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2av0x1.ap @@ -0,0 +1,87 @@ +V ALLIANCE : 6 +H nr2av0x1,P, 5/ 7/2024,100 +A 0,0,4800,7200 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,b_32 +R 1200,4000,ref_ref,b_40 +R 1200,5600,ref_ref,z_56 +R 2000,1600,ref_ref,z_16 +R 2000,3200,ref_ref,a_32 +R 2000,4800,ref_ref,b_48 +R 2800,3200,ref_ref,a_32 +R 2800,4000,ref_ref,a_40 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +S 3800,500,3800,1000,600,*,UP,PTIE +S 3800,6200,3800,6800,600,*,UP,NTIE +S 2000,2300,2000,3900,200,*,UP,POLY +S 2200,1900,2200,2500,200,*,UP,POLY +S 2800,1600,2800,2400,600,*,UP,NDIF +S 3400,2700,3400,3600,200,*,DOWN,POLY +S 0,400,4800,400,800,*,RIGHT,ALU1 +S 0,400,4800,400,800,vss,RIGHT,CALU1 +S 0,5400,4800,5400,4400,*,RIGHT,NWELL +S 0,6800,4800,6800,800,*,RIGHT,ALU1 +S 0,6800,4800,6800,800,vdd,RIGHT,CALU1 +S 1200,1000,1200,1800,200,t04,UP,NTRANS +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,1700,1200,3300,200,*,UP,POLY +S 1200,3100,1200,4100,400,*,UP,ALU1 +S 1200,3200,1200,4000,400,b,UP,CALU1 +S 1200,4100,2000,4100,400,*,RIGHT,ALU1 +S 1200,500,1200,900,200,*,UP,POLY +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1300,3800,1300,6600,200,t03,UP,PTRANS +S 1600,4000,1600,6400,400,n1,UP,PDIF +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,3200,2000,3200,400,a,LEFT,CALU1 +S 2000,3200,3200,3200,600,*,RIGHT,ALU1 +S 2000,3800,2000,6600,200,t05,UP,PTRANS +S 2000,4100,2000,4900,400,*,UP,ALU1 +S 2000,4800,2000,4800,400,b,LEFT,CALU1 +S 2100,2300,4000,2300,400,*,RIGHT,ALU1 +S 2200,1000,2200,1800,200,t06,UP,NTRANS +S 2200,2300,2200,2400,600,*,UP,ALU1 +S 2200,500,2200,900,200,*,UP,POLY +S 2800,3100,2800,4100,400,*,UP,ALU1 +S 2800,3200,2800,4000,400,a,UP,CALU1 +S 2800,4000,2800,6400,600,*,UP,PDIF +S 2800,400,2800,1500,400,*,UP,ALU1 +S 2800,5000,2800,6800,400,*,UP,ALU1 +S 2900,1200,2900,2400,400,*,UP,NDIF +S 3400,1400,3400,1800,200,*,UP,POLY +S 3400,1800,3400,2600,200,t02,UP,NTRANS +S 3400,3800,3400,5400,200,t01,UP,PTRANS +S 3400,5400,3400,5800,200,*,UP,POLY +S 3900,4000,3900,4900,400,*,UP,ALU1 +S 3900,4100,3900,4800,600,*,UP,PDIF +S 4000,2300,4000,4900,400,*,UP,ALU1 +S 400,1500,2100,1500,400,*,RIGHT,ALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 400,1600,2100,1600,400,*,RIGHT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,4900,800,4900,400,*,RIGHT,ALU1 +S 600,500,600,1600,600,*,UP,NDIF +S 800,4900,800,5600,600,*,UP,PDIF +S 800,4900,800,5700,400,*,UP,ALU1 +S 800,5600,1200,5600,600,*,RIGHT,ALU1 +S 900,4900,900,5700,400,*,UP,ALU1 +V 2000,2400,CONT_POLY,an +V 1200,3200,CONT_POLY,* +V 1700,1500,CONT_DIF_N,* +V 2800,1400,CONT_DIF_N,* +V 2800,5100,CONT_DIF_P,* +V 2800,6200,CONT_DIF_P,* +V 3200,3200,CONT_POLY,* +V 3800,600,CONT_BODY_P,* +V 3800,6600,CONT_BODY_N,* +V 3900,2300,CONT_DIF_N,an +V 3900,4100,CONT_DIF_P,an +V 3900,4800,CONT_DIF_P,an +V 600,600,CONT_DIF_N,* +V 800,4900,CONT_DIF_P,* +V 800,5600,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr2av0x1.vbe b/pdks/symbolic/vsclib/cells/nr2av0x1.vbe new file mode 100755 index 000000000..a959b79a4 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2av0x1.vbe @@ -0,0 +1,32 @@ +ENTITY nr2av0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3456; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 2890; + CONSTANT rdown_a_z : NATURAL := 2900; + CONSTANT rup_b_z : NATURAL := 4150; + CONSTANT rup_a_z : NATURAL := 4160; + CONSTANT tplh_b_z : NATURAL := 45; + CONSTANT tphl_b_z : NATURAL := 41; + CONSTANT tphh_a_z : NATURAL := 83; + CONSTANT tpll_a_z : NATURAL := 95; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2av0x1; + +ARCHITECTURE behaviour_data_flow OF nr2av0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2av0x1" + SEVERITY WARNING; + z <= (not (b) and a) after 154 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr2av0x2.ap b/pdks/symbolic/vsclib/cells/nr2av0x2.ap new file mode 100755 index 000000000..ca681f925 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2av0x2.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H nr2av0x2,P,22/ 6/2024,100 +A 0,0,5600,7200 +R 1200,4000,ref_ref,b_40 +R 2000,3200,ref_ref,b_32 +R 2000,4800,ref_ref,z_48 +R 2800,2400,ref_ref,z_24 +R 2800,3200,ref_ref,z_32 +R 2800,4000,ref_ref,z_40 +R 2800,4800,ref_ref,z_48 +R 4400,2400,ref_ref,a_24 +R 5200,1600,ref_ref,a_16 +R 5200,2400,ref_ref,a_24 +S 1800,3100,1800,3600,200,*,UP,POLY +S 2200,2800,2200,3300,200,*,UP,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1100,3800,1100,6600,200,t06,UP,PTRANS +S 1100,4000,2000,4000,400,*,RIGHT,ALU1 +S 1200,1100,1200,2600,200,t08,UP,NTRANS +S 1200,4000,1200,4000,400,b,LEFT,CALU1 +S 1200,700,1200,1100,200,*,UP,POLY +S 1500,4000,1500,6400,400,n1a,UP,PDIF +S 1600,2300,2800,2300,400,*,RIGHT,ALU1 +S 1800,3800,1800,6600,200,t03,UP,PTRANS +S 1900,3400,2800,3400,200,*,RIGHT,POLY +S 1900,4800,2800,4800,400,*,RIGHT,ALU1 +S 1900,4900,2800,4900,400,*,RIGHT,ALU1 +S 2000,3100,2000,4000,400,*,UP,ALU1 +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2200,1100,2200,2600,200,t05,UP,NTRANS +S 2200,700,2200,1100,200,*,UP,POLY +S 2300,4800,2300,5600,400,*,UP,ALU1 +S 2800,2300,2800,4900,400,*,UP,ALU1 +S 2800,2400,2800,4800,400,z,UP,CALU1 +S 2800,3800,2800,6600,200,t04,UP,PTRANS +S 2800,500,2800,2400,600,*,UP,NDIF +S 3200,4000,3200,6400,400,n1b,UP,PDIF +S 3400,2200,4600,2200,200,*,RIGHT,POLY +S 3400,600,3400,1800,200,t02,UP,NTRANS +S 3500,3800,3500,6600,200,t07,UP,PTRANS +S 3600,1500,3600,3300,400,*,UP,ALU1 +S 3600,3300,5000,3300,400,*,RIGHT,ALU1 +S 3900,4000,3900,6400,600,*,UP,PDIF +S 4000,5000,4000,6800,400,*,UP,ALU1 +S 4400,2400,4400,2400,400,a,LEFT,CALU1 +S 4400,2400,5200,2400,600,*,RIGHT,ALU1 +S 4500,2400,4500,3800,200,*,UP,POLY +S 4500,3800,4500,6200,200,t01,UP,PTRANS +S 4500,6200,4500,6600,200,*,UP,POLY +S 5000,3300,5000,4900,400,*,UP,ALU1 +S 5000,4100,5000,4800,600,*,UP,PDIF +S 5000,500,5000,1600,600,*,UP,PTIE +S 500,4000,500,6400,600,*,UP,PDIF +S 500,500,500,2400,600,*,UP,NDIF +S 5200,1500,5200,2500,400,*,UP,ALU1 +S 5200,1600,5200,2400,400,a,UP,CALU1 +S 600,500,600,2400,600,*,UP,NDIF +S 600,5600,600,6800,600,*,UP,ALU1 +S 700,1500,4000,1500,400,*,RIGHT,ALU1 +S 700,1500,700,3300,400,*,UP,ALU1 +S 900,3200,1200,3200,600,*,RIGHT,POLY +V 1700,2300,CONT_DIF_N,* +V 2000,3200,CONT_POLY,* +V 2300,4800,CONT_DIF_P,* +V 2300,5500,CONT_DIF_P,* +V 2800,600,CONT_DIF_N,* +V 3600,3200,CONT_POLY,an +V 3900,1500,CONT_DIF_N,an +V 4000,5100,CONT_DIF_P,* +V 4000,5900,CONT_DIF_P,* +V 4700,2400,CONT_POLY,* +V 5000,4100,CONT_DIF_P,an +V 5000,4800,CONT_DIF_P,an +V 5000,600,CONT_BODY_P,* +V 600,5600,CONT_DIF_P,* +V 600,600,CONT_DIF_N,* +V 600,6300,CONT_DIF_P,* +V 700,3200,CONT_POLY,an +EOF diff --git a/pdks/symbolic/vsclib/cells/nr2av0x2.vbe b/pdks/symbolic/vsclib/cells/nr2av0x2.vbe new file mode 100755 index 000000000..1d34ae033 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2av0x2.vbe @@ -0,0 +1,32 @@ +ENTITY nr2av0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_b : NATURAL := 8; + CONSTANT cin_a : NATURAL := 5; + CONSTANT rdown_b_z : NATURAL := 1550; + CONSTANT rdown_a_z : NATURAL := 1550; + CONSTANT rup_b_z : NATURAL := 2080; + CONSTANT rup_a_z : NATURAL := 2080; + CONSTANT tplh_b_z : NATURAL := 41; + CONSTANT tphl_b_z : NATURAL := 39; + CONSTANT tphh_a_z : NATURAL := 85; + CONSTANT tpll_a_z : NATURAL := 101; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2av0x2; + +ARCHITECTURE behaviour_data_flow OF nr2av0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2av0x2" + SEVERITY WARNING; + z <= (not (b) and a) after 112 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr2av0x4.ap b/pdks/symbolic/vsclib/cells/nr2av0x4.ap new file mode 100755 index 000000000..3b26aba23 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2av0x4.ap @@ -0,0 +1,165 @@ +V ALLIANCE : 6 +H nr2av0x4,P, 5/ 7/2024,100 +A 0,0,10400,7200 +R 1200,1600,ref_ref,z_16 +R 1200,4800,ref_ref,z_48 +R 2000,1600,ref_ref,z_16 +R 2000,4800,ref_ref,z_48 +R 2000,5600,ref_ref,z_56 +R 2800,1600,ref_ref,z_16 +R 2800,2400,ref_ref,b_24 +R 2800,3200,ref_ref,b_32 +R 2800,4800,ref_ref,z_48 +R 3600,1600,ref_ref,z_16 +R 3600,2400,ref_ref,b_24 +R 3600,4800,ref_ref,z_48 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 4400,1600,ref_ref,z_16 +R 4400,2400,ref_ref,b_24 +R 4400,4800,ref_ref,z_48 +R 5200,1600,ref_ref,z_16 +R 5200,2400,ref_ref,b_24 +R 5200,4800,ref_ref,z_48 +R 6000,2400,ref_ref,b_24 +R 6000,4800,ref_ref,z_48 +R 8400,3200,ref_ref,a_32 +R 9200,2400,ref_ref,a_24 +R 9200,3200,ref_ref,a_32 +R 9200,4000,ref_ref,a_40 +S 6700,500,6700,2000,1000,*,DOWN,TALU7 +S 6800,3100,6800,3700,200,*,DOWN,POLY +S 5500,2000,5500,2500,200,*,UP,POLY +S 2300,2800,2300,3300,200,*,UP,POLY +S 0,400,10400,400,800,*,RIGHT,ALU1 +S 0,400,10400,400,800,vss,RIGHT,CALU1 +S 0,5400,10400,5400,4400,*,RIGHT,NWELL +S 0,6800,10400,6800,800,*,RIGHT,ALU1 +S 0,6800,10400,6800,800,vdd,RIGHT,CALU1 +S 1000,2700,1000,3800,200,*,UP,POLY +S 1000,3800,1000,6600,200,t10,UP,PTRANS +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2600,1600,2600,600,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1400,4000,1400,6400,400,n1a,UP,PDIF +S 1600,2500,1600,4000,400,*,UP,ALU1 +S 1600,4000,3800,4000,400,*,RIGHT,ALU1 +S 1600,700,1600,1800,600,*,UP,NDIF +S 1700,3400,2700,3400,200,*,RIGHT,POLY +S 1700,3800,1700,6600,200,t04,UP,PTRANS +S 1700,400,1700,900,600,*,UP,ALU1 +S 1700,700,1700,1800,600,*,UP,NDIF +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,4800,2000,5600,400,z,UP,CALU1 +S 2100,4800,2100,5700,600,*,UP,ALU1 +S 2300,300,2300,700,200,*,UP,POLY +S 2300,700,2300,2600,200,t08,UP,NTRANS +S 2400,3200,2900,3200,400,*,RIGHT,ALU1 +S 2700,2400,6100,2400,400,*,RIGHT,ALU1 +S 2700,3800,2700,6600,200,t05,UP,PTRANS +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2800,2400,2800,3200,400,b,UP,CALU1 +S 2800,2400,2800,3200,600,*,UP,ALU1 +S 2800,4800,2800,4800,400,z,LEFT,CALU1 +S 3100,4000,3100,6400,400,n1b,UP,PDIF +S 3300,300,3300,700,200,*,UP,POLY +S 3300,3200,4400,3200,600,*,RIGHT,POLY +S 3300,700,3300,2600,200,t13,UP,NTRANS +S 3400,3800,3400,6600,200,t11,UP,PTRANS +S 3600,1600,3600,1600,400,z,LEFT,CALU1 +S 3600,2400,3600,2400,400,b,LEFT,CALU1 +S 3600,4800,3600,4800,400,z,LEFT,CALU1 +S 3800,3200,3800,4000,400,*,UP,ALU1 +S 3800,3200,7400,3200,400,*,RIGHT,ALU1 +S 3900,400,3900,900,600,*,UP,ALU1 +S 3900,5600,3900,6800,600,*,UP,ALU1 +S 3900,700,3900,2400,600,*,UP,NDIF +S 400,1600,400,4800,400,*,UP,ALU1 +S 400,1600,5300,1600,400,*,RIGHT,ALU1 +S 400,2400,400,4000,400,z,UP,CALU1 +S 400,4800,6100,4800,400,*,RIGHT,ALU1 +S 4400,1600,4400,1600,400,z,LEFT,CALU1 +S 4400,2400,4400,2400,400,b,LEFT,CALU1 +S 4400,3800,4400,6600,200,t12,UP,PTRANS +S 4400,4800,4400,4800,400,z,LEFT,CALU1 +S 4500,1800,4500,3200,200,*,UP,POLY +S 4500,300,4500,700,200,*,UP,POLY +S 4500,700,4500,1800,200,t14,UP,NTRANS +S 4700,4000,4700,6400,400,n1c,UP,PDIF +S 5000,1500,5000,1600,600,*,UP,ALU1 +S 500,4000,500,6400,600,*,UP,PDIF +S 500,5600,500,6800,600,*,UP,ALU1 +S 5100,3400,6100,3400,200,*,RIGHT,POLY +S 5100,3800,5100,6600,200,t06,UP,PTRANS +S 5200,1600,5200,1600,400,z,LEFT,CALU1 +S 5200,2400,5200,2400,400,b,LEFT,CALU1 +S 5200,4800,5200,4800,400,z,LEFT,CALU1 +S 5300,2400,5300,3400,600,*,UP,POLY +S 5500,300,5500,700,200,*,UP,POLY +S 5500,700,5500,1800,200,t09,UP,NTRANS +S 5600,4000,5600,4800,400,*,UP,ALU1 +S 6000,2400,6000,2400,400,b,LEFT,CALU1 +S 6000,4800,6000,4800,400,z,LEFT,CALU1 +S 600,600,600,1800,600,*,UP,PTIE +S 6100,3800,6100,6600,200,t07,UP,PTRANS +S 6200,400,6200,1100,400,*,UP,ALU1 +S 6300,900,6300,1600,600,*,UP,NDIF +S 6500,4000,6500,6400,400,n1d,UP,PDIF +S 6800,3800,6800,6600,200,t4an,UP,PTRANS +S 7300,4000,7300,6400,600,*,UP,PDIF +S 7300,4800,7300,6800,400,*,UP,ALU1 +S 7400,1500,7400,2400,600,*,UP,NDIF +S 7400,1500,7400,4000,400,*,UP,ALU1 +S 7400,4000,8400,4000,400,*,RIGHT,ALU1 +S 7900,300,7900,700,200,*,UP,POLY +S 7900,3200,8900,3200,600,*,RIGHT,POLY +S 7900,3800,7900,5700,200,t01,UP,PTRANS +S 7900,5700,7900,6100,200,*,UP,POLY +S 7900,700,7900,2600,200,t03,UP,NTRANS +S 8300,3200,9200,3200,400,*,RIGHT,ALU1 +S 8400,3200,8400,3200,400,a,LEFT,CALU1 +S 8400,4000,8400,4900,400,*,UP,ALU1 +S 8400,400,8400,1900,400,*,UP,ALU1 +S 8400,900,8400,2400,600,*,UP,NDIF +S 8500,6600,9300,6600,600,*,RIGHT,NTIE +S 8900,3800,8900,5700,200,t02,UP,PTRANS +S 9200,2300,9200,4100,400,*,UP,ALU1 +S 9200,2400,9200,4000,400,a,UP,CALU1 +S 9400,4000,9400,5500,600,*,UP,PDIF +S 9400,500,9400,2200,600,*,UP,PTIE +S 9400,5300,9400,6800,400,*,UP,ALU1 +V 1200,2600,CONT_POLY,an +V 1700,900,CONT_DIF_N,* +V 2200,4800,CONT_DIF_P,* +V 2200,5600,CONT_DIF_P,* +V 2500,3200,CONT_POLY,* +V 2800,1600,CONT_DIF_N,* +V 3900,5600,CONT_DIF_P,* +V 3900,6300,CONT_DIF_P,* +V 3900,900,CONT_DIF_N,* +V 4300,3200,CONT_POLY,an +V 5000,1500,CONT_DIF_N,* +V 500,5600,CONT_DIF_P,* +V 500,6300,CONT_DIF_P,* +V 5300,2400,CONT_POLY,* +V 5600,4100,CONT_DIF_P,* +V 5600,4800,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 6200,1000,CONT_DIF_N,* +V 7000,3200,CONT_POLY,an +V 7300,4900,CONT_DIF_P,* +V 7300,5600,CONT_DIF_P,* +V 7300,6300,CONT_DIF_P,* +V 7400,1600,CONT_DIF_N,an +V 7400,2300,CONT_DIF_N,an +V 8400,1000,CONT_DIF_N,* +V 8400,1800,CONT_DIF_N,* +V 8400,4100,CONT_DIF_P,an +V 8400,4800,CONT_DIF_P,an +V 8500,6600,CONT_BODY_N,* +V 8600,3200,CONT_POLY,* +V 9300,6600,CONT_BODY_N,* +V 9400,5400,CONT_DIF_P,* +V 9400,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr2av0x4.vbe b/pdks/symbolic/vsclib/cells/nr2av0x4.vbe new file mode 100755 index 000000000..0cb5164e1 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2av0x4.vbe @@ -0,0 +1,32 @@ +ENTITY nr2av0x4 IS +GENERIC ( + CONSTANT area : NATURAL := 7488; + CONSTANT cin_b : NATURAL := 16; + CONSTANT cin_a : NATURAL := 7; + CONSTANT rdown_b_z : NATURAL := 770; + CONSTANT rdown_a_z : NATURAL := 780; + CONSTANT rup_b_z : NATURAL := 1040; + CONSTANT rup_a_z : NATURAL := 1040; + CONSTANT tplh_b_z : NATURAL := 41; + CONSTANT tphl_b_z : NATURAL := 39; + CONSTANT tphh_a_z : NATURAL := 89; + CONSTANT tpll_a_z : NATURAL := 107; + CONSTANT transistors : NATURAL := 15 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2av0x4; + +ARCHITECTURE behaviour_data_flow OF nr2av0x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2av0x4" + SEVERITY WARNING; + z <= (not (b) and a) after 92 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr2av1x05.ap b/pdks/symbolic/vsclib/cells/nr2av1x05.ap new file mode 100755 index 000000000..33f8047dd --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2av1x05.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H nr2av1x05,P,23/ 6/2024,100 +A 0,0,4800,7200 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,b_32 +R 1200,4000,ref_ref,b_40 +R 1200,5600,ref_ref,z_56 +R 2000,1600,ref_ref,z_16 +R 2000,3200,ref_ref,a_32 +R 2000,4800,ref_ref,b_48 +R 2800,3200,ref_ref,a_32 +R 2800,4000,ref_ref,a_40 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +S 2200,2100,2200,2500,200,*,UP,POLY +S 0,400,4800,400,800,*,RIGHT,ALU1 +S 0,400,4800,400,800,vss,RIGHT,CALU1 +S 0,5400,4800,5400,4400,*,RIGHT,NWELL +S 0,6800,4800,6800,800,*,RIGHT,ALU1 +S 0,6800,4800,6800,800,vdd,RIGHT,CALU1 +S 1200,1000,1200,1800,200,t04,UP,NTRANS +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,1800,1200,3300,200,*,UP,POLY +S 1200,3100,1200,4100,400,*,UP,ALU1 +S 1200,3200,1200,4000,400,b,UP,CALU1 +S 1200,4100,2000,4100,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1200,600,1200,1000,200,*,UP,POLY +S 1300,3500,1300,4400,200,*,UP,POLY +S 1300,4400,1300,5900,200,t03,UP,PTRANS +S 1300,5900,1300,6300,200,*,UP,POLY +S 1600,4600,1600,5700,400,n1,UP,PDIF +S 1900,2400,3900,2400,400,*,RIGHT,ALU1 +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,2300,2000,4400,200,*,UP,POLY +S 2000,3200,2000,3200,400,a,LEFT,CALU1 +S 2000,3200,2800,3200,600,*,RIGHT,ALU1 +S 2000,4100,2000,4900,400,*,UP,ALU1 +S 2000,4400,2000,5900,200,t05,UP,PTRANS +S 2000,4800,2000,4800,400,b,LEFT,CALU1 +S 2000,5900,2000,6300,200,*,UP,POLY +S 2200,1000,2200,1800,200,t06,UP,NTRANS +S 2200,600,2200,1000,200,*,UP,POLY +S 2800,1200,2800,2400,600,*,UP,NDIF +S 2800,3100,2800,4100,400,*,UP,ALU1 +S 2800,3200,2800,4000,400,a,UP,CALU1 +S 2800,3500,3400,3500,600,*,RIGHT,POLY +S 2800,400,2800,1500,400,*,UP,ALU1 +S 2800,4600,2800,5700,600,*,UP,PDIF +S 2900,4900,2900,6800,600,*,UP,ALU1 +S 3000,6600,3800,6600,600,*,RIGHT,NTIE +S 3400,1600,3400,2000,200,*,UP,POLY +S 3400,2000,3400,2600,200,t02,UP,NTRANS +S 3400,2600,3400,4400,200,*,UP,POLY +S 3400,4400,3400,5600,200,t01,UP,PTRANS +S 3400,5600,3400,6000,200,*,UP,POLY +S 3800,500,3800,1100,600,*,UP,PTIE +S 3900,2200,3900,4800,400,*,UP,ALU1 +S 400,1500,2100,1500,400,*,RIGHT,ALU1 +S 400,1500,400,5700,400,*,UP,ALU1 +S 400,1600,2100,1600,400,*,RIGHT,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 400,5600,1200,5600,600,*,RIGHT,ALU1 +S 600,500,600,1600,600,*,UP,NDIF +V 1200,3500,CONT_POLY,* +V 1700,1500,CONT_DIF_N,* +V 2000,2400,CONT_POLY,an +V 2800,1400,CONT_DIF_N,* +V 2800,3500,CONT_POLY,* +V 2800,5600,CONT_DIF_P,* +V 2900,4900,CONT_DIF_P,* +V 3000,6600,CONT_BODY_N,* +V 3800,600,CONT_BODY_P,* +V 3800,6600,CONT_BODY_N,* +V 3900,2300,CONT_DIF_N,an +V 3900,4700,CONT_DIF_P,an +V 600,600,CONT_DIF_N,* +V 800,5600,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr2av1x05.vbe b/pdks/symbolic/vsclib/cells/nr2av1x05.vbe new file mode 100755 index 000000000..2ebdfb8a5 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2av1x05.vbe @@ -0,0 +1,32 @@ +ENTITY nr2av1x05 IS +GENERIC ( + CONSTANT area : NATURAL := 3456; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_b_z : NATURAL := 2970; + CONSTANT rdown_a_z : NATURAL := 2940; + CONSTANT rup_b_z : NATURAL := 7760; + CONSTANT rup_a_z : NATURAL := 7780; + CONSTANT tplh_b_z : NATURAL := 53; + CONSTANT tphl_b_z : NATURAL := 34; + CONSTANT tphh_a_z : NATURAL := 90; + CONSTANT tpll_a_z : NATURAL := 83; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2av1x05; + +ARCHITECTURE behaviour_data_flow OF nr2av1x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2av1x05" + SEVERITY WARNING; + z <= (not (b) and a) after 199 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr2v0x05.ap b/pdks/symbolic/vsclib/cells/nr2v0x05.ap new file mode 100755 index 000000000..ba285a066 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2v0x05.ap @@ -0,0 +1,60 @@ +V ALLIANCE : 6 +H nr2v0x05,P,23/ 6/2024,100 +A 0,0,3200,7200 +R 400,5600,ref_ref,z_56 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 2800,4000,ref_ref,a_40 +R 2800,3200,ref_ref,a_32 +R 2000,4800,ref_ref,b_48 +R 2000,3200,ref_ref,a_32 +R 1200,4000,ref_ref,b_40 +R 1200,2400,ref_ref,z_24 +S 2100,2700,2100,3200,200,*,UP,POLY +S 2000,3100,2000,4600,200,*,UP,POLY +S 1200,4000,1200,4000,400,b,LEFT,CALU1 +S 1200,3900,1200,4400,400,*,UP,ALU1 +S 2000,4400,2000,4900,400,*,UP,ALU1 +S 1200,4400,2000,4400,400,*,RIGHT,ALU1 +S 2100,1500,2100,1900,200,*,UP,POLY +S 400,5700,900,5700,400,*,RIGHT,ALU1 +S 2000,4600,2000,6600,200,t01,UP,PTRANS +S 1300,4600,1300,6600,200,t03,UP,PTRANS +S 1600,4800,1600,6400,400,n1,UP,PDIF +S 1200,2200,1200,3100,400,*,UP,ALU1 +S 500,400,500,2300,400,*,UP,ALU1 +S 2700,400,2700,2300,400,*,UP,ALU1 +S 2100,1900,2100,2500,200,t02,UP,NTRANS +S 1100,1900,1100,2500,200,t04,UP,NTRANS +S 1200,2200,1700,2200,400,*,RIGHT,ALU1 +S 1100,1500,1100,1900,200,*,UP,POLY +S 600,600,2600,600,600,*,RIGHT,PTIE +S 400,3200,400,5600,400,z,UP,CALU1 +S 400,3100,400,5700,400,*,UP,ALU1 +S 400,3100,1200,3100,400,*,RIGHT,ALU1 +S 2800,3200,2800,4000,400,a,UP,CALU1 +S 2800,3100,2800,4100,400,*,UP,ALU1 +S 2700,4800,2700,6400,600,*,UP,PDIF +S 2000,4800,2000,4800,400,b,LEFT,CALU1 +S 2000,3200,2800,3200,600,*,RIGHT,ALU1 +S 2000,3200,2000,3200,400,a,LEFT,CALU1 +S 1200,2400,1200,2400,400,z,LEFT,CALU1 +S 1100,2600,1100,3800,200,*,UP,POLY +S 0,6800,3200,6800,800,vdd,RIGHT,CALU1 +S 0,6800,3200,6800,800,*,RIGHT,ALU1 +S 0,5400,3200,5400,4400,*,RIGHT,NWELL +S 0,400,3200,400,800,vss,RIGHT,CALU1 +S 0,400,3200,400,800,*,RIGHT,ALU1 +S 2700,5500,2700,6800,400,*,UP,ALU1 +V 800,5700,CONT_DIF_P,* +V 2700,2200,CONT_DIF_N,* +V 500,2200,CONT_DIF_N,* +V 1600,2200,CONT_DIF_N,* +V 600,600,CONT_BODY_P,* +V 2700,6300,CONT_DIF_P,* +V 2700,5600,CONT_DIF_P,* +V 2600,600,CONT_BODY_P,* +V 1200,4000,CONT_POLY,* +V 2200,3100,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr2v0x05.vbe b/pdks/symbolic/vsclib/cells/nr2v0x05.vbe new file mode 100755 index 000000000..5a2ea1487 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2v0x05.vbe @@ -0,0 +1,32 @@ +ENTITY nr2v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3840; + CONSTANT rdown_b_z : NATURAL := 3860; + CONSTANT rup_a_z : NATURAL := 5820; + CONSTANT rup_b_z : NATURAL := 5810; + CONSTANT tplh_a_z : NATURAL := 54; + CONSTANT tplh_b_z : NATURAL := 46; + CONSTANT tphl_b_z : NATURAL := 41; + CONSTANT tphl_a_z : NATURAL := 49; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2v0x05; + +ARCHITECTURE behaviour_data_flow OF nr2v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2v0x05" + SEVERITY WARNING; + z <= not ((a or b)) after 168 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr2v0x1.ap b/pdks/symbolic/vsclib/cells/nr2v0x1.ap new file mode 100755 index 000000000..308d237a2 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2v0x1.ap @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H nr2v0x1,P,22/ 6/2024,100 +A 0,0,3200,7200 +R 2000,4000,ref_ref,b_40 +R 2000,2400,ref_ref,a_24 +R 400,1600,ref_ref,z_16 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 2800,3200,ref_ref,a_32 +R 1200,3200,ref_ref,b_32 +R 1200,1600,ref_ref,z_16 +S 1700,1400,1700,2100,600,*,DOWN,NDIF +S 800,4900,800,5600,600,*,DOWN,PDIF +S 800,4900,800,5600,600,*,UP,ALU1 +S 2700,5500,2700,6800,400,*,UP,ALU1 +S 2000,3800,2000,6600,200,t01,UP,PTRANS +S 1300,3800,1300,6600,200,t03,UP,PTRANS +S 1600,4000,1600,6400,400,n1,UP,PDIF +S 2000,4000,2000,4000,400,b,LEFT,CALU1 +S 2000,3700,2000,4100,400,*,DOWN,ALU1 +S 1200,3200,1200,3200,400,b,LEFT,CALU1 +S 1200,3100,1200,3700,400,*,UP,ALU1 +S 1200,3700,2000,3700,400,*,RIGHT,ALU1 +S 1100,2000,1100,3300,200,*,UP,POLY +S 2800,3200,2800,3200,400,a,LEFT,CALU1 +S 2700,400,2700,1900,400,*,DOWN,ALU1 +S 2700,1700,2700,2100,600,*,UP,NDIF +S 1100,800,1100,1200,200,*,UP,POLY +S 1100,1200,1100,2000,200,t04,UP,NTRANS +S 2200,1500,2200,2300,200,t02,UP,NTRANS +S 400,1500,1700,1500,400,*,RIGHT,ALU1 +S 2700,4000,2700,6400,600,*,UP,PDIF +S 0,6800,3200,6800,800,vdd,RIGHT,CALU1 +S 0,6800,3200,6800,800,*,RIGHT,ALU1 +S 0,5400,3200,5400,4400,*,RIGHT,NWELL +S 0,400,3200,400,800,vss,RIGHT,CALU1 +S 0,400,3200,400,800,*,RIGHT,ALU1 +S 500,500,500,1800,600,*,UP,NDIF +S 2000,2400,2000,2400,400,a,LEFT,CALU1 +S 2000,2900,2800,2900,400,*,RIGHT,ALU1 +S 2800,2900,2800,3300,400,*,UP,ALU1 +S 2000,2300,2000,2900,400,*,UP,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 2000,3000,2000,3800,200,*,DOWN,POLY +S 400,1600,1200,1600,600,*,RIGHT,ALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 400,4900,900,4900,400,*,RIGHT,ALU1 +V 800,5600,CONT_DIF_P,* +V 2700,6300,CONT_DIF_P,* +V 2700,5600,CONT_DIF_P,* +V 2700,1800,CONT_DIF_N,* +V 1600,1500,CONT_DIF_N,* +V 500,600,CONT_DIF_N,* +V 1200,3200,CONT_POLY,* +V 2600,600,CONT_BODY_P,* +V 2200,2900,CONT_POLY,* +V 800,4900,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr2v0x1.vbe b/pdks/symbolic/vsclib/cells/nr2v0x1.vbe new file mode 100755 index 000000000..0ff531636 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2v0x1.vbe @@ -0,0 +1,32 @@ +ENTITY nr2v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 2880; + CONSTANT rdown_b_z : NATURAL := 2890; + CONSTANT rup_a_z : NATURAL := 4160; + CONSTANT rup_b_z : NATURAL := 4150; + CONSTANT tplh_a_z : NATURAL := 53; + CONSTANT tplh_b_z : NATURAL := 45; + CONSTANT tphl_b_z : NATURAL := 41; + CONSTANT tphl_a_z : NATURAL := 50; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2v0x1; + +ARCHITECTURE behaviour_data_flow OF nr2v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2v0x1" + SEVERITY WARNING; + z <= not ((a or b)) after 135 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr2v0x4.ap b/pdks/symbolic/vsclib/cells/nr2v0x4.ap new file mode 100755 index 000000000..46d73a48d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2v0x4.ap @@ -0,0 +1,141 @@ +V ALLIANCE : 6 +H nr2v0x4,P, 1/ 4/2007,1000 +A 0,0,80000,72000 +R 12000,16000,ref_ref,z_16 +R 12000,40000,ref_ref,z_40 +R 20000,16000,ref_ref,z_16 +R 20000,24000,ref_ref,a_24 +R 20000,40000,ref_ref,z_40 +R 28000,16000,ref_ref,z_16 +R 28000,24000,ref_ref,a_24 +R 28000,32000,ref_ref,b_32 +R 28000,48000,ref_ref,z_48 +R 36000,16000,ref_ref,z_16 +R 36000,24000,ref_ref,a_24 +R 36000,40000,ref_ref,b_40 +R 36000,48000,ref_ref,z_48 +R 4000,24000,ref_ref,z_24 +R 4000,32000,ref_ref,z_32 +R 4000,40000,ref_ref,z_40 +R 44000,24000,ref_ref,a_24 +R 44000,40000,ref_ref,b_40 +R 44000,48000,ref_ref,z_48 +R 52000,24000,ref_ref,a_24 +R 52000,32000,ref_ref,b_32 +R 52000,48000,ref_ref,z_48 +R 60000,24000,ref_ref,a_24 +R 60000,32000,ref_ref,b_32 +R 60000,40000,ref_ref,z_40 +R 68000,16000,ref_ref,a_16 +S 52000,9000,52000,22000,6000,*,UP,NDIF +S 51000,4000,51000,17000,6000,*,UP,ALU1 +S 4000,16000,42000,16000,4000,*,RIGHT,ALU1 +S 38000,24000,38000,31000,4000,*,DOWN,ALU1 +S 38000,28000,38000,34000,6000,*,UP,POLY +S 46000,28000,52000,28000,2000,*,RIGHT,POLY +S 46000,3000,46000,7000,2000,*,UP,POLY +S 36000,3000,36000,7000,2000,*,UP,POLY +S 46000,7000,46000,24000,2000,t06,UP,NTRANS +S 36000,7000,36000,24000,2000,t12,UP,NTRANS +S 53000,28000,53000,34000,6000,*,UP,POLY +S 15000,24000,68000,24000,4000,*,RIGHT,ALU1 +S 15000,24000,15000,27000,4000,*,DOWN,ALU1 +S 10000,28000,15000,28000,2000,*,RIGHT,POLY +S 10000,28000,10000,38000,2000,*,UP,POLY +S 0,4000,80000,4000,8000,*,RIGHT,ALU1 +S 0,4000,80000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,80000,54000,44000,*,RIGHT,NWELL +S 0,68000,80000,68000,8000,*,RIGHT,ALU1 +S 0,68000,80000,68000,8000,vdd,RIGHT,CALU1 +S 10000,38000,10000,66000,2000,t01,UP,PTRANS +S 12000,16000,12000,16000,4000,z,LEFT,CALU1 +S 12000,40000,12000,40000,4000,z,LEFT,CALU1 +S 14000,3000,14000,7000,2000,*,UP,POLY +S 14000,40000,14000,64000,4000,n1a,UP,PDIF +S 14000,7000,14000,20000,2000,t05,UP,NTRANS +S 17000,34000,27000,34000,2000,*,RIGHT,POLY +S 17000,38000,17000,66000,2000,t07,UP,PTRANS +S 20000,16000,20000,16000,4000,z,LEFT,CALU1 +S 20000,24000,20000,24000,4000,a,LEFT,CALU1 +S 20000,40000,20000,40000,4000,z,LEFT,CALU1 +S 24000,20000,24000,34000,2000,*,UP,POLY +S 24000,3000,24000,7000,2000,*,UP,POLY +S 24000,32000,30000,32000,4000,*,RIGHT,ALU1 +S 24000,7000,24000,20000,2000,t11,UP,NTRANS +S 27000,38000,27000,66000,2000,t08,UP,PTRANS +S 28000,16000,28000,16000,4000,z,LEFT,CALU1 +S 28000,24000,28000,24000,4000,a,LEFT,CALU1 +S 28000,32000,28000,32000,4000,b,LEFT,CALU1 +S 28000,48000,28000,48000,4000,z,LEFT,CALU1 +S 30000,32000,30000,40000,4000,*,UP,ALU1 +S 30000,40000,48000,40000,4000,*,RIGHT,ALU1 +S 30000,5000,30000,22000,6000,*,UP,NDIF +S 31000,40000,31000,64000,4000,n1b,UP,PDIF +S 34000,34000,44000,34000,2000,*,RIGHT,POLY +S 34000,38000,34000,66000,2000,t02,UP,PTRANS +S 36000,16000,36000,16000,4000,z,LEFT,CALU1 +S 36000,24000,36000,24000,4000,a,LEFT,CALU1 +S 36000,40000,36000,40000,4000,b,LEFT,CALU1 +S 36000,48000,36000,48000,4000,z,LEFT,CALU1 +S 39000,56000,39000,68000,6000,*,UP,ALU1 +S 4000,16000,4000,41000,4000,*,UP,ALU1 +S 4000,24000,4000,40000,4000,z,UP,CALU1 +S 4000,40000,22000,40000,4000,*,RIGHT,ALU1 +S 4000,41000,22000,41000,4000,*,RIGHT,ALU1 +S 44000,24000,44000,24000,4000,a,LEFT,CALU1 +S 44000,38000,44000,66000,2000,t03,UP,PTRANS +S 44000,40000,44000,40000,4000,b,LEFT,CALU1 +S 44000,48000,44000,48000,4000,z,LEFT,CALU1 +S 47000,40000,47000,64000,4000,n1c,UP,PDIF +S 48000,32000,48000,40000,4000,*,UP,ALU1 +S 48000,32000,61000,32000,4000,*,RIGHT,ALU1 +S 5000,40000,5000,64000,6000,*,UP,PDIF +S 5000,56000,5000,68000,6000,*,UP,ALU1 +S 51000,34000,61000,34000,2000,*,RIGHT,POLY +S 51000,38000,51000,66000,2000,t09,UP,PTRANS +S 52000,24000,52000,24000,4000,a,LEFT,CALU1 +S 52000,32000,52000,32000,4000,b,LEFT,CALU1 +S 52000,48000,52000,48000,4000,z,LEFT,CALU1 +S 56000,40000,56000,48000,4000,*,UP,ALU1 +S 56000,40000,61000,40000,4000,*,RIGHT,ALU1 +S 57000,40000,57000,48000,4000,*,UP,ALU1 +S 60000,24000,60000,24000,4000,a,LEFT,CALU1 +S 60000,32000,60000,32000,4000,b,LEFT,CALU1 +S 60000,40000,60000,40000,4000,z,LEFT,CALU1 +S 61000,38000,61000,66000,2000,t10,UP,PTRANS +S 65000,40000,65000,64000,4000,n1d,UP,PDIF +S 68000,15000,68000,24000,4000,*,UP,ALU1 +S 68000,16000,68000,16000,4000,a,LEFT,CALU1 +S 68000,24000,68000,38000,2000,*,UP,POLY +S 68000,38000,68000,66000,2000,t04,UP,PTRANS +S 68000,5000,68000,16000,14000,*,UP,PTIE +S 7000,5000,7000,18000,6000,*,UP,NDIF +S 73000,56000,73000,68000,6000,*,UP,ALU1 +S 22000,40000,22000,48000,4000,*,UP,ALU1 +S 21000,40000,21000,48000,4000,*,UP,ALU1 +S 21000,48000,57000,48000,4000,*,RIGHT,ALU1 +S 74000,40000,74000,64000,6000,*,UP,PDIF +V 51000,10000,CONT_DIF_N,* +V 51000,17000,CONT_DIF_N,* +V 41000,16000,CONT_DIF_N,* +V 38000,30000,CONT_POLY,* +V 53000,32000,CONT_POLY,* +V 15000,26000,CONT_POLY,* +V 19000,16000,CONT_DIF_N,* +V 25000,32000,CONT_POLY,* +V 30000,6000,CONT_DIF_N,* +V 39000,56000,CONT_DIF_P,* +V 39000,63000,CONT_DIF_P,* +V 5000,56000,CONT_DIF_P,* +V 5000,63000,CONT_DIF_P,* +V 56000,41000,CONT_DIF_P,* +V 56000,48000,CONT_DIF_P,* +V 64000,6000,CONT_BODY_P,* +V 66000,24000,CONT_POLY,* +V 72000,6000,CONT_BODY_P,* +V 73000,56000,CONT_DIF_P,* +V 73000,63000,CONT_DIF_P,* +V 8000,6000,CONT_DIF_N,* +V 22000,41000,CONT_DIF_P,* +V 22000,48000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr2v0x4.vbe b/pdks/symbolic/vsclib/cells/nr2v0x4.vbe new file mode 100755 index 000000000..e70aa1315 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2v0x4.vbe @@ -0,0 +1,32 @@ +ENTITY nr2v0x4 IS +GENERIC ( + CONSTANT area : NATURAL := 5760; + CONSTANT cin_a : NATURAL := 17; + CONSTANT cin_b : NATURAL := 16; + CONSTANT rdown_a_z : NATURAL := 770; + CONSTANT rdown_b_z : NATURAL := 770; + CONSTANT rup_a_z : NATURAL := 1040; + CONSTANT rup_b_z : NATURAL := 1040; + CONSTANT tplh_a_z : NATURAL := 50; + CONSTANT tplh_b_z : NATURAL := 41; + CONSTANT tphl_b_z : NATURAL := 39; + CONSTANT tphl_a_z : NATURAL := 49; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2v0x4; + +ARCHITECTURE behaviour_data_flow OF nr2v0x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2v0x4" + SEVERITY WARNING; + z <= not ((a or b)) after 67 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr2v1x05.ap b/pdks/symbolic/vsclib/cells/nr2v1x05.ap new file mode 100755 index 000000000..823be0f6b --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2v1x05.ap @@ -0,0 +1,63 @@ +V ALLIANCE : 6 +H nr2v1x05,P, 1/ 4/2007,1000 +A 0,0,32000,72000 +R 12000,24000,ref_ref,z_24 +R 12000,40000,ref_ref,b_40 +R 20000,32000,ref_ref,a_32 +R 20000,48000,ref_ref,b_48 +R 28000,32000,ref_ref,a_32 +R 28000,40000,ref_ref,a_40 +R 4000,32000,ref_ref,z_32 +R 4000,40000,ref_ref,z_40 +R 4000,48000,ref_ref,z_48 +R 4000,56000,ref_ref,z_56 +S 0,4000,32000,4000,8000,*,RIGHT,ALU1 +S 0,4000,32000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,32000,54000,44000,*,RIGHT,NWELL +S 0,68000,32000,68000,8000,*,RIGHT,ALU1 +S 0,68000,32000,68000,8000,vdd,RIGHT,CALU1 +S 12000,24000,12000,24000,4000,z,LEFT,CALU1 +S 20000,32000,20000,32000,4000,a,LEFT,CALU1 +S 20000,32000,28000,32000,6000,*,RIGHT,ALU1 +S 20000,48000,20000,48000,4000,b,LEFT,CALU1 +S 28000,31000,28000,41000,4000,*,UP,ALU1 +S 28000,32000,28000,40000,4000,a,UP,CALU1 +S 4000,32000,4000,56000,4000,z,UP,CALU1 +S 6000,6000,26000,6000,6000,*,RIGHT,PTIE +S 12000,40000,12000,40000,4000,b,LEFT,CALU1 +S 5000,17000,5000,20000,6000,*,UP,NDIF +S 11000,15000,11000,22000,2000,t04,UP,NTRANS +S 27000,17000,27000,20000,6000,*,UP,NDIF +S 21000,15000,21000,22000,2000,t02,UP,NTRANS +S 12000,19000,17000,19000,4000,*,RIGHT,ALU1 +S 4000,27000,12000,27000,4000,*,RIGHT,ALU1 +S 12000,19000,12000,27000,4000,*,UP,ALU1 +S 4000,27000,4000,57000,4000,*,UP,ALU1 +S 12000,41000,20000,41000,4000,*,RIGHT,ALU1 +S 12000,35000,12000,41000,4000,*,UP,ALU1 +S 20000,41000,20000,49000,4000,*,UP,ALU1 +S 16000,44000,16000,55000,4000,n1,UP,PDIF +S 20000,42000,20000,57000,2000,t01,UP,PTRANS +S 13000,42000,13000,57000,2000,t03,UP,PTRANS +S 4000,54000,9000,54000,4000,*,LEFT,ALU1 +S 20000,57000,20000,61000,2000,*,UP,POLY +S 27000,44000,27000,55000,6000,*,UP,PDIF +S 21000,22000,21000,31000,2000,*,UP,POLY +S 27000,4000,27000,19000,4000,*,UP,ALU1 +S 5000,4000,5000,19000,4000,*,UP,ALU1 +S 27000,53000,27000,68000,4000,*,UP,ALU1 +S 6000,66000,14000,66000,6000,*,LEFT,NTIE +S 20000,33000,20000,42000,2000,*,UP,POLY +S 11000,22000,11000,36000,2000,*,UP,POLY +V 22000,33000,CONT_POLY,* +V 26000,6000,CONT_BODY_P,* +V 6000,6000,CONT_BODY_P,* +V 5000,18000,CONT_DIF_N,* +V 27000,18000,CONT_DIF_N,* +V 16000,19000,CONT_DIF_N,* +V 12000,36000,CONT_POLY,* +V 8000,54000,CONT_DIF_P,* +V 27000,54000,CONT_DIF_P,* +V 6000,66000,CONT_BODY_N,* +V 14000,66000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr2v1x05.vbe b/pdks/symbolic/vsclib/cells/nr2v1x05.vbe new file mode 100755 index 000000000..92be82c6f --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr2v1x05.vbe @@ -0,0 +1,32 @@ +ENTITY nr2v1x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2304; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 3330; + CONSTANT rdown_b_z : NATURAL := 3360; + CONSTANT rup_a_z : NATURAL := 7770; + CONSTANT rup_b_z : NATURAL := 7750; + CONSTANT tplh_a_z : NATURAL := 58; + CONSTANT tplh_b_z : NATURAL := 51; + CONSTANT tphl_b_z : NATURAL := 36; + CONSTANT tphl_a_z : NATURAL := 41; + CONSTANT transistors : NATURAL := 4 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr2v1x05; + +ARCHITECTURE behaviour_data_flow OF nr2v1x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr2v1x05" + SEVERITY WARNING; + z <= not ((a or b)) after 185 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr3abv0x05.ap b/pdks/symbolic/vsclib/cells/nr3abv0x05.ap new file mode 100755 index 000000000..de7f0b361 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3abv0x05.ap @@ -0,0 +1,97 @@ +V ALLIANCE : 6 +H nr3abv0x05,P,23/ 6/2024,100 +A 0,0,4800,7200 +R 3600,5600,ref_ref,b_56 +R 4400,5600,ref_ref,b_56 +R 4400,4800,ref_ref,b_48 +R 4400,4000,ref_ref,b_40 +R 2800,2400,ref_ref,a_24 +R 2800,3200,ref_ref,a_32 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 1200,4000,ref_ref,c_40 +R 1200,3200,ref_ref,c_32 +R 1200,1600,ref_ref,z_16 +R 400,5600,ref_ref,z_56 +R 400,1600,ref_ref,z_16 +R 2000,4800,ref_ref,c_48 +R 2000,2400,ref_ref,a_24 +S 1000,2900,1000,4500,200,*,DOWN,POLY +S 3500,5600,4400,5600,400,*,LEFT,ALU1 +S 3500,5700,4400,5700,400,*,LEFT,ALU1 +S 3100,2200,3100,2800,200,*,UP,POLY +S 3800,2200,3800,4200,200,*,DOWN,POLY +S 2100,1800,2100,3800,200,*,UP,POLY +S 1100,1800,1100,2900,200,*,UP,POLY +S 2200,5600,2200,6800,600,*,UP,ALU1 +S 3600,5600,3600,5600,400,b,LEFT,CALU1 +S 4400,4000,4400,5600,400,b,UP,CALU1 +S 2800,2400,2800,3200,400,a,UP,CALU1 +S 0,400,4800,400,800,vss,RIGHT,CALU1 +S 0,400,4800,400,800,*,RIGHT,ALU1 +S 0,6800,4800,6800,800,vdd,RIGHT,CALU1 +S 0,6800,4800,6800,800,*,RIGHT,ALU1 +S 400,1500,400,5700,400,*,UP,ALU1 +S 400,1500,1700,1500,400,*,LEFT,ALU1 +S 3800,3900,4300,3900,600,*,LEFT,POLY +S 1200,4800,2100,4800,400,*,RIGHT,ALU1 +S 1200,2800,1200,4800,400,*,UP,ALU1 +S 1700,3900,2000,3900,600,*,LEFT,POLY +S 2800,4500,2800,5700,200,t03,UP,PTRANS +S 3800,4500,3800,5700,200,t01,UP,PTRANS +S 1000,4500,1000,6500,200,t07,UP,PTRANS +S 1700,4500,1700,6500,200,t05,UP,PTRANS +S 500,4800,500,5500,600,*,DOWN,PDIF +S 2200,4700,2200,6300,600,*,DOWN,PDIF +S 4300,4700,4300,6700,400,*,DOWN,PDIF +S 4400,4700,4400,6700,400,*,DOWN,PDIF +S 1700,6500,1700,6900,200,*,UP,POLY +S 1000,6500,1000,6900,200,*,UP,POLY +S 4400,3800,4400,5700,400,*,UP,ALU1 +S 4300,3900,4400,3900,600,*,RIGHT,ALU1 +S 2800,3000,2800,4500,200,*,DOWN,POLY +S 1300,4700,1300,6300,400,n2,UP,PDIF +S 3300,3900,3300,4900,400,*,DOWN,ALU1 +S 1900,3900,3600,3900,400,*,RIGHT,ALU1 +S 500,4800,500,5600,400,*,DOWN,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,3200,1200,4000,400,c,UP,CALU1 +S 2000,4800,2000,4800,400,c,LEFT,CALU1 +S 0,5400,4800,5400,4400,*,RIGHT,NWELL +S 2000,2400,2000,2400,400,a,LEFT,CALU1 +S 2800,2300,2800,3200,600,*,DOWN,ALU1 +S 2000,2400,2900,2400,600,*,RIGHT,ALU1 +S 2600,1400,2600,2000,400,*,UP,NDIF +S 3100,1200,3100,2200,200,t04,UP,NTRANS +S 2100,1200,2100,1800,200,t06,UP,NTRANS +S 1100,1200,1100,1800,200,t08,UP,NTRANS +S 500,500,500,1600,600,*,UP,NDIF +S 3800,1200,3800,2200,200,t02,UP,NTRANS +S 3600,3000,4300,3000,400,*,LEFT,ALU1 +S 3600,3000,3600,3900,400,*,DOWN,ALU1 +S 4300,1800,4300,3000,400,*,UP,ALU1 +S 3400,1400,3400,2000,400,n1,UP,NDIF +S 2600,400,2600,1500,600,*,DOWN,ALU1 +S 400,1600,1200,1600,600,*,LEFT,ALU1 +S 1100,800,1100,1200,200,*,DOWN,POLY +S 2100,800,2100,1200,200,*,DOWN,POLY +S 3100,800,3100,1200,200,*,DOWN,POLY +S 3800,800,3800,1200,200,*,DOWN,POLY +V 2200,5600,CONT_DIF_P,* +V 500,600,CONT_DIF_N,* +V 4300,3900,CONT_POLY,* +V 1200,2900,CONT_POLY,* +V 500,4800,CONT_DIF_P,* +V 500,5500,CONT_DIF_P,* +V 3300,6600,CONT_BODY_N,* +V 4300,6600,CONT_DIF_P,* +V 3300,4800,CONT_DIF_P,nd +V 2000,3900,CONT_POLY,nd +V 2900,2900,CONT_POLY,* +V 2600,1500,CONT_DIF_N,* +V 1600,1500,CONT_DIF_N,* +V 4300,1900,CONT_DIF_N,nd +EOF diff --git a/pdks/symbolic/vsclib/cells/nr3abv0x05.vbe b/pdks/symbolic/vsclib/cells/nr3abv0x05.vbe new file mode 100755 index 000000000..6f10480bf --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3abv0x05.vbe @@ -0,0 +1,38 @@ +ENTITY nr3abv0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 3456; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 4; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 3880; + CONSTANT rdown_c_z : NATURAL := 3860; + CONSTANT rdown_a_z : NATURAL := 3890; + CONSTANT rup_b_z : NATURAL := 5830; + CONSTANT rup_c_z : NATURAL := 5810; + CONSTANT rup_a_z : NATURAL := 5830; + CONSTANT tphh_a_z : NATURAL := 90; + CONSTANT tphl_c_z : NATURAL := 42; + CONSTANT tplh_c_z : NATURAL := 47; + CONSTANT tphh_b_z : NATURAL := 90; + CONSTANT tpll_b_z : NATURAL := 106; + CONSTANT tpll_a_z : NATURAL := 115; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr3abv0x05; + +ARCHITECTURE behaviour_data_flow OF nr3abv0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr3abv0x05" + SEVERITY WARNING; + z <= not ((not a or not b) or c) after 203 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr3av0x05.ap b/pdks/symbolic/vsclib/cells/nr3av0x05.ap new file mode 100755 index 000000000..d9ece0ff2 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3av0x05.ap @@ -0,0 +1,95 @@ +V ALLIANCE : 6 +H nr3av0x05,P,23/ 6/2024,100 +A 0,0,5600,7200 +R 3600,4800,ref_ref,a_48 +R 400,1600,ref_ref,z_16 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,c_32 +R 1200,4000,ref_ref,c_40 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,4000,ref_ref,a_40 +R 2000,2400,ref_ref,b_24 +R 2800,3200,ref_ref,b_32 +R 2800,2400,ref_ref,b_24 +R 2000,4000,ref_ref,c_40 +R 3600,4000,ref_ref,a_40 +S 4600,2000,4600,4400,200,*,UP,POLY +S 3900,1400,3900,1800,600,*,UP,NDIF +S 4600,800,4600,1200,200,*,DOWN,POLY +S 4600,1200,4600,2000,200,t08,UP,NTRANS +S 4600,6200,4600,6600,200,*,UP,POLY +S 5100,4800,5100,5700,400,*,DOWN,ALU1 +S 5100,4900,5100,5600,600,*,DOWN,PDIF +S 4600,4600,4600,6200,200,t07,UP,PTRANS +S 4400,4000,4400,4000,400,a,LEFT,CALU1 +S 3600,4000,3600,4800,400,a,UP,CALU1 +S 3600,3900,3600,4900,400,*,UP,ALU1 +S 1000,2100,1000,3100,200,*,UP,POLY +S 500,1500,500,1900,400,*,DOWN,ALU1 +S 1600,500,1600,1900,600,*,UP,NDIF +S 1000,1500,1000,2100,200,t06,UP,NTRANS +S 400,1600,1200,1600,600,*,LEFT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 400,1500,2900,1500,400,*,LEFT,ALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,3100,1200,4100,400,*,UP,ALU1 +S 1200,3200,1200,4000,400,c,UP,CALU1 +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 2000,2400,2000,2400,400,b,LEFT,CALU1 +S 2000,2400,2800,2400,600,*,RIGHT,ALU1 +S 2800,2300,2800,3300,400,*,UP,ALU1 +S 1200,4000,2000,4000,600,*,RIGHT,ALU1 +S 2000,4000,2000,4000,400,c,LEFT,CALU1 +S 3600,4000,4400,4000,600,*,LEFT,ALU1 +S 2800,2400,2800,3200,400,b,UP,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 1000,1600,1000,2000,200,*,DOWN,POLY +S 3300,1200,3300,1800,200,t02,UP,NTRANS +S 2300,1200,2300,1800,200,t04,UP,NTRANS +S 2300,1800,2300,2500,200,*,DOWN,POLY +S 2300,800,2300,1200,200,*,DOWN,POLY +S 3300,800,3300,1200,200,*,DOWN,POLY +S 3300,1800,3300,2500,200,*,UP,POLY +S 4000,400,4000,1500,600,*,DOWN,ALU1 +S 4000,5600,4000,6800,600,*,UP,ALU1 +S 1400,4900,1400,5700,600,*,UP,PDIF +S 1900,3800,1900,6600,200,t05,UP,PTRANS +S 1300,3400,1900,3400,200,*,LEFT,POLY +S 2300,4000,2300,6400,400,n2,UP,PDIF +S 2600,3800,2600,6600,200,t03,UP,PTRANS +S 3000,4000,3000,6400,400,n1,UP,PDIF +S 3300,3800,3300,6600,200,t01,UP,PTRANS +S 2600,2500,2600,3800,200,*,DOWN,POLY +S 3300,2700,3300,3800,200,*,DOWN,POLY +S 1400,4900,1400,5600,600,*,UP,ALU1 +S 400,4900,1500,4900,400,*,RIGHT,ALU1 +S 4000,4800,4000,6400,600,*,DOWN,PDIF +S 3600,2600,5200,2600,400,*,RIGHT,ALU1 +S 3300,2600,3900,2600,600,*,LEFT,POLY +S 5100,1600,5100,2600,400,*,UP,ALU1 +S 5200,2600,5200,5700,400,*,UP,ALU1 +V 5100,1700,CONT_DIF_N,an +V 5100,5600,CONT_DIF_P,an +V 5100,4900,CONT_DIF_P,an +V 4400,4000,CONT_POLY,* +V 500,1800,CONT_DIF_N,* +V 600,6600,CONT_BODY_N,* +V 1200,3200,CONT_POLY,* +V 600,600,CONT_BODY_P,* +V 4000,1500,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 2500,2500,CONT_POLY,* +V 2800,1500,CONT_DIF_N,* +V 4000,6300,CONT_DIF_P,* +V 4000,5600,CONT_DIF_P,* +V 1400,5600,CONT_DIF_P,* +V 1400,4900,CONT_DIF_P,* +V 3700,2600,CONT_POLY,an +EOF diff --git a/pdks/symbolic/vsclib/cells/nr3av0x05.vbe b/pdks/symbolic/vsclib/cells/nr3av0x05.vbe new file mode 100755 index 000000000..f286873af --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3av0x05.vbe @@ -0,0 +1,38 @@ +ENTITY nr3av0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 4; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 3880; + CONSTANT rdown_c_z : NATURAL := 3870; + CONSTANT rdown_a_z : NATURAL := 4000; + CONSTANT rup_b_z : NATURAL := 6260; + CONSTANT rup_c_z : NATURAL := 6240; + CONSTANT rup_a_z : NATURAL := 6250; + CONSTANT tphh_a_z : NATURAL := 111; + CONSTANT tphl_c_z : NATURAL := 50; + CONSTANT tplh_c_z : NATURAL := 53; + CONSTANT tplh_b_z : NATURAL := 74; + CONSTANT tphl_b_z : NATURAL := 62; + CONSTANT tpll_a_z : NATURAL := 112; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr3av0x05; + +ARCHITECTURE behaviour_data_flow OF nr3av0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr3av0x05" + SEVERITY WARNING; + z <= not ((not a or b) or c) after 204 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr3v0x05.ap b/pdks/symbolic/vsclib/cells/nr3v0x05.ap new file mode 100755 index 000000000..93e1d1a14 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3v0x05.ap @@ -0,0 +1,82 @@ +V ALLIANCE : 6 +H nr3v0x05,P,23/ 6/2024,100 +A 0,0,4000,7200 +R 2000,1600,ref_ref,z_16 +R 1200,1600,ref_ref,z_16 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 3600,4000,ref_ref,a_40 +R 2800,2400,ref_ref,b_24 +R 2000,4800,ref_ref,c_48 +R 2000,3200,ref_ref,b_32 +R 1200,4000,ref_ref,c_40 +R 1200,3200,ref_ref,c_32 +R 3600,4800,ref_ref,a_48 +R 2800,4000,ref_ref,a_40 +S 500,900,500,1500,600,*,DOWN,NDIF +S 2500,1000,2500,1600,600,*,DOWN,NDIF +S 2000,2400,2900,2400,400,*,LEFT,ALU1 +S 400,1600,400,1900,400,*,DOWN,ALU1 +S 3000,1400,3000,3300,200,*,UP,POLY +S 2000,1500,2000,3800,200,*,UP,POLY +S 1000,1500,1000,3200,200,*,UP,POLY +S 3500,400,3500,1100,600,*,UP,ALU1 +S 1500,900,1500,1100,400,*,UP,NDIF +S 3000,700,3000,1300,200,t02,UP,NTRANS +S 2000,700,2000,1300,200,t04,UP,NTRANS +S 1000,700,1000,1300,200,t06,UP,NTRANS +S 2000,2800,2000,3300,400,*,DOWN,ALU1 +S 2000,2800,2200,2800,400,*,LEFT,ALU1 +S 2200,2400,2200,2800,400,*,UP,ALU1 +S 3000,900,3000,1300,200,*,UP,POLY +S 2000,900,2000,1300,200,*,UP,POLY +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 400,1600,400,4900,400,*,UP,ALU1 +S 400,1600,2600,1600,400,*,LEFT,ALU1 +S 400,4900,900,4900,400,*,RIGHT,ALU1 +S 2700,3400,3000,3400,200,*,RIGHT,POLY +S 2700,3800,2700,6600,200,t01,UP,PTRANS +S 2300,4000,2300,6400,400,n1,UP,PDIF +S 2000,3800,2000,6600,200,t03,UP,PTRANS +S 1700,4000,1700,6400,400,n2,UP,PDIF +S 1300,3800,1300,6600,200,t05,UP,PTRANS +S 800,4900,800,5700,600,*,UP,PDIF +S 800,4900,800,5600,600,*,UP,ALU1 +S 3500,4000,3500,6400,600,*,UP,PDIF +S 3000,3200,3500,3200,600,*,RIGHT,POLY +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 0,5400,4000,5400,4400,*,RIGHT,NWELL +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 0,6800,4000,6800,800,*,RIGHT,ALU1 +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,400,4000,400,800,*,RIGHT,ALU1 +S 2800,2400,2800,2400,400,b,LEFT,CALU1 +S 2000,3200,2000,3200,400,b,LEFT,CALU1 +S 1200,3100,1200,4100,400,*,UP,ALU1 +S 1200,4100,2000,4100,400,*,RIGHT,ALU1 +S 2000,4100,2000,4900,400,*,UP,ALU1 +S 2000,4800,2000,4800,400,c,LEFT,CALU1 +S 1200,3200,1200,4000,400,c,UP,CALU1 +S 2800,4000,2800,4000,400,a,LEFT,CALU1 +S 3600,4000,3600,4800,400,a,UP,CALU1 +S 2800,4000,3600,4000,600,*,RIGHT,ALU1 +S 3500,3100,3500,4100,400,*,UP,ALU1 +S 3600,3900,3600,4900,400,*,UP,ALU1 +S 3500,5600,3500,6800,600,*,UP,ALU1 +V 500,1600,CONT_DIF_N,* +V 1500,900,CONT_DIF_N,* +V 3500,1000,CONT_DIF_N,* +V 2500,1600,CONT_DIF_N,* +V 800,4900,CONT_DIF_P,* +V 800,5600,CONT_DIF_P,* +V 3500,3200,CONT_POLY,* +V 3500,6300,CONT_DIF_P,* +V 3500,5600,CONT_DIF_P,* +V 1200,3200,CONT_POLY,* +V 2200,2600,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr3v0x05.vbe b/pdks/symbolic/vsclib/cells/nr3v0x05.vbe new file mode 100755 index 000000000..1edba5b44 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3v0x05.vbe @@ -0,0 +1,38 @@ +ENTITY nr3v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 4; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 3880; + CONSTANT rdown_c_z : NATURAL := 3880; + CONSTANT rdown_a_z : NATURAL := 3980; + CONSTANT rup_b_z : NATURAL := 6260; + CONSTANT rup_c_z : NATURAL := 6240; + CONSTANT rup_a_z : NATURAL := 6250; + CONSTANT tplh_a_z : NATURAL := 81; + CONSTANT tphl_c_z : NATURAL := 49; + CONSTANT tplh_c_z : NATURAL := 52; + CONSTANT tplh_b_z : NATURAL := 73; + CONSTANT tphl_b_z : NATURAL := 61; + CONSTANT tphl_a_z : NATURAL := 67; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr3v0x05; + +ARCHITECTURE behaviour_data_flow OF nr3v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr3v0x05" + SEVERITY WARNING; + z <= not (((b or c) or a)) after 191 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr3v0x1.ap b/pdks/symbolic/vsclib/cells/nr3v0x1.ap new file mode 100755 index 000000000..d6bf94ab5 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3v0x1.ap @@ -0,0 +1,115 @@ +V ALLIANCE : 6 +H nr3v0x1,P,22/ 6/2024,100 +A 0,0,6400,7200 +R 1200,2400,ref_ref,a_24 +R 1200,3200,ref_ref,a_32 +R 1200,4800,ref_ref,z_48 +R 2000,2400,ref_ref,b_24 +R 2000,4000,ref_ref,a_40 +R 2000,4800,ref_ref,z_48 +R 2800,3200,ref_ref,b_32 +R 2800,4000,ref_ref,a_40 +R 2800,4800,ref_ref,z_48 +R 3600,1600,ref_ref,c_16 +R 3600,2400,ref_ref,c_24 +R 3600,3200,ref_ref,b_32 +R 3600,4000,ref_ref,a_40 +R 3600,4800,ref_ref,z_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 4400,1600,ref_ref,c_16 +R 4400,3200,ref_ref,b_32 +R 4400,4000,ref_ref,a_40 +R 5200,2400,ref_ref,b_24 +R 5200,4000,ref_ref,a_40 +S 3200,2000,3200,2500,200,*,UP,POLY +S 1000,2000,1000,2500,200,*,UP,POLY +S 0,400,6400,400,800,*,RIGHT,ALU1 +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 1000,400,1000,800,200,*,UP,POLY +S 1000,800,1000,1800,200,t03,UP,NTRANS +S 1200,2300,1200,4000,400,*,UP,ALU1 +S 1200,2400,1200,3200,400,a,UP,CALU1 +S 1200,2400,1200,3800,200,*,UP,POLY +S 1200,3800,1200,6600,200,t01,UP,PTRANS +S 1200,4000,5300,4000,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1500,4000,1500,6400,400,n1a,UP,PDIF +S 1600,500,1600,1600,600,*,UP,NDIF +S 1900,3300,1900,3800,200,*,UP,POLY +S 1900,3800,1900,6600,200,t04,UP,PTRANS +S 2000,2400,2000,2400,400,b,LEFT,CALU1 +S 2000,2400,2000,3400,200,*,UP,POLY +S 2000,3200,4500,3200,400,*,RIGHT,ALU1 +S 2000,4000,2000,4000,400,a,LEFT,CALU1 +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2100,2300,2100,3200,600,*,UP,ALU1 +S 2200,4000,2200,6400,400,n2a,UP,PDIF +S 2200,400,2200,800,200,*,UP,POLY +S 2200,800,2200,1800,200,t06,UP,NTRANS +S 2600,3400,3600,3400,200,*,RIGHT,POLY +S 2600,3800,2600,6600,200,t07,UP,PTRANS +S 2800,3200,2800,3200,400,b,LEFT,CALU1 +S 2800,4000,2800,4000,400,a,LEFT,CALU1 +S 2800,4800,2800,4800,400,z,LEFT,CALU1 +S 3100,4800,3100,5700,400,*,UP,ALU1 +S 3200,400,3200,800,200,*,UP,POLY +S 3200,800,3200,1800,200,t09,UP,NTRANS +S 3300,2400,3700,2400,400,*,RIGHT,ALU1 +S 3600,1500,3600,2400,400,*,UP,ALU1 +S 3600,1500,4500,1500,400,*,RIGHT,ALU1 +S 3600,1600,3600,2400,400,c,UP,CALU1 +S 3600,1600,4500,1600,400,*,RIGHT,ALU1 +S 3600,2400,3600,3400,200,*,UP,POLY +S 3600,3200,3600,3200,400,b,LEFT,CALU1 +S 3600,3800,3600,6600,200,t08,UP,PTRANS +S 3600,4000,3600,4000,400,a,LEFT,CALU1 +S 3600,4800,3600,4800,400,z,LEFT,CALU1 +S 3700,1500,3700,2400,400,*,UP,ALU1 +S 3900,4000,3900,6400,400,n2b,UP,PDIF +S 3900,500,3900,1600,600,*,UP,NDIF +S 400,1500,2800,1500,400,*,RIGHT,ALU1 +S 400,1500,400,4800,400,*,UP,ALU1 +S 400,1600,400,4000,400,z,UP,CALU1 +S 400,4800,3700,4800,400,*,RIGHT,ALU1 +S 4300,2600,4300,3800,200,*,UP,POLY +S 4300,3800,4300,6600,200,t05,UP,PTRANS +S 4400,1600,4400,1600,400,c,LEFT,CALU1 +S 4400,3200,4400,3200,400,b,LEFT,CALU1 +S 4400,4000,4400,4000,400,a,LEFT,CALU1 +S 4500,2400,4500,3200,400,*,UP,ALU1 +S 4500,2400,5300,2400,400,*,RIGHT,ALU1 +S 4600,4000,4600,6400,400,n1b,UP,PDIF +S 5000,3400,5500,3400,200,*,RIGHT,POLY +S 5000,3800,5000,6600,200,t02,UP,PTRANS +S 5200,2400,5200,2400,400,b,LEFT,CALU1 +S 5200,4000,5200,4000,400,a,LEFT,CALU1 +S 5300,3200,5300,4000,400,*,UP,ALU1 +S 5300,3200,5600,3200,400,*,RIGHT,ALU1 +S 5400,500,5400,2200,600,*,UP,PTIE +S 5500,4000,5500,6400,600,*,UP,PDIF +S 5500,5600,5500,6800,600,*,UP,ALU1 +S 700,4000,700,6400,600,*,UP,PDIF +S 700,5600,700,6800,600,*,UP,ALU1 +V 1200,2400,CONT_POLY,* +V 1600,600,CONT_DIF_N,* +V 2200,2400,CONT_POLY,* +V 2700,1500,CONT_DIF_N,* +V 3100,4900,CONT_DIF_P,* +V 3100,5600,CONT_DIF_P,* +V 3400,2400,CONT_POLY,* +V 3800,600,CONT_DIF_N,* +V 4500,2600,CONT_POLY,* +V 500,1500,CONT_DIF_N,* +V 5400,600,CONT_BODY_P,* +V 5500,3200,CONT_POLY,* +V 5500,5600,CONT_DIF_P,* +V 5500,6300,CONT_DIF_P,* +V 700,5600,CONT_DIF_P,* +V 700,6300,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr3v0x1.vbe b/pdks/symbolic/vsclib/cells/nr3v0x1.vbe new file mode 100755 index 000000000..c30f87e7a --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3v0x1.vbe @@ -0,0 +1,38 @@ +ENTITY nr3v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_b : NATURAL := 8; + CONSTANT cin_c : NATURAL := 7; + CONSTANT cin_a : NATURAL := 9; + CONSTANT rdown_b_z : NATURAL := 2330; + CONSTANT rdown_c_z : NATURAL := 2320; + CONSTANT rdown_a_z : NATURAL := 2390; + CONSTANT rup_b_z : NATURAL := 3130; + CONSTANT rup_c_z : NATURAL := 3120; + CONSTANT rup_a_z : NATURAL := 3140; + CONSTANT tplh_a_z : NATURAL := 77; + CONSTANT tphl_c_z : NATURAL := 48; + CONSTANT tplh_c_z : NATURAL := 45; + CONSTANT tplh_b_z : NATURAL := 67; + CONSTANT tphl_b_z : NATURAL := 64; + CONSTANT tphl_a_z : NATURAL := 74; + CONSTANT transistors : NATURAL := 9 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr3v0x1; + +ARCHITECTURE behaviour_data_flow OF nr3v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr3v0x1" + SEVERITY WARNING; + z <= not (((b or c) or a)) after 131 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr3v0x2.ap b/pdks/symbolic/vsclib/cells/nr3v0x2.ap new file mode 100755 index 000000000..3b0821417 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3v0x2.ap @@ -0,0 +1,142 @@ +V ALLIANCE : 6 +H nr3v0x2,P,22/ 6/2024,100 +A 0,0,8800,7200 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,c_32 +R 1200,4800,ref_ref,z_48 +R 2000,1600,ref_ref,z_16 +R 2000,4000,ref_ref,c_40 +R 2000,4800,ref_ref,z_48 +R 2800,2400,ref_ref,b_24 +R 2800,4000,ref_ref,c_40 +R 2800,4800,ref_ref,z_48 +R 3600,2400,ref_ref,b_24 +R 3600,3200,ref_ref,a_32 +R 3600,4000,ref_ref,c_40 +R 3600,4800,ref_ref,z_48 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,1600,ref_ref,b_16 +R 4400,3200,ref_ref,a_32 +R 4400,4000,ref_ref,c_40 +R 4400,4800,ref_ref,z_48 +R 5200,1600,ref_ref,b_16 +R 5200,2400,ref_ref,a_24 +R 5200,4000,ref_ref,c_40 +R 5200,4800,ref_ref,z_48 +R 6000,2400,ref_ref,a_24 +R 6000,3200,ref_ref,c_32 +R 6000,4000,ref_ref,c_40 +R 6000,4800,ref_ref,z_48 +R 6800,2400,ref_ref,a_24 +R 7600,2400,ref_ref,a_24 +S 7400,2400,7400,3900,200,*,UP,POLY +S 3000,2800,3000,3400,200,*,UP,POLY +S 1000,2300,1000,2800,200,*,UP,POLY +S 0,400,8800,400,800,*,RIGHT,ALU1 +S 0,400,8800,400,800,vss,RIGHT,CALU1 +S 0,5400,8800,5400,4400,*,RIGHT,NWELL +S 0,6800,8800,6800,800,*,RIGHT,ALU1 +S 0,6800,8800,6800,800,vdd,RIGHT,CALU1 +S 1000,600,1000,2100,200,t12,UP,NTRANS +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2600,1200,4000,400,*,UP,ALU1 +S 1200,2800,1200,3900,200,*,UP,POLY +S 1200,3200,1200,3200,400,c,LEFT,CALU1 +S 1200,3900,1200,6600,200,t11,UP,PTRANS +S 1200,4000,6100,4000,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1500,400,1500,900,600,*,UP,ALU1 +S 1500,4100,1500,6400,400,n2a,UP,PDIF +S 1900,3500,1900,3900,200,*,UP,POLY +S 1900,3900,1900,6600,200,t07,UP,PTRANS +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,2500,2000,3500,200,*,UP,POLY +S 2000,4000,2000,4000,400,c,LEFT,CALU1 +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2000,600,2000,2100,200,t08,UP,NTRANS +S 2200,2400,2200,2800,400,*,UP,ALU1 +S 2200,2400,4300,2400,400,*,RIGHT,ALU1 +S 2200,4100,2200,6400,400,n1a,UP,PDIF +S 2600,3500,3600,3500,200,*,RIGHT,POLY +S 2600,3900,2600,6600,200,t03,UP,PTRANS +S 2800,2400,2800,2400,400,b,LEFT,CALU1 +S 2800,4000,2800,4000,400,c,LEFT,CALU1 +S 2800,4800,2800,4800,400,z,LEFT,CALU1 +S 3000,2100,3000,3000,200,*,UP,POLY +S 3000,600,3000,2100,200,t04,UP,NTRANS +S 3100,3200,5100,3200,400,*,RIGHT,ALU1 +S 3100,5600,3100,6800,600,*,UP,ALU1 +S 3500,400,3500,1600,600,*,UP,ALU1 +S 3600,2400,3600,2400,400,b,LEFT,CALU1 +S 3600,3200,3600,3200,400,a,LEFT,CALU1 +S 3600,3900,3600,6600,200,t02,UP,PTRANS +S 3600,4000,3600,4000,400,c,LEFT,CALU1 +S 3600,4800,3600,4800,400,z,LEFT,CALU1 +S 3600,800,3600,1900,600,*,UP,NDIF +S 3900,4100,3900,6400,400,n1b,UP,PDIF +S 400,1600,2600,1600,400,*,RIGHT,ALU1 +S 400,1600,400,4900,400,*,UP,ALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 400,4800,6100,4800,400,*,RIGHT,ALU1 +S 4300,1600,4300,2400,400,*,UP,ALU1 +S 4300,1600,5300,1600,400,*,RIGHT,ALU1 +S 4300,2500,4300,3900,200,*,UP,POLY +S 4300,2500,6700,2500,200,*,RIGHT,POLY +S 4300,3900,4300,6600,200,t06,UP,PTRANS +S 4400,1600,4400,1600,400,b,LEFT,CALU1 +S 4400,3200,4400,3200,400,a,LEFT,CALU1 +S 4400,4000,4400,4000,400,c,LEFT,CALU1 +S 4400,4800,4400,4800,400,z,LEFT,CALU1 +S 4500,1600,4500,2500,600,*,UP,POLY +S 4600,4100,4600,6400,400,n2b,UP,PDIF +S 5000,3500,6000,3500,200,*,RIGHT,POLY +S 5000,3900,5000,6600,200,t10,UP,PTRANS +S 5100,2400,5100,3200,400,*,UP,ALU1 +S 5100,2400,7700,2400,400,*,RIGHT,ALU1 +S 5200,1600,5200,1600,400,b,LEFT,CALU1 +S 5200,2400,5200,2400,400,a,LEFT,CALU1 +S 5200,4000,5200,4000,400,c,LEFT,CALU1 +S 5200,4800,5200,4800,400,z,LEFT,CALU1 +S 5500,4800,5500,5700,400,*,UP,ALU1 +S 6000,2400,6000,2400,400,a,LEFT,CALU1 +S 6000,3200,6000,4000,400,c,UP,CALU1 +S 6000,3200,6000,4000,600,*,UP,ALU1 +S 6000,3900,6000,6600,200,t09,UP,PTRANS +S 6000,4800,6000,4800,400,z,LEFT,CALU1 +S 6400,4100,6400,6400,400,n2a,UP,PDIF +S 6700,2500,6700,3900,200,*,UP,POLY +S 6700,3900,6700,6600,200,t05,UP,PTRANS +S 6800,2400,6800,2400,400,a,LEFT,CALU1 +S 700,4800,700,5600,400,*,UP,ALU1 +S 700,4800,700,5600,600,*,UP,PDIF +S 7100,4100,7100,6400,400,n1a,UP,PDIF +S 7400,3900,7400,6600,200,t01,UP,PTRANS +S 7400,500,7400,1600,1400,*,UP,PTIE +S 7600,2400,7600,2400,400,a,LEFT,CALU1 +S 7900,4100,7900,6400,600,*,UP,PDIF +S 7900,5600,7900,6800,600,*,UP,ALU1 +V 1200,2700,CONT_POLY,* +V 1500,900,CONT_DIF_N,* +V 2200,2700,CONT_POLY,* +V 2500,1600,CONT_DIF_N,* +V 3100,5600,CONT_DIF_P,* +V 3100,6300,CONT_DIF_P,* +V 3200,3200,CONT_POLY,* +V 3500,1600,CONT_DIF_N,* +V 3500,900,CONT_DIF_N,* +V 4500,1600,CONT_POLY,* +V 500,1600,CONT_DIF_N,* +V 5500,4900,CONT_DIF_P,* +V 5500,5600,CONT_DIF_P,* +V 5900,3300,CONT_POLY,* +V 7000,600,CONT_BODY_P,* +V 700,4800,CONT_DIF_P,* +V 700,5500,CONT_DIF_P,* +V 7600,2400,CONT_POLY,* +V 7800,600,CONT_BODY_P,* +V 7900,5600,CONT_DIF_P,* +V 7900,6300,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr3v0x2.vbe b/pdks/symbolic/vsclib/cells/nr3v0x2.vbe new file mode 100755 index 000000000..ec969f26f --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3v0x2.vbe @@ -0,0 +1,38 @@ +ENTITY nr3v0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 6336; + CONSTANT cin_b : NATURAL := 11; + CONSTANT cin_c : NATURAL := 11; + CONSTANT cin_a : NATURAL := 11; + CONSTANT rdown_b_z : NATURAL := 1550; + CONSTANT rdown_c_z : NATURAL := 1550; + CONSTANT rdown_a_z : NATURAL := 1580; + CONSTANT rup_b_z : NATURAL := 2160; + CONSTANT rup_c_z : NATURAL := 2160; + CONSTANT rup_a_z : NATURAL := 2160; + CONSTANT tplh_a_z : NATURAL := 76; + CONSTANT tphl_c_z : NATURAL := 49; + CONSTANT tplh_c_z : NATURAL := 47; + CONSTANT tplh_b_z : NATURAL := 67; + CONSTANT tphl_b_z : NATURAL := 63; + CONSTANT tphl_a_z : NATURAL := 71; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr3v0x2; + +ARCHITECTURE behaviour_data_flow OF nr3v0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr3v0x2" + SEVERITY WARNING; + z <= not (((b or c) or a)) after 109 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr3v0x4.ap b/pdks/symbolic/vsclib/cells/nr3v0x4.ap new file mode 100755 index 000000000..1b8713b01 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3v0x4.ap @@ -0,0 +1,256 @@ +V ALLIANCE : 6 +H nr3v0x4,P,28/ 5/2006,1000 +A 0,0,136000,72000 +R 100000,16000,ref_ref,b_16 +R 100000,24000,ref_ref,a_24 +R 100000,40000,ref_ref,c_40 +R 100000,48000,ref_ref,z_48 +R 108000,16000,ref_ref,b_16 +R 108000,24000,ref_ref,a_24 +R 108000,32000,ref_ref,c_32 +R 108000,40000,ref_ref,c_40 +R 108000,48000,ref_ref,z_48 +R 108000,56000,ref_ref,z_56 +R 116000,16000,ref_ref,b_16 +R 116000,24000,ref_ref,a_24 +R 12000,16000,ref_ref,z_16 +R 12000,32000,ref_ref,c_32 +R 12000,48000,ref_ref,z_48 +R 12000,56000,ref_ref,z_56 +R 124000,24000,ref_ref,a_24 +R 20000,16000,ref_ref,z_16 +R 20000,40000,ref_ref,c_40 +R 20000,48000,ref_ref,z_48 +R 28000,16000,ref_ref,z_16 +R 28000,24000,ref_ref,b_24 +R 28000,32000,ref_ref,b_32 +R 28000,40000,ref_ref,c_40 +R 28000,48000,ref_ref,z_48 +R 36000,16000,ref_ref,z_16 +R 36000,24000,ref_ref,b_24 +R 36000,40000,ref_ref,c_40 +R 36000,48000,ref_ref,z_48 +R 4000,24000,ref_ref,z_24 +R 4000,32000,ref_ref,z_32 +R 4000,40000,ref_ref,z_40 +R 4000,48000,ref_ref,z_48 +R 44000,16000,ref_ref,z_16 +R 44000,24000,ref_ref,b_24 +R 44000,32000,ref_ref,a_32 +R 44000,40000,ref_ref,c_40 +R 44000,48000,ref_ref,z_48 +R 52000,16000,ref_ref,z_16 +R 52000,24000,ref_ref,b_24 +R 52000,32000,ref_ref,a_32 +R 52000,40000,ref_ref,c_40 +R 52000,48000,ref_ref,z_48 +R 60000,16000,ref_ref,z_16 +R 60000,24000,ref_ref,b_24 +R 60000,32000,ref_ref,a_32 +R 60000,40000,ref_ref,c_40 +R 60000,48000,ref_ref,z_48 +R 60000,56000,ref_ref,z_56 +R 68000,24000,ref_ref,b_24 +R 68000,32000,ref_ref,a_32 +R 68000,40000,ref_ref,c_40 +R 68000,48000,ref_ref,z_48 +R 76000,24000,ref_ref,b_24 +R 76000,32000,ref_ref,a_32 +R 76000,40000,ref_ref,c_40 +R 76000,48000,ref_ref,z_48 +R 84000,16000,ref_ref,b_16 +R 84000,24000,ref_ref,b_24 +R 84000,32000,ref_ref,a_32 +R 84000,40000,ref_ref,c_40 +R 84000,48000,ref_ref,z_48 +R 92000,16000,ref_ref,b_16 +R 92000,32000,ref_ref,a_32 +R 92000,40000,ref_ref,c_40 +R 92000,48000,ref_ref,z_48 +S 0,4000,136000,4000,8000,*,RIGHT,ALU1 +S 0,4000,136000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,136000,54000,44000,*,RIGHT,NWELL +S 0,68000,136000,68000,8000,*,RIGHT,ALU1 +S 0,68000,136000,68000,8000,vdd,RIGHT,CALU1 +S 100000,16000,100000,16000,4000,b,RIGHT,CALU1 +S 100000,24000,100000,24000,4000,a,RIGHT,CALU1 +S 100000,40000,100000,40000,4000,c,RIGHT,CALU1 +S 100000,48000,100000,48000,4000,z,RIGHT,CALU1 +S 10000,18000,10000,32000,2000,*,UP,POLY +S 10000,32000,16000,32000,6000,*,RIGHT,POLY +S 10000,6000,10000,18000,2000,t20,UP,NTRANS +S 102000,32000,112000,32000,6000,*,RIGHT,POLY +S 102000,38000,102000,66000,2000,t18,UP,PTRANS +S 102000,4000,102000,34000,2000,*,UP,POLY +S 107000,40000,107000,56000,6000,*,UP,PDIF +S 108000,16000,108000,16000,4000,b,RIGHT,CALU1 +S 108000,24000,108000,24000,4000,a,RIGHT,CALU1 +S 108000,32000,108000,40000,4000,c,UP,CALU1 +S 108000,32000,108000,40000,6000,*,UP,ALU1 +S 108000,48000,108000,56000,4000,z,UP,CALU1 +S 108000,48000,108000,57000,6000,*,UP,ALU1 +S 109000,6000,130000,6000,6000,*,RIGHT,PTIE +S 11000,48000,11000,55000,6000,*,UP,PDIF +S 11000,48000,11000,57000,4000,*,UP,ALU1 +S 112000,38000,112000,66000,2000,t19,UP,PTRANS +S 116000,16000,116000,16000,4000,b,RIGHT,CALU1 +S 116000,24000,116000,24000,4000,a,RIGHT,CALU1 +S 116000,40000,116000,64000,4000,n2e,UP,PDIF +S 119000,14000,119000,38000,2000,*,UP,POLY +S 119000,38000,119000,66000,2000,t12,UP,PTRANS +S 12000,15000,12000,23000,4000,*,UP,ALU1 +S 12000,15000,61000,15000,4000,*,RIGHT,ALU1 +S 12000,16000,12000,16000,4000,z,RIGHT,CALU1 +S 12000,16000,61000,16000,4000,*,RIGHT,ALU1 +S 12000,31000,12000,40000,4000,*,UP,ALU1 +S 12000,32000,12000,32000,4000,c,RIGHT,CALU1 +S 12000,40000,109000,40000,4000,*,RIGHT,ALU1 +S 12000,48000,12000,56000,4000,z,UP,CALU1 +S 12000,48000,12000,57000,4000,*,UP,ALU1 +S 123000,40000,123000,64000,4000,n1e,UP,PDIF +S 124000,24000,124000,24000,4000,a,RIGHT,CALU1 +S 126000,25000,126000,38000,2000,*,UP,POLY +S 126000,38000,126000,66000,2000,t05,UP,PTRANS +S 131000,40000,131000,64000,6000,*,UP,PDIF +S 131000,56000,131000,68000,6000,*,UP,ALU1 +S 16000,38000,16000,58000,2000,t15,UP,PTRANS +S 16000,58000,16000,62000,2000,*,UP,POLY +S 19000,40000,19000,56000,4000,n2a,UP,PDIF +S 20000,16000,20000,16000,4000,z,RIGHT,CALU1 +S 20000,22000,24000,22000,2000,*,RIGHT,POLY +S 20000,23000,24000,23000,2000,*,RIGHT,POLY +S 20000,40000,20000,40000,4000,c,RIGHT,CALU1 +S 20000,48000,20000,48000,4000,z,RIGHT,CALU1 +S 20000,6000,20000,18000,2000,t13,UP,NTRANS +S 23000,24000,23000,38000,2000,*,UP,POLY +S 23000,24000,85000,24000,4000,*,RIGHT,ALU1 +S 23000,38000,23000,58000,2000,t08,UP,PTRANS +S 23000,58000,23000,62000,2000,*,UP,POLY +S 26000,40000,26000,56000,4000,n1a,UP,PDIF +S 26000,5000,26000,16000,6000,*,UP,NDIF +S 28000,16000,28000,16000,4000,z,RIGHT,CALU1 +S 28000,24000,28000,32000,4000,b,UP,CALU1 +S 28000,24000,28000,32000,6000,*,UP,ALU1 +S 28000,40000,28000,40000,4000,c,RIGHT,CALU1 +S 28000,48000,28000,48000,4000,z,RIGHT,CALU1 +S 30000,34000,40000,34000,2000,*,RIGHT,POLY +S 30000,38000,30000,58000,2000,t01,UP,PTRANS +S 30000,58000,30000,62000,2000,*,UP,POLY +S 32000,22000,42000,22000,2000,*,RIGHT,POLY +S 32000,6000,32000,18000,2000,t06,UP,NTRANS +S 35000,40000,35000,64000,4000,*,UP,PDIF +S 35000,55000,35000,68000,6000,*,UP,ALU1 +S 36000,16000,36000,16000,4000,z,RIGHT,CALU1 +S 36000,24000,36000,24000,4000,b,RIGHT,CALU1 +S 36000,40000,36000,40000,4000,c,RIGHT,CALU1 +S 36000,48000,36000,48000,4000,z,RIGHT,CALU1 +S 37000,32000,96000,32000,4000,*,RIGHT,ALU1 +S 40000,22000,40000,34000,2000,*,UP,POLY +S 40000,38000,40000,66000,2000,t02,UP,PTRANS +S 4000,23000,12000,23000,4000,*,RIGHT,ALU1 +S 4000,23000,4000,49000,4000,*,UP,ALU1 +S 4000,24000,4000,48000,4000,z,UP,CALU1 +S 4000,48000,109000,48000,4000,*,RIGHT,ALU1 +S 4000,49000,12000,49000,4000,*,RIGHT,ALU1 +S 42000,6000,42000,18000,2000,t07,UP,NTRANS +S 44000,16000,44000,16000,4000,z,RIGHT,CALU1 +S 44000,24000,44000,24000,4000,b,RIGHT,CALU1 +S 44000,32000,44000,32000,4000,a,RIGHT,CALU1 +S 44000,40000,44000,40000,4000,c,RIGHT,CALU1 +S 44000,40000,44000,64000,4000,n1b,UP,PDIF +S 44000,48000,44000,48000,4000,z,RIGHT,CALU1 +S 47000,33000,47000,38000,2000,*,UP,POLY +S 47000,38000,47000,66000,2000,t09,UP,PTRANS +S 48000,24000,48000,34000,2000,*,UP,POLY +S 48000,24000,54000,24000,6000,*,RIGHT,POLY +S 48000,5000,48000,16000,6000,*,UP,NDIF +S 5000,4000,5000,10000,4000,*,UP,ALU1 +S 5000,8000,5000,16000,6000,*,UP,NDIF +S 51000,40000,51000,64000,4000,n2b,UP,PDIF +S 52000,16000,52000,16000,4000,z,RIGHT,CALU1 +S 52000,24000,52000,24000,4000,b,RIGHT,CALU1 +S 52000,32000,52000,32000,4000,a,RIGHT,CALU1 +S 52000,40000,52000,40000,4000,c,RIGHT,CALU1 +S 52000,48000,52000,48000,4000,z,RIGHT,CALU1 +S 54000,34000,64000,34000,2000,*,RIGHT,POLY +S 54000,38000,54000,66000,2000,t16,UP,PTRANS +S 54000,6000,54000,18000,2000,t14,UP,NTRANS +S 59000,48000,59000,57000,4000,*,UP,ALU1 +S 60000,16000,60000,16000,4000,z,RIGHT,CALU1 +S 60000,24000,60000,24000,4000,b,RIGHT,CALU1 +S 60000,32000,60000,32000,4000,a,RIGHT,CALU1 +S 60000,40000,60000,40000,4000,c,RIGHT,CALU1 +S 60000,48000,60000,56000,4000,z,UP,CALU1 +S 60000,48000,60000,57000,4000,*,UP,ALU1 +S 64000,20000,64000,32000,2000,*,UP,POLY +S 64000,38000,64000,66000,2000,t17,UP,PTRANS +S 64000,4000,102000,4000,2000,*,RIGHT,POLY +S 64000,8000,64000,20000,2000,t21,UP,NTRANS +S 67000,40000,67000,64000,4000,n2c,UP,PDIF +S 68000,24000,68000,24000,4000,b,RIGHT,CALU1 +S 68000,32000,68000,32000,4000,a,RIGHT,CALU1 +S 68000,40000,68000,40000,4000,c,RIGHT,CALU1 +S 68000,48000,68000,48000,4000,z,RIGHT,CALU1 +S 69000,10000,69000,18000,6000,*,UP,NDIF +S 69000,4000,69000,12000,4000,*,UP,ALU1 +S 71000,26000,71000,38000,2000,*,UP,POLY +S 71000,26000,77000,26000,2000,*,RIGHT,POLY +S 71000,38000,71000,66000,2000,t10,UP,PTRANS +S 74000,40000,74000,64000,4000,n1c,UP,PDIF +S 76000,24000,76000,24000,4000,b,RIGHT,CALU1 +S 76000,32000,76000,32000,4000,a,RIGHT,CALU1 +S 76000,40000,76000,40000,4000,c,RIGHT,CALU1 +S 76000,48000,76000,48000,4000,z,RIGHT,CALU1 +S 78000,34000,88000,34000,2000,*,RIGHT,POLY +S 78000,38000,78000,66000,2000,t03,UP,PTRANS +S 83000,16000,117000,16000,4000,*,RIGHT,ALU1 +S 83000,56000,83000,68000,6000,*,UP,ALU1 +S 84000,16000,84000,16000,4000,b,RIGHT,CALU1 +S 84000,16000,84000,24000,6000,*,UP,ALU1 +S 84000,24000,84000,24000,4000,b,RIGHT,CALU1 +S 84000,32000,84000,32000,4000,a,RIGHT,CALU1 +S 84000,40000,84000,40000,4000,c,RIGHT,CALU1 +S 84000,48000,84000,48000,4000,z,RIGHT,CALU1 +S 88000,38000,88000,66000,2000,t04,UP,PTRANS +S 91000,40000,91000,64000,4000,n1d,UP,PDIF +S 92000,16000,92000,16000,4000,b,RIGHT,CALU1 +S 92000,32000,92000,32000,4000,a,RIGHT,CALU1 +S 92000,40000,92000,40000,4000,c,RIGHT,CALU1 +S 92000,48000,92000,48000,4000,z,RIGHT,CALU1 +S 95000,16000,95000,38000,2000,*,UP,POLY +S 95000,38000,95000,66000,2000,t11,UP,PTRANS +S 96000,24000,129000,24000,4000,*,RIGHT,ALU1 +S 96000,24000,96000,32000,4000,*,UP,ALU1 +S 98000,40000,98000,64000,4000,n2d,UP,PDIF +V 107000,48000,CONT_DIF_P,* +V 107000,56000,CONT_DIF_P,* +V 108000,32000,CONT_POLY,* +V 109000,6000,CONT_BODY_P,* +V 11000,48000,CONT_DIF_P,* +V 11000,55000,CONT_DIF_P,* +V 116000,16000,CONT_POLY,* +V 12000,32000,CONT_POLY,* +V 128000,24000,CONT_POLY,* +V 130000,6000,CONT_BODY_P,* +V 131000,56000,CONT_DIF_P,* +V 131000,63000,CONT_DIF_P,* +V 15000,15000,CONT_DIF_N,* +V 24000,24000,CONT_POLY,* +V 26000,6000,CONT_DIF_N,* +V 35000,55000,CONT_DIF_P,* +V 37000,15000,CONT_DIF_N,* +V 38000,32000,CONT_POLY,* +V 48000,6000,CONT_DIF_N,* +V 5000,9000,CONT_DIF_N,* +V 51000,24000,CONT_POLY,* +V 59000,15000,CONT_DIF_N,* +V 59000,48000,CONT_DIF_P,* +V 59000,56000,CONT_DIF_P,* +V 6000,66000,CONT_BODY_N,* +V 69000,11000,CONT_DIF_N,* +V 77000,24000,CONT_POLY,* +V 83000,56000,CONT_DIF_P,* +V 83000,63000,CONT_DIF_P,* +V 87000,32000,CONT_POLY,* +V 93000,16000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr3v0x4.vbe b/pdks/symbolic/vsclib/cells/nr3v0x4.vbe new file mode 100755 index 000000000..16c147e6b --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3v0x4.vbe @@ -0,0 +1,38 @@ +ENTITY nr3v0x4 IS +GENERIC ( + CONSTANT area : NATURAL := 9792; + CONSTANT cin_b : NATURAL := 19; + CONSTANT cin_c : NATURAL := 19; + CONSTANT cin_a : NATURAL := 19; + CONSTANT rdown_b_z : NATURAL := 970; + CONSTANT rdown_c_z : NATURAL := 970; + CONSTANT rdown_a_z : NATURAL := 990; + CONSTANT rup_b_z : NATURAL := 1330; + CONSTANT rup_c_z : NATURAL := 1320; + CONSTANT rup_a_z : NATURAL := 1330; + CONSTANT tplh_a_z : NATURAL := 76; + CONSTANT tphl_c_z : NATURAL := 49; + CONSTANT tplh_c_z : NATURAL := 47; + CONSTANT tplh_b_z : NATURAL := 67; + CONSTANT tphl_b_z : NATURAL := 64; + CONSTANT tphl_a_z : NATURAL := 72; + CONSTANT transistors : NATURAL := 21 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr3v0x4; + +ARCHITECTURE behaviour_data_flow OF nr3v0x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr3v0x4" + SEVERITY WARNING; + z <= not (((b or c) or a)) after 91 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr3v1x05.ap b/pdks/symbolic/vsclib/cells/nr3v1x05.ap new file mode 100755 index 000000000..247409b8d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3v1x05.ap @@ -0,0 +1,81 @@ +V ALLIANCE : 6 +H nr3v1x05,P,23/ 6/2024,100 +A 0,0,4000,7200 +R 2000,1600,ref_ref,z_16 +R 1200,1600,ref_ref,z_16 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 3600,4000,ref_ref,a_40 +R 2800,2400,ref_ref,b_24 +R 2000,4800,ref_ref,c_48 +R 2000,3200,ref_ref,b_32 +R 1200,4000,ref_ref,c_40 +R 1200,3200,ref_ref,c_32 +R 3600,4800,ref_ref,a_48 +R 2800,4000,ref_ref,a_40 +S 2000,2400,2900,2400,400,*,LEFT,ALU1 +S 1000,1100,1000,2100,200,t06,UP,NTRANS +S 2000,2800,2200,2800,400,*,LEFT,ALU1 +S 2000,2800,2000,3300,400,*,DOWN,ALU1 +S 2200,2400,2200,2800,400,*,UP,ALU1 +S 3500,400,3500,1400,400,*,DOWN,ALU1 +S 3500,1200,3500,1800,600,*,UP,NDIF +S 2000,600,2000,1000,200,*,UP,POLY +S 3000,600,3000,1000,200,*,UP,POLY +S 2000,1000,2000,2000,200,t04,UP,NTRANS +S 3000,1000,3000,2000,200,t02,UP,NTRANS +S 3000,2000,3000,3300,200,*,UP,POLY +S 1500,500,1500,2300,400,*,UP,NDIF +S 1000,2500,1000,3200,200,*,UP,POLY +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 400,1600,400,4900,400,*,UP,ALU1 +S 500,1600,500,1900,400,*,DOWN,ALU1 +S 400,1600,2600,1600,400,*,LEFT,ALU1 +S 400,4900,900,4900,400,*,RIGHT,ALU1 +S 2700,3400,3000,3400,200,*,RIGHT,POLY +S 2700,3800,2700,6600,200,t01,UP,PTRANS +S 2300,4000,2300,6400,400,n1,UP,PDIF +S 2000,3800,2000,6600,200,t03,UP,PTRANS +S 1700,4000,1700,6400,400,n2,UP,PDIF +S 1300,3800,1300,6600,200,t05,UP,PTRANS +S 800,4900,800,5700,600,*,UP,PDIF +S 800,4900,800,5600,600,*,UP,ALU1 +S 3500,4000,3500,6400,600,*,UP,PDIF +S 3000,3200,3500,3200,600,*,RIGHT,POLY +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 0,5400,4000,5400,4400,*,RIGHT,NWELL +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 0,6800,4000,6800,800,*,RIGHT,ALU1 +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,400,4000,400,800,*,RIGHT,ALU1 +S 2800,2400,2800,2400,400,b,LEFT,CALU1 +S 2000,3200,2000,3200,400,b,LEFT,CALU1 +S 1200,3100,1200,4100,400,*,UP,ALU1 +S 1200,4100,2000,4100,400,*,RIGHT,ALU1 +S 2000,4100,2000,4900,400,*,UP,ALU1 +S 2000,4800,2000,4800,400,c,LEFT,CALU1 +S 1200,3200,1200,4000,400,c,UP,CALU1 +S 2800,4000,2800,4000,400,a,LEFT,CALU1 +S 3600,4000,3600,4800,400,a,UP,CALU1 +S 2800,4000,3600,4000,600,*,RIGHT,ALU1 +S 3500,3100,3500,4100,400,*,UP,ALU1 +S 3600,3900,3600,4900,400,*,UP,ALU1 +S 3500,5600,3500,6800,600,*,UP,ALU1 +S 2000,2000,2000,3800,200,*,DOWN,POLY +V 1500,800,CONT_DIF_N,* +V 3500,1300,CONT_DIF_N,* +V 2500,1600,CONT_DIF_N,* +V 800,4900,CONT_DIF_P,* +V 800,5600,CONT_DIF_P,* +V 3500,3200,CONT_POLY,* +V 3500,6300,CONT_DIF_P,* +V 3500,5600,CONT_DIF_P,* +V 1200,3200,CONT_POLY,* +V 500,1800,CONT_DIF_N,* +V 2200,2600,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr3v1x05.vbe b/pdks/symbolic/vsclib/cells/nr3v1x05.vbe new file mode 100755 index 000000000..2002ca64d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr3v1x05.vbe @@ -0,0 +1,38 @@ +ENTITY nr3v1x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT cin_a : NATURAL := 5; + CONSTANT rdown_b_z : NATURAL := 2350; + CONSTANT rdown_c_z : NATURAL := 2390; + CONSTANT rdown_a_z : NATURAL := 2410; + CONSTANT rup_b_z : NATURAL := 6280; + CONSTANT rup_c_z : NATURAL := 6240; + CONSTANT rup_a_z : NATURAL := 6270; + CONSTANT tplh_a_z : NATURAL := 86; + CONSTANT tphl_c_z : NATURAL := 39; + CONSTANT tplh_c_z : NATURAL := 57; + CONSTANT tplh_b_z : NATURAL := 78; + CONSTANT tphl_b_z : NATURAL := 47; + CONSTANT tphl_a_z : NATURAL := 50; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr3v1x05; + +ARCHITECTURE behaviour_data_flow OF nr3v1x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr3v1x05" + SEVERITY WARNING; + z <= not (((b or c) or a)) after 168 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr4v0x1.ap b/pdks/symbolic/vsclib/cells/nr4v0x1.ap new file mode 100755 index 000000000..f9f8562ed --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr4v0x1.ap @@ -0,0 +1,150 @@ +V ALLIANCE : 6 +H nr4v0x1,P,22/ 6/2024,100 +A 0,0,8000,7200 +R 6800,4000,ref_ref,a_40 +R 6800,2400,ref_ref,d_24 +R 6800,1600,ref_ref,d_16 +R 6000,4800,ref_ref,a_48 +R 6000,1600,ref_ref,d_16 +R 5200,5600,ref_ref,a_56 +R 5200,3200,ref_ref,b_32 +R 4400,5600,ref_ref,a_56 +R 4400,4000,ref_ref,b_40 +R 4400,2400,ref_ref,c_24 +R 400,4800,ref_ref,a_48 +R 400,4000,ref_ref,a_40 +R 3600,5600,ref_ref,a_56 +R 3600,4800,ref_ref,z_48 +R 3600,4000,ref_ref,b_40 +R 3600,3200,ref_ref,c_32 +R 3600,2400,ref_ref,c_24 +R 3600,1600,ref_ref,z_16 +R 2800,5600,ref_ref,a_56 +R 2800,4800,ref_ref,z_48 +R 2800,4000,ref_ref,b_40 +R 2800,1600,ref_ref,z_16 +R 2000,5600,ref_ref,a_56 +R 2000,4800,ref_ref,z_48 +R 2000,3200,ref_ref,b_32 +R 2000,1600,ref_ref,z_16 +R 1200,5600,ref_ref,a_56 +R 1200,4000,ref_ref,z_40 +R 1200,3200,ref_ref,z_32 +R 1200,2400,ref_ref,z_24 +R 1200,1600,ref_ref,z_16 +S 5800,800,5800,1600,200,*,UP,POLY +S 7100,4700,7100,6800,600,*,UP,ALU1 +S 7100,4100,7100,5500,600,*,UP,PDIF +S 700,4100,700,6700,600,*,UP,PDIF +S 7000,500,7000,2200,600,*,UP,PTIE +S 7000,3300,7000,4000,600,*,UP,ALU1 +S 6800,4000,6800,4000,400,a,LEFT,CALU1 +S 6800,1600,6800,2400,400,d,UP,CALU1 +S 6800,1500,6800,2500,400,*,UP,ALU1 +S 6600,3900,6600,5700,200,t2a,UP,PTRANS +S 6600,3500,7000,3500,200,*,RIGHT,POLY +S 6200,4100,6200,5500,400,n1b,UP,PDIF +S 6000,4800,6000,4800,400,a,LEFT,CALU1 +S 6000,4000,7100,4000,400,*,RIGHT,ALU1 +S 6000,4000,6000,5600,400,*,UP,ALU1 +S 6000,2600,6000,3200,400,*,UP,ALU1 +S 6000,1600,6800,1600,600,*,RIGHT,ALU1 +S 6000,1600,6000,1600,400,d,LEFT,CALU1 +S 5900,3900,5900,5700,200,t2b,UP,PTRANS +S 5900,2700,5900,3900,200,*,UP,POLY +S 5500,4100,5500,5500,400,n2b,UP,PDIF +S 5200,5600,5200,5600,400,a,LEFT,CALU1 +S 5200,3900,5200,5700,200,t2c,UP,PTRANS +S 5200,3200,5200,3200,400,b,LEFT,CALU1 +S 5200,2400,5200,3900,200,*,UP,POLY +S 5100,3200,6000,3200,400,*,RIGHT,ALU1 +S 5100,3200,5100,4000,400,*,UP,ALU1 +S 500,400,500,1600,400,*,UP,ALU1 +S 500,3500,1400,3500,200,*,RIGHT,POLY +S 500,3300,1000,3300,600,*,RIGHT,POLY +S 4800,6600,7000,6600,600,*,RIGHT,NTIE +S 4800,4100,4800,5500,400,n3b,UP,PDIF +S 4700,400,4700,1600,400,*,UP,ALU1 +S 4500,3900,4500,5700,200,t2d,UP,PTRANS +S 4400,5600,4400,5600,400,a,LEFT,CALU1 +S 4400,4000,4400,4000,400,b,LEFT,CALU1 +S 4400,2400,4400,2400,400,c,LEFT,CALU1 +S 4200,800,5800,800,200,*,RIGHT,POLY +S 4200,1800,4200,3500,200,*,UP,POLY +S 4200,1200,4200,1800,200,t3d,UP,NTRANS +S 400,5600,6000,5600,400,*,RIGHT,ALU1 +S 400,4000,400,4800,400,a,UP,CALU1 +S 400,3300,500,3300,600,*,RIGHT,ALU1 +S 400,3200,400,5600,400,*,UP,ALU1 +S 3600,5600,3600,5600,400,a,LEFT,CALU1 +S 3600,4800,3600,4800,400,z,LEFT,CALU1 +S 3600,4000,3600,4000,400,b,LEFT,CALU1 +S 3600,2400,3600,3200,600,*,UP,ALU1 +S 3600,2400,3600,3200,400,c,UP,CALU1 +S 3600,1600,3600,1600,400,z,LEFT,CALU1 +S 3500,6400,3500,6800,200,*,UP,POLY +S 3500,3900,3500,6400,200,t1d,UP,PTRANS +S 3500,3500,4500,3500,200,*,RIGHT,POLY +S 3200,800,3200,1200,200,*,UP,POLY +S 3200,1200,3200,1800,200,t3c,UP,NTRANS +S 3100,4100,3100,6200,400,n3a,UP,PDIF +S 3000,2400,5100,2400,400,*,RIGHT,ALU1 +S 2900,2400,2900,3500,200,*,UP,POLY +S 2800,6400,2800,6800,200,*,UP,POLY +S 2800,5600,2800,5600,400,a,LEFT,CALU1 +S 2800,4800,2800,4800,400,z,LEFT,CALU1 +S 2800,4000,2800,4000,400,b,LEFT,CALU1 +S 2800,3900,2800,6400,200,t1c,UP,PTRANS +S 2800,3400,2800,3900,200,*,UP,POLY +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2600,500,2600,1600,600,*,UP,NDIF +S 2400,4100,2400,6200,400,n2a,UP,PDIF +S 2100,6400,2100,6800,200,*,UP,POLY +S 2100,3900,2100,6400,200,t1b,UP,PTRANS +S 2100,2600,2100,3900,200,*,UP,POLY +S 2000,800,2000,1200,200,*,UP,POLY +S 2000,5600,2000,5600,400,a,LEFT,CALU1 +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2000,4000,5100,4000,400,*,RIGHT,ALU1 +S 2000,3200,2000,3200,400,b,LEFT,CALU1 +S 2000,2500,2000,4000,400,*,UP,ALU1 +S 2000,1800,2000,2600,200,*,UP,POLY +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,1200,2000,1800,200,t3b,UP,NTRANS +S 1700,4100,1700,6200,400,n1a,UP,PDIF +S 1400,6400,1400,6800,200,*,UP,POLY +S 1400,3900,1400,6400,200,t1a,UP,PTRANS +S 1200,5600,1200,5600,400,a,LEFT,CALU1 +S 1200,4800,4100,4800,400,*,RIGHT,ALU1 +S 1200,1600,3800,1600,400,*,RIGHT,ALU1 +S 1200,1600,1200,4000,400,z,UP,CALU1 +S 1200,1500,3800,1500,400,*,RIGHT,ALU1 +S 1200,1500,1200,4800,400,*,UP,ALU1 +S 1000,800,1000,1200,200,*,UP,POLY +S 1000,1800,1000,3500,200,*,UP,POLY +S 1000,1200,1000,1800,200,t3a,UP,NTRANS +S 0,6800,8000,6800,800,vdd,RIGHT,CALU1 +S 0,6800,8000,6800,800,*,RIGHT,ALU1 +S 0,5400,8000,5400,4400,*,RIGHT,NWELL +S 0,400,8000,400,800,vss,RIGHT,CALU1 +S 0,400,8000,400,800,*,RIGHT,ALU1 +V 800,6600,CONT_DIF_P,* +V 7100,5400,CONT_DIF_P,* +V 7100,4700,CONT_DIF_P,* +V 7000,6600,CONT_BODY_N,* +V 7000,600,CONT_BODY_P,* +V 7000,3300,CONT_POLY,* +V 6000,2700,CONT_POLY,* +V 6000,1600,CONT_POLY,* +V 500,3300,CONT_POLY,* +V 500,1500,CONT_DIF_N,* +V 5000,2400,CONT_POLY,* +V 4800,6600,CONT_BODY_N,* +V 4700,1500,CONT_DIF_N,* +V 4000,4800,CONT_DIF_P,* +V 3700,1500,CONT_DIF_N,* +V 3100,2400,CONT_POLY,* +V 2600,600,CONT_DIF_N,* +V 2000,2600,CONT_POLY,* +V 1500,1500,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr4v0x1.vbe b/pdks/symbolic/vsclib/cells/nr4v0x1.vbe new file mode 100755 index 000000000..b31045264 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr4v0x1.vbe @@ -0,0 +1,44 @@ +ENTITY nr4v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 5760; + CONSTANT cin_c : NATURAL := 6; + CONSTANT cin_d : NATURAL := 6; + CONSTANT cin_b : NATURAL := 7; + CONSTANT cin_a : NATURAL := 7; + CONSTANT rdown_c_z : NATURAL := 3900; + CONSTANT rdown_d_z : NATURAL := 3890; + CONSTANT rdown_b_z : NATURAL := 4000; + CONSTANT rdown_a_z : NATURAL := 4150; + CONSTANT rup_c_z : NATURAL := 5460; + CONSTANT rup_d_z : NATURAL := 5400; + CONSTANT rup_b_z : NATURAL := 5480; + CONSTANT rup_a_z : NATURAL := 5480; + CONSTANT tphl_d_z : NATURAL := 58; + CONSTANT tplh_a_z : NATURAL := 116; + CONSTANT tplh_d_z : NATURAL := 49; + CONSTANT tphl_c_z : NATURAL := 80; + CONSTANT tplh_b_z : NATURAL := 106; + CONSTANT tplh_c_z : NATURAL := 83; + CONSTANT tphl_b_z : NATURAL := 95; + CONSTANT tphl_a_z : NATURAL := 103; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + c : in BIT; + d : in BIT; + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr4v0x1; + +ARCHITECTURE behaviour_data_flow OF nr4v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr4v0x1" + SEVERITY WARNING; + z <= not ((((c or d) or b) or a)) after 204 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr4v0x2.ap b/pdks/symbolic/vsclib/cells/nr4v0x2.ap new file mode 100755 index 000000000..11592c087 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr4v0x2.ap @@ -0,0 +1,202 @@ +V ALLIANCE : 6 +H nr4v0x2,P,22/ 6/2024,100 +A 0,0,11200,7200 +R 10000,1600,ref_ref,a_16 +R 1200,1600,ref_ref,z_16 +R 1200,3200,ref_ref,d_32 +R 1200,4000,ref_ref,d_40 +R 1200,5600,ref_ref,z_56 +R 2000,2400,ref_ref,c_24 +R 2000,3200,ref_ref,c_32 +R 2000,4800,ref_ref,d_48 +R 2000,5600,ref_ref,z_56 +R 2800,4000,ref_ref,c_40 +R 2800,4800,ref_ref,d_48 +R 2800,5600,ref_ref,z_56 +R 3600,1600,ref_ref,z_16 +R 3600,2400,ref_ref,b_24 +R 3600,4000,ref_ref,c_40 +R 3600,4800,ref_ref,d_48 +R 3600,5600,ref_ref,z_56 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,2400,ref_ref,b_24 +R 4400,3200,ref_ref,a_32 +R 4400,4000,ref_ref,c_40 +R 4400,4800,ref_ref,d_48 +R 4400,5600,ref_ref,z_56 +R 5200,1600,ref_ref,b_16 +R 5200,3200,ref_ref,a_32 +R 5200,4000,ref_ref,c_40 +R 5200,4800,ref_ref,d_48 +R 5200,5600,ref_ref,z_56 +R 6000,2400,ref_ref,a_24 +R 6000,4000,ref_ref,c_40 +R 6000,4800,ref_ref,d_48 +R 6000,5600,ref_ref,z_56 +R 6800,1600,ref_ref,a_16 +R 6800,3200,ref_ref,c_32 +R 6800,4800,ref_ref,d_48 +R 6800,5600,ref_ref,z_56 +R 7600,1600,ref_ref,a_16 +R 7600,3200,ref_ref,d_32 +R 7600,4000,ref_ref,d_40 +R 7600,4800,ref_ref,d_48 +R 7600,5600,ref_ref,z_56 +R 8400,1600,ref_ref,a_16 +R 9200,1600,ref_ref,a_16 +S 3300,1900,3300,2500,200,*,UP,POLY +S 2900,2300,2900,2900,200,*,DOWN,POLY +S 0,400,11200,400,800,*,RIGHT,ALU1 +S 0,400,11200,400,800,vss,RIGHT,CALU1 +S 0,5400,11200,5400,4400,*,RIGHT,NWELL +S 0,6800,11200,6800,800,*,RIGHT,ALU1 +S 0,6800,11200,6800,800,vdd,RIGHT,CALU1 +S 10000,1600,10000,1600,400,a,LEFT,CALU1 +S 10000,1600,10000,3800,200,*,UP,POLY +S 10000,3800,10000,6500,200,t13,UP,PTRANS +S 10000,6500,10000,6900,200,*,UP,POLY +S 1000,3400,1500,3400,600,*,RIGHT,POLY +S 10500,4000,10500,6300,600,*,UP,PDIF +S 10500,5500,10500,6800,600,*,UP,ALU1 +S 1100,1800,1100,3500,200,*,UP,POLY +S 1100,300,1100,700,200,*,UP,POLY +S 1100,700,1100,1800,200,t12,UP,NTRANS +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,3100,1200,4800,400,*,UP,ALU1 +S 1200,3200,1200,4000,400,d,UP,CALU1 +S 1200,4800,7800,4800,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1500,4000,1500,6500,200,t10,UP,PTRANS +S 1500,6500,1500,6900,200,*,UP,POLY +S 1800,4200,1800,6300,400,n1,UP,PDIF +S 2000,2300,2000,4000,400,*,UP,ALU1 +S 2000,2400,2000,3200,400,c,UP,CALU1 +S 2000,4000,6800,4000,400,*,RIGHT,ALU1 +S 2000,4800,2000,4800,400,d,LEFT,CALU1 +S 2000,5600,2000,5600,400,z,LEFT,CALU1 +S 2100,300,2100,700,200,*,UP,POLY +S 2100,700,2100,1800,200,t09,UP,NTRANS +S 2200,2400,2200,4000,200,*,UP,POLY +S 2200,4000,2200,6500,200,t07,UP,PTRANS +S 2200,6500,2200,6900,200,*,UP,POLY +S 2500,4200,2500,6300,400,n2,UP,PDIF +S 2700,500,2700,1600,600,*,UP,NDIF +S 2800,4000,2800,4000,400,c,LEFT,CALU1 +S 2800,4800,2800,4800,400,d,LEFT,CALU1 +S 2800,5600,2800,5600,400,z,LEFT,CALU1 +S 2900,2400,2900,4000,200,*,UP,POLY +S 2900,4000,2900,6500,200,t04,UP,PTRANS +S 2900,6500,2900,6900,200,*,UP,POLY +S 3000,2400,5200,2400,400,*,RIGHT,ALU1 +S 3200,4200,3200,6300,400,n3,UP,PDIF +S 3300,300,3300,700,200,*,UP,POLY +S 3300,700,3300,1800,200,t06,UP,NTRANS +S 3500,1600,3900,1600,400,*,RIGHT,ALU1 +S 3600,1600,3600,1600,400,z,LEFT,CALU1 +S 3600,2400,3600,2400,400,b,LEFT,CALU1 +S 3600,3400,3600,4000,200,*,UP,POLY +S 3600,3400,4800,3400,200,*,RIGHT,POLY +S 3600,4000,3600,4000,400,c,LEFT,CALU1 +S 3600,4000,3600,6500,200,t01,UP,PTRANS +S 3600,4800,3600,4800,400,d,LEFT,CALU1 +S 3600,5600,3600,5600,400,z,LEFT,CALU1 +S 3600,6500,3600,6900,200,*,UP,POLY +S 4000,3200,6000,3200,400,*,RIGHT,ALU1 +S 400,1500,3900,1500,400,*,RIGHT,ALU1 +S 400,1500,400,5600,400,*,UP,ALU1 +S 400,1600,1200,1600,600,*,RIGHT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,5600,7700,5600,400,*,RIGHT,ALU1 +S 4200,4000,4200,6700,600,*,UP,PDIF +S 4300,1800,4300,3400,200,*,UP,POLY +S 4300,300,4300,700,200,*,UP,POLY +S 4300,700,4300,1800,200,t03,UP,NTRANS +S 4400,2400,4400,2400,400,b,LEFT,CALU1 +S 4400,3200,4400,3200,400,a,LEFT,CALU1 +S 4400,4000,4400,4000,400,c,LEFT,CALU1 +S 4400,4800,4400,4800,400,d,LEFT,CALU1 +S 4400,5600,4400,5600,400,z,LEFT,CALU1 +S 4800,3800,4800,6500,200,t02,UP,PTRANS +S 4800,6500,4800,6900,200,*,UP,POLY +S 4900,2400,5500,2400,600,*,RIGHT,POLY +S 4900,900,4900,1600,600,*,UP,NDIF +S 500,500,500,1600,600,*,UP,NDIF +S 5100,4000,5100,6300,400,n6,UP,PDIF +S 5200,1500,5200,2400,400,*,UP,ALU1 +S 5200,1600,5200,1600,400,b,LEFT,CALU1 +S 5200,3200,5200,3200,400,a,LEFT,CALU1 +S 5200,4000,5200,4000,400,c,LEFT,CALU1 +S 5200,4800,5200,4800,400,d,LEFT,CALU1 +S 5200,5600,5200,5600,400,z,LEFT,CALU1 +S 5500,1800,5500,3800,200,*,UP,POLY +S 5500,1800,9300,1800,200,*,RIGHT,POLY +S 5500,3800,5500,6500,200,t05,UP,PTRANS +S 5500,6500,5500,6900,200,*,UP,POLY +S 5800,4000,5800,6300,400,n5,UP,PDIF +S 6000,1600,10300,1600,400,*,RIGHT,ALU1 +S 6000,1600,6000,3200,400,*,UP,ALU1 +S 6000,2400,6000,2400,400,a,LEFT,CALU1 +S 6000,4000,6000,4000,400,c,LEFT,CALU1 +S 6000,4800,6000,4800,400,d,LEFT,CALU1 +S 6000,5600,6000,5600,400,z,LEFT,CALU1 +S 6200,2800,6200,3800,200,*,UP,POLY +S 6200,2800,6800,2800,200,*,RIGHT,POLY +S 6200,3800,6200,6500,200,t08,UP,PTRANS +S 6200,6500,6200,6900,200,*,UP,POLY +S 6500,4000,6500,6300,400,n4,UP,PDIF +S 6600,600,10600,600,600,*,RIGHT,PTIE +S 6800,1600,6800,1600,400,a,LEFT,CALU1 +S 6800,2400,8600,2400,200,*,RIGHT,POLY +S 6800,2500,6800,4000,400,*,UP,ALU1 +S 6800,3200,6800,3200,400,c,LEFT,CALU1 +S 6800,4800,6800,4800,400,d,LEFT,CALU1 +S 6800,5600,6800,5600,400,z,LEFT,CALU1 +S 6900,3400,7900,3400,200,*,RIGHT,POLY +S 6900,3800,6900,6500,200,t11,UP,PTRANS +S 6900,6500,6900,6900,200,*,UP,POLY +S 7600,1600,7600,1600,400,a,LEFT,CALU1 +S 7600,3200,7600,4800,400,d,UP,CALU1 +S 7600,5600,7600,5600,400,z,LEFT,CALU1 +S 7700,3100,7700,4800,600,*,UP,ALU1 +S 7900,3800,7900,6500,200,t16,UP,PTRANS +S 7900,6500,7900,6900,200,*,UP,POLY +S 8200,4000,8200,6300,400,n7,UP,PDIF +S 8400,1600,8400,1600,400,a,LEFT,CALU1 +S 8600,2400,8600,3800,200,*,UP,POLY +S 8600,3800,8600,6500,200,t15,UP,PTRANS +S 8600,6500,8600,6900,200,*,UP,POLY +S 8900,4000,8900,6300,400,n8,UP,PDIF +S 9200,1600,9200,1600,400,a,LEFT,CALU1 +S 9300,1800,9300,3800,200,*,UP,POLY +S 9300,3800,9300,6500,200,t14,UP,PTRANS +S 9300,6500,9300,6900,200,*,UP,POLY +S 9600,4000,9600,6300,400,n9,UP,PDIF +V 1000,5600,CONT_DIF_P,* +V 10200,1600,CONT_POLY,* +V 10500,5500,CONT_DIF_P,* +V 10500,6200,CONT_DIF_P,* +V 10600,600,CONT_BODY_P,* +V 1200,3400,CONT_POLY,* +V 1600,1500,CONT_DIF_N,* +V 2000,2400,CONT_POLY,* +V 2700,600,CONT_DIF_N,* +V 3100,2400,CONT_POLY,* +V 3800,1500,CONT_DIF_N,* +V 4100,3200,CONT_POLY,* +V 4200,6600,CONT_DIF_P,* +V 4900,600,CONT_DIF_N,* +V 500,600,CONT_DIF_N,* +V 5100,2400,CONT_POLY,* +V 6600,600,CONT_BODY_P,* +V 6800,2600,CONT_POLY,* +V 7400,5600,CONT_DIF_P,* +V 7400,600,CONT_BODY_P,* +V 7800,3200,CONT_POLY,* +V 8200,600,CONT_BODY_P,* +V 9000,600,CONT_BODY_P,* +V 9800,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr4v0x2.vbe b/pdks/symbolic/vsclib/cells/nr4v0x2.vbe new file mode 100755 index 000000000..926e0dac2 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr4v0x2.vbe @@ -0,0 +1,44 @@ +ENTITY nr4v0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 8064; + CONSTANT cin_c : NATURAL := 11; + CONSTANT cin_d : NATURAL := 11; + CONSTANT cin_b : NATURAL := 11; + CONSTANT cin_a : NATURAL := 11; + CONSTANT rdown_c_z : NATURAL := 2120; + CONSTANT rdown_d_z : NATURAL := 2120; + CONSTANT rdown_b_z : NATURAL := 2170; + CONSTANT rdown_a_z : NATURAL := 2250; + CONSTANT rup_c_z : NATURAL := 2970; + CONSTANT rup_d_z : NATURAL := 2960; + CONSTANT rup_b_z : NATURAL := 2970; + CONSTANT rup_a_z : NATURAL := 2970; + CONSTANT tphl_d_z : NATURAL := 59; + CONSTANT tplh_a_z : NATURAL := 110; + CONSTANT tplh_d_z : NATURAL := 50; + CONSTANT tphl_c_z : NATURAL := 79; + CONSTANT tplh_b_z : NATURAL := 102; + CONSTANT tplh_c_z : NATURAL := 81; + CONSTANT tphl_b_z : NATURAL := 92; + CONSTANT tphl_a_z : NATURAL := 99; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + c : in BIT; + d : in BIT; + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr4v0x2; + +ARCHITECTURE behaviour_data_flow OF nr4v0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr4v0x2" + SEVERITY WARNING; + z <= not ((((c or d) or b) or a)) after 148 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/nr4v1x05.ap b/pdks/symbolic/vsclib/cells/nr4v1x05.ap new file mode 100755 index 000000000..dca640202 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr4v1x05.ap @@ -0,0 +1,102 @@ +V ALLIANCE : 6 +H nr4v1x05,P,23/ 6/2024,100 +A 0,0,5600,7200 +R 1200,4000,ref_ref,d_40 +R 1200,5600,ref_ref,z_56 +R 2000,1600,ref_ref,z_16 +R 2000,4800,ref_ref,d_48 +R 2800,1600,ref_ref,z_16 +R 2800,2400,ref_ref,b_24 +R 2800,4000,ref_ref,c_40 +R 3600,2400,ref_ref,b_24 +R 3600,3200,ref_ref,a_32 +R 3600,4800,ref_ref,c_48 +R 3600,5600,ref_ref,c_56 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +R 4400,1600,ref_ref,b_16 +R 4400,2400,ref_ref,b_24 +R 4400,4000,ref_ref,a_40 +S 2500,800,2500,1900,600,*,UP,NDIF +S 3000,2100,3000,2500,200,*,UP,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,1500,1000,2100,200,t2d,UP,NTRANS +S 1000,2100,1000,3700,200,*,UP,POLY +S 1200,3700,1200,4800,400,*,UP,ALU1 +S 1200,4000,1200,4000,400,d,LEFT,CALU1 +S 1200,4000,1900,4000,200,*,RIGHT,POLY +S 1200,4800,2100,4800,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1500,1600,1500,2800,400,*,UP,ALU1 +S 1500,1600,3600,1600,400,*,RIGHT,ALU1 +S 1900,4400,1900,6600,200,t1d,UP,PTRANS +S 2000,1500,2000,2100,200,t2c,UP,NTRANS +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,2100,2000,3200,200,*,UP,POLY +S 2000,4800,2000,4800,400,d,LEFT,CALU1 +S 2200,3100,2200,4000,400,*,UP,ALU1 +S 2200,4000,3600,4000,400,*,RIGHT,ALU1 +S 2200,4600,2200,6400,400,n1,UP,PDIF +S 2300,3300,2600,3300,200,*,RIGHT,POLY +S 2300,3400,2600,3400,200,*,RIGHT,POLY +S 2400,4000,3600,4000,400,*,RIGHT,ALU1 +S 2600,3300,2600,4400,200,*,UP,POLY +S 2600,4400,2600,6600,200,t1c,UP,PTRANS +S 2700,2400,4500,2400,400,*,RIGHT,ALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2800,2400,2800,2400,400,b,LEFT,CALU1 +S 2800,4000,2800,4000,400,c,LEFT,CALU1 +S 2900,4600,2900,6400,400,n2,UP,PDIF +S 3000,1300,3000,1900,200,t2b,UP,NTRANS +S 3000,900,3000,1300,200,*,UP,POLY +S 3200,2400,3200,2500,600,*,UP,ALU1 +S 3300,2700,3300,4400,200,*,UP,POLY +S 3300,4400,3300,6600,200,t1b,UP,PTRANS +S 3500,3200,4400,3200,400,*,RIGHT,ALU1 +S 3600,2400,3600,2400,400,b,LEFT,CALU1 +S 3600,3200,3600,3200,400,a,LEFT,CALU1 +S 3600,4000,3600,5700,400,*,UP,ALU1 +S 3600,4600,3600,6400,400,n3,UP,PDIF +S 3600,4800,3600,5600,400,c,UP,CALU1 +S 4000,1300,4000,1900,200,t2a,UP,NTRANS +S 4000,1900,4000,3700,200,*,UP,POLY +S 4000,3800,4300,3800,600,*,RIGHT,POLY +S 4000,4400,4000,6600,200,t1a,UP,PTRANS +S 4000,900,4000,1300,200,*,UP,POLY +S 400,2800,1500,2800,400,*,RIGHT,ALU1 +S 400,2800,400,5700,400,*,UP,ALU1 +S 400,3200,400,5600,400,z,UP,CALU1 +S 400,5600,1500,5600,400,*,RIGHT,ALU1 +S 400,5700,1500,5700,400,*,RIGHT,ALU1 +S 4400,1500,4400,2400,400,*,UP,ALU1 +S 4400,1600,4400,2400,400,b,UP,CALU1 +S 4400,3200,4400,4100,400,*,UP,ALU1 +S 4400,4000,4400,4000,400,a,LEFT,CALU1 +S 4500,1500,4500,2400,400,*,UP,ALU1 +S 4500,4600,4500,6400,600,*,UP,PDIF +S 4500,5400,4500,6800,400,*,UP,ALU1 +S 4700,500,4700,1700,600,*,UP,NDIF +S 500,400,500,1900,400,*,UP,ALU1 +S 600,600,1400,600,600,*,RIGHT,PTIE +V 2500,800,CONT_DIF_N,* +V 1200,3800,CONT_POLY,* +V 1400,5600,CONT_DIF_P,* +V 1400,600,CONT_BODY_P,* +V 1500,1800,CONT_DIF_N,* +V 2200,3200,CONT_POLY,* +V 3200,2500,CONT_POLY,* +V 3500,1600,CONT_DIF_N,* +V 4400,3800,CONT_POLY,* +V 4500,5500,CONT_DIF_P,* +V 4500,6300,CONT_DIF_P,* +V 4700,600,CONT_DIF_N,* +V 500,1800,CONT_DIF_N,* +V 600,600,CONT_BODY_P,* +V 600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/nr4v1x05.vbe b/pdks/symbolic/vsclib/cells/nr4v1x05.vbe new file mode 100755 index 000000000..0ed42d5e4 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/nr4v1x05.vbe @@ -0,0 +1,44 @@ +ENTITY nr4v1x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_c : NATURAL := 4; + CONSTANT cin_d : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_c_z : NATURAL := 3910; + CONSTANT rdown_d_z : NATURAL := 3920; + CONSTANT rdown_b_z : NATURAL := 4050; + CONSTANT rdown_a_z : NATURAL := 4200; + CONSTANT rup_c_z : NATURAL := 10700; + CONSTANT rup_d_z : NATURAL := 10650; + CONSTANT rup_b_z : NATURAL := 10710; + CONSTANT rup_a_z : NATURAL := 10680; + CONSTANT tphl_d_z : NATURAL := 47; + CONSTANT tplh_a_z : NATURAL := 126; + CONSTANT tplh_d_z : NATURAL := 64; + CONSTANT tphl_c_z : NATURAL := 57; + CONSTANT tplh_b_z : NATURAL := 118; + CONSTANT tplh_c_z : NATURAL := 96; + CONSTANT tphl_b_z : NATURAL := 62; + CONSTANT tphl_a_z : NATURAL := 62; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + c : in BIT; + d : in BIT; + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END nr4v1x05; + +ARCHITECTURE behaviour_data_flow OF nr4v1x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on nr4v1x05" + SEVERITY WARNING; + z <= not ((((c or d) or b) or a)) after 263 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oai211v0x05.ap b/pdks/symbolic/vsclib/cells/oai211v0x05.ap new file mode 100755 index 000000000..97a8ee2a6 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai211v0x05.ap @@ -0,0 +1,98 @@ +V ALLIANCE : 6 +H oai211v0x05,P,23/ 6/2024,100 +A 0,0,4800,7200 +R 1200,1600,ref_ref,b_16 +R 1200,2400,ref_ref,b_24 +R 1200,4000,ref_ref,c_40 +R 1200,5600,ref_ref,z_56 +R 2000,2400,ref_ref,b_24 +R 2000,4000,ref_ref,c_40 +R 2000,5600,ref_ref,z_56 +R 2800,3200,ref_ref,a1_32 +R 2800,4800,ref_ref,c_40 +R 3600,2400,ref_ref,a1_24 +R 3600,3200,ref_ref,a1_32 +R 3600,4800,ref_ref,a2_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +R 4400,4000,ref_ref,a2_40 +R 4400,4800,ref_ref,a2_48 +S 1700,2200,1700,2500,200,*,UP,POLY +S 2700,1900,2700,3200,200,*,UP,POLY +S 2100,2500,2100,4800,200,*,UP,POLY +S 3300,500,3300,2300,600,*,UP,NDIF +S 2600,5000,2600,6700,600,*,UP,PDIF +S 0,400,4800,400,800,*,RIGHT,ALU1 +S 0,400,4800,400,800,vss,RIGHT,CALU1 +S 0,5400,4800,5400,4400,*,RIGHT,NWELL +S 0,6800,4800,6800,800,*,RIGHT,ALU1 +S 0,6800,4800,6800,800,vdd,RIGHT,CALU1 +S 1000,1900,1000,4000,200,*,UP,POLY +S 1000,500,1000,900,200,*,UP,POLY +S 1000,900,1000,1900,200,t08,UP,NTRANS +S 1100,4200,1100,4800,200,*,UP,POLY +S 1100,4800,1100,5700,200,t07,UP,PTRANS +S 1200,1500,1200,2500,400,*,UP,ALU1 +S 1200,1600,1200,2400,400,b,UP,CALU1 +S 1200,2400,2000,2400,600,*,RIGHT,ALU1 +S 1200,4000,1200,4000,400,c,LEFT,CALU1 +S 1200,4000,2000,4000,600,*,RIGHT,ALU1 +S 1200,4100,2800,4100,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1400,1100,1400,1700,400,n2,UP,NDIF +S 1600,5400,1600,5700,600,*,UP,ALU1 +S 1700,500,1700,900,200,*,UP,POLY +S 1700,900,1700,1900,200,t06,UP,NTRANS +S 2000,2400,2000,2400,400,b,LEFT,CALU1 +S 2000,4000,2000,4000,400,c,LEFT,CALU1 +S 2000,5600,2000,5600,400,z,LEFT,CALU1 +S 2100,1500,4300,1500,400,*,RIGHT,ALU1 +S 2100,4800,2100,5700,200,t05,UP,PTRANS +S 2700,500,2700,900,200,*,UP,POLY +S 2700,900,2700,1900,200,t02,UP,NTRANS +S 2800,3200,2800,3200,400,a1,LEFT,CALU1 +S 2800,3200,3600,3200,600,*,RIGHT,ALU1 +S 2800,4100,2800,4900,400,*,UP,ALU1 +S 2800,4800,2800,4800,400,c,LEFT,CALU1 +S 3100,3200,3100,4800,200,*,UP,POLY +S 3100,4800,3100,6400,200,t01,UP,PTRANS +S 3100,6400,3100,6800,200,*,UP,POLY +S 3200,500,3200,2300,400,*,UP,NDIF +S 3500,5000,3500,6200,400,n3,UP,PDIF +S 3600,2300,3600,3300,400,*,UP,ALU1 +S 3600,2400,3600,3200,400,a1,UP,CALU1 +S 3600,4800,3600,4800,400,a2,LEFT,CALU1 +S 3600,4800,4400,4800,600,*,RIGHT,ALU1 +S 3800,1500,3800,2500,200,t04,UP,NTRANS +S 3800,2500,3800,4000,200,*,UP,POLY +S 3800,4200,4200,4200,600,*,RIGHT,POLY +S 3800,4800,3800,6400,200,t03,UP,PTRANS +S 3800,6400,3800,6800,200,*,UP,POLY +S 400,1500,400,5700,400,*,UP,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 400,5600,2000,5600,600,*,RIGHT,ALU1 +S 400,5700,4400,5700,400,*,RIGHT,ALU1 +S 4300,1500,4300,1900,400,*,UP,ALU1 +S 4300,4100,4300,4900,400,*,UP,ALU1 +S 4400,3900,4400,4900,400,*,UP,ALU1 +S 4400,4000,4400,4800,400,a2,UP,CALU1 +S 500,1500,500,1700,400,*,UP,ALU1 +S 500,5000,500,6700,600,*,UP,PDIF +V 2600,6600,CONT_DIF_P,* +V 1200,4000,CONT_POLY,* +V 1500,6600,CONT_BODY_N,* +V 1600,5400,CONT_DIF_P,* +V 1900,2500,CONT_POLY,* +V 2200,1500,CONT_DIF_N,n1 +V 3000,3100,CONT_POLY,* +V 3300,600,CONT_DIF_N,* +V 4300,1800,CONT_DIF_N,n1 +V 4300,4200,CONT_POLY,* +V 4300,5700,CONT_DIF_P,* +V 500,1600,CONT_DIF_N,* +V 500,6600,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/oai211v0x05.vbe b/pdks/symbolic/vsclib/cells/oai211v0x05.vbe new file mode 100755 index 000000000..a05e63aba --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai211v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY oai211v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 3456; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_c : NATURAL := 3; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT rdown_b_z : NATURAL := 4870; + CONSTANT rdown_c_z : NATURAL := 4860; + CONSTANT rdown_a1_z : NATURAL := 5140; + CONSTANT rdown_a2_z : NATURAL := 5140; + CONSTANT rup_b_z : NATURAL := 6620; + CONSTANT rup_c_z : NATURAL := 6640; + CONSTANT rup_a1_z : NATURAL := 7350; + CONSTANT rup_a2_z : NATURAL := 7340; + CONSTANT tphl_b_z : NATURAL := 49; + CONSTANT tphl_c_z : NATURAL := 47; + CONSTANT tplh_a2_z : NATURAL := 87; + CONSTANT tphl_a1_z : NATURAL := 66; + CONSTANT tplh_c_z : NATURAL := 59; + CONSTANT tplh_a1_z : NATURAL := 96; + CONSTANT tplh_b_z : NATURAL := 68; + CONSTANT tphl_a2_z : NATURAL := 57; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b : in BIT; + c : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai211v0x05; + +ARCHITECTURE behaviour_data_flow OF oai211v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai211v0x05" + SEVERITY WARNING; + z <= not((b and c) and (a1 or a2)) after 216 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oai21a2bv0x05.ap b/pdks/symbolic/vsclib/cells/oai21a2bv0x05.ap new file mode 100755 index 000000000..f33603112 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21a2bv0x05.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H oai21a2bv0x05,P, 5/ 7/2024,100 +A 0,0,7200,7200 +R 1200,4800,ref_ref,b_48 +R 6000,3200,ref_ref,a1_32 +R 6800,3200,ref_ref,a1_32 +R 3600,3200,ref_ref,z_32 +R 3600,2400,ref_ref,z_24 +R 2000,4000,ref_ref,b_40 +R 2000,3200,ref_ref,a2_32 +R 1200,2400,ref_ref,a2_24 +R 3600,4000,ref_ref,z_40 +R 4400,4800,ref_ref,z_48 +R 3600,4800,ref_ref,z_48 +R 5200,4800,ref_ref,z_48 +R 3600,1600,ref_ref,z_16 +R 6800,4000,ref_ref,a1_40 +S 3300,4300,3300,5900,1000,*,UP,TALU8 +S 3100,1300,3100,2200,1000,*,UP,TALU7 +S 5500,3200,5500,3800,200,*,DOWN,POLY +S 1800,4200,2200,4200,200,*,LEFT,POLY +S 2000,2300,2000,4100,200,*,UP,POLY +S 1600,1500,1600,2200,600,*,UP,NDIF +S 5700,1400,5700,2400,600,*,UP,NDIF +S 4500,2300,6700,2300,400,*,RIGHT,ALU1 +S 3800,4800,3800,6700,600,*,DOWN,PDIF +S 6200,1900,6200,3800,200,*,UP,POLY +S 2800,3400,4100,3400,200,*,RIGHT,POLY +S 1000,2400,1000,4800,200,*,DOWN,POLY +S 2100,1900,2100,2400,200,*,UP,POLY +S 2600,2400,2800,2400,400,*,RIGHT,ALU1 +S 2600,1500,2600,2400,400,*,UP,ALU1 +S 2100,900,2100,1300,200,*,DOWN,POLY +S 2100,1300,2100,1900,200,t09,UP,NTRANS +S 1600,400,1600,1600,600,*,DOWN,ALU1 +S 400,2000,400,5700,400,*,UP,ALU1 +S 400,2100,500,2100,600,*,LEFT,ALU1 +S 1000,1400,1000,1800,200,*,DOWN,POLY +S 1000,1800,1000,2400,200,t10,UP,NTRANS +S 1200,2400,1200,2400,400,a2,LEFT,CALU1 +S 2000,4000,2000,4000,400,b,LEFT,CALU1 +S 1200,4000,2100,4000,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,b,LEFT,CALU1 +S 1200,4000,1200,4900,400,*,UP,ALU1 +S 1200,3200,2100,3200,400,*,RIGHT,ALU1 +S 1200,2300,1200,3200,400,*,UP,ALU1 +S 3600,2100,3600,2400,600,*,DOWN,NDIF +S 4100,4100,4500,4100,200,*,LEFT,POLY +S 4100,2600,4100,4100,200,*,DOWN,POLY +S 4100,1500,4100,1900,200,*,DOWN,POLY +S 5100,1500,5100,1900,200,*,DOWN,POLY +S 4100,1900,4100,2600,200,t06,UP,NTRANS +S 5100,1900,5100,2600,200,t04,UP,NTRANS +S 5600,1400,5600,2400,400,*,UP,NDIF +S 5700,400,5700,1500,600,*,DOWN,ALU1 +S 6700,1500,6700,2300,400,*,UP,ALU1 +S 6700,1400,6700,1700,600,*,UP,NDIF +S 6200,1200,6200,1900,200,t02,UP,NTRANS +S 6200,800,6200,1200,200,*,DOWN,POLY +S 5200,4000,6000,4000,400,*,RIGHT,ALU1 +S 5200,3100,5200,4000,400,*,UP,ALU1 +S 6800,3200,6800,4000,400,a1,UP,CALU1 +S 6800,3100,6800,4100,400,*,UP,ALU1 +S 6000,3200,6000,3200,400,a1,LEFT,CALU1 +S 6000,3200,6800,3200,600,*,RIGHT,ALU1 +S 6000,4000,6000,5700,400,*,DOWN,ALU1 +S 0,400,7200,400,800,*,RIGHT,ALU1 +S 0,400,7200,400,800,vss,RIGHT,CALU1 +S 0,6800,7200,6800,800,*,RIGHT,ALU1 +S 0,6800,7200,6800,800,vdd,RIGHT,CALU1 +S 6200,3800,6200,5400,200,t01,UP,PTRANS +S 5500,3800,5500,5400,200,t03,UP,PTRANS +S 6700,4000,6700,5200,600,*,DOWN,PDIF +S 2200,4600,2200,5600,200,t07,UP,PTRANS +S 1600,4800,1600,6700,600,*,DOWN,PDIF +S 400,5700,6000,5700,400,*,RIGHT,ALU1 +S 1900,4100,2200,4100,200,*,LEFT,POLY +S 4500,4600,4500,5400,200,t05,UP,PTRANS +S 3900,4800,3900,6700,600,*,DOWN,PDIF +S 1000,6000,1000,6400,200,*,UP,POLY +S 2200,5600,2200,6000,200,*,UP,POLY +S 6200,5400,6200,5800,200,*,UP,POLY +S 5500,5400,5500,5800,200,*,UP,POLY +S 4500,5400,4500,5800,200,*,UP,POLY +S 5800,6600,6600,6600,600,*,LEFT,NTIE +S 3600,600,4400,600,600,*,RIGHT,PTIE +S 2800,2400,2800,5000,400,*,UP,ALU1 +S 3600,4800,5200,4800,600,*,LEFT,ALU1 +S 3600,1500,3600,4900,400,*,DOWN,ALU1 +S 6700,5000,6700,6800,400,*,UP,ALU1 +S 1000,4800,1000,6000,200,t08,UP,PTRANS +S 2000,3200,2000,3200,400,a2,LEFT,CALU1 +S 3600,1600,3600,4800,400,z,UP,CALU1 +S 4400,4800,4400,4800,400,z,LEFT,CALU1 +S 5200,4800,5200,4800,400,z,LEFT,CALU1 +S 0,5400,7200,5400,4400,*,RIGHT,NWELL +V 2800,6600,CONT_BODY_N,* +V 2600,1600,CONT_DIF_N,bn +V 1600,1600,CONT_DIF_N,* +V 500,2100,CONT_DIF_N,a2n +V 1200,3000,CONT_POLY,* +V 3600,2300,CONT_DIF_N,* +V 4600,2300,CONT_DIF_N,n1 +V 5700,1500,CONT_DIF_N,* +V 6700,1600,CONT_DIF_N,n1 +V 5200,3200,CONT_POLY,a2n +V 6400,3200,CONT_POLY,* +V 1800,4000,CONT_POLY,* +V 6700,5100,CONT_DIF_P,* +V 3900,6600,CONT_DIF_P,* +V 1600,6600,CONT_DIF_P,* +V 2800,4900,CONT_DIF_P,bn +V 2800,3200,CONT_POLY,bn +V 5000,4900,CONT_DIF_P,* +V 6600,6600,CONT_BODY_N,* +V 5800,6600,CONT_BODY_N,* +V 3600,600,CONT_BODY_P,* +V 4400,600,CONT_BODY_P,* +V 500,5700,CONT_DIF_P,a2n +EOF diff --git a/pdks/symbolic/vsclib/cells/oai21a2bv0x05.vbe b/pdks/symbolic/vsclib/cells/oai21a2bv0x05.vbe new file mode 100755 index 000000000..eeaebdb81 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21a2bv0x05.vbe @@ -0,0 +1,38 @@ +ENTITY oai21a2bv0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5184; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 5330; + CONSTANT rdown_a2_z : NATURAL := 5360; + CONSTANT rdown_b_z : NATURAL := 4940; + CONSTANT rup_a1_z : NATURAL := 7320; + CONSTANT rup_a2_z : NATURAL := 7350; + CONSTANT rup_b_z : NATURAL := 7490; + CONSTANT tpll_b_z : NATURAL := 91; + CONSTANT tpll_a2_z : NATURAL := 108; + CONSTANT tplh_a1_z : NATURAL := 77; + CONSTANT tphh_b_z : NATURAL := 78; + CONSTANT tphh_a2_z : NATURAL := 104; + CONSTANT tphl_a1_z : NATURAL := 61; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai21a2bv0x05; + +ARCHITECTURE behaviour_data_flow OF oai21a2bv0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai21a2bv0x05" + SEVERITY WARNING; + z <= (not a1 and a2) or b after 244 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oai21a2v0x05.ap b/pdks/symbolic/vsclib/cells/oai21a2v0x05.ap new file mode 100755 index 000000000..4e03ecfb5 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21a2v0x05.ap @@ -0,0 +1,100 @@ +V ALLIANCE : 6 +H oai21a2v0x05,P, 5/ 7/2024,100 +A 0,0,6400,7200 +R 6000,3200,ref_ref,a2_32 +R 2000,4800,ref_ref,z_48 +R 1200,4800,ref_ref,z_48 +R 1200,2400,ref_ref,b_24 +R 2000,3200,ref_ref,b_32 +R 2800,4800,ref_ref,a1_48 +R 6000,4000,ref_ref,a2_40 +R 5200,4000,ref_ref,a2_40 +R 3600,4000,ref_ref,a1_40 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +S 4300,1500,4300,2400,1000,*,UP,TALU7 +S 5200,1800,5200,2400,200,t08,UP,NTRANS +S 4700,800,6100,800,200,*,RIGHT,ALU1 +S 2700,4000,2700,4400,200,*,DOWN,POLY +S 2000,2200,2000,4600,200,*,UP,POLY +S 3200,1900,3200,4000,200,*,UP,POLY +S 3500,4800,3500,6000,600,*,UP,PDIF +S 1200,2400,1200,2400,400,b,LEFT,CALU1 +S 5700,400,5700,2300,600,*,DOWN,ALU1 +S 1400,1500,3800,1500,400,*,RIGHT,ALU1 +S 2800,4000,3700,4000,400,*,RIGHT,ALU1 +S 1200,3200,2100,3200,400,*,RIGHT,ALU1 +S 1200,2300,1200,3200,400,*,UP,ALU1 +S 4400,2300,4800,2300,400,*,LEFT,ALU1 +S 2100,2500,4400,2500,400,*,RIGHT,ALU1 +S 6000,3100,6000,4100,400,*,UP,ALU1 +S 6000,3200,6000,4000,400,a2,UP,CALU1 +S 500,5000,500,6800,400,*,UP,ALU1 +S 400,1600,400,4000,400,z,UP,CALU1 +S 1200,4800,2000,4800,600,*,RIGHT,ALU1 +S 400,1500,400,4100,400,*,UP,ALU1 +S 1200,4100,1200,4900,400,*,UP,ALU1 +S 400,4100,1200,4100,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2000,3200,2000,3200,400,b,LEFT,CALU1 +S 3200,800,3200,1200,200,*,UP,POLY +S 2000,800,2000,1200,200,*,UP,POLY +S 1000,800,1000,1200,200,*,UP,POLY +S 400,1600,500,1600,600,*,RIGHT,ALU1 +S 500,1400,500,1700,600,*,UP,NDIF +S 3200,1200,3200,1900,200,t02,UP,NTRANS +S 3700,1400,3700,1700,600,*,DOWN,NDIF +S 2000,1200,2000,1900,200,t04,UP,NTRANS +S 1000,1200,1000,1900,200,t06,UP,NTRANS +S 2600,500,2600,1700,600,*,UP,NDIF +S 5200,4000,5200,4000,400,a2,LEFT,CALU1 +S 2800,4000,2800,4900,400,*,DOWN,ALU1 +S 2800,4800,2800,4800,400,a1,LEFT,CALU1 +S 3600,4000,3600,4000,400,a1,LEFT,CALU1 +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 5800,4800,5800,6600,600,*,DOWN,NTIE +S 5200,4000,6000,4000,600,*,RIGHT,ALU1 +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,400,6400,400,800,*,RIGHT,ALU1 +S 5200,1600,5200,2000,200,*,DOWN,POLY +S 5200,2600,5200,4200,200,*,UP,POLY +S 5000,600,5800,600,600,*,RIGHT,PTIE +S 4100,4200,5100,4200,200,*,LEFT,POLY +S 4100,4600,4100,5800,200,t07,UP,PTRANS +S 4400,2300,4400,4900,400,*,UP,ALU1 +S 4100,5800,4100,6200,200,*,UP,POLY +S 3600,5400,3600,6800,400,*,UP,ALU1 +S 4400,4900,4700,4900,400,*,RIGHT,ALU1 +S 1000,4600,1000,5400,200,t05,UP,PTRANS +S 2000,4600,2000,6200,200,t03,UP,PTRANS +S 1000,5400,1000,5800,200,*,UP,POLY +S 1000,1900,1000,4600,200,*,UP,POLY +S 500,4800,500,5200,600,*,DOWN,PDIF +S 2000,6200,2000,6600,200,*,UP,POLY +S 2300,4800,2300,6000,400,n2,UP,PDIF +S 2700,4600,2700,6200,200,t01,UP,PTRANS +S 2700,6200,2700,6600,200,*,UP,POLY +V 5700,2100,CONT_DIF_N,* +V 4700,2100,CONT_DIF_N,a2n +V 1200,3100,CONT_POLY,* +V 2200,2500,CONT_POLY,a2n +V 600,6600,CONT_BODY_N,* +V 500,5100,CONT_DIF_P,* +V 500,1600,CONT_DIF_N,* +V 3700,1500,CONT_DIF_N,n1 +V 1500,1500,CONT_DIF_N,n1 +V 2600,600,CONT_DIF_N,* +V 5800,6600,CONT_BODY_N,* +V 5800,600,CONT_BODY_P,* +V 5200,4000,CONT_POLY,* +V 5000,600,CONT_BODY_P,* +V 4600,4900,CONT_DIF_P,a2n +V 3600,5500,CONT_DIF_P,* +V 1500,4900,CONT_DIF_P,* +V 2900,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/oai21a2v0x05.vbe b/pdks/symbolic/vsclib/cells/oai21a2v0x05.vbe new file mode 100755 index 000000000..a19ce2fd6 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21a2v0x05.vbe @@ -0,0 +1,38 @@ +ENTITY oai21a2v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 5320; + CONSTANT rdown_a2_z : NATURAL := 5320; + CONSTANT rdown_b_z : NATURAL := 4920; + CONSTANT rup_a1_z : NATURAL := 7310; + CONSTANT rup_a2_z : NATURAL := 7320; + CONSTANT rup_b_z : NATURAL := 7450; + CONSTANT tphl_b_z : NATURAL := 42; + CONSTANT tpll_a2_z : NATURAL := 96; + CONSTANT tplh_a1_z : NATURAL := 75; + CONSTANT tplh_b_z : NATURAL := 53; + CONSTANT tphh_a2_z : NATURAL := 93; + CONSTANT tphl_a1_z : NATURAL := 57; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai21a2v0x05; + +ARCHITECTURE behaviour_data_flow OF oai21a2v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai21a2v0x05" + SEVERITY WARNING; + z <= not ((a1 or not a2) and b) after 226 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oai21bv0x05.ap b/pdks/symbolic/vsclib/cells/oai21bv0x05.ap new file mode 100755 index 000000000..e04098452 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21bv0x05.ap @@ -0,0 +1,108 @@ +V ALLIANCE : 6 +H oai21bv0x05,P, 5/ 7/2024,100 +A 0,0,6400,7200 +R 1200,5600,ref_ref,z_56 +R 2000,5600,ref_ref,z_56 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +R 2800,4000,ref_ref,a1_40 +R 2800,3200,ref_ref,a2_32 +R 3600,2400,ref_ref,a2_24 +R 1200,3200,ref_ref,a1_32 +R 2000,4000,ref_ref,a1_40 +R 5200,4000,ref_ref,b_40 +R 6000,4800,ref_ref,b_48 +R 6000,4000,ref_ref,b_40 +S 4200,1500,4200,2600,1000,*,UP,TALU7 +S 5200,1800,5200,2400,200,t08,UP,NTRANS +S 4700,800,6000,800,200,*,RIGHT,ALU1 +S 3000,3900,3000,4400,200,*,DOWN,POLY +S 2000,2800,2000,3300,200,*,UP,POLY +S 2300,3200,2300,4600,200,*,UP,POLY +S 4400,4900,4700,4900,400,*,RIGHT,ALU1 +S 4400,2300,4400,4900,400,*,UP,ALU1 +S 1100,4800,4400,4800,400,*,RIGHT,ALU1 +S 4100,4100,5200,4100,200,*,LEFT,POLY +S 4100,4100,4100,4600,200,*,DOWN,POLY +S 5200,2600,5200,3900,200,*,UP,POLY +S 2100,3200,3600,3200,400,*,LEFT,ALU1 +S 2800,3200,2800,3200,400,a2,LEFT,CALU1 +S 3600,2300,3600,3200,400,*,UP,ALU1 +S 4400,2300,4800,2300,400,*,RIGHT,ALU1 +S 5200,1600,5200,2000,200,*,DOWN,POLY +S 5700,400,5700,2400,400,*,DOWN,ALU1 +S 1500,1500,3800,1500,400,*,RIGHT,ALU1 +S 3200,1800,3200,3900,200,*,UP,POLY +S 2600,500,2600,2400,600,*,UP,NDIF +S 3200,700,3200,1100,200,*,UP,POLY +S 3200,1100,3200,1800,200,t02,UP,NTRANS +S 3700,1300,3700,1600,600,*,DOWN,NDIF +S 5000,600,5800,600,600,*,LEFT,PTIE +S 5800,4800,5800,6700,600,*,DOWN,NTIE +S 3500,5600,3500,6800,600,*,UP,ALU1 +S 3500,4800,3500,6000,600,*,UP,PDIF +S 4100,5600,4100,6000,200,*,UP,POLY +S 4100,4600,4100,5600,200,t07,UP,PTRANS +S 1000,1500,1000,1900,200,*,UP,POLY +S 1000,1900,1000,2600,200,t06,UP,NTRANS +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1500,1500,1500,2300,400,*,UP,ALU1 +S 2000,1500,2000,1900,200,*,UP,POLY +S 2000,1900,2000,2600,200,t04,UP,NTRANS +S 2000,5600,2000,5600,400,z,LEFT,CALU1 +S 400,1500,400,5700,400,*,UP,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 400,2200,500,2200,600,*,RIGHT,ALU1 +S 400,5600,2100,5600,400,*,RIGHT,ALU1 +S 400,5700,2100,5700,400,*,RIGHT,ALU1 +S 500,2100,500,2400,600,*,UP,NDIF +S 600,600,1400,600,600,*,RIGHT,PTIE +S 2600,4800,2600,6000,400,n2,UP,PDIF +S 2300,4600,2300,6200,200,t03,UP,PTRANS +S 3000,4600,3000,6200,200,t01,UP,PTRANS +S 1300,5400,1300,6200,200,t05,UP,PTRANS +S 700,5600,700,6700,600,*,UP,PDIF +S 600,5600,600,6700,600,*,UP,PDIF +S 2800,4000,2800,4000,400,a1,LEFT,CALU1 +S 3600,2400,3600,2400,400,a2,LEFT,CALU1 +S 1300,6200,1300,6600,200,*,UP,POLY +S 2300,6200,2300,6600,200,*,UP,POLY +S 3000,6200,3000,6600,200,*,UP,POLY +S 1000,2600,1000,4700,200,*,UP,POLY +S 1200,3200,1200,3200,400,a1,LEFT,CALU1 +S 1200,4000,3300,4000,400,*,RIGHT,ALU1 +S 1200,3100,1200,4000,400,*,UP,ALU1 +S 2000,4000,2000,4000,400,a1,LEFT,CALU1 +S 0,400,6400,400,800,*,RIGHT,ALU1 +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 5200,4000,6000,4000,600,*,RIGHT,ALU1 +S 6000,3900,6000,4900,400,*,UP,ALU1 +S 5200,4000,5200,4000,400,b,LEFT,CALU1 +S 6000,4000,6000,4800,400,b,UP,CALU1 +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +V 5700,2100,CONT_DIF_N,* +V 4700,2100,CONT_DIF_N,bn +V 5400,3900,CONT_POLY,* +V 2600,600,CONT_DIF_N,* +V 3700,1500,CONT_DIF_N,n1 +V 5000,600,CONT_BODY_P,* +V 3500,5600,CONT_DIF_P,* +V 4600,4900,CONT_DIF_P,bn +V 1400,600,CONT_BODY_P,* +V 1500,2200,CONT_DIF_N,n1 +V 500,2200,CONT_DIF_N,* +V 600,600,CONT_BODY_P,* +V 700,6600,CONT_DIF_P,* +V 3200,4000,CONT_POLY,* +V 1800,5700,CONT_DIF_P,* +V 1200,4800,CONT_POLY,bn +V 5800,600,CONT_BODY_P,* +V 5800,6600,CONT_BODY_N,* +V 2200,3200,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/oai21bv0x05.vbe b/pdks/symbolic/vsclib/cells/oai21bv0x05.vbe new file mode 100755 index 000000000..552d312fc --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21bv0x05.vbe @@ -0,0 +1,38 @@ +ENTITY oai21bv0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 5330; + CONSTANT rdown_a2_z : NATURAL := 5330; + CONSTANT rdown_b_z : NATURAL := 4930; + CONSTANT rup_a1_z : NATURAL := 7320; + CONSTANT rup_a2_z : NATURAL := 7300; + CONSTANT rup_b_z : NATURAL := 7480; + CONSTANT tpll_b_z : NATURAL := 90; + CONSTANT tphl_a2_z : NATURAL := 50; + CONSTANT tplh_a1_z : NATURAL := 75; + CONSTANT tphh_b_z : NATURAL := 77; + CONSTANT tplh_a2_z : NATURAL := 65; + CONSTANT tphl_a1_z : NATURAL := 60; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai21bv0x05; + +ARCHITECTURE behaviour_data_flow OF oai21bv0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai21bv0x05" + SEVERITY WARNING; + z <= not ((a1 or a2) and not b) after 227 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oai21v0x05.ap b/pdks/symbolic/vsclib/cells/oai21v0x05.ap new file mode 100755 index 000000000..f2c99a818 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21v0x05.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 6 +H oai21v0x05,P, 5/ 7/2024,100 +A 0,0,4000,7200 +R 2800,2400,ref_ref,a2_24 +R 3600,2400,ref_ref,a2_24 +R 2800,3200,ref_ref,a2_32 +R 3600,4800,ref_ref,a1_48 +R 2800,4000,ref_ref,a1_40 +R 400,5600,ref_ref,z_56 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 2000,5600,ref_ref,z_56 +R 2000,4800,ref_ref,b_48 +R 1200,5600,ref_ref,z_56 +R 1200,4000,ref_ref,b_40 +R 1200,3200,ref_ref,b_32 +S 2000,1200,2000,1800,600,*,UP,TALU7 +S 3000,1800,3000,4300,200,*,UP,POLY +S 1000,2600,1000,4200,200,*,UP,POLY +S 2300,3200,2300,4600,200,*,UP,POLY +S 2500,500,2500,2400,600,*,UP,NDIF +S 1300,4400,1300,5400,200,*,UP,POLY +S 3000,6200,3000,6600,200,*,UP,POLY +S 2300,6200,2300,6600,200,*,UP,POLY +S 1300,6200,1300,6600,200,*,UP,POLY +S 2800,2400,2800,3200,400,a2,UP,CALU1 +S 3600,2400,3600,2400,400,a2,LEFT,CALU1 +S 2800,4000,2800,4000,400,a1,LEFT,CALU1 +S 3600,4800,3600,4800,400,a1,LEFT,CALU1 +S 2000,3200,2900,3200,400,*,LEFT,ALU1 +S 3600,4000,3600,4900,400,*,UP,ALU1 +S 2700,4000,3600,4000,400,*,RIGHT,ALU1 +S 600,5600,600,6700,600,*,UP,PDIF +S 700,5600,700,6700,600,*,UP,PDIF +S 1300,5400,1300,6200,200,t05,UP,PTRANS +S 3500,4800,3500,6000,600,*,UP,PDIF +S 3000,4600,3000,6200,200,t01,UP,PTRANS +S 2300,4600,2300,6200,200,t03,UP,PTRANS +S 2600,4800,2600,6000,400,n2,UP,PDIF +S 600,600,1400,600,600,*,RIGHT,PTIE +S 500,2100,500,2400,600,*,UP,NDIF +S 400,5700,2100,5700,400,*,RIGHT,ALU1 +S 400,5600,2100,5600,400,*,RIGHT,ALU1 +S 400,2200,500,2200,600,*,RIGHT,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 400,1500,400,5700,400,*,UP,ALU1 +S 3500,5700,3500,6800,600,*,UP,ALU1 +S 3500,1300,3500,1600,600,*,UP,NDIF +S 3000,700,3000,1100,200,*,UP,POLY +S 3000,1100,3000,1800,200,t02,UP,NTRANS +S 2800,2300,2800,3200,600,*,UP,ALU1 +S 2700,2400,3600,2400,600,*,RIGHT,ALU1 +S 2400,500,2400,1000,600,*,UP,NDIF +S 2000,5600,2000,5600,400,z,LEFT,CALU1 +S 2000,4800,2000,4800,400,b,LEFT,CALU1 +S 2000,1900,2000,2600,200,t04,UP,NTRANS +S 2000,1500,2000,1900,200,*,UP,POLY +S 1500,1500,3600,1500,400,*,RIGHT,ALU1 +S 1500,1500,1500,2300,400,*,UP,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1200,4800,2100,4800,400,*,RIGHT,ALU1 +S 1200,3200,1200,4000,400,b,UP,CALU1 +S 1200,3100,1200,4800,400,*,UP,ALU1 +S 1000,1900,1000,2600,200,t06,UP,NTRANS +S 1000,1500,1000,1900,200,*,UP,POLY +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 0,6800,4000,6800,800,*,RIGHT,ALU1 +S 0,5400,4000,5400,4400,*,RIGHT,NWELL +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,400,4000,400,800,*,RIGHT,ALU1 +V 2500,600,CONT_DIF_N,* +V 2100,3200,CONT_POLY,* +V 1800,5700,CONT_DIF_P,* +V 3200,4000,CONT_POLY,* +V 700,6600,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 500,2200,CONT_DIF_N,* +V 3500,5700,CONT_DIF_P,* +V 3500,1500,CONT_DIF_N,n1 +V 1500,2200,CONT_DIF_N,n1 +V 1400,600,CONT_BODY_P,* +V 1200,4200,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/oai21v0x05.vbe b/pdks/symbolic/vsclib/cells/oai21v0x05.vbe new file mode 100755 index 000000000..129cae289 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21v0x05.vbe @@ -0,0 +1,38 @@ +ENTITY oai21v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 5310; + CONSTANT rdown_a2_z : NATURAL := 5310; + CONSTANT rdown_b_z : NATURAL := 4920; + CONSTANT rup_a1_z : NATURAL := 7300; + CONSTANT rup_a2_z : NATURAL := 7290; + CONSTANT rup_b_z : NATURAL := 7460; + CONSTANT tphl_b_z : NATURAL := 44; + CONSTANT tphl_a2_z : NATURAL := 48; + CONSTANT tplh_a1_z : NATURAL := 74; + CONSTANT tplh_b_z : NATURAL := 54; + CONSTANT tplh_a2_z : NATURAL := 64; + CONSTANT tphl_a1_z : NATURAL := 58; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai21v0x05; + +ARCHITECTURE behaviour_data_flow OF oai21v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai21v0x05" + SEVERITY WARNING; + z <= not (((a1 or a2) and b)) after 214 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oai21v0x1.ap b/pdks/symbolic/vsclib/cells/oai21v0x1.ap new file mode 100755 index 000000000..2d11fbd36 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21v0x1.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H oai21v0x1,P,22/ 6/2024,100 +A 0,0,4000,7200 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 3600,2400,ref_ref,a1_24 +R 2800,4800,ref_ref,a2_48 +R 2800,4000,ref_ref,a2_40 +R 2800,3200,ref_ref,a1_32 +R 2000,5600,ref_ref,z_56 +R 2000,4000,ref_ref,a2_40 +R 2000,2400,ref_ref,b_24 +R 1200,5600,ref_ref,z_56 +R 1200,4000,ref_ref,b_40 +R 1200,3200,ref_ref,b_32 +S 1800,3100,2300,3100,200,*,RIGHT,POLY +S 2000,2100,2000,3100,200,*,UP,POLY +S 2300,3100,2300,3700,200,*,DOWN,POLY +S 1000,1800,1000,4200,200,*,UP,POLY +S 3000,1800,3000,3900,200,*,UP,POLY +S 400,1600,600,1600,400,*,RIGHT,ALU1 +S 400,1500,600,1500,400,*,RIGHT,ALU1 +S 2500,400,2500,900,600,*,DOWN,ALU1 +S 3500,1500,3500,1600,600,*,UP,ALU1 +S 1500,1500,1500,1600,600,*,UP,ALU1 +S 1400,1600,3600,1600,400,*,RIGHT,ALU1 +S 1000,600,1000,1800,200,t06,UP,NTRANS +S 2000,600,2000,1800,200,t04,UP,NTRANS +S 3000,600,3000,1800,200,t02,UP,NTRANS +S 800,6300,800,6800,600,*,UP,ALU1 +S 700,5400,700,6400,600,*,UP,PDIF +S 400,5600,2100,5600,400,*,RIGHT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,1500,400,5600,400,*,UP,ALU1 +S 3600,2400,3600,2400,400,a1,LEFT,CALU1 +S 3600,2300,3600,3200,400,*,UP,ALU1 +S 3500,5600,3500,6800,600,*,UP,ALU1 +S 3500,4100,3500,6400,600,*,UP,PDIF +S 3000,3900,3000,6600,200,t01,UP,PTRANS +S 3000,3200,3400,3200,600,*,RIGHT,POLY +S 2800,4000,2800,4800,600,*,UP,ALU1 +S 2800,4000,2800,4800,400,a2,UP,CALU1 +S 2800,3200,2800,3200,400,a1,LEFT,CALU1 +S 2700,3200,3600,3200,400,*,RIGHT,ALU1 +S 2600,4100,2600,6400,400,n2,UP,PDIF +S 2300,3900,2300,6600,200,t03,UP,PTRANS +S 2000,5600,2000,5600,400,z,LEFT,CALU1 +S 2000,4100,2900,4100,400,*,RIGHT,ALU1 +S 2000,4000,2900,4000,400,*,RIGHT,ALU1 +S 2000,4000,2000,4000,400,a2,LEFT,CALU1 +S 2000,3200,2000,4100,400,*,UP,ALU1 +S 2000,2400,2000,2400,400,b,LEFT,CALU1 +S 1300,5200,1300,6600,200,t05,UP,PTRANS +S 1300,4200,1300,5200,200,*,UP,POLY +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1200,3200,1200,4000,400,b,UP,CALU1 +S 1200,2400,2100,2400,400,*,RIGHT,ALU1 +S 1200,2400,1200,4400,400,*,UP,ALU1 +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 0,6800,4000,6800,800,*,RIGHT,ALU1 +S 0,5400,4000,5400,4400,*,RIGHT,NWELL +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,400,4000,400,800,*,RIGHT,ALU1 +V 500,1500,CONT_DIF_N,* +V 1500,1500,CONT_DIF_N,n1 +V 2500,900,CONT_DIF_N,* +V 800,6300,CONT_DIF_P,* +V 3500,6300,CONT_DIF_P,* +V 3500,5600,CONT_DIF_P,* +V 3500,3200,CONT_POLY,* +V 3500,1500,CONT_DIF_N,n1 +V 2000,3300,CONT_POLY,* +V 1800,5600,CONT_DIF_P,* +V 1200,4300,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/oai21v0x1.vbe b/pdks/symbolic/vsclib/cells/oai21v0x1.vbe new file mode 100755 index 000000000..ea0a5f436 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21v0x1.vbe @@ -0,0 +1,38 @@ +ENTITY oai21v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a1_z : NATURAL := 3100; + CONSTANT rdown_a2_z : NATURAL := 3110; + CONSTANT rdown_b_z : NATURAL := 2880; + CONSTANT rup_a1_z : NATURAL := 4320; + CONSTANT rup_a2_z : NATURAL := 4320; + CONSTANT rup_b_z : NATURAL := 4250; + CONSTANT tphl_b_z : NATURAL := 40; + CONSTANT tphl_a2_z : NATURAL := 44; + CONSTANT tplh_a1_z : NATURAL := 69; + CONSTANT tplh_b_z : NATURAL := 50; + CONSTANT tplh_a2_z : NATURAL := 60; + CONSTANT tphl_a1_z : NATURAL := 53; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai21v0x1; + +ARCHITECTURE behaviour_data_flow OF oai21v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai21v0x1" + SEVERITY WARNING; + z <= not (((a1 or a2) and b)) after 144 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oai21v0x4.ap b/pdks/symbolic/vsclib/cells/oai21v0x4.ap new file mode 100755 index 000000000..26a2bc547 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21v0x4.ap @@ -0,0 +1,172 @@ +V ALLIANCE : 6 +H oai21v0x4,P, 5/ 7/2024,100 +A 0,0,10400,7200 +R 9200,4000,ref_ref,a1_40 +R 9200,3200,ref_ref,a1_32 +R 9200,2400,ref_ref,a2_24 +R 8400,4000,ref_ref,a1_40 +R 8400,2400,ref_ref,a2_24 +R 7600,5600,ref_ref,z_56 +R 7600,4800,ref_ref,z_48 +R 7600,4000,ref_ref,a1_40 +R 7600,3200,ref_ref,a2_32 +R 6800,4800,ref_ref,z_48 +R 6800,4000,ref_ref,a1_40 +R 6800,3200,ref_ref,a2_32 +R 6000,4800,ref_ref,z_48 +R 6000,4000,ref_ref,a1_40 +R 5200,4800,ref_ref,z_48 +R 5200,3200,ref_ref,a1_32 +R 4400,5600,ref_ref,z_56 +R 4400,4800,ref_ref,z_48 +R 4400,3200,ref_ref,a1_32 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 3600,4800,ref_ref,z_48 +R 3600,3200,ref_ref,a1_32 +R 2800,4800,ref_ref,z_48 +R 2800,3200,ref_ref,a1_32 +R 2000,4800,ref_ref,z_48 +R 2000,4000,ref_ref,b_40 +R 1200,4800,ref_ref,z_48 +R 1200,3200,ref_ref,b_32 +S 3000,2000,3000,2700,1000,*,UP,TALU7 +S 3000,3200,3000,3700,200,*,DOWN,POLY +S 3500,1500,3500,2300,600,*,UP,ALU1 +S 9400,4000,9400,5600,600,*,UP,PDIF +S 9300,4800,9300,6800,600,*,UP,ALU1 +S 9200,700,9200,2400,200,t07,UP,NTRANS +S 9200,3200,9200,4000,600,*,UP,ALU1 +S 9200,3200,9200,4000,400,a1,UP,CALU1 +S 9200,300,9200,700,200,*,UP,POLY +S 9200,2400,9200,2400,400,a2,LEFT,CALU1 +S 8800,5800,8800,6200,200,*,UP,POLY +S 8800,3800,8800,5800,200,t04,UP,PTRANS +S 8800,3100,9400,3100,800,*,RIGHT,POLY +S 8600,500,8600,2200,600,*,UP,NDIF +S 8400,4000,8400,5600,400,n2d,UP,PDIF +S 8400,4000,8400,4000,400,a1,LEFT,CALU1 +S 8400,2400,8400,2400,400,a2,LEFT,CALU1 +S 8300,2400,9300,2400,400,*,RIGHT,ALU1 +S 8300,2400,8300,3200,400,*,UP,ALU1 +S 8100,5800,8100,6200,200,*,UP,POLY +S 8100,3800,8100,5800,200,t11,UP,PTRANS +S 8000,700,8000,2400,200,t06,UP,NTRANS +S 8000,300,8000,700,200,*,UP,POLY +S 8000,2800,9200,2800,200,*,RIGHT,POLY +S 7600,4800,7600,5700,600,*,UP,ALU1 +S 7600,4800,7600,5600,400,z,UP,CALU1 +S 7600,4000,7600,4000,400,a1,LEFT,CALU1 +S 7600,3200,7600,3200,400,a2,LEFT,CALU1 +S 7500,1500,9800,1500,400,*,RIGHT,ALU1 +S 7500,1500,7500,2300,400,*,UP,ALU1 +S 7100,3800,7100,6600,200,t10,UP,PTRANS +S 7000,3400,8100,3400,200,*,RIGHT,POLY +S 7000,300,7000,1200,200,*,UP,POLY +S 7000,2400,7000,3400,200,*,UP,POLY +S 7000,1200,7000,2400,200,t14,UP,NTRANS +S 6800,4800,6800,4800,400,z,LEFT,CALU1 +S 6800,4000,6800,4000,400,a1,LEFT,CALU1 +S 6800,3200,6800,3200,400,a2,LEFT,CALU1 +S 6700,4000,6700,6400,400,n2c,UP,PDIF +S 6700,3200,8300,3200,400,*,RIGHT,ALU1 +S 6500,400,6500,1500,600,*,UP,ALU1 +S 6400,3800,6400,6600,200,t03,UP,PTRANS +S 6000,4800,6000,4800,400,z,LEFT,CALU1 +S 6000,4000,6000,4000,400,a1,LEFT,CALU1 +S 6000,2400,6000,3200,200,*,UP,POLY +S 6000,1200,6000,2400,200,t05,UP,NTRANS +S 5900,5600,5900,6800,600,*,UP,ALU1 +S 5900,4000,9300,4000,400,*,RIGHT,ALU1 +S 5900,3200,5900,4000,400,*,UP,ALU1 +S 5500,1900,5500,2300,400,*,UP,ALU1 +S 5400,3800,5400,6600,200,t02,UP,PTRANS +S 5400,3400,6400,3400,200,*,RIGHT,POLY +S 5200,4800,5200,4800,400,z,LEFT,CALU1 +S 5200,3200,5200,3200,400,a1,LEFT,CALU1 +S 500,5600,500,6800,600,*,UP,ALU1 +S 500,4000,500,6400,600,*,UP,PDIF +S 500,1600,500,2300,600,*,UP,NDIF +S 500,1500,500,2300,600,*,UP,ALU1 +S 5000,700,5000,2400,200,t13,UP,NTRANS +S 5000,4000,5000,6400,400,n2b,UP,PDIF +S 5000,300,7000,300,200,*,RIGHT,POLY +S 4700,3800,4700,6600,200,t09,UP,PTRANS +S 4700,2800,4700,3800,200,*,UP,POLY +S 4500,400,4500,1100,400,*,UP,ALU1 +S 4400,4800,4400,5600,400,z,UP,CALU1 +S 4400,3200,4400,3200,400,a1,LEFT,CALU1 +S 4300,4800,4300,5700,600,*,UP,ALU1 +S 400,4800,7700,4800,400,*,RIGHT,ALU1 +S 400,1600,400,4000,400,z,UP,CALU1 +S 400,1500,400,4800,400,*,UP,ALU1 +S 400,1500,2600,1500,400,*,RIGHT,ALU1 +S 4000,700,4000,2400,200,t12,UP,NTRANS +S 4000,300,4000,700,200,*,UP,POLY +S 3700,3800,3700,6600,200,t08,UP,PTRANS +S 3700,2800,5000,2800,200,*,RIGHT,POLY +S 3700,2800,3700,3800,200,*,UP,POLY +S 3600,4800,3600,4800,400,z,LEFT,CALU1 +S 3600,3200,3600,3200,400,a1,LEFT,CALU1 +S 3300,4000,3300,6400,400,n2a,UP,PDIF +S 3000,700,3000,1800,200,t19,UP,NTRANS +S 3000,3800,3000,6600,200,t01,UP,PTRANS +S 3000,1800,3000,2200,200,*,UP,POLY +S 2800,4800,2800,4800,400,z,LEFT,CALU1 +S 2800,3200,2800,3200,400,a1,LEFT,CALU1 +S 2700,3200,5900,3200,400,*,RIGHT,ALU1 +S 2500,5600,2500,6800,600,*,UP,ALU1 +S 2000,700,2000,2600,200,t18,UP,NTRANS +S 2000,4800,2000,4800,400,z,LEFT,CALU1 +S 2000,4000,2000,4000,400,b,LEFT,CALU1 +S 2000,3800,2000,6600,200,t16,UP,PTRANS +S 2000,300,3000,300,200,*,RIGHT,POLY +S 1500,4800,1500,5600,400,*,UP,ALU1 +S 1400,2300,7500,2300,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1200,4000,2100,4000,400,*,RIGHT,ALU1 +S 1200,3200,1200,3200,400,b,LEFT,CALU1 +S 1200,3100,1200,4000,400,*,UP,ALU1 +S 1000,700,1000,2600,200,t17,UP,NTRANS +S 1000,3800,1000,6600,200,t15,UP,PTRANS +S 1000,3200,2000,3200,600,*,RIGHT,POLY +S 1000,300,1000,700,200,*,UP,POLY +S 0,6800,10400,6800,800,vdd,RIGHT,CALU1 +S 0,6800,10400,6800,800,*,RIGHT,ALU1 +S 0,5400,10400,5400,4400,*,RIGHT,NWELL +S 0,400,10400,400,800,vss,RIGHT,CALU1 +S 0,400,10400,400,800,*,RIGHT,ALU1 +V 9800,6600,CONT_BODY_N,* +V 9700,1500,CONT_DIF_N,n1 +V 9300,5500,CONT_DIF_P,* +V 9300,4800,CONT_DIF_P,* +V 9200,3200,CONT_POLY,* +V 8600,600,CONT_DIF_N,* +V 7600,5500,CONT_DIF_P,* +V 7600,4800,CONT_DIF_P,* +V 7500,2000,CONT_DIF_N,n1 +V 7200,3200,CONT_POLY,* +V 6500,1500,CONT_DIF_N,* +V 5900,6300,CONT_DIF_P,* +V 5900,5600,CONT_DIF_P,* +V 5800,3200,CONT_POLY,* +V 5500,2000,CONT_DIF_N,n1 +V 500,6300,CONT_DIF_P,* +V 500,5600,CONT_DIF_P,* +V 500,2300,CONT_DIF_N,* +V 500,1600,CONT_DIF_N,* +V 4500,1000,CONT_DIF_N,* +V 4200,5500,CONT_DIF_P,* +V 4200,4800,CONT_DIF_P,* +V 3500,1500,CONT_DIF_N,n1 +V 2800,3200,CONT_POLY,* +V 2500,6300,CONT_DIF_P,* +V 2500,5600,CONT_DIF_P,* +V 2500,1500,CONT_DIF_N,* +V 1500,5500,CONT_DIF_P,* +V 1500,4800,CONT_DIF_P,* +V 1500,2300,CONT_DIF_N,n1 +V 1200,3200,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/oai21v0x4.vbe b/pdks/symbolic/vsclib/cells/oai21v0x4.vbe new file mode 100755 index 000000000..957f86b4f --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai21v0x4.vbe @@ -0,0 +1,38 @@ +ENTITY oai21v0x4 IS +GENERIC ( + CONSTANT area : NATURAL := 7488; + CONSTANT cin_a1 : NATURAL := 18; + CONSTANT cin_a2 : NATURAL := 16; + CONSTANT cin_b : NATURAL := 12; + CONSTANT rdown_a1_z : NATURAL := 780; + CONSTANT rdown_a2_z : NATURAL := 780; + CONSTANT rdown_b_z : NATURAL := 720; + CONSTANT rup_a1_z : NATURAL := 1120; + CONSTANT rup_a2_z : NATURAL := 1120; + CONSTANT rup_b_z : NATURAL := 1060; + CONSTANT tphl_b_z : NATURAL := 38; + CONSTANT tphl_a2_z : NATURAL := 42; + CONSTANT tplh_a1_z : NATURAL := 67; + CONSTANT tplh_b_z : NATURAL := 47; + CONSTANT tplh_a2_z : NATURAL := 58; + CONSTANT tphl_a1_z : NATURAL := 51; + CONSTANT transistors : NATURAL := 19 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai21v0x4; + +ARCHITECTURE behaviour_data_flow OF oai21v0x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai21v0x4" + SEVERITY WARNING; + z <= not (((a1 or a2) and b)) after 74 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oai22v0x05.ap b/pdks/symbolic/vsclib/cells/oai22v0x05.ap new file mode 100755 index 000000000..1b00b0ce2 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai22v0x05.ap @@ -0,0 +1,103 @@ +V ALLIANCE : 6 +H oai22v0x05,P, 5/ 7/2024,100 +A 0,0,5600,7200 +R 1200,2400,ref_ref,z_24 +R 1200,4000,ref_ref,b1_40 +R 1200,5600,ref_ref,z_56 +R 2000,3200,ref_ref,b1_32 +R 2000,4800,ref_ref,b2_32 +R 2800,4000,ref_ref,b2_40 +R 3600,2400,ref_ref,a2_24 +R 3600,3200,ref_ref,a2_32 +R 3600,5600,ref_ref,a1_56 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +R 4400,2400,ref_ref,a2_24 +R 4400,4000,ref_ref,a1_40 +R 4400,4800,ref_ref,a1_48 +S 2300,600,2700,600,800,*,RIGHT,PTIE +S 3700,500,3700,2400,600,*,UP,NDIF +S 1500,1400,1500,2400,600,*,UP,NDIF +S 3100,2800,3100,3300,200,*,UP,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,1200,1000,1900,200,t08,UP,NTRANS +S 1000,1900,1000,4000,200,*,UP,POLY +S 1000,800,1000,1200,200,*,UP,POLY +S 1200,2400,1200,2400,400,z,LEFT,CALU1 +S 1200,3200,1200,4100,400,*,UP,ALU1 +S 1200,3200,2100,3200,400,*,RIGHT,ALU1 +S 1200,4000,1200,4000,400,b1,LEFT,CALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1400,4100,1400,4800,200,*,UP,POLY +S 1400,4800,1400,6400,200,t07,UP,PTRANS +S 1400,6400,1400,6800,200,*,UP,POLY +S 1700,5000,1700,6200,400,n2,UP,PDIF +S 2000,3200,2000,3200,400,b1,LEFT,CALU1 +S 2000,4000,2000,4900,400,*,UP,ALU1 +S 2000,4000,2900,4000,400,*,RIGHT,ALU1 +S 2000,4800,2000,4800,400,b2,LEFT,CALU1 +S 2100,1500,2100,1900,200,*,UP,POLY +S 2100,1900,2100,2600,200,t06,UP,NTRANS +S 2100,2600,2100,3900,200,*,UP,POLY +S 2200,4100,2200,4800,200,*,UP,POLY +S 2200,4800,2200,6400,200,t05,UP,PTRANS +S 2200,6400,2200,6800,200,*,UP,POLY +S 2600,1500,2600,2300,400,*,UP,ALU1 +S 2800,4000,2800,4000,400,b2,LEFT,CALU1 +S 3100,1500,3100,1900,200,*,UP,POLY +S 3100,1900,3100,2600,200,t04,UP,NTRANS +S 3200,3200,3200,4600,200,*,UP,POLY +S 3200,3200,3700,3200,400,*,RIGHT,ALU1 +S 3200,4800,3200,6400,200,t03,UP,PTRANS +S 3200,6400,3200,6800,200,*,UP,POLY +S 3500,2400,4400,2400,600,*,RIGHT,ALU1 +S 3500,5000,3500,6200,400,n1,UP,PDIF +S 3600,2300,3600,3200,600,*,UP,ALU1 +S 3600,2400,3600,3200,400,a2,UP,CALU1 +S 3600,4800,3600,5700,400,*,UP,ALU1 +S 3600,4800,4500,4800,400,*,RIGHT,ALU1 +S 3600,500,3600,2400,400,*,UP,NDIF +S 3600,5600,3600,5600,400,a1,LEFT,CALU1 +S 4000,4200,4400,4200,600,*,RIGHT,POLY +S 4000,4800,4000,6400,200,t01,UP,PTRANS +S 4000,6400,4000,6800,200,*,UP,POLY +S 400,1500,4800,1500,400,*,RIGHT,ALU1 +S 400,2300,1700,2300,400,*,RIGHT,ALU1 +S 400,2300,400,5700,400,*,UP,ALU1 +S 400,2400,1700,2400,400,*,RIGHT,ALU1 +S 400,2400,400,5600,400,z,UP,CALU1 +S 400,5600,1200,5600,600,*,RIGHT,ALU1 +S 400,5700,2800,5700,400,*,RIGHT,ALU1 +S 4200,1100,4200,1800,200,t02,UP,NTRANS +S 4200,1800,4200,3800,200,*,UP,POLY +S 4200,700,4200,1100,200,*,UP,POLY +S 4400,2400,4400,2400,400,a2,LEFT,CALU1 +S 4400,4000,4400,4800,400,a1,UP,CALU1 +S 4400,4000,4400,4800,600,*,UP,ALU1 +S 4500,5000,4500,6200,600,*,UP,PDIF +S 4500,6000,4500,6800,400,*,UP,ALU1 +S 4700,1300,4700,1600,600,*,UP,NDIF +S 500,1400,500,1700,600,*,UP,NDIF +S 700,5000,700,6700,600,*,UP,PDIF +S 800,5000,800,6700,600,*,UP,PDIF +V 1200,4000,CONT_POLY,* +V 1600,2300,CONT_DIF_N,* +V 2300,4000,CONT_POLY,* +V 2500,600,CONT_BODY_P,* +V 2600,2200,CONT_DIF_N,n3 +V 2700,5700,CONT_DIF_P,* +V 3300,3200,CONT_POLY,* +V 3600,600,CONT_DIF_N,* +V 4300,4200,CONT_POLY,* +V 4500,6100,CONT_DIF_P,* +V 4700,1500,CONT_DIF_N,n3 +V 500,1500,CONT_DIF_N,n3 +V 800,6600,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/oai22v0x05.vbe b/pdks/symbolic/vsclib/cells/oai22v0x05.vbe new file mode 100755 index 000000000..29d2fc0ee --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai22v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY oai22v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_b1 : NATURAL := 3; + CONSTANT cin_b2 : NATURAL := 3; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT rdown_b1_z : NATURAL := 4930; + CONSTANT rdown_b2_z : NATURAL := 4930; + CONSTANT rdown_a1_z : NATURAL := 4880; + CONSTANT rdown_a2_z : NATURAL := 4880; + CONSTANT rup_b1_z : NATURAL := 7340; + CONSTANT rup_b2_z : NATURAL := 7310; + CONSTANT rup_a1_z : NATURAL := 7340; + CONSTANT rup_a2_z : NATURAL := 7330; + CONSTANT tphl_a2_z : NATURAL := 61; + CONSTANT tphl_b2_z : NATURAL := 51; + CONSTANT tplh_b1_z : NATURAL := 69; + CONSTANT tphl_a1_z : NATURAL := 69; + CONSTANT tplh_b2_z : NATURAL := 58; + CONSTANT tphl_b1_z : NATURAL := 60; + CONSTANT tplh_a1_z : NATURAL := 88; + CONSTANT tplh_a2_z : NATURAL := 78; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai22v0x05; + +ARCHITECTURE behaviour_data_flow OF oai22v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai22v0x05" + SEVERITY WARNING; + z <= not (((b1 or b2) and (a1 or a2))) after 220 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oai23av0x05.ap b/pdks/symbolic/vsclib/cells/oai23av0x05.ap new file mode 100755 index 000000000..3f9589026 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai23av0x05.ap @@ -0,0 +1,138 @@ +V ALLIANCE : 6 +H oai23av0x05,P,24/ 6/2024,100 +A 0,0,7200,7200 +R 400,1600,ref_ref,a2_16 +R 2800,4000,ref_ref,b2_40 +R 6000,3200,ref_ref,b1_32 +R 5200,4000,ref_ref,b1_40 +R 2800,2400,ref_ref,z_24 +R 3600,4000,ref_ref,b2_40 +R 6000,4800,ref_ref,b2_48 +R 5200,4800,ref_ref,b2_48 +R 4400,4800,ref_ref,b2_48 +R 3600,4800,ref_ref,b2_48 +R 2000,4800,ref_ref,z_48 +R 2000,3200,ref_ref,z_32 +R 2000,4000,ref_ref,z_40 +R 400,2400,ref_ref,a2_24 +R 1200,2400,ref_ref,a2_24 +R 1200,3200,ref_ref,a2_32 +S 5800,4300,5800,4900,200,*,DOWN,POLY +S 2600,2900,2600,4000,200,*,UP,POLY +S 1400,2900,1400,3600,200,*,DOWN,POLY +S 1600,4900,1600,6100,400,n3,UP,PDIF +S 3200,4900,3200,6100,400,n2,UP,PDIF +S 6200,2500,6200,4100,200,*,UP,POLY +S 1900,3600,1900,4700,200,*,DOWN,POLY +S 2900,4200,2900,4700,200,*,DOWN,POLY +S 3600,4300,4900,4300,200,*,RIGHT,POLY +S 400,1600,400,2400,400,a2,UP,CALU1 +S 400,1500,400,2500,400,*,DOWN,ALU1 +S 800,500,800,2300,600,*,UP,NDIF +S 700,500,700,2300,600,*,UP,NDIF +S 1400,1800,1400,2500,200,t05,UP,NTRANS +S 1400,1400,1400,1800,200,*,DOWN,POLY +S 3600,6300,3600,6700,200,*,UP,POLY +S 2900,6300,2900,6700,200,*,UP,POLY +S 1900,6300,1900,6700,200,*,UP,POLY +S 1200,6300,1200,6700,200,*,UP,POLY +S 1200,4100,1200,5700,400,*,UP,ALU1 +S 700,4300,1200,4300,200,*,LEFT,POLY +S 500,4100,1200,4100,400,*,RIGHT,ALU1 +S 500,5200,500,6800,400,*,UP,ALU1 +S 5800,1600,5800,2300,400,n1,UP,NDIF +S 4200,4900,4200,6700,600,*,DOWN,PDIF +S 3600,4700,3600,6300,200,t07,UP,PTRANS +S 2900,4700,2900,6300,200,t01,UP,PTRANS +S 500,4900,500,6100,600,*,DOWN,PDIF +S 1200,4700,1200,6300,200,t03,UP,PTRANS +S 1900,4700,1900,6300,200,t04,UP,PTRANS +S 2000,3100,2000,5000,400,*,DOWN,ALU1 +S 2000,5000,2500,5000,400,*,RIGHT,ALU1 +S 6800,2400,6800,5700,400,*,UP,ALU1 +S 1200,5700,6800,5700,400,*,RIGHT,ALU1 +S 5000,3900,5000,4100,600,*,DOWN,ALU1 +S 5100,4000,5300,4000,400,*,LEFT,ALU1 +S 4300,3100,4600,3100,400,*,RIGHT,ALU1 +S 400,2400,1200,2400,600,*,RIGHT,ALU1 +S 4800,6200,4800,6600,200,*,UP,POLY +S 5800,6200,5800,6600,200,*,UP,POLY +S 2800,4000,2800,4000,400,b2,LEFT,CALU1 +S 6000,4800,6000,4800,400,b2,LEFT,CALU1 +S 5200,4800,5200,4800,400,b2,LEFT,CALU1 +S 4400,4800,4400,4800,400,b2,LEFT,CALU1 +S 3600,4000,3600,4800,400,b2,UP,CALU1 +S 6000,3200,6000,3200,400,b1,LEFT,CALU1 +S 2800,2400,2800,2400,400,z,LEFT,CALU1 +S 6400,5100,6400,6700,600,*,DOWN,PDIF +S 6500,5100,6500,6700,600,*,DOWN,PDIF +S 2800,600,3600,600,600,*,LEFT,PTIE +S 3500,3900,3500,4800,400,*,UP,ALU1 +S 3600,3900,3600,4800,400,*,UP,ALU1 +S 2800,4000,3600,4000,600,*,RIGHT,ALU1 +S 0,5400,7200,5400,4400,*,RIGHT,NWELL +S 3600,2900,3600,4600,200,*,UP,POLY +S 3500,4800,6100,4800,400,*,RIGHT,ALU1 +S 1400,3600,1900,3600,200,*,LEFT,POLY +S 1200,2300,1200,3300,400,*,DOWN,ALU1 +S 0,6800,7200,6800,800,vdd,RIGHT,CALU1 +S 0,6800,7200,6800,800,*,RIGHT,ALU1 +S 0,400,7200,400,800,vss,RIGHT,CALU1 +S 0,400,7200,400,800,*,RIGHT,ALU1 +S 4800,4900,4800,6200,200,t09,UP,PTRANS +S 5800,4900,5800,6200,200,t11,UP,PTRANS +S 1200,2400,1200,3200,400,a2,UP,CALU1 +S 2000,3200,2000,4800,400,z,UP,CALU1 +S 6700,2200,6700,2400,600,*,UP,ALU1 +S 6200,1400,6200,2500,200,t12,UP,NTRANS +S 5500,1400,5500,2500,200,t10,UP,NTRANS +S 6200,1000,6200,1400,200,*,DOWN,POLY +S 5500,1000,5500,1400,200,*,DOWN,POLY +S 5000,400,5000,1700,600,*,DOWN,ALU1 +S 5000,1600,5000,2300,600,*,UP,NDIF +S 3900,1500,3900,2200,400,*,DOWN,ALU1 +S 3400,1800,3400,2500,200,t06,UP,NTRANS +S 4400,1800,4400,2500,200,t08,UP,NTRANS +S 4400,1400,4400,1800,200,*,DOWN,POLY +S 3400,2900,3600,2900,200,*,RIGHT,POLY +S 3400,3000,3600,3000,200,*,RIGHT,POLY +S 3400,1400,3400,1800,200,*,DOWN,POLY +S 2900,2200,2900,3100,600,*,UP,ALU1 +S 2400,1800,2400,2500,200,t02,UP,NTRANS +S 2400,1400,2400,1800,200,*,DOWN,POLY +S 2400,2900,2600,2900,200,*,RIGHT,POLY +S 2400,3000,2600,3000,200,*,RIGHT,POLY +S 1900,1500,1900,2200,400,*,DOWN,ALU1 +S 1900,1500,3900,1500,400,*,LEFT,ALU1 +S 5300,3200,6100,3200,400,*,RIGHT,ALU1 +S 5300,3200,5300,4000,400,*,UP,ALU1 +S 4600,2400,6800,2400,400,*,RIGHT,ALU1 +S 2000,3100,3000,3100,400,*,RIGHT,ALU1 +S 5200,4000,5200,4000,400,b1,LEFT,CALU1 +S 4800,4200,4800,4900,200,*,DOWN,POLY +S 4600,2400,4600,3100,400,*,DOWN,ALU1 +S 6100,4200,6100,4800,400,*,DOWN,ALU1 +S 5200,3400,5500,3400,200,*,LEFT,POLY +S 5200,3400,5200,4200,200,*,UP,POLY +S 5500,2500,5500,3400,200,*,UP,POLY +V 600,4100,CONT_POLY,b +V 5300,5700,CONT_DIF_P,b +V 6700,2200,CONT_DIF_N,b +V 800,600,CONT_DIF_N,* +V 1200,3100,CONT_POLY,* +V 500,5300,CONT_DIF_P,* +V 500,6000,CONT_DIF_P,* +V 2400,5000,CONT_DIF_P,* +V 3600,600,CONT_BODY_P,* +V 2800,600,CONT_BODY_P,* +V 5000,4100,CONT_POLY,* +V 6400,6600,CONT_DIF_P,* +V 2800,4000,CONT_POLY,* +V 4200,6600,CONT_DIF_P,* +V 5000,1700,CONT_DIF_N,* +V 3900,2100,CONT_DIF_N,n4 +V 2900,2200,CONT_DIF_N,* +V 1900,2100,CONT_DIF_N,n4 +V 4400,3100,CONT_POLY,* +V 6100,4300,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/oai23av0x05.vbe b/pdks/symbolic/vsclib/cells/oai23av0x05.vbe new file mode 100755 index 000000000..7ee49eab3 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai23av0x05.vbe @@ -0,0 +1,42 @@ +ENTITY oai23av0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5184; + CONSTANT cin_b1 : NATURAL := 6; + CONSTANT cin_b2 : NATURAL := 6; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT rdown_b1_z : NATURAL := 4940; + CONSTANT rdown_b2_z : NATURAL := 4900; + CONSTANT rdown_a2_z : NATURAL := 8140; + CONSTANT rup_b1_z : NATURAL := 7300; + CONSTANT rup_b2_z : NATURAL := 7270; + CONSTANT rup_a2_z : NATURAL := 8030; + CONSTANT tphl_a2_z : NATURAL := 165; + CONSTANT tphl_b2_z : NATURAL := 51; + CONSTANT tpll_b2_z : NATURAL := 127; + CONSTANT tplh_b1_z : NATURAL := 65; + CONSTANT tphh_b1_z : NATURAL := 120; + CONSTANT tplh_a2_z : NATURAL := 238; + CONSTANT tplh_b2_z : NATURAL := 57; + CONSTANT tphh_b2_z : NATURAL := 119; + CONSTANT tphl_b1_z : NATURAL := 58; + CONSTANT tpll_b1_z : NATURAL := 132; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + b1 : in BIT; + b2 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai23av0x05; + +ARCHITECTURE behaviour_data_flow OF oai23av0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai23av0x05" + SEVERITY WARNING; + z <= (not b1 and not b2) or (not a2 and (b1 and b2)) after 234 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oai31v0x05.ap b/pdks/symbolic/vsclib/cells/oai31v0x05.ap new file mode 100755 index 000000000..1e93366f9 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai31v0x05.ap @@ -0,0 +1,98 @@ +V ALLIANCE : 6 +H oai31v0x05,P, 5/ 7/2024,100 +A 0,0,5600,7200 +R 1200,3200,ref_ref,b_32 +R 1200,4800,ref_ref,z_48 +R 2000,2400,ref_ref,b_24 +R 2000,4000,ref_ref,a3_40 +R 2800,4000,ref_ref,a3_40 +R 2800,4800,ref_ref,a3_48 +R 2800,5600,ref_ref,a3_56 +R 3600,2400,ref_ref,a2_24 +R 3600,3200,ref_ref,a2_32 +R 3600,4800,ref_ref,a1_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,2400,ref_ref,a2_24 +R 4400,4000,ref_ref,a1_40 +R 4400,4800,ref_ref,a1_48 +S 1400,5200,1400,6100,800,*,DOWN,TALU8 +S 2000,1900,2000,3300,200,*,UP,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,1000,1000,1900,200,t08,UP,NTRANS +S 1000,1900,1000,3200,200,*,UP,POLY +S 1000,600,1000,1000,200,*,UP,POLY +S 1200,2400,1200,3300,400,*,UP,ALU1 +S 1200,2400,2100,2400,400,*,RIGHT,ALU1 +S 1200,3200,1200,3200,400,b,LEFT,CALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1300,4900,2000,4900,400,*,RIGHT,ALU1 +S 1400,1500,3800,1500,400,*,RIGHT,ALU1 +S 1400,3200,1400,4600,200,*,UP,POLY +S 1400,4600,1400,5700,200,t07,UP,PTRANS +S 1400,5700,1400,6100,200,*,UP,POLY +S 2000,1000,2000,1900,200,t06,UP,NTRANS +S 2000,2400,2000,2400,400,b,LEFT,CALU1 +S 2000,4000,2000,4000,400,a3,LEFT,CALU1 +S 2000,4000,2800,4000,600,*,RIGHT,ALU1 +S 2000,600,2000,1000,200,*,UP,POLY +S 2300,3300,2300,4100,600,*,UP,ALU1 +S 2400,3900,2400,6600,200,t05,UP,PTRANS +S 2600,500,2600,1700,600,*,UP,NDIF +S 2700,4100,2700,6400,400,n2,UP,PDIF +S 2800,3900,2800,5700,400,*,UP,ALU1 +S 2800,4000,2800,5600,400,a3,UP,CALU1 +S 3100,2300,3100,3900,200,*,UP,POLY +S 3100,3900,3100,6600,200,t03,UP,PTRANS +S 3200,1000,3200,1900,200,t04,UP,NTRANS +S 3200,600,3200,1000,200,*,UP,POLY +S 3400,2500,3600,2500,600,*,RIGHT,ALU1 +S 3400,4100,3400,6400,400,n1,UP,PDIF +S 3600,2300,3600,3300,400,*,UP,ALU1 +S 3600,2300,4500,2300,400,*,RIGHT,ALU1 +S 3600,2400,3600,3200,400,a2,UP,CALU1 +S 3600,2400,4500,2400,400,*,RIGHT,ALU1 +S 3600,4800,3600,4800,400,a1,LEFT,CALU1 +S 3600,4800,4500,4800,600,*,RIGHT,ALU1 +S 3800,3500,4400,3500,200,*,RIGHT,POLY +S 3800,3900,3800,6600,200,t01,UP,PTRANS +S 400,1500,400,4900,400,*,UP,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,4800,1200,4800,600,*,RIGHT,ALU1 +S 400,4900,2000,4900,400,*,RIGHT,ALU1 +S 4200,1000,4200,1900,200,t02,UP,NTRANS +S 4200,1900,4200,3500,200,*,UP,POLY +S 4200,600,4200,1000,200,*,UP,POLY +S 4400,2400,4400,2400,400,a2,LEFT,CALU1 +S 4400,3200,4400,4900,400,*,UP,ALU1 +S 4400,4000,4400,4800,400,a1,UP,CALU1 +S 4400,5600,4400,6800,600,*,UP,ALU1 +S 4500,3200,4500,4900,400,*,UP,ALU1 +S 4500,4100,4500,6400,600,*,UP,PDIF +S 4700,1200,4700,1700,600,*,UP,NDIF +S 4700,400,4700,1400,400,*,UP,ALU1 +S 500,1500,500,1700,400,*,UP,ALU1 +S 800,4800,800,5700,600,*,UP,PDIF +S 800,5600,800,6800,600,*,UP,ALU1 +V 1200,3200,CONT_POLY,* +V 1500,1500,CONT_DIF_N,n3 +V 1900,4900,CONT_DIF_P,* +V 2300,3300,CONT_POLY,* +V 2600,600,CONT_DIF_N,* +V 3400,2500,CONT_POLY,* +V 3700,1500,CONT_DIF_N,n3 +V 4400,3300,CONT_POLY,* +V 4400,5600,CONT_DIF_P,* +V 4400,6300,CONT_DIF_P,* +V 4700,1300,CONT_DIF_N,* +V 500,1600,CONT_DIF_N,* +V 600,6600,CONT_BODY_N,* +V 800,5600,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/oai31v0x05.vbe b/pdks/symbolic/vsclib/cells/oai31v0x05.vbe new file mode 100755 index 000000000..8b265c6d3 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai31v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY oai31v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_a3 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT rdown_b_z : NATURAL := 3630; + CONSTANT rdown_a3_z : NATURAL := 4190; + CONSTANT rdown_a2_z : NATURAL := 4180; + CONSTANT rdown_a1_z : NATURAL := 4280; + CONSTANT rup_b_z : NATURAL := 5430; + CONSTANT rup_a3_z : NATURAL := 6510; + CONSTANT rup_a2_z : NATURAL := 6510; + CONSTANT rup_a1_z : NATURAL := 6510; + CONSTANT tphl_a1_z : NATURAL := 71; + CONSTANT tphl_a3_z : NATURAL := 50; + CONSTANT tplh_b_z : NATURAL := 52; + CONSTANT tphl_a2_z : NATURAL := 64; + CONSTANT tplh_a3_z : NATURAL := 67; + CONSTANT tphl_b_z : NATURAL := 45; + CONSTANT tplh_a2_z : NATURAL := 89; + CONSTANT tplh_a1_z : NATURAL := 97; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + b : in BIT; + a3 : in BIT; + a2 : in BIT; + a1 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai31v0x05; + +ARCHITECTURE behaviour_data_flow OF oai31v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai31v0x05" + SEVERITY WARNING; + z <= not(b and ((a1 or a2) or a3)) after 196 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oai31v0x1.ap b/pdks/symbolic/vsclib/cells/oai31v0x1.ap new file mode 100755 index 000000000..3f2fa39da --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai31v0x1.ap @@ -0,0 +1,138 @@ +V ALLIANCE : 6 +H oai31v0x1,P,22/ 6/2024,100 +A 0,0,7200,7200 +R 1200,3200,ref_ref,b_32 +R 1200,4000,ref_ref,b_40 +R 1200,5600,ref_ref,z_56 +R 2000,3200,ref_ref,a1_32 +R 2000,4800,ref_ref,b_48 +R 2000,5600,ref_ref,z_56 +R 2800,4000,ref_ref,a1_40 +R 2800,5600,ref_ref,z_56 +R 3600,2400,ref_ref,a2_24 +R 3600,4800,ref_ref,a1_48 +R 3600,5600,ref_ref,z_56 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,2400,ref_ref,a2_24 +R 4400,3200,ref_ref,a3_32 +R 4400,4000,ref_ref,a3_40 +R 4400,4800,ref_ref,a1_48 +R 4400,5600,ref_ref,z_56 +R 5200,2400,ref_ref,a2_24 +R 5200,4000,ref_ref,a3_40 +R 5200,4800,ref_ref,a1_48 +R 6000,2400,ref_ref,a2_24 +R 6000,4800,ref_ref,a1_48 +R 6800,1600,ref_ref,a2_16 +R 6800,4000,ref_ref,a1_40 +S 1000,2700,1000,3600,200,*,UP,POLY +S 5400,2700,5400,3300,200,*,DOWN,POLY +S 5100,2300,5100,2900,200,*,UP,POLY +S 0,400,7200,400,800,*,RIGHT,ALU1 +S 0,400,7200,400,800,vss,RIGHT,CALU1 +S 0,5400,7200,5400,4400,*,RIGHT,NWELL +S 0,6800,7200,6800,800,*,RIGHT,ALU1 +S 0,6800,7200,6800,800,vdd,RIGHT,CALU1 +S 1000,1000,1000,2600,200,t11,UP,NTRANS +S 1000,3800,1000,5700,200,t10,UP,PTRANS +S 1000,600,1000,1000,200,*,UP,POLY +S 1200,3100,1200,4800,400,*,UP,ALU1 +S 1200,3200,1200,4000,400,b,UP,CALU1 +S 1200,4800,2100,4800,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1500,1500,1500,2400,400,*,UP,ALU1 +S 1500,1500,4700,1500,400,*,RIGHT,ALU1 +S 1600,4200,1600,6400,600,*,UP,PDIF +S 1700,6300,1700,6800,600,*,UP,ALU1 +S 2000,1000,2000,2600,200,t03,UP,NTRANS +S 2000,2600,2000,3500,200,*,UP,POLY +S 2000,3200,2000,3200,400,a1,LEFT,CALU1 +S 2000,4000,3300,4000,400,*,RIGHT,ALU1 +S 2000,4800,2000,4800,400,b,LEFT,CALU1 +S 2000,5600,2000,5600,400,z,LEFT,CALU1 +S 2000,600,2000,1000,200,*,UP,POLY +S 2100,3100,2100,4000,600,*,UP,ALU1 +S 2300,4000,2300,6600,200,t01,UP,PTRANS +S 2700,4200,2700,6400,400,n1a,UP,PDIF +S 2800,4000,2800,4000,400,a1,LEFT,CALU1 +S 2800,5600,2800,5600,400,z,LEFT,CALU1 +S 3000,2800,3000,4000,200,*,UP,POLY +S 3000,4000,3000,6600,200,t04,UP,PTRANS +S 3000,500,3000,2000,1400,*,UP,NDIF +S 3200,2400,3200,2900,400,*,UP,ALU1 +S 3200,2400,6800,2400,400,*,RIGHT,ALU1 +S 3300,4000,3300,4800,400,*,UP,ALU1 +S 3300,4800,6800,4800,400,*,RIGHT,ALU1 +S 3400,4200,3400,6400,400,n2a,UP,PDIF +S 3600,2400,3600,2400,400,a2,LEFT,CALU1 +S 3600,4800,3600,4800,400,a1,LEFT,CALU1 +S 3600,5600,3600,5600,400,z,LEFT,CALU1 +S 3700,3600,4700,3600,200,*,RIGHT,POLY +S 3700,4000,3700,6600,200,t07,UP,PTRANS +S 400,1500,400,5600,400,*,UP,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,5600,4500,5600,400,*,RIGHT,ALU1 +S 4100,2200,4100,3600,200,*,UP,POLY +S 4100,600,4100,2200,200,t09,UP,NTRANS +S 4300,4000,5300,4000,400,*,RIGHT,ALU1 +S 4400,2400,4400,2400,400,a2,LEFT,CALU1 +S 4400,3200,4400,4000,400,a3,UP,CALU1 +S 4400,3200,4400,4000,600,*,UP,ALU1 +S 4400,4800,4400,4800,400,a1,LEFT,CALU1 +S 4400,5600,4400,5600,400,z,LEFT,CALU1 +S 4700,4000,4700,6600,200,t08,UP,PTRANS +S 500,1500,500,2300,600,*,UP,ALU1 +S 500,1600,500,2300,600,*,UP,NDIF +S 500,4600,500,5600,400,*,UP,ALU1 +S 500,4700,500,5400,600,*,UP,PDIF +S 5100,4200,5100,6400,400,n2b,UP,PDIF +S 5100,600,5100,2200,200,t06,UP,NTRANS +S 5200,2400,5200,2400,400,a2,LEFT,CALU1 +S 5200,4000,5200,4000,400,a3,LEFT,CALU1 +S 5200,4800,5200,4800,400,a1,LEFT,CALU1 +S 5300,2400,5300,2900,400,*,UP,ALU1 +S 5400,2700,5400,4000,200,*,UP,POLY +S 5400,4000,5400,6600,200,t05,UP,PTRANS +S 5600,400,5600,1600,600,*,UP,ALU1 +S 5600,800,5600,2000,600,*,UP,NDIF +S 5800,4200,5800,6400,400,n1b,UP,PDIF +S 6000,2400,6000,2400,400,a2,LEFT,CALU1 +S 6000,4800,6000,4800,400,a1,LEFT,CALU1 +S 6100,3600,6800,3600,200,*,RIGHT,POLY +S 6100,4000,6100,6600,200,t02,UP,PTRANS +S 6600,500,6600,2200,600,*,UP,PTIE +S 6600,5600,6600,6800,600,*,UP,ALU1 +S 6700,3300,6700,4800,400,*,UP,ALU1 +S 6700,4200,6700,6400,600,*,UP,PDIF +S 6800,1500,6800,2400,400,*,UP,ALU1 +S 6800,1600,6800,1600,400,a2,LEFT,CALU1 +S 6800,3300,6800,4800,400,*,UP,ALU1 +S 6800,4000,6800,4000,400,a1,LEFT,CALU1 +V 1200,3200,CONT_POLY,* +V 1500,1600,CONT_DIF_N,n3 +V 1500,2300,CONT_DIF_N,n3 +V 1700,6300,CONT_DIF_P,* +V 2200,3400,CONT_POLY,* +V 2600,600,CONT_DIF_N,* +V 3200,2800,CONT_POLY,* +V 3500,600,CONT_DIF_N,* +V 4200,5600,CONT_DIF_P,* +V 4300,3400,CONT_POLY,* +V 4600,1500,CONT_DIF_N,n3 +V 500,1600,CONT_DIF_N,* +V 500,2300,CONT_DIF_N,* +V 500,4700,CONT_DIF_P,* +V 500,5400,CONT_DIF_P,* +V 5300,2800,CONT_POLY,* +V 5600,1600,CONT_DIF_N,* +V 5600,900,CONT_DIF_N,* +V 600,6600,CONT_BODY_N,* +V 6600,5600,CONT_DIF_P,* +V 6600,600,CONT_BODY_P,* +V 6600,6300,CONT_DIF_P,* +V 6700,3400,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/oai31v0x1.vbe b/pdks/symbolic/vsclib/cells/oai31v0x1.vbe new file mode 100755 index 000000000..e9b74cb53 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oai31v0x1.vbe @@ -0,0 +1,44 @@ +ENTITY oai31v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 5184; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a3 : NATURAL := 8; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT cin_a1 : NATURAL := 9; + CONSTANT rdown_b_z : NATURAL := 2040; + CONSTANT rdown_a3_z : NATURAL := 2350; + CONSTANT rdown_a2_z : NATURAL := 2350; + CONSTANT rdown_a1_z : NATURAL := 2400; + CONSTANT rup_b_z : NATURAL := 3150; + CONSTANT rup_a3_z : NATURAL := 3370; + CONSTANT rup_a2_z : NATURAL := 3380; + CONSTANT rup_a1_z : NATURAL := 3380; + CONSTANT tphl_a1_z : NATURAL := 74; + CONSTANT tphl_a3_z : NATURAL := 51; + CONSTANT tplh_b_z : NATURAL := 53; + CONSTANT tphl_a2_z : NATURAL := 66; + CONSTANT tplh_a3_z : NATURAL := 63; + CONSTANT tphl_b_z : NATURAL := 47; + CONSTANT tplh_a2_z : NATURAL := 85; + CONSTANT tplh_a1_z : NATURAL := 95; + CONSTANT transistors : NATURAL := 11 +); +PORT ( + b : in BIT; + a3 : in BIT; + a2 : in BIT; + a1 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oai31v0x1; + +ARCHITECTURE behaviour_data_flow OF oai31v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oai31v0x1" + SEVERITY WARNING; + z <= not(b and ((a1 or a2) or a3)) after 137 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oan21bv0x05.ap b/pdks/symbolic/vsclib/cells/oan21bv0x05.ap new file mode 100755 index 000000000..9c693341c --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oan21bv0x05.ap @@ -0,0 +1,97 @@ +V ALLIANCE : 6 +H oan21bv0x05,P,23/ 6/2024,100 +A 0,0,5600,7200 +R 4400,2400,ref_ref,a2_24 +R 5200,2400,ref_ref,a2_24 +R 1200,5600,ref_ref,z_56 +R 400,5600,ref_ref,z_56 +R 400,4800,ref_ref,z_48 +R 2000,4000,ref_ref,b_40 +R 2800,4000,ref_ref,a1_40 +R 3600,4800,ref_ref,a1_48 +R 2800,4800,ref_ref,a1_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 1200,3200,ref_ref,b_32 +R 5200,3200,ref_ref,a2_32 +S 3000,1900,3000,4200,200,*,DOWN,POLY +S 500,4900,500,5600,600,*,UP,PDIF +S 500,4800,500,5700,400,*,DOWN,ALU1 +S 3600,2500,3600,3600,400,*,UP,ALU1 +S 4400,3600,4400,5500,400,*,UP,ALU1 +S 3600,3600,4400,3600,400,*,RIGHT,ALU1 +S 2400,5900,2400,6800,400,*,UP,ALU1 +S 4000,2500,4700,2500,600,*,LEFT,POLY +S 3700,4000,4000,4000,200,*,LEFT,POLY +S 4000,1900,4000,4000,200,*,UP,POLY +S 3700,6400,3700,6800,200,*,UP,POLY +S 3000,6400,3000,6800,200,*,UP,POLY +S 2500,4600,2500,6200,800,*,DOWN,PDIF +S 3700,4400,3700,6400,200,t01,UP,PTRANS +S 3000,4400,3000,6400,200,t03,UP,PTRANS +S 3300,4600,3300,6200,400,n1,UP,PDIF +S 4500,400,4500,1600,600,*,DOWN,ALU1 +S 4400,2400,5200,2400,600,*,RIGHT,ALU1 +S 4400,2400,4400,2400,400,a2,LEFT,CALU1 +S 1200,3200,1200,3200,400,b,LEFT,CALU1 +S 1200,3100,1200,3600,400,*,UP,ALU1 +S 2000,3600,2000,4100,400,*,UP,ALU1 +S 1200,3600,2000,3600,400,*,RIGHT,ALU1 +S 3500,1500,3500,2500,400,*,UP,ALU1 +S 2100,2500,3600,2500,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 400,5600,1200,5600,600,*,RIGHT,ALU1 +S 400,2400,400,5600,400,z,UP,CALU1 +S 2000,4000,2000,4000,400,b,LEFT,CALU1 +S 3600,4800,3600,4800,400,a1,LEFT,CALU1 +S 2800,4000,2800,4800,400,a1,UP,CALU1 +S 1300,1600,1300,2300,400,*,UP,ALU1 +S 1300,1600,1600,1600,400,*,LEFT,ALU1 +S 400,2300,1300,2300,400,*,LEFT,ALU1 +S 1000,900,1000,1300,200,*,DOWN,POLY +S 2000,1900,2000,4000,200,*,DOWN,POLY +S 1000,1900,1000,4400,200,*,DOWN,POLY +S 2000,900,2000,1300,200,*,DOWN,POLY +S 4000,900,4000,1300,200,*,DOWN,POLY +S 3000,900,3000,1300,200,*,DOWN,POLY +S 2500,400,2500,1700,400,*,DOWN,ALU1 +S 4000,1300,4000,1900,200,t02,UP,NTRANS +S 3000,1300,3000,1900,200,t04,UP,NTRANS +S 2000,1300,2000,1900,200,t08,UP,NTRANS +S 1000,1300,1000,1900,200,t06,UP,NTRANS +S 500,400,500,1600,600,*,DOWN,ALU1 +S 1700,6400,1700,6800,200,*,UP,POLY +S 1000,6400,1000,6800,200,*,UP,POLY +S 2800,3700,2800,4900,400,*,UP,ALU1 +S 1700,4000,2000,4000,200,*,RIGHT,POLY +S 2800,4800,3600,4800,600,*,RIGHT,ALU1 +S 400,2300,400,5700,400,*,UP,ALU1 +S 1700,4400,1700,6400,200,t07,UP,PTRANS +S 1000,4400,1000,6400,200,t05,UP,PTRANS +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 5200,2400,5200,3200,400,a2,UP,CALU1 +S 5200,2300,5200,3300,400,*,DOWN,ALU1 +S 4400,4600,4400,5300,600,*,DOWN,PDIF +S 1300,4600,1300,6200,400,n2,UP,PDIF +V 500,4900,CONT_DIF_P,* +V 500,5600,CONT_DIF_P,* +V 2400,6000,CONT_DIF_P,* +V 5000,6600,CONT_BODY_N,* +V 4500,2500,CONT_POLY,* +V 2200,2500,CONT_POLY,an +V 4500,1600,CONT_DIF_N,* +V 2500,1600,CONT_DIF_N,* +V 3500,1600,CONT_DIF_N,an +V 1500,1600,CONT_DIF_N,* +V 500,1600,CONT_DIF_N,* +V 2800,3800,CONT_POLY,* +V 1200,3200,CONT_POLY,* +V 5000,600,CONT_BODY_P,* +V 4400,4700,CONT_DIF_P,an +V 4400,5400,CONT_DIF_P,an +EOF diff --git a/pdks/symbolic/vsclib/cells/oan21bv0x05.vbe b/pdks/symbolic/vsclib/cells/oan21bv0x05.vbe new file mode 100755 index 000000000..50044f522 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oan21bv0x05.vbe @@ -0,0 +1,38 @@ +ENTITY oan21bv0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a2 : NATURAL := 4; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a2_z : NATURAL := 3930; + CONSTANT rdown_a1_z : NATURAL := 3930; + CONSTANT rdown_b_z : NATURAL := 3850; + CONSTANT rup_a2_z : NATURAL := 5830; + CONSTANT rup_a1_z : NATURAL := 5830; + CONSTANT rup_b_z : NATURAL := 5810; + CONSTANT tphl_b_z : NATURAL := 42; + CONSTANT tplh_b_z : NATURAL := 47; + CONSTANT tpll_a2_z : NATURAL := 114; + CONSTANT tphh_a1_z : NATURAL := 108; + CONSTANT tpll_a1_z : NATURAL := 123; + CONSTANT tphh_a2_z : NATURAL := 96; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a2 : in BIT; + a1 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oan21bv0x05; + +ARCHITECTURE behaviour_data_flow OF oan21bv0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oan21bv0x05" + SEVERITY WARNING; + z <= not b and (a1 or a2) after 210 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/oan21v0x05.ap b/pdks/symbolic/vsclib/cells/oan21v0x05.ap new file mode 100755 index 000000000..62092d73b --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oan21v0x05.ap @@ -0,0 +1,102 @@ +V ALLIANCE : 6 +H oan21v0x05,P, 5/ 7/2024,100 +A 0,0,6400,7200 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 5200,2400,ref_ref,a2_24 +R 4400,2400,ref_ref,a2_24 +R 4400,3200,ref_ref,a2_32 +R 6000,4000,ref_ref,a1_40 +R 5200,4000,ref_ref,a1_40 +R 3600,4000,ref_ref,b_40 +R 4400,4800,ref_ref,b_48 +R 1200,4000,ref_ref,z_40 +R 6000,3200,ref_ref,a1_32 +S 3100,5400,3100,6200,800,*,DOWN,TALU8 +S 1900,1700,1900,2900,800,*,UP,TALU7 +S 5200,1900,5200,4100,200,*,UP,POLY +S 5300,5200,5300,6300,600,*,DOWN,PDIF +S 5200,5400,5200,6800,400,*,UP,ALU1 +S 3200,4000,3600,4000,600,*,RIGHT,ALU1 +S 4000,3200,4600,3200,600,*,LEFT,POLY +S 4700,4200,5200,4200,200,*,RIGHT,POLY +S 4700,4200,4700,5000,200,*,DOWN,POLY +S 2500,5500,3600,5500,400,*,LEFT,ALU1 +S 2500,2200,2500,5500,400,*,UP,ALU1 +S 4700,6500,4700,6900,200,*,UP,POLY +S 4000,6500,4000,6900,200,*,UP,POLY +S 4700,5000,4700,6500,200,t01,UP,PTRANS +S 4400,5200,4400,6300,400,n2,UP,PDIF +S 4000,2600,4000,5000,200,*,UP,POLY +S 3000,5800,3000,6200,200,*,UP,POLY +S 3000,2600,3000,5000,200,*,UP,POLY +S 3000,5000,3000,5800,200,t05,UP,PTRANS +S 4000,5000,4000,6500,200,t03,UP,PTRANS +S 2000,4000,2000,5800,1400,*,DOWN,PDIF +S 4400,4400,4400,4900,400,*,UP,ALU1 +S 1600,4900,1600,6800,600,*,UP,ALU1 +S 600,5900,600,6700,600,*,DOWN,NTIE +S 1000,5000,1000,5400,200,*,UP,POLY +S 1000,3800,1000,5000,200,t07,UP,PTRANS +S 3600,4000,3600,4000,400,b,LEFT,CALU1 +S 3600,3900,3600,4400,400,*,UP,ALU1 +S 3600,4400,4400,4400,400,*,RIGHT,ALU1 +S 4000,1500,4000,1900,200,*,DOWN,POLY +S 3000,1500,3000,1900,200,*,DOWN,POLY +S 5700,1400,5700,1700,600,*,UP,NDIF +S 5200,1200,5200,1900,200,t02,UP,NTRANS +S 2500,2100,2500,2400,600,*,DOWN,NDIF +S 4000,1900,4000,2600,200,t04,UP,NTRANS +S 3000,1900,3000,2600,200,t06,UP,NTRANS +S 5200,800,5200,1200,200,*,DOWN,POLY +S 4600,500,4600,2400,600,*,UP,NDIF +S 3500,1500,5800,1500,400,*,LEFT,ALU1 +S 3500,1500,3500,2300,400,*,UP,ALU1 +S 400,4000,1300,4000,400,*,RIGHT,ALU1 +S 400,4100,1300,4100,400,*,RIGHT,ALU1 +S 600,600,1400,600,600,*,RIGHT,PTIE +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,400,6400,400,800,*,RIGHT,ALU1 +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 1000,2000,1000,2600,200,t08,UP,NTRANS +S 4400,2400,5200,2400,600,*,LEFT,ALU1 +S 4400,2300,4400,3300,400,*,UP,ALU1 +S 1500,400,1500,2400,400,*,DOWN,ALU1 +S 6000,3100,6000,4100,400,*,DOWN,ALU1 +S 5200,4000,6000,4000,600,*,RIGHT,ALU1 +S 400,1500,400,4100,400,*,UP,ALU1 +S 1000,3200,1500,3200,600,*,RIGHT,POLY +S 1000,1600,1000,2000,200,*,DOWN,POLY +S 400,2300,500,2300,600,*,LEFT,ALU1 +S 400,1600,400,4000,400,z,UP,CALU1 +S 6000,3200,6000,4000,400,a1,UP,CALU1 +S 4400,2400,4400,3200,400,a2,UP,CALU1 +S 4400,4800,4400,4800,400,b,LEFT,CALU1 +S 5200,4000,5200,4000,400,a1,LEFT,CALU1 +S 5200,2400,5200,2400,400,a2,LEFT,CALU1 +S 1200,4000,1200,4000,400,z,LEFT,CALU1 +S 1400,3200,2500,3200,400,*,RIGHT,ALU1 +V 5200,6200,CONT_DIF_P,* +V 5200,5500,CONT_DIF_P,* +V 3200,4000,CONT_POLY,* +V 3500,5500,CONT_DIF_P,zn +V 1600,5700,CONT_DIF_P,* +V 1600,4900,CONT_DIF_P,* +V 500,4100,CONT_DIF_P,* +V 5700,1500,CONT_DIF_N,n1 +V 4600,600,CONT_DIF_N,* +V 3500,2200,CONT_DIF_N,n1 +V 2500,2300,CONT_DIF_N,zn +V 600,600,CONT_BODY_P,* +V 1400,600,CONT_BODY_P,* +V 500,2300,CONT_DIF_N,* +V 1500,2300,CONT_DIF_N,* +V 4400,3200,CONT_POLY,* +V 1500,3200,CONT_POLY,zn +V 600,6600,CONT_BODY_N,* +V 5400,4000,CONT_POLY,* +EOF diff --git a/pdks/symbolic/vsclib/cells/oan21v0x05.vbe b/pdks/symbolic/vsclib/cells/oan21v0x05.vbe new file mode 100755 index 000000000..4ea7db281 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/oan21v0x05.vbe @@ -0,0 +1,38 @@ +ENTITY oan21v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_a1 : NATURAL := 3; + CONSTANT cin_a2 : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT rdown_a1_z : NATURAL := 3980; + CONSTANT rdown_a2_z : NATURAL := 3980; + CONSTANT rdown_b_z : NATURAL := 3940; + CONSTANT rup_a1_z : NATURAL := 5000; + CONSTANT rup_a2_z : NATURAL := 4970; + CONSTANT rup_b_z : NATURAL := 4970; + CONSTANT tphh_b_z : NATURAL := 79; + CONSTANT tpll_b_z : NATURAL := 102; + CONSTANT tpll_a1_z : NATURAL := 128; + CONSTANT tphh_a2_z : NATURAL := 87; + CONSTANT tpll_a2_z : NATURAL := 120; + CONSTANT tphh_a1_z : NATURAL := 98; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END oan21v0x05; + +ARCHITECTURE behaviour_data_flow OF oan21v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oan21v0x05" + SEVERITY WARNING; + z <= (a1 or a2) and b after 214 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/or2v0x05.ap b/pdks/symbolic/vsclib/cells/or2v0x05.ap new file mode 100755 index 000000000..c3a5c9b71 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or2v0x05.ap @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H or2v0x05,P,23/ 6/2024,100 +A 0,0,4000,7200 +R 1200,5600,ref_ref,z_56 +R 2000,4000,ref_ref,a_40 +R 2800,3200,ref_ref,b_32 +R 2800,4800,ref_ref,a_48 +R 3600,3200,ref_ref,b_32 +R 3600,4000,ref_ref,b_40 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +S 2300,4000,2300,4800,200,*,UP,POLY +S 2000,2100,2000,4000,200,*,UP,POLY +S 0,400,4000,400,800,*,RIGHT,ALU1 +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,5400,4000,5400,4400,*,RIGHT,NWELL +S 0,6800,4000,6800,800,*,RIGHT,ALU1 +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 1000,1500,1000,2100,200,t06,UP,NTRANS +S 1000,2100,1000,4500,200,*,UP,POLY +S 1000,4500,1000,5700,200,t05,UP,PTRANS +S 1200,2500,1200,4800,400,*,UP,ALU1 +S 1200,2500,2500,2500,400,*,RIGHT,ALU1 +S 1200,4800,2000,4800,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1500,400,1500,1800,600,*,UP,ALU1 +S 1600,4700,1600,6400,600,*,UP,PDIF +S 1700,6300,1700,6800,600,*,UP,ALU1 +S 1900,4000,2800,4000,400,*,RIGHT,ALU1 +S 2000,1500,2000,2100,200,t02,UP,NTRANS +S 2000,4000,2000,4000,400,a,LEFT,CALU1 +S 2000,4800,2000,5600,400,*,UP,ALU1 +S 2000,5600,3600,5600,400,*,RIGHT,ALU1 +S 2300,4800,2300,6600,200,t01,UP,PTRANS +S 2500,1700,2500,2500,400,*,UP,ALU1 +S 2600,5000,2600,6400,400,n1,UP,PDIF +S 2700,3200,3600,3200,400,*,RIGHT,ALU1 +S 2800,3200,2800,3200,400,b,LEFT,CALU1 +S 2800,4000,2800,4900,400,*,UP,ALU1 +S 2800,4800,2800,4800,400,a,LEFT,CALU1 +S 3000,1500,3000,2100,200,t04,UP,NTRANS +S 3000,2100,3000,4800,200,*,UP,POLY +S 3000,4800,3000,6600,200,t03,UP,PTRANS +S 3500,400,3500,1800,600,*,UP,ALU1 +S 3600,3100,3600,4100,400,*,UP,ALU1 +S 3600,3200,3600,4000,400,b,UP,CALU1 +S 400,1500,400,5600,400,*,UP,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,5600,1300,5600,400,*,RIGHT,ALU1 +S 500,1500,500,1900,400,*,UP,ALU1 +S 500,5300,500,5600,400,*,UP,ALU1 +S 600,600,3400,600,600,*,RIGHT,PTIE +V 1200,3300,CONT_POLY,zn +V 1500,1800,CONT_DIF_N,* +V 1700,6300,CONT_DIF_P,* +V 2200,4000,CONT_POLY,* +V 2500,1800,CONT_DIF_N,zn +V 3200,3200,CONT_POLY,* +V 3400,600,CONT_BODY_P,* +V 3500,1800,CONT_DIF_N,* +V 3500,5600,CONT_DIF_P,zn +V 500,1800,CONT_DIF_N,* +V 500,5400,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/or2v0x05.vbe b/pdks/symbolic/vsclib/cells/or2v0x05.vbe new file mode 100755 index 000000000..997b32f12 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or2v0x05.vbe @@ -0,0 +1,32 @@ +ENTITY or2v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 3920; + CONSTANT rdown_b_z : NATURAL := 3920; + CONSTANT rup_a_z : NATURAL := 4970; + CONSTANT rup_b_z : NATURAL := 4960; + CONSTANT tpll_a_z : NATURAL := 107; + CONSTANT tphh_b_z : NATURAL := 74; + CONSTANT tpll_b_z : NATURAL := 97; + CONSTANT tphh_a_z : NATURAL := 86; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END or2v0x05; + +ARCHITECTURE behaviour_data_flow OF or2v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on or2v0x05" + SEVERITY WARNING; + z <= (a or b) after 202 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/or2v0x1.ap b/pdks/symbolic/vsclib/cells/or2v0x1.ap new file mode 100755 index 000000000..52de1ec7d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or2v0x1.ap @@ -0,0 +1,81 @@ +V ALLIANCE : 6 +H or2v0x1,P, 5/ 7/2024,100 +A 0,0,4000,7200 +R 1200,5600,ref_ref,z_48 +R 2000,3200,ref_ref,a_32 +R 2000,4000,ref_ref,b_40 +R 2800,3200,ref_ref,a_32 +R 2800,4000,ref_ref,b_40 +R 3600,2400,ref_ref,a_24 +R 3600,4800,ref_ref,b_48 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +S 1900,600,1900,1700,800,*,UP,TALU7 +S 2300,3100,2300,3700,200,*,DOWN,POLY +S 2000,2700,2000,3300,200,*,UP,POLY +S 1000,2800,1000,3600,200,*,UP,POLY +S 0,400,4000,400,800,*,RIGHT,ALU1 +S 0,400,4000,400,800,vss,RIGHT,CALU1 +S 0,5400,4000,5400,4400,*,RIGHT,NWELL +S 0,6800,4000,6800,800,*,RIGHT,ALU1 +S 0,6800,4000,6800,800,vdd,RIGHT,CALU1 +S 1000,1300,1000,1700,200,*,UP,POLY +S 1000,1700,1000,2600,200,t6,UP,NTRANS +S 1000,3800,1000,5600,200,t5,UP,PTRANS +S 1000,5600,1000,6000,200,*,UP,POLY +S 1200,2300,1200,4800,400,*,UP,ALU1 +S 1200,2300,2600,2300,400,*,RIGHT,ALU1 +S 1200,4800,2300,4800,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1500,900,1500,2400,400,*,UP,NDIF +S 1600,4000,1600,6400,600,*,UP,PDIF +S 1600,400,1600,1000,600,*,UP,ALU1 +S 1600,6300,1600,6800,600,*,UP,ALU1 +S 1900,3200,3600,3200,400,*,RIGHT,ALU1 +S 1900,4000,3600,4000,400,*,RIGHT,ALU1 +S 2000,1600,2000,2000,200,*,UP,POLY +S 2000,2000,2000,2600,200,t02,UP,NTRANS +S 2000,3200,2000,3200,400,a,LEFT,CALU1 +S 2000,4000,2000,4000,400,b,LEFT,CALU1 +S 2300,3300,2300,4500,200,*,UP,POLY +S 2300,4500,2300,6600,200,t01,UP,PTRANS +S 2300,4800,2300,5600,400,*,UP,ALU1 +S 2300,5600,3600,5600,400,*,RIGHT,ALU1 +S 2600,4700,2600,6400,400,n1,UP,PDIF +S 2800,3200,2800,3200,400,a,LEFT,CALU1 +S 2800,4000,2800,4000,400,b,LEFT,CALU1 +S 3000,1600,3000,2000,200,*,UP,POLY +S 3000,2000,3000,2600,200,t04,UP,NTRANS +S 3000,2600,3000,4000,200,*,UP,POLY +S 3000,4500,3000,6600,200,t03,UP,PTRANS +S 3200,3900,3200,4000,600,*,UP,ALU1 +S 3500,400,3500,1000,600,*,UP,ALU1 +S 3500,900,3500,2400,400,*,UP,NDIF +S 3600,2300,3600,3200,400,*,UP,ALU1 +S 3600,2400,3600,2400,400,a,LEFT,CALU1 +S 3600,4000,3600,4900,400,*,UP,ALU1 +S 3600,4800,3600,4800,400,b,LEFT,CALU1 +S 3600,900,3600,2400,400,*,UP,NDIF +S 400,2200,400,5700,400,*,UP,ALU1 +S 400,2400,400,5600,400,z,UP,CALU1 +S 400,5600,1300,5600,400,*,RIGHT,ALU1 +S 500,2200,500,2400,400,*,UP,ALU1 +S 500,4500,500,5300,600,*,UP,PDIF +S 500,4500,500,5600,400,*,UP,ALU1 +V 1200,3200,CONT_POLY,zn +V 1600,1000,CONT_DIF_N,* +V 1600,6300,CONT_DIF_P,* +V 2200,3200,CONT_POLY,* +V 2500,2300,CONT_DIF_N,zn +V 3200,3900,CONT_POLY,* +V 3500,1000,CONT_DIF_N,* +V 3500,5600,CONT_DIF_P,zn +V 500,2300,CONT_DIF_N,* +V 500,4600,CONT_DIF_P,* +V 500,5300,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/or2v0x1.vbe b/pdks/symbolic/vsclib/cells/or2v0x1.vbe new file mode 100755 index 000000000..a8dd09b1b --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or2v0x1.vbe @@ -0,0 +1,32 @@ +ENTITY or2v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2880; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 2660; + CONSTANT rdown_b_z : NATURAL := 2670; + CONSTANT rup_a_z : NATURAL := 3330; + CONSTANT rup_b_z : NATURAL := 3320; + CONSTANT tpll_a_z : NATURAL := 104; + CONSTANT tphh_b_z : NATURAL := 79; + CONSTANT tpll_b_z : NATURAL := 95; + CONSTANT tphh_a_z : NATURAL := 91; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + a : in BIT; + b : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END or2v0x1; + +ARCHITECTURE behaviour_data_flow OF or2v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on or2v0x1" + SEVERITY WARNING; + z <= (a or b) after 167 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/or3v0x05.ap b/pdks/symbolic/vsclib/cells/or3v0x05.ap new file mode 100755 index 000000000..b82d08677 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or3v0x05.ap @@ -0,0 +1,94 @@ +V ALLIANCE : 6 +H or3v0x05,P,23/ 6/2024,100 +A 0,0,5600,7200 +R 1200,5600,ref_ref,z_56 +R 2000,3200,ref_ref,a_32 +R 2800,4000,ref_ref,a_40 +R 3600,2400,ref_ref,b_24 +R 3600,3200,ref_ref,b_32 +R 3600,4800,ref_ref,c_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,2400,ref_ref,b_24 +R 4400,4000,ref_ref,c_40 +R 4400,4800,ref_ref,c_48 +S 2500,3100,2500,3500,200,*,DOWN,POLY +S 1400,3800,1400,4400,200,*,DOWN,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,1200,1000,1800,200,t08,UP,NTRANS +S 1000,1800,1000,4000,200,*,UP,POLY +S 1000,800,1000,1200,200,*,UP,POLY +S 1200,2300,1200,4200,400,*,UP,ALU1 +S 1200,2300,2400,2300,400,*,RIGHT,ALU1 +S 1200,4200,2000,4200,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1400,4500,1400,5700,200,t07,UP,PTRANS +S 1400,5800,1400,6200,200,*,UP,POLY +S 1500,400,1500,1500,600,*,UP,ALU1 +S 1900,3200,2800,3200,400,*,RIGHT,ALU1 +S 1900,3300,2800,3300,400,*,RIGHT,ALU1 +S 1900,4200,1900,6300,400,*,UP,PDIF +S 2000,1200,2000,1800,200,t02,UP,NTRANS +S 2000,1800,2000,3200,200,*,UP,POLY +S 2000,3200,2000,3200,400,a,LEFT,CALU1 +S 2000,4200,2000,4900,400,*,UP,ALU1 +S 2000,4900,2800,4900,400,*,RIGHT,ALU1 +S 2000,6100,2000,6800,400,*,UP,ALU1 +S 2000,800,2000,1200,200,*,UP,POLY +S 2400,1500,2400,2300,400,*,UP,ALU1 +S 2400,1500,4800,1500,400,*,RIGHT,ALU1 +S 2500,3300,2500,4000,200,*,UP,POLY +S 2500,4000,2500,6500,200,t01,UP,PTRANS +S 2500,6500,2500,6900,200,*,UP,POLY +S 2800,3200,2800,4100,400,*,UP,ALU1 +S 2800,4000,2800,4000,400,a,LEFT,CALU1 +S 2800,4200,2800,6300,400,n1,UP,PDIF +S 2800,4900,2800,5700,400,*,UP,ALU1 +S 2800,5700,4500,5700,400,*,RIGHT,ALU1 +S 3000,1200,3000,1800,200,t04,UP,NTRANS +S 3000,2400,3500,2400,600,*,RIGHT,POLY +S 3000,800,3000,1200,200,*,UP,POLY +S 3200,2300,3200,4000,200,*,UP,POLY +S 3200,2400,4500,2400,400,*,RIGHT,ALU1 +S 3200,4000,3200,6500,200,t03,UP,PTRANS +S 3200,6500,3200,6900,200,*,UP,POLY +S 3500,4200,3500,6300,400,n2,UP,PDIF +S 3600,2400,3600,3200,400,b,UP,CALU1 +S 3600,2400,3600,3300,400,*,UP,ALU1 +S 3600,4800,3600,4800,400,c,LEFT,CALU1 +S 3600,4800,4400,4800,600,*,RIGHT,ALU1 +S 3600,500,3600,1600,600,*,UP,NDIF +S 3900,3600,4400,3600,200,*,RIGHT,POLY +S 3900,4000,3900,6500,200,t05,UP,PTRANS +S 3900,6500,3900,6900,200,*,UP,POLY +S 400,1500,400,5600,400,*,UP,ALU1 +S 400,1500,600,1500,400,*,RIGHT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,5500,1300,5500,600,*,RIGHT,ALU1 +S 4200,1200,4200,1800,200,t06,UP,NTRANS +S 4200,1800,4200,3600,200,*,UP,POLY +S 4200,800,4200,1200,200,*,UP,POLY +S 4400,2400,4400,2400,400,b,LEFT,CALU1 +S 4400,3300,4400,4900,400,*,UP,ALU1 +S 4400,4000,4400,4800,400,c,UP,CALU1 +V 1200,3900,CONT_POLY,zn +V 1500,1500,CONT_DIF_N,* +V 2000,6200,CONT_DIF_P,* +V 2200,3200,CONT_POLY,* +V 2500,1500,CONT_DIF_N,zn +V 3300,2400,CONT_POLY,* +V 3600,600,CONT_DIF_N,* +V 4400,3400,CONT_POLY,* +V 4400,5700,CONT_DIF_P,zn +V 4700,1500,CONT_DIF_N,zn +V 500,1500,CONT_DIF_N,* +V 600,6600,CONT_BODY_N,* +V 900,5400,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/or3v0x05.vbe b/pdks/symbolic/vsclib/cells/or3v0x05.vbe new file mode 100755 index 000000000..adeb9b6d1 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or3v0x05.vbe @@ -0,0 +1,38 @@ +ENTITY or3v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 4; + CONSTANT rdown_a_z : NATURAL := 4070; + CONSTANT rdown_b_z : NATURAL := 4070; + CONSTANT rdown_c_z : NATURAL := 4070; + CONSTANT rup_a_z : NATURAL := 5030; + CONSTANT rup_b_z : NATURAL := 4980; + CONSTANT rup_c_z : NATURAL := 4960; + CONSTANT tphh_c_z : NATURAL := 85; + CONSTANT tpll_a_z : NATURAL := 143; + CONSTANT tphh_b_z : NATURAL := 100; + CONSTANT tpll_b_z : NATURAL := 134; + CONSTANT tphh_a_z : NATURAL := 109; + CONSTANT tpll_c_z : NATURAL := 113; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END or3v0x05; + +ARCHITECTURE behaviour_data_flow OF or3v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on or3v0x05" + SEVERITY WARNING; + z <= ((a or b) or c) after 227 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/or3v0x1.ap b/pdks/symbolic/vsclib/cells/or3v0x1.ap new file mode 100755 index 000000000..3083e6122 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or3v0x1.ap @@ -0,0 +1,93 @@ +V ALLIANCE : 6 +H or3v0x1,P,22/ 6/2024,100 +A 0,0,5600,7200 +R 1200,5600,ref_ref,z_56 +R 2000,3200,ref_ref,a_32 +R 2800,4000,ref_ref,a_40 +R 3600,2400,ref_ref,b_24 +R 3600,3200,ref_ref,b_32 +R 3600,4800,ref_ref,c_48 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,2400,ref_ref,b_24 +R 4400,4000,ref_ref,c_40 +R 4400,4800,ref_ref,c_48 +S 1400,3100,1400,3700,200,*,DOWN,POLY +S 1000,2800,1000,3300,200,*,UP,POLY +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,1200,1000,2100,200,t08,UP,NTRANS +S 1000,2100,1000,3200,200,*,UP,POLY +S 1000,800,1000,1200,200,*,UP,POLY +S 1200,2300,1200,4200,400,*,UP,ALU1 +S 1200,2300,2400,2300,400,*,RIGHT,ALU1 +S 1200,4200,2000,4200,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1400,3800,1400,5700,200,t07,UP,PTRANS +S 1400,5700,1400,6100,200,*,UP,POLY +S 1500,1400,1500,1900,400,*,UP,NDIF +S 1500,400,1500,1500,600,*,UP,ALU1 +S 1900,3200,2800,3200,400,*,RIGHT,ALU1 +S 1900,3300,2800,3300,400,*,RIGHT,ALU1 +S 2000,1200,2000,1800,200,t02,UP,NTRANS +S 2000,1800,2000,3200,200,*,UP,POLY +S 2000,3200,2000,3200,400,a,LEFT,CALU1 +S 2000,4000,2000,6400,600,*,UP,PDIF +S 2000,4200,2000,4900,400,*,UP,ALU1 +S 2000,4900,2800,4900,400,*,RIGHT,ALU1 +S 2000,5800,2000,6800,400,*,UP,ALU1 +S 2000,800,2000,1200,200,*,UP,POLY +S 2400,1500,2400,2300,400,*,UP,ALU1 +S 2400,1500,4800,1500,400,*,RIGHT,ALU1 +S 2500,3300,2500,3800,200,*,UP,POLY +S 2500,3800,2500,6600,200,t01,UP,PTRANS +S 2800,3200,2800,4100,400,*,UP,ALU1 +S 2800,4000,2800,4000,400,a,LEFT,CALU1 +S 2800,4000,2800,6400,400,n1,UP,PDIF +S 2800,4900,2800,5700,400,*,UP,ALU1 +S 2800,5700,4500,5700,400,*,RIGHT,ALU1 +S 3000,1200,3000,1800,200,t04,UP,NTRANS +S 3000,2400,3300,2400,600,*,RIGHT,POLY +S 3000,800,3000,1200,200,*,UP,POLY +S 3200,2400,3200,3800,200,*,UP,POLY +S 3200,2400,4500,2400,400,*,RIGHT,ALU1 +S 3200,3800,3200,6600,200,t03,UP,PTRANS +S 3500,4000,3500,6400,400,n2,UP,PDIF +S 3600,2400,3600,3200,400,b,UP,CALU1 +S 3600,2400,3600,3300,400,*,UP,ALU1 +S 3600,4800,3600,4800,400,c,LEFT,CALU1 +S 3600,4800,4400,4800,600,*,RIGHT,ALU1 +S 3600,500,3600,1600,600,*,UP,NDIF +S 3900,3400,4200,3400,200,*,RIGHT,POLY +S 3900,3800,3900,6600,200,t05,UP,PTRANS +S 400,1500,400,5600,400,*,UP,ALU1 +S 400,1500,600,1500,400,*,RIGHT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,5500,1300,5500,600,*,RIGHT,ALU1 +S 4200,1200,4200,1800,200,t06,UP,NTRANS +S 4200,1800,4200,3400,200,*,UP,POLY +S 4200,800,4200,1200,200,*,UP,POLY +S 4300,3100,4300,4900,400,*,UP,ALU1 +S 4400,2400,4400,2400,400,b,LEFT,CALU1 +S 4400,3900,4400,4900,400,*,UP,ALU1 +S 4400,4000,4400,4800,400,c,UP,CALU1 +V 1200,3200,CONT_POLY,zn +V 1500,1500,CONT_DIF_N,* +V 2000,5900,CONT_DIF_P,* +V 2200,3200,CONT_POLY,* +V 2500,1500,CONT_DIF_N,zn +V 3300,2400,CONT_POLY,* +V 3600,600,CONT_DIF_N,* +V 4300,3200,CONT_POLY,* +V 4400,5700,CONT_DIF_P,zn +V 4700,1500,CONT_DIF_N,zn +V 500,1500,CONT_DIF_N,* +V 600,6600,CONT_BODY_N,* +V 900,5400,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/or3v0x1.vbe b/pdks/symbolic/vsclib/cells/or3v0x1.vbe new file mode 100755 index 000000000..1089ee2c9 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or3v0x1.vbe @@ -0,0 +1,38 @@ +ENTITY or3v0x1 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 5; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 2690; + CONSTANT rdown_b_z : NATURAL := 2690; + CONSTANT rdown_c_z : NATURAL := 2690; + CONSTANT rup_a_z : NATURAL := 3170; + CONSTANT rup_b_z : NATURAL := 3150; + CONSTANT rup_c_z : NATURAL := 3130; + CONSTANT tphh_c_z : NATURAL := 91; + CONSTANT tpll_a_z : NATURAL := 147; + CONSTANT tphh_b_z : NATURAL := 107; + CONSTANT tpll_b_z : NATURAL := 137; + CONSTANT tphh_a_z : NATURAL := 118; + CONSTANT tpll_c_z : NATURAL := 116; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END or3v0x1; + +ARCHITECTURE behaviour_data_flow OF or3v0x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on or3v0x1" + SEVERITY WARNING; + z <= ((a or b) or c) after 192 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/or3v0x2.ap b/pdks/symbolic/vsclib/cells/or3v0x2.ap new file mode 100755 index 000000000..acc9c61e8 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or3v0x2.ap @@ -0,0 +1,122 @@ +V ALLIANCE : 6 +H or3v0x2,P,22/ 6/2024,100 +A 0,0,7200,7200 +R 1200,4800,ref_ref,z_48 +R 2800,3200,ref_ref,a_32 +R 3600,2400,ref_ref,b_24 +R 3600,4000,ref_ref,a_40 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,3200,ref_ref,b_32 +R 4400,4000,ref_ref,a_40 +R 5200,2400,ref_ref,c_24 +R 5200,4000,ref_ref,a_40 +R 6000,1600,ref_ref,c_16 +R 6000,2400,ref_ref,c_24 +R 6000,3200,ref_ref,a_32 +R 6000,4000,ref_ref,a_40 +S 1000,2800,1000,3600,200,*,UP,POLY +S 0,400,7200,400,800,*,RIGHT,ALU1 +S 0,400,7200,400,800,vss,RIGHT,CALU1 +S 0,5400,7200,5400,4400,*,RIGHT,NWELL +S 0,6800,7200,6800,800,*,RIGHT,ALU1 +S 0,6800,7200,6800,800,vdd,RIGHT,CALU1 +S 1000,1200,1000,2600,200,t11,UP,NTRANS +S 1000,3800,1000,6600,200,t10,UP,PTRANS +S 1000,800,1000,1200,200,*,UP,POLY +S 1200,2300,1200,4000,400,*,UP,ALU1 +S 1200,2300,2500,2300,400,*,RIGHT,ALU1 +S 1200,4000,2000,4000,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1500,1200,1500,2400,400,*,UP,NDIF +S 1600,1200,1600,2400,400,*,UP,NDIF +S 1600,400,1600,1400,600,*,UP,ALU1 +S 1700,4000,1700,6400,600,*,UP,PDIF +S 1700,5600,1700,6800,600,*,UP,ALU1 +S 2000,4000,2000,4700,400,*,UP,ALU1 +S 2000,4700,4300,4700,400,*,RIGHT,ALU1 +S 2100,1000,2100,1800,200,t03,UP,NTRANS +S 2100,1800,2100,3300,200,*,UP,POLY +S 2100,600,2100,1000,200,*,UP,POLY +S 2200,3200,2800,3200,600,*,RIGHT,ALU1 +S 2300,3800,2300,6000,200,t01,UP,PTRANS +S 2300,6000,2300,6400,200,*,UP,POLY +S 2500,1500,2500,2300,400,*,UP,ALU1 +S 2500,1500,5100,1500,400,*,RIGHT,ALU1 +S 2700,4000,2700,5800,400,n1a,UP,PDIF +S 2800,3100,2800,4000,400,*,UP,ALU1 +S 2800,3200,2800,3200,400,a,LEFT,CALU1 +S 2800,4000,6100,4000,400,*,RIGHT,ALU1 +S 3000,2300,3000,3800,200,*,UP,POLY +S 3000,2400,3600,2400,600,*,RIGHT,POLY +S 3000,3800,3000,6000,200,t04,UP,PTRANS +S 3000,6000,3000,6900,200,*,UP,POLY +S 3000,6900,5400,6900,200,*,RIGHT,POLY +S 3100,1000,3100,1800,200,t06,UP,NTRANS +S 3100,600,3100,1000,200,*,UP,POLY +S 3400,4000,3400,5800,400,n2a,UP,PDIF +S 3600,2300,3600,3200,400,*,UP,ALU1 +S 3600,2400,3600,2400,400,b,LEFT,CALU1 +S 3600,3200,4500,3200,400,*,RIGHT,ALU1 +S 3600,4000,3600,4000,400,a,LEFT,CALU1 +S 3700,3400,4700,3400,200,*,RIGHT,POLY +S 3700,3800,3700,6000,200,t07,UP,PTRANS +S 3800,500,3800,1600,800,*,UP,NDIF +S 400,1500,400,4900,400,*,UP,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,4800,1200,4800,600,*,RIGHT,ALU1 +S 4200,4700,4200,5400,600,*,UP,ALU1 +S 4400,3200,4400,3200,400,b,LEFT,CALU1 +S 4400,4000,4400,4000,400,a,LEFT,CALU1 +S 4500,1000,4500,1800,200,t09,UP,NTRANS +S 4500,600,4500,1000,200,*,UP,POLY +S 4600,2300,4600,3400,400,*,UP,POLY +S 4600,2400,6100,2400,400,*,RIGHT,ALU1 +S 4700,3800,4700,5700,200,t08,UP,PTRANS +S 4700,5700,4700,6100,200,*,UP,POLY +S 5000,4100,5000,5500,400,n2b,UP,PDIF +S 500,1400,500,2400,600,*,UP,NDIF +S 500,1500,500,2400,400,*,UP,ALU1 +S 500,4000,500,4800,600,*,UP,PDIF +S 500,4000,500,4900,400,*,UP,ALU1 +S 5200,2400,5200,2400,400,c,LEFT,CALU1 +S 5200,4000,5200,4000,400,a,LEFT,CALU1 +S 5400,3400,5400,3800,200,*,UP,POLY +S 5400,3800,5400,5700,200,t05,UP,PTRANS +S 5400,5800,5400,6900,200,*,UP,POLY +S 5700,4000,5700,5500,400,n1b,UP,PDIF +S 5900,3200,6500,3200,400,*,RIGHT,ALU1 +S 6000,1600,6000,2400,400,c,UP,CALU1 +S 6000,1600,6000,2400,600,*,UP,ALU1 +S 6000,3200,6000,4000,400,a,UP,CALU1 +S 6000,3200,6000,4000,600,*,UP,ALU1 +S 6100,3200,6400,3200,600,*,RIGHT,POLY +S 6100,3800,6100,5700,200,t02,UP,PTRANS +S 6600,4700,6600,6800,600,*,UP,ALU1 +S 6600,500,6600,2200,600,*,UP,PTIE +S 6700,4000,6700,5500,600,*,UP,PDIF +V 1200,3200,CONT_POLY,zn +V 1600,1400,CONT_DIF_N,* +V 1700,5600,CONT_DIF_P,* +V 1700,6300,CONT_DIF_P,* +V 2200,3200,CONT_POLY,* +V 2600,1500,CONT_DIF_N,zn +V 3600,2400,CONT_POLY,* +V 3800,600,CONT_DIF_N,* +V 4200,4700,CONT_DIF_P,zn +V 4200,5400,CONT_DIF_P,zn +V 4700,2400,CONT_POLY,* +V 5000,1500,CONT_DIF_N,zn +V 500,1600,CONT_DIF_N,* +V 500,2300,CONT_DIF_N,* +V 500,4100,CONT_DIF_P,* +V 500,4800,CONT_DIF_P,* +V 6400,3200,CONT_POLY,* +V 6600,4700,CONT_DIF_P,* +V 6600,5400,CONT_DIF_P,* +V 6600,600,CONT_BODY_P,* +V 6600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/or3v0x2.vbe b/pdks/symbolic/vsclib/cells/or3v0x2.vbe new file mode 100755 index 000000000..6b368f88c --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or3v0x2.vbe @@ -0,0 +1,38 @@ +ENTITY or3v0x2 IS +GENERIC ( + CONSTANT area : NATURAL := 5184; + CONSTANT cin_a : NATURAL := 7; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_c : NATURAL := 6; + CONSTANT rdown_a_z : NATURAL := 1740; + CONSTANT rdown_b_z : NATURAL := 1740; + CONSTANT rdown_c_z : NATURAL := 1740; + CONSTANT rup_a_z : NATURAL := 2160; + CONSTANT rup_b_z : NATURAL := 2140; + CONSTANT rup_c_z : NATURAL := 2130; + CONSTANT tphh_c_z : NATURAL := 87; + CONSTANT tpll_a_z : NATURAL := 136; + CONSTANT tphh_b_z : NATURAL := 105; + CONSTANT tpll_b_z : NATURAL := 125; + CONSTANT tphh_a_z : NATURAL := 118; + CONSTANT tpll_c_z : NATURAL := 103; + CONSTANT transistors : NATURAL := 11 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END or3v0x2; + +ARCHITECTURE behaviour_data_flow OF or3v0x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on or3v0x2" + SEVERITY WARNING; + z <= ((a or b) or c) after 161 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/or3v4x05.ap b/pdks/symbolic/vsclib/cells/or3v4x05.ap new file mode 100755 index 000000000..1c668396d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or3v4x05.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H or3v4x05,P, 5/ 7/2024,100 +A 0,0,5600,7200 +R 1200,5600,ref_ref,z_56 +R 2000,3200,ref_ref,a_32 +R 2000,4000,ref_ref,a_40 +R 2800,4000,ref_ref,a_40 +R 3600,2400,ref_ref,c_24 +R 3600,3200,ref_ref,b_32 +R 400,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 400,5600,ref_ref,z_56 +R 4400,2400,ref_ref,c_24 +R 4400,3200,ref_ref,b_32 +R 4400,4000,ref_ref,b_40 +S 0,400,5600,400,800,*,RIGHT,ALU1 +S 0,400,5600,400,800,vss,RIGHT,CALU1 +S 0,5400,5600,5400,4400,*,RIGHT,NWELL +S 0,6800,5600,6800,800,*,RIGHT,ALU1 +S 0,6800,5600,6800,800,vdd,RIGHT,CALU1 +S 1000,1100,1000,1500,200,*,UP,POLY +S 1000,1500,1000,2100,200,t08,UP,NTRANS +S 1000,2100,1000,4800,200,*,UP,POLY +S 1000,4800,1000,6000,200,t07,UP,PTRANS +S 1000,6000,1000,6400,200,*,UP,POLY +S 1200,2500,1200,4800,400,*,UP,ALU1 +S 1200,2500,2500,2500,400,*,RIGHT,ALU1 +S 1200,4800,4300,4800,400,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,z,LEFT,CALU1 +S 1500,400,1500,1800,600,*,UP,ALU1 +S 1600,4700,1600,6700,600,*,UP,PDIF +S 1600,600,2600,600,600,*,RIGHT,PTIE +S 1700,4700,1700,6700,600,*,UP,PDIF +S 1900,4000,2900,4000,400,*,RIGHT,ALU1 +S 2000,1500,2000,2100,200,t02,UP,NTRANS +S 2000,2100,2000,3700,200,*,UP,POLY +S 2000,3200,2000,4000,400,a,UP,CALU1 +S 2000,3200,2000,4000,600,*,UP,ALU1 +S 2000,3900,2300,3900,600,*,RIGHT,POLY +S 2300,4500,2300,5500,200,t01,UP,PTRANS +S 2300,5500,2300,5900,200,*,UP,POLY +S 2500,1500,2500,2500,400,*,UP,ALU1 +S 2500,1500,4800,1500,400,*,RIGHT,ALU1 +S 2600,4700,2600,5300,400,n1,UP,PDIF +S 2700,6600,4600,6600,600,*,RIGHT,NTIE +S 2800,4000,2800,4000,400,a,LEFT,CALU1 +S 3000,1500,3000,2100,200,t04,UP,NTRANS +S 3000,2100,3000,4500,200,*,UP,POLY +S 3000,4500,3000,5500,200,t03,UP,PTRANS +S 3000,5500,3000,5900,200,*,UP,POLY +S 3100,3200,4500,3200,400,*,RIGHT,ALU1 +S 3300,4700,3300,5300,400,n2,UP,PDIF +S 3500,2400,4500,2400,400,*,RIGHT,ALU1 +S 3600,2400,3600,2400,400,c,LEFT,CALU1 +S 3600,3200,3600,3200,400,b,LEFT,CALU1 +S 3600,500,3600,1900,600,*,UP,NDIF +S 3700,4100,4200,4100,200,*,RIGHT,POLY +S 3700,4500,3700,5500,200,t05,UP,PTRANS +S 3700,5500,3700,5900,200,*,UP,POLY +S 400,1500,400,5700,400,*,UP,ALU1 +S 400,1600,400,5600,400,z,UP,CALU1 +S 400,1800,500,1800,600,*,RIGHT,ALU1 +S 400,5600,1300,5600,400,*,RIGHT,ALU1 +S 400,5700,1300,5700,400,*,RIGHT,ALU1 +S 4200,1200,4200,1800,200,t06,UP,NTRANS +S 4200,2300,4200,4100,200,*,UP,POLY +S 4200,800,4200,1200,200,*,UP,POLY +S 4400,2400,4400,2400,400,c,LEFT,CALU1 +S 4400,3200,4400,4000,400,b,UP,CALU1 +S 4400,3200,4400,4000,600,*,UP,ALU1 +V 1200,2800,CONT_POLY,zn +V 1500,1800,CONT_DIF_N,* +V 1600,600,CONT_BODY_P,* +V 1600,6600,CONT_DIF_P,* +V 2000,3900,CONT_POLY,* +V 2500,1800,CONT_DIF_N,zn +V 2600,600,CONT_BODY_P,* +V 2700,6600,CONT_BODY_N,* +V 3200,3200,CONT_POLY,* +V 3600,600,CONT_DIF_N,* +V 4200,4800,CONT_DIF_P,zn +V 4400,2400,CONT_POLY,* +V 4600,6600,CONT_BODY_N,* +V 4700,1500,CONT_DIF_N,zn +V 500,1800,CONT_DIF_N,* +V 500,5700,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/or3v4x05.vbe b/pdks/symbolic/vsclib/cells/or3v4x05.vbe new file mode 100755 index 000000000..48999c722 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or3v4x05.vbe @@ -0,0 +1,38 @@ +ENTITY or3v4x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4032; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_c : NATURAL := 3; + CONSTANT rdown_a_z : NATURAL := 4430; + CONSTANT rdown_b_z : NATURAL := 4440; + CONSTANT rdown_c_z : NATURAL := 4430; + CONSTANT rup_a_z : NATURAL := 4990; + CONSTANT rup_b_z : NATURAL := 4970; + CONSTANT rup_c_z : NATURAL := 4960; + CONSTANT tphh_c_z : NATURAL := 75; + CONSTANT tpll_a_z : NATURAL := 212; + CONSTANT tphh_b_z : NATURAL := 81; + CONSTANT tpll_b_z : NATURAL := 198; + CONSTANT tphh_a_z : NATURAL := 85; + CONSTANT tpll_c_z : NATURAL := 176; + CONSTANT transistors : NATURAL := 8 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END or3v4x05; + +ARCHITECTURE behaviour_data_flow OF or3v4x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on or3v4x05" + SEVERITY WARNING; + z <= ((a or b) or c) after 255 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/or4v0x05.ap b/pdks/symbolic/vsclib/cells/or4v0x05.ap new file mode 100755 index 000000000..fc52e0516 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or4v0x05.ap @@ -0,0 +1,110 @@ +V ALLIANCE : 6 +H or4v0x05,P, 5/ 7/2024,100 +A 0,0,6400,7200 +R 6000,1600,ref_ref,b_16 +R 5200,4000,ref_ref,a_40 +R 5200,2400,ref_ref,b_24 +R 4400,4800,ref_ref,a_48 +R 4400,3200,ref_ref,c_32 +R 400,4800,ref_ref,z_48 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 400,1600,ref_ref,z_16 +R 3600,5600,ref_ref,d_56 +R 3600,4800,ref_ref,d_48 +R 3600,3200,ref_ref,c_32 +R 3600,2400,ref_ref,c_24 +R 2800,4000,ref_ref,d_40 +R 1200,1600,ref_ref,z_16 +S 2000,4200,2000,6300,800,*,UP,TALU8 +S 1900,200,1900,1200,800,*,UP,TALU7 +S 5300,2900,5300,3400,200,*,UP,POLY +S 2200,4000,3600,4000,400,*,RIGHT,ALU1 +S 2200,3200,2200,4000,400,*,UP,ALU1 +S 4400,4000,5500,4000,400,*,RIGHT,ALU1 +S 5500,3200,5500,4000,400,*,UP,ALU1 +S 5500,5600,5500,6800,600,*,UP,ALU1 +S 1000,2100,1000,4500,200,*,UP,POLY +S 2000,2100,2000,3400,200,*,UP,POLY +S 4300,1800,4300,3900,200,*,UP,POLY +S 1500,500,1500,1900,400,*,UP,NDIF +S 500,1500,500,1900,400,*,UP,ALU1 +S 1000,1500,1000,2100,200,t10,UP,NTRANS +S 3600,500,3600,1900,600,*,UP,NDIF +S 3700,500,3700,1900,600,*,UP,NDIF +S 3000,1100,3000,1500,200,*,UP,POLY +S 3000,1500,3000,2100,200,t06,UP,NTRANS +S 2000,1500,2000,2100,200,t08,UP,NTRANS +S 3600,2500,3600,3900,200,*,UP,POLY +S 3000,2700,3600,2700,600,*,RIGHT,POLY +S 5000,3500,5700,3500,200,*,RIGHT,POLY +S 2000,3500,2900,3500,200,*,RIGHT,POLY +S 5600,4100,5600,6400,600,*,UP,PDIF +S 3900,4100,3900,6400,400,n2,UP,PDIF +S 5000,3900,5000,6600,200,t01,UP,PTRANS +S 4300,3900,4300,6600,200,t03,UP,PTRANS +S 4600,4100,4600,6400,400,n1,UP,PDIF +S 3600,3900,3600,6600,200,t05,UP,PTRANS +S 2900,3900,2900,6600,200,t07,UP,PTRANS +S 3200,4100,3200,6400,400,n3,UP,PDIF +S 6000,1600,6000,1600,400,b,LEFT,CALU1 +S 6000,1500,6000,2400,400,*,UP,ALU1 +S 5900,500,5900,1600,600,*,UP,NDIF +S 5300,800,5300,1200,200,*,UP,POLY +S 5300,1800,5300,3000,200,*,UP,POLY +S 5300,1200,5300,1800,200,t02,UP,NTRANS +S 5200,4000,5200,4000,400,a,LEFT,CALU1 +S 5200,2400,5200,2400,400,b,LEFT,CALU1 +S 500,4700,500,4900,400,*,UP,ALU1 +S 4400,4800,4400,4800,400,a,LEFT,CALU1 +S 4400,4000,4400,4900,400,*,UP,ALU1 +S 4400,3200,4400,3200,400,c,LEFT,CALU1 +S 4400,2400,6000,2400,400,*,RIGHT,ALU1 +S 4300,800,4300,1200,200,*,UP,POLY +S 4300,1200,4300,1800,200,t04,UP,NTRANS +S 400,4800,500,4800,600,*,RIGHT,ALU1 +S 400,1600,400,4800,400,z,UP,CALU1 +S 400,1600,1400,1600,400,*,RIGHT,ALU1 +S 400,1500,400,4900,400,*,UP,ALU1 +S 400,1500,1400,1500,400,*,RIGHT,ALU1 +S 3600,4800,3600,5600,400,d,UP,CALU1 +S 3600,4000,3600,5700,400,*,UP,ALU1 +S 3600,2400,3600,3200,400,c,UP,CALU1 +S 3500,2300,3500,3200,600,*,UP,ALU1 +S 3400,3200,4500,3200,400,*,RIGHT,ALU1 +S 2800,4000,2800,4000,400,d,LEFT,CALU1 +S 2500,1500,4900,1500,400,*,RIGHT,ALU1 +S 2500,1500,2500,2400,400,*,UP,ALU1 +S 1600,5700,1600,6800,400,*,UP,ALU1 +S 1500,4700,1500,5900,400,*,UP,PDIF +S 1300,4800,2500,4800,400,*,RIGHT,ALU1 +S 1300,2400,2500,2400,400,*,RIGHT,ALU1 +S 1300,2400,1300,4800,400,*,UP,ALU1 +S 1200,3200,1200,3400,400,*,UP,ALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1000,4500,1000,5700,200,t09,UP,PTRANS +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,400,6400,400,800,*,RIGHT,ALU1 +V 5500,5600,CONT_DIF_P,* +V 5500,6300,CONT_DIF_P,* +V 500,1800,CONT_DIF_N,* +V 1600,600,CONT_DIF_N,* +V 2500,1800,CONT_DIF_N,zn +V 3400,2700,CONT_POLY,* +V 2200,3300,CONT_POLY,* +V 5500,3300,CONT_POLY,* +V 600,6600,CONT_BODY_N,* +V 600,600,CONT_BODY_P,* +V 5900,600,CONT_DIF_N,* +V 500,4800,CONT_DIF_P,* +V 4800,1500,CONT_DIF_N,zn +V 4500,2400,CONT_POLY,* +V 3600,600,CONT_DIF_N,* +V 2400,4800,CONT_DIF_P,zn +V 1600,5800,CONT_DIF_P,* +V 1200,3300,CONT_POLY,zn +EOF diff --git a/pdks/symbolic/vsclib/cells/or4v0x05.vbe b/pdks/symbolic/vsclib/cells/or4v0x05.vbe new file mode 100755 index 000000000..f5d3f7b0a --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or4v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY or4v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_c : NATURAL := 4; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_d : NATURAL := 5; + CONSTANT rdown_b_z : NATURAL := 4290; + CONSTANT rdown_c_z : NATURAL := 4290; + CONSTANT rdown_a_z : NATURAL := 4290; + CONSTANT rdown_d_z : NATURAL := 4280; + CONSTANT rup_b_z : NATURAL := 5030; + CONSTANT rup_c_z : NATURAL := 4980; + CONSTANT rup_a_z : NATURAL := 5100; + CONSTANT rup_d_z : NATURAL := 4960; + CONSTANT tphh_d_z : NATURAL := 86; + CONSTANT tphh_c_z : NATURAL := 101; + CONSTANT tphh_b_z : NATURAL := 111; + CONSTANT tpll_a_z : NATURAL := 184; + CONSTANT tphh_a_z : NATURAL := 116; + CONSTANT tpll_b_z : NATURAL := 175; + CONSTANT tpll_d_z : NATURAL := 123; + CONSTANT tpll_c_z : NATURAL := 155; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END or4v0x05; + +ARCHITECTURE behaviour_data_flow OF or4v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on or4v0x05" + SEVERITY WARNING; + z <= (((b or c) or a) or d) after 248 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/or4v4x05.ap b/pdks/symbolic/vsclib/cells/or4v4x05.ap new file mode 100755 index 000000000..62055f4c8 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or4v4x05.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H or4v4x05,P, 5/ 7/2024,100 +A 0,0,6400,7200 +R 1200,2400,ref_ref,z_24 +R 2000,4000,ref_ref,d_40 +R 2800,4000,ref_ref,d_40 +R 3600,3200,ref_ref,c_32 +R 3600,4800,ref_ref,d_48 +R 3600,5600,ref_ref,d_56 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,2400,ref_ref,b_24 +R 4400,4000,ref_ref,c_40 +R 4400,5600,ref_ref,a_56 +R 5200,2400,ref_ref,b_24 +R 5200,4000,ref_ref,a_40 +R 5200,4800,ref_ref,a_48 +R 5200,5600,ref_ref,a_56 +R 6000,1600,ref_ref,b_16 +S 2100,4200,2100,6100,400,*,UP,TALU8 +S 3000,1300,3000,2000,400,*,UP,TALU7 +S 1600,4600,1600,6500,600,*,UP,PDIF +S 600,600,1300,600,600,*,RIGHT,PTIE +S 1500,1600,1500,2400,600,*,UP,NDIF +S 1500,900,1500,1600,400,*,UP,ALU1 +S 3600,3500,3600,4600,200,*,UP,POLY +S 3200,3400,3600,3400,200,*,LEFT,POLY +S 5000,1800,5000,4200,200,*,UP,POLY +S 2000,2600,2000,4000,200,*,UP,POLY +S 4000,2100,4000,2400,200,*,UP,POLY +S 3000,2900,3000,3200,200,*,UP,POLY +S 1000,2900,1000,3600,200,*,UP,POLY +S 3500,700,3500,2400,600,*,UP,NDIF +S 0,400,6400,400,800,*,RIGHT,ALU1 +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 1000,1600,1000,2000,200,*,UP,POLY +S 1000,2000,1000,2600,200,t10,UP,NTRANS +S 1000,3900,1000,5100,200,t09,UP,PTRANS +S 1000,5100,1000,5500,200,*,UP,POLY +S 1200,2400,1200,2400,400,z,LEFT,CALU1 +S 1200,3200,1200,4900,400,*,UP,ALU1 +S 1200,3200,2300,3200,400,*,RIGHT,ALU1 +S 1200,4900,2500,4900,400,*,RIGHT,ALU1 +S 1600,5800,1600,6800,400,*,UP,ALU1 +S 1900,4000,3600,4000,400,*,RIGHT,ALU1 +S 2000,1600,2000,2000,200,*,UP,POLY +S 2000,2000,2000,2600,200,t08,UP,NTRANS +S 2000,4000,2000,4000,400,d,LEFT,CALU1 +S 2200,4200,2900,4200,200,*,RIGHT,POLY +S 2300,2300,2300,3200,400,*,UP,ALU1 +S 2300,2300,2700,2300,400,*,RIGHT,ALU1 +S 2700,1500,2700,2300,400,*,UP,ALU1 +S 2700,1500,4600,1500,400,*,RIGHT,ALU1 +S 2800,4000,2800,4000,400,d,LEFT,CALU1 +S 2900,4600,2900,5800,200,t07,UP,PTRANS +S 2900,5800,2900,6200,200,*,UP,POLY +S 3000,1600,3000,2000,200,*,UP,POLY +S 3000,2000,3000,2600,200,t06,UP,NTRANS +S 3100,3200,4400,3200,400,*,RIGHT,ALU1 +S 3200,4800,3200,5600,400,n3,UP,PDIF +S 3400,500,3400,1100,600,*,UP,NDIF +S 3600,3200,3600,3200,400,c,LEFT,CALU1 +S 3600,4000,3600,5700,400,*,UP,ALU1 +S 3600,4600,3600,5800,200,t05,UP,PTRANS +S 3600,4800,3600,5600,400,d,UP,CALU1 +S 3600,5800,3600,6200,200,*,UP,POLY +S 3900,4800,3900,5600,400,n2,UP,PDIF +S 4000,1200,4000,1800,200,t04,UP,NTRANS +S 4000,800,4000,1200,200,*,UP,POLY +S 400,2300,1400,2300,400,*,RIGHT,ALU1 +S 400,2300,400,4900,400,*,UP,ALU1 +S 400,2400,1400,2400,400,*,RIGHT,ALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 400,4800,500,4800,600,*,RIGHT,ALU1 +S 4100,2400,6000,2400,400,*,RIGHT,ALU1 +S 4300,2400,4300,4600,200,*,UP,POLY +S 4300,4600,4300,5800,200,t03,UP,PTRANS +S 4300,5800,4300,6200,200,*,UP,POLY +S 4400,2400,4400,2400,400,b,LEFT,CALU1 +S 4400,3200,4400,4100,400,*,UP,ALU1 +S 4400,4000,4400,4000,400,c,LEFT,CALU1 +S 4400,5600,4400,5600,400,a,LEFT,CALU1 +S 4400,5600,5200,5600,600,*,RIGHT,ALU1 +S 4600,4800,4600,5600,400,n1,UP,PDIF +S 5000,1200,5000,1800,200,t02,UP,NTRANS +S 5000,4600,5000,5800,200,t01,UP,PTRANS +S 5000,5800,5000,6200,200,*,UP,POLY +S 5000,800,5000,1200,200,*,UP,POLY +S 500,4700,500,4900,400,*,UP,ALU1 +S 5200,2400,5200,2400,400,b,LEFT,CALU1 +S 5200,3900,5200,5700,400,*,UP,ALU1 +S 5200,4000,5200,5600,400,a,UP,CALU1 +S 5600,4800,5600,6700,600,*,UP,PDIF +S 5600,500,5600,1600,600,*,UP,NDIF +S 6000,1500,6000,2400,400,*,UP,ALU1 +S 6000,1600,6000,1600,400,b,LEFT,CALU1 +S 600,6000,600,6700,600,*,UP,NTIE +V 1500,1600,CONT_DIF_N,* +V 3500,600,CONT_DIF_N,* +V 1200,3300,CONT_POLY,zn +V 1600,5900,CONT_DIF_P,* +V 2200,4000,CONT_POLY,* +V 2400,4900,CONT_DIF_P,zn +V 2500,2300,CONT_DIF_N,zn +V 3200,3200,CONT_POLY,* +V 4200,2400,CONT_POLY,* +V 4500,1500,CONT_DIF_N,zn +V 500,2300,CONT_DIF_N,* +V 500,4800,CONT_DIF_P,* +V 5200,4000,CONT_POLY,* +V 5600,600,CONT_DIF_N,* +V 5600,6600,CONT_DIF_P,* +V 600,600,CONT_BODY_P,* +V 600,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/or4v4x05.vbe b/pdks/symbolic/vsclib/cells/or4v4x05.vbe new file mode 100755 index 000000000..fb4ad9d77 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/or4v4x05.vbe @@ -0,0 +1,44 @@ +ENTITY or4v4x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_b : NATURAL := 3; + CONSTANT cin_c : NATURAL := 3; + CONSTANT cin_a : NATURAL := 3; + CONSTANT cin_d : NATURAL := 3; + CONSTANT rdown_b_z : NATURAL := 4650; + CONSTANT rdown_c_z : NATURAL := 4650; + CONSTANT rdown_a_z : NATURAL := 4650; + CONSTANT rdown_d_z : NATURAL := 4650; + CONSTANT rup_b_z : NATURAL := 4990; + CONSTANT rup_c_z : NATURAL := 4970; + CONSTANT rup_a_z : NATURAL := 5030; + CONSTANT rup_d_z : NATURAL := 4960; + CONSTANT tphh_d_z : NATURAL := 75; + CONSTANT tphh_c_z : NATURAL := 82; + CONSTANT tphh_b_z : NATURAL := 86; + CONSTANT tpll_a_z : NATURAL := 246; + CONSTANT tphh_a_z : NATURAL := 87; + CONSTANT tpll_b_z : NATURAL := 237; + CONSTANT tpll_d_z : NATURAL := 184; + CONSTANT tpll_c_z : NATURAL := 216; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + b : in BIT; + c : in BIT; + a : in BIT; + d : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END or4v4x05; + +ARCHITECTURE behaviour_data_flow OF or4v4x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on or4v4x05" + SEVERITY WARNING; + z <= (((b or c) or a) or d) after 272 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/rowend_x0.ap b/pdks/symbolic/vsclib/cells/rowend_x0.ap new file mode 100755 index 000000000..4e84187fc --- /dev/null +++ b/pdks/symbolic/vsclib/cells/rowend_x0.ap @@ -0,0 +1,9 @@ +V ALLIANCE : 6 +H rowend_x0,P,11/ 5/2006,1000 +A 0,0,8000,72000 +S 0,4000,8000,4000,8000,*,RIGHT,ALU1 +S 0,4000,8000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,8000,54000,44000,*,RIGHT,NWELL +S 0,68000,8000,68000,8000,*,RIGHT,ALU1 +S 0,68000,8000,68000,8000,vdd,RIGHT,CALU1 +EOF diff --git a/pdks/symbolic/vsclib/cells/rowend_x0.vbe b/pdks/symbolic/vsclib/cells/rowend_x0.vbe new file mode 100755 index 000000000..cfbb6456b --- /dev/null +++ b/pdks/symbolic/vsclib/cells/rowend_x0.vbe @@ -0,0 +1,18 @@ +ENTITY rowend_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 576; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END rowend_x0; + +ARCHITECTURE behaviour_data_flow OF rowend_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rowend_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/vsclib/cells/tie_x0.ap b/pdks/symbolic/vsclib/cells/tie_x0.ap new file mode 100755 index 000000000..7c1b97d5e --- /dev/null +++ b/pdks/symbolic/vsclib/cells/tie_x0.ap @@ -0,0 +1,13 @@ +V ALLIANCE : 6 +H tie_x0,P,16/ 5/2006,1000 +A 0,0,16000,72000 +S 0,4000,16000,4000,8000,*,RIGHT,ALU1 +S 0,4000,16000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,16000,54000,44000,*,RIGHT,NWELL +S 0,68000,16000,68000,8000,*,RIGHT,ALU1 +S 0,68000,16000,68000,8000,vdd,RIGHT,CALU1 +S 8000,42000,8000,67000,10000,*,UP,NTIE +S 8000,5000,8000,22000,10000,*,UP,PTIE +V 8000,6000,CONT_BODY_P,* +V 8000,66000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/tie_x0.vbe b/pdks/symbolic/vsclib/cells/tie_x0.vbe new file mode 100755 index 000000000..ae641fa23 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/tie_x0.vbe @@ -0,0 +1,18 @@ +ENTITY tie_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 1152; + CONSTANT transistors : NATURAL := 0 +); +PORT ( + vdd : in BIT; + vss : in BIT +); +END tie_x0; + +ARCHITECTURE behaviour_data_flow OF tie_x0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on tie_x0" + SEVERITY WARNING; +END; diff --git a/pdks/symbolic/vsclib/cells/vddtie.ap b/pdks/symbolic/vsclib/cells/vddtie.ap new file mode 100755 index 000000000..bb1befa68 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/vddtie.ap @@ -0,0 +1,48 @@ +V ALLIANCE : 6 +H vddtie,P,29/ 5/2006,1000 +A 0,0,24000,72000 +R 12000,40000,ref_ref,z_40 +R 20000,16000,ref_ref,z_16 +R 20000,24000,ref_ref,z_24 +R 20000,32000,ref_ref,z_32 +R 20000,40000,ref_ref,z_40 +R 20000,48000,ref_ref,z_48 +R 20000,56000,ref_ref,z_56 +R 4000,40000,ref_ref,z_40 +S 0,4000,24000,4000,8000,*,RIGHT,ALU1 +S 0,4000,24000,4000,8000,vss,RIGHT,CALU1 +S 0,54000,24000,54000,44000,*,RIGHT,NWELL +S 0,68000,24000,68000,8000,*,RIGHT,ALU1 +S 0,68000,24000,68000,8000,vdd,RIGHT,CALU1 +S 12000,40000,12000,40000,4000,z,RIGHT,CALU1 +S 13000,15000,13000,25000,2000,t*,UP,NTRANS +S 13000,25000,13000,38000,2000,*,UP,POLY +S 13000,38000,13000,57000,2000,t*,UP,PTRANS +S 19000,15000,19000,57000,4000,*,UP,ALU1 +S 19000,17000,19000,23000,6000,*,UP,NDIF +S 19000,40000,19000,55000,6000,*,UP,PDIF +S 20000,15000,20000,57000,4000,*,UP,ALU1 +S 20000,16000,20000,56000,4000,z,UP,CALU1 +S 4000,40000,18000,40000,6000,*,RIGHT,ALU1 +S 4000,40000,20000,40000,6000,*,RIGHT,ALU1 +S 4000,40000,4000,40000,4000,z,RIGHT,CALU1 +S 6000,40000,6000,66000,6000,*,UP,PDIF +S 6000,5000,6000,23000,6000,*,UP,NDIF +S 7000,31000,13000,31000,6000,*,RIGHT,POLY +S 7000,40000,7000,66000,6000,*,UP,PDIF +S 7000,4000,7000,31000,6000,*,UP,ALU1 +S 7000,49000,7000,68000,4000,*,UP,ALU1 +S 7000,5000,7000,23000,6000,*,UP,NDIF +V 18000,6000,CONT_BODY_P,* +V 18000,66000,CONT_BODY_N,* +V 19000,22000,CONT_DIF_N,* +V 19000,41000,CONT_DIF_P,* +V 19000,48000,CONT_DIF_P,* +V 7000,14000,CONT_DIF_N,* +V 7000,22000,CONT_DIF_N,* +V 7000,31000,CONT_POLY,* +V 7000,50000,CONT_DIF_P,* +V 7000,57000,CONT_DIF_P,* +V 7000,6000,CONT_DIF_N,* +V 7000,64000,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/vddtie.vbe b/pdks/symbolic/vsclib/cells/vddtie.vbe new file mode 100755 index 000000000..4733db142 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/vddtie.vbe @@ -0,0 +1,20 @@ +ENTITY vddtie IS +GENERIC ( + CONSTANT area : NATURAL := 1728; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END vddtie; + +ARCHITECTURE behaviour_data_flow OF vddtie IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vddtie" + SEVERITY WARNING; + z <= '1'; +END; diff --git a/pdks/symbolic/vsclib/cells/vsstie.ap b/pdks/symbolic/vsclib/cells/vsstie.ap new file mode 100755 index 000000000..c52299f36 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/vsstie.ap @@ -0,0 +1,47 @@ +V ALLIANCE : 6 +H vsstie,P,30/ 5/2006,1000 +A 0,0,24000,72000 +R 4000,24000,ref_ref,z_24 +R 4000,16000,ref_ref,z_16 +R 20000,56000,ref_ref,z_56 +R 20000,48000,ref_ref,z_48 +R 20000,40000,ref_ref,z_40 +R 20000,32000,ref_ref,z_32 +R 20000,24000,ref_ref,z_24 +R 12000,24000,ref_ref,z_24 +S 20000,24000,20000,56000,4000,z,UP,CALU1 +S 7000,41000,7000,67000,6000,*,UP,PDIF +S 7000,33000,7000,68000,6000,*,UP,ALU1 +S 7000,33000,13000,33000,6000,*,RIGHT,POLY +S 6000,8000,6000,24000,6000,*,UP,NDIF +S 6000,41000,6000,67000,6000,*,UP,PDIF +S 5000,15000,5000,25000,6000,*,UP,ALU1 +S 4000,24000,20000,24000,6000,*,RIGHT,ALU1 +S 4000,16000,4000,24000,4000,z,UP,CALU1 +S 20000,23000,20000,57000,4000,*,UP,ALU1 +S 19000,8000,19000,24000,6000,*,UP,NDIF +S 19000,41000,19000,55000,6000,*,UP,PDIF +S 19000,4000,19000,16000,6000,*,UP,ALU1 +S 19000,23000,19000,57000,4000,*,UP,ALU1 +S 13000,6000,13000,26000,2000,t*,UP,NTRANS +S 13000,39000,13000,57000,2000,t*,UP,PTRANS +S 13000,26000,13000,39000,2000,*,UP,POLY +S 12000,24000,12000,24000,4000,z,LEFT,CALU1 +S 0,68000,24000,68000,8000,vdd,RIGHT,CALU1 +S 0,68000,24000,68000,8000,*,RIGHT,ALU1 +S 0,54000,24000,54000,44000,*,RIGHT,NWELL +S 0,4000,24000,4000,8000,vss,RIGHT,CALU1 +S 0,4000,24000,4000,8000,*,RIGHT,ALU1 +V 7000,66000,CONT_DIF_P,* +V 7000,58000,CONT_DIF_P,* +V 7000,50000,CONT_DIF_P,* +V 7000,42000,CONT_DIF_P,* +V 7000,33000,CONT_POLY,* +V 6000,23000,CONT_DIF_N,* +V 6000,16000,CONT_DIF_N,* +V 19000,9000,CONT_DIF_N,* +V 19000,50000,CONT_DIF_P,* +V 19000,42000,CONT_DIF_P,* +V 19000,16000,CONT_DIF_N,* +V 18000,66000,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/vsstie.vbe b/pdks/symbolic/vsclib/cells/vsstie.vbe new file mode 100755 index 000000000..727683e36 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/vsstie.vbe @@ -0,0 +1,20 @@ +ENTITY vsstie IS +GENERIC ( + CONSTANT area : NATURAL := 1728; + CONSTANT transistors : NATURAL := 2 +); +PORT ( + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END vsstie; + +ARCHITECTURE behaviour_data_flow OF vsstie IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on vsstie" + SEVERITY WARNING; + z <= '0'; +END; diff --git a/pdks/symbolic/vsclib/cells/xaon21v0x05.ap b/pdks/symbolic/vsclib/cells/xaon21v0x05.ap new file mode 100755 index 000000000..fd9259d9d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xaon21v0x05.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 6 +H xaon21v0x05,P, 5/ 7/2024,100 +A 0,0,8000,7200 +R 1200,1600,ref_ref,z_16 +R 1200,4800,ref_ref,z_48 +R 2000,1600,ref_ref,z_16 +R 2800,1600,ref_ref,z_16 +R 3600,3200,ref_ref,a2_32 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 400,4800,ref_ref,z_48 +R 4400,1600,ref_ref,a2_16 +R 4400,2400,ref_ref,a2_24 +R 4400,3200,ref_ref,a2_32 +R 5200,1600,ref_ref,a1_16 +R 5200,2400,ref_ref,a1_24 +R 5200,3200,ref_ref,a1_32 +R 6000,2400,ref_ref,a1_24 +R 6800,4800,ref_ref,b_48 +R 6800,5600,ref_ref,b_56 +R 7600,5600,ref_ref,b_56 +S 3900,4200,3900,6200,800,*,UP,TALU8 +S 5600,1000,5600,2600,800,*,UP,TALU7 +S 1000,3200,1000,4500,200,*,UP,POLY +S 1400,2300,1400,3200,200,*,UP,POLY +S 0,400,8000,400,800,*,RIGHT,ALU1 +S 0,400,8000,400,800,vss,RIGHT,CALU1 +S 0,5400,8000,5400,4400,*,RIGHT,NWELL +S 0,6800,8000,6800,800,*,RIGHT,ALU1 +S 0,6800,8000,6800,800,vdd,RIGHT,CALU1 +S 1000,4500,1000,6100,200,t08,UP,PTRANS +S 1000,6100,1000,6500,200,*,UP,POLY +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2400,1200,4000,400,*,UP,ALU1 +S 1200,2400,3600,2400,400,*,RIGHT,ALU1 +S 1200,4000,2200,4000,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1400,1300,1400,2300,200,t09,UP,NTRANS +S 1400,900,1400,1300,200,*,UP,POLY +S 1700,1500,1700,2100,400,n1,UP,NDIF +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,3300,2000,4500,200,*,UP,POLY +S 2000,4500,2000,6100,200,t10,UP,PTRANS +S 2000,6100,2000,6500,200,*,UP,POLY +S 2100,1300,2100,2300,200,t11,UP,NTRANS +S 2100,2300,2100,3000,200,*,UP,POLY +S 2100,3200,2900,3200,400,*,RIGHT,ALU1 +S 2100,900,2100,1300,200,*,UP,POLY +S 2200,4000,2200,4800,400,*,UP,ALU1 +S 2200,4800,4400,4800,400,*,RIGHT,ALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2900,3200,2900,4100,400,*,UP,ALU1 +S 2900,4100,6900,4100,400,*,RIGHT,ALU1 +S 3000,3400,3000,4500,200,*,UP,POLY +S 3000,3400,4000,3400,200,*,RIGHT,POLY +S 3000,4500,3000,6600,200,t03,UP,PTRANS +S 3100,1300,3100,2300,200,t06,UP,NTRANS +S 3100,2300,3100,2700,200,*,UP,POLY +S 3100,400,3100,1300,200,*,UP,POLY +S 3100,400,6400,400,200,*,RIGHT,POLY +S 3500,5700,3500,6400,600,*,UP,PDIF +S 3500,6300,3500,6800,600,*,UP,ALU1 +S 3600,1900,3600,2400,400,*,UP,ALU1 +S 3600,3200,3600,3200,400,a2,LEFT,CALU1 +S 3600,3200,4400,3200,600,*,RIGHT,ALU1 +S 400,1600,2900,1600,400,*,RIGHT,ALU1 +S 400,1600,400,4900,400,*,UP,ALU1 +S 400,2400,400,4800,400,z,UP,CALU1 +S 400,4800,1500,4800,600,*,RIGHT,ALU1 +S 400,5600,5200,5600,400,*,RIGHT,ALU1 +S 4100,1300,4100,2300,200,t04,UP,NTRANS +S 4100,2300,4100,3100,200,*,UP,POLY +S 4400,1500,4400,3300,400,*,UP,ALU1 +S 4400,1600,4400,3200,400,a2,UP,CALU1 +S 4500,1500,4500,2100,400,n2,UP,NDIF +S 4800,1300,4800,2300,200,t02,UP,NTRANS +S 4800,2300,4800,3100,200,*,UP,POLY +S 4800,3200,5100,3200,600,*,RIGHT,POLY +S 4800,3800,4800,5900,200,t01,UP,PTRANS +S 4800,5900,4800,6300,200,*,UP,POLY +S 5200,1500,5200,3300,400,*,UP,ALU1 +S 5200,1600,5200,3200,400,a1,UP,CALU1 +S 5200,2400,6100,2400,400,*,RIGHT,ALU1 +S 5200,4100,5200,5600,400,*,UP,ALU1 +S 5400,4000,5400,6700,600,*,UP,PDIF +S 5600,1500,5600,2100,1000,*,UP,NDIF +S 5900,400,5900,1700,400,*,UP,ALU1 +S 6000,2400,6000,2400,400,a1,LEFT,CALU1 +S 6000,3400,7300,3400,200,*,RIGHT,POLY +S 6000,3800,6000,5800,200,t05,UP,PTRANS +S 6000,5800,6000,6200,200,*,UP,POLY +S 6400,1300,6400,2300,200,t07,UP,NTRANS +S 6400,2300,6400,3400,200,*,UP,POLY +S 6400,400,6400,1300,200,*,UP,POLY +S 6700,5600,7600,5600,600,*,RIGHT,ALU1 +S 6800,4800,6800,5600,400,b,UP,CALU1 +S 6800,4800,6800,5700,600,*,UP,ALU1 +S 6900,1900,6900,4100,400,*,UP,ALU1 +S 6900,6600,7500,6600,600,*,RIGHT,NTIE +S 700,500,700,2100,600,*,UP,NDIF +S 7300,3400,7300,5600,200,*,UP,POLY +S 7600,5600,7600,5600,400,b,LEFT,CALU1 +S 800,500,800,2100,600,*,UP,NDIF +V 1200,3200,CONT_POLY,an +V 1500,4800,CONT_DIF_P,* +V 2200,3200,CONT_POLY,bn +V 2500,4800,CONT_DIF_P,an +V 2600,1600,CONT_DIF_N,* +V 3500,6300,CONT_DIF_P,* +V 3600,2000,CONT_DIF_N,an +V 3900,3200,CONT_POLY,* +V 4300,4800,CONT_DIF_P,an +V 500,5600,CONT_DIF_P,bn +V 5200,3200,CONT_POLY,* +V 5400,6600,CONT_DIF_P,* +V 5900,1600,CONT_DIF_N,* +V 6500,4100,CONT_DIF_P,bn +V 6900,2000,CONT_DIF_N,bn +V 7100,5700,CONT_POLY,* +V 7200,6600,CONT_BODY_N,* +V 7400,600,CONT_BODY_P,* +V 800,600,CONT_DIF_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/xaon21v0x05.vbe b/pdks/symbolic/vsclib/cells/xaon21v0x05.vbe new file mode 100755 index 000000000..b097d2cdc --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xaon21v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY xaon21v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5760; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a1 : NATURAL := 5; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT rdown_b_z : NATURAL := 3720; + CONSTANT rdown_a1_z : NATURAL := 4090; + CONSTANT rdown_a2_z : NATURAL := 4080; + CONSTANT rup_b_z : NATURAL := 4060; + CONSTANT rup_a1_z : NATURAL := 5250; + CONSTANT rup_a2_z : NATURAL := 5240; + CONSTANT tplh_a1_z : NATURAL := 74; + CONSTANT tplh_a2_z : NATURAL := 70; + CONSTANT tphl_b_z : NATURAL := 29; + CONSTANT tplh_b_z : NATURAL := 92; + CONSTANT tphh_b_z : NATURAL := 61; + CONSTANT tphl_a1_z : NATURAL := 79; + CONSTANT tphl_a2_z : NATURAL := 81; + CONSTANT tpll_a1_z : NATURAL := 97; + CONSTANT tpll_a2_z : NATURAL := 93; + CONSTANT tpll_b_z : NATURAL := 88; + CONSTANT tphh_a1_z : NATURAL := 120; + CONSTANT tphh_a2_z : NATURAL := 122; + CONSTANT transistors : NATURAL := 11 +); +PORT ( + b : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xaon21v0x05; + +ARCHITECTURE behaviour_data_flow OF xaon21v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xaon21v0x05" + SEVERITY WARNING; + z <= (b xor (a1 and a2)) after 194 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/xnr2v8x05.ap b/pdks/symbolic/vsclib/cells/xnr2v8x05.ap new file mode 100755 index 000000000..9add30740 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xnr2v8x05.ap @@ -0,0 +1,117 @@ +V ALLIANCE : 6 +H xnr2v8x05,P, 5/ 7/2024,100 +A 0,0,7200,7200 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 1200,4000,ref_ref,z_40 +R 1200,5600,ref_ref,a_56 +R 2000,5600,ref_ref,a_56 +R 2000,4800,ref_ref,a_48 +R 6000,2400,ref_ref,b_24 +R 5200,1600,ref_ref,b_16 +S 5300,5000,5300,6800,800,*,UP,TALU8 +S 5700,4000,5700,6400,600,*,DOWN,PDIF +S 5500,800,5500,2300,400,*,UP,NDIF +S 5200,3300,5200,3500,200,*,UP,POLY +S 3200,5200,3200,5600,200,*,UP,POLY +S 2200,5300,2200,5600,200,*,UP,POLY +S 5100,2800,5100,3200,200,*,UP,POLY +S 1000,2700,1000,3300,200,*,DOWN,POLY +S 5700,800,5700,2300,400,*,UP,NDIF +S 5100,1900,5100,2500,200,t08,UP,NTRANS +S 1500,500,1500,2300,600,*,UP,NDIF +S 0,400,7200,400,800,*,RIGHT,ALU1 +S 0,400,7200,400,800,vss,RIGHT,CALU1 +S 0,5400,7200,5400,4400,*,RIGHT,NWELL +S 0,6800,7200,6800,800,*,RIGHT,ALU1 +S 0,6800,7200,6800,800,vdd,RIGHT,CALU1 +S 6200,4700,6200,5900,200,t03,UP,PTRANS +S 5200,1600,5200,1600,400,b,LEFT,CALU1 +S 5200,3800,5200,5000,200,t07,UP,PTRANS +S 4200,3800,4200,5000,200,t05,UP,PTRANS +S 5200,5000,5200,5400,200,*,UP,POLY +S 5600,6300,5600,6800,600,*,UP,ALU1 +S 3600,2900,3600,3400,200,*,UP,POLY +S 3500,1500,3500,4200,400,*,UP,ALU1 +S 3200,3800,3200,5000,200,t09,UP,PTRANS +S 3200,3400,3600,3400,200,*,LEFT,POLY +S 3600,2900,4000,2900,200,*,LEFT,POLY +S 4200,6900,6200,6900,200,*,RIGHT,POLY +S 4200,5000,4200,6900,200,*,UP,POLY +S 6200,5900,6200,6900,200,*,UP,POLY +S 3000,300,6200,300,200,*,RIGHT,POLY +S 3300,5600,6800,5600,400,*,RIGHT,ALU1 +S 1000,1500,1000,1900,200,*,DOWN,POLY +S 6800,1500,6800,5600,400,*,UP,ALU1 +S 6700,1600,6800,1600,600,*,LEFT,ALU1 +S 2700,4900,5400,4900,400,*,LEFT,ALU1 +S 400,2200,500,2200,600,*,LEFT,ALU1 +S 2000,1500,2000,1900,200,*,UP,POLY +S 2000,1900,2000,2500,200,t02,UP,NTRANS +S 3000,1900,3000,2500,200,t06,UP,NTRANS +S 4000,1900,4000,2500,200,t10,UP,NTRANS +S 6200,1300,6200,1900,200,t04,UP,NTRANS +S 4400,4100,4700,4100,600,*,LEFT,ALU1 +S 3500,4100,3700,4100,600,*,LEFT,ALU1 +S 2400,2200,2700,2200,400,*,LEFT,ALU1 +S 2700,2200,2700,4900,400,*,UP,ALU1 +S 4400,2300,4400,4200,400,*,UP,ALU1 +S 4400,2300,4700,2300,400,*,RIGHT,ALU1 +S 3000,300,3000,1900,200,*,UP,POLY +S 4000,1500,4000,1900,200,*,DOWN,POLY +S 5100,1600,5100,2000,200,*,DOWN,POLY +S 6200,300,6200,1300,200,*,UP,POLY +S 6200,1900,6200,4700,200,*,UP,POLY +S 1200,5600,1200,5600,400,a,LEFT,CALU1 +S 2000,4800,2000,5600,400,a,UP,CALU1 +S 400,4000,1200,4000,600,*,RIGHT,ALU1 +S 400,2100,400,4100,400,*,UP,ALU1 +S 1000,5000,1000,5400,200,*,UP,POLY +S 1000,3300,1000,3800,200,*,DOWN,POLY +S 2000,4700,2000,5600,400,*,UP,ALU1 +S 1200,4000,1200,4000,400,z,LEFT,CALU1 +S 400,2400,400,4000,400,z,DOWN,CALU1 +S 6000,2400,6000,2400,400,b,LEFT,CALU1 +S 5600,400,5600,900,600,*,DOWN,ALU1 +S 2200,2900,2200,3800,200,*,DOWN,POLY +S 2200,3800,2200,5000,200,t01,UP,PTRANS +S 2000,2900,2200,2900,200,*,LEFT,POLY +S 2000,3000,2200,3000,200,*,LEFT,POLY +S 1600,4000,1600,6700,600,*,DOWN,PDIF +S 1100,5600,2500,5600,400,*,LEFT,ALU1 +S 5600,5900,5600,6400,600,*,DOWN,PDIF +S 5900,2400,6100,2400,400,*,LEFT,ALU1 +S 5900,1600,5900,2400,400,*,DOWN,ALU1 +S 5100,1600,5900,1600,400,*,RIGHT,ALU1 +S 6100,2400,6100,3300,400,*,UP,ALU1 +S 5400,3100,5400,4900,400,*,UP,ALU1 +S 5100,3200,5400,3200,600,*,LEFT,ALU1 +S 1400,1500,3500,1500,400,*,LEFT,ALU1 +S 1400,1500,1400,3100,400,*,UP,ALU1 +S 1100,3100,1400,3100,400,*,LEFT,ALU1 +S 1000,3800,1000,5000,200,t11,UP,PTRANS +S 1000,1900,1000,2500,200,t12,UP,NTRANS +V 5700,6300,CONT_DIF_P,* +V 5600,900,CONT_DIF_N,* +V 4700,4100,CONT_DIF_P,ai +V 6100,3200,CONT_POLY,* +V 2400,600,CONT_BODY_P,* +V 1400,600,CONT_DIF_N,* +V 1600,6600,CONT_DIF_P,* +V 3700,4100,CONT_DIF_P,zn +V 3400,5600,CONT_POLY,bn +V 6700,1600,CONT_DIF_N,bn +V 2700,4700,CONT_DIF_P,an +V 2500,2200,CONT_DIF_N,an +V 3500,2200,CONT_DIF_N,zn +V 5100,3200,CONT_POLY,an +V 4600,2300,CONT_DIF_N,ai +V 1200,3100,CONT_POLY,zn +V 500,2200,CONT_DIF_N,* +V 500,4100,CONT_DIF_P,* +V 2400,5600,CONT_POLY,* +V 600,6600,CONT_BODY_N,* +V 3100,6600,CONT_BODY_N,* +V 6700,5600,CONT_DIF_P,bn +EOF diff --git a/pdks/symbolic/vsclib/cells/xnr2v8x05.vbe b/pdks/symbolic/vsclib/cells/xnr2v8x05.vbe new file mode 100755 index 000000000..13f4565b8 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xnr2v8x05.vbe @@ -0,0 +1,36 @@ +ENTITY xnr2v8x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5184; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_b_z : NATURAL := 4070; + CONSTANT rdown_a_z : NATURAL := 4110; + CONSTANT rup_b_z : NATURAL := 5010; + CONSTANT rup_a_z : NATURAL := 5020; + CONSTANT tphl_a_z : NATURAL := 162; + CONSTANT tphl_b_z : NATURAL := 118; + CONSTANT tplh_b_z : NATURAL := 120; + CONSTANT tplh_a_z : NATURAL := 165; + CONSTANT tphh_b_z : NATURAL := 83; + CONSTANT tpll_b_z : NATURAL := 108; + CONSTANT tphh_a_z : NATURAL := 122; + CONSTANT tpll_a_z : NATURAL := 146; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xnr2v8x05; + +ARCHITECTURE behaviour_data_flow OF xnr2v8x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xnr2v8x05" + SEVERITY WARNING; + z <= not ((b xor a)) after 242 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/xnr3v1x05.ap b/pdks/symbolic/vsclib/cells/xnr3v1x05.ap new file mode 100755 index 000000000..61deb197d --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xnr3v1x05.ap @@ -0,0 +1,183 @@ +V ALLIANCE : 6 +H xnr3v1x05,P, 5/ 7/2024,100 +A 0,0,12800,7200 +R 8400,4800,ref_ref,c_48 +R 7600,4000,ref_ref,c_40 +R 7600,3200,ref_ref,c_32 +R 2800,3200,ref_ref,b_32 +R 2800,2400,ref_ref,b_24 +R 2000,4000,ref_ref,a_40 +R 2000,2400,ref_ref,b_24 +R 12400,4800,ref_ref,z_48 +R 12400,4000,ref_ref,z_40 +R 12400,3200,ref_ref,z_32 +R 12400,2400,ref_ref,z_24 +R 1200,3200,ref_ref,a_32 +R 1200,2400,ref_ref,a_24 +R 11600,4800,ref_ref,z_48 +R 11600,1600,ref_ref,z_16 +R 10800,1600,ref_ref,z_16 +S 1700,5700,1700,7000,800,*,UP,TALU8 +S 2900,4300,2900,6000,800,*,UP,TALU8 +S 6700,1400,6700,2400,800,*,UP,TALU7 +S 11800,3300,11800,4500,200,*,UP,POLY +S 7400,4100,8600,4100,200,*,RIGHT,POLY +S 7800,2300,7800,2700,200,*,UP,POLY +S 6600,3500,9800,3500,200,*,RIGHT,POLY +S 5800,2600,5800,4000,200,*,UP,POLY +S 4800,3200,4800,4600,200,*,UP,POLY +S 1400,2100,1400,3300,200,*,UP,POLY +S 2000,3400,2900,3400,200,*,RIGHT,POLY +S 1000,3200,1000,3500,200,*,DOWN,POLY +S 5200,1900,5200,2400,400,*,UP,NDIF +S 4000,1900,4000,2400,400,*,UP,NDIF +S 4900,4800,6600,4800,400,*,RIGHT,ALU1 +S 4200,5600,4900,5600,400,*,RIGHT,ALU1 +S 4900,4800,4900,5600,400,*,UP,ALU1 +S 6600,3000,6600,4800,400,*,UP,ALU1 +S 3800,3400,3800,4600,200,*,UP,POLY +S 3400,3400,3800,3400,200,*,LEFT,POLY +S 3000,3200,3400,3200,600,*,RIGHT,POLY +S 3800,6500,3800,6900,200,*,UP,POLY +S 4800,6500,4800,6900,200,*,UP,POLY +S 5500,6500,5500,6900,200,*,UP,POLY +S 6000,5500,6000,6800,600,*,UP,ALU1 +S 6100,4800,6100,6300,600,*,UP,PDIF +S 3800,4600,3800,6500,200,t03,UP,PTRANS +S 5500,4600,5500,6500,200,t11,UP,PTRANS +S 4800,4600,4800,6500,200,t09,UP,PTRANS +S 5200,4800,5200,6300,400,n1,UP,PDIF +S 3900,4000,5700,4000,400,*,RIGHT,ALU1 +S 4600,1700,4600,2600,200,t10,UP,NTRANS +S 4600,1300,4600,1700,200,*,UP,POLY +S 2400,500,2400,2400,1400,*,UP,NDIF +S 3400,1300,3400,1700,200,*,UP,POLY +S 3400,1700,3400,2600,200,t05,UP,NTRANS +S 4600,1500,4600,3300,400,*,DOWN,ALU1 +S 3900,2200,3900,4700,400,*,UP,ALU1 +S 2400,4700,3900,4700,400,*,RIGHT,ALU1 +S 5300,2200,5300,3000,400,*,UP,ALU1 +S 5300,3000,6600,3000,400,*,RIGHT,ALU1 +S 9800,6100,9800,6500,200,*,UP,POLY +S 9800,4500,9800,6100,200,t15,UP,PTRANS +S 9800,3500,9800,4500,200,*,UP,POLY +S 9500,2400,11600,2400,400,*,RIGHT,ALU1 +S 9500,1500,9500,2400,400,*,UP,ALU1 +S 9400,3200,9400,5700,400,*,UP,ALU1 +S 9200,4700,9200,6700,600,*,UP,PDIF +S 9000,1900,9000,3500,200,*,UP,POLY +S 9000,1200,9000,1900,200,t16,UP,NTRANS +S 8600,6100,8600,6500,200,*,UP,POLY +S 8600,4500,8600,6100,200,t06,UP,PTRANS +S 8600,3200,10700,3200,400,*,RIGHT,ALU1 +S 8600,1800,8600,3200,400,*,UP,ALU1 +S 8400,900,8400,1900,600,*,UP,NDIF +S 8400,4800,8400,4800,400,c,LEFT,CALU1 +S 8400,400,8400,1000,600,*,UP,ALU1 +S 8100,5600,8100,5900,600,*,UP,PDIF +S 8000,5700,12400,5700,400,*,RIGHT,ALU1 +S 7800,300,7800,1400,200,*,UP,POLY +S 7800,300,10000,300,200,*,RIGHT,POLY +S 7800,1400,7800,2100,200,t07,UP,NTRANS +S 7600,4800,8500,4800,400,*,RIGHT,ALU1 +S 7600,3200,7600,4000,400,c,UP,CALU1 +S 7600,2600,7600,4800,400,*,UP,ALU1 +S 7500,4300,7600,4300,600,*,RIGHT,ALU1 +S 7300,1600,7300,1900,600,*,UP,NDIF +S 7200,1800,8600,1800,400,*,RIGHT,ALU1 +S 7100,5100,7100,6700,600,*,UP,NTIE +S 6300,1500,6300,2100,400,*,UP,ALU1 +S 5800,1700,5800,2600,200,t12,UP,NTRANS +S 5800,1300,5800,1700,200,*,UP,POLY +S 5400,600,6200,600,600,*,RIGHT,PTIE +S 500,4600,500,5700,400,*,UP,ALU1 +S 500,4600,500,5500,600,*,UP,PDIF +S 400,5700,3400,5700,400,*,RIGHT,ALU1 +S 400,1500,6300,1500,400,*,RIGHT,ALU1 +S 400,1500,400,5700,400,*,UP,ALU1 +S 2800,2400,2800,3200,400,b,UP,CALU1 +S 2800,2300,2800,3200,600,*,UP,ALU1 +S 2000,4000,2000,4000,400,a,LEFT,CALU1 +S 2000,3800,2000,5700,200,t04,UP,PTRANS +S 2000,2400,2900,2400,600,*,RIGHT,ALU1 +S 2000,2400,2000,2400,400,b,LEFT,CALU1 +S 1500,4000,1500,6700,400,*,UP,PDIF +S 1400,800,1400,1200,200,*,UP,POLY +S 1400,1200,1400,2100,200,t02,UP,NTRANS +S 12400,2400,12400,4800,400,z,UP,CALU1 +S 12400,1600,12400,4900,400,*,UP,ALU1 +S 12300,5600,12300,5900,600,*,UP,PDIF +S 12300,500,12300,1700,600,*,UP,NDIF +S 1200,4000,2100,4000,400,*,RIGHT,ALU1 +S 1200,2400,1200,3200,400,a,UP,CALU1 +S 1200,2300,1200,4000,400,*,UP,ALU1 +S 11800,6100,11800,6500,200,*,UP,POLY +S 11800,4500,11800,6100,200,t17,UP,PTRANS +S 11700,800,11700,1200,200,*,UP,POLY +S 11700,1900,11700,3200,200,*,UP,POLY +S 11700,1200,11700,1900,200,t18,UP,NTRANS +S 11600,4800,11600,4800,400,z,LEFT,CALU1 +S 11600,2400,11600,4000,400,*,UP,ALU1 +S 11600,1600,11600,1600,400,z,LEFT,CALU1 +S 11400,1400,11400,1700,400,n2,UP,NDIF +S 11200,4900,12400,4900,400,*,RIGHT,ALU1 +S 11200,4800,12400,4800,400,*,RIGHT,ALU1 +S 11000,800,11000,1200,200,*,UP,POLY +S 11000,1200,11000,1900,200,t14,UP,NTRANS +S 10800,6100,10800,6500,200,*,UP,POLY +S 10800,4500,10800,6100,200,t13,UP,PTRANS +S 10800,2400,11000,2400,200,*,RIGHT,POLY +S 10800,2300,11000,2300,200,*,RIGHT,POLY +S 10800,2300,10800,4500,200,*,UP,POLY +S 10800,1600,10800,1600,400,z,LEFT,CALU1 +S 10400,1600,12400,1600,400,*,RIGHT,ALU1 +S 10400,1400,10400,1700,600,*,UP,NDIF +S 10300,4000,11600,4000,400,*,RIGHT,ALU1 +S 10300,4000,10300,4900,400,*,UP,ALU1 +S 1000,3800,1000,5700,200,t01,UP,PTRANS +S 10000,300,10000,1200,200,*,UP,POLY +S 10000,1900,10000,2300,200,*,UP,POLY +S 10000,1200,10000,1900,200,t08,UP,NTRANS +S 0,6800,12800,6800,800,vdd,RIGHT,CALU1 +S 0,6800,12800,6800,800,*,RIGHT,ALU1 +S 0,5400,12800,5400,4400,*,RIGHT,NWELL +S 0,400,12800,400,800,vss,RIGHT,CALU1 +S 0,400,12800,400,800,*,RIGHT,ALU1 +V 6000,6200,CONT_DIF_P,* +V 6000,5500,CONT_DIF_P,* +V 5600,4000,CONT_POLY,bn +V 2800,600,CONT_DIF_N,* +V 4600,3200,CONT_POLY,an +V 3900,2300,CONT_DIF_N,bn +V 9500,1600,CONT_DIF_N,zn +V 9200,6600,CONT_DIF_P,* +V 900,1500,CONT_DIF_N,an +V 8400,1000,CONT_DIF_N,* +V 8100,5700,CONT_DIF_P,cn +V 7600,2700,CONT_POLY,* +V 7500,4300,CONT_POLY,* +V 7300,1800,CONT_DIF_N,cn +V 7100,6600,CONT_BODY_N,* +V 6600,3300,CONT_POLY,iz +V 6300,2000,CONT_DIF_N,an +V 6200,600,CONT_BODY_P,* +V 600,6600,CONT_BODY_N,* +V 5400,600,CONT_BODY_P,* +V 5300,2300,CONT_DIF_N,iz +V 500,5400,CONT_DIF_P,an +V 500,4700,CONT_DIF_P,an +V 4300,5600,CONT_DIF_P,iz +V 3300,5700,CONT_DIF_P,an +V 2800,3200,CONT_POLY,* +V 2500,4700,CONT_DIF_P,bn +V 2000,600,CONT_DIF_N,* +V 1600,6600,CONT_DIF_P,* +V 12300,600,CONT_DIF_N,* +V 12300,5700,CONT_DIF_P,bn +V 1200,3200,CONT_POLY,* +V 11600,3300,CONT_POLY,zn +V 11300,4900,CONT_DIF_P,* +V 10600,3200,CONT_POLY,cn +V 10500,1600,CONT_DIF_N,* +V 10300,4800,CONT_DIF_P,zn +EOF diff --git a/pdks/symbolic/vsclib/cells/xnr3v1x05.vbe b/pdks/symbolic/vsclib/cells/xnr3v1x05.vbe new file mode 100755 index 000000000..c25e02e59 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xnr3v1x05.vbe @@ -0,0 +1,44 @@ +ENTITY xnr3v1x05 IS +GENERIC ( + CONSTANT area : NATURAL := 9216; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_c : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 4780; + CONSTANT rdown_b_z : NATURAL := 4770; + CONSTANT rdown_c_z : NATURAL := 4510; + CONSTANT rup_a_z : NATURAL := 6190; + CONSTANT rup_b_z : NATURAL := 6190; + CONSTANT rup_c_z : NATURAL := 5980; + CONSTANT tphl_a_z : NATURAL := 169; + CONSTANT tphh_a_z : NATURAL := 171; + CONSTANT tphl_b_z : NATURAL := 174; + CONSTANT tphh_b_z : NATURAL := 176; + CONSTANT tphl_c_z : NATURAL := 37; + CONSTANT tphh_c_z : NATURAL := 68; + CONSTANT tplh_c_z : NATURAL := 91; + CONSTANT tpll_c_z : NATURAL := 98; + CONSTANT tplh_b_z : NATURAL := 145; + CONSTANT tpll_b_z : NATURAL := 143; + CONSTANT tplh_a_z : NATURAL := 180; + CONSTANT tpll_a_z : NATURAL := 179; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xnr3v1x05; + +ARCHITECTURE behaviour_data_flow OF xnr3v1x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xnr3v1x05" + SEVERITY WARNING; + z <= not ((a xor b) xor c) after 271 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/xoon21v0x05.ap b/pdks/symbolic/vsclib/cells/xoon21v0x05.ap new file mode 100755 index 000000000..f22ebb11c --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xoon21v0x05.ap @@ -0,0 +1,127 @@ +V ALLIANCE : 6 +H xoon21v0x05,P, 5/ 7/2024,100 +A 0,0,8000,7200 +R 1200,1600,ref_ref,z_16 +R 1200,4800,ref_ref,z_48 +R 2000,1600,ref_ref,z_16 +R 400,2400,ref_ref,z_24 +R 400,3200,ref_ref,z_32 +R 400,4000,ref_ref,z_40 +R 4400,3200,ref_ref,a2_32 +R 4400,4000,ref_ref,a2_40 +R 4400,4800,ref_ref,a2_48 +R 5200,3200,ref_ref,a2_32 +R 5200,4800,ref_ref,a1_48 +R 6000,2400,ref_ref,b_24 +R 6000,4000,ref_ref,a1_40 +R 6000,4800,ref_ref,a1_48 +R 6800,2400,ref_ref,b_24 +R 6800,3200,ref_ref,b_32 +R 6800,4000,ref_ref,b_40 +S 4900,1500,4900,2600,800,*,UP,TALU7 +S 1000,3600,1000,4100,200,*,DOWN,POLY +S 7000,2000,7000,3600,200,*,UP,POLY +S 0,400,8000,400,800,*,RIGHT,ALU1 +S 0,400,8000,400,800,vss,RIGHT,CALU1 +S 0,5400,8000,5400,4400,*,RIGHT,NWELL +S 0,6800,8000,6800,800,*,RIGHT,ALU1 +S 0,6800,8000,6800,800,vdd,RIGHT,CALU1 +S 1000,4300,1000,5900,200,t08,UP,PTRANS +S 1000,5900,1000,6300,200,*,UP,POLY +S 1100,1200,1100,1900,200,t09,UP,NTRANS +S 1100,1900,1100,3800,200,*,UP,POLY +S 1100,800,1100,1200,200,*,UP,POLY +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 1200,2400,1200,4000,400,*,UP,ALU1 +S 1200,2400,3300,2400,400,*,RIGHT,ALU1 +S 1200,4000,2500,4000,400,*,RIGHT,ALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1500,1400,1500,1700,400,n2,UP,NDIF +S 1800,1200,1800,1900,200,t11,UP,NTRANS +S 1800,2300,2000,2300,200,*,RIGHT,POLY +S 1800,2400,2000,2400,200,*,RIGHT,POLY +S 1800,800,1800,1200,200,*,UP,POLY +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 2000,2300,2000,4300,200,*,UP,POLY +S 2000,4300,2000,6600,200,t10,UP,PTRANS +S 2100,3200,3300,3200,400,*,RIGHT,ALU1 +S 2500,4000,2500,4700,400,*,UP,ALU1 +S 2800,1200,2800,1900,200,t06,UP,NTRANS +S 2800,1900,2800,2300,200,*,UP,POLY +S 2800,300,2800,1200,200,*,UP,POLY +S 2800,300,7000,300,200,*,RIGHT,POLY +S 3000,3300,3000,4300,200,*,UP,POLY +S 3000,3300,3800,3300,200,*,RIGHT,POLY +S 3000,4300,3000,6600,200,t03,UP,PTRANS +S 3300,1500,3300,2400,400,*,UP,ALU1 +S 3300,2300,5300,2300,400,*,RIGHT,ALU1 +S 3300,3200,3300,5600,400,*,UP,ALU1 +S 3400,4500,3400,6400,400,n1,UP,PDIF +S 3700,3900,5500,3900,200,*,RIGHT,POLY +S 3700,4300,3700,6600,200,t01,UP,PTRANS +S 3800,1200,3800,1900,200,t04,UP,NTRANS +S 3800,1900,3800,3300,200,*,UP,POLY +S 3800,3100,4400,3100,600,*,RIGHT,POLY +S 400,1600,2400,1600,400,*,RIGHT,ALU1 +S 400,1600,400,4800,400,*,UP,ALU1 +S 400,2400,400,4000,400,z,UP,CALU1 +S 400,4800,1600,4800,400,*,RIGHT,ALU1 +S 400,5600,7500,5600,400,*,RIGHT,ALU1 +S 4200,6300,4200,6800,600,*,UP,ALU1 +S 4300,1500,4300,1700,600,*,UP,NDIF +S 4300,400,4300,1500,600,*,UP,ALU1 +S 4400,3100,4400,4900,400,*,UP,ALU1 +S 4400,3200,4400,4800,400,a2,UP,CALU1 +S 4400,3200,5200,3200,600,*,RIGHT,ALU1 +S 4400,4500,4400,6400,600,*,UP,PDIF +S 500,500,500,1700,600,*,UP,NDIF +S 5200,3200,5200,3200,400,a2,LEFT,CALU1 +S 5200,4800,5200,4800,400,a1,LEFT,CALU1 +S 5200,4800,6000,4800,600,*,RIGHT,ALU1 +S 5300,2000,5300,2300,400,*,UP,ALU1 +S 5300,2000,5300,2300,600,*,UP,NDIF +S 5300,400,5300,1000,400,*,UP,ALU1 +S 5400,5500,5400,6700,600,*,UP,NTIE +S 5500,3900,5500,4600,600,*,UP,POLY +S 5700,2900,5700,3900,200,*,UP,POLY +S 5800,1800,5800,2500,200,t02,UP,NTRANS +S 5800,2500,5800,3000,200,*,UP,POLY +S 6000,2400,6000,2400,400,b,LEFT,CALU1 +S 6000,2400,6800,2400,600,*,RIGHT,ALU1 +S 6000,3900,6000,4900,400,*,UP,ALU1 +S 6000,4000,6000,4800,400,a1,UP,CALU1 +S 6400,1500,6400,2300,600,*,UP,NDIF +S 6400,4000,6400,6700,600,*,UP,PDIF +S 6400,400,6400,1600,600,*,UP,ALU1 +S 6800,2300,6800,4100,400,*,UP,ALU1 +S 6800,2400,6800,4000,400,b,UP,CALU1 +S 7000,1300,7000,2000,200,t07,UP,NTRANS +S 7000,300,7000,1300,200,*,UP,POLY +S 7000,3800,7000,5400,200,t05,UP,PTRANS +S 7000,5400,7000,5800,200,*,UP,POLY +S 7500,1500,7500,1800,600,*,UP,NDIF +S 7500,1600,7500,5600,400,*,UP,ALU1 +S 7500,4100,7500,4800,600,*,UP,PDIF +V 1200,3700,CONT_POLY,an +V 1500,4800,CONT_DIF_P,* +V 2200,3200,CONT_POLY,bn +V 2300,1600,CONT_DIF_N,* +V 2500,4600,CONT_DIF_P,an +V 3300,1600,CONT_DIF_N,an +V 4200,6300,CONT_DIF_P,* +V 4300,1500,CONT_DIF_N,* +V 4500,3100,CONT_POLY,* +V 500,5600,CONT_DIF_P,bn +V 500,600,CONT_DIF_N,* +V 5300,2100,CONT_DIF_N,an +V 5300,900,CONT_BODY_P,* +V 5400,6600,CONT_BODY_N,* +V 5500,4700,CONT_POLY,* +V 6400,1600,CONT_DIF_N,* +V 6400,6600,CONT_DIF_P,* +V 6800,3200,CONT_POLY,* +V 7400,6600,CONT_BODY_N,* +V 7500,1700,CONT_DIF_N,bn +V 7500,4100,CONT_DIF_P,bn +V 7500,4800,CONT_DIF_P,bn +EOF diff --git a/pdks/symbolic/vsclib/cells/xoon21v0x05.vbe b/pdks/symbolic/vsclib/cells/xoon21v0x05.vbe new file mode 100755 index 000000000..5f2cd75a1 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xoon21v0x05.vbe @@ -0,0 +1,44 @@ +ENTITY xoon21v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5760; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a1 : NATURAL := 4; + CONSTANT cin_a2 : NATURAL := 5; + CONSTANT rdown_b_z : NATURAL := 3840; + CONSTANT rdown_a1_z : NATURAL := 4720; + CONSTANT rdown_a2_z : NATURAL := 4690; + CONSTANT rup_b_z : NATURAL := 6870; + CONSTANT rup_a1_z : NATURAL := 6660; + CONSTANT rup_a2_z : NATURAL := 6660; + CONSTANT tplh_a1_z : NATURAL := 98; + CONSTANT tplh_a2_z : NATURAL := 90; + CONSTANT tphl_b_z : NATURAL := 39; + CONSTANT tplh_b_z : NATURAL := 96; + CONSTANT tphh_b_z : NATURAL := 72; + CONSTANT tphl_a1_z : NATURAL := 83; + CONSTANT tphl_a2_z : NATURAL := 74; + CONSTANT tpll_a1_z : NATURAL := 127; + CONSTANT tpll_a2_z : NATURAL := 119; + CONSTANT tpll_b_z : NATURAL := 108; + CONSTANT tphh_a1_z : NATURAL := 118; + CONSTANT tphh_a2_z : NATURAL := 108; + CONSTANT transistors : NATURAL := 11 +); +PORT ( + b : in BIT; + a1 : in BIT; + a2 : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xoon21v0x05; + +ARCHITECTURE behaviour_data_flow OF xoon21v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xoon21v0x05" + SEVERITY WARNING; + z <= (b xor (a1 or a2)) after 234 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/xor2v0x05.ap b/pdks/symbolic/vsclib/cells/xor2v0x05.ap new file mode 100755 index 000000000..6981e6432 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xor2v0x05.ap @@ -0,0 +1,108 @@ +V ALLIANCE : 6 +H xor2v0x05,P,24/ 6/2024,100 +A 0,0,6400,7200 +R 5200,4000,ref_ref,z_40 +R 5200,2400,ref_ref,z_24 +R 6000,3200,ref_ref,z_32 +R 1200,5600,ref_ref,b_56 +R 2000,2400,ref_ref,a_24 +R 2000,3200,ref_ref,a_32 +R 400,4800,ref_ref,b_48 +R 400,5600,ref_ref,b_56 +R 4400,1600,ref_ref,z_16 +R 2800,3200,ref_ref,a_32 +S 4400,5300,4400,5800,200,*,UP,POLY +S 5400,2000,5400,3500,200,*,UP,POLY +S 2800,3400,3400,3400,200,*,LEFT,POLY +S 1100,5800,1100,6300,200,*,UP,POLY +S 1100,6300,2000,6300,200,*,RIGHT,POLY +S 5400,5900,5400,6300,200,*,UP,POLY +S 5900,4800,5900,5700,400,*,UP,ALU1 +S 5900,4900,5900,5600,600,*,UP,PDIF +S 2500,5600,2500,6800,600,*,UP,ALU1 +S 2700,4000,2700,5700,800,*,UP,PDIF +S 2000,3800,2000,5900,200,t03,UP,PTRANS +S 5400,3800,5400,5900,200,t06,UP,PTRANS +S 5900,400,5900,1500,400,*,DOWN,ALU1 +S 4700,2000,4700,2400,200,*,UP,POLY +S 5400,700,5400,1100,200,*,DOWN,POLY +S 4700,700,4700,1100,200,*,DOWN,POLY +S 3700,2000,3700,2400,200,*,UP,POLY +S 5900,1300,5900,1800,600,*,UP,NDIF +S 4700,1100,4700,2000,200,t09,UP,NTRANS +S 5400,1100,5400,2000,200,t07,UP,NTRANS +S 5100,1300,5100,1800,400,n1,UP,NDIF +S 3700,1300,3700,2000,200,t04,UP,NTRANS +S 2700,1300,2700,2000,200,t02,UP,NTRANS +S 2700,2000,2700,3000,200,*,DOWN,POLY +S 900,2100,900,2400,600,*,UP,NDIF +S 1400,1900,1400,2600,200,t05,UP,NTRANS +S 1400,400,1400,1900,200,*,UP,POLY +S 3000,6600,3800,6600,600,*,RIGHT,NTIE +S 1400,400,3700,400,200,*,RIGHT,POLY +S 1500,4800,3400,4800,400,*,LEFT,ALU1 +S 3400,4800,3400,5700,400,*,UP,ALU1 +S 6000,3200,6000,3200,400,z,LEFT,CALU1 +S 5200,4000,5200,4000,400,z,LEFT,CALU1 +S 2000,400,2000,1600,600,*,UP,ALU1 +S 900,4000,1500,4000,400,*,RIGHT,ALU1 +S 1400,3400,2000,3400,200,*,RIGHT,POLY +S 1400,2600,1400,3400,200,*,UP,POLY +S 900,2200,900,4000,400,*,UP,ALU1 +S 2100,1500,2100,2400,600,*,UP,NDIF +S 2000,1500,2000,2400,600,*,UP,NDIF +S 1500,4000,1500,4800,400,*,UP,ALU1 +S 3900,3200,3900,4100,600,*,DOWN,ALU1 +S 3800,3200,5300,3200,400,*,LEFT,ALU1 +S 3200,2400,3800,2400,400,*,RIGHT,ALU1 +S 3800,2400,3800,3200,400,*,DOWN,ALU1 +S 3200,1500,3200,2400,400,*,UP,ALU1 +S 4100,1600,5100,1600,400,*,RIGHT,ALU1 +S 3700,400,3700,1300,200,*,UP,POLY +S 5200,2400,5200,2400,400,z,LEFT,CALU1 +S 5100,1600,5100,2400,400,*,DOWN,ALU1 +S 5100,2400,6000,2400,400,*,LEFT,ALU1 +S 0,400,6400,400,800,*,RIGHT,ALU1 +S 0,400,6400,400,800,vss,RIGHT,CALU1 +S 0,5400,6400,5400,4400,*,RIGHT,NWELL +S 0,6800,6400,6800,800,*,RIGHT,ALU1 +S 0,6800,6400,6800,800,vdd,RIGHT,CALU1 +S 1200,5600,1200,5600,400,b,LEFT,CALU1 +S 2000,2400,2000,3200,400,a,UP,CALU1 +S 400,4700,400,5700,400,*,UP,ALU1 +S 400,4800,400,5600,400,b,UP,CALU1 +S 4400,1600,4400,1600,400,z,LEFT,CALU1 +S 2000,2400,2000,3200,600,*,UP,ALU1 +S 3400,3800,3400,5100,200,t01,UP,PTRANS +S 3400,5100,3400,5500,200,*,UP,POLY +S 2800,3200,2800,3200,400,a,LEFT,CALU1 +S 400,5600,1300,5600,400,*,RIGHT,ALU1 +S 400,5700,1300,5700,400,*,RIGHT,ALU1 +S 1900,3200,2900,3200,400,*,RIGHT,ALU1 +S 4900,4000,6000,4000,400,*,RIGHT,ALU1 +S 4900,4000,4900,4900,400,*,UP,ALU1 +S 6000,2400,6000,4000,400,*,UP,ALU1 +S 3400,5700,5900,5700,400,*,RIGHT,ALU1 +S 4400,3800,4400,5100,200,t08,UP,PTRANS +S 4400,2400,4700,2400,200,*,LEFT,POLY +S 4400,2400,4400,3800,200,*,DOWN,POLY +V 5900,4900,CONT_DIF_P,bn +V 5900,5600,CONT_DIF_P,bn +V 2500,5600,CONT_DIF_P,* +V 5900,1400,CONT_DIF_N,* +V 3800,6600,CONT_BODY_N,* +V 3000,6600,CONT_BODY_N,* +V 4900,4800,CONT_DIF_P,* +V 900,2300,CONT_DIF_N,bn +V 2000,1600,CONT_DIF_N,* +V 900,5700,CONT_POLY,* +V 1500,4100,CONT_DIF_P,bn +V 3200,1600,CONT_DIF_N,an +V 4200,1600,CONT_DIF_N,* +V 3900,4100,CONT_DIF_P,an +V 5200,3200,CONT_POLY,an +V 600,600,CONT_BODY_P,* +V 4200,5700,CONT_POLY,bn +V 2800,3200,CONT_POLY,* +V 4900,4100,CONT_DIF_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/xor2v0x05.vbe b/pdks/symbolic/vsclib/cells/xor2v0x05.vbe new file mode 100755 index 000000000..18b6d83fc --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xor2v0x05.vbe @@ -0,0 +1,36 @@ +ENTITY xor2v0x05 IS +GENERIC ( + CONSTANT area : NATURAL := 4608; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_b_z : NATURAL := 3890; + CONSTANT rdown_a_z : NATURAL := 4140; + CONSTANT rup_b_z : NATURAL := 5490; + CONSTANT rup_a_z : NATURAL := 5740; + CONSTANT tplh_a_z : NATURAL := 74; + CONSTANT tphl_b_z : NATURAL := 39; + CONSTANT tplh_b_z : NATURAL := 79; + CONSTANT tphh_b_z : NATURAL := 72; + CONSTANT tphl_a_z : NATURAL := 63; + CONSTANT tpll_a_z : NATURAL := 97; + CONSTANT tpll_b_z : NATURAL := 80; + CONSTANT tphh_a_z : NATURAL := 86; + CONSTANT transistors : NATURAL := 9 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xor2v0x05; + +ARCHITECTURE behaviour_data_flow OF xor2v0x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xor2v0x05" + SEVERITY WARNING; + z <= (b xor a) after 194 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/xor2v1x05.ap b/pdks/symbolic/vsclib/cells/xor2v1x05.ap new file mode 100755 index 000000000..fee701f1f --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xor2v1x05.ap @@ -0,0 +1,105 @@ +V ALLIANCE : 6 +H xor2v1x05,P, 5/ 7/2024,100 +A 0,0,7200,7200 +R 400,2400,ref_ref,a_24 +R 1200,3200,ref_ref,a_32 +R 2800,2400,ref_ref,z_24 +R 2800,3200,ref_ref,z_32 +R 3600,4800,ref_ref,z_48 +R 400,3200,ref_ref,a_32 +R 5200,4000,ref_ref,b_40 +R 6000,3200,ref_ref,b_32 +R 6000,4000,ref_ref,b_40 +R 3600,4000,ref_ref,z_40 +S 5300,1600,5300,2800,800,*,UP,TALU7 +S 400,800,2000,800,200,*,RIGHT,ALU1 +S 300,6400,1700,6400,200,*,RIGHT,ALU1 +S 4300,2900,5000,2900,200,*,RIGHT,POLY +S 2900,5000,2900,5700,200,*,UP,POLY +S 1200,3400,1900,3400,200,*,RIGHT,POLY +S 1800,2200,1900,2200,600,*,RIGHT,ALU1 +S 1900,4100,2500,4100,400,*,RIGHT,ALU1 +S 1900,1500,5000,1500,400,*,RIGHT,ALU1 +S 1900,1500,1900,4100,400,*,UP,ALU1 +S 3000,5700,4700,5700,400,*,RIGHT,ALU1 +S 700,1400,700,2300,600,*,UP,NDIF +S 700,400,700,1500,600,*,DOWN,ALU1 +S 400,2400,400,3200,400,a,UP,CALU1 +S 400,2300,400,3300,400,*,UP,ALU1 +S 0,400,7200,400,800,*,RIGHT,ALU1 +S 0,400,7200,400,800,vss,RIGHT,CALU1 +S 0,5400,7200,5400,4400,*,RIGHT,NWELL +S 0,6800,7200,6800,800,*,RIGHT,ALU1 +S 0,6800,7200,6800,800,vdd,RIGHT,CALU1 +S 1200,3200,1200,3200,400,a,LEFT,CALU1 +S 2800,2400,2800,3200,400,z,UP,CALU1 +S 400,3200,1200,3200,600,*,RIGHT,ALU1 +S 5200,4000,5200,4000,400,b,LEFT,CALU1 +S 5200,4000,6000,4000,600,*,RIGHT,ALU1 +S 6000,3100,6000,4100,400,*,UP,ALU1 +S 6000,3200,6000,4000,400,b,UP,CALU1 +S 4300,1900,4300,2500,200,t08,UP,NTRANS +S 5200,2100,5200,2300,1000,*,UP,NDIF +S 6200,1900,6200,2500,200,t04,UP,NTRANS +S 5700,400,5700,2300,400,*,UP,ALU1 +S 600,6600,1400,6600,600,*,LEFT,NTIE +S 3300,1900,3300,2500,200,t10,UP,NTRANS +S 2300,1900,2300,2500,200,t06,UP,NTRANS +S 1300,1900,1300,2500,200,t02,UP,NTRANS +S 6700,2200,6800,2200,600,*,LEFT,ALU1 +S 4900,3300,4900,3800,200,*,UP,POLY +S 1300,1500,1300,1900,200,*,UP,POLY +S 1300,2500,1300,3000,200,*,UP,POLY +S 2300,1000,6200,1000,200,*,RIGHT,POLY +S 2300,1000,2300,1900,200,*,UP,POLY +S 6200,1000,6200,1900,200,*,UP,POLY +S 2800,2200,2800,3200,600,*,UP,ALU1 +S 3900,3800,3900,5000,200,t05,UP,PTRANS +S 2900,3800,2900,5000,200,t09,UP,PTRANS +S 1900,3800,1900,5000,200,t01,UP,PTRANS +S 1900,5000,1900,5400,200,*,UP,POLY +S 4900,3800,4900,5000,200,t07,UP,PTRANS +S 4900,5000,4900,5400,200,*,UP,POLY +S 5000,1500,5000,3200,400,*,UP,ALU1 +S 4300,2200,4300,4200,400,*,UP,ALU1 +S 4300,4100,4400,4100,600,*,LEFT,ALU1 +S 3600,4000,3600,4800,400,z,UP,CALU1 +S 2700,3200,3400,3200,400,*,RIGHT,ALU1 +S 3400,3200,3400,4200,400,*,UP,ALU1 +S 3600,3900,3600,4900,400,*,UP,ALU1 +S 3700,2200,4300,2200,400,*,RIGHT,ALU1 +S 2900,2900,3300,2900,200,*,RIGHT,POLY +S 2900,2900,2900,3800,200,*,UP,POLY +S 1200,4600,1200,6800,400,*,UP,ALU1 +S 1200,4000,1200,4800,800,*,UP,PDIF +S 4700,5000,6800,5000,400,*,RIGHT,ALU1 +S 4700,5000,4700,5700,400,*,UP,ALU1 +S 5600,5800,5600,6800,600,*,UP,ALU1 +S 5500,4000,5500,5900,600,*,DOWN,PDIF +S 5600,4000,5600,5900,600,*,DOWN,PDIF +S 6200,4700,6200,5900,200,t03,UP,PTRANS +S 3900,6400,6200,6400,200,*,RIGHT,POLY +S 3900,5000,3900,6400,200,*,UP,POLY +S 6800,2100,6800,5000,400,*,UP,ALU1 +S 6200,5900,6200,6400,200,*,UP,POLY +S 6200,2500,6200,4700,200,*,UP,POLY +V 700,1500,CONT_DIF_N,* +V 1700,600,CONT_BODY_P,* +V 1200,3200,CONT_POLY,* +V 2400,4100,CONT_DIF_P,an +V 4400,4100,CONT_DIF_P,ai +V 6000,3200,CONT_POLY,* +V 600,6600,CONT_BODY_N,* +V 6700,2200,CONT_DIF_N,bn +V 5700,2200,CONT_DIF_N,* +V 1400,6600,CONT_BODY_N,* +V 2800,2200,CONT_DIF_N,* +V 3800,2200,CONT_DIF_N,ai +V 1800,2200,CONT_DIF_N,an +V 5000,3100,CONT_POLY,an +V 3400,4100,CONT_DIF_P,* +V 3100,5700,CONT_POLY,bn +V 1200,4700,CONT_DIF_P,* +V 5600,5800,CONT_DIF_P,* +V 6700,5000,CONT_DIF_P,bn +EOF diff --git a/pdks/symbolic/vsclib/cells/xor2v1x05.vbe b/pdks/symbolic/vsclib/cells/xor2v1x05.vbe new file mode 100755 index 000000000..442a13937 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xor2v1x05.vbe @@ -0,0 +1,36 @@ +ENTITY xor2v1x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5184; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_b_z : NATURAL := 4750; + CONSTANT rdown_a_z : NATURAL := 5090; + CONSTANT rup_b_z : NATURAL := 6230; + CONSTANT rup_a_z : NATURAL := 6570; + CONSTANT tplh_a_z : NATURAL := 84; + CONSTANT tphl_b_z : NATURAL := 39; + CONSTANT tplh_b_z : NATURAL := 53; + CONSTANT tphh_b_z : NATURAL := 57; + CONSTANT tphl_a_z : NATURAL := 71; + CONSTANT tpll_a_z : NATURAL := 114; + CONSTANT tpll_b_z : NATURAL := 70; + CONSTANT tphh_a_z : NATURAL := 102; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xor2v1x05; + +ARCHITECTURE behaviour_data_flow OF xor2v1x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xor2v1x05" + SEVERITY WARNING; + z <= (b xor a) after 215 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/xor2v2x05.ap b/pdks/symbolic/vsclib/cells/xor2v2x05.ap new file mode 100755 index 000000000..6df911d94 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xor2v2x05.ap @@ -0,0 +1,115 @@ +V ALLIANCE : 6 +H xor2v2x05,P, 5/ 7/2024,100 +A 0,0,7200,7200 +R 6800,3200,ref_ref,a_32 +R 6000,5600,ref_ref,b_56 +R 6000,4800,ref_ref,b_48 +R 6000,4000,ref_ref,a_40 +R 4400,1600,ref_ref,z_16 +R 400,4000,ref_ref,z_40 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 3600,1600,ref_ref,z_16 +R 2800,1600,ref_ref,z_16 +R 2000,1600,ref_ref,z_16 +R 1200,4800,ref_ref,z_48 +R 1200,1600,ref_ref,z_16 +R 5200,5600,ref_ref,b_56 +S 3100,1500,3100,2200,800,*,UP,TALU7 +S 5500,800,6900,800,200,*,RIGHT,ALU1 +S 2000,3000,2000,4300,200,*,UP,POLY +S 1000,3600,1000,4000,200,*,DOWN,POLY +S 5200,5600,5200,6900,200,*,DOWN,POLY +S 3600,4200,3600,6400,600,*,UP,PDIF +S 6000,3600,6000,4200,600,*,DOWN,POLY +S 4700,3200,4700,4400,400,*,DOWN,ALU1 +S 3500,3200,3500,5600,400,*,UP,ALU1 +S 4200,5600,4200,6000,200,*,UP,POLY +S 4200,4000,4200,5600,200,t01,UP,PTRANS +S 4000,2600,4000,3600,200,*,UP,POLY +S 4000,3600,6000,3600,200,*,LEFT,POLY +S 5900,4000,6800,4000,400,*,RIGHT,ALU1 +S 6000,2600,6000,3800,200,*,UP,POLY +S 2500,4000,2500,4700,400,*,UP,ALU1 +S 1300,2400,3600,2400,400,*,RIGHT,ALU1 +S 1300,2400,1300,4000,400,*,UP,ALU1 +S 3000,2000,3000,2600,200,t05,UP,NTRANS +S 3000,900,3000,2000,200,*,UP,POLY +S 6500,400,6500,2400,400,*,UP,ALU1 +S 6000,1600,6000,2000,200,*,UP,POLY +S 6000,2000,6000,2600,200,t02,UP,NTRANS +S 1800,1300,1800,2400,200,t08,UP,NTRANS +S 1500,1500,1500,2200,400,n1,UP,NDIF +S 1100,1300,1100,2400,200,t10,UP,NTRANS +S 5500,2200,5500,3200,400,*,UP,ALU1 +S 2100,3200,5500,3200,400,*,RIGHT,ALU1 +S 6800,3100,6800,4000,400,*,DOWN,ALU1 +S 6000,4000,6000,4000,400,a,LEFT,CALU1 +S 6800,3200,6800,3200,400,a,LEFT,CALU1 +S 6000,4800,6000,5600,600,*,UP,ALU1 +S 6000,4800,6000,5600,400,b,UP,CALU1 +S 400,1600,4500,1600,400,*,RIGHT,ALU1 +S 3600,1600,3600,1600,400,z,LEFT,CALU1 +S 2800,1600,2800,1600,400,z,LEFT,CALU1 +S 2000,1600,2000,1600,400,z,LEFT,CALU1 +S 1200,4800,1200,4800,400,z,LEFT,CALU1 +S 1200,1600,1200,1600,400,z,LEFT,CALU1 +S 0,6800,7200,6800,800,vdd,RIGHT,CALU1 +S 0,6800,7200,6800,800,*,RIGHT,ALU1 +S 0,5400,7200,5400,4400,*,RIGHT,NWELL +S 0,400,7200,400,800,vss,RIGHT,CALU1 +S 0,400,7200,400,800,*,RIGHT,ALU1 +S 4000,1800,4000,2600,200,t03,UP,NTRANS +S 5000,1800,5000,2600,200,t06,UP,NTRANS +S 3000,900,5000,900,200,*,RIGHT,POLY +S 1100,900,1100,1300,200,*,UP,POLY +S 1800,900,1800,1300,200,*,UP,POLY +S 5000,900,5000,1800,200,*,UP,POLY +S 400,2400,400,4000,400,z,UP,CALU1 +S 400,4800,1600,4800,400,*,RIGHT,ALU1 +S 400,1600,400,4800,400,*,UP,ALU1 +S 3500,2300,3500,2400,600,*,DOWN,ALU1 +S 4400,1600,4400,1600,400,z,LEFT,CALU1 +S 4500,1600,4500,2300,400,*,UP,ALU1 +S 5800,600,6600,600,600,*,LEFT,PTIE +S 1000,4300,1000,5900,200,t09,UP,PTRANS +S 2000,4300,2000,5900,200,t07,UP,PTRANS +S 3000,4300,3000,5900,200,t04,UP,PTRANS +S 2000,5900,2000,6300,200,*,UP,POLY +S 1000,5900,1000,6300,200,*,UP,POLY +S 3000,2600,3000,4300,200,*,UP,POLY +S 1100,2400,1100,3500,200,*,UP,POLY +S 5200,5600,5200,5600,400,b,LEFT,CALU1 +S 5100,5600,6100,5600,400,*,RIGHT,ALU1 +S 3000,5900,3000,6900,200,*,UP,POLY +S 3000,6900,5200,6900,200,*,RIGHT,POLY +S 4200,3800,4200,4300,200,*,DOWN,POLY +S 5800,6600,6600,6600,600,*,LEFT,NTIE +S 3600,6300,3600,6800,600,*,UP,ALU1 +S 2400,500,2400,2200,600,*,UP,NDIF +S 1300,4000,2500,4000,400,*,RIGHT,ALU1 +S 1200,3700,1300,3700,600,*,RIGHT,ALU1 +S 5000,2600,5000,3000,200,*,UP,POLY +S 400,5600,3500,5600,400,*,RIGHT,ALU1 +S 1800,2400,1800,2900,200,*,UP,POLY +S 1800,2900,2400,2900,200,*,RIGHT,POLY +V 4700,4300,CONT_DIF_P,an +V 6000,4000,CONT_POLY,* +V 2500,4600,CONT_DIF_P,bn +V 1500,4800,CONT_DIF_P,* +V 6500,2300,CONT_DIF_N,* +V 6600,600,CONT_BODY_P,* +V 600,1600,CONT_DIF_N,* +V 5500,2300,CONT_DIF_N,an +V 4500,2200,CONT_DIF_N,* +V 3500,2300,CONT_DIF_N,bn +V 2400,600,CONT_DIF_N,* +V 2200,3200,CONT_POLY,an +V 5800,600,CONT_BODY_P,* +V 500,5600,CONT_DIF_P,an +V 1200,3700,CONT_POLY,bn +V 5400,5600,CONT_POLY,* +V 3600,6300,CONT_DIF_P,* +V 6600,6600,CONT_BODY_N,* +V 5800,6600,CONT_BODY_N,* +EOF diff --git a/pdks/symbolic/vsclib/cells/xor2v2x05.vbe b/pdks/symbolic/vsclib/cells/xor2v2x05.vbe new file mode 100755 index 000000000..08004f8d2 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xor2v2x05.vbe @@ -0,0 +1,36 @@ +ENTITY xor2v2x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5184; + CONSTANT cin_b : NATURAL := 4; + CONSTANT cin_a : NATURAL := 4; + CONSTANT rdown_b_z : NATURAL := 2980; + CONSTANT rdown_a_z : NATURAL := 2990; + CONSTANT rup_b_z : NATURAL := 4690; + CONSTANT rup_a_z : NATURAL := 4650; + CONSTANT tplh_a_z : NATURAL := 82; + CONSTANT tphl_b_z : NATURAL := 43; + CONSTANT tplh_b_z : NATURAL := 74; + CONSTANT tphh_b_z : NATURAL := 78; + CONSTANT tphl_a_z : NATURAL := 49; + CONSTANT tpll_a_z : NATURAL := 96; + CONSTANT tpll_b_z : NATURAL := 91; + CONSTANT tphh_a_z : NATURAL := 84; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xor2v2x05; + +ARCHITECTURE behaviour_data_flow OF xor2v2x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xor2v2x05" + SEVERITY WARNING; + z <= (b xor a) after 170 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/xor2v8x05.ap b/pdks/symbolic/vsclib/cells/xor2v8x05.ap new file mode 100755 index 000000000..dc02061b1 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xor2v8x05.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H xor2v8x05,P, 5/ 7/2024,100 +A 0,0,7200,7200 +R 1200,4800,ref_ref,a_48 +R 400,3200,ref_ref,z_32 +R 400,2400,ref_ref,z_24 +R 1200,4000,ref_ref,z_40 +R 1200,5600,ref_ref,a_56 +R 2000,5600,ref_ref,a_56 +R 6000,2400,ref_ref,b_24 +R 5200,1600,ref_ref,b_16 +R 6000,3200,ref_ref,b_32 +S 5100,1400,5100,2300,800,*,UP,TALU7 +S 4000,5300,4000,5700,200,*,UP,POLY +S 2000,5300,2000,5800,200,*,UP,POLY +S 1000,2800,1000,3600,200,*,UP,POLY +S 1000,1600,1000,2000,200,*,DOWN,POLY +S 1000,2000,1000,2600,200,t12,UP,NTRANS +S 1000,5000,1000,5400,200,*,UP,POLY +S 1000,3800,1000,5000,200,t11,UP,PTRANS +S 1100,3200,1700,3200,400,*,LEFT,ALU1 +S 1700,1500,3600,1500,400,*,LEFT,ALU1 +S 1700,1500,1700,3200,400,*,UP,ALU1 +S 3000,5500,3300,5500,200,*,RIGHT,POLY +S 3300,6900,6200,6900,200,*,RIGHT,POLY +S 3300,5500,3300,6900,200,*,UP,POLY +S 1600,500,1600,2400,600,*,UP,NDIF +S 5600,4100,5600,6400,600,*,DOWN,PDIF +S 4200,300,4200,2000,200,*,UP,POLY +S 4200,300,6200,300,200,*,RIGHT,POLY +S 3200,1600,3200,2000,200,*,DOWN,POLY +S 5000,5100,5000,5500,200,*,UP,POLY +S 2200,2600,2200,3500,200,*,UP,POLY +S 2200,1600,2200,2000,200,*,UP,POLY +S 3600,2300,3700,2300,600,*,LEFT,ALU1 +S 3400,4200,3600,4200,400,*,LEFT,ALU1 +S 3600,1500,3600,4200,400,*,UP,ALU1 +S 400,2200,400,4000,400,*,UP,ALU1 +S 400,2300,500,2300,600,*,LEFT,ALU1 +S 4200,5600,4200,5700,600,*,UP,ALU1 +S 4100,5600,6800,5600,400,*,RIGHT,ALU1 +S 4400,4200,4600,4200,400,*,RIGHT,ALU1 +S 4400,2300,4800,2300,400,*,RIGHT,ALU1 +S 1200,4800,1200,5700,600,*,UP,ALU1 +S 1100,5700,2300,5700,400,*,LEFT,ALU1 +S 2200,2000,2200,2600,200,t02,UP,NTRANS +S 3200,2000,3200,2600,200,t06,UP,NTRANS +S 4200,2000,4200,2600,200,t10,UP,NTRANS +S 3600,3500,4000,3500,200,*,LEFT,POLY +S 3600,3000,3600,3500,200,*,UP,POLY +S 3200,3000,3600,3000,200,*,LEFT,POLY +S 2000,3400,2200,3400,200,*,LEFT,POLY +S 2000,3500,2200,3500,200,*,LEFT,POLY +S 2000,3900,2000,5100,200,t01,UP,PTRANS +S 5000,3900,5000,5100,200,t07,UP,PTRANS +S 4000,3900,4000,5100,200,t05,UP,PTRANS +S 3000,3900,3000,5100,200,t09,UP,PTRANS +S 400,2400,400,3200,400,z,DOWN,CALU1 +S 500,4000,500,4100,600,*,DOWN,ALU1 +S 400,4000,1300,4000,400,*,RIGHT,ALU1 +S 1100,5600,2300,5600,400,*,LEFT,ALU1 +S 2000,5600,2000,5600,400,a,LEFT,CALU1 +S 1200,4800,1200,5600,400,a,UP,CALU1 +S 1500,4000,1500,6700,400,*,DOWN,PDIF +S 5200,1600,5200,2000,200,*,DOWN,POLY +S 5200,2000,5200,2600,200,t08,UP,NTRANS +S 0,400,7200,400,800,*,RIGHT,ALU1 +S 0,400,7200,400,800,vss,RIGHT,CALU1 +S 0,5400,7200,5400,4400,*,RIGHT,NWELL +S 0,6800,7200,6800,800,*,RIGHT,ALU1 +S 0,6800,7200,6800,800,vdd,RIGHT,CALU1 +S 5200,1600,5200,1600,400,b,LEFT,CALU1 +S 5600,6300,5600,6800,600,*,UP,ALU1 +S 4400,2300,4400,4200,400,*,UP,ALU1 +S 1200,4000,1200,4000,400,z,LEFT,CALU1 +S 5600,400,5600,900,600,*,DOWN,ALU1 +S 5700,800,5700,2400,400,*,UP,NDIF +S 1600,6400,1600,6700,600,*,DOWN,PDIF +S 5600,800,5600,1100,600,*,UP,NDIF +S 5100,1600,6000,1600,400,*,RIGHT,ALU1 +S 6000,1600,6000,3300,400,*,DOWN,ALU1 +S 6000,3200,6100,3200,600,*,RIGHT,ALU1 +S 6000,2400,6000,3200,400,b,UP,CALU1 +S 6700,2300,6800,2300,600,*,LEFT,ALU1 +S 6200,2000,6200,2600,200,t04,UP,NTRANS +S 6800,2200,6800,5600,400,*,UP,ALU1 +S 6200,300,6200,2000,200,*,UP,POLY +S 6200,5100,6200,6300,200,t03,UP,PTRANS +S 6200,6300,6200,6900,200,*,UP,POLY +S 6200,3400,6200,5100,200,*,UP,POLY +S 5100,3300,5300,3300,600,*,LEFT,ALU1 +S 5300,3200,5300,4900,400,*,UP,ALU1 +S 5200,2600,5200,3100,200,*,UP,POLY +S 2700,4900,5300,4900,400,*,LEFT,ALU1 +S 2500,4200,2700,4200,600,*,RIGHT,ALU1 +S 2700,2200,2700,4900,400,*,UP,ALU1 +V 2600,6600,CONT_BODY_N,* +V 1600,6600,CONT_DIF_P,* +V 3500,600,CONT_BODY_P,* +V 1600,600,CONT_DIF_N,* +V 500,2300,CONT_DIF_N,* +V 1200,3200,CONT_POLY,zn +V 3700,2300,CONT_DIF_N,zn +V 2700,2300,CONT_DIF_N,an +V 4500,4200,CONT_DIF_P,ai +V 3500,4200,CONT_DIF_P,zn +V 2200,5700,CONT_POLY,* +V 4200,5700,CONT_POLY,bn +V 4700,2300,CONT_DIF_N,ai +V 5600,900,CONT_DIF_N,* +V 5600,6300,CONT_DIF_P,* +V 6100,3200,CONT_POLY,* +V 500,4100,CONT_DIF_P,* +V 6700,5600,CONT_DIF_P,bn +V 6700,2300,CONT_DIF_N,bn +V 5100,3300,CONT_POLY,an +V 2500,4200,CONT_DIF_P,an +V 600,6600,CONT_BODY_N,* +V 600,600,CONT_BODY_P,* +EOF diff --git a/pdks/symbolic/vsclib/cells/xor2v8x05.vbe b/pdks/symbolic/vsclib/cells/xor2v8x05.vbe new file mode 100755 index 000000000..3117c45f4 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xor2v8x05.vbe @@ -0,0 +1,36 @@ +ENTITY xor2v8x05 IS +GENERIC ( + CONSTANT area : NATURAL := 5184; + CONSTANT cin_b : NATURAL := 6; + CONSTANT cin_a : NATURAL := 3; + CONSTANT rdown_b_z : NATURAL := 4060; + CONSTANT rdown_a_z : NATURAL := 4100; + CONSTANT rup_b_z : NATURAL := 5010; + CONSTANT rup_a_z : NATURAL := 5010; + CONSTANT tplh_a_z : NATURAL := 161; + CONSTANT tphl_b_z : NATURAL := 116; + CONSTANT tplh_b_z : NATURAL := 117; + CONSTANT tphh_b_z : NATURAL := 85; + CONSTANT tphl_a_z : NATURAL := 161; + CONSTANT tpll_a_z : NATURAL := 144; + CONSTANT tpll_b_z : NATURAL := 104; + CONSTANT tphh_a_z : NATURAL := 122; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + b : in BIT; + a : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xor2v8x05; + +ARCHITECTURE behaviour_data_flow OF xor2v8x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xor2v8x05" + SEVERITY WARNING; + z <= (b xor a) after 240 ps; +END; diff --git a/pdks/symbolic/vsclib/cells/xor3v1x05.ap b/pdks/symbolic/vsclib/cells/xor3v1x05.ap new file mode 100755 index 000000000..24ce0b3e7 --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xor3v1x05.ap @@ -0,0 +1,174 @@ +V ALLIANCE : 6 +H xor3v1x05,P, 5/ 7/2024,100 +A 0,0,12000,7200 +R 10000,1600,ref_ref,z_16 +R 10800,1600,ref_ref,z_16 +R 11600,2400,ref_ref,z_24 +R 11600,3200,ref_ref,z_32 +R 11600,4000,ref_ref,z_40 +R 11600,4800,ref_ref,z_48 +R 1200,2400,ref_ref,a_24 +R 1200,5600,ref_ref,b_56 +R 2000,2400,ref_ref,a_24 +R 2000,3200,ref_ref,a_32 +R 400,4800,ref_ref,b_48 +R 400,5600,ref_ref,b_56 +R 6800,3200,ref_ref,c_32 +R 6800,4000,ref_ref,c_40 +R 6800,4800,ref_ref,c_48 +R 7600,4000,ref_ref,c_40 +S 5900,1200,5900,2500,1000,*,UP,TALU7 +S 5000,3800,5000,4200,200,*,DOWN,POLY +S 5800,3600,9000,3600,200,*,RIGHT,POLY +S 7000,2300,7000,2800,200,*,UP,POLY +S 0,400,12000,400,800,*,RIGHT,ALU1 +S 0,400,12000,400,800,vss,RIGHT,CALU1 +S 0,5400,12000,5400,4400,*,RIGHT,NWELL +S 0,6800,12000,6800,800,*,RIGHT,ALU1 +S 0,6800,12000,6800,800,vdd,RIGHT,CALU1 +S 10000,1600,10000,1600,400,z,LEFT,CALU1 +S 10000,2300,10000,4500,200,*,UP,POLY +S 10000,2300,10200,2300,200,*,RIGHT,POLY +S 10000,2400,10200,2400,200,*,RIGHT,POLY +S 10000,4500,10000,6100,200,t13,UP,PTRANS +S 10000,6100,10000,6500,200,*,UP,POLY +S 1000,1200,1000,2100,200,t04,UP,NTRANS +S 1000,2100,1000,4000,200,*,UP,POLY +S 1000,300,1000,1200,200,*,UP,POLY +S 1000,300,3100,300,200,*,RIGHT,POLY +S 10200,1200,10200,1900,200,t14,UP,NTRANS +S 10200,800,10200,1200,200,*,UP,POLY +S 10400,4900,11600,4900,400,*,RIGHT,ALU1 +S 10600,1400,10600,1700,400,n2,UP,NDIF +S 10800,1600,10800,1600,400,z,LEFT,CALU1 +S 10800,2500,10800,4100,400,*,UP,ALU1 +S 10900,1200,10900,1900,200,t16,UP,NTRANS +S 10900,1900,10900,3200,200,*,UP,POLY +S 10900,800,10900,1200,200,*,UP,POLY +S 11000,3100,11000,4500,200,*,UP,POLY +S 11000,4500,11000,6100,200,t15,UP,PTRANS +S 11000,6100,11000,6500,200,*,UP,POLY +S 11500,500,11500,1700,600,*,UP,NDIF +S 11500,5600,11500,5900,600,*,UP,PDIF +S 11600,1600,11600,4900,400,*,UP,ALU1 +S 11600,2400,11600,4800,400,z,UP,CALU1 +S 1200,2400,1200,2400,400,a,LEFT,CALU1 +S 1200,2400,2000,2400,600,*,RIGHT,ALU1 +S 1200,5600,1200,5600,400,b,LEFT,CALU1 +S 1300,3700,1300,4800,400,*,UP,ALU1 +S 1300,4800,2800,4800,400,*,RIGHT,ALU1 +S 1600,1400,1600,1900,400,*,UP,NDIF +S 1600,400,1600,1500,600,*,UP,ALU1 +S 1800,4400,1800,6300,200,t03,UP,PTRANS +S 1800,6300,1800,6700,200,*,UP,POLY +S 2000,2300,2000,3300,400,*,UP,ALU1 +S 2000,2400,2000,3200,400,a,UP,CALU1 +S 2100,1200,2100,2100,200,t02,UP,NTRANS +S 2100,2100,2100,3100,200,*,UP,POLY +S 2100,3300,3000,3300,200,*,RIGHT,POLY +S 2400,4600,2400,6700,600,*,UP,PDIF +S 2500,1500,2800,1500,400,*,RIGHT,ALU1 +S 2800,1500,2800,2400,400,*,UP,ALU1 +S 2800,2400,4800,2400,400,*,RIGHT,ALU1 +S 2800,3200,2800,5600,400,*,UP,ALU1 +S 2800,3200,3900,3200,400,*,RIGHT,ALU1 +S 2800,5600,5600,5600,400,*,RIGHT,ALU1 +S 3000,3300,3000,4400,200,*,UP,POLY +S 3000,4400,3000,6300,200,t01,UP,PTRANS +S 3000,6300,3000,6700,200,*,UP,POLY +S 3100,1200,3100,2100,200,t05,UP,NTRANS +S 3100,300,3100,1200,200,*,UP,POLY +S 3500,1600,5600,1600,400,*,RIGHT,ALU1 +S 3500,4000,3500,4800,400,*,UP,ALU1 +S 3500,4000,4800,4000,400,*,RIGHT,ALU1 +S 4000,2500,4000,4400,200,*,UP,POLY +S 4000,4400,4000,6300,200,t11,UP,PTRANS +S 4000,6300,4000,6700,200,*,UP,POLY +S 400,4700,400,5700,400,*,UP,ALU1 +S 400,4800,400,5600,400,b,UP,CALU1 +S 400,5600,1300,5600,400,*,RIGHT,ALU1 +S 400,5700,1300,5700,400,*,RIGHT,ALU1 +S 4100,1200,4100,2100,200,t12,UP,NTRANS +S 4100,2100,4100,2600,200,*,UP,POLY +S 4100,800,4100,1200,200,*,UP,POLY +S 4400,4800,5600,4800,400,*,RIGHT,ALU1 +S 4500,1400,4500,1900,400,n1,UP,NDIF +S 4800,1200,4800,2100,200,t10,UP,NTRANS +S 4800,2100,4800,3700,200,*,UP,POLY +S 4800,2400,4800,4000,400,*,UP,ALU1 +S 4800,800,4800,1200,200,*,UP,POLY +S 5000,4400,5000,6300,200,t09,UP,PTRANS +S 5000,6300,5000,6700,200,*,UP,POLY +S 500,1700,500,3700,400,*,UP,ALU1 +S 500,3700,1300,3700,400,*,RIGHT,ALU1 +S 500,4700,500,5700,400,*,UP,ALU1 +S 5400,400,5400,900,600,*,UP,ALU1 +S 5400,800,5400,1900,600,*,UP,NDIF +S 5600,1600,5600,4800,400,*,UP,ALU1 +S 5600,3400,5900,3400,400,*,RIGHT,ALU1 +S 6400,1900,7800,1900,400,*,RIGHT,ALU1 +S 6500,1700,6500,2000,600,*,UP,NDIF +S 6800,2700,6800,4900,400,*,UP,ALU1 +S 6800,3200,6800,4800,400,c,UP,CALU1 +S 6800,4000,7700,4000,400,*,RIGHT,ALU1 +S 6900,4600,7800,4600,200,*,RIGHT,POLY +S 7000,1500,7000,2200,200,t07,UP,NTRANS +S 7000,300,7000,1500,200,*,UP,POLY +S 7000,300,9200,300,200,*,RIGHT,POLY +S 700,4000,1800,4000,200,*,RIGHT,POLY +S 700,4000,700,4700,200,*,UP,POLY +S 7200,5700,11600,5700,400,*,RIGHT,ALU1 +S 7600,1000,7600,2000,600,*,UP,NDIF +S 7600,4000,7600,4000,400,c,LEFT,CALU1 +S 7600,400,7600,1100,600,*,UP,ALU1 +S 7800,1900,7800,3300,400,*,UP,ALU1 +S 7800,3300,9900,3300,400,*,RIGHT,ALU1 +S 7800,5000,7800,6600,200,t06,UP,PTRANS +S 8200,1200,8200,1900,200,t18,UP,NTRANS +S 8200,1900,8200,3600,200,*,UP,POLY +S 8400,4700,8400,6700,600,*,UP,PDIF +S 8600,3300,8600,5700,400,*,UP,ALU1 +S 8700,1500,8700,2500,400,*,UP,ALU1 +S 8700,2500,10800,2500,400,*,RIGHT,ALU1 +S 9000,3600,9000,4500,200,*,UP,POLY +S 9000,4500,9000,6100,200,t17,UP,PTRANS +S 9000,6100,9000,6500,200,*,UP,POLY +S 9200,1200,9200,1900,200,t08,UP,NTRANS +S 9200,1900,9200,2300,200,*,UP,POLY +S 9200,300,9200,1200,200,*,UP,POLY +S 9500,4100,10800,4100,400,*,RIGHT,ALU1 +S 9500,4100,9500,4900,400,*,UP,ALU1 +S 9600,1400,9600,1700,600,*,UP,NDIF +S 9600,1600,11600,1600,400,*,RIGHT,ALU1 +V 10500,4900,CONT_DIF_P,* +V 10800,3200,CONT_POLY,zn +V 11500,5700,CONT_DIF_P,cn +V 11500,600,CONT_DIF_N,* +V 1300,4700,CONT_DIF_P,bn +V 1600,1500,CONT_DIF_N,* +V 2000,3100,CONT_POLY,* +V 2400,6600,CONT_DIF_P,* +V 2600,1500,CONT_DIF_N,an +V 3500,4700,CONT_DIF_P,an +V 3600,1600,CONT_DIF_N,iz +V 3800,3200,CONT_POLY,bn +V 4500,4800,CONT_DIF_P,iz +V 4800,3800,CONT_POLY,an +V 500,1800,CONT_DIF_N,bn +V 500,4800,CONT_POLY,* +V 5400,900,CONT_DIF_N,* +V 5500,5600,CONT_DIF_P,bn +V 5800,3400,CONT_POLY,iz +V 6300,6600,CONT_BODY_N,* +V 6400,600,CONT_BODY_P,* +V 6500,1900,CONT_DIF_N,cn +V 6800,2800,CONT_POLY,* +V 6800,4400,CONT_POLY,* +V 7300,5700,CONT_DIF_P,cn +V 7600,1100,CONT_DIF_N,* +V 8400,6600,CONT_DIF_P,* +V 8700,1600,CONT_DIF_N,zn +V 9500,4800,CONT_DIF_P,zn +V 9700,1600,CONT_DIF_N,* +V 9800,3300,CONT_POLY,cn +EOF diff --git a/pdks/symbolic/vsclib/cells/xor3v1x05.vbe b/pdks/symbolic/vsclib/cells/xor3v1x05.vbe new file mode 100755 index 000000000..db33f720e --- /dev/null +++ b/pdks/symbolic/vsclib/cells/xor3v1x05.vbe @@ -0,0 +1,44 @@ +ENTITY xor3v1x05 IS +GENERIC ( + CONSTANT area : NATURAL := 8640; + CONSTANT cin_a : NATURAL := 4; + CONSTANT cin_b : NATURAL := 5; + CONSTANT cin_c : NATURAL := 5; + CONSTANT rdown_a_z : NATURAL := 4780; + CONSTANT rdown_b_z : NATURAL := 4780; + CONSTANT rdown_c_z : NATURAL := 4510; + CONSTANT rup_a_z : NATURAL := 6180; + CONSTANT rup_b_z : NATURAL := 6180; + CONSTANT rup_c_z : NATURAL := 5980; + CONSTANT tphl_a_z : NATURAL := 166; + CONSTANT tphh_a_z : NATURAL := 167; + CONSTANT tphl_b_z : NATURAL := 135; + CONSTANT tphh_b_z : NATURAL := 136; + CONSTANT tphl_c_z : NATURAL := 36; + CONSTANT tphh_c_z : NATURAL := 67; + CONSTANT tplh_c_z : NATURAL := 91; + CONSTANT tpll_c_z : NATURAL := 97; + CONSTANT tplh_b_z : NATURAL := 182; + CONSTANT tpll_b_z : NATURAL := 181; + CONSTANT tplh_a_z : NATURAL := 170; + CONSTANT tpll_a_z : NATURAL := 169; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + a : in BIT; + b : in BIT; + c : in BIT; + z : out BIT; + vdd : in BIT; + vss : in BIT +); +END xor3v1x05; + +ARCHITECTURE behaviour_data_flow OF xor3v1x05 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on xor3v1x05" + SEVERITY WARNING; + z <= ((a xor b) xor c) after 268 ps; +END; diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/Sky130vscSetup.py b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/Sky130vscSetup.py new file mode 100644 index 000000000..d2af379d5 --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/Sky130vscSetup.py @@ -0,0 +1,64 @@ +import sys +import os +import socket +from pathlib import Path +from coriolis.designflow.task import ShellEnv +from coriolis.designflow.yosys import Yosys +from coriolis.designflow.klayout import DRC +from coriolis.designflow.technos import Where + + +__all__ = [ 'setupSky130_vsc' ] + + +def setupSky130_vsc ( checkToolkit=None ): + Where( checkToolkit ) + ShellEnv().export() + + pdkDir = Where.coriolisTop / 'pdk' + coriolisTechDir = pdkDir / 'sky130_vsc/libs.tech' + if not pdkDir.is_dir(): + print( '[ERROR] technos.setupSky130_vsc(): PDK directory do *not* exists:' ) + print( ' "{}"'.format(pdkDir.as_posix()) ) + sys.path.append( coriolisTechDir.as_posix() ) + + cellsTop = Path('coiolis/cells') + liberty = cellsTop / 'vsclib/vsclib.lib' + #kdrcRules = pdkDir / 'klayout' / 'drc_sky130.lydrc' + + from coriolis import Cfg + from coriolis import Viewer + from coriolis import CRL + from coriolis.helpers import overlay, l, u, n + from python import techno, vsclib + + techno.setup( coriolisTechDir ) + vsclib.setup( cellsTop ) + + with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.misc.minTraceLevel = 1900 + cfg.misc.maxTraceLevel = 3000 + cfg.katana.eventsLimit = 1000000 + cfg.katana.termSatReservedLocal = 6 + cfg.katana.termSatThreshold = 9 + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + Yosys.setLiberty( liberty ) + #DRC.setDrcRules( kdrcRules ) + ShellEnv.CHECK_TOOLKIT = Where.checkToolkit.as_posix() + + path = None + for pathVar in [ 'PATH', 'path' ]: + if pathVar in os.environ: + path = os.environ[ pathVar ] + os.environ[ pathVar ] = path + ':' + (Where.allianceTop / 'bin').as_posix() + break + + diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/__init__.py b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/__init__.py new file mode 100644 index 000000000..b87e091fc --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/__init__.py @@ -0,0 +1,5 @@ + +import os +from pathlib import Path + +path = Path( os.path.dirname(os.path.abspath(__file__)) ) diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/sky130_vsc.rds b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/sky130_vsc.rds new file mode 100644 index 000000000..882ca91a0 --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/sky130_vsc.rds @@ -0,0 +1,862 @@ +# 20230301 +# --------------------------------------------------------------------------- +# For SkyWater130 +# --------------------------------------------------------------------------- + + + + +# ------------------------------------------------------------------- +# globals define +# ------------------------------------------------------------------- + +define physical_grid 0.005 +define lambda 0.075 + +table cif_layer +# ------------------------------------------------------------------- +# rds_name cif_name +# ------------------------------------------------------------------- + rds_nwell nwell +# rds_pwell pwel + rds_activ diff + rds_ntie tap + rds_ptie tap + rds_ndif nsdm + rds_pdif psdm + rds_nimp nsdm + rds_pimp psdm + rds_poly poly + rds_alu1 li1 + rds_alu2 met1 + rds_alu3 met2 + rds_alu4 met3 + rds_alu5 met4 + rds_alu6 met5 + rds_cont licon1 + rds_via1 mcon + rds_via2 via + rds_via3 via2 + rds_via4 via3 + rds_via5 via4 + rds_cpas pad +end + +table gds_layer +# ------------------------------------------------------------------- +# rds_name gds_number gds_datatype gds_pin_layer gds_pin_datatype +# This version is incompatible with oriinal Alliance for 2nd number +# ------------------------------------------------------------------- + rds_nwell 64 20 + rds_pwell 64 44 + rds_activ 65 20 + rds_ptie 65 44 + rds_ntie 65 44 + rds_pdif 94 20 + rds_ndif 93 44 + rds_pimp 94 20 + rds_nimp 93 44 + rds_poly 66 20 + rds_alu1 67 20 67 16 + rds_alu2 68 20 68 16 + rds_alu3 69 20 69 16 + rds_alu4 70 20 70 16 + rds_alu5 71 20 71 16 + rds_alu6 72 20 72 16 + rds_cont 66 44 + rds_via1 67 44 + rds_via2 68 44 + rds_via3 69 44 + rds_via4 70 44 + rds_via5 71 44 + rds_cpas 76 20 +end + +table lynx_resistor +# ------------------------------------------------------------------- +# rds_name square_resistor(ohm/square) # typical values +# ------------------------------------------------------------------- + rds_poly 48 + rds_alu1 13 + rds_alu2 0.125 + rds_alu3 0.125 + rds_alu4 0.047 + rds_alu5 0.047 + rds_alu6 0.029 + rds_cont 15 + rds_via1 152 + rds_via2 4.5 + rds_via3 3.4 + rds_via4 3.4 + rds_via5 0.38 +end + +table lynx_capa +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- + rds_poly 106.2e-6 55.3e-6 # Ca max POLY_NWELL 2Cf0 max POLY_NWELL + rds_alu1 37.9e-6 40.7e-6 # Ca max M1_NWELL 2Cf0 max M1_NWELL + rds_alu2 25.8e-6 40.6e-6 # Ca max M2_NWELL 2Cf0 max M2_NWELL + rds_alu3 16.9e-6 37.8e-6 # Ca max M3_NWELL 2Cf0 max M3_NWELL + rds_alu4 12.4e-6 41.0e-6 # Ca max M4_NWELL 2Cf0 max M4_NWELL + rds_alu5 8.4e-6 36.7e-6 # hyp + rds_alu6 6.3e-6 38.9e-6 +end + +table lynx_capa_poly +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_poly2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu1 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu2 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu3 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu4 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end + +table lynx_capa_alu5 +# ------------------------------------------------------------------- +# rds_name area_capa(pif/um^2) peri_capa(pif/um) +# ------------------------------------------------------------------- +end +table mbk_to_rds_segment +# ---------------------------------------------------------------------------------- +# mbk_name rds_name1 dlr dwr offset mode rds_name2 dlr dwr offset mode +# ---------------------------------------------------------------------------------- + + + nwell rds_nwell vw 0.300 0.0 .0 all\ +# rds_pimp vw 0.0 -0.80 .275 all \ +# rds_nimp vw 0.0 -1.80 4.15 all +# rds_nimp vw 0.225 0.170 .0 all + + pwell rds_pwell vw 0.300 0.0 .0 all +# rds_nimp vw 0.225 0.170 .0 all + + ndif rds_activ vw 0.15 0.0 .0 all\ + rds_nimp vw 0.275 0.25 .0 all\ + rds_ndif vw 0.15 0.0 .0 all + + pdif rds_activ vw 0.15 0.0 .0 all\ + rds_pimp vw 0.275 0.25 .0 all\ + rds_pdif vw 0.15 0.0 .0 all + + ntie rds_ntie vw 0.10 0.0 .0 all\ + rds_nimp vw 0.225 0.25 .0 all +# rds_activ vw 0.15 0.0 .0 all + + ptie rds_ptie vw 0.10 0.0 .0 all\ + rds_pimp vw 0.225 0.25 .0 all +# rds_activ vw 0.15 0.0 .0 all +# rds_pwell vw 0.460 0.510 .0 all + + + ntrans rds_poly vw 0.13 0.00 .0 all\ + rds_nimp vw 0.125 0.80 .0 all\ + rds_activ vw 0.0 0.55 .0 drc\ + rds_ndif lcw 0.0 0.275 .0 ext\ + rds_ndif rcw 0.0 0.275 .0 ext + + ptrans rds_poly vw 0.13 0.00 .0 all\ + rds_pimp vw 0.125 0.80 .0 all\ + rds_activ vw 0.0 0.55 .0 drc\ + rds_pdif lcw 0.0 0.275 .0 ext\ + rds_pdif rcw 0.0 0.275 .0 ext + + poly rds_poly vw 0.075 0.0 .0 all + + alu1 rds_alu1 vw 0.125 0.03 .0 all + calu1 rds_alu1 vw 0.125 0.03 .0 all + talu1 rds_talu1 vw 0.125 0.03 .0 all + + alu2 rds_alu2 vw 0.125 0.05 .0 all + calu2 rds_alu2 vw 0.125 0.05 .0 all + talu2 rds_talu2 vw 0.125 0.05 .0 all + + alu3 rds_alu3 vw 0.125 0.07 .0 all + calu3 rds_alu3 vw 0.125 0.07 .0 all + talu3 rds_talu3 vw 0.125 0.07 .0 all + + alu4 rds_alu4 vw 0.095 0.19 .0 all + calu4 rds_alu4 vw 0.095 0.19 .0 all + talu4 rds_talu4 vw 0.095 0.19 .0 all + + alu5 rds_alu5 vw 0.095 0.19 .0 all + calu5 rds_alu5 vw 0.095 0.19 .0 all + talu5 rds_talu5 vw 0.095 0.19 .0 all + + alu6 rds_alu6 vw 0.30 0.0 .0 all + calu6 rds_alu6 vw 0.30 0.0 .0 all + talu6 rds_talu6 vw 0.30 0.0 .0 all + + talu7 rds_nimp vw 0.00 0.0 .0 all + talu8 rds_pimp vw 0.00 0.0 .0 all +end + +table mbk_to_rds_connector +# ------------------------------------------------------------------- +# mbk_name rds_name der dwr +# ------------------------------------------------------------------- +end + +table mbk_to_rds_reference +# ------------------------------------------------------------------- +# mbk_name rds_name width +# ------------------------------------------------------------------- + ref_ref rds_ref 0.330 + ref_con rds_ref 0.330 +end + +table mbk_to_rds_via +# ------------------------------------------------------------------- +# mbk_name rds_name1 width mode rds_name2 width mode ... +## ------------------------------------------------------------------ +# difftap.5 +# licon.7 0.170+0.120*2 + cont_body_n \ + rds_cont 0.170 all\ + rds_alu1 0.410 all\ + rds_nimp 0.660 all\ + rds_ntie 0.410 all + +# licon.7 0.170+0.120*2 +# difftap.5 + cont_body_p \ + rds_cont 0.170 all\ + rds_alu1 0.410 all\ + rds_pimp 0.660 all\ + rds_ptie 0.410 all + +# licon.5c + cont_dif_n \ + rds_cont 0.170 all\ + rds_alu1 0.330 all\ + rds_activ 0.290 drc\ + rds_nimp 0.540 all\ + rds_ndif 0.290 all + +# licon.5c + cont_dif_p \ + rds_cont 0.170 all\ + rds_alu1 0.330 all\ + rds_activ 0.290 drc\ + rds_pimp 0.540 all\ + rds_pdif 0.290 all + +# licon.8a +# NPC --> poly2 + cont_poly \ + rds_cont 0.170 all\ + rds_poly 0.330 all\ + rds_alu1 0.330 all + +# m1.4 +# NPC --> poly2 +# m1.5 + cont_via \ + rds_via1 0.170 all\ + rds_alu1 0.330 all\ + rds_alu2 0.350 all + +# via.1b +# via.5b +# m2.5 + cont_via2 \ + rds_via2 0.150 all\ + rds_alu2 0.350 all\ + rds_alu3 0.370 all + +# via.1b +# via.5b +# m2.5 + cont_via3 \ + rds_via3 0.200 all\ + rds_alu3 0.370 all\ + rds_alu4 0.490 all + + cont_via4 \ + rds_via4 0.200 all\ + rds_alu4 0.490 all\ + rds_alu5 0.490 all +end + +table mbk_to_rds_bigvia_hole +# ------------------------------------------------------------------- +# mbk_via_name rds_hole_name side step mode +# ------------------------------------------------------------------- +CONT_VIA RDS_VIA1 0.17 0.34 ALL +CONT_VIA2 RDS_VIA2 0.15 0.32 ALL +CONT_VIA3 RDS_VIA3 0.20 0.40 ALL +CONT_VIA4 RDS_VIA4 0.20 0.40 ALL # should be more than 4 +CONT_VIA5 RDS_VIA5 0.80 1.60 ALL # should be more than 4 +end + +table mbk_to_rds_bigvia_metal +# ------------------------------------------------------------------- +# mbk_via_name rds_name dwr overlap mode +# ------------------------------------------------------------------- +CONT_VIA RDS_ALU1 0.0 0.330 ALL RDS_ALU2 0.0 0.330 ALL +CONT_VIA2 RDS_ALU2 0.0 0.370 ALL RDS_ALU3 0.0 0.370 ALL +CONT_VIA3 RDS_ALU3 0.0 0.370 ALL RDS_ALU4 0.0 0.370 ALL +CONT_VIA4 RDS_ALU4 0.0 0.5 ALL RDS_ALU5 0.0 0.380 ALL +CONT_VIA5 RDS_ALU5 0.0 0.5 ALL RDS_ALU6 0.0 0.8 ALL +end + +table mbk_to_rds_turnvia +# ------------------------------------------------------------------- +# mbk_name rds_name dwr mode +# ------------------------------------------------------------------- + cont_turn1 rds_alu1 0.03 all + cont_turn2 rds_alu2 0.03 all + cont_turn3 rds_alu3 0.03 all + cont_turn4 rds_alu4 0.00 all + cont_turn5 rds_alu5 0.00 all +end + +table lynx_bulk_implicit +# ------------------------------------------------------------------- +# rds_name type[explicit|implicit] +# ------------------------------------------------------------------- +end + +table lynx_transistor +# ------------------------------------------------------------------- +# mbk_name trans_name compostion +# ------------------------------------------------------------------- + ntrans ntrans c_x_n rds_poly rds_ndif rds_ndif rds_pwell + ptrans ptrans c_x_p rds_poly rds_pdif rds_pdif rds_nwell +end + +table lynx_diffusion +# ------------------------------------------------------------------- +# rds_name compostion +# ------------------------------------------------------------------- + rds_ndif rds_activ 1 rds_nimp 1 rds_nwell 0 + rds_pdif rds_activ 1 rds_pimp 1 rds_nwell 1 + rds_ntie rds_activ 1 rds_nimp 1 rds_nwell 1 + rds_ptie rds_activ 1 rds_pimp 1 rds_nwell 0 +end + +table lynx_graph +# ------------------------------------------------------------------- +# rds_name in_contact_with rds_name1 rds_name2 ... +# ------------------------------------------------------------------- + rds_ndif rds_cont rds_ndif + rds_pdif rds_cont rds_pdif + rds_poly rds_cont rds_poly + rds_cont rds_pdif rds_ndif rds_poly rds_alu1 rds_cont + rds_alu1 rds_cont rds_via1 rds_ref rds_alu1 + rds_ref rds_cont rds_via1 rds_alu1 rds_ref + rds_alu2 rds_via1 rds_via2 rds_alu2 + rds_alu3 rds_via2 rds_via3 rds_alu3 + rds_alu4 rds_via3 rds_via4 rds_alu4 + rds_alu5 rds_via4 rds_via5 rds_alu5 + RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 + RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 + RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 + RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 + RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 +end + +table s2r_oversize_denotch +# ------------------------------------------------------------------- +# rds_name oversized_value_for_denotching +# ------------------------------------------------------------------- + rds_nwell 0.635 +# rds_pwell 0.635 + rds_poly 0.100 + rds_alu1 0.080 + rds_alu2 0.080 + rds_alu3 0.080 + rds_alu4 0.080 + rds_alu5 0.080 + rds_activ 0.130 + rds_ntie 0.190 + rds_ptie 0.190 + rds_nimp 0.190 + rds_pimp 0.190 +end + +table s2r_bloc_ring_width +# ------------------------------------------------------------------- +# rds_name ring_width_to_copy_up +# ------------------------------------------------------------------- + rds_nwell 0. # [ RD_NWEL ] +# rds_pwell 0. # [ RD_PWEL ] + rds_poly 0. # [ RD_POLY ] + rds_alu1 0. # [ RD_ALU1 ] + rds_alu2 0. # [ RD_ALU2 ] + rds_alu3 0. # [ RD_ALU3 ] + rds_alu4 0. # [ RD_ALU3 ] + rds_alu5 0. # [ RD_ALU3 ] + rds_activ 0. # [ RD_ACTI ] + rds_ntie 0. # [ RD_NIMP ] + rds_ptie 0. # [ RD_PIMP ] + rds_nimp 0. # [ RD_NIMP ] + rds_pimp 0. # [ RD_PIMP ] +end + +table s2r_minimum_layer_width +# ------------------------------------------------------------------- +# rds_name min_layer_width_to_keep +# ------------------------------------------------------------------- + rds_nwell 0.840 +# rds_pwell 0.840 + rds_poly 0.150 + rds_alu1 0.170 + rds_alu2 0.170 + rds_alu3 0.170 + rds_alu4 0.300 + rds_alu5 0.300 + rds_activ 0.420 + rds_ntie 0.380 + rds_ptie 0.380 + rds_nimp 0.380 + rds_pimp 0.380 +end + +table s2r_post_treat +# ------------------------------------------------------------------- +# rds_name s2r_must_treat_or_not second_layer_whenever_scotch +# ------------------------------------------------------------------- + rds_nwell treat null +# rds_pwell treat null + rds_poly treat null + rds_activ treat null + rds_ntie treat null + rds_ptie treat null + rds_nimp treat null + rds_pimp treat null + rds_alu1 treat null + rds_alu2 treat null + rds_alu3 treat null + rds_alu4 treat null + rds_alu5 treat null + rds_cont notreat null +end + +DRC_RULES + +layer RDS_NWELL 0.840 ; +layer RDS_NTIE 0.380 ; +layer RDS_PTIE 0.380 ; +layer RDS_NIMP 0.380 ; +layer RDS_PIMP 0.380 ; +layer RDS_ACTIV 0.420 ; +layer RDS_CONT 0.170 ; +layer RDS_POLY 0.150 ; +layer RDS_VIA1 0.300 ; +layer RDS_VIA2 0.300 ; +layer RDS_VIA3 0.300 ; +layer RDS_VIA4 0.300 ; +layer RDS_VIA5 0.300 ; +layer RDS_ALU1 0.140 ; +layer RDS_ALU2 0.140 ; +layer RDS_ALU3 0.140 ; +layer RDS_ALU4 0.300 ; +layer RDS_ALU5 0.300 ; +layer RDS_ALU6 0.300 ; +layer RDS_USER0 0.005 ; +layer RDS_USER1 0.005 ; +layer RDS_USER2 0.005 ; + +regles + +# note : ``min'' is different from ``>=''. +# min is applied on polygons and >= is applied on rectangles. +# there is the same difference between max and <=. +# >= is faster than min, but min must be used where it is +# required to consider polygons, for example distance of +# two objects in the same layer +# +# ---------------------------------------------------------- + +# check the nwell shapes +# ---------------------- +characterize RDS_NWELL ( + rule 1 : width >= 0.840 ; + rule 2 : intersection_length min 0.840 ; + rule 3 : notch >= 1.270 ; +); +relation RDS_NWELL , RDS_NWELL ( + rule 4 : spacing axial min 1.270 ; +); +relation RDS_NWELL , RDS_ACTI ( + rule 5 : spacing axial min 0.340 ; +); + +# check the RDS_PIMP shapes +# ------------------------- +characterize RDS_PIMP ( + rule 6 : surface min 0.265 ; + rule 7 : width >= 0.380 ; + rule 8 : intersection_length min 0.380 ; + rule 9 : notch >= 0.380 ; +); +relation RDS_PIMP , RDS_PIMP ( + rule 10 : spacing axial min 0.380 ; +); + +# check the RDS_NIMP shapes +# ------------------------- +characterize RDS_NIMP ( + rule 11 : surface min 0.265 ; + rule 12 : width >= 0.380 ; + rule 13 : intersection_length min 0.380 ; + rule 14 : notch >= 0.380 ; +); +relation RDS_NIMP , RDS_NIMP ( + rule 15 : spacing axial min 0.380 ; +); + +# check the RDS_PTIE shapes +# ------------------------- +characterize RDS_PTIE ( +# rule 16 : surface min 0.255 ; + rule 17 : width >= 0.150 ; + rule 18 : intersection_length min 0.150 ; + rule 19 : notch >= 0.270 ; +); +relation RDS_PTIE , RDS_PTIE ( + rule 20 : spacing axial min 0.270 ; +); + +# check the RDS_NTIE shapes +# ------------------------- +characterize RDS_NTIE ( +# rule 21 : surface min 0.265 ; + rule 22 : width >= 0.150 ; + rule 23 : intersection_length min 0.150 ; + rule 24 : notch >= 0.270 ; +); +relation RDS_NTIE , RDS_NTIE ( + rule 25 : spacing axial min 0.270 ; +); + +# check the RDS_ACTI shapes +# ------------------------- +characterize RDS_ACTI ( + rule 26 : surface min 0.000 ; + rule 27 : width >= 0.420 ; + rule 28 : intersection_length min 0.420 ; + rule 29 : notch >= 0.270 ; +); +relation RDS_ACTI, RDS_ACTI ( + rule 30 : spacing axial min 0.270 ; +); + +# check the RDS_NIMP RDS_PTIE exclusion +# ------------------------------------- +define RDS_NIMP , RDS_PTIE intersection -> NPIMP; +characterize NPIMP ( + rule 31 : width = 0. ; +); +undefine NPIMP; + +# check the RDS_NTIE RDS_PIMP exclusion +# ------------------------------------- +define RDS_NTIE , RDS_PIMP intersection -> NPIMP; +characterize NPIMP ( + rule 32 : width = 0. ; +); +undefine NPIMP; + +# check the RDS_POLY shapes +# ------------------------- +characterize RDS_POLY ( + rule 33 : width >= 0.150 ; + rule 34 : intersection_length min 0.150 ; + rule 35 : notch >= 0.210 ; +); +relation RDS_POLY , RDS_POLY ( + rule 36 : spacing axial min 0.210 ; +); + +define RDS_ACTI , RDS_POLY intersection -> channel; + + # check the channel shapes + # ------------------------- + characterize channel ( + rule 37 : notch >= 0.210 ; + ); + relation channel , channel ( + rule 38 : spacing axial min 0.210 ; + ); + +undefine channel; + +define RDS_ACTI , RDS_CONT intersection -> cont_diff; + + relation RDS_POLY , cont_diff ( + rule 39 : spacing axial >= 0.055 ; + ); + +undefine cont_diff; + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_CONT , RDS_CONT ( + rule 40 : spacing axial >= 0.170 ; +); + +characterize RDS_CONT ( + rule 41 : width = 0.170 ; + rule 42 : length = 0.170 ; +); + +# check RDS_POLY is distant from activ zone of transistor +# ------------------------------------------------------- +relation RDS_POLY , RDS_ACTIV ( + rule 43 : spacing axial >= 0.075 ; +); + +# check RDS_ALU1 shapes +# --------------------- +characterize RDS_ALU1 ( + rule 44 : surface min 0.060 ; + rule 45 : width >= 0.170 ; + rule 46 : intersection_length min 0.170 ; + rule 47 : notch >= 0.170 ; +); +relation RDS_ALU1 , RDS_ALU1 ( + rule 48 : spacing axial min 0.170 ; +); + +# check mcon layers, stacking are free +# --------------------------------------- +relation RDS_VIA1 , RDS_VIA1 ( + rule 49 : spacing axial >= 0.190 ; +); + +characterize RDS_VIA1 ( + rule 50 : width = 0.170 ; + rule 51 : length = 0.170 ; +); + + +# check RDS_ALU2 shapes +# --------------------- +characterize RDS_ALU2 ( +# rule 52 : surface min 0.085 ; + rule 53 : width >= 0.140 ; + rule 54 : intersection_length min 0.140 ; + rule 55 : notch >= 0.140 ; +); +relation RDS_ALU2 , RDS_ALU2 ( + rule 56 : spacing axial min 0.140 ; +); + + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_VIA2 , RDS_VIA2 ( + rule 57 : spacing axial >= 0.170 ; +); + +characterize RDS_VIA2 ( + rule 58 : width = 0.150 ; + rule 59 : length = 0.150 ; +); + + +# check RDS_ALU3 shapes +# --------------------- +characterize RDS_ALU3 ( +# rule 60 : surface min 0.070 ; + rule 61 : width >= 0.140 ; + rule 62 : intersection_length min 0.140 ; + rule 63 : notch >= 0.140 ; +); +relation RDS_ALU3 , RDS_ALU3 ( + rule 64 : spacing axial min 0.140 ; +); + + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_VIA3 , RDS_VIA3 ( + rule 65 : spacing axial >= 0.200 ; +); + +characterize RDS_VIA3 ( + rule 66 : width = 0.200 ; + rule 67 : length = 0.200 ; +); +# check RDS_ALU4 shapes +# --------------------- +characterize RDS_ALU4 ( +# rule 68 : surface min 0.240 ; + rule 69 : width >= 0.300 ; + rule 70 : intersection_length min 0.300 ; + rule 71 : notch >= 0.300 ; +); +relation RDS_ALU4 , RDS_ALU4 ( + rule 72 : spacing axial min 0.300 ; +); + + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_VIA4 , RDS_VIA4 ( + rule 73 : spacing axial >= 0.200 ; +); + +characterize RDS_VIA4 ( + rule 74 : width = 0.200 ; + rule 75 : length = 0.200 ; +); + +# check RDS_ALU5 shapes +# --------------------- +characterize RDS_ALU5 ( +# rule 76 : surface min 0.240 ; + rule 77 : width >= 0.300 ; + rule 78 : intersection_length min 0.300 ; + rule 79 : notch >= 0.300 ; +); +relation RDS_ALU5 , RDS_ALU5 ( + rule 80 : spacing axial min 0.300 ; +); + +# check any_via layers, stacking are free +# --------------------------------------- +relation RDS_VIA5 , RDS_VIA5 ( + rule 81 : spacing axial >= 0.200 ; +); + +characterize RDS_VIA5 ( + rule 82 : width = 0.200 ; + rule 83 : length = 0.200 ; +); + + +# check RDS_ALU6 shapes +# --------------------- +characterize RDS_ALU6 ( +# rule 84 : surface min 0.240 ; + rule 85 : width >= 0.300 ; + rule 86 : intersection_length min 0.300 ; + rule 87 : notch >= 0.300 ; +); +relation RDS_ALU6 , RDS_ALU6 ( + rule 88 : spacing axial min 0.300 ; +); + +end rules +DRC_COMMENT +1 (RDS_NWELL) Minimum width 0.840 +2 (RDS_NWELL) Intersection length 0.840 +3 (RDS_NWELL) Notch 1.270 +4 (RDS_NWELL,RDS_NWELL) Manhatan distance min 1.270 +5 (RDS_NWELL,RDS_ACTI) Manhatan distance min 0.340 +6 (RDS_PIMP) Minimum area 0.265 +7 (RDS_PIMP) Minimum width 0.380 +8 (RDS_PIMP) Intersection length 0.380 +9 (RDS_PIMP) Notch 0.380 +10 (RDS_PIMP,RDS_PIMP) Manhatan distance min 0.380 +11 (RDS_NIMP) Minimum area 0.265 +12 (RDS_NIMP) Minimum width 0.380 +13 (RDS_NIMP) Intersection length 0.380 +14 (RDS_NIMP) Notch 0.380 +15 (RDS_NIMP,RDS_NIMP) Manhatan distance min 0.380 +16 (RDS_PTIE) Minimum area 0.255 +17 (RDS_PTIE) Minimum width 0.150 +18 (RDS_PTIE) Intersection length 0.150 +19 (RDS_PTIE) Notch 0.270 +20 (RDS_PTIE,RDS_PTIE) Manhatan distance min 0.270 +21 (RDS_NTIE) Minimum area 0.265 +22 (RDS_NTIE) Minimum width 0.150 +23 (RDS_NTIE) Intersection length 0.150 +24 (RDS_NTIE) Notch 0.270 +25 (RDS_NTIE,RDS_NTIE) Manhatan distance min 0.270 +26 (RDS_ACTI) Minimum area 0.0 +27 (RDS_ACTI) Minimum width 0.420 +28 (RDS_ACTI) Intersection length 0.420 +29 (RDS_ACTI) Notch 0.270 +30 (RDS_ACTI,RDS_ACTI) Manhatan distance min 0.270 +31 (RDS_NIMP,RDS_PTIE) intersection width 0. +32 (RDS_PIMP,RDS_NTIE) intersection width 0. +33 (RDS_POLY) Minimum width 0.150 +34 (RDS_POLY) Intersection length 0.150 +35 (RDS_POLY) Notch 0.210 +36 (RDS_POLY,RDS_POLY) Manhatan distance min 0.210 +37 (channel) Notch 0.210 +38 (channel) Manhatan distance min 0.210 +39 (cont_diff) Manhatan distance min 0.055 +40 (RDS_CONT,RDS_CONT) Manhatan distance min 0.170 +41 (RDS_CONT) Width 0.170 +42 (RDS_CONT) Length 0.170 +43 (RDS_POLY,RDS_ACTIV) Manhatan distance min 0.075 +44 (RDS_ALU1) Minimum area 0.060 +45 (RDS_ALU1) Minimum width 0.170 +46 (RDS_ALU1) Intersection length 0.170 +47 (RDS_ALU1) Notch 0.170 +48 (RDS_ALU1,RDS_ALU1) Manhatan distance min 0.170 +49 (RDS_VIA1,RDS_VIA1) Manhatan distance mcon min 0.190 +50 (RDS_VIA1) mcon width 0.170 +51 (RDS_VIA1) mcon length 0.170 +52 (RDS_ALU2) Minimum area 0.083 +53 (RDS_ALU2) Minimum width 0.140 +54 (RDS_ALU2) Intersection length 0.140 +55 (RDS_ALU2) Notch 0.140 +56 (RDS_ALU2,RDS_ALU2) Manhatan distance min 0.140 +57 (RDS_VIA2,RDS_VIA2) Manhatan distance via min 0.170 +58 (RDS_VIA2) via width 0.150 +59 (RDS_VIA2) via length 0.150 +60 (RDS_ALU3) Minimum area 0.0676 +61 (RDS_ALU3) Minimum width 0.140 +62 (RDS_ALU3) Intersection length 0.140 +63 (RDS_ALU3) Notch 0.140 +64 (RDS_ALU3,RDS_ALU3) Manhatan distance min 0.140 +65 (RDS_VIA3,RDS_VIA3) Manhatan distance via min 0.200 +66 (RDS_VIA3) via width 0.200 +67 (RDS_VIA3) via length 0.200 +68 (RDS_ALU4) Minimum area 0.240 +69 (RDS_ALU4) Minimum width 0.300 +70 (RDS_ALU4) Intersection length 0.300 +71 (RDS_ALU4) Notch 0.300 +72 (RDS_ALU4,RDS_ALU4) Manhatan distance min 0.300 +73 (RDS_VIA4,RDS_VIA4) Manhatan distance via min 0.200 +74 (RDS_VIA4) via width 0.200 +75 (RDS_VIA4) via length 0.200 +76 (RDS_ALU5) Minimum area 0.240 +77 (RDS_ALU5) Minimum width 0.300 +78 (RDS_ALU5) Intersection length 0.300 +79 (RDS_ALU5) Notch 0.300 +80 (RDS_ALU5,RDS_ALU5) Manhatan distance min 0.300 +81 (RDS_VIA5,RDS_VIA5) Manhatan distance via min 0.200 +82 (RDS_VIA5) via width 0.200 +83 (RDS_VIA5) via length 0.200 +84 (RDS_ALU6) Minimum area 0.240 +85 (RDS_ALU6) Minimum width 0.300 +86 (RDS_ALU6) Intersection length 0.300 +87 (RDS_ALU6) Notch 0.300 +88 (RDS_ALU6,RDS_ALU6) Manhatan distance min 0.300 +END_DRC_COMMENT +END_DRC_RULES diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/spimodel.cfg b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/spimodel.cfg new file mode 100644 index 000000000..c58ef6c96 --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/spimodel.cfg @@ -0,0 +1,5 @@ +# MBK_SPI_MODEL +# configure the transistor models of spi parser/driver +# +sky130_fd_pr__nfet_01v8__model N +sky130_fd_pr__pfet_01v8__model P diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/symbolic.dreal b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/symbolic.dreal new file mode 100644 index 000000000..3c39bd85c --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/symbolic.dreal @@ -0,0 +1,127 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Dreal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 02/08/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +dEFINE DREAL_LOWER_FIGURE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_INSTANCE_STEP 0.1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_CONNECTOR_STEP 0.5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_SEGMENT_STEP 0.7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_LOWER_REFERENCE_STEP 1.0 + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Dreal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE DREAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TAbLE DREAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_TALU7 Talu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_ALU8 Alu8 blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/symbolic.graal b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/symbolic.graal new file mode 100644 index 000000000..4fff22f0c --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/symbolic.graal @@ -0,0 +1,386 @@ +# /*------------------------------------------------------------\ +# | | +# | Title : Parameters File for Graal | +# | | +# | Technology : Cmos V7 | +# | | +# | Date : 27/06/95 | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Graal Peek Bound in lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_PEEK_BOUND 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Grid Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_GRID_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Lower Figure Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_FIGURE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Instance Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_INSTANCE_STEP 1 + +# /*------------------------------------------------------------\ +# | | +# | Lower Connector Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_CONNECTOR_STEP 5 + +# /*------------------------------------------------------------\ +# | | +# | Lower Segment Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_SEGMENT_STEP 7 + +# /*------------------------------------------------------------\ +# | | +# | Lower Reference Text Step in pixel by lambda | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_LOWER_REFERENCE_STEP 10 + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Color Name | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_COLOR_NAME Gray + +# /*------------------------------------------------------------\ +# | | +# | Graal Cursor Size in pixel | +# | | +# \------------------------------------------------------------*/ + +DEFINE GRAAL_CURSOR_SIZE 10 + +# /*------------------------------------------------------------\ +# | | +# | Segment Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_NAME + + NWELL Nwell tan Black + PWELL Pwell light_yellow Black + NDIF Ndif lawn_green Black + PDIF Pdif yellow Black + NTIE Ntie spring_green Black + PTIE Ptie light_goldenrod Black + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 GReen Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + TPOLY Tpoly hot_pink Black + TALU1 Talu1 royal_blue Black + TALU2 Talu2 turquoise Black + TALU3 Talu3 light_pink Black + TALU4 Talu4 green Black + TALU5 Talu5 yellow Black + TALU6 Talu6 violet Black + TALU7 Talu7 red Black + TALU8 Talu8 blue Black + CALU1 CAlu1 royal_blue Black + CALU2 CAlu2 Cyan Black + CALU3 CAlu3 light_pink Black + CALU4 CAlu4 green Black + CALU5 CAlu5 yellow Black + CALU6 CAlu6 violet Black + CALU7 CAlu7 red Black + CALU8 CAlu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Transistor Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_TRANSISTOR_NAME + + NTRANS Ntrans lawn_green Black + PTRANS Ptrans yellow Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Connector Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_CONNECTOR_NAME + + POLY Poly red Black + POLY2 Poly2 orange Black + ALU1 Alu1 royal_blue Black + ALU2 Alu2 Cyan Black + ALU3 Alu3 light_pink Black + ALU4 Alu4 green Black + ALU5 Alu5 yellow Black + ALU6 Alu6 violet Black + ALU7 Alu7 red Black + ALU8 Alu8 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Length and Width for a symbolic Segment | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SEGMENT_VALUE + + NWELL 4 4 + PWELL 4 4 + NDIF 3 2 # LSX 2 -> 3 + PDIF 3 2 # LSX 2 -> 3 + NTIE 3 1 # LSX 2 -> 3 + PTIE 3 1 # LSX 2 -> 3 + NTRANS 1 5 # LSX 4 -> 5 + PTRANS 1 5 # LSX 4 -> 5 + POLY 1 1 + POLY2 1 1 + ALU1 2 1 # LSX 1 -> 2 + ALU2 2 1 + ALU3 2 1 + ALU4 2 1 + ALU5 2 1 + ALU6 2 1 + ALU7 2 1 + ALU8 2 1 + TPOLY 1 1 + TALU1 2 1 # LSX 1 -> 2 + TALU2 2 1 # LSX 2 -> 1 + TALU3 2 1 # LSX 2 -> 1 + TALU4 2 1 # LSX 2 -> 1 + TALU5 2 1 # LSX 2 -> 1 + TALU6 2 1 # LSX 2 -> 1 + TALU7 2 1 # LSX 2 -> 1 + TALU8 2 1 # LSX 2 -> 1 + CALU1 2 0 + CALU2 2 0 + CALU3 2 0 + CALU4 2 0 + CALU5 2 0 + CALU6 2 0 + CALU7 2 0 + CALU8 2 0 + +END + +# /*------------------------------------------------------------\ +# | | +# | Reference Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_REFERENCE_NAME + + REF_REF Ref_Ref red Black + REF_CON Ref_Con Cyan Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_VIA_NAME + + CONT_DIF_N Cont_NDif lawn_green Black + CONT_DIF_P Cont_PDif yellow Black + CONT_BODY_N Cont_NTie spring_green Black + CONT_BODY_P Cont_PTie light_goldenrod Black + CONT_POLY Cont_Poly red Black + CONT_POLY2 Cont_Poly2 orange Black + CONT_VIA Via_1-2 cyan Black + CONT_VIA2 Via_2-3 light_pink Black + CONT_VIA3 Via_3-4 green Black + CONT_VIA4 Via_4-5 yellow Black + CONT_VIA5 Via_5-6 violet Black + CONT_VIA6 Via_6-7 red Black + CONT_VIA7 Via_7-8 blue Black + C_X_N Cont_CxN orange Black + C_X_P Cont_CxP orange Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Big Via Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_NAME + + CONT_VIA Big_Via_1-2 cyan Black + CONT_VIA2 Big_Via_2-3 light_pink Black + CONT_VIA3 Big_Via_3-4 green Black + CONT_VIA4 Big_Via_4-5 yellow Black + CONT_VIA5 Big_Via_5-6 violet Black + CONT_VIA6 Big_Via_6-7 red Black + CONT_VIA7 Big_Via_7-8 blue Black + + CONT_TURN1 Turn_Via_1 royal_blue Black + CONT_TURN2 Turn_Via_2 Cyan Black + CONT_TURN3 Turn_Via_3 light_pink Black + CONT_TURN4 Turn_Via_4 green Black + CONT_TURN5 Turn_Via_5 yellow Black + CONT_TURN6 Turn_Via_6 violet Black + CONT_TURN7 Turn_Via_7 red Black + CONT_TURN8 Turn_Via_7 blue Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Minimun Size for a symbolic Big Via | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_BIGVIA_VALUE + + CONT_VIA 2 + CONT_VIA2 2 + CONT_VIA3 2 + CONT_VIA4 2 + CONT_VIA5 2 + CONT_VIA6 2 + CONT_VIA7 2 + + CONT_TURN1 2 + CONT_TURN2 2 + CONT_TURN3 2 + CONT_TURN4 2 + CONT_TURN5 2 + CONT_TURN6 2 + CONT_TURN7 2 + CONT_TURN8 2 + +END + +# /*------------------------------------------------------------\ +# | | +# | Orient Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_ORIENT_NAME + + NORTH North lawn_green Black + SOUTH South yellow Black + EAST East tan Black + WEST West red Black + +END + +# /*------------------------------------------------------------\ +# | | +# | Symmetry Panel Button Label, Foreground , Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_SYMMETRY_NAME + + NOSYM No_Sym LightBlue Black + SYM_X Sym_X turquoise Black + SYM_Y Sym_Y cyan Black + SYMXY Sym_XY lightCyan Black + ROT_P Rot_P MediumAquamarine Black + ROT_M Rot_M aquamarine Black + SY_RP Sym_RP green Black + SY_RM Sym_RM MediumSpringGreen Black + +END + +# /*------------------------------------------------------------\ +# | | +# | View Layer Panel Button Label, Foreground, Background Color | +# | | +# \------------------------------------------------------------*/ + +TABLE GRAAL_RDS_LAYER_NAME + + RDS_NWELL Nwell tan Black + RDS_PWELL Pwell light_yellow Black + RDS_NIMP Nimp forest_green Black + RDS_PIMP Pimp goldenrod Black + RDS_TALU7 Nimp forest_green Black + RDS_TALU8 Pimp goldenrod Black + RDS_ACTIV Activ brown Black + RDS_NDIF Ndif lawn_green Black + RDS_PDIF Pdif yellow Black + RDS_NTIE Ntie spring_green Black + RDS_PTIE Ptie light_goldenrod Black + RDS_POLY Poly red Black + RDS_POLY2 Poly2 orange Black + RDS_VPOLY VPoly coral Black + RDS_GATE Gate orange Black + RDS_TPOLY Tpoly hot_pink Black + RDS_CONT Cont dark_violet Black + RDS_TCONT TCont orchid Black + RDS_ALU1 Alu1 royal_blue Black + RDS_VALU1 VAlu1 sky_blue Black + RDS_TALU1 Talu1 royal_blue Black + RDS_VIA1 Via1 deep_sky_blue Black + RDS_TVIA1 TVia1 dodger_blue Black + RDS_ALU2 Alu2 cyan Black + RDS_TALU2 Talu2 turquoise Black + RDS_VIA2 Via2 deep_pink Black + RDS_ALU3 Alu3 light_pink Black + RDS_TALU3 Talu3 light_pink Black + RDS_VIA3 Via3 sea_green Black + RDS_ALU4 Alu4 green Black + RDS_TALU4 Talu4 green Black + RDS_VIA4 Via4 gold Black + RDS_ALU5 Alu5 yellow Black + RDS_TALU5 Talu5 yellow Black + RDS_VIA5 Via5 violet_red Black + RDS_ALU6 Alu6 violet Black + RDS_TALU6 Talu6 violet Black + RDS_VIA6 Via6 dark_red Black + RDS_ALU7 Alu7 red Black + RDS_VIA7 Via7 dark_blue Black + RDS_TALU8 Talu8 blue Black + RDS_CPAS Cpas gray Black + RDS_REF Ref coral Black + RDS_ABOX Abox pink Black + +END diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/techno.py b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/techno.py new file mode 100644 index 000000000..8575f7415 --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/techno.py @@ -0,0 +1,663 @@ + +from coriolis import CRL, Hurricane, Viewer, Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, BasicLayer, \ + RegularLayer, Cell, Net, Horizontal, Vertical, Rectilinear, \ + Box, Point, NetExternalComponents +from coriolis.technos.common.colors import toRGB +from coriolis.technos.common.patterns import toHexa +from coriolis.helpers import u +from coriolis.helpers.technology import createBL, createVia +from coriolis.helpers.overlay import CfgCache +from coriolis.helpers.analogtechno import Length, Area, Unit, Asymmetric, loadAnalogTechno, addDevice +from coriolis.designflow.task import ShellEnv + + +__all__ = [ "setup" ] + + +""" +Coriolis Design Technological Rules (DTR) for SkyWater 130nm CMOS General Purpose +================================================================================= + +:Version: rev.LIP6-1 +:Date: December 21, 2022 +:Date: February 2, 2023 +:Date: April 20, 2023 +:Authors: Marie-Minerve Louerat + +Reference documents: + https://skywater-pdk.readthedocs.io/en/main/rules/masks.html + https://skywater-pdk.readthedosc.io/en/main/rules/periphery.html#x + +Beware of the existence of li1 local interconnect using licon to connect to +difftap or to poly and mcon ton connect to metal1 + +Beware that some rules are context dependent (via spacing at end of line or at +one side, wide metal3) + +Beware different description exist of MIM capacitors +here met2, capm, met3 and via2 connects met2/capm to met3 + +===================== ======= ========== ==================================== +SkyWater130 mask Acronym Layer name Coriolis original +purpose for rule layer name +===================== ======= ========== ==================================== +N-Well NWM nwm nwell +Low Vt Nch LVTNM lvtn +active diffusion difftap active +Poly 1 P1M poly poly +P+ Implant PSDM psdm pImplant +N+ Implant NSDM nsdm nImplant +Local Intr Cont. 1 LICM1 licon cut0 contact between difftap and li1, + poly and li1 +Local Intrcnct 1 LI1M li metal metal between poly and metal1 + for local interconnect +Contact CTM1 mcon cut1 contact between li1 and metal1 +Metal 1 MM1 m1 metal1 +Via VIM via cut2 +Metal 2 MM2 m2 metal2 +Via 2-PLM VIM2 via2 cut3 +Metal 3-PLM MM3 m3 metal3 +Via 2-PLM VIM3 via3 cut4 +Metal 4 MM4 m4 metal4 +Via 4 VIM4 via4 cut5 +Metal 5 MM5 m5 metal5 + +capm CAPM capm metcap +Metal 2 MM2 bottom_plate metbot +===================== ======= ============ ==================================== + +""" + + +analogTechnologyTable = \ + ( ('Header', 'Sky130', DbU.UnitPowerMicro, 'rev.LIP6-1') + # ------------------------------------------------------------------------------------ + # ( Rule name , [Layer1] , [Layer2] , Value , Rule flags , Reference ) + , ('physicalGrid' , 0.005 , Length , 'GSF') + , ('transistorMinL' , 0.15 , Length , 'poly.1 and device details') + #, ('transistorMinL' , 0.38 , Length , 'lvtn.1a') + , ('transistorMaxL' , 38 , Length , 'rule0002') + , ('transistorMinW' , 0.42 , Length , 'difftap.2') + #, ('transistorMinW' , 0.36 , Length , 'difftap.2b') + , ('transistorMaxW' , 4000 , Length , 'rule0004') + + # N-WELL (nwm) + , ('minWidth' , 'nwm' , 0.84 , Length , 'nwell.1') + , ('minSpacing' , 'nwm' , 1.27 , Length , 'nwell.2a') + , ('minArea' , 'nwm' , 0 , Area , 'N/A') + + # LVTN (lvtn) + , ('minWidth' , 'lvtn' , 0.38 , Length , 'lvtn.1a') + , ('minSpacing' , 'lvtn' , 0.38 , Length , 'lvtn.2') + , ('minArea' , 'lvtn' , 0.265 , Area , 'lvtn.13') + , ('minEnclosure' , 'nwm' , 'lvtn' , 0.38 , Length|Asymmetric, 'lvtn.10') + + # DIFF (difftap) + , ('minWidth' , 'difftap' , 0.15 , Length , 'difftap.1') + , ('minSpacing' , 'difftap' , 0.27 , Length , 'difftap.3') + , ('minArea' , 'difftap' , 0 , Area , 'N/A') + , ('minEnclosure' , 'nwm' , 'difftap' , 0.18 , Length|Asymmetric, 'difftap.10') + + # Poly1 (poly) + , ('minWidth' , 'poly' , 0.15 , Length , 'poly.1a') + , ('minSpacing' , 'poly' , 0.21 , Length , 'poly.2') + , ('minGateSpacing' , 'poly' , 0.21 , Length , 'poly.2') + , ('minArea' , 'poly' , 0 , Area , 'N/A') + , ('minSpacing' , 'poly' , 'difftap' , 0.075 , Length , 'poly.4') + , ('minExtension' , 'poly' , 'difftap' , 0.130 , Length|Asymmetric, 'poly.8') + , ('minGateExtension' , 'difftap' , 'poly' , 0.25 , Length|Asymmetric, 'poly.7') + , ('minExtension' , 'difftap' , 'poly' , 0.25 , Length|Asymmetric, 'poly.7') + + # 4.1.6 PPLUS (psdm) + , ('minWidth' , 'psdm' , 0.38 , Length , 'psd.1') + , ('minSpacing' , 'psdm' , 0.38 , Length , 'psd.2') + , ('minArea' , 'psdm' , 0.255 , Area , 'psd.10b') + , ('minSpacing' , 'psdm' , 'difftap' , 0.130 , Length , 'psd.7') + , ('minGateExtension' , 'psdm' , 'poly' , 0.00 , Length|Asymmetric, 'N/A') + , ('minOverlap' , 'psdm' , 'difftap' , 0.00 , Length , 'N/A') + , ('minEnclosure' , 'psdm' , 'difftap' , 0.125 , Length|Asymmetric, 'psd.5a') + , ('minStrapEnclosure' , 'psdm' , 'difftap' , 0.125 , Length , 'psd.5b') + , ('minSpacing' , 'nsdm' , 'psdm' , 0.00 , Length , 'N/A') + , ('minEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minLengthEnclosure', 'psdm' , 'difftap' , 0 , Length|Asymmetric, 'N/A') + , ('minWidthEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'psdm' , 'difftap' , 0.125 , Length|Asymmetric, 'dup. psd.5a') + , ('minStrapEnclosure' , 'psdm' , 0.125 , Length , 'dup. psd.5b') + + # NPLUS (nsdm) + , ('minWidth' , 'nsdm' , 0.38 , Length , 'nsd.1') + , ('minSpacing' , 'nsdm' , 0.38 , Length , 'nsd.2') + , ('minArea' , 'nsdm' , 0.265 , Area , 'nsd.10a') + , ('minSpacing' , 'nsdm' , 'difftap' , 0.130 , Length , 'nsd.7') + , ('minGateExtension' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minOverlap' , 'nsdm' , 'difftap' , 0 , Length , 'N/A') + , ('minEnclosure' , 'nsdm' , 'difftap' , 0.125 , Length|Asymmetric, 'nsd.5a') + , ('minStrapEnclosure' , 'nsdm' , 'difftap' , 0.125 , Length , 'nsd.5b') + , ('minEnclosure' , 'nsdm' , 'nwm' , 0 , Length|Asymmetric, 'N/A') + , ('minEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minLengthEnclosure', 'nsdm' , 'difftap' , 0 , Length|Asymmetric, 'N/A') + , ('minWidthEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + , ('minGateEnclosure' , 'nsdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'nsdm' , 'difftap' , 0.125 , Length|Asymmetric, 'dup. nsd.5a') + , ('minStrapEnclosure' , 'nsdm' , 0.215 , Length , 'dup. nsd.5b') + + # LICM1 (licon) + , ('minWidth' , 'licon' , 0.17 , Length , 'licon.1') + , ('minSpacing' , 'licon' , 0.17 , Length , 'licon.2') + , ('minGateSpacing' , 'licon' , 'poly' , 0.25 , Length|Asymmetric, 'licon.10') + , ('minSpacing' , 'licon' , 'poly' , 0.25 , Length|Asymmetric, 'licon.10') + , ('minSpacing' , 'licon' , 'difftap' , 0.19 , Length , 'licon.14') + #, ('minSpacing' , 'licon' , 'difftap' , 0.06 , Length , 'licon.5b') + , ('minEnclosure' , 'difftap' , 'licon' , 0.04 , Length|Asymmetric, 'licon.5a and licon.7 : 0.12 isolated tap') + , ('minEnclosure' , 'poly' , 'licon' , 0.05 , Length|Asymmetric, 'licon.8 and licon.8a : 0.08') + , ('minEnclosure' , 'psdm' , 'licon' , 0 , Length|Asymmetric, 'N/A') + , ('minEnclosure' , 'nsdm' , 'licon' , 0 , Length|Asymmetric, 'N/A') + , ('minGateEnclosure' , 'psdm' , 'poly' , 0 , Length|Asymmetric, 'N/A') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'poly' , 'licon' , 0.05 , Length|Asymmetric, 'dup. licon.8 and licon.8a') + , ('minExtension' , 'psdm' , 'licon' , 0.25 , Length|Asymmetric, 'dup.') + , ('minExtension' , 'nsdm' , 'licon' , 0.25 , Length|Asymmetric, 'dup.') + + # LI1M (li) + , ('minWidth' , 'li' , 0.17 , Length , 'li.1') + , ('minSpacing' , 'li' , 0.17 , Length , 'li.3') + , ('minArea' , 'li' , 0.0561, Area , 'li.6') + , ('minEnclosure' , 'li' , 'licon' , 0.08 , Length|Asymmetric, 'li.5') + , ('minEnclosure' , 'li' , 'mcon' , 0.00 , Length|Asymmetric, 'ct.4') + + # CTM1 (mcon) + , ('minWidth' , 'mcon' , 0.17 , Length , 'ct.1') + , ('minSpacing' , 'mcon' , 0.19 , Length , 'ct.2') + + + # MM1 (m1) + , ('minWidth' , 'm1' , 0.14 , Length , 'm1.1') + , ('minSpacing' , 'm1' , 0.14 , Length , 'm1.2') + , ('minArea' , 'm1' , 0.083 , Area , 'm1.6') + , ('minEnclosure' , 'm1' , 'mcon' , 0.03 , Length|Asymmetric, 'm1.4 and m1.5 : 0.06 one side') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm1' , 'mcon' , 0.03 , Length|Asymmetric, 'm1.4 and m1.5') + + # VIM (via) + , ('minWidth' , 'via' , 0.15 , Length , 'via.1a') + , ('minSpacing' , 'via' , 0.17 , Length , 'via.2') + , ('minEnclosure' , 'm1' , 'via' , 0.55 , Length|Asymmetric, 'via.4a and via.5a : 0.085 on one side') + # Error: duplicated rule, needed by "old Pharos". + , ('lineExtension' , 'm1' , 'via' , 0.55 , Length|Asymmetric, 'dup. via.a4 and via.5a : 0.085 on one side') + + # MM2 (m2) + , ('minWidth' , 'm2' , 0.14 , Length , 'm2.1') + , ('minSpacing' , 'm2' , 0.14 , Length , 'm2.2') + , ('minArea' , 'm2' , 0.0676, Area , 'm2.6') + , ('minEnclosure' , 'm2' , 'via' , 0.055 , Length|Asymmetric, 'm2.4 and m2.5 : 0.085 end of line') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm2' , 'via' , 0.055 , Length|Asymmetric, 'dup. m2.4 and m2.5 : 0.085 end of line') + + # VIM2 (via2) + , ('minWidth' , 'via2' , 0.20 , Length , 'via2.1a') + , ('minSpacing' , 'via2' , 0.20 , Length , 'via2.2') + , ('minEnclosure' , 'm2' , 'via2' , 0.04 , Length|Asymmetric, 'via2.4 via2.5 : 0.085 and via2.14') + + # MM3 (m3) + , ('minWidth' , 'm3' , 0.30 , Length , 'm3.1') + , ('minSpacing' , 'm3' , 0.30 , Length , 'm3.2') + , ('minSpacing' , 'widem3' , 0.40 , Length , 'm3.3d') + , ('minArea' , 'm3' , 0.24 , Area , 'm3.6' ) + , ('minEnclosure' , 'm3' , 'via2' , 0.065 , Length|Asymmetric, 'm3.4') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm3' , 'via2' , 0.065 , Length|Asymmetric, 'dup. m3.4') + + # VIM3 (via3) + , ('minWidth' , 'via3' , 0.20 , Length , 'via3.1') + , ('minSpacing' , 'via3' , 0.20 , Length , 'via3.2') + , ('minEnclosure' , 'm3' , 'via3' , 0.060 , Length|Asymmetric, 'via3.4 and via3.5 end of line : 0.090') + + # MM4 (m4) + , ('minWidth' , 'm4' , 0.30 , Length , 'm4.1') + , ('minSpacing' , 'm4' , 0.30 , Length , 'm4.2') + , ('minArea' , 'm4' , 0.24 , Area , 'm4.4a') + , ('minEnclosure' , 'm4' , 'via3' , 0.065 , Length|Asymmetric, 'm4.3') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm4' , 'via3' , 0.065 , Length|Asymmetric, 'dup. m4.3 ') + + # VIM4 (via4) + , ('minWidth' , 'via4' , 0.80 , Length , 'via4.1') + , ('minSpacing' , 'via4' , 0.80 , Length , 'via4.2') + , ('minEnclosure' , 'm4' , 'via4' , 0.19 , Length|Asymmetric, 'via4.4') + + # MM5 (m5) + , ('minWidth' , 'm5' , 1.6 , Length , 'm5.1') + , ('minSpacing' , 'm5' , 1.6 , Length , 'm5.2') + , ('minArea' , 'm5' , 4.00 , Area , 'm5.4') + , ('minEnclosure' , 'm5' , 'via4' , 0.310 , Length|Asymmetric, 'm5.3') + # Error: duplicated rule, needed by "old Pharos". + , ('minExtension' , 'm5' , 'via4' , 0.310 , Length|Asymmetric, 'dup. m5.3 ') + + + #capm + #, ('minWidth' , 'metcap' , 1.0 , Length , 'capm.1') + #, ('minWidth' , 'metcapdum' , 0.5 , Length , '') + #, ('maxWidth' , 'metcap' , 300.0 , Length , '') + #, ('maxWidth' , 'metbot' , 350.0 , Length , '') + #, ('minSpacing' , 'metcap' , 0.84 , Length , 'capm.2a') + #, ('minSpacing' , 'metbot' , 0.8 , Length , 'metcap.2b') + #, ('minSpacing' , 'cut1' , 'metcap' , 0.50 , Length , '') + #, ('minSpacing' , 'cut2' , 'metcap' , 0.50 , Length , 'capm.5') + #, ('minSpacingOnMetbot', 'cut2' , 0.2 , Length , 'via2.2') + #, ('minSpacingOnMetbot', 'via2' , 0.2 , Length , 'via2.2') + #, ('minSpacingOnMetcap', 'cut2' , 0.2 , Length , 'via2.2') + #, ('minEnclosure' , 'm2' , 'metcap' , 0.14 , Length|Asymmetric, 'capm.3') + #, ('minEnclosure' , 'metbot' , 'cut1' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'metbot' , 'cut2' , 0.04 , Length|Asymmetric, 'via2.14') + #, ('minEnclosure' , 'metcap' , 'cut2' , 0.14 , Length|Asymmetric, 'capm.4') + #, ('minArea' , 'metcap' , 0 , Area , 'na') + #, ('minAreaInMetcap' , 'cut2' , 0 , Area , 'na') + #, ('MIMCap' , 1.25 , Unit , 'na') + #, ('MIMPerimeterCap' , 0.17 , Unit , 'na') + + + #capm + , ('minWidth' , 'capm' , 1.0 , Length , 'capm.1') + , ('minWidth' , 'capmdum' , 0.5 , Length , '') + , ('maxWidth' , 'capm' , 30.0 , Length , '') + , ('maxWidth' , 'metbot' , 35.0 , Length , '') + , ('minSpacing' , 'capm' , 0.84 , Length , 'capm.2a') + #, ('minSpacing' , 'm3' , 0.8 , Length , 'capm.2b') + , ('minSpacingWide1' , 'm2' , 0.8 , Length , 'capm.2b') + , ('minSpacing' , 'via' , 'capm' , 0.50 , Length , 'fake') + , ('minSpacing' , 'via2' , 'capm' , 0.50 , Length , 'capm.5') + , ('minSpacingOnMetBot', 'via2' , 0.2 , Length , 'via2.2') + , ('minSpacingOnMetCap', 'via2' , 0.2 , Length , 'via2.2') + , ('minSpacingOnMetBot', 'via' , 0.2 , Length , 'via2.2 fake') + , ('minSpacingOnMetCap', 'via' , 0.2 , Length , 'via2.2 fake') + , ('minEnclosure' , 'm2' , 'capm' , 0.14 , Length|Asymmetric, 'capm.3') + , ('minEnclosure' , 'm3' , 'via' , 0.055, Length|Asymmetric, 'via.4a') + #, ('minEnclosure' , 'm3' , 'via2' , 0.04 , Length|Asymmetric, 'via2.14') + , ('minEnclosure' , 'capm' , 'via' , 0.14 , Length|Asymmetric, 'capm.4 fake') + , ('minEnclosure' , 'capm' , 'via2' , 0.14 , Length|Asymmetric, 'capm.4') + , ('minArea' , 'capm' , 0 , Area , 'na') + , ('minAreaInMetcap' , 'via2' , 0 , Area , 'na') + , ('MIMCap' , 1.25 , Unit , 'na') + , ('MIMPerimeterCap' , 0.17 , Unit , 'na') + , ('PIPCap' , 1.25 , Unit , 'na') + , ('PIPPerimeterCap' , 0.17 , Unit , 'na') + + ) + + +def _loadDtr (): + """ + Load design kit physical rules for SkyWater 130nm. + """ + loadAnalogTechno( analogTechnologyTable, __file__ ) + + +def _loadDevices (): + addDevice( name = 'DifferentialPairBulkConnected' + #, spice = spiceDir+'DiffPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'DifferentialPairBulkUnconnected' + #, spice = spiceDir+'DiffPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'G1', 'G2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.DP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.DP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.DP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.DP_interdigitated.py' ) + , ('WIP DP' , 'coriolis.oroshi.wip_dp.py' ) + ) + ) + addDevice( name = 'LevelShifterBulkUnconnected' + #, spice = spiceDir+'LevelShifterBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S1', 'S2', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.LS_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.LS_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.LS_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.LS_interdigitated.py' ) + ) + ) + addDevice( name = 'TransistorBulkConnected' + #, spice = spiceDir+'TransistorBulkConnected.spi' + , connectors = ( 'D', 'G', 'S' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'TransistorBulkUnconnected' + #, spice = spiceDir+'TransistorBulkUnconnected.spi' + , connectors = ( 'D', 'G', 'S', 'B' ) + , layouts = ( ('Rotate transistor', 'coriolis.oroshi.Transistor_rotate.py') + , ('Common transistor', 'coriolis.oroshi.Transistor_common.py') + , ('WIP Transistor' , 'coriolis.oroshi.wip_transistor.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkConnected' + #, spice = spiceDir+'CCPairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CrossCoupledPairBulkUnconnected' + #, spice = spiceDir+'CCPairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CCP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CCP_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.CCP_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.CCP_interdigitated.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkConnected' + #, spice = spiceDir+'CommonSourcePairBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'CommonSourcePairBulkUnconnected' + #, spice = spiceDir+'CommonSourcePairBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'G', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.CSP_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.CSP_symmetrical.py' ) + , ('Interdigitated' , 'coriolis.oroshi.CSP_interdigitated.py' ) + , ('WIP CSP' , 'coriolis.oroshi.wip_csp.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkConnected' + #, spice = spiceDir+'CurrMirBulkConnected.spi' + , connectors = ( 'D1', 'D2', 'S' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'SimpleCurrentMirrorBulkUnconnected' + #, spice = spiceDir+'CurrMirBulkUnconnected.spi' + , connectors = ( 'D1', 'D2', 'S', 'B' ) + , layouts = ( ('Horizontal M2' , 'coriolis.oroshi.SCM_horizontalM2.py' ) + , ('Symmetrical' , 'coriolis.oroshi.SCM_symmetrical.py' ) + , ('Common centroid', 'coriolis.oroshi.SCM_2DCommonCentroid.py') + , ('Interdigitated' , 'coriolis.oroshi.SCM_interdigitated.py' ) + ) + ) + addDevice( name = 'MultiCapacitor' + #, spice = spiceDir+'MIM_OneCapacitor.spi' + , connectors = ( 'T1', 'B1' ) + , layouts = ( ('Matrix', 'coriolis.oroshi.multicapacitor.py' ), + ) + ) + #addDevice( name = 'Resistor' + # #, spice = spiceDir+'MIM_OneCapacitor.spi' + # , connectors = ( 'PIN1', 'PIN2' ) + # , layouts = ( ('Snake', 'coriolis.oroshi.resistorsnake.py' ), + # ) + # ) + + +def _setup_techno ( coriolisTechDir ): + ShellEnv.RDS_TECHNO_NAME = (coriolisTechDir / 'sky130_vsc' / 'sky130_vsc.rds').as_posix() + ShellEnv.GRAAL_TECHNO_NAME = (coriolisTechDir / 'sky130_vsc' / 'symbolic.graal' ).as_posix() + ShellEnv.DREAL_TECHNO_NAME = (coriolisTechDir / 'sky130_vsc' / 'symbolic.dreal' ).as_posix() + + db = DataBase.getDB() + CRL.System.get() + + tech = Technology.create(db, 'Sky130_vsc') + + DbU.setPrecision( 2 ) + DbU.setPhysicalsPerGrid( 0.0025, DbU.UnitPowerMicro ) + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + cfg.gdsDriver.metricDbu = 1e-09 + cfg.gdsDriver.dbuPerUu = 0.001 + DbU.setGridsPerLambda ( 30 ) + DbU.setSymbolicSnapGridStep( DbU.fromGrid( 1.0 )) + DbU.setPolygonStep ( DbU.fromGrid( 1.0 )) + DbU.setStringMode ( DbU.StringModePhysical, DbU.UnitPowerMicro ) + + createBL( tech, 'nwm' , BasicLayer.Material.nWell , size=u(0.84), spacing=u(1.27), gds2Layer= 64, gds2DataType= 20 ) + createBL( tech, 'nsdm' , BasicLayer.Material.nImplant, size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 93, gds2DataType= 44 ) + createBL( tech, 'psdm' , BasicLayer.Material.pImplant, size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 94, gds2DataType= 20 ) + createBL( tech, 'hvi' , BasicLayer.Material.other , gds2Layer= 75, gds2DataType= 20 ) + createBL( tech, 'difftap.pin' , BasicLayer.Material.other , gds2Layer= 65, gds2DataType= 16 ) + createBL( tech, 'difftap.block', BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 10 ) + createBL( tech, 'poly.pin' , BasicLayer.Material.other , gds2Layer= 66, gds2DataType= 16 ) + createBL( tech, 'poly.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 20 ) + createBL( tech, 'li.pin' , BasicLayer.Material.other , gds2Layer= 67, gds2DataType= 16 ) + createBL( tech, 'li.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 40 ) + createBL( tech, 'm1.pin' , BasicLayer.Material.other , gds2Layer= 68, gds2DataType= 16 ) + createBL( tech, 'm1.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 60 ) + createBL( tech, 'm2.pin' , BasicLayer.Material.other , gds2Layer= 69, gds2DataType= 16 ) + createBL( tech, 'm2.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 80 ) + createBL( tech, 'm3.pin' , BasicLayer.Material.other , gds2Layer= 70, gds2DataType= 16 ) + createBL( tech, 'm3.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=100 ) + createBL( tech, 'm4.pin' , BasicLayer.Material.other , gds2Layer= 71, gds2DataType= 16 ) + createBL( tech, 'm4.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=120 ) + createBL( tech, 'm5.pin' , BasicLayer.Material.other , gds2Layer= 72, gds2DataType= 16 ) + createBL( tech, 'm5.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=140 ) + createBL( tech, 'licon.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 30 ) + createBL( tech, 'mcon.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 50 ) + createBL( tech, 'via.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 70 ) + createBL( tech, 'via2.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType= 90 ) + createBL( tech, 'via3.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=110 ) + createBL( tech, 'via4.block' , BasicLayer.Material.blockage, gds2Layer=100, gds2DataType=130 ) + createBL( tech, 'difftap' , BasicLayer.Material.active , size=u(0.15), spacing=u(0.27), gds2Layer= 65, gds2DataType= 20 ) + createBL( tech, 'poly' , BasicLayer.Material.poly , size=u(0.15), spacing=u(0.21), gds2Layer= 66, gds2DataType= 20 ) + createBL( tech, 'licon' , BasicLayer.Material.cut , size=u(0.17), spacing=u(0.17), gds2Layer= 66, gds2DataType= 44 ) + createBL( tech, 'li' , BasicLayer.Material.metal , size=u(0.17), spacing=u(0.17), gds2Layer= 67, gds2DataType= 20 ) + createBL( tech, 'mcon' , BasicLayer.Material.cut , size=u(0.17), spacing=u(0.19), gds2Layer= 67, gds2DataType= 44 ) + createBL( tech, 'm1' , BasicLayer.Material.metal , size=u(0.14), spacing=u(0.14), area=0.083, gds2Layer= 68, gds2DataType= 20 ) + createBL( tech, 'via' , BasicLayer.Material.cut , size=u(0.15), spacing=u(0.17), gds2Layer= 68, gds2DataType= 44 ) + createBL( tech, 'm2' , BasicLayer.Material.metal , size=u(0.14), spacing=u(0.14), area=0.0676, gds2Layer= 69, gds2DataType= 20 ) + createBL( tech, 'capm' , BasicLayer.Material.metal ) + createBL( tech, 'via2' , BasicLayer.Material.cut , size=u(0.2 ), spacing=u(0.2 ), gds2Layer= 69, gds2DataType= 44 ) + createBL( tech, 'm3' , BasicLayer.Material.metal , size=u(0.3 ), spacing=u(0.3 ), area=0.24, gds2Layer= 70, gds2DataType= 20 ) + createBL( tech, 'via3' , BasicLayer.Material.cut , size=u(0.2 ), spacing=u(0.2 ), gds2Layer= 70, gds2DataType= 44 ) + createBL( tech, 'm4' , BasicLayer.Material.metal , size=u(0.3 ), spacing=u(0.3 ), area=0.24, gds2Layer= 71, gds2DataType= 20 ) + createBL( tech, 'via4' , BasicLayer.Material.cut , size=u(0.8 ), spacing=u(0.8 ), gds2Layer= 71, gds2DataType= 44 ) + createBL( tech, 'm5' , BasicLayer.Material.metal , size=u(1.6 ), spacing=u(1.6 ), area=4.0, gds2Layer= 72, gds2DataType= 20 ) + createBL( tech, 'hvtp' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer= 78, gds2DataType= 44 ) + createBL( tech, 'lvtn' , BasicLayer.Material.other , size=u(0.38), spacing=u(0.38), area=0.265, gds2Layer=125, gds2DataType= 44 ) + createBL( tech, 'areaid_sc' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 4 ) + createBL( tech, 'pad' , BasicLayer.Material.cut , size=u(40.0), spacing=u(1.27), gds2Layer= 76, gds2DataType= 20 ) + createBL( tech, 'areaid_diode' , BasicLayer.Material.other , gds2Layer= 81, gds2DataType= 23 ) + createBL( tech, 'pnp' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 44 ) + createBL( tech, 'diffres' , BasicLayer.Material.other , gds2Layer= 65, gds2DataType= 13 ) + createBL( tech, 'npn' , BasicLayer.Material.other , gds2Layer= 82, gds2DataType= 20 ) + createBL( tech, 'polyres' , BasicLayer.Material.other , gds2Layer= 66, gds2DataType= 13 ) + createBL( tech, 'prBoundary' , BasicLayer.Material.other , gds2Layer=235, gds2DataType= 4 ) + + tech.addLayerAlias( 'm1', 'met1' ) + tech.addLayerAlias( 'm2', 'met2' ) + tech.addLayerAlias( 'm3', 'met3' ) + tech.addLayerAlias( 'm4', 'met4' ) + tech.addLayerAlias( 'm5', 'met5' ) + + # ViaLayers + createVia( tech, 'li_mcon_m1' , 'li' , 'mcon', 'm1', u(0.17) ) + createVia( tech, 'm1_via_m2' , 'm1' , 'via' , 'm2', u(0.15) ) + createVia( tech, 'm2_via2_m3' , 'm2' , 'via2', 'm3', u(0.2 ) ) + createVia( tech, 'capm_via2_m3', 'capm', 'via2', 'm3', u(0.2 ) ) + createVia( tech, 'm3_via3_m4' , 'm3' , 'via3', 'm4', u(0.2 ) ) + createVia( tech, 'm4_via4_m5' , 'm4' , 'via4', 'm5', u(0.8 ) ) + + # Blockages + tech.getLayer('difftap').setBlockageLayer( tech.getLayer('difftap.block') ) + tech.getLayer('poly') .setBlockageLayer( tech.getLayer('poly.block') ) + tech.getLayer('li') .setBlockageLayer( tech.getLayer('li.block') ) + tech.getLayer('m1') .setBlockageLayer( tech.getLayer('m1.block') ) + tech.getLayer('m2') .setBlockageLayer( tech.getLayer('m2.block') ) + tech.getLayer('m3') .setBlockageLayer( tech.getLayer('m3.block') ) + tech.getLayer('m4') .setBlockageLayer( tech.getLayer('m4.block') ) + tech.getLayer('m5') .setBlockageLayer( tech.getLayer('m5.block') ) + tech.getLayer('licon') .setBlockageLayer( tech.getLayer('licon.block') ) + tech.getLayer('mcon') .setBlockageLayer( tech.getLayer('mcon.block') ) + tech.getLayer('via') .setBlockageLayer( tech.getLayer('via.block') ) + tech.getLayer('via2') .setBlockageLayer( tech.getLayer('via2.block') ) + tech.getLayer('via3') .setBlockageLayer( tech.getLayer('via3.block') ) + tech.getLayer('via4') .setBlockageLayer( tech.getLayer('via4.block') ) + + # Coriolis internal layers + createBL( tech, 'text.cell' , BasicLayer.Material.other, ) + createBL( tech, 'text.instance', BasicLayer.Material.other, ) + createBL( tech, 'SPL1' , BasicLayer.Material.other, ) + createBL( tech, 'AutoLayer' , BasicLayer.Material.other, ) + createBL( tech, 'gmetalh' , BasicLayer.Material.metal, ) + createBL( tech, 'gcontact' , BasicLayer.Material.cut, ) + createBL( tech, 'gmetalv' , BasicLayer.Material.metal, ) + + # Resistors + # ResistorLayer.create(tech, 'poly_res', 'poly', 'polyres') + # ResistorLayer.create(tech, 'active_res', 'difftap', 'diffres') + + # Transistors + # GateLayer.create(tech, 'hvmosgate' , 'difftap', 'poly', 'hvi') + # GateLayer.create(tech, 'mosgate' , 'difftap', 'poly') + # GateLayer.create(tech, 'mosgate_sc', 'difftap', 'poly') + # TransistorLayer.create(tech, 'nfet_01v8' , 'mosgate' , 'nsdm') + # TransistorLayer.create(tech, 'nfet_01v8_lvt' , 'mosgate' , ('nsdm', 'lvtn')) + # TransistorLayer.create(tech, 'nfet_01v8_sc' , 'mosgate_sc', 'nsdm') + # TransistorLayer.create(tech, 'nfet_g5v0d10v5', 'hvmosgate' , 'nsdm') + # TransistorLayer.create(tech, 'pfet_01v8' , 'mosgate' , 'psdm', 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_hvt' , 'mosgate' , ('psdm', 'hvtp'), 'nwm') + # TransistorLayer.create(tech, 'pfet_01v8_lvt' , 'mosgate' , ('psdm', 'lvtn'), 'nwm') + # TransistorLayer.create(tech, 'pfet_g5v0d10v5', 'hvmosgate' , 'psdm', 'nwm') + + # Bipolars + # Not implemented: Bipolar 'pnp_05v5_w0u68l0u68' + # Not implemented: Bipolar 'npn_05v5_w1u00l2u00' + # Not implemented: Bipolar 'pnp_05v5_w3u40l3u40' + # Not implemented: Bipolar 'npn_05v5_w1u00l1u00' + + +def _setup_display (): + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [black] + + threshold = 0.2 if Viewer.Graphics.isHighDpi() else 0.1 + + style = Viewer.DisplayStyle( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - black background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + # Viewer. + style.addDrawingStyle( group='Viewer', name='fallback' , color=toRGB('Gray238' ), border=1, pattern='55AA55AA55AA55AA' ) + style.addDrawingStyle( group='Viewer', name='background' , color=toRGB('Gray50' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='rubber' , color=toRGB('192,0,192' ), border=4, threshold=0.02 ) + style.addDrawingStyle( group='Viewer', name='phantom' , color=toRGB('Seashell4' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries' , color=toRGB('wheat1' ), border=2, pattern='0000000000000000', threshold=0 ) + style.addDrawingStyle( group='Viewer', name='marker' , color=toRGB('80,250,80' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionDraw' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='selectionFill' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='grid' , color=toRGB('White' ), border=1, threshold=2.0 ) + style.addDrawingStyle( group='Viewer', name='spot' , color=toRGB('White' ), border=2, threshold=6.0 ) + style.addDrawingStyle( group='Viewer', name='ghost' , color=toRGB('White' ), border=1 ) + style.addDrawingStyle( group='Viewer', name='text.ruler' , color=toRGB('White' ), border=1, threshold= 0.0 ) + style.addDrawingStyle( group='Viewer', name='text.instance' , color=toRGB('White' ), border=1, threshold=400.0 ) + style.addDrawingStyle( group='Viewer', name='text.reference', color=toRGB('White' ), border=1, threshold=200.0 ) + style.addDrawingStyle( group='Viewer', name='undef' , color=toRGB('Violet' ), border=0, pattern='2244118822441188' ) + + # Active Layers. + style.addDrawingStyle(group='Active Layers', name='nwm' , color=toRGB('Tan' ), pattern=toHexa('urgo.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='nsdm' , color=toRGB('LawnGreen'), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='psdm' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='hvtp' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='lvtn' , color=toRGB('Yellow' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='difftap' , color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='difftap.pin', color=toRGB('White' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Active Layers', name='poly.pin' , color=toRGB('Red' ), pattern=toHexa('antihash0.8'), border=2, threshold=threshold) + + # Routing Layers. + style.addDrawingStyle(group='Routing Layers', name='li' , color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='li.pin', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m1' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m1.pin', color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m2' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m2.pin', color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m3' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m3.pin', color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m4' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m4.pin', color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m5' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=1, threshold=threshold) + style.addDrawingStyle(group='Routing Layers', name='m5.pin', color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=2, threshold=threshold) + + # Cuts (VIA holes). + style.addDrawingStyle(group='Cuts (VIA holes', name='licon', color=toRGB('0,150,150'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='mcon' , color=toRGB('Aqua' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via' , color=toRGB('LightPink'), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via2' , color=toRGB('Green' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via3' , color=toRGB('Yellow' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='via4' , color=toRGB('Violet' ), threshold=threshold) + style.addDrawingStyle(group='Cuts (VIA holes', name='pad' , color=toRGB('Red' ), threshold=threshold) + + # Blockages. + style.addDrawingStyle(group='Blockages', name='difftap.block', color=toRGB('Blue' ), pattern=toHexa('slash.8' ), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='poly.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='li.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m1.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m2.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m3.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m4.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='m5.block' , color=toRGB('Blue' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='licon.block' , color=toRGB('Aqua' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='mcon.block' , color=toRGB('LightPink'), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via.block' , color=toRGB('Green' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via2.block' , color=toRGB('Yellow' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via3.block' , color=toRGB('Violet' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + style.addDrawingStyle(group='Blockages', name='via4.block' , color=toRGB('Red' ), pattern=toHexa('poids4.8'), border=4, threshold=threshold) + + # Knick & Kite. + style.addDrawingStyle( group='Knik & Kite', name='SPL1' , color=toRGB('Red' ) ) + style.addDrawingStyle( group='Knik & Kite', name='AutoLayer' , color=toRGB('Magenta' ) ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalh' , color=toRGB('128,255,200'), pattern=toHexa('antislash2.32' ), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gmetalv' , color=toRGB('200,200,255'), pattern=toHexa('light_antihash1.8'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='gcontact' , color=toRGB('255,255,190'), border=1 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::Edge' , color=toRGB('255,255,190'), pattern='0000000000000000' , border=4, threshold=0.02 ) + style.addDrawingStyle( group='Knik & Kite', name='Anabatic::GCell', color=toRGB('255,255,190'), pattern='0000000000000000' , border=2, threshold=threshold ) + + Viewer.Graphics.addStyle( style ) + + # ---------------------------------------------------------------------- + # Style: Alliance.Classic [white]. + + style = Viewer.DisplayStyle( 'Alliance.Classic [white]' ) + style.inheritFrom( 'Alliance.Classic [black]' ) + style.setDescription( 'Alliance Classic Look - white background' ) + style.setDarkening ( Viewer.DisplayStyle.HSVr(1.0, 3.0, 2.5) ) + + style.addDrawingStyle( group='Viewer', name='background', color=toRGB('White'), border=1 ) + style.addDrawingStyle( group='Viewer', name='foreground', color=toRGB('Black'), border=1 ) + style.addDrawingStyle( group='Viewer', name='boundaries', color=toRGB('Black'), border=1, pattern='0000000000000000' ) + Viewer.Graphics.addStyle( style ) + + Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + + +def setup ( coriolisTechDir ): + _setup_techno( coriolisTechDir ) + _setup_display() + try: + from .techno_symb import setup as setupSymbolic + except: + pass + else: + setupSymbolic() + _loadDtr() + _loadDevices() + diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/techno_symb.py b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/techno_symb.py new file mode 100644 index 000000000..3196a87e3 --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/techno_symb.py @@ -0,0 +1,284 @@ + +from coriolis.helpers import l, u, n +from coriolis.Hurricane import DataBase, Technology, Layer, BasicLayer, DiffusionLayer, \ + TransistorLayer, RegularLayer, ContactLayer, ViaLayer + +__all__ = [ 'setup' ] + + +def setup (): + tech = DataBase.getDB().getTechnology() + tech.addLayerAlias( 'nwm' , 'nWell' ) + tech.addLayerAlias( 'difftap' , 'active' ) + #tech.addLayerAlias( 'poly' , 'poly' ) + tech.addLayerAlias( 'psdm' , 'pImplant' ) + tech.addLayerAlias( 'nsdm' , 'nImplant' ) + tech.addLayerAlias( 'licon' , 'cut0' ) + tech.addLayerAlias( 'li' , 'metal1' ) + tech.addLayerAlias( 'mcon' , 'cut1' ) + tech.addLayerAlias( 'm1' , 'metal2' ) + tech.addLayerAlias( 'via' , 'cut2' ) + tech.addLayerAlias( 'm2' , 'metal3' ) + tech.addLayerAlias( 'via2' , 'cut3' ) + tech.addLayerAlias( 'm3' , 'metal4' ) + tech.addLayerAlias( 'via3' , 'cut4' ) + tech.addLayerAlias( 'm4' , 'metla5' ) + tech.addLayerAlias( 'via4' , 'cut5' ) + tech.addLayerAlias( 'm5' , 'metal6' ) + tech.addLayerAlias( 'li.block', 'blockage1' ) + tech.addLayerAlias( 'm1.block', 'blockage2' ) + tech.addLayerAlias( 'm2.block', 'blockage3' ) + tech.addLayerAlias( 'm3.block', 'blockage4' ) + tech.addLayerAlias( 'm4.block', 'blockage5' ) + tech.addLayerAlias( 'm5.block', 'blockage6' ) + tech.addLayerAlias( 'capm' , 'metcap' ) + tech.addLayerAlias( 'capm' , 'metcapdum' ) + tech.addLayerAlias( 'm3' , 'metbot' ) + + nWell = tech.getBasicLayer( 'nwm' ) + active = tech.getBasicLayer( 'difftap' ) + poly = tech.getBasicLayer( 'poly' ) + pImplant = tech.getBasicLayer( 'psdm' ) + nImplant = tech.getBasicLayer( 'nsdm' ) + cut0 = tech.getBasicLayer( 'licon' ) + metal1 = tech.getBasicLayer( 'li' ) + cut1 = tech.getBasicLayer( 'mcon' ) + metal2 = tech.getBasicLayer( 'm1' ) + cut2 = tech.getBasicLayer( 'via' ) + metal3 = tech.getBasicLayer( 'm2' ) + cut3 = tech.getBasicLayer( 'via2' ) + metal4 = tech.getBasicLayer( 'm3' ) + cut4 = tech.getBasicLayer( 'via3' ) + metal5 = tech.getBasicLayer( 'm4' ) + cut5 = tech.getBasicLayer( 'via4' ) + metal6 = tech.getBasicLayer( 'm5' ) + blockage1 = tech.getBasicLayer( 'blockage1' ) + blockage2 = tech.getBasicLayer( 'blockage1' ) + blockage3 = tech.getBasicLayer( 'blockage2' ) + blockage4 = tech.getBasicLayer( 'blockage3' ) + blockage5 = tech.getBasicLayer( 'blockage4' ) + blockage6 = tech.getBasicLayer( 'blockage5' ) + + # Composite/Symbolic layers. + NWELL = RegularLayer .create( tech, 'NWELL' , nWell ) + #PWELL = RegularLayer .create( tech, 'PWELL' , pWell ) + NTIE = DiffusionLayer .create( tech, 'NTIE' , nImplant , active, nWell) + PTIE = DiffusionLayer .create( tech, 'PTIE' , pImplant , active, None) + NDIF = DiffusionLayer .create( tech, 'NDIF' , nImplant , active, None ) + PDIF = DiffusionLayer .create( tech, 'PDIF' , pImplant , active, None ) + GATE = DiffusionLayer .create( tech, 'GATE' , poly , active, None ) + NTRANS = TransistorLayer.create( tech, 'NTRANS' , nImplant , active, poly, None ) + PTRANS = TransistorLayer.create( tech, 'PTRANS' , pImplant , active, poly, nWell ) + POLY = RegularLayer .create( tech, 'POLY' , poly ) + METAL1 = RegularLayer .create( tech, 'METAL1' , metal1 ) + METAL2 = RegularLayer .create( tech, 'METAL2' , metal2 ) + METAL3 = RegularLayer .create( tech, 'METAL3' , metal3 ) + METAL4 = RegularLayer .create( tech, 'METAL4' , metal4 ) + METAL5 = RegularLayer .create( tech, 'METAL5' , metal5 ) + METAL6 = RegularLayer .create( tech, 'METAL6' , metal6 ) + CONT_BODY_N = ContactLayer .create( tech, 'CONT_BODY_N', nImplant , active, cut0, metal1, None ) + CONT_BODY_P = ContactLayer .create( tech, 'CONT_BODY_P', pImplant , active, cut0, metal1, None ) + CONT_DIF_N = ContactLayer .create( tech, 'CONT_DIF_N' , nImplant , active, cut0, metal1, None ) + CONT_DIF_P = ContactLayer .create( tech, 'CONT_DIF_P' , pImplant , active, cut0, metal1, None ) + CONT_POLY = ViaLayer .create( tech, 'CONT_POLY' , poly, cut0, metal1 ) + + # VIAs for symbolic technologies. + VIA12 = ViaLayer .create( tech, 'VIA12' , metal1, cut1, metal2 ) + VIA23 = ViaLayer .create( tech, 'VIA23' , metal2, cut2, metal3 ) + #VIA23cap = ViaLayer .create( tech, 'VIA23cap' , metcap, cut2, metal3 ) + VIA34 = ViaLayer .create( tech, 'VIA34' , metal3, cut3, metal4 ) + VIA45 = ViaLayer .create( tech, 'VIA45' , metal4, cut4, metal5 ) + VIA56 = ViaLayer .create( tech, 'VIA56' , metal5, cut5, metal6 ) + BLOCKAGE1 = RegularLayer.create( tech, 'BLOCKAGE1' , blockage1 ) + BLOCKAGE2 = RegularLayer.create( tech, 'BLOCKAGE2' , blockage2 ) + BLOCKAGE3 = RegularLayer.create( tech, 'BLOCKAGE3' , blockage3 ) + BLOCKAGE4 = RegularLayer.create( tech, 'BLOCKAGE4' , blockage4 ) + BLOCKAGE5 = RegularLayer.create( tech, 'BLOCKAGE5' , blockage5 ) + BLOCKAGE6 = RegularLayer.create( tech, 'BLOCKAGE6' , blockage6 ) + + tech.setSymbolicLayer( CONT_BODY_N.getName() ) + tech.setSymbolicLayer( CONT_BODY_P.getName() ) + tech.setSymbolicLayer( CONT_DIF_N .getName() ) + tech.setSymbolicLayer( CONT_DIF_P .getName() ) + tech.setSymbolicLayer( CONT_POLY .getName() ) + tech.setSymbolicLayer( POLY .getName() ) + tech.setSymbolicLayer( METAL1 .getName() ) + tech.setSymbolicLayer( METAL2 .getName() ) + tech.setSymbolicLayer( METAL3 .getName() ) + tech.setSymbolicLayer( METAL4 .getName() ) + tech.setSymbolicLayer( METAL5 .getName() ) + tech.setSymbolicLayer( METAL6 .getName() ) + tech.setSymbolicLayer( BLOCKAGE1 .getName() ) + tech.setSymbolicLayer( BLOCKAGE2 .getName() ) + tech.setSymbolicLayer( BLOCKAGE3 .getName() ) + tech.setSymbolicLayer( BLOCKAGE4 .getName() ) + tech.setSymbolicLayer( BLOCKAGE5 .getName() ) + tech.setSymbolicLayer( BLOCKAGE6 .getName() ) + tech.setSymbolicLayer( VIA12 .getName() ) + tech.setSymbolicLayer( VIA23 .getName() ) + tech.setSymbolicLayer( VIA34 .getName() ) + tech.setSymbolicLayer( VIA45 .getName() ) + tech.setSymbolicLayer( VIA56 .getName() ) + + NWELL.setExtentionCap( nWell, l(0.0) ) + #PWELL.setExtentionCap( pWell, l(0.0) ) + + NTIE.setMinimalSize ( l(3.0) ) + NTIE.setExtentionCap ( nWell , l(1.5) ) + NTIE.setExtentionWidth( nWell , l(0.5) ) + NTIE.setExtentionCap ( nImplant, l(1.0) ) + NTIE.setExtentionWidth( nImplant, l(0.5) ) + NTIE.setExtentionCap ( active , l(0.5) ) + NTIE.setExtentionWidth( active , l(0.0) ) + + PTIE.setMinimalSize ( l(3.0) ) + PTIE.setExtentionCap ( nWell , l(1.5) ) + PTIE.setExtentionWidth( nWell , l(0.5) ) + PTIE.setExtentionCap ( nImplant, l(1.0) ) + PTIE.setExtentionWidth( nImplant, l(0.5) ) + PTIE.setExtentionCap ( active , l(0.5) ) + PTIE.setExtentionWidth( active , l(0.0) ) + + NDIF.setMinimalSize ( l(3.0) ) + NDIF.setExtentionCap ( nImplant, l(1.0) ) + NDIF.setExtentionWidth( nImplant, l(0.5) ) + NDIF.setExtentionCap ( active , l(0.5) ) + NDIF.setExtentionWidth( active , l(0.0) ) + + PDIF.setMinimalSize ( l(3.0) ) + PDIF.setExtentionCap ( pImplant, l(1.0) ) + PDIF.setExtentionWidth( pImplant, l(0.5) ) + PDIF.setExtentionCap ( active , l(0.5) ) + PDIF.setExtentionWidth( active , l(0.0) ) + + GATE.setMinimalSize ( l(1.0) ) + GATE.setExtentionCap ( poly , l(1.5) ) + + NTRANS.setMinimalSize ( l( 1.0) ) + NTRANS.setExtentionCap ( nImplant, l(-1.0) ) + NTRANS.setExtentionWidth( nImplant, l( 2.5) ) + NTRANS.setExtentionCap ( active , l(-1.5) ) + NTRANS.setExtentionWidth( active , l( 2.0) ) + + PTRANS.setMinimalSize ( l( 1.0) ) + PTRANS.setExtentionCap ( nWell , l(-1.0) ) + PTRANS.setExtentionWidth( nWell , l( 4.5) ) + PTRANS.setExtentionCap ( pImplant, l(-1.0) ) + PTRANS.setExtentionWidth( pImplant, l( 4.0) ) + PTRANS.setExtentionCap ( active , l(-1.5) ) + PTRANS.setExtentionWidth( active , l( 3.0) ) + + POLY .setMinimalSize ( l(1.0) ) + POLY .setExtentionCap ( poly , l(0.5) ) + #POLY2.setMinimalSize ( l(1.0) ) + #POLY2.setExtentionCap ( poly , l(0.5) ) + + METAL1 .setMinimalSize ( l(1.0) ) + METAL1 .setExtentionCap ( metal1 , l(0.5) ) + METAL2 .setMinimalSize ( l(1.0) ) + METAL2 .setExtentionCap ( metal2 , l(1.0) ) + METAL3 .setMinimalSize ( l(1.0) ) + METAL3 .setExtentionCap ( metal3 , l(1.0) ) + METAL4 .setMinimalSize ( l(1.0) ) + METAL4 .setExtentionCap ( metal4 , l(1.0) ) + METAL4 .setMinimalSpacing( l(3.0) ) + METAL5 .setMinimalSize ( l(2.0) ) + METAL5 .setExtentionCap ( metal5 , l(1.0) ) + #METAL6 .setMinimalSize ( l(2.0) ) + #METAL6 .setExtentionCap ( metal6 , l(1.0) ) + #METAL7 .setMinimalSize ( l(2.0) ) + #METAL7 .setExtentionCap ( metal7 , l(1.0) ) + #METAL8 .setMinimalSize ( l(2.0) ) + #METAL8 .setExtentionCap ( metal8 , l(1.0) ) + #METAL9 .setMinimalSize ( l(2.0) ) + #METAL9 .setExtentionCap ( metal9 , l(1.0) ) + #METAL10.setMinimalSize ( l(2.0) ) + #METAL10.setExtentionCap ( metal10 , l(1.0) ) + + # Contacts (i.e. Active <--> Metal) (symbolic). + CONT_BODY_N.setMinimalSize( l( 1.0) ) + CONT_BODY_N.setEnclosure ( nWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( nImplant, l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( active , l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_N.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_BODY_P.setMinimalSize( l( 1.0) ) + #CONT_BODY_P.setEnclosure ( pWell , l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( pImplant, l( 1.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( active , l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_BODY_P.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_N.setMinimalSize( l( 1.0) ) + CONT_DIF_N.setEnclosure ( nImplant, l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_N.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_DIF_P.setMinimalSize( l( 1.0) ) + CONT_DIF_P.setEnclosure ( pImplant, l( 1.0), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( active , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_DIF_P.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + CONT_POLY.setMinimalSize( l( 1.0) ) + CONT_POLY.setEnclosure ( poly , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + CONT_POLY.setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + + # VIAs (i.e. Metal <--> Metal) (symbolic). + VIA12 .setMinimalSize ( l( 1.0) ) + VIA12 .setEnclosure ( metal1 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setEnclosure ( metal2 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA12 .setMinimalSpacing( l( 4.0) ) + VIA23 .setMinimalSize ( l( 1.0) ) + VIA23 .setEnclosure ( metal2 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setEnclosure ( metal3 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA23 .setMinimalSpacing( l( 4.0) ) + VIA34 .setMinimalSize ( l( 1.0) ) + VIA34 .setEnclosure ( metal3 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setEnclosure ( metal4 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA34 .setMinimalSpacing( l( 4.0) ) + VIA45 .setMinimalSize ( l( 1.0) ) + VIA45 .setEnclosure ( metal4 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + VIA45 .setMinimalSpacing( l( 4.0) ) + #VIA56 .setMinimalSize ( l( 1.0) ) + #VIA56 .setEnclosure ( metal5 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA56 .setMinimalSpacing( l( 4.0) ) + #VIA67 .setMinimalSize ( l( 1.0) ) + #VIA67 .setEnclosure ( metal6 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA67 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA78 .setMinimalSize ( l( 1.0) ) + #VIA78 .setEnclosure ( metal7 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA78 .setMinimalSpacing( l( 4.0) ) + #VIA89 .setMinimalSize ( l( 1.0) ) + #VIA89 .setEnclosure ( metal8 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA89 .setMinimalSpacing( l( 4.0) ) + #VIA910.setMinimalSize ( l( 1.0) ) + #VIA910.setEnclosure ( metal9 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setEnclosure ( metal10 , l( 0.5), Layer.EnclosureH|Layer.EnclosureV ) + #VIA910.setMinimalSpacing( l( 4.0) ) + + # Blockages (symbolic). + BLOCKAGE1 .setMinimalSize ( l( 1.0) ) + BLOCKAGE1 .setExtentionCap( blockage1 , l( 0.5) ) + BLOCKAGE2 .setMinimalSize ( l( 2.0) ) + BLOCKAGE2 .setExtentionCap( blockage2 , l( 0.5) ) + BLOCKAGE3 .setMinimalSize ( l( 2.0) ) + BLOCKAGE3 .setExtentionCap( blockage3 , l( 0.5) ) + BLOCKAGE4 .setMinimalSize ( l( 2.0) ) + BLOCKAGE4 .setExtentionCap( blockage4 , l( 0.5) ) + BLOCKAGE5 .setMinimalSize ( l( 2.0) ) + BLOCKAGE5 .setExtentionCap( blockage5 , l( 1.0) ) + #BLOCKAGE6 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE6 .setExtentionCap( blockage6 , l( 1.0) ) + #BLOCKAGE7 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE7 .setExtentionCap( blockage7 , l( 1.0) ) + #BLOCKAGE8 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE8 .setExtentionCap( blockage8 , l( 1.0) ) + #BLOCKAGE9 .setMinimalSize ( l( 2.0) ) + #BLOCKAGE9 .setExtentionCap( blockage9 , l( 1.0) ) + #BLOCKAGE10.setMinimalSize ( l( 2.0) ) + #BLOCKAGE10.setExtentionCap( blockage10, l( 1.0) ) diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/vsclib.lib b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/vsclib.lib new file mode 100644 index 000000000..7d37ce4ad --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/vsclib.lib @@ -0,0 +1,22638 @@ +/************************************************************************/ +/* */ +/* Avertec Release v3.4p5 (64 bits on Linux 4.4.0-22621-Microsoft) */ +/* argv: /home/nshimizu/lip6/alliance-check-toolkit/bin/buildLib.tcl /home/nshimizu/lip6/alliance-check-toolkit/cells/vsclib/techno/C4M.Sky130_tt_model_hitas.spice spice vsclib */ +/* */ +/* User: nshimizu */ +/* Generation date Mon Jun 24 17:15:39 2024 */ +/* */ +/* liberty data flow `vsclib.lib` */ +/* */ +/************************************************************************/ + + + +library (vsclib.lib) { + + technology (cmos) ; + date : "Mon Jun 24 17:15:39 2024" ; + delay_model : table_lookup ; + nom_voltage : 5.00 ; + nom_temperature : 70.0 ; + nom_process : 1.0 ; + slew_derate_from_library : 1.0 ; + default_fanout_load : 1000.0 ; + default_inout_pin_cap : 1000.0 ; + default_input_pin_cap : 1000.0 ; + default_output_pin_cap : 0.0 ; + voltage_unit : "1V" ; + time_unit : "1ps" ; + capacitive_load_unit (1,ff) ; + pulling_resistance_unit : "1ohm" ; + current_unit : "1mA" ; + leakage_power_unit : "1uW" ; + default_cell_leakage_power : 0.0 ; + input_threshold_pct_rise : 50.0 ; + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_rise : 50.0 ; + output_threshold_pct_fall : 50.0 ; + slew_lower_threshold_pct_fall : 20.0 ; + slew_upper_threshold_pct_fall : 80.0 ; + slew_lower_threshold_pct_rise : 20.0 ; + slew_upper_threshold_pct_rise : 80.0 ; + + lu_table_template (inslew_load_5x5__109) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.88, 1.75, 3.50, 7.00, 14.00"); + } + lu_table_template (inslew_load_5x5__108) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("19.65, 39.29, 78.58, 157.17, 314.33"); + } + lu_table_template (inslew_load_5x5__107) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.44, 0.87, 1.74, 3.48, 6.96"); + } + lu_table_template (inslew_load_5x5__106) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.20, 2.39, 4.79, 9.58, 19.15"); + } + lu_table_template (inslew_load_5x5__105) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.67, 1.34, 2.68, 5.35, 10.71"); + } + lu_table_template (inslew_load_5x5__104) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.90, 1.80, 3.60, 7.21, 14.42"); + } + lu_table_template (inslew_load_5x5__103) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.91, 1.83, 3.66, 7.32, 14.64"); + } + lu_table_template (inslew_load_5x5__102) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.94, 1.89, 3.77, 7.55, 15.10"); + } + lu_table_template (inslew_load_5x5__101) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.44, 0.89, 1.78, 3.56, 7.11"); + } + lu_table_template (inslew_load_5x5__100) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("4.87, 9.73, 19.46, 38.92, 77.84"); + } + lu_table_template (inslew_load_5x5__99) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.00, 1.99, 3.98, 7.96, 15.93"); + } + lu_table_template (inslew_load_5x5__98) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.56, 1.13, 2.26, 4.51, 9.03"); + } + lu_table_template (inslew_load_5x5__97) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.64, 1.29, 2.58, 5.16, 10.31"); + } + lu_table_template (inslew_load_5x5__96) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.87, 1.73, 3.47, 6.93, 13.86"); + } + lu_table_template (inslew_load_5x5__95) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.66, 1.32, 2.65, 5.29, 10.59"); + } + lu_table_template (inslew_load_5x5__94) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.57, 1.14, 2.28, 4.56, 9.13"); + } + lu_table_template (inslew_load_5x5__93) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.70, 1.40, 2.79, 5.58, 11.17"); + } + lu_table_template (inslew_load_5x5__92) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.60, 1.20, 2.40, 4.80, 9.59"); + } + lu_table_template (inslew_load_5x5__91) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.54, 1.07, 2.15, 4.30, 8.60"); + } + lu_table_template (inslew_load_5x5__90) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.83, 1.66, 3.32, 6.64, 13.28"); + } + lu_table_template (inslew_load_5x5__89) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.46, 2.92, 5.85, 11.69, 23.38"); + } + lu_table_template (inslew_load_5x5__88) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.90, 1.80, 3.61, 7.21, 14.43"); + } + lu_table_template (inslew_load_5x5__87) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.55, 3.10, 6.20, 12.39"); + } + lu_table_template (inslew_load_5x5__86) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.02, 2.04, 4.08, 8.16, 16.32"); + } + lu_table_template (inslew_load_5x5__85) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("3.02, 6.04, 12.08, 24.15, 48.30"); + } + lu_table_template (inslew_load_5x5__84) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.95, 1.90, 3.79, 7.58, 15.16"); + } + lu_table_template (inslew_load_5x5__83) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.83, 1.66, 3.32, 6.65, 13.30"); + } + lu_table_template (inslew_load_5x5__82) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.70, 1.41, 2.82, 5.64, 11.27"); + } + lu_table_template (inslew_load_5x5__81) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.68, 1.37, 2.73, 5.47, 10.94"); + } + lu_table_template (inslew_load_5x5__80) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.07, 2.15, 4.29, 8.58, 17.17"); + } + lu_table_template (inslew_load_5x5__79) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.10, 2.19, 4.38, 8.77, 17.53"); + } + lu_table_template (inslew_load_5x5__78) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.18, 4.37, 8.74, 17.47, 34.95"); + } + lu_table_template (inslew_load_5x5__77) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.35, 2.71, 5.42, 10.84, 21.67"); + } + lu_table_template (inslew_load_5x5__76) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.11, 2.23, 4.45, 8.91, 17.82"); + } + lu_table_template (inslew_load_5x5__75) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("3.81, 7.61, 15.22, 30.45, 60.90"); + } + lu_table_template (inslew_load_5x5__74) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.07, 4.14, 8.27, 16.55, 33.10"); + } + lu_table_template (inslew_load_5x5__73) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.46, 2.92, 5.84, 11.68, 23.35"); + } + lu_table_template (inslew_load_5x5__72) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.96, 1.93, 3.86, 7.72, 15.44"); + } + lu_table_template (inslew_load_5x5__71) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.05, 2.11, 4.22, 8.44, 16.88"); + } + lu_table_template (inslew_load_5x5__70) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.83, 1.67, 3.33, 6.67, 13.33"); + } + lu_table_template (inslew_load_5x5__69) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.71, 1.42, 2.84, 5.68, 11.36"); + } + lu_table_template (inslew_load_5x5__68) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.74, 5.47, 10.95, 21.90, 43.80"); + } + lu_table_template (inslew_load_5x5__67) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.92, 1.84, 3.68, 7.37, 14.73"); + } + lu_table_template (inslew_load_5x5__66) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.72, 1.43, 2.87, 5.74, 11.48"); + } + lu_table_template (inslew_load_5x5__65) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.90, 1.80, 3.61, 7.21, 14.43"); + } + lu_table_template (inslew_load_5x5__64) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.69, 5.38, 10.76, 21.52, 43.04"); + } + lu_table_template (inslew_load_5x5__63) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.29, 2.58, 5.15, 10.30, 20.60"); + } + lu_table_template (inslew_load_5x5__62) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.06, 2.12, 4.24, 8.48, 16.95"); + } + lu_table_template (inslew_load_5x5__61) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.95, 3.89, 7.78, 15.57, 31.13"); + } + lu_table_template (inslew_load_5x5__60) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.52, 3.03, 6.06, 12.12, 24.25"); + } + lu_table_template (inslew_load_5x5__59) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.13, 2.26, 4.51, 9.02, 18.05"); + } + lu_table_template (inslew_load_5x5__58) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.37, 2.75, 5.49, 10.99, 21.98"); + } + lu_table_template (inslew_load_5x5__57) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.98, 1.96, 3.92, 7.85, 15.69"); + } + lu_table_template (inslew_load_5x5__56) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.96, 1.91, 3.83, 7.66, 15.32"); + } + lu_table_template (inslew_load_5x5__55) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.62, 1.25, 2.50, 5.00, 10.00"); + } + lu_table_template (inslew_load_5x5__54) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.58, 1.16, 2.33, 4.65, 9.31"); + } + lu_table_template (inslew_load_5x5__53) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.75, 1.50, 2.99, 5.98, 11.96"); + } + lu_table_template (inslew_load_5x5__52) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.01, 4.02, 8.04, 16.09, 32.17"); + } + lu_table_template (inslew_load_5x5__51) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.08, 2.17, 4.33, 8.66, 17.32"); + } + lu_table_template (inslew_load_5x5__50) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.84, 1.68, 3.37, 6.74, 13.47"); + } + lu_table_template (inslew_load_5x5__49) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.51, 1.03, 2.05, 4.10, 8.20"); + } + lu_table_template (inslew_load_5x5__48) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.03, 4.06, 8.13, 16.25, 32.50"); + } + lu_table_template (inslew_load_5x5__47) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.11, 2.23, 4.45, 8.91, 17.82"); + } + lu_table_template (inslew_load_5x5__46) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.54, 3.08, 6.16, 12.32"); + } + lu_table_template (inslew_load_5x5__45) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.57, 1.15, 2.29, 4.59, 9.18"); + } + lu_table_template (inslew_load_5x5__44) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.73, 1.47, 2.94, 5.88, 11.76"); + } + lu_table_template (inslew_load_5x5__43) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.57, 1.14, 2.27, 4.54, 9.08"); + } + lu_table_template (inslew_load_5x5__42) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.21, 4.41, 8.82, 17.64, 35.29"); + } + lu_table_template (inslew_load_5x5__41) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.98, 1.96, 3.93, 7.85, 15.71"); + } + lu_table_template (inslew_load_5x5__40) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.49, 0.98, 1.95, 3.90, 7.81"); + } + lu_table_template (inslew_load_5x5__39) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.46, 0.93, 1.85, 3.70, 7.41"); + } + lu_table_template (inslew_load_5x5__38) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.56, 1.11, 2.23, 4.46, 8.91"); + } + lu_table_template (inslew_load_5x5__37) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.70, 1.40, 2.80, 5.59, 11.18"); + } + lu_table_template (inslew_load_5x5__36) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.79, 1.58, 3.15, 6.31, 12.62"); + } + lu_table_template (inslew_ckslew_5x5__0) { + variable_1 : constrained_pin_transition; + variable_2 : related_pin_transition; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + lu_table_template (inslew_5__0) { + variable_1 : input_net_transition; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + lu_table_template (inslew_load_5x5__35) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.53, 1.07, 2.13, 4.27, 8.53"); + } + lu_table_template (inslew_load_5x5__34) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.39, 4.77, 9.55, 19.09, 38.19"); + } + lu_table_template (inslew_load_5x5__33) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.27, 2.54, 5.07, 10.14, 20.29"); + } + lu_table_template (inslew_load_5x5__32) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.13, 2.27, 4.53, 9.07, 18.13"); + } + lu_table_template (inslew_load_5x5__31) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("3.38, 6.77, 13.53, 27.06, 54.13"); + } + lu_table_template (inslew_load_5x5__30) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.63, 1.26, 2.53, 5.06, 10.11"); + } + lu_table_template (inslew_load_5x5__29) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.52, 1.05, 2.09, 4.19, 8.37"); + } + lu_table_template (inslew_load_5x5__28) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.49, 0.99, 1.98, 3.96, 7.92"); + } + lu_table_template (inslew_load_5x5__27) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.07, 2.13, 4.26, 8.52, 17.04"); + } + lu_table_template (inslew_load_5x5__26) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.79, 1.59, 3.17, 6.35, 12.70"); + } + lu_table_template (inslew_load_5x5__25) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.65, 1.30, 2.59, 5.18, 10.36"); + } + lu_table_template (inslew_load_5x5__24) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.67, 3.34, 6.68, 13.35, 26.71"); + } + lu_table_template (inslew_load_5x5__23) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.06, 2.12, 4.24, 8.49, 16.97"); + } + lu_table_template (inslew_load_5x5__22) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.15, 2.29, 4.58, 9.17, 18.33"); + } + lu_table_template (inslew_load_5x5__21) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.96, 1.93, 3.86, 7.71, 15.42"); + } + lu_table_template (inslew_load_5x5__20) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.24, 2.49, 4.97, 9.94, 19.89"); + } + lu_table_template (inslew_load_5x5__19) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.01, 2.01, 4.02, 8.05, 16.09"); + } + lu_table_template (inslew_load_5x5__18) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.55, 3.10, 6.20, 12.40"); + } + lu_table_template (inslew_load_5x5__17) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.76, 1.52, 3.03, 6.07, 12.13"); + } + lu_table_template (inslew_load_5x5__16) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.75, 1.50, 2.99, 5.98, 11.97"); + } + lu_table_template (inslew_load_5x5__15) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.66, 1.32, 2.64, 5.28, 10.56"); + } + lu_table_template (inslew_load_5x5__14) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.67, 1.34, 2.68, 5.37, 10.74"); + } + lu_table_template (inslew_load_5x5__13) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.13, 2.25, 4.51, 9.02, 18.04"); + } + lu_table_template (inslew_load_5x5__12) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("3.07, 6.15, 12.30, 24.59, 49.19"); + } + lu_table_template (inslew_load_5x5__11) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.66, 3.31, 6.63, 13.25, 26.50"); + } + lu_table_template (inslew_load_5x5__10) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.15, 2.30, 4.60, 9.19, 18.39"); + } + lu_table_template (inslew_load_5x5__9) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.24, 2.49, 4.97, 9.95, 19.90"); + } + lu_table_template (inslew_load_5x5__8) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.66, 1.33, 2.66, 5.31, 10.62"); + } + lu_table_template (inslew_load_5x5__7) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.63, 1.26, 2.52, 5.04, 10.07"); + } + lu_table_template (inslew_load_5x5__6) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.98, 1.96, 3.91, 7.82, 15.65"); + } + lu_table_template (inslew_load_5x5__5) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.81, 1.61, 3.22, 6.44, 12.88"); + } + lu_table_template (inslew_load_5x5__4) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.60, 1.19, 2.39, 4.78, 9.55"); + } + lu_table_template (inslew_load_5x5__3) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.35, 4.71, 9.41, 18.82, 37.65"); + } + lu_table_template (inslew_load_5x5__2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.41, 2.83, 5.65, 11.30, 22.61"); + } + lu_table_template (inslew_load_5x5__1) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.70, 1.39, 2.78, 5.56, 11.13"); + } + lu_table_template (inslew_load_5x5__0) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.57, 1.14, 2.28, 4.56, 9.12"); + } + power_lut_template (energy_inslew_load_5x5__109) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.88, 1.75, 3.50, 7.00, 14.00"); + } + power_lut_template (energy_inslew_load_5x5__108) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("19.65, 39.29, 78.58, 157.17, 314.33"); + } + power_lut_template (energy_inslew_load_5x5__107) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.44, 0.87, 1.74, 3.48, 6.96"); + } + power_lut_template (energy_inslew_load_5x5__106) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.20, 2.39, 4.79, 9.58, 19.15"); + } + power_lut_template (energy_inslew_load_5x5__105) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.67, 1.34, 2.68, 5.35, 10.71"); + } + power_lut_template (energy_inslew_load_5x5__104) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.90, 1.80, 3.60, 7.21, 14.42"); + } + power_lut_template (energy_inslew_load_5x5__103) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.91, 1.83, 3.66, 7.32, 14.64"); + } + power_lut_template (energy_inslew_load_5x5__102) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.94, 1.89, 3.77, 7.55, 15.10"); + } + power_lut_template (energy_inslew_load_5x5__101) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.44, 0.89, 1.78, 3.56, 7.11"); + } + power_lut_template (energy_inslew_load_5x5__100) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("4.87, 9.73, 19.46, 38.92, 77.84"); + } + power_lut_template (energy_inslew_load_5x5__99) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.00, 1.99, 3.98, 7.96, 15.93"); + } + power_lut_template (energy_inslew_load_5x5__98) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.56, 1.13, 2.26, 4.51, 9.03"); + } + power_lut_template (energy_inslew_load_5x5__97) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.64, 1.29, 2.58, 5.16, 10.31"); + } + power_lut_template (energy_inslew_load_5x5__96) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.87, 1.73, 3.47, 6.93, 13.86"); + } + power_lut_template (energy_inslew_load_5x5__95) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.66, 1.32, 2.65, 5.29, 10.59"); + } + power_lut_template (energy_inslew_load_5x5__94) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.57, 1.14, 2.28, 4.56, 9.13"); + } + power_lut_template (energy_inslew_load_5x5__93) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.70, 1.40, 2.79, 5.58, 11.17"); + } + power_lut_template (energy_inslew_load_5x5__92) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.60, 1.20, 2.40, 4.80, 9.59"); + } + power_lut_template (energy_inslew_load_5x5__91) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.54, 1.07, 2.15, 4.30, 8.60"); + } + power_lut_template (energy_inslew_load_5x5__90) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.83, 1.66, 3.32, 6.64, 13.28"); + } + power_lut_template (energy_inslew_load_5x5__89) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.46, 2.92, 5.85, 11.69, 23.38"); + } + power_lut_template (energy_inslew_load_5x5__88) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.90, 1.80, 3.61, 7.21, 14.43"); + } + power_lut_template (energy_inslew_load_5x5__87) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.55, 3.10, 6.20, 12.39"); + } + power_lut_template (energy_inslew_load_5x5__86) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.02, 2.04, 4.08, 8.16, 16.32"); + } + power_lut_template (energy_inslew_load_5x5__85) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("3.02, 6.04, 12.08, 24.15, 48.30"); + } + power_lut_template (energy_inslew_load_5x5__84) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.95, 1.90, 3.79, 7.58, 15.16"); + } + power_lut_template (energy_inslew_load_5x5__83) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.83, 1.66, 3.32, 6.65, 13.30"); + } + power_lut_template (energy_inslew_load_5x5__82) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.70, 1.41, 2.82, 5.64, 11.27"); + } + power_lut_template (energy_inslew_load_5x5__81) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.68, 1.37, 2.73, 5.47, 10.94"); + } + power_lut_template (energy_inslew_load_5x5__80) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.07, 2.15, 4.29, 8.58, 17.17"); + } + power_lut_template (energy_inslew_load_5x5__79) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.10, 2.19, 4.38, 8.77, 17.53"); + } + power_lut_template (energy_inslew_load_5x5__78) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.18, 4.37, 8.74, 17.47, 34.95"); + } + power_lut_template (energy_inslew_load_5x5__77) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.35, 2.71, 5.42, 10.84, 21.67"); + } + power_lut_template (energy_inslew_load_5x5__76) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.11, 2.23, 4.45, 8.91, 17.82"); + } + power_lut_template (energy_inslew_load_5x5__75) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("3.81, 7.61, 15.22, 30.45, 60.90"); + } + power_lut_template (energy_inslew_load_5x5__74) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.07, 4.14, 8.27, 16.55, 33.10"); + } + power_lut_template (energy_inslew_load_5x5__73) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.46, 2.92, 5.84, 11.68, 23.35"); + } + power_lut_template (energy_inslew_load_5x5__72) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.96, 1.93, 3.86, 7.72, 15.44"); + } + power_lut_template (energy_inslew_load_5x5__71) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.05, 2.11, 4.22, 8.44, 16.88"); + } + power_lut_template (energy_inslew_load_5x5__70) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.83, 1.67, 3.33, 6.67, 13.33"); + } + power_lut_template (energy_inslew_load_5x5__69) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.71, 1.42, 2.84, 5.68, 11.36"); + } + power_lut_template (energy_inslew_load_5x5__68) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.74, 5.47, 10.95, 21.90, 43.80"); + } + power_lut_template (energy_inslew_load_5x5__67) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.92, 1.84, 3.68, 7.37, 14.73"); + } + power_lut_template (energy_inslew_load_5x5__66) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.72, 1.43, 2.87, 5.74, 11.48"); + } + power_lut_template (energy_inslew_load_5x5__65) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.90, 1.80, 3.61, 7.21, 14.43"); + } + power_lut_template (energy_inslew_load_5x5__64) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.69, 5.38, 10.76, 21.52, 43.04"); + } + power_lut_template (energy_inslew_load_5x5__63) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.29, 2.58, 5.15, 10.30, 20.60"); + } + power_lut_template (energy_inslew_load_5x5__62) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.06, 2.12, 4.24, 8.48, 16.95"); + } + power_lut_template (energy_inslew_load_5x5__61) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.95, 3.89, 7.78, 15.57, 31.13"); + } + power_lut_template (energy_inslew_load_5x5__60) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.52, 3.03, 6.06, 12.12, 24.25"); + } + power_lut_template (energy_inslew_load_5x5__59) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.13, 2.26, 4.51, 9.02, 18.05"); + } + power_lut_template (energy_inslew_load_5x5__58) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.37, 2.75, 5.49, 10.99, 21.98"); + } + power_lut_template (energy_inslew_load_5x5__57) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.98, 1.96, 3.92, 7.85, 15.69"); + } + power_lut_template (energy_inslew_load_5x5__56) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.96, 1.91, 3.83, 7.66, 15.32"); + } + power_lut_template (energy_inslew_load_5x5__55) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.62, 1.25, 2.50, 5.00, 10.00"); + } + power_lut_template (energy_inslew_load_5x5__54) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.58, 1.16, 2.33, 4.65, 9.31"); + } + power_lut_template (energy_inslew_load_5x5__53) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.75, 1.50, 2.99, 5.98, 11.96"); + } + power_lut_template (energy_inslew_load_5x5__52) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.01, 4.02, 8.04, 16.09, 32.17"); + } + power_lut_template (energy_inslew_load_5x5__51) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.08, 2.17, 4.33, 8.66, 17.32"); + } + power_lut_template (energy_inslew_load_5x5__50) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.84, 1.68, 3.37, 6.74, 13.47"); + } + power_lut_template (energy_inslew_load_5x5__49) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.51, 1.03, 2.05, 4.10, 8.20"); + } + power_lut_template (energy_inslew_load_5x5__48) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.03, 4.06, 8.13, 16.25, 32.50"); + } + power_lut_template (energy_inslew_load_5x5__47) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.11, 2.23, 4.45, 8.91, 17.82"); + } + power_lut_template (energy_inslew_load_5x5__46) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.54, 3.08, 6.16, 12.32"); + } + power_lut_template (energy_inslew_load_5x5__45) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.57, 1.15, 2.29, 4.59, 9.18"); + } + power_lut_template (energy_inslew_load_5x5__44) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.73, 1.47, 2.94, 5.88, 11.76"); + } + power_lut_template (energy_inslew_load_5x5__43) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.57, 1.14, 2.27, 4.54, 9.08"); + } + power_lut_template (energy_inslew_load_5x5__42) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.21, 4.41, 8.82, 17.64, 35.29"); + } + power_lut_template (energy_inslew_load_5x5__41) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.98, 1.96, 3.93, 7.85, 15.71"); + } + power_lut_template (energy_inslew_load_5x5__40) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.49, 0.98, 1.95, 3.90, 7.81"); + } + power_lut_template (energy_inslew_load_5x5__39) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.46, 0.93, 1.85, 3.70, 7.41"); + } + power_lut_template (energy_inslew_load_5x5__38) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.56, 1.11, 2.23, 4.46, 8.91"); + } + power_lut_template (energy_inslew_load_5x5__37) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.70, 1.40, 2.80, 5.59, 11.18"); + } + power_lut_template (energy_inslew_load_5x5__36) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.79, 1.58, 3.15, 6.31, 12.62"); + } + power_lut_template (energy_inslew_5__0) { + variable_1 : input_transition_time; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + } + power_lut_template (energy_inslew_load_5x5__35) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.53, 1.07, 2.13, 4.27, 8.53"); + } + power_lut_template (energy_inslew_load_5x5__34) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.39, 4.77, 9.55, 19.09, 38.19"); + } + power_lut_template (energy_inslew_load_5x5__33) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.27, 2.54, 5.07, 10.14, 20.29"); + } + power_lut_template (energy_inslew_load_5x5__32) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.13, 2.27, 4.53, 9.07, 18.13"); + } + power_lut_template (energy_inslew_load_5x5__31) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("3.38, 6.77, 13.53, 27.06, 54.13"); + } + power_lut_template (energy_inslew_load_5x5__30) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.63, 1.26, 2.53, 5.06, 10.11"); + } + power_lut_template (energy_inslew_load_5x5__29) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.52, 1.05, 2.09, 4.19, 8.37"); + } + power_lut_template (energy_inslew_load_5x5__28) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.49, 0.99, 1.98, 3.96, 7.92"); + } + power_lut_template (energy_inslew_load_5x5__27) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.07, 2.13, 4.26, 8.52, 17.04"); + } + power_lut_template (energy_inslew_load_5x5__26) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.79, 1.59, 3.17, 6.35, 12.70"); + } + power_lut_template (energy_inslew_load_5x5__25) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.65, 1.30, 2.59, 5.18, 10.36"); + } + power_lut_template (energy_inslew_load_5x5__24) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.67, 3.34, 6.68, 13.35, 26.71"); + } + power_lut_template (energy_inslew_load_5x5__23) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.06, 2.12, 4.24, 8.49, 16.97"); + } + power_lut_template (energy_inslew_load_5x5__22) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.15, 2.29, 4.58, 9.17, 18.33"); + } + power_lut_template (energy_inslew_load_5x5__21) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.96, 1.93, 3.86, 7.71, 15.42"); + } + power_lut_template (energy_inslew_load_5x5__20) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.24, 2.49, 4.97, 9.94, 19.89"); + } + power_lut_template (energy_inslew_load_5x5__19) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.01, 2.01, 4.02, 8.05, 16.09"); + } + power_lut_template (energy_inslew_load_5x5__18) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.77, 1.55, 3.10, 6.20, 12.40"); + } + power_lut_template (energy_inslew_load_5x5__17) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.76, 1.52, 3.03, 6.07, 12.13"); + } + power_lut_template (energy_inslew_load_5x5__16) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.75, 1.50, 2.99, 5.98, 11.97"); + } + power_lut_template (energy_inslew_load_5x5__15) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.66, 1.32, 2.64, 5.28, 10.56"); + } + power_lut_template (energy_inslew_load_5x5__14) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.67, 1.34, 2.68, 5.37, 10.74"); + } + power_lut_template (energy_inslew_load_5x5__13) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.13, 2.25, 4.51, 9.02, 18.04"); + } + power_lut_template (energy_inslew_load_5x5__12) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("3.07, 6.15, 12.30, 24.59, 49.19"); + } + power_lut_template (energy_inslew_load_5x5__11) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.66, 3.31, 6.63, 13.25, 26.50"); + } + power_lut_template (energy_inslew_load_5x5__10) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.15, 2.30, 4.60, 9.19, 18.39"); + } + power_lut_template (energy_inslew_load_5x5__9) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.24, 2.49, 4.97, 9.95, 19.90"); + } + power_lut_template (energy_inslew_load_5x5__8) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.66, 1.33, 2.66, 5.31, 10.62"); + } + power_lut_template (energy_inslew_load_5x5__7) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.63, 1.26, 2.52, 5.04, 10.07"); + } + power_lut_template (energy_inslew_load_5x5__6) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.98, 1.96, 3.91, 7.82, 15.65"); + } + power_lut_template (energy_inslew_load_5x5__5) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.81, 1.61, 3.22, 6.44, 12.88"); + } + power_lut_template (energy_inslew_load_5x5__4) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.60, 1.19, 2.39, 4.78, 9.55"); + } + power_lut_template (energy_inslew_load_5x5__3) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("2.35, 4.71, 9.41, 18.82, 37.65"); + } + power_lut_template (energy_inslew_load_5x5__2) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("1.41, 2.83, 5.65, 11.30, 22.61"); + } + power_lut_template (energy_inslew_load_5x5__1) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.70, 1.39, 2.78, 5.56, 11.13"); + } + power_lut_template (energy_inslew_load_5x5__0) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("50.0, 100.0, 200.0, 400.0, 800.0"); + index_2 ("0.57, 1.14, 2.28, 4.56, 9.12"); + } + + + + + cell (an2v0x05) { + area : 0.0 ; + cell_leakage_power : 7.1 ; + leakage_power () { + when : "(b & a)" ; + value : 9.3 ; + } + leakage_power () { + when : "(!(a) | !(b))" ; + value : 4.9 ; + } + pin (b) { + direction : input ; + capacitance : 3.01 ; + } + pin (a) { + direction : input ; + capacitance : 2.95 ; + } + pin (z) { + function : "(b & a)" ; + direction : output ; + capacitance : 2.28 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("41.5, 41.5, 41.5, 53.8, 75.5", \ + "36.8, 36.8, 36.8, 49.7, 72.2", \ + "22.5, 22.5, 22.5, 36.1, 60.0", \ + "-12.0, -12.0, -12.0, 2.5, 28.4", \ + "-86.4, -86.4, -86.4, -70.9, -42.7"); + } + rise_transition (inslew_load_5x5__0) { + values ("41.7, 41.7, 41.7, 62.7, 103.9", \ + "48.9, 48.9, 48.9, 70.1, 111.4", \ + "61.8, 61.8, 61.8, 83.2, 124.9", \ + "85.8, 85.8, 85.8, 107.4, 149.7", \ + "131.7, 131.7, 131.7, 153.6, 196.6"); + } + cell_fall (inslew_load_5x5__0) { + values ("70.2, 70.2, 70.2, 83.1, 105.1", \ + "89.5, 89.5, 89.5, 103.2, 127.2", \ + "122.5, 122.5, 122.5, 137.1, 163.3", \ + "184.0, 184.0, 184.0, 199.6, 228.2", \ + "304.2, 304.2, 304.2, 320.5, 351.5"); + } + fall_transition (inslew_load_5x5__0) { + values ("44.7, 44.7, 44.7, 54.6, 73.3", \ + "61.6, 61.6, 61.6, 71.9, 91.2", \ + "93.3, 93.3, 93.3, 103.8, 124.0", \ + "155.2, 155.2, 155.2, 165.9, 186.9", \ + "278.0, 278.0, 278.0, 289.0, 310.5"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__0) { + values ("38.8, 38.8, 38.8, 50.8, 72.1", \ + "37.4, 37.4, 37.4, 50.1, 72.4", \ + "29.4, 29.4, 29.4, 43.0, 66.9", \ + "8.6, 8.6, 8.6, 23.2, 49.3", \ + "-37.4, -37.4, -37.4, -21.8, 6.8"); + } + rise_transition (inslew_load_5x5__0) { + values ("37.8, 37.8, 37.8, 58.8, 100.2", \ + "46.5, 46.5, 46.5, 67.6, 108.9", \ + "61.8, 61.8, 61.8, 83.1, 124.8", \ + "90.1, 90.1, 90.1, 111.7, 154.1", \ + "144.9, 144.9, 144.9, 166.8, 209.9"); + } + cell_fall (inslew_load_5x5__0) { + values ("58.8, 58.8, 58.8, 71.1, 92.1", \ + "72.3, 72.3, 72.3, 85.7, 108.6", \ + "94.7, 94.7, 94.7, 108.8, 134.2", \ + "135.2, 135.2, 135.2, 150.5, 178.2", \ + "213.4, 213.4, 213.4, 229.6, 259.8"); + } + fall_transition (inslew_load_5x5__0) { + values ("37.4, 37.4, 37.4, 47.2, 65.5", \ + "51.5, 51.5, 51.5, 61.6, 80.5", \ + "77.6, 77.6, 77.6, 88.2, 107.9", \ + "128.8, 128.8, 128.8, 139.4, 160.2", \ + "230.1, 230.1, 230.1, 241.0, 262.2"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__0) { + values ("142.0, 142.0, 142.0, 170.5, 227.6", \ + "162.7, 162.7, 162.7, 191.2, 248.2", \ + "203.3, 203.3, 203.3, 231.8, 288.8", \ + "283.5, 283.5, 283.5, 312.0, 369.1", \ + "443.2, 443.2, 443.2, 471.7, 528.7"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("190.2, 190.2, 190.2, 218.7, 275.7", \ + "255.3, 255.3, 255.3, 283.8, 340.9", \ + "382.9, 382.9, 382.9, 411.4, 468.4", \ + "636.6, 636.6, 636.6, 665.1, 722.1", \ + "1143.1, 1143.1, 1143.1, 1171.6, 1228.6"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__0) { + values ("117.3, 117.3, 117.3, 145.9, 202.9", \ + "140.9, 140.9, 140.9, 169.4, 226.5", \ + "187.2, 187.2, 187.2, 215.7, 272.7", \ + "278.9, 278.9, 278.9, 307.4, 364.4", \ + "461.7, 461.7, 461.7, 490.2, 547.3"); + } + fall_power (energy_inslew_load_5x5__0) { + values ("154.3, 154.3, 154.3, 182.8, 239.8", \ + "206.6, 206.6, 206.6, 235.2, 292.2", \ + "309.2, 309.2, 309.2, 337.7, 394.7", \ + "513.1, 513.1, 513.1, 541.6, 598.6", \ + "920.2, 920.2, 920.2, 948.7, 1005.7"); + } + } + } + } + + cell (an2v0x1) { + area : 0.0 ; + cell_leakage_power : 2.9 ; + leakage_power () { + when : "(b & a)" ; + value : 5.4 ; + } + leakage_power () { + when : "(!(a) | !(b))" ; + value : 0.45 ; + } + pin (b) { + direction : input ; + capacitance : 3.22 ; + } + pin (a) { + direction : input ; + capacitance : 3.53 ; + } + pin (z) { + function : "(b & a)" ; + direction : output ; + capacitance : 2.78 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("42.8, 42.8, 42.8, 53.1, 71.3", \ + "39.4, 39.4, 39.4, 50.2, 69.1", \ + "27.8, 27.8, 27.8, 39.1, 59.2", \ + "-1.0, -1.0, -1.0, 11.0, 32.5", \ + "-63.9, -63.9, -63.9, -51.2, -28.0"); + } + rise_transition (inslew_load_5x5__1) { + values ("36.7, 36.7, 36.7, 52.3, 82.5", \ + "43.7, 43.7, 43.7, 59.3, 89.7", \ + "56.5, 56.5, 56.5, 72.3, 103.0", \ + "80.6, 80.6, 80.6, 96.5, 127.7", \ + "127.1, 127.1, 127.1, 143.2, 174.9"); + } + cell_fall (inslew_load_5x5__1) { + values ("65.8, 65.8, 65.8, 76.5, 94.6", \ + "82.7, 82.7, 82.7, 93.8, 113.5", \ + "110.6, 110.6, 110.6, 122.5, 143.6", \ + "162.0, 162.0, 162.0, 174.6, 197.9", \ + "262.5, 262.5, 262.5, 274.9, 299.9"); + } + fall_transition (inslew_load_5x5__1) { + values ("40.4, 40.4, 40.4, 48.0, 62.2", \ + "55.6, 55.6, 55.6, 63.6, 78.2", \ + "84.4, 84.4, 84.4, 92.4, 107.9", \ + "140.4, 140.4, 140.4, 148.7, 164.5", \ + "251.7, 251.7, 251.7, 260.2, 276.6"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__1) { + values ("40.7, 40.7, 40.7, 50.8, 68.5", \ + "41.2, 41.2, 41.2, 51.8, 70.5", \ + "36.9, 36.9, 36.9, 48.2, 68.3", \ + "23.5, 23.5, 23.5, 35.5, 57.4", \ + "-7.4, -7.4, -7.4, 5.4, 28.9"); + } + rise_transition (inslew_load_5x5__1) { + values ("33.2, 33.2, 33.2, 48.6, 78.8", \ + "41.7, 41.7, 41.7, 57.3, 87.6", \ + "57.0, 57.0, 57.0, 72.7, 103.5", \ + "85.7, 85.7, 85.7, 101.7, 132.8", \ + "141.6, 141.6, 141.6, 157.7, 189.5"); + } + cell_fall (inslew_load_5x5__1) { + values ("55.3, 55.3, 55.3, 65.4, 82.6", \ + "66.3, 66.3, 66.3, 77.1, 95.8", \ + "83.2, 83.2, 83.2, 94.7, 115.3", \ + "113.0, 113.0, 113.0, 125.4, 147.9", \ + "170.0, 170.0, 170.0, 182.7, 207.3"); + } + fall_transition (inslew_load_5x5__1) { + values ("33.8, 33.8, 33.8, 41.3, 55.2", \ + "46.4, 46.4, 46.4, 54.1, 68.6", \ + "69.9, 69.9, 69.9, 77.8, 92.9", \ + "115.6, 115.6, 115.6, 123.8, 139.5", \ + "206.5, 206.5, 206.5, 214.8, 231.1"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__1) { + values ("191.1, 191.1, 191.1, 225.9, 295.5", \ + "220.3, 220.3, 220.3, 255.0, 324.6", \ + "277.7, 277.7, 277.7, 312.4, 382.0", \ + "391.2, 391.2, 391.2, 426.0, 495.5", \ + "616.9, 616.9, 616.9, 651.6, 721.2"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("249.0, 249.0, 249.0, 283.7, 353.3", \ + "331.7, 331.7, 331.7, 366.5, 436.0", \ + "493.6, 493.6, 493.6, 528.3, 597.9", \ + "815.1, 815.1, 815.1, 849.9, 919.5", \ + "1457.1, 1457.1, 1457.1, 1491.9, 1561.4"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__1) { + values ("160.8, 160.8, 160.8, 195.6, 265.2", \ + "194.7, 194.7, 194.7, 229.5, 299.0", \ + "261.1, 261.1, 261.1, 295.9, 365.4", \ + "392.5, 392.5, 392.5, 427.3, 496.8", \ + "654.4, 654.4, 654.4, 689.2, 758.7"); + } + fall_power (energy_inslew_load_5x5__1) { + values ("203.7, 203.7, 203.7, 238.5, 308.0", \ + "269.2, 269.2, 269.2, 304.0, 373.6", \ + "397.4, 397.4, 397.4, 432.2, 501.8", \ + "652.0, 652.0, 652.0, 686.8, 756.4", \ + "1160.3, 1160.3, 1160.3, 1195.1, 1264.7"); + } + } + } + } + + cell (an2v0x4) { + area : 0.0 ; + cell_leakage_power : 3.1 ; + leakage_power () { + when : "(b & a)" ; + value : 2.7 ; + } + leakage_power () { + when : "(!(a) | !(b))" ; + value : 3.5 ; + } + pin (b) { + direction : input ; + capacitance : 5.23 ; + } + pin (a) { + direction : input ; + capacitance : 5.45 ; + } + pin (z) { + function : "(a & b)" ; + direction : output ; + capacitance : 5.65 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("43.1, 43.1, 43.1, 51.3, 65.5", \ + "39.9, 39.9, 39.9, 48.3, 63.0", \ + "28.0, 28.0, 28.0, 36.6, 52.0", \ + "-2.7, -2.7, -2.7, 6.2, 22.5", \ + "-70.6, -70.6, -70.6, -61.5, -44.3"); + } + rise_transition (inslew_load_5x5__2) { + values ("34.5, 34.5, 34.5, 45.7, 67.5", \ + "42.1, 42.1, 42.1, 53.3, 75.2", \ + "55.8, 55.8, 55.8, 67.1, 89.1", \ + "81.1, 81.1, 81.1, 92.4, 114.7", \ + "129.3, 129.3, 129.3, 140.8, 163.4"); + } + cell_fall (inslew_load_5x5__2) { + values ("67.2, 67.2, 67.2, 74.8, 88.3", \ + "85.0, 85.0, 85.0, 93.2, 107.3", \ + "114.4, 114.4, 114.4, 123.0, 138.5", \ + "169.0, 169.0, 169.0, 177.3, 194.1", \ + "276.1, 276.1, 276.1, 284.6, 300.5"); + } + fall_transition (inslew_load_5x5__2) { + values ("36.4, 36.4, 36.4, 41.6, 51.1", \ + "50.6, 50.6, 50.6, 55.8, 65.7", \ + "77.2, 77.2, 77.2, 82.4, 92.6", \ + "129.2, 129.2, 129.2, 134.5, 144.8", \ + "231.8, 231.8, 231.8, 237.3, 248.2"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__2) { + values ("41.1, 41.1, 41.1, 49.1, 63.1", \ + "41.5, 41.5, 41.5, 49.8, 64.4", \ + "36.2, 36.2, 36.2, 44.7, 60.2", \ + "19.4, 19.4, 19.4, 28.3, 44.7", \ + "-19.6, -19.6, -19.6, -10.4, 6.8"); + } + rise_transition (inslew_load_5x5__2) { + values ("30.7, 30.7, 30.7, 41.9, 63.6", \ + "40.0, 40.0, 40.0, 51.2, 73.1", \ + "56.2, 56.2, 56.2, 67.5, 89.5", \ + "86.1, 86.1, 86.1, 97.4, 119.8", \ + "143.6, 143.6, 143.6, 155.1, 177.8"); + } + cell_fall (inslew_load_5x5__2) { + values ("57.4, 57.4, 57.4, 65.0, 77.7", \ + "70.1, 70.1, 70.1, 77.9, 91.8", \ + "89.5, 89.5, 89.5, 98.0, 112.9", \ + "124.1, 124.1, 124.1, 132.7, 149.3", \ + "191.7, 191.7, 191.7, 200.0, 216.1"); + } + fall_transition (inslew_load_5x5__2) { + values ("31.0, 31.0, 31.0, 36.0, 45.4", \ + "42.9, 42.9, 42.9, 48.1, 57.8", \ + "65.2, 65.2, 65.2, 70.4, 80.5", \ + "108.8, 108.8, 108.8, 114.0, 124.3", \ + "194.8, 194.8, 194.8, 200.2, 210.9"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__2) { + values ("430.0, 430.0, 430.0, 500.7, 641.9", \ + "492.1, 492.1, 492.1, 562.7, 704.0", \ + "612.4, 612.4, 612.4, 683.0, 824.3", \ + "848.2, 848.2, 848.2, 918.8, 1060.1", \ + "1313.9, 1313.9, 1313.9, 1384.5, 1525.8"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("547.2, 547.2, 547.2, 617.9, 759.1", \ + "721.0, 721.0, 721.0, 791.7, 933.0", \ + "1059.3, 1059.3, 1059.3, 1129.9, 1271.2", \ + "1729.8, 1729.8, 1729.8, 1800.4, 1941.7", \ + "3067.2, 3067.2, 3067.2, 3137.8, 3279.1"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__2) { + values ("368.6, 368.6, 368.6, 439.2, 580.5", \ + "440.6, 440.6, 440.6, 511.3, 652.6", \ + "579.7, 579.7, 579.7, 650.4, 791.7", \ + "852.6, 852.6, 852.6, 923.3, 1064.6", \ + "1394.2, 1394.2, 1394.2, 1464.9, 1606.1"); + } + fall_power (energy_inslew_load_5x5__2) { + values ("460.3, 460.3, 460.3, 530.9, 672.2", \ + "602.2, 602.2, 602.2, 672.8, 814.1", \ + "877.8, 877.8, 877.8, 948.5, 1089.8", \ + "1424.0, 1424.0, 1424.0, 1494.7, 1635.9", \ + "2513.0, 2513.0, 2513.0, 2583.6, 2724.9"); + } + } + } + } + + cell (an2v0x8) { + area : 0.0 ; + cell_leakage_power : 10 ; + leakage_power () { + when : "(b & a)" ; + value : 9.6 ; + } + leakage_power () { + when : "(!(a) | !(b))" ; + value : 11 ; + } + pin (b) { + direction : input ; + capacitance : 8.57 ; + } + pin (a) { + direction : input ; + capacitance : 9.15 ; + } + pin (z) { + function : "(a & b)" ; + direction : output ; + capacitance : 9.41 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("44.8, 44.8, 44.8, 51.9, 64.3", \ + "41.7, 41.7, 41.7, 48.9, 61.7", \ + "29.8, 29.8, 29.8, 37.1, 50.4", \ + "-1.3, -1.3, -1.3, 6.2, 20.2", \ + "-70.7, -70.7, -70.7, -62.9, -48.4"); + } + rise_transition (inslew_load_5x5__3) { + values ("34.7, 34.7, 34.7, 44.1, 62.4", \ + "42.1, 42.1, 42.1, 51.5, 69.9", \ + "55.5, 55.5, 55.5, 65.0, 83.5", \ + "80.5, 80.5, 80.5, 90.0, 108.7", \ + "127.9, 127.9, 127.9, 137.6, 156.5"); + } + cell_fall (inslew_load_5x5__3) { + values ("69.7, 69.7, 69.7, 76.1, 87.7", \ + "88.7, 88.7, 88.7, 95.6, 107.5", \ + "119.9, 119.9, 119.9, 127.0, 140.2", \ + "177.6, 177.6, 177.6, 184.2, 198.1", \ + "290.1, 290.1, 290.1, 296.8, 309.8"); + } + fall_transition (inslew_load_5x5__3) { + values ("38.0, 38.0, 38.0, 42.2, 50.2", \ + "52.8, 52.8, 52.8, 57.0, 65.4", \ + "80.2, 80.2, 80.2, 84.5, 92.9", \ + "133.6, 133.6, 133.6, 138.1, 146.5", \ + "239.0, 239.0, 239.0, 243.4, 252.3"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__3) { + values ("43.0, 43.0, 43.0, 50.0, 62.2", \ + "43.7, 43.7, 43.7, 50.9, 63.5", \ + "38.5, 38.5, 38.5, 45.9, 59.2", \ + "21.5, 21.5, 21.5, 28.9, 43.1", \ + "-18.7, -18.7, -18.7, -10.8, 3.9"); + } + rise_transition (inslew_load_5x5__3) { + values ("30.7, 30.7, 30.7, 40.2, 58.4", \ + "39.9, 39.9, 39.9, 49.3, 67.7", \ + "55.9, 55.9, 55.9, 65.3, 83.8", \ + "85.4, 85.4, 85.4, 94.9, 113.6", \ + "142.1, 142.1, 142.1, 151.7, 170.7"); + } + cell_fall (inslew_load_5x5__3) { + values ("60.0, 60.0, 60.0, 66.3, 77.5", \ + "73.7, 73.7, 73.7, 80.4, 92.1", \ + "94.6, 94.6, 94.6, 101.7, 114.5", \ + "131.6, 131.6, 131.6, 138.5, 152.4", \ + "203.5, 203.5, 203.5, 210.2, 222.9"); + } + fall_transition (inslew_load_5x5__3) { + values ("32.3, 32.3, 32.3, 36.6, 44.5", \ + "44.8, 44.8, 44.8, 49.0, 57.2", \ + "67.6, 67.6, 67.6, 72.0, 80.3", \ + "112.2, 112.2, 112.2, 116.5, 124.9", \ + "200.0, 200.0, 200.0, 204.4, 213.4"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__3) { + values ("789.1, 789.1, 789.1, 906.8, 1142.1", \ + "899.3, 899.3, 899.3, 1017.0, 1252.3", \ + "1112.5, 1112.5, 1112.5, 1230.2, 1465.5", \ + "1529.6, 1529.6, 1529.6, 1647.3, 1882.6", \ + "2351.2, 2351.2, 2351.2, 2468.8, 2704.1"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("1024.0, 1024.0, 1024.0, 1141.6, 1376.9", \ + "1344.1, 1344.1, 1344.1, 1461.7, 1697.0", \ + "1960.9, 1960.9, 1960.9, 2078.6, 2313.9", \ + "3180.2, 3180.2, 3180.2, 3297.9, 3533.2", \ + "5609.3, 5609.3, 5609.3, 5726.9, 5962.2"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__3) { + values ("679.9, 679.9, 679.9, 797.5, 1032.8", \ + "809.2, 809.2, 809.2, 926.8, 1162.1", \ + "1056.8, 1056.8, 1056.8, 1174.4, 1409.7", \ + "1541.0, 1541.0, 1541.0, 1658.6, 1893.9", \ + "2499.0, 2499.0, 2499.0, 2616.6, 2851.9"); + } + fall_power (energy_inslew_load_5x5__3) { + values ("865.6, 865.6, 865.6, 983.3, 1218.6", \ + "1126.7, 1126.7, 1126.7, 1244.3, 1479.6", \ + "1628.3, 1628.3, 1628.3, 1746.0, 1981.3", \ + "2618.6, 2618.6, 2618.6, 2736.3, 2971.6", \ + "4591.7, 4591.7, 4591.7, 4709.3, 4944.6"); + } + } + } + } + + cell (an3v0x05) { + area : 0.0 ; + cell_leakage_power : 13 ; + leakage_power () { + when : "(c & b & a)" ; + value : 22 ; + } + leakage_power () { + when : "(!(a) | !(b) | !(c))" ; + value : 4.9 ; + } + pin (c) { + direction : input ; + capacitance : 3.21 ; + } + pin (b) { + direction : input ; + capacitance : 3.23 ; + } + pin (a) { + direction : input ; + capacitance : 2.98 ; + } + pin (z) { + function : "(a & b & c)" ; + direction : output ; + capacitance : 2.39 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("59.2, 59.2, 59.2, 73.1, 97.7", \ + "54.0, 54.0, 54.0, 68.3, 93.4", \ + "39.3, 39.3, 39.3, 54.2, 80.4", \ + "4.0, 4.0, 4.0, 19.5, 47.4", \ + "-74.4, -74.4, -74.4, -58.0, -28.1"); + } + rise_transition (inslew_load_5x5__4) { + values ("59.6, 59.6, 59.6, 81.9, 125.5", \ + "65.9, 65.9, 65.9, 88.3, 132.0", \ + "78.3, 78.3, 78.3, 100.8, 144.9", \ + "101.9, 101.9, 101.9, 124.6, 169.2", \ + "147.7, 147.7, 147.7, 170.7, 215.8"); + } + cell_fall (inslew_load_5x5__4) { + values ("85.6, 85.6, 85.6, 99.6, 123.6", \ + "107.3, 107.3, 107.3, 121.8, 147.7", \ + "143.5, 143.5, 143.5, 158.9, 186.8", \ + "210.2, 210.2, 210.2, 226.6, 256.7", \ + "339.7, 339.7, 339.7, 356.7, 389.1"); + } + fall_transition (inslew_load_5x5__4) { + values ("53.4, 53.4, 53.4, 63.9, 83.9", \ + "70.6, 70.6, 70.6, 81.5, 102.0", \ + "102.7, 102.7, 102.7, 113.9, 135.2", \ + "165.2, 165.2, 165.2, 176.7, 198.8", \ + "289.2, 289.2, 289.2, 300.8, 323.5"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("56.7, 56.7, 56.7, 70.3, 94.3", \ + "55.5, 55.5, 55.5, 69.6, 94.4", \ + "47.6, 47.6, 47.6, 62.4, 88.5", \ + "25.2, 25.2, 25.2, 40.8, 68.9", \ + "-26.2, -26.2, -26.2, -9.7, 20.6"); + } + rise_transition (inslew_load_5x5__4) { + values ("54.4, 54.4, 54.4, 76.6, 120.0", \ + "62.3, 62.3, 62.3, 84.7, 128.3", \ + "77.0, 77.0, 77.0, 99.5, 143.5", \ + "104.8, 104.8, 104.8, 127.6, 172.2", \ + "158.8, 158.8, 158.8, 181.8, 227.1"); + } + cell_fall (inslew_load_5x5__4) { + values ("75.5, 75.5, 75.5, 89.1, 112.2", \ + "91.7, 91.7, 91.7, 106.0, 130.9", \ + "117.6, 117.6, 117.6, 132.7, 159.8", \ + "163.7, 163.7, 163.7, 179.8, 209.2", \ + "251.8, 251.8, 251.8, 268.7, 300.5"); + } + fall_transition (inslew_load_5x5__4) { + values ("46.7, 46.7, 46.7, 57.2, 76.8", \ + "61.2, 61.2, 61.2, 72.0, 92.2", \ + "88.0, 88.0, 88.0, 99.1, 120.1", \ + "140.1, 140.1, 140.1, 151.4, 173.4", \ + "243.3, 243.3, 243.3, 254.9, 277.4"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__4) { + values ("51.6, 51.6, 51.6, 64.8, 88.2", \ + "53.6, 53.6, 53.6, 67.5, 91.8", \ + "51.5, 51.5, 51.5, 66.2, 92.1", \ + "41.0, 41.0, 41.0, 56.6, 84.7", \ + "15.1, 15.1, 15.1, 31.6, 62.1"); + } + rise_transition (inslew_load_5x5__4) { + values ("48.5, 48.5, 48.5, 70.6, 113.9", \ + "57.8, 57.8, 57.8, 80.1, 123.6", \ + "74.6, 74.6, 74.6, 97.1, 141.1", \ + "106.3, 106.3, 106.3, 129.1, 173.7", \ + "168.0, 168.0, 168.0, 191.1, 236.5"); + } + cell_fall (inslew_load_5x5__4) { + values ("64.4, 64.4, 64.4, 77.3, 99.4", \ + "75.8, 75.8, 75.8, 89.7, 113.6", \ + "92.8, 92.8, 92.8, 107.5, 133.8", \ + "121.7, 121.7, 121.7, 137.5, 166.0", \ + "175.7, 175.7, 175.7, 192.4, 223.5"); + } + fall_transition (inslew_load_5x5__4) { + values ("39.7, 39.7, 39.7, 50.0, 69.3", \ + "52.1, 52.1, 52.1, 62.6, 82.5", \ + "74.7, 74.7, 74.7, 85.7, 106.3", \ + "118.8, 118.8, 118.8, 130.0, 151.7", \ + "206.0, 206.0, 206.0, 217.5, 239.8"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__4) { + values ("208.5, 208.5, 208.5, 238.4, 298.1", \ + "229.3, 229.3, 229.3, 259.2, 318.9", \ + "270.9, 270.9, 270.9, 300.8, 360.5", \ + "353.3, 353.3, 353.3, 383.2, 442.9", \ + "517.3, 517.3, 517.3, 547.1, 606.8"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("251.3, 251.3, 251.3, 281.2, 340.9", \ + "323.3, 323.3, 323.3, 353.2, 412.9", \ + "464.1, 464.1, 464.1, 494.0, 553.7", \ + "743.8, 743.8, 743.8, 773.6, 833.3", \ + "1301.9, 1301.9, 1301.9, 1331.8, 1391.5"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__4) { + values ("180.1, 180.1, 180.1, 210.0, 269.7", \ + "204.3, 204.3, 204.3, 234.2, 293.9", \ + "251.8, 251.8, 251.8, 281.7, 341.4", \ + "346.0, 346.0, 346.0, 375.8, 435.5", \ + "533.3, 533.3, 533.3, 563.2, 622.9"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("214.4, 214.4, 214.4, 244.2, 303.9", \ + "272.8, 272.8, 272.8, 302.7, 362.4", \ + "387.0, 387.0, 387.0, 416.9, 476.6", \ + "613.7, 613.7, 613.7, 643.6, 703.3", \ + "1066.1, 1066.1, 1066.1, 1096.0, 1155.7"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__4) { + values ("150.7, 150.7, 150.7, 180.5, 240.2", \ + "177.6, 177.6, 177.6, 207.4, 267.2", \ + "230.5, 230.5, 230.5, 260.3, 320.0", \ + "335.1, 335.1, 335.1, 364.9, 424.7", \ + "543.6, 543.6, 543.6, 573.5, 633.2"); + } + fall_power (energy_inslew_load_5x5__4) { + values ("176.3, 176.3, 176.3, 206.2, 265.9", \ + "224.3, 224.3, 224.3, 254.2, 313.9", \ + "318.2, 318.2, 318.2, 348.1, 407.8", \ + "504.5, 504.5, 504.5, 534.4, 594.1", \ + "876.4, 876.4, 876.4, 906.2, 965.9"); + } + } + } + } + + cell (an3v0x1) { + area : 0.0 ; + cell_leakage_power : 4.3 ; + leakage_power () { + when : "(c & b & a)" ; + value : 8.1 ; + } + leakage_power () { + when : "(!(a) | !(b) | !(c))" ; + value : 0.45 ; + } + pin (c) { + direction : input ; + capacitance : 3.64 ; + } + pin (b) { + direction : input ; + capacitance : 3.73 ; + } + pin (a) { + direction : input ; + capacitance : 3.43 ; + } + pin (z) { + function : "(a & b & c)" ; + direction : output ; + capacitance : 3.22 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__5) { + values ("55.6, 55.6, 55.6, 68.0, 89.6", \ + "50.7, 50.7, 50.7, 63.3, 85.5", \ + "35.9, 35.9, 35.9, 49.1, 72.2", \ + "-0.1, -0.1, -0.1, 13.6, 38.2", \ + "-79.9, -79.9, -79.9, -65.5, -39.2"); + } + rise_transition (inslew_load_5x5__5) { + values ("49.8, 49.8, 49.8, 67.8, 103.0", \ + "55.4, 55.4, 55.4, 73.5, 108.8", \ + "66.2, 66.2, 66.2, 84.4, 120.0", \ + "86.7, 86.7, 86.7, 105.1, 141.1", \ + "126.4, 126.4, 126.4, 145.0, 181.4"); + } + cell_fall (inslew_load_5x5__5) { + values ("84.3, 84.3, 84.3, 96.7, 118.2", \ + "105.4, 105.4, 105.4, 118.4, 141.6", \ + "140.8, 140.8, 140.8, 154.7, 179.4", \ + "206.0, 206.0, 206.0, 220.4, 247.4", \ + "332.6, 332.6, 332.6, 347.1, 375.9"); + } + fall_transition (inslew_load_5x5__5) { + values ("51.4, 51.4, 51.4, 60.3, 77.0", \ + "68.5, 68.5, 68.5, 77.7, 94.9", \ + "100.2, 100.2, 100.2, 109.6, 127.7", \ + "162.1, 162.1, 162.1, 171.7, 190.3", \ + "284.6, 284.6, 284.6, 294.6, 313.8"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__5) { + values ("53.2, 53.2, 53.2, 65.3, 86.5", \ + "51.9, 51.9, 51.9, 64.4, 86.3", \ + "43.4, 43.4, 43.4, 56.5, 79.6", \ + "19.7, 19.7, 19.7, 33.5, 58.2", \ + "-34.3, -34.3, -34.3, -19.8, 6.8"); + } + rise_transition (inslew_load_5x5__5) { + values ("45.3, 45.3, 45.3, 63.3, 98.3", \ + "52.3, 52.3, 52.3, 70.4, 105.6", \ + "65.1, 65.1, 65.1, 83.4, 118.9", \ + "89.5, 89.5, 89.5, 107.9, 143.9", \ + "136.5, 136.5, 136.5, 155.1, 191.7"); + } + cell_fall (inslew_load_5x5__5) { + values ("74.2, 74.2, 74.2, 86.4, 107.1", \ + "90.4, 90.4, 90.4, 103.0, 125.5", \ + "115.9, 115.9, 115.9, 129.5, 153.5", \ + "161.4, 161.4, 161.4, 175.8, 202.1", \ + "248.7, 248.7, 248.7, 263.3, 291.7"); + } + fall_transition (inslew_load_5x5__5) { + values ("45.0, 45.0, 45.0, 53.8, 70.2", \ + "59.5, 59.5, 59.5, 68.6, 85.5", \ + "86.3, 86.3, 86.3, 95.6, 113.4", \ + "138.4, 138.4, 138.4, 148.0, 166.4", \ + "241.7, 241.7, 241.7, 251.6, 270.7"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__5) { + values ("48.5, 48.5, 48.5, 60.3, 80.9", \ + "49.9, 49.9, 49.9, 62.2, 83.7", \ + "46.6, 46.6, 46.6, 59.5, 82.5", \ + "33.7, 33.7, 33.7, 47.4, 72.3", \ + "2.8, 2.8, 2.8, 17.4, 44.3"); + } + rise_transition (inslew_load_5x5__5) { + values ("40.4, 40.4, 40.4, 58.3, 93.2", \ + "48.5, 48.5, 48.5, 66.5, 101.6", \ + "63.1, 63.1, 63.1, 81.3, 116.7", \ + "90.6, 90.6, 90.6, 109.0, 145.0", \ + "144.0, 144.0, 144.0, 162.6, 199.3"); + } + cell_fall (inslew_load_5x5__5) { + values ("63.5, 63.5, 63.5, 75.2, 95.0", \ + "75.2, 75.2, 75.2, 87.6, 109.1", \ + "92.6, 92.6, 92.6, 105.8, 129.3", \ + "122.3, 122.3, 122.3, 136.5, 162.1", \ + "178.2, 178.2, 178.2, 192.9, 220.9"); + } + fall_transition (inslew_load_5x5__5) { + values ("38.3, 38.3, 38.3, 46.9, 63.0", \ + "50.8, 50.8, 50.8, 59.8, 76.4", \ + "73.9, 73.9, 73.9, 83.2, 100.6", \ + "118.8, 118.8, 118.8, 128.3, 146.6", \ + "207.8, 207.8, 207.8, 217.4, 236.3"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__5) { + values ("264.1, 264.1, 264.1, 304.4, 384.9", \ + "289.7, 289.7, 289.7, 330.0, 410.5", \ + "340.6, 340.6, 340.6, 380.9, 461.4", \ + "441.3, 441.3, 441.3, 481.6, 562.1", \ + "641.2, 641.2, 641.2, 681.5, 762.0"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("328.8, 328.8, 328.8, 369.0, 449.5", \ + "423.7, 423.7, 423.7, 463.9, 544.4", \ + "608.8, 608.8, 608.8, 649.1, 729.6", \ + "976.1, 976.1, 976.1, 1016.4, 1096.9", \ + "1709.0, 1709.0, 1709.0, 1749.3, 1829.8"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__5) { + values ("229.4, 229.4, 229.4, 269.6, 350.1", \ + "259.4, 259.4, 259.4, 299.7, 380.2", \ + "318.3, 318.3, 318.3, 358.6, 439.1", \ + "434.9, 434.9, 434.9, 475.1, 555.6", \ + "666.3, 666.3, 666.3, 706.6, 787.1"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("282.4, 282.4, 282.4, 322.7, 403.2", \ + "360.8, 360.8, 360.8, 401.0, 481.5", \ + "513.3, 513.3, 513.3, 553.5, 634.1", \ + "815.8, 815.8, 815.8, 856.0, 936.5", \ + "1419.3, 1419.3, 1419.3, 1459.6, 1540.1"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__5) { + values ("193.2, 193.2, 193.2, 233.4, 313.9", \ + "226.5, 226.5, 226.5, 266.8, 347.3", \ + "291.8, 291.8, 291.8, 332.0, 412.5", \ + "420.8, 420.8, 420.8, 461.1, 541.6", \ + "677.7, 677.7, 677.7, 717.9, 798.4"); + } + fall_power (energy_inslew_load_5x5__5) { + values ("235.2, 235.2, 235.2, 275.4, 356.0", \ + "301.1, 301.1, 301.1, 341.4, 421.9", \ + "429.5, 429.5, 429.5, 469.7, 550.3", \ + "684.0, 684.0, 684.0, 724.2, 804.7", \ + "1191.8, 1191.8, 1191.8, 1232.0, 1312.5"); + } + } + } + } + + cell (an3v0x2) { + area : 0.0 ; + cell_leakage_power : 1.2 ; + leakage_power () { + when : "(c & b & a)" ; + value : 0.83 ; + } + leakage_power () { + when : "(!(a) | !(b) | !(c))" ; + value : 1.5 ; + } + pin (c) { + direction : input ; + capacitance : 4.38 ; + } + pin (b) { + direction : input ; + capacitance : 4.31 ; + } + pin (a) { + direction : input ; + capacitance : 4.26 ; + } + pin (z) { + function : "(a & b & c)" ; + direction : output ; + capacitance : 3.91 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("56.9, 56.9, 56.9, 68.0, 87.6", \ + "51.9, 51.9, 51.9, 63.2, 83.2", \ + "37.5, 37.5, 37.5, 49.0, 69.9", \ + "2.0, 2.0, 2.0, 14.0, 35.9", \ + "-76.3, -76.3, -76.3, -63.9, -40.7"); + } + rise_transition (inslew_load_5x5__6) { + values ("51.3, 51.3, 51.3, 66.7, 96.8", \ + "57.6, 57.6, 57.6, 73.2, 103.4", \ + "70.1, 70.1, 70.1, 85.7, 116.1", \ + "93.7, 93.7, 93.7, 109.3, 140.1", \ + "139.1, 139.1, 139.1, 155.0, 186.1"); + } + cell_fall (inslew_load_5x5__6) { + values ("75.1, 75.1, 75.1, 85.3, 102.8", \ + "94.9, 94.9, 94.9, 105.7, 124.6", \ + "127.9, 127.9, 127.9, 139.4, 159.8", \ + "188.5, 188.5, 188.5, 200.5, 222.9", \ + "307.3, 307.3, 307.3, 319.2, 342.1"); + } + fall_transition (inslew_load_5x5__6) { + values ("40.2, 40.2, 40.2, 47.3, 60.3", \ + "54.1, 54.1, 54.1, 61.4, 74.9", \ + "80.0, 80.0, 80.0, 87.4, 101.5", \ + "130.6, 130.6, 130.6, 138.1, 152.8", \ + "230.4, 230.4, 230.4, 238.2, 253.5"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("54.1, 54.1, 54.1, 65.0, 84.1", \ + "53.1, 53.1, 53.1, 64.2, 84.1", \ + "45.5, 45.5, 45.5, 57.0, 77.8", \ + "23.4, 23.4, 23.4, 35.4, 57.5", \ + "-27.3, -27.3, -27.3, -14.8, 8.6"); + } + rise_transition (inslew_load_5x5__6) { + values ("46.0, 46.0, 46.0, 61.4, 91.4", \ + "54.0, 54.0, 54.0, 69.5, 99.7", \ + "69.0, 69.0, 69.0, 84.5, 115.0", \ + "97.0, 97.0, 97.0, 112.7, 143.5", \ + "151.2, 151.2, 151.2, 167.0, 198.3"); + } + cell_fall (inslew_load_5x5__6) { + values ("66.2, 66.2, 66.2, 76.2, 93.0", \ + "80.9, 80.9, 80.9, 91.3, 109.7", \ + "104.0, 104.0, 104.0, 115.3, 135.0", \ + "145.0, 145.0, 145.0, 157.0, 178.9", \ + "224.5, 224.5, 224.5, 236.2, 259.3"); + } + fall_transition (inslew_load_5x5__6) { + values ("35.2, 35.2, 35.2, 42.1, 54.9", \ + "46.8, 46.8, 46.8, 54.0, 67.2", \ + "68.4, 68.4, 68.4, 75.7, 89.7", \ + "110.5, 110.5, 110.5, 117.9, 132.3", \ + "193.6, 193.6, 193.6, 201.4, 216.3"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__6) { + values ("48.6, 48.6, 48.6, 59.2, 77.9", \ + "50.6, 50.6, 50.6, 61.6, 81.0", \ + "48.1, 48.1, 48.1, 59.6, 80.2", \ + "37.1, 37.1, 37.1, 49.1, 71.2", \ + "9.7, 9.7, 9.7, 22.2, 45.7"); + } + rise_transition (inslew_load_5x5__6) { + values ("40.0, 40.0, 40.0, 55.4, 85.3", \ + "49.4, 49.4, 49.4, 64.8, 94.9", \ + "66.2, 66.2, 66.2, 81.8, 112.1", \ + "97.7, 97.7, 97.7, 113.4, 144.2", \ + "158.8, 158.8, 158.8, 174.7, 206.0"); + } + cell_fall (inslew_load_5x5__6) { + values ("56.4, 56.4, 56.4, 66.0, 82.0", \ + "66.9, 66.9, 66.9, 77.1, 94.5", \ + "82.4, 82.4, 82.4, 93.4, 112.5", \ + "108.6, 108.6, 108.6, 120.3, 141.6", \ + "158.1, 158.1, 158.1, 169.7, 192.8"); + } + fall_transition (inslew_load_5x5__6) { + values ("29.8, 29.8, 29.8, 36.6, 49.1", \ + "39.8, 39.8, 39.8, 46.9, 59.9", \ + "58.4, 58.4, 58.4, 65.7, 79.3", \ + "94.5, 94.5, 94.5, 101.9, 116.2", \ + "165.9, 165.9, 165.9, 173.7, 188.4"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__6) { + values ("350.5, 350.5, 350.5, 399.4, 497.2", \ + "385.9, 385.9, 385.9, 434.8, 532.6", \ + "456.6, 456.6, 456.6, 505.5, 603.3", \ + "596.1, 596.1, 596.1, 645.0, 742.8", \ + "872.8, 872.8, 872.8, 921.7, 1019.5"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("397.7, 397.7, 397.7, 446.6, 544.4", \ + "512.1, 512.1, 512.1, 561.0, 658.8", \ + "735.6, 735.6, 735.6, 784.5, 882.3", \ + "1179.5, 1179.5, 1179.5, 1228.4, 1326.2", \ + "2065.1, 2065.1, 2065.1, 2114.0, 2211.8"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__6) { + values ("303.3, 303.3, 303.3, 352.2, 450.0", \ + "345.4, 345.4, 345.4, 394.3, 492.1", \ + "427.8, 427.8, 427.8, 476.7, 574.5", \ + "590.2, 590.2, 590.2, 639.1, 736.9", \ + "912.7, 912.7, 912.7, 961.6, 1059.4"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("340.4, 340.4, 340.4, 389.3, 487.1", \ + "433.1, 433.1, 433.1, 482.0, 579.8", \ + "614.0, 614.0, 614.0, 662.9, 760.7", \ + "973.1, 973.1, 973.1, 1022.0, 1119.8", \ + "1689.5, 1689.5, 1689.5, 1738.4, 1836.2"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__6) { + values ("253.5, 253.5, 253.5, 302.4, 400.2", \ + "299.9, 299.9, 299.9, 348.8, 446.6", \ + "390.2, 390.2, 390.2, 439.1, 536.9", \ + "568.3, 568.3, 568.3, 617.2, 715.0", \ + "922.8, 922.8, 922.8, 971.7, 1069.5"); + } + fall_power (energy_inslew_load_5x5__6) { + values ("282.2, 282.2, 282.2, 331.1, 428.9", \ + "359.8, 359.8, 359.8, 408.7, 506.5", \ + "511.2, 511.2, 511.2, 560.1, 657.9", \ + "811.4, 811.4, 811.4, 860.3, 958.1", \ + "1410.5, 1410.5, 1410.5, 1459.4, 1557.2"); + } + } + } + } + + cell (an3v6x05) { + area : 0.0 ; + cell_leakage_power : 13 ; + leakage_power () { + when : "(c & b & a)" ; + value : 22 ; + } + leakage_power () { + when : "(!(a) | !(b) | !(c))" ; + value : 4.9 ; + } + pin (c) { + direction : input ; + capacitance : 3.38 ; + } + pin (b) { + direction : input ; + capacitance : 3.38 ; + } + pin (a) { + direction : input ; + capacitance : 3.33 ; + } + pin (z) { + function : "(c & a & b)" ; + direction : output ; + capacitance : 2.52 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__7) { + values ("59.8, 59.8, 59.8, 74.4, 100.0", \ + "54.6, 54.6, 54.6, 69.5, 95.8", \ + "40.1, 40.1, 40.1, 55.6, 83.0", \ + "4.6, 4.6, 4.6, 20.9, 50.0", \ + "-73.7, -73.7, -73.7, -56.5, -25.2"); + } + rise_transition (inslew_load_5x5__7) { + values ("60.7, 60.7, 60.7, 84.2, 130.0", \ + "67.1, 67.1, 67.1, 90.6, 136.7", \ + "79.4, 79.4, 79.4, 103.1, 149.5", \ + "103.0, 103.0, 103.0, 127.0, 173.9", \ + "148.8, 148.8, 148.8, 173.0, 220.6"); + } + cell_fall (inslew_load_5x5__7) { + values ("86.2, 86.2, 86.2, 100.8, 125.8", \ + "107.9, 107.9, 107.9, 123.2, 150.1", \ + "144.2, 144.2, 144.2, 160.4, 189.5", \ + "211.0, 211.0, 211.0, 228.2, 259.7", \ + "340.4, 340.4, 340.4, 358.3, 392.3"); + } + fall_transition (inslew_load_5x5__7) { + values ("53.8, 53.8, 53.8, 64.9, 85.8", \ + "71.1, 71.1, 71.1, 82.6, 104.1", \ + "103.3, 103.3, 103.3, 115.0, 137.4", \ + "165.8, 165.8, 165.8, 177.8, 201.1", \ + "289.8, 289.8, 289.8, 302.0, 325.9"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__7) { + values ("57.3, 57.3, 57.3, 71.5, 96.5", \ + "56.1, 56.1, 56.1, 70.8, 96.7", \ + "48.2, 48.2, 48.2, 63.7, 91.0", \ + "25.9, 25.9, 25.9, 42.2, 71.5", \ + "-25.5, -25.5, -25.5, -8.2, 23.4"); + } + rise_transition (inslew_load_5x5__7) { + values ("55.5, 55.5, 55.5, 78.8, 124.6", \ + "63.4, 63.4, 63.4, 86.9, 132.9", \ + "78.1, 78.1, 78.1, 101.8, 148.2", \ + "105.9, 105.9, 105.9, 129.9, 176.9", \ + "159.9, 159.9, 159.9, 184.2, 231.9"); + } + cell_fall (inslew_load_5x5__7) { + values ("76.1, 76.1, 76.1, 90.2, 114.3", \ + "92.3, 92.3, 92.3, 107.3, 133.2", \ + "118.3, 118.3, 118.3, 134.1, 162.4", \ + "164.5, 164.5, 164.5, 181.3, 212.0", \ + "252.7, 252.7, 252.7, 270.4, 303.6"); + } + fall_transition (inslew_load_5x5__7) { + values ("47.2, 47.2, 47.2, 58.2, 78.8", \ + "61.7, 61.7, 61.7, 73.0, 94.2", \ + "88.6, 88.6, 88.6, 100.3, 122.2", \ + "140.7, 140.7, 140.7, 152.6, 175.6", \ + "243.9, 243.9, 243.9, 256.1, 279.7"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__7) { + values ("52.3, 52.3, 52.3, 66.1, 90.4", \ + "54.2, 54.2, 54.2, 68.6, 94.1", \ + "52.0, 52.0, 52.0, 67.4, 94.5", \ + "41.7, 41.7, 41.7, 58.0, 87.4", \ + "15.7, 15.7, 15.7, 33.1, 65.0"); + } + rise_transition (inslew_load_5x5__7) { + values ("49.6, 49.6, 49.6, 72.9, 118.4", \ + "58.9, 58.9, 58.9, 82.4, 128.2", \ + "75.8, 75.8, 75.8, 99.5, 145.8", \ + "107.5, 107.5, 107.5, 131.5, 178.4", \ + "169.1, 169.1, 169.1, 193.4, 241.2"); + } + cell_fall (inslew_load_5x5__7) { + values ("65.0, 65.0, 65.0, 78.5, 101.4", \ + "76.3, 76.3, 76.3, 90.9, 115.7", \ + "93.4, 93.4, 93.4, 108.8, 136.1", \ + "122.4, 122.4, 122.4, 139.0, 168.7", \ + "176.4, 176.4, 176.4, 193.9, 226.5"); + } + fall_transition (inslew_load_5x5__7) { + values ("40.2, 40.2, 40.2, 51.0, 71.2", \ + "52.6, 52.6, 52.6, 63.6, 84.5", \ + "75.3, 75.3, 75.3, 86.8, 108.4", \ + "119.4, 119.4, 119.4, 131.1, 153.9", \ + "206.5, 206.5, 206.5, 218.7, 242.1"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__7) { + values ("209.6, 209.6, 209.6, 241.1, 304.0", \ + "230.4, 230.4, 230.4, 261.9, 324.9", \ + "272.0, 272.0, 272.0, 303.4, 366.4", \ + "354.4, 354.4, 354.4, 385.9, 448.8", \ + "518.3, 518.3, 518.3, 549.8, 612.8"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("252.3, 252.3, 252.3, 283.8, 346.8", \ + "324.3, 324.3, 324.3, 355.8, 418.7", \ + "465.1, 465.1, 465.1, 496.6, 559.6", \ + "744.8, 744.8, 744.8, 776.2, 839.2", \ + "1302.9, 1302.9, 1302.9, 1334.4, 1397.4"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__7) { + values ("181.2, 181.2, 181.2, 212.7, 275.6", \ + "205.3, 205.3, 205.3, 236.8, 299.8", \ + "252.9, 252.9, 252.9, 284.4, 347.3", \ + "347.0, 347.0, 347.0, 378.5, 441.5", \ + "534.4, 534.4, 534.4, 565.8, 628.8"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("215.4, 215.4, 215.4, 246.8, 309.8", \ + "273.8, 273.8, 273.8, 305.3, 368.3", \ + "388.0, 388.0, 388.0, 419.5, 482.5", \ + "614.7, 614.7, 614.7, 646.2, 709.2", \ + "1067.1, 1067.1, 1067.1, 1098.6, 1161.6"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__7) { + values ("151.7, 151.7, 151.7, 183.2, 246.2", \ + "178.6, 178.6, 178.6, 210.1, 273.1", \ + "231.5, 231.5, 231.5, 263.0, 326.0", \ + "336.1, 336.1, 336.1, 367.6, 430.6", \ + "544.6, 544.6, 544.6, 576.1, 639.0"); + } + fall_power (energy_inslew_load_5x5__7) { + values ("177.3, 177.3, 177.3, 208.8, 271.7", \ + "225.3, 225.3, 225.3, 256.8, 319.8", \ + "319.2, 319.2, 319.2, 350.7, 413.7", \ + "505.5, 505.5, 505.5, 537.0, 600.0", \ + "877.4, 877.4, 877.4, 908.8, 971.8"); + } + } + } + } + + cell (an4v0x05) { + area : 0.0 ; + cell_leakage_power : 12 ; + leakage_power () { + when : "(d & c & b & a)" ; + value : 19 ; + } + leakage_power () { + when : "(!(a) | !(b) | !(c) | !(d))" ; + value : 4.9 ; + } + pin (d) { + direction : input ; + capacitance : 3.56 ; + } + pin (c) { + direction : input ; + capacitance : 3.31 ; + } + pin (b) { + direction : input ; + capacitance : 3.32 ; + } + pin (a) { + direction : input ; + capacitance : 3.44 ; + } + pin (z) { + function : "(a & b & c & d)" ; + direction : output ; + capacitance : 2.66 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__8) { + values ("73.4, 73.4, 73.4, 89.4, 117.6", \ + "66.1, 66.1, 66.1, 82.3, 111.0", \ + "48.5, 48.5, 48.5, 65.2, 94.8", \ + "7.0, 7.0, 7.0, 24.2, 55.2", \ + "-84.9, -84.9, -84.9, -66.9, -34.0"); + } + rise_transition (inslew_load_5x5__8) { + values ("76.3, 76.3, 76.3, 101.2, 150.0", \ + "81.5, 81.5, 81.5, 106.5, 155.4", \ + "92.4, 92.4, 92.4, 117.5, 166.6", \ + "113.6, 113.6, 113.6, 138.9, 188.4", \ + "154.8, 154.8, 154.8, 180.3, 230.5"); + } + cell_fall (inslew_load_5x5__8) { + values ("104.6, 104.6, 104.6, 120.5, 148.0", \ + "130.8, 130.8, 130.8, 147.3, 176.7", \ + "174.6, 174.6, 174.6, 192.0, 223.3", \ + "255.3, 255.3, 255.3, 273.6, 307.4", \ + "411.7, 411.7, 411.7, 430.4, 466.6"); + } + fall_transition (inslew_load_5x5__8) { + values ("67.0, 67.0, 67.0, 79.0, 101.4", \ + "86.6, 86.6, 86.6, 98.9, 121.9", \ + "123.0, 123.0, 123.0, 135.5, 159.4", \ + "193.6, 193.6, 193.6, 206.3, 231.0", \ + "333.2, 333.2, 333.2, 346.2, 371.6"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__8) { + values ("70.2, 70.2, 70.2, 85.9, 113.5", \ + "67.2, 67.2, 67.2, 83.2, 111.5", \ + "56.3, 56.3, 56.3, 72.9, 102.3", \ + "27.2, 27.2, 27.2, 44.4, 75.6", \ + "-40.0, -40.0, -40.0, -21.8, 11.5"); + } + rise_transition (inslew_load_5x5__8) { + values ("70.2, 70.2, 70.2, 95.0, 143.6", \ + "77.0, 77.0, 77.0, 102.0, 150.7", \ + "90.4, 90.4, 90.4, 115.5, 164.6", \ + "115.9, 115.9, 115.9, 141.3, 190.9", \ + "165.4, 165.4, 165.4, 191.0, 241.2"); + } + cell_fall (inslew_load_5x5__8) { + values ("94.1, 94.1, 94.1, 109.7, 136.4", \ + "114.9, 114.9, 114.9, 131.0, 159.6", \ + "148.4, 148.4, 148.4, 165.4, 196.1", \ + "208.2, 208.2, 208.2, 226.3, 259.3", \ + "322.5, 322.5, 322.5, 341.3, 376.8"); + } + fall_transition (inslew_load_5x5__8) { + values ("59.7, 59.7, 59.7, 71.5, 93.7", \ + "76.4, 76.4, 76.4, 88.5, 111.2", \ + "107.0, 107.0, 107.0, 119.4, 143.0", \ + "166.3, 166.3, 166.3, 178.9, 203.4", \ + "283.5, 283.5, 283.5, 296.5, 321.6"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__8) { + values ("64.4, 64.4, 64.4, 79.7, 106.6", \ + "64.7, 64.7, 64.7, 80.4, 108.2", \ + "58.8, 58.8, 58.8, 75.3, 104.4", \ + "39.6, 39.6, 39.6, 56.8, 87.9", \ + "-6.8, -6.8, -6.8, 11.4, 44.9"); + } + rise_transition (inslew_load_5x5__8) { + values ("63.1, 63.1, 63.1, 87.9, 136.2", \ + "71.3, 71.3, 71.3, 96.2, 144.7", \ + "86.5, 86.5, 86.5, 111.6, 160.6", \ + "115.3, 115.3, 115.3, 140.6, 190.2", \ + "171.1, 171.1, 171.1, 196.7, 247.0"); + } + cell_fall (inslew_load_5x5__8) { + values ("83.3, 83.3, 83.3, 98.4, 124.2", \ + "99.7, 99.7, 99.7, 115.6, 143.1", \ + "125.2, 125.2, 125.2, 141.9, 171.7", \ + "169.1, 169.1, 169.1, 186.9, 219.1", \ + "252.1, 252.1, 252.1, 270.7, 305.7"); + } + fall_transition (inslew_load_5x5__8) { + values ("52.4, 52.4, 52.4, 64.0, 85.8", \ + "66.9, 66.9, 66.9, 78.8, 101.3", \ + "93.4, 93.4, 93.4, 105.7, 129.0", \ + "144.8, 144.8, 144.8, 157.3, 181.6", \ + "246.2, 246.2, 246.2, 259.1, 284.0"); + } + } + timing (maxd_z_d_positive_unate) { + related_pin : "d" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__8) { + values ("56.8, 56.8, 56.8, 71.6, 97.7", \ + "59.6, 59.6, 59.6, 75.0, 102.1", \ + "57.9, 57.9, 57.9, 74.2, 102.9", \ + "47.4, 47.4, 47.4, 64.6, 95.6", \ + "19.8, 19.8, 19.8, 38.1, 71.7"); + } + rise_transition (inslew_load_5x5__8) { + values ("55.8, 55.8, 55.8, 80.4, 128.5", \ + "65.1, 65.1, 65.1, 89.9, 138.3", \ + "81.9, 81.9, 81.9, 106.9, 155.8", \ + "113.5, 113.5, 113.5, 138.8, 188.3", \ + "174.8, 174.8, 174.8, 200.4, 250.8"); + } + cell_fall (inslew_load_5x5__8) { + values ("71.1, 71.1, 71.1, 85.5, 110.1", \ + "83.6, 83.6, 83.6, 99.0, 125.5", \ + "102.0, 102.0, 102.0, 118.3, 147.3", \ + "132.7, 132.7, 132.7, 150.1, 181.6", \ + "189.5, 189.5, 189.5, 208.0, 242.3"); + } + fall_transition (inslew_load_5x5__8) { + values ("44.4, 44.4, 44.4, 55.9, 77.3", \ + "57.3, 57.3, 57.3, 69.0, 91.1", \ + "80.5, 80.5, 80.5, 92.7, 115.6", \ + "125.7, 125.7, 125.7, 138.1, 162.1", \ + "214.7, 214.7, 214.7, 227.6, 252.3"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__8) { + values ("257.3, 257.3, 257.3, 290.5, 356.9", \ + "274.7, 274.7, 274.7, 307.9, 374.3", \ + "309.8, 309.8, 309.8, 343.0, 409.4", \ + "379.9, 379.9, 379.9, 413.1, 479.5", \ + "519.2, 519.2, 519.2, 552.4, 618.8"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("304.5, 304.5, 304.5, 337.7, 404.1", \ + "382.4, 382.4, 382.4, 415.6, 482.0", \ + "534.6, 534.6, 534.6, 567.8, 634.2", \ + "836.3, 836.3, 836.3, 869.5, 935.9", \ + "1438.0, 1438.0, 1438.0, 1471.2, 1537.6"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__8) { + values ("228.1, 228.1, 228.1, 261.3, 327.7", \ + "249.1, 249.1, 249.1, 282.3, 348.7", \ + "290.9, 290.9, 290.9, 324.1, 390.5", \ + "373.6, 373.6, 373.6, 406.8, 473.2", \ + "537.9, 537.9, 537.9, 571.1, 637.5"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("265.8, 265.8, 265.8, 299.0, 365.4", \ + "330.2, 330.2, 330.2, 363.4, 429.8", \ + "455.4, 455.4, 455.4, 488.6, 555.0", \ + "703.3, 703.3, 703.3, 736.5, 802.9", \ + "1197.7, 1197.7, 1197.7, 1230.9, 1297.3"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__8) { + values ("195.3, 195.3, 195.3, 228.5, 294.9", \ + "218.8, 218.8, 218.8, 252.0, 318.4", \ + "265.0, 265.0, 265.0, 298.2, 364.6", \ + "356.2, 356.2, 356.2, 389.4, 455.8", \ + "537.5, 537.5, 537.5, 570.7, 637.1"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("228.0, 228.0, 228.0, 261.2, 327.6", \ + "282.7, 282.7, 282.7, 315.9, 382.3", \ + "388.9, 388.9, 388.9, 422.1, 488.5", \ + "599.3, 599.3, 599.3, 632.5, 698.9", \ + "1018.7, 1018.7, 1018.7, 1051.9, 1118.3"); + } + } + internal_power (energy_pos_z_d) { + related_pin : "d" ; + rise_power (energy_inslew_load_5x5__8) { + values ("162.9, 162.9, 162.9, 196.1, 262.5", \ + "188.4, 188.4, 188.4, 221.6, 288.0", \ + "238.0, 238.0, 238.0, 271.2, 337.6", \ + "336.1, 336.1, 336.1, 369.3, 435.7", \ + "531.3, 531.3, 531.3, 564.5, 630.9"); + } + fall_power (energy_inslew_load_5x5__8) { + values ("188.1, 188.1, 188.1, 221.3, 287.7", \ + "235.2, 235.2, 235.2, 268.4, 334.8", \ + "326.7, 326.7, 326.7, 359.9, 426.3", \ + "507.8, 507.8, 507.8, 541.0, 607.4", \ + "869.1, 869.1, 869.1, 902.3, 968.8"); + } + } + } + } + + cell (aoi112v0x05) { + area : 0.0 ; + cell_leakage_power : 1.3 ; + leakage_power () { + when : "(!(c2) & !(c1) & !(b) & a)" ; + value : 1.1 ; + } + leakage_power () { + when : "(b & c1 & c2)" ; + value : 2.9 ; + } + leakage_power () { + when : "(b & (c1 ^ c2))" ; + value : 2.1 ; + } + leakage_power () { + when : "((a & (b ^ (c1 | c2))) | (b & !(c1) & !(c2)))" ; + value : 1.2 ; + } + leakage_power () { + when : "(c2 & c1 & !(b) & !(a))" ; + value : 3 ; + } + leakage_power () { + when : "(!(c2) & c1 & !(b) & !(a))" ; + value : 0.00012 ; + } + leakage_power () { + when : "(c2 & !(c1) & !(b) & !(a))" ; + value : 0.00011 ; + } + leakage_power () { + when : "(!(c2) & !(c1) & !(b) & !(a))" ; + value : 6.8e-05 ; + } + pin (c2) { + direction : input ; + capacitance : 4.95 ; + } + pin (c1) { + direction : input ; + capacitance : 4.56 ; + } + pin (b) { + direction : input ; + capacitance : 4.65 ; + } + pin (a) { + direction : input ; + capacitance : 4.12 ; + } + pin (z) { + function : "(((!(c2) & !(b)) & !(a)) | ((!(c1) & !(b)) & !(a)))" ; + direction : output ; + capacitance : 4.97 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__9) { + values ("105.9, 105.9, 105.9, 137.9, 201.8", \ + "100.9, 100.9, 100.9, 133.3, 197.8", \ + "90.1, 90.1, 90.1, 122.9, 188.0", \ + "69.5, 69.5, 69.5, 102.6, 168.2", \ + "26.5, 26.5, 26.5, 60.5, 127.5"); + } + rise_transition (inslew_load_5x5__9) { + values ("195.6, 195.6, 195.6, 250.2, 360.2", \ + "221.2, 221.2, 221.2, 275.6, 384.9", \ + "268.9, 268.9, 268.9, 323.3, 432.6", \ + "366.0, 366.0, 366.0, 419.4, 527.1", \ + "563.8, 563.8, 563.8, 616.0, 721.4"); + } + cell_fall (inslew_load_5x5__9) { + values ("58.7, 58.7, 58.7, 75.8, 108.7", \ + "76.1, 76.1, 76.1, 95.0, 130.4", \ + "103.3, 103.3, 103.3, 124.3, 163.6", \ + "151.5, 151.5, 151.5, 174.4, 217.9", \ + "243.4, 243.4, 243.4, 267.8, 314.8"); + } + fall_transition (inslew_load_5x5__9) { + values ("61.7, 61.7, 61.7, 81.3, 120.9", \ + "90.1, 90.1, 90.1, 109.5, 148.2", \ + "142.6, 142.6, 142.6, 162.4, 201.2", \ + "244.5, 244.5, 244.5, 264.7, 304.4", \ + "446.1, 446.1, 446.1, 466.7, 507.3"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__9) { + values ("84.1, 84.1, 84.1, 116.5, 180.9", \ + "88.0, 88.0, 88.0, 121.0, 186.0", \ + "92.8, 92.8, 92.8, 126.8, 193.4", \ + "100.2, 100.2, 100.2, 135.6, 204.3", \ + "111.8, 111.8, 111.8, 148.8, 220.6"); + } + rise_transition (inslew_load_5x5__9) { + values ("150.4, 150.4, 150.4, 205.6, 317.1", \ + "181.2, 181.2, 181.2, 235.7, 346.2", \ + "240.9, 240.9, 240.9, 294.5, 403.0", \ + "359.2, 359.2, 359.2, 413.9, 520.0", \ + "596.8, 596.8, 596.8, 649.9, 756.0"); + } + cell_fall (inslew_load_5x5__9) { + values ("50.2, 50.2, 50.2, 67.9, 101.2", \ + "59.2, 59.2, 59.2, 79.3, 116.1", \ + "69.6, 69.6, 69.6, 92.8, 134.9", \ + "83.2, 83.2, 83.2, 109.5, 157.9", \ + "105.1, 105.1, 105.1, 133.8, 187.9"); + } + fall_transition (inslew_load_5x5__9) { + values ("52.8, 52.8, 52.8, 72.3, 111.8", \ + "74.1, 74.1, 74.1, 93.7, 132.3", \ + "113.0, 113.0, 113.0, 133.4, 172.8", \ + "187.8, 187.8, 187.8, 209.1, 250.3", \ + "334.7, 334.7, 334.7, 356.9, 400.1"); + } + } + timing (maxd_z_c1_negative_unate) { + related_pin : "c1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__9) { + values ("56.6, 56.6, 56.6, 90.0, 155.2", \ + "73.2, 73.2, 73.2, 107.9, 174.2", \ + "107.5, 107.5, 107.5, 143.1, 211.6", \ + "173.1, 173.1, 173.1, 209.5, 280.5", \ + "301.6, 301.6, 301.6, 338.4, 411.6"); + } + rise_transition (inslew_load_5x5__9) { + values ("100.6, 100.6, 100.6, 156.3, 269.3", \ + "147.5, 147.5, 147.5, 202.6, 314.3", \ + "241.4, 241.4, 241.4, 296.7, 406.2", \ + "426.7, 426.7, 426.7, 480.5, 591.2", \ + "794.5, 794.5, 794.5, 847.8, 955.9"); + } + cell_fall (inslew_load_5x5__9) { + values ("27.1, 27.1, 27.1, 43.6, 74.1", \ + "22.0, 22.0, 22.0, 40.9, 74.3", \ + "7.5, 7.5, 7.5, 29.6, 68.1", \ + "-26.1, -26.1, -26.1, -0.6, 44.5", \ + "-97.6, -97.6, -97.6, -69.1, -17.2"); + } + fall_transition (inslew_load_5x5__9) { + values ("40.3, 40.3, 40.3, 60.2, 99.9", \ + "52.1, 52.1, 52.1, 72.2, 111.7", \ + "74.0, 74.0, 74.0, 94.9, 135.0", \ + "116.4, 116.4, 116.4, 138.3, 180.2", \ + "199.5, 199.5, 199.5, 222.4, 266.5"); + } + } + timing (maxd_z_c2_negative_unate) { + related_pin : "c2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__9) { + values ("45.1, 45.1, 45.1, 79.1, 144.4", \ + "55.6, 55.6, 55.6, 90.7, 157.8", \ + "79.0, 79.0, 79.0, 114.3, 184.1", \ + "120.3, 120.3, 120.3, 158.1, 230.3", \ + "199.6, 199.6, 199.6, 239.0, 315.1"); + } + rise_transition (inslew_load_5x5__9) { + values ("82.3, 82.3, 82.3, 137.8, 250.5", \ + "120.8, 120.8, 120.8, 175.0, 286.3", \ + "199.6, 199.6, 199.6, 251.6, 361.6", \ + "351.5, 351.5, 351.5, 404.9, 511.9", \ + "651.8, 651.8, 651.8, 706.2, 814.0"); + } + cell_fall (inslew_load_5x5__9) { + values ("25.6, 25.6, 25.6, 43.9, 75.8", \ + "24.0, 24.0, 24.0, 45.7, 82.1", \ + "16.2, 16.2, 16.2, 41.7, 84.9", \ + "-3.6, -3.6, -3.6, 25.5, 76.4", \ + "-46.5, -46.5, -46.5, -14.5, 43.6"); + } + fall_transition (inslew_load_5x5__9) { + values ("33.9, 33.9, 33.9, 54.1, 94.0", \ + "48.1, 48.1, 48.1, 69.1, 109.2", \ + "74.1, 74.1, 74.1, 96.3, 138.1", \ + "124.1, 124.1, 124.1, 147.6, 191.9", \ + "222.8, 222.8, 222.8, 247.2, 294.1"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__9) { + values ("216.4, 216.4, 216.4, 278.6, 402.9", \ + "241.7, 241.7, 241.7, 303.9, 428.2", \ + "292.3, 292.3, 292.3, 354.4, 478.8", \ + "393.4, 393.4, 393.4, 455.6, 580.0", \ + "595.7, 595.7, 595.7, 657.9, 782.3"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("189.5, 189.5, 189.5, 251.7, 376.1", \ + "238.7, 238.7, 238.7, 300.9, 425.3", \ + "337.1, 337.1, 337.1, 399.3, 523.7", \ + "534.0, 534.0, 534.0, 596.2, 720.5", \ + "927.6, 927.6, 927.6, 989.8, 1114.2"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__9) { + values ("166.1, 166.1, 166.1, 228.3, 352.6", \ + "194.4, 194.4, 194.4, 256.5, 380.9", \ + "250.9, 250.9, 250.9, 313.1, 437.5", \ + "364.0, 364.0, 364.0, 426.2, 550.6", \ + "590.2, 590.2, 590.2, 652.4, 776.8"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("150.9, 150.9, 150.9, 213.1, 337.4", \ + "180.9, 180.9, 180.9, 243.1, 367.5", \ + "241.0, 241.0, 241.0, 303.2, 427.6", \ + "361.2, 361.2, 361.2, 423.4, 547.7", \ + "601.5, 601.5, 601.5, 663.7, 788.1"); + } + } + internal_power (energy_neg_z_c1) { + related_pin : "c1" ; + rise_power (energy_inslew_load_5x5__9) { + values ("118.2, 118.2, 118.2, 180.4, 304.8", \ + "161.9, 161.9, 161.9, 224.1, 348.5", \ + "249.4, 249.4, 249.4, 311.6, 436.0", \ + "424.4, 424.4, 424.4, 486.5, 610.9", \ + "774.2, 774.2, 774.2, 836.4, 960.8"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("104.7, 104.7, 104.7, 166.9, 291.3", \ + "121.6, 121.6, 121.6, 183.8, 308.2", \ + "155.5, 155.5, 155.5, 217.7, 342.0", \ + "223.2, 223.2, 223.2, 285.4, 409.7", \ + "358.6, 358.6, 358.6, 420.8, 545.1"); + } + } + internal_power (energy_neg_z_c2) { + related_pin : "c2" ; + rise_power (energy_inslew_load_5x5__9) { + values ("94.3, 94.3, 94.3, 156.5, 280.9", \ + "128.7, 128.7, 128.7, 190.9, 315.2", \ + "197.4, 197.4, 197.4, 259.5, 383.9", \ + "334.7, 334.7, 334.7, 396.9, 521.3", \ + "609.5, 609.5, 609.5, 671.7, 796.0"); + } + fall_power (energy_inslew_load_5x5__9) { + values ("83.3, 83.3, 83.3, 145.5, 269.8", \ + "102.2, 102.2, 102.2, 164.4, 288.7", \ + "140.0, 140.0, 140.0, 202.2, 326.5", \ + "215.6, 215.6, 215.6, 277.8, 402.1", \ + "366.8, 366.8, 366.8, 429.0, 553.3"); + } + } + } + } + + cell (aoi211v0x05) { + area : 0.0 ; + cell_leakage_power : 1.3 ; + leakage_power () { + when : "(!(c) & !(b) & a2 & a1)" ; + value : 1.1 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a2) & a1)" ; + value : 0.00012 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(b) & c)" ; + value : 2.1 ; + } + leakage_power () { + when : "(!(c) & !(b) & a2 & !(a1))" ; + value : 0.00011 ; + } + leakage_power () { + when : "(b & c)" ; + value : 2.9 ; + } + leakage_power () { + when : "((a1 & a2 & (b ^ c)) | (b & !(c)))" ; + value : 1.2 ; + } + leakage_power () { + when : "(c & !(b) & !(a2) & !(a1))" ; + value : 3 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a2) & !(a1))" ; + value : 6.8e-05 ; + } + pin (c) { + direction : input ; + capacitance : 4.28 ; + } + pin (b) { + direction : input ; + capacitance : 4.25 ; + } + pin (a2) { + direction : input ; + capacitance : 4.60 ; + } + pin (a1) { + direction : input ; + capacitance : 4.46 ; + } + pin (z) { + function : "(((!(c) & !(b)) & !(a1)) | ((!(c) & !(b)) & !(a2)))" ; + direction : output ; + capacitance : 4.60 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("118.3, 118.3, 118.3, 147.8, 206.9", \ + "124.3, 124.3, 124.3, 154.2, 213.6", \ + "134.3, 134.3, 134.3, 164.4, 224.3", \ + "154.7, 154.7, 154.7, 184.8, 244.9", \ + "196.5, 196.5, 196.5, 226.7, 286.9"); + } + rise_transition (inslew_load_5x5__10) { + values ("214.3, 214.3, 214.3, 264.9, 366.6", \ + "258.4, 258.4, 258.4, 308.7, 409.7", \ + "340.7, 340.7, 340.7, 391.1, 492.2", \ + "503.5, 503.5, 503.5, 553.3, 653.9", \ + "830.2, 830.2, 830.2, 879.6, 978.9"); + } + cell_fall (inslew_load_5x5__10) { + values ("43.2, 43.2, 43.2, 57.4, 84.9", \ + "49.7, 49.7, 49.7, 65.0, 94.0", \ + "58.9, 58.9, 58.9, 75.5, 107.0", \ + "74.2, 74.2, 74.2, 92.1, 126.4", \ + "102.4, 102.4, 102.4, 121.3, 157.9"); + } + fall_transition (inslew_load_5x5__10) { + values ("59.2, 59.2, 59.2, 77.5, 114.6", \ + "81.6, 81.6, 81.6, 99.8, 136.3", \ + "124.7, 124.7, 124.7, 143.0, 179.3", \ + "209.5, 209.5, 209.5, 228.0, 264.7", \ + "378.3, 378.3, 378.3, 397.0, 434.1"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("105.2, 105.2, 105.2, 134.8, 193.9", \ + "104.0, 104.0, 104.0, 134.0, 193.6", \ + "100.1, 100.1, 100.1, 130.4, 190.6", \ + "93.4, 93.4, 93.4, 123.9, 184.4", \ + "79.4, 79.4, 79.4, 110.3, 172.5"); + } + rise_transition (inslew_load_5x5__10) { + values ("192.2, 192.2, 192.2, 242.7, 344.2", \ + "224.5, 224.5, 224.5, 274.8, 375.6", \ + "284.1, 284.1, 284.1, 334.4, 435.4", \ + "403.5, 403.5, 403.5, 453.0, 552.6", \ + "644.6, 644.6, 644.6, 693.3, 791.3"); + } + cell_fall (inslew_load_5x5__10) { + values ("42.0, 42.0, 42.0, 57.3, 85.7", \ + "54.1, 54.1, 54.1, 70.9, 101.9", \ + "73.0, 73.0, 73.0, 91.5, 125.9", \ + "107.0, 107.0, 107.0, 126.9, 164.7", \ + "172.2, 172.2, 172.2, 193.2, 233.8"); + } + fall_transition (inslew_load_5x5__10) { + values ("51.4, 51.4, 51.4, 69.9, 107.0", \ + "77.5, 77.5, 77.5, 96.0, 132.7", \ + "125.9, 125.9, 125.9, 144.8, 181.9", \ + "220.3, 220.3, 220.3, 239.6, 277.5", \ + "407.6, 407.6, 407.6, 427.2, 465.8"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("73.8, 73.8, 73.8, 103.9, 163.5", \ + "77.3, 77.3, 77.3, 108.0, 168.3", \ + "81.8, 81.8, 81.8, 113.5, 175.3", \ + "88.7, 88.7, 88.7, 121.7, 185.7", \ + "100.2, 100.2, 100.2, 134.4, 201.2"); + } + rise_transition (inslew_load_5x5__10) { + values ("134.3, 134.3, 134.3, 185.2, 288.1", \ + "164.9, 164.9, 164.9, 215.3, 317.1", \ + "224.8, 224.8, 224.8, 274.2, 374.1", \ + "343.1, 343.1, 343.1, 393.9, 491.7", \ + "581.0, 581.0, 581.0, 629.7, 727.8"); + } + cell_fall (inslew_load_5x5__10) { + values ("40.8, 40.8, 40.8, 58.0, 89.5", \ + "48.5, 48.5, 48.5, 68.2, 103.4", \ + "57.3, 57.3, 57.3, 79.9, 120.4", \ + "69.7, 69.7, 69.7, 94.9, 141.2", \ + "90.7, 90.7, 90.7, 117.9, 169.1"); + } + fall_transition (inslew_load_5x5__10) { + values ("43.5, 43.5, 43.5, 61.5, 97.7", \ + "64.5, 64.5, 64.5, 82.9, 118.7", \ + "103.0, 103.0, 103.0, 122.2, 159.0", \ + "177.3, 177.3, 177.3, 197.3, 235.9", \ + "323.9, 323.9, 323.9, 344.6, 385.0"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__10) { + values ("42.6, 42.6, 42.6, 74.2, 134.7", \ + "49.8, 49.8, 49.8, 82.7, 145.3", \ + "66.1, 66.1, 66.1, 99.5, 165.0", \ + "92.7, 92.7, 92.7, 129.2, 198.0", \ + "143.1, 143.1, 143.1, 181.2, 254.3"); + } + rise_transition (inslew_load_5x5__10) { + values ("78.9, 78.9, 78.9, 129.9, 233.9", \ + "111.5, 111.5, 111.5, 161.9, 264.3", \ + "181.0, 181.0, 181.0, 228.9, 330.4", \ + "313.3, 313.3, 313.3, 363.5, 462.9", \ + "576.0, 576.0, 576.0, 626.6, 727.2"); + } + cell_fall (inslew_load_5x5__10) { + values ("27.7, 27.7, 27.7, 46.7, 79.3", \ + "28.8, 28.8, 28.8, 51.2, 88.7", \ + "26.0, 26.0, 26.0, 52.1, 96.4", \ + "16.2, 16.2, 16.2, 45.6, 97.5", \ + "-6.2, -6.2, -6.2, 25.6, 84.2"); + } + fall_transition (inslew_load_5x5__10) { + values ("31.5, 31.5, 31.5, 49.8, 85.8", \ + "48.2, 48.2, 48.2, 67.3, 103.4", \ + "78.6, 78.6, 78.6, 99.0, 137.0", \ + "137.2, 137.2, 137.2, 158.9, 199.5", \ + "252.7, 252.7, 252.7, 275.4, 318.7"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__10) { + values ("240.8, 240.8, 240.8, 298.2, 413.2", \ + "285.3, 285.3, 285.3, 342.8, 457.7", \ + "374.5, 374.5, 374.5, 431.9, 546.9", \ + "552.8, 552.8, 552.8, 610.2, 725.2", \ + "909.3, 909.3, 909.3, 966.8, 1081.7"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("173.5, 173.5, 173.5, 231.0, 345.9", \ + "220.8, 220.8, 220.8, 278.3, 393.2", \ + "315.4, 315.4, 315.4, 372.9, 487.8", \ + "504.6, 504.6, 504.6, 562.0, 677.0", \ + "882.9, 882.9, 882.9, 940.4, 1055.3"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__10) { + values ("213.6, 213.6, 213.6, 271.0, 386.0", \ + "245.4, 245.4, 245.4, 302.9, 417.8", \ + "309.0, 309.0, 309.0, 366.5, 481.4", \ + "436.4, 436.4, 436.4, 493.8, 608.8", \ + "691.0, 691.0, 691.0, 748.5, 863.4"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("151.4, 151.4, 151.4, 208.9, 323.8", \ + "200.0, 200.0, 200.0, 257.5, 372.4", \ + "297.2, 297.2, 297.2, 354.7, 469.6", \ + "491.6, 491.6, 491.6, 549.0, 664.0", \ + "880.3, 880.3, 880.3, 937.8, 1052.7"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__10) { + values ("147.6, 147.6, 147.6, 205.1, 320.0", \ + "175.9, 175.9, 175.9, 233.4, 348.3", \ + "232.4, 232.4, 232.4, 289.9, 404.8", \ + "345.5, 345.5, 345.5, 403.0, 517.9", \ + "571.7, 571.7, 571.7, 629.2, 744.1"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("121.0, 121.0, 121.0, 178.4, 293.4", \ + "151.0, 151.0, 151.0, 208.5, 323.4", \ + "211.1, 211.1, 211.1, 268.6, 383.5", \ + "331.3, 331.3, 331.3, 388.7, 503.7", \ + "571.6, 571.6, 571.6, 629.1, 744.0"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__10) { + values ("86.3, 86.3, 86.3, 143.8, 258.7", \ + "115.4, 115.4, 115.4, 172.9, 287.8", \ + "173.5, 173.5, 173.5, 231.0, 345.9", \ + "289.8, 289.8, 289.8, 347.2, 462.2", \ + "522.3, 522.3, 522.3, 579.7, 694.7"); + } + fall_power (energy_inslew_load_5x5__10) { + values ("78.1, 78.1, 78.1, 135.5, 250.5", \ + "98.4, 98.4, 98.4, 155.9, 270.8", \ + "139.2, 139.2, 139.2, 196.7, 311.6", \ + "220.7, 220.7, 220.7, 278.2, 393.1", \ + "383.8, 383.8, 383.8, 441.3, 556.2"); + } + } + } + } + + cell (aoi211v0x1) { + area : 0.0 ; + cell_leakage_power : 4.6 ; + leakage_power () { + when : "(c & b & a2 & a1)" ; + value : 14 ; + } + leakage_power () { + when : "(a1 & a2 & (b ^ c))" ; + value : 5.1 ; + } + leakage_power () { + when : "(!(c) & !(b) & a2 & a1)" ; + value : 4.6 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a2) & a1)" ; + value : 0.00018 ; + } + leakage_power () { + when : "((a1 ^ a2) & b & c)" ; + value : 9.8 ; + } + leakage_power () { + when : "((a1 ^ a2) & b & !(c))" ; + value : 3.8 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(b) & c)" ; + value : 5.5 ; + } + leakage_power () { + when : "(!(c) & !(b) & a2 & !(a1))" ; + value : 0.00016 ; + } + leakage_power () { + when : "(!(c) & b & !(a2) & !(a1))" ; + value : 2.5 ; + } + leakage_power () { + when : "(!(a1) & !(a2) & c)" ; + value : 5.9 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a2) & !(a1))" ; + value : 9.5e-05 ; + } + pin (c) { + direction : input ; + capacitance : 7.43 ; + } + pin (b) { + direction : input ; + capacitance : 7.90 ; + } + pin (a2) { + direction : input ; + capacitance : 8.82 ; + } + pin (a1) { + direction : input ; + capacitance : 8.14 ; + } + pin (z) { + function : "(((!(c) & !(b)) & !(a1)) | ((!(c) & !(b)) & !(a2)))" ; + direction : output ; + capacitance : 6.63 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("109.3, 109.3, 109.3, 130.5, 173.1", \ + "112.9, 112.9, 112.9, 134.4, 177.4", \ + "118.4, 118.4, 118.4, 140.1, 183.5", \ + "130.4, 130.4, 130.4, 152.1, 195.5", \ + "155.1, 155.1, 155.1, 176.9, 220.5"); + } + rise_transition (inslew_load_5x5__11) { + values ("199.1, 199.1, 199.1, 235.5, 308.6", \ + "239.3, 239.3, 239.3, 275.6, 348.2", \ + "314.4, 314.4, 314.4, 350.7, 423.5", \ + "463.5, 463.5, 463.5, 499.4, 571.3", \ + "763.1, 763.1, 763.1, 798.5, 869.7"); + } + cell_fall (inslew_load_5x5__11) { + values ("42.9, 42.9, 42.9, 54.0, 75.6", \ + "50.8, 50.8, 50.8, 62.7, 85.6", \ + "62.9, 62.9, 62.9, 75.8, 100.5", \ + "84.2, 84.2, 84.2, 98.0, 124.6", \ + "124.8, 124.8, 124.8, 139.3, 167.5"); + } + fall_transition (inslew_load_5x5__11) { + values ("57.9, 57.9, 57.9, 72.2, 101.0", \ + "81.9, 81.9, 81.9, 96.2, 124.7", \ + "127.7, 127.7, 127.7, 142.0, 170.4", \ + "217.9, 217.9, 217.9, 232.3, 260.9", \ + "397.2, 397.2, 397.2, 411.7, 440.6"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("97.2, 97.2, 97.2, 118.5, 161.1", \ + "94.0, 94.0, 94.0, 115.7, 158.9", \ + "86.8, 86.8, 86.8, 108.7, 152.3", \ + "73.5, 73.5, 73.5, 95.6, 139.4", \ + "45.7, 45.7, 45.7, 68.3, 112.9"); + } + rise_transition (inslew_load_5x5__11) { + values ("178.8, 178.8, 178.8, 215.1, 288.1", \ + "208.2, 208.2, 208.2, 244.4, 317.0", \ + "262.4, 262.4, 262.4, 298.6, 371.2", \ + "371.6, 371.6, 371.6, 407.1, 478.6", \ + "592.5, 592.5, 592.5, 627.4, 697.6"); + } + cell_fall (inslew_load_5x5__11) { + values ("41.1, 41.1, 41.1, 53.1, 75.6", \ + "54.7, 54.7, 54.7, 67.8, 92.4", \ + "76.6, 76.6, 76.6, 90.9, 118.1", \ + "116.5, 116.5, 116.5, 131.9, 161.4", \ + "194.1, 194.1, 194.1, 210.2, 241.5"); + } + fall_transition (inslew_load_5x5__11) { + values ("49.4, 49.4, 49.4, 63.9, 92.8", \ + "77.0, 77.0, 77.0, 91.6, 120.3", \ + "128.0, 128.0, 128.0, 142.8, 171.9", \ + "227.4, 227.4, 227.4, 242.4, 272.1", \ + "424.6, 424.6, 424.6, 439.7, 469.8"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("62.8, 62.8, 62.8, 84.6, 127.7", \ + "62.9, 62.9, 62.9, 85.5, 129.4", \ + "61.7, 61.7, 61.7, 85.1, 130.4", \ + "56.8, 56.8, 56.8, 81.3, 128.9", \ + "44.3, 44.3, 44.3, 70.1, 120.0"); + } + rise_transition (inslew_load_5x5__11) { + values ("116.9, 116.9, 116.9, 153.5, 227.3", \ + "143.2, 143.2, 143.2, 179.3, 252.2", \ + "195.3, 195.3, 195.3, 230.6, 302.0", \ + "297.6, 297.6, 297.6, 332.9, 405.4", \ + "503.8, 503.8, 503.8, 539.3, 609.7"); + } + cell_fall (inslew_load_5x5__11) { + values ("40.2, 40.2, 40.2, 54.8, 81.4", \ + "50.4, 50.4, 50.4, 66.9, 96.7", \ + "64.4, 64.4, 64.4, 83.0, 116.9", \ + "87.3, 87.3, 87.3, 107.7, 145.9", \ + "129.8, 129.8, 129.8, 151.6, 193.1"); + } + fall_transition (inslew_load_5x5__11) { + values ("40.1, 40.1, 40.1, 54.8, 84.0", \ + "62.9, 62.9, 62.9, 77.9, 106.9", \ + "104.5, 104.5, 104.5, 120.0, 149.9", \ + "184.8, 184.8, 184.8, 200.8, 232.0", \ + "343.4, 343.4, 343.4, 359.9, 392.2"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__11) { + values ("30.9, 30.9, 30.9, 54.6, 98.8", \ + "36.0, 36.0, 36.0, 59.0, 105.4", \ + "44.0, 44.0, 44.0, 70.2, 117.9", \ + "56.9, 56.9, 56.9, 84.8, 137.4", \ + "80.7, 80.7, 80.7, 109.8, 165.8"); + } + rise_transition (inslew_load_5x5__11) { + values ("61.9, 61.9, 61.9, 98.5, 172.7", \ + "92.4, 92.4, 92.4, 126.3, 199.2", \ + "151.3, 151.3, 151.3, 187.3, 257.3", \ + "266.8, 266.8, 266.8, 303.4, 375.7", \ + "496.2, 496.2, 496.2, 533.2, 606.6"); + } + cell_fall (inslew_load_5x5__11) { + values ("25.0, 25.0, 25.0, 41.7, 69.7", \ + "28.2, 28.2, 28.2, 47.5, 79.8", \ + "30.0, 30.0, 30.0, 51.9, 89.7", \ + "30.3, 30.3, 30.3, 54.4, 97.6", \ + "28.8, 28.8, 28.8, 54.4, 102.1"); + } + fall_transition (inslew_load_5x5__11) { + values ("26.8, 26.8, 26.8, 41.9, 71.0", \ + "45.0, 45.0, 45.0, 60.8, 90.3", \ + "78.2, 78.2, 78.2, 94.9, 126.0", \ + "142.4, 142.4, 142.4, 159.9, 192.9", \ + "269.4, 269.4, 269.4, 287.4, 322.2"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__11) { + values ("445.4, 445.4, 445.4, 528.3, 693.9", \ + "526.5, 526.5, 526.5, 609.4, 775.0", \ + "688.7, 688.7, 688.7, 771.6, 937.2", \ + "1013.1, 1013.1, 1013.1, 1095.9, 1261.6", \ + "1661.9, 1661.9, 1661.9, 1744.7, 1910.3"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("319.2, 319.2, 319.2, 402.0, 567.7", \ + "414.3, 414.3, 414.3, 497.1, 662.8", \ + "604.4, 604.4, 604.4, 687.3, 852.9", \ + "984.8, 984.8, 984.8, 1067.6, 1233.3", \ + "1745.5, 1745.5, 1745.5, 1828.3, 1994.0"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__11) { + values ("395.6, 395.6, 395.6, 478.4, 644.0", \ + "453.1, 453.1, 453.1, 535.9, 701.6", \ + "568.1, 568.1, 568.1, 651.0, 816.6", \ + "798.3, 798.3, 798.3, 881.1, 1046.7", \ + "1258.5, 1258.5, 1258.5, 1341.3, 1507.0"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("277.4, 277.4, 277.4, 360.3, 525.9", \ + "374.1, 374.1, 374.1, 456.9, 622.6", \ + "567.4, 567.4, 567.4, 650.3, 815.9", \ + "954.1, 954.1, 954.1, 1036.9, 1202.6", \ + "1727.4, 1727.4, 1727.4, 1810.2, 1975.9"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__11) { + values ("253.4, 253.4, 253.4, 336.3, 501.9", \ + "300.8, 300.8, 300.8, 383.6, 549.2", \ + "395.4, 395.4, 395.4, 478.2, 643.9", \ + "584.6, 584.6, 584.6, 667.5, 833.1", \ + "963.2, 963.2, 963.2, 1046.0, 1211.6"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("211.1, 211.1, 211.1, 293.9, 459.6", \ + "270.5, 270.5, 270.5, 353.3, 519.0", \ + "389.4, 389.4, 389.4, 472.2, 637.9", \ + "627.1, 627.1, 627.1, 710.0, 875.6", \ + "1102.6, 1102.6, 1102.6, 1185.5, 1351.1"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__11) { + values ("130.9, 130.9, 130.9, 213.7, 379.4", \ + "179.9, 179.9, 179.9, 262.7, 428.3", \ + "277.8, 277.8, 277.8, 360.6, 526.2", \ + "473.6, 473.6, 473.6, 556.4, 722.0", \ + "865.1, 865.1, 865.1, 948.0, 1113.6"); + } + fall_power (energy_inslew_load_5x5__11) { + values ("125.0, 125.0, 125.0, 207.9, 373.5", \ + "166.4, 166.4, 166.4, 249.2, 414.9", \ + "249.1, 249.1, 249.1, 331.9, 497.6", \ + "414.5, 414.5, 414.5, 497.4, 663.0", \ + "745.4, 745.4, 745.4, 828.2, 993.9"); + } + } + } + } + + cell (aoi211v0x2) { + area : 0.0 ; + cell_leakage_power : 22 ; + leakage_power () { + when : "(c & b & a2 & a1)" ; + value : 90 ; + } + leakage_power () { + when : "(a1 & a2 & (b ^ c))" ; + value : 27 ; + } + leakage_power () { + when : "(!(c) & !(b) & a2 & a1)" ; + value : 24 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a2) & a1)" ; + value : 0.00039 ; + } + leakage_power () { + when : "((a1 ^ a2) & b & c)" ; + value : 51 ; + } + leakage_power () { + when : "((a1 ^ a2) & b & !(c))" ; + value : 16 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(b) & c)" ; + value : 20 ; + } + leakage_power () { + when : "(!(c) & !(b) & a2 & !(a1))" ; + value : 0.00036 ; + } + leakage_power () { + when : "(!(c) & b & !(a2) & !(a1))" ; + value : 5 ; + } + leakage_power () { + when : "(!(a1) & !(a2) & c)" ; + value : 12 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a2) & !(a1))" ; + value : 0.00022 ; + } + pin (c) { + direction : input ; + capacitance : 14.70 ; + } + pin (b) { + direction : input ; + capacitance : 15.14 ; + } + pin (a2) { + direction : input ; + capacitance : 16.21 ; + } + pin (a1) { + direction : input ; + capacitance : 16.77 ; + } + pin (z) { + function : "(((!(c) & !(b)) & !(a1)) | ((!(c) & !(b)) & !(a2)))" ; + direction : output ; + capacitance : 12.30 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("107.9, 107.9, 107.9, 127.6, 167.0", \ + "111.5, 111.5, 111.5, 131.4, 171.3", \ + "117.0, 117.0, 117.0, 137.1, 177.4", \ + "129.0, 129.0, 129.0, 149.1, 189.4", \ + "153.6, 153.6, 153.6, 173.9, 214.4"); + } + rise_transition (inslew_load_5x5__12) { + values ("196.7, 196.7, 196.7, 230.4, 298.2", \ + "237.0, 237.0, 237.0, 270.6, 338.0", \ + "312.0, 312.0, 312.0, 345.7, 413.2", \ + "461.1, 461.1, 461.1, 494.4, 561.1", \ + "760.8, 760.8, 760.8, 793.6, 859.6"); + } + cell_fall (inslew_load_5x5__12) { + values ("42.2, 42.2, 42.2, 52.4, 72.5", \ + "50.0, 50.0, 50.0, 61.0, 82.3", \ + "62.0, 62.0, 62.0, 74.0, 97.0", \ + "83.2, 83.2, 83.2, 96.1, 120.9", \ + "123.8, 123.8, 123.8, 137.3, 163.5"); + } + fall_transition (inslew_load_5x5__12) { + values ("56.9, 56.9, 56.9, 70.2, 96.9", \ + "80.9, 80.9, 80.9, 94.2, 120.7", \ + "126.7, 126.7, 126.7, 140.0, 166.3", \ + "216.9, 216.9, 216.9, 230.2, 256.8", \ + "396.2, 396.2, 396.2, 409.6, 436.5"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("94.1, 94.1, 94.1, 113.7, 152.8", \ + "90.2, 90.2, 90.2, 110.2, 149.8", \ + "81.7, 81.7, 81.7, 101.8, 141.8", \ + "66.0, 66.0, 66.0, 86.2, 126.5", \ + "33.3, 33.3, 33.3, 54.0, 95.1"); + } + rise_transition (inslew_load_5x5__12) { + values ("174.3, 174.3, 174.3, 207.6, 274.6", \ + "202.9, 202.9, 202.9, 236.2, 302.8", \ + "255.6, 255.6, 255.6, 288.9, 355.6", \ + "362.1, 362.1, 362.1, 394.7, 460.4", \ + "577.7, 577.7, 577.7, 609.7, 674.1"); + } + cell_fall (inslew_load_5x5__12) { + values ("40.5, 40.5, 40.5, 51.7, 72.7", \ + "54.7, 54.7, 54.7, 66.9, 89.8", \ + "77.9, 77.9, 77.9, 91.2, 116.4", \ + "120.5, 120.5, 120.5, 134.7, 162.0", \ + "203.7, 203.7, 203.7, 218.5, 247.3"); + } + fall_transition (inslew_load_5x5__12) { + values ("48.6, 48.6, 48.6, 62.1, 88.9", \ + "77.0, 77.0, 77.0, 90.5, 117.2", \ + "129.3, 129.3, 129.3, 143.1, 170.1", \ + "231.3, 231.3, 231.3, 245.2, 272.7", \ + "433.7, 433.7, 433.7, 447.7, 475.5"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("61.6, 61.6, 61.6, 81.9, 122.0", \ + "62.3, 62.3, 62.3, 83.3, 124.1", \ + "62.2, 62.2, 62.2, 84.0, 126.1", \ + "59.8, 59.8, 59.8, 82.6, 126.8", \ + "52.6, 52.6, 52.6, 76.4, 122.6"); + } + rise_transition (inslew_load_5x5__12) { + values ("115.0, 115.0, 115.0, 148.9, 217.3", \ + "142.2, 142.2, 142.2, 175.7, 243.3", \ + "196.1, 196.1, 196.1, 228.9, 295.1", \ + "301.9, 301.9, 301.9, 334.7, 402.1", \ + "515.2, 515.2, 515.2, 548.0, 613.3"); + } + cell_fall (inslew_load_5x5__12) { + values ("37.7, 37.7, 37.7, 50.9, 75.0", \ + "47.1, 47.1, 47.1, 62.1, 89.2", \ + "59.8, 59.8, 59.8, 76.8, 107.7", \ + "80.8, 80.8, 80.8, 99.3, 134.1", \ + "119.7, 119.7, 119.7, 139.4, 177.1"); + } + fall_transition (inslew_load_5x5__12) { + values ("37.6, 37.6, 37.6, 50.5, 76.1", \ + "59.8, 59.8, 59.8, 73.0, 98.5", \ + "100.5, 100.5, 100.5, 114.2, 140.6", \ + "179.3, 179.3, 179.3, 193.5, 221.1", \ + "335.2, 335.2, 335.2, 349.7, 378.4"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__12) { + values ("29.5, 29.5, 29.5, 51.7, 92.9", \ + "35.2, 35.2, 35.2, 56.5, 99.8", \ + "44.4, 44.4, 44.4, 68.8, 113.1", \ + "60.0, 60.0, 60.0, 85.8, 134.7", \ + "89.3, 89.3, 89.3, 116.1, 167.9"); + } + rise_transition (inslew_load_5x5__12) { + values ("59.8, 59.8, 59.8, 93.8, 162.5", \ + "91.3, 91.3, 91.3, 122.1, 190.1", \ + "151.9, 151.9, 151.9, 185.3, 250.0", \ + "270.8, 270.8, 270.8, 304.7, 371.8", \ + "507.0, 507.0, 507.0, 541.3, 609.3"); + } + cell_fall (inslew_load_5x5__12) { + values ("22.8, 22.8, 22.8, 38.2, 63.8", \ + "25.3, 25.3, 25.3, 43.0, 72.7", \ + "26.0, 26.0, 26.0, 46.1, 80.8", \ + "24.5, 24.5, 24.5, 46.4, 86.1", \ + "19.6, 19.6, 19.6, 42.8, 86.4"); + } + fall_transition (inslew_load_5x5__12) { + values ("25.0, 25.0, 25.0, 38.4, 64.0", \ + "42.8, 42.8, 42.8, 56.8, 82.9", \ + "75.3, 75.3, 75.3, 90.1, 117.8", \ + "138.4, 138.4, 138.4, 153.9, 183.4", \ + "263.2, 263.2, 263.2, 279.3, 310.3"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__12) { + values ("880.0, 880.0, 880.0, 1033.7, 1341.1", \ + "1042.2, 1042.2, 1042.2, 1195.9, 1503.3", \ + "1366.5, 1366.5, 1366.5, 1520.2, 1827.7", \ + "2015.3, 2015.3, 2015.3, 2169.0, 2476.4", \ + "3312.8, 3312.8, 3312.8, 3466.5, 3773.9"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("626.9, 626.9, 626.9, 780.6, 1088.0", \ + "817.0, 817.0, 817.0, 970.7, 1278.2", \ + "1197.4, 1197.4, 1197.4, 1351.1, 1658.5", \ + "1958.1, 1958.1, 1958.1, 2111.8, 2419.2", \ + "3479.5, 3479.5, 3479.5, 3633.2, 3940.6"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__12) { + values ("777.4, 777.4, 777.4, 931.1, 1238.5", \ + "890.6, 890.6, 890.6, 1044.3, 1351.7", \ + "1117.1, 1117.1, 1117.1, 1270.8, 1578.2", \ + "1570.0, 1570.0, 1570.0, 1723.7, 2031.1", \ + "2475.9, 2475.9, 2475.9, 2629.6, 2937.0"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("550.4, 550.4, 550.4, 704.1, 1011.5", \ + "750.7, 750.7, 750.7, 904.4, 1211.8", \ + "1151.4, 1151.4, 1151.4, 1305.1, 1612.5", \ + "1952.8, 1952.8, 1952.8, 2106.5, 2413.9", \ + "3555.5, 3555.5, 3555.5, 3709.2, 4016.6"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__12) { + values ("499.0, 499.0, 499.0, 652.7, 960.1", \ + "597.7, 597.7, 597.7, 751.4, 1058.8", \ + "795.1, 795.1, 795.1, 948.8, 1256.2", \ + "1189.9, 1189.9, 1189.9, 1343.6, 1651.0", \ + "1979.6, 1979.6, 1979.6, 2133.3, 2440.7"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("408.5, 408.5, 408.5, 562.2, 869.7", \ + "529.0, 529.0, 529.0, 682.7, 990.1", \ + "769.9, 769.9, 769.9, 923.6, 1231.0", \ + "1251.7, 1251.7, 1251.7, 1405.4, 1712.9", \ + "2215.4, 2215.4, 2215.4, 2369.1, 2676.5"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__12) { + values ("253.7, 253.7, 253.7, 407.4, 714.8", \ + "355.4, 355.4, 355.4, 509.1, 816.5", \ + "558.7, 558.7, 558.7, 712.4, 1019.8", \ + "965.5, 965.5, 965.5, 1119.2, 1426.6", \ + "1779.0, 1779.0, 1779.0, 1932.7, 2240.1"); + } + fall_power (energy_inslew_load_5x5__12) { + values ("238.9, 238.9, 238.9, 392.6, 700.0", \ + "322.3, 322.3, 322.3, 476.0, 783.4", \ + "489.2, 489.2, 489.2, 642.9, 950.3", \ + "823.0, 823.0, 823.0, 976.7, 1284.1", \ + "1490.6, 1490.6, 1490.6, 1644.3, 1951.7"); + } + } + } + } + + cell (aoi211v5x05) { + area : 0.0 ; + cell_leakage_power : 0.93 ; + leakage_power () { + when : "(!(c) & !(b) & a2 & a1)" ; + value : 1 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a2) & a1)" ; + value : 0.00012 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(b) & c)" ; + value : 1.8 ; + } + leakage_power () { + when : "(!(c) & !(b) & a2 & !(a1))" ; + value : 0.00011 ; + } + leakage_power () { + when : "((a1 & a2 & (b ^ c)) | (b & !(c)))" ; + value : 1.1 ; + } + leakage_power () { + when : "((!((a1 | a2)) & c) | (b & c))" ; + value : 2.5 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a2) & !(a1))" ; + value : 6.8e-05 ; + } + pin (c) { + direction : input ; + capacitance : 4.16 ; + } + pin (b) { + direction : input ; + capacitance : 4.39 ; + } + pin (a2) { + direction : input ; + capacitance : 4.49 ; + } + pin (a1) { + direction : input ; + capacitance : 4.68 ; + } + pin (z) { + function : "(((!(c) & !(b)) & !(a2)) | ((!(c) & !(b)) & !(a1)))" ; + direction : output ; + capacitance : 4.51 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("124.3, 124.3, 124.3, 155.0, 216.5", \ + "133.0, 133.0, 133.0, 164.1, 225.9", \ + "147.9, 147.9, 147.9, 179.2, 241.5", \ + "178.0, 178.0, 178.0, 209.3, 271.7", \ + "239.3, 239.3, 239.3, 270.7, 333.1"); + } + rise_transition (inslew_load_5x5__13) { + values ("223.2, 223.2, 223.2, 275.7, 381.2", \ + "272.0, 272.0, 272.0, 324.2, 429.1", \ + "363.1, 363.1, 363.1, 415.5, 520.4", \ + "542.6, 542.6, 542.6, 594.7, 699.3", \ + "902.6, 902.6, 902.6, 954.2, 1057.8"); + } + cell_fall (inslew_load_5x5__13) { + values ("41.3, 41.3, 41.3, 55.3, 82.4", \ + "46.2, 46.2, 46.2, 61.4, 90.0", \ + "52.4, 52.4, 52.4, 69.0, 100.3", \ + "61.2, 61.2, 61.2, 79.3, 113.6", \ + "76.6, 76.6, 76.6, 95.7, 132.6"); + } + fall_transition (inslew_load_5x5__13) { + values ("57.1, 57.1, 57.1, 75.0, 111.3", \ + "77.9, 77.9, 77.9, 95.7, 131.5", \ + "117.9, 117.9, 117.9, 135.9, 171.5", \ + "196.6, 196.6, 196.6, 214.9, 251.0", \ + "353.2, 353.2, 353.2, 371.7, 408.3"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("109.6, 109.6, 109.6, 140.4, 201.9", \ + "109.6, 109.6, 109.6, 140.9, 202.9", \ + "108.1, 108.1, 108.1, 139.6, 202.3", \ + "106.1, 106.1, 106.1, 137.8, 200.6", \ + "101.9, 101.9, 101.9, 134.9, 198.2"); + } + rise_transition (inslew_load_5x5__13) { + values ("198.4, 198.4, 198.4, 250.8, 356.2", \ + "233.2, 233.2, 233.2, 285.4, 390.0", \ + "297.4, 297.4, 297.4, 349.6, 454.5", \ + "425.1, 425.1, 425.1, 476.7, 580.4", \ + "682.7, 682.7, 682.7, 733.5, 835.6"); + } + cell_fall (inslew_load_5x5__13) { + values ("40.6, 40.6, 40.6, 55.6, 83.6", \ + "51.5, 51.5, 51.5, 68.1, 98.8", \ + "68.2, 68.2, 68.2, 86.7, 120.8", \ + "97.9, 97.9, 97.9, 117.9, 155.6", \ + "154.8, 154.8, 154.8, 175.9, 216.4"); + } + fall_transition (inslew_load_5x5__13) { + values ("50.0, 50.0, 50.0, 68.1, 104.4", \ + "74.9, 74.9, 74.9, 93.2, 129.2", \ + "121.3, 121.3, 121.3, 140.0, 176.5", \ + "211.9, 211.9, 211.9, 230.9, 268.3", \ + "391.8, 391.8, 391.8, 411.0, 449.2"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("76.9, 76.9, 76.9, 108.3, 170.3", \ + "81.5, 81.5, 81.5, 113.4, 176.1", \ + "88.1, 88.1, 88.1, 121.0, 185.2", \ + "99.6, 99.6, 99.6, 133.6, 199.7", \ + "120.0, 120.0, 120.0, 155.3, 224.1"); + } + rise_transition (inslew_load_5x5__13) { + values ("138.8, 138.8, 138.8, 191.7, 298.4", \ + "171.4, 171.4, 171.4, 223.7, 329.5", \ + "234.6, 234.6, 234.6, 286.0, 390.0", \ + "359.8, 359.8, 359.8, 412.2, 513.9", \ + "611.0, 611.0, 611.0, 661.8, 767.1"); + } + cell_fall (inslew_load_5x5__13) { + values ("39.6, 39.6, 39.6, 56.6, 87.6", \ + "46.1, 46.1, 46.1, 65.7, 100.5", \ + "53.0, 53.0, 53.0, 75.6, 115.8", \ + "61.6, 61.6, 61.6, 86.8, 133.0", \ + "74.8, 74.8, 74.8, 102.1, 153.4"); + } + fall_transition (inslew_load_5x5__13) { + values ("42.6, 42.6, 42.6, 60.2, 95.7", \ + "62.7, 62.7, 62.7, 80.8, 115.9", \ + "99.8, 99.8, 99.8, 118.7, 154.9", \ + "171.1, 171.1, 171.1, 191.0, 229.1", \ + "312.0, 312.0, 312.0, 332.6, 372.6"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__13) { + values ("44.8, 44.8, 44.8, 77.5, 140.5", \ + "53.1, 53.1, 53.1, 87.3, 152.2", \ + "71.9, 71.9, 71.9, 106.2, 174.0", \ + "103.1, 103.1, 103.1, 140.6, 211.5", \ + "163.0, 163.0, 163.0, 202.0, 276.9"); + } + rise_transition (inslew_load_5x5__13) { + values ("81.9, 81.9, 81.9, 134.8, 242.8", \ + "116.1, 116.1, 116.1, 168.7, 275.1", \ + "189.1, 189.1, 189.1, 238.9, 344.2", \ + "328.0, 328.0, 328.0, 379.9, 483.0", \ + "603.6, 603.6, 603.6, 655.9, 759.9"); + } + cell_fall (inslew_load_5x5__13) { + values ("26.9, 26.9, 26.9, 45.7, 77.8", \ + "27.1, 27.1, 27.1, 49.4, 86.4", \ + "22.6, 22.6, 22.6, 48.6, 92.7", \ + "9.3, 9.3, 9.3, 38.8, 90.6", \ + "-20.2, -20.2, -20.2, 11.9, 70.8"); + } + fall_transition (inslew_load_5x5__13) { + values ("31.1, 31.1, 31.1, 49.0, 84.3", \ + "47.0, 47.0, 47.0, 65.9, 101.4", \ + "76.2, 76.2, 76.2, 96.4, 133.9", \ + "132.3, 132.3, 132.3, 153.9, 194.2", \ + "243.0, 243.0, 243.0, 265.6, 308.7"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__13) { + values ("237.7, 237.7, 237.7, 294.1, 406.8", \ + "284.5, 284.5, 284.5, 340.8, 453.6", \ + "378.0, 378.0, 378.0, 434.4, 547.1", \ + "565.1, 565.1, 565.1, 621.4, 734.2", \ + "939.2, 939.2, 939.2, 995.6, 1108.3"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("165.1, 165.1, 165.1, 221.4, 334.1", \ + "207.8, 207.8, 207.8, 264.1, 376.9", \ + "293.2, 293.2, 293.2, 349.6, 462.3", \ + "464.0, 464.0, 464.0, 520.4, 633.1", \ + "805.8, 805.8, 805.8, 862.1, 974.8"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__13) { + values ("208.7, 208.7, 208.7, 265.1, 377.8", \ + "241.2, 241.2, 241.2, 297.6, 410.3", \ + "306.2, 306.2, 306.2, 362.6, 475.3", \ + "436.1, 436.1, 436.1, 492.5, 605.2", \ + "696.0, 696.0, 696.0, 752.4, 865.1"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("144.8, 144.8, 144.8, 201.2, 313.9", \ + "190.8, 190.8, 190.8, 247.1, 359.8", \ + "282.6, 282.6, 282.6, 338.9, 451.7", \ + "466.2, 466.2, 466.2, 522.6, 635.3", \ + "833.5, 833.5, 833.5, 889.8, 1002.6"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__13) { + values ("144.7, 144.7, 144.7, 201.1, 313.8", \ + "173.4, 173.4, 173.4, 229.7, 342.5", \ + "230.7, 230.7, 230.7, 287.0, 399.8", \ + "345.3, 345.3, 345.3, 401.6, 514.4", \ + "574.5, 574.5, 574.5, 630.8, 743.6"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("116.2, 116.2, 116.2, 172.6, 285.3", \ + "144.4, 144.4, 144.4, 200.8, 313.5", \ + "200.8, 200.8, 200.8, 257.1, 369.8", \ + "313.5, 313.5, 313.5, 369.8, 482.6", \ + "538.9, 538.9, 538.9, 595.3, 708.0"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__13) { + values ("85.5, 85.5, 85.5, 141.8, 254.5", \ + "114.7, 114.7, 114.7, 171.0, 283.8", \ + "173.1, 173.1, 173.1, 229.5, 342.2", \ + "290.0, 290.0, 290.0, 346.3, 459.1", \ + "523.7, 523.7, 523.7, 580.1, 692.8"); + } + fall_power (energy_inslew_load_5x5__13) { + values ("75.5, 75.5, 75.5, 131.8, 244.5", \ + "94.4, 94.4, 94.4, 150.8, 263.5", \ + "132.3, 132.3, 132.3, 188.7, 301.4", \ + "208.1, 208.1, 208.1, 264.5, 377.2", \ + "359.8, 359.8, 359.8, 416.1, 528.8"); + } + } + } + } + + cell (aoi21a2bv0x05) { + area : 0.0 ; + cell_leakage_power : 5.3 ; + leakage_power () { + when : "(b & !(a2) & a1)" ; + value : 5.2 ; + } + leakage_power () { + when : "(a2 & b)" ; + value : 9.7 ; + } + leakage_power () { + when : "(a2 & !(b))" ; + value : 5.6 ; + } + leakage_power () { + when : "(b & !(a2) & !(a1))" ; + value : 4.9 ; + } + leakage_power () { + when : "(!(a2) & !(b))" ; + value : 0.79 ; + } + pin (b) { + direction : input ; + capacitance : 2.99 ; + } + pin (a2) { + direction : input ; + capacitance : 2.84 ; + } + pin (a1) { + direction : input ; + capacitance : 3.32 ; + } + pin (z) { + function : "(!((a1 & !(a2))) & b)" ; + direction : output ; + capacitance : 2.68 ; + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("80.2, 80.2, 80.2, 98.0, 133.3", \ + "82.9, 82.9, 82.9, 100.9, 136.6", \ + "83.0, 83.0, 83.0, 101.6, 137.6", \ + "78.8, 78.8, 78.8, 97.8, 134.8", \ + "66.4, 66.4, 66.4, 86.0, 124.2"); + } + rise_transition (inslew_load_5x5__14) { + values ("96.3, 96.3, 96.3, 128.3, 192.5", \ + "106.5, 106.5, 106.5, 138.1, 202.2", \ + "124.6, 124.6, 124.6, 155.9, 219.4", \ + "159.3, 159.3, 159.3, 190.3, 252.8", \ + "226.5, 226.5, 226.5, 257.5, 320.4"); + } + cell_fall (inslew_load_5x5__14) { + values ("77.6, 77.6, 77.6, 91.3, 116.3", \ + "89.7, 89.7, 89.7, 104.1, 130.4", \ + "108.2, 108.2, 108.2, 123.6, 151.9", \ + "140.3, 140.3, 140.3, 156.7, 187.1", \ + "199.9, 199.9, 199.9, 217.2, 250.2"); + } + fall_transition (inslew_load_5x5__14) { + values ("58.0, 58.0, 58.0, 73.1, 103.0", \ + "72.5, 72.5, 72.5, 87.8, 117.8", \ + "99.6, 99.6, 99.6, 115.1, 145.4", \ + "152.1, 152.1, 152.1, 167.7, 198.7", \ + "255.7, 255.7, 255.7, 271.7, 303.0"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__14) { + values ("50.6, 50.6, 50.6, 69.7, 105.8", \ + "55.8, 55.8, 55.8, 75.3, 112.4", \ + "62.5, 62.5, 62.5, 82.4, 120.7", \ + "70.4, 70.4, 70.4, 91.9, 131.8", \ + "81.9, 81.9, 81.9, 104.6, 147.3"); + } + rise_transition (inslew_load_5x5__14) { + values ("48.5, 48.5, 48.5, 80.8, 146.6", \ + "61.4, 61.4, 61.4, 93.4, 158.7", \ + "86.6, 86.6, 86.6, 117.8, 182.5", \ + "132.6, 132.6, 132.6, 164.7, 228.1", \ + "221.8, 221.8, 221.8, 254.3, 318.5"); + } + cell_fall (inslew_load_5x5__14) { + values ("48.7, 48.7, 48.7, 62.5, 85.4", \ + "53.9, 53.9, 53.9, 69.0, 94.3", \ + "59.9, 59.9, 59.9, 76.6, 105.0", \ + "67.7, 67.7, 67.7, 86.5, 118.5", \ + "81.5, 81.5, 81.5, 100.6, 137.6"); + } + fall_transition (inslew_load_5x5__14) { + values ("31.1, 31.1, 31.1, 42.3, 63.5", \ + "40.7, 40.7, 40.7, 52.4, 74.1", \ + "58.5, 58.5, 58.5, 70.8, 93.6", \ + "93.3, 93.3, 93.3, 106.0, 130.2", \ + "162.0, 162.0, 162.0, 175.3, 200.4"); + } + } + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__14) { + values ("62.4, 62.4, 62.4, 80.2, 115.6", \ + "69.1, 69.1, 69.1, 87.5, 123.4", \ + "81.1, 81.1, 81.1, 99.8, 136.5", \ + "103.5, 103.5, 103.5, 122.8, 160.7", \ + "147.3, 147.3, 147.3, 167.0, 206.0"); + } + rise_transition (inslew_load_5x5__14) { + values ("123.4, 123.4, 123.4, 155.3, 219.5", \ + "161.4, 161.4, 161.4, 192.9, 256.3", \ + "236.0, 236.0, 236.0, 266.9, 329.2", \ + "383.3, 383.3, 383.3, 416.0, 477.3", \ + "678.9, 678.9, 678.9, 709.7, 771.3"); + } + cell_fall (inslew_load_5x5__14) { + values ("33.2, 33.2, 33.2, 44.8, 67.1", \ + "35.7, 35.7, 35.7, 48.3, 72.2", \ + "37.5, 37.5, 37.5, 51.5, 77.7", \ + "38.6, 38.6, 38.6, 53.7, 82.5", \ + "39.0, 39.0, 39.0, 55.0, 85.7"); + } + fall_transition (inslew_load_5x5__14) { + values ("50.5, 50.5, 50.5, 65.4, 95.2", \ + "70.1, 70.1, 70.1, 84.9, 114.6", \ + "108.0, 108.0, 108.0, 123.0, 152.7", \ + "182.8, 182.8, 182.8, 198.1, 228.2", \ + "331.8, 331.8, 331.8, 347.2, 377.8"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__14) { + values ("185.4, 185.4, 185.4, 219.0, 286.1", \ + "215.8, 215.8, 215.8, 249.3, 316.4", \ + "275.6, 275.6, 275.6, 309.2, 376.3", \ + "394.4, 394.4, 394.4, 427.9, 495.0", \ + "631.3, 631.3, 631.3, 664.9, 732.0"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("197.5, 197.5, 197.5, 231.1, 298.2", \ + "245.6, 245.6, 245.6, 279.2, 346.3", \ + "340.1, 340.1, 340.1, 373.6, 440.7", \ + "527.9, 527.9, 527.9, 561.4, 628.5", \ + "902.7, 902.7, 902.7, 936.3, 1003.4"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__14) { + values ("122.1, 122.1, 122.1, 155.6, 222.8", \ + "153.7, 153.7, 153.7, 187.2, 254.3", \ + "215.9, 215.9, 215.9, 249.4, 316.6", \ + "339.7, 339.7, 339.7, 373.2, 440.3", \ + "586.7, 586.7, 586.7, 620.2, 687.3"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("135.0, 135.0, 135.0, 168.5, 235.6", \ + "174.2, 174.2, 174.2, 207.8, 274.9", \ + "251.8, 251.8, 251.8, 285.4, 352.5", \ + "406.6, 406.6, 406.6, 440.2, 507.3", \ + "715.9, 715.9, 715.9, 749.4, 816.6"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__14) { + values ("126.5, 126.5, 126.5, 160.1, 227.2", \ + "160.8, 160.8, 160.8, 194.3, 261.4", \ + "229.2, 229.2, 229.2, 262.8, 329.9", \ + "366.2, 366.2, 366.2, 399.8, 466.9", \ + "640.1, 640.1, 640.1, 673.7, 740.8"); + } + fall_power (energy_inslew_load_5x5__14) { + values ("101.4, 101.4, 101.4, 135.0, 202.1", \ + "130.6, 130.6, 130.6, 164.1, 231.3", \ + "189.0, 189.0, 189.0, 222.5, 289.7", \ + "305.8, 305.8, 305.8, 339.3, 406.4", \ + "539.4, 539.4, 539.4, 572.9, 640.0"); + } + } + } + } + + cell (aoi21a2bv5x05) { + area : 0.0 ; + cell_leakage_power : 5.3 ; + leakage_power () { + when : "(b & !(a2) & a1)" ; + value : 5.2 ; + } + leakage_power () { + when : "(a2 & b)" ; + value : 9.7 ; + } + leakage_power () { + when : "(a2 & !(b))" ; + value : 5.6 ; + } + leakage_power () { + when : "(b & !(a2) & !(a1))" ; + value : 4.9 ; + } + leakage_power () { + when : "(!(a2) & !(b))" ; + value : 0.79 ; + } + pin (b) { + direction : input ; + capacitance : 2.89 ; + } + pin (a2) { + direction : input ; + capacitance : 2.99 ; + } + pin (a1) { + direction : input ; + capacitance : 3.57 ; + } + pin (z) { + function : "(!((a1 & !(a2))) & b)" ; + direction : output ; + capacitance : 2.64 ; + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__15) { + values ("80.9, 80.9, 80.9, 98.4, 133.1", \ + "83.7, 83.7, 83.7, 101.4, 136.5", \ + "83.9, 83.9, 83.9, 102.1, 137.5", \ + "79.7, 79.7, 79.7, 98.3, 134.7", \ + "67.2, 67.2, 67.2, 86.5, 124.1"); + } + rise_transition (inslew_load_5x5__15) { + values ("97.4, 97.4, 97.4, 128.8, 192.1", \ + "107.5, 107.5, 107.5, 138.7, 201.7", \ + "125.6, 125.6, 125.6, 156.5, 218.9", \ + "160.5, 160.5, 160.5, 190.9, 252.4", \ + "227.6, 227.6, 227.6, 258.1, 320.0"); + } + cell_fall (inslew_load_5x5__15) { + values ("77.8, 77.8, 77.8, 91.3, 115.9", \ + "90.1, 90.1, 90.1, 104.3, 130.2", \ + "108.7, 108.7, 108.7, 123.8, 151.7", \ + "140.6, 140.6, 140.6, 156.7, 186.7", \ + "200.2, 200.2, 200.2, 217.3, 249.7"); + } + fall_transition (inslew_load_5x5__15) { + values ("58.2, 58.2, 58.2, 73.1, 102.5", \ + "72.7, 72.7, 72.7, 87.8, 117.2", \ + "99.8, 99.8, 99.8, 115.0, 144.9", \ + "152.3, 152.3, 152.3, 167.7, 198.1", \ + "255.9, 255.9, 255.9, 271.5, 302.4"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__15) { + values ("51.4, 51.4, 51.4, 70.3, 105.8", \ + "56.7, 56.7, 56.7, 75.8, 112.4", \ + "63.5, 63.5, 63.5, 83.1, 120.9", \ + "71.3, 71.3, 71.3, 92.5, 131.8", \ + "82.8, 82.8, 82.8, 105.0, 147.1"); + } + rise_transition (inslew_load_5x5__15) { + values ("48.7, 48.7, 48.7, 80.5, 145.2", \ + "61.6, 61.6, 61.6, 92.9, 157.1", \ + "86.8, 86.8, 86.8, 117.3, 181.0", \ + "132.7, 132.7, 132.7, 164.2, 226.6", \ + "221.8, 221.8, 221.8, 253.7, 316.9"); + } + cell_fall (inslew_load_5x5__15) { + values ("49.5, 49.5, 49.5, 63.3, 86.1", \ + "54.7, 54.7, 54.7, 69.7, 94.8", \ + "60.6, 60.6, 60.6, 77.1, 105.3", \ + "68.3, 68.3, 68.3, 86.9, 118.6", \ + "81.8, 81.8, 81.8, 100.7, 137.2"); + } + fall_transition (inslew_load_5x5__15) { + values ("31.4, 31.4, 31.4, 42.5, 63.4", \ + "40.9, 40.9, 40.9, 52.5, 73.9", \ + "58.6, 58.6, 58.6, 70.8, 93.3", \ + "93.2, 93.2, 93.2, 105.7, 129.6", \ + "161.4, 161.4, 161.4, 174.5, 199.4"); + } + } + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__15) { + values ("63.0, 63.0, 63.0, 80.5, 115.4", \ + "69.8, 69.8, 69.8, 87.8, 123.1", \ + "81.7, 81.7, 81.7, 100.1, 136.2", \ + "104.2, 104.2, 104.2, 123.2, 160.4", \ + "147.9, 147.9, 147.9, 167.4, 205.7"); + } + rise_transition (inslew_load_5x5__15) { + values ("124.5, 124.5, 124.5, 155.8, 219.0", \ + "162.4, 162.4, 162.4, 193.4, 255.7", \ + "237.0, 237.0, 237.0, 267.4, 328.7", \ + "384.3, 384.3, 384.3, 416.5, 476.8", \ + "679.9, 679.9, 679.9, 710.2, 770.8"); + } + cell_fall (inslew_load_5x5__15) { + values ("33.3, 33.3, 33.3, 44.7, 66.6", \ + "35.7, 35.7, 35.7, 48.2, 71.7", \ + "37.6, 37.6, 37.6, 51.3, 77.1", \ + "38.7, 38.7, 38.7, 53.6, 81.8", \ + "39.1, 39.1, 39.1, 54.8, 85.1"); + } + fall_transition (inslew_load_5x5__15) { + values ("50.5, 50.5, 50.5, 65.2, 94.6", \ + "70.1, 70.1, 70.1, 84.8, 114.0", \ + "108.1, 108.1, 108.1, 122.8, 152.0", \ + "182.9, 182.9, 182.9, 197.9, 227.6", \ + "331.9, 331.9, 331.9, 347.0, 377.1"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__15) { + values ("187.0, 187.0, 187.0, 220.0, 286.0", \ + "217.4, 217.4, 217.4, 250.4, 316.4", \ + "277.2, 277.2, 277.2, 310.2, 376.2", \ + "396.0, 396.0, 396.0, 429.0, 495.0", \ + "632.9, 632.9, 632.9, 665.9, 732.0"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("198.4, 198.4, 198.4, 231.4, 297.4", \ + "246.4, 246.4, 246.4, 279.4, 345.4", \ + "340.9, 340.9, 340.9, 373.9, 439.9", \ + "528.7, 528.7, 528.7, 561.7, 627.7", \ + "903.5, 903.5, 903.5, 936.5, 1002.5"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__15) { + values ("124.7, 124.7, 124.7, 157.7, 223.8", \ + "156.3, 156.3, 156.3, 189.3, 255.3", \ + "218.6, 218.6, 218.6, 251.6, 317.6", \ + "342.4, 342.4, 342.4, 375.4, 441.4", \ + "589.4, 589.4, 589.4, 622.4, 688.5"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("137.8, 137.8, 137.8, 170.8, 236.8", \ + "177.0, 177.0, 177.0, 210.0, 276.0", \ + "254.7, 254.7, 254.7, 287.7, 353.7", \ + "409.5, 409.5, 409.5, 442.5, 508.5", \ + "718.7, 718.7, 718.7, 751.7, 817.7"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__15) { + values ("127.6, 127.6, 127.6, 160.6, 226.6", \ + "161.9, 161.9, 161.9, 194.9, 260.9", \ + "230.3, 230.3, 230.3, 263.3, 329.4", \ + "367.3, 367.3, 367.3, 400.3, 466.3", \ + "641.2, 641.2, 641.2, 674.2, 740.2"); + } + fall_power (energy_inslew_load_5x5__15) { + values ("101.6, 101.6, 101.6, 134.6, 200.6", \ + "130.8, 130.8, 130.8, 163.8, 229.8", \ + "189.2, 189.2, 189.2, 222.2, 288.2", \ + "306.0, 306.0, 306.0, 339.0, 405.0", \ + "539.5, 539.5, 539.5, 572.5, 638.6"); + } + } + } + } + + cell (aoi21a2v0x05) { + area : 0.0 ; + cell_leakage_power : 2.3 ; + leakage_power () { + when : "(!(b) & !(a2) & a1)" ; + value : 0.39 ; + } + leakage_power () { + when : "(a2 & b)" ; + value : 5.6 ; + } + leakage_power () { + when : "(a2 & !(b))" ; + value : 4.9 ; + } + leakage_power () { + when : "(!(a2) & b)" ; + value : 0.79 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 0.00012 ; + } + pin (b) { + direction : input ; + capacitance : 3.10 ; + } + pin (a2) { + direction : input ; + capacitance : 3.17 ; + } + pin (a1) { + direction : input ; + capacitance : 3.60 ; + } + pin (z) { + function : "((a2 | !(a1)) & !(b))" ; + direction : output ; + capacitance : 2.99 ; + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__16) { + values ("77.6, 77.6, 77.6, 97.3, 136.5", \ + "79.9, 79.9, 79.9, 99.8, 139.4", \ + "79.6, 79.6, 79.6, 100.1, 140.0", \ + "75.2, 75.2, 75.2, 96.2, 137.2", \ + "62.8, 62.8, 62.8, 84.6, 126.9"); + } + rise_transition (inslew_load_5x5__16) { + values ("96.7, 96.7, 96.7, 132.4, 204.2", \ + "107.1, 107.1, 107.1, 142.3, 213.9", \ + "125.1, 125.1, 125.1, 160.1, 230.9", \ + "159.7, 159.7, 159.7, 194.2, 264.1", \ + "226.9, 226.9, 226.9, 262.8, 331.4"); + } + cell_fall (inslew_load_5x5__16) { + values ("73.2, 73.2, 73.2, 88.0, 115.0", \ + "85.2, 85.2, 85.2, 100.9, 129.4", \ + "103.7, 103.7, 103.7, 120.5, 151.3", \ + "136.0, 136.0, 136.0, 154.0, 187.4", \ + "196.4, 196.4, 196.4, 215.6, 251.9"); + } + fall_transition (inslew_load_5x5__16) { + values ("56.0, 56.0, 56.0, 72.7, 106.0", \ + "70.7, 70.7, 70.7, 87.6, 120.9", \ + "98.0, 98.0, 98.0, 115.1, 148.7", \ + "151.0, 151.0, 151.0, 168.4, 202.6", \ + "255.5, 255.5, 255.5, 273.2, 307.9"); + } + } + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("63.9, 63.9, 63.9, 83.8, 123.2", \ + "70.9, 70.9, 70.9, 91.1, 131.0", \ + "82.7, 82.7, 82.7, 103.5, 144.7", \ + "105.2, 105.2, 105.2, 126.7, 168.8", \ + "149.0, 149.0, 149.0, 171.0, 214.4"); + } + rise_transition (inslew_load_5x5__16) { + values ("126.2, 126.2, 126.2, 161.7, 233.4", \ + "164.1, 164.1, 164.1, 199.2, 270.0", \ + "238.7, 238.7, 238.7, 273.2, 342.7", \ + "386.0, 386.0, 386.0, 422.2, 490.5", \ + "681.5, 681.5, 681.5, 715.9, 788.8"); + } + cell_fall (inslew_load_5x5__16) { + values ("34.4, 34.4, 34.4, 47.3, 71.9", \ + "37.0, 37.0, 37.0, 51.0, 77.3", \ + "39.0, 39.0, 39.0, 54.4, 83.3", \ + "40.2, 40.2, 40.2, 56.9, 88.6", \ + "40.7, 40.7, 40.7, 58.3, 92.4"); + } + fall_transition (inslew_load_5x5__16) { + values ("52.0, 52.0, 52.0, 68.6, 101.9", \ + "71.6, 71.6, 71.6, 88.1, 121.2", \ + "109.5, 109.5, 109.5, 126.2, 159.2", \ + "184.4, 184.4, 184.4, 201.4, 234.9", \ + "333.4, 333.4, 333.4, 350.5, 384.6"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__16) { + values ("34.1, 34.1, 34.1, 55.9, 97.0", \ + "45.7, 45.7, 45.7, 68.5, 111.7", \ + "65.0, 65.0, 65.0, 89.7, 135.7", \ + "101.1, 101.1, 101.1, 127.1, 176.5", \ + "171.7, 171.7, 171.7, 198.6, 250.6"); + } + rise_transition (inslew_load_5x5__16) { + values ("66.6, 66.6, 66.6, 102.6, 175.3", \ + "105.2, 105.2, 105.2, 140.3, 212.4", \ + "177.8, 177.8, 177.8, 213.8, 285.0", \ + "320.8, 320.8, 320.8, 357.3, 429.4", \ + "605.4, 605.4, 605.4, 642.1, 715.1"); + } + cell_fall (inslew_load_5x5__16) { + values ("17.5, 17.5, 17.5, 31.4, 54.5", \ + "14.7, 14.7, 14.7, 31.3, 58.7", \ + "5.9, 5.9, 5.9, 25.2, 58.1", \ + "-14.1, -14.1, -14.1, 7.4, 45.8", \ + "-56.0, -56.0, -56.0, -32.8, 10.1"); + } + fall_transition (inslew_load_5x5__16) { + values ("25.6, 25.6, 25.6, 37.9, 61.2", \ + "39.6, 39.6, 39.6, 52.8, 77.1", \ + "66.1, 66.1, 66.1, 80.3, 106.5", \ + "117.7, 117.7, 117.7, 132.9, 161.2", \ + "220.0, 220.0, 220.0, 235.9, 266.1"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__16) { + values ("175.6, 175.6, 175.6, 213.0, 287.8", \ + "205.9, 205.9, 205.9, 243.3, 318.1", \ + "265.6, 265.6, 265.6, 303.0, 377.8", \ + "384.3, 384.3, 384.3, 421.7, 496.4", \ + "621.2, 621.2, 621.2, 658.5, 733.3"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("185.0, 185.0, 185.0, 222.4, 297.2", \ + "233.0, 233.0, 233.0, 270.4, 345.2", \ + "327.3, 327.3, 327.3, 364.7, 439.5", \ + "515.1, 515.1, 515.1, 552.5, 627.3", \ + "889.8, 889.8, 889.8, 927.2, 1002.0"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__16) { + values ("129.4, 129.4, 129.4, 166.8, 241.6", \ + "163.7, 163.7, 163.7, 201.1, 275.9", \ + "232.2, 232.2, 232.2, 269.6, 344.4", \ + "369.1, 369.1, 369.1, 406.5, 481.3", \ + "643.0, 643.0, 643.0, 680.4, 755.2"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("104.8, 104.8, 104.8, 142.2, 217.0", \ + "134.0, 134.0, 134.0, 171.4, 246.2", \ + "192.4, 192.4, 192.4, 229.8, 304.6", \ + "309.2, 309.2, 309.2, 346.6, 421.4", \ + "542.8, 542.8, 542.8, 580.2, 655.0"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__16) { + values ("65.7, 65.7, 65.7, 103.1, 177.9", \ + "94.1, 94.1, 94.1, 131.5, 206.3", \ + "150.9, 150.9, 150.9, 188.3, 263.1", \ + "264.6, 264.6, 264.6, 302.0, 376.8", \ + "491.8, 491.8, 491.8, 529.2, 604.0"); + } + fall_power (energy_inslew_load_5x5__16) { + values ("54.2, 54.2, 54.2, 91.6, 166.4", \ + "70.9, 70.9, 70.9, 108.2, 183.0", \ + "104.2, 104.2, 104.2, 141.6, 216.4", \ + "171.0, 171.0, 171.0, 208.4, 283.2", \ + "304.5, 304.5, 304.5, 341.9, 416.7"); + } + } + } + } + + cell (aoi21bv0x05) { + area : 0.0 ; + cell_leakage_power : 3.6 ; + leakage_power () { + when : "(b & a2 & a1)" ; + value : 5.2 ; + } + leakage_power () { + when : "(!((a1 & a2)) & b)" ; + value : 4.9 ; + } + leakage_power () { + when : "!(b)" ; + value : 0.79 ; + } + pin (b) { + direction : input ; + capacitance : 3.17 ; + } + pin (a2) { + direction : input ; + capacitance : 3.29 ; + } + pin (a1) { + direction : input ; + capacitance : 3.33 ; + } + pin (z) { + function : "(!((a2 & a1)) & b)" ; + direction : output ; + capacitance : 3.03 ; + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__17) { + values ("56.0, 56.0, 56.0, 77.4, 118.0", \ + "61.6, 61.6, 61.6, 83.6, 125.2", \ + "68.6, 68.6, 68.6, 91.0, 133.9", \ + "76.5, 76.5, 76.5, 100.5, 145.3", \ + "88.0, 88.0, 88.0, 113.4, 161.0"); + } + rise_transition (inslew_load_5x5__17) { + values ("54.3, 54.3, 54.3, 90.8, 165.4", \ + "67.3, 67.3, 67.3, 103.8, 177.7", \ + "92.4, 92.4, 92.4, 127.7, 200.9", \ + "138.3, 138.3, 138.3, 174.4, 246.3", \ + "227.4, 227.4, 227.4, 264.0, 336.3"); + } + cell_fall (inslew_load_5x5__17) { + values ("53.0, 53.0, 53.0, 68.3, 93.8", \ + "58.4, 58.4, 58.4, 75.1, 103.0", \ + "64.6, 64.6, 64.6, 83.1, 114.4", \ + "72.4, 72.4, 72.4, 93.2, 128.8", \ + "85.5, 85.5, 85.5, 107.3, 148.1"); + } + fall_transition (inslew_load_5x5__17) { + values ("33.7, 33.7, 33.7, 46.4, 70.2", \ + "43.2, 43.2, 43.2, 56.4, 80.7", \ + "60.9, 60.9, 60.9, 74.7, 100.2", \ + "95.3, 95.3, 95.3, 109.6, 136.7", \ + "163.0, 163.0, 163.0, 178.0, 206.3"); + } + } + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("64.2, 64.2, 64.2, 84.3, 124.3", \ + "71.2, 71.2, 71.2, 91.7, 132.1", \ + "83.0, 83.0, 83.0, 104.1, 145.8", \ + "105.5, 105.5, 105.5, 127.3, 169.9", \ + "149.3, 149.3, 149.3, 171.6, 215.5"); + } + rise_transition (inslew_load_5x5__17) { + values ("126.7, 126.7, 126.7, 162.7, 235.4", \ + "164.6, 164.6, 164.6, 200.2, 272.0", \ + "239.2, 239.2, 239.2, 274.1, 344.6", \ + "386.4, 386.4, 386.4, 423.1, 492.4", \ + "682.0, 682.0, 682.0, 716.8, 790.7"); + } + cell_fall (inslew_load_5x5__17) { + values ("34.6, 34.6, 34.6, 47.6, 72.6", \ + "37.2, 37.2, 37.2, 51.4, 78.0", \ + "39.2, 39.2, 39.2, 54.8, 84.1", \ + "40.4, 40.4, 40.4, 57.4, 89.5", \ + "40.9, 40.9, 40.9, 58.8, 93.3"); + } + fall_transition (inslew_load_5x5__17) { + values ("52.2, 52.2, 52.2, 69.0, 102.9", \ + "71.8, 71.8, 71.8, 88.6, 122.1", \ + "109.8, 109.8, 109.8, 126.7, 160.1", \ + "184.6, 184.6, 184.6, 201.8, 235.8", \ + "333.6, 333.6, 333.6, 351.0, 385.5"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__17) { + values ("53.3, 53.3, 53.3, 73.6, 113.7", \ + "53.9, 53.9, 53.9, 75.0, 115.8", \ + "53.7, 53.7, 53.7, 75.5, 117.7", \ + "51.3, 51.3, 51.3, 74.2, 118.5", \ + "44.5, 44.5, 44.5, 68.4, 114.9"); + } + rise_transition (inslew_load_5x5__17) { + values ("107.7, 107.7, 107.7, 143.5, 216.0", \ + "136.1, 136.1, 136.1, 171.4, 242.9", \ + "191.5, 191.5, 191.5, 227.3, 297.1", \ + "302.6, 302.6, 302.6, 337.5, 409.2", \ + "524.3, 524.3, 524.3, 559.3, 629.2"); + } + cell_fall (inslew_load_5x5__17) { + values ("33.9, 33.9, 33.9, 48.1, 74.2", \ + "41.7, 41.7, 41.7, 57.6, 86.5", \ + "53.5, 53.5, 53.5, 71.2, 103.5", \ + "74.1, 74.1, 74.1, 93.2, 129.0", \ + "113.5, 113.5, 113.5, 133.5, 171.9"); + } + fall_transition (inslew_load_5x5__17) { + values ("45.3, 45.3, 45.3, 62.3, 96.2", \ + "68.2, 68.2, 68.2, 85.5, 119.3", \ + "111.6, 111.6, 111.6, 129.3, 163.8", \ + "196.7, 196.7, 196.7, 214.7, 250.2", \ + "365.8, 365.8, 365.8, 384.1, 420.2"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__17) { + values ("133.3, 133.3, 133.3, 171.2, 247.0", \ + "164.9, 164.9, 164.9, 202.9, 278.7", \ + "227.3, 227.3, 227.3, 265.2, 341.0", \ + "351.1, 351.1, 351.1, 389.0, 464.8", \ + "598.1, 598.1, 598.1, 636.0, 711.9"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("146.6, 146.6, 146.6, 184.5, 260.3", \ + "185.8, 185.8, 185.8, 223.7, 299.6", \ + "263.5, 263.5, 263.5, 301.4, 377.2", \ + "418.3, 418.3, 418.3, 456.2, 532.0", \ + "727.5, 727.5, 727.5, 765.4, 841.3"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__17) { + values ("130.0, 130.0, 130.0, 167.9, 243.7", \ + "164.2, 164.2, 164.2, 202.1, 277.9", \ + "232.7, 232.7, 232.7, 270.6, 346.4", \ + "369.6, 369.6, 369.6, 407.5, 483.4", \ + "643.5, 643.5, 643.5, 681.4, 757.3"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("105.3, 105.3, 105.3, 143.2, 219.1", \ + "134.5, 134.5, 134.5, 172.4, 248.3", \ + "192.9, 192.9, 192.9, 230.8, 306.7", \ + "309.7, 309.7, 309.7, 347.6, 423.4", \ + "543.3, 543.3, 543.3, 581.2, 657.0"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__17) { + values ("108.2, 108.2, 108.2, 146.2, 222.0", \ + "132.5, 132.5, 132.5, 170.4, 246.2", \ + "180.9, 180.9, 180.9, 218.8, 294.7", \ + "277.8, 277.8, 277.8, 315.7, 391.6", \ + "471.7, 471.7, 471.7, 509.6, 585.4"); + } + fall_power (energy_inslew_load_5x5__17) { + values ("89.0, 89.0, 89.0, 126.9, 202.7", \ + "119.7, 119.7, 119.7, 157.6, 233.4", \ + "181.1, 181.1, 181.1, 219.0, 294.8", \ + "303.9, 303.9, 303.9, 341.8, 417.6", \ + "549.5, 549.5, 549.5, 587.4, 663.2"); + } + } + } + } + + cell (aoi21v0x05) { + area : 0.0 ; + cell_leakage_power : 0.24 ; + leakage_power () { + when : "(!(b) & a2 & a1)" ; + value : 0.39 ; + } + leakage_power () { + when : "(!(b) & !(a2) & a1)" ; + value : 9.9e-05 ; + } + leakage_power () { + when : "(!(b) & a2 & !(a1))" ; + value : 8.7e-05 ; + } + leakage_power () { + when : "b" ; + value : 0.79 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 3.5e-05 ; + } + pin (b) { + direction : input ; + capacitance : 3.01 ; + } + pin (a2) { + direction : input ; + capacitance : 3.31 ; + } + pin (a1) { + direction : input ; + capacitance : 3.13 ; + } + pin (z) { + function : "((!(b) & !(a2)) | (!(b) & !(a1)))" ; + direction : output ; + capacitance : 3.10 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("65.7, 65.7, 65.7, 86.3, 127.1", \ + "72.7, 72.7, 72.7, 93.6, 134.9", \ + "84.6, 84.6, 84.6, 106.1, 148.6", \ + "107.2, 107.2, 107.2, 129.3, 172.8", \ + "151.0, 151.0, 151.0, 173.7, 218.6"); + } + rise_transition (inslew_load_5x5__18) { + values ("129.3, 129.3, 129.3, 166.2, 240.5", \ + "167.2, 167.2, 167.2, 203.6, 277.0", \ + "241.8, 241.8, 241.8, 277.5, 349.6", \ + "391.2, 391.2, 391.2, 426.4, 497.2", \ + "684.6, 684.6, 684.6, 720.2, 795.5"); + } + cell_fall (inslew_load_5x5__18) { + values ("35.2, 35.2, 35.2, 48.5, 74.0", \ + "37.8, 37.8, 37.8, 52.3, 79.4", \ + "39.9, 39.9, 39.9, 55.8, 85.6", \ + "41.2, 41.2, 41.2, 58.5, 91.2", \ + "41.7, 41.7, 41.7, 60.0, 95.2"); + } + fall_transition (inslew_load_5x5__18) { + values ("53.1, 53.1, 53.1, 70.1, 104.7", \ + "72.6, 72.6, 72.6, 89.7, 123.9", \ + "110.5, 110.5, 110.5, 127.8, 162.0", \ + "185.4, 185.4, 185.4, 203.0, 237.6", \ + "334.4, 334.4, 334.4, 352.2, 387.4"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("54.8, 54.8, 54.8, 75.5, 116.5", \ + "55.5, 55.5, 55.5, 77.0, 118.6", \ + "55.4, 55.4, 55.4, 77.6, 120.6", \ + "53.0, 53.0, 53.0, 76.4, 121.5", \ + "46.3, 46.3, 46.3, 70.7, 118.1"); + } + rise_transition (inslew_load_5x5__18) { + values ("110.3, 110.3, 110.3, 147.0, 221.1", \ + "138.7, 138.7, 138.7, 174.8, 247.8", \ + "195.2, 195.2, 195.2, 230.6, 302.1", \ + "305.2, 305.2, 305.2, 340.8, 414.0", \ + "526.9, 526.9, 526.9, 562.7, 634.0"); + } + cell_fall (inslew_load_5x5__18) { + values ("34.5, 34.5, 34.5, 49.0, 75.6", \ + "42.5, 42.5, 42.5, 58.7, 88.0", \ + "54.4, 54.4, 54.4, 72.3, 105.3", \ + "75.0, 75.0, 75.0, 94.5, 130.9", \ + "114.4, 114.4, 114.4, 134.8, 174.0"); + } + fall_transition (inslew_load_5x5__18) { + values ("46.0, 46.0, 46.0, 63.4, 98.1", \ + "69.0, 69.0, 69.0, 86.6, 121.2", \ + "112.4, 112.4, 112.4, 130.4, 165.7", \ + "197.5, 197.5, 197.5, 215.9, 252.1", \ + "366.6, 366.6, 366.6, 385.3, 422.2"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__18) { + values ("34.5, 34.5, 34.5, 56.9, 99.4", \ + "46.3, 46.3, 46.3, 69.6, 114.2", \ + "65.7, 65.7, 65.7, 91.2, 138.6", \ + "101.8, 101.8, 101.8, 128.7, 179.7", \ + "172.5, 172.5, 172.5, 200.3, 254.0"); + } + rise_transition (inslew_load_5x5__18) { + values ("67.5, 67.5, 67.5, 104.6, 180.2", \ + "106.4, 106.4, 106.4, 142.3, 217.0", \ + "179.0, 179.0, 179.0, 216.3, 289.9", \ + "322.0, 322.0, 322.0, 359.8, 434.4", \ + "606.6, 606.6, 606.6, 644.6, 720.2"); + } + cell_fall (inslew_load_5x5__18) { + values ("18.0, 18.0, 18.0, 32.3, 56.0", \ + "15.3, 15.3, 15.3, 32.3, 60.5", \ + "6.6, 6.6, 6.6, 26.5, 60.3", \ + "-13.3, -13.3, -13.3, 8.9, 48.3", \ + "-55.1, -55.1, -55.1, -31.2, 13.0"); + } + fall_transition (inslew_load_5x5__18) { + values ("26.1, 26.1, 26.1, 38.7, 62.9", \ + "40.1, 40.1, 40.1, 53.7, 78.8", \ + "66.6, 66.6, 66.6, 81.3, 108.3", \ + "118.3, 118.3, 118.3, 133.9, 163.2", \ + "220.6, 220.6, 220.6, 237.0, 268.3"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__18) { + values ("132.8, 132.8, 132.8, 171.5, 249.0", \ + "167.0, 167.0, 167.0, 205.7, 283.2", \ + "235.5, 235.5, 235.5, 274.2, 351.7", \ + "372.4, 372.4, 372.4, 411.2, 488.6", \ + "646.3, 646.3, 646.3, 685.1, 762.6"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("107.0, 107.0, 107.0, 145.8, 223.3", \ + "136.2, 136.2, 136.2, 175.0, 252.4", \ + "194.6, 194.6, 194.6, 233.4, 310.8", \ + "311.4, 311.4, 311.4, 350.2, 427.6", \ + "545.0, 545.0, 545.0, 583.7, 661.2"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__18) { + values ("111.1, 111.1, 111.1, 149.8, 227.3", \ + "135.3, 135.3, 135.3, 174.0, 251.5", \ + "183.7, 183.7, 183.7, 222.5, 299.9", \ + "280.6, 280.6, 280.6, 319.4, 396.9", \ + "474.5, 474.5, 474.5, 513.2, 590.7"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("90.7, 90.7, 90.7, 129.4, 206.9", \ + "121.4, 121.4, 121.4, 160.1, 237.6", \ + "182.8, 182.8, 182.8, 221.5, 299.0", \ + "305.6, 305.6, 305.6, 344.3, 421.8", \ + "551.2, 551.2, 551.2, 589.9, 667.4"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__18) { + values ("67.1, 67.1, 67.1, 105.8, 183.3", \ + "95.5, 95.5, 95.5, 134.2, 211.7", \ + "152.3, 152.3, 152.3, 191.0, 268.5", \ + "265.9, 265.9, 265.9, 304.7, 382.1", \ + "493.2, 493.2, 493.2, 531.9, 609.4"); + } + fall_power (energy_inslew_load_5x5__18) { + values ("55.5, 55.5, 55.5, 94.2, 171.7", \ + "72.2, 72.2, 72.2, 110.9, 188.4", \ + "105.6, 105.6, 105.6, 144.3, 221.8", \ + "172.3, 172.3, 172.3, 211.1, 288.5", \ + "305.9, 305.9, 305.9, 344.6, 422.1"); + } + } + } + } + + cell (aoi22v0x05) { + area : 0.0 ; + cell_leakage_power : 0.39 ; + leakage_power () { + when : "(a1 & a2 & (b1 ^ b2))" ; + value : 1.2 ; + } + leakage_power () { + when : "(!(b2) & !(b1) & a2 & a1)" ; + value : 0.78 ; + } + leakage_power () { + when : "(!(b2) & b1 & !(a2) & a1)" ; + value : 0.00013 ; + } + leakage_power () { + when : "((a1 & !(a2) & !(b1) & b2) | (!(a1) & a2 & b1 & !(b2)))" ; + value : 0.00012 ; + } + leakage_power () { + when : "(b2 & !(b1) & a2 & !(a1))" ; + value : 0.00011 ; + } + leakage_power () { + when : "(b1 & b2)" ; + value : 1.6 ; + } + leakage_power () { + when : "((a1 & !(a2) & !(b1) & !(b2)) | (!(a1) & !(a2) & b1 & !(b2)))" ; + value : 6.6e-05 ; + } + leakage_power () { + when : "(!(a1) & ((a2 & !(b1) & !(b2)) | (!(a2) & !(b1) & b2)))" ; + value : 5.5e-05 ; + } + leakage_power () { + when : "(!(b2) & !(b1) & !(a2) & !(a1))" ; + value : 2.4e-06 ; + } + pin (b2) { + direction : input ; + capacitance : 3.13 ; + } + pin (b1) { + direction : input ; + capacitance : 3.48 ; + } + pin (a2) { + direction : input ; + capacitance : 3.36 ; + } + pin (a1) { + direction : input ; + capacitance : 3.42 ; + } + pin (z) { + function : "((((!(b2) & !(a1)) | (!(b2) & !(a2))) | (!(b1) & !(a1))) | (!(b1) & !(a2)))" ; + direction : output ; + capacitance : 4.02 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("76.2, 76.2, 76.2, 102.8, 155.6", \ + "83.4, 83.4, 83.4, 110.4, 163.7", \ + "95.6, 95.6, 95.6, 123.3, 177.8", \ + "118.5, 118.5, 118.5, 147.0, 202.9", \ + "162.6, 162.6, 162.6, 191.9, 249.6"); + } + rise_transition (inslew_load_5x5__19) { + values ("148.0, 148.0, 148.0, 196.1, 292.8", \ + "185.7, 185.7, 185.7, 233.1, 329.0", \ + "259.9, 259.9, 259.9, 306.4, 400.6", \ + "409.1, 409.1, 409.1, 454.9, 547.2", \ + "702.7, 702.7, 702.7, 748.8, 844.8"); + } + cell_fall (inslew_load_5x5__19) { + values ("44.1, 44.1, 44.1, 60.8, 93.3", \ + "47.5, 47.5, 47.5, 65.5, 99.6", \ + "50.5, 50.5, 50.5, 70.3, 107.5", \ + "52.6, 52.6, 52.6, 74.3, 115.3", \ + "53.7, 53.7, 53.7, 77.0, 121.5"); + } + fall_transition (inslew_load_5x5__19) { + values ("64.2, 64.2, 64.2, 86.5, 131.9", \ + "83.7, 83.7, 83.7, 105.8, 150.3", \ + "121.8, 121.8, 121.8, 144.1, 188.2", \ + "196.8, 196.8, 196.8, 219.5, 264.1", \ + "346.0, 346.0, 346.0, 368.9, 414.4"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("65.4, 65.4, 65.4, 92.1, 145.1", \ + "66.5, 66.5, 66.5, 93.9, 147.5", \ + "66.8, 66.8, 66.8, 95.2, 150.5", \ + "65.0, 65.0, 65.0, 94.8, 152.3", \ + "58.8, 58.8, 58.8, 90.0, 150.5"); + } + rise_transition (inslew_load_5x5__19) { + values ("128.9, 128.9, 128.9, 176.8, 273.4", \ + "157.0, 157.0, 157.0, 204.2, 299.6", \ + "213.1, 213.1, 213.1, 259.3, 352.8", \ + "323.3, 323.3, 323.3, 369.6, 463.6", \ + "545.1, 545.1, 545.1, 591.5, 684.0"); + } + cell_fall (inslew_load_5x5__19) { + values ("44.2, 44.2, 44.2, 61.9, 95.3", \ + "53.3, 53.3, 53.3, 73.0, 109.2", \ + "66.3, 66.3, 66.3, 88.4, 129.0", \ + "87.9, 87.9, 87.9, 112.2, 157.5", \ + "127.8, 127.8, 127.8, 153.7, 203.1"); + } + fall_transition (inslew_load_5x5__19) { + values ("57.3, 57.3, 57.3, 79.9, 125.2", \ + "80.5, 80.5, 80.5, 103.0, 147.8", \ + "124.2, 124.2, 124.2, 147.3, 192.5", \ + "209.5, 209.5, 209.5, 233.2, 279.6", \ + "378.8, 378.8, 378.8, 402.9, 450.4"); + } + } + timing (maxd_z_b1_negative_unate) { + related_pin : "b1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("49.6, 49.6, 49.6, 77.6, 131.6", \ + "64.4, 64.4, 64.4, 93.6, 149.5", \ + "92.6, 92.6, 92.6, 123.1, 182.0", \ + "144.4, 144.4, 144.4, 177.1, 239.2", \ + "245.4, 245.4, 245.4, 279.4, 345.2"); + } + rise_transition (inslew_load_5x5__19) { + values ("92.9, 92.9, 92.9, 141.5, 240.6", \ + "134.8, 134.8, 134.8, 183.2, 280.1", \ + "219.0, 219.0, 219.0, 266.1, 363.5", \ + "382.7, 382.7, 382.7, 431.1, 526.6", \ + "708.4, 708.4, 708.4, 757.1, 853.9"); + } + cell_fall (inslew_load_5x5__19) { + values ("28.0, 28.0, 28.0, 45.8, 78.9", \ + "24.1, 24.1, 24.1, 44.0, 79.8", \ + "12.3, 12.3, 12.3, 35.2, 75.7", \ + "-15.5, -15.5, -15.5, 10.4, 57.1", \ + "-74.9, -74.9, -74.9, -46.2, 6.5"); + } + fall_transition (inslew_load_5x5__19) { + values ("44.5, 44.5, 44.5, 66.8, 111.7", \ + "57.7, 57.7, 57.7, 80.0, 124.4", \ + "82.7, 82.7, 82.7, 105.8, 150.4", \ + "131.5, 131.5, 131.5, 155.4, 201.6", \ + "227.8, 227.8, 227.8, 252.5, 300.5"); + } + } + timing (maxd_z_b2_negative_unate) { + related_pin : "b2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__19) { + values ("39.3, 39.3, 39.3, 67.8, 122.1", \ + "48.8, 48.8, 48.8, 78.4, 135.1", \ + "64.4, 64.4, 64.4, 97.2, 157.2", \ + "92.3, 92.3, 92.3, 127.4, 192.9", \ + "145.5, 145.5, 145.5, 182.3, 252.5"); + } + rise_transition (inslew_load_5x5__19) { + values ("76.0, 76.0, 76.0, 124.3, 223.0", \ + "110.7, 110.7, 110.7, 157.3, 254.4", \ + "177.7, 177.7, 177.7, 225.9, 320.9", \ + "309.2, 309.2, 309.2, 358.2, 454.9", \ + "570.5, 570.5, 570.5, 620.2, 718.4"); + } + cell_fall (inslew_load_5x5__19) { + values ("27.1, 27.1, 27.1, 46.6, 81.1", \ + "27.3, 27.3, 27.3, 50.0, 88.7", \ + "23.2, 23.2, 23.2, 49.6, 94.7", \ + "11.1, 11.1, 11.1, 40.9, 93.4", \ + "-15.7, -15.7, -15.7, 16.5, 75.8"); + } + fall_transition (inslew_load_5x5__19) { + values ("38.1, 38.1, 38.1, 60.7, 105.8", \ + "54.0, 54.0, 54.0, 77.2, 122.2", \ + "83.5, 83.5, 83.5, 107.9, 154.2", \ + "140.9, 140.9, 140.9, 166.3, 214.9", \ + "254.4, 254.4, 254.4, 280.7, 331.6"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__19) { + values ("152.5, 152.5, 152.5, 202.8, 303.3", \ + "186.7, 186.7, 186.7, 237.0, 337.6", \ + "255.2, 255.2, 255.2, 305.5, 406.1", \ + "392.1, 392.1, 392.1, 442.4, 543.0", \ + "666.0, 666.0, 666.0, 716.3, 816.9"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("132.3, 132.3, 132.3, 182.6, 283.2", \ + "161.5, 161.5, 161.5, 211.8, 312.4", \ + "219.9, 219.9, 219.9, 270.2, 370.8", \ + "336.7, 336.7, 336.7, 387.0, 487.5", \ + "570.2, 570.2, 570.2, 620.5, 721.1"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__19) { + values ("130.8, 130.8, 130.8, 181.0, 281.6", \ + "155.0, 155.0, 155.0, 205.3, 305.9", \ + "203.4, 203.4, 203.4, 253.7, 354.3", \ + "300.3, 300.3, 300.3, 350.6, 451.2", \ + "494.2, 494.2, 494.2, 544.5, 645.0"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("115.9, 115.9, 115.9, 166.2, 266.8", \ + "146.6, 146.6, 146.6, 196.9, 297.5", \ + "208.0, 208.0, 208.0, 258.3, 358.9", \ + "330.8, 330.8, 330.8, 381.1, 481.7", \ + "576.4, 576.4, 576.4, 626.7, 727.3"); + } + } + internal_power (energy_neg_z_b1) { + related_pin : "b1" ; + rise_power (energy_inslew_load_5x5__19) { + values ("94.4, 94.4, 94.4, 144.7, 245.3", \ + "128.0, 128.0, 128.0, 178.3, 278.9", \ + "195.2, 195.2, 195.2, 245.4, 346.0", \ + "329.5, 329.5, 329.5, 379.8, 480.4", \ + "598.2, 598.2, 598.2, 648.5, 749.0"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("85.0, 85.0, 85.0, 135.3, 235.9", \ + "100.7, 100.7, 100.7, 151.0, 251.6", \ + "132.1, 132.1, 132.1, 182.4, 283.0", \ + "194.9, 194.9, 194.9, 245.2, 345.8", \ + "320.4, 320.4, 320.4, 370.7, 471.3"); + } + } + internal_power (energy_neg_z_b2) { + related_pin : "b2" ; + rise_power (energy_inslew_load_5x5__19) { + values ("74.6, 74.6, 74.6, 124.9, 225.5", \ + "100.1, 100.1, 100.1, 150.4, 251.0", \ + "151.0, 151.0, 151.0, 201.3, 301.9", \ + "253.0, 253.0, 253.0, 303.3, 403.8", \ + "456.8, 456.8, 456.8, 507.1, 607.7"); + } + fall_power (energy_inslew_load_5x5__19) { + values ("68.7, 68.7, 68.7, 119.0, 219.6", \ + "86.0, 86.0, 86.0, 136.3, 236.9", \ + "120.5, 120.5, 120.5, 170.8, 271.4", \ + "189.5, 189.5, 189.5, 239.8, 340.4", \ + "327.6, 327.6, 327.6, 377.9, 478.5"); + } + } + } + } + + cell (aoi22v0x1) { + area : 0.0 ; + cell_leakage_power : 1.6 ; + leakage_power () { + when : "(b2 & b1 & a2 & a1)" ; + value : 5 ; + } + leakage_power () { + when : "(a1 & a2 & (b1 ^ b2))" ; + value : 3.6 ; + } + leakage_power () { + when : "(!(b2) & !(b1) & a2 & a1)" ; + value : 2.2 ; + } + leakage_power () { + when : "(!(b2) & b1 & !(a2) & a1)" ; + value : 0.00014 ; + } + leakage_power () { + when : "((a1 & !(a2) & !(b1) & b2) | (!(a1) & a2 & b1 & !(b2)))" ; + value : 0.00013 ; + } + leakage_power () { + when : "(b2 & !(b1) & a2 & !(a1))" ; + value : 0.00011 ; + } + leakage_power () { + when : "(!((a1 & a2)) & b1 & b2)" ; + value : 5.1 ; + } + leakage_power () { + when : "((a1 & !(a2) & !(b1) & !(b2)) | (!(a1) & !(a2) & b1 & !(b2)))" ; + value : 7.1e-05 ; + } + leakage_power () { + when : "(!(a1) & ((a2 & !(b1) & !(b2)) | (!(a2) & !(b1) & b2)))" ; + value : 5.8e-05 ; + } + leakage_power () { + when : "(!(b2) & !(b1) & !(a2) & !(a1))" ; + value : 2.5e-06 ; + } + pin (b2) { + direction : input ; + capacitance : 4.98 ; + } + pin (b1) { + direction : input ; + capacitance : 4.96 ; + } + pin (a2) { + direction : input ; + capacitance : 4.97 ; + } + pin (a1) { + direction : input ; + capacitance : 5.23 ; + } + pin (z) { + function : "((((!(b2) & !(a1)) | (!(b2) & !(a2))) | (!(b1) & !(a1))) | (!(b1) & !(a2)))" ; + direction : output ; + capacitance : 4.97 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("76.0, 76.0, 76.0, 98.2, 142.3", \ + "86.2, 86.2, 86.2, 108.7, 153.3", \ + "103.9, 103.9, 103.9, 126.9, 172.5", \ + "138.2, 138.2, 138.2, 161.7, 208.0", \ + "205.5, 205.5, 205.5, 229.5, 276.9"); + } + rise_transition (inslew_load_5x5__20) { + values ("141.8, 141.8, 141.8, 180.4, 258.3", \ + "184.8, 184.8, 184.8, 223.0, 300.1", \ + "267.7, 267.7, 267.7, 305.3, 381.3", \ + "433.4, 433.4, 433.4, 470.5, 545.0", \ + "765.2, 765.2, 765.2, 801.9, 875.6"); + } + cell_fall (inslew_load_5x5__20) { + values ("35.0, 35.0, 35.0, 46.9, 69.9", \ + "36.0, 36.0, 36.0, 49.2, 74.0", \ + "34.4, 34.4, 34.4, 49.2, 76.9", \ + "27.4, 27.4, 27.4, 43.9, 74.9", \ + "10.7, 10.7, 10.7, 28.4, 62.4"); + } + fall_transition (inslew_load_5x5__20) { + values ("50.2, 50.2, 50.2, 65.2, 95.4", \ + "66.7, 66.7, 66.7, 81.7, 111.7", \ + "98.7, 98.7, 98.7, 114.0, 144.1", \ + "161.6, 161.6, 161.6, 177.3, 208.1", \ + "286.5, 286.5, 286.5, 302.5, 334.1"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("63.9, 63.9, 63.9, 86.3, 130.5", \ + "67.7, 67.7, 67.7, 90.7, 135.6", \ + "73.3, 73.3, 73.3, 96.9, 143.2", \ + "82.9, 82.9, 82.9, 107.4, 155.0", \ + "100.5, 100.5, 100.5, 125.7, 175.1"); + } + rise_transition (inslew_load_5x5__20) { + values ("121.2, 121.2, 121.2, 159.7, 237.4", \ + "154.5, 154.5, 154.5, 192.5, 269.2", \ + "219.4, 219.4, 219.4, 256.6, 331.9", \ + "346.9, 346.9, 346.9, 386.1, 460.0", \ + "603.2, 603.2, 603.2, 640.4, 714.7"); + } + cell_fall (inslew_load_5x5__20) { + values ("34.3, 34.3, 34.3, 47.3, 71.3", \ + "39.9, 39.9, 39.9, 54.7, 81.6", \ + "46.7, 46.7, 46.7, 63.6, 94.3", \ + "56.8, 56.8, 56.8, 75.3, 110.0", \ + "74.4, 74.4, 74.4, 94.2, 131.9"); + } + fall_transition (inslew_load_5x5__20) { + values ("43.9, 43.9, 43.9, 59.1, 89.4", \ + "63.5, 63.5, 63.5, 79.0, 109.3", \ + "100.4, 100.4, 100.4, 116.4, 147.5", \ + "172.6, 172.6, 172.6, 189.1, 221.3", \ + "315.8, 315.8, 315.8, 332.7, 365.9"); + } + } + timing (maxd_z_b1_negative_unate) { + related_pin : "b1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("48.3, 48.3, 48.3, 71.9, 117.1", \ + "65.9, 65.9, 65.9, 90.5, 137.3", \ + "98.6, 98.6, 98.6, 124.2, 173.3", \ + "159.7, 159.7, 159.7, 186.4, 237.7", \ + "279.4, 279.4, 279.4, 306.9, 360.5"); + } + rise_transition (inslew_load_5x5__20) { + values ("86.3, 86.3, 86.3, 125.1, 204.3", \ + "132.6, 132.6, 132.6, 171.8, 249.3", \ + "223.6, 223.6, 223.6, 261.8, 340.2", \ + "400.3, 400.3, 400.3, 438.9, 515.4", \ + "751.4, 751.4, 751.4, 790.1, 867.3"); + } + cell_fall (inslew_load_5x5__20) { + values ("21.6, 21.6, 21.6, 34.5, 58.2", \ + "15.9, 15.9, 15.9, 30.9, 57.4", \ + "0.8, 0.8, 0.8, 18.5, 49.4", \ + "-33.2, -33.2, -33.2, -12.9, 23.3", \ + "-104.6, -104.6, -104.6, -82.2, -40.8"); + } + fall_transition (inslew_load_5x5__20) { + values ("35.0, 35.0, 35.0, 50.1, 80.1", \ + "46.2, 46.2, 46.2, 61.6, 91.6", \ + "67.4, 67.4, 67.4, 83.5, 114.4", \ + "108.5, 108.5, 108.5, 125.4, 157.9", \ + "189.6, 189.6, 189.6, 207.2, 241.3"); + } + } + timing (maxd_z_b2_negative_unate) { + related_pin : "b2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__20) { + values ("36.7, 36.7, 36.7, 60.9, 106.6", \ + "48.8, 48.8, 48.8, 73.7, 121.5", \ + "69.2, 69.2, 69.2, 96.2, 146.8", \ + "106.9, 106.9, 106.9, 135.4, 189.4", \ + "180.5, 180.5, 180.5, 209.9, 266.8"); + } + rise_transition (inslew_load_5x5__20) { + values ("67.9, 67.9, 67.9, 106.8, 185.6", \ + "107.2, 107.2, 107.2, 144.7, 222.5", \ + "181.5, 181.5, 181.5, 220.1, 296.8", \ + "327.0, 327.0, 327.0, 366.1, 443.3", \ + "616.1, 616.1, 616.1, 655.5, 733.6"); + } + cell_fall (inslew_load_5x5__20) { + values ("19.4, 19.4, 19.4, 34.3, 59.7", \ + "16.9, 16.9, 16.9, 34.5, 64.1", \ + "8.1, 8.1, 8.1, 28.8, 64.0", \ + "-12.1, -12.1, -12.1, 11.1, 52.2", \ + "-54.8, -54.8, -54.8, -29.6, 16.7"); + } + fall_transition (inslew_load_5x5__20) { + values ("28.8, 28.8, 28.8, 44.4, 74.6", \ + "42.2, 42.2, 42.2, 58.5, 89.4", \ + "67.2, 67.2, 67.2, 84.5, 117.0", \ + "116.0, 116.0, 116.0, 134.2, 168.6", \ + "212.7, 212.7, 212.7, 231.5, 267.7"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__20) { + values ("225.2, 225.2, 225.2, 287.3, 411.6", \ + "284.7, 284.7, 284.7, 346.8, 471.1", \ + "403.6, 403.6, 403.6, 465.8, 590.1", \ + "641.6, 641.6, 641.6, 703.8, 828.0", \ + "1117.5, 1117.5, 1117.5, 1179.7, 1304.0"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("184.0, 184.0, 184.0, 246.1, 370.4", \ + "225.2, 225.2, 225.2, 287.3, 411.6", \ + "307.5, 307.5, 307.5, 369.7, 494.0", \ + "472.3, 472.3, 472.3, 534.5, 658.8", \ + "801.9, 801.9, 801.9, 864.0, 988.3"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__20) { + values ("189.2, 189.2, 189.2, 251.3, 375.6", \ + "233.4, 233.4, 233.4, 295.6, 419.9", \ + "321.9, 321.9, 321.9, 384.0, 508.3", \ + "498.8, 498.8, 498.8, 561.0, 685.3", \ + "852.7, 852.7, 852.7, 914.9, 1039.2"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("155.8, 155.8, 155.8, 218.0, 342.3", \ + "199.8, 199.8, 199.8, 262.0, 386.3", \ + "287.9, 287.9, 287.9, 350.0, 474.3", \ + "463.9, 463.9, 463.9, 526.0, 650.3", \ + "815.9, 815.9, 815.9, 878.1, 1002.4"); + } + } + internal_power (energy_neg_z_b1) { + related_pin : "b1" ; + rise_power (energy_inslew_load_5x5__20) { + values ("137.7, 137.7, 137.7, 199.9, 324.2", \ + "194.4, 194.4, 194.4, 256.5, 380.8", \ + "307.7, 307.7, 307.7, 369.8, 494.1", \ + "534.3, 534.3, 534.3, 596.4, 720.7", \ + "987.4, 987.4, 987.4, 1049.6, 1173.9"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("116.6, 116.6, 116.6, 178.7, 303.0", \ + "138.2, 138.2, 138.2, 200.4, 324.7", \ + "181.6, 181.6, 181.6, 243.7, 368.0", \ + "268.2, 268.2, 268.2, 330.4, 454.6", \ + "441.5, 441.5, 441.5, 503.7, 628.0"); + } + } + internal_power (energy_neg_z_b2) { + related_pin : "b2" ; + rise_power (energy_inslew_load_5x5__20) { + values ("104.8, 104.8, 104.8, 167.0, 291.2", \ + "149.3, 149.3, 149.3, 211.4, 335.7", \ + "238.2, 238.2, 238.2, 300.3, 424.6", \ + "416.0, 416.0, 416.0, 478.2, 602.5", \ + "771.7, 771.7, 771.7, 833.8, 958.1"); + } + fall_power (energy_inslew_load_5x5__20) { + values ("88.3, 88.3, 88.3, 150.5, 274.8", \ + "112.7, 112.7, 112.7, 174.8, 299.1", \ + "161.5, 161.5, 161.5, 223.6, 347.9", \ + "259.0, 259.0, 259.0, 321.1, 445.4", \ + "454.0, 454.0, 454.0, 516.2, 640.5"); + } + } + } + } + + cell (aoi22v5x05) { + area : 0.0 ; + cell_leakage_power : 0.39 ; + leakage_power () { + when : "(a1 & a2 & (b1 ^ b2))" ; + value : 1.2 ; + } + leakage_power () { + when : "(!(b2) & !(b1) & a2 & a1)" ; + value : 0.78 ; + } + leakage_power () { + when : "(!(b2) & b1 & !(a2) & a1)" ; + value : 0.00013 ; + } + leakage_power () { + when : "((a1 & !(a2) & !(b1) & b2) | (!(a1) & a2 & b1 & !(b2)))" ; + value : 0.00012 ; + } + leakage_power () { + when : "(b2 & !(b1) & a2 & !(a1))" ; + value : 0.00011 ; + } + leakage_power () { + when : "(b1 & b2)" ; + value : 1.6 ; + } + leakage_power () { + when : "((a1 & !(a2) & !(b1) & !(b2)) | (!(a1) & !(a2) & b1 & !(b2)))" ; + value : 6.6e-05 ; + } + leakage_power () { + when : "(!(a1) & ((a2 & !(b1) & !(b2)) | (!(a2) & !(b1) & b2)))" ; + value : 5.5e-05 ; + } + leakage_power () { + when : "(!(b2) & !(b1) & !(a2) & !(a1))" ; + value : 2.4e-06 ; + } + pin (b2) { + direction : input ; + capacitance : 3.26 ; + } + pin (b1) { + direction : input ; + capacitance : 3.22 ; + } + pin (a2) { + direction : input ; + capacitance : 3.35 ; + } + pin (a1) { + direction : input ; + capacitance : 4.45 ; + } + pin (z) { + function : "((((!(b2) & !(a2)) | (!(b2) & !(a1))) | (!(b1) & !(a2))) | (!(b1) & !(a1)))" ; + direction : output ; + capacitance : 3.86 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("71.1, 71.1, 71.1, 96.6, 147.3", \ + "78.2, 78.2, 78.2, 104.2, 155.3", \ + "90.3, 90.3, 90.3, 116.9, 169.3", \ + "113.0, 113.0, 113.0, 140.5, 194.1", \ + "157.0, 157.0, 157.0, 185.2, 240.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("139.0, 139.0, 139.0, 184.9, 277.6", \ + "176.8, 176.8, 176.8, 222.1, 313.8", \ + "251.1, 251.1, 251.1, 295.6, 385.7", \ + "400.4, 400.4, 400.4, 444.3, 532.6", \ + "693.9, 693.9, 693.9, 738.2, 830.4"); + } + cell_fall (inslew_load_5x5__21) { + values ("42.2, 42.2, 42.2, 58.3, 89.5", \ + "45.5, 45.5, 45.5, 62.8, 95.7", \ + "48.3, 48.3, 48.3, 67.4, 103.2", \ + "50.2, 50.2, 50.2, 71.1, 110.7", \ + "51.2, 51.2, 51.2, 73.5, 116.4"); + } + fall_transition (inslew_load_5x5__21) { + values ("61.8, 61.8, 61.8, 83.1, 126.6", \ + "81.3, 81.3, 81.3, 102.5, 145.1", \ + "119.4, 119.4, 119.4, 140.8, 183.1", \ + "194.4, 194.4, 194.4, 216.1, 259.0", \ + "343.5, 343.5, 343.5, 365.5, 409.1"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("60.3, 60.3, 60.3, 86.0, 136.7", \ + "61.2, 61.2, 61.2, 87.6, 139.1", \ + "61.3, 61.3, 61.3, 88.7, 141.9", \ + "59.2, 59.2, 59.2, 88.0, 143.4", \ + "52.7, 52.7, 52.7, 82.8, 141.1"); + } + rise_transition (inslew_load_5x5__21) { + values ("119.9, 119.9, 119.9, 165.7, 258.2", \ + "148.1, 148.1, 148.1, 193.2, 284.5", \ + "204.5, 204.5, 204.5, 248.6, 338.0", \ + "314.5, 314.5, 314.5, 358.9, 449.1", \ + "536.3, 536.3, 536.3, 580.8, 669.4"); + } + cell_fall (inslew_load_5x5__21) { + values ("42.2, 42.2, 42.2, 59.3, 91.4", \ + "51.1, 51.1, 51.1, 70.1, 105.1", \ + "63.8, 63.8, 63.8, 85.2, 124.4", \ + "85.2, 85.2, 85.2, 108.6, 152.4", \ + "124.9, 124.9, 124.9, 149.9, 197.5"); + } + fall_transition (inslew_load_5x5__21) { + values ("54.9, 54.9, 54.9, 76.5, 119.9", \ + "78.1, 78.1, 78.1, 99.7, 142.6", \ + "121.7, 121.7, 121.7, 143.9, 187.3", \ + "207.0, 207.0, 207.0, 229.7, 274.2", \ + "376.2, 376.2, 376.2, 399.3, 444.9"); + } + } + timing (maxd_z_b1_negative_unate) { + related_pin : "b1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("48.3, 48.3, 48.3, 75.4, 127.2", \ + "64.1, 64.1, 64.1, 92.4, 146.1", \ + "92.1, 92.1, 92.1, 121.9, 178.5", \ + "143.8, 143.8, 143.8, 175.3, 235.2", \ + "244.8, 244.8, 244.8, 277.4, 340.7"); + } + rise_transition (inslew_load_5x5__21) { + values ("89.7, 89.7, 89.7, 136.2, 231.1", \ + "133.2, 133.2, 133.2, 179.8, 272.4", \ + "217.4, 217.4, 217.4, 263.1, 355.1", \ + "381.1, 381.1, 381.1, 427.5, 519.2", \ + "706.7, 706.7, 706.7, 753.4, 846.3"); + } + cell_fall (inslew_load_5x5__21) { + values ("27.3, 27.3, 27.3, 44.3, 76.2", \ + "23.2, 23.2, 23.2, 42.4, 76.9", \ + "11.3, 11.3, 11.3, 33.4, 72.5", \ + "-16.7, -16.7, -16.7, 8.3, 53.4", \ + "-76.1, -76.1, -76.1, -48.6, 2.3"); + } + fall_transition (inslew_load_5x5__21) { + values ("43.6, 43.6, 43.6, 64.9, 107.9", \ + "56.7, 56.7, 56.7, 78.2, 120.7", \ + "81.8, 81.8, 81.8, 103.9, 146.7", \ + "130.5, 130.5, 130.5, 153.4, 197.8", \ + "226.7, 226.7, 226.7, 250.4, 296.6"); + } + } + timing (maxd_z_b2_negative_unate) { + related_pin : "b2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__21) { + values ("38.1, 38.1, 38.1, 65.6, 117.8", \ + "48.3, 48.3, 48.3, 77.0, 131.6", \ + "63.8, 63.8, 63.8, 95.4, 153.7", \ + "91.5, 91.5, 91.5, 125.3, 188.5", \ + "144.6, 144.6, 144.6, 180.0, 247.6"); + } + rise_transition (inslew_load_5x5__21) { + values ("72.7, 72.7, 72.7, 119.1, 213.6", \ + "109.0, 109.0, 109.0, 153.9, 246.9", \ + "176.0, 176.0, 176.0, 222.3, 314.0", \ + "307.4, 307.4, 307.4, 354.5, 447.3", \ + "568.8, 568.8, 568.8, 616.4, 710.6"); + } + cell_fall (inslew_load_5x5__21) { + values ("26.3, 26.3, 26.3, 45.1, 78.3", \ + "26.3, 26.3, 26.3, 48.2, 85.7", \ + "22.0, 22.0, 22.0, 47.5, 91.2", \ + "9.8, 9.8, 9.8, 38.5, 89.3", \ + "-17.1, -17.1, -17.1, 13.8, 71.1"); + } + fall_transition (inslew_load_5x5__21) { + values ("37.1, 37.1, 37.1, 58.8, 102.0", \ + "53.0, 53.0, 53.0, 75.3, 118.4", \ + "82.5, 82.5, 82.5, 105.9, 150.4", \ + "139.8, 139.8, 139.8, 164.2, 211.0", \ + "253.3, 253.3, 253.3, 278.6, 327.4"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("142.9, 142.9, 142.9, 191.1, 287.5", \ + "177.2, 177.2, 177.2, 225.4, 321.7", \ + "245.7, 245.7, 245.7, 293.8, 390.2", \ + "382.6, 382.6, 382.6, 430.8, 527.2", \ + "656.5, 656.5, 656.5, 704.7, 801.1"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("126.9, 126.9, 126.9, 175.1, 271.5", \ + "156.1, 156.1, 156.1, 204.3, 300.7", \ + "214.5, 214.5, 214.5, 262.7, 359.1", \ + "331.3, 331.3, 331.3, 379.5, 475.8", \ + "564.8, 564.8, 564.8, 613.0, 709.4"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("121.2, 121.2, 121.2, 169.4, 265.8", \ + "145.5, 145.5, 145.5, 193.6, 290.0", \ + "193.9, 193.9, 193.9, 242.1, 338.5", \ + "290.8, 290.8, 290.8, 339.0, 435.4", \ + "484.6, 484.6, 484.6, 532.8, 629.2"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("110.5, 110.5, 110.5, 158.7, 255.1", \ + "141.2, 141.2, 141.2, 189.4, 285.8", \ + "202.6, 202.6, 202.6, 250.8, 347.2", \ + "325.4, 325.4, 325.4, 373.6, 470.0", \ + "571.0, 571.0, 571.0, 619.2, 715.6"); + } + } + internal_power (energy_neg_z_b1) { + related_pin : "b1" ; + rise_power (energy_inslew_load_5x5__21) { + values ("92.3, 92.3, 92.3, 140.5, 236.9", \ + "125.9, 125.9, 125.9, 174.1, 270.5", \ + "193.1, 193.1, 193.1, 241.2, 337.6", \ + "327.4, 327.4, 327.4, 375.6, 472.0", \ + "596.1, 596.1, 596.1, 644.3, 740.6"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("82.9, 82.9, 82.9, 131.1, 227.5", \ + "98.6, 98.6, 98.6, 146.8, 243.2", \ + "130.0, 130.0, 130.0, 178.2, 274.6", \ + "192.8, 192.8, 192.8, 241.0, 337.3", \ + "318.3, 318.3, 318.3, 366.5, 462.9"); + } + } + internal_power (energy_neg_z_b2) { + related_pin : "b2" ; + rise_power (energy_inslew_load_5x5__21) { + values ("72.5, 72.5, 72.5, 120.7, 217.1", \ + "98.0, 98.0, 98.0, 146.2, 242.5", \ + "148.9, 148.9, 148.9, 197.1, 293.5", \ + "250.9, 250.9, 250.9, 299.1, 395.4", \ + "454.7, 454.7, 454.7, 502.9, 599.3"); + } + fall_power (energy_inslew_load_5x5__21) { + values ("66.6, 66.6, 66.6, 114.8, 211.2", \ + "83.9, 83.9, 83.9, 132.1, 228.4", \ + "118.4, 118.4, 118.4, 166.6, 263.0", \ + "187.4, 187.4, 187.4, 235.6, 332.0", \ + "325.5, 325.5, 325.5, 373.7, 470.1"); + } + } + } + } + + cell (aoi31v0x05) { + area : 0.0 ; + cell_leakage_power : 0.25 ; + leakage_power () { + when : "(!(b) & a3 & a2 & a1)" ; + value : 0.59 ; + } + leakage_power () { + when : "(!(b) & !(a3) & a2 & a1)" ; + value : 8.1e-05 ; + } + leakage_power () { + when : "(!(b) & a3 & !(a2) & a1)" ; + value : 7.2e-05 ; + } + leakage_power () { + when : "(!(b) & a3 & a2 & !(a1))" ; + value : 7e-05 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(a3) & !(b))" ; + value : 3.5e-05 ; + } + leakage_power () { + when : "b" ; + value : 1.2 ; + } + leakage_power () { + when : "(!(a1) & !(a2) & !(b))" ; + value : 3.4e-05 ; + } + pin (b) { + direction : input ; + capacitance : 3.12 ; + } + pin (a3) { + direction : input ; + capacitance : 3.66 ; + } + pin (a2) { + direction : input ; + capacitance : 3.69 ; + } + pin (a1) { + direction : input ; + capacitance : 3.90 ; + } + pin (z) { + function : "(((!(b) & !(a1)) | (!(b) & !(a2))) | (!(b) & !(a3)))" ; + direction : output ; + capacitance : 4.58 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("95.8, 95.8, 95.8, 125.9, 186.0", \ + "111.2, 111.2, 111.2, 141.6, 202.1", \ + "138.8, 138.8, 138.8, 169.9, 230.9", \ + "192.5, 192.5, 192.5, 223.9, 286.6", \ + "298.6, 298.6, 298.6, 330.5, 393.6"); + } + rise_transition (inslew_load_5x5__22) { + values ("180.7, 180.7, 180.7, 235.6, 346.1", \ + "232.3, 232.3, 232.3, 286.7, 396.5", \ + "331.1, 331.1, 331.1, 384.9, 493.3", \ + "528.2, 528.2, 528.2, 581.1, 687.8", \ + "922.7, 922.7, 922.7, 975.1, 1080.3"); + } + cell_fall (inslew_load_5x5__22) { + values ("40.5, 40.5, 40.5, 57.1, 89.5", \ + "38.5, 38.5, 38.5, 56.0, 89.6", \ + "31.6, 31.6, 31.6, 50.7, 86.7", \ + "14.1, 14.1, 14.1, 35.2, 74.8", \ + "-24.4, -24.4, -24.4, -1.6, 41.8"); + } + fall_transition (inslew_load_5x5__22) { + values ("69.4, 69.4, 69.4, 93.9, 143.4", \ + "84.8, 84.8, 84.8, 109.2, 157.8", \ + "115.4, 115.4, 115.4, 139.7, 188.3", \ + "176.0, 176.0, 176.0, 200.6, 249.1", \ + "296.5, 296.5, 296.5, 321.4, 370.7"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("83.3, 83.3, 83.3, 113.6, 173.7", \ + "91.9, 91.9, 91.9, 122.6, 183.3", \ + "106.3, 106.3, 106.3, 137.7, 199.5", \ + "133.6, 133.6, 133.6, 165.8, 229.0", \ + "186.3, 186.3, 186.3, 219.4, 284.4"); + } + rise_transition (inslew_load_5x5__22) { + values ("158.4, 158.4, 158.4, 213.2, 323.5", \ + "198.6, 198.6, 198.6, 252.7, 362.2", \ + "276.3, 276.3, 276.3, 329.5, 437.3", \ + "431.9, 431.9, 431.9, 484.2, 589.9", \ + "738.8, 738.8, 738.8, 795.6, 899.8"); + } + cell_fall (inslew_load_5x5__22) { + values ("39.1, 39.1, 39.1, 56.3, 89.2", \ + "41.7, 41.7, 41.7, 60.5, 95.6", \ + "42.8, 42.8, 42.8, 64.0, 102.8", \ + "41.1, 41.1, 41.1, 64.5, 107.9", \ + "34.4, 34.4, 34.4, 59.6, 107.3"); + } + fall_transition (inslew_load_5x5__22) { + values ("60.8, 60.8, 60.8, 85.2, 134.7", \ + "79.1, 79.1, 79.1, 103.6, 152.5", \ + "114.4, 114.4, 114.4, 139.3, 188.2", \ + "183.7, 183.7, 183.7, 209.0, 258.9", \ + "321.3, 321.3, 321.3, 347.0, 397.9"); + } + } + timing (maxd_z_a3_negative_unate) { + related_pin : "a3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("70.4, 70.4, 70.4, 100.8, 161.0", \ + "74.2, 74.2, 74.2, 105.2, 166.1", \ + "79.1, 79.1, 79.1, 111.2, 173.6", \ + "87.4, 87.4, 87.4, 120.7, 185.2", \ + "101.8, 101.8, 101.8, 136.3, 203.6"); + } + rise_transition (inslew_load_5x5__22) { + values ("135.4, 135.4, 135.4, 190.0, 300.1", \ + "168.1, 168.1, 168.1, 221.9, 331.0", \ + "231.7, 231.7, 231.7, 284.5, 391.6", \ + "356.8, 356.8, 356.8, 411.5, 516.3", \ + "608.3, 608.3, 608.3, 661.0, 766.2"); + } + cell_fall (inslew_load_5x5__22) { + values ("35.1, 35.1, 35.1, 53.5, 87.5", \ + "41.4, 41.4, 41.4, 62.0, 99.1", \ + "49.2, 49.2, 49.2, 72.6, 114.5", \ + "60.9, 60.9, 60.9, 86.7, 134.1", \ + "81.6, 81.6, 81.6, 109.2, 161.2"); + } + fall_transition (inslew_load_5x5__22) { + values ("51.1, 51.1, 51.1, 75.8, 125.7", \ + "71.8, 71.8, 71.8, 96.8, 146.2", \ + "110.8, 110.8, 110.8, 136.5, 186.6", \ + "187.0, 187.0, 187.0, 213.3, 264.8", \ + "338.3, 338.3, 338.3, 365.1, 417.8"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__22) { + values ("45.7, 45.7, 45.7, 77.8, 139.2", \ + "57.3, 57.3, 57.3, 90.7, 154.4", \ + "77.7, 77.7, 77.7, 113.7, 180.9", \ + "114.5, 114.5, 114.5, 153.1, 225.4", \ + "185.6, 185.6, 185.6, 226.0, 303.3"); + } + rise_transition (inslew_load_5x5__22) { + values ("86.6, 86.6, 86.6, 141.8, 254.8", \ + "123.7, 123.7, 123.7, 178.3, 288.6", \ + "196.9, 196.9, 196.9, 251.3, 361.7", \ + "340.2, 340.2, 340.2, 395.6, 505.0", \ + "624.9, 624.9, 624.9, 680.9, 791.9"); + } + cell_fall (inslew_load_5x5__22) { + values ("25.1, 25.1, 25.1, 44.0, 76.6", \ + "23.8, 23.8, 23.8, 46.4, 84.1", \ + "16.4, 16.4, 16.4, 43.3, 88.4", \ + "-2.5, -2.5, -2.5, 28.3, 82.0", \ + "-43.6, -43.6, -43.6, -9.6, 52.0"); + } + fall_transition (inslew_load_5x5__22) { + values ("32.1, 32.1, 32.1, 50.3, 86.1", \ + "46.7, 46.7, 46.7, 65.9, 101.9", \ + "73.7, 73.7, 73.7, 94.4, 132.6", \ + "125.8, 125.8, 125.8, 148.1, 189.5", \ + "228.4, 228.4, 228.4, 252.1, 296.8"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__22) { + values ("190.4, 190.4, 190.4, 247.7, 362.3", \ + "237.9, 237.9, 237.9, 295.2, 409.8", \ + "332.9, 332.9, 332.9, 390.2, 504.8", \ + "522.8, 522.8, 522.8, 580.1, 694.7", \ + "902.7, 902.7, 902.7, 960.0, 1074.6"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("150.2, 150.2, 150.2, 207.5, 322.1", \ + "176.4, 176.4, 176.4, 233.7, 348.3", \ + "228.7, 228.7, 228.7, 286.0, 400.6", \ + "333.3, 333.3, 333.3, 390.6, 505.2", \ + "542.5, 542.5, 542.5, 599.8, 714.4"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__22) { + values ("164.6, 164.6, 164.6, 221.9, 336.5", \ + "200.6, 200.6, 200.6, 257.9, 372.5", \ + "272.7, 272.7, 272.7, 330.0, 444.6", \ + "416.7, 416.7, 416.7, 474.0, 588.6", \ + "704.9, 704.9, 704.9, 762.2, 876.8"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("128.9, 128.9, 128.9, 186.2, 300.8", \ + "157.2, 157.2, 157.2, 214.5, 329.1", \ + "213.8, 213.8, 213.8, 271.1, 385.7", \ + "327.1, 327.1, 327.1, 384.4, 498.9", \ + "553.5, 553.5, 553.5, 610.8, 725.4"); + } + } + internal_power (energy_neg_z_a3) { + related_pin : "a3" ; + rise_power (energy_inslew_load_5x5__22) { + values ("138.8, 138.8, 138.8, 196.1, 310.7", \ + "167.0, 167.0, 167.0, 224.3, 338.9", \ + "223.5, 223.5, 223.5, 280.8, 395.4", \ + "336.4, 336.4, 336.4, 393.7, 508.3", \ + "562.3, 562.3, 562.3, 619.6, 734.1"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("106.4, 106.4, 106.4, 163.7, 278.3", \ + "136.0, 136.0, 136.0, 193.3, 307.9", \ + "195.3, 195.3, 195.3, 252.6, 367.2", \ + "313.9, 313.9, 313.9, 371.1, 485.7", \ + "551.0, 551.0, 551.0, 608.3, 722.9"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__22) { + values ("85.9, 85.9, 85.9, 143.2, 257.8", \ + "114.3, 114.3, 114.3, 171.6, 286.2", \ + "171.1, 171.1, 171.1, 228.4, 343.0", \ + "284.7, 284.7, 284.7, 342.0, 456.6", \ + "512.0, 512.0, 512.0, 569.3, 683.9"); + } + fall_power (energy_inslew_load_5x5__22) { + values ("73.8, 73.8, 73.8, 131.1, 245.7", \ + "90.5, 90.5, 90.5, 147.8, 262.4", \ + "123.9, 123.9, 123.9, 181.2, 295.8", \ + "190.6, 190.6, 190.6, 247.9, 362.5", \ + "324.2, 324.2, 324.2, 381.5, 496.0"); + } + } + } + } + + cell (aoi31v0x1) { + area : 0.0 ; + cell_leakage_power : 0.78 ; + leakage_power () { + when : "(!(b) & a3 & a2 & a1)" ; + value : 1.7 ; + } + leakage_power () { + when : "(!(b) & !(a3) & a2 & a1)" ; + value : 0.00015 ; + } + leakage_power () { + when : "(!(b) & a3 & !(a2) & a1)" ; + value : 0.00014 ; + } + leakage_power () { + when : "(!(b) & a3 & a2 & !(a1))" ; + value : 0.00013 ; + } + leakage_power () { + when : "((a1 & !(a2) & !(a3) & !(b)) | (!(a1) & (a2 ^ a3) & !(b)))" ; + value : 6.7e-05 ; + } + leakage_power () { + when : "b" ; + value : 3.8 ; + } + leakage_power () { + when : "(!(b) & !(a3) & !(a2) & !(a1))" ; + value : 6.6e-05 ; + } + pin (b) { + direction : input ; + capacitance : 4.38 ; + } + pin (a3) { + direction : input ; + capacitance : 5.31 ; + } + pin (a2) { + direction : input ; + capacitance : 5.29 ; + } + pin (a1) { + direction : input ; + capacitance : 5.08 ; + } + pin (z) { + function : "(((!(b) & !(a1)) | (!(b) & !(a2))) | (!(b) & !(a3)))" ; + direction : output ; + capacitance : 4.24 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("90.8, 90.8, 90.8, 109.6, 147.3", \ + "109.0, 109.0, 109.0, 128.0, 166.0", \ + "141.6, 141.6, 141.6, 160.8, 199.1", \ + "204.2, 204.2, 204.2, 223.8, 262.6", \ + "329.1, 329.1, 329.1, 348.9, 388.2"); + } + rise_transition (inslew_load_5x5__23) { + values ("165.1, 165.1, 165.1, 198.2, 264.7", \ + "221.4, 221.4, 221.4, 254.1, 320.2", \ + "327.3, 327.3, 327.3, 359.8, 425.0", \ + "537.3, 537.3, 537.3, 569.3, 633.6", \ + "956.9, 956.9, 956.9, 988.6, 1052.2"); + } + cell_fall (inslew_load_5x5__23) { + values ("31.7, 31.7, 31.7, 41.1, 59.6", \ + "28.0, 28.0, 28.0, 38.2, 57.9", \ + "17.9, 17.9, 17.9, 29.3, 50.9", \ + "-5.6, -5.6, -5.6, 7.0, 31.1", \ + "-55.7, -55.7, -55.7, -42.0, -15.5"); + } + fall_transition (inslew_load_5x5__23) { + values ("55.8, 55.8, 55.8, 69.4, 96.6", \ + "69.7, 69.7, 69.7, 83.2, 110.3", \ + "97.1, 97.1, 97.1, 110.8, 137.8", \ + "151.3, 151.3, 151.3, 165.2, 192.6", \ + "258.9, 258.9, 258.9, 273.0, 301.0"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("77.3, 77.3, 77.3, 96.3, 134.0", \ + "88.1, 88.1, 88.1, 107.4, 145.5", \ + "106.3, 106.3, 106.3, 126.0, 165.1", \ + "141.4, 141.4, 141.4, 161.5, 201.1", \ + "210.3, 210.3, 210.3, 230.7, 271.3"); + } + rise_transition (inslew_load_5x5__23) { + values ("141.9, 141.9, 141.9, 174.9, 241.3", \ + "186.2, 186.2, 186.2, 218.9, 284.5", \ + "270.2, 270.2, 270.2, 302.3, 367.0", \ + "437.2, 437.2, 437.2, 468.9, 532.5", \ + "771.4, 771.4, 771.4, 802.7, 865.6"); + } + cell_fall (inslew_load_5x5__23) { + values ("29.8, 29.8, 29.8, 40.0, 59.2", \ + "30.3, 30.3, 30.3, 41.7, 62.8", \ + "27.8, 27.8, 27.8, 40.6, 64.5", \ + "19.5, 19.5, 19.5, 33.7, 60.4", \ + "0.7, 0.7, 0.7, 15.9, 45.0"); + } + fall_transition (inslew_load_5x5__23) { + values ("47.6, 47.6, 47.6, 61.3, 88.5", \ + "64.3, 64.3, 64.3, 78.1, 105.3", \ + "96.2, 96.2, 96.2, 110.3, 138.0", \ + "159.1, 159.1, 159.1, 173.5, 201.8", \ + "284.0, 284.0, 284.0, 298.6, 327.5"); + } + } + timing (maxd_z_a3_negative_unate) { + related_pin : "a3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("63.3, 63.3, 63.3, 82.5, 120.4", \ + "68.7, 68.7, 68.7, 88.5, 126.9", \ + "77.2, 77.2, 77.2, 97.3, 136.8", \ + "92.5, 92.5, 92.5, 113.3, 154.0", \ + "121.8, 121.8, 121.8, 143.1, 185.1"); + } + rise_transition (inslew_load_5x5__23) { + values ("118.3, 118.3, 118.3, 151.0, 217.2", \ + "154.7, 154.7, 154.7, 187.1, 252.4", \ + "224.2, 224.2, 224.2, 256.0, 320.2", \ + "360.4, 360.4, 360.4, 394.1, 457.1", \ + "633.8, 633.8, 633.8, 665.5, 728.9"); + } + cell_fall (inslew_load_5x5__23) { + values ("25.4, 25.4, 25.4, 36.5, 57.0", \ + "28.9, 28.9, 28.9, 41.8, 64.8", \ + "32.6, 32.6, 32.6, 47.1, 73.4", \ + "37.3, 37.3, 37.3, 53.0, 82.5", \ + "45.0, 45.0, 45.0, 61.6, 93.5"); + } + fall_transition (inslew_load_5x5__23) { + values ("38.4, 38.4, 38.4, 52.1, 79.8", \ + "57.1, 57.1, 57.1, 71.3, 99.1", \ + "92.6, 92.6, 92.6, 107.2, 135.8", \ + "162.1, 162.1, 162.1, 177.1, 206.4", \ + "300.4, 300.4, 300.4, 315.6, 345.6"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__23) { + values ("30.4, 30.4, 30.4, 51.4, 90.7", \ + "37.1, 37.1, 37.1, 59.1, 100.6", \ + "47.5, 47.5, 47.5, 71.9, 116.6", \ + "65.6, 65.6, 65.6, 91.6, 140.4", \ + "100.2, 100.2, 100.2, 127.2, 179.2"); + } + rise_transition (inslew_load_5x5__23) { + values ("60.5, 60.5, 60.5, 93.7, 160.6", \ + "92.6, 92.6, 92.6, 124.6, 190.7", \ + "153.8, 153.8, 153.8, 187.1, 252.5", \ + "274.3, 274.3, 274.3, 308.2, 374.9", \ + "514.0, 514.0, 514.0, 548.3, 616.0"); + } + cell_fall (inslew_load_5x5__23) { + values ("22.4, 22.4, 22.4, 37.9, 64.0", \ + "23.5, 23.5, 23.5, 41.5, 71.9", \ + "22.1, 22.1, 22.1, 42.7, 78.3", \ + "16.5, 16.5, 16.5, 39.2, 80.1", \ + "3.7, 3.7, 3.7, 27.8, 72.9"); + } + fall_transition (inslew_load_5x5__23) { + values ("28.1, 28.1, 28.1, 42.1, 69.2", \ + "45.1, 45.1, 45.1, 59.8, 87.5", \ + "76.8, 76.8, 76.8, 92.5, 121.8", \ + "138.6, 138.6, 138.6, 155.1, 186.4", \ + "261.3, 261.3, 261.3, 278.3, 311.3"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__23) { + values ("268.8, 268.8, 268.8, 321.8, 427.9", \ + "346.9, 346.9, 346.9, 400.0, 506.0", \ + "503.2, 503.2, 503.2, 556.2, 662.3", \ + "815.6, 815.6, 815.6, 868.7, 974.8", \ + "1440.6, 1440.6, 1440.6, 1493.6, 1599.7"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("196.0, 196.0, 196.0, 249.0, 355.1", \ + "233.5, 233.5, 233.5, 286.5, 392.6", \ + "308.5, 308.5, 308.5, 361.5, 467.6", \ + "458.4, 458.4, 458.4, 511.5, 617.5", \ + "758.4, 758.4, 758.4, 811.4, 917.5"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__23) { + values ("227.4, 227.4, 227.4, 280.4, 386.5", \ + "287.4, 287.4, 287.4, 340.4, 446.5", \ + "407.3, 407.3, 407.3, 460.4, 566.4", \ + "647.3, 647.3, 647.3, 700.3, 806.4", \ + "1127.2, 1127.2, 1127.2, 1180.2, 1286.3"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("162.5, 162.5, 162.5, 215.5, 321.6", \ + "203.9, 203.9, 203.9, 256.9, 363.0", \ + "286.8, 286.8, 286.8, 339.8, 445.9", \ + "452.5, 452.5, 452.5, 505.5, 611.6", \ + "784.0, 784.0, 784.0, 837.0, 943.1"); + } + } + internal_power (energy_neg_z_a3) { + related_pin : "a3" ; + rise_power (energy_inslew_load_5x5__23) { + values ("186.2, 186.2, 186.2, 239.3, 345.3", \ + "234.0, 234.0, 234.0, 287.1, 393.1", \ + "329.6, 329.6, 329.6, 382.6, 488.7", \ + "520.7, 520.7, 520.7, 573.7, 679.8", \ + "902.9, 902.9, 902.9, 956.0, 1062.1"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("126.9, 126.9, 126.9, 179.9, 286.0", \ + "170.7, 170.7, 170.7, 223.7, 329.8", \ + "258.2, 258.2, 258.2, 311.2, 417.3", \ + "433.2, 433.2, 433.2, 486.2, 592.3", \ + "783.2, 783.2, 783.2, 836.3, 942.4"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__23) { + values ("88.0, 88.0, 88.0, 141.0, 247.1", \ + "123.0, 123.0, 123.0, 176.0, 282.1", \ + "192.9, 192.9, 192.9, 245.9, 352.0", \ + "332.7, 332.7, 332.7, 385.7, 491.8", \ + "612.4, 612.4, 612.4, 665.4, 771.5"); + } + fall_power (energy_inslew_load_5x5__23) { + values ("80.2, 80.2, 80.2, 133.2, 239.3", \ + "107.3, 107.3, 107.3, 160.4, 266.4", \ + "161.6, 161.6, 161.6, 214.7, 320.7", \ + "270.2, 270.2, 270.2, 323.3, 429.3", \ + "487.4, 487.4, 487.4, 540.5, 646.5"); + } + } + } + } + + cell (aoi31v0x2) { + area : 0.0 ; + cell_leakage_power : 2 ; + leakage_power () { + when : "(!(b) & a3 & a2 & a1)" ; + value : 3.9 ; + } + leakage_power () { + when : "(!(b) & !(a3) & a2 & a1)" ; + value : 0.00028 ; + } + leakage_power () { + when : "((a1 ^ a2) & a3 & !(b))" ; + value : 0.00024 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(a3) & !(b))" ; + value : 9.2e-05 ; + } + leakage_power () { + when : "(!(b) & a3 & !(a2) & !(a1))" ; + value : 9.1e-05 ; + } + leakage_power () { + when : "b" ; + value : 10 ; + } + leakage_power () { + when : "(!(b) & !(a3) & !(a2) & !(a1))" ; + value : 9e-05 ; + } + pin (b) { + direction : input ; + capacitance : 8.12 ; + } + pin (a3) { + direction : input ; + capacitance : 9.79 ; + } + pin (a2) { + direction : input ; + capacitance : 10.67 ; + } + pin (a1) { + direction : input ; + capacitance : 11.51 ; + } + pin (z) { + function : "(((!(b) & !(a3)) | (!(b) & !(a2))) | (!(b) & !(a1)))" ; + direction : output ; + capacitance : 6.68 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("88.6, 88.6, 88.6, 102.6, 130.5", \ + "108.7, 108.7, 108.7, 122.8, 151.0", \ + "144.8, 144.8, 144.8, 159.1, 187.5", \ + "214.4, 214.4, 214.4, 228.9, 257.7", \ + "353.2, 353.2, 353.2, 367.8, 397.0"); + } + rise_transition (inslew_load_5x5__24) { + values ("161.0, 161.0, 161.0, 185.6, 235.0", \ + "220.5, 220.5, 220.5, 244.8, 293.8", \ + "332.1, 332.1, 332.1, 356.2, 404.7", \ + "552.7, 552.7, 552.7, 576.6, 624.4", \ + "993.3, 993.3, 993.3, 1016.9, 1064.3"); + } + cell_fall (inslew_load_5x5__24) { + values ("27.4, 27.4, 27.4, 33.9, 47.0", \ + "22.6, 22.6, 22.6, 29.8, 43.9", \ + "10.3, 10.3, 10.3, 18.5, 34.2", \ + "-17.3, -17.3, -17.3, -8.1, 9.3", \ + "-75.4, -75.4, -75.4, -65.5, -46.2"); + } + fall_transition (inslew_load_5x5__24) { + values ("49.9, 49.9, 49.9, 59.3, 78.1", \ + "62.9, 62.9, 62.9, 72.3, 91.1", \ + "88.5, 88.5, 88.5, 98.0, 116.9", \ + "139.0, 139.0, 139.0, 148.7, 167.9", \ + "239.4, 239.4, 239.4, 249.3, 268.8"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("74.6, 74.6, 74.6, 88.6, 116.7", \ + "87.2, 87.2, 87.2, 101.5, 129.9", \ + "109.1, 109.1, 109.1, 123.7, 152.9", \ + "151.4, 151.4, 151.4, 166.2, 195.7", \ + "234.9, 234.9, 234.9, 250.0, 280.0"); + } + rise_transition (inslew_load_5x5__24) { + values ("136.8, 136.8, 136.8, 161.3, 210.5", \ + "184.4, 184.4, 184.4, 208.6, 257.3", \ + "273.9, 273.9, 273.9, 297.8, 345.9", \ + "451.6, 451.6, 451.6, 475.2, 522.5", \ + "806.7, 806.7, 806.7, 830.1, 876.9"); + } + cell_fall (inslew_load_5x5__24) { + values ("25.1, 25.1, 25.1, 32.4, 46.2", \ + "24.0, 24.0, 24.0, 32.3, 47.7", \ + "18.7, 18.7, 18.7, 28.0, 45.6", \ + "5.2, 5.2, 5.2, 15.5, 35.2", \ + "-23.7, -23.7, -23.7, -12.6, 8.6"); + } + fall_transition (inslew_load_5x5__24) { + values ("41.7, 41.7, 41.7, 51.2, 70.1", \ + "57.2, 57.2, 57.2, 66.9, 85.8", \ + "86.9, 86.9, 86.9, 96.7, 116.2", \ + "145.2, 145.2, 145.2, 155.3, 175.2", \ + "261.1, 261.1, 261.1, 271.3, 291.6"); + } + } + timing (maxd_z_a3_negative_unate) { + related_pin : "a3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("59.5, 59.5, 59.5, 73.8, 102.0", \ + "66.4, 66.4, 66.4, 81.2, 109.9", \ + "77.7, 77.7, 77.7, 92.7, 122.1", \ + "98.8, 98.8, 98.8, 114.2, 144.5", \ + "139.9, 139.9, 139.9, 155.7, 186.7"); + } + rise_transition (inslew_load_5x5__24) { + values ("111.5, 111.5, 111.5, 135.8, 184.9", \ + "150.4, 150.4, 150.4, 174.4, 222.9", \ + "224.2, 224.2, 224.2, 247.8, 295.4", \ + "368.5, 368.5, 368.5, 394.1, 441.0", \ + "657.9, 657.9, 657.9, 681.6, 728.7"); + } + cell_fall (inslew_load_5x5__24) { + values ("20.3, 20.3, 20.3, 28.6, 43.4", \ + "22.1, 22.1, 22.1, 31.6, 48.8", \ + "22.9, 22.9, 22.9, 33.6, 53.2", \ + "22.6, 22.6, 22.6, 34.1, 55.9", \ + "20.7, 20.7, 20.7, 32.8, 56.1"); + } + fall_transition (inslew_load_5x5__24) { + values ("32.8, 32.8, 32.8, 42.5, 61.4", \ + "50.2, 50.2, 50.2, 60.3, 79.8", \ + "83.5, 83.5, 83.5, 93.8, 113.9", \ + "148.9, 148.9, 148.9, 159.4, 180.0", \ + "278.9, 278.9, 278.9, 289.5, 310.6"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__24) { + values ("25.6, 25.6, 25.6, 41.6, 71.5", \ + "33.2, 33.2, 33.2, 50.3, 81.4", \ + "46.0, 46.0, 46.0, 64.3, 98.6", \ + "69.5, 69.5, 69.5, 88.8, 125.6", \ + "115.3, 115.3, 115.3, 135.2, 173.8"); + } + rise_transition (inslew_load_5x5__24) { + values ("53.3, 53.3, 53.3, 78.0, 127.3", \ + "87.0, 87.0, 87.0, 111.4, 159.2", \ + "151.4, 151.4, 151.4, 176.2, 225.3", \ + "278.4, 278.4, 278.4, 303.6, 353.4", \ + "531.2, 531.2, 531.2, 556.6, 607.1"); + } + cell_fall (inslew_load_5x5__24) { + values ("16.0, 16.0, 16.0, 27.8, 47.4", \ + "15.0, 15.0, 15.0, 28.8, 51.9", \ + "10.5, 10.5, 10.5, 26.1, 53.2", \ + "-0.1, -0.1, -0.1, 16.6, 47.4", \ + "-22.6, -22.6, -22.6, -5.0, 28.4"); + } + fall_transition (inslew_load_5x5__24) { + values ("23.0, 23.0, 23.0, 33.1, 52.0", \ + "38.6, 38.6, 38.6, 49.3, 69.1", \ + "67.9, 67.9, 67.9, 79.3, 100.5", \ + "125.4, 125.4, 125.4, 137.3, 160.0", \ + "239.7, 239.7, 239.7, 252.0, 275.8"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__24) { + values ("559.6, 559.6, 559.6, 643.1, 810.0", \ + "734.0, 734.0, 734.0, 817.5, 984.4", \ + "1082.8, 1082.8, 1082.8, 1166.3, 1333.2", \ + "1780.4, 1780.4, 1780.4, 1863.8, 2030.7", \ + "3175.5, 3175.5, 3175.5, 3258.9, 3425.9"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("392.5, 392.5, 392.5, 476.0, 642.9", \ + "470.2, 470.2, 470.2, 553.7, 720.6", \ + "625.6, 625.6, 625.6, 709.1, 876.0", \ + "936.4, 936.4, 936.4, 1019.8, 1186.7", \ + "1557.9, 1557.9, 1557.9, 1641.3, 1808.2"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__24) { + values ("467.8, 467.8, 467.8, 551.2, 718.1", \ + "603.9, 603.9, 603.9, 687.3, 854.3", \ + "876.1, 876.1, 876.1, 959.6, 1126.5", \ + "1420.7, 1420.7, 1420.7, 1504.1, 1671.1", \ + "2509.7, 2509.7, 2509.7, 2593.2, 2760.1"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("315.7, 315.7, 315.7, 399.1, 566.0", \ + "400.9, 400.9, 400.9, 484.4, 651.3", \ + "571.5, 571.5, 571.5, 654.9, 821.9", \ + "912.5, 912.5, 912.5, 996.0, 1162.9", \ + "1594.7, 1594.7, 1594.7, 1678.2, 1845.1"); + } + } + internal_power (energy_neg_z_a3) { + related_pin : "a3" ; + rise_power (energy_inslew_load_5x5__24) { + values ("373.8, 373.8, 373.8, 457.3, 624.2", \ + "481.9, 481.9, 481.9, 565.4, 732.3", \ + "698.0, 698.0, 698.0, 781.5, 948.4", \ + "1130.2, 1130.2, 1130.2, 1213.7, 1380.6", \ + "1994.7, 1994.7, 1994.7, 2078.1, 2245.1"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("236.7, 236.7, 236.7, 320.2, 487.1", \ + "328.3, 328.3, 328.3, 411.8, 578.7", \ + "511.5, 511.5, 511.5, 595.0, 761.9", \ + "878.0, 878.0, 878.0, 961.4, 1128.4", \ + "1610.9, 1610.9, 1610.9, 1694.3, 1861.3"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__24) { + values ("163.1, 163.1, 163.1, 246.6, 413.5", \ + "242.4, 242.4, 242.4, 325.8, 492.7", \ + "400.8, 400.8, 400.8, 484.3, 651.2", \ + "717.8, 717.8, 717.8, 801.2, 968.1", \ + "1351.6, 1351.6, 1351.6, 1435.1, 1602.0"); + } + fall_power (energy_inslew_load_5x5__24) { + values ("138.5, 138.5, 138.5, 221.9, 388.9", \ + "193.9, 193.9, 193.9, 277.3, 444.3", \ + "304.7, 304.7, 304.7, 388.2, 555.1", \ + "526.4, 526.4, 526.4, 609.9, 776.8", \ + "969.8, 969.8, 969.8, 1053.3, 1220.2"); + } + } + } + } + + cell (aon21bv0x05) { + area : 0.0 ; + cell_leakage_power : 1.2 ; + leakage_power () { + when : "(a1 & a2)" ; + value : 4.9 ; + } + leakage_power () { + when : "(!(b) & !(a2) & a1)" ; + value : 0.00013 ; + } + leakage_power () { + when : "(!(b) & a2 & !(a1))" ; + value : 0.00012 ; + } + leakage_power () { + when : "(!((a1 & a2)) & b)" ; + value : 1.1 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 6.6e-05 ; + } + pin (b) { + direction : input ; + capacitance : 2.58 ; + } + pin (a2) { + direction : input ; + capacitance : 2.96 ; + } + pin (a1) { + direction : input ; + capacitance : 2.58 ; + } + pin (z) { + function : "(!(b) | (a2 & a1))" ; + direction : output ; + capacitance : 2.59 ; + timing (maxd_z_a1_positive_unate) { + related_pin : "a1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__25) { + values ("70.4, 70.4, 70.4, 88.7, 123.1", \ + "71.2, 71.2, 71.2, 90.0, 125.1", \ + "67.1, 67.1, 67.1, 86.6, 123.0", \ + "52.5, 52.5, 52.5, 73.1, 111.4", \ + "16.7, 16.7, 16.7, 38.3, 79.1"); + } + rise_transition (inslew_load_5x5__25) { + values ("83.5, 83.5, 83.5, 118.6, 188.9", \ + "96.5, 96.5, 96.5, 131.7, 202.1", \ + "120.0, 120.0, 120.0, 155.4, 225.5", \ + "163.6, 163.6, 163.6, 199.3, 269.9", \ + "247.3, 247.3, 247.3, 283.4, 354.7"); + } + cell_fall (inslew_load_5x5__25) { + values ("64.4, 64.4, 64.4, 78.4, 103.3", \ + "74.1, 74.1, 74.1, 89.3, 116.2", \ + "88.1, 88.1, 88.1, 104.8, 134.7", \ + "111.3, 111.3, 111.3, 130.0, 163.3", \ + "153.8, 153.8, 153.8, 173.9, 211.5"); + } + fall_transition (inslew_load_5x5__25) { + values ("47.6, 47.6, 47.6, 62.3, 90.9", \ + "57.9, 57.9, 57.9, 72.9, 101.9", \ + "77.1, 77.1, 77.1, 92.6, 122.2", \ + "114.3, 114.3, 114.3, 130.2, 161.1", \ + "187.6, 187.6, 187.6, 204.0, 236.0"); + } + } + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__25) { + values ("67.2, 67.2, 67.2, 85.3, 119.4", \ + "73.1, 73.1, 73.1, 91.8, 126.7", \ + "78.3, 78.3, 78.3, 97.9, 134.3", \ + "82.2, 82.2, 82.2, 102.9, 141.6", \ + "84.5, 84.5, 84.5, 106.4, 147.7"); + } + rise_transition (inslew_load_5x5__25) { + values ("77.3, 77.3, 77.3, 112.8, 182.7", \ + "93.3, 93.3, 93.3, 128.5, 198.9", \ + "121.2, 121.2, 121.2, 156.7, 226.7", \ + "172.8, 172.8, 172.8, 208.6, 279.2", \ + "272.4, 272.4, 272.4, 308.5, 380.0"); + } + cell_fall (inslew_load_5x5__25) { + values ("56.4, 56.4, 56.4, 69.8, 93.7", \ + "61.7, 61.7, 61.7, 76.1, 101.9", \ + "67.2, 67.2, 67.2, 83.2, 111.6", \ + "73.5, 73.5, 73.5, 91.3, 123.3", \ + "81.6, 81.6, 81.6, 101.4, 137.4"); + } + fall_transition (inslew_load_5x5__25) { + values ("43.1, 43.1, 43.1, 57.6, 86.1", \ + "51.4, 51.4, 51.4, 66.2, 94.9", \ + "67.0, 67.0, 67.0, 82.1, 111.4", \ + "96.8, 96.8, 96.8, 112.6, 142.8", \ + "155.5, 155.5, 155.5, 171.8, 203.3"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__25) { + values ("34.7, 34.7, 34.7, 54.3, 89.7", \ + "46.6, 46.6, 46.6, 68.2, 106.9", \ + "66.8, 66.8, 66.8, 90.2, 132.9", \ + "104.8, 104.8, 104.8, 129.5, 176.0", \ + "179.4, 179.4, 179.4, 205.0, 254.3"); + } + rise_transition (inslew_load_5x5__25) { + values ("68.4, 68.4, 68.4, 103.9, 174.4", \ + "107.4, 107.4, 107.4, 143.5, 214.2", \ + "181.1, 181.1, 181.1, 217.7, 289.7", \ + "326.0, 326.0, 326.0, 363.0, 436.0", \ + "614.6, 614.6, 614.6, 651.7, 725.6"); + } + cell_fall (inslew_load_5x5__25) { + values ("16.1, 16.1, 16.1, 30.1, 54.0", \ + "12.3, 12.3, 12.3, 29.0, 56.9", \ + "1.6, 1.6, 1.6, 21.1, 54.3", \ + "-22.2, -22.2, -22.2, -0.4, 38.4", \ + "-71.8, -71.8, -71.8, -48.3, -4.7"); + } + fall_transition (inslew_load_5x5__25) { + values ("28.8, 28.8, 28.8, 43.6, 72.5", \ + "41.8, 41.8, 41.8, 57.4, 87.0", \ + "66.7, 66.7, 66.7, 83.2, 114.3", \ + "115.3, 115.3, 115.3, 132.6, 165.7", \ + "211.9, 211.9, 211.9, 229.8, 264.4"); + } + } + internal_power (energy_pos_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__25) { + values ("157.7, 157.7, 157.7, 190.0, 254.8", \ + "180.3, 180.3, 180.3, 212.6, 277.4", \ + "224.7, 224.7, 224.7, 257.1, 321.9", \ + "312.9, 312.9, 312.9, 345.2, 410.0", \ + "488.2, 488.2, 488.2, 520.5, 585.3"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("173.4, 173.4, 173.4, 205.7, 270.5", \ + "219.0, 219.0, 219.0, 251.4, 316.2", \ + "309.2, 309.2, 309.2, 341.5, 406.3", \ + "488.7, 488.7, 488.7, 521.1, 585.8", \ + "847.4, 847.4, 847.4, 879.8, 944.6"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__25) { + values ("137.8, 137.8, 137.8, 170.2, 234.9", \ + "163.7, 163.7, 163.7, 196.1, 260.9", \ + "214.6, 214.6, 214.6, 246.9, 311.7", \ + "315.2, 315.2, 315.2, 347.6, 412.4", \ + "515.8, 515.8, 515.8, 548.1, 612.9"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("147.1, 147.1, 147.1, 179.5, 244.2", \ + "182.4, 182.4, 182.4, 214.8, 279.5", \ + "252.1, 252.1, 252.1, 284.4, 349.2", \ + "390.8, 390.8, 390.8, 423.2, 488.0", \ + "668.0, 668.0, 668.0, 700.4, 765.2"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__25) { + values ("57.4, 57.4, 57.4, 89.8, 154.6", \ + "83.2, 83.2, 83.2, 115.5, 180.3", \ + "134.6, 134.6, 134.6, 167.0, 231.8", \ + "237.5, 237.5, 237.5, 269.9, 334.7", \ + "443.3, 443.3, 443.3, 475.7, 540.4"); + } + fall_power (energy_inslew_load_5x5__25) { + values ("46.6, 46.6, 46.6, 79.0, 143.8", \ + "60.2, 60.2, 60.2, 92.5, 157.3", \ + "87.3, 87.3, 87.3, 119.6, 184.4", \ + "141.4, 141.4, 141.4, 173.8, 238.6", \ + "249.8, 249.8, 249.8, 282.2, 347.0"); + } + } + } + } + + cell (aon21bv0x1) { + area : 0.0 ; + cell_leakage_power : 0.82 ; + leakage_power () { + when : "(a1 & a2)" ; + value : 1.4 ; + } + leakage_power () { + when : "(!(b) & !(a2) & a1)" ; + value : 0.00015 ; + } + leakage_power () { + when : "(!(b) & a2 & !(a1))" ; + value : 0.00016 ; + } + leakage_power () { + when : "(!((a1 & a2)) & b)" ; + value : 2.6 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 7.2e-05 ; + } + pin (b) { + direction : input ; + capacitance : 3.75 ; + } + pin (a2) { + direction : input ; + capacitance : 3.89 ; + } + pin (a1) { + direction : input ; + capacitance : 3.60 ; + } + pin (z) { + function : "(!(b) | (a2 & a1))" ; + direction : output ; + capacitance : 3.17 ; + timing (maxd_z_a1_positive_unate) { + related_pin : "a1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__26) { + values ("50.6, 50.6, 50.6, 63.5, 87.6", \ + "52.7, 52.7, 52.7, 66.0, 90.8", \ + "50.3, 50.3, 50.3, 64.2, 90.1", \ + "39.2, 39.2, 39.2, 53.9, 81.4", \ + "11.4, 11.4, 11.4, 26.9, 56.3"); + } + rise_transition (inslew_load_5x5__26) { + values ("54.9, 54.9, 54.9, 78.8, 126.5", \ + "68.5, 68.5, 68.5, 92.4, 140.2", \ + "91.0, 91.0, 91.0, 115.0, 162.6", \ + "131.7, 131.7, 131.7, 155.9, 203.9", \ + "209.2, 209.2, 209.2, 233.7, 282.2"); + } + cell_fall (inslew_load_5x5__26) { + values ("53.6, 53.6, 53.6, 63.2, 80.3", \ + "62.1, 62.1, 62.1, 72.6, 91.4", \ + "74.2, 74.2, 74.2, 86.0, 106.9", \ + "94.2, 94.2, 94.2, 107.2, 130.8", \ + "130.6, 130.6, 130.6, 144.8, 171.5"); + } + fall_transition (inslew_load_5x5__26) { + values ("35.0, 35.0, 35.0, 44.8, 63.9", \ + "43.5, 43.5, 43.5, 53.6, 73.0", \ + "59.2, 59.2, 59.2, 69.5, 89.6", \ + "89.4, 89.4, 89.4, 100.2, 121.1", \ + "148.9, 148.9, 148.9, 160.1, 181.9"); + } + } + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__26) { + values ("55.3, 55.3, 55.3, 68.3, 92.8", \ + "54.0, 54.0, 54.0, 67.5, 92.5", \ + "45.8, 45.8, 45.8, 59.8, 85.8", \ + "22.3, 22.3, 22.3, 37.0, 64.3", \ + "-31.3, -31.3, -31.3, -15.9, 13.3"); + } + rise_transition (inslew_load_5x5__26) { + values ("61.3, 61.3, 61.3, 85.1, 132.9", \ + "72.5, 72.5, 72.5, 96.5, 144.4", \ + "92.2, 92.2, 92.2, 116.3, 163.9", \ + "127.8, 127.8, 127.8, 152.1, 200.0", \ + "195.2, 195.2, 195.2, 219.6, 268.1"); + } + cell_fall (inslew_load_5x5__26) { + values ("62.0, 62.0, 62.0, 72.1, 90.0", \ + "74.2, 74.2, 74.2, 85.2, 104.8", \ + "93.4, 93.4, 93.4, 105.4, 127.4", \ + "127.0, 127.0, 127.0, 140.5, 164.7", \ + "191.0, 191.0, 191.0, 205.4, 232.8"); + } + fall_transition (inslew_load_5x5__26) { + values ("38.9, 38.9, 38.9, 48.9, 68.2", \ + "48.8, 48.8, 48.8, 59.0, 78.7", \ + "67.0, 67.0, 67.0, 77.6, 97.9", \ + "102.3, 102.3, 102.3, 113.3, 134.6", \ + "171.9, 171.9, 171.9, 183.2, 205.3"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__26) { + values ("28.1, 28.1, 28.1, 42.8, 68.8", \ + "39.2, 39.2, 39.2, 55.2, 83.9", \ + "58.3, 58.3, 58.3, 75.3, 106.9", \ + "94.5, 94.5, 94.5, 112.3, 146.3", \ + "166.0, 166.0, 166.0, 184.2, 219.8"); + } + rise_transition (inslew_load_5x5__26) { + values ("56.2, 56.2, 56.2, 80.5, 128.2", \ + "94.2, 94.2, 94.2, 118.9, 167.3", \ + "166.2, 166.2, 166.2, 191.2, 240.5", \ + "308.1, 308.1, 308.1, 333.3, 383.3", \ + "590.6, 590.6, 590.6, 616.0, 666.4"); + } + cell_fall (inslew_load_5x5__26) { + values ("11.3, 11.3, 11.3, 22.0, 39.7", \ + "6.9, 6.9, 6.9, 19.6, 40.8", \ + "-3.9, -3.9, -3.9, 10.5, 35.7", \ + "-27.3, -27.3, -27.3, -11.3, 17.6", \ + "-75.0, -75.0, -75.0, -58.0, -26.2"); + } + fall_transition (inslew_load_5x5__26) { + values ("23.0, 23.0, 23.0, 33.2, 52.7", \ + "35.3, 35.3, 35.3, 46.2, 66.5", \ + "59.1, 59.1, 59.1, 70.6, 92.2", \ + "105.9, 105.9, 105.9, 117.9, 140.8", \ + "199.0, 199.0, 199.0, 211.3, 235.3"); + } + } + internal_power (energy_pos_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__26) { + values ("196.3, 196.3, 196.3, 235.9, 315.3", \ + "232.6, 232.6, 232.6, 272.3, 351.7", \ + "303.4, 303.4, 303.4, 343.1, 422.5", \ + "443.7, 443.7, 443.7, 483.4, 562.8", \ + "723.1, 723.1, 723.1, 762.8, 842.2"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("227.9, 227.9, 227.9, 267.5, 346.9", \ + "293.5, 293.5, 293.5, 333.2, 412.6", \ + "422.9, 422.9, 422.9, 462.6, 542.0", \ + "680.8, 680.8, 680.8, 720.5, 799.9", \ + "1196.0, 1196.0, 1196.0, 1235.7, 1315.1"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__26) { + values ("234.7, 234.7, 234.7, 274.4, 353.7", \ + "267.7, 267.7, 267.7, 307.4, 386.8", \ + "332.6, 332.6, 332.6, 372.3, 451.6", \ + "460.6, 460.6, 460.6, 500.3, 579.6", \ + "714.8, 714.8, 714.8, 754.5, 833.9"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("270.8, 270.8, 270.8, 310.4, 389.8", \ + "349.7, 349.7, 349.7, 389.4, 468.8", \ + "505.6, 505.6, 505.6, 545.2, 624.6", \ + "816.0, 816.0, 816.0, 855.7, 935.0", \ + "1436.1, 1436.1, 1436.1, 1475.8, 1555.2"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__26) { + values ("82.9, 82.9, 82.9, 122.6, 201.9", \ + "127.2, 127.2, 127.2, 166.8, 246.2", \ + "215.7, 215.7, 215.7, 255.4, 334.8", \ + "392.8, 392.8, 392.8, 432.5, 511.8", \ + "747.0, 747.0, 747.0, 786.6, 866.0"); + } + fall_power (energy_inslew_load_5x5__26) { + values ("63.8, 63.8, 63.8, 103.5, 182.9", \ + "86.9, 86.9, 86.9, 126.6, 206.0", \ + "133.1, 133.1, 133.1, 172.8, 252.2", \ + "225.4, 225.4, 225.4, 265.1, 344.5", \ + "410.1, 410.1, 410.1, 449.8, 529.2"); + } + } + } + } + + cell (aon21bv0x2) { + area : 0.0 ; + cell_leakage_power : 0.98 ; + leakage_power () { + when : "(a1 & a2)" ; + value : 2 ; + } + leakage_power () { + when : "(!(b) & !(a2) & a1)" ; + value : 0.00018 ; + } + leakage_power () { + when : "(!(b) & a2 & !(a1))" ; + value : 0.0002 ; + } + leakage_power () { + when : "(!((a1 & a2)) & b)" ; + value : 2.9 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 0.00011 ; + } + pin (b) { + direction : input ; + capacitance : 5.45 ; + } + pin (a2) { + direction : input ; + capacitance : 4.83 ; + } + pin (a1) { + direction : input ; + capacitance : 4.41 ; + } + pin (z) { + function : "(!(b) | (a2 & a1))" ; + direction : output ; + capacitance : 4.26 ; + timing (maxd_z_a1_positive_unate) { + related_pin : "a1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__27) { + values ("51.7, 51.7, 51.7, 62.6, 82.9", \ + "55.9, 55.9, 55.9, 67.2, 88.1", \ + "57.9, 57.9, 57.9, 69.6, 91.5", \ + "55.6, 55.6, 55.6, 68.0, 91.2", \ + "45.7, 45.7, 45.7, 58.6, 83.2"); + } + rise_transition (inslew_load_5x5__27) { + values ("51.0, 51.0, 51.0, 69.4, 106.3", \ + "65.7, 65.7, 65.7, 84.1, 120.7", \ + "90.6, 90.6, 90.6, 109.2, 145.8", \ + "136.0, 136.0, 136.0, 154.7, 191.7", \ + "223.0, 223.0, 223.0, 241.8, 279.1"); + } + cell_fall (inslew_load_5x5__27) { + values ("49.4, 49.4, 49.4, 57.1, 70.8", \ + "56.0, 56.0, 56.0, 64.4, 79.5", \ + "64.4, 64.4, 64.4, 73.8, 90.7", \ + "77.5, 77.5, 77.5, 88.0, 106.7", \ + "100.6, 100.6, 100.6, 111.7, 133.2"); + } + fall_transition (inslew_load_5x5__27) { + values ("31.0, 31.0, 31.0, 38.7, 53.5", \ + "38.5, 38.5, 38.5, 46.3, 61.5", \ + "52.4, 52.4, 52.4, 60.5, 76.1", \ + "79.0, 79.0, 79.0, 87.5, 104.0", \ + "131.6, 131.6, 131.6, 140.4, 157.6"); + } + } + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__27) { + values ("55.9, 55.9, 55.9, 67.0, 87.5", \ + "55.8, 55.8, 55.8, 67.2, 88.3", \ + "49.7, 49.7, 49.7, 61.4, 83.3", \ + "31.1, 31.1, 31.1, 43.4, 66.4", \ + "-12.5, -12.5, -12.5, 0.2, 24.6"); + } + rise_transition (inslew_load_5x5__27) { + values ("57.2, 57.2, 57.2, 75.6, 112.5", \ + "69.2, 69.2, 69.2, 87.6, 124.2", \ + "90.2, 90.2, 90.2, 108.8, 145.4", \ + "128.8, 128.8, 128.8, 147.4, 184.4", \ + "202.1, 202.1, 202.1, 220.9, 258.1"); + } + cell_fall (inslew_load_5x5__27) { + values ("57.6, 57.6, 57.6, 65.6, 80.1", \ + "68.5, 68.5, 68.5, 77.3, 93.1", \ + "85.6, 85.6, 85.6, 95.1, 113.0", \ + "115.1, 115.1, 115.1, 125.9, 145.5", \ + "171.4, 171.4, 171.4, 182.7, 204.5"); + } + fall_transition (inslew_load_5x5__27) { + values ("34.8, 34.8, 34.8, 42.5, 57.5", \ + "43.8, 43.8, 43.8, 51.7, 67.1", \ + "60.5, 60.5, 60.5, 68.9, 84.7", \ + "92.9, 92.9, 92.9, 101.5, 118.1", \ + "156.9, 156.9, 156.9, 165.6, 182.9"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__27) { + values ("26.4, 26.4, 26.4, 38.8, 60.8", \ + "38.7, 38.7, 38.7, 52.0, 76.2", \ + "60.3, 60.3, 60.3, 74.3, 100.6", \ + "101.6, 101.6, 101.6, 116.1, 144.0", \ + "183.1, 183.1, 183.1, 197.9, 226.9"); + } + rise_transition (inslew_load_5x5__27) { + values ("50.6, 50.6, 50.6, 69.5, 106.3", \ + "89.4, 89.4, 89.4, 108.5, 145.8", \ + "162.7, 162.7, 162.7, 181.9, 219.9", \ + "306.8, 306.8, 306.8, 326.2, 364.7", \ + "593.8, 593.8, 593.8, 613.3, 652.2"); + } + cell_fall (inslew_load_5x5__27) { + values ("8.0, 8.0, 8.0, 17.0, 31.8", \ + "2.3, 2.3, 2.3, 12.9, 30.7", \ + "-10.8, -10.8, -10.8, 1.2, 22.4", \ + "-38.3, -38.3, -38.3, -25.1, -1.0", \ + "-94.0, -94.0, -94.0, -80.1, -53.9"); + } + fall_transition (inslew_load_5x5__27) { + values ("20.1, 20.1, 20.1, 28.2, 43.4", \ + "31.8, 31.8, 31.8, 40.4, 56.5", \ + "54.3, 54.3, 54.3, 63.4, 80.6", \ + "98.7, 98.7, 98.7, 108.2, 126.5", \ + "187.1, 187.1, 187.1, 196.9, 215.9"); + } + } + internal_power (energy_pos_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__27) { + values ("290.7, 290.7, 290.7, 344.0, 450.5", \ + "350.7, 350.7, 350.7, 404.0, 510.5", \ + "468.0, 468.0, 468.0, 521.3, 627.8", \ + "700.1, 700.1, 700.1, 753.3, 859.9", \ + "1162.2, 1162.2, 1162.2, 1215.4, 1321.9"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("315.9, 315.9, 315.9, 369.1, 475.6", \ + "400.4, 400.4, 400.4, 453.6, 560.1", \ + "567.1, 567.1, 567.1, 620.4, 726.9", \ + "899.2, 899.2, 899.2, 952.5, 1059.0", \ + "1562.5, 1562.5, 1562.5, 1615.7, 1722.2"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__27) { + values ("340.7, 340.7, 340.7, 393.9, 500.4", \ + "393.1, 393.1, 393.1, 446.3, 552.8", \ + "495.6, 495.6, 495.6, 548.9, 655.4", \ + "698.1, 698.1, 698.1, 751.4, 857.9", \ + "1100.5, 1100.5, 1100.5, 1153.8, 1260.3"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("376.1, 376.1, 376.1, 429.3, 535.8", \ + "482.8, 482.8, 482.8, 536.1, 642.6", \ + "693.6, 693.6, 693.6, 746.8, 853.3", \ + "1113.2, 1113.2, 1113.2, 1166.4, 1272.9", \ + "1951.3, 1951.3, 1951.3, 2004.6, 2111.1"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__27) { + values ("128.5, 128.5, 128.5, 181.8, 288.3", \ + "205.6, 205.6, 205.6, 258.8, 365.3", \ + "359.6, 359.6, 359.6, 412.9, 519.4", \ + "667.8, 667.8, 667.8, 721.0, 827.5", \ + "1284.0, 1284.0, 1284.0, 1337.3, 1443.8"); + } + fall_power (energy_inslew_load_5x5__27) { + values ("91.5, 91.5, 91.5, 144.8, 251.3", \ + "128.0, 128.0, 128.0, 181.3, 287.8", \ + "201.0, 201.0, 201.0, 254.3, 360.8", \ + "347.1, 347.1, 347.1, 400.3, 506.8", \ + "639.1, 639.1, 639.1, 692.4, 798.9"); + } + } + } + } + + cell (aon21v0x05) { + area : 0.0 ; + cell_leakage_power : 2 ; + leakage_power () { + when : "(!(b) & a2 & a1)" ; + value : 0.39 ; + } + leakage_power () { + when : "b" ; + value : 0.79 ; + } + leakage_power () { + when : "(!((a1 & a2)) & !(b))" ; + value : 4.9 ; + } + pin (b) { + direction : input ; + capacitance : 3.43 ; + } + pin (a2) { + direction : input ; + capacitance : 3.12 ; + } + pin (a1) { + direction : input ; + capacitance : 3.55 ; + } + pin (z) { + function : "((a2 & a1) | b)" ; + direction : output ; + capacitance : 1.98 ; + timing (maxd_z_a1_positive_unate) { + related_pin : "a1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__28) { + values ("63.3, 63.3, 63.3, 75.2, 96.2", \ + "68.8, 68.8, 68.8, 81.2, 103.1", \ + "75.6, 75.6, 75.6, 88.6, 112.1", \ + "85.0, 85.0, 85.0, 98.7, 123.9", \ + "100.0, 100.0, 100.0, 114.3, 141.4"); + } + rise_transition (inslew_load_5x5__28) { + values ("54.7, 54.7, 54.7, 73.3, 109.5", \ + "67.0, 67.0, 67.0, 85.7, 122.3", \ + "90.5, 90.5, 90.5, 109.4, 146.4", \ + "136.1, 136.1, 136.1, 155.2, 192.7", \ + "226.3, 226.3, 226.3, 245.5, 283.5"); + } + cell_fall (inslew_load_5x5__28) { + values ("88.2, 88.2, 88.2, 100.2, 121.4", \ + "94.9, 94.9, 94.9, 107.2, 129.4", \ + "105.8, 105.8, 105.8, 118.8, 142.1", \ + "125.9, 125.9, 125.9, 139.6, 164.6", \ + "164.1, 164.1, 164.1, 178.2, 205.0"); + } + fall_transition (inslew_load_5x5__28) { + values ("56.2, 56.2, 56.2, 65.1, 82.0", \ + "68.6, 68.6, 68.6, 77.7, 94.9", \ + "93.0, 93.0, 93.0, 102.2, 120.0", \ + "141.9, 141.9, 141.9, 151.3, 169.5", \ + "237.9, 237.9, 237.9, 247.4, 266.1"); + } + } + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__28) { + values ("62.2, 62.2, 62.2, 73.9, 94.4", \ + "73.9, 73.9, 73.9, 86.2, 108.0", \ + "91.3, 91.3, 91.3, 104.3, 127.8", \ + "120.9, 120.9, 120.9, 134.7, 160.0", \ + "176.7, 176.7, 176.7, 191.0, 218.3"); + } + rise_transition (inslew_load_5x5__28) { + values ("50.2, 50.2, 50.2, 68.8, 104.9", \ + "64.9, 64.9, 64.9, 83.6, 120.1", \ + "91.9, 91.9, 91.9, 110.8, 147.8", \ + "143.7, 143.7, 143.7, 162.8, 200.4", \ + "246.0, 246.0, 246.0, 265.2, 303.2"); + } + cell_fall (inslew_load_5x5__28) { + values ("77.4, 77.4, 77.4, 89.3, 109.8", \ + "78.2, 78.2, 78.2, 90.3, 111.8", \ + "77.8, 77.8, 77.8, 90.3, 113.1", \ + "74.0, 74.0, 74.0, 87.3, 111.4", \ + "63.4, 63.4, 63.4, 77.3, 103.3"); + } + fall_transition (inslew_load_5x5__28) { + values ("49.9, 49.9, 49.9, 58.7, 75.4", \ + "59.2, 59.2, 59.2, 68.2, 85.1", \ + "77.7, 77.7, 77.7, 86.9, 104.3", \ + "113.8, 113.8, 113.8, 123.1, 141.1", \ + "186.4, 186.4, 186.4, 195.9, 214.3"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__28) { + values ("43.0, 43.0, 43.0, 53.8, 72.7", \ + "44.1, 44.1, 44.1, 55.5, 75.6", \ + "40.1, 40.1, 40.1, 52.4, 74.1", \ + "26.8, 26.8, 26.8, 39.9, 63.6", \ + "-4.2, -4.2, -4.2, 9.7, 35.4"); + } + rise_transition (inslew_load_5x5__28) { + values ("35.8, 35.8, 35.8, 54.1, 89.8", \ + "45.8, 45.8, 45.8, 64.2, 100.2", \ + "63.0, 63.0, 63.0, 81.7, 118.1", \ + "95.2, 95.2, 95.2, 114.1, 151.2", \ + "157.5, 157.5, 157.5, 176.6, 214.3"); + } + cell_fall (inslew_load_5x5__28) { + values ("60.6, 60.6, 60.6, 71.7, 90.6", \ + "72.4, 72.4, 72.4, 84.3, 104.8", \ + "91.9, 91.9, 91.9, 104.4, 126.9", \ + "126.3, 126.3, 126.3, 139.7, 164.0", \ + "191.7, 191.7, 191.7, 205.7, 232.2"); + } + fall_transition (inslew_load_5x5__28) { + values ("36.7, 36.7, 36.7, 45.4, 61.5", \ + "49.5, 49.5, 49.5, 58.3, 75.0", \ + "73.6, 73.6, 73.6, 82.8, 100.1", \ + "120.6, 120.6, 120.6, 129.9, 148.1", \ + "213.7, 213.7, 213.7, 223.3, 241.8"); + } + } + internal_power (energy_pos_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__28) { + values ("182.9, 182.9, 182.9, 207.6, 257.1", \ + "223.3, 223.3, 223.3, 248.1, 297.5", \ + "303.7, 303.7, 303.7, 328.5, 377.9", \ + "463.8, 463.8, 463.8, 488.5, 538.0", \ + "783.6, 783.6, 783.6, 808.3, 857.8"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("238.1, 238.1, 238.1, 262.8, 312.3", \ + "289.1, 289.1, 289.1, 313.8, 363.3", \ + "390.6, 390.6, 390.6, 415.4, 464.8", \ + "594.0, 594.0, 594.0, 618.7, 668.2", \ + "998.6, 998.6, 998.6, 1023.3, 1072.8"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__28) { + values ("162.5, 162.5, 162.5, 187.2, 236.7", \ + "206.5, 206.5, 206.5, 231.3, 280.8", \ + "293.1, 293.1, 293.1, 317.9, 367.4", \ + "465.2, 465.2, 465.2, 489.9, 539.4", \ + "808.6, 808.6, 808.6, 833.3, 882.8"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("207.9, 207.9, 207.9, 232.6, 282.1", \ + "244.6, 244.6, 244.6, 269.4, 318.9", \ + "318.1, 318.1, 318.1, 342.8, 392.3", \ + "464.0, 464.0, 464.0, 488.8, 538.2", \ + "756.6, 756.6, 756.6, 781.3, 830.8"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__28) { + values ("116.2, 116.2, 116.2, 140.9, 190.4", \ + "141.3, 141.3, 141.3, 166.1, 215.5", \ + "190.3, 190.3, 190.3, 215.0, 264.5", \ + "287.1, 287.1, 287.1, 311.9, 361.3", \ + "480.0, 480.0, 480.0, 504.7, 554.2"); + } + fall_power (energy_inslew_load_5x5__28) { + values ("149.4, 149.4, 149.4, 174.2, 223.6", \ + "194.7, 194.7, 194.7, 219.5, 268.9", \ + "284.1, 284.1, 284.1, 308.9, 358.3", \ + "461.5, 461.5, 461.5, 486.2, 535.7", \ + "815.5, 815.5, 815.5, 840.2, 889.7"); + } + } + } + } + + cell (bf1v0x05) { + area : 0.0 ; + cell_leakage_power : 4.8 ; + leakage_power () { + when : "a" ; + value : 4.7 ; + } + leakage_power () { + when : "!(a)" ; + value : 4.9 ; + } + pin (a) { + direction : input ; + capacitance : 2.59 ; + } + pin (z) { + function : "a" ; + direction : output ; + capacitance : 2.09 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__29) { + values ("32.3, 32.3, 32.3, 43.1, 62.4", \ + "30.2, 30.2, 30.2, 41.8, 62.1", \ + "21.3, 21.3, 21.3, 33.8, 55.8", \ + "-1.1, -1.1, -1.1, 12.5, 36.7", \ + "-49.0, -49.0, -49.0, -34.5, -8.0"); + } + rise_transition (inslew_load_5x5__29) { + values ("31.8, 31.8, 31.8, 51.0, 88.9", \ + "41.1, 41.1, 41.1, 60.4, 98.3", \ + "56.9, 56.9, 56.9, 76.5, 114.8", \ + "86.2, 86.2, 86.2, 106.1, 145.0", \ + "142.8, 142.8, 142.8, 162.9, 202.5"); + } + cell_fall (inslew_load_5x5__29) { + values ("53.7, 53.7, 53.7, 65.0, 84.2", \ + "66.8, 66.8, 66.8, 79.2, 100.4", \ + "89.6, 89.6, 89.6, 102.6, 126.2", \ + "131.5, 131.5, 131.5, 145.7, 171.3", \ + "213.1, 213.1, 213.1, 227.9, 256.0"); + } + fall_transition (inslew_load_5x5__29) { + values ("34.7, 34.7, 34.7, 43.7, 60.5", \ + "49.0, 49.0, 49.0, 58.2, 75.6", \ + "75.6, 75.6, 75.6, 85.3, 103.4", \ + "128.1, 128.1, 128.1, 137.8, 156.9", \ + "232.3, 232.3, 232.3, 242.3, 261.6"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__29) { + values ("101.6, 101.6, 101.6, 127.8, 180.1", \ + "125.6, 125.6, 125.6, 151.8, 204.1", \ + "172.8, 172.8, 172.8, 199.0, 251.3", \ + "266.4, 266.4, 266.4, 292.6, 344.9", \ + "453.0, 453.0, 453.0, 479.2, 531.5"); + } + fall_power (energy_inslew_load_5x5__29) { + values ("140.4, 140.4, 140.4, 166.6, 218.9", \ + "193.1, 193.1, 193.1, 219.2, 271.6", \ + "296.8, 296.8, 296.8, 322.9, 375.3", \ + "503.2, 503.2, 503.2, 529.4, 581.7", \ + "915.5, 915.5, 915.5, 941.7, 994.0"); + } + } + } + } + + cell (bf1v0x1) { + area : 0.0 ; + cell_leakage_power : 1.6 ; + leakage_power () { + when : "a" ; + value : 2.7 ; + } + leakage_power () { + when : "!(a)" ; + value : 0.45 ; + } + pin (a) { + direction : input ; + capacitance : 2.97 ; + } + pin (z) { + function : "a" ; + direction : output ; + capacitance : 2.53 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__30) { + values ("35.5, 35.5, 35.5, 44.7, 60.6", \ + "39.2, 39.2, 39.2, 49.0, 66.1", \ + "42.6, 42.6, 42.6, 53.2, 71.8", \ + "46.1, 46.1, 46.1, 57.2, 77.8", \ + "50.6, 50.6, 50.6, 62.4, 84.5"); + } + rise_transition (inslew_load_5x5__30) { + values ("28.0, 28.0, 28.0, 42.1, 69.4", \ + "38.6, 38.6, 38.6, 52.8, 80.4", \ + "57.7, 57.7, 57.7, 72.0, 100.0", \ + "93.8, 93.8, 93.8, 108.3, 136.8", \ + "164.6, 164.6, 164.6, 179.2, 208.2"); + } + cell_fall (inslew_load_5x5__30) { + values ("45.5, 45.5, 45.5, 54.5, 69.8", \ + "51.1, 51.1, 51.1, 61.0, 77.6", \ + "58.8, 58.8, 58.8, 69.0, 87.4", \ + "70.2, 70.2, 70.2, 81.3, 101.2", \ + "90.3, 90.3, 90.3, 102.1, 124.1"); + } + fall_transition (inslew_load_5x5__30) { + values ("28.8, 28.8, 28.8, 35.5, 48.0", \ + "39.3, 39.3, 39.3, 46.1, 59.0", \ + "58.8, 58.8, 58.8, 66.0, 79.5", \ + "97.2, 97.2, 97.2, 104.5, 118.6", \ + "173.5, 173.5, 173.5, 180.7, 195.2"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__30) { + values ("144.7, 144.7, 144.7, 176.3, 239.5", \ + "190.3, 190.3, 190.3, 221.9, 285.1", \ + "280.7, 280.7, 280.7, 312.3, 375.5", \ + "460.6, 460.6, 460.6, 492.2, 555.4", \ + "819.7, 819.7, 819.7, 851.3, 914.5"); + } + fall_power (energy_inslew_load_5x5__30) { + values ("166.0, 166.0, 166.0, 197.6, 260.8", \ + "217.4, 217.4, 217.4, 249.0, 312.2", \ + "318.4, 318.4, 318.4, 350.0, 413.2", \ + "519.1, 519.1, 519.1, 550.7, 613.9", \ + "919.8, 919.8, 919.8, 951.4, 1014.6"); + } + } + } + } + + cell (bf1v0x12) { + area : 0.0 ; + cell_leakage_power : 9.8 ; + leakage_power () { + when : "a" ; + value : 3.4 ; + } + leakage_power () { + when : "!(a)" ; + value : 16 ; + } + pin (a) { + direction : input ; + capacitance : 9.86 ; + } + pin (z) { + function : "a" ; + direction : output ; + capacitance : 13.53 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__31) { + values ("41.8, 41.8, 41.8, 48.6, 60.4", \ + "45.2, 45.2, 45.2, 52.2, 64.6", \ + "45.9, 45.9, 45.9, 53.1, 66.2", \ + "41.4, 41.4, 41.4, 48.7, 62.7", \ + "27.6, 27.6, 27.6, 35.3, 49.9"); + } + rise_transition (inslew_load_5x5__31) { + values ("27.5, 27.5, 27.5, 36.7, 54.4", \ + "38.4, 38.4, 38.4, 47.5, 65.4", \ + "57.2, 57.2, 57.2, 66.4, 84.5", \ + "92.4, 92.4, 92.4, 101.6, 119.9", \ + "160.3, 160.3, 160.3, 169.7, 188.1"); + } + cell_fall (inslew_load_5x5__31) { + values ("51.3, 51.3, 51.3, 57.8, 68.7", \ + "60.5, 60.5, 60.5, 67.0, 78.7", \ + "73.7, 73.7, 73.7, 80.8, 93.0", \ + "95.8, 95.8, 95.8, 103.1, 116.9", \ + "139.0, 139.0, 139.0, 145.4, 158.8"); + } + fall_transition (inslew_load_5x5__31) { + values ("30.1, 30.1, 30.1, 34.2, 42.1", \ + "40.6, 40.6, 40.6, 44.8, 52.8", \ + "60.5, 60.5, 60.5, 64.8, 73.0", \ + "99.8, 99.8, 99.8, 104.0, 112.3", \ + "177.1, 177.1, 177.1, 181.5, 190.2"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__31) { + values ("909.9, 909.9, 909.9, 1079.0, 1417.3", \ + "1128.5, 1128.5, 1128.5, 1297.6, 1635.9", \ + "1549.5, 1549.5, 1549.5, 1718.7, 2057.0", \ + "2376.3, 2376.3, 2376.3, 2545.5, 2883.8", \ + "4016.3, 4016.3, 4016.3, 4185.4, 4523.7"); + } + fall_power (energy_inslew_load_5x5__31) { + values ("1127.2, 1127.2, 1127.2, 1296.4, 1634.7", \ + "1444.8, 1444.8, 1444.8, 1613.9, 1952.2", \ + "2064.7, 2064.7, 2064.7, 2233.8, 2572.1", \ + "3294.8, 3294.8, 3294.8, 3464.0, 3802.3", \ + "5747.6, 5747.6, 5747.6, 5916.8, 6255.1"); + } + } + } + } + + cell (bf1v0x2) { + area : 0.0 ; + cell_leakage_power : 0.88 ; + leakage_power () { + when : "a" ; + value : 0.28 ; + } + leakage_power () { + when : "!(a)" ; + value : 1.5 ; + } + pin (a) { + direction : input ; + capacitance : 3.49 ; + } + pin (z) { + function : "a" ; + direction : output ; + capacitance : 4.53 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__32) { + values ("39.3, 39.3, 39.3, 50.6, 70.7", \ + "40.8, 40.8, 40.8, 52.8, 73.8", \ + "38.6, 38.6, 38.6, 51.3, 74.0", \ + "29.1, 29.1, 29.1, 42.7, 67.4", \ + "6.2, 6.2, 6.2, 20.4, 47.1"); + } + rise_transition (inslew_load_5x5__32) { + values ("31.6, 31.6, 31.6, 49.1, 83.8", \ + "42.1, 42.1, 42.1, 59.8, 94.3", \ + "60.4, 60.4, 60.4, 78.2, 113.0", \ + "94.0, 94.0, 94.0, 112.0, 147.4", \ + "159.0, 159.0, 159.0, 177.3, 213.2"); + } + cell_fall (inslew_load_5x5__32) { + values ("49.0, 49.0, 49.0, 59.2, 76.2", \ + "57.8, 57.8, 57.8, 69.1, 87.8", \ + "71.9, 71.9, 71.9, 83.8, 104.9", \ + "95.9, 95.9, 95.9, 109.3, 132.5", \ + "142.5, 142.5, 142.5, 155.6, 182.0"); + } + fall_transition (inslew_load_5x5__32) { + values ("27.5, 27.5, 27.5, 35.1, 48.9", \ + "37.6, 37.6, 37.6, 45.3, 59.7", \ + "56.3, 56.3, 56.3, 64.4, 79.5", \ + "93.0, 93.0, 93.0, 101.3, 117.3", \ + "166.0, 166.0, 166.0, 174.6, 191.0"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__32) { + values ("203.8, 203.8, 203.8, 260.5, 373.8", \ + "250.9, 250.9, 250.9, 307.6, 420.9", \ + "343.1, 343.1, 343.1, 399.8, 513.1", \ + "525.2, 525.2, 525.2, 581.9, 695.2", \ + "887.9, 887.9, 887.9, 944.6, 1057.9"); + } + fall_power (energy_inslew_load_5x5__32) { + values ("243.3, 243.3, 243.3, 300.0, 413.3", \ + "317.4, 317.4, 317.4, 374.0, 487.4", \ + "463.1, 463.1, 463.1, 519.7, 633.1", \ + "753.1, 753.1, 753.1, 809.7, 923.1", \ + "1332.2, 1332.2, 1332.2, 1388.9, 1502.2"); + } + } + } + } + + cell (bf1v0x4) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "a" ; + value : 1.3 ; + } + leakage_power () { + when : "!(a)" ; + value : 3.5 ; + } + pin (a) { + direction : input ; + capacitance : 5.07 ; + } + pin (z) { + function : "a" ; + direction : output ; + capacitance : 5.07 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__33) { + values ("36.6, 36.6, 36.6, 43.9, 56.4", \ + "37.8, 37.8, 37.8, 45.3, 58.5", \ + "34.1, 34.1, 34.1, 41.8, 55.8", \ + "20.8, 20.8, 20.8, 28.8, 43.8", \ + "-10.6, -10.6, -10.6, -2.2, 13.4"); + } + rise_transition (inslew_load_5x5__33) { + values ("25.0, 25.0, 25.0, 35.2, 54.7", \ + "35.3, 35.3, 35.3, 45.4, 65.1", \ + "52.8, 52.8, 52.8, 62.9, 82.8", \ + "84.8, 84.8, 84.8, 95.0, 115.0", \ + "146.3, 146.3, 146.3, 156.6, 177.0"); + } + cell_fall (inslew_load_5x5__33) { + values ("51.6, 51.6, 51.6, 58.5, 70.0", \ + "62.5, 62.5, 62.5, 69.5, 82.1", \ + "79.5, 79.5, 79.5, 87.1, 100.5", \ + "109.4, 109.4, 109.4, 117.2, 132.2", \ + "168.5, 168.5, 168.5, 175.8, 190.1"); + } + fall_transition (inslew_load_5x5__33) { + values ("28.2, 28.2, 28.2, 32.7, 41.1", \ + "39.4, 39.4, 39.4, 44.0, 52.6", \ + "60.4, 60.4, 60.4, 65.1, 74.0", \ + "101.9, 101.9, 101.9, 106.4, 115.5", \ + "183.6, 183.6, 183.6, 188.3, 197.8"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__33) { + values ("328.8, 328.8, 328.8, 392.2, 519.0", \ + "404.8, 404.8, 404.8, 468.2, 595.0", \ + "551.2, 551.2, 551.2, 614.6, 741.4", \ + "838.7, 838.7, 838.7, 902.1, 1028.9", \ + "1409.4, 1409.4, 1409.4, 1472.8, 1599.6"); + } + fall_power (energy_inslew_load_5x5__33) { + values ("420.5, 420.5, 420.5, 483.9, 610.7", \ + "554.2, 554.2, 554.2, 617.6, 744.4", \ + "815.4, 815.4, 815.4, 878.8, 1005.6", \ + "1334.1, 1334.1, 1334.1, 1397.5, 1524.3", \ + "2369.0, 2369.0, 2369.0, 2432.4, 2559.2"); + } + } + } + } + + cell (bf1v0x8) { + area : 0.0 ; + cell_leakage_power : 7.5 ; + leakage_power () { + when : "a" ; + value : 4.4 ; + } + leakage_power () { + when : "!(a)" ; + value : 11 ; + } + pin (a) { + direction : input ; + capacitance : 7.79 ; + } + pin (z) { + function : "a" ; + direction : output ; + capacitance : 9.55 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__34) { + values ("40.3, 40.3, 40.3, 47.8, 60.8", \ + "42.8, 42.8, 42.8, 50.6, 64.1", \ + "41.9, 41.9, 41.9, 49.9, 64.3", \ + "34.0, 34.0, 34.0, 42.1, 57.6", \ + "13.6, 13.6, 13.6, 22.2, 38.2"); + } + rise_transition (inslew_load_5x5__34) { + values ("27.9, 27.9, 27.9, 38.2, 58.2", \ + "38.5, 38.5, 38.5, 48.8, 68.9", \ + "57.1, 57.1, 57.1, 67.5, 87.8", \ + "91.4, 91.4, 91.4, 101.9, 122.4", \ + "157.6, 157.6, 157.6, 168.2, 189.0"); + } + cell_fall (inslew_load_5x5__34) { + values ("50.7, 50.7, 50.7, 57.8, 69.4", \ + "60.3, 60.3, 60.3, 67.3, 80.1", \ + "74.6, 74.6, 74.6, 82.3, 95.6", \ + "99.0, 99.0, 99.0, 107.1, 122.2", \ + "147.0, 147.0, 147.0, 154.3, 169.2"); + } + fall_transition (inslew_load_5x5__34) { + values ("28.6, 28.6, 28.6, 33.1, 41.7", \ + "38.7, 38.7, 38.7, 43.3, 52.0", \ + "57.8, 57.8, 57.8, 62.5, 71.6", \ + "95.7, 95.7, 95.7, 100.2, 109.4", \ + "170.2, 170.2, 170.2, 175.0, 184.5"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__34) { + values ("600.6, 600.6, 600.6, 719.9, 958.6", \ + "740.1, 740.1, 740.1, 859.5, 1098.1", \ + "1010.0, 1010.0, 1010.0, 1129.3, 1368.0", \ + "1539.4, 1539.4, 1539.4, 1658.7, 1897.4", \ + "2590.0, 2590.0, 2590.0, 2709.3, 2948.0"); + } + fall_power (energy_inslew_load_5x5__34) { + values ("732.0, 732.0, 732.0, 851.3, 1090.0", \ + "940.1, 940.1, 940.1, 1059.4, 1298.1", \ + "1348.0, 1348.0, 1348.0, 1467.3, 1705.9", \ + "2158.5, 2158.5, 2158.5, 2277.8, 2516.5", \ + "3775.9, 3775.9, 3775.9, 3895.3, 4133.9"); + } + } + } + } + + cell (bf1v5x05) { + area : 0.0 ; + cell_leakage_power : 4.9 ; + leakage_power () { + when : "1" ; + value : 4.9 ; + } + pin (a) { + direction : input ; + capacitance : 2.66 ; + } + pin (z) { + function : "a" ; + direction : output ; + capacitance : 2.13 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__35) { + values ("39.7, 39.7, 39.7, 51.0, 71.0", \ + "43.2, 43.2, 43.2, 55.3, 76.6", \ + "45.4, 45.4, 45.4, 58.5, 81.8", \ + "46.0, 46.0, 46.0, 60.1, 85.7", \ + "44.4, 44.4, 44.4, 59.5, 87.4"); + } + rise_transition (inslew_load_5x5__35) { + values ("35.6, 35.6, 35.6, 55.2, 94.0", \ + "47.0, 47.0, 47.0, 66.8, 105.5", \ + "67.2, 67.2, 67.2, 87.2, 126.5", \ + "105.1, 105.1, 105.1, 125.5, 165.4", \ + "179.4, 179.4, 179.4, 199.9, 240.6"); + } + cell_fall (inslew_load_5x5__35) { + values ("45.1, 45.1, 45.1, 56.1, 74.6", \ + "51.5, 51.5, 51.5, 63.4, 83.8", \ + "60.6, 60.6, 60.6, 73.5, 96.2", \ + "76.0, 76.0, 76.0, 89.9, 114.8", \ + "103.9, 103.9, 103.9, 118.9, 146.3"); + } + fall_transition (inslew_load_5x5__35) { + values ("29.6, 29.6, 29.6, 38.5, 55.4", \ + "40.3, 40.3, 40.3, 49.6, 66.9", \ + "60.6, 60.6, 60.6, 70.1, 88.2", \ + "100.1, 100.1, 100.1, 109.9, 128.9", \ + "178.5, 178.5, 178.5, 188.6, 208.1"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__35) { + values ("109.5, 109.5, 109.5, 136.2, 189.5", \ + "141.2, 141.2, 141.2, 167.8, 221.2", \ + "203.7, 203.7, 203.7, 230.4, 283.7", \ + "328.0, 328.0, 328.0, 354.7, 408.0", \ + "576.2, 576.2, 576.2, 602.8, 656.2"); + } + fall_power (energy_inslew_load_5x5__35) { + values ("127.6, 127.6, 127.6, 154.2, 207.6", \ + "170.2, 170.2, 170.2, 196.9, 250.2", \ + "254.4, 254.4, 254.4, 281.1, 334.5", \ + "422.2, 422.2, 422.2, 448.9, 502.3", \ + "757.5, 757.5, 757.5, 784.2, 837.5"); + } + } + } + } + + cell (dfnt1v0x2) { + area : 0.0 ; + cell_leakage_power : 14 ; + leakage_power () { + when : "(z & d & !(cp))" ; + value : 15 ; + } + leakage_power () { + when : "(!(z) & d & !(cp))" ; + value : 9.5 ; + } + leakage_power () { + when : "(z & !(d) & !(cp))" ; + value : 18 ; + } + leakage_power () { + when : "(!(z) & !(d) & !(cp))" ; + value : 13 ; + } + ff(iz,iz_neg) { + clocked_on : "cp" ; + next_state : "d" ; + + } + pin (d) { + direction : input ; + capacitance : 2.82 ; + timing (d_cp_setup_rising) { + timing_type : setup_rising ; + related_pin : "cp" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("-38.6, -37.7, -29.1, -4.9, 50.1", \ + "-34.9, -34.0, -25.4, -1.2, 53.8", \ + "-31.2, -30.3, -21.7, 2.5, 57.5", \ + "-27.8, -26.9, -18.3, 5.9, 60.9", \ + "-24.2, -23.3, -14.7, 9.5, 64.5"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("-376.1, -379.1, -376.4, -361.1, -320.4", \ + "-368.7, -371.7, -369.0, -353.7, -313.0", \ + "-356.2, -359.2, -356.5, -341.2, -300.5", \ + "-332.2, -335.2, -332.5, -317.2, -276.5", \ + "-285.6, -288.6, -285.9, -270.6, -229.9"); + } + } + timing (d_cp_hold_rising) { + timing_type : hold_rising ; + related_pin : "cp" ; + rise_constraint (inslew_ckslew_5x5__0) { + values ("81.7, 80.8, 72.2, 48.0, -7.0", \ + "78.0, 77.1, 68.5, 44.3, -10.7", \ + "74.3, 73.4, 64.8, 40.6, -14.4", \ + "70.9, 70.0, 61.4, 37.2, -17.8", \ + "67.3, 66.4, 57.8, 33.6, -21.4"); + } + fall_constraint (inslew_ckslew_5x5__0) { + values ("402.4, 405.4, 402.7, 387.4, 346.7", \ + "395.0, 398.0, 395.3, 380.0, 339.3", \ + "382.5, 385.5, 382.8, 367.5, 326.8", \ + "358.5, 361.5, 358.8, 343.5, 302.8", \ + "311.9, 314.9, 312.2, 296.9, 256.2"); + } + } + internal_power (energy_d) { + rise_power (energy_inslew_5__0) { + values ("114.2, 138.9, 188.1, 286.7, 483.7"); + } + fall_power (energy_inslew_5__0) { + values ("131.4, 161.2, 220.7, 339.7, 577.6"); + } + } + } + pin (cp) { + direction : input ; + capacitance : 2.73 ; + internal_power (energy_cp) { + rise_power (energy_inslew_5__0) { + values ("352.4, 377.1, 425.1, 519.4, 706.4"); + } + fall_power (energy_inslew_5__0) { + values ("416.9, 467.7, 567.6, 766.2, 1162.6"); + } + } + } + pin (z) { + function : "iz" ; + direction : output ; + capacitance : 3.15 ; + timing (maxd_z_cp_rising_edge) { + timing_type : rising_edge ; + related_pin : "cp" ; + cell_fall (inslew_load_5x5__36) { + values ("143.4, 143.4, 143.4, 151.7, 165.4", \ + "144.0, 144.0, 144.0, 152.4, 166.1", \ + "137.0, 137.0, 137.0, 145.3, 159.1", \ + "113.2, 113.2, 113.2, 121.5, 135.4", \ + "53.8, 53.8, 53.8, 62.2, 76.2"); + } + fall_transition (inslew_load_5x5__36) { + values ("29.7, 29.7, 29.7, 35.3, 45.6", \ + "29.9, 29.9, 29.9, 35.5, 45.8", \ + "30.3, 30.3, 30.3, 35.9, 46.3", \ + "30.9, 30.9, 30.9, 36.5, 47.0", \ + "32.0, 32.0, 32.0, 37.6, 48.1"); + } + cell_rise (inslew_load_5x5__36) { + values ("115.0, 115.0, 115.0, 124.0, 139.9", \ + "114.1, 114.1, 114.1, 123.1, 139.1", \ + "101.6, 101.6, 101.6, 110.8, 126.9", \ + "67.3, 67.3, 67.3, 76.5, 92.7", \ + "-14.8, -14.8, -14.8, -5.6, 10.9"); + } + rise_transition (inslew_load_5x5__36) { + values ("40.5, 40.5, 40.5, 53.0, 77.3", \ + "41.8, 41.8, 41.8, 54.3, 78.6", \ + "43.1, 43.1, 43.1, 55.6, 80.0", \ + "45.1, 45.1, 45.1, 57.6, 82.0", \ + "48.1, 48.1, 48.1, 60.7, 85.1"); + } + } + internal_power (energy_nun_z_cp) { + related_pin : "cp" ; + rise_power (energy_inslew_load_5x5__36) { + values ("299.4, 299.4, 299.4, 338.9, 417.7", \ + "304.8, 304.8, 304.8, 344.2, 423.1", \ + "310.1, 310.1, 310.1, 349.6, 428.4", \ + "318.5, 318.5, 318.5, 357.9, 436.8", \ + "331.1, 331.1, 331.1, 370.6, 449.4"); + } + fall_power (energy_inslew_load_5x5__36) { + values ("300.1, 300.1, 300.1, 339.5, 418.4", \ + "301.4, 301.4, 301.4, 340.9, 419.7", \ + "303.9, 303.9, 303.9, 343.3, 422.1", \ + "307.9, 307.9, 307.9, 347.3, 426.2", \ + "314.5, 314.5, 314.5, 353.9, 432.8"); + } + } + } + } + + cell (dly1v0x05) { + area : 0.0 ; + cell_leakage_power : 4.9 ; + leakage_power () { + when : "1" ; + value : 4.9 ; + } + pin (a) { + direction : input ; + capacitance : 2.24 ; + } + pin (z) { + function : "a" ; + direction : output ; + capacitance : 2.80 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__37) { + values ("114.8, 114.8, 114.8, 129.7, 156.1", \ + "113.7, 113.7, 113.7, 128.8, 155.4", \ + "104.8, 104.8, 104.8, 120.2, 147.4", \ + "75.9, 75.9, 75.9, 91.8, 119.8", \ + "7.9, 7.9, 7.9, 24.4, 53.7"); + } + rise_transition (inslew_load_5x5__37) { + values ("50.5, 50.5, 50.5, 76.2, 127.2", \ + "52.9, 52.9, 52.9, 78.6, 129.0", \ + "57.1, 57.1, 57.1, 82.9, 133.5", \ + "64.1, 64.1, 64.1, 90.0, 140.7", \ + "76.2, 76.2, 76.2, 102.4, 153.5"); + } + cell_fall (inslew_load_5x5__37) { + values ("120.2, 120.2, 120.2, 133.6, 156.3", \ + "137.2, 137.2, 137.2, 151.0, 174.2", \ + "163.2, 163.2, 163.2, 177.4, 201.4", \ + "207.1, 207.1, 207.1, 221.9, 247.3", \ + "285.1, 285.1, 285.1, 301.1, 328.4"); + } + fall_transition (inslew_load_5x5__37) { + values ("31.7, 31.7, 31.7, 43.1, 65.0", \ + "34.0, 34.0, 34.0, 45.5, 67.5", \ + "37.9, 37.9, 37.9, 49.6, 71.6", \ + "44.8, 44.8, 44.8, 56.7, 79.1", \ + "57.7, 57.7, 57.7, 69.9, 92.8"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__37) { + values ("261.1, 261.1, 261.1, 296.0, 365.9", \ + "280.1, 280.1, 280.1, 315.0, 384.9", \ + "316.2, 316.2, 316.2, 351.1, 421.0", \ + "383.3, 383.3, 383.3, 418.3, 488.2", \ + "512.7, 512.7, 512.7, 547.7, 617.6"); + } + fall_power (energy_inslew_load_5x5__37) { + values ("270.4, 270.4, 270.4, 305.3, 375.2", \ + "310.5, 310.5, 310.5, 345.5, 415.4", \ + "388.0, 388.0, 388.0, 422.9, 492.8", \ + "539.9, 539.9, 539.9, 574.9, 644.8", \ + "841.7, 841.7, 841.7, 876.6, 946.5"); + } + } + } + } + + cell (dly2v0x05) { + area : 0.0 ; + cell_leakage_power : 0.16 ; + leakage_power () { + when : "a" ; + value : 0.25 ; + } + leakage_power () { + when : "!(a)" ; + value : 0.07 ; + } + pin (a) { + direction : input ; + capacitance : 2.88 ; + } + pin (z) { + function : "a" ; + direction : output ; + capacitance : 2.23 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__38) { + values ("127.4, 127.4, 127.4, 150.3, 191.3", \ + "126.4, 126.4, 126.4, 149.6, 191.3", \ + "123.0, 123.0, 123.0, 146.7, 189.7", \ + "113.0, 113.0, 113.0, 137.6, 182.6", \ + "88.2, 88.2, 88.2, 113.5, 161.0"); + } + rise_transition (inslew_load_5x5__38) { + values ("119.0, 119.0, 119.0, 152.2, 217.3", \ + "129.5, 129.5, 129.5, 162.8, 228.0", \ + "150.9, 150.9, 150.9, 184.3, 249.9", \ + "193.7, 193.7, 193.7, 227.3, 293.4", \ + "279.2, 279.2, 279.2, 313.0, 379.8"); + } + cell_fall (inslew_load_5x5__38) { + values ("159.4, 159.4, 159.4, 181.0, 219.2", \ + "176.5, 176.5, 176.5, 199.2, 239.1", \ + "206.6, 206.6, 206.6, 230.5, 273.0", \ + "264.2, 264.2, 264.2, 289.5, 335.8", \ + "376.6, 376.6, 376.6, 402.3, 452.1"); + } + fall_transition (inslew_load_5x5__38) { + values ("96.6, 96.6, 96.6, 114.6, 148.7", \ + "114.0, 114.0, 114.0, 132.2, 167.0", \ + "146.7, 146.7, 146.7, 165.3, 201.0", \ + "211.4, 211.4, 211.4, 230.3, 266.9", \ + "340.4, 340.4, 340.4, 359.7, 397.4"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__38) { + values ("205.4, 205.4, 205.4, 233.3, 289.0", \ + "225.0, 225.0, 225.0, 252.8, 308.5", \ + "264.3, 264.3, 264.3, 292.2, 347.9", \ + "343.3, 343.3, 343.3, 371.1, 426.9", \ + "501.4, 501.4, 501.4, 529.3, 585.0"); + } + fall_power (energy_inslew_load_5x5__38) { + values ("232.2, 232.2, 232.2, 260.1, 315.8", \ + "275.0, 275.0, 275.0, 302.9, 358.6", \ + "359.0, 359.0, 359.0, 386.8, 442.5", \ + "526.4, 526.4, 526.4, 554.3, 610.0", \ + "861.4, 861.4, 861.4, 889.2, 945.0"); + } + } + } + } + + cell (iv1v0x05) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "a" ; + value : 4.9 ; + } + leakage_power () { + when : "!(a)" ; + value : 3.4e-05 ; + } + pin (a) { + direction : input ; + capacitance : 2.67 ; + } + pin (z) { + function : "!(a)" ; + direction : output ; + capacitance : 1.85 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__39) { + values ("19.5, 19.5, 19.5, 30.4, 49.6", \ + "24.6, 24.6, 24.6, 36.6, 58.2", \ + "33.0, 33.0, 33.0, 45.9, 69.9", \ + "48.7, 48.7, 48.7, 62.2, 88.0", \ + "79.4, 79.4, 79.4, 93.3, 120.4"); + } + rise_transition (inslew_load_5x5__39) { + values ("45.9, 45.9, 45.9, 63.3, 97.2", \ + "76.5, 76.5, 76.5, 94.2, 128.8", \ + "135.6, 135.6, 135.6, 153.6, 188.9", \ + "252.8, 252.8, 252.8, 270.9, 306.8", \ + "486.5, 486.5, 486.5, 504.8, 541.0"); + } + cell_fall (inslew_load_5x5__39) { + values ("12.8, 12.8, 12.8, 22.2, 38.0", \ + "12.1, 12.1, 12.1, 22.9, 41.5", \ + "9.2, 9.2, 9.2, 21.1, 42.5", \ + "2.2, 2.2, 2.2, 14.9, 38.6", \ + "-12.2, -12.2, -12.2, 0.9, 26.2"); + } + fall_transition (inslew_load_5x5__39) { + values ("22.7, 22.7, 22.7, 30.6, 45.3", \ + "38.6, 38.6, 38.6, 46.9, 62.5", \ + "69.4, 69.4, 69.4, 78.1, 94.7", \ + "130.2, 130.2, 130.2, 139.3, 156.7", \ + "251.4, 251.4, 251.4, 260.7, 278.8"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__39) { + values ("51.6, 51.6, 51.6, 74.8, 121.1", \ + "80.5, 80.5, 80.5, 103.7, 150.0", \ + "138.3, 138.3, 138.3, 161.5, 207.8", \ + "253.9, 253.9, 253.9, 277.1, 323.4", \ + "485.1, 485.1, 485.1, 508.3, 554.5"); + } + fall_power (energy_inslew_load_5x5__39) { + values ("45.8, 45.8, 45.8, 68.9, 115.2", \ + "68.0, 68.0, 68.0, 91.2, 137.5", \ + "112.6, 112.6, 112.6, 135.7, 182.0", \ + "201.6, 201.6, 201.6, 224.7, 271.0", \ + "379.6, 379.6, 379.6, 402.7, 449.0"); + } + } + } + } + + cell (iv1v1x05) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "a" ; + value : 4.9 ; + } + leakage_power () { + when : "!(a)" ; + value : 6.2e-05 ; + } + pin (a) { + direction : input ; + capacitance : 2.87 ; + } + pin (z) { + function : "!(a)" ; + direction : output ; + capacitance : 1.95 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__40) { + values ("24.6, 24.6, 24.6, 35.6, 55.2", \ + "36.0, 36.0, 36.0, 47.8, 69.4", \ + "56.5, 56.5, 56.5, 68.9, 92.3", \ + "96.1, 96.1, 96.1, 109.0, 133.8", \ + "174.6, 174.6, 174.6, 187.8, 213.4"); + } + rise_transition (inslew_load_5x5__40) { + values ("52.8, 52.8, 52.8, 71.0, 106.5", \ + "92.3, 92.3, 92.3, 110.7, 146.8", \ + "168.0, 168.0, 168.0, 186.6, 223.2", \ + "317.6, 317.6, 317.6, 336.3, 373.4", \ + "616.0, 616.0, 616.0, 634.7, 672.1"); + } + cell_fall (inslew_load_5x5__40) { + values ("6.6, 6.6, 6.6, 14.7, 28.0", \ + "1.0, 1.0, 1.0, 10.5, 26.6", \ + "-11.6, -11.6, -11.6, -0.8, 18.0", \ + "-37.9, -37.9, -37.9, -26.2, -4.8", \ + "-90.8, -90.8, -90.8, -78.7, -55.6"); + } + fall_transition (inslew_load_5x5__40) { + values ("18.4, 18.4, 18.4, 24.7, 36.2", \ + "30.6, 30.6, 30.6, 37.5, 50.1", \ + "54.4, 54.4, 54.4, 61.8, 75.5", \ + "101.5, 101.5, 101.5, 109.2, 124.0", \ + "195.2, 195.2, 195.2, 203.2, 218.7"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__40) { + values ("63.4, 63.4, 63.4, 87.8, 136.6", \ + "102.6, 102.6, 102.6, 127.0, 175.8", \ + "181.0, 181.0, 181.0, 205.4, 254.2", \ + "337.8, 337.8, 337.8, 362.2, 411.0", \ + "651.4, 651.4, 651.4, 675.8, 724.6"); + } + fall_power (energy_inslew_load_5x5__40) { + values ("44.4, 44.4, 44.4, 68.8, 117.6", \ + "64.2, 64.2, 64.2, 88.6, 137.4", \ + "103.8, 103.8, 103.8, 128.2, 177.0", \ + "182.9, 182.9, 182.9, 207.3, 256.1", \ + "341.2, 341.2, 341.2, 365.6, 414.4"); + } + } + } + } + + + cell (mxi2v0x05) { + area : 0.0 ; + cell_leakage_power : 0.4 ; + leakage_power () { + when : "(s & a1 & a0)" ; + value : 0.81 ; + } + leakage_power () { + when : "(!(s) & a1 & a0)" ; + value : 0.79 ; + } + leakage_power () { + when : "(!(s) & !(a1) & a0)" ; + value : 0.59 ; + } + leakage_power () { + when : "(s & a1 & !(a0))" ; + value : 0.61 ; + } + leakage_power () { + when : "(!(s) & a1 & !(a0))" ; + value : 0.00015 ; + } + leakage_power () { + when : "(!(a1) & s)" ; + value : 0.021 ; + } + leakage_power () { + when : "(!(s) & !(a1) & !(a0))" ; + value : 0.0001 ; + } + pin (s) { + direction : input ; + capacitance : 5.90 ; + } + pin (a1) { + direction : input ; + capacitance : 3.24 ; + } + pin (a0) { + direction : input ; + capacitance : 3.38 ; + } + pin (z) { + function : "((!(a1) & (s | !(a0))) | (!(s) & !(a0)))" ; + direction : output ; + capacitance : 3.93 ; + timing (maxd_z_s_positive_unate) { + related_pin : "s" ; + when : "(a0 & !(a1))" ; + sdf_cond : "(a0 & !(a1))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__41) { + values ("77.5, 77.5, 77.5, 103.1, 154.4", \ + "72.8, 72.8, 72.8, 98.7, 150.1", \ + "56.4, 56.4, 56.4, 82.4, 134.1", \ + "15.6, 15.6, 15.6, 42.1, 94.3", \ + "-72.8, -72.8, -72.8, -45.8, 7.2"); + } + rise_transition (inslew_load_5x5__41) { + values ("107.6, 107.6, 107.6, 154.5, 249.3", \ + "116.9, 116.9, 116.9, 163.8, 258.2", \ + "131.9, 131.9, 131.9, 178.4, 272.4", \ + "158.0, 158.0, 158.0, 204.4, 297.9", \ + "207.4, 207.4, 207.4, 253.1, 345.7"); + } + cell_fall (inslew_load_5x5__41) { + values ("104.8, 104.8, 104.8, 122.7, 156.3", \ + "130.3, 130.3, 130.3, 149.1, 184.2", \ + "173.7, 173.7, 173.7, 193.7, 231.0", \ + "254.6, 254.6, 254.6, 275.7, 315.7", \ + "411.5, 411.5, 411.5, 433.9, 476.6"); + } + fall_transition (inslew_load_5x5__41) { + values ("75.9, 75.9, 75.9, 97.6, 140.9", \ + "93.6, 93.6, 93.6, 115.3, 158.7", \ + "126.4, 126.4, 126.4, 148.2, 191.4", \ + "189.9, 189.9, 189.9, 212.0, 255.6", \ + "315.7, 315.7, 315.7, 338.0, 382.1"); + } + } + timing (maxd_z_a0_negative_unate) { + related_pin : "a0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("40.7, 40.7, 40.7, 68.8, 121.9", \ + "50.6, 50.6, 50.6, 80.6, 136.0", \ + "66.0, 66.0, 66.0, 98.4, 157.9", \ + "93.6, 93.6, 93.6, 128.1, 192.6", \ + "146.7, 146.7, 146.7, 182.7, 251.6"); + } + rise_transition (inslew_load_5x5__41) { + values ("74.6, 74.6, 74.6, 121.9, 217.8", \ + "110.4, 110.4, 110.4, 157.3, 251.6", \ + "177.5, 177.5, 177.5, 224.9, 318.5", \ + "309.0, 309.0, 309.0, 357.0, 451.7", \ + "570.3, 570.3, 570.3, 618.8, 714.9"); + } + cell_fall (inslew_load_5x5__41) { + values ("26.6, 26.6, 26.6, 45.8, 79.5", \ + "26.7, 26.7, 26.7, 49.0, 87.0", \ + "22.5, 22.5, 22.5, 48.4, 92.7", \ + "10.3, 10.3, 10.3, 39.5, 91.1", \ + "-16.5, -16.5, -16.5, 15.0, 73.1"); + } + fall_transition (inslew_load_5x5__41) { + values ("37.6, 37.6, 37.6, 59.6, 103.6", \ + "53.4, 53.4, 53.4, 76.1, 120.0", \ + "82.9, 82.9, 82.9, 106.7, 152.1", \ + "140.3, 140.3, 140.3, 165.1, 212.7", \ + "253.8, 253.8, 253.8, 279.5, 329.2"); + } + } + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("40.7, 40.7, 40.7, 68.8, 121.9", \ + "50.6, 50.6, 50.6, 80.6, 136.0", \ + "66.0, 66.0, 66.0, 98.4, 157.9", \ + "93.6, 93.6, 93.6, 128.1, 192.6", \ + "146.7, 146.7, 146.7, 182.7, 251.6"); + } + rise_transition (inslew_load_5x5__41) { + values ("74.6, 74.6, 74.6, 121.9, 217.8", \ + "110.4, 110.4, 110.4, 157.3, 251.6", \ + "177.5, 177.5, 177.5, 224.9, 318.5", \ + "309.0, 309.0, 309.0, 357.0, 451.7", \ + "570.3, 570.3, 570.3, 618.8, 714.9"); + } + cell_fall (inslew_load_5x5__41) { + values ("26.6, 26.6, 26.6, 45.8, 79.5", \ + "26.7, 26.7, 26.7, 49.0, 87.0", \ + "22.5, 22.5, 22.5, 48.4, 92.7", \ + "10.3, 10.3, 10.3, 39.5, 91.1", \ + "-16.5, -16.5, -16.5, 15.0, 73.1"); + } + fall_transition (inslew_load_5x5__41) { + values ("37.6, 37.6, 37.6, 59.6, 103.6", \ + "53.4, 53.4, 53.4, 76.1, 120.0", \ + "82.9, 82.9, 82.9, 106.7, 152.1", \ + "140.3, 140.3, 140.3, 165.1, 212.7", \ + "253.8, 253.8, 253.8, 279.5, 329.2"); + } + } + timing (maxd_z_s_negative_unate) { + related_pin : "s" ; + when : "(!(a0) & a1)" ; + sdf_cond : "(!(a0) & a1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__41) { + values ("64.0, 64.0, 64.0, 90.1, 141.7", \ + "70.9, 70.9, 70.9, 97.5, 149.7", \ + "82.8, 82.8, 82.8, 110.0, 163.6", \ + "105.3, 105.3, 105.3, 133.4, 188.3", \ + "149.1, 149.1, 149.1, 177.9, 234.5"); + } + rise_transition (inslew_load_5x5__41) { + values ("126.4, 126.4, 126.4, 173.1, 267.4", \ + "164.3, 164.3, 164.3, 210.4, 303.7", \ + "238.9, 238.9, 238.9, 284.2, 375.8", \ + "386.2, 386.2, 386.2, 433.0, 522.9", \ + "681.7, 681.7, 681.7, 726.8, 820.8"); + } + cell_fall (inslew_load_5x5__41) { + values ("37.2, 37.2, 37.2, 53.9, 85.9", \ + "40.1, 40.1, 40.1, 58.1, 91.9", \ + "42.4, 42.4, 42.4, 62.3, 99.2", \ + "43.9, 43.9, 43.9, 65.5, 106.2", \ + "44.6, 44.6, 44.6, 67.5, 111.5"); + } + fall_transition (inslew_load_5x5__41) { + values ("55.7, 55.7, 55.7, 77.4, 121.5", \ + "75.2, 75.2, 75.2, 96.9, 140.2", \ + "113.2, 113.2, 113.2, 135.0, 178.2", \ + "188.1, 188.1, 188.1, 210.3, 254.0", \ + "337.1, 337.1, 337.1, 359.6, 404.1"); + } + } + internal_power (energy_pos_z_s) { + related_pin : "s" ; + when : "(a0 & !(a1))" ; + rise_power (energy_inslew_load_5x5__41) { + values ("172.0, 172.0, 172.0, 221.1, 319.3", \ + "186.6, 186.6, 186.6, 235.7, 333.9", \ + "214.3, 214.3, 214.3, 263.4, 361.6", \ + "267.9, 267.9, 267.9, 317.0, 415.1", \ + "373.2, 373.2, 373.2, 422.3, 520.5"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("218.8, 218.8, 218.8, 267.9, 366.1", \ + "270.1, 270.1, 270.1, 319.2, 417.4", \ + "369.2, 369.2, 369.2, 418.3, 516.5", \ + "565.2, 565.2, 565.2, 614.3, 712.5", \ + "956.0, 956.0, 956.0, 1005.1, 1103.3"); + } + } + internal_power (energy_neg_z_a0) { + related_pin : "a0" ; + rise_power (energy_inslew_load_5x5__41) { + values ("73.4, 73.4, 73.4, 122.5, 220.7", \ + "98.9, 98.9, 98.9, 148.0, 246.2", \ + "149.8, 149.8, 149.8, 198.9, 297.1", \ + "251.8, 251.8, 251.8, 300.9, 399.0", \ + "455.6, 455.6, 455.6, 504.7, 602.9"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("67.5, 67.5, 67.5, 116.6, 214.8", \ + "84.8, 84.8, 84.8, 133.9, 232.0", \ + "119.3, 119.3, 119.3, 168.4, 266.6", \ + "188.3, 188.3, 188.3, 237.4, 335.6", \ + "326.4, 326.4, 326.4, 375.5, 473.7"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__41) { + values ("73.4, 73.4, 73.4, 122.5, 220.7", \ + "98.9, 98.9, 98.9, 148.0, 246.2", \ + "149.8, 149.8, 149.8, 198.9, 297.1", \ + "251.8, 251.8, 251.8, 300.9, 399.0", \ + "455.6, 455.6, 455.6, 504.7, 602.9"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("67.5, 67.5, 67.5, 116.6, 214.8", \ + "84.8, 84.8, 84.8, 133.9, 232.0", \ + "119.3, 119.3, 119.3, 168.4, 266.6", \ + "188.3, 188.3, 188.3, 237.4, 335.6", \ + "326.4, 326.4, 326.4, 375.5, 473.7"); + } + } + internal_power (energy_neg_z_s) { + related_pin : "s" ; + when : "(!(a0) & a1)" ; + rise_power (energy_inslew_load_5x5__41) { + values ("129.6, 129.6, 129.6, 178.7, 276.9", \ + "163.9, 163.9, 163.9, 213.0, 311.1", \ + "232.3, 232.3, 232.3, 281.4, 379.6", \ + "369.3, 369.3, 369.3, 418.4, 516.6", \ + "643.2, 643.2, 643.2, 692.3, 790.5"); + } + fall_power (energy_inslew_load_5x5__41) { + values ("113.0, 113.0, 113.0, 162.1, 260.3", \ + "142.2, 142.2, 142.2, 191.3, 289.5", \ + "200.6, 200.6, 200.6, 249.7, 347.9", \ + "317.4, 317.4, 317.4, 366.5, 464.6", \ + "550.9, 550.9, 550.9, 600.0, 698.2"); + } + } + } + } + + cell (mxi2v0x2) { + area : 0.0 ; + cell_leakage_power : 1.7 ; + leakage_power () { + when : "(a0 & !(s))" ; + value : 3.8 ; + } + leakage_power () { + when : "(a1 & s)" ; + value : 4.3 ; + } + leakage_power () { + when : "(!(s) & a1 & !(a0))" ; + value : 0.00024 ; + } + leakage_power () { + when : "(!(a1) & s)" ; + value : 0.45 ; + } + leakage_power () { + when : "(!(s) & !(a1) & !(a0))" ; + value : 0.00014 ; + } + pin (s) { + direction : input ; + capacitance : 11.92 ; + } + pin (a1) { + direction : input ; + capacitance : 8.71 ; + } + pin (a0) { + direction : input ; + capacitance : 8.92 ; + } + pin (z) { + function : "((!(a0) & (!(a1) | !(s))) | (!(a1) & s))" ; + direction : output ; + capacitance : 8.82 ; + timing (maxd_z_s_positive_unate) { + related_pin : "s" ; + when : "(a0 & !(a1))" ; + sdf_cond : "(a0 & !(a1))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__42) { + values ("68.7, 68.7, 68.7, 90.9, 132.7", \ + "75.8, 75.8, 75.8, 98.6, 141.1", \ + "82.3, 82.3, 82.3, 105.9, 149.6", \ + "86.8, 86.8, 86.8, 111.4, 157.2", \ + "89.1, 89.1, 89.1, 114.8, 163.2"); + } + rise_transition (inslew_load_5x5__42) { + values ("58.2, 58.2, 58.2, 94.4, 167.8", \ + "72.1, 72.1, 72.1, 108.4, 180.8", \ + "96.3, 96.3, 96.3, 132.1, 204.2", \ + "139.9, 139.9, 139.9, 175.8, 247.3", \ + "223.5, 223.5, 223.5, 259.7, 331.3"); + } + cell_fall (inslew_load_5x5__42) { + values ("71.1, 71.1, 71.1, 88.0, 116.5", \ + "79.9, 79.9, 79.9, 97.9, 128.3", \ + "91.4, 91.4, 91.4, 110.9, 144.2", \ + "108.6, 108.6, 108.6, 129.4, 166.5", \ + "136.6, 136.6, 136.6, 160.0, 200.9"); + } + fall_transition (inslew_load_5x5__42) { + values ("43.6, 43.6, 43.6, 59.7, 90.6", \ + "52.8, 52.8, 52.8, 69.2, 100.4", \ + "69.9, 69.9, 69.9, 86.6, 118.6", \ + "103.0, 103.0, 103.0, 120.1, 153.1", \ + "168.3, 168.3, 168.3, 185.7, 219.6"); + } + } + timing (maxd_z_a0_negative_unate) { + related_pin : "a0" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__42) { + values ("62.5, 62.5, 62.5, 83.0, 123.6", \ + "70.7, 70.7, 70.7, 91.5, 132.6", \ + "84.6, 84.6, 84.6, 106.0, 148.2", \ + "111.6, 111.6, 111.6, 133.5, 176.5", \ + "164.6, 164.6, 164.6, 186.9, 231.0"); + } + rise_transition (inslew_load_5x5__42) { + values ("121.7, 121.7, 121.7, 157.5, 229.6", \ + "162.9, 162.9, 162.9, 198.2, 269.4", \ + "242.7, 242.7, 242.7, 277.4, 347.5", \ + "402.1, 402.1, 402.1, 436.4, 505.2", \ + "716.1, 716.1, 716.1, 750.6, 823.3"); + } + cell_fall (inslew_load_5x5__42) { + values ("31.5, 31.5, 31.5, 43.7, 66.9", \ + "33.1, 33.1, 33.1, 46.5, 71.6", \ + "33.2, 33.2, 33.2, 48.2, 76.0", \ + "30.8, 30.8, 30.8, 47.1, 77.9", \ + "24.0, 24.0, 24.0, 41.3, 74.6"); + } + fall_transition (inslew_load_5x5__42) { + values ("46.8, 46.8, 46.8, 62.1, 92.7", \ + "64.7, 64.7, 64.7, 80.0, 110.5", \ + "99.4, 99.4, 99.4, 114.9, 145.5", \ + "167.8, 167.8, 167.8, 183.6, 214.8", \ + "303.7, 303.7, 303.7, 319.8, 351.6"); + } + } + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__42) { + values ("62.5, 62.5, 62.5, 83.0, 123.6", \ + "70.7, 70.7, 70.7, 91.5, 132.6", \ + "84.6, 84.6, 84.6, 106.0, 148.2", \ + "111.6, 111.6, 111.6, 133.5, 176.5", \ + "164.6, 164.6, 164.6, 186.9, 231.0"); + } + rise_transition (inslew_load_5x5__42) { + values ("121.7, 121.7, 121.7, 157.5, 229.6", \ + "162.9, 162.9, 162.9, 198.2, 269.4", \ + "242.7, 242.7, 242.7, 277.4, 347.5", \ + "402.1, 402.1, 402.1, 436.4, 505.2", \ + "716.1, 716.1, 716.1, 750.6, 823.3"); + } + cell_fall (inslew_load_5x5__42) { + values ("31.5, 31.5, 31.5, 43.7, 66.9", \ + "33.1, 33.1, 33.1, 46.5, 71.6", \ + "33.2, 33.2, 33.2, 48.2, 76.0", \ + "30.8, 30.8, 30.8, 47.1, 77.9", \ + "24.0, 24.0, 24.0, 41.3, 74.6"); + } + fall_transition (inslew_load_5x5__42) { + values ("46.8, 46.8, 46.8, 62.1, 92.7", \ + "64.7, 64.7, 64.7, 80.0, 110.5", \ + "99.4, 99.4, 99.4, 114.9, 145.5", \ + "167.8, 167.8, 167.8, 183.6, 214.8", \ + "303.7, 303.7, 303.7, 319.8, 351.6"); + } + } + timing (maxd_z_s_negative_unate) { + related_pin : "s" ; + when : "(!(a0) & a1)" ; + sdf_cond : "(!(a0) & a1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__42) { + values ("35.3, 35.3, 35.3, 57.9, 100.0", \ + "46.0, 46.0, 46.0, 70.0, 114.3", \ + "63.2, 63.2, 63.2, 88.7, 136.1", \ + "94.6, 94.6, 94.6, 121.4, 172.2", \ + "155.7, 155.7, 155.7, 183.4, 236.9"); + } + rise_transition (inslew_load_5x5__42) { + values ("65.1, 65.1, 65.1, 101.4, 174.2", \ + "103.7, 103.7, 103.7, 139.6, 211.7", \ + "175.4, 175.4, 175.4, 211.6, 283.1", \ + "315.4, 315.4, 315.4, 352.0, 424.4", \ + "593.8, 593.8, 593.8, 630.7, 703.9"); + } + cell_fall (inslew_load_5x5__42) { + values ("20.1, 20.1, 20.1, 34.9, 60.4", \ + "18.5, 18.5, 18.5, 36.0, 65.4", \ + "11.9, 11.9, 11.9, 32.2, 66.9", \ + "-3.8, -3.8, -3.8, 18.6, 58.9", \ + "-37.3, -37.3, -37.3, -13.1, 31.7"); + } + fall_transition (inslew_load_5x5__42) { + values ("29.7, 29.7, 29.7, 45.5, 76.4", \ + "44.1, 44.1, 44.1, 60.6, 91.9", \ + "71.1, 71.1, 71.1, 88.4, 121.3", \ + "123.8, 123.8, 123.8, 141.9, 176.5", \ + "228.3, 228.3, 228.3, 247.0, 283.1"); + } + } + internal_power (energy_pos_z_s) { + related_pin : "s" ; + when : "(a0 & !(a1))" ; + rise_power (energy_inslew_load_5x5__42) { + values ("341.1, 341.1, 341.1, 451.4, 671.9", \ + "399.4, 399.4, 399.4, 509.7, 730.3", \ + "512.7, 512.7, 512.7, 623.0, 843.5", \ + "735.4, 735.4, 735.4, 845.6, 1066.2", \ + "1177.8, 1177.8, 1177.8, 1288.0, 1508.6"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("384.7, 384.7, 384.7, 494.9, 715.5", \ + "457.9, 457.9, 457.9, 568.2, 788.7", \ + "601.4, 601.4, 601.4, 711.7, 932.3", \ + "886.6, 886.6, 886.6, 996.9, 1217.4", \ + "1455.5, 1455.5, 1455.5, 1565.8, 1786.3"); + } + } + internal_power (energy_neg_z_a0) { + related_pin : "a0" ; + rise_power (energy_inslew_load_5x5__42) { + values ("364.2, 364.2, 364.2, 474.5, 695.1", \ + "472.5, 472.5, 472.5, 582.8, 803.3", \ + "689.0, 689.0, 689.0, 799.3, 1019.8", \ + "1122.0, 1122.0, 1122.0, 1232.3, 1452.8", \ + "1988.1, 1988.1, 1988.1, 2098.3, 2318.9"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("298.2, 298.2, 298.2, 408.5, 629.0", \ + "380.1, 380.1, 380.1, 490.4, 710.9", \ + "543.9, 543.9, 543.9, 654.2, 874.7", \ + "871.5, 871.5, 871.5, 981.8, 1202.3", \ + "1526.6, 1526.6, 1526.6, 1636.9, 1857.5"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__42) { + values ("364.2, 364.2, 364.2, 474.5, 695.1", \ + "472.5, 472.5, 472.5, 582.8, 803.3", \ + "689.0, 689.0, 689.0, 799.3, 1019.8", \ + "1122.0, 1122.0, 1122.0, 1232.3, 1452.8", \ + "1988.1, 1988.1, 1988.1, 2098.3, 2318.9"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("298.2, 298.2, 298.2, 408.5, 629.0", \ + "380.1, 380.1, 380.1, 490.4, 710.9", \ + "543.9, 543.9, 543.9, 654.2, 874.7", \ + "871.5, 871.5, 871.5, 981.8, 1202.3", \ + "1526.6, 1526.6, 1526.6, 1636.9, 1857.5"); + } + } + internal_power (energy_neg_z_s) { + related_pin : "s" ; + when : "(!(a0) & a1)" ; + rise_power (energy_inslew_load_5x5__42) { + values ("187.6, 187.6, 187.6, 297.9, 518.4", \ + "268.4, 268.4, 268.4, 378.6, 599.2", \ + "429.9, 429.9, 429.9, 540.2, 760.7", \ + "752.9, 752.9, 752.9, 863.2, 1083.8", \ + "1399.0, 1399.0, 1399.0, 1509.3, 1729.8"); + } + fall_power (energy_inslew_load_5x5__42) { + values ("162.2, 162.2, 162.2, 272.5, 493.0", \ + "210.7, 210.7, 210.7, 321.0, 541.6", \ + "307.8, 307.8, 307.8, 418.0, 638.6", \ + "501.8, 501.8, 501.8, 612.1, 832.7", \ + "890.0, 890.0, 890.0, 1000.3, 1220.8"); + } + } + } + } + + cell (mxn2v0x05) { + area : 0.0 ; + cell_leakage_power : 6 ; + leakage_power () { + when : "(a0 & a1)" ; + value : 6.5 ; + } + leakage_power () { + when : "((a0 & !(a1) & !(s)) | (!(a0) & a1 & s))" ; + value : 6.6 ; + } + leakage_power () { + when : "((!(a0) & (!(a1) | !(s))) | (!(a1) & s))" ; + value : 4.9 ; + } + pin (s) { + direction : input ; + capacitance : 4.66 ; + } + pin (a1) { + direction : input ; + capacitance : 2.74 ; + } + pin (a0) { + direction : input ; + capacitance : 2.80 ; + } + pin (z) { + function : "((a1 & (a0 | s)) | (a0 & !(s)))" ; + direction : output ; + capacitance : 2.27 ; + timing (maxd_z_a0_positive_unate) { + related_pin : "a0" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("72.1, 72.1, 72.1, 85.7, 109.6", \ + "76.8, 76.8, 76.8, 90.9, 115.9", \ + "82.0, 82.0, 82.0, 96.7, 123.2", \ + "87.0, 87.0, 87.0, 102.6, 131.0", \ + "92.3, 92.3, 92.3, 108.6, 139.1"); + } + rise_transition (inslew_load_5x5__43) { + values ("62.9, 62.9, 62.9, 84.2, 125.8", \ + "74.5, 74.5, 74.5, 95.9, 137.8", \ + "96.7, 96.7, 96.7, 118.3, 160.7", \ + "140.0, 140.0, 140.0, 161.8, 204.7", \ + "225.3, 225.3, 225.3, 247.2, 290.8"); + } + cell_fall (inslew_load_5x5__43) { + values ("104.4, 104.4, 104.4, 118.3, 143.1", \ + "113.0, 113.0, 113.0, 127.3, 153.1", \ + "127.5, 127.5, 127.5, 142.5, 169.5", \ + "154.7, 154.7, 154.7, 170.4, 199.3", \ + "206.9, 206.9, 206.9, 223.1, 254.0"); + } + fall_transition (inslew_load_5x5__43) { + values ("69.7, 69.7, 69.7, 80.1, 99.6", \ + "84.3, 84.3, 84.3, 94.8, 114.7", \ + "112.7, 112.7, 112.7, 123.3, 143.8", \ + "169.5, 169.5, 169.5, 180.4, 201.4", \ + "281.6, 281.6, 281.6, 292.6, 314.2"); + } + } + timing (maxd_z_a1_positive_unate) { + related_pin : "a1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("72.1, 72.1, 72.1, 85.7, 109.6", \ + "76.8, 76.8, 76.8, 90.9, 115.9", \ + "82.0, 82.0, 82.0, 96.7, 123.2", \ + "87.0, 87.0, 87.0, 102.6, 131.0", \ + "92.3, 92.3, 92.3, 108.6, 139.1"); + } + rise_transition (inslew_load_5x5__43) { + values ("62.9, 62.9, 62.9, 84.2, 125.8", \ + "74.5, 74.5, 74.5, 95.9, 137.8", \ + "96.7, 96.7, 96.7, 118.3, 160.7", \ + "140.0, 140.0, 140.0, 161.8, 204.7", \ + "225.3, 225.3, 225.3, 247.2, 290.8"); + } + cell_fall (inslew_load_5x5__43) { + values ("104.4, 104.4, 104.4, 118.3, 143.1", \ + "113.0, 113.0, 113.0, 127.3, 153.1", \ + "127.5, 127.5, 127.5, 142.5, 169.5", \ + "154.7, 154.7, 154.7, 170.4, 199.3", \ + "206.9, 206.9, 206.9, 223.1, 254.0"); + } + fall_transition (inslew_load_5x5__43) { + values ("69.7, 69.7, 69.7, 80.1, 99.6", \ + "84.3, 84.3, 84.3, 94.8, 114.7", \ + "112.7, 112.7, 112.7, 123.3, 143.8", \ + "169.5, 169.5, 169.5, 180.4, 201.4", \ + "281.6, 281.6, 281.6, 292.6, 314.2"); + } + } + timing (maxd_z_s_positive_unate) { + related_pin : "s" ; + when : "(!(a0) & a1)" ; + sdf_cond : "(!(a0) & a1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__43) { + values ("61.4, 61.4, 61.4, 74.4, 97.2", \ + "64.4, 64.4, 64.4, 77.9, 101.7", \ + "63.1, 63.1, 63.1, 77.3, 102.7", \ + "52.8, 52.8, 52.8, 67.8, 95.1", \ + "25.2, 25.2, 25.2, 41.2, 70.5"); + } + rise_transition (inslew_load_5x5__43) { + values ("51.7, 51.7, 51.7, 72.8, 114.1", \ + "61.4, 61.4, 61.4, 82.7, 124.2", \ + "78.9, 78.9, 78.9, 100.3, 142.3", \ + "111.5, 111.5, 111.5, 133.2, 175.8", \ + "174.8, 174.8, 174.8, 196.7, 239.9"); + } + cell_fall (inslew_load_5x5__43) { + values ("81.6, 81.6, 81.6, 94.9, 117.7", \ + "95.2, 95.2, 95.2, 109.0, 133.3", \ + "115.9, 115.9, 115.9, 130.4, 156.5", \ + "150.9, 150.9, 150.9, 166.3, 194.4", \ + "216.2, 216.2, 216.2, 232.3, 262.6"); + } + fall_transition (inslew_load_5x5__43) { + values ("50.4, 50.4, 50.4, 60.4, 79.4", \ + "64.2, 64.2, 64.2, 74.5, 93.9", \ + "90.1, 90.1, 90.1, 100.7, 120.8", \ + "140.4, 140.4, 140.4, 151.2, 172.1", \ + "239.8, 239.8, 239.8, 250.8, 272.1"); + } + } + timing (maxd_z_s_negative_unate) { + related_pin : "s" ; + when : "(a0 & !(a1))" ; + sdf_cond : "(a0 & !(a1))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__43) { + values ("128.2, 128.2, 128.2, 141.8, 165.7", \ + "152.2, 152.2, 152.2, 166.2, 190.9", \ + "191.2, 191.2, 191.2, 205.7, 231.5", \ + "261.3, 261.3, 261.3, 276.4, 303.9", \ + "393.1, 393.1, 393.1, 408.9, 438.2"); + } + rise_transition (inslew_load_5x5__43) { + values ("62.2, 62.2, 62.2, 83.5, 125.1", \ + "70.8, 70.8, 70.8, 92.2, 134.0", \ + "86.1, 86.1, 86.1, 107.6, 149.8", \ + "114.9, 114.9, 114.9, 136.6, 179.2", \ + "171.0, 171.0, 171.0, 192.9, 236.1"); + } + cell_fall (inslew_load_5x5__43) { + values ("91.4, 91.4, 91.4, 104.2, 126.1", \ + "88.9, 88.9, 88.9, 102.0, 124.3", \ + "75.6, 75.6, 75.6, 89.0, 112.1", \ + "39.3, 39.3, 39.3, 53.0, 77.1", \ + "-42.6, -42.6, -42.6, -28.4, -2.8"); + } + fall_transition (inslew_load_5x5__43) { + values ("43.4, 43.4, 43.4, 53.3, 71.9", \ + "47.0, 47.0, 47.0, 57.0, 75.8", \ + "52.8, 52.8, 52.8, 62.8, 81.8", \ + "62.3, 62.3, 62.3, 72.5, 91.9", \ + "79.9, 79.9, 79.9, 90.4, 110.2"); + } + } + internal_power (energy_pos_z_a0) { + related_pin : "a0" ; + rise_power (energy_inslew_load_5x5__43) { + values ("184.0, 184.0, 184.0, 212.4, 269.1", \ + "216.9, 216.9, 216.9, 245.3, 302.1", \ + "282.4, 282.4, 282.4, 310.8, 367.6", \ + "412.7, 412.7, 412.7, 441.1, 497.8", \ + "672.6, 672.6, 672.6, 701.0, 757.8"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("243.6, 243.6, 243.6, 272.0, 328.7", \ + "292.3, 292.3, 292.3, 320.7, 377.5", \ + "389.0, 389.0, 389.0, 417.4, 474.2", \ + "582.7, 582.7, 582.7, 611.1, 667.9", \ + "968.2, 968.2, 968.2, 996.6, 1053.3"); + } + } + internal_power (energy_pos_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__43) { + values ("184.0, 184.0, 184.0, 212.4, 269.1", \ + "216.9, 216.9, 216.9, 245.3, 302.1", \ + "282.4, 282.4, 282.4, 310.8, 367.6", \ + "412.7, 412.7, 412.7, 441.1, 497.8", \ + "672.6, 672.6, 672.6, 701.0, 757.8"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("243.6, 243.6, 243.6, 272.0, 328.7", \ + "292.3, 292.3, 292.3, 320.7, 377.5", \ + "389.0, 389.0, 389.0, 417.4, 474.2", \ + "582.7, 582.7, 582.7, 611.1, 667.9", \ + "968.2, 968.2, 968.2, 996.6, 1053.3"); + } + } + internal_power (energy_pos_z_s) { + related_pin : "s" ; + when : "(!(a0) & a1)" ; + rise_power (energy_inslew_load_5x5__43) { + values ("137.4, 137.4, 137.4, 165.7, 222.5", \ + "158.6, 158.6, 158.6, 187.0, 243.7", \ + "199.6, 199.6, 199.6, 228.0, 284.8", \ + "280.3, 280.3, 280.3, 308.7, 365.4", \ + "440.3, 440.3, 440.3, 468.7, 525.4"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("171.8, 171.8, 171.8, 200.2, 257.0", \ + "212.0, 212.0, 212.0, 240.3, 297.1", \ + "290.1, 290.1, 290.1, 318.5, 375.2", \ + "444.5, 444.5, 444.5, 472.8, 529.6", \ + "752.0, 752.0, 752.0, 780.3, 837.1"); + } + } + internal_power (energy_neg_z_s) { + related_pin : "s" ; + when : "(a0 & !(a1))" ; + rise_power (energy_inslew_load_5x5__43) { + values ("235.7, 235.7, 235.7, 264.1, 320.8", \ + "279.8, 279.8, 279.8, 308.2, 364.9", \ + "365.0, 365.0, 365.0, 393.4, 450.2", \ + "533.3, 533.3, 533.3, 561.6, 618.4", \ + "868.2, 868.2, 868.2, 896.6, 953.3"); + } + fall_power (energy_inslew_load_5x5__43) { + values ("211.4, 211.4, 211.4, 239.7, 296.5", \ + "228.2, 228.2, 228.2, 256.5, 313.3", \ + "258.8, 258.8, 258.8, 287.2, 343.9", \ + "316.4, 316.4, 316.4, 344.8, 401.6", \ + "428.8, 428.8, 428.8, 457.2, 513.9"); + } + } + } + } + + cell (nd2abv0x05) { + area : 0.0 ; + cell_leakage_power : 7.3 ; + leakage_power () { + when : "(a ^ b)" ; + value : 4.9 ; + } + leakage_power () { + when : "!((a ^ b))" ; + value : 9.7 ; + } + pin (b) { + direction : input ; + capacitance : 2.97 ; + } + pin (a) { + direction : input ; + capacitance : 2.68 ; + } + pin (z) { + function : "(b | a)" ; + direction : output ; + capacitance : 2.94 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__44) { + values ("60.0, 60.0, 60.0, 74.0, 100.3", \ + "68.5, 68.5, 68.5, 83.1, 110.4", \ + "78.6, 78.6, 78.6, 94.1, 122.8", \ + "92.8, 92.8, 92.8, 109.2, 139.9", \ + "116.3, 116.3, 116.3, 133.6, 166.5"); + } + rise_transition (inslew_load_5x5__44) { + values ("62.4, 62.4, 62.4, 89.0, 142.2", \ + "80.1, 80.1, 80.1, 106.7, 160.2", \ + "110.4, 110.4, 110.4, 137.2, 190.4", \ + "166.4, 166.4, 166.4, 193.6, 247.3", \ + "275.1, 275.1, 275.1, 302.5, 356.9"); + } + cell_fall (inslew_load_5x5__44) { + values ("49.9, 49.9, 49.9, 60.3, 79.0", \ + "53.2, 53.2, 53.2, 64.5, 84.5", \ + "55.5, 55.5, 55.5, 68.0, 90.2", \ + "56.2, 56.2, 56.2, 69.7, 94.9", \ + "53.6, 53.6, 53.6, 68.9, 96.6"); + } + fall_transition (inslew_load_5x5__44) { + values ("36.2, 36.2, 36.2, 47.4, 69.2", \ + "43.3, 43.3, 43.3, 54.7, 76.7", \ + "56.8, 56.8, 56.8, 68.4, 90.9", \ + "82.7, 82.7, 82.7, 95.0, 118.1", \ + "133.7, 133.7, 133.7, 146.3, 170.7"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__44) { + values ("50.8, 50.8, 50.8, 65.8, 92.6", \ + "57.1, 57.1, 57.1, 72.8, 100.9", \ + "63.3, 63.3, 63.3, 80.1, 110.1", \ + "70.4, 70.4, 70.4, 88.3, 120.8", \ + "80.5, 80.5, 80.5, 99.2, 134.5"); + } + rise_transition (inslew_load_5x5__44) { + values ("45.8, 45.8, 45.8, 72.7, 125.9", \ + "60.3, 60.3, 60.3, 87.3, 140.4", \ + "85.2, 85.2, 85.2, 112.5, 166.0", \ + "131.4, 131.4, 131.4, 158.9, 213.1", \ + "220.7, 220.7, 220.7, 248.6, 303.5"); + } + cell_fall (inslew_load_5x5__44) { + values ("48.1, 48.1, 48.1, 60.7, 81.9", \ + "53.0, 53.0, 53.0, 66.8, 90.0", \ + "59.0, 59.0, 59.0, 73.9, 99.8", \ + "66.4, 66.4, 66.4, 83.2, 112.1", \ + "79.6, 79.6, 79.6, 96.5, 129.4"); + } + fall_transition (inslew_load_5x5__44) { + values ("31.9, 31.9, 31.9, 43.7, 66.0", \ + "40.7, 40.7, 40.7, 52.7, 75.5", \ + "57.1, 57.1, 57.1, 69.5, 93.1", \ + "89.1, 89.1, 89.1, 101.9, 126.5", \ + "152.4, 152.4, 152.4, 165.6, 191.0"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__44) { + values ("164.2, 164.2, 164.2, 201.0, 274.4", \ + "202.0, 202.0, 202.0, 238.7, 312.2", \ + "275.8, 275.8, 275.8, 312.5, 386.0", \ + "422.2, 422.2, 422.2, 458.9, 532.4", \ + "713.9, 713.9, 713.9, 750.6, 824.1"); + } + fall_power (energy_inslew_load_5x5__44) { + values ("171.9, 171.9, 171.9, 208.6, 282.1", \ + "211.8, 211.8, 211.8, 248.5, 322.0", \ + "290.8, 290.8, 290.8, 327.5, 401.0", \ + "448.2, 448.2, 448.2, 484.9, 558.4", \ + "762.6, 762.6, 762.6, 799.3, 872.8"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__44) { + values ("139.0, 139.0, 139.0, 175.7, 249.2", \ + "173.4, 173.4, 173.4, 210.1, 283.6", \ + "240.9, 240.9, 240.9, 277.6, 351.1", \ + "374.7, 374.7, 374.7, 411.4, 484.9", \ + "641.5, 641.5, 641.5, 678.3, 751.8"); + } + fall_power (energy_inslew_load_5x5__44) { + values ("150.1, 150.1, 150.1, 186.8, 260.3", \ + "191.4, 191.4, 191.4, 228.1, 301.6", \ + "273.0, 273.0, 273.0, 309.8, 383.3", \ + "435.7, 435.7, 435.7, 472.5, 546.0", \ + "760.6, 760.6, 760.6, 797.4, 870.9"); + } + } + } + } + + cell (nd2av0x05) { + area : 0.0 ; + cell_leakage_power : 1.9 ; + leakage_power () { + when : "a" ; + value : 4.7 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 1.1 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 9.9e-05 ; + } + pin (b) { + direction : input ; + capacitance : 2.68 ; + } + pin (a) { + direction : input ; + capacitance : 2.77 ; + } + pin (z) { + function : "(!(b) | a)" ; + direction : output ; + capacitance : 2.29 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__45) { + values ("55.2, 55.2, 55.2, 71.0, 101.1", \ + "60.6, 60.6, 60.6, 77.0, 107.8", \ + "65.0, 65.0, 65.0, 82.3, 114.5", \ + "67.5, 67.5, 67.5, 85.9, 120.2", \ + "67.2, 67.2, 67.2, 86.6, 123.4"); + } + rise_transition (inslew_load_5x5__45) { + values ("62.7, 62.7, 62.7, 94.0, 156.2", \ + "79.5, 79.5, 79.5, 110.6, 172.9", \ + "107.7, 107.7, 107.7, 139.0, 201.1", \ + "158.8, 158.8, 158.8, 190.4, 253.1", \ + "257.0, 257.0, 257.0, 289.0, 352.3"); + } + cell_fall (inslew_load_5x5__45) { + values ("50.7, 50.7, 50.7, 62.4, 83.4", \ + "55.7, 55.7, 55.7, 68.4, 91.1", \ + "61.3, 61.3, 61.3, 75.5, 100.7", \ + "68.7, 68.7, 68.7, 84.4, 113.0", \ + "79.5, 79.5, 79.5, 97.0, 129.2"); + } + fall_transition (inslew_load_5x5__45) { + values ("38.8, 38.8, 38.8, 51.7, 76.9", \ + "46.9, 46.9, 46.9, 60.0, 85.4", \ + "62.0, 62.0, 62.0, 75.4, 101.4", \ + "91.2, 91.2, 91.2, 105.1, 132.0", \ + "148.6, 148.6, 148.6, 163.0, 191.0"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__45) { + values ("32.3, 32.3, 32.3, 50.0, 81.8", \ + "44.0, 44.0, 44.0, 63.4, 98.3", \ + "64.0, 64.0, 64.0, 85.0, 123.5", \ + "101.9, 101.9, 101.9, 124.0, 165.7", \ + "176.4, 176.4, 176.4, 199.2, 243.2"); + } + rise_transition (inslew_load_5x5__45) { + values ("64.3, 64.3, 64.3, 95.9, 158.5", \ + "103.2, 103.2, 103.2, 135.2, 198.1", \ + "176.9, 176.9, 176.9, 209.3, 273.3", \ + "321.8, 321.8, 321.8, 354.5, 419.4", \ + "610.3, 610.3, 610.3, 643.3, 708.8"); + } + cell_fall (inslew_load_5x5__45) { + values ("14.3, 14.3, 14.3, 27.1, 48.8", \ + "10.2, 10.2, 10.2, 25.4, 50.9", \ + "-0.7, -0.7, -0.7, 16.8, 47.2", \ + "-24.8, -24.8, -24.8, -5.2, 29.9", \ + "-74.5, -74.5, -74.5, -53.5, -14.3"); + } + fall_transition (inslew_load_5x5__45) { + values ("27.0, 27.0, 27.0, 40.3, 65.9", \ + "40.0, 40.0, 40.0, 53.9, 80.3", \ + "64.7, 64.7, 64.7, 79.5, 107.3", \ + "113.3, 113.3, 113.3, 128.7, 158.3", \ + "209.8, 209.8, 209.8, 225.7, 256.6"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__45) { + values ("124.2, 124.2, 124.2, 152.9, 210.2", \ + "151.7, 151.7, 151.7, 180.3, 237.7", \ + "205.6, 205.6, 205.6, 234.2, 291.6", \ + "312.5, 312.5, 312.5, 341.2, 398.6", \ + "525.8, 525.8, 525.8, 554.5, 611.8"); + } + fall_power (energy_inslew_load_5x5__45) { + values ("138.4, 138.4, 138.4, 167.0, 224.4", \ + "175.7, 175.7, 175.7, 204.3, 261.7", \ + "249.5, 249.5, 249.5, 278.2, 335.5", \ + "396.7, 396.7, 396.7, 425.4, 482.8", \ + "691.0, 691.0, 691.0, 719.7, 777.0"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__45) { + values ("53.7, 53.7, 53.7, 82.4, 139.7", \ + "79.4, 79.4, 79.4, 108.1, 165.5", \ + "130.9, 130.9, 130.9, 159.6, 216.9", \ + "233.8, 233.8, 233.8, 262.5, 319.8", \ + "439.6, 439.6, 439.6, 468.3, 525.6"); + } + fall_power (energy_inslew_load_5x5__45) { + values ("42.9, 42.9, 42.9, 71.6, 128.9", \ + "56.4, 56.4, 56.4, 85.1, 142.5", \ + "83.5, 83.5, 83.5, 112.2, 169.6", \ + "137.7, 137.7, 137.7, 166.4, 223.8", \ + "246.1, 246.1, 246.1, 274.8, 332.1"); + } + } + } + } + + cell (nd2av0x1) { + area : 0.0 ; + cell_leakage_power : 1.3 ; + leakage_power () { + when : "a" ; + value : 1.3 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 2.6 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 0.00014 ; + } + pin (b) { + direction : input ; + capacitance : 4.15 ; + } + pin (a) { + direction : input ; + capacitance : 3.01 ; + } + pin (z) { + function : "(!(b) | a)" ; + direction : output ; + capacitance : 3.08 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__46) { + values ("56.2, 56.2, 56.2, 68.8, 92.4", \ + "64.0, 64.0, 64.0, 77.1, 101.6", \ + "73.0, 73.0, 73.0, 86.9, 112.7", \ + "85.2, 85.2, 85.2, 99.9, 127.4", \ + "104.8, 104.8, 104.8, 120.2, 149.6"); + } + rise_transition (inslew_load_5x5__46) { + values ("56.7, 56.7, 56.7, 79.9, 126.2", \ + "74.2, 74.2, 74.2, 97.4, 144.0", \ + "103.9, 103.9, 103.9, 127.4, 173.6", \ + "158.8, 158.8, 158.8, 182.5, 229.2", \ + "264.8, 264.8, 264.8, 288.6, 335.9"); + } + cell_fall (inslew_load_5x5__46) { + values ("47.4, 47.4, 47.4, 56.4, 72.7", \ + "51.0, 51.0, 51.0, 60.8, 78.4", \ + "53.7, 53.7, 53.7, 64.7, 84.3", \ + "55.7, 55.7, 55.7, 67.7, 89.9", \ + "55.8, 55.8, 55.8, 69.2, 93.9"); + } + fall_transition (inslew_load_5x5__46) { + values ("33.1, 33.1, 33.1, 42.6, 61.1", \ + "40.0, 40.0, 40.0, 49.7, 68.4", \ + "53.0, 53.0, 53.0, 62.9, 82.2", \ + "77.9, 77.9, 77.9, 88.3, 108.3", \ + "127.1, 127.1, 127.1, 137.9, 158.7"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__46) { + values ("27.7, 27.7, 27.7, 41.9, 67.3", \ + "38.7, 38.7, 38.7, 54.2, 82.3", \ + "57.8, 57.8, 57.8, 74.3, 105.1", \ + "94.0, 94.0, 94.0, 111.3, 144.3", \ + "165.4, 165.4, 165.4, 183.2, 217.7"); + } + rise_transition (inslew_load_5x5__46) { + values ("55.4, 55.4, 55.4, 79.1, 125.4", \ + "93.5, 93.5, 93.5, 117.5, 164.5", \ + "165.5, 165.5, 165.5, 189.8, 237.6", \ + "307.3, 307.3, 307.3, 331.8, 380.3", \ + "589.8, 589.8, 589.8, 614.5, 663.4"); + } + cell_fall (inslew_load_5x5__46) { + values ("10.9, 10.9, 10.9, 21.4, 38.8", \ + "6.5, 6.5, 6.5, 18.9, 39.6", \ + "-4.4, -4.4, -4.4, 9.7, 34.3", \ + "-27.8, -27.8, -27.8, -12.2, 15.9", \ + "-75.5, -75.5, -75.5, -59.0, -28.0"); + } + fall_transition (inslew_load_5x5__46) { + values ("22.7, 22.7, 22.7, 32.6, 51.5", \ + "35.0, 35.0, 35.0, 45.6, 65.4", \ + "58.7, 58.7, 58.7, 69.9, 90.9", \ + "105.5, 105.5, 105.5, 117.2, 139.5", \ + "198.6, 198.6, 198.6, 210.6, 233.9"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__46) { + values ("184.3, 184.3, 184.3, 222.8, 299.9", \ + "228.2, 228.2, 228.2, 266.7, 343.7", \ + "314.0, 314.0, 314.0, 352.5, 429.6", \ + "484.3, 484.3, 484.3, 522.8, 599.8", \ + "823.5, 823.5, 823.5, 862.0, 939.0"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("194.2, 194.2, 194.2, 232.7, 309.7", \ + "242.0, 242.0, 242.0, 280.5, 357.5", \ + "336.5, 336.5, 336.5, 375.0, 452.0", \ + "524.9, 524.9, 524.9, 563.4, 640.4", \ + "901.3, 901.3, 901.3, 939.8, 1016.9"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__46) { + values ("81.7, 81.7, 81.7, 120.2, 197.2", \ + "126.0, 126.0, 126.0, 164.5, 241.5", \ + "214.5, 214.5, 214.5, 253.0, 330.1", \ + "391.6, 391.6, 391.6, 430.1, 507.1", \ + "745.8, 745.8, 745.8, 784.3, 861.3"); + } + fall_power (energy_inslew_load_5x5__46) { + values ("62.7, 62.7, 62.7, 101.2, 178.2", \ + "85.8, 85.8, 85.8, 124.3, 201.3", \ + "131.9, 131.9, 131.9, 170.4, 247.5", \ + "224.3, 224.3, 224.3, 262.8, 339.8", \ + "409.0, 409.0, 409.0, 447.5, 524.5"); + } + } + } + } + + cell (nd2av0x2) { + area : 0.0 ; + cell_leakage_power : 1.1 ; + leakage_power () { + when : "a" ; + value : 0.45 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 2.9 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 0.00016 ; + } + pin (b) { + direction : input ; + capacitance : 5.20 ; + } + pin (a) { + direction : input ; + capacitance : 3.55 ; + } + pin (z) { + function : "(!(b) | a)" ; + direction : output ; + capacitance : 4.45 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__47) { + values ("55.3, 55.3, 55.3, 66.7, 87.8", \ + "62.9, 62.9, 62.9, 74.7, 96.7", \ + "71.0, 71.0, 71.0, 83.5, 106.6", \ + "81.2, 81.2, 81.2, 94.4, 119.1", \ + "96.7, 96.7, 96.7, 110.5, 136.8"); + } + rise_transition (inslew_load_5x5__47) { + values ("50.8, 50.8, 50.8, 70.1, 108.5", \ + "67.3, 67.3, 67.3, 86.6, 124.8", \ + "95.2, 95.2, 95.2, 114.6, 152.9", \ + "146.4, 146.4, 146.4, 166.0, 204.8", \ + "245.4, 245.4, 245.4, 265.1, 304.3"); + } + cell_fall (inslew_load_5x5__47) { + values ("48.7, 48.7, 48.7, 56.8, 71.6", \ + "53.0, 53.0, 53.0, 61.9, 77.8", \ + "57.4, 57.4, 57.4, 67.3, 84.8", \ + "62.4, 62.4, 62.4, 73.0, 92.9", \ + "68.7, 68.7, 68.7, 80.7, 102.6"); + } + fall_transition (inslew_load_5x5__47) { + values ("31.7, 31.7, 31.7, 40.2, 56.7", \ + "38.3, 38.3, 38.3, 47.0, 63.7", \ + "50.8, 50.8, 50.8, 59.6, 76.8", \ + "74.6, 74.6, 74.6, 83.9, 101.7", \ + "121.6, 121.6, 121.6, 131.3, 149.8"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__47) { + values ("26.1, 26.1, 26.1, 39.0, 62.0", \ + "37.1, 37.1, 37.1, 51.0, 76.4", \ + "56.0, 56.0, 56.0, 70.9, 98.5", \ + "92.1, 92.1, 92.1, 107.6, 137.1", \ + "163.3, 163.3, 163.3, 179.1, 209.9"); + } + rise_transition (inslew_load_5x5__47) { + values ("50.5, 50.5, 50.5, 70.2, 108.6", \ + "87.3, 87.3, 87.3, 107.3, 146.3", \ + "157.1, 157.1, 157.1, 177.3, 217.1", \ + "294.6, 294.6, 294.6, 314.9, 355.3", \ + "568.3, 568.3, 568.3, 588.8, 629.5"); + } + cell_fall (inslew_load_5x5__47) { + values ("9.8, 9.8, 9.8, 19.5, 35.5", \ + "5.2, 5.2, 5.2, 16.5, 35.7", \ + "-5.9, -5.9, -5.9, 6.9, 29.5", \ + "-29.5, -29.5, -29.5, -15.4, 10.2", \ + "-77.5, -77.5, -77.5, -62.7, -34.6"); + } + fall_transition (inslew_load_5x5__47) { + values ("21.6, 21.6, 21.6, 30.6, 47.5", \ + "34.0, 34.0, 34.0, 43.5, 61.3", \ + "57.9, 57.9, 57.9, 67.9, 86.8", \ + "105.0, 105.0, 105.0, 115.4, 135.5", \ + "198.8, 198.8, 198.8, 209.5, 230.4"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__47) { + values ("267.3, 267.3, 267.3, 323.0, 434.3", \ + "328.0, 328.0, 328.0, 383.7, 495.1", \ + "446.4, 446.4, 446.4, 502.1, 613.5", \ + "680.6, 680.6, 680.6, 736.3, 847.7", \ + "1146.8, 1146.8, 1146.8, 1202.5, 1313.9"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("280.9, 280.9, 280.9, 336.6, 448.0", \ + "344.9, 344.9, 344.9, 400.5, 511.9", \ + "471.1, 471.1, 471.1, 526.7, 638.1", \ + "722.4, 722.4, 722.4, 778.1, 889.5", \ + "1224.6, 1224.6, 1224.6, 1280.3, 1391.7"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__47) { + values ("126.4, 126.4, 126.4, 182.1, 293.4", \ + "198.9, 198.9, 198.9, 254.6, 366.0", \ + "344.0, 344.0, 344.0, 399.7, 511.0", \ + "634.2, 634.2, 634.2, 689.9, 801.2", \ + "1214.5, 1214.5, 1214.5, 1270.2, 1381.5"); + } + fall_power (energy_inslew_load_5x5__47) { + values ("95.1, 95.1, 95.1, 150.7, 262.1", \ + "132.6, 132.6, 132.6, 188.3, 299.7", \ + "207.7, 207.7, 207.7, 263.4, 374.8", \ + "358.0, 358.0, 358.0, 413.6, 525.0", \ + "658.4, 658.4, 658.4, 714.1, 825.4"); + } + } + } + } + + cell (nd2av0x4) { + area : 0.0 ; + cell_leakage_power : 3 ; + leakage_power () { + when : "a" ; + value : 1.3 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 7.8 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 0.00032 ; + } + pin (b) { + direction : input ; + capacitance : 9.70 ; + } + pin (a) { + direction : input ; + capacitance : 5.09 ; + } + pin (z) { + function : "(a | !(b))" ; + direction : output ; + capacitance : 8.13 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__48) { + values ("57.0, 57.0, 57.0, 67.5, 87.0", \ + "62.9, 62.9, 62.9, 73.7, 93.9", \ + "66.9, 66.9, 66.9, 78.2, 99.2", \ + "66.9, 66.9, 66.9, 78.7, 101.0", \ + "60.1, 60.1, 60.1, 72.4, 96.0"); + } + rise_transition (inslew_load_5x5__48) { + values ("50.9, 50.9, 50.9, 68.4, 103.6", \ + "66.4, 66.4, 66.4, 84.0, 118.8", \ + "92.3, 92.3, 92.3, 110.0, 145.0", \ + "138.9, 138.9, 138.9, 156.7, 191.9", \ + "227.7, 227.7, 227.7, 245.6, 281.2"); + } + cell_fall (inslew_load_5x5__48) { + values ("56.7, 56.7, 56.7, 64.2, 77.8", \ + "64.1, 64.1, 64.1, 72.2, 86.9", \ + "73.6, 73.6, 73.6, 82.4, 98.8", \ + "88.1, 88.1, 88.1, 98.0, 115.6", \ + "113.7, 113.7, 113.7, 124.1, 144.2"); + } + fall_transition (inslew_load_5x5__48) { + values ("33.3, 33.3, 33.3, 40.7, 55.0", \ + "40.7, 40.7, 40.7, 48.3, 62.8", \ + "54.5, 54.5, 54.5, 62.4, 77.3", \ + "81.1, 81.1, 81.1, 89.3, 105.2", \ + "133.4, 133.4, 133.4, 141.9, 158.4"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__48) { + values ("25.8, 25.8, 25.8, 37.7, 58.8", \ + "38.1, 38.1, 38.1, 50.8, 74.1", \ + "59.6, 59.6, 59.6, 73.0, 98.2", \ + "100.9, 100.9, 100.9, 114.8, 141.5", \ + "182.4, 182.4, 182.4, 196.6, 224.2"); + } + rise_transition (inslew_load_5x5__48) { + values ("49.8, 49.8, 49.8, 67.7, 102.9", \ + "88.5, 88.5, 88.5, 106.7, 142.4", \ + "161.8, 161.8, 161.8, 180.2, 216.4", \ + "305.9, 305.9, 305.9, 324.4, 361.1", \ + "592.9, 592.9, 592.9, 611.5, 648.6"); + } + cell_fall (inslew_load_5x5__48) { + values ("7.5, 7.5, 7.5, 16.2, 30.5", \ + "1.7, 1.7, 1.7, 12.0, 29.2", \ + "-11.4, -11.4, -11.4, 0.2, 20.5", \ + "-38.9, -38.9, -38.9, -26.3, -3.1", \ + "-94.7, -94.7, -94.7, -81.4, -56.2"); + } + fall_transition (inslew_load_5x5__48) { + values ("19.8, 19.8, 19.8, 27.5, 42.1", \ + "31.4, 31.4, 31.4, 39.6, 55.1", \ + "53.8, 53.8, 53.8, 62.6, 79.1", \ + "98.2, 98.2, 98.2, 107.3, 124.8", \ + "186.7, 186.7, 186.7, 196.0, 214.2"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__48) { + values ("495.2, 495.2, 495.2, 596.8, 799.9", \ + "588.0, 588.0, 588.0, 689.6, 892.7", \ + "765.5, 765.5, 765.5, 867.1, 1070.2", \ + "1112.1, 1112.1, 1112.1, 1213.7, 1416.8", \ + "1799.2, 1799.2, 1799.2, 1900.7, 2103.9"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("539.6, 539.6, 539.6, 641.2, 844.3", \ + "654.5, 654.5, 654.5, 756.0, 959.2", \ + "879.8, 879.8, 879.8, 981.3, 1184.5", \ + "1327.5, 1327.5, 1327.5, 1429.1, 1632.3", \ + "2221.1, 2221.1, 2221.1, 2322.7, 2525.8"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__48) { + values ("252.1, 252.1, 252.1, 353.7, 556.9", \ + "406.2, 406.2, 406.2, 507.8, 710.9", \ + "714.3, 714.3, 714.3, 815.9, 1019.0", \ + "1330.6, 1330.6, 1330.6, 1432.2, 1635.3", \ + "2563.1, 2563.1, 2563.1, 2664.7, 2867.8"); + } + fall_power (energy_inslew_load_5x5__48) { + values ("178.1, 178.1, 178.1, 279.6, 482.8", \ + "251.1, 251.1, 251.1, 352.7, 555.8", \ + "397.1, 397.1, 397.1, 498.7, 701.8", \ + "689.2, 689.2, 689.2, 790.8, 993.9", \ + "1273.3, 1273.3, 1273.3, 1374.9, 1578.0"); + } + } + } + } + + cell (nd2v0x05) { + area : 0.0 ; + cell_leakage_power : 0.29 ; + leakage_power () { + when : "(b & a)" ; + value : 1.1 ; + } + leakage_power () { + when : "(!(b) & a)" ; + value : 6.5e-05 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 5.4e-05 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 1.2e-06 ; + } + pin (b) { + direction : input ; + capacitance : 2.66 ; + } + pin (a) { + direction : input ; + capacitance : 2.39 ; + } + pin (z) { + function : "(!(a) | !(b))" ; + direction : output ; + capacitance : 2.05 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__49) { + values ("42.5, 42.5, 42.5, 57.5, 85.6", \ + "60.6, 60.6, 60.6, 76.8, 107.0", \ + "92.6, 92.6, 92.6, 109.9, 142.7", \ + "154.0, 154.0, 154.0, 172.1, 207.0", \ + "275.3, 275.3, 275.3, 293.9, 330.3"); + } + rise_transition (inslew_load_5x5__49) { + values ("82.1, 82.1, 82.1, 110.1, 166.0", \ + "130.3, 130.3, 130.3, 158.6, 214.5", \ + "221.5, 221.5, 221.5, 250.1, 306.8", \ + "400.9, 400.9, 400.9, 429.7, 487.0", \ + "757.9, 757.9, 757.9, 786.9, 844.6"); + } + cell_fall (inslew_load_5x5__49) { + values ("15.3, 15.3, 15.3, 25.2, 43.2", \ + "8.0, 8.0, 8.0, 19.5, 40.0", \ + "-9.8, -9.8, -9.8, 3.6, 27.6", \ + "-48.7, -48.7, -48.7, -33.3, -5.4", \ + "-129.0, -129.0, -129.0, -112.2, -80.7"); + } + fall_transition (inslew_load_5x5__49) { + values ("31.7, 31.7, 31.7, 43.1, 65.7", \ + "42.6, 42.6, 42.6, 54.3, 77.1", \ + "63.4, 63.4, 63.4, 75.7, 99.3", \ + "104.0, 104.0, 104.0, 116.9, 141.7", \ + "184.1, 184.1, 184.1, 197.5, 223.5"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__49) { + values ("30.3, 30.3, 30.3, 46.4, 75.3", \ + "41.8, 41.8, 41.8, 59.4, 91.2", \ + "61.7, 61.7, 61.7, 80.6, 115.6", \ + "99.5, 99.5, 99.5, 119.4, 157.0", \ + "173.9, 173.9, 173.9, 194.4, 234.0"); + } + rise_transition (inslew_load_5x5__49) { + values ("60.9, 60.9, 60.9, 89.2, 144.8", \ + "99.8, 99.8, 99.8, 128.5, 184.9", \ + "173.4, 173.4, 173.4, 202.5, 259.8", \ + "318.3, 318.3, 318.3, 347.6, 405.7", \ + "606.8, 606.8, 606.8, 636.3, 694.9"); + } + cell_fall (inslew_load_5x5__49) { + values ("12.8, 12.8, 12.8, 24.6, 44.4", \ + "8.4, 8.4, 8.4, 22.4, 45.8", \ + "-2.7, -2.7, -2.7, 13.3, 41.1", \ + "-27.0, -27.0, -27.0, -9.2, 22.8", \ + "-76.8, -76.8, -76.8, -57.9, -22.4"); + } + fall_transition (inslew_load_5x5__49) { + values ("25.6, 25.6, 25.6, 37.5, 60.4", \ + "38.4, 38.4, 38.4, 51.0, 74.8", \ + "63.1, 63.1, 63.1, 76.4, 101.5", \ + "111.6, 111.6, 111.6, 125.5, 152.1", \ + "208.1, 208.1, 208.1, 222.3, 250.1"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__49) { + values ("71.6, 71.6, 71.6, 97.2, 148.5", \ + "104.8, 104.8, 104.8, 130.4, 181.7", \ + "171.1, 171.1, 171.1, 196.8, 248.0", \ + "303.9, 303.9, 303.9, 329.5, 380.8", \ + "569.4, 569.4, 569.4, 595.0, 646.2"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("56.2, 56.2, 56.2, 81.8, 133.1", \ + "68.2, 68.2, 68.2, 93.8, 145.0", \ + "92.1, 92.1, 92.1, 117.8, 169.0", \ + "140.1, 140.1, 140.1, 165.7, 217.0", \ + "236.0, 236.0, 236.0, 261.7, 312.9"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__49) { + values ("50.7, 50.7, 50.7, 76.3, 127.6", \ + "76.4, 76.4, 76.4, 102.0, 153.3", \ + "127.8, 127.8, 127.8, 153.5, 204.7", \ + "230.7, 230.7, 230.7, 256.4, 307.6", \ + "436.5, 436.5, 436.5, 462.2, 513.4"); + } + fall_power (energy_inslew_load_5x5__49) { + values ("39.9, 39.9, 39.9, 65.5, 116.7", \ + "53.4, 53.4, 53.4, 79.0, 130.3", \ + "80.5, 80.5, 80.5, 106.1, 157.4", \ + "134.7, 134.7, 134.7, 160.3, 211.6", \ + "243.1, 243.1, 243.1, 268.7, 319.9"); + } + } + } + } + + cell (nd2v0x1) { + area : 0.0 ; + cell_leakage_power : 0.66 ; + leakage_power () { + when : "(b & a)" ; + value : 2.6 ; + } + leakage_power () { + when : "(!(b) & a)" ; + value : 7e-05 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 5.6e-05 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 1.3e-06 ; + } + pin (b) { + direction : input ; + capacitance : 3.50 ; + } + pin (a) { + direction : input ; + capacitance : 3.50 ; + } + pin (z) { + function : "(!(b) | !(a))" ; + direction : output ; + capacitance : 3.37 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__50) { + values ("41.0, 41.0, 41.0, 55.3, 81.8", \ + "58.3, 58.3, 58.3, 73.7, 102.4", \ + "88.7, 88.7, 88.7, 105.2, 136.4", \ + "147.1, 147.1, 147.1, 164.3, 197.6", \ + "262.4, 262.4, 262.4, 280.1, 314.7"); + } + rise_transition (inslew_load_5x5__50) { + values ("77.4, 77.4, 77.4, 102.8, 153.7", \ + "123.9, 123.9, 123.9, 149.7, 200.5", \ + "211.7, 211.7, 211.7, 237.8, 289.3", \ + "384.6, 384.6, 384.6, 410.8, 463.0", \ + "728.7, 728.7, 728.7, 755.0, 807.6"); + } + cell_fall (inslew_load_5x5__50) { + values ("15.0, 15.0, 15.0, 24.2, 41.0", \ + "8.1, 8.1, 8.1, 19.0, 38.3", \ + "-8.8, -8.8, -8.8, 3.9, 26.7", \ + "-45.8, -45.8, -45.8, -31.2, -4.6", \ + "-122.2, -122.2, -122.2, -106.3, -76.3"); + } + fall_transition (inslew_load_5x5__50) { + values ("29.5, 29.5, 29.5, 39.8, 60.1", \ + "40.1, 40.1, 40.1, 50.7, 71.2", \ + "60.2, 60.2, 60.2, 71.4, 92.8", \ + "99.4, 99.4, 99.4, 111.1, 133.8", \ + "176.9, 176.9, 176.9, 189.1, 212.8"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__50) { + values ("29.1, 29.1, 29.1, 44.4, 71.8", \ + "40.2, 40.2, 40.2, 57.0, 87.2", \ + "59.4, 59.4, 59.4, 77.3, 110.6", \ + "95.6, 95.6, 95.6, 114.5, 150.3", \ + "167.1, 167.1, 167.1, 186.4, 224.0"); + } + rise_transition (inslew_load_5x5__50) { + values ("57.7, 57.7, 57.7, 83.4, 134.0", \ + "95.7, 95.7, 95.7, 121.9, 173.1", \ + "167.8, 167.8, 167.8, 194.3, 246.4", \ + "309.6, 309.6, 309.6, 336.4, 389.3", \ + "592.1, 592.1, 592.1, 619.0, 672.5"); + } + cell_fall (inslew_load_5x5__50) { + values ("12.0, 12.0, 12.0, 23.1, 41.8", \ + "7.7, 7.7, 7.7, 21.0, 43.1", \ + "-3.0, -3.0, -3.0, 12.2, 38.5", \ + "-26.3, -26.3, -26.3, -9.4, 20.9", \ + "-73.9, -73.9, -73.9, -56.0, -22.5"); + } + fall_transition (inslew_load_5x5__50) { + values ("23.6, 23.6, 23.6, 34.4, 55.0", \ + "36.0, 36.0, 36.0, 47.5, 69.0", \ + "59.8, 59.8, 59.8, 71.9, 94.7", \ + "106.6, 106.6, 106.6, 119.3, 143.5", \ + "199.8, 199.8, 199.8, 212.8, 238.1"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__50) { + values ("120.4, 120.4, 120.4, 162.5, 246.7", \ + "176.7, 176.7, 176.7, 218.8, 303.0", \ + "289.4, 289.4, 289.4, 331.5, 415.7", \ + "514.7, 514.7, 514.7, 556.8, 641.0", \ + "965.4, 965.4, 965.4, 1007.5, 1091.7"); + } + fall_power (energy_inslew_load_5x5__50) { + values ("94.4, 94.4, 94.4, 136.5, 220.7", \ + "114.7, 114.7, 114.7, 156.8, 241.0", \ + "155.3, 155.3, 155.3, 197.4, 281.6", \ + "236.4, 236.4, 236.4, 278.5, 362.7", \ + "398.7, 398.7, 398.7, 440.8, 525.0"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__50) { + values ("85.3, 85.3, 85.3, 127.4, 211.6", \ + "129.6, 129.6, 129.6, 171.7, 255.9", \ + "218.1, 218.1, 218.1, 260.2, 344.4", \ + "395.2, 395.2, 395.2, 437.3, 521.5", \ + "749.4, 749.4, 749.4, 791.5, 875.7"); + } + fall_power (energy_inslew_load_5x5__50) { + values ("66.3, 66.3, 66.3, 108.4, 192.6", \ + "89.3, 89.3, 89.3, 131.4, 215.6", \ + "135.5, 135.5, 135.5, 177.6, 261.8", \ + "227.9, 227.9, 227.9, 270.0, 354.2", \ + "412.5, 412.5, 412.5, 454.6, 538.8"); + } + } + } + } + + cell (nd2v0x2) { + area : 0.0 ; + cell_leakage_power : 0.72 ; + leakage_power () { + when : "(b & a)" ; + value : 2.9 ; + } + leakage_power () { + when : "(!(b) & a)" ; + value : 0.00011 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 9e-05 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 1.9e-06 ; + } + pin (b) { + direction : input ; + capacitance : 5.12 ; + } + pin (a) { + direction : input ; + capacitance : 5.39 ; + } + pin (z) { + function : "(!(b) | !(a))" ; + direction : output ; + capacitance : 4.33 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__51) { + values ("38.8, 38.8, 38.8, 50.3, 71.7", \ + "57.1, 57.1, 57.1, 69.4, 92.5", \ + "89.5, 89.5, 89.5, 102.5, 127.4", \ + "151.9, 151.9, 151.9, 165.4, 191.7", \ + "275.2, 275.2, 275.2, 289.1, 316.3"); + } + rise_transition (inslew_load_5x5__51) { + values ("69.5, 69.5, 69.5, 88.3, 125.5", \ + "116.0, 116.0, 116.0, 135.0, 172.5", \ + "203.6, 203.6, 203.6, 222.8, 260.8", \ + "375.8, 375.8, 375.8, 395.2, 433.6", \ + "718.8, 718.8, 718.8, 738.2, 777.0"); + } + cell_fall (inslew_load_5x5__51) { + values ("11.9, 11.9, 11.9, 19.1, 32.2", \ + "4.0, 4.0, 4.0, 12.6, 27.9", \ + "-14.7, -14.7, -14.7, -4.5, 13.6", \ + "-54.9, -54.9, -54.9, -43.3, -22.1", \ + "-137.2, -137.2, -137.2, -124.7, -100.9"); + } + fall_transition (inslew_load_5x5__51) { + values ("26.2, 26.2, 26.2, 33.8, 48.8", \ + "36.2, 36.2, 36.2, 44.2, 59.6", \ + "55.4, 55.4, 55.4, 63.9, 80.1", \ + "92.9, 92.9, 92.9, 101.8, 119.0", \ + "167.0, 167.0, 167.0, 176.3, 194.3"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__51) { + values ("26.6, 26.6, 26.6, 39.2, 61.5", \ + "39.0, 39.0, 39.0, 52.4, 77.0", \ + "60.5, 60.5, 60.5, 74.8, 101.4", \ + "101.8, 101.8, 101.8, 116.6, 144.9", \ + "183.4, 183.4, 183.4, 198.4, 227.8"); + } + rise_transition (inslew_load_5x5__51) { + values ("51.0, 51.0, 51.0, 70.1, 107.5", \ + "89.7, 89.7, 89.7, 109.1, 147.0", \ + "163.0, 163.0, 163.0, 182.6, 221.2", \ + "307.1, 307.1, 307.1, 326.8, 366.0", \ + "594.2, 594.2, 594.2, 614.0, 653.4"); + } + cell_fall (inslew_load_5x5__51) { + values ("8.2, 8.2, 8.2, 17.3, 32.3", \ + "2.5, 2.5, 2.5, 13.2, 31.3", \ + "-10.6, -10.6, -10.6, 1.6, 23.0", \ + "-38.1, -38.1, -38.1, -24.7, -0.3", \ + "-93.8, -93.8, -93.8, -79.7, -53.0"); + } + fall_transition (inslew_load_5x5__51) { + values ("20.3, 20.3, 20.3, 28.5, 43.9", \ + "31.9, 31.9, 31.9, 40.7, 57.0", \ + "54.4, 54.4, 54.4, 63.7, 81.2", \ + "98.8, 98.8, 98.8, 108.5, 127.1", \ + "187.3, 187.3, 187.3, 197.2, 216.5"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__51) { + values ("186.5, 186.5, 186.5, 240.7, 348.9", \ + "282.7, 282.7, 282.7, 336.8, 445.1", \ + "475.0, 475.0, 475.0, 529.1, 637.4", \ + "859.6, 859.6, 859.6, 913.7, 1022.0", \ + "1628.9, 1628.9, 1628.9, 1683.0, 1791.3"); + } + fall_power (energy_inslew_load_5x5__51) { + values ("140.1, 140.1, 140.1, 194.2, 302.5", \ + "172.5, 172.5, 172.5, 226.6, 334.9", \ + "237.2, 237.2, 237.2, 291.3, 399.6", \ + "366.7, 366.7, 366.7, 420.9, 529.1", \ + "625.7, 625.7, 625.7, 679.9, 788.2"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__51) { + values ("129.4, 129.4, 129.4, 183.6, 291.8", \ + "206.5, 206.5, 206.5, 260.6, 368.9", \ + "360.5, 360.5, 360.5, 414.7, 522.9", \ + "668.6, 668.6, 668.6, 722.8, 831.0", \ + "1284.9, 1284.9, 1284.9, 1339.0, 1447.3"); + } + fall_power (energy_inslew_load_5x5__51) { + values ("92.4, 92.4, 92.4, 146.5, 254.8", \ + "128.9, 128.9, 128.9, 183.0, 291.3", \ + "201.9, 201.9, 201.9, 256.0, 364.3", \ + "347.9, 347.9, 347.9, 402.1, 510.4", \ + "640.0, 640.0, 640.0, 694.2, 802.4"); + } + } + } + } + + cell (nd2v0x4) { + area : 0.0 ; + cell_leakage_power : 2 ; + leakage_power () { + when : "(b & a)" ; + value : 7.8 ; + } + leakage_power () { + when : "(!(b) & a)" ; + value : 0.00022 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 0.00018 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 3.8e-06 ; + } + pin (b) { + direction : input ; + capacitance : 9.73 ; + } + pin (a) { + direction : input ; + capacitance : 10.34 ; + } + pin (z) { + function : "(!(b) | !(a))" ; + direction : output ; + capacitance : 8.04 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__52) { + values ("37.0, 37.0, 37.0, 47.7, 67.6", \ + "55.2, 55.2, 55.2, 66.7, 88.2", \ + "87.5, 87.5, 87.5, 99.6, 122.7", \ + "149.5, 149.5, 149.5, 162.0, 186.5", \ + "272.1, 272.1, 272.1, 284.9, 310.1"); + } + rise_transition (inslew_load_5x5__52) { + values ("63.9, 63.9, 63.9, 80.8, 114.2", \ + "109.0, 109.0, 109.0, 126.1, 159.8", \ + "193.7, 193.7, 193.7, 210.9, 245.1", \ + "360.0, 360.0, 360.0, 377.4, 412.0", \ + "691.0, 691.0, 691.0, 708.4, 743.3"); + } + cell_fall (inslew_load_5x5__52) { + values ("11.6, 11.6, 11.6, 18.4, 30.8", \ + "3.6, 3.6, 3.6, 11.7, 26.2", \ + "-15.1, -15.1, -15.1, -5.6, 11.5", \ + "-55.3, -55.3, -55.3, -44.5, -24.5", \ + "-137.4, -137.4, -137.4, -125.7, -103.5"); + } + fall_transition (inslew_load_5x5__52) { + values ("25.7, 25.7, 25.7, 32.8, 46.7", \ + "35.7, 35.7, 35.7, 43.2, 57.5", \ + "55.0, 55.0, 55.0, 62.9, 78.0", \ + "92.5, 92.5, 92.5, 100.8, 116.8", \ + "166.7, 166.7, 166.7, 175.4, 192.2"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__52) { + values ("24.9, 24.9, 24.9, 36.7, 57.6", \ + "37.2, 37.2, 37.2, 49.8, 72.8", \ + "58.5, 58.5, 58.5, 71.8, 96.7", \ + "99.2, 99.2, 99.2, 113.0, 139.4", \ + "179.6, 179.6, 179.6, 193.6, 221.0"); + } + rise_transition (inslew_load_5x5__52) { + values ("46.3, 46.3, 46.3, 63.6, 97.2", \ + "83.8, 83.8, 83.8, 101.3, 135.4", \ + "154.4, 154.4, 154.4, 172.1, 206.8", \ + "293.2, 293.2, 293.2, 311.0, 346.2", \ + "569.5, 569.5, 569.5, 587.3, 622.8"); + } + cell_fall (inslew_load_5x5__52) { + values ("7.7, 7.7, 7.7, 16.4, 30.6", \ + "2.0, 2.0, 2.0, 12.2, 29.3", \ + "-11.0, -11.0, -11.0, 0.5, 20.6", \ + "-38.2, -38.2, -38.2, -25.7, -2.8", \ + "-93.4, -93.4, -93.4, -80.3, -55.4"); + } + fall_transition (inslew_load_5x5__52) { + values ("19.6, 19.6, 19.6, 27.3, 41.8", \ + "31.4, 31.4, 31.4, 39.5, 54.8", \ + "53.9, 53.9, 53.9, 62.6, 78.9", \ + "98.6, 98.6, 98.6, 107.6, 124.8", \ + "187.4, 187.4, 187.4, 196.6, 214.6"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__52) { + values ("361.9, 361.9, 361.9, 462.4, 663.5", \ + "551.1, 551.1, 551.1, 651.6, 852.7", \ + "929.5, 929.5, 929.5, 1030.0, 1231.1", \ + "1686.3, 1686.3, 1686.3, 1786.9, 1987.9", \ + "3200.0, 3200.0, 3200.0, 3300.5, 3501.6"); + } + fall_power (energy_inslew_load_5x5__52) { + values ("272.7, 272.7, 272.7, 373.2, 574.3", \ + "337.7, 337.7, 337.7, 438.3, 639.4", \ + "467.8, 467.8, 467.8, 568.3, 769.4", \ + "727.9, 727.9, 727.9, 828.4, 1029.5", \ + "1248.1, 1248.1, 1248.1, 1348.6, 1549.7"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__52) { + values ("247.6, 247.6, 247.6, 348.2, 549.3", \ + "398.2, 398.2, 398.2, 498.7, 699.8", \ + "699.4, 699.4, 699.4, 799.9, 1001.0", \ + "1301.7, 1301.7, 1301.7, 1402.2, 1603.3", \ + "2506.3, 2506.3, 2506.3, 2606.8, 2807.9"); + } + fall_power (energy_inslew_load_5x5__52) { + values ("177.6, 177.6, 177.6, 278.1, 479.2", \ + "251.2, 251.2, 251.2, 351.7, 552.8", \ + "398.3, 398.3, 398.3, 498.9, 699.9", \ + "692.6, 692.6, 692.6, 793.1, 994.2", \ + "1281.2, 1281.2, 1281.2, 1381.7, 1582.8"); + } + } + } + } + + cell (nd2v3x05) { + area : 0.0 ; + cell_leakage_power : 2.3 ; + leakage_power () { + when : "(b & a)" ; + value : 9.3 ; + } + leakage_power () { + when : "(!(b) & a)" ; + value : 8.6e-05 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 6.9e-05 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 1.5e-06 ; + } + pin (b) { + direction : input ; + capacitance : 3.61 ; + } + pin (a) { + direction : input ; + capacitance : 3.54 ; + } + pin (z) { + function : "(!(b) | !(a))" ; + direction : output ; + capacitance : 2.99 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__53) { + values ("56.5, 56.5, 56.5, 73.2, 104.9", \ + "90.7, 90.7, 90.7, 108.1, 141.3", \ + "149.3, 149.3, 149.3, 167.4, 202.3", \ + "260.6, 260.6, 260.6, 279.3, 315.8", \ + "480.0, 480.0, 480.0, 499.0, 536.5"); + } + rise_transition (inslew_load_5x5__53) { + values ("104.7, 104.7, 104.7, 137.8, 204.1", \ + "182.6, 182.6, 182.6, 215.9, 281.9", \ + "320.7, 320.7, 320.7, 354.1, 420.6", \ + "587.1, 587.1, 587.1, 620.7, 687.6", \ + "1114.6, 1114.6, 1114.6, 1148.3, 1215.6"); + } + cell_fall (inslew_load_5x5__53) { + values ("6.9, 6.9, 6.9, 13.4, 25.0", \ + "-5.3, -5.3, -5.3, 2.6, 16.7", \ + "-34.4, -34.4, -34.4, -24.2, -6.5", \ + "-97.3, -97.3, -97.3, -84.8, -62.7", \ + "-227.6, -227.6, -227.6, -213.0, -186.5"); + } + fall_transition (inslew_load_5x5__53) { + values ("22.3, 22.3, 22.3, 29.0, 41.9", \ + "28.9, 28.9, 28.9, 36.1, 49.6", \ + "40.7, 40.7, 40.7, 48.6, 63.3", \ + "62.6, 62.6, 62.6, 71.3, 87.7", \ + "104.6, 104.6, 104.6, 114.2, 132.2"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__53) { + values ("37.6, 37.6, 37.6, 55.7, 88.4", \ + "65.4, 65.4, 65.4, 84.1, 118.7", \ + "112.6, 112.6, 112.6, 132.0, 168.7", \ + "202.3, 202.3, 202.3, 222.2, 260.6", \ + "379.1, 379.1, 379.1, 399.3, 438.8"); + } + rise_transition (inslew_load_5x5__53) { + values ("69.6, 69.6, 69.6, 103.2, 169.8", \ + "136.7, 136.7, 136.7, 170.4, 236.8", \ + "255.7, 255.7, 255.7, 289.6, 356.6", \ + "485.5, 485.5, 485.5, 519.5, 587.0", \ + "940.6, 940.6, 940.6, 974.7, 1042.6"); + } + cell_fall (inslew_load_5x5__53) { + values ("1.6, 1.6, 1.6, 10.3, 24.2", \ + "-10.4, -10.4, -10.4, 0.5, 18.0", \ + "-37.1, -37.1, -37.1, -23.7, -1.7", \ + "-92.5, -92.5, -92.5, -77.0, -50.2", \ + "-204.9, -204.9, -204.9, -187.8, -156.8"); + } + fall_transition (inslew_load_5x5__53) { + values ("15.7, 15.7, 15.7, 23.1, 36.7", \ + "22.9, 22.9, 22.9, 31.1, 45.9", \ + "36.3, 36.3, 36.3, 45.5, 61.9", \ + "62.3, 62.3, 62.3, 72.3, 90.6", \ + "113.8, 113.8, 113.8, 124.4, 144.2"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__53) { + values ("135.1, 135.1, 135.1, 172.5, 247.2", \ + "198.4, 198.4, 198.4, 235.8, 310.5", \ + "325.0, 325.0, 325.0, 362.4, 437.1", \ + "578.2, 578.2, 578.2, 615.5, 690.3", \ + "1084.5, 1084.5, 1084.5, 1121.9, 1196.7"); + } + fall_power (energy_inslew_load_5x5__53) { + values ("91.0, 91.0, 91.0, 128.4, 203.2", \ + "101.2, 101.2, 101.2, 138.6, 213.4", \ + "121.7, 121.7, 121.7, 159.0, 233.8", \ + "162.5, 162.5, 162.5, 199.9, 274.6", \ + "244.2, 244.2, 244.2, 281.6, 356.3"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__53) { + values ("90.7, 90.7, 90.7, 128.0, 202.8", \ + "144.1, 144.1, 144.1, 181.4, 256.2", \ + "250.8, 250.8, 250.8, 288.2, 363.0", \ + "464.4, 464.4, 464.4, 501.8, 576.5", \ + "891.5, 891.5, 891.5, 928.9, 1003.7"); + } + fall_power (energy_inslew_load_5x5__53) { + values ("49.7, 49.7, 49.7, 87.1, 161.8", \ + "61.9, 61.9, 61.9, 99.2, 174.0", \ + "86.2, 86.2, 86.2, 123.6, 198.4", \ + "135.0, 135.0, 135.0, 172.4, 247.1", \ + "232.5, 232.5, 232.5, 269.9, 344.6"); + } + } + } + } + + cell (nd2v5x05) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "(b & a)" ; + value : 9.7 ; + } + leakage_power () { + when : "(!(b) & a)" ; + value : 6.2e-05 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 5.1e-05 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 1.1e-06 ; + } + pin (b) { + direction : input ; + capacitance : 2.88 ; + } + pin (a) { + direction : input ; + capacitance : 2.82 ; + } + pin (z) { + function : "(!(a) | !(b))" ; + direction : output ; + capacitance : 2.33 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__54) { + values ("33.1, 33.1, 33.1, 45.2, 67.5", \ + "45.1, 45.1, 45.1, 58.4, 82.9", \ + "66.0, 66.0, 66.0, 80.3, 107.2", \ + "106.0, 106.0, 106.0, 121.0, 149.8", \ + "184.7, 184.7, 184.7, 200.1, 230.3"); + } + rise_transition (inslew_load_5x5__54) { + values ("66.7, 66.7, 66.7, 88.0, 130.1", \ + "106.3, 106.3, 106.3, 128.0, 170.7", \ + "182.2, 182.2, 182.2, 204.1, 247.5", \ + "331.9, 331.9, 331.9, 354.1, 398.1", \ + "630.3, 630.3, 630.3, 652.6, 697.0"); + } + cell_fall (inslew_load_5x5__54) { + values ("18.0, 18.0, 18.0, 27.7, 45.5", \ + "13.8, 13.8, 13.8, 24.8, 44.8", \ + "2.8, 2.8, 2.8, 15.4, 38.1", \ + "-21.3, -21.3, -21.3, -7.5, 18.1", \ + "-71.2, -71.2, -71.2, -56.5, -28.4"); + } + fall_transition (inslew_load_5x5__54) { + values ("34.0, 34.0, 34.0, 45.3, 67.9", \ + "47.5, 47.5, 47.5, 59.1, 81.8", \ + "73.8, 73.8, 73.8, 85.7, 109.0", \ + "125.4, 125.4, 125.4, 137.8, 161.8", \ + "228.2, 228.2, 228.2, 240.8, 265.6"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__54) { + values ("22.6, 22.6, 22.6, 35.8, 59.0", \ + "28.4, 28.4, 28.4, 43.1, 69.1", \ + "37.7, 37.7, 37.7, 53.6, 82.7", \ + "54.9, 54.9, 54.9, 71.7, 103.3", \ + "88.5, 88.5, 88.5, 105.7, 139.1"); + } + rise_transition (inslew_load_5x5__54) { + values ("49.7, 49.7, 49.7, 71.4, 113.7", \ + "81.1, 81.1, 81.1, 103.2, 146.4", \ + "141.4, 141.4, 141.4, 163.8, 207.9", \ + "260.4, 260.4, 260.4, 283.1, 328.0", \ + "497.6, 497.6, 497.6, 520.5, 565.9"); + } + cell_fall (inslew_load_5x5__54) { + values ("15.7, 15.7, 15.7, 27.1, 46.6", \ + "15.2, 15.2, 15.2, 28.4, 51.0", \ + "12.3, 12.3, 12.3, 26.9, 53.0", \ + "4.8, 4.8, 4.8, 20.7, 49.9", \ + "-10.7, -10.7, -10.7, 5.7, 37.2"); + } + fall_transition (inslew_load_5x5__54) { + values ("27.6, 27.6, 27.6, 39.4, 62.3", \ + "43.6, 43.6, 43.6, 55.9, 79.5", \ + "74.5, 74.5, 74.5, 87.2, 111.8", \ + "135.3, 135.3, 135.3, 148.5, 174.0", \ + "256.6, 256.6, 256.6, 270.0, 296.3"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__54) { + values ("82.0, 82.0, 82.0, 111.1, 169.3", \ + "121.2, 121.2, 121.2, 150.3, 208.5", \ + "199.6, 199.6, 199.6, 228.7, 286.9", \ + "356.4, 356.4, 356.4, 385.5, 443.7", \ + "670.0, 670.0, 670.0, 699.1, 757.3"); + } + fall_power (energy_inslew_load_5x5__54) { + values ("70.5, 70.5, 70.5, 99.6, 157.7", \ + "90.3, 90.3, 90.3, 119.4, 177.5", \ + "129.8, 129.8, 129.8, 158.9, 217.1", \ + "209.0, 209.0, 209.0, 238.1, 296.3", \ + "367.3, 367.3, 367.3, 396.4, 454.6"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__54) { + values ("57.4, 57.4, 57.4, 86.5, 144.7", \ + "86.8, 86.8, 86.8, 115.9, 174.1", \ + "145.7, 145.7, 145.7, 174.8, 233.0", \ + "263.5, 263.5, 263.5, 292.6, 350.7", \ + "499.0, 499.0, 499.0, 528.1, 586.3"); + } + fall_power (energy_inslew_load_5x5__54) { + values ("52.0, 52.0, 52.0, 81.1, 139.3", \ + "73.8, 73.8, 73.8, 102.9, 161.1", \ + "117.4, 117.4, 117.4, 146.5, 204.6", \ + "204.5, 204.5, 204.5, 233.6, 291.8", \ + "378.8, 378.8, 378.8, 407.9, 466.1"); + } + } + } + } + + cell (nd3abv0x05) { + area : 0.0 ; + cell_leakage_power : 0.55 ; + leakage_power () { + when : "(a & !(b))" ; + value : 0.32 ; + } + leakage_power () { + when : "b" ; + value : 0.72 ; + } + leakage_power () { + when : "(c & !(b) & !(a))" ; + value : 1.1 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 0.00013 ; + } + pin (c) { + direction : input ; + capacitance : 2.47 ; + } + pin (b) { + direction : input ; + capacitance : 3.55 ; + } + pin (a) { + direction : input ; + capacitance : 3.29 ; + } + pin (z) { + function : "(!(c) | a | b)" ; + direction : output ; + capacitance : 2.50 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__55) { + values ("73.1, 73.1, 73.1, 90.6, 123.6", \ + "86.5, 86.5, 86.5, 104.8, 138.9", \ + "106.3, 106.3, 106.3, 125.6, 161.5", \ + "139.3, 139.3, 139.3, 159.7, 198.0", \ + "200.1, 200.1, 200.1, 221.6, 262.5"); + } + rise_transition (inslew_load_5x5__55) { + values ("76.4, 76.4, 76.4, 110.2, 178.1", \ + "96.9, 96.9, 96.9, 130.9, 198.9", \ + "132.5, 132.5, 132.5, 166.8, 234.6", \ + "199.2, 199.2, 199.2, 233.8, 302.3", \ + "329.0, 329.0, 329.0, 363.9, 433.2"); + } + cell_fall (inslew_load_5x5__55) { + values ("69.7, 69.7, 69.7, 83.7, 108.7", \ + "68.3, 68.3, 68.3, 83.3, 109.6", \ + "63.8, 63.8, 63.8, 79.8, 108.4", \ + "52.3, 52.3, 52.3, 69.8, 101.4", \ + "25.7, 25.7, 25.7, 44.9, 80.2"); + } + fall_transition (inslew_load_5x5__55) { + values ("50.9, 50.9, 50.9, 65.2, 92.9", \ + "58.5, 58.5, 58.5, 73.0, 101.0", \ + "73.2, 73.2, 73.2, 88.1, 116.7", \ + "102.0, 102.0, 102.0, 117.3, 146.8", \ + "159.2, 159.2, 159.2, 175.0, 205.5"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__55) { + values ("59.7, 59.7, 59.7, 76.9, 109.5", \ + "64.1, 64.1, 64.1, 81.9, 115.2", \ + "65.2, 65.2, 65.2, 83.8, 118.5", \ + "60.3, 60.3, 60.3, 80.1, 116.9", \ + "44.0, 44.0, 44.0, 64.9, 104.4"); + } + rise_transition (inslew_load_5x5__55) { + values ("66.7, 66.7, 66.7, 100.8, 168.6", \ + "82.6, 82.6, 82.6, 116.5, 184.3", \ + "108.9, 108.9, 108.9, 143.0, 211.5", \ + "156.1, 156.1, 156.1, 190.5, 258.6", \ + "246.1, 246.1, 246.1, 280.9, 349.8"); + } + cell_fall (inslew_load_5x5__55) { + values ("61.9, 61.9, 61.9, 75.0, 98.4", \ + "69.6, 69.6, 69.6, 83.9, 109.2", \ + "80.1, 80.1, 80.1, 95.9, 124.1", \ + "96.4, 96.4, 96.4, 114.0, 145.7", \ + "124.8, 124.8, 124.8, 144.1, 179.8"); + } + fall_transition (inslew_load_5x5__55) { + values ("43.3, 43.3, 43.3, 57.4, 84.9", \ + "52.5, 52.5, 52.5, 66.9, 94.6", \ + "69.7, 69.7, 69.7, 84.5, 112.9", \ + "102.8, 102.8, 102.8, 118.1, 147.7", \ + "168.0, 168.0, 168.0, 183.7, 214.4"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__55) { + values ("34.0, 34.0, 34.0, 53.0, 87.3", \ + "45.8, 45.8, 45.8, 66.7, 104.3", \ + "66.0, 66.0, 66.0, 88.6, 130.0", \ + "103.9, 103.9, 103.9, 127.8, 172.9", \ + "178.5, 178.5, 178.5, 203.2, 250.9"); + } + rise_transition (inslew_load_5x5__55) { + values ("67.1, 67.1, 67.1, 101.5, 169.5", \ + "106.1, 106.1, 106.1, 140.9, 209.3", \ + "179.8, 179.8, 179.8, 215.1, 284.6", \ + "324.7, 324.7, 324.7, 360.4, 430.9", \ + "613.3, 613.3, 613.3, 649.2, 720.4"); + } + cell_fall (inslew_load_5x5__55) { + values ("15.6, 15.6, 15.6, 29.2, 52.4", \ + "11.7, 11.7, 11.7, 27.9, 55.1", \ + "0.9, 0.9, 0.9, 19.8, 52.2", \ + "-23.0, -23.0, -23.0, -1.8, 35.8", \ + "-72.6, -72.6, -72.6, -49.9, -7.6"); + } + fall_transition (inslew_load_5x5__55) { + values ("28.2, 28.2, 28.2, 42.6, 70.4", \ + "41.3, 41.3, 41.3, 56.4, 85.0", \ + "66.1, 66.1, 66.1, 82.1, 112.2", \ + "114.7, 114.7, 114.7, 131.5, 163.4", \ + "211.2, 211.2, 211.2, 228.5, 262.0"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__55) { + values ("165.4, 165.4, 165.4, 196.7, 259.2", \ + "206.9, 206.9, 206.9, 238.1, 300.6", \ + "288.4, 288.4, 288.4, 319.7, 382.2", \ + "450.5, 450.5, 450.5, 481.8, 544.3", \ + "774.0, 774.0, 774.0, 805.2, 867.7"); + } + fall_power (energy_inslew_load_5x5__55) { + values ("192.7, 192.7, 192.7, 224.0, 286.5", \ + "229.4, 229.4, 229.4, 260.6, 323.1", \ + "302.3, 302.3, 302.3, 333.6, 396.1", \ + "447.9, 447.9, 447.9, 479.1, 541.6", \ + "739.2, 739.2, 739.2, 770.4, 832.9"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__55) { + values ("131.4, 131.4, 131.4, 162.7, 225.2", \ + "156.0, 156.0, 156.0, 187.2, 249.7", \ + "203.6, 203.6, 203.6, 234.8, 297.3", \ + "297.6, 297.6, 297.6, 328.9, 391.4", \ + "484.9, 484.9, 484.9, 516.1, 578.6"); + } + fall_power (energy_inslew_load_5x5__55) { + values ("151.5, 151.5, 151.5, 182.7, 245.2", \ + "190.1, 190.1, 190.1, 221.4, 283.9", \ + "266.5, 266.5, 266.5, 297.8, 360.3", \ + "418.7, 418.7, 418.7, 449.9, 512.4", \ + "722.4, 722.4, 722.4, 753.7, 816.1"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__55) { + values ("56.3, 56.3, 56.3, 87.5, 150.0", \ + "82.0, 82.0, 82.0, 113.3, 175.8", \ + "133.5, 133.5, 133.5, 164.7, 227.2", \ + "236.4, 236.4, 236.4, 267.6, 330.1", \ + "442.2, 442.2, 442.2, 473.4, 535.9"); + } + fall_power (energy_inslew_load_5x5__55) { + values ("45.5, 45.5, 45.5, 76.7, 139.2", \ + "59.0, 59.0, 59.0, 90.3, 152.8", \ + "86.1, 86.1, 86.1, 117.4, 179.9", \ + "140.3, 140.3, 140.3, 171.5, 234.0", \ + "248.7, 248.7, 248.7, 279.9, 342.4"); + } + } + } + } + + cell (nd3av0x05) { + area : 0.0 ; + cell_leakage_power : 3.8 ; + leakage_power () { + when : "a" ; + value : 4.9 ; + } + leakage_power () { + when : "(c & b & !(a))" ; + value : 14 ; + } + leakage_power () { + when : "(!(c) & b & !(a))" ; + value : 8.1e-05 ; + } + leakage_power () { + when : "(c & !(b) & !(a))" ; + value : 7.2e-05 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 3.5e-05 ; + } + pin (c) { + direction : input ; + capacitance : 2.97 ; + } + pin (b) { + direction : input ; + capacitance : 3.32 ; + } + pin (a) { + direction : input ; + capacitance : 2.81 ; + } + pin (z) { + function : "(a | !(c) | !(b))" ; + direction : output ; + capacitance : 3.83 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__56) { + values ("74.7, 74.7, 74.7, 94.9, 134.2", \ + "84.9, 84.9, 84.9, 105.8, 145.9", \ + "98.1, 98.1, 98.1, 120.0, 161.5", \ + "117.2, 117.2, 117.2, 140.5, 184.5", \ + "149.4, 149.4, 149.4, 174.2, 221.2"); + } + rise_transition (inslew_load_5x5__56) { + values ("94.2, 94.2, 94.2, 136.6, 222.1", \ + "114.9, 114.9, 114.9, 157.7, 242.0", \ + "149.8, 149.8, 149.8, 192.2, 277.4", \ + "213.6, 213.6, 213.6, 256.4, 341.1", \ + "336.3, 336.3, 336.3, 379.6, 465.3"); + } + cell_fall (inslew_load_5x5__56) { + values ("59.5, 59.5, 59.5, 74.0, 101.8", \ + "62.2, 62.2, 62.2, 77.5, 106.3", \ + "63.2, 63.2, 63.2, 79.8, 110.5", \ + "60.3, 60.3, 60.3, 78.8, 112.7", \ + "49.7, 49.7, 49.7, 70.5, 108.4"); + } + fall_transition (inslew_load_5x5__56) { + values ("56.5, 56.5, 56.5, 76.9, 117.7", \ + "62.8, 62.8, 62.8, 83.1, 123.7", \ + "74.8, 74.8, 74.8, 95.3, 135.7", \ + "98.0, 98.0, 98.0, 118.9, 159.8", \ + "143.3, 143.3, 143.3, 164.8, 206.9"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__56) { + values ("48.7, 48.7, 48.7, 70.3, 110.7", \ + "64.2, 64.2, 64.2, 87.7, 131.2", \ + "90.0, 90.0, 90.0, 115.7, 163.3", \ + "137.8, 137.8, 137.8, 165.3, 217.2", \ + "231.0, 231.0, 231.0, 259.6, 314.9"); + } + rise_transition (inslew_load_5x5__56) { + values ("94.6, 94.6, 94.6, 137.0, 221.8", \ + "138.8, 138.8, 138.8, 181.7, 266.5", \ + "221.4, 221.4, 221.4, 265.0, 351.1", \ + "383.3, 383.3, 383.3, 427.5, 514.8", \ + "705.2, 705.2, 705.2, 749.7, 838.1"); + } + cell_fall (inslew_load_5x5__56) { + values ("25.9, 25.9, 25.9, 41.1, 69.3", \ + "22.2, 22.2, 22.2, 39.5, 70.5", \ + "10.5, 10.5, 10.5, 30.7, 66.5", \ + "-17.4, -17.4, -17.4, 5.8, 47.6", \ + "-77.1, -77.1, -77.1, -51.3, -3.7"); + } + fall_transition (inslew_load_5x5__56) { + values ("44.8, 44.8, 44.8, 65.3, 106.2", \ + "57.1, 57.1, 57.1, 77.9, 118.6", \ + "80.6, 80.6, 80.6, 102.0, 143.6", \ + "126.2, 126.2, 126.2, 148.4, 191.5", \ + "216.2, 216.2, 216.2, 239.1, 283.8"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__56) { + values ("36.9, 36.9, 36.9, 59.5, 100.6", \ + "47.4, 47.4, 47.4, 72.5, 117.3", \ + "64.2, 64.2, 64.2, 91.8, 141.6", \ + "94.7, 94.7, 94.7, 124.3, 179.3", \ + "154.0, 154.0, 154.0, 184.9, 244.0"); + } + rise_transition (inslew_load_5x5__56) { + values ("72.9, 72.9, 72.9, 115.6, 200.4", \ + "110.2, 110.2, 110.2, 153.7, 238.8", \ + "180.3, 180.3, 180.3, 224.5, 311.2", \ + "317.6, 317.6, 317.6, 362.3, 450.6", \ + "590.6, 590.6, 590.6, 635.8, 725.2"); + } + cell_fall (inslew_load_5x5__56) { + values ("21.3, 21.3, 21.3, 37.9, 67.5", \ + "19.8, 19.8, 19.8, 39.6, 73.1", \ + "13.0, 13.0, 13.0, 36.2, 75.8", \ + "-3.9, -3.9, -3.9, 22.2, 68.5", \ + "-40.3, -40.3, -40.3, -11.9, 40.4"); + } + fall_transition (inslew_load_5x5__56) { + values ("35.8, 35.8, 35.8, 56.3, 97.9", \ + "49.7, 49.7, 49.7, 71.2, 112.6", \ + "76.1, 76.1, 76.1, 98.5, 141.5", \ + "127.5, 127.5, 127.5, 150.8, 195.7", \ + "229.5, 229.5, 229.5, 253.5, 300.1"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__56) { + values ("186.0, 186.0, 186.0, 233.9, 329.7", \ + "223.0, 223.0, 223.0, 270.9, 366.6", \ + "295.5, 295.5, 295.5, 343.3, 439.1", \ + "439.1, 439.1, 439.1, 487.0, 582.7", \ + "725.6, 725.6, 725.6, 773.4, 869.2"); + } + fall_power (energy_inslew_load_5x5__56) { + values ("194.6, 194.6, 194.6, 242.4, 338.2", \ + "232.1, 232.1, 232.1, 279.9, 375.7", \ + "306.4, 306.4, 306.4, 354.3, 450.0", \ + "454.6, 454.6, 454.6, 502.5, 598.2", \ + "750.8, 750.8, 750.8, 798.6, 894.4"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__56) { + values ("101.5, 101.5, 101.5, 149.4, 245.1", \ + "137.0, 137.0, 137.0, 184.9, 280.6", \ + "208.0, 208.0, 208.0, 255.9, 351.6", \ + "350.0, 350.0, 350.0, 397.9, 493.6", \ + "634.0, 634.0, 634.0, 681.9, 777.6"); + } + fall_power (energy_inslew_load_5x5__56) { + values ("89.1, 89.1, 89.1, 137.0, 232.7", \ + "105.0, 105.0, 105.0, 152.9, 248.6", \ + "136.8, 136.8, 136.8, 184.6, 280.4", \ + "200.3, 200.3, 200.3, 248.2, 344.0", \ + "327.5, 327.5, 327.5, 375.4, 471.1"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__56) { + values ("75.5, 75.5, 75.5, 123.3, 219.1", \ + "104.5, 104.5, 104.5, 152.4, 248.1", \ + "162.7, 162.7, 162.7, 210.5, 306.3", \ + "278.9, 278.9, 278.9, 326.8, 422.5", \ + "511.4, 511.4, 511.4, 559.3, 655.0"); + } + fall_power (energy_inslew_load_5x5__56) { + values ("66.6, 66.6, 66.6, 114.5, 210.2", \ + "83.9, 83.9, 83.9, 131.8, 227.5", \ + "118.4, 118.4, 118.4, 166.3, 262.1", \ + "187.6, 187.6, 187.6, 235.4, 331.2", \ + "325.8, 325.8, 325.8, 373.6, 469.4"); + } + } + } + } + + cell (nd3v0x05) { + area : 0.0 ; + cell_leakage_power : 2 ; + leakage_power () { + when : "(c & b & a)" ; + value : 14 ; + } + leakage_power () { + when : "(!(c) & b & a)" ; + value : 4.7e-05 ; + } + leakage_power () { + when : "(c & !(b) & a)" ; + value : 3.8e-05 ; + } + leakage_power () { + when : "(c & b & !(a))" ; + value : 3.7e-05 ; + } + leakage_power () { + when : "((a ^ b) & !(c))" ; + value : 8e-07 ; + } + leakage_power () { + when : "(c & !(b) & !(a))" ; + value : 7.6e-07 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 3.5e-07 ; + } + pin (c) { + direction : input ; + capacitance : 3.48 ; + } + pin (b) { + direction : input ; + capacitance : 3.06 ; + } + pin (a) { + direction : input ; + capacitance : 2.88 ; + } + pin (z) { + function : "((!(a) | !(b)) | !(c))" ; + direction : output ; + capacitance : 3.92 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__57) { + values ("60.0, 60.0, 60.0, 81.4, 122.3", \ + "81.5, 81.5, 81.5, 104.4, 147.7", \ + "118.6, 118.6, 118.6, 143.4, 190.1", \ + "188.7, 188.7, 188.7, 214.9, 265.2", \ + "326.1, 326.1, 326.1, 353.3, 406.3"); + } + rise_transition (inslew_load_5x5__57) { + values ("116.5, 116.5, 116.5, 160.4, 246.7", \ + "169.9, 169.9, 169.9, 213.6, 300.1", \ + "270.1, 270.1, 270.1, 314.3, 401.8", \ + "466.2, 466.2, 466.2, 510.9, 599.5", \ + "856.2, 856.2, 856.2, 901.1, 990.6"); + } + cell_fall (inslew_load_5x5__57) { + values ("28.1, 28.1, 28.1, 42.6, 70.7", \ + "21.1, 21.1, 21.1, 37.0, 66.6", \ + "3.4, 3.4, 3.4, 21.6, 54.6", \ + "-37.0, -37.0, -37.0, -16.1, 21.9", \ + "-123.3, -123.3, -123.3, -99.7, -56.0"); + } + fall_transition (inslew_load_5x5__57) { + values ("53.4, 53.4, 53.4, 74.2, 116.3", \ + "63.4, 63.4, 63.4, 84.2, 125.7", \ + "83.2, 83.2, 83.2, 104.3, 145.7", \ + "121.6, 121.6, 121.6, 143.3, 185.8", \ + "197.1, 197.1, 197.1, 219.5, 263.4"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__57) { + values ("49.3, 49.3, 49.3, 71.3, 112.6", \ + "64.8, 64.8, 64.8, 88.9, 133.2", \ + "90.6, 90.6, 90.6, 116.9, 165.6", \ + "138.5, 138.5, 138.5, 166.6, 219.6", \ + "231.7, 231.7, 231.7, 261.0, 317.6"); + } + rise_transition (inslew_load_5x5__57) { + values ("95.7, 95.7, 95.7, 139.1, 225.9", \ + "139.8, 139.8, 139.8, 183.8, 270.6", \ + "222.5, 222.5, 222.5, 267.2, 355.3", \ + "384.4, 384.4, 384.4, 429.6, 519.1", \ + "706.3, 706.3, 706.3, 751.9, 842.4"); + } + cell_fall (inslew_load_5x5__57) { + values ("26.3, 26.3, 26.3, 41.8, 70.6", \ + "22.6, 22.6, 22.6, 40.3, 72.0", \ + "11.0, 11.0, 11.0, 31.7, 68.2", \ + "-16.8, -16.8, -16.8, 6.9, 49.5", \ + "-76.4, -76.4, -76.4, -50.1, -1.5"); + } + fall_transition (inslew_load_5x5__57) { + values ("45.3, 45.3, 45.3, 66.3, 108.3", \ + "57.6, 57.6, 57.6, 78.9, 120.6", \ + "81.1, 81.1, 81.1, 103.0, 145.6", \ + "126.7, 126.7, 126.7, 149.5, 193.6", \ + "216.8, 216.8, 216.8, 240.2, 286.0"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__57) { + values ("37.5, 37.5, 37.5, 60.6, 102.6", \ + "48.0, 48.0, 48.0, 73.7, 119.4", \ + "64.9, 64.9, 64.9, 93.1, 143.9", \ + "95.5, 95.5, 95.5, 125.8, 181.9", \ + "154.8, 154.8, 154.8, 186.4, 246.8"); + } + rise_transition (inslew_load_5x5__57) { + values ("73.9, 73.9, 73.9, 117.7, 204.5", \ + "111.3, 111.3, 111.3, 155.8, 243.0", \ + "181.4, 181.4, 181.4, 226.6, 315.4", \ + "318.7, 318.7, 318.7, 364.5, 454.9", \ + "591.7, 591.7, 591.7, 638.0, 729.6"); + } + cell_fall (inslew_load_5x5__57) { + values ("21.7, 21.7, 21.7, 38.6, 68.9", \ + "20.4, 20.4, 20.4, 40.5, 74.6", \ + "13.6, 13.6, 13.6, 37.2, 77.6", \ + "-3.2, -3.2, -3.2, 23.4, 70.7", \ + "-39.6, -39.6, -39.6, -10.5, 42.8"); + } + fall_transition (inslew_load_5x5__57) { + values ("36.3, 36.3, 36.3, 57.3, 99.9", \ + "50.2, 50.2, 50.2, 72.2, 114.6", \ + "76.6, 76.6, 76.6, 99.6, 143.5", \ + "128.1, 128.1, 128.1, 151.9, 197.8", \ + "230.1, 230.1, 230.1, 254.6, 302.4"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__57) { + values ("128.7, 128.7, 128.7, 177.8, 275.9", \ + "173.3, 173.3, 173.3, 222.4, 320.5", \ + "262.6, 262.6, 262.6, 311.6, 409.7", \ + "441.1, 441.1, 441.1, 490.1, 588.2", \ + "798.1, 798.1, 798.1, 847.1, 945.2"); + } + fall_power (energy_inslew_load_5x5__57) { + values ("111.8, 111.8, 111.8, 160.8, 258.9", \ + "125.7, 125.7, 125.7, 174.7, 272.8", \ + "153.5, 153.5, 153.5, 202.5, 300.6", \ + "209.1, 209.1, 209.1, 258.1, 356.2", \ + "320.2, 320.2, 320.2, 369.3, 467.3"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__57) { + values ("102.7, 102.7, 102.7, 151.7, 249.8", \ + "138.2, 138.2, 138.2, 187.2, 285.3", \ + "209.2, 209.2, 209.2, 258.2, 356.3", \ + "351.2, 351.2, 351.2, 400.2, 498.3", \ + "635.2, 635.2, 635.2, 684.2, 782.3"); + } + fall_power (energy_inslew_load_5x5__57) { + values ("90.3, 90.3, 90.3, 139.3, 237.4", \ + "106.2, 106.2, 106.2, 155.2, 253.3", \ + "137.9, 137.9, 137.9, 187.0, 285.1", \ + "201.5, 201.5, 201.5, 250.6, 348.6", \ + "328.7, 328.7, 328.7, 377.7, 475.8"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__57) { + values ("76.6, 76.6, 76.6, 125.7, 223.8", \ + "105.7, 105.7, 105.7, 154.7, 252.8", \ + "163.8, 163.8, 163.8, 212.9, 310.9", \ + "280.1, 280.1, 280.1, 329.1, 427.2", \ + "512.6, 512.6, 512.6, 561.6, 659.7"); + } + fall_power (energy_inslew_load_5x5__57) { + values ("67.8, 67.8, 67.8, 116.8, 214.9", \ + "85.1, 85.1, 85.1, 134.1, 232.2", \ + "119.6, 119.6, 119.6, 168.7, 266.7", \ + "188.7, 188.7, 188.7, 237.8, 335.8", \ + "326.9, 326.9, 326.9, 376.0, 474.1"); + } + } + } + } + + cell (nd3v0x1) { + area : 0.0 ; + cell_leakage_power : 0.43 ; + leakage_power () { + when : "(c & b & a)" ; + value : 3 ; + } + leakage_power () { + when : "(!(c) & b & a)" ; + value : 0.00011 ; + } + leakage_power () { + when : "(c & !(b) & a)" ; + value : 9e-05 ; + } + leakage_power () { + when : "(c & b & !(a))" ; + value : 8.6e-05 ; + } + leakage_power () { + when : "((a ^ b) & !(c))" ; + value : 1.9e-06 ; + } + leakage_power () { + when : "(c & !(b) & !(a))" ; + value : 1.8e-06 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 8.3e-07 ; + } + pin (c) { + direction : input ; + capacitance : 4.95 ; + } + pin (b) { + direction : input ; + capacitance : 4.84 ; + } + pin (a) { + direction : input ; + capacitance : 4.94 ; + } + pin (z) { + function : "((!(c) | !(b)) | !(a))" ; + direction : output ; + capacitance : 5.49 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__58) { + values ("51.7, 51.7, 51.7, 66.5, 94.7", \ + "72.3, 72.3, 72.3, 88.3, 118.6", \ + "108.5, 108.5, 108.5, 125.7, 158.4", \ + "177.6, 177.6, 177.6, 195.6, 230.6", \ + "313.5, 313.5, 313.5, 332.1, 368.7"); + } + rise_transition (inslew_load_5x5__58) { + values ("91.2, 91.2, 91.2, 117.6, 170.8", \ + "139.6, 139.6, 139.6, 166.4, 219.3", \ + "230.7, 230.7, 230.7, 257.8, 311.4", \ + "409.5, 409.5, 409.5, 436.9, 491.2", \ + "765.3, 765.3, 765.3, 792.8, 847.5"); + } + cell_fall (inslew_load_5x5__58) { + values ("21.9, 21.9, 21.9, 31.7, 50.5", \ + "14.3, 14.3, 14.3, 25.3, 45.6", \ + "-4.5, -4.5, -4.5, 8.2, 31.5", \ + "-46.6, -46.6, -46.6, -31.9, -4.8", \ + "-134.7, -134.7, -134.7, -118.3, -87.5"); + } + fall_transition (inslew_load_5x5__58) { + values ("43.8, 43.8, 43.8, 57.1, 83.9", \ + "53.4, 53.4, 53.4, 66.8, 93.6", \ + "72.4, 72.4, 72.4, 86.1, 113.1", \ + "109.2, 109.2, 109.2, 123.4, 151.3", \ + "181.8, 181.8, 181.8, 196.5, 225.3"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__58) { + values ("41.3, 41.3, 41.3, 56.8, 85.6", \ + "56.4, 56.4, 56.4, 73.3, 104.7", \ + "82.2, 82.2, 82.2, 100.6, 134.9", \ + "131.0, 131.0, 131.0, 150.4, 187.5", \ + "226.8, 226.8, 226.8, 246.9, 286.0"); + } + rise_transition (inslew_load_5x5__58) { + values ("73.6, 73.6, 73.6, 100.2, 153.5", \ + "114.4, 114.4, 114.4, 141.4, 194.7", \ + "191.1, 191.1, 191.1, 218.6, 272.7", \ + "341.9, 341.9, 341.9, 369.7, 424.6", \ + "641.8, 641.8, 641.8, 669.8, 725.3"); + } + cell_fall (inslew_load_5x5__58) { + values ("19.6, 19.6, 19.6, 30.4, 50.1", \ + "14.6, 14.6, 14.6, 27.2, 49.6", \ + "1.0, 1.0, 1.0, 15.8, 42.0", \ + "-29.6, -29.6, -29.6, -12.8, 17.6", \ + "-93.8, -93.8, -93.8, -75.5, -41.0"); + } + fall_transition (inslew_load_5x5__58) { + values ("36.2, 36.2, 36.2, 49.7, 76.5", \ + "47.7, 47.7, 47.7, 61.6, 88.5", \ + "69.7, 69.7, 69.7, 84.1, 112.0", \ + "112.7, 112.7, 112.7, 127.6, 156.6", \ + "197.7, 197.7, 197.7, 213.1, 243.2"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__58) { + values ("29.4, 29.4, 29.4, 46.1, 75.8", \ + "39.7, 39.7, 39.7, 58.1, 90.9", \ + "56.9, 56.9, 56.9, 76.7, 113.1", \ + "89.1, 89.1, 89.1, 110.1, 149.6", \ + "152.3, 152.3, 152.3, 173.9, 215.7"); + } + rise_transition (inslew_load_5x5__58) { + values ("54.8, 54.8, 54.8, 81.8, 135.3", \ + "89.6, 89.6, 89.6, 117.1, 170.8", \ + "155.4, 155.4, 155.4, 183.3, 238.0", \ + "284.6, 284.6, 284.6, 312.8, 368.5", \ + "541.8, 541.8, 541.8, 570.2, 626.6"); + } + cell_fall (inslew_load_5x5__58) { + values ("14.6, 14.6, 14.6, 27.0, 48.1", \ + "11.4, 11.4, 11.4, 26.2, 51.0", \ + "2.3, 2.3, 2.3, 19.4, 48.9", \ + "-17.9, -17.9, -17.9, 1.0, 35.1", \ + "-59.8, -59.8, -59.8, -39.6, -1.7"); + } + fall_transition (inslew_load_5x5__58) { + values ("27.8, 27.8, 27.8, 41.7, 68.6", \ + "40.7, 40.7, 40.7, 55.2, 82.9", \ + "65.3, 65.3, 65.3, 80.5, 109.5", \ + "113.7, 113.7, 113.7, 129.4, 159.7", \ + "209.9, 209.9, 209.9, 226.0, 257.4"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__58) { + values ("228.6, 228.6, 228.6, 297.2, 434.6", \ + "319.5, 319.5, 319.5, 388.2, 525.6", \ + "501.4, 501.4, 501.4, 570.1, 707.5", \ + "865.2, 865.2, 865.2, 933.9, 1071.3", \ + "1592.8, 1592.8, 1592.8, 1661.5, 1798.9"); + } + fall_power (energy_inslew_load_5x5__58) { + values ("194.6, 194.6, 194.6, 263.3, 400.7", \ + "223.2, 223.2, 223.2, 291.9, 429.2", \ + "280.3, 280.3, 280.3, 349.0, 486.3", \ + "394.4, 394.4, 394.4, 463.1, 600.5", \ + "622.7, 622.7, 622.7, 691.4, 828.8"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__58) { + values ("178.4, 178.4, 178.4, 247.1, 384.4", \ + "252.2, 252.2, 252.2, 320.9, 458.3", \ + "399.8, 399.8, 399.8, 468.5, 605.9", \ + "695.1, 695.1, 695.1, 763.8, 901.2", \ + "1285.7, 1285.7, 1285.7, 1354.4, 1491.8"); + } + fall_power (energy_inslew_load_5x5__58) { + values ("150.8, 150.8, 150.8, 219.5, 356.9", \ + "182.7, 182.7, 182.7, 251.4, 388.8", \ + "246.6, 246.6, 246.6, 315.3, 452.6", \ + "374.3, 374.3, 374.3, 443.0, 580.3", \ + "629.7, 629.7, 629.7, 698.3, 835.7"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__58) { + values ("127.0, 127.0, 127.0, 195.7, 333.0", \ + "187.9, 187.9, 187.9, 256.6, 394.0", \ + "309.8, 309.8, 309.8, 378.5, 515.9", \ + "553.6, 553.6, 553.6, 622.3, 759.6", \ + "1041.1, 1041.1, 1041.1, 1109.8, 1247.2"); + } + fall_power (energy_inslew_load_5x5__58) { + values ("106.0, 106.0, 106.0, 174.7, 312.1", \ + "140.7, 140.7, 140.7, 209.4, 346.8", \ + "210.1, 210.1, 210.1, 278.8, 416.2", \ + "348.9, 348.9, 348.9, 417.6, 555.0", \ + "626.5, 626.5, 626.5, 695.2, 832.6"); + } + } + } + } + + cell (nd4v0x05) { + area : 0.0 ; + cell_leakage_power : 1.9 ; + leakage_power () { + when : "(d & c & b & a)" ; + value : 19 ; + } + leakage_power () { + when : "(!(d) & c & b & a)" ; + value : 7e-05 ; + } + leakage_power () { + when : "(d & !(c) & b & a)" ; + value : 5.6e-05 ; + } + leakage_power () { + when : "(d & c & !(b) & a)" ; + value : 5.5e-05 ; + } + leakage_power () { + when : "(d & c & b & !(a))" ; + value : 5.4e-05 ; + } + leakage_power () { + when : "((a & (b ^ c) & !(d)) | (!(a) & b & c & !(d)))" ; + value : 1.3e-06 ; + } + leakage_power () { + when : "((a & !(b) & !(c) & d) | (!(a) & (b ^ c) & d))" ; + value : 1.2e-06 ; + } + leakage_power () { + when : "((a & !(b) & !(c) & !(d)) | (!(a) & (b ^ c) & !(d)))" ; + value : 5.7e-07 ; + } + leakage_power () { + when : "(d & !(c) & !(b) & !(a))" ; + value : 5.6e-07 ; + } + leakage_power () { + when : "(!(d) & !(c) & !(b) & !(a))" ; + value : 3.6e-07 ; + } + pin (d) { + direction : input ; + capacitance : 3.32 ; + } + pin (c) { + direction : input ; + capacitance : 3.77 ; + } + pin (b) { + direction : input ; + capacitance : 3.88 ; + } + pin (a) { + direction : input ; + capacitance : 3.41 ; + } + pin (z) { + function : "(((!(a) | !(b)) | !(c)) | !(d))" ; + direction : output ; + capacitance : 4.51 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__59) { + values ("76.7, 76.7, 76.7, 100.5, 147.1", \ + "103.2, 103.2, 103.2, 128.4, 176.8", \ + "148.6, 148.6, 148.6, 175.7, 227.3", \ + "233.9, 233.9, 233.9, 262.5, 317.7", \ + "400.4, 400.4, 400.4, 430.2, 488.4"); + } + rise_transition (inslew_load_5x5__59) { + values ("148.4, 148.4, 148.4, 198.5, 298.8", \ + "209.6, 209.6, 209.6, 259.4, 359.7", \ + "322.5, 322.5, 322.5, 372.9, 472.8", \ + "542.5, 542.5, 542.5, 593.4, 694.5", \ + "979.2, 979.2, 979.2, 1030.4, 1132.4"); + } + cell_fall (inslew_load_5x5__59) { + values ("37.2, 37.2, 37.2, 53.2, 84.9", \ + "28.5, 28.5, 28.5, 45.4, 78.0", \ + "8.2, 8.2, 8.2, 26.9, 61.9", \ + "-38.1, -38.1, -38.1, -16.6, 22.9", \ + "-137.9, -137.9, -137.9, -113.3, -67.7"); + } + fall_transition (inslew_load_5x5__59) { + values ("74.1, 74.1, 74.1, 99.9, 151.7", \ + "82.9, 82.9, 82.9, 108.2, 159.3", \ + "100.5, 100.5, 100.5, 125.9, 176.7", \ + "135.3, 135.3, 135.3, 161.2, 212.2", \ + "203.4, 203.4, 203.4, 230.0, 282.3"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__59) { + values ("65.6, 65.6, 65.6, 89.9, 136.8", \ + "86.3, 86.3, 86.3, 112.4, 161.6", \ + "120.7, 120.7, 120.7, 149.0, 202.1", \ + "183.9, 183.9, 183.9, 214.2, 271.9", \ + "306.6, 306.6, 306.6, 338.4, 399.8"); + } + rise_transition (inslew_load_5x5__59) { + values ("126.2, 126.2, 126.2, 176.4, 276.3", \ + "177.6, 177.6, 177.6, 227.7, 328.3", \ + "272.4, 272.4, 272.4, 323.2, 423.6", \ + "457.0, 457.0, 457.0, 508.4, 610.3", \ + "823.4, 823.4, 823.4, 875.2, 978.2"); + } + cell_fall (inslew_load_5x5__59) { + values ("34.8, 34.8, 34.8, 51.3, 83.4", \ + "29.8, 29.8, 29.8, 47.9, 81.7", \ + "15.4, 15.4, 15.4, 36.1, 73.7", \ + "-19.5, -19.5, -19.5, 4.4, 48.0", \ + "-95.7, -95.7, -95.7, -68.5, -18.3"); + } + fall_transition (inslew_load_5x5__59) { + values ("64.3, 64.3, 64.3, 90.0, 141.8", \ + "75.4, 75.4, 75.4, 101.0, 152.1", \ + "97.0, 97.0, 97.0, 123.0, 174.1", \ + "138.7, 138.7, 138.7, 165.5, 217.8", \ + "220.7, 220.7, 220.7, 248.2, 302.2"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__59) { + values ("54.1, 54.1, 54.1, 79.0, 126.1", \ + "70.1, 70.1, 70.1, 97.3, 147.4", \ + "95.8, 95.8, 95.8, 125.6, 180.5", \ + "142.4, 142.4, 142.4, 174.5, 234.7", \ + "232.4, 232.4, 232.4, 266.1, 330.7"); + } + rise_transition (inslew_load_5x5__59) { + values ("103.6, 103.6, 103.6, 154.1, 253.5", \ + "148.0, 148.0, 148.0, 198.4, 298.0", \ + "229.9, 229.9, 229.9, 281.2, 382.2", \ + "389.6, 389.6, 389.6, 441.5, 544.1", \ + "706.4, 706.4, 706.4, 758.8, 862.7"); + } + cell_fall (inslew_load_5x5__59) { + values ("29.9, 29.9, 29.9, 47.5, 80.3", \ + "27.5, 27.5, 27.5, 47.4, 83.0", \ + "17.5, 17.5, 17.5, 40.6, 81.5", \ + "-8.2, -8.2, -8.2, 18.6, 66.4", \ + "-64.6, -64.6, -64.6, -34.6, 20.3"); + } + fall_transition (inslew_load_5x5__59) { + values ("52.9, 52.9, 52.9, 79.0, 130.8", \ + "65.9, 65.9, 65.9, 92.1, 143.8", \ + "90.2, 90.2, 90.2, 117.0, 169.3", \ + "137.2, 137.2, 137.2, 165.0, 218.9", \ + "229.7, 229.7, 229.7, 258.3, 314.2"); + } + } + timing (maxd_z_d_negative_unate) { + related_pin : "d" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__59) { + values ("41.1, 41.1, 41.1, 67.1, 114.8", \ + "52.7, 52.7, 52.7, 81.6, 133.1", \ + "70.9, 70.9, 70.9, 102.7, 159.8", \ + "103.5, 103.5, 103.5, 137.8, 200.9", \ + "166.4, 166.4, 166.4, 202.3, 270.5"); + } + rise_transition (inslew_load_5x5__59) { + values ("79.1, 79.1, 79.1, 129.3, 229.2", \ + "118.0, 118.0, 118.0, 168.9, 268.9", \ + "189.7, 189.7, 189.7, 241.5, 343.2", \ + "329.7, 329.7, 329.7, 382.2, 485.7", \ + "607.7, 607.7, 607.7, 660.7, 765.7"); + } + cell_fall (inslew_load_5x5__59) { + values ("23.4, 23.4, 23.4, 41.6, 75.7", \ + "22.5, 22.5, 22.5, 44.5, 81.9", \ + "16.0, 16.0, 16.0, 42.0, 86.4", \ + "-1.5, -1.5, -1.5, 28.3, 80.6", \ + "-39.8, -39.8, -39.8, -6.9, 52.8"); + } + fall_transition (inslew_load_5x5__59) { + values ("41.5, 41.5, 41.5, 66.8, 119.6", \ + "55.7, 55.7, 55.7, 82.4, 134.0", \ + "82.2, 82.2, 82.2, 110.0, 163.6", \ + "133.6, 133.6, 133.6, 162.5, 218.3", \ + "235.5, 235.5, 235.5, 265.2, 323.0"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__59) { + values ("169.5, 169.5, 169.5, 225.9, 338.7", \ + "220.4, 220.4, 220.4, 276.8, 389.6", \ + "322.3, 322.3, 322.3, 378.7, 491.4", \ + "525.9, 525.9, 525.9, 582.3, 695.1", \ + "933.2, 933.2, 933.2, 989.6, 1102.4"); + } + fall_power (energy_inslew_load_5x5__59) { + values ("151.0, 151.0, 151.0, 207.4, 320.2", \ + "163.5, 163.5, 163.5, 219.9, 332.7", \ + "188.4, 188.4, 188.4, 244.8, 357.6", \ + "238.3, 238.3, 238.3, 294.7, 407.5", \ + "338.0, 338.0, 338.0, 394.4, 507.2"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__59) { + values ("141.0, 141.0, 141.0, 197.4, 310.2", \ + "182.4, 182.4, 182.4, 238.8, 351.6", \ + "265.2, 265.2, 265.2, 321.6, 434.4", \ + "430.9, 430.9, 430.9, 487.3, 600.1", \ + "762.2, 762.2, 762.2, 818.6, 931.4"); + } + fall_power (energy_inslew_load_5x5__59) { + values ("127.5, 127.5, 127.5, 183.9, 296.7", \ + "142.1, 142.1, 142.1, 198.5, 311.3", \ + "171.3, 171.3, 171.3, 227.7, 340.5", \ + "229.7, 229.7, 229.7, 286.1, 398.9", \ + "346.4, 346.4, 346.4, 402.8, 515.6"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__59) { + values ("113.1, 113.1, 113.1, 169.5, 282.3", \ + "147.9, 147.9, 147.9, 204.3, 317.1", \ + "217.5, 217.5, 217.5, 273.9, 386.7", \ + "356.7, 356.7, 356.7, 413.1, 525.9", \ + "635.1, 635.1, 635.1, 691.5, 804.3"); + } + fall_power (energy_inslew_load_5x5__59) { + values ("101.3, 101.3, 101.3, 157.7, 270.4", \ + "117.2, 117.2, 117.2, 173.6, 286.4", \ + "149.1, 149.1, 149.1, 205.5, 318.3", \ + "212.9, 212.9, 212.9, 269.3, 382.1", \ + "340.6, 340.6, 340.6, 397.0, 509.8"); + } + } + internal_power (energy_neg_z_d) { + related_pin : "d" ; + rise_power (energy_inslew_load_5x5__59) { + values ("84.0, 84.0, 84.0, 140.4, 253.2", \ + "113.7, 113.7, 113.7, 170.1, 282.9", \ + "173.1, 173.1, 173.1, 229.5, 342.3", \ + "291.8, 291.8, 291.8, 348.2, 461.0", \ + "529.3, 529.3, 529.3, 585.7, 698.5"); + } + fall_power (energy_inslew_load_5x5__59) { + values ("75.5, 75.5, 75.5, 131.9, 244.7", \ + "92.5, 92.5, 92.5, 148.9, 261.7", \ + "126.5, 126.5, 126.5, 182.9, 295.7", \ + "194.6, 194.6, 194.6, 251.0, 363.8", \ + "330.7, 330.7, 330.7, 387.1, 499.9"); + } + } + } + } + + cell (nd4v0x1) { + area : 0.0 ; + cell_leakage_power : 0.14 ; + leakage_power () { + when : "(d & c & b & a)" ; + value : 1.1 ; + } + leakage_power () { + when : "(!(d) & c & b & a)" ; + value : 0.00011 ; + } + leakage_power () { + when : "(d & !(c) & b & a)" ; + value : 9e-05 ; + } + leakage_power () { + when : "((a ^ b) & c & d)" ; + value : 8.6e-05 ; + } + leakage_power () { + when : "((a & (b ^ c) & !(d)) | (!(a) & b & c & !(d)))" ; + value : 1.9e-06 ; + } + leakage_power () { + when : "((a & !(b) & !(c) & d) | (!(a) & (b ^ c) & d))" ; + value : 1.8e-06 ; + } + leakage_power () { + when : "((a & !(b) & !(c) & !(d)) | (!(a) & ((b & !(c) & !(d)) | (!(b) & (c ^ d)))))" ; + value : 8.3e-07 ; + } + leakage_power () { + when : "(!(d) & !(c) & !(b) & !(a))" ; + value : 5.2e-07 ; + } + pin (d) { + direction : input ; + capacitance : 4.78 ; + } + pin (c) { + direction : input ; + capacitance : 4.95 ; + } + pin (b) { + direction : input ; + capacitance : 5.04 ; + } + pin (a) { + direction : input ; + capacitance : 4.86 ; + } + pin (z) { + function : "(((!(a) | !(b)) | !(c)) | !(d))" ; + direction : output ; + capacitance : 6.06 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__60) { + values ("70.2, 70.2, 70.2, 89.3, 126.4", \ + "96.7, 96.7, 96.7, 117.1, 156.1", \ + "142.6, 142.6, 142.6, 164.4, 206.2", \ + "229.1, 229.1, 229.1, 252.1, 296.7", \ + "398.6, 398.6, 398.6, 422.5, 469.4"); + } + rise_transition (inslew_load_5x5__60) { + values ("118.6, 118.6, 118.6, 153.9, 224.1", \ + "172.8, 172.8, 172.8, 207.8, 278.5", \ + "273.1, 273.1, 273.1, 308.4, 378.6", \ + "468.7, 468.7, 468.7, 504.4, 575.3", \ + "857.0, 857.0, 857.0, 893.0, 964.5"); + } + cell_fall (inslew_load_5x5__60) { + values ("32.1, 32.1, 32.1, 44.5, 69.1", \ + "22.8, 22.8, 22.8, 36.1, 61.6", \ + "1.1, 1.1, 1.1, 16.1, 44.0", \ + "-47.8, -47.8, -47.8, -30.5, 1.5", \ + "-152.7, -152.7, -152.7, -132.8, -95.6"); + } + fall_transition (inslew_load_5x5__60) { + values ("65.4, 65.4, 65.4, 85.0, 124.4", \ + "73.8, 73.8, 73.8, 93.1, 131.9", \ + "90.4, 90.4, 90.4, 109.9, 148.9", \ + "123.1, 123.1, 123.1, 143.1, 182.3", \ + "187.0, 187.0, 187.0, 207.6, 248.0"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__60) { + values ("59.7, 59.7, 59.7, 79.3, 116.7", \ + "80.6, 80.6, 80.6, 101.7, 141.5", \ + "115.8, 115.8, 115.8, 138.7, 181.9", \ + "181.3, 181.3, 181.3, 205.7, 252.5", \ + "309.2, 309.2, 309.2, 334.7, 384.2"); + } + rise_transition (inslew_load_5x5__60) { + values ("100.2, 100.2, 100.2, 135.6, 205.5", \ + "146.3, 146.3, 146.3, 181.5, 251.3", \ + "231.4, 231.4, 231.4, 267.1, 337.6", \ + "397.5, 397.5, 397.5, 433.5, 505.1", \ + "727.1, 727.1, 727.1, 763.5, 835.8"); + } + cell_fall (inslew_load_5x5__60) { + values ("29.7, 29.7, 29.7, 42.6, 67.6", \ + "23.7, 23.7, 23.7, 38.1, 64.9", \ + "7.3, 7.3, 7.3, 24.0, 54.5", \ + "-31.3, -31.3, -31.3, -11.7, 23.8", \ + "-114.1, -114.1, -114.1, -92.0, -50.9"); + } + fall_transition (inslew_load_5x5__60) { + values ("56.2, 56.2, 56.2, 75.6, 114.9", \ + "66.5, 66.5, 66.5, 86.1, 125.1", \ + "86.6, 86.6, 86.6, 106.7, 146.0", \ + "125.5, 125.5, 125.5, 146.2, 186.6", \ + "201.8, 201.8, 201.8, 223.1, 265.0"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__60) { + values ("48.6, 48.6, 48.6, 68.8, 106.8", \ + "65.1, 65.1, 65.1, 87.2, 128.1", \ + "92.3, 92.3, 92.3, 116.5, 161.4", \ + "142.7, 142.7, 142.7, 168.5, 217.4", \ + "240.8, 240.8, 240.8, 267.7, 319.8"); + } + rise_transition (inslew_load_5x5__60) { + values ("81.4, 81.4, 81.4, 116.4, 186.6", \ + "121.8, 121.8, 121.8, 157.3, 227.3", \ + "196.6, 196.6, 196.6, 232.7, 303.6", \ + "342.6, 342.6, 342.6, 379.0, 451.2", \ + "632.3, 632.3, 632.3, 669.1, 742.2"); + } + cell_fall (inslew_load_5x5__60) { + values ("24.8, 24.8, 24.8, 38.7, 64.6", \ + "20.8, 20.8, 20.8, 36.9, 65.7", \ + "8.0, 8.0, 8.0, 27.0, 60.6", \ + "-22.5, -22.5, -22.5, -0.4, 39.0", \ + "-88.0, -88.0, -88.0, -63.4, -18.0"); + } + fall_transition (inslew_load_5x5__60) { + values ("45.4, 45.4, 45.4, 65.0, 104.5", \ + "57.2, 57.2, 57.2, 77.2, 116.7", \ + "79.5, 79.5, 79.5, 100.3, 140.6", \ + "122.6, 122.6, 122.6, 144.1, 186.0", \ + "207.6, 207.6, 207.6, 229.8, 273.2"); + } + } + timing (maxd_z_d_negative_unate) { + related_pin : "d" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__60) { + values ("37.9, 37.9, 37.9, 59.2, 97.8", \ + "55.3, 55.3, 55.3, 78.3, 119.9", \ + "85.1, 85.1, 85.1, 109.8, 155.3", \ + "141.9, 141.9, 141.9, 167.8, 216.8", \ + "253.6, 253.6, 253.6, 280.3, 331.9"); + } + rise_transition (inslew_load_5x5__60) { + values ("64.4, 64.4, 64.4, 99.6, 169.8", \ + "107.2, 107.2, 107.2, 142.9, 213.0", \ + "186.5, 186.5, 186.5, 222.6, 293.8", \ + "341.6, 341.6, 341.6, 378.1, 450.3", \ + "649.9, 649.9, 649.9, 686.6, 759.5"); + } + cell_fall (inslew_load_5x5__60) { + values ("16.6, 16.6, 16.6, 32.1, 59.0", \ + "11.2, 11.2, 11.2, 30.2, 61.6", \ + "-4.6, -4.6, -4.6, 18.6, 56.9", \ + "-40.8, -40.8, -40.8, -13.5, 33.0", \ + "-116.9, -116.9, -116.9, -86.4, -31.7"); + } + fall_transition (inslew_load_5x5__60) { + values ("32.8, 32.8, 32.8, 52.6, 92.0", \ + "43.1, 43.1, 43.1, 64.0, 104.1", \ + "62.1, 62.1, 62.1, 84.2, 126.1", \ + "98.6, 98.6, 98.6, 121.9, 166.1", \ + "170.7, 170.7, 170.7, 194.8, 241.3"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__60) { + values ("261.8, 261.8, 261.8, 337.6, 489.2", \ + "346.6, 346.6, 346.6, 422.4, 573.9", \ + "516.1, 516.1, 516.1, 591.9, 743.4", \ + "855.1, 855.1, 855.1, 930.9, 1082.5", \ + "1533.2, 1533.2, 1533.2, 1609.0, 1760.6"); + } + fall_power (energy_inslew_load_5x5__60) { + values ("232.3, 232.3, 232.3, 308.1, 459.7", \ + "252.4, 252.4, 252.4, 328.2, 479.8", \ + "292.6, 292.6, 292.6, 368.3, 519.9", \ + "372.9, 372.9, 372.9, 448.6, 600.2", \ + "533.5, 533.5, 533.5, 609.2, 760.8"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__60) { + values ("215.9, 215.9, 215.9, 291.6, 443.2", \ + "285.4, 285.4, 285.4, 361.2, 512.8", \ + "424.5, 424.5, 424.5, 500.3, 651.8", \ + "702.7, 702.7, 702.7, 778.5, 930.0", \ + "1259.0, 1259.0, 1259.0, 1334.8, 1486.4"); + } + fall_power (energy_inslew_load_5x5__60) { + values ("192.7, 192.7, 192.7, 268.5, 420.1", \ + "216.0, 216.0, 216.0, 291.8, 443.4", \ + "262.7, 262.7, 262.7, 338.5, 490.0", \ + "356.0, 356.0, 356.0, 431.8, 583.3", \ + "542.6, 542.6, 542.6, 618.4, 769.9"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__60) { + values ("171.2, 171.2, 171.2, 247.0, 398.5", \ + "230.6, 230.6, 230.6, 306.4, 457.9", \ + "349.3, 349.3, 349.3, 425.1, 576.7", \ + "586.8, 586.8, 586.8, 662.6, 814.1", \ + "1061.7, 1061.7, 1061.7, 1137.5, 1289.1"); + } + fall_power (energy_inslew_load_5x5__60) { + values ("148.5, 148.5, 148.5, 224.3, 375.9", \ + "173.5, 173.5, 173.5, 249.3, 400.9", \ + "223.6, 223.6, 223.6, 299.4, 451.0", \ + "323.8, 323.8, 323.8, 399.6, 551.1", \ + "524.1, 524.1, 524.1, 599.9, 751.4"); + } + } + internal_power (energy_neg_z_d) { + related_pin : "d" ; + rise_power (energy_inslew_load_5x5__60) { + values ("136.7, 136.7, 136.7, 212.4, 364.0", \ + "200.8, 200.8, 200.8, 276.6, 428.1", \ + "329.0, 329.0, 329.0, 404.8, 556.4", \ + "585.5, 585.5, 585.5, 661.3, 812.9", \ + "1098.5, 1098.5, 1098.5, 1174.3, 1325.8"); + } + fall_power (energy_inslew_load_5x5__60) { + values ("97.5, 97.5, 97.5, 173.2, 324.8", \ + "115.9, 115.9, 115.9, 191.7, 343.2", \ + "152.8, 152.8, 152.8, 228.5, 380.1", \ + "226.5, 226.5, 226.5, 302.3, 453.8", \ + "374.0, 374.0, 374.0, 449.7, 601.3"); + } + } + } + } + + cell (nd4v0x2) { + area : 0.0 ; + cell_leakage_power : 0.68 ; + leakage_power () { + when : "(d & c & b & a)" ; + value : 5.4 ; + } + leakage_power () { + when : "(!(d) & c & b & a)" ; + value : 0.00019 ; + } + leakage_power () { + when : "(a & (b ^ c) & d)" ; + value : 0.00015 ; + } + leakage_power () { + when : "(d & c & b & !(a))" ; + value : 0.00014 ; + } + leakage_power () { + when : "((a & ((b & !(c) & !(d)) | (!(b) & (c ^ d)))) | (!(a) & b & (c ^ d)))" ; + value : 3.4e-06 ; + } + leakage_power () { + when : "(d & c & !(b) & !(a))" ; + value : 3.3e-06 ; + } + leakage_power () { + when : "((a & !(b) & !(c) & !(d)) | (!(a) & ((b & !(c) & !(d)) | (!(b) & (c ^ d)))))" ; + value : 1.5e-06 ; + } + leakage_power () { + when : "(!(d) & !(c) & !(b) & !(a))" ; + value : 9.6e-07 ; + } + pin (d) { + direction : input ; + capacitance : 6.78 ; + } + pin (c) { + direction : input ; + capacitance : 7.02 ; + } + pin (b) { + direction : input ; + capacitance : 8.12 ; + } + pin (a) { + direction : input ; + capacitance : 8.26 ; + } + pin (z) { + function : "(((!(d) | !(c)) | !(b)) | !(a))" ; + direction : output ; + capacitance : 7.78 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__61) { + values ("74.7, 74.7, 74.7, 93.0, 128.8", \ + "103.9, 103.9, 103.9, 123.3, 160.7", \ + "153.6, 153.6, 153.6, 174.2, 214.0", \ + "247.0, 247.0, 247.0, 268.7, 311.0", \ + "430.0, 430.0, 430.0, 452.5, 496.6"); + } + rise_transition (inslew_load_5x5__61) { + values ("124.7, 124.7, 124.7, 157.8, 224.0", \ + "184.7, 184.7, 184.7, 217.4, 283.8", \ + "294.0, 294.0, 294.0, 326.9, 392.5", \ + "506.4, 506.4, 506.4, 539.6, 605.8", \ + "927.7, 927.7, 927.7, 961.2, 1027.9"); + } + cell_fall (inslew_load_5x5__61) { + values ("30.7, 30.7, 30.7, 41.6, 63.2", \ + "21.0, 21.0, 21.0, 32.6, 55.2", \ + "-1.7, -1.7, -1.7, 11.5, 36.4", \ + "-53.2, -53.2, -53.2, -37.6, -8.7", \ + "-163.3, -163.3, -163.3, -145.3, -111.5"); + } + fall_transition (inslew_load_5x5__61) { + values ("63.2, 63.2, 63.2, 80.4, 115.1", \ + "70.8, 70.8, 70.8, 88.0, 122.1", \ + "86.3, 86.3, 86.3, 103.5, 137.5", \ + "116.4, 116.4, 116.4, 134.0, 168.7", \ + "174.8, 174.8, 174.8, 193.0, 228.9"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__61) { + values ("63.0, 63.0, 63.0, 81.7, 117.8", \ + "86.3, 86.3, 86.3, 106.4, 144.5", \ + "125.0, 125.0, 125.0, 146.6, 187.8", \ + "197.1, 197.1, 197.1, 220.0, 264.2", \ + "337.7, 337.7, 337.7, 361.5, 408.0"); + } + rise_transition (inslew_load_5x5__61) { + values ("104.5, 104.5, 104.5, 137.7, 203.5", \ + "156.0, 156.0, 156.0, 188.9, 254.3", \ + "249.9, 249.9, 249.9, 283.2, 349.1", \ + "432.3, 432.3, 432.3, 465.9, 532.7", \ + "794.1, 794.1, 794.1, 827.9, 895.4"); + } + cell_fall (inslew_load_5x5__61) { + values ("28.0, 28.0, 28.0, 39.5, 61.6", \ + "21.4, 21.4, 21.4, 34.2, 58.1", \ + "3.6, 3.6, 3.6, 18.6, 46.0", \ + "-37.9, -37.9, -37.9, -20.2, 12.0", \ + "-126.8, -126.8, -126.8, -106.7, -69.2"); + } + fall_transition (inslew_load_5x5__61) { + values ("53.8, 53.8, 53.8, 70.9, 105.4", \ + "63.4, 63.4, 63.4, 80.7, 115.1", \ + "82.1, 82.1, 82.1, 99.9, 134.6", \ + "118.1, 118.1, 118.1, 136.5, 172.3", \ + "188.6, 188.6, 188.6, 207.6, 244.7"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__61) { + values ("50.4, 50.4, 50.4, 69.8, 106.4", \ + "68.7, 68.7, 68.7, 89.8, 129.1", \ + "98.6, 98.6, 98.6, 121.5, 164.3", \ + "153.9, 153.9, 153.9, 178.2, 224.4", \ + "261.5, 261.5, 261.5, 286.7, 335.7"); + } + rise_transition (inslew_load_5x5__61) { + values ("83.5, 83.5, 83.5, 116.4, 182.4", \ + "128.7, 128.7, 128.7, 161.9, 227.4", \ + "211.1, 211.1, 211.1, 244.7, 311.0", \ + "371.2, 371.2, 371.2, 405.2, 472.6", \ + "688.7, 688.7, 688.7, 723.0, 791.3"); + } + cell_fall (inslew_load_5x5__61) { + values ("23.0, 23.0, 23.0, 35.3, 58.3", \ + "18.2, 18.2, 18.2, 32.7, 58.5", \ + "4.1, 4.1, 4.1, 21.3, 51.6", \ + "-29.0, -29.0, -29.0, -9.0, 26.9", \ + "-99.4, -99.4, -99.4, -77.1, -35.8"); + } + fall_transition (inslew_load_5x5__61) { + values ("42.9, 42.9, 42.9, 60.1, 94.9", \ + "54.1, 54.1, 54.1, 71.8, 106.5", \ + "75.2, 75.2, 75.2, 93.6, 129.3", \ + "116.0, 116.0, 116.0, 135.1, 172.3", \ + "196.3, 196.3, 196.3, 216.1, 254.7"); + } + } + timing (maxd_z_d_negative_unate) { + related_pin : "d" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__61) { + values ("35.7, 35.7, 35.7, 56.5, 94.0", \ + "49.3, 49.3, 49.3, 72.1, 112.8", \ + "71.2, 71.2, 71.2, 95.8, 140.7", \ + "111.6, 111.6, 111.6, 137.6, 186.4", \ + "190.2, 190.2, 190.2, 217.2, 269.0"); + } + rise_transition (inslew_load_5x5__61) { + values ("60.6, 60.6, 60.6, 93.8, 159.7", \ + "100.3, 100.3, 100.3, 134.0, 199.8", \ + "172.9, 172.9, 172.9, 207.1, 274.1", \ + "314.2, 314.2, 314.2, 348.8, 417.0", \ + "594.7, 594.7, 594.7, 629.6, 698.8"); + } + cell_fall (inslew_load_5x5__61) { + values ("15.7, 15.7, 15.7, 29.5, 53.4", \ + "12.2, 12.2, 12.2, 28.9, 56.9", \ + "1.3, 1.3, 1.3, 21.1, 54.7", \ + "-23.6, -23.6, -23.6, -1.1, 38.5", \ + "-75.7, -75.7, -75.7, -51.3, -6.4"); + } + fall_transition (inslew_load_5x5__61) { + values ("31.7, 31.7, 31.7, 49.3, 83.8", \ + "44.1, 44.1, 44.1, 62.5, 97.8", \ + "67.3, 67.3, 67.3, 86.6, 123.5", \ + "112.8, 112.8, 112.8, 132.8, 171.3", \ + "202.9, 202.9, 202.9, 223.4, 263.4"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__61) { + values ("375.9, 375.9, 375.9, 473.1, 667.7", \ + "500.5, 500.5, 500.5, 597.8, 792.4", \ + "749.8, 749.8, 749.8, 847.1, 1041.7", \ + "1248.5, 1248.5, 1248.5, 1345.8, 1540.3", \ + "2245.8, 2245.8, 2245.8, 2343.1, 2537.6"); + } + fall_power (energy_inslew_load_5x5__61) { + values ("326.2, 326.2, 326.2, 423.5, 618.1", \ + "352.0, 352.0, 352.0, 449.3, 643.9", \ + "403.6, 403.6, 403.6, 500.9, 695.5", \ + "506.9, 506.9, 506.9, 604.1, 798.7", \ + "713.3, 713.3, 713.3, 810.6, 1005.1"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__61) { + values ("307.7, 307.7, 307.7, 405.0, 599.6", \ + "411.1, 411.1, 411.1, 508.4, 703.0", \ + "618.0, 618.0, 618.0, 715.3, 909.8", \ + "1031.7, 1031.7, 1031.7, 1129.0, 1323.5", \ + "1859.0, 1859.0, 1859.0, 1956.3, 2150.9"); + } + fall_power (energy_inslew_load_5x5__61) { + values ("267.2, 267.2, 267.2, 364.4, 559.0", \ + "297.6, 297.6, 297.6, 394.9, 589.4", \ + "358.4, 358.4, 358.4, 455.7, 650.3", \ + "480.2, 480.2, 480.2, 577.4, 772.0", \ + "723.6, 723.6, 723.6, 820.9, 1015.4"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__61) { + values ("239.8, 239.8, 239.8, 337.1, 531.7", \ + "327.7, 327.7, 327.7, 425.0, 619.6", \ + "503.5, 503.5, 503.5, 600.8, 795.4", \ + "855.1, 855.1, 855.1, 952.4, 1146.9", \ + "1558.3, 1558.3, 1558.3, 1655.5, 1850.1"); + } + fall_power (energy_inslew_load_5x5__61) { + values ("202.1, 202.1, 202.1, 299.3, 493.9", \ + "235.9, 235.9, 235.9, 333.1, 527.7", \ + "303.5, 303.5, 303.5, 400.7, 595.3", \ + "438.6, 438.6, 438.6, 535.9, 730.5", \ + "709.0, 709.0, 709.0, 806.3, 1000.9"); + } + } + internal_power (energy_neg_z_d) { + related_pin : "d" ; + rise_power (energy_inslew_load_5x5__61) { + values ("167.8, 167.8, 167.8, 265.0, 459.6", \ + "242.9, 242.9, 242.9, 340.1, 534.7", \ + "393.0, 393.0, 393.0, 490.3, 684.9", \ + "693.4, 693.4, 693.4, 790.7, 985.3", \ + "1294.2, 1294.2, 1294.2, 1391.4, 1586.0"); + } + fall_power (energy_inslew_load_5x5__61) { + values ("138.9, 138.9, 138.9, 236.2, 430.8", \ + "175.9, 175.9, 175.9, 273.2, 467.8", \ + "249.9, 249.9, 249.9, 347.2, 541.8", \ + "398.0, 398.0, 398.0, 495.3, 689.8", \ + "694.1, 694.1, 694.1, 791.4, 985.9"); + } + } + } + } + + cell (nr2av0x1) { + area : 0.0 ; + cell_leakage_power : 1.1 ; + leakage_power () { + when : "(b & a)" ; + value : 1.9 ; + } + leakage_power () { + when : "(!(b) & a)" ; + value : 0.4 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 0.62 ; + } + pin (b) { + direction : input ; + capacitance : 4.53 ; + } + pin (a) { + direction : input ; + capacitance : 3.26 ; + } + pin (z) { + function : "(a & !(b))" ; + direction : output ; + capacitance : 4.24 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__62) { + values ("70.9, 70.9, 70.9, 88.9, 124.3", \ + "72.3, 72.3, 72.3, 90.5, 126.2", \ + "70.3, 70.3, 70.3, 88.9, 125.1", \ + "62.4, 62.4, 62.4, 81.5, 118.7", \ + "43.6, 43.6, 43.6, 63.4, 101.7"); + } + rise_transition (inslew_load_5x5__62) { + values ("84.0, 84.0, 84.0, 115.3, 177.9", \ + "93.6, 93.6, 93.6, 124.5, 187.0", \ + "110.4, 110.4, 110.4, 141.0, 202.8", \ + "142.7, 142.7, 142.7, 172.8, 233.8", \ + "205.1, 205.1, 205.1, 235.3, 296.4"); + } + cell_fall (inslew_load_5x5__62) { + values ("71.1, 71.1, 71.1, 84.1, 107.4", \ + "83.5, 83.5, 83.5, 97.4, 122.3", \ + "102.9, 102.9, 102.9, 117.9, 145.0", \ + "137.3, 137.3, 137.3, 153.2, 182.9", \ + "201.5, 201.5, 201.5, 218.8, 251.0"); + } + fall_transition (inslew_load_5x5__62) { + values ("45.4, 45.4, 45.4, 57.4, 81.1", \ + "58.8, 58.8, 58.8, 71.0, 94.8", \ + "83.9, 83.9, 83.9, 96.3, 120.5", \ + "132.3, 132.3, 132.3, 145.0, 169.9", \ + "227.9, 227.9, 227.9, 240.9, 266.3"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__62) { + values ("31.2, 31.2, 31.2, 51.3, 88.6", \ + "39.4, 39.4, 39.4, 60.8, 100.4", \ + "52.4, 52.4, 52.4, 75.4, 117.9", \ + "76.0, 76.0, 76.0, 100.3, 146.2", \ + "121.8, 121.8, 121.8, 146.9, 195.4"); + } + rise_transition (inslew_load_5x5__62) { + values ("59.4, 59.4, 59.4, 90.9, 153.6", \ + "93.7, 93.7, 93.7, 124.7, 187.4", \ + "158.3, 158.3, 158.3, 189.9, 252.0", \ + "285.4, 285.4, 285.4, 317.4, 380.5", \ + "538.3, 538.3, 538.3, 570.5, 634.5"); + } + cell_fall (inslew_load_5x5__62) { + values ("19.6, 19.6, 19.6, 33.6, 57.1", \ + "19.2, 19.2, 19.2, 35.7, 63.2", \ + "15.2, 15.2, 15.2, 34.1, 66.6", \ + "4.8, 4.8, 4.8, 25.6, 63.0", \ + "-17.5, -17.5, -17.5, 4.5, 45.9"); + } + fall_transition (inslew_load_5x5__62) { + values ("26.1, 26.1, 26.1, 38.5, 62.3", \ + "41.8, 41.8, 41.8, 55.0, 79.6", \ + "71.3, 71.3, 71.3, 85.4, 111.6", \ + "128.9, 128.9, 128.9, 143.8, 171.9", \ + "243.3, 243.3, 243.3, 258.8, 288.5"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__62) { + values ("240.8, 240.8, 240.8, 293.8, 399.8", \ + "281.3, 281.3, 281.3, 334.3, 440.3", \ + "360.9, 360.9, 360.9, 413.9, 519.9", \ + "519.1, 519.1, 519.1, 572.1, 678.1", \ + "834.8, 834.8, 834.8, 887.8, 993.8"); + } + fall_power (energy_inslew_load_5x5__62) { + values ("262.7, 262.7, 262.7, 315.7, 421.7", \ + "329.2, 329.2, 329.2, 382.2, 488.2", \ + "460.0, 460.0, 460.0, 513.0, 618.9", \ + "719.9, 719.9, 719.9, 772.9, 878.9", \ + "1239.0, 1239.0, 1239.0, 1292.0, 1398.0"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__62) { + values ("92.0, 92.0, 92.0, 145.0, 250.9", \ + "131.6, 131.6, 131.6, 184.6, 290.5", \ + "210.8, 210.8, 210.8, 263.8, 369.8", \ + "369.3, 369.3, 369.3, 422.3, 528.2", \ + "686.2, 686.2, 686.2, 739.2, 845.2"); + } + fall_power (energy_inslew_load_5x5__62) { + values ("81.3, 81.3, 81.3, 134.3, 240.3", \ + "109.0, 109.0, 109.0, 162.0, 268.0", \ + "164.5, 164.5, 164.5, 217.4, 323.4", \ + "275.3, 275.3, 275.3, 328.3, 434.2", \ + "497.0, 497.0, 497.0, 550.0, 655.9"); + } + } + } + } + + cell (nr2av0x2) { + area : 0.0 ; + cell_leakage_power : 2.5 ; + leakage_power () { + when : "(b & a)" ; + value : 4.4 ; + } + leakage_power () { + when : "(!(b) & a)" ; + value : 1.4 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 2.9 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 1.2 ; + } + pin (b) { + direction : input ; + capacitance : 7.68 ; + } + pin (a) { + direction : input ; + capacitance : 4.50 ; + } + pin (z) { + function : "(a & !(b))" ; + direction : output ; + capacitance : 5.15 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__63) { + values ("65.6, 65.6, 65.6, 76.5, 98.4", \ + "66.5, 66.5, 66.5, 77.7, 99.6", \ + "63.2, 63.2, 63.2, 74.7, 97.1", \ + "52.2, 52.2, 52.2, 64.0, 87.0", \ + "26.6, 26.6, 26.6, 38.9, 62.8"); + } + rise_transition (inslew_load_5x5__63) { + values ("72.1, 72.1, 72.1, 90.7, 128.8", \ + "80.7, 80.7, 80.7, 99.3, 136.9", \ + "96.0, 96.0, 96.0, 114.5, 151.7", \ + "124.7, 124.7, 124.7, 143.6, 180.3", \ + "181.4, 181.4, 181.4, 199.8, 237.7"); + } + cell_fall (inslew_load_5x5__63) { + values ("75.1, 75.1, 75.1, 84.0, 100.3", \ + "89.7, 89.7, 89.7, 99.1, 116.4", \ + "112.6, 112.6, 112.6, 122.7, 141.2", \ + "154.2, 154.2, 154.2, 164.7, 184.3", \ + "232.7, 232.7, 232.7, 243.8, 265.1"); + } + fall_transition (inslew_load_5x5__63) { + values ("45.1, 45.1, 45.1, 52.6, 67.2", \ + "59.9, 59.9, 59.9, 67.5, 82.3", \ + "87.5, 87.5, 87.5, 95.2, 110.2", \ + "141.0, 141.0, 141.0, 148.7, 164.3", \ + "246.7, 246.7, 246.7, 254.6, 270.3"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__63) { + values ("22.0, 22.0, 22.0, 34.9, 58.8", \ + "28.5, 28.5, 28.5, 42.4, 68.0", \ + "38.8, 38.8, 38.8, 53.6, 81.3", \ + "57.8, 57.8, 57.8, 73.2, 102.7", \ + "94.9, 94.9, 94.9, 110.7, 141.4"); + } + rise_transition (inslew_load_5x5__63) { + values ("46.4, 46.4, 46.4, 65.2, 103.3", \ + "78.9, 78.9, 78.9, 98.1, 135.8", \ + "140.6, 140.6, 140.6, 160.1, 198.4", \ + "262.3, 262.3, 262.3, 281.9, 320.8", \ + "504.4, 504.4, 504.4, 524.2, 563.5"); + } + cell_fall (inslew_load_5x5__63) { + values ("14.0, 14.0, 14.0, 24.0, 40.5", \ + "13.5, 13.5, 13.5, 25.0, 44.5", \ + "10.4, 10.4, 10.4, 23.2, 45.8", \ + "2.8, 2.8, 2.8, 16.4, 41.6", \ + "-13.1, -13.1, -13.1, 1.0, 28.0"); + } + fall_transition (inslew_load_5x5__63) { + values ("20.4, 20.4, 20.4, 28.5, 43.3", \ + "36.0, 36.0, 36.0, 44.5, 60.3", \ + "65.7, 65.7, 65.7, 74.7, 91.5", \ + "124.0, 124.0, 124.0, 133.3, 151.2", \ + "239.9, 239.9, 239.9, 249.5, 268.1"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__63) { + values ("400.9, 400.9, 400.9, 465.3, 594.0", \ + "462.2, 462.2, 462.2, 526.6, 655.4", \ + "582.3, 582.3, 582.3, 646.7, 775.4", \ + "820.2, 820.2, 820.2, 884.6, 1013.3", \ + "1294.1, 1294.1, 1294.1, 1358.5, 1487.2"); + } + fall_power (energy_inslew_load_5x5__63) { + values ("465.3, 465.3, 465.3, 529.7, 658.4", \ + "586.3, 586.3, 586.3, 650.6, 779.4", \ + "822.5, 822.5, 822.5, 886.9, 1015.6", \ + "1291.3, 1291.3, 1291.3, 1355.6, 1484.4", \ + "2226.4, 2226.4, 2226.4, 2290.8, 2419.5"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__63) { + values ("137.9, 137.9, 137.9, 202.2, 331.0", \ + "212.8, 212.8, 212.8, 277.2, 405.9", \ + "362.7, 362.7, 362.7, 427.1, 555.8", \ + "662.5, 662.5, 662.5, 726.9, 855.6", \ + "1262.0, 1262.0, 1262.0, 1326.4, 1455.2"); + } + fall_power (energy_inslew_load_5x5__63) { + values ("120.7, 120.7, 120.7, 185.1, 313.9", \ + "175.6, 175.6, 175.6, 240.0, 368.8", \ + "285.4, 285.4, 285.4, 349.8, 478.5", \ + "505.0, 505.0, 505.0, 569.4, 698.1", \ + "944.1, 944.1, 944.1, 1008.5, 1137.2"); + } + } + } + } + + cell (nr2av0x4) { + area : 0.0 ; + cell_leakage_power : 5.6 ; + leakage_power () { + when : "(b & a)" ; + value : 10 ; + } + leakage_power () { + when : "(!(b) & a)" ; + value : 4.1 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 5.9 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 2.5 ; + } + pin (b) { + direction : input ; + capacitance : 15.73 ; + } + pin (a) { + direction : input ; + capacitance : 6.66 ; + } + pin (z) { + function : "(a & !(b))" ; + direction : output ; + capacitance : 10.76 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__64) { + values ("69.7, 69.7, 69.7, 81.3, 104.1", \ + "71.6, 71.6, 71.6, 83.3, 106.3", \ + "69.7, 69.7, 69.7, 81.7, 105.3", \ + "61.1, 61.1, 61.1, 73.6, 97.7", \ + "39.9, 39.9, 39.9, 52.9, 78.0"); + } + rise_transition (inslew_load_5x5__64) { + values ("74.0, 74.0, 74.0, 93.7, 133.3", \ + "82.7, 82.7, 82.7, 102.1, 141.4", \ + "98.1, 98.1, 98.1, 117.4, 156.3", \ + "127.0, 127.0, 127.0, 146.8, 185.1", \ + "183.9, 183.9, 183.9, 203.2, 241.6"); + } + cell_fall (inslew_load_5x5__64) { + values ("78.9, 78.9, 78.9, 88.3, 105.5", \ + "93.0, 93.0, 93.0, 102.8, 120.9", \ + "115.1, 115.1, 115.1, 125.6, 144.8", \ + "154.3, 154.3, 154.3, 165.0, 185.4", \ + "227.5, 227.5, 227.5, 239.0, 260.8"); + } + fall_transition (inslew_load_5x5__64) { + values ("48.1, 48.1, 48.1, 56.0, 71.4", \ + "62.3, 62.3, 62.3, 70.4, 85.9", \ + "89.1, 89.1, 89.1, 97.1, 112.9", \ + "140.5, 140.5, 140.5, 148.8, 165.0", \ + "242.6, 242.6, 242.6, 250.9, 267.1"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__64) { + values ("22.5, 22.5, 22.5, 36.0, 60.9", \ + "28.8, 28.8, 28.8, 43.4, 70.0", \ + "38.5, 38.5, 38.5, 54.0, 82.9", \ + "56.2, 56.2, 56.2, 72.4, 103.3", \ + "90.6, 90.6, 90.6, 107.2, 139.4"); + } + rise_transition (inslew_load_5x5__64) { + values ("46.6, 46.6, 46.6, 66.3, 106.1", \ + "78.9, 78.9, 78.9, 98.9, 138.4", \ + "139.9, 139.9, 139.9, 160.2, 200.2", \ + "259.9, 259.9, 259.9, 280.5, 321.1", \ + "498.8, 498.8, 498.8, 519.5, 560.6"); + } + cell_fall (inslew_load_5x5__64) { + values ("14.9, 14.9, 14.9, 25.3, 42.6", \ + "14.8, 14.8, 14.8, 26.8, 47.1", \ + "12.4, 12.4, 12.4, 25.7, 49.2", \ + "6.0, 6.0, 6.0, 20.3, 46.5", \ + "-7.5, -7.5, -7.5, 7.2, 35.4"); + } + fall_transition (inslew_load_5x5__64) { + values ("21.0, 21.0, 21.0, 29.5, 45.2", \ + "37.1, 37.1, 37.1, 46.0, 62.6", \ + "67.5, 67.5, 67.5, 76.9, 94.6", \ + "127.2, 127.2, 127.2, 137.0, 155.8", \ + "245.9, 245.9, 245.9, 256.0, 275.5"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__64) { + values ("780.3, 780.3, 780.3, 914.8, 1183.9", \ + "891.6, 891.6, 891.6, 1026.1, 1295.1", \ + "1109.0, 1109.0, 1109.0, 1243.5, 1512.5", \ + "1538.9, 1538.9, 1538.9, 1673.4, 1942.4", \ + "2394.2, 2394.2, 2394.2, 2528.7, 2797.7"); + } + fall_power (energy_inslew_load_5x5__64) { + values ("913.8, 913.8, 913.8, 1048.3, 1317.3", \ + "1124.0, 1124.0, 1124.0, 1258.6, 1527.6", \ + "1534.6, 1534.6, 1534.6, 1669.2, 1938.2", \ + "2347.5, 2347.5, 2347.5, 2482.0, 2751.0", \ + "3968.8, 3968.8, 3968.8, 4103.3, 4372.3"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__64) { + values ("278.8, 278.8, 278.8, 413.3, 682.3", \ + "426.0, 426.0, 426.0, 560.5, 829.5", \ + "720.4, 720.4, 720.4, 854.9, 1123.9", \ + "1309.1, 1309.1, 1309.1, 1443.6, 1712.6", \ + "2486.6, 2486.6, 2486.6, 2621.1, 2890.1"); + } + fall_power (energy_inslew_load_5x5__64) { + values ("249.5, 249.5, 249.5, 384.0, 653.1", \ + "361.6, 361.6, 361.6, 496.1, 765.2", \ + "585.8, 585.8, 585.8, 720.3, 989.3", \ + "1034.2, 1034.2, 1034.2, 1168.7, 1437.7", \ + "1930.9, 1930.9, 1930.9, 2065.5, 2334.5"); + } + } + } + } + + cell (nr2av1x05) { + area : 0.0 ; + cell_leakage_power : 2.9 ; + leakage_power () { + when : "(b & a)" ; + value : 5.6 ; + } + leakage_power () { + when : "(!(b) & a)" ; + value : 4.9 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 0.72 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 0.32 ; + } + pin (b) { + direction : input ; + capacitance : 3.40 ; + } + pin (a) { + direction : input ; + capacitance : 2.77 ; + } + pin (z) { + function : "(a & !(b))" ; + direction : output ; + capacitance : 3.61 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__65) { + values ("83.0, 83.0, 83.0, 108.7, 159.9", \ + "89.2, 89.2, 89.2, 115.4, 166.8", \ + "95.8, 95.8, 95.8, 122.1, 174.1", \ + "103.9, 103.9, 103.9, 130.8, 183.2", \ + "117.1, 117.1, 117.1, 144.2, 197.8"); + } + rise_transition (inslew_load_5x5__65) { + values ("106.9, 106.9, 106.9, 153.8, 248.7", \ + "124.7, 124.7, 124.7, 171.7, 266.0", \ + "154.9, 154.9, 154.9, 201.5, 295.7", \ + "211.6, 211.6, 211.6, 257.8, 351.0", \ + "322.9, 322.9, 322.9, 368.4, 460.4"); + } + cell_fall (inslew_load_5x5__65) { + values ("54.6, 54.6, 54.6, 67.3, 89.1", \ + "61.1, 61.1, 61.1, 74.9, 98.7", \ + "69.2, 69.2, 69.2, 84.6, 111.2", \ + "81.6, 81.6, 81.6, 98.3, 128.4", \ + "102.3, 102.3, 102.3, 121.0, 154.7"); + } + fall_transition (inslew_load_5x5__65) { + values ("36.0, 36.0, 36.0, 46.6, 66.9", \ + "46.0, 46.0, 46.0, 57.1, 77.9", \ + "65.0, 65.0, 65.0, 76.5, 98.2", \ + "101.9, 101.9, 101.9, 113.9, 136.8", \ + "174.8, 174.8, 174.8, 187.3, 211.1"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__65) { + values ("47.3, 47.3, 47.3, 74.9, 127.8", \ + "67.7, 67.7, 67.7, 96.5, 151.0", \ + "103.5, 103.5, 103.5, 133.5, 190.5", \ + "171.7, 171.7, 171.7, 202.7, 262.4", \ + "306.0, 306.0, 306.0, 337.8, 399.8"); + } + rise_transition (inslew_load_5x5__65) { + values ("85.9, 85.9, 85.9, 133.2, 229.8", \ + "138.4, 138.4, 138.4, 186.2, 280.5", \ + "236.8, 236.8, 236.8, 283.8, 379.2", \ + "429.1, 429.1, 429.1, 476.4, 570.3", \ + "811.4, 811.4, 811.4, 858.8, 953.3"); + } + cell_fall (inslew_load_5x5__65) { + values ("12.1, 12.1, 12.1, 25.1, 46.2", \ + "4.7, 4.7, 4.7, 20.8, 46.6", \ + "-13.5, -13.5, -13.5, 5.9, 37.9", \ + "-53.2, -53.2, -53.2, -30.6, 8.1", \ + "-135.1, -135.1, -135.1, -110.1, -65.0"); + } + fall_transition (inslew_load_5x5__65) { + values ("22.1, 22.1, 22.1, 33.0, 53.4", \ + "32.8, 32.8, 32.8, 44.9, 66.6", \ + "52.6, 52.6, 52.6, 66.2, 90.3", \ + "90.6, 90.6, 90.6, 105.6, 132.7", \ + "165.8, 165.8, 165.8, 181.8, 211.6"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__65) { + values ("180.3, 180.3, 180.3, 225.4, 315.6", \ + "215.7, 215.7, 215.7, 260.7, 350.9", \ + "285.0, 285.0, 285.0, 330.1, 420.3", \ + "422.8, 422.8, 422.8, 467.9, 558.0", \ + "697.3, 697.3, 697.3, 742.4, 832.5"); + } + fall_power (energy_inslew_load_5x5__65) { + values ("177.2, 177.2, 177.2, 222.3, 312.5", \ + "222.3, 222.3, 222.3, 267.4, 357.6", \ + "311.2, 311.2, 311.2, 356.2, 446.4", \ + "488.0, 488.0, 488.0, 533.1, 623.3", \ + "841.2, 841.2, 841.2, 886.3, 976.5"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__65) { + values ("82.7, 82.7, 82.7, 127.8, 218.0", \ + "120.0, 120.0, 120.0, 165.1, 255.3", \ + "194.7, 194.7, 194.7, 239.8, 330.0", \ + "344.1, 344.1, 344.1, 389.2, 479.4", \ + "642.9, 642.9, 642.9, 688.0, 778.2"); + } + fall_power (energy_inslew_load_5x5__65) { + values ("58.1, 58.1, 58.1, 103.2, 193.3", \ + "71.3, 71.3, 71.3, 116.4, 206.6", \ + "97.8, 97.8, 97.8, 142.9, 233.1", \ + "150.8, 150.8, 150.8, 195.9, 286.0", \ + "256.7, 256.7, 256.7, 301.8, 392.0"); + } + } + } + } + + cell (nr2v0x05) { + area : 0.0 ; + cell_leakage_power : 0.49 ; + leakage_power () { + when : "(!(b) & a)" ; + value : 0.44 ; + } + leakage_power () { + when : "b" ; + value : 1 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 6.7e-05 ; + } + pin (b) { + direction : input ; + capacitance : 3.31 ; + } + pin (a) { + direction : input ; + capacitance : 3.44 ; + } + pin (z) { + function : "(!(b) & !(a))" ; + direction : output ; + capacitance : 2.87 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__66) { + values ("37.6, 37.6, 37.6, 52.5, 81.7", \ + "35.2, 35.2, 35.2, 50.8, 81.0", \ + "29.0, 29.0, 29.0, 45.5, 77.1", \ + "14.7, 14.7, 14.7, 32.1, 65.8", \ + "-15.7, -15.7, -15.7, 2.5, 38.0"); + } + rise_transition (inslew_load_5x5__66) { + values ("84.0, 84.0, 84.0, 110.0, 162.6", \ + "109.0, 109.0, 109.0, 134.5, 186.1", \ + "157.3, 157.3, 157.3, 182.9, 234.8", \ + "254.2, 254.2, 254.2, 280.0, 331.2", \ + "447.7, 447.7, 447.7, 473.6, 525.2"); + } + cell_fall (inslew_load_5x5__66) { + values ("32.1, 32.1, 32.1, 43.6, 64.5", \ + "42.4, 42.4, 42.4, 55.3, 78.7", \ + "59.4, 59.4, 59.4, 73.5, 99.7", \ + "90.6, 90.6, 90.6, 105.7, 134.4", \ + "151.7, 151.7, 151.7, 167.3, 197.7"); + } + fall_transition (inslew_load_5x5__66) { + values ("37.3, 37.3, 37.3, 48.6, 71.0", \ + "61.3, 61.3, 61.3, 72.9, 95.4", \ + "106.7, 106.7, 106.7, 118.6, 141.8", \ + "195.9, 195.9, 195.9, 208.1, 232.0", \ + "373.1, 373.1, 373.1, 385.5, 410.0"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__66) { + values ("25.9, 25.9, 25.9, 42.7, 73.5", \ + "31.5, 31.5, 31.5, 49.8, 83.1", \ + "40.0, 40.0, 40.0, 59.8, 96.2", \ + "55.1, 55.1, 55.1, 76.0, 115.5", \ + "84.1, 84.1, 84.1, 105.8, 147.5"); + } + rise_transition (inslew_load_5x5__66) { + values ("54.3, 54.3, 54.3, 80.8, 134.3", \ + "85.7, 85.7, 85.7, 112.6, 165.6", \ + "145.6, 145.6, 145.6, 173.0, 226.7", \ + "263.6, 263.6, 263.6, 291.4, 346.2", \ + "498.8, 498.8, 498.8, 526.8, 582.3"); + } + cell_fall (inslew_load_5x5__66) { + values ("19.4, 19.4, 19.4, 32.6, 54.8", \ + "20.4, 20.4, 20.4, 35.7, 61.6", \ + "19.6, 19.6, 19.6, 36.8, 67.0", \ + "15.8, 15.8, 15.8, 34.5, 68.6", \ + "7.0, 7.0, 7.0, 26.6, 63.7"); + } + fall_transition (inslew_load_5x5__66) { + values ("26.3, 26.3, 26.3, 38.0, 60.4", \ + "43.3, 43.3, 43.3, 55.7, 78.8", \ + "75.5, 75.5, 75.5, 88.5, 113.1", \ + "138.5, 138.5, 138.5, 152.1, 178.2", \ + "263.7, 263.7, 263.7, 277.7, 305.0"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__66) { + values ("106.5, 106.5, 106.5, 142.4, 214.1", \ + "132.9, 132.9, 132.9, 168.7, 240.5", \ + "185.5, 185.5, 185.5, 221.4, 293.1", \ + "290.9, 290.9, 290.9, 326.8, 398.5", \ + "501.6, 501.6, 501.6, 537.5, 609.2"); + } + fall_power (energy_inslew_load_5x5__66) { + values ("99.4, 99.4, 99.4, 135.2, 207.0", \ + "140.1, 140.1, 140.1, 175.9, 247.7", \ + "221.4, 221.4, 221.4, 257.3, 329.0", \ + "384.2, 384.2, 384.2, 420.1, 491.8", \ + "709.7, 709.7, 709.7, 745.6, 817.3"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__66) { + values ("64.1, 64.1, 64.1, 100.0, 171.7", \ + "92.8, 92.8, 92.8, 128.6, 200.3", \ + "150.1, 150.1, 150.1, 185.9, 257.7", \ + "264.7, 264.7, 264.7, 300.6, 372.3", \ + "493.9, 493.9, 493.9, 529.8, 601.5"); + } + fall_power (energy_inslew_load_5x5__66) { + values ("59.7, 59.7, 59.7, 95.6, 167.3", \ + "83.1, 83.1, 83.1, 119.0, 190.7", \ + "130.0, 130.0, 130.0, 165.8, 237.6", \ + "223.7, 223.7, 223.7, 259.5, 331.3", \ + "411.0, 411.0, 411.0, 446.9, 518.6"); + } + } + } + } + + cell (nr2v0x1) { + area : 0.0 ; + cell_leakage_power : 0.7 ; + leakage_power () { + when : "(!(b) & a)" ; + value : 0.62 ; + } + leakage_power () { + when : "b" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 0.00012 ; + } + pin (b) { + direction : input ; + capacitance : 4.30 ; + } + pin (a) { + direction : input ; + capacitance : 4.21 ; + } + pin (z) { + function : "(!(b) & !(a))" ; + direction : output ; + capacitance : 3.68 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__67) { + values ("44.3, 44.3, 44.3, 60.2, 91.4", \ + "44.2, 44.2, 44.2, 60.6, 92.7", \ + "42.5, 42.5, 42.5, 59.6, 92.8", \ + "37.4, 37.4, 37.4, 55.4, 90.3", \ + "25.8, 25.8, 25.8, 44.5, 81.1"); + } + rise_transition (inslew_load_5x5__67) { + values ("90.6, 90.6, 90.6, 117.4, 171.4", \ + "118.3, 118.3, 118.3, 144.6, 197.8", \ + "172.1, 172.1, 172.1, 199.2, 251.1", \ + "279.8, 279.8, 279.8, 306.0, 358.1", \ + "494.9, 494.9, 494.9, 521.1, 573.4"); + } + cell_fall (inslew_load_5x5__67) { + values ("29.7, 29.7, 29.7, 40.6, 60.3", \ + "37.6, 37.6, 37.6, 50.0, 72.3", \ + "49.7, 49.7, 49.7, 63.5, 88.8", \ + "71.5, 71.5, 71.5, 86.2, 114.1", \ + "113.5, 113.5, 113.5, 128.9, 158.7"); + } + fall_transition (inslew_load_5x5__67) { + values ("34.6, 34.6, 34.6, 45.1, 65.7", \ + "56.4, 56.4, 56.4, 67.2, 88.2", \ + "97.7, 97.7, 97.7, 108.9, 130.6", \ + "178.7, 178.7, 178.7, 190.2, 212.8", \ + "339.7, 339.7, 339.7, 351.4, 374.7"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__67) { + values ("28.4, 28.4, 28.4, 46.2, 79.0", \ + "36.4, 36.4, 36.4, 55.4, 90.3", \ + "49.2, 49.2, 49.2, 69.5, 107.1", \ + "72.7, 72.7, 72.7, 94.0, 134.4", \ + "118.5, 118.5, 118.5, 140.4, 182.9"); + } + rise_transition (inslew_load_5x5__67) { + values ("55.3, 55.3, 55.3, 82.7, 137.0", \ + "89.5, 89.5, 89.5, 116.6, 171.3", \ + "154.1, 154.1, 154.1, 181.7, 235.8", \ + "281.2, 281.2, 281.2, 309.0, 364.0", \ + "534.0, 534.0, 534.0, 562.1, 617.8"); + } + cell_fall (inslew_load_5x5__67) { + values ("17.6, 17.6, 17.6, 30.2, 51.3", \ + "16.8, 16.8, 16.8, 31.6, 56.5", \ + "12.5, 12.5, 12.5, 29.4, 58.6", \ + "1.9, 1.9, 1.9, 20.3, 53.7", \ + "-20.4, -20.4, -20.4, -1.0, 35.4"); + } + fall_transition (inslew_load_5x5__67) { + values ("24.3, 24.3, 24.3, 35.3, 56.1", \ + "39.9, 39.9, 39.9, 51.6, 73.3", \ + "69.3, 69.3, 69.3, 81.8, 104.9", \ + "126.9, 126.9, 126.9, 140.0, 164.7", \ + "241.3, 241.3, 241.3, 254.8, 280.8"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__67) { + values ("145.8, 145.8, 145.8, 191.9, 284.0", \ + "183.5, 183.5, 183.5, 229.6, 321.7", \ + "258.9, 258.9, 258.9, 305.0, 397.1", \ + "409.7, 409.7, 409.7, 455.8, 547.9", \ + "711.3, 711.3, 711.3, 757.4, 849.5"); + } + fall_power (energy_inslew_load_5x5__67) { + values ("125.1, 125.1, 125.1, 171.1, 263.2", \ + "173.5, 173.5, 173.5, 219.5, 311.6", \ + "270.3, 270.3, 270.3, 316.3, 408.4", \ + "463.8, 463.8, 463.8, 509.9, 602.0", \ + "851.0, 851.0, 851.0, 897.0, 989.1"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__67) { + values ("85.0, 85.0, 85.0, 131.1, 223.2", \ + "124.7, 124.7, 124.7, 170.7, 262.8", \ + "203.9, 203.9, 203.9, 249.9, 342.0", \ + "362.4, 362.4, 362.4, 408.4, 500.5", \ + "679.3, 679.3, 679.3, 725.3, 817.4"); + } + fall_power (energy_inslew_load_5x5__67) { + values ("74.4, 74.4, 74.4, 120.4, 212.5", \ + "102.1, 102.1, 102.1, 148.1, 240.2", \ + "157.5, 157.5, 157.5, 203.6, 295.6", \ + "268.4, 268.4, 268.4, 314.4, 406.5", \ + "490.1, 490.1, 490.1, 536.1, 628.2"); + } + } + } + } + + cell (nr2v0x4) { + area : 0.0 ; + cell_leakage_power : 2.8 ; + leakage_power () { + when : "(!(b) & a)" ; + value : 2.5 ; + } + leakage_power () { + when : "b" ; + value : 5.9 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 0.0007 ; + } + pin (b) { + direction : input ; + capacitance : 15.86 ; + } + pin (a) { + direction : input ; + capacitance : 16.27 ; + } + pin (z) { + function : "(!(b) & !(a))" ; + direction : output ; + capacitance : 10.95 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__68) { + values ("39.1, 39.1, 39.1, 51.0, 74.4", \ + "37.8, 37.8, 37.8, 50.2, 74.4", \ + "33.9, 33.9, 33.9, 46.9, 72.1", \ + "24.5, 24.5, 24.5, 38.2, 64.8", \ + "4.4, 4.4, 4.4, 18.6, 46.4"); + } + rise_transition (inslew_load_5x5__68) { + values ("82.5, 82.5, 82.5, 102.3, 142.3", \ + "108.8, 108.8, 108.8, 128.2, 167.5", \ + "159.6, 159.6, 159.6, 179.1, 218.7", \ + "261.7, 261.7, 261.7, 281.2, 320.0", \ + "465.5, 465.5, 465.5, 485.0, 524.0"); + } + cell_fall (inslew_load_5x5__68) { + values ("27.5, 27.5, 27.5, 36.3, 52.1", \ + "36.0, 36.0, 36.0, 45.9, 63.9", \ + "49.8, 49.8, 49.8, 60.6, 80.8", \ + "75.1, 75.1, 75.1, 86.7, 108.7", \ + "124.7, 124.7, 124.7, 136.7, 159.9"); + } + fall_transition (inslew_load_5x5__68) { + values ("30.9, 30.9, 30.9, 38.9, 54.3", \ + "52.7, 52.7, 52.7, 60.9, 76.6", \ + "94.0, 94.0, 94.0, 102.4, 118.8", \ + "175.1, 175.1, 175.1, 183.8, 200.7", \ + "336.5, 336.5, 336.5, 345.3, 362.7"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__68) { + values ("22.9, 22.9, 22.9, 36.6, 61.8", \ + "29.5, 29.5, 29.5, 44.2, 71.2", \ + "39.8, 39.8, 39.8, 55.5, 84.7", \ + "58.8, 58.8, 58.8, 75.1, 106.3", \ + "95.7, 95.7, 95.7, 112.4, 145.1"); + } + rise_transition (inslew_load_5x5__68) { + values ("47.4, 47.4, 47.4, 67.4, 107.9", \ + "80.0, 80.0, 80.0, 100.4, 140.5", \ + "141.7, 141.7, 141.7, 162.4, 203.1", \ + "263.3, 263.3, 263.3, 284.2, 325.5", \ + "505.3, 505.3, 505.3, 526.3, 568.0"); + } + cell_fall (inslew_load_5x5__68) { + values ("14.8, 14.8, 14.8, 25.3, 42.7", \ + "14.5, 14.5, 14.5, 26.6, 47.1", \ + "11.6, 11.6, 11.6, 25.0, 48.8", \ + "4.1, 4.1, 4.1, 18.6, 45.2", \ + "-11.5, -11.5, -11.5, 3.4, 32.1"); + } + fall_transition (inslew_load_5x5__68) { + values ("21.2, 21.2, 21.2, 29.8, 45.7", \ + "37.0, 37.0, 37.0, 46.1, 62.9", \ + "67.0, 67.0, 67.0, 76.6, 94.6", \ + "125.9, 125.9, 125.9, 135.9, 155.0", \ + "243.0, 243.0, 243.0, 253.2, 273.2"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__68) { + values ("525.7, 525.7, 525.7, 662.6, 936.3", \ + "666.7, 666.7, 666.7, 803.6, 1077.3", \ + "948.6, 948.6, 948.6, 1085.5, 1359.2", \ + "1512.4, 1512.4, 1512.4, 1649.3, 1923.0", \ + "2640.0, 2640.0, 2640.0, 2776.9, 3050.6"); + } + fall_power (energy_inslew_load_5x5__68) { + values ("447.4, 447.4, 447.4, 584.3, 858.0", \ + "636.8, 636.8, 636.8, 773.6, 1047.4", \ + "1015.5, 1015.5, 1015.5, 1152.3, 1426.1", \ + "1772.9, 1772.9, 1772.9, 1909.8, 2183.5", \ + "3287.8, 3287.8, 3287.8, 3424.7, 3698.4"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__68) { + values ("283.7, 283.7, 283.7, 420.5, 694.3", \ + "433.4, 433.4, 433.4, 570.2, 844.0", \ + "732.7, 732.7, 732.7, 869.6, 1143.3", \ + "1331.5, 1331.5, 1331.5, 1468.4, 1742.1", \ + "2529.0, 2529.0, 2529.0, 2665.9, 2939.6"); + } + fall_power (energy_inslew_load_5x5__68) { + values ("250.6, 250.6, 250.6, 387.5, 661.2", \ + "361.4, 361.4, 361.4, 498.3, 772.0", \ + "583.1, 583.1, 583.1, 719.9, 993.7", \ + "1026.4, 1026.4, 1026.4, 1163.3, 1437.0", \ + "1913.0, 1913.0, 1913.0, 2049.9, 2323.6"); + } + } + } + } + + cell (nr2v1x05) { + area : 0.0 ; + cell_leakage_power : 0.35 ; + leakage_power () { + when : "(!(b) & a)" ; + value : 0.32 ; + } + leakage_power () { + when : "b" ; + value : 0.72 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 0.00013 ; + } + pin (b) { + direction : input ; + capacitance : 2.94 ; + } + pin (a) { + direction : input ; + capacitance : 3.04 ; + } + pin (z) { + function : "(!(b) & !(a))" ; + direction : output ; + capacitance : 2.84 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__69) { + values ("54.3, 54.3, 54.3, 75.0, 115.8", \ + "62.1, 62.1, 62.1, 83.4, 124.7", \ + "76.3, 76.3, 76.3, 97.9, 140.4", \ + "103.8, 103.8, 103.8, 125.9, 169.1", \ + "158.0, 158.0, 158.0, 180.5, 224.7"); + } + rise_transition (inslew_load_5x5__69) { + values ("111.1, 111.1, 111.1, 147.9, 222.1", \ + "152.9, 152.9, 152.9, 189.2, 262.6", \ + "234.3, 234.3, 234.3, 270.1, 342.3", \ + "396.8, 396.8, 396.8, 432.2, 503.2", \ + "716.8, 716.8, 716.8, 752.4, 827.3"); + } + cell_fall (inslew_load_5x5__69) { + values ("20.4, 20.4, 20.4, 31.0, 49.4", \ + "21.1, 21.1, 21.1, 33.5, 55.0", \ + "19.8, 19.8, 19.8, 33.8, 58.9", \ + "14.9, 14.9, 14.9, 30.2, 58.6", \ + "3.8, 3.8, 3.8, 19.9, 50.7"); + } + fall_transition (inslew_load_5x5__69) { + values ("28.7, 28.7, 28.7, 38.1, 56.2", \ + "45.2, 45.2, 45.2, 55.2, 74.1", \ + "76.8, 76.8, 76.8, 87.4, 107.5", \ + "139.1, 139.1, 139.1, 150.2, 171.6", \ + "262.8, 262.8, 262.8, 274.3, 296.7"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__69) { + values ("39.6, 39.6, 39.6, 61.9, 104.1", \ + "56.8, 56.8, 56.8, 80.1, 123.9", \ + "86.9, 86.9, 86.9, 111.2, 157.4", \ + "144.3, 144.3, 144.3, 169.5, 218.0", \ + "257.5, 257.5, 257.5, 283.3, 333.7"); + } + rise_transition (inslew_load_5x5__69) { + values ("73.9, 73.9, 73.9, 111.4, 186.8", \ + "122.0, 122.0, 122.0, 159.2, 233.8", \ + "212.3, 212.3, 212.3, 249.3, 323.4", \ + "389.1, 389.1, 389.1, 426.5, 500.7", \ + "740.9, 740.9, 740.9, 778.5, 853.3"); + } + cell_fall (inslew_load_5x5__69) { + values ("11.7, 11.7, 11.7, 23.6, 43.1", \ + "5.2, 5.2, 5.2, 19.8, 43.5", \ + "-10.5, -10.5, -10.5, 6.6, 35.6", \ + "-44.6, -44.6, -44.6, -25.1, 9.2", \ + "-114.4, -114.4, -114.4, -93.2, -54.3"); + } + fall_transition (inslew_load_5x5__69) { + values ("21.6, 21.6, 21.6, 31.5, 49.9", \ + "33.3, 33.3, 33.3, 44.2, 63.8", \ + "55.2, 55.2, 55.2, 67.2, 88.9", \ + "97.8, 97.8, 97.8, 110.8, 134.8", \ + "182.2, 182.2, 182.2, 196.0, 221.9"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__69) { + values ("103.8, 103.8, 103.8, 139.3, 210.3", \ + "138.4, 138.4, 138.4, 173.9, 244.9", \ + "207.7, 207.7, 207.7, 243.3, 314.3", \ + "346.4, 346.4, 346.4, 381.9, 452.9", \ + "623.7, 623.7, 623.7, 659.2, 730.2"); + } + fall_power (energy_inslew_load_5x5__69) { + values ("77.2, 77.2, 77.2, 112.7, 183.8", \ + "104.9, 104.9, 104.9, 140.4, 211.4", \ + "160.1, 160.1, 160.1, 195.6, 266.6", \ + "270.6, 270.6, 270.6, 306.1, 377.1", \ + "491.5, 491.5, 491.5, 527.1, 598.1"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__69) { + values ("69.4, 69.4, 69.4, 104.9, 175.9", \ + "103.1, 103.1, 103.1, 138.6, 209.7", \ + "170.7, 170.7, 170.7, 206.2, 277.2", \ + "305.8, 305.8, 305.8, 341.3, 412.3", \ + "576.0, 576.0, 576.0, 611.5, 682.5"); + } + fall_power (energy_inslew_load_5x5__69) { + values ("49.7, 49.7, 49.7, 85.2, 156.2", \ + "64.0, 64.0, 64.0, 99.5, 170.5", \ + "92.6, 92.6, 92.6, 128.1, 199.1", \ + "149.8, 149.8, 149.8, 185.3, 256.3", \ + "264.1, 264.1, 264.1, 299.6, 370.7"); + } + } + } + } + + cell (nr3abv0x05) { + area : 0.0 ; + cell_leakage_power : 5.5 ; + leakage_power () { + when : "(c & b & a)" ; + value : 11 ; + } + leakage_power () { + when : "(!(c) & b & a)" ; + value : 9.7 ; + } + leakage_power () { + when : "(!((a & b)) & c)" ; + value : 1 ; + } + leakage_power () { + when : "(!((a & b)) & !(c))" ; + value : 0.44 ; + } + pin (c) { + direction : input ; + capacitance : 3.69 ; + } + pin (b) { + direction : input ; + capacitance : 3.64 ; + } + pin (a) { + direction : input ; + capacitance : 3.11 ; + } + pin (z) { + function : "(a & b & !(c))" ; + direction : output ; + capacitance : 3.33 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__70) { + values ("65.1, 65.1, 65.1, 82.1, 115.6", \ + "59.9, 59.9, 59.9, 77.1, 110.9", \ + "44.8, 44.8, 44.8, 62.5, 96.6", \ + "9.7, 9.7, 9.7, 27.8, 62.8", \ + "-65.6, -65.6, -65.6, -46.8, -10.7"); + } + rise_transition (inslew_load_5x5__70) { + values ("83.3, 83.3, 83.3, 113.7, 175.1", \ + "89.1, 89.1, 89.1, 119.4, 180.7", \ + "99.8, 99.8, 99.8, 129.9, 190.6", \ + "120.6, 120.6, 120.6, 150.2, 210.2", \ + "159.9, 159.9, 159.9, 189.8, 250.0"); + } + cell_fall (inslew_load_5x5__70) { + values ("100.9, 100.9, 100.9, 115.7, 142.4", \ + "127.9, 127.9, 127.9, 143.5, 172.0", \ + "174.5, 174.5, 174.5, 190.9, 221.7", \ + "262.1, 262.1, 262.1, 279.5, 312.2", \ + "432.9, 432.9, 432.9, 451.2, 486.1"); + } + fall_transition (inslew_load_5x5__70) { + values ("67.1, 67.1, 67.1, 80.4, 106.3", \ + "89.7, 89.7, 89.7, 103.2, 129.4", \ + "131.7, 131.7, 131.7, 145.5, 172.2", \ + "213.5, 213.5, 213.5, 227.4, 254.8", \ + "375.6, 375.6, 375.6, 389.7, 417.4"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__70) { + values ("63.8, 63.8, 63.8, 80.9, 114.2", \ + "61.9, 61.9, 61.9, 79.1, 112.8", \ + "53.2, 53.2, 53.2, 70.9, 105.0", \ + "31.8, 31.8, 31.8, 50.0, 85.2", \ + "-15.3, -15.3, -15.3, 3.7, 40.2"); + } + rise_transition (inslew_load_5x5__70) { + values ("80.4, 80.4, 80.4, 110.9, 172.4", \ + "87.3, 87.3, 87.3, 117.6, 179.0", \ + "100.1, 100.1, 100.1, 130.1, 190.8", \ + "124.7, 124.7, 124.7, 154.3, 214.1", \ + "171.7, 171.7, 171.7, 201.5, 261.9"); + } + cell_fall (inslew_load_5x5__70) { + values ("86.1, 86.1, 86.1, 100.4, 126.2", \ + "105.9, 105.9, 105.9, 121.0, 148.5", \ + "138.6, 138.6, 138.6, 154.8, 184.5", \ + "199.0, 199.0, 199.0, 216.0, 248.0", \ + "315.2, 315.2, 315.2, 333.2, 367.4"); + } + fall_transition (inslew_load_5x5__70) { + values ("57.4, 57.4, 57.4, 70.6, 96.5", \ + "76.2, 76.2, 76.2, 89.5, 115.6", \ + "110.8, 110.8, 110.8, 124.4, 150.8", \ + "177.7, 177.7, 177.7, 191.7, 218.9", \ + "310.4, 310.4, 310.4, 324.4, 352.1"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__70) { + values ("28.7, 28.7, 28.7, 47.8, 83.3", \ + "34.6, 34.6, 34.6, 55.4, 93.3", \ + "43.3, 43.3, 43.3, 65.9, 107.4", \ + "58.5, 58.5, 58.5, 82.6, 127.7", \ + "87.6, 87.6, 87.6, 112.6, 160.7"); + } + rise_transition (inslew_load_5x5__70) { + values ("58.6, 58.6, 58.6, 89.8, 151.7", \ + "90.1, 90.1, 90.1, 121.2, 182.8", \ + "150.0, 150.0, 150.0, 181.7, 243.9", \ + "268.1, 268.1, 268.1, 300.3, 363.7", \ + "503.3, 503.3, 503.3, 535.8, 600.2"); + } + cell_fall (inslew_load_5x5__70) { + values ("21.7, 21.7, 21.7, 36.5, 61.5", \ + "23.1, 23.1, 23.1, 40.2, 69.2", \ + "22.5, 22.5, 22.5, 42.0, 75.9", \ + "18.9, 18.9, 18.9, 40.2, 78.9", \ + "10.2, 10.2, 10.2, 32.8, 75.2"); + } + fall_transition (inslew_load_5x5__70) { + values ("28.3, 28.3, 28.3, 41.7, 67.7", \ + "45.4, 45.4, 45.4, 59.5, 86.1", \ + "77.6, 77.6, 77.6, 92.6, 120.7", \ + "140.8, 140.8, 140.8, 156.4, 186.3", \ + "266.0, 266.0, 266.0, 282.2, 313.6"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__70) { + values ("218.2, 218.2, 218.2, 259.8, 343.2", \ + "241.9, 241.9, 241.9, 283.6, 366.9", \ + "288.9, 288.9, 288.9, 330.6, 413.9", \ + "382.0, 382.0, 382.0, 423.7, 507.0", \ + "567.4, 567.4, 567.4, 609.1, 692.4"); + } + fall_power (energy_inslew_load_5x5__70) { + values ("283.3, 283.3, 283.3, 324.9, 408.3", \ + "368.1, 368.1, 368.1, 409.8, 493.1", \ + "533.7, 533.7, 533.7, 575.3, 658.7", \ + "862.0, 862.0, 862.0, 903.7, 987.0", \ + "1517.2, 1517.2, 1517.2, 1558.9, 1642.2"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__70) { + values ("191.7, 191.7, 191.7, 233.4, 316.7", \ + "218.9, 218.9, 218.9, 260.6, 343.9", \ + "272.4, 272.4, 272.4, 314.1, 397.4", \ + "378.6, 378.6, 378.6, 420.2, 503.6", \ + "590.4, 590.4, 590.4, 632.0, 715.4"); + } + fall_power (energy_inslew_load_5x5__70) { + values ("238.0, 238.0, 238.0, 279.6, 363.0", \ + "305.7, 305.7, 305.7, 347.4, 430.7", \ + "437.6, 437.6, 437.6, 479.2, 562.6", \ + "699.3, 699.3, 699.3, 740.9, 824.3", \ + "1221.4, 1221.4, 1221.4, 1263.0, 1346.4"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__70) { + values ("69.9, 69.9, 69.9, 111.6, 194.9", \ + "98.6, 98.6, 98.6, 140.2, 223.6", \ + "155.9, 155.9, 155.9, 197.5, 280.9", \ + "270.5, 270.5, 270.5, 312.2, 395.5", \ + "499.8, 499.8, 499.8, 541.4, 624.8"); + } + fall_power (energy_inslew_load_5x5__70) { + values ("65.5, 65.5, 65.5, 107.2, 190.5", \ + "88.9, 88.9, 88.9, 130.6, 213.9", \ + "135.8, 135.8, 135.8, 177.4, 260.8", \ + "229.5, 229.5, 229.5, 271.1, 354.5", \ + "416.8, 416.8, 416.8, 458.5, 541.8"); + } + } + } + } + + cell (nr3av0x05) { + area : 0.0 ; + cell_leakage_power : 0.99 ; + leakage_power () { + when : "(!(c) & b & a)" ; + value : 1 ; + } + leakage_power () { + when : "(a & c)" ; + value : 1.9 ; + } + leakage_power () { + when : "(!(c) & !(b) & a)" ; + value : 0.4 ; + } + leakage_power () { + when : "(c & b & !(a))" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(a) & (b ^ c))" ; + value : 0.62 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 0.57 ; + } + pin (c) { + direction : input ; + capacitance : 4.19 ; + } + pin (b) { + direction : input ; + capacitance : 4.22 ; + } + pin (a) { + direction : input ; + capacitance : 3.32 ; + } + pin (z) { + function : "(a & !(b) & !(c))" ; + direction : output ; + capacitance : 4.22 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__71) { + values ("118.9, 118.9, 118.9, 145.9, 199.9", \ + "118.8, 118.8, 118.8, 145.8, 199.9", \ + "113.5, 113.5, 113.5, 141.1, 195.4", \ + "99.3, 99.3, 99.3, 127.0, 182.1", \ + "69.3, 69.3, 69.3, 97.3, 152.8"); + } + rise_transition (inslew_load_5x5__71) { + values ("164.4, 164.4, 164.4, 211.0, 304.4", \ + "173.7, 173.7, 173.7, 219.9, 313.1", \ + "189.6, 189.6, 189.6, 235.7, 328.3", \ + "218.3, 218.3, 218.3, 264.4, 357.0", \ + "274.1, 274.1, 274.1, 319.9, 412.2"); + } + cell_fall (inslew_load_5x5__71) { + values ("90.8, 90.8, 90.8, 106.6, 136.2", \ + "107.8, 107.8, 107.8, 124.5, 155.4", \ + "135.1, 135.1, 135.1, 152.9, 186.0", \ + "183.2, 183.2, 183.2, 202.3, 238.2", \ + "274.5, 274.5, 274.5, 294.5, 333.4"); + } + fall_transition (inslew_load_5x5__71) { + values ("62.2, 62.2, 62.2, 78.6, 111.7", \ + "79.1, 79.1, 79.1, 95.6, 128.3", \ + "110.1, 110.1, 110.1, 126.8, 159.5", \ + "169.6, 169.6, 169.6, 186.5, 219.6", \ + "286.4, 286.4, 286.4, 303.6, 337.2"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__71) { + values ("71.7, 71.7, 71.7, 99.4, 154.1", \ + "75.3, 75.3, 75.3, 103.6, 159.0", \ + "79.7, 79.7, 79.7, 108.9, 166.0", \ + "86.5, 86.5, 86.5, 116.9, 175.9", \ + "97.8, 97.8, 97.8, 129.3, 191.0"); + } + rise_transition (inslew_load_5x5__71) { + values ("129.6, 129.6, 129.6, 176.3, 270.6", \ + "160.7, 160.7, 160.7, 206.8, 300.1", \ + "220.9, 220.9, 220.9, 266.1, 357.6", \ + "339.2, 339.2, 339.2, 386.1, 475.7", \ + "577.0, 577.0, 577.0, 621.8, 711.8"); + } + cell_fall (inslew_load_5x5__71) { + values ("39.4, 39.4, 39.4, 55.4, 84.5", \ + "46.8, 46.8, 46.8, 65.1, 97.9", \ + "55.5, 55.5, 55.5, 76.4, 114.1", \ + "67.7, 67.7, 67.7, 91.0, 134.0", \ + "88.6, 88.6, 88.6, 113.6, 161.0"); + } + fall_transition (inslew_load_5x5__71) { + values ("42.1, 42.1, 42.1, 58.6, 91.8", \ + "63.1, 63.1, 63.1, 80.0, 112.9", \ + "101.5, 101.5, 101.5, 119.2, 153.1", \ + "175.7, 175.7, 175.7, 194.2, 229.8", \ + "322.3, 322.3, 322.3, 341.4, 378.5"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__71) { + values ("40.2, 40.2, 40.2, 69.4, 125.0", \ + "48.1, 48.1, 48.1, 78.6, 136.3", \ + "63.6, 63.6, 63.6, 95.0, 155.6", \ + "89.9, 89.9, 89.9, 123.7, 187.4", \ + "140.2, 140.2, 140.2, 175.4, 242.9"); + } + rise_transition (inslew_load_5x5__71) { + values ("74.4, 74.4, 74.4, 121.2, 216.3", \ + "108.2, 108.2, 108.2, 154.7, 248.1", \ + "176.9, 176.9, 176.9, 221.8, 314.8", \ + "309.2, 309.2, 309.2, 355.3, 446.6", \ + "571.8, 571.8, 571.8, 618.3, 710.8"); + } + cell_fall (inslew_load_5x5__71) { + values ("26.0, 26.0, 26.0, 43.9, 74.2", \ + "26.9, 26.9, 26.9, 47.9, 83.0", \ + "23.7, 23.7, 23.7, 48.1, 89.7", \ + "13.7, 13.7, 13.7, 41.1, 89.5", \ + "-8.8, -8.8, -8.8, 20.7, 75.1"); + } + fall_transition (inslew_load_5x5__71) { + values ("30.0, 30.0, 30.0, 46.9, 79.9", \ + "46.6, 46.6, 46.6, 64.3, 97.6", \ + "76.9, 76.9, 76.9, 95.8, 131.0", \ + "135.4, 135.4, 135.4, 155.4, 193.1", \ + "250.9, 250.9, 250.9, 271.8, 311.8"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__71) { + values ("284.6, 284.6, 284.6, 337.3, 442.8", \ + "321.0, 321.0, 321.0, 373.8, 479.2", \ + "393.2, 393.2, 393.2, 446.0, 551.5", \ + "536.9, 536.9, 536.9, 589.6, 695.1", \ + "823.7, 823.7, 823.7, 876.4, 981.9"); + } + fall_power (energy_inslew_load_5x5__71) { + values ("285.7, 285.7, 285.7, 338.5, 444.0", \ + "352.7, 352.7, 352.7, 405.4, 510.9", \ + "484.4, 484.4, 484.4, 537.1, 642.6", \ + "746.1, 746.1, 746.1, 798.9, 904.3", \ + "1268.7, 1268.7, 1268.7, 1321.4, 1426.9"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__71) { + values ("142.6, 142.6, 142.6, 195.4, 300.8", \ + "170.9, 170.9, 170.9, 223.6, 329.1", \ + "227.5, 227.5, 227.5, 280.2, 385.7", \ + "340.5, 340.5, 340.5, 393.3, 498.8", \ + "566.7, 566.7, 566.7, 619.5, 724.9"); + } + fall_power (energy_inslew_load_5x5__71) { + values ("116.5, 116.5, 116.5, 169.2, 274.7", \ + "146.5, 146.5, 146.5, 199.3, 304.7", \ + "206.6, 206.6, 206.6, 259.3, 364.8", \ + "326.8, 326.8, 326.8, 379.5, 485.0", \ + "567.1, 567.1, 567.1, 619.9, 725.3"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__71) { + values ("81.3, 81.3, 81.3, 134.1, 239.5", \ + "110.4, 110.4, 110.4, 163.1, 268.6", \ + "168.5, 168.5, 168.5, 221.3, 326.7", \ + "284.8, 284.8, 284.8, 337.5, 443.0", \ + "517.3, 517.3, 517.3, 570.0, 675.5"); + } + fall_power (energy_inslew_load_5x5__71) { + values ("73.6, 73.6, 73.6, 126.3, 231.8", \ + "94.0, 94.0, 94.0, 146.7, 252.2", \ + "134.7, 134.7, 134.7, 187.5, 292.9", \ + "216.2, 216.2, 216.2, 269.0, 374.5", \ + "379.3, 379.3, 379.3, 432.0, 537.5"); + } + } + } + } + + cell (nr3v0x05) { + area : 0.0 ; + cell_leakage_power : 0.67 ; + leakage_power () { + when : "(!(c) & !(b) & a)" ; + value : 0.57 ; + } + leakage_power () { + when : "((a & (b ^ c)) | (b & !(c)))" ; + value : 0.62 ; + } + leakage_power () { + when : "(!((a & !(b))) & c)" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 0.0001 ; + } + pin (c) { + direction : input ; + capacitance : 4.29 ; + } + pin (b) { + direction : input ; + capacitance : 4.26 ; + } + pin (a) { + direction : input ; + capacitance : 4.48 ; + } + pin (z) { + function : "((!(c) & !(b)) & !(a))" ; + direction : output ; + capacitance : 3.86 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__72) { + values ("91.4, 91.4, 91.4, 116.2, 165.9", \ + "86.1, 86.1, 86.1, 111.4, 161.7", \ + "75.2, 75.2, 75.2, 100.8, 151.5", \ + "54.0, 54.0, 54.0, 80.3, 131.5", \ + "11.0, 11.0, 11.0, 37.6, 90.0"); + } + rise_transition (inslew_load_5x5__72) { + values ("171.1, 171.1, 171.1, 213.4, 298.4", \ + "196.7, 196.7, 196.7, 238.9, 323.5", \ + "244.7, 244.7, 244.7, 286.7, 371.2", \ + "342.2, 342.2, 342.2, 383.4, 466.5", \ + "540.3, 540.3, 540.3, 580.8, 662.1"); + } + cell_fall (inslew_load_5x5__72) { + values ("47.1, 47.1, 47.1, 61.1, 87.4", \ + "63.3, 63.3, 63.3, 78.8, 107.6", \ + "89.3, 89.3, 89.3, 106.3, 138.3", \ + "136.5, 136.5, 136.5, 154.8, 189.9", \ + "227.7, 227.7, 227.7, 247.0, 284.4"); + } + fall_transition (inslew_load_5x5__72) { + values ("49.5, 49.5, 49.5, 64.6, 95.1", \ + "77.9, 77.9, 77.9, 93.1, 123.1", \ + "130.2, 130.2, 130.2, 145.7, 176.1", \ + "231.8, 231.8, 231.8, 247.6, 278.7", \ + "433.2, 433.2, 433.2, 449.2, 481.0"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__72) { + values ("69.4, 69.4, 69.4, 94.7, 144.8", \ + "72.9, 72.9, 72.9, 98.8, 149.6", \ + "77.2, 77.2, 77.2, 104.0, 156.4", \ + "83.8, 83.8, 83.8, 111.8, 166.0", \ + "95.1, 95.1, 95.1, 123.9, 180.6"); + } + rise_transition (inslew_load_5x5__72) { + values ("125.7, 125.7, 125.7, 168.3, 254.4", \ + "156.8, 156.8, 156.8, 198.9, 284.1", \ + "217.0, 217.0, 217.0, 258.3, 341.8", \ + "335.3, 335.3, 335.3, 376.6, 460.3", \ + "573.1, 573.1, 573.1, 614.2, 696.5"); + } + cell_fall (inslew_load_5x5__72) { + values ("37.9, 37.9, 37.9, 52.7, 79.7", \ + "45.2, 45.2, 45.2, 62.1, 92.5", \ + "53.6, 53.6, 53.6, 73.0, 108.0", \ + "65.6, 65.6, 65.6, 87.1, 126.9", \ + "86.4, 86.4, 86.4, 109.4, 153.2"); + } + fall_transition (inslew_load_5x5__72) { + values ("40.7, 40.7, 40.7, 55.8, 86.1", \ + "61.6, 61.6, 61.6, 77.1, 107.3", \ + "100.0, 100.0, 100.0, 116.2, 147.4", \ + "174.1, 174.1, 174.1, 191.1, 223.8", \ + "320.6, 320.6, 320.6, 338.1, 372.2"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__72) { + values ("37.6, 37.6, 37.6, 64.5, 115.6", \ + "45.5, 45.5, 45.5, 73.5, 126.7", \ + "60.8, 60.8, 60.8, 89.7, 145.5", \ + "87.0, 87.0, 87.0, 118.1, 176.7", \ + "137.2, 137.2, 137.2, 169.4, 231.6"); + } + rise_transition (inslew_load_5x5__72) { + values ("70.5, 70.5, 70.5, 113.1, 199.9", \ + "104.4, 104.4, 104.4, 146.8, 232.0", \ + "173.0, 173.0, 173.0, 214.0, 299.2", \ + "305.2, 305.2, 305.2, 347.5, 430.9", \ + "567.8, 567.8, 567.8, 610.4, 695.0"); + } + cell_fall (inslew_load_5x5__72) { + values ("24.3, 24.3, 24.3, 41.0, 69.3", \ + "24.9, 24.9, 24.9, 44.5, 77.4", \ + "21.5, 21.5, 21.5, 44.2, 83.1", \ + "11.2, 11.2, 11.2, 36.6, 81.7", \ + "-11.4, -11.4, -11.4, 15.7, 66.2"); + } + fall_transition (inslew_load_5x5__72) { + values ("28.5, 28.5, 28.5, 44.1, 74.2", \ + "45.0, 45.0, 45.0, 61.4, 92.0", \ + "75.2, 75.2, 75.2, 92.7, 125.1", \ + "133.6, 133.6, 133.6, 152.1, 186.9", \ + "249.1, 249.1, 249.1, 268.3, 305.2"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__72) { + values ("188.4, 188.4, 188.4, 236.7, 333.1", \ + "213.7, 213.7, 213.7, 262.0, 358.4", \ + "264.3, 264.3, 264.3, 312.5, 409.0", \ + "365.4, 365.4, 365.4, 413.7, 510.2", \ + "567.7, 567.7, 567.7, 616.0, 712.5"); + } + fall_power (energy_inslew_load_5x5__72) { + values ("150.6, 150.6, 150.6, 198.8, 295.3", \ + "199.8, 199.8, 199.8, 248.0, 344.5", \ + "298.2, 298.2, 298.2, 346.5, 442.9", \ + "495.1, 495.1, 495.1, 543.3, 639.8", \ + "888.7, 888.7, 888.7, 937.0, 1033.4"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__72) { + values ("138.1, 138.1, 138.1, 186.4, 282.8", \ + "166.4, 166.4, 166.4, 214.6, 311.1", \ + "223.0, 223.0, 223.0, 271.2, 367.7", \ + "336.0, 336.0, 336.0, 384.3, 480.8", \ + "562.2, 562.2, 562.2, 610.5, 706.9"); + } + fall_power (energy_inslew_load_5x5__72) { + values ("112.0, 112.0, 112.0, 160.2, 256.7", \ + "142.0, 142.0, 142.0, 190.3, 286.7", \ + "202.1, 202.1, 202.1, 250.3, 346.8", \ + "322.3, 322.3, 322.3, 370.5, 467.0", \ + "562.6, 562.6, 562.6, 610.9, 707.3"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__72) { + values ("76.8, 76.8, 76.8, 125.1, 221.5", \ + "105.9, 105.9, 105.9, 154.1, 250.6", \ + "164.0, 164.0, 164.0, 212.3, 308.7", \ + "280.3, 280.3, 280.3, 328.5, 425.0", \ + "512.8, 512.8, 512.8, 561.0, 657.5"); + } + fall_power (energy_inslew_load_5x5__72) { + values ("69.1, 69.1, 69.1, 117.3, 213.8", \ + "89.5, 89.5, 89.5, 137.7, 234.2", \ + "130.2, 130.2, 130.2, 178.5, 274.9", \ + "211.7, 211.7, 211.7, 260.0, 356.5", \ + "374.8, 374.8, 374.8, 423.0, 519.5"); + } + } + } + } + + cell (nr3v0x1) { + area : 0.0 ; + cell_leakage_power : 1.7 ; + leakage_power () { + when : "(!(c) & !(b) & a)" ; + value : 1.1 ; + } + leakage_power () { + when : "(b & c)" ; + value : 2.9 ; + } + leakage_power () { + when : "((a & (b ^ c)) | (b & !(c)))" ; + value : 1.2 ; + } + leakage_power () { + when : "(c & !(b) & !(a))" ; + value : 3 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 0.00014 ; + } + pin (c) { + direction : input ; + capacitance : 7.83 ; + } + pin (b) { + direction : input ; + capacitance : 8.10 ; + } + pin (a) { + direction : input ; + capacitance : 8.49 ; + } + pin (z) { + function : "((!(c) & !(b)) & !(a))" ; + direction : output ; + capacitance : 5.84 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__73) { + values ("82.5, 82.5, 82.5, 101.4, 139.0", \ + "74.5, 74.5, 74.5, 93.7, 131.9", \ + "58.5, 58.5, 58.5, 77.9, 116.5", \ + "26.5, 26.5, 26.5, 46.4, 86.1", \ + "-38.3, -38.3, -38.3, -17.7, 22.8"); + } + rise_transition (inslew_load_5x5__73) { + values ("156.9, 156.9, 156.9, 188.8, 253.0", \ + "178.0, 178.0, 178.0, 209.9, 273.9", \ + "217.8, 217.8, 217.8, 249.5, 313.1", \ + "299.8, 299.8, 299.8, 330.7, 393.0", \ + "467.1, 467.1, 467.1, 497.5, 558.5"); + } + cell_fall (inslew_load_5x5__73) { + values ("48.1, 48.1, 48.1, 60.3, 83.4", \ + "67.9, 67.9, 67.9, 81.2, 106.3", \ + "100.1, 100.1, 100.1, 114.6, 142.2", \ + "159.4, 159.4, 159.4, 174.9, 204.9", \ + "274.9, 274.9, 274.9, 291.2, 322.8"); + } + fall_transition (inslew_load_5x5__73) { + values ("47.5, 47.5, 47.5, 60.3, 86.2", \ + "78.3, 78.3, 78.3, 91.2, 116.7", \ + "134.5, 134.5, 134.5, 147.6, 173.3", \ + "243.3, 243.3, 243.3, 256.6, 282.8", \ + "458.8, 458.8, 458.8, 472.2, 498.8"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__73) { + values ("60.8, 60.8, 60.8, 80.1, 118.1", \ + "61.1, 61.1, 61.1, 81.1, 119.9", \ + "59.7, 59.7, 59.7, 80.4, 120.6", \ + "54.5, 54.5, 54.5, 76.3, 118.6", \ + "41.8, 41.8, 41.8, 64.6, 109.0"); + } + rise_transition (inslew_load_5x5__73) { + values ("112.1, 112.1, 112.1, 144.3, 209.1", \ + "138.9, 138.9, 138.9, 170.6, 234.6", \ + "191.3, 191.3, 191.3, 222.4, 285.0", \ + "293.6, 293.6, 293.6, 324.8, 389.0", \ + "499.6, 499.6, 499.6, 530.9, 593.2"); + } + cell_fall (inslew_load_5x5__73) { + values ("38.5, 38.5, 38.5, 51.5, 75.3", \ + "48.5, 48.5, 48.5, 63.2, 90.0", \ + "62.2, 62.2, 62.2, 78.8, 109.3", \ + "84.9, 84.9, 84.9, 103.1, 137.2", \ + "127.4, 127.4, 127.4, 146.6, 183.6"); + } + fall_transition (inslew_load_5x5__73) { + values ("38.4, 38.4, 38.4, 51.4, 77.2", \ + "61.2, 61.2, 61.2, 74.5, 100.1", \ + "102.7, 102.7, 102.7, 116.5, 143.0", \ + "183.0, 183.0, 183.0, 197.2, 224.8", \ + "341.5, 341.5, 341.5, 356.1, 384.7"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__73) { + values ("28.4, 28.4, 28.4, 49.5, 88.9", \ + "33.5, 33.5, 33.5, 54.7, 96.1", \ + "41.2, 41.2, 41.2, 64.7, 107.9", \ + "53.9, 53.9, 53.9, 78.9, 125.9", \ + "77.6, 77.6, 77.6, 103.5, 153.3"); + } + rise_transition (inslew_load_5x5__73) { + values ("57.3, 57.3, 57.3, 89.5, 154.6", \ + "88.1, 88.1, 88.1, 118.4, 182.9", \ + "147.0, 147.0, 147.0, 178.9, 241.4", \ + "262.4, 262.4, 262.4, 294.8, 358.7", \ + "491.8, 491.8, 491.8, 524.5, 589.3"); + } + cell_fall (inslew_load_5x5__73) { + values ("22.9, 22.9, 22.9, 38.1, 63.5", \ + "25.8, 25.8, 25.8, 43.3, 72.7", \ + "27.4, 27.4, 27.4, 47.1, 81.3", \ + "27.5, 27.5, 27.5, 49.0, 87.9", \ + "25.9, 25.9, 25.9, 48.6, 91.2"); + } + fall_transition (inslew_load_5x5__73) { + values ("25.0, 25.0, 25.0, 38.5, 64.2", \ + "43.2, 43.2, 43.2, 57.3, 83.5", \ + "76.3, 76.3, 76.3, 91.1, 118.9", \ + "140.4, 140.4, 140.4, 155.9, 185.3", \ + "267.3, 267.3, 267.3, 283.3, 314.2"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__73) { + values ("343.4, 343.4, 343.4, 416.4, 562.3", \ + "384.5, 384.5, 384.5, 457.5, 603.4", \ + "466.7, 466.7, 466.7, 539.7, 685.7", \ + "631.2, 631.2, 631.2, 704.2, 850.1", \ + "960.1, 960.1, 960.1, 1033.0, 1179.0"); + } + fall_power (energy_inslew_load_5x5__73) { + values ("278.8, 278.8, 278.8, 351.8, 497.7", \ + "374.5, 374.5, 374.5, 447.5, 593.4", \ + "565.9, 565.9, 565.9, 638.9, 784.8", \ + "948.7, 948.7, 948.7, 1021.6, 1167.6", \ + "1714.2, 1714.2, 1714.2, 1787.2, 1933.1"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__73) { + values ("243.0, 243.0, 243.0, 316.0, 462.0", \ + "290.3, 290.3, 290.3, 363.3, 509.3", \ + "385.0, 385.0, 385.0, 457.9, 603.9", \ + "574.2, 574.2, 574.2, 647.2, 793.2", \ + "952.7, 952.7, 952.7, 1025.7, 1171.7"); + } + fall_power (energy_inslew_load_5x5__73) { + values ("201.8, 201.8, 201.8, 274.8, 420.7", \ + "261.2, 261.2, 261.2, 334.2, 480.2", \ + "380.1, 380.1, 380.1, 453.1, 599.1", \ + "617.9, 617.9, 617.9, 690.9, 836.8", \ + "1093.4, 1093.4, 1093.4, 1166.4, 1312.3"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__73) { + values ("120.5, 120.5, 120.5, 193.5, 339.4", \ + "169.4, 169.4, 169.4, 242.4, 388.4", \ + "267.3, 267.3, 267.3, 340.3, 486.3", \ + "463.1, 463.1, 463.1, 536.1, 682.1", \ + "854.7, 854.7, 854.7, 927.7, 1073.6"); + } + fall_power (energy_inslew_load_5x5__73) { + values ("115.8, 115.8, 115.8, 188.8, 334.7", \ + "157.1, 157.1, 157.1, 230.1, 376.1", \ + "239.9, 239.9, 239.9, 312.8, 458.8", \ + "405.3, 405.3, 405.3, 478.3, 624.2", \ + "736.1, 736.1, 736.1, 809.1, 955.1"); + } + } + } + } + + cell (nr3v0x2) { + area : 0.0 ; + cell_leakage_power : 1.7 ; + leakage_power () { + when : "(!(c) & !(b) & a)" ; + value : 1.5 ; + } + leakage_power () { + when : "((a & (b ^ c)) | (b & !(c)))" ; + value : 1.7 ; + } + leakage_power () { + when : "(!((a & !(b))) & c)" ; + value : 3.8 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 0.00028 ; + } + pin (c) { + direction : input ; + capacitance : 11.39 ; + } + pin (b) { + direction : input ; + capacitance : 11.23 ; + } + pin (a) { + direction : input ; + capacitance : 11.12 ; + } + pin (z) { + function : "((!(c) & !(b)) & !(a))" ; + direction : output ; + capacitance : 8.27 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__74) { + values ("85.4, 85.4, 85.4, 104.3, 142.0", \ + "78.5, 78.5, 78.5, 97.8, 136.1", \ + "64.8, 64.8, 64.8, 84.2, 122.9", \ + "37.6, 37.6, 37.6, 57.4, 97.0", \ + "-17.1, -17.1, -17.1, 3.2, 43.5"); + } + rise_transition (inslew_load_5x5__74) { + values ("160.9, 160.9, 160.9, 192.8, 256.9", \ + "184.3, 184.3, 184.3, 216.3, 280.2", \ + "228.4, 228.4, 228.4, 260.0, 323.8", \ + "318.2, 318.2, 318.2, 349.3, 411.8", \ + "501.1, 501.1, 501.1, 531.6, 592.8"); + } + cell_fall (inslew_load_5x5__74) { + values ("44.9, 44.9, 44.9, 56.3, 77.8", \ + "62.5, 62.5, 62.5, 75.1, 98.6", \ + "91.3, 91.3, 91.3, 105.0, 131.1", \ + "144.3, 144.3, 144.3, 159.0, 187.3", \ + "247.6, 247.6, 247.6, 263.0, 292.9"); + } + fall_transition (inslew_load_5x5__74) { + values ("44.2, 44.2, 44.2, 55.9, 79.4", \ + "73.0, 73.0, 73.0, 84.8, 107.9", \ + "125.8, 125.8, 125.8, 137.8, 161.3", \ + "228.5, 228.5, 228.5, 240.7, 264.7", \ + "432.0, 432.0, 432.0, 444.3, 468.8"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__74) { + values ("63.1, 63.1, 63.1, 82.5, 120.7", \ + "65.3, 65.3, 65.3, 85.3, 124.2", \ + "67.5, 67.5, 67.5, 88.1, 128.2", \ + "70.0, 70.0, 70.0, 91.5, 133.3", \ + "72.8, 72.8, 72.8, 95.1, 138.7"); + } + rise_transition (inslew_load_5x5__74) { + values ("115.5, 115.5, 115.5, 147.6, 212.5", \ + "145.2, 145.2, 145.2, 177.0, 241.0", \ + "203.1, 203.1, 203.1, 234.2, 297.0", \ + "316.3, 316.3, 316.3, 347.5, 411.4", \ + "544.2, 544.2, 544.2, 575.4, 637.5"); + } + cell_fall (inslew_load_5x5__74) { + values ("35.8, 35.8, 35.8, 48.0, 70.2", \ + "43.5, 43.5, 43.5, 57.5, 82.7", \ + "53.3, 53.3, 53.3, 69.2, 98.2", \ + "68.4, 68.4, 68.4, 85.9, 118.6", \ + "95.8, 95.8, 95.8, 114.4, 150.1"); + } + fall_transition (inslew_load_5x5__74) { + values ("35.9, 35.9, 35.9, 47.7, 71.0", \ + "56.7, 56.7, 56.7, 68.9, 92.3", \ + "94.9, 94.9, 94.9, 107.6, 132.0", \ + "168.9, 168.9, 168.9, 182.1, 207.7", \ + "315.0, 315.0, 315.0, 328.7, 355.3"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__74) { + values ("29.4, 29.4, 29.4, 50.6, 90.0", \ + "36.0, 36.0, 36.0, 57.0, 98.5", \ + "46.5, 46.5, 46.5, 69.7, 112.7", \ + "65.0, 65.0, 65.0, 89.4, 135.8", \ + "100.1, 100.1, 100.1, 125.4, 174.3"); + } + rise_transition (inslew_load_5x5__74) { + values ("58.6, 58.6, 58.6, 90.8, 155.9", \ + "91.4, 91.4, 91.4, 121.7, 186.3", \ + "154.2, 154.2, 154.2, 185.9, 248.4", \ + "277.2, 277.2, 277.2, 309.4, 373.0", \ + "521.7, 521.7, 521.7, 554.1, 618.5"); + } + cell_fall (inslew_load_5x5__74) { + values ("21.1, 21.1, 21.1, 35.5, 59.2", \ + "22.5, 22.5, 22.5, 39.2, 67.0", \ + "21.5, 21.5, 21.5, 40.3, 73.0", \ + "16.5, 16.5, 16.5, 37.2, 74.5", \ + "5.1, 5.1, 5.1, 27.0, 67.9"); + } + fall_transition (inslew_load_5x5__74) { + values ("23.7, 23.7, 23.7, 36.1, 59.4", \ + "40.5, 40.5, 40.5, 53.6, 77.7", \ + "71.5, 71.5, 71.5, 85.3, 111.0", \ + "131.6, 131.6, 131.6, 146.1, 173.5", \ + "250.7, 250.7, 250.7, 265.6, 294.6"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__74) { + values ("500.2, 500.2, 500.2, 603.6, 810.5", \ + "565.4, 565.4, 565.4, 668.9, 875.7", \ + "696.0, 696.0, 696.0, 799.4, 1006.3", \ + "957.0, 957.0, 957.0, 1060.5, 1267.3", \ + "1479.2, 1479.2, 1479.2, 1582.6, 1789.5"); + } + fall_power (energy_inslew_load_5x5__74) { + values ("391.8, 391.8, 391.8, 495.2, 702.1", \ + "528.1, 528.1, 528.1, 631.5, 838.4", \ + "800.7, 800.7, 800.7, 904.2, 1111.0", \ + "1346.0, 1346.0, 1346.0, 1449.4, 1656.3", \ + "2436.4, 2436.4, 2436.4, 2539.9, 2746.7"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__74) { + values ("357.1, 357.1, 357.1, 460.6, 667.4", \ + "433.3, 433.3, 433.3, 536.7, 743.6", \ + "585.7, 585.7, 585.7, 689.1, 896.0", \ + "890.4, 890.4, 890.4, 993.8, 1200.7", \ + "1499.9, 1499.9, 1499.9, 1603.3, 1810.2"); + } + fall_power (energy_inslew_load_5x5__74) { + values ("281.1, 281.1, 281.1, 384.5, 591.4", \ + "361.6, 361.6, 361.6, 465.1, 671.9", \ + "522.8, 522.8, 522.8, 626.2, 833.1", \ + "845.0, 845.0, 845.0, 948.4, 1155.3", \ + "1489.4, 1489.4, 1489.4, 1592.8, 1799.7"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__74) { + values ("176.8, 176.8, 176.8, 280.3, 487.1", \ + "252.2, 252.2, 252.2, 355.7, 562.5", \ + "403.0, 403.0, 403.0, 506.4, 713.3", \ + "704.5, 704.5, 704.5, 808.0, 1014.8", \ + "1307.6, 1307.6, 1307.6, 1411.1, 1617.9"); + } + fall_power (energy_inslew_load_5x5__74) { + values ("162.7, 162.7, 162.7, 266.1, 473.0", \ + "219.9, 219.9, 219.9, 323.3, 530.2", \ + "334.4, 334.4, 334.4, 437.8, 644.7", \ + "563.4, 563.4, 563.4, 666.8, 873.7", \ + "1021.3, 1021.3, 1021.3, 1124.8, 1331.6"); + } + } + } + } + + cell (nr3v0x4) { + area : 0.0 ; + cell_leakage_power : 3.1 ; + leakage_power () { + when : "(!(c) & !(b) & a)" ; + value : 2.7 ; + } + leakage_power () { + when : "((a & (b ^ c)) | (b & !(c)))" ; + value : 2.9 ; + } + leakage_power () { + when : "(!((a & !(b))) & c)" ; + value : 6.9 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 0.00051 ; + } + pin (c) { + direction : input ; + capacitance : 19.04 ; + } + pin (b) { + direction : input ; + capacitance : 19.30 ; + } + pin (a) { + direction : input ; + capacitance : 18.16 ; + } + pin (z) { + function : "((!(c) & !(b)) & !(a))" ; + direction : output ; + capacitance : 15.22 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__75) { + values ("85.5, 85.5, 85.5, 105.8, 146.4", \ + "77.6, 77.6, 77.6, 98.4, 139.5", \ + "61.9, 61.9, 61.9, 82.9, 124.5", \ + "30.6, 30.6, 30.6, 52.0, 94.7", \ + "-32.9, -32.9, -32.9, -10.8, 32.8"); + } + rise_transition (inslew_load_5x5__75) { + values ("161.6, 161.6, 161.6, 196.0, 265.3", \ + "183.0, 183.0, 183.0, 217.4, 286.4", \ + "223.2, 223.2, 223.2, 257.4, 326.2", \ + "306.0, 306.0, 306.0, 339.4, 406.7", \ + "474.8, 474.8, 474.8, 507.6, 573.6"); + } + cell_fall (inslew_load_5x5__75) { + values ("48.5, 48.5, 48.5, 61.4, 85.9", \ + "68.1, 68.1, 68.1, 82.3, 109.0", \ + "99.9, 99.9, 99.9, 115.4, 144.8", \ + "158.4, 158.4, 158.4, 175.1, 207.0", \ + "272.3, 272.3, 272.3, 289.7, 323.5"); + } + fall_transition (inslew_load_5x5__75) { + values ("47.2, 47.2, 47.2, 60.8, 88.2", \ + "77.6, 77.6, 77.6, 91.3, 118.3", \ + "132.9, 132.9, 132.9, 146.8, 174.0", \ + "240.1, 240.1, 240.1, 254.1, 281.9", \ + "452.2, 452.2, 452.2, 466.4, 494.6"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__75) { + values ("62.3, 62.3, 62.3, 83.2, 124.2", \ + "61.7, 61.7, 61.7, 83.3, 125.1", \ + "58.4, 58.4, 58.4, 80.8, 124.2", \ + "49.2, 49.2, 49.2, 72.8, 118.6", \ + "27.7, 27.7, 27.7, 52.6, 101.1"); + } + rise_transition (inslew_load_5x5__75) { + values ("114.4, 114.4, 114.4, 149.1, 219.2", \ + "139.7, 139.7, 139.7, 173.9, 243.0", \ + "189.2, 189.2, 189.2, 222.8, 290.4", \ + "285.9, 285.9, 285.9, 319.5, 388.7", \ + "480.5, 480.5, 480.5, 514.3, 581.7"); + } + cell_fall (inslew_load_5x5__75) { + values ("39.5, 39.5, 39.5, 53.2, 78.4", \ + "50.6, 50.6, 50.6, 66.1, 94.3", \ + "66.5, 66.5, 66.5, 83.9, 115.9", \ + "93.6, 93.6, 93.6, 112.6, 148.3", \ + "144.8, 144.8, 144.8, 164.9, 203.5"); + } + fall_transition (inslew_load_5x5__75) { + values ("38.8, 38.8, 38.8, 52.5, 79.8", \ + "62.3, 62.3, 62.3, 76.2, 103.4", \ + "105.1, 105.1, 105.1, 119.5, 147.4", \ + "187.8, 187.8, 187.8, 202.6, 231.6", \ + "351.3, 351.3, 351.3, 366.5, 396.5"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__75) { + values ("30.4, 30.4, 30.4, 53.1, 95.3", \ + "35.9, 35.9, 35.9, 58.6, 103.0", \ + "44.1, 44.1, 44.1, 69.3, 115.6", \ + "57.7, 57.7, 57.7, 84.4, 134.7", \ + "83.0, 83.0, 83.0, 110.8, 164.1"); + } + rise_transition (inslew_load_5x5__75) { + values ("60.0, 60.0, 60.0, 94.7, 165.1", \ + "91.0, 91.0, 91.0, 123.9, 193.7", \ + "150.5, 150.5, 150.5, 184.9, 252.5", \ + "267.0, 267.0, 267.0, 301.9, 370.8", \ + "498.4, 498.4, 498.4, 533.6, 603.4"); + } + cell_fall (inslew_load_5x5__75) { + values ("23.9, 23.9, 23.9, 39.9, 66.6", \ + "26.8, 26.8, 26.8, 45.3, 76.2", \ + "28.2, 28.2, 28.2, 49.1, 85.2", \ + "27.6, 27.6, 27.6, 50.6, 91.9", \ + "24.5, 24.5, 24.5, 48.9, 94.4"); + } + fall_transition (inslew_load_5x5__75) { + values ("25.4, 25.4, 25.4, 39.7, 66.8", \ + "43.3, 43.3, 43.3, 58.2, 85.9", \ + "75.9, 75.9, 75.9, 91.6, 120.8", \ + "138.9, 138.9, 138.9, 155.3, 186.5", \ + "263.5, 263.5, 263.5, 280.5, 313.3"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__75) { + values ("855.5, 855.5, 855.5, 1045.8, 1426.4", \ + "956.1, 956.1, 956.1, 1146.4, 1527.0", \ + "1157.2, 1157.2, 1157.2, 1347.5, 1728.1", \ + "1559.5, 1559.5, 1559.5, 1749.8, 2130.4", \ + "2364.1, 2364.1, 2364.1, 2554.4, 2935.0"); + } + fall_power (energy_inslew_load_5x5__75) { + values ("687.4, 687.4, 687.4, 877.7, 1258.3", \ + "917.5, 917.5, 917.5, 1107.8, 1488.4", \ + "1377.8, 1377.8, 1377.8, 1568.1, 1948.7", \ + "2298.2, 2298.2, 2298.2, 2488.5, 2869.1", \ + "4139.1, 4139.1, 4139.1, 4329.4, 4710.0"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__75) { + values ("598.1, 598.1, 598.1, 788.4, 1169.0", \ + "704.5, 704.5, 704.5, 894.8, 1275.4", \ + "917.2, 917.2, 917.2, 1107.5, 1488.1", \ + "1342.6, 1342.6, 1342.6, 1532.9, 1913.5", \ + "2193.5, 2193.5, 2193.5, 2383.8, 2764.4"); + } + fall_power (energy_inslew_load_5x5__75) { + values ("512.7, 512.7, 512.7, 703.0, 1083.6", \ + "666.3, 666.3, 666.3, 856.6, 1237.2", \ + "973.5, 973.5, 973.5, 1163.8, 1544.4", \ + "1587.9, 1587.9, 1587.9, 1778.3, 2158.9", \ + "2816.8, 2816.8, 2816.8, 3007.1, 3387.7"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__75) { + values ("306.6, 306.6, 306.6, 496.9, 877.5", \ + "426.2, 426.2, 426.2, 616.5, 997.1", \ + "665.3, 665.3, 665.3, 855.6, 1236.3", \ + "1143.6, 1143.6, 1143.6, 1333.9, 1714.6", \ + "2100.3, 2100.3, 2100.3, 2290.6, 2671.2"); + } + fall_power (energy_inslew_load_5x5__75) { + values ("292.1, 292.1, 292.1, 482.4, 863.0", \ + "390.6, 390.6, 390.6, 580.9, 961.5", \ + "587.7, 587.7, 587.7, 778.0, 1158.6", \ + "981.7, 981.7, 981.7, 1172.0, 1552.7", \ + "1769.9, 1769.9, 1769.9, 1960.2, 2340.8"); + } + } + } + } + + cell (nr3v1x05) { + area : 0.0 ; + cell_leakage_power : 0.67 ; + leakage_power () { + when : "(!(c) & !(b) & a)" ; + value : 0.57 ; + } + leakage_power () { + when : "((a & (b ^ c)) | (b & !(c)))" ; + value : 0.62 ; + } + leakage_power () { + when : "(!((a & !(b))) & c)" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 0.00014 ; + } + pin (c) { + direction : input ; + capacitance : 4.62 ; + } + pin (b) { + direction : input ; + capacitance : 4.63 ; + } + pin (a) { + direction : input ; + capacitance : 4.85 ; + } + pin (z) { + function : "((!(c) & !(b)) & !(a))" ; + direction : output ; + capacitance : 4.45 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__76) { + values ("107.5, 107.5, 107.5, 136.1, 193.4", \ + "115.4, 115.4, 115.4, 144.5, 202.2", \ + "129.1, 129.1, 129.1, 158.4, 216.5", \ + "157.2, 157.2, 157.2, 186.4, 244.6", \ + "214.1, 214.1, 214.1, 243.4, 301.7"); + } + rise_transition (inslew_load_5x5__76) { + values ("195.2, 195.2, 195.2, 244.0, 342.4", \ + "242.9, 242.9, 242.9, 291.7, 389.4", \ + "331.8, 331.8, 331.8, 380.6, 478.5", \ + "507.3, 507.3, 507.3, 555.5, 653.0", \ + "858.8, 858.8, 858.8, 906.8, 1003.2"); + } + cell_fall (inslew_load_5x5__76) { + values ("27.6, 27.6, 27.6, 38.3, 57.5", \ + "31.7, 31.7, 31.7, 44.1, 66.3", \ + "36.5, 36.5, 36.5, 50.5, 76.2", \ + "43.1, 43.1, 43.1, 58.5, 87.4", \ + "54.6, 54.6, 54.6, 70.9, 102.3"); + } + fall_transition (inslew_load_5x5__76) { + values ("32.9, 32.9, 32.9, 42.8, 62.3", \ + "51.2, 51.2, 51.2, 61.6, 81.6", \ + "86.1, 86.1, 86.1, 97.1, 118.1", \ + "154.5, 154.5, 154.5, 166.0, 188.2", \ + "290.5, 290.5, 290.5, 302.3, 325.5"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__76) { + values ("82.2, 82.2, 82.2, 111.3, 169.0", \ + "98.6, 98.6, 98.6, 128.1, 186.4", \ + "126.5, 126.5, 126.5, 156.8, 215.7", \ + "180.3, 180.3, 180.3, 210.8, 270.8", \ + "286.6, 286.6, 286.6, 317.5, 378.5"); + } + rise_transition (inslew_load_5x5__76) { + values ("144.1, 144.1, 144.1, 193.5, 293.1", \ + "196.1, 196.1, 196.1, 245.0, 343.8", \ + "291.9, 291.9, 291.9, 340.2, 437.9", \ + "480.7, 480.7, 480.7, 528.4, 624.5", \ + "857.7, 857.7, 857.7, 904.9, 999.8"); + } + cell_fall (inslew_load_5x5__76) { + values ("21.6, 21.6, 21.6, 33.0, 52.9", \ + "19.1, 19.1, 19.1, 32.9, 56.6", \ + "9.9, 9.9, 9.9, 26.3, 54.9", \ + "-12.3, -12.3, -12.3, 6.4, 40.2", \ + "-59.5, -59.5, -59.5, -38.9, -0.7"); + } + fall_transition (inslew_load_5x5__76) { + values ("27.8, 27.8, 27.8, 38.0, 57.5", \ + "41.3, 41.3, 41.3, 52.3, 72.7", \ + "66.4, 66.4, 66.4, 78.5, 100.7", \ + "115.0, 115.0, 115.0, 128.0, 152.4", \ + "210.9, 210.9, 210.9, 224.6, 250.9"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__76) { + values ("48.5, 48.5, 48.5, 78.9, 137.5", \ + "68.8, 68.8, 68.8, 100.2, 160.2", \ + "106.6, 106.6, 106.6, 138.8, 200.5", \ + "178.3, 178.3, 178.3, 211.2, 274.9", \ + "318.8, 318.8, 318.8, 352.1, 417.6"); + } + rise_transition (inslew_load_5x5__76) { + values ("84.6, 84.6, 84.6, 134.1, 234.8", \ + "137.4, 137.4, 137.4, 186.4, 285.6", \ + "236.8, 236.8, 236.8, 286.6, 383.8", \ + "431.4, 431.4, 431.4, 479.9, 579.1", \ + "816.6, 816.6, 816.6, 864.8, 961.7"); + } + cell_fall (inslew_load_5x5__76) { + values ("13.2, 13.2, 13.2, 26.1, 47.0", \ + "5.9, 5.9, 5.9, 21.9, 47.5", \ + "-12.2, -12.2, -12.2, 7.2, 39.0", \ + "-51.8, -51.8, -51.8, -29.2, 9.5", \ + "-133.4, -133.4, -133.4, -108.3, -63.3"); + } + fall_transition (inslew_load_5x5__76) { + values ("21.2, 21.2, 21.2, 31.8, 51.5", \ + "31.8, 31.8, 31.8, 43.7, 64.7", \ + "51.3, 51.3, 51.3, 64.7, 88.2", \ + "88.9, 88.9, 88.9, 103.7, 130.2", \ + "162.9, 162.9, 162.9, 178.7, 208.2"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__76) { + values ("219.8, 219.8, 219.8, 275.4, 386.8", \ + "267.9, 267.9, 267.9, 323.6, 435.0", \ + "364.3, 364.3, 364.3, 420.0, 531.3", \ + "557.0, 557.0, 557.0, 612.7, 724.0", \ + "942.4, 942.4, 942.4, 998.1, 1109.5"); + } + fall_power (energy_inslew_load_5x5__76) { + values ("142.0, 142.0, 142.0, 197.7, 309.0", \ + "188.4, 188.4, 188.4, 244.1, 355.5", \ + "281.4, 281.4, 281.4, 337.1, 448.4", \ + "467.3, 467.3, 467.3, 523.0, 634.3", \ + "839.1, 839.1, 839.1, 894.7, 1006.1"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__76) { + values ("166.7, 166.7, 166.7, 222.4, 333.7", \ + "215.1, 215.1, 215.1, 270.8, 382.2", \ + "312.0, 312.0, 312.0, 367.6, 479.0", \ + "505.6, 505.6, 505.6, 561.3, 672.6", \ + "892.9, 892.9, 892.9, 948.6, 1060.0"); + } + fall_power (energy_inslew_load_5x5__76) { + values ("108.2, 108.2, 108.2, 163.9, 275.2", \ + "133.7, 133.7, 133.7, 189.4, 300.7", \ + "184.7, 184.7, 184.7, 240.3, 351.7", \ + "286.6, 286.6, 286.6, 342.3, 453.6", \ + "490.5, 490.5, 490.5, 546.1, 657.5"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__76) { + values ("102.6, 102.6, 102.6, 158.3, 269.7", \ + "149.0, 149.0, 149.0, 204.7, 316.1", \ + "241.8, 241.8, 241.8, 297.5, 408.9", \ + "427.5, 427.5, 427.5, 483.1, 594.5", \ + "798.7, 798.7, 798.7, 854.4, 965.7"); + } + fall_power (energy_inslew_load_5x5__76) { + values ("71.1, 71.1, 71.1, 126.8, 238.2", \ + "87.2, 87.2, 87.2, 142.8, 254.2", \ + "119.2, 119.2, 119.2, 174.9, 286.2", \ + "183.3, 183.3, 183.3, 238.9, 350.3", \ + "311.4, 311.4, 311.4, 367.1, 478.4"); + } + } + } + } + + cell (nr4v0x1) { + area : 0.0 ; + cell_leakage_power : 0.81 ; + leakage_power () { + when : "(!(d) & !(c) & !(b) & a)" ; + value : 0.69 ; + } + leakage_power () { + when : "((a & ((b & !(c) & !(d)) | (!(b) & (c ^ d)))) | (b & !(c) & !(d)))" ; + value : 0.72 ; + } + leakage_power () { + when : "((a & ((b & (c ^ d)) | (!(b) & c & d))) | (!(a) & ((b & (c ^ d)) | (c & !(d)))))" ; + value : 0.79 ; + } + leakage_power () { + when : "((!(a) & !((b & !(c))) & d) | (b & c & d))" ; + value : 1.8 ; + } + leakage_power () { + when : "(!(d) & !(c) & !(b) & !(a))" ; + value : 0.00013 ; + } + pin (d) { + direction : input ; + capacitance : 5.92 ; + } + pin (c) { + direction : input ; + capacitance : 6.04 ; + } + pin (b) { + direction : input ; + capacitance : 6.82 ; + } + pin (a) { + direction : input ; + capacitance : 7.88 ; + } + pin (z) { + function : "(((!(d) & !(c)) & !(b)) & !(a))" ; + direction : output ; + capacitance : 5.42 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__77) { + values ("152.2, 152.2, 152.2, 180.5, 237.4", \ + "139.4, 139.4, 139.4, 168.1, 225.4", \ + "112.3, 112.3, 112.3, 141.4, 199.5", \ + "59.9, 59.9, 59.9, 89.1, 147.3", \ + "-42.3, -42.3, -42.3, -12.8, 45.7"); + } + rise_transition (inslew_load_5x5__77) { + values ("273.7, 273.7, 273.7, 322.3, 419.9", \ + "292.2, 292.2, 292.2, 340.4, 437.1", \ + "325.5, 325.5, 325.5, 374.1, 471.0", \ + "388.9, 388.9, 388.9, 437.3, 534.3", \ + "521.2, 521.2, 521.2, 568.4, 663.4"); + } + cell_fall (inslew_load_5x5__77) { + values ("78.1, 78.1, 78.1, 95.9, 131.0", \ + "107.9, 107.9, 107.9, 126.8, 163.6", \ + "160.6, 160.6, 160.6, 180.9, 220.3", \ + "254.6, 254.6, 254.6, 276.4, 318.6", \ + "435.4, 435.4, 435.4, 458.2, 502.9"); + } + fall_transition (inslew_load_5x5__77) { + values ("76.4, 76.4, 76.4, 98.0, 141.9", \ + "116.1, 116.1, 116.1, 137.3, 180.1", \ + "191.4, 191.4, 191.4, 212.6, 254.6", \ + "333.1, 333.1, 333.1, 354.4, 396.5", \ + "611.2, 611.2, 611.2, 632.5, 674.9"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__77) { + values ("122.9, 122.9, 122.9, 151.5, 208.7", \ + "117.9, 117.9, 117.9, 146.9, 204.6", \ + "105.4, 105.4, 105.4, 134.9, 193.4", \ + "79.7, 79.7, 79.7, 109.9, 169.8", \ + "26.2, 26.2, 26.2, 57.6, 119.3"); + } + rise_transition (inslew_load_5x5__77) { + values ("217.2, 217.2, 217.2, 266.2, 364.6", \ + "240.5, 240.5, 240.5, 289.1, 386.7", \ + "282.8, 282.8, 282.8, 331.0, 428.3", \ + "368.5, 368.5, 368.5, 415.8, 511.2", \ + "544.3, 544.3, 544.3, 590.7, 683.9"); + } + cell_fall (inslew_load_5x5__77) { + values ("68.7, 68.7, 68.7, 86.9, 122.4", \ + "88.0, 88.0, 88.0, 108.0, 145.8", \ + "119.9, 119.9, 119.9, 142.0, 183.7", \ + "173.5, 173.5, 173.5, 197.7, 243.8", \ + "273.6, 273.6, 273.6, 299.5, 349.4"); + } + fall_transition (inslew_load_5x5__77) { + values ("66.0, 66.0, 66.0, 87.6, 131.2", \ + "95.8, 95.8, 95.8, 117.0, 159.6", \ + "152.4, 152.4, 152.4, 173.8, 216.0", \ + "258.7, 258.7, 258.7, 280.5, 323.4", \ + "467.0, 467.0, 467.0, 489.2, 533.0"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__77) { + values ("83.3, 83.3, 83.3, 112.4, 170.0", \ + "83.2, 83.2, 83.2, 113.0, 171.5", \ + "81.5, 81.5, 81.5, 112.4, 172.6", \ + "75.3, 75.3, 75.3, 107.8, 170.4", \ + "58.5, 58.5, 58.5, 92.7, 158.6"); + } + rise_transition (inslew_load_5x5__77) { + values ("147.9, 147.9, 147.9, 197.0, 296.2", \ + "173.6, 173.6, 173.6, 222.3, 320.6", \ + "224.6, 224.6, 224.6, 272.5, 369.0", \ + "325.4, 325.4, 325.4, 373.0, 469.1", \ + "527.6, 527.6, 527.6, 575.0, 669.2"); + } + cell_fall (inslew_load_5x5__77) { + values ("55.8, 55.8, 55.8, 74.9, 110.9", \ + "68.0, 68.0, 68.0, 89.5, 128.9", \ + "86.4, 86.4, 86.4, 110.7, 155.0", \ + "114.2, 114.2, 114.2, 141.2, 191.4", \ + "163.5, 163.5, 163.5, 192.6, 248.0"); + } + fall_transition (inslew_load_5x5__77) { + values ("52.5, 52.5, 52.5, 74.0, 117.1", \ + "76.8, 76.8, 76.8, 98.2, 140.4", \ + "122.5, 122.5, 122.5, 144.5, 187.1", \ + "208.4, 208.4, 208.4, 231.1, 275.1", \ + "376.3, 376.3, 376.3, 399.6, 445.3"); + } + } + timing (maxd_z_d_negative_unate) { + related_pin : "d" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__77) { + values ("36.3, 36.3, 36.3, 67.2, 126.0", \ + "40.3, 40.3, 40.3, 72.5, 133.0", \ + "46.1, 46.1, 46.1, 77.9, 141.2", \ + "53.8, 53.8, 53.8, 89.7, 155.7", \ + "65.9, 65.9, 65.9, 103.8, 175.9"); + } + rise_transition (inslew_load_5x5__77) { + values ("70.8, 70.8, 70.8, 119.8, 219.3", \ + "101.9, 101.9, 101.9, 150.8, 249.0", \ + "159.7, 159.7, 159.7, 204.7, 301.4", \ + "271.9, 271.9, 271.9, 320.1, 413.6", \ + "494.2, 494.2, 494.2, 543.1, 639.8"); + } + cell_fall (inslew_load_5x5__77) { + values ("34.5, 34.5, 34.5, 56.2, 93.8", \ + "39.8, 39.8, 39.8, 64.9, 107.2", \ + "46.7, 46.7, 46.7, 75.1, 123.8", \ + "54.5, 54.5, 54.5, 85.9, 141.7", \ + "66.3, 66.3, 66.3, 99.8, 161.9"); + } + fall_transition (inslew_load_5x5__77) { + values ("32.1, 32.1, 32.1, 53.7, 96.6", \ + "52.3, 52.3, 52.3, 74.6, 117.0", \ + "90.3, 90.3, 90.3, 113.5, 157.2", \ + "161.8, 161.8, 161.8, 185.9, 231.8", \ + "302.0, 302.0, 302.0, 326.9, 375.0"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__77) { + values ("371.5, 371.5, 371.5, 439.2, 574.7", \ + "392.7, 392.7, 392.7, 460.4, 595.9", \ + "435.0, 435.0, 435.0, 502.8, 638.2", \ + "519.7, 519.7, 519.7, 587.5, 722.9", \ + "689.2, 689.2, 689.2, 756.9, 892.3"); + } + fall_power (energy_inslew_load_5x5__77) { + values ("286.8, 286.8, 286.8, 354.5, 490.0", \ + "364.6, 364.6, 364.6, 432.3, 567.8", \ + "520.2, 520.2, 520.2, 588.0, 723.4", \ + "831.5, 831.5, 831.5, 899.2, 1034.7", \ + "1454.0, 1454.0, 1454.0, 1521.7, 1657.1"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__77) { + values ("293.1, 293.1, 293.1, 360.8, 496.2", \ + "318.8, 318.8, 318.8, 386.5, 522.0", \ + "370.3, 370.3, 370.3, 438.1, 573.5", \ + "473.4, 473.4, 473.4, 541.1, 676.6", \ + "679.5, 679.5, 679.5, 747.2, 882.7"); + } + fall_power (energy_inslew_load_5x5__77) { + values ("227.5, 227.5, 227.5, 295.3, 430.7", \ + "278.8, 278.8, 278.8, 346.6, 482.0", \ + "381.4, 381.4, 381.4, 449.2, 584.6", \ + "586.6, 586.6, 586.6, 654.4, 789.8", \ + "997.0, 997.0, 997.0, 1064.8, 1200.2"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__77) { + values ("198.0, 198.0, 198.0, 265.8, 401.2", \ + "226.1, 226.1, 226.1, 293.8, 429.3", \ + "282.2, 282.2, 282.2, 349.9, 485.4", \ + "394.4, 394.4, 394.4, 462.1, 597.6", \ + "618.8, 618.8, 618.8, 686.5, 822.0"); + } + fall_power (energy_inslew_load_5x5__77) { + values ("169.9, 169.9, 169.9, 237.6, 373.1", \ + "206.9, 206.9, 206.9, 274.6, 410.0", \ + "280.7, 280.7, 280.7, 348.5, 483.9", \ + "428.5, 428.5, 428.5, 496.2, 631.7", \ + "724.0, 724.0, 724.0, 791.7, 927.2"); + } + } + internal_power (energy_neg_z_d) { + related_pin : "d" ; + rise_power (energy_inslew_load_5x5__77) { + values ("96.0, 96.0, 96.0, 163.7, 299.2", \ + "125.3, 125.3, 125.3, 193.1, 328.5", \ + "184.0, 184.0, 184.0, 251.7, 387.2", \ + "301.3, 301.3, 301.3, 369.0, 504.5", \ + "536.0, 536.0, 536.0, 603.7, 739.1"); + } + fall_power (energy_inslew_load_5x5__77) { + values ("96.6, 96.6, 96.6, 164.3, 299.8", \ + "124.5, 124.5, 124.5, 192.2, 327.6", \ + "180.1, 180.1, 180.1, 247.9, 383.3", \ + "291.5, 291.5, 291.5, 359.2, 494.7", \ + "514.3, 514.3, 514.3, 582.0, 717.4"); + } + } + } + } + + cell (nr4v0x2) { + area : 0.0 ; + cell_leakage_power : 1.8 ; + leakage_power () { + when : "((a & ((!(b) & (!(c) | !(d))) | (!(c) & !(d)))) | (b & !(c) & !(d)))" ; + value : 1.5 ; + } + leakage_power () { + when : "((a & ((b & (c ^ d)) | (!(b) & c & d))) | (!(a) & ((b & (c ^ d)) | (c & !(d)))))" ; + value : 1.7 ; + } + leakage_power () { + when : "((!(a) & !((b & !(c))) & d) | (b & c & d))" ; + value : 3.9 ; + } + leakage_power () { + when : "(!(d) & !(c) & !(b) & !(a))" ; + value : 0.0002 ; + } + pin (d) { + direction : input ; + capacitance : 11.74 ; + } + pin (c) { + direction : input ; + capacitance : 11.43 ; + } + pin (b) { + direction : input ; + capacitance : 10.81 ; + } + pin (a) { + direction : input ; + capacitance : 11.29 ; + } + pin (z) { + function : "(((!(d) & !(c)) & !(b)) & !(a))" ; + direction : output ; + capacitance : 8.74 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__78) { + values ("153.5, 153.5, 153.5, 180.8, 235.9", \ + "142.6, 142.6, 142.6, 170.3, 225.7", \ + "119.1, 119.1, 119.1, 147.2, 203.4", \ + "73.8, 73.8, 73.8, 102.0, 158.3", \ + "-14.1, -14.1, -14.1, 14.2, 70.8"); + } + rise_transition (inslew_load_5x5__78) { + values ("268.6, 268.6, 268.6, 314.7, 407.1", \ + "289.2, 289.2, 289.2, 334.9, 426.5", \ + "326.6, 326.6, 326.6, 372.6, 464.4", \ + "397.9, 397.9, 397.9, 443.7, 535.7", \ + "545.0, 545.0, 545.0, 589.8, 680.0"); + } + cell_fall (inslew_load_5x5__78) { + values ("67.7, 67.7, 67.7, 83.2, 113.4", \ + "95.3, 95.3, 95.3, 112.0, 144.0", \ + "140.8, 140.8, 140.8, 158.8, 193.5", \ + "222.9, 222.9, 222.9, 242.2, 279.6", \ + "381.5, 381.5, 381.5, 401.8, 441.5"); + } + fall_transition (inslew_load_5x5__78) { + values ("64.5, 64.5, 64.5, 82.4, 118.7", \ + "101.6, 101.6, 101.6, 119.3, 154.8", \ + "168.4, 168.4, 168.4, 186.1, 221.1", \ + "295.7, 295.7, 295.7, 313.6, 348.9", \ + "546.7, 546.7, 546.7, 564.7, 600.4"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__78) { + values ("123.5, 123.5, 123.5, 151.1, 206.4", \ + "119.0, 119.0, 119.0, 147.1, 202.9", \ + "107.8, 107.8, 107.8, 136.3, 192.9", \ + "84.6, 84.6, 84.6, 113.7, 171.6", \ + "36.5, 36.5, 36.5, 66.8, 126.3"); + } + rise_transition (inslew_load_5x5__78) { + values ("212.5, 212.5, 212.5, 258.8, 351.9", \ + "236.1, 236.1, 236.1, 282.1, 374.4", \ + "279.0, 279.0, 279.0, 324.6, 416.7", \ + "365.6, 365.6, 365.6, 410.4, 500.7", \ + "543.1, 543.1, 543.1, 587.0, 675.3"); + } + cell_fall (inslew_load_5x5__78) { + values ("59.8, 59.8, 59.8, 75.7, 106.4", \ + "78.5, 78.5, 78.5, 96.1, 129.2", \ + "107.2, 107.2, 107.2, 126.7, 163.4", \ + "156.2, 156.2, 156.2, 177.6, 218.3", \ + "248.9, 248.9, 248.9, 271.7, 315.7"); + } + fall_transition (inslew_load_5x5__78) { + values ("56.3, 56.3, 56.3, 74.2, 110.2", \ + "85.3, 85.3, 85.3, 103.0, 138.2", \ + "137.8, 137.8, 137.8, 155.7, 191.0", \ + "237.6, 237.6, 237.6, 256.0, 292.1", \ + "434.1, 434.1, 434.1, 452.8, 489.8"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__78) { + values ("84.0, 84.0, 84.0, 112.1, 167.9", \ + "85.9, 85.9, 85.9, 114.7, 171.3", \ + "86.8, 86.8, 86.8, 116.5, 174.6", \ + "87.4, 87.4, 87.4, 118.4, 178.5", \ + "85.0, 85.0, 85.0, 116.9, 180.1"); + } + rise_transition (inslew_load_5x5__78) { + values ("145.4, 145.4, 145.4, 191.9, 285.6", \ + "174.0, 174.0, 174.0, 220.0, 312.9", \ + "227.4, 227.4, 227.4, 272.6, 364.0", \ + "335.0, 335.0, 335.0, 381.4, 470.6", \ + "550.9, 550.9, 550.9, 595.0, 684.4"); + } + cell_fall (inslew_load_5x5__78) { + values ("48.7, 48.7, 48.7, 65.5, 96.8", \ + "59.4, 59.4, 59.4, 78.5, 113.1", \ + "73.0, 73.0, 73.0, 94.8, 134.4", \ + "92.8, 92.8, 92.8, 117.2, 162.4", \ + "127.2, 127.2, 127.2, 153.6, 203.6"); + } + fall_transition (inslew_load_5x5__78) { + values ("45.4, 45.4, 45.4, 63.2, 99.0", \ + "68.0, 68.0, 68.0, 86.0, 121.2", \ + "108.8, 108.8, 108.8, 127.5, 163.4", \ + "186.2, 186.2, 186.2, 205.7, 243.2", \ + "338.2, 338.2, 338.2, 358.3, 397.4"); + } + } + timing (maxd_z_d_negative_unate) { + related_pin : "d" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__78) { + values ("35.1, 35.1, 35.1, 64.7, 121.7", \ + "40.9, 40.9, 40.9, 72.0, 130.6", \ + "49.4, 49.4, 49.4, 78.6, 139.5", \ + "63.4, 63.4, 63.4, 97.4, 160.2", \ + "88.5, 88.5, 88.5, 124.1, 192.3"); + } + rise_transition (inslew_load_5x5__78) { + values ("67.4, 67.4, 67.4, 113.1, 207.0", \ + "101.3, 101.3, 101.3, 147.1, 239.9", \ + "161.2, 161.2, 161.2, 201.7, 292.9", \ + "279.1, 279.1, 279.1, 324.3, 412.1", \ + "513.0, 513.0, 513.0, 558.7, 649.4"); + } + cell_fall (inslew_load_5x5__78) { + values ("29.6, 29.6, 29.6, 49.0, 81.9", \ + "33.7, 33.7, 33.7, 56.2, 93.7", \ + "36.8, 36.8, 36.8, 62.5, 106.3", \ + "38.3, 38.3, 38.3, 66.7, 117.3", \ + "38.3, 38.3, 38.3, 68.7, 125.0"); + } + fall_transition (inslew_load_5x5__78) { + values ("28.0, 28.0, 28.0, 46.3, 81.8", \ + "46.9, 46.9, 46.9, 65.8, 101.4", \ + "80.9, 80.9, 80.9, 100.8, 137.9", \ + "145.7, 145.7, 145.7, 166.6, 206.0", \ + "273.2, 273.2, 273.2, 294.9, 336.5"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__78) { + values ("622.6, 622.6, 622.6, 731.8, 950.2", \ + "663.4, 663.4, 663.4, 772.6, 991.0", \ + "744.8, 744.8, 744.8, 854.0, 1072.4", \ + "907.7, 907.7, 907.7, 1017.0, 1235.4", \ + "1233.6, 1233.6, 1233.6, 1342.8, 1561.2"); + } + fall_power (energy_inslew_load_5x5__78) { + values ("463.9, 463.9, 463.9, 573.1, 791.5", \ + "593.9, 593.9, 593.9, 703.1, 921.6", \ + "854.1, 854.1, 854.1, 963.3, 1181.7", \ + "1374.4, 1374.4, 1374.4, 1483.6, 1702.0", \ + "2415.0, 2415.0, 2415.0, 2524.2, 2742.6"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__78) { + values ("490.0, 490.0, 490.0, 599.2, 817.6", \ + "534.7, 534.7, 534.7, 643.9, 862.3", \ + "624.2, 624.2, 624.2, 733.4, 951.8", \ + "803.0, 803.0, 803.0, 912.2, 1130.6", \ + "1160.7, 1160.7, 1160.7, 1269.9, 1488.3"); + } + fall_power (energy_inslew_load_5x5__78) { + values ("373.8, 373.8, 373.8, 483.0, 701.4", \ + "464.2, 464.2, 464.2, 573.4, 791.8", \ + "645.0, 645.0, 645.0, 754.2, 972.6", \ + "1006.6, 1006.6, 1006.6, 1115.9, 1334.3", \ + "1729.9, 1729.9, 1729.9, 1839.2, 2057.6"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__78) { + values ("334.8, 334.8, 334.8, 444.0, 662.4", \ + "387.1, 387.1, 387.1, 496.3, 714.7", \ + "491.6, 491.6, 491.6, 600.8, 819.2", \ + "700.8, 700.8, 700.8, 810.0, 1028.4", \ + "1119.1, 1119.1, 1119.1, 1228.3, 1446.7"); + } + fall_power (energy_inslew_load_5x5__78) { + values ("276.0, 276.0, 276.0, 385.2, 603.6", \ + "336.3, 336.3, 336.3, 445.5, 663.9", \ + "457.0, 457.0, 457.0, 566.2, 784.6", \ + "698.4, 698.4, 698.4, 807.6, 1026.0", \ + "1181.3, 1181.3, 1181.3, 1290.5, 1508.9"); + } + } + internal_power (energy_neg_z_d) { + related_pin : "d" ; + rise_power (energy_inslew_load_5x5__78) { + values ("161.0, 161.0, 161.0, 270.2, 488.6", \ + "214.7, 214.7, 214.7, 323.9, 542.3", \ + "322.0, 322.0, 322.0, 431.2, 649.6", \ + "536.8, 536.8, 536.8, 646.0, 864.4", \ + "966.3, 966.3, 966.3, 1075.5, 1293.9"); + } + fall_power (energy_inslew_load_5x5__78) { + values ("156.6, 156.6, 156.6, 265.8, 484.2", \ + "202.1, 202.1, 202.1, 311.3, 529.7", \ + "293.0, 293.0, 293.0, 402.2, 620.6", \ + "474.9, 474.9, 474.9, 584.1, 802.5", \ + "838.7, 838.7, 838.7, 947.9, 1166.3"); + } + } + } + } + + cell (nr4v1x05) { + area : 0.0 ; + cell_leakage_power : 1 ; + leakage_power () { + when : "(a & ((b & (c ^ d)) | (!(b) & c & d)))" ; + value : 0.79 ; + } + leakage_power () { + when : "(!(d) & !(c) & !(b) & a)" ; + value : 0.67 ; + } + leakage_power () { + when : "(b & c & d)" ; + value : 2 ; + } + leakage_power () { + when : "((a & ((b & !(c) & !(d)) | (!(b) & (c ^ d)))) | (b & !(c) & !(d)))" ; + value : 0.7 ; + } + leakage_power () { + when : "(!(a) & ((b & (c ^ d)) | (c & !(d))))" ; + value : 0.8 ; + } + leakage_power () { + when : "(!(a) & !(b) & d)" ; + value : 2.1 ; + } + leakage_power () { + when : "(!(d) & !(c) & !(b) & !(a))" ; + value : 0.00013 ; + } + pin (d) { + direction : input ; + capacitance : 3.53 ; + } + pin (c) { + direction : input ; + capacitance : 4.24 ; + } + pin (b) { + direction : input ; + capacitance : 4.08 ; + } + pin (a) { + direction : input ; + capacitance : 3.55 ; + } + pin (z) { + function : "(((!(d) & !(c)) & !(b)) & !(a))" ; + direction : output ; + capacitance : 4.38 ; + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__79) { + values ("147.5, 147.5, 147.5, 187.1, 266.4", \ + "146.4, 146.4, 146.4, 186.4, 265.9", \ + "142.4, 142.4, 142.4, 182.8, 263.0", \ + "135.4, 135.4, 135.4, 175.7, 256.2", \ + "123.4, 123.4, 123.4, 163.7, 244.1"); + } + rise_transition (inslew_load_5x5__79) { + values ("283.7, 283.7, 283.7, 355.7, 500.1", \ + "321.5, 321.5, 321.5, 393.0, 536.6", \ + "392.5, 392.5, 392.5, 464.3, 607.9", \ + "531.3, 531.3, 531.3, 603.0, 746.9", \ + "810.9, 810.9, 810.9, 881.3, 1024.0"); + } + cell_fall (inslew_load_5x5__79) { + values ("47.6, 47.6, 47.6, 63.3, 92.9", \ + "61.8, 61.8, 61.8, 79.3, 111.7", \ + "84.5, 84.5, 84.5, 104.0, 140.2", \ + "125.5, 125.5, 125.5, 146.6, 186.7", \ + "204.4, 204.4, 204.4, 226.7, 269.8"); + } + fall_transition (inslew_load_5x5__79) { + values ("51.8, 51.8, 51.8, 68.9, 103.5", \ + "78.0, 78.0, 78.0, 95.2, 129.2", \ + "127.3, 127.3, 127.3, 145.0, 179.4", \ + "223.7, 223.7, 223.7, 241.8, 277.2", \ + "414.9, 414.9, 414.9, 433.3, 469.7"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__79) { + values ("126.0, 126.0, 126.0, 165.9, 245.6", \ + "135.2, 135.2, 135.2, 175.5, 255.5", \ + "150.1, 150.1, 150.1, 190.7, 271.4", \ + "179.0, 179.0, 179.0, 219.9, 301.1", \ + "234.9, 234.9, 234.9, 276.4, 359.7"); + } + rise_transition (inslew_load_5x5__79) { + values ("237.4, 237.4, 237.4, 310.2, 456.4", \ + "284.2, 284.2, 284.2, 356.5, 501.9", \ + "371.1, 371.1, 371.1, 443.1, 587.9", \ + "543.5, 543.5, 543.5, 614.6, 757.9", \ + "889.5, 889.5, 889.5, 959.7, 1100.9"); + } + cell_fall (inslew_load_5x5__79) { + values ("40.5, 40.5, 40.5, 56.8, 86.9", \ + "45.6, 45.6, 45.6, 64.5, 98.4", \ + "49.5, 49.5, 49.5, 71.5, 111.0", \ + "51.4, 51.4, 51.4, 76.5, 122.2", \ + "50.7, 50.7, 50.7, 78.1, 129.6"); + } + fall_transition (inslew_load_5x5__79) { + values ("44.7, 44.7, 44.7, 61.8, 96.3", \ + "63.3, 63.3, 63.3, 80.9, 115.0", \ + "97.7, 97.7, 97.7, 116.2, 151.6", \ + "164.0, 164.0, 164.0, 183.6, 221.1", \ + "294.6, 294.6, 294.6, 315.1, 354.7"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__79) { + values ("93.4, 93.4, 93.4, 133.8, 214.0", \ + "105.8, 105.8, 105.8, 146.7, 227.5", \ + "128.4, 128.4, 128.4, 170.5, 252.3", \ + "170.9, 170.9, 170.9, 213.8, 297.7", \ + "252.8, 252.8, 252.8, 296.9, 383.3"); + } + rise_transition (inslew_load_5x5__79) { + values ("175.3, 175.3, 175.3, 248.7, 396.7", \ + "220.5, 220.5, 220.5, 293.3, 440.3", \ + "309.0, 309.0, 309.0, 380.7, 525.7", \ + "484.8, 484.8, 484.8, 555.3, 697.5", \ + "830.3, 830.3, 830.3, 905.4, 1045.6"); + } + cell_fall (inslew_load_5x5__79) { + values ("34.4, 34.4, 34.4, 51.4, 81.9", \ + "35.4, 35.4, 35.4, 55.5, 90.5", \ + "31.1, 31.1, 31.1, 55.1, 96.8", \ + "16.4, 16.4, 16.4, 44.3, 93.8", \ + "-17.7, -17.7, -17.7, 13.2, 70.1"); + } + fall_transition (inslew_load_5x5__79) { + values ("38.9, 38.9, 38.9, 56.1, 90.5", \ + "54.6, 54.6, 54.6, 72.5, 106.8", \ + "83.3, 83.3, 83.3, 102.5, 138.6", \ + "138.0, 138.0, 138.0, 158.7, 197.6", \ + "245.2, 245.2, 245.2, 267.1, 309.1"); + } + } + timing (maxd_z_d_negative_unate) { + related_pin : "d" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__79) { + values ("55.6, 55.6, 55.6, 97.2, 178.2", \ + "70.0, 70.0, 70.0, 113.0, 195.3", \ + "100.1, 100.1, 100.1, 144.3, 229.3", \ + "158.2, 158.2, 158.2, 202.7, 291.1", \ + "268.0, 268.0, 268.0, 315.1, 406.2"); + } + rise_transition (inslew_load_5x5__79) { + values ("106.7, 106.7, 106.7, 180.6, 330.6", \ + "152.9, 152.9, 152.9, 226.0, 374.6", \ + "245.3, 245.3, 245.3, 318.3, 464.0", \ + "429.0, 429.0, 429.0, 498.6, 645.4", \ + "788.2, 788.2, 788.2, 860.1, 1003.0"); + } + cell_fall (inslew_load_5x5__79) { + values ("24.1, 24.1, 24.1, 42.7, 74.2", \ + "20.7, 20.7, 20.7, 43.2, 80.1", \ + "8.5, 8.5, 8.5, 35.8, 80.6", \ + "-20.7, -20.7, -20.7, 11.2, 65.5", \ + "-83.1, -83.1, -83.1, -47.4, 16.2"); + } + fall_transition (inslew_load_5x5__79) { + values ("29.8, 29.8, 29.8, 47.3, 81.6", \ + "42.9, 42.9, 42.9, 61.6, 96.3", \ + "66.7, 66.7, 66.7, 87.2, 124.3", \ + "111.9, 111.9, 111.9, 134.3, 175.2", \ + "200.4, 200.4, 200.4, 224.5, 269.3"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__79) { + values ("212.0, 212.0, 212.0, 266.8, 376.3", \ + "237.8, 237.8, 237.8, 292.6, 402.2", \ + "289.6, 289.6, 289.6, 344.4, 453.9", \ + "393.1, 393.1, 393.1, 447.8, 557.4", \ + "600.0, 600.0, 600.0, 654.8, 764.4"); + } + fall_power (energy_inslew_load_5x5__79) { + values ("149.3, 149.3, 149.3, 204.1, 313.6", \ + "194.8, 194.8, 194.8, 249.6, 359.2", \ + "286.0, 286.0, 286.0, 340.8, 450.3", \ + "468.2, 468.2, 468.2, 523.0, 632.6", \ + "832.8, 832.8, 832.8, 887.6, 997.1"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__79) { + values ("178.7, 178.7, 178.7, 233.5, 343.1", \ + "209.4, 209.4, 209.4, 264.1, 373.7", \ + "270.6, 270.6, 270.6, 325.4, 435.0", \ + "393.2, 393.2, 393.2, 448.0, 557.6", \ + "638.4, 638.4, 638.4, 693.2, 802.7"); + } + fall_power (energy_inslew_load_5x5__79) { + values ("118.6, 118.6, 118.6, 173.4, 283.0", \ + "143.5, 143.5, 143.5, 198.3, 307.8", \ + "193.2, 193.2, 193.2, 248.0, 357.6", \ + "292.8, 292.8, 292.8, 347.5, 457.1", \ + "491.8, 491.8, 491.8, 546.6, 656.1"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__79) { + values ("132.0, 132.0, 132.0, 186.8, 296.4", \ + "161.0, 161.0, 161.0, 215.8, 325.4", \ + "219.0, 219.0, 219.0, 273.8, 383.4", \ + "335.1, 335.1, 335.1, 389.8, 499.4", \ + "567.1, 567.1, 567.1, 621.9, 731.4"); + } + fall_power (energy_inslew_load_5x5__79) { + values ("97.4, 97.4, 97.4, 152.2, 261.8", \ + "115.3, 115.3, 115.3, 170.0, 279.6", \ + "150.9, 150.9, 150.9, 205.7, 315.3", \ + "222.3, 222.3, 222.3, 277.1, 386.7", \ + "365.1, 365.1, 365.1, 419.9, 529.4"); + } + } + internal_power (energy_neg_z_d) { + related_pin : "d" ; + rise_power (energy_inslew_load_5x5__79) { + values ("83.6, 83.6, 83.6, 138.4, 247.9", \ + "111.9, 111.9, 111.9, 166.7, 276.3", \ + "168.6, 168.6, 168.6, 223.4, 332.9", \ + "282.0, 282.0, 282.0, 336.7, 446.3", \ + "508.7, 508.7, 508.7, 563.4, 673.0"); + } + fall_power (energy_inslew_load_5x5__79) { + values ("67.2, 67.2, 67.2, 122.0, 231.5", \ + "80.1, 80.1, 80.1, 134.8, 244.4", \ + "105.8, 105.8, 105.8, 160.6, 270.1", \ + "157.3, 157.3, 157.3, 212.1, 321.6", \ + "260.2, 260.2, 260.2, 315.0, 424.6"); + } + } + } + } + + cell (oai211v0x05) { + area : 0.0 ; + cell_leakage_power : 0.95 ; + leakage_power () { + when : "(!(c) & b & a2 & a1)" ; + value : 9.4e-05 ; + } + leakage_power () { + when : "(c & !(b) & a2 & a1)" ; + value : 7.6e-05 ; + } + leakage_power () { + when : "(c & b & !(a2) & a1)" ; + value : 5.1 ; + } + leakage_power () { + when : "(a2 & b & c)" ; + value : 5.3 ; + } + leakage_power () { + when : "((a1 ^ a2) & b & !(c))" ; + value : 4.8e-05 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(b) & c)" ; + value : 3.9e-05 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(b) & !(c))" ; + value : 1.2e-06 ; + } + leakage_power () { + when : "(c & b & !(a2) & !(a1))" ; + value : 7.3e-05 ; + } + leakage_power () { + when : "((a1 & a2 & !(b) & !(c)) | (!(a1) & !(a2) & b & !(c)))" ; + value : 1.6e-06 ; + } + leakage_power () { + when : "(c & !(b) & !(a2) & !(a1))" ; + value : 1.5e-06 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a2) & !(a1))" ; + value : 7e-07 ; + } + pin (c) { + direction : input ; + capacitance : 3.06 ; + } + pin (b) { + direction : input ; + capacitance : 2.85 ; + } + pin (a2) { + direction : input ; + capacitance : 3.62 ; + } + pin (a1) { + direction : input ; + capacitance : 3.59 ; + } + pin (z) { + function : "(((!(a2) & !(a1)) | !(b)) | !(c))" ; + direction : output ; + capacitance : 4.29 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__80) { + values ("88.2, 88.2, 88.2, 116.4, 172.7", \ + "103.5, 103.5, 103.5, 132.0, 188.7", \ + "130.9, 130.9, 130.9, 160.2, 217.5", \ + "184.5, 184.5, 184.5, 214.0, 272.2", \ + "290.5, 290.5, 290.5, 320.4, 379.7"); + } + rise_transition (inslew_load_5x5__80) { + values ("167.0, 167.0, 167.0, 218.3, 321.6", \ + "218.7, 218.7, 218.7, 269.5, 372.2", \ + "317.7, 317.7, 317.7, 367.9, 469.2", \ + "514.9, 514.9, 514.9, 564.4, 664.1", \ + "909.6, 909.6, 909.6, 958.6, 1057.0"); + } + cell_fall (inslew_load_5x5__80) { + values ("41.7, 41.7, 41.7, 57.1, 87.5", \ + "39.8, 39.8, 39.8, 56.1, 87.6", \ + "33.0, 33.0, 33.0, 50.8, 84.6", \ + "15.6, 15.6, 15.6, 35.3, 72.5", \ + "-22.8, -22.8, -22.8, -1.5, 39.2"); + } + fall_transition (inslew_load_5x5__80) { + values ("71.0, 71.0, 71.0, 94.0, 140.3", \ + "86.6, 86.6, 86.6, 109.2, 154.8", \ + "117.0, 117.0, 117.0, 139.7, 185.3", \ + "177.6, 177.6, 177.6, 200.6, 246.1", \ + "298.1, 298.1, 298.1, 321.4, 367.6"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__80) { + values ("72.6, 72.6, 72.6, 101.8, 159.1", \ + "96.8, 96.8, 96.8, 126.9, 185.6", \ + "138.3, 138.3, 138.3, 169.9, 230.6", \ + "216.5, 216.5, 216.5, 249.3, 313.0", \ + "369.6, 369.6, 369.6, 403.5, 469.6"); + } + rise_transition (inslew_load_5x5__80) { + values ("126.0, 126.0, 126.0, 178.2, 284.4", \ + "182.3, 182.3, 182.3, 233.3, 337.2", \ + "284.7, 284.7, 284.7, 335.9, 439.3", \ + "486.2, 486.2, 486.2, 537.3, 639.5", \ + "886.2, 886.2, 886.2, 937.5, 1039.8"); + } + cell_fall (inslew_load_5x5__80) { + values ("34.3, 34.3, 34.3, 50.0, 80.5", \ + "27.5, 27.5, 27.5, 44.5, 76.5", \ + "10.0, 10.0, 10.0, 29.3, 64.7", \ + "-30.7, -30.7, -30.7, -8.3, 32.4", \ + "-118.6, -118.6, -118.6, -93.1, -46.0"); + } + fall_transition (inslew_load_5x5__80) { + values ("60.6, 60.6, 60.6, 83.5, 129.7", \ + "70.4, 70.4, 70.4, 93.3, 138.7", \ + "89.8, 89.8, 89.8, 112.8, 158.1", \ + "127.4, 127.4, 127.4, 151.1, 197.4", \ + "201.0, 201.0, 201.0, 225.5, 273.3"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__80) { + values ("56.9, 56.9, 56.9, 83.2, 133.5", \ + "75.2, 75.2, 75.2, 103.7, 156.6", \ + "105.6, 105.6, 105.6, 136.5, 194.0", \ + "161.8, 161.8, 161.8, 194.9, 257.3", \ + "271.4, 271.4, 271.4, 305.9, 372.4"); + } + rise_transition (inslew_load_5x5__80) { + values ("112.4, 112.4, 112.4, 167.1, 275.2", \ + "162.1, 162.1, 162.1, 216.8, 326.2", \ + "254.1, 254.1, 254.1, 309.5, 418.9", \ + "433.7, 433.7, 433.7, 489.7, 600.6", \ + "790.4, 790.4, 790.4, 846.8, 959.0"); + } + cell_fall (inslew_load_5x5__80) { + values ("26.8, 26.8, 26.8, 43.6, 74.9", \ + "22.5, 22.5, 22.5, 41.7, 75.9", \ + "9.0, 9.0, 9.0, 31.6, 71.3", \ + "-23.5, -23.5, -23.5, 2.9, 49.6", \ + "-93.6, -93.6, -93.6, -63.9, -9.6"); + } + fall_transition (inslew_load_5x5__80) { + values ("46.4, 46.4, 46.4, 69.4, 115.4", \ + "57.8, 57.8, 57.8, 81.0, 126.9", \ + "79.3, 79.3, 79.3, 103.3, 149.8", \ + "120.7, 120.7, 120.7, 145.7, 194.0", \ + "201.9, 201.9, 201.9, 227.9, 278.3"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__80) { + values ("44.1, 44.1, 44.1, 71.4, 122.0", \ + "57.2, 57.2, 57.2, 87.2, 141.4", \ + "78.1, 78.1, 78.1, 111.0, 170.7", \ + "116.2, 116.2, 116.2, 151.5, 217.1", \ + "190.0, 190.0, 190.0, 227.0, 297.5"); + } + rise_transition (inslew_load_5x5__80) { + values ("87.6, 87.6, 87.6, 141.9, 250.4", \ + "129.7, 129.7, 129.7, 184.8, 293.2", \ + "207.6, 207.6, 207.6, 263.6, 373.7", \ + "360.0, 360.0, 360.0, 416.6, 528.5", \ + "662.8, 662.8, 662.8, 719.8, 833.1"); + } + cell_fall (inslew_load_5x5__80) { + values ("22.5, 22.5, 22.5, 40.7, 73.4", \ + "20.5, 20.5, 20.5, 42.2, 78.9", \ + "11.7, 11.7, 11.7, 37.5, 81.2", \ + "-10.2, -10.2, -10.2, 19.5, 71.3", \ + "-57.3, -57.3, -57.3, -24.5, 35.0"); + } + fall_transition (inslew_load_5x5__80) { + values ("37.6, 37.6, 37.6, 60.5, 107.2", \ + "50.6, 50.6, 50.6, 74.6, 120.9", \ + "75.0, 75.0, 75.0, 100.1, 148.1", \ + "122.2, 122.2, 122.2, 148.5, 198.8", \ + "215.6, 215.6, 215.6, 242.8, 295.4"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__80) { + values ("176.0, 176.0, 176.0, 229.7, 337.0", \ + "223.5, 223.5, 223.5, 277.2, 384.5", \ + "318.5, 318.5, 318.5, 372.1, 479.4", \ + "508.4, 508.4, 508.4, 562.1, 669.4", \ + "888.3, 888.3, 888.3, 941.9, 1049.2"); + } + fall_power (energy_inslew_load_5x5__80) { + values ("154.1, 154.1, 154.1, 207.7, 315.0", \ + "180.2, 180.2, 180.2, 233.9, 341.2", \ + "232.5, 232.5, 232.5, 286.2, 393.5", \ + "337.1, 337.1, 337.1, 390.8, 498.1", \ + "546.3, 546.3, 546.3, 600.0, 707.3"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__80) { + values ("135.9, 135.9, 135.9, 189.5, 296.8", \ + "179.0, 179.0, 179.0, 232.6, 339.9", \ + "265.1, 265.1, 265.1, 318.8, 426.1", \ + "437.5, 437.5, 437.5, 491.1, 598.4", \ + "782.2, 782.2, 782.2, 835.9, 943.2"); + } + fall_power (energy_inslew_load_5x5__80) { + values ("127.4, 127.4, 127.4, 181.0, 288.3", \ + "140.7, 140.7, 140.7, 194.4, 301.7", \ + "167.4, 167.4, 167.4, 221.0, 328.3", \ + "220.8, 220.8, 220.8, 274.4, 381.7", \ + "327.5, 327.5, 327.5, 381.1, 488.4"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__80) { + values ("107.4, 107.4, 107.4, 161.0, 268.3", \ + "142.9, 142.9, 142.9, 196.6, 303.9", \ + "214.1, 214.1, 214.1, 267.7, 375.0", \ + "356.3, 356.3, 356.3, 409.9, 517.2", \ + "640.8, 640.8, 640.8, 694.4, 801.7"); + } + fall_power (energy_inslew_load_5x5__80) { + values ("92.9, 92.9, 92.9, 146.6, 253.9", \ + "106.6, 106.6, 106.6, 160.3, 267.6", \ + "134.0, 134.0, 134.0, 187.6, 294.9", \ + "188.7, 188.7, 188.7, 242.4, 349.7", \ + "298.3, 298.3, 298.3, 351.9, 459.2"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__80) { + values ("81.2, 81.2, 81.2, 134.8, 242.1", \ + "110.5, 110.5, 110.5, 164.1, 271.4", \ + "169.0, 169.0, 169.0, 222.6, 329.9", \ + "286.0, 286.0, 286.0, 339.7, 447.0", \ + "520.1, 520.1, 520.1, 573.8, 681.1"); + } + fall_power (energy_inslew_load_5x5__80) { + values ("70.6, 70.6, 70.6, 124.2, 231.5", \ + "85.8, 85.8, 85.8, 139.4, 246.7", \ + "116.2, 116.2, 116.2, 169.8, 277.1", \ + "177.0, 177.0, 177.0, 230.6, 337.9", \ + "298.5, 298.5, 298.5, 352.2, 459.5"); + } + } + } + } + + cell (oai21a2bv0x05) { + area : 0.0 ; + cell_leakage_power : 5.1 ; + leakage_power () { + when : "(!(b) & a2 & a1)" ; + value : 5.6 ; + } + leakage_power () { + when : "(a2 & b)" ; + value : 9.5 ; + } + leakage_power () { + when : "(!(b) & a2 & !(a1))" ; + value : 4.9 ; + } + leakage_power () { + when : "(!(a2) & b)" ; + value : 4.7 ; + } + leakage_power () { + when : "(!(a2) & !(b))" ; + value : 0.97 ; + } + pin (b) { + direction : input ; + capacitance : 2.55 ; + } + pin (a2) { + direction : input ; + capacitance : 2.65 ; + } + pin (a1) { + direction : input ; + capacitance : 3.17 ; + } + pin (z) { + function : "(!((a1 | !(a2))) | b)" ; + direction : output ; + capacitance : 2.73 ; + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__81) { + values ("72.4, 72.4, 72.4, 91.5, 128.2", \ + "81.0, 81.0, 81.0, 100.5, 137.9", \ + "91.2, 91.2, 91.2, 111.3, 149.6", \ + "104.5, 104.5, 104.5, 125.5, 165.5", \ + "125.3, 125.3, 125.3, 147.3, 189.3"); + } + rise_transition (inslew_load_5x5__81) { + values ("73.0, 73.0, 73.0, 106.0, 173.0", \ + "89.3, 89.3, 89.3, 122.2, 188.6", \ + "117.8, 117.8, 117.8, 151.2, 216.3", \ + "170.6, 170.6, 170.6, 203.1, 269.5", \ + "272.2, 272.2, 272.2, 305.0, 370.1"); + } + cell_fall (inslew_load_5x5__81) { + values ("66.3, 66.3, 66.3, 79.4, 103.7", \ + "71.3, 71.3, 71.3, 85.3, 110.9", \ + "76.1, 76.1, 76.1, 91.3, 119.0", \ + "80.2, 80.2, 80.2, 97.1, 127.8", \ + "84.4, 84.4, 84.4, 102.6, 136.7"); + } + fall_transition (inslew_load_5x5__81) { + values ("51.3, 51.3, 51.3, 66.5, 96.8", \ + "59.6, 59.6, 59.6, 75.0, 105.1", \ + "75.2, 75.2, 75.2, 90.8, 121.2", \ + "105.3, 105.3, 105.3, 121.3, 152.4", \ + "164.3, 164.3, 164.3, 181.0, 213.0"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__81) { + values ("48.1, 48.1, 48.1, 67.3, 103.1", \ + "51.5, 51.5, 51.5, 71.7, 108.4", \ + "52.2, 52.2, 52.2, 73.8, 112.5", \ + "48.2, 48.2, 48.2, 71.4, 113.2", \ + "35.4, 35.4, 35.4, 60.3, 105.9"); + } + rise_transition (inslew_load_5x5__81) { + values ("50.8, 50.8, 50.8, 88.3, 162.5", \ + "64.6, 64.6, 64.6, 101.9, 176.0", \ + "87.4, 87.4, 87.4, 125.1, 199.1", \ + "129.0, 129.0, 129.0, 167.1, 242.0", \ + "209.0, 209.0, 209.0, 247.5, 323.4"); + } + cell_fall (inslew_load_5x5__81) { + values ("51.7, 51.7, 51.7, 67.4, 94.0", \ + "59.0, 59.0, 59.0, 76.4, 105.8", \ + "69.4, 69.4, 69.4, 88.7, 122.0", \ + "85.9, 85.9, 85.9, 107.8, 145.6", \ + "116.9, 116.9, 116.9, 139.8, 182.9"); + } + fall_transition (inslew_load_5x5__81) { + values ("36.8, 36.8, 36.8, 52.6, 83.0", \ + "46.8, 46.8, 46.8, 63.0, 94.0", \ + "65.4, 65.4, 65.4, 82.3, 114.3", \ + "101.6, 101.6, 101.6, 119.0, 152.5", \ + "172.8, 172.8, 172.8, 191.0, 225.9"); + } + } + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__81) { + values ("60.6, 60.6, 60.6, 78.8, 114.9", \ + "67.3, 67.3, 67.3, 86.0, 122.6", \ + "79.2, 79.2, 79.2, 98.3, 135.7", \ + "101.6, 101.6, 101.6, 121.3, 159.9", \ + "145.3, 145.3, 145.3, 165.4, 205.2"); + } + rise_transition (inslew_load_5x5__81) { + values ("120.3, 120.3, 120.3, 152.7, 218.1", \ + "158.3, 158.3, 158.3, 190.3, 254.9", \ + "233.0, 233.0, 233.0, 264.4, 327.8", \ + "380.2, 380.2, 380.2, 413.5, 475.9", \ + "675.8, 675.8, 675.8, 707.2, 769.9"); + } + cell_fall (inslew_load_5x5__81) { + values ("36.4, 36.4, 36.4, 48.1, 70.6", \ + "39.1, 39.1, 39.1, 51.8, 75.9", \ + "41.3, 41.3, 41.3, 55.3, 81.7", \ + "42.7, 42.7, 42.7, 57.9, 86.9", \ + "43.2, 43.2, 43.2, 59.3, 90.5"); + } + fall_transition (inslew_load_5x5__81) { + values ("54.4, 54.4, 54.4, 69.5, 100.0", \ + "73.9, 73.9, 73.9, 89.0, 119.3", \ + "111.9, 111.9, 111.9, 127.2, 157.3", \ + "186.8, 186.8, 186.8, 202.3, 232.9", \ + "335.8, 335.8, 335.8, 351.5, 382.6"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__81) { + values ("167.6, 167.6, 167.6, 201.8, 270.1", \ + "201.1, 201.1, 201.1, 235.2, 303.6", \ + "266.9, 266.9, 266.9, 301.0, 369.4", \ + "397.2, 397.2, 397.2, 431.4, 499.7", \ + "656.9, 656.9, 656.9, 691.1, 759.4"); + } + fall_power (energy_inslew_load_5x5__81) { + values ("187.8, 187.8, 187.8, 222.0, 290.4", \ + "226.5, 226.5, 226.5, 260.7, 329.0", \ + "303.1, 303.1, 303.1, 337.2, 405.6", \ + "455.6, 455.6, 455.6, 489.7, 558.1", \ + "760.2, 760.2, 760.2, 794.3, 862.7"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__81) { + values ("108.9, 108.9, 108.9, 143.1, 211.5", \ + "134.2, 134.2, 134.2, 168.4, 236.8", \ + "184.0, 184.0, 184.0, 218.2, 286.5", \ + "282.9, 282.9, 282.9, 317.1, 385.5", \ + "480.3, 480.3, 480.3, 514.5, 582.9"); + } + fall_power (energy_inslew_load_5x5__81) { + values ("126.2, 126.2, 126.2, 160.4, 228.8", \ + "164.6, 164.6, 164.6, 198.8, 267.2", \ + "240.6, 240.6, 240.6, 274.8, 343.1", \ + "392.1, 392.1, 392.1, 426.3, 494.6", \ + "694.7, 694.7, 694.7, 728.9, 797.3"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__81) { + values ("123.2, 123.2, 123.2, 157.4, 225.7", \ + "157.4, 157.4, 157.4, 191.6, 260.0", \ + "225.9, 225.9, 225.9, 260.1, 328.4", \ + "362.9, 362.9, 362.9, 397.0, 465.4", \ + "636.8, 636.8, 636.8, 670.9, 739.3"); + } + fall_power (energy_inslew_load_5x5__81) { + values ("110.1, 110.1, 110.1, 144.3, 212.7", \ + "139.3, 139.3, 139.3, 173.5, 241.9", \ + "197.7, 197.7, 197.7, 231.9, 300.3", \ + "314.5, 314.5, 314.5, 348.7, 417.1", \ + "548.1, 548.1, 548.1, 582.3, 650.6"); + } + } + } + } + + cell (oai21a2v0x05) { + area : 0.0 ; + cell_leakage_power : 2.3 ; + leakage_power () { + when : "(b & a2 & a1)" ; + value : 5.6 ; + } + leakage_power () { + when : "(!(b) & !(a2) & a1)" ; + value : 0.00016 ; + } + leakage_power () { + when : "((!(a1) & a2) | (a2 & !(b)))" ; + value : 4.9 ; + } + leakage_power () { + when : "(!(a2) & b)" ; + value : 0.97 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 0.0001 ; + } + pin (b) { + direction : input ; + capacitance : 2.37 ; + } + pin (a2) { + direction : input ; + capacitance : 2.78 ; + } + pin (a1) { + direction : input ; + capacitance : 3.13 ; + } + pin (z) { + function : "(!(b) | (!(a1) & a2))" ; + direction : output ; + capacitance : 2.82 ; + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__82) { + values ("66.6, 66.6, 66.6, 86.1, 123.8", \ + "74.7, 74.7, 74.7, 94.7, 133.0", \ + "84.5, 84.5, 84.5, 105.1, 144.4", \ + "97.5, 97.5, 97.5, 119.0, 160.1", \ + "118.5, 118.5, 118.5, 141.1, 184.3"); + } + rise_transition (inslew_load_5x5__82) { + values ("69.0, 69.0, 69.0, 103.1, 172.5", \ + "85.8, 85.8, 85.8, 119.5, 188.1", \ + "114.2, 114.2, 114.2, 148.4, 215.7", \ + "167.0, 167.0, 167.0, 200.6, 268.8", \ + "268.9, 268.9, 268.9, 302.7, 369.8"); + } + cell_fall (inslew_load_5x5__82) { + values ("61.9, 61.9, 61.9, 75.2, 99.7", \ + "66.7, 66.7, 66.7, 80.8, 106.8", \ + "71.4, 71.4, 71.4, 86.8, 114.9", \ + "75.9, 75.9, 75.9, 93.1, 124.3", \ + "81.2, 81.2, 81.2, 99.7, 134.6"); + } + fall_transition (inslew_load_5x5__82) { + values ("48.8, 48.8, 48.8, 64.5, 95.6", \ + "57.2, 57.2, 57.2, 73.0, 104.0", \ + "72.9, 72.9, 72.9, 88.9, 120.2", \ + "103.2, 103.2, 103.2, 119.6, 151.7", \ + "162.6, 162.6, 162.6, 179.9, 212.7"); + } + } + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__82) { + values ("60.5, 60.5, 60.5, 79.3, 116.5", \ + "67.2, 67.2, 67.2, 86.5, 124.2", \ + "79.1, 79.1, 79.1, 98.8, 137.4", \ + "101.5, 101.5, 101.5, 121.8, 161.6", \ + "145.2, 145.2, 145.2, 166.0, 207.0"); + } + rise_transition (inslew_load_5x5__82) { + values ("120.2, 120.2, 120.2, 153.6, 221.1", \ + "158.2, 158.2, 158.2, 191.2, 257.8", \ + "232.9, 232.9, 232.9, 265.3, 330.7", \ + "380.1, 380.1, 380.1, 414.4, 478.7", \ + "675.7, 675.7, 675.7, 708.1, 772.8"); + } + cell_fall (inslew_load_5x5__82) { + values ("36.2, 36.2, 36.2, 48.2, 71.4", \ + "38.9, 38.9, 38.9, 52.0, 76.7", \ + "41.0, 41.0, 41.0, 55.5, 82.7", \ + "42.4, 42.4, 42.4, 58.1, 87.9", \ + "43.0, 43.0, 43.0, 59.6, 91.7"); + } + fall_transition (inslew_load_5x5__82) { + values ("54.2, 54.2, 54.2, 69.7, 101.1", \ + "73.7, 73.7, 73.7, 89.2, 120.4", \ + "111.6, 111.6, 111.6, 127.4, 158.5", \ + "186.6, 186.6, 186.6, 202.5, 234.1", \ + "335.5, 335.5, 335.5, 351.7, 383.8"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__82) { + values ("36.2, 36.2, 36.2, 57.2, 95.5", \ + "48.2, 48.2, 48.2, 71.4, 113.0", \ + "68.6, 68.6, 68.6, 93.8, 139.7", \ + "106.6, 106.6, 106.6, 133.4, 183.5", \ + "181.2, 181.2, 181.2, 209.0, 262.3"); + } + rise_transition (inslew_load_5x5__82) { + values ("71.0, 71.0, 71.0, 109.5, 186.0", \ + "110.0, 110.0, 110.0, 149.1, 226.0", \ + "183.7, 183.7, 183.7, 223.4, 301.6", \ + "328.7, 328.7, 328.7, 368.8, 448.2", \ + "617.3, 617.3, 617.3, 657.6, 737.9"); + } + cell_fall (inslew_load_5x5__82) { + values ("17.4, 17.4, 17.4, 32.2, 57.7", \ + "14.0, 14.0, 14.0, 31.6, 61.2", \ + "3.6, 3.6, 3.6, 24.3, 59.7", \ + "-20.0, -20.0, -20.0, 3.3, 44.8", \ + "-69.4, -69.4, -69.4, -44.1, 2.6"); + } + fall_transition (inslew_load_5x5__82) { + values ("30.3, 30.3, 30.3, 46.2, 77.8", \ + "43.4, 43.4, 43.4, 60.2, 92.2", \ + "68.4, 68.4, 68.4, 86.2, 119.8", \ + "117.1, 117.1, 117.1, 135.8, 171.5", \ + "213.7, 213.7, 213.7, 233.1, 270.6"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__82) { + values ("153.1, 153.1, 153.1, 188.4, 258.8", \ + "186.5, 186.5, 186.5, 221.7, 292.1", \ + "252.1, 252.1, 252.1, 287.3, 357.7", \ + "382.2, 382.2, 382.2, 417.5, 487.9", \ + "641.9, 641.9, 641.9, 677.1, 747.6"); + } + fall_power (energy_inslew_load_5x5__82) { + values ("172.7, 172.7, 172.7, 207.9, 278.4", \ + "211.4, 211.4, 211.4, 246.6, 317.1", \ + "287.8, 287.8, 287.8, 323.1, 393.5", \ + "440.3, 440.3, 440.3, 475.5, 546.0", \ + "744.9, 744.9, 744.9, 780.1, 850.6"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__82) { + values ("123.1, 123.1, 123.1, 158.3, 228.8", \ + "157.3, 157.3, 157.3, 192.6, 263.0", \ + "225.8, 225.8, 225.8, 261.0, 331.5", \ + "362.8, 362.8, 362.8, 398.0, 468.5", \ + "636.7, 636.7, 636.7, 671.9, 742.4"); + } + fall_power (energy_inslew_load_5x5__82) { + values ("109.6, 109.6, 109.6, 144.8, 215.3", \ + "138.8, 138.8, 138.8, 174.0, 244.5", \ + "197.2, 197.2, 197.2, 232.4, 302.9", \ + "314.0, 314.0, 314.0, 349.2, 419.6", \ + "547.5, 547.5, 547.5, 582.8, 653.2"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__82) { + values ("59.7, 59.7, 59.7, 95.0, 165.4", \ + "85.5, 85.5, 85.5, 120.7, 191.2", \ + "136.9, 136.9, 136.9, 172.1, 242.6", \ + "239.8, 239.8, 239.8, 275.0, 345.5", \ + "445.6, 445.6, 445.6, 480.8, 551.3"); + } + fall_power (energy_inslew_load_5x5__82) { + values ("50.0, 50.0, 50.0, 85.2, 155.7", \ + "63.5, 63.5, 63.5, 98.8, 169.2", \ + "90.6, 90.6, 90.6, 125.9, 196.3", \ + "144.8, 144.8, 144.8, 180.1, 250.5", \ + "253.2, 253.2, 253.2, 288.4, 358.9"); + } + } + } + } + + cell (oai21bv0x05) { + area : 0.0 ; + cell_leakage_power : 1.6 ; + leakage_power () { + when : "(!(b) & !(a2) & a1)" ; + value : 0.77 ; + } + leakage_power () { + when : "(a2 & !(b))" ; + value : 0.97 ; + } + leakage_power () { + when : "b" ; + value : 4.7 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 0.00014 ; + } + pin (b) { + direction : input ; + capacitance : 2.63 ; + } + pin (a2) { + direction : input ; + capacitance : 3.16 ; + } + pin (a1) { + direction : input ; + capacitance : 3.36 ; + } + pin (z) { + function : "(!((a1 | a2)) | b)" ; + direction : output ; + capacitance : 3.32 ; + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__83) { + values ("54.5, 54.5, 54.5, 77.3, 120.4", \ + "58.3, 58.3, 58.3, 82.1, 126.1", \ + "59.5, 59.5, 59.5, 84.9, 131.0", \ + "55.9, 55.9, 55.9, 83.4, 132.8", \ + "43.3, 43.3, 43.3, 73.0, 127.0"); + } + rise_transition (inslew_load_5x5__83) { + values ("60.2, 60.2, 60.2, 105.4, 196.1", \ + "73.8, 73.8, 73.8, 119.0, 209.1", \ + "96.8, 96.8, 96.8, 142.3, 232.9", \ + "138.3, 138.3, 138.3, 184.5, 275.1", \ + "218.2, 218.2, 218.2, 264.9, 356.8"); + } + cell_fall (inslew_load_5x5__83) { + values ("57.1, 57.1, 57.1, 75.5, 106.9", \ + "64.9, 64.9, 64.9, 85.2, 119.5", \ + "75.6, 75.6, 75.6, 98.4, 137.1", \ + "92.2, 92.2, 92.2, 118.0, 162.3", \ + "123.1, 123.1, 123.1, 150.3, 201.3"); + } + fall_transition (inslew_load_5x5__83) { + values ("41.2, 41.2, 41.2, 60.2, 97.1", \ + "51.2, 51.2, 51.2, 70.7, 108.1", \ + "69.8, 69.8, 69.8, 90.0, 128.5", \ + "105.8, 105.8, 105.8, 126.9, 167.1", \ + "176.7, 176.7, 176.7, 198.7, 240.5"); + } + } + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__83) { + values ("64.6, 64.6, 64.6, 86.6, 130.4", \ + "71.5, 71.5, 71.5, 94.0, 138.3", \ + "83.4, 83.4, 83.4, 106.5, 152.0", \ + "105.9, 105.9, 105.9, 129.7, 176.4", \ + "149.7, 149.7, 149.7, 174.1, 222.2"); + } + rise_transition (inslew_load_5x5__83) { + values ("127.3, 127.3, 127.3, 166.9, 246.6", \ + "165.3, 165.3, 165.3, 204.3, 283.1", \ + "239.8, 239.8, 239.8, 278.1, 355.5", \ + "387.1, 387.1, 387.1, 427.1, 503.0", \ + "682.7, 682.7, 682.7, 720.8, 801.2"); + } + cell_fall (inslew_load_5x5__83) { + values ("39.0, 39.0, 39.0, 53.0, 80.1", \ + "42.0, 42.0, 42.0, 57.2, 85.9", \ + "44.4, 44.4, 44.4, 61.2, 92.7", \ + "46.1, 46.1, 46.1, 64.3, 99.0", \ + "46.8, 46.8, 46.8, 66.2, 103.6"); + } + fall_transition (inslew_load_5x5__83) { + values ("57.7, 57.7, 57.7, 76.1, 113.3", \ + "77.3, 77.3, 77.3, 95.6, 132.3", \ + "115.3, 115.3, 115.3, 133.8, 170.3", \ + "190.2, 190.2, 190.2, 209.0, 246.1", \ + "339.3, 339.3, 339.3, 358.3, 396.0"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__83) { + values ("51.5, 51.5, 51.5, 74.8, 119.6", \ + "67.6, 67.6, 67.6, 92.1, 138.6", \ + "95.2, 95.2, 95.2, 121.0, 170.3", \ + "146.8, 146.8, 146.8, 174.0, 226.2", \ + "247.7, 247.7, 247.7, 275.9, 330.8"); + } + rise_transition (inslew_load_5x5__83) { + values ("92.5, 92.5, 92.5, 132.4, 213.7", \ + "136.4, 136.4, 136.4, 176.2, 256.1", \ + "220.0, 220.0, 220.0, 259.6, 338.9", \ + "383.7, 383.7, 383.7, 423.8, 503.2", \ + "709.4, 709.4, 709.4, 749.7, 829.9"); + } + cell_fall (inslew_load_5x5__83) { + values ("29.5, 29.5, 29.5, 44.0, 71.6", \ + "25.7, 25.7, 25.7, 42.1, 72.0", \ + "14.1, 14.1, 14.1, 33.0, 67.0", \ + "-13.6, -13.6, -13.6, 7.9, 47.0", \ + "-72.8, -72.8, -72.8, -49.1, -4.9"); + } + fall_transition (inslew_load_5x5__83) { + values ("46.0, 46.0, 46.0, 64.4, 101.4", \ + "59.2, 59.2, 59.2, 77.7, 114.4", \ + "84.3, 84.3, 84.3, 103.4, 140.4", \ + "133.1, 133.1, 133.1, 152.9, 191.3", \ + "229.5, 229.5, 229.5, 249.9, 289.8"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__83) { + values ("121.0, 121.0, 121.0, 162.5, 245.6", \ + "146.3, 146.3, 146.3, 187.9, 271.0", \ + "196.2, 196.2, 196.2, 237.7, 320.8", \ + "295.1, 295.1, 295.1, 336.7, 419.8", \ + "492.6, 492.6, 492.6, 534.1, 617.2"); + } + fall_power (energy_inslew_load_5x5__83) { + values ("138.6, 138.6, 138.6, 180.2, 263.3", \ + "177.0, 177.0, 177.0, 218.6, 301.7", \ + "253.0, 253.0, 253.0, 294.5, 377.6", \ + "404.5, 404.5, 404.5, 446.0, 529.1", \ + "707.2, 707.2, 707.2, 748.7, 831.8"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__83) { + values ("130.7, 130.7, 130.7, 172.2, 255.3", \ + "164.9, 164.9, 164.9, 206.5, 289.5", \ + "233.4, 233.4, 233.4, 274.9, 358.0", \ + "370.3, 370.3, 370.3, 411.9, 495.0", \ + "644.2, 644.2, 644.2, 685.8, 768.9"); + } + fall_power (energy_inslew_load_5x5__83) { + values ("117.7, 117.7, 117.7, 159.2, 242.3", \ + "146.9, 146.9, 146.9, 188.4, 271.5", \ + "205.3, 205.3, 205.3, 246.8, 329.9", \ + "322.0, 322.0, 322.0, 363.6, 446.7", \ + "555.6, 555.6, 555.6, 597.2, 680.3"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__83) { + values ("94.2, 94.2, 94.2, 135.8, 218.9", \ + "127.8, 127.8, 127.8, 169.4, 252.5", \ + "195.0, 195.0, 195.0, 236.5, 319.6", \ + "329.3, 329.3, 329.3, 370.9, 454.0", \ + "598.0, 598.0, 598.0, 639.5, 722.6"); + } + fall_power (energy_inslew_load_5x5__83) { + values ("88.5, 88.5, 88.5, 130.0, 213.1", \ + "104.2, 104.2, 104.2, 145.7, 228.8", \ + "135.6, 135.6, 135.6, 177.1, 260.2", \ + "198.3, 198.3, 198.3, 239.9, 323.0", \ + "323.9, 323.9, 323.9, 365.4, 448.5"); + } + } + } + } + + cell (oai21v0x05) { + area : 0.0 ; + cell_leakage_power : 0.29 ; + leakage_power () { + when : "(!(b) & a2 & a1)" ; + value : 0.00013 ; + } + leakage_power () { + when : "(b & !(a2) & a1)" ; + value : 0.77 ; + } + leakage_power () { + when : "(a2 & b)" ; + value : 0.97 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(b))" ; + value : 6.6e-05 ; + } + leakage_power () { + when : "(b & !(a2) & !(a1))" ; + value : 0.00011 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 2.4e-06 ; + } + pin (b) { + direction : input ; + capacitance : 2.59 ; + } + pin (a2) { + direction : input ; + capacitance : 3.31 ; + } + pin (a1) { + direction : input ; + capacitance : 3.12 ; + } + pin (z) { + function : "((!(a2) & !(a1)) | !(b))" ; + direction : output ; + capacitance : 3.32 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__83) { + values ("64.4, 64.4, 64.4, 86.5, 130.3", \ + "71.4, 71.4, 71.4, 93.9, 138.2", \ + "83.2, 83.2, 83.2, 106.4, 151.9", \ + "105.8, 105.8, 105.8, 129.6, 176.2", \ + "149.6, 149.6, 149.6, 174.0, 222.1"); + } + rise_transition (inslew_load_5x5__83) { + values ("127.1, 127.1, 127.1, 166.6, 246.3", \ + "165.1, 165.1, 165.1, 204.1, 282.8", \ + "239.6, 239.6, 239.6, 277.9, 355.3", \ + "386.9, 386.9, 386.9, 426.8, 502.8", \ + "682.5, 682.5, 682.5, 720.6, 801.0"); + } + cell_fall (inslew_load_5x5__83) { + values ("38.9, 38.9, 38.9, 52.9, 80.0", \ + "41.8, 41.8, 41.8, 57.1, 85.8", \ + "44.3, 44.3, 44.3, 61.1, 92.5", \ + "45.9, 45.9, 45.9, 64.2, 98.8", \ + "46.7, 46.7, 46.7, 66.1, 103.5"); + } + fall_transition (inslew_load_5x5__83) { + values ("57.6, 57.6, 57.6, 75.9, 113.2", \ + "77.1, 77.1, 77.1, 95.4, 132.1", \ + "115.1, 115.1, 115.1, 133.6, 170.2", \ + "190.1, 190.1, 190.1, 208.9, 245.9", \ + "339.1, 339.1, 339.1, 358.1, 395.9"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__83) { + values ("51.4, 51.4, 51.4, 74.7, 119.5", \ + "67.4, 67.4, 67.4, 92.0, 138.5", \ + "95.0, 95.0, 95.0, 120.9, 170.2", \ + "146.6, 146.6, 146.6, 173.9, 226.1", \ + "247.6, 247.6, 247.6, 275.8, 330.6"); + } + rise_transition (inslew_load_5x5__83) { + values ("92.3, 92.3, 92.3, 132.1, 213.5", \ + "136.2, 136.2, 136.2, 175.9, 255.9", \ + "219.8, 219.8, 219.8, 259.4, 338.7", \ + "383.5, 383.5, 383.5, 423.6, 503.0", \ + "709.2, 709.2, 709.2, 749.5, 829.7"); + } + cell_fall (inslew_load_5x5__83) { + values ("29.3, 29.3, 29.3, 43.9, 71.5", \ + "25.6, 25.6, 25.6, 42.0, 71.9", \ + "13.9, 13.9, 13.9, 32.8, 66.8", \ + "-13.7, -13.7, -13.7, 7.7, 46.9", \ + "-73.0, -73.0, -73.0, -49.3, -5.1"); + } + fall_transition (inslew_load_5x5__83) { + values ("45.9, 45.9, 45.9, 64.3, 101.3", \ + "59.1, 59.1, 59.1, 77.5, 114.3", \ + "84.2, 84.2, 84.2, 103.2, 140.3", \ + "133.0, 133.0, 133.0, 152.8, 191.1", \ + "229.3, 229.3, 229.3, 249.7, 289.6"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__83) { + values ("40.2, 40.2, 40.2, 64.3, 108.7", \ + "52.6, 52.6, 52.6, 79.2, 127.1", \ + "73.2, 73.2, 73.2, 102.4, 155.3", \ + "111.5, 111.5, 111.5, 142.7, 200.7", \ + "186.3, 186.3, 186.3, 218.7, 280.9"); + } + rise_transition (inslew_load_5x5__83) { + values ("77.9, 77.9, 77.9, 123.2, 213.3", \ + "117.1, 117.1, 117.1, 163.0, 253.3", \ + "190.9, 190.9, 190.9, 237.6, 329.4", \ + "335.9, 335.9, 335.9, 383.1, 476.4", \ + "624.5, 624.5, 624.5, 672.1, 766.5"); + } + cell_fall (inslew_load_5x5__83) { + values ("20.2, 20.2, 20.2, 36.9, 66.2", \ + "17.3, 17.3, 17.3, 37.3, 70.8", \ + "7.5, 7.5, 7.5, 31.1, 71.1", \ + "-15.6, -15.6, -15.6, 11.2, 58.4", \ + "-64.7, -64.7, -64.7, -35.3, 18.4"); + } + fall_transition (inslew_load_5x5__83) { + values ("33.2, 33.2, 33.2, 51.8, 89.0", \ + "46.5, 46.5, 46.5, 66.1, 103.4", \ + "71.7, 71.7, 71.7, 92.4, 131.4", \ + "120.5, 120.5, 120.5, 142.4, 183.8", \ + "217.2, 217.2, 217.2, 240.0, 283.7"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__83) { + values ("130.4, 130.4, 130.4, 172.0, 255.1", \ + "164.7, 164.7, 164.7, 206.2, 289.3", \ + "233.2, 233.2, 233.2, 274.7, 357.8", \ + "370.1, 370.1, 370.1, 411.7, 494.8", \ + "644.0, 644.0, 644.0, 685.6, 768.7"); + } + fall_power (energy_inslew_load_5x5__83) { + values ("117.3, 117.3, 117.3, 158.9, 242.0", \ + "146.5, 146.5, 146.5, 188.1, 271.2", \ + "204.9, 204.9, 204.9, 246.5, 329.6", \ + "321.7, 321.7, 321.7, 363.3, 446.4", \ + "555.3, 555.3, 555.3, 596.8, 679.9"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__83) { + values ("94.0, 94.0, 94.0, 135.6, 218.7", \ + "127.6, 127.6, 127.6, 169.1, 252.2", \ + "194.8, 194.8, 194.8, 236.3, 319.4", \ + "329.1, 329.1, 329.1, 370.6, 453.7", \ + "597.8, 597.8, 597.8, 639.3, 722.4"); + } + fall_power (energy_inslew_load_5x5__83) { + values ("88.2, 88.2, 88.2, 129.7, 212.8", \ + "103.9, 103.9, 103.9, 145.4, 228.5", \ + "135.3, 135.3, 135.3, 176.8, 259.9", \ + "198.0, 198.0, 198.0, 239.6, 322.7", \ + "323.6, 323.6, 323.6, 365.1, 448.2"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__83) { + values ("66.1, 66.1, 66.1, 107.6, 190.7", \ + "91.8, 91.8, 91.8, 133.3, 216.4", \ + "143.2, 143.2, 143.2, 184.8, 267.9", \ + "246.1, 246.1, 246.1, 287.7, 370.8", \ + "451.9, 451.9, 451.9, 493.5, 576.6"); + } + fall_power (energy_inslew_load_5x5__83) { + values ("56.3, 56.3, 56.3, 97.9, 181.0", \ + "69.9, 69.9, 69.9, 111.4, 194.5", \ + "97.0, 97.0, 97.0, 138.5, 221.6", \ + "151.1, 151.1, 151.1, 192.7, 275.8", \ + "259.5, 259.5, 259.5, 301.1, 384.2"); + } + } + } + } + + cell (oai21v0x1) { + area : 0.0 ; + cell_leakage_power : 0.74 ; + leakage_power () { + when : "(!(b) & a2 & a1)" ; + value : 0.00014 ; + } + leakage_power () { + when : "(b & !(a2) & a1)" ; + value : 1.9 ; + } + leakage_power () { + when : "(a2 & b)" ; + value : 2.6 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(b))" ; + value : 7.1e-05 ; + } + leakage_power () { + when : "(b & !(a2) & !(a1))" ; + value : 0.00011 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 2.5e-06 ; + } + pin (b) { + direction : input ; + capacitance : 3.70 ; + } + pin (a2) { + direction : input ; + capacitance : 5.04 ; + } + pin (a1) { + direction : input ; + capacitance : 4.62 ; + } + pin (z) { + function : "(!(b) | (!(a2) & !(a1)))" ; + direction : output ; + capacitance : 3.79 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__84) { + values ("66.0, 66.0, 66.0, 83.0, 116.8", \ + "76.0, 76.0, 76.0, 93.3, 127.5", \ + "93.5, 93.5, 93.5, 111.2, 146.4", \ + "127.5, 127.5, 127.5, 145.6, 181.3", \ + "194.7, 194.7, 194.7, 213.1, 249.5"); + } + rise_transition (inslew_load_5x5__84) { + values ("124.6, 124.6, 124.6, 154.0, 213.1", \ + "167.8, 167.8, 167.8, 196.8, 255.3", \ + "251.0, 251.0, 251.0, 279.6, 337.2", \ + "416.9, 416.9, 416.9, 445.1, 501.8", \ + "744.5, 744.5, 744.5, 776.8, 832.9"); + } + cell_fall (inslew_load_5x5__84) { + values ("30.5, 30.5, 30.5, 39.8, 57.6", \ + "31.0, 31.0, 31.0, 41.4, 60.9", \ + "28.7, 28.7, 28.7, 40.4, 62.3", \ + "21.2, 21.2, 21.2, 34.1, 58.5", \ + "4.1, 4.1, 4.1, 17.8, 44.4"); + } + fall_transition (inslew_load_5x5__84) { + values ("44.8, 44.8, 44.8, 56.3, 79.1", \ + "61.3, 61.3, 61.3, 72.8, 95.6", \ + "93.2, 93.2, 93.2, 104.9, 128.0", \ + "155.9, 155.9, 155.9, 168.0, 191.7", \ + "280.7, 280.7, 280.7, 292.9, 317.2"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__84) { + values ("48.1, 48.1, 48.1, 66.2, 101.1", \ + "66.8, 66.8, 66.8, 85.8, 121.9", \ + "99.0, 99.0, 99.0, 118.8, 156.8", \ + "159.9, 159.9, 159.9, 180.5, 220.2", \ + "279.6, 279.6, 279.6, 300.6, 341.9"); + } + rise_transition (inslew_load_5x5__84) { + values ("83.4, 83.4, 83.4, 112.8, 172.7", \ + "131.8, 131.8, 131.8, 161.2, 220.4", \ + "222.3, 222.3, 222.3, 251.5, 310.2", \ + "399.0, 399.0, 399.0, 428.5, 487.0", \ + "750.0, 750.0, 750.0, 779.6, 838.7"); + } + cell_fall (inslew_load_5x5__84) { + values ("21.9, 21.9, 21.9, 31.8, 50.2", \ + "16.3, 16.3, 16.3, 27.8, 48.6", \ + "1.2, 1.2, 1.2, 14.8, 39.1", \ + "-32.8, -32.8, -32.8, -17.2, 11.2", \ + "-104.2, -104.2, -104.2, -87.0, -54.7"); + } + fall_transition (inslew_load_5x5__84) { + values ("35.2, 35.2, 35.2, 46.7, 69.6", \ + "46.4, 46.4, 46.4, 58.2, 81.2", \ + "67.7, 67.7, 67.7, 80.0, 103.8", \ + "108.8, 108.8, 108.8, 121.7, 146.7", \ + "189.8, 189.8, 189.8, 203.3, 229.5"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__84) { + values ("30.8, 30.8, 30.8, 47.8, 78.1", \ + "42.1, 42.1, 42.1, 60.7, 94.1", \ + "61.3, 61.3, 61.3, 81.3, 118.2", \ + "97.7, 97.7, 97.7, 118.7, 158.6", \ + "169.1, 169.1, 169.1, 190.8, 232.9"); + } + rise_transition (inslew_load_5x5__84) { + values ("60.4, 60.4, 60.4, 89.3, 146.7", \ + "98.5, 98.5, 98.5, 127.8, 185.3", \ + "170.6, 170.6, 170.6, 200.3, 258.9", \ + "312.5, 312.5, 312.5, 342.5, 402.0", \ + "594.9, 594.9, 594.9, 625.2, 685.3"); + } + cell_fall (inslew_load_5x5__84) { + values ("13.6, 13.6, 13.6, 25.6, 45.9", \ + "9.7, 9.7, 9.7, 24.0, 48.1", \ + "-0.7, -0.7, -0.7, 15.9, 44.6", \ + "-23.8, -23.8, -23.8, -5.2, 28.1", \ + "-71.4, -71.4, -71.4, -51.4, -14.2"); + } + fall_transition (inslew_load_5x5__84) { + values ("25.2, 25.2, 25.2, 37.2, 60.2", \ + "37.7, 37.7, 37.7, 50.4, 74.3", \ + "61.6, 61.6, 61.6, 75.1, 100.4", \ + "108.5, 108.5, 108.5, 122.6, 149.6", \ + "201.6, 201.6, 201.6, 216.3, 244.6"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__84) { + values ("197.5, 197.5, 197.5, 244.9, 339.6", \ + "257.0, 257.0, 257.0, 304.3, 399.1", \ + "375.9, 375.9, 375.9, 423.3, 518.1", \ + "613.9, 613.9, 613.9, 661.3, 756.1", \ + "1089.8, 1089.8, 1089.8, 1137.2, 1232.0"); + } + fall_power (energy_inslew_load_5x5__84) { + values ("161.6, 161.6, 161.6, 209.0, 303.7", \ + "202.8, 202.8, 202.8, 250.1, 344.9", \ + "285.1, 285.1, 285.1, 332.5, 427.3", \ + "449.9, 449.9, 449.9, 497.3, 592.1", \ + "779.5, 779.5, 779.5, 826.8, 921.6"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__84) { + values ("134.2, 134.2, 134.2, 181.6, 276.4", \ + "190.8, 190.8, 190.8, 238.2, 333.0", \ + "304.1, 304.1, 304.1, 351.5, 446.3", \ + "530.7, 530.7, 530.7, 578.1, 672.9", \ + "983.9, 983.9, 983.9, 1031.3, 1126.1"); + } + fall_power (energy_inslew_load_5x5__84) { + values ("117.6, 117.6, 117.6, 164.9, 259.7", \ + "139.2, 139.2, 139.2, 186.6, 281.4", \ + "182.5, 182.5, 182.5, 229.9, 324.7", \ + "269.2, 269.2, 269.2, 316.6, 411.4", \ + "442.5, 442.5, 442.5, 489.9, 584.7"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__84) { + values ("89.7, 89.7, 89.7, 137.1, 231.9", \ + "134.0, 134.0, 134.0, 181.4, 276.1", \ + "222.5, 222.5, 222.5, 269.9, 364.7", \ + "399.6, 399.6, 399.6, 447.0, 541.8", \ + "753.8, 753.8, 753.8, 801.2, 895.9"); + } + fall_power (energy_inslew_load_5x5__84) { + values ("72.4, 72.4, 72.4, 119.8, 214.6", \ + "95.5, 95.5, 95.5, 142.9, 237.7", \ + "141.7, 141.7, 141.7, 189.1, 283.8", \ + "234.0, 234.0, 234.0, 281.4, 376.2", \ + "418.7, 418.7, 418.7, 466.1, 560.9"); + } + } + } + } + + cell (oai21v0x4) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "(!(b) & a2 & a1)" ; + value : 0.0028 ; + } + leakage_power () { + when : "(b & !(a2) & a1)" ; + value : 5.8 ; + } + leakage_power () { + when : "(a2 & b)" ; + value : 8.9 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(b))" ; + value : 0.0014 ; + } + leakage_power () { + when : "(b & !(a2) & !(a1))" ; + value : 0.0019 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 4.4e-05 ; + } + pin (b) { + direction : input ; + capacitance : 11.27 ; + } + pin (a2) { + direction : input ; + capacitance : 16.54 ; + } + pin (a1) { + direction : input ; + capacitance : 17.51 ; + } + pin (z) { + function : "(!(b) | (!(a2) & !(a1)))" ; + direction : output ; + capacitance : 12.08 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__85) { + values ("60.9, 60.9, 60.9, 74.3, 100.8", \ + "69.2, 69.2, 69.2, 83.0, 109.9", \ + "83.8, 83.8, 83.8, 97.8, 125.4", \ + "111.8, 111.8, 111.8, 126.1, 154.5", \ + "166.8, 166.8, 166.8, 181.5, 210.4"); + } + rise_transition (inslew_load_5x5__85) { + values ("116.0, 116.0, 116.0, 139.0, 185.4", \ + "156.7, 156.7, 156.7, 179.4, 225.2", \ + "235.2, 235.2, 235.2, 257.5, 302.5", \ + "391.6, 391.6, 391.6, 413.7, 458.1", \ + "699.6, 699.6, 699.6, 721.8, 770.5"); + } + cell_fall (inslew_load_5x5__85) { + values ("30.0, 30.0, 30.0, 37.7, 52.3", \ + "31.5, 31.5, 31.5, 40.0, 56.1", \ + "31.0, 31.0, 31.0, 40.6, 58.8", \ + "27.3, 27.3, 27.3, 37.9, 58.0", \ + "18.1, 18.1, 18.1, 29.3, 51.0"); + } + fall_transition (inslew_load_5x5__85) { + values ("43.1, 43.1, 43.1, 52.3, 70.7", \ + "60.3, 60.3, 60.3, 69.7, 88.0", \ + "93.5, 93.5, 93.5, 103.0, 121.8", \ + "158.8, 158.8, 158.8, 168.5, 187.7", \ + "288.6, 288.6, 288.6, 298.5, 318.1"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__85) { + values ("43.1, 43.1, 43.1, 57.6, 85.4", \ + "60.5, 60.5, 60.5, 75.7, 104.6", \ + "90.3, 90.3, 90.3, 106.1, 136.6", \ + "146.4, 146.4, 146.4, 162.8, 194.8", \ + "256.7, 256.7, 256.7, 273.5, 306.5"); + } + rise_transition (inslew_load_5x5__85) { + values ("75.0, 75.0, 75.0, 98.4, 145.1", \ + "121.9, 121.9, 121.9, 145.1, 191.8", \ + "209.0, 209.0, 209.0, 232.1, 278.2", \ + "378.9, 378.9, 378.9, 402.2, 448.5", \ + "716.4, 716.4, 716.4, 739.8, 786.4"); + } + cell_fall (inslew_load_5x5__85) { + values ("21.0, 21.0, 21.0, 29.2, 44.4", \ + "15.8, 15.8, 15.8, 25.4, 42.8", \ + "1.7, 1.7, 1.7, 12.9, 33.3", \ + "-30.0, -30.0, -30.0, -17.2, 6.4", \ + "-96.1, -96.1, -96.1, -82.2, -55.6"); + } + fall_transition (inslew_load_5x5__85) { + values ("33.5, 33.5, 33.5, 42.8, 61.2", \ + "45.2, 45.2, 45.2, 54.8, 73.4", \ + "67.4, 67.4, 67.4, 77.4, 96.8", \ + "110.4, 110.4, 110.4, 120.9, 141.3", \ + "195.5, 195.5, 195.5, 206.4, 227.7"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__85) { + values ("29.7, 29.7, 29.7, 45.1, 72.5", \ + "43.8, 43.8, 43.8, 60.4, 90.4", \ + "68.1, 68.1, 68.1, 85.7, 118.3", \ + "114.1, 114.1, 114.1, 132.4, 167.3", \ + "204.7, 204.7, 204.7, 223.5, 259.9"); + } + rise_transition (inslew_load_5x5__85) { + values ("52.3, 52.3, 52.3, 75.7, 121.7", \ + "92.1, 92.1, 92.1, 115.9, 162.4", \ + "166.4, 166.4, 166.4, 190.4, 237.7", \ + "311.8, 311.8, 311.8, 336.0, 384.0", \ + "600.9, 600.9, 600.9, 625.3, 673.8"); + } + cell_fall (inslew_load_5x5__85) { + values ("9.9, 9.9, 9.9, 20.3, 37.4", \ + "3.9, 3.9, 3.9, 16.4, 37.1", \ + "-10.4, -10.4, -10.4, 4.0, 28.9", \ + "-40.9, -40.9, -40.9, -24.7, 4.1", \ + "-103.0, -103.0, -103.0, -85.8, -53.6"); + } + fall_transition (inslew_load_5x5__85) { + values ("21.9, 21.9, 21.9, 31.8, 50.4", \ + "33.2, 33.2, 33.2, 43.7, 63.3", \ + "54.7, 54.7, 54.7, 65.9, 86.9", \ + "96.9, 96.9, 96.9, 108.7, 131.1", \ + "180.9, 180.9, 180.9, 193.0, 216.6"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__85) { + values ("742.6, 742.6, 742.6, 893.6, 1195.5", \ + "967.1, 967.1, 967.1, 1118.1, 1420.0", \ + "1416.1, 1416.1, 1416.1, 1567.0, 1868.9", \ + "2314.0, 2314.0, 2314.0, 2465.0, 2766.9", \ + "4109.9, 4109.9, 4109.9, 4260.8, 4562.7"); + } + fall_power (energy_inslew_load_5x5__85) { + values ("615.2, 615.2, 615.2, 766.1, 1068.0", \ + "784.9, 784.9, 784.9, 935.9, 1237.8", \ + "1124.4, 1124.4, 1124.4, 1275.3, 1577.2", \ + "1803.3, 1803.3, 1803.3, 1954.3, 2256.2", \ + "3161.2, 3161.2, 3161.2, 3312.1, 3614.0"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__85) { + values ("490.6, 490.6, 490.6, 641.5, 943.4", \ + "709.1, 709.1, 709.1, 860.1, 1162.0", \ + "1146.2, 1146.2, 1146.2, 1297.2, 1599.1", \ + "2020.5, 2020.5, 2020.5, 2171.4, 2473.3", \ + "3768.9, 3768.9, 3768.9, 3919.9, 4221.8"); + } + fall_power (energy_inslew_load_5x5__85) { + values ("437.2, 437.2, 437.2, 588.2, 890.1", \ + "528.2, 528.2, 528.2, 679.1, 981.0", \ + "710.1, 710.1, 710.1, 861.1, 1163.0", \ + "1074.0, 1074.0, 1074.0, 1224.9, 1526.8", \ + "1801.7, 1801.7, 1801.7, 1952.6, 2254.5"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__85) { + values ("317.8, 317.8, 317.8, 468.8, 770.7", \ + "491.9, 491.9, 491.9, 642.9, 944.8", \ + "840.2, 840.2, 840.2, 991.1, 1293.0", \ + "1536.7, 1536.7, 1536.7, 1687.6, 1989.5", \ + "2929.6, 2929.6, 2929.6, 3080.6, 3382.5"); + } + fall_power (energy_inslew_load_5x5__85) { + values ("236.5, 236.5, 236.5, 387.4, 689.3", \ + "314.7, 314.7, 314.7, 465.6, 767.5", \ + "471.2, 471.2, 471.2, 622.1, 924.0", \ + "784.1, 784.1, 784.1, 935.1, 1237.0", \ + "1410.0, 1410.0, 1410.0, 1561.0, 1862.9"); + } + } + } + } + + cell (oai22v0x05) { + area : 0.0 ; + cell_leakage_power : 0.22 ; + leakage_power () { + when : "(!(b2) & !(b1) & a2 & a1)" ; + value : 0.00026 ; + } + leakage_power () { + when : "(!(b2) & b1 & !(a2) & a1)" ; + value : 0.39 ; + } + leakage_power () { + when : "((a1 & ((a2 & b1 & !(b2)) | (!(a2) & b2))) | (a2 & b1 & !(b2)))" ; + value : 0.59 ; + } + leakage_power () { + when : "(a2 & b2)" ; + value : 0.79 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(b1) & !(b2))" ; + value : 0.00013 ; + } + leakage_power () { + when : "(b2 & b1 & !(a2) & !(a1))" ; + value : 0.00021 ; + } + leakage_power () { + when : "(!(a1) & !(a2) & (b1 ^ b2))" ; + value : 0.00011 ; + } + leakage_power () { + when : "(!(b2) & !(b1) & !(a2) & !(a1))" ; + value : 4.7e-06 ; + } + pin (b2) { + direction : input ; + capacitance : 3.09 ; + } + pin (b1) { + direction : input ; + capacitance : 3.16 ; + } + pin (a2) { + direction : input ; + capacitance : 3.31 ; + } + pin (a1) { + direction : input ; + capacitance : 3.39 ; + } + pin (z) { + function : "((!(a2) & !(a1)) | (!(b2) & !(b1)))" ; + direction : output ; + capacitance : 4.08 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__86) { + values ("74.6, 74.6, 74.6, 101.6, 155.2", \ + "81.8, 81.8, 81.8, 109.1, 163.2", \ + "93.9, 93.9, 93.9, 122.0, 177.3", \ + "116.8, 116.8, 116.8, 145.7, 202.4", \ + "160.8, 160.8, 160.8, 190.6, 249.1"); + } + rise_transition (inslew_load_5x5__86) { + values ("145.1, 145.1, 145.1, 193.8, 292.0", \ + "182.8, 182.8, 182.8, 230.9, 328.1", \ + "257.1, 257.1, 257.1, 304.3, 399.8", \ + "406.3, 406.3, 406.3, 452.8, 546.4", \ + "699.9, 699.9, 699.9, 746.7, 844.0"); + } + cell_fall (inslew_load_5x5__86) { + values ("45.2, 45.2, 45.2, 62.1, 95.0", \ + "48.7, 48.7, 48.7, 66.9, 101.4", \ + "51.9, 51.9, 51.9, 71.9, 109.4", \ + "54.1, 54.1, 54.1, 76.1, 117.5", \ + "55.3, 55.3, 55.3, 78.8, 123.8"); + } + fall_transition (inslew_load_5x5__86) { + values ("65.6, 65.6, 65.6, 88.3, 134.4", \ + "85.2, 85.2, 85.2, 107.6, 152.8", \ + "123.3, 123.3, 123.3, 145.9, 190.6", \ + "198.4, 198.4, 198.4, 221.3, 266.6", \ + "347.5, 347.5, 347.5, 370.8, 416.9"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__86) { + values ("62.2, 62.2, 62.2, 90.2, 144.8", \ + "78.9, 78.9, 78.9, 108.2, 164.3", \ + "107.0, 107.0, 107.0, 138.1, 197.3", \ + "159.2, 159.2, 159.2, 192.1, 254.9", \ + "260.5, 260.5, 260.5, 294.8, 361.1"); + } + rise_transition (inslew_load_5x5__86) { + values ("110.4, 110.4, 110.4, 159.7, 260.4", \ + "154.4, 154.4, 154.4, 203.6, 301.6", \ + "237.9, 237.9, 237.9, 286.5, 385.2", \ + "401.9, 401.9, 401.9, 450.9, 548.1", \ + "727.6, 727.6, 727.6, 777.0, 875.2"); + } + cell_fall (inslew_load_5x5__86) { + values ("36.0, 36.0, 36.0, 53.3, 86.5", \ + "33.1, 33.1, 33.1, 52.3, 87.8", \ + "22.5, 22.5, 22.5, 44.7, 84.6", \ + "-4.0, -4.0, -4.0, 21.3, 67.4", \ + "-62.4, -62.4, -62.4, -34.1, 18.3"); + } + fall_transition (inslew_load_5x5__86) { + values ("54.1, 54.1, 54.1, 76.6, 122.4", \ + "67.2, 67.2, 67.2, 89.8, 134.8", \ + "92.6, 92.6, 92.6, 115.7, 160.8", \ + "141.7, 141.7, 141.7, 165.7, 212.2", \ + "238.4, 238.4, 238.4, 263.2, 311.6"); + } + } + timing (maxd_z_b1_negative_unate) { + related_pin : "b1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__86) { + values ("54.1, 54.1, 54.1, 81.4, 135.2", \ + "54.8, 54.8, 54.8, 83.0, 137.5", \ + "54.6, 54.6, 54.6, 83.8, 140.0", \ + "52.2, 52.2, 52.2, 82.9, 141.7", \ + "45.5, 45.5, 45.5, 77.5, 139.4"); + } + rise_transition (inslew_load_5x5__86) { + values ("109.2, 109.2, 109.2, 157.5, 255.3", \ + "137.6, 137.6, 137.6, 185.2, 281.7", \ + "193.0, 193.0, 193.0, 240.7, 335.2", \ + "304.0, 304.0, 304.0, 351.0, 446.4", \ + "525.8, 525.8, 525.8, 572.9, 666.7"); + } + cell_fall (inslew_load_5x5__86) { + values ("36.7, 36.7, 36.7, 55.2, 89.4", \ + "45.2, 45.2, 45.2, 65.8, 103.0", \ + "57.5, 57.5, 57.5, 80.5, 122.3", \ + "78.5, 78.5, 78.5, 103.6, 150.2", \ + "118.1, 118.1, 118.1, 144.7, 195.2"); + } + fall_transition (inslew_load_5x5__86) { + values ("49.3, 49.3, 49.3, 72.1, 118.1", \ + "72.4, 72.4, 72.4, 95.3, 140.7", \ + "115.9, 115.9, 115.9, 139.4, 185.4", \ + "201.1, 201.1, 201.1, 225.2, 272.4", \ + "370.2, 370.2, 370.2, 394.8, 443.1"); + } + } + timing (maxd_z_b2_negative_unate) { + related_pin : "b2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__86) { + values ("41.8, 41.8, 41.8, 70.9, 126.0", \ + "51.8, 51.8, 51.8, 82.8, 140.2", \ + "67.3, 67.3, 67.3, 100.8, 162.4", \ + "95.0, 95.0, 95.0, 130.7, 197.4", \ + "148.1, 148.1, 148.1, 185.5, 256.8"); + } + rise_transition (inslew_load_5x5__86) { + values ("76.4, 76.4, 76.4, 125.6, 225.4", \ + "112.2, 112.2, 112.2, 160.9, 258.9", \ + "179.4, 179.4, 179.4, 228.5, 325.8", \ + "310.9, 310.9, 310.9, 360.7, 459.0", \ + "572.2, 572.2, 572.2, 622.6, 722.3"); + } + cell_fall (inslew_load_5x5__86) { + values ("26.8, 26.8, 26.8, 46.2, 81.2", \ + "27.1, 27.1, 27.1, 49.9, 88.9", \ + "23.2, 23.2, 23.2, 49.7, 95.3", \ + "11.2, 11.2, 11.2, 41.2, 94.3", \ + "-15.6, -15.6, -15.6, 17.0, 77.0"); + } + fall_transition (inslew_load_5x5__86) { + values ("38.2, 38.2, 38.2, 60.9, 106.8", \ + "54.1, 54.1, 54.1, 77.6, 123.1", \ + "83.7, 83.7, 83.7, 108.3, 155.3", \ + "141.1, 141.1, 141.1, 166.9, 216.1", \ + "254.7, 254.7, 254.7, 281.3, 332.8"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__86) { + values ("149.4, 149.4, 149.4, 200.4, 302.4", \ + "183.7, 183.7, 183.7, 234.7, 336.7", \ + "252.1, 252.1, 252.1, 303.1, 405.2", \ + "389.1, 389.1, 389.1, 440.1, 542.1", \ + "663.0, 663.0, 663.0, 714.0, 816.0"); + } + fall_power (energy_inslew_load_5x5__86) { + values ("135.6, 135.6, 135.6, 186.6, 288.7", \ + "164.8, 164.8, 164.8, 215.8, 317.9", \ + "223.2, 223.2, 223.2, 274.2, 376.3", \ + "340.0, 340.0, 340.0, 391.0, 493.0", \ + "573.6, 573.6, 573.6, 624.6, 726.6"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__86) { + values ("113.0, 113.0, 113.0, 164.0, 266.0", \ + "146.6, 146.6, 146.6, 197.6, 299.6", \ + "213.7, 213.7, 213.7, 264.7, 366.8", \ + "348.1, 348.1, 348.1, 399.1, 501.1", \ + "616.7, 616.7, 616.7, 667.8, 769.8"); + } + fall_power (energy_inslew_load_5x5__86) { + values ("106.5, 106.5, 106.5, 157.5, 259.5", \ + "122.2, 122.2, 122.2, 173.2, 275.2", \ + "153.6, 153.6, 153.6, 204.6, 306.6", \ + "216.3, 216.3, 216.3, 267.3, 369.3", \ + "341.9, 341.9, 341.9, 392.9, 494.9"); + } + } + internal_power (energy_neg_z_b1) { + related_pin : "b1" ; + rise_power (energy_inslew_load_5x5__86) { + values ("109.8, 109.8, 109.8, 160.8, 262.9", \ + "134.1, 134.1, 134.1, 185.1, 287.1", \ + "182.5, 182.5, 182.5, 233.5, 335.5", \ + "279.4, 279.4, 279.4, 330.4, 432.4", \ + "473.2, 473.2, 473.2, 524.3, 626.3"); + } + fall_power (energy_inslew_load_5x5__86) { + values ("98.5, 98.5, 98.5, 149.5, 251.6", \ + "129.2, 129.2, 129.2, 180.2, 282.3", \ + "190.6, 190.6, 190.6, 241.6, 343.7", \ + "313.4, 313.4, 313.4, 364.4, 466.5", \ + "559.0, 559.0, 559.0, 610.0, 712.1"); + } + } + internal_power (energy_neg_z_b2) { + related_pin : "b2" ; + rise_power (energy_inslew_load_5x5__86) { + values ("75.3, 75.3, 75.3, 126.3, 228.3", \ + "100.8, 100.8, 100.8, 151.8, 253.8", \ + "151.8, 151.8, 151.8, 202.8, 304.8", \ + "253.7, 253.7, 253.7, 304.7, 406.7", \ + "457.5, 457.5, 457.5, 508.5, 610.5"); + } + fall_power (energy_inslew_load_5x5__86) { + values ("69.4, 69.4, 69.4, 120.4, 222.5", \ + "86.7, 86.7, 86.7, 137.7, 239.7", \ + "121.2, 121.2, 121.2, 172.2, 274.2", \ + "190.2, 190.2, 190.2, 241.2, 343.3", \ + "328.3, 328.3, 328.3, 379.3, 481.3"); + } + } + } + } + + cell (oai23av0x05) { + area : 0.0 ; + cell_leakage_power : 1.9 ; + leakage_power () { + when : "(b2 & b1 & a2)" ; + value : 6.2 ; + } + leakage_power () { + when : "(b2 & !(b1) & a2)" ; + value : 0.79 ; + } + leakage_power () { + when : "(!(b2) & !(b1) & a2)" ; + value : 0.00026 ; + } + leakage_power () { + when : "(b2 & b1 & !(a2))" ; + value : 5.4 ; + } + leakage_power () { + when : "(!(b2) & b1 & !(a2))" ; + value : 0.39 ; + } + leakage_power () { + when : "((a2 & b1 & !(b2)) | (!(a2) & !(b1) & b2))" ; + value : 0.59 ; + } + leakage_power () { + when : "(!(b2) & !(b1) & !(a2))" ; + value : 0.00013 ; + } + pin (b2) { + direction : input ; + capacitance : 6.88 ; + } + pin (b1) { + direction : input ; + capacitance : 6.13 ; + } + pin (a2) { + direction : input ; + capacitance : 3.53 ; + } + pin (z) { + function : "((b1 & b2 & !(a2)) | (!(b1) & !(b2)))" ; + direction : output ; + capacitance : 3.10 ; + timing (maxd_z_b1_positive_unate) { + related_pin : "b1" ; + when : "(!(a2) & b2)" ; + sdf_cond : "(!(a2) & b2)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__87) { + values ("92.3, 92.3, 92.3, 112.7, 153.3", \ + "89.5, 89.5, 89.5, 110.1, 150.8", \ + "78.7, 78.7, 78.7, 99.4, 140.4", \ + "50.8, 50.8, 50.8, 72.0, 113.4", \ + "-10.6, -10.6, -10.6, 10.9, 53.3"); + } + rise_transition (inslew_load_5x5__87) { + values ("125.7, 125.7, 125.7, 162.6, 236.9", \ + "134.6, 134.6, 134.6, 171.6, 245.6", \ + "151.1, 151.1, 151.1, 187.7, 261.6", \ + "182.2, 182.2, 182.2, 218.5, 291.6", \ + "242.9, 242.9, 242.9, 278.7, 350.9"); + } + cell_fall (inslew_load_5x5__87) { + values ("103.0, 103.0, 103.0, 117.3, 144.3", \ + "123.5, 123.5, 123.5, 138.4, 166.7", \ + "157.5, 157.5, 157.5, 173.4, 203.5", \ + "219.7, 219.7, 219.7, 236.6, 268.8", \ + "339.7, 339.7, 339.7, 357.6, 392.1"); + } + fall_transition (inslew_load_5x5__87) { + values ("83.1, 83.1, 83.1, 100.2, 134.4", \ + "101.8, 101.8, 101.8, 118.9, 152.9", \ + "136.5, 136.5, 136.5, 153.8, 187.9", \ + "204.2, 204.2, 204.2, 221.6, 256.2", \ + "338.3, 338.3, 338.3, 355.9, 390.9"); + } + } + timing (maxd_z_b2_positive_unate) { + related_pin : "b2" ; + when : "(!(a2) & b1)" ; + sdf_cond : "(!(a2) & b1)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__87) { + values ("90.4, 90.4, 90.4, 110.7, 151.3", \ + "91.5, 91.5, 91.5, 112.1, 152.8", \ + "88.2, 88.2, 88.2, 108.9, 150.0", \ + "75.8, 75.8, 75.8, 97.1, 138.5", \ + "46.7, 46.7, 46.7, 68.3, 110.6"); + } + rise_transition (inslew_load_5x5__87) { + values ("121.2, 121.2, 121.2, 158.0, 232.5", \ + "132.2, 132.2, 132.2, 169.2, 243.3", \ + "151.9, 151.9, 151.9, 188.5, 262.3", \ + "188.9, 188.9, 188.9, 225.1, 298.3", \ + "262.1, 262.1, 262.1, 297.7, 369.7"); + } + cell_fall (inslew_load_5x5__87) { + values ("90.9, 90.9, 90.9, 104.8, 131.2", \ + "105.2, 105.2, 105.2, 119.7, 147.3", \ + "127.5, 127.5, 127.5, 143.0, 172.3", \ + "166.5, 166.5, 166.5, 183.0, 214.5", \ + "240.0, 240.0, 240.0, 257.6, 291.3"); + } + fall_transition (inslew_load_5x5__87) { + values ("75.2, 75.2, 75.2, 92.3, 126.6", \ + "90.6, 90.6, 90.6, 107.7, 142.0", \ + "119.0, 119.0, 119.0, 136.2, 170.3", \ + "174.3, 174.3, 174.3, 191.7, 226.1", \ + "283.8, 283.8, 283.8, 301.3, 336.2"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__87) { + values ("54.1, 54.1, 54.1, 75.6, 117.5", \ + "70.3, 70.3, 70.3, 93.0, 136.4", \ + "98.0, 98.0, 98.0, 122.0, 168.0", \ + "149.7, 149.7, 149.7, 175.1, 223.7", \ + "250.7, 250.7, 250.7, 277.0, 328.1"); + } + rise_transition (inslew_load_5x5__87) { + values ("96.7, 96.7, 96.7, 133.9, 209.6", \ + "140.6, 140.6, 140.6, 178.4, 252.2", \ + "224.2, 224.2, 224.2, 261.1, 335.0", \ + "388.0, 388.0, 388.0, 425.3, 499.3", \ + "713.6, 713.6, 713.6, 751.2, 826.0"); + } + cell_fall (inslew_load_5x5__87) { + values ("30.5, 30.5, 30.5, 44.1, 69.7", \ + "26.9, 26.9, 26.9, 42.1, 70.0", \ + "15.4, 15.4, 15.4, 33.0, 64.7", \ + "-12.0, -12.0, -12.0, 7.9, 44.5", \ + "-71.2, -71.2, -71.2, -49.1, -7.8"); + } + fall_transition (inslew_load_5x5__87) { + values ("47.2, 47.2, 47.2, 64.4, 98.9", \ + "60.4, 60.4, 60.4, 77.6, 111.9", \ + "85.6, 85.6, 85.6, 103.3, 137.9", \ + "134.4, 134.4, 134.4, 152.9, 188.6", \ + "230.8, 230.8, 230.8, 249.9, 287.1"); + } + } + timing (maxd_z_b1_negative_unate) { + related_pin : "b1" ; + when : "!(b2)" ; + sdf_cond : "!(b2)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__87) { + values ("47.4, 47.4, 47.4, 68.3, 109.3", \ + "47.9, 47.9, 47.9, 69.4, 111.4", \ + "47.4, 47.4, 47.4, 69.9, 113.2", \ + "44.7, 44.7, 44.7, 68.3, 113.7", \ + "37.7, 37.7, 37.7, 62.2, 109.9"); + } + rise_transition (inslew_load_5x5__87) { + values ("97.6, 97.6, 97.6, 134.2, 208.1", \ + "126.2, 126.2, 126.2, 162.2, 235.1", \ + "181.7, 181.7, 181.7, 218.2, 289.5", \ + "292.7, 292.7, 292.7, 328.4, 401.7", \ + "514.4, 514.4, 514.4, 550.2, 621.6"); + } + cell_fall (inslew_load_5x5__87) { + values ("32.1, 32.1, 32.1, 46.7, 73.4", \ + "40.0, 40.0, 40.0, 56.2, 85.6", \ + "51.7, 51.7, 51.7, 69.8, 102.8", \ + "72.3, 72.3, 72.3, 91.8, 128.4", \ + "111.6, 111.6, 111.6, 132.0, 171.3"); + } + fall_transition (inslew_load_5x5__87) { + values ("43.9, 43.9, 43.9, 61.2, 96.0", \ + "66.8, 66.8, 66.8, 84.4, 118.9", \ + "110.2, 110.2, 110.2, 128.2, 163.4", \ + "195.3, 195.3, 195.3, 213.7, 249.8", \ + "364.3, 364.3, 364.3, 383.0, 419.9"); + } + } + timing (maxd_z_b2_negative_unate) { + related_pin : "b2" ; + when : "!(b1)" ; + sdf_cond : "!(b1)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__87) { + values ("34.3, 34.3, 34.3, 57.2, 99.7", \ + "43.8, 43.8, 43.8, 68.2, 113.0", \ + "58.8, 58.8, 58.8, 85.0, 133.3", \ + "86.0, 86.0, 86.0, 113.8, 166.0", \ + "138.9, 138.9, 138.9, 167.6, 223.0"); + } + rise_transition (inslew_load_5x5__87) { + values ("64.6, 64.6, 64.6, 102.0, 177.1", \ + "100.4, 100.4, 100.4, 137.4, 211.9", \ + "167.4, 167.4, 167.4, 205.0, 278.9", \ + "298.7, 298.7, 298.7, 336.8, 411.9", \ + "560.0, 560.0, 560.0, 598.4, 674.5"); + } + cell_fall (inslew_load_5x5__87) { + values ("21.6, 21.6, 21.6, 37.3, 64.9", \ + "21.0, 21.0, 21.0, 39.5, 70.9", \ + "16.1, 16.1, 16.1, 37.5, 74.3", \ + "3.5, 3.5, 3.5, 27.2, 69.7", \ + "-23.8, -23.8, -23.8, 1.6, 48.9"); + } + fall_transition (inslew_load_5x5__87) { + values ("32.6, 32.6, 32.6, 50.1, 84.8", \ + "48.3, 48.3, 48.3, 66.5, 101.3", \ + "77.6, 77.6, 77.6, 96.7, 132.9", \ + "134.8, 134.8, 134.8, 154.6, 192.7", \ + "248.2, 248.2, 248.2, 268.6, 308.3"); + } + } + internal_power (energy_pos_z_b1) { + related_pin : "b1" ; + when : "(!(a2) & b2)" ; + rise_power (energy_inslew_load_5x5__87) { + values ("259.5, 259.5, 259.5, 298.2, 375.7", \ + "286.4, 286.4, 286.4, 325.1, 402.6", \ + "339.5, 339.5, 339.5, 378.2, 455.6", \ + "444.6, 444.6, 444.6, 483.3, 560.7", \ + "653.6, 653.6, 653.6, 692.3, 769.8"); + } + fall_power (energy_inslew_load_5x5__87) { + values ("310.9, 310.9, 310.9, 349.6, 427.1", \ + "391.0, 391.0, 391.0, 429.7, 507.2", \ + "547.8, 547.8, 547.8, 586.5, 664.0", \ + "859.5, 859.5, 859.5, 898.2, 975.7", \ + "1481.8, 1481.8, 1481.8, 1520.5, 1598.0"); + } + } + internal_power (energy_pos_z_b2) { + related_pin : "b2" ; + when : "(!(a2) & b1)" ; + rise_power (energy_inslew_load_5x5__87) { + values ("230.4, 230.4, 230.4, 269.1, 346.6", \ + "261.6, 261.6, 261.6, 300.4, 377.8", \ + "322.9, 322.9, 322.9, 361.6, 439.1", \ + "444.2, 444.2, 444.2, 482.9, 560.4", \ + "686.1, 686.1, 686.1, 724.8, 802.2"); + } + fall_power (energy_inslew_load_5x5__87) { + values ("266.8, 266.8, 266.8, 305.5, 383.0", \ + "330.2, 330.2, 330.2, 369.0, 446.4", \ + "454.4, 454.4, 454.4, 493.1, 570.5", \ + "700.9, 700.9, 700.9, 739.6, 817.1", \ + "1193.1, 1193.1, 1193.1, 1231.9, 1309.3"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__87) { + values ("98.6, 98.6, 98.6, 137.3, 214.8", \ + "132.2, 132.2, 132.2, 170.9, 248.4", \ + "199.4, 199.4, 199.4, 238.1, 315.5", \ + "333.7, 333.7, 333.7, 372.4, 449.9", \ + "602.4, 602.4, 602.4, 641.1, 718.5"); + } + fall_power (energy_inslew_load_5x5__87) { + values ("91.2, 91.2, 91.2, 130.0, 207.4", \ + "106.9, 106.9, 106.9, 145.7, 223.1", \ + "138.3, 138.3, 138.3, 177.0, 254.5", \ + "201.1, 201.1, 201.1, 239.8, 317.3", \ + "326.6, 326.6, 326.6, 365.4, 442.8"); + } + } + internal_power (energy_neg_z_b1) { + related_pin : "b1" ; + when : "!(b2)" ; + rise_power (energy_inslew_load_5x5__87) { + values ("97.6, 97.6, 97.6, 136.3, 213.7", \ + "121.8, 121.8, 121.8, 160.5, 238.0", \ + "170.2, 170.2, 170.2, 209.0, 286.4", \ + "267.1, 267.1, 267.1, 305.9, 383.3", \ + "461.0, 461.0, 461.0, 499.7, 577.1"); + } + fall_power (energy_inslew_load_5x5__87) { + values ("86.3, 86.3, 86.3, 125.0, 202.4", \ + "117.0, 117.0, 117.0, 155.7, 233.1", \ + "178.4, 178.4, 178.4, 217.1, 294.5", \ + "301.2, 301.2, 301.2, 339.9, 417.3", \ + "546.8, 546.8, 546.8, 585.5, 662.9"); + } + } + internal_power (energy_neg_z_b2) { + related_pin : "b2" ; + when : "!(b1)" ; + rise_power (energy_inslew_load_5x5__87) { + values ("63.0, 63.0, 63.0, 101.8, 179.2", \ + "88.5, 88.5, 88.5, 127.2, 204.7", \ + "139.5, 139.5, 139.5, 178.2, 255.6", \ + "241.4, 241.4, 241.4, 280.1, 357.6", \ + "445.2, 445.2, 445.2, 484.0, 561.4"); + } + fall_power (energy_inslew_load_5x5__87) { + values ("57.2, 57.2, 57.2, 95.9, 173.3", \ + "74.4, 74.4, 74.4, 113.1, 190.6", \ + "108.9, 108.9, 108.9, 147.6, 225.1", \ + "178.0, 178.0, 178.0, 216.7, 294.1", \ + "316.0, 316.0, 316.0, 354.7, 432.2"); + } + } + } + } + + cell (oai31v0x05) { + area : 0.0 ; + cell_leakage_power : 3 ; + leakage_power () { + when : "(!(b) & a3 & a2 & a1)" ; + value : 0.00017 ; + } + leakage_power () { + when : "(b & !(a3) & !(a2) & a1)" ; + value : 7.7 ; + } + leakage_power () { + when : "((a1 & (a2 ^ a3) & !(b)) | (!(a1) & a2 & a3 & !(b)))" ; + value : 0.00012 ; + } + leakage_power () { + when : "((a1 & (a2 ^ a3) & b) | (a2 & !(a3) & b))" ; + value : 7.8 ; + } + leakage_power () { + when : "(!((a1 & !(a2))) & a3 & b)" ; + value : 8.5 ; + } + leakage_power () { + when : "((a1 & !(a2) & !(a3) & !(b)) | (!(a1) & (a2 ^ a3) & !(b)))" ; + value : 5.9e-05 ; + } + leakage_power () { + when : "(b & !(a3) & !(a2) & !(a1))" ; + value : 0.00014 ; + } + leakage_power () { + when : "(!(b) & !(a3) & !(a2) & !(a1))" ; + value : 2.9e-06 ; + } + pin (b) { + direction : input ; + capacitance : 2.89 ; + } + pin (a3) { + direction : input ; + capacitance : 4.73 ; + } + pin (a2) { + direction : input ; + capacitance : 4.64 ; + } + pin (a1) { + direction : input ; + capacitance : 4.82 ; + } + pin (z) { + function : "(((!(a3) & !(a2)) & !(a1)) | !(b))" ; + direction : output ; + capacitance : 3.61 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__88) { + values ("118.8, 118.8, 118.8, 143.4, 192.6", \ + "127.5, 127.5, 127.5, 152.3, 201.9", \ + "142.3, 142.3, 142.3, 167.3, 217.3", \ + "172.5, 172.5, 172.5, 197.5, 247.5", \ + "233.8, 233.8, 233.8, 258.8, 308.8"); + } + rise_transition (inslew_load_5x5__88) { + values ("213.8, 213.8, 213.8, 255.8, 340.1", \ + "262.7, 262.7, 262.7, 304.4, 388.2", \ + "353.8, 353.8, 353.8, 395.7, 479.6", \ + "533.3, 533.3, 533.3, 574.9, 658.6", \ + "893.4, 893.4, 893.4, 934.6, 1017.4"); + } + cell_fall (inslew_load_5x5__88) { + values ("42.8, 42.8, 42.8, 53.9, 75.6", \ + "47.8, 47.8, 47.8, 59.8, 82.9", \ + "54.0, 54.0, 54.0, 67.3, 92.5", \ + "63.0, 63.0, 63.0, 77.4, 105.1", \ + "78.4, 78.4, 78.4, 93.6, 123.3"); + } + fall_transition (inslew_load_5x5__88) { + values ("58.6, 58.6, 58.6, 73.0, 102.0", \ + "79.4, 79.4, 79.4, 93.7, 122.4", \ + "119.4, 119.4, 119.4, 133.9, 162.4", \ + "198.2, 198.2, 198.2, 212.8, 241.8", \ + "354.8, 354.8, 354.8, 369.6, 399.0"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__88) { + values ("92.5, 92.5, 92.5, 117.4, 167.0", \ + "108.6, 108.6, 108.6, 133.8, 183.9", \ + "136.0, 136.0, 136.0, 161.8, 212.5", \ + "188.7, 188.7, 188.7, 214.7, 266.2", \ + "292.6, 292.6, 292.6, 319.0, 371.4"); + } + rise_transition (inslew_load_5x5__88) { + values ("161.0, 161.0, 161.0, 203.4, 288.8", \ + "212.3, 212.3, 212.3, 254.3, 339.0", \ + "307.0, 307.0, 307.0, 348.6, 432.3", \ + "494.2, 494.2, 494.2, 535.1, 617.5", \ + "868.0, 868.0, 868.0, 908.5, 989.8"); + } + cell_fall (inslew_load_5x5__88) { + values ("36.2, 36.2, 36.2, 47.6, 69.5", \ + "34.9, 34.9, 34.9, 47.6, 71.5", \ + "27.8, 27.8, 27.8, 42.4, 69.5", \ + "8.9, 8.9, 8.9, 25.4, 56.3", \ + "-33.1, -33.1, -33.1, -15.0, 19.5"); + } + fall_transition (inslew_load_5x5__88) { + values ("50.6, 50.6, 50.6, 65.0, 93.9", \ + "65.1, 65.1, 65.1, 79.6, 108.3", \ + "92.8, 92.8, 92.8, 107.6, 136.5", \ + "146.6, 146.6, 146.6, 161.9, 191.7", \ + "252.8, 252.8, 252.8, 268.5, 299.4"); + } + } + timing (maxd_z_a3_negative_unate) { + related_pin : "a3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__88) { + values ("58.6, 58.6, 58.6, 84.3, 134.7", \ + "78.7, 78.7, 78.7, 105.3, 156.8", \ + "115.9, 115.9, 115.9, 143.3, 196.2", \ + "186.3, 186.3, 186.3, 214.5, 269.2", \ + "324.0, 324.0, 324.0, 352.6, 408.9"); + } + rise_transition (inslew_load_5x5__88) { + values ("100.5, 100.5, 100.5, 143.0, 229.3", \ + "152.5, 152.5, 152.5, 194.5, 279.5", \ + "250.9, 250.9, 250.9, 293.5, 376.8", \ + "443.5, 443.5, 443.5, 485.1, 570.3", \ + "825.0, 825.0, 825.0, 866.4, 949.3"); + } + cell_fall (inslew_load_5x5__88) { + values ("27.0, 27.0, 27.0, 39.0, 61.5", \ + "21.5, 21.5, 21.5, 35.3, 60.3", \ + "5.9, 5.9, 5.9, 22.2, 51.4", \ + "-30.4, -30.4, -30.4, -11.3, 22.9", \ + "-107.6, -107.6, -107.6, -86.2, -46.6"); + } + fall_transition (inslew_load_5x5__88) { + values ("40.2, 40.2, 40.2, 54.6, 83.3", \ + "51.4, 51.4, 51.4, 66.1, 94.7", \ + "72.4, 72.4, 72.4, 87.7, 117.1", \ + "112.7, 112.7, 112.7, 128.8, 159.8", \ + "191.6, 191.6, 191.6, 208.5, 241.1"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__88) { + values ("34.4, 34.4, 34.4, 54.5, 90.7", \ + "45.9, 45.9, 45.9, 68.0, 107.7", \ + "65.4, 65.4, 65.4, 89.4, 133.3", \ + "102.0, 102.0, 102.0, 127.5, 175.4", \ + "173.8, 173.8, 173.8, 200.2, 251.1"); + } + rise_transition (inslew_load_5x5__88) { + values ("68.2, 68.2, 68.2, 104.6, 176.9", \ + "106.9, 106.9, 106.9, 143.9, 216.5", \ + "180.3, 180.3, 180.3, 217.9, 291.8", \ + "324.9, 324.9, 324.9, 362.9, 438.1", \ + "612.7, 612.7, 612.7, 651.0, 727.0"); + } + cell_fall (inslew_load_5x5__88) { + values ("16.9, 16.9, 16.9, 31.0, 55.3", \ + "13.7, 13.7, 13.7, 30.6, 58.9", \ + "3.9, 3.9, 3.9, 23.7, 57.6", \ + "-18.3, -18.3, -18.3, 3.9, 43.6", \ + "-64.9, -64.9, -64.9, -40.8, 3.8"); + } + fall_transition (inslew_load_5x5__88) { + values ("28.8, 28.8, 28.8, 43.5, 72.3", \ + "41.9, 41.9, 41.9, 57.4, 86.8", \ + "66.7, 66.7, 66.7, 83.2, 114.2", \ + "115.1, 115.1, 115.1, 132.5, 165.6", \ + "211.2, 211.2, 211.2, 229.3, 264.1"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__88) { + values ("227.6, 227.6, 227.6, 272.7, 362.9", \ + "274.4, 274.4, 274.4, 319.5, 409.7", \ + "367.9, 367.9, 367.9, 413.0, 503.2", \ + "555.0, 555.0, 555.0, 600.1, 690.3", \ + "929.1, 929.1, 929.1, 974.2, 1064.4"); + } + fall_power (energy_inslew_load_5x5__88) { + values ("170.1, 170.1, 170.1, 215.2, 305.3", \ + "212.8, 212.8, 212.8, 257.9, 348.0", \ + "298.2, 298.2, 298.2, 343.3, 433.5", \ + "469.1, 469.1, 469.1, 514.1, 604.3", \ + "810.8, 810.8, 810.8, 855.9, 946.0"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__88) { + values ("175.0, 175.0, 175.0, 220.0, 310.2", \ + "220.4, 220.4, 220.4, 265.5, 355.6", \ + "311.2, 311.2, 311.2, 356.3, 446.5", \ + "492.9, 492.9, 492.9, 537.9, 628.1", \ + "856.2, 856.2, 856.2, 901.2, 991.4"); + } + fall_power (energy_inslew_load_5x5__88) { + values ("139.5, 139.5, 139.5, 184.6, 274.8", \ + "164.0, 164.0, 164.0, 209.1, 299.3", \ + "213.0, 213.0, 213.0, 258.1, 348.3", \ + "311.0, 311.0, 311.0, 356.1, 446.3", \ + "507.1, 507.1, 507.1, 552.2, 642.3"); + } + } + internal_power (energy_neg_z_a3) { + related_pin : "a3" ; + rise_power (energy_inslew_load_5x5__88) { + values ("113.2, 113.2, 113.2, 158.3, 248.4", \ + "156.6, 156.6, 156.6, 201.7, 291.9", \ + "243.5, 243.5, 243.5, 288.6, 378.8", \ + "417.3, 417.3, 417.3, 462.4, 552.5", \ + "764.8, 764.8, 764.8, 809.9, 900.1"); + } + fall_power (energy_inslew_load_5x5__88) { + values ("104.0, 104.0, 104.0, 149.1, 239.3", \ + "119.6, 119.6, 119.6, 164.7, 254.8", \ + "150.7, 150.7, 150.7, 195.8, 286.0", \ + "213.1, 213.1, 213.1, 258.2, 348.3", \ + "337.7, 337.7, 337.7, 382.8, 473.0"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__88) { + values ("77.0, 77.0, 77.0, 122.1, 212.2", \ + "110.8, 110.8, 110.8, 155.9, 246.1", \ + "178.6, 178.6, 178.6, 223.7, 313.8", \ + "314.1, 314.1, 314.1, 359.2, 449.3", \ + "585.0, 585.0, 585.0, 630.1, 720.3"); + } + fall_power (energy_inslew_load_5x5__88) { + values ("65.3, 65.3, 65.3, 110.4, 200.6", \ + "83.5, 83.5, 83.5, 128.6, 218.8", \ + "119.9, 119.9, 119.9, 165.0, 255.2", \ + "192.8, 192.8, 192.8, 237.9, 328.1", \ + "338.6, 338.6, 338.6, 383.7, 473.8"); + } + } + } + } + + cell (oai31v0x1) { + area : 0.0 ; + cell_leakage_power : 0.83 ; + leakage_power () { + when : "(!(b) & a3 & a2 & a1)" ; + value : 0.00027 ; + } + leakage_power () { + when : "(b & !(a3) & !(a2) & a1)" ; + value : 1.7 ; + } + leakage_power () { + when : "((a1 & (a2 ^ a3) & !(b)) | (!(a1) & a2 & a3 & !(b)))" ; + value : 0.00018 ; + } + leakage_power () { + when : "((a1 & (a2 ^ a3) & b) | (a2 & !(a3) & b))" ; + value : 1.8 ; + } + leakage_power () { + when : "(!((a1 & !(a2))) & a3 & b)" ; + value : 3.2 ; + } + leakage_power () { + when : "((a1 & !(a2) & !(a3) & !(b)) | (!(a1) & (a2 ^ a3) & !(b)))" ; + value : 9.1e-05 ; + } + leakage_power () { + when : "(b & !(a3) & !(a2) & !(a1))" ; + value : 0.00021 ; + } + leakage_power () { + when : "(!(b) & !(a3) & !(a2) & !(a1))" ; + value : 4.5e-06 ; + } + pin (b) { + direction : input ; + capacitance : 4.36 ; + } + pin (a3) { + direction : input ; + capacitance : 7.54 ; + } + pin (a2) { + direction : input ; + capacitance : 8.45 ; + } + pin (a1) { + direction : input ; + capacitance : 9.06 ; + } + pin (z) { + function : "(((!(a3) & !(a2)) & !(a1)) | !(b))" ; + direction : output ; + capacitance : 5.85 ; + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__89) { + values ("108.2, 108.2, 108.2, 128.6, 169.3", \ + "112.8, 112.8, 112.8, 133.4, 174.5", \ + "120.1, 120.1, 120.1, 140.9, 182.3", \ + "135.5, 135.5, 135.5, 156.3, 197.8", \ + "167.1, 167.1, 167.1, 188.1, 229.8"); + } + rise_transition (inslew_load_5x5__89) { + values ("197.2, 197.2, 197.2, 232.0, 302.0", \ + "239.1, 239.1, 239.1, 273.9, 343.4", \ + "317.3, 317.3, 317.3, 352.1, 421.8", \ + "472.3, 472.3, 472.3, 506.7, 575.6", \ + "783.4, 783.4, 783.4, 817.4, 885.7"); + } + cell_fall (inslew_load_5x5__89) { + values ("44.7, 44.7, 44.7, 54.8, 74.7", \ + "52.0, 52.0, 52.0, 63.0, 84.1", \ + "63.0, 63.0, 63.0, 74.9, 97.9", \ + "81.7, 81.7, 81.7, 94.5, 119.4", \ + "116.8, 116.8, 116.8, 130.4, 156.9"); + } + fall_transition (inslew_load_5x5__89) { + values ("59.8, 59.8, 59.8, 73.0, 99.6", \ + "82.8, 82.8, 82.8, 96.0, 122.4", \ + "127.0, 127.0, 127.0, 140.2, 166.4", \ + "214.0, 214.0, 214.0, 227.3, 253.8", \ + "386.9, 386.9, 386.9, 400.4, 427.1"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__89) { + values ("83.7, 83.7, 83.7, 104.3, 145.5", \ + "96.6, 96.6, 96.6, 117.6, 159.3", \ + "118.4, 118.4, 118.4, 139.8, 182.3", \ + "160.1, 160.1, 160.1, 181.9, 225.1", \ + "241.9, 241.9, 241.9, 264.2, 308.3"); + } + rise_transition (inslew_load_5x5__89) { + values ("147.3, 147.3, 147.3, 182.5, 253.3", \ + "193.5, 193.5, 193.5, 228.3, 298.5", \ + "279.5, 279.5, 279.5, 313.9, 383.2", \ + "450.1, 450.1, 450.1, 484.0, 552.1", \ + "791.1, 791.1, 791.1, 824.6, 891.9"); + } + cell_fall (inslew_load_5x5__89) { + values ("37.2, 37.2, 37.2, 47.7, 67.9", \ + "37.3, 37.3, 37.3, 48.9, 70.9", \ + "33.2, 33.2, 33.2, 46.4, 71.2", \ + "20.5, 20.5, 20.5, 35.4, 63.4", \ + "-8.3, -8.3, -8.3, 7.8, 38.8"); + } + fall_transition (inslew_load_5x5__89) { + values ("50.7, 50.7, 50.7, 64.0, 90.5", \ + "66.4, 66.4, 66.4, 79.7, 105.9", \ + "96.3, 96.3, 96.3, 109.8, 136.4", \ + "154.4, 154.4, 154.4, 168.4, 195.7", \ + "269.6, 269.6, 269.6, 283.8, 311.9"); + } + } + timing (maxd_z_a3_negative_unate) { + related_pin : "a3" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__89) { + values ("50.5, 50.5, 50.5, 72.2, 114.1", \ + "67.4, 67.4, 67.4, 89.9, 133.2", \ + "99.1, 99.1, 99.1, 122.3, 167.1", \ + "159.3, 159.3, 159.3, 182.9, 229.4", \ + "276.5, 276.5, 276.5, 300.7, 348.1"); + } + rise_transition (inslew_load_5x5__89) { + values ("88.5, 88.5, 88.5, 123.7, 195.2", \ + "135.8, 135.8, 135.8, 170.7, 241.0", \ + "226.4, 226.4, 226.4, 261.1, 331.4", \ + "404.5, 404.5, 404.5, 438.8, 508.0", \ + "757.0, 757.0, 757.0, 791.5, 859.9"); + } + cell_fall (inslew_load_5x5__89) { + values ("26.9, 26.9, 26.9, 38.1, 58.9", \ + "22.4, 22.4, 22.4, 35.2, 58.4", \ + "9.0, 9.0, 9.0, 24.0, 50.9", \ + "-22.0, -22.0, -22.0, -4.8, 26.5", \ + "-87.8, -87.8, -87.8, -68.8, -33.2"); + } + fall_transition (inslew_load_5x5__89) { + values ("39.2, 39.2, 39.2, 52.5, 78.8", \ + "51.2, 51.2, 51.2, 64.7, 91.0", \ + "73.7, 73.7, 73.7, 87.8, 114.9", \ + "117.3, 117.3, 117.3, 131.9, 160.3", \ + "203.0, 203.0, 203.0, 218.2, 247.9"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__89) { + values ("31.7, 31.7, 31.7, 50.2, 83.2", \ + "42.4, 42.4, 42.4, 62.8, 99.2", \ + "60.6, 60.6, 60.6, 82.8, 123.2", \ + "94.9, 94.9, 94.9, 118.4, 162.5", \ + "162.1, 162.1, 162.1, 186.4, 233.2"); + } + rise_transition (inslew_load_5x5__89) { + values ("58.5, 58.5, 58.5, 88.8, 148.9", \ + "93.3, 93.3, 93.3, 124.2, 184.5", \ + "159.5, 159.5, 159.5, 190.8, 252.3", \ + "289.7, 289.7, 289.7, 321.4, 384.0", \ + "548.9, 548.9, 548.9, 580.9, 644.3"); + } + cell_fall (inslew_load_5x5__89) { + values ("15.8, 15.8, 15.8, 29.1, 51.8", \ + "12.6, 12.6, 12.6, 28.5, 55.1", \ + "3.0, 3.0, 3.0, 21.5, 53.3", \ + "-18.6, -18.6, -18.6, 2.1, 39.2", \ + "-63.7, -63.7, -63.7, -41.3, 0.2"); + } + fall_transition (inslew_load_5x5__89) { + values ("27.5, 27.5, 27.5, 41.1, 67.5", \ + "40.4, 40.4, 40.4, 54.7, 81.9", \ + "64.9, 64.9, 64.9, 80.2, 108.9", \ + "113.0, 113.0, 113.0, 129.0, 159.6", \ + "208.4, 208.4, 208.4, 225.0, 257.2"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__89) { + values ("406.7, 406.7, 406.7, 479.7, 625.9", \ + "484.5, 484.5, 484.5, 557.5, 703.7", \ + "640.1, 640.1, 640.1, 713.2, 859.3", \ + "951.3, 951.3, 951.3, 1024.4, 1170.5", \ + "1573.8, 1573.8, 1573.8, 1646.8, 1793.0"); + } + fall_power (energy_inslew_load_5x5__89) { + values ("313.6, 313.6, 313.6, 386.6, 532.8", \ + "400.0, 400.0, 400.0, 473.1, 619.2", \ + "572.8, 572.8, 572.8, 645.9, 792.0", \ + "918.5, 918.5, 918.5, 991.6, 1137.7", \ + "1609.9, 1609.9, 1609.9, 1682.9, 1829.1"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__89) { + values ("309.0, 309.0, 309.0, 382.1, 528.2", \ + "388.3, 388.3, 388.3, 461.4, 607.5", \ + "546.9, 546.9, 546.9, 620.0, 766.2", \ + "864.2, 864.2, 864.2, 937.2, 1083.4", \ + "1498.6, 1498.6, 1498.6, 1571.7, 1717.9"); + } + fall_power (energy_inslew_load_5x5__89) { + values ("250.4, 250.4, 250.4, 323.5, 469.6", \ + "299.3, 299.3, 299.3, 372.3, 518.5", \ + "397.0, 397.0, 397.0, 470.1, 616.2", \ + "592.5, 592.5, 592.5, 665.6, 811.7", \ + "983.5, 983.5, 983.5, 1056.6, 1202.7"); + } + } + internal_power (energy_neg_z_a3) { + related_pin : "a3" ; + rise_power (energy_inslew_load_5x5__89) { + values ("191.0, 191.0, 191.0, 264.1, 410.2", \ + "267.8, 267.8, 267.8, 340.8, 487.0", \ + "421.3, 421.3, 421.3, 494.4, 640.5", \ + "728.4, 728.4, 728.4, 801.4, 947.6", \ + "1342.5, 1342.5, 1342.5, 1415.5, 1561.7"); + } + fall_power (energy_inslew_load_5x5__89) { + values ("180.0, 180.0, 180.0, 253.0, 399.2", \ + "211.4, 211.4, 211.4, 284.5, 430.6", \ + "274.3, 274.3, 274.3, 347.4, 493.6", \ + "400.2, 400.2, 400.2, 473.2, 619.4", \ + "651.8, 651.8, 651.8, 724.9, 871.0"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__89) { + values ("127.5, 127.5, 127.5, 200.6, 346.7", \ + "185.7, 185.7, 185.7, 258.8, 404.9", \ + "302.1, 302.1, 302.1, 375.2, 521.3", \ + "534.9, 534.9, 534.9, 607.9, 754.1", \ + "1000.4, 1000.4, 1000.4, 1073.4, 1219.6"); + } + fall_power (energy_inslew_load_5x5__89) { + values ("108.8, 108.8, 108.8, 181.8, 328.0", \ + "140.7, 140.7, 140.7, 213.8, 359.9", \ + "204.6, 204.6, 204.6, 277.7, 423.8", \ + "332.4, 332.4, 332.4, 405.5, 551.6", \ + "588.0, 588.0, 588.0, 661.1, 807.2"); + } + } + } + } + + cell (oan21bv0x05) { + area : 0.0 ; + cell_leakage_power : 1.2 ; + leakage_power () { + when : "(b & !(a2) & a1)" ; + value : 1.5 ; + } + leakage_power () { + when : "(a2 & b)" ; + value : 2 ; + } + leakage_power () { + when : "((!(a1) & (a2 ^ b)) | (a2 & !(b)))" ; + value : 1 ; + } + leakage_power () { + when : "(!(a2) & !(b))" ; + value : 0.44 ; + } + pin (b) { + direction : input ; + capacitance : 3.46 ; + } + pin (a2) { + direction : input ; + capacitance : 3.60 ; + } + pin (a1) { + direction : input ; + capacitance : 3.52 ; + } + pin (z) { + function : "((a1 | a2) & !(b))" ; + direction : output ; + capacitance : 3.32 ; + timing (maxd_z_a1_positive_unate) { + related_pin : "a1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__90) { + values ("83.3, 83.3, 83.3, 100.4, 134.0", \ + "94.3, 94.3, 94.3, 111.8, 145.8", \ + "110.8, 110.8, 110.8, 128.8, 163.8", \ + "139.0, 139.0, 139.0, 157.8, 193.9", \ + "191.2, 191.2, 191.2, 211.1, 249.1"); + } + rise_transition (inslew_load_5x5__90) { + values ("87.0, 87.0, 87.0, 117.2, 178.3", \ + "99.1, 99.1, 99.1, 129.0, 189.6", \ + "121.9, 121.9, 121.9, 151.4, 211.1", \ + "164.9, 164.9, 164.9, 194.7, 254.7", \ + "251.1, 251.1, 251.1, 281.0, 340.3"); + } + cell_fall (inslew_load_5x5__90) { + values ("100.6, 100.6, 100.6, 115.5, 142.4", \ + "103.6, 103.6, 103.6, 118.9, 146.8", \ + "107.3, 107.3, 107.3, 123.3, 152.6", \ + "111.4, 111.4, 111.4, 128.1, 159.3", \ + "115.6, 115.6, 115.6, 133.1, 166.2"); + } + fall_transition (inslew_load_5x5__90) { + values ("70.2, 70.2, 70.2, 83.4, 109.3", \ + "82.0, 82.0, 82.0, 95.4, 121.4", \ + "105.2, 105.2, 105.2, 118.7, 145.0", \ + "151.0, 151.0, 151.0, 164.8, 191.6", \ + "242.0, 242.0, 242.0, 255.9, 283.4"); + } + } + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__90) { + values ("72.2, 72.2, 72.2, 89.1, 122.4", \ + "75.0, 75.0, 75.0, 92.2, 125.9", \ + "74.9, 74.9, 74.9, 92.6, 126.9", \ + "70.0, 70.0, 70.0, 88.3, 123.6", \ + "55.9, 55.9, 55.9, 75.2, 112.2"); + } + rise_transition (inslew_load_5x5__90) { + values ("81.5, 81.5, 81.5, 111.8, 173.1", \ + "90.5, 90.5, 90.5, 120.7, 181.6", \ + "106.8, 106.8, 106.8, 136.6, 196.9", \ + "137.6, 137.6, 137.6, 168.0, 227.1", \ + "198.7, 198.7, 198.7, 228.5, 289.2"); + } + cell_fall (inslew_load_5x5__90) { + values ("84.5, 84.5, 84.5, 98.7, 124.3", \ + "98.3, 98.3, 98.3, 113.2, 140.2", \ + "119.8, 119.8, 119.8, 135.7, 164.7", \ + "157.3, 157.3, 157.3, 174.0, 205.4", \ + "227.9, 227.9, 227.9, 245.6, 279.1"); + } + fall_transition (inslew_load_5x5__90) { + values ("55.8, 55.8, 55.8, 69.0, 94.7", \ + "71.4, 71.4, 71.4, 84.7, 110.6", \ + "100.4, 100.4, 100.4, 113.9, 140.2", \ + "156.4, 156.4, 156.4, 170.2, 197.1", \ + "267.0, 267.0, 267.0, 280.9, 308.5"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__90) { + values ("28.6, 28.6, 28.6, 47.7, 83.0", \ + "34.5, 34.5, 34.5, 55.3, 93.0", \ + "43.2, 43.2, 43.2, 65.8, 107.1", \ + "58.4, 58.4, 58.4, 82.4, 127.4", \ + "87.5, 87.5, 87.5, 112.4, 160.3"); + } + rise_transition (inslew_load_5x5__90) { + values ("58.5, 58.5, 58.5, 89.5, 151.2", \ + "89.9, 89.9, 89.9, 120.9, 182.3", \ + "149.9, 149.9, 149.9, 181.5, 243.4", \ + "268.0, 268.0, 268.0, 300.1, 363.2", \ + "503.2, 503.2, 503.2, 535.6, 599.7"); + } + cell_fall (inslew_load_5x5__90) { + values ("21.7, 21.7, 21.7, 36.4, 61.3", \ + "23.0, 23.0, 23.0, 40.1, 69.0", \ + "22.4, 22.4, 22.4, 41.8, 75.7", \ + "18.8, 18.8, 18.8, 40.1, 78.6", \ + "10.1, 10.1, 10.1, 32.6, 74.9"); + } + fall_transition (inslew_load_5x5__90) { + values ("28.2, 28.2, 28.2, 41.6, 67.5", \ + "45.3, 45.3, 45.3, 59.4, 85.9", \ + "77.6, 77.6, 77.6, 92.5, 120.5", \ + "140.7, 140.7, 140.7, 156.3, 186.1", \ + "265.9, 265.9, 265.9, 282.1, 313.3"); + } + } + internal_power (energy_pos_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__90) { + values ("242.3, 242.3, 242.3, 283.8, 366.8", \ + "295.8, 295.8, 295.8, 337.3, 420.3", \ + "401.2, 401.2, 401.2, 442.7, 525.7", \ + "611.1, 611.1, 611.1, 652.6, 735.6", \ + "1030.0, 1030.0, 1030.0, 1071.5, 1154.5"); + } + fall_power (energy_inslew_load_5x5__90) { + values ("295.6, 295.6, 295.6, 337.1, 420.1", \ + "341.9, 341.9, 341.9, 383.3, 466.3", \ + "433.9, 433.9, 433.9, 475.4, 558.4", \ + "618.3, 618.3, 618.3, 659.8, 742.8", \ + "986.5, 986.5, 986.5, 1028.0, 1111.0"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__90) { + values ("197.0, 197.0, 197.0, 238.5, 321.5", \ + "229.7, 229.7, 229.7, 271.2, 354.2", \ + "293.9, 293.9, 293.9, 335.4, 418.4", \ + "421.0, 421.0, 421.0, 462.5, 545.5", \ + "674.5, 674.5, 674.5, 716.0, 799.0"); + } + fall_power (energy_inslew_load_5x5__90) { + values ("229.4, 229.4, 229.4, 270.9, 353.9", \ + "283.9, 283.9, 283.9, 325.4, 408.4", \ + "390.4, 390.4, 390.4, 431.9, 514.9", \ + "601.4, 601.4, 601.4, 642.9, 725.9", \ + "1022.2, 1022.2, 1022.2, 1063.7, 1146.7"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__90) { + values ("69.7, 69.7, 69.7, 111.2, 194.2", \ + "98.4, 98.4, 98.4, 139.9, 222.9", \ + "155.7, 155.7, 155.7, 197.2, 280.2", \ + "270.3, 270.3, 270.3, 311.8, 394.8", \ + "499.6, 499.6, 499.6, 541.1, 624.1"); + } + fall_power (energy_inslew_load_5x5__90) { + values ("65.3, 65.3, 65.3, 106.8, 189.8", \ + "88.8, 88.8, 88.8, 130.3, 213.3", \ + "135.6, 135.6, 135.6, 177.1, 260.1", \ + "229.3, 229.3, 229.3, 270.8, 353.8", \ + "416.7, 416.7, 416.7, 458.2, 541.2"); + } + } + } + } + + cell (oan21v0x05) { + area : 0.0 ; + cell_leakage_power : 2.4 ; + leakage_power () { + when : "(b & !(a2) & a1)" ; + value : 0.9 ; + } + leakage_power () { + when : "(a2 & b)" ; + value : 1.3 ; + } + leakage_power () { + when : "(!((a1 | a2)) | !(b))" ; + value : 4.9 ; + } + pin (b) { + direction : input ; + capacitance : 2.51 ; + } + pin (a2) { + direction : input ; + capacitance : 3.19 ; + } + pin (a1) { + direction : input ; + capacitance : 3.24 ; + } + pin (z) { + function : "(b & (a1 | a2))" ; + direction : output ; + capacitance : 2.15 ; + timing (maxd_z_a1_positive_unate) { + related_pin : "a1" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__91) { + values ("65.2, 65.2, 65.2, 78.0, 100.4", \ + "70.1, 70.1, 70.1, 83.4, 106.9", \ + "75.6, 75.6, 75.6, 89.5, 114.6", \ + "81.8, 81.8, 81.8, 96.5, 123.5", \ + "90.2, 90.2, 90.2, 105.7, 134.7"); + } + rise_transition (inslew_load_5x5__91) { + values ("57.0, 57.0, 57.0, 77.1, 116.4", \ + "68.9, 68.9, 68.9, 89.2, 128.8", \ + "91.5, 91.5, 91.5, 112.0, 152.0", \ + "135.5, 135.5, 135.5, 156.2, 196.8", \ + "222.3, 222.3, 222.3, 243.1, 284.2"); + } + cell_fall (inslew_load_5x5__91) { + values ("91.6, 91.6, 91.6, 104.6, 127.3", \ + "99.6, 99.6, 99.6, 112.9, 136.9", \ + "113.0, 113.0, 113.0, 127.0, 152.2", \ + "138.3, 138.3, 138.3, 153.1, 180.1", \ + "187.2, 187.2, 187.2, 202.5, 231.6"); + } + fall_transition (inslew_load_5x5__91) { + values ("59.2, 59.2, 59.2, 68.9, 87.1", \ + "72.9, 72.9, 72.9, 82.8, 101.3", \ + "99.7, 99.7, 99.7, 109.6, 128.8", \ + "153.2, 153.2, 153.2, 163.3, 183.0", \ + "258.7, 258.7, 258.7, 269.0, 289.1"); + } + } + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__91) { + values ("54.8, 54.8, 54.8, 67.2, 88.9", \ + "52.7, 52.7, 52.7, 65.5, 88.1", \ + "43.1, 43.1, 43.1, 56.6, 80.4", \ + "17.9, 17.9, 17.9, 32.0, 57.6", \ + "-38.9, -38.9, -38.9, -23.9, 3.6"); + } + rise_transition (inslew_load_5x5__91) { + values ("49.9, 49.9, 49.9, 69.9, 108.9", \ + "58.0, 58.0, 58.0, 78.1, 117.5", \ + "73.0, 73.0, 73.0, 93.3, 133.0", \ + "101.5, 101.5, 101.5, 122.0, 162.2", \ + "156.7, 156.7, 156.7, 177.4, 218.2"); + } + cell_fall (inslew_load_5x5__91) { + values ("78.8, 78.8, 78.8, 91.3, 112.7", \ + "96.7, 96.7, 96.7, 109.7, 132.9", \ + "126.7, 126.7, 126.7, 140.6, 165.5", \ + "182.3, 182.3, 182.3, 197.1, 224.1", \ + "289.7, 289.7, 289.7, 305.1, 334.3"); + } + fall_transition (inslew_load_5x5__91) { + values ("47.0, 47.0, 47.0, 56.4, 74.2", \ + "62.9, 62.9, 62.9, 72.7, 91.0", \ + "92.8, 92.8, 92.8, 102.8, 121.8", \ + "151.4, 151.4, 151.4, 161.5, 181.2", \ + "267.3, 267.3, 267.3, 277.6, 297.8"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__91) { + values ("45.1, 45.1, 45.1, 56.9, 77.8", \ + "45.2, 45.2, 45.2, 57.6, 79.5", \ + "39.7, 39.7, 39.7, 52.9, 76.2", \ + "22.8, 22.8, 22.8, 36.8, 62.3", \ + "-16.2, -16.2, -16.2, -1.2, 26.3"); + } + rise_transition (inslew_load_5x5__91) { + values ("41.7, 41.7, 41.7, 61.6, 100.5", \ + "50.9, 50.9, 50.9, 70.9, 110.0", \ + "67.0, 67.0, 67.0, 87.3, 126.8", \ + "97.4, 97.4, 97.4, 117.9, 158.1", \ + "156.4, 156.4, 156.4, 177.1, 217.9"); + } + cell_fall (inslew_load_5x5__91) { + values ("63.1, 63.1, 63.1, 75.0, 95.5", \ + "76.0, 76.0, 76.0, 88.8, 110.8", \ + "96.6, 96.6, 96.6, 110.1, 134.3", \ + "133.2, 133.2, 133.2, 147.7, 173.9", \ + "203.2, 203.2, 203.2, 218.4, 247.0"); + } + fall_transition (inslew_load_5x5__91) { + values ("39.4, 39.4, 39.4, 48.7, 66.2", \ + "52.7, 52.7, 52.7, 62.2, 80.2", \ + "77.2, 77.2, 77.2, 87.2, 105.8", \ + "125.3, 125.3, 125.3, 135.3, 154.9", \ + "220.4, 220.4, 220.4, 230.7, 250.7"); + } + } + internal_power (energy_pos_z_a1) { + related_pin : "a1" ; + rise_power (energy_inslew_load_5x5__91) { + values ("187.5, 187.5, 187.5, 214.4, 268.1", \ + "226.0, 226.0, 226.0, 252.9, 306.6", \ + "302.3, 302.3, 302.3, 329.2, 382.9", \ + "454.5, 454.5, 454.5, 481.3, 535.1", \ + "758.2, 758.2, 758.2, 785.1, 838.8"); + } + fall_power (energy_inslew_load_5x5__91) { + values ("235.5, 235.5, 235.5, 262.3, 316.1", \ + "288.5, 288.5, 288.5, 315.4, 369.1", \ + "393.8, 393.8, 393.8, 420.7, 474.4", \ + "604.6, 604.6, 604.6, 631.4, 685.2", \ + "1024.3, 1024.3, 1024.3, 1051.2, 1105.0"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + rise_power (energy_inslew_load_5x5__91) { + values ("153.6, 153.6, 153.6, 180.5, 234.2", \ + "175.2, 175.2, 175.2, 202.0, 255.8", \ + "217.6, 217.6, 217.6, 244.4, 298.2", \ + "301.4, 301.4, 301.4, 328.3, 382.0", \ + "468.2, 468.2, 468.2, 495.1, 548.8"); + } + fall_power (energy_inslew_load_5x5__91) { + values ("184.8, 184.8, 184.8, 211.7, 265.4", \ + "239.9, 239.9, 239.9, 266.7, 320.5", \ + "347.5, 347.5, 347.5, 374.4, 428.1", \ + "561.5, 561.5, 561.5, 588.4, 642.1", \ + "988.3, 988.3, 988.3, 1015.2, 1069.0"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__91) { + values ("115.8, 115.8, 115.8, 142.7, 196.4", \ + "137.2, 137.2, 137.2, 164.1, 217.8", \ + "179.0, 179.0, 179.0, 205.8, 259.6", \ + "261.6, 261.6, 261.6, 288.5, 342.2", \ + "425.9, 425.9, 425.9, 452.8, 506.5"); + } + fall_power (energy_inslew_load_5x5__91) { + values ("146.0, 146.0, 146.0, 172.8, 226.6", \ + "189.2, 189.2, 189.2, 216.1, 269.8", \ + "273.6, 273.6, 273.6, 300.4, 354.2", \ + "441.1, 441.1, 441.1, 468.0, 521.7", \ + "775.4, 775.4, 775.4, 802.2, 856.0"); + } + } + } + } + + cell (or2v0x05) { + area : 0.0 ; + cell_leakage_power : 1.8 ; + leakage_power () { + when : "(!(b) & a)" ; + value : 0.22 ; + } + leakage_power () { + when : "b" ; + value : 0.45 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 4.9 ; + } + pin (b) { + direction : input ; + capacitance : 3.25 ; + } + pin (a) { + direction : input ; + capacitance : 3.15 ; + } + pin (z) { + function : "(a | b)" ; + direction : output ; + capacitance : 2.40 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__92) { + values ("60.2, 60.2, 60.2, 73.3, 96.6", \ + "71.8, 71.8, 71.8, 85.8, 110.6", \ + "89.2, 89.2, 89.2, 104.3, 131.3", \ + "118.9, 118.9, 118.9, 135.1, 164.7", \ + "174.7, 174.7, 174.7, 191.9, 224.0"); + } + rise_transition (inslew_load_5x5__92) { + values ("47.4, 47.4, 47.4, 69.5, 112.9", \ + "61.6, 61.6, 61.6, 84.0, 127.8", \ + "87.5, 87.5, 87.5, 110.2, 154.6", \ + "137.0, 137.0, 137.0, 160.0, 205.2", \ + "234.4, 234.4, 234.4, 257.5, 303.4"); + } + cell_fall (inslew_load_5x5__92) { + values ("70.7, 70.7, 70.7, 84.2, 107.4", \ + "70.9, 70.9, 70.9, 85.0, 109.3", \ + "69.5, 69.5, 69.5, 84.1, 110.3", \ + "64.0, 64.0, 64.0, 79.6, 107.6", \ + "49.6, 49.6, 49.6, 66.2, 96.7"); + } + fall_transition (inslew_load_5x5__92) { + values ("46.6, 46.6, 46.6, 57.0, 76.7", \ + "55.7, 55.7, 55.7, 66.3, 86.3", \ + "73.4, 73.4, 73.4, 84.3, 104.9", \ + "108.7, 108.7, 108.7, 119.9, 141.4", \ + "179.1, 179.1, 179.1, 190.5, 212.6"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__92) { + values ("48.1, 48.1, 48.1, 60.7, 83.2", \ + "51.2, 51.2, 51.2, 64.7, 88.5", \ + "51.6, 51.6, 51.6, 66.1, 91.8", \ + "46.9, 46.9, 46.9, 62.6, 90.8", \ + "33.2, 33.2, 33.2, 49.9, 80.7"); + } + rise_transition (inslew_load_5x5__92) { + values ("40.8, 40.8, 40.8, 62.8, 106.4", \ + "51.6, 51.6, 51.6, 73.9, 117.4", \ + "70.6, 70.6, 70.6, 93.1, 137.1", \ + "106.0, 106.0, 106.0, 128.8, 173.6", \ + "174.9, 174.9, 174.9, 198.1, 243.6"); + } + cell_fall (inslew_load_5x5__92) { + values ("59.8, 59.8, 59.8, 72.4, 93.9", \ + "69.0, 69.0, 69.0, 82.6, 105.9", \ + "83.0, 83.0, 83.0, 97.5, 123.3", \ + "106.6, 106.6, 106.6, 122.3, 150.4", \ + "150.8, 150.8, 150.8, 167.5, 198.3"); + } + fall_transition (inslew_load_5x5__92) { + values ("36.2, 36.2, 36.2, 46.4, 65.6", \ + "47.8, 47.8, 47.8, 58.3, 78.0", \ + "69.4, 69.4, 69.4, 80.3, 100.8", \ + "111.5, 111.5, 111.5, 122.6, 144.1", \ + "194.7, 194.7, 194.7, 206.2, 228.3"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__92) { + values ("169.2, 169.2, 169.2, 199.2, 259.1", \ + "216.9, 216.9, 216.9, 246.9, 306.9", \ + "311.1, 311.1, 311.1, 341.1, 401.0", \ + "498.4, 498.4, 498.4, 528.3, 588.3", \ + "872.1, 872.1, 872.1, 902.1, 962.1"); + } + fall_power (energy_inslew_load_5x5__92) { + values ("206.8, 206.8, 206.8, 236.8, 296.7", \ + "245.8, 245.8, 245.8, 275.8, 335.8", \ + "323.5, 323.5, 323.5, 353.5, 413.4", \ + "478.9, 478.9, 478.9, 508.9, 568.9", \ + "789.7, 789.7, 789.7, 819.7, 879.7"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__92) { + values ("128.9, 128.9, 128.9, 158.8, 218.8", \ + "158.0, 158.0, 158.0, 188.0, 247.9", \ + "215.0, 215.0, 215.0, 244.9, 304.9", \ + "327.8, 327.8, 327.8, 357.8, 417.8", \ + "552.8, 552.8, 552.8, 582.7, 642.7"); + } + fall_power (energy_inslew_load_5x5__92) { + values ("154.5, 154.5, 154.5, 184.4, 244.4", \ + "198.2, 198.2, 198.2, 228.1, 288.1", \ + "284.0, 284.0, 284.0, 314.0, 373.9", \ + "454.7, 454.7, 454.7, 484.7, 544.6", \ + "795.3, 795.3, 795.3, 825.3, 885.2"); + } + } + } + } + + cell (or2v0x1) { + area : 0.0 ; + cell_leakage_power : 0.82 ; + leakage_power () { + when : "(!(b) & a)" ; + value : 0.59 ; + } + leakage_power () { + when : "b" ; + value : 1.4 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 0.45 ; + } + pin (b) { + direction : input ; + capacitance : 3.61 ; + } + pin (a) { + direction : input ; + capacitance : 3.64 ; + } + pin (z) { + function : "(a | b)" ; + direction : output ; + capacitance : 2.79 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__93) { + values ("63.8, 63.8, 63.8, 74.5, 93.2", \ + "80.1, 80.1, 80.1, 91.5, 111.6", \ + "106.3, 106.3, 106.3, 118.4, 140.2", \ + "153.4, 153.4, 153.4, 166.2, 189.7", \ + "244.0, 244.0, 244.0, 257.3, 282.7"); + } + rise_transition (inslew_load_5x5__93) { + values ("42.0, 42.0, 42.0, 57.6, 88.1", \ + "57.1, 57.1, 57.1, 72.9, 103.7", \ + "84.7, 84.7, 84.7, 100.7, 132.0", \ + "137.9, 137.9, 137.9, 154.0, 185.8", \ + "242.9, 242.9, 242.9, 259.1, 291.3"); + } + cell_fall (inslew_load_5x5__93) { + values ("61.2, 61.2, 61.2, 72.0, 90.1", \ + "58.2, 58.2, 58.2, 69.1, 88.1", \ + "49.9, 49.9, 49.9, 61.2, 81.5", \ + "30.0, 30.0, 30.0, 42.1, 63.7", \ + "-13.2, -13.2, -13.2, -0.5, 23.1"); + } + fall_transition (inslew_load_5x5__93) { + values ("41.1, 41.1, 41.1, 48.7, 62.9", \ + "48.6, 48.6, 48.6, 56.4, 71.0", \ + "63.5, 63.5, 63.5, 71.4, 86.4", \ + "93.1, 93.1, 93.1, 101.2, 116.9", \ + "152.1, 152.1, 152.1, 160.4, 176.3"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__93) { + values ("50.4, 50.4, 50.4, 60.7, 78.7", \ + "57.2, 57.2, 57.2, 68.1, 87.3", \ + "64.5, 64.5, 64.5, 76.2, 97.0", \ + "73.9, 73.9, 73.9, 86.3, 108.9", \ + "88.5, 88.5, 88.5, 101.6, 126.0"); + } + rise_transition (inslew_load_5x5__93) { + values ("35.0, 35.0, 35.0, 50.5, 80.8", \ + "46.4, 46.4, 46.4, 62.1, 92.7", \ + "66.7, 66.7, 66.7, 82.5, 113.5", \ + "104.9, 104.9, 104.9, 121.0, 152.5", \ + "179.8, 179.8, 179.8, 196.0, 228.0"); + } + cell_fall (inslew_load_5x5__93) { + values ("52.1, 52.1, 52.1, 62.1, 79.0", \ + "57.4, 57.4, 57.4, 68.2, 86.4", \ + "63.9, 63.9, 63.9, 75.1, 95.2", \ + "72.1, 72.1, 72.1, 84.3, 106.0", \ + "85.8, 85.8, 85.8, 98.5, 122.5"); + } + fall_transition (inslew_load_5x5__93) { + values ("31.6, 31.6, 31.6, 39.1, 52.9", \ + "41.6, 41.6, 41.6, 49.3, 63.5", \ + "60.2, 60.2, 60.2, 68.2, 83.0", \ + "96.6, 96.6, 96.6, 104.7, 120.4", \ + "168.6, 168.6, 168.6, 176.8, 192.9"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__93) { + values ("213.9, 213.9, 213.9, 248.8, 318.6", \ + "279.2, 279.2, 279.2, 314.1, 383.9", \ + "407.5, 407.5, 407.5, 442.4, 512.2", \ + "662.0, 662.0, 662.0, 696.9, 766.7", \ + "1170.0, 1170.0, 1170.0, 1204.9, 1274.7"); + } + fall_power (energy_inslew_load_5x5__93) { + values ("247.1, 247.1, 247.1, 282.0, 351.8", \ + "288.3, 288.3, 288.3, 323.2, 393.0", \ + "370.2, 370.2, 370.2, 405.1, 474.9", \ + "534.4, 534.4, 534.4, 569.3, 639.1", \ + "862.3, 862.3, 862.3, 897.2, 967.0"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__93) { + values ("162.4, 162.4, 162.4, 197.3, 267.1", \ + "203.9, 203.9, 203.9, 238.8, 308.6", \ + "284.5, 284.5, 284.5, 319.4, 389.2", \ + "443.9, 443.9, 443.9, 478.8, 548.6", \ + "761.6, 761.6, 761.6, 796.5, 866.3"); + } + fall_power (energy_inslew_load_5x5__93) { + values ("184.1, 184.1, 184.1, 219.0, 288.8", \ + "232.3, 232.3, 232.3, 267.2, 337.0", \ + "326.6, 326.6, 326.6, 361.5, 431.3", \ + "513.8, 513.8, 513.8, 548.7, 618.5", \ + "887.4, 887.4, 887.4, 922.3, 992.1"); + } + } + } + } + + cell (or3v0x05) { + area : 0.0 ; + cell_leakage_power : 1.7 ; + leakage_power () { + when : "(!(c) & !(b) & a)" ; + value : 0.52 ; + } + leakage_power () { + when : "(b & c)" ; + value : 1.3 ; + } + leakage_power () { + when : "((a & (b ^ c)) | (b & !(c)))" ; + value : 0.57 ; + } + leakage_power () { + when : "(c & !(b) & !(a))" ; + value : 1.4 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 4.9 ; + } + pin (c) { + direction : input ; + capacitance : 4.08 ; + } + pin (b) { + direction : input ; + capacitance : 4.04 ; + } + pin (a) { + direction : input ; + capacitance : 4.10 ; + } + pin (z) { + function : "(a | b | c)" ; + direction : output ; + capacitance : 2.28 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__94) { + values ("76.4, 76.4, 76.4, 89.7, 112.9", \ + "94.7, 94.7, 94.7, 108.8, 133.7", \ + "123.4, 123.4, 123.4, 138.3, 165.2", \ + "174.1, 174.1, 174.1, 190.0, 219.1", \ + "270.8, 270.8, 270.8, 287.3, 318.7"); + } + rise_transition (inslew_load_5x5__94) { + values ("54.9, 54.9, 54.9, 76.2, 117.8", \ + "71.7, 71.7, 71.7, 93.2, 135.2", \ + "102.0, 102.0, 102.0, 123.8, 166.4", \ + "160.2, 160.2, 160.2, 182.3, 225.6", \ + "274.9, 274.9, 274.9, 297.1, 341.0"); + } + cell_fall (inslew_load_5x5__94) { + values ("124.3, 124.3, 124.3, 138.5, 164.0", \ + "120.2, 120.2, 120.2, 134.7, 160.8", \ + "111.1, 111.1, 111.1, 126.0, 152.9", \ + "93.7, 93.7, 93.7, 109.1, 137.4", \ + "57.4, 57.4, 57.4, 73.4, 103.4"); + } + fall_transition (inslew_load_5x5__94) { + values ("76.9, 76.9, 76.9, 87.5, 107.3", \ + "86.4, 86.4, 86.4, 97.0, 117.2", \ + "104.1, 104.1, 104.1, 114.8, 135.4", \ + "139.7, 139.7, 139.7, 150.5, 171.6", \ + "211.8, 211.8, 211.8, 222.9, 244.2"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__94) { + values ("67.3, 67.3, 67.3, 80.2, 102.9", \ + "76.8, 76.8, 76.8, 90.4, 114.5", \ + "87.9, 87.9, 87.9, 102.4, 128.2", \ + "102.4, 102.4, 102.4, 117.8, 145.9", \ + "125.3, 125.3, 125.3, 141.6, 171.9"); + } + rise_transition (inslew_load_5x5__94) { + values ("49.6, 49.6, 49.6, 70.8, 112.2", \ + "62.3, 62.3, 62.3, 83.7, 125.5", \ + "85.0, 85.0, 85.0, 106.6, 148.9", \ + "127.5, 127.5, 127.5, 149.5, 192.4", \ + "210.7, 210.7, 210.7, 232.7, 276.4"); + } + cell_fall (inslew_load_5x5__94) { + values ("104.0, 104.0, 104.0, 117.8, 142.1", \ + "109.1, 109.1, 109.1, 123.2, 148.5", \ + "115.8, 115.8, 115.8, 130.5, 156.9", \ + "126.4, 126.4, 126.4, 141.9, 170.1", \ + "144.9, 144.9, 144.9, 161.0, 191.2"); + } + fall_transition (inslew_load_5x5__94) { + values ("62.4, 62.4, 62.4, 72.7, 92.2", \ + "73.4, 73.4, 73.4, 84.0, 103.7", \ + "94.8, 94.8, 94.8, 105.4, 125.8", \ + "137.5, 137.5, 137.5, 148.3, 169.4", \ + "221.3, 221.3, 221.3, 232.3, 253.8"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__94) { + values ("54.6, 54.6, 54.6, 67.0, 88.8", \ + "58.1, 58.1, 58.1, 71.2, 94.3", \ + "57.5, 57.5, 57.5, 71.5, 96.3", \ + "49.2, 49.2, 49.2, 64.2, 91.3", \ + "26.6, 26.6, 26.6, 42.6, 72.0"); + } + rise_transition (inslew_load_5x5__94) { + values ("42.5, 42.5, 42.5, 63.6, 104.8", \ + "53.2, 53.2, 53.2, 74.4, 115.9", \ + "71.3, 71.3, 71.3, 92.8, 134.8", \ + "105.0, 105.0, 105.0, 126.8, 169.5", \ + "170.1, 170.1, 170.1, 192.2, 235.6"); + } + cell_fall (inslew_load_5x5__94) { + values ("75.4, 75.4, 75.4, 88.3, 110.4", \ + "85.5, 85.5, 85.5, 99.1, 122.7", \ + "103.6, 103.6, 103.6, 118.0, 143.7", \ + "135.6, 135.6, 135.6, 150.9, 178.7", \ + "194.1, 194.1, 194.1, 210.2, 240.3"); + } + fall_transition (inslew_load_5x5__94) { + values ("44.5, 44.5, 44.5, 54.5, 73.3", \ + "56.8, 56.8, 56.8, 67.0, 86.3", \ + "80.6, 80.6, 80.6, 91.3, 111.2", \ + "127.7, 127.7, 127.7, 138.4, 159.3", \ + "220.0, 220.0, 220.0, 231.1, 252.5"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__94) { + values ("228.8, 228.8, 228.8, 257.3, 314.3", \ + "289.8, 289.8, 289.8, 318.3, 375.3", \ + "409.6, 409.6, 409.6, 438.1, 495.2", \ + "647.8, 647.8, 647.8, 676.3, 733.4", \ + "1123.1, 1123.1, 1123.1, 1151.6, 1208.7"); + } + fall_power (energy_inslew_load_5x5__94) { + values ("328.5, 328.5, 328.5, 357.0, 414.1", \ + "368.2, 368.2, 368.2, 396.8, 453.8", \ + "446.0, 446.0, 446.0, 474.5, 531.6", \ + "601.9, 601.9, 601.9, 630.4, 687.5", \ + "915.1, 915.1, 915.1, 943.7, 1000.7"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__94) { + values ("189.5, 189.5, 189.5, 218.0, 275.0", \ + "228.3, 228.3, 228.3, 256.8, 313.9", \ + "304.1, 304.1, 304.1, 332.6, 389.7", \ + "454.1, 454.1, 454.1, 482.6, 539.6", \ + "752.7, 752.7, 752.7, 781.2, 838.2"); + } + fall_power (energy_inslew_load_5x5__94) { + values ("262.9, 262.9, 262.9, 291.4, 348.4", \ + "307.1, 307.1, 307.1, 335.6, 392.6", \ + "394.3, 394.3, 394.3, 422.8, 479.9", \ + "569.1, 569.1, 569.1, 597.6, 654.7", \ + "916.6, 916.6, 916.6, 945.1, 1002.2"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__94) { + values ("145.4, 145.4, 145.4, 173.9, 230.9", \ + "172.8, 172.8, 172.8, 201.3, 258.3", \ + "225.7, 225.7, 225.7, 254.3, 311.3", \ + "330.2, 330.2, 330.2, 358.7, 415.8", \ + "537.9, 537.9, 537.9, 566.4, 623.4"); + } + fall_power (energy_inslew_load_5x5__94) { + values ("183.7, 183.7, 183.7, 212.2, 269.2", \ + "229.7, 229.7, 229.7, 258.3, 315.3", \ + "321.4, 321.4, 321.4, 349.9, 407.0", \ + "504.0, 504.0, 504.0, 532.5, 589.6", \ + "867.4, 867.4, 867.4, 896.0, 953.0"); + } + } + } + } + + cell (or3v0x1) { + area : 0.0 ; + cell_leakage_power : 0.83 ; + leakage_power () { + when : "(!(c) & !(b) & a)" ; + value : 0.57 ; + } + leakage_power () { + when : "((a & (b ^ c)) | (b & !(c)))" ; + value : 0.62 ; + } + leakage_power () { + when : "(!((a & !(b))) & c)" ; + value : 1.5 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 0.67 ; + } + pin (c) { + direction : input ; + capacitance : 4.51 ; + } + pin (b) { + direction : input ; + capacitance : 4.26 ; + } + pin (a) { + direction : input ; + capacitance : 4.28 ; + } + pin (z) { + function : "(a | b | c)" ; + direction : output ; + capacitance : 2.65 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__95) { + values ("78.5, 78.5, 78.5, 88.7, 106.6", \ + "99.0, 99.0, 99.0, 109.7, 128.8", \ + "131.2, 131.2, 131.2, 142.4, 163.0", \ + "188.5, 188.5, 188.5, 200.3, 222.3", \ + "298.0, 298.0, 298.0, 310.1, 333.4"); + } + rise_transition (inslew_load_5x5__95) { + values ("47.6, 47.6, 47.6, 61.9, 89.5", \ + "63.7, 63.7, 63.7, 78.1, 106.1", \ + "92.8, 92.8, 92.8, 107.3, 135.7", \ + "148.7, 148.7, 148.7, 163.3, 192.2", \ + "258.7, 258.7, 258.7, 273.6, 302.7"); + } + cell_fall (inslew_load_5x5__95) { + values ("124.6, 124.6, 124.6, 135.4, 155.0", \ + "119.4, 119.4, 119.4, 130.4, 150.2", \ + "107.9, 107.9, 107.9, 119.1, 139.5", \ + "85.7, 85.7, 85.7, 97.3, 118.6", \ + "39.4, 39.4, 39.4, 51.3, 73.8"); + } + fall_transition (inslew_load_5x5__95) { + values ("74.9, 74.9, 74.9, 82.4, 96.9", \ + "83.2, 83.2, 83.2, 90.8, 105.4", \ + "98.8, 98.8, 98.8, 106.4, 121.2", \ + "130.2, 130.2, 130.2, 138.0, 153.0", \ + "194.4, 194.4, 194.4, 202.2, 217.5"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__95) { + values ("69.0, 69.0, 69.0, 79.0, 96.4", \ + "80.4, 80.4, 80.4, 90.9, 109.4", \ + "94.8, 94.8, 94.8, 105.8, 125.6", \ + "115.4, 115.4, 115.4, 127.0, 148.2", \ + "150.2, 150.2, 150.2, 162.2, 185.0"); + } + rise_transition (inslew_load_5x5__95) { + values ("42.6, 42.6, 42.6, 56.7, 84.3", \ + "54.7, 54.7, 54.7, 69.0, 96.9", \ + "76.4, 76.4, 76.4, 90.9, 119.1", \ + "117.6, 117.6, 117.6, 132.2, 160.9", \ + "198.0, 198.0, 198.0, 212.7, 241.7"); + } + cell_fall (inslew_load_5x5__95) { + values ("103.7, 103.7, 103.7, 114.1, 133.1", \ + "107.3, 107.3, 107.3, 118.0, 137.4", \ + "111.5, 111.5, 111.5, 122.6, 142.6", \ + "117.2, 117.2, 117.2, 128.7, 150.0", \ + "124.9, 124.9, 124.9, 136.8, 159.4"); + } + fall_transition (inslew_load_5x5__95) { + values ("60.1, 60.1, 60.1, 67.7, 81.7", \ + "70.1, 70.1, 70.1, 77.7, 92.0", \ + "89.6, 89.6, 89.6, 97.1, 111.9", \ + "128.0, 128.0, 128.0, 135.8, 150.8", \ + "205.2, 205.2, 205.2, 213.1, 228.4"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__95) { + values ("55.6, 55.6, 55.6, 65.2, 81.8", \ + "60.8, 60.8, 60.8, 70.9, 88.6", \ + "63.3, 63.3, 63.3, 74.0, 93.1", \ + "60.9, 60.9, 60.9, 72.2, 92.9", \ + "49.8, 49.8, 49.8, 61.7, 83.9"); + } + rise_transition (inslew_load_5x5__95) { + values ("35.6, 35.6, 35.6, 49.6, 77.0", \ + "45.7, 45.7, 45.7, 59.9, 87.5", \ + "63.3, 63.3, 63.3, 77.7, 105.7", \ + "96.1, 96.1, 96.1, 110.6, 139.1", \ + "159.7, 159.7, 159.7, 174.3, 203.2"); + } + cell_fall (inslew_load_5x5__95) { + values ("73.8, 73.8, 73.8, 84.0, 101.3", \ + "82.4, 82.4, 82.4, 92.8, 111.1", \ + "97.7, 97.7, 97.7, 108.5, 128.1", \ + "123.7, 123.7, 123.7, 135.1, 156.1", \ + "170.2, 170.2, 170.2, 182.1, 204.7"); + } + fall_transition (inslew_load_5x5__95) { + values ("42.1, 42.1, 42.1, 49.3, 62.9", \ + "53.1, 53.1, 53.1, 60.5, 74.4", \ + "75.1, 75.1, 75.1, 82.7, 97.1", \ + "118.5, 118.5, 118.5, 126.2, 141.2", \ + "203.9, 203.9, 203.9, 211.8, 227.1"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__95) { + values ("279.6, 279.6, 279.6, 312.7, 378.9", \ + "354.4, 354.4, 354.4, 387.5, 453.6", \ + "499.8, 499.8, 499.8, 532.9, 599.1", \ + "787.9, 787.9, 787.9, 821.0, 887.2", \ + "1362.2, 1362.2, 1362.2, 1395.3, 1461.4"); + } + fall_power (energy_inslew_load_5x5__95) { + values ("410.2, 410.2, 410.2, 443.2, 509.4", \ + "453.2, 453.2, 453.2, 486.2, 552.4", \ + "536.9, 536.9, 536.9, 570.0, 636.2", \ + "705.3, 705.3, 705.3, 738.4, 804.6", \ + "1044.8, 1044.8, 1044.8, 1077.9, 1144.1"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__95) { + values ("233.1, 233.1, 233.1, 266.2, 332.4", \ + "282.3, 282.3, 282.3, 315.4, 381.5", \ + "377.2, 377.2, 377.2, 410.3, 476.4", \ + "564.4, 564.4, 564.4, 597.5, 663.6", \ + "936.3, 936.3, 936.3, 969.4, 1035.6"); + } + fall_power (energy_inslew_load_5x5__95) { + values ("328.5, 328.5, 328.5, 361.6, 427.8", \ + "378.1, 378.1, 378.1, 411.1, 477.3", \ + "475.9, 475.9, 475.9, 509.0, 575.2", \ + "671.2, 671.2, 671.2, 704.3, 770.5", \ + "1062.5, 1062.5, 1062.5, 1095.5, 1161.7"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__95) { + values ("179.7, 179.7, 179.7, 212.7, 278.9", \ + "215.5, 215.5, 215.5, 248.5, 314.7", \ + "284.2, 284.2, 284.2, 317.3, 383.4", \ + "418.7, 418.7, 418.7, 451.8, 518.0", \ + "685.7, 685.7, 685.7, 718.8, 784.9"); + } + fall_power (energy_inslew_load_5x5__95) { + values ("228.9, 228.9, 228.9, 262.0, 328.1", \ + "281.4, 281.4, 281.4, 314.5, 380.6", \ + "386.3, 386.3, 386.3, 419.4, 485.6", \ + "595.2, 595.2, 595.2, 628.2, 694.4", \ + "1010.3, 1010.3, 1010.3, 1043.4, 1109.5"); + } + } + } + } + + cell (or3v0x2) { + area : 0.0 ; + cell_leakage_power : 1.6 ; + leakage_power () { + when : "(!(c) & !(b) & a)" ; + value : 0.98 ; + } + leakage_power () { + when : "((a & (b ^ c)) | (b & !(c)))" ; + value : 1.1 ; + } + leakage_power () { + when : "(!((a & !(b))) & c)" ; + value : 2.7 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 1.5 ; + } + pin (c) { + direction : input ; + capacitance : 5.78 ; + } + pin (b) { + direction : input ; + capacitance : 6.01 ; + } + pin (a) { + direction : input ; + capacitance : 6.72 ; + } + pin (z) { + function : "(a | b | c)" ; + direction : output ; + capacitance : 3.47 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__96) { + values ("83.3, 83.3, 83.3, 93.4, 111.2", \ + "111.0, 111.0, 111.0, 121.5, 140.5", \ + "156.2, 156.2, 156.2, 167.1, 187.4", \ + "239.0, 239.0, 239.0, 250.3, 271.7", \ + "399.3, 399.3, 399.3, 410.9, 433.5"); + } + rise_transition (inslew_load_5x5__96) { + values ("51.0, 51.0, 51.0, 64.8, 91.6", \ + "72.5, 72.5, 72.5, 86.4, 113.5", \ + "110.6, 110.6, 110.6, 124.6, 152.1", \ + "183.4, 183.4, 183.4, 197.5, 225.4", \ + "327.0, 327.0, 327.0, 341.1, 369.3"); + } + cell_fall (inslew_load_5x5__96) { + values ("90.8, 90.8, 90.8, 100.8, 118.1", \ + "81.1, 81.1, 81.1, 91.2, 108.9", \ + "61.7, 61.7, 61.7, 71.9, 90.3", \ + "21.6, 21.6, 21.6, 32.2, 51.7", \ + "-60.2, -60.2, -60.2, -49.9, -29.3"); + } + fall_transition (inslew_load_5x5__96) { + values ("58.2, 58.2, 58.2, 64.7, 77.1", \ + "64.0, 64.0, 64.0, 70.6, 83.1", \ + "75.2, 75.2, 75.2, 81.8, 94.4", \ + "98.6, 98.6, 98.6, 105.1, 117.9", \ + "145.9, 145.9, 145.9, 152.8, 165.8"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__96) { + values ("72.3, 72.3, 72.3, 82.2, 99.6", \ + "89.3, 89.3, 89.3, 99.6, 118.0", \ + "113.9, 113.9, 113.9, 124.7, 144.4", \ + "155.7, 155.7, 155.7, 166.8, 187.7", \ + "233.2, 233.2, 233.2, 244.7, 266.8"); + } + rise_transition (inslew_load_5x5__96) { + values ("44.5, 44.5, 44.5, 58.3, 84.9", \ + "60.9, 60.9, 60.9, 74.7, 101.7", \ + "89.5, 89.5, 89.5, 103.5, 130.8", \ + "143.7, 143.7, 143.7, 157.8, 185.5", \ + "249.9, 249.9, 249.9, 264.0, 292.1"); + } + cell_fall (inslew_load_5x5__96) { + values ("75.7, 75.7, 75.7, 85.2, 101.9", \ + "74.3, 74.3, 74.3, 84.1, 101.2", \ + "68.7, 68.7, 68.7, 78.9, 96.8", \ + "54.0, 54.0, 54.0, 64.6, 84.0", \ + "20.6, 20.6, 20.6, 31.0, 51.6"); + } + fall_transition (inslew_load_5x5__96) { + values ("46.0, 46.0, 46.0, 52.5, 64.4", \ + "53.5, 53.5, 53.5, 60.0, 72.1", \ + "68.4, 68.4, 68.4, 75.0, 87.5", \ + "97.5, 97.5, 97.5, 104.0, 116.8", \ + "155.5, 155.5, 155.5, 162.4, 175.4"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__96) { + values ("56.0, 56.0, 56.0, 65.5, 82.1", \ + "65.2, 65.2, 65.2, 75.2, 92.9", \ + "75.8, 75.8, 75.8, 86.3, 105.3", \ + "90.0, 90.0, 90.0, 100.9, 121.4", \ + "113.2, 113.2, 113.2, 124.6, 146.1"); + } + rise_transition (inslew_load_5x5__96) { + values ("35.2, 35.2, 35.2, 48.9, 75.4", \ + "48.6, 48.6, 48.6, 62.4, 89.1", \ + "71.7, 71.7, 71.7, 85.6, 112.7", \ + "114.7, 114.7, 114.7, 128.7, 156.2", \ + "198.1, 198.1, 198.1, 212.3, 240.2"); + } + cell_fall (inslew_load_5x5__96) { + values ("51.7, 51.7, 51.7, 60.6, 75.5", \ + "56.3, 56.3, 56.3, 65.4, 81.6", \ + "61.4, 61.4, 61.4, 71.4, 88.7", \ + "65.7, 65.7, 65.7, 76.2, 95.4", \ + "71.1, 71.1, 71.1, 81.4, 102.0"); + } + fall_transition (inslew_load_5x5__96) { + values ("30.8, 30.8, 30.8, 36.9, 48.3", \ + "40.0, 40.0, 40.0, 46.4, 58.0", \ + "57.6, 57.6, 57.6, 64.2, 76.5", \ + "91.5, 91.5, 91.5, 98.0, 110.7", \ + "158.0, 158.0, 158.0, 164.9, 177.9"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__96) { + values ("409.9, 409.9, 409.9, 453.3, 539.9", \ + "537.0, 537.0, 537.0, 580.3, 666.9", \ + "782.8, 782.8, 782.8, 826.1, 912.7", \ + "1269.1, 1269.1, 1269.1, 1312.4, 1399.1", \ + "2238.5, 2238.5, 2238.5, 2281.9, 2368.5"); + } + fall_power (energy_inslew_load_5x5__96) { + values ("522.4, 522.4, 522.4, 565.7, 652.4", \ + "571.6, 571.6, 571.6, 614.9, 701.5", \ + "668.7, 668.7, 668.7, 712.0, 798.7", \ + "865.6, 865.6, 865.6, 908.9, 995.6", \ + "1262.3, 1262.3, 1262.3, 1305.6, 1392.2"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__96) { + values ("334.1, 334.1, 334.1, 377.4, 464.1", \ + "419.4, 419.4, 419.4, 462.8, 549.4", \ + "583.9, 583.9, 583.9, 627.2, 713.9", \ + "908.1, 908.1, 908.1, 951.4, 1038.0", \ + "1553.5, 1553.5, 1553.5, 1596.8, 1683.5"); + } + fall_power (energy_inslew_load_5x5__96) { + values ("408.3, 408.3, 408.3, 451.7, 538.3", \ + "467.0, 467.0, 467.0, 510.3, 596.9", \ + "584.2, 584.2, 584.2, 627.5, 714.2", \ + "816.4, 816.4, 816.4, 859.7, 946.3", \ + "1281.5, 1281.5, 1281.5, 1324.9, 1411.5"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__96) { + values ("245.9, 245.9, 245.9, 289.2, 375.9", \ + "307.5, 307.5, 307.5, 350.8, 437.5", \ + "425.9, 425.9, 425.9, 469.2, 555.8", \ + "658.5, 658.5, 658.5, 701.8, 788.4", \ + "1120.8, 1120.8, 1120.8, 1164.1, 1250.8"); + } + fall_power (energy_inslew_load_5x5__96) { + values ("271.9, 271.9, 271.9, 315.2, 401.8", \ + "337.9, 337.9, 337.9, 381.2, 467.8", \ + "468.1, 468.1, 468.1, 511.4, 598.0", \ + "724.3, 724.3, 724.3, 767.6, 854.2", \ + "1234.8, 1234.8, 1234.8, 1278.2, 1364.8"); + } + } + } + } + + cell (or3v4x05) { + area : 0.0 ; + cell_leakage_power : 3.7 ; + leakage_power () { + when : "(c & b & a)" ; + value : 4.6 ; + } + leakage_power () { + when : "(!(c) & !(b) & a)" ; + value : 1.4 ; + } + leakage_power () { + when : "(c & b & !(a))" ; + value : 4.8 ; + } + leakage_power () { + when : "((a & (b ^ c)) | (b & !(c)))" ; + value : 1.6 ; + } + leakage_power () { + when : "(c & !(b) & !(a))" ; + value : 5.1 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 4.9 ; + } + pin (c) { + direction : input ; + capacitance : 2.30 ; + } + pin (b) { + direction : input ; + capacitance : 2.57 ; + } + pin (a) { + direction : input ; + capacitance : 2.50 ; + } + pin (z) { + function : "(a | b | c)" ; + direction : output ; + capacitance : 2.58 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__97) { + values ("54.5, 54.5, 54.5, 68.2, 92.6", \ + "57.4, 57.4, 57.4, 72.0, 97.6", \ + "56.4, 56.4, 56.4, 72.0, 99.4", \ + "47.4, 47.4, 47.4, 64.0, 94.0", \ + "23.6, 23.6, 23.6, 41.4, 74.1"); + } + rise_transition (inslew_load_5x5__97) { + values ("46.5, 46.5, 46.5, 70.2, 117.3", \ + "56.6, 56.6, 56.6, 80.6, 127.3", \ + "74.6, 74.6, 74.6, 98.8, 146.1", \ + "108.0, 108.0, 108.0, 132.6, 180.6", \ + "172.6, 172.6, 172.6, 197.5, 246.3"); + } + cell_fall (inslew_load_5x5__97) { + values ("184.4, 184.4, 184.4, 201.3, 231.6", \ + "204.7, 204.7, 204.7, 222.0, 253.5", \ + "240.5, 240.5, 240.5, 258.3, 291.2", \ + "310.7, 310.7, 310.7, 329.0, 363.6", \ + "452.3, 452.3, 452.3, 470.1, 506.2"); + } + fall_transition (inslew_load_5x5__97) { + values ("121.0, 121.0, 121.0, 133.0, 156.2", \ + "146.3, 146.3, 146.3, 158.4, 182.0", \ + "193.5, 193.5, 193.5, 205.9, 229.7", \ + "286.1, 286.1, 286.1, 298.6, 322.9", \ + "470.1, 470.1, 470.1, 483.0, 508.0"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__97) { + values ("50.0, 50.0, 50.0, 63.6, 87.7", \ + "47.6, 47.6, 47.6, 61.8, 86.8", \ + "34.4, 34.4, 34.4, 49.4, 75.9", \ + "-1.6, -1.6, -1.6, 14.5, 43.1", \ + "-83.3, -83.3, -83.3, -66.1, -34.9"); + } + rise_transition (inslew_load_5x5__97) { + values ("44.1, 44.1, 44.1, 67.7, 114.6", \ + "51.9, 51.9, 51.9, 75.8, 122.4", \ + "65.1, 65.1, 65.1, 89.1, 136.1", \ + "88.3, 88.3, 88.3, 112.6, 160.3", \ + "131.6, 131.6, 131.6, 156.3, 204.7"); + } + cell_fall (inslew_load_5x5__97) { + values ("159.0, 159.0, 159.0, 175.4, 205.0", \ + "188.2, 188.2, 188.2, 205.1, 235.8", \ + "237.4, 237.4, 237.4, 255.1, 287.4", \ + "330.5, 330.5, 330.5, 348.7, 383.1", \ + "514.9, 514.9, 514.9, 532.8, 568.8"); + } + fall_transition (inslew_load_5x5__97) { + values ("101.3, 101.3, 101.3, 113.3, 136.1", \ + "127.7, 127.7, 127.7, 139.7, 163.0", \ + "174.7, 174.7, 174.7, 187.0, 210.8", \ + "266.5, 266.5, 266.5, 279.0, 303.2", \ + "449.3, 449.3, 449.3, 462.2, 487.1"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__97) { + values ("45.0, 45.0, 45.0, 58.3, 82.1", \ + "39.6, 39.6, 39.6, 53.5, 78.1", \ + "20.3, 20.3, 20.3, 35.0, 60.9", \ + "-29.3, -29.3, -29.3, -13.6, 14.1", \ + "-139.9, -139.9, -139.9, -123.2, -93.1"); + } + rise_transition (inslew_load_5x5__97) { + values ("41.4, 41.4, 41.4, 64.9, 111.7", \ + "48.2, 48.2, 48.2, 72.0, 118.5", \ + "59.2, 59.2, 59.2, 83.2, 130.0", \ + "77.8, 77.8, 77.8, 102.0, 149.4", \ + "111.0, 111.0, 111.0, 135.5, 183.6"); + } + cell_fall (inslew_load_5x5__97) { + values ("128.8, 128.8, 128.8, 144.6, 172.9", \ + "161.6, 161.6, 161.6, 178.2, 207.9", \ + "219.8, 219.8, 219.8, 237.2, 268.9", \ + "329.4, 329.4, 329.4, 347.5, 381.4", \ + "541.9, 541.9, 541.9, 559.9, 595.7"); + } + fall_transition (inslew_load_5x5__97) { + values ("80.1, 80.1, 80.1, 92.0, 114.1", \ + "105.2, 105.2, 105.2, 117.1, 140.0", \ + "152.2, 152.2, 152.2, 164.4, 188.0", \ + "242.6, 242.6, 242.6, 255.0, 279.1", \ + "420.8, 420.8, 420.8, 433.7, 458.6"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__97) { + values ("150.3, 150.3, 150.3, 182.6, 247.0", \ + "177.0, 177.0, 177.0, 209.2, 273.7", \ + "229.1, 229.1, 229.1, 261.3, 325.8", \ + "331.9, 331.9, 331.9, 364.1, 428.6", \ + "536.4, 536.4, 536.4, 568.6, 633.0"); + } + fall_power (energy_inslew_load_5x5__97) { + values ("321.3, 321.3, 321.3, 353.6, 418.0", \ + "384.8, 384.8, 384.8, 417.1, 481.5", \ + "507.3, 507.3, 507.3, 539.5, 604.0", \ + "749.7, 749.7, 749.7, 781.9, 846.4", \ + "1233.4, 1233.4, 1233.4, 1265.6, 1330.1"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__97) { + values ("135.4, 135.4, 135.4, 167.7, 232.1", \ + "150.6, 150.6, 150.6, 182.8, 247.3", \ + "179.2, 179.2, 179.2, 211.5, 275.9", \ + "234.5, 234.5, 234.5, 266.7, 331.2", \ + "343.0, 343.0, 343.0, 375.2, 439.7"); + } + fall_power (energy_inslew_load_5x5__97) { + values ("273.0, 273.0, 273.0, 305.2, 369.7", \ + "335.9, 335.9, 335.9, 368.1, 432.6", \ + "454.3, 454.3, 454.3, 486.6, 551.0", \ + "688.2, 688.2, 688.2, 720.4, 784.9", \ + "1155.1, 1155.1, 1155.1, 1187.3, 1251.8"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__97) { + values ("120.8, 120.8, 120.8, 153.0, 217.4", \ + "131.4, 131.4, 131.4, 163.6, 228.0", \ + "150.8, 150.8, 150.8, 183.1, 247.5", \ + "187.4, 187.4, 187.4, 219.7, 284.1", \ + "257.9, 257.9, 257.9, 290.1, 354.6"); + } + fall_power (energy_inslew_load_5x5__97) { + values ("218.8, 218.8, 218.8, 251.0, 315.5", \ + "277.4, 277.4, 277.4, 309.6, 374.1", \ + "390.6, 390.6, 390.6, 422.8, 487.3", \ + "612.3, 612.3, 612.3, 644.5, 708.9", \ + "1052.7, 1052.7, 1052.7, 1085.0, 1149.4"); + } + } + } + } + + cell (or4v0x05) { + area : 0.0 ; + cell_leakage_power : 1.5 ; + leakage_power () { + when : "(!(d) & !(c) & !(b) & a)" ; + value : 0.49 ; + } + leakage_power () { + when : "((a & ((b & !(c) & !(d)) | (!(b) & (c ^ d)))) | (b & !(c) & !(d)))" ; + value : 0.51 ; + } + leakage_power () { + when : "((a & ((b & (c ^ d)) | (!(b) & c & d))) | (!(a) & ((b & (c ^ d)) | (c & !(d)))))" ; + value : 0.55 ; + } + leakage_power () { + when : "((!(a) & !((b & !(c))) & d) | (b & c & d))" ; + value : 1.3 ; + } + leakage_power () { + when : "(!(d) & !(c) & !(b) & !(a))" ; + value : 4.9 ; + } + pin (d) { + direction : input ; + capacitance : 4.42 ; + } + pin (c) { + direction : input ; + capacitance : 4.15 ; + } + pin (b) { + direction : input ; + capacitance : 4.10 ; + } + pin (a) { + direction : input ; + capacitance : 4.25 ; + } + pin (z) { + function : "(a | b | c | d)" ; + direction : output ; + capacitance : 2.58 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__97) { + values ("82.9, 82.9, 82.9, 97.7, 123.7", \ + "102.4, 102.4, 102.4, 118.1, 145.8", \ + "132.9, 132.9, 132.9, 149.5, 179.5", \ + "186.3, 186.3, 186.3, 204.0, 236.5", \ + "287.7, 287.7, 287.7, 306.2, 341.3"); + } + rise_transition (inslew_load_5x5__97) { + values ("60.1, 60.1, 60.1, 84.1, 131.0", \ + "77.2, 77.2, 77.2, 101.5, 148.8", \ + "108.2, 108.2, 108.2, 132.8, 180.8", \ + "167.6, 167.6, 167.6, 192.4, 241.3", \ + "284.4, 284.4, 284.4, 309.4, 359.0"); + } + cell_fall (inslew_load_5x5__97) { + values ("204.1, 204.1, 204.1, 221.0, 251.3", \ + "202.6, 202.6, 202.6, 219.7, 250.5", \ + "196.8, 196.8, 196.8, 214.2, 245.9", \ + "185.4, 185.4, 185.4, 203.2, 236.1", \ + "165.2, 165.2, 165.2, 183.5, 218.0"); + } + fall_transition (inslew_load_5x5__97) { + values ("117.5, 117.5, 117.5, 129.6, 152.8", \ + "129.2, 129.2, 129.2, 141.3, 164.7", \ + "151.3, 151.3, 151.3, 163.5, 187.2", \ + "193.7, 193.7, 193.7, 206.1, 230.0", \ + "278.2, 278.2, 278.2, 290.7, 315.0"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__97) { + values ("75.3, 75.3, 75.3, 89.8, 115.3", \ + "86.3, 86.3, 86.3, 101.6, 128.5", \ + "99.2, 99.2, 99.2, 115.4, 144.3", \ + "116.5, 116.5, 116.5, 133.8, 165.1", \ + "144.0, 144.0, 144.0, 162.2, 196.1"); + } + rise_transition (inslew_load_5x5__97) { + values ("55.7, 55.7, 55.7, 79.6, 126.3", \ + "68.7, 68.7, 68.7, 92.8, 139.9", \ + "91.9, 91.9, 91.9, 116.2, 164.0", \ + "135.4, 135.4, 135.4, 160.1, 208.6", \ + "220.3, 220.3, 220.3, 245.3, 294.5"); + } + cell_fall (inslew_load_5x5__97) { + values ("175.0, 175.0, 175.0, 191.4, 220.9", \ + "182.0, 182.0, 182.0, 198.8, 228.9", \ + "191.0, 191.0, 191.0, 208.2, 239.4", \ + "208.0, 208.0, 208.0, 225.8, 258.5", \ + "241.9, 241.9, 241.9, 260.1, 294.7"); + } + fall_transition (inslew_load_5x5__97) { + values ("99.3, 99.3, 99.3, 111.3, 134.0", \ + "113.1, 113.1, 113.1, 125.1, 148.2", \ + "138.0, 138.0, 138.0, 150.1, 173.6", \ + "186.7, 186.7, 186.7, 199.1, 223.0", \ + "284.5, 284.5, 284.5, 297.0, 321.4"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__97) { + values ("67.3, 67.3, 67.3, 81.5, 106.4", \ + "72.9, 72.9, 72.9, 87.8, 113.9", \ + "75.3, 75.3, 75.3, 91.1, 119.1", \ + "70.9, 70.9, 70.9, 87.7, 118.1", \ + "54.0, 54.0, 54.0, 71.9, 104.9"); + } + rise_transition (inslew_load_5x5__97) { + values ("51.1, 51.1, 51.1, 74.9, 121.5", \ + "61.9, 61.9, 61.9, 85.9, 132.9", \ + "80.8, 80.8, 80.8, 105.1, 152.6", \ + "115.6, 115.6, 115.6, 140.3, 188.4", \ + "182.9, 182.9, 182.9, 207.7, 256.7"); + } + cell_fall (inslew_load_5x5__97) { + values ("135.8, 135.8, 135.8, 151.5, 179.5", \ + "148.0, 148.0, 148.0, 164.2, 193.2", \ + "167.6, 167.6, 167.6, 184.4, 214.7", \ + "204.2, 204.2, 204.2, 221.8, 254.1", \ + "274.8, 274.8, 274.8, 293.0, 327.5"); + } + fall_transition (inslew_load_5x5__97) { + values ("76.7, 76.7, 76.7, 88.5, 110.7", \ + "91.4, 91.4, 91.4, 103.4, 125.9", \ + "117.9, 117.9, 117.9, 129.9, 153.1", \ + "170.6, 170.6, 170.6, 182.9, 206.7", \ + "276.1, 276.1, 276.1, 288.6, 312.9"); + } + } + timing (maxd_z_d_positive_unate) { + related_pin : "d" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__97) { + values ("54.1, 54.1, 54.1, 67.7, 91.8", \ + "55.2, 55.2, 55.2, 69.5, 94.7", \ + "49.2, 49.2, 49.2, 64.5, 91.4", \ + "29.3, 29.3, 29.3, 45.7, 75.1", \ + "-17.6, -17.6, -17.6, -0.1, 32.0"); + } + rise_transition (inslew_load_5x5__97) { + values ("43.9, 43.9, 43.9, 67.5, 114.4", \ + "53.4, 53.4, 53.4, 77.2, 123.9", \ + "69.5, 69.5, 69.5, 93.6, 140.8", \ + "98.7, 98.7, 98.7, 123.2, 171.1", \ + "154.7, 154.7, 154.7, 179.5, 228.2"); + } + cell_fall (inslew_load_5x5__97) { + values ("88.8, 88.8, 88.8, 103.4, 128.4", \ + "105.6, 105.6, 105.6, 121.0, 148.0", \ + "129.2, 129.2, 129.2, 145.4, 174.6", \ + "181.4, 181.4, 181.4, 198.7, 230.3", \ + "279.4, 279.4, 279.4, 297.5, 331.7"); + } + fall_transition (inslew_load_5x5__97) { + values ("50.7, 50.7, 50.7, 62.0, 83.2", \ + "66.9, 66.9, 66.9, 78.5, 100.3", \ + "93.2, 93.2, 93.2, 105.1, 127.7", \ + "148.6, 148.6, 148.6, 160.8, 184.4", \ + "257.5, 257.5, 257.5, 270.0, 294.3"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__97) { + values ("249.2, 249.2, 249.2, 281.5, 345.9", \ + "311.8, 311.8, 311.8, 344.0, 408.5", \ + "434.6, 434.6, 434.6, 466.8, 531.3", \ + "678.5, 678.5, 678.5, 710.8, 775.2", \ + "1165.1, 1165.1, 1165.1, 1197.3, 1261.7"); + } + fall_power (energy_inslew_load_5x5__97) { + values ("438.2, 438.2, 438.2, 470.5, 534.9", \ + "480.3, 480.3, 480.3, 512.5, 577.0", \ + "562.7, 562.7, 562.7, 594.9, 659.4", \ + "725.1, 725.1, 725.1, 757.3, 821.8", \ + "1049.4, 1049.4, 1049.4, 1081.6, 1146.1"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__97) { + values ("213.8, 213.8, 213.8, 246.0, 310.5", \ + "253.8, 253.8, 253.8, 286.0, 350.5", \ + "331.9, 331.9, 331.9, 364.1, 428.5", \ + "486.1, 486.1, 486.1, 518.4, 582.8", \ + "793.2, 793.2, 793.2, 825.5, 889.9"); + } + fall_power (energy_inslew_load_5x5__97) { + values ("370.0, 370.0, 370.0, 402.3, 466.7", \ + "417.7, 417.7, 417.7, 449.9, 514.4", \ + "509.5, 509.5, 509.5, 541.7, 606.2", \ + "691.6, 691.6, 691.6, 723.8, 788.2", \ + "1056.3, 1056.3, 1056.3, 1088.5, 1153.0"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__97) { + values ("182.4, 182.4, 182.4, 214.6, 279.0", \ + "211.0, 211.0, 211.0, 243.3, 307.7", \ + "266.4, 266.4, 266.4, 298.7, 363.1", \ + "375.3, 375.3, 375.3, 407.5, 472.0", \ + "591.5, 591.5, 591.5, 623.7, 688.1"); + } + fall_power (energy_inslew_load_5x5__97) { + values ("284.9, 284.9, 284.9, 317.2, 381.6", \ + "334.3, 334.3, 334.3, 366.5, 431.0", \ + "429.3, 429.3, 429.3, 461.5, 526.0", \ + "619.2, 619.2, 619.2, 651.4, 715.8", \ + "999.0, 999.0, 999.0, 1031.3, 1095.7"); + } + } + internal_power (energy_pos_z_d) { + related_pin : "d" ; + rise_power (energy_inslew_load_5x5__97) { + values ("139.5, 139.5, 139.5, 171.7, 236.2", \ + "161.5, 161.5, 161.5, 193.7, 258.2", \ + "203.8, 203.8, 203.8, 236.0, 300.4", \ + "286.5, 286.5, 286.5, 318.7, 383.2", \ + "450.5, 450.5, 450.5, 482.7, 547.2"); + } + fall_power (energy_inslew_load_5x5__97) { + values ("189.9, 189.9, 189.9, 222.1, 286.5", \ + "240.5, 240.5, 240.5, 272.8, 337.2", \ + "334.0, 334.0, 334.0, 366.3, 430.7", \ + "525.2, 525.2, 525.2, 557.4, 621.9", \ + "905.3, 905.3, 905.3, 937.6, 1002.0"); + } + } + } + } + + cell (or4v4x05) { + area : 0.0 ; + cell_leakage_power : 3.5 ; + leakage_power () { + when : "(d & c & b & a)" ; + value : 4.8 ; + } + leakage_power () { + when : "(!(d) & !(c) & !(b) & a)" ; + value : 1.3 ; + } + leakage_power () { + when : "(d & c & b & !(a))" ; + value : 5 ; + } + leakage_power () { + when : "((a & ((b & (c ^ d)) | (!(b) & c & d))) | (b & (c ^ d)))" ; + value : 1.6 ; + } + leakage_power () { + when : "((a & ((b & !(c) & !(d)) | (!(b) & (c ^ d)))) | (b & !(c) & !(d)))" ; + value : 1.4 ; + } + leakage_power () { + when : "(d & c & !(b) & !(a))" ; + value : 5.2 ; + } + leakage_power () { + when : "(!(d) & c & !(b) & !(a))" ; + value : 1.7 ; + } + leakage_power () { + when : "(d & !(c) & !(b) & !(a))" ; + value : 5.4 ; + } + leakage_power () { + when : "(!(d) & !(c) & !(b) & !(a))" ; + value : 4.9 ; + } + pin (d) { + direction : input ; + capacitance : 3.01 ; + } + pin (c) { + direction : input ; + capacitance : 2.68 ; + } + pin (b) { + direction : input ; + capacitance : 2.86 ; + } + pin (a) { + direction : input ; + capacitance : 2.97 ; + } + pin (z) { + function : "(a | b | c | d)" ; + direction : output ; + capacitance : 2.26 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__98) { + values ("57.2, 57.2, 57.2, 69.8, 91.8", \ + "62.7, 62.7, 62.7, 75.9, 99.2", \ + "67.0, 67.0, 67.0, 81.1, 106.1", \ + "69.2, 69.2, 69.2, 84.2, 111.5", \ + "68.0, 68.0, 68.0, 83.9, 113.5"); + } + rise_transition (inslew_load_5x5__98) { + values ("45.8, 45.8, 45.8, 66.7, 107.5", \ + "56.9, 56.9, 56.9, 78.0, 119.1", \ + "76.9, 76.9, 76.9, 98.2, 139.9", \ + "114.7, 114.7, 114.7, 136.3, 178.6", \ + "188.2, 188.2, 188.2, 210.0, 253.1"); + } + cell_fall (inslew_load_5x5__98) { + values ("247.7, 247.7, 247.7, 263.2, 291.7", \ + "270.1, 270.1, 270.1, 285.8, 315.0", \ + "308.6, 308.6, 308.6, 324.5, 354.7", \ + "384.2, 384.2, 384.2, 400.1, 431.3", \ + "536.3, 536.3, 536.3, 552.0, 583.5"); + } + fall_transition (inslew_load_5x5__98) { + values ("158.1, 158.1, 158.1, 168.9, 189.7", \ + "185.8, 185.8, 185.8, 196.7, 217.6", \ + "237.8, 237.8, 237.8, 248.7, 269.9", \ + "339.4, 339.4, 339.4, 350.5, 372.3", \ + "540.8, 540.8, 540.8, 552.2, 574.4"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__98) { + values ("53.3, 53.3, 53.3, 65.7, 87.5", \ + "54.1, 54.1, 54.1, 67.1, 90.0", \ + "48.2, 48.2, 48.2, 62.0, 86.4", \ + "28.1, 28.1, 28.1, 42.7, 69.2", \ + "-20.2, -20.2, -20.2, -4.6, 24.1"); + } + rise_transition (inslew_load_5x5__98) { + values ("43.6, 43.6, 43.6, 64.4, 105.2", \ + "52.7, 52.7, 52.7, 73.7, 114.8", \ + "68.6, 68.6, 68.6, 89.8, 131.3", \ + "97.6, 97.6, 97.6, 119.1, 161.2", \ + "153.0, 153.0, 153.0, 174.7, 217.5"); + } + cell_fall (inslew_load_5x5__98) { + values ("213.4, 213.4, 213.4, 228.6, 256.4", \ + "239.2, 239.2, 239.2, 254.7, 283.3", \ + "280.0, 280.0, 280.0, 295.8, 325.4", \ + "357.6, 357.6, 357.6, 373.6, 404.4", \ + "512.2, 512.2, 512.2, 527.8, 559.5"); + } + fall_transition (inslew_load_5x5__98) { + values ("134.0, 134.0, 134.0, 144.7, 165.4", \ + "160.4, 160.4, 160.4, 171.2, 192.0", \ + "206.9, 206.9, 206.9, 217.8, 238.9", \ + "296.7, 296.7, 296.7, 307.7, 329.3", \ + "475.1, 475.1, 475.1, 486.4, 508.4"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__98) { + values ("49.2, 49.2, 49.2, 61.5, 83.0", \ + "45.9, 45.9, 45.9, 58.6, 81.0", \ + "30.5, 30.5, 30.5, 43.9, 67.6", \ + "-11.2, -11.2, -11.2, 3.1, 28.5", \ + "-106.1, -106.1, -106.1, -91.0, -63.4"); + } + rise_transition (inslew_load_5x5__98) { + values ("41.4, 41.4, 41.4, 62.2, 102.9", \ + "48.8, 48.8, 48.8, 69.7, 110.7", \ + "61.0, 61.0, 61.0, 82.2, 123.5", \ + "82.1, 82.1, 82.1, 103.4, 145.3", \ + "120.6, 120.6, 120.6, 142.2, 184.7"); + } + cell_fall (inslew_load_5x5__98) { + values ("178.2, 178.2, 178.2, 193.1, 219.9", \ + "211.6, 211.6, 211.6, 226.9, 254.9", \ + "268.9, 268.9, 268.9, 284.6, 313.9", \ + "377.3, 377.3, 377.3, 393.4, 424.1", \ + "588.9, 588.9, 588.9, 604.5, 636.1"); + } + fall_transition (inslew_load_5x5__98) { + values ("111.0, 111.0, 111.0, 121.5, 142.0", \ + "139.4, 139.4, 139.4, 150.1, 170.8", \ + "190.0, 190.0, 190.0, 201.0, 221.9", \ + "287.8, 287.8, 287.8, 298.8, 320.3", \ + "481.5, 481.5, 481.5, 492.9, 514.9"); + } + } + timing (maxd_z_d_positive_unate) { + related_pin : "d" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__98) { + values ("43.8, 43.8, 43.8, 55.8, 77.0", \ + "38.2, 38.2, 38.2, 50.7, 72.7", \ + "18.1, 18.1, 18.1, 31.3, 54.5", \ + "-33.2, -33.2, -33.2, -19.2, 5.6", \ + "-147.9, -147.9, -147.9, -133.1, -106.2"); + } + rise_transition (inslew_load_5x5__98) { + values ("38.4, 38.4, 38.4, 59.2, 100.3", \ + "45.2, 45.2, 45.2, 66.1, 106.9", \ + "55.9, 55.9, 55.9, 77.0, 118.1", \ + "73.8, 73.8, 73.8, 95.1, 136.7", \ + "105.6, 105.6, 105.6, 127.1, 169.3"); + } + cell_fall (inslew_load_5x5__98) { + values ("135.4, 135.4, 135.4, 149.7, 175.3", \ + "172.5, 172.5, 172.5, 187.4, 214.3", \ + "231.1, 231.1, 231.1, 246.6, 275.2", \ + "348.4, 348.4, 348.4, 364.4, 394.8", \ + "578.4, 578.4, 578.4, 594.0, 625.7"); + } + fall_transition (inslew_load_5x5__98) { + values ("83.3, 83.3, 83.3, 93.8, 113.6", \ + "112.5, 112.5, 112.5, 123.0, 143.5", \ + "159.7, 159.7, 159.7, 170.5, 191.3", \ + "255.3, 255.3, 255.3, 266.2, 287.6", \ + "444.7, 444.7, 444.7, 456.1, 478.0"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__98) { + values ("160.2, 160.2, 160.2, 188.4, 244.8", \ + "192.3, 192.3, 192.3, 220.5, 276.9", \ + "255.3, 255.3, 255.3, 283.5, 339.9", \ + "380.0, 380.0, 380.0, 408.3, 464.7", \ + "628.5, 628.5, 628.5, 656.7, 713.2"); + } + fall_power (energy_inslew_load_5x5__98) { + values ("402.7, 402.7, 402.7, 430.9, 487.4", \ + "469.8, 469.8, 469.8, 498.0, 554.4", \ + "599.4, 599.4, 599.4, 627.6, 684.0", \ + "855.5, 855.5, 855.5, 883.7, 940.1", \ + "1365.5, 1365.5, 1365.5, 1393.7, 1450.1"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__98) { + values ("146.4, 146.4, 146.4, 174.6, 231.0", \ + "167.9, 167.9, 167.9, 196.1, 252.5", \ + "209.4, 209.4, 209.4, 237.6, 294.0", \ + "290.6, 290.6, 290.6, 318.8, 375.3", \ + "451.5, 451.5, 451.5, 479.7, 536.1"); + } + fall_power (energy_inslew_load_5x5__98) { + values ("344.5, 344.5, 344.5, 372.7, 429.1", \ + "405.7, 405.7, 405.7, 433.9, 490.3", \ + "519.5, 519.5, 519.5, 547.7, 604.1", \ + "742.8, 742.8, 742.8, 771.0, 827.4", \ + "1188.1, 1188.1, 1188.1, 1216.4, 1272.8"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__98) { + values ("132.9, 132.9, 132.9, 161.1, 217.6", \ + "145.9, 145.9, 145.9, 174.1, 230.5", \ + "170.1, 170.1, 170.1, 198.3, 254.7", \ + "216.1, 216.1, 216.1, 244.3, 300.7", \ + "305.6, 305.6, 305.6, 333.8, 390.2"); + } + fall_power (energy_inslew_load_5x5__98) { + values ("288.9, 288.9, 288.9, 317.1, 373.6", \ + "354.0, 354.0, 354.0, 382.2, 438.6", \ + "475.7, 475.7, 475.7, 503.9, 560.4", \ + "714.5, 714.5, 714.5, 742.7, 799.1", \ + "1190.0, 1190.0, 1190.0, 1218.2, 1274.6"); + } + } + internal_power (energy_pos_z_d) { + related_pin : "d" ; + rise_power (energy_inslew_load_5x5__98) { + values ("117.0, 117.0, 117.0, 145.2, 201.7", \ + "127.1, 127.1, 127.1, 155.3, 211.7", \ + "145.5, 145.5, 145.5, 173.7, 230.1", \ + "179.6, 179.6, 179.6, 207.8, 264.3", \ + "245.0, 245.0, 245.0, 273.3, 329.7"); + } + fall_power (energy_inslew_load_5x5__98) { + values ("222.3, 222.3, 222.3, 250.5, 306.9", \ + "286.1, 286.1, 286.1, 314.3, 370.7", \ + "398.8, 398.8, 398.8, 427.0, 483.4", \ + "625.8, 625.8, 625.8, 654.0, 710.4", \ + "1078.2, 1078.2, 1078.2, 1106.4, 1162.8"); + } + } + } + } + + cell (rowend_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + } + + cell (tie_x0) { + area : 0.0 ; + cell_leakage_power : 0 ; + } + + cell (vddtie) { + area : 0.0 ; + cell_leakage_power : 0 ; + pin (z) { + function : "1" ; + direction : output ; + capacitance : 3.81 ; + } + } + + cell (vfeed1) { + area : 0.0 ; + cell_leakage_power : 0 ; + } + + cell (vsstie) { + area : 0.0 ; + cell_leakage_power : 0 ; + pin (z) { + function : "0" ; + direction : output ; + capacitance : 4.07 ; + } + } + + cell (xaon21v0x05) { + area : 0.0 ; + cell_leakage_power : 2.5 ; + leakage_power () { + when : "(b & a2 & a1)" ; + value : 5.4 ; + } + leakage_power () { + when : "(!(b) & a2 & a1)" ; + value : 2.8 ; + } + leakage_power () { + when : "((a1 ^ a2) & !(b))" ; + value : 2.2 ; + } + leakage_power () { + when : "(!((a1 & a2)) & b)" ; + value : 1 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 1.2 ; + } + pin (b) { + direction : input ; + capacitance : 5.62 ; + } + pin (a2) { + direction : input ; + capacitance : 4.20 ; + } + pin (a1) { + direction : input ; + capacitance : 4.11 ; + } + pin (z) { + function : "((a1 & a2) ^ b)" ; + direction : output ; + capacitance : 3.98 ; + timing (maxd_z_a1_positive_unate) { + related_pin : "a1" ; + when : "(a2 & !(b))" ; + sdf_cond : "(a2 & !(b))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__99) { + values ("90.5, 90.5, 90.5, 114.9, 162.2", \ + "100.9, 100.9, 100.9, 125.8, 173.7", \ + "116.7, 116.7, 116.7, 141.9, 190.9", \ + "145.0, 145.0, 145.0, 170.5, 221.1", \ + "196.0, 196.0, 196.0, 223.4, 276.0"); + } + rise_transition (inslew_load_5x5__99) { + values ("100.0, 100.0, 100.0, 142.6, 229.2", \ + "118.4, 118.4, 118.4, 161.2, 247.3", \ + "153.2, 153.2, 153.2, 195.6, 280.5", \ + "222.8, 222.8, 222.8, 263.4, 349.0", \ + "357.5, 357.5, 357.5, 399.8, 483.7"); + } + cell_fall (inslew_load_5x5__99) { + values ("44.7, 44.7, 44.7, 59.0, 83.7", \ + "43.5, 43.5, 43.5, 59.4, 86.2", \ + "35.2, 35.2, 35.2, 53.9, 84.6", \ + "11.0, 11.0, 11.0, 34.6, 72.0", \ + "-47.5, -47.5, -47.5, -16.8, 31.5"); + } + fall_transition (inslew_load_5x5__99) { + values ("31.5, 31.5, 31.5, 46.6, 76.2", \ + "34.4, 34.4, 34.4, 49.9, 79.6", \ + "39.3, 39.3, 39.3, 55.7, 86.3", \ + "47.3, 47.3, 47.3, 65.3, 98.0", \ + "59.9, 59.9, 59.9, 80.8, 117.3"); + } + } + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + when : "(a1 & !(b))" ; + sdf_cond : "(a1 & !(b))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__99) { + values ("101.7, 101.7, 101.7, 126.3, 173.7", \ + "119.4, 119.4, 119.4, 144.5, 192.7", \ + "147.7, 147.7, 147.7, 173.0, 222.3", \ + "198.4, 198.4, 198.4, 224.6, 275.6", \ + "292.8, 292.8, 292.8, 320.4, 373.5"); + } + rise_transition (inslew_load_5x5__99) { + values ("104.8, 104.8, 104.8, 147.3, 233.9", \ + "126.5, 126.5, 126.5, 169.3, 255.0", \ + "166.6, 166.6, 166.6, 208.0, 293.5", \ + "245.3, 245.3, 245.3, 286.6, 371.0", \ + "398.2, 398.2, 398.2, 440.5, 524.4"); + } + cell_fall (inslew_load_5x5__99) { + values ("46.0, 46.0, 46.0, 60.4, 85.4", \ + "42.8, 42.8, 42.8, 58.6, 85.3", \ + "29.8, 29.8, 29.8, 47.9, 77.7", \ + "-4.2, -4.2, -4.2, 18.0, 53.2", \ + "-82.3, -82.3, -82.3, -54.1, -9.5"); + } + fall_transition (inslew_load_5x5__99) { + values ("31.9, 31.9, 31.9, 47.0, 76.5", \ + "34.3, 34.3, 34.3, 49.7, 79.4", \ + "38.2, 38.2, 38.2, 54.4, 84.8", \ + "44.8, 44.8, 44.8, 62.4, 94.4", \ + "55.4, 55.4, 55.4, 75.4, 110.6"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + when : "(!(a1) | !(a2))" ; + sdf_cond : "(!(a1) | !(a2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__99) { + values ("43.0, 43.0, 43.0, 58.0, 89.3", \ + "46.7, 46.7, 46.7, 62.7, 95.3", \ + "48.1, 48.1, 48.1, 65.6, 99.4", \ + "47.5, 47.5, 47.5, 66.7, 100.3", \ + "43.2, 43.2, 43.2, 63.9, 102.5"); + } + rise_transition (inslew_load_5x5__99) { + values ("41.1, 41.1, 41.1, 65.9, 121.8", \ + "52.6, 52.6, 52.6, 78.6, 135.0", \ + "70.6, 70.6, 70.6, 97.6, 153.9", \ + "105.3, 105.3, 105.3, 133.0, 185.2", \ + "173.5, 173.5, 173.5, 201.9, 257.8"); + } + cell_fall (inslew_load_5x5__99) { + values ("64.3, 64.3, 64.3, 79.7, 106.3", \ + "73.1, 73.1, 73.1, 89.5, 117.9", \ + "85.1, 85.1, 85.1, 102.8, 133.7", \ + "104.2, 104.2, 104.2, 123.0, 157.2", \ + "138.7, 138.7, 138.7, 158.8, 195.6"); + } + fall_transition (inslew_load_5x5__99) { + values ("42.1, 42.1, 42.1, 57.6, 87.5", \ + "52.5, 52.5, 52.5, 68.2, 98.5", \ + "71.9, 71.9, 71.9, 87.9, 118.8", \ + "109.7, 109.7, 109.7, 126.1, 157.8", \ + "184.3, 184.3, 184.3, 201.0, 233.7"); + } + } + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + when : "(a2 & b)" ; + sdf_cond : "(a2 & b)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__99) { + values ("56.9, 56.9, 56.9, 73.0, 104.8", \ + "56.1, 56.1, 56.1, 73.0, 106.0", \ + "51.3, 51.3, 51.3, 69.5, 104.5", \ + "36.7, 36.7, 36.7, 56.7, 94.9", \ + "2.7, 2.7, 2.7, 24.3, 65.9"); + } + rise_transition (inslew_load_5x5__99) { + values ("109.4, 109.4, 109.4, 137.5, 194.4", \ + "132.1, 132.1, 132.1, 159.5, 215.0", \ + "175.7, 175.7, 175.7, 203.3, 259.4", \ + "263.0, 263.0, 263.0, 290.9, 346.4", \ + "436.0, 436.0, 436.0, 464.4, 520.8"); + } + cell_fall (inslew_load_5x5__99) { + values ("61.0, 61.0, 61.0, 73.3, 98.2", \ + "63.2, 63.2, 63.2, 76.1, 102.0", \ + "63.8, 63.8, 63.8, 78.0, 105.7", \ + "59.9, 59.9, 59.9, 75.7, 106.2", \ + "47.0, 47.0, 47.0, 64.2, 97.7"); + } + fall_transition (inslew_load_5x5__99) { + values ("95.4, 95.4, 95.4, 114.8, 153.8", \ + "113.5, 113.5, 113.5, 132.6, 170.9", \ + "149.0, 149.0, 149.0, 168.1, 206.4", \ + "219.5, 219.5, 219.5, 238.8, 277.0", \ + "359.6, 359.6, 359.6, 379.0, 417.8"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + when : "(a1 & b)" ; + sdf_cond : "(a1 & b)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__99) { + values ("52.7, 52.7, 52.7, 68.8, 100.7", \ + "48.9, 48.9, 48.9, 66.0, 99.1", \ + "37.5, 37.5, 37.5, 56.3, 92.0", \ + "8.7, 8.7, 8.7, 29.8, 69.6", \ + "-55.2, -55.2, -55.2, -31.9, 12.5"); + } + rise_transition (inslew_load_5x5__99) { + values ("102.2, 102.2, 102.2, 130.3, 187.1", \ + "120.1, 120.1, 120.1, 148.1, 203.4", \ + "155.6, 155.6, 155.6, 183.4, 238.5", \ + "225.3, 225.3, 225.3, 253.6, 309.5", \ + "362.5, 362.5, 362.5, 391.6, 448.9"); + } + cell_fall (inslew_load_5x5__99) { + values ("61.5, 61.5, 61.5, 74.1, 99.4", \ + "69.4, 69.4, 69.4, 83.2, 110.1", \ + "79.3, 79.3, 79.3, 94.8, 124.5", \ + "92.5, 92.5, 92.5, 109.9, 143.3", \ + "113.2, 113.2, 113.2, 132.2, 169.0"); + } + fall_transition (inslew_load_5x5__99) { + values ("88.0, 88.0, 88.0, 107.4, 146.5", \ + "109.2, 109.2, 109.2, 128.5, 167.2", \ + "149.8, 149.8, 149.8, 169.3, 207.9", \ + "229.0, 229.0, 229.0, 248.8, 288.1", \ + "385.6, 385.6, 385.6, 405.7, 445.8"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + when : "(a1 & a2)" ; + sdf_cond : "(a1 & a2)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__99) { + values ("73.0, 73.0, 73.0, 96.1, 142.0", \ + "75.0, 75.0, 75.0, 98.5, 144.9", \ + "77.4, 77.4, 77.4, 101.4, 148.8", \ + "81.4, 81.4, 81.4, 106.1, 154.5", \ + "87.7, 87.7, 87.7, 113.1, 163.2"); + } + rise_transition (inslew_load_5x5__99) { + values ("145.4, 145.4, 145.4, 187.2, 271.4", \ + "178.2, 178.2, 178.2, 219.6, 303.2", \ + "242.2, 242.2, 242.2, 283.0, 365.3", \ + "371.2, 371.2, 371.2, 411.3, 492.0", \ + "625.8, 625.8, 625.8, 670.1, 749.8"); + } + cell_fall (inslew_load_5x5__99) { + values ("22.5, 22.5, 22.5, 36.0, 62.7", \ + "28.6, 28.6, 28.6, 44.1, 70.7", \ + "38.8, 38.8, 38.8, 56.2, 88.1", \ + "56.8, 56.8, 56.8, 75.8, 111.3", \ + "91.2, 91.2, 91.2, 111.1, 149.3"); + } + fall_transition (inslew_load_5x5__99) { + values ("41.6, 41.6, 41.6, 59.7, 98.3", \ + "64.0, 64.0, 64.0, 82.8, 118.1", \ + "107.1, 107.1, 107.1, 126.6, 165.0", \ + "192.1, 192.1, 192.1, 212.1, 251.6", \ + "361.2, 361.2, 361.2, 381.5, 421.8"); + } + } + internal_power (energy_pos_z_a1) { + related_pin : "a1" ; + when : "(a2 & !(b))" ; + rise_power (energy_inslew_load_5x5__99) { + values ("278.1, 278.1, 278.1, 327.9, 427.5", \ + "334.1, 334.1, 334.1, 383.9, 483.4", \ + "445.2, 445.2, 445.2, 495.0, 594.5", \ + "666.4, 666.4, 666.4, 716.2, 815.8", \ + "1108.2, 1108.2, 1108.2, 1158.0, 1257.5"); + } + fall_power (energy_inslew_load_5x5__99) { + values ("235.0, 235.0, 235.0, 284.8, 384.3", \ + "283.4, 283.4, 283.4, 333.2, 432.8", \ + "380.3, 380.3, 380.3, 430.1, 529.6", \ + "574.0, 574.0, 574.0, 623.8, 723.4", \ + "961.5, 961.5, 961.5, 1011.3, 1110.8"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + when : "(a1 & !(b))" ; + rise_power (energy_inslew_load_5x5__99) { + values ("296.2, 296.2, 296.2, 346.0, 445.5", \ + "357.3, 357.3, 357.3, 407.1, 506.6", \ + "477.5, 477.5, 477.5, 527.2, 626.8", \ + "715.9, 715.9, 715.9, 765.7, 865.3", \ + "1191.7, 1191.7, 1191.7, 1241.5, 1341.0"); + } + fall_power (energy_inslew_load_5x5__99) { + values ("242.3, 242.3, 242.3, 292.1, 391.6", \ + "277.5, 277.5, 277.5, 327.3, 426.8", \ + "347.9, 347.9, 347.9, 397.7, 497.3", \ + "488.8, 488.8, 488.8, 538.6, 638.1", \ + "770.5, 770.5, 770.5, 820.3, 919.9"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + when : "(!(a1) | !(a2))" ; + rise_power (energy_inslew_load_5x5__99) { + values ("198.4, 198.4, 198.4, 248.2, 347.8", \ + "247.0, 247.0, 247.0, 296.7, 396.3", \ + "342.7, 342.7, 342.7, 392.5, 492.1", \ + "533.4, 533.4, 533.4, 583.1, 682.7", \ + "914.0, 914.0, 914.0, 963.7, 1063.3"); + } + fall_power (energy_inslew_load_5x5__99) { + values ("271.8, 271.8, 271.8, 321.6, 421.1", \ + "338.3, 338.3, 338.3, 388.1, 487.6", \ + "469.6, 469.6, 469.6, 519.4, 618.9", \ + "731.1, 731.1, 731.1, 780.9, 880.4", \ + "1253.4, 1253.4, 1253.4, 1303.1, 1402.7"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + when : "(a2 & b)" ; + rise_power (energy_inslew_load_5x5__99) { + values ("281.4, 281.4, 281.4, 331.1, 430.7", \ + "329.8, 329.8, 329.8, 379.6, 479.1", \ + "426.7, 426.7, 426.7, 476.5, 576.0", \ + "620.4, 620.4, 620.4, 670.2, 769.7", \ + "1007.9, 1007.9, 1007.9, 1057.7, 1157.2"); + } + fall_power (energy_inslew_load_5x5__99) { + values ("263.0, 263.0, 263.0, 312.8, 412.4", \ + "302.5, 302.5, 302.5, 352.3, 451.9", \ + "381.5, 381.5, 381.5, 431.3, 530.8", \ + "539.4, 539.4, 539.4, 589.2, 688.8", \ + "855.3, 855.3, 855.3, 905.1, 1004.7"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + when : "(a1 & b)" ; + rise_power (energy_inslew_load_5x5__99) { + values ("257.1, 257.1, 257.1, 306.9, 406.4", \ + "292.3, 292.3, 292.3, 342.1, 441.6", \ + "362.7, 362.7, 362.7, 412.5, 512.1", \ + "503.6, 503.6, 503.6, 553.4, 652.9", \ + "785.3, 785.3, 785.3, 835.1, 934.7"); + } + fall_power (energy_inslew_load_5x5__99) { + values ("240.3, 240.3, 240.3, 290.1, 389.7", \ + "281.9, 281.9, 281.9, 331.7, 431.3", \ + "365.1, 365.1, 365.1, 414.9, 514.4", \ + "531.5, 531.5, 531.5, 581.2, 680.8", \ + "864.2, 864.2, 864.2, 913.9, 1013.5"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + when : "(a1 & a2)" ; + rise_power (energy_inslew_load_5x5__99) { + values ("168.2, 168.2, 168.2, 217.9, 317.5", \ + "201.8, 201.8, 201.8, 251.6, 351.1", \ + "269.1, 269.1, 269.1, 318.8, 418.4", \ + "403.6, 403.6, 403.6, 453.4, 552.9", \ + "672.7, 672.7, 672.7, 722.5, 822.0"); + } + fall_power (energy_inslew_load_5x5__99) { + values ("98.4, 98.4, 98.4, 148.1, 247.7", \ + "137.8, 137.8, 137.8, 187.6, 287.1", \ + "216.7, 216.7, 216.7, 266.4, 366.0", \ + "374.4, 374.4, 374.4, 424.2, 523.7", \ + "689.9, 689.9, 689.9, 739.7, 839.2"); + } + } + } + } + + cell (xnr2v0x1) { + area : 0.0 ; + cell_leakage_power : 5.8e+03 ; + leakage_power () { + when : "(a & b)" ; + value : 1.4 ; + } + leakage_power () { + when : "(a & !(b))" ; + value : 1.1e+04 ; + } + leakage_power () { + when : "(!(a) & b)" ; + value : 6.7e+03 ; + } + pin (b) { + direction : input ; + capacitance : 5.50 ; + } + pin (a) { + direction : input ; + capacitance : 3.34 ; + } + pin (z) { + direction : inout ; + capacitance : 19.46 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__100) { + values ("62.9, 62.9, 62.9, 144.4, 306.6", \ + "59.4, 59.4, 59.4, 141.8, 303.9", \ + "48.2, 48.2, 48.2, 132.4, 294.9", \ + "20.7, 20.7, 20.7, 109.7, 273.6", \ + "-41.6, -41.6, -41.6, 58.4, 227.9"); + } + rise_transition (inslew_load_5x5__100) { + values ("72.5, 72.5, 72.5, 216.4, 507.1", \ + "73.9, 73.9, 73.9, 216.8, 507.1", \ + "77.2, 77.2, 77.2, 217.9, 507.3", \ + "82.8, 82.8, 82.8, 222.2, 508.3", \ + "93.6, 93.6, 93.6, 233.9, 514.1"); + } + cell_fall (inslew_load_5x5__100) { + values ("165.9, 165.9, 165.9, 235.3, 355.8", \ + "175.2, 175.2, 175.2, 246.3, 369.0", \ + "188.2, 188.2, 188.2, 262.2, 388.7", \ + "204.7, 204.7, 204.7, 282.8, 416.2", \ + "227.8, 227.8, 227.8, 310.5, 454.3"); + } + fall_transition (inslew_load_5x5__100) { + values ("87.4, 87.4, 87.4, 165.2, 322.3", \ + "99.4, 99.4, 99.4, 177.4, 333.8", \ + "122.4, 122.4, 122.4, 201.1, 356.7", \ + "167.9, 167.9, 167.9, 247.5, 402.5", \ + "257.5, 257.5, 257.5, 338.3, 494.7"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__100) { + values ("54.3, 54.3, 54.3, 138.6, 302.5", \ + "59.9, 59.9, 59.9, 145.7, 309.5", \ + "64.7, 64.7, 64.7, 153.2, 317.9", \ + "67.9, 67.9, 67.9, 160.4, 328.1", \ + "69.9, 69.9, 69.9, 167.6, 341.7"); + } + rise_transition (inslew_load_5x5__100) { + values ("47.0, 47.0, 47.0, 193.7, 493.2", \ + "60.8, 60.8, 60.8, 206.0, 504.6", \ + "84.4, 84.4, 84.4, 228.0, 524.0", \ + "127.5, 127.5, 127.5, 270.8, 561.4", \ + "210.6, 210.6, 210.6, 353.5, 640.0"); + } + cell_fall (inslew_load_5x5__100) { + values ("155.0, 155.0, 155.0, 219.8, 336.1", \ + "149.4, 149.4, 149.4, 214.2, 330.6", \ + "133.0, 133.0, 133.0, 197.8, 314.3", \ + "92.7, 92.7, 92.7, 157.7, 274.3", \ + "3.5, 3.5, 3.5, 68.7, 185.4"); + } + fall_transition (inslew_load_5x5__100) { + values ("62.1, 62.1, 62.1, 140.0, 300.0", \ + "62.4, 62.4, 62.4, 140.2, 300.2", \ + "62.7, 62.7, 62.7, 140.6, 300.5", \ + "63.4, 63.4, 63.4, 141.2, 301.0", \ + "64.5, 64.5, 64.5, 142.3, 301.9"); + } + } + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__100) { + values ("67.0, 67.0, 67.0, 152.4, 322.4", \ + "69.7, 69.7, 69.7, 157.5, 328.0", \ + "71.1, 71.1, 71.1, 164.1, 337.9", \ + "68.3, 68.3, 68.3, 169.6, 352.3", \ + "57.0, 57.0, 57.0, 167.4, 366.7"); + } + rise_transition (inslew_load_5x5__100) { + values ("123.6, 123.6, 123.6, 278.2, 591.3", \ + "148.6, 148.6, 148.6, 299.5, 610.4", \ + "196.8, 196.8, 196.8, 346.6, 650.3", \ + "293.1, 293.1, 293.1, 442.8, 742.0", \ + "483.9, 483.9, 483.9, 635.9, 935.2"); + } + cell_fall (inslew_load_5x5__100) { + values ("144.7, 144.7, 144.7, 209.5, 325.9", \ + "141.5, 141.5, 141.5, 206.4, 322.9", \ + "132.0, 132.0, 132.0, 197.2, 314.0", \ + "106.7, 106.7, 106.7, 172.4, 289.6", \ + "47.6, 47.6, 47.6, 114.3, 232.4"); + } + fall_transition (inslew_load_5x5__100) { + values ("62.3, 62.3, 62.3, 140.1, 300.1", \ + "63.0, 63.0, 63.0, 140.8, 300.7", \ + "64.6, 64.6, 64.6, 142.4, 302.0", \ + "67.4, 67.4, 67.4, 145.3, 304.4", \ + "72.8, 72.8, 72.8, 150.3, 308.9"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__100) { + values ("73.3, 73.3, 73.3, 154.7, 316.9", \ + "67.6, 67.6, 67.6, 149.2, 311.4", \ + "51.0, 51.0, 51.0, 133.1, 295.2", \ + "10.5, 10.5, 10.5, 93.3, 255.5", \ + "-80.2, -80.2, -80.2, 4.0, 166.4"); + } + rise_transition (inslew_load_5x5__100) { + values ("72.2, 72.2, 72.2, 216.4, 507.1", \ + "72.7, 72.7, 72.7, 216.4, 507.1", \ + "73.4, 73.4, 73.4, 216.6, 507.1", \ + "74.7, 74.7, 74.7, 217.0, 507.1", \ + "76.9, 76.9, 76.9, 217.8, 507.2"); + } + cell_fall (inslew_load_5x5__100) { + values ("124.2, 124.2, 124.2, 186.1, 301.0", \ + "137.1, 137.1, 137.1, 200.7, 316.3", \ + "151.0, 151.0, 151.0, 216.9, 334.2", \ + "167.6, 167.6, 167.6, 237.2, 358.0", \ + "189.3, 189.3, 189.3, 264.1, 391.6"); + } + fall_transition (inslew_load_5x5__100) { + values ("49.2, 49.2, 49.2, 127.3, 289.6", \ + "56.4, 56.4, 56.4, 134.3, 295.3", \ + "68.2, 68.2, 68.2, 146.0, 305.0", \ + "89.3, 89.3, 89.3, 167.1, 324.1", \ + "129.0, 129.0, 129.0, 207.8, 363.4"); + } + } + timing (maxd_z_z_clear_negative_unate) { + related_pin : "z" ; + timing_sense : negative_unate ; + timing_type : clear ; + cell_fall (inslew_load_5x5__100) { + values ("71.6, 71.6, 71.6, 133.9, 248.9", \ + "91.4, 91.4, 91.4, 158.9, 277.4", \ + "117.6, 117.6, 117.6, 191.8, 318.5", \ + "156.1, 156.1, 156.1, 237.1, 376.7", \ + "224.2, 224.2, 224.2, 310.5, 465.0"); + } + fall_transition (inslew_load_5x5__100) { + values ("50.7, 50.7, 50.7, 128.8, 290.8", \ + "75.9, 75.9, 75.9, 153.6, 311.8", \ + "123.9, 123.9, 123.9, 202.6, 358.3", \ + "218.2, 218.2, 218.2, 298.6, 454.0", \ + "405.4, 405.4, 405.4, 487.3, 646.2"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__100) { + values ("238.9, 238.9, 238.9, 482.2, 968.7", \ + "270.9, 270.9, 270.9, 514.2, 1000.7", \ + "334.9, 334.9, 334.9, 578.2, 1064.7", \ + "462.9, 462.9, 462.9, 706.2, 1192.7", \ + "718.9, 718.9, 718.9, 962.2, 1448.7"); + } + fall_power (energy_inslew_load_5x5__100) { + values ("578.6, 578.6, 578.6, 821.8, 1308.3", \ + "647.4, 647.4, 647.4, 890.6, 1377.1", \ + "783.2, 783.2, 783.2, 1026.5, 1513.0", \ + "1054.8, 1054.8, 1054.8, 1298.1, 1784.6", \ + "1596.3, 1596.3, 1596.3, 1839.6, 2326.1"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__100) { + values ("207.4, 207.4, 207.4, 450.6, 937.1", \ + "253.7, 253.7, 253.7, 496.9, 983.4", \ + "344.7, 344.7, 344.7, 588.0, 1074.5", \ + "525.1, 525.1, 525.1, 768.4, 1254.9", \ + "885.0, 885.0, 885.0, 1128.3, 1614.8"); + } + fall_power (energy_inslew_load_5x5__100) { + values ("608.1, 608.1, 608.1, 851.3, 1337.8", \ + "653.1, 653.1, 653.1, 896.3, 1382.8", \ + "742.8, 742.8, 742.8, 986.0, 1472.5", \ + "922.1, 922.1, 922.1, 1165.3, 1651.8", \ + "1280.3, 1280.3, 1280.3, 1523.5, 2010.0"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__100) { + values ("270.3, 270.3, 270.3, 513.6, 1000.1", \ + "314.8, 314.8, 314.8, 558.1, 1044.6", \ + "403.9, 403.9, 403.9, 647.1, 1133.6", \ + "581.9, 581.9, 581.9, 825.1, 1311.6", \ + "938.0, 938.0, 938.0, 1181.2, 1667.7"); + } + fall_power (energy_inslew_load_5x5__100) { + values ("497.5, 497.5, 497.5, 740.8, 1227.3", \ + "530.9, 530.9, 530.9, 774.1, 1260.6", \ + "598.1, 598.1, 598.1, 841.3, 1327.8", \ + "731.5, 731.5, 731.5, 974.8, 1461.3", \ + "998.0, 998.0, 998.0, 1241.3, 1727.8"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__100) { + values ("349.8, 349.8, 349.8, 593.1, 1079.6", \ + "394.3, 394.3, 394.3, 637.6, 1124.1", \ + "483.3, 483.3, 483.3, 726.6, 1213.1", \ + "661.4, 661.4, 661.4, 904.6, 1391.1", \ + "1017.4, 1017.4, 1017.4, 1260.7, 1747.2"); + } + fall_power (energy_inslew_load_5x5__100) { + values ("441.2, 441.2, 441.2, 684.4, 1170.9", \ + "500.9, 500.9, 500.9, 744.1, 1230.6", \ + "614.8, 614.8, 614.8, 858.1, 1344.6", \ + "837.2, 837.2, 837.2, 1080.4, 1566.9", \ + "1277.8, 1277.8, 1277.8, 1521.1, 2007.6"); + } + } + internal_power (energy_neg_z_z) { + related_pin : "z" ; + fall_power (energy_inslew_load_5x5__100) { + values ("236.7, 236.7, 236.7, 480.0, 966.5", \ + "285.3, 285.3, 285.3, 528.6, 1015.1", \ + "382.5, 382.5, 382.5, 625.7, 1112.2", \ + "576.9, 576.9, 576.9, 820.1, 1306.6", \ + "965.6, 965.6, 965.6, 1208.9, 1695.4"); + } + } + } + } + + cell (xnr2v8x05) { + area : 0.0 ; + cell_leakage_power : 11 ; + leakage_power () { + when : "(b & a)" ; + value : 16 ; + } + leakage_power () { + when : "(a ^ b)" ; + value : 9.7 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 6.6 ; + } + pin (b) { + direction : input ; + capacitance : 5.54 ; + } + pin (a) { + direction : input ; + capacitance : 2.75 ; + } + pin (z) { + function : "!((a ^ b))" ; + direction : output ; + capacitance : 1.78 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + when : "b" ; + sdf_cond : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__101) { + values ("81.4, 81.4, 81.4, 92.7, 112.9", \ + "86.4, 86.4, 86.4, 98.0, 118.7", \ + "88.8, 88.8, 88.8, 100.7, 122.4", \ + "84.3, 84.3, 84.3, 96.7, 119.5", \ + "65.0, 65.0, 65.0, 77.9, 102.1"); + } + rise_transition (inslew_load_5x5__101) { + values ("64.8, 64.8, 64.8, 81.7, 114.7", \ + "74.3, 74.3, 74.3, 91.2, 124.3", \ + "92.4, 92.4, 92.4, 109.5, 142.9", \ + "127.1, 127.1, 127.1, 144.3, 178.0", \ + "194.4, 194.4, 194.4, 211.6, 245.7"); + } + cell_fall (inslew_load_5x5__101) { + values ("95.2, 95.2, 95.2, 106.3, 126.3", \ + "97.5, 97.5, 97.5, 108.8, 129.3", \ + "97.7, 97.7, 97.7, 109.4, 130.5", \ + "91.4, 91.4, 91.4, 103.6, 125.9", \ + "71.1, 71.1, 71.1, 83.7, 107.4"); + } + fall_transition (inslew_load_5x5__101) { + values ("61.2, 61.2, 61.2, 69.5, 84.9", \ + "69.7, 69.7, 69.7, 78.0, 93.7", \ + "86.6, 86.6, 86.6, 94.9, 110.9", \ + "120.0, 120.0, 120.0, 128.4, 144.8", \ + "186.0, 186.0, 186.0, 194.6, 211.3"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + when : "a" ; + sdf_cond : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__101) { + values ("44.2, 44.2, 44.2, 54.5, 72.6", \ + "46.3, 46.3, 46.3, 57.1, 76.1", \ + "44.8, 44.8, 44.8, 56.3, 76.7", \ + "36.0, 36.0, 36.0, 48.0, 70.1", \ + "13.9, 13.9, 13.9, 26.6, 50.3"); + } + rise_transition (inslew_load_5x5__101) { + values ("40.8, 40.8, 40.8, 57.4, 89.8", \ + "50.8, 50.8, 50.8, 67.5, 100.2", \ + "68.9, 68.9, 68.9, 85.8, 118.8", \ + "103.0, 103.0, 103.0, 120.1, 153.7", \ + "169.8, 169.8, 169.8, 187.0, 221.1"); + } + cell_fall (inslew_load_5x5__101) { + values ("59.3, 59.3, 59.3, 69.8, 87.7", \ + "68.7, 68.7, 68.7, 79.7, 98.9", \ + "87.4, 87.4, 87.4, 98.9, 119.7", \ + "118.7, 118.7, 118.7, 131.0, 153.5", \ + "178.3, 178.3, 178.3, 191.0, 215.3"); + } + fall_transition (inslew_load_5x5__101) { + values ("39.8, 39.8, 39.8, 47.7, 62.5", \ + "52.2, 52.2, 52.2, 60.3, 75.6", \ + "78.3, 78.3, 78.3, 86.6, 102.5", \ + "128.4, 128.4, 128.4, 136.9, 153.3", \ + "227.9, 227.9, 227.9, 236.5, 253.4"); + } + } + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + when : "!(b)" ; + sdf_cond : "!(b)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__101) { + values ("128.4, 128.4, 128.4, 139.7, 160.0", \ + "138.9, 138.9, 138.9, 150.5, 171.1", \ + "152.2, 152.2, 152.2, 163.9, 185.1", \ + "169.5, 169.5, 169.5, 181.6, 203.7", \ + "195.8, 195.8, 195.8, 208.3, 231.5"); + } + rise_transition (inslew_load_5x5__101) { + values ("66.3, 66.3, 66.3, 83.2, 116.2", \ + "72.3, 72.3, 72.3, 89.3, 122.4", \ + "83.6, 83.6, 83.6, 100.6, 133.9", \ + "105.0, 105.0, 105.0, 122.1, 155.6", \ + "146.5, 146.5, 146.5, 163.6, 197.6"); + } + cell_fall (inslew_load_5x5__101) { + values ("122.1, 122.1, 122.1, 133.0, 152.0", \ + "127.6, 127.6, 127.6, 138.6, 157.9", \ + "130.8, 130.8, 130.8, 141.8, 161.7", \ + "128.4, 128.4, 128.4, 139.7, 160.2", \ + "114.5, 114.5, 114.5, 126.3, 147.5"); + } + fall_transition (inslew_load_5x5__101) { + values ("50.1, 50.1, 50.1, 58.2, 73.4", \ + "53.2, 53.2, 53.2, 61.3, 76.6", \ + "59.1, 59.1, 59.1, 67.3, 82.7", \ + "69.7, 69.7, 69.7, 77.9, 93.6", \ + "90.6, 90.6, 90.6, 98.8, 115.0"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + when : "!(a)" ; + sdf_cond : "!(a)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__101) { + values ("82.0, 82.0, 82.0, 92.6, 111.2", \ + "90.1, 90.1, 90.1, 101.0, 120.1", \ + "100.4, 100.4, 100.4, 111.7, 131.7", \ + "115.9, 115.9, 115.9, 127.7, 149.0", \ + "141.2, 141.2, 141.2, 153.6, 176.3"); + } + rise_transition (inslew_load_5x5__101) { + values ("45.6, 45.6, 45.6, 62.2, 94.8", \ + "51.9, 51.9, 51.9, 68.6, 101.3", \ + "63.4, 63.4, 63.4, 80.2, 113.1", \ + "84.9, 84.9, 84.9, 101.9, 135.2", \ + "126.9, 126.9, 126.9, 144.0, 177.8"); + } + cell_fall (inslew_load_5x5__101) { + values ("72.7, 72.7, 72.7, 82.5, 99.4", \ + "79.1, 79.1, 79.1, 89.4, 107.0", \ + "85.6, 85.6, 85.6, 96.4, 115.1", \ + "92.1, 92.1, 92.1, 103.3, 123.4", \ + "101.0, 101.0, 101.0, 112.8, 134.2"); + } + fall_transition (inslew_load_5x5__101) { + values ("31.5, 31.5, 31.5, 39.2, 53.7", \ + "37.4, 37.4, 37.4, 45.2, 60.0", \ + "47.0, 47.0, 47.0, 54.9, 70.0", \ + "62.9, 62.9, 62.9, 71.2, 86.6", \ + "94.0, 94.0, 94.0, 102.3, 118.5"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + when : "b" ; + rise_power (energy_inslew_load_5x5__101) { + values ("253.2, 253.2, 253.2, 275.4, 319.9", \ + "284.2, 284.2, 284.2, 306.5, 350.9", \ + "345.9, 345.9, 345.9, 368.1, 412.6", \ + "467.9, 467.9, 467.9, 490.2, 534.6", \ + "710.3, 710.3, 710.3, 732.6, 777.0"); + } + fall_power (energy_inslew_load_5x5__101) { + values ("302.4, 302.4, 302.4, 324.6, 369.1", \ + "342.8, 342.8, 342.8, 365.1, 409.5", \ + "423.6, 423.6, 423.6, 445.8, 490.2", \ + "584.8, 584.8, 584.8, 607.0, 651.4", \ + "906.2, 906.2, 906.2, 928.5, 972.9"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + when : "a" ; + rise_power (energy_inslew_load_5x5__101) { + values ("125.8, 125.8, 125.8, 148.1, 192.5", \ + "152.5, 152.5, 152.5, 174.7, 219.2", \ + "204.7, 204.7, 204.7, 226.9, 271.4", \ + "308.1, 308.1, 308.1, 330.3, 374.8", \ + "514.2, 514.2, 514.2, 536.4, 580.9"); + } + fall_power (energy_inslew_load_5x5__101) { + values ("156.5, 156.5, 156.5, 178.8, 223.2", \ + "202.1, 202.1, 202.1, 224.3, 268.8", \ + "295.1, 295.1, 295.1, 317.4, 361.8", \ + "478.8, 478.8, 478.8, 501.0, 545.5", \ + "845.5, 845.5, 845.5, 867.7, 912.2"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + when : "!(b)" ; + rise_power (energy_inslew_load_5x5__101) { + values ("374.0, 374.0, 374.0, 396.2, 440.7", \ + "422.7, 422.7, 422.7, 445.0, 489.4", \ + "518.0, 518.0, 518.0, 540.2, 584.7", \ + "706.5, 706.5, 706.5, 728.7, 773.2", \ + "1081.6, 1081.6, 1081.6, 1103.8, 1148.3"); + } + fall_power (energy_inslew_load_5x5__101) { + values ("368.9, 368.9, 368.9, 391.1, 435.6", \ + "405.4, 405.4, 405.4, 427.6, 472.1", \ + "476.7, 476.7, 476.7, 498.9, 543.3", \ + "616.2, 616.2, 616.2, 638.4, 682.9", \ + "893.4, 893.4, 893.4, 915.6, 960.1"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + when : "!(a)" ; + rise_power (energy_inslew_load_5x5__101) { + values ("218.2, 218.2, 218.2, 240.4, 284.9", \ + "263.8, 263.8, 263.8, 286.0, 330.4", \ + "353.3, 353.3, 353.3, 375.5, 419.9", \ + "530.8, 530.8, 530.8, 553.1, 597.5", \ + "885.1, 885.1, 885.1, 907.3, 951.7"); + } + fall_power (energy_inslew_load_5x5__101) { + values ("210.2, 210.2, 210.2, 232.4, 276.9", \ + "249.8, 249.8, 249.8, 272.0, 316.4", \ + "325.1, 325.1, 325.1, 347.4, 391.8", \ + "471.1, 471.1, 471.1, 493.3, 537.7", \ + "761.4, 761.4, 761.4, 783.6, 828.1"); + } + } + } + } + + cell (xnr3v1x05) { + area : 0.0 ; + cell_leakage_power : 1.9 ; + leakage_power () { + when : "(c & b & a)" ; + value : 2.5 ; + } + leakage_power () { + when : "(a & (b ^ c))" ; + value : 1.7 ; + } + leakage_power () { + when : "(!(c) & !(b) & a)" ; + value : 2.1 ; + } + leakage_power () { + when : "(c & b & !(a))" ; + value : 2.4 ; + } + leakage_power () { + when : "(!(c) & b & !(a))" ; + value : 2.8 ; + } + leakage_power () { + when : "(c & !(b) & !(a))" ; + value : 1.2 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 0.4 ; + } + pin (c) { + direction : input ; + capacitance : 4.62 ; + } + pin (b) { + direction : input ; + capacitance : 5.61 ; + } + pin (a) { + direction : input ; + capacitance : 3.70 ; + } + pin (z) { + function : "(a ^ b ^ !(c))" ; + direction : output ; + capacitance : 3.77 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + when : "(b ^ c)" ; + sdf_cond : "(b ^ c)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__102) { + values ("171.3, 171.3, 171.3, 197.6, 248.4", \ + "174.3, 174.3, 174.3, 200.7, 251.5", \ + "171.9, 171.9, 171.9, 198.2, 249.2", \ + "155.6, 155.6, 155.6, 182.0, 233.1", \ + "109.3, 109.3, 109.3, 136.1, 187.3"); + } + rise_transition (inslew_load_5x5__102) { + values ("93.5, 93.5, 93.5, 138.8, 231.3", \ + "94.6, 94.6, 94.6, 139.8, 232.3", \ + "96.4, 96.4, 96.4, 141.6, 234.0", \ + "99.5, 99.5, 99.5, 144.5, 236.7", \ + "104.9, 104.9, 104.9, 150.1, 242.2"); + } + cell_fall (inslew_load_5x5__102) { + values ("141.7, 141.7, 141.7, 161.2, 194.9", \ + "150.5, 150.5, 150.5, 170.3, 204.3", \ + "160.4, 160.4, 160.4, 180.7, 215.5", \ + "171.4, 171.4, 171.4, 192.8, 228.9", \ + "183.5, 183.5, 183.5, 206.8, 245.2"); + } + fall_transition (inslew_load_5x5__102) { + values ("40.0, 40.0, 40.0, 61.1, 102.5", \ + "40.5, 40.5, 40.5, 61.6, 103.2", \ + "41.5, 41.5, 41.5, 62.7, 104.1", \ + "43.1, 43.1, 43.1, 64.6, 106.1", \ + "46.0, 46.0, 46.0, 68.1, 110.0"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + when : "(a ^ c)" ; + sdf_cond : "(a ^ c)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__102) { + values ("182.4, 182.4, 182.4, 209.2, 260.6", \ + "189.7, 189.7, 189.7, 216.6, 268.2", \ + "198.0, 198.0, 198.0, 225.1, 277.0", \ + "209.5, 209.5, 209.5, 236.8, 289.2", \ + "228.0, 228.0, 228.0, 254.8, 308.1"); + } + rise_transition (inslew_load_5x5__102) { + values ("107.3, 107.3, 107.3, 152.5, 244.6", \ + "111.6, 111.6, 111.6, 157.1, 249.0", \ + "119.4, 119.4, 119.4, 164.8, 256.1", \ + "134.1, 134.1, 134.1, 179.5, 270.2", \ + "162.6, 162.6, 162.6, 205.5, 296.2"); + } + cell_fall (inslew_load_5x5__102) { + values ("134.0, 134.0, 134.0, 153.3, 186.9", \ + "143.7, 143.7, 143.7, 163.4, 197.4", \ + "155.9, 155.9, 155.9, 176.3, 211.1", \ + "172.5, 172.5, 172.5, 194.1, 230.4", \ + "197.6, 197.6, 197.6, 221.3, 260.4"); + } + fall_transition (inslew_load_5x5__102) { + values ("39.9, 39.9, 39.9, 60.9, 102.4", \ + "40.5, 40.5, 40.5, 61.6, 103.1", \ + "41.5, 41.5, 41.5, 62.8, 104.1", \ + "43.4, 43.4, 43.4, 65.0, 106.5", \ + "46.7, 46.7, 46.7, 69.0, 111.0"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + when : "(a ^ b)" ; + sdf_cond : "(a ^ b)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__102) { + values ("51.5, 51.5, 51.5, 70.6, 109.7", \ + "56.4, 56.4, 56.4, 76.1, 116.2", \ + "59.8, 59.8, 59.8, 81.3, 122.7", \ + "62.0, 62.0, 62.0, 85.6, 126.7", \ + "62.7, 62.7, 62.7, 88.3, 135.7"); + } + rise_transition (inslew_load_5x5__102) { + values ("48.6, 48.6, 48.6, 80.4, 150.4", \ + "59.9, 59.9, 59.9, 92.1, 162.0", \ + "78.2, 78.2, 78.2, 111.3, 180.8", \ + "112.9, 112.9, 112.9, 146.9, 210.9", \ + "180.9, 180.9, 180.9, 215.8, 284.4"); + } + cell_fall (inslew_load_5x5__102) { + values ("78.8, 78.8, 78.8, 98.7, 133.6", \ + "88.4, 88.4, 88.4, 109.4, 145.9", \ + "101.2, 101.2, 101.2, 123.4, 162.7", \ + "120.2, 120.2, 120.2, 144.2, 187.0", \ + "153.3, 153.3, 153.3, 178.4, 225.3"); + } + fall_transition (inslew_load_5x5__102) { + values ("54.3, 54.3, 54.3, 75.6, 117.6", \ + "65.4, 65.4, 65.4, 86.9, 129.0", \ + "85.9, 85.9, 85.9, 107.9, 150.4", \ + "125.7, 125.7, 125.7, 148.0, 191.4", \ + "203.8, 203.8, 203.8, 226.6, 270.9"); + } + } + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + when : "!((b ^ c))" ; + sdf_cond : "!((b ^ c))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__102) { + values ("177.4, 177.4, 177.4, 204.4, 256.2", \ + "183.2, 183.2, 183.2, 210.3, 262.4", \ + "189.8, 189.8, 189.8, 217.2, 269.6", \ + "195.4, 195.4, 195.4, 222.3, 275.6", \ + "197.0, 197.0, 197.0, 225.2, 279.5"); + } + rise_transition (inslew_load_5x5__102) { + values ("114.7, 114.7, 114.7, 160.2, 251.9", \ + "121.9, 121.9, 121.9, 167.3, 258.5", \ + "135.8, 135.8, 135.8, 181.2, 271.8", \ + "163.2, 163.2, 163.2, 206.1, 296.8", \ + "216.1, 216.1, 216.1, 259.8, 349.7"); + } + cell_fall (inslew_load_5x5__102) { + values ("136.2, 136.2, 136.2, 149.6, 175.5", \ + "138.8, 138.8, 138.8, 152.4, 178.4", \ + "135.6, 135.6, 135.6, 149.3, 175.6", \ + "118.2, 118.2, 118.2, 132.2, 158.9", \ + "69.6, 69.6, 69.6, 84.0, 111.4"); + } + fall_transition (inslew_load_5x5__102) { + values ("77.8, 77.8, 77.8, 94.8, 128.9", \ + "79.0, 79.0, 79.0, 95.9, 130.0", \ + "80.8, 80.8, 80.8, 97.8, 131.8", \ + "83.9, 83.9, 83.9, 100.9, 134.9", \ + "88.9, 88.9, 88.9, 105.9, 139.7"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + when : "!((a ^ c))" ; + sdf_cond : "!((a ^ c))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__102) { + values ("126.4, 126.4, 126.4, 152.8, 203.6", \ + "143.3, 143.3, 143.3, 170.1, 221.6", \ + "170.5, 170.5, 170.5, 197.8, 250.2", \ + "218.8, 218.8, 218.8, 245.8, 299.4", \ + "308.2, 308.2, 308.2, 337.5, 391.9"); + } + rise_transition (inslew_load_5x5__102) { + values ("95.0, 95.0, 95.0, 140.2, 232.7", \ + "107.8, 107.8, 107.8, 152.9, 245.0", \ + "128.8, 128.8, 128.8, 174.2, 265.1", \ + "170.2, 170.2, 170.2, 213.1, 303.7", \ + "250.0, 250.0, 250.0, 294.7, 381.9"); + } + cell_fall (inslew_load_5x5__102) { + values ("141.7, 141.7, 141.7, 156.2, 183.9", \ + "147.0, 147.0, 147.0, 162.0, 190.3", \ + "151.9, 151.9, 151.9, 167.4, 196.8", \ + "156.8, 156.8, 156.8, 173.3, 204.2", \ + "162.1, 162.1, 162.1, 180.1, 213.6"); + } + fall_transition (inslew_load_5x5__102) { + values ("91.4, 91.4, 91.4, 108.5, 142.3", \ + "96.3, 96.3, 96.3, 113.5, 147.3", \ + "104.6, 104.6, 104.6, 121.9, 155.8", \ + "120.3, 120.3, 120.3, 137.7, 171.9", \ + "150.6, 150.6, 150.6, 168.4, 203.2"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + when : "!((a ^ b))" ; + sdf_cond : "!((a ^ b))" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__102) { + values ("81.2, 81.2, 81.2, 106.1, 155.6", \ + "88.4, 88.4, 88.4, 113.6, 163.6", \ + "100.6, 100.6, 100.6, 126.4, 177.5", \ + "123.3, 123.3, 123.3, 149.9, 202.3", \ + "166.7, 166.7, 166.7, 194.2, 248.3"); + } + rise_transition (inslew_load_5x5__102) { + values ("156.9, 156.9, 156.9, 202.0, 292.8", \ + "194.3, 194.3, 194.3, 238.9, 328.8", \ + "268.0, 268.0, 268.0, 311.8, 400.2", \ + "416.6, 416.6, 416.6, 459.6, 546.2", \ + "709.2, 709.2, 709.2, 752.5, 842.7"); + } + cell_fall (inslew_load_5x5__102) { + values ("22.0, 22.0, 22.0, 35.3, 61.5", \ + "24.2, 24.2, 24.2, 40.3, 68.2", \ + "25.3, 25.3, 25.3, 43.6, 76.4", \ + "24.9, 24.9, 24.9, 44.9, 81.9", \ + "22.3, 22.3, 22.3, 43.5, 83.8"); + } + fall_transition (inslew_load_5x5__102) { + values ("37.0, 37.0, 37.0, 52.6, 86.8", \ + "55.0, 55.0, 55.0, 72.0, 104.6", \ + "89.4, 89.4, 89.4, 107.1, 141.5", \ + "157.2, 157.2, 157.2, 175.4, 211.0", \ + "292.0, 292.0, 292.0, 310.6, 347.2"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + when : "(b ^ c)" ; + rise_power (energy_inslew_load_5x5__102) { + values ("541.6, 541.6, 541.6, 588.8, 683.1", \ + "579.1, 579.1, 579.1, 626.3, 720.6", \ + "653.3, 653.3, 653.3, 700.4, 794.8", \ + "799.8, 799.8, 799.8, 847.0, 941.4", \ + "1090.3, 1090.3, 1090.3, 1137.5, 1231.8"); + } + fall_power (energy_inslew_load_5x5__102) { + values ("558.6, 558.6, 558.6, 605.8, 700.1", \ + "620.9, 620.9, 620.9, 668.1, 762.4", \ + "743.4, 743.4, 743.4, 790.6, 884.9", \ + "986.3, 986.3, 986.3, 1033.5, 1127.9", \ + "1470.7, 1470.7, 1470.7, 1517.9, 1612.2"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + when : "(a ^ c)" ; + rise_power (energy_inslew_load_5x5__102) { + values ("537.3, 537.3, 537.3, 584.4, 678.8", \ + "599.2, 599.2, 599.2, 646.4, 740.7", \ + "717.7, 717.7, 717.7, 764.8, 859.2", \ + "951.5, 951.5, 951.5, 998.6, 1093.0", \ + "1416.9, 1416.9, 1416.9, 1464.1, 1558.5"); + } + fall_power (energy_inslew_load_5x5__102) { + values ("564.4, 564.4, 564.4, 611.6, 706.0", \ + "635.7, 635.7, 635.7, 682.9, 777.2", \ + "775.5, 775.5, 775.5, 822.6, 917.0", \ + "1052.7, 1052.7, 1052.7, 1099.9, 1194.3", \ + "1605.4, 1605.4, 1605.4, 1652.6, 1746.9"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + when : "(a ^ b)" ; + rise_power (energy_inslew_load_5x5__102) { + values ("171.6, 171.6, 171.6, 218.8, 313.1", \ + "209.6, 209.6, 209.6, 256.8, 351.1", \ + "284.6, 284.6, 284.6, 331.8, 426.1", \ + "433.8, 433.8, 433.8, 481.0, 575.3", \ + "731.6, 731.6, 731.6, 778.7, 873.1"); + } + fall_power (energy_inslew_load_5x5__102) { + values ("239.8, 239.8, 239.8, 287.0, 381.4", \ + "288.0, 288.0, 288.0, 335.2, 429.5", \ + "382.9, 382.9, 382.9, 430.1, 524.4", \ + "571.7, 571.7, 571.7, 618.9, 713.3", \ + "948.6, 948.6, 948.6, 995.7, 1090.1"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + when : "!((b ^ c))" ; + rise_power (energy_inslew_load_5x5__102) { + values ("617.6, 617.6, 617.6, 664.7, 759.1", \ + "681.8, 681.8, 681.8, 729.0, 823.3", \ + "809.5, 809.5, 809.5, 856.7, 951.1", \ + "1064.6, 1064.6, 1064.6, 1111.8, 1206.2", \ + "1572.7, 1572.7, 1572.7, 1619.9, 1714.2"); + } + fall_power (energy_inslew_load_5x5__102) { + values ("506.9, 506.9, 506.9, 554.0, 648.4", \ + "543.6, 543.6, 543.6, 590.8, 685.1", \ + "616.3, 616.3, 616.3, 663.5, 757.8", \ + "760.6, 760.6, 760.6, 807.8, 902.1", \ + "1047.3, 1047.3, 1047.3, 1094.5, 1188.8"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + when : "!((a ^ c))" ; + rise_power (energy_inslew_load_5x5__102) { + values ("383.4, 383.4, 383.4, 430.5, 524.9", \ + "460.2, 460.2, 460.2, 507.4, 601.7", \ + "609.3, 609.3, 609.3, 656.4, 750.8", \ + "905.6, 905.6, 905.6, 952.7, 1047.1", \ + "1496.1, 1496.1, 1496.1, 1543.3, 1637.6"); + } + fall_power (energy_inslew_load_5x5__102) { + values ("492.4, 492.4, 492.4, 539.6, 633.9", \ + "550.7, 550.7, 550.7, 597.8, 692.2", \ + "663.0, 663.0, 663.0, 710.2, 804.5", \ + "885.2, 885.2, 885.2, 932.3, 1026.7", \ + "1328.1, 1328.1, 1328.1, 1375.3, 1469.6"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + when : "!((a ^ b))" ; + rise_power (energy_inslew_load_5x5__102) { + values ("161.7, 161.7, 161.7, 208.9, 303.3", \ + "195.8, 195.8, 195.8, 243.0, 337.4", \ + "264.0, 264.0, 264.0, 311.2, 405.5", \ + "400.4, 400.4, 400.4, 447.6, 541.9", \ + "673.1, 673.1, 673.1, 720.3, 814.6"); + } + fall_power (energy_inslew_load_5x5__102) { + values ("86.4, 86.4, 86.4, 133.6, 227.9", \ + "116.0, 116.0, 116.0, 163.2, 257.5", \ + "175.2, 175.2, 175.2, 222.3, 316.7", \ + "293.5, 293.5, 293.5, 340.7, 435.0", \ + "530.1, 530.1, 530.1, 577.3, 671.6"); + } + } + } + } + + cell (xoon21v0x05) { + area : 0.0 ; + cell_leakage_power : 1.5 ; + leakage_power () { + when : "(b & !(a2) & a1)" ; + value : 1.8 ; + } + leakage_power () { + when : "(!(b) & !(a2) & a1)" ; + value : 0.62 ; + } + leakage_power () { + when : "(a2 & b)" ; + value : 2.8 ; + } + leakage_power () { + when : "(a2 & !(b))" ; + value : 1.6 ; + } + leakage_power () { + when : "(b & !(a2) & !(a1))" ; + value : 0.4 ; + } + leakage_power () { + when : "(!(b) & !(a2) & !(a1))" ; + value : 2 ; + } + pin (b) { + direction : input ; + capacitance : 4.62 ; + } + pin (a2) { + direction : input ; + capacitance : 4.17 ; + } + pin (a1) { + direction : input ; + capacitance : 3.97 ; + } + pin (z) { + function : "((a1 | a2) ^ b)" ; + direction : output ; + capacitance : 3.66 ; + timing (maxd_z_a1_positive_unate) { + related_pin : "a1" ; + when : "(!(a2) & !(b))" ; + sdf_cond : "(!(a2) & !(b))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__103) { + values ("85.9, 85.9, 85.9, 110.7, 159.7", \ + "103.4, 103.4, 103.4, 129.1, 179.0", \ + "131.0, 131.0, 131.0, 157.6, 208.8", \ + "180.1, 180.1, 180.1, 207.5, 259.7", \ + "273.2, 273.2, 273.2, 302.5, 358.0"); + } + rise_transition (inslew_load_5x5__103) { + values ("83.3, 83.3, 83.3, 126.3, 216.2", \ + "104.8, 104.8, 104.8, 147.9, 237.1", \ + "141.3, 141.3, 141.3, 185.1, 272.8", \ + "211.5, 211.5, 211.5, 254.0, 340.5", \ + "349.2, 349.2, 349.2, 392.9, 478.7"); + } + cell_fall (inslew_load_5x5__103) { + values ("58.3, 58.3, 58.3, 79.5, 115.1", \ + "49.7, 49.7, 49.7, 72.5, 110.2", \ + "29.4, 29.4, 29.4, 55.3, 97.0", \ + "-16.3, -16.3, -16.3, 14.7, 63.4", \ + "-118.3, -118.3, -118.3, -79.0, -18.2"); + } + fall_transition (inslew_load_5x5__103) { + values ("43.4, 43.4, 43.4, 64.6, 105.1", \ + "46.0, 46.0, 46.0, 67.6, 108.6", \ + "50.6, 50.6, 50.6, 73.2, 115.3", \ + "58.3, 58.3, 58.3, 82.8, 127.1", \ + "71.1, 71.1, 71.1, 98.8, 147.4"); + } + } + timing (maxd_z_a2_positive_unate) { + related_pin : "a2" ; + when : "(!(a1) & !(b))" ; + sdf_cond : "(!(a1) & !(b))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__103) { + values ("85.8, 85.8, 85.8, 110.7, 159.6", \ + "95.5, 95.5, 95.5, 121.1, 170.8", \ + "105.6, 105.6, 105.6, 132.0, 182.9", \ + "116.9, 116.9, 116.9, 143.3, 195.3", \ + "131.7, 131.7, 131.7, 160.4, 213.6"); + } + rise_transition (inslew_load_5x5__103) { + values ("83.3, 83.3, 83.3, 126.2, 216.1", \ + "99.8, 99.8, 99.8, 143.1, 232.6", \ + "127.0, 127.0, 127.0, 170.8, 258.9", \ + "177.9, 177.9, 177.9, 219.5, 306.7", \ + "276.2, 276.2, 276.2, 319.6, 403.6"); + } + cell_fall (inslew_load_5x5__103) { + values ("63.9, 63.9, 63.9, 84.8, 120.0", \ + "63.8, 63.8, 63.8, 86.6, 124.4", \ + "56.5, 56.5, 56.5, 83.1, 125.6", \ + "33.1, 33.1, 33.1, 65.5, 116.3", \ + "-26.6, -26.6, -26.6, 15.2, 79.5"); + } + fall_transition (inslew_load_5x5__103) { + values ("42.9, 42.9, 42.9, 63.9, 104.4", \ + "46.1, 46.1, 46.1, 67.7, 108.7", \ + "51.5, 51.5, 51.5, 74.4, 116.7", \ + "60.6, 60.6, 60.6, 85.6, 130.6", \ + "75.1, 75.1, 75.1, 103.7, 153.6"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + when : "(!(a1) & !(a2))" ; + sdf_cond : "(!(a1) & !(a2))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__103) { + values ("53.3, 53.3, 53.3, 71.0, 112.6", \ + "60.0, 60.0, 60.0, 78.8, 121.9", \ + "66.2, 66.2, 66.2, 87.3, 132.8", \ + "70.4, 70.4, 70.4, 95.1, 143.4", \ + "76.4, 76.4, 76.4, 103.3, 151.1"); + } + rise_transition (inslew_load_5x5__103) { + values ("49.6, 49.6, 49.6, 78.5, 151.0", \ + "65.3, 65.3, 65.3, 95.7, 170.2", \ + "89.3, 89.3, 89.3, 123.1, 200.2", \ + "128.6, 128.6, 128.6, 166.4, 245.3", \ + "205.6, 205.6, 205.6, 244.7, 317.8"); + } + cell_fall (inslew_load_5x5__103) { + values ("81.8, 81.8, 81.8, 101.9, 136.7", \ + "91.0, 91.0, 91.0, 112.2, 148.7", \ + "102.9, 102.9, 102.9, 125.3, 164.6", \ + "119.0, 119.0, 119.0, 143.3, 186.0", \ + "145.8, 145.8, 145.8, 171.3, 218.3"); + } + fall_transition (inslew_load_5x5__103) { + values ("54.1, 54.1, 54.1, 75.2, 116.2", \ + "64.7, 64.7, 64.7, 86.0, 127.2", \ + "84.2, 84.2, 84.2, 105.8, 147.5", \ + "121.5, 121.5, 121.5, 143.5, 186.2", \ + "194.4, 194.4, 194.4, 217.0, 260.7"); + } + } + timing (maxd_z_a1_negative_unate) { + related_pin : "a1" ; + when : "(!(a2) & b)" ; + sdf_cond : "(!(a2) & b)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__103) { + values ("107.9, 107.9, 107.9, 130.5, 175.7", \ + "103.6, 103.6, 103.6, 126.5, 172.1", \ + "94.1, 94.1, 94.1, 117.3, 163.3", \ + "74.2, 74.2, 74.2, 97.9, 145.3", \ + "32.2, 32.2, 32.2, 56.8, 105.4"); + } + rise_transition (inslew_load_5x5__103) { + values ("206.4, 206.4, 206.4, 246.6, 327.5", \ + "230.6, 230.6, 230.6, 270.7, 351.1", \ + "277.2, 277.2, 277.2, 317.0, 396.8", \ + "373.0, 373.0, 373.0, 411.8, 490.1", \ + "568.2, 568.2, 568.2, 606.4, 683.2"); + } + cell_fall (inslew_load_5x5__103) { + values ("79.9, 79.9, 79.9, 107.4, 162.4", \ + "94.0, 94.0, 94.0, 121.6, 176.6", \ + "116.7, 116.7, 116.7, 144.3, 199.3", \ + "157.4, 157.4, 157.4, 184.9, 240.0", \ + "235.6, 235.6, 235.6, 263.1, 318.2"); + } + fall_transition (inslew_load_5x5__103) { + values ("73.3, 73.3, 73.3, 98.1, 147.8", \ + "96.0, 96.0, 96.0, 120.9, 170.5", \ + "139.1, 139.1, 139.1, 163.9, 213.6", \ + "223.1, 223.1, 223.1, 247.9, 297.6", \ + "389.6, 389.6, 389.6, 414.5, 464.2"); + } + } + timing (maxd_z_a2_negative_unate) { + related_pin : "a2" ; + when : "(!(a1) & b)" ; + sdf_cond : "(!(a1) & b)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__103) { + values ("98.2, 98.2, 98.2, 121.0, 166.6", \ + "103.3, 103.3, 103.3, 126.5, 172.6", \ + "109.3, 109.3, 109.3, 133.5, 181.1", \ + "116.6, 116.6, 116.6, 142.4, 192.7", \ + "125.6, 125.6, 125.6, 153.0, 206.5"); + } + rise_transition (inslew_load_5x5__103) { + values ("178.7, 178.7, 178.7, 219.7, 302.1", \ + "207.5, 207.5, 207.5, 247.8, 329.0", \ + "264.8, 264.8, 264.8, 304.2, 383.6", \ + "377.3, 377.3, 377.3, 416.8, 497.8", \ + "603.5, 603.5, 603.5, 643.2, 722.1"); + } + cell_fall (inslew_load_5x5__103) { + values ("79.8, 79.8, 79.8, 107.4, 162.4", \ + "86.8, 86.8, 86.8, 114.3, 169.4", \ + "93.1, 93.1, 93.1, 120.7, 175.7", \ + "98.2, 98.2, 98.2, 125.7, 180.8", \ + "101.9, 101.9, 101.9, 129.5, 184.5"); + } + fall_transition (inslew_load_5x5__103) { + values ("73.2, 73.2, 73.2, 98.0, 147.7", \ + "90.4, 90.4, 90.4, 115.2, 164.9", \ + "122.1, 122.1, 122.1, 147.0, 196.7", \ + "182.7, 182.7, 182.7, 207.5, 257.2", \ + "301.1, 301.1, 301.1, 326.0, 375.7"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + when : "(a1 | a2)" ; + sdf_cond : "(a1 | a2)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__103) { + values ("92.7, 92.7, 92.7, 116.8, 164.8", \ + "102.9, 102.9, 102.9, 127.3, 175.8", \ + "119.6, 119.6, 119.6, 144.8, 193.9", \ + "150.9, 150.9, 150.9, 176.5, 226.9", \ + "211.8, 211.8, 211.8, 238.0, 289.8"); + } + rise_transition (inslew_load_5x5__103) { + values ("172.0, 172.0, 172.0, 215.7, 303.7", \ + "215.1, 215.1, 215.1, 258.3, 345.6", \ + "296.3, 296.3, 296.3, 338.9, 424.9", \ + "458.0, 458.0, 458.0, 500.0, 584.4", \ + "782.1, 782.1, 782.1, 823.6, 906.9"); + } + cell_fall (inslew_load_5x5__103) { + values ("56.1, 56.1, 56.1, 83.0, 136.9", \ + "55.8, 55.8, 55.8, 84.2, 140.4", \ + "44.7, 44.7, 44.7, 76.1, 136.6", \ + "4.2, 4.2, 4.2, 42.3, 111.0", \ + "-109.8, -109.8, -109.8, -57.7, 28.7"); + } + fall_transition (inslew_load_5x5__103) { + values ("70.8, 70.8, 70.8, 97.4, 150.7", \ + "87.3, 87.3, 87.3, 114.4, 167.9", \ + "115.5, 115.5, 115.5, 144.4, 200.1", \ + "160.6, 160.6, 160.6, 194.1, 255.4", \ + "228.9, 228.9, 228.9, 272.1, 345.9"); + } + } + internal_power (energy_pos_z_a1) { + related_pin : "a1" ; + when : "(!(a2) & !(b))" ; + rise_power (energy_inslew_load_5x5__103) { + values ("245.5, 245.5, 245.5, 291.3, 382.8", \ + "305.2, 305.2, 305.2, 351.0, 442.5", \ + "423.0, 423.0, 423.0, 468.7, 560.2", \ + "657.1, 657.1, 657.1, 702.8, 794.3", \ + "1124.4, 1124.4, 1124.4, 1170.1, 1261.6"); + } + fall_power (energy_inslew_load_5x5__103) { + values ("237.5, 237.5, 237.5, 283.2, 374.7", \ + "270.5, 270.5, 270.5, 316.2, 407.7", \ + "336.5, 336.5, 336.5, 382.3, 473.8", \ + "468.6, 468.6, 468.6, 514.4, 605.9", \ + "732.8, 732.8, 732.8, 778.6, 870.1"); + } + } + internal_power (energy_pos_z_a2) { + related_pin : "a2" ; + when : "(!(a1) & !(b))" ; + rise_power (energy_inslew_load_5x5__103) { + values ("239.2, 239.2, 239.2, 285.0, 376.5", \ + "276.0, 276.0, 276.0, 321.8, 413.2", \ + "347.8, 347.8, 347.8, 393.5, 485.0", \ + "489.3, 489.3, 489.3, 535.1, 626.6", \ + "770.7, 770.7, 770.7, 816.4, 907.9"); + } + fall_power (energy_inslew_load_5x5__103) { + values ("225.7, 225.7, 225.7, 271.4, 362.9", \ + "260.6, 260.6, 260.6, 306.4, 397.9", \ + "330.6, 330.6, 330.6, 376.3, 467.8", \ + "470.4, 470.4, 470.4, 516.1, 607.6", \ + "750.1, 750.1, 750.1, 795.8, 887.3"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + when : "(!(a1) & !(a2))" ; + rise_power (energy_inslew_load_5x5__103) { + values ("183.7, 183.7, 183.7, 229.4, 320.9", \ + "222.1, 222.1, 222.1, 267.8, 359.3", \ + "297.7, 297.7, 297.7, 343.4, 434.9", \ + "448.1, 448.1, 448.1, 493.9, 585.3", \ + "748.2, 748.2, 748.2, 794.0, 885.4"); + } + fall_power (energy_inslew_load_5x5__103) { + values ("250.1, 250.1, 250.1, 295.8, 387.3", \ + "296.6, 296.6, 296.6, 342.4, 433.8", \ + "388.5, 388.5, 388.5, 434.2, 525.7", \ + "571.2, 571.2, 571.2, 616.9, 708.4", \ + "935.8, 935.8, 935.8, 981.5, 1073.0"); + } + } + internal_power (energy_neg_z_a1) { + related_pin : "a1" ; + when : "(!(a2) & b)" ; + rise_power (energy_inslew_load_5x5__103) { + values ("297.0, 297.0, 297.0, 342.7, 434.2", \ + "330.0, 330.0, 330.0, 375.7, 467.2", \ + "396.1, 396.1, 396.1, 441.8, 533.3", \ + "528.2, 528.2, 528.2, 573.9, 665.4", \ + "792.4, 792.4, 792.4, 838.1, 929.6"); + } + fall_power (energy_inslew_load_5x5__103) { + values ("205.2, 205.2, 205.2, 251.0, 342.5", \ + "249.7, 249.7, 249.7, 295.4, 386.9", \ + "338.5, 338.5, 338.5, 384.3, 475.8", \ + "516.3, 516.3, 516.3, 562.0, 653.5", \ + "871.8, 871.8, 871.8, 917.6, 1009.0"); + } + } + internal_power (energy_neg_z_a2) { + related_pin : "a2" ; + when : "(!(a1) & b)" ; + rise_power (energy_inslew_load_5x5__103) { + values ("253.2, 253.2, 253.2, 298.9, 390.4", \ + "288.1, 288.1, 288.1, 333.9, 425.4", \ + "358.1, 358.1, 358.1, 403.8, 495.3", \ + "497.9, 497.9, 497.9, 543.6, 635.1", \ + "777.6, 777.6, 777.6, 823.3, 914.8"); + } + fall_power (energy_inslew_load_5x5__103) { + values ("199.0, 199.0, 199.0, 244.7, 336.2", \ + "224.2, 224.2, 224.2, 270.0, 361.4", \ + "274.7, 274.7, 274.7, 320.4, 411.9", \ + "375.6, 375.6, 375.6, 421.4, 512.8", \ + "577.5, 577.5, 577.5, 623.2, 714.7"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + when : "(a1 | a2)" ; + rise_power (energy_inslew_load_5x5__103) { + values ("181.0, 181.0, 181.0, 226.7, 318.2", \ + "218.7, 218.7, 218.7, 264.4, 355.9", \ + "294.1, 294.1, 294.1, 339.9, 431.4", \ + "445.0, 445.0, 445.0, 490.7, 582.2", \ + "746.7, 746.7, 746.7, 792.4, 883.9"); + } + fall_power (energy_inslew_load_5x5__103) { + values ("91.0, 91.0, 91.0, 136.8, 228.2", \ + "120.2, 120.2, 120.2, 166.0, 257.4", \ + "178.6, 178.6, 178.6, 224.4, 315.8", \ + "295.4, 295.4, 295.4, 341.1, 432.6", \ + "529.0, 529.0, 529.0, 574.7, 666.2"); + } + } + } + } + + cell (xor2v0x05) { + area : 0.0 ; + cell_leakage_power : 3.5 ; + leakage_power () { + when : "(b & a)" ; + value : 5.6 ; + } + leakage_power () { + when : "(!(b) & a)" ; + value : 2.7 ; + } + leakage_power () { + when : "(b & !(a))" ; + value : 1.4 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 4.1 ; + } + pin (b) { + direction : input ; + capacitance : 5.05 ; + } + pin (a) { + direction : input ; + capacitance : 2.84 ; + } + pin (z) { + function : "(a ^ b)" ; + direction : output ; + capacitance : 3.60 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + when : "!(b)" ; + sdf_cond : "!(b)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__104) { + values ("73.6, 73.6, 73.6, 91.9, 127.3", \ + "80.9, 80.9, 80.9, 99.7, 135.7", \ + "87.9, 87.9, 87.9, 106.0, 142.8", \ + "93.8, 93.8, 93.8, 113.8, 151.1", \ + "97.9, 97.9, 97.9, 119.0, 159.0"); + } + rise_transition (inslew_load_5x5__104) { + values ("71.4, 71.4, 71.4, 103.1, 167.9", \ + "85.8, 85.8, 85.8, 117.8, 181.9", \ + "111.8, 111.8, 111.8, 141.3, 204.9", \ + "160.2, 160.2, 160.2, 191.6, 253.1", \ + "253.8, 253.8, 253.8, 285.6, 348.3"); + } + cell_fall (inslew_load_5x5__104) { + values ("53.2, 53.2, 53.2, 69.5, 96.8", \ + "53.1, 53.1, 53.1, 71.2, 101.1", \ + "46.0, 46.0, 46.0, 67.4, 101.5", \ + "23.2, 23.2, 23.2, 49.5, 91.3", \ + "-34.6, -34.6, -34.6, -0.2, 53.1"); + } + fall_transition (inslew_load_5x5__104) { + values ("35.3, 35.3, 35.3, 50.5, 79.3", \ + "38.5, 38.5, 38.5, 54.3, 83.8", \ + "43.9, 43.9, 43.9, 60.8, 91.6", \ + "52.8, 52.8, 52.8, 71.7, 105.1", \ + "67.2, 67.2, 67.2, 89.1, 127.2"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + when : "!(a)" ; + sdf_cond : "!(a)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__104) { + values ("60.6, 60.6, 60.6, 81.8, 126.9", \ + "75.3, 75.3, 75.3, 98.2, 144.6", \ + "97.3, 97.3, 97.3, 121.1, 169.1", \ + "136.7, 136.7, 136.7, 160.8, 208.2", \ + "213.0, 213.0, 213.0, 240.0, 289.5"); + } + rise_transition (inslew_load_5x5__104) { + values ("61.7, 61.7, 61.7, 98.8, 182.3", \ + "84.5, 84.5, 84.5, 123.6, 208.4", \ + "120.9, 120.9, 120.9, 160.9, 245.2", \ + "188.5, 188.5, 188.5, 227.0, 307.0", \ + "322.1, 322.1, 322.1, 363.4, 442.3"); + } + cell_fall (inslew_load_5x5__104) { + values ("50.7, 50.7, 50.7, 65.8, 91.4", \ + "51.0, 51.0, 51.0, 67.1, 94.4", \ + "45.7, 45.7, 45.7, 63.5, 93.4", \ + "29.9, 29.9, 29.9, 49.4, 83.1", \ + "-7.2, -7.2, -7.2, 14.6, 52.6"); + } + fall_transition (inslew_load_5x5__104) { + values ("33.7, 33.7, 33.7, 48.6, 77.5", \ + "39.7, 39.7, 39.7, 55.0, 84.1", \ + "51.0, 51.0, 51.0, 66.6, 96.4", \ + "72.4, 72.4, 72.4, 88.7, 119.4", \ + "114.4, 114.4, 114.4, 131.2, 163.4"); + } + } + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + when : "b" ; + sdf_cond : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__104) { + values ("75.8, 75.8, 75.8, 98.9, 144.9", \ + "78.5, 78.5, 78.5, 102.4, 149.4", \ + "80.2, 80.2, 80.2, 105.7, 154.7", \ + "78.5, 78.5, 78.5, 106.0, 158.7", \ + "69.4, 69.4, 69.4, 98.9, 155.8"); + } + rise_transition (inslew_load_5x5__104) { + values ("146.3, 146.3, 146.3, 188.8, 274.8", \ + "174.1, 174.1, 174.1, 215.5, 299.7", \ + "228.6, 228.6, 228.6, 269.9, 353.1", \ + "337.5, 337.5, 337.5, 378.9, 461.4", \ + "553.6, 553.6, 553.6, 595.5, 678.9"); + } + cell_fall (inslew_load_5x5__104) { + values ("48.7, 48.7, 48.7, 61.1, 85.6", \ + "49.8, 49.8, 49.8, 63.8, 90.4", \ + "45.2, 45.2, 45.2, 61.6, 92.2", \ + "27.8, 27.8, 27.8, 47.0, 82.8", \ + "-15.3, -15.3, -15.3, 6.4, 47.7"); + } + fall_transition (inslew_load_5x5__104) { + values ("66.7, 66.7, 66.7, 83.4, 117.1", \ + "80.7, 80.7, 80.7, 97.4, 130.6", \ + "107.6, 107.6, 107.6, 124.9, 158.6", \ + "159.2, 159.2, 159.2, 177.2, 212.3", \ + "260.0, 260.0, 260.0, 278.7, 315.4"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + when : "a" ; + sdf_cond : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__104) { + values ("59.0, 59.0, 59.0, 76.3, 110.6", \ + "58.9, 58.9, 58.9, 76.9, 111.8", \ + "57.0, 57.0, 57.0, 75.6, 111.8", \ + "50.6, 50.6, 50.6, 70.3, 108.5", \ + "35.0, 35.0, 35.0, 55.7, 96.0"); + } + rise_transition (inslew_load_5x5__104) { + values ("121.6, 121.6, 121.6, 153.1, 216.5", \ + "148.7, 148.7, 148.7, 179.6, 242.0", \ + "202.3, 202.3, 202.3, 233.7, 294.6", \ + "309.9, 309.9, 309.9, 340.4, 401.4", \ + "524.6, 524.6, 524.6, 555.3, 616.5"); + } + cell_fall (inslew_load_5x5__104) { + values ("27.0, 27.0, 27.0, 40.0, 65.7", \ + "35.5, 35.5, 35.5, 50.6, 77.6", \ + "49.5, 49.5, 49.5, 66.0, 96.6", \ + "75.2, 75.2, 75.2, 92.8, 126.2", \ + "125.1, 125.1, 125.1, 143.5, 178.9"); + } + fall_transition (inslew_load_5x5__104) { + values ("41.2, 41.2, 41.2, 56.8, 90.5", \ + "65.3, 65.3, 65.3, 81.9, 114.1", \ + "111.5, 111.5, 111.5, 128.5, 161.9", \ + "202.4, 202.4, 202.4, 219.7, 253.9", \ + "383.5, 383.5, 383.5, 401.0, 435.7"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + when : "!(b)" ; + rise_power (energy_inslew_load_5x5__104) { + values ("233.2, 233.2, 233.2, 278.2, 368.3", \ + "271.0, 271.0, 271.0, 316.0, 406.2", \ + "344.9, 344.9, 344.9, 389.9, 480.0", \ + "490.2, 490.2, 490.2, 535.3, 625.4", \ + "778.9, 778.9, 778.9, 824.0, 914.1"); + } + fall_power (energy_inslew_load_5x5__104) { + values ("217.8, 217.8, 217.8, 262.9, 353.0", \ + "253.8, 253.8, 253.8, 298.8, 388.9", \ + "325.6, 325.6, 325.6, 370.7, 460.8", \ + "469.3, 469.3, 469.3, 514.4, 604.5", \ + "756.7, 756.7, 756.7, 801.8, 891.9"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + when : "!(a)" ; + rise_power (energy_inslew_load_5x5__104) { + values ("194.4, 194.4, 194.4, 239.5, 329.6", \ + "252.4, 252.4, 252.4, 297.5, 387.6", \ + "367.1, 367.1, 367.1, 412.1, 502.2", \ + "595.1, 595.1, 595.1, 640.2, 730.3", \ + "1050.5, 1050.5, 1050.5, 1095.6, 1185.7"); + } + fall_power (energy_inslew_load_5x5__104) { + values ("217.2, 217.2, 217.2, 262.2, 352.3", \ + "258.2, 258.2, 258.2, 303.3, 393.4", \ + "339.5, 339.5, 339.5, 384.6, 474.7", \ + "501.4, 501.4, 501.4, 546.5, 636.6", \ + "824.8, 824.8, 824.8, 869.8, 960.0"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + when : "b" ; + rise_power (energy_inslew_load_5x5__104) { + values ("216.1, 216.1, 216.1, 261.1, 351.2", \ + "252.0, 252.0, 252.0, 297.0, 387.2", \ + "323.8, 323.8, 323.8, 368.9, 459.0", \ + "467.5, 467.5, 467.5, 512.6, 602.7", \ + "754.9, 754.9, 754.9, 800.0, 890.1"); + } + fall_power (energy_inslew_load_5x5__104) { + values ("189.2, 189.2, 189.2, 234.3, 324.4", \ + "212.6, 212.6, 212.6, 257.7, 347.8", \ + "259.5, 259.5, 259.5, 304.6, 394.7", \ + "353.3, 353.3, 353.3, 398.4, 488.5", \ + "540.9, 540.9, 540.9, 585.9, 676.1"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + when : "a" ; + rise_power (energy_inslew_load_5x5__104) { + values ("166.7, 166.7, 166.7, 211.8, 301.9", \ + "198.2, 198.2, 198.2, 243.3, 333.4", \ + "261.2, 261.2, 261.2, 306.2, 396.4", \ + "387.1, 387.1, 387.1, 432.2, 522.3", \ + "638.9, 638.9, 638.9, 684.0, 774.1"); + } + fall_power (energy_inslew_load_5x5__104) { + values ("100.0, 100.0, 100.0, 145.0, 235.1", \ + "142.7, 142.7, 142.7, 187.8, 277.9", \ + "228.3, 228.3, 228.3, 273.4, 363.5", \ + "399.4, 399.4, 399.4, 444.5, 534.6", \ + "741.7, 741.7, 741.7, 786.7, 876.8"); + } + } + } + } + + cell (xor2v1x05) { + area : 0.0 ; + cell_leakage_power : 9.3 ; + leakage_power () { + when : "(b & a)" ; + value : 16 ; + } + leakage_power () { + when : "(a ^ b)" ; + value : 4.9 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 6.6 ; + } + pin (b) { + direction : input ; + capacitance : 5.31 ; + } + pin (a) { + direction : input ; + capacitance : 2.67 ; + } + pin (z) { + function : "(a ^ b)" ; + direction : output ; + capacitance : 2.68 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + when : "!(b)" ; + sdf_cond : "!(b)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__105) { + values ("85.3, 85.3, 85.3, 103.9, 140.3", \ + "89.5, 89.5, 89.5, 108.5, 145.4", \ + "91.1, 91.1, 91.1, 110.8, 148.5", \ + "86.9, 86.9, 86.9, 107.8, 147.3", \ + "72.1, 72.1, 72.1, 94.5, 136.9"); + } + rise_transition (inslew_load_5x5__105) { + values ("96.8, 96.8, 96.8, 131.0, 200.5", \ + "106.5, 106.5, 106.5, 140.2, 209.0", \ + "123.4, 123.4, 123.4, 157.6, 225.2", \ + "156.1, 156.1, 156.1, 189.8, 258.1", \ + "219.4, 219.4, 219.4, 253.5, 321.0"); + } + cell_fall (inslew_load_5x5__105) { + values ("84.3, 84.3, 84.3, 97.8, 122.6", \ + "92.3, 92.3, 92.3, 106.6, 132.8", \ + "101.6, 101.6, 101.6, 117.2, 145.7", \ + "113.5, 113.5, 113.5, 130.6, 162.4", \ + "131.0, 131.0, 131.0, 150.0, 185.1"); + } + fall_transition (inslew_load_5x5__105) { + values ("64.2, 64.2, 64.2, 79.4, 109.4", \ + "73.8, 73.8, 73.8, 89.2, 119.4", \ + "91.8, 91.8, 91.8, 107.5, 138.1", \ + "126.6, 126.6, 126.6, 142.7, 174.0", \ + "194.7, 194.7, 194.7, 211.2, 243.5"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + when : "!(a)" ; + sdf_cond : "!(a)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__105) { + values ("46.2, 46.2, 46.2, 62.1, 96.8", \ + "52.0, 52.0, 52.0, 68.6, 104.4", \ + "56.8, 56.8, 56.8, 75.7, 113.1", \ + "62.5, 62.5, 62.5, 83.1, 119.5", \ + "71.6, 71.6, 71.6, 93.6, 135.2"); + } + rise_transition (inslew_load_5x5__105) { + values ("49.6, 49.6, 49.6, 78.0, 144.5", \ + "66.5, 66.5, 66.5, 95.6, 162.7", \ + "92.2, 92.2, 92.2, 124.7, 192.4", \ + "139.9, 139.9, 139.9, 173.4, 236.9", \ + "234.4, 234.4, 234.4, 268.5, 336.2"); + } + cell_fall (inslew_load_5x5__105) { + values ("50.7, 50.7, 50.7, 65.0, 89.8", \ + "56.4, 56.4, 56.4, 72.0, 98.8", \ + "63.7, 63.7, 63.7, 80.6, 110.3", \ + "73.8, 73.8, 73.8, 92.5, 125.6", \ + "91.5, 91.5, 91.5, 111.3, 148.3"); + } + fall_transition (inslew_load_5x5__105) { + values ("36.8, 36.8, 36.8, 52.0, 81.6", \ + "46.3, 46.3, 46.3, 61.9, 91.9", \ + "64.1, 64.1, 64.1, 80.1, 110.8", \ + "98.8, 98.8, 98.8, 115.2, 146.9", \ + "167.4, 167.4, 167.4, 184.2, 216.7"); + } + } + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + when : "b" ; + sdf_cond : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__105) { + values ("67.7, 67.7, 67.7, 85.9, 122.1", \ + "69.6, 69.6, 69.6, 88.7, 126.1", \ + "69.5, 69.5, 69.5, 90.0, 129.6", \ + "63.6, 63.6, 63.6, 86.1, 129.2", \ + "46.0, 46.0, 46.0, 70.3, 117.3"); + } + rise_transition (inslew_load_5x5__105) { + values ("134.6, 134.6, 134.6, 169.1, 238.9", \ + "161.3, 161.3, 161.3, 194.9, 262.9", \ + "212.6, 212.6, 212.6, 246.3, 314.9", \ + "314.7, 314.7, 314.7, 348.9, 416.7", \ + "517.2, 517.2, 517.2, 552.0, 620.8"); + } + cell_fall (inslew_load_5x5__105) { + values ("49.4, 49.4, 49.4, 60.4, 82.3", \ + "51.5, 51.5, 51.5, 63.9, 87.8", \ + "49.3, 49.3, 49.3, 63.8, 91.1", \ + "37.2, 37.2, 37.2, 54.0, 85.8", \ + "5.9, 5.9, 5.9, 24.8, 61.0"); + } + fall_transition (inslew_load_5x5__105) { + values ("67.6, 67.6, 67.6, 82.6, 113.0", \ + "82.8, 82.8, 82.8, 97.9, 127.9", \ + "112.1, 112.1, 112.1, 127.7, 158.2", \ + "168.7, 168.7, 168.7, 184.9, 216.5", \ + "279.7, 279.7, 279.7, 296.4, 329.3"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + when : "a" ; + sdf_cond : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__105) { + values ("29.3, 29.3, 29.3, 49.0, 86.3", \ + "39.2, 39.2, 39.2, 58.7, 97.6", \ + "56.9, 56.9, 56.9, 79.0, 119.4", \ + "90.2, 90.2, 90.2, 113.4, 157.8", \ + "155.5, 155.5, 155.5, 179.5, 226.2"); + } + rise_transition (inslew_load_5x5__105) { + values ("68.9, 68.9, 68.9, 103.4, 173.2", \ + "108.7, 108.7, 108.7, 140.6, 209.1", \ + "186.1, 186.1, 186.1, 220.4, 286.6", \ + "339.3, 339.3, 339.3, 374.1, 443.0", \ + "644.7, 644.7, 644.7, 679.8, 749.5"); + } + cell_fall (inslew_load_5x5__105) { + values ("14.8, 14.8, 14.8, 27.8, 50.3", \ + "12.8, 12.8, 12.8, 28.2, 54.7", \ + "6.0, 6.0, 6.0, 23.8, 54.9", \ + "-10.0, -10.0, -10.0, 9.6, 45.3", \ + "-43.7, -43.7, -43.7, -22.8, 16.5"); + } + fall_transition (inslew_load_5x5__105) { + values ("29.9, 29.9, 29.9, 44.6, 73.2", \ + "44.6, 44.6, 44.6, 60.0, 89.9", \ + "72.7, 72.7, 72.7, 89.0, 120.1", \ + "128.0, 128.0, 128.0, 144.9, 177.6", \ + "238.1, 238.1, 238.1, 255.3, 289.2"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + when : "!(b)" ; + rise_power (energy_inslew_load_5x5__105) { + values ("232.2, 232.2, 232.2, 265.6, 332.6", \ + "264.3, 264.3, 264.3, 297.8, 364.7", \ + "327.4, 327.4, 327.4, 360.8, 427.8", \ + "452.2, 452.2, 452.2, 485.7, 552.6", \ + "700.8, 700.8, 700.8, 734.2, 801.1"); + } + fall_power (energy_inslew_load_5x5__105) { + values ("245.8, 245.8, 245.8, 279.2, 346.1", \ + "288.7, 288.7, 288.7, 322.2, 389.1", \ + "373.2, 373.2, 373.2, 406.7, 473.6", \ + "541.3, 541.3, 541.3, 574.7, 641.7", \ + "876.6, 876.6, 876.6, 910.1, 977.0"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + when : "!(a)" ; + rise_power (energy_inslew_load_5x5__105) { + values ("126.8, 126.8, 126.8, 160.2, 227.1", \ + "158.5, 158.5, 158.5, 192.0, 258.9", \ + "221.1, 221.1, 221.1, 254.6, 321.5", \ + "345.4, 345.4, 345.4, 378.9, 445.8", \ + "593.5, 593.5, 593.5, 627.0, 693.9"); + } + fall_power (energy_inslew_load_5x5__105) { + values ("140.8, 140.8, 140.8, 174.3, 241.2", \ + "180.7, 180.7, 180.7, 214.2, 281.1", \ + "259.7, 259.7, 259.7, 293.2, 360.1", \ + "417.1, 417.1, 417.1, 450.6, 517.5", \ + "731.5, 731.5, 731.5, 764.9, 831.8"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + when : "b" ; + rise_power (energy_inslew_load_5x5__105) { + values ("179.5, 179.5, 179.5, 213.0, 279.9", \ + "208.4, 208.4, 208.4, 241.9, 308.8", \ + "266.2, 266.2, 266.2, 299.7, 366.6", \ + "381.8, 381.8, 381.8, 415.3, 482.2", \ + "613.0, 613.0, 613.0, 646.4, 713.4"); + } + fall_power (energy_inslew_load_5x5__105) { + values ("158.7, 158.7, 158.7, 192.1, 259.0", \ + "180.9, 180.9, 180.9, 214.4, 281.3", \ + "225.4, 225.4, 225.4, 258.9, 325.8", \ + "314.4, 314.4, 314.4, 347.9, 414.8", \ + "492.5, 492.5, 492.5, 525.9, 592.8"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + when : "a" ; + rise_power (energy_inslew_load_5x5__105) { + values ("61.5, 61.5, 61.5, 94.9, 161.9", \ + "90.3, 90.3, 90.3, 123.8, 190.7", \ + "148.0, 148.0, 148.0, 181.4, 248.3", \ + "263.3, 263.3, 263.3, 296.7, 363.7", \ + "493.9, 493.9, 493.9, 527.4, 594.3"); + } + fall_power (energy_inslew_load_5x5__105) { + values ("52.0, 52.0, 52.0, 85.5, 152.4", \ + "69.8, 69.8, 69.8, 103.3, 170.2", \ + "105.4, 105.4, 105.4, 138.9, 205.8", \ + "176.6, 176.6, 176.6, 210.0, 276.9", \ + "318.9, 318.9, 318.9, 352.3, 419.2"); + } + } + } + } + + cell (xor2v2x05) { + area : 0.0 ; + cell_leakage_power : 0.79 ; + leakage_power () { + when : "(b & a)" ; + value : 1.2 ; + } + leakage_power () { + when : "(a ^ b)" ; + value : 0.4 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 0.79 ; + } + pin (b) { + direction : input ; + capacitance : 4.62 ; + } + pin (a) { + direction : input ; + capacitance : 4.14 ; + } + pin (z) { + function : "(a ^ b)" ; + direction : output ; + capacitance : 4.79 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + when : "!(b)" ; + sdf_cond : "!(b)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__106) { + values ("103.0, 103.0, 103.0, 128.4, 177.7", \ + "118.8, 118.8, 118.8, 144.5, 194.4", \ + "140.4, 140.4, 140.4, 165.6, 216.6", \ + "179.9, 179.9, 179.9, 204.5, 256.4", \ + "249.8, 249.8, 249.8, 276.6, 329.1"); + } + rise_transition (inslew_load_5x5__106) { + values ("102.0, 102.0, 102.0, 145.4, 233.6", \ + "121.4, 121.4, 121.4, 164.7, 252.4", \ + "153.4, 153.4, 153.4, 195.0, 281.5", \ + "222.8, 222.8, 222.8, 261.4, 347.4", \ + "356.1, 356.1, 356.1, 396.9, 479.5"); + } + cell_fall (inslew_load_5x5__106) { + values ("69.6, 69.6, 69.6, 85.1, 112.8", \ + "72.7, 72.7, 72.7, 89.0, 117.8", \ + "71.7, 71.7, 71.7, 89.1, 119.9", \ + "61.8, 61.8, 61.8, 80.9, 114.7", \ + "34.7, 34.7, 34.7, 55.4, 93.2"); + } + fall_transition (inslew_load_5x5__106) { + values ("47.4, 47.4, 47.4, 64.1, 97.0", \ + "53.0, 53.0, 53.0, 69.9, 102.9", \ + "63.5, 63.5, 63.5, 80.7, 113.9", \ + "83.5, 83.5, 83.5, 101.1, 135.1", \ + "122.3, 122.3, 122.3, 140.7, 175.6"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + when : "!(a)" ; + sdf_cond : "!(a)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__106) { + values ("86.4, 86.4, 86.4, 111.3, 160.8", \ + "99.4, 99.4, 99.4, 124.8, 175.0", \ + "118.0, 118.0, 118.0, 144.2, 195.4", \ + "147.2, 147.2, 147.2, 174.3, 224.4", \ + "198.8, 198.8, 198.8, 228.0, 281.5"); + } + rise_transition (inslew_load_5x5__106) { + values ("78.4, 78.4, 78.4, 120.0, 207.8", \ + "94.2, 94.2, 94.2, 135.9, 223.2", \ + "123.3, 123.3, 123.3, 165.4, 251.5", \ + "178.4, 178.4, 178.4, 219.5, 300.6", \ + "286.2, 286.2, 286.2, 328.6, 410.2"); + } + cell_fall (inslew_load_5x5__106) { + values ("67.9, 67.9, 67.9, 85.8, 116.0", \ + "72.1, 72.1, 72.1, 91.1, 123.0", \ + "73.6, 73.6, 73.6, 94.1, 128.7", \ + "69.4, 69.4, 69.4, 91.5, 129.9", \ + "53.4, 53.4, 53.4, 77.9, 120.7"); + } + fall_transition (inslew_load_5x5__106) { + values ("42.9, 42.9, 42.9, 60.3, 93.7", \ + "49.8, 49.8, 49.8, 67.5, 101.2", \ + "62.5, 62.5, 62.5, 80.6, 115.0", \ + "86.9, 86.9, 86.9, 105.6, 141.0", \ + "134.8, 134.8, 134.8, 153.8, 190.8"); + } + } + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + when : "b" ; + sdf_cond : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__106) { + values ("73.8, 73.8, 73.8, 98.2, 146.8", \ + "73.4, 73.4, 73.4, 98.9, 148.7", \ + "67.6, 67.6, 67.6, 95.3, 148.1", \ + "48.6, 48.6, 48.6, 79.6, 137.9", \ + "1.8, 1.8, 1.8, 36.4, 101.6"); + } + rise_transition (inslew_load_5x5__106) { + values ("131.7, 131.7, 131.7, 175.1, 263.1", \ + "151.7, 151.7, 151.7, 194.0, 280.0", \ + "190.0, 190.0, 190.0, 232.3, 317.6", \ + "265.5, 265.5, 265.5, 308.6, 393.5", \ + "413.8, 413.8, 413.8, 458.0, 544.9"); + } + cell_fall (inslew_load_5x5__106) { + values ("69.7, 69.7, 69.7, 87.7, 123.4", \ + "77.7, 77.7, 77.7, 97.3, 134.9", \ + "86.4, 86.4, 86.4, 108.6, 150.5", \ + "94.6, 94.6, 94.6, 120.0, 167.8", \ + "102.0, 102.0, 102.0, 130.5, 184.5"); + } + fall_transition (inslew_load_5x5__106) { + values ("88.0, 88.0, 88.0, 112.3, 161.8", \ + "106.4, 106.4, 106.4, 130.4, 178.6", \ + "142.1, 142.1, 142.1, 166.3, 214.3", \ + "211.2, 211.2, 211.2, 236.2, 285.2", \ + "347.0, 347.0, 347.0, 372.7, 423.3"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + when : "a" ; + sdf_cond : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__106) { + values ("71.3, 71.3, 71.3, 95.7, 144.3", \ + "72.2, 72.2, 72.2, 97.8, 147.7", \ + "69.5, 69.5, 69.5, 97.2, 149.8", \ + "57.7, 57.7, 57.7, 88.3, 146.0", \ + "27.0, 27.0, 27.0, 60.6, 124.3"); + } + rise_transition (inslew_load_5x5__106) { + values ("127.3, 127.3, 127.3, 170.7, 258.6", \ + "150.0, 150.0, 150.0, 192.3, 278.2", \ + "192.9, 192.9, 192.9, 235.3, 320.5", \ + "278.0, 278.0, 278.0, 320.9, 405.7", \ + "445.9, 445.9, 445.9, 489.6, 576.0"); + } + cell_fall (inslew_load_5x5__106) { + values ("37.1, 37.1, 37.1, 55.8, 91.9", \ + "41.1, 41.1, 41.1, 60.2, 98.4", \ + "45.2, 45.2, 45.2, 67.9, 108.8", \ + "48.8, 48.8, 48.8, 74.0, 120.8", \ + "52.5, 52.5, 52.5, 79.5, 131.0"); + } + fall_transition (inslew_load_5x5__106) { + values ("56.1, 56.1, 56.1, 80.2, 129.3", \ + "74.4, 74.4, 74.4, 96.9, 145.1", \ + "110.2, 110.2, 110.2, 134.3, 180.8", \ + "180.6, 180.6, 180.6, 205.3, 253.7", \ + "320.6, 320.6, 320.6, 345.6, 395.1"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + when : "!(b)" ; + rise_power (energy_inslew_load_5x5__106) { + values ("305.1, 305.1, 305.1, 365.0, 484.7", \ + "356.2, 356.2, 356.2, 416.0, 535.7", \ + "456.0, 456.0, 456.0, 515.9, 635.6", \ + "653.1, 653.1, 653.1, 712.9, 832.6", \ + "1044.8, 1044.8, 1044.8, 1104.7, 1224.4"); + } + fall_power (energy_inslew_load_5x5__106) { + values ("289.4, 289.4, 289.4, 349.2, 468.9", \ + "327.0, 327.0, 327.0, 386.9, 506.6", \ + "401.1, 401.1, 401.1, 461.0, 580.7", \ + "548.3, 548.3, 548.3, 608.2, 727.9", \ + "841.8, 841.8, 841.8, 901.6, 1021.3"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + when : "!(a)" ; + rise_power (energy_inslew_load_5x5__106) { + values ("262.5, 262.5, 262.5, 322.4, 442.1", \ + "308.8, 308.8, 308.8, 368.7, 488.4", \ + "399.7, 399.7, 399.7, 459.5, 579.2", \ + "579.4, 579.4, 579.4, 639.3, 759.0", \ + "937.1, 937.1, 937.1, 996.9, 1116.6"); + } + fall_power (energy_inslew_load_5x5__106) { + values ("254.5, 254.5, 254.5, 314.3, 434.0", \ + "293.2, 293.2, 293.2, 353.1, 472.8", \ + "369.5, 369.5, 369.5, 429.3, 549.0", \ + "520.9, 520.9, 520.9, 580.7, 700.4", \ + "822.6, 822.6, 822.6, 882.5, 1002.2"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + when : "b" ; + rise_power (energy_inslew_load_5x5__106) { + values ("244.4, 244.4, 244.4, 304.2, 423.9", \ + "272.1, 272.1, 272.1, 331.9, 451.6", \ + "327.4, 327.4, 327.4, 387.3, 507.0", \ + "438.2, 438.2, 438.2, 498.0, 617.7", \ + "659.7, 659.7, 659.7, 719.5, 839.2"); + } + fall_power (energy_inslew_load_5x5__106) { + values ("227.2, 227.2, 227.2, 287.0, 406.7", \ + "257.5, 257.5, 257.5, 317.3, 437.0", \ + "318.0, 318.0, 318.0, 377.8, 497.5", \ + "439.1, 439.1, 439.1, 498.9, 618.6", \ + "681.2, 681.2, 681.2, 741.0, 860.7"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + when : "a" ; + rise_power (energy_inslew_load_5x5__106) { + values ("236.0, 236.0, 236.0, 295.8, 415.5", \ + "269.0, 269.0, 269.0, 328.8, 448.5", \ + "334.9, 334.9, 334.9, 394.8, 514.5", \ + "466.8, 466.8, 466.8, 526.7, 646.4", \ + "730.6, 730.6, 730.6, 790.5, 910.2"); + } + fall_power (energy_inslew_load_5x5__106) { + values ("128.3, 128.3, 128.3, 188.1, 307.8", \ + "157.6, 157.6, 157.6, 217.4, 337.1", \ + "216.1, 216.1, 216.1, 276.0, 395.7", \ + "333.3, 333.3, 333.3, 393.1, 512.8", \ + "567.5, 567.5, 567.5, 627.4, 747.1"); + } + } + } + } + + cell (xor2v8x05) { + area : 0.0 ; + cell_leakage_power : 10 ; + leakage_power () { + when : "(b & a)" ; + value : 15 ; + } + leakage_power () { + when : "(a ^ b)" ; + value : 11 ; + } + leakage_power () { + when : "(!(b) & !(a))" ; + value : 4.9 ; + } + pin (b) { + direction : input ; + capacitance : 5.53 ; + } + pin (a) { + direction : input ; + capacitance : 2.96 ; + } + pin (z) { + function : "(a ^ b)" ; + direction : output ; + capacitance : 1.74 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + when : "!(b)" ; + sdf_cond : "!(b)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__107) { + values ("81.1, 81.1, 81.1, 92.3, 112.0", \ + "86.0, 86.0, 86.0, 97.4, 117.7", \ + "88.5, 88.5, 88.5, 100.2, 121.5", \ + "83.9, 83.9, 83.9, 96.1, 118.4", \ + "64.7, 64.7, 64.7, 77.3, 101.0"); + } + rise_transition (inslew_load_5x5__107) { + values ("64.4, 64.4, 64.4, 80.9, 113.2", \ + "73.9, 73.9, 73.9, 90.5, 122.9", \ + "92.0, 92.0, 92.0, 108.7, 141.5", \ + "126.7, 126.7, 126.7, 143.5, 176.6", \ + "194.0, 194.0, 194.0, 210.8, 244.2"); + } + cell_fall (inslew_load_5x5__107) { + values ("95.0, 95.0, 95.0, 105.9, 125.6", \ + "97.2, 97.2, 97.2, 108.3, 128.5", \ + "97.4, 97.4, 97.4, 108.9, 129.6", \ + "91.2, 91.2, 91.2, 103.1, 125.0", \ + "70.8, 70.8, 70.8, 83.2, 106.4"); + } + fall_transition (inslew_load_5x5__107) { + values ("61.0, 61.0, 61.0, 69.1, 84.3", \ + "69.5, 69.5, 69.5, 77.6, 93.0", \ + "86.3, 86.3, 86.3, 94.5, 110.2", \ + "119.8, 119.8, 119.8, 128.0, 144.1", \ + "185.7, 185.7, 185.7, 194.1, 210.5"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + when : "!(a)" ; + sdf_cond : "!(a)" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__107) { + values ("46.1, 46.1, 46.1, 56.3, 74.1", \ + "48.0, 48.0, 48.0, 58.6, 77.4", \ + "46.1, 46.1, 46.1, 57.4, 77.5", \ + "37.3, 37.3, 37.3, 49.1, 70.8", \ + "15.0, 15.0, 15.0, 27.5, 50.8"); + } + rise_transition (inslew_load_5x5__107) { + values ("41.1, 41.1, 41.1, 57.4, 89.1", \ + "51.0, 51.0, 51.0, 67.4, 99.4", \ + "69.0, 69.0, 69.0, 85.5, 117.9", \ + "103.1, 103.1, 103.1, 119.9, 152.7", \ + "169.8, 169.8, 169.8, 186.7, 220.0"); + } + cell_fall (inslew_load_5x5__107) { + values ("54.0, 54.0, 54.0, 64.2, 81.7", \ + "64.5, 64.5, 64.5, 75.2, 94.1", \ + "82.0, 82.0, 82.0, 93.3, 113.7", \ + "113.5, 113.5, 113.5, 125.5, 147.6", \ + "173.2, 173.2, 173.2, 185.7, 209.5"); + } + fall_transition (inslew_load_5x5__107) { + values ("38.1, 38.1, 38.1, 45.8, 60.3", \ + "52.0, 52.0, 52.0, 59.9, 74.9", \ + "77.5, 77.5, 77.5, 85.6, 101.2", \ + "127.5, 127.5, 127.5, 135.8, 151.9", \ + "226.9, 226.9, 226.9, 235.4, 251.9"); + } + } + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + when : "b" ; + sdf_cond : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__107) { + values ("128.1, 128.1, 128.1, 139.3, 159.2", \ + "138.6, 138.6, 138.6, 149.9, 170.1", \ + "151.9, 151.9, 151.9, 163.4, 184.3", \ + "169.3, 169.3, 169.3, 181.2, 202.9", \ + "195.6, 195.6, 195.6, 207.9, 230.7"); + } + rise_transition (inslew_load_5x5__107) { + values ("66.0, 66.0, 66.0, 82.5, 114.9", \ + "72.1, 72.1, 72.1, 88.6, 121.1", \ + "83.3, 83.3, 83.3, 100.0, 132.6", \ + "104.7, 104.7, 104.7, 121.4, 154.3", \ + "146.2, 146.2, 146.2, 163.0, 196.3"); + } + cell_fall (inslew_load_5x5__107) { + values ("122.0, 122.0, 122.0, 132.7, 151.4", \ + "127.4, 127.4, 127.4, 138.2, 157.2", \ + "130.6, 130.6, 130.6, 141.4, 161.0", \ + "128.2, 128.2, 128.2, 139.3, 159.5", \ + "114.4, 114.4, 114.4, 125.9, 146.8"); + } + fall_transition (inslew_load_5x5__107) { + values ("50.2, 50.2, 50.2, 58.1, 73.0", \ + "53.2, 53.2, 53.2, 61.2, 76.2", \ + "59.1, 59.1, 59.1, 67.2, 82.2", \ + "69.6, 69.6, 69.6, 77.7, 93.1", \ + "90.5, 90.5, 90.5, 98.7, 114.5"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + when : "a" ; + sdf_cond : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__107) { + values ("79.9, 79.9, 79.9, 90.3, 108.4", \ + "88.1, 88.1, 88.1, 98.7, 117.5", \ + "98.7, 98.7, 98.7, 109.8, 129.4", \ + "114.5, 114.5, 114.5, 126.0, 147.0", \ + "140.1, 140.1, 140.1, 152.2, 174.5"); + } + rise_transition (inslew_load_5x5__107) { + values ("44.8, 44.8, 44.8, 61.1, 92.9", \ + "51.2, 51.2, 51.2, 67.6, 99.6", \ + "62.7, 62.7, 62.7, 79.2, 111.5", \ + "84.4, 84.4, 84.4, 101.1, 133.7", \ + "126.3, 126.3, 126.3, 143.1, 176.2"); + } + cell_fall (inslew_load_5x5__107) { + values ("79.6, 79.6, 79.6, 89.6, 106.6", \ + "84.8, 84.8, 84.8, 95.1, 112.7", \ + "89.3, 89.3, 89.3, 99.9, 118.4", \ + "97.5, 97.5, 97.5, 108.5, 128.3", \ + "106.1, 106.1, 106.1, 117.7, 138.8"); + } + fall_transition (inslew_load_5x5__107) { + values ("34.9, 34.9, 34.9, 42.6, 56.9", \ + "39.6, 39.6, 39.6, 47.4, 61.9", \ + "47.1, 47.1, 47.1, 55.0, 69.8", \ + "63.8, 63.8, 63.8, 71.9, 87.1", \ + "94.9, 94.9, 94.9, 103.1, 118.9"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + when : "!(b)" ; + rise_power (energy_inslew_load_5x5__107) { + values ("252.4, 252.4, 252.4, 274.1, 317.6", \ + "283.5, 283.5, 283.5, 305.2, 348.7", \ + "345.1, 345.1, 345.1, 366.9, 410.4", \ + "467.1, 467.1, 467.1, 488.9, 532.4", \ + "709.6, 709.6, 709.6, 731.3, 774.8"); + } + fall_power (energy_inslew_load_5x5__107) { + values ("301.6, 301.6, 301.6, 323.3, 366.8", \ + "342.0, 342.0, 342.0, 363.7, 407.2", \ + "422.7, 422.7, 422.7, 444.4, 487.9", \ + "583.9, 583.9, 583.9, 605.7, 649.2", \ + "905.4, 905.4, 905.4, 927.1, 970.7"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + when : "!(a)" ; + rise_power (energy_inslew_load_5x5__107) { + values ("126.8, 126.8, 126.8, 148.5, 192.0", \ + "153.4, 153.4, 153.4, 175.1, 218.6", \ + "205.5, 205.5, 205.5, 227.3, 270.8", \ + "308.9, 308.9, 308.9, 330.7, 374.2", \ + "515.0, 515.0, 515.0, 536.7, 580.2"); + } + fall_power (energy_inslew_load_5x5__107) { + values ("154.9, 154.9, 154.9, 176.6, 220.1", \ + "202.4, 202.4, 202.4, 224.2, 267.7", \ + "294.7, 294.7, 294.7, 316.4, 360.0", \ + "478.4, 478.4, 478.4, 500.1, 543.6", \ + "845.1, 845.1, 845.1, 866.8, 910.3"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + when : "b" ; + rise_power (energy_inslew_load_5x5__107) { + values ("373.3, 373.3, 373.3, 395.1, 438.6", \ + "422.1, 422.1, 422.1, 443.8, 487.3", \ + "517.3, 517.3, 517.3, 539.1, 582.6", \ + "705.8, 705.8, 705.8, 727.6, 771.1", \ + "1081.0, 1081.0, 1081.0, 1102.7, 1146.2"); + } + fall_power (energy_inslew_load_5x5__107) { + values ("368.6, 368.6, 368.6, 390.3, 433.8", \ + "405.0, 405.0, 405.0, 426.8, 470.3", \ + "476.3, 476.3, 476.3, 498.0, 541.6", \ + "615.8, 615.8, 615.8, 637.5, 681.0", \ + "893.0, 893.0, 893.0, 914.8, 958.3"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + when : "a" ; + rise_power (energy_inslew_load_5x5__107) { + values ("216.4, 216.4, 216.4, 238.1, 281.6", \ + "262.0, 262.0, 262.0, 283.8, 327.3", \ + "351.5, 351.5, 351.5, 373.3, 416.8", \ + "529.2, 529.2, 529.2, 551.0, 594.5", \ + "883.5, 883.5, 883.5, 905.2, 948.7"); + } + fall_power (energy_inslew_load_5x5__107) { + values ("213.6, 213.6, 213.6, 235.4, 278.9", \ + "251.6, 251.6, 251.6, 273.4, 316.9", \ + "324.2, 324.2, 324.2, 346.0, 389.5", \ + "471.2, 471.2, 471.2, 493.0, 536.5", \ + "761.6, 761.6, 761.6, 783.3, 826.9"); + } + } + } + } + + cell (xor3v0x05) { + area : 0.0 ; + cell_leakage_power : 4.5e+03 ; + leakage_power () { + when : "(a & b & c)" ; + value : 6.5 ; + } + leakage_power () { + when : "(a & b & !(c))" ; + value : 1.1e+04 ; + } + leakage_power () { + when : "(a & !(b) & c)" ; + value : 6.8e+03 ; + } + leakage_power () { + when : "(!(a) & b & c)" ; + value : 4.4e+03 ; + } + leakage_power () { + when : "(!(a) & !(b) & !(c))" ; + value : 6.2 ; + } + pin (c) { + direction : input ; + capacitance : 13.51 ; + } + pin (b) { + direction : input ; + capacitance : 12.04 ; + } + pin (a) { + direction : input ; + capacitance : 10.53 ; + } + pin (z) { + direction : inout ; + capacitance : 78.58 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__108) { + values ("414.6, 414.6, 414.6, 952.8, 2032.9", \ + "412.6, 412.6, 412.6, 950.8, 2030.8", \ + "396.1, 396.1, 396.1, 934.5, 2014.3", \ + "343.3, 343.3, 343.3, 881.8, 1961.4", \ + "208.1, 208.1, 208.1, 746.9, 1826.3"); + } + rise_transition (inslew_load_5x5__108) { + values ("509.1, 509.1, 509.1, 1392.2, 3171.4", \ + "519.3, 519.3, 519.3, 1402.2, 3181.1", \ + "535.2, 535.2, 535.2, 1417.8, 3196.5", \ + "558.9, 558.9, 558.9, 1441.2, 3219.4", \ + "593.5, 593.5, 593.5, 1475.4, 3253.1"); + } + cell_fall (inslew_load_5x5__108) { + values ("1051.8, 1051.8, 1051.8, 1307.0, 1747.0", \ + "1095.4, 1095.4, 1095.4, 1353.5, 1797.6", \ + "1181.2, 1181.2, 1181.2, 1444.7, 1896.5", \ + "1347.4, 1347.4, 1347.4, 1619.2, 2085.6", \ + "1671.3, 1671.3, 1671.3, 1955.0, 2445.8"); + } + fall_transition (inslew_load_5x5__108) { + values ("361.8, 361.8, 361.8, 657.5, 1247.9", \ + "385.0, 385.0, 385.0, 681.1, 1270.8", \ + "430.9, 430.9, 430.9, 727.9, 1316.9", \ + "522.4, 522.4, 522.4, 821.0, 1410.4", \ + "705.1, 705.1, 705.1, 1006.1, 1595.3"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__108) { + values ("408.7, 408.7, 408.7, 946.8, 2027.1", \ + "417.7, 417.7, 417.7, 956.0, 2036.0", \ + "429.4, 429.4, 429.4, 967.9, 2047.6", \ + "446.2, 446.2, 446.2, 985.2, 2064.4", \ + "474.1, 474.1, 474.1, 1014.0, 2092.8"); + } + rise_transition (inslew_load_5x5__108) { + values ("496.8, 496.8, 496.8, 1380.1, 3159.5", \ + "517.0, 517.0, 517.0, 1399.9, 3179.0", \ + "554.8, 554.8, 554.8, 1437.1, 3215.4", \ + "626.7, 626.7, 626.7, 1508.3, 3285.5", \ + "766.8, 766.8, 766.8, 1647.7, 3423.2"); + } + cell_fall (inslew_load_5x5__108) { + values ("663.4, 663.4, 663.4, 902.9, 1326.3", \ + "695.0, 695.0, 695.0, 938.5, 1365.5", \ + "737.6, 737.6, 737.6, 987.1, 1420.6", \ + "810.1, 810.1, 810.1, 1069.0, 1514.3", \ + "941.0, 941.0, 941.0, 1213.4, 1681.0"); + } + fall_transition (inslew_load_5x5__108) { + values ("263.5, 263.5, 263.5, 558.3, 1155.0", \ + "285.1, 285.1, 285.1, 580.4, 1174.6", \ + "321.8, 321.8, 321.8, 616.8, 1209.1", \ + "391.7, 391.7, 391.7, 688.0, 1277.5", \ + "529.8, 529.8, 529.8, 828.5, 1418.0"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__108) { + values ("541.3, 541.3, 541.3, 1080.2, 2159.5", \ + "549.6, 549.6, 549.6, 1088.6, 2167.8", \ + "561.1, 561.1, 561.1, 1100.3, 2179.4", \ + "578.9, 578.9, 578.9, 1118.5, 2197.4", \ + "611.5, 611.5, 611.5, 1151.7, 2230.4"); + } + rise_transition (inslew_load_5x5__108) { + values ("605.4, 605.4, 605.4, 1487.2, 3264.7", \ + "624.0, 624.0, 624.0, 1505.6, 3282.8", \ + "658.6, 658.6, 658.6, 1540.0, 3316.7", \ + "725.5, 725.5, 725.5, 1606.5, 3382.4", \ + "857.0, 857.0, 857.0, 1737.7, 3512.3"); + } + cell_fall (inslew_load_5x5__108) { + values ("942.7, 942.7, 942.7, 1191.8, 1624.8", \ + "950.7, 950.7, 950.7, 1200.1, 1633.5", \ + "957.7, 957.7, 957.7, 1207.6, 1641.6", \ + "959.5, 959.5, 959.5, 1210.2, 1645.2", \ + "944.6, 944.6, 944.6, 1196.7, 1632.8"); + } + fall_transition (inslew_load_5x5__108) { + values ("319.3, 319.3, 319.3, 614.1, 1206.7", \ + "321.3, 321.3, 321.3, 616.2, 1208.6", \ + "324.6, 324.6, 324.6, 619.6, 1211.8", \ + "330.2, 330.2, 330.2, 625.2, 1217.1", \ + "339.1, 339.1, 339.1, 634.3, 1225.7"); + } + } + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__108) { + values ("545.5, 545.5, 545.5, 1084.6, 2163.8", \ + "578.5, 578.5, 578.5, 1118.0, 2196.9", \ + "644.5, 644.5, 644.5, 1184.6, 2263.4", \ + "776.4, 776.4, 776.4, 1317.1, 2396.0", \ + "1040.5, 1040.5, 1040.5, 1581.4, 2661.1"); + } + rise_transition (inslew_load_5x5__108) { + values ("638.3, 638.3, 638.3, 1519.8, 3296.8", \ + "702.6, 702.6, 702.6, 1583.7, 3359.9", \ + "830.5, 830.5, 830.5, 1711.3, 3486.1", \ + "1085.7, 1085.7, 1085.7, 1965.7, 3738.8", \ + "1595.6, 1595.6, 1595.6, 2473.6, 4244.7"); + } + cell_fall (inslew_load_5x5__108) { + values ("896.5, 896.5, 896.5, 1145.0, 1577.4", \ + "896.6, 896.6, 896.6, 1145.6, 1578.7", \ + "883.8, 883.8, 883.8, 1133.7, 1567.8", \ + "835.5, 835.5, 835.5, 1086.6, 1521.7", \ + "705.8, 705.8, 705.8, 958.8, 1396.1"); + } + fall_transition (inslew_load_5x5__108) { + values ("315.4, 315.4, 315.4, 610.2, 1203.0", \ + "319.0, 319.0, 319.0, 613.9, 1206.5", \ + "324.8, 324.8, 324.8, 619.7, 1211.9", \ + "333.3, 333.3, 333.3, 628.4, 1220.2", \ + "345.7, 345.7, 345.7, 641.1, 1232.2"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__108) { + values ("214.8, 214.8, 214.8, 719.4, 1741.9", \ + "231.0, 231.0, 231.0, 735.9, 1751.9", \ + "251.8, 251.8, 251.8, 758.2, 1772.0", \ + "290.3, 290.3, 290.3, 798.9, 1812.1", \ + "367.9, 367.9, 367.9, 877.7, 1892.0"); + } + rise_transition (inslew_load_5x5__108) { + values ("365.1, 365.1, 365.1, 1236.9, 3003.0", \ + "425.0, 425.0, 425.0, 1295.2, 3050.3", \ + "527.0, 527.0, 527.0, 1394.2, 3144.8", \ + "721.4, 721.4, 721.4, 1587.6, 3334.1", \ + "1106.5, 1106.5, 1106.5, 1970.7, 3714.1"); + } + cell_fall (inslew_load_5x5__108) { + values ("888.3, 888.3, 888.3, 1136.1, 1567.7", \ + "901.5, 901.5, 901.5, 1150.4, 1583.3", \ + "920.1, 920.1, 920.1, 1171.1, 1606.4", \ + "950.4, 950.4, 950.4, 1205.0, 1644.4", \ + "1000.4, 1000.4, 1000.4, 1261.3, 1709.4"); + } + fall_transition (inslew_load_5x5__108) { + values ("311.0, 311.0, 311.0, 605.7, 1198.8", \ + "318.2, 318.2, 318.2, 613.1, 1205.7", \ + "331.9, 331.9, 331.9, 627.0, 1218.7", \ + "357.7, 357.7, 357.7, 653.3, 1243.9", \ + "408.0, 408.0, 408.0, 704.6, 1293.8"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__108) { + values ("458.6, 458.6, 458.6, 996.8, 2076.8", \ + "465.0, 465.0, 465.0, 1003.3, 2083.3", \ + "470.1, 470.1, 470.1, 1008.4, 2088.3", \ + "469.2, 469.2, 469.2, 1007.7, 2087.4", \ + "449.8, 449.8, 449.8, 988.4, 2067.9"); + } + rise_transition (inslew_load_5x5__108) { + values ("519.9, 519.9, 519.9, 1402.8, 3181.7", \ + "525.4, 525.4, 525.4, 1408.2, 3187.0", \ + "534.7, 534.7, 534.7, 1417.3, 3196.0", \ + "550.2, 550.2, 550.2, 1432.6, 3211.0", \ + "574.9, 574.9, 574.9, 1457.0, 3234.9"); + } + cell_fall (inslew_load_5x5__108) { + values ("1041.3, 1041.3, 1041.3, 1294.9, 1732.9", \ + "1053.4, 1053.4, 1053.4, 1307.9, 1747.1", \ + "1070.5, 1070.5, 1070.5, 1326.7, 1768.0", \ + "1099.1, 1099.1, 1099.1, 1358.3, 1803.8", \ + "1151.8, 1151.8, 1151.8, 1416.3, 1869.7"); + } + fall_transition (inslew_load_5x5__108) { + values ("350.0, 350.0, 350.0, 645.5, 1236.4", \ + "356.7, 356.7, 356.7, 652.3, 1242.9", \ + "369.2, 369.2, 369.2, 665.0, 1255.1", \ + "393.2, 393.2, 393.2, 689.5, 1279.0", \ + "440.4, 440.4, 440.4, 737.5, 1326.5"); + } + } + timing (maxd_z_z_clear_negative_unate) { + related_pin : "z" ; + timing_sense : negative_unate ; + timing_type : clear ; + cell_fall (inslew_load_5x5__108) { + values ("285.9, 285.9, 285.9, 498.9, 908.2", \ + "332.9, 332.9, 332.9, 550.6, 960.8", \ + "391.7, 391.7, 391.7, 618.4, 1031.8", \ + "457.3, 457.3, 457.3, 699.2, 1124.7", \ + "531.6, 531.6, 531.6, 793.9, 1243.9"); + } + fall_transition (inslew_load_5x5__108) { + values ("149.0, 149.0, 149.0, 446.7, 1058.7", \ + "167.3, 167.3, 167.3, 463.3, 1072.6", \ + "203.8, 203.8, 203.8, 498.1, 1101.3", \ + "276.1, 276.1, 276.1, 571.2, 1166.3", \ + "419.9, 419.9, 419.9, 716.7, 1305.8"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__108) { + values ("934.1, 934.1, 934.1, 1916.4, 3881.0", \ + "944.9, 944.9, 944.9, 1927.2, 3891.8", \ + "962.0, 962.0, 962.0, 1944.3, 3908.8", \ + "987.4, 987.4, 987.4, 1969.7, 3934.3", \ + "1024.7, 1024.7, 1024.7, 2007.0, 3971.6"); + } + fall_power (energy_inslew_load_5x5__108) { + values ("2383.5, 2383.5, 2383.5, 3365.8, 5330.4", \ + "2508.5, 2508.5, 2508.5, 3490.8, 5455.4", \ + "2758.1, 2758.1, 2758.1, 3740.4, 5704.9", \ + "3256.4, 3256.4, 3256.4, 4238.7, 6203.3", \ + "4252.8, 4252.8, 4252.8, 5235.1, 7199.7"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__108) { + values ("963.9, 963.9, 963.9, 1946.1, 3910.7", \ + "1028.2, 1028.2, 1028.2, 2010.5, 3975.1", \ + "1154.3, 1154.3, 1154.3, 2136.6, 4101.2", \ + "1403.4, 1403.4, 1403.4, 2385.7, 4350.3", \ + "1898.9, 1898.9, 1898.9, 2881.2, 4845.8"); + } + fall_power (energy_inslew_load_5x5__108) { + values ("1501.0, 1501.0, 1501.0, 2483.3, 4447.9", \ + "1605.5, 1605.5, 1605.5, 2587.8, 4552.4", \ + "1799.5, 1799.5, 1799.5, 2781.7, 4746.3", \ + "2179.0, 2179.0, 2179.0, 3161.3, 5125.9", \ + "2935.0, 2935.0, 2935.0, 3917.3, 5881.9"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__108) { + values ("1223.9, 1223.9, 1223.9, 2206.2, 4170.8", \ + "1285.9, 1285.9, 1285.9, 2268.1, 4232.7", \ + "1407.2, 1407.2, 1407.2, 2389.5, 4354.1", \ + "1647.5, 1647.5, 1647.5, 2629.8, 4594.3", \ + "2126.2, 2126.2, 2126.2, 3108.5, 5073.1"); + } + fall_power (energy_inslew_load_5x5__108) { + values ("2406.8, 2406.8, 2406.8, 3389.1, 5353.7", \ + "2487.4, 2487.4, 2487.4, 3469.7, 5434.3", \ + "2645.1, 2645.1, 2645.1, 3627.4, 5592.0", \ + "2954.8, 2954.8, 2954.8, 3937.1, 5901.7", \ + "3562.0, 3562.0, 3562.0, 4544.3, 6508.9"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + rise_power (energy_inslew_load_5x5__108) { + values ("1073.2, 1073.2, 1073.2, 2055.5, 4020.1", \ + "1143.1, 1143.1, 1143.1, 2125.4, 4090.0", \ + "1283.0, 1283.0, 1283.0, 2265.3, 4229.9", \ + "1562.7, 1562.7, 1562.7, 2545.0, 4509.6", \ + "2122.1, 2122.1, 2122.1, 3104.4, 5069.0"); + } + fall_power (energy_inslew_load_5x5__108) { + values ("2133.7, 2133.7, 2133.7, 3116.0, 5080.6", \ + "2153.2, 2153.2, 2153.2, 3135.5, 5100.1", \ + "2183.8, 2183.8, 2183.8, 3166.1, 5130.7", \ + "2229.6, 2229.6, 2229.6, 3211.9, 5176.5", \ + "2296.6, 2296.6, 2296.6, 3278.9, 5243.5"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + rise_power (energy_inslew_load_5x5__108) { + values ("424.8, 424.8, 424.8, 1407.1, 3371.7", \ + "478.0, 478.0, 478.0, 1460.3, 3424.9", \ + "584.5, 584.5, 584.5, 1566.8, 3531.4", \ + "797.5, 797.5, 797.5, 1779.8, 3744.4", \ + "1223.5, 1223.5, 1223.5, 2205.8, 4170.4"); + } + fall_power (energy_inslew_load_5x5__108) { + values ("2152.9, 2152.9, 2152.9, 3135.2, 5099.8", \ + "2234.5, 2234.5, 2234.5, 3216.8, 5181.4", \ + "2393.1, 2393.1, 2393.1, 3375.4, 5340.0", \ + "2703.8, 2703.8, 2703.8, 3686.1, 5650.7", \ + "3319.3, 3319.3, 3319.3, 4301.6, 6266.2"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + rise_power (energy_inslew_load_5x5__108) { + values ("1198.1, 1198.1, 1198.1, 2180.4, 4145.0", \ + "1273.9, 1273.9, 1273.9, 2256.2, 4220.8", \ + "1423.7, 1423.7, 1423.7, 2406.0, 4370.5", \ + "1720.0, 1720.0, 1720.0, 2702.3, 4666.9", \ + "2306.0, 2306.0, 2306.0, 3288.3, 5252.9"); + } + fall_power (energy_inslew_load_5x5__108) { + values ("2505.9, 2505.9, 2505.9, 3488.2, 5452.8", \ + "2583.8, 2583.8, 2583.8, 3566.1, 5530.7", \ + "2734.9, 2734.9, 2734.9, 3717.2, 5681.8", \ + "3032.4, 3032.4, 3032.4, 4014.7, 5979.3", \ + "3623.9, 3623.9, 3623.9, 4606.2, 6570.8"); + } + } + internal_power (energy_neg_z_z) { + related_pin : "z" ; + fall_power (energy_inslew_load_5x5__108) { + values ("806.1, 806.1, 806.1, 1788.4, 3753.0", \ + "849.0, 849.0, 849.0, 1831.3, 3795.9", \ + "934.7, 934.7, 934.7, 1917.0, 3881.6", \ + "1106.0, 1106.0, 1106.0, 2088.3, 4052.9", \ + "1448.8, 1448.8, 1448.8, 2431.1, 4395.7"); + } + } + } + } + + cell (xor3v1x05) { + area : 0.0 ; + cell_leakage_power : 2 ; + leakage_power () { + when : "(c & b & a)" ; + value : 2.4 ; + } + leakage_power () { + when : "(!(c) & b & a)" ; + value : 2.8 ; + } + leakage_power () { + when : "((a ^ b) & c)" ; + value : 1.9 ; + } + leakage_power () { + when : "((a ^ b) & !(c))" ; + value : 1.1 ; + } + leakage_power () { + when : "(c & !(b) & !(a))" ; + value : 1.7 ; + } + leakage_power () { + when : "(!(c) & !(b) & !(a))" ; + value : 2.1 ; + } + pin (c) { + direction : input ; + capacitance : 4.58 ; + } + pin (b) { + direction : input ; + capacitance : 5.44 ; + } + pin (a) { + direction : input ; + capacitance : 3.73 ; + } + pin (z) { + function : "(a ^ b ^ c)" ; + direction : output ; + capacitance : 3.50 ; + timing (maxd_z_a_positive_unate) { + related_pin : "a" ; + when : "!((b ^ c))" ; + sdf_cond : "!((b ^ c))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__109) { + values ("191.4, 191.4, 191.4, 216.3, 264.0", \ + "205.3, 205.3, 205.3, 230.3, 278.3", \ + "222.2, 222.2, 222.2, 247.4, 295.8", \ + "246.5, 246.5, 246.5, 272.0, 320.8", \ + "286.5, 286.5, 286.5, 311.6, 361.3"); + } + rise_transition (inslew_load_5x5__109) { + values ("101.1, 101.1, 101.1, 143.0, 228.4", \ + "106.2, 106.2, 106.2, 148.3, 233.4", \ + "115.0, 115.0, 115.0, 157.1, 241.7", \ + "131.3, 131.3, 131.3, 173.4, 257.4", \ + "163.0, 163.0, 163.0, 202.8, 286.7"); + } + cell_fall (inslew_load_5x5__109) { + values ("126.0, 126.0, 126.0, 139.9, 166.4", \ + "128.4, 128.4, 128.4, 142.8, 170.1", \ + "128.3, 128.3, 128.3, 143.6, 172.4", \ + "120.7, 120.7, 120.7, 137.3, 168.5", \ + "96.0, 96.0, 96.0, 114.1, 148.8"); + } + fall_transition (inslew_load_5x5__109) { + values ("94.9, 94.9, 94.9, 110.8, 142.3", \ + "102.7, 102.7, 102.7, 118.7, 150.2", \ + "117.5, 117.5, 117.5, 133.7, 165.5", \ + "146.7, 146.7, 146.7, 163.2, 195.5", \ + "203.8, 203.8, 203.8, 220.7, 253.7"); + } + } + timing (maxd_z_b_positive_unate) { + related_pin : "b" ; + when : "!((a ^ c))" ; + sdf_cond : "!((a ^ c))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__109) { + values ("138.1, 138.1, 138.1, 162.2, 209.3", \ + "146.0, 146.0, 146.0, 170.6, 217.7", \ + "152.7, 152.7, 152.7, 177.2, 224.8", \ + "159.2, 159.2, 159.2, 184.3, 232.3", \ + "165.0, 165.0, 165.0, 190.4, 239.1"); + } + rise_transition (inslew_load_5x5__109) { + values ("84.2, 84.2, 84.2, 125.8, 211.8", \ + "89.2, 89.2, 89.2, 131.1, 216.8", \ + "95.6, 95.6, 95.6, 137.2, 222.8", \ + "106.8, 106.8, 106.8, 149.0, 234.1", \ + "127.7, 127.7, 127.7, 169.8, 253.8"); + } + cell_fall (inslew_load_5x5__109) { + values ("147.2, 147.2, 147.2, 162.1, 190.1", \ + "156.3, 156.3, 156.3, 171.7, 201.0", \ + "170.7, 170.7, 170.7, 187.3, 218.5", \ + "195.8, 195.8, 195.8, 213.8, 248.1", \ + "241.4, 241.4, 241.4, 261.2, 298.3"); + } + fall_transition (inslew_load_5x5__109) { + values ("109.3, 109.3, 109.3, 125.4, 157.0", \ + "122.1, 122.1, 122.1, 138.4, 170.2", \ + "147.1, 147.1, 147.1, 163.6, 195.9", \ + "196.8, 196.8, 196.8, 213.7, 246.6", \ + "294.0, 294.0, 294.0, 311.3, 345.1"); + } + } + timing (maxd_z_c_positive_unate) { + related_pin : "c" ; + when : "!((a ^ b))" ; + sdf_cond : "!((a ^ b))" ; + timing_sense : positive_unate ; + cell_rise (inslew_load_5x5__109) { + values ("50.1, 50.1, 50.1, 67.7, 104.0", \ + "54.8, 54.8, 54.8, 73.1, 110.3", \ + "58.0, 58.0, 58.0, 78.1, 116.7", \ + "60.2, 60.2, 60.2, 82.3, 120.7", \ + "60.6, 60.6, 60.6, 84.6, 129.0"); + } + rise_transition (inslew_load_5x5__109) { + values ("46.5, 46.5, 46.5, 75.6, 140.0", \ + "57.6, 57.6, 57.6, 87.2, 151.6", \ + "75.7, 75.7, 75.7, 106.5, 170.7", \ + "110.4, 110.4, 110.4, 142.0, 201.4", \ + "178.3, 178.3, 178.3, 210.8, 274.6"); + } + cell_fall (inslew_load_5x5__109) { + values ("77.1, 77.1, 77.1, 95.9, 128.6", \ + "86.7, 86.7, 86.7, 106.4, 140.8", \ + "99.4, 99.4, 99.4, 120.3, 157.3", \ + "118.3, 118.3, 118.3, 140.8, 181.0", \ + "151.3, 151.3, 151.3, 174.8, 218.7"); + } + fall_transition (inslew_load_5x5__109) { + values ("52.7, 52.7, 52.7, 72.6, 111.5", \ + "63.8, 63.8, 63.8, 83.8, 122.9", \ + "84.3, 84.3, 84.3, 104.7, 144.3", \ + "124.1, 124.1, 124.1, 144.8, 185.2", \ + "202.1, 202.1, 202.1, 223.3, 264.5"); + } + } + timing (maxd_z_a_negative_unate) { + related_pin : "a" ; + when : "(b ^ c)" ; + sdf_cond : "(b ^ c)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__109) { + values ("167.7, 167.7, 167.7, 192.8, 240.9", \ + "173.3, 173.3, 173.3, 198.5, 246.9", \ + "179.6, 179.6, 179.6, 205.1, 253.8", \ + "184.6, 184.6, 184.6, 209.6, 259.2", \ + "185.7, 185.7, 185.7, 212.1, 262.4"); + } + rise_transition (inslew_load_5x5__109) { + values ("108.2, 108.2, 108.2, 150.4, 235.4", \ + "115.5, 115.5, 115.5, 157.6, 242.1", \ + "129.6, 129.6, 129.6, 171.7, 255.7", \ + "157.1, 157.1, 157.1, 196.8, 280.8", \ + "210.0, 210.0, 210.0, 250.8, 332.3"); + } + cell_fall (inslew_load_5x5__109) { + values ("152.8, 152.8, 152.8, 166.2, 191.6", \ + "164.4, 164.4, 164.4, 178.2, 204.4", \ + "177.5, 177.5, 177.5, 191.9, 219.2", \ + "194.5, 194.5, 194.5, 209.9, 238.9", \ + "219.7, 219.7, 219.7, 236.6, 268.2"); + } + fall_transition (inslew_load_5x5__109) { + values ("87.1, 87.1, 87.1, 102.9, 134.3", \ + "92.8, 92.8, 92.8, 108.7, 140.1", \ + "102.1, 102.1, 102.1, 118.1, 149.6", \ + "119.4, 119.4, 119.4, 135.7, 167.5", \ + "153.2, 153.2, 153.2, 169.7, 202.1"); + } + } + timing (maxd_z_b_negative_unate) { + related_pin : "b" ; + when : "(a ^ c)" ; + sdf_cond : "(a ^ c)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__109) { + values ("195.0, 195.0, 195.0, 220.3, 269.0", \ + "209.5, 209.5, 209.5, 235.0, 284.0", \ + "234.8, 234.8, 234.8, 259.7, 309.3", \ + "282.3, 282.3, 282.3, 308.5, 358.8", \ + "371.9, 371.9, 371.9, 399.7, 451.9"); + } + rise_transition (inslew_load_5x5__109) { + values ("121.7, 121.7, 121.7, 163.8, 248.1", \ + "133.9, 133.9, 133.9, 176.0, 259.9", \ + "157.4, 157.4, 157.4, 197.1, 281.1", \ + "203.5, 203.5, 203.5, 244.0, 327.2", \ + "293.3, 293.3, 293.3, 335.0, 416.8"); + } + cell_fall (inslew_load_5x5__109) { + values ("106.6, 106.6, 106.6, 118.6, 142.1", \ + "112.4, 112.4, 112.4, 124.8, 148.8", \ + "116.4, 116.4, 116.4, 129.4, 154.2", \ + "118.1, 118.1, 118.1, 131.9, 158.2", \ + "114.5, 114.5, 114.5, 129.7, 158.4"); + } + fall_transition (inslew_load_5x5__109) { + values ("71.1, 71.1, 71.1, 87.0, 118.7", \ + "75.5, 75.5, 75.5, 91.3, 122.9", \ + "81.9, 81.9, 81.9, 97.7, 129.3", \ + "93.5, 93.5, 93.5, 109.4, 140.8", \ + "115.6, 115.6, 115.6, 131.8, 163.5"); + } + } + timing (maxd_z_c_negative_unate) { + related_pin : "c" ; + when : "(a ^ b)" ; + sdf_cond : "(a ^ b)" ; + timing_sense : negative_unate ; + cell_rise (inslew_load_5x5__109) { + values ("79.4, 79.4, 79.4, 102.4, 148.4", \ + "86.5, 86.5, 86.5, 109.9, 156.3", \ + "98.6, 98.6, 98.6, 122.6, 170.2", \ + "121.2, 121.2, 121.2, 146.0, 194.7", \ + "164.7, 164.7, 164.7, 190.2, 240.5"); + } + rise_transition (inslew_load_5x5__109) { + values ("153.5, 153.5, 153.5, 195.3, 279.5", \ + "191.0, 191.0, 191.0, 232.3, 315.6", \ + "264.8, 264.8, 264.8, 305.3, 387.2", \ + "413.4, 413.4, 413.4, 453.3, 533.5", \ + "705.9, 705.9, 705.9, 746.1, 830.2"); + } + cell_fall (inslew_load_5x5__109) { + values ("20.9, 20.9, 20.9, 33.4, 57.8", \ + "22.9, 22.9, 22.9, 38.0, 64.4", \ + "23.9, 23.9, 23.9, 41.0, 71.8", \ + "23.4, 23.4, 23.4, 42.1, 76.7", \ + "20.8, 20.8, 20.8, 40.5, 78.1"); + } + fall_transition (inslew_load_5x5__109) { + values ("35.8, 35.8, 35.8, 50.4, 81.7", \ + "53.7, 53.7, 53.7, 69.6, 100.0", \ + "88.1, 88.1, 88.1, 104.6, 136.6", \ + "155.9, 155.9, 155.9, 172.8, 205.9", \ + "290.6, 290.6, 290.6, 307.9, 342.0"); + } + } + internal_power (energy_pos_z_a) { + related_pin : "a" ; + when : "!((b ^ c))" ; + rise_power (energy_inslew_load_5x5__109) { + values ("600.5, 600.5, 600.5, 644.3, 731.8", \ + "664.6, 664.6, 664.6, 708.4, 795.9", \ + "785.6, 785.6, 785.6, 829.3, 916.8", \ + "1022.8, 1022.8, 1022.8, 1066.6, 1154.1", \ + "1493.9, 1493.9, 1493.9, 1537.6, 1625.2"); + } + fall_power (energy_inslew_load_5x5__109) { + values ("528.6, 528.6, 528.6, 572.3, 659.9", \ + "587.4, 587.4, 587.4, 631.1, 718.7", \ + "704.1, 704.1, 704.1, 747.9, 835.4", \ + "937.4, 937.4, 937.4, 981.2, 1068.7", \ + "1402.9, 1402.9, 1402.9, 1446.7, 1534.2"); + } + } + internal_power (energy_pos_z_b) { + related_pin : "b" ; + when : "!((a ^ c))" ; + rise_power (energy_inslew_load_5x5__109) { + values ("456.8, 456.8, 456.8, 500.5, 588.1", \ + "513.4, 513.4, 513.4, 557.2, 644.7", \ + "620.0, 620.0, 620.0, 663.8, 751.3", \ + "829.2, 829.2, 829.2, 873.0, 960.5", \ + "1245.1, 1245.1, 1245.1, 1288.9, 1376.4"); + } + fall_power (energy_inslew_load_5x5__109) { + values ("488.6, 488.6, 488.6, 532.4, 619.9", \ + "557.4, 557.4, 557.4, 601.1, 688.6", \ + "694.2, 694.2, 694.2, 737.9, 825.4", \ + "968.4, 968.4, 968.4, 1012.2, 1099.7", \ + "1514.6, 1514.6, 1514.6, 1558.4, 1645.9"); + } + } + internal_power (energy_pos_z_c) { + related_pin : "c" ; + when : "!((a ^ b))" ; + rise_power (energy_inslew_load_5x5__109) { + values ("168.0, 168.0, 168.0, 211.8, 299.3", \ + "206.0, 206.0, 206.0, 249.8, 337.3", \ + "281.0, 281.0, 281.0, 324.8, 412.3", \ + "430.2, 430.2, 430.2, 474.0, 561.5", \ + "728.0, 728.0, 728.0, 771.7, 859.3"); + } + fall_power (energy_inslew_load_5x5__109) { + values ("236.2, 236.2, 236.2, 280.0, 367.5", \ + "284.3, 284.3, 284.3, 328.1, 415.6", \ + "379.3, 379.3, 379.3, 423.0, 510.6", \ + "568.1, 568.1, 568.1, 611.9, 699.4", \ + "944.9, 944.9, 944.9, 988.7, 1076.2"); + } + } + internal_power (energy_neg_z_a) { + related_pin : "a" ; + when : "(b ^ c)" ; + rise_power (energy_inslew_load_5x5__109) { + values ("576.9, 576.9, 576.9, 620.7, 708.2", \ + "641.4, 641.4, 641.4, 685.2, 772.7", \ + "769.2, 769.2, 769.2, 813.0, 900.5", \ + "1024.3, 1024.3, 1024.3, 1068.1, 1155.6", \ + "1532.3, 1532.3, 1532.3, 1576.0, 1663.6"); + } + fall_power (energy_inslew_load_5x5__109) { + values ("558.0, 558.0, 558.0, 601.8, 689.3", \ + "617.9, 617.9, 617.9, 661.6, 749.1", \ + "731.9, 731.9, 731.9, 775.7, 863.2", \ + "956.3, 956.3, 956.3, 1000.1, 1087.6", \ + "1402.2, 1402.2, 1402.2, 1446.0, 1533.5"); + } + } + internal_power (energy_neg_z_b) { + related_pin : "b" ; + when : "(a ^ c)" ; + rise_power (energy_inslew_load_5x5__109) { + values ("547.6, 547.6, 547.6, 591.3, 678.9", \ + "625.9, 625.9, 625.9, 669.7, 757.2", \ + "781.3, 781.3, 781.3, 825.1, 912.6", \ + "1092.5, 1092.5, 1092.5, 1136.3, 1223.8", \ + "1711.4, 1711.4, 1711.4, 1755.1, 1842.7"); + } + fall_power (energy_inslew_load_5x5__109) { + values ("426.3, 426.3, 426.3, 470.1, 557.6", \ + "479.7, 479.7, 479.7, 523.4, 610.9", \ + "581.4, 581.4, 581.4, 625.1, 712.7", \ + "781.9, 781.9, 781.9, 825.7, 913.2", \ + "1181.4, 1181.4, 1181.4, 1225.2, 1312.7"); + } + } + internal_power (energy_neg_z_c) { + related_pin : "c" ; + when : "(a ^ b)" ; + rise_power (energy_inslew_load_5x5__109) { + values ("158.2, 158.2, 158.2, 202.0, 289.5", \ + "192.3, 192.3, 192.3, 236.1, 323.6", \ + "260.5, 260.5, 260.5, 304.2, 391.8", \ + "396.9, 396.9, 396.9, 440.6, 528.1", \ + "669.6, 669.6, 669.6, 713.3, 800.9"); + } + fall_power (energy_inslew_load_5x5__109) { + values ("83.0, 83.0, 83.0, 126.8, 214.3", \ + "112.6, 112.6, 112.6, 156.3, 243.9", \ + "171.7, 171.7, 171.7, 215.5, 303.0", \ + "290.1, 290.1, 290.1, 333.8, 421.4", \ + "526.7, 526.7, 526.7, 570.5, 658.0"); + } + } + } + } + +} diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/vsclib.py b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/vsclib.py new file mode 100644 index 000000000..96dcac7c6 --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/coriolis/sky130_vsc/vsclib.py @@ -0,0 +1,225 @@ + +import sys +import os.path +from coriolis import Cfg +from coriolis.Hurricane import Technology, DataBase, DbU, Library, Layer, RegularLayer, \ + BasicLayer, Cell, Net, Horizontal, Vertical, \ + Rectilinear, Box, Point, Instance, Transformation, \ + NetExternalComponents, Pad +import coriolis.Viewer +from coriolis.CRL import AllianceFramework, Environment, Gds, LefImport, \ + CellGauge, RoutingGauge, RoutingLayerGauge +from coriolis.helpers import l, u, n, overlay, io, ndaTopDir +from coriolis.helpers.overlay import CfgCache, UpdateSession +from coriolis.Anabatic import StyleFlags +from coriolis.helpers.technology import createBL + + +__all__ = [ "setup" ] + + +def _routing (): + """ + Define the routing gauge along with the various P&R tool parameters. + """ + af = AllianceFramework.get() + db = DataBase.getDB() + tech = db.getTechnology() + rg = RoutingGauge.create('vsclib') + rg.setSymbolic( True ) + dirM1 = RoutingLayerGauge.Vertical + dirM2 = RoutingLayerGauge.Horizontal + netBuilderStyle = 'HV,3RL+' + routingStyle = StyleFlags.HV + + Nimp = createBL( tech, 'Nimp' , BasicLayer.Material.blockage ) + nimp = RegularLayer.create( tech, 'BLOCKAGE7', Nimp ) + tech.setSymbolicLayer( nimp .getName() ) + Pimp = createBL( tech, 'Pimp' , BasicLayer.Material.blockage ) + pimp = RegularLayer.create( tech, 'BLOCKAGE8', Pimp ) + tech.setSymbolicLayer( pimp .getName() ) + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL1' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.PinOnly # layer usage + , 0 # depth + , 0.0 # density (deprecated) + , l( 4.0) # track offset from AB + , l( 8.0) # track pitch + , l( 4.0) # wire width + , l( 3.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 4.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL2' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 1 # depth + , 0.0 # density (deprecated) + , l( 4.0) # track offset from AB + , l( 8.0) # track pitch + , l( 4.0) # wire width + , l( 4.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 6.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL3' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 2 # depth + , 0.0 # density (deprecated) + , l( 4.0) # track offset from AB + , l( 8.0) # track pitch + , l( 4.0) # wire width + , l( 4.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 6.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL4' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 3 # depth + , 0.0 # density (deprecated) + , l( 4.0) # track offset from AB + , l( 16.0) # track pitch + , l( 4.0) # wire width + , l( 4.0) # perpandicular wire width + , l( 2.0) # VIA side + , l( 6.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL5' ) # metal + , dirM1 # preferred routing direction + , RoutingLayerGauge.Default # layer usage + , 4 # depth + , 0.0 # density (deprecated) + , l( 4.0) # track offset from AB + , l( 16.0) # track pitch + , l( 8.0) # wire width + , l( 8.0) # perpandicular wire width + , l( 4.0) # VIA side + , l( 6.0) )) # obstacle dW + rg.addLayerGauge( + RoutingLayerGauge.create( tech.getLayer( 'METAL6' ) # metal + , dirM2 # preferred routing direction + , RoutingLayerGauge.PowerSupply # layer usage + , 5 # depth + , 0.0 # density (deprecated) + , l( 4.0) # track offset from AB + , l(16.0) # track pitch + , l(12.0) # wire width + , l(12.0) # perpandicular wire width + , l( 4.0) # VIA side + , l( 4.0 ) )) # obstacle dW + af.addRoutingGauge( rg ) + af.setRoutingGauge( 'vsclib' ) + + cg = CellGauge.create( 'vsclib' + , 'METAL1' # pin layer name. + , l( 8.0) # pitch. + , l( 72.0) # cell slice height. + , l( 8.0) # cell slice step. + ) + af.addCellGauge( cg ) + af.setCellGauge( 'vsclib' ) + + with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg: + # Place & Route setup + cfg.viewer.minimumSize = 500 + cfg.viewer.pixelThreshold = 2 + cfg.lefImport.minTerminalWidth = 0.0 + cfg.crlcore.groundName = 'vss' + cfg.crlcore.powerName = 'vdd' + cfg.etesian.bloat = 'disabled' + cfg.etesian.aspectRatio = 1.00 + cfg.etesian.aspectRatio = [10, 1000] + cfg.etesian.spaceMargin = 0.10 + cfg.etesian.densityVariation = 0.05 + cfg.etesian.routingDriven = False + cfg.etesian.latchUpDistance = l(2000.0) + #cfg.etesian.diodeName = 'diode' + #cfg.etesian.antennaInsertThreshold = 0.50 + #cfg.etesian.antennaMaxWL = u(250.0) + cfg.etesian.feedNames = 'tie_x0,rowend_x0' + cfg.etesian.defaultFeed = 'tie_x0' + cfg.etesian.cell.zero = 'vsstie' + cfg.etesian.cell.one = 'vddtie' + cfg.etesian.effort = 2 + cfg.etesian.effort = ( ('Fast' , 1) + , ('Standard', 2) + , ('High' , 3) + , ('Extreme' , 4) + ) + cfg.etesian.graphics = 2 + cfg.etesian.graphics = ( ('Show every step' , 1) + , ('Show lower bound', 2) + , ('Show result only', 3) + ) + cfg.anabatic.routingGauge = 'vsclib' + cfg.anabatic.cellGauge = 'vsclib' + cfg.anabatic.globalLengthThreshold = 30*l(100.0) + cfg.anabatic.saturateRatio = 0.90 + cfg.anabatic.saturateRp = 10 + cfg.anabatic.topRoutingLayer = 'METAL5' + cfg.anabatic.edgeLength = 192 + cfg.anabatic.edgeWidth = 32 + cfg.anabatic.edgeCostH = 9.0 + cfg.anabatic.edgeCostK = -10.0 + cfg.anabatic.edgeHInc = 1.0 + cfg.anabatic.edgeHScaling = 1.0 + cfg.anabatic.globalIterations = 10 + cfg.anabatic.globalIterations = [ 1, 100 ] + cfg.anabatic.gcell.displayMode = 1 + cfg.anabatic.gcell.displayMode = (("Boundary", 1), ("Density", 2)) + cfg.anabatic.netBuilderStyle = netBuilderStyle + cfg.anabatic.routingStyle = routingStyle + cfg.katana.disableStackedVias = False + cfg.katana.hTracksReservedLocal = 4 + cfg.katana.hTracksReservedLocal = [0, 20] + cfg.katana.vTracksReservedLocal = 3 + cfg.katana.vTracksReservedLocal = [0, 20] + cfg.katana.termSatReservedLocal = 8 + cfg.katana.termSatThreshold = 9 + cfg.katana.eventsLimit = 4000002 + cfg.katana.ripupCost = 3 + cfg.katana.ripupCost = [0, None] + cfg.katana.strapRipupLimit = 16 + cfg.katana.strapRipupLimit = [1, None] + cfg.katana.localRipupLimit = 9 + cfg.katana.localRipupLimit = [1, None] + cfg.katana.globalRipupLimit = 5 + cfg.katana.globalRipupLimit = [1, None] + cfg.katana.longGlobalRipupLimit = 5 + cfg.chip.padCoreSide = 'North' + # Plugins setup + cfg.clockTree.minimumSide = l(96.0) * 6 + cfg.clockTree.buffer = 'bf1v0x12' + cfg.clockTree.placerEngine = 'Etesian' + cfg.block.spareSide = 10*l(96.0) + cfg.spares.buffer = 'bf1v0x12' + cfg.spares.maxSinks = 31 + + +def _loadNsxlib2 ( cellsTop ): + """ + Setup for NSXLIB2 Alliance library. It is an symbolic library + from which cells are loaded on demand, so we only setup pathes. + + :param cellsTop: The top directory containing the cells views. + """ + af = AllianceFramework.get() + env = af.getEnvironment() + env.setSCALE_X ( 100 ) + env.setCATALOG ( 'CATAL' ) + env.setPOWER ( 'vdd' ) + env.setGROUND ( 'vss' ) + env.setCLOCK ( '^ck$|m_clock|^clk$' ) + env.setBLOCKAGE( 'blockage[Nn]et.*' ) + env.setPad ( '.*_mpx$' ) + env.setRegister( 'df.*' ) + env.setWORKING_LIBRARY( '.' ) + env.addSYSTEM_LIBRARY ( library=(cellsTop / 'vsclib').as_posix(), mode=Environment.Append ) + + +def setup ( cellsTop ): + _routing() + _loadNsxlib2( cellsTop ) diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/core/sky130A_mr.drc b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/core/sky130A_mr.drc new file mode 100644 index 000000000..46c9b1fd1 --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/core/sky130A_mr.drc @@ -0,0 +1,800 @@ +# DRC for SKY130 according to : +# https://skywater-pdk.readthedocs.io/en/latest/rules/periphery.html +# https://skywater-pdk.readthedocs.io/en/latest/rules/layers.html +# +# Distributed under GNU GPLv3: https://www.gnu.org/licenses/ +# +# History : +# 2022-6-22 : 2022.6.30_01.07 release +# +# 2023-6-14 : 2023.6.14_01.08 release +# +########################################################################################## +release = "2023.6.14_01.08" + +require 'time' +require "logger" + +exec_start_time = Time.now + +logger = Logger.new(STDOUT) + +logger.formatter = proc do |severity, datetime, progname, msg| + "#{msg} +" +end +# optionnal for a batch launch : klayout -b -rd input=my_layout.gds -rd report=sky130_drc.txt -r drc_sky130.drc +if $input + source($input, $top_cell) +end + +if $report == "" + report("SKY130 DRC runset") +elsif $report + report("SKY130 DRC runset", $report) +else + report("SKY130 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "sky130_drc.txt")) +end + +AL = true # do not change +CU = false # do not change +# choose betwen only one of AL or CU back-end flow here : +backend_flow = AL + +option_FEOL = false +option_BEOL = false +option_OFFGRID = false +option_SEAL = false +option_FLOATING_MET = false + +# enable / disable rule groups +if $feol == "1" || $feol == "true" + option_FEOL = true # front-end-of-line checks +else + option_FEOL = false +end + +if $beol == "1" || $beol == "true" + option_BEOL = true # back-end-of-line checks +else + option_BEOL = false +end + +if $offgrid == "1" || $offgrid == "true" + option_OFFGRID = true # manufacturing grid/angle checks +else + option_OFFGRID = false +end + +if $seal == "1" || $seal == "true" + option_SEAL = true # option_SEAL RING checks +else + option_SEAL = false +end + +if $floating_met == "1" || $floating_met == "true" + option_FLOATING_MET = true # back-end-of-line checks +else + option_FLOATING_MET = false +end + +# klayout setup +######################## +# use a tile size of 1mm - not used in deep mode- +# tiles(1000.um) +# use a tile border of 10 micron: +# tile_borders(1.um) +#no_borders + +# hierachical +deep + +if $thr + threads($thr) +else + threads(4) +end + +# if more inof is needed, set true +# verbose(true) +verbose(true) + +# layers definitions +######################## + +# all except purpose (datatype) 5 -- label and 44 -- via +li_wildcard = "67/20" +mcon_wildcard = "67/44" + +m1_wildcard = "68/20" +via_wildcard = "68/44" + +m2_wildcard = "69/20" +via2_wildcard = "69/44" + +m3_wildcard = "70/20" +via3_wildcard = "70/44" + +m4_wildcard = "71/20" +via4_wildcard = "71/44" + +m5_wildcard = "72/20" + +nsdm_wildcard = "93/44" + +psdm_wildcard = "94/20" +nwell_wildcard = "64/20" + +diff = input(65, 20) +tap = polygons(65, 44) +nwell = polygons(nwell_wildcard) +dnwell = polygons(64, 18) +pwbm = polygons(19, 44) +pwde = polygons(124, 20) +natfet = polygons(124, 21) +hvtr = polygons(18, 20) +hvtp = polygons(78, 44) +ldntm = polygons(11, 44) +hvi = polygons(75, 20) +tunm = polygons(80, 20) +lvtn = polygons(125, 44) +poly = polygons(66, 20) +hvntm = polygons(125, 20) +nsdm = polygons(nsdm_wildcard) +psdm = polygons(psdm_wildcard) +rpm = polygons(86, 20) +urpm = polygons(79, 20) +npc = polygons(95, 20) +licon = polygons(66, 44) + +li = polygons(li_wildcard) +mcon = polygons(mcon_wildcard) + +m1 = polygons(m1_wildcard) +via = polygons(via_wildcard) + +m2 = polygons(m2_wildcard) +via2 = polygons(via2_wildcard) + +m3 = polygons(m3_wildcard) +via3 = polygons(via3_wildcard) + +m4 = polygons(m4_wildcard) +via4 = polygons(via4_wildcard) + +m5 = polygons(m5_wildcard) + +pad = polygons(76, 20) +nsm = polygons(61, 20) +capm = polygons(89, 44) +cap2m = polygons(97, 44) +vhvi = polygons(74, 21) +uhvi = polygons(74, 22) +npn = polygons(82, 20) +inductor = polygons(82, 24) +vpp = polygons(82, 64) +pnp = polygons(82, 44) +lvs_prune = polygons(84, 44) +ncm = polygons(92, 44) +padcenter = polygons(81, 20) +mf = polygons(76, 44) +areaid_sl = polygons(81, 1) +areaid_ce = polygons(81, 2) +areaid_fe = polygons(81, 3) +areaid_sc = polygons(81, 4) +areaid_sf = polygons(81, 6) +areaid_sw = polygons(81, 7) +areaid_sr = polygons(81, 8) +areaid_mt = polygons(81, 10) +areaid_dt = polygons(81, 11) +areaid_ft = polygons(81, 12) +areaid_ww = polygons(81, 13) +areaid_ld = polygons(81, 14) +areaid_ns = polygons(81, 15) +areaid_ij = polygons(81, 17) +areaid_zr = polygons(81, 18) +areaid_ed = polygons(81, 19) +areaid_de = polygons(81, 23) +areaid_rd = polygons(81, 24) +areaid_dn = polygons(81, 50) +areaid_cr = polygons(81, 51) +areaid_cd = polygons(81, 52) +areaid_st = polygons(81, 53) +areaid_op = polygons(81, 54) +areaid_en = polygons(81, 57) +areaid_en20 = polygons(81, 58) +areaid_le = polygons(81, 60) +areaid_hl = polygons(81, 63) +areaid_sd = polygons(81, 70) +areaid_po = polygons(81, 81) +areaid_it = polygons(81, 84) +areaid_et = polygons(81, 101) +areaid_lvt = polygons(81, 108) +areaid_re = polygons(81, 125) +areaid_ag = polygons(81, 79) +poly_rs = polygons(66, 13) +diff_rs = polygons(65, 13) +pwell_rs = polygons(64, 13) +li_rs = polygons(67, 13) +cfom = polygons(22, 20) + + +# Define a new custom function that selects polygons by their number of holes: +# It will return a new layer containing those polygons with min to max holes. +# max can be nil to omit the upper limit. +class DRC::DRCLayer + def with_holes(min, max) + new_data = RBA::Region::new + self.data.each do |p| + if p.holes >= (min || 0) && (!max || p.holes <= max) + new_data.insert(p) + end + end + DRC::DRCLayer::new(@engine, new_data) + end +end + +# DRC section +######################## +log("DRC section") + +if option_FEOL +log("option_FEOL section") +# dnwell +log("START: 64/18 (dnwell)") +dnwell.width(3.0, euclidian).output("dnwell.2", "dnwell.2 : min. dnwell width : 3.0um") +log("END: 64/18 (dnwell)") + +not_sram = layout(source.cell_obj).select("-*sky130_sram_*kbyte_*") +not_sram_nsdm = not_sram.input(nsdm_wildcard) +not_sram_psdm = not_sram.input(psdm_wildcard) +not_sram_nwell = not_sram.input(nwell_wildcard) + +# This is a hack, should be reverted + +not_io = layout(source.cell_obj).select("-*sky130_fd_io__gpiov2_amux", "-*sky130_fd_io__simple_pad_and_busses") +not_io_nwell = not_io.input(nwell_wildcard) + +# nwell +log("START: 64/20 (nwell)") +nwell.width(0.84, euclidian).output("nwell.1", "nwell.1 : min. nwell width : 0.84um") +nwell.space(1.27, euclidian).output("nwell.2a", "nwell.2a : min. nwell spacing (merged if less) : 1.27um") +nwell_interact = not_sram_nwell.and(not_io_nwell).merge +dnwell.enclosing(nwell_interact.holes, 1.03, euclidian).output("nwell.6", "nwell.6 : min enclosure of nwellHole by dnwell : 1.03um") +log("END: 64/20 (nwell)") + +# hvtp +log("START: 78/44 (hvtp)") +hvtp.width(0.38, euclidian).output("hvtp.1", "hvtp.1 : min. hvtp width : 0.38um") +hvtp.space(0.38, euclidian).output("hvtp.2", "hvtp.2 : min. hvtp spacing : 0.38um") +log("END: 78/44 (hvtp)") + +# hvtr +log("START: 18/20 (htvr)") +hvtr.width(0.38, euclidian).output("hvtr.1", "hvtr.1 : min. hvtr width : 0.38um") +hvtr.separation(hvtp, 0.38, euclidian).output("hvtr.2", "hvtr.2 : min. hvtr spacing : 0.38um") +hvtr.and(hvtp).output("hvtr.2_a", "hvtr.2_a : hvtr must not overlap hvtp") +log("END: 18/20 (htvr)") + +# lvtn +log("START: 25/44 (lvtn)") +lvtn.width(0.38, euclidian).output("lvtn.1a", "lvtn.1a : min. lvtn width : 0.38um") +lvtn.space(0.38, euclidian).output("lvtn.2", "lvtn.2 : min. lvtn spacing : 0.38um") +log("END: 25/44 (lvtn)") + +# ncm +log("START: 92/44 (ncm)") +ncm.width(0.38, euclidian).output("ncm.1", "ncm.1 : min. ncm width : 0.38um") +ncm.space(0.38, euclidian).output("ncm.2a", "ncm.2a : min. ncm spacing : 0.38um") +log("END: 92/44 (ncm)") + +# diff-tap +log("START: 65/20 (diff)") +difftap = diff.or(tap) +diff_width = diff.rectangles.width(0.15, euclidian).polygons +diff_cross_areaid_ce = diff_width.edges.outside_part(areaid_ce).not(diff_width.outside(areaid_ce).edges) +diff_cross_areaid_ce.output("difftap.1", "difftap.1 : min. diff width across areaid:ce : 0.15um") +diff.outside(areaid_ce).width(0.15, euclidian).output("difftap.1_a", "difftap.1_a : min. diff width in periphery : 0.15um") +log("END: 65/20 (diff)") + +log("START: 65/44 (tap)") +tap_width = tap.rectangles.width(0.15, euclidian).polygons +tap_cross_areaid_ce = tap_width.edges.outside_part(areaid_ce).not(tap_width.outside(areaid_ce).edges) +tap_cross_areaid_ce.output("difftap.1_b", "difftap.1_b : min. tap width across areaid:ce : 0.15um") +tap.not(areaid_ce).width(0.15, euclidian).output("difftap.1_c", "difftap.1_c : min. tap width in periphery : 0.15um") +log("END: 65/44 (tap)") + +difftap.space(0.27, euclidian).output("difftap.3", "difftap.3 : min. difftap spacing : 0.27um") + +# tunm +log("START: 80/20 (tunm)") +tunm.width(0.41, euclidian).output("tunm.1", "tunm.1 : min. tunm width : 0.41um") +tunm.space(0.5, euclidian).output("tunm.2", "tunm.2 : min. tunm spacing : 0.5um") +log("END: 80/20 (tunm)") + +# poly +log("START: 66/20 (poly)") +poly.width(0.15, euclidian).output("poly.1a", "poly.1a : min. poly width : 0.15um") +poly.not(areaid_ce).space(0.21, euclidian).output("poly.2", "poly.2 : min. poly spacing : 0.21um") + + +# rpm +log("START: 86/20 (rpm)") +rpm.width(1.27, euclidian).output("rpm.1a", "rpm.1a : min. rpm width : 1.27um") +rpm.space(0.84, euclidian).output("rpm.2", "rpm.2 : min. rpm spacing : 0.84um") +log("END: 86/20 (rpm)") + +# urpm +log("START: 79/20 (urpm)") +urpm.width(1.27, euclidian).output("urpm.1a", "urpm.1a : min. rpm width : 1.27um") +urpm.space(0.84, euclidian).output("urpm.2", "urpm.2 : min. rpm spacing : 0.84um") +log("END: 79/20 (urpm)") + +# npc +log("START: 95/20 (npc)") +npc.width(0.27, euclidian).output("npc.1", "npc.1 : min. npc width : 0.27um") +npc.space(0.27, euclidian).output("npc.2", "npc.2 : min. npc spacing, should be manually merged if less than : 0.27um") +log("END: 95/20 (npc)") + +# nsdm +log("START: 93/44 (nsdm)") +not_sram_nsdm.outside(areaid_ce).width(0.38, euclidian).output("nsd.1", "nsd.1 : min. nsdm width : 0.38um") +not_sram_nsdm.not(areaid_ce).space(0.38, euclidian).output("nsd.2", "nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um") +log("END: 93/44 (nsdm)") + +# psdm +log("START: 94/20 (psdm)") +not_sram_psdm.outside(areaid_ce).width(0.38, euclidian).output("psd.1", "psd.1 : min. psdm width : 0.38um") +not_sram_psdm.not(areaid_ce).space(0.38, euclidian).output("psd.2", "psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um") +log("END: 94/20 (psdm)") + +# licon +log("START: 66/44 (licon)") +if option_SEAL + ringLICON = licon.drc(with_holes > 0) + rectLICON = licon.not(ringLICON) +else + rectLICON = licon +end +xfom = difftap.not(poly) +licon1ToXfom = licon.interacting(licon.and(xfom)) +licon1ToXfom_PERI = licon1ToXfom.not(areaid_ce) +rectLICON.non_rectangles.output("licon.1", "licon.1 : licon should be rectangle") +rectLICON.not(rpm.or(urpm)).edges.without_length(0.17).output("licon.1_a/b", "licon.1_a/b : minimum/maximum width of licon : 0.17um") +licon1ToXfom_PERI.separation(npc, 0.09, euclidian).output("licon.13", "licon.13 : min. difftap licon spacing to npc : 0.09um") +licon1ToXfom_PERI.and(npc).output("licon.13_a", "licon.13_a : licon of diffTap in periphery must not overlap npc") +licon.interacting(poly).and(licon.interacting(difftap)).output("licon.17", "licon.17 : Licons may not overlap both poly and (diff or tap)") +log("END: 66/44 (licon)") + +# CAPM +log("START: 89/44 (capm)") +capm.width(1.0, euclidian).output("capm.1", "capm.1 : min. capm width : 1.0um") +capm.space(0.84, euclidian).output("capm.2a", "capm.2a : min. capm spacing : 0.84um") +m3.interacting(capm).isolated(1.2, euclidian).output("capm.2b", "capm.2b : min. capm spacing : 1.2um") +(m3.interacting(capm)).isolated(1.2, euclidian).output("capm.2b_a", "capm.2b_a : min. spacing of m3_bot_plate : 1.2um") +capm.and(m3).enclosing(m3, 0.14, euclidian).output("capm.3", "capm.3 : min. capm and m3 enclosure of m3 : 0.14um") +m3.enclosing(capm, 0.14, euclidian).output("capm.3_a", "capm.3_a : min. m3 enclosure of capm : 0.14um") +capm.enclosing(via3, 0.14, euclidian).output("capm.4", "capm.4 : min. capm enclosure of via3 : 0.14um") +capm.separation(via3, 0.14, euclidian).output("capm.5", "capm.5 : min. capm spacing to via3 : 0.14um") +(m3.not_interacting(capm)).separation(capm, 0.5, euclidian).output("capm.11", "capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um") +log("END: 89/44 (capm)") + +# CAP2M +log("START: 97/44 (cap2m)") +cap2m.width(1.0, euclidian).output("cap2m.1", "cap2m.1 : min. cap2m width : 1.0um") +cap2m.space(0.84, euclidian).output("cap2m.2a", "cap2m.2a : min. cap2m spacing : 0.84um") +m4.interacting(cap2m).isolated(1.2, euclidian).output("cap2m.2b", "cap2m.2b : min. cap2m spacing : 1.2um") +(m4.interacting(cap2m)).isolated(1.2, euclidian).output("cap2m.2b_a", "cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um") +cap2m.and(m4).enclosing(m4, 0.14, euclidian).output("cap2m.3", "cap2m.3 : min. m4 enclosure of cap2m : 0.14um") +m4.enclosing(cap2m, 0.14, euclidian).output("cap2m.3_a", "cap2m.3_a : min. m4 enclosure of cap2m : 0.14um") +cap2m.enclosing(via4, 0.2, euclidian).output("cap2m.4", "cap2m.4 : min. cap2m enclosure of via4 : 0.14um") +cap2m.separation(via4, 0.2, euclidian).output("cap2m.5", "cap2m.5 : min. cap2m spacing to via4 : 0.14um") +(m4.not_interacting(cap2m)).separation(cap2m, 0.5, euclidian).output("cap2m.11", "cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um") +log("END: 97/44 (cap2m)") +end #option_FEOL + +if option_BEOL +log("option_BEOL section") + +# li +log("START: 67/20 (li)") +linotace = li.not(li.interacting(areaid_ce)) +linotace.width(0.17, euclidian).output("li.1", "li.1 : min. li width : 0.17um") +# This rule is taking a long time in some slots +linotace.edges.space(0.17, euclidian).output("li.3", "li.3 : min. li spacing : 0.17um") +licon_peri = licon.not(areaid_ce) +li_edges_with_less_enclosure = li.enclosing(licon_peri, 0.08, projection).second_edges +error_corners = li_edges_with_less_enclosure.width(angle_limit(100.0), 1.dbu) +li_interact = licon_peri.interacting(error_corners.polygons(1.dbu)) +li_interact.output("li.5", "li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um") +linotace.with_area(nil, 0.0561).output("li.6", "li.6 : min. li area : 0.0561um²") +log("END: 67/20 (li)") + +# ct +log("START: 67/44 (mcon)") +mconnotace = mcon.not(areaid_ce) +if option_SEAL + ringMCON = mcon.drc(with_holes > 0) + rectMCON = mcon.not(ringMCON) +else + rectMCON = mcon +end +rectMCON_peri = rectMCON.not(areaid_ce) +rectMCON.non_rectangles.output("ct.1", "ct.1: non-ring mcon should be rectangular") +# rectMCON_peri.edges.without_length(0.17).output("ct.1_a/b", "ct.1_a/b : minimum/maximum width of mcon : 0.17um") +rectMCON_peri.drc(width < 0.17).output("ct.1_a", "ct.1_a : minimum width of mcon : 0.17um") +rectMCON_peri.drc(length > 0.17).output("ct.1_b", "ct.1_b : maximum length of mcon : 0.17um") +mcon.space(0.19, euclidian).output("ct.2", "ct.2 : min. mcon spacing : 0.19um") +if option_SEAL + ringMCON.width(0.17, euclidian).output("ct.3", "ct.3 : min. width of ring-shaped mcon : 0.17um") + ringMCON.drc(width >= 0.175).output("ct.3_a", "ct.3_a : max. width of ring-shaped mcon : 0.175um") + ringMCON.not(areaid_sl).output("ct.3_b", "ct.3_b: ring-shaped mcon must be enclosed by areaid_sl") +end +mconnotace.not(li).output("ct.4", "ct.4 : mcon should covered by li") +log("END: 67/44 (mcon)") + +# m1 +log("START: 68/20 (m1)") +m1.width(0.14, euclidian).output("m1.1", "m1.1 : min. m1 width : 0.14um") +huge_m1 = m1.sized(-1.5).sized(1.5).snap(0.005) & m1 +non_huge_m1 = m1.edges - huge_m1 +huge_m1 = huge_m1.edges.outside_part(m1.merged) + +non_huge_m1.space(0.14, euclidian).output("m1.2", "m1.2 : min. m1 spacing : 0.14um") + +(huge_m1.separation(non_huge_m1, 0.28, euclidian) + huge_m1.space(0.28, euclidian)).output("m1.3ab", "m1.3ab : min. 3um.m1 spacing m1 : 0.28um") + +#not_in_cell6 = layout(source.cell_obj).select("-s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b", "-s8fpls_pl8", "-s8fs_cmux4_fm") +not_in_cell6 = layout(source.cell_obj).select("-s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b", "-s8fs_cmux4_fm") +not_in_cell6_m1 = not_in_cell6.input(m1_wildcard) + +not_in_cell6_m1.enclosing(mconnotace, 0.03, euclidian).output("791_m1.4", "791_m1.4 : min. m1 enclosure of mcon : 0.03um") +mconnotace.not(m1).output("m1.4", "m1.4 : mcon periphery must be enclosed by m1") +in_cell6 = layout(source.cell_obj).select("-*", "+s8cell_ee_plus_sseln_a", "+s8cell_ee_plus_sseln_b", "+s8cell_ee_plus_sselp_a", "+s8cell_ee_plus_sselp_b", "+s8fpls_pl8", "+s8fs_cmux4_fm") +in_cell6_m1 = in_cell6.input(m1_wildcard) +in_cell6_m1.enclosing(mcon, 0.005, euclidian).output("m1.4a", "m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um") + +in_cell6_m1.not(m1).output('m1.4a_a', 'm1.4a_a : mcon periph must be enclosed by met1 for specific cells') + +m1.with_area(0..0.083).output("m1.6", "m1.6 : min. m1 area : 0.083um²") + +m1.holes.with_area(0..0.14).output("m1.7", "m1.7 : min. m1 with holes area : 0.14um²") +if option_FLOATING_MET + m1.not_interacting(via.or(mcon)).output("m1.x", "floating met1, must interact with via1") +end + +if backend_flow = AL + #Could flag false positive, fix would be to add .rectangles for m1 + mconnotace_edges_with_less_enclosure_m1 = m1.enclosing(mconnotace, 0.06, projection).second_edges + error_corners_m1 = mconnotace_edges_with_less_enclosure_m1.width(angle_limit(100.0), 1.dbu) + mconnotace_interact_m1 = mconnotace.interacting(error_corners_m1.polygons(1.dbu)) + mconnotace_interact_m1.output("m1.5", "m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um") +end +log("END: 68/20 (m1)") + +# via +log("START: 68/44 (via)") +if backend_flow = AL + if option_SEAL + ringVIA = via.drc(with_holes > 0) + rectVIA = via.not(ringVIA) + else + rectVIA = via + end + + via_not_mt = rectVIA.not(areaid_mt) + + via_not_mt.non_rectangles.output("via.1a", "via.1a : via outside of moduleCut should be rectangular") + via_not_mt.width(0.15, euclidian).output("via.1a_a", "via.1a_a : min. width of via outside of moduleCut : 0.15um") + # via_not_mt.edges.without_length(nil, 0.15 + 1.dbu).output("via.1a_b", "via.1a_b : maximum length of via : 0.15um") + via_not_mt.drc(length > 0.15).output("via.1a_b", "via.1a_b : maximum length of via : 0.15um") + + via.space(0.17, euclidian).output("via.2", "via.2 : min. via spacing : 0.17um") + + if option_SEAL + ringVIA.width(0.2, euclidian).output("via.3", "via.3 : min. width of ring-shaped via : 0.2um") + ringVIA.drc(width >= 0.205).output("via.3_a", "via.3_a : max. width of ring-shaped via : 0.205um") + ringVIA.not(areaid_sl).output("via.3_b", "via.3_b: ring-shaped via must be enclosed by areaid_sl") + end + + m1.edges.enclosing(rectVIA.drc(width == 0.15), 0.055, euclidian).output("via.4a", "via.4a : min. m1 enclosure of 0.15um via : 0.055um") + rectVIA.squares.drc(width == 0.15).not(m1).output("via.4a_a", "via.4a_a : 0.15um via must be enclosed by met1") + + via1_edges_with_less_enclosure_m1 = m1.edges.enclosing(rectVIA.drc(width == 0.15), 0.085, projection).second_edges + error_corners_via1 = via1_edges_with_less_enclosure_m1.width(angle_limit(100.0), 1.dbu) + via2_interact = via.interacting(error_corners_via1.polygons(1.dbu)) + via2_interact.output("via.5a", "via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um") + +end +log("END: 68/44 (via)") + +# m2 +log("START: 69/20 (m2)") +m2.width(0.14, euclidian).output("m2.1", "m2.1 : min. m2 width : 0.14um") + +huge_m2 = m2.sized(-1.5).sized(1.5).snap(0.005) & m2 +non_huge_m2 = m2.edges - huge_m2 +huge_m2 = huge_m2.edges.outside_part(m2.merged) +via_outside_periphery = via.not(areaid_ce) + +non_huge_m2.space(0.14, euclidian).output("m2.2", "m2.2 : min. m2 spacing : 0.14um") + +(huge_m2.separation(non_huge_m2, 0.28, euclidian) + huge_m2.space(0.28, euclidian)).output("m2.3ab", "m2.3ab : min. 3um.m2 spacing m2 : 0.28um") + +m2.with_area(0..0.0676).output("m2.6", "m2.6 : min. m2 area : 0.0676um²") +m2.holes.with_area(0..0.14).output("m2.7", "m2.7 : min. m2 holes area : 0.14um²") +if option_FLOATING_MET + m2.not_interacting(via.or(via2)).output("m2.x", "floating met2, must interact with via1 or via2") +end +if backend_flow = AL + m2.enclosing(via_outside_periphery, 0.055, euclidian).output("m2.4", "m2.4 : min. m2 enclosure of via : 0.055um") + via_outside_periphery.not(m2).output("m2.4_a", "m2.4_a : via in periphery must be enclosed by met2") + via_edges_with_less_enclosure_m2 = m2.enclosing(via, 0.085, projection).second_edges + error_corners = via_edges_with_less_enclosure_m2.width(angle_limit(100.0), 1.dbu) + via_interact = via.interacting(error_corners.polygons(1.dbu)) + via_interact.output("m2.5", "m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um") + +end +log("END: 69/20 (m2)") + +# via2 +log("START: 69/44 (via2)") +if backend_flow = AL + if option_SEAL + ringVIA2 = via2.drc(with_holes > 0) + rectVIA2 = via2.not(ringVIA2) + else + rectVIA2 = via2 + end + + via2_not_mt = rectVIA2.not(areaid_mt) + via2_not_mt.non_rectangles.output("via2.1a", "via2.1a : via2 outside of moduleCut should be rectangular") + via2_not_mt.width(0.2, euclidian).output("via2.1a_a", "via2.1a_a : min. width of via2 outside of moduleCut : 0.2um") + via2_not_mt.edges.without_length(nil, 0.2 + 1.dbu).output("via2.1a_b", "via2.1a_b : maximum length of via2 : 0.2um") + via2.space(0.2, euclidian).output("via2.2", "via2.2 : min. via2 spacing : 0.2um") + + if option_SEAL + ringVIA2.width(0.2, euclidian).output("via2.3", "via2.3 : min. width of ring-shaped via2 : 0.2um") + ringVIA2.drc(width >= 0.205).output("via2.3_a", "via2.3_a : max. width of ring-shaped via2 : 0.205um") + ringVIA2.not(areaid_sl).output("via2.3_b", "via2.3_b: ring-shaped via2 must be enclosed by areaid_sl") + end + + m2.enclosing(via2, 0.04, euclidian).output("via2.4", "via2.4 : min. m2 enclosure of via2 : 0.04um") + via2.not(m2).output("via2.4_a", "via2.4_a : via must be enclosed by met2") + + via2_edges_with_less_enclosure = m2.enclosing(via2, 0.085, projection).second_edges + error_corners = via2_edges_with_less_enclosure.width(angle_limit(100.0), 1.dbu) + via2_interact = via2.interacting(error_corners.polygons(1.dbu)) + via2_interact.output("via2.5", "via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um") +end +log("END: 69/44 (via2)") + +# m3 +log("START: 70/20 (m3)") +m3.width(0.3, euclidian).output("m3.1", "m3.1 : min. m3 width : 0.3um") + +huge_m3 = m3.sized(-1.5).sized(1.5).snap(0.005) & m3 +non_huge_m3 = m3.edges - huge_m3 +huge_m3 = huge_m3.edges.outside_part(m3.merged) + +non_huge_m3.space(0.3, euclidian).output("m3.2", "m3.2 : min. m3 spacing : 0.3um") + +m3.with_area(0..0.240).output("m3.6", "m3.6 : min. m3 area : 0.240um²") + +(huge_m3.separation(non_huge_m3, 0.4, euclidian) + huge_m3.space(0.4, euclidian)).output("m3.3cd", "m3.3cd : min. 3um.m3 spacing m3 : 0.4um") +if option_FLOATING_MET + m3.not_interacting(via2.or(via3)).output("m3.x", "floating met3, must interact with via2 or via3") +end +if backend_flow = AL + m3.enclosing(via2, 0.065, euclidian).output("m3.4", "m3.4 : min. m3 enclosure of via2 : 0.065um") + via2.not(m3).output("m3.4_a", "m3.4_a : via2 must be enclosed by met3") +end +log("END: 70/20 (m3)") + +# via3 +log("START: 70/44 (via3)") +if backend_flow = AL + if option_SEAL + ringVIA3 = via3.drc(with_holes > 0) + rectVIA3 = via3.not(ringVIA3) + else + rectVIA3 = via3 + end + + via3_not_mt = rectVIA3.not(areaid_mt) + via3_not_mt.non_rectangles.output("via3.1", "via3.1 : via3 outside of moduleCut should be rectangular") + via3_not_mt.width(0.2, euclidian).output("via3.1_a", "via3.1_a : min. width of via3 outside of moduleCut : 0.2um") + via3_not_mt.edges.without_length(nil, 0.2 + 1.dbu).output("via3.1_b", "via3.1_b : maximum length of via3 : 0.2um") + + via3.space(0.2, euclidian).output("via3.2", "via3.2 : min. via3 spacing : 0.2um") + m3.enclosing(via3, 0.06, euclidian).output("via3.4", "via3.4 : min. m3 enclosure of via3 : 0.06um") + rectVIA3.not(m3).output("via3.4_a", "via3.4_a : non-ring via3 must be enclosed by met3") + + via_edges_with_less_enclosure = m3.enclosing(via3, 0.09, projection).second_edges + error_corners = via_edges_with_less_enclosure.width(angle_limit(100.0), 1.dbu) + via3_interact = via3.interacting(error_corners.polygons(1.dbu)) + via3_interact.output("via3.5", "via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um") +end +log("END: 70/44 (via3)") + +# m4 +log("START: 71/20 (m4)") +m4.width(0.3, euclidian).output("m4.1", "m4.1 : min. m4 width : 0.3um") + +huge_m4 = m4.sized(-1.5).sized(1.5).snap(0.005) & m4 +non_huge_m4 = m4.edges - huge_m4 +huge_m4 = huge_m4.edges.outside_part(m4.merged) + +non_huge_m4.space(0.3, euclidian).output("m4.2", "m4.2 : min. m4 spacing : 0.3um") + +m4.with_area(0..0.240).output("m4.4a", "m4.4a : min. m4 area : 0.240um²") + +(huge_m4.separation(non_huge_m4, 0.4, euclidian) + huge_m4.space(0.4, euclidian)).output("m4.5ab", "m4.5ab : min. 3um.m4 spacing m4 : 0.4um") +if option_FLOATING_MET + m4.not_interacting(via3.or(via4)).output("m4.x", "floating met3, must interact with via3 or via4") +end +if backend_flow = AL + m4.enclosing(via3, 0.065, euclidian).output("m4.3", "m4.3 : min. m4 enclosure of via3 : 0.065um") + via3.not(m4).output("m4.3_a", "m4.3_a : via3 must be enclosed by met4") +end +log("END: 71/20 (m4)") + +# via4 +log("START: 71/44 (via4)") +if option_SEAL + ringVIA4 = via4.drc(with_holes > 0) + rectVIA4 = via4.not(ringVIA4) +else + rectVIA4 = via4 +end + +via4_not_mt = rectVIA4.not(areaid_mt) +via4_not_mt.non_rectangles.output("via4.1", "via4.1 : via4 outside of moduleCut should be rectangular") +rectVIA4.width(0.8, euclidian).output("via4.1_a", "via4.1_a : min. width of via4 outside of moduleCut : 0.8um") +rectVIA4.drc(length > 0.8).output("via4.1_b", "via4.1_b : maximum length of via4 : 0.8um") + +via4.space(0.8, euclidian).polygons.output("via4.2", "via4.2 : min. via4 spacing : 0.8um") + +if option_SEAL + ringVIA4.width(0.8, euclidian).output("via4.3", "via4.3 : min. width of ring-shaped via4 : 0.8um") + ringVIA4.drc(width >= 0.805).output("via4.3_a", "via4.3_a : max. width of ring-shaped via4 : 0.805um") + ringVIA4.not(areaid_sl).output("via4.3_b", "via4.3_b: ring-shaped via4 must be enclosed by areaid_sl") +end + +m4.enclosing(via4, 0.19, euclidian).output("via4.4", "via4.4 : min. m4 enclosure of via4 : 0.19um") +rectVIA4.not(m4).output("via4.4_a", "via4.4_a : m4 must enclose all via4") +log("END: 71/44 (via4)") + +# m5 +log("START: 72/20 (m5)") +m5.width(1.6, euclidian).output("m5.1", "m5.1 : min. m5 width : 1.6um") + +m5.space(1.6, euclidian).output("m5.2", "m5.2 : min. m5 spacing : 1.6um") + +m5.enclosing(via4, 0.31, euclidian).output("m5.3", "m5.3 : min. m5 enclosure of via4 : 0.31um") +via4.not(m5).output("m5.3_a", "m5.3_a : via must be enclosed by m5") +if option_FLOATING_MET + m5.not_interacting(via4).output("m5.x", "floating met5, must interact with via4") +end +m5.with_area(0..4.0).output("m5.4", "m5.4 : min. m5 area : 4.0um²") +log("END: 72/20 (m5)") + +# pad +log("START: 76/20 (pad)") +pad.space(1.27, euclidian).output("pad.2", "pad.2 : min. pad spacing : 1.27um") +log("END: 76/20 (pad)") + +end #option_BEOL + +if option_FEOL +log("option_FEOL section") + +# hvi +log("START: 75/20 (hvi)") +hvi_peri = hvi.not(areaid_ce) +hvi_peri.width(0.6, euclidian).output("hvi.1", "hvi.1 : min. hvi width : 0.6um") +hvi_peri.space(0.7, euclidian).output("hvi.2a", "hvi.2a : min. hvi spacing : 0.7um") +log("END: 75/20 (hvi)") + +# hvntm +log("START: 125/20 (hvntm)") +hvntm_peri = hvntm.not(areaid_ce) +hvntm_peri.width(0.7, euclidian).output("hvntm.1", "hvntm.1 : min. hvntm width : 0.7um") +hvntm_peri.space(0.7, euclidian).output("hvntm.2", "hvntm.2 : min. hvntm spacing : 0.7um") +log("END: 125/20 (hvntm)") + +end #option_FEOL + + +if option_OFFGRID +log("option_OFFGRID-ANGLES section") + +dnwell.ongrid(0.005).output("dnwell_option_OFFGRID", "x.1b : option_OFFGRID vertex on dnwell") +dnwell.with_angle(0 .. 45).output("dnwell_angle", "x.3a : non 45 degree angle dnwell") +nwell.ongrid(0.005).output("nwell_option_OFFGRID", "x.1b : option_OFFGRID vertex on nwell") +nwell.with_angle(0 .. 45).output("nwell_angle", "x.3a : non 45 degree angle nwell") +pwbm.ongrid(0.005).output("pwbm_option_OFFGRID", "x.1b : option_OFFGRID vertex on pwbm") +pwbm.with_angle(0 .. 45).output("pwbm_angle", "x.3a : non 45 degree angle pwbm") +pwde.ongrid(0.005).output("pwde_option_OFFGRID", "x.1b : option_OFFGRID vertex on pwde") +pwde.with_angle(0 .. 45).output("pwde_angle", "x.3a : non 45 degree angle pwde") +hvtp.ongrid(0.005).output("hvtp_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvtp") +hvtp.with_angle(0 .. 45).output("hvtp_angle", "x.3a : non 45 degree angle hvtp") +hvtr.ongrid(0.005).output("hvtr_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvtr") +hvtr.with_angle(0 .. 45).output("hvtr_angle", "x.3a : non 45 degree angle hvtr") +lvtn.ongrid(0.005).output("lvtn_option_OFFGRID", "x.1b : option_OFFGRID vertex on lvtn") +lvtn.with_angle(0 .. 45).output("lvtn_angle", "x.3a : non 45 degree angle lvtn") +ncm.ongrid(0.005).output("ncm_option_OFFGRID", "x.1b : option_OFFGRID vertex on ncm") +ncm.with_angle(0 .. 45).output("ncm_angle", "x.3a : non 45 degree angle ncm") +diff.ongrid(0.005).output("diff_option_OFFGRID", "x.1b : option_OFFGRID vertex on diff") +tap.ongrid(0.005).output("tap_option_OFFGRID", "x.1b : option_OFFGRID vertex on tap") +diff.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("diff_angle", "x.2 : non 90 degree angle diff") +diff.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("diff_angle", "x.2c : non 45 degree angle diff") +tap.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("tap_angle", "x.2 : non 90 degree angle tap") +tap.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("tap_angle", "x.2c : non 45 degree angle tap") +tunm.ongrid(0.005).output("tunm_option_OFFGRID", "x.1b : option_OFFGRID vertex on tunm") +tunm.with_angle(0 .. 45).output("tunm_angle", "x.3a : non 45 degree angle tunm") +poly.ongrid(0.005).output("poly_option_OFFGRID", "x.1b : option_OFFGRID vertex on poly") +poly.with_angle(0 .. 90).output("poly_angle", "x.2 : non 90 degree angle poly") +rpm.ongrid(0.005).output("rpm_option_OFFGRID", "x.1b : option_OFFGRID vertex on rpm") +rpm.with_angle(0 .. 45).output("rpm_angle", "x.3a : non 45 degree angle rpm") +npc.ongrid(0.005).output("npc_option_OFFGRID", "x.1b : option_OFFGRID vertex on npc") +npc.with_angle(0 .. 45).output("npc_angle", "x.3a : non 45 degree angle npc") +nsdm.ongrid(0.005).output("nsdm_option_OFFGRID", "x.1b : option_OFFGRID vertex on nsdm") +nsdm.with_angle(0 .. 45).output("nsdm_angle", "x.3a : non 45 degree angle nsdm") +psdm.ongrid(0.005).output("psdm_option_OFFGRID", "x.1b : option_OFFGRID vertex on psdm") +psdm.with_angle(0 .. 45).output("psdm_angle", "x.3a : non 45 degree angle psdm") +licon.ongrid(0.005).output("licon_option_OFFGRID", "x.1b : option_OFFGRID vertex on licon") +licon.with_angle(0 .. 90).output("licon_angle", "x.2 : non 90 degree angle licon") +li.ongrid(0.005).output("li_option_OFFGRID", "x.1b : option_OFFGRID vertex on li") +li.with_angle(0 .. 45).output("li_angle", "x.3a : non 45 degree angle li") +mcon.ongrid(0.005).output("ct_option_OFFGRID", "x.1b : option_OFFGRID vertex on mcon") +mcon.with_angle(0 .. 90).output("ct_angle", "x.2 : non 90 degree angle mcon") +vpp.ongrid(0.005).output("vpp_option_OFFGRID", "x.1b : option_OFFGRID vertex on vpp") +vpp.with_angle(0 .. 45).output("vpp_angle", "x.3a : non 45 degree angle vpp") +m1.ongrid(0.005).output("m1_option_OFFGRID", "x.1b : option_OFFGRID vertex on m1") +m1.with_angle(0 .. 45).output("m1_angle", "x.3a : non 45 degree angle m1") +via.ongrid(0.005).output("via_option_OFFGRID", "x.1b : option_OFFGRID vertex on via") +via.with_angle(0 .. 90).output("via_angle", "x.2 : non 90 degree angle via") +m2.ongrid(0.005).output("m2_option_OFFGRID", "x.1b : option_OFFGRID vertex on m2") +m2.with_angle(0 .. 45).output("m2_angle", "x.3a : non 45 degree angle m2") +via2.ongrid(0.005).output("via2_option_OFFGRID", "x.1b : option_OFFGRID vertex on via2") +via2.with_angle(0 .. 90).output("via2_angle", "x.2 : non 90 degree angle via2") +m3.ongrid(0.005).output("m3_option_OFFGRID", "x.1b : option_OFFGRID vertex on m3") +m3.with_angle(0 .. 45).output("m3_angle", "x.3a : non 45 degree angle m3") +via3.ongrid(0.005).output("via3_option_OFFGRID", "x.1b : option_OFFGRID vertex on via3") +via3.with_angle(0 .. 90).output("via3_angle", "x.2 : non 90 degree angle via3") +nsm.ongrid(0.005).output("nsm_option_OFFGRID", "x.1b : option_OFFGRID vertex on nsm") +nsm.with_angle(0 .. 45).output("nsm_angle", "x.3a : non 45 degree angle nsm") +m4.ongrid(0.005).output("m4_option_OFFGRID", "x.1b : option_OFFGRID vertex on m4") +m4.with_angle(0 .. 45).output("m4_angle", "x.3a : non 45 degree angle m4") +via4.ongrid(0.005).output("via4_option_OFFGRID", "x.1b : option_OFFGRID vertex on via4") +via4.with_angle(0 .. 90).output("via4_angle", "x.2 : non 90 degree angle via4") +m5.ongrid(0.005).output("m5_option_OFFGRID", "x.1b : option_OFFGRID vertex on m5") +m5.with_angle(0 .. 45).output("m5_angle", "x.3a : non 45 degree angle m5") +pad.ongrid(0.005).output("pad_option_OFFGRID", "x.1b : option_OFFGRID vertex on pad") +pad.with_angle(0 .. 45).output("pad_angle", "x.3a : non 45 degree angle pad") +mf.ongrid(0.005).output("mf_option_OFFGRID", "x.1b : option_OFFGRID vertex on mf") +mf.with_angle(0 .. 90).output("mf_angle", "x.2 : non 90 degree angle mf") +hvi.ongrid(0.005).output("hvi_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvi") +hvi.with_angle(0 .. 45).output("hvi_angle", "x.3a : non 45 degree angle hvi") +hvntm.ongrid(0.005).output("hvntm_option_OFFGRID", "x.1b : option_OFFGRID vertex on hvntm") +hvntm.with_angle(0 .. 45).output("hvntm_angle", "x.3a : non 45 degree angle hvntm") +vhvi.ongrid(0.005).output("vhvi_option_OFFGRID", "x.1b : option_OFFGRID vertex on vhvi") +vhvi.with_angle(0 .. 45).output("vhvi_angle", "x.3a : non 45 degree angle vhvi") +uhvi.ongrid(0.005).output("uhvi_option_OFFGRID", "x.1b : option_OFFGRID vertex on uhvi") +uhvi.with_angle(0 .. 45).output("uhvi_angle", "x.3a : non 45 degree angle uhvi") +pwell_rs.ongrid(0.005).output("pwell_rs_option_OFFGRID", "x.1b : option_OFFGRID vertex on pwell_rs") +pwell_rs.with_angle(0 .. 45).output("pwell_rs_angle", "x.3a : non 45 degree angle pwell_rs") +areaid_re.ongrid(0.005).output("areaid_re_option_OFFGRID", "x.1b : option_OFFGRID vertex on areaid.re") + +end #option_OFFGRID +logger.info(" ") +logger.info("Cell exclusion list:") +logger.info(" rule | cell") +logger.info(" nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram") +logger.info(" nsd.1 | sram") +logger.info(" nsd.2 | sram") +logger.info(" psd.1 | sram") +logger.info(" psd.2 | sram") +logger.info(" ") +logger.info("release #{release}") diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/drc_sky130.lydrc b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/drc_sky130.lydrc new file mode 100755 index 000000000..68a49f4bc --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/drc_sky130.lydrc @@ -0,0 +1,878 @@ + + + + + drc + + + + false + false + + true + drc_scripts + tools_menu.drc.end + dsl + drc-dsl-xml + # +# DRC for SKY130 according to : +# https://skywater-pdk.readthedocs.io/en/latest/rules/periphery.html +# https://skywater-pdk.readthedocs.io/en/latest/rules/layers.html +# +# Distributed under GNU GPLv3: https://www.gnu.org/licenses/ +# +# History : +# 2020-10-04 : v1.0 : initial release +# +########################################################################################## +tstart = Time.now + +# optionnal for a batch launch : klayout -b -rd input=my_layout.gds -rd report=sky130_drc.txt -r drc_sky130.drc +if $input + source($input) +end + +if $report +# report($report) + report("SKY130 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), $report)) +else + report("SKY130 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "sky130_drc.txt")) +end + +AL = true # do not change +CU = false # do not change +# choose betwen only one of AL or CU back-end flow here : +backend_flow = AL + +# enable / disable rule groups +FEOL = true # front-end-of-line checks +BEOL = true # back-end-of-line checks +OFFGRID = true # manufacturing grid/angle checks + +# klayout setup +######################## +# use a tile size of 1mm - not used in deep mode- +tiles(1000.um) +# use a tile border of 10 micron: +tile_borders(1.um) +#no_borders + +# hierachical +deep + +# use 4 cpu cores +threads(4) +# if more inof is needed, set true +verbose(false) + +# layers definitions +######################## +diff = input(65, 20) +tap = polygons(65, 44) +nwell = polygons(64, 20) +dnwell = polygons(64, 18) +pwbm = polygons(19, 44) +pwde = polygons(124, 20) +natfet = polygons(124, 21) +hvtr = polygons(18, 20) +hvtp = polygons(78, 44) +ldntm = polygons(11, 44) +hvi = polygons(75, 20) +tunm = polygons(80, 20) +lvtn = polygons(125, 44) +poly = polygons(66, 20) +hvntm = polygons(125, 20) +nsdm = polygons(93, 44) +psdm = polygons(94, 20) +rpm = polygons(86, 20) +urpm = polygons(79, 20) +npc = polygons(95, 20) +licon = polygons(66, 44) +li = input(67, 20) +mcon = polygons(67, 44) +m1 = polygons(68, 20) +via = polygons(68, 44) +m2 = polygons(69, 20) +via2 = polygons(69, 44) +m3 = polygons(70, 20) +via3 = polygons(70, 44) +m4 = polygons(71, 20) +via4 = polygons(71, 44) +m5 = polygons(72, 20) +pad = polygons(76, 20) +nsm = polygons(61, 20) +capm = polygons(89, 44) +cap2m = polygons(97, 44) +vhvi = polygons(74, 21) +uhvi = polygons(74, 22) +npn = polygons(82, 20) +inductor = polygons(82, 24) +vpp = polygons(82, 64) +pnp = polygons(82, 44) +lvs_prune = polygons(84, 44) +ncm = polygons(92, 44) +padcenter = polygons(81, 20) +mf = polygons(76, 44) +areaid_sl = polygons(81, 1) +areaid_ce = polygons(81, 2) +areaid_fe = polygons(81, 3) +areaid_sc = polygons(81, 4) +areaid_sf = polygons(81, 6) +areaid_sw = polygons(81, 7) +areaid_sr = polygons(81, 8) +areaid_mt = polygons(81, 10) +areaid_dt = polygons(81, 11) +areaid_ft = polygons(81, 12) +areaid_ww = polygons(81, 13) +areaid_ld = polygons(81, 14) +areaid_ns = polygons(81, 15) +areaid_ij = polygons(81, 17) +areaid_zr = polygons(81, 18) +areaid_ed = polygons(81, 19) +areaid_de = polygons(81, 23) +areaid_rd = polygons(81, 24) +areaid_dn = polygons(81, 50) +areaid_cr = polygons(81, 51) +areaid_cd = polygons(81, 52) +areaid_st = polygons(81, 53) +areaid_op = polygons(81, 54) +areaid_en = polygons(81, 57) +areaid_en20 = polygons(81, 58) +areaid_le = polygons(81, 60) +areaid_hl = polygons(81, 63) +areaid_sd = polygons(81, 70) +areaid_po = polygons(81, 81) +areaid_it = polygons(81, 84) +areaid_et = polygons(81, 101) +areaid_lvt = polygons(81, 108) +areaid_re = polygons(81, 125) +areaid_ag = polygons(81, 79) +poly_rs = polygons(66, 13) +diff_rs = polygons(65, 13) +pwell_rs = polygons(64, 13) +li_rs = polygons(67, 13) +cfom = polygons(22, 20) + + +# Define a new custom function that selects polygons by their number of holes: +# It will return a new layer containing those polygons with min to max holes. +# max can be nil to omit the upper limit. +class DRC::DRCLayer + def with_holes(min, max) + new_data = RBA::Region::new + self.data.each do |p| + if p.holes >= (min || 0) && (!max || p.holes <= max) + new_data.insert(p) + end + end + DRC::DRCLayer::new(@engine, new_data) + end +end + +# DRC section +######################## +info("DRC section") + +if FEOL +info("FEOL section") +gate = diff & poly + +# dnwell +dnwell.width(3.0, euclidian).output("dnwell.2", "dnwell.2 : min. dnwell width : 3.0um") +dnwell.not(uhvi).not(areaid_po).isolated(6.3, euclidian).output("dnwell.3", "dnwell.3 : min. dnwell spacing : 6.3um") +dnwell.and(pnp).output("dnwell.4", "dnwell.4 : dnwell must not overlap pnp") +dnwell.and(psdm).edges.not(psdm.edges).output("dnwell.5", "p+ must not straddle dnwell") +# dnwell.6 rue not coded + +# nwell +nwell.width(0.84, euclidian).output("nwell.1", "nwell.1 : min. nwell width : 0.84um") +nwell.space(1.27, euclidian).output("nwell.2a", "nwell.2a : min. nwell spacing (merged if less) : 1.27um") +# rule nwell.4 is suitable for digital cells +#nwell.not(uhvi).not(areaid_en20).not_interacting(tap.and(licon).and(li)).output("nwell.4", "nwell4 : all nwell exempt inside uhvi must contain a n+tap") +nwell.enclosing(dnwell.not(uhvi).not(areaid_po), 0.4, euclidian).output("nwell.5", "nwell.5 : min. nwell enclosing dnwell exempt unside uhvi : 0.4um") +dnwell.enclosing(nwell.not(uhvi), 1.03, euclidian).output("nwell.6", "nwell.6 : min. dnwell enclosing nwell exempt unside uhvi : 1.03um") +dnwell.separation(nwell, 4.5, euclidian).output("nwell.7", "nwell.7 : min. dnwell separation nwell : 4.5um") + +# pwbm +pwbm.not(uhvi).output("pwbm", "pwbm must be inside uhvi") +dnwell.and(uhvi).edges.not(pwbm).output("pwbm.4", "pwbm.4 : dnwell inside uhvi must be enclosed by pwbm") + +# pwde +pwde.not(pwbm).output("pwdem.3", "pwdem.3 : pwde must be inside pwbm") +pwde.not(uhvi).output("pwdem.4", "pwdem.4 : pwde must be inside uhvi") +pwde.not(dnwell).output("pwdem.5", "pwdem.5 : pwde must be inside dnwell") + +# hvtp +#hvtp.not(nwell).output("hvtp", "hvtp must inside nwell") +hvtp.width(0.38, euclidian).output("hvtp.1", "hvtp.1 : min. hvtp width : 0.38um") +hvtp.space(0.38, euclidian).output("hvtp.2", "hvtp.2 : min. hvtp spacing : 0.38um") +hvtp.enclosing(gate.and(psdm), 0.18, euclidian).output("hvtp.3", "hvtp.3 : min. hvtp enclosure of pfet gate : 0.18um") +hvtp.separation(gate.and(psdm), 0.18, euclidian).output("hvtp.4", "hvtp.4 : min. hvtp spacing pfet gate: 0.18um") +hvtp.with_area(0..0.265).output("hvtp.5", "hvtp.5 : min. hvtp area : 0.265um²") + +# hvtr +hvtr.width(0.38, euclidian).output("hvtr.1", "hvtr.1 : min. hvtr width : 0.38um") +hvtr.isolated(0.38, euclidian).output("hvtr.2", "hvtr.2 : min. hvtr spacing : 0.38um") + +# lvtn +lvtn.width(0.38, euclidian).output("lvtn.1", "lvtn.1 : min. lvtn width : 0.38um") +lvtn.space(0.38, euclidian).output("lvtn.2", "lvtn.2 : min. lvtn spacing : 0.38um") +lvtn.separation(diff.and(poly).not(uhvi), 0.18, euclidian).output("lvtn.3a", "lvtn.3a : min. lvtn spacing to gate : 0.18um") +lvtn.separation(diff.and(nwell).not(poly), 0.235, projection).output("lvtn.3b", "lvtn.3b : min. lvtn spacing to pfet s/d : 0.18um") +lvtn.enclosing(gate.not(uhvi), 0.18, euclidian).output("lvtn.4b", "lvtn.4b : min. lvtn enclosing to gate : 0.18um") +lvtn.separation(hvtp, 0.38, euclidian).output("lvtn.9", "lvtn.9 : min. lvtn spacing hvtp : 0.38um") +nwell.not_interacting(gate.and(nwell.not(hvi).not(areaid_ce))).enclosing(lvtn.not(uhvi), 0.18, euclidian).polygons.without_area(0).output("lvtn.4b", "lvtn.4b : min. lvtn enclosure of gate : 0.18um") +lvtn.separation(nwell.inside(areaid_ce), 0.38, euclidian).output("lvtn.12", "lvtn.12 : min. lvtn spacing nwell inside areaid.ce : 0.38um") +lvtn.with_area(0..0.265).output("lvtn.13", "lvtn.13 : min. lvtn area : 0.265um²") + +# ncm +ncm.and(tap.and(nwell).or(diff.not(nwell))).output("ncm.x.3", "ncm.x.3 : ncm must not overlap n+diff") +ncm.width(0.38, euclidian).output("ncm.1", "ncm.1 : min. ncm width : 0.38um") +ncm.space(0.38, euclidian).output("ncm.2", "ncm.2 : min. ncm spacing manual merge if smaller : 0.38um") +ncm.enclosing(diff.and(nwell), 0.18, euclidian).output("ncm.3", "ncm.3 : min. ncm enclosure of p+diff : 0.18um") +ncm.separation(lvtn.and(diff), 0.23, euclidian).output("ncm.5", "ncm.5 : min. ncm spacing lvtn diff : 0.23um") +ncm.separation(diff.not(nwell), 0.2, euclidian).output("ncm.6", "ncm.6 : min. ncm spacing nfet : 0.2um") +ncm.with_area(0..0.265).output("ncm.7", "ncm.13 : min. ncm area : 0.265um²") + +# diff-tap +difftap = diff + tap +difftap.width(0.15, euclidian).output("difftap.1", "difftap.1 : min. difftap width : 0.15um") +not_in_cell1 = layout(source.cell_obj).select("s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b" , "-s8fpls_pl8", "-s8fpls_rdrv4" , "-s8fpls_rdrv4f", "-s8fpls_rdrv8") +not_in_cell1_diff = not_in_cell1.input(65, 20) +not_in_cell1_diff.not(areaid_sc).not(poly).edges.and(gate.edges).with_length(0,0.42).output("difftap.2", "difftap.2: min. gate (exempt areaid.sc) width : 0.42um") +diff.and(areaid_sc).not(poly).edges.and(gate.edges).with_length(0,0.36).output("difftap.2", "difftap.2: min. gate inside areaid.sc width : 0.36um") +difftap.space(0.27, euclidian).output("difftap.3", "difftap.3 : min. difftap spacing : 0.27um") +tap.edges.and(diff.edges).with_length(0,0.29).output("difftap.4", "difftap.4 : min. tap bound by diffusion : 0.29um") +tap.edges.and(diff.edges).space(0.4, projection).output("difftap.5", "difftap.5 : min. tap bound by 2 diffusions : 0.4um") +(tap.edges.and(diff.edges)).extended(0.01, 0.01, 0, 0, false).not(tap.and(diff)).and(diff.or(tap)).output("difftap.6", "difftap.6 : diff and tap not allowed to extend beyong their abutting ege") +tap.edges.not_interacting(diff.edges).separation(diff.edges, 0.13, euclidian).output("difftap.7", "difftap.7 : min. diff/tap spacing to non-coincident diff edge : 0.13um") +diff.edges.not_interacting(tap.edges).separation(tap.edges, 0.13, euclidian).output("difftap.7", "difftap.7 : min. diff/tap spacing to non-coincident tap edge : 0.13um") +nwell.enclosing(diff.not(uhvi).and(psdm), 0.18, euclidian).output("difftap.8", "difftap.8 : min. p+diff enclosure by nwell : 0.18um") +diff.not(uhvi).and(nsdm).separation(nwell, 0.34, euclidian).output("difftap.9", "difftap.9 : min. n+diff spacing to nwell : 0.34um") +nwell.enclosing(tap.not(uhvi).and(nsdm), 0.18, euclidian).output("difftap.10", "difftap.10 : min. n+tap enclosure by nwell : 0.18um") +tap.not(uhvi).and(psdm).separation(nwell, 0.13, euclidian).output("difftap.11", "difftap.11 : min. p+tap spacing to nwell : 0.13um") + +# tunm +tunm.width(0.41, euclidian).output("tunm.1", "tunm.1 : min. tunm width : 0.41um") +tunm.isolated(0.5, euclidian).output("tunm.2", "tunm.2 : min. tunm spacing : 0.5um") +tunm.enclosing(gate, 0.095, euclidian).output("tunm.3", "tunm.3 : min. tunm beyond gate : 0.095um") +tunm.separation(gate.not_interacting(tunm), 0.095, euclidian).output("tunm.4", "tunm.4 : min. tunm spacing to gate outside tunm: 0.095um") +gate.and(tunm).edges.not(gate.edges).output("tunm.5", "tunm.5 : gate must not straddle tunm") +tunm.not(dnwell).output("tunm.6a", "tunm.6a : tunm not allowed outside dnwell") +tunm.with_area(0..0.672).output("tunm.7", "tunm.7 : min. tunm area : 0.672um²") + +# poly +poly.width(0.15, euclidian).output("poly.1a", "poly.1a : min. poly width : 0.15um") +poly.not(diff).edges.and(gate.and(lvtn).edges).space(0.35, euclidian).output("poly.1b", "poly.1b: min. lvtn gate width : 0.35um") +poly.space(0.21, euclidian).output("poly.2", "poly.2 : min. poly spacing : 0.21um") +poly.and(rpm.or(urpm).or(poly_rs)).width(0.33, euclidian).output("poly.3", "poly.3 : min. poly resistor width : 0.33um") +poly.not(gate).separation(diff, 0.075, projection).polygons.without_area(0).output("poly.4", "poly.4 : min. poly on field spacing to diff : 0.075um") +poly.not(gate).separation(tap, 0.055, euclidian).output("poly.5", "poly.5 : min. poly on field spacing to tap : 0.055um") +gate.separation(tap, 0.3, projection).polygons.and(diff).output("poly.6", "poly.6 : min. gate spacing to tap : 0.3um") +diff.enclosing(gate, 0.25, projection).polygons.without_area(0).output("poly.7", "poly.7 : min. source/drain length : 0.25um") +poly.enclosing(gate, 0.13, projection).polygons.without_area(0).output("poly.8", "poly.8 : min. poly extention gate (endcap) : 0.13um") +poly.and(rpm.or(urpm).or(poly_rs)).separation(poly.or(difftap), 0.48, euclidian).polygons.without_area(0).output("poly.9", "poly.9 : min. poly resistor space to poly or diff/tap : 0.48um") +diff.merged.edges.end_segments(0.01).and(poly).output("poly.10", "poly.10 : poly must not overlap diff corner") +gate.with_angle(0 .. 90).output("poly.11", "poly.11 : non 90 degree angle gate") +not_in_cell3 = layout(source.cell_obj).select("s8fgvr_n_fg2") +not_in_cell3_poly = not_in_cell3.input(66, 20) +not_in_cell3_poly.not(hvi).not(nwell.not(hvi)).and(tap).output("poly.12", "poly.12 : poly must not overlap tap") +poly.and(diff_rs).output("poly.15", "poly.15 : poly must not overlap diff resistor") + +# rpm +rpm.width(1.27, euclidian).output("rpm.1a", "rpm.1a : min. rpm width : 1.27um") +rpm.space(0.84, euclidian).output("rpm.2", "rpm.2 : min. rpm spacing : 0.84um") +rpm.enclosing(poly.and(poly_rs).and(psdm), 0.2, euclidian).output("rpm.3", "rpm.3 : min. rpm enclosure of poly resistor : 0.2um") +psdm.enclosing(poly.and(poly_rs).and(rpm), 0.11, euclidian).output("rpm.4", "rpm.4 : min. psdm enclosure of poly resistor : 0.11um") +npc.enclosing(poly.and(poly_rs).and(rpm), 0.095, euclidian).output("rpm.5", "rpm.5 : min. npc enclosure of poly resistor : 0.095um") +rpm.separation(nsdm, 0.2, euclidian).output("rpm.6", "rpm.6 : min. rpm spacing nsdm: 0.2um") +rpm.separation(poly, 0.2, euclidian).output("rpm.7", "rpm.7 : min. rpm spacing poly: 0.2um") +rpm.and(poly).edges.not(poly.edges).output("rpm.8", "rpm.8 : poly must not straddle rpm") +poly.and(poly_rs).and(rpm).separation(hvntm, 0.185, euclidian).output("rpm.9", "rpm.9 : min. poly resistor spacing hvntm: 0.185um") +rpm.and(pwbm).output("rpm.10", "rpm.107 : min. rpm spacing pwbm: na") + +# varac +varac = poly & tap & (nwell - hvi) - areaid_ce +tap.not(poly).edges.and(varac.edges).space(0.18, euclidian).output("varac.1", "varac.1: min. varac channel length : 0.18um") +tap.and(poly).edges.and(varac.edges).space(1.0, euclidian).output("varac.2", "varac.2: min. varac channel wdth : 1.0um") +varac.separation(hvtp, 0.18, euclidian).output("varac.3", "varac.3: min. varac channel space to hvtp : 0.18um") +varac.separation(licon.and(tap), 0.25, euclidian).output("varac.4", "varac.4: min. varac channel space to licon on tap : 0.25um") +nwell.enclosing(poly.overlapping(varac), 0.15, euclidian).output("varac.5", "varac.5: min. nwell enclosure of poly overlapping varac channel : 0.15um") +tap.overlapping(varac).separation(difftap, 0.27, euclidian).polygons.without_area(0).output("varac.6", "varac.6: min. varac channel tap space to difftap : 0.27um") +nwell.overlapping(varac).and(diff.and(nwell)).output("varac.7", "varac.7: nwell overlapping varac channel must not overlap p+diff") + +# photo +photodiode = dnwell & areaid_po +photodiode.edges.without_length(3.0).output("photo.2", "photo.2 : minimum/maximum width of photodiode : 3.0um") +photodiode.space(5.0, euclidian).output("photo.3", "photo.3 : mini. photodiode spacing : 5.0um") +photodiode.separation(dnwell, 5.3, euclidian).output("photo.4", "photo.4 : mini. photodiode spacing to dnwell : 5.3um") +areaid_po.not(dnwell).output("photo.5.6", "photo.5.6 : photodiode edges must coincide areaid.po and enclosed by dnwell") +photodiode.not(tap.not(nwell).holes).output("photo.7", "photo.7 : photodiode must be enclosed by p+tap ring") +photodiode.and(nwell).edges.without_length(0.84).output("photo.8", "photo.8 : minimum/maximum width of nwell inside photodiode : 0.84um") +areaid_po.edges.and(photodiode.and(nwell).sized(1.08)).without_length(12.0).output("photo.9", "photo.9 : minimum/maximum enclosure of nwell by photodiode : 1.08um") +photodiode.and(tap).edges.without_length(0.41).output("photo.10", "photo.10 : minimum/maximum width of tap inside photodiode : 0.41um") + +# npc +npc.width(0.27, euclidian).output("npc.1", "npc.1 : min. npc width : 0.27um") +npc.space(0.27, euclidian).output("npc.2", "npc.2 : min. npc spacing, should be mnually merge if less : 0.27um") +npc.separation(gate, 0.09, euclidian).output("npc.4", "npc.4 : min. npc spacing to gate : 0.09um") + +# nsdm/psdm +npsdm = nsdm + psdm +nsdm.width(0.38, euclidian).output("nsdm.1", "nsdm.1 : min. nsdm width : 0.38um") +psdm.width(0.38, euclidian).output("psdm.1", "psdm.1 : min. psdm width : 0.38um") +nsdm.space(0.38, euclidian).output("n/psdm.1", "n/psdm.1 : min. nsdm spacing, should be mnually merge if less : 0.38um") +psdm.space(0.38, euclidian).output("n/psdm.1", "n/psdm.1 : min. psdm spacing, should be mnually merge if less : 0.38um") +npsdm.enclosing(diff, 0.125, euclidian).polygons.not(tap.sized(0.125)).output("n/psdm.5a", "n/psdm.5a : min. n/psdm enclosure diff except butting edge : 0.125um") +npsdm.enclosing(tap, 0.125, euclidian).polygons.not(diff.sized(0.125)).output("n/psdm.5b", "n/psdm.5b : min. n/psdm enclosure tap except butting edge : 0.125um") +tap.edges.and(diff.edges).not(npsdm).output("n/psdm.6", "n/psdm.6 : min. n/psdm enclosure of butting edge : 0.0um") +nsdm.and(difftap).separation(psdm.and(difftap), 0.13, euclidian).polygons.without_area(0).output("n/psdm.7", "n/psdm.7 : min. nsdm diff spacing to psdm diff except butting edge : 0.13um") +diff.and((nsdm.and(nwell)).or(psdm.not(nwell))).output("n/psdm.8", "n/psdm.8 : diff should be the opposite type of well/substrate underneath") +tap.and((nsdm.not(nwell)).or(psdm.and(nwell))).output("n/psdm.8", "n/psdm.8 : tap should be the same type of well/substrate underneath") +tap.and(diff).without_area(0).output("tap and diff", "tap and diff must not overlap") +nsdm.with_area(0..0.265).output("n/psdm.10a", "n/psdm.10a : min. nsdm area : 0.265um²") +psdm.with_area(0..0.265).output("n/psdm.10b", "n/psdm.10b : min. psdm area : 0.265um²") + +# licon +licon.not(poly.interacting(poly_rs)).edges.without_length(0.17).output("licon.1", "licon.1 : minimum/maximum width of licon : 0.17um") +licon.and(poly.interacting(poly_rs)).not_interacting((licon.and(poly.interacting(poly_rs)).edges.with_length(0.19)).or(licon.and(poly.interacting(poly_rs)).edges.with_length(2.0))).output("licon.1b/c", "licon.1b/c : minimum/maximum width/length of licon inside poly resistor : 2.0/0.19um") +licon.space(0.17, euclidian).output("licon.2", "licon.2 : min. licon spacing : 0.17um") +licon.and(poly.interacting(poly_rs)).edges.with_length(0.19).space(0.35, euclidian).output("licon.2b", "licon.2b : min. licon 0.19um edge on resistor spacing : 0.35um") +licon.interacting(licon.and(poly.interacting(poly_rs)).edges.with_length(2.0)).separation(licon.and(poly.interacting(poly_rs)), 0.51, euclidian).output("licon.2c", "licon.2c : min. licon 2.0um edge on resistor spacing : 0.51um") +licon.and(poly.interacting(poly_rs)).separation(licon.not(poly.interacting(poly_rs)), 0.51, euclidian).output("licon.2d", "licon.2d : min. licon on resistor spacing other licon : 0.51um") +# rule licon.3 not coded +licon.not(li).not(poly.or(diff).or(tap)).output("licon.4", "licon.4 : min. licon must overlap li and (poly or tap or diff) ") +diff.enclosing(licon, 0.04, euclidian).output("licon.5", "licon.5 : min. diff enclosure of licon : 0.04um") +tap.edges.and(diff.edges).separation(licon.and(tap).edges, 0.06, euclidian).output("licon.6", "licon.6 : min. abutting edge spacing to licon tap : 0.06um") +licon_edges_with_less_enclosure_tap = tap.enclosing(licon, 0.12, projection).second_edges +opposite1 = (licon.edges - licon_edges_with_less_enclosure_tap).width(0.17 + 1.dbu, projection).polygons +licon.not_interacting(opposite1).output("licon.7", "licon.7 : min. tap enclosure of licon by one of 2 opposite edges : 0.12um") +poly.enclosing(licon, 0.05, euclidian).output("licon.8", "licon.8 : min. poly enclosure of licon : 0.05um") +licon008 = licon.interacting(poly.enclosing(licon, 0.08, euclidian).polygons) +licon_edges_with_less_enclosure_poly = poly.enclosing(licon, 0.08, projection).second_edges +opposite2 = (licon.edges - licon_edges_with_less_enclosure_poly).width(0.17 + 1.dbu, projection).polygons +licon008.not_interacting(opposite2).output("licon.8a", "licon.8a : min. poly enclosure of licon by one of 2 opposite edges : 0.08um") +# rule licon.9 not coded +licon.and(tap.and(nwell.not(hvi))).separation(varac, 0.25, euclidian).output("licon.10", "licon.10 : min. licon spacing to varac channel : 0.25um") +not_in_cell4 = layout(source.cell_obj).select("-s8fs_gwdlvx4", "-s8fs_gwdlvx8", "-s8fs_hvrsw_x4", "-s8fs_hvrsw8", "-s8fs_hvrsw264", "-s8fs_hvrsw520", "-s8fs_rdecdrv", "-s8fs_rdec8”, “s8fs_rdec32", "-s8fs_rdec264", "-s8fs_rdec520") +not_in_cell4_licon = not_in_cell4.input(66, 44) +not_in_cell4_licon.and(diff.or(tap)).separation(gate.not(areaid_sc), 0.055, euclidian).output("licon.11", "licon.11 : min. licon spacing to gate : 0.055um") +licon.and(diff.or(tap)).separation(gate.and(areaid_sc), 0.05, euclidian).output("licon.11a", "licon.11a : min. licon spacing to gate inside areaid.sc : 0.05um") +in_cell4 = layout(source.cell_obj).select("+s8fs_gwdlvx4", "+s8fs_gwdlvx8", "+s8fs_hvrsw_x4", "+s8fs_hvrsw8", "+s8fs_hvrsw264", "+s8fs_hvrsw520") +in_cell4_licon = in_cell4.input(66, 44) +in_cell4_licon.and(diff.or(tap)).separation(gate, 0.04, euclidian).output("licon.11c", "licon.11c : min. licon spacing to gate for specific cells: 0.04um") +# rules 11.b , 11.d not coded +diff.interacting(gate).not(diff.interacting(gate).width(5.7, euclidian).polygons).output("licon.12", "licon.12 : max. sd width without licon : 5.7um") +licon.and(diff.or(tap)).separation(npc, 0.09, euclidian).output("licon.13", "licon.13 : min. difftap licon spacing to npc : 0.09um") +licon.and(poly).separation(diff.or(tap), 0.19, euclidian).output("licon.14", "licon.14 : min. poly licon spacing to difftap : 0.19um") +npc.enclosing(licon.and(poly), 0.1, euclidian).output("licon.15", "licon.15 : min. npc enclosure of poly-licon : 0.1um") +# rule licon.16 not applicable for the diff for the nmos of a nand gates or the pmos of a nor gates +#diff.not(gate).not_interacting(licon).output("licon.16", "licon.16 : diff must enclose one licon") +tap.not(uhvi).not_interacting(licon).output("licon.16", "licon.16 : tap must enclose one licon") +poly.and(tap).edges.not(tap.edges).output("licon.17", "licon.17 : tap must not straddle poly") +npc.not_interacting(licon.and(poly)).output("licon.18", "licon.18 : npc mut enclosed one poly-licon") + +# li +not_in_cell5 = layout(source.cell_obj).select("-s8rf2_xcmvpp_hd5_*") +not_in_cell5_li = not_in_cell5.input(67, 20) +not_in_cell5_li.width(0.17, euclidian).output("li.1", "li.1 : min. li width : 0.17um") +in_cell5 = layout(source.cell_obj).select("+s8rf2_xcmvpp_hd5_*") +in_cell5_li = in_cell5.input(67, 20) +in_cell5_li.width(0.14, euclidian).output("li.1a", "li.1a : min. li width for the cells s8rf2_xcmvpp_hd5_* : 0.14um") +# rule li.2 not coded +not_in_cell5_li.isolated(0.17, euclidian).output("li.3", "li.3 : min. li spacing : 0.17um") +in_cell5_li.space(0.14, euclidian).output("li.3a", "li.3a : min. li spacing for the cells s8rf2_xcmvpp_hd5_* : 0.14um") +licon08 = licon.interacting(li.enclosing(licon, 0.08, euclidian).polygons) +licon_edges_with_less_enclosure_li = li.enclosing(licon, 0.08, projection).second_edges +opposite3 = (licon.edges - licon_edges_with_less_enclosure_li).width(0.17 + 1.dbu, projection).polygons +licon08.not_interacting(opposite3).output("li.5", "li.5 : min. li enclosure of licon of 2 opposite edges : 0.08um") +li.with_area(0..0.0561).output("li.6", "li.6 : min. li area : 0.0561um²") + +# vpp +vpp.width(1.43, euclidian).output("vpp.1", "vpp.1 : min. vpp width : 1.43um") +# rules 1.b, 1.c not coded +vpp.and(poly.or(difftap)).output("vpp.3", "vpp.3 : vpp must not overlapp poly or diff or tap") +vpp.and(nwell).edges.not(vpp.edges).output("vpp.4", "vpp.4 : vpp must not straddle nwell") +vpp.and(dnwell).edges.not(vpp.edges).output("vpp.4", "vpp.4 : vpp must not straddle dnwell") +vpp.and(poly.or(li).or(m1).or(m2)).separation(poly.or(li).or(m1).or(m2), 1.5, euclidian).polygons.with_area(2.25,nil).output("vpp.5", "vpp.5 : min. vpp spacing to poly or li or m1 or m2 : 1.5um") +vpp.with_area(0..area(vpp.and(m3))*0.25).output("vpp.5a", "vpp.5a : max. m3 density in vpp : 0.25") +vpp.with_area(0..area(vpp.and(m4))*0.3).output("vpp.5b", "vpp.5b : max. m4 density in vpp : 0.3") +vpp.with_area(0..area(vpp.and(m5))*0.4).output("vpp.5c", "vpp.5c : max. m5 density in vpp : 0.4") +nwell.enclosing(vpp, 1.5, euclidian).output("vpp.8", "vpp.8 : nwell enclosure of vpp : 1.5") +vpp.separation(nwell, 1.5, euclidian).polygons.without_area(0).output("vpp.9", "vpp.9 : vpp spacing to nwell : 1.5") +# rule vpp.10 not coded +# rule vpp.11 not coded because moscap is not defined properly by any gds layer +# rules vpp.12a, 12b, 12c not coded because specific to one cell +if backend_flow = CU + m1.separation(vpp.and(m1), 0.16, euclidian).polygons.without_area(0).output("vpp.13", "vpp.13 : m1 spacing to m1inside vpp : 0.16") +end + +# CAPM +capm.width(1.0, euclidian).output("capm.1", "capm.1 : min. capm width : 1.0um") +capm.space(0.84, euclidian).output("capm.2a", "capm.2a : min. capm spacing : 0.84um") +m2.interacting(capm).isolated(1.2, euclidian).output("capm.2b", "capm.2b : min. capm spacing : 1.2um") +m2.enclosing(capm, 0.14, euclidian).output("capm.3", "capm.3 : min. m2 enclosure of capm : 0.14um") +capm.enclosing(via2, 0.14, euclidian).output("capm.4", "capm.4 : min. capm enclosure of via2 : 0.14um") +capm.separation(via2, 0.14, euclidian).output("capm.5", "capm.5 : min. capm spacing to via2 : 0.14um") +capm.sized(-20.0).sized(20.0).output("capm.6", "capm.6 : max. capm lenght/width : 20um") +capm.with_angle(0 .. 90).output("capm.7", "capm.7 : capm not rectangle") +capm.separation(via, 0.14, euclidian).polygons.without_area(0).output("capm.8", "capm.8 : min. capm spacing to via : 0.14um") +capm.and(nwell).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle nwell") +capm.and(diff).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle diff") +capm.and(tap).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle tap") +capm.and(poly).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle poly") +capm.and(li).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle li") +capm.and(m1).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle m1") +capm.separation(m2.not_interacting(capm), 0.14, euclidian).output("capm.11", "capm.11 : min. capm spacing to m2 not overlapping capm : 0.5um") + +end #FEOL + +if BEOL +info("BEOL section") + +# ct +mcon.edges.without_length(0.17).output("ct.1", "ct.1 : minimum/maximum width of mcon : 0.17um") +mcon.space(0.19, euclidian).output("ct.2", "ct.2 : min. mcon spacing : 0.19um") +# rule ct.3 not coded +mcon.not(li).output("ct.4", "ct.4 : mcon should covered by li") +if backend_flow = CU + li.interacting(li.and(m1).not(mcon).with_holes(1,10)).enclosing(mcon, 0.2, euclidian).output("ct.irdrop.1", "ct.irdrop.1 : min. li enclsoure of 1..10 mcon : 0.2um") + li.interacting(li.and(m1).not(mcon).with_holes(11,100)).enclosing(mcon, 0.3, euclidian).output("ct.irdrop.2", "ct.irdrop.2 : min. li enclsoure of 11..100 mcon : 0.3um") +end + +# m1 +huge_m1 = m1.sized(-1.5).sized(1.5) +m1.width(0.14, euclidian).output("m1.1", "m1.1 : min. m1 width : 0.14um") +m1.space(0.14, euclidian).output("m1.2", "m1.2 : min. m1 spacing : 0.14um") +huge_m1.separation(m1, 0.28, euclidian).output("m1.3ab", "m1.3ab : min. 3um.m1 spacing m1 : 0.28um") +not_in_cell6 = layout(source.cell_obj).select("-s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b", "-s8fpls_pl8", "-s8fs_cmux4_fm") +not_in_cell6_m1 = not_in_cell6.input(68, 20) +not_in_cell6_m1.enclosing(mcon, 0.03, euclidian).output("m1.4", "m1.4 : min. m1 enclosure of mcon : 0.03um") +in_cell6 = layout(source.cell_obj).select("+s8cell_ee_plus_sseln_a", "+s8cell_ee_plus_sseln_b", "+s8cell_ee_plus_sselp_a", "+s8cell_ee_plus_sselp_b", "+s8fpls_pl8", "+s8fs_cmux4_fm") +in_cell6_m1 = in_cell6.input(68, 20) +in_cell6_m1.enclosing(mcon, 0.005, euclidian).output("m1.4a", "m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um") +m1.with_area(0..0.083).output("m1.6", "m1.6 : min. m1 area : 0.083um²") +m1.holes.with_area(0..0.14).output("m1.7", "m1.7 : min. m1 holes area : 0.14um²") +if backend_flow = AL + mcon06 = mcon.interacting(poly.enclosing(m1, 0.06, euclidian).polygons) + mcon_edges_with_less_enclosure_m1 = m1.enclosing(mcon, 0.06, projection).second_edges + opposite4 = (mcon.edges - mcon_edges_with_less_enclosure_m1).width(0.17 + 1.dbu, projection).polygons + mcon06.not_interacting(opposite4).output("m1.5", "m1.5 : min. m1 enclosure of mcon of 2 opposite edges : 0.06um") + # rule m1.pd.1, rule m1.pd.2a, rule m1.pd.2b not coded +end +if bakend_flow = CU + m1.sized(-2.0).sized(2.0).output("m1.11", "m1.11 : max. m1 width after slotting : 4.0um") + # rule m1.12 not coded because inconsistent with m1.11 + # rule m1.13, m1.14, m1.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 +end + +# via +#rule via.3 not coded +via.not(m1).output("via.4c.5c", "via.4c.5c : m1 must enclose all via") +if backend_flow = AL + via.not(areaid_mt).edges.without_length(0.15).output("via.1a", "via.1a : minimum/maximum width of via : 0.15um") + via.and(areaid_mt).not_interacting((via.and(areaid_mt).edges.without_length(0.15)).or(via.and(areaid_mt).edges.without_length(0.23)).or(via.and(areaid_mt).edges.without_length(0.28))).output("via.1b", "via.1b : minimum/maximum width of via in areaid.mt: 0.15um or 0.23um or 0.28um") + via.space(0.17, euclidian).output("via.2", "via.2 : min. via spacing : 0.17um") + m1.enclosing(via.not_interacting(via.edges.without_length(0.15)), 0.055, euclidian).output("via.4a", "via.4a : min. m1 enclosure of 0.15um via : 0.055um") + m1.enclosing(via.not_interacting(via.edges.without_length(0.23)), 0.03, euclidian).output("via.4b", "via.4b : min. m1 enclosure of 0.23um via : 0.03um") + via1_edges_with_less_enclosure_m1 = m1.enclosing(via.not_interacting(via.edges.without_length(0.15)), 0.085, projection).second_edges + opposite5 = (via.not_interacting(via.edges.without_length(0.15)).edges - via1_edges_with_less_enclosure_m1).width(0.15 + 1.dbu, projection).polygons + via.not_interacting(via.edges.without_length(0.15)).not_interacting(opposite5).output("via1.5a", "via1.5a : min. m1 enclosure of 0.15um via of 2 opposite edges : 0.085um") + via2_edges_with_less_enclosure_m1 = m1.enclosing(via.not_interacting(via.edges.without_length(0.23)), 0.06, projection).second_edges + opposite6 = (via.not_interacting(via.edges.without_length(0.23)).edges - via2_edges_with_less_enclosure_m1).width(0.23 + 1.dbu, projection).polygons + via.not_interacting(via.edges.without_length(0.23)).not_interacting(opposite6).output("via1.5b", "via1.5b : min. m1 enclosure of 0.23um via of 2 opposite edges : 0.06um") +end +if backend_flow = CU + via.not(areaid_mt).edges.without_length(0.18).output("via.11", "via.11 : minimum/maximum width of via : 0.18um") + via.space(0.13, euclidian).output("via.12", "via.12 : min. via spacing : 0.13um") + # rule via.13 not coded because not understandable + via1_edges_with_less_enclosure_m1 = m1.enclosing(via, 0.04, projection).second_edges + opposite5 = (via.edges - via1_edges_with_less_enclosure_m1).width(0.18 + 1.dbu, projection).polygons + via.not_interacting(opposite5).output("via1.14", "via1.14 : min. m1 enclosure of 0.04um via of 2 opposite edges : 0.04um") + # rules via.irdrop.1, via.irdrop.2, via.irdrop.3, via.irdrop.4 not coded because not understandable +end + +# m2 +huge_m2 = m2.sized(-1.5).sized(1.5) +m2.width(0.14, euclidian).output("m2.1", "m2.1 : min. m2 width : 0.14um") +m2.space(0.14, euclidian).output("m2.2", "m2.2 : min. m2 spacing : 0.14um") +huge_m2.separation(m2, 0.28, euclidian).output("m2.3ab", "m2.3ab : min. 3um.m2 spacing m2 : 0.28um") +# rule m2.3c not coded +m2.with_area(0..0.0676).output("m2.6", "m2.6 : min. m2 area : 0.0676um²") +m2.holes.with_area(0..0.14).output("m2.7", "m2.7 : min. m2 holes area : 0.14um²") +via.not(m2).output("m2.via", "m2.via : m2 must enclose via") +if backend_flow = AL + m2.enclosing(via, 0.055, euclidian).output("m2.4", "m2.4 : min. m2 enclosure of via : 0.055um") + via_edges_with_less_enclosure_m2 = m2.enclosing(via, 0.085, projection).second_edges + error_corners = via_edges_with_less_enclosure_m2.width(angle_limit(100.0), 1.dbu) + via_interact = via.interacting(error_corners.polygons(1.dbu)) + via_interact.output("m2.5", "m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um") + # opposite7 = (via.edges - via_edges_with_less_enclosure_m2).width(0.14 + 1.dbu, projection).polygons + # via.not_interacting(opposite7).output("m2.5", "m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um") + # rule m2.pd.1, rule m2.pd.2a, rule m2.pd.2b not coded +end +if bakend_flow = CU + m2.sized(-2.0).sized(2.0).output("m2.11", "m2.11 : max. m2 width after slotting : 4.0um") + # rule m2.12 not coded because inconsistent with m2.11 + # rule m2.13, m2.14, m2.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 +end + +# via2 +#rule via233 not coded +via2.not(m2).output("via2", "via2 : m2 must enclose all via2") +if backend_flow = AL + via2.not(areaid_mt).edges.without_length(0.2).output("via2.1a", "via2.1a : minimum/maximum width of via2 : 0.2um") + via2.and(areaid_mt).not_interacting((via2.and(areaid_mt).edges.without_length(0.2)).or(via2.and(areaid_mt).edges.without_length(1.2)).or(via2.and(areaid_mt).edges.without_length(1.5))).output("via2.1b", "via2.1b : minimum/maximum width of via2 in areaid.mt: 0.2um or 1.2um or 1.5um") + via2.space(0.2, euclidian).output("via2.2", "via2.2 : min. via2 spacing : 0.2um") + m2.enclosing(via2, 0.04, euclidian).output("via2.4", "via2.4 : min. m2 enclosure of via2 : 0.04um") + m2.enclosing(via2.not_interacting(via2.edges.without_length(1.5)), 0.14, euclidian).output("via2.4a", "via2.4a : min. m2 enclosure of 1.5um via2 : 0.14um") + via2_edges_with_less_enclosure_m2 = m2.enclosing(via2, 0.085, projection).second_edges + opposite8 = (via2.edges - via2_edges_with_less_enclosure_m2).width(0.2 + 1.dbu, projection).polygons + via2.not_interacting(opposite8).output("via2.5", "via2.5 : min. m2 enclosure of via2 of 2 opposite edges : 0.085um") +end +if backend_flow = CU + via2.edges.without_length(0.21).output("via2.11", "via2.11 : minimum/maximum width of via2 : 0.21um") + via2.isolated(0.18, euclidian).output("via2.12", "via2.12 : min. via2 spacing : 0.18um") + # rule via2.13 not coded because not understandable, or not clear + m2.enclosing(via2, 0.035, euclidian).output("via2.14", "via2.14 : min. m2 enclosure of via2 : 0.035um") + # rules via2.irdrop.1, via2.irdrop.2, via2.irdrop.3, via2.irdrop.4 not coded because not understandable +end + +# m3 +huge_m3 = m3.sized(-1.5).sized(1.5) +m3.width(0.3, euclidian).output("m3.1", "m3.1 : min. m3 width : 0.3um") +m3.space(0.3, euclidian).output("m3.2", "m3.2 : min. m3 spacing : 0.3um") +huge_m3.separation(m3, 0.4, euclidian).output("m3.3ab", "m3.3ab : min. 3um.m3 spacing m3 : 0.4um") +# rule m3.3c not coded +m3.with_area(0..0.24).output("m3.6", "m3.6 : min. m2 area : 0.24um²") +via2.not(m3).output("m3.via2", "m3.via2 : m3 must enclose via2") +if backend_flow = AL + m3.enclosing(via2, 0.065, euclidian).output("m3.4", "m3.4 : min. m3 enclosure of via2 : 0.065um") + via2_edges_with_less_enclosure_m3 = m3.enclosing(via2, 0.085, projection).second_edges + opposite9 = (via2.edges - via2_edges_with_less_enclosure_m3).width(0.3 + 1.dbu, projection).polygons + via2.not_interacting(opposite9).output("m3.5", "m3.5 : min. m3 enclosure of via2 of 2 opposite edges : 0.085um") + # rule m3.pd.1, rule m3.pd.2a, rule m3.pd.2b not coded +end +if bakend_flow = CU + m3.holes.with_area(0..0.2).output("m3.7", "m3.7 : min. m2 holes area : 0.2um²") + m3.sized(-2.0).sized(2.0).output("m3.11", "m3.11 : max. m3 width after slotting : 4.0um") + # rule m3.12 not coded because inconsistent with m3.11 + # rule m3.13, m3.14, m3.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 +end + +# via3 +#rule via3.3 not coded +via3.not(m3).output("via3", "via3 : m3 must enclose all via3") +if backend_flow = AL + via3.not(areaid_mt).edges.without_length(0.2).output("via3.1a", "via3.1a : minimum/maximum width of via3 : 0.2um") + via3.and(areaid_mt).not_interacting((via3.and(areaid_mt).edges.without_length(0.2)).or(via3.and(areaid_mt).edges.without_length(0.8))).output("via3.1a", "via3.1a : minimum/maximum width of via3 in areaid.mt: 0.2um or 0.8um") + via3.space(0.2, euclidian).output("via3.2", "via3.2 : min. via3 spacing : 0.2um") + m3.enclosing(via3, 0.06, euclidian).output("via3.4", "via3.4 : min. m3 enclosure of via3 : 0.06um") + via3_edges_with_less_enclosure_m3 = m3.enclosing(via3, 0.09, projection).second_edges + opposite10 = (via3.edges - via3_edges_with_less_enclosure_m3).width(0.2 + 1.dbu, projection).polygons + via3.not_interacting(opposite10).output("via3.5", "via3.5 : min. m2 enclosure of via3 of 2 opposite edges : 0.09um") +end +if backend_flow = CU + via3.edges.without_length(0.21).output("via3.11", "via3.11 : minimum/maximum width of via3 : 0.21um") + via3.space(0.18, euclidian).output("via3.12", "via3.12 : min. via3 spacing : 0.18um") + m3.enclosing(via3, 0.055, euclidian).output("via3.13", "via3.13 : min. m3 enclosure of via3 : 0.055um") + # rule via3.14 not coded because not understandable, or not clear + # rules via3.irdrop.1, via3.irdrop.2, via3.irdrop.3, via3.irdrop.4 not coded because not understandable +end + +# nsm +nsm.width(3.0, euclidian).output("nsm.1", "nsm.1 : min. nsm width : 3.0um") +nsm.space(4.0, euclidian).output("nsm.2", "nsm.2 : min. nsm spacing : 4.0um") +nsm.enclosing(diff, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of diff : 3.0um") +nsm.enclosing(tap, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of tap : 3.0um") +nsm.enclosing(poly, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of poly : 3.0um") +nsm.enclosing(li, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of li : 3.0um") +nsm.enclosing(m1, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m1 : 3.0um") +nsm.enclosing(m2, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m2 : 3.0um") +nsm.enclosing(m3, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m3 : 3.0um") +nsm.enclosing(m4, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m4 : 3.0um") +nsm.enclosing(m5, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m5 : 3.0um") +nsm.enclosing(cfom, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of cfom : 3.0um") +if backend_flow = AL + nsm.separation(diff, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to diff : 1.0um") + nsm.separation(tap, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to tap : 1.0um") + nsm.separation(poly, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to poly : 1.0um") + nsm.separation(li, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to li : 1.0um") + nsm.separation(m1, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m1 : 1.0um") + nsm.separation(m2, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m2 : 1.0um") + nsm.separation(m3, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m3 : 1.0um") + nsm.separation(m4, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m4 : 1.0um") + nsm.separation(m5, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m5 : 1.0um") + nsm.separation(cfom, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to cfom : 1.0um") +end + +# m4 +huge_m4 = m4.sized(-1.5).sized(1.5) +m4.width(0.3, euclidian).output("m4.1", "m4.1 : min. m4 width : 0.3um") +m4.space(0.3, euclidian).output("m4.2", "m4.2 : min. m4 spacing : 0.3um") +m4.with_area(0..0.24).output("m4.4", "m4.4 : min. m2 area : 0.24um²") +huge_m4.separation(m4, 0.4, euclidian).output("m4.5ab", "m4.5ab : min. 3um.m4 spacing m4 : 0.4um") +via3.not(m4).output("m4.via3", "m4.via3 : m4 must enclose via3") +if backend_flow = AL + m4.enclosing(via3, 0.065, euclidian).output("m4.3", "m4.3 : min. m4 enclosure of via3 : 0.065um") + via3_edges_with_less_enclosure_m4 = m4.enclosing(via2, 0.085, projection).second_edges + opposite9 = (via3.edges - via3_edges_with_less_enclosure_m4).width(0.3 + 1.dbu, projection).polygons + via3.not_interacting(opposite9).output("m4.5", "m4.5 : min. m4 enclosure of via3 of 2 opposite edges : 0.085um") + # rule m4.pd.1, rule m4.pd.2a, rule m4.pd.2b not coded +end +if bakend_flow = CU + m4.holes.with_area(0..0.2).output("m4.7", "m4.7 : min. m2 holes area : 0.2um²") + m4.sized(-5.0).sized(5.0).output("m4.11", "m4.11 : max. m4 width after slotting : 10.0um") + # rule m4.12 not coded because inconsistent with m4.11 + # rule m4.13, m4.14, m4.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759 + m4.enclosing(via3, 0.06, euclidian).output("m4.15", "m4.15 : min. m4 enclosure of via3 : 0.06um") +end + +# via4 +via4.edges.without_length(0.8).output("via4.1a", "via4.1a : minimum/maximum width of via4 : 0.8um") +via4.space(0.8, euclidian).output("via4.2", "via4.2 : min. via4 spacing : 0.8um") +#rule via4.3 not coded +m4.enclosing(via4, 0.19, euclidian).output("via4.4", "via4.4 : min. m4 enclosure of via4 : 0.19um") +via4.not(m4).output("via4", "via4 : m4 must enclose all via4") +if backend_flow = CU + # rules via4.irdrop.1, via4.irdrop.2, via4.irdrop.3, via4.irdrop.4 not coded because not understandable +end + +# m5 +m5.width(1.6, euclidian).output("m5.1", "m5.1 : min. m5 width : 1.6um") +m5.space(1.6, euclidian).output("m5.2", "m5.2 : min. m5 spacing : 1.6um") +via4.not(m5).output("m5.via4", "m5.via4 : m5 must enclose via4") +m5.enclosing(via4, 0.31, euclidian).output("m5.3", "m4.3 : min. m5 enclosure of via4 : 0.31um") + +# pad +pad.isolated(1.27, euclidian).output("pad.2", "pad.2 : min. pad spacing : 1.27um") + +end #BEOL + +if FEOL +info("FEOL section") + +# mf +mf.not_interacting(mf.edges.without_length(0.8)).output("mf.1", "mf.1 : minimum/maximum width of fuse : 0.8um") +mf.not_interacting(mf.edges.without_length(7.2)).output("mf.2", "mf.2 : minimum/maximum length of fuse : 7.2um") +mf.space(1.96, euclidian).output("mf.3", "mf.3 : min. fuse center spacing : 2.76um") +# fuses need more clarification on fuse_shield, fuse layers ... + +# hvi +hvi.width(0.6, euclidian).output("hvi.1", "hvi.1 : min. hvi width : 0.6um") +hvi.space(0.7, euclidian).output("hvi.2", "hvi.2 : min. hvi spacing, merge if less : 0.7um") +hvi.and(tunm).output("hvi.4", "hvi.4 : hvi must not overlapp tunm") +hvi.and(nwell).separation(nwell, 2.0, euclidian).output("hvnwell.8", "hvnwelli.8 : min. hvnwel spacing to nwell : 2.0") +areaid_hl.not(hvi).output("hvnwel.9", "hvnwell.9 : hvi must overlapp hvnwell") +# rule hvnell.10 not coded +diff.not(psdm.and(diff_rs)).and(hvi).width(0.29, euclidian).output("hvdifftap.14", "hvdifftap.14 : min. diff inside hvi width : 0.29um") +diff.and(psdm.and(diff_rs)).and(hvi).width(0.15, euclidian).output("hvdifftap.14a", "hvdifftap.14a : min. p+diff resistor inside hvi width : 0.15um") +diff.and(hvi).isolated(0.3, euclidian).output("hvdifftap.15a", "hvdifftap.15a : min. diff inside hvi spacing : 0.3um") +diff.and(hvi).and(nsdm).separation(diff.and(hvi).and(psdm), 0.37, euclidian).polygons.without_area(0).output("hvdifftap.15b", "hvdifftap.15b : min. n+diff inside hvi spacing to p+diff inside hvi except abutting: 0.37um") +tap.and(hvi).edges.and(diff).without_length(0.7).output("hvdifftap.16", "hvdifftap.16 : min. tap inside hvi abuttng diff : 0.7um") +hvi.and(nwell).enclosing(diff, 0.33, euclidian).output("hvdifftap.17", "hvdifftap.17 : min. hvnwell enclosure of p+diff : 0.33um") +hvi.and(nwell).separation(diff, 0.43, euclidian).output("hvdifftap.18", "hvdifftap.18 : min. hvnwell spacing to n+diff : 0.43um") +hvi.and(nwell).enclosing(tap, 0.33, euclidian).output("hvdifftap.19", "hvdifftap.19 : min. hvnwell enclosure of n+tap : 0.33um") +hvi.and(nwell).separation(tap, 0.43, euclidian).output("hvdifftap.20", "hvdifftap.20 : min. hvnwell spacing to p+tap : 0.43um") +hvi.and(diff).edges.not(diff.edges).output("hvdifftap.21", "hvdifftap.21 : diff must not straddle hvi") +hvi.and(tap).edges.not(tap.edges).output("hvdifftap.21", "hvdifftap.21 : tap must not straddle hvi") +hvi.enclosing(difftap, 0.18, euclidian).output("hvdifftap.22", "hvdifftap.22 : min. hvi enclosure of diff or tap : 0.18um") +hvi.separation(difftap, 0.18, euclidian).output("hvdifftap.23", "hvdifftap.23 : min. hvi spacing to diff or tap : 0.18um") +hvi.and(diff).not(nwell).separation(nwell, 0.43, euclidian).output("hvdifftap.24", "hvdifftap.24 : min. hv n+diff spacing to nwell : 0.43um") +diff.and(hvi).not(nwell).isolated(1.07, euclidian).polygons.and(tap).output("hvdifftap.25", "hvdifftap.25 : min. n+diff inside hvi spacing accros p+tap : 1.07um") +diff.not(poly).edges.and(gate.and(hvi).edges).space(0.35, euclidian).output("hvpoly.13", "hvpoly.13: min. hvi gate length : 0.5um") +hvi.and(poly).edges.not(poly.edges).output("hvpoly.14", "hvpoly.14 : poly must not straddle hvi") + +# hvntm +hvntm.width(0.7, euclidian).output("hvntm.1", "hvntm.1 : min. hvntm width : 0.7um") +hvntm.space(0.7, euclidian).output("hvntm.2", "hvntm.2 : min. hvntm spacing : 0.7um") +hvntm.enclosing(diff.and(nwell).and(hvi), 0.185, euclidian).output("hvntm.3", "hvntm.3 : min. hvntm enclosure of hv n+diff : 0.185um") +hvntm.separation(diff.not(nwell).not(hvi), 0.185, euclidian).output("hvntm.4", "hvntm.4 : min. hvntm spacing to n+diff : 0.185um") +hvntm.separation(diff.and(nwell).not(hvi), 0.185, euclidian).output("hvntm.5", "hvntm.5 : min. hvntm spacing to p+diff : 0.185um") +hvntm.separation(tap.not(nwell).not(hvi), 0.185, euclidian).polygons.without_area(0).output("hvntm.6a", "hvntm.6a : min. hvntm spacing to p+tap : 0.185um") +hvntm.and(areaid_ce).output("hvntm.9", "hvntm.9 : hvntm must not overlapp areaid.ce") + +# denmos +poly.not_interacting(pwde).interacting(areaid_en).width(1.055, projection).output("denmos.1", "denmos.1 : min. de_nfet gate width : 1.055um") +diff.not_interacting(pwde).enclosing(poly.interacting(areaid_en), 0.28, projection).polygons.without_area(0).output("denmos.2", "denmos.2 : min. de_nfet source ouside poly width : 0.28um") +diff.not_interacting(pwde).and(poly.interacting(areaid_en)).width(0.925, projection).output("denmos.3", "denmos.3 : min. de_nfet source inside poly width : 0.925um") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).width(0.17, euclidian).output("denmos.4", "denmos.4 : min. de_nfet drain width : 0.17um") +nwell.not_interacting(pwde).and(poly.interacting(areaid_en)).width(0.225, projection).polygons.or(nwell.and(poly.interacting(areaid_en)).sized(-0.1125).sized(0.1125)).output("denmos.5", "denmos.5 : min. de_nfet source inside nwell width : 0.225m") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).separation(diff.interacting(poly.interacting(areaid_en)), 1.585, projection).output("denmos.6", "denmos.6 : min. de_nfet source spacing to drain : 1.585um") +nwell.not_interacting(pwde).and(poly.and(diff).interacting(areaid_en)).edges.without_length(5.0, nil).output("denmos.7", "denmos.7 : min. de_nfet channel width : 5.0um") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("denmos.8", "denmos.8 : 90deg. not allowed for de_nfet drain") +nwell.not_interacting(pwde).interacting(areaid_en).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("denmos.9a", "denmos.9a : 90deg. not allowed for de_nfet nwell") +nwell.not_interacting(pwde).interacting(areaid_en).edges.with_angle(45).without_length(0.607..0.609).output("denmos.9a", "denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners") +nwell.not_interacting(pwde).interacting(areaid_en).edges.with_angle(135).without_length(0.607..0.609).output("denmos.9a", "denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(45).without_length(0.7..0.71).output("denmos.9b", "denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners") +diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(135).without_length(0.7..0.71).output("denmos.9b", "denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners") +nwell.not_interacting(pwde).enclosing(diff.interacting(areaid_en).not_interacting(poly), 0.66, euclidian).output("denmos.10", "denmos.10 : min. nwell enclosure of de_nfet drain : 0.66um") +nwell.not_interacting(pwde).interacting(areaid_en).separation(tap.not(nwell), 0.86, euclidian).output("denmos.11", "denmos.11 : min. de_nfet nwell spacing to tap : 0.86um") +nwell.not_interacting(pwde).interacting(areaid_en).isolated(2.4, euclidian).output("denmos.12", "denmos.12 : min. de_nfet nwell : 2.4um") +nsdm.not_interacting(pwde).enclosing(diff.interacting(areaid_en).interacting(poly), 0.13, euclidian).output("denmos.13", "denmos.13 : min. nsdm enclosure of de_nfet source : 0.13um") + +# depmos +poly.interacting(pwde).interacting(areaid_en).width(1.05, projection).output("depmos.1", "depmos.1 : min. de_pfet gate width : 1.05um") +diff.interacting(pwde).enclosing(poly.interacting(areaid_en), 0.28, projection).polygons.without_area(0).output("depmos.2", "depmos.2 : min. de_pfet source ouside poly width : 0.28um") +diff.interacting(pwde).and(poly.interacting(areaid_en)).width(0.92, projection).output("depmos.3", "depmos.3 : min. de_pfet source inside poly width : 0.92um") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).width(0.17, euclidian).output("depmos.4", "depmos.4 : min. de_pfet drain width : 0.17um") +pwde.not(nwell).and(poly.interacting(areaid_en)).width(0.26, projection).polygons.or(pwde.not(nwell).and(poly.interacting(areaid_en)).sized(-0.13).sized(0.13)).output("depmos.5", "depmos.5 : min. de_pfet source inside nwell width : 0.26m") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).separation(diff.interacting(poly.interacting(areaid_en)), 1.19, projection).output("depmos.6", "depmos.6 : min. de_pfet source spacing to drain : 1.19um") +nwell.interacting(pwde).and(poly.and(diff).interacting(areaid_en)).edges.without_length(5.0, nil).output("depmos.7", "depmos.7 : min. de_pfet channel width : 5.0um") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("depmos.8", "depmos.8 : 90deg. not allowed for de_pfet drain") +pwde.not(nwell).interacting(areaid_en).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("depmos.9a", "depmos.9a : 90deg. not allowed for de_pfet pwell") +pwde.not(nwell).interacting(areaid_en).edges.with_angle(45).without_length(0.607..0.609).output("depmos.9a", "depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners") +pwde.not(nwell).interacting(areaid_en).edges.with_angle(135).without_length(0.607..0.609).output("depmos.9a", "depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(45).without_length(0.7..0.71).output("depmos.9b", "depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners") +diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(135).without_length(0.7..0.71).output("depmos.9b", "depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners") +nwell.interacting(pwde).separation(diff.interacting(areaid_en).not_interacting(poly), 0.86, euclidian).output("depmos.10", "depmos.10 : min. pwell enclosure of de_pfet drain : 0.86um") +pwde.not(nwell).interacting(areaid_en).separation(tap.and(nwell), 0.66, euclidian).output("depmos.11", "depmos.11 : min. de_pfet pwell spacing to tap : 0.66um") +psdm.interacting(pwde).enclosing(diff.interacting(areaid_en).interacting(poly), 0.13, euclidian).output("depmos.12", "depmos.12 : min. psdm enclosure of de_pfet source : 0.13um") + +# extd +areaid_en.and(difftap).edges.not(difftap.edges).output("extd.1", "extd.1 : difftap must not straddle areaid.en") +difftap.interacting(areaid_en).not(poly).with_area(0).output("extd.2", "extd.2 : poly must not overlapp entirely difftap in areaid.en") +# rules extd.4, extd.5, extd.6, extd.7 not coded because specific to some cells + +# vhvi +# rules vhvi.vhv.1, vhvi.vhv.2, vhvi.vhv.3, vhvi.vhv.4, vhvi.vhv.5, vhvi.vhv.6 not coded +vhvi.width(0.02, euclidian).output("vhvi.1", "vhvi.1 : min. vhvi width : 0.02um") +vhvi.and(areaid_ce).output("vhvi.2", "vhvi.2 : vhvi must not overlap areaid.ce") +vhvi.and(hvi).output("vhvi.3", "vhvi.3 : vhvi must not overlap hvi") +# rules vhvi.4, vhvi.6 not coded +vhvi.and(diff).edges.not(diff.edges).output("vhvi.5", "vhvi.5 : vhvi must not straddle diff") +vhvi.and(tap).edges.not(tap.edges).output("vhvi.5", "vhvi.5 : vhvi must not straddle tap") +vhvi.and(poly).edges.not(poly.edges).output("vhvi.7", "vhvi.7 : vhvi must not straddle poly") + +nwell.and(vhvi).separation(nwell, 2.5, euclidian).output("hv.nwell.1", "hv.nwell.1 : min. vhvi nwell spacing to nwell : 2.5um") +diff.and(vhvi).space(0.3, euclidian).output("hv.diff.1", "hv.diff.1 : min. vhvi diff spacing : 0.3um") +nwell.interacting(diff.and(vhvi)).separation(diff.not(nwell), 0.43, euclidian).output("hv.diff.2", "hv.diff.2 : min. vhvi nwell spacing n+diff : 0.43um") +diff.and(vhvi).not(nwell).separation(nwell, 0.55, euclidian).output("hv.diff.3a", "hv.diff.3a : min. vhvi n+diff spacing nwell : 0.55um") +# rule hv.diff.3b not coded +poly.and(vhvi).not(diff).separation(diff, 0.3, euclidian).polygons.without_area(0).output("hv.poly.2", "hv.poly.2 : min. vhvi poly spacing to diff : 0.3um") +poly.and(vhvi).not(diff).separation(nwell, 0.55, euclidian).polygons.without_area(0).output("hv.poly.3", "hv.poly.3 : min. vhvi poly spacing to nwell : 0.55um") +nwell.enclosing(poly.and(vhvi).not(diff), 0.3, euclidian).polygons.without_area(0).output("hv.poly.4", "hv.poly.4 : min. nwell enclosure of vhvi poly : 0.3um") +#poly.and(vhvi).enclosing(diff.interacting(areaid_en), 0.16, projection).polygons.without_area(0).output("hv.poly.6", "hv.poly.6 : min. poly enclosure of hvfet gate : 0.16um") +# rule hv.poly.7 not coded + +# uhvi +uhvi.and(diff).edges.not(diff.edges).output("uhvi.1", "uhvi.1 : diff must not straddle uhvi") +uhvi.and(tap).edges.not(tap.edges).output("uhvi.1", "uhvi.1 : tap must not straddle uhvi") +uhvi.and(poly).edges.not(poly.edges).output("uhvi.2", "uhvi.2 : poly must not straddle uhvi") +pwbm.not(uhvi).output("uhvi.3", "uhvi.3 : uhvi must not enclose pwbm") +uhvi.and(dnwell).edges.not(dnwell.edges).output("uhvi.4", "uhvi.4 : dnwell must not straddle uhvi") +areaid_en20.not(uhvi).output("uhvi.5", "uhvi.5 : uhvi must not enclose areaid.en20") +#dnwell.not(uhvi).output("uhvi.6", "uhvi.6 : uhvi must not enclose dnwell") +natfet.not(uhvi).output("uhvi.7", "uhvi.7 : uhvi must not enclose natfet") + +# pwell_res +pwell_rs.width(2.65).output("pwres.2", "pwres.2 : min. pwell resistor width : 2.65um") +pwell_rs.sized(-2.65).sized(2.65).output("pwres.2", "pwres.2 : max. pwell resistor width : 2.65um") +pwell_rs.interacting(pwell_rs.edges.with_length(2.651,26.499)).output("pwres.3", "pwres.3 : min. pwell resistor length : 26.5um") +pwell_rs.interacting(pwell_rs.edges.with_length(265.0, nil)).output("pwres.4", "pwres.4 : max. pwell resistor length : 265um") +tap.interacting(pwell_rs).separation(nwell, 0.22, euclidian).output("pwres.5", "pwres.5 : min. pwell resistor tap spacing to nwell : 0.22um") +tap.interacting(pwell_rs).and(tap.sized(0.22).and(nwell)).output("pwres.5", "pwres.5 : max. pwell resistor tap spacing to nwell : 0.22um") +tap.interacting(pwell_rs).width(0.53).output("pwres.6", "pwres.6 : min. width of tap inside pwell resistor : 0.53um") +tap.interacting(pwell_rs).sized(-0.265).sized(0.265).output("pwres.6", "pwres.6 : max. width of tap inside pwell resistor : 0.53um") +# rules pwres.7a, pwres.7b not coded +pwell_rs.and(diff).output("pwres.8", "pwres.8 : diff not allowed inside pwell resistor") +pwell_rs.and(poly).output("pwres.8", "pwres.8 : poly not allowed inside pwell resistor") +# rules pwres.9, pwres.10 not coded + +# rf_diode +areaid_re.with_angle(0 .. 90).output("rfdiode.1", "rfdiode.1 : non 90 degree angle areaid.re") +areaid_re.not(nwell).or(nwell.interacting(areaid_re).not(areaid_re)).output("rfdiode.2", "rfdiode.2 : areaid.re must coincide rf nwell diode") +# rule rfdiode.3 not coded + +end #FEOL + +if OFFGRID +info("OFFGRID-ANGLES section") + +dnwell.ongrid(0.005).output("dnwell_OFFGRID", "x.1b : OFFGRID vertex on dnwell") +dnwell.with_angle(0 .. 45).output("dnwell_angle", "x.3a : non 45 degree angle dnwell") +nwell.ongrid(0.005).output("nwell_OFFGRID", "x.1b : OFFGRID vertex on nwell") +nwell.with_angle(0 .. 45).output("nwell_angle", "x.3a : non 45 degree angle nwell") +pwbm.ongrid(0.005).output("pwbm_OFFGRID", "x.1b : OFFGRID vertex on pwbm") +pwbm.with_angle(0 .. 45).output("pwbm_angle", "x.3a : non 45 degree angle pwbm") +pwde.ongrid(0.005).output("pwde_OFFGRID", "x.1b : OFFGRID vertex on pwde") +pwde.with_angle(0 .. 45).output("pwde_angle", "x.3a : non 45 degree angle pwde") +hvtp.ongrid(0.005).output("hvtp_OFFGRID", "x.1b : OFFGRID vertex on hvtp") +hvtp.with_angle(0 .. 45).output("hvtp_angle", "x.3a : non 45 degree angle hvtp") +hvtr.ongrid(0.005).output("hvtr_OFFGRID", "x.1b : OFFGRID vertex on hvtr") +hvtr.with_angle(0 .. 45).output("hvtr_angle", "x.3a : non 45 degree angle hvtr") +lvtn.ongrid(0.005).output("lvtn_OFFGRID", "x.1b : OFFGRID vertex on lvtn") +lvtn.with_angle(0 .. 45).output("lvtn_angle", "x.3a : non 45 degree angle lvtn") +ncm.ongrid(0.005).output("ncm_OFFGRID", "x.1b : OFFGRID vertex on ncm") +ncm.with_angle(0 .. 45).output("ncm_angle", "x.3a : non 45 degree angle ncm") +diff.ongrid(0.005).output("diff_OFFGRID", "x.1b : OFFGRID vertex on diff") +tap.ongrid(0.005).output("tap_OFFGRID", "x.1b : OFFGRID vertex on tap") +diff.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("diff_angle", "x.2 : non 90 degree angle diff") +diff.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("diff_angle", "x.2c : non 45 degree angle diff") +tap.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("tap_angle", "x.2 : non 90 degree angle tap") +tap.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("tap_angle", "x.2c : non 45 degree angle tap") +tunm.ongrid(0.005).output("tunm_OFFGRID", "x.1b : OFFGRID vertex on tunm") +tunm.with_angle(0 .. 45).output("tunm_angle", "x.3a : non 45 degree angle tunm") +poly.ongrid(0.005).output("poly_OFFGRID", "x.1b : OFFGRID vertex on poly") +poly.with_angle(0 .. 90).output("poly_angle", "x.2 : non 90 degree angle poly") +rpm.ongrid(0.005).output("rpm_OFFGRID", "x.1b : OFFGRID vertex on rpm") +rpm.with_angle(0 .. 45).output("rpm_angle", "x.3a : non 45 degree angle rpm") +npc.ongrid(0.005).output("npc_OFFGRID", "x.1b : OFFGRID vertex on npc") +npc.with_angle(0 .. 45).output("npc_angle", "x.3a : non 45 degree angle npc") +nsdm.ongrid(0.005).output("nsdm_OFFGRID", "x.1b : OFFGRID vertex on nsdm") +nsdm.with_angle(0 .. 45).output("nsdm_angle", "x.3a : non 45 degree angle nsdm") +psdm.ongrid(0.005).output("psdm_OFFGRID", "x.1b : OFFGRID vertex on psdm") +psdm.with_angle(0 .. 45).output("psdm_angle", "x.3a : non 45 degree angle psdm") +licon.ongrid(0.005).output("licon_OFFGRID", "x.1b : OFFGRID vertex on licon") +licon.with_angle(0 .. 90).output("licon_angle", "x.2 : non 90 degree angle licon") +li.ongrid(0.005).output("li_OFFGRID", "x.1b : OFFGRID vertex on li") +li.with_angle(0 .. 45).output("li_angle", "x.3a : non 45 degree angle li") +mcon.ongrid(0.005).output("ct_OFFGRID", "x.1b : OFFGRID vertex on mcon") +mcon.with_angle(0 .. 90).output("ct_angle", "x.2 : non 90 degree angle mcon") +vpp.ongrid(0.005).output("vpp_OFFGRID", "x.1b : OFFGRID vertex on vpp") +vpp.with_angle(0 .. 45).output("vpp_angle", "x.3a : non 45 degree angle vpp") +m1.ongrid(0.005).output("m1_OFFGRID", "x.1b : OFFGRID vertex on m1") +m1.with_angle(0 .. 45).output("m1_angle", "x.3a : non 45 degree angle m1") +via.ongrid(0.005).output("via_OFFGRID", "x.1b : OFFGRID vertex on via") +via.with_angle(0 .. 90).output("via_angle", "x.2 : non 90 degree angle via") +m2.ongrid(0.005).output("m2_OFFGRID", "x.1b : OFFGRID vertex on m2") +m2.with_angle(0 .. 45).output("m2_angle", "x.3a : non 45 degree angle m2") +via2.ongrid(0.005).output("via2_OFFGRID", "x.1b : OFFGRID vertex on via2") +via2.with_angle(0 .. 90).output("via2_angle", "x.2 : non 90 degree angle via2") +m3.ongrid(0.005).output("m3_OFFGRID", "x.1b : OFFGRID vertex on m3") +m3.with_angle(0 .. 45).output("m3_angle", "x.3a : non 45 degree angle m3") +via3.ongrid(0.005).output("via3_OFFGRID", "x.1b : OFFGRID vertex on via3") +via3.with_angle(0 .. 90).output("via3_angle", "x.2 : non 90 degree angle via3") +nsm.ongrid(0.005).output("nsm_OFFGRID", "x.1b : OFFGRID vertex on nsm") +nsm.with_angle(0 .. 45).output("nsm_angle", "x.3a : non 45 degree angle nsm") +m4.ongrid(0.005).output("m4_OFFGRID", "x.1b : OFFGRID vertex on m4") +m4.with_angle(0 .. 45).output("m4_angle", "x.3a : non 45 degree angle m4") +via4.ongrid(0.005).output("via4_OFFGRID", "x.1b : OFFGRID vertex on via4") +via4.with_angle(0 .. 90).output("via4_angle", "x.2 : non 90 degree angle via4") +m5.ongrid(0.005).output("m5_OFFGRID", "x.1b : OFFGRID vertex on m5") +m5.with_angle(0 .. 45).output("m5_angle", "x.3a : non 45 degree angle m5") +pad.ongrid(0.005).output("pad_OFFGRID", "x.1b : OFFGRID vertex on pad") +pad.with_angle(0 .. 45).output("pad_angle", "x.3a : non 45 degree angle pad") +mf.ongrid(0.005).output("mf_OFFGRID", "x.1b : OFFGRID vertex on mf") +mf.with_angle(0 .. 90).output("mf_angle", "x.2 : non 90 degree angle mf") +hvi.ongrid(0.005).output("hvi_OFFGRID", "x.1b : OFFGRID vertex on hvi") +hvi.with_angle(0 .. 45).output("hvi_angle", "x.3a : non 45 degree angle hvi") +hvntm.ongrid(0.005).output("hvntm_OFFGRID", "x.1b : OFFGRID vertex on hvntm") +hvntm.with_angle(0 .. 45).output("hvntm_angle", "x.3a : non 45 degree angle hvntm") +vhvi.ongrid(0.005).output("vhvi_OFFGRID", "x.1b : OFFGRID vertex on vhvi") +vhvi.with_angle(0 .. 45).output("vhvi_angle", "x.3a : non 45 degree angle vhvi") +uhvi.ongrid(0.005).output("uhvi_OFFGRID", "x.1b : OFFGRID vertex on uhvi") +uhvi.with_angle(0 .. 45).output("uhvi_angle", "x.3a : non 45 degree angle uhvi") +pwell_rs.ongrid(0.005).output("pwell_rs_OFFGRID", "x.1b : OFFGRID vertex on pwell_rs") +pwell_rs.with_angle(0 .. 45).output("pwell_rs_angle", "x.3a : non 45 degree angle pwell_rs") +areaid_re.ongrid(0.005).output("areaid_re_OFFGRID", "x.1b : OFFGRID vertex on areaid.re") + +end #OFFGRID + +# time spent for the DRC +time = Time.now +hours = ((time - tstart)/3600).to_i +minutes = ((time - tstart)/60 - hours * 60).to_i +seconds = ((time - tstart) - (minutes * 60 + hours * 3600)).to_i +$stdout.write "DRC finished at : #{time.hour}:#{time.min}:#{time.sec} - DRC duration = #{hours} hrs. #{minutes} min. #{seconds} sec.\n" + diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/sky130A.lydrc b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/sky130A.lydrc new file mode 100644 index 000000000..67ec2a5cf --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/sky130A.lydrc @@ -0,0 +1,39 @@ + + + DRC + + drc + + + + false + false + 0 + + true + sky130a + tools_menu.sky130a>lvs("Sky130A").end + dsl + drc-dsl-xml + +# Take input from layout window +# $input = nil + +# Interactive report +# $report = "" + +# Enable all parts +$feol = "true" +$beol = "true" +$offgrid = "true" + +# Disabled for now +$seal = "false" +$floating_met = "false" + +# Default threads +$thr = nil + +# %include ./core/sky130A_mr.drc + + diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/sky130A.lyp b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/sky130A.lyp new file mode 100755 index 000000000..cf7ec0b5d --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/sky130A.lyp @@ -0,0 +1,8241 @@ + + + + #ccccd9 + #ccccd9 + 0 + 0 + C7 + C0 + true + true + false + 1 + false + false + 0 + prBoundary.boundary - 235/4 + 235/4@1 + + + #00ffff + #00ffff + 0 + 0 + C21 + C0 + true + true + false + 1 + false + false + 0 + pwell.drawing - 64/44 + 64/44@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + C39 + C0 + true + true + false + 1 + false + false + 0 + pwell.pin - 122/16 + 122/16@1 + + + #9900e6 + #9900e6 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + pwell.label - 64/59 + 64/59@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + pwell.res - 64/13 + 64/13@1 + + + #ffbff2 + #ffbff2 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + pwell.cut - 64/14 + 64/14@1 + + + #ffffff + #96c8ff + 0 + 0 + C39 + C0 + true + true + false + 1 + false + false + 0 + pwelliso.pin - 44/16 + 44/16@1 + + + #9900e6 + #9900e6 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + pwelliso.label - 44/5 + 44/5@1 + + + #00cc66 + #00cc66 + 0 + 0 + C21 + C0 + true + true + false + 1 + false + false + 0 + nwell.drawing - 64/20 + 64/20@1 + + + #ff00ff + #ff00ff + 0 + 0 + C2 + C0 + true + true + false + 1 + false + false + 0 + nwell.net - 84/23 + 84/23@1 + + + #268c6b + #268c6b + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + nwell.pin - 64/16 + 64/16@1 + + + #333399 + #333399 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + nwell.label - 64/5 + 64/5@1 + + + #c8ffc8 + #c8ffc8 + 0 + 0 + C48 + C0 + true + true + false + 1 + false + false + 0 + dnwell.drawing - 64/18 + 64/18@1 + + + #00ffff + #00ffff + 0 + 0 + C6 + C0 + true + true + false + 1 + false + false + 0 + vhvi.drawing - 74/21 + 74/21@1 + + + #00ff00 + #00ff00 + 0 + 0 + C35 + C0 + true + true + false + 1 + false + false + 0 + diff.drawing - 65/20 + 65/20@1 + + + #00ff00 + #00ff00 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + diff.res - 65/13 + 65/13@1 + + + #00ff00 + #00ff00 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + diff.cut - 65/14 + 65/14@1 + + + #268c6b + #268c6b + 0 + 0 + C37 + C0 + false + true + false + 1 + false + false + 0 + diff.pin - 65/16 + 65/16@1 + + + #c8ffc8 + #c8ffc8 + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + diff.label - 65/6 + 65/6@1 + + + #00ff00 + #00ff00 + 0 + 0 + C5 + C0 + false + true + false + 1 + false + false + 0 + diff.net - 65/23 + 65/23@1 + + + #00ff00 + #00ff00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + false + 0 + diff.boundary - 65/4 + 65/4@1 + + + #9900e6 + #9900e6 + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + diff.hv - 65/8 + 65/8@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C35 + C0 + true + true + false + 1 + false + false + 0 + tap.drawing - 65/44 + 65/44@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + tap.pin - 65/48 + 65/48@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C5 + C0 + false + true + false + 1 + false + false + 0 + tap.net - 65/41 + 65/41@1 + + + #d9cc00 + #d9cc00 + 0 + 0 + C0 + C0 + false + true + false + 1 + false + false + 0 + tap.boundary - 65/60 + 65/60@1 + + + #fff464 + #fff464 + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + tap.label - 65/5 + 65/5@1 + + + #9900e6 + #9900e6 + 0 + 0 + C23 + C0 + true + true + false + 1 + false + false + 0 + psdm.drawing - 94/20 + 94/20@1 + + + #e61f0d + #e61f0d + 0 + 0 + C22 + C0 + true + true + false + 1 + false + false + 0 + nsdm.drawing - 93/44 + 93/44@1 + + + #ff0000 + #ff0000 + 0 + 0 + C42 + C0 + true + true + false + 1 + false + false + 0 + poly.drawing - 66/20 + 66/20@1 + + + #ff8000 + #ff8000 + 0 + 0 + C39 + C0 + true + true + false + 1 + false + false + 0 + poly.pin - 66/16 + 66/16@1 + + + #ff0000 + #ff0000 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + poly.res - 66/13 + 66/13@1 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.cut - 66/14 + 66/14@1 + + + #ff0000 + #ff0000 + 0 + 0 + I1 + C0 + true + true + false + 1 + false + false + 0 + poly.gate - 66/9 + 66/9@1 + + + #ffafaf + #ffafaf + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.label - 66/5 + 66/5@1 + + + #ff0000 + #ff0000 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + poly.boundary - 66/4 + 66/4@1 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.probe - 66/25 + 66/25@1 + + + #ff0000 + #ff0000 + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + poly.short - 66/15 + 66/15@1 + + + #ff0000 + #ff0000 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + poly.net - 66/23 + 66/23@1 + + + #ff0000 + #ff0000 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + poly.model - 66/83 + 66/83@1 + + + #00cc66 + #00cc66 + 0 + 0 + C51 + C0 + true + true + false + 1 + false + false + 0 + ldntm.drawing - 11/44 + 11/44@1 + + + #96c8ff + #ffffff + 0 + 0 + C15 + C0 + true + true + false + 1 + false + false + 0 + lvtn.drawing - 125/44 + 125/44@1 + + + #ff8000 + #ffffff + 0 + 0 + C14 + C0 + true + true + false + 1 + false + false + 0 + hvtp.drawing - 78/44 + 78/44@1 + + + #ff0000 + #e61f0d + 0 + 0 + C14 + C0 + false + true + false + 1 + false + false + 0 + hvtr.drawing - 18/20 + 18/20@1 + + + #9900e6 + #9900e6 + 0 + 0 + C42 + C0 + true + true + false + 1 + false + false + 0 + tunm.drawing - 80/20 + 80/20@1 + + + #ffffcc + #ffffcc + 0 + 0 + C24 + C0 + true + true + false + 1 + false + false + 0 + licon1.drawing - 66/44 + 66/44@1 + + + #ffffcc + #ffffcc + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + licon1.boundary - 66/60 + 66/60@1 + + + #ffe6bf + #c8ffff + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + licon1.pin - 66/58 + 66/58@1 + + + #ffffcc + #ffffcc + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + licon1.net - 66/41 + 66/41@1 + + + #bf4026 + #bf4026 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + npc.drawing - 95/20 + 95/20@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + li1.drawing - 67/20 + 67/20@1 + + + #bf4026 + #bf4026 + 0 + 0 + C47 + C0 + true + true + false + 1 + false + false + 0 + li1.pin - 67/16 + 67/16@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + I1 + C0 + false + true + false + 1 + false + false + 0 + li1.res - 67/13 + 67/13@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + li1.cut - 67/14 + 67/14@1 + + + #bf4026 + #bf4026 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + li1.label - 67/5 + 67/5@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C54 + C0 + true + true + false + 1 + false + false + 0 + li1.net - 67/23 + 67/23@1 + + + #d9e6ff + #d9e6ff + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + li1.boundary - 67/4 + 67/4@1 + + + #bf4026 + #bf4026 + 0 + 0 + C54 + C0 + true + true + false + 1 + false + false + 0 + li1.blockage - 67/10 + 67/10@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + li1.short - 67/15 + 67/15@1 + + + #ffe6bf + #ffe6bf + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + li1.probe - 67/25 + 67/25@1 + + + #ccccd9 + #ccccd9 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + mcon.drawing - 67/44 + 67/44@1 + + + #ccccd9 + #ccccd9 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + mcon.boundary - 67/60 + 67/60@1 + + + #ffffcc + #d9e6ff + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + mcon.pin - 67/48 + 67/48@1 + + + #ccccd9 + #ccccd9 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + mcon.net - 67/41 + 67/41@1 + + + #0000ff + #0000ff + 0 + 0 + C7 + C0 + true + true + false + 1 + false + false + 0 + met1.drawing - 68/20 + 68/20@1 + + + #0000ff + #0000ff + 0 + 0 + I1 + C0 + false + true + false + 1 + false + false + 0 + met1.res - 68/13 + 68/13@1 + + + #0000ff + #0000ff + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + met1.cut - 68/14 + 68/14@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C6 + C0 + true + true + false + 1 + false + false + 0 + met1.pin - 68/16 + 68/16@1 + + + #96c8ff + #96c8ff + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + met1.label - 68/5 + 68/5@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + met1.net - 68/23 + 68/23@1 + + + #0000ff + #0000ff + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + met1.boundary - 68/4 + 68/4@1 + + + #0000ff + #0000ff + 0 + 0 + C54 + C0 + true + true + false + 1 + false + false + 0 + met1.blockage - 68/10 + 68/10@1 + + + #0000ff + #0000ff + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + met1.short - 68/15 + 68/15@1 + + + #0000ff + #0000ff + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + met1.probe - 68/25 + 68/25@1 + + + #0000ff + #0000ff + 0 + 0 + C26 + C0 + false + true + false + 1 + false + false + 0 + met1.option1 - 68/32 + 68/32@1 + + + #0000ff + #0000ff + 0 + 0 + C27 + C0 + false + true + false + 1 + false + false + 0 + met1.option2 - 68/33 + 68/33@1 + + + #0000ff + #0000ff + 0 + 0 + C28 + C0 + false + true + false + 1 + false + false + 0 + met1.option3 - 68/34 + 68/34@1 + + + #0000ff + #0000ff + 0 + 0 + C29 + C0 + false + true + false + 1 + false + false + 0 + met1.option4 - 68/35 + 68/35@1 + + + #0000ff + #0000ff + 0 + 0 + C30 + C0 + false + true + false + 1 + false + false + 0 + met1.option5 - 68/36 + 68/36@1 + + + #0000ff + #0000ff + 0 + 0 + C31 + C0 + false + true + false + 1 + false + false + 0 + met1.option6 - 68/37 + 68/37@1 + + + #0000ff + #0000ff + 0 + 0 + C32 + C0 + false + true + false + 1 + false + false + 0 + met1.option7 - 68/38 + 68/38@1 + + + #0000ff + #0000ff + 0 + 0 + C33 + C0 + false + true + false + 1 + false + false + 0 + met1.option8 - 68/39 + 68/39@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + via.drawing - 68/44 + 68/44@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + via.boundary - 68/60 + 68/60@1 + + + #5e00e6 + #5e00e6 + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + via.net - 68/41 + 68/41@1 + + + #ae7dff + #ae7dff + 0 + 0 + C6 + C0 + false + true + false + 1 + false + false + 0 + via.pin - 68/58 + 68/58@1 + + + #ff00ff + #ff00ff + 0 + 0 + C38 + C0 + true + true + false + 1 + false + false + 0 + met2.drawing - 69/20 + 69/20@1 + + + #ff00ff + #ff00ff + 0 + 0 + I1 + C0 + false + true + false + 1 + false + false + 0 + met2.res - 69/13 + 69/13@1 + + + #ff00ff + #ff00ff + 0 + 0 + C1 + C0 + false + true + false + 1 + false + false + 0 + met2.cut - 69/14 + 69/14@1 + + + #ff00ff + #ff00ff + 0 + 0 + C46 + C0 + true + true + false + 1 + false + false + 0 + met2.pin - 69/16 + 69/16@1 + + + #ffc8ff + #ffc8ff + 0 + 0 + C1 + C0 + true + true + false + 1 + false + false + 0 + met2.label - 69/5 + 69/5@1 + + + #ff00ff + #ff00ff + 0 + 0 + C5 + C0 + true + true + false + 1 + false + false + 0 + met2.net - 69/23 + 69/23@1 + + + #ff00ff + #ff00ff + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + met2.boundary - 69/4 + 69/4@1 + + + #ff00ff + #ff00ff + 0 + 0 + C54 + C0 + true + true + false + 1 + false + false + 0 + met2.blockage - 69/10 + 69/10@1 + + + #ff00ff + #ff00ff + 0 + 0 + C37 + C0 + true + true + false + 1 + false + false + 0 + met2.short - 69/15 + 69/15@1 + + + #ff00ff + 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38/21 + 38/21@1 + + + #fff5e6 + #fff5e6 + 0 + 0 + C11 + C0 + false + true + false + 1 + false + false + 0 + chvntm.maskDrop - 38/22 + 38/22@1 + + + #00cc66 + #00cc66 + 0 + 0 + C21 + C0 + false + true + false + 1 + false + false + 0 + cldntm.drawing - 11/20 + 11/20@1 + + + #00cc66 + #00cc66 + 0 + 0 + C13 + C0 + true + true + false + 1 + false + false + 0 + cldntm.mask - 11/0 + 11/0@1 + + + #ff8000 + #ff8000 + 0 + 0 + C0 + C0 + true + true + false + 1 + false + false + 0 + clvom.drawing - 45/20 + 45/20@1 + + + #268c6b + #268c6b + 0 + 0 + C17 + C0 + true + true + false + 1 + false + false + 0 + clvom.mask - 46/0 + 46/0@1 + + + #268c6b + #268c6b + 0 + 0 + C14 + C0 + false + true + false + 1 + false + false + 0 + clvom.maskAdd - 45/21 + 45/21@1 + + + #8c8ca6 + #8c8ca6 + 0 + 0 + C3 + C0 + false + true + false + 1 + false + false + 0 + clvom.maskDrop - 45/22 + 45/22@1 + + + #ff8000 + #ff8000 + 0 + 0 + C21 + C0 + false + true + false + 1 + false + false + 0 + cp1m.drawing - 33/44 + 33/44@1 + + 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................ + ................ + ...*............ + ..*.*........... + .*...*.......... + *.....*......... + .*...*.......... + ..*.*........... + ...*............ + + 54 + sparsediam + + + + .......*.......* + ......*......... + .....*.......... + ................ + ................ + ................ + .*.............. + *............... + .......*.......* + ..............*. + .............*.. + ................ + ................ + ................ + .........*...... + ........*....... + + 55 + rain + + + *** + 1 + solid + + + ****.. + 2 + dashed + + + *.. + 3 + dots + + + ***..*.. + 4 + dashDot + + + **.. + 5 + shortDash + + + ****..**.. + 6 + doubleDash + + + *... + 7 + hidden + + + *** + 8 + thickLine + + diff --git a/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/sky130A.lyt b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/sky130A.lyt new file mode 100755 index 000000000..9a48d2c10 --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/libs.tech/klayout/sky130A.lyt @@ -0,0 +1,200 @@ + + + sky130A_el + sky130A Elements + + 0.001 + + sky130A.lyp + true + + + 1 + true + true + + + true + layer_map('66/15 : PY_SHORT';'72/15 : M5_SHORT';'81/14 : LDID';'122/16 : PWELL_PIN';'64/5 : NWELLLABEL';'64/16 : NWELLPT';'64/59 : PWELLLABEL';'64/20 : NWELL';'64/18 : DNWELL';'65/20 : DIFF';'65/44 : TAP';'125/44 : LVTN';'78/44 : HVTP';'75/20 : HVI';'80/20 : TUNM';'66/20 : POLY';'95/20 : NPC';'94/20 : PSDM';'93/44 : NSDM';'66/44 : LICON1';'67/20 : LI1';'67/16 : LI1T';'67/5 : LI1P';'67/44 : MCON';'68/20 : MET1';'68/16 : MET1T';'68/5 : MET1P';'68/44 : VIA1';'69/20 : MET2';'69/16 : MET2T';'69/5 : MET2P';'69/44 : VIA2';'70/20 : MET3';'70/16 : MET3T';'70/5 : MET3P';'70/44 : VIA3';'71/20 : MET4';'71/16 : MET4T';'71/5 : MET4P';'71/44 : VIA4';'72/20 : MET5';'72/16 : MET5T';'72/5 : MET5P';'76/20 : PAD';'76/16 : PADT';'76/5 : PADP';'81/4 : BOUND';'83/44 : TEXT';'18/20 : HVTR';'92/44 : NCM';'86/20 : RPM';'61/20 : NSM';'74/20 : RDL';'74/21 : VHVI';'11/44 : LDNTM';'125/20 : HVNTM';'85/44 : PMM';'82/44 : PNP';'82/64 : CAP';'82/24 : IND';'64/13 : PWRES';'66/13 : POLYRES';'65/13 : DIFFRES';'81/23 : DIODE') + true + true + + + true + layer_map('met1 : met1.drawing (68/20)';'met1.LABEL : met1.label (68/5)';'met1.PIN : met1.pin (68/16)';'via : via.drawing (68/44)';'met2 : met2.drawing (69/20)';'met2.LABEL : met2.label (69/5)';'met2.PIN : met2.pin (69/16)';'via2 : via2.drawing (69/44)';'met3 : met3.drawing (70/20)';'met3.LABEL : met3.label (70/5)';'met3.PIN : met3.pin (70/16)';'via3 : via3.drawing (70/44)';'met4 : met4.drawing (71/20)';'met4.LABEL : met4.label (71/5)';'met4.PIN : met4.pin (71/16)';'via4 : via4.drawing (71/44)';'met5 : met5.drawing (72/20)';'met5.LABEL : met5.label (72/5)';'met5.PIN : met5.pin (72/16)') + 0.001 + true + #1 + true + #1 + false + #1 + true + OUTLINE + true + PLACEMENT_BLK + true + REGIONS + true + + 0 + true + .PIN + 2 + true + .PIN + 2 + true + .FILL + 5 + true + .OBS + 3 + true + .BLK + 4 + true + .LABEL + 1 + true + .LABEL + 1 + true + + 0 + true + + 0 + VIA_ + true + default + false + false + + + + false + true + true + 64 + 0 + 1 + 0 + DATA + 0 + 0 + BORDER + layer_map() + true + + + 0.001 + 1 + 100 + 100 + 0 + 0 + 0 + false + false + false + true + layer_map() + + + 0 + 0.001 + layer_map() + true + false + + + 1 + 0.001 + layer_map() + true + false + true + + + + + + GDS2 + + true + false + false + false + false + false + 8000 + 32000 + LIB + + + 2 + false + false + 1 + * + false + + + 0 + + + false + false + + + 0 + + true + + + + + + + MET4,VIA4,MET5 + MET3,VIA3,MET4 + MET2,VIA2,MET3 + MET1,VIA1,MET2 + LI,MCON,MET1 + POLY,LICON,LI + POLY='66/20' + LICON='66/44' + LI='67/20' + MCON='67/44' + MET1='68/20' + VIA1='68/44' + MET2='69/20' + VIA2='69/44' + MET3='70/20' + VIA3='70/44' + MET4='71/20' + VIA4='71/44' + META5='72/20' + + MET4,VIA4,MET5 + MET3,VIA3,MET4 + MET2,VIA2,MET3 + MET1,VIA1,MET2 + LI,MCON,MET1 + POLY,LICON,LI + POLY='66/20' + LICON='66/44' + LI='67/20' + MCON='67/44' + MET1='68/20' + VIA1='68/44' + MET2='69/20' + VIA2='69/44' + MET3='70/20' + VIA3='70/44' + MET4='71/20' + VIA4='71/44' + META5='72/20' + + diff --git a/pdks/symbolic/vsclib/sky130_vsc/meson.build b/pdks/symbolic/vsclib/sky130_vsc/meson.build new file mode 100644 index 000000000..216c85904 --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/meson.build @@ -0,0 +1,27 @@ + +project( + 'pdk_sky130_vsc', + version: '0.1.0', + meson_version: '>= 1.2.0', + default_options: ['warning_level=3'] +) + +python = import('python') +py = python.find_installation('python3') +py_deps = py.dependency() + +pdks_dir = py.get_install_dir() / 'pdks' / 'sky130_vsc' + +find_py = 'find libs.tech/coriolis -type f -name "*.py"' +res = run_command('sh', '-c', find_py, check:true) +py_files = res.stdout().strip().split('\n') + +find_data = 'find libs.tech/coriolis -type f ! -name "*.py"' +res = run_command('sh', '-c', find_data, check:true) +data_files = res.stdout().strip().split('\n') + +py.install_sources( files(py_files) , subdir: 'pdks/sky130_vsc' ) +py.install_sources( files(data_files) , subdir: 'pdks/sky130_vsc' ) + +install_subdir( 'libs.tech/klayout' , install_dir: pdks_dir ) + diff --git a/pdks/symbolic/vsclib/sky130_vsc/pyproject.toml b/pdks/symbolic/vsclib/sky130_vsc/pyproject.toml new file mode 100644 index 000000000..7fc220a80 --- /dev/null +++ b/pdks/symbolic/vsclib/sky130_vsc/pyproject.toml @@ -0,0 +1,25 @@ +[project] +name = "pdk_sky130_vsc" +version = "0.1.0" +description = "Sky130 vsc PDK for Coriolis EDA" +authors = [ { name = "Coriolis EDA Contributers" } ] +requires-python = ">= 3.8" + +[build-system] +requires = [ + "meson", + "meson-python", + "ninja", + "setuptools", + "cibuildwheel", + "build", + "pdm-backend" +] +build-backend = "mesonpy" + +[tool.meson] +build-dir = "build" + +[tool.cibuildwheel] +build = "cp310-*" +skip = ["cp36-*", "cp37-*", "pp*"] diff --git a/pdm.lock b/pdm.lock index 0207c95bf..4fdea14f4 100644 --- a/pdm.lock +++ b/pdm.lock @@ -4,8 +4,11 @@ [metadata] groups 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"sha256:9c998a5d7606ca835065cdabc013ae6c66eb9ea76a00a1e3bc6e0cfe2b4f71f4"}, +] + [[package]] name = "pypdf" version = "3.17.1" requires_python = ">=3.6" summary = "A pure-python PDF library capable of splitting, merging, cropping, and transforming PDF files" dependencies = [ + "dataclasses; python_version < \"3.7\"", "typing-extensions>=3.7.4.3; python_version < \"3.10\"", ] files = [ @@ -902,6 +956,7 @@ summary = "pytest: simple powerful testing with Python" dependencies = [ "colorama; sys_platform == \"win32\"", "exceptiongroup>=1.0.0rc8; python_version < \"3.11\"", + "importlib-metadata>=0.12; python_version < \"3.8\"", "iniconfig", "packaging", "pluggy<2.0,>=0.12", diff --git a/pyproject.toml b/pyproject.toml index 5b23c051f..9bd0641f2 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,5 +1,5 @@ [project] -name = "coriolis-eda" +name = "coriolis_eda" dynamic = ["version"] description = "Place and Route for semiconductors" authors = [ { name = "Coriolis EDA Contributers" } ] @@ -40,6 +40,7 @@ include = [ "unicorn", "unittests", ] +dependencies = ["ninja>=1.11.1.2", "doit>=0.36.0"] [build-system] requires = ["setuptools", "pdm-backend", "meson @ git+https://github.com/robtaylor/meson@homebrew-fixes", "ninja", "meson-python == 0.13.2", "cmake", "dunamai"] build-backend = "mesonpy" @@ -64,6 +65,17 @@ before-all = ''' wget http://lemon.cs.elte.hu/pub/sources/lemon-1.3.1.tar.gz; tar -xzf lemon-1.3.1.tar.gz; cd lemon-1.3.1; mkdir build; cd build; cmake ..; make install; cd ../.. ''' +[tool.cibuildwheel.macos] +build = "cp310-*" +build-frontend = "build" +skip = ["cp36-*", "cp37-*", "cp38-*", "cp39-*", "pp*"] +before-all = ''' + brew install ccache doxygen qt@5 qwt-qt5 rapidjson boost eigen pkg-config; \ + brew install --cask mactex; \ + brew install automake libtool libx11 openmotif; \ + brew install --cask xquartz +''' + [tool.pdm.version] source = "scm" getter = "_build_utils.version"